From 4b2913a89869400a25d749280f309f681994b0a8 Mon Sep 17 00:00:00 2001 From: WillianChan Date: Thu, 2 Sep 2021 17:47:44 +0800 Subject: [modify][components][utilities]add qemu-a9 section information for var export and fix some problems. Signed-off-by: WillianChan --- bsp/qemu-vexpress-a9/link.lds | 5 +++++ 1 file changed, 5 insertions(+) (limited to 'bsp') diff --git a/bsp/qemu-vexpress-a9/link.lds b/bsp/qemu-vexpress-a9/link.lds index 797cd7e3ef..8e4f65b454 100644 --- a/bsp/qemu-vexpress-a9/link.lds +++ b/bsp/qemu-vexpress-a9/link.lds @@ -26,7 +26,12 @@ SECTIONS __vsymtab_start = .; KEEP(*(VSymTab)) __vsymtab_end = .; + + /* section information for var export */ . = ALIGN(4); + __ve_table_start = .; + KEEP(*(SORT(*.VarExpTab.*))) + __ve_table_end = .; /* section information for modules */ . = ALIGN(4); -- cgit v1.3.1 From 28b7723256c138a99511a44a59825cb62d43d52b Mon Sep 17 00:00:00 2001 From: liuhy Date: Fri, 10 Sep 2021 17:58:56 +0800 Subject: delete essemi bsp es8p508x (libraries) --- bsp/essemi/es8p508x/libraries/CMSIS/ES8P508x.h | 3117 -------------------- bsp/essemi/es8p508x/libraries/CMSIS/core_cm0.h | 668 ----- bsp/essemi/es8p508x/libraries/CMSIS/core_cmFunc.h | 636 ---- bsp/essemi/es8p508x/libraries/CMSIS/core_cmInstr.h | 688 ----- .../es8p508x/libraries/CMSIS/startup_ES8P508x.s | 233 -- .../es8p508x/libraries/CMSIS/system_ES8P508x.c | 76 - .../es8p508x/libraries/CMSIS/system_ES8P508x.h | 23 - .../libraries/Library/Include/irqhandler.h | 17 - .../es8p508x/libraries/Library/Include/lib_adc.h | 239 -- .../es8p508x/libraries/Library/Include/lib_aes.h | 74 - .../libraries/Library/Include/lib_config.h | 32 - .../es8p508x/libraries/Library/Include/lib_crc.h | 93 - .../libraries/Library/Include/lib_flashiap.h | 44 - .../es8p508x/libraries/Library/Include/lib_gpio.h | 243 -- .../es8p508x/libraries/Library/Include/lib_iap.h | 42 - .../es8p508x/libraries/Library/Include/lib_iic.h | 229 -- .../libraries/Library/Include/lib_printf.h | 33 - .../es8p508x/libraries/Library/Include/lib_rtc.h | 84 - .../es8p508x/libraries/Library/Include/lib_scs.h | 98 - .../es8p508x/libraries/Library/Include/lib_scu.h | 314 -- .../es8p508x/libraries/Library/Include/lib_spi.h | 141 - .../es8p508x/libraries/Library/Include/lib_timer.h | 310 -- .../es8p508x/libraries/Library/Include/lib_uart.h | 171 -- .../es8p508x/libraries/Library/Include/lib_wdt.h | 100 - .../es8p508x/libraries/Library/Include/type.h | 19 - .../es8p508x/libraries/Library/Source/irqhandler.c | 27 - .../es8p508x/libraries/Library/Source/lib_adc.c | 301 -- .../es8p508x/libraries/Library/Source/lib_aes.c | 222 -- .../es8p508x/libraries/Library/Source/lib_crc.c | 96 - .../libraries/Library/Source/lib_flashiap.c | 355 --- .../es8p508x/libraries/Library/Source/lib_gpio.c | 619 ---- .../es8p508x/libraries/Library/Source/lib_iap.c | 97 - .../es8p508x/libraries/Library/Source/lib_iic.c | 311 -- .../es8p508x/libraries/Library/Source/lib_printf.c | 283 -- .../es8p508x/libraries/Library/Source/lib_rtc.c | 1906 ------------ .../es8p508x/libraries/Library/Source/lib_scs.c | 97 - .../es8p508x/libraries/Library/Source/lib_scu.c | 387 --- .../es8p508x/libraries/Library/Source/lib_spi.c | 233 -- .../es8p508x/libraries/Library/Source/lib_timer.c | 569 ---- .../es8p508x/libraries/Library/Source/lib_uart.c | 198 -- .../es8p508x/libraries/Library/Source/lib_wdt.c | 172 -- bsp/essemi/es8p508x/libraries/SConscript | 27 - 42 files changed, 13624 deletions(-) delete mode 100644 bsp/essemi/es8p508x/libraries/CMSIS/ES8P508x.h delete mode 100644 bsp/essemi/es8p508x/libraries/CMSIS/core_cm0.h delete mode 100644 bsp/essemi/es8p508x/libraries/CMSIS/core_cmFunc.h delete mode 100644 bsp/essemi/es8p508x/libraries/CMSIS/core_cmInstr.h delete mode 100644 bsp/essemi/es8p508x/libraries/CMSIS/startup_ES8P508x.s delete mode 100644 bsp/essemi/es8p508x/libraries/CMSIS/system_ES8P508x.c delete mode 100644 bsp/essemi/es8p508x/libraries/CMSIS/system_ES8P508x.h delete mode 100644 bsp/essemi/es8p508x/libraries/Library/Include/irqhandler.h delete mode 100644 bsp/essemi/es8p508x/libraries/Library/Include/lib_adc.h delete mode 100644 bsp/essemi/es8p508x/libraries/Library/Include/lib_aes.h delete mode 100644 bsp/essemi/es8p508x/libraries/Library/Include/lib_config.h delete mode 100644 bsp/essemi/es8p508x/libraries/Library/Include/lib_crc.h delete mode 100644 bsp/essemi/es8p508x/libraries/Library/Include/lib_flashiap.h delete mode 100644 bsp/essemi/es8p508x/libraries/Library/Include/lib_gpio.h delete mode 100644 bsp/essemi/es8p508x/libraries/Library/Include/lib_iap.h delete mode 100644 bsp/essemi/es8p508x/libraries/Library/Include/lib_iic.h delete mode 100644 bsp/essemi/es8p508x/libraries/Library/Include/lib_printf.h delete mode 100644 bsp/essemi/es8p508x/libraries/Library/Include/lib_rtc.h delete mode 100644 bsp/essemi/es8p508x/libraries/Library/Include/lib_scs.h delete mode 100644 bsp/essemi/es8p508x/libraries/Library/Include/lib_scu.h delete mode 100644 bsp/essemi/es8p508x/libraries/Library/Include/lib_spi.h delete mode 100644 bsp/essemi/es8p508x/libraries/Library/Include/lib_timer.h delete mode 100644 bsp/essemi/es8p508x/libraries/Library/Include/lib_uart.h delete mode 100644 bsp/essemi/es8p508x/libraries/Library/Include/lib_wdt.h delete mode 100644 bsp/essemi/es8p508x/libraries/Library/Include/type.h delete mode 100644 bsp/essemi/es8p508x/libraries/Library/Source/irqhandler.c delete mode 100644 bsp/essemi/es8p508x/libraries/Library/Source/lib_adc.c delete mode 100644 bsp/essemi/es8p508x/libraries/Library/Source/lib_aes.c delete mode 100644 bsp/essemi/es8p508x/libraries/Library/Source/lib_crc.c delete mode 100644 bsp/essemi/es8p508x/libraries/Library/Source/lib_flashiap.c delete mode 100644 bsp/essemi/es8p508x/libraries/Library/Source/lib_gpio.c delete mode 100644 bsp/essemi/es8p508x/libraries/Library/Source/lib_iap.c delete mode 100644 bsp/essemi/es8p508x/libraries/Library/Source/lib_iic.c delete mode 100644 bsp/essemi/es8p508x/libraries/Library/Source/lib_printf.c delete mode 100644 bsp/essemi/es8p508x/libraries/Library/Source/lib_rtc.c delete mode 100644 bsp/essemi/es8p508x/libraries/Library/Source/lib_scs.c delete mode 100644 bsp/essemi/es8p508x/libraries/Library/Source/lib_scu.c delete mode 100644 bsp/essemi/es8p508x/libraries/Library/Source/lib_spi.c delete mode 100644 bsp/essemi/es8p508x/libraries/Library/Source/lib_timer.c delete mode 100644 bsp/essemi/es8p508x/libraries/Library/Source/lib_uart.c delete mode 100644 bsp/essemi/es8p508x/libraries/Library/Source/lib_wdt.c delete mode 100644 bsp/essemi/es8p508x/libraries/SConscript (limited to 'bsp') diff --git a/bsp/essemi/es8p508x/libraries/CMSIS/ES8P508x.h b/bsp/essemi/es8p508x/libraries/CMSIS/ES8P508x.h deleted file mode 100644 index e6eab20bc4..0000000000 --- a/bsp/essemi/es8p508x/libraries/CMSIS/ES8P508x.h +++ /dev/null @@ -1,3117 +0,0 @@ -/******************************************************************* -* *file : ES8P508x.h -* *description: ES8P508x Device Head File -* *author : Eastsoft MCU Software Team -* *version : V0.01 -* *data : 7/11/2017 -* -* *Copyright (C) 2017 Shanghai Eastsoft Microelectronics Co., Ltd. -*******************************************************************/ -#ifndef __ES8P508x_H__ -#define __ES8P508x_H__ - -#define __I volatile const /* defines 'read only' permissions */ -#define __O volatile /* defines 'write only' permissions */ -#define __IO volatile /* defines 'read / write' permissions */ - -#define __CM0_REV 0 /* Core Revision r0p0 */ -#define __NVIC_PRIO_BITS 2 /* ES8P508x uses 2 Bits for the Priority Levels */ -#define __Vendor_SysTickConfig 0 /* Set to 1 if different SysTick Config is used */ - -typedef enum IRQn -{ - /****** Cortex-M0 Processor Exceptions Numbers ******************************************************/ - RST_IRQn = -15, - NonMaskableInt_IRQn = -14, - HardFault_IRQn = -13, - SVC_IRQn = -5, - PendSV_IRQn = -2, - SysTick_IRQn = -1, - PINT0_IRQn = 0, - PINT1_IRQn = 1, - PINT2_IRQn = 2, - PINT3_IRQn = 3, - PINT4_IRQn = 4, - PINT5_IRQn = 5, - PINT6_IRQn = 6, - PINT7_IRQn = 7, - T16N0_IRQn = 8, - T16N1_IRQn = 9, - T16N2_IRQn = 10, - T16N3_IRQn = 11, - T32N0_IRQn = 12, - Reserved0_IRQn = 13, - IWDT_IRQn = 14, - WWDT_IRQn = 15, - CCM_IRQn = 16, - PLK_IRQn = 17, - LVD_IRQn = 18, - KINT_IRQn = 19, - RTC_IRQn = 20, - ADC_IRQn = 21, - Reserved1_IRQn = 22, - AES_IRQn = 23, - UART0_IRQn = 24, - UART1_IRQn = 25, - UART2_IRQn = 26, - UART3_IRQn = 27, - UART4_IRQn = 28, - UART5_IRQn = 29, - SPI0_IRQn = 30, - I2C0_IRQn = 31, -} IRQn_Type; - - -#include "core_cm0.h" -#include - - -/******************************************************************************/ -/* 设备特殊寄存器结构定䷿ */ -/******************************************************************************/ - -/* 允许匿名结构和匿名联县 */ -#pragma anon_unions - -typedef union -{ - struct - { - uint32_t PROT: 1; - uint32_t RESERVED0: 31; - }; - uint32_t Word; -} SCU_PROT_Typedef; - -typedef union -{ - struct - { - uint32_t NMIEN: 1; - uint32_t NMICS: 5; - uint32_t RESERVED0: 26; - }; - uint32_t Word; -} SCU_NMICON_Typedef; - -typedef union -{ - struct - { - uint32_t PORF: 1; - uint32_t PORRCF: 1; - uint32_t PORRSTF: 1; - uint32_t BORF: 1; - uint32_t WWDTRSTF: 1; - uint32_t IWDTRSTF: 1; - uint32_t MRSTF: 1; - uint32_t SOFT_RSTF: 1; - uint32_t POR_LOST: 1; - uint32_t CFG_RST: 1; - uint32_t LOCKUP_RST: 1; - uint32_t RESERVED0: 21; - }; - uint32_t Word; -} SCU_PWRC_Typedef; - -typedef union -{ - struct - { - uint32_t FLAG0: 1; - uint32_t FLAG1: 1; - uint32_t FLAG2: 1; - uint32_t FLAG3: 1; - uint32_t FLAG4: 1; - uint32_t RESERVED0: 27; - }; - uint32_t Word; -} SCU_FAULTFLAG_Typedef; - -typedef union -{ - struct - { - uint32_t WAKEUPTIME: 12; - uint32_t MOSC_EN: 1; - uint32_t CLKFLT_EN: 1; - uint32_t FLASHPW_PD: 1; - uint32_t RESERVED0: 1; - uint32_t LDOLP_VOSEL: 3; - uint32_t LDOHP_SOFT: 1; - uint32_t RESERVED1: 12; - }; - uint32_t Word; -} SCU_WAKEUPTIME_Typedef; - -typedef union -{ - struct - { - uint32_t PINST: 1; - uint32_t RESERVED0: 31; - }; - uint32_t Word; -} SCU_MRSTN_SOFT_Typedef; - -typedef union -{ - struct - { - uint32_t T16N0HT: 1; - uint32_t T16N1HT: 1; - uint32_t T16N2HT: 1; - uint32_t T16N3HT: 1; - uint32_t RESERVED0: 4; - uint32_t T32N0HT: 1; - uint32_t RESERVED1: 7; - uint32_t IWDTHT: 1; - uint32_t WWDTHT: 1; - uint32_t RESERVED2: 14; - }; - uint32_t Word; -} SCU_DBGHALT_Typedef; - -typedef union -{ - struct - { - uint32_t ACCT: 4; - uint32_t HS: 1; - uint32_t RESERVED0: 27; - }; - uint32_t Word; -} SCU_FLASHWAIT_Typedef; - -typedef union -{ - struct - { - uint32_t RESERVED0: 1; - uint32_t BORV: 4; - uint32_t BORFLT: 3; - uint32_t RESERVED1: 24; - }; - uint32_t Word; -} SCU_SOFTCFG_Typedef; - -typedef union -{ - struct - { - uint32_t EN: 1; - uint32_t FLTEN: 1; - uint32_t RESERVED0: 2; - uint32_t VS: 4; - uint32_t IF: 1; - uint32_t IE: 1; - uint32_t IFS: 3; - uint32_t RESERVED1: 2; - uint32_t LVDO: 1; - uint32_t RESERVED2: 16; - }; - uint32_t Word; -} SCU_LVDCON_Typedef; - -typedef union -{ - struct - { - uint32_t EN: 1; - uint32_t RESERVED0: 3; - uint32_t IE: 1; - uint32_t IFS: 3; - uint32_t IF: 1; - uint32_t RESERVED1: 7; - uint32_t FLAG: 1; - uint32_t RESERVED2: 15; - }; - uint32_t Word; -} SCU_CCM_Typedef; - -typedef union -{ - struct - { - uint32_t IE: 1; - uint32_t RESERVED0: 3; - uint32_t LK_IFS: 3; - uint32_t RESERVED1: 1; - uint32_t IF: 1; - uint32_t RESERVED2: 7; - uint32_t LK_FLAG: 1; - uint32_t RESERVED3: 15; - }; - uint32_t Word; -} SCU_PLLLKCON_Typedef; - -typedef union -{ - struct - { - uint32_t CLK_SEL: 2; - uint32_t XTAL_LP: 1; - uint32_t RESERVED0: 5; - uint32_t PLL_MUX: 1; - uint32_t RESERVED1: 3; - uint32_t SYSCLK_DIV: 3; - uint32_t RESERVED2: 1; - uint32_t CLKFLT_BY: 8; - uint32_t CLKOUT0_SEL: 2; - uint32_t CLKOUT1_SEL: 2; - uint32_t RESERVED3: 4; - }; - uint32_t Word; -} SCU_SCLKEN0_Typedef; - -typedef union -{ - struct - { - uint32_t XTAL_EN: 1; - uint32_t HRC_EN: 1; - uint32_t RESERVED0: 6; - uint32_t PLL_REF_SEL: 3; - uint32_t PLL_48M_SEL: 1; - uint32_t PLL_EN: 1; - uint32_t PLL_BYLOCK: 1; - uint32_t RESERVED1: 2; - uint32_t XTAL_RDY: 1; - uint32_t HRC_RDY: 1; - uint32_t PLL_RDY: 1; - uint32_t RESERVED2: 13; - }; - uint32_t Word; -} SCU_SCLKEN1_Typedef; - -typedef union -{ - struct - { - uint32_t SCU_EN: 1; - uint32_t GPIO_EN: 1; - uint32_t IAP_EN: 1; - uint32_t CRC_EN: 1; - uint32_t ADC_EN: 1; - uint32_t RTC_EN: 1; - uint32_t RESERVED0: 1; - uint32_t IWDT_EN: 1; - uint32_t WWDT_EN: 1; - uint32_t AES_EN: 1; - uint32_t RESERVED1: 22; - }; - uint32_t Word; -} SCU_PCLKEN0_Typedef; - -typedef union -{ - struct - { - uint32_t T16N0_EN: 1; - uint32_t T16N1_EN: 1; - uint32_t T16N2_EN: 1; - uint32_t T16N3_EN: 1; - uint32_t RESERVED0: 4; - uint32_t T32N0_EN: 1; - uint32_t RESERVED1: 7; - uint32_t UART0_EN: 1; - uint32_t UART1_EN: 1; - uint32_t UART2_EN: 1; - uint32_t UART3_EN: 1; - uint32_t UART4_EN: 1; - uint32_t UART5_EN: 1; - uint32_t RESERVED2: 2; - uint32_t SPI0_EN: 1; - uint32_t RESERVED3: 3; - uint32_t I2C0_EN: 1; - uint32_t RESERVED4: 3; - }; - uint32_t Word; -} SCU_PCLKEN1_Typedef; - -typedef union -{ - struct - { - uint32_t RESERVED0: 1; - uint32_t GPIO_RST: 1; - uint32_t IAP_RST: 1; - uint32_t CRC_RST: 1; - uint32_t ADC_RST: 1; - uint32_t RTC_RST: 1; - uint32_t RESERVED1: 1; - uint32_t IWDT_RST: 1; - uint32_t WWDT_RST: 1; - uint32_t AES_RST: 1; - uint32_t RESERVED2: 22; - }; - uint32_t Word; -} SCU_PRSTEN0_Typedef; - -typedef union -{ - struct - { - uint32_t T16N0_RST: 1; - uint32_t T16N1_RST: 1; - uint32_t T16N2_RST: 1; - uint32_t T16N3_RST: 1; - uint32_t RESERVED0: 4; - uint32_t T32N0_RST: 1; - uint32_t RESERVED1: 7; - uint32_t UART0_RST: 1; - uint32_t UART1_RST: 1; - uint32_t UART2_RST: 1; - uint32_t UART3_RST: 1; - uint32_t UART4_RST: 1; - uint32_t UART5_RST: 1; - uint32_t RESERVED2: 2; - uint32_t SPI0_RST: 1; - uint32_t RESERVED3: 3; - uint32_t I2C0_RST: 1; - uint32_t RESERVED4: 3; - }; - uint32_t Word; -} SCU_PRSTEN1_Typedef; - -typedef union -{ - struct - { - uint32_t T16N0EN: 1; - uint32_t T16N1EN: 1; - uint32_t T16N2EN: 1; - uint32_t T16N3EN: 1; - uint32_t RESERVED0: 4; - uint32_t T32N0EN: 1; - uint32_t RESERVED1: 23; - }; - uint32_t Word; -} SCU_TIMEREN_Typedef; - -typedef union -{ - struct - { - uint32_t T16N0DIS: 1; - uint32_t T16N1DIS: 1; - uint32_t T16N2DIS: 1; - uint32_t T16N3DIS: 1; - uint32_t RESERVED0: 4; - uint32_t T32N0DIS: 1; - uint32_t RESERVED1: 23; - }; - uint32_t Word; -} SCU_TIMERDIS_Typedef; - -typedef union -{ - struct - { - uint32_t EN: 1; - uint32_t RESERVED0: 31; - }; - uint32_t Word; -} SCU_TBLREMAPEN_Typedef; - -typedef union -{ - struct - { - uint32_t TBLOFF: 32; - }; - uint32_t Word; -} SCU_TBLOFF_Typedef; - -typedef struct -{ - __IO SCU_PROT_Typedef PROT; - __IO SCU_NMICON_Typedef NMICON; - __IO SCU_PWRC_Typedef PWRC; - __IO SCU_FAULTFLAG_Typedef FAULTFLAG; - __IO SCU_WAKEUPTIME_Typedef WAKEUPTIME; - __IO SCU_MRSTN_SOFT_Typedef MRSTN_SOFT; - __IO SCU_DBGHALT_Typedef DBGHALT; - uint32_t RESERVED0 ; - __IO SCU_FLASHWAIT_Typedef FLASHWAIT; - __IO SCU_SOFTCFG_Typedef SOFTCFG; - __IO SCU_LVDCON_Typedef LVDCON; - __IO SCU_CCM_Typedef CCM; - __IO SCU_PLLLKCON_Typedef PLLLKCON; - uint32_t RESERVED1[3] ; - __IO SCU_SCLKEN0_Typedef SCLKEN0; - __IO SCU_SCLKEN1_Typedef SCLKEN1; - __IO SCU_PCLKEN0_Typedef PCLKEN0; - __IO SCU_PCLKEN1_Typedef PCLKEN1; - __IO SCU_PRSTEN0_Typedef PRSTEN0; - __IO SCU_PRSTEN1_Typedef PRSTEN1; - __O SCU_TIMEREN_Typedef TIMEREN; - __IO SCU_TIMERDIS_Typedef TIMERDIS; - __IO SCU_TBLREMAPEN_Typedef TBLREMAPEN; - __IO SCU_TBLOFF_Typedef TBLOFF; -} SCU_TypeDef; - -typedef union -{ - struct - { - uint32_t UL: 32; - }; - uint32_t Word; -} CRC_UL_Typedef; - -typedef union -{ - struct - { - uint32_t EN: 1; - uint32_t RST: 1; - uint32_t HS: 1; - uint32_t DS: 1; - uint32_t REQ: 1; - uint32_t ACK: 1; - uint32_t RESERVED0: 2; - uint32_t MOD: 2; - uint32_t BYTE: 2; - uint32_t REFIN: 1; - uint32_t REFOUT: 1; - uint32_t XOROUT: 1; - uint32_t RESERVED1: 17; - }; - uint32_t Word; -} CRC_CON_Typedef; - -typedef union -{ - struct - { - uint32_t TRIG: 32; - }; - uint32_t Word; -} CRC_TRIG_Typedef; - -typedef union -{ - struct - { - uint32_t ADDR: 17; - uint32_t RESERVED0: 3; - uint32_t IFREN: 1; - uint32_t RESERVED1: 11; - }; - uint32_t Word; -} CRC_ADDR_Typedef; - -typedef union -{ - struct - { - uint32_t CRC_SIZE: 15; - uint32_t RESERVED0: 17; - }; - uint32_t Word; -} CRC_SIZE_Typedef; - -typedef union -{ - struct - { - uint32_t DI: 32; - }; - uint32_t Word; -} CRC_DI_Typedef; - -typedef union -{ - struct - { - uint32_t DO: 32; - }; - uint32_t Word; -} CRC_DO_Typedef; - -typedef union -{ - struct - { - uint32_t BUSY: 1; - uint32_t RSTF: 1; - uint32_t EMPTY_ERR: 1; - uint32_t RESERVED0: 29; - }; - uint32_t Word; -} CRC_STA_Typedef; - -typedef union -{ - struct - { - uint32_t FADR: 15; - uint32_t RESERVED0: 5; - uint32_t IFREN: 1; - uint32_t RESERVED1: 11; - }; - uint32_t Word; -} CRC_FA_Typedef; - -typedef struct -{ - __IO CRC_UL_Typedef UL; - __IO CRC_CON_Typedef CON; - __IO CRC_TRIG_Typedef TRIG; - __IO CRC_ADDR_Typedef ADDR; - __IO CRC_SIZE_Typedef SIZE; - __IO CRC_DI_Typedef DI; - __I CRC_DO_Typedef DO; - __IO CRC_STA_Typedef STA; - __I CRC_FA_Typedef FA; -} CRC_TypeDef; - -typedef union -{ - struct - { - uint32_t PORT_0: 1; - uint32_t PORT_1: 1; - uint32_t PORT_2: 1; - uint32_t PORT_3: 1; - uint32_t PORT_4: 1; - uint32_t PORT_5: 1; - uint32_t PORT_6: 1; - uint32_t PORT_7: 1; - uint32_t PORT_8: 1; - uint32_t PORT_9: 1; - uint32_t PORT_10: 1; - uint32_t PORT_11: 1; - uint32_t PORT_12: 1; - uint32_t PORT_13: 1; - uint32_t PORT_14: 1; - uint32_t PORT_15: 1; - uint32_t PORT_16: 1; - uint32_t PORT_17: 1; - uint32_t PORT_18: 1; - uint32_t PORT_19: 1; - uint32_t PORT_20: 1; - uint32_t PORT_21: 1; - uint32_t PORT_22: 1; - uint32_t PORT_23: 1; - uint32_t PORT_24: 1; - uint32_t PORT_25: 1; - uint32_t PORT_26: 1; - uint32_t PORT_27: 1; - uint32_t PORT_28: 1; - uint32_t PORT_29: 1; - uint32_t PORT_30: 1; - uint32_t PORT_31: 1; - }; - uint32_t Word; -} GPIO_PAPORT_Typedef; - -typedef union -{ - struct - { - uint32_t DATA_0: 1; - uint32_t DATA_1: 1; - uint32_t DATA_2: 1; - uint32_t DATA_3: 1; - uint32_t DATA_4: 1; - uint32_t DATA_5: 1; - uint32_t DATA_6: 1; - uint32_t DATA_7: 1; - uint32_t DATA_8: 1; - uint32_t DATA_9: 1; - uint32_t DATA_10: 1; - uint32_t DATA_11: 1; - uint32_t DATA_12: 1; - uint32_t DATA_13: 1; - uint32_t DATA_14: 1; - uint32_t DATA_15: 1; - uint32_t DATA_16: 1; - uint32_t DATA_17: 1; - uint32_t DATA_18: 1; - uint32_t DATA_19: 1; - uint32_t DATA_20: 1; - uint32_t DATA_21: 1; - uint32_t DATA_22: 1; - uint32_t DATA_23: 1; - uint32_t DATA_24: 1; - uint32_t DATA_25: 1; - uint32_t DATA_26: 1; - uint32_t DATA_27: 1; - uint32_t DATA_28: 1; - uint32_t DATA_29: 1; - uint32_t DATA_30: 1; - uint32_t DATA_31: 1; - }; - uint32_t Word; -} GPIO_PADATA_Typedef; - -typedef union -{ - uint32_t Word; -} GPIO_PADATABSR_Typedef; - -typedef union -{ - uint32_t Word; -} GPIO_PADATABCR_Typedef; - -typedef union -{ - uint32_t Word; -} GPIO_PADATABRR_Typedef; - -typedef union -{ - struct - { - uint32_t DIR_0: 1; - uint32_t DIR_1: 1; - uint32_t DIR_2: 1; - uint32_t DIR_3: 1; - uint32_t DIR_4: 1; - uint32_t DIR_5: 1; - uint32_t DIR_6: 1; - uint32_t DIR_7: 1; - uint32_t DIR_8: 1; - uint32_t DIR_9: 1; - uint32_t DIR_10: 1; - uint32_t DIR_11: 1; - uint32_t DIR_12: 1; - uint32_t DIR_13: 1; - uint32_t DIR_14: 1; - uint32_t DIR_15: 1; - uint32_t DIR_16: 1; - uint32_t DIR_17: 1; - uint32_t DIR_18: 1; - uint32_t DIR_19: 1; - uint32_t DIR_20: 1; - uint32_t DIR_21: 1; - uint32_t DIR_22: 1; - uint32_t DIR_23: 1; - uint32_t DIR_24: 1; - uint32_t DIR_25: 1; - uint32_t DIR_26: 1; - uint32_t DIR_27: 1; - uint32_t DIR_28: 1; - uint32_t DIR_29: 1; - uint32_t DIR_30: 1; - uint32_t DIR_31: 1; - }; - uint32_t Word; -} GPIO_PADIR_Typedef; - -typedef union -{ - uint32_t Word; -} GPIO_PADIRBSR_Typedef; - -typedef union -{ - uint32_t Word; -} GPIO_PADIRBCR_Typedef; - -typedef union -{ - uint32_t Word; -} GPIO_PADIRBRR_Typedef; - -typedef union -{ - struct - { - uint32_t PA0: 2; - uint32_t RESERVED0: 2; - uint32_t PA1: 2; - uint32_t RESERVED1: 2; - uint32_t PA2: 2; - uint32_t RESERVED2: 2; - uint32_t PA3: 2; - uint32_t RESERVED3: 2; - uint32_t PA4: 2; - uint32_t RESERVED4: 2; - uint32_t PA5: 2; - uint32_t RESERVED5: 2; - uint32_t PA6: 2; - uint32_t RESERVED6: 2; - uint32_t PA7: 2; - uint32_t RESERVED7: 2; - }; - uint32_t Word; -} GPIO_PAFUNC0_Typedef; - -typedef union -{ - struct - { - uint32_t PA8: 2; - uint32_t RESERVED0: 2; - uint32_t PA9: 2; - uint32_t RESERVED1: 2; - uint32_t PA10: 2; - uint32_t RESERVED2: 2; - uint32_t PA11: 2; - uint32_t RESERVED3: 2; - uint32_t PA12: 2; - uint32_t RESERVED4: 2; - uint32_t PA13: 2; - uint32_t RESERVED5: 2; - uint32_t PA14: 2; - uint32_t RESERVED6: 2; - uint32_t PA15: 2; - uint32_t RESERVED7: 2; - }; - uint32_t Word; -} GPIO_PAFUNC1_Typedef; - -typedef union -{ - struct - { - uint32_t PA16: 2; - uint32_t RESERVED0: 2; - uint32_t PA17: 2; - uint32_t RESERVED1: 2; - uint32_t PA18: 2; - uint32_t RESERVED2: 2; - uint32_t PA19: 2; - uint32_t RESERVED3: 2; - uint32_t PA20: 2; - uint32_t RESERVED4: 2; - uint32_t PA21: 2; - uint32_t RESERVED5: 2; - uint32_t PA22: 2; - uint32_t RESERVED6: 2; - uint32_t PA23: 2; - uint32_t RESERVED7: 2; - }; - uint32_t Word; -} GPIO_PAFUNC2_Typedef; - -typedef union -{ - struct - { - uint32_t PA24: 2; - uint32_t RESERVED0: 2; - uint32_t PA25: 2; - uint32_t RESERVED1: 2; - uint32_t PA26: 2; - uint32_t RESERVED2: 2; - uint32_t PA27: 2; - uint32_t RESERVED3: 2; - uint32_t PA28: 2; - uint32_t RESERVED4: 2; - uint32_t PA29: 2; - uint32_t RESERVED5: 2; - uint32_t PA30: 2; - uint32_t RESERVED6: 2; - uint32_t PA31: 2; - uint32_t RESERVED7: 2; - }; - uint32_t Word; -} GPIO_PAFUNC3_Typedef; - -typedef union -{ - struct - { - uint32_t INEB_0: 1; - uint32_t INEB_1: 1; - uint32_t INEB_2: 1; - uint32_t INEB_3: 1; - uint32_t INEB_4: 1; - uint32_t INEB_5: 1; - uint32_t INEB_6: 1; - uint32_t INEB_7: 1; - uint32_t INEB_8: 1; - uint32_t INEB_9: 1; - uint32_t INEB_10: 1; - uint32_t INEB_11: 1; - uint32_t INEB_12: 1; - uint32_t INEB_13: 1; - uint32_t INEB_14: 1; - uint32_t INEB_15: 1; - uint32_t INEB_16: 1; - uint32_t INEB_17: 1; - uint32_t INEB_18: 1; - uint32_t INEB_19: 1; - uint32_t INEB_20: 1; - uint32_t INEB_21: 1; - uint32_t INEB_22: 1; - uint32_t INEB_23: 1; - uint32_t INEB_24: 1; - uint32_t INEB_25: 1; - uint32_t INEB_26: 1; - uint32_t INEB_27: 1; - uint32_t INEB_28: 1; - uint32_t INEB_29: 1; - uint32_t INEB_30: 1; - uint32_t INEB_31: 1; - }; - uint32_t Word; -} GPIO_PAINEB_Typedef; - -typedef union -{ - struct - { - uint32_t ODE_0: 1; - uint32_t ODE_1: 1; - uint32_t ODE_2: 1; - uint32_t ODE_3: 1; - uint32_t ODE_4: 1; - uint32_t ODE_5: 1; - uint32_t ODE_6: 1; - uint32_t ODE_7: 1; - uint32_t ODE_8: 1; - uint32_t ODE_9: 1; - uint32_t ODE_10: 1; - uint32_t ODE_11: 1; - uint32_t ODE_12: 1; - uint32_t ODE_13: 1; - uint32_t ODE_14: 1; - uint32_t ODE_15: 1; - uint32_t ODE_16: 1; - uint32_t ODE_17: 1; - uint32_t ODE_18: 1; - uint32_t ODE_19: 1; - uint32_t ODE_20: 1; - uint32_t ODE_21: 1; - uint32_t ODE_22: 1; - uint32_t ODE_23: 1; - uint32_t ODE_24: 1; - uint32_t ODE_25: 1; - uint32_t ODE_26: 1; - uint32_t ODE_27: 1; - uint32_t ODE_28: 1; - uint32_t ODE_29: 1; - uint32_t ODE_30: 1; - uint32_t ODE_31: 1; - }; - uint32_t Word; -} GPIO_PAODE_Typedef; - -typedef union -{ - struct - { - uint32_t PUE_0: 1; - uint32_t PUE_1: 1; - uint32_t PUE_2: 1; - uint32_t PUE_3: 1; - uint32_t PUE_4: 1; - uint32_t PUE_5: 1; - uint32_t PUE_6: 1; - uint32_t PUE_7: 1; - uint32_t PUE_8: 1; - uint32_t PUE_9: 1; - uint32_t PUE_10: 1; - uint32_t PUE_11: 1; - uint32_t PUE_12: 1; - uint32_t PUE_13: 1; - uint32_t PUE_14: 1; - uint32_t PUE_15: 1; - uint32_t PUE_16: 1; - uint32_t PUE_17: 1; - uint32_t PUE_18: 1; - uint32_t PUE_19: 1; - uint32_t PUE_20: 1; - uint32_t PUE_21: 1; - uint32_t PUE_22: 1; - uint32_t PUE_23: 1; - uint32_t PUE_24: 1; - uint32_t PUE_25: 1; - uint32_t PUE_26: 1; - uint32_t PUE_27: 1; - uint32_t PUE_28: 1; - uint32_t PUE_29: 1; - uint32_t PUE_30: 1; - uint32_t PUE_31: 1; - }; - uint32_t Word; -} GPIO_PAPUE_Typedef; - -typedef union -{ - struct - { - uint32_t PDE_0: 1; - uint32_t PDE_1: 1; - uint32_t PDE_2: 1; - uint32_t PDE_3: 1; - uint32_t PDE_4: 1; - uint32_t PDE_5: 1; - uint32_t PDE_6: 1; - uint32_t PDE_7: 1; - uint32_t PDE_8: 1; - uint32_t PDE_9: 1; - uint32_t PDE_10: 1; - uint32_t PDE_11: 1; - uint32_t PDE_12: 1; - uint32_t PDE_13: 1; - uint32_t PDE_14: 1; - uint32_t PDE_15: 1; - uint32_t PDE_16: 1; - uint32_t PDE_17: 1; - uint32_t PDE_18: 1; - uint32_t PDE_19: 1; - uint32_t PDE_20: 1; - uint32_t PDE_21: 1; - uint32_t PDE_22: 1; - uint32_t PDE_23: 1; - uint32_t PDE_24: 1; - uint32_t PDE_25: 1; - uint32_t PDE_26: 1; - uint32_t PDE_27: 1; - uint32_t PDE_28: 1; - uint32_t PDE_29: 1; - uint32_t PDE_30: 1; - uint32_t PDE_31: 1; - }; - uint32_t Word; -} GPIO_PAPDE_Typedef; - -typedef union -{ - struct - { - uint32_t DS_0: 1; - uint32_t DS_1: 1; - uint32_t DS_2: 1; - uint32_t DS_3: 1; - uint32_t DS_4: 1; - uint32_t DS_5: 1; - uint32_t DS_6: 1; - uint32_t DS_7: 1; - uint32_t DS_8: 1; - uint32_t DS_9: 1; - uint32_t DS_10: 1; - uint32_t DS_11: 1; - uint32_t DS_12: 1; - uint32_t DS_13: 1; - uint32_t DS_14: 1; - uint32_t DS_15: 1; - uint32_t DS_16: 1; - uint32_t DS_17: 1; - uint32_t DS_18: 1; - uint32_t DS_19: 1; - uint32_t DS_20: 1; - uint32_t DS_21: 1; - uint32_t DS_22: 1; - uint32_t DS_23: 1; - uint32_t DS_24: 1; - uint32_t DS_25: 1; - uint32_t DS_26: 1; - uint32_t DS_27: 1; - uint32_t DS_28: 1; - uint32_t DS_29: 1; - uint32_t DS_30: 1; - uint32_t DS_31: 1; - }; - uint32_t Word; -} GPIO_PADS_Typedef; - -typedef union -{ - struct - { - uint32_t PORT_0: 1; - uint32_t PORT_1: 1; - uint32_t PORT_2: 1; - uint32_t PORT_3: 1; - uint32_t PORT_4: 1; - uint32_t PORT_5: 1; - uint32_t PORT_6: 1; - uint32_t PORT_7: 1; - uint32_t PORT_8: 1; - uint32_t PORT_9: 1; - uint32_t PORT_10: 1; - uint32_t PORT_11: 1; - uint32_t PORT_12: 1; - uint32_t PORT_13: 1; - uint32_t RESERVED0: 18; - }; - uint32_t Word; -} GPIO_PBPORT_Typedef; - -typedef union -{ - struct - { - uint32_t DATA_0: 1; - uint32_t DATA_1: 1; - uint32_t DATA_2: 1; - uint32_t DATA_3: 1; - uint32_t DATA_4: 1; - uint32_t DATA_5: 1; - uint32_t DATA_6: 1; - uint32_t DATA_7: 1; - uint32_t DATA_8: 1; - uint32_t DATA_9: 1; - uint32_t DATA_10: 1; - uint32_t DATA_11: 1; - uint32_t DATA_12: 1; - uint32_t DATA_13: 1; - uint32_t RESERVED0: 18; - }; - uint32_t Word; -} GPIO_PBDATA_Typedef; - -typedef union -{ - uint32_t Word; -} GPIO_PBDATABSR_Typedef; - -typedef union -{ - uint32_t Word; -} GPIO_PBDATABCR_Typedef; - -typedef union -{ - uint32_t Word; -} GPIO_PBDATABRR_Typedef; - -typedef union -{ - struct - { - uint32_t DIR_0: 1; - uint32_t DIR_1: 1; - uint32_t DIR_2: 1; - uint32_t DIR_3: 1; - uint32_t DIR_4: 1; - uint32_t DIR_5: 1; - uint32_t DIR_6: 1; - uint32_t DIR_7: 1; - uint32_t DIR_8: 1; - uint32_t DIR_9: 1; - uint32_t DIR_10: 1; - uint32_t DIR_11: 1; - uint32_t DIR_12: 1; - uint32_t DIR_13: 1; - uint32_t RESERVED0: 18; - }; - uint32_t Word; -} GPIO_PBDIR_Typedef; - -typedef union -{ - uint32_t Word; -} GPIO_PBDIRBSR_Typedef; - -typedef union -{ - uint32_t Word; -} GPIO_PBDIRBCR_Typedef; - -typedef union -{ - uint32_t Word; -} GPIO_PBDIRBRR_Typedef; - -typedef union -{ - struct - { - uint32_t PB0: 2; - uint32_t RESERVED0: 2; - uint32_t PB1: 2; - uint32_t RESERVED1: 2; - uint32_t PB2: 2; - uint32_t RESERVED2: 2; - uint32_t PB3: 2; - uint32_t RESERVED3: 2; - uint32_t PB4: 2; - uint32_t RESERVED4: 2; - uint32_t PB5: 2; - uint32_t RESERVED5: 2; - uint32_t PB6: 2; - uint32_t RESERVED6: 2; - uint32_t PB7: 2; - uint32_t RESERVED7: 2; - }; - uint32_t Word; -} GPIO_PBFUNC0_Typedef; - -typedef union -{ - struct - { - uint32_t PB8: 2; - uint32_t RESERVED0: 2; - uint32_t PB9: 2; - uint32_t RESERVED1: 2; - uint32_t PB10: 2; - uint32_t RESERVED2: 2; - uint32_t PB11: 2; - uint32_t RESERVED3: 2; - uint32_t PB12: 2; - uint32_t RESERVED4: 2; - uint32_t PB13: 2; - uint32_t RESERVED5: 10; - }; - uint32_t Word; -} GPIO_PBFUNC1_Typedef; - -typedef union -{ - struct - { - uint32_t INEB_0: 1; - uint32_t INEB_1: 1; - uint32_t INEB_2: 1; - uint32_t INEB_3: 1; - uint32_t INEB_4: 1; - uint32_t INEB_5: 1; - uint32_t INEB_6: 1; - uint32_t INEB_7: 1; - uint32_t INEB_8: 1; - uint32_t INEB_9: 1; - uint32_t INEB_10: 1; - uint32_t INEB_11: 1; - uint32_t INEB_12: 1; - uint32_t INEB_13: 1; - uint32_t RESERVED0: 18; - }; - uint32_t Word; -} GPIO_PBINEB_Typedef; - -typedef union -{ - struct - { - uint32_t ODE_0: 1; - uint32_t ODE_1: 1; - uint32_t ODE_2: 1; - uint32_t ODE_3: 1; - uint32_t ODE_4: 1; - uint32_t ODE_5: 1; - uint32_t ODE_6: 1; - uint32_t ODE_7: 1; - uint32_t ODE_8: 1; - uint32_t ODE_9: 1; - uint32_t ODE_10: 1; - uint32_t ODE_11: 1; - uint32_t ODE_12: 1; - uint32_t ODE_13: 1; - uint32_t RESERVED0: 18; - }; - uint32_t Word; -} GPIO_PBODE_Typedef; - -typedef union -{ - struct - { - uint32_t PUEN_0: 1; - uint32_t PUEN_1: 1; - uint32_t PUEN_2: 1; - uint32_t PUEN_3: 1; - uint32_t PUEN_4: 1; - uint32_t PUEN_5: 1; - uint32_t PUEN_6: 1; - uint32_t PUEN_7: 1; - uint32_t PUEN_8: 1; - uint32_t PUEN_9: 1; - uint32_t PUEN_10: 1; - uint32_t PUEN_11: 1; - uint32_t PUEN_12: 1; - uint32_t PUEN_13: 1; - uint32_t RESERVED0: 18; - }; - uint32_t Word; -} GPIO_PBPUE_Typedef; - -typedef union -{ - struct - { - uint32_t PDEN_0: 1; - uint32_t PDEN_1: 1; - uint32_t PDEN_2: 1; - uint32_t PDEN_3: 1; - uint32_t PDEN_4: 1; - uint32_t PDEN_5: 1; - uint32_t PDEN_6: 1; - uint32_t PDEN_7: 1; - uint32_t PDEN_8: 1; - uint32_t PDEN_9: 1; - uint32_t PDEN_10: 1; - uint32_t PDEN_11: 1; - uint32_t PDEN_12: 1; - uint32_t PDEN_13: 1; - uint32_t RESERVED0: 18; - }; - uint32_t Word; -} GPIO_PBPDE_Typedef; - -typedef union -{ - struct - { - uint32_t DS_0: 1; - uint32_t DS_1: 1; - uint32_t DS_2: 1; - uint32_t DS_3: 1; - uint32_t DS_4: 1; - uint32_t DS_5: 1; - uint32_t DS_6: 1; - uint32_t DS_7: 1; - uint32_t DS_8: 1; - uint32_t DS_9: 1; - uint32_t DS_10: 1; - uint32_t DS_11: 1; - uint32_t DS_12: 1; - uint32_t DS_13: 1; - uint32_t RESERVED0: 18; - }; - uint32_t Word; -} GPIO_PBDS_Typedef; - -typedef union -{ - struct - { - uint32_t PINTIE: 8; - uint32_t PMASK: 8; - uint32_t RESERVED0: 16; - }; - uint32_t Word; -} GPIO_PINTIE_Typedef; - -typedef union -{ - struct - { - uint32_t PINTIF_0: 1; - uint32_t PINTIF_1: 1; - uint32_t PINTIF_2: 1; - uint32_t PINTIF_3: 1; - uint32_t PINTIF_4: 1; - uint32_t PINTIF_5: 1; - uint32_t PINTIF_6: 1; - uint32_t PINTIF_7: 1; - uint32_t RESERVED0: 24; - }; - uint32_t Word; -} GPIO_PINTIF_Typedef; - -typedef union -{ - struct - { - uint32_t PINT0SEL: 3; - uint32_t RESERVED0: 1; - uint32_t PINT1SEL: 3; - uint32_t RESERVED1: 1; - uint32_t PINT2SEL: 3; - uint32_t RESERVED2: 1; - uint32_t PINT3SEL: 3; - uint32_t RESERVED3: 1; - uint32_t PINT4SEL: 3; - uint32_t RESERVED4: 1; - uint32_t PINT5SEL: 3; - uint32_t RESERVED5: 1; - uint32_t PINT6SEL: 3; - uint32_t RESERVED6: 1; - uint32_t PINT7SEL: 3; - uint32_t RESERVED7: 1; - }; - uint32_t Word; -} GPIO_PINTSEL_Typedef; - -typedef union -{ - struct - { - uint32_t PINT0CFG: 3; - uint32_t RESERVED0: 1; - uint32_t PINT1CFG: 3; - uint32_t RESERVED1: 1; - uint32_t PINT2CFG: 3; - uint32_t RESERVED2: 1; - uint32_t PINT3CFG: 3; - uint32_t RESERVED3: 1; - uint32_t PINT4CFG: 3; - uint32_t RESERVED4: 1; - uint32_t PINT5CFG: 3; - uint32_t RESERVED5: 1; - uint32_t PINT6CFG: 3; - uint32_t RESERVED6: 1; - uint32_t PINT7CFG: 3; - uint32_t RESERVED7: 1; - }; - uint32_t Word; -} GPIO_PINTCFG_Typedef; - -typedef union -{ - struct - { - uint32_t KINTIE: 8; - uint32_t KMASK: 8; - uint32_t RESERVED0: 16; - }; - uint32_t Word; -} GPIO_KINTIE_Typedef; - -typedef union -{ - struct - { - uint32_t KINTIF_0: 1; - uint32_t KINTIF_1: 1; - uint32_t KINTIF_2: 1; - uint32_t KINTIF_3: 1; - uint32_t KINTIF_4: 1; - uint32_t KINTIF_5: 1; - uint32_t KINTIF_6: 1; - uint32_t KINTIF_7: 1; - uint32_t RESERVED0: 24; - }; - uint32_t Word; -} GPIO_KINTIF_Typedef; - -typedef union -{ - struct - { - uint32_t KINT0SEL: 3; - uint32_t RESERVED0: 1; - uint32_t KINT1SEL: 3; - uint32_t RESERVED1: 1; - uint32_t KINT2SEL: 3; - uint32_t RESERVED2: 1; - uint32_t KINT3SEL: 3; - uint32_t RESERVED3: 1; - uint32_t KINT4SEL: 3; - uint32_t RESERVED4: 1; - uint32_t KINT5SEL: 3; - uint32_t RESERVED5: 1; - uint32_t KINT6SEL: 3; - uint32_t RESERVED6: 1; - uint32_t KINT7SEL: 3; - uint32_t RESERVED7: 1; - }; - uint32_t Word; -} GPIO_KINTSEL_Typedef; - -typedef union -{ - struct - { - uint32_t KINT0CFG: 3; - uint32_t RESERVED0: 1; - uint32_t KINT1CFG: 3; - uint32_t RESERVED1: 1; - uint32_t KINT2CFG: 3; - uint32_t RESERVED2: 1; - uint32_t KINT3CFG: 3; - uint32_t RESERVED3: 1; - uint32_t KINT4CFG: 3; - uint32_t RESERVED4: 1; - uint32_t KINT5CFG: 3; - uint32_t RESERVED5: 1; - uint32_t KINT6CFG: 3; - uint32_t RESERVED6: 1; - uint32_t KINT7CFG: 3; - uint32_t RESERVED7: 1; - }; - uint32_t Word; -} GPIO_KINTCFG_Typedef; - -typedef union -{ - struct - { - uint32_t FLT_S_0: 1; - uint32_t FLT_S_1: 1; - uint32_t FLT_S_2: 1; - uint32_t FLT_S_3: 1; - uint32_t FLT_S_4: 1; - uint32_t FLT_S_5: 1; - uint32_t FLT_S_6: 1; - uint32_t FLT_S_7: 1; - uint32_t RESERVED0: 24; - }; - uint32_t Word; -} GPIO_IOINTFLTS_Typedef; - -typedef union -{ - struct - { - uint32_t FLT0_SEL: 4; - uint32_t FLT1_SEL: 4; - uint32_t FLT2_SEL: 4; - uint32_t FLT3_SEL: 4; - uint32_t RESERVED0: 16; - }; - uint32_t Word; -} GPIO_TMRFLTSEL_Typedef; - -typedef union -{ - struct - { - uint32_t TX0PS: 2; - uint32_t RESERVED0: 2; - uint32_t TX0PLV: 1; - uint32_t TX0_S: 2; - uint32_t RESERVED1: 1; - uint32_t TX1PS: 2; - uint32_t RESERVED2: 2; - uint32_t TX1PLV: 1; - uint32_t TX1_S: 2; - uint32_t RESERVED3: 1; - uint32_t TX2PS: 2; - uint32_t RESERVED4: 2; - uint32_t TX2PLV: 1; - uint32_t TX2_S: 2; - uint32_t RESERVED5: 1; - uint32_t TX3PS: 2; - uint32_t RESERVED6: 2; - uint32_t TX3PLV: 1; - uint32_t TX3_S: 2; - uint32_t RESERVED7: 1; - }; - uint32_t Word; -} GPIO_TXPWM_Typedef; - -typedef union -{ - struct - { - uint32_t BUZEN: 1; - uint32_t RESERVED0: 7; - uint32_t BUZ_LOAD: 20; - uint32_t RESERVED1: 4; - }; - uint32_t Word; -} GPIO_BUZC_Typedef; - -typedef struct -{ - __I GPIO_PAPORT_Typedef PAPORT; - uint32_t RESERVED0[3] ; - __IO GPIO_PADATA_Typedef PADATA; - __O GPIO_PADATABSR_Typedef PADATABSR; - __O GPIO_PADATABCR_Typedef PADATABCR; - __O GPIO_PADATABRR_Typedef PADATABRR; - __IO GPIO_PADIR_Typedef PADIR; - __O GPIO_PADIRBSR_Typedef PADIRBSR; - __O GPIO_PADIRBCR_Typedef PADIRBCR; - __O GPIO_PADIRBRR_Typedef PADIRBRR; - __IO GPIO_PAFUNC0_Typedef PAFUNC0; - __IO GPIO_PAFUNC1_Typedef PAFUNC1; - __IO GPIO_PAFUNC2_Typedef PAFUNC2; - __IO GPIO_PAFUNC3_Typedef PAFUNC3; - __IO GPIO_PAINEB_Typedef PAINEB; - __IO GPIO_PAODE_Typedef PAODE; - __IO GPIO_PAPUE_Typedef PAPUE; - __IO GPIO_PAPDE_Typedef PAPDE; - __IO GPIO_PADS_Typedef PADS; - uint32_t RESERVED1[11] ; - __I GPIO_PBPORT_Typedef PBPORT; - uint32_t RESERVED2[3] ; - __IO GPIO_PBDATA_Typedef PBDATA; - __O GPIO_PBDATABSR_Typedef PBDATABSR; - __O GPIO_PBDATABCR_Typedef PBDATABCR; - __O GPIO_PBDATABRR_Typedef PBDATABRR; - __IO GPIO_PBDIR_Typedef PBDIR; - __O GPIO_PBDIRBSR_Typedef PBDIRBSR; - __O GPIO_PBDIRBCR_Typedef PBDIRBCR; - __O GPIO_PBDIRBRR_Typedef PBDIRBRR; - __IO GPIO_PBFUNC0_Typedef PBFUNC0; - __IO GPIO_PBFUNC1_Typedef PBFUNC1; - uint32_t RESERVED3[2] ; - __IO GPIO_PBINEB_Typedef PBINEB; - __IO GPIO_PBODE_Typedef PBODE; - __IO GPIO_PBPUE_Typedef PBPUE; - __IO GPIO_PBPDE_Typedef PBPDE; - __IO GPIO_PBDS_Typedef PBDS; - uint32_t RESERVED4[139] ; - __IO GPIO_PINTIE_Typedef PINTIE; - __IO GPIO_PINTIF_Typedef PINTIF; - __IO GPIO_PINTSEL_Typedef PINTSEL; - __IO GPIO_PINTCFG_Typedef PINTCFG; - __IO GPIO_KINTIE_Typedef KINTIE; - __IO GPIO_KINTIF_Typedef KINTIF; - __IO GPIO_KINTSEL_Typedef KINTSEL; - __IO GPIO_KINTCFG_Typedef KINTCFG; - uint32_t RESERVED5[4] ; - __IO GPIO_IOINTFLTS_Typedef IOINTFLTS; - uint32_t RESERVED6[3] ; - __IO GPIO_TMRFLTSEL_Typedef TMRFLTSEL; - uint32_t RESERVED7[15] ; - __IO GPIO_TXPWM_Typedef TXPWM; - uint32_t RESERVED8[3] ; - __IO GPIO_BUZC_Typedef BUZC; -} GPIO_TypeDef; - -typedef union -{ - struct - { - uint32_t EN: 1; - uint32_t RST: 1; - uint32_t RESERVED0: 2; - uint32_t FLASH_REQ: 1; - uint32_t FLASH_ACK: 1; - uint32_t RESERVED1: 1; - uint32_t FLASH_FAIL: 1; - uint32_t FEWE: 1; - uint32_t SEWE: 1; - uint32_t RESERVED2: 22; - }; - uint32_t Word; -} IAP_CON_Typedef; - -typedef union -{ - struct - { - uint32_t RESERVED0: 2; - uint32_t IAPCA: 8; - uint32_t IAPPA: 7; - uint32_t RESERVED1: 3; - uint32_t IFREN: 1; - uint32_t RESERVED2: 11; - }; - uint32_t Word; -} IAP_ADDR_Typedef; - -typedef union -{ - struct - { - uint32_t DATA: 32; - }; - uint32_t Word; -} IAP_DATA_Typedef; - -typedef union -{ - struct - { - uint32_t TRIG: 32; - }; - uint32_t Word; -} IAP_TRIG_Typedef; - -typedef union -{ - struct - { - uint32_t UL: 32; - }; - uint32_t Word; -} IAP_UL_Typedef; - -typedef union -{ - struct - { - uint32_t BSY: 1; - uint32_t PERASE_END: 1; - uint32_t PROG_END: 1; - uint32_t TIMEOUT_ERR: 1; - uint32_t OP_ERR: 1; - uint32_t MERASE_END: 1; - uint32_t UERASE_END: 1; - uint32_t RESERVED0: 25; - }; - uint32_t Word; -} IAP_STA_Typedef; - -typedef union -{ - struct - { - uint32_t IAP_WPROT: 32; - }; - uint32_t Word; -} IAP_WPROT0_Typedef; - -typedef union -{ - struct - { - uint32_t IAP_WPROT: 32; - }; - uint32_t Word; -} IAP_WPROT1_Typedef; - -typedef union -{ - struct - { - uint32_t IAP_WPROT: 1; - uint32_t RESERVED0: 31; - }; - uint32_t Word; -} IAP_WPROT2_Typedef; - -typedef struct -{ - __IO IAP_CON_Typedef CON; - __IO IAP_ADDR_Typedef ADDR; - __IO IAP_DATA_Typedef DATA; - __IO IAP_TRIG_Typedef TRIG; - __IO IAP_UL_Typedef UL; - __IO IAP_STA_Typedef STA; - __IO IAP_WPROT0_Typedef WPROT0; - __IO IAP_WPROT1_Typedef WPROT1; - __IO IAP_WPROT2_Typedef WPROT2; -} IAP_TypeDef; - -typedef union -{ - struct - { - uint32_t DR: 12; - uint32_t RESERVED0: 20; - }; - uint32_t Word; -} ADC_DR_Typedef; - -typedef union -{ - struct - { - uint32_t EN: 1; - uint32_t TRIG: 1; - uint32_t ACP_EN: 1; - uint32_t RESERVED0: 1; - uint32_t BIT_SEL: 2; - uint32_t RESERVED1: 26; - }; - uint32_t Word; -} ADC_CON0_Typedef; - -typedef union -{ - struct - { - uint32_t CLKDIV: 3; - uint32_t RESERVED0: 1; - uint32_t CLKS: 2; - uint32_t RESERVED1: 2; - uint32_t VREFP: 2; - uint32_t VREFN: 1; - uint32_t VRBUF_EN: 1; - uint32_t SMPS: 1; - uint32_t SMPON: 1; - uint32_t HSEN: 1; - uint32_t RESERVED2: 1; - uint32_t ST: 5; - uint32_t RESERVED3: 3; - uint32_t VCMBUF_EN: 1; - uint32_t VCMBUF_HS: 1; - uint32_t RESERVED4: 6; - }; - uint32_t Word; -} ADC_CON1_Typedef; - -typedef union -{ - struct - { - uint32_t CHS: 5; - uint32_t RESERVED0: 3; - uint32_t VDD5_FLAG_EN: 1; - uint32_t RESERVED1: 23; - }; - uint32_t Word; -} ADC_CHS_Typedef; - -typedef union -{ - struct - { - uint32_t IE: 1; - uint32_t ACPMINIE: 1; - uint32_t ACPMAXIE: 1; - uint32_t ACPOVIE: 1; - uint32_t RESERVED0: 28; - }; - uint32_t Word; -} ADC_IE_Typedef; - -typedef union -{ - struct - { - uint32_t IF: 1; - uint32_t ACPMINIF: 1; - uint32_t ACPMAXIF: 1; - uint32_t ACPOVIF: 1; - uint32_t RESERVED0: 28; - }; - uint32_t Word; -} ADC_IF_Typedef; - -typedef union -{ - struct - { - uint32_t OVFL_TIME: 12; - uint32_t RESERVED0: 4; - uint32_t TIMES: 2; - uint32_t RESERVED1: 2; - uint32_t CLKS: 1; - uint32_t RESERVED2: 11; - }; - uint32_t Word; -} ADC_ACPC_Typedef; - -typedef union -{ - struct - { - uint32_t CMP_MIN: 12; - uint32_t RESERVED0: 4; - uint32_t CMP_MAX: 12; - uint32_t RESERVED1: 4; - }; - uint32_t Word; -} ADC_ACPCMP_Typedef; - -typedef union -{ - struct - { - uint32_t MEAN_DATA: 12; - uint32_t RESERVED0: 20; - }; - uint32_t Word; -} ADC_ACPMEAN_Typedef; - -typedef union -{ - struct - { - uint32_t VREF_EN: 1; - uint32_t RESERVED2: 1; - uint32_t IREF_EN: 1; - uint32_t RESERVED0: 1; - uint32_t VDET_EN: 1; - uint32_t VDET_SEL: 1; - uint32_t RESERVED1: 26; - }; - uint32_t Word; -} ADC_VREFCON_Typedef; - -typedef struct -{ - __I ADC_DR_Typedef DR; - __IO ADC_CON0_Typedef CON0; - __IO ADC_CON1_Typedef CON1; - __IO ADC_CHS_Typedef CHS; - __IO ADC_IE_Typedef IE; - __IO ADC_IF_Typedef IF; - uint32_t RESERVED0[4] ; - __IO ADC_ACPC_Typedef ACPC; - uint32_t RESERVED1 ; - __IO ADC_ACPCMP_Typedef ACPCMP; - __I ADC_ACPMEAN_Typedef ACPMEAN; - uint32_t RESERVED2[2] ; - __IO ADC_VREFCON_Typedef VREFCON; -} ADC_TypeDef; - -typedef union -{ - struct - { - uint32_t TMUP: 1; - uint32_t TMWR: 1; - uint32_t HSWI: 1; - uint32_t RESERVED0: 1; - uint32_t CLKS: 2; - uint32_t XST: 1; - uint32_t PON: 1; - uint32_t RESERVED1: 24; - }; - uint32_t Word; -} RTC_CON_Typedef; - -typedef union -{ - struct - { - uint32_t CALF: 8; - uint32_t DEV: 1; - uint32_t COCR: 3; - uint32_t CLKC: 1; - uint32_t RESERVED0: 19; - }; - uint32_t Word; -} RTC_CAL_Typedef; - -typedef union -{ - struct - { - uint32_t WM: 7; - uint32_t RESERVED0: 1; - uint32_t WH: 6; - uint32_t RESERVED1: 2; - uint32_t WW: 7; - uint32_t RESERVED2: 9; - }; - uint32_t Word; -} RTC_WA_Typedef; - -typedef union -{ - struct - { - uint32_t DM: 7; - uint32_t RESERVED0: 1; - uint32_t DH: 6; - uint32_t RESERVED1: 18; - }; - uint32_t Word; -} RTC_DA_Typedef; - -typedef union -{ - struct - { - uint32_t SEC: 7; - uint32_t RESERVED0: 1; - uint32_t MIN: 7; - uint32_t RESERVED1: 1; - uint32_t HOUR: 6; - uint32_t RESERVED2: 10; - }; - uint32_t Word; -} RTC_HMS_Typedef; - -typedef union -{ - struct - { - uint32_t WEEK: 7; - uint32_t RESERVED0: 1; - uint32_t DAY: 6; - uint32_t RESERVED1: 2; - uint32_t MON: 5; - uint32_t RESERVED2: 3; - uint32_t YEAR: 8; - }; - uint32_t Word; -} RTC_YMDW_Typedef; - -typedef union -{ - struct - { - uint32_t SCDIE: 1; - uint32_t MINIE: 1; - uint32_t HORIE: 1; - uint32_t DAYIE: 1; - uint32_t MONIE: 1; - uint32_t RESERVED0: 3; - uint32_t DALE: 1; - uint32_t WALE: 1; - uint32_t RESERVED1: 22; - }; - uint32_t Word; -} RTC_IE_Typedef; - -typedef union -{ - struct - { - uint32_t SCDIF: 1; - uint32_t MINIF: 1; - uint32_t HORIF: 1; - uint32_t DAYIF: 1; - uint32_t MONIF: 1; - uint32_t RESERVED0: 3; - uint32_t DAFG: 1; - uint32_t WAFG: 1; - uint32_t RESERVED1: 22; - }; - uint32_t Word; -} RTC_IF_Typedef; - -typedef union -{ - struct - { - uint32_t WP: 32; - }; - uint32_t Word; -} RTC_WP_Typedef; - -typedef struct -{ - __IO RTC_CON_Typedef CON; - __IO RTC_CAL_Typedef CAL; - __IO RTC_WA_Typedef WA; - __IO RTC_DA_Typedef DA; - __IO RTC_HMS_Typedef HMS; - __IO RTC_YMDW_Typedef YMDW; - __IO RTC_IE_Typedef IE; - __IO RTC_IF_Typedef IF; - __IO RTC_WP_Typedef WP; -} RTC_TypeDef; - -typedef union -{ - struct - { - uint32_t LOAD: 32; - }; - uint32_t Word; -} IWDT_LOAD_Typedef; - -typedef union -{ - struct - { - uint32_t VALUE: 32; - }; - uint32_t Word; -} IWDT_VALUE_Typedef; - -typedef union -{ - struct - { - uint32_t EN: 1; - uint32_t IE: 1; - uint32_t RSTEN: 1; - uint32_t CLKS: 1; - uint32_t RESERVED0: 28; - }; - uint32_t Word; -} IWDT_CON_Typedef; - -typedef union -{ - struct - { - uint32_t INTCLR: 32; - }; - uint32_t Word; -} IWDT_INTCLR_Typedef; - -typedef union -{ - struct - { - uint32_t WDTIF: 1; - uint32_t RESERVED0: 31; - }; - uint32_t Word; -} IWDT_RIS_Typedef; - -typedef union -{ - struct - { - uint32_t LOCK: 1; - uint32_t RESERVED0: 31; - }; - uint32_t Word; -} IWDT_LOCK_Typedef; - -typedef struct -{ - __O IWDT_LOAD_Typedef LOAD; - __I IWDT_VALUE_Typedef VALUE; - __IO IWDT_CON_Typedef CON; - __O IWDT_INTCLR_Typedef INTCLR; - __I IWDT_RIS_Typedef RIS; - uint32_t RESERVED0[59] ; - __IO IWDT_LOCK_Typedef LOCK; -} IWDT_TypeDef; - -typedef union -{ - struct - { - uint32_t LOAD: 32; - }; - uint32_t Word; -} WWDT_LOAD_Typedef; - -typedef union -{ - struct - { - uint32_t VALUE: 32; - }; - uint32_t Word; -} WWDT_VALUE_Typedef; - -typedef union -{ - struct - { - uint32_t EN: 1; - uint32_t IE: 1; - uint32_t RSTEN: 1; - uint32_t CLKS: 1; - uint32_t WWDTWIN: 2; - uint32_t RESERVED0: 26; - }; - uint32_t Word; -} WWDT_CON_Typedef; - -typedef union -{ - struct - { - uint32_t INTCLR: 32; - }; - uint32_t Word; -} WWDT_INTCLR_Typedef; - -typedef union -{ - struct - { - uint32_t WWDTIF: 1; - uint32_t RESERVED0: 31; - }; - uint32_t Word; -} WWDT_RIS_Typedef; - -typedef union -{ - struct - { - uint32_t LOCK: 1; - uint32_t RESERVED0: 31; - }; - uint32_t Word; -} WWDT_LOCK_Typedef; - -typedef struct -{ - __O WWDT_LOAD_Typedef LOAD; - __I WWDT_VALUE_Typedef VALUE; - __IO WWDT_CON_Typedef CON; - __O WWDT_INTCLR_Typedef INTCLR; - __I WWDT_RIS_Typedef RIS; - uint32_t RESERVED0[59] ; - __IO WWDT_LOCK_Typedef LOCK; -} WWDT_TypeDef; - -typedef union -{ - struct - { - uint32_t CNT: 16; - uint32_t RESERVED0: 16; - }; - uint32_t Word; -} T16N_CNT_Typedef; - -typedef union -{ - struct - { - uint32_t PRECNT: 8; - uint32_t RESERVED0: 24; - }; - uint32_t Word; -} T16N_PRECNT_Typedef; - -typedef union -{ - struct - { - uint32_t PREMAT: 8; - uint32_t RESERVED0: 24; - }; - uint32_t Word; -} T16N_PREMAT_Typedef; - -typedef union -{ - struct - { - uint32_t EN: 1; - uint32_t CS: 2; - uint32_t SYNC: 1; - uint32_t EDGE: 2; - uint32_t MOD: 2; - uint32_t MAT0S: 2; - uint32_t MAT1S: 2; - uint32_t MAT2S: 2; - uint32_t MAT3S: 2; - uint32_t ASYWEN: 1; - uint32_t RESERVED0: 15; - }; - uint32_t Word; -} T16N_CON0_Typedef; - -typedef union -{ - struct - { - uint32_t CAPPE: 1; - uint32_t CAPNE: 1; - uint32_t CAPIS0: 1; - uint32_t CAPIS1: 1; - uint32_t CAPT: 4; - uint32_t CAPL0: 1; - uint32_t CAPL1: 1; - uint32_t RESERVED0: 22; - }; - uint32_t Word; -} T16N_CON1_Typedef; - -typedef union -{ - struct - { - uint32_t MOE0: 1; - uint32_t MOE1: 1; - uint32_t POL0: 1; - uint32_t POL1: 1; - uint32_t MOM0: 2; - uint32_t MOM1: 2; - uint32_t MOM2: 2; - uint32_t MOM3: 2; - uint32_t PBKEN: 1; - uint32_t PBKPS: 1; - uint32_t PBKF: 1; - uint32_t RESERVED0: 1; - uint32_t PBKS: 3; - uint32_t RESERVED1: 1; - uint32_t PBKL0: 1; - uint32_t PBKL1: 1; - uint32_t RESERVED2: 10; - }; - uint32_t Word; -} T16N_CON2_Typedef; - -typedef union -{ - struct - { - uint32_t MAT0IE: 1; - uint32_t MAT1IE: 1; - uint32_t MAT2IE: 1; - uint32_t MAT3IE: 1; - uint32_t OVIE: 1; - uint32_t CAP0IE: 1; - uint32_t CAP1IE: 1; - uint32_t PBKIE: 1; - uint32_t RESERVED0: 24; - }; - uint32_t Word; -} T16N_IE_Typedef; - -typedef union -{ - struct - { - uint32_t MAT0IF: 1; - uint32_t MAT1IF: 1; - uint32_t MAT2IF: 1; - uint32_t MAT3IF: 1; - uint32_t OVIF: 1; - uint32_t CAP0IF: 1; - uint32_t CAP1IF: 1; - uint32_t PBKIF: 1; - uint32_t RESERVED0: 24; - }; - uint32_t Word; -} T16N_IF_Typedef; - -typedef union -{ - struct - { - uint32_t MAT0TAR: 1; - uint32_t MAT1TAR: 1; - uint32_t MAT2TAR: 1; - uint32_t MAT3TAR: 1; - uint32_t OVTAR: 1; - uint32_t RESERVED0: 27; - }; - uint32_t Word; -} T16N_TRG_Typedef; - -typedef union -{ - struct - { - uint32_t MAT0: 16; - uint32_t RESERVED0: 16; - }; - uint32_t Word; -} T16N_MAT0_Typedef; - -typedef union -{ - struct - { - uint32_t MAT1: 16; - uint32_t RESERVED0: 16; - }; - uint32_t Word; -} T16N_MAT1_Typedef; - -typedef union -{ - struct - { - uint32_t MAT2: 16; - uint32_t RESERVED0: 16; - }; - uint32_t Word; -} T16N_MAT2_Typedef; - -typedef union -{ - struct - { - uint32_t MAT3: 16; - uint32_t RESERVED0: 16; - }; - uint32_t Word; -} T16N_MAT3_Typedef; - -typedef struct -{ - __IO T16N_CNT_Typedef CNT; - uint32_t RESERVED0; - __IO T16N_PRECNT_Typedef PRECNT; - __IO T16N_PREMAT_Typedef PREMAT; - __IO T16N_CON0_Typedef CON0; - __IO T16N_CON1_Typedef CON1; - __IO T16N_CON2_Typedef CON2; - uint32_t RESERVED1; - __IO T16N_IE_Typedef IE; - __IO T16N_IF_Typedef IF; - __IO T16N_TRG_Typedef TRG; - uint32_t RESERVED2; - __IO T16N_MAT0_Typedef MAT0; - __IO T16N_MAT1_Typedef MAT1; - __IO T16N_MAT2_Typedef MAT2; - __IO T16N_MAT3_Typedef MAT3; -} T16N_TypeDef; - -typedef union -{ - struct - { - uint32_t CNT: 32; - }; - uint32_t Word; -} T32N_CNT_Typedef; - -typedef union -{ - struct - { - uint32_t PRECNT: 8; - uint32_t RESERVED0: 24; - }; - uint32_t Word; -} T32N_PRECNT_Typedef; - -typedef union -{ - struct - { - uint32_t PREMAT: 8; - uint32_t RESERVED0: 24; - }; - uint32_t Word; -} T32N_PREMAT_Typedef; - -typedef union -{ - struct - { - uint32_t EN: 1; - uint32_t CS: 2; - uint32_t SYNC: 1; - uint32_t EDGE: 2; - uint32_t MOD: 2; - uint32_t MAT0S: 2; - uint32_t MAT1S: 2; - uint32_t MAT2S: 2; - uint32_t MAT3S: 2; - uint32_t ASYNC_WREN: 1; - uint32_t RESERVED0: 15; - }; - uint32_t Word; -} T32N_CON0_Typedef; - -typedef union -{ - struct - { - uint32_t CAPPE: 1; - uint32_t CAPNE: 1; - uint32_t CAPIS0: 1; - uint32_t CAPIS1: 1; - uint32_t CAPT: 4; - uint32_t CAPL0: 1; - uint32_t CAPL1: 1; - uint32_t RESERVED0: 22; - }; - uint32_t Word; -} T32N_CON1_Typedef; - -typedef union -{ - struct - { - uint32_t MOE0: 1; - uint32_t MOE1: 1; - uint32_t POL0: 1; - uint32_t POL1: 1; - uint32_t MOM0: 2; - uint32_t MOM1: 2; - uint32_t MOM2: 2; - uint32_t MOM3: 2; - uint32_t RESERVED0: 20; - }; - uint32_t Word; -} T32N_CON2_Typedef; - -typedef union -{ - struct - { - uint32_t MAT0IE: 1; - uint32_t MAT1IE: 1; - uint32_t MAT2IE: 1; - uint32_t MAT3IE: 1; - uint32_t OVIE: 1; - uint32_t CAP0IE: 1; - uint32_t CAP1IE: 1; - uint32_t RESERVED0: 25; - }; - uint32_t Word; -} T32N_IE_Typedef; - -typedef union -{ - struct - { - uint32_t MAT0IF: 1; - uint32_t MAT1IF: 1; - uint32_t MAT2IF: 1; - uint32_t MAT3IF: 1; - uint32_t OVIF: 1; - uint32_t CAP0IF: 1; - uint32_t CAP1IF: 1; - uint32_t RESERVED0: 25; - }; - uint32_t Word; -} T32N_IF_Typedef; - -typedef union -{ - struct - { - uint32_t MAT0TAR: 1; - uint32_t MAT1TAR: 1; - uint32_t MAT2TAR: 1; - uint32_t MAT3TAR: 1; - uint32_t OVTAR: 1; - uint32_t RESERVED0: 27; - }; - uint32_t Word; -} T32N_TRG_Typedef; - -typedef union -{ - struct - { - uint32_t MAT0: 32; - }; - uint32_t Word; -} T32N_MAT0_Typedef; - -typedef union -{ - struct - { - uint32_t MAT1: 32; - }; - uint32_t Word; -} T32N_MAT1_Typedef; - -typedef union -{ - struct - { - uint32_t MAT2: 32; - }; - uint32_t Word; -} T32N_MAT2_Typedef; - -typedef union -{ - struct - { - uint32_t MAT3: 32; - }; - uint32_t Word; -} T32N_MAT3_Typedef; - -typedef struct -{ - __IO T32N_CNT_Typedef CNT; - uint32_t RESERVED0; - __IO T32N_PRECNT_Typedef PRECNT; - __IO T32N_PREMAT_Typedef PREMAT; - __IO T32N_CON0_Typedef CON0; - __IO T32N_CON1_Typedef CON1; - __IO T32N_CON2_Typedef CON2; - uint32_t RESERVED1; - __IO T32N_IE_Typedef IE; - __IO T32N_IF_Typedef IF; - __IO T32N_TRG_Typedef TRG; - uint32_t RESERVED2; - __IO T32N_MAT0_Typedef MAT0; - __IO T32N_MAT1_Typedef MAT1; - __IO T32N_MAT2_Typedef MAT2; - __IO T32N_MAT3_Typedef MAT3; -} T32N_TypeDef; - -typedef union -{ - struct - { - uint32_t TXEN: 1; - uint32_t TRST: 1; - uint32_t TXFS: 1; - uint32_t RESERVED0: 1; - uint32_t TXMOD: 3; - uint32_t TXP: 1; - uint32_t RXEN: 1; - uint32_t RRST: 1; - uint32_t RESERVED1: 2; - uint32_t RXMOD: 3; - uint32_t RXP: 1; - uint32_t RESERVED2: 12; - uint32_t BCS: 3; - uint32_t RESERVED3: 1; - }; - uint32_t Word; -} UART_CON_Typedef; - -typedef union -{ - struct - { - uint32_t BRR: 11; - uint32_t RESERVED0: 21; - }; - uint32_t Word; -} UART_BRR_Typedef; - -typedef union -{ - uint8_t Byte[4]; - uint16_t HalfWord[2]; - uint32_t Word; -} UART_TBW_Typedef; - -typedef union -{ - uint8_t Byte[4]; - uint16_t HalfWord[2]; - uint32_t Word; -} UART_RBR_Typedef; - -typedef union -{ - struct - { - uint32_t TB0: 9; - uint32_t RESERVED0: 3; - uint32_t TP0: 1; - uint32_t TBEF0: 1; - uint32_t RESERVED1: 2; - uint32_t TB1: 9; - uint32_t RESERVED2: 3; - uint32_t TP1: 1; - uint32_t TBEF1: 1; - uint32_t RESERVED3: 2; - }; - uint32_t Word; -} UART_TB01_Typedef; - -typedef union -{ - struct - { - uint32_t TB2: 9; - uint32_t RESERVED0: 3; - uint32_t TP2: 1; - uint32_t TBEF2: 1; - uint32_t RESERVED1: 2; - uint32_t TB3: 9; - uint32_t RESERVED2: 3; - uint32_t TP3: 1; - uint32_t TBEF3: 1; - uint32_t RESERVED3: 2; - }; - uint32_t Word; -} UART_TB23_Typedef; - -typedef union -{ - struct - { - uint32_t RB0: 9; - uint32_t RESERVED0: 3; - uint32_t RP0: 1; - uint32_t RBFF0: 1; - uint32_t FE0: 1; - uint32_t PE0: 1; - uint32_t RB1: 9; - uint32_t RESERVED1: 3; - uint32_t RP1: 1; - uint32_t RBFF1: 1; - uint32_t FE1: 1; - uint32_t PE1: 1; - }; - uint32_t Word; -} UART_RB01_Typedef; - -typedef union -{ - struct - { - uint32_t RB2: 9; - uint32_t RESERVED0: 3; - uint32_t RP2: 1; - uint32_t RBFF2: 1; - uint32_t FE2: 1; - uint32_t PE2: 1; - uint32_t RB3: 9; - uint32_t RESERVED1: 3; - uint32_t RP3: 1; - uint32_t RBFF3: 1; - uint32_t FE3: 1; - uint32_t PE3: 1; - }; - uint32_t Word; -} UART_RB23_Typedef; - -typedef union -{ - struct - { - uint32_t TBIE: 1; - uint32_t RBIE: 1; - uint32_t ROIE: 1; - uint32_t FEIE: 1; - uint32_t PEIE: 1; - uint32_t TBEIE: 1; - uint32_t RESERVED0: 2; - uint32_t TBIM: 2; - uint32_t RBIM: 2; - uint32_t TIDIE: 1; - uint32_t RIDIE: 1; - uint32_t RESERVED1: 18; - }; - uint32_t Word; -} UART_IE_Typedef; - -typedef union -{ - struct - { - uint32_t TBIF: 1; - uint32_t RBIF: 1; - uint32_t ROIF: 1; - uint32_t FEIF: 1; - uint32_t PEIF: 1; - uint32_t TBEIF: 1; - uint32_t RESERVED0: 6; - uint32_t TIDIF: 1; - uint32_t RIDIF: 1; - uint32_t RESERVED1: 18; - }; - uint32_t Word; -} UART_IF_Typedef; - -typedef struct -{ - __IO UART_CON_Typedef CON; - __IO UART_BRR_Typedef BRR; - __O UART_TBW_Typedef TBW; - __I UART_RBR_Typedef RBR; - __I UART_TB01_Typedef TB01; - __I UART_TB23_Typedef TB23; - __I UART_RB01_Typedef RB01; - __I UART_RB23_Typedef RB23; - __IO UART_IE_Typedef IE; - __IO UART_IF_Typedef IF; -} UART_TypeDef; - -typedef union -{ - struct - { - uint32_t EN: 1; - uint32_t RST: 1; - uint32_t MS: 1; - uint32_t REN: 1; - uint32_t RESERVED0: 1; - uint32_t DRE: 1; - uint32_t DFS: 2; - uint32_t RESERVED1: 8; - uint32_t TME: 1; - uint32_t TMS: 1; - uint32_t TMP: 6; - uint32_t DW: 3; - uint32_t RESERVED2: 3; - uint32_t TXCLR: 1; - uint32_t RXCLR: 1; - }; - uint32_t Word; -} SPI_CON_Typedef; - -typedef union -{ - uint8_t Byte[4]; - uint16_t HalfWord[2]; - uint32_t Word; -} SPI_TBW_Typedef; - -typedef union -{ - uint8_t Byte[4]; - uint16_t HalfWord[2]; - uint32_t Word; -} SPI_RBR_Typedef; - -typedef union -{ - struct - { - uint32_t TBIE: 1; - uint32_t RBIE: 1; - uint32_t TEIE: 1; - uint32_t ROIE: 1; - uint32_t IDIE: 1; - uint32_t NSSIE: 1; - uint32_t TBWEIE: 1; - uint32_t RESERVED0: 1; - uint32_t TBIM: 2; - uint32_t RBIM: 2; - uint32_t RESERVED1: 20; - }; - uint32_t Word; -} SPI_IE_Typedef; - -typedef union -{ - struct - { - uint32_t TBIF: 1; - uint32_t RBIF: 1; - uint32_t TEIF: 1; - uint32_t ROIF: 1; - uint32_t IDIF: 1; - uint32_t NSSIF: 1; - uint32_t TBWEIF: 1; - uint32_t RESERVED0: 25; - }; - uint32_t Word; -} SPI_IF_Typedef; - -typedef union -{ - struct - { - uint32_t TB0: 8; - uint32_t TB1: 8; - uint32_t TB2: 8; - uint32_t TB3: 8; - }; - uint32_t Word; -} SPI_TB_Typedef; - -typedef union -{ - struct - { - uint32_t RB0: 8; - uint32_t RB1: 8; - uint32_t RB2: 8; - uint32_t RB3: 8; - }; - uint32_t Word; -} SPI_RB_Typedef; - -typedef union -{ - struct - { - uint32_t RESERVED0: 7; - uint32_t NSS: 1; - uint32_t TBEF0: 1; - uint32_t TBEF1: 1; - uint32_t TBEF2: 1; - uint32_t TBEF3: 1; - uint32_t RBFF0: 1; - uint32_t RBFF1: 1; - uint32_t RBFF2: 1; - uint32_t RBFF3: 1; - uint32_t IDLE: 1; - uint32_t RESERVED1: 15; - }; - uint32_t Word; -} SPI_STA_Typedef; - -typedef union -{ - struct - { - uint32_t CKS: 10; - uint32_t RESERVED0: 22; - }; - uint32_t Word; -} SPI_CKS_Typedef; - -typedef struct -{ - __IO SPI_CON_Typedef CON; - uint32_t RESERVED0 ; - __O SPI_TBW_Typedef TBW; - __I SPI_RBR_Typedef RBR; - __IO SPI_IE_Typedef IE; - __IO SPI_IF_Typedef IF; - __I SPI_TB_Typedef TB; - __I SPI_RB_Typedef RB; - __I SPI_STA_Typedef STA; - __IO SPI_CKS_Typedef CKS; -} SPI_TypeDef; - -typedef union -{ - struct - { - uint32_t EN: 1; - uint32_t RST: 1; - uint32_t SCKOD: 1; - uint32_t SDAOD: 1; - uint32_t SCKSE: 1; - uint32_t SDASE: 1; - uint32_t RESERVED0: 1; - uint32_t TJE: 1; - uint32_t TJP: 8; - uint32_t RW: 1; - uint32_t SA: 7; - uint32_t RESERVED1: 8; - }; - uint32_t Word; -} I2C_CON_Typedef; - -typedef union -{ - struct - { - uint32_t MS: 1; - uint32_t RDM: 3; - uint32_t CSE: 1; - uint32_t ANAE: 1; - uint32_t SRAE: 1; - uint32_t SPAE: 1; - uint32_t ADLY: 3; - uint32_t ADE: 1; - uint32_t TIS: 4; - uint32_t SRT: 1; - uint32_t SPT: 1; - uint32_t RDT: 1; - uint32_t BLD: 1; - uint32_t RESERVED0: 4; - uint32_t TAS: 1; - uint32_t RESERVED1: 7; - }; - uint32_t Word; -} I2C_MOD_Typedef; - -typedef union -{ - struct - { - uint32_t SRIE: 1; - uint32_t SPIE: 1; - uint32_t TBIE: 1; - uint32_t RBIE: 1; - uint32_t TEIE: 1; - uint32_t ROIE: 1; - uint32_t NAIE: 1; - uint32_t TBWEIE: 1; - uint32_t TBIM: 2; - uint32_t RBIM: 2; - uint32_t TIDLEIE: 1; - uint32_t RESERVED0: 19; - }; - uint32_t Word; -} I2C_IE_Typedef; - -typedef union -{ - struct - { - uint32_t SRIF: 1; - uint32_t SPIF: 1; - uint32_t TBIF: 1; - uint32_t RBIF: 1; - uint32_t TEIF: 1; - uint32_t ROIF: 1; - uint32_t NAIF: 1; - uint32_t TBWEIF: 1; - uint32_t RESERVED0: 4; - uint32_t TIDLEIF: 1; - uint32_t RESERVED1: 19; - }; - uint32_t Word; -} I2C_IF_Typedef; - -typedef union -{ - uint8_t Byte[4]; - uint16_t HalfWord[2]; - uint32_t Word; -} I2C_TBW_Typedef; - -typedef union -{ - uint8_t Byte[4]; - uint16_t HalfWord[2]; - uint32_t Word; -} I2C_RBR_Typedef; - -typedef union -{ - struct - { - uint32_t TB0: 8; - uint32_t TB1: 8; - uint32_t TB2: 8; - uint32_t TB3: 8; - }; - uint32_t Word; -} I2C_TB_Typedef; - -typedef union -{ - struct - { - uint32_t RB0: 8; - uint32_t RB1: 8; - uint32_t RB2: 8; - uint32_t RB3: 8; - }; - uint32_t Word; -} I2C_RB_Typedef; - -typedef union -{ - struct - { - uint32_t RESERVED0: 8; - uint32_t TBEF0: 1; - uint32_t TBEF1: 1; - uint32_t TBEF2: 1; - uint32_t TBEF3: 1; - uint32_t RBFF0: 1; - uint32_t RBFF1: 1; - uint32_t RBFF2: 1; - uint32_t RBFF3: 1; - uint32_t ACK: 1; - uint32_t IDLE: 1; - uint32_t RESERVED1: 14; - }; - uint32_t Word; -} I2C_STA_Typedef; - -typedef struct -{ - __IO I2C_CON_Typedef CON; - __IO I2C_MOD_Typedef MOD; - __IO I2C_IE_Typedef IE; - __IO I2C_IF_Typedef IF; - __O I2C_TBW_Typedef TBW; - __I I2C_RBR_Typedef RBR; - __I I2C_TB_Typedef TB; - __I I2C_RB_Typedef RB; - __I I2C_STA_Typedef STA; -} I2C_TypeDef; - -typedef union -{ - struct - { - uint32_t AES_DATA0: 32; - }; - uint32_t Word; -} AES_DATA0_Typedef; - -typedef union -{ - struct - { - uint32_t AES_DATA1: 32; - }; - uint32_t Word; -} AES_DATA1_Typedef; - -typedef union -{ - struct - { - uint32_t AES_DATA2: 32; - }; - uint32_t Word; -} AES_DATA2_Typedef; - -typedef union -{ - struct - { - uint32_t AES_DATA3: 32; - }; - uint32_t Word; -} AES_DATA3_Typedef; - -typedef union -{ - struct - { - uint32_t AES_KEY0: 32; - }; - uint32_t Word; -} AES_KEY0_Typedef; - -typedef union -{ - struct - { - uint32_t AES_KEY1: 32; - }; - uint32_t Word; -} AES_KEY1_Typedef; - -typedef union -{ - struct - { - uint32_t AES_KEY2: 32; - }; - uint32_t Word; -} AES_KEY2_Typedef; - -typedef union -{ - struct - { - uint32_t AES_KEY3: 32; - }; - uint32_t Word; -} AES_KEY3_Typedef; - -typedef union -{ - struct - { - uint32_t GO_DONE: 1; - uint32_t ENCRYPT: 1; - uint32_t RESERVED0: 4; - uint32_t IE: 1; - uint32_t IF: 1; - uint32_t RESERVED1: 24; - }; - uint32_t Word; -} AES_CON_Typedef; - -typedef struct -{ - __IO AES_DATA0_Typedef DATA0; - __IO AES_DATA1_Typedef DATA1; - __IO AES_DATA2_Typedef DATA2; - __IO AES_DATA3_Typedef DATA3; - __IO AES_KEY0_Typedef KEY0; - __IO AES_KEY1_Typedef KEY1; - __IO AES_KEY2_Typedef KEY2; - __IO AES_KEY3_Typedef KEY3; - __IO AES_CON_Typedef CON; -} AES_TypeDef; - -/******************************************************************************/ -/* 物理地址映射 */ -/******************************************************************************/ - -/* Base addresses */ -#define FLASH_BASE (0x00000000UL) -#define SRAM_BASE (0x20000000UL) -#define APB_BASE (0x40000000UL) -#define RAM_BASE (0x60000000UL) - -/* APB peripherals */ -#define SCU_BASE (APB_BASE + 0x00000) -#define CRC_BASE (APB_BASE + 0x00C00) -#define GPIO_BASE (APB_BASE + 0x20000) -#define IAP_BASE (APB_BASE + 0x00800) -#define ADC_BASE (APB_BASE + 0x01000) -#define RTC_BASE (APB_BASE + 0x01400) -#define IWDT_BASE (APB_BASE + 0x01C00) -#define WWDT_BASE (APB_BASE + 0x01800) -#define T16N0_BASE (APB_BASE + 0x02000) -#define T16N1_BASE (APB_BASE + 0x02400) -#define T16N2_BASE (APB_BASE + 0x02800) -#define T16N3_BASE (APB_BASE + 0x02C00) -#define T32N0_BASE (APB_BASE + 0x04000) -#define UART0_BASE (APB_BASE + 0x06000) -#define UART1_BASE (APB_BASE + 0x06400) -#define UART2_BASE (APB_BASE + 0x06800) -#define UART3_BASE (APB_BASE + 0x06C00) -#define UART4_BASE (APB_BASE + 0x07000) -#define UART5_BASE (APB_BASE + 0x07400) -#define SPI0_BASE (APB_BASE + 0x08000) -#define I2C0_BASE (APB_BASE + 0x09000) -#define AES_BASE (APB_BASE + 0x0A000) - -/******************************************************************************/ -/* 外设定义 */ -/******************************************************************************/ -#define SCU ((SCU_TypeDef *) SCU_BASE ) -#define CRC ((CRC_TypeDef *) CRC_BASE ) -#define GPIO ((GPIO_TypeDef *) GPIO_BASE ) -#define IAP ((IAP_TypeDef *) IAP_BASE ) -#define ADC ((ADC_TypeDef *) ADC_BASE ) -#define RTC ((RTC_TypeDef *) RTC_BASE ) -#define IWDT ((IWDT_TypeDef *) IWDT_BASE ) -#define WWDT ((WWDT_TypeDef *) WWDT_BASE ) -#define T16N0 ((T16N_TypeDef *) T16N0_BASE ) -#define T16N1 ((T16N_TypeDef *) T16N1_BASE ) -#define T16N2 ((T16N_TypeDef *) T16N2_BASE ) -#define T16N3 ((T16N_TypeDef *) T16N3_BASE ) -#define T32N0 ((T32N_TypeDef *) T32N0_BASE ) -#define UART0 ((UART_TypeDef *) UART0_BASE ) -#define UART1 ((UART_TypeDef *) UART1_BASE ) -#define UART2 ((UART_TypeDef *) UART2_BASE ) -#define UART3 ((UART_TypeDef *) UART3_BASE ) -#define UART4 ((UART_TypeDef *) UART4_BASE ) -#define UART5 ((UART_TypeDef *) UART5_BASE ) -#define SPI0 ((SPI_TypeDef *) SPI0_BASE ) -#define I2C0 ((I2C_TypeDef *) I2C0_BASE ) -#define AES ((AES_TypeDef *) AES_BASE ) - - -#endif diff --git a/bsp/essemi/es8p508x/libraries/CMSIS/core_cm0.h b/bsp/essemi/es8p508x/libraries/CMSIS/core_cm0.h deleted file mode 100644 index e788e0a60a..0000000000 --- a/bsp/essemi/es8p508x/libraries/CMSIS/core_cm0.h +++ /dev/null @@ -1,668 +0,0 @@ -/**************************************************************************//** - * @file core_cm0.h - * @brief CMSIS Cortex-M0 Core Peripheral Access Layer Header File - * @version V3.02 - * @date 16. July 2012 - * - * @note - * Copyright (C) 2009-2012 ARM Limited. All rights reserved. - * - * @par - * ARM Limited (ARM) is supplying this software for use with Cortex-M - * processor based microcontrollers. This file can be freely distributed - * within development tools that are supporting such ARM based processors. - * - * @par - * THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED - * OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF - * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE. - * ARM SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR - * CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER. - * - ******************************************************************************/ -#if defined ( __ICCARM__ ) - #pragma system_include /* treat file as system include file for MISRA check */ -#endif - -#ifdef __cplusplus - extern "C" { -#endif - -#ifndef __CORE_CM0_H_GENERIC -#define __CORE_CM0_H_GENERIC - -/** \page CMSIS_MISRA_Exceptions MISRA-C:2004 Compliance Exceptions - CMSIS violates the following MISRA-C:2004 rules: - - \li Required Rule 8.5, object/function definition in header file.
- Function definitions in header files are used to allow 'inlining'. - - \li Required Rule 18.4, declaration of union type or object of union type: '{...}'.
- Unions are used for effective representation of core registers. - - \li Advisory Rule 19.7, Function-like macro defined.
- Function-like macros are used to allow more efficient code. - */ - - -/******************************************************************************* - * CMSIS definitions - ******************************************************************************/ -/** \ingroup Cortex_M0 - @{ - */ - -/* CMSIS CM0 definitions */ -#define __CM0_CMSIS_VERSION_MAIN (0x03) /*!< [31:16] CMSIS HAL main version */ -#define __CM0_CMSIS_VERSION_SUB (0x01) /*!< [15:0] CMSIS HAL sub version */ -#define __CM0_CMSIS_VERSION ((__CM0_CMSIS_VERSION_MAIN << 16) | \ - __CM0_CMSIS_VERSION_SUB ) /*!< CMSIS HAL version number */ - -#define __CORTEX_M (0x00) /*!< Cortex-M Core */ - - -#if defined ( __CC_ARM ) - #define __ASM __asm /*!< asm keyword for ARM Compiler */ - #define __INLINE __inline /*!< inline keyword for ARM Compiler */ - #define __STATIC_INLINE static __inline - -#elif defined ( __ICCARM__ ) - #define __ASM __asm /*!< asm keyword for IAR Compiler */ - #define __INLINE inline /*!< inline keyword for IAR Compiler. Only available in High optimization mode! */ - #define __STATIC_INLINE static inline - -#elif defined ( __GNUC__ ) - #define __ASM __asm /*!< asm keyword for GNU Compiler */ - #define __INLINE inline /*!< inline keyword for GNU Compiler */ - #define __STATIC_INLINE static inline - -#elif defined ( __TASKING__ ) - #define __ASM __asm /*!< asm keyword for TASKING Compiler */ - #define __INLINE inline /*!< inline keyword for TASKING Compiler */ - #define __STATIC_INLINE static inline - -#endif - -/** __FPU_USED indicates whether an FPU is used or not. This core does not support an FPU at all -*/ -#define __FPU_USED 0 - -#if defined ( __CC_ARM ) - #if defined __TARGET_FPU_VFP - #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" - #endif - -#elif defined ( __ICCARM__ ) - #if defined __ARMVFP__ - #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" - #endif - -#elif defined ( __GNUC__ ) - #if defined (__VFP_FP__) && !defined(__SOFTFP__) - #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" - #endif - -#elif defined ( __TASKING__ ) - #if defined __FPU_VFP__ - #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" - #endif -#endif - -#include /* standard types definitions */ -#include /* Core Instruction Access */ -#include /* Core Function Access */ - - -#endif /* __CORE_CM0_H_GENERIC */ - -#ifndef __CMSIS_GENERIC - -#ifndef __CORE_CM0_H_DEPENDANT -#define __CORE_CM0_H_DEPENDANT - -/* check device defines and use defaults */ -#if defined __CHECK_DEVICE_DEFINES - #ifndef __CM0_REV - #define __CM0_REV 0x0000 - #warning "__CM0_REV not defined in device header file; using default!" - #endif - - #ifndef __NVIC_PRIO_BITS - #define __NVIC_PRIO_BITS 2 - #warning "__NVIC_PRIO_BITS not defined in device header file; using default!" - #endif - - #ifndef __Vendor_SysTickConfig - #define __Vendor_SysTickConfig 0 - #warning "__Vendor_SysTickConfig not defined in device header file; using default!" - #endif -#endif - -/* IO definitions (access restrictions to peripheral registers) */ -/** - \defgroup CMSIS_glob_defs CMSIS Global Defines - - IO Type Qualifiers are used - \li to specify the access to peripheral variables. - \li for automatic generation of peripheral register debug information. -*/ -#ifdef __cplusplus - #define __I volatile /*!< Defines 'read only' permissions */ -#else - #define __I volatile const /*!< Defines 'read only' permissions */ -#endif -#define __O volatile /*!< Defines 'write only' permissions */ -#define __IO volatile /*!< Defines 'read / write' permissions */ - -/*@} end of group Cortex_M0 */ - - - -/******************************************************************************* - * Register Abstraction - Core Register contain: - - Core Register - - Core NVIC Register - - Core SCB Register - - Core SysTick Register - ******************************************************************************/ -/** \defgroup CMSIS_core_register Defines and Type Definitions - \brief Type definitions and defines for Cortex-M processor based devices. -*/ - -/** \ingroup CMSIS_core_register - \defgroup CMSIS_CORE Status and Control Registers - \brief Core Register type definitions. - @{ - */ - -/** \brief Union type to access the Application Program Status Register (APSR). - */ -typedef union -{ - struct - { -#if (__CORTEX_M != 0x04) - uint32_t _reserved0:27; /*!< bit: 0..26 Reserved */ -#else - uint32_t _reserved0:16; /*!< bit: 0..15 Reserved */ - uint32_t GE:4; /*!< bit: 16..19 Greater than or Equal flags */ - uint32_t _reserved1:7; /*!< bit: 20..26 Reserved */ -#endif - uint32_t Q:1; /*!< bit: 27 Saturation condition flag */ - uint32_t V:1; /*!< bit: 28 Overflow condition code flag */ - uint32_t C:1; /*!< bit: 29 Carry condition code flag */ - uint32_t Z:1; /*!< bit: 30 Zero condition code flag */ - uint32_t N:1; /*!< bit: 31 Negative condition code flag */ - } b; /*!< Structure used for bit access */ - uint32_t w; /*!< Type used for word access */ -} APSR_Type; - - -/** \brief Union type to access the Interrupt Program Status Register (IPSR). - */ -typedef union -{ - struct - { - uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */ - uint32_t _reserved0:23; /*!< bit: 9..31 Reserved */ - } b; /*!< Structure used for bit access */ - uint32_t w; /*!< Type used for word access */ -} IPSR_Type; - - -/** \brief Union type to access the Special-Purpose Program Status Registers (xPSR). - */ -typedef union -{ - struct - { - uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */ -#if (__CORTEX_M != 0x04) - uint32_t _reserved0:15; /*!< bit: 9..23 Reserved */ -#else - uint32_t _reserved0:7; /*!< bit: 9..15 Reserved */ - uint32_t GE:4; /*!< bit: 16..19 Greater than or Equal flags */ - uint32_t _reserved1:4; /*!< bit: 20..23 Reserved */ -#endif - uint32_t T:1; /*!< bit: 24 Thumb bit (read 0) */ - uint32_t IT:2; /*!< bit: 25..26 saved IT state (read 0) */ - uint32_t Q:1; /*!< bit: 27 Saturation condition flag */ - uint32_t V:1; /*!< bit: 28 Overflow condition code flag */ - uint32_t C:1; /*!< bit: 29 Carry condition code flag */ - uint32_t Z:1; /*!< bit: 30 Zero condition code flag */ - uint32_t N:1; /*!< bit: 31 Negative condition code flag */ - } b; /*!< Structure used for bit access */ - uint32_t w; /*!< Type used for word access */ -} xPSR_Type; - - -/** \brief Union type to access the Control Registers (CONTROL). - */ -typedef union -{ - struct - { - uint32_t nPRIV:1; /*!< bit: 0 Execution privilege in Thread mode */ - uint32_t SPSEL:1; /*!< bit: 1 Stack to be used */ - uint32_t FPCA:1; /*!< bit: 2 FP extension active flag */ - uint32_t _reserved0:29; /*!< bit: 3..31 Reserved */ - } b; /*!< Structure used for bit access */ - uint32_t w; /*!< Type used for word access */ -} CONTROL_Type; - -/*@} end of group CMSIS_CORE */ - - -/** \ingroup CMSIS_core_register - \defgroup CMSIS_NVIC Nested Vectored Interrupt Controller (NVIC) - \brief Type definitions for the NVIC Registers - @{ - */ - -/** \brief Structure type to access the Nested Vectored Interrupt Controller (NVIC). - */ -typedef struct -{ - __IO uint32_t ISER[1]; /*!< Offset: 0x000 (R/W) Interrupt Set Enable Register */ - uint32_t RESERVED0[31]; - __IO uint32_t ICER[1]; /*!< Offset: 0x080 (R/W) Interrupt Clear Enable Register */ - uint32_t RSERVED1[31]; - __IO uint32_t ISPR[1]; /*!< Offset: 0x100 (R/W) Interrupt Set Pending Register */ - uint32_t RESERVED2[31]; - __IO uint32_t ICPR[1]; /*!< Offset: 0x180 (R/W) Interrupt Clear Pending Register */ - uint32_t RESERVED3[31]; - uint32_t RESERVED4[64]; - __IO uint32_t IP[8]; /*!< Offset: 0x300 (R/W) Interrupt Priority Register */ -} NVIC_Type; - -/*@} end of group CMSIS_NVIC */ - - -/** \ingroup CMSIS_core_register - \defgroup CMSIS_SCB System Control Block (SCB) - \brief Type definitions for the System Control Block Registers - @{ - */ - -/** \brief Structure type to access the System Control Block (SCB). - */ -typedef struct -{ - __I uint32_t CPUID; /*!< Offset: 0x000 (R/ ) CPUID Base Register */ - __IO uint32_t ICSR; /*!< Offset: 0x004 (R/W) Interrupt Control and State Register */ - uint32_t RESERVED0; - __IO uint32_t AIRCR; /*!< Offset: 0x00C (R/W) Application Interrupt and Reset Control Register */ - __IO uint32_t SCR; /*!< Offset: 0x010 (R/W) System Control Register */ - __IO uint32_t CCR; /*!< Offset: 0x014 (R/W) Configuration Control Register */ - uint32_t RESERVED1; - __IO uint32_t SHP[2]; /*!< Offset: 0x01C (R/W) System Handlers Priority Registers. [0] is RESERVED */ - __IO uint32_t SHCSR; /*!< Offset: 0x024 (R/W) System Handler Control and State Register */ -} SCB_Type; - -/* SCB CPUID Register Definitions */ -#define SCB_CPUID_IMPLEMENTER_Pos 24 /*!< SCB CPUID: IMPLEMENTER Position */ -#define SCB_CPUID_IMPLEMENTER_Msk (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos) /*!< SCB CPUID: IMPLEMENTER Mask */ - -#define SCB_CPUID_VARIANT_Pos 20 /*!< SCB CPUID: VARIANT Position */ -#define SCB_CPUID_VARIANT_Msk (0xFUL << SCB_CPUID_VARIANT_Pos) /*!< SCB CPUID: VARIANT Mask */ - -#define SCB_CPUID_ARCHITECTURE_Pos 16 /*!< SCB CPUID: ARCHITECTURE Position */ -#define SCB_CPUID_ARCHITECTURE_Msk (0xFUL << SCB_CPUID_ARCHITECTURE_Pos) /*!< SCB CPUID: ARCHITECTURE Mask */ - -#define SCB_CPUID_PARTNO_Pos 4 /*!< SCB CPUID: PARTNO Position */ -#define SCB_CPUID_PARTNO_Msk (0xFFFUL << SCB_CPUID_PARTNO_Pos) /*!< SCB CPUID: PARTNO Mask */ - -#define SCB_CPUID_REVISION_Pos 0 /*!< SCB CPUID: REVISION Position */ -#define SCB_CPUID_REVISION_Msk (0xFUL << SCB_CPUID_REVISION_Pos) /*!< SCB CPUID: REVISION Mask */ - -/* SCB Interrupt Control State Register Definitions */ -#define SCB_ICSR_NMIPENDSET_Pos 31 /*!< SCB ICSR: NMIPENDSET Position */ -#define SCB_ICSR_NMIPENDSET_Msk (1UL << SCB_ICSR_NMIPENDSET_Pos) /*!< SCB ICSR: NMIPENDSET Mask */ - -#define SCB_ICSR_PENDSVSET_Pos 28 /*!< SCB ICSR: PENDSVSET Position */ -#define SCB_ICSR_PENDSVSET_Msk (1UL << SCB_ICSR_PENDSVSET_Pos) /*!< SCB ICSR: PENDSVSET Mask */ - -#define SCB_ICSR_PENDSVCLR_Pos 27 /*!< SCB ICSR: PENDSVCLR Position */ -#define SCB_ICSR_PENDSVCLR_Msk (1UL << SCB_ICSR_PENDSVCLR_Pos) /*!< SCB ICSR: PENDSVCLR Mask */ - -#define SCB_ICSR_PENDSTSET_Pos 26 /*!< SCB ICSR: PENDSTSET Position */ -#define SCB_ICSR_PENDSTSET_Msk (1UL << SCB_ICSR_PENDSTSET_Pos) /*!< SCB ICSR: PENDSTSET Mask */ - -#define SCB_ICSR_PENDSTCLR_Pos 25 /*!< SCB ICSR: PENDSTCLR Position */ -#define SCB_ICSR_PENDSTCLR_Msk (1UL << SCB_ICSR_PENDSTCLR_Pos) /*!< SCB ICSR: PENDSTCLR Mask */ - -#define SCB_ICSR_ISRPREEMPT_Pos 23 /*!< SCB ICSR: ISRPREEMPT Position */ -#define SCB_ICSR_ISRPREEMPT_Msk (1UL << SCB_ICSR_ISRPREEMPT_Pos) /*!< SCB ICSR: ISRPREEMPT Mask */ - -#define SCB_ICSR_ISRPENDING_Pos 22 /*!< SCB ICSR: ISRPENDING Position */ -#define SCB_ICSR_ISRPENDING_Msk (1UL << SCB_ICSR_ISRPENDING_Pos) /*!< SCB ICSR: ISRPENDING Mask */ - -#define SCB_ICSR_VECTPENDING_Pos 12 /*!< SCB ICSR: VECTPENDING Position */ -#define SCB_ICSR_VECTPENDING_Msk (0x1FFUL << SCB_ICSR_VECTPENDING_Pos) /*!< SCB ICSR: VECTPENDING Mask */ - -#define SCB_ICSR_VECTACTIVE_Pos 0 /*!< SCB ICSR: VECTACTIVE Position */ -#define SCB_ICSR_VECTACTIVE_Msk (0x1FFUL << SCB_ICSR_VECTACTIVE_Pos) /*!< SCB ICSR: VECTACTIVE Mask */ - -/* SCB Application Interrupt and Reset Control Register Definitions */ -#define SCB_AIRCR_VECTKEY_Pos 16 /*!< SCB AIRCR: VECTKEY Position */ -#define SCB_AIRCR_VECTKEY_Msk (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos) /*!< SCB AIRCR: VECTKEY Mask */ - -#define SCB_AIRCR_VECTKEYSTAT_Pos 16 /*!< SCB AIRCR: VECTKEYSTAT Position */ -#define SCB_AIRCR_VECTKEYSTAT_Msk (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos) /*!< SCB AIRCR: VECTKEYSTAT Mask */ - -#define SCB_AIRCR_ENDIANESS_Pos 15 /*!< SCB AIRCR: ENDIANESS Position */ -#define SCB_AIRCR_ENDIANESS_Msk (1UL << SCB_AIRCR_ENDIANESS_Pos) /*!< SCB AIRCR: ENDIANESS Mask */ - -#define SCB_AIRCR_SYSRESETREQ_Pos 2 /*!< SCB AIRCR: SYSRESETREQ Position */ -#define SCB_AIRCR_SYSRESETREQ_Msk (1UL << SCB_AIRCR_SYSRESETREQ_Pos) /*!< SCB AIRCR: SYSRESETREQ Mask */ - -#define SCB_AIRCR_VECTCLRACTIVE_Pos 1 /*!< SCB AIRCR: VECTCLRACTIVE Position */ -#define SCB_AIRCR_VECTCLRACTIVE_Msk (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos) /*!< SCB AIRCR: VECTCLRACTIVE Mask */ - -/* SCB System Control Register Definitions */ -#define SCB_SCR_SEVONPEND_Pos 4 /*!< SCB SCR: SEVONPEND Position */ -#define SCB_SCR_SEVONPEND_Msk (1UL << SCB_SCR_SEVONPEND_Pos) /*!< SCB SCR: SEVONPEND Mask */ - -#define SCB_SCR_SLEEPDEEP_Pos 2 /*!< SCB SCR: SLEEPDEEP Position */ -#define SCB_SCR_SLEEPDEEP_Msk (1UL << SCB_SCR_SLEEPDEEP_Pos) /*!< SCB SCR: SLEEPDEEP Mask */ - -#define SCB_SCR_SLEEPONEXIT_Pos 1 /*!< SCB SCR: SLEEPONEXIT Position */ -#define SCB_SCR_SLEEPONEXIT_Msk (1UL << SCB_SCR_SLEEPONEXIT_Pos) /*!< SCB SCR: SLEEPONEXIT Mask */ - -/* SCB Configuration Control Register Definitions */ -#define SCB_CCR_STKALIGN_Pos 9 /*!< SCB CCR: STKALIGN Position */ -#define SCB_CCR_STKALIGN_Msk (1UL << SCB_CCR_STKALIGN_Pos) /*!< SCB CCR: STKALIGN Mask */ - -#define SCB_CCR_UNALIGN_TRP_Pos 3 /*!< SCB CCR: UNALIGN_TRP Position */ -#define SCB_CCR_UNALIGN_TRP_Msk (1UL << SCB_CCR_UNALIGN_TRP_Pos) /*!< SCB CCR: UNALIGN_TRP Mask */ - -/* SCB System Handler Control and State Register Definitions */ -#define SCB_SHCSR_SVCALLPENDED_Pos 15 /*!< SCB SHCSR: SVCALLPENDED Position */ -#define SCB_SHCSR_SVCALLPENDED_Msk (1UL << SCB_SHCSR_SVCALLPENDED_Pos) /*!< SCB SHCSR: SVCALLPENDED Mask */ - -/*@} end of group CMSIS_SCB */ - - -/** \ingroup CMSIS_core_register - \defgroup CMSIS_SysTick System Tick Timer (SysTick) - \brief Type definitions for the System Timer Registers. - @{ - */ - -/** \brief Structure type to access the System Timer (SysTick). - */ -typedef struct -{ - __IO uint32_t CTRL; /*!< Offset: 0x000 (R/W) SysTick Control and Status Register */ - __IO uint32_t LOAD; /*!< Offset: 0x004 (R/W) SysTick Reload Value Register */ - __IO uint32_t VAL; /*!< Offset: 0x008 (R/W) SysTick Current Value Register */ - __I uint32_t CALIB; /*!< Offset: 0x00C (R/ ) SysTick Calibration Register */ -} SysTick_Type; - -/* SysTick Control / Status Register Definitions */ -#define SysTick_CTRL_COUNTFLAG_Pos 16 /*!< SysTick CTRL: COUNTFLAG Position */ -#define SysTick_CTRL_COUNTFLAG_Msk (1UL << SysTick_CTRL_COUNTFLAG_Pos) /*!< SysTick CTRL: COUNTFLAG Mask */ - -#define SysTick_CTRL_CLKSOURCE_Pos 2 /*!< SysTick CTRL: CLKSOURCE Position */ -#define SysTick_CTRL_CLKSOURCE_Msk (1UL << SysTick_CTRL_CLKSOURCE_Pos) /*!< SysTick CTRL: CLKSOURCE Mask */ - -#define SysTick_CTRL_TICKINT_Pos 1 /*!< SysTick CTRL: TICKINT Position */ -#define SysTick_CTRL_TICKINT_Msk (1UL << SysTick_CTRL_TICKINT_Pos) /*!< SysTick CTRL: TICKINT Mask */ - -#define SysTick_CTRL_ENABLE_Pos 0 /*!< SysTick CTRL: ENABLE Position */ -#define SysTick_CTRL_ENABLE_Msk (1UL << SysTick_CTRL_ENABLE_Pos) /*!< SysTick CTRL: ENABLE Mask */ - -/* SysTick Reload Register Definitions */ -#define SysTick_LOAD_RELOAD_Pos 0 /*!< SysTick LOAD: RELOAD Position */ -#define SysTick_LOAD_RELOAD_Msk (0xFFFFFFUL << SysTick_LOAD_RELOAD_Pos) /*!< SysTick LOAD: RELOAD Mask */ - -/* SysTick Current Register Definitions */ -#define SysTick_VAL_CURRENT_Pos 0 /*!< SysTick VAL: CURRENT Position */ -#define SysTick_VAL_CURRENT_Msk (0xFFFFFFUL << SysTick_VAL_CURRENT_Pos) /*!< SysTick VAL: CURRENT Mask */ - -/* SysTick Calibration Register Definitions */ -#define SysTick_CALIB_NOREF_Pos 31 /*!< SysTick CALIB: NOREF Position */ -#define SysTick_CALIB_NOREF_Msk (1UL << SysTick_CALIB_NOREF_Pos) /*!< SysTick CALIB: NOREF Mask */ - -#define SysTick_CALIB_SKEW_Pos 30 /*!< SysTick CALIB: SKEW Position */ -#define SysTick_CALIB_SKEW_Msk (1UL << SysTick_CALIB_SKEW_Pos) /*!< SysTick CALIB: SKEW Mask */ - -#define SysTick_CALIB_TENMS_Pos 0 /*!< SysTick CALIB: TENMS Position */ -#define SysTick_CALIB_TENMS_Msk (0xFFFFFFUL << SysTick_VAL_CURRENT_Pos) /*!< SysTick CALIB: TENMS Mask */ - -/*@} end of group CMSIS_SysTick */ - - -/** \ingroup CMSIS_core_register - \defgroup CMSIS_CoreDebug Core Debug Registers (CoreDebug) - \brief Cortex-M0 Core Debug Registers (DCB registers, SHCSR, and DFSR) - are only accessible over DAP and not via processor. Therefore - they are not covered by the Cortex-M0 header file. - @{ - */ -/*@} end of group CMSIS_CoreDebug */ - - -/** \ingroup CMSIS_core_register - \defgroup CMSIS_core_base Core Definitions - \brief Definitions for base addresses, unions, and structures. - @{ - */ - -/* Memory mapping of Cortex-M0 Hardware */ -#define SCS_BASE (0xE000E000UL) /*!< System Control Space Base Address */ -#define SysTick_BASE (SCS_BASE + 0x0010UL) /*!< SysTick Base Address */ -#define NVIC_BASE (SCS_BASE + 0x0100UL) /*!< NVIC Base Address */ -#define SCB_BASE (SCS_BASE + 0x0D00UL) /*!< System Control Block Base Address */ - -#define SCB ((SCB_Type *) SCB_BASE ) /*!< SCB configuration struct */ -#define SysTick ((SysTick_Type *) SysTick_BASE ) /*!< SysTick configuration struct */ -#define NVIC ((NVIC_Type *) NVIC_BASE ) /*!< NVIC configuration struct */ - - -/*@} */ - - - -/******************************************************************************* - * Hardware Abstraction Layer - Core Function Interface contains: - - Core NVIC Functions - - Core SysTick Functions - - Core Register Access Functions - ******************************************************************************/ -/** \defgroup CMSIS_Core_FunctionInterface Functions and Instructions Reference -*/ - - - -/* ########################## NVIC functions #################################### */ -/** \ingroup CMSIS_Core_FunctionInterface - \defgroup CMSIS_Core_NVICFunctions NVIC Functions - \brief Functions that manage interrupts and exceptions via the NVIC. - @{ - */ - -/* Interrupt Priorities are WORD accessible only under ARMv6M */ -/* The following MACROS handle generation of the register offset and byte masks */ -#define _BIT_SHIFT(IRQn) ( (((uint32_t)(IRQn) ) & 0x03) * 8 ) -#define _SHP_IDX(IRQn) ( ((((uint32_t)(IRQn) & 0x0F)-8) >> 2) ) -#define _IP_IDX(IRQn) ( ((uint32_t)(IRQn) >> 2) ) - - -/** \brief Enable External Interrupt - - The function enables a device-specific interrupt in the NVIC interrupt controller. - - \param [in] IRQn External interrupt number. Value cannot be negative. - */ -__STATIC_INLINE void NVIC_EnableIRQ(IRQn_Type IRQn) -{ - NVIC->ISER[0] = (1 << ((uint32_t)(IRQn) & 0x1F)); -} - - -/** \brief Disable External Interrupt - - The function disables a device-specific interrupt in the NVIC interrupt controller. - - \param [in] IRQn External interrupt number. Value cannot be negative. - */ -__STATIC_INLINE void NVIC_DisableIRQ(IRQn_Type IRQn) -{ - NVIC->ICER[0] = (1 << ((uint32_t)(IRQn) & 0x1F)); -} - - -/** \brief Get Pending Interrupt - - The function reads the pending register in the NVIC and returns the pending bit - for the specified interrupt. - - \param [in] IRQn Interrupt number. - - \return 0 Interrupt status is not pending. - \return 1 Interrupt status is pending. - */ -__STATIC_INLINE uint32_t NVIC_GetPendingIRQ(IRQn_Type IRQn) -{ - return((uint32_t) ((NVIC->ISPR[0] & (1 << ((uint32_t)(IRQn) & 0x1F)))?1:0)); -} - - -/** \brief Set Pending Interrupt - - The function sets the pending bit of an external interrupt. - - \param [in] IRQn Interrupt number. Value cannot be negative. - */ -__STATIC_INLINE void NVIC_SetPendingIRQ(IRQn_Type IRQn) -{ - NVIC->ISPR[0] = (1 << ((uint32_t)(IRQn) & 0x1F)); -} - - -/** \brief Clear Pending Interrupt - - The function clears the pending bit of an external interrupt. - - \param [in] IRQn External interrupt number. Value cannot be negative. - */ -__STATIC_INLINE void NVIC_ClearPendingIRQ(IRQn_Type IRQn) -{ - NVIC->ICPR[0] = (1 << ((uint32_t)(IRQn) & 0x1F)); /* Clear pending interrupt */ -} - - -/** \brief Set Interrupt Priority - - The function sets the priority of an interrupt. - - \note The priority cannot be set for every core interrupt. - - \param [in] IRQn Interrupt number. - \param [in] priority Priority to set. - */ -__STATIC_INLINE void NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority) -{ - if(IRQn < 0) { - SCB->SHP[_SHP_IDX(IRQn)] = (SCB->SHP[_SHP_IDX(IRQn)] & ~(0xFF << _BIT_SHIFT(IRQn))) | - (((priority << (8 - __NVIC_PRIO_BITS)) & 0xFF) << _BIT_SHIFT(IRQn)); } - else { - NVIC->IP[_IP_IDX(IRQn)] = (NVIC->IP[_IP_IDX(IRQn)] & ~(0xFF << _BIT_SHIFT(IRQn))) | - (((priority << (8 - __NVIC_PRIO_BITS)) & 0xFF) << _BIT_SHIFT(IRQn)); } -} - - -/** \brief Get Interrupt Priority - - The function reads the priority of an interrupt. The interrupt - number can be positive to specify an external (device specific) - interrupt, or negative to specify an internal (core) interrupt. - - - \param [in] IRQn Interrupt number. - \return Interrupt Priority. Value is aligned automatically to the implemented - priority bits of the microcontroller. - */ -__STATIC_INLINE uint32_t NVIC_GetPriority(IRQn_Type IRQn) -{ - - if(IRQn < 0) { - return((uint32_t)((SCB->SHP[_SHP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) >> (8 - __NVIC_PRIO_BITS))); } /* get priority for Cortex-M0 system interrupts */ - else { - return((uint32_t)((NVIC->IP[ _IP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) >> (8 - __NVIC_PRIO_BITS))); } /* get priority for device specific interrupts */ -} - - -/** \brief System Reset - - The function initiates a system reset request to reset the MCU. - */ -__STATIC_INLINE void NVIC_SystemReset(void) -{ - __DSB(); /* Ensure all outstanding memory accesses included - buffered write are completed before reset */ - SCB->AIRCR = ((0x5FA << SCB_AIRCR_VECTKEY_Pos) | - SCB_AIRCR_SYSRESETREQ_Msk); - __DSB(); /* Ensure completion of memory access */ - while(1); /* wait until reset */ -} - -/*@} end of CMSIS_Core_NVICFunctions */ - - - -/* ################################## SysTick function ############################################ */ -/** \ingroup CMSIS_Core_FunctionInterface - \defgroup CMSIS_Core_SysTickFunctions SysTick Functions - \brief Functions that configure the System. - @{ - */ - -#if (__Vendor_SysTickConfig == 0) - -/** \brief System Tick Configuration - - The function initializes the System Timer and its interrupt, and starts the System Tick Timer. - Counter is in free running mode to generate periodic interrupts. - - \param [in] ticks Number of ticks between two interrupts. - - \return 0 Function succeeded. - \return 1 Function failed. - - \note When the variable __Vendor_SysTickConfig is set to 1, then the - function SysTick_Config is not included. In this case, the file device.h - must contain a vendor-specific implementation of this function. - - */ -__STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks) -{ - if ((ticks - 1) > SysTick_LOAD_RELOAD_Msk) return (1); /* Reload value impossible */ - - SysTick->LOAD = ticks - 1; /* set reload register */ - NVIC_SetPriority (SysTick_IRQn, (1<<__NVIC_PRIO_BITS) - 1); /* set Priority for Systick Interrupt */ - SysTick->VAL = 0; /* Load the SysTick Counter Value */ - SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk | - SysTick_CTRL_TICKINT_Msk | - SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */ - return (0); /* Function successful */ -} - -#endif - -/*@} end of CMSIS_Core_SysTickFunctions */ - - - - -#endif /* __CORE_CM0_H_DEPENDANT */ - -#endif /* __CMSIS_GENERIC */ - -#ifdef __cplusplus -} -#endif diff --git a/bsp/essemi/es8p508x/libraries/CMSIS/core_cmFunc.h b/bsp/essemi/es8p508x/libraries/CMSIS/core_cmFunc.h deleted file mode 100644 index 0a18fafc30..0000000000 --- a/bsp/essemi/es8p508x/libraries/CMSIS/core_cmFunc.h +++ /dev/null @@ -1,636 +0,0 @@ -/**************************************************************************//** - * @file core_cmFunc.h - * @brief CMSIS Cortex-M Core Function Access Header File - * @version V3.20 - * @date 25. February 2013 - * - * @note - * - ******************************************************************************/ -/* Copyright (c) 2009 - 2013 ARM LIMITED - - All rights reserved. - Redistribution and use in source and binary forms, with or without - modification, are permitted provided that the following conditions are met: - - Redistributions of source code must retain the above copyright - notice, this list of conditions and the following disclaimer. - - Redistributions in binary form must reproduce the above copyright - notice, this list of conditions and the following disclaimer in the - documentation and/or other materials provided with the distribution. - - Neither the name of ARM nor the names of its contributors may be used - to endorse or promote products derived from this software without - specific prior written permission. - * - THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" - AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE - ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE - LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR - CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF - SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS - INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN - CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) - ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE - POSSIBILITY OF SUCH DAMAGE. - ---------------------------------------------------------------------------*/ - - -#ifndef __CORE_CMFUNC_H -#define __CORE_CMFUNC_H - - -/* ########################### Core Function Access ########################### */ -/** \ingroup CMSIS_Core_FunctionInterface - \defgroup CMSIS_Core_RegAccFunctions CMSIS Core Register Access Functions - @{ - */ - -#if defined ( __CC_ARM ) /*------------------RealView Compiler -----------------*/ -/* ARM armcc specific functions */ - -#if (__ARMCC_VERSION < 400677) - #error "Please use ARM Compiler Toolchain V4.0.677 or later!" -#endif - -/* intrinsic void __enable_irq(); */ -/* intrinsic void __disable_irq(); */ - -/** \brief Get Control Register - - This function returns the content of the Control Register. - - \return Control Register value - */ -__STATIC_INLINE uint32_t __get_CONTROL(void) -{ - register uint32_t __regControl __ASM("control"); - return(__regControl); -} - - -/** \brief Set Control Register - - This function writes the given value to the Control Register. - - \param [in] control Control Register value to set - */ -__STATIC_INLINE void __set_CONTROL(uint32_t control) -{ - register uint32_t __regControl __ASM("control"); - __regControl = control; -} - - -/** \brief Get IPSR Register - - This function returns the content of the IPSR Register. - - \return IPSR Register value - */ -__STATIC_INLINE uint32_t __get_IPSR(void) -{ - register uint32_t __regIPSR __ASM("ipsr"); - return(__regIPSR); -} - - -/** \brief Get APSR Register - - This function returns the content of the APSR Register. - - \return APSR Register value - */ -__STATIC_INLINE uint32_t __get_APSR(void) -{ - register uint32_t __regAPSR __ASM("apsr"); - return(__regAPSR); -} - - -/** \brief Get xPSR Register - - This function returns the content of the xPSR Register. - - \return xPSR Register value - */ -__STATIC_INLINE uint32_t __get_xPSR(void) -{ - register uint32_t __regXPSR __ASM("xpsr"); - return(__regXPSR); -} - - -/** \brief Get Process Stack Pointer - - This function returns the current value of the Process Stack Pointer (PSP). - - \return PSP Register value - */ -__STATIC_INLINE uint32_t __get_PSP(void) -{ - register uint32_t __regProcessStackPointer __ASM("psp"); - return(__regProcessStackPointer); -} - - -/** \brief Set Process Stack Pointer - - This function assigns the given value to the Process Stack Pointer (PSP). - - \param [in] topOfProcStack Process Stack Pointer value to set - */ -__STATIC_INLINE void __set_PSP(uint32_t topOfProcStack) -{ - register uint32_t __regProcessStackPointer __ASM("psp"); - __regProcessStackPointer = topOfProcStack; -} - - -/** \brief Get Main Stack Pointer - - This function returns the current value of the Main Stack Pointer (MSP). - - \return MSP Register value - */ -__STATIC_INLINE uint32_t __get_MSP(void) -{ - register uint32_t __regMainStackPointer __ASM("msp"); - return(__regMainStackPointer); -} - - -/** \brief Set Main Stack Pointer - - This function assigns the given value to the Main Stack Pointer (MSP). - - \param [in] topOfMainStack Main Stack Pointer value to set - */ -__STATIC_INLINE void __set_MSP(uint32_t topOfMainStack) -{ - register uint32_t __regMainStackPointer __ASM("msp"); - __regMainStackPointer = topOfMainStack; -} - - -/** \brief Get Priority Mask - - This function returns the current state of the priority mask bit from the Priority Mask Register. - - \return Priority Mask value - */ -__STATIC_INLINE uint32_t __get_PRIMASK(void) -{ - register uint32_t __regPriMask __ASM("primask"); - return(__regPriMask); -} - - -/** \brief Set Priority Mask - - This function assigns the given value to the Priority Mask Register. - - \param [in] priMask Priority Mask - */ -__STATIC_INLINE void __set_PRIMASK(uint32_t priMask) -{ - register uint32_t __regPriMask __ASM("primask"); - __regPriMask = (priMask); -} - - -#if (__CORTEX_M >= 0x03) - -/** \brief Enable FIQ - - This function enables FIQ interrupts by clearing the F-bit in the CPSR. - Can only be executed in Privileged modes. - */ -#define __enable_fault_irq __enable_fiq - - -/** \brief Disable FIQ - - This function disables FIQ interrupts by setting the F-bit in the CPSR. - Can only be executed in Privileged modes. - */ -#define __disable_fault_irq __disable_fiq - - -/** \brief Get Base Priority - - This function returns the current value of the Base Priority register. - - \return Base Priority register value - */ -__STATIC_INLINE uint32_t __get_BASEPRI(void) -{ - register uint32_t __regBasePri __ASM("basepri"); - return(__regBasePri); -} - - -/** \brief Set Base Priority - - This function assigns the given value to the Base Priority register. - - \param [in] basePri Base Priority value to set - */ -__STATIC_INLINE void __set_BASEPRI(uint32_t basePri) -{ - register uint32_t __regBasePri __ASM("basepri"); - __regBasePri = (basePri & 0xff); -} - - -/** \brief Get Fault Mask - - This function returns the current value of the Fault Mask register. - - \return Fault Mask register value - */ -__STATIC_INLINE uint32_t __get_FAULTMASK(void) -{ - register uint32_t __regFaultMask __ASM("faultmask"); - return(__regFaultMask); -} - - -/** \brief Set Fault Mask - - This function assigns the given value to the Fault Mask register. - - \param [in] faultMask Fault Mask value to set - */ -__STATIC_INLINE void __set_FAULTMASK(uint32_t faultMask) -{ - register uint32_t __regFaultMask __ASM("faultmask"); - __regFaultMask = (faultMask & (uint32_t)1); -} - -#endif /* (__CORTEX_M >= 0x03) */ - - -#if (__CORTEX_M == 0x04) - -/** \brief Get FPSCR - - This function returns the current value of the Floating Point Status/Control register. - - \return Floating Point Status/Control register value - */ -__STATIC_INLINE uint32_t __get_FPSCR(void) -{ -#if (__FPU_PRESENT == 1) && (__FPU_USED == 1) - register uint32_t __regfpscr __ASM("fpscr"); - return(__regfpscr); -#else - return(0); -#endif -} - - -/** \brief Set FPSCR - - This function assigns the given value to the Floating Point Status/Control register. - - \param [in] fpscr Floating Point Status/Control value to set - */ -__STATIC_INLINE void __set_FPSCR(uint32_t fpscr) -{ -#if (__FPU_PRESENT == 1) && (__FPU_USED == 1) - register uint32_t __regfpscr __ASM("fpscr"); - __regfpscr = (fpscr); -#endif -} - -#endif /* (__CORTEX_M == 0x04) */ - - -#elif defined ( __ICCARM__ ) /*------------------ ICC Compiler -------------------*/ -/* IAR iccarm specific functions */ - -#include - - -#elif defined ( __TMS470__ ) /*---------------- TI CCS Compiler ------------------*/ -/* TI CCS specific functions */ - -#include - - -#elif defined ( __GNUC__ ) /*------------------ GNU Compiler ---------------------*/ -/* GNU gcc specific functions */ - -/** \brief Enable IRQ Interrupts - - This function enables IRQ interrupts by clearing the I-bit in the CPSR. - Can only be executed in Privileged modes. - */ -__attribute__( ( always_inline ) ) __STATIC_INLINE void __enable_irq(void) -{ - __ASM volatile ("cpsie i" : : : "memory"); -} - - -/** \brief Disable IRQ Interrupts - - This function disables IRQ interrupts by setting the I-bit in the CPSR. - Can only be executed in Privileged modes. - */ -__attribute__( ( always_inline ) ) __STATIC_INLINE void __disable_irq(void) -{ - __ASM volatile ("cpsid i" : : : "memory"); -} - - -/** \brief Get Control Register - - This function returns the content of the Control Register. - - \return Control Register value - */ -__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_CONTROL(void) -{ - uint32_t result; - - __ASM volatile ("MRS %0, control" : "=r" (result) ); - return(result); -} - - -/** \brief Set Control Register - - This function writes the given value to the Control Register. - - \param [in] control Control Register value to set - */ -__attribute__( ( always_inline ) ) __STATIC_INLINE void __set_CONTROL(uint32_t control) -{ - __ASM volatile ("MSR control, %0" : : "r" (control) : "memory"); -} - - -/** \brief Get IPSR Register - - This function returns the content of the IPSR Register. - - \return IPSR Register value - */ -__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_IPSR(void) -{ - uint32_t result; - - __ASM volatile ("MRS %0, ipsr" : "=r" (result) ); - return(result); -} - - -/** \brief Get APSR Register - - This function returns the content of the APSR Register. - - \return APSR Register value - */ -__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_APSR(void) -{ - uint32_t result; - - __ASM volatile ("MRS %0, apsr" : "=r" (result) ); - return(result); -} - - -/** \brief Get xPSR Register - - This function returns the content of the xPSR Register. - - \return xPSR Register value - */ -__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_xPSR(void) -{ - uint32_t result; - - __ASM volatile ("MRS %0, xpsr" : "=r" (result) ); - return(result); -} - - -/** \brief Get Process Stack Pointer - - This function returns the current value of the Process Stack Pointer (PSP). - - \return PSP Register value - */ -__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_PSP(void) -{ - register uint32_t result; - - __ASM volatile ("MRS %0, psp\n" : "=r" (result) ); - return(result); -} - - -/** \brief Set Process Stack Pointer - - This function assigns the given value to the Process Stack Pointer (PSP). - - \param [in] topOfProcStack Process Stack Pointer value to set - */ -__attribute__( ( always_inline ) ) __STATIC_INLINE void __set_PSP(uint32_t topOfProcStack) -{ - __ASM volatile ("MSR psp, %0\n" : : "r" (topOfProcStack) : "sp"); -} - - -/** \brief Get Main Stack Pointer - - This function returns the current value of the Main Stack Pointer (MSP). - - \return MSP Register value - */ -__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_MSP(void) -{ - register uint32_t result; - - __ASM volatile ("MRS %0, msp\n" : "=r" (result) ); - return(result); -} - - -/** \brief Set Main Stack Pointer - - This function assigns the given value to the Main Stack Pointer (MSP). - - \param [in] topOfMainStack Main Stack Pointer value to set - */ -__attribute__( ( always_inline ) ) __STATIC_INLINE void __set_MSP(uint32_t topOfMainStack) -{ - __ASM volatile ("MSR msp, %0\n" : : "r" (topOfMainStack) : "sp"); -} - - -/** \brief Get Priority Mask - - This function returns the current state of the priority mask bit from the Priority Mask Register. - - \return Priority Mask value - */ -__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_PRIMASK(void) -{ - uint32_t result; - - __ASM volatile ("MRS %0, primask" : "=r" (result) ); - return(result); -} - - -/** \brief Set Priority Mask - - This function assigns the given value to the Priority Mask Register. - - \param [in] priMask Priority Mask - */ -__attribute__( ( always_inline ) ) __STATIC_INLINE void __set_PRIMASK(uint32_t priMask) -{ - __ASM volatile ("MSR primask, %0" : : "r" (priMask) : "memory"); -} - - -#if (__CORTEX_M >= 0x03) - -/** \brief Enable FIQ - - This function enables FIQ interrupts by clearing the F-bit in the CPSR. - Can only be executed in Privileged modes. - */ -__attribute__( ( always_inline ) ) __STATIC_INLINE void __enable_fault_irq(void) -{ - __ASM volatile ("cpsie f" : : : "memory"); -} - - -/** \brief Disable FIQ - - This function disables FIQ interrupts by setting the F-bit in the CPSR. - Can only be executed in Privileged modes. - */ -__attribute__( ( always_inline ) ) __STATIC_INLINE void __disable_fault_irq(void) -{ - __ASM volatile ("cpsid f" : : : "memory"); -} - - -/** \brief Get Base Priority - - This function returns the current value of the Base Priority register. - - \return Base Priority register value - */ -__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_BASEPRI(void) -{ - uint32_t result; - - __ASM volatile ("MRS %0, basepri_max" : "=r" (result) ); - return(result); -} - - -/** \brief Set Base Priority - - This function assigns the given value to the Base Priority register. - - \param [in] basePri Base Priority value to set - */ -__attribute__( ( always_inline ) ) __STATIC_INLINE void __set_BASEPRI(uint32_t value) -{ - __ASM volatile ("MSR basepri, %0" : : "r" (value) : "memory"); -} - - -/** \brief Get Fault Mask - - This function returns the current value of the Fault Mask register. - - \return Fault Mask register value - */ -__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_FAULTMASK(void) -{ - uint32_t result; - - __ASM volatile ("MRS %0, faultmask" : "=r" (result) ); - return(result); -} - - -/** \brief Set Fault Mask - - This function assigns the given value to the Fault Mask register. - - \param [in] faultMask Fault Mask value to set - */ -__attribute__( ( always_inline ) ) __STATIC_INLINE void __set_FAULTMASK(uint32_t faultMask) -{ - __ASM volatile ("MSR faultmask, %0" : : "r" (faultMask) : "memory"); -} - -#endif /* (__CORTEX_M >= 0x03) */ - - -#if (__CORTEX_M == 0x04) - -/** \brief Get FPSCR - - This function returns the current value of the Floating Point Status/Control register. - - \return Floating Point Status/Control register value - */ -__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_FPSCR(void) -{ -#if (__FPU_PRESENT == 1) && (__FPU_USED == 1) - uint32_t result; - - /* Empty asm statement works as a scheduling barrier */ - __ASM volatile (""); - __ASM volatile ("VMRS %0, fpscr" : "=r" (result) ); - __ASM volatile (""); - return(result); -#else - return(0); -#endif -} - - -/** \brief Set FPSCR - - This function assigns the given value to the Floating Point Status/Control register. - - \param [in] fpscr Floating Point Status/Control value to set - */ -__attribute__( ( always_inline ) ) __STATIC_INLINE void __set_FPSCR(uint32_t fpscr) -{ -#if (__FPU_PRESENT == 1) && (__FPU_USED == 1) - /* Empty asm statement works as a scheduling barrier */ - __ASM volatile (""); - __ASM volatile ("VMSR fpscr, %0" : : "r" (fpscr) : "vfpcc"); - __ASM volatile (""); -#endif -} - -#endif /* (__CORTEX_M == 0x04) */ - - -#elif defined ( __TASKING__ ) /*------------------ TASKING Compiler --------------*/ -/* TASKING carm specific functions */ - -/* - * The CMSIS functions have been implemented as intrinsics in the compiler. - * Please use "carm -?i" to get an up to date list of all instrinsics, - * Including the CMSIS ones. - */ - -#endif - -/*@} end of CMSIS_Core_RegAccFunctions */ - - -#endif /* __CORE_CMFUNC_H */ diff --git a/bsp/essemi/es8p508x/libraries/CMSIS/core_cmInstr.h b/bsp/essemi/es8p508x/libraries/CMSIS/core_cmInstr.h deleted file mode 100644 index d213f0eed7..0000000000 --- a/bsp/essemi/es8p508x/libraries/CMSIS/core_cmInstr.h +++ /dev/null @@ -1,688 +0,0 @@ -/**************************************************************************//** - * @file core_cmInstr.h - * @brief CMSIS Cortex-M Core Instruction Access Header File - * @version V3.20 - * @date 05. March 2013 - * - * @note - * - ******************************************************************************/ -/* Copyright (c) 2009 - 2013 ARM LIMITED - - All rights reserved. - Redistribution and use in source and binary forms, with or without - modification, are permitted provided that the following conditions are met: - - Redistributions of source code must retain the above copyright - notice, this list of conditions and the following disclaimer. - - Redistributions in binary form must reproduce the above copyright - notice, this list of conditions and the following disclaimer in the - documentation and/or other materials provided with the distribution. - - Neither the name of ARM nor the names of its contributors may be used - to endorse or promote products derived from this software without - specific prior written permission. - * - THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" - AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE - ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE - LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR - CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF - SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS - INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN - CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) - ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE - POSSIBILITY OF SUCH DAMAGE. - ---------------------------------------------------------------------------*/ - - -#ifndef __CORE_CMINSTR_H -#define __CORE_CMINSTR_H - - -/* ########################## Core Instruction Access ######################### */ -/** \defgroup CMSIS_Core_InstructionInterface CMSIS Core Instruction Interface - Access to dedicated instructions - @{ -*/ - -#if defined ( __CC_ARM ) /*------------------RealView Compiler -----------------*/ -/* ARM armcc specific functions */ - -#if (__ARMCC_VERSION < 400677) - #error "Please use ARM Compiler Toolchain V4.0.677 or later!" -#endif - - -/** \brief No Operation - - No Operation does nothing. This instruction can be used for code alignment purposes. - */ -#define __NOP __nop - - -/** \brief Wait For Interrupt - - Wait For Interrupt is a hint instruction that suspends execution - until one of a number of events occurs. - */ -#define __WFI __wfi - - -/** \brief Wait For Event - - Wait For Event is a hint instruction that permits the processor to enter - a low-power state until one of a number of events occurs. - */ -#define __WFE __wfe - - -/** \brief Send Event - - Send Event is a hint instruction. It causes an event to be signaled to the CPU. - */ -#define __SEV __sev - - -/** \brief Instruction Synchronization Barrier - - Instruction Synchronization Barrier flushes the pipeline in the processor, - so that all instructions following the ISB are fetched from cache or - memory, after the instruction has been completed. - */ -#define __ISB() __isb(0xF) - - -/** \brief Data Synchronization Barrier - - This function acts as a special kind of Data Memory Barrier. - It completes when all explicit memory accesses before this instruction complete. - */ -#define __DSB() __dsb(0xF) - - -/** \brief Data Memory Barrier - - This function ensures the apparent order of the explicit memory operations before - and after the instruction, without ensuring their completion. - */ -#define __DMB() __dmb(0xF) - - -/** \brief Reverse byte order (32 bit) - - This function reverses the byte order in integer value. - - \param [in] value Value to reverse - \return Reversed value - */ -#define __REV __rev - - -/** \brief Reverse byte order (16 bit) - - This function reverses the byte order in two unsigned short values. - - \param [in] value Value to reverse - \return Reversed value - */ -#ifndef __NO_EMBEDDED_ASM -__attribute__((section(".rev16_text"))) __STATIC_INLINE __ASM uint32_t __REV16(uint32_t value) -{ - rev16 r0, r0 - bx lr -} -#endif - -/** \brief Reverse byte order in signed short value - - This function reverses the byte order in a signed short value with sign extension to integer. - - \param [in] value Value to reverse - \return Reversed value - */ -#ifndef __NO_EMBEDDED_ASM -__attribute__((section(".revsh_text"))) __STATIC_INLINE __ASM int32_t __REVSH(int32_t value) -{ - revsh r0, r0 - bx lr -} -#endif - - -/** \brief Rotate Right in unsigned value (32 bit) - - This function Rotate Right (immediate) provides the value of the contents of a register rotated by a variable number of bits. - - \param [in] value Value to rotate - \param [in] value Number of Bits to rotate - \return Rotated value - */ -#define __ROR __ror - - -/** \brief Breakpoint - - This function causes the processor to enter Debug state. - Debug tools can use this to investigate system state when the instruction at a particular address is reached. - - \param [in] value is ignored by the processor. - If required, a debugger can use it to store additional information about the breakpoint. - */ -#define __BKPT(value) __breakpoint(value) - - -#if (__CORTEX_M >= 0x03) - -/** \brief Reverse bit order of value - - This function reverses the bit order of the given value. - - \param [in] value Value to reverse - \return Reversed value - */ -#define __RBIT __rbit - - -/** \brief LDR Exclusive (8 bit) - - This function performs a exclusive LDR command for 8 bit value. - - \param [in] ptr Pointer to data - \return value of type uint8_t at (*ptr) - */ -#define __LDREXB(ptr) ((uint8_t ) __ldrex(ptr)) - - -/** \brief LDR Exclusive (16 bit) - - This function performs a exclusive LDR command for 16 bit values. - - \param [in] ptr Pointer to data - \return value of type uint16_t at (*ptr) - */ -#define __LDREXH(ptr) ((uint16_t) __ldrex(ptr)) - - -/** \brief LDR Exclusive (32 bit) - - This function performs a exclusive LDR command for 32 bit values. - - \param [in] ptr Pointer to data - \return value of type uint32_t at (*ptr) - */ -#define __LDREXW(ptr) ((uint32_t ) __ldrex(ptr)) - - -/** \brief STR Exclusive (8 bit) - - This function performs a exclusive STR command for 8 bit values. - - \param [in] value Value to store - \param [in] ptr Pointer to location - \return 0 Function succeeded - \return 1 Function failed - */ -#define __STREXB(value, ptr) __strex(value, ptr) - - -/** \brief STR Exclusive (16 bit) - - This function performs a exclusive STR command for 16 bit values. - - \param [in] value Value to store - \param [in] ptr Pointer to location - \return 0 Function succeeded - \return 1 Function failed - */ -#define __STREXH(value, ptr) __strex(value, ptr) - - -/** \brief STR Exclusive (32 bit) - - This function performs a exclusive STR command for 32 bit values. - - \param [in] value Value to store - \param [in] ptr Pointer to location - \return 0 Function succeeded - \return 1 Function failed - */ -#define __STREXW(value, ptr) __strex(value, ptr) - - -/** \brief Remove the exclusive lock - - This function removes the exclusive lock which is created by LDREX. - - */ -#define __CLREX __clrex - - -/** \brief Signed Saturate - - This function saturates a signed value. - - \param [in] value Value to be saturated - \param [in] sat Bit position to saturate to (1..32) - \return Saturated value - */ -#define __SSAT __ssat - - -/** \brief Unsigned Saturate - - This function saturates an unsigned value. - - \param [in] value Value to be saturated - \param [in] sat Bit position to saturate to (0..31) - \return Saturated value - */ -#define __USAT __usat - - -/** \brief Count leading zeros - - This function counts the number of leading zeros of a data value. - - \param [in] value Value to count the leading zeros - \return number of leading zeros in value - */ -#define __CLZ __clz - -#endif /* (__CORTEX_M >= 0x03) */ - - - -#elif defined ( __ICCARM__ ) /*------------------ ICC Compiler -------------------*/ -/* IAR iccarm specific functions */ - -#include - - -#elif defined ( __TMS470__ ) /*---------------- TI CCS Compiler ------------------*/ -/* TI CCS specific functions */ - -#include - - -#elif defined ( __GNUC__ ) /*------------------ GNU Compiler ---------------------*/ -/* GNU gcc specific functions */ - -/* Define macros for porting to both thumb1 and thumb2. - * For thumb1, use low register (r0-r7), specified by constrant "l" - * Otherwise, use general registers, specified by constrant "r" */ -#if defined (__thumb__) && !defined (__thumb2__) -#define __CMSIS_GCC_OUT_REG(r) "=l" (r) -#define __CMSIS_GCC_USE_REG(r) "l" (r) -#else -#define __CMSIS_GCC_OUT_REG(r) "=r" (r) -#define __CMSIS_GCC_USE_REG(r) "r" (r) -#endif - -/** \brief No Operation - - No Operation does nothing. This instruction can be used for code alignment purposes. - */ -__attribute__( ( always_inline ) ) __STATIC_INLINE void __NOP(void) -{ - __ASM volatile ("nop"); -} - - -/** \brief Wait For Interrupt - - Wait For Interrupt is a hint instruction that suspends execution - until one of a number of events occurs. - */ -__attribute__( ( always_inline ) ) __STATIC_INLINE void __WFI(void) -{ - __ASM volatile ("wfi"); -} - - -/** \brief Wait For Event - - Wait For Event is a hint instruction that permits the processor to enter - a low-power state until one of a number of events occurs. - */ -__attribute__( ( always_inline ) ) __STATIC_INLINE void __WFE(void) -{ - __ASM volatile ("wfe"); -} - - -/** \brief Send Event - - Send Event is a hint instruction. It causes an event to be signaled to the CPU. - */ -__attribute__( ( always_inline ) ) __STATIC_INLINE void __SEV(void) -{ - __ASM volatile ("sev"); -} - - -/** \brief Instruction Synchronization Barrier - - Instruction Synchronization Barrier flushes the pipeline in the processor, - so that all instructions following the ISB are fetched from cache or - memory, after the instruction has been completed. - */ -__attribute__( ( always_inline ) ) __STATIC_INLINE void __ISB(void) -{ - __ASM volatile ("isb"); -} - - -/** \brief Data Synchronization Barrier - - This function acts as a special kind of Data Memory Barrier. - It completes when all explicit memory accesses before this instruction complete. - */ -__attribute__( ( always_inline ) ) __STATIC_INLINE void __DSB(void) -{ - __ASM volatile ("dsb"); -} - - -/** \brief Data Memory Barrier - - This function ensures the apparent order of the explicit memory operations before - and after the instruction, without ensuring their completion. - */ -__attribute__( ( always_inline ) ) __STATIC_INLINE void __DMB(void) -{ - __ASM volatile ("dmb"); -} - - -/** \brief Reverse byte order (32 bit) - - This function reverses the byte order in integer value. - - \param [in] value Value to reverse - \return Reversed value - */ -__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __REV(uint32_t value) -{ -#if (__GNUC__ > 4) || (__GNUC__ == 4 && __GNUC_MINOR__ >= 5) - return __builtin_bswap32(value); -#else - uint32_t result; - - __ASM volatile ("rev %0, %1" : __CMSIS_GCC_OUT_REG (result) : __CMSIS_GCC_USE_REG (value) ); - return(result); -#endif -} - - -/** \brief Reverse byte order (16 bit) - - This function reverses the byte order in two unsigned short values. - - \param [in] value Value to reverse - \return Reversed value - */ -__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __REV16(uint32_t value) -{ - uint32_t result; - - __ASM volatile ("rev16 %0, %1" : __CMSIS_GCC_OUT_REG (result) : __CMSIS_GCC_USE_REG (value) ); - return(result); -} - - -/** \brief Reverse byte order in signed short value - - This function reverses the byte order in a signed short value with sign extension to integer. - - \param [in] value Value to reverse - \return Reversed value - */ -__attribute__( ( always_inline ) ) __STATIC_INLINE int32_t __REVSH(int32_t value) -{ -#if (__GNUC__ > 4) || (__GNUC__ == 4 && __GNUC_MINOR__ >= 8) - return (short)__builtin_bswap16(value); -#else - uint32_t result; - - __ASM volatile ("revsh %0, %1" : __CMSIS_GCC_OUT_REG (result) : __CMSIS_GCC_USE_REG (value) ); - return(result); -#endif -} - - -/** \brief Rotate Right in unsigned value (32 bit) - - This function Rotate Right (immediate) provides the value of the contents of a register rotated by a variable number of bits. - - \param [in] value Value to rotate - \param [in] value Number of Bits to rotate - \return Rotated value - */ -__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __ROR(uint32_t op1, uint32_t op2) -{ - return (op1 >> op2) | (op1 << (32 - op2)); -} - - -/** \brief Breakpoint - - This function causes the processor to enter Debug state. - Debug tools can use this to investigate system state when the instruction at a particular address is reached. - - \param [in] value is ignored by the processor. - If required, a debugger can use it to store additional information about the breakpoint. - */ -#define __BKPT(value) __ASM volatile ("bkpt "#value) - - -#if (__CORTEX_M >= 0x03) - -/** \brief Reverse bit order of value - - This function reverses the bit order of the given value. - - \param [in] value Value to reverse - \return Reversed value - */ -__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __RBIT(uint32_t value) -{ - uint32_t result; - - __ASM volatile ("rbit %0, %1" : "=r" (result) : "r" (value) ); - return(result); -} - - -/** \brief LDR Exclusive (8 bit) - - This function performs a exclusive LDR command for 8 bit value. - - \param [in] ptr Pointer to data - \return value of type uint8_t at (*ptr) - */ -__attribute__( ( always_inline ) ) __STATIC_INLINE uint8_t __LDREXB(volatile uint8_t *addr) -{ - uint32_t result; - -#if (__GNUC__ > 4) || (__GNUC__ == 4 && __GNUC_MINOR__ >= 8) - __ASM volatile ("ldrexb %0, %1" : "=r" (result) : "Q" (*addr) ); -#else - /* Prior to GCC 4.8, "Q" will be expanded to [rx, #0] which is not - accepted by assembler. So has to use following less efficient pattern. - */ - __ASM volatile ("ldrexb %0, [%1]" : "=r" (result) : "r" (addr) : "memory" ); -#endif - return(result); -} - - -/** \brief LDR Exclusive (16 bit) - - This function performs a exclusive LDR command for 16 bit values. - - \param [in] ptr Pointer to data - \return value of type uint16_t at (*ptr) - */ -__attribute__( ( always_inline ) ) __STATIC_INLINE uint16_t __LDREXH(volatile uint16_t *addr) -{ - uint32_t result; - -#if (__GNUC__ > 4) || (__GNUC__ == 4 && __GNUC_MINOR__ >= 8) - __ASM volatile ("ldrexh %0, %1" : "=r" (result) : "Q" (*addr) ); -#else - /* Prior to GCC 4.8, "Q" will be expanded to [rx, #0] which is not - accepted by assembler. So has to use following less efficient pattern. - */ - __ASM volatile ("ldrexh %0, [%1]" : "=r" (result) : "r" (addr) : "memory" ); -#endif - return(result); -} - - -/** \brief LDR Exclusive (32 bit) - - This function performs a exclusive LDR command for 32 bit values. - - \param [in] ptr Pointer to data - \return value of type uint32_t at (*ptr) - */ -__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __LDREXW(volatile uint32_t *addr) -{ - uint32_t result; - - __ASM volatile ("ldrex %0, %1" : "=r" (result) : "Q" (*addr) ); - return(result); -} - - -/** \brief STR Exclusive (8 bit) - - This function performs a exclusive STR command for 8 bit values. - - \param [in] value Value to store - \param [in] ptr Pointer to location - \return 0 Function succeeded - \return 1 Function failed - */ -__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __STREXB(uint8_t value, volatile uint8_t *addr) -{ - uint32_t result; - - __ASM volatile ("strexb %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" (value) ); - return(result); -} - - -/** \brief STR Exclusive (16 bit) - - This function performs a exclusive STR command for 16 bit values. - - \param [in] value Value to store - \param [in] ptr Pointer to location - \return 0 Function succeeded - \return 1 Function failed - */ -__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __STREXH(uint16_t value, volatile uint16_t *addr) -{ - uint32_t result; - - __ASM volatile ("strexh %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" (value) ); - return(result); -} - - -/** \brief STR Exclusive (32 bit) - - This function performs a exclusive STR command for 32 bit values. - - \param [in] value Value to store - \param [in] ptr Pointer to location - \return 0 Function succeeded - \return 1 Function failed - */ -__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __STREXW(uint32_t value, volatile uint32_t *addr) -{ - uint32_t result; - - __ASM volatile ("strex %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" (value) ); - return(result); -} - - -/** \brief Remove the exclusive lock - - This function removes the exclusive lock which is created by LDREX. - - */ -__attribute__( ( always_inline ) ) __STATIC_INLINE void __CLREX(void) -{ - __ASM volatile ("clrex" ::: "memory"); -} - - -/** \brief Signed Saturate - - This function saturates a signed value. - - \param [in] value Value to be saturated - \param [in] sat Bit position to saturate to (1..32) - \return Saturated value - */ -#define __SSAT(ARG1,ARG2) \ -({ \ - uint32_t __RES, __ARG1 = (ARG1); \ - __ASM ("ssat %0, %1, %2" : "=r" (__RES) : "I" (ARG2), "r" (__ARG1) ); \ - __RES; \ - }) - - -/** \brief Unsigned Saturate - - This function saturates an unsigned value. - - \param [in] value Value to be saturated - \param [in] sat Bit position to saturate to (0..31) - \return Saturated value - */ -#define __USAT(ARG1,ARG2) \ -({ \ - uint32_t __RES, __ARG1 = (ARG1); \ - __ASM ("usat %0, %1, %2" : "=r" (__RES) : "I" (ARG2), "r" (__ARG1) ); \ - __RES; \ - }) - - -/** \brief Count leading zeros - - This function counts the number of leading zeros of a data value. - - \param [in] value Value to count the leading zeros - \return number of leading zeros in value - */ -__attribute__( ( always_inline ) ) __STATIC_INLINE uint8_t __CLZ(uint32_t value) -{ - uint32_t result; - - __ASM volatile ("clz %0, %1" : "=r" (result) : "r" (value) ); - return(result); -} - -#endif /* (__CORTEX_M >= 0x03) */ - - - - -#elif defined ( __TASKING__ ) /*------------------ TASKING Compiler --------------*/ -/* TASKING carm specific functions */ - -/* - * The CMSIS functions have been implemented as intrinsics in the compiler. - * Please use "carm -?i" to get an up to date list of all intrinsics, - * Including the CMSIS ones. - */ - -#endif - -/*@}*/ /* end of group CMSIS_Core_InstructionInterface */ - -#endif /* __CORE_CMINSTR_H */ diff --git a/bsp/essemi/es8p508x/libraries/CMSIS/startup_ES8P508x.s b/bsp/essemi/es8p508x/libraries/CMSIS/startup_ES8P508x.s deleted file mode 100644 index 69e528223e..0000000000 --- a/bsp/essemi/es8p508x/libraries/CMSIS/startup_ES8P508x.s +++ /dev/null @@ -1,233 +0,0 @@ -;******************************************************************************* -; *file : startup_ES8P508x.s -; *description: ES8P508x Device Startup File -; *author : Eastsoft MCU Software Team -; *version : V0.01 -; *data : 6/30/2017 -; -; *Copyright (C) 2017 Shanghai Eastsoft Microelectronics Co., Ltd. -; * -; * THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED -; * OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF -; * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE. -; * ARM SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR -; * CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER. -;******************************************************************************* - - -; Stack Configuration -; Stack Size (in Bytes) <0x0-0xFFFFFFFF:8> -; - -Stack_Size EQU 0x00000400 - - AREA STACK, NOINIT, READWRITE, ALIGN=3 -Stack_Mem SPACE Stack_Size -__initial_sp - - -; Heap Configuration -; Heap Size (in Bytes) <0x0-0xFFFFFFFF:8> -; - -Heap_Size EQU 0x00000400 - - AREA HEAP, NOINIT, READWRITE, ALIGN=3 -__heap_base -Heap_Mem SPACE Heap_Size -__heap_limit - - PRESERVE8 - THUMB - -; Vector Table Mapped to Address 0 at Reset - - AREA RESET, DATA, READONLY - EXPORT __Vectors - -__Vectors DCD __initial_sp ; Top of Stack - DCD Reset_IRQHandler ; Reset Handler - DCD NMI_IRQHandler ; NMI Handler - DCD HardFault_IRQHandler ; HardFault Handler - DCD 0 ; Reserved - DCD 0 ; Reserved - DCD 0 ; Reserved - DCD 0 ; Reserved - DCD 0 ; Reserved - DCD 0 ; Reserved - DCD 0 ; Reserved - DCD SVC_IRQHandler ; SVCall Handler - DCD 0 ; Reserved - DCD 0 ; Reserved - DCD PendSV_Handler ; PendSV Handler - DCD SysTick_Handler ; SysTick Handler - - ; External Interrupts - DCD PINT0_IRQHandler ;16, PINT0 IRQHandler - DCD PINT1_IRQHandler ;17, PINT1 IRQHandler - DCD PINT2_IRQHandler ;18, PINT2 IRQHandler - DCD PINT3_IRQHandler ;19, PINT3 IRQHandler - DCD PINT4_IRQHandler ;20, PINT4 IRQHandler - DCD PINT5_IRQHandler ;21, PINT5 IRQHandler - DCD PINT6_IRQHandler ;22, PINT6 IRQHandler - DCD PINT7_IRQHandler ;23, PINT7 IRQHandler - DCD T16N0_IRQHandler ;24, T16N0 IRQHandler - DCD T16N1_IRQHandler ;25, T16N1 IRQHandler - DCD T16N2_IRQHandler ;26, T16N2 IRQHandler - DCD T16N3_IRQHandler ;27, T16N3 IRQHandler - DCD T32N0_IRQHandler ;28, T32N0 IRQHandler - DCD 0 ;29, Reserved - DCD IWDT_IRQHandler ;30, IWDT IRQHandler - DCD WWDT_IRQHandler ;31, WWDT IRQHandler - DCD CCM_IRQHandler ;32, WDT IRQHandler - DCD PLK_IRQHandler ;33, PLK IRQHandler - DCD LVD_IRQHandler ;34, LVD IRQHandler - DCD KINT_IRQHandler ;35, KINT IRQHandler - DCD RTC_IRQHandler ;36, RTC IRQHandler - DCD ADC_IRQHandler ;37, ADC IRQHandler - DCD 0 ;38, Reserved - DCD AES_IRQHandler ;39, AES IRQHandler - DCD UART0_IRQHandler ;40, UART0 IRQHandler - DCD UART1_IRQHandler ;41, UART1 IRQHandler - DCD UART2_IRQHandler ;42, UART2 IRQHandler - DCD UART3_IRQHandler ;43, UART3 IRQHandler - DCD UART4_IRQHandler ;44, UART4 IRQHandler - DCD UART5_IRQHandler ;45, UART5 IRQHandler - DCD SPI0_IRQHandler ;46, SPI0 IRQHandler - DCD I2C0_IRQHandler ;47, I2C0 IRQHandler - - AREA |.text|, CODE, READONLY - -; Reset Handler - -Reset_IRQHandler PROC - EXPORT Reset_IRQHandler [WEAK] - IMPORT __main - IMPORT SystemInit - LDR R0, =SystemInit - BLX R0 - LDR R0, =__main - BX R0 - ENDP - -; Dummy Exception IRQHandlers (infinite loops which can be modified) - -NMI_IRQHandler PROC - EXPORT NMI_IRQHandler [WEAK] - B . - ENDP -HardFault_IRQHandler PROC - EXPORT HardFault_IRQHandler [WEAK] - B . - ENDP -SVC_IRQHandler PROC - EXPORT SVC_IRQHandler [WEAK] - B . - ENDP -PendSV_Handler PROC - EXPORT PendSV_Handler [WEAK] - B . - ENDP -SysTick_Handler PROC - EXPORT SysTick_Handler [WEAK] - B . - ENDP - -Default_IRQHandler PROC - EXPORT PINT0_IRQHandler [WEAK] - EXPORT PINT1_IRQHandler [WEAK] - EXPORT PINT2_IRQHandler [WEAK] - EXPORT PINT3_IRQHandler [WEAK] - EXPORT PINT4_IRQHandler [WEAK] - EXPORT PINT5_IRQHandler [WEAK] - EXPORT PINT6_IRQHandler [WEAK] - EXPORT PINT7_IRQHandler [WEAK] - EXPORT T16N0_IRQHandler [WEAK] - EXPORT T16N1_IRQHandler [WEAK] - EXPORT T16N2_IRQHandler [WEAK] - EXPORT T16N3_IRQHandler [WEAK] - EXPORT T32N0_IRQHandler [WEAK] - EXPORT IWDT_IRQHandler [WEAK] - EXPORT WWDT_IRQHandler [WEAK] - EXPORT CCM_IRQHandler [WEAK] - EXPORT PLK_IRQHandler [WEAK] - EXPORT LVD_IRQHandler [WEAK] - EXPORT KINT_IRQHandler [WEAK] - EXPORT RTC_IRQHandler [WEAK] - EXPORT ADC_IRQHandler [WEAK] - EXPORT AES_IRQHandler [WEAK] - EXPORT UART0_IRQHandler [WEAK] - EXPORT UART1_IRQHandler [WEAK] - EXPORT UART2_IRQHandler [WEAK] - EXPORT UART3_IRQHandler [WEAK] - EXPORT UART4_IRQHandler [WEAK] - EXPORT UART5_IRQHandler [WEAK] - EXPORT SPI0_IRQHandler [WEAK] - EXPORT I2C0_IRQHandler [WEAK] - - - -PINT0_IRQHandler -PINT1_IRQHandler -PINT2_IRQHandler -PINT3_IRQHandler -PINT4_IRQHandler -PINT5_IRQHandler -PINT6_IRQHandler -PINT7_IRQHandler -T16N0_IRQHandler -T16N1_IRQHandler -T16N2_IRQHandler -T16N3_IRQHandler -T32N0_IRQHandler -IWDT_IRQHandler -WWDT_IRQHandler -CCM_IRQHandler -PLK_IRQHandler -LVD_IRQHandler -KINT_IRQHandler -RTC_IRQHandler -ADC_IRQHandler -AES_IRQHandler -UART0_IRQHandler -UART1_IRQHandler -UART2_IRQHandler -UART3_IRQHandler -UART4_IRQHandler -UART5_IRQHandler -SPI0_IRQHandler -I2C0_IRQHandler - - B . - - ENDP - - - - ALIGN - -; User Initial Stack & Heap - - IF :DEF:__MICROLIB - - EXPORT __initial_sp - EXPORT __heap_base - EXPORT __heap_limit - - ELSE - - IMPORT __use_two_region_memory - EXPORT __user_initial_stackheap -__user_initial_stackheap - - LDR R0, = Heap_Mem - LDR R1, =(Stack_Mem + Stack_Size) - LDR R2, = (Heap_Mem + Heap_Size) - LDR R3, = Stack_Mem - BX LR - - ALIGN - - ENDIF - - END diff --git a/bsp/essemi/es8p508x/libraries/CMSIS/system_ES8P508x.c b/bsp/essemi/es8p508x/libraries/CMSIS/system_ES8P508x.c deleted file mode 100644 index eb22f8c9da..0000000000 --- a/bsp/essemi/es8p508x/libraries/CMSIS/system_ES8P508x.c +++ /dev/null @@ -1,76 +0,0 @@ -/*************************************************************** -*Copyright (C), 2017, Shanghai Eastsoft Microelectronics Co., Ltd -*ļ system_ES8P508x.c -* ߣ Liut -* V1.00 -* ڣ 2017/07/14 -* ⺯ļ -* ע ES8P508xоƬ - ѧϰʾʹãûֱôķջеκηΡ -***************************************************************/ -#include "system_ES8P508x.h" -#include "lib_config.h" - -uint32_t SystemCoreClock = 48000000; - - -/*************************************************************** -SystemCoreClockUpdate - ϵͳʱΪڲʱ20MHZͬʱSystemCoreClock -ֵ -ֵ -ֵ -***************************************************************/ -void SystemCoreClockUpdate (void) -{ - uint32_t Prot_Temp; - uint16_t Count=0; - SystemClockSelect(SCU_SysClk_HRC , CLK_SEL_HRC); //ѡϵͳʱΪHRCʱ - PLLClock_Config(DISABLE, SCU_PLL_HRC, SCU_PLL_48M,ENABLE); //PLLֹ - Prot_Temp = SCU->PROT.PROT; - if(Prot_Temp != 0) //д - {SCU->PROT.Word = 0x55AA6996;} // - - SCU->SCLKEN1.HRC_EN = 1; //ʹڲ20MHZ - do - { - Count++; - } - while((SCU->SCLKEN1.HRC_RDY == 0)&&(Count != 0xFFF)); //ȴʱӿ - - if(Count == 0xFFF) - { - return ; - } - - SCU->SCLKEN0.SYSCLK_DIV = 0; //ϵͳʱӺƵ1:1 - - switch(SCU->SCLKEN0.CLK_SEL) - { - case 0: - SystemCoreClock = 20000000; //HRC - break; - case 1: - SystemCoreClock = 32000; //LRC - break; - default: - break; - } - - if(Prot_Temp != 0) //д - {SCU->PROT.Word = 0x00000000;} //д -} - -/*************************************************************** -SystemInit - ϵͳʼʱ -ֵ -ֵ -ֵ -***************************************************************/ -void SystemInit (void) -{ - SystemCoreClockUpdate(); -} - -/*************************END OF FILE**********************/ diff --git a/bsp/essemi/es8p508x/libraries/CMSIS/system_ES8P508x.h b/bsp/essemi/es8p508x/libraries/CMSIS/system_ES8P508x.h deleted file mode 100644 index b0fa1595c9..0000000000 --- a/bsp/essemi/es8p508x/libraries/CMSIS/system_ES8P508x.h +++ /dev/null @@ -1,23 +0,0 @@ -/*************************************************************** -*Copyright (C), 2017, Shanghai Eastsoft Microelectronics Co., Ltd. -*ļ system_ES8P508x.h -* ߣ Liut -* V1.00 -* ڣ 2017/07/14 -* ⺯ļ -* ע ES8P508xоƬ - ѧϰʾʹãûֱôķջеκηΡ -***************************************************************/ -#ifndef __SYSTEMES8P508x_H__ -#define __SYSTEMES8P508x_H__ - -#include "ES8P508x.h" -#include "type.h" - -extern uint32_t SystemCoreClock; -extern void SystemInit(void); -extern void SystemCoreClockUpdate(void); - -#endif - -/*************************END OF FILE**********************/ diff --git a/bsp/essemi/es8p508x/libraries/Library/Include/irqhandler.h b/bsp/essemi/es8p508x/libraries/Library/Include/irqhandler.h deleted file mode 100644 index fec6f2d62d..0000000000 --- a/bsp/essemi/es8p508x/libraries/Library/Include/irqhandler.h +++ /dev/null @@ -1,17 +0,0 @@ - -#ifndef __IRQHANDLER_H__ -#define __IRQHANDLER_H__ - -#include "ES8P508x.h" - -extern void systick_irq_cbk(void); - -/************жϺ***********/ -void NMI_IRQHandler(void); -void HardFault_IRQHandler(void); -void SVC_IRQHandler(void); -void PendSV_IRQHandler(void); -void SysTick_IRQHandler(void); - -#endif - diff --git a/bsp/essemi/es8p508x/libraries/Library/Include/lib_adc.h b/bsp/essemi/es8p508x/libraries/Library/Include/lib_adc.h deleted file mode 100644 index afcb552435..0000000000 --- a/bsp/essemi/es8p508x/libraries/Library/Include/lib_adc.h +++ /dev/null @@ -1,239 +0,0 @@ -/*************************************************************** - *Copyright (C), 2017, Shanghai Eastsoft Microelectronics Co., Ltd - *ļ lib_timer.c - * ߣ Liut - * V1.00 - * ڣ 2017/07/14 - * ADCģ⺯ - * ע ES8P508xоƬ - ѧϰʾʹãûֱôķջеκηΡ - ***************************************************************/ -#ifndef __LIBADC_H__ -#define __LIBADC_H__ - -#include "ES8P508x.h" -#include "type.h" - -/* ڲοѹѡ */ -typedef enum { - ADC_VREF_SEL_2_0 = 0, /* ڲοѹ2.048v*/ - ADC_VREF_SEL_1_6 = 1, /* ڲοѹ1.6v*/ - ADC_VREF_SEL_MAX = 1, -}ADC_TYPE_VREF_SEL; - -/* ADCʱԴѡ */ -typedef enum -{ - ADC_ClkS_PCLK = 0x0 , //ʱӣPCLK - ADC_ClkS_PLL = 0x1 , //ʱӣPLL - ADC_ClkS_32K = 0x2 , //ʱӣADCCLK(32KHZ) -}ADC_TYPE_CLKS; - -/* ADCʱԴԤƵ */ -typedef enum -{ - ADC_ClkDiv_1 = 0x0 , //ԤƵ1:1 - ADC_ClkDiv_2 = 0x1 , //ԤƵ1:2 - ADC_ClkDiv_4 = 0x2 , //ԤƵ1:4 - ADC_ClkDiv_8 = 0x3 , //ԤƵ1:8 - ADC_ClkDiv_16 = 0x4 , //ԤƵ1:16 - ADC_ClkDiv_32 = 0x5 , //ԤƵ1:32 - ADC_ClkDiv_64 = 0x6 , //ԤƵ1:64 - ADC_ClkDiv_256 = 0x7 , //ԤƵ1:256 -}ADC_TYPE_CLKDIV; - -/* οѹѡ */ -typedef enum -{ - ADC_VrefP_Vcc = 0x0 , //οѹVDDѹ - ADC_VrefP_Exter = 0x3 , //οѹⲿοѹ -}ADC_TYPE_VREFP; - -/* ģʽѡ */ -typedef enum -{ - ADC_SMPS_SOFT = 0, /* */ - ADC_SMPS_HARD = 1, /* Ӳ */ -}ADC_TYPE_SMPS; - - -/* תٶѡ */ -typedef enum -{ - ADC_ConvSpeed_Low = 0x0 , //ADתٶȣ - ADC_ConvSpeed_High = 0x1 , //ADתٶȣ -}ADC_TYPE_HSEN; - -/* ADCͨѡ */ -typedef enum -{ - ADC_CHS_AIN0 = 0, /* ͨ 0 */ - ADC_CHS_AIN1 = 1, /* ͨ 1 */ - ADC_CHS_AIN2 = 2, /* ͨ 2 */ - ADC_CHS_AIN3 = 3, /* ͨ 3 */ - ADC_CHS_AIN4 = 4, /* ͨ 4 */ - ADC_CHS_AIN5 = 5, /* ͨ 5 */ - ADC_CHS_AIN6 = 6, /* ͨ 6 */ - ADC_CHS_AIN7 = 7, /* ͨ 7 */ - ADC_CHS_AIN8 = 8, /* ͨ 8 */ - ADC_CHS_AIN9 = 9, /* ͨ 9 */ - ADC_CHS_AIN10 = 10, /* ͨ 10 */ - ADC_CHS_AIN11 = 11, /* ͨ 11 */ - ADC_CHS_AIN12 = 12, /* ͨ 12 */ - ADC_CHS_AIN13 = 13, /* ͨ 13 */ - ADC_CHS_AIN14 = 14, /* ͨ 14 */ - ADC_CHS_AIN15 = 15, /* ͨ 15 */ -}ADC_TYPE_CHS; - -/*ADC coreѡλ*/ -typedef enum -{ - ADC_LP_86ua = 2, //ADC Core Ϊ86Ƽʹ - ADC_LP_215ua = 0, //ADC Core Ϊ215uA - ADC_LP_120ua = 1, //ADC Core Ϊ120uA - ADC_LP_70ua = 3, //ADC Core Ϊ70uA -}ADC_TYPE_BUFLP; - -/*ADC buffѡλ*/ -typedef enum -{ - ADC_BUFF_0ua = 0, //ADC buffΪ0uAƼʹ - ADC_BUFF_34ua = 1, //ADC buffΪ34uA - ADC_BUFF_95ua = 2, //ADC buffΪ95uA -}ADC_TYPE_BUFEN; - -/* ADC IF ״̬ */ -typedef enum -{ - ADC_IF = 0x01, - ADC_IF_ACPMIN = 0x02, - ADC_IF_ACPMAX =0x04, - ADC_IF_ACPOVER = 0x08, -}ADC_TYPE_IF; - -/* ADC IE ״̬ */ -typedef enum -{ - ADC_IE = 0x01, - ADC_IE_ACPMIN = 0x02, - ADC_IE_ACPMAX =0x04, - ADC_IE_ACPOVER = 0x08, -}ADC_TYPE_IE; - -/* ADCʼýṹ嶨 */ -typedef struct -{ - ADC_TYPE_CLKS ADC_ClkS; //ADCCON1:bit3 ADCʱԴѡ - ADC_TYPE_CLKDIV ADC_ClkDiv; //ADCCON1:bit2-0 ADCʱԴԤƵ - ADC_TYPE_VREFP ADC_VrefP; //ADCCON1:bit9-8 ADCοѹѡ - ADC_TYPE_SMPS ADC_SampS; //ADCCON1:bit12 ADCģʽѡ - ADC_TYPE_CHS ADC_ChS; //ADCCHS:bit0-3 ADCģͨѡ - //ADC_TYPE_VREF_SEL VREF_SEL; //οѹѡ - uint8_t ST; //Ӳʱ (ģʽΪӲʱ) 0~31 - TYPE_FUNCEN ADC_VREFN; //οѹѡλ - TYPE_FUNCEN ADC_VRBUF_EN; -}ADC_InitStruType; - -/* ԶȽϵͷֵ ѡ*/ -typedef enum -{ - ADC_ACP_MIN_MIN = 0x0, /* Сͷֵ*/ - ADC_ACP_MIN_MAX = 0xfff, /* ͷֵ*/ -}ADC_TYPE_ACP_MIN; - -/* ԶȽϸ߷ֵ ѡ*/ -typedef enum -{ - ADC_ACP_MAX_MIN = 0x0, /* С߷ֵ*/ - ADC_ACP_MAX_MAX = 0xfff, /* ߷ֵ*/ -}ADC_TYPE_ACP_MAX; - -/* ÿԶתȽʱѡ */ -typedef enum -{ - ADC_ACPC_OVFL_TIME_MAX = 0x9c3, /* ʱ */ -}ADC_TYPE_ACPC_OVFL_TIME; - -/* ԶתȽϴ */ -typedef enum -{ - ADC_ACPC_TIMES_1 = 0, /* 1 */ - ADC_ACPC_TIMES_2 = 1, /* 2 */ - ADC_ACPC_TIMES_4 = 2, /* 4 */ - ADC_ACPC_TIMES_8 = 3, /* 8 */ - ADC_ACPC_TIMES_MAX = 3, -}ADC_TYPE_ACPC_TIMES; - -/* ACPʱӵʱԴ */ -typedef enum -{ - ADC_ACPC_CLKS_PCLK = 0, /* PCLK */ - ADC_ACPC_CLKS_LRC = 1, /* LRC(32KHz) */ -}ADC_TYPE_ACPC_CLKS; - -typedef FuncState ADC_TYPE_CHOP_EN1, ADC_TYPE_CHOP_EN; -typedef FuncState ADC_TYPE_VREF_EN,ADC_TYPE_IREF_EN; -typedef FuncState ADC_TYPE_EN,ADC_TYPE_ACP_EN; - -/* ԶȽϹܳʼṹ*/ -typedef struct -{ - ADC_TYPE_ACP_EN ACP_EN; /* ԶȽϹʹλ*/ - uint16_t ACPC_OVER_TIME; /* ԶȽʱ(ʹó0) 0~0x9c3 */ - ADC_TYPE_ACPC_TIMES ACPC_TIMES; /* ԶȽϴ(ȼʱ) */ - uint16_t ACPC_MIN_TARGET; /* ƽֵͷֵ (0xfffر) 0~0xfff */ - uint16_t ACPC_MAX_TARGET; /* ƽֵ߷ֵ (0x0ر) 0~0xfff */ -}ADC_ACP_TypeDef; - -/************ADCģ궨***********/ -/* ADCʹܿ */ -#define ADC_Enable() (ADC->CON0.EN = 0x1) -#define ADC_Disable() (ADC->CON0.EN = 0x0) - -/* ԶȽϹʹ*/ -#define ADC_ACP_Enable() (ADC->CON0.ACP_EN = 1) -#define ADC_ACP_Disable() (ADC->CON0.ACP_EN = 0) - -/* ADCʼת */ -#define ADC_Start() (ADC->CON0.TRIG = 0x1) - -/* ADC */ -#define ADC_SampStart() (ADC->CON1.SMPON = 0x1) -#define ADC_SampStop() (ADC->CON1.SMPON = 0x0) - -/* ADC VDD */ -#define ADC_VDD5_FLAG_Enable() (ADC->CHS.VDD5_FLAG_EN = 0x1) -#define ADC_VDD5_FLAG_Disable() (ADC->CHS.VDD5_FLAG_EN = 0x0) - -/* ADCжʹܿ */ -#define ADC_IE_Enable() (ADC->IE.IE = 0x1) -#define ADC_IE_Disable() (ADC->IE.IE = 0x0) - -#define ADC_ACPMINIE_Enable() (ADC->IE.ACPMINIE = 1) -#define ADC_ACPMINIE_Disable() (ADC->IE.ACPMINIE = 0) - -#define ADC_ACPMAXIE_Enable() (ADC->IE.ACPMAXIE = 1) -#define ADC_ACPMAXIE_Disable() (ADC->IE.ACPMAXIE = 0) - -#define ADC_ACPOVIE_Enable() (ADC->IE.ACPOVIE = 1) -#define ADC_ACPOVIE_Disable() (ADC->IE.ACPOVIE = 0) - -/************ADCģ麯***********/ -void ADC_Init(ADC_InitStruType * ADC_InitStruct); -void ADC_Set_CH(ADC_TYPE_CHS AdcCH); -uint16_t ADC_GetConvValue(void); -FlagStatus ADC_GetConvStatus(void); -ErrorStatus ADC_ACPConfig(ADC_ACP_TypeDef *ADC_ACP_InitStruct); -ErrorStatus ADC_SoftStart(void); -ErrorStatus ADC_SoftStop(void); -uint16_t ADC_GetACPMeanValue(void); -uint16_t ADC_GetACPMinValue(void); -uint16_t ADC_GetACPMaxValue(void); -FlagStatus ADC_GetFlagStatus(ADC_TYPE_IF IFName); -ITStatus ADC_GetITStatus(ADC_TYPE_IE IEName); -ErrorStatus ADC_ClearIFStatus(ADC_TYPE_IF IFName); -void ADC_Reset(void); - -#endif - -/*************************END OF FILE**********************/ diff --git a/bsp/essemi/es8p508x/libraries/Library/Include/lib_aes.h b/bsp/essemi/es8p508x/libraries/Library/Include/lib_aes.h deleted file mode 100644 index 13c8046278..0000000000 --- a/bsp/essemi/es8p508x/libraries/Library/Include/lib_aes.h +++ /dev/null @@ -1,74 +0,0 @@ -/*************************************************************** - *Copyright (C), 2017, Shanghai Eastsoft Microelectronics Co., Ltd - *ļ lib_aes.c - * ߣ zoux - * V1.00 - * ڣ 2017/07/14 - * AESģ⺯ - * ע ES8P508xоƬ - ѧϰʾʹãûֱôķջеκηΡ - ***************************************************************/ -#ifndef __LIBAES_H__ -#define __LIBAES_H__ - -#include "ES8P508x.h" -#include "type.h" - -/* ܽģʽѡλ */ -typedef enum { - AES_MODE_DECRYPT = 0, /* */ - AES_MODE_ENCRYPT = 1, /* */ -}AES_TYPE_MODE; - -/* /ܿλ */ -typedef enum { - AES_DONE_YES = 0, /* */ - AES_DONE_NO = 1, /* ڼ */ -}AES_TYPE_DONE; - -/* ӽݽṹ */ -typedef struct { - uint32_t DATA[4]; -}AES_DATA_TypeDef; - -typedef enum { - AES_IF_IF = 0x80, -}AES_TYPE_IF; - -typedef enum { - AES_IT_IT = 0x40, -}AES_TYPE_IT; - -/* ӽԿṹ */ -typedef struct { - uint32_t KEY[4]; -}AES_KEY_TypeDef; - -/* ӽܳʼṹ */ -typedef struct { - AES_TYPE_MODE MODE; /* ܻ߽ */ -}AES_InitStruType; - -/* ӽʹܣʼ */ -#define AES_Enable() (AES->CON.GO_DONE = 1) -/* ģر */ -#define AES_Disable() (AES->CON.GO_DONE = 0) - - -/********************* ADCģ麯 *********************/ -void AES_Init(AES_InitStruType * AES_InitStruct); -void AES_WriteKey(uint32_t *AES_KEY); -void AES_ReadKey(uint32_t * AES_KEY); - -void AES_WriteData(uint32_t *AES_DATA); -void AES_ReadData(uint32_t * AES_DATA); - -void AES_ITConfig(AES_TYPE_IT AES_IE, TYPE_FUNCEN NewState); -void AES_ClearITPendingBit(void); -FlagStatus AES_GetFlagStatus(AES_TYPE_IF Flag); - -AES_TYPE_DONE AES_GetDoneStatus(void); -void AES_Reset(void); - -#endif - diff --git a/bsp/essemi/es8p508x/libraries/Library/Include/lib_config.h b/bsp/essemi/es8p508x/libraries/Library/Include/lib_config.h deleted file mode 100644 index 8178813ca9..0000000000 --- a/bsp/essemi/es8p508x/libraries/Library/Include/lib_config.h +++ /dev/null @@ -1,32 +0,0 @@ -/*************************************************************** - *Copyright (C), 2017, Shanghai Eastsoft Microelectronics Co., Ltd. - *ļ lib_config.h - * : Liut - * : V1.00 - * : 2017/07/14 - * ⺯ļ - * ע ES8P508xоƬ - ѧϰʾʹãûֱôķջеκηΡ - ***************************************************************/ -#ifndef __LIBCONFIG_H__ -#define __LIBCONFIG_H__ - -#include "lib_adc.h" -#include "lib_iic.h" -#include "lib_scs.h" -#include "lib_scu.h" -#include "lib_spi.h" -#include "lib_timer.h" -#include "lib_uart.h" -#include "lib_wdt.h" -#include "lib_flashiap.h" -#include "lib_gpio.h" -#include "lib_printf.h" -#include "lib_iap.h" -#include "lib_crc.h" -#include "lib_aes.h" -#include "lib_rtc.h" - -#endif - -/*************************END OF FILE**********************/ diff --git a/bsp/essemi/es8p508x/libraries/Library/Include/lib_crc.h b/bsp/essemi/es8p508x/libraries/Library/Include/lib_crc.h deleted file mode 100644 index 1ab36cca7b..0000000000 --- a/bsp/essemi/es8p508x/libraries/Library/Include/lib_crc.h +++ /dev/null @@ -1,93 +0,0 @@ -/*************************************************************** - *Copyright (C), 2017, Shanghai Eastsoft Microelectronics Co., Ltd. - *ļ - * : Liut - * : V1.00 - * : 2017/07/14 - * - * ע ES8P508xоƬ - ѧϰʾʹãûֱôķջеκηΡ - ***************************************************************/ -#ifndef __LIBCRC_H -#define __LIBCRC_H - -#include "ES8P508x.h" -#include "type.h" - -#ifdef __cplusplus -extern "C" { -#endif - -#define CRC_EmptayCheck_addr 0x10000010 -#define CRC_FlashVerify_addr 0x10000014 -#define CRC_UserCal_addr 0x10000018 -#define CRC_CheckReset_addr 0x1000001C - -typedef uint32_t (*CRC_EM)(void* address, uint32_t data_len); -typedef uint32_t (*CRC_FL)(void* address, uint32_t data_len, uint32_t type); -typedef uint32_t (*CRC_US)(void* address, uint32_t data_len, uint32_t type); -typedef uint32_t (*CRC_CH)(void); - - -typedef enum -{ - CRC_XOROUT_NORMAL = 0x0, //ȡ - CRC_XOROUT_ANTI = (1U<<14), //ȡ -} CRC_XOROUT; - -typedef enum -{ - CRC_REFOUT_NORMAL = 0x0, // - CRC_REFOUT_REVERSE = (1U<<13), // -} CRC_REFOUT; - -typedef enum -{ - CRC_REFIN_NORMAL = 0x0, // - CRC_REFIN_REVERSE = (1U<<12), //뵹 -} CRC_REFIN; - - -typedef enum -{ - CRC_MOD_CRC32 = 0x0, //CRCλΪֽ - CRC_MOD_CRC16 = (2U<<8), //CRCλΪ - CRC_MOD_CRC16_CCITT = (3U<<8), //CRCλΪ -} CRC_MOD_TYPE; - -typedef enum -{ - CRC_INIT_DATA_ALL_0 = 0x0, //CRCʼȫΪ0 - CRC_INIT_DATA_ALL_1 = (1U<<3), //CRCʼȫΪ1 -} CRC_INIT_DATA; - -typedef enum -{ - CRC_HS_TYPE_DISABLE = 0x0, //CRCģʽֹ - CRC_HS_TYPE_ENABLE = (1U<<2), //CRCģʽʹܣCRCʱС24Mʱʹ -} CRC_HS_TYPE; - - -/*CRC_CON ֵṹʼ*/ -typedef struct -{ - CRC_XOROUT xorout; - CRC_REFOUT refout; - CRC_REFIN refin; - CRC_MOD_TYPE mode; - CRC_INIT_DATA init_data_type; - CRC_HS_TYPE hs_type; -} CRC_CONValueStruType; - -uint32_t CRC_getTypeValue(CRC_CONValueStruType con_value); -uint32_t CRC_EmptayCheck(void* address, uint32_t data_len); -uint32_t CRC_FlashVerify(void* address, uint32_t data_len, uint32_t type); -uint32_t CRC_UserCal(void* address, uint32_t data_len, uint32_t type); -uint32_t CRC_CheckReset(void); - -#ifdef __cplusplus -} -#endif - -#endif -/*************************END OF FILE**********************/ diff --git a/bsp/essemi/es8p508x/libraries/Library/Include/lib_flashiap.h b/bsp/essemi/es8p508x/libraries/Library/Include/lib_flashiap.h deleted file mode 100644 index b297e08712..0000000000 --- a/bsp/essemi/es8p508x/libraries/Library/Include/lib_flashiap.h +++ /dev/null @@ -1,44 +0,0 @@ -/*************************************************************** - *Copyright (C), 2017, Shanghai Eastsoft Microelectronics Co., Ltd. - *ļ lib_flashiap.h - * ߣ Liut - * V1.00 - * ڣ 2017/07/14 - * flashд⺯ͷļ - * ע ES8P508xоƬ - ѧϰʾʹãûֱôķջеκηΡ - ***************************************************************/ -#ifndef __LIBIAP_H__ -#define __LIBIAP_H__ - -#include "ES8P508x.h" -#include "type.h" - -/*************IAPģ궨************/ - -/* Ĵ */ -#define FlashIAP_RegUnLock() (IAP->UL.UL = 0x49415055) -#define FlashIAP_RegLock() (IAP->UL.UL = 0x00000000) - -/* ʹIAP */ -#define FlashIAP_Enable() (IAP->CON.EN = 0x1) -#define FlashIAP_Disable() (IAP->CON.EN = 0x0) - -/* IAP */ -#define FlashIAP_REQ() (IAP->CON.FLASH_REQ = 0x1) - -/************Flashģ麯***********/ -ErrorStatus FlashIap_Close_WPROT(uint8_t Page); -ErrorStatus FlashIap_Open_WPROT(uint8_t Page); -ErrorStatus FlashIap_CloseAll_WPROT(void); -ErrorStatus FlashIap_OpenAll_WPROT(void); -ErrorStatus FlashIap_Unlock(void); -ErrorStatus FlashIap_WriteEnd(void); -ErrorStatus FlashIap_ErasePage(uint8_t Page_Addr); -ErrorStatus FlashIap_WriteCont(uint8_t Unit_addr, uint8_t Page_addr, uint32_t Data32); -ErrorStatus FlashIap_WriteWord(uint8_t Unit_addr, uint8_t Page_addr, uint32_t Data32); -ErrorStatus Flash_Read(uint32_t * Ram_Addr, uint32_t Flash_Addr, uint8_t Len); - -#endif -/*************************END OF FILE**********************/ - diff --git a/bsp/essemi/es8p508x/libraries/Library/Include/lib_gpio.h b/bsp/essemi/es8p508x/libraries/Library/Include/lib_gpio.h deleted file mode 100644 index 301c6b286c..0000000000 --- a/bsp/essemi/es8p508x/libraries/Library/Include/lib_gpio.h +++ /dev/null @@ -1,243 +0,0 @@ -/*************************************************************** - *Copyright (C), 2017, Shanghai Eastsoft Microelectronics Co., Ltd. - *ļ lib_gpio.h - * ߣ Liut - * V1.00 - * ڣ 2017/07/14 - * GPIOģ鼰ⲿжϡжϿ⺯ͷļ - * ע ES8P508xоƬ - ѧϰʾʹãûֱôķջеκηΡ - ***************************************************************/ -#ifndef __LIBGPIO_H__ -#define __LIBGPIO_H__ - -#include "ES8P508x.h" -#include "type.h" - -/*״̬*/ - -/*˿ڶ*/ -typedef enum -{ - GPIOA = 0x0 , - GPIOB = 0x1 , -}GPIO_TYPE; - -/*Ŷ*/ -typedef enum -{ - GPIO_Pin_0 = 0x00, - GPIO_Pin_1 = 0x01, - GPIO_Pin_2 = 0x02, - GPIO_Pin_3 = 0x03, - GPIO_Pin_4 = 0x04, - GPIO_Pin_5 = 0x05, - GPIO_Pin_6 = 0x06, - GPIO_Pin_7 = 0x07, - GPIO_Pin_8 = 0x08, - GPIO_Pin_9 = 0x09, - GPIO_Pin_10 = 0x0A, - GPIO_Pin_11 = 0x0B, - GPIO_Pin_12 = 0x0C, - GPIO_Pin_13 = 0x0D, - GPIO_Pin_14 = 0x0E, - GPIO_Pin_15 = 0x0F, - GPIO_Pin_16 = 0x10, - GPIO_Pin_17 = 0x11, - GPIO_Pin_18 = 0x12, - GPIO_Pin_19 = 0x13, - GPIO_Pin_20 = 0x14, - GPIO_Pin_21 = 0x15, - GPIO_Pin_22 = 0x16, - GPIO_Pin_23 = 0x17, - GPIO_Pin_24 = 0x18, - GPIO_Pin_25 = 0x19, - GPIO_Pin_26 = 0x1A, - GPIO_Pin_27 = 0x1B, - GPIO_Pin_28 = 0x1C, - GPIO_Pin_29 = 0x1D, - GPIO_Pin_30 = 0x1E, - GPIO_Pin_31 = 0x1F, -}GPIO_TYPE_PIN; - -/* Źѡ */ -typedef enum -{ - GPIO_Func_0 = 0x0 , - GPIO_Func_1 = 0x1 , - GPIO_Func_2 = 0x2 , - GPIO_Func_3 = 0x3 , -}GPIO_TYPE_FUNC; - -/* ŷѡ */ -typedef enum -{ - GPIO_Dir_Out = 0x0 , - GPIO_Dir_In = 0x1 , -}GPIO_TYPE_DIR; - -/* ѡ */ -typedef enum -{ - GPIO_DS_Output_Normal = 0, // ͨ - GPIO_DS_Output_Strong = 1, // ǿ -} GPIO_TYPE_DS; - -/* ź */ -typedef enum { - GPIO_Pin_Signal_Digital = 0, // ź - GPIO_Pin_Signal_Analog = 1, // ģź -} GPIO_Pin_Signal; - -/* ʹ */ -typedef enum { - GPIO_PUE_Input_Disable = 0, // ֹ - GPIO_PUE_Input_Enable = 1, // ʹ -} GPIO_PUE_Input; - -/* ʹ */ -typedef enum { - GPIO_PDE_Input_Disable = 0, // ֹ - GPIO_PDE_Input_Enable = 1, // ʹ -} GPIO_PDE_Input; - - -/* ©ʹλ */ -typedef enum { - GPIO_ODE_Output_Disable = 0, // ©ֹ - GPIO_ODE_Output_Enable = 1, // ©ʹ -} GPIO_ODE_Output; - -/* GPIOʼýṹ嶨 */ -typedef struct -{ - GPIO_Pin_Signal GPIO_Signal; /* ϵźֻͣģ */ - GPIO_TYPE_FUNC GPIO_Func; //Źѡ - GPIO_TYPE_DIR GPIO_Direction; //ѡ - GPIO_PUE_Input GPIO_PUEN; //ʹ - GPIO_PDE_Input GPIO_PDEN; //ʹ - GPIO_ODE_Output GPIO_OD; //ģʽ©ʹ - GPIO_TYPE_DS GPIO_DS; // -}GPIO_InitStruType; - -/* PINT */ -typedef enum -{ - PINT0 = 0x0 , - PINT1 = 0x1 , - PINT2 = 0x2 , - PINT3 = 0x3 , - PINT4 = 0x4 , - PINT5 = 0x5 , - PINT6 = 0x6 , - PINT7 = 0x7 , -}PINT_TYPE; - -/* PINT SEL */ -typedef enum -{ - PINT_SEL0 = 0x0 , - PINT_SEL1 = 0x1 , - PINT_SEL2 = 0x2 , - PINT_SEL3 = 0x3 , - PINT_SEL4 = 0x4 , - PINT_SEL5 = 0x5 , - PINT_SEL6 = 0x6 , - PINT_SEL7 = 0x7 , -}PINT_TYPE_SEL; - -/* PINT Trigger */ -typedef enum -{ - PINT_Trig_Rise = 0x0 , - PINT_Trig_Fall = 0x1 , - PINT_Trig_High = 0x2 , - PINT_Trig_Low = 0x3 , - PINT_Trig_Change = 0x4 , -}PINT_TYPE_TRIG; - - -/* PINTжϱ־ */ -typedef enum -{ - PINT_IT_PINT0 = 0x01 , - PINT_IT_PINT1 = 0x02 , - PINT_IT_PINT2 = 0x04 , - PINT_IT_PINT3 = 0x08 , - PINT_IT_PINT4 = 0x10 , - PINT_IT_PINT5 = 0x20 , - PINT_IT_PINT6 = 0x40 , - PINT_IT_PINT7 = 0x80 , - PINT_IT_PINTAll = 0xFF , -}PINT_TYPE_IT; - -/* PINTʹܿ */ -#define PINT0_Enable() (GPIO->PINTIE.PINTIE |= 0X1) -#define PINT1_Enable() (GPIO->PINTIE.PINTIE |= 0x2) -#define PINT2_Enable() (GPIO->PINTIE.PINTIE |= 0x4) -#define PINT3_Enable() (GPIO->PINTIE.PINTIE |= 0x8) -#define PINT4_Enable() (GPIO->PINTIE.PINTIE |= 0x10) -#define PINT5_Enable() (GPIO->PINTIE.PINTIE |= 0x20) -#define PINT6_Enable() (GPIO->PINTIE.PINTIE |= 0x40) -#define PINT7_Enable() (GPIO->PINTIE.PINTIE |= 0x80) -#define PINT0_Disable() (GPIO->PINTIE.PINTIE &= ~0x01) -#define PINT1_Disable() (GPIO->PINTIE.PINTIE &= ~0x02) -#define PINT2_Disable() (GPIO->PINTIE.PINTIE &= ~0x04) -#define PINT3_Disable() (GPIO->PINTIE.PINTIE &= ~0x08) -#define PINT4_Disable() (GPIO->PINTIE.PINTIE &= ~0x10) -#define PINT5_Disable() (GPIO->PINTIE.PINTIE &= ~0x20) -#define PINT6_Disable() (GPIO->PINTIE.PINTIE &= ~0x40) -#define PINT7_Disable() (GPIO->PINTIE.PINTIE &= ~0x80) - -/* PINTʹܿ */ -#define PINT0_MaskEnable() (GPIO->PINTIE.PMASK |= 0X01) -#define PINT1_MaskEnable() (GPIO->PINTIE.PMASK |= 0x02) -#define PINT2_MaskEnable() (GPIO->PINTIE.PMASK |= 0x04) -#define PINT3_MaskEnable() (GPIO->PINTIE.PMASK |= 0x08) -#define PINT4_MaskEnable() (GPIO->PINTIE.PMASK |= 0x10) -#define PINT5_MaskEnable() (GPIO->PINTIE.PMASK |= 0x20) -#define PINT6_MaskEnable() (GPIO->PINTIE.PMASK |= 0x40) -#define PINT7_MaskEnable() (GPIO->PINTIE.PMASK |= 0x80) -#define PINT0_MaskDisable() (GPIO->PINTIE.PMASK &= ~0x01) -#define PINT1_MaskDisable() (GPIO->PINTIE.PMASK &= ~0x02) -#define PINT2_MaskDisable() (GPIO->PINTIE.PMASK &= ~0x04) -#define PINT3_MaskDisable() (GPIO->PINTIE.PMASK &= ~0x08) -#define PINT4_MaskDisable() (GPIO->PINTIE.PMASK &= ~0x10) -#define PINT5_MaskDisable() (GPIO->PINTIE.PMASK &= ~0x20) -#define PINT6_MaskDisable() (GPIO->PINTIE.PMASK &= ~0x40) -#define PINT7_MaskDisable() (GPIO->PINTIE.PMASK &= ~0x80) - -/* PINTжϱ */ -#define PINT_ClearAllITPending() (GPIO->PIF.Word = (uint32_t)0xff) - -void GPIO_Init(GPIO_TYPE GPIOx,GPIO_TYPE_PIN PINx, GPIO_InitStruType* GPIO_InitStruct); -void GPIO_Write(GPIO_TYPE GPIOx, uint32_t Value); -uint32_t GPIO_Read(GPIO_TYPE GPIOx); -PinStatus GPIO_ReadBit(GPIO_TYPE GPIOx,GPIO_TYPE_PIN PINx); -void GPIOA_SetBit(GPIO_TYPE_PIN PINx); -void GPIOA_ResetBit(GPIO_TYPE_PIN PINx); -void GPIOA_ToggleBit(GPIO_TYPE_PIN PINx); -void GPIOB_SetBit(GPIO_TYPE_PIN PINx); -void GPIOB_ResetBit(GPIO_TYPE_PIN PINx); -void GPIOB_ToggleBit(GPIO_TYPE_PIN PINx); -void GPIOA_SetDirection(GPIO_TYPE_PIN PINx, GPIO_TYPE_DIR Dir_Type); -void GPIOB_SetDirection(GPIO_TYPE_PIN PINx, GPIO_TYPE_DIR Dir_Type); -void PINT_Config(PINT_TYPE PINTx, PINT_TYPE_SEL SELx, PINT_TYPE_TRIG TRIGx); -void GPIO_SetSingalTypeFromPin(GPIO_TYPE GPIOx,GPIO_TYPE_PIN PINx, GPIO_Pin_Signal GPIO_Signal); -void GPIO_SetDirRegFromPin(GPIO_TYPE GPIOx,GPIO_TYPE_PIN PINx, GPIO_TYPE_DIR Dir); -void GPIO_SetODERegFromPin(GPIO_TYPE GPIOx,GPIO_TYPE_PIN PINx, GPIO_ODE_Output ODE); -void GPIO_SetDSRegFromPin(GPIO_TYPE GPIOx,GPIO_TYPE_PIN PINx, GPIO_TYPE_DS DS); -void GPIO_SetPUERegFromPin(GPIO_TYPE GPIOx,GPIO_TYPE_PIN PINx, GPIO_PUE_Input PUE); -void GPIO_SetPDERegFromPin(GPIO_TYPE GPIOx,GPIO_TYPE_PIN PINx, GPIO_PDE_Input PDE); -void GPIO_SetFuncxRegFromPin(GPIO_TYPE GPIOx,GPIO_TYPE_PIN PINx, GPIO_TYPE_FUNC Func); -FlagStatus PINT_GetIFStatus(PINT_TYPE_IT PINT_Flag); -FlagStatus PINT_GetITStatus(PINT_TYPE_IT PINT_Flag); -void PINT_ClearITPendingBit(PINT_TYPE_IT PINT_Flag); - -#endif - - - - - - diff --git a/bsp/essemi/es8p508x/libraries/Library/Include/lib_iap.h b/bsp/essemi/es8p508x/libraries/Library/Include/lib_iap.h deleted file mode 100644 index 61a404d3ea..0000000000 --- a/bsp/essemi/es8p508x/libraries/Library/Include/lib_iap.h +++ /dev/null @@ -1,42 +0,0 @@ -/*************************************************************** - *Copyright (C), 2017, Shanghai Eastsoft Microelectronics Co., Ltd. - *ļ - * : Liut - * : V1.00 - * : 2017/07/14 - * - * ע ES8P508xоƬ - ѧϰʾʹãûֱôķջеκηΡ - ***************************************************************/ -#ifndef __ES8P508x_IAP_TABLE_H -#define __ES8P508x_IAP_TABLE_H - -#include "ES8P508x.h" -#include "type.h" - -#ifdef __cplusplus -extern "C" { -#endif - -#define IAP_PageProgram_addr 0x10000008 -#define IAP_PageErase_addr 0x10000000 -#define IAP_WordProgram_addr 0x10000004 - -typedef ErrorStatus (*IAP_PE)(uint32_t address); -typedef ErrorStatus (*IAP_WP)(uint32_t address, uint32_t data); -typedef ErrorStatus (*IAP_PP)(uint32_t address, uint32_t data[], uint32_t length, uint32_t erase); - -ErrorStatus IAP_PageErase(uint32_t address); -ErrorStatus IAP_WordProgram(uint32_t address, uint32_t data); -ErrorStatus IAP_PageProgram(uint32_t address, uint32_t data[], uint32_t length, uint32_t erase); -ErrorStatus IAPRead(uint32_t *Ram_Addr, uint32_t Flash_Addr, uint8_t Len); - -#define PageEraseEnable 0x00000001 -#define PageEraseDisable 0x00000000 - -#ifdef __cplusplus -} -#endif - -#endif -/*************************END OF FILE**********************/ diff --git a/bsp/essemi/es8p508x/libraries/Library/Include/lib_iic.h b/bsp/essemi/es8p508x/libraries/Library/Include/lib_iic.h deleted file mode 100644 index dae43c1964..0000000000 --- a/bsp/essemi/es8p508x/libraries/Library/Include/lib_iic.h +++ /dev/null @@ -1,229 +0,0 @@ -/*************************************************************** - *Copyright (C), 2017, Shanghai Eastsoft Microelectronics Co., Ltd. - *ļ lib_iic.h - * ߣ Liut - * V1.00 - * ڣ 2017/07/14 - * I2Cģ⺯ͷļ - * ע ES8P508xоƬ - ѧϰʾʹãûֱôķջеκηΡ - ***************************************************************/ -#ifndef __LIBIIC_H__ -#define __LIBIIC_H__ - -#include "ES8P508x.h" -#include "type.h" -#include "system_ES8P508x.h" - -/* ſ© */ -typedef enum -{ - I2C_PinMode_PP = 0x0 , //˿ģʽ: - I2C_PinMode_OD = 0x1 , //˿ģʽ:© -}I2C_TYPE_PINOD; - -/* ģʽ */ -typedef enum -{ - I2C_Mode_Master = 0x0 , //ģʽ - I2C_Mode_Slave = 0x1 , //ģʽ -}I2C_TYPE_MODE; - -/* Ӧʱ */ -typedef enum -{ - I2C_AckDelay_0P5 = 0x0 , //Ӧʱ:0.5ʱ - I2C_AckDelay_1 = 0x1 , //Ӧʱ:1ʱ - I2C_AckDelay_1P5 = 0x2 , //Ӧʱ:1.5ʱ - I2C_AckDelay_2 = 0x3 , //Ӧʱ:2ʱ - I2C_AckDelay_2P5 = 0x4 , //Ӧʱ:2.5ʱ - I2C_AckDelay_3 = 0x5 , //Ӧʱ:3ʱ - I2C_AckDelay_3P5 = 0x6 , //Ӧʱ:3.5ʱ - I2C_AckDelay_4 = 0x7 , //Ӧʱ:4ʱ -}I2C_TYPE_ADLY; - -/* ģʽ */ -typedef enum -{ - I2C_RecMode_0 = 0x0 , //ģʽ1ֽڣACK - I2C_RecMode_1 = 0x1 , //ģʽ1ֽڣNACK - I2C_RecMode_2 = 0x2 , //ģʽ2ֽڣÿֽڷACK - I2C_RecMode_3 = 0x3 , //ģʽ2ֽڣǰһֽڷACKһֽڷNACK - I2C_RecMode_4 = 0x4 , //ģʽ4ֽڣÿֽڷACK - I2C_RecMode_5 = 0x5 , //ģʽ4ֽڣǰ3ֽڷACKһֽڷNACK - I2C_RecMode_6 = 0x6, //ģʽգÿֽڷACK - I2C_RecMode_7 = 0x7, //ģʽɸֽڽգNACK -}I2C_TYPE_RECMODE; - -/* ֡ */ -typedef enum -{ - I2C_TI_Disable = 0x0 , //֡:0 - I2C_TI_1 = 0x1 , //֡:1 - I2C_TI_2 = 0x2 , //֡:2 - I2C_TI_3 = 0x3 , //֡:3 - I2C_TI_4 = 0x4 , //֡:4 - I2C_TI_5 = 0x5 , //֡:5 - I2C_TI_6 = 0x6 , //֡:6 - I2C_TI_7 = 0x7 , //֡:7 - I2C_TI_8 = 0x8 , //֡:8 - I2C_TI_9 = 0x9 , //֡:9 - I2C_TI_10 = 0xA , //֡:10 - I2C_TI_11 = 0xB , //֡:11 - I2C_TI_12 = 0xC , //֡:12 - I2C_TI_13 = 0xD , //֡:13 - I2C_TI_14 = 0xE , //֡:14 - I2C_TI_15 = 0xF , //֡:15 -}I2C_TYPE_TIS; - -/* I2Cʼýṹ嶨 */ -typedef struct -{ - I2C_TYPE_PINOD I2C_SclOd; //SCL˿ģʽ - - I2C_TYPE_PINOD I2C_SdaOd; //SDA˿ģʽ - - TYPE_FUNCEN I2C_16XSamp; //˿16ٲʹ - - uint32_t I2C_Clk; //I2CƵ - - I2C_TYPE_MODE I2C_Mode; //ģʽ - - TYPE_FUNCEN I2C_AutoStop; //Զֹͣ - - TYPE_FUNCEN I2C_AutoCall; //ԶѰ -}I2C_InitStruType; - -/* ͡жģʽ */ -typedef enum -{ - I2C_TRBIM_Byte = 0x0 , //ֽж - I2C_TRBIM_HalfWord = 0x1 , //ж - I2C_TRBIM_Word = 0x2 , //ж -}I2C_TYPE_TRBIM; - - -/* дģʽ */ -typedef enum -{ - I2C_Mode_Write = 0x0 , - I2C_Mode_Read = 0x1 , -}I2C_TYPE_RWMODE; - -/* жʹܱ־λ */ -typedef enum -{ - I2C_IT_SR = 0x0001 , //ʼλ - I2C_IT_SP = 0x0002 , //ֹͣλ - I2C_IT_TB = 0x0004 , //ͻ - I2C_IT_RB = 0x0008 , //ջ - I2C_IT_TE = 0x0010 , //ݴ - I2C_IT_RO = 0x0020 , // - I2C_IT_NA = 0x0040 , //δӦNACK - I2C_IT_TBWE = 0x0080 , //д - I2C_IT_TIDLE = 0x01000 , //Ϳж -}I2C_TYPE_IT; - -/* жϱ־λ */ -typedef enum -{ - I2C_Flag_SR = 0x0001 , //ʼλ - I2C_Flag_SP = 0x0002 , //ֹͣλ - I2C_Flag_TB = 0x0004 , //ͻ - I2C_Flag_RB = 0x0008 , //ջ - I2C_Flag_TE = 0x0010 , //ݴ - I2C_Flag_RO = 0x0020 , // - I2C_Flag_NA = 0x0040 , //δӦNACK - I2C_Flag_TBWE = 0x0080, //джϱ־λ - I2C_Flag_TIDLE= 0X1000, //I2C Ϳжϱ־λ -}I2C_TYPE_FLAG; - - -/* ־ */ -typedef enum -{ - I2C_Clr_SR = 0x0001 , //ʼλ - I2C_Clr_SP = 0x0002 , //ֹͣλ - I2C_Clr_TE = 0x0010 , //ݴ - I2C_Clr_RO = 0x0020 , // - I2C_Clr_NA = 0x0040 , //δӦNACK - I2C_Clr_TBWE = 0x0080 , //д - I2C_Clr_TIDLE= 0X01000, //I2C Ϳ -}I2C_CLR_IF; - - -/*************I2Cģ궨************/ - -/* I2Cģʹܿ */ -#define I2C_Enable() (I2C0->CON.EN = 1) -#define I2C_Disable() (I2C0->CON.EN = 0) - -/* I2Cģ鸴λ */ -#define I2C_Reset() (I2C0->CON.RST = 1) - -/* I2Cʱʹܿ */ -#define I2C_TJEnable() (I2C0->CON.TJE = 1) -#define I2C_TJDisable() (I2C0->CON.TJE = 0) - -/* I2Cģʽд */ -#define I2C_Read() (I2C0->CON.RW = 1) -#define I2C_Write() (I2C0->CON.RW = 0) - -/* I2CʱԶȴʹܿƣӻģʽ֧֣ */ -#define I2C_CSEnable() (I2C0->MOD.CSE = 1) -#define I2C_CSDisable() (I2C0->MOD.CSE = 0) - -/* I2CԶδӦʹܿƣӻģʽ֧֣ */ -#define I2C_ANAEnable() (I2C0->MOD.ANAE = 1) -#define I2C_ANADisable() (I2C0->MOD.ANAE = 0) - -/* I2CԶѰʹܿƣģʽ֧֣ */ -#define I2C_SRAEnable() (I2C0->MOD.SRAE = 1) -#define I2C_SRADisable() (I2C0->MOD.SRAE = 0) - -/* I2CԶʹܿƣģʽ֧֣ */ -#define I2C_SPAEnable() (I2C0->MOD.SPAE = 1) -#define I2C_SPADisable() (I2C0->MOD.SPAE = 0) - -/* I2Cʼλģʽ֧֣ */ -#define I2C_SRTrigger() (I2C0->MOD.SRT=1) - -/* I2Cֹͣλģʽ֧֣ */ -#define I2C_SPTrigger() (I2C0->MOD.SPT = 1) - -/* I2Cݴģʽ֧֣ */ -#define I2C_RDTrigger() (I2C0->MOD.RDT = 1) - - -/* I2Cͷ */ -#define I2C_Release() (I2C0->MOD.BLD = 1) - -/* I2CӦãӻģʽ֧֣ */ -#define I2C_TACK() (I2C0->MOD.TAS = 1) -#define I2C_TNACK() (I2C0->MOD.TAS = 0) - -/************I2Cģ麯***********/ -void I2C_Init(I2C_InitStruType* I2C_InitStruct); -void I2C_ITConfig(I2C_TYPE_IT I2C_IT,TYPE_FUNCEN NewState); -void I2C_SendAddress(uint8_t I2C_Address,I2C_TYPE_RWMODE Mode); -void I2C_SetAddress(uint8_t I2C_Address); -void I2C_RecModeConfig(I2C_TYPE_RECMODE RecType); -void I2C_TBIMConfig(I2C_TYPE_TRBIM Type); -void I2C_RBIMConfig(I2C_TYPE_TRBIM Type); -void I2C_AckDelay(I2C_TYPE_ADLY Type,TYPE_FUNCEN NewStatus); -void I2C_TISConfig(I2C_TYPE_TIS Time); -void I2C_SendByte(uint8_t Byte); -void I2C_SendHalfWord(uint16_t HalfWord); -void I2C_SendWord(uint32_t Word); -uint8_t I2C_RecByte(void); -uint16_t I2C_RecHalfWord(void); -uint32_t I2C_RecWord(void); -I2C_TYPE_RWMODE I2C_GetRWMode(void); -FlagStatus I2C_GetTBStatus(void); -FlagStatus I2C_GetFlagStatus(I2C_TYPE_FLAG I2C_Flag); -FlagStatus I2C_GetITStatus( I2C_TYPE_IT I2C_Flag); -void I2C_ClearITPendingBit(I2C_CLR_IF I2C_IT); - -#endif - -/*************************END OF FILE**********************/ diff --git a/bsp/essemi/es8p508x/libraries/Library/Include/lib_printf.h b/bsp/essemi/es8p508x/libraries/Library/Include/lib_printf.h deleted file mode 100644 index 7bee613c8a..0000000000 --- a/bsp/essemi/es8p508x/libraries/Library/Include/lib_printf.h +++ /dev/null @@ -1,33 +0,0 @@ -/*************************************************************** - *Copyright (C), 2017, Shanghai Eastsoft Microelectronics Co., Ltd. - *ļ lib_printf.h - * ߣ Liut - * V1.00 - * ڣ 2017/07/14 - * ڴӡ⺯ͷļ - * ע ES8P508xоƬ - ѧϰʾʹãûֱôķջеκηΡ - ***************************************************************/ -#ifndef __LIBPRINTF_H__ -#define __LIBPRINTF_H__ - -#include "lib_uart.h" -#include -#include "type.h" - -int fputc(int ch, FILE *f); -static char *itoa(int value, char *string, int radix); -ErrorStatus UART_printf(uint8_t *Data,...); - -#ifdef __clang__ -ErrorStatus UART_printf(uint8_t *Data, ...); - -#elif defined __CC_ARM - -#define UART_printf printf - -#endif - -#endif - -/*************************END OF FILE**********************/ diff --git a/bsp/essemi/es8p508x/libraries/Library/Include/lib_rtc.h b/bsp/essemi/es8p508x/libraries/Library/Include/lib_rtc.h deleted file mode 100644 index 86dbb5bcc4..0000000000 --- a/bsp/essemi/es8p508x/libraries/Library/Include/lib_rtc.h +++ /dev/null @@ -1,84 +0,0 @@ -/********************************************************* - *Copyright (C), 2017, Shanghai Eastsoft Microelectronics Co., Ltd. - *ļ: lib_rtc.h - * : WangMX - * : V1.00 - * : 2017/07/14 - * : RTCģͷļ - * ע: HRSDK-GDB-ES8P508x V1.1 - ѧϰʾʹãûֱôķջеκηΡ - **********************************************************/ -#ifndef __LIBRTC_H__ -#define __LIBRTC_H__ - -#include "ES8P508x.h" -#include "type.h" - -/*RTCʱԴѡ*/ -typedef enum -{ - RTC_LOSC = 0x0, //ⲿ32768HZʱ RTCȷʱ - RTC_LRC = 0x1, //ڲLRCʱ RTCǾȷʱ - RTC_PLCK_256 = 0x2, //PLCLK/256 RTCͨ - RTC_PLCK = 0x3, //PCLK RTCͨ -}RTC_TYPE_CLKS; - -/*RTCʱ12/24Сʱѡ*/ -typedef enum -{ - RTC_HOUR12 = 0x0, //12Сʱ - RTC_HOUR24 = 0x1, //24Сʱ -}RTC_TYPE_TIME; - -/* RTCжԴѡ */ -typedef enum { - RTC_Interrupt_Source_Second = 0x001, // ж - RTC_Interrupt_Source_Minute = 0x002, // ж - RTC_Interrupt_Source_Hour = 0x004, // Сʱж - RTC_Interrupt_Source_Day = 0x008, // ж - RTC_Interrupt_Source_Month = 0x010, // ж - RTC_Interrupt_Source_DayALE = 0x100, // ж - RTC_Interrupt_Source_WeekALE = 0x200, // ж -} RTC_Interrupt_Source; - - -/********************* RTCģ麯 *********************/ -void RTC_Init(RTC_TYPE_CLKS CLKx,RTC_TYPE_TIME HOURx); -uint32_t RTC_ReadHourmode(void); -uint32_t RTC_ReadSecond(void); -uint32_t RTC_ReadMinute(void); -uint32_t RTC_ReadHour(uint32_t *meridiem); -uint32_t RTC_ReadDay(void); -uint32_t RTC_ReadMonth(void); -uint32_t RTC_ReadYear(void); -uint32_t RTC_ReadWeek(void); - -ErrorStatus RTC_WriteSecond(uint32_t second); -ErrorStatus RTC_WriteMinute(uint32_t minute); -ErrorStatus RTC_WriteHour(uint32_t hour, uint32_t meridiem); -ErrorStatus RTC_WriteDay(uint32_t day); -ErrorStatus RTC_WriteMonth(uint32_t month); -ErrorStatus RTC_WriteYear(uint32_t year); -ErrorStatus RTC_WriteWeek(uint32_t week); - -uint32_t RTC_ReadWeekAlarmMinute(void); -uint32_t RTC_ReadWeekAlarmHour(uint32_t *meridiem); -uint32_t RTC_ReadWeekAlarmWeek(void); -uint32_t RTC_ReadDayAlarmMinute(void); -uint32_t RTC_ReadDayAlarmHour(uint32_t *meridiem); - -ErrorStatus RTC_WriteWeekAlarmMinute(uint32_t minute); -ErrorStatus RTC_WriteWeekAlarmHour(uint32_t hour, uint32_t meridiem); -ErrorStatus RTC_WriteWeekAlarmWeek(uint32_t week); -ErrorStatus RTC_WriteDayAlarmMinute(uint32_t minute); -ErrorStatus RTC_WriteDayAlarmHour(uint32_t hour, uint32_t meridiem); - -void RTC_InterruptEnable(RTC_Interrupt_Source src); -void RTC_InterruptDisable(RTC_Interrupt_Source src); -ITStatus RTC_GetITStatus(RTC_Interrupt_Source src); -FlagStatus RTC_GetFlagStatus(RTC_Interrupt_Source src); -void RTC_ClearITPendingBit(RTC_Interrupt_Source src); - -#endif - -/*************************END OF FILE**********************/ diff --git a/bsp/essemi/es8p508x/libraries/Library/Include/lib_scs.h b/bsp/essemi/es8p508x/libraries/Library/Include/lib_scs.h deleted file mode 100644 index e69c9a674f..0000000000 --- a/bsp/essemi/es8p508x/libraries/Library/Include/lib_scs.h +++ /dev/null @@ -1,98 +0,0 @@ -/*************************************************************** - *Copyright (C), 2017, Shanghai Eastsoft Microelectronics Co., Ltd. - *ļ lib_scs.h - * ߣ Liut - * V1.00 - * ڣ 2017/07/14 - * ںģ⺯ͷļ - * ע ES8P508xоƬ - ѧϰʾʹãûֱôķջеκηΡ - ***************************************************************/ -#ifndef __LIBNVIC_H__ -#define __LIBNVIC_H__ - -#include "ES8P508x.h" -#include "type.h" - -/* жԴѡ */ -typedef enum -{ - NVIC_PINT0_IRQn = 0, - NVIC_PINT1_IRQn = 1, - NVIC_PINT2_IRQn = 2, - NVIC_PINT3_IRQn = 3, - NVIC_PINT4_IRQn = 4, - NVIC_PINT5_IRQn = 5, - NVIC_PINT6_IRQn = 6, - NVIC_PINT7_IRQn = 7, - NVIC_T16N0_IRQn = 8, - NVIC_T16N1_IRQn = 9, - NVIC_T16N2_IRQn = 10, - NVIC_T16N3_IRQn = 11, - NVIC_T32N0_IRQn = 12, - NVIC_IWDT_IRQn = 14, - NVIC_WWDT_IRQn = 15, - NVIC_CCM_IRQn = 16, - NVIC_PLK_IRQn = 17, - NVIC_LVD_IRQn = 18, - NVIC_KINT_IRQn = 19, - NVIC_RTC_IRQn = 20, - NVIC_ADC_IRQn = 21, - NVIC_AES_IRQn = 23, - NVIC_UART0_IRQn = 24, - NVIC_UART1_IRQn = 25, - NVIC_UART2_IRQn = 26, - NVIC_UART3_IRQn = 27, - NVIC_UART4_IRQn = 28, - NVIC_UART5_IRQn = 29, - NVIC_SPI0_IRQn = 30, - NVIC_I2C0_IRQn = 31, -}NVIC_IRQChannel; - -/* ȼ */ -typedef enum -{ - NVIC_Priority_0 = 0x0 , - NVIC_Priority_1 = 0x1 , - NVIC_Priority_2 = 0x2 , - NVIC_Priority_3 = 0x3 , -}NVIC_IRQPriority; - -/* ģʽ */ -typedef enum -{ - SCB_LP_SleepOnExit = 0x02 , //ISRжϴ򷵻ص߳ģʽʱǷ - SCB_LP_SleepDeep = 0x04 , //˯ - SCB_LP_SEVOPend = 0x10 , //жϹʱǷΪѵѡλ -}SCB_TYPE_SCR; - -/* SysTickʱԴѡ */ -typedef enum -{ - SysTick_ClkS_Base = 0x0 , //׼ʱ(Hclk/3) - SysTick_ClkS_Cpu = 0x1 , //ʱ(Hclk) -}SYST_TYPE_CLKS; - -/* SysTickʼýṹ嶨 */ -typedef struct -{ - uint32_t SysTick_Value; //ݼֵ24λҶ - SYST_TYPE_CLKS SysTick_ClkSource; //ʱԴѡ - TYPE_FUNCEN SysTick_ITEnable; //жʹܡʧ -}SYSTICK_InitStruType; - -/**************ģ궨*************/ - -/*SysTickʹ*/ -#define SysTick_Enable() (SysTick->CTRL |= 0x00000001) -#define SysTick_Disable() (SysTick->CTRL &= 0xFFFFFFFE) - -/************SCSģ麯***********/ -void NVIC_Init(NVIC_IRQChannel Channel,NVIC_IRQPriority Priority,TYPE_FUNCEN Cmd); -void SCB_SystemLPConfig(SCB_TYPE_SCR LowPowerMode, TYPE_FUNCEN NewState); -uint32_t SCB_GetCpuID(void); -void SysTick_Init(SYSTICK_InitStruType* SysT_InitStruct); - -#endif - -/*************************END OF FILE**********************/ diff --git a/bsp/essemi/es8p508x/libraries/Library/Include/lib_scu.h b/bsp/essemi/es8p508x/libraries/Library/Include/lib_scu.h deleted file mode 100644 index a07440153b..0000000000 --- a/bsp/essemi/es8p508x/libraries/Library/Include/lib_scu.h +++ /dev/null @@ -1,314 +0,0 @@ -/*************************************************************** - *Copyright (C), 2017, Shanghai Eastsoft Microelectronics Co., Ltd. - *ļ lib_scu.h - * ߣ Liut - * V1.00 - * ڣ 2017/07/14 - * ںģ⺯ͷļ - * ע ES8P508xоƬ - ѧϰʾʹãûֱôķջеκηΡ - ***************************************************************/ -#ifndef __LIBSCU_H -#define __LIBSCU_H - -#include "system_ES8P508x.h" -#include "ES8P508x.h" -#include "type.h" - -/* NMIжѡ */ -typedef enum -{ - SCU_PINT0_IRQn = 0, - SCU_PINT1_IRQn = 1, - SCU_PINT2_IRQn = 2, - SCU_PINT3_IRQn = 3, - SCU_PINT4_IRQn = 4, - SCU_PINT5_IRQn = 5, - SCU_PINT6_IRQn = 6, - SCU_PINT7_IRQn = 7, - SCU_T16N0_IRQn = 8, - SCU_T16N1_IRQn = 9, - SCU_T16N2_IRQn = 10, - SCU_T16N3_IRQn = 11, - SCU_T32N0_IRQn = 12, - SCU_IWDT_IRQn = 14, - SCU_WWDT_IRQn = 15, - SCU_CCM_IRQn = 16, - SCU_PLK_IRQn = 17, - SCU_LVD_IRQn = 18, - SCU_KINT_IRQn = 19, - SCU_RTC_IRQn = 20, - SCU_ADC_IRQn = 21, - SCU_AES_IRQn = 23, - SCU_UART0_IRQn = 24, - SCU_UART1_IRQn = 25, - SCU_UART2_IRQn = 26, - SCU_UART3_IRQn = 27, - SCU_UART4_IRQn = 28, - SCU_UART5_IRQn = 29, - SCU_SPI0_IRQn = 30, - SCU_I2C0_IRQn = 31, -}SCU_TYPE_NMICS; - -/* PWRCλ״̬Ĵ־λ */ -typedef enum -{ - SCU_PWRC_PORF= 0X00001, //PORλ־λ - SCU_PWRC_RRCF = 0X00002, //PORCλ־λ - SCU_PWRC_PORRSTF = 0x00004, //PORܸλ־ - SCU_PWRC_BORF = 0x00008, //BORܸλ־ - SCU_PWRC_WWDTRSTF = 0x00010, //WWDTλ־ - SCU_PWRC_IWDTRSTF = 0x00020, //IWDTλ־ - SCU_PWRC_MRSTF = 0x00040, //MRSTnλ־ - SCU_PWRC_SOFTRSTF = 0x00080, //λ־ -}SCU_TYPE_PWRC; - -/* LVDĴ־λ */ -typedef enum -{ - SCU_LVDFlag_IF = 0x0100, //LVDжϱ־ - SCU_LVDFlag_Out = 0x8000, //״̬λ -}SCU_TYPE_LVD0CON; - -/* ʱѡ */ -typedef enum -{ - SCU_SysClk_HRC = 0x0 , //ڲ20MHZ RCʱ - SCU_SysClk_XTAL = 0x1 , //ⲿʱ - SCU_SysClk_PLL = 0x2 , //PLL -}SCU_TYPE_SYSCLK; - -/*clk_selʱԴѡ*/ -typedef enum -{ - CLK_SEL_HRC = 0x0, //HRC 20M - CLK_SEL_LRC = 0x1, //LRC 32KHz - CLK_SEL_XTAL = 0x2, //ӾXTAL -}SCU_TYPE_CLK_SEL; - -/* PLLʱԴѡ */ -typedef enum -{ - SCU_PLL_HRC = 0x0 , //PLLʱԴHRC - SCU_PLL_LRC = 0x2 , //PLLʱԴLRC - SCU_PLL_XTAL_32K = 0x3 , //PLLʱԴXTAL - SCU_PLL_XTAL_4M = 0x4 , //PLLʱԴXTAL - SCU_PLL_XTAL_8M = 0x5, //PLLʱԴXTAL - SCU_PLL_XTAL_16M = 0x6, //PLLʱԴXTAL - SCU_PLL_XTAL_20M = 0x7, //PLLʱԴXTAL -} SCU_PLL_Origin; - -/* PLLʱƵ */ -typedef enum -{ - SCU_PLL_32M = 0x0 , //PLLʱΪ32MHz - SCU_PLL_48M = 0x1 , //PLLʱΪ48Mhz -} SCU_PLL_Out; - -/************SCUģ궨***********/ -/* SCUд */ -#define SCU_RegUnLock() (SCU->PROT.Word = 0x55AA6996) -#define SCU_RegLock() (SCU->PROT.Word = 0x00000000) - -/* NMIʹܿ */ -#define SCU_NMI_Enable() (SCU->NMICON.NMIEN = 0x1) -#define SCU_NMI_Disable() (SCU->NMICON.NMIEN = 0x0) - -/*-------LVDģ-------*/ - -/* LVDʹܿ */ -#define SCU_LVD_Enable() (SCU->LVDCON.EN = 0x1) -#define SCU_LVD_Disable() (SCU->LVDCON.EN = 0x0) - -/* LVD˲ʹܿ */ -#define SCU_LVDFLT_Enable() (SCU->LVDCON.FLTEN = 0x1) -#define SCU_LVDFLT_Disable() (SCU->LVDCON.FLTEN = 0x0) - -/* LVDѹѡ */ -#define SCU_LVDVS_2V0() (SCU->LVDCON.VS = 0x0) -#define SCU_LVDVS_2V1() (SCU->LVDCON.VS = 0x1) -#define SCU_LVDVS_2V2() (SCU->LVDCON.VS = 0x2) -#define SCU_LVDVS_2V4() (SCU->LVDCON.VS = 0x3) -#define SCU_LVDVS_2V6() (SCU->LVDCON.VS = 0x4) -#define SCU_LVDVS_2V8() (SCU->LVDCON.VS = 0x5) -#define SCU_LVDVS_3V0() (SCU->LVDCON.VS = 0x6) -#define SCU_LVDVS_3V6() (SCU->LVDCON.VS = 0x7) -#define SCU_LVDVS_4V() (SCU->LVDCON.VS = 0x8) -#define SCU_LVDVS_4V6() (SCU->LVDCON.VS = 0x9) -#define SCU_LVDVS_2V3() (SCU->LVDCON.VS = 0xA) -#define SCU_LVDVS_LVDIN() (SCU->LVDCON.VS = 0xE) - -/* LVDжʹܿ */ -#define SCU_LVDIT_Enable() (SCU->LVDCON.IE = 0x1) -#define SCU_LVDIT_Disable() (SCU->LVDCON.IE = 0x0) - -/* LVDжϱ־λ */ -#define SCU_LVDClearIFBit() (SCU->LVDCON.IF = 1) - -/* LVDжϲģʽѡ */ -#define SCU_LVDIFS_Rise() (SCU->LVDCON.IFS = 0x0) //LVDOزж -#define SCU_LVDIFS_Fall() (SCU->LVDCON.IFS = 0x1) //LVDO½زж -#define SCU_LVDIFS_High() (SCU->LVDCON.IFS = 0x2) //LVDOߵƽж -#define SCU_LVDIFS_Low() (SCU->LVDCON.IFS = 0x3) //LVDO͵ƽж -#define SCU_LVDIFS_Change() (SCU->LVDCON.IFS = 0x4) //LVDOƽ仯ж - -/* FLASHʵȴʱѡ */ -#define SCU_FlashWait_1Tclk() (SCU->FLASHWAIT.ACCT = 0x0) -#define SCU_FlashWait_2Tclk() (SCU->FLASHWAIT.ACCT = 0x1) -#define SCU_FlashWait_3Tclk() (SCU->FLASHWAIT.ACCT = 0x2) -#define SCU_FlashWait_4Tclk() (SCU->FLASHWAIT.ACCT = 0x3) -#define SCU_FlashWait_5Tclk() (SCU->FLASHWAIT.ACCT = 0x4) -#define SCU_FlashWait_6Tclk() (SCU->FLASHWAIT.ACCT = 0x5) -#define SCU_FlashWait_7Tclk() (SCU->FLASHWAIT.ACCT = 0x6) -#define SCU_FlashWait_8Tclk() (SCU->FLASHWAIT.ACCT = 0x7) -#define SCU_FlashWait_9Tclk() (SCU->FLASHWAIT.ACCT = 0x8) -#define SCU_FlashWait_10Tclk() (SCU->FLASHWAIT.ACCT = 0x9) -#define SCU_FlashWait_11Tclk() (SCU->FLASHWAIT.ACCT = 0xA) -#define SCU_FlashWait_12Tclk() (SCU->FLASHWAIT.ACCT = 0xB) -#define SCU_FlashWait_13Tclk() (SCU->FLASHWAIT.ACCT = 0xC) -#define SCU_FlashWait_14Tclk() (SCU->FLASHWAIT.ACCT = 0xD) -#define SCU_FlashWait_15Tclk() (SCU->FLASHWAIT.ACCT = 0xE) -#define SCU_FlashWait_16Tclk() (SCU->FLASHWAIT.ACCT = 0xF) - -/* ϵͳʱӺƵѡ */ -#define SCU_SysClk_Div1() (SCU->SCLKEN0.SYSCLK_DIV = 0) -#define SCU_SysClk_Div2() (SCU->SCLKEN0.SYSCLK_DIV = 1) -#define SCU_SysClk_Div4() (SCU->SCLKEN0.SYSCLK_DIV = 2) -#define SCU_SysClk_Div8() (SCU->SCLKEN0.SYSCLK_DIV = 3) -#define SCU_SysClk_Div16() (SCU->SCLKEN0.SYSCLK_DIV = 4) -#define SCU_SysClk_Div32() (SCU->SCLKEN0.SYSCLK_DIV = 5) -#define SCU_SysClk_Div64() (SCU->SCLKEN0.SYSCLK_DIV = 6) -#define SCU_SysClk_Div128() (SCU->SCLKEN0.SYSCLK_DIV = 7) - -/* HRCʹܿ (ڲ20Mhz) */ -#define SCU_HRC_Enable() (SCU->SCLKEN1.HRC_EN = 1) -#define SCU_HRC_Disable() (SCU->SCLKEN1.HRC_EN = 0) - -/* XTALʹܿ */ -#define SCU_XTAL_Enable() (SCU->SCLKEN1.XTAL_EN = 1) -#define SCU_XTAL_Disable() (SCU->SCLKEN1.XTAL_EN = 0) - -/* PLLģʽʹܿ */ -#define SCU_PLL_Enable() (SCU->SCLKEN1.PLL_EN = 1) -#define SCU_PLL_Disable() (SCU->SCLKEN1.PLL_EN = 0) - -/*-------ʱӿ-------*/ -/* SCUʱʹܿ */ -#define SCU_SCUCLK_Enable() (SCU->PCLKEN0.SCU_EN = 1) -#define SCU_SCUCLK_Disable() (SCU->PCLKEN0.SCU_EN = 0) - -/* GPIOʱʹܿ */ -#define SCU_GPIOCLK_Enable() (SCU->PCLKEN0.GPIO_EN = 1) -#define SCU_GPIOCLK_Disable() (SCU->PCLKEN0.GPIO_EN = 0) - -/* FLASH IAPʱʹܿ */ -#define SCU_IAPCLK_Enable() (SCU->PCLKEN0.IAP_EN = 1) -#define SCU_IAPCLK_Disable() (SCU->PCLKEN0.IAP_EN = 0) - -/* CRCʱʹܿ */ -#define SCU_CRCCLK_Enable() (SCU->PCLKEN0.CRC_EN = 1) -#define SCU_CRCCLK_Disable() (SCU->PCLKEN0.CRC_EN = 0) - -/* ADCʱʹܿ */ -#define SCU_ADCCLK_Enable() (SCU->PCLKEN0.ADC_EN = 1) -#define SCU_ADCCLK_Disable() (SCU->PCLKEN0.ADC_EN = 0) - -/* RTCʱʹܿ */ -#define SCU_RTCCLK_Enable() (SCU->PCLKEN0.RTC_EN = 1) -#define SCU_RTCCLK_Disable() (SCU->PCLKEN0.RTC_EN = 0) - -/* IWDTʱʹܿ */ -#define SCU_IWDTCLK_Enable() (SCU->PCLKEN0.IWDT_EN = 1) -#define SCU_IWDTCLK_Disable() (SCU->PCLKEN0.IWDT_EN = 0) - -/* WWDTʱʹܿ */ -#define SCU_WWDTCLK_Enable() (SCU->PCLKEN0.WWDT_EN = 1) -#define SCU_WWDTCLK_Disable() (SCU->PCLKEN0.WWDT_EN = 0) - -/* AESʱʹܿ */ -#define SCU_AESCLK_Enable() (SCU->PCLKEN0.AES_EN = 1) -#define SCU_AESCLK_Disable() (SCU->PCLKEN0.AES_EN = 0) - -/* T16N0ʱʹܿ */ -#define SCU_T16N0CLK_Enable() (SCU->PCLKEN1.T16N0_EN = 1) -#define SCU_T16N0CLK_Disable() (SCU->PCLKEN1.T16N0_EN = 0) - -/* T16N1ʱʹܿ */ -#define SCU_T16N1CLK_Enable() (SCU->PCLKEN1.T16N1_EN = 1) -#define SCU_T16N1CLK_Disable() (SCU->PCLKEN1.T16N1_EN = 0) - -/* T16N2ʱʹܿ */ -#define SCU_T16N2CLK_Enable() (SCU->PCLKEN1.T16N2_EN = 1) -#define SCU_T16N2CLK_Disable() (SCU->PCLKEN1.T16N2_EN = 0) - -/* T16N3ʱʹܿ */ -#define SCU_T16N3CLK_Enable() (SCU->PCLKEN1.T16N3_EN = 1) -#define SCU_T16N3CLK_Disable() (SCU->PCLKEN1.T16N3_EN = 0) - -/* T32N0ʱʹܿ */ -#define SCU_T32N0CLK_Enable() (SCU->PCLKEN1.T32N0_EN = 1) -#define SCU_T32N0CLK_Disable() (SCU->PCLKEN1.T32N0_EN = 0) - -/* UART0ʱʹܿ */ -#define SCU_UART0CLK_Enable() (SCU->PCLKEN1.UART0_EN = 1) -#define SCU_UART0CLK_Disable() (SCU->PCLKEN1.UART0_EN = 0) - -/* UART1ʱʹܿ */ -#define SCU_UART1CLK_Enable() (SCU->PCLKEN1.UART1_EN = 1) -#define SCU_UART1CLK_Disable() (SCU->PCLKEN1.UART1_EN = 0) - -/* UART2ʱʹܿ */ -#define SCU_UART2CLK_Enable() (SCU->PCLKEN1.UART2_EN = 1) -#define SCU_UART2CLK_Disable() (SCU->PCLKEN1.UART2_EN = 0) - -/* UART3ʱʹܿ */ -#define SCU_UART3CLK_Enable() (SCU->PCLKEN1.UART3_EN = 1) -#define SCU_UART3CLK_Disable() (SCU->PCLKEN1.UART3_EN = 0) - -/* UART4ʱʹܿ */ -#define SCU_UART4CLK_Enable() (SCU->PCLKEN1.UART4_EN = 1) -#define SCU_UART4CLK_Disable() (SCU->PCLKEN1.UART4_EN = 0) - -/* UART5ʱʹܿ */ -#define SCU_UART5CLK_Enable() (SCU->PCLKEN1.UART5_EN = 1) -#define SCU_UART5CLK_Disable() (SCU->PCLKEN1.UART5_EN = 0) - -/* SPI0ʱʹܿ */ -#define SCU_SPI0CLK_Enable() (SCU->PCLKEN1.SPI0_EN = 1) -#define SCU_SPI0CLK_Disable() (SCU->PCLKEN1.SPI0_EN = 0) - -/* IIC0ʱʹܿ */ -#define SCU_IIC0CLK_Enable() (SCU->PCLKEN1.I2C0_EN = 1) -#define SCU_IIC0CLK_Disable() (SCU->PCLKEN1.I2C0_EN = 0) - -/* жӳʹܿ */ -#define SCU_TBLRemap_Enable() (SCU->TBLREMAPEN.EN= 1) -#define SCU_TBLRemap_Disable() (SCU->TBLREMAPEN.EN= 0) - -/* жƫƼĴ xΪ2^24=16777216 */ -#define SCU_TBL_Offset(x) (SCU->TBLOFF.TBLOFF = (uint32_t)x) - -/************SCUģ麯***********/ -void SCU_OpenXTAL(void); -void SCU_NMISelect(SCU_TYPE_NMICS NMI_Type); -FlagStatus SCU_GetPWRCFlagStatus(SCU_TYPE_PWRC PWRC_Flag); -void SCU_ClearPWRCFlagBit(SCU_TYPE_PWRC PWRC_Flag); -FlagStatus SCU_GetLVDFlagStatus(SCU_TYPE_LVD0CON LVD_Flag); -void SCU_SysClkSelect(SCU_TYPE_SYSCLK Sysclk); -SCU_TYPE_SYSCLK SCU_GetSysClk(void); -FlagStatus SCU_HRCReadyFlag(void); -FlagStatus SCU_XTALReadyFlag(void); -FlagStatus SCU_PLLReadyFlag(void); -void SystemClockConfig(void); -void SystemClockConfig_1(void); -void DeviceClockAllEnable(void); -void DeviceClockAllDisable(void); -void SystemClockSelect(SCU_TYPE_SYSCLK SYSCLKx , SCU_TYPE_CLK_SEL CLK_SEL); -void PLLClock_Config(TYPE_FUNCEN pll_en , SCU_PLL_Origin pll_origin ,SCU_PLL_Out pll_out,TYPE_FUNCEN sys_pll); -#endif -/*************************END OF FILE**********************/ - - - - - diff --git a/bsp/essemi/es8p508x/libraries/Library/Include/lib_spi.h b/bsp/essemi/es8p508x/libraries/Library/Include/lib_spi.h deleted file mode 100644 index 8089ae8b66..0000000000 --- a/bsp/essemi/es8p508x/libraries/Library/Include/lib_spi.h +++ /dev/null @@ -1,141 +0,0 @@ -/*************************************************************** - *Copyright (C), 2017, Shanghai Eastsoft Microelectronics Co., Ltd. - *ļ lib_spi.h - * ߣ Liut - * V1.00 - * ڣ 2017/07/14 - * SPIģ⺯ͷļ - * ע ES8P508xоƬ - ѧϰʾʹãûֱôķջеκηΡ - ***************************************************************/ -#ifndef __LIBSPI_H__ -#define __LIBSPI_H__ - -#include "system_ES8P508x.h" -#include "ES8P508x.h" -#include "type.h" - -/* ͨݸʽ */ -typedef enum -{ - SPI_RiseSendFallRec = 0x0 , //ͨݸʽطͣȣ½ؽգ - SPI_FallSendRiseRec = 0x1 , //ͨݸʽ½طͣȣؽգ - SPI_RiseRecFallSend = 0x2 , //ͨݸʽؽգȣ½طͣ - SPI_FallRecRiseSend = 0x3 , //ͨݸʽ½ؽգȣطͣ -}SPI_TYPE_DFS; - -/* ͨѶģʽ */ -typedef enum -{ - SPI_Mode_Master = 0x0 , //ͨѶģʽ - SPI_Mode_Slave = 0x1 , //ͨѶģʽӶ -}SPI_TYPE_MODE; - -/* ADCʼýṹ嶨 */ -typedef struct -{ - uint32_t SPI_Freq; //SPIƵ - - SPI_TYPE_DFS SPI_Df; //ͨѶݸʽ - - SPI_TYPE_MODE SPI_Mode; //ͨѶģʽ - - uint8_t SPI_DW; //֡λ - - TYPE_FUNCEN SPI_DelayRec; //ʱʹ - - TYPE_FUNCEN SPI_DelaySend; //ͼʹ - - uint8_t SPI_SendDelayPeroid;//ͼ - -}SPI_InitStruType; - -/* ־λ */ -typedef enum -{ - SPI_Flag_TB = 0x00000001, - SPI_Flag_RB = 0x00000002, - SPI_Flag_TE = 0x00000004, - SPI_Flag_RO = 0x00000008, - SPI_Flag_ID = 0x00000010, - SPI_Flag_NSSIF = 0x00000020, - SPI_Flag_TBWE = 0x00000040, - SPI_Flag_NSS = 0x00000080, - SPI_Flag_TBEF0 = 0x00000100, - SPI_Flag_TBEF1 = 0x00000200, - SPI_Flag_TBEF2 = 0x00000400, - SPI_Flag_TBEF3 = 0x00000800, - SPI_Flag_RBFF0 = 0x00001000, - SPI_Flag_RBFF1 = 0x00002000, - SPI_Flag_RBFF2 = 0x00004000, - SPI_Flag_RBFF3 = 0x00008000, - SPI_Flag_IDLE = 0x00010000, - SPI_Flag_TMS = 0x00020000, -}SPI_TYPE_FLAG; - -/* жģʽѡ */ -typedef enum -{ - SPI_IType_BYTE = 0x0 , - SPI_IType_HALFWORD = 0x1 , - SPI_IType_WORD = 0x2 , -}SPI_TYPE_TRBIM; - -/* SPIж */ -typedef enum -{ - SPI_IT_TB = 0x01 , - SPI_IT_RB = 0x02 , - SPI_IT_TE = 0x04 , - SPI_IT_RO = 0x08 , - SPI_IT_ID = 0x10 , - SPI_IT_NSS = 0x20 , - SPI_IT_TBWE = 0x40 , -}SPI_TYPE_IT; - -/* SPIжϱ־ */ -typedef enum -{ - SPI_Clr_TE = 0x04 , - SPI_Clr_RO = 0x08 , - SPI_Clr_ID = 0x10 , - SPI_Clr_NSS = 0x20 , - SPI_Clr_TBWE = 0x40 , -}SPI_CLR_IF; - -/************SPIģ궨***********/ - -/* SPIʹܿ */ -#define SPI_Enable() (SPI0->CON.EN = 1) -#define SPI_Disable() (SPI0->CON.EN = 0) - -/* SPIʹܿ */ -#define SPI_RecEnable() (SPI0->CON.REN = 1) -#define SPI_RecDisable() (SPI0->CON.REN = 0) - -/* SPIλ */ -#define SPI_Rst() (SPI0->CON.RST = 1) - -/* SPI */ -#define SPI_RX_CLR() (SPI0->CON.RXCLR = 1) -#define SPI_TX_CLR() (SPI0->CON.TXCLR = 1) - -/************SPIģ麯***********/ -void SPI_Init(SPI_InitStruType* SPI_InitStruct); -void SPI_ITConfig(SPI_TYPE_IT SPI_IE,TYPE_FUNCEN NewState); -void SPI_DataFormatConfig(SPI_TYPE_DFS Type); -void SPI_SendByte(uint8_t Temp); -void SPI_SendHalfWord(uint16_t Temp); -void SPI_SendWord(uint32_t Temp); -uint8_t SPI_RecByte(void); -uint16_t SPI_RecHalfWord(void); -uint32_t SPI_RecWord(void); -void SPI_TBIMConfig(SPI_TYPE_TRBIM Type); -void SPI_RBIMConfig(SPI_TYPE_TRBIM Type); -FlagStatus SPI_GetFlagStatus(SPI_TYPE_FLAG Flag); -ITStatus SPI_GetITStatus(SPI_TYPE_IT Flag); -void SPI_ClearITPendingBit(SPI_CLR_IF Flag); - -#endif - -/*************************END OF FILE**********************/ diff --git a/bsp/essemi/es8p508x/libraries/Library/Include/lib_timer.h b/bsp/essemi/es8p508x/libraries/Library/Include/lib_timer.h deleted file mode 100644 index d5493c8e3a..0000000000 --- a/bsp/essemi/es8p508x/libraries/Library/Include/lib_timer.h +++ /dev/null @@ -1,310 +0,0 @@ -/****************************************************************************************** - * Copyright (C), 2017, Shanghai Eastsoft Microelectronics Co., Ltd. - * ļ: lib_timer.h - * : Liut - * : V1.00 - * : 2017/07/14 - * : 16λʱ/32λʱ/⺯ͷļ - * ע: ES8P508xϵоƬ - * ѧϰʾʹãûֱôķջеκηΡ - *******************************************************************************************/ -#ifndef __LIBTIMER_H__ -#define __LIBTIMER_H__ - -#include "ES8P508x.h" -#include "type.h" - -/* ʱԴѡ */ -typedef enum -{ - TIM_ClkS_PCLK = 0x0 , //ʱԴѡ:ڲPCLK - TIM_ClkS_CK0 = 0x1 , //ʱԴѡ:ⲿCK0ʱ - TIM_ClkS_CK1 = 0x2 , //ʱԴѡ:ⲿCK1ʱ -}TIM_TYPE_CLKS; - -/* ⲿʱӼѡ */ -typedef enum -{ - TIM_EDGE_Rise = 0x0 , //ⲿʱӼѡ: - TIM_EDGE_Fall = 0x1 , //ⲿʱӼѡ:½ - TIM_EDGE_All = 0x2 , //ⲿʱӼѡ: -}TIM_TYPE_EDGE; - - -/* ģʽѡ */ -typedef enum -{ - TIM_Mode_TC0 = 0x0 , //ģʽ:ʱģʽ - TIM_Mode_TC1 = 0x1 , //ģʽ:ʱģʽ - TIM_Mode_CAP = 0x2 , //ģʽ:׽ģʽ - TIM_Mode_PWM = 0x3 , //ģʽ:ģʽ -}TIM_TYPE_MODE; - -/* TIMʼýṹ嶨 */ -typedef struct -{ - TIM_TYPE_CLKS TIM_ClkS; //ʱԴѡ - TYPE_FUNCEN TIM_SYNC; //ⲿʱͬ - TIM_TYPE_EDGE TIM_EDGE; //ⲿʱӼѡ - TIM_TYPE_MODE TIM_Mode; //ģʽѡ -}TIM_BaseInitStruType; - -/* ƥĴֵƥĹģʽ */ -typedef enum -{ - TIM_Go_No = 0x0 , //ƥĴֵƥĹģʽ:ж - TIM_Hold_Int = 0x1 , //ƥĴֵƥĹģʽ:ּж - TIM_Clr_Int = 0x2 , //ƥĴֵƥĹģʽ:㲢¼ж - TIM_Go_Int = 0x3 , //ƥĴֵƥĹģʽ:ж -}TIM_TYPE_MATCON; - -/* ƥĴֵƥ˿ڵĹģʽ */ -typedef enum -{ - TIM_Out_Hold = 0x0 , //ƥĴֵƥ˿ڵĹģʽ - TIM_Out_Low = 0x1 , //ƥĴֵƥ˿ڵĹģʽ0 - TIM_Out_High = 0x2 , //ƥĴֵƥ˿ڵĹģʽ1 - TIM_Out_Switch = 0x3 , //ƥĴֵƥ˿ڵĹģʽȡ -}TIM_TYPE_MATOUT; - -/* ׽ */ -typedef enum -{ - TIM_CapTime_1 = 0x0 , //׽:1 - TIM_CapTime_2 = 0x1 , //׽:2 - TIM_CapTime_3 = 0x2 , //׽:3 - TIM_CapTime_4 = 0x3 , //׽:4 - TIM_CapTime_5 = 0x4 , //׽:5 - TIM_CapTime_6 = 0x5 , //׽:6 - TIM_CapTime_7 = 0x6 , //׽:7 - TIM_CapTime_8 = 0x7 , //׽:8 - TIM_CapTime_9 = 0x8 , //׽:9 - TIM_CapTime_10 = 0x9 , //׽:10 - TIM_CapTime_11 = 0xA , //׽:11 - TIM_CapTime_12 = 0xB , //׽:12 - TIM_CapTime_13 = 0xC , //׽:13 - TIM_CapTime_14 = 0xD , //׽:14 - TIM_CapTime_15 = 0xE , //׽:15 - TIM_CapTime_16 = 0xF , //׽:16 -}TIM_TYPE_CAPT; - -/* PWM */ -typedef enum -{ - POSITIVE = 0X00, // - NEGATIVE = 0X01, // -}T16Nx_PWMOUT_POLAR_Type; - -/* ƹܳʼṹ嶨 */ -typedef struct -{ - TYPE_FUNCEN T16Nx_MOE0; //˿0ʹ - TYPE_FUNCEN T16Nx_MOE1; //˿1ʹ - T16Nx_PWMOUT_POLAR_Type T16Nx_POL0; //T16NxOUT0ѡλ - T16Nx_PWMOUT_POLAR_Type T16Nx_POL1; //T16NxOUT1ѡλ -}T16Nx_PWMInitStruType; - -/* ׽ܳʼṹ嶨 */ -typedef struct -{ - TYPE_FUNCEN TIM_CapRise; //ز׽ʹ - TYPE_FUNCEN TIM_CapFall; //½ز׽ʹ - TYPE_FUNCEN TIM_CapIS0; //˿0ʹ - TYPE_FUNCEN TIM_CapIS1; //˿1ʹ - TIM_TYPE_CAPT TIM_CapTime; //׽ -}TIM_CapInitStruType; - -/* PWMɲƽ */ -typedef enum -{ - PWMBKOUT_Low = 0, - PWMBKOUT_High = 1, -}T16Nx_PWMBKOUT_LEVEl; - -/* PWMɲźżѡ */ -typedef enum -{ - PWMBKP_High = 0, - PWMBKP_Low = 1, -}T16Nx_PWMBKP_LEVEl; - -/*PWMɲźԴѡ*/ -typedef enum -{ - PWMBKPS_PINT0 = 0, - PWMBKPS_PINT1 = 1, - PWMBKPS_PINT2 = 2, - PWMBKPS_PINT3 = 3, - PWMBKPS_PINT4 = 4, - PWMBKPS_PINT5 = 5, - PWMBKPS_PINT6 = 6, - PWMBKPS_PINT7 = 7, -}T16Nx_PWMBKP_S; - -/*PWMɲ*/ -typedef struct -{ - - T16Nx_PWMBKOUT_LEVEl T16Nx_PWMBKL0; //PWMͨ0ɲƽѡ - T16Nx_PWMBKOUT_LEVEl T16Nx_PWMBKL1; //PWMͨ1ɲƽѡ - T16Nx_PWMBKP_S T16Nx_PWMBKS; //PWMͨźԴѡ - T16Nx_PWMBKP_LEVEl T16Nx_PWMBKPS; //PWMͨɲźżѡ - TYPE_FUNCEN T16Nx_PWMBKEN; //PWMɲʹ -}T16Nx_PWMBK_Type; - -/* ж */ -typedef enum -{ - TIM_IT_MAT0 = 0x01 , - TIM_IT_MAT1 = 0x02 , - TIM_IT_MAT2 = 0x04 , - TIM_IT_MAT3 = 0x08 , - TIM_IT_N = 0x10 , - TIM_IT_CAP0 = 0x20 , - TIM_IT_CAP1 = 0x40 , - TIM_IT_PBK = 0x80 , -}TIM_TYPE_IT; - -typedef enum -{ - TIM_IF_MAT0 = 0x01 , - TIM_IF_MAT1 = 0x02 , - TIM_IF_MAT2 = 0x04 , - TIM_IF_MAT3 = 0x08 , - TIM_IF_N = 0x10 , - TIM_IF_CAP0 = 0x20 , - TIM_IF_CAP1 = 0x40 , - TIM_IF_PBK = 0x80 , -}TIM_TYPE_IF; - -/* ƥĴ */ -typedef enum -{ - TIM_MAT0 = 0x00 , - TIM_MAT1 = 0x01 , - TIM_MAT2 = 0x02 , - TIM_MAT3 = 0x03 , -}TIM_TYPE_MATX; - -/*T16N ADCʹܿ*/ -typedef enum -{ - T16Nx_MAT0 = 0x02, //PWMͨ0ƥ0ʹ - T16Nx_MAT1 = 0x04, //PWMͨ0ƥ1ʹ - T16Nx_MAT2 = 0x20, //PWMͨ1ƥ2ʹ - T16Nx_MAT3 = 0x40, //PWMͨ1ƥ3ʹ -}T16Nx_PWMTRG_type; - -/*************TIMģ궨************/ - -/* TIMģʹܿ */ -#define T16N0_Enable() (T16N0->CON0.EN = 1) -#define T16N1_Enable() (T16N1->CON0.EN = 1) -#define T16N2_Enable() (T16N2->CON0.EN = 1) -#define T16N3_Enable() (T16N3->CON0.EN = 1) -#define T32N0_Enable() (T32N0->CON0.EN = 1) -#define T16N0_Disable() (T16N0->CON0.EN = 0) -#define T16N1_Disable() (T16N1->CON0.EN = 0) -#define T16N2_Disable() (T16N2->CON0.EN = 0) -#define T16N3_Disable() (T16N3->CON0.EN = 0) -#define T32N0_Disable() (T32N0->CON0.EN = 0) - -/* 첽дʹܿ */ -#define T16N0_ASYNCWR_Enable() (T16N0->CON0.ASYWEN = 1) -#define T16N1_ASYNCWR_Enable() (T16N1->CON0.ASYWEN = 1) -#define T16N2_ASYNCWR_Enable() (T16N2->CON0.ASYWEN = 1) -#define T16N3_ASYNCWR_Enable() (T16N3->CON0.ASYWEN = 1) -#define T32N0_ASYNCWR_Enable() (T32N0->CON0.ASYNCWREN = 1) -#define T16N0_ASYNCWR_Disable() (T16N0->CON0.ASYWEN= 0) -#define T16N1_ASYNCWR_Disable() (T16N1->CON0.ASYWEN = 0) -#define T16N2_ASYNCWR_Disable() (T16N2->CON0.ASYWEN = 0) -#define T16N3_ASYNCWR_Disable() (T16N3->CON0.ASYWEN = 0) -#define T32N0_ASYNCWR_Disable() (T32N0->CON0.ASYNCWREN = 0) - -/* PWMʹܿ */ -#define T16N0_PwmOut0_Enable() (T16N0->CON2.MOE0 = 1) -#define T16N1_PwmOut0_Enable() (T16N1->CON2.MOE0 = 1) -#define T16N2_PwmOut0_Enable() (T16N2->CON2.MOE0 = 1) -#define T16N3_PwmOut0_Enable() (T16N3->CON2.MOE0 = 1) -#define T32N0_PwmOut0_Enable() (T32N0->CON2.MOE0 = 1) -#define T16N0_PwmOut1_Enable() (T16N0->CON2.MOE1 = 1) -#define T16N1_PwmOut1_Enable() (T16N1->CON2.MOE1 = 1) -#define T16N2_PwmOut1_Enable() (T16N2->CON2.MOE1 = 1) -#define T16N3_PwmOut1_Enable() (T16N3->CON2.MOE1 = 1) -#define T32N0_PwmOut1_Enable() (T32N0->CON2.MOE1 = 1) -#define T16N0_PwmOut0_Disable() (T16N0->CON2.MOE0 = 0) -#define T16N1_PwmOut0_Disable() (T16N1->CON2.MOE0 = 0) -#define T16N2_PwmOut0_Disable() (T16N2->CON2.MOE0 = 0) -#define T16N3_PwmOut0_Disable() (T16N3->CON2.MOE0 = 0) -#define T32N0_PwmOut0_Disable() (T32N0->CON2.MOE0 = 0) -#define T16N0_PwmOut1_Disable() (T16N0->CON2.MOE1 = 0) -#define T16N1_PwmOut1_Disable() (T16N1->CON2.MOE1 = 0) -#define T16N2_PwmOut1_Disable() (T16N2->CON2.MOE1 = 0) -#define T16N3_PwmOut1_Disable() (T16N3->CON2.MOE1 = 0) -#define T32N0_PwmOut1_Disable() (T32N0->CON2.MOE1 = 0) - -/************T16ģ麯***********/ -void T16Nx_BaseInit(T16N_TypeDef* T16Nx,TIM_BaseInitStruType* TIM_BaseInitStruct); -void T16Nx_CapInit(T16N_TypeDef* T16Nx,TIM_CapInitStruType* TIM_CapInitStruct); -void T16Nx_MAT0ITConfig(T16N_TypeDef* T16Nx,TIM_TYPE_MATCON Type); -void T16Nx_MAT1ITConfig(T16N_TypeDef* T16Nx,TIM_TYPE_MATCON Type); -void T16Nx_MAT2ITConfig(T16N_TypeDef* T16Nx,TIM_TYPE_MATCON Type); -void T16Nx_MAT3ITConfig(T16N_TypeDef* T16Nx,TIM_TYPE_MATCON Type); -void T16Nx_MAT0Out0Config(T16N_TypeDef* T16Nx,TIM_TYPE_MATOUT Type); -void T16Nx_MAT1Out0Config(T16N_TypeDef* T16Nx,TIM_TYPE_MATOUT Type); -void T16Nx_MAT2Out1Config(T16N_TypeDef* T16Nx,TIM_TYPE_MATOUT Type); -void T16Nx_MAT3Out1Config(T16N_TypeDef* T16Nx,TIM_TYPE_MATOUT Type); -void T16Nx_ITConfig(T16N_TypeDef* T16Nx,TIM_TYPE_IT Type,TYPE_FUNCEN NewState); -void T16Nx_PWMOutConfig(T16N_TypeDef* T16Nx,T16Nx_PWMInitStruType* T16Nx_PWMInitStruct); -void T16Nx_PWMBK_Config(T16N_TypeDef* T16Nx,T16Nx_PWMBK_Type* type); -void T16Nx_TRG_Config(T16N_TypeDef* T16Nx,T16Nx_PWMTRG_type Type,TYPE_FUNCEN NewState); -FlagStatus T16Nx_GetPWMBKF(T16N_TypeDef* T16Nx); -void T16Nx_ResetPWMBKF(T16N_TypeDef* T16Nx); -void T16Nx_SetCNT(T16N_TypeDef* T16Nx,uint16_t Value); -void T16Nx_SetPRECNT(T16N_TypeDef* T16Nx,uint8_t Value); -void T16Nx_SetPREMAT(T16N_TypeDef* T16Nx,uint8_t Value); -void T16Nx_SetMAT0(T16N_TypeDef* T16Nx,uint16_t Value); -void T16Nx_SetMAT1(T16N_TypeDef* T16Nx,uint16_t Value); -void T16Nx_SetMAT2(T16N_TypeDef* T16Nx,uint16_t Value); -void T16Nx_SetMAT3(T16N_TypeDef* T16Nx,uint16_t Value); -uint16_t T16Nx_GetMAT0(T16N_TypeDef* T16Nx); -uint16_t T16Nx_GetMAT1(T16N_TypeDef* T16Nx); -uint16_t T16Nx_GetMAT2(T16N_TypeDef* T16Nx); -uint16_t T16Nx_GetMAT3(T16N_TypeDef* T16Nx); -uint16_t T16Nx_GetCNT(T16N_TypeDef* T16Nx); -uint8_t T16Nx_GetPRECNT(T16N_TypeDef* T16Nx); -FlagStatus T16Nx_GetFlagStatus(T16N_TypeDef* T16Nx,TIM_TYPE_IF TIM_Flag); -ITStatus T16Nx_GetITStatus(T16N_TypeDef* T16Nx,TIM_TYPE_IT TIM_Flag); -void T16Nx_ClearIFPendingBit(T16N_TypeDef* T16Nx,TIM_TYPE_IF TIM_Flag); -/************************************T32ģ麯********************************************************/ -void T32Nx_BaseInit(T32N_TypeDef* T32Nx,TIM_BaseInitStruType* TIM_BaseInitStruct); -void T32Nx_CapInit(T32N_TypeDef* T32Nx,TIM_CapInitStruType* TIM_CapInitStruct); -void T32Nx_MAT0ITConfig(T32N_TypeDef* T32Nx,TIM_TYPE_MATCON Type); -void T32Nx_MAT1ITConfig(T32N_TypeDef* T32Nx,TIM_TYPE_MATCON Type); -void T32Nx_MAT2ITConfig(T32N_TypeDef* T32Nx,TIM_TYPE_MATCON Type); -void T32Nx_MAT3ITConfig(T32N_TypeDef* T32Nx,TIM_TYPE_MATCON Type); -void T32Nx_MAT0Out0Config(T32N_TypeDef* T32Nx,TIM_TYPE_MATOUT Type); -void T32Nx_MAT1Out0Config(T32N_TypeDef* T32Nx,TIM_TYPE_MATOUT Type); -void T32Nx_MAT2Out1Config(T32N_TypeDef* T32Nx,TIM_TYPE_MATOUT Type); -void T32Nx_MAT3Out1Config(T32N_TypeDef* T32Nx,TIM_TYPE_MATOUT Type); -void T32Nx_ITConfig(T32N_TypeDef* T32Nx,TIM_TYPE_IT Type,TYPE_FUNCEN NewState); -void T32Nx_SetCNT(T32N_TypeDef* T16Nx,uint32_t Value); -void T32Nx_SetPRECNT(T32N_TypeDef* T32Nx,uint8_t Value); -void T32Nx_SetPREMAT(T32N_TypeDef* T32Nx,uint8_t Value); -void T32Nx_SetMAT0(T32N_TypeDef* T32Nx,uint32_t Value); -void T32Nx_SetMAT1(T32N_TypeDef* T32Nx,uint32_t Value); -void T32Nx_SetMAT2(T32N_TypeDef* T32Nx,uint32_t Value); -void T32Nx_SetMAT3(T32N_TypeDef* T32Nx,uint32_t Value); -uint32_t T32Nx_GetMAT0(T32N_TypeDef* T32Nx); -uint32_t T32Nx_GetMAT1(T32N_TypeDef* T32Nx); -uint32_t T32Nx_GetMAT2(T32N_TypeDef* T32Nx); -uint32_t T32Nx_GetMAT3(T32N_TypeDef* T32Nx); -uint32_t T32Nx_GetCNT(T32N_TypeDef* T32Nx); -uint8_t T32Nx_GetPRECNT(T32N_TypeDef* T32Nx); -FlagStatus T32Nx_GetFlagStatus(T32N_TypeDef* T32Nx,TIM_TYPE_IF TIM_Flag); -ITStatus T32Nx_GetITStatus(T32N_TypeDef* T32Nx,TIM_TYPE_IT TIM_Flag); -void T32Nx_ClearIFPendingBit(T32N_TypeDef* T32Nx,TIM_TYPE_IF TIM_Flag); - -#endif - -/*************************END OF FILE**********************/ diff --git a/bsp/essemi/es8p508x/libraries/Library/Include/lib_uart.h b/bsp/essemi/es8p508x/libraries/Library/Include/lib_uart.h deleted file mode 100644 index 7b0d0fe1df..0000000000 --- a/bsp/essemi/es8p508x/libraries/Library/Include/lib_uart.h +++ /dev/null @@ -1,171 +0,0 @@ -/*************************************************************** - *Copyright (C), 2017, Shanghai Eastsoft Microelectronics Co., Ltd. - *ļ lib_uart.h - * ߣ Liut - * V1.00 - * ڣ 2017/07/14 - * UARTģ⺯ͷļ - * ע ES8P508xоƬ - ѧϰʾʹãûֱôķջеκηΡ - ***************************************************************/ -#ifndef __LIBUART_H__ -#define __LIBUART_H__ - -#include "ES8P508x.h" -#include "type.h" -#include "system_ES8P508x.h" - -/* ֹ֡ͣλѡ */ -typedef enum -{ - UART_StopBits_1 = 0x0 , //ֹ֡ͣλ1λ - UART_StopBits_2 = 0x1 , //ֹ֡ͣλ2λ -}UART_TYPE_TXFS; - -/* ݸʽ */ -typedef enum -{ - UART_DataMode_7 = 0x0 , //ݸʽ:7λ - UART_DataMode_8 = 0x1 , //ݸʽ:8λ - UART_DataMode_9 = 0x2 , //ݸʽ:9λ - UART_DataMode_7Odd = 0x4 , //ݸʽ:7λ+У - UART_DataMode_7Even = 0x5 , //ݸʽ:7λ+żУ - UART_DataMode_8Odd = 0x6 , //ݸʽ:8λ+У - UART_DataMode_8Even = 0x7 , //ݸʽ:8λ+żУ -}UART_TYPE_DATAMOD; - -/* ˿ڼ */ -typedef enum -{ - UART_Polar_Normal = 0x0 , //Ͷ˿ڼ: - UART_Polar_Opposite = 0x1 , //Ͷ˿ڼ: -}UART_TYPE_RTXP; - -/* ʷʱѡ */ -typedef enum -{ - UART_Clock_1 = 0x1 , //ʷʱ:PCLK - UART_Clock_2 = 0x2 , //ʷʱ:PCLK/2 - UART_Clock_4 = 0x3 , //ʷʱ:PCLK/4 - UART_Clock_8 = 0x4 , //ʷʱ:PCLK/8 - -}UART_TYPE_BCS; - -/* UARTʼýṹ嶨 */ -typedef struct -{ - UART_TYPE_TXFS UART_StopBits; //ֹ֡ͣλѡ - UART_TYPE_DATAMOD UART_TxMode; //֡ʽ - UART_TYPE_RTXP UART_TxPolar; //Ͷ˿ڼ - UART_TYPE_DATAMOD UART_RxMode; //֡ʽ - UART_TYPE_RTXP UART_RxPolar; //ն˿ڼ - uint32_t UART_BaudRate; //䲨 - UART_TYPE_BCS UART_ClockSet; //ʷʱѡ -}UART_InitStruType; - -/* жѡ */ -typedef enum -{ - UART_IT_TB = 0x0001 , - UART_IT_RB = 0x0002 , - UART_IT_RO = 0x0004 , - UART_IT_FE = 0x0008 , - UART_IT_PE = 0x0010 , - UART_IT_TBWE = 0x0020 , - UART_IT_TXIDLE = 0x1000 , - UART_IT_RXIDLE = 0x2000 , -}UART_TYPE_IT; - -/* ־λ */ -typedef enum -{ - UART_FLAG_TB = 0x0001 , - UART_FLAG_RB = 0x0002 , - UART_FLAG_RO = 0x0004 , - UART_FLAG_FE = 0x0008 , - UART_FLAG_PE = 0x0010 , - UART_FLAG_TBWE = 0x0020 , - UART_FLAG_TXIDLE = 0x1000 , - UART_FLAG_RXIDLE = 0x2000 , -}UART_TYPE_FLAG; - -/* жϱ־λ */ -typedef enum -{ - UART_Clr_RO = 0x0004 , - UART_Clr_FE = 0x0008 , - UART_Clr_PE = 0x0010 , - UART_Clr_TBWE = 0x0020 , -}UART_CLR_IF; - -/* ͡жģʽ */ -typedef enum -{ - UART_TRBIM_Byte = 0x0 , //ж:ֽ - UART_TRBIM_HalfWord = 0x1 , //ж: - UART_TRBIM_Word = 0x2 , //ж: -}UART_TYPE_TRBIM; - -/*************UARTģ궨************/ -/* ʹܿ */ -#define UART0_TxEnable() (UART0->CON.TXEN = 1) -#define UART1_TxEnable() (UART1->CON.TXEN = 1) -#define UART2_TxEnable() (UART2->CON.TXEN = 1) -#define UART3_TxEnable() (UART3->CON.TXEN = 1) -#define UART4_TxEnable() (UART4->CON.TXEN = 1) -#define UART5_TxEnable() (UART5->CON.TXEN = 1) -#define UART0_TxDisable() (UART0->CON.TXEN = 0) -#define UART1_TxDisable() (UART1->CON.TXEN = 0) -#define UART2_TxDisable() (UART2->CON.TXEN = 0) -#define UART3_TxDisable() (UART3->CON.TXEN = 0) -#define UART4_TxDisable() (UART4->CON.TXEN = 0) -#define UART5_TxDisable() (UART5->CON.TXEN = 0) - -/* ʹܿ */ -#define UART0_RxEnable() (UART0->CON.RXEN = 1) -#define UART1_RxEnable() (UART1->CON.RXEN = 1) -#define UART2_RxEnable() (UART2->CON.RXEN = 1) -#define UART3_RxEnable() (UART3->CON.RXEN = 1) -#define UART4_RxEnable() (UART4->CON.RXEN = 1) -#define UART5_RxEnable() (UART5->CON.RXEN = 1) -#define UART0_RxDisable() (UART0->CON.RXEN = 0) -#define UART1_RxDisable() (UART1->CON.RXEN = 0) -#define UART2_RxDisable() (UART2->CON.RXEN = 0) -#define UART3_RxDisable() (UART3->CON.RXEN = 0) -#define UART4_RxDisable() (UART4->CON.RXEN = 0) -#define UART5_RxDisable() (UART5->CON.RXEN = 0) - -/* λ */ -#define UART0_TxRst() (UART0->CON.TRST = 1) -#define UART1_TxRst() (UART1->CON.TRST = 1) -#define UART2_TxRst() (UART2->CON.TRST = 1) -#define UART3_TxRst() (UART3->CON.TRST = 1) -#define UART4_TxRst() (UART4->CON.TRST = 1) -#define UART5_TxRst() (UART5->CON.TRST = 1) - -/* λ */ -#define UART0_RxRst() (UART0->CON.RRST = 1) -#define UART1_RxRst() (UART1->CON.RRST = 1) -#define UART2_RxRst() (UART2->CON.RRST = 1) -#define UART3_RxRst() (UART3->CON.RRST = 1) -#define UART4_RxRst() (UART4->CON.RRST = 1) -#define UART5_RxRst() (UART5->CON.RRST = 1) - -/************UARTģ麯***********/ -void UART_Init(UART_TypeDef* UARTx,UART_InitStruType* UART_InitStruct); -void UART_ITConfig(UART_TypeDef* UARTx,UART_TYPE_IT UART_IT,TYPE_FUNCEN NewState); -void UART_TBIMConfig(UART_TypeDef* UARTx,UART_TYPE_TRBIM Type); -void UART_RBIMConfig(UART_TypeDef* UARTx,UART_TYPE_TRBIM Type); -void UART_SendByte(UART_TypeDef* UARTx,uint8_t Temp08); -void UART_SendHalfWord(UART_TypeDef* UARTx,uint16_t Temp16); -void UART_SendWord(UART_TypeDef* UARTx,uint32_t Temp32); -uint8_t UART_RecByte(UART_TypeDef* UARTx); -uint16_t UART_RecHalfWord(UART_TypeDef* UARTx); -uint32_t UART_RecWord(UART_TypeDef* UARTx); -FlagStatus UART_GetFlagStatus(UART_TypeDef* UARTx,UART_TYPE_FLAG UART_Flag); -ITStatus UART_GetITStatus(UART_TypeDef* UARTx,UART_TYPE_IT UART_Flag); -void UART_ClearITPendingBit(UART_TypeDef* UARTx,UART_CLR_IF UART_Flag); - -#endif - -/*************************END OF FILE**********************/ diff --git a/bsp/essemi/es8p508x/libraries/Library/Include/lib_wdt.h b/bsp/essemi/es8p508x/libraries/Library/Include/lib_wdt.h deleted file mode 100644 index 45ad9d4287..0000000000 --- a/bsp/essemi/es8p508x/libraries/Library/Include/lib_wdt.h +++ /dev/null @@ -1,100 +0,0 @@ -/*************************************************************** - *Copyright (C), 2017, Shanghai Eastsoft Microelectronics Co., Ltd - *ļ lib_wdt.c - * ߣ Liut - * V1.00 - * ڣ 2017/02/04 - * Źģ⺯ - * ע ES8P508xоƬ - ѧϰʾʹãûֱôķջеκηΡ - ***************************************************************/ -#ifndef __LIBWDT_H__ -#define __LIBWDT_H__ - -#include "system_ES8P508x.h" -#include "ES8P508x.h" -#include "type.h" - -/* WDTʱѡ */ -typedef enum -{ - WDT_CLOCK_PCLK = 0x0, //PCLK - WDT_CLOCK_WDT = 0x1, //WDTʱԴ32kHz -} WDT_TYPE_CLKS; - -/* ʼṹ */ -typedef struct -{ - uint32_t WDT_Tms; //ʱʱ䣬λms - TYPE_FUNCEN WDT_IE; //жʹ - TYPE_FUNCEN WDT_Rst; //λʹ - WDT_TYPE_CLKS WDT_Clock;//ʱѡ -} IWDT_InitStruType; - -typedef enum -{ - WDT_WIN_25 = 0x0, //25%ڽֹιιλ - WDT_WIN_50 = 0x1, //50%ڽֹιιλ - WDT_WIN_75 = 0x2, //75%ڽֹιιλ - WDT_WIN_100 = 0x3, //ֹιιʹŹ -} WDT_TYPE_WIN; - -/* ʼṹ */ -typedef struct -{ - uint32_t WDT_Tms; //ʱʱ䣬λms - TYPE_FUNCEN WDT_IE; //жʹ - TYPE_FUNCEN WDT_Rst; //λʹ - WDT_TYPE_CLKS WDT_Clock;//ʱѡ - WDT_TYPE_WIN WDT_Win; //ֹι -} WWDT_InitStruType; - -#define IWDT_RegUnLock() (IWDT->LOCK.Word = 0x1ACCE551) -#define IWDT_RegLock() (IWDT->LOCK.Word = 0x0) - -#define IWDT_Enable() {IWDT_RegUnLock();IWDT->CON.EN = 1;IWDT_RegLock();} -#define IWDT_Disable() {IWDT_RegUnLock();IWDT->CON.EN = 0;IWDT_RegLock();} - -#define IWDT_Clear() {IWDT_RegUnLock();IWDT->INTCLR.INTCLR = 0;IWDT_RegLock();} - -#define IWDT_ITEnable() {IWDT_RegUnLock();IWDT->CON.IE = 1;IWDT_RegLock();} -#define IWDT_ITDisable() {IWDT_RegUnLock();IWDT->CON.IE = 0;IWDT_RegLock();} - -#define IWDT_RstEnable() {IWDT_RegUnLock();IWDT->CON.RSTEN = 1;IWDT_RegLock();} -#define IWDT_RstDisable() {IWDT_RegUnLock();IWDT->CON.RSTEN = 0;IWDT_RegLock();} - -#define IWDT_CLOCK_PCLK() {IWDT_RegUnLock();IWDT->CON.CLKS = 0;IWDT_RegLock();} -#define IWDT_CLOCK_WDT() {IWDT_RegUnLock();IWDT->CON.CLKS = 1;IWDT_RegLock();} - -#define WWDT_RegUnLock() (WWDT->LOCK.Word = 0x1ACCE551) -#define WWDT_RegLock() (WWDT->LOCK.Word = 0x0) - -#define WWDT_Enable() {WWDT_RegUnLock();WWDT->CON.EN = 1;WWDT_RegLock();} -#define WWDT_Disable() {WWDT_RegUnLock();WWDT->CON.EN = 0;WWDT_RegLock();} - -#define WWDT_Clear() {WWDT_RegUnLock();WWDT->INTCLR.INTCLR = 0;WWDT_RegLock();} - -#define WWDT_ITEnable() {WWDT_RegUnLock();WWDT->CON.IE = 1;WWDT_RegLock();} -#define WWDT_ITDisable() {WWDT_RegUnLock();WWDT->CON.IE = 0;WWDT_RegLock();} - -#define WWDT_RstEnable() {WWDT_RegUnLock();WWDT->CON.RSTEN = 1;WWDT_RegLock();} -#define WWDT_RstDisable() {WWDT_RegUnLock();WWDT->CON.RSTEN = 0;WWDT_RegLock();} - -#define WWDT_CLOCK_PCLK() {WWDT_RegUnLock();WWDT->CON.CLKS = 0;WWDT_RegLock();} -#define WWDT_CLOCK_WDT() {WWDT_RegUnLock();WWDT->CON.CLKS = 1;WWDT_RegLock();} - -void IWDT_Init(IWDT_InitStruType *IWDT_InitStruct); -void IWDT_SetReloadValue(uint32_t Value); -uint32_t IWDT_GetValue(void); -FlagStatus IWDT_GetFlagStatus(void); -FlagStatus IWDT_GetITStatus(void); -void WWDT_Init(WWDT_InitStruType *WDT_InitStruct); -void WWDT_SetReloadValue(uint32_t Value); -uint32_t WWDT_GetValue(void); -FlagStatus WWDT_GetFlagStatus(void); -FlagStatus WWDT_GetITStatus(void); - -#endif - -/*************************END OF FILE**********************/ - diff --git a/bsp/essemi/es8p508x/libraries/Library/Include/type.h b/bsp/essemi/es8p508x/libraries/Library/Include/type.h deleted file mode 100644 index a23d72e8bd..0000000000 --- a/bsp/essemi/es8p508x/libraries/Library/Include/type.h +++ /dev/null @@ -1,19 +0,0 @@ -/********************************************************* - *Copyright (C), 2017, Shanghai Eastsoft Microelectronics Co., Ltd. - *ļ: type.h - * : Liut - * : V1.01 - * : 2017/11/01 - * : type define - * ע: HRSDK-GDB-8P508x - ѧϰʾʹãûֱôķջеκηΡ - **********************************************************/ -#ifndef __TYPE_H__ -#define __TYPE_H__ - -typedef enum {DISABLE = 0, ENABLE = !DISABLE} TYPE_FUNCEN,FuncState,TYPE_PINTIE,TYPE_PINTMASK,TYPE_BUZZEN; -typedef enum {RESET = 0, SET = !RESET} FlagStatus, ITStatus, PinStatus; -typedef enum {ERROR = 0, SUCCESS = !ERROR} ErrorStatus; - - -#endif diff --git a/bsp/essemi/es8p508x/libraries/Library/Source/irqhandler.c b/bsp/essemi/es8p508x/libraries/Library/Source/irqhandler.c deleted file mode 100644 index bd0d9b0f14..0000000000 --- a/bsp/essemi/es8p508x/libraries/Library/Source/irqhandler.c +++ /dev/null @@ -1,27 +0,0 @@ -#include "irqhandler.h" - -void NMI_IRQHandler(void) -{ - -} - -void HardFault_IRQHandler(void) -{ - while(1) - { - } -} - -void SVC_IRQHandler(void) -{ - -} - -void PendSV_IRQHandler(void) -{ - -} -void SysTick_Handler(void) -{ - systick_irq_cbk(); -} diff --git a/bsp/essemi/es8p508x/libraries/Library/Source/lib_adc.c b/bsp/essemi/es8p508x/libraries/Library/Source/lib_adc.c deleted file mode 100644 index 23aea8a229..0000000000 --- a/bsp/essemi/es8p508x/libraries/Library/Source/lib_adc.c +++ /dev/null @@ -1,301 +0,0 @@ -/*************************************************************** - *Copyright (C), 2017, Shanghai Eastsoft Microelectronics Co., Ltd - *ļ lib_timer.c - * ߣ Liut - * V1.00 - * ڣ 2017/07/14 - * ADCģ⺯ - * ע ES8P508xоƬ - ѧϰʾʹãûֱôķջеκηΡ - ***************************************************************/ -#include "lib_adc.h" - -/*************************************************************** - ADC_Init - ʼADCģ - ֵʼýṹַ - ֵ - ֵ - ***************************************************************/ -void ADC_Init(ADC_InitStruType * ADC_InitStruct) -{ - ADC->VREFCON.VREF_EN = ENABLE; //ڲVREFPʹ - ADC->VREFCON.IREF_EN = ENABLE; //IREFʹλ - ADC->CON1.VCMBUF_EN = ENABLE; //ADCģѹVCM BUFʹ - ADC ->CON1.VCMBUF_HS = ENABLE; //ADCģѹVCM BUFģʽʹ - ADC->CON1.HSEN = ENABLE; //ADCתٶȣ - ADC->CHS.VDD5_FLAG_EN = DISABLE; //VDD - - ADC->CON1.CLKS = ADC_InitStruct->ADC_ClkS; //ADCCON1:bit3 ADCʱԴѡ - ADC->CON1.CLKDIV = ADC_InitStruct->ADC_ClkDiv; //ADCCON1:bit2-0 ADCʱԴԤƵ - ADC->CON1.VREFP = ADC_InitStruct->ADC_VrefP; //ADCCON1:bit9-8 ADCοѹѡ - ADC->CON1.SMPS = ADC_InitStruct->ADC_SampS; //ADCCON1:bit12 ADCģʽѡ - ADC->CHS.CHS = ADC_InitStruct->ADC_ChS; //ADCCHS:bit0-3 ADCģͨѡ - ADC->CON1.ST = ADC_InitStruct->ST; //ADCCON1:bit20-16 ADCʱѡ ST*2+1Tadclk - //ADC->VREFCON.VREF_SEL=ADC_InitStruct->VREF_SEL;//ڲοѹѡ - - ADC->CON1.VREFN = ADC_InitStruct->ADC_VREFN; //οѹʹλ - ADC->CON1.VRBUF_EN = ADC_InitStruct->ADC_VRBUF_EN; //VREF BUFʹλ -} - - -/*************************************************************** - ADC_Set_CH - ѡADCģͨ - ֵͨ - ֵ - ֵ - ***************************************************************/ -void ADC_Set_CH(ADC_TYPE_CHS AdcCH) -{ - ADC->CHS.CHS = AdcCH; -} - -/*************************************************************** - ADC_GetConvValue - ȡADCת - ֵ - ֵ - ֵתֵ - ***************************************************************/ -uint16_t ADC_GetConvValue(void) -{ - return ((uint16_t)ADC->DR.DR); -} - -/*************************************************************** - ADC_GetConvStatus - ȡADCת״̬ - ֵ - ֵ - ֵRESET()/SET(ת) - ***************************************************************/ -FlagStatus ADC_GetConvStatus(void) -{ - FlagStatus bitstatus = RESET; - - /* ת״̬Ĵ */ - if ((ADC->CON0.TRIG != (uint32_t)RESET)) - bitstatus = SET; //ת - else - bitstatus = RESET; //ת - - return bitstatus; -} - -/*************************************************************** - ADC_ACPConfig - ADC ԶȽϹܳʼ - ֵADC_ACP_InitStruct ԶȽϹܳʼṹ - ֵ - ֵSUCCESS ɹ - ERROR ʧ - ***************************************************************/ -ErrorStatus ADC_ACPConfig(ADC_ACP_TypeDef *ADC_ACP_InitStruct) -{ - if(ADC_ACP_InitStruct->ACPC_OVER_TIME > ADC_ACPC_OVFL_TIME_MAX - ||ADC_ACP_InitStruct->ACPC_TIMES > ADC_ACPC_TIMES_MAX - ||ADC_ACP_InitStruct->ACPC_MIN_TARGET > ADC_ACP_MIN_MAX - ||ADC_ACP_InitStruct->ACPC_MAX_TARGET > ADC_ACP_MAX_MAX) - { - return ERROR; - } - - if(ADC_ACP_InitStruct->ACP_EN == ENABLE) - { - if(ADC->CON1.CLKS == ADC_ClkS_PCLK) - { - ADC->ACPC.CLKS = ADC_ACPC_CLKS_PCLK; - } - else - { - ADC->ACPC.CLKS = ADC_ACPC_CLKS_LRC; - } - - ADC->ACPC.OVFL_TIME = ADC_ACP_InitStruct ->ACPC_OVER_TIME; - ADC->ACPC.TIMES = ADC_ACP_InitStruct->ACPC_TIMES; - ADC->IE.ACPOVIE = ENABLE; - - /* û߷ֵó0(Сֵ)ǿΪرոù */ - if(ADC_ACP_InitStruct ->ACPC_MAX_TARGET ==0x0) - { - ADC->IE.ACPMAXIE = DISABLE; - } - else - { - ADC->ACPCMP.CMP_MAX =ADC_ACP_InitStruct ->ACPC_MAX_TARGET; - ADC->IE.ACPMAXIE = ENABLE; - } - - /* ûͷֵó0xfff(ֵ)ǿΪرոù */ - if(ADC_ACP_InitStruct ->ACPC_MIN_TARGET == 0xfff) - { - ADC->IE.ACPMINIE = DISABLE; - } - else - { - ADC->ACPCMP.CMP_MIN =ADC_ACP_InitStruct ->ACPC_MIN_TARGET; - ADC->IE.ACPMINIE = ENABLE; - } - - ADC->CON0.ACP_EN = ENABLE; - - } - else - { - ADC->CON0.ACP_EN = DISABLE; - } - - return SUCCESS; -} - -/*************************************************************** - ADC_SampStart - ADC - - ֵ - ֵ - ֵSUCCESS ɹ - ERROR ʧ - ***************************************************************/ -ErrorStatus ADC_SoftStart(void) -{ - if(ADC->CON1.SMPS == ADC_SMPS_HARD) - return ERROR; - - ADC ->CON1.SMPON = SET; - return SUCCESS; -} - -/*************************************************************** - ADC_SampStop - ADC -ֹͣ - ֵ - ֵ - ֵSUCCESS ɹ - ERROR ʧ - ***************************************************************/ -ErrorStatus ADC_SoftStop(void) -{ - if(ADC->CON1.SMPS == ADC_SMPS_HARD) - return ERROR; - - ADC->CON1.SMPON = RESET; - return SUCCESS; -} - -/*************************************************************** - ADC_GetACPMeanValue - ADC õԶȽƽֵ - ֵ - ֵ - ֵ - ***************************************************************/ -uint16_t ADC_GetACPMeanValue(void) -{ - return ((uint16_t)ADC->ACPMEAN.MEAN_DATA); -} - -/*************************************************************** - ADC_GetACPMINValue - ADC õԶȽƽֵ - ֵ - ֵ - ֵ - ***************************************************************/ -uint16_t ADC_GetACPMinValue(void) -{ - return ((uint16_t)ADC->ACPCMP.CMP_MIN); -} - -/*************************************************************** - ADC_GetACPMAXValue - ADC õԶȽƽֵ - ֵ - ֵ - ֵ - ***************************************************************/ -uint16_t ADC_GetACPMaxValue(void) -{ - return ((uint16_t)ADC->ACPCMP.CMP_MAX); -} - -/*************************************************************** - ADC_GetFlagStatus - ȡADC־λ״̬ - ֵIFNameADCжϱ־ - ֵ - ֵSET/RESET - ***************************************************************/ -FlagStatus ADC_GetFlagStatus(ADC_TYPE_IF IFName) -{ - FlagStatus bitstatus = RESET; - - /* жϱ־λ */ - if (((ADC->IF.Word & IFName) != (uint32_t)RESET)) - bitstatus = SET; //ת - else - bitstatus = RESET; //ж - - return bitstatus; -} - -/*************************************************************** - ADC_GetITStatus - ȡADCж״̬δʹӦжʱ᷵SET - ֵ - ֵ - ֵSETжϣ/RESETжϣ - ***************************************************************/ -ITStatus ADC_GetITStatus(ADC_TYPE_IE IEName) -{ - ITStatus bitstatus = RESET; - - /* жϱ־λ */ - if (((ADC->IE.Word & IEName) != (uint32_t)RESET)) - bitstatus = SET; //תɣж - else - bitstatus = RESET; //ж - - return bitstatus; -} - -/*************************************************************** - ADC_ClearIFStatus - ADC ضж - ֵIFName жѡ - ADC_IF ADCж - ADC_IF_ACPMIN Զתͷֵж - ADC_IF_ACPMAX Զת߷ֵж - ADC_IF_ACPOVER Զתж - ֵ - ֵSUCCESS ɹ - ERROR ʧ - ***************************************************************/ -ErrorStatus ADC_ClearIFStatus(ADC_TYPE_IF IFName) -{ - ADC->IF.Word = (uint32_t)IFName; - - return SUCCESS; -} -/*************************************************************** - ADC_Reset - ADCλ - ֵ - ֵ - ֵ - ***************************************************************/ -void ADC_Reset(void) -{ - ADC->CON0.Word = 0x00000030; - ADC->CON1.Word = 0x00041000; - ADC->CHS.Word = 0x00000100; - ADC->IE.Word = 0x00000000; - ADC->IF.Word = 0x00000000; - ADC->ACPC.Word = 0x00000000; - ADC->ACPCMP.Word = 0x0FFF0000; - ADC->VREFCON.Word = 0x00000000; -} - -/*************************END OF FILE**********************/ - - diff --git a/bsp/essemi/es8p508x/libraries/Library/Source/lib_aes.c b/bsp/essemi/es8p508x/libraries/Library/Source/lib_aes.c deleted file mode 100644 index e8f07e8bba..0000000000 --- a/bsp/essemi/es8p508x/libraries/Library/Source/lib_aes.c +++ /dev/null @@ -1,222 +0,0 @@ -/*************************************************************** - *Copyright (C), 2017, Shanghai Eastsoft Microelectronics Co., Ltd. - *ļ - * : AE - * : V1.00 - * : 2017/07/14 - * - * ע ES8P508оƬ - ѧϰʾʹãûֱôķջеκηΡ - ***************************************************************/ -#include "lib_aes.h" - -/*************************************************************** -AES_Init - AESܳʼ -ֵAES_InitStruct ʼṹ -ֵ -ֵ -***************************************************************/ -void AES_Init(AES_InitStruType * AES_InitStruct) -{ - - - AES_Reset(); - - AES->CON.ENCRYPT = AES_InitStruct->MODE; - return; -} - -/*************************************************************** -AES_WriteKey - AESдԿ -ֵAES_KEY дԿ -ֵ -ֵ -***************************************************************/ -void AES_WriteKey(uint32_t *AES_KEY) -{ - uint32_t *address = AES_KEY; - - AES->KEY3.AES_KEY3 = *address; - address ++; - AES->KEY2.AES_KEY2 = *address; - address ++; - AES->KEY1.AES_KEY1 = *address; - address ++; - AES->KEY0.AES_KEY0 = *address; -} - -/*************************************************************** -AES_ReadKey - AESԿ -ֵ -ֵAES_DATAԿλ -ֵ -***************************************************************/ -void AES_ReadKey(uint32_t * AES_KEY) -{ - uint32_t *address = AES_KEY; - - *address = AES->KEY3.AES_KEY3; - address ++; - *address = AES->KEY2.AES_KEY2; - address ++; - *address = AES->KEY1.AES_KEY1; - address ++; - *address = AES->KEY0.AES_KEY0; - return; -} - -/*************************************************************** -AES_WriteData - AESдݺ -ֵAES_DATA д -ֵ -ֵ -***************************************************************/ -void AES_WriteData(uint32_t *AES_DATA) -{ - uint32_t *address = AES_DATA; - - AES->DATA3.AES_DATA3 = *address; - address ++; - AES->DATA2.AES_DATA2 = *address; - address ++; - AES->DATA1.AES_DATA1 = *address; - address ++; - AES->DATA0.AES_DATA0 = *address; -} - -/*************************************************************** -AES_WriteData - AESݺ -ֵ -ֵAES_DATAݴλ -ֵ -***************************************************************/ -void AES_ReadData(uint32_t * AES_DATA) -{ - uint32_t *address = AES_DATA; - - *address = AES->DATA3.AES_DATA3; - address ++; - *address = AES->DATA2.AES_DATA2; - address ++; - *address = AES->DATA1.AES_DATA1; - address ++; - *address = AES->DATA0.AES_DATA0; - return; -} - -/*************************************************************** -AES_ITConfig - AESжʹ -ֵAES_IE - NewState Enable/Disable -ֵ -ֵ -***************************************************************/ -void AES_ITConfig(AES_TYPE_IT AES_IE, TYPE_FUNCEN NewState) -{ - uint32_t Word = AES->CON.Word&0xffffff8e; - - if(AES->CON.GO_DONE == 1) - { - return; - } - - if (NewState == ENABLE) - Word |= (uint32_t)AES_IE; - else - - Word &= ~(uint32_t)AES_IE; - - AES->CON.Word = Word; - return; - -} - -/*************************************************************** -AES_GetFlagStatus - AESضжϱ־ -ֵIFName - AES_IF_IF ӽж -ֵ -ֵжϱ־ -***************************************************************/ -FlagStatus AES_GetFlagStatus(AES_TYPE_IF IFName) -{ - - if(AES->CON.Word & IFName) { - return SET; - } - return RESET; -} - -/*************************************************************** -AES_ClearITPendingBit - AESضжϱ־ -ֵIFName - AES_IF_DONE ӽж -ֵ -ֵ -***************************************************************/ -void AES_ClearITPendingBit(void) -{ - /* ǵIFGO_DONEͬһwordУIFֵܻһЩ - * GO_DONE1ʱȡֵGO_DONE0ֵԭ1ٶиֵ - * òҪв - */ - - if(AES->CON.GO_DONE == SET) - { - return; - } - - AES->CON.IF = SET; - - return; -} - -/*************************************************************** -AES_GetDoneStatus - AESǷ/ -ֵ -ֵ -ֵAES_DONE_NO δ - AES_DONE_YES δܻ߼Ѿ -***************************************************************/ -AES_TYPE_DONE AES_GetDoneStatus(void) -{ - if(AES->CON.GO_DONE == 1) - { - return AES_DONE_NO; - } - - return AES_DONE_YES; -} - -/*************************************************************** -AES_Reset - AESλ -ֵ -ֵ -ֵ -***************************************************************/ -void AES_Reset(void) -{ - AES->DATA0.Word = 0x00000000; - AES->DATA1.Word = 0x00000000; - AES->DATA2.Word = 0x00000000; - AES->DATA3.Word = 0x00000000; - - AES->KEY0.Word = 0x00000000; - AES->KEY1.Word = 0x00000000; - AES->KEY2.Word = 0x00000000; - AES->KEY3.Word = 0x00000000; - - AES->CON.Word = 0x00000000; -} - - diff --git a/bsp/essemi/es8p508x/libraries/Library/Source/lib_crc.c b/bsp/essemi/es8p508x/libraries/Library/Source/lib_crc.c deleted file mode 100644 index 547d50fddf..0000000000 --- a/bsp/essemi/es8p508x/libraries/Library/Source/lib_crc.c +++ /dev/null @@ -1,96 +0,0 @@ -/*************************************************************** - *Copyright (C), 2017, Shanghai Eastsoft Microelectronics Co., Ltd. - *ļ - * : Liut - * : V1.00 - * : 2017/07/14 - * - * ע ES8P508xоƬ - ѧϰʾʹãûֱôķջеκηΡ - ***************************************************************/ -#include "lib_crc.h" - - /*************************************************************** - CRC_getTypeValue - òһCRC_CONò - ֵcon_value CRC_CON ֵṹ - ֵCRC_CONֵ - ***************************************************************/ -uint32_t CRC_getTypeValue(CRC_CONValueStruType con_value) -{ - uint32_t type =0; - type = (con_value.xorout | con_value.refout | con_value.refin |\ - con_value.mode|con_value.hs_type|con_value.init_data_type); - return type; -} - - /*************************************************************** - CRC_EmptayCheck - պ - ֵaddress: ׵ַ data_lenֽڳ - ֵ1ɹ0 ʧ - ***************************************************************/ -uint32_t CRC_EmptayCheck(void* address, uint32_t data_len) -{ - CRC_EM CRC_EmptayCheck = (CRC_EM)(*(uint32_t *)CRC_EmptayCheck_addr); - - uint32_t result; - __ASM("CPSID i"); - result = (*CRC_EmptayCheck)(address, data_len); - __ASM("CPSIE i"); - return result; -} - - /*************************************************************** - CRC_FlashVerify - FLASHУ麯 - ֵaddress: У׵ַ data_lenУֽڳȣ type:У鷽ʽ - ֵCRCУ - ***************************************************************/ -uint32_t CRC_FlashVerify(void* address, uint32_t data_len, uint32_t type) -{ - CRC_FL CRC_FlashVerify = (CRC_FL)(*(uint32_t *)CRC_FlashVerify_addr); - - uint32_t result; - __ASM("CPSID i"); - result = (*CRC_FlashVerify)(address, data_len, type); - __ASM("CPSIE i"); - return result; -} - - /*************************************************************** - CRC_UserCal - ûУ麯 - ֵaddress: ûУ׵ַ data_lenУֽڳȣ type:У鷽ʽ - ֵCRCУ - ***************************************************************/ -uint32_t CRC_UserCal(void* address, uint32_t data_len, uint32_t type) -{ - CRC_US CRC_UserCal = (CRC_US)(*(uint32_t *)CRC_UserCal_addr); - - uint32_t result; - __ASM("CPSID i"); - result = (*CRC_UserCal)(address, data_len, type); - __ASM("CPSIE i"); - return result; -} - - /*************************************************************** - CRC_CheckReset - CRCλѯ - ֵ - ֵλ־1иλ־0޸λ־ - ***************************************************************/ -uint32_t CRC_CheckReset(void) -{ - CRC_CH CRC_CheckReset = (CRC_CH)(*(uint32_t *)CRC_CheckReset_addr); - - uint32_t result; - __ASM("CPSID i"); - result = (*CRC_CheckReset)(); - __ASM("CPSIE i"); - return result; -} - -/************************END OF FILE**************************/ - diff --git a/bsp/essemi/es8p508x/libraries/Library/Source/lib_flashiap.c b/bsp/essemi/es8p508x/libraries/Library/Source/lib_flashiap.c deleted file mode 100644 index 599478b164..0000000000 --- a/bsp/essemi/es8p508x/libraries/Library/Source/lib_flashiap.c +++ /dev/null @@ -1,355 +0,0 @@ -/*************************************************************** - *Copyright (C), 2017, Shanghai Eastsoft Microelectronics Co., Ltd - *ļ lib_flashiap.c - * ߣ Liut - * V1.00 - * ڣ 2017/07/14 - * flashд⺯ - * ע ES8P508xоƬ - ѧϰʾʹãûֱôķջеκηΡ - ***************************************************************/ -#include "lib_flashiap.h" - -/*************************************************************** - FlashIap_Close_WPROT - IAPرд - ֵPage:0-63,ÿpageӦ2Kֽ,64 ΪINFO - ֵ - ֵɹʧ - ***************************************************************/ -ErrorStatus FlashIap_Close_WPROT(uint8_t Page) -{ - if(Page > 64) - return ERROR; - - if(Page == 64) - { - IAP->WPROT2.Word = 0x00000000; - return SUCCESS; - } - - if(Page < 32) - { - IAP->WPROT0.Word &=~ ((uint32_t)0x1 << Page); - } - else - { - Page -= 32; - IAP->WPROT1.Word &=~ ((uint32_t)0x1 << Page); - } - - return SUCCESS; -} - -/*************************************************************** - FlashIap_Open_WPROT - IAPд - ֵPage:0-63,ÿpageӦ2Kֽ,,64 ΪINFO - ֵ - ֵɹʧ - ***************************************************************/ -ErrorStatus FlashIap_Open_WPROT(uint8_t Page) -{ - if(Page > 64) - return ERROR; - - if(Page == 64) - { - IAP->WPROT2.Word = 0x00000001; - return SUCCESS; - } - - if(Page < 32) - { - IAP->WPROT0.Word &=~ ((uint32_t)0x1 << Page); - IAP->WPROT0.Word |= ((uint32_t)0x1 << Page); - } - else - { - Page -= 32; - IAP->WPROT1.Word &=~ ((uint32_t)0x1 << Page); - IAP->WPROT1.Word |= ((uint32_t)0x1 << Page); - } - - return SUCCESS; -} - -/*************************************************************** - FlashIap_CloseAll_WPROT - IAPرд - ֵPage:0-63,ÿpageӦ2Kֽ - ֵ - ֵɹʧ - ***************************************************************/ -ErrorStatus FlashIap_CloseAll_WPROT(void) -{ - IAP->WPROT0.Word = 0x00000000; - IAP->WPROT1.Word = 0x00000000; - IAP->WPROT2.Word = 0x00000000; - - return SUCCESS; -} -/*************************************************************** - FlashIap_OpenAll_WPROT - IAPд - ֵ - ֵ - ֵɹʧ - ***************************************************************/ -ErrorStatus FlashIap_OpenAll_WPROT(void) -{ - IAP->WPROT0.Word = 0xFFFFFFFF; - IAP->WPROT1.Word = 0xFFFFFFFF; - IAP->WPROT2.Word = 0xFFFFFFFF; - - return SUCCESS; -} - -/*************************************************************** - FlashIap_Unlock - IAP - ֵ - ֵ - ֵɹʧ - ***************************************************************/ -ErrorStatus FlashIap_Unlock(void) -{ - uint16_t Temp16; - - FlashIAP_RegUnLock(); // IAP - - FlashIAP_Enable(); //ʹIAP - - FlashIAP_REQ(); // - - for(Temp16 = 0; Temp16 < 0xFFFF; Temp16++) //ȴFLASHӦź - { - if(IAP->CON.FLASH_ACK != 0) - break; - } - - if(Temp16 == 0xFFFF) - return ERROR; - else - return SUCCESS; -} - -/*************************************************************** - FlashIap_WriteEnd - IAPд - ֵ - ֵ - ֵɹʧ - ***************************************************************/ -ErrorStatus FlashIap_WriteEnd(void) -{ - uint32_t Temp32; - - FlashIAP_RegUnLock(); //IAP - - IAP->CON.Word &= 0xFFFFFFEE; //IAPFLASH() - - for(Temp32 = 0; Temp32 < 0xFFFF; Temp32++) //ȴFLASHӦź() - { - if(IAP->CON.FLASH_ACK == 0) - break; - } - - if(Temp32 == 0xFFFF) - return ERROR; - else - return SUCCESS; -} - -/*************************************************************** - FlashIap_ErasePage - IAPҳ - ֵPage_Addrҳַ - ֵ - ֵɹʧ - ***************************************************************/ -ErrorStatus FlashIap_ErasePage(uint8_t Page_Addr) -{ - uint16_t Temp16; - uint32_t temp; - - temp = __get_PRIMASK(); //ȡPRIMASKĴǰ״̬ - __disable_irq(); //ж - - if(FlashIap_Unlock() == ERROR) - { - __set_PRIMASK(temp); //ָPRIMASKĴ״̬ - return ERROR; - } - - if(FlashIap_CloseAll_WPROT() == ERROR) - { - __set_PRIMASK(temp); - return ERROR; - } - - IAP->ADDR.IAPPA = Page_Addr; //ҳַ - - IAP->TRIG.TRIG = 0x00005EA1; // - - for(Temp16 = 0; Temp16 < 0xFFFF; Temp16++) - { //жIAP״̬ - if((IAP->STA.Word & (uint32_t)0x01) == (uint32_t)0x00) - break; - } - - if(Temp16 == 0xFFFF) - { - __set_PRIMASK(temp); //ָPRIMASKĴ״̬ - return ERROR; - } - - for(Temp16 = 0; Temp16 < 0xFFFF; Temp16++) - { - if((IAP->STA.Word & (uint32_t)0x02) == (uint32_t)0x02) //жIAPҳ־ - break; - } - - if(Temp16 == 0xFFFF) - { - __set_PRIMASK(temp); //ָPRIMASKĴ״̬ - return ERROR; - } - - if(FlashIap_WriteEnd() == ERROR) - { - __set_PRIMASK(temp); //ָPRIMASKĴ״̬ - return ERROR; - } - - if(FlashIap_OpenAll_WPROT() == ERROR) - { - __set_PRIMASK(temp); - return ERROR; - } - - __set_PRIMASK(temp); //ָPRIMASKĴ״̬ - - return SUCCESS; -} - -/*************************************************************** - FlashIap_WriteCont - IAPд - ֵUnit_addrԪַ Page_addrҳַ Data32 - ֵ - ֵɹʧ - ***************************************************************/ -ErrorStatus FlashIap_WriteCont(uint8_t Unit_addr, uint8_t Page_addr, uint32_t Data32) -{ - uint16_t temp16; - - IAP->ADDR.IAPPA = Page_addr; //ַ - IAP->ADDR.IAPCA = Unit_addr; - - IAP->DATA.DATA = Data32; // - IAP->TRIG.TRIG = 0x00005DA2; // - - for(temp16 = 0; temp16 < 0xFFFF; temp16++) - { - if((IAP->STA.Word & (uint32_t)0x01) == (uint32_t)0x00) //жIAP״̬ - break; - } - - if(temp16 == 0xFFFF) - return ERROR; - - for(temp16 = 0; temp16 < 0xFFFF; temp16++) - { - if((IAP->STA.Word & 0x04)==0x04) //жIAP̽־ - break; - } - - if(temp16 == 0xFFFF) - return ERROR; - - return SUCCESS; -} - -/*************************************************************** - FlashIap_WriteWord - IAPдһ - ֵUnit_addrԪַ Page_addrҳַ Data32 - ֵ - ֵɹʧ - ***************************************************************/ -ErrorStatus FlashIap_WriteWord(uint8_t Unit_addr, uint8_t Page_addr, uint32_t Data32) -{ - uint32_t temp; - - temp = __get_PRIMASK(); //ȡPRIMASKĴǰ״̬ - __disable_irq(); //ж - - if(FlashIap_Unlock() == ERROR) - { - __set_PRIMASK(temp); //ָPRIMASKĴ״̬ - return ERROR; - } - - if(FlashIap_CloseAll_WPROT() == ERROR) - { - __set_PRIMASK(temp); //رд״̬ - return ERROR; - } - - if(FlashIap_WriteCont(Unit_addr, Page_addr, Data32) == ERROR) - { - __set_PRIMASK(temp); //ָPRIMASKĴ״̬ - return ERROR; - } - - if(FlashIap_WriteEnd() == ERROR) - { - __set_PRIMASK(temp); //ָPRIMASKĴ״̬ - return ERROR; - } - - if(FlashIap_OpenAll_WPROT() == ERROR) - { - __set_PRIMASK(temp); //д״̬ - return ERROR; - } - - __set_PRIMASK(temp); //ָPRIMASKĴ״̬ - - return SUCCESS; -} - -/*************************************************************** - Flash_Read - Flash - ֵRam_AddrݵĴŵַ Flash_AddrFlashַ0x00000000 ~ 0x0001FFFF Lenȡֳ - ֵ - ֵɹʧ - ***************************************************************/ -ErrorStatus Flash_Read(uint32_t * Ram_Addr, uint32_t Flash_Addr, uint8_t Len) -{ - uint8_t i; - uint32_t *ram_addr32; - const uint32_t *flash_addr32; - - ram_addr32 = (uint32_t *)Ram_Addr; - flash_addr32 = (const uint32_t *)Flash_Addr; - - if((Len == 0) & (Len>(0x20000 - Flash_Addr) / 4)) //ж϶ȡǷϷ - { - return ERROR; - } - - for(i=0; iGPIO_Signal == GPIO_Pin_Signal_Analog) { - GPIO_SetSingalTypeFromPin(GPIOx, PINx, GPIO_Pin_Signal_Analog); - GPIO_SetDirRegFromPin(GPIOx, PINx, GPIO_Dir_In); - GPIO_SetFuncxRegFromPin(GPIOx, PINx, GPIO_Func_0); - } - else { - GPIO_SetSingalTypeFromPin(GPIOx, PINx, GPIO_Pin_Signal_Digital); - GPIO_SetDirRegFromPin(GPIOx, PINx, GPIO_InitStruct->GPIO_Direction); - GPIO_SetFuncxRegFromPin(GPIOx, PINx, GPIO_InitStruct->GPIO_Func); - - if (GPIO_InitStruct->GPIO_Direction == GPIO_Dir_Out) { - GPIO_SetODERegFromPin(GPIOx, PINx, GPIO_InitStruct->GPIO_OD); - GPIO_SetDSRegFromPin(GPIOx, PINx, GPIO_InitStruct->GPIO_DS); - } - GPIO_SetPUERegFromPin(GPIOx, PINx, GPIO_InitStruct->GPIO_PUEN); - GPIO_SetPDERegFromPin(GPIOx, PINx, GPIO_InitStruct->GPIO_PDEN); - } -} - -/*************************************************************** - GPIO_SetFuncxRegFromPin - GPIOŵĹܸ - ֵPinĿ - Funcܸñ - ֵ - ֵ - ***************************************************************/ -void GPIO_SetFuncxRegFromPin(GPIO_TYPE GPIOx,GPIO_TYPE_PIN PINx, GPIO_TYPE_FUNC Func) -{ - uint32_t value; - - switch (Func) { - case GPIO_Func_0: - value = 0; - break; - case GPIO_Func_1: - value = 1; - break; - case GPIO_Func_2: - value = 2; - break; - case GPIO_Func_3: - value = 3; - break; - default: - value = 0; - break; - } - - /* Ź */ - if(GPIOx == GPIOB){ - switch (PINx) { - case GPIO_Pin_0: - GPIO->PBFUNC0.PB0 = value; - break; - case GPIO_Pin_1: - GPIO->PBFUNC0.PB1 = value; - break; - case GPIO_Pin_2: - GPIO->PBFUNC0.PB2 = value; - break; - case GPIO_Pin_3: - GPIO->PBFUNC0.PB3 = value; - break; - case GPIO_Pin_4: - GPIO->PBFUNC0.PB4 = value; - break; - case GPIO_Pin_5: - GPIO->PBFUNC0.PB5 = value; - break; - case GPIO_Pin_6: - GPIO->PBFUNC0.PB6 = value; - break; - case GPIO_Pin_7: - GPIO->PBFUNC0.PB7 = value; - break; - case GPIO_Pin_8: - GPIO->PBFUNC1.PB8 = value; - break; - case GPIO_Pin_9: - GPIO->PBFUNC1.PB9 = value; - break; - case GPIO_Pin_10: - GPIO->PBFUNC1.PB10 = value; - break; - case GPIO_Pin_11: - GPIO->PBFUNC1.PB11 = value; - break; - case GPIO_Pin_12: - GPIO->PBFUNC1.PB12 = value; - break; - case GPIO_Pin_13: - GPIO->PBFUNC1.PB13 = value; - break; - default: - break; - } - } - - else{ - switch (PINx) { - case GPIO_Pin_0: - GPIO->PAFUNC0.PA0 = value; - break; - case GPIO_Pin_1: - GPIO->PAFUNC0.PA1 = value; - break; - case GPIO_Pin_2: - GPIO->PAFUNC0.PA2 = value; - break; - case GPIO_Pin_3: - GPIO->PAFUNC0.PA3 = value; - break; - case GPIO_Pin_4: - GPIO->PAFUNC0.PA4 = value; - break; - case GPIO_Pin_5: - GPIO->PAFUNC0.PA5 = value; - break; - case GPIO_Pin_6: - GPIO->PAFUNC0.PA6 = value; - break; - case GPIO_Pin_7: - GPIO->PAFUNC0.PA7 = value; - break; - case GPIO_Pin_8: - GPIO->PAFUNC1.PA8 = value; - break; - case GPIO_Pin_9: - GPIO->PAFUNC1.PA9 = value; - break; - case GPIO_Pin_10: - GPIO->PAFUNC1.PA10 = value; - break; - case GPIO_Pin_11: - GPIO->PAFUNC1.PA11 = value; - break; - case GPIO_Pin_12: - GPIO->PAFUNC1.PA12 = value; - break; - case GPIO_Pin_13: - GPIO->PAFUNC1.PA13 = value; - break; - case GPIO_Pin_14: - GPIO->PAFUNC1.PA14 = value; - break; - case GPIO_Pin_15: - GPIO->PAFUNC1.PA15 = value; - break; - case GPIO_Pin_16: - GPIO->PAFUNC2.PA16 = value; - break; - case GPIO_Pin_17: - GPIO->PAFUNC2.PA17 = value; - break; - case GPIO_Pin_18: - GPIO->PAFUNC2.PA18 = value; - break; - case GPIO_Pin_19: - GPIO->PAFUNC2.PA19 = value; - break; - case GPIO_Pin_20: - GPIO->PAFUNC2.PA20 = value; - break; - case GPIO_Pin_21: - GPIO->PAFUNC2.PA21 = value; - break; - case GPIO_Pin_22: - GPIO->PAFUNC2.PA22 = value; - break; - case GPIO_Pin_23: - GPIO->PAFUNC2.PA23 = value; - break; - case GPIO_Pin_24: - GPIO->PAFUNC3.PA24 = value; - break; - case GPIO_Pin_25: - GPIO->PAFUNC3.PA25 = value; - break; - case GPIO_Pin_26: - GPIO->PAFUNC3.PA26 = value; - break; - case GPIO_Pin_27: - GPIO->PAFUNC3.PA27 = value; - break; - case GPIO_Pin_28: - GPIO->PAFUNC3.PA28 = value; - break; - case GPIO_Pin_29: - GPIO->PAFUNC3.PA29 = value; - break; - case GPIO_Pin_30: - GPIO->PAFUNC3.PA30 = value; - break; - case GPIO_Pin_31: - GPIO->PAFUNC3.PA31 = value; - break; - default: - break; - } - } - return; -} - -/*************************************************************** - GPIO_SetSingalTypeFromPin - ŵź - ֵPin: Ŀ - Signal: ŵź - ֵ - ֵ - ***************************************************************/ -void GPIO_SetSingalTypeFromPin(GPIO_TYPE GPIOx,GPIO_TYPE_PIN PINx, GPIO_Pin_Signal GPIO_Signal) -{ - if(GPIOx == GPIOB) { - if (GPIO_Signal == GPIO_Pin_Signal_Digital) - GPIO->PBINEB.Word &= (~(1 << PINx)); - else - GPIO->PBINEB.Word |= (1 << PINx); - } - else{ - if (GPIO_Signal == GPIO_Pin_Signal_Digital) - GPIO->PAINEB.Word &= (~(1 << PINx)); - else - GPIO->PAINEB.Word |= (1 << PINx); - } - - return; -} - -/*************************************************************** - GPIO_SetDirRegFromPin - ŵ - ֵPin: Ŀ - Dirŷ - ֵ - ֵ - ***************************************************************/ -void GPIO_SetDirRegFromPin(GPIO_TYPE GPIOx,GPIO_TYPE_PIN PINx, GPIO_TYPE_DIR Dir) -{ - if (GPIOx == GPIOB) { - if (Dir == GPIO_Dir_In) - GPIO->PBDIRBSR.Word = (1 << PINx); - else - GPIO->PBDIRBCR.Word = (1 << PINx); - } - else { - if (Dir == GPIO_Dir_In) - GPIO->PADIRBSR.Word = (1 << PINx); - else - GPIO->PADIRBCR.Word = (1 << PINx); - } - - return; -} - -/*************************************************************** - GPIO_SetODERegFromPin - ŵ©ʽ - ֵPin: Ŀ -ODE: ©ʽ -ֵ -ֵ - ***************************************************************/ -void GPIO_SetODERegFromPin(GPIO_TYPE GPIOx,GPIO_TYPE_PIN PINx, GPIO_ODE_Output ODE) -{ - if (GPIOx == GPIOB) { - if (ODE == GPIO_ODE_Output_Disable) - GPIO->PBODE.Word &= (~(1 << PINx)); - else - GPIO->PBODE.Word |= (1 << PINx); - } - else { - if (ODE == GPIO_ODE_Output_Disable) - GPIO->PAODE.Word &= (~(1 << PINx)); - else - GPIO->PAODE.Word |= (1 << PINx); - } - - return; -} - -/*************************************************************** - GPIO_SetDSRegFromPin - ŵ - ֵPin: Ŀ -DS: ʽ -ֵ -ֵ - ***************************************************************/ -void GPIO_SetDSRegFromPin(GPIO_TYPE GPIOx,GPIO_TYPE_PIN PINx, GPIO_TYPE_DS DS) -{ - if (GPIOx == GPIOB) { - if (DS == GPIO_DS_Output_Normal) - GPIO->PBDS.Word &= (~(1 << PINx)); - else - GPIO->PBDS.Word |= (1 << PINx); - } - else { - if (DS == GPIO_DS_Output_Normal) - GPIO->PADS.Word &= (~(1 << PINx)); - else - GPIO->PADS.Word |= (1 << PINx); - } - - return; -} - -/*************************************************************** - GPIO_SetPUERegFromPin - ŵʽ - ֵPin: Ŀ -PUE: ʽ -ֵ -ֵ - ***************************************************************/ -void GPIO_SetPUERegFromPin(GPIO_TYPE GPIOx,GPIO_TYPE_PIN PINx, GPIO_PUE_Input PUE) -{ - if (GPIOx == GPIOB) { - if (PUE == GPIO_PUE_Input_Disable) - GPIO->PBPUE.Word &= (~(1 << PINx)); - else - GPIO->PBPUE.Word |= (1 << PINx); - } - else { - if (PUE == GPIO_PUE_Input_Disable) - GPIO->PAPUE.Word &= (~(1 << PINx)); - else - GPIO->PAPUE.Word |= (1 << PINx); - } -} - -/*************************************************************** - GPIO_SetPDERegFromPin - ŵʽ - ֵPin: Ŀ - PDEʽ - ֵ - ֵ - ***************************************************************/ -void GPIO_SetPDERegFromPin(GPIO_TYPE GPIOx,GPIO_TYPE_PIN PINx, GPIO_PDE_Input PDE) -{ - if (GPIOx == GPIOB) { - if (PDE == GPIO_PDE_Input_Disable) - GPIO->PBPDE.Word &= (~(1 << PINx)); - else - GPIO->PBPDE.Word |= (1 << PINx); - } - else { - if (PDE == GPIO_PDE_Input_Disable) - GPIO->PAPDE.Word &= (~(1 << PINx)); - else - GPIO->PAPDE.Word |= (1 << PINx); - } - - return; -} - -/*************************************************************** - GPIO_Write - GPIO˿д - ֵGPIOxGPIOA/GPIOB ValueҪдݡע⣺ЩڵţõֵӦλõ - ֵ - ֵ - ***************************************************************/ -void GPIO_Write(GPIO_TYPE GPIOx, uint32_t Value) -{ - if(GPIOx == GPIOA) - GPIO->PADATA.Word = Value; - else if(GPIOx == GPIOB) - GPIO->PBDATA.Word = Value; -} - -/*************************************************************** - GPIO_Read - GPIO˿ڶ - ֵGPIOxGPIOA/GPIOB - ֵ - ֵݡע⣺ЩڵţֵӦλЧ - ***************************************************************/ -uint32_t GPIO_Read(GPIO_TYPE GPIOx) -{ - if(GPIOx == GPIOA) - return GPIO->PAPORT.Word; - else if(GPIOx == GPIOB) - return GPIO->PBPORT.Word; - - return 0; -} - -/*************************************************************** - GPIO_ReadBit - GPIO˿ڶijλ - ֵGPIOxGPIOA/GPIOB PINx:GPIO_Pin_0 GPIO_Pin_31 - ֵ - ֵݡע⣺ЩڵţֵЧ - ***************************************************************/ -PinStatus GPIO_ReadBit(GPIO_TYPE GPIOx,GPIO_TYPE_PIN PINx) -{ - PinStatus bitstatus = RESET; - - if(GPIOx == GPIOA) - { - if((GPIO->PAPORT.Word&((uint32_t)0x1<PBPORT.Word&((uint32_t)0x1<PADATABSR.Word = (uint32_t)0x1<PADATABCR.Word = (uint32_t)0x1<PADATABRR.Word = (uint32_t)0x1<PBDATABSR.Word = (uint32_t)0x1<PBDATABCR.Word = (uint32_t)0x1<PBDATABRR.Word = (uint32_t)0x1<PADIR.Word &=~((uint32_t)0x1 << PINx); - GPIO->PADIR.Word |= ((uint32_t)Dir_Type <PBDIR.Word &=~((uint32_t)0x1 << PINx); - GPIO->PBDIR.Word |= ((uint32_t)Dir_Type <BUZC.BUZ_LOAD = (SystemCoreClock/(freq*2)) - 1; - GPIO->BUZC.BUZEN = buzz_en; -} -/*************************************************************** - PINT_Config - PINT - ֵPINTxѡPINT0 PINT7 SELxѡ TRIGxѡ - ֵ - ֵ - ***************************************************************/ -void PINT_Config(PINT_TYPE PINTx, PINT_TYPE_SEL SELx, PINT_TYPE_TRIG TRIGx) -{ - GPIO->PINTSEL.Word &= ~((uint32_t)0x07<<(PINTx*4)); - GPIO->PINTSEL.Word |=((uint32_t)SELx << (PINTx*4)); //selѡ - - GPIO->PINTCFG.Word &= ~((uint32_t)0x07<<(PINTx*4)); - GPIO->PINTCFG.Word |=((uint32_t)TRIGx << (PINTx*4)); //ʽѡ -} - -/*************************************************************** - PINT_GetIFStatus - PINTȡжϱ־ - ֵPINTxPINT0-PINT7 - ֵ - ֵSET/RESET - ***************************************************************/ -FlagStatus PINT_GetIFStatus(PINT_TYPE_IT PINT_Flag) -{ - FlagStatus bitstatus = RESET; - - if((GPIO->PINTIF.Word & (uint32_t)PINT_Flag) != (uint32_t)RESET) - bitstatus = SET; - else - bitstatus = RESET; - - return bitstatus; -} - -/*************************************************************** - PINT_GetITStatus - PINTȡжϱ־ - ֵPINTxPINT0-PINT7 - ֵ - ֵSET/RESET - ***************************************************************/ -FlagStatus PINT_GetITStatus(PINT_TYPE_IT PINT_Flag) -{ - FlagStatus bitstatus = RESET; - - if((GPIO->PINTIF.Word & (uint32_t)PINT_Flag) != (uint32_t)RESET) - bitstatus = SET; - else - bitstatus = RESET; - - return bitstatus; -} - -/*************************************************************** - PINT_ClearITPendingBit - PINTжϱ־ - ֵPINTж - ֵ - ֵ - ***************************************************************/ -void PINT_ClearITPendingBit(PINT_TYPE_IT PINT_Flag) -{ - GPIO->PINTIF.Word = (uint32_t)PINT_Flag; -} - -/*************************END OF FILE**********************/ - - - diff --git a/bsp/essemi/es8p508x/libraries/Library/Source/lib_iap.c b/bsp/essemi/es8p508x/libraries/Library/Source/lib_iap.c deleted file mode 100644 index 9cd1bb4daf..0000000000 --- a/bsp/essemi/es8p508x/libraries/Library/Source/lib_iap.c +++ /dev/null @@ -1,97 +0,0 @@ -/*************************************************************** - *Copyright (C), 2017, Shanghai Eastsoft Microelectronics Co., Ltd. - *ļ - * : Liut - * : V1.00 - * : 2017/07/14 - * - * ע ES8P508оƬ - ѧϰʾʹãûֱôķջеκηΡ - ***************************************************************/ -#include "lib_iap.h" - -/************************************************* - * @brief IAP ҳ.ص̻ROMеij - * @param address: ҳ׵ַ - * @retval None - ***********************************************/ -ErrorStatus IAP_PageErase(uint32_t address) -{ - IAP_PE IAPPageErase = (IAP_PE)(*(uint32_t *)IAP_PageErase_addr); - - ErrorStatus result; - __ASM("CPSID i"); - result = (*IAPPageErase)(address); - __ASM("CPSIE i"); - return result; -} - -/************************************************* - * @brief IAP Ա.ص̻ROMеij - * @param address: ׵ַ - * @param data: - * @retval None - ************************************************/ -ErrorStatus IAP_WordProgram(uint32_t address, uint32_t data) -{ - IAP_WP IAPWordProgram = (IAP_WP)(*(uint32_t *)IAP_WordProgram_addr); - - ErrorStatus result; - __ASM("CPSID i"); - result = (*IAPWordProgram)( address, data); - __ASM("CPSIE i"); - return result; -} - -/************************************************ - * @brief IAP Ա.ص̻ROMеij - * @param address: ׵ַ - * @param data[]: - * @param length: ݳȣֽڣ - * @param address: ҳǷȲ - * @arg 0: - * @arg 1: - * @retval None - **********************************************/ -ErrorStatus IAP_PageProgram(uint32_t address, uint32_t data[], uint32_t length, uint32_t erase) //@0x100001c5 -{ - IAP_PP IAPPageProgram = (IAP_PP)(*(uint32_t *)IAP_PageProgram_addr); - - ErrorStatus result; - __ASM("CPSID i"); - result = (*IAPPageProgram)(address,data,length,erase); - __ASM("CPSIE i"); - return result; -} -/************************************* - IARead - Flash - ֵڴַ--ȡݵĴŵַ - Flashַ - ȡݵijȣλΪ֣4ֽڣ - ֵɹ/ʧ - **************************************/ -ErrorStatus IAPRead(uint32_t *Ram_Addr, uint32_t Flash_Addr, uint8_t Len) -{ - uint8_t i; - uint32_t *ram_addr; - const uint32_t *flash_addr; - - ram_addr = Ram_Addr; - flash_addr = (const uint32_t *)Flash_Addr; - - if (Len == 0) - return ERROR; - - for (i = 0; i < Len; ++i) - { - *ram_addr = *flash_addr; - ++ram_addr; - ++flash_addr; - } - - return SUCCESS; -} - -/************************END OF FILE**************************/ - diff --git a/bsp/essemi/es8p508x/libraries/Library/Source/lib_iic.c b/bsp/essemi/es8p508x/libraries/Library/Source/lib_iic.c deleted file mode 100644 index ab987843f1..0000000000 --- a/bsp/essemi/es8p508x/libraries/Library/Source/lib_iic.c +++ /dev/null @@ -1,311 +0,0 @@ -/*************************************************************** - *Copyright (C), 2017, Shanghai Eastsoft Microelectronics Co., Ltd - *ļ lib_iic.c - * ߣ Liut - * V1.00 - * ڣ 2017/07/14 - * IICģ⺯ - * ע ES8P508xоƬ - ѧϰʾʹãûֱôķջеκηΡ - ***************************************************************/ -#include "lib_iic.h" - -/*************************************************************** - I2C_Init - I2Cʼ - ֵI2C_InitStructʼýṹַ - ֵ - ֵ - ***************************************************************/ -void I2C_Init(I2C_InitStruType* I2C_InitStruct) -{ - uint32_t temp; - - if(I2C_InitStruct->I2C_Mode == I2C_Mode_Master) - { - if(I2C_InitStruct->I2C_16XSamp != DISABLE) - temp = SystemCoreClock/24/I2C_InitStruct->I2C_Clk - 1; - else - temp = SystemCoreClock/16/I2C_InitStruct->I2C_Clk - 1; - - if(temp > 254) - temp = 255; - - I2C0->CON.TJP = temp; //ʱʱ - - I2C0->CON.TJE = 0x1; //ʹʱʱ - } - - I2C0->CON.SDASE = I2C_InitStruct->I2C_16XSamp; //16 - I2C0->CON.SCKSE = I2C_InitStruct->I2C_16XSamp; - I2C0->CON.SCKOD = I2C_InitStruct->I2C_SclOd; //˿ڿ© - I2C0->CON.SDAOD = I2C_InitStruct->I2C_SdaOd; - I2C0->MOD.MS = I2C_InitStruct->I2C_Mode; //ģʽ - I2C0->MOD.SPAE = I2C_InitStruct->I2C_AutoStop; //Զֹͣ - I2C0->MOD.SRAE = I2C_InitStruct->I2C_AutoCall; //ԶѰ -} - -/*************************************************************** - I2C_ITConfig - I2Cж - ֵI2C_ITҪõж NewStateʹܻر - ֵ - ֵ - ***************************************************************/ -void I2C_ITConfig(I2C_TYPE_IT I2C_IT,TYPE_FUNCEN NewState) -{ - if (NewState != DISABLE) - I2C0->IE.Word |= (uint32_t)I2C_IT; - else - I2C0->IE.Word &= ~((uint32_t)I2C_IT); -} - -/*************************************************************** - I2C_SendAddress - I2Cʹӻַ - ֵI2C_Address7λӻַ 0x00~0xfe Modeд - ֵ - ֵ - ***************************************************************/ -void I2C_SendAddress(uint8_t I2C_Address,I2C_TYPE_RWMODE Mode) -{ - I2C0->CON.SA = I2C_Address>>1; - I2C0->CON.RW = Mode; -} - -/*************************************************************** - I2C_SetAddress - I2Cõַڴӻģʽ - ֵI2C_Address7λӻַ 0x00~0xfe - ֵ - ֵ - ***************************************************************/ -void I2C_SetAddress(uint8_t I2C_Address) -{ - I2C0->CON.SA = I2C_Address>>1; -} - -/*************************************************************** - I2C_RecModeConfig - I2Cýģʽ - ֵRecTypeģʽ - ֵ - ֵ - ***************************************************************/ -void I2C_RecModeConfig(I2C_TYPE_RECMODE RecType) -{ - I2C0->MOD.RDM = RecType; -} - -/*************************************************************** - I2C_TBIMConfig - I2Cͻжģʽѡ - ֵTypeжģʽ - ֵ - ֵ - ***************************************************************/ -void I2C_TBIMConfig(I2C_TYPE_TRBIM Type) -{ - I2C0->IE.TBIM = Type; -} - -/*************************************************************** - I2C_RBIMConfig - I2Cջжģʽѡ - ֵTypeжģʽ - ֵ - ֵ - ***************************************************************/ -void I2C_RBIMConfig(I2C_TYPE_TRBIM Type) -{ - I2C0->IE.RBIM = Type; -} - -/*************************************************************** - I2C_AckDelay - I2CӦʱ - ֵTypeʱʱ NewStatusʹܡʧ - ֵ - ֵ - ***************************************************************/ -void I2C_AckDelay(I2C_TYPE_ADLY Type,TYPE_FUNCEN NewStatus) -{ - I2C0->MOD.ADLY = Type; - I2C0->MOD.ADE = NewStatus; -} - -/*************************************************************** - I2C_TISConfig - I2C֡ - ֵTime - ֵ - ֵ - ***************************************************************/ -void I2C_TISConfig(I2C_TYPE_TIS Time) -{ - I2C0->MOD.TIS = Time; -} - -/*************************************************************** - I2C_SendByte - I2Cֽڷ - ֵByteֽ - ֵ - ֵ - ***************************************************************/ -void I2C_SendByte(uint8_t Byte) -{ - I2C0->TBW.Byte[0] = Byte; -} - -/*************************************************************** - I2C_SendHalfWord - I2Cַ - ֵHalfWord - ֵ - ֵ - ***************************************************************/ -void I2C_SendHalfWord(uint16_t HalfWord) -{ - I2C0->TBW.HalfWord[0] = HalfWord; -} - -/*************************************************************** - I2C_SendWord - I2Cַ - ֵWord - ֵ - ֵ - ***************************************************************/ -void I2C_SendWord(uint32_t Word) -{ - I2C0->TBW.Word = Word; -} - -/*************************************************************** - I2C_RecByte - I2C-ֽ - ֵ - ֵ - ֵյ - ***************************************************************/ -uint8_t I2C_RecByte(void) -{ - return I2C0->RBR.Byte[0] ; -} - -/*************************************************************** - I2C_RecHalfWord - I2C- - ֵ - ֵ - ֵյ - ***************************************************************/ -uint16_t I2C_RecHalfWord(void) -{ - return I2C0->RBR.HalfWord[0]; -} - -/*************************************************************** - I2C_RecWord - I2C- - ֵ - ֵ - ֵյ - ***************************************************************/ -uint32_t I2C_RecWord(void) -{ - return I2C0->RBR.Word ; -} - -/*************************************************************** - I2C_GetRWMode - I2Cд״̬ȡ - ֵ - ֵ - ֵ/д - ***************************************************************/ -I2C_TYPE_RWMODE I2C_GetRWMode(void) -{ - I2C_TYPE_RWMODE Status = I2C_Mode_Write; - - if(I2C0->CON.RW != 0) - Status = I2C_Mode_Read; - else - Status = I2C_Mode_Write; - - return Status; -} - -/*************************************************************** - I2C_GetTBStatus - I2CȡͻĴ״̬,TB0-TB3ȫ򷵻SET,򷵻RESET - ֵ - ֵ - ֵSET/RESET - ***************************************************************/ -FlagStatus I2C_GetTBStatus(void) -{ - FlagStatus bitstatus = RESET; - - if((I2C0->STA.Word&(uint32_t)0x0f00) != (uint32_t)0x0f00) - bitstatus = RESET; - else - bitstatus = SET; - - return bitstatus; -} - -/*************************************************************** - I2C_GetFlagStatus - I2Cȡ־λ״̬ - ֵI2C_FlagѡҪı־λ - ֵ - ֵSET/RESET - ***************************************************************/ -FlagStatus I2C_GetFlagStatus(I2C_TYPE_FLAG I2C_Flag) -{ - FlagStatus bitstatus = RESET; - - if ((I2C0->IF.Word & (uint32_t)I2C_Flag) != RESET) - bitstatus = SET; - else - bitstatus = RESET; - - return bitstatus; -} - -/************************************* - I2C_GetITStatus - ȡжʹ״̬ - ֵI2C_Flag жʹλ - ж - ֵSET/RESET - **************************************/ -FlagStatus I2C_GetITStatus( I2C_TYPE_IT I2C_Flag) -{ - FlagStatus status = RESET; - - if ((I2C0->IE.Word & (uint32_t)I2C_Flag) == RESET) - return status; - - if ((I2C0->IF.Word & (uint32_t)I2C_Flag) != RESET) - status = SET; - - return status; -} - -/*************************************************************** - I2C_ClearITPendingBit - I2Cжϱ־ - ֵI2C_IT־λ - ֵ - ֵ - ***************************************************************/ -void I2C_ClearITPendingBit(I2C_CLR_IF I2C_IT) -{ - I2C0->IF.Word = (uint32_t)I2C_IT; -} - -/*************************END OF FILE**********************/ - diff --git a/bsp/essemi/es8p508x/libraries/Library/Source/lib_printf.c b/bsp/essemi/es8p508x/libraries/Library/Source/lib_printf.c deleted file mode 100644 index f2afdc3142..0000000000 --- a/bsp/essemi/es8p508x/libraries/Library/Source/lib_printf.c +++ /dev/null @@ -1,283 +0,0 @@ -/*************************************************************** - *Copyright (C), 2017, Shanghai Eastsoft Microelectronics Co., Ltd - *ļ lib_printf.c - * ߣ Liut - * V1.00 - * ڣ 2017/07/14 - * ڴӡ⺯ - * ע ES8P508xоƬ - ѧϰʾʹãûֱôķջеκηΡ - ***************************************************************/ -#include "lib_printf.h" -#include - -/*************************************************************** - fputc - ضc⺯printfUART - ֵ - ֵ - ֵ - ***************************************************************/ -/*ʹprintf()Ҫ΢⣺Use MicroLIB*/ -int fputc(int ch, FILE *f) -{ - FlagStatus Status = RESET; - uint32_t Count=0; - -#if defined __PRINTF_USE_UART3__ - UART_SendByte(UART3, (unsigned char) ch); - do - { - Status = UART_GetFlagStatus(UART3,UART_FLAG_TXIDLE); - Count++; - }while((Status == RESET)&&(Count != 0x1CE2)); - - if(Count == 0x1CE2) - return (EOF); - -#elif defined __PRINTF_USE_UART2__ - UART_SendByte(UART2, (unsigned char) ch); - do - { - Status = UART_GetFlagStatus(UART2,UART_FLAG_TXIDLE); - Count++; - }while((Status == RESET)&&(Count != 0x1CE2)); - - if(Count == 0x1CE2) - return (EOF); - -#elif defined __PRINTF_USE_UART1__ - UART_SendByte(UART1, (unsigned char) ch); - do - { - Status = UART_GetFlagStatus(UART1,UART_FLAG_TXIDLE); - Count++; - }while((Status == RESET)&&(Count != 0x1CE2)); - - if(Count == 0x1CE2) - return (EOF); - -#else - UART_SendByte(UART0, (unsigned char) ch); - do - { - Status = UART_GetFlagStatus(UART0,UART_FLAG_TXIDLE); - Count++; - }while((Status == RESET)&&(Count != 0x1CE2)); - - if(Count == 0x1CE2) - return (EOF); - -#endif - return (ch); -} - -#ifdef __clang__ //ʹõidesignerʱ򲻵΢ -/*************************************************************** - תַ - ֵ -radix =10 ʾ10ƣΪ0 - * -value Ҫת - * -buf תַ - * -radix = 10 - ֵ - ***************************************************************/ -static char *itoa(int value, char *string, int radix) -{ - int i, d; - int flag = 0; - char *ptr = string; - - /* This implementation only works for decimal numbers. */ - if (radix != 10) - { - *ptr = 0; - return string; - } - - if (!value) - { - *ptr++ = 0x30; - *ptr = 0; - return string; - } - - /* if this is a negative value insert the minus sign. */ - if (value < 0) - { - *ptr++ = '-'; - - /* Make the value positive. */ - value *= -1; - } - - for (i = 10000; i > 0; i /= 10) - { - d = value / i; - - if (d || flag) - { - *ptr++ = (char)(d + 0x30); - value -= (d * i); - flag = 1; - } - } - - /* Null terminate the string. */ - *ptr = 0; - - return string; -} -/*************************************************************** - ʽCеprintfûõC - ֵ -UARTx ͨ - * -Data Ҫ͵ڵݵָ - * -... - ֵ - Ӧã UART_printf("\r\n this is a demo \r\n" ); - * UART1_printf("\r\n %d \r\n", i ); - * UART1_printf("\r\n %s \r\n", j ); - ***************************************************************/ -/* δCʱʹô˺Cеprintfprintfȫ - ֻ֧\r \n %d %s */ -ErrorStatus UART_printf(uint8_t *Data,...) -{ - UART_TypeDef *UARTx; - const char *s; - int d; - char buf[16]; - ErrorStatus RET = SUCCESS; - FlagStatus Status = RESET; - uint32_t Count=0; - va_list ap; - -/** - ** - **ʹú궨ѡʹһ - ** -***/ -#if defined __PRINTF_USE_UART3__ - - UARTx = UART3; - -#elif defined __PRINTF_USE_UART2__ - - UARTx = UART2; - -#elif defined __PRINTF_USE_UART1__ - - UARTx = UART1; - -#else - - UARTx = UART0; - -#endif - - va_start(ap, Data); - - while ( *Data != 0) // жǷ񵽴ַ - { - if ( *Data == 0x5c ) //'\' - { - switch ( *++Data ) - { - case 'r': //س - Count=0; - UART_SendByte(UARTx, 0x0d); - do - { - Status = UART_GetFlagStatus(UARTx,UART_FLAG_TXIDLE); - Count++; - }while((Status == RESET)&&(Count != 0x1CE2)); - - if(Count == 0x1CE2) - RET = ERROR; - - Data ++; - break; - - case 'n': //з - Count=0; - UART_SendByte(UARTx, 0x0a); - do - { - Status = UART_GetFlagStatus(UARTx,UART_FLAG_TXIDLE); - Count++; - }while((Status == RESET)&&(Count != 0x1CE2)); - - if(Count == 0x1CE2) - RET = ERROR; - - Data ++; - break; - - default: - Data ++; - break; - } - } - else if ( *Data == '%') - { - switch ( *++Data ) - { - case 's': //ַ - s = va_arg(ap, const char *); - for ( ; *s; s++) - { - Count=0; - UART_SendByte(UARTx,*s); - do - { - Status = UART_GetFlagStatus(UARTx,UART_FLAG_TXIDLE); - Count++; - }while((Status == RESET)&&(Count != 0x1CE2)); - - if(Count == 0x1CE2) - RET = ERROR; - } - Data++; - break; - - case 'd': //ʮ - d = va_arg(ap, int); - itoa(d, buf, 10); - for (s = buf; *s; s++) - { - Count=0; - UART_SendByte(UARTx,*s); - do - { - Status = UART_GetFlagStatus(UARTx,UART_FLAG_TXIDLE); - Count++; - }while((Status == RESET)&&(Count != 0x1CE2)); - - if(Count == 0x1CE2) - RET = ERROR; - } - Data++; - break; - default: - Data++; - break; - } - } /* end of else if */ - else - { - Count=0; - UART_SendByte(UARTx, *Data++); - do - { - Status = UART_GetFlagStatus(UARTx,UART_FLAG_TXIDLE); - Count++; - }while((Status == RESET)&&(Count != 0x1CE2)); - - if(Count == 0x1CE2) - RET = ERROR; - } - } - return RET; -} - -#endif -/*************************END OF FILE**********************/ - diff --git a/bsp/essemi/es8p508x/libraries/Library/Source/lib_rtc.c b/bsp/essemi/es8p508x/libraries/Library/Source/lib_rtc.c deleted file mode 100644 index dfede6ca29..0000000000 --- a/bsp/essemi/es8p508x/libraries/Library/Source/lib_rtc.c +++ /dev/null @@ -1,1906 +0,0 @@ -/********************************************************* - *Copyright (C), 2017, Shanghai Eastsoft Microelectronics Co., Ltd. - *ļ: lib_rtc.c - * : Liut - * : V1.00 - * : 2017/07/14 - * : RTCģ - * ע: HRSDK-GDB-ES8P508 V1.1 - ѧϰʾʹãûֱôķջеκηΡ - **********************************************************/ -#include "lib_rtc.h" -#include "lib_scu.h" - -/*************************************************************** - RTC_Init - ʵʱʱӳʼ - ֵCLKx:RTCʱԴѡHOURx12Сʱ/24Сʱѡ - ֵ - ֵ - ***************************************************************/ -void RTC_Init(RTC_TYPE_CLKS CLKx,RTC_TYPE_TIME HOURx) -{ - uint32_t flag; - - if(CLKx == RTC_LOSC ) - { - uint32_t Prot_Temp; - - Prot_Temp = SCU->PROT.PROT; - - if(Prot_Temp != 0) //д - SCU_RegUnLock(); // - - SCU_XTAL_Enable(); //ʹⲿ32kHZ - while(SCU_XTALReadyFlag() != SET); //ȴʱӿ - - if(Prot_Temp != 0) - SCU_RegLock(); //д - } - - /* RTCд */ - flag = RTC->WP.WP; - if (flag == 0x00000000) - RTC->WP.WP = 0x55AAAA55; - RTC->CON.PON = 0; // 㣬ʹRTC - RTC->CON.HSWI = HOURx; // 24Сʱģʽ - RTC->CON.CLKS = CLKx; // ʱԴѡ32768Hz - - /* RTCд */ - if (flag == 0x00000000) - RTC->WP.WP = 0x00000000; -} -/*************************************************************** - RTC_StartRead - ʵʱʱӶ - ֵ - ֵ - ֵ - ***************************************************************/ -void RTC_StartRead(void) -{ - RTC->CON.TMWR = 0; // Ƕ - RTC->CON.TMUP = 1; // - while (RTC->CON.TMUP == 1); //ȴ -} - -/*************************************************************** - RTC_ReadHourmode - ȡСʱģʽ - ֵ - ֵ - ֵǰСʱģʽ - ***************************************************************/ -uint32_t RTC_ReadHourmode(void) -{ - uint32_t flag; - uint32_t result; - - /* RTCд */ - flag = RTC->WP.WP; - if (flag == 0x00000000) - RTC->WP.WP = 0x55AAAA55; - - /* */ - RTC_StartRead(); - - result = RTC->CON.HSWI; - - /* RTCд */ - if (flag == 0x00000000) - RTC->WP.WP = 0x00000000; - - return result; -} -/*************************************************************** - RTC_ReadSecond - ȡ - ֵ - ֵ - ֵǰ - ***************************************************************/ -uint32_t RTC_ReadSecond(void) -{ - uint32_t flag; - uint32_t result; - - /* RTCд */ - flag = RTC->WP.WP; - if (flag == 0x00000000) - RTC->WP.WP = 0x55AAAA55; - - /* */ - RTC_StartRead(); - - /* ʱ */ - result = ((RTC->HMS.SEC & (uint32_t)0x01) * 1); - result += (((RTC->HMS.SEC >> 1) & (uint32_t)0x01) * 2); - result += (((RTC->HMS.SEC >> 2) & (uint32_t)0x01) * 4); - result += (((RTC->HMS.SEC >> 3) & (uint32_t)0x01) * 8); - result += (((RTC->HMS.SEC >> 4) & (uint32_t)0x01) * 10); - result += (((RTC->HMS.SEC >> 5) & (uint32_t)0x01) * 20); - result += (((RTC->HMS.SEC >> 6) & (uint32_t)0x01) * 40); - - /* RTCд */ - if (flag == 0x00000000) - RTC->WP.WP = 0x00000000; - - return result; -} - -/*************************************************************** - RTC_ReadMinute - ȡ - ֵ - ֵ - ֵǰķ - ***************************************************************/ -uint32_t RTC_ReadMinute(void) -{ - uint32_t flag; - uint32_t result; - - /* RTCд */ - flag = RTC->WP.WP; - if (flag == 0x00000000) - RTC->WP.WP = 0x55AAAA55; - - /* */ - RTC_StartRead(); - - /* ʱ */ - result = ((RTC->HMS.MIN & (uint32_t)0x01) * 1); - result += (((RTC->HMS.MIN >> 1) & (uint32_t)0x01) * 2); - result += (((RTC->HMS.MIN >> 2) & (uint32_t)0x01) * 4); - result += (((RTC->HMS.MIN >> 3) & (uint32_t)0x01) * 8); - result += (((RTC->HMS.MIN >> 4) & (uint32_t)0x01) * 10); - result += (((RTC->HMS.MIN >> 5) & (uint32_t)0x01) * 20); - result += (((RTC->HMS.MIN >> 6) & (uint32_t)0x01) * 40); - - /* RTCд */ - if (flag == 0x00000000) - RTC->WP.WP = 0x00000000; - - return result; -} - -/*************************************************************** - RTC_ReadHour - ȡСʱ - ֵ - ֵ - ֵǰСʱ - ***************************************************************/ -uint32_t RTC_ReadHour(uint32_t *meridiem) -{ - uint32_t flag; - uint32_t result; - - /* RTCд */ - flag = RTC->WP.WP; - if (flag == 0x00000000) - RTC->WP.WP = 0x55AAAA55; - - /* */ - RTC_StartRead(); - - /* ʱ */ - result = ((RTC->HMS.HOUR & (uint32_t)0x01) * 1); - result += (((RTC->HMS.HOUR >> 1) & (uint32_t)0x01) * 2); - result += (((RTC->HMS.HOUR >> 2) & (uint32_t)0x01) * 4); - result += (((RTC->HMS.HOUR >> 3) & (uint32_t)0x01) * 8); - result += (((RTC->HMS.HOUR >> 4) & (uint32_t)0x01) * 10); - - if(RTC_ReadHourmode() == RTC_HOUR24) //24Сʱģʽ20Сʱ - { - result += (((RTC->HMS.HOUR >> 5) & (uint32_t)0x01) * 20); - } - else //12Сʱģʽ1 PM,0 AM - { - *meridiem = (((RTC->HMS.HOUR >> 5) & (uint32_t)0x01)); - } - - /* RTCд */ - if (flag == 0x00000000) - RTC->WP.WP = 0x00000000; - - return result; -} - -/*************************************************************** - RTC_ReadDay - ȡ - ֵ - ֵ - ֵǰ - ***************************************************************/ -uint32_t RTC_ReadDay(void) -{ - uint32_t flag; - uint32_t result; - - /* RTCд */ - flag = RTC->WP.WP; - if (flag == 0x00000000) - RTC->WP.WP = 0x55AAAA55; - /* */ - RTC_StartRead(); - - /* ʱ */ - result = ((RTC->YMDW.DAY & (uint32_t)0x01) * 1); - result += (((RTC->YMDW.DAY >> 1) & (uint32_t)0x01) * 2); - result += (((RTC->YMDW.DAY >> 2) & (uint32_t)0x01) * 4); - result += (((RTC->YMDW.DAY >> 3) & (uint32_t)0x01) * 8); - result += (((RTC->YMDW.DAY >> 4) & (uint32_t)0x01) * 10); - result += (((RTC->YMDW.DAY >> 5) & (uint32_t)0x01) * 20); - - /* RTCд */ - /* RTCд */ - if (flag == 0x00000000) - RTC->WP.WP = 0x00000000; - return result; -} - -/*************************************************************** - RTC_ReadMonth - ȡ - ֵ - ֵ - ֵǰ - ***************************************************************/ -uint32_t RTC_ReadMonth(void) -{ - uint32_t flag; - uint32_t result; - - /* RTCд */ - flag = RTC->WP.WP; - if (flag == 0x00000000) - RTC->WP.WP = 0x55AAAA55; - - /* */ - RTC_StartRead(); - - /* ʱ */ - result = ((RTC->YMDW.MON & (uint32_t)0x01) * 1); - result += (((RTC->YMDW.MON >> 1) & (uint32_t)0x01) * 2); - result += (((RTC->YMDW.MON >> 2) & (uint32_t)0x01) * 4); - result += (((RTC->YMDW.MON >> 3) & (uint32_t)0x01) * 8); - result += (((RTC->YMDW.MON >> 4) & (uint32_t)0x01) * 10); - - /* RTCд */ - if (flag == 0x00000000) - RTC->WP.WP = 0x00000000; - - return result; -} - -/*************************************************************** - RTC_ReadYear - ȡ - ֵ - ֵ - ֵǰ - ***************************************************************/ -uint32_t RTC_ReadYear(void) -{ - uint32_t flag; - uint32_t result; - - /* RTCд */ - flag = RTC->WP.WP; - if (flag == 0x00000000) - RTC->WP.WP = 0x55AAAA55; - - /* */ - RTC_StartRead(); - - /* ʱ */ - result = ((RTC->YMDW.YEAR & (uint32_t)0x01) * 1); - result += (((RTC->YMDW.YEAR >> 1) & (uint32_t)0x01) * 2); - result += (((RTC->YMDW.YEAR >> 2) & (uint32_t)0x01) * 4); - result += (((RTC->YMDW.YEAR >> 3) & (uint32_t)0x01) * 8); - result += (((RTC->YMDW.YEAR >> 4) & (uint32_t)0x01) * 10); - result += (((RTC->YMDW.YEAR >> 5) & (uint32_t)0x01) * 20); - result += (((RTC->YMDW.YEAR >> 6) & (uint32_t)0x01) * 40); - result += (((RTC->YMDW.YEAR >> 7) & (uint32_t)0x01) * 80); - result += 2000; - - /* RTCд */ - if (flag == 0x00000000) - RTC->WP.WP = 0x00000000; - - return result; -} -/*************************************************************** - RTC_ReadWeek - ȡ - ֵ - ֵ - ֵǰ - ***************************************************************/ -uint32_t RTC_ReadWeek(void) -{ - uint32_t flag; - uint32_t result; - - /* RTCд */ - flag = RTC->WP.WP; - if (flag == 0x00000000) - RTC->WP.WP = 0x55AAAA55; - - /* */ - RTC_StartRead(); - - /* ʱ */ - switch(RTC->YMDW.WEEK) - { - case 0x00: result = 0;break; - case 0x01: result = 1;break; - case 0x02: result = 2;break; - case 0x03: result = 3;break; - case 0x04: result = 4;break; - case 0x05: result = 5;break; - case 0x06: result = 6;break; - default: result = 0;break; - } - - /* RTCд */ - if (flag == 0x00000000) - RTC->WP.WP = 0x00000000; - - return result; -} - -/*************************************************************** - RTC_StartRead - ʵʱʱд - ֵ - ֵ - ֵ - ***************************************************************/ -void RTC_StartWrite(void) -{ - /* д */ - RTC->CON.TMWR = 1; // д - RTC->CON.TMUP = 1; // д - while (RTC->CON.TMUP == 1); //ȴд -} - -/*************************************************************** - RTC_WriteSecond - ޸ - ֵsecond: - ֵ - ֵ - ***************************************************************/ -ErrorStatus RTC_WriteSecond(uint32_t second) -{ - uint32_t flag = 0; - uint32_t sec_buf = 0; - - /* */ - if (second >= 60) - return ERROR; - - /* RTCд */ - flag = RTC->WP.WP; - if (flag == 0x00000000) - RTC->WP.WP = 0x55AAAA55; - - /* µֵ */ - if (second >= 40) - { - sec_buf |= (uint32_t)1<<6; - second -= 40; - } - else - { - sec_buf &= ~(uint32_t)1<<6; - } - - if (second >= 20) - { - sec_buf |= (uint32_t)1<<5; - second -= 20; - } - else - { - sec_buf &= ~(uint32_t)1<<5; - } - - if (second >= 10) - { - sec_buf |= (uint32_t)1<<4; - second -= 10; - } - else - { - sec_buf &= ~(uint32_t)1<<4; - } - - if (second >= 8) - { - sec_buf |= (uint32_t)1<<3; - second -= 8; - } - else - { - sec_buf &= ~(uint32_t)1<<3; - } - - if (second >= 4) - { - sec_buf |= (uint32_t)1<<2; - second -= 4; - } - else - { - sec_buf &= ~(uint32_t)1<<2; - } - - if (second >= 2) - { - sec_buf |= (uint32_t)1<<1; - second -= 2; - } - else - { - sec_buf &= ~(uint32_t)1<<1; - } - - if (second >= 1) - { - sec_buf |= (uint32_t)1; - second -= 1; - } - else - { - sec_buf &= ~(uint32_t)1; - } - - RTC->HMS.SEC = sec_buf; - - /* д */ - RTC_StartWrite(); - - /* RTCд */ - if (flag == 0x00000000) - RTC->WP.WP = 0x00000000; - return SUCCESS; -} - -/*************************************************************** - RTC_WriteMinute - ޸ - ֵminute: - ֵ - ֵ - ***************************************************************/ -ErrorStatus RTC_WriteMinute(uint32_t minute) -{ - uint32_t flag; - uint32_t min_buf = 0; - - /* */ - if (minute >= 60) - return ERROR; - - /* RTCд */ - flag = RTC->WP.WP; - if (flag == 0x00000000) - RTC->WP.WP = 0x55AAAA55; - - /* µֵ */ - if (minute >= 40) - { - min_buf |= (uint32_t)1<<6; - minute -= 40; - } - else - { - min_buf &= ~(uint32_t)1<<6; - } - - if (minute >= 20) - { - min_buf |= (uint32_t)1<<5; - minute -= 20; - } - else - { - min_buf &= ~(uint32_t)1<<5; - } - - if (minute >= 10) - { - min_buf |= (uint32_t)1<<4; - minute -= 10; - } - else - { - min_buf &= ~(uint32_t)1<<4; - } - - if (minute >= 8) - { - min_buf |= (uint32_t)1<<3; - minute -= 8; - } - else - { - min_buf &= ~(uint32_t)1<<3; - } - - if (minute >= 4) - { - min_buf |= (uint32_t)1<<2; - minute -= 4; - } - else - { - min_buf &= ~(uint32_t)1<<2; - } - - if (minute >= 2) - { - min_buf |= (uint32_t)1<<1; - minute -= 2; - } - else - { - min_buf &= ~(uint32_t)1<<1; - } - - if (minute >= 1) - { - min_buf |= (uint32_t)1; - minute -= 1; - } - else - { - min_buf &= ~(uint32_t)1; - } - - RTC->HMS.MIN = min_buf; - - /* д */ - RTC_StartWrite(); - - /* RTCд */ - if (flag == 0x00000000) - RTC->WP.WP = 0x00000000; - return SUCCESS; -} - - -/*************************************************************** - RTC_WriteHour - ޸ʱ - ֵhour: ʱ - ֵ - ֵ - ***************************************************************/ -ErrorStatus RTC_WriteHour(uint32_t hour, uint32_t meridiem) -{ - uint32_t flag,mode; - uint32_t hour_buf = 0; - - /* */ - if (hour >= 24) - return ERROR; - - mode = RTC_ReadHourmode(); - - if(mode == RTC_HOUR12 && hour > 12) //12Сʱģʽɴ12Сʱ - return ERROR; - - /* RTCд */ - flag = RTC->WP.WP; - if (flag == 0x00000000) - RTC->WP.WP = 0x55AAAA55; - - /* µֵ */ - if(mode == RTC_HOUR24) - { - if (hour >= 20) - { - hour_buf |= (uint32_t)1<<5; - hour -= 20; - } - else - { - hour_buf &= ~((uint32_t)1<<5); - } - } - else - { - if(meridiem == 1) - hour_buf |= (uint32_t)1<<5; - else - hour_buf &= ~((uint32_t)1<<5); - } - - if (hour >= 10) - { - hour_buf |= (uint32_t)1<<4; - hour -= 10; - } - else - { - hour_buf &= ~((uint32_t)1<<4); - } - - if (hour >= 8) - { - hour_buf |= (uint32_t)1<<3; - hour -= 8; - } - else - { - hour_buf &= ~((uint32_t)1<<3); - } - - if (hour >= 4) - { - hour_buf |= (uint32_t)1<<2; - hour -= 4; - } - else - { - hour_buf &= ~((uint32_t)1<<2); - } - - if (hour >= 2) - { - hour_buf |= (uint32_t)1<<1; - hour -= 2; - } - else - { - hour_buf &= ~((uint32_t)1<<1); - } - - if (hour >= 1) - { - hour_buf |= (uint32_t)1; - hour -= 1; - } - else - { - hour_buf &= ~(uint32_t)1; - } - - RTC->HMS.HOUR = hour_buf; - - /* д */ - RTC_StartWrite(); - - /* RTCд */ - if (flag == 0x00000000) - RTC->WP.WP = 0x00000000; - return SUCCESS; -} - -/*************************************************************** - RTC_WriteDay - ޸ - ֵday: - ֵ - ֵ - ***************************************************************/ -ErrorStatus RTC_WriteDay(uint32_t day) -{ - uint32_t flag; - uint32_t day_buf = 0; - - /* */ - if ((day == 0) || (day >= 32)) - return ERROR; - - /* RTCд */ - flag = RTC->WP.WP; - if (flag == 0x00000000) - RTC->WP.WP = 0x55AAAA55; - - /* µֵ */ - if (day >= 20) - { - day_buf |= (uint32_t)1<<5; - day -= 20; - } - else - { - day_buf &= ~((uint32_t)1<<5); - } - - if (day >= 10) - { - day_buf |= (uint32_t)1<<4; - day -= 10; - } - else - { - day_buf &= ~((uint32_t)1<<4); - } - - if (day >= 8) - { - day_buf |= (uint32_t)1<<3; - day -= 8; - } - else - { - day_buf &= ~((uint32_t)1<<3); - } - - if (day >= 4) - { - day_buf |= (uint32_t)1<<2; - day -= 4; - } - else - { - day_buf &= ~((uint32_t)1<<2); - } - - if (day >= 2) - { - day_buf |= (uint32_t)1<<1; - day -= 2; - } - else - { - day_buf &= ~((uint32_t)1<<1); - } - - if (day >= 1) - { - day_buf |= (uint32_t)1; - day -= 1; - } - else - { - day_buf &= ~(uint32_t)1; - } - - RTC->YMDW.DAY = day_buf; - - /* д */ - RTC_StartWrite(); - - /* RTCд */ - if (flag == 0x00000000) - RTC->WP.WP = 0x00000000; - return SUCCESS; -} - - -/*************************************************************** - RTC_WriteMonth - ޸ - ֵmonth: - ֵ - ֵ - ***************************************************************/ -ErrorStatus RTC_WriteMonth(uint32_t month) -{ - uint32_t flag; - uint32_t month_buf = 0; - - /* */ - if ((month == 0) || (month >= 13)) - return ERROR; - - /* RTCд */ - flag = RTC->WP.WP; - if (flag == 0x00000000) - RTC->WP.WP = 0x55AAAA55; - - /* µֵ */ - if (month >= 10) - { - month_buf |= (uint32_t)1<<4; - month -= 10; - } - else - { - month_buf &= ~((uint32_t)1<<4); - } - - if (month >= 8) - { - month_buf |= (uint32_t)1<<3; - month -= 8; - } - else - { - month_buf &= ~((uint32_t)1<<3); - } - - if (month >= 4) - { - month_buf |= (uint32_t)1<<2; - month -= 4; - } - else - { - month_buf &= ~((uint32_t)1<<2); - } - - if (month >= 2) - { - month_buf |= (uint32_t)1<<1; - month -= 2; - } - else - { - month_buf &= ~((uint32_t)1<<1); - } - - if (month >= 1) - { - month_buf |= (uint32_t)1; - month -= 1; - } - else - { - month_buf &= ~(uint32_t)1; - } - - RTC->YMDW.MON = month_buf; - - /* д */ - RTC_StartWrite(); - - /* RTCд */ - if (flag == 0x00000000) - RTC->WP.WP = 0x00000000; - return SUCCESS; -} - -/*************************************************************** - RTC_WriteYear - ޸ - ֵyear: - ֵ - ֵ - ***************************************************************/ -ErrorStatus RTC_WriteYear(uint32_t year) -{ - uint32_t flag; - uint32_t year_buf = 0; - - /* */ - if ((year < 2000) || (year > 2099)) - return ERROR; - - /* ת */ - year -= 2000; - - /* RTCд */ - flag = RTC->WP.WP; - if (flag == 0x00000000) - RTC->WP.WP = 0x55AAAA55; - - /* µֵ */ - if (year >= 80) - { - year_buf |= (uint32_t)1<<7; - year -= 80; - } - else - { - year_buf &= ~((uint32_t)1<<7); - } - - if (year >= 40) - { - year_buf |= (uint32_t)1<<6; - year -= 40; - } - else - { - year_buf &= ~((uint32_t)1<<6); - } - - if (year >= 20) - { - year_buf |= (uint32_t)1<<5; - year -= 20; - } - else - { - year_buf &= ~((uint32_t)1<<5); - } - - if (year >= 10) - { - year_buf |= (uint32_t)1<<4; - year -= 10; - } - else - { - year_buf &= ~((uint32_t)1<<4); - } - - if (year >= 8) - { - year_buf |= (uint32_t)1<<3; - year -= 8; - } - else - { - year_buf &= ~((uint32_t)1<<3); - } - - if (year >= 4) - { - year_buf |= (uint32_t)1<<2; - year -= 4; - } - else - { - year_buf &= ~((uint32_t)1<<2); - } - - if (year >= 2) - { - year_buf |= (uint32_t)1<<1; - year -= 2; - } - else - { - year_buf &= ~((uint32_t)1<<1); - } - - if (year >= 1) - { - year_buf |= (uint32_t)1; - year -= 1; - } - else - { - year_buf &= ~(uint32_t)1; - } - - RTC->YMDW.YEAR = year_buf; - - /* д */ - RTC_StartWrite(); - - /* RTCд */ - if (flag == 0x00000000) - RTC->WP.WP = 0x00000000; - return SUCCESS; -} - -/*************************************************************** - RTC_WriteWeek - ޸ - ֵweek: ڣ0-6 - ֵ - ֵ - ***************************************************************/ -ErrorStatus RTC_WriteWeek(uint32_t week) -{ - uint32_t flag; - - /* */ - if (week > 6) - return ERROR; - - /* RTCд */ - flag = RTC->WP.WP; - if (flag == 0x00000000) - RTC->WP.WP = 0x55AAAA55; - - RTC->YMDW.WEEK = week; - - /* д */ - RTC->CON.TMWR = 1; // д - RTC->CON.TMUP = 1; // д - while (RTC->CON.TMUP == 1); - - /* RTCд */ - if (flag == 0x00000000) - RTC->WP.WP = 0x00000000; - return SUCCESS; -} - -/*************************************************************** - RTC_ReadWeekAlarmMinute - ȡ - ֵ - ֵ - ֵǰķ - ***************************************************************/ -uint32_t RTC_ReadWeekAlarmMinute(void) -{ - uint32_t flag; - uint32_t result; - - /* RTCд */ - flag = RTC->WP.WP; - if (flag == 0x00000000) - RTC->WP.WP = 0x55AAAA55; - - /* */ - RTC_StartRead(); - - /* ʱ */ - result = ((RTC->WA.WM & (uint32_t)0x01) * 1); - result += (((RTC->WA.WM >> 1) & (uint32_t)0x01) * 2); - result += (((RTC->WA.WM >> 2) & (uint32_t)0x01) * 4); - result += (((RTC->WA.WM >> 3) & (uint32_t)0x01) * 8); - result += (((RTC->WA.WM >> 4) & (uint32_t)0x01) * 10); - result += (((RTC->WA.WM >> 5) & (uint32_t)0x01) * 20); - result += (((RTC->WA.WM >> 6) & (uint32_t)0x01) * 40); - - /* RTCд */ - if (flag == 0x00000000) - RTC->WP.WP = 0x00000000; - - return result; -} - -/*************************************************************** - RTC_ReadWeekAlarmHour - ȡСʱ - ֵ - ֵ - ֵǰСʱ - ***************************************************************/ -uint32_t RTC_ReadWeekAlarmHour(uint32_t *meridiem) -{ - uint32_t flag; - uint32_t result; - - /* RTCд */ - flag = RTC->WP.WP; - if (flag == 0x00000000) - RTC->WP.WP = 0x55AAAA55; - - /* */ - RTC_StartRead(); - - /* ʱ */ - result = ((RTC->WA.WH & (uint32_t)0x01) * 1); - result += (((RTC->WA.WH >> 1) & (uint32_t)0x01) * 2); - result += (((RTC->WA.WH >> 2) & (uint32_t)0x01) * 4); - result += (((RTC->WA.WH >> 3) & (uint32_t)0x01) * 8); - result += (((RTC->WA.WH >> 4) & (uint32_t)0x01) * 10); - - if(RTC_ReadHourmode() == RTC_HOUR24) //24Сʱģʽ20Сʱ - { - result += (((RTC->WA.WH >> 5) & (uint32_t)0x01) * 20); - } - else //12Сʱģʽ1 PM,0 AM - { - *meridiem = (((RTC->WA.WH >> 5) & (uint32_t)0x01)); - } - - /* RTCд */ - if (flag == 0x00000000) - RTC->WP.WP = 0x00000000; - - return result; -} - -/*************************************************************** - RTC_ReadWeekAlarmWeek - ȡ - ֵ - ֵ - ֵǰ - ***************************************************************/ -uint32_t RTC_ReadWeekAlarmWeek(void) -{ - uint32_t flag; - uint32_t result; - - /* RTCд */ - flag = RTC->WP.WP; - if (flag == 0x00000000) - RTC->WP.WP = 0x55AAAA55; - - /* */ - RTC_StartRead(); - - /* ʱ */ - switch(RTC->WA.WW) - { - case 0x00: result = 0;break; - case 0x01: result = 1;break; - case 0x02: result = 2;break; - case 0x03: result = 3;break; - case 0x04: result = 4;break; - case 0x05: result = 5;break; - case 0x06: result = 6;break; - default: result = 0;break; - } - - /* RTCд */ - if (flag == 0x00000000) - RTC->WP.WP = 0x00000000; - - return result; -} - - -/*************************************************************** - RTC_ReadDayAlarmMinute - ȡ - ֵ - ֵ - ֵǰķ - ***************************************************************/ -uint32_t RTC_ReadDayAlarmMinute(void) -{ - uint32_t flag; - uint32_t result; - - /* RTCд */ - flag = RTC->WP.WP; - if (flag == 0x00000000) - RTC->WP.WP = 0x55AAAA55; - - /* */ - RTC_StartRead(); - - /* ʱ */ - result = ((RTC->DA.DM & (uint32_t)0x01) * 1); - result += (((RTC->DA.DM >> 1) & (uint32_t)0x01) * 2); - result += (((RTC->DA.DM >> 2) & (uint32_t)0x01) * 4); - result += (((RTC->DA.DM >> 3) & (uint32_t)0x01) * 8); - result += (((RTC->DA.DM >> 4) & (uint32_t)0x01) * 10); - result += (((RTC->DA.DM >> 5) & (uint32_t)0x01) * 20); - result += (((RTC->DA.DM >> 6) & (uint32_t)0x01) * 40); - - /* RTCд */ - if (flag == 0x00000000) - RTC->WP.WP = 0x00000000; - - return result; -} - -/*************************************************************** - RTC_ReadDaykAlarmHour - ȡСʱ - ֵ - ֵ - ֵǰСʱ - ***************************************************************/ -uint32_t RTC_ReadDayAlarmHour(uint32_t *meridiem) -{ - uint32_t flag; - uint32_t result; - - /* RTCд */ - flag = RTC->WP.WP; - if (flag == 0x00000000) - RTC->WP.WP = 0x55AAAA55; - - /* */ - RTC_StartRead(); - - /* ʱ */ - result = ((RTC->DA.DH & (uint32_t)0x01) * 1); - result += (((RTC->DA.DH >> 1) & (uint32_t)0x01) * 2); - result += (((RTC->DA.DH >> 2) & (uint32_t)0x01) * 4); - result += (((RTC->DA.DH >> 3) & (uint32_t)0x01) * 8); - result += (((RTC->DA.DH >> 4) & (uint32_t)0x01) * 10); - - if(RTC_ReadHourmode() == RTC_HOUR24) //24Сʱģʽ20Сʱ - { - result += (((RTC->DA.DH >> 5) & (uint32_t)0x01) * 20); - } - else //12Сʱģʽ1 PM,0 AM - { - *meridiem = (((RTC->DA.DH >> 5) & (uint32_t)0x01)); - } - - /* RTCд */ - if (flag == 0x00000000) - RTC->WP.WP = 0x00000000; - - return result; -} - -/*************************************************************** - RTC_WriteWeekAlarmMinute - ޸ķ - ֵminute: - ֵ - ֵ - ***************************************************************/ -ErrorStatus RTC_WriteWeekAlarmMinute(uint32_t minute) -{ - uint32_t flag; - uint32_t minute_buf = 0; - - /* */ - if (minute >= 60) - return ERROR; - - /* RTCд */ - flag = RTC->WP.WP; - if (flag == 0x00000000) - RTC->WP.WP = 0x55AAAA55; - - /* µֵ */ - if (minute >= 40) - { - minute_buf |= (uint32_t)1<<6; - minute -= 40; - } - else - { - minute_buf &= ~(uint32_t)1<<6; - } - - if (minute >= 20) - { - minute_buf |= (uint32_t)1<<5; - minute -= 20; - } - else - { - minute_buf &= ~(uint32_t)1<<5; - } - - if (minute >= 10) - { - minute_buf |= (uint32_t)1<<4; - minute -= 10; - } - else - { - minute_buf &= ~(uint32_t)1<<4; - } - - if (minute >= 8) - { - minute_buf |= (uint32_t)1<<3; - minute -= 8; - } - else - { - minute_buf &= ~(uint32_t)1<<3; - } - - if (minute >= 4) - { - minute_buf |= (uint32_t)1<<2; - minute -= 4; - } - else - { - minute_buf &= ~(uint32_t)1<<2; - } - - if (minute >= 2) - { - minute_buf |= (uint32_t)1<<1; - minute -= 2; - } - else - { - minute_buf &= ~(uint32_t)1<<1; - } - - if (minute >= 1) - { - minute_buf |= (uint32_t)1; - minute -= 1; - } - else - { - minute_buf &= ~(uint32_t)1; - } - - RTC->WA.WM = minute_buf; - - /* RTCд */ - if (flag == 0x00000000) - RTC->WP.WP = 0x00000000; - return SUCCESS; -} - -/*************************************************************** - RTC_WriteWeekAlarmHour - ޸Сʱ - ֵhour: Сʱ - meridiem(12СʱģʽʱЧ) - 0 AM - 1 PM - ֵ - ֵ - ***************************************************************/ -ErrorStatus RTC_WriteWeekAlarmHour(uint32_t hour, uint32_t meridiem) -{ - uint32_t flag,mode; - uint32_t hour_buf = 0; - - /* */ - if (hour >= 24) - return ERROR; - - mode = RTC_ReadHourmode(); - - if(mode == RTC_HOUR12 && hour > 12) //12Сʱģʽɴ12Сʱ - return ERROR; - - /* RTCд */ - flag = RTC->WP.WP; - if (flag == 0x00000000) - RTC->WP.WP = 0x55AAAA55; - - /* µֵ */ - if(mode == RTC_HOUR24) - { - if (hour >= 20) - { - hour_buf |= (uint32_t)1<<5; - hour -= 20; - } - else - { - hour_buf &= ~((uint32_t)1<<5); - } - } - else - { - if(meridiem == 1) - hour_buf |= (uint32_t)1<<5; - else - hour_buf &= ~((uint32_t)1<<5); - } - - if (hour >= 10) - { - hour_buf |= (uint32_t)1<<4; - hour -= 10; - } - else - { - hour_buf &= ~((uint32_t)1<<4); - } - - if (hour >= 8) - { - hour_buf |= (uint32_t)1<<3; - hour -= 8; - } - else - { - hour_buf &= ~((uint32_t)1<<3); - } - - if (hour >= 4) - { - hour_buf |= (uint32_t)1<<2; - hour -= 4; - } - else - { - hour_buf &= ~((uint32_t)1<<2); - } - - if (hour >= 2) - { - hour_buf |= (uint32_t)1<<1; - hour -= 2; - } - else - { - hour_buf &= ~((uint32_t)1<<1); - } - - if (hour >= 1) - { - hour_buf |= (uint32_t)1; - hour -= 1; - } - else - { - hour_buf &= ~(uint32_t)1; - } - - RTC->WA.WH = hour_buf; - - - /* RTCд */ - if (flag == 0x00000000) - RTC->WP.WP = 0x00000000; - return SUCCESS; -} -/*************************************************************** - RTC_WriteWeekAlarmWeek - ޸ - ֵweek: ڣ0-6 - ֵ - ֵ - ***************************************************************/ -ErrorStatus RTC_WriteWeekAlarmWeek(uint32_t week) -{ - uint32_t flag; - - /* */ - if (week > 6) - return ERROR; - - /* RTCд */ - flag = RTC->WP.WP; - if (flag == 0x00000000) - RTC->WP.WP = 0x55AAAA55; - - RTC->WA.WW = week; - - /* RTCд */ - if (flag == 0x00000000) - RTC->WP.WP = 0x00000000; - return SUCCESS; -} - -/*************************************************************** - RTC_WriteDayAlarmMinute - ޸ķ - ֵminute: - ֵ - ֵ - ***************************************************************/ -ErrorStatus RTC_WriteDayAlarmMinute(uint32_t minute) -{ - uint32_t flag,minute_buf; - - /* */ - if (minute >= 60) - return ERROR; - - /* RTCд */ - flag = RTC->WP.WP; - if (flag == 0x00000000) - RTC->WP.WP = 0x55AAAA55; - - /* µֵ */ - if (minute >= 40) - { - minute_buf |= (uint32_t)1<<6; - minute -= 40; - } - else - { - minute_buf &= ~(uint32_t)1<<6; - } - - if (minute >= 20) - { - minute_buf |= (uint32_t)1<<5; - minute -= 20; - } - else - { - minute_buf &= ~(uint32_t)1<<5; - } - - if (minute >= 10) - { - minute_buf |= (uint32_t)1<<4; - minute -= 10; - } - else - { - minute_buf &= ~(uint32_t)1<<4; - } - - if (minute >= 8) - { - minute_buf |= (uint32_t)1<<3; - minute -= 8; - } - else - { - minute_buf &= ~(uint32_t)1<<3; - } - - if (minute >= 4) - { - minute_buf |= (uint32_t)1<<2; - minute -= 4; - } - else - { - minute_buf &= ~(uint32_t)1<<2; - } - - if (minute >= 2) - { - minute_buf |= (uint32_t)1<<1; - minute -= 2; - } - else - { - minute_buf &= ~(uint32_t)1<<1; - } - - if (minute >= 1) - { - minute_buf |= (uint32_t)1; - minute -= 1; - } - else - { - minute_buf &= ~(uint32_t)1; - } - - RTC->DA.DM = minute_buf; - - - /* RTCд */ - if (flag == 0x00000000) - RTC->WP.WP = 0x00000000; - return SUCCESS; -} - -/*************************************************************** - RTC_WriteDayAlarmHour - ޸Сʱ - ֵhour: Сʱ - meridiem(12СʱģʽʱЧ) - 0 AM - 1 PM - ֵ - ֵ - ***************************************************************/ -ErrorStatus RTC_WriteDayAlarmHour(uint32_t hour, uint32_t meridiem) -{ - uint32_t flag,mode; - uint32_t hour_buf = 0; - - /* */ - if (hour >= 24) - return ERROR; - - mode = RTC_ReadHourmode(); - - if(mode == RTC_HOUR12 && hour > 12) //12Сʱģʽɴ12Сʱ - return ERROR; - - /* RTCд */ - flag = RTC->WP.WP; - if (flag == 0x00000000) - RTC->WP.WP = 0x55AAAA55; - - /* µֵ */ - if(mode == RTC_HOUR24) - { - if (hour >= 20) - { - hour_buf |= (uint32_t)1<<5; - hour -= 20; - } - else - { - hour_buf &= ~((uint32_t)1<<5); - } - } - else - { - if(meridiem == 1) - hour_buf |= (uint32_t)1<<5; - else - hour_buf &= ~((uint32_t)1<<5); - } - - if (hour >= 10) - { - hour_buf |= (uint32_t)1<<4; - hour -= 10; - } - else - { - hour_buf &= ~((uint32_t)1<<4); - } - - if (hour >= 8) - { - hour_buf |= (uint32_t)1<<3; - hour -= 8; - } - else - { - hour_buf &= ~((uint32_t)1<<3); - } - - if (hour >= 4) - { - hour_buf |= (uint32_t)1<<2; - hour -= 4; - } - else - { - hour_buf &= ~((uint32_t)1<<2); - } - - if (hour >= 2) - { - hour_buf |= (uint32_t)1<<1; - hour -= 2; - } - else - { - hour_buf &= ~((uint32_t)1<<1); - } - - if (hour >= 1) - { - hour_buf |= (uint32_t)1; - hour -= 1; - } - else - { - hour_buf &= ~(uint32_t)1; - } - - RTC->DA.DH = hour_buf; - - /* RTCд */ - if (flag == 0x00000000) - RTC->WP.WP = 0x00000000; - return SUCCESS; -} - - -/*************************************************************** - RTC_InterruptEnable - ʹʵʱʱӵijЩж - ֵsrc: ʵʱʱӵжԴ - ֵ - ֵ - ***************************************************************/ -void RTC_InterruptEnable(RTC_Interrupt_Source src) -{ - uint32_t flag; - - /* RTCд */ - flag = RTC->WP.WP; - if (flag == 0x00000000) - RTC->WP.WP = 0x55AAAA55; - - /* µֵ */ - switch (src) - { - case RTC_Interrupt_Source_Second: - RTC->IE.SCDIE = 1; - break; - case RTC_Interrupt_Source_Minute: - RTC->IE.MINIE = 1; - break; - case RTC_Interrupt_Source_Hour: - RTC->IE.HORIE = 1; - break; - case RTC_Interrupt_Source_Day: - RTC->IE.DAYIE = 1; - break; - case RTC_Interrupt_Source_Month: - RTC->IE.MONIE = 1; - break; - case RTC_Interrupt_Source_DayALE: - RTC->IE.DALE = 1; - break; - case RTC_Interrupt_Source_WeekALE: - RTC->IE.WALE = 1; - break; - default: - break; - } - - /* RTCд */ - if (flag == 0x00000000) - RTC->WP.WP = 0x00000000; - - NVIC->ISER[0] |= (1 << 20); // ʹNVICж - return; -} - -/*************************************************************** - RTC_InterruptDisable - ʵʱʱӵijЩж - ֵsrc: ʵʱʱӵжԴ - ֵ - ֵ - ***************************************************************/ -void RTC_InterruptDisable(RTC_Interrupt_Source src) -{ - uint32_t flag; - - /* RTCд */ - flag = RTC->WP.WP; - if (flag == 0x00000000) - RTC->WP.WP = 0x55AAAA55; - - /* µֵ */ - switch (src) - { - case RTC_Interrupt_Source_Second: - RTC->IE.SCDIE = 0; - break; - case RTC_Interrupt_Source_Minute: - RTC->IE.MINIE = 0; - break; - case RTC_Interrupt_Source_Hour: - RTC->IE.HORIE = 0; - break; - case RTC_Interrupt_Source_Day: - RTC->IE.DAYIE = 0; - break; - case RTC_Interrupt_Source_Month: - RTC->IE.MONIE = 0; - break; - case RTC_Interrupt_Source_DayALE: - RTC->IE.DALE = 0; - break; - case RTC_Interrupt_Source_WeekALE: - RTC->IE.WALE = 0; - break; - default: - break; - } - /* RTCд */ - if (flag == 0x00000000) - RTC->WP.WP = 0x00000000; - return; -} - -/*************************************************************** - RTC_GetITStatus - ȡʵʱʱӵijЩж״̬ - ֵsrc: ʵʱʱӵжԴ - ֵ - ֵжϱ־ - ***************************************************************/ -ITStatus RTC_GetITStatus(RTC_Interrupt_Source src) -{ - ITStatus result = RESET; - - switch (src) - { - case RTC_Interrupt_Source_Second: - if(RTC->IE.SCDIE) - result = SET; - break; - case RTC_Interrupt_Source_Minute: - if(RTC->IE.MINIE) - result = SET; - break; - case RTC_Interrupt_Source_Hour: - if(RTC->IE.HORIE) - result = SET; - break; - case RTC_Interrupt_Source_Day: - if(RTC->IE.DAYIE) - result = SET; - break; - case RTC_Interrupt_Source_Month: - if(RTC->IE.MONIE) - result = SET; - break; - case RTC_Interrupt_Source_DayALE: - if(RTC->IE.DALE) - result = SET; - break; - case RTC_Interrupt_Source_WeekALE: - if(RTC->IE.WALE) - result = SET; - break; - default: - result = RESET; - break; - } - - return result; -} - -/*************************************************************** - RTC_GetFlagStatus - ȡʵʱʱӵijЩжϱ־ - ֵsrc: ʵʱʱӵжԴ - ֵ - ֵжϱ־ - ***************************************************************/ -FlagStatus RTC_GetFlagStatus(RTC_Interrupt_Source src) -{ - FlagStatus result = RESET; - - switch (src) - { - case RTC_Interrupt_Source_Second: - if(RTC->IF.SCDIF) - result = SET; - break; - case RTC_Interrupt_Source_Minute: - if(RTC->IF.MINIF) - result = SET; - break; - case RTC_Interrupt_Source_Hour: - if(RTC->IF.HORIF) - result = SET; - break; - case RTC_Interrupt_Source_Day: - if(RTC->IF.DAYIF) - result = SET; - break; - case RTC_Interrupt_Source_Month: - if(RTC->IF.MONIF) - result = SET; - break; - case RTC_Interrupt_Source_DayALE: - if(RTC->IF.DAFG) - result = SET; - break; - case RTC_Interrupt_Source_WeekALE: - if(RTC->IF.WAFG) - result = SET; - break; - default: - result = RESET; - break; - } - - return result; -} - -/*************************************************************** - RTC_ClearITPendingBit - ָжϱ־λ - ֵsrc: ʵʱʱӵжԴ - ֵ - ֵ - ***************************************************************/ -void RTC_ClearITPendingBit(RTC_Interrupt_Source src) -{ - uint32_t flag; - - /* RTCд */ - flag = RTC->WP.WP; - if (flag == 0x00000000) - RTC->WP.WP = 0x55AAAA55; - - switch (src) - { - case RTC_Interrupt_Source_Second: - RTC->IF.Word = RTC_Interrupt_Source_Second; - break; - case RTC_Interrupt_Source_Minute: - RTC->IF.Word = RTC_Interrupt_Source_Minute; - break; - case RTC_Interrupt_Source_Hour: - RTC->IF.Word = RTC_Interrupt_Source_Hour; - break; - case RTC_Interrupt_Source_Day: - RTC->IF.Word = RTC_Interrupt_Source_Day; - break; - case RTC_Interrupt_Source_Month: - RTC->IF.Word = RTC_Interrupt_Source_Month; - break; - case RTC_Interrupt_Source_DayALE: - RTC->IF.Word = RTC_Interrupt_Source_DayALE; - break; - case RTC_Interrupt_Source_WeekALE: - RTC->IF.Word = RTC_Interrupt_Source_WeekALE; - break; - default: - - break; - } - - /* RTCд */ - if (flag == 0x00000000) - RTC->WP.WP = 0x00000000; - return; -} - -/*************************END OF FILE**********************/ - - diff --git a/bsp/essemi/es8p508x/libraries/Library/Source/lib_scs.c b/bsp/essemi/es8p508x/libraries/Library/Source/lib_scs.c deleted file mode 100644 index 6579ddaee1..0000000000 --- a/bsp/essemi/es8p508x/libraries/Library/Source/lib_scs.c +++ /dev/null @@ -1,97 +0,0 @@ -/*************************************************************** - *Copyright (C), 2017, Shanghai Eastsoft Microelectronics Co., Ltd - *ļ lib_scs.c - * ߣ Liut - * V1.00 - * ڣ 2017/07/14 - * ںģ⺯ - * ע ES8P508xоƬ - ѧϰʾʹãûֱôķջеκηΡ - ***************************************************************/ -#include "lib_scs.h" - -/*************************************************************** - NVIC_Init - NVICʼ - ֵChannelжͨ Priorityжȼ Cmdʧܻʹ - ֵ - ֵ - ***************************************************************/ -void NVIC_Init(NVIC_IRQChannel Channel,NVIC_IRQPriority Priority,TYPE_FUNCEN Cmd) -{ - uint32_t tmppriority = 0x00; - - if (Cmd != DISABLE) - { - /* Compute the Corresponding IRQ Priority */ - tmppriority = NVIC->IP[Channel >> 0x02]; - tmppriority &= (uint32_t)(~(((uint32_t)0xFF) << ((Channel & 0x03) * 8))); - tmppriority |= (uint32_t)((((uint32_t)Priority << 6) & 0xFF) << ((Channel & 0x03) * 8)); - - NVIC->IP[Channel >> 0x02] = tmppriority; - - /* Enable the Selected IRQ Channels */ - NVIC->ISER[0] = (uint32_t)0x01 << (Channel & (uint8_t)0x1F); - } - else - { - /* Disable the Selected IRQ Channels */ - NVIC->ICER[0] = (uint32_t)0x01 << (Channel & (uint8_t)0x1F); - } -} - -/*************************************************************** - SCB_SystemLPConfig - ϵͳģʽ - ֵLowPowerModeģʽ NewStateʹܡʹ - ֵ - ֵ - ***************************************************************/ -void SCB_SystemLPConfig(SCB_TYPE_SCR LowPowerMode, TYPE_FUNCEN NewState) -{ - if (NewState != DISABLE) - SCB->SCR |= LowPowerMode; - else - SCB->SCR &= (uint32_t)(~(uint32_t)LowPowerMode); -} - -/*************************************************************** - SCB_GetCpuID - ȡCPUID - ֵ - ֵ - ֵ32λIDֵ - ***************************************************************/ -uint32_t SCB_GetCpuID(void) -{ - return (SCB->CPUID); -} - -/*************************************************************** - SysTick_Init - SysTickʼ - ֵʼýṹַ - ֵ - ֵ - ***************************************************************/ -void SysTick_Init(SYSTICK_InitStruType* SysT_InitStruct) -{ - uint32_t temp32 = 0; - - SysTick->LOAD = SysT_InitStruct->SysTick_Value; - SysTick->VAL = (uint32_t)0; - - if(SysT_InitStruct->SysTick_ClkSource != SysTick_ClkS_Base) - temp32 |= 0x00000004; - else - temp32 &= 0xFFFFFFFB; - - if(SysT_InitStruct->SysTick_ITEnable != DISABLE) - temp32 |= 0x00000002; - else - temp32 &= 0xFFFFFFFD; - - SysTick->CTRL = temp32; -} - -/*************************END OF FILE**********************/ diff --git a/bsp/essemi/es8p508x/libraries/Library/Source/lib_scu.c b/bsp/essemi/es8p508x/libraries/Library/Source/lib_scu.c deleted file mode 100644 index 48a3b51ac9..0000000000 --- a/bsp/essemi/es8p508x/libraries/Library/Source/lib_scu.c +++ /dev/null @@ -1,387 +0,0 @@ -/*************************************************************** - *Copyright (C), 2017, Shanghai Eastsoft Microelectronics Co., Ltd - *ļ lib_scu.c - * ߣ Liut - * V1.00 - * ڣ 2017/07/14 - * ϵͳģ⺯ - * ע ES8P508xоƬ - ѧϰʾʹãûֱôķջеκηΡ - ***************************************************************/ -#include "lib_scu.h" - -/*************************************************************** - SCU_OpenXTAL - : ⲿʱ - ֵ - ֵ - ֵϵͳʱԴ - ***************************************************************/ -void SCU_OpenXTAL(void) -{ - SCU_RegUnLock(); - SCU->SCLKEN1.XTAL_EN = 1; - SCU->SCLKEN0.XTAL_LP = 0; - while(SCU->SCLKEN1.XTAL_RDY == 0); //ȴⲿʱȶ - SCU_RegLock() ; -} - -/*************************************************************** - SCU_NMISelect - NMIж - ֵж - ֵ - ֵ - ***************************************************************/ -void SCU_NMISelect(SCU_TYPE_NMICS NMI_Type) -{ - SCU_RegUnLock(); - SCU->NMICON.NMICS = NMI_Type; - SCU_RegLock() ; -} - -/*************************************************************** - SCU_GetPWRCFlagStatus - ȡPWRCλ״̬Ĵ־λ״̬ - ֵPWRCĴ־λ - ֵ - ֵRESET/SET - ***************************************************************/ -FlagStatus SCU_GetPWRCFlagStatus(SCU_TYPE_PWRC PWRC_Flag) -{ - FlagStatus bitstatus = RESET; - if((SCU->PWRC.Word & (uint32_t)PWRC_Flag) != (uint32_t)RESET) - bitstatus = SET; - else - bitstatus = RESET; - - return bitstatus; -} - -/*************************************************************** - SCU_ClearPWRCFlagBit - PWRCλ״̬Ĵ־λ - ֵPWRCĴ־λ - ֵ - ֵ - ***************************************************************/ -void SCU_ClearPWRCFlagBit(SCU_TYPE_PWRC PWRC_Flag) -{ - SCU_RegUnLock() ; - SCU->PWRC.Word &= ~((uint32_t)PWRC_Flag); - SCU_RegLock() ; -} - -/*************************************************************** - SCU_GetLVDFlagStatus - ȡLVDDĴ־λ״̬ - ֵLVDĴ־λ - ֵ - ֵRESET/SET - ***************************************************************/ -FlagStatus SCU_GetLVDFlagStatus(SCU_TYPE_LVD0CON LVD_Flag) -{ - FlagStatus bitstatus = RESET; - - if((SCU->LVDCON.Word & (uint32_t)LVD_Flag) != (uint32_t)RESET) - bitstatus = SET; - else - bitstatus = RESET; - - return bitstatus; -} - -/*************************************************************** - SCU_SysClkSelect - ѡϵͳʱ - ֵʱԴ - ֵ - ֵ - ***************************************************************/ -void SCU_SysClkSelect(SCU_TYPE_SYSCLK Sysclk) -{ - SCU_RegUnLock() ; - SCU->SCLKEN0.CLK_SEL = Sysclk; - SCU_RegLock() ; -} - -/*************************************************************** - SCU_GetSysClk - ȡϵͳʱԴ - ֵ - ֵ - ֵϵͳʱԴ - ***************************************************************/ -SCU_TYPE_SYSCLK SCU_GetSysClk(void) -{ - return (SCU_TYPE_SYSCLK)(SCU->SCLKEN0.CLK_SEL); -} - -/*************************************************************** - SCU_HRCReadyFlag - ȡHRCȶ־λ - ֵ - ֵ - ֵRESETȶ/SETȶ - ***************************************************************/ -FlagStatus SCU_HRCReadyFlag(void) -{ - FlagStatus bitstatus = RESET; - - if((SCU->SCLKEN1.HRC_RDY) != (uint32_t)RESET) - bitstatus = SET; - else - bitstatus = RESET; - - return bitstatus; -} - -/*************************************************************** - SCU_XTALReadyFlag - ȡXTALȶ־λ - ֵ - ֵ - ֵRESETȶ/SETȶ - ***************************************************************/ -FlagStatus SCU_XTALReadyFlag(void) -{ - FlagStatus bitstatus = RESET; - - if((SCU->SCLKEN1.XTAL_RDY) != (uint32_t)RESET) - bitstatus = SET; - else - bitstatus = RESET; - - return bitstatus; -} - -/*************************************************************** - SCU_LOSCReadyFlag - ȡLOSCȶ־λ - ֵ - ֵ - ֵRESETȶ/SETȶ - ***************************************************************/ -FlagStatus SCU_PLLReadyFlag(void) -{ - FlagStatus bitstatus = RESET; - - if((SCU->SCLKEN1.PLL_RDY) != (uint32_t)RESET) - bitstatus = SET; - else - bitstatus = RESET; - - return bitstatus; -} - -/*************************************************************** - SystemClockConfig - ϵͳʱãڲʱӣ20MHZʱ - ֵ - ֵ - ֵ -***************************************************************/ -void SystemClockConfig(void) -{ - uint32_t Prot_Temp; - - Prot_Temp = SCU->PROT.PROT; - - if(Prot_Temp != 0) //д - SCU_RegUnLock(); // - - SCU_HRC_Enable(); //ʹڲ20MHZ - while(SCU_HRCReadyFlag() != SET); //ȴʱӿ - SCU_SysClkSelect(SCU_SysClk_HRC); //ѡڲ20MHZΪϵͳʱ - - SCU_SysClk_Div1(); //ϵͳʱӺƵ1:1 - - SystemCoreClock = 20000000; - - if(Prot_Temp != 0) //д - SCU_RegLock(); //д -} - -/*************************************************************** - DeviceClockAllEnable - ʱ - ֵ - ֵ - ֵ - ***************************************************************/ -void DeviceClockAllEnable(void) -{ - uint32_t Prot_Temp; - - Prot_Temp = SCU->PROT.PROT; - if(Prot_Temp != 0) //д - SCU_RegUnLock(); // - - SCU->PCLKEN0.Word = 0xFFFFFFFF; - SCU->PCLKEN1.Word = 0xFFFFFFFF; //ʱ - - if(Prot_Temp != 0) //д - SCU_RegLock(); //д -} - -/*************************************************************** - DeviceClockAllDisable - رʱ - ֵ - ֵ - ֵ - ***************************************************************/ -void DeviceClockAllDisable(void) -{ - uint32_t Prot_Temp; - - Prot_Temp = SCU->PROT.PROT; - if(Prot_Temp != 0) //д - SCU_RegUnLock(); // - - SCU->PCLKEN0.Word = 0x00000000; //رʱӣscu޷ر - SCU->PCLKEN1.Word = 0x00000000; - - if(Prot_Temp != 0) //д - SCU_RegLock(); //д -} - -/*************************************************************** - SystemClockConfig - ϵͳʱѡ - ֵCLKx ϵͳʱԴѡ - ֵ - ֵ - ***************************************************************/ -void SystemClockSelect(SCU_TYPE_SYSCLK SYSCLKx , SCU_TYPE_CLK_SEL CLK_SEL) -{ - SCU_RegUnLock(); // - - switch(SYSCLKx) - { - case 0: - SCU_HRC_Enable(); - while(SCU_HRCReadyFlag() != SET); - break; - case 1: - SCU_XTAL_Enable(); - while(SCU_XTALReadyFlag() != SET); - break; - case 2: - SCU_PLL_Enable(); - while(SCU_PLLReadyFlag() != SET); - break; - default:break; - } - - SCU->SCLKEN0.SYSCLK_DIV = 0; - SCU->SCLKEN0.CLK_SEL = CLK_SEL; - - SCU_RegLock(); -} - - -/*************************************************************** - PLLClock_Config - PLLʱ,PLLʱΪϵͳʱ - ֵpll_en:ǷPLLpll_originpllʱԴѡpll_outpllƵѡsys_pllϵͳʱǷʹPLLʱ - ֵ - ֵ - ***************************************************************/ -void PLLClock_Config(TYPE_FUNCEN pll_en , SCU_PLL_Origin pll_origin ,SCU_PLL_Out pll_out,TYPE_FUNCEN sys_pll) -{ - SCU_RegUnLock(); - - if(pll_en == DISABLE) //PLLΪֱֹӽֹPLL - { - SCU->SCLKEN0.PLL_MUX = 0; - SCU->SCLKEN1.PLL_BYLOCK = 0; - SCU->SCLKEN0.CLKFLT_BY = 0x00; - SCU->SCLKEN1.PLL_EN = 0; - return; - } - - if((pll_origin == SCU_PLL_HRC)) //ʹڲʱӣ迪ڲʱ - { - if(SCU->SCLKEN1.HRC_RDY == 0) - { - SCU->SCLKEN1.HRC_EN = 1; - while(SCU->SCLKEN1.HRC_RDY == 0); //ȴHRC - } - } - - if((pll_origin == SCU_PLL_XTAL_32K) - || (pll_origin == SCU_PLL_XTAL_4M) - ||(pll_origin == SCU_PLL_XTAL_8M) - || (pll_origin == SCU_PLL_XTAL_16M) - || (pll_origin == SCU_PLL_XTAL_20M)) //ʹⲿʱӣ迪ⲿʱ - { - if(SCU->SCLKEN1.XTAL_RDY == 0) - { - SCU->SCLKEN1.XTAL_EN = 1; - SCU->SCLKEN0.XTAL_LP = 0; - while(SCU->SCLKEN1.XTAL_RDY == 0); //ȴXTAL - } - } - - switch(pll_origin) - { - case SCU_PLL_HRC: - SCU->SCLKEN1.PLL_REF_SEL = 0x00; - break; - case SCU_PLL_LRC: - SCU->SCLKEN1.PLL_REF_SEL = 0x02; - break; - case SCU_PLL_XTAL_32K: - SCU->SCLKEN1.PLL_REF_SEL = 0x03; - break; - case SCU_PLL_XTAL_4M: - SCU->SCLKEN1.PLL_REF_SEL = 0x04; - break; - case SCU_PLL_XTAL_8M: - SCU->SCLKEN1.PLL_REF_SEL = 0x05; - break; - case SCU_PLL_XTAL_16M: - SCU->SCLKEN1.PLL_REF_SEL = 0x06; - break; - case SCU_PLL_XTAL_20M: - SCU->SCLKEN1.PLL_REF_SEL = 0x07; - break; - default: - break; - } - - SCU->SCLKEN1.PLL_48M_SEL = pll_out; //PLLΪ3248Mhz - - SCU->SCLKEN1.PLL_EN = 1; - while(SCU->SCLKEN1.PLL_RDY == 0); - - - if(sys_pll == ENABLE) - { - - if(pll_out == SCU_PLL_32M) - { - SCU->SCLKEN0.CLKFLT_BY = 0; - } - else - { - SCU->SCLKEN0.CLKFLT_BY = 0x55; //48M ʱ˲· - } - SCU->SCLKEN1.PLL_BYLOCK = 1; - SCU->SCLKEN0.PLL_MUX = 1; - } - else - { - SCU->SCLKEN0.PLL_MUX = 0; - SCU->SCLKEN1.PLL_BYLOCK = 0; - SCU->SCLKEN0.CLKFLT_BY = 0x00; - } - - SCU_RegLock(); -} - -/*************************END OF FILE**********************/ - - - diff --git a/bsp/essemi/es8p508x/libraries/Library/Source/lib_spi.c b/bsp/essemi/es8p508x/libraries/Library/Source/lib_spi.c deleted file mode 100644 index 666c142dcf..0000000000 --- a/bsp/essemi/es8p508x/libraries/Library/Source/lib_spi.c +++ /dev/null @@ -1,233 +0,0 @@ -/*************************************************************** - *Copyright (C), 2017, Shanghai Eastsoft Microelectronics Co., Ltd - *ļ lib_spi.c - * ߣ Liut - * V1.00 - * ڣ 2017/07/14 - * SPIģ⺯ - * ע ES8P508xоƬ - ѧϰʾʹãûֱôķջеκηΡ - ***************************************************************/ -#include "lib_spi.h" - -/*************************************************************** - SPI0_Init - SPIʼ - ֵʼýṹַ - ֵ - ֵ - ***************************************************************/ -void SPI_Init(SPI_InitStruType* SPI_InitStruct) -{ - uint32_t Temp = 0; - - Temp = SystemCoreClock / (SPI_InitStruct->SPI_Freq * 2); - if(Temp > 254) - Temp = 255; - - SPI0->CKS.CKS = Temp; - - SPI0->CON.DFS = SPI_InitStruct->SPI_Df; - SPI0->CON.MS = SPI_InitStruct->SPI_Mode; - SPI0->CON.DW = SPI_InitStruct->SPI_DW; - SPI0->CON.DRE = SPI_InitStruct->SPI_DelayRec; - SPI0->CON.TME = SPI_InitStruct->SPI_DelaySend; - - Temp = (uint32_t)SPI_InitStruct->SPI_SendDelayPeroid - 1; - if(Temp > 62) - Temp = 63; - - SPI0->CON.TMP = Temp; -} - -/*************************************************************** - SPI0_ITConfig - SPIж - ֵSPI_IEж NewStateʹܡʧ - ֵ - ֵ - ***************************************************************/ -void SPI_ITConfig(SPI_TYPE_IT SPI_IE,TYPE_FUNCEN NewState) -{ - if(NewState != DISABLE) - SPI0->IE.Word |= (uint32_t)SPI_IE; - else - SPI0->IE.Word &= ~((uint32_t)SPI_IE); -} - -/*************************************************************** - SPI0_DataFormatConfig - SPIݸʽ - ֵݸʽ - ֵ - ֵ - ***************************************************************/ -void SPI_DataFormatConfig(SPI_TYPE_DFS Type) -{ - SPI0->CON.DFS = Type; -} - -/*************************************************************** - SPI0_SendByte - SPIһֽڣ8λ - ֵҪ͵ - ֵ - ֵ - ***************************************************************/ -void SPI_SendByte(uint8_t Temp) -{ - SPI0->TBW.Byte[0] = Temp; -} - -/*************************************************************** - SPI0_SendHalfWord - SPIһ֣16λ - ֵҪ͵ - ֵ - ֵ - ***************************************************************/ -void SPI_SendHalfWord(uint16_t Temp) -{ - SPI0->TBW.HalfWord[0] = Temp; -} - -/*************************************************************** - SPI0_SendWord - SPIһ֣32λ - ֵҪ͵ - ֵ - ֵ - ***************************************************************/ -void SPI_SendWord(uint32_t Temp) -{ - SPI0->TBW.Word = Temp; -} - -/*************************************************************** - SPI0_RecByte - SPIһֽ - ֵ - ֵ - ֵյ - ***************************************************************/ -uint8_t SPI_RecByte(void) -{ - return SPI0->RBR.Byte[0]; -} - -/*************************************************************** - SPI0_RecHalfWord - SPIһ - ֵ - ֵ - ֵյ - ***************************************************************/ -uint16_t SPI_RecHalfWord(void) -{ - return SPI0->RBR.HalfWord[0]; -} - -/*************************************************************** - SPI0_RecWord - SPIһ - ֵ - ֵ - ֵյ - ***************************************************************/ -uint32_t SPI_RecWord(void) -{ - return SPI0->RBR.Word; -} - -/*************************************************************** - SPI0_TBIMConfig - SPIͻжģʽѡ - ֵжģʽ - ֵ - ֵ - ***************************************************************/ -void SPI_TBIMConfig(SPI_TYPE_TRBIM Type) -{ - SPI0->IE.TBIM = Type; -} - -/*************************************************************** - SPI0_RBIMConfig - SPIջжģʽѡ - ֵжģʽ - ֵ - ֵ - ***************************************************************/ -void SPI_RBIMConfig(SPI_TYPE_TRBIM Type) -{ - SPI0->IE.RBIM = Type; -} - -/*************************************************************** - SPI0_GetFlagStatus - SPI־λ״̬ - ֵ־λ - ֵ - ֵSET/RESET - ***************************************************************/ -FlagStatus SPI_GetFlagStatus(SPI_TYPE_FLAG Flag) -{ - FlagStatus bitstatus = RESET; - - /* ȡĴ */ - if((uint32_t)Flag <= 0x00000040) - { - if ((SPI0->IF.Word & Flag) != (uint32_t)RESET) - bitstatus = SET; - else - bitstatus = RESET; - } - - else - { - if ((SPI0->STA.Word & Flag) != (uint32_t)RESET) - bitstatus = SET; - else - bitstatus = RESET; - } - - return bitstatus; -} - -/*************************************************************** - SPI0_GetITStatus - SPIж״̬,δʹӦжʱ᷵SET - ֵжϱ־λ - ֵ - ֵSET/RESET - ***************************************************************/ -ITStatus SPI_GetITStatus(SPI_TYPE_IT Flag) -{ - FlagStatus bitstatus = RESET; - uint32_t itstatus = 0x0, itenable = 0x0; - - itstatus = SPI0->IF.Word & (uint32_t)Flag; - itenable = SPI0->IE.Word & (uint32_t)Flag; - - if ((itstatus != (uint32_t)RESET) && (itenable != (uint32_t)RESET)) - bitstatus = SET; - else - bitstatus = RESET; - - return bitstatus; -} - -/*************************************************************** - SPI0_ClearITPendingBit - SPIжϱ־ - ֵ־λ - ֵ - ֵ - ***************************************************************/ -void SPI_ClearITPendingBit(SPI_CLR_IF Flag) -{ - SPI0->IF.Word = (uint32_t)Flag; -} - -/*************************END OF FILE**********************/ - diff --git a/bsp/essemi/es8p508x/libraries/Library/Source/lib_timer.c b/bsp/essemi/es8p508x/libraries/Library/Source/lib_timer.c deleted file mode 100644 index 495e53b4cf..0000000000 --- a/bsp/essemi/es8p508x/libraries/Library/Source/lib_timer.c +++ /dev/null @@ -1,569 +0,0 @@ -/*************************************************************** - *Copyright (C), 2017, Shanghai Eastsoft Microelectronics Co., Ltd - *ļ lib_timer.c - * ߣ Liut - * V1.00 - * ڣ 2017/07/14 - * ʱģ⺯ - * ע ES8P508xоƬ - ѧϰʾʹãûֱôķջеκηΡ - ***************************************************************/ -#include "lib_timer.h" - -/*************************************************************** - T16Nx_BaseInit - T16Nxʼ - ֵT16NxT16N0/1/2/3 TIM_BaseInitStructʼýṹַ - ֵ - ֵ - ***************************************************************/ -void T16Nx_BaseInit(T16N_TypeDef* T16Nx,TIM_BaseInitStruType* TIM_BaseInitStruct) -{ - T16Nx->CON0.CS = TIM_BaseInitStruct->TIM_ClkS; - T16Nx->CON0.SYNC = TIM_BaseInitStruct->TIM_SYNC; - T16Nx->CON0.EDGE = TIM_BaseInitStruct->TIM_EDGE; - T16Nx->CON0.MOD = TIM_BaseInitStruct->TIM_Mode; -} -/*************************************************************** - T32Nx_BaseInit - T32Nxʼ - ֵT32NxT32N0 TIM_BaseInitStructʼýṹַ - ֵ - ֵ - ***************************************************************/ -void T32Nx_BaseInit(T32N_TypeDef* T32Nx,TIM_BaseInitStruType* TIM_BaseInitStruct) -{ - T32Nx->CON0.CS = TIM_BaseInitStruct->TIM_ClkS; - T32Nx->CON0.SYNC = TIM_BaseInitStruct->TIM_SYNC; - T32Nx->CON0.EDGE = TIM_BaseInitStruct->TIM_EDGE; - T32Nx->CON0.MOD = TIM_BaseInitStruct->TIM_Mode; -} -/*************************************************************** - T16Nx_CapInit - T16Nx׽ʼ - ֵT16NxT16N0/1/2/3 TIM_CapInitStructʼýṹַ - ֵ - ֵ - ***************************************************************/ -void T16Nx_CapInit(T16N_TypeDef* T16Nx,TIM_CapInitStruType* TIM_CapInitStruct) -{ - T16Nx->CON1.CAPPE = TIM_CapInitStruct->TIM_CapRise; - T16Nx->CON1.CAPNE = TIM_CapInitStruct->TIM_CapFall; - T16Nx->CON1.CAPIS0 = TIM_CapInitStruct->TIM_CapIS0; - T16Nx->CON1.CAPIS1 = TIM_CapInitStruct->TIM_CapIS1; - T16Nx->CON1.CAPT = TIM_CapInitStruct->TIM_CapTime; -} -/*************************************************************** - T32Nx_CapInit - T32Nx׽ʼ - ֵT32NxT32N0 TIM_CapInitStructʼýṹַ - ֵ - ֵ - ***************************************************************/ -void T32Nx_CapInit(T32N_TypeDef* T32Nx,TIM_CapInitStruType* TIM_CapInitStruct) -{ - T32Nx->CON1.CAPPE = TIM_CapInitStruct->TIM_CapRise; - T32Nx->CON1.CAPNE = TIM_CapInitStruct->TIM_CapFall; - T32Nx->CON1.CAPIS0 = TIM_CapInitStruct->TIM_CapIS0; - T32Nx->CON1.CAPIS1 = TIM_CapInitStruct->TIM_CapIS1; - T32Nx->CON1.CAPT = TIM_CapInitStruct->TIM_CapTime; -} -/*************************************************************** - T16Nx_MATxITConfig - T16NxƥĹģʽ - ֵT16NxT16N0/1/2/3 TypeƥĹģʽ - ֵ - ֵ - ***************************************************************/ -void T16Nx_MAT0ITConfig(T16N_TypeDef* T16Nx,TIM_TYPE_MATCON Type) -{ - T16Nx->CON0.MAT0S = Type; -} -void T16Nx_MAT1ITConfig(T16N_TypeDef* T16Nx,TIM_TYPE_MATCON Type) -{ - T16Nx->CON0.MAT1S = Type; -} -void T16Nx_MAT2ITConfig(T16N_TypeDef* T16Nx,TIM_TYPE_MATCON Type) -{ - T16Nx->CON0.MAT2S = Type; -} -void T16Nx_MAT3ITConfig(T16N_TypeDef* T16Nx,TIM_TYPE_MATCON Type) -{ - T16Nx->CON0.MAT3S = Type; -} -/*************************************************************** - T32Nx_MATxITConfig - T32NxƥĹģʽ - ֵT32NxT32N0 TypeƥĹģʽ - ֵ - ֵ - ***************************************************************/ -void T32Nx_MAT0ITConfig(T32N_TypeDef* T32Nx,TIM_TYPE_MATCON Type) -{ - T32Nx->CON0.MAT0S = Type; -} -void T32Nx_MAT1ITConfig(T32N_TypeDef* T32Nx,TIM_TYPE_MATCON Type) -{ - T32Nx->CON0.MAT1S = Type; -} -void T32Nx_MAT2ITConfig(T32N_TypeDef* T32Nx,TIM_TYPE_MATCON Type) -{ - T32Nx->CON0.MAT2S = Type; -} -void T32Nx_MAT3ITConfig(T32N_TypeDef* T32Nx,TIM_TYPE_MATCON Type) -{ - T32Nx->CON0.MAT3S = Type; -} -/*************************************************************** - T16Nx_MATxOutxConfig - T16Nxƥ˿ڵģʽ - ֵT16NxT16N0/1/2/3 Typeƥ˿ڵĹģʽ - ֵ - ֵ - ***************************************************************/ -void T16Nx_MAT0Out0Config(T16N_TypeDef* T16Nx,TIM_TYPE_MATOUT Type) -{ - T16Nx->CON2.MOM0 = Type; -} -void T16Nx_MAT1Out0Config(T16N_TypeDef* T16Nx,TIM_TYPE_MATOUT Type) -{ - T16Nx->CON2.MOM1 = Type; -} -void T16Nx_MAT2Out1Config(T16N_TypeDef* T16Nx,TIM_TYPE_MATOUT Type) -{ - T16Nx->CON2.MOM2 = Type; -} -void T16Nx_MAT3Out1Config(T16N_TypeDef* T16Nx,TIM_TYPE_MATOUT Type) -{ - T16Nx->CON2.MOM3 = Type; -} -/*************************************************************** - T32Nx_MATxOutxConfig - T32Nxƥ˿ڵģʽ - ֵT32NxT32N0 Typeƥ˿ڵĹģʽ - ֵ - ֵ - ***************************************************************/ -void T32Nx_MAT0Out0Config(T32N_TypeDef* T32Nx,TIM_TYPE_MATOUT Type) -{ - T32Nx->CON2.MOM0 = Type; -} -void T32Nx_MAT1Out0Config(T32N_TypeDef* T32Nx,TIM_TYPE_MATOUT Type) -{ - T32Nx->CON2.MOM1 = Type; -} -void T32Nx_MAT2Out1Config(T32N_TypeDef* T32Nx,TIM_TYPE_MATOUT Type) -{ - T32Nx->CON2.MOM2 = Type; -} -void T32Nx_MAT3Out1Config(T32N_TypeDef* T32Nx,TIM_TYPE_MATOUT Type) -{ - T32Nx->CON2.MOM3 = Type; -} -/*************************************************************** - T16Nx_ITConfig - T16Nж - ֵT16NxT16N0/1/2/3 Typeж NewStateʹ/ʧ - ֵ - ֵ - ***************************************************************/ -void T16Nx_ITConfig(T16N_TypeDef* T16Nx,TIM_TYPE_IT Type,TYPE_FUNCEN NewState) -{ - if (NewState != DISABLE) - T16Nx->IE.Word |= (uint32_t)Type; - else - T16Nx->IE.Word &= (~(uint32_t)Type); -} -/*************************************************************** - T32Nx_ITConfig - T32Nж - ֵT32NxT32N0 Typeж NewStateʹ/ʧ - ֵ - ֵ - ***************************************************************/ -void T32Nx_ITConfig(T32N_TypeDef* T32Nx,TIM_TYPE_IT Type,TYPE_FUNCEN NewState) -{ - if (NewState != DISABLE) - T32Nx->IE.Word|= (uint32_t)Type; - else - T32Nx->IE.Word &= (~(uint32_t)Type); -} -/*************************************************************** - T16Nx_PWMOutConfig - T16N0OUT0,T16N1OUT0T16N2OUT0T16N3OUT0 áԭΪʹuartƣ˲uartͬʱʹá - ֵ - ֵ - ֵ - ***************************************************************/ -void T16Nx_PWMOutConfig(T16N_TypeDef* T16Nx,T16Nx_PWMInitStruType* T16Nx_PWMInitStruct) -{ - T16Nx->CON2.MOE0 = T16Nx_PWMInitStruct->T16Nx_MOE0; //˿0Ƿʹ - T16Nx->CON2.MOE1 = T16Nx_PWMInitStruct->T16Nx_MOE1; //˿1Ƿʹ - T16Nx->CON2.POL0 = T16Nx_PWMInitStruct->T16Nx_POL0; //T16NxOut0 - T16Nx->CON2.POL1 = T16Nx_PWMInitStruct->T16Nx_POL1; //T16NxOut1 -} -/*************************************************************** - T16Nx_PWMBK_Config - PWMɲ - ֵT16NxT16N0/1/2/3 ,Type PWMɲṹ - ֵ - ֵ - ***************************************************************/ -void T16Nx_PWMBK_Config(T16N_TypeDef* T16Nx,T16Nx_PWMBK_Type* type) -{ - T16Nx->CON2.PBKL0 = type->T16Nx_PWMBKL0; //PWMͨ0ɲƽѡ - T16Nx->CON2.PBKL1 = type->T16Nx_PWMBKL1; //PWMͨ1ɲƽѡ - T16Nx->CON2.PBKS = type->T16Nx_PWMBKS; //PWMźԴѡ - T16Nx->CON2.PBKPS = type->T16Nx_PWMBKPS; //PWMͨɲźżѡ - T16Nx->CON2.PBKEN = type->T16Nx_PWMBKEN; //PWMͨɲʹ -} -/*************************************************************** - T16Nx_TRG_Config - : T16N ADCʹ - ֵT16NxT16N0/1/2/3 - ֵ - ֵ - ***************************************************************/ -void T16Nx_TRG_Config(T16N_TypeDef* T16Nx,T16Nx_PWMTRG_type Type,TYPE_FUNCEN NewState) -{ - if(Type == T16Nx_MAT0) - T16Nx->TRG.MAT0TAR = 1; - else if(Type == T16Nx_MAT1) - T16Nx->TRG.MAT1TAR = 1; - else if(Type == T16Nx_MAT2) - T16Nx->TRG.MAT2TAR = 1; - else if(Type == T16Nx_MAT3) - T16Nx->TRG.MAT3TAR = 1; - - T16Nx->TRG.OVTAR = NewState; -} -/*************************************************************** - T16Nx_GetPWMBKF - ȡPWMBKFɲ־λ - ֵT16NxT16N0/1/2/3 - ֵPWMBKF־λֵSETɲ¼RESETδɲ¼ - ֵ - ***************************************************************/ -FlagStatus T16Nx_GetPWMBKF(T16N_TypeDef* T16Nx) -{ - if(T16Nx->CON2.PBKF == 1) - return SET; - else - return RESET; -} -/*************************************************************** - T16Nx_ResetPWMBKF - : PWMBKF־־PWM˿ڻָshuc - ֵT16NxT16N0/1/2/3 - ֵ - ֵ - ***************************************************************/ -void T16Nx_ResetPWMBKF(T16N_TypeDef* T16Nx) -{ - T16Nx->CON2.PBKF = 1; -} -/*************************************************************** - T16Nx_SetCNT - üֵ - ֵT16NxT16N0/1/2/3 Value16λֵ - ֵ - ֵ - ***************************************************************/ -void T16Nx_SetCNT(T16N_TypeDef* T16Nx,uint16_t Value) -{ - T16Nx->CNT.CNT = Value; -} -/*************************************************************** - T32Nx_SetCNT - üֵ - ֵT32NxT32N0 Value32λֵ16λʱҶ룩 - ֵ - ֵ - ***************************************************************/ -void T32Nx_SetCNT(T32N_TypeDef* T32Nx,uint32_t Value) -{ - T32Nx->CNT.CNT = Value; -} -/*************************************************************** - T16Nx_SetPRECNT - ԤƵĴֵ - ֵT16NxT16N0/1/2/3 Value8λֵ - ֵ - ֵ - ***************************************************************/ -void T16Nx_SetPRECNT(T16N_TypeDef* T16Nx,uint8_t Value) -{ - T16Nx->PRECNT.PRECNT = Value; -} -/*************************************************************** - T32Nx_SetPRECNT - ԤƵĴֵ - ֵT32NxT32N0 Value8λֵ - ֵ - ֵ - ***************************************************************/ -void T32Nx_SetPRECNT(T32N_TypeDef* T32Nx,uint8_t Value) -{ - T32Nx->PRECNT.PRECNT = Value - 1; -} -/*************************************************************** - T16Nx_SetPREMAT - ԤƵƥĴֵ - ֵT16NxT16N0/1/2/3 Value8λֵ - ֵ - ֵ - ***************************************************************/ -void T16Nx_SetPREMAT(T16N_TypeDef* T16Nx,uint8_t Value) -{ - T16Nx->PREMAT.PREMAT = Value - 1; -} -/*************************************************************** - T32Nx_SetPREMAT - ԤƵƥĴֵ - ֵT32NxT32N0 Value8λֵ - ֵ - ֵ - ***************************************************************/ -void T32Nx_SetPREMAT(T32N_TypeDef* T32Nx,uint8_t Value) -{ - T32Nx->PREMAT.PREMAT = Value - 1; -} -/*************************************************************** - T16Nx_SetMATx - ƥĴ - ֵT16NxT16N0/1/2/3 MATxTIM_MAT0/1/2/3 Value16λֵ - ֵ - ֵ - ***************************************************************/ -void T16Nx_SetMAT0(T16N_TypeDef* T16Nx,uint16_t Value) -{ - T16Nx->MAT0.MAT0 = Value; -} -void T16Nx_SetMAT1(T16N_TypeDef* T16Nx,uint16_t Value) -{ - T16Nx->MAT1.MAT1 = Value; -} -void T16Nx_SetMAT2(T16N_TypeDef* T16Nx,uint16_t Value) -{ - T16Nx->MAT2.MAT2 = Value; -} -void T16Nx_SetMAT3(T16N_TypeDef* T16Nx,uint16_t Value) -{ - T16Nx->MAT3.MAT3 = Value; -} -/*************************************************************** - T32Nx_SetMATx - ƥĴ - ֵT32NxT32N0 MATxTIM_MAT0/1/2/3 Value32λֵ - ֵ - ֵ - ***************************************************************/ -void T32Nx_SetMAT0(T32N_TypeDef* T32Nx,uint32_t Value) -{ - T32Nx->MAT0.MAT0 = Value; -} -void T32Nx_SetMAT1(T32N_TypeDef* T32Nx,uint32_t Value) -{ - T32Nx->MAT1.MAT1 = Value; -} -void T32Nx_SetMAT2(T32N_TypeDef* T32Nx,uint32_t Value) -{ - T32Nx->MAT2.MAT2 = Value; -} -void T32Nx_SetMAT3(T32N_TypeDef* T32Nx,uint32_t Value) -{ - T32Nx->MAT3.MAT3 = Value; -} -/*************************************************************** - T16Nx_GetMATx - ȡƥĴֵ - ֵT16NxT16N0/1/2/3 - ֵ - ֵ16λֵ - ***************************************************************/ -uint16_t T16Nx_GetMAT0(T16N_TypeDef* T16Nx) -{ - return (T16Nx->MAT0.MAT0); -} -uint16_t T16Nx_GetMAT1(T16N_TypeDef* T16Nx) -{ - return (T16Nx->MAT1.MAT1); -} -uint16_t T16Nx_GetMAT2(T16N_TypeDef* T16Nx) -{ - return (T16Nx->MAT2.MAT2); -} -uint16_t T16Nx_GetMAT3(T16N_TypeDef* T16Nx) -{ - return (T16Nx->MAT3.MAT3); -} -/*************************************************************** - T32Nx_GetMATx - ȡƥĴֵ - ֵT32NxT32N0/3 MATxTIM_MAT0/1/2/3 - ֵ - ֵ32λֵ - ***************************************************************/ -uint32_t T32Nx_GetMAT0(T32N_TypeDef* T32Nx) -{ - return (T32Nx->MAT0.MAT0); -} -uint32_t T32Nx_GetMAT1(T32N_TypeDef* T32Nx) -{ - return (T32Nx->MAT1.MAT1); -} -uint32_t T32Nx_GetMAT2(T32N_TypeDef* T32Nx) -{ - return (T32Nx->MAT2.MAT2); -} -uint32_t T32Nx_GetMAT3(T32N_TypeDef* T32Nx) -{ - return (T32Nx->MAT3.MAT3); -} -/*************************************************************** - T16Nx_GetCNT - ȡĴֵ - ֵT16NxT16N0/1/2/3 - ֵ16λֵ - ***************************************************************/ -uint16_t T16Nx_GetCNT(T16N_TypeDef* T16Nx) -{ - return (T16Nx->CNT.CNT); -} -/*************************************************************** - T32Nx_GetCNT - ȡĴֵ - ֵT32NxT32N0/3 - ֵ16/32λֵ - ***************************************************************/ -uint32_t T32Nx_GetCNT(T32N_TypeDef* T32Nx) -{ - return (T32Nx->CNT.CNT); -} -/*************************************************************** - T16Nx_GetPRECNT - ȡԤƵĴֵ - ֵT16NxT16N0/1/2/3 - ֵ - ֵ8λֵ - ***************************************************************/ -uint8_t T16Nx_GetPRECNT(T16N_TypeDef* T16Nx) -{ - return (uint8_t)(T16Nx->PRECNT.PRECNT); -} -/*************************************************************** - T32Nx_GetPRECNT - ȡԤƵĴֵ - ֵT32NxT32N0 - ֵ - ֵ8λֵ - ***************************************************************/ -uint8_t T32Nx_GetPRECNT(T32N_TypeDef* T32Nx) -{ - return (uint8_t)(T32Nx->PRECNT.PRECNT); -} -/*************************************************************** - T16Nx_GetFlagStatus - ȡָ־λ - ֵT16NxT16N0/1/2/3 TIM_Flagжϱ־λ - ֵ - ֵRESET/SET - ***************************************************************/ -FlagStatus T16Nx_GetFlagStatus(T16N_TypeDef* T16Nx,TIM_TYPE_IF TIM_Flag) -{ - FlagStatus bitstatus = RESET; - - if((T16Nx->IF.Word & (uint32_t)TIM_Flag) != (uint32_t)RESET) - bitstatus = SET; - else - bitstatus = RESET; - - return bitstatus; -} -/*************************************************************** - T32Nx_GetFlagStatus - ȡָ־λ - ֵT32NxT32N0 TIM_Flagжϱ־λ - ֵ - ֵRESET/SET - ***************************************************************/ -FlagStatus T32Nx_GetFlagStatus(T32N_TypeDef* T32Nx,TIM_TYPE_IF TIM_Flag) -{ - FlagStatus bitstatus = RESET; - - if((T32Nx->IF.Word & (uint32_t)TIM_Flag) != (uint32_t)RESET) - bitstatus = SET; - else - bitstatus = RESET; - - return bitstatus; -} - -/*************************************************************** - T16Nx_GetITStatus - ȡָжϱ־λ,δʹӦжʱ᷵SET - ֵT16NxT16N0/1/2/3 TIM_Flagжϱ־λ - ֵ - ֵRESET/SET - ***************************************************************/ -ITStatus T16Nx_GetITStatus(T16N_TypeDef* T16Nx,TIM_TYPE_IT TIM_Flag) -{ - ITStatus bitstatus = RESET; - uint32_t itstatus = 0x0, itenable = 0x0; - - itstatus = T16Nx->IF.Word & (uint32_t)TIM_Flag; - itenable = T16Nx->IE.Word & (uint32_t)TIM_Flag; - - if ((itstatus != (uint32_t)RESET) && (itenable != (uint32_t)RESET)) - bitstatus = SET; - else - bitstatus = RESET; - - return bitstatus; -} -/*************************************************************** - T32Nx_GetITStatus - ȡָжϱ־λ,δʹӦжʱ᷵SET - ֵT32NxT32N0 TIM_Flagжϱ־λ - ֵ - ֵRESET/SET - ***************************************************************/ -ITStatus T32Nx_GetITStatus(T32N_TypeDef* T32Nx,TIM_TYPE_IT TIM_Flag) -{ - ITStatus bitstatus = RESET; - uint32_t itstatus = 0x0, itenable = 0x0; - - itstatus = T32Nx->IF.Word & (uint32_t)TIM_Flag; - itenable = T32Nx->IE.Word & (uint32_t)TIM_Flag; - - if ((itstatus != (uint32_t)RESET) && (itenable != (uint32_t)RESET)) - bitstatus = SET; - else - bitstatus = RESET; - - return bitstatus; -} -/*************************************************************** - T16Nx_ClearIFPendingBit - ָжϱ־λ - ֵT16NxT16N0/1/2/3 TIM_Flagжϱ־λ - ֵ - ֵ - ***************************************************************/ -void T16Nx_ClearIFPendingBit(T16N_TypeDef* T16Nx,TIM_TYPE_IF TIM_Flag) -{ - T16Nx->IF.Word = (uint32_t)TIM_Flag; -} -/*************************************************************** - T32Nx_ClearIFPendingBit - ָжϱ־λ - ֵT32NxT32N0 TIM_Flagжϱ־λ - ֵ - ֵ - ***************************************************************/ -void T32Nx_ClearIFPendingBit(T32N_TypeDef* T32Nx,TIM_TYPE_IF TIM_Flag) -{ - T32Nx->IF.Word = (uint32_t)TIM_Flag; -} - -/*************************END OF FILE**********************/ diff --git a/bsp/essemi/es8p508x/libraries/Library/Source/lib_uart.c b/bsp/essemi/es8p508x/libraries/Library/Source/lib_uart.c deleted file mode 100644 index 0314562ff0..0000000000 --- a/bsp/essemi/es8p508x/libraries/Library/Source/lib_uart.c +++ /dev/null @@ -1,198 +0,0 @@ -/*************************************************************** - *Copyright (C), 2017, Shanghai Eastsoft Microelectronics Co., Ltd - *ļ lib_uart.c - * ߣ Liut - * V1.00 - * ڣ 2017/07/14 - * UARTģ⺯ - * ע ES8P508xоƬ - ѧϰʾʹãûֱôķջеκηΡ - ***************************************************************/ -#include "lib_uart.h" - -/*************************************************************** - UART_Init - UARTʼ - ֵUARTxUART0/1/2/3/4/5 UART_InitStructʼýṹַ - ֵ - ֵ - ***************************************************************/ -void UART_Init(UART_TypeDef* UARTx,UART_InitStruType* UART_InitStruct) -{ - uint32_t BaudClockTemp = 0, BaudTemp = 0; - - if(UART_InitStruct->UART_ClockSet == UART_Clock_1) - { - BaudClockTemp = (SystemCoreClock/16)%UART_InitStruct->UART_BaudRate; - if(UART_InitStruct->UART_BaudRate >= (2*BaudClockTemp)) - { - BaudTemp = (SystemCoreClock/16/UART_InitStruct->UART_BaudRate)-1; - } - else - { - BaudTemp = SystemCoreClock/16/UART_InitStruct->UART_BaudRate; - } - } - else if(UART_InitStruct->UART_ClockSet == UART_Clock_2) - { - BaudClockTemp = (SystemCoreClock/32)%UART_InitStruct->UART_BaudRate; - if(UART_InitStruct->UART_BaudRate >= (2*BaudClockTemp)) - { - BaudTemp = (SystemCoreClock/32/UART_InitStruct->UART_BaudRate)-1; - } - else - { - BaudTemp = SystemCoreClock/32/UART_InitStruct->UART_BaudRate; - } - } - else if(UART_InitStruct->UART_ClockSet == UART_Clock_4) - { - BaudClockTemp = (SystemCoreClock/64)%UART_InitStruct->UART_BaudRate; - if(UART_InitStruct->UART_BaudRate >= (2*BaudClockTemp)) - { - BaudTemp = (SystemCoreClock/64/UART_InitStruct->UART_BaudRate)-1; - } - else - { - BaudTemp = SystemCoreClock/64/UART_InitStruct->UART_BaudRate; - } - } - - if(BaudTemp > 2046) - { - BaudTemp = 2047; - } - - UARTx->CON.BCS = UART_InitStruct->UART_ClockSet; - UARTx->BRR.BRR = BaudTemp ; - - UARTx->CON.TXFS = UART_InitStruct->UART_StopBits; - UARTx->CON.TXMOD = UART_InitStruct->UART_TxMode; - UARTx->CON.TXP = UART_InitStruct->UART_TxPolar; - UARTx->CON.RXMOD = UART_InitStruct->UART_RxMode; - UARTx->CON.RXP = UART_InitStruct->UART_RxPolar; -} -/*************************************************************** - UART_ITConfig - UARTж - ֵUARTxUART0/1/2/3/4/5 UART_ITж NewStateʹ/ʧ - ֵ - ֵ - ***************************************************************/ -void UART_ITConfig(UART_TypeDef* UARTx,UART_TYPE_IT UART_IT,TYPE_FUNCEN NewState) -{ - if (NewState != DISABLE) - UARTx->IE.Word = (UARTx->IE.Word & (uint32_t)0x0000FFFF) | (uint32_t) UART_IT; - else - UARTx->IE.Word = (UARTx->IE.Word & (uint32_t)0x0000FFFF) & (~((uint32_t) UART_IT)); -} -/*************************************************************** - UART_TBIMConfig - UARTͻжģʽѡ - ֵUARTxUART0/1/2/3/4/5 Typeжģʽ - ֵ - ֵ - ***************************************************************/ -void UART_TBIMConfig(UART_TypeDef* UARTx,UART_TYPE_TRBIM Type) -{ - UARTx->IE.TBIM = Type; -} -/*************************************************************** - UART_RBIMConfig - UARTջжģʽѡ - ֵUARTxUART0/1/2/3 Typeжģʽ - ֵ - ֵ - ***************************************************************/ -void UART_RBIMConfig(UART_TypeDef* UARTx,UART_TYPE_TRBIM Type) -{ - UARTx->IE.RBIM = Type; -} -/*************************************************************** - UART_Sendxxxx - UARTֽڡ֡ - ֵUARTxUART0/1/2/3/4/5 - ֵ - ֵ - ***************************************************************/ -void UART_SendByte(UART_TypeDef* UARTx,uint8_t Temp08) -{ - UARTx->TBW.Byte[0] = Temp08; -} -void UART_SendHalfWord(UART_TypeDef* UARTx,uint16_t Temp16) -{ - UARTx->TBW.HalfWord[0] = Temp16; -} -void UART_SendWord(UART_TypeDef* UARTx,uint32_t Temp32) -{ - UARTx->TBW.Word = Temp32; -} -/*************************************************************** - UART_Recxxxx - UARTֽڡ֡ - ֵUARTxUART0/1/2/3/4/5 - ֵ - ֵ - ***************************************************************/ -uint8_t UART_RecByte(UART_TypeDef* UARTx) -{ - return UARTx->RBR.Byte[0]; -} -uint16_t UART_RecHalfWord(UART_TypeDef* UARTx) -{ - return UARTx->RBR.HalfWord[0]; -} -uint32_t UART_RecWord(UART_TypeDef* UARTx) -{ - return UARTx->RBR.Word; -} -/*************************************************************** - UART_GetFlagStatus - UARTȡ־λ״̬ - ֵUARTxUART0/1/2/3/4/5 UART_Flag־λ - ֵ - ֵSET/RESET - ***************************************************************/ -FlagStatus UART_GetFlagStatus(UART_TypeDef* UARTx,UART_TYPE_FLAG UART_Flag) -{ - FlagStatus bitstatus = RESET; - - if ((UARTx->IF.Word & ((uint32_t)UART_Flag)) != RESET) - bitstatus = SET; - else - bitstatus = RESET; - - return bitstatus; -} - -/*************************************************************** - UART_GetITStatus - UARTȡж״̬ - ֵUARTxUART0/1/2/3/4/5 UART_Flag־λ - ֵ - ֵSET/RESET - ***************************************************************/ -ITStatus UART_GetITStatus(UART_TypeDef* UARTx,UART_TYPE_IT UART_IT) -{ - FlagStatus bitstatus = RESET; - - if((UARTx->IE.Word & ((uint32_t)UART_IT)) == 0) - bitstatus = RESET; - else - bitstatus = SET; - - return bitstatus; -} -/*************************************************************** - UART_ClearIFPendingBit - UART־λ - ֵUARTxUART0/1/2/3/4/5 UART_Flag־λ - ֵ - ֵ - ***************************************************************/ -void UART_ClearIFPendingBit(UART_TypeDef* UARTx,UART_CLR_IF UART_Flag) -{ - UARTx->IF.Word = (uint32_t)UART_Flag; -} - -/*************************END OF FILE**********************/ diff --git a/bsp/essemi/es8p508x/libraries/Library/Source/lib_wdt.c b/bsp/essemi/es8p508x/libraries/Library/Source/lib_wdt.c deleted file mode 100644 index 2218a204a9..0000000000 --- a/bsp/essemi/es8p508x/libraries/Library/Source/lib_wdt.c +++ /dev/null @@ -1,172 +0,0 @@ -/*************************************************************** - *Copyright (C), 2017, Shanghai Eastsoft Microelectronics Co., Ltd - *ļ lib_wdt.c - * ߣ Liut - * V1.00 - * ڣ 2017/02/04 - * Źģ⺯ - * ע ES8P508xоƬ - ѧϰʾʹãûֱôķջеκηΡ - ***************************************************************/ -#include "lib_wdt.h" - -/************************************* - IWDT_Init - IWDTʼ - ֵʼṹ - ֵ - **************************************/ -void IWDT_Init(IWDT_InitStruType *WDT_InitStruct) -{ - uint32_t tmp; - - if (WDT_InitStruct->WDT_Clock != WDT_CLOCK_PCLK) - tmp = (uint32_t)(32 * WDT_InitStruct->WDT_Tms); - else - tmp = SystemCoreClock / 1000 * WDT_InitStruct->WDT_Tms; - - IWDT->LOAD.LOAD = tmp; - IWDT->CON.CLKS = WDT_InitStruct->WDT_Clock; - IWDT->CON.IE = WDT_InitStruct->WDT_IE; - IWDT->CON.RSTEN = WDT_InitStruct->WDT_Rst; - - return; -} - -/************************************* - IWDT_SetReloadValue - WDTصijֵ - ֵʼֵ32-bit޷ - ֵ - **************************************/ -void IWDT_SetReloadValue(uint32_t Value) -{ - IWDT->LOAD.LOAD = Value; - return; -} - -/************************************* - IWDT_GetValue - ȡWDTǰֵ - ֵ - ֵǰֵ - **************************************/ -uint32_t IWDT_GetValue(void) -{ - return (uint32_t)IWDT->VALUE.VALUE; -} - -/************************************* - IWDT_GetFlagStatus - ȡWDTж״̬ - ֵ - ֵSET/RESET - **************************************/ -FlagStatus IWDT_GetFlagStatus(void) -{ - FlagStatus bitstatus = RESET; - - if (IWDT->RIS.WDTIF != RESET) - bitstatus = SET; - - return bitstatus; -} - -/************************************* - IWDT_GetITStatus - ȡWDTʹж״̬ - ֵ - ֵSET/RESET - **************************************/ -FlagStatus IWDT_GetITStatus(void) -{ - FlagStatus bitstatus = RESET; - - if (IWDT->CON.IE != RESET) - bitstatus = SET; - - return bitstatus; -} - -/************************************* - WWDT_Init - WWDTʼ - ֵʼṹ - ֵ - **************************************/ -void WWDT_Init(WWDT_InitStruType *WDT_InitStruct) -{ - uint32_t tmp; - - if (WDT_InitStruct->WDT_Clock != WDT_CLOCK_PCLK) - tmp = (uint32_t)(32 * WDT_InitStruct->WDT_Tms); - else - tmp = SystemCoreClock / 1000 * WDT_InitStruct->WDT_Tms; - - WWDT->LOAD.LOAD = tmp; - WWDT->CON.CLKS = WDT_InitStruct->WDT_Clock; - WWDT->CON.IE = WDT_InitStruct->WDT_IE; - WWDT->CON.RSTEN = WDT_InitStruct->WDT_Rst; - WWDT->CON.WWDTWIN = WDT_InitStruct->WDT_Win; - - return; -} - -/************************************* - WWDT_SetReloadValue - WDTصijֵ - ֵʼֵ32-bit޷ - ֵ - **************************************/ -void WWDT_SetReloadValue(uint32_t Value) -{ - WWDT->LOAD.LOAD = Value; - return; -} - -/************************************* - WWDT_GetValue - ȡWDTǰֵ - ֵ - ֵǰֵ - **************************************/ -uint32_t WWDT_GetValue(void) -{ - return (uint32_t)WWDT->VALUE.VALUE; -} - -/************************************* - WWDT_GetFlagStatus - ȡWDTж״̬ - ֵ - ֵSET/RESET - **************************************/ -FlagStatus WWDT_GetFlagStatus(void) -{ - FlagStatus bitstatus = RESET; - - if (WWDT->RIS.WWDTIF != RESET) - bitstatus = SET; - - return bitstatus; -} - -/************************************* - WWDT_GetIEStatus - ȡWDTжʹ״̬ - ֵ - ֵSET/RESET - **************************************/ -FlagStatus WWDT_GetITStatus(void) -{ - FlagStatus bitstatus = RESET; - - if (WWDT->CON.IE != RESET) - bitstatus = SET; - - return bitstatus; -} - -/*************************END OF FILE**********************/ - - diff --git a/bsp/essemi/es8p508x/libraries/SConscript b/bsp/essemi/es8p508x/libraries/SConscript deleted file mode 100644 index e67dc9e4e3..0000000000 --- a/bsp/essemi/es8p508x/libraries/SConscript +++ /dev/null @@ -1,27 +0,0 @@ -import rtconfig -Import('RTT_ROOT') -from building import * - -# get current directory -cwd = GetCurrentDir() - -# The set of source files associated with this SConscript file. -src = [] - -src += Glob('Library/Source/*.c') -src += ['CMSIS/system_ES8P508x.c'] - -#add for startup script -if rtconfig.CROSS_TOOL == 'gcc': - src = src -elif rtconfig.CROSS_TOOL == 'keil': - src = src + ['CMSIS/startup_ES8P508x.s'] -elif rtconfig.CROSS_TOOL == 'iar': - src = src - -path = [cwd + '/CMSIS', - cwd + '/Library/Include',] - -group = DefineGroup('Libraries', src, depend = [''], CPPPATH = path) - -Return('group') -- cgit v1.3.1 From 7f97f62a94aa9688b6b00edaf15daa743777cfa4 Mon Sep 17 00:00:00 2001 From: liuhy Date: Fri, 10 Sep 2021 17:59:34 +0800 Subject: delete essemi bsp es8p508x (all) --- bsp/essemi/es8p508x/.config | 405 ----------- bsp/essemi/es8p508x/Kconfig | 27 - bsp/essemi/es8p508x/README.md | 91 --- bsp/essemi/es8p508x/SConscript | 14 - bsp/essemi/es8p508x/SConstruct | 39 - bsp/essemi/es8p508x/applications/SConscript | 9 - bsp/essemi/es8p508x/applications/main.c | 34 - bsp/essemi/es8p508x/drivers/Kconfig | 51 -- bsp/essemi/es8p508x/drivers/SConscript | 21 - bsp/essemi/es8p508x/drivers/board.c | 120 ---- bsp/essemi/es8p508x/drivers/board.h | 35 - bsp/essemi/es8p508x/drivers/drv_gpio.c | 479 ------------- bsp/essemi/es8p508x/drivers/drv_gpio.h | 16 - bsp/essemi/es8p508x/drivers/drv_uart.c | 444 ------------ bsp/essemi/es8p508x/drivers/drv_uart.h | 16 - .../es8p508x/drivers/linker_scripts/link.sct | 15 - bsp/essemi/es8p508x/figures/ESLinkII-mini.jpg | Bin 1807119 -> 0 bytes .../es8p508x/figures/HRSDK-GDB-ES8P508x-V1.0.jpg | Bin 2153855 -> 0 bytes bsp/essemi/es8p508x/project.uvopt | 174 ----- bsp/essemi/es8p508x/project.uvproj | 790 --------------------- bsp/essemi/es8p508x/rtconfig.h | 162 ----- bsp/essemi/es8p508x/rtconfig.py | 135 ---- bsp/essemi/es8p508x/template.uvopt | 174 ----- bsp/essemi/es8p508x/template.uvproj | 400 ----------- 24 files changed, 3651 deletions(-) delete mode 100644 bsp/essemi/es8p508x/.config delete mode 100644 bsp/essemi/es8p508x/Kconfig delete mode 100644 bsp/essemi/es8p508x/README.md delete mode 100644 bsp/essemi/es8p508x/SConscript delete mode 100644 bsp/essemi/es8p508x/SConstruct delete mode 100644 bsp/essemi/es8p508x/applications/SConscript delete mode 100644 bsp/essemi/es8p508x/applications/main.c delete mode 100644 bsp/essemi/es8p508x/drivers/Kconfig delete mode 100644 bsp/essemi/es8p508x/drivers/SConscript delete mode 100644 bsp/essemi/es8p508x/drivers/board.c delete mode 100644 bsp/essemi/es8p508x/drivers/board.h delete mode 100644 bsp/essemi/es8p508x/drivers/drv_gpio.c delete mode 100644 bsp/essemi/es8p508x/drivers/drv_gpio.h delete mode 100644 bsp/essemi/es8p508x/drivers/drv_uart.c delete mode 100644 bsp/essemi/es8p508x/drivers/drv_uart.h delete mode 100644 bsp/essemi/es8p508x/drivers/linker_scripts/link.sct delete mode 100644 bsp/essemi/es8p508x/figures/ESLinkII-mini.jpg delete mode 100644 bsp/essemi/es8p508x/figures/HRSDK-GDB-ES8P508x-V1.0.jpg delete mode 100644 bsp/essemi/es8p508x/project.uvopt delete mode 100644 bsp/essemi/es8p508x/project.uvproj delete mode 100644 bsp/essemi/es8p508x/rtconfig.h delete mode 100644 bsp/essemi/es8p508x/rtconfig.py delete mode 100644 bsp/essemi/es8p508x/template.uvopt delete mode 100644 bsp/essemi/es8p508x/template.uvproj (limited to 'bsp') diff --git a/bsp/essemi/es8p508x/.config b/bsp/essemi/es8p508x/.config deleted file mode 100644 index ff8ee21d05..0000000000 --- a/bsp/essemi/es8p508x/.config +++ /dev/null @@ -1,405 +0,0 @@ -# -# Automatically generated file; DO NOT EDIT. -# RT-Thread Configuration -# - -# -# RT-Thread Kernel -# -CONFIG_RT_NAME_MAX=8 -# CONFIG_RT_USING_ARCH_DATA_TYPE is not set -# CONFIG_RT_USING_SMP is not set -CONFIG_RT_ALIGN_SIZE=4 -# CONFIG_RT_THREAD_PRIORITY_8 is not set -CONFIG_RT_THREAD_PRIORITY_32=y -# CONFIG_RT_THREAD_PRIORITY_256 is not set -CONFIG_RT_THREAD_PRIORITY_MAX=32 -CONFIG_RT_TICK_PER_SECOND=100 -CONFIG_RT_USING_OVERFLOW_CHECK=y -CONFIG_RT_USING_HOOK=y -CONFIG_RT_USING_IDLE_HOOK=y -CONFIG_RT_IDLE_HOOK_LIST_SIZE=4 -CONFIG_IDLE_THREAD_STACK_SIZE=256 -# CONFIG_RT_USING_TIMER_SOFT is not set -CONFIG_RT_DEBUG=y -# CONFIG_RT_DEBUG_COLOR is not set -# CONFIG_RT_DEBUG_INIT_CONFIG is not set -# CONFIG_RT_DEBUG_THREAD_CONFIG is not set -# CONFIG_RT_DEBUG_SCHEDULER_CONFIG is not set -# CONFIG_RT_DEBUG_IPC_CONFIG is not set -# CONFIG_RT_DEBUG_TIMER_CONFIG is not set -# CONFIG_RT_DEBUG_IRQ_CONFIG is not set -# CONFIG_RT_DEBUG_MEM_CONFIG is not set -# CONFIG_RT_DEBUG_SLAB_CONFIG is not set -# CONFIG_RT_DEBUG_MEMHEAP_CONFIG is not set -# CONFIG_RT_DEBUG_MODULE_CONFIG is not set - -# -# Inter-Thread communication -# -CONFIG_RT_USING_SEMAPHORE=y -CONFIG_RT_USING_MUTEX=y -CONFIG_RT_USING_EVENT=y -CONFIG_RT_USING_MAILBOX=y -CONFIG_RT_USING_MESSAGEQUEUE=y -# CONFIG_RT_USING_SIGNALS is not set - -# -# Memory Management -# -CONFIG_RT_USING_MEMPOOL=y -# CONFIG_RT_USING_MEMHEAP is not set -# CONFIG_RT_USING_NOHEAP is not set -CONFIG_RT_USING_SMALL_MEM=y -# CONFIG_RT_USING_SLAB is not set -# CONFIG_RT_USING_MEMTRACE is not set -CONFIG_RT_USING_HEAP=y - -# -# Kernel Device Object -# -CONFIG_RT_USING_DEVICE=y -# CONFIG_RT_USING_DEVICE_OPS is not set -# CONFIG_RT_USING_INTERRUPT_INFO is not set -CONFIG_RT_USING_CONSOLE=y -CONFIG_RT_CONSOLEBUF_SIZE=128 -CONFIG_RT_CONSOLE_DEVICE_NAME="uart5" -CONFIG_RT_VER_NUM=0x40002 -# CONFIG_RT_USING_CPU_FFS is not set -# CONFIG_ARCH_CPU_STACK_GROWS_UPWARD is not set - -# -# RT-Thread Components -# -CONFIG_RT_USING_COMPONENTS_INIT=y -CONFIG_RT_USING_USER_MAIN=y -CONFIG_RT_MAIN_THREAD_STACK_SIZE=2048 -CONFIG_RT_MAIN_THREAD_PRIORITY=10 - -# -# C++ features -# -# CONFIG_RT_USING_CPLUSPLUS is not set - -# -# Command shell -# -CONFIG_RT_USING_FINSH=y -CONFIG_FINSH_THREAD_NAME="tshell" -CONFIG_FINSH_USING_HISTORY=y -CONFIG_FINSH_HISTORY_LINES=5 -CONFIG_FINSH_USING_SYMTAB=y -CONFIG_FINSH_USING_DESCRIPTION=y -# CONFIG_FINSH_ECHO_DISABLE_DEFAULT is not set -CONFIG_FINSH_THREAD_PRIORITY=20 -CONFIG_FINSH_THREAD_STACK_SIZE=2048 -CONFIG_FINSH_CMD_SIZE=80 -# CONFIG_FINSH_USING_AUTH is not set -CONFIG_FINSH_USING_MSH=y -CONFIG_FINSH_USING_MSH_DEFAULT=y -CONFIG_FINSH_USING_MSH_ONLY=y -CONFIG_FINSH_ARG_MAX=10 - -# -# Device virtual file system -# -# CONFIG_RT_USING_DFS is not set - -# -# Device Drivers -# -CONFIG_RT_USING_DEVICE_IPC=y -CONFIG_RT_PIPE_BUFSZ=512 -# CONFIG_RT_USING_SYSTEM_WORKQUEUE is not set -CONFIG_RT_USING_SERIAL=y -# CONFIG_RT_SERIAL_USING_DMA is not set -CONFIG_RT_SERIAL_RB_BUFSZ=64 -# CONFIG_RT_USING_CAN is not set -# CONFIG_RT_USING_HWTIMER is not set -# CONFIG_RT_USING_CPUTIME is not set -# CONFIG_RT_USING_I2C is not set -CONFIG_RT_USING_PIN=y -# CONFIG_RT_USING_ADC is not set -# CONFIG_RT_USING_PWM is not set -# CONFIG_RT_USING_MTD_NOR is not set -# CONFIG_RT_USING_MTD_NAND is not set -# CONFIG_RT_USING_PM is not set -# CONFIG_RT_USING_RTC is not set -# CONFIG_RT_USING_SDIO is not set -# CONFIG_RT_USING_SPI is not set -# CONFIG_RT_USING_WDT is not set -# CONFIG_RT_USING_AUDIO is not set -# CONFIG_RT_USING_SENSOR is not set -# CONFIG_RT_USING_TOUCH is not set -# CONFIG_RT_USING_HWCRYPTO is not set -# CONFIG_RT_USING_PULSE_ENCODER is not set -# CONFIG_RT_USING_INPUT_CAPTURE is not set -# CONFIG_RT_USING_WIFI is not set - -# -# Using USB -# -# CONFIG_RT_USING_USB_HOST is not set -# CONFIG_RT_USING_USB_DEVICE is not set - -# -# POSIX layer and C standard library -# -# CONFIG_RT_USING_LIBC is not set -# CONFIG_RT_USING_PTHREADS is not set -# CONFIG_RT_LIBC_USING_TIME is not set - -# -# Network -# - -# -# Socket abstraction layer -# -# CONFIG_RT_USING_SAL is not set - -# -# Network interface device -# -# CONFIG_RT_USING_NETDEV is not set - -# -# light weight TCP/IP stack -# -# CONFIG_RT_USING_LWIP is not set - -# -# AT commands -# -# CONFIG_RT_USING_AT is not set - -# -# VBUS(Virtual Software BUS) -# -# CONFIG_RT_USING_VBUS is not set - -# -# Utilities -# -# CONFIG_RT_USING_RYM is not set -# CONFIG_RT_USING_ULOG is not set -# CONFIG_RT_USING_UTEST is not set - -# -# RT-Thread online packages -# - -# -# IoT - internet of things -# -# CONFIG_PKG_USING_PAHOMQTT is not set -# CONFIG_PKG_USING_WEBCLIENT is not set -# CONFIG_PKG_USING_WEBNET is not set -# CONFIG_PKG_USING_MONGOOSE is not set -# CONFIG_PKG_USING_MYMQTT is not set -# CONFIG_PKG_USING_WEBTERMINAL is not set -# CONFIG_PKG_USING_CJSON is not set -# CONFIG_PKG_USING_JSMN is not set -# CONFIG_PKG_USING_LIBMODBUS is not set -# CONFIG_PKG_USING_FREEMODBUS is not set -# CONFIG_PKG_USING_LJSON is not set -# CONFIG_PKG_USING_EZXML is not set -# CONFIG_PKG_USING_NANOPB is not set - -# -# Wi-Fi -# - -# -# Marvell WiFi -# -# CONFIG_PKG_USING_WLANMARVELL is not set - -# -# Wiced WiFi -# -# CONFIG_PKG_USING_WLAN_WICED is not set -# CONFIG_PKG_USING_RW007 is not set -# CONFIG_PKG_USING_COAP is not set -# CONFIG_PKG_USING_NOPOLL is not set -# CONFIG_PKG_USING_NETUTILS is not set -# CONFIG_PKG_USING_PPP_DEVICE is not set -# CONFIG_PKG_USING_AT_DEVICE is not set -# CONFIG_PKG_USING_ATSRV_SOCKET is not set -# CONFIG_PKG_USING_WIZNET is not set - -# -# IoT Cloud -# -# CONFIG_PKG_USING_ONENET is not set -# CONFIG_PKG_USING_GAGENT_CLOUD is not set -# CONFIG_PKG_USING_ALI_IOTKIT is not set -# CONFIG_PKG_USING_AZURE is not set -# CONFIG_PKG_USING_TENCENT_IOTHUB is not set -# CONFIG_PKG_USING_JIOT-C-SDK is not set -# CONFIG_PKG_USING_NIMBLE is not set -# CONFIG_PKG_USING_OTA_DOWNLOADER is not set -# CONFIG_PKG_USING_IPMSG is not set -# CONFIG_PKG_USING_LSSDP is not set -# CONFIG_PKG_USING_AIRKISS_OPEN is not set -# CONFIG_PKG_USING_LIBRWS is not set -# CONFIG_PKG_USING_TCPSERVER is not set -# CONFIG_PKG_USING_PROTOBUF_C is not set -# CONFIG_PKG_USING_ONNX_PARSER is not set -# CONFIG_PKG_USING_ONNX_BACKEND is not set -# CONFIG_PKG_USING_DLT645 is not set -# CONFIG_PKG_USING_QXWZ is not set -# CONFIG_PKG_USING_SMTP_CLIENT is not set -# CONFIG_PKG_USING_ABUP_FOTA is not set - -# -# security packages -# -# CONFIG_PKG_USING_MBEDTLS is not set -# CONFIG_PKG_USING_libsodium is not set -# CONFIG_PKG_USING_TINYCRYPT is not set - -# -# language packages -# -# CONFIG_PKG_USING_LUA is not set -# CONFIG_PKG_USING_JERRYSCRIPT is not set -# CONFIG_PKG_USING_MICROPYTHON is not set - -# -# multimedia packages -# -# CONFIG_PKG_USING_OPENMV is not set -# CONFIG_PKG_USING_MUPDF is not set -# CONFIG_PKG_USING_STEMWIN is not set -# CONFIG_PKG_USING_WAVPLAYER is not set -# CONFIG_PKG_USING_TJPGD is not set - -# -# tools packages -# -# CONFIG_PKG_USING_CMBACKTRACE is not set -# CONFIG_PKG_USING_EASYFLASH is not set -# CONFIG_PKG_USING_EASYLOGGER is not set -# CONFIG_PKG_USING_SYSTEMVIEW is not set -# CONFIG_PKG_USING_RDB is not set -# CONFIG_PKG_USING_QRCODE is not set -# CONFIG_PKG_USING_ULOG_EASYFLASH is not set -# CONFIG_PKG_USING_ADBD is not set -# CONFIG_PKG_USING_COREMARK is not set -# CONFIG_PKG_USING_DHRYSTONE is not set -# CONFIG_PKG_USING_NR_MICRO_SHELL is not set - -# -# system packages -# -# CONFIG_PKG_USING_GUIENGINE is not set -# CONFIG_PKG_USING_CAIRO is not set -# CONFIG_PKG_USING_PIXMAN is not set -# CONFIG_PKG_USING_LWEXT4 is not set -# CONFIG_PKG_USING_PARTITION is not set -# CONFIG_PKG_USING_FAL is not set -# CONFIG_PKG_USING_SQLITE is not set -# CONFIG_PKG_USING_RTI is not set -# CONFIG_PKG_USING_LITTLEVGL2RTT is not set -# CONFIG_PKG_USING_CMSIS is not set -# CONFIG_PKG_USING_DFS_YAFFS is not set -# CONFIG_PKG_USING_LITTLEFS is not set -# CONFIG_PKG_USING_THREAD_POOL is not set -# CONFIG_PKG_USING_ROBOTS is not set - -# -# peripheral libraries and drivers -# -# CONFIG_PKG_USING_SENSORS_DRIVERS is not set -# CONFIG_PKG_USING_REALTEK_AMEBA is not set -# CONFIG_PKG_USING_SHT2X is not set -# CONFIG_PKG_USING_SHT3X is not set -# CONFIG_PKG_USING_STM32_SDIO is not set -# CONFIG_PKG_USING_ICM20608 is not set -# CONFIG_PKG_USING_U8G2 is not set -# CONFIG_PKG_USING_BUTTON is not set -# CONFIG_PKG_USING_PCF8574 is not set -# CONFIG_PKG_USING_SX12XX is not set -# CONFIG_PKG_USING_SIGNAL_LED is not set -# CONFIG_PKG_USING_LEDBLINK is not set -# CONFIG_PKG_USING_WM_LIBRARIES is not set -# CONFIG_PKG_USING_KENDRYTE_SDK is not set -# CONFIG_PKG_USING_INFRARED is not set -# CONFIG_PKG_USING_ROSSERIAL is not set -# CONFIG_PKG_USING_AGILE_BUTTON is not set -# CONFIG_PKG_USING_AGILE_LED is not set -# CONFIG_PKG_USING_AT24CXX is not set -# CONFIG_PKG_USING_MOTIONDRIVER2RTT is not set -# CONFIG_PKG_USING_AD7746 is not set -# CONFIG_PKG_USING_PCA9685 is not set -# CONFIG_PKG_USING_I2C_TOOLS is not set -# CONFIG_PKG_USING_NRF24L01 is not set -# CONFIG_PKG_USING_TOUCH_DRIVERS is not set -# CONFIG_PKG_USING_LCD_DRIVERS is not set -# CONFIG_PKG_USING_MAX17048 is not set -# CONFIG_PKG_USING_RPLIDAR is not set - -# -# miscellaneous packages -# -# CONFIG_PKG_USING_LIBCSV is not set -# CONFIG_PKG_USING_OPTPARSE is not set -# CONFIG_PKG_USING_FASTLZ is not set -# CONFIG_PKG_USING_MINILZO is not set -# CONFIG_PKG_USING_QUICKLZ is not set -# CONFIG_PKG_USING_MULTIBUTTON is not set -# CONFIG_PKG_USING_FLEXIBLE_BUTTON is not set -# CONFIG_PKG_USING_CANFESTIVAL is not set -# CONFIG_PKG_USING_ZLIB is not set -# CONFIG_PKG_USING_DSTR is not set -# CONFIG_PKG_USING_TINYFRAME is not set -# CONFIG_PKG_USING_KENDRYTE_DEMO is not set -# CONFIG_PKG_USING_DIGITALCTRL is not set -# CONFIG_PKG_USING_UPACKER is not set -# CONFIG_PKG_USING_UPARAM is not set - -# -# samples: kernel and components samples -# -# CONFIG_PKG_USING_KERNEL_SAMPLES is not set -# CONFIG_PKG_USING_FILESYSTEM_SAMPLES is not set -# CONFIG_PKG_USING_NETWORK_SAMPLES is not set -# CONFIG_PKG_USING_PERIPHERAL_SAMPLES is not set -# CONFIG_PKG_USING_HELLO is not set -# CONFIG_PKG_USING_VI is not set -# CONFIG_PKG_USING_NNOM is not set -# CONFIG_PKG_USING_LIBANN is not set -# CONFIG_PKG_USING_ELAPACK is not set -# CONFIG_PKG_USING_ARMv7M_DWT is not set -# CONFIG_PKG_USING_VT100 is not set -# CONFIG_PKG_USING_ULAPACK is not set -# CONFIG_PKG_USING_UKAL is not set -CONFIG_SOC_ES8P508x=y - -# -# Hardware Drivers Config -# - -# -# On-chip Peripheral Drivers -# -CONFIG_BSP_USING_GPIO=y - -# -# UART Drivers -# -# CONFIG_BSP_USING_UART0 is not set -# CONFIG_BSP_USING_UART1 is not set -# CONFIG_BSP_USING_UART2 is not set -# CONFIG_BSP_USING_UART3 is not set -# CONFIG_BSP_USING_UART4 is not set -CONFIG_BSP_USING_UART5=y - -# -# Onboard Peripheral Drivers -# - -# -# Offboard Peripheral Drivers -# diff --git a/bsp/essemi/es8p508x/Kconfig b/bsp/essemi/es8p508x/Kconfig deleted file mode 100644 index 57778bdbef..0000000000 --- a/bsp/essemi/es8p508x/Kconfig +++ /dev/null @@ -1,27 +0,0 @@ -mainmenu "RT-Thread Configuration" - -config BSP_DIR - string - option env="BSP_ROOT" - default "." - -config RTT_DIR - string - option env="RTT_ROOT" - default "../../.." - -config PKGS_DIR - string - option env="PKGS_ROOT" - default "packages" - -source "$RTT_DIR/Kconfig" -source "$PKGS_DIR/Kconfig" - -config SOC_ES8P508x - bool - select RT_USING_COMPONENTS_INIT - select RT_USING_USER_MAIN - default y - -source "drivers/Kconfig" diff --git a/bsp/essemi/es8p508x/README.md b/bsp/essemi/es8p508x/README.md deleted file mode 100644 index 68c95b3ede..0000000000 --- a/bsp/essemi/es8p508x/README.md +++ /dev/null @@ -1,91 +0,0 @@ -# HRSDK-GDB-ES8P508 开发板 BSP 说明 -标签： EastSoft、国产MCU、Cortex-M0、ES8P5088FLLQ - -## 1. 简介 - -本文档为上海东软载波微电子开发团队为 HRSDK-GDB-ES8P508 开发板提供的 BSP (板级支持包) 说明。 -通过阅读本文档，开发者可以快速地上手该 BSP，将 RT-Thread 运行在开发板上。 - -### 1.1 开发板介绍 - -主要内容如下： -HRSDK-GDB-ES8P508x 是东软载波微电子官方推出的一款基于 ARM Cortex-M0 内核的开发板，最高主频为 48MHz，可满足基础功能测试及高端功能扩展等开发需求。 - -开发板外观如下图所示： - -HRSDK-GDB-ES8P508x-V1.0 - -![ES8P508](figures/HRSDK-GDB-ES8P508x-V1.0.jpg) - -该开发板常用 **板载资源** 如下： - -- MCU：ES8P5088FLLQ，主频 48MHz，24KB SRAM，128KB FLASH，45 GPIOs -- 常用外设 - - LED：1个，(PA14) - - 按键：1个(MRSTN) -- 常用接口：GPIO、UART、SPI、I2C -- 调试接口，ESLinkⅡ(EastSoft 官方推出的开发工具，有标准版和mini版两种版本，均自带 CDC 串口功能) SWD 下载 - -外设支持: - -本 BSP 目前对外设的支持情况如下： - -| **片上外设** | **支持情况** | **备注** | -| :---------------- | :----------: | :-----------------------------------| -| GPIO | 支持 | 45 GPIOs | -| UART | 支持 | UART0/1/2/3/4/5 | - - -更多详细信息请咨询[上海东软载波微电子技术支持](http://www.essemi.com/) - -## 2. 快速上手 - -本 BSP 为开发者提供 MDK4 工程。下面以 MDK4 开发环境为例，介绍如何将系统运行起来。 - -### 硬件连接 - -使用 ESLinkⅡ (自带 CDC 串口)或 Jlink 等调试工具连接开发板到 PC，拨动开关选择使用调试工具供电或使用外部电源供电。若使用 Jlink 等调试工具，还需要将 UART5_TX(PB13)、UART5_RX(PB12)、GND 接到串口工具上。 - -使用ESlinkⅡ(mini)连接开发板如下图所示： - -ESLinkⅡ(mini) + HRSDK-GDB-ES8P508-V1.0 - -![ESLinkII](figures/ESLinkII-mini.jpg) - -### 编译下载 - -双击 project.uvprojx 文件，打开 MDK4 工程，工程默认配置使用 JLink 下载程序，在通过 JLink 连接开发板的基础上，点击下载按钮即可下载程序到开发板，如果使用 ESLinkⅡ，则选择 "CMSIS-DAP Debugger"，连接正常后即可编译并下载程序到开发板。 - -### 运行结果 - -下载程序成功之后，系统会自动运行，观察串口输出的信息，同时开发板LED闪烁。 - -```bash - \ | / -- RT - Thread Operating System - / | \ 4.0.2 build Jul 12 2019 - 2006 - 2019 Copyright by rt-thread team -msh /> -``` -## 3. 进阶使用 - -此 BSP 默认只开启了 GPIO 和 uart5 的功能，如果需使用 SPI 等更多高级功能，需要利用 ENV 工具对 BSP 进行配置，步骤如下： - -1. 在 bsp 下打开 env 工具。 - -2. 输入`menuconfig`命令配置工程，配置好之后保存退出。 - -3. 输入`pkgs --update`命令更新软件包。 - -4. 输入`scons --target=MDK4` 命令重新生成工程。 - -更多 Env 工具的详细介绍请参考 [RT-Thread 文档中心](https://www.rt-thread.org/document/site/) - -## 4. 联系人信息 - -- [wangyongquan](https://github.com/wangyq2018) - -## 5. 参考 - -- [ EastSoft 官网](http://www.essemi.com) - diff --git a/bsp/essemi/es8p508x/SConscript b/bsp/essemi/es8p508x/SConscript deleted file mode 100644 index 11d722608a..0000000000 --- a/bsp/essemi/es8p508x/SConscript +++ /dev/null @@ -1,14 +0,0 @@ -# RT-Thread SConscript bridge -import os -from building import * - -objs = [] -cwd = GetCurrentDir() -list = os.listdir(cwd) - -for d in list: - path = os.path.join(cwd, d) - if os.path.isfile(os.path.join(path, 'SConscript')): - objs = objs + SConscript(os.path.join(d, 'SConscript')) - -Return('objs') diff --git a/bsp/essemi/es8p508x/SConstruct b/bsp/essemi/es8p508x/SConstruct deleted file mode 100644 index 164265293d..0000000000 --- a/bsp/essemi/es8p508x/SConstruct +++ /dev/null @@ -1,39 +0,0 @@ -import os -import sys -import rtconfig - -if os.getenv('RTT_ROOT'): - RTT_ROOT = os.getenv('RTT_ROOT') -else: - RTT_ROOT = os.path.normpath(os.getcwd() + '/../../..') - -sys.path = sys.path + [os.path.join(RTT_ROOT, 'tools')] -try: - from building import * -except: - print('Cannot found RT-Thread root directory, please check RTT_ROOT') - print(RTT_ROOT) - exit(-1) - -TARGET = 'rtthread.' + rtconfig.TARGET_EXT - -env = Environment(tools = ['mingw'], - AS = rtconfig.AS, ASFLAGS = rtconfig.AFLAGS, - CC = rtconfig.CC, CCFLAGS = rtconfig.CFLAGS, - AR = rtconfig.AR, ARFLAGS = '-rc', - LINK = rtconfig.LINK, LINKFLAGS = rtconfig.LFLAGS) -env.PrependENVPath('PATH', rtconfig.EXEC_PATH) - -if rtconfig.PLATFORM == 'iar': - env.Replace(CCCOM = ['$CC $CCFLAGS $CPPFLAGS $_CPPDEFFLAGS $_CPPINCFLAGS -o $TARGET $SOURCES']) - env.Replace(ARFLAGS = ['']) - env.Replace(LINKCOM = env["LINKCOM"] + ' --map project.map') - -Export('RTT_ROOT') -Export('rtconfig') - -# prepare building environment -objs = PrepareBuilding(env, RTT_ROOT, has_libcpu=False) - -# make a building -DoBuilding(TARGET, objs) diff --git a/bsp/essemi/es8p508x/applications/SConscript b/bsp/essemi/es8p508x/applications/SConscript deleted file mode 100644 index 51b0290a69..0000000000 --- a/bsp/essemi/es8p508x/applications/SConscript +++ /dev/null @@ -1,9 +0,0 @@ -from building import * - -cwd = GetCurrentDir() -src = Glob('*.c') - -CPPPATH = [cwd] -group = DefineGroup('Applications', src, depend = [''], CPPPATH = CPPPATH) - -Return('group') diff --git a/bsp/essemi/es8p508x/applications/main.c b/bsp/essemi/es8p508x/applications/main.c deleted file mode 100644 index 6494a970b5..0000000000 --- a/bsp/essemi/es8p508x/applications/main.c +++ /dev/null @@ -1,34 +0,0 @@ -/* - * Copyright (C) 2018 Shanghai Eastsoft Microelectronics Co., Ltd. - * - * SPDX-License-Identifier: Apache-2.0 - * - * Change Logs: - * Date Author Notes - * 2019-07-12 wangyq the first version - */ - -#include -#include -#include - -#define LED_PIN 29 - -int main(void) -{ - int count = 1; - - /* set PA14 pin mode to output */ - rt_pin_mode(LED_PIN, PIN_MODE_OUTPUT); - - while (count++) - { - rt_pin_write(LED_PIN, PIN_HIGH); - rt_thread_mdelay(500); - rt_pin_write(LED_PIN, PIN_LOW); - rt_thread_mdelay(500); - } - - return RT_EOK; -} - diff --git a/bsp/essemi/es8p508x/drivers/Kconfig b/bsp/essemi/es8p508x/drivers/Kconfig deleted file mode 100644 index 98a7d173b3..0000000000 --- a/bsp/essemi/es8p508x/drivers/Kconfig +++ /dev/null @@ -1,51 +0,0 @@ -menu "Hardware Drivers Config" - - menu "On-chip Peripheral Drivers" - config BSP_USING_GPIO - bool "Enable GPIO" - select RT_USING_PIN - default y - - menu "UART Drivers" - config BSP_USING_UART0 - bool "Enable UART0 PB00/PB01(R/T)" - select RT_USING_SERIAL - default n - - config BSP_USING_UART1 - bool "Enable UART1 PA18/PA17(R/T)" - select RT_USING_SERIAL - default n - - config BSP_USING_UART2 - bool "Enable UART2 PA04/PA05(R/T)" - select RT_USING_SERIAL - default n - - config BSP_USING_UART3 - bool "Enable UART3 PA30/PA29(R/T)" - select RT_USING_SERIAL - default n - - config BSP_USING_UART4 - bool "Enable UART4 PB10/PB11(R/T)" - select RT_USING_SERIAL - default n - - config BSP_USING_UART5 - bool "Enable UART5 PB12/PB13(R/T)" - select RT_USING_SERIAL - default y - endmenu - - endmenu - - menu "Onboard Peripheral Drivers" - - endmenu - - menu "Offboard Peripheral Drivers" - - endmenu - -endmenu diff --git a/bsp/essemi/es8p508x/drivers/SConscript b/bsp/essemi/es8p508x/drivers/SConscript deleted file mode 100644 index f2b341e073..0000000000 --- a/bsp/essemi/es8p508x/drivers/SConscript +++ /dev/null @@ -1,21 +0,0 @@ -from building import * - -cwd = GetCurrentDir() - -# add the general drivers. -src = Split(''' -board.c -''') - -# add gpio code -if GetDepend('RT_USING_PIN'): - src += ['drv_gpio.c'] - -# add serial driver code -if GetDepend('BSP_USING_UART0') or GetDepend('BSP_USING_UART1') or GetDepend('BSP_USING_UART2') or GetDepend('BSP_USING_UART3') or GetDepend('BSP_USING_UART4') or GetDepend('BSP_USING_UART5'): - src += ['drv_uart.c'] - -CPPPATH = [cwd] -group = DefineGroup('Drivers', src, depend = [''], CPPPATH = CPPPATH) - -Return('group') diff --git a/bsp/essemi/es8p508x/drivers/board.c b/bsp/essemi/es8p508x/drivers/board.c deleted file mode 100644 index b013fa327c..0000000000 --- a/bsp/essemi/es8p508x/drivers/board.c +++ /dev/null @@ -1,120 +0,0 @@ -/* - * Copyright (C) 2018 Shanghai Eastsoft Microelectronics Co., Ltd. - * - * SPDX-License-Identifier: Apache-2.0 - * - * Change Logs: - * Date Author Notes - * 2019-07-11 wangyq the first version - */ - -#include -#include -#include "board.h" -#include "drv_uart.h" -#include "drv_gpio.h" -#include -#include - -/** - * @addtogroup es8p - */ - -/*@{*/ - -/******************************************************************************* -* Function Name : NVIC_Configuration -* Description : Configures Vector Table base location. -* Input : None -* Output : None -* Return : None -*******************************************************************************/ -void NVIC_Configuration(void) -{ -} - -/******************************************************************************* - * Function Name : SystemClock_Configuration - * Description : Configures the System Clock. - * Input : None - * Output : None - * Return : None - *******************************************************************************/ -void SystemClock_Config(void) -{ - /* system clock 48MHz */ - PLLClock_Config(ENABLE, SCU_PLL_HRC, SCU_PLL_48M, ENABLE); -} - -/******************************************************************************* - * Function Name : SysTick_Configuration - * Description : Configures the SysTick for OS tick. - * Input : None - * Output : None - * Return : None - *******************************************************************************/ -void SysTick_Configuration(void) -{ - /* ticks = SYS_CLK / RT_TICK_PER_SECOND */ - SysTick_Config(SystemCoreClock / RT_TICK_PER_SECOND); -} - -/** - * This is the timer interrupt service routine. - * - */ -void systick_irq_cbk(void) -{ - /* enter interrupt */ - rt_interrupt_enter(); - - rt_tick_increase(); - - /* leave interrupt */ - rt_interrupt_leave(); -} - -/*@}*/ -/** - * This function will initial es8p board. - */ -void rt_hw_board_init(void) -{ - /* NVIC Configuration */ - NVIC_Configuration(); - - /*System Clock Configuration */ - SystemClock_Config(); - - /* Configure the SysTick */ - SysTick_Configuration(); - -#ifdef RT_USING_HEAP - rt_system_heap_init((void *)HEAP_BEGIN, (void *)HEAP_END); -#endif -#ifdef RT_USING_COMPONENTS_INIT - rt_components_board_init(); -#endif -#ifdef RT_USING_CONSOLE - rt_console_set_device(RT_CONSOLE_DEVICE_NAME); -#endif -} - -/** - * This function will delay for some us. - * - * @param us the delay time of us - */ -void rt_hw_us_delay(rt_uint32_t us) -{ - unsigned int start, now, delta, reload, us_tick; - start = SysTick->VAL; - reload = SysTick->LOAD; - us_tick = SystemCoreClock / 1000000UL; - do - { - now = SysTick->VAL; - delta = start > now ? start - now : reload + start - now; - } - while (delta < us_tick * us); -} diff --git a/bsp/essemi/es8p508x/drivers/board.h b/bsp/essemi/es8p508x/drivers/board.h deleted file mode 100644 index 0dcfdd432f..0000000000 --- a/bsp/essemi/es8p508x/drivers/board.h +++ /dev/null @@ -1,35 +0,0 @@ -/* - * Copyright (C) 2018 Shanghai Eastsoft Microelectronics Co., Ltd. - * - * SPDX-License-Identifier: Apache-2.0 - * - * Change Logs: - * Date Author Notes - * 2019-07-11 wangyq the first version - */ - -// <<< Use Configuration Wizard in Context Menu >>> -#ifndef __BOARD_H__ -#define __BOARD_H__ - -#include - -#define ES8P_SRAM_SIZE 0x6000 -#define ES8P_SRAM_END (0x20000000 + ES8P_SRAM_SIZE) - -#if defined(__CC_ARM) || defined(__CLANG_ARM) - extern int Image$$RW_IRAM1$$ZI$$Limit; - #define HEAP_BEGIN ((void *)&Image$$RW_IRAM1$$ZI$$Limit) -#elif __ICCARM__ - #pragma section="HEAP" - #define HEAP_BEGIN (__segment_end("HEAP")) -#else - extern int __bss_end; - #define HEAP_BEGIN ((void *)&__bss_end) -#endif - -#define HEAP_END ES8P_SRAM_END - -void rt_hw_board_init(void); - -#endif diff --git a/bsp/essemi/es8p508x/drivers/drv_gpio.c b/bsp/essemi/es8p508x/drivers/drv_gpio.c deleted file mode 100644 index 9dfc09ef8e..0000000000 --- a/bsp/essemi/es8p508x/drivers/drv_gpio.c +++ /dev/null @@ -1,479 +0,0 @@ -/* - * Copyright (C) 2018 Shanghai Eastsoft Microelectronics Co., Ltd. - * - * SPDX-License-Identifier: Apache-2.0 - * - * Change Logs: - * Date Author Notes - * 2019-07-11 wangyq the first version - */ - -#include -#include -#include "board.h" -#include "drv_gpio.h" -#include -#include - -#ifdef RT_USING_PIN - -#define __ES8P_PIN(index, gpio, gpio_index) {index, GPIO##gpio, GPIO_Pin_##gpio_index} -#define __ES8P_PIN_DEFAULT {-1, GPIOA, GPIO_Pin_0} - -/* es8p GPIO driver */ -struct pin_index -{ - int index; - GPIO_TYPE gpio; - GPIO_TYPE_PIN pin; -}; - -static const struct pin_index pins[] = -{ - __ES8P_PIN_DEFAULT, - __ES8P_PIN(1, B, 0), - __ES8P_PIN(2, B, 1), - __ES8P_PIN(3, B, 2), - __ES8P_PIN(4, B, 3), - __ES8P_PIN(5, B, 4), - __ES8P_PIN(6, B, 5), - __ES8P_PIN(7, B, 6), - __ES8P_PIN(8, B, 7), - __ES8P_PIN(9, B, 8), - __ES8P_PIN(10, B, 9), - __ES8P_PIN(11, B, 10), - __ES8P_PIN(12, B, 11), - __ES8P_PIN(13, B, 12), - __ES8P_PIN(14, B, 13), - __ES8P_PIN(15, A, 0), - __ES8P_PIN(16, A, 1), - __ES8P_PIN(17, A, 2), - __ES8P_PIN(18, A, 3), - __ES8P_PIN(19, A, 4), - __ES8P_PIN(20, A, 5), - __ES8P_PIN(21, A, 6), - __ES8P_PIN(22, A, 7), - __ES8P_PIN(23, A, 8), - __ES8P_PIN(24, A, 9), - __ES8P_PIN(25, A, 10), - __ES8P_PIN(26, A, 11), - __ES8P_PIN(27, A, 12), - __ES8P_PIN(28, A, 13), - __ES8P_PIN(29, A, 14), - __ES8P_PIN(30, A, 15), - __ES8P_PIN(31, A, 16), - __ES8P_PIN_DEFAULT, - __ES8P_PIN_DEFAULT, - __ES8P_PIN(34, A, 17), - __ES8P_PIN(35, A, 18), - __ES8P_PIN_DEFAULT, - __ES8P_PIN(37, A, 20), - __ES8P_PIN(38, A, 21), - __ES8P_PIN(39, A, 22), - __ES8P_PIN(40, A, 23), - __ES8P_PIN(41, A, 24), - __ES8P_PIN(42, A, 25), - __ES8P_PIN(43, A, 26), - __ES8P_PIN(44, A, 27), - __ES8P_PIN(45, A, 28), - __ES8P_PIN(46, A, 29), - __ES8P_PIN(47, A, 30), - __ES8P_PIN(48, A, 31), -}; - -struct irq_map -{ - PINT_TYPE pinno; - IRQn_Type irqno; -}; -static const struct irq_map irq_map[] = -{ - {PINT0, PINT0_IRQn}, - {PINT1, PINT1_IRQn}, - {PINT2, PINT2_IRQn}, - {PINT3, PINT3_IRQn}, - {PINT4, PINT4_IRQn}, - {PINT5, PINT5_IRQn}, - {PINT6, PINT6_IRQn}, - {PINT7, PINT7_IRQn}, -}; - -struct rt_pin_irq_hdr pin_irq_hdr_tab[] = -{ - {-1, 0, RT_NULL, RT_NULL}, - {-1, 0, RT_NULL, RT_NULL}, - {-1, 0, RT_NULL, RT_NULL}, - {-1, 0, RT_NULL, RT_NULL}, - {-1, 0, RT_NULL, RT_NULL}, - {-1, 0, RT_NULL, RT_NULL}, - {-1, 0, RT_NULL, RT_NULL}, - {-1, 0, RT_NULL, RT_NULL}, -}; - -#define ITEM_NUM(items) sizeof(items) / sizeof(items[0]) -const struct pin_index *get_pin(uint8_t pin) -{ - const struct pin_index *index; - if (pin < ITEM_NUM(pins)) - { - index = &pins[pin]; - if (index->index == -1) - index = RT_NULL; - } - else - { - index = RT_NULL; - } - return index; -}; - -void es8p_pin_write(rt_device_t dev, rt_base_t pin, rt_base_t value) -{ - const struct pin_index *index; - index = get_pin(pin); - if (index == RT_NULL) - { - return; - } - - if (value == 0) - { - if (index->gpio == GPIOA) - GPIOA_ResetBit(index->pin); - else if (index->gpio == GPIOB) - GPIOB_ResetBit(index->pin); - } - else - { - if (index->gpio == GPIOA) - GPIOA_SetBit(index->pin); - else if (index->gpio == GPIOB) - GPIOB_SetBit(index->pin); - } -} - -int es8p_pin_read(rt_device_t dev, rt_base_t pin) -{ - int value; - const struct pin_index *index; - value = PIN_LOW; - index = get_pin(pin); - if (index == RT_NULL) - { - return value; - } - value = GPIO_ReadBit(index->gpio, index->pin); - return value; -} - -void es8p_pin_mode(rt_device_t dev, rt_base_t pin, rt_base_t mode) -{ - const struct pin_index *index; - GPIO_InitStruType gpio_initstruct; - index = get_pin(pin); - if (index == RT_NULL) - { - return; - } - - /* Configure GPIO_InitStructure */ - gpio_initstruct.GPIO_Signal = GPIO_Pin_Signal_Digital; - gpio_initstruct.GPIO_Func = GPIO_Func_0; - gpio_initstruct.GPIO_OD = GPIO_ODE_Output_Disable; - gpio_initstruct.GPIO_PUEN = GPIO_PUE_Input_Disable; - gpio_initstruct.GPIO_PDEN = GPIO_PDE_Input_Disable; - gpio_initstruct.GPIO_DS = GPIO_DS_Output_Normal; - - if (mode == PIN_MODE_OUTPUT) - { - /* output setting */ - gpio_initstruct.GPIO_Direction = GPIO_Dir_Out; - } - else if (mode == PIN_MODE_INPUT) - { - /* input setting: not pull. */ - gpio_initstruct.GPIO_Direction = GPIO_Dir_In; - } - else if (mode == PIN_MODE_INPUT_PULLUP) - { - /* input setting: pull up. */ - gpio_initstruct.GPIO_Direction = GPIO_Dir_In; - gpio_initstruct.GPIO_PUEN = GPIO_PUE_Input_Enable; - } - else if (mode == PIN_MODE_INPUT_PULLDOWN) - { - /* input setting: pull down. */ - gpio_initstruct.GPIO_Direction = GPIO_Dir_In; - gpio_initstruct.GPIO_PDEN = GPIO_PDE_Input_Enable; - } - else if (mode == PIN_MODE_OUTPUT_OD) - { - /* output setting: od. */ - gpio_initstruct.GPIO_Direction = GPIO_Dir_Out; - gpio_initstruct.GPIO_OD = GPIO_ODE_Output_Enable; - } - GPIO_Init(index->gpio, index->pin, &gpio_initstruct); -} - -rt_inline const struct irq_map *get_pin_irq_map(rt_uint16_t gpio_pin) -{ - rt_int32_t mapindex = gpio_pin & 0x00FF; - if (mapindex < 0 || mapindex >= 32) - { - return RT_NULL; - } - return &irq_map[mapindex % 8]; -}; - -rt_err_t es8p_pin_attach_irq(struct rt_device *device, rt_int32_t pin, - rt_uint32_t mode, void (*hdr)(void *args), void *args) -{ - const struct pin_index *index; - rt_base_t level; - rt_int32_t irqindex; - index = get_pin(pin); - if (index == RT_NULL) - { - return RT_ENOSYS; - } - - irqindex = index->pin % 8; - level = rt_hw_interrupt_disable(); - - if (pin_irq_hdr_tab[irqindex].pin == pin && - pin_irq_hdr_tab[irqindex].hdr == hdr && - pin_irq_hdr_tab[irqindex].mode == mode && - pin_irq_hdr_tab[irqindex].args == args) - { - rt_hw_interrupt_enable(level); - return RT_EOK; - } - if (pin_irq_hdr_tab[irqindex].pin != -1) - { - rt_hw_interrupt_enable(level); - return RT_EBUSY; - } - - pin_irq_hdr_tab[irqindex].pin = pin; - pin_irq_hdr_tab[irqindex].hdr = hdr; - pin_irq_hdr_tab[irqindex].mode = mode; - pin_irq_hdr_tab[irqindex].args = args; - rt_hw_interrupt_enable(level); - - return RT_EOK; -} - -rt_err_t es8p_pin_detach_irq(struct rt_device *device, rt_int32_t pin) -{ - const struct pin_index *index; - rt_base_t level; - rt_int32_t irqindex = -1; - index = get_pin(pin); - if (index == RT_NULL) - { - return RT_ENOSYS; - } - irqindex = index->pin % 8; - level = rt_hw_interrupt_disable(); - - if (pin_irq_hdr_tab[irqindex].pin == -1) - { - rt_hw_interrupt_enable(level); - return RT_EOK; - } - pin_irq_hdr_tab[irqindex].pin = -1; - pin_irq_hdr_tab[irqindex].hdr = RT_NULL; - pin_irq_hdr_tab[irqindex].mode = 0; - pin_irq_hdr_tab[irqindex].args = RT_NULL; - rt_hw_interrupt_enable(level); - return RT_EOK; -} - -rt_err_t es8p_pin_irq_enable(struct rt_device *device, rt_base_t pin, - rt_uint32_t enabled) -{ - const struct pin_index *index; - const struct irq_map *irqmap; - rt_base_t level; - rt_int32_t irqindex = -1; - /* Configure GPIO_InitStructure */ - GPIO_InitStruType gpio_initstruct; - - index = get_pin(pin); - if (index == RT_NULL) - { - return RT_ENOSYS; - } - if (enabled == PIN_IRQ_ENABLE) - { - irqindex = pin % 8; - level = rt_hw_interrupt_disable(); - if (pin_irq_hdr_tab[irqindex].pin == -1) - { - rt_hw_interrupt_enable(level); - return RT_ENOSYS; - } - irqmap = &irq_map[irqindex]; - - /* Configure GPIO_InitStructure */ - gpio_initstruct.GPIO_Signal = GPIO_Pin_Signal_Digital; - gpio_initstruct.GPIO_Func = GPIO_Func_0; - gpio_initstruct.GPIO_Direction = GPIO_Dir_In; - gpio_initstruct.GPIO_OD = GPIO_ODE_Output_Disable; - gpio_initstruct.GPIO_DS = GPIO_DS_Output_Normal; - - switch (pin_irq_hdr_tab[irqindex].mode) - { - case PIN_IRQ_MODE_RISING: - gpio_initstruct.GPIO_PUEN = GPIO_PUE_Input_Disable; - gpio_initstruct.GPIO_PDEN = GPIO_PDE_Input_Enable; - if (index->gpio == GPIOA) - PINT_Config(irqmap->pinno, (PINT_TYPE_SEL)(pin >> 3), PINT_Trig_Rise); - else - PINT_Config(irqmap->pinno, (PINT_TYPE_SEL)((pin >> 3) + 4), PINT_Trig_Rise); - break; - - case PIN_IRQ_MODE_FALLING: - gpio_initstruct.GPIO_PUEN = GPIO_PUE_Input_Enable; - gpio_initstruct.GPIO_PDEN = GPIO_PDE_Input_Disable; - if (index->gpio == GPIOA) - PINT_Config(irqmap->pinno, (PINT_TYPE_SEL)(pin >> 3), PINT_Trig_Fall); - else - PINT_Config(irqmap->pinno, (PINT_TYPE_SEL)((pin >> 3) + 4), PINT_Trig_Fall); - break; - - case PIN_IRQ_MODE_RISING_FALLING: - gpio_initstruct.GPIO_PUEN = GPIO_PUE_Input_Disable; - gpio_initstruct.GPIO_PDEN = GPIO_PDE_Input_Disable; - if (index->gpio == GPIOA) - PINT_Config(irqmap->pinno, (PINT_TYPE_SEL)(pin >> 3), PINT_Trig_Change); - else - PINT_Config(irqmap->pinno, (PINT_TYPE_SEL)((pin >> 3) + 4), PINT_Trig_Change); - break; - - default: - break; - } - GPIO_Init(index->gpio, index->pin, &gpio_initstruct); - NVIC_EnableIRQ(irqmap->irqno); - rt_hw_interrupt_enable(level); - } - else if (enabled == PIN_IRQ_DISABLE) - { - irqmap = get_pin_irq_map(index->pin); - if (irqmap == RT_NULL) - { - return RT_ENOSYS; - } - NVIC_DisableIRQ(irqmap->irqno); - } - else - { - return RT_ENOSYS; - } - return RT_EOK; -} - -const static struct rt_pin_ops _es8p_pin_ops = -{ - es8p_pin_mode, - es8p_pin_write, - es8p_pin_read, - es8p_pin_attach_irq, - es8p_pin_detach_irq, - es8p_pin_irq_enable, - RT_NULL, -}; - -int rt_hw_pin_init(void) -{ - int result; - SCU_GPIOCLK_Enable(); - result = rt_device_pin_register("pin", &_es8p_pin_ops, RT_NULL); - return result; -} -INIT_BOARD_EXPORT(rt_hw_pin_init); - -rt_inline void pin_irq_hdr(PINT_TYPE_IT GPIO_Pin) -{ - uint16_t irqno; - /* pin no. convert to dec no. */ - for (irqno = 0; irqno < 16; irqno++) - { - if ((0x01 << irqno) == GPIO_Pin) - { - break; - } - } - if (pin_irq_hdr_tab[irqno].hdr) - { - pin_irq_hdr_tab[irqno].hdr(pin_irq_hdr_tab[irqno].args); - } -} - -rt_inline void GPIO_EXTI_Callback(PINT_TYPE_IT GPIO_Pin) -{ - if (PINT_GetIFStatus(GPIO_Pin) != RESET) - { - PINT_ClearITPendingBit(GPIO_Pin); - pin_irq_hdr(GPIO_Pin); - } -} - -void PINT0_IRQHandler(void) -{ - rt_interrupt_enter(); - GPIO_EXTI_Callback(PINT_IT_PINT0); - rt_interrupt_leave(); -} - -void PINT1_IRQHandler(void) -{ - rt_interrupt_enter(); - GPIO_EXTI_Callback(PINT_IT_PINT1); - rt_interrupt_leave(); -} - -void PINT2_IRQHandler(void) -{ - rt_interrupt_enter(); - GPIO_EXTI_Callback(PINT_IT_PINT2); - rt_interrupt_leave(); -} - -void PINT3_IRQHandler(void) -{ - rt_interrupt_enter(); - GPIO_EXTI_Callback(PINT_IT_PINT3); - rt_interrupt_leave(); -} - -void PINT4_IRQHandler(void) -{ - rt_interrupt_enter(); - GPIO_EXTI_Callback(PINT_IT_PINT4); - rt_interrupt_leave(); -} - -void PINT5_IRQHandler(void) -{ - rt_interrupt_enter(); - GPIO_EXTI_Callback(PINT_IT_PINT5); - rt_interrupt_leave(); -} - -void PINT6_IRQHandler(void) -{ - rt_interrupt_enter(); - GPIO_EXTI_Callback(PINT_IT_PINT6); - rt_interrupt_leave(); -} - -void PINT7_IRQHandler(void) -{ - rt_interrupt_enter(); - GPIO_EXTI_Callback(PINT_IT_PINT7); - rt_interrupt_leave(); -} - -#endif diff --git a/bsp/essemi/es8p508x/drivers/drv_gpio.h b/bsp/essemi/es8p508x/drivers/drv_gpio.h deleted file mode 100644 index 28a5987f20..0000000000 --- a/bsp/essemi/es8p508x/drivers/drv_gpio.h +++ /dev/null @@ -1,16 +0,0 @@ -/* - * Copyright (C) 2018 Shanghai Eastsoft Microelectronics Co., Ltd. - * - * SPDX-License-Identifier: Apache-2.0 - * - * Change Logs: - * Date Author Notes - * 2019-07-11 wangyq the first version - */ - -#ifndef DRV_GPIO_H__ -#define DRV_GPIO_H__ - -int rt_hw_pin_init(void); - -#endif diff --git a/bsp/essemi/es8p508x/drivers/drv_uart.c b/bsp/essemi/es8p508x/drivers/drv_uart.c deleted file mode 100644 index 3fb1410a48..0000000000 --- a/bsp/essemi/es8p508x/drivers/drv_uart.c +++ /dev/null @@ -1,444 +0,0 @@ -/* - * Copyright (C) 2018 Shanghai Eastsoft Microelectronics Co., Ltd. - * - * SPDX-License-Identifier: Apache-2.0 - * - * Change Logs: - * Date Author Notes - * 2019-07-12 wangyq the first version - */ - -#include -#include -#include -#include "board.h" -#include "drv_uart.h" -#include -#include - -#ifdef RT_USING_SERIAL - -/* es8p uart driver */ -struct es8p_uart -{ - UART_TypeDef *huart; - IRQn_Type irq; -}; - -static rt_err_t es8px_configure(struct rt_serial_device *serial, struct serial_configure *cfg) -{ - GPIO_InitStruType gpio_initstruct; - UART_InitStruType uart_initstruct; - struct es8p_uart *uart; - RT_ASSERT(serial != RT_NULL); - RT_ASSERT(cfg != RT_NULL); - uart = (struct es8p_uart *)serial->parent.user_data; - - gpio_initstruct.GPIO_Signal = GPIO_Pin_Signal_Digital; - gpio_initstruct.GPIO_OD = GPIO_ODE_Output_Disable; - gpio_initstruct.GPIO_PUEN = GPIO_PUE_Input_Enable; - gpio_initstruct.GPIO_PDEN = GPIO_PDE_Input_Disable; - gpio_initstruct.GPIO_DS = GPIO_DS_Output_Normal; - -#ifdef BSP_USING_UART0 - gpio_initstruct.GPIO_Func = GPIO_Func_2; - /* Initialize rx pin */ - gpio_initstruct.GPIO_Direction = GPIO_Dir_In; - GPIO_Init(GPIOB, GPIO_Pin_0, &gpio_initstruct); - /* Initialize tx pin ,the same as rx pin except mode */ - gpio_initstruct.GPIO_Direction = GPIO_Dir_Out; - GPIO_Init(GPIOB, GPIO_Pin_1, &gpio_initstruct); -#endif - -#ifdef BSP_USING_UART1 - gpio_initstruct.GPIO_Func = GPIO_Func_1; - /* Initialize rx pin */ - gpio_initstruct.GPIO_Direction = GPIO_Dir_In; - GPIO_Init(GPIOA, GPIO_Pin_18, &gpio_initstruct); - /* Initialize tx pin ,the same as rx pin except mode */ - gpio_initstruct.GPIO_Direction = GPIO_Dir_Out; - GPIO_Init(GPIOA, GPIO_Pin_17, &gpio_initstruct); -#endif - -#ifdef BSP_USING_UART2 - gpio_initstruct.GPIO_Func = GPIO_Func_2; - /* Initialize rx pin */ - gpio_initstruct.GPIO_Direction = GPIO_Dir_In; - GPIO_Init(GPIOA, GPIO_Pin_4, &gpio_initstruct); - /* Initialize tx pin ,the same as rx pin except mode */ - gpio_initstruct.GPIO_Direction = GPIO_Dir_Out; - GPIO_Init(GPIOA, GPIO_Pin_5, &gpio_initstruct); -#endif - -#ifdef BSP_USING_UART3 - gpio_initstruct.GPIO_Func = GPIO_Func_2; - /* Initialize rx pin */ - gpio_initstruct.GPIO_Direction = GPIO_Dir_In; - GPIO_Init(GPIOA, GPIO_Pin_30, &gpio_initstruct); - /* Initialize tx pin ,the same as rx pin except mode */ - gpio_initstruct.GPIO_Direction = GPIO_Dir_Out; - GPIO_Init(GPIOA, GPIO_Pin_29, &gpio_initstruct); -#endif - -#ifdef BSP_USING_UART4 - gpio_initstruct.GPIO_Func = GPIO_Func_1; - /* Initialize rx pin */ - gpio_initstruct.GPIO_Direction = GPIO_Dir_In; - GPIO_Init(GPIOB, GPIO_Pin_10, &gpio_initstruct); - /* Initialize tx pin ,the same as rx pin except mode */ - gpio_initstruct.GPIO_Direction = GPIO_Dir_Out; - GPIO_Init(GPIOB, GPIO_Pin_11, &gpio_initstruct); -#endif - -#ifdef BSP_USING_UART5 - gpio_initstruct.GPIO_Func = GPIO_Func_1; - /* Initialize rx pin */ - gpio_initstruct.GPIO_Direction = GPIO_Dir_In; - GPIO_Init(GPIOB, GPIO_Pin_12, &gpio_initstruct); - /* Initialize tx pin ,the same as rx pin except mode */ - gpio_initstruct.GPIO_Direction = GPIO_Dir_Out; - GPIO_Init(GPIOB, GPIO_Pin_13, &gpio_initstruct); -#endif - - uart_initstruct.UART_ClockSet = UART_Clock_1; - uart_initstruct.UART_BaudRate = cfg->baud_rate; - uart_initstruct.UART_RxPolar = UART_Polar_Normal; - uart_initstruct.UART_TxPolar = UART_Polar_Normal; - - if (cfg->data_bits == DATA_BITS_7) - { - uart_initstruct.UART_RxMode = UART_DataMode_7; - uart_initstruct.UART_TxMode = UART_DataMode_7; - - if (cfg->parity == PARITY_EVEN) - { - uart_initstruct.UART_RxMode = UART_DataMode_7Even; - uart_initstruct.UART_TxMode = UART_DataMode_7Even; - } - else if (cfg->parity == PARITY_ODD) - { - uart_initstruct.UART_RxMode = UART_DataMode_7Odd; - uart_initstruct.UART_TxMode = UART_DataMode_7Odd; - } - } - else if (cfg->data_bits == DATA_BITS_8) - { - uart_initstruct.UART_RxMode = UART_DataMode_8; - uart_initstruct.UART_TxMode = UART_DataMode_8; - - if (cfg->parity == PARITY_EVEN) - { - uart_initstruct.UART_RxMode = UART_DataMode_8Even; - uart_initstruct.UART_TxMode = UART_DataMode_8Even; - } - else if (cfg->parity == PARITY_ODD) - { - uart_initstruct.UART_RxMode = UART_DataMode_8Odd; - uart_initstruct.UART_TxMode = UART_DataMode_8Odd; - } - } - else if (cfg->data_bits == DATA_BITS_9) - { - uart_initstruct.UART_RxMode = UART_DataMode_9; - uart_initstruct.UART_TxMode = UART_DataMode_9; - } - - if (cfg->bit_order == BIT_ORDER_MSB) - { - return RT_EINVAL; - } - - if (cfg->invert == NRZ_INVERTED) - { - uart_initstruct.UART_RxPolar = UART_Polar_Opposite; - uart_initstruct.UART_TxPolar = UART_Polar_Opposite; - } - - /* config uart function */ - UART_Init(uart->huart, &uart_initstruct); - /* enable rx and tx */ - uart->huart->CON.RXEN = 1; - uart->huart->CON.TXEN = 1; - - NVIC_SetPriority(uart->irq, 1); - - return RT_EOK; -} - -static rt_err_t es8px_control(struct rt_serial_device *serial, int cmd, void *arg) -{ - struct es8p_uart *uart; - RT_ASSERT(serial != RT_NULL); - - uart = (struct es8p_uart *)serial->parent.user_data; - - switch (cmd) - { - case RT_DEVICE_CTRL_CLR_INT: - /* disable rx irq */ - NVIC_DisableIRQ(uart->irq); - /* disable interrupt */ - UART_ITConfig(uart->huart, UART_IT_RB, DISABLE); - break; - - case RT_DEVICE_CTRL_SET_INT: - /* enable rx irq */ - NVIC_EnableIRQ(uart->irq); - /* enable interrupt */ - UART_ITConfig(uart->huart, UART_IT_RB, ENABLE); - break; - } - - return RT_EOK; -} - -static int es8px_putc(struct rt_serial_device *serial, char c) -{ - struct es8p_uart *uart; - RT_ASSERT(serial != RT_NULL); - uart = (struct es8p_uart *)serial->parent.user_data; - - while (UART_GetFlagStatus(uart->huart, UART_FLAG_TB) == RESET) ; - UART_SendByte(uart->huart, c); - - return 1; -} - -static int es8px_getc(struct rt_serial_device *serial) -{ - int ch = -1; - struct es8p_uart *uart; - - RT_ASSERT(serial != RT_NULL); - uart = (struct es8p_uart *)serial->parent.user_data; - - if (UART_GetFlagStatus(uart->huart, UART_FLAG_RB)) - { - ch = UART_RecByte(uart->huart); - } - - return ch; -} - -static const struct rt_uart_ops es8px_uart_ops = -{ - es8px_configure, - es8px_control, - es8px_putc, - es8px_getc, -}; - -#ifdef BSP_USING_UART0 -/* UART0 device driver structure */ -struct es8p_uart uart0 = -{ - UART0, - UART0_IRQn -}; - -struct rt_serial_device serial0; - -void UART0_IRQHandler(void) -{ - /* enter interrupt */ - rt_interrupt_enter(); - - if (UART0->IF.RBIF) - { - rt_hw_serial_isr(&serial0, RT_SERIAL_EVENT_RX_IND); - } - /* leave interrupt */ - rt_interrupt_leave(); -} -#endif /* BSP_USING_UART0 */ - -#ifdef BSP_USING_UART1 -/* UART1 device driver structure */ -struct es8p_uart uart1 = -{ - UART1, - UART1_IRQn -}; - -struct rt_serial_device serial1; - -void UART1_IRQHandler(void) -{ - /* enter interrupt */ - rt_interrupt_enter(); - - if (UART1->IF.RBIF) - { - rt_hw_serial_isr(&serial1, RT_SERIAL_EVENT_RX_IND); - } - /* leave interrupt */ - rt_interrupt_leave(); -} -#endif /* BSP_USING_UART1 */ - -#ifdef BSP_USING_UART2 -/* UART1 device driver structure */ -struct es8p_uart uart2 = -{ - UART2, - UART2_IRQn -}; - -struct rt_serial_device serial2; - -void UART2_IRQHandler(void) -{ - /* enter interrupt */ - rt_interrupt_enter(); - - if (UART2->IF.RBIF) - { - rt_hw_serial_isr(&serial2, RT_SERIAL_EVENT_RX_IND); - } - /* leave interrupt */ - rt_interrupt_leave(); -} -#endif /* BSP_USING_UART2 */ - -#ifdef BSP_USING_UART3 -/* UART3 device driver structure */ -struct es8p_uart uart3 = -{ - UART3, - UART3_IRQn -}; - -struct rt_serial_device serial3; - -void UART3_IRQHandler(void) -{ - /* enter interrupt */ - rt_interrupt_enter(); - - if (UART3->IF.RBIF) - { - rt_hw_serial_isr(&serial3, RT_SERIAL_EVENT_RX_IND); - } - /* leave interrupt */ - rt_interrupt_leave(); -} -#endif /* BSP_USING_UART3 */ - -#ifdef BSP_USING_UART4 -/* UART4 device driver structure */ -struct es8p_uart uart4 = -{ - UART4, - UART4_IRQn -}; - -struct rt_serial_device serial4; - -void UART4_IRQHandler(void) -{ - /* enter interrupt */ - rt_interrupt_enter(); - - if (UART4->IF.RBIF) - { - rt_hw_serial_isr(&serial4, RT_SERIAL_EVENT_RX_IND); - } - /* leave interrupt */ - rt_interrupt_leave(); -} -#endif /* BSP_USING_UART4 */ - -#ifdef BSP_USING_UART5 -/* UART5 device driver structure */ -struct es8p_uart uart5 = -{ - UART5, - UART5_IRQn -}; - -struct rt_serial_device serial5; - -void UART5_IRQHandler(void) -{ - /* enter interrupt */ - rt_interrupt_enter(); - - if (UART5->IF.RBIF) - { - rt_hw_serial_isr(&serial5, RT_SERIAL_EVENT_RX_IND); - } - /* leave interrupt */ - rt_interrupt_leave(); -} -#endif /* BSP_USING_UART5 */ - -int rt_hw_uart_init(void) -{ - struct es8p_uart *uart; - struct serial_configure config = RT_SERIAL_CONFIG_DEFAULT; - -#ifdef BSP_USING_UART0 - uart = &uart0; - serial0.ops = &es8px_uart_ops; - serial0.config = config; - - /* register UART0 device */ - rt_hw_serial_register(&serial0, "uart0", - RT_DEVICE_FLAG_RDWR | RT_DEVICE_FLAG_INT_RX, uart); -#endif /* BSP_USING_UART0 */ - -#ifdef BSP_USING_UART1 - uart = &uart1; - serial1.ops = &es8px_uart_ops; - serial1.config = config; - - /* register UART1 device */ - rt_hw_serial_register(&serial1, "uart1", - RT_DEVICE_FLAG_RDWR | RT_DEVICE_FLAG_INT_RX, uart); -#endif /* BSP_USING_UART1 */ - -#ifdef BSP_USING_UART2 - uart = &uart2; - serial2.ops = &es8px_uart_ops; - serial2.config = config; - - /* register UART2 device */ - rt_hw_serial_register(&serial2, "uart2", - RT_DEVICE_FLAG_RDWR | RT_DEVICE_FLAG_INT_RX, uart); -#endif /* BSP_USING_UART2 */ - -#ifdef BSP_USING_UART3 - uart = &uart3; - serial3.ops = &es8px_uart_ops; - serial3.config = config; - - /* register UART3 device */ - rt_hw_serial_register(&serial3, "uart3", - RT_DEVICE_FLAG_RDWR | RT_DEVICE_FLAG_INT_RX, uart); -#endif /* BSP_USING_UART3 */ - -#ifdef BSP_USING_UART4 - uart = &uart4; - serial4.ops = &es8px_uart_ops; - serial4.config = config; - - /* register UART4 device */ - rt_hw_serial_register(&serial4, "uart4", - RT_DEVICE_FLAG_RDWR | RT_DEVICE_FLAG_INT_RX, uart); -#endif /* BSP_USING_UART4 */ - -#ifdef BSP_USING_UART5 - uart = &uart5; - serial5.ops = &es8px_uart_ops; - serial5.config = config; - - /* register UART5 device */ - rt_hw_serial_register(&serial5, "uart5", - RT_DEVICE_FLAG_RDWR | RT_DEVICE_FLAG_INT_RX, uart); -#endif /* BSP_USING_UART5 */ - - return 0; -} -INIT_BOARD_EXPORT(rt_hw_uart_init); - -#endif diff --git a/bsp/essemi/es8p508x/drivers/drv_uart.h b/bsp/essemi/es8p508x/drivers/drv_uart.h deleted file mode 100644 index 77abf1cfd4..0000000000 --- a/bsp/essemi/es8p508x/drivers/drv_uart.h +++ /dev/null @@ -1,16 +0,0 @@ -/* - * Copyright (C) 2018 Shanghai Eastsoft Microelectronics Co., Ltd. - * - * SPDX-License-Identifier: Apache-2.0 - * - * Change Logs: - * Date Author Notes - * 2019-07-12 wangyq the first version - */ - -#ifndef DRV_UART_H__ -#define DRV_UART_H__ - -int rt_hw_uart_init(void); - -#endif diff --git a/bsp/essemi/es8p508x/drivers/linker_scripts/link.sct b/bsp/essemi/es8p508x/drivers/linker_scripts/link.sct deleted file mode 100644 index 47ab250a8b..0000000000 --- a/bsp/essemi/es8p508x/drivers/linker_scripts/link.sct +++ /dev/null @@ -1,15 +0,0 @@ -; ************************************************************* -; *** Scatter-Loading Description File generated by uVision *** -; ************************************************************* - -LR_IROM1 0x00000000 0x00020000 { ; load region size_region - ER_IROM1 0x00000000 0x00020000 { ; load address = execution address - *.o (RESET, +First) - *(InRoot$$Sections) - .ANY (+RO) - } - RW_IRAM1 0x20000000 0x00006000 { ; RW data - .ANY (+RW +ZI) - } -} - diff --git a/bsp/essemi/es8p508x/figures/ESLinkII-mini.jpg b/bsp/essemi/es8p508x/figures/ESLinkII-mini.jpg deleted file mode 100644 index 7dfc7aa1ae..0000000000 Binary files a/bsp/essemi/es8p508x/figures/ESLinkII-mini.jpg and /dev/null differ diff --git a/bsp/essemi/es8p508x/figures/HRSDK-GDB-ES8P508x-V1.0.jpg b/bsp/essemi/es8p508x/figures/HRSDK-GDB-ES8P508x-V1.0.jpg deleted file mode 100644 index a31b7c0704..0000000000 Binary files a/bsp/essemi/es8p508x/figures/HRSDK-GDB-ES8P508x-V1.0.jpg and /dev/null differ diff --git a/bsp/essemi/es8p508x/project.uvopt b/bsp/essemi/es8p508x/project.uvopt deleted file mode 100644 index 26bbe6a024..0000000000 --- a/bsp/essemi/es8p508x/project.uvopt +++ /dev/null @@ -1,174 +0,0 @@ - - - - 1.0 - -
### uVision Project, (C) Keil Software
- - - *.c - *.s*; *.src; *.a* - *.obj - *.lib - *.txt; *.h; *.inc - *.plm - *.cpp - - - - 0 - 0 - - - - rt-thread - 0x4 - ARM-ADS - - 20000000 - - 1 - 1 - 1 - 0 - - - 1 - 65535 - 0 - 0 - 0 - - - 79 - 66 - 8 - .\build\keil\ - - - 1 - 1 - 1 - 0 - 1 - 1 - 0 - 1 - 0 - 0 - 0 - 0 - - - 1 - 1 - 1 - 1 - 1 - 1 - 1 - 0 - 0 - - - 0 - 0 - 1 - - 0 - - SARMCM3.DLL - - DARMCM1.DLL - -pCM0 - SARMCM3.DLL - - TARMCM1.DLL - - - - 0 - 1 - 1 - 1 - 1 - 1 - 1 - 1 - 1 - 1 - 1 - 1 - 1 - 1 - 0 - 1 - 0 - 0 - 1 - 13 - - - - - - - - - - - BIN\CMSIS_AGDI.dll - - - - 0 - JL2CM3 - -U12345678 -O78 -S0 -A0 -C0 -JU1 -JI127.0.0.1 -JP0 -RST0 -N00("ARM CoreSight SW-DP") -D00(0BB11477) -L00(0) -TO18 -TC10000000 -TP21 -TDS8007 -TDT0 -TDC1F -TIEFFFFFFFF -TIP8 -TB1 -TFE0 -FO15 -FD20000000 -FC800 -FN1 -FF0ES8P508x -FS00 -FL020000 - - - 0 - CMSIS_AGDI - -X"essemi CMSIS-DAP" -U0001A000000A -O207 -S0 -C0 -P00 -N00("ARM CoreSight SW-DP") -D00(0BB11477) -L00(0) -FO15 -FD20000000 -FC6000 -FN1 -FF0ES8P508x -FS00 -FL020000 - - - 0 - UL2CM3 - UL2CM3(-O207 -S0 -C0 -FO7 -FD20000000 -FC6000 -FN1 -FF0ES8P508x -FS00000000 -FL020000) - - - - - 0 - - - 0 - 0 - 0 - 0 - 0 - 0 - 0 - 0 - 0 - 0 - 0 - 0 - 0 - 0 - 0 - 0 - 0 - 0 - 0 - 0 - 0 - 0 - 0 - 0 - - - - - - - diff --git a/bsp/essemi/es8p508x/project.uvproj b/bsp/essemi/es8p508x/project.uvproj deleted file mode 100644 index 26dac69d04..0000000000 --- a/bsp/essemi/es8p508x/project.uvproj +++ /dev/null @@ -1,790 +0,0 @@ - - - 1.1 -
### uVision Project, (C) Keil Software
- - - rt-thread - 0x4 - ARM-ADS - - - ES8P508xFLXX - ES - IRAM(0x20000000-0x20005FFF) IROM(0x00000000-0x0001FFFF) CLOCK(20000000) CPUTYPE("Cortex-M0") - - "STARTUP\HR\startup_ES8P508x.s" ("ES8P508x Startup Code") - UL2CM3(-O207 -S0 -C0 -FO7 -FD20000000 -FC6000 -FN1 -FF0ES8P508x -FS00000000 -FL020000) - 0 - ES8P508x.h - - - - - - - - - - SFD\HR\ES8P508x.SFR - 0 - 0 - - - - HR\ - HR\ - - 0 - 0 - 0 - 0 - 1 - - .\build\keil\ - rt-thread - 1 - 0 - 0 - 1 - 1 - .\build\keil\ - 1 - 0 - 0 - - 0 - 0 - - - 0 - 0 - 0 - 0 - - - 0 - 0 - - - 0 - 0 - - - 1 - 0 - fromelf --bin !L --output rtthread.bin - fromelf --text -c ".\build\keil\@L.axf" --output ".\build\keil\@L.txt" - 0 - 0 - - 0 - - - - 0 - 0 - 0 - 0 - 0 - 1 - 0 - 0 - 0 - 0 - 3 - - - 1 - - - SARMCM3.DLL - - DARMCM1.DLL - -pCM0 - SARMCM3.DLL - - TARMCM1.DLL - - - - - 1 - 0 - 0 - 0 - 16 - - - 0 - 1 - 1 - 1 - 1 - 1 - 1 - 1 - 1 - - - 1 - 1 - 1 - 1 - 1 - 1 - 0 - 1 - 0 - - 0 - 13 - - - - - - - - - - - - - - BIN\CMSIS_AGDI.dll - - - - - 1 - 0 - 0 - 1 - 1 - 4096 - - 1 - BIN\UL2CM3.DLL - "" () - - - - - 0 - - - - 0 - 1 - 1 - 1 - 1 - 1 - 1 - 1 - 0 - 1 - 1 - 0 - 0 - 1 - 0 - 0 - 1 - 1 - 1 - 1 - 1 - 1 - 1 - 1 - 1 - 0 - 0 - "Cortex-M0" - - 0 - 0 - 0 - 1 - 1 - 0 - 0 - 0 - 0 - 0 - 8 - 0 - 0 - 0 - 3 - 5 - 0 - 0 - 0 - 0 - 0 - 0 - 0 - 0 - 0 - 0 - 1 - 0 - 0 - 0 - 0 - 1 - 0 - - - 0 - 0x0 - 0x0 - - - 0 - 0x0 - 0x0 - - - 0 - 0x0 - 0x0 - - - 0 - 0x0 - 0x0 - - - 0 - 0x0 - 0x0 - - - 0 - 0x0 - 0x0 - - - 0 - 0x20000000 - 0x6000 - - - 1 - 0x0 - 0x20000 - - - 0 - 0x0 - 0x0 - - - 1 - 0x0 - 0x0 - - - 1 - 0x0 - 0x0 - - - 1 - 0x0 - 0x0 - - - 1 - 0x0 - 0x20000 - - - 1 - 0x0 - 0x0 - - - 0 - 0x0 - 0x0 - - - 0 - 0x0 - 0x0 - - - 0 - 0x0 - 0x0 - - - 0 - 0x20000000 - 0x6000 - - - 0 - 0x0 - 0x0 - - - - - - 1 - 1 - 0 - 0 - 1 - 0 - 0 - 0 - 0 - 0 - 0 - 0 - 0 - - --c99 - - - .;..\..\..\include;applications;.;drivers;libraries\CMSIS;libraries\Library\Include;..\..\..\libcpu\arm\common;..\..\..\libcpu\arm\cortex-m0;..\..\..\components\drivers\include;..\..\..\components\drivers\include;..\..\..\components\drivers\include;..\..\..\components\finsh;..\..\..\components\libc\compilers\common - - - - 1 - 0 - 0 - 0 - 0 - 0 - 0 - 0 - - - - - - - - - 1 - 0 - 0 - 0 - 1 - 0 - 0x00000000 - 0x20000000 - - - - - - - - - - - - Kernel - - - clock.c - 1 - ..\..\..\src\clock.c - - - - - components.c - 1 - ..\..\..\src\components.c - - - - - device.c - 1 - ..\..\..\src\device.c - - - - - idle.c - 1 - ..\..\..\src\idle.c - - - - - ipc.c - 1 - ..\..\..\src\ipc.c - - - - - irq.c - 1 - ..\..\..\src\irq.c - - - - - kservice.c - 1 - ..\..\..\src\kservice.c - - - - - mem.c - 1 - ..\..\..\src\mem.c - - - - - mempool.c - 1 - ..\..\..\src\mempool.c - - - - - object.c - 1 - ..\..\..\src\object.c - - - - - scheduler.c - 1 - ..\..\..\src\scheduler.c - - - - - signal.c - 1 - ..\..\..\src\signal.c - - - - - thread.c - 1 - ..\..\..\src\thread.c - - - - - timer.c - 1 - ..\..\..\src\timer.c - - - - - Applications - - - main.c - 1 - applications\main.c - - - - - Drivers - - - board.c - 1 - drivers\board.c - - - - - drv_gpio.c - 1 - drivers\drv_gpio.c - - - - - drv_uart.c - 1 - drivers\drv_uart.c - - - - - Libraries - - - irqhandler.c - 1 - libraries\Library\Source\irqhandler.c - - - - - lib_adc.c - 1 - libraries\Library\Source\lib_adc.c - - - - - lib_aes.c - 1 - libraries\Library\Source\lib_aes.c - - - - - lib_crc.c - 1 - libraries\Library\Source\lib_crc.c - - - - - lib_flashiap.c - 1 - libraries\Library\Source\lib_flashiap.c - - - - - lib_gpio.c - 1 - libraries\Library\Source\lib_gpio.c - - - - - lib_iap.c - 1 - libraries\Library\Source\lib_iap.c - - - - - lib_iic.c - 1 - libraries\Library\Source\lib_iic.c - - - - - lib_printf.c - 1 - libraries\Library\Source\lib_printf.c - - - - - lib_rtc.c - 1 - libraries\Library\Source\lib_rtc.c - - - - - lib_scs.c - 1 - libraries\Library\Source\lib_scs.c - - - - - lib_scu.c - 1 - libraries\Library\Source\lib_scu.c - - - - - lib_spi.c - 1 - libraries\Library\Source\lib_spi.c - - - - - lib_timer.c - 1 - libraries\Library\Source\lib_timer.c - - - - - lib_uart.c - 1 - libraries\Library\Source\lib_uart.c - - - - - lib_wdt.c - 1 - libraries\Library\Source\lib_wdt.c - - - - - system_ES8P508x.c - 1 - libraries\CMSIS\system_ES8P508x.c - - - - - startup_ES8P508x.s - 2 - libraries\CMSIS\startup_ES8P508x.s - - - - - cpu - - - backtrace.c - 1 - ..\..\..\libcpu\arm\common\backtrace.c - - - - - div0.c - 1 - ..\..\..\libcpu\arm\common\div0.c - - - - - showmem.c - 1 - ..\..\..\libcpu\arm\common\showmem.c - - - - - cpuport.c - 1 - ..\..\..\libcpu\arm\cortex-m0\cpuport.c - - - - - context_rvds.S - 2 - ..\..\..\libcpu\arm\cortex-m0\context_rvds.S - - - - - DeviceDrivers - - - pin.c - 1 - ..\..\..\components\drivers\misc\pin.c - - - - - serial.c - 1 - ..\..\..\components\drivers\serial\serial.c - - - - - completion.c - 1 - ..\..\..\components\drivers\src\completion.c - - - - - dataqueue.c - 1 - ..\..\..\components\drivers\src\dataqueue.c - - - - - pipe.c - 1 - ..\..\..\components\drivers\src\pipe.c - - - - - ringblk_buf.c - 1 - ..\..\..\components\drivers\src\ringblk_buf.c - - - - - ringbuffer.c - 1 - ..\..\..\components\drivers\src\ringbuffer.c - - - - - waitqueue.c - 1 - ..\..\..\components\drivers\src\waitqueue.c - - - - - workqueue.c - 1 - ..\..\..\components\drivers\src\workqueue.c - - - - - finsh - - - shell.c - 1 - ..\..\..\components\finsh\shell.c - - - - - cmd.c - 1 - ..\..\..\components\finsh\cmd.c - - - - - msh.c - 1 - ..\..\..\components\finsh\msh.c - - - - - - - diff --git a/bsp/essemi/es8p508x/rtconfig.h b/bsp/essemi/es8p508x/rtconfig.h deleted file mode 100644 index 034174f9ec..0000000000 --- a/bsp/essemi/es8p508x/rtconfig.h +++ /dev/null @@ -1,162 +0,0 @@ -#ifndef RT_CONFIG_H__ -#define RT_CONFIG_H__ - -/* Automatically generated file; DO NOT EDIT. */ -/* RT-Thread Configuration */ - -/* RT-Thread Kernel */ - -#define RT_NAME_MAX 8 -#define RT_ALIGN_SIZE 4 -#define RT_THREAD_PRIORITY_32 -#define RT_THREAD_PRIORITY_MAX 32 -#define RT_TICK_PER_SECOND 100 -#define RT_USING_OVERFLOW_CHECK -#define RT_USING_HOOK -#define RT_USING_IDLE_HOOK -#define RT_IDLE_HOOK_LIST_SIZE 4 -#define IDLE_THREAD_STACK_SIZE 256 -#define RT_DEBUG - -/* Inter-Thread communication */ - -#define RT_USING_SEMAPHORE -#define RT_USING_MUTEX -#define RT_USING_EVENT -#define RT_USING_MAILBOX -#define RT_USING_MESSAGEQUEUE - -/* Memory Management */ - -#define RT_USING_MEMPOOL -#define RT_USING_SMALL_MEM -#define RT_USING_HEAP - -/* Kernel Device Object */ - -#define RT_USING_DEVICE -#define RT_USING_CONSOLE -#define RT_CONSOLEBUF_SIZE 128 -#define RT_CONSOLE_DEVICE_NAME "uart5" -#define RT_VER_NUM 0x40002 - -/* RT-Thread Components */ - -#define RT_USING_COMPONENTS_INIT -#define RT_USING_USER_MAIN -#define RT_MAIN_THREAD_STACK_SIZE 2048 -#define RT_MAIN_THREAD_PRIORITY 10 - -/* C++ features */ - - -/* Command shell */ - -#define RT_USING_FINSH -#define FINSH_THREAD_NAME "tshell" -#define FINSH_USING_HISTORY -#define FINSH_HISTORY_LINES 5 -#define FINSH_USING_SYMTAB -#define FINSH_USING_DESCRIPTION -#define FINSH_THREAD_PRIORITY 20 -#define FINSH_THREAD_STACK_SIZE 2048 -#define FINSH_CMD_SIZE 80 -#define FINSH_USING_MSH -#define FINSH_USING_MSH_DEFAULT -#define FINSH_USING_MSH_ONLY -#define FINSH_ARG_MAX 10 - -/* Device virtual file system */ - - -/* Device Drivers */ - -#define RT_USING_DEVICE_IPC -#define RT_PIPE_BUFSZ 512 -#define RT_USING_SERIAL -#define RT_SERIAL_RB_BUFSZ 64 -#define RT_USING_PIN - -/* Using USB */ - - -/* POSIX layer and C standard library */ - - -/* Network */ - -/* Socket abstraction layer */ - - -/* Network interface device */ - - -/* light weight TCP/IP stack */ - - -/* AT commands */ - - -/* VBUS(Virtual Software BUS) */ - - -/* Utilities */ - - -/* RT-Thread online packages */ - -/* IoT - internet of things */ - - -/* Wi-Fi */ - -/* Marvell WiFi */ - - -/* Wiced WiFi */ - - -/* IoT Cloud */ - - -/* security packages */ - - -/* language packages */ - - -/* multimedia packages */ - - -/* tools packages */ - - -/* system packages */ - - -/* peripheral libraries and drivers */ - - -/* miscellaneous packages */ - - -/* samples: kernel and components samples */ - -#define SOC_ES8P508x - -/* Hardware Drivers Config */ - -/* On-chip Peripheral Drivers */ - -#define BSP_USING_GPIO - -/* UART Drivers */ - -#define BSP_USING_UART5 - -/* Onboard Peripheral Drivers */ - -/* Offboard Peripheral Drivers */ - - -#endif diff --git a/bsp/essemi/es8p508x/rtconfig.py b/bsp/essemi/es8p508x/rtconfig.py deleted file mode 100644 index eb371bf3a7..0000000000 --- a/bsp/essemi/es8p508x/rtconfig.py +++ /dev/null @@ -1,135 +0,0 @@ -import os -import sys - -# toolchains options -CROSS_TOOL = 'keil' - -if os.getenv('RTT_CC'): - CROSS_TOOL = os.getenv('RTT_CC') - -# device options -ARCH = 'arm' -CPU = 'cortex-m0' - -# cross_tool provides the cross compiler -# EXEC_PATH is the compiler execute path, for example, CodeSourcery, Keil MDK, IAR -if CROSS_TOOL == 'gcc': # not support gcc yet - PLATFORM = 'gcc' - EXEC_PATH = 'C:/GCC' - -elif CROSS_TOOL == 'keil': - PLATFORM = 'armcc' - EXEC_PATH = 'C:/Keil' - -elif CROSS_TOOL == 'iar': # not support iar yet - PLATFORM = 'iar' - EXEC_PATH = 'C:/IAR' - -if os.getenv('RTT_EXEC_PATH'): - EXEC_PATH = os.getenv('RTT_EXEC_PATH') - -BUILD = 'debug' -#BUILD = 'release' - -if PLATFORM == 'gcc': - # toolchains - PREFIX = 'arm-none-eabi-' - CC = PREFIX + 'gcc' - CXX = PREFIX + 'g++' - AS = PREFIX + 'gcc' - AR = PREFIX + 'ar' - LINK = PREFIX + 'gcc' - TARGET_EXT = 'elf' - SIZE = PREFIX + 'size' - OBJDUMP = PREFIX + 'objdump' - OBJCPY = PREFIX + 'objcopy' - DEVICE = ' -mcpu=' + CPU + ' -mthumb -ffunction-sections -fdata-sections' - CFLAGS = DEVICE - AFLAGS = ' -c' + DEVICE + ' -x assembler-with-cpp -Wa,-mimplicit-it=thumb' - LFLAGS = DEVICE + ' -Wl,--gc-sections,-Map=rtthread.map,-cref,-u,Reset_Handler -T drivers/linker_scripts/link.lds' - - CPATH = '' - LPATH = '' - - if BUILD == 'debug': - CFLAGS += ' -O0 -gdwarf-2 -g' - AFLAGS += ' -gdwarf-2' - else: - CFLAGS += ' -O2' - - POST_ACTION = OBJCPY + ' -O binary $TARGET rtthread.bin\n' + OBJCPY + ' -O ihex $TARGET rtthread.hex\n' + SIZE + ' $TARGET \n' -elif PLATFORM == 'armcc': - # toolchains - CC = 'armcc' - AS = 'armasm' - AR = 'armar' - LINK = 'armlink' - TARGET_EXT = 'axf' - - DEVICE = ' --device DARMSTM' - CFLAGS = '-c ' + DEVICE + ' --apcs=interwork --c99' - AFLAGS = DEVICE + ' --apcs=interwork ' - LFLAGS = DEVICE + ' --scatter "drivers/linker_scripts/link.sct" --info sizes --info totals --info unused --info veneers --list rtthread.map --strict' - - CFLAGS += ' -I' + EXEC_PATH + '/ARM/ARMCC/include' - LFLAGS += ' --libpath ' + EXEC_PATH + '/ARM/ARMCC/lib' - - CFLAGS += ' -D__MICROLIB ' - AFLAGS += ' --pd "__MICROLIB SETA 1" ' - LFLAGS += ' --library_type=microlib ' - EXEC_PATH += '/ARM/ARMCC/bin' - - if BUILD == 'debug': - CFLAGS += ' -g -O0' - AFLAGS += ' -g' - else: - CFLAGS += ' -O2' - - POST_ACTION = 'fromelf --bin $TARGET --output rtthread.bin \nfromelf -z $TARGET' - -elif PLATFORM == 'iar': - # toolchains - CC = 'iccarm' - AS = 'iasmarm' - AR = 'iarchive' - LINK = 'ilinkarm' - TARGET_EXT = 'out' - - DEVICE = '-Dewarm' - - CFLAGS = DEVICE - CFLAGS += ' --diag_suppress Pa050' - CFLAGS += ' --no_cse' - CFLAGS += ' --no_unroll' - CFLAGS += ' --no_inline' - CFLAGS += ' --no_code_motion' - CFLAGS += ' --no_tbaa' - CFLAGS += ' --no_clustering' - CFLAGS += ' --no_scheduling' - CFLAGS += ' --endian=little' - CFLAGS += ' --cpu=Cortex-M0' - CFLAGS += ' -e' - CFLAGS += ' --fpu=None' - CFLAGS += ' --dlib_config "' + EXEC_PATH + '/arm/INC/c/DLib_Config_Normal.h"' - CFLAGS += ' --silent' - - AFLAGS = DEVICE - AFLAGS += ' -s+' - AFLAGS += ' -w+' - AFLAGS += ' -r' - AFLAGS += ' --cpu Cortex-M0' - AFLAGS += ' --fpu None' - AFLAGS += ' -S' - - LFLAGS = ' --config "drivers\linker_scripts\link.icf"' - LFLAGS += ' --redirect _Printf=_PrintfTiny' - LFLAGS += ' --redirect _Scanf=_ScanfSmall' - if BUILD == 'debug': - CFLAGS += ' --debug' - CFLAGS += ' -On' - else: - CFLAGS += ' -Oh' - - LFLAGS += ' --entry __iar_program_start' - EXEC_PATH = EXEC_PATH + '/arm/bin/' - POST_ACTION = '' diff --git a/bsp/essemi/es8p508x/template.uvopt b/bsp/essemi/es8p508x/template.uvopt deleted file mode 100644 index 26bbe6a024..0000000000 --- a/bsp/essemi/es8p508x/template.uvopt +++ /dev/null @@ -1,174 +0,0 @@ - - - - 1.0 - -
### uVision Project, (C) Keil Software
- - - *.c - *.s*; *.src; *.a* - *.obj - *.lib - *.txt; *.h; *.inc - *.plm - *.cpp - - - - 0 - 0 - - - - rt-thread - 0x4 - ARM-ADS - - 20000000 - - 1 - 1 - 1 - 0 - - - 1 - 65535 - 0 - 0 - 0 - - - 79 - 66 - 8 - .\build\keil\ - - - 1 - 1 - 1 - 0 - 1 - 1 - 0 - 1 - 0 - 0 - 0 - 0 - - - 1 - 1 - 1 - 1 - 1 - 1 - 1 - 0 - 0 - - - 0 - 0 - 1 - - 0 - - SARMCM3.DLL - - DARMCM1.DLL - -pCM0 - SARMCM3.DLL - - TARMCM1.DLL - - - - 0 - 1 - 1 - 1 - 1 - 1 - 1 - 1 - 1 - 1 - 1 - 1 - 1 - 1 - 0 - 1 - 0 - 0 - 1 - 13 - - - - - - - - - - - BIN\CMSIS_AGDI.dll - - - - 0 - JL2CM3 - -U12345678 -O78 -S0 -A0 -C0 -JU1 -JI127.0.0.1 -JP0 -RST0 -N00("ARM CoreSight SW-DP") -D00(0BB11477) -L00(0) -TO18 -TC10000000 -TP21 -TDS8007 -TDT0 -TDC1F -TIEFFFFFFFF -TIP8 -TB1 -TFE0 -FO15 -FD20000000 -FC800 -FN1 -FF0ES8P508x -FS00 -FL020000 - - - 0 - CMSIS_AGDI - -X"essemi CMSIS-DAP" -U0001A000000A -O207 -S0 -C0 -P00 -N00("ARM CoreSight SW-DP") -D00(0BB11477) -L00(0) -FO15 -FD20000000 -FC6000 -FN1 -FF0ES8P508x -FS00 -FL020000 - - - 0 - UL2CM3 - UL2CM3(-O207 -S0 -C0 -FO7 -FD20000000 -FC6000 -FN1 -FF0ES8P508x -FS00000000 -FL020000) - - - - - 0 - - - 0 - 0 - 0 - 0 - 0 - 0 - 0 - 0 - 0 - 0 - 0 - 0 - 0 - 0 - 0 - 0 - 0 - 0 - 0 - 0 - 0 - 0 - 0 - 0 - - - - - - - diff --git a/bsp/essemi/es8p508x/template.uvproj b/bsp/essemi/es8p508x/template.uvproj deleted file mode 100644 index fe2d881412..0000000000 --- a/bsp/essemi/es8p508x/template.uvproj +++ /dev/null @@ -1,400 +0,0 @@ - - - - 1.1 - -
### uVision Project, (C) Keil Software
- - - - rt-thread - 0x4 - ARM-ADS - - - ES8P508xFLXX - ES - IRAM(0x20000000-0x20005FFF) IROM(0x00000000-0x0001FFFF) CLOCK(20000000) CPUTYPE("Cortex-M0") - - "STARTUP\HR\startup_ES8P508x.s" ("ES8P508x Startup Code") - UL2CM3(-O207 -S0 -C0 -FO7 -FD20000000 -FC6000 -FN1 -FF0ES8P508x -FS00000000 -FL020000) - 0 - ES8P508x.h - - - - - - - - - - SFD\HR\ES8P508x.SFR - 0 - 0 - - - - HR\ - HR\ - - 0 - 0 - 0 - 0 - 1 - - .\build\keil\ - rt-thread - 1 - 0 - 0 - 1 - 1 - .\build\keil\ - 1 - 0 - 0 - - 0 - 0 - - - 0 - 0 - 0 - 0 - - - 0 - 0 - - - 0 - 0 - - - 1 - 0 - fromelf --bin !L --output rtthread.bin - fromelf --text -c ".\build\keil\@L.axf" --output ".\build\keil\@L.txt" - 0 - 0 - - 0 - - - - 0 - 0 - 0 - 0 - 0 - 1 - 0 - 0 - 0 - 0 - 3 - - - 1 - - - SARMCM3.DLL - - DARMCM1.DLL - -pCM0 - SARMCM3.DLL - - TARMCM1.DLL - - - - - 1 - 0 - 0 - 0 - 16 - - - 0 - 1 - 1 - 1 - 1 - 1 - 1 - 1 - 1 - - - 1 - 1 - 1 - 1 - 1 - 1 - 0 - 1 - 0 - - 0 - 13 - - - - - - - - - - - - - - BIN\CMSIS_AGDI.dll - - - - - 1 - 0 - 0 - 1 - 1 - 4096 - - 1 - BIN\UL2CM3.DLL - "" () - - - - - 0 - - - - 0 - 1 - 1 - 1 - 1 - 1 - 1 - 1 - 0 - 1 - 1 - 0 - 0 - 1 - 0 - 0 - 1 - 1 - 1 - 1 - 1 - 1 - 1 - 1 - 1 - 0 - 0 - "Cortex-M0" - - 0 - 0 - 0 - 1 - 1 - 0 - 0 - 0 - 0 - 0 - 8 - 0 - 0 - 0 - 3 - 5 - 0 - 0 - 0 - 0 - 0 - 0 - 0 - 0 - 0 - 0 - 1 - 0 - 0 - 0 - 0 - 1 - 0 - - - 0 - 0x0 - 0x0 - - - 0 - 0x0 - 0x0 - - - 0 - 0x0 - 0x0 - - - 0 - 0x0 - 0x0 - - - 0 - 0x0 - 0x0 - - - 0 - 0x0 - 0x0 - - - 0 - 0x20000000 - 0x6000 - - - 1 - 0x0 - 0x20000 - - - 0 - 0x0 - 0x0 - - - 1 - 0x0 - 0x0 - - - 1 - 0x0 - 0x0 - - - 1 - 0x0 - 0x0 - - - 1 - 0x0 - 0x20000 - - - 1 - 0x0 - 0x0 - - - 0 - 0x0 - 0x0 - - - 0 - 0x0 - 0x0 - - - 0 - 0x0 - 0x0 - - - 0 - 0x20000000 - 0x6000 - - - 0 - 0x0 - 0x0 - - - - - - 1 - 1 - 0 - 0 - 1 - 0 - 0 - 0 - 0 - 0 - 0 - 0 - 0 - - --c99 - - - - - - - 1 - 0 - 0 - 0 - 0 - 0 - 0 - 0 - - - - - - - - - 1 - 0 - 0 - 0 - 1 - 0 - 0x00000000 - 0x20000000 - - - - --map --first='startup_M451Series.o(RESET)' --datacompressor=off --info=inline --entry Reset_Handler - - - - - - - - - -- cgit v1.3.1 From 056caf7a2f559b931efd93e16992a8bd060bcc5b Mon Sep 17 00:00:00 2001 From: liuhy Date: Fri, 10 Sep 2021 18:01:04 +0800 Subject: delete essemi bsp es32f0271 (libraries) --- .../CMSIS/CMSIS_END_USER_LICENCE_AGREEMENT.pdf | Bin 172641 -> 0 bytes .../CMSIS/CMSIS_END_USER_LICENCE_AGREEMENT.rtf | 793 --- .../ES32F0271/Include/ES32F0271/reg_ad16c4t.h | 683 -- .../EastSoft/ES32F0271/Include/ES32F0271/reg_adc.h | 795 --- .../EastSoft/ES32F0271/Include/ES32F0271/reg_aes.h | 193 - .../EastSoft/ES32F0271/Include/ES32F0271/reg_cmp.h | 95 - .../EastSoft/ES32F0271/Include/ES32F0271/reg_crc.h | 125 - .../EastSoft/ES32F0271/Include/ES32F0271/reg_dac.h | 97 - .../EastSoft/ES32F0271/Include/ES32F0271/reg_dma.h | 825 --- .../ES32F0271/Include/ES32F0271/reg_exti.h | 809 --- .../EastSoft/ES32F0271/Include/ES32F0271/reg_fc.h | 181 - .../ES32F0271/Include/ES32F0271/reg_gpio.h | 710 -- .../ES32F0271/Include/ES32F0271/reg_hdiv.h | 75 - .../EastSoft/ES32F0271/Include/ES32F0271/reg_i2c.h | 623 -- .../ES32F0271/Include/ES32F0271/reg_iwdg.h | 73 - .../EastSoft/ES32F0271/Include/ES32F0271/reg_mcm.h | 211 - .../ES32F0271/Include/ES32F0271/reg_mswd.h | 58 - .../EastSoft/ES32F0271/Include/ES32F0271/reg_rcu.h | 585 -- .../EastSoft/ES32F0271/Include/ES32F0271/reg_rtc.h | 613 -- .../EastSoft/ES32F0271/Include/ES32F0271/reg_spi.h | 444 -- .../ES32F0271/Include/ES32F0271/reg_syscfg.h | 215 - .../ES32F0271/Include/ES32F0271/reg_tick.h | 113 - .../ES32F0271/Include/ES32F0271/reg_uart.h | 606 -- .../EastSoft/ES32F0271/Include/ES32F0271/reg_usb.h | 873 --- .../ES32F0271/Include/ES32F0271/reg_wwdg.h | 88 - .../ES32F0271/Include/ES32F0271/reg_wwdt.h | 92 - .../Device/EastSoft/ES32F0271/Include/es32f0271.h | 389 -- .../Device/EastSoft/ES32F0271/Include/rt_misc.h | 183 - .../Device/EastSoft/ES32F0271/ReleaseNote.html | 16 - .../ES32F0271/Startup/iar/startup_es32f027x.s | 256 - .../Device/EastSoft/ES32F0271/Startup/keil/boot.c | 321 - .../ES32F0271/Startup/keil/startup_es32f027x.s | 244 - .../Device/EastSoft/ES32F0271/System/core_cm0.c | 472 -- .../Device/EastSoft/ES32F0271/System/retarget.c | 55 - .../EastSoft/ES32F0271/System/system_es32f027x.c | 79 - .../EastSoft/ES32F0271/System/system_es32f027x.h | 83 - .../libraries/CMSIS/Include/arm_common_tables.h | 121 - .../libraries/CMSIS/Include/arm_const_structs.h | 66 - .../es32f0271/libraries/CMSIS/Include/arm_math.h | 7157 -------------------- .../libraries/CMSIS/Include/cmsis_armcc.h | 870 --- .../libraries/CMSIS/Include/cmsis_armclang.h | 1877 ----- .../libraries/CMSIS/Include/cmsis_compiler.h | 266 - .../es32f0271/libraries/CMSIS/Include/cmsis_gcc.h | 2088 ------ .../libraries/CMSIS/Include/cmsis_iccarm.h | 913 --- .../libraries/CMSIS/Include/cmsis_version.h | 39 - .../libraries/CMSIS/Include/core_armv8mbl.h | 1896 ------ .../libraries/CMSIS/Include/core_armv8mml.h | 2960 -------- .../es32f0271/libraries/CMSIS/Include/core_cm0.h | 888 --- .../libraries/CMSIS/Include/core_cm0plus.h | 1023 --- .../es32f0271/libraries/CMSIS/Include/core_cm23.h | 1899 ------ .../es32f0271/libraries/CMSIS/Include/core_cm3.h | 1933 ------ .../es32f0271/libraries/CMSIS/Include/core_cm33.h | 2963 -------- .../es32f0271/libraries/CMSIS/Include/core_cm4.h | 2118 ------ .../es32f0271/libraries/CMSIS/Include/core_cm7.h | 2660 -------- .../es32f0271/libraries/CMSIS/Include/core_sc000.h | 1016 --- .../es32f0271/libraries/CMSIS/Include/core_sc300.h | 1903 ------ .../es32f0271/libraries/CMSIS/Include/mpu_armv7.h | 197 - .../es32f0271/libraries/CMSIS/Include/mpu_armv8.h | 333 - .../es32f0271/libraries/CMSIS/Include/tz_context.h | 70 - .../libraries/CMSIS/RTOS/Template/cmsis_os.h | 707 -- bsp/essemi/es32f0271/libraries/CMSIS/index.html | 14 - .../Include/md_ad16c4t.h | 4484 ------------ .../ES32F027x_MD_StdPeriph_Driver/Include/md_adc.h | 6109 ----------------- .../ES32F027x_MD_StdPeriph_Driver/Include/md_aes.h | 941 --- .../ES32F027x_MD_StdPeriph_Driver/Include/md_cmp.h | 573 -- .../ES32F027x_MD_StdPeriph_Driver/Include/md_crc.h | 519 -- .../ES32F027x_MD_StdPeriph_Driver/Include/md_dac.h | 290 - .../ES32F027x_MD_StdPeriph_Driver/Include/md_dma.h | 5561 --------------- .../Include/md_exti.h | 5167 -------------- .../ES32F027x_MD_StdPeriph_Driver/Include/md_fc.h | 832 --- .../Include/md_gpio.h | 2873 -------- .../Include/md_hdiv.h | 292 - .../ES32F027x_MD_StdPeriph_Driver/Include/md_i2c.h | 3273 --------- .../ES32F027x_MD_StdPeriph_Driver/Include/md_rcu.h | 5804 ---------------- .../ES32F027x_MD_StdPeriph_Driver/Include/md_rtc.h | 2785 -------- .../ES32F027x_MD_StdPeriph_Driver/Include/md_spi.h | 2523 ------- .../Include/md_syscfg.h | 1249 ---- .../Include/md_tick.h | 433 -- .../Include/md_uart.h | 2874 -------- .../Include/md_wwdt.h | 382 -- .../Include/usb_lowlayer_api.h | 728 -- .../ES32F027x_MD_StdPeriph_Driver/ReleaseNote.html | 17 - .../ES32F027x_MD_StdPeriph_Driver/Source/md_adc.c | 298 - .../ES32F027x_MD_StdPeriph_Driver/Source/md_fc.c | 300 - .../ES32F027x_MD_StdPeriph_Driver/Source/md_gpio.c | 215 - .../ES32F027x_MD_StdPeriph_Driver/Source/md_i2c.c | 245 - .../ES32F027x_MD_StdPeriph_Driver/Source/md_rcu.c | 378 -- .../ES32F027x_MD_StdPeriph_Driver/Source/md_spi.c | 108 - .../ES32F027x_MD_StdPeriph_Driver/Source/md_tick.c | 207 - .../ES32F027x_MD_StdPeriph_Driver/Source/md_uart.c | 127 - .../ES32F027x_MD_StdPeriph_Driver/Source/md_usb.c | 3804 ----------- .../ES32F027x_MD_StdPeriph_Driver/Source/md_wwdt.c | 86 - bsp/essemi/es32f0271/libraries/SConscript | 32 - .../es32f0271/libraries/usblib/drivers/type.h | 41 - .../libraries/usblib/drivers/usb_lowlayer_api.h | 728 -- 95 files changed, 102328 deletions(-) delete mode 100644 bsp/essemi/es32f0271/libraries/CMSIS/CMSIS_END_USER_LICENCE_AGREEMENT.pdf delete mode 100644 bsp/essemi/es32f0271/libraries/CMSIS/CMSIS_END_USER_LICENCE_AGREEMENT.rtf delete mode 100644 bsp/essemi/es32f0271/libraries/CMSIS/Device/EastSoft/ES32F0271/Include/ES32F0271/reg_ad16c4t.h delete mode 100644 bsp/essemi/es32f0271/libraries/CMSIS/Device/EastSoft/ES32F0271/Include/ES32F0271/reg_adc.h delete mode 100644 bsp/essemi/es32f0271/libraries/CMSIS/Device/EastSoft/ES32F0271/Include/ES32F0271/reg_aes.h delete mode 100644 bsp/essemi/es32f0271/libraries/CMSIS/Device/EastSoft/ES32F0271/Include/ES32F0271/reg_cmp.h delete mode 100644 bsp/essemi/es32f0271/libraries/CMSIS/Device/EastSoft/ES32F0271/Include/ES32F0271/reg_crc.h delete mode 100644 bsp/essemi/es32f0271/libraries/CMSIS/Device/EastSoft/ES32F0271/Include/ES32F0271/reg_dac.h delete mode 100644 bsp/essemi/es32f0271/libraries/CMSIS/Device/EastSoft/ES32F0271/Include/ES32F0271/reg_dma.h delete mode 100644 bsp/essemi/es32f0271/libraries/CMSIS/Device/EastSoft/ES32F0271/Include/ES32F0271/reg_exti.h delete mode 100644 bsp/essemi/es32f0271/libraries/CMSIS/Device/EastSoft/ES32F0271/Include/ES32F0271/reg_fc.h delete mode 100644 bsp/essemi/es32f0271/libraries/CMSIS/Device/EastSoft/ES32F0271/Include/ES32F0271/reg_gpio.h delete mode 100644 bsp/essemi/es32f0271/libraries/CMSIS/Device/EastSoft/ES32F0271/Include/ES32F0271/reg_hdiv.h delete mode 100644 bsp/essemi/es32f0271/libraries/CMSIS/Device/EastSoft/ES32F0271/Include/ES32F0271/reg_i2c.h delete mode 100644 bsp/essemi/es32f0271/libraries/CMSIS/Device/EastSoft/ES32F0271/Include/ES32F0271/reg_iwdg.h delete mode 100644 bsp/essemi/es32f0271/libraries/CMSIS/Device/EastSoft/ES32F0271/Include/ES32F0271/reg_mcm.h delete mode 100644 bsp/essemi/es32f0271/libraries/CMSIS/Device/EastSoft/ES32F0271/Include/ES32F0271/reg_mswd.h delete mode 100644 bsp/essemi/es32f0271/libraries/CMSIS/Device/EastSoft/ES32F0271/Include/ES32F0271/reg_rcu.h delete mode 100644 bsp/essemi/es32f0271/libraries/CMSIS/Device/EastSoft/ES32F0271/Include/ES32F0271/reg_rtc.h delete mode 100644 bsp/essemi/es32f0271/libraries/CMSIS/Device/EastSoft/ES32F0271/Include/ES32F0271/reg_spi.h delete mode 100644 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bsp/essemi/es32f0271/libraries/CMSIS/Device/EastSoft/ES32F0271/Startup/iar/startup_es32f027x.s delete mode 100644 bsp/essemi/es32f0271/libraries/CMSIS/Device/EastSoft/ES32F0271/Startup/keil/boot.c delete mode 100644 bsp/essemi/es32f0271/libraries/CMSIS/Device/EastSoft/ES32F0271/Startup/keil/startup_es32f027x.s delete mode 100644 bsp/essemi/es32f0271/libraries/CMSIS/Device/EastSoft/ES32F0271/System/core_cm0.c delete mode 100644 bsp/essemi/es32f0271/libraries/CMSIS/Device/EastSoft/ES32F0271/System/retarget.c delete mode 100644 bsp/essemi/es32f0271/libraries/CMSIS/Device/EastSoft/ES32F0271/System/system_es32f027x.c delete mode 100644 bsp/essemi/es32f0271/libraries/CMSIS/Device/EastSoft/ES32F0271/System/system_es32f027x.h delete mode 100644 bsp/essemi/es32f0271/libraries/CMSIS/Include/arm_common_tables.h delete mode 100644 bsp/essemi/es32f0271/libraries/CMSIS/Include/arm_const_structs.h delete mode 100644 bsp/essemi/es32f0271/libraries/CMSIS/Include/arm_math.h delete mode 100644 bsp/essemi/es32f0271/libraries/CMSIS/Include/cmsis_armcc.h delete mode 100644 bsp/essemi/es32f0271/libraries/CMSIS/Include/cmsis_armclang.h delete mode 100644 bsp/essemi/es32f0271/libraries/CMSIS/Include/cmsis_compiler.h delete mode 100644 bsp/essemi/es32f0271/libraries/CMSIS/Include/cmsis_gcc.h delete mode 100644 bsp/essemi/es32f0271/libraries/CMSIS/Include/cmsis_iccarm.h delete mode 100644 bsp/essemi/es32f0271/libraries/CMSIS/Include/cmsis_version.h delete mode 100644 bsp/essemi/es32f0271/libraries/CMSIS/Include/core_armv8mbl.h delete mode 100644 bsp/essemi/es32f0271/libraries/CMSIS/Include/core_armv8mml.h delete mode 100644 bsp/essemi/es32f0271/libraries/CMSIS/Include/core_cm0.h delete mode 100644 bsp/essemi/es32f0271/libraries/CMSIS/Include/core_cm0plus.h delete mode 100644 bsp/essemi/es32f0271/libraries/CMSIS/Include/core_cm23.h delete mode 100644 bsp/essemi/es32f0271/libraries/CMSIS/Include/core_cm3.h delete mode 100644 bsp/essemi/es32f0271/libraries/CMSIS/Include/core_cm33.h delete mode 100644 bsp/essemi/es32f0271/libraries/CMSIS/Include/core_cm4.h delete mode 100644 bsp/essemi/es32f0271/libraries/CMSIS/Include/core_cm7.h delete mode 100644 bsp/essemi/es32f0271/libraries/CMSIS/Include/core_sc000.h delete mode 100644 bsp/essemi/es32f0271/libraries/CMSIS/Include/core_sc300.h delete mode 100644 bsp/essemi/es32f0271/libraries/CMSIS/Include/mpu_armv7.h delete mode 100644 bsp/essemi/es32f0271/libraries/CMSIS/Include/mpu_armv8.h delete mode 100644 bsp/essemi/es32f0271/libraries/CMSIS/Include/tz_context.h delete mode 100644 bsp/essemi/es32f0271/libraries/CMSIS/RTOS/Template/cmsis_os.h delete mode 100644 bsp/essemi/es32f0271/libraries/CMSIS/index.html delete mode 100644 bsp/essemi/es32f0271/libraries/ES32F027x_MD_StdPeriph_Driver/Include/md_ad16c4t.h delete mode 100644 bsp/essemi/es32f0271/libraries/ES32F027x_MD_StdPeriph_Driver/Include/md_adc.h delete mode 100644 bsp/essemi/es32f0271/libraries/ES32F027x_MD_StdPeriph_Driver/Include/md_aes.h delete mode 100644 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bsp/essemi/es32f0271/libraries/ES32F027x_MD_StdPeriph_Driver/Source/md_gpio.c delete mode 100644 bsp/essemi/es32f0271/libraries/ES32F027x_MD_StdPeriph_Driver/Source/md_i2c.c delete mode 100644 bsp/essemi/es32f0271/libraries/ES32F027x_MD_StdPeriph_Driver/Source/md_rcu.c delete mode 100644 bsp/essemi/es32f0271/libraries/ES32F027x_MD_StdPeriph_Driver/Source/md_spi.c delete mode 100644 bsp/essemi/es32f0271/libraries/ES32F027x_MD_StdPeriph_Driver/Source/md_tick.c delete mode 100644 bsp/essemi/es32f0271/libraries/ES32F027x_MD_StdPeriph_Driver/Source/md_uart.c delete mode 100644 bsp/essemi/es32f0271/libraries/ES32F027x_MD_StdPeriph_Driver/Source/md_usb.c delete mode 100644 bsp/essemi/es32f0271/libraries/ES32F027x_MD_StdPeriph_Driver/Source/md_wwdt.c delete mode 100644 bsp/essemi/es32f0271/libraries/SConscript delete mode 100644 bsp/essemi/es32f0271/libraries/usblib/drivers/type.h delete mode 100644 bsp/essemi/es32f0271/libraries/usblib/drivers/usb_lowlayer_api.h (limited to 'bsp') diff --git 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\fs18\loch\af1\hich\af1\dbch\af1\insrsid11754636 -\hich\af1\dbch\af1\loch\f1 NUMPAGES}}{\fldrslt {\rtlch\fcs1 \af1 \ltrch\fcs0 \fs18\lang1024\langfe1024\loch\af1\hich\af1\dbch\af1\noproof\insrsid9508363 \hich\af1\dbch\af1\loch\f1 4}}}\sectd \ltrsect\linex0\endnhere\sectdefaultcl\sftnbj {\rtlch\fcs1 \af1 -\ltrch\fcs0 \fs18\loch\af1\hich\af1\dbch\af1\insrsid11754636 \cell \cell }\pard \ltrpar\ql \li0\ri0\widctlpar\intbl\wrapdefault\aspalpha\aspnum\faauto\adjustright\rin0\lin0 {\rtlch\fcs1 \af1 \ltrch\fcs0 \fs18\loch\af1\hich\af1\dbch\af1\insrsid11754636 -\trowd \irow0\irowband0\lastrow \ltrrow\ts11\trgaph108\trrh240\trleft-108\trftsWidth1\trautofit1\trpaddl108\trpaddr108\trpaddfl3\trpaddfr3\tblind0\tblindtype3 \clvertalt\clbrdrt\brdrtbl \clbrdrl\brdrtbl \clbrdrb\brdrtbl \clbrdrr\brdrtbl -\cltxlrtb\clftsWidth3\clwWidth4513\clshdrawnil \cellx4405\clvertalt\clbrdrt\brdrtbl \clbrdrl\brdrtbl \clbrdrb\brdrtbl \clbrdrr\brdrtbl \cltxlrtb\clftsWidth3\clwWidth4513\clshdrawnil \cellx8918\row }\pard \ltrpar\ql \li0\ri0\sa200\sl276\slmult1 -\widctlpar\wrapdefault\aspalpha\aspnum\faauto\adjustright\rin0\lin0\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid11754636 -\par }}{\*\pnseclvl1\pnucrm\pnstart1\pnindent720\pnhang {\pntxta .}}{\*\pnseclvl2\pnucltr\pnstart1\pnindent720\pnhang {\pntxta .}}{\*\pnseclvl3\pndec\pnstart1\pnindent720\pnhang {\pntxta .}}{\*\pnseclvl4\pnlcltr\pnstart1\pnindent720\pnhang {\pntxta )}} -{\*\pnseclvl5\pndec\pnstart1\pnindent720\pnhang {\pntxtb (}{\pntxta )}}{\*\pnseclvl6\pnlcltr\pnstart1\pnindent720\pnhang {\pntxtb (}{\pntxta )}}{\*\pnseclvl7\pnlcrm\pnstart1\pnindent720\pnhang {\pntxtb (}{\pntxta )}}{\*\pnseclvl8 -\pnlcltr\pnstart1\pnindent720\pnhang {\pntxtb (}{\pntxta )}}{\*\pnseclvl9\pnlcrm\pnstart1\pnindent720\pnhang {\pntxtb (}{\pntxta )}}\pard\plain \ltrpar\qj \li0\ri0\sa240\widctlpar -\tx916\tx1832\tx2748\tx3664\tx4580\tx5496\tx6412\tx7328\tx8244\tx9160\tx10076\tx10992\tx11908\tx12824\tx13740\tx14656\wrapdefault\aspalpha\aspnum\faauto\adjustright\rin0\lin0\itap0\pararsid11754636 \cbpat8 \rtlch\fcs1 \af0\afs22\alang1025 \ltrch\fcs0 -\fs22\lang2057\langfe1033\loch\af37\hich\af37\dbch\af37\cgrid\langnp2057\langfenp1033 {\rtlch\fcs1 \af1\afs18 \ltrch\fcs0 \f1\fs18\cf1\lang2057\langfe2057\langfenp2057\insrsid11754636\charrsid15280636 END USER LICENCE AGREEMENT FOR THE }{\rtlch\fcs1 -\af1\afs18 \ltrch\fcs0 \f1\fs18\cf1\lang2057\langfe2057\langfenp2057\insrsid11754636 CORTEX MICROCONTROLLER SOFTWARE INTERFACE STANDARD (CMSIS) DELIVERABLES }{\rtlch\fcs1 \af1\afs18 \ltrch\fcs0 -\f1\fs18\cf1\lang2057\langfe2057\langfenp2057\insrsid11754636\charrsid15280636 -\par THIS END USER LICENCE AGREEMENT ("LICENCE") IS A LEGAL AGREEMENT BETWEEN YOU (EITHER A }{\rtlch\fcs1 \af1\afs18 \ltrch\fcs0 \f1\fs18\cf1\lang2057\langfe2057\langfenp2057\insrsid11754636\charrsid5861575 -SINGLE INDIVIDUAL, OR SINGLE LEGAL ENTITY) AND ARM LIMITED ("ARM") FOR THE USE OF THE CMSIS }{\rtlch\fcs1 \af1\afs18 \ltrch\fcs0 \f1\fs18\cf1\lang2057\langfe2057\langfenp2057\insrsid11754636 DELIVERABLES}{\rtlch\fcs1 \af1\afs18 \ltrch\fcs0 -\f1\fs18\cf1\lang2057\langfe2057\langfenp2057\insrsid11754636\charrsid5861575 . ARM IS ONLY WILLING TO LICENSE THE }{\rtlch\fcs1 \af1\afs18 \ltrch\fcs0 \f1\fs18\cf1\lang2057\langfe2057\langfenp2057\insrsid11754636 CMSIS DELIVERABLES }{\rtlch\fcs1 -\af1\afs18 \ltrch\fcs0 \f1\fs18\cf1\lang2057\langfe2057\langfenp2057\insrsid11754636\charrsid5861575 TO YOU ON CONDITION THAT YOU ACCEPT ALL OF THE}{\rtlch\fcs1 \af1\afs18 \ltrch\fcs0 -\f1\fs18\cf1\lang2057\langfe2057\langfenp2057\insrsid11754636\charrsid15280636 TERMS IN THIS LICENCE. BY CLICKING "I AGREE", OR BY INSTALLING OR OTHERWISE USING OR COPYING THE }{\rtlch\fcs1 \af1\afs18 \ltrch\fcs0 -\f1\fs18\cf1\lang2057\langfe2057\langfenp2057\insrsid11754636 CMSIS DELIVERABLES }{\rtlch\fcs1 \af1\afs18 \ltrch\fcs0 \f1\fs18\cf1\lang2057\langfe2057\langfenp2057\insrsid11754636\charrsid15280636 -YOU INDICATE THAT YOU AGREE TO BE BOUND BY ALL THE TERMS OF THIS LICENCE. IF YOU DO NOT AGREE TO THE TERMS OF THIS LICENCE, ARM IS UNWILLING TO LICENSE YOU TO USE }{\rtlch\fcs1 \af1\afs18 \ltrch\fcs0 -\f1\fs18\cf1\lang2057\langfe2057\langfenp2057\insrsid11754636 OF }{\rtlch\fcs1 \af1\afs18 \ltrch\fcs0 \f1\fs18\cf1\lang2057\langfe2057\langfenp2057\insrsid11754636\charrsid15280636 THE }{\rtlch\fcs1 \af1\afs18 \ltrch\fcs0 -\f1\fs18\cf1\lang2057\langfe2057\langfenp2057\insrsid11754636 CMSIS DELIVERABLES}{\rtlch\fcs1 \af1\afs18 \ltrch\fcs0 \f1\fs18\cf1\lang2057\langfe2057\langfenp2057\insrsid11754636\charrsid15280636 AND YOU MAY NOT INSTALL, USE OR COPY THE }{\rtlch\fcs1 -\af1\afs18 \ltrch\fcs0 \f1\fs18\cf1\lang2057\langfe2057\langfenp2057\insrsid11754636 CMSIS DELIVERABLES}{\rtlch\fcs1 \af1\afs18 \ltrch\fcs0 \f1\fs18\cf1\lang2057\langfe2057\langfenp2057\insrsid11754636\charrsid15280636 . -\par }\pard \ltrpar\qj \li0\ri0\sa200\sl276\slmult1\widctlpar\wrapdefault\aspalpha\aspnum\faauto\adjustright\rin0\lin0\itap0\pararsid11754636 {\rtlch\fcs1 \af1\afs18 \ltrch\fcs0 \f1\fs18\cf1\lang2057\langfe2057\langfenp2057\insrsid11754636 \'93 -CMSIS Deliverables\'94 means the following components: (i) CMSIS-CORE; (ii) CMSIS-DRIVER; (iii) CMSIS-DSP; (iv) CMSIS-PACK; (v) CMSIS-RTOS API; and (vi) CMSIS-SVD . -\par }\pard \ltrpar\qj \li0\ri0\sa200\sl276\slmult1\widctlpar\tx0\wrapdefault\aspalpha\aspnum\faauto\adjustright\rin0\lin0\itap0\pararsid11754636 {\rtlch\fcs1 \af1\afs18 \ltrch\fcs0 \f1\fs18\cf1\lang2057\langfe2057\langfenp2057\insrsid11754636 \'93CMSIS-CORE -\'94 means the specification defining the application programming interface, naming and coding conventions for the Cortex-M processor cores. -\par \'94}{\rtlch\fcs1 \af1\afs18 \ltrch\fcs0 \f1\fs18\insrsid11754636\charrsid488451 \hich\af1\dbch\af37\loch\f1 CMSIS-DRIVER}{\rtlch\fcs1 \af1\afs18 \ltrch\fcs0 \f1\fs18\cf1\lang2057\langfe2057\langfenp2057\insrsid11754636 \'94}{\rtlch\fcs1 \af0 \ltrch\fcs0 -\insrsid11754636 \hich\af37\dbch\af37\loch\f37 }{\rtlch\fcs1 \af1\afs18 \ltrch\fcs0 \f1\fs18\insrsid11754636\charrsid488451 \hich\af1\dbch\af37\loch\f1 means the specification defining }{\rtlch\fcs1 \af1\afs18 \ltrch\fcs0 \f1\fs18\insrsid11754636 -\hich\af1\dbch\af37\loch\f1 a generic}{\rtlch\fcs1 \af1\afs18 \ltrch\fcs0 \f1\fs18\insrsid11754636\charrsid488451 \hich\af1\dbch\af37\loch\f1 }{\rtlch\fcs1 \af1\afs18 \ltrch\fcs0 \f1\fs18\insrsid11754636 \hich\af1\dbch\af37\loch\f1 p}{\rtlch\fcs1 -\af1\afs18 \ltrch\fcs0 \f1\fs18\insrsid11754636\charrsid488451 \hich\af1\dbch\af37\loch\f1 eripheral }{\rtlch\fcs1 \af1\afs18 \ltrch\fcs0 \f1\fs18\insrsid11754636 \hich\af1\dbch\af37\loch\f1 d}{\rtlch\fcs1 \af1\afs18 \ltrch\fcs0 -\f1\fs18\insrsid11754636\charrsid488451 \hich\af1\dbch\af37\loch\f1 river application programming interface, naming and coding conventions}{\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid11754636 . -\par }\pard \ltrpar\qj \li0\ri0\sa200\sl276\slmult1\widctlpar\wrapdefault\aspalpha\aspnum\faauto\adjustright\rin0\lin0\itap0\pararsid11754636 {\rtlch\fcs1 \af1\afs18 \ltrch\fcs0 \f1\fs18\cf1\lang2057\langfe2057\langfenp2057\insrsid11754636 \'93CMSIS-DSP\'94 - means the digital signal process (DSP) library specification defining the application programming interface of a DSP library implementation}{\rtlch\fcs1 \af1\afs18 \ltrch\fcs0 -\f1\fs18\cf1\lang2057\langfe2057\langfenp2057\insrsid11754636\charrsid15023647 .}{\rtlch\fcs1 \af1\afs18 \ltrch\fcs0 \f1\fs18\cf1\lang2057\langfe2057\langfenp2057\insrsid11754636 -\par }\pard \ltrpar\qj \li0\ri0\sa200\sl276\slmult1\widctlpar\tx0\wrapdefault\aspalpha\aspnum\faauto\adjustright\rin0\lin0\itap0\pararsid11754636 {\rtlch\fcs1 \af1\afs18 \ltrch\fcs0 \f1\fs18\cf1\lang2057\langfe2057\langfenp2057\insrsid11754636 \'93}{ -\rtlch\fcs1 \af1\afs18 \ltrch\fcs0 \f1\fs18\insrsid11754636\charrsid13240697 \hich\af1\dbch\af37\loch\f1 CMSIS-PACK}{\rtlch\fcs1 \af1\afs18 \ltrch\fcs0 \f1\fs18\cf1\lang2057\langfe2057\langfenp2057\insrsid11754636 \'94}{\rtlch\fcs1 \af0 \ltrch\fcs0 -\insrsid11754636\charrsid13240697 \hich\af37\dbch\af37\loch\f37 }{\rtlch\fcs1 \af1\afs18 \ltrch\fcs0 \f1\fs18\insrsid11754636\charrsid13240697 \hich\af1\dbch\af37\loch\f1 means the specification defining a software pack file format}{\rtlch\fcs1 -\af1\afs18 \ltrch\fcs0 \f1\fs18\insrsid11754636 \hich\af1\dbch\af37\loch\f1 , verification utility, }{\rtlch\fcs1 \af1\afs18 \ltrch\fcs0 \f1\fs18\insrsid11754636\charrsid13240697 \hich\af1\dbch\af37\loch\f1 and the associated XML schema file}{\rtlch\fcs1 -\af0 \ltrch\fcs0 \insrsid11754636\charrsid13240697 .}{\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid11754636 -\par }{\rtlch\fcs1 \af1\afs18 \ltrch\fcs0 \f1\fs18\cf1\lang2057\langfe2057\langfenp2057\insrsid11754636 \'93CMSIS-RTOS API\'94 means the - real-time operating system (RTOS) specification defining a generic application programming interface layer for a RTOS system}{\rtlch\fcs1 \af1\afs18 \ltrch\fcs0 \f1\fs18\cf1\lang2057\langfe2057\langfenp2057\insrsid11754636\charrsid15023647 .}{ -\rtlch\fcs1 \af1\afs18 \ltrch\fcs0 \f1\fs18\cf1\lang2057\langfe2057\langfenp2057\insrsid11754636 -\par }\pard \ltrpar\qj \li0\ri0\sa200\sl276\slmult1\widctlpar\wrapdefault\aspalpha\aspnum\faauto\adjustright\rin0\lin0\itap0\pararsid11754636 {\rtlch\fcs1 \af1\afs18 \ltrch\fcs0 \f1\fs18\insrsid11754636\charrsid4029239 \hich\af1\dbch\af37\loch\f1 -Notwithstanding the foregoing, }{\rtlch\fcs1 \af1\afs18 \ltrch\fcs0 \f1\fs18\insrsid11754636\charrsid4730869 \hich\af1\dbch\af37\loch\f1 the CMSIS D}{\rtlch\fcs1 \af1\afs18 \ltrch\fcs0 \f1\fs18\insrsid11754636 \hich\af1\dbch\af37\loch\f1 eliverables}{ -\rtlch\fcs1 \af1\afs18 \ltrch\fcs0 \f1\fs18\insrsid11754636\charrsid4730869 \hich\af1\dbch\af37\loch\f1 shall not}{\rtlch\fcs1 \af1\afs18 \ltrch\fcs0 \f1\fs18\insrsid11754636\charrsid4029239 \hich\af1\dbch\af37\loch\f1 include}{\rtlch\fcs1 \af1\afs18 -\ltrch\fcs0 \f1\fs18\insrsid11754636 \hich\af1\dbch\af37\loch\f1 :}{\rtlch\fcs1 \af1\afs18 \ltrch\fcs0 \f1\fs18\insrsid11754636\charrsid4029239 \hich\af1\dbch\af37\loch\f1 (i) the implementation of other published specification -\hich\af1\dbch\af37\loch\f1 s }{\rtlch\fcs1 \af1\afs18 \ltrch\fcs0 \f1\fs18\insrsid11754636 \hich\af1\dbch\af37\loch\f1 referenced }{\rtlch\fcs1 \af1\afs18 \ltrch\fcs0 \f1\fs18\insrsid11754636\charrsid4029239 \hich\af1\dbch\af37\loch\f1 in th}{ -\rtlch\fcs1 \af1\afs18 \ltrch\fcs0 \f1\fs18\insrsid11754636 \hich\af1\dbch\af37\loch\f1 e}{\rtlch\fcs1 \af1\afs18 \ltrch\fcs0 \f1\fs18\insrsid11754636\charrsid4029239 \hich\af1\dbch\af37\loch\f1 }{\rtlch\fcs1 \af1\afs18 \ltrch\fcs0 -\f1\fs18\insrsid11754636 \hich\af1\dbch\af37\loch\f1 CMSIS Deliverables }{\rtlch\fcs1 \af1\afs18 \ltrch\fcs0 \f1\fs18\insrsid11754636\charrsid4029239 \hich\af1\dbch\af37\loch\f1 -; (ii) any enabling technologies that may be necessary to make or use any product or portion thereof that }{\rtlch\fcs1 \af1\afs18 \ltrch\fcs0 \f1\fs18\insrsid11754636\charrsid4283548 \hich\af1\dbch\af37\loch\f1 complies with the }{\rtlch\fcs1 \af1\afs18 -\ltrch\fcs0 \f1\fs18\insrsid11754636 \hich\af1\dbch\af37\loch\f1 CMSIS Deliverables}{\rtlch\fcs1 \af1\afs18 \ltrch\fcs0 \f1\fs18\insrsid11754636\charrsid4283548 \hich\af1\dbch\af37\loch\f1 , but are not themselves expressly set forth in the }{\rtlch\fcs1 -\af1\afs18 \ltrch\fcs0 \f1\fs18\insrsid11754636 \hich\af1\dbch\af37\loch\f1 CMSIS Deliverables }{\rtlch\fcs1 \af1\afs18 \ltrch\fcs0 \f1\fs18\insrsid11754636\charrsid4283548 \hich\af1\dbch\af37\loch\f1 (e.\hich\af1\dbch\af37\loch\f1 -g. compiler front ends, code generators, back ends, libraries or other compiler, assembler or linker technologies; validation or debug software or hardware; applications, operating system or driver software; RISC architecture; processor microarchitecture) -\hich\af1\dbch\af37\loch\f1 ;\hich\af1\dbch\af37\loch\f1 (iii) maskworks and physical layouts of integrated circuit designs; or (iv) RTL or other high}{\rtlch\fcs1 \af1\afs18 \ltrch\fcs0 \f1\fs18\insrsid11754636\charrsid4029239 -\hich\af1\dbch\af37\loch\f1 level representations of integrated circuit designs.}{\rtlch\fcs1 \af1\afs18 \ltrch\fcs0 \f1\fs18\insrsid11754636 -\par }{\rtlch\fcs1 \af1\afs18 \ltrch\fcs0 \f1\fs18\cf1\lang2057\langfe2057\langfenp2057\insrsid11754636 \'93CMSIS-SVD\'94 }{\rtlch\fcs1 \af1\afs18 \ltrch\fcs0 \f1\fs18\cf1\lang2057\langfe2057\langfenp2057\insrsid11754636\charrsid9306407 means }{\rtlch\fcs1 -\af1\afs18 \ltrch\fcs0 \f1\fs18\cf1\lang2057\langfe2057\langfenp2057\insrsid11754636 the specification defining the System View Description (SVD), verification utility, }{\rtlch\fcs1 \af1\afs18 \ltrch\fcs0 -\f1\fs18\cf17\lang1033\langfe2057\langnp1033\langfenp2057\insrsid11754636\charrsid9306407 and associated XML}{\rtlch\fcs1 \af1\afs18 \ltrch\fcs0 \f1\fs18\cf17\lang1033\langfe2057\langnp1033\langfenp2057\insrsid11754636 schema}{\rtlch\fcs1 \af1\afs18 -\ltrch\fcs0 \f1\fs18\cf17\lang1033\langfe2057\langnp1033\langfenp2057\insrsid11754636\charrsid9306407 files. }{\rtlch\fcs1 \af1\afs18 \ltrch\fcs0 \f1\fs18\cf1\lang2057\langfe2057\langfenp2057\insrsid11754636\charrsid9306407 -\par }{\rtlch\fcs1 \af1\afs18 \ltrch\fcs0 \f1\fs18\cf1\lang2057\langfe2057\langfenp2057\insrsid11754636 \'93Separate Files\'94 means the components in }{\rtlch\fcs1 \af1\afs18 \ltrch\fcs0 -\f1\fs18\cf1\lang2057\langfe2057\langfenp2057\insrsid11754636\charrsid10227990 the CMSIS reference implementation identified}{\rtlch\fcs1 \af1\afs18 \ltrch\fcs0 \f1\fs18\cf1\lang2057\langfe2057\langfenp2057\insrsid11754636 - in the Schedule that demonstrate the usage of the CMSIS-CORE, CMSIS-DRIVER, CMSIS-DSP, CMSIS-PACK and CMSIS-RTOS API, }{\rtlch\fcs1 \af1\afs18 \ltrch\fcs0 \f1\fs18\cf1\lang2057\langfe2057\langfenp2057\insrsid11754636\charrsid3618484 for microprocessors -or device specific software applications that are for use with microprocessors.}{\rtlch\fcs1 \af1\afs18 \ltrch\fcs0 \f1\fs18\cf1\lang2057\langfe2057\langfenp2057\insrsid11754636 -\par }\pard \ltrpar\qj \li0\ri0\sa240\widctlpar\tx916\tx1832\tx2748\tx3664\tx4580\tx5496\tx6412\tx7328\tx8244\tx9160\tx10076\tx10992\tx11908\tx12824\tx13740\tx14656\wrapdefault\aspalpha\aspnum\faauto\adjustright\rin0\lin0\itap0\pararsid11754636 \cbpat8 { -\rtlch\fcs1 \af1\afs18 \ltrch\fcs0 \f1\fs18\cf1\lang2057\langfe2057\langfenp2057\insrsid11754636\charrsid15280636 1. LICENCE GRANTS. -\par }\pard \ltrpar\qj \li0\ri0\widctlpar\tx916\tx1832\tx2748\tx3664\tx4580\tx5496\tx6412\tx7328\tx8244\tx9160\tx10076\tx10992\tx11908\tx12824\tx13740\tx14656\wrapdefault\aspalpha\aspnum\faauto\adjustright\rin0\lin0\itap0\pararsid11754636 \cbpat8 {\rtlch\fcs1 -\af1\afs18 \ltrch\fcs0 \f1\fs18\cf1\lang2057\langfe2057\langfenp2057\insrsid11754636 1.1}{\rtlch\fcs1 \af1\afs18 \ltrch\fcs0 \f1\fs18\cf1\lang2057\langfe2057\langfenp2057\insrsid11754636\charrsid15280636 }{\rtlch\fcs1 \af1\afs18 \ltrch\fcs0 -\f1\fs18\cf1\lang2057\langfe2057\langfenp2057\insrsid11754636 CMSIS DELIVERABLES -\par -\par }{\rtlch\fcs1 \af1\afs18 \ltrch\fcs0 \f1\fs18\cf1\lang2057\langfe2057\langfenp2057\insrsid11754636\charrsid6756135 ARM hereby grants to you, subject to the terms and conditions of this Licence, a non-exclusive, non-transferable }{\rtlch\fcs1 \af1\afs18 -\ltrch\fcs0 \f1\fs18\cf1\lang2057\langfe2057\langfenp2057\insrsid11754636\charrsid1317547 licence, to use and copy the }{\rtlch\fcs1 \af1\afs18 \ltrch\fcs0 \f1\fs18\cf1\lang2057\langfe2057\langfenp2057\insrsid11754636 CMSIS D}{\rtlch\fcs1 \af1\afs18 -\ltrch\fcs0 \f1\fs18\insrsid11754636 \hich\af1\dbch\af37\loch\f1 eliverables}{\rtlch\fcs1 \af1\afs18 \ltrch\fcs0 \f1\fs18\cf1\lang2057\langfe2057\langfenp2057\insrsid11754636 }{\rtlch\fcs1 \af1\afs18 \ltrch\fcs0 -\f1\fs18\cf1\lang2057\langfe2057\langfenp2057\insrsid11754636\charrsid6756135 for the purpose of: }{\rtlch\fcs1 \af1\afs18 \ltrch\fcs0 \f1\fs18\cf1\lang2057\langfe2057\langfenp2057\insrsid11754636 -\par }{\rtlch\fcs1 \af1\afs18 \ltrch\fcs0 \f1\fs18\cf1\lang2057\langfe2057\langfenp2057\insrsid11754636\charrsid6756135 -\par }\pard \ltrpar\qj \li0\ri0\sa200\sl276\slmult1\widctlpar -\tx426\tx916\tx1832\tx2748\tx3664\tx4580\tx5496\tx6412\tx7328\tx8244\tx9160\tx10076\tx10992\tx11908\tx12824\tx13740\tx14656\wrapdefault\aspalpha\aspnum\faauto\adjustright\rin0\lin0\itap0\pararsid11754636 \cbpat8 {\rtlch\fcs1 \af1\afs18 \ltrch\fcs0 -\f1\fs18\cf1\lang2057\langfe2057\langfenp2057\insrsid11754636\charrsid6756135 (i) subject to clause 1.}{\rtlch\fcs1 \af1\afs18 \ltrch\fcs0 \f1\fs18\cf1\lang2057\langfe2057\langfenp2057\insrsid11754636 2}{\rtlch\fcs1 \af1\afs18 \ltrch\fcs0 -\f1\fs18\cf1\lang2057\langfe2057\langfenp2057\insrsid11754636\charrsid6756135 , developing, having developed, manufacturing, having manufactured, offering to sell, selling, supplying or otherwise distributing products that comply with the }{\rtlch\fcs1 -\af1\afs18 \ltrch\fcs0 \f1\fs18\cf1\lang2057\langfe2057\langfenp2057\insrsid11754636 CMSIS D}{\rtlch\fcs1 \af1\afs18 \ltrch\fcs0 \f1\fs18\insrsid11754636 \hich\af1\dbch\af37\loch\f1 eliverables}{\rtlch\fcs1 \af1\afs18 \ltrch\fcs0 -\f1\fs18\cf1\lang2057\langfe2057\langfenp2057\insrsid11754636\charrsid6756135 ; and -\par }{\rtlch\fcs1 \af1\afs18 \ltrch\fcs0 \f1\fs18\cf1\lang2057\langfe2057\langfenp2057\insrsid11754636\charrsid1317547 (ii) distributing and having distributed (directly or through your customers and authorised distributors) the CMSIS-D}{\rtlch\fcs1 -\af1\afs18 \ltrch\fcs0 \f1\fs18\insrsid11754636 \hich\af1\dbch\af37\loch\f1 eliverables}{\rtlch\fcs1 \af1\afs18 \ltrch\fcs0 \f1\fs18\cf1\lang2057\langfe2057\langfenp2057\insrsid11754636\charrsid1317547 unmodified, with the products}{\rtlch\fcs1 -\af1\afs18 \ltrch\fcs0 \f1\fs18\cf1\lang2057\langfe2057\langfenp2057\insrsid11754636\charrsid6756135 you have developed under }{\rtlch\fcs1 \af1\afs18 \ltrch\fcs0 \f1\fs18\cf1\lang2057\langfe2057\langfenp2057\insrsid11754636 Clause 1.1 (i) }{\rtlch\fcs1 -\af1\afs18 \ltrch\fcs0 \f1\fs18\cf1\lang2057\langfe2057\langfenp2057\insrsid11754636\charrsid6756135 provided you preserve any copyright notices which are included with the CMSIS}{\rtlch\fcs1 \af1\afs18 \ltrch\fcs0 -\f1\fs18\cf1\lang2057\langfe2057\langfenp2057\insrsid11754636 D}{\rtlch\fcs1 \af1\afs18 \ltrch\fcs0 \f1\fs18\insrsid11754636 \hich\af1\dbch\af37\loch\f1 eliverables}{\rtlch\fcs1 \af1\afs18 \ltrch\fcs0 -\f1\fs18\cf1\lang2057\langfe2057\langfenp2057\insrsid11754636\charrsid6756135 . -\par }\pard \ltrpar\qj \li0\ri0\widctlpar\tx916\tx1832\tx2748\tx3664\tx4580\tx5496\tx6412\tx7328\tx8244\tx9160\tx10076\tx10992\tx11908\tx12824\tx13740\tx14656\wrapdefault\aspalpha\aspnum\faauto\adjustright\rin0\lin0\itap0\pararsid11754636 \cbpat8 {\rtlch\fcs1 -\af1\afs18 \ltrch\fcs0 \f1\fs18\cf1\lang2057\langfe2057\langfenp2057\insrsid11754636 1.2}{\rtlch\fcs1 \af1\afs18 \ltrch\fcs0 \f1\fs18\cf1\lang2057\langfe2057\langfenp2057\insrsid11754636\charrsid15280636 CONDITIONS ON REDISTRIBUTION}{\rtlch\fcs1 -\af1\afs18 \ltrch\fcs0 \f1\fs18\cf1\lang2057\langfe2057\langfenp2057\insrsid11754636 .}{\rtlch\fcs1 \af1\afs18 \ltrch\fcs0 \f1\fs18\cf1\lang2057\langfe2057\langfenp2057\insrsid11754636\charrsid15280636 }{\rtlch\fcs1 \af1\afs18 \ltrch\fcs0 -\f1\fs18\cf1\lang2057\langfe2057\langfenp2057\insrsid11754636 -\par -\par }\pard \ltrpar\qj \li0\ri0\sa200\sl276\slmult1\widctlpar\tx916\tx1832\tx2748\tx3664\tx4580\tx5496\tx6412\tx7328\tx8244\tx9160\tx10076\tx10992\tx11908\tx12824\tx13740\tx14656\wrapdefault\aspalpha\aspnum\faauto\adjustright\rin0\lin0\itap0\pararsid11754636 -\cbpat8 {\rtlch\fcs1 \af1\afs18 \ltrch\fcs0 \f1\fs18\lang1024\langfe1024\noproof\insrsid11754636\charrsid1928237 \hich\af1\dbch\af37\loch\f1 -If you distribute (directly or through your customers and authorised distributors) the products you have created pursuant to Clauses 1.1}{\rtlch\fcs1 \af1\afs18 \ltrch\fcs0 \f1\fs18\lang1024\langfe1024\noproof\insrsid11754636 \hich\af1\dbch\af37\loch\f1 -}{\rtlch\fcs1 \af1\afs18 \ltrch\fcs0 \f1\fs18\lang1024\langfe1024\noproof\insrsid11754636\charrsid1928237 \hich\af1\dbch\af37\loch\f1 (i) you agree: (a) not to use ARM\hich\f1 \rquote \loch\f1 s name\hich\af1\dbch\af37\loch\f1 -, logo or trademarks to market any or all of the }{\rtlch\fcs1 \af1\afs18 \ltrch\fcs0 \f1\fs18\cf1\lang2057\langfe2057\langfenp2057\insrsid11754636\charrsid1928237 products created under Clause 1.1 (i); }{\rtlch\fcs1 \af1\afs18 \ltrch\fcs0 -\f1\fs18\lang1024\langfe1024\noproof\insrsid11754636\charrsid1928237 \hich\af1\dbch\af37\loch\f1 (b) }{\rtlch\fcs1 \af1\afs18 \ltrch\fcs0 \f1\fs18\lang1024\langfe1024\noproof\insrsid11754636 \hich\af1\dbch\af37\loch\f1 to }{\rtlch\fcs1 \af1\afs18 -\ltrch\fcs0 \f1\fs18\lang1024\langfe1024\noproof\insrsid11754636\charrsid1928237 \hich\af1\dbch\af37\loch\f1 pr}{\rtlch\fcs1 \af1\afs18 \ltrch\fcs0 \f1\fs18\lang1024\langfe1024\noproof\insrsid11754636 \hich\af1\dbch\af37\loch\f1 e}{\rtlch\fcs1 \af1\afs18 -\ltrch\fcs0 \f1\fs18\lang1024\langfe1024\noproof\insrsid11754636\charrsid1928237 \hich\af1\dbch\af37\loch\f1 serve any copyright notices included in the }{\rtlch\fcs1 \af1\afs18 \ltrch\fcs0 \f1\fs18\lang1024\langfe1024\noproof\insrsid11754636 -\hich\af1\dbch\af37\loch\f1 CMSIS D}{\rtlch\fcs1 \af1\afs18 \ltrch\fcs0 \f1\fs18\insrsid11754636 \hich\af1\dbch\af37\loch\f1 eliverables}{\rtlch\fcs1 \af1\afs18 \ltrch\fcs0 \f1\fs18\lang1024\langfe1024\noproof\insrsid11754636\charrsid1928237 -\hich\af1\dbch\af37\loch\f1 ; and (c) to ensure your customers and authorised distributors comply with this Clause 1.}{\rtlch\fcs1 \af1\afs18 \ltrch\fcs0 \f1\fs18\lang1024\langfe1024\noproof\insrsid11754636 \hich\af1\dbch\af37\loch\f1 2}{\rtlch\fcs1 -\af1\afs18 \ltrch\fcs0 \f1\fs18\lang1024\langfe1024\noproof\insrsid11754636\charrsid1928237 .}{\rtlch\fcs1 \af1\afs18 \ltrch\fcs0 \f1\fs18\lang1024\langfe1024\noproof\insrsid11754636 \hich\af1\dbch\af37\loch\f1 }{\rtlch\fcs1 \af1\afs18 \ltrch\fcs0 -\f1\fs18\cf1\lang2057\langfe2057\langfenp2057\insrsid11754636 -\par }\pard \ltrpar\qj \li0\ri0\sa240\widctlpar\tx916\tx1832\tx2748\tx3664\tx4580\tx5496\tx6412\tx7328\tx8244\tx9160\tx10076\tx10992\tx11908\tx12824\tx13740\tx14656\wrapdefault\aspalpha\aspnum\faauto\adjustright\rin0\lin0\itap0\pararsid11754636 \cbpat8 { -\rtlch\fcs1 \af1\afs18 \ltrch\fcs0 \f1\fs18\cf1\lang2057\langfe2057\langfenp2057\insrsid11754636\charrsid15280636 2. RESTRICTIONS ON USE OF THE}{\rtlch\fcs1 \af1\afs18 \ltrch\fcs0 \f1\fs18\cf1\lang2057\langfe2057\langfenp2057\insrsid11754636 - CMSIS DELIVERABLES}{\rtlch\fcs1 \af1\afs18 \ltrch\fcs0 \f1\fs18\cf1\lang2057\langfe2057\langfenp2057\insrsid11754636\charrsid15280636 . -\par }\pard \ltrpar\qj \li0\ri0\sa200\sl276\slmult1\widctlpar\tx916\tx1832\tx2748\tx3664\tx4580\tx5496\tx6412\tx7328\tx8244\tx9160\tx10076\tx10992\tx11908\tx12824\tx13740\tx14656\wrapdefault\aspalpha\aspnum\faauto\adjustright\rin0\lin0\itap0\pararsid11754636 -\cbpat8 {\rtlch\fcs1 \af1\afs18 \ltrch\fcs0 \f1\fs18\cf1\lang2057\langfe2057\langfenp2057\insrsid11754636\charrsid15280636 PERMITTED USERS: The }{\rtlch\fcs1 \af1\afs18 \ltrch\fcs0 \f1\fs18\cf1\lang2057\langfe2057\langfenp2057\insrsid11754636 -CMSIS Deliverables }{\rtlch\fcs1 \af1\afs18 \ltrch\fcs0 \f1\fs18\cf1\lang2057\langfe2057\langfenp2057\insrsid11754636\charrsid15280636 shall be used only by you (either a single individual, or single legal entity) your employees, or by your }{\rtlch\fcs1 -\af1\afs18 \ltrch\fcs0 \f1\fs18\cf1\lang2057\langfe2057\langfenp2057\insrsid11754636 on-site }{\rtlch\fcs1 \af1\afs18 \ltrch\fcs0 \f1\fs18\cf1\lang2057\langfe2057\langfenp2057\insrsid11754636\charrsid15280636 -bona fide sub-contractors for whose acts and omissions you hereby agree to be responsible to ARM}{\rtlch\fcs1 \af1\afs18 \ltrch\fcs0 \f1\fs18\cf1\lang2057\langfe2057\langfenp2057\insrsid11754636 for}{\rtlch\fcs1 \af1\afs18 \ltrch\fcs0 -\f1\fs18\cf1\lang2057\langfe2057\langfenp2057\insrsid11754636\charrsid15280636 to the same extent as }{\rtlch\fcs1 \af1\afs18 \ltrch\fcs0 \f1\fs18\cf1\lang2057\langfe2057\langfenp2057\insrsid11754636 you are for }{\rtlch\fcs1 \af1\afs18 \ltrch\fcs0 -\f1\fs18\cf1\lang2057\langfe2057\langfenp2057\insrsid11754636\charrsid15280636 your employees, and provided always that such sub-contractors}{\rtlch\fcs1 \af1\afs18 \ltrch\fcs0 \f1\fs18\cf1\lang2057\langfe2057\langfenp2057\insrsid11754636 :}{\rtlch\fcs1 -\af1\afs18 \ltrch\fcs0 \f1\fs18\cf1\lang2057\langfe2057\langfenp2057\insrsid11754636\charrsid15280636 (i) are contractually obligated to use the }{\rtlch\fcs1 \af1\afs18 \ltrch\fcs0 \f1\fs18\cf1\lang2057\langfe2057\langfenp2057\insrsid11754636 -CMSIS Deliverables }{\rtlch\fcs1 \af1\afs18 \ltrch\fcs0 \f1\fs18\cf1\lang2057\langfe2057\langfenp2057\insrsid11754636\charrsid15280636 only for your benefit}{\rtlch\fcs1 \af1\afs18 \ltrch\fcs0 \f1\fs18\cf1\lang2057\langfe2057\langfenp2057\insrsid11754636 -;}{\rtlch\fcs1 \af1\afs18 \ltrch\fcs0 \f1\fs18\cf1\lang2057\langfe2057\langfenp2057\insrsid11754636\charrsid15280636 and (i}{\rtlch\fcs1 \af1\afs18 \ltrch\fcs0 \f1\fs18\cf1\lang2057\langfe2057\langfenp2057\insrsid11754636 i}{\rtlch\fcs1 \af1\afs18 -\ltrch\fcs0 \f1\fs18\cf1\lang2057\langfe2057\langfenp2057\insrsid11754636\charrsid15280636 ) agree to assign all their work product and any rights they create therein in the supply of such work to you. -\par COPYRIGHT AND RESERVATION OF RIGHTS}{\rtlch\fcs1 \af1\afs18 \ltrch\fcs0 \f1\fs18\cf1\lang2057\langfe2057\langfenp2057\insrsid11754636\charrsid14488502 : The }{\rtlch\fcs1 \af1\afs18 \ltrch\fcs0 -\f1\fs18\cf1\lang2057\langfe2057\langfenp2057\insrsid11754636 CMSIS Deliverables}{\rtlch\fcs1 \af1\afs18 \ltrch\fcs0 \f1\fs18\cf1\lang2057\langfe2057\langfenp2057\insrsid11754636\charrsid14488502 - are owned by ARM or its licensors and are protected by copyright and other intellectual property laws and international treaties. The }{\rtlch\fcs1 \af1\afs18 \ltrch\fcs0 \f1\fs18\cf1\lang2057\langfe2057\langfenp2057\insrsid11754636 CMSIS Deliverables}{ -\rtlch\fcs1 \af1\afs18 \ltrch\fcs0 \f1\fs18\cf1\lang2057\langfe2057\langfenp2057\insrsid11754636\charrsid14488502 are licensed not sold. Except as expressly licensed herein, you acquire no right, title or interest in the }{\rtlch\fcs1 \af1\afs18 -\ltrch\fcs0 \f1\fs18\cf1\lang2057\langfe2057\langfenp2057\insrsid11754636 CMSIS Deliverables}{\rtlch\fcs1 \af1\afs18 \ltrch\fcs0 \f1\fs18\cf1\lang2057\langfe2057\langfenp2057\insrsid11754636\charrsid14488502 - or any intellectual property therein. In no event shall the licences granted herein be construed as granting you, expressly or by implication, estoppels or otherwise, a licence to use any ARM technology except the }{\rtlch\fcs1 \af1\afs18 \ltrch\fcs0 -\f1\fs18\cf1\lang2057\langfe2057\langfenp2057\insrsid11754636 CMSIS Deliverables}{\rtlch\fcs1 \af1\afs18 \ltrch\fcs0 \f1\fs18\cf1\lang2057\langfe2057\langfenp2057\insrsid11754636\charrsid14488502 .}{\rtlch\fcs1 \af1\afs18 \ltrch\fcs0 -\f1\fs18\cf1\lang2057\langfe2057\langfenp2057\insrsid11754636\charrsid15280636 -\par }\pard \ltrpar\qj \li0\ri0\sa240\widctlpar\tx916\tx1832\tx2748\tx3664\tx4580\tx5496\tx6412\tx7328\tx8244\tx9160\tx10076\tx10992\tx11908\tx12824\tx13740\tx14656\wrapdefault\aspalpha\aspnum\faauto\adjustright\rin0\lin0\itap0\pararsid11754636 \cbpat8 { -\rtlch\fcs1 \af1\afs18 \ltrch\fcs0 \f1\fs18\cf1\lang2057\langfe2057\langfenp2057\insrsid11754636\charrsid15280636 }{\rtlch\fcs1 \af1\afs18 \ltrch\fcs0 \f1\fs18\cf1\lang2057\langfe2057\langfenp2057\insrsid11754636 3}{\rtlch\fcs1 \af1\afs18 \ltrch\fcs0 -\f1\fs18\cf1\lang2057\langfe2057\langfenp2057\insrsid11754636\charrsid15280636 . SUPPORT. -\par ARM is not obligated to support the }{\rtlch\fcs1 \af1\afs18 \ltrch\fcs0 \f1\fs18\cf1\lang2057\langfe2057\langfenp2057\insrsid11754636 CMSIS Deliverables but}{\rtlch\fcs1 \af1\afs18 \ltrch\fcs0 -\f1\fs18\cf1\lang2057\langfe2057\langfenp2057\insrsid11754636\charrsid15280636 may do so entirely at ARM's discretion. -\par }{\rtlch\fcs1 \af1\afs18 \ltrch\fcs0 \f1\fs18\cf1\lang2057\langfe2057\langfenp2057\insrsid11754636 4}{\rtlch\fcs1 \af1\afs18 \ltrch\fcs0 \f1\fs18\cf1\lang2057\langfe2057\langfenp2057\insrsid11754636\charrsid15280636 . }{\rtlch\fcs1 \af1\afs18 \ltrch\fcs0 -\f1\fs18\cf1\lang2057\langfe2057\langfenp2057\insrsid11754636 NO }{\rtlch\fcs1 \af1\afs18 \ltrch\fcs0 \f1\fs18\cf1\lang2057\langfe2057\langfenp2057\insrsid11754636\charrsid15280636 WARRANT}{\rtlch\fcs1 \af1\afs18 \ltrch\fcs0 -\f1\fs18\cf1\lang2057\langfe2057\langfenp2057\insrsid11754636 Y.}{\rtlch\fcs1 \af1\afs18 \ltrch\fcs0 \f1\fs18\cf1\lang2057\langfe2057\langfenp2057\insrsid11754636\charrsid15280636 -\par YOU AGREE THAT THE }{\rtlch\fcs1 \af1\afs18 \ltrch\fcs0 \f1\fs18\cf1\lang2057\langfe2057\langfenp2057\insrsid11754636 CMSIS DELIVERABLES ARE}{\rtlch\fcs1 \af1\afs18 \ltrch\fcs0 -\f1\fs18\cf1\lang2057\langfe2057\langfenp2057\insrsid11754636\charrsid15280636 - LICENSED "AS IS", AND THAT ARM EXPRESSLY DISCLAIMS ALL REPRESENTATIONS, WARRANTIES, CONDITIONS OR OTHER TERMS, EXPRESS, IMPLIED OR STATUTORY, INCLUDING WITHOUT LIMITATION THE IMPLIED WARR -ANTIES OF NON-INFRINGEMENT, SATISFACTORY QUALITY, AND FITNESS FOR A PARTICULAR PURPOSE.}{\rtlch\fcs1 \af1\afs18 \ltrch\fcs0 \f1\fs18\cf1\lang2057\langfe2057\langfenp2057\insrsid11754636 THE CMSIS DELIVERABLES MAY CONTAIN ERRORS. }{\rtlch\fcs1 -\af1\afs18 \ltrch\fcs0 \f1\fs18\insrsid11754636 -\par }{\rtlch\fcs1 \af1\afs18 \ltrch\fcs0 \f1\fs18\cf1\lang2057\langfe2057\langfenp2057\insrsid11754636 5}{\rtlch\fcs1 \af1\afs18 \ltrch\fcs0 \f1\fs18\cf1\lang2057\langfe2057\langfenp2057\insrsid11754636\charrsid15280636 . LIMITATION OF LIABILITY. -\par THE MAXIMUM LIABILITY OF ARM TO YOU IN AGGREGATE FOR ALL CLAIMS MADE AGAINST ARM IN CONTRACT}{\rtlch\fcs1 \af1\afs18 \ltrch\fcs0 \f1\fs18\cf1\lang2057\langfe2057\langfenp2057\insrsid11754636 ,}{\rtlch\fcs1 \af1\afs18 \ltrch\fcs0 -\f1\fs18\cf1\lang2057\langfe2057\langfenp2057\insrsid11754636\charrsid15280636 TORT OR OTHERWISE UNDER OR IN CONNECTION WITH THE SUBJECT MATTER OF THIS LICENCE SHALL NOT EXCEED }{\rtlch\fcs1 \af1\afs18 \ltrch\fcs0 -\f1\fs18\cf1\lang2057\langfe2057\langfenp2057\insrsid11754636 THE GREATER OF (I) }{\rtlch\fcs1 \af1\afs18 \ltrch\fcs0 \f1\fs18\cf1\lang2057\langfe2057\langfenp2057\insrsid11754636\charrsid15280636 -THE TOTAL OF SUMS PAID BY YOU TO ARM (IF ANY) FOR THIS LICENCE}{\rtlch\fcs1 \af1\afs18 \ltrch\fcs0 \f1\fs18\cf1\lang2057\langfe2057\langfenp2057\insrsid11754636 AND (II) US$10.00}{\rtlch\fcs1 \af1\afs18 \ltrch\fcs0 -\f1\fs18\cf1\lang2057\langfe2057\langfenp2057\insrsid11754636\charrsid15280636 .}{\rtlch\fcs1 \af1\afs18 \ltrch\fcs0 \f1\fs18\cf1\lang2057\langfe2057\langfenp2057\insrsid11754636 THE LIMITATIONS, EXCLUSIONS AND DISCLAIMERS IN THIS LICEN -CE SHALL APPLY TO THE MAXIMUM EXTENT ALLOWED BY APPLICABLE LAW. -\par }\pard \ltrpar\qj \li0\ri0\sa200\sl276\slmult1\widctlpar\wrapdefault\aspalpha\aspnum\faauto\adjustright\rin0\lin0\itap0\pararsid11754636 {\rtlch\fcs1 \af1\afs18 \ltrch\fcs0 \f1\fs18\lang1024\langfe1024\noproof\insrsid11754636 \hich\af1\dbch\af37\loch\f1 6 -}{\rtlch\fcs1 \af1\afs18 \ltrch\fcs0 \f1\fs18\lang1024\langfe1024\noproof\insrsid11754636\charrsid13830602 \hich\af1\dbch\af37\loch\f1 . THIRD PARTY RIGHTS.}{\rtlch\fcs1 \af1\afs18 \ltrch\fcs0 \f1\fs18\insrsid11754636\charrsid13830602 -\par }{\rtlch\fcs1 \af1\afs18 \ltrch\fcs0 \f1\fs18\lang1024\langfe1024\noproof\insrsid11754636\charrsid13830602 \hich\af1\dbch\af37\loch\f1 -The Separate Files are delivered subject to and your use is governed by their own separate licence agreements. This Licence does not apply to such Separate Files and the\hich\af1\dbch\af37\loch\f1 \hich\f1 y are not included in the term \'93}{\rtlch\fcs1 -\af1\afs18 \ltrch\fcs0 \f1\fs18\lang1024\langfe1024\noproof\insrsid11754636 \hich\af1\dbch\af37\loch\f1 CMSIS Deliverables}{\rtlch\fcs1 \af1\afs18 \ltrch\fcs0 \f1\fs18\lang1024\langfe1024\noproof\insrsid11754636\charrsid13830602 -\loch\af1\dbch\af37\hich\f1 \'94\loch\f1 \hich\f1 under this Licence. You agree to comply with all terms and conditions imposed on you in respect of such Separate Files including those identified in the Schedule (\'93\loch\f1 \hich\f1 Third Party Terms -\'94\loch\f1 ). -\par \hich\af1\dbch\af37\loch\f1 ARM HEREBY DISCLA\hich\af1\dbch\af37\loch\f1 \hich\f1 -IMS ANY AND ALL WARRANTIES EXPRESS OR IMPLIED FROM ANY THIRD PARTIES REGARDING ANY SEPARATE FILES, ANY THIRD PARTY MATERIALS INCLUDED IN THE SOFTWARE, ANY THIRD PARTY MATERIALS FROM WHICH THE SOFTWARE IS DERIVED (COLLECTIVELY \'93\loch\f1 \hich\f1 -OTHER CODE\'94\loch\f1 ), AND THE USE OF\hich\af1\dbch\af37\loch\f1 \hich\af1\dbch\af37\loch\f1 -ANY OR ALL THE OTHER CODE IN CONNECTION WITH THE SOFTWARE, INCLUDING (WITHOUT LIMITATION) ANY WARRANTIES OF SATISFACTORY QUALITY OR FITNESS FOR A PARTICULAR PURPOSE. -\par \hich\af1\dbch\af37\loch\f1 NO THIRD PARTY LICENSORS OF OTHER CODE SHALL HAVE ANY LIABILITY FOR ANY DIRECT, INDIRECT, \hich\af1\dbch\af37\loch\f1 -INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING WITHOUT LIMITATION LOST PROFITS), HOWEVER CAUSED AND WHETHER MADE UNDER CONTRACT, TORT OR OTHER LEGAL THEORY, ARISING IN ANY WAY OUT OF THE USE OR DISTRIBUTION OF THE OTHER CODE OR THE EX -\hich\af1\dbch\af37\loch\f1 E\hich\af1\dbch\af37\loch\f1 RCISE OF ANY RIGHTS GRANTED UNDER EITHER OR BOTH THIS LICENCE AND THE LEGAL TERMS APPLICABLE TO ANY SEPARATE FILES, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGES. -\par }\pard \ltrpar\qj \li0\ri0\sa240\widctlpar\tx916\tx1832\tx2748\tx3664\tx4580\tx5496\tx6412\tx7328\tx8244\tx9160\tx10076\tx10992\tx11908\tx12824\tx13740\tx14656\wrapdefault\aspalpha\aspnum\faauto\adjustright\rin0\lin0\itap0\pararsid11754636 \cbpat8 { -\rtlch\fcs1 \af1\afs18 \ltrch\fcs0 \f1\fs18\cf1\lang2057\langfe2057\langfenp2057\insrsid11754636 7}{\rtlch\fcs1 \af1\afs18 \ltrch\fcs0 \f1\fs18\cf1\lang2057\langfe2057\langfenp2057\insrsid11754636\charrsid15280636 . U.S. GOVERNMENT END USERS. -\par US Government Restrictions: Use, duplication, reproduction, release, modification, disclosure or transfer of this commercial product and accompanying documentation is restricted in accordance with the terms of this Licence. -\par }{\rtlch\fcs1 \af1\afs18 \ltrch\fcs0 \f1\fs18\cf1\lang2057\langfe2057\langfenp2057\insrsid11754636 8}{\rtlch\fcs1 \af1\afs18 \ltrch\fcs0 \f1\fs18\cf1\lang2057\langfe2057\langfenp2057\insrsid11754636\charrsid15280636 . TERM AND TERMINATION. -\par }{\rtlch\fcs1 \af1\afs18 \ltrch\fcs0 \f1\fs18\cf1\lang2057\langfe2057\langfenp2057\insrsid11754636 8.1 }{\rtlch\fcs1 \af1\afs18 \ltrch\fcs0 \f1\fs18\cf1\lang2057\langfe2057\langfenp2057\insrsid11754636\charrsid15280636 -This Licence shall remain in force until terminated }{\rtlch\fcs1 \af1\afs18 \ltrch\fcs0 \f1\fs18\cf1\lang2057\langfe2057\langfenp2057\insrsid11754636 in accordance with the terms of Clause 8.2 or Clause 8.3 below}{\rtlch\fcs1 \af1\afs18 \ltrch\fcs0 -\f1\fs18\cf1\lang2057\langfe2057\langfenp2057\insrsid11754636\charrsid15280636 . }{\rtlch\fcs1 \af1\afs18 \ltrch\fcs0 \f1\fs18\cf1\lang2057\langfe2057\langfenp2057\insrsid11754636 -\par 8.2 }{\rtlch\fcs1 \af1\afs18 \ltrch\fcs0 \f1\fs18\cf1\lang2057\langfe2057\langfenp2057\insrsid11754636\charrsid15280636 -Without prejudice to any of its other rights if you are in breach of any of the terms and conditions of this Licence then ARM may terminate this Licence immediately upon giving written notice to you}{\rtlch\fcs1 \af1\afs18 \ltrch\fcs0 -\f1\fs18\cf1\lang2057\langfe2057\langfenp2057\insrsid11754636\charrsid7630822 . You may terminate this Licence at any time. }{\rtlch\fcs1 \af1\afs18 \ltrch\fcs0 \f1\fs18\cf1\lang2057\langfe2057\langfenp2057\insrsid11754636 -\par }\pard \ltrpar\qj \li0\ri0\sa200\sl276\slmult1\widctlpar\wrapdefault\aspalpha\aspnum\faauto\adjustright\rin0\lin0\itap0\pararsid11754636 {\rtlch\fcs1 \af1\afs18 \ltrch\fcs0 \f1\fs18\insrsid11754636\charrsid7106724 \hich\af1\dbch\af37\loch\f1 -8.3 This Licence shall immediately terminate and shall be unavailable to you if you or any party affiliated to you asserts any patents against ARM, ARM affiliates, third parties who have a valid licence fro\hich\af1\dbch\af37\loch\f1 -m ARM for the CMSIS Deliverables, or any customers or distributors of any of them based upon a claim that your (or your affiliate) patent is Necessary to implement the }{\rtlch\fcs1 \af1\afs18 \ltrch\fcs0 \f1\fs18\insrsid11754636 -\hich\af1\dbch\af37\loch\f1 CMSIS Deliverables}{\rtlch\fcs1 \af1\afs18 \ltrch\fcs0 \f1\fs18\insrsid11754636\charrsid7106724 \hich\af1\dbch\af37\loch\f1 . In this Licence}{\rtlch\fcs1 \af1\afs18 \ltrch\fcs0 \f1\fs18\insrsid11754636 -\hich\af1\dbch\af37\loch\f1 :}{\rtlch\fcs1 \af1\afs18 \ltrch\fcs0 \f1\fs18\insrsid11754636\charrsid7106724 \hich\af1\dbch\af37\loch\f1 (i) "affiliate" means any entity controlling, contr\hich\af1\dbch\af37\loch\f1 -olled by or under common control with a party (in fact or in law, via voting securities, management control or otherwise) and "affiliated" shall be construed accordingly; (ii) "assert" means to allege infringement in legal or administrative proceedings, o -\hich\af1\dbch\af37\loch\f1 r\hich\af1\dbch\af37\loch\f1 proceedings before any other competent trade, arbitral or international authority; }{\rtlch\fcs1 \af1\afs18 \ltrch\fcs0 \f1\fs18\insrsid11754636 \hich\af1\dbch\af37\loch\f1 and }{\rtlch\fcs1 -\af1\afs18 \ltrch\fcs0 \f1\fs18\insrsid11754636\charrsid7106724 \hich\af1\dbch\af37\loch\f1 \hich\f1 (iii) \'93\loch\f1 \hich\f1 Necessary\'94\loch\f1 - means with respect to any claims of any patent, those claims which, without the appropriate permission of the patent owner, will be infringed when imp\hich\af1\dbch\af37\loch\f1 lementing the CMSIS}{\rtlch\fcs1 \af1\afs18 \ltrch\fcs0 -\f1\fs18\insrsid11754636 \hich\af1\dbch\af37\loch\f1 Deliverables }{\rtlch\fcs1 \af1\afs18 \ltrch\fcs0 \f1\fs18\insrsid11754636\charrsid7106724 \hich\af1\dbch\af37\loch\f1 -because no alternative, commercially reasonable, non-infringing way of implementing the CMSIS}{\rtlch\fcs1 \af1\afs18 \ltrch\fcs0 \f1\fs18\insrsid11754636 \hich\af1\dbch\af37\loch\f1 Deliverables }{\rtlch\fcs1 \af1\afs18 \ltrch\fcs0 -\f1\fs18\insrsid11754636\charrsid7106724 \hich\af1\dbch\af37\loch\f1 is known.}{\rtlch\fcs1 \af1\afs18 \ltrch\fcs0 \f1\fs18\insrsid11754636\charrsid5900444 \hich\af1\dbch\af37\loch\f1 }{\rtlch\fcs1 \af1\afs18 \ltrch\fcs0 \f1\fs18\insrsid11754636 -\par }\pard \ltrpar\qj \li0\ri0\sa240\widctlpar\tx916\tx1832\tx2748\tx3664\tx4580\tx5496\tx6412\tx7328\tx8244\tx9160\tx10076\tx10992\tx11908\tx12824\tx13740\tx14656\wrapdefault\aspalpha\aspnum\faauto\adjustright\rin0\lin0\itap0\pararsid11754636 \cbpat8 { -\rtlch\fcs1 \af1\afs18 \ltrch\fcs0 \f1\fs18\cf1\lang2057\langfe2057\langfenp2057\insrsid11754636 8.4 }{\rtlch\fcs1 \af1\afs18 \ltrch\fcs0 \f1\fs18\cf1\lang2057\langfe2057\langfenp2057\insrsid11754636\charrsid7630822 Upon termination of this Licence,}{ -\rtlch\fcs1 \af1\afs18 \ltrch\fcs0 \f1\fs18\cf1\lang2057\langfe2057\langfenp2057\insrsid11754636\charrsid15280636 you shall stop }{\rtlch\fcs1 \af1\afs18 \ltrch\fcs0 \f1\fs18\cf1\lang2057\langfe2057\langfenp2057\insrsid11754636\charrsid15098396 -using the }{\rtlch\fcs1 \af1\afs18 \ltrch\fcs0 \f1\fs18\cf1\lang2057\langfe2057\langfenp2057\insrsid11754636 CMSIS Deliverables}{\rtlch\fcs1 \af1\afs18 \ltrch\fcs0 \f1\fs18\cf1\lang2057\langfe2057\langfenp2057\insrsid11754636\charrsid15098396 - and destroy all copies of the }{\rtlch\fcs1 \af1\afs18 \ltrch\fcs0 \f1\fs18\cf1\lang2057\langfe2057\langfenp2057\insrsid11754636 CMSIS Deliverables}{\rtlch\fcs1 \af1\afs18 \ltrch\fcs0 -\f1\fs18\cf1\lang2057\langfe2057\langfenp2057\insrsid11754636\charrsid15098396 in your possession. The provisions of clauses 5, 6, 7, 8 and 9 shall survive termination of this Licence.}{\rtlch\fcs1 \af1\afs18 \ltrch\fcs0 -\f1\fs18\cf1\lang2057\langfe2057\langfenp2057\insrsid11754636\charrsid15280636 -\par }{\rtlch\fcs1 \af1\afs18 \ltrch\fcs0 \f1\fs18\cf1\lang2057\langfe2057\langfenp2057\insrsid11754636 9}{\rtlch\fcs1 \af1\afs18 \ltrch\fcs0 \f1\fs18\cf1\lang2057\langfe2057\langfenp2057\insrsid11754636\charrsid15280636 . GENERAL. -\par This Licence is governed by English Law. Except where ARM agrees otherwise in a written contract signed by you and ARM, this is the only agreement between you and ARM relating to the }{\rtlch\fcs1 \af1\afs18 \ltrch\fcs0 -\f1\fs18\cf1\lang2057\langfe2057\langfenp2057\insrsid11754636 CMSIS Deliverables}{\rtlch\fcs1 \af1\afs18 \ltrch\fcs0 \f1\fs18\cf1\lang2057\langfe2057\langfenp2057\insrsid11754636\charrsid15280636 - and it may only be modified by written agreement between you and ARM. Except as expressly agreed in writing, this Licence may not be modified by purchase orders, ad -vertising or other representation by any person. If any clause or sentence in this Licence is held by a court of law to be illegal or unenforceable the remaining provisions of this Licence shall not be affected thereby. The failure by ARM to enforce any o -f the provisions of this Licence, unless waived in writing, shall not constitute a waiver of ARM's rights to enforce such provision or any other provision of this Licence in the future.}{\rtlch\fcs1 \af1\afs18 \ltrch\fcs0 -\f1\fs18\cf1\lang2057\langfe2057\langfenp2057\insrsid11754636 This Licence may not be assigned without the prior written consent of ARM. -\par }\pard \ltrpar\qc \li0\ri0\sa240\widctlpar\tx916\tx1832\tx2748\tx3664\tx4580\tx5496\tx6412\tx7328\tx8244\tx9160\tx10076\tx10992\tx11908\tx12824\tx13740\tx14656\wrapdefault\aspalpha\aspnum\faauto\adjustright\rin0\lin0\itap0\pararsid11754636 \cbpat8 { -\rtlch\fcs1 \af1\afs18 \ltrch\fcs0 \f1\fs18\cf1\lang2057\langfe2057\langfenp2057\insrsid11754636 \page SCHEDULE -\par }\pard \ltrpar\qj \li0\ri0\sa240\widctlpar\tx916\tx1832\tx2748\tx3664\tx4580\tx5496\tx6412\tx7328\tx8244\tx9160\tx10076\tx10992\tx11908\tx12824\tx13740\tx14656\wrapdefault\aspalpha\aspnum\faauto\adjustright\rin0\lin0\itap0\pararsid11754636 \cbpat8 { -\rtlch\fcs1 \af1\afs18 \ltrch\fcs0 \f1\fs18\cf1\lang2057\langfe2057\langfenp2057\insrsid11754636 Separate Files -\par }\pard \ltrpar\qj \li0\ri0\sa200\sl276\slmult1\widctlpar\wrapdefault\aspalpha\aspnum\faauto\adjustright\rin0\lin0\itap0\pararsid11754636 {\rtlch\fcs1 \af1\afs18 \ltrch\fcs0 \f1\fs18\cf1\lang2057\langfe2057\langfenp2057\insrsid11754636 The }{\rtlch\fcs1 -\af1\afs18 \ltrch\fcs0 \f1\fs18\cf1\lang2057\langfe2057\langfenp2057\insrsid11754636\charrsid15098396 package }{\rtlch\fcs1 \af1\afs18 \ltrch\fcs0 \f1\fs18\cf1\lang2057\langfe2057\langfenp2057\insrsid11754636 also }{\rtlch\fcs1 \af1\afs18 \ltrch\fcs0 -\f1\fs18\cf1\lang2057\langfe2057\langfenp2057\insrsid11754636\charrsid15098396 includes the components}{\rtlch\fcs1 \af1\afs18 \ltrch\fcs0 \f1\fs18\cf1\lang2057\langfe2057\langfenp2057\insrsid11754636 contained in the following directories}{\rtlch\fcs1 -\af1\afs18 \ltrch\fcs0 \f1\fs18\cf1\lang2057\langfe2057\langfenp2057\insrsid11754636\charrsid15098396 :}{\rtlch\fcs1 \af1\afs18 \ltrch\fcs0 \f1\fs18\cf1\lang2057\langfe2057\langfenp2057\insrsid11754636 -\par {\listtext\pard\plain\ltrpar \rtlch\fcs1 \af1\afs18 \ltrch\fcs0 \f1\fs18\cf1\insrsid11754636 \hich\af1\dbch\af0\loch\f1 (a)\tab}}\pard \ltrpar -\qj \fi-360\li720\ri0\widctlpar\wrapdefault\aspalpha\aspnum\faauto\ls16\adjustright\rin0\lin720\itap0\pararsid11754636 {\rtlch\fcs1 \af1\afs18 \ltrch\fcs0 \f1\fs18\cf1\lang2057\langfe2057\langfenp2057\insrsid11754636 ./}{\rtlch\fcs1 \af1\afs18 -\ltrch\fcs0 \f1\fs18\insrsid11754636\charrsid7090778 \hich\af1\dbch\af37\loch\f1 CMSIS}{\rtlch\fcs1 \af1\afs18 \ltrch\fcs0 \f1\fs18\insrsid11754636 \hich\af1\dbch\af37\loch\f1 /}{\rtlch\fcs1 \af1\afs18 \ltrch\fcs0 \f1\fs18\insrsid11754636\charrsid7090778 -\hich\af1\dbch\af37\loch\f1 DSP_Lib}{\rtlch\fcs1 \af1\afs18 \ltrch\fcs0 \f1\fs18\insrsid11754636 \hich\af1\dbch\af37\loch\f1 - }{\rtlch\fcs1 \af1\afs18 \ltrch\fcs0 \f1\fs18\cf1\lang2057\langfe2057\langfenp2057\insrsid11754636\charrsid15098396 -DSP Library sources and examples}{\rtlch\fcs1 \af1\afs18 \ltrch\fcs0 \f1\fs18\insrsid11754636 \hich\af1\dbch\af37\loch\f1 ; -\par {\listtext\pard\plain\ltrpar \rtlch\fcs1 \af1\afs18 \ltrch\fcs0 \f1\fs18\cf1\insrsid11754636 \hich\af1\dbch\af0\loch\f1 (b)\tab}}{\rtlch\fcs1 \af1\afs18 \ltrch\fcs0 \f1\fs18\cf1\lang2057\langfe2057\langfenp2057\insrsid11754636 ./}{\rtlch\fcs1 \af1\afs18 -\ltrch\fcs0 \f1\fs18\insrsid11754636\charrsid7090778 \hich\af1\dbch\af37\loch\f1 CMSIS}{\rtlch\fcs1 \af1\afs18 \ltrch\fcs0 \f1\fs18\insrsid11754636 \hich\af1\dbch\af37\loch\f1 /}{\rtlch\fcs1 \af1\afs18 \ltrch\fcs0 \f1\fs18\insrsid11754636\charrsid7090778 -\hich\af1\dbch\af37\loch\f1 Include}{\rtlch\fcs1 \af1\afs18 \ltrch\fcs0 \f1\fs18\insrsid11754636 \hich\af1\dbch\af37\loch\f1 - Header files; -\par {\listtext\pard\plain\ltrpar \rtlch\fcs1 \af1\afs18 \ltrch\fcs0 \f1\fs18\cf1\insrsid11754636 \hich\af1\dbch\af0\loch\f1 (c)\tab}}{\rtlch\fcs1 \af1\afs18 \ltrch\fcs0 \f1\fs18\cf1\lang2057\langfe2057\langfenp2057\insrsid11754636 ./}{\rtlch\fcs1 \af1\afs18 -\ltrch\fcs0 \f1\fs18\insrsid11754636\charrsid7090778 \hich\af1\dbch\af37\loch\f1 CMSIS}{\rtlch\fcs1 \af1\afs18 \ltrch\fcs0 \f1\fs18\insrsid11754636 \hich\af1\dbch\af37\loch\f1 /}{\rtlch\fcs1 \af1\afs18 \ltrch\fcs0 \f1\fs18\insrsid11754636\charrsid7090778 -\hich\af1\dbch\af37\loch\f1 Lib}{\rtlch\fcs1 \af1\afs18 \ltrch\fcs0 \f1\fs18\insrsid11754636 \hich\af1\dbch\af37\loch\f1 - }{\rtlch\fcs1 \af1\afs18 \ltrch\fcs0 \f1\fs18\insrsid11754636\charrsid7090778 \hich\af1\dbch\af37\loch\f1 -DSP Library build for various toolchains}{\rtlch\fcs1 \af1\afs18 \ltrch\fcs0 \f1\fs18\insrsid11754636 \hich\af1\dbch\af37\loch\f1 ; -\par {\listtext\pard\plain\ltrpar \rtlch\fcs1 \af1\afs18 \ltrch\fcs0 \f1\fs18\cf1\insrsid11754636 \hich\af1\dbch\af0\loch\f1 (d)\tab}}{\rtlch\fcs1 \af1\afs18 \ltrch\fcs0 \f1\fs18\cf1\lang2057\langfe2057\langfenp2057\insrsid11754636 ./}{\rtlch\fcs1 \af1\afs18 -\ltrch\fcs0 \f1\fs18\insrsid11754636\charrsid7090778 \hich\af1\dbch\af37\loch\f1 CMSIS}{\rtlch\fcs1 \af1\afs18 \ltrch\fcs0 \f1\fs18\insrsid11754636 \hich\af1\dbch\af37\loch\f1 /}{\rtlch\fcs1 \af1\afs18 \ltrch\fcs0 \f1\fs18\insrsid11754636\charrsid7090778 -\hich\af1\dbch\af37\loch\f1 RTOS}{\rtlch\fcs1 \af1\afs18 \ltrch\fcs0 \f1\fs18\insrsid11754636 \hich\af1\dbch\af37\loch\f1 - }{\rtlch\fcs1 \af1\afs18 \ltrch\fcs0 \f1\fs18\insrsid11754636\charrsid7090778 \hich\af1\dbch\af37\loch\f1 -Header file template for CMSIS-RTOS implementation}{\rtlch\fcs1 \af1\afs18 \ltrch\fcs0 \f1\fs18\insrsid11754636 \hich\af1\dbch\af37\loch\f1 ; and -\par {\listtext\pard\plain\ltrpar \rtlch\fcs1 \af1\afs18 \ltrch\fcs0 \f1\fs18\cf1\insrsid11754636 \hich\af1\dbch\af0\loch\f1 (e)\tab}}{\rtlch\fcs1 \af1\afs18 \ltrch\fcs0 \f1\fs18\cf1\lang2057\langfe2057\langfenp2057\insrsid11754636 .}{\rtlch\fcs1 \af1\afs18 -\ltrch\fcs0 \f1\fs18\insrsid11754636 \hich\af1\dbch\af37\loch\f1 /Device - T}{\rtlch\fcs1 \af1\afs18 \ltrch\fcs0 \f1\fs18\insrsid11754636\charrsid14488502 \hich\af1\dbch\af37\loch\f1 emplate files and implementations for Cortex-M class processors}{ -\rtlch\fcs1 \af1\afs18 \ltrch\fcs0 \f1\fs18\insrsid11754636 \hich\af1\dbch\af37\loch\f1 . -\par }\pard \ltrpar\qj \li0\ri0\sa200\sl276\slmult1\widctlpar\wrapdefault\aspalpha\aspnum\faauto\adjustright\rin0\lin0\itap0\pararsid11754636 {\rtlch\fcs1 \af1\afs18 \ltrch\fcs0 \f1\fs18\insrsid11754636 -\par \hich\af1\dbch\af37\loch\f1 All of the above components (a\hich\f1 \endash \loch\f1 e) are licensed to you under the terms of the BSD licence, which is incorp\hich\af1\dbch\af37\loch\f1 orated within or alongside the above components. -\par }\pard \ltrpar\qj \li284\ri0\widctlpar\wrapdefault\aspalpha\aspnum\faauto\adjustright\rin0\lin284\itap0\pararsid11754636 {\rtlch\fcs1 \af1\afs18 \ltrch\fcs0 \f1\fs18\insrsid11754636 \hich\af1\dbch\af37\loch\f1 }{\rtlch\fcs1 \af1\afs18 \ltrch\fcs0 -\f1\fs18\insrsid11754636\charrsid13975144 \hich\af1\dbch\af37\loch\f1 (f)}{\rtlch\fcs1 \af1\afs18 \ltrch\fcs0 \f1\fs18\insrsid11754636 \hich\af1\dbch\af37\loch\f1 }{\rtlch\fcs1 \af1\afs18 \ltrch\fcs0 \f1\fs18\insrsid11754636\charrsid13975144 -\hich\af1\dbch\af37\loch\f1 ./CMSIS/Driver \hich\f1 \endash \loch\f1 CMSIS-Driver header files}{\rtlch\fcs1 \af1\afs18 \ltrch\fcs0 \f1\fs18\insrsid11754636 -\par }{\rtlch\fcs1 \af1\afs18 \ltrch\fcs0 \f1\fs18\insrsid11754636\charrsid13975144 \hich\af1\dbch\af37\loch\f1 (g)}{\rtlch\fcs1 \af1\afs18 \ltrch\fcs0 \f1\fs18\insrsid11754636 \hich\af1\dbch\af37\loch\f1 }{\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid11754636 -\hich\af37\dbch\af37\loch\f37 }{\rtlch\fcs1 \af1\afs18 \ltrch\fcs0 \f1\fs18\insrsid11754636 \hich\af1\dbch\af37\loch\f1 ./CMSIS/Pack \hich\f1 \endash \loch\f1 Example Device Family Pack}{\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid11754636\charrsid13975144 - -\par }\pard\plain \ltrpar\s32\ql \li0\ri0\widctlpar\wrapdefault\aspalpha\aspnum\faauto\adjustright\rin0\lin0\itap0\pararsid11754636 \rtlch\fcs1 \af0\afs21\alang1025 \ltrch\fcs0 \f39\fs21\lang2057\langfe1033\cgrid\langnp2057\langfenp1033 {\rtlch\fcs1 -\af1\afs18 \ltrch\fcs0 \f1\fs18\insrsid11754636 -\par The above components (f \endash g) are licensed to you under the terms of the zlib licence, which is incorporated within or alongside the above components. -\par -\par }{\rtlch\fcs1 \af1\afs18 \ltrch\fcs0 \f1\fs18\insrsid11754636\charrsid14488502 }{\rtlch\fcs1 \af1\afs18 \ltrch\fcs0 \f1\fs18\insrsid11754636 -\par -\par -\par }\pard\plain \ltrpar\qj \li0\ri0\sa200\sl276\slmult1\widctlpar\wrapdefault\aspalpha\aspnum\faauto\adjustright\rin0\lin0\itap0\pararsid11754636 \rtlch\fcs1 \af0\afs22\alang1025 \ltrch\fcs0 -\fs22\lang2057\langfe1033\loch\af37\hich\af37\dbch\af37\cgrid\langnp2057\langfenp1033 {\rtlch\fcs1 \af1\afs18 \ltrch\fcs0 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-000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000105000000000000}} \ No newline at end of file diff --git a/bsp/essemi/es32f0271/libraries/CMSIS/Device/EastSoft/ES32F0271/Include/ES32F0271/reg_ad16c4t.h b/bsp/essemi/es32f0271/libraries/CMSIS/Device/EastSoft/ES32F0271/Include/ES32F0271/reg_ad16c4t.h deleted file mode 100644 index f70a10e35c..0000000000 --- a/bsp/essemi/es32f0271/libraries/CMSIS/Device/EastSoft/ES32F0271/Include/ES32F0271/reg_ad16c4t.h +++ /dev/null @@ -1,683 +0,0 @@ -/** - ************************************************************************************** - * @file reg_AD16C4T.h - * @brief AD16C4T Head File - * - * @version V0.01 - * @date 3/12/2018 - * @author Eastsoft MCU Software Team - * @note - * - * Copyright (C) 2018 Shanghai Eastsoft Microelectronics Co., Ltd. ALL rights reserved. - * - ************************************************************************************** - */ - -#ifndef __REG_AD16C4T_H__ -#define __REG_AD16C4T_H__ - - -/******************************************************************************/ -/* 设备特殊寄存器结构定义 */ -/******************************************************************************/ - -/* 允许匿名结构和匿名联合 */ -/* #pragma anon_unions */ - -/****************** Bit definition for AD16C4T_CON1 register ************************/ - -#define AD16C4T_CON1_DBGSEL_POS 15U -#define AD16C4T_CON1_DBGSEL_MSK BIT(AD16C4T_CON1_DBGSEL_POS) - -#define AD16C4T_CON1_CMPSEL_POSS 11U -#define AD16C4T_CON1_CMPSEL_POSE 13U -#define AD16C4T_CON1_CMPSEL_MSK BITS(AD16C4T_CON1_CMPSEL_POSS,AD16C4T_CON1_CMPSEL_POSE) - -#define AD16C4T_CON1_CMPSELP_POS 10U -#define AD16C4T_CON1_CMPSELP_MSK BIT(AD16C4T_CON1_CMPSELP_POS) - -#define AD16C4T_CON1_DFCKSEL_POSS 8U -#define AD16C4T_CON1_DFCKSEL_POSE 9U -#define AD16C4T_CON1_DFCKSEL_MSK BITS(AD16C4T_CON1_DFCKSEL_POSS,AD16C4T_CON1_DFCKSEL_POSE) - -#define AD16C4T_CON1_ARPEN_POS 7U -#define AD16C4T_CON1_ARPEN_MSK BIT(AD16C4T_CON1_ARPEN_POS) - -#define AD16C4T_CON1_CMSEL_POSS 5U -#define AD16C4T_CON1_CMSEL_POSE 6U -#define AD16C4T_CON1_CMSEL_MSK BITS(AD16C4T_CON1_CMSEL_POSS,AD16C4T_CON1_CMSEL_POSE) - -#define AD16C4T_CON1_DIRSEL_POS 4U -#define AD16C4T_CON1_DIRSEL_MSK BIT(AD16C4T_CON1_DIRSEL_POS) - -#define AD16C4T_CON1_SPMEN_POS 3U -#define AD16C4T_CON1_SPMEN_MSK BIT(AD16C4T_CON1_SPMEN_POS) - -#define AD16C4T_CON1_UERSEL_POS 2U -#define AD16C4T_CON1_UERSEL_MSK BIT(AD16C4T_CON1_UERSEL_POS) - -#define AD16C4T_CON1_DISUE_POS 1U -#define AD16C4T_CON1_DISUE_MSK BIT(AD16C4T_CON1_DISUE_POS) - -#define AD16C4T_CON1_CNTEN_POS 0U -#define AD16C4T_CON1_CNTEN_MSK BIT(AD16C4T_CON1_CNTEN_POS) - -/****************** Bit definition for AD16C4T_CON2 register ************************/ - -#define AD16C4T_CON2_OISS4_POS 14U -#define AD16C4T_CON2_OISS4_MSK BIT(AD16C4T_CON2_OISS4_POS) - -#define AD16C4T_CON2_OISS3N_POS 13U -#define AD16C4T_CON2_OISS3N_MSK BIT(AD16C4T_CON2_OISS3N_POS) - -#define AD16C4T_CON2_OISS3_POS 12U -#define AD16C4T_CON2_OISS3_MSK BIT(AD16C4T_CON2_OISS3_POS) - -#define AD16C4T_CON2_OISS2N_POS 11U -#define AD16C4T_CON2_OISS2N_MSK BIT(AD16C4T_CON2_OISS2N_POS) - -#define AD16C4T_CON2_OISS2_POS 10U -#define AD16C4T_CON2_OISS2_MSK BIT(AD16C4T_CON2_OISS2_POS) - -#define AD16C4T_CON2_OISS1N_POS 9U -#define AD16C4T_CON2_OISS1N_MSK BIT(AD16C4T_CON2_OISS1N_POS) - -#define AD16C4T_CON2_OISS1_POS 8U -#define AD16C4T_CON2_OISS1_MSK BIT(AD16C4T_CON2_OISS1_POS) - -#define AD16C4T_CON2_I1SEL_POS 7U -#define AD16C4T_CON2_I1SEL_MSK BIT(AD16C4T_CON2_I1SEL_POS) - -#define AD16C4T_CON2_MMSEL_POSS 4U -#define AD16C4T_CON2_MMSEL_POSE 6U -#define AD16C4T_CON2_MMSEL_MSK BITS(AD16C4T_CON2_MMSEL_POSS,AD16C4T_CON2_MMSEL_POSE) - -#define AD16C4T_CON2_CCDMASEL_POS 3U -#define AD16C4T_CON2_CCDMASEL_MSK BIT(AD16C4T_CON2_CCDMASEL_POS) - -#define AD16C4T_CON2_CCUSEL_POS 2U -#define AD16C4T_CON2_CCUSEL_MSK BIT(AD16C4T_CON2_CCUSEL_POS) - -#define AD16C4T_CON2_CCPCEN_POS 0U -#define AD16C4T_CON2_CCPCEN_MSK BIT(AD16C4T_CON2_CCPCEN_POS) - -/****************** Bit definition for AD16C4T_SMCON register ************************/ - -#define AD16C4T_SMCON_ETPOL_POS 15U -#define AD16C4T_SMCON_ETPOL_MSK BIT(AD16C4T_SMCON_ETPOL_POS) - -#define AD16C4T_SMCON_ECM2EN_POS 14U -#define AD16C4T_SMCON_ECM2EN_MSK BIT(AD16C4T_SMCON_ECM2EN_POS) - -#define AD16C4T_SMCON_ETFLT_POSS 8U -#define AD16C4T_SMCON_ETFLT_POSE 11U -#define AD16C4T_SMCON_ETFLT_MSK BITS(AD16C4T_SMCON_ETFLT_POSS,AD16C4T_SMCON_ETFLT_POSE) - -#define AD16C4T_SMCON_MSCFG_POS 7U -#define AD16C4T_SMCON_MSCFG_MSK BIT(AD16C4T_SMCON_MSCFG_POS) - -#define AD16C4T_SMCON_TSSEL_POSS 4U -#define AD16C4T_SMCON_TSSEL_POSE 6U -#define AD16C4T_SMCON_TSSEL_MSK BITS(AD16C4T_SMCON_TSSEL_POSS,AD16C4T_SMCON_TSSEL_POSE) - -#define AD16C4T_SMCON_CHCSEL_POS 3U -#define AD16C4T_SMCON_CHCSEL_MSK BIT(AD16C4T_SMCON_CHCSEL_POS) - -#define AD16C4T_SMCON_SMODS_POSS 0U -#define AD16C4T_SMCON_SMODS_POSE 2U -#define AD16C4T_SMCON_SMODS_MSK BITS(AD16C4T_SMCON_SMODS_POSS,AD16C4T_SMCON_SMODS_POSE) - -/****************** Bit definition for AD16C4T_IER register ************************/ - -#define AD16C4T_IER_CH4OVI_POS 12U -#define AD16C4T_IER_CH4OVI_MSK BIT(AD16C4T_IER_CH4OVI_POS) - -#define AD16C4T_IER_CH3OVI_POS 11U -#define AD16C4T_IER_CH3OVI_MSK BIT(AD16C4T_IER_CH3OVI_POS) - -#define AD16C4T_IER_CH2OVI_POS 10U -#define AD16C4T_IER_CH2OVI_MSK BIT(AD16C4T_IER_CH2OVI_POS) - -#define AD16C4T_IER_CH1OVI_POS 9U -#define AD16C4T_IER_CH1OVI_MSK BIT(AD16C4T_IER_CH1OVI_POS) - -#define AD16C4T_IER_BRKI_POS 7U -#define AD16C4T_IER_BRKI_MSK BIT(AD16C4T_IER_BRKI_POS) - -#define AD16C4T_IER_TRGI_POS 6U -#define AD16C4T_IER_TRGI_MSK BIT(AD16C4T_IER_TRGI_POS) - -#define AD16C4T_IER_COMI_POS 5U -#define AD16C4T_IER_COMI_MSK BIT(AD16C4T_IER_COMI_POS) - -#define AD16C4T_IER_CH4I_POS 4U -#define AD16C4T_IER_CH4I_MSK BIT(AD16C4T_IER_CH4I_POS) - -#define AD16C4T_IER_CH3I_POS 3U -#define AD16C4T_IER_CH3I_MSK BIT(AD16C4T_IER_CH3I_POS) - -#define AD16C4T_IER_CH2I_POS 2U -#define AD16C4T_IER_CH2I_MSK BIT(AD16C4T_IER_CH2I_POS) - -#define AD16C4T_IER_CH1I_POS 1U -#define AD16C4T_IER_CH1I_MSK BIT(AD16C4T_IER_CH1I_POS) - -#define AD16C4T_IER_UI_POS 0U -#define AD16C4T_IER_UI_MSK BIT(AD16C4T_IER_UI_POS) - -/****************** Bit definition for AD16C4T_IDR register ************************/ - -#define AD16C4T_IDR_CH4OVI_POS 12U -#define AD16C4T_IDR_CH4OVI_MSK BIT(AD16C4T_IDR_CH4OVI_POS) - -#define AD16C4T_IDR_CH3OVI_POS 11U -#define AD16C4T_IDR_CH3OVI_MSK BIT(AD16C4T_IDR_CH3OVI_POS) - -#define AD16C4T_IDR_CH2OVI_POS 10U -#define AD16C4T_IDR_CH2OVI_MSK BIT(AD16C4T_IDR_CH2OVI_POS) - -#define AD16C4T_IDR_CH1OVI_POS 9U -#define AD16C4T_IDR_CH1OVI_MSK BIT(AD16C4T_IDR_CH1OVI_POS) - -#define AD16C4T_IDR_BRKI_POS 7U -#define AD16C4T_IDR_BRKI_MSK BIT(AD16C4T_IDR_BRKI_POS) - -#define AD16C4T_IDR_TRGI_POS 6U -#define AD16C4T_IDR_TRGI_MSK BIT(AD16C4T_IDR_TRGI_POS) - -#define AD16C4T_IDR_COMI_POS 5U -#define AD16C4T_IDR_COMI_MSK BIT(AD16C4T_IDR_COMI_POS) - -#define AD16C4T_IDR_CH4I_POS 4U -#define AD16C4T_IDR_CH4I_MSK BIT(AD16C4T_IDR_CH4I_POS) - -#define AD16C4T_IDR_CH3I_POS 3U -#define AD16C4T_IDR_CH3I_MSK BIT(AD16C4T_IDR_CH3I_POS) - -#define AD16C4T_IDR_CH2I_POS 2U -#define AD16C4T_IDR_CH2I_MSK BIT(AD16C4T_IDR_CH2I_POS) - -#define AD16C4T_IDR_CH1I_POS 1U -#define AD16C4T_IDR_CH1I_MSK BIT(AD16C4T_IDR_CH1I_POS) - -#define AD16C4T_IDR_UI_POS 0U -#define AD16C4T_IDR_UI_MSK BIT(AD16C4T_IDR_UI_POS) - -/****************** Bit definition for AD16C4T_IVS register ************************/ - -#define AD16C4T_IVS_CH4OVI_POS 12U -#define AD16C4T_IVS_CH4OVI_MSK BIT(AD16C4T_IVS_CH4OVI_POS) - -#define AD16C4T_IVS_CH3OVI_POS 11U -#define AD16C4T_IVS_CH3OVI_MSK BIT(AD16C4T_IVS_CH3OVI_POS) - -#define AD16C4T_IVS_CH2OVI_POS 10U -#define AD16C4T_IVS_CH2OVI_MSK BIT(AD16C4T_IVS_CH2OVI_POS) - -#define AD16C4T_IVS_CH1OVI_POS 9U -#define AD16C4T_IVS_CH1OVI_MSK BIT(AD16C4T_IVS_CH1OVI_POS) - -#define AD16C4T_IVS_BRKI_POS 7U -#define AD16C4T_IVS_BRKI_MSK BIT(AD16C4T_IVS_BRKI_POS) - -#define AD16C4T_IVS_TRGI_POS 6U -#define AD16C4T_IVS_TRGI_MSK BIT(AD16C4T_IVS_TRGI_POS) - -#define AD16C4T_IVS_COMI_POS 5U -#define AD16C4T_IVS_COMI_MSK BIT(AD16C4T_IVS_COMI_POS) - -#define AD16C4T_IVS_CH4I_POS 4U -#define AD16C4T_IVS_CH4I_MSK BIT(AD16C4T_IVS_CH4I_POS) - -#define AD16C4T_IVS_CH3I_POS 3U -#define AD16C4T_IVS_CH3I_MSK BIT(AD16C4T_IVS_CH3I_POS) - -#define AD16C4T_IVS_CH2I_POS 2U -#define AD16C4T_IVS_CH2I_MSK BIT(AD16C4T_IVS_CH2I_POS) - -#define AD16C4T_IVS_CH1I_POS 1U -#define AD16C4T_IVS_CH1I_MSK BIT(AD16C4T_IVS_CH1I_POS) - -#define AD16C4T_IVS_UI_POS 0U -#define AD16C4T_IVS_UI_MSK BIT(AD16C4T_IVS_UI_POS) - -/****************** Bit definition for AD16C4T_RIF register ************************/ - -#define AD16C4T_RIF_CH4OVI_POS 12U -#define AD16C4T_RIF_CH4OVI_MSK BIT(AD16C4T_RIF_CH4OVI_POS) - -#define AD16C4T_RIF_CH3OVI_POS 11U -#define AD16C4T_RIF_CH3OVI_MSK BIT(AD16C4T_RIF_CH3OVI_POS) - -#define AD16C4T_RIF_CH2OVI_POS 10U -#define AD16C4T_RIF_CH2OVI_MSK BIT(AD16C4T_RIF_CH2OVI_POS) - -#define AD16C4T_RIF_CH1OVI_POS 9U -#define AD16C4T_RIF_CH1OVI_MSK BIT(AD16C4T_RIF_CH1OVI_POS) - -#define AD16C4T_RIF_BRKI_POS 7U -#define AD16C4T_RIF_BRKI_MSK BIT(AD16C4T_RIF_BRKI_POS) - -#define AD16C4T_RIF_TRGI_POS 6U -#define AD16C4T_RIF_TRGI_MSK BIT(AD16C4T_RIF_TRGI_POS) - -#define AD16C4T_RIF_COMI_POS 5U -#define AD16C4T_RIF_COMI_MSK BIT(AD16C4T_RIF_COMI_POS) - -#define AD16C4T_RIF_CH4I_POS 4U -#define AD16C4T_RIF_CH4I_MSK BIT(AD16C4T_RIF_CH4I_POS) - -#define AD16C4T_RIF_CH3I_POS 3U -#define AD16C4T_RIF_CH3I_MSK BIT(AD16C4T_RIF_CH3I_POS) - -#define AD16C4T_RIF_CH2I_POS 2U -#define AD16C4T_RIF_CH2I_MSK BIT(AD16C4T_RIF_CH2I_POS) - -#define AD16C4T_RIF_CH1I_POS 1U -#define AD16C4T_RIF_CH1I_MSK BIT(AD16C4T_RIF_CH1I_POS) - -#define AD16C4T_RIF_UI_POS 0U -#define AD16C4T_RIF_UI_MSK BIT(AD16C4T_RIF_UI_POS) - -/****************** Bit definition for AD16C4T_IFM register ************************/ - -#define AD16C4T_IFM_CH4OVI_POS 12U -#define AD16C4T_IFM_CH4OVI_MSK BIT(AD16C4T_IFM_CH4OVI_POS) - -#define AD16C4T_IFM_CH3OVI_POS 11U -#define AD16C4T_IFM_CH3OVI_MSK BIT(AD16C4T_IFM_CH3OVI_POS) - -#define AD16C4T_IFM_CH2OVI_POS 10U -#define AD16C4T_IFM_CH2OVI_MSK BIT(AD16C4T_IFM_CH2OVI_POS) - -#define AD16C4T_IFM_CH1OVI_POS 9U -#define AD16C4T_IFM_CH1OVI_MSK BIT(AD16C4T_IFM_CH1OVI_POS) - -#define AD16C4T_IFM_BRKI_POS 7U -#define AD16C4T_IFM_BRKI_MSK BIT(AD16C4T_IFM_BRKI_POS) - -#define AD16C4T_IFM_TRGI_POS 6U -#define AD16C4T_IFM_TRGI_MSK BIT(AD16C4T_IFM_TRGI_POS) - -#define AD16C4T_IFM_COMI_POS 5U -#define AD16C4T_IFM_COMI_MSK BIT(AD16C4T_IFM_COMI_POS) - -#define AD16C4T_IFM_CH4I_POS 4U -#define AD16C4T_IFM_CH4I_MSK BIT(AD16C4T_IFM_CH4I_POS) - -#define AD16C4T_IFM_CH3I_POS 3U -#define AD16C4T_IFM_CH3I_MSK BIT(AD16C4T_IFM_CH3I_POS) - -#define AD16C4T_IFM_CH2I_POS 2U -#define AD16C4T_IFM_CH2I_MSK BIT(AD16C4T_IFM_CH2I_POS) - -#define AD16C4T_IFM_CH1I_POS 1U -#define AD16C4T_IFM_CH1I_MSK BIT(AD16C4T_IFM_CH1I_POS) - -#define AD16C4T_IFM_UI_POS 0U -#define AD16C4T_IFM_UI_MSK BIT(AD16C4T_IFM_UI_POS) - -/****************** Bit definition for AD16C4T_ICR register ************************/ - -#define AD16C4T_ICR_CH4OVI_POS 12U -#define AD16C4T_ICR_CH4OVI_MSK BIT(AD16C4T_ICR_CH4OVI_POS) - -#define AD16C4T_ICR_CH3OVI_POS 11U -#define AD16C4T_ICR_CH3OVI_MSK BIT(AD16C4T_ICR_CH3OVI_POS) - -#define AD16C4T_ICR_CH2OVI_POS 10U -#define AD16C4T_ICR_CH2OVI_MSK BIT(AD16C4T_ICR_CH2OVI_POS) - -#define AD16C4T_ICR_CH1OVI_POS 9U -#define AD16C4T_ICR_CH1OVI_MSK BIT(AD16C4T_ICR_CH1OVI_POS) - -#define AD16C4T_ICR_BRKI_POS 7U -#define AD16C4T_ICR_BRKI_MSK BIT(AD16C4T_ICR_BRKI_POS) - -#define AD16C4T_ICR_TRGI_POS 6U -#define AD16C4T_ICR_TRGI_MSK BIT(AD16C4T_ICR_TRGI_POS) - -#define AD16C4T_ICR_COMI_POS 5U -#define AD16C4T_ICR_COMI_MSK BIT(AD16C4T_ICR_COMI_POS) - -#define AD16C4T_ICR_CH4I_POS 4U -#define AD16C4T_ICR_CH4I_MSK BIT(AD16C4T_ICR_CH4I_POS) - -#define AD16C4T_ICR_CH3I_POS 3U -#define AD16C4T_ICR_CH3I_MSK BIT(AD16C4T_ICR_CH3I_POS) - -#define AD16C4T_ICR_CH2I_POS 2U -#define AD16C4T_ICR_CH2I_MSK BIT(AD16C4T_ICR_CH2I_POS) - -#define AD16C4T_ICR_CH1I_POS 1U -#define AD16C4T_ICR_CH1I_MSK BIT(AD16C4T_ICR_CH1I_POS) - -#define AD16C4T_ICR_UI_POS 0U -#define AD16C4T_ICR_UI_MSK BIT(AD16C4T_ICR_UI_POS) - -/****************** Bit definition for AD16C4T_SGE register ************************/ - -#define AD16C4T_SGE_SGBRK_POS 7U -#define AD16C4T_SGE_SGBRK_MSK BIT(AD16C4T_SGE_SGBRK_POS) - -#define AD16C4T_SGE_SGTRG_POS 6U -#define AD16C4T_SGE_SGTRG_MSK BIT(AD16C4T_SGE_SGTRG_POS) - -#define AD16C4T_SGE_SGCOM_POS 5U -#define AD16C4T_SGE_SGCOM_MSK BIT(AD16C4T_SGE_SGCOM_POS) - -#define AD16C4T_SGE_SGCH4_POS 4U -#define AD16C4T_SGE_SGCH4_MSK BIT(AD16C4T_SGE_SGCH4_POS) - -#define AD16C4T_SGE_SGCH3_POS 3U -#define AD16C4T_SGE_SGCH3_MSK BIT(AD16C4T_SGE_SGCH3_POS) - -#define AD16C4T_SGE_SGCH2_POS 2U -#define AD16C4T_SGE_SGCH2_MSK BIT(AD16C4T_SGE_SGCH2_POS) - -#define AD16C4T_SGE_SGCH1_POS 1U -#define AD16C4T_SGE_SGCH1_MSK BIT(AD16C4T_SGE_SGCH1_POS) - -#define AD16C4T_SGE_SGU_POS 0U -#define AD16C4T_SGE_SGU_MSK BIT(AD16C4T_SGE_SGU_POS) - -/****************** Bit definition for AD16C4T_CHMR1_OUTPUT register ************************/ - -#define AD16C4T_CHMR1_OUTPUT_CH2OCLREN_POS 15U -#define AD16C4T_CHMR1_OUTPUT_CH2OCLREN_MSK BIT(AD16C4T_CHMR1_OUTPUT_CH2OCLREN_POS) - -#define AD16C4T_CHMR1_OUTPUT_CH2MOD_POSS 12U -#define AD16C4T_CHMR1_OUTPUT_CH2MOD_POSE 14U -#define AD16C4T_CHMR1_OUTPUT_CH2MOD_MSK BITS(AD16C4T_CHMR1_OUTPUT_CH2MOD_POSS,AD16C4T_CHMR1_OUTPUT_CH2MOD_POSE) - -#define AD16C4T_CHMR1_OUTPUT_CH2PEN_POS 11U -#define AD16C4T_CHMR1_OUTPUT_CH2PEN_MSK BIT(AD16C4T_CHMR1_OUTPUT_CH2PEN_POS) - -#define AD16C4T_CHMR1_OUTPUT_CH2FEN_POS 10U -#define AD16C4T_CHMR1_OUTPUT_CH2FEN_MSK BIT(AD16C4T_CHMR1_OUTPUT_CH2FEN_POS) - -#define AD16C4T_CHMR1_OUTPUT_CC2SSEL_POSS 8U -#define AD16C4T_CHMR1_OUTPUT_CC2SSEL_POSE 9U -#define AD16C4T_CHMR1_OUTPUT_CC2SSEL_MSK BITS(AD16C4T_CHMR1_OUTPUT_CC2SSEL_POSS,AD16C4T_CHMR1_OUTPUT_CC2SSEL_POSE) - -#define AD16C4T_CHMR1_OUTPUT_CH1OCLREN_POS 7U -#define AD16C4T_CHMR1_OUTPUT_CH1OCLREN_MSK BIT(AD16C4T_CHMR1_OUTPUT_CH1OCLREN_POS) - -#define AD16C4T_CHMR1_OUTPUT_CH1MOD_POSS 4U -#define AD16C4T_CHMR1_OUTPUT_CH1MOD_POSE 6U -#define AD16C4T_CHMR1_OUTPUT_CH1MOD_MSK BITS(AD16C4T_CHMR1_OUTPUT_CH1MOD_POSS,AD16C4T_CHMR1_OUTPUT_CH1MOD_POSE) - -#define AD16C4T_CHMR1_OUTPUT_CH1PEN_POS 3U -#define AD16C4T_CHMR1_OUTPUT_CH1PEN_MSK BIT(AD16C4T_CHMR1_OUTPUT_CH1PEN_POS) - -#define AD16C4T_CHMR1_OUTPUT_CH1FEN_POS 2U -#define AD16C4T_CHMR1_OUTPUT_CH1FEN_MSK BIT(AD16C4T_CHMR1_OUTPUT_CH1FEN_POS) - -#define AD16C4T_CHMR1_OUTPUT_CC1SSEL_POSS 0U -#define AD16C4T_CHMR1_OUTPUT_CC1SSEL_POSE 1U -#define AD16C4T_CHMR1_OUTPUT_CC1SSEL_MSK BITS(AD16C4T_CHMR1_OUTPUT_CC1SSEL_POSS,AD16C4T_CHMR1_OUTPUT_CC1SSEL_POSE) - -/****************** Bit definition for AD16C4T_CHMR1_INPUT register ************************/ - -#define AD16C4T_CHMR1_INPUT_I2FLT_POSS 12U -#define AD16C4T_CHMR1_INPUT_I2FLT_POSE 15U -#define AD16C4T_CHMR1_INPUT_I2FLT_MSK BITS(AD16C4T_CHMR1_INPUT_I2FLT_POSS,AD16C4T_CHMR1_INPUT_I2FLT_POSE) - -#define AD16C4T_CHMR1_INPUT_I2PRES_POSS 10U -#define AD16C4T_CHMR1_INPUT_I2PRES_POSE 11U -#define AD16C4T_CHMR1_INPUT_I2PRES_MSK BITS(AD16C4T_CHMR1_INPUT_I2PRES_POSS,AD16C4T_CHMR1_INPUT_I2PRES_POSE) - -#define AD16C4T_CHMR1_INPUT_CC2SSEL_POSS 8U -#define AD16C4T_CHMR1_INPUT_CC2SSEL_POSE 9U -#define AD16C4T_CHMR1_INPUT_CC2SSEL_MSK BITS(AD16C4T_CHMR1_INPUT_CC2SSEL_POSS,AD16C4T_CHMR1_INPUT_CC2SSEL_POSE) - -#define AD16C4T_CHMR1_INPUT_I1FLT_POSS 4U -#define AD16C4T_CHMR1_INPUT_I1FLT_POSE 7U -#define AD16C4T_CHMR1_INPUT_I1FLT_MSK BITS(AD16C4T_CHMR1_INPUT_I1FLT_POSS,AD16C4T_CHMR1_INPUT_I1FLT_POSE) - -#define AD16C4T_CHMR1_INPUT_I1PRES_POSS 2U -#define AD16C4T_CHMR1_INPUT_I1PRES_POSE 3U -#define AD16C4T_CHMR1_INPUT_I1PRES_MSK BITS(AD16C4T_CHMR1_INPUT_I1PRES_POSS,AD16C4T_CHMR1_INPUT_I1PRES_POSE) - -#define AD16C4T_CHMR1_INPUT_CC1SSEL_POSS 0U -#define AD16C4T_CHMR1_INPUT_CC1SSEL_POSE 1U -#define AD16C4T_CHMR1_INPUT_CC1SSEL_MSK BITS(AD16C4T_CHMR1_INPUT_CC1SSEL_POSS,AD16C4T_CHMR1_INPUT_CC1SSEL_POSE) - -/****************** Bit definition for AD16C4T_CHMR2_OUTPUT register ************************/ - -#define AD16C4T_CHMR2_OUTPUT_CH4OCLREN_POS 15U -#define AD16C4T_CHMR2_OUTPUT_CH4OCLREN_MSK BIT(AD16C4T_CHMR2_OUTPUT_CH4OCLREN_POS) - -#define AD16C4T_CHMR2_OUTPUT_CH4MOD_POSS 12U -#define AD16C4T_CHMR2_OUTPUT_CH4MOD_POSE 14U -#define AD16C4T_CHMR2_OUTPUT_CH4MOD_MSK BITS(AD16C4T_CHMR2_OUTPUT_CH4MOD_POSS,AD16C4T_CHMR2_OUTPUT_CH4MOD_POSE) - -#define AD16C4T_CHMR2_OUTPUT_CH4PEN_POS 11U -#define AD16C4T_CHMR2_OUTPUT_CH4PEN_MSK BIT(AD16C4T_CHMR2_OUTPUT_CH4PEN_POS) - -#define AD16C4T_CHMR2_OUTPUT_CH4FEN_POS 10U -#define AD16C4T_CHMR2_OUTPUT_CH4FEN_MSK BIT(AD16C4T_CHMR2_OUTPUT_CH4FEN_POS) - -#define AD16C4T_CHMR2_OUTPUT_CC4SSEL_POSS 8U -#define AD16C4T_CHMR2_OUTPUT_CC4SSEL_POSE 9U -#define AD16C4T_CHMR2_OUTPUT_CC4SSEL_MSK BITS(AD16C4T_CHMR2_OUTPUT_CC4SSEL_POSS,AD16C4T_CHMR2_OUTPUT_CC4SSEL_POSE) - -#define AD16C4T_CHMR2_OUTPUT_CH3OCLREN_POS 7U -#define AD16C4T_CHMR2_OUTPUT_CH3OCLREN_MSK BIT(AD16C4T_CHMR2_OUTPUT_CH3OCLREN_POS) - -#define AD16C4T_CHMR2_OUTPUT_CH3MOD_POSS 4U -#define AD16C4T_CHMR2_OUTPUT_CH3MOD_POSE 6U -#define AD16C4T_CHMR2_OUTPUT_CH3MOD_MSK BITS(AD16C4T_CHMR2_OUTPUT_CH3MOD_POSS,AD16C4T_CHMR2_OUTPUT_CH3MOD_POSE) - -#define AD16C4T_CHMR2_OUTPUT_CH3PEN_POS 3U -#define AD16C4T_CHMR2_OUTPUT_CH3PEN_MSK BIT(AD16C4T_CHMR2_OUTPUT_CH3PEN_POS) - -#define AD16C4T_CHMR2_OUTPUT_CH3FEN_POS 2U -#define AD16C4T_CHMR2_OUTPUT_CH3FEN_MSK BIT(AD16C4T_CHMR2_OUTPUT_CH3FEN_POS) - -#define AD16C4T_CHMR2_OUTPUT_CC3SSEL_POSS 0U -#define AD16C4T_CHMR2_OUTPUT_CC3SSEL_POSE 1U -#define AD16C4T_CHMR2_OUTPUT_CC3SSEL_MSK BITS(AD16C4T_CHMR2_OUTPUT_CC3SSEL_POSS,AD16C4T_CHMR2_OUTPUT_CC3SSEL_POSE) - -/****************** Bit definition for AD16C4T_CHMR2_INPUT register ************************/ - -#define AD16C4T_CHMR2_INPUT_I4FLT_POSS 12U -#define AD16C4T_CHMR2_INPUT_I4FLT_POSE 15U -#define AD16C4T_CHMR2_INPUT_I4FLT_MSK BITS(AD16C4T_CHMR2_INPUT_I4FLT_POSS,AD16C4T_CHMR2_INPUT_I4FLT_POSE) - -#define AD16C4T_CHMR2_INPUT_I4PRES_POSS 10U -#define AD16C4T_CHMR2_INPUT_I4PRES_POSE 11U -#define AD16C4T_CHMR2_INPUT_I4PRES_MSK BITS(AD16C4T_CHMR2_INPUT_I4PRES_POSS,AD16C4T_CHMR2_INPUT_I4PRES_POSE) - -#define AD16C4T_CHMR2_INPUT_CC4SSEL_POSS 8U -#define AD16C4T_CHMR2_INPUT_CC4SSEL_POSE 9U -#define AD16C4T_CHMR2_INPUT_CC4SSEL_MSK BITS(AD16C4T_CHMR2_INPUT_CC4SSEL_POSS,AD16C4T_CHMR2_INPUT_CC4SSEL_POSE) - -#define AD16C4T_CHMR2_INPUT_I3FLT_POSS 4U -#define AD16C4T_CHMR2_INPUT_I3FLT_POSE 7U -#define AD16C4T_CHMR2_INPUT_I3FLT_MSK BITS(AD16C4T_CHMR2_INPUT_I3FLT_POSS,AD16C4T_CHMR2_INPUT_I3FLT_POSE) - -#define AD16C4T_CHMR2_INPUT_I3PRES_POSS 2U -#define AD16C4T_CHMR2_INPUT_I3PRES_POSE 3U -#define AD16C4T_CHMR2_INPUT_I3PRES_MSK BITS(AD16C4T_CHMR2_INPUT_I3PRES_POSS,AD16C4T_CHMR2_INPUT_I3PRES_POSE) - -#define AD16C4T_CHMR2_INPUT_CC3SSEL_POSS 0U -#define AD16C4T_CHMR2_INPUT_CC3SSEL_POSE 1U -#define AD16C4T_CHMR2_INPUT_CC3SSEL_MSK BITS(AD16C4T_CHMR2_INPUT_CC3SSEL_POSS,AD16C4T_CHMR2_INPUT_CC3SSEL_POSE) - -/****************** Bit definition for AD16C4T_CCEP register ************************/ - -#define AD16C4T_CCEP_CC4NPOL_POS 15U -#define AD16C4T_CCEP_CC4NPOL_MSK BIT(AD16C4T_CCEP_CC4NPOL_POS) - -#define AD16C4T_CCEP_CC4POL_POS 13U -#define AD16C4T_CCEP_CC4POL_MSK BIT(AD16C4T_CCEP_CC4POL_POS) - -#define AD16C4T_CCEP_CC4EN_POS 12U -#define AD16C4T_CCEP_CC4EN_MSK BIT(AD16C4T_CCEP_CC4EN_POS) - -#define AD16C4T_CCEP_CC3NPOL_POS 11U -#define AD16C4T_CCEP_CC3NPOL_MSK BIT(AD16C4T_CCEP_CC3NPOL_POS) - -#define AD16C4T_CCEP_CC3NEN_POS 10U -#define AD16C4T_CCEP_CC3NEN_MSK BIT(AD16C4T_CCEP_CC3NEN_POS) - -#define AD16C4T_CCEP_CC3POL_POS 9U -#define AD16C4T_CCEP_CC3POL_MSK BIT(AD16C4T_CCEP_CC3POL_POS) - -#define AD16C4T_CCEP_CC3EN_POS 8U -#define AD16C4T_CCEP_CC3EN_MSK BIT(AD16C4T_CCEP_CC3EN_POS) - -#define AD16C4T_CCEP_CC2NPOL_POS 7U -#define AD16C4T_CCEP_CC2NPOL_MSK BIT(AD16C4T_CCEP_CC2NPOL_POS) - -#define AD16C4T_CCEP_CC2NEN_POS 6U -#define AD16C4T_CCEP_CC2NEN_MSK BIT(AD16C4T_CCEP_CC2NEN_POS) - -#define AD16C4T_CCEP_CC2POL_POS 5U -#define AD16C4T_CCEP_CC2POL_MSK BIT(AD16C4T_CCEP_CC2POL_POS) - -#define AD16C4T_CCEP_CC2EN_POS 4U -#define AD16C4T_CCEP_CC2EN_MSK BIT(AD16C4T_CCEP_CC2EN_POS) - -#define AD16C4T_CCEP_CC1NPOL_POS 3U -#define AD16C4T_CCEP_CC1NPOL_MSK BIT(AD16C4T_CCEP_CC1NPOL_POS) - -#define AD16C4T_CCEP_CC1NEN_POS 2U -#define AD16C4T_CCEP_CC1NEN_MSK BIT(AD16C4T_CCEP_CC1NEN_POS) - -#define AD16C4T_CCEP_CC1POL_POS 1U -#define AD16C4T_CCEP_CC1POL_MSK BIT(AD16C4T_CCEP_CC1POL_POS) - -#define AD16C4T_CCEP_CC1EN_POS 0U -#define AD16C4T_CCEP_CC1EN_MSK BIT(AD16C4T_CCEP_CC1EN_POS) - -/****************** Bit definition for AD16C4T_COUNT register ************************/ - -#define AD16C4T_COUNT_CNTV_POSS 0U -#define AD16C4T_COUNT_CNTV_POSE 15U -#define AD16C4T_COUNT_CNTV_MSK BITS(AD16C4T_COUNT_CNTV_POSS,AD16C4T_COUNT_CNTV_POSE) - -/****************** Bit definition for AD16C4T_PRES register ************************/ - -#define AD16C4T_PRES_PSCV_POSS 0U -#define AD16C4T_PRES_PSCV_POSE 15U -#define AD16C4T_PRES_PSCV_MSK BITS(AD16C4T_PRES_PSCV_POSS,AD16C4T_PRES_PSCV_POSE) - -/****************** Bit definition for AD16C4T_AR register ************************/ - -#define AD16C4T_AR_ARV_POSS 0U -#define AD16C4T_AR_ARV_POSE 15U -#define AD16C4T_AR_ARV_MSK BITS(AD16C4T_AR_ARV_POSS,AD16C4T_AR_ARV_POSE) - -/****************** Bit definition for AD16C4T_REPAR register ************************/ - -#define AD16C4T_REPAR_REPV_POSS 0U -#define AD16C4T_REPAR_REPV_POSE 7U -#define AD16C4T_REPAR_REPV_MSK BITS(AD16C4T_REPAR_REPV_POSS,AD16C4T_REPAR_REPV_POSE) - -/****************** Bit definition for AD16C4T_CCVAL1 register ************************/ - -#define AD16C4T_CCVAL1_CCRV1_POSS 0U -#define AD16C4T_CCVAL1_CCRV1_POSE 15U -#define AD16C4T_CCVAL1_CCRV1_MSK BITS(AD16C4T_CCVAL1_CCRV1_POSS,AD16C4T_CCVAL1_CCRV1_POSE) - -/****************** Bit definition for AD16C4T_CCVAL2 register ************************/ - -#define AD16C4T_CCVAL2_CCRV2_POSS 0U -#define AD16C4T_CCVAL2_CCRV2_POSE 15U -#define AD16C4T_CCVAL2_CCRV2_MSK BITS(AD16C4T_CCVAL2_CCRV2_POSS,AD16C4T_CCVAL2_CCRV2_POSE) - -/****************** Bit definition for AD16C4T_CCVAL3 register ************************/ - -#define AD16C4T_CCVAL3_CCRV3_POSS 0U -#define AD16C4T_CCVAL3_CCRV3_POSE 15U -#define AD16C4T_CCVAL3_CCRV3_MSK BITS(AD16C4T_CCVAL3_CCRV3_POSS,AD16C4T_CCVAL3_CCRV3_POSE) - -/****************** Bit definition for AD16C4T_CCVAL4 register ************************/ - -#define AD16C4T_CCVAL4_CCRV4_POSS 0U -#define AD16C4T_CCVAL4_CCRV4_POSE 15U -#define AD16C4T_CCVAL4_CCRV4_MSK BITS(AD16C4T_CCVAL4_CCRV4_POSS,AD16C4T_CCVAL4_CCRV4_POSE) - -/****************** Bit definition for AD16C4T_BDCFG register ************************/ - -#define AD16C4T_BDCFG_GOEN_POS 15U -#define AD16C4T_BDCFG_GOEN_MSK BIT(AD16C4T_BDCFG_GOEN_POS) - -#define AD16C4T_BDCFG_AOEN_POS 14U -#define AD16C4T_BDCFG_AOEN_MSK BIT(AD16C4T_BDCFG_AOEN_POS) - -#define AD16C4T_BDCFG_BRKP_POS 13U -#define AD16C4T_BDCFG_BRKP_MSK BIT(AD16C4T_BDCFG_BRKP_POS) - -#define AD16C4T_BDCFG_BRKEN_POS 12U -#define AD16C4T_BDCFG_BRKEN_MSK BIT(AD16C4T_BDCFG_BRKEN_POS) - -#define AD16C4T_BDCFG_OFFSSR_POS 11U -#define AD16C4T_BDCFG_OFFSSR_MSK BIT(AD16C4T_BDCFG_OFFSSR_POS) - -#define AD16C4T_BDCFG_OFFSSI_POS 10U -#define AD16C4T_BDCFG_OFFSSI_MSK BIT(AD16C4T_BDCFG_OFFSSI_POS) - -#define AD16C4T_BDCFG_LOCKLVL_POSS 8U -#define AD16C4T_BDCFG_LOCKLVL_POSE 9U -#define AD16C4T_BDCFG_LOCKLVL_MSK BITS(AD16C4T_BDCFG_LOCKLVL_POSS,AD16C4T_BDCFG_LOCKLVL_POSE) - -#define AD16C4T_BDCFG_DT_POSS 0U -#define AD16C4T_BDCFG_DT_POSE 7U -#define AD16C4T_BDCFG_DT_MSK BITS(AD16C4T_BDCFG_DT_POSS,AD16C4T_BDCFG_DT_POSE) - -/****************** Bit definition for AD16C4T_DMAEN register ************************/ - -#define AD16C4T_DMAEN_TRGIDE_POS 6U -#define AD16C4T_DMAEN_TRGIDE_MSK BIT(AD16C4T_DMAEN_TRGIDE_POS) - -#define AD16C4T_DMAEN_COMDE_POS 5U -#define AD16C4T_DMAEN_COMDE_MSK BIT(AD16C4T_DMAEN_COMDE_POS) - -#define AD16C4T_DMAEN_CH4DE_POS 4U -#define AD16C4T_DMAEN_CH4DE_MSK BIT(AD16C4T_DMAEN_CH4DE_POS) - -#define AD16C4T_DMAEN_CH3DE_POS 3U -#define AD16C4T_DMAEN_CH3DE_MSK BIT(AD16C4T_DMAEN_CH3DE_POS) - -#define AD16C4T_DMAEN_CH2DE_POS 2U -#define AD16C4T_DMAEN_CH2DE_MSK BIT(AD16C4T_DMAEN_CH2DE_POS) - -#define AD16C4T_DMAEN_CH1DE_POS 1U -#define AD16C4T_DMAEN_CH1DE_MSK BIT(AD16C4T_DMAEN_CH1DE_POS) - -#define AD16C4T_DMAEN_UDE_POS 0U -#define AD16C4T_DMAEN_UDE_MSK BIT(AD16C4T_DMAEN_UDE_POS) - -typedef struct -{ - __IO uint32_t CON1; /* 0x000 AD16C4T_CON1 Control register 1 */ - __IO uint32_t CON2; /* 0x004 AD16C4T_CON2 Control register 2 */ - __IO uint32_t SMCON; /* 0x008 AD16C4T_SMCON Slave mode control register */ - __O uint32_t IER; /* 0x00C AD16C4T_IER Interrupt Enable register */ - __O uint32_t IDR; /* 0x010 AD16C4T_IDR Interrupt Disable register */ - __I uint32_t IVS; /* 0x014 AD16C4T_IVS Interrupt Valid status register */ - __I uint32_t RIF; /* 0x018 AD16C4T_RIF Interrupt Raw interrupt Flag */ - __I uint32_t IFM; /* 0x01C AD16C4T_IFM Interrupt Masked interrupt Flag */ - __O uint32_t ICR; /* 0x020 AD16C4T_ICR Interrupt Clear status register */ - __O uint32_t SGE; /* 0x024 AD16C4T_SGE Event generation register */ - __IO uint32_t CHMR1; /* 0x028 AD16C4T_CHMR1 Capture/compare mode register 1 */ - __IO uint32_t CHMR2; /* 0x02C AD16C4T_CHMR2 Capture/compare mode register 2 */ - __IO uint32_t CCEP; /* 0x030 AD16C4T_CCEP Capture/compare enable register */ - __IO uint32_t COUNT; /* 0x034 AD16C4T_COUNT Timer Counter */ - __IO uint32_t PRES; /* 0x038 AD16C4T_PRES Prescaler */ - __IO uint32_t AR; /* 0x03C AD16C4T_AR Auto-reload register */ - __IO uint32_t REPAR; /* 0x040 AD16C4T_REPAR Repetition counter register */ - __IO uint32_t CCVAL1; /* 0x044 AD16C4T_CCVAL1 Capture/compare register 1 */ - __IO uint32_t CCVAL2; /* 0x048 AD16C4T_CCVAL2 Capture/compare register 2 */ - __IO uint32_t CCVAL3; /* 0x04C AD16C4T_CCVAL3 Capture/compare register 3 */ - __IO uint32_t CCVAL4; /* 0x050 AD16C4T_CCVAL4 Capture/compare register 4 */ - __IO uint32_t BDCFG; /* 0x054 AD16C4T_BDCFG Break and dead-time register */ - __IO uint32_t DMAEN; /* 0x058 AD16C4T_DMAEN DMA trigger event enable */ -} AD16C4T_TypeDef; - -#endif -/******************* (C) COPYRIGHT Eastsoft Microelectronics END OF REG_AD16C4T.H****/ - diff --git a/bsp/essemi/es32f0271/libraries/CMSIS/Device/EastSoft/ES32F0271/Include/ES32F0271/reg_adc.h b/bsp/essemi/es32f0271/libraries/CMSIS/Device/EastSoft/ES32F0271/Include/ES32F0271/reg_adc.h deleted file mode 100644 index e1b57e2773..0000000000 --- a/bsp/essemi/es32f0271/libraries/CMSIS/Device/EastSoft/ES32F0271/Include/ES32F0271/reg_adc.h +++ /dev/null @@ -1,795 +0,0 @@ -/** - ************************************************************************************** - * @file REG_ADC.h - * @brief ADC Header File - * - * @version V1.00.01 - * @date 04/12/2018 - * @author Eastsoft MCU Software Team - * @note - * - * Copyright (C) 2018 Shanghai Eastsoft Microelectronics Co., Ltd. ALL rights reserved. - * - ************************************************************************************** - */ - -#ifndef __ADC_H__ -#define __ADC_H__ - - -/******************************************************************************/ -/* 设备特殊寄存器结构定义 */ -/******************************************************************************/ - -/* 允许匿名结构和匿名联合 */ -/* #pragma anon_unions */ - -/****************** Bit definition for ADC_CFG register ************************/ - -#define ADC_CFG_TESTEN_POSS 8U -#define ADC_CFG_TESTEN_POSE 15U -#define ADC_CFG_TESTEN_MSK BITS(ADC_CFG_TESTEN_POSS,ADC_CFG_TESTEN_POSE) - -#define ADC_CFG_MODE_POS 0U -#define ADC_CFG_MODE_MSK BIT(ADC_CFG_MODE_POS) - -/****************** Bit definition for ADC_SRATE register ************************/ - -#define ADC_SRATE_CNT_POSS 16U -#define ADC_SRATE_CNT_POSE 23U -#define ADC_SRATE_CNT_MSK BITS(ADC_SRATE_CNT_POSS,ADC_SRATE_CNT_POSE) - -#define ADC_SRATE_CNTINI_POSS 8U -#define ADC_SRATE_CNTINI_POSE 15U -#define ADC_SRATE_CNTINI_MSK BITS(ADC_SRATE_CNTINI_POSS,ADC_SRATE_CNTINI_POSE) - -#define ADC_SRATE_CKDIV_POSS 1U -#define ADC_SRATE_CKDIV_POSE 4U -#define ADC_SRATE_CKDIV_MSK BITS(ADC_SRATE_CKDIV_POSS,ADC_SRATE_CKDIV_POSE) - -#define ADC_SRATE_CKEN_POS 0U -#define ADC_SRATE_CKEN_MSK BIT(ADC_SRATE_CKEN_POS) - -/****************** Bit definition for ADC_CHINV register ************************/ - -#define ADC_CHINV_CH15INV_POS 15U -#define ADC_CHINV_CH15INV_MSK BIT(ADC_CHINV_CH15INV_POS) - -#define ADC_CHINV_CH14INV_POS 14U -#define ADC_CHINV_CH14INV_MSK BIT(ADC_CHINV_CH14INV_POS) - -#define ADC_CHINV_CH13INV_POS 13U -#define ADC_CHINV_CH13INV_MSK BIT(ADC_CHINV_CH13INV_POS) - -#define ADC_CHINV_CH12INV_POS 12U -#define ADC_CHINV_CH12INV_MSK BIT(ADC_CHINV_CH12INV_POS) - -#define ADC_CHINV_CH11INV_POS 11U -#define ADC_CHINV_CH11INV_MSK BIT(ADC_CHINV_CH11INV_POS) - -#define ADC_CHINV_CH10INV_POS 10U -#define ADC_CHINV_CH10INV_MSK BIT(ADC_CHINV_CH10INV_POS) - -#define ADC_CHINV_CH9INV_POS 9U -#define ADC_CHINV_CH9INV_MSK BIT(ADC_CHINV_CH9INV_POS) - -#define ADC_CHINV_CH8INV_POS 8U -#define ADC_CHINV_CH8INV_MSK BIT(ADC_CHINV_CH8INV_POS) - -#define ADC_CHINV_CH7INV_POS 7U -#define ADC_CHINV_CH7INV_MSK BIT(ADC_CHINV_CH7INV_POS) - -#define ADC_CHINV_CH6INV_POS 6U -#define ADC_CHINV_CH6INV_MSK BIT(ADC_CHINV_CH6INV_POS) - -#define ADC_CHINV_CH5INV_POS 5U -#define ADC_CHINV_CH5INV_MSK BIT(ADC_CHINV_CH5INV_POS) - -#define ADC_CHINV_CH4INV_POS 4U -#define ADC_CHINV_CH4INV_MSK BIT(ADC_CHINV_CH4INV_POS) - -#define ADC_CHINV_CH3INV_POS 3U -#define ADC_CHINV_CH3INV_MSK BIT(ADC_CHINV_CH3INV_POS) - -#define ADC_CHINV_CH2INV_POS 2U -#define ADC_CHINV_CH2INV_MSK BIT(ADC_CHINV_CH2INV_POS) - -#define ADC_CHINV_CH1INV_POS 1U -#define ADC_CHINV_CH1INV_MSK BIT(ADC_CHINV_CH1INV_POS) - -#define ADC_CHINV_CH0INV_POS 0U -#define ADC_CHINV_CH0INV_MSK BIT(ADC_CHINV_CH0INV_POS) - -/****************** Bit definition for ADC_GAINL register ************************/ - -#define ADC_GAINL_CH7PGA_POSS 21U -#define ADC_GAINL_CH7PGA_POSE 23U -#define ADC_GAINL_CH7PGA_MSK BITS(ADC_GAINL_CH7PGA_POSS,ADC_GAINL_CH7PGA_POSE) - -#define ADC_GAINL_CH6PGA_POSS 18U -#define ADC_GAINL_CH6PGA_POSE 20U -#define ADC_GAINL_CH6PGA_MSK BITS(ADC_GAINL_CH6PGA_POSS,ADC_GAINL_CH6PGA_POSE) - -#define ADC_GAINL_CH5PGA_POSS 15U -#define ADC_GAINL_CH5PGA_POSE 17U -#define ADC_GAINL_CH5PGA_MSK BITS(ADC_GAINL_CH5PGA_POSS,ADC_GAINL_CH5PGA_POSE) - -#define ADC_GAINL_CH4PGA_POSS 12U -#define ADC_GAINL_CH4PGA_POSE 14U -#define ADC_GAINL_CH4PGA_MSK BITS(ADC_GAINL_CH4PGA_POSS,ADC_GAINL_CH4PGA_POSE) - -#define ADC_GAINL_CH3PGA_POSS 9U -#define ADC_GAINL_CH3PGA_POSE 11U -#define ADC_GAINL_CH3PGA_MSK BITS(ADC_GAINL_CH3PGA_POSS,ADC_GAINL_CH3PGA_POSE) - -#define ADC_GAINL_CH2PGA_POSS 6U -#define ADC_GAINL_CH2PGA_POSE 8U -#define ADC_GAINL_CH2PGA_MSK BITS(ADC_GAINL_CH2PGA_POSS,ADC_GAINL_CH2PGA_POSE) - -#define ADC_GAINL_CH1PGA_POSS 3U -#define ADC_GAINL_CH1PGA_POSE 5U -#define ADC_GAINL_CH1PGA_MSK BITS(ADC_GAINL_CH1PGA_POSS,ADC_GAINL_CH1PGA_POSE) - -#define ADC_GAINL_CH0PGA_POSS 0U -#define ADC_GAINL_CH0PGA_POSE 2U -#define ADC_GAINL_CH0PGA_MSK BITS(ADC_GAINL_CH0PGA_POSS,ADC_GAINL_CH0PGA_POSE) - -/****************** Bit definition for ADC_GAINH register ************************/ - -#define ADC_GAINH_CH15PGA_POSS 21U -#define ADC_GAINH_CH15PGA_POSE 23U -#define ADC_GAINH_CH15PGA_MSK BITS(ADC_GAINH_CH15PGA_POSS,ADC_GAINH_CH15PGA_POSE) - -#define ADC_GAINH_CH14PGA_POSS 18U -#define ADC_GAINH_CH14PGA_POSE 20U -#define ADC_GAINH_CH14PGA_MSK BITS(ADC_GAINH_CH14PGA_POSS,ADC_GAINH_CH14PGA_POSE) - -#define ADC_GAINH_CH13PGA_POSS 15U -#define ADC_GAINH_CH13PGA_POSE 17U -#define ADC_GAINH_CH13PGA_MSK BITS(ADC_GAINH_CH13PGA_POSS,ADC_GAINH_CH13PGA_POSE) - -#define ADC_GAINH_CH12PGA_POSS 12U -#define ADC_GAINH_CH12PGA_POSE 14U -#define ADC_GAINH_CH12PGA_MSK BITS(ADC_GAINH_CH12PGA_POSS,ADC_GAINH_CH12PGA_POSE) - -#define ADC_GAINH_CH11PGA_POSS 9U -#define ADC_GAINH_CH11PGA_POSE 11U -#define ADC_GAINH_CH11PGA_MSK BITS(ADC_GAINH_CH11PGA_POSS,ADC_GAINH_CH11PGA_POSE) - -#define ADC_GAINH_CH10PGA_POSS 6U -#define ADC_GAINH_CH10PGA_POSE 8U -#define ADC_GAINH_CH10PGA_MSK BITS(ADC_GAINH_CH10PGA_POSS,ADC_GAINH_CH10PGA_POSE) - -#define ADC_GAINH_CH9PGA_POSS 3U -#define ADC_GAINH_CH9PGA_POSE 5U -#define ADC_GAINH_CH9PGA_MSK BITS(ADC_GAINH_CH9PGA_POSS,ADC_GAINH_CH9PGA_POSE) - -#define ADC_GAINH_CH8PGA_POSS 0U -#define ADC_GAINH_CH8PGA_POSE 2U -#define ADC_GAINH_CH8PGA_MSK BITS(ADC_GAINH_CH8PGA_POSS,ADC_GAINH_CH8PGA_POSE) - -/****************** Bit definition for ADC_FRF register ************************/ - -#define ADC_FRF_FFRST_POS 4U -#define ADC_FRF_FFRST_MSK BIT(ADC_FRF_FFRST_POS) - -#define ADC_FRF_SS3RF_POS 3U -#define ADC_FRF_SS3RF_MSK BIT(ADC_FRF_SS3RF_POS) - -#define ADC_FRF_SS2RF_POS 2U -#define ADC_FRF_SS2RF_MSK BIT(ADC_FRF_SS2RF_POS) - -#define ADC_FRF_SS1RF_POS 1U -#define ADC_FRF_SS1RF_MSK BIT(ADC_FRF_SS1RF_POS) - -#define ADC_FRF_SS0RF_POS 0U -#define ADC_FRF_SS0RF_MSK BIT(ADC_FRF_SS0RF_POS) - -/****************** Bit definition for ADC_SSEN register ************************/ - -#define ADC_SSEN_IDLE_POS 4U -#define ADC_SSEN_IDLE_MSK BIT(ADC_SSEN_IDLE_POS) - -#define ADC_SSEN_SS3EN_POS 3U -#define ADC_SSEN_SS3EN_MSK BIT(ADC_SSEN_SS3EN_POS) - -#define ADC_SSEN_SS2EN_POS 2U -#define ADC_SSEN_SS2EN_MSK BIT(ADC_SSEN_SS2EN_POS) - -#define ADC_SSEN_SS1EN_POS 1U -#define ADC_SSEN_SS1EN_MSK BIT(ADC_SSEN_SS1EN_POS) - -#define ADC_SSEN_SS0EN_POS 0U -#define ADC_SSEN_SS0EN_MSK BIT(ADC_SSEN_SS0EN_POS) - -/****************** Bit definition for ADC_SWTRI register ************************/ - -#define ADC_SWTRI_SS3_POS 3U -#define ADC_SWTRI_SS3_MSK BIT(ADC_SWTRI_SS3_POS) - -#define ADC_SWTRI_SS2_POS 2U -#define ADC_SWTRI_SS2_MSK BIT(ADC_SWTRI_SS2_POS) - -#define ADC_SWTRI_SS1_POS 1U -#define ADC_SWTRI_SS1_MSK BIT(ADC_SWTRI_SS1_POS) - -#define ADC_SWTRI_SS0_POS 0U -#define ADC_SWTRI_SS0_MSK BIT(ADC_SWTRI_SS0_POS) - -/****************** Bit definition for ADC_IER register ************************/ - -#define ADC_IER_TOIE_POS 4U -#define ADC_IER_TOIE_MSK BIT(ADC_IER_TOIE_POS) - -#define ADC_IER_SS3IE_POS 3U -#define ADC_IER_SS3IE_MSK BIT(ADC_IER_SS3IE_POS) - -#define ADC_IER_SS2IE_POS 2U -#define ADC_IER_SS2IE_MSK BIT(ADC_IER_SS2IE_POS) - -#define ADC_IER_SS1IE_POS 1U -#define ADC_IER_SS1IE_MSK BIT(ADC_IER_SS1IE_POS) - -#define ADC_IER_SS0IE_POS 0U -#define ADC_IER_SS0IE_MSK BIT(ADC_IER_SS0IE_POS) - -/****************** Bit definition for ADC_IDR register ************************/ - -#define ADC_IDR_TOID_POS 4U -#define ADC_IDR_TOID_MSK BIT(ADC_IDR_TOID_POS) - -#define ADC_IDR_SS3ID_POS 3U -#define ADC_IDR_SS3ID_MSK BIT(ADC_IDR_SS3ID_POS) - -#define ADC_IDR_SS2ID_POS 2U -#define ADC_IDR_SS2ID_MSK BIT(ADC_IDR_SS2ID_POS) - -#define ADC_IDR_SS1ID_POS 1U -#define ADC_IDR_SS1ID_MSK BIT(ADC_IDR_SS1ID_POS) - -#define ADC_IDR_SS0ID_POS 0U -#define ADC_IDR_SS0ID_MSK BIT(ADC_IDR_SS0ID_POS) - -/****************** Bit definition for ADC_IVS register ************************/ - -#define ADC_IVS_TOIVS_POS 4U -#define ADC_IVS_TOIVS_MSK BIT(ADC_IVS_TOIVS_POS) - -#define ADC_IVS_SS3IVS_POS 3U -#define ADC_IVS_SS3IVS_MSK BIT(ADC_IVS_SS3IVS_POS) - -#define ADC_IVS_SS2IVS_POS 2U -#define ADC_IVS_SS2IVS_MSK BIT(ADC_IVS_SS2IVS_POS) - -#define ADC_IVS_SS1IVS_POS 1U -#define ADC_IVS_SS1IVS_MSK BIT(ADC_IVS_SS1IVS_POS) - -#define ADC_IVS_SS0IVS_POS 0U -#define ADC_IVS_SS0IVS_MSK BIT(ADC_IVS_SS0IVS_POS) - -/****************** Bit definition for ADC_RIF register ************************/ - -#define ADC_RIF_TORIF_POS 4U -#define ADC_RIF_TORIF_MSK BIT(ADC_RIF_TORIF_POS) - -#define ADC_RIF_SS3RIF_POS 3U -#define ADC_RIF_SS3RIF_MSK BIT(ADC_RIF_SS3RIF_POS) - -#define ADC_RIF_SS2RIF_POS 2U -#define ADC_RIF_SS2RIF_MSK BIT(ADC_RIF_SS2RIF_POS) - -#define ADC_RIF_SS1RIF_POS 1U -#define ADC_RIF_SS1RIF_MSK BIT(ADC_RIF_SS1RIF_POS) - -#define ADC_RIF_SS0RIF_POS 0U -#define ADC_RIF_SS0RIF_MSK BIT(ADC_RIF_SS0RIF_POS) - -/****************** Bit definition for ADC_IFM register ************************/ - -#define ADC_IFM_TOIFM_POS 4U -#define ADC_IFM_TOIFM_MSK BIT(ADC_IFM_TOIFM_POS) - -#define ADC_IFM_SS3IFM_POS 3U -#define ADC_IFM_SS3IFM_MSK BIT(ADC_IFM_SS3IFM_POS) - -#define ADC_IFM_SS2IFM_POS 2U -#define ADC_IFM_SS2IFM_MSK BIT(ADC_IFM_SS2IFM_POS) - -#define ADC_IFM_SS1IFM_POS 1U -#define ADC_IFM_SS1IFM_MSK BIT(ADC_IFM_SS1IFM_POS) - -#define ADC_IFM_SS0IFM_POS 0U -#define ADC_IFM_SS0IFM_MSK BIT(ADC_IFM_SS0IFM_POS) - -/****************** Bit definition for ADC_ICR register ************************/ - -#define ADC_ICR_TOICR_POS 4U -#define ADC_ICR_TOICR_MSK BIT(ADC_ICR_TOICR_POS) - -#define ADC_ICR_SS3ICR_POS 3U -#define ADC_ICR_SS3ICR_MSK BIT(ADC_ICR_SS3ICR_POS) - -#define ADC_ICR_SS2ICR_POS 2U -#define ADC_ICR_SS2ICR_MSK BIT(ADC_ICR_SS2ICR_POS) - -#define ADC_ICR_SS1ICR_POS 1U -#define ADC_ICR_SS1ICR_MSK BIT(ADC_ICR_SS1ICR_POS) - -#define ADC_ICR_SS0ICR_POS 0U -#define ADC_ICR_SS0ICR_MSK BIT(ADC_ICR_SS0ICR_POS) - -/****************** Bit definition for ADC_DMA register ************************/ - -#define ADC_DMA_SS3_DMAEN_POS 3U -#define ADC_DMA_SS3_DMAEN_MSK BIT(ADC_DMA_SS3_DMAEN_POS) - -#define ADC_DMA_SS2_DMAEN_POS 2U -#define ADC_DMA_SS2_DMAEN_MSK BIT(ADC_DMA_SS2_DMAEN_POS) - -#define ADC_DMA_SS1_DMAEN_POS 1U -#define ADC_DMA_SS1_DMAEN_MSK BIT(ADC_DMA_SS1_DMAEN_POS) - -#define ADC_DMA_SS0_DMAEN_POS 0U -#define ADC_DMA_SS0_DMAEN_MSK BIT(ADC_DMA_SS0_DMAEN_POS) - -/****************** Bit definition for ADC_SS0_CON register ************************/ - -#define ADC_SS0_CON_SEL_POSS 11U -#define ADC_SS0_CON_SEL_POSE 15U -#define ADC_SS0_CON_SEL_MSK BITS(ADC_SS0_CON_SEL_POSS,ADC_SS0_CON_SEL_POSE) - -#define ADC_SS0_CON_TYP_POS 8U -#define ADC_SS0_CON_TYP_MSK BIT(ADC_SS0_CON_TYP_POS) - -#define ADC_SS0_CON_PRI_POSS 4U -#define ADC_SS0_CON_PRI_POSE 5U -#define ADC_SS0_CON_PRI_MSK BITS(ADC_SS0_CON_PRI_POSS,ADC_SS0_CON_PRI_POSE) - -#define ADC_SS0_CON_ONE_POS 0U -#define ADC_SS0_CON_ONE_MSK BIT(ADC_SS0_CON_ONE_POS) - -/****************** Bit definition for ADC_SS0_MUX0 register ************************/ - -#define ADC_SS0_MUX0_MUX7_POSS 28U -#define ADC_SS0_MUX0_MUX7_POSE 31U -#define ADC_SS0_MUX0_MUX7_MSK BITS(ADC_SS0_MUX0_MUX7_POSS,ADC_SS0_MUX0_MUX7_POSE) - -#define ADC_SS0_MUX0_MUX6_POSS 24U -#define ADC_SS0_MUX0_MUX6_POSE 27U -#define ADC_SS0_MUX0_MUX6_MSK BITS(ADC_SS0_MUX0_MUX6_POSS,ADC_SS0_MUX0_MUX6_POSE) - -#define ADC_SS0_MUX0_MUX5_POSS 20U -#define ADC_SS0_MUX0_MUX5_POSE 23U -#define ADC_SS0_MUX0_MUX5_MSK BITS(ADC_SS0_MUX0_MUX5_POSS,ADC_SS0_MUX0_MUX5_POSE) - -#define ADC_SS0_MUX0_MUX4_POSS 16U -#define ADC_SS0_MUX0_MUX4_POSE 19U -#define ADC_SS0_MUX0_MUX4_MSK BITS(ADC_SS0_MUX0_MUX4_POSS,ADC_SS0_MUX0_MUX4_POSE) - -#define ADC_SS0_MUX0_MUX3_POSS 12U -#define ADC_SS0_MUX0_MUX3_POSE 15U -#define ADC_SS0_MUX0_MUX3_MSK BITS(ADC_SS0_MUX0_MUX3_POSS,ADC_SS0_MUX0_MUX3_POSE) - -#define ADC_SS0_MUX0_MUX2_POSS 8U -#define ADC_SS0_MUX0_MUX2_POSE 11U -#define ADC_SS0_MUX0_MUX2_MSK BITS(ADC_SS0_MUX0_MUX2_POSS,ADC_SS0_MUX0_MUX2_POSE) - -#define ADC_SS0_MUX0_MUX1_POSS 4U -#define ADC_SS0_MUX0_MUX1_POSE 7U -#define ADC_SS0_MUX0_MUX1_MSK BITS(ADC_SS0_MUX0_MUX1_POSS,ADC_SS0_MUX0_MUX1_POSE) - -#define ADC_SS0_MUX0_MUX0_POSS 0U -#define ADC_SS0_MUX0_MUX0_POSE 3U -#define ADC_SS0_MUX0_MUX0_MSK BITS(ADC_SS0_MUX0_MUX0_POSS,ADC_SS0_MUX0_MUX0_POSE) - -/****************** Bit definition for ADC_SS0_MUX1 register ************************/ - -#define ADC_SS0_MUX1_MUX15_POSS 28U -#define ADC_SS0_MUX1_MUX15_POSE 31U -#define ADC_SS0_MUX1_MUX15_MSK BITS(ADC_SS0_MUX1_MUX15_POSS,ADC_SS0_MUX1_MUX15_POSE) - -#define ADC_SS0_MUX1_MUX14_POSS 24U -#define ADC_SS0_MUX1_MUX14_POSE 27U -#define ADC_SS0_MUX1_MUX14_MSK BITS(ADC_SS0_MUX1_MUX14_POSS,ADC_SS0_MUX1_MUX14_POSE) - -#define ADC_SS0_MUX1_MUX13_POSS 20U -#define ADC_SS0_MUX1_MUX13_POSE 23U -#define ADC_SS0_MUX1_MUX13_MSK BITS(ADC_SS0_MUX1_MUX13_POSS,ADC_SS0_MUX1_MUX13_POSE) - -#define ADC_SS0_MUX1_MUX12_POSS 16U -#define ADC_SS0_MUX1_MUX12_POSE 19U -#define ADC_SS0_MUX1_MUX12_MSK BITS(ADC_SS0_MUX1_MUX12_POSS,ADC_SS0_MUX1_MUX12_POSE) - -#define ADC_SS0_MUX1_MUX11_POSS 12U -#define ADC_SS0_MUX1_MUX11_POSE 15U -#define ADC_SS0_MUX1_MUX11_MSK BITS(ADC_SS0_MUX1_MUX11_POSS,ADC_SS0_MUX1_MUX11_POSE) - -#define ADC_SS0_MUX1_MUX10_POSS 8U -#define ADC_SS0_MUX1_MUX10_POSE 11U -#define ADC_SS0_MUX1_MUX10_MSK BITS(ADC_SS0_MUX1_MUX10_POSS,ADC_SS0_MUX1_MUX10_POSE) - -#define ADC_SS0_MUX1_MUX9_POSS 4U -#define ADC_SS0_MUX1_MUX9_POSE 7U -#define ADC_SS0_MUX1_MUX9_MSK BITS(ADC_SS0_MUX1_MUX9_POSS,ADC_SS0_MUX1_MUX9_POSE) - -#define ADC_SS0_MUX1_MUX8_POSS 0U -#define ADC_SS0_MUX1_MUX8_POSE 3U -#define ADC_SS0_MUX1_MUX8_MSK BITS(ADC_SS0_MUX1_MUX8_POSS,ADC_SS0_MUX1_MUX8_POSE) - -/****************** Bit definition for ADC_SS0_END register ************************/ - -#define ADC_SS0_END_IE15_POS 23U -#define ADC_SS0_END_IE15_MSK BIT(ADC_SS0_END_IE15_POS) - -#define ADC_SS0_END_IE14_POS 22U -#define ADC_SS0_END_IE14_MSK BIT(ADC_SS0_END_IE14_POS) - -#define ADC_SS0_END_IE13_POS 21U -#define ADC_SS0_END_IE13_MSK BIT(ADC_SS0_END_IE13_POS) - -#define ADC_SS0_END_IE12_POS 20U -#define ADC_SS0_END_IE12_MSK BIT(ADC_SS0_END_IE12_POS) - -#define ADC_SS0_END_IE11_POS 19U -#define ADC_SS0_END_IE11_MSK BIT(ADC_SS0_END_IE11_POS) - -#define ADC_SS0_END_IE10_POS 18U -#define ADC_SS0_END_IE10_MSK BIT(ADC_SS0_END_IE10_POS) - -#define ADC_SS0_END_IE9_POS 17U -#define ADC_SS0_END_IE9_MSK BIT(ADC_SS0_END_IE9_POS) - -#define ADC_SS0_END_IE8_POS 16U -#define ADC_SS0_END_IE8_MSK BIT(ADC_SS0_END_IE8_POS) - -#define ADC_SS0_END_IE7_POS 15U -#define ADC_SS0_END_IE7_MSK BIT(ADC_SS0_END_IE7_POS) - -#define ADC_SS0_END_IE6_POS 14U -#define ADC_SS0_END_IE6_MSK BIT(ADC_SS0_END_IE6_POS) - -#define ADC_SS0_END_IE5_POS 13U -#define ADC_SS0_END_IE5_MSK BIT(ADC_SS0_END_IE5_POS) - -#define ADC_SS0_END_IE4_POS 12U -#define ADC_SS0_END_IE4_MSK BIT(ADC_SS0_END_IE4_POS) - -#define ADC_SS0_END_IE3_POS 11U -#define ADC_SS0_END_IE3_MSK BIT(ADC_SS0_END_IE3_POS) - -#define ADC_SS0_END_IE2_POS 10U -#define ADC_SS0_END_IE2_MSK BIT(ADC_SS0_END_IE2_POS) - -#define ADC_SS0_END_IE1_POS 9U -#define ADC_SS0_END_IE1_MSK BIT(ADC_SS0_END_IE1_POS) - -#define ADC_SS0_END_IE0_POS 8U -#define ADC_SS0_END_IE0_MSK BIT(ADC_SS0_END_IE0_POS) - -#define ADC_SS0_END_END_POSS 0U -#define ADC_SS0_END_END_POSE 3U -#define ADC_SS0_END_END_MSK BITS(ADC_SS0_END_END_POSS,ADC_SS0_END_END_POSE) - -/****************** Bit definition for ADC_SS0_FSTAT register ************************/ - -#define ADC_SS0_FSTAT_OV_POS 11U -#define ADC_SS0_FSTAT_OV_MSK BIT(ADC_SS0_FSTAT_OV_POS) - -#define ADC_SS0_FSTAT_FULL_POS 10U -#define ADC_SS0_FSTAT_FULL_MSK BIT(ADC_SS0_FSTAT_FULL_POS) - -#define ADC_SS0_FSTAT_UV_POS 9U -#define ADC_SS0_FSTAT_UV_MSK BIT(ADC_SS0_FSTAT_UV_POS) - -#define ADC_SS0_FSTAT_EMPTY_POS 8U -#define ADC_SS0_FSTAT_EMPTY_MSK BIT(ADC_SS0_FSTAT_EMPTY_POS) - -#define ADC_SS0_FSTAT_HPTR_POSS 4U -#define ADC_SS0_FSTAT_HPTR_POSE 7U -#define ADC_SS0_FSTAT_HPTR_MSK BITS(ADC_SS0_FSTAT_HPTR_POSS,ADC_SS0_FSTAT_HPTR_POSE) - -#define ADC_SS0_FSTAT_TPTR_POSS 0U -#define ADC_SS0_FSTAT_TPTR_POSE 3U -#define ADC_SS0_FSTAT_TPTR_MSK BITS(ADC_SS0_FSTAT_TPTR_POSS,ADC_SS0_FSTAT_TPTR_POSE) - -/****************** Bit definition for ADC_SS0_DATA register ************************/ - -#define ADC_SS0_DATA_DATA_POSS 0U -#define ADC_SS0_DATA_DATA_POSE 11U -#define ADC_SS0_DATA_DATA_MSK BITS(ADC_SS0_DATA_DATA_POSS,ADC_SS0_DATA_DATA_POSE) - -/****************** Bit definition for ADC_SS1_CON register ************************/ - -#define ADC_SS1_CON_SEL_POSS 11U -#define ADC_SS1_CON_SEL_POSE 15U -#define ADC_SS1_CON_SEL_MSK BITS(ADC_SS1_CON_SEL_POSS,ADC_SS1_CON_SEL_POSE) - -#define ADC_SS1_CON_TYP_POS 8U -#define ADC_SS1_CON_TYP_MSK BIT(ADC_SS1_CON_TYP_POS) - -#define ADC_SS1_CON_PRI_POSS 4U -#define ADC_SS1_CON_PRI_POSE 5U -#define ADC_SS1_CON_PRI_MSK BITS(ADC_SS1_CON_PRI_POSS,ADC_SS1_CON_PRI_POSE) - -#define ADC_SS1_CON_ONE_POS 0U -#define ADC_SS1_CON_ONE_MSK BIT(ADC_SS1_CON_ONE_POS) - -/****************** Bit definition for ADC_SS1_MUX0 register ************************/ - -#define ADC_SS1_MUX0_MUX7_POSS 28U -#define ADC_SS1_MUX0_MUX7_POSE 31U -#define ADC_SS1_MUX0_MUX7_MSK BITS(ADC_SS1_MUX0_MUX7_POSS,ADC_SS1_MUX0_MUX7_POSE) - -#define ADC_SS1_MUX0_MUX6_POSS 24U -#define ADC_SS1_MUX0_MUX6_POSE 27U -#define ADC_SS1_MUX0_MUX6_MSK BITS(ADC_SS1_MUX0_MUX6_POSS,ADC_SS1_MUX0_MUX6_POSE) - -#define ADC_SS1_MUX0_MUX5_POSS 20U -#define ADC_SS1_MUX0_MUX5_POSE 23U -#define ADC_SS1_MUX0_MUX5_MSK BITS(ADC_SS1_MUX0_MUX5_POSS,ADC_SS1_MUX0_MUX5_POSE) - -#define ADC_SS1_MUX0_MUX4_POSS 16U -#define ADC_SS1_MUX0_MUX4_POSE 19U -#define ADC_SS1_MUX0_MUX4_MSK BITS(ADC_SS1_MUX0_MUX4_POSS,ADC_SS1_MUX0_MUX4_POSE) - -#define ADC_SS1_MUX0_MUX3_POSS 12U -#define ADC_SS1_MUX0_MUX3_POSE 15U -#define ADC_SS1_MUX0_MUX3_MSK BITS(ADC_SS1_MUX0_MUX3_POSS,ADC_SS1_MUX0_MUX3_POSE) - -#define ADC_SS1_MUX0_MUX2_POSS 8U -#define ADC_SS1_MUX0_MUX2_POSE 11U -#define ADC_SS1_MUX0_MUX2_MSK BITS(ADC_SS1_MUX0_MUX2_POSS,ADC_SS1_MUX0_MUX2_POSE) - -#define ADC_SS1_MUX0_MUX1_POSS 4U -#define ADC_SS1_MUX0_MUX1_POSE 7U -#define ADC_SS1_MUX0_MUX1_MSK BITS(ADC_SS1_MUX0_MUX1_POSS,ADC_SS1_MUX0_MUX1_POSE) - -#define ADC_SS1_MUX0_MUX0_POSS 0U -#define ADC_SS1_MUX0_MUX0_POSE 3U -#define ADC_SS1_MUX0_MUX0_MSK BITS(ADC_SS1_MUX0_MUX0_POSS,ADC_SS1_MUX0_MUX0_POSE) - -/****************** Bit definition for ADC_SS1_END register ************************/ - -#define ADC_SS1_END_IE7_POS 15U -#define ADC_SS1_END_IE7_MSK BIT(ADC_SS1_END_IE7_POS) - -#define ADC_SS1_END_IE6_POS 14U -#define ADC_SS1_END_IE6_MSK BIT(ADC_SS1_END_IE6_POS) - -#define ADC_SS1_END_IE5_POS 13U -#define ADC_SS1_END_IE5_MSK BIT(ADC_SS1_END_IE5_POS) - -#define ADC_SS1_END_IE4_POS 12U -#define ADC_SS1_END_IE4_MSK BIT(ADC_SS1_END_IE4_POS) - -#define ADC_SS1_END_IE3_POS 11U -#define ADC_SS1_END_IE3_MSK BIT(ADC_SS1_END_IE3_POS) - -#define ADC_SS1_END_IE2_POS 10U -#define ADC_SS1_END_IE2_MSK BIT(ADC_SS1_END_IE2_POS) - -#define ADC_SS1_END_IE1_POS 9U -#define ADC_SS1_END_IE1_MSK BIT(ADC_SS1_END_IE1_POS) - -#define ADC_SS1_END_IE0_POS 8U -#define ADC_SS1_END_IE0_MSK BIT(ADC_SS1_END_IE0_POS) - -#define ADC_SS1_END_END_POSS 0U -#define ADC_SS1_END_END_POSE 2U -#define ADC_SS1_END_END_MSK BITS(ADC_SS1_END_END_POSS,ADC_SS1_END_END_POSE) - -/****************** Bit definition for ADC_SS1_FSTAT register ************************/ - -#define ADC_SS1_FSTAT_OV_POS 11U -#define ADC_SS1_FSTAT_OV_MSK BIT(ADC_SS1_FSTAT_OV_POS) - -#define ADC_SS1_FSTAT_FULL_POS 10U -#define ADC_SS1_FSTAT_FULL_MSK BIT(ADC_SS1_FSTAT_FULL_POS) - -#define ADC_SS1_FSTAT_UV_POS 9U -#define ADC_SS1_FSTAT_UV_MSK BIT(ADC_SS1_FSTAT_UV_POS) - -#define ADC_SS1_FSTAT_EMPTY_POS 8U -#define ADC_SS1_FSTAT_EMPTY_MSK BIT(ADC_SS1_FSTAT_EMPTY_POS) - -#define ADC_SS1_FSTAT_HPTR_POSS 4U -#define ADC_SS1_FSTAT_HPTR_POSE 7U -#define ADC_SS1_FSTAT_HPTR_MSK BITS(ADC_SS1_FSTAT_HPTR_POSS,ADC_SS1_FSTAT_HPTR_POSE) - -#define ADC_SS1_FSTAT_TPTR_POSS 0U -#define ADC_SS1_FSTAT_TPTR_POSE 3U -#define ADC_SS1_FSTAT_TPTR_MSK BITS(ADC_SS1_FSTAT_TPTR_POSS,ADC_SS1_FSTAT_TPTR_POSE) - -/****************** Bit definition for ADC_SS1_DATA register ************************/ - -#define ADC_SS1_DATA_DATA_POSS 0U -#define ADC_SS1_DATA_DATA_POSE 11U -#define ADC_SS1_DATA_DATA_MSK BITS(ADC_SS1_DATA_DATA_POSS,ADC_SS1_DATA_DATA_POSE) - -/****************** Bit definition for ADC_SS2_CON register ************************/ - -#define ADC_SS2_CON_SEL_POSS 11U -#define ADC_SS2_CON_SEL_POSE 15U -#define ADC_SS2_CON_SEL_MSK BITS(ADC_SS2_CON_SEL_POSS,ADC_SS2_CON_SEL_POSE) - -#define ADC_SS2_CON_TYP_POS 8U -#define ADC_SS2_CON_TYP_MSK BIT(ADC_SS2_CON_TYP_POS) - -#define ADC_SS2_CON_PRI_POSS 4U -#define ADC_SS2_CON_PRI_POSE 5U -#define ADC_SS2_CON_PRI_MSK BITS(ADC_SS2_CON_PRI_POSS,ADC_SS2_CON_PRI_POSE) - -#define ADC_SS2_CON_ONE_POS 0U -#define ADC_SS2_CON_ONE_MSK BIT(ADC_SS2_CON_ONE_POS) - -/****************** Bit definition for ADC_SS2_MUX0 register ************************/ - -#define ADC_SS2_MUX0_MUX3_POSS 12U -#define ADC_SS2_MUX0_MUX3_POSE 15U -#define ADC_SS2_MUX0_MUX3_MSK BITS(ADC_SS2_MUX0_MUX3_POSS,ADC_SS2_MUX0_MUX3_POSE) - -#define ADC_SS2_MUX0_MUX2_POSS 8U -#define ADC_SS2_MUX0_MUX2_POSE 11U -#define ADC_SS2_MUX0_MUX2_MSK BITS(ADC_SS2_MUX0_MUX2_POSS,ADC_SS2_MUX0_MUX2_POSE) - -#define ADC_SS2_MUX0_MUX1_POSS 4U -#define ADC_SS2_MUX0_MUX1_POSE 7U -#define ADC_SS2_MUX0_MUX1_MSK BITS(ADC_SS2_MUX0_MUX1_POSS,ADC_SS2_MUX0_MUX1_POSE) - -#define ADC_SS2_MUX0_MUX0_POSS 0U -#define ADC_SS2_MUX0_MUX0_POSE 3U -#define ADC_SS2_MUX0_MUX0_MSK BITS(ADC_SS2_MUX0_MUX0_POSS,ADC_SS2_MUX0_MUX0_POSE) - -/****************** Bit definition for ADC_SS2_END register ************************/ - -#define ADC_SS2_END_IE3_POS 11U -#define ADC_SS2_END_IE3_MSK BIT(ADC_SS2_END_IE3_POS) - -#define ADC_SS2_END_IE2_POS 10U -#define ADC_SS2_END_IE2_MSK BIT(ADC_SS2_END_IE2_POS) - -#define ADC_SS2_END_IE1_POS 9U -#define ADC_SS2_END_IE1_MSK BIT(ADC_SS2_END_IE1_POS) - -#define ADC_SS2_END_IE0_POS 8U -#define ADC_SS2_END_IE0_MSK BIT(ADC_SS2_END_IE0_POS) - -#define ADC_SS2_END_END_POSS 0U -#define ADC_SS2_END_END_POSE 1U -#define ADC_SS2_END_END_MSK BITS(ADC_SS2_END_END_POSS,ADC_SS2_END_END_POSE) - -/****************** Bit definition for ADC_SS2_FSTAT register ************************/ - -#define ADC_SS2_FSTAT_OV_POS 11U -#define ADC_SS2_FSTAT_OV_MSK BIT(ADC_SS2_FSTAT_OV_POS) - -#define ADC_SS2_FSTAT_FULL_POS 10U -#define ADC_SS2_FSTAT_FULL_MSK BIT(ADC_SS2_FSTAT_FULL_POS) - -#define ADC_SS2_FSTAT_UV_POS 9U -#define ADC_SS2_FSTAT_UV_MSK BIT(ADC_SS2_FSTAT_UV_POS) - -#define ADC_SS2_FSTAT_EMPTY_POS 8U -#define ADC_SS2_FSTAT_EMPTY_MSK BIT(ADC_SS2_FSTAT_EMPTY_POS) - -#define ADC_SS2_FSTAT_HPTR_POSS 4U -#define ADC_SS2_FSTAT_HPTR_POSE 7U -#define ADC_SS2_FSTAT_HPTR_MSK BITS(ADC_SS2_FSTAT_HPTR_POSS,ADC_SS2_FSTAT_HPTR_POSE) - -#define ADC_SS2_FSTAT_TPTR_POSS 0U -#define ADC_SS2_FSTAT_TPTR_POSE 3U -#define ADC_SS2_FSTAT_TPTR_MSK BITS(ADC_SS2_FSTAT_TPTR_POSS,ADC_SS2_FSTAT_TPTR_POSE) - -/****************** Bit definition for ADC_SS2_DATA register ************************/ - -#define ADC_SS2_DATA_DATA_POSS 0U -#define ADC_SS2_DATA_DATA_POSE 11U -#define ADC_SS2_DATA_DATA_MSK BITS(ADC_SS2_DATA_DATA_POSS,ADC_SS2_DATA_DATA_POSE) - -/****************** Bit definition for ADC_SS3_CON register ************************/ - -#define ADC_SS3_CON_SEL_POSS 11U -#define ADC_SS3_CON_SEL_POSE 15U -#define ADC_SS3_CON_SEL_MSK BITS(ADC_SS3_CON_SEL_POSS,ADC_SS3_CON_SEL_POSE) - -#define ADC_SS3_CON_TYP_POS 8U -#define ADC_SS3_CON_TYP_MSK BIT(ADC_SS3_CON_TYP_POS) - -#define ADC_SS3_CON_PRI_POSS 4U -#define ADC_SS3_CON_PRI_POSE 5U -#define ADC_SS3_CON_PRI_MSK BITS(ADC_SS3_CON_PRI_POSS,ADC_SS3_CON_PRI_POSE) - -#define ADC_SS3_CON_ONE_POS 0U -#define ADC_SS3_CON_ONE_MSK BIT(ADC_SS3_CON_ONE_POS) - -/****************** Bit definition for ADC_SS3_MUX0 register ************************/ - -#define ADC_SS3_MUX0_MUX0_POSS 0U -#define ADC_SS3_MUX0_MUX0_POSE 3U -#define ADC_SS3_MUX0_MUX0_MSK BITS(ADC_SS3_MUX0_MUX0_POSS,ADC_SS3_MUX0_MUX0_POSE) - -/****************** Bit definition for ADC_SS3_END register ************************/ - -#define ADC_SS3_END_IE0_POS 8U -#define ADC_SS3_END_IE0_MSK BIT(ADC_SS3_END_IE0_POS) - -#define ADC_SS3_END_END_POS 0U -#define ADC_SS3_END_END_MSK BIT(ADC_SS3_END_END_POS) - -/****************** Bit definition for ADC_SS3_FSTAT register ************************/ - -#define ADC_SS3_FSTAT_OV_POS 11U -#define ADC_SS3_FSTAT_OV_MSK BIT(ADC_SS3_FSTAT_OV_POS) - -#define ADC_SS3_FSTAT_FULL_POS 10U -#define ADC_SS3_FSTAT_FULL_MSK BIT(ADC_SS3_FSTAT_FULL_POS) - -#define ADC_SS3_FSTAT_UV_POS 9U -#define ADC_SS3_FSTAT_UV_MSK BIT(ADC_SS3_FSTAT_UV_POS) - -#define ADC_SS3_FSTAT_EMPTY_POS 8U -#define ADC_SS3_FSTAT_EMPTY_MSK BIT(ADC_SS3_FSTAT_EMPTY_POS) - -#define ADC_SS3_FSTAT_HPTR_POSS 4U -#define ADC_SS3_FSTAT_HPTR_POSE 7U -#define ADC_SS3_FSTAT_HPTR_MSK BITS(ADC_SS3_FSTAT_HPTR_POSS,ADC_SS3_FSTAT_HPTR_POSE) - -#define ADC_SS3_FSTAT_TPTR_POSS 0U -#define ADC_SS3_FSTAT_TPTR_POSE 3U -#define ADC_SS3_FSTAT_TPTR_MSK BITS(ADC_SS3_FSTAT_TPTR_POSS,ADC_SS3_FSTAT_TPTR_POSE) - -/****************** Bit definition for ADC_SS3_DATA register ************************/ - -#define ADC_SS3_DATA_DATA_POSS 0U -#define ADC_SS3_DATA_DATA_POSE 11U -#define ADC_SS3_DATA_DATA_MSK BITS(ADC_SS3_DATA_DATA_POSS,ADC_SS3_DATA_DATA_POSE) - -typedef struct -{ - __IO uint32_t CFG; - __IO uint32_t SRATE; - __IO uint32_t CHINV; - __IO uint32_t GAINL; - __IO uint32_t GAINH; - __O uint32_t FRF; - __IO uint32_t SSEN; - __IO uint32_t SWTRI; - __O uint32_t IER; - __O uint32_t IDR; - __I uint32_t IVS; - __I uint32_t RIF; - __I uint32_t IFM; - __O uint32_t ICR; - __IO uint32_t DMA; - uint32_t RESERVED0 ; - __IO uint32_t SS0_CON; - __IO uint32_t SS0_MUX0; - __IO uint32_t SS0_MUX1; - __IO uint32_t SS0_END; - __I uint32_t SS0_FSTAT; - __IO uint32_t SS0_DATA; - uint32_t RESERVED1[2] ; - __IO uint32_t SS1_CON; - __IO uint32_t SS1_MUX0; - __IO uint32_t SS1_END; - __I uint32_t SS1_FSTAT; - __IO uint32_t SS1_DATA; - uint32_t RESERVED2 ; - __IO uint32_t SS2_CON; - __IO uint32_t SS2_MUX0; - __IO uint32_t SS2_END; - __I uint32_t SS2_FSTAT; - __IO uint32_t SS2_DATA; - uint32_t RESERVED3 ; - __IO uint32_t SS3_CON; - __IO uint32_t SS3_MUX0; - __IO uint32_t SS3_END; - __I uint32_t SS3_FSTAT; - __IO uint32_t SS3_DATA; -} ADC_TypeDef; - - - - - -#endif diff --git a/bsp/essemi/es32f0271/libraries/CMSIS/Device/EastSoft/ES32F0271/Include/ES32F0271/reg_aes.h b/bsp/essemi/es32f0271/libraries/CMSIS/Device/EastSoft/ES32F0271/Include/ES32F0271/reg_aes.h deleted file mode 100644 index dd47cdea10..0000000000 --- a/bsp/essemi/es32f0271/libraries/CMSIS/Device/EastSoft/ES32F0271/Include/ES32F0271/reg_aes.h +++ /dev/null @@ -1,193 +0,0 @@ -/** - ************************************************************************************** - * @file REG_AES.h - * @brief AES Head File - * - * @version V0.01 - * @data 11/16/2018 - * @author Eastsoft AE Team - * @note - * - * Copyright (C) 2018 Shanghai Eastsoft Microelectronics Co., Ltd. ALL rights reserved. - * - ************************************************************************************** - */ - -#ifndef __AES_H__ -#define __AES_H__ - - -/******************************************************************************/ -/* 设备特殊寄存器结构定义 */ -/******************************************************************************/ - -/* 允许匿名结构和匿名联合 */ -/* #pragma anon_unions */ - -/****************** Bit definition for AES_CON register ************************/ - -#define AES_CON_READY_POS 22U -#define AES_CON_READY_MSK BIT(AES_CON_READY_POS) - -#define AES_CON_OT_DMA_ST_POS 21U -#define AES_CON_OT_DMA_ST_MSK BIT(AES_CON_OT_DMA_ST_POS) - -#define AES_CON_IT_DMA_ST_POS 20U -#define AES_CON_IT_DMA_ST_MSK BIT(AES_CON_IT_DMA_ST_POS) - -#define AES_CON_OT_DEPTH_POSS 18U -#define AES_CON_OT_DEPTH_POSE 19U -#define AES_CON_OT_DEPTH_MSK BITS(AES_CON_OT_DEPTH_POSS,AES_CON_OT_DEPTH_POSE) - -#define AES_CON_IT_DEPTH_POSS 16U -#define AES_CON_IT_DEPTH_POSE 17U -#define AES_CON_IT_DEPTH_MSK BITS(AES_CON_IT_DEPTH_POSS,AES_CON_IT_DEPTH_POSE) - -#define AES_CON_RE_INIT_POS 8U -#define AES_CON_RE_INIT_MSK BIT(AES_CON_RE_INIT_POS) - -#define AES_CON_DMA_EN_POSS 6U -#define AES_CON_DMA_EN_POSE 7U -#define AES_CON_DMA_EN_MSK BITS(AES_CON_DMA_EN_POSS,AES_CON_DMA_EN_POSE) - -#define AES_CON_BL_POSS 3U -#define AES_CON_BL_POSE 5U -#define AES_CON_BL_MSK BITS(AES_CON_BL_POSS,AES_CON_BL_POSE) - -#define AES_CON_REV_POS 2U -#define AES_CON_REV_MSK BIT(AES_CON_REV_POS) - -#define AES_CON_MODE_POS 1U -#define AES_CON_MODE_MSK BIT(AES_CON_MODE_POS) - -#define AES_CON_START_POS 0U -#define AES_CON_START_MSK BIT(AES_CON_START_POS) - -/****************** Bit definition for AES_IER register ************************/ - -#define AES_IER_DECIE_POS 1U -#define AES_IER_DECIE_MSK BIT(AES_IER_DECIE_POS) - -#define AES_IER_ENCIE_POS 0U -#define AES_IER_ENCIE_MSK BIT(AES_IER_ENCIE_POS) - -/****************** Bit definition for AES_IDR register ************************/ - -#define AES_IDR_DECID_POS 1U -#define AES_IDR_DECID_MSK BIT(AES_IDR_DECID_POS) - -#define AES_IDR_ENCID_POS 0U -#define AES_IDR_ENCID_MSK BIT(AES_IDR_ENCID_POS) - -/****************** Bit definition for AES_IVS register ************************/ - -#define AES_IVS_DECIVS_POS 1U -#define AES_IVS_DECIVS_MSK BIT(AES_IVS_DECIVS_POS) - -#define AES_IVS_ENCIVS_POS 0U -#define AES_IVS_ENCIVS_MSK BIT(AES_IVS_ENCIVS_POS) - -/****************** Bit definition for AES_RIF register ************************/ - -#define AES_RIF_DECRIF_POS 1U -#define AES_RIF_DECRIF_MSK BIT(AES_RIF_DECRIF_POS) - -#define AES_RIF_ENCRIF_POS 0U -#define AES_RIF_ENCRIF_MSK BIT(AES_RIF_ENCRIF_POS) - -/****************** Bit definition for AES_IFM register ************************/ - -#define AES_IFM_DECIFM_POS 1U -#define AES_IFM_DECIFM_MSK BIT(AES_IFM_DECIFM_POS) - -#define AES_IFM_ENCIFM_POS 0U -#define AES_IFM_ENCIFM_MSK BIT(AES_IFM_ENCIFM_POS) - -/****************** Bit definition for AES_ICR register ************************/ - -#define AES_ICR_DECICR_POS 1U -#define AES_ICR_DECICR_MSK BIT(AES_ICR_DECICR_POS) - -#define AES_ICR_ENCICR_POS 0U -#define AES_ICR_ENCICR_MSK BIT(AES_ICR_ENCICR_POS) - -/****************** Bit definition for AES_DIO register ************************/ - -#define AES_DIO_DIO_POSS 0U -#define AES_DIO_DIO_POSE 31U -#define AES_DIO_DIO_MSK BITS(AES_DIO_DIO_POSS,AES_DIO_DIO_POSE) - -/****************** Bit definition for AES_KEY0 register ************************/ - -#define AES_KEY0_KEY0_POSS 0U -#define AES_KEY0_KEY0_POSE 31U -#define AES_KEY0_KEY0_MSK BITS(AES_KEY0_KEY0_POSS,AES_KEY0_KEY0_POSE) - -/****************** Bit definition for AES_KEY1 register ************************/ - -#define AES_KEY1_KEY1_POSS 0U -#define AES_KEY1_KEY1_POSE 31U -#define AES_KEY1_KEY1_MSK BITS(AES_KEY1_KEY1_POSS,AES_KEY1_KEY1_POSE) - -/****************** Bit definition for AES_KEY2 register ************************/ - -#define AES_KEY2_KEY2_POSS 0U -#define AES_KEY2_KEY2_POSE 31U -#define AES_KEY2_KEY2_MSK BITS(AES_KEY2_KEY2_POSS,AES_KEY2_KEY2_POSE) - -/****************** Bit definition for AES_KEY3 register ************************/ - -#define AES_KEY3_KEY3_POSS 0U -#define AES_KEY3_KEY3_POSE 31U -#define AES_KEY3_KEY3_MSK BITS(AES_KEY3_KEY3_POSS,AES_KEY3_KEY3_POSE) - -/****************** Bit definition for AES_IV0 register ************************/ - -#define AES_IV0_IV0_POSS 0U -#define AES_IV0_IV0_POSE 31U -#define AES_IV0_IV0_MSK BITS(AES_IV0_IV0_POSS,AES_IV0_IV0_POSE) - -/****************** Bit definition for AES_IV1 register ************************/ - -#define AES_IV1_IV1_POSS 0U -#define AES_IV1_IV1_POSE 31U -#define AES_IV1_IV1_MSK BITS(AES_IV1_IV1_POSS,AES_IV1_IV1_POSE) - -/****************** Bit definition for AES_IV2 register ************************/ - -#define AES_IV2_IV2_POSS 0U -#define AES_IV2_IV2_POSE 31U -#define AES_IV2_IV2_MSK BITS(AES_IV2_IV2_POSS,AES_IV2_IV2_POSE) - -/****************** Bit definition for AES_IV3 register ************************/ - -#define AES_IV3_IV3_POSS 0U -#define AES_IV3_IV3_POSE 31U -#define AES_IV3_IV3_MSK BITS(AES_IV3_IV3_POSS,AES_IV3_IV3_POSE) - -typedef struct -{ - __IO uint32_t CON; /* 0x000 AES_CON AES Control Register */ - __O uint32_t IER; /* 0x004 AES_IER AES Interrupt Enable Register */ - __O uint32_t IDR; /* 0x008 AES_IDR AES Interrupt Disable Register */ - __I uint32_t IVS; /* 0x00C AES_IVS AES Interrupt Valid Status Register */ - __I uint32_t RIF; /* 0x010 AES_RIF AES Raw Interrupt Flag Status Register */ - __I uint32_t IFM; /* 0x014 AES_IFM AES Interrupt Flag Masked Register */ - __O uint32_t ICR; /* 0x018 AES_ICR AES Interrupt Clear Register */ - __IO uint32_t DIO; /* 0x01C AES_DIO AES 128-bit Input/Output Data Register */ - __IO uint32_t KEY0; /* 0x020 AES_KEY0 AES 256-bit Keyword Register 0 */ - __IO uint32_t KEY1; /* 0x024 AES_KEY1 AES 256-bit Keyword Register 1 */ - __IO uint32_t KEY2; /* 0x028 AES_KEY2 AES 256-bit Keyword Register 2 */ - __IO uint32_t KEY3; /* 0x02C AES_KEY3 AES 256-bit Keyword Register 3 */ - uint32_t RESERVED0[4] ; - __IO uint32_t IV0; /* 0x040 AES_IV0 AES 128-bit Initial Vector Register 0 */ - __IO uint32_t IV1; /* 0x044 AES_IV1 AES 128-bit Initial Vector Register 1 */ - __IO uint32_t IV2; /* 0x048 AES_IV2 AES 128-bit Initial Vector Register 2 */ - __IO uint32_t IV3; /* 0x04C AES_IV3 AES 128-bit Initial Vector Register 3 */ -} AES_TypeDef; - - - - - -#endif diff --git a/bsp/essemi/es32f0271/libraries/CMSIS/Device/EastSoft/ES32F0271/Include/ES32F0271/reg_cmp.h b/bsp/essemi/es32f0271/libraries/CMSIS/Device/EastSoft/ES32F0271/Include/ES32F0271/reg_cmp.h deleted file mode 100644 index 8b1f4e5de6..0000000000 --- a/bsp/essemi/es32f0271/libraries/CMSIS/Device/EastSoft/ES32F0271/Include/ES32F0271/reg_cmp.h +++ /dev/null @@ -1,95 +0,0 @@ -/** - ************************************************************************************** - * @file REG_CMP.h - * @brief CMP Head File - * - * @version V0.01 - * @data 12/3/2018 - * @author Eastsoft MCU Software Team - * @note - * - * Copyright (C) 2018 Shanghai Eastsoft Microelectronics Co., Ltd. ALL rights reserved. - * - ************************************************************************************** - */ - -#ifndef __CMP_H__ -#define __CMP_H__ - - -/******************************************************************************/ -/* 设备特殊寄存器结构定义 */ -/******************************************************************************/ - -/* 允许匿名结构和匿名联合 */ -/* #pragma anon_unions */ - -/****************** Bit definition for CMP_CON register ************************/ - -#define CMP_CON_REFON_POS 4U -#define CMP_CON_REFON_MSK BIT(CMP_CON_REFON_POS) - -#define CMP_CON_CMPON2_POS 1U -#define CMP_CON_CMPON2_MSK BIT(CMP_CON_CMPON2_POS) - -#define CMP_CON_CMPON1_POS 0U -#define CMP_CON_CMPON1_MSK BIT(CMP_CON_CMPON1_POS) - -/****************** Bit definition for CMP_CFG1 register ************************/ - -#define CMP_CFG1_RS_POSS 4U -#define CMP_CFG1_RS_POSE 5U -#define CMP_CFG1_RS_MSK BITS(CMP_CFG1_RS_POSS,CMP_CFG1_RS_POSE) - -#define CMP_CFG1_FEN_POS 3U -#define CMP_CFG1_FEN_MSK BIT(CMP_CFG1_FEN_POS) - -#define CMP_CFG1_PSEN_POS 2U -#define CMP_CFG1_PSEN_MSK BIT(CMP_CFG1_PSEN_POS) - -#define CMP_CFG1_INSEL_POS 1U -#define CMP_CFG1_INSEL_MSK BIT(CMP_CFG1_INSEL_POS) - -#define CMP_CFG1_IPSEL_POS 0U -#define CMP_CFG1_IPSEL_MSK BIT(CMP_CFG1_IPSEL_POS) - -/****************** Bit definition for CMP_CFG2 register ************************/ - -#define CMP_CFG2_RS_POSS 4U -#define CMP_CFG2_RS_POSE 5U -#define CMP_CFG2_RS_MSK BITS(CMP_CFG2_RS_POSS,CMP_CFG2_RS_POSE) - -#define CMP_CFG2_FEN_POS 3U -#define CMP_CFG2_FEN_MSK BIT(CMP_CFG1_FEN_POS) - -#define CMP_CFG2_PSEN_POS 2U -#define CMP_CFG2_PSEN_MSK BIT(CMP_CFG1_PSEN_POS) - -#define CMP_CFG2_INSEL_POS 1U -#define CMP_CFG2_INSEL_MSK BIT(CMP_CFG1_INSEL_POS) - -#define CMP_CFG2_IPSEL_POS 0U -#define CMP_CFG2_IPSEL_MSK BIT(CMP_CFG1_IPSEL_POS) - -/****************** Bit definition for CMP_RULT register ************************/ - -#define CMP_RULT_CMPO2_POS 1U -#define CMP_RULT_CMPO2_MSK BIT(CMP_RULT_CMPO2_POS) - -#define CMP_RULT_CMPO1_POS 0U -#define CMP_RULT_CMPO1_MSK BIT(CMP_RULT_CMPO1_POS) - -typedef struct -{ - __IO uint32_t CON; - __IO uint32_t CFG1; - __IO uint32_t CFG2; - uint32_t RESERVED0[2] ; - __I uint32_t RULT; -} CMP_TypeDef; - - - - - -#endif diff --git a/bsp/essemi/es32f0271/libraries/CMSIS/Device/EastSoft/ES32F0271/Include/ES32F0271/reg_crc.h b/bsp/essemi/es32f0271/libraries/CMSIS/Device/EastSoft/ES32F0271/Include/ES32F0271/reg_crc.h deleted file mode 100644 index cdbb00b45c..0000000000 --- a/bsp/essemi/es32f0271/libraries/CMSIS/Device/EastSoft/ES32F0271/Include/ES32F0271/reg_crc.h +++ /dev/null @@ -1,125 +0,0 @@ -/** - ************************************************************************************** - * @file REG_CRC.h - * @brief CRC Head File - * - * @version V0.01 - * @data 11/16/2018 - * @author Eastsoft MCU Software Team - * @note - * - * Copyright (C) 2018 Shanghai Eastsoft Microelectronics Co., Ltd. ALL rights reserved. - * - ************************************************************************************** - */ - -#ifndef __CRC_H__ -#define __CRC_H__ - - -/******************************************************************************/ -/* 设备特殊寄存器结构定义 */ -/******************************************************************************/ - -/* 允许匿名结构和匿名联合 */ -/* #pragma anon_unions */ - -/****************** Bit definition for CRC_INIT register ************************/ - -#define CRC_INIT_INIT_POSS 0U -#define CRC_INIT_INIT_POSE 31U -#define CRC_INIT_INIT_MSK BITS(CRC_INIT_INIT_POSS,CRC_INIT_INIT_POSE) - -/****************** Bit definition for CRC_POLY register ************************/ - -#define CRC_POLY_POLY_POSS 0U -#define CRC_POLY_POLY_POSE 31U -#define CRC_POLY_POLY_MSK BITS(CRC_POLY_POLY_POSS,CRC_POLY_POLY_POSE) - -/****************** Bit definition for CRC_DATA register ************************/ - -#define CRC_DATA_DATA_POSS 0U -#define CRC_DATA_DATA_POSE 31U -#define CRC_DATA_DATA_MSK BITS(CRC_DATA_DATA_POSS,CRC_DATA_DATA_POSE) - -/****************** Bit definition for CRC_COMP register ************************/ - -#define CRC_COMP_COMP_POSS 0U -#define CRC_COMP_COMP_POSE 31U -#define CRC_COMP_COMP_MSK BITS(CRC_COMP_COMP_POSS,CRC_COMP_COMP_POSE) - -/****************** Bit definition for CRC_REMA register ************************/ - -#define CRC_REMA_REMA_POSS 0U -#define CRC_REMA_REMA_POSE 31U -#define CRC_REMA_REMA_MSK BITS(CRC_REMA_REMA_POSS,CRC_REMA_REMA_POSE) - -/****************** Bit definition for CRC_CON register ************************/ - -#define CRC_CON_DMA_POS 16U -#define CRC_CON_DMA_MSK BIT(CRC_CON_DMA_POS) - -#define CRC_CON_MSB_POS 12U -#define CRC_CON_MSB_MSK BIT(CRC_CON_MSB_POS) - -#define CRC_CON_REOUT_POS 10U -#define CRC_CON_REOUT_MSK BIT(CRC_CON_REOUT_POS) - -#define CRC_CON_REIN_POS 8U -#define CRC_CON_REIN_MSK BIT(CRC_CON_REIN_POS) - -#define CRC_CON_SIZE_POSS 4U -#define CRC_CON_SIZE_POSE 5U -#define CRC_CON_SIZE_MSK BITS(CRC_CON_SIZE_POSS,CRC_CON_SIZE_POSE) - -#define CRC_CON_MODE_POSS 2U -#define CRC_CON_MODE_POSE 3U -#define CRC_CON_MODE_MSK BITS(CRC_CON_MODE_POSS,CRC_CON_MODE_POSE) - -#define CRC_CON_RESET_POS 0U -#define CRC_CON_RESET_MSK BIT(CRC_CON_RESET_POS) - -/****************** Bit definition for CRC_DOUT register ************************/ - -#define CRC_DOUT_DOUT_POSS 0U -#define CRC_DOUT_DOUT_POSE 31U -#define CRC_DOUT_DOUT_MSK BITS(CRC_DOUT_DOUT_POSS,CRC_DOUT_DOUT_POSE) - -/****************** Bit definition for CRC_DOUT_XOR register ************************/ - -#define CRC_DOUT_XOR_DOUT_XOR_POSS 0U -#define CRC_DOUT_XOR_DOUT_XOR_POSE 31U -#define CRC_DOUT_XOR_DOUT_XOR_MSK BITS(CRC_DOUT_XOR_DOUT_XOR_POSS,CRC_DOUT_XOR_DOUT_XOR_POSE) - -/****************** Bit definition for CRC_STAT register ************************/ - -#define CRC_STAT_FAIL_POS 8U -#define CRC_STAT_FAIL_MSK BIT(CRC_STAT_FAIL_POS) - -#define CRC_STAT_EMPTY_POS 2U -#define CRC_STAT_EMPTY_MSK BIT(CRC_STAT_EMPTY_POS) - -#define CRC_STAT_BUSY_POS 1U -#define CRC_STAT_BUSY_MSK BIT(CRC_STAT_BUSY_POS) - -#define CRC_STAT_DONE_POS 0U -#define CRC_STAT_DONE_MSK BIT(CRC_STAT_DONE_POS) - -typedef struct -{ - __IO uint32_t INIT; /* 0x000 CRC_INIT CRC Iintial Value Register */ - __IO uint32_t POLY; /* 0x004 CRC_POLY CRC Polynomial Register */ - __IO uint32_t DATA; /* 0x008 CRC_DATA CRC Input Data Register */ - __IO uint32_t COMP; /* 0x00C CRC_COMP CRC Compare Data Register */ - __IO uint32_t REMA; /* 0x010 CRC_REMA CRC Remainder Register */ - __IO uint32_t CON; /* 0x014 CRC_CTRL CRC Control Register */ - __I uint32_t DOUT; /* 0x018 CRC_DOUT CRC Output Data Register */ - __I uint32_t DOUT_XOR; /* 0x01C CRC_DOUT_XOR CRC Output Data Register */ - __I uint32_t STAT; /* 0x020 CRC_STA CRC Status Register */ -} CRC_TypeDef; - - - - - -#endif diff --git a/bsp/essemi/es32f0271/libraries/CMSIS/Device/EastSoft/ES32F0271/Include/ES32F0271/reg_dac.h b/bsp/essemi/es32f0271/libraries/CMSIS/Device/EastSoft/ES32F0271/Include/ES32F0271/reg_dac.h deleted file mode 100644 index 73a409e5eb..0000000000 --- a/bsp/essemi/es32f0271/libraries/CMSIS/Device/EastSoft/ES32F0271/Include/ES32F0271/reg_dac.h +++ /dev/null @@ -1,97 +0,0 @@ -/** - ************************************************************************************** - * @file REG_DAC.h - * @brief DAC Head File - * - * @version V0.01 - * @data 1/14/2019 - * @author Eastsoft MCU Software Team - * @note - * - * Copyright (C) 2018 Shanghai Eastsoft Microelectronics Co., Ltd. ALL rights reserved. - * - ************************************************************************************** - */ - -#ifndef __DAC_H__ -#define __DAC_H__ - - -/******************************************************************************/ -/* 设备特殊寄存器结构定义 */ -/******************************************************************************/ - -/* 允许匿名结构和匿名联合 */ -/* #pragma anon_unions */ - -/****************** Bit definition for DAC_CON register ************************/ - -#define DAC_CON_T_SEL_POSS 9U -#define DAC_CON_T_SEL_POSE 13U -#define DAC_CON_T_SEL_MSK BITS(DAC_CON_T_SEL_POSS,DAC_CON_T_SEL_POSE) - -#define DAC_CON_TRIEN_POS 8U -#define DAC_CON_TRIEN_MSK BIT(DAC_CON_TRIEN_POS) - -#define DAC_CON_MAMP_POSS 3U -#define DAC_CON_MAMP_POSE 6U -#define DAC_CON_MAMP_MSK BITS(DAC_CON_MAMP_POSS,DAC_CON_MAMP_POSE) - -#define DAC_CON_WAVE_POSS 1U -#define DAC_CON_WAVE_POSE 2U -#define DAC_CON_WAVE_MSK BITS(DAC_CON_WAVE_POSS,DAC_CON_WAVE_POSE) - -#define DAC_CON_INVREN_POS 0U -#define DAC_CON_INVREN_MSK BIT(DAC_CON_INVREN_POS) - -/****************** Bit definition for DAC_DIV register ************************/ - -#define DAC_DIV_DIV_VALUE_POSS 0U -#define DAC_DIV_DIV_VALUE_POSE 15U -#define DAC_DIV_DIV_VALUE_MSK BITS(DAC_DIV_DIV_VALUE_POSS,DAC_DIV_DIV_VALUE_POSE) - -/****************** Bit definition for DAC_STAT register ************************/ - -#define DAC_STAT_TX_FULL_POS 1U -#define DAC_STAT_TX_FULL_MSK BIT(DAC_STAT_TX_FULL_POS) - -#define DAC_STAT_BUSY_POS 0U -#define DAC_STAT_BUSY_MSK BIT(DAC_STAT_BUSY_POS) - -/****************** Bit definition for DAC_EN register ************************/ - -#define DAC_EN_DAC_EN_POS 0U -#define DAC_EN_DAC_EN_MSK BIT(DAC_EN_DAC_EN_POS) - -/****************** Bit definition for DAC_DMAC register ************************/ - -#define DAC_DMAC_TXDMAEN_POS 0U -#define DAC_DMAC_TXDMAEN_MSK BIT(DAC_DMAC_TXDMAEN_POS) - -/****************** Bit definition for DAC_TRIG register ************************/ - -#define DAC_TRIG_S_TRIG_POS 0U -#define DAC_TRIG_S_TRIG_MSK BIT(DAC_TRIG_S_TRIG_POS) - -/****************** Bit definition for DAC_DATA register ************************/ - -#define DAC_DATA_TXDATA_POSS 0U -#define DAC_DATA_TXDATA_POSE 11U -#define DAC_DATA_TXDATA_MSK BITS(DAC_DATA_TXDATA_POSS,DAC_DATA_TXDATA_POSE) - -typedef struct -{ - __IO uint32_t CON; - __IO uint32_t DIV; - __I uint32_t STAT; - __IO uint32_t EN; - __IO uint32_t DMAC; - __O uint32_t TRIG; - __IO uint32_t DATA; -} DAC_TypeDef; - - - - - -#endif diff --git a/bsp/essemi/es32f0271/libraries/CMSIS/Device/EastSoft/ES32F0271/Include/ES32F0271/reg_dma.h b/bsp/essemi/es32f0271/libraries/CMSIS/Device/EastSoft/ES32F0271/Include/ES32F0271/reg_dma.h deleted file mode 100644 index bead8afcdb..0000000000 --- a/bsp/essemi/es32f0271/libraries/CMSIS/Device/EastSoft/ES32F0271/Include/ES32F0271/reg_dma.h +++ /dev/null @@ -1,825 +0,0 @@ -/** - ************************************************************************************** - * @file REG_DMA.h - * @brief DMA Head File - * - * @version V0.01 - * @date 12/5/2018 - * @author Eastsoft MCU Software Team - * @note - * - * Copyright (C) 2018 Shanghai Eastsoft Microelectronics Co., Ltd. ALL rights reserved. - * - ************************************************************************************** - */ - -#ifndef __DMA_H__ -#define __DMA_H__ - - -/******************************************************************************/ -/* 设备特殊寄存器结构定义 */ -/******************************************************************************/ - -/* 允许匿名结构和匿名联合 */ -/* #pragma anon_unions */ - -/****************** Bit definition for DMA_IER register ************************/ - -#define DMA_IER_CH5TABIE_POS 11U -#define DMA_IER_CH5TABIE_MSK BIT(DMA_IER_CH5TABIE_POS) - -#define DMA_IER_CH5BTDIE_POS 10U -#define DMA_IER_CH5BTDIE_MSK BIT(DMA_IER_CH5BTDIE_POS) - -#define DMA_IER_CH4TABIE_POS 9U -#define DMA_IER_CH4TABIE_MSK BIT(DMA_IER_CH4TABIE_POS) - -#define DMA_IER_CH4BTDIE_POS 8U -#define DMA_IER_CH4BTDIE_MSK BIT(DMA_IER_CH4BTDIE_POS) - -#define DMA_IER_CH3TABIE_POS 7U -#define DMA_IER_CH3TABIE_MSK BIT(DMA_IER_CH3TABIE_POS) - -#define DMA_IER_CH3BTDIE_POS 6U -#define DMA_IER_CH3BTDIE_MSK BIT(DMA_IER_CH3BTDIE_POS) - -#define DMA_IER_CH2TABIE_POS 5U -#define DMA_IER_CH2TABIE_MSK BIT(DMA_IER_CH2TABIE_POS) - -#define DMA_IER_CH2BTDIE_POS 4U -#define DMA_IER_CH2BTDIE_MSK BIT(DMA_IER_CH2BTDIE_POS) - -#define DMA_IER_CH1TABIE_POS 3U -#define DMA_IER_CH1TABIE_MSK BIT(DMA_IER_CH1TABIE_POS) - -#define DMA_IER_CH1BTDIE_POS 2U -#define DMA_IER_CH1BTDIE_MSK BIT(DMA_IER_CH1BTDIE_POS) - -#define DMA_IER_CH0TABIE_POS 1U -#define DMA_IER_CH0TABIE_MSK BIT(DMA_IER_CH0TABIE_POS) - -#define DMA_IER_CH0BTDIE_POS 0U -#define DMA_IER_CH0BTDIE_MSK BIT(DMA_IER_CH0BTDIE_POS) - -/****************** Bit definition for DMA_IDR register ************************/ - -#define DMA_IDR_CH5TABID_POS 11U -#define DMA_IDR_CH5TABID_MSK BIT(DMA_IDR_CH5TABID_POS) - -#define DMA_IDR_CH5BTDID_POS 10U -#define DMA_IDR_CH5BTDID_MSK BIT(DMA_IDR_CH5BTDID_POS) - -#define DMA_IDR_CH4TABID_POS 9U -#define DMA_IDR_CH4TABID_MSK BIT(DMA_IDR_CH4TABID_POS) - -#define DMA_IDR_CH4BTDID_POS 8U -#define DMA_IDR_CH4BTDID_MSK BIT(DMA_IDR_CH4BTDID_POS) - -#define DMA_IDR_CH3TABID_POS 7U -#define DMA_IDR_CH3TABID_MSK BIT(DMA_IDR_CH3TABID_POS) - -#define DMA_IDR_CH3BTDID_POS 6U -#define DMA_IDR_CH3BTDID_MSK BIT(DMA_IDR_CH3BTDID_POS) - -#define DMA_IDR_CH2TABID_POS 5U -#define DMA_IDR_CH2TABID_MSK BIT(DMA_IDR_CH2TABID_POS) - -#define DMA_IDR_CH2BTDID_POS 4U -#define DMA_IDR_CH2BTDID_MSK BIT(DMA_IDR_CH2BTDID_POS) - -#define DMA_IDR_CH1TABID_POS 3U -#define DMA_IDR_CH1TABID_MSK BIT(DMA_IDR_CH1TABID_POS) - -#define DMA_IDR_CH1BTDID_POS 2U -#define DMA_IDR_CH1BTDID_MSK BIT(DMA_IDR_CH1BTDID_POS) - -#define DMA_IDR_CH0TABID_POS 1U -#define DMA_IDR_CH0TABID_MSK BIT(DMA_IDR_CH0TABID_POS) - -#define DMA_IDR_CH0BTDID_POS 0U -#define DMA_IDR_CH0BTDID_MSK BIT(DMA_IDR_CH0BTDID_POS) - -/****************** Bit definition for DMA_IVS register ************************/ - -#define DMA_IVS_CH5TABIVS_POS 11U -#define DMA_IVS_CH5TABIVS_MSK BIT(DMA_IVS_CH5TABIVS_POS) - -#define DMA_IVS_CH5BTDIVS_POS 10U -#define DMA_IVS_CH5BTDIVS_MSK BIT(DMA_IVS_CH5BTDIVS_POS) - -#define DMA_IVS_CH4TABIVS_POS 9U -#define DMA_IVS_CH4TABIVS_MSK BIT(DMA_IVS_CH4TABIVS_POS) - -#define DMA_IVS_CH4BTDIVS_POS 8U -#define DMA_IVS_CH4BTDIVS_MSK BIT(DMA_IVS_CH4BTDIVS_POS) - -#define DMA_IVS_CH3TABIVS_POS 7U -#define DMA_IVS_CH3TABIVS_MSK BIT(DMA_IVS_CH3TABIVS_POS) - -#define DMA_IVS_CH3BTDIVS_POS 6U -#define DMA_IVS_CH3BTDIVS_MSK BIT(DMA_IVS_CH3BTDIVS_POS) - -#define DMA_IVS_CH2TABIVS_POS 5U -#define DMA_IVS_CH2TABIVS_MSK BIT(DMA_IVS_CH2TABIVS_POS) - -#define DMA_IVS_CH2BTDIVS_POS 4U -#define DMA_IVS_CH2BTDIVS_MSK BIT(DMA_IVS_CH2BTDIVS_POS) - -#define DMA_IVS_CH1TABIVS_POS 3U -#define DMA_IVS_CH1TABIVS_MSK BIT(DMA_IVS_CH1TABIVS_POS) - -#define DMA_IVS_CH1BTDIVS_POS 2U -#define DMA_IVS_CH1BTDIVS_MSK BIT(DMA_IVS_CH1BTDIVS_POS) - -#define DMA_IVS_CH0TABIVS_POS 1U -#define DMA_IVS_CH0TABIVS_MSK BIT(DMA_IVS_CH0TABIVS_POS) - -#define DMA_IVS_CH0BTDIVS_POS 0U -#define DMA_IVS_CH0BTDIVS_MSK BIT(DMA_IVS_CH0BTDIVS_POS) - -/****************** Bit definition for DMA_RIF register ************************/ - -#define DMA_RIF_CH5TABRIF_POS 11U -#define DMA_RIF_CH5TABRIF_MSK BIT(DMA_RIF_CH5TABRIF_POS) - -#define DMA_RIF_CH5BTDRIF_POS 10U -#define DMA_RIF_CH5BTDRIF_MSK BIT(DMA_RIF_CH5BTDRIF_POS) - -#define DMA_RIF_CH4TABRIF_POS 9U -#define DMA_RIF_CH4TABRIF_MSK BIT(DMA_RIF_CH4TABRIF_POS) - -#define DMA_RIF_CH4BTDRIF_POS 8U -#define DMA_RIF_CH4BTDRIF_MSK BIT(DMA_RIF_CH4BTDRIF_POS) - -#define DMA_RIF_CH3TABRIF_POS 7U -#define DMA_RIF_CH3TABRIF_MSK BIT(DMA_RIF_CH3TABRIF_POS) - -#define DMA_RIF_CH3BTDRIF_POS 6U -#define DMA_RIF_CH3BTDRIF_MSK BIT(DMA_RIF_CH3BTDRIF_POS) - -#define DMA_RIF_CH2TABRIF_POS 5U -#define DMA_RIF_CH2TABRIF_MSK BIT(DMA_RIF_CH2TABRIF_POS) - -#define DMA_RIF_CH2BTDRIF_POS 4U -#define DMA_RIF_CH2BTDRIF_MSK BIT(DMA_RIF_CH2BTDRIF_POS) - -#define DMA_RIF_CH1TABRIF_POS 3U -#define DMA_RIF_CH1TABRIF_MSK BIT(DMA_RIF_CH1TABRIF_POS) - -#define DMA_RIF_CH1BTDRIF_POS 2U -#define DMA_RIF_CH1BTDRIF_MSK BIT(DMA_RIF_CH1BTDRIF_POS) - -#define DMA_RIF_CH0TABRIF_POS 1U -#define DMA_RIF_CH0TABRIF_MSK BIT(DMA_RIF_CH0TABRIF_POS) - -#define DMA_RIF_CH0BTDRIF_POS 0U -#define DMA_RIF_CH0BTDRIF_MSK BIT(DMA_RIF_CH0BTDRIF_POS) - -/****************** Bit definition for DMA_IFM register ************************/ - -#define DMA_IFM_CH5TABIFM_POS 11U -#define DMA_IFM_CH5TABIFM_MSK BIT(DMA_IFM_CH5TABIFM_POS) - -#define DMA_IFM_CH5BTDIFM_POS 10U -#define DMA_IFM_CH5BTDIFM_MSK BIT(DMA_IFM_CH5BTDIFM_POS) - -#define DMA_IFM_CH4TABIFM_POS 9U -#define DMA_IFM_CH4TABIFM_MSK BIT(DMA_IFM_CH4TABIFM_POS) - -#define DMA_IFM_CH4BTDIFM_POS 8U -#define DMA_IFM_CH4BTDIFM_MSK BIT(DMA_IFM_CH4BTDIFM_POS) - -#define DMA_IFM_CH3TABIFM_POS 7U -#define DMA_IFM_CH3TABIFM_MSK BIT(DMA_IFM_CH3TABIFM_POS) - -#define DMA_IFM_CH3BTDIFM_POS 6U -#define DMA_IFM_CH3BTDIFM_MSK BIT(DMA_IFM_CH3BTDIFM_POS) - -#define DMA_IFM_CH2TABIFM_POS 5U -#define DMA_IFM_CH2TABIFM_MSK BIT(DMA_IFM_CH2TABIFM_POS) - -#define DMA_IFM_CH2BTDIFM_POS 4U -#define DMA_IFM_CH2BTDIFM_MSK BIT(DMA_IFM_CH2BTDIFM_POS) - -#define DMA_IFM_CH1TABIFM_POS 3U -#define DMA_IFM_CH1TABIFM_MSK BIT(DMA_IFM_CH1TABIFM_POS) - -#define DMA_IFM_CH1BTDIFM_POS 2U -#define DMA_IFM_CH1BTDIFM_MSK BIT(DMA_IFM_CH1BTDIFM_POS) - -#define DMA_IFM_CH0TABIFM_POS 1U -#define DMA_IFM_CH0TABIFM_MSK BIT(DMA_IFM_CH0TABIFM_POS) - -#define DMA_IFM_CH0BTDIFM_POS 0U -#define DMA_IFM_CH0BTDIFM_MSK BIT(DMA_IFM_CH0BTDIFM_POS) - -/****************** Bit definition for DMA_ICR register ************************/ - -#define DMA_ICR_CH5TABICR_POS 11U -#define DMA_ICR_CH5TABICR_MSK BIT(DMA_ICR_CH5TABICR_POS) - -#define DMA_ICR_CH5BTDICR_POS 10U -#define DMA_ICR_CH5BTDICR_MSK BIT(DMA_ICR_CH5BTDICR_POS) - -#define DMA_ICR_CH4TABICR_POS 9U -#define DMA_ICR_CH4TABICR_MSK BIT(DMA_ICR_CH4TABICR_POS) - -#define DMA_ICR_CH4BTDICR_POS 8U -#define DMA_ICR_CH4BTDICR_MSK BIT(DMA_ICR_CH4BTDICR_POS) - -#define DMA_ICR_CH3TABICR_POS 7U -#define DMA_ICR_CH3TABICR_MSK BIT(DMA_ICR_CH3TABICR_POS) - -#define DMA_ICR_CH3BTDICR_POS 6U -#define DMA_ICR_CH3BTDICR_MSK BIT(DMA_ICR_CH3BTDICR_POS) - -#define DMA_ICR_CH2TABICR_POS 5U -#define DMA_ICR_CH2TABICR_MSK BIT(DMA_ICR_CH2TABICR_POS) - -#define DMA_ICR_CH2BTDICR_POS 4U -#define DMA_ICR_CH2BTDICR_MSK BIT(DMA_ICR_CH2BTDICR_POS) - -#define DMA_ICR_CH1TABICR_POS 3U -#define DMA_ICR_CH1TABICR_MSK BIT(DMA_ICR_CH1TABICR_POS) - -#define DMA_ICR_CH1BTDICR_POS 2U -#define DMA_ICR_CH1BTDICR_MSK BIT(DMA_ICR_CH1BTDICR_POS) - -#define DMA_ICR_CH0TABICR_POS 1U -#define DMA_ICR_CH0TABICR_MSK BIT(DMA_ICR_CH0TABICR_POS) - -#define DMA_ICR_CH0BTDICR_POS 0U -#define DMA_ICR_CH0BTDICR_MSK BIT(DMA_ICR_CH0BTDICR_POS) - -/****************** Bit definition for DMA_EMSG register ************************/ - -#define DMA_EMSG_CH5PFSER_POS 23U -#define DMA_EMSG_CH5PFSER_MSK BIT(DMA_EMSG_CH5PFSER_POS) - -#define DMA_EMSG_CH5PFOV_POS 22U -#define DMA_EMSG_CH5PFOV_MSK BIT(DMA_EMSG_CH5PFOV_POS) - -#define DMA_EMSG_CH5SETBUER_POS 21U -#define DMA_EMSG_CH5SETBUER_MSK BIT(DMA_EMSG_CH5SETBUER_POS) - -#define DMA_EMSG_CH5SETBCER_POS 20U -#define DMA_EMSG_CH5SETBCER_MSK BIT(DMA_EMSG_CH5SETBCER_POS) - -#define DMA_EMSG_CH4PFSER_POS 19U -#define DMA_EMSG_CH4PFSER_MSK BIT(DMA_EMSG_CH4PFSER_POS) - -#define DMA_EMSG_CH4PFOV_POS 18U -#define DMA_EMSG_CH4PFOV_MSK BIT(DMA_EMSG_CH4PFOV_POS) - -#define DMA_EMSG_CH4SETBUER_POS 17U -#define DMA_EMSG_CH4SETBUER_MSK BIT(DMA_EMSG_CH4SETBUER_POS) - -#define DMA_EMSG_CH4SETBCER_POS 16U -#define DMA_EMSG_CH4SETBCER_MSK BIT(DMA_EMSG_CH4SETBCER_POS) - -#define DMA_EMSG_CH3PFSER_POS 15U -#define DMA_EMSG_CH3PFSER_MSK BIT(DMA_EMSG_CH3PFSER_POS) - -#define DMA_EMSG_CH3PFOV_POS 14U -#define DMA_EMSG_CH3PFOV_MSK BIT(DMA_EMSG_CH3PFOV_POS) - -#define DMA_EMSG_CH3SETBUER_POS 13U -#define DMA_EMSG_CH3SETBUER_MSK BIT(DMA_EMSG_CH3SETBUER_POS) - -#define DMA_EMSG_CH3SETBCER_POS 12U -#define DMA_EMSG_CH3SETBCER_MSK BIT(DMA_EMSG_CH3SETBCER_POS) - -#define DMA_EMSG_CH2PFSER_POS 11U -#define DMA_EMSG_CH2PFSER_MSK BIT(DMA_EMSG_CH2PFSER_POS) - -#define DMA_EMSG_CH2PFOV_POS 10U -#define DMA_EMSG_CH2PFOV_MSK BIT(DMA_EMSG_CH2PFOV_POS) - -#define DMA_EMSG_CH2SETBUER_POS 9U -#define DMA_EMSG_CH2SETBUER_MSK BIT(DMA_EMSG_CH2SETBUER_POS) - -#define DMA_EMSG_CH2SETBCER_POS 8U -#define DMA_EMSG_CH2SETBCER_MSK BIT(DMA_EMSG_CH2SETBCER_POS) - -#define DMA_EMSG_CH1PFSER_POS 7U -#define DMA_EMSG_CH1PFSER_MSK BIT(DMA_EMSG_CH1PFSER_POS) - -#define DMA_EMSG_CH1PFOV_POS 6U -#define DMA_EMSG_CH1PFOV_MSK BIT(DMA_EMSG_CH1PFOV_POS) - -#define DMA_EMSG_CH1SETBUER_POS 5U -#define DMA_EMSG_CH1SETBUER_MSK BIT(DMA_EMSG_CH1SETBUER_POS) - -#define DMA_EMSG_CH1SETBCER_POS 4U -#define DMA_EMSG_CH1SETBCER_MSK BIT(DMA_EMSG_CH1SETBCER_POS) - -#define DMA_EMSG_CH0PFSER_POS 3U -#define DMA_EMSG_CH0PFSER_MSK BIT(DMA_EMSG_CH0PFSER_POS) - -#define DMA_EMSG_CH0PFOV_POS 2U -#define DMA_EMSG_CH0PFOV_MSK BIT(DMA_EMSG_CH0PFOV_POS) - -#define DMA_EMSG_CH0SETBUER_POS 1U -#define DMA_EMSG_CH0SETBUER_MSK BIT(DMA_EMSG_CH0SETBUER_POS) - -#define DMA_EMSG_CH0SETBCER_POS 0U -#define DMA_EMSG_CH0SETBCER_MSK BIT(DMA_EMSG_CH0SETBCER_POS) - -/****************** Bit definition for DMA_CSR0 register ************************/ - -#define DMA_CSR0_DINCOS_POS 30U -#define DMA_CSR0_DINCOS_MSK BIT(DMA_CSR0_DINCOS_POS) - -#define DMA_CSR0_DBUSEL_POSS 27U -#define DMA_CSR0_DBUSEL_POSE 29U -#define DMA_CSR0_DBUSEL_MSK BITS(DMA_CSR0_DBUSEL_POSS,DMA_CSR0_DBUSEL_POSE) - -#define DMA_CSR0_DDWSEL_POSS 25U -#define DMA_CSR0_DDWSEL_POSE 26U -#define DMA_CSR0_DDWSEL_MSK BITS(DMA_CSR0_DDWSEL_POSS,DMA_CSR0_DDWSEL_POSE) - -#define DMA_CSR0_DINC_POS 24U -#define DMA_CSR0_DINC_MSK BIT(DMA_CSR0_DINC_POS) - -#define DMA_CSR0_SINCOS_POS 22U -#define DMA_CSR0_SINCOS_MSK BIT(DMA_CSR0_SINCOS_POS) - -#define DMA_CSR0_SBUSEL_POSS 19U -#define DMA_CSR0_SBUSEL_POSE 21U -#define DMA_CSR0_SBUSEL_MSK BITS(DMA_CSR0_SBUSEL_POSS,DMA_CSR0_SBUSEL_POSE) - -#define DMA_CSR0_SDWSEL_POSS 17U -#define DMA_CSR0_SDWSEL_POSE 18U -#define DMA_CSR0_SDWSEL_MSK BITS(DMA_CSR0_SDWSEL_POSS,DMA_CSR0_SDWSEL_POSE) - -#define DMA_CSR0_SINC_POS 16U -#define DMA_CSR0_SINC_MSK BIT(DMA_CSR0_SINC_POS) - -#define DMA_CSR0_PHSS_POSS 9U -#define DMA_CSR0_PHSS_POSE 15U -#define DMA_CSR0_PHSS_MSK BITS(DMA_CSR0_PHSS_POSS,DMA_CSR0_PHSS_POSE) - -#define DMA_CSR0_CHPRI_POSS 6U -#define DMA_CSR0_CHPRI_POSE 8U -#define DMA_CSR0_CHPRI_MSK BITS(DMA_CSR0_CHPRI_POSS,DMA_CSR0_CHPRI_POSE) - -#define DMA_CSR0_MODESEL_POSS 4U -#define DMA_CSR0_MODESEL_POSE 5U -#define DMA_CSR0_MODESEL_MSK BITS(DMA_CSR0_MODESEL_POSS,DMA_CSR0_MODESEL_POSE) - -#define DMA_CSR0_DIRMDEN_POS 3U -#define DMA_CSR0_DIRMDEN_MSK BIT(DMA_CSR0_DIRMDEN_POS) - -#define DMA_CSR0_PFCTRL_POS 2U -#define DMA_CSR0_PFCTRL_MSK BIT(DMA_CSR0_PFCTRL_POS) - -#define DMA_CSR0_CIRC_POS 1U -#define DMA_CSR0_CIRC_MSK BIT(DMA_CSR0_CIRC_POS) - -#define DMA_CSR0_CHEN_POS 0U -#define DMA_CSR0_CHEN_MSK BIT(DMA_CSR0_CHEN_POS) - -/****************** Bit definition for DMA_SAR0 register ************************/ - -#define DMA_SAR0_SAR_POSS 0U -#define DMA_SAR0_SAR_POSE 31U -#define DMA_SAR0_SAR_MSK BITS(DMA_SAR0_SAR_POSS,DMA_SAR0_SAR_POSE) - -/****************** Bit definition for DMA_DAR0 register ************************/ - -#define DMA_DAR0_DAR_POSS 0U -#define DMA_DAR0_DAR_POSE 31U -#define DMA_DAR0_DAR_MSK BITS(DMA_DAR0_DAR_POSS,DMA_DAR0_DAR_POSE) - -/****************** Bit definition for DMA_BCR0 register ************************/ - -#define DMA_BCR0_CBCR_POSS 16U -#define DMA_BCR0_CBCR_POSE 31U -#define DMA_BCR0_CBCR_MSK BITS(DMA_BCR0_CBCR_POSS,DMA_BCR0_CBCR_POSE) - -#define DMA_BCR0_BCR_POSS 0U -#define DMA_BCR0_BCR_POSE 15U -#define DMA_BCR0_BCR_MSK BITS(DMA_BCR0_BCR_POSS,DMA_BCR0_BCR_POSE) - -/****************** Bit definition for DMA_CSR1 register ************************/ - -#define DMA_CSR1_DINCOS_POS 30U -#define DMA_CSR1_DINCOS_MSK BIT(DMA_CSR1_DINCOS_POS) - -#define DMA_CSR1_DBUSEL_POSS 27U -#define DMA_CSR1_DBUSEL_POSE 29U -#define DMA_CSR1_DBUSEL_MSK BITS(DMA_CSR1_DBUSEL_POSS,DMA_CSR1_DBUSEL_POSE) - -#define DMA_CSR1_DDWSEL_POSS 25U -#define DMA_CSR1_DDWSEL_POSE 26U -#define DMA_CSR1_DDWSEL_MSK BITS(DMA_CSR1_DDWSEL_POSS,DMA_CSR1_DDWSEL_POSE) - -#define DMA_CSR1_DINC_POS 24U -#define DMA_CSR1_DINC_MSK BIT(DMA_CSR1_DINC_POS) - -#define DMA_CSR1_SINCOS_POS 22U -#define DMA_CSR1_SINCOS_MSK BIT(DMA_CSR1_SINCOS_POS) - -#define DMA_CSR1_SBUSEL_POSS 19U -#define DMA_CSR1_SBUSEL_POSE 21U -#define DMA_CSR1_SBUSEL_MSK BITS(DMA_CSR1_SBUSEL_POSS,DMA_CSR1_SBUSEL_POSE) - -#define DMA_CSR1_SDWSEL_POSS 17U -#define DMA_CSR1_SDWSEL_POSE 18U -#define DMA_CSR1_SDWSEL_MSK BITS(DMA_CSR1_SDWSEL_POSS,DMA_CSR1_SDWSEL_POSE) - -#define DMA_CSR1_SINC_POS 16U -#define DMA_CSR1_SINC_MSK BIT(DMA_CSR1_SINC_POS) - -#define DMA_CSR1_PHSS_POSS 9U -#define DMA_CSR1_PHSS_POSE 15U -#define DMA_CSR1_PHSS_MSK BITS(DMA_CSR1_PHSS_POSS,DMA_CSR1_PHSS_POSE) - -#define DMA_CSR1_CHPRI_POSS 6U -#define DMA_CSR1_CHPRI_POSE 8U -#define DMA_CSR1_CHPRI_MSK BITS(DMA_CSR1_CHPRI_POSS,DMA_CSR1_CHPRI_POSE) - -#define DMA_CSR1_MODESEL_POSS 4U -#define DMA_CSR1_MODESEL_POSE 5U -#define DMA_CSR1_MODESEL_MSK BITS(DMA_CSR1_MODESEL_POSS,DMA_CSR1_MODESEL_POSE) - -#define DMA_CSR1_DIRMDEN_POS 3U -#define DMA_CSR1_DIRMDEN_MSK BIT(DMA_CSR1_DIRMDEN_POS) - -#define DMA_CSR1_PFCTRL_POS 2U -#define DMA_CSR1_PFCTRL_MSK BIT(DMA_CSR1_PFCTRL_POS) - -#define DMA_CSR1_CIRC_POS 1U -#define DMA_CSR1_CIRC_MSK BIT(DMA_CSR1_CIRC_POS) - -#define DMA_CSR1_CHEN_POS 0U -#define DMA_CSR1_CHEN_MSK BIT(DMA_CSR1_CHEN_POS) - -/****************** Bit definition for DMA_SAR1 register ************************/ - -#define DMA_SAR1_SAR_POSS 0U -#define DMA_SAR1_SAR_POSE 31U -#define DMA_SAR1_SAR_MSK BITS(DMA_SAR1_SAR_POSS,DMA_SAR1_SAR_POSE) - -/****************** Bit definition for DMA_DAR1 register ************************/ - -#define DMA_DAR1_DAR_POSS 0U -#define DMA_DAR1_DAR_POSE 31U -#define DMA_DAR1_DAR_MSK BITS(DMA_DAR1_DAR_POSS,DMA_DAR1_DAR_POSE) - -/****************** Bit definition for DMA_BCR1 register ************************/ - -#define DMA_BCR1_CBCR_POSS 16U -#define DMA_BCR1_CBCR_POSE 31U -#define DMA_BCR1_CBCR_MSK BITS(DMA_BCR1_CBCR_POSS,DMA_BCR1_CBCR_POSE) - -#define DMA_BCR1_BCR_POSS 0U -#define DMA_BCR1_BCR_POSE 15U -#define DMA_BCR1_BCR_MSK BITS(DMA_BCR1_BCR_POSS,DMA_BCR1_BCR_POSE) - -/****************** Bit definition for DMA_CSR2 register ************************/ - -#define DMA_CSR2_DINCOS_POS 30U -#define DMA_CSR2_DINCOS_MSK BIT(DMA_CSR2_DINCOS_POS) - -#define DMA_CSR2_DBUSEL_POSS 27U -#define DMA_CSR2_DBUSEL_POSE 29U -#define DMA_CSR2_DBUSEL_MSK BITS(DMA_CSR2_DBUSEL_POSS,DMA_CSR2_DBUSEL_POSE) - -#define DMA_CSR2_DDWSEL_POSS 25U -#define DMA_CSR2_DDWSEL_POSE 26U -#define DMA_CSR2_DDWSEL_MSK BITS(DMA_CSR2_DDWSEL_POSS,DMA_CSR2_DDWSEL_POSE) - -#define DMA_CSR2_DINC_POS 24U -#define DMA_CSR2_DINC_MSK BIT(DMA_CSR2_DINC_POS) - -#define DMA_CSR2_SINCOS_POS 22U -#define DMA_CSR2_SINCOS_MSK BIT(DMA_CSR2_SINCOS_POS) - -#define DMA_CSR2_SBUSEL_POSS 19U -#define DMA_CSR2_SBUSEL_POSE 21U -#define DMA_CSR2_SBUSEL_MSK BITS(DMA_CSR2_SBUSEL_POSS,DMA_CSR2_SBUSEL_POSE) - -#define DMA_CSR2_SDWSEL_POSS 17U -#define DMA_CSR2_SDWSEL_POSE 18U -#define DMA_CSR2_SDWSEL_MSK BITS(DMA_CSR2_SDWSEL_POSS,DMA_CSR2_SDWSEL_POSE) - -#define DMA_CSR2_SINC_POS 16U -#define DMA_CSR2_SINC_MSK BIT(DMA_CSR2_SINC_POS) - -#define DMA_CSR2_PHSS_POSS 9U -#define DMA_CSR2_PHSS_POSE 15U -#define DMA_CSR2_PHSS_MSK BITS(DMA_CSR2_PHSS_POSS,DMA_CSR2_PHSS_POSE) - -#define DMA_CSR2_CHPRI_POSS 6U -#define DMA_CSR2_CHPRI_POSE 8U -#define DMA_CSR2_CHPRI_MSK BITS(DMA_CSR2_CHPRI_POSS,DMA_CSR2_CHPRI_POSE) - -#define DMA_CSR2_MODESEL_POSS 4U -#define DMA_CSR2_MODESEL_POSE 5U -#define DMA_CSR2_MODESEL_MSK BITS(DMA_CSR2_MODESEL_POSS,DMA_CSR2_MODESEL_POSE) - -#define DMA_CSR2_DIRMDEN_POS 3U -#define DMA_CSR2_DIRMDEN_MSK BIT(DMA_CSR2_DIRMDEN_POS) - -#define DMA_CSR2_PFCTRL_POS 2U -#define DMA_CSR2_PFCTRL_MSK BIT(DMA_CSR2_PFCTRL_POS) - -#define DMA_CSR2_CIRC_POS 1U -#define DMA_CSR2_CIRC_MSK BIT(DMA_CSR2_CIRC_POS) - -#define DMA_CSR2_CHEN_POS 0U -#define DMA_CSR2_CHEN_MSK BIT(DMA_CSR2_CHEN_POS) - -/****************** Bit definition for DMA_SAR2 register ************************/ - -#define DMA_SAR2_SAR_POSS 0U -#define DMA_SAR2_SAR_POSE 31U -#define DMA_SAR2_SAR_MSK BITS(DMA_SAR2_SAR_POSS,DMA_SAR2_SAR_POSE) - -/****************** Bit definition for DMA_DAR2 register ************************/ - -#define DMA_DAR2_DAR_POSS 0U -#define DMA_DAR2_DAR_POSE 31U -#define DMA_DAR2_DAR_MSK BITS(DMA_DAR2_DAR_POSS,DMA_DAR2_DAR_POSE) - -/****************** Bit definition for DMA_BCR2 register ************************/ - -#define DMA_BCR2_CBCR_POSS 16U -#define DMA_BCR2_CBCR_POSE 31U -#define DMA_BCR2_CBCR_MSK BITS(DMA_BCR2_CBCR_POSS,DMA_BCR2_CBCR_POSE) - -#define DMA_BCR2_BCR_POSS 0U -#define DMA_BCR2_BCR_POSE 15U -#define DMA_BCR2_BCR_MSK BITS(DMA_BCR2_BCR_POSS,DMA_BCR2_BCR_POSE) - -/****************** Bit definition for DMA_CSR3 register ************************/ - -#define DMA_CSR3_DINCOS_POS 30U -#define DMA_CSR3_DINCOS_MSK BIT(DMA_CSR3_DINCOS_POS) - -#define DMA_CSR3_DBUSEL_POSS 27U -#define DMA_CSR3_DBUSEL_POSE 29U -#define DMA_CSR3_DBUSEL_MSK BITS(DMA_CSR3_DBUSEL_POSS,DMA_CSR3_DBUSEL_POSE) - -#define DMA_CSR3_DDWSEL_POSS 25U -#define DMA_CSR3_DDWSEL_POSE 26U -#define DMA_CSR3_DDWSEL_MSK BITS(DMA_CSR3_DDWSEL_POSS,DMA_CSR3_DDWSEL_POSE) - -#define DMA_CSR3_DINC_POS 24U -#define DMA_CSR3_DINC_MSK BIT(DMA_CSR3_DINC_POS) - -#define DMA_CSR3_SINCOS_POS 22U -#define DMA_CSR3_SINCOS_MSK BIT(DMA_CSR3_SINCOS_POS) - -#define DMA_CSR3_SBUSEL_POSS 19U -#define DMA_CSR3_SBUSEL_POSE 21U -#define DMA_CSR3_SBUSEL_MSK BITS(DMA_CSR3_SBUSEL_POSS,DMA_CSR3_SBUSEL_POSE) - -#define DMA_CSR3_SDWSEL_POSS 17U -#define DMA_CSR3_SDWSEL_POSE 18U -#define DMA_CSR3_SDWSEL_MSK BITS(DMA_CSR3_SDWSEL_POSS,DMA_CSR3_SDWSEL_POSE) - -#define DMA_CSR3_SINC_POS 16U -#define DMA_CSR3_SINC_MSK BIT(DMA_CSR3_SINC_POS) - -#define DMA_CSR3_PHSS_POSS 9U -#define DMA_CSR3_PHSS_POSE 15U -#define DMA_CSR3_PHSS_MSK BITS(DMA_CSR3_PHSS_POSS,DMA_CSR3_PHSS_POSE) - -#define DMA_CSR3_CHPRI_POSS 6U -#define DMA_CSR3_CHPRI_POSE 8U -#define DMA_CSR3_CHPRI_MSK BITS(DMA_CSR3_CHPRI_POSS,DMA_CSR3_CHPRI_POSE) - -#define DMA_CSR3_MODESEL_POSS 4U -#define DMA_CSR3_MODESEL_POSE 5U -#define DMA_CSR3_MODESEL_MSK BITS(DMA_CSR3_MODESEL_POSS,DMA_CSR3_MODESEL_POSE) - -#define DMA_CSR3_DIRMDEN_POS 3U -#define DMA_CSR3_DIRMDEN_MSK BIT(DMA_CSR3_DIRMDEN_POS) - -#define DMA_CSR3_PFCTRL_POS 2U -#define DMA_CSR3_PFCTRL_MSK BIT(DMA_CSR3_PFCTRL_POS) - -#define DMA_CSR3_CIRC_POS 1U -#define DMA_CSR3_CIRC_MSK BIT(DMA_CSR3_CIRC_POS) - -#define DMA_CSR3_CHEN_POS 0U -#define DMA_CSR3_CHEN_MSK BIT(DMA_CSR3_CHEN_POS) - -/****************** Bit definition for DMA_SAR3 register ************************/ - -#define DMA_SAR3_SAR_POSS 0U -#define DMA_SAR3_SAR_POSE 31U -#define DMA_SAR3_SAR_MSK BITS(DMA_SAR3_SAR_POSS,DMA_SAR3_SAR_POSE) - -/****************** Bit definition for DMA_DAR3 register ************************/ - -#define DMA_DAR3_DAR_POSS 0U -#define DMA_DAR3_DAR_POSE 31U -#define DMA_DAR3_DAR_MSK BITS(DMA_DAR3_DAR_POSS,DMA_DAR3_DAR_POSE) - -/****************** Bit definition for DMA_BCR3 register ************************/ - -#define DMA_BCR3_CBCR_POSS 16U -#define DMA_BCR3_CBCR_POSE 31U -#define DMA_BCR3_CBCR_MSK BITS(DMA_BCR3_CBCR_POSS,DMA_BCR3_CBCR_POSE) - -#define DMA_BCR3_BCR_POSS 0U -#define DMA_BCR3_BCR_POSE 15U -#define DMA_BCR3_BCR_MSK BITS(DMA_BCR3_BCR_POSS,DMA_BCR3_BCR_POSE) - -/****************** Bit definition for DMA_CSR4 register ************************/ - -#define DMA_CSR4_DINCOS_POS 30U -#define DMA_CSR4_DINCOS_MSK BIT(DMA_CSR4_DINCOS_POS) - -#define DMA_CSR4_DBUSEL_POSS 27U -#define DMA_CSR4_DBUSEL_POSE 29U -#define DMA_CSR4_DBUSEL_MSK BITS(DMA_CSR4_DBUSEL_POSS,DMA_CSR4_DBUSEL_POSE) - -#define DMA_CSR4_DDWSEL_POSS 25U -#define DMA_CSR4_DDWSEL_POSE 26U -#define DMA_CSR4_DDWSEL_MSK BITS(DMA_CSR4_DDWSEL_POSS,DMA_CSR4_DDWSEL_POSE) - -#define DMA_CSR4_DINC_POS 24U -#define DMA_CSR4_DINC_MSK BIT(DMA_CSR4_DINC_POS) - -#define DMA_CSR4_SINCOS_POS 22U -#define DMA_CSR4_SINCOS_MSK BIT(DMA_CSR4_SINCOS_POS) - -#define DMA_CSR4_SBUSEL_POSS 19U -#define DMA_CSR4_SBUSEL_POSE 21U -#define DMA_CSR4_SBUSEL_MSK BITS(DMA_CSR4_SBUSEL_POSS,DMA_CSR4_SBUSEL_POSE) - -#define DMA_CSR4_SDWSEL_POSS 17U -#define DMA_CSR4_SDWSEL_POSE 18U -#define DMA_CSR4_SDWSEL_MSK BITS(DMA_CSR4_SDWSEL_POSS,DMA_CSR4_SDWSEL_POSE) - -#define DMA_CSR4_SINC_POS 16U -#define DMA_CSR4_SINC_MSK BIT(DMA_CSR4_SINC_POS) - -#define DMA_CSR4_PHSS_POSS 9U -#define DMA_CSR4_PHSS_POSE 15U -#define DMA_CSR4_PHSS_MSK BITS(DMA_CSR4_PHSS_POSS,DMA_CSR4_PHSS_POSE) - -#define DMA_CSR4_CHPRI_POSS 6U -#define DMA_CSR4_CHPRI_POSE 8U -#define DMA_CSR4_CHPRI_MSK BITS(DMA_CSR4_CHPRI_POSS,DMA_CSR4_CHPRI_POSE) - -#define DMA_CSR4_MODESEL_POSS 4U -#define DMA_CSR4_MODESEL_POSE 5U -#define DMA_CSR4_MODESEL_MSK BITS(DMA_CSR4_MODESEL_POSS,DMA_CSR4_MODESEL_POSE) - -#define DMA_CSR4_DIRMDEN_POS 3U -#define DMA_CSR4_DIRMDEN_MSK BIT(DMA_CSR4_DIRMDEN_POS) - -#define DMA_CSR4_PFCTRL_POS 2U -#define DMA_CSR4_PFCTRL_MSK BIT(DMA_CSR4_PFCTRL_POS) - -#define DMA_CSR4_CIRC_POS 1U -#define DMA_CSR4_CIRC_MSK BIT(DMA_CSR4_CIRC_POS) - -#define DMA_CSR4_CHEN_POS 0U -#define DMA_CSR4_CHEN_MSK BIT(DMA_CSR4_CHEN_POS) - -/****************** Bit definition for DMA_SAR4 register ************************/ - -#define DMA_SAR4_SAR_POSS 0U -#define DMA_SAR4_SAR_POSE 31U -#define DMA_SAR4_SAR_MSK BITS(DMA_SAR4_SAR_POSS,DMA_SAR4_SAR_POSE) - -/****************** Bit definition for DMA_DAR4 register ************************/ - -#define DMA_DAR4_DAR_POSS 0U -#define DMA_DAR4_DAR_POSE 31U -#define DMA_DAR4_DAR_MSK BITS(DMA_DAR4_DAR_POSS,DMA_DAR4_DAR_POSE) - -/****************** Bit definition for DMA_BCR4 register ************************/ - -#define DMA_BCR4_CBCR_POSS 16U -#define DMA_BCR4_CBCR_POSE 31U -#define DMA_BCR4_CBCR_MSK BITS(DMA_BCR4_CBCR_POSS,DMA_BCR4_CBCR_POSE) - -#define DMA_BCR4_BCR_POSS 0U -#define DMA_BCR4_BCR_POSE 15U -#define DMA_BCR4_BCR_MSK BITS(DMA_BCR4_BCR_POSS,DMA_BCR4_BCR_POSE) - -/****************** Bit definition for DMA_CSR5 register ************************/ - -#define DMA_CSR5_DINCOS_POS 30U -#define DMA_CSR5_DINCOS_MSK BIT(DMA_CSR5_DINCOS_POS) - -#define DMA_CSR5_DBUSEL_POSS 27U -#define DMA_CSR5_DBUSEL_POSE 29U -#define DMA_CSR5_DBUSEL_MSK BITS(DMA_CSR5_DBUSEL_POSS,DMA_CSR5_DBUSEL_POSE) - -#define DMA_CSR5_DDWSEL_POSS 25U -#define DMA_CSR5_DDWSEL_POSE 26U -#define DMA_CSR5_DDWSEL_MSK BITS(DMA_CSR5_DDWSEL_POSS,DMA_CSR5_DDWSEL_POSE) - -#define DMA_CSR5_DINC_POS 24U -#define DMA_CSR5_DINC_MSK BIT(DMA_CSR5_DINC_POS) - -#define DMA_CSR5_SINCOS_POS 22U -#define DMA_CSR5_SINCOS_MSK BIT(DMA_CSR5_SINCOS_POS) - -#define DMA_CSR5_SBUSEL_POSS 19U -#define DMA_CSR5_SBUSEL_POSE 21U -#define DMA_CSR5_SBUSEL_MSK BITS(DMA_CSR5_SBUSEL_POSS,DMA_CSR5_SBUSEL_POSE) - -#define DMA_CSR5_SDWSEL_POSS 17U -#define DMA_CSR5_SDWSEL_POSE 18U -#define DMA_CSR5_SDWSEL_MSK BITS(DMA_CSR5_SDWSEL_POSS,DMA_CSR5_SDWSEL_POSE) - -#define DMA_CSR5_SINC_POS 16U -#define DMA_CSR5_SINC_MSK BIT(DMA_CSR5_SINC_POS) - -#define DMA_CSR5_PHSS_POSS 9U -#define DMA_CSR5_PHSS_POSE 15U -#define DMA_CSR5_PHSS_MSK BITS(DMA_CSR5_PHSS_POSS,DMA_CSR5_PHSS_POSE) - -#define DMA_CSR5_CHPRI_POSS 6U -#define DMA_CSR5_CHPRI_POSE 8U -#define DMA_CSR5_CHPRI_MSK BITS(DMA_CSR5_CHPRI_POSS,DMA_CSR5_CHPRI_POSE) - -#define DMA_CSR5_MODESEL_POSS 4U -#define DMA_CSR5_MODESEL_POSE 5U -#define DMA_CSR5_MODESEL_MSK BITS(DMA_CSR5_MODESEL_POSS,DMA_CSR5_MODESEL_POSE) - -#define DMA_CSR5_DIRMDEN_POS 3U -#define DMA_CSR5_DIRMDEN_MSK BIT(DMA_CSR5_DIRMDEN_POS) - -#define DMA_CSR5_PFCTRL_POS 2U -#define DMA_CSR5_PFCTRL_MSK BIT(DMA_CSR5_PFCTRL_POS) - -#define DMA_CSR5_CIRC_POS 1U -#define DMA_CSR5_CIRC_MSK BIT(DMA_CSR5_CIRC_POS) - -#define DMA_CSR5_CHEN_POS 0U -#define DMA_CSR5_CHEN_MSK BIT(DMA_CSR5_CHEN_POS) - -/****************** Bit definition for DMA_SAR5 register ************************/ - -#define DMA_SAR5_SAR_POSS 0U -#define DMA_SAR5_SAR_POSE 31U -#define DMA_SAR5_SAR_MSK BITS(DMA_SAR5_SAR_POSS,DMA_SAR5_SAR_POSE) - -/****************** Bit definition for DMA_DAR5 register ************************/ - -#define DMA_DAR5_DAR_POSS 0U -#define DMA_DAR5_DAR_POSE 31U -#define DMA_DAR5_DAR_MSK BITS(DMA_DAR5_DAR_POSS,DMA_DAR5_DAR_POSE) - -/****************** Bit definition for DMA_BCR5 register ************************/ - -#define DMA_BCR5_CBCR_POSS 16U -#define DMA_BCR5_CBCR_POSE 31U -#define DMA_BCR5_CBCR_MSK BITS(DMA_BCR5_CBCR_POSS,DMA_BCR5_CBCR_POSE) - -#define DMA_BCR5_BCR_POSS 0U -#define DMA_BCR5_BCR_POSE 15U -#define DMA_BCR5_BCR_MSK BITS(DMA_BCR5_BCR_POSS,DMA_BCR5_BCR_POSE) - -typedef struct -{ - __O uint32_t IER; - __O uint32_t IDR; - __I uint32_t IVS; - __I uint32_t RIF; - __I uint32_t IFM; - __O uint32_t ICR; - __I uint32_t EMSG; - uint32_t RESERVED0 ; - __IO uint32_t CSR0; - __IO uint32_t SAR0; - __IO uint32_t DAR0; - __IO uint32_t BCR0; - __IO uint32_t CSR1; - __IO uint32_t SAR1; - __IO uint32_t DAR1; - __IO uint32_t BCR1; - __IO uint32_t CSR2; - __IO uint32_t SAR2; - __IO uint32_t DAR2; - __IO uint32_t BCR2; - __IO uint32_t CSR3; - __IO uint32_t SAR3; - __IO uint32_t DAR3; - __IO uint32_t BCR3; - __IO uint32_t CSR4; - __IO uint32_t SAR4; - __IO uint32_t DAR4; - __IO uint32_t BCR4; - __IO uint32_t CSR5; - __IO uint32_t SAR5; - __IO uint32_t DAR5; - __IO uint32_t BCR5; -} DMA_TypeDef; - - - - - -#endif diff --git a/bsp/essemi/es32f0271/libraries/CMSIS/Device/EastSoft/ES32F0271/Include/ES32F0271/reg_exti.h b/bsp/essemi/es32f0271/libraries/CMSIS/Device/EastSoft/ES32F0271/Include/ES32F0271/reg_exti.h deleted file mode 100644 index 92a8228889..0000000000 --- a/bsp/essemi/es32f0271/libraries/CMSIS/Device/EastSoft/ES32F0271/Include/ES32F0271/reg_exti.h +++ /dev/null @@ -1,809 +0,0 @@ -/** - ************************************************************************************** - * @file REG_EXTI.h - * @brief EXTI Head File - * - * @version V0.01 - * @data 12/3/2018 - * @author Eastsoft MCU Software Team - * @note - * - * Copyright (C) 2018 Shanghai Eastsoft Microelectronics Co., Ltd. ALL rights reserved. - * - ************************************************************************************** - */ - -#ifndef __EXTI_H__ -#define __EXTI_H__ - - -/******************************************************************************/ -/* 设备特殊寄存器结构定义 */ -/******************************************************************************/ - -/* 允许匿名结构和匿名联合 */ -/* #pragma anon_unions */ - -/****************** Bit definition for EXTI_IER register ************************/ - -#define EXTI_IER_WAKEUP_POS 21U -#define EXTI_IER_WAKEUP_MSK BIT(EXTI_IER_WAKEUP_POS) - -#define EXTI_IER_PVD0_POS 20U -#define EXTI_IER_PVD0_MSK BIT(EXTI_IER_PVD0_POS) - -#define EXTI_IER_CMP2_POS 17U -#define EXTI_IER_CMP2_MSK BIT(EXTI_IER_CMP2_POS) - -#define EXTI_IER_CMP1_POS 16U -#define EXTI_IER_CMP1_MSK BIT(EXTI_IER_CMP1_POS) - -#define EXTI_IER_GPIO15_POS 15U -#define EXTI_IER_GPIO15_MSK BIT(EXTI_IER_GPIO15_POS) - -#define EXTI_IER_GPIO14_POS 14U -#define EXTI_IER_GPIO14_MSK BIT(EXTI_IER_GPIO14_POS) - -#define EXTI_IER_GPIO13_POS 13U -#define EXTI_IER_GPIO13_MSK BIT(EXTI_IER_GPIO13_POS) - -#define EXTI_IER_GPIO12_POS 12U -#define EXTI_IER_GPIO12_MSK BIT(EXTI_IER_GPIO12_POS) - -#define EXTI_IER_GPIO11_POS 11U -#define EXTI_IER_GPIO11_MSK BIT(EXTI_IER_GPIO11_POS) - -#define EXTI_IER_GPIO10_POS 10U -#define EXTI_IER_GPIO10_MSK BIT(EXTI_IER_GPIO10_POS) - -#define EXTI_IER_GPIO9_POS 9U -#define EXTI_IER_GPIO9_MSK BIT(EXTI_IER_GPIO9_POS) - -#define EXTI_IER_GPIO8_POS 8U -#define EXTI_IER_GPIO8_MSK BIT(EXTI_IER_GPIO8_POS) - -#define EXTI_IER_GPIO7_POS 7U -#define EXTI_IER_GPIO7_MSK BIT(EXTI_IER_GPIO7_POS) - -#define EXTI_IER_GPIO6_POS 6U -#define EXTI_IER_GPIO6_MSK BIT(EXTI_IER_GPIO6_POS) - -#define EXTI_IER_GPIO5_POS 5U -#define EXTI_IER_GPIO5_MSK BIT(EXTI_IER_GPIO5_POS) - -#define EXTI_IER_GPIO4_POS 4U -#define EXTI_IER_GPIO4_MSK BIT(EXTI_IER_GPIO4_POS) - -#define EXTI_IER_GPIO3_POS 3U -#define EXTI_IER_GPIO3_MSK BIT(EXTI_IER_GPIO3_POS) - -#define EXTI_IER_GPIO2_POS 2U -#define EXTI_IER_GPIO2_MSK BIT(EXTI_IER_GPIO2_POS) - -#define EXTI_IER_GPIO1_POS 1U -#define EXTI_IER_GPIO1_MSK BIT(EXTI_IER_GPIO1_POS) - -#define EXTI_IER_GPIO0_POS 0U -#define EXTI_IER_GPIO0_MSK BIT(EXTI_IER_GPIO0_POS) - -/****************** Bit definition for EXTI_IDR register ************************/ - -#define EXTI_IDR_WAKEUP_POS 21U -#define EXTI_IDR_WAKEUP_MSK BIT(EXTI_IDR_WAKEUP_POS) - -#define EXTI_IDR_PVD0_POS 20U -#define EXTI_IDR_PVD0_MSK BIT(EXTI_IDR_PVD0_POS) - -#define EXTI_IDR_CMP2_POS 17U -#define EXTI_IDR_CMP2_MSK BIT(EXTI_IDR_CMP2_POS) - -#define EXTI_IDR_CMP1_POS 16U -#define EXTI_IDR_CMP1_MSK BIT(EXTI_IDR_CMP1_POS) - -#define EXTI_IDR_GPIO15_POS 15U -#define EXTI_IDR_GPIO15_MSK BIT(EXTI_IDR_GPIO15_POS) - -#define EXTI_IDR_GPIO14_POS 14U -#define EXTI_IDR_GPIO14_MSK BIT(EXTI_IDR_GPIO14_POS) - -#define EXTI_IDR_GPIO13_POS 13U -#define EXTI_IDR_GPIO13_MSK BIT(EXTI_IDR_GPIO13_POS) - -#define EXTI_IDR_GPIO12_POS 12U -#define EXTI_IDR_GPIO12_MSK BIT(EXTI_IDR_GPIO12_POS) - -#define EXTI_IDR_GPIO11_POS 11U -#define EXTI_IDR_GPIO11_MSK BIT(EXTI_IDR_GPIO11_POS) - -#define EXTI_IDR_GPIO10_POS 10U -#define EXTI_IDR_GPIO10_MSK BIT(EXTI_IDR_GPIO10_POS) - -#define EXTI_IDR_GPIO9_POS 9U -#define EXTI_IDR_GPIO9_MSK BIT(EXTI_IDR_GPIO9_POS) - -#define EXTI_IDR_GPIO8_POS 8U -#define EXTI_IDR_GPIO8_MSK BIT(EXTI_IDR_GPIO8_POS) - -#define EXTI_IDR_GPIO7_POS 7U -#define EXTI_IDR_GPIO7_MSK BIT(EXTI_IDR_GPIO7_POS) - -#define EXTI_IDR_GPIO6_POS 6U -#define EXTI_IDR_GPIO6_MSK BIT(EXTI_IDR_GPIO6_POS) - -#define EXTI_IDR_GPIO5_POS 5U -#define EXTI_IDR_GPIO5_MSK BIT(EXTI_IDR_GPIO5_POS) - -#define EXTI_IDR_GPIO4_POS 4U -#define EXTI_IDR_GPIO4_MSK BIT(EXTI_IDR_GPIO4_POS) - -#define EXTI_IDR_GPIO3_POS 3U -#define EXTI_IDR_GPIO3_MSK BIT(EXTI_IDR_GPIO3_POS) - -#define EXTI_IDR_GPIO2_POS 2U -#define EXTI_IDR_GPIO2_MSK BIT(EXTI_IDR_GPIO2_POS) - -#define EXTI_IDR_GPIO1_POS 1U -#define EXTI_IDR_GPIO1_MSK BIT(EXTI_IDR_GPIO1_POS) - -#define EXTI_IDR_GPIO0_POS 0U -#define EXTI_IDR_GPIO0_MSK BIT(EXTI_IDR_GPIO0_POS) - -/****************** Bit definition for EXTI_IVS register ************************/ - -#define EXTI_IVS_WAKEUP_POS 21U -#define EXTI_IVS_WAKEUP_MSK BIT(EXTI_IVS_WAKEUP_POS) - -#define EXTI_IVS_PVD0_POS 20U -#define EXTI_IVS_PVD0_MSK BIT(EXTI_IVS_PVD0_POS) - -#define EXTI_IVS_CMP2_POS 17U -#define EXTI_IVS_CMP2_MSK BIT(EXTI_IVS_CMP2_POS) - -#define EXTI_IVS_CMP1_POS 16U -#define EXTI_IVS_CMP1_MSK BIT(EXTI_IVS_CMP1_POS) - -#define EXTI_IVS_GPIO15_POS 15U -#define EXTI_IVS_GPIO15_MSK BIT(EXTI_IVS_GPIO15_POS) - -#define EXTI_IVS_GPIO14_POS 14U -#define EXTI_IVS_GPIO14_MSK BIT(EXTI_IVS_GPIO14_POS) - -#define EXTI_IVS_GPIO13_POS 13U -#define EXTI_IVS_GPIO13_MSK BIT(EXTI_IVS_GPIO13_POS) - -#define EXTI_IVS_GPIO12_POS 12U -#define EXTI_IVS_GPIO12_MSK BIT(EXTI_IVS_GPIO12_POS) - -#define EXTI_IVS_GPIO11_POS 11U -#define EXTI_IVS_GPIO11_MSK BIT(EXTI_IVS_GPIO11_POS) - -#define EXTI_IVS_GPIO10_POS 10U -#define EXTI_IVS_GPIO10_MSK BIT(EXTI_IVS_GPIO10_POS) - -#define EXTI_IVS_GPIO9_POS 9U -#define EXTI_IVS_GPIO9_MSK BIT(EXTI_IVS_GPIO9_POS) - -#define EXTI_IVS_GPIO8_POS 8U -#define EXTI_IVS_GPIO8_MSK BIT(EXTI_IVS_GPIO8_POS) - -#define EXTI_IVS_GPIO7_POS 7U -#define EXTI_IVS_GPIO7_MSK BIT(EXTI_IVS_GPIO7_POS) - -#define EXTI_IVS_GPIO6_POS 6U -#define EXTI_IVS_GPIO6_MSK BIT(EXTI_IVS_GPIO6_POS) - -#define EXTI_IVS_GPIO5_POS 5U -#define EXTI_IVS_GPIO5_MSK BIT(EXTI_IVS_GPIO5_POS) - -#define EXTI_IVS_GPIO4_POS 4U -#define EXTI_IVS_GPIO4_MSK BIT(EXTI_IVS_GPIO4_POS) - -#define EXTI_IVS_GPIO3_POS 3U -#define EXTI_IVS_GPIO3_MSK BIT(EXTI_IVS_GPIO3_POS) - -#define EXTI_IVS_GPIO2_POS 2U -#define EXTI_IVS_GPIO2_MSK BIT(EXTI_IVS_GPIO2_POS) - -#define EXTI_IVS_GPIO1_POS 1U -#define EXTI_IVS_GPIO1_MSK BIT(EXTI_IVS_GPIO1_POS) - -#define EXTI_IVS_GPIO0_POS 0U -#define EXTI_IVS_GPIO0_MSK BIT(EXTI_IVS_GPIO0_POS) - -/****************** Bit definition for EXTI_RIF register ************************/ - -#define EXTI_RIF_WAKEUP_POS 21U -#define EXTI_RIF_WAKEUP_MSK BIT(EXTI_RIF_WAKEUP_POS) - -#define EXTI_RIF_PVD0_POS 20U -#define EXTI_RIF_PVD0_MSK BIT(EXTI_RIF_PVD0_POS) - -#define EXTI_RIF_CMP2_POS 17U -#define EXTI_RIF_CMP2_MSK BIT(EXTI_RIF_CMP2_POS) - -#define EXTI_RIF_CMP1_POS 16U -#define EXTI_RIF_CMP1_MSK BIT(EXTI_RIF_CMP1_POS) - -#define EXTI_RIF_GPIO15_POS 15U -#define EXTI_RIF_GPIO15_MSK BIT(EXTI_RIF_GPIO15_POS) - -#define EXTI_RIF_GPIO14_POS 14U -#define EXTI_RIF_GPIO14_MSK BIT(EXTI_RIF_GPIO14_POS) - -#define EXTI_RIF_GPIO13_POS 13U -#define EXTI_RIF_GPIO13_MSK BIT(EXTI_RIF_GPIO13_POS) - -#define EXTI_RIF_GPIO12_POS 12U -#define EXTI_RIF_GPIO12_MSK BIT(EXTI_RIF_GPIO12_POS) - -#define EXTI_RIF_GPIO11_POS 11U -#define EXTI_RIF_GPIO11_MSK BIT(EXTI_RIF_GPIO11_POS) - -#define EXTI_RIF_GPIO10_POS 10U -#define EXTI_RIF_GPIO10_MSK BIT(EXTI_RIF_GPIO10_POS) - -#define EXTI_RIF_GPIO9_POS 9U -#define EXTI_RIF_GPIO9_MSK BIT(EXTI_RIF_GPIO9_POS) - -#define EXTI_RIF_GPIO8_POS 8U -#define EXTI_RIF_GPIO8_MSK BIT(EXTI_RIF_GPIO8_POS) - -#define EXTI_RIF_GPIO7_POS 7U -#define EXTI_RIF_GPIO7_MSK BIT(EXTI_RIF_GPIO7_POS) - -#define EXTI_RIF_GPIO6_POS 6U -#define EXTI_RIF_GPIO6_MSK BIT(EXTI_RIF_GPIO6_POS) - -#define EXTI_RIF_GPIO5_POS 5U -#define EXTI_RIF_GPIO5_MSK BIT(EXTI_RIF_GPIO5_POS) - -#define EXTI_RIF_GPIO4_POS 4U -#define EXTI_RIF_GPIO4_MSK BIT(EXTI_RIF_GPIO4_POS) - -#define EXTI_RIF_GPIO3_POS 3U -#define EXTI_RIF_GPIO3_MSK BIT(EXTI_RIF_GPIO3_POS) - -#define EXTI_RIF_GPIO2_POS 2U -#define EXTI_RIF_GPIO2_MSK BIT(EXTI_RIF_GPIO2_POS) - -#define EXTI_RIF_GPIO1_POS 1U -#define EXTI_RIF_GPIO1_MSK BIT(EXTI_RIF_GPIO1_POS) - -#define EXTI_RIF_GPIO0_POS 0U -#define EXTI_RIF_GPIO0_MSK BIT(EXTI_RIF_GPIO0_POS) - -/****************** Bit definition for EXTI_IFM register ************************/ - -#define EXTI_IFM_WAKEUP_POS 21U -#define EXTI_IFM_WAKEUP_MSK BIT(EXTI_IFM_WAKEUP_POS) - -#define EXTI_IFM_PVD0_POS 20U -#define EXTI_IFM_PVD0_MSK BIT(EXTI_IFM_PVD0_POS) - -#define EXTI_IFM_CMP2_POS 17U -#define EXTI_IFM_CMP2_MSK BIT(EXTI_IFM_CMP2_POS) - -#define EXTI_IFM_CMP1_POS 16U -#define EXTI_IFM_CMP1_MSK BIT(EXTI_IFM_CMP1_POS) - -#define EXTI_IFM_GPIO15_POS 15U -#define EXTI_IFM_GPIO15_MSK BIT(EXTI_IFM_GPIO15_POS) - -#define EXTI_IFM_GPIO14_POS 14U -#define EXTI_IFM_GPIO14_MSK BIT(EXTI_IFM_GPIO14_POS) - -#define EXTI_IFM_GPIO13_POS 13U -#define EXTI_IFM_GPIO13_MSK BIT(EXTI_IFM_GPIO13_POS) - -#define EXTI_IFM_GPIO12_POS 12U -#define EXTI_IFM_GPIO12_MSK BIT(EXTI_IFM_GPIO12_POS) - -#define EXTI_IFM_GPIO11_POS 11U -#define EXTI_IFM_GPIO11_MSK BIT(EXTI_IFM_GPIO11_POS) - -#define EXTI_IFM_GPIO10_POS 10U -#define EXTI_IFM_GPIO10_MSK BIT(EXTI_IFM_GPIO10_POS) - -#define EXTI_IFM_GPIO9_POS 9U -#define EXTI_IFM_GPIO9_MSK BIT(EXTI_IFM_GPIO9_POS) - -#define EXTI_IFM_GPIO8_POS 8U -#define EXTI_IFM_GPIO8_MSK BIT(EXTI_IFM_GPIO8_POS) - -#define EXTI_IFM_GPIO7_POS 7U -#define EXTI_IFM_GPIO7_MSK BIT(EXTI_IFM_GPIO7_POS) - -#define EXTI_IFM_GPIO6_POS 6U -#define EXTI_IFM_GPIO6_MSK BIT(EXTI_IFM_GPIO6_POS) - -#define EXTI_IFM_GPIO5_POS 5U -#define EXTI_IFM_GPIO5_MSK BIT(EXTI_IFM_GPIO5_POS) - -#define EXTI_IFM_GPIO4_POS 4U -#define EXTI_IFM_GPIO4_MSK BIT(EXTI_IFM_GPIO4_POS) - -#define EXTI_IFM_GPIO3_POS 3U -#define EXTI_IFM_GPIO3_MSK BIT(EXTI_IFM_GPIO3_POS) - -#define EXTI_IFM_GPIO2_POS 2U -#define EXTI_IFM_GPIO2_MSK BIT(EXTI_IFM_GPIO2_POS) - -#define EXTI_IFM_GPIO1_POS 1U -#define EXTI_IFM_GPIO1_MSK BIT(EXTI_IFM_GPIO1_POS) - -#define EXTI_IFM_GPIO0_POS 0U -#define EXTI_IFM_GPIO0_MSK BIT(EXTI_IFM_GPIO0_POS) - -/****************** Bit definition for EXTI_ICR register ************************/ - -#define EXTI_ICR_WAKEUP_POS 21U -#define EXTI_ICR_WAKEUP_MSK BIT(EXTI_ICR_WAKEUP_POS) - -#define EXTI_ICR_PVD0_POS 20U -#define EXTI_ICR_PVD0_MSK BIT(EXTI_ICR_PVD0_POS) - -#define EXTI_ICR_CMP2_POS 17U -#define EXTI_ICR_CMP2_MSK BIT(EXTI_ICR_CMP2_POS) - -#define EXTI_ICR_CMP1_POS 16U -#define EXTI_ICR_CMP1_MSK BIT(EXTI_ICR_CMP1_POS) - -#define EXTI_ICR_GPIO15_POS 15U -#define EXTI_ICR_GPIO15_MSK BIT(EXTI_ICR_GPIO15_POS) - -#define EXTI_ICR_GPIO14_POS 14U -#define EXTI_ICR_GPIO14_MSK BIT(EXTI_ICR_GPIO14_POS) - -#define EXTI_ICR_GPIO13_POS 13U -#define EXTI_ICR_GPIO13_MSK BIT(EXTI_ICR_GPIO13_POS) - -#define EXTI_ICR_GPIO12_POS 12U -#define EXTI_ICR_GPIO12_MSK BIT(EXTI_ICR_GPIO12_POS) - -#define EXTI_ICR_GPIO11_POS 11U -#define EXTI_ICR_GPIO11_MSK BIT(EXTI_ICR_GPIO11_POS) - -#define EXTI_ICR_GPIO10_POS 10U -#define EXTI_ICR_GPIO10_MSK BIT(EXTI_ICR_GPIO10_POS) - -#define EXTI_ICR_GPIO9_POS 9U -#define EXTI_ICR_GPIO9_MSK BIT(EXTI_ICR_GPIO9_POS) - -#define EXTI_ICR_GPIO8_POS 8U -#define EXTI_ICR_GPIO8_MSK BIT(EXTI_ICR_GPIO8_POS) - -#define EXTI_ICR_GPIO7_POS 7U -#define EXTI_ICR_GPIO7_MSK BIT(EXTI_ICR_GPIO7_POS) - -#define EXTI_ICR_GPIO6_POS 6U -#define EXTI_ICR_GPIO6_MSK BIT(EXTI_ICR_GPIO6_POS) - -#define EXTI_ICR_GPIO5_POS 5U -#define EXTI_ICR_GPIO5_MSK BIT(EXTI_ICR_GPIO5_POS) - -#define EXTI_ICR_GPIO4_POS 4U -#define EXTI_ICR_GPIO4_MSK BIT(EXTI_ICR_GPIO4_POS) - -#define EXTI_ICR_GPIO3_POS 3U -#define EXTI_ICR_GPIO3_MSK BIT(EXTI_ICR_GPIO3_POS) - -#define EXTI_ICR_GPIO2_POS 2U -#define EXTI_ICR_GPIO2_MSK BIT(EXTI_ICR_GPIO2_POS) - -#define EXTI_ICR_GPIO1_POS 1U -#define EXTI_ICR_GPIO1_MSK BIT(EXTI_ICR_GPIO1_POS) - -#define EXTI_ICR_GPIO0_POS 0U -#define EXTI_ICR_GPIO0_MSK BIT(EXTI_ICR_GPIO0_POS) - -/****************** Bit definition for EXTI_RTS register ************************/ - -#define EXTI_RTS_WAKEUP_POS 21U -#define EXTI_RTS_WAKEUP_MSK BIT(EXTI_RTS_WAKEUP_POS) - -#define EXTI_RTS_PVD0_POS 20U -#define EXTI_RTS_PVD0_MSK BIT(EXTI_RTS_PVD0_POS) - -#define EXTI_RTS_CMP2_POS 17U -#define EXTI_RTS_CMP2_MSK BIT(EXTI_RTS_CMP2_POS) - -#define EXTI_RTS_CMP1_POS 16U -#define EXTI_RTS_CMP1_MSK BIT(EXTI_RTS_CMP1_POS) - -#define EXTI_RTS_GPIO15_POS 15U -#define EXTI_RTS_GPIO15_MSK BIT(EXTI_RTS_GPIO15_POS) - -#define EXTI_RTS_GPIO14_POS 14U -#define EXTI_RTS_GPIO14_MSK BIT(EXTI_RTS_GPIO14_POS) - -#define EXTI_RTS_GPIO13_POS 13U -#define EXTI_RTS_GPIO13_MSK BIT(EXTI_RTS_GPIO13_POS) - -#define EXTI_RTS_GPIO12_POS 12U -#define EXTI_RTS_GPIO12_MSK BIT(EXTI_RTS_GPIO12_POS) - -#define EXTI_RTS_GPIO11_POS 11U -#define EXTI_RTS_GPIO11_MSK BIT(EXTI_RTS_GPIO11_POS) - -#define EXTI_RTS_GPIO10_POS 10U -#define EXTI_RTS_GPIO10_MSK BIT(EXTI_RTS_GPIO10_POS) - -#define EXTI_RTS_GPIO9_POS 9U -#define EXTI_RTS_GPIO9_MSK BIT(EXTI_RTS_GPIO9_POS) - -#define EXTI_RTS_GPIO8_POS 8U -#define EXTI_RTS_GPIO8_MSK BIT(EXTI_RTS_GPIO8_POS) - -#define EXTI_RTS_GPIO7_POS 7U -#define EXTI_RTS_GPIO7_MSK BIT(EXTI_RTS_GPIO7_POS) - -#define EXTI_RTS_GPIO6_POS 6U -#define EXTI_RTS_GPIO6_MSK BIT(EXTI_RTS_GPIO6_POS) - -#define EXTI_RTS_GPIO5_POS 5U -#define EXTI_RTS_GPIO5_MSK BIT(EXTI_RTS_GPIO5_POS) - -#define EXTI_RTS_GPIO4_POS 4U -#define EXTI_RTS_GPIO4_MSK BIT(EXTI_RTS_GPIO4_POS) - -#define EXTI_RTS_GPIO3_POS 3U -#define EXTI_RTS_GPIO3_MSK BIT(EXTI_RTS_GPIO3_POS) - -#define EXTI_RTS_GPIO2_POS 2U -#define EXTI_RTS_GPIO2_MSK BIT(EXTI_RTS_GPIO2_POS) - -#define EXTI_RTS_GPIO1_POS 1U -#define EXTI_RTS_GPIO1_MSK BIT(EXTI_RTS_GPIO1_POS) - -#define EXTI_RTS_GPIO0_POS 0U -#define EXTI_RTS_GPIO0_MSK BIT(EXTI_RTS_GPIO0_POS) - -/****************** Bit definition for EXTI_FTS register ************************/ - -#define EXTI_FTS_WAKEUP_POS 21U -#define EXTI_FTS_WAKEUP_MSK BIT(EXTI_FTS_WAKEUP_POS) - -#define EXTI_FTS_PVD0_POS 20U -#define EXTI_FTS_PVD0_MSK BIT(EXTI_FTS_PVD0_POS) - -#define EXTI_FTS_CMP2_POS 17U -#define EXTI_FTS_CMP2_MSK BIT(EXTI_FTS_CMP2_POS) - -#define EXTI_FTS_CMP1_POS 16U -#define EXTI_FTS_CMP1_MSK BIT(EXTI_FTS_CMP1_POS) - -#define EXTI_FTS_GPIO15_POS 15U -#define EXTI_FTS_GPIO15_MSK BIT(EXTI_FTS_GPIO15_POS) - -#define EXTI_FTS_GPIO14_POS 14U -#define EXTI_FTS_GPIO14_MSK BIT(EXTI_FTS_GPIO14_POS) - -#define EXTI_FTS_GPIO13_POS 13U -#define EXTI_FTS_GPIO13_MSK BIT(EXTI_FTS_GPIO13_POS) - -#define EXTI_FTS_GPIO12_POS 12U -#define EXTI_FTS_GPIO12_MSK BIT(EXTI_FTS_GPIO12_POS) - -#define EXTI_FTS_GPIO11_POS 11U -#define EXTI_FTS_GPIO11_MSK BIT(EXTI_FTS_GPIO11_POS) - -#define EXTI_FTS_GPIO10_POS 10U -#define EXTI_FTS_GPIO10_MSK BIT(EXTI_FTS_GPIO10_POS) - -#define EXTI_FTS_GPIO9_POS 9U -#define EXTI_FTS_GPIO9_MSK BIT(EXTI_FTS_GPIO9_POS) - -#define EXTI_FTS_GPIO8_POS 8U -#define EXTI_FTS_GPIO8_MSK BIT(EXTI_FTS_GPIO8_POS) - -#define EXTI_FTS_GPIO7_POS 7U -#define EXTI_FTS_GPIO7_MSK BIT(EXTI_FTS_GPIO7_POS) - -#define EXTI_FTS_GPIO6_POS 6U -#define EXTI_FTS_GPIO6_MSK BIT(EXTI_FTS_GPIO6_POS) - -#define EXTI_FTS_GPIO5_POS 5U -#define EXTI_FTS_GPIO5_MSK BIT(EXTI_FTS_GPIO5_POS) - -#define EXTI_FTS_GPIO4_POS 4U -#define EXTI_FTS_GPIO4_MSK BIT(EXTI_FTS_GPIO4_POS) - -#define EXTI_FTS_GPIO3_POS 3U -#define EXTI_FTS_GPIO3_MSK BIT(EXTI_FTS_GPIO3_POS) - -#define EXTI_FTS_GPIO2_POS 2U -#define EXTI_FTS_GPIO2_MSK BIT(EXTI_FTS_GPIO2_POS) - -#define EXTI_FTS_GPIO1_POS 1U -#define EXTI_FTS_GPIO1_MSK BIT(EXTI_FTS_GPIO1_POS) - -#define EXTI_FTS_GPIO0_POS 0U -#define EXTI_FTS_GPIO0_MSK BIT(EXTI_FTS_GPIO0_POS) - -/****************** Bit definition for EXTI_SWI register ************************/ - -#define EXTI_SWI_WAKEUP_POS 21U -#define EXTI_SWI_WAKEUP_MSK BIT(EXTI_SWI_WAKEUP_POS) - -#define EXTI_SWI_PVD0_POS 20U -#define EXTI_SWI_PVD0_MSK BIT(EXTI_SWI_PVD0_POS) - -#define EXTI_SWI_CMP2_POS 17U -#define EXTI_SWI_CMP2_MSK BIT(EXTI_SWI_CMP2_POS) - -#define EXTI_SWI_CMP1_POS 16U -#define EXTI_SWI_CMP1_MSK BIT(EXTI_SWI_CMP1_POS) - -#define EXTI_SWI_GPIO15_POS 15U -#define EXTI_SWI_GPIO15_MSK BIT(EXTI_SWI_GPIO15_POS) - -#define EXTI_SWI_GPIO14_POS 14U -#define EXTI_SWI_GPIO14_MSK BIT(EXTI_SWI_GPIO14_POS) - -#define EXTI_SWI_GPIO13_POS 13U -#define EXTI_SWI_GPIO13_MSK BIT(EXTI_SWI_GPIO13_POS) - -#define EXTI_SWI_GPIO12_POS 12U -#define EXTI_SWI_GPIO12_MSK BIT(EXTI_SWI_GPIO12_POS) - -#define EXTI_SWI_GPIO11_POS 11U -#define EXTI_SWI_GPIO11_MSK BIT(EXTI_SWI_GPIO11_POS) - -#define EXTI_SWI_GPIO10_POS 10U -#define EXTI_SWI_GPIO10_MSK BIT(EXTI_SWI_GPIO10_POS) - -#define EXTI_SWI_GPIO9_POS 9U -#define EXTI_SWI_GPIO9_MSK BIT(EXTI_SWI_GPIO9_POS) - -#define EXTI_SWI_GPIO8_POS 8U -#define EXTI_SWI_GPIO8_MSK BIT(EXTI_SWI_GPIO8_POS) - -#define EXTI_SWI_GPIO7_POS 7U -#define EXTI_SWI_GPIO7_MSK BIT(EXTI_SWI_GPIO7_POS) - -#define EXTI_SWI_GPIO6_POS 6U -#define EXTI_SWI_GPIO6_MSK BIT(EXTI_SWI_GPIO6_POS) - -#define EXTI_SWI_GPIO5_POS 5U -#define EXTI_SWI_GPIO5_MSK BIT(EXTI_SWI_GPIO5_POS) - -#define EXTI_SWI_GPIO4_POS 4U -#define EXTI_SWI_GPIO4_MSK BIT(EXTI_SWI_GPIO4_POS) - -#define EXTI_SWI_GPIO3_POS 3U -#define EXTI_SWI_GPIO3_MSK BIT(EXTI_SWI_GPIO3_POS) - -#define EXTI_SWI_GPIO2_POS 2U -#define EXTI_SWI_GPIO2_MSK BIT(EXTI_SWI_GPIO2_POS) - -#define EXTI_SWI_GPIO1_POS 1U -#define EXTI_SWI_GPIO1_MSK BIT(EXTI_SWI_GPIO1_POS) - -#define EXTI_SWI_GPIO0_POS 0U -#define EXTI_SWI_GPIO0_MSK BIT(EXTI_SWI_GPIO0_POS) - -/****************** Bit definition for EXTI_ADTE register ************************/ - -#define EXTI_ADTE_WAKEUP_POS 21U -#define EXTI_ADTE_WAKEUP_MSK BIT(EXTI_ADTE_WAKEUP_POS) - -#define EXTI_ADTE_PVD0_POS 20U -#define EXTI_ADTE_PVD0_MSK BIT(EXTI_ADTE_PVD0_POS) - -#define EXTI_ADTE_CMP2_POS 17U -#define EXTI_ADTE_CMP2_MSK BIT(EXTI_ADTE_CMP2_POS) - -#define EXTI_ADTE_CMP1_POS 16U -#define EXTI_ADTE_CMP1_MSK BIT(EXTI_ADTE_CMP1_POS) - -#define EXTI_ADTE_GPIO15_POS 15U -#define EXTI_ADTE_GPIO15_MSK BIT(EXTI_ADTE_GPIO15_POS) - -#define EXTI_ADTE_GPIO14_POS 14U -#define EXTI_ADTE_GPIO14_MSK BIT(EXTI_ADTE_GPIO14_POS) - -#define EXTI_ADTE_GPIO13_POS 13U -#define EXTI_ADTE_GPIO13_MSK BIT(EXTI_ADTE_GPIO13_POS) - -#define EXTI_ADTE_GPIO12_POS 12U -#define EXTI_ADTE_GPIO12_MSK BIT(EXTI_ADTE_GPIO12_POS) - -#define EXTI_ADTE_GPIO11_POS 11U -#define EXTI_ADTE_GPIO11_MSK BIT(EXTI_ADTE_GPIO11_POS) - -#define EXTI_ADTE_GPIO10_POS 10U -#define EXTI_ADTE_GPIO10_MSK BIT(EXTI_ADTE_GPIO10_POS) - -#define EXTI_ADTE_GPIO9_POS 9U -#define EXTI_ADTE_GPIO9_MSK BIT(EXTI_ADTE_GPIO9_POS) - -#define EXTI_ADTE_GPIO8_POS 8U -#define EXTI_ADTE_GPIO8_MSK BIT(EXTI_ADTE_GPIO8_POS) - -#define EXTI_ADTE_GPIO7_POS 7U -#define EXTI_ADTE_GPIO7_MSK BIT(EXTI_ADTE_GPIO7_POS) - -#define EXTI_ADTE_GPIO6_POS 6U -#define EXTI_ADTE_GPIO6_MSK BIT(EXTI_ADTE_GPIO6_POS) - -#define EXTI_ADTE_GPIO5_POS 5U -#define EXTI_ADTE_GPIO5_MSK BIT(EXTI_ADTE_GPIO5_POS) - -#define EXTI_ADTE_GPIO4_POS 4U -#define EXTI_ADTE_GPIO4_MSK BIT(EXTI_ADTE_GPIO4_POS) - -#define EXTI_ADTE_GPIO3_POS 3U -#define EXTI_ADTE_GPIO3_MSK BIT(EXTI_ADTE_GPIO3_POS) - -#define EXTI_ADTE_GPIO2_POS 2U -#define EXTI_ADTE_GPIO2_MSK BIT(EXTI_ADTE_GPIO2_POS) - -#define EXTI_ADTE_GPIO1_POS 1U -#define EXTI_ADTE_GPIO1_MSK BIT(EXTI_ADTE_GPIO1_POS) - -#define EXTI_ADTE_GPIO0_POS 0U -#define EXTI_ADTE_GPIO0_MSK BIT(EXTI_ADTE_GPIO0_POS) - -/****************** Bit definition for EXTI_DB register ************************/ - -#define EXTI_DB_WAKEUP_POS 21U -#define EXTI_DB_WAKEUP_MSK BIT(EXTI_DB_WAKEUP_POS) - -#define EXTI_DB_PVD0_POS 20U -#define EXTI_DB_PVD0_MSK BIT(EXTI_DB_PVD0_POS) - -#define EXTI_DB_CMP2_POS 17U -#define EXTI_DB_CMP2_MSK BIT(EXTI_DB_CMP2_POS) - -#define EXTI_DB_CMP1_POS 16U -#define EXTI_DB_CMP1_MSK BIT(EXTI_DB_CMP1_POS) - -#define EXTI_DB_GPIO15_POS 15U -#define EXTI_DB_GPIO15_MSK BIT(EXTI_DB_GPIO15_POS) - -#define EXTI_DB_GPIO14_POS 14U -#define EXTI_DB_GPIO14_MSK BIT(EXTI_DB_GPIO14_POS) - -#define EXTI_DB_GPIO13_POS 13U -#define EXTI_DB_GPIO13_MSK BIT(EXTI_DB_GPIO13_POS) - -#define EXTI_DB_GPIO12_POS 12U -#define EXTI_DB_GPIO12_MSK BIT(EXTI_DB_GPIO12_POS) - -#define EXTI_DB_GPIO11_POS 11U -#define EXTI_DB_GPIO11_MSK BIT(EXTI_DB_GPIO11_POS) - -#define EXTI_DB_GPIO10_POS 10U -#define EXTI_DB_GPIO10_MSK BIT(EXTI_DB_GPIO10_POS) - -#define EXTI_DB_GPIO9_POS 9U -#define EXTI_DB_GPIO9_MSK BIT(EXTI_DB_GPIO9_POS) - -#define EXTI_DB_GPIO8_POS 8U -#define EXTI_DB_GPIO8_MSK BIT(EXTI_DB_GPIO8_POS) - -#define EXTI_DB_GPIO7_POS 7U -#define EXTI_DB_GPIO7_MSK BIT(EXTI_DB_GPIO7_POS) - -#define EXTI_DB_GPIO6_POS 6U -#define EXTI_DB_GPIO6_MSK BIT(EXTI_DB_GPIO6_POS) - -#define EXTI_DB_GPIO5_POS 5U -#define EXTI_DB_GPIO5_MSK BIT(EXTI_DB_GPIO5_POS) - -#define EXTI_DB_GPIO4_POS 4U -#define EXTI_DB_GPIO4_MSK BIT(EXTI_DB_GPIO4_POS) - -#define EXTI_DB_GPIO3_POS 3U -#define EXTI_DB_GPIO3_MSK BIT(EXTI_DB_GPIO3_POS) - -#define EXTI_DB_GPIO2_POS 2U -#define EXTI_DB_GPIO2_MSK BIT(EXTI_DB_GPIO2_POS) - -#define EXTI_DB_GPIO1_POS 1U -#define EXTI_DB_GPIO1_MSK BIT(EXTI_DB_GPIO1_POS) - -#define EXTI_DB_GPIO0_POS 0U -#define EXTI_DB_GPIO0_MSK BIT(EXTI_DB_GPIO0_POS) - -/****************** Bit definition for EXTI_DBCON register ************************/ - -#define EXTI_DBCON_DBPRE_POSS 8U -#define EXTI_DBCON_DBPRE_POSE 15U -#define EXTI_DBCON_DBPRE_MSK BITS(EXTI_DBCON_DBPRE_POSS,EXTI_DBCON_DBPRE_POSE) - -#define EXTI_DBCON_DBCNT_POSS 0U -#define EXTI_DBCON_DBCNT_POSE 2U -#define EXTI_DBCON_DBCNT_MSK BITS(EXTI_DBCON_DBCNT_POSS,EXTI_DBCON_DBCNT_POSE) - -/****************** Bit definition for EXTI_ICFG1 register ************************/ - -#define EXTI_ICFG1_GPIO7_POSS 28U -#define EXTI_ICFG1_GPIO7_POSE 31U -#define EXTI_ICFG1_GPIO7_MSK BITS(EXTI_ICFG1_GPIO7_POSS,EXTI_ICFG1_GPIO7_POSE) - -#define EXTI_ICFG1_GPIO6_POSS 24U -#define EXTI_ICFG1_GPIO6_POSE 27U -#define EXTI_ICFG1_GPIO6_MSK BITS(EXTI_ICFG1_GPIO6_POSS,EXTI_ICFG1_GPIO6_POSE) - -#define EXTI_ICFG1_GPIO5_POSS 20U -#define EXTI_ICFG1_GPIO5_POSE 23U -#define EXTI_ICFG1_GPIO5_MSK BITS(EXTI_ICFG1_GPIO5_POSS,EXTI_ICFG1_GPIO5_POSE) - -#define EXTI_ICFG1_GPIO4_POSS 16U -#define EXTI_ICFG1_GPIO4_POSE 19U -#define EXTI_ICFG1_GPIO4_MSK BITS(EXTI_ICFG1_GPIO4_POSS,EXTI_ICFG1_GPIO4_POSE) - -#define EXTI_ICFG1_GPIO3_POSS 12U -#define EXTI_ICFG1_GPIO3_POSE 15U -#define EXTI_ICFG1_GPIO3_MSK BITS(EXTI_ICFG1_GPIO3_POSS,EXTI_ICFG1_GPIO3_POSE) - -#define EXTI_ICFG1_GPIO2_POSS 8U -#define EXTI_ICFG1_GPIO2_POSE 11U -#define EXTI_ICFG1_GPIO2_MSK BITS(EXTI_ICFG1_GPIO2_POSS,EXTI_ICFG1_GPIO2_POSE) - -#define EXTI_ICFG1_GPIO1_POSS 4U -#define EXTI_ICFG1_GPIO1_POSE 7U -#define EXTI_ICFG1_GPIO1_MSK BITS(EXTI_ICFG1_GPIO1_POSS,EXTI_ICFG1_GPIO1_POSE) - -#define EXTI_ICFG1_GPIO0_POSS 0U -#define EXTI_ICFG1_GPIO0_POSE 3U -#define EXTI_ICFG1_GPIO0_MSK BITS(EXTI_ICFG1_GPIO0_POSS,EXTI_ICFG1_GPIO0_POSE) - -/****************** Bit definition for EXTI_ICFG2 register ************************/ - -#define EXTI_ICFG2_GPIO15_POSS 28U -#define EXTI_ICFG2_GPIO15_POSE 31U -#define EXTI_ICFG2_GPIO15_MSK BITS(EXTI_ICFG2_GPIO15_POSS,EXTI_ICFG2_GPIO15_POSE) - -#define EXTI_ICFG2_GPIO14_POSS 24U -#define EXTI_ICFG2_GPIO14_POSE 27U -#define EXTI_ICFG2_GPIO14_MSK BITS(EXTI_ICFG2_GPIO14_POSS,EXTI_ICFG2_GPIO14_POSE) - -#define EXTI_ICFG2_GPIO13_POSS 20U -#define EXTI_ICFG2_GPIO13_POSE 23U -#define EXTI_ICFG2_GPIO13_MSK BITS(EXTI_ICFG2_GPIO13_POSS,EXTI_ICFG2_GPIO13_POSE) - -#define EXTI_ICFG2_GPIO12_POSS 16U -#define EXTI_ICFG2_GPIO12_POSE 19U -#define EXTI_ICFG2_GPIO12_MSK BITS(EXTI_ICFG2_GPIO12_POSS,EXTI_ICFG2_GPIO12_POSE) - -#define EXTI_ICFG2_GPIO11_POSS 12U -#define EXTI_ICFG2_GPIO11_POSE 15U -#define EXTI_ICFG2_GPIO11_MSK BITS(EXTI_ICFG2_GPIO11_POSS,EXTI_ICFG2_GPIO11_POSE) - -#define EXTI_ICFG2_GPIO10_POSS 8U -#define EXTI_ICFG2_GPIO10_POSE 11U -#define EXTI_ICFG2_GPIO10_MSK BITS(EXTI_ICFG2_GPIO10_POSS,EXTI_ICFG2_GPIO10_POSE) - -#define EXTI_ICFG2_GPIO9_POSS 4U -#define EXTI_ICFG2_GPIO9_POSE 7U -#define EXTI_ICFG2_GPIO9_MSK BITS(EXTI_ICFG2_GPIO9_POSS,EXTI_ICFG2_GPIO9_POSE) - -#define EXTI_ICFG2_GPIO8_POSS 0U -#define EXTI_ICFG2_GPIO8_POSE 3U -#define EXTI_ICFG2_GPIO8_MSK BITS(EXTI_ICFG2_GPIO8_POSS,EXTI_ICFG2_GPIO8_POSE) - -typedef struct -{ - __O uint32_t IER; - __O uint32_t IDR; - __I uint32_t IVS; - __I uint32_t RIF; - __I uint32_t IFM; - __O uint32_t ICR; - __IO uint32_t RTS; - __IO uint32_t FTS; - __O uint32_t SWI; - __IO uint32_t ADTE; - __IO uint32_t DB; - __IO uint32_t DBCON; - __IO uint32_t ICFG1; - __IO uint32_t ICFG2; -} EXTI_TypeDef; - - - - - -#endif diff --git a/bsp/essemi/es32f0271/libraries/CMSIS/Device/EastSoft/ES32F0271/Include/ES32F0271/reg_fc.h b/bsp/essemi/es32f0271/libraries/CMSIS/Device/EastSoft/ES32F0271/Include/ES32F0271/reg_fc.h deleted file mode 100644 index 0b9850cb4e..0000000000 --- a/bsp/essemi/es32f0271/libraries/CMSIS/Device/EastSoft/ES32F0271/Include/ES32F0271/reg_fc.h +++ /dev/null @@ -1,181 +0,0 @@ -/** - ************************************************************************************** - * @file REG_FC.h - * @brief FC Head File - * - * @version V0.01 - * @data 12/3/2018 - * @author Eastsoft MCU Software Team - * @note - * - * Copyright (C) 2018 Shanghai Eastsoft Microelectronics Co., Ltd. ALL rights reserved. - * - ************************************************************************************** - */ - -#ifndef __fc_H__ -#define __fc_H__ - - -/******************************************************************************/ -/* 设备特殊寄存器结构定义 */ -/******************************************************************************/ - -/* 允许匿名结构和匿名联合 */ -/* #pragma anon_unions */ - -/****************** Bit definition for FC_CMD register ************************/ - -#define FC_CMD_FC_CMD_POSS 0U -#define FC_CMD_FC_CMD_POSE 7U -#define FC_CMD_FC_CMD_MSK BITS(FC_CMD_FC_CMD_POSS,FC_CMD_FC_CMD_POSE) - -/****************** Bit definition for FC_PA register ************************/ - -#define FC_PA_PCNT_POSS 25U -#define FC_PA_PCNT_POSE 31U -#define FC_PA_PCNT_MSK BITS(FC_PA_PCNT_POSS,FC_PA_PCNT_POSE) - -#define FC_PA_IFREN_POS 24U -#define FC_PA_IFREN_MSK BIT(FC_PA_IFREN_POS) - -#define FC_PA_PROG_ADDR_POSS 0U -#define FC_PA_PROG_ADDR_POSE 23U -#define FC_PA_PROG_ADDR_MSK BITS(FC_PA_PROG_ADDR_POSS,FC_PA_PROG_ADDR_POSE) - -/****************** Bit definition for FC_PLD register ************************/ - -#define FC_PLD_PROG_DATA_L_POSS 0U -#define FC_PLD_PROG_DATA_L_POSE 31U -#define FC_PLD_PROG_DATA_L_MSK BITS(FC_PLD_PROG_DATA_L_POSS,FC_PLD_PROG_DATA_L_POSE) - -/****************** Bit definition for FC_PHD register ************************/ - -#define FC_PHD_PROG_DATA_H_POSS 0U -#define FC_PHD_PROG_DATA_H_POSE 31U -#define FC_PHD_PROG_DATA_H_MSK BITS(FC_PHD_PROG_DATA_H_POSS,FC_PHD_PROG_DATA_H_POSE) - -/****************** Bit definition for FC_CON register ************************/ - -#define FC_CON_SLEEP_POS 9U -#define FC_CON_SLEEP_MSK BIT(FC_CON_SLEEP_POS) - -#define FC_CON_PFEN_POS 8U -#define FC_CON_PFEN_MSK BIT(FC_CON_PFEN_POS) - -#define FC_CON_WAIT_POSS 0U -#define FC_CON_WAIT_POSE 1U -#define FC_CON_WAIT_MSK BITS(FC_CON_WAIT_POSS,FC_CON_WAIT_POSE) - -/****************** Bit definition for FC_STAT register ************************/ - -#define FC_STAT_OPVD_POS 2U -#define FC_STAT_OPVD_MSK BIT(FC_STAT_OPVD_POS) - -#define FC_STAT_MUNP2_POS 1U -#define FC_STAT_MUNP2_MSK BIT(FC_STAT_MUNP2_POS) - -#define FC_STAT_MUNP1_POS 0U -#define FC_STAT_MUNP1_MSK BIT(FC_STAT_MUNP1_POS) - -/****************** Bit definition for FC_UPL register ************************/ - -#define FC_UPL_UPL_POSS 0U -#define FC_UPL_UPL_POSE 31U -#define FC_UPL_UPL_MSK BITS(FC_UPL_UPL_POSS,FC_UPL_UPL_POSE) - -/****************** Bit definition for FC_UPH register ************************/ - -#define FC_UPH_UPH_POSS 0U -#define FC_UPH_UPH_POSE 31U -#define FC_UPH_UPH_MSK BITS(FC_UPH_UPH_POSS,FC_UPH_UPH_POSE) - -/****************** Bit definition for FC_OP_TRIM register ************************/ - -#define FC_OP_TRIM_BGTRIMVD_POSS 24U -#define FC_OP_TRIM_BGTRIMVD_POSE 31U -#define FC_OP_TRIM_BGTRIMVD_MSK BITS(FC_OP_TRIM_BGTRIMVD_POSS,FC_OP_TRIM_BGTRIMVD_POSE) - -#define FC_OP_TRIM_BGTRIM_POSS 16U -#define FC_OP_TRIM_BGTRIM_POSE 23U -#define FC_OP_TRIM_BGTRIM_MSK BITS(FC_OP_TRIM_BGTRIM_POSS,FC_OP_TRIM_BGTRIM_POSE) - -#define FC_OP_TRIM_HRCTRIMVD_POSS 8U -#define FC_OP_TRIM_HRCTRIMVD_POSE 15U -#define FC_OP_TRIM_HRCTRIMVD_MSK BITS(FC_OP_TRIM_HRCTRIMVD_POSS,FC_OP_TRIM_HRCTRIMVD_POSE) - -#define FC_OP_TRIM_HRCTRIM_POSS 0U -#define FC_OP_TRIM_HRCTRIM_POSE 7U -#define FC_OP_TRIM_HRCTRIM_MSK BITS(FC_OP_TRIM_HRCTRIM_POSS,FC_OP_TRIM_HRCTRIM_POSE) - -/****************** Bit definition for FC_OP_PRT2L register ************************/ - -#define FC_OP_PRT2L_PRTLV2L_POSS 0U -#define FC_OP_PRT2L_PRTLV2L_POSE 31U -#define FC_OP_PRT2L_PRTLV2L_MSK BITS(FC_OP_PRT2L_PRTLV2L_POSS,FC_OP_PRT2L_PRTLV2L_POSE) - -/****************** Bit definition for FC_OP_PRT2H register ************************/ - -#define FC_OP_PRT2H_PRTLV2H_POSS 0U -#define FC_OP_PRT2H_PRTLV2H_POSE 31U -#define FC_OP_PRT2H_PRTLV2H_MSK BITS(FC_OP_PRT2H_PRTLV2H_POSS,FC_OP_PRT2H_PRTLV2H_POSE) - -/****************** Bit definition for FC_OP_PRT1L register ************************/ - -#define FC_OP_PRT1L_PRTLV1L_POSS 0U -#define FC_OP_PRT1L_PRTLV1L_POSE 31U -#define FC_OP_PRT1L_PRTLV1L_MSK BITS(FC_OP_PRT1L_PRTLV1L_POSS,FC_OP_PRT1L_PRTLV1L_POSE) - -/****************** Bit definition for FC_OP_PRT1H register ************************/ - -#define FC_OP_PRT1H_PRTLV1H_POSS 0U -#define FC_OP_PRT1H_PRTLV1H_POSE 31U -#define FC_OP_PRT1H_PRTLV1H_MSK BITS(FC_OP_PRT1H_PRTLV1H_POSS,FC_OP_PRT1H_PRTLV1H_POSE) - -/****************** Bit definition for FC_OP_REMAP register ************************/ - -#define FC_OP_REMAP_HREMAP_POSS 8U -#define FC_OP_REMAP_HREMAP_POSE 15U -#define FC_OP_REMAP_HREMAP_MSK BITS(FC_OP_REMAP_HREMAP_POSS,FC_OP_REMAP_HREMAP_POSE) - -#define FC_OP_REMAP_SREMAP_POSS 4U -#define FC_OP_REMAP_SREMAP_POSE 5U -#define FC_OP_REMAP_SREMAP_MSK BITS(FC_OP_REMAP_SREMAP_POSS,FC_OP_REMAP_SREMAP_POSE) - -#define FC_OP_REMAP_SEFBASE_POSS 0U -#define FC_OP_REMAP_SEFBASE_POSE 3U -#define FC_OP_REMAP_SEFBASE_MSK BITS(FC_OP_REMAP_SEFBASE_POSS,FC_OP_REMAP_SEFBASE_POSE) - -typedef struct -{ - __IO uint32_t CMD; - __IO uint32_t PA; - __IO uint32_t PLD; - __IO uint32_t PHD; - __IO uint32_t CON; - __I uint32_t STAT; - uint32_t RESERVED0[2] ; - __IO uint32_t UPL; - __IO uint32_t UPH; - uint32_t RESERVED1[2] ; - __I uint32_t OP_TRIM; - uint32_t RESERVED2[4] ; -// uint32_t ADCTRIM_1V; -// uint32_t ADCTRIM_2V; -// uint32_t RESERVED3; - - uint32_t ADCTRIM_VDD5V_VREF5V; - uint32_t ADCTRIM_VDD3V3_VREF3V3; - uint32_t ADCTRIM_VDD5V_VREF2V5; - __I uint32_t OP_PRT2L; - __I uint32_t OP_PRT2H; - __I uint32_t OP_PRT1L; - __I uint32_t OP_PRT1H; - __I uint32_t OP_REMAP; -} FC_TypeDef; - - - - - -#endif diff --git a/bsp/essemi/es32f0271/libraries/CMSIS/Device/EastSoft/ES32F0271/Include/ES32F0271/reg_gpio.h b/bsp/essemi/es32f0271/libraries/CMSIS/Device/EastSoft/ES32F0271/Include/ES32F0271/reg_gpio.h deleted file mode 100644 index d965ef3b94..0000000000 --- a/bsp/essemi/es32f0271/libraries/CMSIS/Device/EastSoft/ES32F0271/Include/ES32F0271/reg_gpio.h +++ /dev/null @@ -1,710 +0,0 @@ -/** - ************************************************************************************** - * @file REG_GPIO.h - * @brief GPIO Head File - * - * @version V0.01 - * @date 12/5/2018 - * @author Eastsoft MCU Software Team - * @note - * - * Copyright (C) 2018 Shanghai Eastsoft Microelectronics Co., Ltd. ALL rights reserved. - * - ************************************************************************************** - */ - -#ifndef __GPIO_H__ -#define __GPIO_H__ - - -/******************************************************************************/ -/* 设备特殊寄存器结构定义 */ -/******************************************************************************/ - -/* 允许匿名结构和匿名联合 */ -/* #pragma anon_unions */ - -/****************** Bit definition for GPIO_IDATA register ************************/ - -#define GPIO_IDATA_ID15_POS 15U -#define GPIO_IDATA_ID15_MSK BIT(GPIO_IDATA_ID15_POS) - -#define GPIO_IDATA_ID14_POS 14U -#define GPIO_IDATA_ID14_MSK BIT(GPIO_IDATA_ID14_POS) - -#define GPIO_IDATA_ID13_POS 13U -#define GPIO_IDATA_ID13_MSK BIT(GPIO_IDATA_ID13_POS) - -#define GPIO_IDATA_ID12_POS 12U -#define GPIO_IDATA_ID12_MSK BIT(GPIO_IDATA_ID12_POS) - -#define GPIO_IDATA_ID11_POS 11U -#define GPIO_IDATA_ID11_MSK BIT(GPIO_IDATA_ID11_POS) - -#define GPIO_IDATA_ID10_POS 10U -#define GPIO_IDATA_ID10_MSK BIT(GPIO_IDATA_ID10_POS) - -#define GPIO_IDATA_ID9_POS 9U -#define GPIO_IDATA_ID9_MSK BIT(GPIO_IDATA_ID9_POS) - -#define GPIO_IDATA_ID8_POS 8U -#define GPIO_IDATA_ID8_MSK BIT(GPIO_IDATA_ID8_POS) - -#define GPIO_IDATA_ID7_POS 7U -#define GPIO_IDATA_ID7_MSK BIT(GPIO_IDATA_ID7_POS) - -#define GPIO_IDATA_ID6_POS 6U -#define GPIO_IDATA_ID6_MSK BIT(GPIO_IDATA_ID6_POS) - -#define GPIO_IDATA_ID5_POS 5U -#define GPIO_IDATA_ID5_MSK BIT(GPIO_IDATA_ID5_POS) - -#define GPIO_IDATA_ID4_POS 4U -#define GPIO_IDATA_ID4_MSK BIT(GPIO_IDATA_ID4_POS) - -#define GPIO_IDATA_ID3_POS 3U -#define GPIO_IDATA_ID3_MSK BIT(GPIO_IDATA_ID3_POS) - -#define GPIO_IDATA_ID2_POS 2U -#define GPIO_IDATA_ID2_MSK BIT(GPIO_IDATA_ID2_POS) - -#define GPIO_IDATA_ID1_POS 1U -#define GPIO_IDATA_ID1_MSK BIT(GPIO_IDATA_ID1_POS) - -#define GPIO_IDATA_ID0_POS 0U -#define GPIO_IDATA_ID0_MSK BIT(GPIO_IDATA_ID0_POS) - -/****************** Bit definition for GPIO_ODATA register ************************/ - -#define GPIO_ODATA_OD15_POS 15U -#define GPIO_ODATA_OD15_MSK BIT(GPIO_ODATA_OD15_POS) - -#define GPIO_ODATA_OD14_POS 14U -#define GPIO_ODATA_OD14_MSK BIT(GPIO_ODATA_OD14_POS) - -#define GPIO_ODATA_OD13_POS 13U -#define GPIO_ODATA_OD13_MSK BIT(GPIO_ODATA_OD13_POS) - -#define GPIO_ODATA_OD12_POS 12U -#define GPIO_ODATA_OD12_MSK BIT(GPIO_ODATA_OD12_POS) - -#define GPIO_ODATA_OD11_POS 11U -#define GPIO_ODATA_OD11_MSK BIT(GPIO_ODATA_OD11_POS) - -#define GPIO_ODATA_OD10_POS 10U -#define GPIO_ODATA_OD10_MSK BIT(GPIO_ODATA_OD10_POS) - -#define GPIO_ODATA_OD9_POS 9U -#define GPIO_ODATA_OD9_MSK BIT(GPIO_ODATA_OD9_POS) - -#define GPIO_ODATA_OD8_POS 8U -#define GPIO_ODATA_OD8_MSK BIT(GPIO_ODATA_OD8_POS) - -#define GPIO_ODATA_OD7_POS 7U -#define GPIO_ODATA_OD7_MSK BIT(GPIO_ODATA_OD7_POS) - -#define GPIO_ODATA_OD6_POS 6U -#define GPIO_ODATA_OD6_MSK BIT(GPIO_ODATA_OD6_POS) - -#define GPIO_ODATA_OD5_POS 5U -#define GPIO_ODATA_OD5_MSK BIT(GPIO_ODATA_OD5_POS) - -#define GPIO_ODATA_OD4_POS 4U -#define GPIO_ODATA_OD4_MSK BIT(GPIO_ODATA_OD4_POS) - -#define GPIO_ODATA_OD3_POS 3U -#define GPIO_ODATA_OD3_MSK BIT(GPIO_ODATA_OD3_POS) - -#define GPIO_ODATA_OD2_POS 2U -#define GPIO_ODATA_OD2_MSK BIT(GPIO_ODATA_OD2_POS) - -#define GPIO_ODATA_OD1_POS 1U -#define GPIO_ODATA_OD1_MSK BIT(GPIO_ODATA_OD1_POS) - -#define GPIO_ODATA_OD0_POS 0U -#define GPIO_ODATA_OD0_MSK BIT(GPIO_ODATA_OD0_POS) - -/****************** Bit definition for GPIO_BSBR register ************************/ - -#define GPIO_BSBR_BR15_POS 31U -#define GPIO_BSBR_BR15_MSK BIT(GPIO_BSBR_BR15_POS) - -#define GPIO_BSBR_BR14_POS 30U -#define GPIO_BSBR_BR14_MSK BIT(GPIO_BSBR_BR14_POS) - -#define GPIO_BSBR_BR13_POS 29U -#define GPIO_BSBR_BR13_MSK BIT(GPIO_BSBR_BR13_POS) - -#define GPIO_BSBR_BR12_POS 28U -#define GPIO_BSBR_BR12_MSK BIT(GPIO_BSBR_BR12_POS) - -#define GPIO_BSBR_BR11_POS 27U -#define GPIO_BSBR_BR11_MSK BIT(GPIO_BSBR_BR11_POS) - -#define GPIO_BSBR_BR10_POS 26U -#define GPIO_BSBR_BR10_MSK BIT(GPIO_BSBR_BR10_POS) - -#define GPIO_BSBR_BR9_POS 25U -#define GPIO_BSBR_BR9_MSK BIT(GPIO_BSBR_BR9_POS) - -#define GPIO_BSBR_BR8_POS 24U -#define GPIO_BSBR_BR8_MSK BIT(GPIO_BSBR_BR8_POS) - -#define GPIO_BSBR_BR7_POS 23U -#define GPIO_BSBR_BR7_MSK BIT(GPIO_BSBR_BR7_POS) - -#define GPIO_BSBR_BR6_POS 22U -#define GPIO_BSBR_BR6_MSK BIT(GPIO_BSBR_BR6_POS) - -#define GPIO_BSBR_BR5_POS 21U -#define GPIO_BSBR_BR5_MSK BIT(GPIO_BSBR_BR5_POS) - -#define GPIO_BSBR_BR4_POS 20U -#define GPIO_BSBR_BR4_MSK BIT(GPIO_BSBR_BR4_POS) - -#define GPIO_BSBR_BR3_POS 19U -#define GPIO_BSBR_BR3_MSK BIT(GPIO_BSBR_BR3_POS) - -#define GPIO_BSBR_BR2_POS 18U -#define GPIO_BSBR_BR2_MSK BIT(GPIO_BSBR_BR2_POS) - -#define GPIO_BSBR_BR1_POS 17U -#define GPIO_BSBR_BR1_MSK BIT(GPIO_BSBR_BR1_POS) - -#define GPIO_BSBR_BR0_POS 16U -#define GPIO_BSBR_BR0_MSK BIT(GPIO_BSBR_BR0_POS) - -#define GPIO_BSBR_BS15_POS 15U -#define GPIO_BSBR_BS15_MSK BIT(GPIO_BSBR_BS15_POS) - -#define GPIO_BSBR_BS14_POS 14U -#define GPIO_BSBR_BS14_MSK BIT(GPIO_BSBR_BS14_POS) - -#define GPIO_BSBR_BS13_POS 13U -#define GPIO_BSBR_BS13_MSK BIT(GPIO_BSBR_BS13_POS) - -#define GPIO_BSBR_BS12_POS 12U -#define GPIO_BSBR_BS12_MSK BIT(GPIO_BSBR_BS12_POS) - -#define GPIO_BSBR_BS11_POS 11U -#define GPIO_BSBR_BS11_MSK BIT(GPIO_BSBR_BS11_POS) - -#define GPIO_BSBR_BS10_POS 10U -#define GPIO_BSBR_BS10_MSK BIT(GPIO_BSBR_BS10_POS) - -#define GPIO_BSBR_BS9_POS 9U -#define GPIO_BSBR_BS9_MSK BIT(GPIO_BSBR_BS9_POS) - -#define GPIO_BSBR_BS8_POS 8U -#define GPIO_BSBR_BS8_MSK BIT(GPIO_BSBR_BS8_POS) - -#define GPIO_BSBR_BS7_POS 7U -#define GPIO_BSBR_BS7_MSK BIT(GPIO_BSBR_BS7_POS) - -#define GPIO_BSBR_BS6_POS 6U -#define GPIO_BSBR_BS6_MSK BIT(GPIO_BSBR_BS6_POS) - -#define GPIO_BSBR_BS5_POS 5U -#define GPIO_BSBR_BS5_MSK BIT(GPIO_BSBR_BS5_POS) - -#define GPIO_BSBR_BS4_POS 4U -#define GPIO_BSBR_BS4_MSK BIT(GPIO_BSBR_BS4_POS) - -#define GPIO_BSBR_BS3_POS 3U -#define GPIO_BSBR_BS3_MSK BIT(GPIO_BSBR_BS3_POS) - -#define GPIO_BSBR_BS2_POS 2U -#define GPIO_BSBR_BS2_MSK BIT(GPIO_BSBR_BS2_POS) - -#define GPIO_BSBR_BS1_POS 1U -#define GPIO_BSBR_BS1_MSK BIT(GPIO_BSBR_BS1_POS) - -#define GPIO_BSBR_BS0_POS 0U -#define GPIO_BSBR_BS0_MSK BIT(GPIO_BSBR_BS0_POS) - -/****************** Bit definition for GPIO_LCK register ************************/ - -#define GPIO_LCK_LCKK_POS 16U -#define GPIO_LCK_LCKK_MSK BIT(GPIO_LCK_LCKK_POS) - -#define GPIO_LCK_LCK15_POS 15U -#define GPIO_LCK_LCK15_MSK BIT(GPIO_LCK_LCK15_POS) - -#define GPIO_LCK_LCK14_POS 14U -#define GPIO_LCK_LCK14_MSK BIT(GPIO_LCK_LCK14_POS) - -#define GPIO_LCK_LCK13_POS 13U -#define GPIO_LCK_LCK13_MSK BIT(GPIO_LCK_LCK13_POS) - -#define GPIO_LCK_LCK12_POS 12U -#define GPIO_LCK_LCK12_MSK BIT(GPIO_LCK_LCK12_POS) - -#define GPIO_LCK_LCK11_POS 11U -#define GPIO_LCK_LCK11_MSK BIT(GPIO_LCK_LCK11_POS) - -#define GPIO_LCK_LCK10_POS 10U -#define GPIO_LCK_LCK10_MSK BIT(GPIO_LCK_LCK10_POS) - -#define GPIO_LCK_LCK9_POS 9U -#define GPIO_LCK_LCK9_MSK BIT(GPIO_LCK_LCK9_POS) - -#define GPIO_LCK_LCK8_POS 8U -#define GPIO_LCK_LCK8_MSK BIT(GPIO_LCK_LCK8_POS) - -#define GPIO_LCK_LCK7_POS 7U -#define GPIO_LCK_LCK7_MSK BIT(GPIO_LCK_LCK7_POS) - -#define GPIO_LCK_LCK6_POS 6U -#define GPIO_LCK_LCK6_MSK BIT(GPIO_LCK_LCK6_POS) - -#define GPIO_LCK_LCK5_POS 5U -#define GPIO_LCK_LCK5_MSK BIT(GPIO_LCK_LCK5_POS) - -#define GPIO_LCK_LCK4_POS 4U -#define GPIO_LCK_LCK4_MSK BIT(GPIO_LCK_LCK4_POS) - -#define GPIO_LCK_LCK3_POS 3U -#define GPIO_LCK_LCK3_MSK BIT(GPIO_LCK_LCK3_POS) - -#define GPIO_LCK_LCK2_POS 2U -#define GPIO_LCK_LCK2_MSK BIT(GPIO_LCK_LCK2_POS) - -#define GPIO_LCK_LCK1_POS 1U -#define GPIO_LCK_LCK1_MSK BIT(GPIO_LCK_LCK1_POS) - -#define GPIO_LCK_LCK0_POS 0U -#define GPIO_LCK_LCK0_MSK BIT(GPIO_LCK_LCK0_POS) - -/****************** Bit definition for GPIO_MOD register ************************/ - -#define GPIO_MOD_MOD15_POSS 30U -#define GPIO_MOD_MOD15_POSE 31U -#define GPIO_MOD_MOD15_MSK BITS(GPIO_MOD_MOD15_POSS,GPIO_MOD_MOD15_POSE) - -#define GPIO_MOD_MOD14_POSS 28U -#define GPIO_MOD_MOD14_POSE 29U -#define GPIO_MOD_MOD14_MSK BITS(GPIO_MOD_MOD14_POSS,GPIO_MOD_MOD14_POSE) - -#define GPIO_MOD_MOD13_POSS 26U -#define GPIO_MOD_MOD13_POSE 27U -#define GPIO_MOD_MOD13_MSK BITS(GPIO_MOD_MOD13_POSS,GPIO_MOD_MOD13_POSE) - -#define GPIO_MOD_MOD12_POSS 24U -#define GPIO_MOD_MOD12_POSE 25U -#define GPIO_MOD_MOD12_MSK BITS(GPIO_MOD_MOD12_POSS,GPIO_MOD_MOD12_POSE) - -#define GPIO_MOD_MOD11_POSS 22U -#define GPIO_MOD_MOD11_POSE 23U -#define GPIO_MOD_MOD11_MSK BITS(GPIO_MOD_MOD11_POSS,GPIO_MOD_MOD11_POSE) - -#define GPIO_MOD_MOD10_POSS 20U -#define GPIO_MOD_MOD10_POSE 21U -#define GPIO_MOD_MOD10_MSK BITS(GPIO_MOD_MOD10_POSS,GPIO_MOD_MOD10_POSE) - -#define GPIO_MOD_MOD9_POSS 18U -#define GPIO_MOD_MOD9_POSE 19U -#define GPIO_MOD_MOD9_MSK BITS(GPIO_MOD_MOD9_POSS,GPIO_MOD_MOD9_POSE) - -#define GPIO_MOD_MOD8_POSS 16U -#define GPIO_MOD_MOD8_POSE 17U -#define GPIO_MOD_MOD8_MSK BITS(GPIO_MOD_MOD8_POSS,GPIO_MOD_MOD8_POSE) - -#define GPIO_MOD_MOD7_POSS 14U -#define GPIO_MOD_MOD7_POSE 15U -#define GPIO_MOD_MOD7_MSK BITS(GPIO_MOD_MOD7_POSS,GPIO_MOD_MOD7_POSE) - -#define GPIO_MOD_MOD6_POSS 12U -#define GPIO_MOD_MOD6_POSE 13U -#define GPIO_MOD_MOD6_MSK BITS(GPIO_MOD_MOD6_POSS,GPIO_MOD_MOD6_POSE) - -#define GPIO_MOD_MOD5_POSS 10U -#define GPIO_MOD_MOD5_POSE 11U -#define GPIO_MOD_MOD5_MSK BITS(GPIO_MOD_MOD5_POSS,GPIO_MOD_MOD5_POSE) - -#define GPIO_MOD_MOD4_POSS 8U -#define GPIO_MOD_MOD4_POSE 9U -#define GPIO_MOD_MOD4_MSK BITS(GPIO_MOD_MOD4_POSS,GPIO_MOD_MOD4_POSE) - -#define GPIO_MOD_MOD3_POSS 6U -#define GPIO_MOD_MOD3_POSE 7U -#define GPIO_MOD_MOD3_MSK BITS(GPIO_MOD_MOD3_POSS,GPIO_MOD_MOD3_POSE) - -#define GPIO_MOD_MOD2_POSS 4U -#define GPIO_MOD_MOD2_POSE 5U -#define GPIO_MOD_MOD2_MSK BITS(GPIO_MOD_MOD2_POSS,GPIO_MOD_MOD2_POSE) - -#define GPIO_MOD_MOD1_POSS 2U -#define GPIO_MOD_MOD1_POSE 3U -#define GPIO_MOD_MOD1_MSK BITS(GPIO_MOD_MOD1_POSS,GPIO_MOD_MOD1_POSE) - -#define GPIO_MOD_MOD0_POSS 0U -#define GPIO_MOD_MOD0_POSE 1U -#define GPIO_MOD_MOD0_MSK BITS(GPIO_MOD_MOD0_POSS,GPIO_MOD_MOD0_POSE) - -/****************** Bit definition for GPIO_PUD register ************************/ - -#define GPIO_PUD_PUD15_POSS 30U -#define GPIO_PUD_PUD15_POSE 31U -#define GPIO_PUD_PUD15_MSK BITS(GPIO_PUD_PUD15_POSS,GPIO_PUD_PUD15_POSE) - -#define GPIO_PUD_PUD14_POSS 28U -#define GPIO_PUD_PUD14_POSE 29U -#define GPIO_PUD_PUD14_MSK BITS(GPIO_PUD_PUD14_POSS,GPIO_PUD_PUD14_POSE) - -#define GPIO_PUD_PUD13_POSS 26U -#define GPIO_PUD_PUD13_POSE 27U -#define GPIO_PUD_PUD13_MSK BITS(GPIO_PUD_PUD13_POSS,GPIO_PUD_PUD13_POSE) - -#define GPIO_PUD_PUD12_POSS 24U -#define GPIO_PUD_PUD12_POSE 25U -#define GPIO_PUD_PUD12_MSK BITS(GPIO_PUD_PUD12_POSS,GPIO_PUD_PUD12_POSE) - -#define GPIO_PUD_PUD11_POSS 22U -#define GPIO_PUD_PUD11_POSE 23U -#define GPIO_PUD_PUD11_MSK BITS(GPIO_PUD_PUD11_POSS,GPIO_PUD_PUD11_POSE) - -#define GPIO_PUD_PUD10_POSS 20U -#define GPIO_PUD_PUD10_POSE 21U -#define GPIO_PUD_PUD10_MSK BITS(GPIO_PUD_PUD10_POSS,GPIO_PUD_PUD10_POSE) - -#define GPIO_PUD_PUD9_POSS 18U -#define GPIO_PUD_PUD9_POSE 19U -#define GPIO_PUD_PUD9_MSK BITS(GPIO_PUD_PUD9_POSS,GPIO_PUD_PUD9_POSE) - -#define GPIO_PUD_PUD8_POSS 16U -#define GPIO_PUD_PUD8_POSE 17U -#define GPIO_PUD_PUD8_MSK BITS(GPIO_PUD_PUD8_POSS,GPIO_PUD_PUD8_POSE) - -#define GPIO_PUD_PUD7_POSS 14U -#define GPIO_PUD_PUD7_POSE 15U -#define GPIO_PUD_PUD7_MSK BITS(GPIO_PUD_PUD7_POSS,GPIO_PUD_PUD7_POSE) - -#define GPIO_PUD_PUD6_POSS 12U -#define GPIO_PUD_PUD6_POSE 13U -#define GPIO_PUD_PUD6_MSK BITS(GPIO_PUD_PUD6_POSS,GPIO_PUD_PUD6_POSE) - -#define GPIO_PUD_PUD5_POSS 10U -#define GPIO_PUD_PUD5_POSE 11U -#define GPIO_PUD_PUD5_MSK BITS(GPIO_PUD_PUD5_POSS,GPIO_PUD_PUD5_POSE) - -#define GPIO_PUD_PUD4_POSS 8U -#define GPIO_PUD_PUD4_POSE 9U -#define GPIO_PUD_PUD4_MSK BITS(GPIO_PUD_PUD4_POSS,GPIO_PUD_PUD4_POSE) - -#define GPIO_PUD_PUD3_POSS 6U -#define GPIO_PUD_PUD3_POSE 7U -#define GPIO_PUD_PUD3_MSK BITS(GPIO_PUD_PUD3_POSS,GPIO_PUD_PUD3_POSE) - -#define GPIO_PUD_PUD2_POSS 4U -#define GPIO_PUD_PUD2_POSE 5U -#define GPIO_PUD_PUD2_MSK BITS(GPIO_PUD_PUD2_POSS,GPIO_PUD_PUD2_POSE) - -#define GPIO_PUD_PUD1_POSS 2U -#define GPIO_PUD_PUD1_POSE 3U -#define GPIO_PUD_PUD1_MSK BITS(GPIO_PUD_PUD1_POSS,GPIO_PUD_PUD1_POSE) - -#define GPIO_PUD_PUD0_POSS 0U -#define GPIO_PUD_PUD0_POSE 1U -#define GPIO_PUD_PUD0_MSK BITS(GPIO_PUD_PUD0_POSS,GPIO_PUD_PUD0_POSE) - -/****************** Bit definition for GPIO_OT register ************************/ - -#define GPIO_OT_OT15_POS 15U -#define GPIO_OT_OT15_MSK BIT(GPIO_OT_OT15_POS) - -#define GPIO_OT_OT14_POS 14U -#define GPIO_OT_OT14_MSK BIT(GPIO_OT_OT14_POS) - -#define GPIO_OT_OT13_POS 13U -#define GPIO_OT_OT13_MSK BIT(GPIO_OT_OT13_POS) - -#define GPIO_OT_OT12_POS 12U -#define GPIO_OT_OT12_MSK BIT(GPIO_OT_OT12_POS) - -#define GPIO_OT_OT11_POS 11U -#define GPIO_OT_OT11_MSK BIT(GPIO_OT_OT11_POS) - -#define GPIO_OT_OT10_POS 10U -#define GPIO_OT_OT10_MSK BIT(GPIO_OT_OT10_POS) - -#define GPIO_OT_OT9_POS 9U -#define GPIO_OT_OT9_MSK BIT(GPIO_OT_OT9_POS) - -#define GPIO_OT_OT8_POS 8U -#define GPIO_OT_OT8_MSK BIT(GPIO_OT_OT8_POS) - -#define GPIO_OT_OT7_POS 7U -#define GPIO_OT_OT7_MSK BIT(GPIO_OT_OT7_POS) - -#define GPIO_OT_OT6_POS 6U -#define GPIO_OT_OT6_MSK BIT(GPIO_OT_OT6_POS) - -#define GPIO_OT_OT5_POS 5U -#define GPIO_OT_OT5_MSK BIT(GPIO_OT_OT5_POS) - -#define GPIO_OT_OT4_POS 4U -#define GPIO_OT_OT4_MSK BIT(GPIO_OT_OT4_POS) - -#define GPIO_OT_OT3_POS 3U -#define GPIO_OT_OT3_MSK BIT(GPIO_OT_OT3_POS) - -#define GPIO_OT_OT2_POS 2U -#define GPIO_OT_OT2_MSK BIT(GPIO_OT_OT2_POS) - -#define GPIO_OT_OT1_POS 1U -#define GPIO_OT_OT1_MSK BIT(GPIO_OT_OT1_POS) - -#define GPIO_OT_OT0_POS 0U -#define GPIO_OT_OT0_MSK BIT(GPIO_OT_OT0_POS) - -#define GPIO_OT_OT_POSS 0U -#define GPIO_OT_OT_POSE 15U -#define GPIO_OT_OT_MSK BITS(GPIO_OT_OT_POSS,GPIO_OT_OT_POSE) - -/****************** Bit definition for GPIO_DS register ************************/ - -#define GPIO_DS_DS15_POS 15U -#define GPIO_DS_DS15_MSK BIT(GPIO_DS_DS15_POS) - -#define GPIO_DS_DS14_POS 14U -#define GPIO_DS_DS14_MSK BIT(GPIO_DS_DS14_POS) - -#define GPIO_DS_DS13_POS 13U -#define GPIO_DS_DS13_MSK BIT(GPIO_DS_DS13_POS) - -#define GPIO_DS_DS12_POS 12U -#define GPIO_DS_DS12_MSK BIT(GPIO_DS_DS12_POS) - -#define GPIO_DS_DS11_POS 11U -#define GPIO_DS_DS11_MSK BIT(GPIO_DS_DS11_POS) - -#define GPIO_DS_DS10_POS 10U -#define GPIO_DS_DS10_MSK BIT(GPIO_DS_DS10_POS) - -#define GPIO_DS_DS9_POS 9U -#define GPIO_DS_DS9_MSK BIT(GPIO_DS_DS9_POS) - -#define GPIO_DS_DS8_POS 8U -#define GPIO_DS_DS8_MSK BIT(GPIO_DS_DS8_POS) - -#define GPIO_DS_DS7_POS 7U -#define GPIO_DS_DS7_MSK BIT(GPIO_DS_DS7_POS) - -#define GPIO_DS_DS6_POS 6U -#define GPIO_DS_DS6_MSK BIT(GPIO_DS_DS6_POS) - -#define GPIO_DS_DS5_POS 5U -#define GPIO_DS_DS5_MSK BIT(GPIO_DS_DS5_POS) - -#define GPIO_DS_DS4_POS 4U -#define GPIO_DS_DS4_MSK BIT(GPIO_DS_DS4_POS) - -#define GPIO_DS_DS3_POS 3U -#define GPIO_DS_DS3_MSK BIT(GPIO_DS_DS3_POS) - -#define GPIO_DS_DS2_POS 2U -#define GPIO_DS_DS2_MSK BIT(GPIO_DS_DS2_POS) - -#define GPIO_DS_DS1_POS 1U -#define GPIO_DS_DS1_MSK BIT(GPIO_DS_DS1_POS) - -#define GPIO_DS_DS0_POS 0U -#define GPIO_DS_DS0_MSK BIT(GPIO_DS_DS0_POS) - -#define GPIO_DS_DS_POSS 0U -#define GPIO_DS_DS_POSE 15U -#define GPIO_DS_DS_MSK BITS(GPIO_DS_DS_POSS,GPIO_DS_DS_POSE) - -/****************** Bit definition for GPIO_FIR register ************************/ - -#define GPIO_FIR_FIR15_POS 15U -#define GPIO_FIR_FIR15_MSK BIT(GPIO_FIR_FIR15_POS) - -#define GPIO_FIR_FIR14_POS 14U -#define GPIO_FIR_FIR14_MSK BIT(GPIO_FIR_FIR14_POS) - -#define GPIO_FIR_FIR13_POS 13U -#define GPIO_FIR_FIR13_MSK BIT(GPIO_FIR_FIR13_POS) - -#define GPIO_FIR_FIR12_POS 12U -#define GPIO_FIR_FIR12_MSK BIT(GPIO_FIR_FIR12_POS) - -#define GPIO_FIR_FIR11_POS 11U -#define GPIO_FIR_FIR11_MSK BIT(GPIO_FIR_FIR11_POS) - -#define GPIO_FIR_FIR10_POS 10U -#define GPIO_FIR_FIR10_MSK BIT(GPIO_FIR_FIR10_POS) - -#define GPIO_FIR_FIR9_POS 9U -#define GPIO_FIR_FIR9_MSK BIT(GPIO_FIR_FIR9_POS) - -#define GPIO_FIR_FIR8_POS 8U -#define GPIO_FIR_FIR8_MSK BIT(GPIO_FIR_FIR8_POS) - -#define GPIO_FIR_FIR7_POS 7U -#define GPIO_FIR_FIR7_MSK BIT(GPIO_FIR_FIR7_POS) - -#define GPIO_FIR_FIR6_POS 6U -#define GPIO_FIR_FIR6_MSK BIT(GPIO_FIR_FIR6_POS) - -#define GPIO_FIR_FIR5_POS 5U -#define GPIO_FIR_FIR5_MSK BIT(GPIO_FIR_FIR5_POS) - -#define GPIO_FIR_FIR4_POS 4U -#define GPIO_FIR_FIR4_MSK BIT(GPIO_FIR_FIR4_POS) - -#define GPIO_FIR_FIR3_POS 3U -#define GPIO_FIR_FIR3_MSK BIT(GPIO_FIR_FIR3_POS) - -#define GPIO_FIR_FIR2_POS 2U -#define GPIO_FIR_FIR2_MSK BIT(GPIO_FIR_FIR2_POS) - -#define GPIO_FIR_FIR1_POS 1U -#define GPIO_FIR_FIR1_MSK BIT(GPIO_FIR_FIR1_POS) - -#define GPIO_FIR_FIR0_POS 0U -#define GPIO_FIR_FIR0_MSK BIT(GPIO_FIR_FIR0_POS) - -/****************** Bit definition for GPIO_IST register ************************/ - -#define GPIO_IST_IST15_POS 15U -#define GPIO_IST_IST15_MSK BIT(GPIO_IST_IST15_POS) - -#define GPIO_IST_IST14_POS 14U -#define GPIO_IST_IST14_MSK BIT(GPIO_IST_IST14_POS) - -#define GPIO_IST_IST13_POS 13U -#define GPIO_IST_IST13_MSK BIT(GPIO_IST_IST13_POS) - -#define GPIO_IST_IST12_POS 12U -#define GPIO_IST_IST12_MSK BIT(GPIO_IST_IST12_POS) - -#define GPIO_IST_IST11_POS 11U -#define GPIO_IST_IST11_MSK BIT(GPIO_IST_IST11_POS) - -#define GPIO_IST_IST10_POS 10U -#define GPIO_IST_IST10_MSK BIT(GPIO_IST_IST10_POS) - -#define GPIO_IST_IST9_POS 9U -#define GPIO_IST_IST9_MSK BIT(GPIO_IST_IST9_POS) - -#define GPIO_IST_IST8_POS 8U -#define GPIO_IST_IST8_MSK BIT(GPIO_IST_IST8_POS) - -#define GPIO_IST_IST7_POS 7U -#define GPIO_IST_IST7_MSK BIT(GPIO_IST_IST7_POS) - -#define GPIO_IST_IST6_POS 6U -#define GPIO_IST_IST6_MSK BIT(GPIO_IST_IST6_POS) - -#define GPIO_IST_IST5_POS 5U -#define GPIO_IST_IST5_MSK BIT(GPIO_IST_IST5_POS) - -#define GPIO_IST_IST4_POS 4U -#define GPIO_IST_IST4_MSK BIT(GPIO_IST_IST4_POS) - -#define GPIO_IST_IST3_POS 3U -#define GPIO_IST_IST3_MSK BIT(GPIO_IST_IST3_POS) - -#define GPIO_IST_IST2_POS 2U -#define GPIO_IST_IST2_MSK BIT(GPIO_IST_IST2_POS) - -#define GPIO_IST_IST1_POS 1U -#define GPIO_IST_IST1_MSK BIT(GPIO_IST_IST1_POS) - -#define GPIO_IST_IST0_POS 0U -#define GPIO_IST_IST0_MSK BIT(GPIO_IST_IST0_POS) - -#define GPIO_IST_IST_POSS 0U -#define GPIO_IST_IST_POSE 15U -#define GPIO_IST_IST_MSK BITS(GPIO_IST_IST_POSS, GPIO_IST_IST_POSE) - -/****************** Bit definition for GPIO_AFL register ************************/ - -#define GPIO_AFL_AF7_POSS 28U -#define GPIO_AFL_AF7_POSE 31U -#define GPIO_AFL_AF7_MSK BITS(GPIO_AFL_AF7_POSS,GPIO_AFL_AF7_POSE) - -#define GPIO_AFL_AF6_POSS 24U -#define GPIO_AFL_AF6_POSE 27U -#define GPIO_AFL_AF6_MSK BITS(GPIO_AFL_AF6_POSS,GPIO_AFL_AF6_POSE) - -#define GPIO_AFL_AF5_POSS 20U -#define GPIO_AFL_AF5_POSE 23U -#define GPIO_AFL_AF5_MSK BITS(GPIO_AFL_AF5_POSS,GPIO_AFL_AF5_POSE) - -#define GPIO_AFL_AF4_POSS 16U -#define GPIO_AFL_AF4_POSE 19U -#define GPIO_AFL_AF4_MSK BITS(GPIO_AFL_AF4_POSS,GPIO_AFL_AF4_POSE) - -#define GPIO_AFL_AF3_POSS 12U -#define GPIO_AFL_AF3_POSE 15U -#define GPIO_AFL_AF3_MSK BITS(GPIO_AFL_AF3_POSS,GPIO_AFL_AF3_POSE) - -#define GPIO_AFL_AF2_POSS 8U -#define GPIO_AFL_AF2_POSE 11U -#define GPIO_AFL_AF2_MSK BITS(GPIO_AFL_AF2_POSS,GPIO_AFL_AF2_POSE) - -#define GPIO_AFL_AF1_POSS 4U -#define GPIO_AFL_AF1_POSE 7U -#define GPIO_AFL_AF1_MSK BITS(GPIO_AFL_AF1_POSS,GPIO_AFL_AF1_POSE) - -#define GPIO_AFL_AF0_POSS 0U -#define GPIO_AFL_AF0_POSE 3U -#define GPIO_AFL_AF0_MSK BITS(GPIO_AFL_AF0_POSS,GPIO_AFL_AF0_POSE) - -/****************** Bit definition for GPIO_AFH register ************************/ - -#define GPIO_AFH_AF15_POSS 28U -#define GPIO_AFH_AF15_POSE 31U -#define GPIO_AFH_AF15_MSK BITS(GPIO_AFH_AF15_POSS,GPIO_AFH_AF15_POSE) - -#define GPIO_AFH_AF14_POSS 24U -#define GPIO_AFH_AF14_POSE 27U -#define GPIO_AFH_AF14_MSK BITS(GPIO_AFH_AF14_POSS,GPIO_AFH_AF14_POSE) - -#define GPIO_AFH_AF13_POSS 20U -#define GPIO_AFH_AF13_POSE 23U -#define GPIO_AFH_AF13_MSK BITS(GPIO_AFH_AF13_POSS,GPIO_AFH_AF13_POSE) - -#define GPIO_AFH_AF12_POSS 16U -#define GPIO_AFH_AF12_POSE 19U -#define GPIO_AFH_AF12_MSK BITS(GPIO_AFH_AF12_POSS,GPIO_AFH_AF12_POSE) - -#define GPIO_AFH_AF11_POSS 12U -#define GPIO_AFH_AF11_POSE 15U -#define GPIO_AFH_AF11_MSK BITS(GPIO_AFH_AF11_POSS,GPIO_AFH_AF11_POSE) - -#define GPIO_AFH_AF10_POSS 8U -#define GPIO_AFH_AF10_POSE 11U -#define GPIO_AFH_AF10_MSK BITS(GPIO_AFH_AF10_POSS,GPIO_AFH_AF10_POSE) - -#define GPIO_AFH_AF9_POSS 4U -#define GPIO_AFH_AF9_POSE 7U -#define GPIO_AFH_AF9_MSK BITS(GPIO_AFH_AF9_POSS,GPIO_AFH_AF9_POSE) - -#define GPIO_AFH_AF8_POSS 0U -#define GPIO_AFH_AF8_POSE 3U -#define GPIO_AFH_AF8_MSK BITS(GPIO_AFH_AF8_POSS,GPIO_AFH_AF8_POSE) - -typedef struct -{ - __I uint32_t IDATA; - __IO uint32_t ODATA; - __O uint32_t BSBR; - __IO uint32_t LCK; - __IO uint32_t MOD; - __IO uint32_t PUD; - __IO uint32_t OT; - __IO uint32_t DS; - __IO uint32_t FIR; - __IO uint32_t IST; - __IO uint32_t AFL; - __IO uint32_t AFH; -} GPIO_TypeDef; - - - - - -#endif diff --git a/bsp/essemi/es32f0271/libraries/CMSIS/Device/EastSoft/ES32F0271/Include/ES32F0271/reg_hdiv.h b/bsp/essemi/es32f0271/libraries/CMSIS/Device/EastSoft/ES32F0271/Include/ES32F0271/reg_hdiv.h deleted file mode 100644 index d1ffd0d102..0000000000 --- a/bsp/essemi/es32f0271/libraries/CMSIS/Device/EastSoft/ES32F0271/Include/ES32F0271/reg_hdiv.h +++ /dev/null @@ -1,75 +0,0 @@ -/** - ************************************************************************************** - * @file REG_HDIV.h - * @brief HDIV Head File - * - * @version V0.01 - * @data 12/3/2018 - * @author Eastsoft MCU Software Team - * @note - * - * Copyright (C) 2018 Shanghai Eastsoft Microelectronics Co., Ltd. ALL rights reserved. - * - ************************************************************************************** - */ - -#ifndef __hdiv_H__ -#define __hdiv_H__ - - -/******************************************************************************/ -/* 设备特殊寄存器结构定义 */ -/******************************************************************************/ - -/* 允许匿名结构和匿名联合 */ -/* #pragma anon_unions */ - -/****************** Bit definition for HDIV_DIVDR register ************************/ - -#define HDIV_DIVDR_DIVS_POSS 0U -#define HDIV_DIVDR_DIVS_POSE 31U -#define HDIV_DIVDR_DIVD_MSK BITS(HDIV_DIVDR_DIVD_POSS,HDIV_DIVDR_DIVD_POSE) - -/****************** Bit definition for HDIV_DIVSR register ************************/ - -#define HDIV_DIVSR_DIVS_POSS 0U -#define HDIV_DIVSR_DIVS_POSE 31U -#define HDIV_DIVSR_DIVS_MSK BITS(HDIV_DIVSR_DIVS_POSS,HDIV_DIVSR_DIVS_POSE) - -/****************** Bit definition for HDIV_DIVQR register ************************/ - -#define HDIV_DIVQR_DIVQ_POSS 0U -#define HDIV_DIVQR_DIVQ_POSE 31U -#define HDIV_DIVQR_DIVQ_MSK BITS(HDIV_DIVQR_DIVQ_POSS,HDIV_DIVQR_DIVQ_POSE) - -/****************** Bit definition for HDIV_DIVRR register ************************/ - -#define HDIV_DIVRR_DIVR_POSS 0U -#define HDIV_DIVRR_DIVR_POSE 31U -#define HDIV_DIVRR_DIVR_MSK BITS(HDIV_DIVRR_DIVR_POSS,HDIV_DIVRR_DIVR_POSE) - -/****************** Bit definition for HDIV_DIVSTAT register ************************/ - -#define HDIV_DIVSTAT_SIGN_POS 2U -#define HDIV_DIVSTAT_SIGN_MSK BIT(HDIV_DIVSTAT_SIGN_POS) - -#define HDIV_DIVSTAT_DIV0_POS 1U -#define HDIV_DIVSTAT_DIV0_MSK BIT(HDIV_DIVSTAT_DIV0_POS) - -#define HDIV_DIVSTAT_BUSY_POS 0U -#define HDIV_DIVSTAT_BUSY_MSK BIT(HDIV_DIVSTAT_BUSY_POS) - -typedef struct -{ - __IO uint32_t DIVDR; - __IO uint32_t DIVSR; - __I uint32_t DIVQR; - __I uint32_t DIVRR; - __I uint32_t DIVSTAT; -} HDIV_TypeDef; - - - - - -#endif diff --git a/bsp/essemi/es32f0271/libraries/CMSIS/Device/EastSoft/ES32F0271/Include/ES32F0271/reg_i2c.h b/bsp/essemi/es32f0271/libraries/CMSIS/Device/EastSoft/ES32F0271/Include/ES32F0271/reg_i2c.h deleted file mode 100644 index 887eb01e03..0000000000 --- a/bsp/essemi/es32f0271/libraries/CMSIS/Device/EastSoft/ES32F0271/Include/ES32F0271/reg_i2c.h +++ /dev/null @@ -1,623 +0,0 @@ -/** - ************************************************************************************** - * @file REG_I2C.h - * @brief I2C Head File - * - * @version V0.01 - * @date 4/12/2018 - * @author Eastsoft MCU Software Team - * @note - * - * Copyright (C) 2018 Shanghai Eastsoft Microelectronics Co., Ltd. ALL rights reserved. - * - ************************************************************************************** - */ - -#ifndef __REG_I2C_H__ -#define __REG_I2C_H__ - - -/******************************************************************************/ -/* 设备特殊寄存器结构定义 */ -/******************************************************************************/ - -/* 允许匿名结构和匿名联合 */ -/* #pragma anon_unions */ - -/****************** Bit definition for I2C_CON1 register ************************/ - -#define I2C_CON1_PECEN_POS 23U -#define I2C_CON1_PECEN_MSK BIT(I2C_CON1_PECEN_POS) - -#define I2C_CON1_ALERTEN_POS 22U -#define I2C_CON1_ALERTEN_MSK BIT(I2C_CON1_ALERTEN_POS) - -#define I2C_CON1_SMBDEN_POS 21U -#define I2C_CON1_SMBDEN_MSK BIT(I2C_CON1_SMBDEN_POS) - -#define I2C_CON1_SMBHEN_POS 20U -#define I2C_CON1_SMBHEN_MSK BIT(I2C_CON1_SMBHEN_POS) - -#define I2C_CON1_GCEN_POS 19U -#define I2C_CON1_GCEN_MSK BIT(I2C_CON1_GCEN_POS) - -#define I2C_CON1_NOSTRETCH_POS 17U -#define I2C_CON1_NOSTRETCH_MSK BIT(I2C_CON1_NOSTRETCH_POS) - -#define I2C_CON1_SBC_POS 16U -#define I2C_CON1_SBC_MSK BIT(I2C_CON1_SBC_POS) - -#define I2C_CON1_RXDMAEN_POS 15U -#define I2C_CON1_RXDMAEN_MSK BIT(I2C_CON1_RXDMAEN_POS) - -#define I2C_CON1_TXDMAEN_POS 14U -#define I2C_CON1_TXDMAEN_MSK BIT(I2C_CON1_TXDMAEN_POS) - -#define I2C_CON1_DNF_POSS 8U -#define I2C_CON1_DNF_POSE 11U -#define I2C_CON1_DNF_MSK BITS(I2C_CON1_DNF_POSS,I2C_CON1_DNF_POSE) - -#define I2C_CON1_PE_POS 0U -#define I2C_CON1_PE_MSK BIT(I2C_CON1_PE_POS) - -/****************** Bit definition for I2C_CON2 register ************************/ - -#define I2C_CON2_ACK_UPD_POS 29U -#define I2C_CON2_ACK_UPD_MSK BIT(I2C_CON2_ACK_UPD_POS) - -#define I2C_CON2_HOLDACK_POS 28U -#define I2C_CON2_HOLDACK_MSK BIT(I2C_CON2_HOLDACK_POS) - -#define I2C_CON2_PECBYTE_POS 26U -#define I2C_CON2_PECBYTE_MSK BIT(I2C_CON2_PECBYTE_POS) - -#define I2C_CON2_AUTOEND_POS 25U -#define I2C_CON2_AUTOEND_MSK BIT(I2C_CON2_AUTOEND_POS) - -#define I2C_CON2_RELOAD_POS 24U -#define I2C_CON2_RELOAD_MSK BIT(I2C_CON2_RELOAD_POS) - -#define I2C_CON2_NBYTES_POSS 16U -#define I2C_CON2_NBYTES_POSE 23U -#define I2C_CON2_NBYTES_MSK BITS(I2C_CON2_NBYTES_POSS,I2C_CON2_NBYTES_POSE) - -#define I2C_CON2_NACK_POS 15U -#define I2C_CON2_NACK_MSK BIT(I2C_CON2_NACK_POS) - -#define I2C_CON2_STOP_POS 14U -#define I2C_CON2_STOP_MSK BIT(I2C_CON2_STOP_POS) - -#define I2C_CON2_START_POS 13U -#define I2C_CON2_START_MSK BIT(I2C_CON2_START_POS) - -#define I2C_CON2_HEAD10R_POS 12U -#define I2C_CON2_HEAD10R_MSK BIT(I2C_CON2_HEAD10R_POS) - -#define I2C_CON2_ADD10_POS 11U -#define I2C_CON2_ADD10_MSK BIT(I2C_CON2_ADD10_POS) - -#define I2C_CON2_RD_WRN_POS 10U -#define I2C_CON2_RD_WRN_MSK BIT(I2C_CON2_RD_WRN_POS) - -#define I2C_CON2_SADD_POSS 0U -#define I2C_CON2_SADD_POSE 9U -#define I2C_CON2_SADD_MSK BITS(I2C_CON2_SADD_POSS,I2C_CON2_SADD_POSE) - -/****************** Bit definition for I2C_ADDR1 register ************************/ - -#define I2C_ADDR1_OA1EN_POS 15U -#define I2C_ADDR1_OA1EN_MSK BIT(I2C_ADDR1_OA1EN_POS) - -#define I2C_ADDR1_OA1MODE_POS 10U -#define I2C_ADDR1_OA1MODE_MSK BIT(I2C_ADDR1_OA1MODE_POS) - -#define I2C_ADDR1_OA1_POSS 0U -#define I2C_ADDR1_OA1_POSE 9U -#define I2C_ADDR1_OA1_MSK BITS(I2C_ADDR1_OA1_POSS,I2C_ADDR1_OA1_POSE) - -/****************** Bit definition for I2C_ADDR2 register ************************/ - -#define I2C_ADDR2_OA2EN_POS 15U -#define I2C_ADDR2_OA2EN_MSK BIT(I2C_ADDR2_OA2EN_POS) - -#define I2C_ADDR2_OA2MSK_POSS 8U -#define I2C_ADDR2_OA2MSK_POSE 10U -#define I2C_ADDR2_OA2MSK_MSK BITS(I2C_ADDR2_OA2MSK_POSS,I2C_ADDR2_OA2MSK_POSE) - -#define I2C_ADDR2_OA2_POSS 1U -#define I2C_ADDR2_OA2_POSE 7U -#define I2C_ADDR2_OA2_MSK BITS(I2C_ADDR2_OA2_POSS,I2C_ADDR2_OA2_POSE) - -/****************** Bit definition for I2C_TIMINGR register ************************/ - -#define I2C_TIMINGR_PRESC_POSS 28U -#define I2C_TIMINGR_PRESC_POSE 31U -#define I2C_TIMINGR_PRESC_MSK BITS(I2C_TIMINGR_PRESC_POSS,I2C_TIMINGR_PRESC_POSE) - -#define I2C_TIMINGR_SCLDEL_POSS 20U -#define I2C_TIMINGR_SCLDEL_POSE 23U -#define I2C_TIMINGR_SCLDEL_MSK BITS(I2C_TIMINGR_SCLDEL_POSS,I2C_TIMINGR_SCLDEL_POSE) - -#define I2C_TIMINGR_SDADEL_POSS 16U -#define I2C_TIMINGR_SDADEL_POSE 19U -#define I2C_TIMINGR_SDADEL_MSK BITS(I2C_TIMINGR_SDADEL_POSS,I2C_TIMINGR_SDADEL_POSE) - -#define I2C_TIMINGR_SCLH_POSS 8U -#define I2C_TIMINGR_SCLH_POSE 15U -#define I2C_TIMINGR_SCLH_MSK BITS(I2C_TIMINGR_SCLH_POSS,I2C_TIMINGR_SCLH_POSE) - -#define I2C_TIMINGR_SCLL_POSS 0U -#define I2C_TIMINGR_SCLL_POSE 7U -#define I2C_TIMINGR_SCLL_MSK BITS(I2C_TIMINGR_SCLL_POSS,I2C_TIMINGR_SCLL_POSE) - -/****************** Bit definition for I2C_TIMEOUTR register ************************/ - -#define I2C_TIMEOUTR_TEXTEN_POS 31U -#define I2C_TIMEOUTR_TEXTEN_MSK BIT(I2C_TIMEOUTR_TEXTEN_POS) - -#define I2C_TIMEOUTR_TIMEOUTB_POSS 16U -#define I2C_TIMEOUTR_TIMEOUTB_POSE 27U -#define I2C_TIMEOUTR_TIMEOUTB_MSK BITS(I2C_TIMEOUTR_TIMEOUTB_POSS,I2C_TIMEOUTR_TIMEOUTB_POSE) - -#define I2C_TIMEOUTR_TIMEOUTEN_POS 15U -#define I2C_TIMEOUTR_TIMEOUTEN_MSK BIT(I2C_TIMEOUTR_TIMEOUTEN_POS) - -#define I2C_TIMEOUTR_TIDLE_POS 12U -#define I2C_TIMEOUTR_TIDLE_MSK BIT(I2C_TIMEOUTR_TIDLE_POS) - -#define I2C_TIMEOUTR_TIMEOUTA_POSS 0U -#define I2C_TIMEOUTR_TIMEOUTA_POSE 11U -#define I2C_TIMEOUTR_TIMEOUTA_MSK BITS(I2C_TIMEOUTR_TIMEOUTA_POSS,I2C_TIMEOUTR_TIMEOUTA_POSE) - -/****************** Bit definition for I2C_STAT register ************************/ - -#define I2C_STAT_ADDCODE_POSS 17U -#define I2C_STAT_ADDCODE_POSE 23U -#define I2C_STAT_ADDCODE_MSK BITS(I2C_STAT_ADDCODE_POSS,I2C_STAT_ADDCODE_POSE) - -#define I2C_STAT_DIR_POS 16U -#define I2C_STAT_DIR_MSK BIT(I2C_STAT_DIR_POS) - -#define I2C_STAT_BUSY_POS 15U -#define I2C_STAT_BUSY_MSK BIT(I2C_STAT_BUSY_POS) - -#define I2C_STAT_TCR_POS 11U -#define I2C_STAT_TCR_MSK BIT(I2C_STAT_TCR_POS) - -#define I2C_STAT_TC_POS 10U -#define I2C_STAT_TC_MSK BIT(I2C_STAT_TC_POS) - -#define I2C_STAT_RXTH_POS 9U -#define I2C_STAT_RXTH_MSK BIT(I2C_STAT_RXTH_POS) - -#define I2C_STAT_RXUD_POS 8U -#define I2C_STAT_RXUD_MSK BIT(I2C_STAT_RXUD_POS) - -#define I2C_STAT_RXOV_POS 7U -#define I2C_STAT_RXOV_MSK BIT(I2C_STAT_RXOV_POS) - -#define I2C_STAT_RXF_POS 6U -#define I2C_STAT_RXF_MSK BIT(I2C_STAT_RXF_POS) - -#define I2C_STAT_RXE_POS 5U -#define I2C_STAT_RXE_MSK BIT(I2C_STAT_RXE_POS) - -#define I2C_STAT_TXTH_POS 4U -#define I2C_STAT_TXTH_MSK BIT(I2C_STAT_TXTH_POS) - -#define I2C_STAT_TXUD_POS 3U -#define I2C_STAT_TXUD_MSK BIT(I2C_STAT_TXUD_POS) - -#define I2C_STAT_TXOV_POS 2U -#define I2C_STAT_TXOV_MSK BIT(I2C_STAT_TXOV_POS) - -#define I2C_STAT_TXF_POS 1U -#define I2C_STAT_TXF_MSK BIT(I2C_STAT_TXF_POS) - -#define I2C_STAT_TXE_POS 0U -#define I2C_STAT_TXE_MSK BIT(I2C_STAT_TXE_POS) - -/****************** Bit definition for I2C_FCON register ************************/ - -#define I2C_FCON_RXFTH_POSS 14U -#define I2C_FCON_RXFTH_POSE 15U -#define I2C_FCON_RXFTH_MSK BITS(I2C_FCON_RXFTH_POSS,I2C_FCON_RXFTH_POSE) - -#define I2C_FCON_RXFRST_POS 13U -#define I2C_FCON_RXFRST_MSK BIT(I2C_FCON_RXFRST_POS) - -#define I2C_FCON_RXFLV_POSS 8U -#define I2C_FCON_RXFLV_POSE 12U -#define I2C_FCON_RXFLV_MSK BITS(I2C_FCON_RXFLV_POSS,I2C_FCON_RXFLV_POSE) - -#define I2C_FCON_TXFTH_POSS 6U -#define I2C_FCON_TXFTH_POSE 7U -#define I2C_FCON_TXFTH_MSK BITS(I2C_FCON_TXFTH_POSS,I2C_FCON_TXFTH_POSE) - -#define I2C_FCON_TXFRST_POS 5U -#define I2C_FCON_TXFRST_MSK BIT(I2C_FCON_TXFRST_POS) - -#define I2C_FCON_TXFLV_POSS 0U -#define I2C_FCON_TXFLV_POSE 4U -#define I2C_FCON_TXFLV_MSK BITS(I2C_FCON_TXFLV_POSS,I2C_FCON_TXFLV_POSE) - -/****************** Bit definition for I2C_PECR register ************************/ - -#define I2C_PECR_PEC_POSS 0U -#define I2C_PECR_PEC_POSE 7U -#define I2C_PECR_PEC_MSK BITS(I2C_PECR_PEC_POSS,I2C_PECR_PEC_POSE) - -/****************** Bit definition for I2C_RXDATA register ************************/ - -#define I2C_RXDATA_RXDATA_POSS 0U -#define I2C_RXDATA_RXDATA_POSE 7U -#define I2C_RXDATA_RXDATA_MSK BITS(I2C_RXDATA_RXDATA_POSS,I2C_RXDATA_RXDATA_POSE) - -/****************** Bit definition for I2C_TXDATA register ************************/ - -#define I2C_TXDATA_TXDATA_POSS 0U -#define I2C_TXDATA_TXDATA_POSE 7U -#define I2C_TXDATA_TXDATA_MSK BITS(I2C_TXDATA_TXDATA_POSS,I2C_TXDATA_TXDATA_POSE) - -/****************** Bit definition for I2C_IER register ************************/ - -#define I2C_IER_ALERTIE_POS 20U -#define I2C_IER_ALERTIE_MSK BIT(I2C_IER_ALERTIE_POS) - -#define I2C_IER_TOUTIE_POS 19U -#define I2C_IER_TOUTIE_MSK BIT(I2C_IER_TOUTIE_POS) - -#define I2C_IER_PECEIE_POS 18U -#define I2C_IER_PECEIE_MSK BIT(I2C_IER_PECEIE_POS) - -#define I2C_IER_ARLOIE_POS 17U -#define I2C_IER_ARLOIE_MSK BIT(I2C_IER_ARLOIE_POS) - -#define I2C_IER_BERRIE_POS 16U -#define I2C_IER_BERRIE_MSK BIT(I2C_IER_BERRIE_POS) - -#define I2C_IER_STOPIE_POS 14U -#define I2C_IER_STOPIE_MSK BIT(I2C_IER_STOPIE_POS) - -#define I2C_IER_NACKIE_POS 13U -#define I2C_IER_NACKIE_MSK BIT(I2C_IER_NACKIE_POS) - -#define I2C_IER_ADDRIE_POS 12U -#define I2C_IER_ADDRIE_MSK BIT(I2C_IER_ADDRIE_POS) - -#define I2C_IER_TCRIE_POS 11U -#define I2C_IER_TCRIE_MSK BIT(I2C_IER_TCRIE_POS) - -#define I2C_IER_TCIE_POS 10U -#define I2C_IER_TCIE_MSK BIT(I2C_IER_TCIE_POS) - -#define I2C_IER_RXTHIE_POS 9U -#define I2C_IER_RXTHIE_MSK BIT(I2C_IER_RXTHIE_POS) - -#define I2C_IER_RXUDIE_POS 8U -#define I2C_IER_RXUDIE_MSK BIT(I2C_IER_RXUDIE_POS) - -#define I2C_IER_RXOVIE_POS 7U -#define I2C_IER_RXOVIE_MSK BIT(I2C_IER_RXOVIE_POS) - -#define I2C_IER_RXFIE_POS 6U -#define I2C_IER_RXFIE_MSK BIT(I2C_IER_RXFIE_POS) - -#define I2C_IER_TXTHIE_POS 4U -#define I2C_IER_TXTHIE_MSK BIT(I2C_IER_TXTHIE_POS) - -#define I2C_IER_TXUDIE_POS 3U -#define I2C_IER_TXUDIE_MSK BIT(I2C_IER_TXUDIE_POS) - -#define I2C_IER_TXOVIE_POS 2U -#define I2C_IER_TXOVIE_MSK BIT(I2C_IER_TXOVIE_POS) - -#define I2C_IER_TXEIE_POS 0U -#define I2C_IER_TXEIE_MSK BIT(I2C_IER_TXEIE_POS) - -/****************** Bit definition for I2C_IDR register ************************/ - -#define I2C_IDR_ALERTID_POS 20U -#define I2C_IDR_ALERTID_MSK BIT(I2C_IDR_ALERTID_POS) - -#define I2C_IDR_TOUTID_POS 19U -#define I2C_IDR_TOUTID_MSK BIT(I2C_IDR_TOUTID_POS) - -#define I2C_IDR_PECEID_POS 18U -#define I2C_IDR_PECEID_MSK BIT(I2C_IDR_PECEID_POS) - -#define I2C_IDR_ARLOID_POS 17U -#define I2C_IDR_ARLOID_MSK BIT(I2C_IDR_ARLOID_POS) - -#define I2C_IDR_BERRID_POS 16U -#define I2C_IDR_BERRID_MSK BIT(I2C_IDR_BERRID_POS) - -#define I2C_IDR_STOPID_POS 14U -#define I2C_IDR_STOPID_MSK BIT(I2C_IDR_STOPID_POS) - -#define I2C_IDR_NACKID_POS 13U -#define I2C_IDR_NACKID_MSK BIT(I2C_IDR_NACKID_POS) - -#define I2C_IDR_ADDRID_POS 12U -#define I2C_IDR_ADDRID_MSK BIT(I2C_IDR_ADDRID_POS) - -#define I2C_IDR_TCRID_POS 11U -#define I2C_IDR_TCRID_MSK BIT(I2C_IDR_TCRID_POS) - -#define I2C_IDR_TCID_POS 10U -#define I2C_IDR_TCID_MSK BIT(I2C_IDR_TCID_POS) - -#define I2C_IDR_RXTHID_POS 9U -#define I2C_IDR_RXTHID_MSK BIT(I2C_IDR_RXTHID_POS) - -#define I2C_IDR_RXUDID_POS 8U -#define I2C_IDR_RXUDID_MSK BIT(I2C_IDR_RXUDID_POS) - -#define I2C_IDR_RXOVID_POS 7U -#define I2C_IDR_RXOVID_MSK BIT(I2C_IDR_RXOVID_POS) - -#define I2C_IDR_RXFID_POS 6U -#define I2C_IDR_RXFID_MSK BIT(I2C_IDR_RXFID_POS) - -#define I2C_IDR_TXTHID_POS 4U -#define I2C_IDR_TXTHID_MSK BIT(I2C_IDR_TXTHID_POS) - -#define I2C_IDR_TXUDID_POS 3U -#define I2C_IDR_TXUDID_MSK BIT(I2C_IDR_TXUDID_POS) - -#define I2C_IDR_TXOVID_POS 2U -#define I2C_IDR_TXOVID_MSK BIT(I2C_IDR_TXOVID_POS) - -#define I2C_IDR_TXEID_POS 0U -#define I2C_IDR_TXEID_MSK BIT(I2C_IDR_TXEID_POS) - -/****************** Bit definition for I2C_IVS register ************************/ - -#define I2C_IVS_ALERTIV_POS 20U -#define I2C_IVS_ALERTIV_MSK BIT(I2C_IVS_ALERTIV_POS) - -#define I2C_IVS_TOUTIV_POS 19U -#define I2C_IVS_TOUTIV_MSK BIT(I2C_IVS_TOUTIV_POS) - -#define I2C_IVS_PECEIV_POS 18U -#define I2C_IVS_PECEIV_MSK BIT(I2C_IVS_PECEIV_POS) - -#define I2C_IVS_ARLOIV_POS 17U -#define I2C_IVS_ARLOIV_MSK BIT(I2C_IVS_ARLOIV_POS) - -#define I2C_IVS_BERRIV_POS 16U -#define I2C_IVS_BERRIV_MSK BIT(I2C_IVS_BERRIV_POS) - -#define I2C_IVS_STOPIV_POS 14U -#define I2C_IVS_STOPIV_MSK BIT(I2C_IVS_STOPIV_POS) - -#define I2C_IVS_NACKIV_POS 13U -#define I2C_IVS_NACKIV_MSK BIT(I2C_IVS_NACKIV_POS) - -#define I2C_IVS_ADDRIV_POS 12U -#define I2C_IVS_ADDRIV_MSK BIT(I2C_IVS_ADDRIV_POS) - -#define I2C_IVS_TCRIV_POS 11U -#define I2C_IVS_TCRIV_MSK BIT(I2C_IVS_TCRIV_POS) - -#define I2C_IVS_TCIV_POS 10U -#define I2C_IVS_TCIV_MSK BIT(I2C_IVS_TCIV_POS) - -#define I2C_IVS_RXTHIV_POS 9U -#define I2C_IVS_RXTHIV_MSK BIT(I2C_IVS_RXTHIV_POS) - -#define I2C_IVS_RXUDIV_POS 8U -#define I2C_IVS_RXUDIV_MSK BIT(I2C_IVS_RXUDIV_POS) - -#define I2C_IVS_RXOVIV_POS 7U -#define I2C_IVS_RXOVIV_MSK BIT(I2C_IVS_RXOVIV_POS) - -#define I2C_IVS_RXFIV_POS 6U -#define I2C_IVS_RXFIV_MSK BIT(I2C_IVS_RXFIV_POS) - -#define I2C_IVS_TXTHIV_POS 4U -#define I2C_IVS_TXTHIV_MSK BIT(I2C_IVS_TXTHIV_POS) - -#define I2C_IVS_TXUDIV_POS 3U -#define I2C_IVS_TXUDIV_MSK BIT(I2C_IVS_TXUDIV_POS) - -#define I2C_IVS_TXOVIV_POS 2U -#define I2C_IVS_TXOVIV_MSK BIT(I2C_IVS_TXOVIV_POS) - -#define I2C_IVS_TXEIV_POS 0U -#define I2C_IVS_TXEIV_MSK BIT(I2C_IVS_TXEIV_POS) - -/****************** Bit definition for I2C_RIF register ************************/ - -#define I2C_RIF_ALERTRI_POS 20U -#define I2C_RIF_ALERTRI_MSK BIT(I2C_RIF_ALERTRI_POS) - -#define I2C_RIF_TOUTRI_POS 19U -#define I2C_RIF_TOUTRI_MSK BIT(I2C_RIF_TOUTRI_POS) - -#define I2C_RIF_PECERI_POS 18U -#define I2C_RIF_PECERI_MSK BIT(I2C_RIF_PECERI_POS) - -#define I2C_RIF_ARLORI_POS 17U -#define I2C_RIF_ARLORI_MSK BIT(I2C_RIF_ARLORI_POS) - -#define I2C_RIF_BERRRI_POS 16U -#define I2C_RIF_BERRRI_MSK BIT(I2C_RIF_BERRRI_POS) - -#define I2C_RIF_STOPRI_POS 14U -#define I2C_RIF_STOPRI_MSK BIT(I2C_RIF_STOPRI_POS) - -#define I2C_RIF_NACKRI_POS 13U -#define I2C_RIF_NACKRI_MSK BIT(I2C_RIF_NACKRI_POS) - -#define I2C_RIF_ADDRRI_POS 12U -#define I2C_RIF_ADDRRI_MSK BIT(I2C_RIF_ADDRRI_POS) - -#define I2C_RIF_TCRRI_POS 11U -#define I2C_RIF_TCRRI_MSK BIT(I2C_RIF_TCRRI_POS) - -#define I2C_RIF_TCRI_POS 10U -#define I2C_RIF_TCRI_MSK BIT(I2C_RIF_TCRI_POS) - -#define I2C_RIF_RXTHRI_POS 9U -#define I2C_RIF_RXTHRI_MSK BIT(I2C_RIF_RXTHRI_POS) - -#define I2C_RIF_RXUDRI_POS 8U -#define I2C_RIF_RXUDRI_MSK BIT(I2C_RIF_RXUDRI_POS) - -#define I2C_RIF_RXOVRI_POS 7U -#define I2C_RIF_RXOVRI_MSK BIT(I2C_RIF_RXOVRI_POS) - -#define I2C_RIF_RXFRI_POS 6U -#define I2C_RIF_RXFRI_MSK BIT(I2C_RIF_RXFRI_POS) - -#define I2C_RIF_TXTHRI_POS 4U -#define I2C_RIF_TXTHRI_MSK BIT(I2C_RIF_TXTHRI_POS) - -#define I2C_RIF_TXUDRI_POS 3U -#define I2C_RIF_TXUDRI_MSK BIT(I2C_RIF_TXUDRI_POS) - -#define I2C_RIF_TXOVRI_POS 2U -#define I2C_RIF_TXOVRI_MSK BIT(I2C_RIF_TXOVRI_POS) - -#define I2C_RIF_TXERI_POS 0U -#define I2C_RIF_TXERI_MSK BIT(I2C_RIF_TXERI_POS) - -/****************** Bit definition for I2C_IFM register ************************/ - -#define I2C_IFM_ALERTFM_POS 20U -#define I2C_IFM_ALERTFM_MSK BIT(I2C_IFM_ALERTFM_POS) - -#define I2C_IFM_TOUTFM_POS 19U -#define I2C_IFM_TOUTFM_MSK BIT(I2C_IFM_TOUTFM_POS) - -#define I2C_IFM_PECEFM_POS 18U -#define I2C_IFM_PECEFM_MSK BIT(I2C_IFM_PECEFM_POS) - -#define I2C_IFM_ARLOFM_POS 17U -#define I2C_IFM_ARLOFM_MSK BIT(I2C_IFM_ARLOFM_POS) - -#define I2C_IFM_BERRFM_POS 16U -#define I2C_IFM_BERRFM_MSK BIT(I2C_IFM_BERRFM_POS) - -#define I2C_IFM_STOPFM_POS 14U -#define I2C_IFM_STOPFM_MSK BIT(I2C_IFM_STOPFM_POS) - -#define I2C_IFM_NACKFM_POS 13U -#define I2C_IFM_NACKFM_MSK BIT(I2C_IFM_NACKFM_POS) - -#define I2C_IFM_ADDRFM_POS 12U -#define I2C_IFM_ADDRFM_MSK BIT(I2C_IFM_ADDRFM_POS) - -#define I2C_IFM_TCRFM_POS 11U -#define I2C_IFM_TCRFM_MSK BIT(I2C_IFM_TCRFM_POS) - -#define I2C_IFM_TCFM_POS 10U -#define I2C_IFM_TCFM_MSK BIT(I2C_IFM_TCFM_POS) - -#define I2C_IFM_RXTHFM_POS 9U -#define I2C_IFM_RXTHFM_MSK BIT(I2C_IFM_RXTHFM_POS) - -#define I2C_IFM_RXUDFM_POS 8U -#define I2C_IFM_RXUDFM_MSK BIT(I2C_IFM_RXUDFM_POS) - -#define I2C_IFM_RXOVFM_POS 7U -#define I2C_IFM_RXOVFM_MSK BIT(I2C_IFM_RXOVFM_POS) - -#define I2C_IFM_RXFFM_POS 6U -#define I2C_IFM_RXFFM_MSK BIT(I2C_IFM_RXFFM_POS) - -#define I2C_IFM_TXTHFM_POS 4U -#define I2C_IFM_TXTHFM_MSK BIT(I2C_IFM_TXTHFM_POS) - -#define I2C_IFM_TXUDFM_POS 3U -#define I2C_IFM_TXUDFM_MSK BIT(I2C_IFM_TXUDFM_POS) - -#define I2C_IFM_TXOVFM_POS 2U -#define I2C_IFM_TXOVFM_MSK BIT(I2C_IFM_TXOVFM_POS) - -#define I2C_IFM_TXEFM_POS 0U -#define I2C_IFM_TXEFM_MSK BIT(I2C_IFM_TXEFM_POS) - -/****************** Bit definition for I2C_ICR register ************************/ - -#define I2C_ICR_ALERTIC_POS 20U -#define I2C_ICR_ALERTIC_MSK BIT(I2C_ICR_ALERTIC_POS) - -#define I2C_ICR_TOUTIC_POS 19U -#define I2C_ICR_TOUTIC_MSK BIT(I2C_ICR_TOUTIC_POS) - -#define I2C_ICR_PECEIC_POS 18U -#define I2C_ICR_PECEIC_MSK BIT(I2C_ICR_PECEIC_POS) - -#define I2C_ICR_ARLOIC_POS 17U -#define I2C_ICR_ARLOIC_MSK BIT(I2C_ICR_ARLOIC_POS) - -#define I2C_ICR_BERRIC_POS 16U -#define I2C_ICR_BERRIC_MSK BIT(I2C_ICR_BERRIC_POS) - -#define I2C_ICR_STOPIC_POS 14U -#define I2C_ICR_STOPIC_MSK BIT(I2C_ICR_STOPIC_POS) - -#define I2C_ICR_NACKIC_POS 13U -#define I2C_ICR_NACKIC_MSK BIT(I2C_ICR_NACKIC_POS) - -#define I2C_ICR_ADDRIC_POS 12U -#define I2C_ICR_ADDRIC_MSK BIT(I2C_ICR_ADDRIC_POS) - -#define I2C_ICR_TCRIC_POS 11U -#define I2C_ICR_TCRIC_MSK BIT(I2C_ICR_TCRIC_POS) - -#define I2C_ICR_TCIC_POS 10U -#define I2C_ICR_TCIC_MSK BIT(I2C_ICR_TCIC_POS) - -#define I2C_ICR_RXTHIC_POS 9U -#define I2C_ICR_RXTHIC_MSK BIT(I2C_ICR_RXTHIC_POS) - -#define I2C_ICR_RXUDIC_POS 8U -#define I2C_ICR_RXUDIC_MSK BIT(I2C_ICR_RXUDIC_POS) - -#define I2C_ICR_RXOVIC_POS 7U -#define I2C_ICR_RXOVIC_MSK BIT(I2C_ICR_RXOVIC_POS) - -#define I2C_ICR_RXFIC_POS 6U -#define I2C_ICR_RXFIC_MSK BIT(I2C_ICR_RXFIC_POS) - -#define I2C_ICR_TXTHIC_POS 4U -#define I2C_ICR_TXTHIC_MSK BIT(I2C_ICR_TXTHIC_POS) - -#define I2C_ICR_TXUDIC_POS 3U -#define I2C_ICR_TXUDIC_MSK BIT(I2C_ICR_TXUDIC_POS) - -#define I2C_ICR_TXOVIC_POS 2U -#define I2C_ICR_TXOVIC_MSK BIT(I2C_ICR_TXOVIC_POS) - -#define I2C_ICR_TXEIC_POS 0U -#define I2C_ICR_TXEIC_MSK BIT(I2C_ICR_TXEIC_POS) - -typedef struct -{ - __IO uint32_t CON1; - __IO uint32_t CON2; - __IO uint32_t ADDR1; - __IO uint32_t ADDR2; - __IO uint32_t TIMINGR; - __IO uint32_t TIMEOUTR; - __I uint32_t STAT; - __IO uint32_t FCON; - __I uint32_t PECR; - __I uint32_t RXDATA; - __O uint32_t TXDATA; - __O uint32_t IER; - __O uint32_t IDR; - __I uint32_t IVS; - __I uint32_t RIF; - __I uint32_t IFM; - __O uint32_t ICR; -} I2C_TypeDef; - - - - - -#endif diff --git a/bsp/essemi/es32f0271/libraries/CMSIS/Device/EastSoft/ES32F0271/Include/ES32F0271/reg_iwdg.h b/bsp/essemi/es32f0271/libraries/CMSIS/Device/EastSoft/ES32F0271/Include/ES32F0271/reg_iwdg.h deleted file mode 100644 index a5c657c89a..0000000000 --- a/bsp/essemi/es32f0271/libraries/CMSIS/Device/EastSoft/ES32F0271/Include/ES32F0271/reg_iwdg.h +++ /dev/null @@ -1,73 +0,0 @@ -/** - ************************************************************************************** - * @file reg_IWDG.h - * @brief IWDG Head File - * - * @version V1.00.01 - * @data 19/10/2018 - * @author Eastsoft AE Team - * @note - * - * Copyright (C) 2018 Shanghai Eastsoft Microelectronics Co., Ltd. ALL rights reserved. - * - ************************************************************************************** - */ - -#ifndef __IWDG_H__ -#define __IWDG_H__ - -typedef struct -{ - __O uint32_t KR ; /* 0x00 IWDG_KR - Key register */ - __IO uint32_t PR ; /* 0x04 IWDG_PR - Prescaler register */ - __IO uint32_t RLR ; /* 0x08 IWDG_RLR - Reload register */ - __I uint32_t FR ; /* 0x0C IWDG_SR - Status register */ - __IO uint32_t WINR; /* 0x10 IWDG_WINR - Window register */ -} IWDG_TypeDef; - -/******************************************************************************/ -/* Ȧs줸wq */ -/******************************************************************************/ - -/* #pragma anon_unions */ - -/****************** Bit definition for IWDG_KR register ************************/ - -#define IWDG_KR_KEY_POSS 0U -#define IWDG_KR_KEY_POSE 15U -#define IWDG_KR_KEY_MSK BITS(IWDG_KR_KEY_POSS,IWDG_KR_KEY_POSE) - -/****************** Bit definition for IWDG_PR register ************************/ - -#define IWDG_PR_PR_POSS 0U -#define IWDG_PR_PR_POSE 2U -#define IWDG_PR_PR_MSK BITS(IWDG_PR_PR_POSS,IWDG_PR_PR_POSE) - -/****************** Bit definition for IWDG_RLR register ************************/ - -#define IWDG_RLR_RL_POSS 0U -#define IWDG_RLR_RL_POSE 12U -#define IWDG_RLR_RL_MSK BITS(IWDG_RLR_RL_POSS,IWDG_RLR_RL_POSE) - -/****************** Bit definition for IWDG_FR register ************************/ - -#define IWDG_FR_BUSY_POS 15U -#define IWDG_FR_BUSY_MSK BIT(IWDG_FR_BUSY_POS) - -#define IWDG_FR_STR_POS 12U -#define IWDG_FR_STR_MSK BIT(IWDG_FR_STR_POS) - -#define IWDG_FR_CNT_POSS 0U -#define IWDG_FR_CNT_POSE 11U -#define IWDG_FR_CNT_MSK BITS(IWDG_FR_CNT_POSS,IWDG_FR_CNT_POSE) - -/****************** Bit definition for IWDG_WINR register ************************/ - -#define IWDG_WINR_WIN_POSS 0U -#define IWDG_WINR_WIN_POSE 31U -#define IWDG_WINR_WIN_MSK BITS(IWDG_WINR_WIN_POSS,IWDG_WINR_WIN_POSE) - - -#else -/* */ -#endif diff --git a/bsp/essemi/es32f0271/libraries/CMSIS/Device/EastSoft/ES32F0271/Include/ES32F0271/reg_mcm.h b/bsp/essemi/es32f0271/libraries/CMSIS/Device/EastSoft/ES32F0271/Include/ES32F0271/reg_mcm.h deleted file mode 100644 index ebb675dafe..0000000000 --- a/bsp/essemi/es32f0271/libraries/CMSIS/Device/EastSoft/ES32F0271/Include/ES32F0271/reg_mcm.h +++ /dev/null @@ -1,211 +0,0 @@ -/** - ************************************************************************************** - * @file reg_MCM.h - * @brief MCM Head File - * - * @version V1.00.01 - * @data 19/10/2018 - * @author Eastsoft AE Team - * @note - * - * Copyright (C) 2018 Shanghai Eastsoft Microelectronics Co., Ltd. ALL rights reserved. - * - ************************************************************************************** - */ - -#ifndef __MCM_H__ -#define __MCM_H__ - -typedef struct -{ - __IO uint32_t RAMP_INI; // 0x00 MCM Ramp Generator Initialization Register - __IO uint32_t RAMP_IDATA; // 0x04 MCM Ramp Generator Initial Data Register - __IO uint32_t RAMP_DIV; // 0x08 MCM Ramp Clock Divider Register - __IO uint32_t RAMP_SCALE; // 0x0C MCM Ramp Generator Output Scale Register - __IO uint32_t RAMP_STEP; // 0x10 MCM Step Increment of the Ramp Output Register - __IO uint32_t RAMP_SET; // 0x14 MCM Ramp Generator Reference Data Register - __IO uint32_t RAMP_EN; // 0x18 MCM Ramp Generator Enable Register - __I uint32_t RAMP_DO; // 0x1C MCM Ramp Generator Output Register - __IO uint32_t RMAP_CON; // 0x20 MCM Connect Ramp Generator to PI control Register - __IO uint32_t IX_UPD; // 0x24 MCM Inverse Transform Update Register - __IO uint32_t IX_VQ; // 0x28 MCM Inverse Park Transform Vq Input Register - __IO uint32_t IX_VD; // 0x2C MCM Inverse Park Transform Vd Input Register - __I uint32_t IX_VA; // 0x30 MCM Inverse Clarke Transform Va Output Register - __I uint32_t IX_VB; // 0x34 MCM Inverse Clarke Transform Vb Output Register - __I uint32_t IX_VC; // 0x38 MCM Inverse Clarke Transform Vc Output Register - __I uint32_t IX_VALPHA; // 0x3C MCM Inverse Clarke Transform Valpha Output Register - __I uint32_t IX_VBETA; // 0x40 MCM Inverse Clarke Transform Vbeta Output Register - __I uint32_t IX_SVMVA; // 0x44 MCM Inverse Clarke Transform SVPWM Va Output Register - __I uint32_t IX_SVMVB; // 0x48 MCM Inverse Clarke Transform SVPWM Vb Output Register - __I uint32_t IX_SVMVC; // 0x4C MCM Inverse Clarke Transform SVPWM Vc Output Register - __I uint32_t IX_DONE; // 0x50 MCM Inverse Transform Processing Status Register - __I uint32_t IX_SDONE; // 0x54 MCM Inverse SVPWM Process Status Register - __IO uint32_t IX_CON; // 0x58 MCM Connect PI Control To The Inverse Transform Register - __IO uint32_t IX_NORMAL; // 0x5C MCM Normal Clarke Inverse Transform Register - __IO uint32_t X_UPD; // 0x60 MCM Transform Function Update Register - __IO uint32_t X_IA; // 0x64 MCM Clarke Transform Ia Input Register - __IO uint32_t X_IB; // 0x68 MCM Clarke Transform Ib Input Register - __IO uint32_t X_IC; // 0x6C MCM Clarke Transform Ic Input Register - __I uint32_t X_IALPHA; // 0x70 MCM Clarke Transform Ialpha Output Register - __I uint32_t X_IBETA; // 0x74 MCM Clarke Transform Ibeta Output Register - __I uint32_t X_ID; // 0x78 MCM Park Transform Id Output Register - __I uint32_t X_IQ; // 0x7C MCM Park Transform Iq Output Register - __I uint32_t X_DONE; // 0x80 MCM Transform Process Status Register - __IO uint32_t X_CON; // 0x84 MCM Forward Transform Input Source Selection Register - uint32_t REV88; // 0x88 RESERVED - __IO uint32_t PI0_UPD; // 0x8C MCM PI Control 0 Update Register - __IO uint32_t PI0_INI; // 0x90 MCM Initialize PI Control 0 Register - __IO uint32_t PI0_IDATA; // 0x94 MCM PI Control 0 Initial Data Register - __IO uint32_t PI0_ELIMIT; // 0x98 MCM PI Control 0 Error Limit Register - __IO uint32_t PI0_KP; // 0x9C MCM PI Control 0 Kp Coefficient Register - __IO uint32_t PI0_KI; // 0xA0 MCM PI Control 0 Ki Coefficient Register - __IO uint32_t PI0_REF; // 0xA4 MCM PI Control 0 Reference Value Register - __IO uint32_t PI0_ACTUAL; // 0xA8 MCM PI Control 0 Actual Value Register - __IO uint32_t PI0_MIN; // 0xAC MCM PI Control 0 Minimum Output Register - __IO uint32_t PI0_MAX; // 0xB0 MCM PI Control 0 Maximum Output Register - __I uint32_t PI0_DO; // 0xB4 MCM PI Control 0 Data Out Register - __IO uint32_t PI0_OSCALE; // 0xB8 MCM PI Control 0 Data Output Scale Register - __I uint32_t PI_DONE; // 0xBC MCM PI Control Processing Status Register - __IO uint32_t PI1_UPD; // 0xC0 MCM PI Control 1 Update Register - __IO uint32_t PI1_INI; // 0xC4 MCM Initialize PI Control 1 Register - __IO uint32_t PI1_IDATA; // 0xC8 MCM PI Control 1 Initial Data Register - __IO uint32_t PI1_ELIMIT; // 0xCC MCM PI Control 1 Error Limit Register - __IO uint32_t PI1_KP; // 0xD0 MCM PI Control 1 Kp Coefficient Register - __IO uint32_t PI1_KI; // 0xD4 MCM PI Control 1 Ki Coefficient Register - __IO uint32_t PI1_REF; // 0xD8 MCM PI Control 1 Reference Value Register - __IO uint32_t PI1_ACTUAL; // 0xDC MCM PI Control 1 Actual Value Register - __IO uint32_t PI1_MIN; // 0xE0 MCM PI Control 1 Minimum Output Register - __IO uint32_t PI1_MAX; // 0xE4 MCM PI Control 1 Maximum Output Register - __I uint32_t PI1_DO; // 0xE8 MCM PI Control 1 Data Out Register - __IO uint32_t PI1_OSCALE; // 0xEC MCM PI Control 1 Data Output Scale Register - __IO uint32_t PI2_UPD; // 0xF0 MCM PI Control 2 Update Register - __IO uint32_t PI2_INI; // 0xF4 MCM Initialize PI Control 2 Register - __IO uint32_t PI2_IDATA; // 0xF8 MCM PI Control 2 Initial Data Register - __IO uint32_t PI2_ELIMIT; // 0xFC MCM PI Control 2 Error Limit Register - __IO uint32_t PI2_KP; // 0x100 MCM PI Control 2 Kp Coefficient Register - __IO uint32_t PI2_KI; // 0x104 MCM PI Control 2 Ki Coefficient Register - __IO uint32_t PI2_REF; // 0x108 MCM PI Control 2 Reference Value Register - __IO uint32_t PI2_ACTUAL; // 0x10C MCM PI Control 2 Actual Value Register - __IO uint32_t PI2_MIN; // 0x110 MCM PI Control 2 Minimum Output Register - __IO uint32_t PI2_MAX; // 0x114 MCM PI Control 2 Maximum Output Register - __I uint32_t PI2_DO; // 0x118 MCM PI Control 2 Data Out Register - __IO uint32_t PI2_OSCALE; // 0x11C MCM PI Control 2 Data Output Scale Register - __IO uint32_t COR_START; // 0x120 MCM Start CORDIC Calculation Register - __IO uint32_t COR_X; // 0x124 MCM CORDIC X Input Register - __IO uint32_t COR_Y; // 0x128 MCM CORDIC Y Input Register - __I uint32_t COR_RES; // 0x12C MCM CORDIC Result Register - __I uint32_t COR_DONE; // 0x130 MCM CORDIC Processing Status Register - __IO uint32_t COR_CON; // 0x134 MCM CORDIC Input Selection Register - uint32_t REV138; // 0x138 RESERVED - uint32_t REV13C; // 0x13C RESERVED - __IO uint32_t LPFA_INI; // 0x140 MCM LPF A Channel Initialize Register - __IO uint32_t LPFA_UPD; // 0x144 MCM LPF A Channel Update Register - __IO uint32_t LPFA_DIN; // 0x148 MCM LPF A Input Register - __IO uint32_t LPFA_A0; // 0x14C MCM LPF A a0 Coefficient Register - __IO uint32_t LPFA_B0; // 0x150 MCM LPF A b0 Coefficient Register - __IO uint32_t LPFA_B1; // 0x154 MCM LPF A b1 Coefficient Register - - __IO uint32_t LPFA_A0SCALE; // 0x158 MCM LPF A a0 Coefficient Scale Register - __IO uint32_t LPFA_B0SCALE; // 0x15C MCM LPF A b0 Coefficient Scale Register - __IO uint32_t LPFA_B1SCALE; // 0x160 MCM LPF A b1 Coefficient Scale Register - - __I uint32_t LPFA_DO; // 0x164 MCM LPF A Data Output Register - __I uint32_t LPFA_DONE; // 0x168 MCM LPF A Process Status Register - __IO uint32_t LPFB_INI; // 0x16C MCM LPF B Channel Initialize Register - __IO uint32_t LPFB_UPD; // 0x170 MCM LPF B Channel Update Register - __IO uint32_t LPFB_DIN; // 0x174 MCM LPF B Input Register - __IO uint32_t LPFB_A0; // 0x178 MCM LPF B a0 Coefficient Register - __IO uint32_t LPFB_B0; // 0x17C MCM LPF B b0 Coefficient Register - __IO uint32_t LPFB_B1; // 0x180 MCM LPF B b1 Coefficient Register - - __IO uint32_t LPFB_A0SCALE; // 0x184 MCM LPF B a0 Coefficient Scale Register - __IO uint32_t LPFB_B0SCALE; // 0x188 MCM LPF B b0 Coefficient Scale Register - __IO uint32_t LPFB_B1SCALE; // 0x18C MCM LPF B b1 Coefficient Scale Register - - __I uint32_t LPFB_DO; // 0x190 MCM LPF B Data Output Register - __I uint32_t LPFB_DONE; // 0x194 MCM LPF B Process Status Register - __IO uint32_t LPFC_INI; // 0x198 MCM LPF C Channel Initialize Register - __IO uint32_t LPFC_UPD; // 0x19C MCM LPF C Channel Update Register - __IO uint32_t LPFC_DIN; // 0x1A0 MCM LPF C Input Register - __IO uint32_t LPFC_A0; // 0x1A4 MCM LPF C a0 Coefficient Register - __IO uint32_t LPFC_B0; // 0x1A8 MCM LPF C b0 Coefficient Register - __IO uint32_t LPFC_B1; // 0x1AC MCM LPF C b1 Coefficient Register - - __IO uint32_t LPFC_A0SCALE; // 0x1B0 MCM LPF C a0 Coefficient Scale Register - __IO uint32_t LPFC_B0SCALE; // 0x1B4 MCM LPF C b0 Coefficient Scale Register - __IO uint32_t LPFC_B1SCALE; // 0x1B8 MCM LPF C b1 Coefficient Scale Register - - __I uint32_t LPFC_DO; // 0x1BC MCM LPF C Data Output Register - __I uint32_t LPFC_DONE; // 0x1C0 MCM LPF C Process Status Register - __IO uint32_t GL_UPD; // 0x1C4 MCM Global Update Register - __IO uint32_t GL_STAT; // 0x1C8 MCM Global Status Register - __IO uint32_t THETA_SIN; // 0x1CC MCM Sine Angle Register - __IO uint32_t THETA_COS; // 0x1D0 MCM Cosine Angle Register - __IO uint32_t PI_TYPE; // 0x1D4 MCM PI Control Type Register - __IO uint32_t MOTOR_DIR; // 0x1D8 MCM Motor Direction Register - __I uint32_t MCM_VER; // 0x1DC MCM Version Register - __IO uint32_t SMC_UPD; // 0x1E0 MCM Slide Mode Controller Update Register - __IO uint32_t SMC_INI; // 0x1E4 MCM Slide Mode Controller Initialization Register - __IO uint32_t SMC_ALPHAINI; // 0x1E8 MCM Slide Mode Controller Alpha Initial Data Register - __IO uint32_t SMC_BETAINI; // 0x1EC MCM Slide Mode Controller Beta Initial Data Register - __IO uint32_t SMC_A0; // 0x1F0 MCM Slide Mode Controller Dynamic LPF coefficient Register - __IO uint32_t SMC_ELIMIT; // 0x1F4 MCM Slide Mode Controller Error Limit Register - __IO uint32_t SMC_KSLIDE; // 0x1F8 MCM Slide Mode Controller Z Factor Error Amplification Register - __I uint32_t SMC_DONE; // 0x1FC MCM Slide Mode Controller Process Status Register - __IO uint32_t SMC_IEALPHA; // 0x200 MCM SMC Estimated Current Alpha Register - __IO uint32_t SMC_IEBETA; // 0x204 MCM SMC Estimated Current Beta Register - __IO uint32_t SMC_IALPHA; // 0x208 MCM SMC Measured Current Alpha Register - __IO uint32_t SMC_IBETA; // 0x20C MCM SMC Measured Current Beta Register - __IO uint32_t SMC_DISI; // 0x210 MCM SMC Estimated Current Input Selection Register - __I uint32_t SMC_ZALPHA; // 0x214 MCM SMC Z Factor Alpha Register - __I uint32_t SMC_ZBETA; // 0x218 MCM SMC Z Factor Beta Register - __I uint32_t SMC_BEMF1A; // 0x21C MCM SMC Estimated BEMF Alpha Register - __I uint32_t SMC_BEMF1B; // 0x220 MCM SMC Estimated BEMF Beta Register - __I uint32_t SMC_BEMF2A; // 0x224 MCM SMC BEMF Filtered Alpha Register - __I uint32_t SMC_BEMF2B; // 0x228 MCM SMC BEMF Filtered Beta Register - __IO uint32_t SMC_LPFSCALE; // 0x22C MCM SMC LPF Coefficient Scale Factor Register - uint32_t REV230; // 0x230 RESERVED - __IO uint32_t VM_UPD; // 0x234 MCM Virtual Motor Update Register - __IO uint32_t VM_INI; // 0x238 MCM Virtual Motor Initialization Register - __IO uint32_t VM_ALPHAINI; // 0x23C MCM Virtual Motor Initial Data Alpha Register - __IO uint32_t VM_BETAINI; // 0x240 MCM Virtual Motor Initial Data Beta Register - __IO uint32_t VM_KF; // 0x244 MCM Virtual Motor F Constant Register - __IO uint32_t VM_KG; // 0x248 MCM Virtual Motor G Constant Register - __IO uint32_t VM_VALPHA; // 0x24C MCM Virtual Motor Voltage Vector Alpha Register - __IO uint32_t VM_VBETA; // 0x250 MCM Virtual Motor Voltage Vector BETA Register - __IO uint32_t VM_BEMFA; // 0x254 MCM Virtual Motor BEMF Vector Alpha Register - __IO uint32_t VM_BEMFB; // 0x258 MCM Virtual Motor BEMF Vector BETA Register - __IO uint32_t VM_ZALPHA; // 0x25C MCM Virtual Motor Z Vector Alpha Register - __IO uint32_t VM_ZBETA; // 0x260 MCM Virtual Motor Z Vector BETA Register - __IO uint32_t VM_DISZ; // 0x264 MCM Virtual Motor Z Factor Input Selection Register - __I uint32_t VM_DONE; // 0x268 MCM Virtual Motor Process Status Register - __I uint32_t VM_IEALPHA; // 0x26C MCM Virtual Motor Estimated IS Result Alpha Register - __I uint32_t VM_IEBETA; // 0x270 MCM Virtual Motor Estimated IS Result BETA Register - __IO uint32_t VM_CON; // 0x274 MCM Virtual Motor Connect Register - - __IO uint32_t VM_KFSCALE; // 0x278 MCM Virtual Motor F Constant Scale Register - __IO uint32_t VM_KGSCALE; // 0x27C MCM Virtual Motor G Constant Scale Register - __IO uint32_t VM_CONVS; // 0x280 MCM Virtual Motor Voltage Connect Register - - uint32_t REV284; // 0x284 RESERVED - __IO uint32_t SVM_UPD; // 0x288 MCM SVM Update Register - __IO uint32_t SVM_CON; // 0x28C MCM SVM Source Input Select Register - __IO uint32_t SVM_DINA; // 0x290 MCM SVM Phase A Register - __IO uint32_t SVM_DINB; // 0x294 MCM SVM Phase B Register - __IO uint32_t SVM_DINC; // 0x298 MCM SVM Phase C Register -} MCM_TypeDef; - -/******************************************************************************/ -/* Ȧs줸wq */ -/******************************************************************************/ - -/* #pragma anon_unions */ - -/****************** Bit definition for WWDG_CR register ************************/ - - - - -#else -/* */ -#endif diff --git a/bsp/essemi/es32f0271/libraries/CMSIS/Device/EastSoft/ES32F0271/Include/ES32F0271/reg_mswd.h b/bsp/essemi/es32f0271/libraries/CMSIS/Device/EastSoft/ES32F0271/Include/ES32F0271/reg_mswd.h deleted file mode 100644 index 3a7d2f5dcf..0000000000 --- a/bsp/essemi/es32f0271/libraries/CMSIS/Device/EastSoft/ES32F0271/Include/ES32F0271/reg_mswd.h +++ /dev/null @@ -1,58 +0,0 @@ -/** - ************************************************************************************** - * @file reg_MSWD.h - * @brief WWDG Head File - * - * @version V1.00.01 - * @data 19/10/2018 - * @author Eastsoft AE Team - * @note - * - * Copyright (C) 2018 Shanghai Eastsoft Microelectronics Co., Ltd. ALL rights reserved. - * - ************************************************************************************** - */ - -#ifndef __MSWD_H__ -#define __MSWD_H__ - -typedef struct -{ - __IO uint32_t CFG; // 0x00 SW_CFG Serial Wire Configure Register - __IO uint32_t JTAG2SWD; // 0x04 SW_JTAG2SW Serial Wire JTAG2SWD Register - __IO uint32_t LINERESET; // 0x08 SW_LINERESET Serial Wire LINERESET Resister - __O uint32_t STS; // 0x0C SW_STS Serial Wire STATUS Register - __IO uint32_t DP_IDR_ABORT; // 0x10 SW_DP_IDR_ABORT Serial Wire DP R-IDR W-ABORT Register - __IO uint32_t DP_CSR_WCR; // 0x14 SW_DP_CSR_WCR Serial Wire DP R-CSR W-WCR Register - __IO uint32_t DP_RESEND_SELECT; // 0x18 SW_DP_RESEND_SELECT Serial Wire DP R-RESEND W-SELECT Register - __IO uint32_t DP_RDBUF_ROUTESEL; // 0x1C SW_DP_RDBUF_ROUTESEL Serial Wire DP R-RDBUF W-ROUTESEL Register - __IO uint32_t AP_CSW; // 0x20 SW_AP_CSW Serial Wire AP CSW Register - __IO uint32_t AP_TAR; // 0x24 SW_AP_TAR Serial Wire AP TAR Register - __IO uint32_t AP_DRW; // 0x28 SW_AP_DRW Serial Wire AP DRW Register - __IO uint32_t AP_BD0; // 0x2C SW_AP_BD0 Serial Wire AP BD0 Register - __IO uint32_t AP_BD1; // 0x30 SW_AP_BD1 Serial Wire AP BD1 Register - __IO uint32_t AP_BD2; // 0x34 SW_AP_BD2 Serial Wire AP BD2 Register - __IO uint32_t AP_BD3; // 0x38 SW_AP_BD3 Serial Wire AP BD3 Register - __IO uint32_t AP_CFG; // 0x3C SW_AP_CFG Serial Wire AP CFG Register - __IO uint32_t AP_BASE; // 0x40 SW_AP_BASE Serial Wire AP BASE Register - __IO uint32_t AP_IDR; // 0x44 SW_AP_IDR Serial Wire AP IDR Register - uint32_t RES0; // 0x48 - uint32_t RES1; // 0x4C - __IO uint32_t ISP_CMD; // 0x50 SW_ISP_CMD Serial Wire ISP Command Register - __IO uint32_t ISP_DAT; // 0x54 SW_ISP_DAT Serial Wire ISP Data Register -} MSWD_TypeDef; - -/******************************************************************************/ -/* Ȧs줸wq */ -/******************************************************************************/ - -/* #pragma anon_unions */ - -/****************** Bit definition for WWDG_CR register ************************/ - - - - -#else -/* */ -#endif diff --git a/bsp/essemi/es32f0271/libraries/CMSIS/Device/EastSoft/ES32F0271/Include/ES32F0271/reg_rcu.h b/bsp/essemi/es32f0271/libraries/CMSIS/Device/EastSoft/ES32F0271/Include/ES32F0271/reg_rcu.h deleted file mode 100644 index af6a59c419..0000000000 --- a/bsp/essemi/es32f0271/libraries/CMSIS/Device/EastSoft/ES32F0271/Include/ES32F0271/reg_rcu.h +++ /dev/null @@ -1,585 +0,0 @@ -/** - ************************************************************************************** - * @file REG_RCU.h - * @brief RCU Head File - * - * @version V0.01 - * @date 12/5/2018 - * @author Eastsoft MCU Software Team - * @note - * - * Copyright (C) 2018 Shanghai Eastsoft Microelectronics Co., Ltd. ALL rights reserved. - * - ************************************************************************************** - */ - -#ifndef __RCU_H__ -#define __RCU_H__ - - -/******************************************************************************/ -/* 设备特殊寄存器结构定义 */ -/******************************************************************************/ - -/* 允许匿名结构和匿名联合 */ -/* #pragma anon_unions */ - -/****************** Bit definition for RCU_CON register ************************/ - -#define RCU_CON_SWRDY_POS 24U -#define RCU_CON_SWRDY_MSK BIT(RCU_CON_SWRDY_POS) - -#define RCU_CON_CSSFLG_POS 23U -#define RCU_CON_CSSFLG_MSK BIT(RCU_CON_CSSFLG_POS) - -#define RCU_CON_PLL1RDY_POS 21U -#define RCU_CON_PLL1RDY_MSK BIT(RCU_CON_PLL1RDY_POS) - -#define RCU_CON_PLL0RDY_POS 20U -#define RCU_CON_PLL0RDY_MSK BIT(RCU_CON_PLL0RDY_POS) - -#define RCU_CON_LOSCRDY_POS 19U -#define RCU_CON_LOSCRDY_MSK BIT(RCU_CON_LOSCRDY_POS) - -#define RCU_CON_LRCRDY_POS 18U -#define RCU_CON_LRCRDY_MSK BIT(RCU_CON_LRCRDY_POS) - -#define RCU_CON_HOSCRDY_POS 17U -#define RCU_CON_HOSCRDY_MSK BIT(RCU_CON_HOSCRDY_POS) - -#define RCU_CON_HRCRDY_POS 16U -#define RCU_CON_HRCRDY_MSK BIT(RCU_CON_HRCRDY_POS) - -#define RCU_CON_CSSON_POS 7U -#define RCU_CON_CSSON_MSK BIT(RCU_CON_CSSON_POS) - -#define RCU_CON_PLL1ON_POS 5U -#define RCU_CON_PLL1ON_MSK BIT(RCU_CON_PLL1ON_POS) - -#define RCU_CON_PLL0ON_POS 4U -#define RCU_CON_PLL0ON_MSK BIT(RCU_CON_PLL0ON_POS) - -#define RCU_CON_LOSCON_POS 3U -#define RCU_CON_LOSCON_MSK BIT(RCU_CON_LOSCON_POS) - -#define RCU_CON_LRCON_POS 2U -#define RCU_CON_LRCON_MSK BIT(RCU_CON_LRCON_POS) - -#define RCU_CON_HOSCON_POS 1U -#define RCU_CON_HOSCON_MSK BIT(RCU_CON_HOSCON_POS) - -#define RCU_CON_HRCON_POS 0U -#define RCU_CON_HRCON_MSK BIT(RCU_CON_HRCON_POS) - -/****************** Bit definition for RCU_CFG register ************************/ - -#define RCU_CFG_CKCFG_POS 31U -#define RCU_CFG_CKCFG_MSK BIT(RCU_CFG_CKCFG_POS) - -#define RCU_CFG_MPRE_POSS 28U -#define RCU_CFG_MPRE_POSE 30U -#define RCU_CFG_MPRE_MSK BITS(RCU_CFG_MPRE_POSS,RCU_CFG_MPRE_POSE) - -#define RCU_CFG_MSW_POSS 24U -#define RCU_CFG_MSW_POSE 27U -#define RCU_CFG_MSW_MSK BITS(RCU_CFG_MSW_POSS,RCU_CFG_MSW_POSE) - -#define RCU_CFG_PLLMUL_POSS 17U -#define RCU_CFG_PLLMUL_POSE 21U -#define RCU_CFG_PLLMUL_MSK BITS(RCU_CFG_PLLMUL_POSS,RCU_CFG_PLLMUL_POSE) - -#define RCU_CFG_PLLSRC_POS 16U -#define RCU_CFG_PLLSRC_MSK BIT(RCU_CFG_PLLSRC_POS) - -#define RCU_CFG_HOSCDIV_POSS 12U -#define RCU_CFG_HOSCDIV_POSE 14U -#define RCU_CFG_HOSCDIV_MSK BITS(RCU_CFG_HOSCDIV_POSS,RCU_CFG_HOSCDIV_POSE) - -#define RCU_CFG_PPRE_POSS 8U -#define RCU_CFG_PPRE_POSE 10U -#define RCU_CFG_PPRE_MSK BITS(RCU_CFG_PPRE_POSS,RCU_CFG_PPRE_POSE) - -#define RCU_CFG_HPRE_POSS 4U -#define RCU_CFG_HPRE_POSE 7U -#define RCU_CFG_HPRE_MSK BITS(RCU_CFG_HPRE_POSS,RCU_CFG_HPRE_POSE) - -#define RCU_CFG_SW_POSS 0U -#define RCU_CFG_SW_POSE 2U -#define RCU_CFG_SW_MSK BITS(RCU_CFG_SW_POSS,RCU_CFG_SW_POSE) - -/****************** Bit definition for RCU_STCALIB register ************************/ - -#define RCU_STCALIB_SKEW_POS 30U -#define RCU_STCALIB_SKEW_MSK BIT(RCU_STCALIB_SKEW_POS) - -#define RCU_STCALIB_TENMS_POSS 0U -#define RCU_STCALIB_TENMS_POSE 23U -#define RCU_STCALIB_TENMS_MSK BITS(RCU_STCALIB_TENMS_POSS,RCU_STCALIB_TENMS_POSE) - -/****************** Bit definition for RCU_PSCK register ************************/ - -#define RCU_PSCK_I2S2CKSL_POSS 2U -#define RCU_PSCK_I2S2CKSL_POSE 3U -#define RCU_PSCK_I2S2CKSL_MSK BITS(RCU_PSCK_I2S2CKSL_POSS,RCU_PSCK_I2S2CKSL_POSE) - -#define RCU_PSCK_I2S1CKSL_POSS 0U -#define RCU_PSCK_I2S1CKSL_POSE 1U -#define RCU_PSCK_I2S1CKSL_MSK BITS(RCU_PSCK_I2S1CKSL_POSS,RCU_PSCK_I2S1CKSL_POSE) - -/****************** Bit definition for RCU_AHBRST register ************************/ - -#define RCU_AHBRST_GPDEN_POS 19U -#define RCU_AHBRST_GPDEN_MSK BIT(RCU_AHBRST_GPDEN_POS) - -#define RCU_AHBRST_GPCEN_POS 18U -#define RCU_AHBRST_GPCEN_MSK BIT(RCU_AHBRST_GPCEN_POS) - -#define RCU_AHBRST_GPBEN_POS 17U -#define RCU_AHBRST_GPBEN_MSK BIT(RCU_AHBRST_GPBEN_POS) - -#define RCU_AHBRST_GPAEN_POS 16U -#define RCU_AHBRST_GPAEN_MSK BIT(RCU_AHBRST_GPAEN_POS) - -#define RCU_AHBRST_HDIVEN_POS 15U -#define RCU_AHBRST_HDIVEN_MSK BIT(RCU_AHBRST_HDIVEN_POS) - -#define RCU_AHBRST_USBEN_POS 14U -#define RCU_AHBRST_USBEN_MSK BIT(RCU_AHBRST_USBEN_POS) - -#define RCU_AHBRST_AESEN_POS 13U -#define RCU_AHBRST_AESEN_MSK BIT(RCU_AHBRST_AESEN_POS) - -#define RCU_AHBRST_CRCEN_POS 12U -#define RCU_AHBRST_CRCEN_MSK BIT(RCU_AHBRST_CRCEN_POS) - -#define RCU_AHBRST_RTCEN_POS 6U -#define RCU_AHBRST_RTCEN_MSK BIT(RCU_AHBRST_RTCEN_POS) - -#define RCU_AHBRST_DMA1EN_POS 0U -#define RCU_AHBRST_DMA1EN_MSK BIT(RCU_AHBRST_DMA1EN_POS) - -/****************** Bit definition for RCU_APB1RST register ************************/ - -#define RCU_APB1RST_DACEN_POS 23U -#define RCU_APB1RST_DACEN_MSK BIT(RCU_APB1RST_DACEN_POS) - -#define RCU_APB1RST_I2C2EN_POS 22U -#define RCU_APB1RST_I2C2EN_MSK BIT(RCU_APB1RST_I2C2EN_POS) - -#define RCU_APB1RST_I2C1EN_POS 21U -#define RCU_APB1RST_I2C1EN_MSK BIT(RCU_APB1RST_I2C1EN_POS) - -#define RCU_APB1RST_SUART2EN_POS 20U -#define RCU_APB1RST_SUART2EN_MSK BIT(RCU_APB1RST_SUART2EN_POS) - -#define RCU_APB1RST_SUART1EN_POS 19U -#define RCU_APB1RST_SUART1EN_MSK BIT(RCU_APB1RST_SUART1EN_POS) - -#define RCU_APB1RST_UART3EN_POS 18U -#define RCU_APB1RST_UART3EN_MSK BIT(RCU_APB1RST_UART3EN_POS) - -#define RCU_APB1RST_UART2EN_POS 17U -#define RCU_APB1RST_UART2EN_MSK BIT(RCU_APB1RST_UART2EN_POS) - -#define RCU_APB1RST_SPI2EN_POS 14U -#define RCU_APB1RST_SPI2EN_MSK BIT(RCU_APB1RST_SPI2EN_POS) - -#define RCU_APB1RST_IWDTEN_POS 12U -#define RCU_APB1RST_IWDTEN_MSK BIT(RCU_APB1RST_IWDTEN_POS) - -#define RCU_APB1RST_WWDTEN_POS 11U -#define RCU_APB1RST_WWDTEN_MSK BIT(RCU_APB1RST_WWDTEN_POS) - -#define RCU_APB1RST_BS16T1EN_POS 4U -#define RCU_APB1RST_BS16T1EN_MSK BIT(RCU_APB1RST_BS16T1EN_POS) - -#define RCU_APB1RST_GP16C4T3EN_POS 3U -#define RCU_APB1RST_GP16C4T3EN_MSK BIT(RCU_APB1RST_GP16C4T3EN_POS) - -#define RCU_APB1RST_GP16C4T2EN_POS 2U -#define RCU_APB1RST_GP16C4T2EN_MSK BIT(RCU_APB1RST_GP16C4T2EN_POS) - -#define RCU_APB1RST_GP16C4T1EN_POS 1U -#define RCU_APB1RST_GP16C4T1EN_MSK BIT(RCU_APB1RST_GP16C4T1EN_POS) - -#define RCU_APB1RST_GP32C4T1EN_POS 0U -#define RCU_APB1RST_GP32C4T1EN_MSK BIT(RCU_APB1RST_GP32C4T1EN_POS) - -/****************** Bit definition for RCU_APB2RST register ************************/ - -#define RCU_APB2RST_CMPEN_POS 23U -#define RCU_APB2RST_CMPEN_MSK BIT(RCU_APB2RST_CMPEN_POS) - -#define RCU_APB2RST_GP16C2T4EN_POS 19U -#define RCU_APB2RST_GP16C2T4EN_MSK BIT(RCU_APB2RST_GP16C2T4EN_POS) - -#define RCU_APB2RST_GP16C2T3EN_POS 18U -#define RCU_APB2RST_GP16C2T3EN_MSK BIT(RCU_APB2RST_GP16C2T3EN_POS) - -#define RCU_APB2RST_GP16C2T2EN_POS 17U -#define RCU_APB2RST_GP16C2T2EN_MSK BIT(RCU_APB2RST_GP16C2T2EN_POS) - -#define RCU_APB2RST_GP16C2T1EN_POS 16U -#define RCU_APB2RST_GP16C2T1EN_MSK BIT(RCU_APB2RST_GP16C2T1EN_POS) - -#define RCU_APB2RST_UART1EN_POS 14U -#define RCU_APB2RST_UART1EN_MSK BIT(RCU_APB2RST_UART1EN_POS) - -#define RCU_APB2RST_SPI1EN_POS 12U -#define RCU_APB2RST_SPI1EN_MSK BIT(RCU_APB2RST_SPI1EN_POS) - -#define RCU_APB2RST_AD16C4T1EN_POS 11U -#define RCU_APB2RST_AD16C4T1EN_MSK BIT(RCU_APB2RST_AD16C4T1EN_POS) - -#define RCU_APB2RST_ADCEN_POS 9U -#define RCU_APB2RST_ADCEN_MSK BIT(RCU_APB2RST_ADCEN_POS) - -/****************** Bit definition for RCU_AHBEN register ************************/ - -#define RCU_AHBEN_GPDEN_POS 19U -#define RCU_AHBEN_GPDEN_MSK BIT(RCU_AHBEN_GPDEN_POS) - -#define RCU_AHBEN_GPCEN_POS 18U -#define RCU_AHBEN_GPCEN_MSK BIT(RCU_AHBEN_GPCEN_POS) - -#define RCU_AHBEN_GPBEN_POS 17U -#define RCU_AHBEN_GPBEN_MSK BIT(RCU_AHBEN_GPBEN_POS) - -#define RCU_AHBEN_GPAEN_POS 16U -#define RCU_AHBEN_GPAEN_MSK BIT(RCU_AHBEN_GPAEN_POS) - -#define RCU_AHBEN_HDIVEN_POS 15U -#define RCU_AHBEN_HDIVEN_MSK BIT(RCU_AHBEN_HDIVEN_POS) - -#define RCU_AHBEN_USBEN_POS 14U -#define RCU_AHBEN_USBEN_MSK BIT(RCU_AHBEN_USBEN_POS) - -#define RCU_AHBEN_AESEN_POS 13U -#define RCU_AHBEN_AESEN_MSK BIT(RCU_AHBEN_AESEN_POS) - -#define RCU_AHBEN_CRCEN_POS 12U -#define RCU_AHBEN_CRCEN_MSK BIT(RCU_AHBEN_CRCEN_POS) - -#define RCU_AHBEN_RTCEN_POS 6U -#define RCU_AHBEN_RTCEN_MSK BIT(RCU_AHBEN_RTCEN_POS) - -#define RCU_AHBEN_DMA1EN_POS 0U -#define RCU_AHBEN_DMA1EN_MSK BIT(RCU_AHBEN_DMA1EN_POS) - -/****************** Bit definition for RCU_APB1EN register ************************/ - -#define RCU_APB1EN_DACEN_POS 23U -#define RCU_APB1EN_DACEN_MSK BIT(RCU_APB1EN_DACEN_POS) - -#define RCU_APB1EN_I2C2EN_POS 22U -#define RCU_APB1EN_I2C2EN_MSK BIT(RCU_APB1EN_I2C2EN_POS) - -#define RCU_APB1EN_I2C1EN_POS 21U -#define RCU_APB1EN_I2C1EN_MSK BIT(RCU_APB1EN_I2C1EN_POS) - -#define RCU_APB1EN_SUART2EN_POS 20U -#define RCU_APB1EN_SUART2EN_MSK BIT(RCU_APB1EN_SUART2EN_POS) - -#define RCU_APB1EN_SUART1EN_POS 19U -#define RCU_APB1EN_SUART1EN_MSK BIT(RCU_APB1EN_SUART1EN_POS) - -#define RCU_APB1EN_UART3EN_POS 18U -#define RCU_APB1EN_UART3EN_MSK BIT(RCU_APB1EN_UART3EN_POS) - -#define RCU_APB1EN_UART2EN_POS 17U -#define RCU_APB1EN_UART2EN_MSK BIT(RCU_APB1EN_UART2EN_POS) - -#define RCU_APB1EN_SPI2EN_POS 14U -#define RCU_APB1EN_SPI2EN_MSK BIT(RCU_APB1EN_SPI2EN_POS) - -#define RCU_APB1EN_IWDTEN_POS 12U -#define RCU_APB1EN_IWDTEN_MSK BIT(RCU_APB1EN_IWDTEN_POS) - -#define RCU_APB1EN_WWDTEN_POS 11U -#define RCU_APB1EN_WWDTEN_MSK BIT(RCU_APB1EN_WWDTEN_POS) - -#define RCU_APB1EN_BS16T1EN_POS 4U -#define RCU_APB1EN_BS16T1EN_MSK BIT(RCU_APB1EN_BS16T1EN_POS) - -#define RCU_APB1EN_GP16C4T3EN_POS 3U -#define RCU_APB1EN_GP16C4T3EN_MSK BIT(RCU_APB1EN_GP16C4T3EN_POS) - -#define RCU_APB1EN_GP16C4T2EN_POS 2U -#define RCU_APB1EN_GP16C4T2EN_MSK BIT(RCU_APB1EN_GP16C4T2EN_POS) - -#define RCU_APB1EN_GP16C4T1EN_POS 1U -#define RCU_APB1EN_GP16C4T1EN_MSK BIT(RCU_APB1EN_GP16C4T1EN_POS) - -#define RCU_APB1EN_GP32C4T1EN_POS 0U -#define RCU_APB1EN_GP32C4T1EN_MSK BIT(RCU_APB1EN_GP32C4T1EN_POS) - -/****************** Bit definition for RCU_APB2EN register ************************/ - -#define RCU_APB2EN_CMPEN_POS 23U -#define RCU_APB2EN_CMPEN_MSK BIT(RCU_APB2EN_CMPEN_POS) - -#define RCU_APB2EN_GP16C2T4EN_POS 19U -#define RCU_APB2EN_GP16C2T4EN_MSK BIT(RCU_APB2EN_GP16C2T4EN_POS) - -#define RCU_APB2EN_GP16C2T3EN_POS 18U -#define RCU_APB2EN_GP16C2T3EN_MSK BIT(RCU_APB2EN_GP16C2T3EN_POS) - -#define RCU_APB2EN_GP16C2T2EN_POS 17U -#define RCU_APB2EN_GP16C2T2EN_MSK BIT(RCU_APB2EN_GP16C2T2EN_POS) - -#define RCU_APB2EN_GP16C2T1EN_POS 16U -#define RCU_APB2EN_GP16C2T1EN_MSK BIT(RCU_APB2EN_GP16C2T1EN_POS) - -#define RCU_APB2EN_UART1EN_POS 14U -#define RCU_APB2EN_UART1EN_MSK BIT(RCU_APB2EN_UART1EN_POS) - -#define RCU_APB2EN_SPI1EN_POS 12U -#define RCU_APB2EN_SPI1EN_MSK BIT(RCU_APB2EN_SPI1EN_POS) - -#define RCU_APB2EN_AD16C4T1EN_POS 11U -#define RCU_APB2EN_AD16C4T1EN_MSK BIT(RCU_APB2EN_AD16C4T1EN_POS) - -#define RCU_APB2EN_ADCEN_POS 9U -#define RCU_APB2EN_ADCEN_MSK BIT(RCU_APB2EN_ADCEN_POS) - -/****************** Bit definition for RCU_AHBSL register ************************/ - -#define RCU_AHBSL_GPDEN_POS 19U -#define RCU_AHBSL_GPDEN_MSK BIT(RCU_AHBSL_GPDEN_POS) - -#define RCU_AHBSL_GPCEN_POS 18U -#define RCU_AHBSL_GPCEN_MSK BIT(RCU_AHBSL_GPCEN_POS) - -#define RCU_AHBSL_GPBEN_POS 17U -#define RCU_AHBSL_GPBEN_MSK BIT(RCU_AHBSL_GPBEN_POS) - -#define RCU_AHBSL_GPAEN_POS 16U -#define RCU_AHBSL_GPAEN_MSK BIT(RCU_AHBSL_GPAEN_POS) - -#define RCU_AHBSL_HDIVEN_POS 15U -#define RCU_AHBSL_HDIVEN_MSK BIT(RCU_AHBSL_HDIVEN_POS) - -#define RCU_AHBSL_USBEN_POS 14U -#define RCU_AHBSL_USBEN_MSK BIT(RCU_AHBSL_USBEN_POS) - -#define RCU_AHBSL_AESEN_POS 13U -#define RCU_AHBSL_AESEN_MSK BIT(RCU_AHBSL_AESEN_POS) - -#define RCU_AHBSL_CRCEN_POS 12U -#define RCU_AHBSL_CRCEN_MSK BIT(RCU_AHBSL_CRCEN_POS) - -#define RCU_AHBSL_RTCEN_POS 6U -#define RCU_AHBSL_RTCEN_MSK BIT(RCU_AHBSL_RTCEN_POS) - -#define RCU_AHBSL_DMA1EN_POS 0U -#define RCU_AHBSL_DMA1EN_MSK BIT(RCU_AHBSL_DMA1EN_POS) - -/****************** Bit definition for RCU_APB1SL register ************************/ - -#define RCU_APB1SL_DACEN_POS 23U -#define RCU_APB1SL_DACEN_MSK BIT(RCU_APB1SL_DACEN_POS) - -#define RCU_APB1SL_I2C2EN_POS 22U -#define RCU_APB1SL_I2C2EN_MSK BIT(RCU_APB1SL_I2C2EN_POS) - -#define RCU_APB1SL_I2C1EN_POS 21U -#define RCU_APB1SL_I2C1EN_MSK BIT(RCU_APB1SL_I2C1EN_POS) - -#define RCU_APB1SL_SUART2EN_POS 20U -#define RCU_APB1SL_SUART2EN_MSK BIT(RCU_APB1SL_SUART2EN_POS) - -#define RCU_APB1SL_SUART1EN_POS 19U -#define RCU_APB1SL_SUART1EN_MSK BIT(RCU_APB1SL_SUART1EN_POS) - -#define RCU_APB1SL_UART3EN_POS 18U -#define RCU_APB1SL_UART3EN_MSK BIT(RCU_APB1SL_UART3EN_POS) - -#define RCU_APB1SL_UART2EN_POS 17U -#define RCU_APB1SL_UART2EN_MSK BIT(RCU_APB1SL_UART2EN_POS) - -#define RCU_APB1SL_SPI2EN_POS 14U -#define RCU_APB1SL_SPI2EN_MSK BIT(RCU_APB1SL_SPI2EN_POS) - -#define RCU_APB1SL_IWDTEN_POS 12U -#define RCU_APB1SL_IWDTEN_MSK BIT(RCU_APB1SL_IWDTEN_POS) - -#define RCU_APB1SL_WWDTEN_POS 11U -#define RCU_APB1SL_WWDTEN_MSK BIT(RCU_APB1SL_WWDTEN_POS) - -#define RCU_APB1SL_BS16T1EN_POS 4U -#define RCU_APB1SL_BS16T1EN_MSK BIT(RCU_APB1SL_BS16T1EN_POS) - -#define RCU_APB1SL_GP16C4T3EN_POS 3U -#define RCU_APB1SL_GP16C4T3EN_MSK BIT(RCU_APB1SL_GP16C4T3EN_POS) - -#define RCU_APB1SL_GP16C4T2EN_POS 2U -#define RCU_APB1SL_GP16C4T2EN_MSK BIT(RCU_APB1SL_GP16C4T2EN_POS) - -#define RCU_APB1SL_GP16C4T1EN_POS 1U -#define RCU_APB1SL_GP16C4T1EN_MSK BIT(RCU_APB1SL_GP16C4T1EN_POS) - -#define RCU_APB1SL_GP32C4T1EN_POS 0U -#define RCU_APB1SL_GP32C4T1EN_MSK BIT(RCU_APB1SL_GP32C4T1EN_POS) - -/****************** Bit definition for RCU_APB2SL register ************************/ - -#define RCU_APB2SL_CMPEN_POS 23U -#define RCU_APB2SL_CMPEN_MSK BIT(RCU_APB2SL_CMPEN_POS) - -#define RCU_APB2SL_GP16C2T4EN_POS 19U -#define RCU_APB2SL_GP16C2T4EN_MSK BIT(RCU_APB2SL_GP16C2T4EN_POS) - -#define RCU_APB2SL_GP16C2T3EN_POS 18U -#define RCU_APB2SL_GP16C2T3EN_MSK BIT(RCU_APB2SL_GP16C2T3EN_POS) - -#define RCU_APB2SL_GP16C2T2EN_POS 17U -#define RCU_APB2SL_GP16C2T2EN_MSK BIT(RCU_APB2SL_GP16C2T2EN_POS) - -#define RCU_APB2SL_GP16C2T1EN_POS 16U -#define RCU_APB2SL_GP16C2T1EN_MSK BIT(RCU_APB2SL_GP16C2T1EN_POS) - -#define RCU_APB2SL_UART1EN_POS 14U -#define RCU_APB2SL_UART1EN_MSK BIT(RCU_APB2SL_UART1EN_POS) - -#define RCU_APB2SL_SPI1EN_POS 12U -#define RCU_APB2SL_SPI1EN_MSK BIT(RCU_APB2SL_SPI1EN_POS) - -#define RCU_APB2SL_AD16C4T1EN_POS 11U -#define RCU_APB2SL_AD16C4T1EN_MSK BIT(RCU_APB2SL_AD16C4T1EN_POS) - -#define RCU_APB2SL_ADCEN_POS 9U -#define RCU_APB2SL_ADCEN_MSK BIT(RCU_APB2SL_ADCEN_POS) - -/****************** Bit definition for RCU_AHBDSL register ************************/ - -#define RCU_AHBDSL_GPDEN_POS 19U -#define RCU_AHBDSL_GPDEN_MSK BIT(RCU_AHBDSL_GPDEN_POS) - -#define RCU_AHBDSL_GPCEN_POS 18U -#define RCU_AHBDSL_GPCEN_MSK BIT(RCU_AHBDSL_GPCEN_POS) - -#define RCU_AHBDSL_GPBEN_POS 17U -#define RCU_AHBDSL_GPBEN_MSK BIT(RCU_AHBDSL_GPBEN_POS) - -#define RCU_AHBDSL_GPAEN_POS 16U -#define RCU_AHBDSL_GPAEN_MSK BIT(RCU_AHBDSL_GPAEN_POS) - -#define RCU_AHBDSL_HDIVEN_POS 15U -#define RCU_AHBDSL_HDIVEN_MSK BIT(RCU_AHBDSL_HDIVEN_POS) - -#define RCU_AHBDSL_USBEN_POS 14U -#define RCU_AHBDSL_USBEN_MSK BIT(RCU_AHBDSL_USBEN_POS) - -#define RCU_AHBDSL_AESEN_POS 13U -#define RCU_AHBDSL_AESEN_MSK BIT(RCU_AHBDSL_AESEN_POS) - -#define RCU_AHBDSL_CRCEN_POS 12U -#define RCU_AHBDSL_CRCEN_MSK BIT(RCU_AHBDSL_CRCEN_POS) - -#define RCU_AHBDSL_RTCEN_POS 6U -#define RCU_AHBDSL_RTCEN_MSK BIT(RCU_AHBDSL_RTCEN_POS) - -#define RCU_AHBDSL_DMA1EN_POS 0U -#define RCU_AHBDSL_DMA1EN_MSK BIT(RCU_AHBDSL_DMA1EN_POS) - -/****************** Bit definition for RCU_APB1DSL register ************************/ - -#define RCU_APB1DSL_DACEN_POS 23U -#define RCU_APB1DSL_DACEN_MSK BIT(RCU_APB1DSL_DACEN_POS) - -#define RCU_APB1DSL_I2C2EN_POS 22U -#define RCU_APB1DSL_I2C2EN_MSK BIT(RCU_APB1DSL_I2C2EN_POS) - -#define RCU_APB1DSL_I2C1EN_POS 21U -#define RCU_APB1DSL_I2C1EN_MSK BIT(RCU_APB1DSL_I2C1EN_POS) - -#define RCU_APB1DSL_SUART2EN_POS 20U -#define RCU_APB1DSL_SUART2EN_MSK BIT(RCU_APB1DSL_SUART2EN_POS) - -#define RCU_APB1DSL_SUART1EN_POS 19U -#define RCU_APB1DSL_SUART1EN_MSK BIT(RCU_APB1DSL_SUART1EN_POS) - -#define RCU_APB1DSL_UART3EN_POS 18U -#define RCU_APB1DSL_UART3EN_MSK BIT(RCU_APB1DSL_UART3EN_POS) - -#define RCU_APB1DSL_UART2EN_POS 17U -#define RCU_APB1DSL_UART2EN_MSK BIT(RCU_APB1DSL_UART2EN_POS) - -#define RCU_APB1DSL_SPI2EN_POS 14U -#define RCU_APB1DSL_SPI2EN_MSK BIT(RCU_APB1DSL_SPI2EN_POS) - -#define RCU_APB1DSL_IWDTEN_POS 12U -#define RCU_APB1DSL_IWDTEN_MSK BIT(RCU_APB1DSL_IWDTEN_POS) - -#define RCU_APB1DSL_WWDTEN_POS 11U -#define RCU_APB1DSL_WWDTEN_MSK BIT(RCU_APB1DSL_WWDTEN_POS) - -#define RCU_APB1DSL_BS16T1EN_POS 4U -#define RCU_APB1DSL_BS16T1EN_MSK BIT(RCU_APB1DSL_BS16T1EN_POS) - -#define RCU_APB1DSL_GP16C4T3EN_POS 3U -#define RCU_APB1DSL_GP16C4T3EN_MSK BIT(RCU_APB1DSL_GP16C4T3EN_POS) - -#define RCU_APB1DSL_GP16C4T2EN_POS 2U -#define RCU_APB1DSL_GP16C4T2EN_MSK BIT(RCU_APB1DSL_GP16C4T2EN_POS) - -#define RCU_APB1DSL_GP16C4T1EN_POS 1U -#define RCU_APB1DSL_GP16C4T1EN_MSK BIT(RCU_APB1DSL_GP16C4T1EN_POS) - -#define RCU_APB1DSL_GP32C4T1EN_POS 0U -#define RCU_APB1DSL_GP32C4T1EN_MSK BIT(RCU_APB1DSL_GP32C4T1EN_POS) - -/****************** Bit definition for RCU_APB2DSL register ************************/ - -#define RCU_APB2DSL_CMPEN_POS 23U -#define RCU_APB2DSL_CMPEN_MSK BIT(RCU_APB2DSL_CMPEN_POS) - -#define RCU_APB2DSL_GP16C2T4EN_POS 19U -#define RCU_APB2DSL_GP16C2T4EN_MSK BIT(RCU_APB2DSL_GP16C2T4EN_POS) - -#define RCU_APB2DSL_GP16C2T3EN_POS 18U -#define RCU_APB2DSL_GP16C2T3EN_MSK BIT(RCU_APB2DSL_GP16C2T3EN_POS) - -#define RCU_APB2DSL_GP16C2T2EN_POS 17U -#define RCU_APB2DSL_GP16C2T2EN_MSK BIT(RCU_APB2DSL_GP16C2T2EN_POS) - -#define RCU_APB2DSL_GP16C2T1EN_POS 16U -#define RCU_APB2DSL_GP16C2T1EN_MSK BIT(RCU_APB2DSL_GP16C2T1EN_POS) - -#define RCU_APB2DSL_UART1EN_POS 14U -#define RCU_APB2DSL_UART1EN_MSK BIT(RCU_APB2DSL_UART1EN_POS) - -#define RCU_APB2DSL_SPI1EN_POS 12U -#define RCU_APB2DSL_SPI1EN_MSK BIT(RCU_APB2DSL_SPI1EN_POS) - -#define RCU_APB2DSL_AD16C4T1EN_POS 11U -#define RCU_APB2DSL_AD16C4T1EN_MSK BIT(RCU_APB2DSL_AD16C4T1EN_POS) - -#define RCU_APB2DSL_ADCEN_POS 9U -#define RCU_APB2DSL_ADCEN_MSK BIT(RCU_APB2DSL_ADCEN_POS) - -typedef struct -{ - __IO uint32_t CON; - __IO uint32_t CFG; - __IO uint32_t STCALIB; - __IO uint32_t PSCK; - __IO uint32_t AHBRST; - __IO uint32_t APB1RST; - __IO uint32_t APB2RST; - __IO uint32_t AHBEN; - __IO uint32_t APB1EN; - __IO uint32_t APB2EN; - __IO uint32_t AHBSL; - __IO uint32_t APB1SL; - __IO uint32_t APB2SL; - __IO uint32_t AHBDSL; - __IO uint32_t APB1DSL; - __IO uint32_t APB2DSL; -} RCU_TypeDef; - - - - - -#endif diff --git a/bsp/essemi/es32f0271/libraries/CMSIS/Device/EastSoft/ES32F0271/Include/ES32F0271/reg_rtc.h b/bsp/essemi/es32f0271/libraries/CMSIS/Device/EastSoft/ES32F0271/Include/ES32F0271/reg_rtc.h deleted file mode 100644 index a22674f22b..0000000000 --- a/bsp/essemi/es32f0271/libraries/CMSIS/Device/EastSoft/ES32F0271/Include/ES32F0271/reg_rtc.h +++ /dev/null @@ -1,613 +0,0 @@ -/** - ************************************************************************************** - * @file REG_RTC.h - * @brief RTC Head File - * - * @version V0.01 - * @date 12/5/2018 - * @author Eastsoft MCU Software Team - * @note - * - * Copyright (C) 2018 Shanghai Eastsoft Microelectronics Co., Ltd. ALL rights reserved. - * - ************************************************************************************** - */ - -#ifndef __RTC_H__ -#define __RTC_H__ - - -/******************************************************************************/ -/* 设备特殊寄存器结构定义 */ -/******************************************************************************/ - -/* 允许匿名结构和匿名联合 */ -/* #pragma anon_unions */ - -/****************** Bit definition for RTC_CON register ************************/ - -#define RTC_CON_MODE_POS 30U -#define RTC_CON_MODE_MSK BIT(RTC_CON_MODE_POS) - -#define RTC_CON_CALVAL_POSS 24U -#define RTC_CON_CALVAL_POSE 29U -#define RTC_CON_CALVAL_MSK BITS(RTC_CON_CALVAL_POSS,RTC_CON_CALVAL_POSE) - -#define RTC_CON_SCALE_POSS 16U -#define RTC_CON_SCALE_POSE 23U -#define RTC_CON_SCALE_MSK BITS(RTC_CON_SCALE_POSS,RTC_CON_SCALE_POSE) - -#define RTC_CON_PSCALE_POSS 8U -#define RTC_CON_PSCALE_POSE 14U -#define RTC_CON_PSCALE_MSK BITS(RTC_CON_PSCALE_POSS,RTC_CON_PSCALE_POSE) - -#define RTC_CON_CYCLE_POS 5U -#define RTC_CON_CYCLE_MSK BIT(RTC_CON_CYCLE_POS) - -#define RTC_CON_CALIB_POS 4U -#define RTC_CON_CALIB_MSK BIT(RTC_CON_CALIB_POS) - -#define RTC_CON_CKSEL_POSS 2U -#define RTC_CON_CKSEL_POSE 3U -#define RTC_CON_CKSEL_MSK BITS(RTC_CON_CKSEL_POSS,RTC_CON_CKSEL_POSE) - -#define RTC_CON_RTCEN_POS 0U -#define RTC_CON_RTCEN_MSK BIT(RTC_CON_RTCEN_POS) - -/****************** Bit definition for RTC_WKUP register ************************/ - -#define RTC_WKUP_WKSCAL_POSS 26U -#define RTC_WKUP_WKSCAL_POSE 29U -#define RTC_WKUP_WKSCAL_MSK BITS(RTC_WKUP_WKSCAL_POSS,RTC_WKUP_WKSCAL_POSE) - -#define RTC_WKUP_WKSEL_POSS 24U -#define RTC_WKUP_WKSEL_POSE 25U -#define RTC_WKUP_WKSEL_MSK BITS(RTC_WKUP_WKSEL_POSS,RTC_WKUP_WKSEL_POSE) - -#define RTC_WKUP_WKCAL_POSS 0U -#define RTC_WKUP_WKCAL_POSE 23U -#define RTC_WKUP_WKCAL_MSK BITS(RTC_WKUP_WKCAL_POSS,RTC_WKUP_WKCAL_POSE) - -/****************** Bit definition for RTC_TIME register ************************/ - -#define RTC_TIME_WEEK_POSS 24U -#define RTC_TIME_WEEK_POSE 26U -#define RTC_TIME_WEEK_MSK BITS(RTC_TIME_WEEK_POSS,RTC_TIME_WEEK_POSE) - -#define RTC_TIME_HOUR_T_POSS 20U -#define RTC_TIME_HOUR_T_POSE 21U -#define RTC_TIME_HOUR_T_MSK BITS(RTC_TIME_HOUR_T_POSS,RTC_TIME_HOUR_T_POSE) - -#define RTC_TIME_HOUR_U_POSS 16U -#define RTC_TIME_HOUR_U_POSE 19U -#define RTC_TIME_HOUR_U_MSK BITS(RTC_TIME_HOUR_U_POSS,RTC_TIME_HOUR_U_POSE) - -#define RTC_TIME_MIN_T_POSS 12U -#define RTC_TIME_MIN_T_POSE 14U -#define RTC_TIME_MIN_T_MSK BITS(RTC_TIME_MIN_T_POSS,RTC_TIME_MIN_T_POSE) - -#define RTC_TIME_MIN_U_POSS 8U -#define RTC_TIME_MIN_U_POSE 11U -#define RTC_TIME_MIN_U_MSK BITS(RTC_TIME_MIN_U_POSS,RTC_TIME_MIN_U_POSE) - -#define RTC_TIME_SEC_T_POSS 4U -#define RTC_TIME_SEC_T_POSE 6U -#define RTC_TIME_SEC_T_MSK BITS(RTC_TIME_SEC_T_POSS,RTC_TIME_SEC_T_POSE) - -#define RTC_TIME_SEC_U_POSS 0U -#define RTC_TIME_SEC_U_POSE 3U -#define RTC_TIME_SEC_U_MSK BITS(RTC_TIME_SEC_U_POSS,RTC_TIME_SEC_U_POSE) - -/****************** Bit definition for RTC_CAL register ************************/ - -#define RTC_CAL_YEAR_T_POSS 20U -#define RTC_CAL_YEAR_T_POSE 23U -#define RTC_CAL_YEAR_T_MSK BITS(RTC_CAL_YEAR_T_POSS,RTC_CAL_YEAR_T_POSE) - -#define RTC_CAL_YEAR_U_POSS 16U -#define RTC_CAL_YEAR_U_POSE 19U -#define RTC_CAL_YEAR_U_MSK BITS(RTC_CAL_YEAR_U_POSS,RTC_CAL_YEAR_U_POSE) - -#define RTC_CAL_MON_T_POS 12U -#define RTC_CAL_MON_T_MSK BIT(RTC_CAL_MON_T_POS) - -#define RTC_CAL_MON_U_POSS 8U -#define RTC_CAL_MON_U_POSE 11U -#define RTC_CAL_MON_U_MSK BITS(RTC_CAL_MON_U_POSS,RTC_CAL_MON_U_POSE) - -#define RTC_CAL_DATE_T_POSS 4U -#define RTC_CAL_DATE_T_POSE 5U -#define RTC_CAL_DATE_T_MSK BITS(RTC_CAL_DATE_T_POSS,RTC_CAL_DATE_T_POSE) - -#define RTC_CAL_DATE_U_POSS 0U -#define RTC_CAL_DATE_U_POSE 3U -#define RTC_CAL_DATE_U_MSK BITS(RTC_CAL_DATE_U_POSS,RTC_CAL_DATE_U_POSE) - -/****************** Bit definition for RTC_ALTIME register ************************/ - -#define RTC_ALTIME_WEEK_POSS 24U -#define RTC_ALTIME_WEEK_POSE 26U -#define RTC_ALTIME_WEEK_MSK BITS(RTC_ALTIME_WEEK_POSS,RTC_ALTIME_WEEK_POSE) - -#define RTC_ALTIME_HOUR_T_POSS 20U -#define RTC_ALTIME_HOUR_T_POSE 21U -#define RTC_ALTIME_HOUR_T_MSK BITS(RTC_ALTIME_HOUR_T_POSS,RTC_ALTIME_HOUR_T_POSE) - -#define RTC_ALTIME_HOUR_U_POSS 16U -#define RTC_ALTIME_HOUR_U_POSE 19U -#define RTC_ALTIME_HOUR_U_MSK BITS(RTC_ALTIME_HOUR_U_POSS,RTC_ALTIME_HOUR_U_POSE) - -#define RTC_ALTIME_MIN_T_POSS 12U -#define RTC_ALTIME_MIN_T_POSE 14U -#define RTC_ALTIME_MIN_T_MSK BITS(RTC_ALTIME_MIN_T_POSS,RTC_ALTIME_MIN_T_POSE) - -#define RTC_ALTIME_MIN_U_POSS 8U -#define RTC_ALTIME_MIN_U_POSE 11U -#define RTC_ALTIME_MIN_U_MSK BITS(RTC_ALTIME_MIN_U_POSS,RTC_ALTIME_MIN_U_POSE) - -#define RTC_ALTIME_SEC_T_POSS 4U -#define RTC_ALTIME_SEC_T_POSE 6U -#define RTC_ALTIME_SEC_T_MSK BITS(RTC_ALTIME_SEC_T_POSS,RTC_ALTIME_SEC_T_POSE) - -#define RTC_ALTIME_SEC_U_POSS 0U -#define RTC_ALTIME_SEC_U_POSE 3U -#define RTC_ALTIME_SEC_U_MSK BITS(RTC_ALTIME_SEC_U_POSS,RTC_ALTIME_SEC_U_POSE) - -/****************** Bit definition for RTC_ALCAL register ************************/ - -#define RTC_ALCAL_YEAR_T_POSS 20U -#define RTC_ALCAL_YEAR_T_POSE 23U -#define RTC_ALCAL_YEAR_T_MSK BITS(RTC_ALCAL_YEAR_T_POSS,RTC_ALCAL_YEAR_T_POSE) - -#define RTC_ALCAL_YEAR_U_POSS 16U -#define RTC_ALCAL_YEAR_U_POSE 19U -#define RTC_ALCAL_YEAR_U_MSK BITS(RTC_ALCAL_YEAR_U_POSS,RTC_ALCAL_YEAR_U_POSE) - -#define RTC_ALCAL_MON_T_POS 12U -#define RTC_ALCAL_MON_T_MSK BIT(RTC_ALCAL_MON_T_POS) - -#define RTC_ALCAL_MON_U_POSS 8U -#define RTC_ALCAL_MON_U_POSE 11U -#define RTC_ALCAL_MON_U_MSK BITS(RTC_ALCAL_MON_U_POSS,RTC_ALCAL_MON_U_POSE) - -#define RTC_ALCAL_DATE_T_POSS 4U -#define RTC_ALCAL_DATE_T_POSE 5U -#define RTC_ALCAL_DATE_T_MSK BITS(RTC_ALCAL_DATE_T_POSS,RTC_ALCAL_DATE_T_POSE) - -#define RTC_ALCAL_DATE_U_POSS 0U -#define RTC_ALCAL_DATE_U_POSE 3U -#define RTC_ALCAL_DATE_U_MSK BITS(RTC_ALCAL_DATE_U_POSS,RTC_ALCAL_DATE_U_POSE) - -/****************** Bit definition for RTC_ALEN register ************************/ - -#define RTC_ALEN_YEAR_POS 6U -#define RTC_ALEN_YEAR_MSK BIT(RTC_ALEN_YEAR_POS) - -#define RTC_ALEN_MONTH_POS 5U -#define RTC_ALEN_MONTH_MSK BIT(RTC_ALEN_MONTH_POS) - -#define RTC_ALEN_DATE_POS 4U -#define RTC_ALEN_DATE_MSK BIT(RTC_ALEN_DATE_POS) - -#define RTC_ALEN_WEEK_POS 3U -#define RTC_ALEN_WEEK_MSK BIT(RTC_ALEN_WEEK_POS) - -#define RTC_ALEN_HOUR_POS 2U -#define RTC_ALEN_HOUR_MSK BIT(RTC_ALEN_HOUR_POS) - -#define RTC_ALEN_MIN_POS 1U -#define RTC_ALEN_MIN_MSK BIT(RTC_ALEN_MIN_POS) - -#define RTC_ALEN_SEC_POS 0U -#define RTC_ALEN_SEC_MSK BIT(RTC_ALEN_SEC_POS) - -/****************** Bit definition for RTC_TRIG register ************************/ - -#define RTC_TRIG_WKTM_POS 16U -#define RTC_TRIG_WKTM_MSK BIT(RTC_TRIG_WKTM_POS) - -#define RTC_TRIG_F1HZ_POS 15U -#define RTC_TRIG_F1HZ_MSK BIT(RTC_TRIG_F1HZ_POS) - -#define RTC_TRIG_RYEAR_POS 14U -#define RTC_TRIG_RYEAR_MSK BIT(RTC_TRIG_RYEAR_POS) - -#define RTC_TRIG_RMON_POS 13U -#define RTC_TRIG_RMON_MSK BIT(RTC_TRIG_RMON_POS) - -#define RTC_TRIG_RDATE_POS 12U -#define RTC_TRIG_RDATE_MSK BIT(RTC_TRIG_RDATE_POS) - -#define RTC_TRIG_RWEEK_POS 11U -#define RTC_TRIG_RWEEK_MSK BIT(RTC_TRIG_RWEEK_POS) - -#define RTC_TRIG_RHOUR_POS 10U -#define RTC_TRIG_RHOUR_MSK BIT(RTC_TRIG_RHOUR_POS) - -#define RTC_TRIG_RMIN_POS 9U -#define RTC_TRIG_RMIN_MSK BIT(RTC_TRIG_RMIN_POS) - -#define RTC_TRIG_RSEC_POS 8U -#define RTC_TRIG_RSEC_MSK BIT(RTC_TRIG_RSEC_POS) - -#define RTC_TRIG_AMALL_POS 7U -#define RTC_TRIG_AMALL_MSK BIT(RTC_TRIG_AMALL_POS) - -#define RTC_TRIG_AYEAR_POS 6U -#define RTC_TRIG_AYEAR_MSK BIT(RTC_TRIG_AYEAR_POS) - -#define RTC_TRIG_AMON_POS 5U -#define RTC_TRIG_AMON_MSK BIT(RTC_TRIG_AMON_POS) - -#define RTC_TRIG_ADTAE_POS 4U -#define RTC_TRIG_ADTAE_MSK BIT(RTC_TRIG_ADTAE_POS) - -#define RTC_TRIG_AWEEK_POS 3U -#define RTC_TRIG_AWEEK_MSK BIT(RTC_TRIG_AWEEK_POS) - -#define RTC_TRIG_AHOUR_POS 2U -#define RTC_TRIG_AHOUR_MSK BIT(RTC_TRIG_AHOUR_POS) - -#define RTC_TRIG_AMIN_POS 1U -#define RTC_TRIG_AMIN_MSK BIT(RTC_TRIG_AMIN_POS) - -#define RTC_TRIG_ASEC_POS 0U -#define RTC_TRIG_ASEC_MSK BIT(RTC_TRIG_ASEC_POS) - -/****************** Bit definition for RTC_IER register ************************/ - -#define RTC_IER_WKTM_POS 16U -#define RTC_IER_WKTM_MSK BIT(RTC_IER_WKTM_POS) - -#define RTC_IER_F1HZ_POS 15U -#define RTC_IER_F1HZ_MSK BIT(RTC_IER_F1HZ_POS) - -#define RTC_IER_RYEAR_POS 14U -#define RTC_IER_RYEAR_MSK BIT(RTC_IER_RYEAR_POS) - -#define RTC_IER_RMON_POS 13U -#define RTC_IER_RMON_MSK BIT(RTC_IER_RMON_POS) - -#define RTC_IER_RDATE_POS 12U -#define RTC_IER_RDATE_MSK BIT(RTC_IER_RDATE_POS) - -#define RTC_IER_RWEEK_POS 11U -#define RTC_IER_RWEEK_MSK BIT(RTC_IER_RWEEK_POS) - -#define RTC_IER_RHOUR_POS 10U -#define RTC_IER_RHOUR_MSK BIT(RTC_IER_RHOUR_POS) - -#define RTC_IER_RMIN_POS 9U -#define RTC_IER_RMIN_MSK BIT(RTC_IER_RMIN_POS) - -#define RTC_IER_RSEC_POS 8U -#define RTC_IER_RSEC_MSK BIT(RTC_IER_RSEC_POS) - -#define RTC_IER_AMALL_POS 7U -#define RTC_IER_AMALL_MSK BIT(RTC_IER_AMALL_POS) - -#define RTC_IER_AYEAR_POS 6U -#define RTC_IER_AYEAR_MSK BIT(RTC_IER_AYEAR_POS) - -#define RTC_IER_AMON_POS 5U -#define RTC_IER_AMON_MSK BIT(RTC_IER_AMON_POS) - -#define RTC_IER_ADTAE_POS 4U -#define RTC_IER_ADTAE_MSK BIT(RTC_IER_ADTAE_POS) - -#define RTC_IER_AWEEK_POS 3U -#define RTC_IER_AWEEK_MSK BIT(RTC_IER_AWEEK_POS) - -#define RTC_IER_AHOUR_POS 2U -#define RTC_IER_AHOUR_MSK BIT(RTC_IER_AHOUR_POS) - -#define RTC_IER_AMIN_POS 1U -#define RTC_IER_AMIN_MSK BIT(RTC_IER_AMIN_POS) - -#define RTC_IER_ASEC_POS 0U -#define RTC_IER_ASEC_MSK BIT(RTC_IER_ASEC_POS) - -/****************** Bit definition for RTC_IDR register ************************/ - -#define RTC_IDR_WKTM_POS 16U -#define RTC_IDR_WKTM_MSK BIT(RTC_IDR_WKTM_POS) - -#define RTC_IDR_F1HZ_POS 15U -#define RTC_IDR_F1HZ_MSK BIT(RTC_IDR_F1HZ_POS) - -#define RTC_IDR_RYEAR_POS 14U -#define RTC_IDR_RYEAR_MSK BIT(RTC_IDR_RYEAR_POS) - -#define RTC_IDR_RMON_POS 13U -#define RTC_IDR_RMON_MSK BIT(RTC_IDR_RMON_POS) - -#define RTC_IDR_RDATE_POS 12U -#define RTC_IDR_RDATE_MSK BIT(RTC_IDR_RDATE_POS) - -#define RTC_IDR_RWEEK_POS 11U -#define RTC_IDR_RWEEK_MSK BIT(RTC_IDR_RWEEK_POS) - -#define RTC_IDR_RHOUR_POS 10U -#define RTC_IDR_RHOUR_MSK BIT(RTC_IDR_RHOUR_POS) - -#define RTC_IDR_RMIN_POS 9U -#define RTC_IDR_RMIN_MSK BIT(RTC_IDR_RMIN_POS) - -#define RTC_IDR_RSEC_POS 8U -#define RTC_IDR_RSEC_MSK BIT(RTC_IDR_RSEC_POS) - -#define RTC_IDR_AMALL_POS 7U -#define RTC_IDR_AMALL_MSK BIT(RTC_IDR_AMALL_POS) - -#define RTC_IDR_AYEAR_POS 6U -#define RTC_IDR_AYEAR_MSK BIT(RTC_IDR_AYEAR_POS) - -#define RTC_IDR_AMON_POS 5U -#define RTC_IDR_AMON_MSK BIT(RTC_IDR_AMON_POS) - -#define RTC_IDR_ADTAE_POS 4U -#define RTC_IDR_ADTAE_MSK BIT(RTC_IDR_ADTAE_POS) - -#define RTC_IDR_AWEEK_POS 3U -#define RTC_IDR_AWEEK_MSK BIT(RTC_IDR_AWEEK_POS) - -#define RTC_IDR_AHOUR_POS 2U -#define RTC_IDR_AHOUR_MSK BIT(RTC_IDR_AHOUR_POS) - -#define RTC_IDR_AMIN_POS 1U -#define RTC_IDR_AMIN_MSK BIT(RTC_IDR_AMIN_POS) - -#define RTC_IDR_ASEC_POS 0U -#define RTC_IDR_ASEC_MSK BIT(RTC_IDR_ASEC_POS) - -/****************** Bit definition for RTC_IVS register ************************/ - -#define RTC_IVS_WKTM_POS 16U -#define RTC_IVS_WKTM_MSK BIT(RTC_IVS_WKTM_POS) - -#define RTC_IVS_F1HZ_POS 15U -#define RTC_IVS_F1HZ_MSK BIT(RTC_IVS_F1HZ_POS) - -#define RTC_IVS_RYEAR_POS 14U -#define RTC_IVS_RYEAR_MSK BIT(RTC_IVS_RYEAR_POS) - -#define RTC_IVS_RMON_POS 13U -#define RTC_IVS_RMON_MSK BIT(RTC_IVS_RMON_POS) - -#define RTC_IVS_RDATE_POS 12U -#define RTC_IVS_RDATE_MSK BIT(RTC_IVS_RDATE_POS) - -#define RTC_IVS_RWEEK_POS 11U -#define RTC_IVS_RWEEK_MSK BIT(RTC_IVS_RWEEK_POS) - -#define RTC_IVS_RHOUR_POS 10U -#define RTC_IVS_RHOUR_MSK BIT(RTC_IVS_RHOUR_POS) - -#define RTC_IVS_RMIN_POS 9U -#define RTC_IVS_RMIN_MSK BIT(RTC_IVS_RMIN_POS) - -#define RTC_IVS_RSEC_POS 8U -#define RTC_IVS_RSEC_MSK BIT(RTC_IVS_RSEC_POS) - -#define RTC_IVS_AMALL_POS 7U -#define RTC_IVS_AMALL_MSK BIT(RTC_IVS_AMALL_POS) - -#define RTC_IVS_AYEAR_POS 6U -#define RTC_IVS_AYEAR_MSK BIT(RTC_IVS_AYEAR_POS) - -#define RTC_IVS_AMON_POS 5U -#define RTC_IVS_AMON_MSK BIT(RTC_IVS_AMON_POS) - -#define RTC_IVS_ADTAE_POS 4U -#define RTC_IVS_ADTAE_MSK BIT(RTC_IVS_ADTAE_POS) - -#define RTC_IVS_AWEEK_POS 3U -#define RTC_IVS_AWEEK_MSK BIT(RTC_IVS_AWEEK_POS) - -#define RTC_IVS_AHOUR_POS 2U -#define RTC_IVS_AHOUR_MSK BIT(RTC_IVS_AHOUR_POS) - -#define RTC_IVS_AMIN_POS 1U -#define RTC_IVS_AMIN_MSK BIT(RTC_IVS_AMIN_POS) - -#define RTC_IVS_ASEC_POS 0U -#define RTC_IVS_ASEC_MSK BIT(RTC_IVS_ASEC_POS) - -/****************** Bit definition for RTC_RIF register ************************/ - -#define RTC_RIF_WKTM_POS 16U -#define RTC_RIF_WKTM_MSK BIT(RTC_RIF_WKTM_POS) - -#define RTC_RIF_F1HZ_POS 15U -#define RTC_RIF_F1HZ_MSK BIT(RTC_RIF_F1HZ_POS) - -#define RTC_RIF_RYEAR_POS 14U -#define RTC_RIF_RYEAR_MSK BIT(RTC_RIF_RYEAR_POS) - -#define RTC_RIF_RMON_POS 13U -#define RTC_RIF_RMON_MSK BIT(RTC_RIF_RMON_POS) - -#define RTC_RIF_RDATE_POS 12U -#define RTC_RIF_RDATE_MSK BIT(RTC_RIF_RDATE_POS) - -#define RTC_RIF_RWEEK_POS 11U -#define RTC_RIF_RWEEK_MSK BIT(RTC_RIF_RWEEK_POS) - -#define RTC_RIF_RHOUR_POS 10U -#define RTC_RIF_RHOUR_MSK BIT(RTC_RIF_RHOUR_POS) - -#define RTC_RIF_RMIN_POS 9U -#define RTC_RIF_RMIN_MSK BIT(RTC_RIF_RMIN_POS) - -#define RTC_RIF_RSEC_POS 8U -#define RTC_RIF_RSEC_MSK BIT(RTC_RIF_RSEC_POS) - -#define RTC_RIF_AMALL_POS 7U -#define RTC_RIF_AMALL_MSK BIT(RTC_RIF_AMALL_POS) - -#define RTC_RIF_AYEAR_POS 6U -#define RTC_RIF_AYEAR_MSK BIT(RTC_RIF_AYEAR_POS) - -#define RTC_RIF_AMON_POS 5U -#define RTC_RIF_AMON_MSK BIT(RTC_RIF_AMON_POS) - -#define RTC_RIF_ADTAE_POS 4U -#define RTC_RIF_ADTAE_MSK BIT(RTC_RIF_ADTAE_POS) - -#define RTC_RIF_AWEEK_POS 3U -#define RTC_RIF_AWEEK_MSK BIT(RTC_RIF_AWEEK_POS) - -#define RTC_RIF_AHOUR_POS 2U -#define RTC_RIF_AHOUR_MSK BIT(RTC_RIF_AHOUR_POS) - -#define RTC_RIF_AMIN_POS 1U -#define RTC_RIF_AMIN_MSK BIT(RTC_RIF_AMIN_POS) - -#define RTC_RIF_ASEC_POS 0U -#define RTC_RIF_ASEC_MSK BIT(RTC_RIF_ASEC_POS) - -/****************** Bit definition for RTC_IFM register ************************/ - -#define RTC_IFM_WKTM_POS 16U -#define RTC_IFM_WKTM_MSK BIT(RTC_IFM_WKTM_POS) - -#define RTC_IFM_F1HZ_POS 15U -#define RTC_IFM_F1HZ_MSK BIT(RTC_IFM_F1HZ_POS) - -#define RTC_IFM_RYEAR_POS 14U -#define RTC_IFM_RYEAR_MSK BIT(RTC_IFM_RYEAR_POS) - -#define RTC_IFM_RMON_POS 13U -#define RTC_IFM_RMON_MSK BIT(RTC_IFM_RMON_POS) - -#define RTC_IFM_RDATE_POS 12U -#define RTC_IFM_RDATE_MSK BIT(RTC_IFM_RDATE_POS) - -#define RTC_IFM_RWEEK_POS 11U -#define RTC_IFM_RWEEK_MSK BIT(RTC_IFM_RWEEK_POS) - -#define RTC_IFM_RHOUR_POS 10U -#define RTC_IFM_RHOUR_MSK BIT(RTC_IFM_RHOUR_POS) - -#define RTC_IFM_RMIN_POS 9U -#define RTC_IFM_RMIN_MSK BIT(RTC_IFM_RMIN_POS) - -#define RTC_IFM_RSEC_POS 8U -#define RTC_IFM_RSEC_MSK BIT(RTC_IFM_RSEC_POS) - -#define RTC_IFM_AMALL_POS 7U -#define RTC_IFM_AMALL_MSK BIT(RTC_IFM_AMALL_POS) - -#define RTC_IFM_AYEAR_POS 6U -#define RTC_IFM_AYEAR_MSK BIT(RTC_IFM_AYEAR_POS) - -#define RTC_IFM_AMON_POS 5U -#define RTC_IFM_AMON_MSK BIT(RTC_IFM_AMON_POS) - -#define RTC_IFM_ADTAE_POS 4U -#define RTC_IFM_ADTAE_MSK BIT(RTC_IFM_ADTAE_POS) - -#define RTC_IFM_AWEEK_POS 3U -#define RTC_IFM_AWEEK_MSK BIT(RTC_IFM_AWEEK_POS) - -#define RTC_IFM_AHOUR_POS 2U -#define RTC_IFM_AHOUR_MSK BIT(RTC_IFM_AHOUR_POS) - -#define RTC_IFM_AMIN_POS 1U -#define RTC_IFM_AMIN_MSK BIT(RTC_IFM_AMIN_POS) - -#define RTC_IFM_ASEC_POS 0U -#define RTC_IFM_ASEC_MSK BIT(RTC_IFM_ASEC_POS) - -/****************** Bit definition for RTC_ICR register ************************/ - -#define RTC_ICR_WKTM_POS 16U -#define RTC_ICR_WKTM_MSK BIT(RTC_ICR_WKTM_POS) - -#define RTC_ICR_F1HZ_POS 15U -#define RTC_ICR_F1HZ_MSK BIT(RTC_ICR_F1HZ_POS) - -#define RTC_ICR_RYEAR_POS 14U -#define RTC_ICR_RYEAR_MSK BIT(RTC_ICR_RYEAR_POS) - -#define RTC_ICR_RMON_POS 13U -#define RTC_ICR_RMON_MSK BIT(RTC_ICR_RMON_POS) - -#define RTC_ICR_RDATE_POS 12U -#define RTC_ICR_RDATE_MSK BIT(RTC_ICR_RDATE_POS) - -#define RTC_ICR_RWEEK_POS 11U -#define RTC_ICR_RWEEK_MSK BIT(RTC_ICR_RWEEK_POS) - -#define RTC_ICR_RHOUR_POS 10U -#define RTC_ICR_RHOUR_MSK BIT(RTC_ICR_RHOUR_POS) - -#define RTC_ICR_RMIN_POS 9U -#define RTC_ICR_RMIN_MSK BIT(RTC_ICR_RMIN_POS) - -#define RTC_ICR_RSEC_POS 8U -#define RTC_ICR_RSEC_MSK BIT(RTC_ICR_RSEC_POS) - -#define RTC_ICR_AMALL_POS 7U -#define RTC_ICR_AMALL_MSK BIT(RTC_ICR_AMALL_POS) - -#define RTC_ICR_AYEAR_POS 6U -#define RTC_ICR_AYEAR_MSK BIT(RTC_ICR_AYEAR_POS) - -#define RTC_ICR_AMON_POS 5U -#define RTC_ICR_AMON_MSK BIT(RTC_ICR_AMON_POS) - -#define RTC_ICR_ADTAE_POS 4U -#define RTC_ICR_ADTAE_MSK BIT(RTC_ICR_ADTAE_POS) - -#define RTC_ICR_AWEEK_POS 3U -#define RTC_ICR_AWEEK_MSK BIT(RTC_ICR_AWEEK_POS) - -#define RTC_ICR_AHOUR_POS 2U -#define RTC_ICR_AHOUR_MSK BIT(RTC_ICR_AHOUR_POS) - -#define RTC_ICR_AMIN_POS 1U -#define RTC_ICR_AMIN_MSK BIT(RTC_ICR_AMIN_POS) - -#define RTC_ICR_ASEC_POS 0U -#define RTC_ICR_ASEC_MSK BIT(RTC_ICR_ASEC_POS) - -/****************** Bit definition for RTC_STAT register ************************/ - -#define RTC_STAT_SYNDONE_POS 1U -#define RTC_STAT_SYNDONE_MSK BIT(RTC_STAT_SYNDONE_POS) - -#define RTC_STAT_EMPTY_POS 0U -#define RTC_STAT_EMPTY_MSK BIT(RTC_STAT_EMPTY_POS) - -/****************** Bit definition for RTC_BKEN register ************************/ - -#define RTC_BKEN_BKEN_POS 0U -#define RTC_BKEN_BKEN_MSK BIT(RTC_BKEN_BKEN_POS) - -typedef struct -{ - __IO uint32_t CON; - __IO uint32_t WKUP; - __IO uint32_t TIME; - __IO uint32_t CAL; - __IO uint32_t ALTIME; - __IO uint32_t ALCAL; - __IO uint32_t ALEN; - __IO uint32_t TRIG; - __O uint32_t IER; - __O uint32_t IDR; - __I uint32_t IVS; - __I uint32_t RIF; - __I uint32_t IFM; - __O uint32_t ICR; - uint32_t RESERVED0[2] ; - __I uint32_t STAT; - __IO uint32_t BKEN; -} RTC_TypeDef; - - - - - -#endif diff --git a/bsp/essemi/es32f0271/libraries/CMSIS/Device/EastSoft/ES32F0271/Include/ES32F0271/reg_spi.h b/bsp/essemi/es32f0271/libraries/CMSIS/Device/EastSoft/ES32F0271/Include/ES32F0271/reg_spi.h deleted file mode 100644 index 0d7fbf6ccc..0000000000 --- a/bsp/essemi/es32f0271/libraries/CMSIS/Device/EastSoft/ES32F0271/Include/ES32F0271/reg_spi.h +++ /dev/null @@ -1,444 +0,0 @@ -/** - ************************************************************************************** - * @file REG_SPI.h - * @brief SPI Head File - * - * @version V0.01 - * @data 12/3/2018 - * @author Eastsoft MCU Software Team - * @note - * - * Copyright (C) 2018 Shanghai Eastsoft Microelectronics Co., Ltd. ALL rights reserved. - * - ************************************************************************************** - */ - -#ifndef __SPI_H__ -#define __SPI_H__ - - -/******************************************************************************/ -/* 设备特殊寄存器结构定义 */ -/******************************************************************************/ - -/* 允许匿名结构和匿名联合 */ -/* #pragma anon_unions */ - -/****************** Bit definition for SPI_CON1 register ************************/ - -#define SPI_CON1_BIDEN_POS 15U -#define SPI_CON1_BIDEN_MSK BIT(SPI_CON1_BIDEN_POS) - -#define SPI_CON1_BIDOEN_POS 14U -#define SPI_CON1_BIDOEN_MSK BIT(SPI_CON1_BIDOEN_POS) - -#define SPI_CON1_CRCEN_POS 13U -#define SPI_CON1_CRCEN_MSK BIT(SPI_CON1_CRCEN_POS) - -#define SPI_CON1_NXTCRC_POS 12U -#define SPI_CON1_NXTCRC_MSK BIT(SPI_CON1_NXTCRC_POS) - -#define SPI_CON1_FLEN_POS 11U -#define SPI_CON1_FLEN_MSK BIT(SPI_CON1_FLEN_POS) - -#define SPI_CON1_RXO_POS 10U -#define SPI_CON1_RXO_MSK BIT(SPI_CON1_RXO_POS) - -#define SPI_CON1_SSEN_POS 9U -#define SPI_CON1_SSEN_MSK BIT(SPI_CON1_SSEN_POS) - -#define SPI_CON1_SSOUT_POS 8U -#define SPI_CON1_SSOUT_MSK BIT(SPI_CON1_SSOUT_POS) - -#define SPI_CON1_LSBFST_POS 7U -#define SPI_CON1_LSBFST_MSK BIT(SPI_CON1_LSBFST_POS) - -#define SPI_CON1_SPIEN_POS 6U -#define SPI_CON1_SPIEN_MSK BIT(SPI_CON1_SPIEN_POS) - -#define SPI_CON1_BAUD_POSS 3U -#define SPI_CON1_BAUD_POSE 5U -#define SPI_CON1_BAUD_MSK BITS(SPI_CON1_BAUD_POSS,SPI_CON1_BAUD_POSE) - -#define SPI_CON1_MSTREN_POS 2U -#define SPI_CON1_MSTREN_MSK BIT(SPI_CON1_MSTREN_POS) - -#define SPI_CON1_CPOL_POS 1U -#define SPI_CON1_CPOL_MSK BIT(SPI_CON1_CPOL_POS) - -#define SPI_CON1_CPHA_POS 0U -#define SPI_CON1_CPHA_MSK BIT(SPI_CON1_CPHA_POS) - -/****************** Bit definition for SPI_CON2 register ************************/ - -#define SPI_CON2_RXFTH_POSS 14U -#define SPI_CON2_RXFTH_POSE 15U -#define SPI_CON2_RXFTH_MSK BITS(SPI_CON2_RXFTH_POSS,SPI_CON2_RXFTH_POSE) - -#define SPI_CON2_TXFTH_POSS 12U -#define SPI_CON2_TXFTH_POSE 13U -#define SPI_CON2_TXFTH_MSK BITS(SPI_CON2_TXFTH_POSS,SPI_CON2_TXFTH_POSE) - -#define SPI_CON2_FRF_POS 4U -#define SPI_CON2_FRF_MSK BIT(SPI_CON2_FRF_POS) - -#define SPI_CON2_NSSP_POS 3U -#define SPI_CON2_NSSP_MSK BIT(SPI_CON2_NSSP_POS) - -#define SPI_CON2_NSSOE_POS 2U -#define SPI_CON2_NSSOE_MSK BIT(SPI_CON2_NSSOE_POS) - -#define SPI_CON2_TXDMA_POS 1U -#define SPI_CON2_TXDMA_MSK BIT(SPI_CON2_TXDMA_POS) - -#define SPI_CON2_RXDMA_POS 0U -#define SPI_CON2_RXDMA_MSK BIT(SPI_CON2_RXDMA_POS) - -/****************** Bit definition for SPI_STAT register ************************/ - -#define SPI_STAT_RXFLV_POSS 24U -#define SPI_STAT_RXFLV_POSE 28U -#define SPI_STAT_RXFLV_MSK BITS(SPI_STAT_RXFLV_POSS,SPI_STAT_RXFLV_POSE) - -#define SPI_STAT_TXFLV_POSS 16U -#define SPI_STAT_TXFLV_POSE 20U -#define SPI_STAT_TXFLV_MSK BITS(SPI_STAT_TXFLV_POSS,SPI_STAT_TXFLV_POSE) - -#define SPI_STAT_BUSY_POS 15U -#define SPI_STAT_BUSY_MSK BIT(SPI_STAT_BUSY_POS) - -#define SPI_STAT_CHSIDE_POS 14U -#define SPI_STAT_CHSIDE_MSK BIT(SPI_STAT_CHSIDE_POS) - -#define SPI_STAT_RXTH_POS 12U -#define SPI_STAT_RXTH_MSK BIT(SPI_STAT_RXTH_POS) - -#define SPI_STAT_RXUD_POS 11U -#define SPI_STAT_RXUD_MSK BIT(SPI_STAT_RXUD_POS) - -#define SPI_STAT_RXOV_POS 10U -#define SPI_STAT_RXOV_MSK BIT(SPI_STAT_RXOV_POS) - -#define SPI_STAT_RXF_POS 9U -#define SPI_STAT_RXF_MSK BIT(SPI_STAT_RXF_POS) - -#define SPI_STAT_RXE_POS 8U -#define SPI_STAT_RXE_MSK BIT(SPI_STAT_RXE_POS) - -#define SPI_STAT_TXTH_POS 4U -#define SPI_STAT_TXTH_MSK BIT(SPI_STAT_TXTH_POS) - -#define SPI_STAT_TXUD_POS 3U -#define SPI_STAT_TXUD_MSK BIT(SPI_STAT_TXUD_POS) - -#define SPI_STAT_TXOV_POS 2U -#define SPI_STAT_TXOV_MSK BIT(SPI_STAT_TXOV_POS) - -#define SPI_STAT_TXF_POS 1U -#define SPI_STAT_TXF_MSK BIT(SPI_STAT_TXF_POS) - -#define SPI_STAT_TXE_POS 0U -#define SPI_STAT_TXE_MSK BIT(SPI_STAT_TXE_POS) - -/****************** Bit definition for SPI_DATA register ************************/ - -#define SPI_DATA_DATA_POSS 0U -#define SPI_DATA_DATA_POSE 15U -#define SPI_DATA_DATA_MSK BITS(SPI_DATA_DATA_POSS,SPI_DATA_DATA_POSE) - -/****************** Bit definition for SPI_CRCPOLY register ************************/ - -#define SPI_CRCPOLY_CRCPOLY_POSS 0U -#define SPI_CRCPOLY_CRCPOLY_POSE 15U -#define SPI_CRCPOLY_CRCPOLY_MSK BITS(SPI_CRCPOLY_CRCPOLY_POSS,SPI_CRCPOLY_CRCPOLY_POSE) - -/****************** Bit definition for SPI_RXCRC register ************************/ - -#define SPI_RXCRC_RXCRC_POSS 0U -#define SPI_RXCRC_RXCRC_POSE 15U -#define SPI_RXCRC_RXCRC_MSK BITS(SPI_RXCRC_RXCRC_POSS,SPI_RXCRC_RXCRC_POSE) - -/****************** Bit definition for SPI_TXCRC register ************************/ - -#define SPI_TXCRC_TXCRC_POSS 0U -#define SPI_TXCRC_TXCRC_POSE 15U -#define SPI_TXCRC_TXCRC_MSK BITS(SPI_TXCRC_TXCRC_POSS,SPI_TXCRC_TXCRC_POSE) - -/****************** Bit definition for SPI_I2SCFG register ************************/ - -#define SPI_I2SCFG_I2SMOD_POS 11U -#define SPI_I2SCFG_I2SMOD_MSK BIT(SPI_I2SCFG_I2SMOD_POS) - -#define SPI_I2SCFG_I2SE_POS 10U -#define SPI_I2SCFG_I2SE_MSK BIT(SPI_I2SCFG_I2SE_POS) - -#define SPI_I2SCFG_I2SCFG_POSS 8U -#define SPI_I2SCFG_I2SCFG_POSE 9U -#define SPI_I2SCFG_I2SCFG_MSK BITS(SPI_I2SCFG_I2SCFG_POSS,SPI_I2SCFG_I2SCFG_POSE) - -#define SPI_I2SCFG_PCMSYNC_POS 7U -#define SPI_I2SCFG_PCMSYNC_MSK BIT(SPI_I2SCFG_PCMSYNC_POS) - -#define SPI_I2SCFG_I2SSTD_POSS 4U -#define SPI_I2SCFG_I2SSTD_POSE 5U -#define SPI_I2SCFG_I2SSTD_MSK BITS(SPI_I2SCFG_I2SSTD_POSS,SPI_I2SCFG_I2SSTD_POSE) - -#define SPI_I2SCFG_CKPOL_POS 3U -#define SPI_I2SCFG_CKPOL_MSK BIT(SPI_I2SCFG_CKPOL_POS) - -#define SPI_I2SCFG_DATLEN_POSS 1U -#define SPI_I2SCFG_DATLEN_POSE 2U -#define SPI_I2SCFG_DATLEN_MSK BITS(SPI_I2SCFG_DATLEN_POSS,SPI_I2SCFG_DATLEN_POSE) - -#define SPI_I2SCFG_CHLEN_POS 0U -#define SPI_I2SCFG_CHLEN_MSK BIT(SPI_I2SCFG_CHLEN_POS) - -/****************** Bit definition for SPI_I2SPR register ************************/ - -#define SPI_I2SPR_EXTCKEN_POS 10U -#define SPI_I2SPR_EXTCKEN_MSK BIT(SPI_I2SPR_EXTCKEN_POS) - -#define SPI_I2SPR_MCKOE_POS 9U -#define SPI_I2SPR_MCKOE_MSK BIT(SPI_I2SPR_MCKOE_POS) - -#define SPI_I2SPR_ODD_POS 8U -#define SPI_I2SPR_ODD_MSK BIT(SPI_I2SPR_ODD_POS) - -#define SPI_I2SPR_I2SDIV_POSS 0U -#define SPI_I2SPR_I2SDIV_POSE 7U -#define SPI_I2SPR_I2SDIV_MSK BITS(SPI_I2SPR_I2SDIV_POSS,SPI_I2SPR_I2SDIV_POSE) - -/****************** Bit definition for SPI_IER register ************************/ - -#define SPI_IER_FREIE_POS 18U -#define SPI_IER_FREIE_MSK BIT(SPI_IER_FREIE_POS) - -#define SPI_IER_MODFIE_POS 17U -#define SPI_IER_MODFIE_MSK BIT(SPI_IER_MODFIE_POS) - -#define SPI_IER_CRCERRIE_POS 16U -#define SPI_IER_CRCERRIE_MSK BIT(SPI_IER_CRCERRIE_POS) - -#define SPI_IER_RXTHIE_POS 12U -#define SPI_IER_RXTHIE_MSK BIT(SPI_IER_RXTHIE_POS) - -#define SPI_IER_RXUDIE_POS 11U -#define SPI_IER_RXUDIE_MSK BIT(SPI_IER_RXUDIE_POS) - -#define SPI_IER_RXOVIE_POS 10U -#define SPI_IER_RXOVIE_MSK BIT(SPI_IER_RXOVIE_POS) - -#define SPI_IER_RXFIE_POS 9U -#define SPI_IER_RXFIE_MSK BIT(SPI_IER_RXFIE_POS) - -#define SPI_IER_TXTHIE_POS 4U -#define SPI_IER_TXTHIE_MSK BIT(SPI_IER_TXTHIE_POS) - -#define SPI_IER_TXUDIE_POS 3U -#define SPI_IER_TXUDIE_MSK BIT(SPI_IER_TXUDIE_POS) - -#define SPI_IER_TXOVIE_POS 2U -#define SPI_IER_TXOVIE_MSK BIT(SPI_IER_TXOVIE_POS) - -#define SPI_IER_TXEIE_POS 0U -#define SPI_IER_TXEIE_MSK BIT(SPI_IER_TXEIE_POS) - -/****************** Bit definition for SPI_IDR register ************************/ - -#define SPI_IDR_FREID_POS 18U -#define SPI_IDR_FREID_MSK BIT(SPI_IDR_FREID_POS) - -#define SPI_IDR_MODFID_POS 17U -#define SPI_IDR_MODFID_MSK BIT(SPI_IDR_MODFID_POS) - -#define SPI_IDR_CRCERRID_POS 16U -#define SPI_IDR_CRCERRID_MSK BIT(SPI_IDR_CRCERRID_POS) - -#define SPI_IDR_RXTHID_POS 12U -#define SPI_IDR_RXTHID_MSK BIT(SPI_IDR_RXTHID_POS) - -#define SPI_IDR_RXUDID_POS 11U -#define SPI_IDR_RXUDID_MSK BIT(SPI_IDR_RXUDID_POS) - -#define SPI_IDR_RXOVID_POS 10U -#define SPI_IDR_RXOVID_MSK BIT(SPI_IDR_RXOVID_POS) - -#define SPI_IDR_RXFID_POS 9U -#define SPI_IDR_RXFID_MSK BIT(SPI_IDR_RXFID_POS) - -#define SPI_IDR_TXTHID_POS 4U -#define SPI_IDR_TXTHID_MSK BIT(SPI_IDR_TXTHID_POS) - -#define SPI_IDR_TXUDID_POS 3U -#define SPI_IDR_TXUDID_MSK BIT(SPI_IDR_TXUDID_POS) - -#define SPI_IDR_TXOVID_POS 2U -#define SPI_IDR_TXOVID_MSK BIT(SPI_IDR_TXOVID_POS) - -#define SPI_IDR_TXEID_POS 0U -#define SPI_IDR_TXEID_MSK BIT(SPI_IDR_TXEID_POS) - -/****************** Bit definition for SPI_IVS register ************************/ - -#define SPI_IVS_FREIV_POS 18U -#define SPI_IVS_FREIV_MSK BIT(SPI_IVS_FREIV_POS) - -#define SPI_IVS_MODFIV_POS 17U -#define SPI_IVS_MODFIV_MSK BIT(SPI_IVS_MODFIV_POS) - -#define SPI_IVS_CRCERRIV_POS 16U -#define SPI_IVS_CRCERRIV_MSK BIT(SPI_IVS_CRCERRIV_POS) - -#define SPI_IVS_RXTHIV_POS 12U -#define SPI_IVS_RXTHIV_MSK BIT(SPI_IVS_RXTHIV_POS) - -#define SPI_IVS_RXUDIV_POS 11U -#define SPI_IVS_RXUDIV_MSK BIT(SPI_IVS_RXUDIV_POS) - -#define SPI_IVS_RXOVIV_POS 10U -#define SPI_IVS_RXOVIV_MSK BIT(SPI_IVS_RXOVIV_POS) - -#define SPI_IVS_RXFIV_POS 9U -#define SPI_IVS_RXFIV_MSK BIT(SPI_IVS_RXFIV_POS) - -#define SPI_IVS_TXTHIV_POS 4U -#define SPI_IVS_TXTHIV_MSK BIT(SPI_IVS_TXTHIV_POS) - -#define SPI_IVS_TXUDIV_POS 3U -#define SPI_IVS_TXUDIV_MSK BIT(SPI_IVS_TXUDIV_POS) - -#define SPI_IVS_TXOVIV_POS 2U -#define SPI_IVS_TXOVIV_MSK BIT(SPI_IVS_TXOVIV_POS) - -#define SPI_IVS_TXEIV_POS 0U -#define SPI_IVS_TXEIV_MSK BIT(SPI_IVS_TXEIV_POS) - -/****************** Bit definition for SPI_RIF register ************************/ - -#define SPI_RIF_FRERI_POS 18U -#define SPI_RIF_FRERI_MSK BIT(SPI_RIF_FRERI_POS) - -#define SPI_RIF_MODFRI_POS 17U -#define SPI_RIF_MODFRI_MSK BIT(SPI_RIF_MODFRI_POS) - -#define SPI_RIF_CRCERRRI_POS 16U -#define SPI_RIF_CRCERRRI_MSK BIT(SPI_RIF_CRCERRRI_POS) - -#define SPI_RIF_RXTHRI_POS 12U -#define SPI_RIF_RXTHRI_MSK BIT(SPI_RIF_RXTHRI_POS) - -#define SPI_RIF_RXUDRI_POS 11U -#define SPI_RIF_RXUDRI_MSK BIT(SPI_RIF_RXUDRI_POS) - -#define SPI_RIF_RXOVRI_POS 10U -#define SPI_RIF_RXOVRI_MSK BIT(SPI_RIF_RXOVRI_POS) - -#define SPI_RIF_RXFRI_POS 9U -#define SPI_RIF_RXFRI_MSK BIT(SPI_RIF_RXFRI_POS) - -#define SPI_RIF_TXTHRI_POS 4U -#define SPI_RIF_TXTHRI_MSK BIT(SPI_RIF_TXTHRI_POS) - -#define SPI_RIF_TXUDRI_POS 3U -#define SPI_RIF_TXUDRI_MSK BIT(SPI_RIF_TXUDRI_POS) - -#define SPI_RIF_TXOVRI_POS 2U -#define SPI_RIF_TXOVRI_MSK BIT(SPI_RIF_TXOVRI_POS) - -#define SPI_RIF_TXERI_POS 0U -#define SPI_RIF_TXERI_MSK BIT(SPI_RIF_TXERI_POS) - -/****************** Bit definition for SPI_IFM register ************************/ - -#define SPI_IFM_FREFM_POS 18U -#define SPI_IFM_FREFM_MSK BIT(SPI_IFM_FREFM_POS) - -#define SPI_IFM_MODFFM_POS 17U -#define SPI_IFM_MODFFM_MSK BIT(SPI_IFM_MODFFM_POS) - -#define SPI_IFM_CRCERRFM_POS 16U -#define SPI_IFM_CRCERRFM_MSK BIT(SPI_IFM_CRCERRFM_POS) - -#define SPI_IFM_RXTHFM_POS 12U -#define SPI_IFM_RXTHFM_MSK BIT(SPI_IFM_RXTHFM_POS) - -#define SPI_IFM_RXUDFM_POS 11U -#define SPI_IFM_RXUDFM_MSK BIT(SPI_IFM_RXUDFM_POS) - -#define SPI_IFM_RXOVFM_POS 10U -#define SPI_IFM_RXOVFM_MSK BIT(SPI_IFM_RXOVFM_POS) - -#define SPI_IFM_RXFFM_POS 9U -#define SPI_IFM_RXFFM_MSK BIT(SPI_IFM_RXFFM_POS) - -#define SPI_IFM_TXTHFM_POS 4U -#define SPI_IFM_TXTHFM_MSK BIT(SPI_IFM_TXTHFM_POS) - -#define SPI_IFM_TXUDFM_POS 3U -#define SPI_IFM_TXUDFM_MSK BIT(SPI_IFM_TXUDFM_POS) - -#define SPI_IFM_TXOVFM_POS 2U -#define SPI_IFM_TXOVFM_MSK BIT(SPI_IFM_TXOVFM_POS) - -#define SPI_IFM_TXEFM_POS 0U -#define SPI_IFM_TXEFM_MSK BIT(SPI_IFM_TXEFM_POS) - -/****************** Bit definition for SPI_ICR register ************************/ - -#define SPI_ICR_FREIC_POS 18U -#define SPI_ICR_FREIC_MSK BIT(SPI_ICR_FREIC_POS) - -#define SPI_ICR_MODFIC_POS 17U -#define SPI_ICR_MODFIC_MSK BIT(SPI_ICR_MODFIC_POS) - -#define SPI_ICR_CRCERRIC_POS 16U -#define SPI_ICR_CRCERRIC_MSK BIT(SPI_ICR_CRCERRIC_POS) - -#define SPI_ICR_RXTHIC_POS 12U -#define SPI_ICR_RXTHIC_MSK BIT(SPI_ICR_RXTHIC_POS) - -#define SPI_ICR_RXUDIC_POS 11U -#define SPI_ICR_RXUDIC_MSK BIT(SPI_ICR_RXUDIC_POS) - -#define SPI_ICR_RXOVIC_POS 10U -#define SPI_ICR_RXOVIC_MSK BIT(SPI_ICR_RXOVIC_POS) - -#define SPI_ICR_RXFIC_POS 9U -#define SPI_ICR_RXFIC_MSK BIT(SPI_ICR_RXFIC_POS) - -#define SPI_ICR_TXTHIC_POS 4U -#define SPI_ICR_TXTHIC_MSK BIT(SPI_ICR_TXTHIC_POS) - -#define SPI_ICR_TXUDIC_POS 3U -#define SPI_ICR_TXUDIC_MSK BIT(SPI_ICR_TXUDIC_POS) - -#define SPI_ICR_TXOVIC_POS 2U -#define SPI_ICR_TXOVIC_MSK BIT(SPI_ICR_TXOVIC_POS) - -#define SPI_ICR_TXEIC_POS 0U -#define SPI_ICR_TXEIC_MSK BIT(SPI_ICR_TXEIC_POS) - -typedef struct -{ - __IO uint32_t CON1; - __IO uint32_t CON2; - __I uint32_t STAT; - __IO uint32_t DATA; - __IO uint32_t CRCPOLY; - __I uint32_t RXCRC; - __I uint32_t TXCRC; - __IO uint32_t I2SCFG; - __IO uint32_t I2SPR; - __O uint32_t IER; - __O uint32_t IDR; - __I uint32_t IVS; - __I uint32_t RIF; - __I uint32_t IFM; - __O uint32_t ICR; -} SPI_TypeDef; - - - - - -#endif diff --git a/bsp/essemi/es32f0271/libraries/CMSIS/Device/EastSoft/ES32F0271/Include/ES32F0271/reg_syscfg.h b/bsp/essemi/es32f0271/libraries/CMSIS/Device/EastSoft/ES32F0271/Include/ES32F0271/reg_syscfg.h deleted file mode 100644 index 675d9484c9..0000000000 --- a/bsp/essemi/es32f0271/libraries/CMSIS/Device/EastSoft/ES32F0271/Include/ES32F0271/reg_syscfg.h +++ /dev/null @@ -1,215 +0,0 @@ -/** - ************************************************************************************** - * @file REG_SYSCFG.h - * @brief SYSCFG Head File - * - * @version V0.01 - * @date 12/5/2018 - * @author Eastsoft MCU Software Team - * @note - * - * Copyright (C) 2018 Shanghai Eastsoft Microelectronics Co., Ltd. ALL rights reserved. - * - ************************************************************************************** - */ - -#ifndef __SYSCFG_H__ -#define __SYSCFG_H__ - - -/******************************************************************************/ -/* 设备特殊寄存器结构定义 */ -/******************************************************************************/ - -/* 允许匿名结构和匿名联合 */ -/* #pragma anon_unions */ - -/****************** Bit definition for SYSCFG_REMAP register ************************/ - -#define SYSCFG_REMAP_REALMOD_POSS 10U -#define SYSCFG_REMAP_REALMOD_POSE 11U -#define SYSCFG_REMAP_REALMOD_MSK BITS(SYSCFG_REMAP_REALMOD_POSS,SYSCFG_REMAP_REALMOD_POSE) - -#define SYSCFG_REMAP_EFBASE_POSS 4U -#define SYSCFG_REMAP_EFBASE_POSE 7U -#define SYSCFG_REMAP_EFBASE_MSK BITS(SYSCFG_REMAP_EFBASE_POSS,SYSCFG_REMAP_EFBASE_POSE) - -#define SYSCFG_REMAP_MEMMOD_POSS 2U -#define SYSCFG_REMAP_MEMMOD_POSE 3U -#define SYSCFG_REMAP_MEMMOD_MSK BITS(SYSCFG_REMAP_MEMMOD_POSS,SYSCFG_REMAP_MEMMOD_POSE) - -#define SYSCFG_REMAP_REMAP_POS 0U -#define SYSCFG_REMAP_REMAP_MSK BIT(SYSCFG_REMAP_REMAP_POS) - -/****************** Bit definition for SYSCFG_TRIM register ************************/ - -#define SYSCFG_TRIM_CNT_POSS 20U -#define SYSCFG_TRIM_CNT_POSE 31U -#define SYSCFG_TRIM_CNT_MSK BITS(SYSCFG_TRIM_CNT_POSS,SYSCFG_TRIM_CNT_POSE) - -#define SYSCFG_TRIM_FAIL_POS 18U -#define SYSCFG_TRIM_FAIL_MSK BIT(SYSCFG_TRIM_FAIL_POS) - -#define SYSCFG_TRIM_NOEQU_POS 17U -#define SYSCFG_TRIM_NOEQU_MSK BIT(SYSCFG_TRIM_NOEQU_POS) - -#define SYSCFG_TRIM_BUSY_POS 16U -#define SYSCFG_TRIM_BUSY_MSK BIT(SYSCFG_TRIM_BUSY_POS) - -#define SYSCFG_TRIM_HRCTRIM_POSS 8U -#define SYSCFG_TRIM_HRCTRIM_POSE 15U -#define SYSCFG_TRIM_HRCTRIM_MSK BITS(SYSCFG_TRIM_HRCTRIM_POSS,SYSCFG_TRIM_HRCTRIM_POSE) - -#define SYSCFG_TRIM_TSRC_POS 1U -#define SYSCFG_TRIM_TSRC_MSK BIT(SYSCFG_TRIM_TSRC_POS) - -#define SYSCFG_TRIM_TRIM_POS 0U -#define SYSCFG_TRIM_TRIM_MSK BIT(SYSCFG_TRIM_TRIM_POS) - -/****************** Bit definition for SYSCFG_IRSEL register ************************/ - -#define SYSCFG_IRSEL_PLR_POS 8U -#define SYSCFG_IRSEL_PLR_MSK BIT(SYSCFG_IRSEL_PLR_POS) - -#define SYSCFG_IRSEL_SEL2_POSS 4U -#define SYSCFG_IRSEL_SEL2_POSE 7U -#define SYSCFG_IRSEL_SEL2_MSK BITS(SYSCFG_IRSEL_SEL2_POSS,SYSCFG_IRSEL_SEL2_POSE) - -#define SYSCFG_IRSEL_SEL1_POSS 0U -#define SYSCFG_IRSEL_SEL1_POSE 3U -#define SYSCFG_IRSEL_SEL1_MSK BITS(SYSCFG_IRSEL_SEL1_POSS,SYSCFG_IRSEL_SEL1_POSE) - -/****************** Bit definition for SYSCFG_CFG register ************************/ - -#define SYSCFG_CFG_DBGH_EN_POSS 16U -#define SYSCFG_CFG_DBGH_EN_POSE 31U -#define SYSCFG_CFG_DBGH_EN_MSK BITS(SYSCFG_CFG_DBGH_EN_POSS,SYSCFG_CFG_DBGH_EN_POSE) - -#define SYSCFG_CFG_PVD_LCK_POS 14U -#define SYSCFG_CFG_PVD_LCK_MSK BIT(SYSCFG_CFG_PVD_LCK_POS) - -#define SYSCFG_CFG_CSS_LCK_POS 13U -#define SYSCFG_CFG_CSS_LCK_MSK BIT(SYSCFG_CFG_CSS_LCK_POS) - -#define SYSCFG_CFG_CPU_LCK_POS 12U -#define SYSCFG_CFG_CPU_LCK_MSK BIT(SYSCFG_CFG_CPU_LCK_POS) - -#define SYSCFG_CFG_VTST_POSS 8U -#define SYSCFG_CFG_VTST_POSE 9U -#define SYSCFG_CFG_VTST_MSK BITS(SYSCFG_CFG_VTST_POSS,SYSCFG_CFG_VTST_POSE) - -#define SYSCFG_CFG_NRSTREQ_POS 7U -#define SYSCFG_CFG_NRSTREQ_MSK BIT(SYSCFG_CFG_NRSTREQ_POS) - -#define SYSCFG_CFG_CURRGEN_POS 5U -#define SYSCFG_CFG_CURRGEN_MSK BIT(SYSCFG_CFG_CURRGEN_POS) - -#define SYSCFG_CFG_TEMPEN_POS 4U -#define SYSCFG_CFG_TEMPEN_MSK BIT(SYSCFG_CFG_TEMPEN_POS) - -#define SYSCFG_CFG_VREFEN_POS 3U -#define SYSCFG_CFG_VREFEN_MSK BIT(SYSCFG_CFG_VREFEN_POS) - -#define SYSCFG_CFG_VRLS_POSS 0U -#define SYSCFG_CFG_VRLS_POSE 2U -#define SYSCFG_CFG_VRLS_MSK BITS(SYSCFG_CFG_VRLS_POSS,SYSCFG_CFG_VRLS_POSE) - -/****************** Bit definition for SYSCFG_PWCON register ************************/ - -#define SYSCFG_PWCON_IOLOCK_POS 23U -#define SYSCFG_PWCON_IOLOCK_MSK BIT(SYSCFG_PWCON_IOLOCK_POS) - -#define SYSCFG_PWCON_BGTRIM_POSS 17U -#define SYSCFG_PWCON_BGTRIM_POSE 20U -#define SYSCFG_PWCON_BGTRIM_MSK BITS(SYSCFG_PWCON_BGTRIM_POSS,SYSCFG_PWCON_BGTRIM_POSE) - -#define SYSCFG_PWCON_HRCLOCK_POS 16U -#define SYSCFG_PWCON_HRCLOCK_MSK BIT(SYSCFG_PWCON_HRCLOCK_POS) - -#define SYSCFG_PWCON_HRCTRIM_POSS 8U -#define SYSCFG_PWCON_HRCTRIM_POSE 15U -#define SYSCFG_PWCON_HRCTRIM_MSK BITS(SYSCFG_PWCON_HRCTRIM_POSS,SYSCFG_PWCON_HRCTRIM_POSE) - -#define SYSCFG_PWCON_LOSCDRV_POSS 5U -#define SYSCFG_PWCON_LOSCDRV_POSE 7U -#define SYSCFG_PWCON_LOSCDRV_MSK BITS(SYSCFG_PWCON_LOSCDRV_POSS,SYSCFG_PWCON_LOSCDRV_POSE) - -#define SYSCFG_PWCON_PVDEN_POS 4U -#define SYSCFG_PWCON_PVDEN_MSK BIT(SYSCFG_PWCON_PVDEN_POS) - -#define SYSCFG_PWCON_PVLS_POSS 0U -#define SYSCFG_PWCON_PVLS_POSE 3U -#define SYSCFG_PWCON_PVLS_MSK BITS(SYSCFG_PWCON_PVLS_POSS,SYSCFG_PWCON_PVLS_POSE) - -/****************** Bit definition for SYSCFG_WKCON register ************************/ - -#define SYSCFG_WKCON_WKCLR_POS 31U -#define SYSCFG_WKCON_WKCLR_MSK BIT(SYSCFG_WKCON_WKCLR_POS) - -#define SYSCFG_WKCON_LPLS_POSS 28U -#define SYSCFG_WKCON_LPLS_POSE 30U -#define SYSCFG_WKCON_LPLS_MSK BITS(SYSCFG_WKCON_LPLS_POSS,SYSCFG_WKCON_LPLS_POSE) - -#define SYSCFG_WKCON_WKEG_POSS 16U -#define SYSCFG_WKCON_WKEG_POSE 27U -#define SYSCFG_WKCON_WKEG_MSK BITS(SYSCFG_WKCON_WKEG_POSS,SYSCFG_WKCON_WKEG_POSE) - -#define SYSCFG_WKCON_WKEN_POSS 0U -#define SYSCFG_WKCON_WKEN_POSE 11U -#define SYSCFG_WKCON_WKEN_MSK BITS(SYSCFG_WKCON_WKEN_POSS,SYSCFG_WKCON_WKEN_POSE) - -/****************** Bit definition for SYSCFG_WKSTAT register ************************/ - -#define SYSCFG_WKSTAT_FLAG_POS 16U -#define SYSCFG_WKSTAT_FLAG_MSK BIT(SYSCFG_WKSTAT_FLAG_POS) - -#define SYSCFG_WKSTAT_FG_POSS 0U -#define SYSCFG_WKSTAT_FG_POSE 11U -#define SYSCFG_WKSTAT_FG_MSK BITS(SYSCFG_WKSTAT_FG_POSS,SYSCFG_WKSTAT_FG_POSE) - -/****************** Bit definition for SYSCFG_BKREG0 register ************************/ - -#define SYSCFG_BKREG0_BKREG0_POSS 0U -#define SYSCFG_BKREG0_BKREG0_POSE 31U -#define SYSCFG_BKREG0_BKREG0_MSK BITS(SYSCFG_BKREG0_BKREG0_POSS,SYSCFG_BKREG0_BKREG0_POSE) - -/****************** Bit definition for SYSCFG_BKREG1 register ************************/ - -#define SYSCFG_BKREG1_BKREG1_POSS 0U -#define SYSCFG_BKREG1_BKREG1_POSE 31U -#define SYSCFG_BKREG1_BKREG1_MSK BITS(SYSCFG_BKREG1_BKREG1_POSS,SYSCFG_BKREG1_BKREG1_POSE) - -/****************** Bit definition for SYSCFG_BKREG2 register ************************/ - -#define SYSCFG_BKREG2_BKREG2_POSS 0U -#define SYSCFG_BKREG2_BKREG2_POSE 31U -#define SYSCFG_BKREG2_BKREG2_MSK BITS(SYSCFG_BKREG2_BKREG2_POSS,SYSCFG_BKREG2_BKREG2_POSE) - -/****************** Bit definition for SYSCFG_BKREG3 register ************************/ - -#define SYSCFG_BKREG3_BKREG3_POSS 0U -#define SYSCFG_BKREG3_BKREG3_POSE 29U -#define SYSCFG_BKREG3_BKREG3_MSK BITS(SYSCFG_BKREG3_BKREG3_POSS,SYSCFG_BKREG3_BKREG3_POSE) - -typedef struct -{ - __O uint32_t REMAP; - __O uint32_t TRIM; - __IO uint32_t IRSEL; - uint32_t RESERVED0[12] ; - __IO uint32_t CFG; - __IO uint32_t PWCON; - uint32_t RESERVED1 ; - __IO uint32_t WKCON; - __I uint32_t WKSTAT; - __IO uint32_t BKREG0; - __IO uint32_t BKREG1; - __IO uint32_t BKREG2; - __IO uint32_t BKREG3; -} SYSCFG_TypeDef; - - - - - -#endif diff --git a/bsp/essemi/es32f0271/libraries/CMSIS/Device/EastSoft/ES32F0271/Include/ES32F0271/reg_tick.h b/bsp/essemi/es32f0271/libraries/CMSIS/Device/EastSoft/ES32F0271/Include/ES32F0271/reg_tick.h deleted file mode 100644 index 13122aef46..0000000000 --- a/bsp/essemi/es32f0271/libraries/CMSIS/Device/EastSoft/ES32F0271/Include/ES32F0271/reg_tick.h +++ /dev/null @@ -1,113 +0,0 @@ -/** - ************************************************************************************** - * @file reg_TICK.h - * @brief TICK Head File - * - * @version V1.00.01 - * @date 19/10/2018 - * @author Eastsoft AE Team - * @note - * - * Copyright (C) 2018 Shanghai Eastsoft Microelectronics Co., Ltd. ALL rights reserved. - * - ************************************************************************************** - */ - -#ifndef __TICK_H__ -#define __TICK_H__ - -/******************************************************************************/ -/* Ȧs줸wq */ -/******************************************************************************/ - -/* #pragma anon_unions */ - -/****************** Bit definition for TICK_CSR register ************************/ - -#define TICK_CSR_ENABLE_POS 0U -#define TICK_CSR_ENABLE_MSK BIT(TICK_CSR_ENABLE_POS) - -#define TICK_CSR_TICKINT_POS 1U -#define TICK_CSR_TICKINT_MSK BIT(TICK_CSR_TICKINT_POS) - -#define TICK_CSR_CLKSOURCE_POS 2U -#define TICK_CSR_CLKSOURCE_MSK BIT(TICK_CSR_CLKSOURCE_POS) - -#define TICK_CSR_COUNTFLAG_POS 16U -#define TICK_CSR_COUNTFLAG_MSK BIT(TICK_CSR_COUNTFLAG_POS) - -/****************** Bit definition for TICK_RVR register ************************/ - -#define TICK_RVR_RELOAD_POSS 0U -#define TICK_RVR_RELOAD_POSE 23U -#define TICK_RVR_RELOAD_MSK BITS(TICK_RVR_RELOAD_POSS,TICK_RVR_RELOAD_POSE) - -/****************** Bit definition for TICK_CVR register ************************/ - -#define TICK_CVR_CURRENT_POSS 0U -#define TICK_CVR_CURRENT_POSE 23U -#define TICK_CVR_CURRENT_MSK BITS(TICK_CVR_CURRENT_POSS,TICK_CVR_CURRENT_POSE) - - -/****************** Bit definition for TICK_CALIB register ************************/ - -#define TICK_CALIB_TENMS_POSS 0U -#define TICK_CALIB_TENMS_POSE 23U -#define TICK_CALIB_TENMS_MSK BITS(TICK_CALIB_TENMS_POSS,TICK_CALIB_TENMS_POSE) - -#define TICK_CALIB_SKEW_POS 30U -#define TICK_CALIB_SKEW_MSK BIT(TICK_CALIB_SKEW_POS) - -#define TICK_CALIB_NOREF_POS 31U -#define TICK_CALIB_NOREF_MSK BIT(TICK_CALIB_NOREF_POS) - - -/* TICK Register */ -#define pTICK TICK - -/* TICK CSR Register(TICK_CSR) */ -#define CSR_COUNTFLAG(x) (x<<16) /* Indicates whether the counter has counted to 0 since the last read of this register - 0 timer has not counted to 0 - 1 timer has counted to 0 */ -#define CSR_CLKSOURCE(x) (x<<2) /* Indicates the SysTick clock source: - 0 SysTick uses the optional external reference clock - 1 SysTick uses the processor clock */ -#define CSR_TICKINT(x) (x<<1) /* Indicates whether counting to 0 causes the status of the SysTick exception to change to pending: - 0 count to 0 does not affect the SysTick exception status - 1 count to 0 changes the SysTick exception status to pending */ -#define CSR_ENABLE(x) (x<<0) /* /Indicates the enabled status of the SysTick counter: - 0 counter is disabled - 1 counter is operating */ - - -/* TICK RVR Register(TICK_RVR) */ -#define RVR_RELOAD(x) (x<<0) /* The value to load into the SYST_CVR register when the counter reaches 0 */ - - -/* TICK CVR Register(TICK_CVR) */ -#define CVR_CURRENT(x) (x<<0) /* Current counter value - This is the value of the counter at the time it is sampled */ - - -/* TICK CALIB Register(TICK_CALIB) */ -#define CALIB_NOREF(x) (x<<31) /* Indicates whether the IMPLEMENTATION DEFINED reference clock is provided: - 0 the reference clock is implemented - 1 the reference clock is not implemented - When this bit is 1, the CLKSOURCE bit of the SYST_CSR register is forced to 1 and cannot be cleared to 0 */ -#define CALIB_SKEW(x) (x<<30) /* Indicates whether the 10ms calibration value is exact: - 0 10ms calibration value is exact - 1 10ms calibration value is inexact, because of the clock frequency */ -#define CALIB_TENMS(x) (x<<0) /* Optionally, holds a reload value to be used for 10ms (100Hz) timing, subject to system clock skew errors. - If this field is zero, the calibration value is not known */ -typedef struct -{ - __IO uint32_t CSR; /* 0x0, Control and Status */ - __IO uint32_t RVR; /* 0x4, Reload Value */ - __IO uint32_t CVR; /* 0x8, Current Value */ - __I uint32_t CALIB; /* 0xC, Calibration */ -} TICK_TypeDef; - - -#else -/* */ -#endif diff --git a/bsp/essemi/es32f0271/libraries/CMSIS/Device/EastSoft/ES32F0271/Include/ES32F0271/reg_uart.h b/bsp/essemi/es32f0271/libraries/CMSIS/Device/EastSoft/ES32F0271/Include/ES32F0271/reg_uart.h deleted file mode 100644 index 1cd5670f8e..0000000000 --- a/bsp/essemi/es32f0271/libraries/CMSIS/Device/EastSoft/ES32F0271/Include/ES32F0271/reg_uart.h +++ /dev/null @@ -1,606 +0,0 @@ -/** - ************************************************************************************** - * @file REG_UART.h - * @brief UART Head File - * - * @version V0.01 - * @data 12/3/2018 - * @author Eastsoft MCU Software Team - * @note - * - * Copyright (C) 2018 Shanghai Eastsoft Microelectronics Co., Ltd. ALL rights reserved. - * - ************************************************************************************** - */ - -#ifndef __UART_H__ -#define __UART_H__ - - -/******************************************************************************/ -/* 设备特殊寄存器结构定义 */ -/******************************************************************************/ - -/* 允许匿名结构和匿名联合 */ -/* #pragma anon_unions */ - -/****************** Bit definition for UART_RXBUF register ************************/ - -#define UART_RXBUF_RXBUF_POSS 0U -#define UART_RXBUF_RXBUF_POSE 8U -#define UART_RXBUF_RXBUF_MSK BITS(UART_RXBUF_RXBUF_POSS,UART_RXBUF_RXBUF_POSE) - -/****************** Bit definition for UART_TXBUF register ************************/ - -#define UART_TXBUF_TXBUF_POSS 0U -#define UART_TXBUF_TXBUF_POSE 8U -#define UART_TXBUF_TXBUF_MSK BITS(UART_TXBUF_TXBUF_POSS,UART_TXBUF_TXBUF_POSE) - -/****************** Bit definition for UART_BRR register ************************/ - -#define UART_BRR_BRR_POSS 0U -#define UART_BRR_BRR_POSE 15U -#define UART_BRR_BRR_MSK BITS(UART_BRR_BRR_POSS,UART_BRR_BRR_POSE) - -/****************** Bit definition for UART_LCON register ************************/ - -#define UART_LCON_TXEN_POS 15U -#define UART_LCON_TXEN_MSK BIT(UART_LCON_TXEN_POS) - -#define UART_LCON_RXEN_POS 14U -#define UART_LCON_RXEN_MSK BIT(UART_LCON_RXEN_POS) - -#define UART_LCON_DBCEN_POS 13U -#define UART_LCON_DBCEN_MSK BIT(UART_LCON_DBCEN_POS) - -#define UART_LCON_BREAK_POS 10U -#define UART_LCON_BREAK_MSK BIT(UART_LCON_BREAK_POS) - -#define UART_LCON_SWAP_POS 9U -#define UART_LCON_SWAP_MSK BIT(UART_LCON_SWAP_POS) - -#define UART_LCON_TXINV_POS 8U -#define UART_LCON_TXINV_MSK BIT(UART_LCON_TXINV_POS) - -#define UART_LCON_RXINV_POS 7U -#define UART_LCON_RXINV_MSK BIT(UART_LCON_RXINV_POS) - -#define UART_LCON_DATAINV_POS 6U -#define UART_LCON_DATAINV_MSK BIT(UART_LCON_DATAINV_POS) - -#define UART_LCON_MSB_POS 5U -#define UART_LCON_MSB_MSK BIT(UART_LCON_MSB_POS) - -#define UART_LCON_PS_POS 4U -#define UART_LCON_PS_MSK BIT(UART_LCON_PS_POS) - -#define UART_LCON_PE_POS 3U -#define UART_LCON_PE_MSK BIT(UART_LCON_PE_POS) - -#define UART_LCON_STOP_POS 2U -#define UART_LCON_STOP_MSK BIT(UART_LCON_STOP_POS) - -#define UART_LCON_DLS_POSS 0U -#define UART_LCON_DLS_POSE 1U -#define UART_LCON_DLS_MSK BITS(UART_LCON_DLS_POSS,UART_LCON_DLS_POSE) - -/****************** Bit definition for UART_MCON register ************************/ - -#define UART_MCON_TXDMAEN_POS 15U -#define UART_MCON_TXDMAEN_MSK BIT(UART_MCON_TXDMAEN_POS) - -#define UART_MCON_RXDMAEN_POS 14U -#define UART_MCON_RXDMAEN_MSK BIT(UART_MCON_RXDMAEN_POS) - -#define UART_MCON_ABRREPT_POS 11U -#define UART_MCON_ABRREPT_MSK BIT(UART_MCON_ABRREPT_POS) - -#define UART_MCON_ABRMOD_POSS 9U -#define UART_MCON_ABRMOD_POSE 10U -#define UART_MCON_ABRMOD_MSK BITS(UART_MCON_ABRMOD_POSS,UART_MCON_ABRMOD_POSE) - -#define UART_MCON_ABREN_POS 8U -#define UART_MCON_ABREN_MSK BIT(UART_MCON_ABREN_POS) - -#define UART_MCON_BKREQ_POS 5U -#define UART_MCON_BKREQ_MSK BIT(UART_MCON_BKREQ_POS) - -#define UART_MCON_HDEN_POS 4U -#define UART_MCON_HDEN_MSK BIT(UART_MCON_HDEN_POS) - -#define UART_MCON_IREN_POS 3U -#define UART_MCON_IREN_MSK BIT(UART_MCON_IREN_POS) - -#define UART_MCON_AFCEN_POS 2U -#define UART_MCON_AFCEN_MSK BIT(UART_MCON_AFCEN_POS) - -#define UART_MCON_RTSSET_POS 1U -#define UART_MCON_RTSSET_MSK BIT(UART_MCON_RTSSET_POS) - -#define UART_MCON_LPBKEN_POS 0U -#define UART_MCON_LPBKEN_MSK BIT(UART_MCON_LPBKEN_POS) - -/****************** Bit definition for UART_RS485 register ************************/ - -#define UART_RS485_DLY_POSS 16U -#define UART_RS485_DLY_POSE 23U -#define UART_RS485_DLY_MSK BITS(UART_RS485_DLY_POSS,UART_RS485_DLY_POSE) - -#define UART_RS485_ADDR_POSS 8U -#define UART_RS485_ADDR_POSE 15U -#define UART_RS485_ADDR_MSK BITS(UART_RS485_ADDR_POSS,UART_RS485_ADDR_POSE) - -#define UART_RS485_AADINV_POS 3U -#define UART_RS485_AADINV_MSK BIT(UART_RS485_AADINV_POS) - -#define UART_RS485_AADACEN_POS 2U -#define UART_RS485_AADACEN_MSK BIT(UART_RS485_AADACEN_POS) - -#define UART_RS485_AADNEN_POS 1U -#define UART_RS485_AADNEN_MSK BIT(UART_RS485_AADNEN_POS) - -#define UART_RS485_AADEN_POS 0U -#define UART_RS485_AADEN_MSK BIT(UART_RS485_AADEN_POS) - -/****************** Bit definition for UART_SCARD register ************************/ - -#define UART_SCARD_BLEN_POSS 24U -#define UART_SCARD_BLEN_POSE 31U -#define UART_SCARD_BLEN_MSK BITS(UART_SCARD_BLEN_POSS,UART_SCARD_BLEN_POSE) - -#define UART_SCARD_GT_POSS 16U -#define UART_SCARD_GT_POSE 23U -#define UART_SCARD_GT_MSK BITS(UART_SCARD_GT_POSS,UART_SCARD_GT_POSE) - -#define UART_SCARD_PSC_POSS 8U -#define UART_SCARD_PSC_POSE 15U -#define UART_SCARD_PSC_MSK BITS(UART_SCARD_PSC_POSS,UART_SCARD_PSC_POSE) - -#define UART_SCARD_SCCNT_POSS 3U -#define UART_SCARD_SCCNT_POSE 5U -#define UART_SCARD_SCCNT_MSK BITS(UART_SCARD_SCCNT_POSS,UART_SCARD_SCCNT_POSE) - -#define UART_SCARD_SCLKEN_POS 2U -#define UART_SCARD_SCLKEN_MSK BIT(UART_SCARD_SCLKEN_POS) - -#define UART_SCARD_SCNACK_POS 1U -#define UART_SCARD_SCNACK_MSK BIT(UART_SCARD_SCNACK_POS) - -#define UART_SCARD_SCEN_POS 0U -#define UART_SCARD_SCEN_MSK BIT(UART_SCARD_SCEN_POS) - -/****************** Bit definition for UART_LIN register ************************/ - -#define UART_LIN_LINBKREQ_POS 2U -#define UART_LIN_LINBKREQ_MSK BIT(UART_LIN_LINBKREQ_POS) - -#define UART_LIN_LINBDL_POS 1U -#define UART_LIN_LINBDL_MSK BIT(UART_LIN_LINBDL_POS) - -#define UART_LIN_LINEN_POS 0U -#define UART_LIN_LINEN_MSK BIT(UART_LIN_LINEN_POS) - -/****************** Bit definition for UART_RTOR register ************************/ - -#define UART_RTOR_RTOEN_POS 24U -#define UART_RTOR_RTOEN_MSK BIT(UART_RTOR_RTOEN_POS) - -#define UART_RTOR_RTO_POSS 0U -#define UART_RTOR_RTO_POSE 23U -#define UART_RTOR_RTO_MSK BITS(UART_RTOR_RTO_POSS,UART_RTOR_RTO_POSE) - -/****************** Bit definition for UART_FCON register ************************/ - -#define UART_FCON_TXFL_POSS 11U -#define UART_FCON_TXFL_POSE 15U -#define UART_FCON_TXFL_MSK BITS(UART_FCON_TXFL_POSS,UART_FCON_TXFL_POSE) - -#define UART_FCON_TXTH_POSS 9U -#define UART_FCON_TXTH_POSE 10U -#define UART_FCON_TXTH_MSK BITS(UART_FCON_TXTH_POSS,UART_FCON_TXTH_POSE) - -#define UART_FCON_TFRST_POS 8U -#define UART_FCON_TFRST_MSK BIT(UART_FCON_TFRST_POS) - -#define UART_FCON_RXFL_POSS 3U -#define UART_FCON_RXFL_POSE 7U -#define UART_FCON_RXFL_MSK BITS(UART_FCON_RXFL_POSS,UART_FCON_RXFL_POSE) - -#define UART_FCON_RXTH_POSS 1U -#define UART_FCON_RXTH_POSE 2U -#define UART_FCON_RXTH_MSK BITS(UART_FCON_RXTH_POSS,UART_FCON_RXTH_POSE) - -#define UART_FCON_RFRST_POS 0U -#define UART_FCON_RFRST_MSK BIT(UART_FCON_RFRST_POS) - -/****************** Bit definition for UART_STAT register ************************/ - -#define UART_STAT_TFOERR_POS 18U -#define UART_STAT_TFOERR_MSK BIT(UART_STAT_TFOERR_POS) - -#define UART_STAT_TFFULL_POS 17U -#define UART_STAT_TFFULL_MSK BIT(UART_STAT_TFFULL_POS) - -#define UART_STAT_TFEMPTY_POS 16U -#define UART_STAT_TFEMPTY_MSK BIT(UART_STAT_TFEMPTY_POS) - -#define UART_STAT_TFTH_POS 15U -#define UART_STAT_TFTH_MSK BIT(UART_STAT_TFTH_POS) - -#define UART_STAT_TSBUSY_POS 14U -#define UART_STAT_TSBUSY_MSK BIT(UART_STAT_TSBUSY_POS) - -#define UART_STAT_RFUERR_POS 13U -#define UART_STAT_RFUERR_MSK BIT(UART_STAT_RFUERR_POS) - -#define UART_STAT_RFOERR_POS 12U -#define UART_STAT_RFOERR_MSK BIT(UART_STAT_RFOERR_POS) - -#define UART_STAT_RFFULL_POS 11U -#define UART_STAT_RFFULL_MSK BIT(UART_STAT_RFFULL_POS) - -#define UART_STAT_RFEMPTY_POS 10U -#define UART_STAT_RFEMPTY_MSK BIT(UART_STAT_RFEMPTY_POS) - -#define UART_STAT_RFTH_POS 9U -#define UART_STAT_RFTH_MSK BIT(UART_STAT_RFTH_POS) - -#define UART_STAT_RSBUSY_POS 8U -#define UART_STAT_RSBUSY_MSK BIT(UART_STAT_RSBUSY_POS) - -#define UART_STAT_CTSSTA_POS 3U -#define UART_STAT_CTSSTA_MSK BIT(UART_STAT_CTSSTA_POS) - -#define UART_STAT_BKERR_POS 2U -#define UART_STAT_BKERR_MSK BIT(UART_STAT_BKERR_POS) - -#define UART_STAT_FERR_POS 1U -#define UART_STAT_FERR_MSK BIT(UART_STAT_FERR_POS) - -#define UART_STAT_PERR_POS 0U -#define UART_STAT_PERR_MSK BIT(UART_STAT_PERR_POS) - -/****************** Bit definition for UART_IER register ************************/ - -#define UART_IER_TFOVER_POS 18U -#define UART_IER_TFOVER_MSK BIT(UART_IER_TFOVER_POS) - -#define UART_IER_TFEMPTY_POS 16U -#define UART_IER_TFEMPTY_MSK BIT(UART_IER_TFEMPTY_POS) - -#define UART_IER_TFTH_POS 15U -#define UART_IER_TFTH_MSK BIT(UART_IER_TFTH_POS) - -#define UART_IER_TBC_POS 14U -#define UART_IER_TBC_MSK BIT(UART_IER_TBC_POS) - -#define UART_IER_RFUERR_POS 13U -#define UART_IER_RFUERR_MSK BIT(UART_IER_RFUERR_POS) - -#define UART_IER_RFOERR_POS 12U -#define UART_IER_RFOERR_MSK BIT(UART_IER_RFOERR_POS) - -#define UART_IER_RFFULL_POS 11U -#define UART_IER_RFFULL_MSK BIT(UART_IER_RFFULL_POS) - -#define UART_IER_RFTH_POS 9U -#define UART_IER_RFTH_MSK BIT(UART_IER_RFTH_POS) - -#define UART_IER_NOISE_POS 8U -#define UART_IER_NOISE_MSK BIT(UART_IER_NOISE_POS) - -#define UART_IER_EOB_POS 7U -#define UART_IER_EOB_MSK BIT(UART_IER_EOB_POS) - -#define UART_IER_LINBK_POS 6U -#define UART_IER_LINBK_MSK BIT(UART_IER_LINBK_POS) - -#define UART_IER_ADDRM_POS 5U -#define UART_IER_ADDRM_MSK BIT(UART_IER_ADDRM_POS) - -#define UART_IER_RXTO_POS 4U -#define UART_IER_RXTO_MSK BIT(UART_IER_RXTO_POS) - -#define UART_IER_DCTS_POS 3U -#define UART_IER_DCTS_MSK BIT(UART_IER_DCTS_POS) - -#define UART_IER_ABTO_POS 2U -#define UART_IER_ABTO_MSK BIT(UART_IER_ABTO_POS) - -#define UART_IER_ABEND_POS 1U -#define UART_IER_ABEND_MSK BIT(UART_IER_ABEND_POS) - -#define UART_IER_RXBERR_POS 0U -#define UART_IER_RXBERR_MSK BIT(UART_IER_RXBERR_POS) - -/****************** Bit definition for UART_IDR register ************************/ - -#define UART_IDR_TFOVER_POS 18U -#define UART_IDR_TFOVER_MSK BIT(UART_IDR_TFOVER_POS) - -#define UART_IDR_TFEMPTY_POS 16U -#define UART_IDR_TFEMPTY_MSK BIT(UART_IDR_TFEMPTY_POS) - -#define UART_IDR_TFTH_POS 15U -#define UART_IDR_TFTH_MSK BIT(UART_IDR_TFTH_POS) - -#define UART_IDR_TBC_POS 14U -#define UART_IDR_TBC_MSK BIT(UART_IDR_TBC_POS) - -#define UART_IDR_RFUERR_POS 13U -#define UART_IDR_RFUERR_MSK BIT(UART_IDR_RFUERR_POS) - -#define UART_IDR_RFOERR_POS 12U -#define UART_IDR_RFOERR_MSK BIT(UART_IDR_RFOERR_POS) - -#define UART_IDR_RFFULL_POS 11U -#define UART_IDR_RFFULL_MSK BIT(UART_IDR_RFFULL_POS) - -#define UART_IDR_RFTH_POS 9U -#define UART_IDR_RFTH_MSK BIT(UART_IDR_RFTH_POS) - -#define UART_IDR_NOISE_POS 8U -#define UART_IDR_NOISE_MSK BIT(UART_IDR_NOISE_POS) - -#define UART_IDR_EOB_POS 7U -#define UART_IDR_EOB_MSK BIT(UART_IDR_EOB_POS) - -#define UART_IDR_LINBK_POS 6U -#define UART_IDR_LINBK_MSK BIT(UART_IDR_LINBK_POS) - -#define UART_IDR_ADDRM_POS 5U -#define UART_IDR_ADDRM_MSK BIT(UART_IDR_ADDRM_POS) - -#define UART_IDR_RXTO_POS 4U -#define UART_IDR_RXTO_MSK BIT(UART_IDR_RXTO_POS) - -#define UART_IDR_DCTS_POS 3U -#define UART_IDR_DCTS_MSK BIT(UART_IDR_DCTS_POS) - -#define UART_IDR_ABTO_POS 2U -#define UART_IDR_ABTO_MSK BIT(UART_IDR_ABTO_POS) - -#define UART_IDR_ABEND_POS 1U -#define UART_IDR_ABEND_MSK BIT(UART_IDR_ABEND_POS) - -#define UART_IDR_RXBERR_POS 0U -#define UART_IDR_RXBERR_MSK BIT(UART_IDR_RXBERR_POS) - -/****************** Bit definition for UART_IVS register ************************/ - -#define UART_IVS_TFOVER_POS 18U -#define UART_IVS_TFOVER_MSK BIT(UART_IVS_TFOVER_POS) - -#define UART_IVS_TFEMPTY_POS 16U -#define UART_IVS_TFEMPTY_MSK BIT(UART_IVS_TFEMPTY_POS) - -#define UART_IVS_TFTH_POS 15U -#define UART_IVS_TFTH_MSK BIT(UART_IVS_TFTH_POS) - -#define UART_IVS_TBC_POS 14U -#define UART_IVS_TBC_MSK BIT(UART_IVS_TBC_POS) - -#define UART_IVS_RFUERR_POS 13U -#define UART_IVS_RFUERR_MSK BIT(UART_IVS_RFUERR_POS) - -#define UART_IVS_RFOERR_POS 12U -#define UART_IVS_RFOERR_MSK BIT(UART_IVS_RFOERR_POS) - -#define UART_IVS_RFFULL_POS 11U -#define UART_IVS_RFFULL_MSK BIT(UART_IVS_RFFULL_POS) - -#define UART_IVS_RFTH_POS 9U -#define UART_IVS_RFTH_MSK BIT(UART_IVS_RFTH_POS) - -#define UART_IVS_NOISE_POS 8U -#define UART_IVS_NOISE_MSK BIT(UART_IVS_NOISE_POS) - -#define UART_IVS_EOB_POS 7U -#define UART_IVS_EOB_MSK BIT(UART_IVS_EOB_POS) - -#define UART_IVS_LINBK_POS 6U -#define UART_IVS_LINBK_MSK BIT(UART_IVS_LINBK_POS) - -#define UART_IVS_ADDRM_POS 5U -#define UART_IVS_ADDRM_MSK BIT(UART_IVS_ADDRM_POS) - -#define UART_IVS_RXTO_POS 4U -#define UART_IVS_RXTO_MSK BIT(UART_IVS_RXTO_POS) - -#define UART_IVS_DCTS_POS 3U -#define UART_IVS_DCTS_MSK BIT(UART_IVS_DCTS_POS) - -#define UART_IVS_ABTO_POS 2U -#define UART_IVS_ABTO_MSK BIT(UART_IVS_ABTO_POS) - -#define UART_IVS_ABEND_POS 1U -#define UART_IVS_ABEND_MSK BIT(UART_IVS_ABEND_POS) - -#define UART_IVS_RXBERR_POS 0U -#define UART_IVS_RXBERR_MSK BIT(UART_IVS_RXBERR_POS) - -/****************** Bit definition for UART_RIF register ************************/ - -#define UART_RIF_TFOVER_POS 18U -#define UART_RIF_TFOVER_MSK BIT(UART_RIF_TFOVER_POS) - -#define UART_RIF_TFEMPTY_POS 16U -#define UART_RIF_TFEMPTY_MSK BIT(UART_RIF_TFEMPTY_POS) - -#define UART_RIF_TFTH_POS 15U -#define UART_RIF_TFTH_MSK BIT(UART_RIF_TFTH_POS) - -#define UART_RIF_TBC_POS 14U -#define UART_RIF_TBC_MSK BIT(UART_RIF_TBC_POS) - -#define UART_RIF_RFUERR_POS 13U -#define UART_RIF_RFUERR_MSK BIT(UART_RIF_RFUERR_POS) - -#define UART_RIF_RFOERR_POS 12U -#define UART_RIF_RFOERR_MSK BIT(UART_RIF_RFOERR_POS) - -#define UART_RIF_RFFULL_POS 11U -#define UART_RIF_RFFULL_MSK BIT(UART_RIF_RFFULL_POS) - -#define UART_RIF_RFTH_POS 9U -#define UART_RIF_RFTH_MSK BIT(UART_RIF_RFTH_POS) - -#define UART_RIF_NOISE_POS 8U -#define UART_RIF_NOISE_MSK BIT(UART_RIF_NOISE_POS) - -#define UART_RIF_EOB_POS 7U -#define UART_RIF_EOB_MSK BIT(UART_RIF_EOB_POS) - -#define UART_RIF_LINBK_POS 6U -#define UART_RIF_LINBK_MSK BIT(UART_RIF_LINBK_POS) - -#define UART_RIF_ADDRM_POS 5U -#define UART_RIF_ADDRM_MSK BIT(UART_RIF_ADDRM_POS) - -#define UART_RIF_RXTO_POS 4U -#define UART_RIF_RXTO_MSK BIT(UART_RIF_RXTO_POS) - -#define UART_RIF_DCTS_POS 3U -#define UART_RIF_DCTS_MSK BIT(UART_RIF_DCTS_POS) - -#define UART_RIF_ABTO_POS 2U -#define UART_RIF_ABTO_MSK BIT(UART_RIF_ABTO_POS) - -#define UART_RIF_ABEND_POS 1U -#define UART_RIF_ABEND_MSK BIT(UART_RIF_ABEND_POS) - -#define UART_RIF_RXBERR_POS 0U -#define UART_RIF_RXBERR_MSK BIT(UART_RIF_RXBERR_POS) - -/****************** Bit definition for UART_IFM register ************************/ - -#define UART_IFM_TFOVER_POS 18U -#define UART_IFM_TFOVER_MSK BIT(UART_IFM_TFOVER_POS) - -#define UART_IFM_TFEMPTY_POS 16U -#define UART_IFM_TFEMPTY_MSK BIT(UART_IFM_TFEMPTY_POS) - -#define UART_IFM_TFTH_POS 15U -#define UART_IFM_TFTH_MSK BIT(UART_IFM_TFTH_POS) - -#define UART_IFM_TBC_POS 14U -#define UART_IFM_TBC_MSK BIT(UART_IFM_TBC_POS) - -#define UART_IFM_RFUERR_POS 13U -#define UART_IFM_RFUERR_MSK BIT(UART_IFM_RFUERR_POS) - -#define UART_IFM_RFOERR_POS 12U -#define UART_IFM_RFOERR_MSK BIT(UART_IFM_RFOERR_POS) - -#define UART_IFM_RFFULL_POS 11U -#define UART_IFM_RFFULL_MSK BIT(UART_IFM_RFFULL_POS) - -#define UART_IFM_RFTH_POS 9U -#define UART_IFM_RFTH_MSK BIT(UART_IFM_RFTH_POS) - -#define UART_IFM_NOISE_POS 8U -#define UART_IFM_NOISE_MSK BIT(UART_IFM_NOISE_POS) - -#define UART_IFM_EOB_POS 7U -#define UART_IFM_EOB_MSK BIT(UART_IFM_EOB_POS) - -#define UART_IFM_LINBK_POS 6U -#define UART_IFM_LINBK_MSK BIT(UART_IFM_LINBK_POS) - -#define UART_IFM_ADDRM_POS 5U -#define UART_IFM_ADDRM_MSK BIT(UART_IFM_ADDRM_POS) - -#define UART_IFM_RXTO_POS 4U -#define UART_IFM_RXTO_MSK BIT(UART_IFM_RXTO_POS) - -#define UART_IFM_DCTS_POS 3U -#define UART_IFM_DCTS_MSK BIT(UART_IFM_DCTS_POS) - -#define UART_IFM_ABTO_POS 2U -#define UART_IFM_ABTO_MSK BIT(UART_IFM_ABTO_POS) - -#define UART_IFM_ABEND_POS 1U -#define UART_IFM_ABEND_MSK BIT(UART_IFM_ABEND_POS) - -#define UART_IFM_RXBERR_POS 0U -#define UART_IFM_RXBERR_MSK BIT(UART_IFM_RXBERR_POS) - -/****************** Bit definition for UART_ICR register ************************/ - -#define UART_ICR_TFOVER_POS 18U -#define UART_ICR_TFOVER_MSK BIT(UART_ICR_TFOVER_POS) - -#define UART_ICR_TFEMPTY_POS 16U -#define UART_ICR_TFEMPTY_MSK BIT(UART_ICR_TFEMPTY_POS) - -#define UART_ICR_TFTH_POS 15U -#define UART_ICR_TFTH_MSK BIT(UART_ICR_TFTH_POS) - -#define UART_ICR_TBC_POS 14U -#define UART_ICR_TBC_MSK BIT(UART_ICR_TBC_POS) - -#define UART_ICR_RFUERR_POS 13U -#define UART_ICR_RFUERR_MSK BIT(UART_ICR_RFUERR_POS) - -#define UART_ICR_RFOERR_POS 12U -#define UART_ICR_RFOERR_MSK BIT(UART_ICR_RFOERR_POS) - -#define UART_ICR_RFFULL_POS 11U -#define UART_ICR_RFFULL_MSK BIT(UART_ICR_RFFULL_POS) - -#define UART_ICR_RFTH_POS 9U -#define UART_ICR_RFTH_MSK BIT(UART_ICR_RFTH_POS) - -#define UART_ICR_NOISE_POS 8U -#define UART_ICR_NOISE_MSK BIT(UART_ICR_NOISE_POS) - -#define UART_ICR_EOB_POS 7U -#define UART_ICR_EOB_MSK BIT(UART_ICR_EOB_POS) - -#define UART_ICR_LINBK_POS 6U -#define UART_ICR_LINBK_MSK BIT(UART_ICR_LINBK_POS) - -#define UART_ICR_ADDRM_POS 5U -#define UART_ICR_ADDRM_MSK BIT(UART_ICR_ADDRM_POS) - -#define UART_ICR_RXTO_POS 4U -#define UART_ICR_RXTO_MSK BIT(UART_ICR_RXTO_POS) - -#define UART_ICR_DCTS_POS 3U -#define UART_ICR_DCTS_MSK BIT(UART_ICR_DCTS_POS) - -#define UART_ICR_ABTO_POS 2U -#define UART_ICR_ABTO_MSK BIT(UART_ICR_ABTO_POS) - -#define UART_ICR_ABEND_POS 1U -#define UART_ICR_ABEND_MSK BIT(UART_ICR_ABEND_POS) - -#define UART_ICR_RXBERR_POS 0U -#define UART_ICR_RXBERR_MSK BIT(UART_ICR_RXBERR_POS) - -typedef struct -{ - __I uint32_t RXBUF; - __IO uint32_t TXBUF; - __IO uint32_t BRR; - __IO uint32_t LCON; - __IO uint32_t MCON; - __IO uint32_t RS485; - __IO uint32_t SCARD; - __IO uint32_t LIN; - __IO uint32_t RTOR; - __O uint32_t FCON; - __I uint32_t STAT; - __O uint32_t IER; - __O uint32_t IDR; - __I uint32_t IVS; - __I uint32_t RIF; - __I uint32_t IFM; - __O uint32_t ICR; -} UART_TypeDef; - - - - - -#endif diff --git a/bsp/essemi/es32f0271/libraries/CMSIS/Device/EastSoft/ES32F0271/Include/ES32F0271/reg_usb.h b/bsp/essemi/es32f0271/libraries/CMSIS/Device/EastSoft/ES32F0271/Include/ES32F0271/reg_usb.h deleted file mode 100644 index 9685806551..0000000000 --- a/bsp/essemi/es32f0271/libraries/CMSIS/Device/EastSoft/ES32F0271/Include/ES32F0271/reg_usb.h +++ /dev/null @@ -1,873 +0,0 @@ -/** - ************************************************************************************** - * @file reg_usb.h - * @brief USB Head File - * @data 5/22/2018 - * @author Eastsoft AE Team - * @note - * - * Copyright (C) 2018 Shanghai Eastsoft Microelectronics Co., Ltd. ALL rights reserved. - * - ************************************************************************************** - */ - -#ifndef __REG_USB_H__ -#define __REG_USB_H__ - - -/******************************************************************************/ -/* ṹ嶨 */ -/******************************************************************************/ - -/* ṹ */ -/* #pragma anon_unions */ - -/****************** Bit definition for USB_FADDR register ************************/ - -#define USB_FADDR_ADDR_POSS 0U -#define USB_FADDR_ADDR_POSE 6U -#define USB_FADDR_ADDR_MSK BITS(USB_FADDR_ADDR_POSS,USB_FADDR_ADDR_POSE) - -/****************** Bit definition for USB_POWER register ************************/ - -#define USB_POWER_ISOUDT_POSS 7U -#define USB_POWER_ISOUDT_MSK BIT(USB_POWER_ISOUDT_POSS) - -#define USB_POWER_RESET_POSS 3U -#define USB_POWER_RESET_MSK BIT(USB_POWER_RESET_POSS) - -#define USB_POWER_RESUME_POSS 2U -#define USB_POWER_RESUME_MSK BIT(USB_POWER_RESUME_POSS) - -#define USB_POWER_SUSPEND_POSS 1U -#define USB_POWER_SUSPEND_MSK BIT(USB_POWER_SUSPEND_POSS) - -#define USB_POWER_SUSPENDEN_POSS 0U -#define USB_POWER_SUSPENDEN_MSK BIT(USB_POWER_SUSPENDEN_POSS) - -/****************** Bit definition for USB_DPDMCTL register ************************/ - -#define USB_DPDMCTL_DPPUD_POSS 3U -#define USB_DPDMCTL_DPPUD_POSE 4U -#define USB_DPDMCTL_DPPUD_MSK BITS(USB_DPDMCTL_DPPUD_POSS,USB_DPDMCTL_DPPUD_POSE) - -#define USB_DPDMCTL_DMPUD_POSS 1U -#define USB_DPDMCTL_DMPUD_POSE 2U -#define USB_DPDMCTL_DMPUD_MSK BITS(USB_DPDMCTL_DMPUD_POSS,USB_DPDMCTL_DMPUD_POSE) - -#define USB_DPDMCTL_PHYPWREN_POS 0U -#define USB_DPDMCTL_PHYPWREN_MSK BIT(USB_DPDMCTL_PHYPWREN_POS) - -/****************** Bit definition for USB_SWCID register ************************/ - -#define USB_SWCID_HOST_POSS 1U -#define USB_SWCID_HOST_MSK BIT(USB_SWCID_HOST_POSS) - -#define USB_SWCID_CIDCTRL_POSS 0U -#define USB_SWCID_CIDCTRL_MSK BIT(USB_SWCID_CIDCTRL_POSS) - -/****************** Bit definition for USB_SWVBUS register ************************/ - -#define USB_SWVBUS_VALTH_POS 3U -#define USB_SWVBUS_VALTH_MSK BIT(USB_SWVBUS_VALTH_POS) - -#define USB_SWVBUS_SESVALTH_POS 2U -#define USB_SWVBUS_SESVALTH_MSK BIT(USB_SWVBUS_SESVALTH_POS) - -#define USB_SWVBUS_SESENDTH_POS 1U -#define USB_SWVBUS_SESENDTH_MSK BIT(USB_SWVBUS_SESENDTH_POS) - -#define USB_SWVBUS_SIGCTRL_POS 0U -#define USB_SWVBUS_SIGCTRL_MSK BIT(USB_SWVBUS_SIGCTRL_POS) - -/****************** Bit definition for USB_TMODE register ************************/ - -#define USB_TMODE_PROTECT_POSS 1U -#define USB_TMODE_PROTECT_POSE 7U -#define USB_TMODE_PROTECT_MSK BITS(USB_TMODE_PROTECT_POSS,USB_TMODE_PROTECT_POSE) - -#define USB_TMODE_ENABLE_POS 0U -#define USB_TMODE_ENABLE_MSK BIT(USB_TMODE_ENABLE_POS) - -/****************** Bit definition for USB_FRAME1 register ************************/ - -#define USB_FRAME1_LOWFRAME_POSS 0U -#define USB_FRAME1_LOWFRAME_POSE 7U -#define USB_FRAME1_LOWFRAME_MSK BITS(USB_FRAME1_LOWFRAME_POSS,USB_FRAME1_LOWFRAME_POSE) - -/****************** Bit definition for USB_FRAME2 register ************************/ - -#define USB_FRAME2_UPFRAME_POSS 0U -#define USB_FRAME2_UPFRAME_POSE 2U -#define USB_FRAME2_UPFRAME_MSK BITS(USB_FRAME2_UPFRAME_POSS,USB_FRAME2_UPFRAME_POSE) - -/****************** Bit definition for USB_INDEX register ************************/ - -#define USB_INDEX_EPTIDX_POSS 0U -#define USB_INDEX_EPTIDX_POSE 3U -#define USB_INDEX_EPTIDX_MSK BITS(USB_INDEX_EPTIDX_POSS,USB_INDEX_EPTIDX_POSE) - -/****************** Bit definition for USB_DEVCTRL register ************************/ - -#define USB_DEVCTRL_FSDEV_POS 6U -#define USB_DEVCTRL_FSDEV_MSK BIT(USB_DEVCTRL_FSDEV_POS) - -#define USB_DEVCTRL_LSDEV_POS 5U -#define USB_DEVCTRL_LSDEV_MSK BIT(USB_DEVCTRL_LSDEV_POS) - -#define USB_DEVCTRL_HOST_POS 2U -#define USB_DEVCTRL_HOST_MSK BIT(USB_DEVCTRL_HOST_POS) - -#define USB_DEVCTRL_HOSTREQ_POS 1U -#define USB_DEVCTRL_HOSTREQ_MSK BIT(USB_DEVCTRL_HOSTREQ_POS) - -#define USB_DEVCTRL_SESSION_POS 0U -#define USB_DEVCTRL_SESSION_MSK BIT(USB_DEVCTRL_SESSION_POS) - -/****************** Bit definition for USB_TXMAXP register ************************/ - -#define USB_TXMAXP_MAXSIZE_POSS 0U -#define USB_TXMAXP_MAXSIZE_POSE 7U -#define USB_TXMAXP_MAXSIZE_MSK BITS(USB_TXMAXP_MAXSIZE_POSS,USB_TXMAXP_MAXSIZE_POSE) - -/****************** Bit definition for USB_CSR0L_TXCSRL register ************************/ - -// -//Endpoint 0 -// -/* host mode */ -#define USB_CSR0L_TXCSRL_NAKTO_POS 7U -#define USB_CSR0L_TXCSRL_NAKTO_MSK BIT(USB_CSR0L_TXCSRL_NAKTO_POS) - -#define USB_CSR0L_TXCSRL_STATUSPKT_POS 6U -#define USB_CSR0L_TXCSRL_STATUSPKT_MSK BIT(USB_CSR0L_TXCSRL_STATUSPKT_POS) - -#define USB_CSR0L_TXCSRL_REQPKT_POS 5U -#define USB_CSR0L_TXCSRL_REQPKT_MSK BIT(USB_CSR0L_TXCSRL_REQPKT_POS) - -#define USB_CSR0L_TXCSRL_ERROR_POS 4U -#define USB_CSR0L_TXCSRL_ERROR_MSK BIT(USB_CSR0L_TXCSRL_ERROR_POS) - -#define USB_CSR0L_TXCSRL_SETUPPKT_POS 3U -#define USB_CSR0L_TXCSRL_SETUPPKT_MSK BIT(USB_CSR0L_TXCSRL_SETUPPKT_POS) - -/* device mode */ -#define USB_CSR0L_TXCSRL_SETENDC_POS 7U -#define USB_CSR0L_TXCSRL_SETENDC_MSK BIT(USB_CSR0L_TXCSRL_SETENDC_POS) - -#define USB_CSR0L_TXCSRL_RXRDYC_POS 6U -#define USB_CSR0L_TXCSRL_RXRDYC_MSK BIT(USB_CSR0L_TXCSRL_RXRDYC_POS) - -#define USB_CSR0L_TXCSRL_STALL_POS 5U -#define USB_CSR0L_TXCSRL_STALL_MSK BIT(USB_CSR0L_TXCSRL_STALL_POS) - -#define USB_CSR0L_TXCSRL_SETEND_POS 4U -#define USB_CSR0L_TXCSRL_SETEND_MSK BIT(USB_CSR0L_TXCSRL_SETEND_POS) - -#define USB_CSR0L_TXCSRL_DATAEND_POS 3U -#define USB_CSR0L_TXCSRL_DATAEND_MSK BIT(USB_CSR0L_TXCSRL_DATAEND_POS) - -#define USB_CSR0L_TXCSRL_STALLED_POS 2U -#define USB_CSR0L_TXCSRL_STALLED_MSK BIT(USB_CSR0L_TXCSRL_STALLED_POS) - -#define USB_CSR0L_TXCSRL_TXRDY_POS 1U -#define USB_CSR0L_TXCSRL_TXRDY_MSK BIT(USB_CSR0L_TXCSRL_TXRDY_POS) - -#define USB_CSR0L_TXCSRL_RXRDY_POS 0U -#define USB_CSR0L_TXCSRL_RXRDY_MSK BIT(USB_CSR0L_TXCSRL_RXRDY_POS) - -// -//Endpoint 1-6 -// -/* host mode */ -#define USB_CSR0L_TXCSRL_NACKOUT_POS 7U -#define USB_CSR0L_TXCSRL_NACKOUT_MSK BIT(USB_CSR0L_TXCSRL_NACKOUT_POS) - -#define USB_CSR0L_TXCSRL_CLRDATAT_POS 6U -#define USB_CSR0L_TXCSRL_CLRDATAT_MSK BIT(USB_CSR0L_TXCSRL_CLRDATAT_POS) - -#define USB_CSR0L_TXCSRL_RXSTALL_POS 5U -#define USB_CSR0L_TXCSRL_RXSTALL_MSK BIT(USB_CSR0L_TXCSRL_RXSTALL_POS) - -#define USB_CSR0L_TXCSRL_TXPKTRDY_POS 0U -#define USB_CSR0L_TXCSRL_TXPKTRDY_MSK BIT(USB_CSR0L_TXCSRL_TXPKTRDY_POS) - -/* device mode */ -#define USB_CSR0L_TXCSRL_INCOMPTX_POS 7U -#define USB_CSR0L_TXCSRL_INCOMPTX_MSK BIT(USB_CSR0L_TXCSRL_INCOMPTX_POS) - -#define USB_CSR0L_TXCSRL_CLRDATAT_POS 6U -#define USB_CSR0L_TXCSRL_CLRDATAT_MSK BIT(USB_CSR0L_TXCSRL_CLRDATAT_POS) - -#define USB_CSR0L_TXCSRL_SENTSTALL_POS 5U -#define USB_CSR0L_TXCSRL_SENTSTALL_MSK BIT(USB_CSR0L_TXCSRL_SENTSTALL_POS) - -#define USB_CSR0L_TXCSRL_SENDSTALL_POS 4U -#define USB_CSR0L_TXCSRL_SENDSTALL_MSK BIT(USB_CSR0L_TXCSRL_SENDSTALL_POS) - -#define USB_CSR0L_TXCSRL_FLUSHFIFO_POS 3U -#define USB_CSR0L_TXCSRL_FLUSHFIFO_MSK BIT(USB_CSR0L_TXCSRL_FLUSHFIFO_POS) - -#define USB_CSR0L_TXCSRL_UNDERRUN_POS 2U -#define USB_CSR0L_TXCSRL_UNDERRUN_MSK BIT(USB_CSR0L_TXCSRL_UNDERRUN_POS) - -#define USB_CSR0L_TXCSRL_FIFONE_POS 1U -#define USB_CSR0L_TXCSRL_FIFONE_MSK BIT(USB_CSR0L_TXCSRL_FIFONE_POS) - -#define USB_CSR0L_TXCSRL_TXPKTRDY_POS 0U -#define USB_CSR0L_TXCSRL_TXPKTRDY_MSK BIT(USB_CSR0L_TXCSRL_TXPKTRDY_POS) - -/****************** Bit definition for USB_CSR0H_TXCSRH register ************************/ -// -//For endpoint 0 -// -#define USB_CSR0H_TXCSRH_FLUSH_POS 0U -#define USB_CSR0H_TXCSRH_FLUSH_MSK BIT(USB_CSR0H_TXCSRH_FLUSH_POS) - -// -//For endpoint 1-6 -// -#define USB_CSR0H_TXCSRH_AUTOSET_POS 7U -#define USB_CSR0H_TXCSRH_AUTOSET_MSK BIT(USB_CSR0H_TXCSRH_AUTOSET_POS) - -#define USB_CSR0H_TXCSRH_ISO_POS 6U -#define USB_CSR0H_TXCSRH_ISO_MSK BIT(USB_CSR0H_TXCSRH_ISO_POS) - -#define USB_CSR0H_TXCSRH_MODE_POS 5U -#define USB_CSR0H_TXCSRH_MODE_MSK BIT(USB_CSR0H_TXCSRH_MODE_POS) - -#define USB_CSR0H_TXCSRH_FDT_POS 3U -#define USB_CSR0H_TXCSRH_FDT_MSK BIT(USB_CSR0H_TXCSRH_FDT_POS) - -/****************** Bit definition for USB_RXMAXP register ************************/ - -#define USB_RXMAXP_MAXSIZE_POSS 0U -#define USB_RXMAXP_MAXSIZE_POSE 7U -#define USB_RXMAXP_MAXSIZE_MSK BITS(USB_RXMAXP_MAXSIZE_POSS,USB_RXMAXP_MAXSIZE_POSE) - -/****************** Bit definition for USB_RXCSRL register ************************/ - -#define USB_RXCSRL_CLRDT_POS 7U -#define USB_RXCSRL_CLRDT_MSK BIT(USB_RXCSRL_CLRDT_POS) - -#define USB_RXCSRL_STALLED_POS 6U -#define USB_RXCSRL_STALLED_MSK BIT(USB_RXCSRL_STALLED_POS) - -#define USB_RXCSRL_REQPKT_POS 5U -#define USB_RXCSRL_REQPKT_MSK BIT(USB_RXCSRL_REQPKT_POS) - -#define USB_RXCSRL_STALL_POS 5U -#define USB_RXCSRL_STALL_MSK BIT(USB_RXCSRL_STALL_POS) - -#define USB_RXCSRL_FLUSH_POS 4U -#define USB_RXCSRL_FLUSH_MSK BIT(USB_RXCSRL_FLUSH_POS) - -#define USB_RXCSRL_DATAERR_NAKTO_POS 3U -#define USB_RXCSRL_DATAERR_NAKTO_MSK BIT(USB_RXCSRL_DATAERR_NAKTO_POS) - -#define USB_RXCSRL_ERROR_POS 2U -#define USB_RXCSRL_ERROR_MSK BIT(USB_RXCSRL_ERROR_POS) - -#define USB_RXCSRL_OVERRUN_POS 2U -#define USB_RXCSRL_OVERRUN_MSK BIT(USB_RXCSRL_OVERRUN_POS) - -#define USB_RXCSRL_FULL_POS 1U -#define USB_RXCSRL_FULL_MSK BIT(USB_RXCSRL_FULL_POS) - -#define USB_RXCSRL_RXRDY_POS 0U -#define USB_RXCSRL_RXRDY_MSK BIT(USB_RXCSRL_RXRDY_POS) - -/****************** Bit definition for USB_RXCSRH register ************************/ - -#define USB_RXCSRH_AUTOCLR_POS 7U -#define USB_RXCSRH_AUTOCLR_MSK BIT(USB_RXCSRH_AUTOCLR_POS) - -#define USB_RXCSRH_AUTOREQ_POS 6U -#define USB_RXCSRH_AUTOREQ_MSK BIT(USB_RXCSRH_AUTOREQ_POS) - -#define USB_RXCSRH_ISO_POS 6U -#define USB_RXCSRH_ISO_MSK BIT(USB_RXCSRH_ISO_POS) - -/****************** Bit definition for USB_RXCOUNT1 register ************************/ - -#define USB_RXCOUNT1_COUNT_POSS 0U -#define USB_RXCOUNT1_COUNT_POSE 6U -#define USB_RXCOUNT1_COUNT_MSK BITS(USB_RXCOUNT1_COUNT_POSS,USB_RXCOUNT1_COUNT_POSE) - -#define USB_RXCOUNT1_PKTLOW_POSS 0U -#define USB_RXCOUNT1_PKTLOW_POSE 7U -#define USB_RXCOUNT1_PKTLOW_MSK BITS(USB_RXCOUNT1_PKTLOW_POSS,USB_RXCOUNT1_PKTLOW_POSE) - -/****************** Bit definition for USB_RXCOUNT2 register ************************/ - -#define USB_RXCOUNT2_PKTHIGH_POSS 0U -#define USB_RXCOUNT2_PKTHIGH_POSE 2U -#define USB_RXCOUNT2_PKTHIGH_MSK BITS(USB_RXCOUNT2_PKTHIGH_POSS,USB_RXCOUNT2_PKTHIGH_POSE) - -/****************** Bit definition for USB_TXTYPE register ************************/ - -#define USB_TXTYPE_PROTOCOL_POSS 4U -#define USB_TXTYPE_PROTOCOL_POSE 5U -#define USB_TXTYPE_PROTOCOL_MSK BITS(USB_TXTYPE_PROTOCOL_POSS,USB_TXTYPE_PROTOCOL_POSE) - -#define USB_TXTYPE_TEPN_POSS 0U -#define USB_TXTYPE_TEPN_POSE 3U -#define USB_TXTYPE_TEPN_MSK BITS(USB_TXTYPE_TEPN_POSS,USB_TXTYPE_TEPN_POSE) - -/****************** Bit definition for USB_NAKLIMIT0_TXINTERVAL register ************************/ - -#define USB_NAKLIMIT0_TXINTERVAL_NAKLMT_POSS 0U -#define USB_NAKLIMIT0_TXINTERVAL_NAKLMT_POSE 7U -#define USB_NAKLIMIT0_TXINTERVAL_NAKLMT_MSK BITS(USB_NAKLIMIT0_TXINTERVAL_NAKLMT_POSS,USB_NAKLIMIT0_TXINTERVAL_NAKLMT_POSE) - -/****************** Bit definition for USB_RXTYPE register ************************/ - -#define USB_RXTYPE_PROTOCOL_POSS 4U -#define USB_RXTYPE_PROTOCOL_POSE 5U -#define USB_RXTYPE_PROTOCOL_MSK BITS(USB_RXTYPE_PROTOCOL_POSS,USB_RXTYPE_PROTOCOL_POSE) - -#define USB_RXTYPE_TEPN_POSS 0U -#define USB_RXTYPE_TEPN_POSE 3U -#define USB_RXTYPE_TEPN_MSK BITS(USB_RXTYPE_TEPN_POSS,USB_RXTYPE_TEPN_POSE) - -/****************** Bit definition for USB_RXINTERVAL register ************************/ - -#define USB_RXINTERVAL_NAKLMT_POSS 0U -#define USB_RXINTERVAL_NAKLMT_POSE 7U -#define USB_RXINTERVAL_NAKLMT_MSK BITS(USB_RXINTERVAL_NAKLMT_POSS,USB_RXINTERVAL_NAKLMT_POSE) - -/****************** Bit definition for USB_TXFIFO1 register ************************/ - -#define USB_TXFIFO1_ADDRL_POSS 0U -#define USB_TXFIFO1_ADDRL_POSE 7U -#define USB_TXFIFO1_ADDRL_MSK BITS(USB_TXFIFO1_ADDRL_POSS,USB_TXFIFO1_ADDRL_POSE) - -/****************** Bit definition for USB_TXFIFO2 register ************************/ - -#define USB_TXFIFO2_MAXPKTSIZE_POSS 5U -#define USB_TXFIFO2_MAXPKTSIZE_POSE 7U -#define USB_TXFIFO2_MAXPKTSIZE_MSK BITS(USB_TXFIFO2_MAXPKTSIZE_POSS,USB_TXFIFO2_MAXPKTSIZE_POSE) - -#define USB_TXFIFO2_DPB_POS 4U -#define USB_TXFIFO2_DPB_MSK BIT(USB_TXFIFO2_DPB_POS) - -#define USB_TXFIFO2_ADDRH_POSS 0U -#define USB_TXFIFO2_ADDRH_POSE 3U -#define USB_TXFIFO2_ADDRH_MSK BITS(USB_TXFIFO2_ADDRH_POSS,USB_TXFIFO2_ADDRH_POSE) - -/****************** Bit definition for USB_RXFIFO1 register ************************/ - -#define USB_RXFIFO1_ADDRL_POSS 0U -#define USB_RXFIFO1_ADDRL_POSE 7U -#define USB_RXFIFO1_ADDRL_MSK BITS(USB_RXFIFO1_ADDRL_POSS,USB_RXFIFO1_ADDRL_POSE) - -/****************** Bit definition for USB_RXFIFO2 register ************************/ - -#define USB_RXFIFO2_MAXPKTSIZE_POSS 5U -#define USB_RXFIFO2_MAXPKTSIZE_POSE 7U -#define USB_RXFIFO2_MAXPKTSIZE_MSK BITS(USB_RXFIFO2_MAXPKTSIZE_POSS,USB_RXFIFO2_MAXPKTSIZE_POSE) - -#define USB_RXFIFO2_DPB_POS 4U -#define USB_RXFIFO2_DPB_MSK BIT(USB_RXFIFO2_DPB_POS) - -#define USB_RXFIFO2_ADDRH_POSS 0U -#define USB_RXFIFO2_ADDRH_POSE 3U -#define USB_RXFIFO2_ADDRH_MSK BITS(USB_RXFIFO2_ADDRH_POSS,USB_RXFIFO2_ADDRH_POSE) - -/************* Bit definition for USB_EP0FIFO/USB_EPxFIFO register *****************/ - -#define USB_EPxFIFO_FIFO_POSS 0U -#define USB_EPxFIFO_FIFO_POSE 7U -#define USB_EPxFIFO_FIFO_MSK BITS(USB_EPxFIFO_FIFO_POSS,USB_EPxFIFO_FIFO_POSE) - -/****************** Bit definition for USB_TXIER register ************************/ - -#define USB_TXIER_EP6IE_POS 6U -#define USB_TXIER_EP6IE_MSK BIT(USB_TXIER_EP6IE_POS) - -#define USB_TXIER_EP5IE_POS 5U -#define USB_TXIER_EP5IE_MSK BIT(USB_TXIER_EP5IE_POS) - -#define USB_TXIER_EP4IE_POS 4U -#define USB_TXIER_EP4IE_MSK BIT(USB_TXIER_EP4IE_POS) - -#define USB_TXIER_EP3IE_POS 3U -#define USB_TXIER_EP3IE_MSK BIT(USB_TXIER_EP3IE_POS) - -#define USB_TXIER_EP2IE_POS 2U -#define USB_TXIER_EP2IE_MSK BIT(USB_TXIER_EP2IE_POS) - -#define USB_TXIER_EP1IE_POS 1U -#define USB_TXIER_EP1IE_MSK BIT(USB_TXIER_EP1IE_POS) - -#define USB_TXIER_EP0IE_POS 0U -#define USB_TXIER_EP0IE_MSK BIT(USB_TXIER_EP0IE_POS) - -/****************** Bit definition for USB_RXIER register ************************/ - -#define USB_RXIER_EP6IE_POS 6U -#define USB_RXIER_EP6IE_MSK BIT(USB_RXIER_EP6IE_POS) - -#define USB_RXIER_EP5IE_POS 5U -#define USB_RXIER_EP5IE_MSK BIT(USB_RXIER_EP5IE_POS) - -#define USB_RXIER_EP4IE_POS 4U -#define USB_RXIER_EP4IE_MSK BIT(USB_RXIER_EP4IE_POS) - -#define USB_RXIER_EP3IE_POS 3U -#define USB_RXIER_EP3IE_MSK BIT(USB_RXIER_EP3IE_POS) - -#define USB_RXIER_EP2IE_POS 2U -#define USB_RXIER_EP2IE_MSK BIT(USB_RXIER_EP2IE_POS) - -#define USB_RXIER_EP1IE_POS 1U -#define USB_RXIER_EP1IE_MSK BIT(USB_RXIER_EP1IE_POS) - -/****************** Bit definition for USB_TXIDR register ************************/ - -#define USB_TXIDR_EP6ID_POS 6U -#define USB_TXIDR_EP6ID_MSK BIT(USB_TXIDR_EP6ID_POS) - -#define USB_TXIDR_EP5ID_POS 5U -#define USB_TXIDR_EP5ID_MSK BIT(USB_TXIDR_EP5ID_POS) - -#define USB_TXIDR_EP4ID_POS 4U -#define USB_TXIDR_EP4ID_MSK BIT(USB_TXIDR_EP4ID_POS) - -#define USB_TXIDR_EP3ID_POS 3U -#define USB_TXIDR_EP3ID_MSK BIT(USB_TXIDR_EP3ID_POS) - -#define USB_TXIDR_EP2ID_POS 2U -#define USB_TXIDR_EP2ID_MSK BIT(USB_TXIDR_EP2ID_POS) - -#define USB_TXIDR_EP1ID_POS 1U -#define USB_TXIDR_EP1ID_MSK BIT(USB_TXIDR_EP1ID_POS) - -#define USB_TXIDR_EP0ID_POS 0U -#define USB_TXIDR_EP0ID_MSK BIT(USB_TXIDR_EP0ID_POS) - -/****************** Bit definition for USB_RXIDR register ************************/ - -#define USB_RXIDR_EP6ID_POS 6U -#define USB_RXIDR_EP6ID_MSK BIT(USB_RXIDR_EP6ID_POS) - -#define USB_RXIDR_EP5ID_POS 5U -#define USB_RXIDR_EP5ID_MSK BIT(USB_RXIDR_EP5ID_POS) - -#define USB_RXIDR_EP4ID_POS 4U -#define USB_RXIDR_EP4ID_MSK BIT(USB_RXIDR_EP4ID_POS) - -#define USB_RXIDR_EP3ID_POS 3U -#define USB_RXIDR_EP3ID_MSK BIT(USB_RXIDR_EP3ID_POS) - -#define USB_RXIDR_EP2ID_POS 2U -#define USB_RXIDR_EP2ID_MSK BIT(USB_RXIDR_EP2ID_POS) - -#define USB_RXIDR_EP1ID_POS 1U -#define USB_RXIDR_EP1ID_MSK BIT(USB_RXIDR_EP1ID_POS) - -/****************** Bit definition for USB_TXIVS register ************************/ - -#define USB_TXIVS_EP6IVS_POS 6U -#define USB_TXIVS_EP6IVS_MSK BIT(USB_TXIVS_EP6IVS_POS) - -#define USB_TXIVS_EP5IVS_POS 5U -#define USB_TXIVS_EP5IVS_MSK BIT(USB_TXIVS_EP5IVS_POS) - -#define USB_TXIVS_EP4IVS_POS 4U -#define USB_TXIVS_EP4IVS_MSK BIT(USB_TXIVS_EP4IVS_POS) - -#define USB_TXIVS_EP3IVS_POS 3U -#define USB_TXIVS_EP3IVS_MSK BIT(USB_TXIVS_EP3IVS_POS) - -#define USB_TXIVS_EP2IVS_POS 2U -#define USB_TXIVS_EP2IVS_MSK BIT(USB_TXIVS_EP2IVS_POS) - -#define USB_TXIVS_EP1IVS_POS 1U -#define USB_TXIVS_EP1IVS_MSK BIT(USB_TXIVS_EP1IVS_POS) - -#define USB_TXIVS_EP0IVS_POS 0U -#define USB_TXIVS_EP0IVS_MSK BIT(USB_TXIVS_EP0IVS_POS) - -/****************** Bit definition for USB_RXIVS register ************************/ - -#define USB_RXIVS_EP6IVS_POS 6U -#define USB_RXIVS_EP6IVS_MSK BIT(USB_RXIVS_EP6IVS_POS) - -#define USB_RXIVS_EP5IVS_POS 5U -#define USB_RXIVS_EP5IVS_MSK BIT(USB_RXIVS_EP5IVS_POS) - -#define USB_RXIVS_EP4IVS_POS 4U -#define USB_RXIVS_EP4IVS_MSK BIT(USB_RXIVS_EP4IVS_POS) - -#define USB_RXIVS_EP3IVS_POS 3U -#define USB_RXIVS_EP3IVS_MSK BIT(USB_RXIVS_EP3IVS_POS) - -#define USB_RXIVS_EP2IVS_POS 2U -#define USB_RXIVS_EP2IVS_MSK BIT(USB_RXIVS_EP2IVS_POS) - -#define USB_RXIVS_EP1IVS_POS 1U -#define USB_RXIVS_EP1IVS_MSK BIT(USB_RXIVS_EP1IVS_POS) - -/****************** Bit definition for USB_TXRIF register ************************/ - -#define USB_TXRIF_EP6RIF_POS 6U -#define USB_TXRIF_EP6RIF_MSK BIT(USB_TXRIF_EP6RIF_POS) - -#define USB_TXRIF_EP5RIF_POS 5U -#define USB_TXRIF_EP5RIF_MSK BIT(USB_TXRIF_EP5RIF_POS) - -#define USB_TXRIF_EP4RIF_POS 4U -#define USB_TXRIF_EP4RIF_MSK BIT(USB_TXRIF_EP4RIF_POS) - -#define USB_TXRIF_EP3RIF_POS 3U -#define USB_TXRIF_EP3RIF_MSK BIT(USB_TXRIF_EP3RIF_POS) - -#define USB_TXRIF_EP2RIF_POS 2U -#define USB_TXRIF_EP2RIF_MSK BIT(USB_TXRIF_EP2RIF_POS) - -#define USB_TXRIF_EP1RIF_POS 1U -#define USB_TXRIF_EP1RIF_MSK BIT(USB_TXRIF_EP1RIF_POS) - -#define USB_TXRIF_EP0RIF_POS 0U -#define USB_TXRIF_EP0RIF_MSK BIT(USB_TXRIF_EP0RIF_POS) - -/****************** Bit definition for USB_RXRIF register ************************/ - -#define USB_RXRIF_EP6RIF_POS 6U -#define USB_RXRIF_EP6RIF_MSK BIT(USB_RXRIF_EP6RIF_POS) - -#define USB_RXRIF_EP5RIF_POS 5U -#define USB_RXRIF_EP5RIF_MSK BIT(USB_RXRIF_EP5RIF_POS) - -#define USB_RXRIF_EP4RIF_POS 4U -#define USB_RXRIF_EP4RIF_MSK BIT(USB_RXRIF_EP4RIF_POS) - -#define USB_RXRIF_EP3RIF_POS 3U -#define USB_RXRIF_EP3RIF_MSK BIT(USB_RXRIF_EP3RIF_POS) - -#define USB_RXRIF_EP2RIF_POS 2U -#define USB_RXRIF_EP2RIF_MSK BIT(USB_RXRIF_EP2RIF_POS) - -#define USB_RXRIF_EP1RIF_POS 1U -#define USB_RXRIF_EP1RIF_MSK BIT(USB_RXRIF_EP1RIF_POS) - -/****************** Bit definition for USB_TXIFM register ************************/ - -#define USB_TXIFM_EP6IFM_POS 6U -#define USB_TXIFM_EP6IFM_MSK BIT(USB_TXIFM_EP6IFM_POS) - -#define USB_TXIFM_EP5IFM_POS 5U -#define USB_TXIFM_EP5IFM_MSK BIT(USB_TXIFM_EP5IFM_POS) - -#define USB_TXIFM_EP4IFM_POS 4U -#define USB_TXIFM_EP4IFM_MSK BIT(USB_TXIFM_EP4IFM_POS) - -#define USB_TXIFM_EP3IFM_POS 3U -#define USB_TXIFM_EP3IFM_MSK BIT(USB_TXIFM_EP3IFM_POS) - -#define USB_TXIFM_EP2IFM_POS 2U -#define USB_TXIFM_EP2IFM_MSK BIT(USB_TXIFM_EP2IFM_POS) - -#define USB_TXIFM_EP1IFM_POS 1U -#define USB_TXIFM_EP1IFM_MSK BIT(USB_TXIFM_EP1IFM_POS) - -#define USB_TXIFM_EP0IFM_POS 0U -#define USB_TXIFM_EP0IFM_MSK BIT(USB_TXIFM_EP0IFM_POS) - -/****************** Bit definition for USB_RXIFM register ************************/ - -#define USB_RXIFM_EP6IFM_POS 6U -#define USB_RXIFM_EP6IFM_MSK BIT(USB_RXIFM_EP6IFM_POS) - -#define USB_RXIFM_EP5IFM_POS 5U -#define USB_RXIFM_EP5IFM_MSK BIT(USB_RXIFM_EP5IFM_POS) - -#define USB_RXIFM_EP4IFM_POS 4U -#define USB_RXIFM_EP4IFM_MSK BIT(USB_RXIFM_EP4IFM_POS) - -#define USB_RXIFM_EP3IFM_POS 3U -#define USB_RXIFM_EP3IFM_MSK BIT(USB_RXIFM_EP3IFM_POS) - -#define USB_RXIFM_EP2IFM_POS 2U -#define USB_RXIFM_EP2IFM_MSK BIT(USB_RXIFM_EP2IFM_POS) - -#define USB_RXIFM_EP1IFM_POS 1U -#define USB_RXIFM_EP1IFM_MSK BIT(USB_RXIFM_EP1IFM_POS) - -/****************** Bit definition for USB_TXICR register ************************/ - -#define USB_TXICR_EP6ICR_POS 6U -#define USB_TXICR_EP6ICR_MSK BIT(USB_TXICR_EP6ICR_POS) - -#define USB_TXICR_EP5ICR_POS 5U -#define USB_TXICR_EP5ICR_MSK BIT(USB_TXICR_EP5ICR_POS) - -#define USB_TXICR_EP4ICR_POS 4U -#define USB_TXICR_EP4ICR_MSK BIT(USB_TXICR_EP4ICR_POS) - -#define USB_TXICR_EP3ICR_POS 3U -#define USB_TXICR_EP3ICR_MSK BIT(USB_TXICR_EP3ICR_POS) - -#define USB_TXICR_EP2ICR_POS 2U -#define USB_TXICR_EP2ICR_MSK BIT(USB_TXICR_EP2ICR_POS) - -#define USB_TXICR_EP1ICR_POS 1U -#define USB_TXICR_EP1ICR_MSK BIT(USB_TXICR_EP1ICR_POS) - -#define USB_TXICR_EP0ICR_POS 0U -#define USB_TXICR_EP0ICR_MSK BIT(USB_TXICR_EP0ICR_POS) - -/****************** Bit definition for USB_RXICR register ************************/ - -#define USB_RXICR_EP6ICR_POS 6U -#define USB_RXICR_EP6ICR_MSK BIT(USB_RXICR_EP6ICR_POS) - -#define USB_RXICR_EP5ICR_POS 5U -#define USB_RXICR_EP5ICR_MSK BIT(USB_RXICR_EP5ICR_POS) - -#define USB_RXICR_EP4ICR_POS 4U -#define USB_RXICR_EP4ICR_MSK BIT(USB_RXICR_EP4ICR_POS) - -#define USB_RXICR_EP3ICR_POS 3U -#define USB_RXICR_EP3ICR_MSK BIT(USB_RXICR_EP3ICR_POS) - -#define USB_RXICR_EP2ICR_POS 2U -#define USB_RXICR_EP2ICR_MSK BIT(USB_RXICR_EP2ICR_POS) - -#define USB_RXICR_EP1ICR_POS 1U -#define USB_RXICR_EP1ICR_MSK BIT(USB_RXICR_EP1ICR_POS) - -/****************** Bit definition for USB_IER register ************************/ - -#define USB_IER_SESREQIE_POS 6U -#define USB_IER_SESREQIE_MSK BIT(USB_IER_SESREQIE_POS) - -#define USB_IER_DISCONIE_POS 5U -#define USB_IER_DISCONIE_MSK BIT(USB_IER_DISCONIE_POS) - -#define USB_IER_CONIE_POS 4U -#define USB_IER_CONIE_MSK BIT(USB_IER_CONIE_POS) - -#define USB_IER_SOFIE_POS 3U -#define USB_IER_SOFIE_MSK BIT(USB_IER_SOFIE_POS) - -#define USB_IER_BABIE_POS 2U -#define USB_IER_BABIE_MSK BIT(USB_IER_BABIE_POS) - -#define USB_IER_RESTIE_POS 2U -#define USB_IER_RESTIE_MSK BIT(USB_IER_RESTIE_POS) - -#define USB_IER_RESIE_POS 1U -#define USB_IER_RESIE_MSK BIT(USB_IER_RESIE_POS) - -#define USB_IER_SUSPDIE_POS 0U -#define USB_IER_SUSPDIE_MSK BIT(USB_IER_SUSPDIE_POS) - -/****************** Bit definition for USB_IDR register ************************/ - -#define USB_IDR_SESREQID_POS 6U -#define USB_IDR_SESREQID_MSK BIT(USB_IDR_SESREQID_POS) - -#define USB_IDR_DISCONID_POS 5U -#define USB_IDR_DISCONID_MSK BIT(USB_IDR_DISCONID_POS) - -#define USB_IDR_CONID_POS 4U -#define USB_IDR_CONID_MSK BIT(USB_IDR_CONID_POS) - -#define USB_IDR_SOFID_POS 3U -#define USB_IDR_SOFID_MSK BIT(USB_IDR_SOFID_POS) - -#define USB_IDR_BABID_POS 2U -#define USB_IDR_BABID_MSK BIT(USB_IDR_BABID_POS) - -#define USB_IDR_RESTID_POS 2U -#define USB_IDR_RESTID_MSK BIT(USB_IDR_RESTID_POS) - -#define USB_IDR_RESID_POS 1U -#define USB_IDR_RESID_MSK BIT(USB_IDR_RESID_POS) - -#define USB_IDR_SUSPDID_POS 0U -#define USB_IDR_SUSPDID_MSK BIT(USB_IDR_SUSPDID_POS) - -/****************** Bit definition for USB_IVS register ************************/ - -#define USB_IVS_SESREQIVS_POS 6U -#define USB_IVS_SESREQIVS_MSK BIT(USB_IVS_SESREQIVS_POS) - -#define USB_IVS_DISCONIVS_POS 5U -#define USB_IVS_DISCONIVS_MSK BIT(USB_IVS_DISCONIVS_POS) - -#define USB_IVS_CONIVS_POS 4U -#define USB_IVS_CONIVS_MSK BIT(USB_IVS_CONIVS_POS) - -#define USB_IVS_SOFIVS_POS 3U -#define USB_IVS_SOFIVS_MSK BIT(USB_IVS_SOFIVS_POS) - -#define USB_IVS_BABIVS_POS 2U -#define USB_IVS_BABIVS_MSK BIT(USB_IVS_BABIVS_POS) - -#define USB_IVS_RESTIVS_POS 2U -#define USB_IVS_RESTIVS_MSK BIT(USB_IVS_RESTIVS_POS) - -#define USB_IVS_RESIVS_POS 1U -#define USB_IVS_RESIVS_MSK BIT(USB_IVS_RESIVS_POS) - -#define USB_IVS_SUSPDIVS_POS 0U -#define USB_IVS_SUSPDIVS_MSK BIT(USB_IVS_SUSPDIVS_POS) - -/****************** Bit definition for USB_RIF register ************************/ - -#define USB_RIF_SESREQRIF_POS 6U -#define USB_RIF_SESREQRIF_MSK BIT(USB_RIF_SESREQRIF_POS) - -#define USB_RIF_DISCONRIF_POS 5U -#define USB_RIF_DISCONRIF_MSK BIT(USB_RIF_DISCONRIF_POS) - -#define USB_RIF_CONRIF_POS 4U -#define USB_RIF_CONRIF_MSK BIT(USB_RIF_CONRIF_POS) - -#define USB_RIF_SOFRIF_POS 3U -#define USB_RIF_SOFRIF_MSK BIT(USB_RIF_SOFRIF_POS) - -#define USB_RIF_BABRIF_POS 2U -#define USB_RIF_BABRIF_MSK BIT(USB_RIF_BABRIF_POS) - -#define USB_RIF_RESTRIF_POS 2U -#define USB_RIF_RESTRIF_MSK BIT(USB_RIF_RESTRIF_POS) - -#define USB_RIF_RESRIF_POS 1U -#define USB_RIF_RESRIF_MSK BIT(USB_RIF_RESRIF_POS) - -#define USB_RIF_SUSPDRIF_POS 0U -#define USB_RIF_SUSPDRIF_MSK BIT(USB_RIF_SUSPDRIF_POS) - -/****************** Bit definition for USB_IFM register ************************/ - -#define USB_IFM_SESREQIFM_POS 6U -#define USB_IFM_SESREQIFM_MSK BIT(USB_IFM_SESREQIFM_POS) - -#define USB_IFM_DISCONIFM_POS 5U -#define USB_IFM_DISCONIFM_MSK BIT(USB_IFM_DISCONIFM_POS) - -#define USB_IFM_CONIFM_POS 4U -#define USB_IFM_CONIFM_MSK BIT(USB_IFM_CONIFM_POS) - -#define USB_IFM_SOFIFM_POS 3U -#define USB_IFM_SOFIFM_MSK BIT(USB_IFM_SOFIFM_POS) - -#define USB_IFM_BABIFM_POS 2U -#define USB_IFM_BABIFM_MSK BIT(USB_IFM_BABIFM_POS) - -#define USB_IFM_RESTIFM_POS 2U -#define USB_IFM_RESTIFM_MSK BIT(USB_IFM_RESTIFM_POS) - -#define USB_IFM_RESIFM_POS 1U -#define USB_IFM_RESIFM_MSK BIT(USB_IFM_RESIFM_POS) - -#define USB_IFM_SUSPDIFM_POS 0U -#define USB_IFM_SUSPDIFM_MSK BIT(USB_IFM_SUSPDIFM_POS) - -/****************** Bit definition for USB_ICR register ************************/ - -#define USB_ICR_SESREQICR_POS 6U -#define USB_ICR_SESREQICR_MSK BIT(USB_ICR_SESREQICR_POS) - -#define USB_ICR_DISCONICR_POS 5U -#define USB_ICR_DISCONICR_MSK BIT(USB_ICR_DISCONICR_POS) - -#define USB_ICR_CONICR_POS 4U -#define USB_ICR_CONICR_MSK BIT(USB_ICR_CONICR_POS) - -#define USB_ICR_SOFICR_POS 3U -#define USB_ICR_SOFICR_MSK BIT(USB_ICR_SOFICR_POS) - -#define USB_ICR_BABICR_POS 2U -#define USB_ICR_BABICR_MSK BIT(USB_ICR_BABICR_POS) - -#define USB_ICR_RESTICR_POS 2U -#define USB_ICR_RESTICR_MSK BIT(USB_ICR_RESTICR_POS) - -#define USB_ICR_RESICR_POS 1U -#define USB_ICR_RESICR_MSK BIT(USB_ICR_RESICR_POS) - -#define USB_ICR_SUSPDICR_POS 0U -#define USB_ICR_SUSPDICR_MSK BIT(USB_ICR_SUSPDICR_POS) - -typedef struct -{ - __IO uint8_t FADDR ; //0x0000 Function address register. - __IO uint8_t POWER ; //0x0001 Power management register. - __IO uint8_t DPDMCTRL ; //0x0002 DP DM Control register. - __IO uint8_t SWCID ; //0x0003 Softwave CID register. - __IO uint8_t SWVBUS ; //0x0004 Softwave VBUS register. - __IO uint8_t TMODE ; //0x0005 Test Mode register. - __IO uint8_t RES002[6] ; //0x0006~0x0B, Reserved - __IO uint8_t FRAME1 ; //0x000C, Frame number bits 0 to 7. - __IO uint8_t FRAME2 ; //0x000D, Frame number bits 8 to 10. - __IO uint8_t INDEX ; //0x000E, Index register for selecting the endp - __IO uint8_t DEVCTRL ; //0x000F, USB device control register. - __IO uint8_t TXMAXP ; //0x0010, Peripheral mode - Maximum packet size - __IO uint8_t CSR0L_TXCSRL ;//0x0011, Peripheral mode - Control Status regi - __IO uint8_t CSR0H_TXCSRH ;//0x0012, Peripheral mode - Control Status regi - __IO uint8_t RXMAXP ; //0x0013, Peripheral mode - Maximum packet size - __IO uint8_t RXCSR1 ; //0x0014, Peripheral mode - Control Status regi - __IO uint8_t RXCSR2 ; //0x0015, Peripheral mode - Control Status regi - __IO uint8_t RXCOUNT1 ; //0x0016, Peripheral mode - Number of bytes in - __IO uint8_t RXCOUNT2 ; //0x0017, Peripheral mode - Number of bytes in - __IO uint8_t TXTYPE ; //0x0018, Peripheral mode - // - __IO uint8_t NAKLIMIT0_TXINTERVAL ; //0x0019, Peripheral mode - // - __IO uint8_t RXTYPE ; //0x001A, Peripheral mode - // - __IO uint8_t RXINTERVAL ; //0x001B, Peripheral mode - // - __IO uint8_t TXFIFO1 ; //0x001C, Tx Endpoint FIFO details - __IO uint8_t TXFIFO2 ; //0x001D, Tx Endpoint FIFO details - __IO uint8_t RXFIFO1 ; //0x001E, Rx Endpoint FIFO details - __IO uint8_t RXFIFO2 ; //0x001F, Rx Endpoint FIFO details - __IO uint8_t EP0FIFO ; //0x0020, FIFOs for Endpoints 0. - __IO uint8_t RES021[3] ; //0x0021~0x23, Reserved - __IO uint8_t EP1FIFO ; //0x0024, FIFOs for Endpoints 1. - __IO uint8_t RES025[3] ; //0x0025~0x27, Reserved - __IO uint8_t EP2FIFO ; //0x0028, FIFOs for Endpoints 2. - __IO uint8_t RES029[3] ; //0x0029~0x2B, Reserved - __IO uint8_t EP3FIFO ; //0x002C, FIFOs for Endpoints 3. - __IO uint8_t RES02D[3] ; //0x002D~0x2F, Reserved - __IO uint8_t EP4FIFO ; //0x0030, FIFOs for Endpoints 4. - __IO uint8_t RES031[3] ; //0x0031~0x33, Reserved - __IO uint8_t EP5FIFO ; //0x0034, FIFOs for Endpoints 5. - __IO uint8_t RES035[3] ; //0x0035~0x37, Reserved - __IO uint8_t EP6FIFO ; //0x0038, FIFOs for Endpoints 6. - __IO uint8_t RES039[71] ; //0x0039~0x7C, Reserved - __IO uint8_t TXIER ; //0x0080, TX Endpoint 0~6 Interrupt Enable - __IO uint8_t RES081 ; //0x0081, Reserved - __IO uint8_t RXIER ; //0x0082, RX Endpoint 0~6 Interrupt Enable - __IO uint8_t RES083 ; //0x0083, Reserved - __IO uint8_t TXIDR ; //0x0084, TX Endpoint 0~6 Interrupt Disable - __IO uint8_t RES085 ; //0x0085, Reserved - __IO uint8_t RXIDR ; //0x0086, RX Endpoint 0~6 Interrupt Disable - __IO uint8_t RES087 ; //0x0087, Reserved - __IO uint8_t TXIVS ; //0x0088, TX Endpoint 0~6 Interrupt Valid Status - __IO uint8_t RES089 ; //0x0089, Reserved - __IO uint8_t RXIVS ; //0x008A, RX Endpoint 0~6 Interrupt Valid Status - __IO uint8_t RES08B ; //0x008B, Reserved - __IO uint8_t TXRIF ; //0x008C, TX Endpoint 0~6 Raw Interrupt Flag Status - __IO uint8_t RES08D ; //0x008D, Reserved - __IO uint8_t RXRIF ; //0x008E, RX Endpoint 0~6 Raw Interrupt Flag Status - __IO uint8_t RES08F ; //0x008F, Reserved - __IO uint8_t TXIFM ; //0x0090, TX Endpoint 0~6 Interrupt Flag Masked Status - __IO uint8_t RES091 ; //0x0091, Reserved - __IO uint8_t RXIFM ; //0x0092, RX Endpoint 0~6 Interrupt Flag Masked Status - __IO uint8_t RES093 ; //0x0093, Reserved - __IO uint8_t TXICR ; //0x0094, TX Endpoint 0~6 Interrupt Clear Register - __IO uint8_t RES095 ; //0x0095, Reserved - __IO uint8_t RXICR ; //0x0096, RX Endpoint 0~6 Interrupt Clear Register - __IO uint8_t RES097[9] ; //0x0097~0x9C, Reserved - __O uint32_t IER ; //0x00A0, USB Interrupt Enable Register - __O uint32_t IDR ; //0x00A4, USB Interrupt Disable Register - __I uint32_t IVS ; //0x00A8, USB Interrupt Valid Register - __I uint32_t RIF ; //0x00AC, USB Raw Interrupt Flag Status Register - __I uint32_t IFM ; //0x00B0, USB Interrupt Flag Masked Status - __O uint32_t ICR ; //0x00B4, USB Interrupt Clear Register -} USBCTRL_TypeDef; - - -#endif diff --git a/bsp/essemi/es32f0271/libraries/CMSIS/Device/EastSoft/ES32F0271/Include/ES32F0271/reg_wwdg.h b/bsp/essemi/es32f0271/libraries/CMSIS/Device/EastSoft/ES32F0271/Include/ES32F0271/reg_wwdg.h deleted file mode 100644 index 0c64ea3d43..0000000000 --- a/bsp/essemi/es32f0271/libraries/CMSIS/Device/EastSoft/ES32F0271/Include/ES32F0271/reg_wwdg.h +++ /dev/null @@ -1,88 +0,0 @@ -/** - ************************************************************************************** - * @file reg_WWDG.h - * @brief WWDG Head File - * - * @version V1.00.01 - * @data 19/10/2018 - * @author Eastsoft AE Team - * @note - * - * Copyright (C) 2018 Shanghai Eastsoft Microelectronics Co., Ltd. ALL rights reserved. - * - ************************************************************************************** - */ - -#ifndef __WWDG_H__ -#define __WWDG_H__ - -typedef struct -{ - __IO uint32_t CR; /* 0x00 WWDG_CR Control register */ - __IO uint32_t CFR; /* 0x04 WWDG_CFR Configuration register */ - __O uint32_t IER; /* 0x08 WWDG_IER Interrupt enable register */ - __O uint32_t IDR; /* 0x0C WWDG_IDR Interrupt disable register */ - __I uint32_t IVS; /* 0x10 WWDG_IVS Interrupt valid status */ - __I uint32_t RIF; /* 0x14 WWDG_RIF Raw interrupt flag */ - __I uint32_t IFM; /* 0x18 WWDG_IFM Interrupt flag masked */ - __O uint32_t ICR; /* 0x1C WWDG_ICR Interrupt clear register */ -} WWDG_TypeDef; - -/******************************************************************************/ -/* Ȧs줸wq */ -/******************************************************************************/ - -/* #pragma anon_unions */ - -/****************** Bit definition for WWDG_CR register ************************/ - -#define WWDG_CR_WDGA_POS 7U -#define WWDG_CR_WDGA_MSK BIT(WWDG_CR_WDGA_POS) - -#define WWDG_CR_T_POSS 0U -#define WWDG_CR_T_POSE 6U -#define WWDG_CR_T_MSK BITS(WWDG_CR_T_POSS,WWDG_CR_T_POSE) - -/****************** Bit definition for WWDG_CFR register ************************/ - -#define WWDG_CFR_WDGTB_POS 7U -#define WWDG_CFR_WDGTB_MSK BIT(WWDG_CFR_WDGTB_POS) - -#define WWDG_CFR_W_POSS 0U -#define WWDG_CFR_W_POSE 6U -#define WWDG_CFR_W_MSK BITS(WWDG_CFR_W_POSS,WWDG_CFR_W_POSE) - -/****************** Bit definition for WWDG_IER register ************************/ - -#define WWDG_IER_EWIS_POS 7U -#define WWDG_IER_EWIS_MSK BIT(WWDG_IER_EWIS_POS) - -/****************** Bit definition for WWDG_IDR register ************************/ - -#define WWDG_IDR_EWIS_POS 7U -#define WWDG_IDR_EWIS_MSK BIT(WWDG_IER_EWIS_POS) - -/****************** Bit definition for WWDG_IVS register ************************/ - -#define WWDG_IVS_EWIS_POS 7U -#define WWDG_IVS_EWIS_MSK BIT(WWDG_IER_EWIS_POS) - -/****************** Bit definition for WWDG_RIF register ************************/ - -#define WWDG_RIF_EWIS_POS 7U -#define WWDG_RIF_EWIS_MSK BIT(WWDG_IER_EWIS_POS) - -/****************** Bit definition for WWDG_IFM register ************************/ - -#define WWDG_IFM_EWIS_POS 7U -#define WWDG_IFM_EWIS_MSK BIT(WWDG_IER_EWIS_POS) - -/****************** Bit definition for WWDG_ICR register ************************/ - -#define WWDG_ICR_EWIS_POS 7U -#define WWDG_ICR_EWIS_MSK BIT(WWDG_IER_EWIS_POS) - - -#else -/* */ -#endif diff --git a/bsp/essemi/es32f0271/libraries/CMSIS/Device/EastSoft/ES32F0271/Include/ES32F0271/reg_wwdt.h b/bsp/essemi/es32f0271/libraries/CMSIS/Device/EastSoft/ES32F0271/Include/ES32F0271/reg_wwdt.h deleted file mode 100644 index b1ee6dcf18..0000000000 --- a/bsp/essemi/es32f0271/libraries/CMSIS/Device/EastSoft/ES32F0271/Include/ES32F0271/reg_wwdt.h +++ /dev/null @@ -1,92 +0,0 @@ -/** - ************************************************************************************** - * @file REG_WWDT.h - * @brief WWDT Head File - * - * @version V0.01 - * @date 4/12/2018 - * @author Eastsoft MCU Software Team - * @note - * - * Copyright (C) 2018 Shanghai Eastsoft Microelectronics Co., Ltd. ALL rights reserved. - * - ************************************************************************************** - */ - -#ifndef __REG_WWDT_H__ -#define __REG_WWDT_H__ - - -/******************************************************************************/ -/* 设备特殊寄存器结构定义 */ -/******************************************************************************/ - -/* 允许匿名结构和匿名联合 */ -/* #pragma anon_unions */ - -/****************** Bit definition for WWDT_CON register ************************/ - -#define WWDT_CON_WDGA_POS 7U -#define WWDT_CON_WDGA_MSK BIT(WWDT_CON_WDGA_POS) - -#define WWDT_CON_T_POSS 0U -#define WWDT_CON_T_POSE 6U -#define WWDT_CON_T_MSK BITS(WWDT_CON_T_POSS,WWDT_CON_T_POSE) - -/****************** Bit definition for WWDT_CFG register ************************/ - -#define WWDT_CFG_WDGTB_POSS 7U -#define WWDT_CFG_WDGTB_POSE 8U -#define WWDT_CFG_WDGTB_MSK BITS(WWDT_CFG_WDGTB_POSS,WWDT_CFG_WDGTB_POSE) - -#define WWDT_CFG_W_POSS 0U -#define WWDT_CFG_W_POSE 6U -#define WWDT_CFG_W_MSK BITS(WWDT_CFG_W_POSS,WWDT_CFG_W_POSE) - -/****************** Bit definition for WWDT_IER register ************************/ - -#define WWDT_IER_EWIS_POS 0U -#define WWDT_IER_EWIS_MSK BIT(WWDT_IER_EWIS_POS) - -/****************** Bit definition for WWDT_IDR register ************************/ - -#define WWDT_IDR_EWIS_POS 0U -#define WWDT_IDR_EWIS_MSK BIT(WWDT_IDR_EWIS_POS) - -/****************** Bit definition for WWDT_IVS register ************************/ - -#define WWDT_IVS_EWIS_POS 0U -#define WWDT_IVS_EWIS_MSK BIT(WWDT_IVS_EWIS_POS) - -/****************** Bit definition for WWDT_RIF register ************************/ - -#define WWDT_RIF_EWIF_POS 0U -#define WWDT_RIF_EWIF_MSK BIT(WWDT_RIF_EWIF_POS) - -/****************** Bit definition for WWDT_IFM register ************************/ - -#define WWDT_IFM_EWIM_POS 0U -#define WWDT_IFM_EWIM_MSK BIT(WWDT_IFM_EWIM_POS) - -/****************** Bit definition for WWDT_ICR register ************************/ - -#define WWDT_ICR_EWIC_POS 0U -#define WWDT_ICR_EWIC_MSK BIT(WWDT_ICR_EWIC_POS) - -typedef struct -{ - __IO uint32_t CON; - __IO uint32_t CFG; - __O uint32_t IER; - __O uint32_t IDR; - __I uint32_t IVS; - __I uint32_t RIF; - __I uint32_t IFM; - __O uint32_t ICR; -} WWDT_TypeDef; - - - - - -#endif diff --git a/bsp/essemi/es32f0271/libraries/CMSIS/Device/EastSoft/ES32F0271/Include/es32f0271.h b/bsp/essemi/es32f0271/libraries/CMSIS/Device/EastSoft/ES32F0271/Include/es32f0271.h deleted file mode 100644 index 2810051370..0000000000 --- a/bsp/essemi/es32f0271/libraries/CMSIS/Device/EastSoft/ES32F0271/Include/es32f0271.h +++ /dev/null @@ -1,389 +0,0 @@ -/******************************************************************* -* *file : ES32F0271_sub.h -* *description: ES32F0271 Device Head File -* *author : Eastsoft AE Team -* *version : V1.00.01 -* *data : 4/10/2018 -* -* *Copyright (C) 2018 Shanghai Eastsoft Microelectronics Co., Ltd. -*******************************************************************/ - -/** @addtogroup CMSIS - * @{ - */ - -/** @addtogroup ES32F0271_SUB1 - * @{ - */ - -#ifndef __ES32F0271_SUB_H__ -#define __ES32F0271_SUB_H__ - -#ifdef __cplusplus -extern "C"{ -#endif - -/** - * @brief defines 'read only' 、'write only'、 'read / write' permissions. - */ -#define __I volatile const /* defines 'read only' permissions */ -#define __O volatile /* defines 'write only' permissions */ -#define __IO volatile /* defines 'read / write' permissions */ - -/** @addtogroup Configuration_section_for_CMSIS - * @{ - */ -/** - * @brief configuration of the cortex-M3 processor and core peripherals. - */ - -#define __MPU_PRESENT 0 /*!< cm0ikmcu does not provide a MPU present or not */ -#define __NVIC_PRIO_BITS 2 /*!< cm0ikmcu Supports 2 Bits for the Priority Levels */ -#define __Vendor_SysTickConfig 0 /*!< Set to 1 if different SysTick Config is used */ -/** - * @} - */ - -/** @addtogroup peripherals_interrupt_number_definition - * @{ - */ - -typedef enum IRQn -{ - - /****** ES32 Processor Exceptions Numbers ******************************************************/ - - /*************** Cortex-M0 Processor Exceptions Numbers **************************/ - NonMaskableInt_IRQn = -14, /*!< 2 Non Maskable Interrupt */ - HardFault_IRQn = -13, /*!< 3 Cortex-M0 Hard Fault Interrupt */ - SVCall_IRQn = -5, /*!< 11 Cortex-M0 SV Call Interrupt */ - PendSV_IRQn = -2, /*!< 14 Cortex-M0 Pend SV Interrupt */ - SysTick_IRQn = -1, /*!< 15 Cortex-M0 System Tick Interrupt */ - - /**************** ES32F0271_SUB specific Exceptions Numbers **************************/ - WWDT_IRQn = 0, /* 0 | WWDT Interrupt */ - PVD_IRQn = 1, /* 1 | PVD Interrupt EXTI[20] */ - RTC_IRQn = 2, /* 2 | RTC Interrupt */ - WAKEUP_IRQn = 3, /* 3 | WAKEUP Interrupt EXTI[21] */ - CM0IKMCU_IRQ04_IRQn = 4, /* 4 | Interrupt */ - EXTI_0to1_IRQn = 5, /* 5 | EXTI[1:0] Interrupt GPIOx[1:0] */ - EXTI_2to3_IRQn = 6, /* 6 | EXTI[3:2] Interrupt GPIOx[3:2] */ - EXTI_4to15_IRQn = 7, /* 7 | EXTI[15:4] Interrupt GPIOx[15:4] */ - CM0IKMCU_IRQ08_IRQn = 8, /* 8 | Interrupt */ - DMA1_CH0_IRQn = 9, /* 9 | DMA1_CH0 Interrupt */ - DMA1_CH12_IRQn = 10, /* 10 | DMA1_CH12 Interrupt */ - DMA1_CH345_IRQn = 11, /* 11 | DMA1_CH345 Interrupt */ - ADC_CMP_IRQn = 12, /* 12 | ADC/COMP0-3 Interrupt EXTI[19:16]) */ - AD16C4T1_IRQn = 13, /* 13 | AD16C4T1 Interrupt */ - BS16T1_IRQn = 14, /* 14 | BS16T1 Interrupt */ - GP32C4T1_IRQn = 15, /* 15 | GP32C4T1 Interrupt */ - GP16C4T1_IRQn = 16, /* 16 | GP16C4T1 Interrupt */ - GP16C4T2_IRQn = 17, /* 17 | GP16C4T2 Interrupt */ - GP16C4T3_IRQn = 18, /* 18 | GP16C4T3 Interrupt */ - GP16C2T1_IRQn = 19, /* 19 | GP16C2T1 Interrupt */ - GP16C2T2_IRQn = 20, /* 20 | GP16C2T2 Interrupt */ - GP16C2T3_IRQn = 21, /* 21 | GP16C2T3 Interrupt */ - GP16C2T4_IRQn = 22, /* 22 | GP16C2T4 Interrupt */ - I2C1_IRQn = 23, /* 23 | I2C1 Interrupt */ - I2C2_IRQn = 24, /* 24 | I2C2 Interrupt */ - SPI1_IRQn = 25, /* 25 | SPI1 Interrupt */ - SPI2_IRQn = 26, /* 26 | SPI2 Interrupt */ - UART1_IRQn = 27, /* 27 | UART1 Interrupt */ - UART2_IRQn = 28, /* 28 | UART2 Interrupt */ - UART3_IRQn = 29, /* 29 | UART3 Interrupt */ - SUART12_IRQn = 30, /* 30 | SUART1/2 Interrupt */ - USB_IRQn = 31 /* 31 | USB Interrupt */ -} IRQn_Type; - -/** - * @} - */ - -/* Includes-------------------------------------------------------------------------------*/ - -#include "core_cm0.h" -#include -#include -#include "system_es32f027x.h" -/** - * @brief these files declare Peripheral register bit_definition. - */ -#include "reg_rcu.h" -#include "reg_syscfg.h" -#include "reg_fc.h" -#include "reg_dma.h" -#include "reg_gpio.h" -#include "reg_i2c.h" -#include "reg_uart.h" -#include "reg_adc.h" -#include "reg_cmp.h" -#include "reg_dac.h" -#include "reg_spi.h" -#include "reg_crc.h" -#include "reg_ad16c4t.h" -#include "reg_hdiv.h" -#include "reg_aes.h" -#include "reg_wwdt.h" -#include "reg_rtc.h" -#include "reg_mswd.h" -#include "reg_mcm.h" -#include "reg_exti.h" -#include "reg_usb.h" - -/******************************************************************************/ -/* Peripheral register */ -/******************************************************************************/ - -/* allow anonymous structures and anonymous enumeration */ -/* #pragma anon_unions */ - -/******************************************************************************/ -/* Peripheral memory map */ -/******************************************************************************/ - -/********************* Base addresses *************************/ -#define FLASH_BASE (0x08000000UL) -#define FLASH_INFO_BASE (0x1FFFE000UL) /* EFLASH Info ( 6K Bytes) - Boot Loader Memory */ -#define SRAM_BASE (0x20000000UL) -#define APB1_BASE (0x40000000UL) -#define APB2_BASE (0x40010000UL) -#define AHB1_BASE (0x40020000UL) -#define AHB2_BASE (0x48000000UL) -#define CM0IN_BASE (0xE0000000UL) - -/* Cortex簧-M0 internal Peripherals - CM0IN_BASE: 0xE0000000*/ -#define TICK_BASE (CM0IN_BASE + 0xE010) - -#define SRAM1_BASE (SRAM_BASE + 0x0000) // SRAM1 Memory ( 4K Bytes) -#define SRAM2_BASE (SRAM_BASE + 0x1000) // SRAM2 Memory ( 4K Bytes) for Rev.B -#define STACK_SIZE 0x00000400>>2 // Stack size (in Words) -#define SRAMTOP 0x1000//0x2000 // Jackey 2018.9.5 - -/***************** peripherals base addresses ********************/ -/* APB1 */ -#define GP32C4T1_BASE (APB1_BASE + 0x0000) -#define GP16C4T1_BASE (APB1_BASE + 0x0400) -#define GP16C4T2_BASE (APB1_BASE + 0x0800) -#define GP16C4T3_BASE (APB1_BASE + 0x0C00) -#define BS16T1_BASE (APB1_BASE + 0x1000) -#define WWDT_BASE (APB1_BASE + 0x2C00) -#define IWDT_BASE (APB1_BASE + 0x3000) -#define SPI2_BASE (APB1_BASE + 0x3800) -#define UART2_BASE (APB1_BASE + 0x4400) -#define UART3_BASE (APB1_BASE + 0x4800) -#define SUART1_BASE (APB1_BASE + 0x4C00) -#define SUART2_BASE (APB1_BASE + 0x5000) -#define I2C1_BASE (APB1_BASE + 0x5400) -#define I2C2_BASE (APB1_BASE + 0x5800) -#define DAC_BASE (APB1_BASE + 0x5C00) -#define PWR_BASE (APB1_BASE + 0x7000) -/* APB2 */ -#define EXTI_BASE (APB2_BASE + 0x0400) -#define ADC_BASE (APB2_BASE + 0x2400) -#define AD16C4T1_BASE (APB2_BASE + 0x2C00) -#define SPI1_BASE (APB2_BASE + 0x3000) -#define UART1_BASE (APB2_BASE + 0x3800) -#define GP16C2T1_BASE (APB2_BASE + 0x4000) -#define GP16C2T2_BASE (APB2_BASE + 0x4400) -#define GP16C2T3_BASE (APB2_BASE + 0x4800) -#define GP16C2T4_BASE (APB2_BASE + 0x4C00) -#define MCM_BASE (APB2_BASE + 0x5400) -#define DBGMCU_BASE (APB2_BASE + 0x5800) -#define COMP_BASE (APB2_BASE + 0x5C00) -/* AHB1 */ -#define DMA1_BASE (AHB1_BASE + 0x0000) -#define RCU_BASE (AHB1_BASE + 0x1000) -#define SYSCFG_BASE (AHB1_BASE + 0x1400) -#define RTC_BASE (AHB1_BASE + 0x1800) -#define EFLASH_BASE (AHB1_BASE + 0x2000) -#define MSWD_BASE (AHB1_BASE + 0x2C00) -#define CRC_BASE (AHB1_BASE + 0x3000) -#define AES_BASE (AHB1_BASE + 0x3400) -#define USB_BASE (AHB1_BASE + 0x3800) -#define HDIV_BASE (AHB1_BASE + 0x3C00) -/* AHB2 */ -#define GPIOA_BASE (AHB2_BASE + 0x0000) -#define GPIOB_BASE (AHB2_BASE + 0x0400) -#define GPIOC_BASE (AHB2_BASE + 0x0800) -#define GPIOD_BASE (AHB2_BASE + 0x0C00) -#define GPIOE_BASE (AHB2_BASE + 0x1000) -#define GPIOF_BASE (AHB2_BASE + 0x1400) - -/********************* Peripheral declaration *************************/ -#define TICK (( TICK_TypeDef *) TICK_BASE) -#define GPIOA (( GPIO_TypeDef *) GPIOA_BASE) -#define GPIOB (( GPIO_TypeDef *) GPIOB_BASE) -#define GPIOC (( GPIO_TypeDef *) GPIOC_BASE) -#define GPIOD (( GPIO_TypeDef *) GPIOD_BASE) -#define DMA1 (( DMA_TypeDef *) DMA1_BASE) -#define RCU (( RCU_TypeDef *) RCU_BASE) -#define SYSCFG (( SYSCFG_TypeDef *) SYSCFG_BASE) -#define FC (( FC_TypeDef *) EFLASH_BASE) -#define CRC (( CRC_TypeDef *) CRC_BASE) -#define AES (( AES_TypeDef *) AES_BASE) -#define HDIV (( HDIV_TypeDef *) HDIV_BASE) -#define MSWD (( MSWD_TypeDef *) MSWD_BASE) -#define USB (( USBCTRL_TypeDef *) USB_BASE) -#define USBH (( USBCTRL_TypeDef *) USB_BASE) -#define USBD (( USBCTRL_TypeDef *) USB_BASE) -#define IWDT (( IWDT_TypeDef *) IWDT_BASE) -#define WWDT (( WWDT_TypeDef *) WWDT_BASE) -#define ADC (( ADC_TypeDef *) ADC_BASE) -#define AD16C4T1 (( AD16C4T_TypeDef *) AD16C4T1_BASE) -#define GP32C4T1 (( AD16C4T_TypeDef *) GP32C4T1_BASE) -#define GP16C4T1 (( AD16C4T_TypeDef *) GP16C4T1_BASE) -#define GP16C4T2 (( AD16C4T_TypeDef *) GP16C4T2_BASE) -#define GP16C4T3 (( AD16C4T_TypeDef *) GP16C4T3_BASE) -#define GP16C2T1 (( AD16C4T_TypeDef *) GP16C2T1_BASE) -#define GP16C2T2 (( AD16C4T_TypeDef *) GP16C2T2_BASE) -#define GP16C2T3 (( AD16C4T_TypeDef *) GP16C2T3_BASE) -#define GP16C2T4 (( AD16C4T_TypeDef *) GP16C2T4_BASE) -#define BS16T1 (( AD16C4T_TypeDef *) BS16T1_BASE) -#define SPI1 (( SPI_TypeDef *) SPI1_BASE) -#define SPI2 (( SPI_TypeDef *) SPI2_BASE) -#define I2C1 (( I2C_TypeDef *) I2C1_BASE) -#define I2C2 (( I2C_TypeDef *) I2C2_BASE) -#define DAC (( DAC_TypeDef *) DAC_BASE) -#define CMP (( CMP_TypeDef *) COMP_BASE) -#define UART1 (( UART_TypeDef *) UART1_BASE) -#define UART2 (( UART_TypeDef *) UART2_BASE) -#define UART3 (( UART_TypeDef *) UART3_BASE) -#define SUART1 (( UART_TypeDef *) SUART1_BASE) -#define SUART2 (( UART_TypeDef *) SUART2_BASE) -#define EXTI (( EXTI_TypeDef *) EXTI_BASE) -#define RTC (( RTC_TypeDef *) RTC_BASE) -#define MCM (( MCM_TypeDef *) MCM_BASE) -/* Special stuff */ -#define MSG_INCR ( __IO uint8_t *) (DBGMCU_BASE + 0x50) -#define MSG_WR ( __IO uint32_t *) (DBGMCU_BASE + 0x54) -#define MSG_END ( __IO uint32_t *) (DBGMCU_BASE + 0x58) -#define MSG_INCR_S ( __IO uint32_t *) (DBGMCU_BASE + 0x5C) -#define MSG_INCR_X ( __IO uint32_t *) (DBGMCU_BASE + 0x60) -#define MSG_INCR_B ( __IO uint32_t *) (DBGMCU_BASE + 0x64) -#define MSG_PTR ( __IO uint8_t **) (DBGMCU_BASE + 0x68) -#define MSG_INCR_D ( __IO uint32_t *) (DBGMCU_BASE + 0x78) -#define INCR_ERR_CNT ( __IO uint32_t *) (DBGMCU_BASE + 0x6C) - -#define END_SIM *MSG_END -#define SIM_FAIL 0xFFFFAAAA -#define SIM_PASS 0xFFFF5555 -/******************************************************************************/ -/* macros */ -/******************************************************************************/ - -/** @addtogroup Public_macros - * @{ - */ -#if defined (__CC_ARM) -#define __INLINE__ __inline -#else -#define __INLINE__ inline -#endif - -#define __isr__ - -#define UNUSED(x) ((void)(x)) - -#ifdef USE_ASSERT -#define assert_param(x) \ -do \ -{ \ - if (!(x)) \ - { \ - __disable_irq(); \ - while (1) \ - ; \ - } \ -} while (0) -#else -#define assert_param(x) -#endif - -#define BIT(x) ((uint32_t)((uint32_t)0x01U<<(x))) - -#define BITS(start, end) ((0xFFFFFFFFUL << (start)) &\ - (0xFFFFFFFFUL >> (31U - (uint32_t)(end)))) - -#define SET_BIT(REG, SETMASK) ((REG) |= (SETMASK)) - -#define CLEAR_BIT(REG, SETMASK) ((REG) &= ~(SETMASK)) - -#define READ_BIT(REG, SETMASK) ((REG) & (SETMASK)) - -#define CLEAR_REG(REG) ((REG) = (0x0)) - -#define WRITE_REG(REG, VAL) ((REG) = (VAL)) - -#define READ_REG(REG) ((REG)) - -#define MODIFY_REG(REG, CLEARMASK, SETMASK) WRITE_REG((REG), (((READ_REG(REG)) & (~(CLEARMASK))) | (SETMASK))) - -#define POSITION_VAL(VAL) (__CLZ(__RBIT(VAL))) - -/** - * @} - */ - -/******************************************************************************/ -/* types */ -/******************************************************************************/ -/** @addtogroup Public_types - * @{ - */ -typedef enum -{ - DISABLE = 0, - ENABLE = !DISABLE -} TypeFunc,FuncState; -#define IS_FUNC_STATE(x) (((x) == DISABLE) || ((x) == ENABLE)) - -typedef enum -{ - RESET = 0, - SET = !RESET -} FlagStatus, ITStatus, PinStatus; - -typedef enum -{ - ERROR = 0, - SUCCESS = !ERROR -} ErrorStatus; - -typedef enum -{ - BIT_RESET = 0x0, - BIT_SET = 0x1, -} BitStatus; - -typedef enum -{ - FALSE = 0x0, - TRUE = 0x1, -} TypeBool; - -typedef enum -{ - UNLOCK = 0x0, - LOCK = 0x1, -} LockState; -#define IS_LOCK_STATE(x) (((x) == UNLOCK) || ((x) == LOCK)) - -/** - * @} Public_types - */ - -#ifdef __cplusplus -} -#endif - -#endif - -/** - * @} ES32F0271_SUB - */ - -/** - * @} CMSIS - */ - -/************* (C) COPYRIGHT Eastsoft Microelectronics *****END OF FILE****/ diff --git a/bsp/essemi/es32f0271/libraries/CMSIS/Device/EastSoft/ES32F0271/Include/rt_misc.h b/bsp/essemi/es32f0271/libraries/CMSIS/Device/EastSoft/ES32F0271/Include/rt_misc.h deleted file mode 100644 index 71a3270c6e..0000000000 --- a/bsp/essemi/es32f0271/libraries/CMSIS/Device/EastSoft/ES32F0271/Include/rt_misc.h +++ /dev/null @@ -1,183 +0,0 @@ -/* rt_misc.h: definitions for miscellaneous retargetable functions - * - * Copyright 1999,2013-2014 ARM Limited. All rights reserved. - * - * RCS $Revision$ - * Checkin $Date$ - * Revising $Author$ - */ - -#ifndef __RT_MISC_H -#define __RT_MISC_H -#define __ARMCLIB_VERSION 5060019 - -#ifdef __cplusplus -extern "C" { -#endif - -#include -#include - -/* - * This will be called during startup if it's defined, in order to - * allow a user reimplementation of getenv() to initialise itself. - */ -extern void _getenv_init(void); - -/* - * This will be called during startup if it's defined, in order to - * allow a user reimplementation of clock() to initialise itself. - */ -extern void _clock_init(void); - -/* - * This must return a pointer to __USER_LIBSPACE_SIZE bytes of - * zero-initialised space, used to store vital static data such as - * errno, the heap state, and the FP status word. - */ -#define __USER_LIBSPACE_SIZE 96 -extern void *__user_libspace(void); - -/* - * This is the library init function itself, provided just in case - * a user needs to call it directly. It is called just after - * __rt_stackheap_init(), and passed an initial chunk of memory to - * use as a heap. It returns argc and argv ready to be passed to - * main(). (The __argc_argv structure contains four words rather - * than just two, in case you need to pass anything else to main() - * such as the Unix envp. For AArch64 struct __argc_argv is 8 words - * (4 registers) and explicit padding is used to ensure argc is in w0.) - */ -struct __argc_argv { -#if (defined(__ARM_64BIT_STATE) || defined(__TARGET_ARCH_AARCH64)) && \ - (defined(__ARM_BIG_ENDIAN) || defined(__BIG_ENDIAN)) - int padding; -#endif - int argc; -#if (defined(__ARM_64BIT_STATE) || defined(__TARGET_ARCH_AARCH64)) && \ - !(defined(__ARM_BIG_ENDIAN) || defined(__BIG_ENDIAN)) - int padding; -#endif - char **argv; - void *r2; - void *r3; -}; -extern __value_in_regs struct __argc_argv -__rt_lib_init(unsigned /*heapbase*/, unsigned /*heaptop*/); - -/* - * This function is responsible for constructing argc and argv to - * be passed to main(). Normally it works by calling - * _sys_command_string() and then splitting up the returned command - * line. If you define main() without arguments, the compiler also - * defines an empty version of this function to save time. In - * special circumstances, you might need to redefine this function - * explicitly yourself. - */ -__value_in_regs struct __argc_argv __ARM_get_argv(void */*internal use only*/); - -/* - * This is the library shutdown function, analogous to - * __rt_lib_init(). - */ -extern void __rt_lib_shutdown(void); - -/* - * The medium-level exit function. exit() calls atexit()-registered - * functions and shuts down the library; _sys_exit() does neither - * of those things; __rt_exit() shuts down the library but doesn't - * call atexit() functions. - */ -extern void __rt_exit(int /*returncode*/); /* never returns */ - -/* - * This can be defined to override the standard memory models' way - * of determining where to put the initial stack and heap. - * - * The input parameters R0 and R2 contain nothing useful. The input - * parameters SP and SL are the values that were in SP and SL when - * the program began execution (so you can return them if you want - * to keep that stack). - * - * The two `limit' fields in the return structure are ignored if - * you are using the one-region memory model: the memory region is - * taken to be all the space between heap_base and stack_base. - */ -struct __initial_stackheap { - unsigned heap_base; /* low-address end of initial heap */ - unsigned stack_base; /* high-address end of initial stack */ - unsigned heap_limit; /* high-address end of initial heap */ - unsigned stack_limit; /* low-address end of initial stack */ -}; -extern __value_in_regs struct __initial_stackheap -__user_initial_stackheap(unsigned /*R0*/, unsigned /*SP*/, - unsigned /*R2*/, unsigned /*SL*/); - -/* - * This can be defined to give bounds on the address space the heap - * will ever use. - */ -struct __heap_extent { - uintptr_t base; - size_t range; -}; -extern __value_in_regs struct __heap_extent -__user_heap_extent(uintptr_t /*ignore*/, size_t /*ignore*/); - -/* - * This can be defined to specify how much spare stack is needed - * below SL in addition to the 256 bytes required by ATPCS: - * `always' gives the number of bytes of extra stack required at - * all instants (so that an interrupt handler has space to run in, - * for example), while `cleanup' gives the number of bytes of extra - * stack required to be available after a stack overflow has - * occurred, so that the stack overflow routine (e.g. SIGSTAK - * handler) has room to tidy up. - */ -struct __stack_slop { - unsigned always, cleanup; -}; -extern __value_in_regs struct __stack_slop -__user_stack_slop(unsigned /*ignore*/, unsigned /*ignore*/); - -/* - * This can be defined to return extra blocks of memory, separate - * from the initial one, to be used by the heap. It should place a - * pointer to a block of at least the requested size in `*base', - * and return the size of the block. It should return 0 if no such - * block can be returned, in which case the value stored at `*base' - * is never used. - */ -extern size_t __user_heap_extend(int /*ignore*/, - void ** /*base*/, - size_t /*requestedsize*/); - -/* - * Redefine this to completely override the C handling of signals - * (bypassing the signal() mechanism). Return values are 0 to - * continue execution, or a non-zero value to cause an exit with - * that return code. - */ -int __raise(int /*sig*/, intptr_t /*type*/); - -/* - * Redefine this to change the default handling of signals. The - * interface is the same as __raise(), but this function will only - * get called after the C signal handling mechanism has declined to - * process the signal. - */ -int __default_signal_handler(int /*sig*/, intptr_t /*type*/); - -/* - * Redefine this to replace the library's entire signal handling - * mechanism in the most efficient possible way. The default - * implementation of this is what calls __raise (above). - */ -void __rt_raise(int /*sig*/, intptr_t /*type*/); - -#ifdef __cplusplus -} -#endif - -#endif - diff --git a/bsp/essemi/es32f0271/libraries/CMSIS/Device/EastSoft/ES32F0271/ReleaseNote.html b/bsp/essemi/es32f0271/libraries/CMSIS/Device/EastSoft/ES32F0271/ReleaseNote.html deleted file mode 100644 index dce80ba62c..0000000000 --- a/bsp/essemi/es32f0271/libraries/CMSIS/Device/EastSoft/ES32F0271/ReleaseNote.html +++ /dev/null @@ -1,16 +0,0 @@ - - - - -ReleaseNote -

ES32F0271 Device Release Note

-

V1.00 2019-1-4

-

初版发布

-

V1.03 2019-09-23

-
    -
  1. Drivers\CMSIS\Device\EastSoft\ES32F0271\Startup\iar\ : 增加startup_es32f027x.s
    2. - -
-

 

- - \ No newline at end of file diff --git a/bsp/essemi/es32f0271/libraries/CMSIS/Device/EastSoft/ES32F0271/Startup/iar/startup_es32f027x.s b/bsp/essemi/es32f0271/libraries/CMSIS/Device/EastSoft/ES32F0271/Startup/iar/startup_es32f027x.s deleted file mode 100644 index bda1ad6ecd..0000000000 --- a/bsp/essemi/es32f0271/libraries/CMSIS/Device/EastSoft/ES32F0271/Startup/iar/startup_es32f027x.s +++ /dev/null @@ -1,256 +0,0 @@ -;******************************************************************************* -; file : startup_ES32f027x.s -; description: ES32F027x Device Startup File -; author : Eastsoft MCU Software Team -; data : 10 Dec 2018 -; Copyright (C) Shanghai Eastsoft Microelectronics Co. Ltd. All rights reserved. -;******************************************************************************* - - MODULE ?cstartup - - ;; Forward declaration of sections. - SECTION CSTACK:DATA:NOROOT(3) - SECTION .intvec:CODE:NOROOT(2) - - EXTERN __iar_program_start - PUBLIC __vector_table - - DATA -__vector_table - DCD sfe(CSTACK) ;0, load top of stack - DCD Reset_Handler ;1, reset handler - DCD NMI_Handler ;2, nmi handler - DCD HardFault_Handler ;3, hard fault handler - DCD 0 ;4, MPU Fault Handler - DCD 0 ;5, Bus Fault Handler - DCD 0 ;6, Usage Fault Handler - DCD 0 ;7, Reserved - DCD 0 ;8, Reserved - DCD 0 ;9, Reserved - DCD 0 ;10, Reserved - DCD SVC_Handler ;11, svcall handler - DCD 0 ;12, Reserved - DCD 0 ;13, Reserved - DCD PENDSV_Handler ;14, PENDSV Handler - DCD SYSTICK_Handler ;15, SYSTICK Handler - DCD WWDT_IRQHandler ;16, WWDT IRQHandler - DCD PVD_IRQHandler ;17, PVD IRQHandler - DCD RTC_IRQHandler ;18, RTC IRQHandler - DCD LowPowerWakeup_IRQHandler ;19, LowPowerWakeup IRQHandler - DCD 0 ;20, Reserved - DCD EXTI0_1_IRQHandler ;21, EXTI01_1 IRQHandler - DCD EXTI2_3_IRQHandler ;22, EXTI2_3 IRQHandler - DCD EXTI4_15_IRQHandler ;23, EXTI4_15 IRQHandler - DCD 0 ;24, Reserved - DCD DMA1_CH0_IRQHandler ;25, DMA1_CH1 IRQHandler - DCD DMA1_CH1_2_IRQHandler ;26, DMA1_CH2_3 IRQHandler - DCD DMA1_CH3_5_IRQHandler ;27, DMA1_CH4_7 IRQHandler - DCD ADC_CMP_IRQHandler ;28, ADC_CMP IRQHandler - DCD AD16C4T1_IRQHandler ;29, AD16C4T1 IRQHandler - DCD BS16T1_IRQHandler ;30, BS16T1 IRQHandler - DCD GP32C4T1_IRQHandler ;31, GP32C4T1 IRQHandler - DCD GP16C4T1_IRQHandler ;32, GP16C4T1 IRQHandler - DCD GP16C4T2_IRQHandler ;33, GP16C4T2 IRQHandler - DCD GP16C4T3_IRQHandler ;34, GP16C4T3 IRQHandler - DCD GP16C2T1_IRQHandler ;35, GP16C2T1 IRQHandler - DCD GP16C2T2_IRQHandler ;36, GP16C2T2 IRQHandler - DCD GP16C2T3_IRQHandler ;37, GP16C2T3 IRQHandler - DCD GP16C2T4_IRQHandler ;38, GP16C2T4 IRQHandler - DCD I2C1_IRQHandler ;39, I2C1 IRQHandler - DCD I2C2_IRQHandler ;40, I2C2 IRQHandler - DCD SPI1_IRQHandler ;41, SPI1 IRQHandler - DCD SPI2_IRQHandler ;42, SPI2 IRQHandler - DCD UART1_IRQHandler ;43, UART1 IRQHandler - DCD UART2_IRQHandler ;44, UART2 IRQHandler - DCD UART3_AES_IRQHandler ;45, UART3_AES IRQHandler - DCD SUART1_SUART2_IRQHandler ;46, SUART1_SUART2 IRQHandler - DCD USB_IRQHandler ;47, USB IRQHandler - -;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; -;; -;; Default interrupt handlers. -;; - THUMB - - PUBWEAK Reset_Handler - SECTION .text:CODE:NOROOT:REORDER(2) -Reset_Handler - LDR R0, =__iar_program_start - BX R0 - - PUBWEAK NMI_Handler - SECTION .text:CODE:NOROOT:REORDER(1) -NMI_Handler - B NMI_Handler - - PUBWEAK HardFault_Handler - SECTION .text:CODE:NOROOT:REORDER(1) -HardFault_Handler - B HardFault_Handler - - PUBWEAK SVC_Handler - SECTION .text:CODE:NOROOT:REORDER(1) -SVC_Handler - B SVC_Handler - - PUBWEAK PENDSV_Handler - SECTION .text:CODE:NOROOT:REORDER(1) -PENDSV_Handler - B PENDSV_Handler - - PUBWEAK SYSTICK_Handler - SECTION .text:CODE:NOROOT:REORDER(1) -SYSTICK_Handler - B SYSTICK_Handler - - PUBWEAK WWDT_IRQHandler - SECTION .text:CODE:NOROOT:REORDER(1) -WWDT_IRQHandler - B WWDT_IRQHandler - - PUBWEAK PVD_IRQHandler - SECTION .text:CODE:NOROOT:REORDER(1) -PVD_IRQHandler - B PVD_IRQHandler - - PUBWEAK RTC_IRQHandler - SECTION .text:CODE:NOROOT:REORDER(1) -RTC_IRQHandler - B RTC_IRQHandler - - PUBWEAK LowPowerWakeup_IRQHandler - SECTION .text:CODE:NOROOT:REORDER(1) -LowPowerWakeup_IRQHandler - B LowPowerWakeup_IRQHandler - - PUBWEAK EXTI0_1_IRQHandler - SECTION .text:CODE:NOROOT:REORDER(1) -EXTI0_1_IRQHandler - B EXTI0_1_IRQHandler - - PUBWEAK EXTI2_3_IRQHandler - SECTION .text:CODE:NOROOT:REORDER(1) -EXTI2_3_IRQHandler - B EXTI2_3_IRQHandler - - PUBWEAK EXTI4_15_IRQHandler - SECTION .text:CODE:NOROOT:REORDER(1) -EXTI4_15_IRQHandler - B EXTI4_15_IRQHandler - - PUBWEAK DMA1_CH0_IRQHandler - SECTION .text:CODE:NOROOT:REORDER(1) -DMA1_CH0_IRQHandler - B DMA1_CH0_IRQHandler - - PUBWEAK DMA1_CH1_2_IRQHandler - SECTION .text:CODE:NOROOT:REORDER(1) -DMA1_CH1_2_IRQHandler - B DMA1_CH1_2_IRQHandler - - PUBWEAK DMA1_CH3_5_IRQHandler - SECTION .text:CODE:NOROOT:REORDER(1) -DMA1_CH3_5_IRQHandler - B DMA1_CH3_5_IRQHandler - - PUBWEAK ADC_CMP_IRQHandler - SECTION .text:CODE:NOROOT:REORDER(1) -ADC_CMP_IRQHandler - B ADC_CMP_IRQHandler - - PUBWEAK AD16C4T1_IRQHandler - SECTION .text:CODE:NOROOT:REORDER(1) -AD16C4T1_IRQHandler - B AD16C4T1_IRQHandler - - PUBWEAK BS16T1_IRQHandler - SECTION .text:CODE:NOROOT:REORDER(1) -BS16T1_IRQHandler - B BS16T1_IRQHandler - - PUBWEAK GP32C4T1_IRQHandler - SECTION .text:CODE:NOROOT:REORDER(1) -GP32C4T1_IRQHandler - B GP32C4T1_IRQHandler - - PUBWEAK GP16C4T1_IRQHandler - SECTION .text:CODE:NOROOT:REORDER(1) -GP16C4T1_IRQHandler - B GP16C4T1_IRQHandler - - PUBWEAK GP16C4T2_IRQHandler - SECTION .text:CODE:NOROOT:REORDER(1) -GP16C4T2_IRQHandler - B GP16C4T2_IRQHandler - - PUBWEAK GP16C4T3_IRQHandler - SECTION .text:CODE:NOROOT:REORDER(1) -GP16C4T3_IRQHandler - B GP16C4T3_IRQHandler - - PUBWEAK GP16C2T1_IRQHandler - SECTION .text:CODE:NOROOT:REORDER(1) -GP16C2T1_IRQHandler - B GP16C2T1_IRQHandler - - PUBWEAK GP16C2T2_IRQHandler - SECTION .text:CODE:NOROOT:REORDER(1) -GP16C2T2_IRQHandler - B GP16C2T2_IRQHandler - - PUBWEAK GP16C2T3_IRQHandler - SECTION .text:CODE:NOROOT:REORDER(1) -GP16C2T3_IRQHandler - B GP16C2T3_IRQHandler - - PUBWEAK GP16C2T4_IRQHandler - SECTION .text:CODE:NOROOT:REORDER(1) -GP16C2T4_IRQHandler - B GP16C2T4_IRQHandler - - PUBWEAK I2C1_IRQHandler - SECTION .text:CODE:NOROOT:REORDER(1) -I2C1_IRQHandler - B I2C1_IRQHandler - - PUBWEAK I2C2_IRQHandler - SECTION .text:CODE:NOROOT:REORDER(1) -I2C2_IRQHandler - B I2C2_IRQHandler - - PUBWEAK SPI1_IRQHandler - SECTION .text:CODE:NOROOT:REORDER(1) -SPI1_IRQHandler - B SPI1_IRQHandler - - PUBWEAK SPI2_IRQHandler - SECTION .text:CODE:NOROOT:REORDER(1) -SPI2_IRQHandler - B SPI2_IRQHandler - - PUBWEAK UART1_IRQHandler - SECTION .text:CODE:NOROOT:REORDER(1) -UART1_IRQHandler - B UART1_IRQHandler - - PUBWEAK UART2_IRQHandler - SECTION .text:CODE:NOROOT:REORDER(1) -UART2_IRQHandler - B UART2_IRQHandler - - PUBWEAK UART3_AES_IRQHandler - SECTION .text:CODE:NOROOT:REORDER(1) -UART3_AES_IRQHandler - B UART3_AES_IRQHandler - - PUBWEAK SUART1_SUART2_IRQHandler - SECTION .text:CODE:NOROOT:REORDER(1) -SUART1_SUART2_IRQHandler - B SUART1_SUART2_IRQHandler - - PUBWEAK USB_IRQHandler - SECTION .text:CODE:NOROOT:REORDER(1) -USB_IRQHandler - B USB_IRQHandler - - END diff --git a/bsp/essemi/es32f0271/libraries/CMSIS/Device/EastSoft/ES32F0271/Startup/keil/boot.c b/bsp/essemi/es32f0271/libraries/CMSIS/Device/EastSoft/ES32F0271/Startup/keil/boot.c deleted file mode 100644 index 4c4e15ee4c..0000000000 --- a/bsp/essemi/es32f0271/libraries/CMSIS/Device/EastSoft/ES32F0271/Startup/keil/boot.c +++ /dev/null @@ -1,321 +0,0 @@ - -// -// Boot (vectors) file for Cortex-M0 Integration Kit -// - -#include -#include -#include -#include "es32F0271_sub.h" - -// -// Build a stand-alone image -// - -#pragma import(__use_no_semihosting) - - -/*----------------------------------------------------------------------*/ -/*-------------- Interrupt Handlers --------------*/ -/*----------------------------------------------------------------------*/ -// The following functions are defined weakly to allow the user -// to override them at link time simply by declaring their own -// function of the same name. -// -// If no user function is provided, the weak function is used. -// -//------------------------------------ IRQ NMI Handler -__weak void NMI_Handler(void) -{ - while(1); -} -//------------------------------------ IRQ Hard Fault Handler -__weak void HardFault_Handler(void) -{ - //printf("Hard Fault\r\n"); - while(1); -} -//------------------------------------ IRQ SVCall Handler -__weak void SVC_Handler(void) -{ - while(1); -} -//------------------------------------ IRQ PendSV Handler -__weak void PendSV_Handler(void) -{ - while(1); -} -//------------------------------------ IRQ SysTick Handler -__weak void SysTick_Handler(void) -{ - while(1); -} -//------------------------------------ IRQ 31 -__weak void USB_IRQHandler(void) -{ - while(1); -} -//------------------------------------ IRQ 30 -__weak void SUART12_IRQHandler(void) -{ - while(1); -} -//------------------------------------ IRQ 29 -__weak void UART3_IRQHandler(void) -{ - while(1); -} -//------------------------------------ IRQ 28 -__weak void UART2_IRQHandler(void) -{ - while(1); -} -//------------------------------------ IRQ 27 -__weak void UART1_IRQHandler(void) -{ - while(1); -} -//------------------------------------ IRQ 26 -__weak void SPI2_IRQHandler(void) -{ - while(1); -} -//------------------------------------ IRQ 25 -__weak void SPI1_IRQHandler(void) -{ - while(1); -} -//------------------------------------ IRQ 24 -__weak void I2C2_IRQHandler(void) -{ - while(1); -} -//------------------------------------ IRQ 23 -__weak void I2C1_IRQHandler(void) -{ - while(1); -} -//------------------------------------ IRQ 22 -__weak void GPTIMC4_IRQHandler(void) -{ - while(1); -} -//------------------------------------ IRQ 21 -__weak void GPTIMC3_IRQHandler(void) -{ - while(1); -} -//------------------------------------ IRQ 20 -__weak void GPTIMC2_IRQHandler(void) -{ - while(1); -} -//------------------------------------ IRQ 19 -__weak void GPTIMC1_IRQHandler(void) -{ - while(1); -} -//------------------------------------ IRQ 18 -__weak void GPTIMB3_IRQHandler(void) -{ - while(1); -} -//------------------------------------ IRQ 17 -__weak void GPTIMB2_IRQHandler(void) -{ - while(1); -} -//------------------------------------ IRQ 16 -__weak void GPTIMB1_IRQHandler(void) -{ - while(1); -} -//------------------------------------ IRQ 15 -__weak void GPTIMA1_IRQHandler(void) -{ - while(1); -} -//------------------------------------ IRQ 14 -__weak void BSTIM1_IRQHandler(void) -{ - while(1); -} -//------------------------------------ IRQ 13 -__weak void ADTIM1_IRQHandler(void) -{ - while(1); -} -//------------------------------------ IRQ 12 -__weak void ADC_COMP_IRQHandler(void) -{ - // while(1); -} -//------------------------------------ IRQ 11 -__weak void DMA1_CH345_IRQHandler(void) -{ - while(1); -} -//------------------------------------ IRQ 10 -__weak void DMA1_CH12_IRQHandler(void) -{ - while(1); -} -//------------------------------------ IRQ 9 -__weak void DMA1_CH0_IRQHandler(void) -{ - while(1); -} -//------------------------------------ IRQ 8 -//------------------------------------ IRQ 7 -__weak void EXTI_4to15_IRQHandler(void) -{ - while(1); -} -//------------------------------------ IRQ 6 -__weak void EXTI_2to3_IRQHandler(void) -{ - while(1); -} -//------------------------------------ IRQ 5 -__weak void EXTI_0to1_IRQHandler(void) -{ - while(1); -} -//------------------------------------ IRQ 4 -//------------------------------------ IRQ 3 -__weak void WAKEUP_IRQHandler(void) -{ - while(1); -} -//------------------------------------ IRQ 2 -__weak void RTC_IRQHandler(void) -{ - while(1); -} -//------------------------------------ IRQ 1 -__weak void PVD_IRQHandler(void) -{ - while(1); -} -//------------------------------------ IRQ 0 -__weak void WWDT_IRQHandler(void) -{ - while(1); -} - - -/*----------------------------------------------------------------------*/ -/*-------------- Defined Handler --------------*/ -/*----------------------------------------------------------------------*/ -__weak void Default_IRQHandler(void) -{ - while(1); -} - -/*----------------------------------------------------------------------*/ -/*-------------- Symbols defined in linker script ---------*/ -/*----------------------------------------------------------------------*/ - -extern void __main(void); - -/*----------------------------------------------------------------------*/ -/*-------------- Reset Handler --------------*/ -/*----------------------------------------------------------------------*/ -void Reset_Handler(void) -{ - __main(); - while(1) {;} // In case main() fails -} - -/*----------------------------------------------------------------------*/ -/*-------------- Set up Vector Table --------------*/ -/*----------------------------------------------------------------------*/ -typedef void (*const vect_t)(void) __irq; - -vect_t __Vectors[] -__attribute__ ((section("vectors"))) = { - (vect_t)(SRAM1_BASE+SRAMTOP),//(vect_t)(0x20000F80), // Top of Stack - Allowing 4 words for DEBUGDRIVERDATA - (vect_t)Reset_Handler, // Reset Handler - (vect_t)NMI_Handler, // NMI Handler - (vect_t)HardFault_Handler,// Hard Fault Handler - 0, // Reserved - 0, // Reserved - 0, // Reserved - 0, // Reserved - 0, // Reserved - 0, // Reserved - 0, // Reserved - (vect_t)SVC_Handler, // SVCall Handler - 0, // Reserved - 0, // Reserved - (vect_t)PendSV_Handler, // PendSV Handler - (vect_t)SysTick_Handler, // SysTick Handler - /*----------External Exceptions---------------------------------------------*/ - // External Interrupts 0 - 31 - // These are essentially unused, so will all - // take the same default handler if invoked. - // External Interrupts - //|=========================================| - //| IRQ NO. | M621 | - //|-----------------------------------------| - (vect_t)WWDT_IRQHandler, //| 0 | WWDG | | - (vect_t)PVD_IRQHandler, //| 1 | PVD | EXTI[20] | - (vect_t)RTC_IRQHandler, //| 2 | RTC | | - (vect_t)WAKEUP_IRQHandler, //| 3 | WAKEUP | EXTI[21] | - (vect_t)Default_IRQHandler, //| 4 | | | - (vect_t)EXTI_0to1_IRQHandler, //| 5 | EXTI[1:0] | GPIOx[1:0] | - (vect_t)EXTI_2to3_IRQHandler, //| 6 | EXTI[3:2] | GPIOx[3:2] | - (vect_t)EXTI_4to15_IRQHandler, //| 7 | EXTI[15:4] | GPIOx[15:4] | - (vect_t)Default_IRQHandler, //| 8 | | | - (vect_t)DMA1_CH0_IRQHandler, //| 9 | DMA1_CH0 | | - (vect_t)DMA1_CH12_IRQHandler, //| 10 | DMA1_CH12 | | - (vect_t)DMA1_CH345_IRQHandler, //| 11 | DMA1_CH345 | | - (vect_t)ADC_COMP_IRQHandler, //| 12 | ADC/COMP0-3 | EXTI[19:16] | - (vect_t)ADTIM1_IRQHandler, //| 13 | ADTIM1 | | - (vect_t)BSTIM1_IRQHandler, //| 14 | BSTIM1 | | - (vect_t)GPTIMA1_IRQHandler, //| 15 | GPTIMA1 | | - (vect_t)GPTIMB1_IRQHandler, //| 16 | GPTIMB1 | | - (vect_t)GPTIMB2_IRQHandler, //| 17 | GPTIMB2 | | - (vect_t)GPTIMB3_IRQHandler, //| 18 | GPTIMB3 | | - (vect_t)GPTIMC1_IRQHandler, //| 19 | GPTIMC1 | | - (vect_t)GPTIMC2_IRQHandler, //| 20 | GPTIMC2 | | - (vect_t)GPTIMC3_IRQHandler, //| 21 | GPTIMC3 | | - (vect_t)GPTIMC4_IRQHandler, //| 22 | GPTIMC4 | | - (vect_t)I2C1_IRQHandler, //| 23 | I2C1 | | - (vect_t)I2C2_IRQHandler, //| 24 | I2C2 | | - (vect_t)SPI1_IRQHandler, //| 25 | SPI1 | | - (vect_t)SPI2_IRQHandler, //| 26 | SPI2 | | - (vect_t)UART1_IRQHandler, //| 27 | UART1 | | - (vect_t)UART2_IRQHandler, //| 28 | UART2 | | - (vect_t)UART3_IRQHandler, //| 29 | UART3 | | - (vect_t)SUART12_IRQHandler, //| 30 | SUART1/2 | | - (vect_t)USB_IRQHandler //| 31 | USB | | - //==========================================| -}; - - -/*----------------------------------------------------------------------*/ -/*-------------- Set up initial stack and heap --------------*/ -/*----------------------------------------------------------------------*/ -__value_in_regs struct __initial_stackheap -__user_initial_stackheap(unsigned hb, unsigned sb, unsigned hl, unsigned sl) -{ - struct __initial_stackheap s; - - s.heap_base = hb; - s.stack_base = sb; - s.heap_limit = s.stack_base; - s.stack_limit = s.heap_base; - return s; -} - -/*----------------------------------------------------------------------*/ -/*------ Set test status bits in testbench when main() exits -------*/ -/*----------------------------------------------------------------------*/ -void _sys_exit(int return_code) -{ - while(1); -} - - - diff --git a/bsp/essemi/es32f0271/libraries/CMSIS/Device/EastSoft/ES32F0271/Startup/keil/startup_es32f027x.s b/bsp/essemi/es32f0271/libraries/CMSIS/Device/EastSoft/ES32F0271/Startup/keil/startup_es32f027x.s deleted file mode 100644 index 78c14566c3..0000000000 --- a/bsp/essemi/es32f0271/libraries/CMSIS/Device/EastSoft/ES32F0271/Startup/keil/startup_es32f027x.s +++ /dev/null @@ -1,244 +0,0 @@ -;******************************************************************************* -; *file : startup_ES32F027x.s -; *description: ES32F027x Device Startup File -; *author : Eastsoft MCU Software Team -; *version : V0.01 -; *data : 12/10/2018 -; -; *Copyright (C) 2018 Shanghai Eastsoft Microelectronics Co., Ltd. -; * -; * THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED -; * OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF -; * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE. -; * ARM SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR -; * CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER. -;******************************************************************************* - - -; Stack Configuration -; Stack Size (in Bytes) <0x0-0xFFFFFFFF:8> -; - -Stack_Size EQU 0x00000400 - - AREA STACK, NOINIT, READWRITE, ALIGN=3 -Stack_Mem SPACE Stack_Size -__initial_sp - - -; Heap Configuration -; Heap Size (in Bytes) <0x0-0xFFFFFFFF:8> -; - -Heap_Size EQU 0x00000000 - - AREA HEAP, NOINIT, READWRITE, ALIGN=3 -__heap_base -Heap_Mem SPACE Heap_Size -__heap_limit - - - PRESERVE8 - THUMB - - -; Vector Table Mapped to Address 0 at Reset - - AREA RESET, DATA, READONLY - EXPORT __Vectors - -__Vectors DCD __initial_sp ; Top of Stack - ; External Interrupts - DCD Reset_Handler ;1, Reset Handler - DCD NMI_Handler ;2, NMI Handler - DCD HardFault_Handler ;3, HARDFAULT Handler - DCD 0 ;4, Reserved - DCD 0 ;5, Reserved - DCD 0 ;6, Reserved - DCD 0 ;7, Reserved - DCD 0 ;8, Reserved - DCD 0 ;9, Reserved - DCD 0 ;10, Reserved - DCD SVC_Handler ;11, SVC Handler - DCD 0 ;12, Reserved - DCD 0 ;13, Reserved - DCD PendSV_Handler ;14, PENDSV Handler - DCD SysTick_Handler ;15, SYSTICK Handler - DCD WWDT_IRQHandler ;16, WWDT IRQHandler - DCD PVD_IRQHandler ;17, PVD IRQHandler - DCD RTC_IRQHandler ;18, RTC IRQHandler - DCD LowPowerWakeup_IRQHandler ;19, LowPowerWakeup IRQHandler - DCD 0 ;20, Reserved - DCD EXTI0_1_IRQHandler ;21, EXTI01_1 IRQHandler - DCD EXTI2_3_IRQHandler ;22, EXTI2_3 IRQHandler - DCD EXTI4_15_IRQHandler ;23, EXTI4_15 IRQHandler - DCD 0 ;24, Reserved - DCD DMA1_CH0_IRQHandler ;25, DMA1_CH0 IRQHandler - DCD DMA1_CH1_2_IRQHandler ;26, DMA1_CH1_2 IRQHandler - DCD DMA1_CH3_5_IRQHandler ;27, DMA1_CH3_5 IRQHandler - DCD ADC_CMP_IRQHandler ;28, ADC_CMP IRQHandler - DCD AD16C4T1_IRQHandler ;29, AD16C4T1 IRQHandler - DCD BS16T1_IRQHandler ;30, BS16T1 IRQHandler - DCD GP32C4T1_IRQHandler ;31, GP32C4T1 IRQHandler - DCD GP16C4T1_IRQHandler ;32, GP16C4T1 IRQHandler - DCD GP16C4T2_IRQHandler ;33, GP16C4T2 IRQHandler - DCD GP16C4T3_IRQHandler ;34, GP16C4T3 IRQHandler - DCD GP16C2T1_IRQHandler ;35, GP16C2T1 IRQHandler - DCD GP16C2T2_IRQHandler ;36, GP16C2T2 IRQHandler - DCD GP16C2T3_IRQHandler ;37, GP16C2T3 IRQHandler - DCD GP16C2T4_IRQHandler ;38, GP16C2T4 IRQHandler - DCD I2C1_IRQHandler ;39, I2C1 IRQHandler - DCD I2C2_IRQHandler ;40, I2C2 IRQHandler - DCD SPI1_IRQHandler ;41, SPI1 IRQHandler - DCD SPI2_IRQHandler ;42, SPI2 IRQHandler - DCD UART1_IRQHandler ;43, UART1 IRQHandler - DCD UART2_IRQHandler ;44, UART2 IRQHandler - DCD UART3_AES_IRQHandler ;45, UART3_AES IRQHandler - DCD SUART1_SUART2_IRQHandler ;46, SUART1_SUART2 IRQHandler - DCD USB_IRQHandler ;47, USB IRQHandler - - - AREA |.text|, CODE, READONLY - - -; Reset Handler - -Reset_Handler PROC - EXPORT Reset_Handler [WEAK] - IMPORT __main - IMPORT SystemInit - LDR R0, =SystemInit - BLX R0 - LDR R0, =__main - BX R0 - ENDP - -; Dummy Exception IRQHandlers (infinite loops which can be modified) - -NMI_Handler PROC - EXPORT NMI_Handler [WEAK] - B . - ENDP -HardFault_Handler PROC - EXPORT HardFault_Handler [WEAK] - B . - ENDP - - -SVC_Handler PROC - EXPORT SVC_Handler [WEAK] - B . - ENDP - -PendSV_Handler PROC - EXPORT PendSV_Handler [WEAK] - B . - ENDP -SysTick_Handler PROC - EXPORT SysTick_Handler [WEAK] - B . - ENDP - -Default_Handler PROC - - - - EXPORT WWDT_IRQHandler [WEAK] - EXPORT PVD_IRQHandler [WEAK] - EXPORT RTC_IRQHandler [WEAK] - EXPORT LowPowerWakeup_IRQHandler [WEAK] - EXPORT EXTI0_1_IRQHandler [WEAK] - EXPORT EXTI2_3_IRQHandler [WEAK] - EXPORT EXTI4_15_IRQHandler [WEAK] - EXPORT DMA1_CH0_IRQHandler [WEAK] - EXPORT DMA1_CH1_2_IRQHandler [WEAK] - EXPORT DMA1_CH3_5_IRQHandler [WEAK] - EXPORT ADC_CMP_IRQHandler [WEAK] - EXPORT AD16C4T1_IRQHandler [WEAK] - EXPORT BS16T1_IRQHandler [WEAK] - EXPORT GP32C4T1_IRQHandler [WEAK] - EXPORT GP16C4T1_IRQHandler [WEAK] - EXPORT GP16C4T2_IRQHandler [WEAK] - EXPORT GP16C4T3_IRQHandler [WEAK] - EXPORT GP16C2T1_IRQHandler [WEAK] - EXPORT GP16C2T2_IRQHandler [WEAK] - EXPORT GP16C2T3_IRQHandler [WEAK] - EXPORT GP16C2T4_IRQHandler [WEAK] - EXPORT I2C1_IRQHandler [WEAK] - EXPORT I2C2_IRQHandler [WEAK] - EXPORT SPI1_IRQHandler [WEAK] - EXPORT SPI2_IRQHandler [WEAK] - EXPORT UART1_IRQHandler [WEAK] - EXPORT UART2_IRQHandler [WEAK] - EXPORT UART3_AES_IRQHandler [WEAK] - EXPORT SUART1_SUART2_IRQHandler [WEAK] - EXPORT USB_IRQHandler [WEAK] - - - -WWDT_IRQHandler -PVD_IRQHandler -RTC_IRQHandler -LowPowerWakeup_IRQHandler -EXTI0_1_IRQHandler -EXTI2_3_IRQHandler -EXTI4_15_IRQHandler -DMA1_CH0_IRQHandler -DMA1_CH1_2_IRQHandler -DMA1_CH3_5_IRQHandler -ADC_CMP_IRQHandler -AD16C4T1_IRQHandler -BS16T1_IRQHandler -GP32C4T1_IRQHandler -GP16C4T1_IRQHandler -GP16C4T2_IRQHandler -GP16C4T3_IRQHandler -GP16C2T1_IRQHandler -GP16C2T2_IRQHandler -GP16C2T3_IRQHandler -GP16C2T4_IRQHandler -I2C1_IRQHandler -I2C2_IRQHandler -SPI1_IRQHandler -SPI2_IRQHandler -UART1_IRQHandler -UART2_IRQHandler -UART3_AES_IRQHandler -SUART1_SUART2_IRQHandler -USB_IRQHandler - - - B . - - ENDP - - ALIGN - -; User Initial Stack & Heap - - IF :DEF:__MICROLIB - - EXPORT __initial_sp - EXPORT __heap_base - EXPORT __heap_limit - - ELSE - - IMPORT __use_two_region_memory - EXPORT __user_initial_stackheap - -__user_initial_stackheap - - LDR R0, = Heap_Mem - LDR R1, =(Stack_Mem + Stack_Size) - LDR R2, = (Heap_Mem + Heap_Size) - LDR R3, = Stack_Mem - BX LR - - ALIGN - - ENDIF - - END - - diff --git a/bsp/essemi/es32f0271/libraries/CMSIS/Device/EastSoft/ES32F0271/System/core_cm0.c b/bsp/essemi/es32f0271/libraries/CMSIS/Device/EastSoft/ES32F0271/System/core_cm0.c deleted file mode 100644 index e8a1ed21c0..0000000000 --- a/bsp/essemi/es32f0271/libraries/CMSIS/Device/EastSoft/ES32F0271/System/core_cm0.c +++ /dev/null @@ -1,472 +0,0 @@ -/* - *----------------------------------------------------------------------------- - * The confidential and proprietary information contained in this file may - * only be used by a person authorised under and to the extent permitted - * by a subsisting licensing agreement from ARM Limited. - * - * (C) COPYRIGHT 2009-2010 ARM Limited. - * ALL RIGHTS RESERVED - * - * This entire notice must be reproduced on all copies of this file - * and copies of this file may only be made by a person if such person is - * permitted to do so under the terms of a subsisting license agreement - * from ARM Limited. - * - * SVN Information - * - * Checked In : $Date: 2008-12-31 10:59:44 +0000 (Wed, 31 Dec 2008) $ - * - * Revision : $Revision: 97564 $ - * - * Release Information : Cortex-M0-AT510-r0p0-03rel0 - *----------------------------------------------------------------------------- - */ - - -#include - - -/* define compiler specific symbols */ -#if defined ( __CC_ARM ) - #define __ASM __asm /*!< asm keyword for armcc */ - #define __INLINE __inline /*!< inline keyword for armcc */ - -#elif defined ( __ICCARM__ ) - #define __ASM __asm /*!< asm keyword for iarcc */ - #define __INLINE inline /*!< inline keyword for iarcc. Only avaiable in High optimization mode! */ - #define __nop __no_operation /*!< no operation intrinsic in iarcc */ - -#elif defined ( __GNUC__ ) - #define __ASM asm /*!< asm keyword for gcc */ - #define __INLINE inline /*!< inline keyword for gcc */ -#endif - - - -#if defined ( __CC_ARM ) /*------------------RealView Compiler -----------------*/ - -/** - * @brief Return the Process Stack Pointer - * - * @param none - * @return uint32_t ProcessStackPointer - * - * Return the actual process stack pointer - */ -__ASM uint32_t __get_PSP(void) -{ - mrs r0, psp - bx lr -} - -/** - * @brief Set the Process Stack Pointer - * - * @param uint32_t Process Stack Pointer - * @return none - * - * Assign the value ProcessStackPointer to the MSP - * (process stack pointer) Cortex processor register - */ -__ASM void __set_PSP(uint32_t topOfProcStack) -{ - msr psp, r0 - bx lr -} - -/** - * @brief Return the Main Stack Pointer - * - * @param none - * @return uint32_t Main Stack Pointer - * - * Return the current value of the MSP (main stack pointer) - * Cortex processor register - */ -__ASM uint32_t __get_MSP(void) -{ - mrs r0, msp - bx lr -} - -/** - * @brief Set the Main Stack Pointer - * - * @param uint32_t Main Stack Pointer - * @return none - * - * Assign the value mainStackPointer to the MSP - * (main stack pointer) Cortex processor register - */ -__ASM void __set_MSP(uint32_t mainStackPointer) -{ - msr msp, r0 - bx lr -} - -/** - * @brief Reverse byte order in unsigned short value - * - * @param uint16_t value to reverse - * @return uint32_t reversed value - * - * Reverse byte order in unsigned short value - */ -__ASM uint32_t __REV16(uint16_t value) -{ - rev16 r0, r0 - bx lr -} - -/** - * @brief Reverse byte order in signed short value with sign extension to integer - * - * @param int16_t value to reverse - * @return int32_t reversed value - * - * Reverse byte order in signed short value with sign extension to integer - */ -__ASM int32_t __REVSH(int16_t value) -{ - revsh r0, r0 - bx lr -} - - -#if (__ARMCC_VERSION < 400000) - - -/** - * @brief Return the Priority Mask value - * - * @param none - * @return uint32_t PriMask - * - * Return the state of the priority mask bit from the priority mask - * register - */ -__ASM uint32_t __get_PRIMASK(void) -{ - mrs r0, primask - bx lr -} - -/** - * @brief Set the Priority Mask value - * - * @param uint32_t PriMask - * @return none - * - * Set the priority mask bit in the priority mask register - */ -__ASM void __set_PRIMASK(uint32_t priMask) -{ - msr primask, r0 - bx lr -} - - -/** - * @brief Return the Control Register value - * - * @param none - * @return uint32_t Control value - * - * Return the content of the control register - */ -__ASM uint32_t __get_CONTROL(void) -{ - mrs r0, control - bx lr -} - -/** - * @brief Set the Control Register value - * - * @param uint32_t Control value - * @return none - * - * Set the control register - */ -__ASM void __set_CONTROL(uint32_t control) -{ - msr control, r0 - bx lr -} - -#endif /* __ARMCC_VERSION */ - - -#elif (defined (__ICCARM__)) /*------------------ ICC Compiler -------------------*/ -#pragma diag_suppress=Pe940 - -/** - * @brief Return the Process Stack Pointer - * - * @param none - * @return uint32_t ProcessStackPointer - * - * Return the actual process stack pointer - */ -uint32_t __get_PSP(void) -{ - __ASM("mrs r0, psp"); - __ASM("bx lr"); -} - -/** - * @brief Set the Process Stack Pointer - * - * @param uint32_t Process Stack Pointer - * @return none - * - * Assign the value ProcessStackPointer to the MSP - * (process stack pointer) Cortex processor register - */ -void __set_PSP(uint32_t topOfProcStack) -{ - __ASM("msr psp, r0"); - __ASM("bx lr"); -} - -/** - * @brief Return the Main Stack Pointer - * - * @param none - * @return uint32_t Main Stack Pointer - * - * Return the current value of the MSP (main stack pointer) - * Cortex processor register - */ -uint32_t __get_MSP(void) -{ - __ASM("mrs r0, msp"); - __ASM("bx lr"); -} - -/** - * @brief Set the Main Stack Pointer - * - * @param uint32_t Main Stack Pointer - * @return none - * - * Assign the value mainStackPointer to the MSP - * (main stack pointer) Cortex processor register - */ -void __set_MSP(uint32_t topOfMainStack) -{ - __ASM("msr msp, r0"); - __ASM("bx lr"); -} - -/** - * @brief Reverse byte order in unsigned short value - * - * @param uint16_t value to reverse - * @return uint32_t reversed value - * - * Reverse byte order in unsigned short value - */ -uint32_t __REV16(uint16_t value) -{ - __ASM("rev16 r0, r0"); - __ASM("bx lr"); -} - - -#pragma diag_default=Pe940 - - - - -#elif (defined (__GNUC__)) /*------------------ GNU Compiler ---------------------*/ - -/** - * @brief Return the Process Stack Pointer - * - * @param none - * @return uint32_t ProcessStackPointer - * - * Return the actual process stack pointer - */ -uint32_t __get_PSP(void) -{ - uint32_t result=0; - - __ASM volatile ("MRS %0, psp" : "=r" (result) ); - return(result); -} - -/** - * @brief Set the Process Stack Pointer - * - * @param uint32_t Process Stack Pointer - * @return none - * - * Assign the value ProcessStackPointer to the MSP - * (process stack pointer) Cortex processor register - */ -void __set_PSP(uint32_t topOfProcStack) -{ - __ASM volatile ("MSR psp, %0" : : "r" (topOfProcStack) ); -} - -/** - * @brief Return the Main Stack Pointer - * - * @param none - * @return uint32_t Main Stack Pointer - * - * Return the current value of the MSP (main stack pointer) - * Cortex processor register - */ -uint32_t __get_MSP(void) -{ - uint32_t result=0; - - __ASM volatile ("MRS %0, msp" : "=r" (result) ); - return(result); -} - -/** - * @brief Set the Main Stack Pointer - * - * @param uint32_t Main Stack Pointer - * @return none - * - * Assign the value mainStackPointer to the MSP - * (main stack pointer) Cortex processor register - */ -void __set_MSP(uint32_t topOfMainStack) -{ - __ASM volatile ("MSR msp, %0" : : "r" (topOfMainStack) ); -} - - -/** - * @brief Return the Priority Mask value - * - * @param none - * @return uint32_t PriMask - * - * Return the state of the priority mask bit from the priority mask - * register - */ -uint32_t __get_PRIMASK(void) -{ - uint32_t result=0; - - __ASM volatile ("MRS %0, primask" : "=r" (result) ); - return(result); -} - -/** - * @brief Set the Priority Mask value - * - * @param uint32_t PriMask - * @return none - * - * Set the priority mask bit in the priority mask register - */ -void __set_PRIMASK(uint32_t priMask) -{ - __ASM volatile ("MSR primask, %0" : : "r" (priMask) ); -} - - -/** - * @brief Reverse byte order in integer value - * - * @param uint32_t value to reverse - * @return uint32_t reversed value - * - * Reverse byte order in integer value - */ -uint32_t __REV(uint32_t value) -{ - uint32_t result=0; - - __ASM volatile ("rev %0, %1" : "=r" (result) : "r" (value) ); - return(result); -} - -/** - * @brief Reverse byte order in unsigned short value - * - * @param uint16_t value to reverse - * @return uint32_t reversed value - * - * Reverse byte order in unsigned short value - */ -uint32_t __REV16(uint16_t value) -{ - uint32_t result=0; - - __ASM volatile ("rev16 %0, %1" : "=r" (result) : "r" (value) ); - return(result); -} - -/** - * @brief Reverse byte order in signed short value with sign extension to integer - * - * @param int32_t value to reverse - * @return int32_t reversed value - * - * Reverse byte order in signed short value with sign extension to integer - */ -int32_t __REVSH(int16_t value) -{ - uint32_t result=0; - - __ASM volatile ("revsh %0, %1" : "=r" (result) : "r" (value) ); - return(result); -} - - -/** - * @brief Return the Control Register value - * - * @param none - * @return uint32_t Control value - * - * Return the content of the control register - */ -uint32_t __get_CONTROL(void) -{ - uint32_t result=0; - - __ASM volatile ("MRS %0, control" : "=r" (result) ); - return(result); -} - -/** - * @brief Set the Control Register value - * - * @param uint32_t Control value - * @return none - * - * Set the control register - */ -void __set_CONTROL(uint32_t control) -{ - __ASM volatile ("MSR control, %0" : : "r" (control) ); -} - -#endif - - - - - - - - - - - - - - - - - diff --git a/bsp/essemi/es32f0271/libraries/CMSIS/Device/EastSoft/ES32F0271/System/retarget.c b/bsp/essemi/es32f0271/libraries/CMSIS/Device/EastSoft/ES32F0271/System/retarget.c deleted file mode 100644 index 1303e0765e..0000000000 --- a/bsp/essemi/es32f0271/libraries/CMSIS/Device/EastSoft/ES32F0271/System/retarget.c +++ /dev/null @@ -1,55 +0,0 @@ -/******************************************************************************/ -/* RETARGET.C: 'Retarget' layer for target-dependent low level functions */ -/******************************************************************************/ -/* This file is part of the uVision/ARM development tools. */ -/* Copyright (c) 2005-2006 Keil Software. All rights reserved. */ -/* This software may only be used under the terms of a valid, current, */ -/* end user licence from KEIL for a compatible version of KEIL software */ -/* development tools. Nothing else gives you the right to use this software. */ -/******************************************************************************/ - -#include -#include - -//#pragma import(__use_no_semihosting_swi) - -__weak uint8_t sendchar(uint8_t ui8char) -{ - (void) ui8char; - return 0; -} - - -int ITM_fputc(int ch); /* ITM debug */ - -struct __FILE -{ -int handle; /* Add whatever you need here */ -}; -FILE __stdout; - - -int fputc(int ch, FILE *f) -{ - return (sendchar(ch)); -} - - -int ferror(FILE *f) -{ - /* Your implementation of ferror */ - return EOF; -} - - -void _ttywrch(int ch) -{ - sendchar(ch); -} - - -void _sys_exit(int return_code) -{ -label: - goto label; /* endless loop */ -} diff --git a/bsp/essemi/es32f0271/libraries/CMSIS/Device/EastSoft/ES32F0271/System/system_es32f027x.c b/bsp/essemi/es32f0271/libraries/CMSIS/Device/EastSoft/ES32F0271/System/system_es32f027x.c deleted file mode 100644 index 6112c52bb4..0000000000 --- a/bsp/essemi/es32f0271/libraries/CMSIS/Device/EastSoft/ES32F0271/System/system_es32f027x.c +++ /dev/null @@ -1,79 +0,0 @@ -/** - ************************************************************************************** - * @file system_es32f027x.c - * @brief System File. - * - * @version V0.01 - * @data 5/17/2018 - * @author Eastsoft AE Team - * @note - * - * Copyright (C) 2018 Shanghai Eastsoft Microelectronics Co., Ltd. ALL rights reserved. - * - ************************************************************************************** - */ - -/* Incudes--------------------------------------------------------*/ -#include "system_es32f027x.h" - -/** @addtogroup CMSIS - * @{ - */ - -/** @addtogroup System_ES32F027X - * @{ - */ - -/* Public Functions -----------------------------------------------------------*/ -/* Public Init Structure ------------------------------------------------------*/ -/* Public Macros --------------------------------------------------------------*/ -/* Public Constants -----------------------------------------------------------*/ -/* Private Macros -------------------------------------------------------------*/ -/* Private Constants-----------------------------------------------------------*/ - -/* Private Variables ----------------------------------------------------------*/ -/** @addtogroup Private_Variables - * @{ - */ - -/** - * @brief update the value of SystemCoreClock after changing the system clock. - */ -unsigned int SystemCoreClock = 4000000; -unsigned int SystemFrequency_SysClk = 4000000; -unsigned int SystemFrequency_AHBClk = 4000000; -unsigned int SystemFrequency_APBClk = 4000000; -unsigned int PLL1Frequency = 48000000; -unsigned int PLL0Frequency = 4000000; - -/** - * @} Private_Variables - */ - -/* Private Functions ----------------------------------------------------------*/ -/** @addtogroup Private_Functions - * @{ - */ - -/** - * @brief:SystemInit. - * @param:none - * @retval:none - */ -void SystemInit (void) -{ -} - -/** - * @} Private_Functions - */ - -/** - * @} System_ES32F072X - */ - -/** - * @} CMSIS - */ -/********** (C) COPYRIGHT Eastsoft Microelectronics END OF FILE SYSTEM_ES32F027X.H **********/ - diff --git a/bsp/essemi/es32f0271/libraries/CMSIS/Device/EastSoft/ES32F0271/System/system_es32f027x.h b/bsp/essemi/es32f0271/libraries/CMSIS/Device/EastSoft/ES32F0271/System/system_es32f027x.h deleted file mode 100644 index d2cee80354..0000000000 --- a/bsp/essemi/es32f0271/libraries/CMSIS/Device/EastSoft/ES32F0271/System/system_es32f027x.h +++ /dev/null @@ -1,83 +0,0 @@ -/** - ************************************************************************************** - * @file SYSTEM_ES32F027x.H - * @brief es32f0271 system head file. - * - * @version V0.01 - * @data 5/17/2018 - * @author Eastsoft AE Team - * @note - * - * Copyright (C) 2018 Shanghai Eastsoft Microelectronics Co., Ltd. ALL rights reserved. - * - ************************************************************************************** - */ - -/* Define to prevent recursive inclusion -------------------------------------*/ - -#ifndef __SYSTEM_ES32F027x_H__ -#define __SYSTEM_ES32F027x_H__ - -#ifdef __cplusplus - extern "C" { -#endif - -/* Includes -------------------------------------------------------*/ -#include - -/** @addtogroup CMSIS - * @{ - */ - -/** @addtogroup System_ES32F027x - * @{ - */ - -/* Public Functions -----------------------------------------------------------*/ -/* Public Init Structure ------------------------------------------------------*/ -/* Public Macros --------------------------------------------------------------*/ -/* Public Constants -----------------------------------------------------------*/ -/* Private Variables ----------------------------------------------------------*/ -/* Private Macros -------------------------------------------------------------*/ -/* Private Constants-----------------------------------------------------------*/ - -/* Public Types ---------------------------------------------------------------*/ -/** @addtogroup Public_Types - * @{ - */ -extern unsigned int SystemCoreClock; -extern unsigned int SystemFrequency_SysClk; -extern unsigned int SystemFrequency_AHBClk; -extern unsigned int SystemFrequency_APBClk; -extern unsigned int PLL1Frequency; -extern unsigned int PLL0Frequency; - -/* Exported function -------------------------------------------------*/ -/** @addtogroup Public_Functions - * @{ - */ - -extern void SystemInit (void); - -#ifdef __cplusplus -} -#endif - -#endif - -/** - * @} Public_Functions - */ - -/** - * @} Public_Types - */ - -/** - * @} System_ES32F027x - */ - -/** - * @} CMSIS - */ -/********** (C) COPYRIGHT Eastsoft Microelectronics END OF FILE SYSTEM_ES32F027x.H **********/ diff --git a/bsp/essemi/es32f0271/libraries/CMSIS/Include/arm_common_tables.h b/bsp/essemi/es32f0271/libraries/CMSIS/Include/arm_common_tables.h deleted file mode 100644 index dfea7460e9..0000000000 --- a/bsp/essemi/es32f0271/libraries/CMSIS/Include/arm_common_tables.h +++ /dev/null @@ -1,121 +0,0 @@ -/* ---------------------------------------------------------------------- - * Project: CMSIS DSP Library - * Title: arm_common_tables.h - * Description: Extern declaration for common tables - * - * $Date: 27. January 2017 - * $Revision: V.1.5.1 - * - * Target Processor: Cortex-M cores - * -------------------------------------------------------------------- */ -/* - * Copyright (C) 2010-2017 ARM Limited or its affiliates. All rights reserved. - * - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed under the Apache License, Version 2.0 (the License); you may - * not use this file except in compliance with the License. - * You may obtain a copy of the License at - * - * www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an AS IS BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - */ - -#ifndef _ARM_COMMON_TABLES_H -#define _ARM_COMMON_TABLES_H - -#include "arm_math.h" - -extern const uint16_t armBitRevTable[1024]; -extern const q15_t armRecipTableQ15[64]; -extern const q31_t armRecipTableQ31[64]; -extern const float32_t twiddleCoef_16[32]; -extern const float32_t twiddleCoef_32[64]; -extern const float32_t twiddleCoef_64[128]; -extern const float32_t twiddleCoef_128[256]; -extern const float32_t twiddleCoef_256[512]; -extern const float32_t twiddleCoef_512[1024]; -extern const float32_t twiddleCoef_1024[2048]; -extern const float32_t twiddleCoef_2048[4096]; -extern const float32_t twiddleCoef_4096[8192]; -#define twiddleCoef twiddleCoef_4096 -extern const q31_t twiddleCoef_16_q31[24]; -extern const q31_t twiddleCoef_32_q31[48]; -extern const q31_t twiddleCoef_64_q31[96]; -extern const q31_t twiddleCoef_128_q31[192]; -extern const q31_t twiddleCoef_256_q31[384]; -extern const q31_t twiddleCoef_512_q31[768]; -extern const q31_t twiddleCoef_1024_q31[1536]; -extern const q31_t twiddleCoef_2048_q31[3072]; -extern const q31_t twiddleCoef_4096_q31[6144]; -extern const q15_t twiddleCoef_16_q15[24]; -extern const q15_t twiddleCoef_32_q15[48]; -extern const q15_t twiddleCoef_64_q15[96]; -extern const q15_t twiddleCoef_128_q15[192]; -extern const q15_t twiddleCoef_256_q15[384]; -extern const q15_t twiddleCoef_512_q15[768]; -extern const q15_t twiddleCoef_1024_q15[1536]; -extern const q15_t twiddleCoef_2048_q15[3072]; -extern const q15_t twiddleCoef_4096_q15[6144]; -extern const float32_t twiddleCoef_rfft_32[32]; -extern const float32_t twiddleCoef_rfft_64[64]; -extern const float32_t twiddleCoef_rfft_128[128]; -extern const float32_t twiddleCoef_rfft_256[256]; -extern const float32_t twiddleCoef_rfft_512[512]; -extern const float32_t twiddleCoef_rfft_1024[1024]; -extern const float32_t twiddleCoef_rfft_2048[2048]; -extern const float32_t twiddleCoef_rfft_4096[4096]; - -/* floating-point bit reversal tables */ -#define ARMBITREVINDEXTABLE_16_TABLE_LENGTH ((uint16_t)20) -#define ARMBITREVINDEXTABLE_32_TABLE_LENGTH ((uint16_t)48) -#define ARMBITREVINDEXTABLE_64_TABLE_LENGTH ((uint16_t)56) -#define ARMBITREVINDEXTABLE_128_TABLE_LENGTH ((uint16_t)208) -#define ARMBITREVINDEXTABLE_256_TABLE_LENGTH ((uint16_t)440) -#define ARMBITREVINDEXTABLE_512_TABLE_LENGTH ((uint16_t)448) -#define ARMBITREVINDEXTABLE_1024_TABLE_LENGTH ((uint16_t)1800) -#define ARMBITREVINDEXTABLE_2048_TABLE_LENGTH ((uint16_t)3808) -#define ARMBITREVINDEXTABLE_4096_TABLE_LENGTH ((uint16_t)4032) - -extern const uint16_t armBitRevIndexTable16[ARMBITREVINDEXTABLE_16_TABLE_LENGTH]; -extern const uint16_t armBitRevIndexTable32[ARMBITREVINDEXTABLE_32_TABLE_LENGTH]; -extern const uint16_t armBitRevIndexTable64[ARMBITREVINDEXTABLE_64_TABLE_LENGTH]; -extern const uint16_t armBitRevIndexTable128[ARMBITREVINDEXTABLE_128_TABLE_LENGTH]; -extern const uint16_t armBitRevIndexTable256[ARMBITREVINDEXTABLE_256_TABLE_LENGTH]; -extern const uint16_t armBitRevIndexTable512[ARMBITREVINDEXTABLE_512_TABLE_LENGTH]; -extern const uint16_t armBitRevIndexTable1024[ARMBITREVINDEXTABLE_1024_TABLE_LENGTH]; -extern const uint16_t armBitRevIndexTable2048[ARMBITREVINDEXTABLE_2048_TABLE_LENGTH]; -extern const uint16_t armBitRevIndexTable4096[ARMBITREVINDEXTABLE_4096_TABLE_LENGTH]; - -/* fixed-point bit reversal tables */ -#define ARMBITREVINDEXTABLE_FIXED_16_TABLE_LENGTH ((uint16_t)12) -#define ARMBITREVINDEXTABLE_FIXED_32_TABLE_LENGTH ((uint16_t)24) -#define ARMBITREVINDEXTABLE_FIXED_64_TABLE_LENGTH ((uint16_t)56) -#define ARMBITREVINDEXTABLE_FIXED_128_TABLE_LENGTH ((uint16_t)112) -#define ARMBITREVINDEXTABLE_FIXED_256_TABLE_LENGTH ((uint16_t)240) -#define ARMBITREVINDEXTABLE_FIXED_512_TABLE_LENGTH ((uint16_t)480) -#define ARMBITREVINDEXTABLE_FIXED_1024_TABLE_LENGTH ((uint16_t)992) -#define ARMBITREVINDEXTABLE_FIXED_2048_TABLE_LENGTH ((uint16_t)1984) -#define ARMBITREVINDEXTABLE_FIXED_4096_TABLE_LENGTH ((uint16_t)4032) - -extern const uint16_t armBitRevIndexTable_fixed_16[ARMBITREVINDEXTABLE_FIXED_16_TABLE_LENGTH]; -extern const uint16_t armBitRevIndexTable_fixed_32[ARMBITREVINDEXTABLE_FIXED_32_TABLE_LENGTH]; -extern const uint16_t armBitRevIndexTable_fixed_64[ARMBITREVINDEXTABLE_FIXED_64_TABLE_LENGTH]; -extern const uint16_t armBitRevIndexTable_fixed_128[ARMBITREVINDEXTABLE_FIXED_128_TABLE_LENGTH]; -extern const uint16_t armBitRevIndexTable_fixed_256[ARMBITREVINDEXTABLE_FIXED_256_TABLE_LENGTH]; -extern const uint16_t armBitRevIndexTable_fixed_512[ARMBITREVINDEXTABLE_FIXED_512_TABLE_LENGTH]; -extern const uint16_t armBitRevIndexTable_fixed_1024[ARMBITREVINDEXTABLE_FIXED_1024_TABLE_LENGTH]; -extern const uint16_t armBitRevIndexTable_fixed_2048[ARMBITREVINDEXTABLE_FIXED_2048_TABLE_LENGTH]; -extern const uint16_t armBitRevIndexTable_fixed_4096[ARMBITREVINDEXTABLE_FIXED_4096_TABLE_LENGTH]; - -/* Tables for Fast Math Sine and Cosine */ -extern const float32_t sinTable_f32[FAST_MATH_TABLE_SIZE + 1]; -extern const q31_t sinTable_q31[FAST_MATH_TABLE_SIZE + 1]; -extern const q15_t sinTable_q15[FAST_MATH_TABLE_SIZE + 1]; - -#endif /* ARM_COMMON_TABLES_H */ diff --git a/bsp/essemi/es32f0271/libraries/CMSIS/Include/arm_const_structs.h b/bsp/essemi/es32f0271/libraries/CMSIS/Include/arm_const_structs.h deleted file mode 100644 index 80a3e8bbe7..0000000000 --- a/bsp/essemi/es32f0271/libraries/CMSIS/Include/arm_const_structs.h +++ /dev/null @@ -1,66 +0,0 @@ -/* ---------------------------------------------------------------------- - * Project: CMSIS DSP Library - * Title: arm_const_structs.h - * Description: Constant structs that are initialized for user convenience. - * For example, some can be given as arguments to the arm_cfft_f32() function. - * - * $Date: 27. January 2017 - * $Revision: V.1.5.1 - * - * Target Processor: Cortex-M cores - * -------------------------------------------------------------------- */ -/* - * Copyright (C) 2010-2017 ARM Limited or its affiliates. All rights reserved. - * - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed under the Apache License, Version 2.0 (the License); you may - * not use this file except in compliance with the License. - * You may obtain a copy of the License at - * - * www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an AS IS BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - */ - -#ifndef _ARM_CONST_STRUCTS_H -#define _ARM_CONST_STRUCTS_H - -#include "arm_math.h" -#include "arm_common_tables.h" - - extern const arm_cfft_instance_f32 arm_cfft_sR_f32_len16; - extern const arm_cfft_instance_f32 arm_cfft_sR_f32_len32; - extern const arm_cfft_instance_f32 arm_cfft_sR_f32_len64; - extern const arm_cfft_instance_f32 arm_cfft_sR_f32_len128; - extern const arm_cfft_instance_f32 arm_cfft_sR_f32_len256; - extern const arm_cfft_instance_f32 arm_cfft_sR_f32_len512; - extern const arm_cfft_instance_f32 arm_cfft_sR_f32_len1024; - extern const arm_cfft_instance_f32 arm_cfft_sR_f32_len2048; - extern const arm_cfft_instance_f32 arm_cfft_sR_f32_len4096; - - extern const arm_cfft_instance_q31 arm_cfft_sR_q31_len16; - extern const arm_cfft_instance_q31 arm_cfft_sR_q31_len32; - extern const arm_cfft_instance_q31 arm_cfft_sR_q31_len64; - extern const arm_cfft_instance_q31 arm_cfft_sR_q31_len128; - extern const arm_cfft_instance_q31 arm_cfft_sR_q31_len256; - extern const arm_cfft_instance_q31 arm_cfft_sR_q31_len512; - extern const arm_cfft_instance_q31 arm_cfft_sR_q31_len1024; - extern const arm_cfft_instance_q31 arm_cfft_sR_q31_len2048; - extern const arm_cfft_instance_q31 arm_cfft_sR_q31_len4096; - - extern const arm_cfft_instance_q15 arm_cfft_sR_q15_len16; - extern const arm_cfft_instance_q15 arm_cfft_sR_q15_len32; - extern const arm_cfft_instance_q15 arm_cfft_sR_q15_len64; - extern const arm_cfft_instance_q15 arm_cfft_sR_q15_len128; - extern const arm_cfft_instance_q15 arm_cfft_sR_q15_len256; - extern const arm_cfft_instance_q15 arm_cfft_sR_q15_len512; - extern const arm_cfft_instance_q15 arm_cfft_sR_q15_len1024; - extern const arm_cfft_instance_q15 arm_cfft_sR_q15_len2048; - extern const arm_cfft_instance_q15 arm_cfft_sR_q15_len4096; - -#endif diff --git a/bsp/essemi/es32f0271/libraries/CMSIS/Include/arm_math.h b/bsp/essemi/es32f0271/libraries/CMSIS/Include/arm_math.h deleted file mode 100644 index ea9dd26aa8..0000000000 --- a/bsp/essemi/es32f0271/libraries/CMSIS/Include/arm_math.h +++ /dev/null @@ -1,7157 +0,0 @@ -/****************************************************************************** - * @file arm_math.h - * @brief Public header file for CMSIS DSP LibraryU - * @version V1.5.3 - * @date 10. January 2018 - ******************************************************************************/ -/* - * Copyright (c) 2010-2018 Arm Limited or its affiliates. All rights reserved. - * - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed under the Apache License, Version 2.0 (the License); you may - * not use this file except in compliance with the License. - * You may obtain a copy of the License at - * - * www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an AS IS BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - */ - -/** - \mainpage CMSIS DSP Software Library - * - * Introduction - * ------------ - * - * This user manual describes the CMSIS DSP software library, - * a suite of common signal processing functions for use on Cortex-M processor based devices. - * - * The library is divided into a number of functions each covering a specific category: - * - Basic math functions - * - Fast math functions - * - Complex math functions - * - Filters - * - Matrix functions - * - Transforms - * - Motor control functions - * - Statistical functions - * - Support functions - * - Interpolation functions - * - * The library has separate functions for operating on 8-bit integers, 16-bit integers, - * 32-bit integer and 32-bit floating-point values. - * - * Using the Library - * ------------ - * - * The library installer contains prebuilt versions of the libraries in the Lib folder. - * - arm_cortexM7lfdp_math.lib (Cortex-M7, Little endian, Double Precision Floating Point Unit) - * - arm_cortexM7bfdp_math.lib (Cortex-M7, Big endian, Double Precision Floating Point Unit) - * - arm_cortexM7lfsp_math.lib (Cortex-M7, Little endian, Single Precision Floating Point Unit) - * - arm_cortexM7bfsp_math.lib (Cortex-M7, Big endian and Single Precision Floating Point Unit on) - * - arm_cortexM7l_math.lib (Cortex-M7, Little endian) - * - arm_cortexM7b_math.lib (Cortex-M7, Big endian) - * - arm_cortexM4lf_math.lib (Cortex-M4, Little endian, Floating Point Unit) - * - arm_cortexM4bf_math.lib (Cortex-M4, Big endian, Floating Point Unit) - * - arm_cortexM4l_math.lib (Cortex-M4, Little endian) - * - arm_cortexM4b_math.lib (Cortex-M4, Big endian) - * - arm_cortexM3l_math.lib (Cortex-M3, Little endian) - * - arm_cortexM3b_math.lib (Cortex-M3, Big endian) - * - arm_cortexM0l_math.lib (Cortex-M0 / Cortex-M0+, Little endian) - * - arm_cortexM0b_math.lib (Cortex-M0 / Cortex-M0+, Big endian) - * - arm_ARMv8MBLl_math.lib (Armv8-M Baseline, Little endian) - * - arm_ARMv8MMLl_math.lib (Armv8-M Mainline, Little endian) - * - arm_ARMv8MMLlfsp_math.lib (Armv8-M Mainline, Little endian, Single Precision Floating Point Unit) - * - arm_ARMv8MMLld_math.lib (Armv8-M Mainline, Little endian, DSP instructions) - * - arm_ARMv8MMLldfsp_math.lib (Armv8-M Mainline, Little endian, DSP instructions, Single Precision Floating Point Unit) - * - * The library functions are declared in the public file arm_math.h which is placed in the Include folder. - * Simply include this file and link the appropriate library in the application and begin calling the library functions. The Library supports single - * public header file arm_math.h for Cortex-M cores with little endian and big endian. Same header file will be used for floating point unit(FPU) variants. - * Define the appropriate preprocessor macro ARM_MATH_CM7 or ARM_MATH_CM4 or ARM_MATH_CM3 or - * ARM_MATH_CM0 or ARM_MATH_CM0PLUS depending on the target processor in the application. - * For Armv8-M cores define preprocessor macro ARM_MATH_ARMV8MBL or ARM_MATH_ARMV8MML. - * Set preprocessor macro __DSP_PRESENT if Armv8-M Mainline core supports DSP instructions. - * - * - * Examples - * -------- - * - * The library ships with a number of examples which demonstrate how to use the library functions. - * - * Toolchain Support - * ------------ - * - * The library has been developed and tested with MDK version 5.14.0.0 - * The library is being tested in GCC and IAR toolchains and updates on this activity will be made available shortly. - * - * Building the Library - * ------------ - * - * The library installer contains a project file to rebuild libraries on MDK toolchain in the CMSIS\\DSP_Lib\\Source\\ARM folder. - * - arm_cortexM_math.uvprojx - * - * - * The libraries can be built by opening the arm_cortexM_math.uvprojx project in MDK-ARM, selecting a specific target, and defining the optional preprocessor macros detailed above. - * - * Preprocessor Macros - * ------------ - * - * Each library project have different preprocessor macros. - * - * - UNALIGNED_SUPPORT_DISABLE: - * - * Define macro UNALIGNED_SUPPORT_DISABLE, If the silicon does not support unaligned memory access - * - * - ARM_MATH_BIG_ENDIAN: - * - * Define macro ARM_MATH_BIG_ENDIAN to build the library for big endian targets. By default library builds for little endian targets. - * - * - ARM_MATH_MATRIX_CHECK: - * - * Define macro ARM_MATH_MATRIX_CHECK for checking on the input and output sizes of matrices - * - * - ARM_MATH_ROUNDING: - * - * Define macro ARM_MATH_ROUNDING for rounding on support functions - * - * - ARM_MATH_CMx: - * - * Define macro ARM_MATH_CM4 for building the library on Cortex-M4 target, ARM_MATH_CM3 for building library on Cortex-M3 target - * and ARM_MATH_CM0 for building library on Cortex-M0 target, ARM_MATH_CM0PLUS for building library on Cortex-M0+ target, and - * ARM_MATH_CM7 for building the library on cortex-M7. - * - * - ARM_MATH_ARMV8MxL: - * - * Define macro ARM_MATH_ARMV8MBL for building the library on Armv8-M Baseline target, ARM_MATH_ARMV8MML for building library - * on Armv8-M Mainline target. - * - * - __FPU_PRESENT: - * - * Initialize macro __FPU_PRESENT = 1 when building on FPU supported Targets. Enable this macro for floating point libraries. - * - * - __DSP_PRESENT: - * - * Initialize macro __DSP_PRESENT = 1 when Armv8-M Mainline core supports DSP instructions. - * - *
- * CMSIS-DSP in ARM::CMSIS Pack - * ----------------------------- - * - * The following files relevant to CMSIS-DSP are present in the ARM::CMSIS Pack directories: - * |File/Folder |Content | - * |------------------------------|------------------------------------------------------------------------| - * |\b CMSIS\\Documentation\\DSP | This documentation | - * |\b CMSIS\\DSP_Lib | Software license agreement (license.txt) | - * |\b CMSIS\\DSP_Lib\\Examples | Example projects demonstrating the usage of the library functions | - * |\b CMSIS\\DSP_Lib\\Source | Source files for rebuilding the library | - * - *
- * Revision History of CMSIS-DSP - * ------------ - * Please refer to \ref ChangeLog_pg. - * - * Copyright Notice - * ------------ - * - * Copyright (C) 2010-2015 Arm Limited. All rights reserved. - */ - - -/** - * @defgroup groupMath Basic Math Functions - */ - -/** - * @defgroup groupFastMath Fast Math Functions - * This set of functions provides a fast approximation to sine, cosine, and square root. - * As compared to most of the other functions in the CMSIS math library, the fast math functions - * operate on individual values and not arrays. - * There are separate functions for Q15, Q31, and floating-point data. - * - */ - -/** - * @defgroup groupCmplxMath Complex Math Functions - * This set of functions operates on complex data vectors. - * The data in the complex arrays is stored in an interleaved fashion - * (real, imag, real, imag, ...). - * In the API functions, the number of samples in a complex array refers - * to the number of complex values; the array contains twice this number of - * real values. - */ - -/** - * @defgroup groupFilters Filtering Functions - */ - -/** - * @defgroup groupMatrix Matrix Functions - * - * This set of functions provides basic matrix math operations. - * The functions operate on matrix data structures. For example, - * the type - * definition for the floating-point matrix structure is shown - * below: - * 
- *     typedef struct
- *     {
- *       uint16_t numRows;     // number of rows of the matrix.
- *       uint16_t numCols;     // number of columns of the matrix.
- *       float32_t *pData;     // points to the data of the matrix.
- *     } arm_matrix_instance_f32;
- *
- * There are similar definitions for Q15 and Q31 data types. - * - * The structure specifies the size of the matrix and then points to - * an array of data. The array is of size numRows X numCols - * and the values are arranged in row order. That is, the - * matrix element (i, j) is stored at: - * 
- *     pData[i*numCols + j]
- *
- * - * \par Init Functions - * There is an associated initialization function for each type of matrix - * data structure. - * The initialization function sets the values of the internal structure fields. - * Refer to the function arm_mat_init_f32(), arm_mat_init_q31() - * and arm_mat_init_q15() for floating-point, Q31 and Q15 types, respectively. - * - * \par - * Use of the initialization function is optional. However, if initialization function is used - * then the instance structure cannot be placed into a const data section. - * To place the instance structure in a const data - * section, manually initialize the data structure. For example: - * 
- * arm_matrix_instance_f32 S = {nRows, nColumns, pData};
- * arm_matrix_instance_q31 S = {nRows, nColumns, pData};
- * arm_matrix_instance_q15 S = {nRows, nColumns, pData};
- *
- * where nRows specifies the number of rows, nColumns - * specifies the number of columns, and pData points to the - * data array. - * - * \par Size Checking - * By default all of the matrix functions perform size checking on the input and - * output matrices. For example, the matrix addition function verifies that the - * two input matrices and the output matrix all have the same number of rows and - * columns. If the size check fails the functions return: - * 
- *     ARM_MATH_SIZE_MISMATCH
- *
- * Otherwise the functions return - * 
- *     ARM_MATH_SUCCESS
- *
- * There is some overhead associated with this matrix size checking. - * The matrix size checking is enabled via the \#define - * 
- *     ARM_MATH_MATRIX_CHECK
- *
- * within the library project settings. By default this macro is defined - * and size checking is enabled. By changing the project settings and - * undefining this macro size checking is eliminated and the functions - * run a bit faster. With size checking disabled the functions always - * return ARM_MATH_SUCCESS. - */ - -/** - * @defgroup groupTransforms Transform Functions - */ - -/** - * @defgroup groupController Controller Functions - */ - -/** - * @defgroup groupStats Statistics Functions - */ -/** - * @defgroup groupSupport Support Functions - */ - -/** - * @defgroup groupInterpolation Interpolation Functions - * These functions perform 1- and 2-dimensional interpolation of data. - * Linear interpolation is used for 1-dimensional data and - * bilinear interpolation is used for 2-dimensional data. - */ - -/** - * @defgroup groupExamples Examples - */ -#ifndef _ARM_MATH_H -#define _ARM_MATH_H - -/* Compiler specific diagnostic adjustment */ -#if defined ( __CC_ARM ) - -#elif defined ( __ARMCC_VERSION ) && ( __ARMCC_VERSION >= 6010050 ) - -#elif defined ( __GNUC__ ) -#pragma GCC diagnostic push -#pragma GCC diagnostic ignored "-Wsign-conversion" -#pragma GCC diagnostic ignored "-Wconversion" -#pragma GCC diagnostic ignored "-Wunused-parameter" - -#elif defined ( __ICCARM__ ) - -#elif defined ( __TI_ARM__ ) - -#elif defined ( __CSMC__ ) - -#elif defined ( __TASKING__ ) - -#else - #error Unknown compiler -#endif - - -#define __CMSIS_GENERIC /* disable NVIC and Systick functions */ - -#if defined(ARM_MATH_CM7) - #include "core_cm7.h" - #define ARM_MATH_DSP -#elif defined (ARM_MATH_CM4) - #include "core_cm4.h" - #define ARM_MATH_DSP -#elif defined (ARM_MATH_CM3) - #include "core_cm3.h" -#elif defined (ARM_MATH_CM0) - #include "core_cm0.h" - #define ARM_MATH_CM0_FAMILY -#elif defined (ARM_MATH_CM0PLUS) - #include "core_cm0plus.h" - #define ARM_MATH_CM0_FAMILY -#elif defined (ARM_MATH_ARMV8MBL) - #include "core_armv8mbl.h" - #define ARM_MATH_CM0_FAMILY -#elif defined (ARM_MATH_ARMV8MML) - #include "core_armv8mml.h" - #if (defined (__DSP_PRESENT) && (__DSP_PRESENT == 1)) - #define ARM_MATH_DSP - #endif -#else - #error "Define according the used Cortex core ARM_MATH_CM7, ARM_MATH_CM4, ARM_MATH_CM3, ARM_MATH_CM0PLUS, ARM_MATH_CM0, ARM_MATH_ARMV8MBL, ARM_MATH_ARMV8MML" -#endif - -#undef __CMSIS_GENERIC /* enable NVIC and Systick functions */ -#include "string.h" -#include "math.h" -#ifdef __cplusplus -extern "C" -{ -#endif - - - /** - * @brief Macros required for reciprocal calculation in Normalized LMS - */ - -#define DELTA_Q31 (0x100) -#define DELTA_Q15 0x5 -#define INDEX_MASK 0x0000003F -#ifndef PI - #define PI 3.14159265358979f -#endif - - /** - * @brief Macros required for SINE and COSINE Fast math approximations - */ - -#define FAST_MATH_TABLE_SIZE 512 -#define FAST_MATH_Q31_SHIFT (32 - 10) -#define FAST_MATH_Q15_SHIFT (16 - 10) -#define CONTROLLER_Q31_SHIFT (32 - 9) -#define TABLE_SPACING_Q31 0x400000 -#define TABLE_SPACING_Q15 0x80 - - /** - * @brief Macros required for SINE and COSINE Controller functions - */ - /* 1.31(q31) Fixed value of 2/360 */ - /* -1 to +1 is divided into 360 values so total spacing is (2/360) */ -#define INPUT_SPACING 0xB60B61 - - /** - * @brief Macro for Unaligned Support - */ -#ifndef UNALIGNED_SUPPORT_DISABLE - #define ALIGN4 -#else - #if defined (__GNUC__) - #define ALIGN4 __attribute__((aligned(4))) - #else - #define ALIGN4 __align(4) - #endif -#endif /* #ifndef UNALIGNED_SUPPORT_DISABLE */ - - /** - * @brief Error status returned by some functions in the library. - */ - - typedef enum - { - ARM_MATH_SUCCESS = 0, /**< No error */ - ARM_MATH_ARGUMENT_ERROR = -1, /**< One or more arguments are incorrect */ - ARM_MATH_LENGTH_ERROR = -2, /**< Length of data buffer is incorrect */ - ARM_MATH_SIZE_MISMATCH = -3, /**< Size of matrices is not compatible with the operation. */ - ARM_MATH_NANINF = -4, /**< Not-a-number (NaN) or infinity is generated */ - ARM_MATH_SINGULAR = -5, /**< Generated by matrix inversion if the input matrix is singular and cannot be inverted. */ - ARM_MATH_TEST_FAILURE = -6 /**< Test Failed */ - } arm_status; - - /** - * @brief 8-bit fractional data type in 1.7 format. - */ - typedef int8_t q7_t; - - /** - * @brief 16-bit fractional data type in 1.15 format. - */ - typedef int16_t q15_t; - - /** - * @brief 32-bit fractional data type in 1.31 format. - */ - typedef int32_t q31_t; - - /** - * @brief 64-bit fractional data type in 1.63 format. - */ - typedef int64_t q63_t; - - /** - * @brief 32-bit floating-point type definition. - */ - typedef float float32_t; - - /** - * @brief 64-bit floating-point type definition. - */ - typedef double float64_t; - - /** - * @brief definition to read/write two 16 bit values. - */ -#if defined ( __CC_ARM ) - #define __SIMD32_TYPE int32_t __packed - #define CMSIS_UNUSED __attribute__((unused)) - #define CMSIS_INLINE __attribute__((always_inline)) - -#elif defined ( __ARMCC_VERSION ) && ( __ARMCC_VERSION >= 6010050 ) - #define __SIMD32_TYPE int32_t - #define CMSIS_UNUSED __attribute__((unused)) - #define CMSIS_INLINE __attribute__((always_inline)) - -#elif defined ( __GNUC__ ) - #define __SIMD32_TYPE int32_t - #define CMSIS_UNUSED __attribute__((unused)) - #define CMSIS_INLINE __attribute__((always_inline)) - -#elif defined ( __ICCARM__ ) - #define __SIMD32_TYPE int32_t __packed - #define CMSIS_UNUSED - #define CMSIS_INLINE - -#elif defined ( __TI_ARM__ ) - #define __SIMD32_TYPE int32_t - #define CMSIS_UNUSED __attribute__((unused)) - #define CMSIS_INLINE - -#elif defined ( __CSMC__ ) - #define __SIMD32_TYPE int32_t - #define CMSIS_UNUSED - #define CMSIS_INLINE - -#elif defined ( __TASKING__ ) - #define __SIMD32_TYPE __unaligned int32_t - #define CMSIS_UNUSED - #define CMSIS_INLINE - -#else - #error Unknown compiler -#endif - -#define __SIMD32(addr) (*(__SIMD32_TYPE **) & (addr)) -#define __SIMD32_CONST(addr) ((__SIMD32_TYPE *)(addr)) -#define _SIMD32_OFFSET(addr) (*(__SIMD32_TYPE *) (addr)) -#define __SIMD64(addr) (*(int64_t **) & (addr)) - -#if !defined (ARM_MATH_DSP) - /** - * @brief definition to pack two 16 bit values. - */ -#define __PKHBT(ARG1, ARG2, ARG3) ( (((int32_t)(ARG1) << 0) & (int32_t)0x0000FFFF) | \ - (((int32_t)(ARG2) << ARG3) & (int32_t)0xFFFF0000) ) -#define __PKHTB(ARG1, ARG2, ARG3) ( (((int32_t)(ARG1) << 0) & (int32_t)0xFFFF0000) | \ - (((int32_t)(ARG2) >> ARG3) & (int32_t)0x0000FFFF) ) - -#endif /* !defined (ARM_MATH_DSP) */ - - /** - * @brief definition to pack four 8 bit values. - */ -#ifndef ARM_MATH_BIG_ENDIAN - -#define __PACKq7(v0,v1,v2,v3) ( (((int32_t)(v0) << 0) & (int32_t)0x000000FF) | \ - (((int32_t)(v1) << 8) & (int32_t)0x0000FF00) | \ - (((int32_t)(v2) << 16) & (int32_t)0x00FF0000) | \ - (((int32_t)(v3) << 24) & (int32_t)0xFF000000) ) -#else - -#define __PACKq7(v0,v1,v2,v3) ( (((int32_t)(v3) << 0) & (int32_t)0x000000FF) | \ - (((int32_t)(v2) << 8) & (int32_t)0x0000FF00) | \ - (((int32_t)(v1) << 16) & (int32_t)0x00FF0000) | \ - (((int32_t)(v0) << 24) & (int32_t)0xFF000000) ) - -#endif - - - /** - * @brief Clips Q63 to Q31 values. - */ - CMSIS_INLINE __STATIC_INLINE q31_t clip_q63_to_q31( - q63_t x) - { - return ((q31_t) (x >> 32) != ((q31_t) x >> 31)) ? - ((0x7FFFFFFF ^ ((q31_t) (x >> 63)))) : (q31_t) x; - } - - /** - * @brief Clips Q63 to Q15 values. - */ - CMSIS_INLINE __STATIC_INLINE q15_t clip_q63_to_q15( - q63_t x) - { - return ((q31_t) (x >> 32) != ((q31_t) x >> 31)) ? - ((0x7FFF ^ ((q15_t) (x >> 63)))) : (q15_t) (x >> 15); - } - - /** - * @brief Clips Q31 to Q7 values. - */ - CMSIS_INLINE __STATIC_INLINE q7_t clip_q31_to_q7( - q31_t x) - { - return ((q31_t) (x >> 24) != ((q31_t) x >> 23)) ? - ((0x7F ^ ((q7_t) (x >> 31)))) : (q7_t) x; - } - - /** - * @brief Clips Q31 to Q15 values. - */ - CMSIS_INLINE __STATIC_INLINE q15_t clip_q31_to_q15( - q31_t x) - { - return ((q31_t) (x >> 16) != ((q31_t) x >> 15)) ? - ((0x7FFF ^ ((q15_t) (x >> 31)))) : (q15_t) x; - } - - /** - * @brief Multiplies 32 X 64 and returns 32 bit result in 2.30 format. - */ - - CMSIS_INLINE __STATIC_INLINE q63_t mult32x64( - q63_t x, - q31_t y) - { - return ((((q63_t) (x & 0x00000000FFFFFFFF) * y) >> 32) + - (((q63_t) (x >> 32) * y))); - } - - /** - * @brief Function to Calculates 1/in (reciprocal) value of Q31 Data type. - */ - - CMSIS_INLINE __STATIC_INLINE uint32_t arm_recip_q31( - q31_t in, - q31_t * dst, - q31_t * pRecipTable) - { - q31_t out; - uint32_t tempVal; - uint32_t index, i; - uint32_t signBits; - - if (in > 0) - { - signBits = ((uint32_t) (__CLZ( in) - 1)); - } - else - { - signBits = ((uint32_t) (__CLZ(-in) - 1)); - } - - /* Convert input sample to 1.31 format */ - in = (in << signBits); - - /* calculation of index for initial approximated Val */ - index = (uint32_t)(in >> 24); - index = (index & INDEX_MASK); - - /* 1.31 with exp 1 */ - out = pRecipTable[index]; - - /* calculation of reciprocal value */ - /* running approximation for two iterations */ - for (i = 0U; i < 2U; i++) - { - tempVal = (uint32_t) (((q63_t) in * out) >> 31); - tempVal = 0x7FFFFFFFu - tempVal; - /* 1.31 with exp 1 */ - /* out = (q31_t) (((q63_t) out * tempVal) >> 30); */ - out = clip_q63_to_q31(((q63_t) out * tempVal) >> 30); - } - - /* write output */ - *dst = out; - - /* return num of signbits of out = 1/in value */ - return (signBits + 1U); - } - - - /** - * @brief Function to Calculates 1/in (reciprocal) value of Q15 Data type. - */ - CMSIS_INLINE __STATIC_INLINE uint32_t arm_recip_q15( - q15_t in, - q15_t * dst, - q15_t * pRecipTable) - { - q15_t out = 0; - uint32_t tempVal = 0; - uint32_t index = 0, i = 0; - uint32_t signBits = 0; - - if (in > 0) - { - signBits = ((uint32_t)(__CLZ( in) - 17)); - } - else - { - signBits = ((uint32_t)(__CLZ(-in) - 17)); - } - - /* Convert input sample to 1.15 format */ - in = (in << signBits); - - /* calculation of index for initial approximated Val */ - index = (uint32_t)(in >> 8); - index = (index & INDEX_MASK); - - /* 1.15 with exp 1 */ - out = pRecipTable[index]; - - /* calculation of reciprocal value */ - /* running approximation for two iterations */ - for (i = 0U; i < 2U; i++) - { - tempVal = (uint32_t) (((q31_t) in * out) >> 15); - tempVal = 0x7FFFu - tempVal; - /* 1.15 with exp 1 */ - out = (q15_t) (((q31_t) out * tempVal) >> 14); - /* out = clip_q31_to_q15(((q31_t) out * tempVal) >> 14); */ - } - - /* write output */ - *dst = out; - - /* return num of signbits of out = 1/in value */ - return (signBits + 1); - } - - -/* - * @brief C custom defined intrinsic function for M3 and M0 processors - */ -#if !defined (ARM_MATH_DSP) - - /* - * @brief C custom defined QADD8 for M3 and M0 processors - */ - CMSIS_INLINE __STATIC_INLINE uint32_t __QADD8( - uint32_t x, - uint32_t y) - { - q31_t r, s, t, u; - - r = __SSAT(((((q31_t)x << 24) >> 24) + (((q31_t)y << 24) >> 24)), 8) & (int32_t)0x000000FF; - s = __SSAT(((((q31_t)x << 16) >> 24) + (((q31_t)y << 16) >> 24)), 8) & (int32_t)0x000000FF; - t = __SSAT(((((q31_t)x << 8) >> 24) + (((q31_t)y << 8) >> 24)), 8) & (int32_t)0x000000FF; - u = __SSAT(((((q31_t)x ) >> 24) + (((q31_t)y ) >> 24)), 8) & (int32_t)0x000000FF; - - return ((uint32_t)((u << 24) | (t << 16) | (s << 8) | (r ))); - } - - - /* - * @brief C custom defined QSUB8 for M3 and M0 processors - */ - CMSIS_INLINE __STATIC_INLINE uint32_t __QSUB8( - uint32_t x, - uint32_t y) - { - q31_t r, s, t, u; - - r = __SSAT(((((q31_t)x << 24) >> 24) - (((q31_t)y << 24) >> 24)), 8) & (int32_t)0x000000FF; - s = __SSAT(((((q31_t)x << 16) >> 24) - (((q31_t)y << 16) >> 24)), 8) & (int32_t)0x000000FF; - t = __SSAT(((((q31_t)x << 8) >> 24) - (((q31_t)y << 8) >> 24)), 8) & (int32_t)0x000000FF; - u = __SSAT(((((q31_t)x ) >> 24) - (((q31_t)y ) >> 24)), 8) & (int32_t)0x000000FF; - - return ((uint32_t)((u << 24) | (t << 16) | (s << 8) | (r ))); - } - - - /* - * @brief C custom defined QADD16 for M3 and M0 processors - */ - CMSIS_INLINE __STATIC_INLINE uint32_t __QADD16( - uint32_t x, - uint32_t y) - { -/* q31_t r, s; without initialisation 'arm_offset_q15 test' fails but 'intrinsic' tests pass! for armCC */ - q31_t r = 0, s = 0; - - r = __SSAT(((((q31_t)x << 16) >> 16) + (((q31_t)y << 16) >> 16)), 16) & (int32_t)0x0000FFFF; - s = __SSAT(((((q31_t)x ) >> 16) + (((q31_t)y ) >> 16)), 16) & (int32_t)0x0000FFFF; - - return ((uint32_t)((s << 16) | (r ))); - } - - - /* - * @brief C custom defined SHADD16 for M3 and M0 processors - */ - CMSIS_INLINE __STATIC_INLINE uint32_t __SHADD16( - uint32_t x, - uint32_t y) - { - q31_t r, s; - - r = (((((q31_t)x << 16) >> 16) + (((q31_t)y << 16) >> 16)) >> 1) & (int32_t)0x0000FFFF; - s = (((((q31_t)x ) >> 16) + (((q31_t)y ) >> 16)) >> 1) & (int32_t)0x0000FFFF; - - return ((uint32_t)((s << 16) | (r ))); - } - - - /* - * @brief C custom defined QSUB16 for M3 and M0 processors - */ - CMSIS_INLINE __STATIC_INLINE uint32_t __QSUB16( - uint32_t x, - uint32_t y) - { - q31_t r, s; - - r = __SSAT(((((q31_t)x << 16) >> 16) - (((q31_t)y << 16) >> 16)), 16) & (int32_t)0x0000FFFF; - s = __SSAT(((((q31_t)x ) >> 16) - (((q31_t)y ) >> 16)), 16) & (int32_t)0x0000FFFF; - - return ((uint32_t)((s << 16) | (r ))); - } - - - /* - * @brief C custom defined SHSUB16 for M3 and M0 processors - */ - CMSIS_INLINE __STATIC_INLINE uint32_t __SHSUB16( - uint32_t x, - uint32_t y) - { - q31_t r, s; - - r = (((((q31_t)x << 16) >> 16) - (((q31_t)y << 16) >> 16)) >> 1) & (int32_t)0x0000FFFF; - s = (((((q31_t)x ) >> 16) - (((q31_t)y ) >> 16)) >> 1) & (int32_t)0x0000FFFF; - - return ((uint32_t)((s << 16) | (r ))); - } - - - /* - * @brief C custom defined QASX for M3 and M0 processors - */ - CMSIS_INLINE __STATIC_INLINE uint32_t __QASX( - uint32_t x, - uint32_t y) - { - q31_t r, s; - - r = __SSAT(((((q31_t)x << 16) >> 16) - (((q31_t)y ) >> 16)), 16) & (int32_t)0x0000FFFF; - s = __SSAT(((((q31_t)x ) >> 16) + (((q31_t)y << 16) >> 16)), 16) & (int32_t)0x0000FFFF; - - return ((uint32_t)((s << 16) | (r ))); - } - - - /* - * @brief C custom defined SHASX for M3 and M0 processors - */ - CMSIS_INLINE __STATIC_INLINE uint32_t __SHASX( - uint32_t x, - uint32_t y) - { - q31_t r, s; - - r = (((((q31_t)x << 16) >> 16) - (((q31_t)y ) >> 16)) >> 1) & (int32_t)0x0000FFFF; - s = (((((q31_t)x ) >> 16) + (((q31_t)y << 16) >> 16)) >> 1) & (int32_t)0x0000FFFF; - - return ((uint32_t)((s << 16) | (r ))); - } - - - /* - * @brief C custom defined QSAX for M3 and M0 processors - */ - CMSIS_INLINE __STATIC_INLINE uint32_t __QSAX( - uint32_t x, - uint32_t y) - { - q31_t r, s; - - r = __SSAT(((((q31_t)x << 16) >> 16) + (((q31_t)y ) >> 16)), 16) & (int32_t)0x0000FFFF; - s = __SSAT(((((q31_t)x ) >> 16) - (((q31_t)y << 16) >> 16)), 16) & (int32_t)0x0000FFFF; - - return ((uint32_t)((s << 16) | (r ))); - } - - - /* - * @brief C custom defined SHSAX for M3 and M0 processors - */ - CMSIS_INLINE __STATIC_INLINE uint32_t __SHSAX( - uint32_t x, - uint32_t y) - { - q31_t r, s; - - r = (((((q31_t)x << 16) >> 16) + (((q31_t)y ) >> 16)) >> 1) & (int32_t)0x0000FFFF; - s = (((((q31_t)x ) >> 16) - (((q31_t)y << 16) >> 16)) >> 1) & (int32_t)0x0000FFFF; - - return ((uint32_t)((s << 16) | (r ))); - } - - - /* - * @brief C custom defined SMUSDX for M3 and M0 processors - */ - CMSIS_INLINE __STATIC_INLINE uint32_t __SMUSDX( - uint32_t x, - uint32_t y) - { - return ((uint32_t)(((((q31_t)x << 16) >> 16) * (((q31_t)y ) >> 16)) - - ((((q31_t)x ) >> 16) * (((q31_t)y << 16) >> 16)) )); - } - - /* - * @brief C custom defined SMUADX for M3 and M0 processors - */ - CMSIS_INLINE __STATIC_INLINE uint32_t __SMUADX( - uint32_t x, - uint32_t y) - { - return ((uint32_t)(((((q31_t)x << 16) >> 16) * (((q31_t)y ) >> 16)) + - ((((q31_t)x ) >> 16) * (((q31_t)y << 16) >> 16)) )); - } - - - /* - * @brief C custom defined QADD for M3 and M0 processors - */ - CMSIS_INLINE __STATIC_INLINE int32_t __QADD( - int32_t x, - int32_t y) - { - return ((int32_t)(clip_q63_to_q31((q63_t)x + (q31_t)y))); - } - - - /* - * @brief C custom defined QSUB for M3 and M0 processors - */ - CMSIS_INLINE __STATIC_INLINE int32_t __QSUB( - int32_t x, - int32_t y) - { - return ((int32_t)(clip_q63_to_q31((q63_t)x - (q31_t)y))); - } - - - /* - * @brief C custom defined SMLAD for M3 and M0 processors - */ - CMSIS_INLINE __STATIC_INLINE uint32_t __SMLAD( - uint32_t x, - uint32_t y, - uint32_t sum) - { - return ((uint32_t)(((((q31_t)x << 16) >> 16) * (((q31_t)y << 16) >> 16)) + - ((((q31_t)x ) >> 16) * (((q31_t)y ) >> 16)) + - ( ((q31_t)sum ) ) )); - } - - - /* - * @brief C custom defined SMLADX for M3 and M0 processors - */ - CMSIS_INLINE __STATIC_INLINE uint32_t __SMLADX( - uint32_t x, - uint32_t y, - uint32_t sum) - { - return ((uint32_t)(((((q31_t)x << 16) >> 16) * (((q31_t)y ) >> 16)) + - ((((q31_t)x ) >> 16) * (((q31_t)y << 16) >> 16)) + - ( ((q31_t)sum ) ) )); - } - - - /* - * @brief C custom defined SMLSDX for M3 and M0 processors - */ - CMSIS_INLINE __STATIC_INLINE uint32_t __SMLSDX( - uint32_t x, - uint32_t y, - uint32_t sum) - { - return ((uint32_t)(((((q31_t)x << 16) >> 16) * (((q31_t)y ) >> 16)) - - ((((q31_t)x ) >> 16) * (((q31_t)y << 16) >> 16)) + - ( ((q31_t)sum ) ) )); - } - - - /* - * @brief C custom defined SMLALD for M3 and M0 processors - */ - CMSIS_INLINE __STATIC_INLINE uint64_t __SMLALD( - uint32_t x, - uint32_t y, - uint64_t sum) - { -/* return (sum + ((q15_t) (x >> 16) * (q15_t) (y >> 16)) + ((q15_t) x * (q15_t) y)); */ - return ((uint64_t)(((((q31_t)x << 16) >> 16) * (((q31_t)y << 16) >> 16)) + - ((((q31_t)x ) >> 16) * (((q31_t)y ) >> 16)) + - ( ((q63_t)sum ) ) )); - } - - - /* - * @brief C custom defined SMLALDX for M3 and M0 processors - */ - CMSIS_INLINE __STATIC_INLINE uint64_t __SMLALDX( - uint32_t x, - uint32_t y, - uint64_t sum) - { -/* return (sum + ((q15_t) (x >> 16) * (q15_t) y)) + ((q15_t) x * (q15_t) (y >> 16)); */ - return ((uint64_t)(((((q31_t)x << 16) >> 16) * (((q31_t)y ) >> 16)) + - ((((q31_t)x ) >> 16) * (((q31_t)y << 16) >> 16)) + - ( ((q63_t)sum ) ) )); - } - - - /* - * @brief C custom defined SMUAD for M3 and M0 processors - */ - CMSIS_INLINE __STATIC_INLINE uint32_t __SMUAD( - uint32_t x, - uint32_t y) - { - return ((uint32_t)(((((q31_t)x << 16) >> 16) * (((q31_t)y << 16) >> 16)) + - ((((q31_t)x ) >> 16) * (((q31_t)y ) >> 16)) )); - } - - - /* - * @brief C custom defined SMUSD for M3 and M0 processors - */ - CMSIS_INLINE __STATIC_INLINE uint32_t __SMUSD( - uint32_t x, - uint32_t y) - { - return ((uint32_t)(((((q31_t)x << 16) >> 16) * (((q31_t)y << 16) >> 16)) - - ((((q31_t)x ) >> 16) * (((q31_t)y ) >> 16)) )); - } - - - /* - * @brief C custom defined SXTB16 for M3 and M0 processors - */ - CMSIS_INLINE __STATIC_INLINE uint32_t __SXTB16( - uint32_t x) - { - return ((uint32_t)(((((q31_t)x << 24) >> 24) & (q31_t)0x0000FFFF) | - ((((q31_t)x << 8) >> 8) & (q31_t)0xFFFF0000) )); - } - - /* - * @brief C custom defined SMMLA for M3 and M0 processors - */ - CMSIS_INLINE __STATIC_INLINE int32_t __SMMLA( - int32_t x, - int32_t y, - int32_t sum) - { - return (sum + (int32_t) (((int64_t) x * y) >> 32)); - } - -#endif /* !defined (ARM_MATH_DSP) */ - - - /** - * @brief Instance structure for the Q7 FIR filter. - */ - typedef struct - { - uint16_t numTaps; /**< number of filter coefficients in the filter. */ - q7_t *pState; /**< points to the state variable array. The array is of length numTaps+blockSize-1. */ - q7_t *pCoeffs; /**< points to the coefficient array. The array is of length numTaps.*/ - } arm_fir_instance_q7; - - /** - * @brief Instance structure for the Q15 FIR filter. - */ - typedef struct - { - uint16_t numTaps; /**< number of filter coefficients in the filter. */ - q15_t *pState; /**< points to the state variable array. The array is of length numTaps+blockSize-1. */ - q15_t *pCoeffs; /**< points to the coefficient array. The array is of length numTaps.*/ - } arm_fir_instance_q15; - - /** - * @brief Instance structure for the Q31 FIR filter. - */ - typedef struct - { - uint16_t numTaps; /**< number of filter coefficients in the filter. */ - q31_t *pState; /**< points to the state variable array. The array is of length numTaps+blockSize-1. */ - q31_t *pCoeffs; /**< points to the coefficient array. The array is of length numTaps. */ - } arm_fir_instance_q31; - - /** - * @brief Instance structure for the floating-point FIR filter. - */ - typedef struct - { - uint16_t numTaps; /**< number of filter coefficients in the filter. */ - float32_t *pState; /**< points to the state variable array. The array is of length numTaps+blockSize-1. */ - float32_t *pCoeffs; /**< points to the coefficient array. The array is of length numTaps. */ - } arm_fir_instance_f32; - - - /** - * @brief Processing function for the Q7 FIR filter. - * @param[in] S points to an instance of the Q7 FIR filter structure. - * @param[in] pSrc points to the block of input data. - * @param[out] pDst points to the block of output data. - * @param[in] blockSize number of samples to process. - */ - void arm_fir_q7( - const arm_fir_instance_q7 * S, - q7_t * pSrc, - q7_t * pDst, - uint32_t blockSize); - - - /** - * @brief Initialization function for the Q7 FIR filter. - * @param[in,out] S points to an instance of the Q7 FIR structure. - * @param[in] numTaps Number of filter coefficients in the filter. - * @param[in] pCoeffs points to the filter coefficients. - * @param[in] pState points to the state buffer. - * @param[in] blockSize number of samples that are processed. - */ - void arm_fir_init_q7( - arm_fir_instance_q7 * S, - uint16_t numTaps, - q7_t * pCoeffs, - q7_t * pState, - uint32_t blockSize); - - - /** - * @brief Processing function for the Q15 FIR filter. - * @param[in] S points to an instance of the Q15 FIR structure. - * @param[in] pSrc points to the block of input data. - * @param[out] pDst points to the block of output data. - * @param[in] blockSize number of samples to process. - */ - void arm_fir_q15( - const arm_fir_instance_q15 * S, - q15_t * pSrc, - q15_t * pDst, - uint32_t blockSize); - - - /** - * @brief Processing function for the fast Q15 FIR filter for Cortex-M3 and Cortex-M4. - * @param[in] S points to an instance of the Q15 FIR filter structure. - * @param[in] pSrc points to the block of input data. - * @param[out] pDst points to the block of output data. - * @param[in] blockSize number of samples to process. - */ - void arm_fir_fast_q15( - const arm_fir_instance_q15 * S, - q15_t * pSrc, - q15_t * pDst, - uint32_t blockSize); - - - /** - * @brief Initialization function for the Q15 FIR filter. - * @param[in,out] S points to an instance of the Q15 FIR filter structure. - * @param[in] numTaps Number of filter coefficients in the filter. Must be even and greater than or equal to 4. - * @param[in] pCoeffs points to the filter coefficients. - * @param[in] pState points to the state buffer. - * @param[in] blockSize number of samples that are processed at a time. - * @return The function returns ARM_MATH_SUCCESS if initialization was successful or ARM_MATH_ARGUMENT_ERROR if - * numTaps is not a supported value. - */ - arm_status arm_fir_init_q15( - arm_fir_instance_q15 * S, - uint16_t numTaps, - q15_t * pCoeffs, - q15_t * pState, - uint32_t blockSize); - - - /** - * @brief Processing function for the Q31 FIR filter. - * @param[in] S points to an instance of the Q31 FIR filter structure. - * @param[in] pSrc points to the block of input data. - * @param[out] pDst points to the block of output data. - * @param[in] blockSize number of samples to process. - */ - void arm_fir_q31( - const arm_fir_instance_q31 * S, - q31_t * pSrc, - q31_t * pDst, - uint32_t blockSize); - - - /** - * @brief Processing function for the fast Q31 FIR filter for Cortex-M3 and Cortex-M4. - * @param[in] S points to an instance of the Q31 FIR structure. - * @param[in] pSrc points to the block of input data. - * @param[out] pDst points to the block of output data. - * @param[in] blockSize number of samples to process. - */ - void arm_fir_fast_q31( - const arm_fir_instance_q31 * S, - q31_t * pSrc, - q31_t * pDst, - uint32_t blockSize); - - - /** - * @brief Initialization function for the Q31 FIR filter. - * @param[in,out] S points to an instance of the Q31 FIR structure. - * @param[in] numTaps Number of filter coefficients in the filter. - * @param[in] pCoeffs points to the filter coefficients. - * @param[in] pState points to the state buffer. - * @param[in] blockSize number of samples that are processed at a time. - */ - void arm_fir_init_q31( - arm_fir_instance_q31 * S, - uint16_t numTaps, - q31_t * pCoeffs, - q31_t * pState, - uint32_t blockSize); - - - /** - * @brief Processing function for the floating-point FIR filter. - * @param[in] S points to an instance of the floating-point FIR structure. - * @param[in] pSrc points to the block of input data. - * @param[out] pDst points to the block of output data. - * @param[in] blockSize number of samples to process. - */ - void arm_fir_f32( - const arm_fir_instance_f32 * S, - float32_t * pSrc, - float32_t * pDst, - uint32_t blockSize); - - - /** - * @brief Initialization function for the floating-point FIR filter. - * @param[in,out] S points to an instance of the floating-point FIR filter structure. - * @param[in] numTaps Number of filter coefficients in the filter. - * @param[in] pCoeffs points to the filter coefficients. - * @param[in] pState points to the state buffer. - * @param[in] blockSize number of samples that are processed at a time. - */ - void arm_fir_init_f32( - arm_fir_instance_f32 * S, - uint16_t numTaps, - float32_t * pCoeffs, - float32_t * pState, - uint32_t blockSize); - - - /** - * @brief Instance structure for the Q15 Biquad cascade filter. - */ - typedef struct - { - int8_t numStages; /**< number of 2nd order stages in the filter. Overall order is 2*numStages. */ - q15_t *pState; /**< Points to the array of state coefficients. The array is of length 4*numStages. */ - q15_t *pCoeffs; /**< Points to the array of coefficients. The array is of length 5*numStages. */ - int8_t postShift; /**< Additional shift, in bits, applied to each output sample. */ - } arm_biquad_casd_df1_inst_q15; - - /** - * @brief Instance structure for the Q31 Biquad cascade filter. - */ - typedef struct - { - uint32_t numStages; /**< number of 2nd order stages in the filter. Overall order is 2*numStages. */ - q31_t *pState; /**< Points to the array of state coefficients. The array is of length 4*numStages. */ - q31_t *pCoeffs; /**< Points to the array of coefficients. The array is of length 5*numStages. */ - uint8_t postShift; /**< Additional shift, in bits, applied to each output sample. */ - } arm_biquad_casd_df1_inst_q31; - - /** - * @brief Instance structure for the floating-point Biquad cascade filter. - */ - typedef struct - { - uint32_t numStages; /**< number of 2nd order stages in the filter. Overall order is 2*numStages. */ - float32_t *pState; /**< Points to the array of state coefficients. The array is of length 4*numStages. */ - float32_t *pCoeffs; /**< Points to the array of coefficients. The array is of length 5*numStages. */ - } arm_biquad_casd_df1_inst_f32; - - - /** - * @brief Processing function for the Q15 Biquad cascade filter. - * @param[in] S points to an instance of the Q15 Biquad cascade structure. - * @param[in] pSrc points to the block of input data. - * @param[out] pDst points to the block of output data. - * @param[in] blockSize number of samples to process. - */ - void arm_biquad_cascade_df1_q15( - const arm_biquad_casd_df1_inst_q15 * S, - q15_t * pSrc, - q15_t * pDst, - uint32_t blockSize); - - - /** - * @brief Initialization function for the Q15 Biquad cascade filter. - * @param[in,out] S points to an instance of the Q15 Biquad cascade structure. - * @param[in] numStages number of 2nd order stages in the filter. - * @param[in] pCoeffs points to the filter coefficients. - * @param[in] pState points to the state buffer. - * @param[in] postShift Shift to be applied to the output. Varies according to the coefficients format - */ - void arm_biquad_cascade_df1_init_q15( - arm_biquad_casd_df1_inst_q15 * S, - uint8_t numStages, - q15_t * pCoeffs, - q15_t * pState, - int8_t postShift); - - - /** - * @brief Fast but less precise processing function for the Q15 Biquad cascade filter for Cortex-M3 and Cortex-M4. - * @param[in] S points to an instance of the Q15 Biquad cascade structure. - * @param[in] pSrc points to the block of input data. - * @param[out] pDst points to the block of output data. - * @param[in] blockSize number of samples to process. - */ - void arm_biquad_cascade_df1_fast_q15( - const arm_biquad_casd_df1_inst_q15 * S, - q15_t * pSrc, - q15_t * pDst, - uint32_t blockSize); - - - /** - * @brief Processing function for the Q31 Biquad cascade filter - * @param[in] S points to an instance of the Q31 Biquad cascade structure. - * @param[in] pSrc points to the block of input data. - * @param[out] pDst points to the block of output data. - * @param[in] blockSize number of samples to process. - */ - void arm_biquad_cascade_df1_q31( - const arm_biquad_casd_df1_inst_q31 * S, - q31_t * pSrc, - q31_t * pDst, - uint32_t blockSize); - - - /** - * @brief Fast but less precise processing function for the Q31 Biquad cascade filter for Cortex-M3 and Cortex-M4. - * @param[in] S points to an instance of the Q31 Biquad cascade structure. - * @param[in] pSrc points to the block of input data. - * @param[out] pDst points to the block of output data. - * @param[in] blockSize number of samples to process. - */ - void arm_biquad_cascade_df1_fast_q31( - const arm_biquad_casd_df1_inst_q31 * S, - q31_t * pSrc, - q31_t * pDst, - uint32_t blockSize); - - - /** - * @brief Initialization function for the Q31 Biquad cascade filter. - * @param[in,out] S points to an instance of the Q31 Biquad cascade structure. - * @param[in] numStages number of 2nd order stages in the filter. - * @param[in] pCoeffs points to the filter coefficients. - * @param[in] pState points to the state buffer. - * @param[in] postShift Shift to be applied to the output. Varies according to the coefficients format - */ - void arm_biquad_cascade_df1_init_q31( - arm_biquad_casd_df1_inst_q31 * S, - uint8_t numStages, - q31_t * pCoeffs, - q31_t * pState, - int8_t postShift); - - - /** - * @brief Processing function for the floating-point Biquad cascade filter. - * @param[in] S points to an instance of the floating-point Biquad cascade structure. - * @param[in] pSrc points to the block of input data. - * @param[out] pDst points to the block of output data. - * @param[in] blockSize number of samples to process. - */ - void arm_biquad_cascade_df1_f32( - const arm_biquad_casd_df1_inst_f32 * S, - float32_t * pSrc, - float32_t * pDst, - uint32_t blockSize); - - - /** - * @brief Initialization function for the floating-point Biquad cascade filter. - * @param[in,out] S points to an instance of the floating-point Biquad cascade structure. - * @param[in] numStages number of 2nd order stages in the filter. - * @param[in] pCoeffs points to the filter coefficients. - * @param[in] pState points to the state buffer. - */ - void arm_biquad_cascade_df1_init_f32( - arm_biquad_casd_df1_inst_f32 * S, - uint8_t numStages, - float32_t * pCoeffs, - float32_t * pState); - - - /** - * @brief Instance structure for the floating-point matrix structure. - */ - typedef struct - { - uint16_t numRows; /**< number of rows of the matrix. */ - uint16_t numCols; /**< number of columns of the matrix. */ - float32_t *pData; /**< points to the data of the matrix. */ - } arm_matrix_instance_f32; - - - /** - * @brief Instance structure for the floating-point matrix structure. - */ - typedef struct - { - uint16_t numRows; /**< number of rows of the matrix. */ - uint16_t numCols; /**< number of columns of the matrix. */ - float64_t *pData; /**< points to the data of the matrix. */ - } arm_matrix_instance_f64; - - /** - * @brief Instance structure for the Q15 matrix structure. - */ - typedef struct - { - uint16_t numRows; /**< number of rows of the matrix. */ - uint16_t numCols; /**< number of columns of the matrix. */ - q15_t *pData; /**< points to the data of the matrix. */ - } arm_matrix_instance_q15; - - /** - * @brief Instance structure for the Q31 matrix structure. - */ - typedef struct - { - uint16_t numRows; /**< number of rows of the matrix. */ - uint16_t numCols; /**< number of columns of the matrix. */ - q31_t *pData; /**< points to the data of the matrix. */ - } arm_matrix_instance_q31; - - - /** - * @brief Floating-point matrix addition. - * @param[in] pSrcA points to the first input matrix structure - * @param[in] pSrcB points to the second input matrix structure - * @param[out] pDst points to output matrix structure - * @return The function returns either - * ARM_MATH_SIZE_MISMATCH or ARM_MATH_SUCCESS based on the outcome of size checking. - */ - arm_status arm_mat_add_f32( - const arm_matrix_instance_f32 * pSrcA, - const arm_matrix_instance_f32 * pSrcB, - arm_matrix_instance_f32 * pDst); - - - /** - * @brief Q15 matrix addition. - * @param[in] pSrcA points to the first input matrix structure - * @param[in] pSrcB points to the second input matrix structure - * @param[out] pDst points to output matrix structure - * @return The function returns either - * ARM_MATH_SIZE_MISMATCH or ARM_MATH_SUCCESS based on the outcome of size checking. - */ - arm_status arm_mat_add_q15( - const arm_matrix_instance_q15 * pSrcA, - const arm_matrix_instance_q15 * pSrcB, - arm_matrix_instance_q15 * pDst); - - - /** - * @brief Q31 matrix addition. - * @param[in] pSrcA points to the first input matrix structure - * @param[in] pSrcB points to the second input matrix structure - * @param[out] pDst points to output matrix structure - * @return The function returns either - * ARM_MATH_SIZE_MISMATCH or ARM_MATH_SUCCESS based on the outcome of size checking. - */ - arm_status arm_mat_add_q31( - const arm_matrix_instance_q31 * pSrcA, - const arm_matrix_instance_q31 * pSrcB, - arm_matrix_instance_q31 * pDst); - - - /** - * @brief Floating-point, complex, matrix multiplication. - * @param[in] pSrcA points to the first input matrix structure - * @param[in] pSrcB points to the second input matrix structure - * @param[out] pDst points to output matrix structure - * @return The function returns either - * ARM_MATH_SIZE_MISMATCH or ARM_MATH_SUCCESS based on the outcome of size checking. - */ - arm_status arm_mat_cmplx_mult_f32( - const arm_matrix_instance_f32 * pSrcA, - const arm_matrix_instance_f32 * pSrcB, - arm_matrix_instance_f32 * pDst); - - - /** - * @brief Q15, complex, matrix multiplication. - * @param[in] pSrcA points to the first input matrix structure - * @param[in] pSrcB points to the second input matrix structure - * @param[out] pDst points to output matrix structure - * @return The function returns either - * ARM_MATH_SIZE_MISMATCH or ARM_MATH_SUCCESS based on the outcome of size checking. - */ - arm_status arm_mat_cmplx_mult_q15( - const arm_matrix_instance_q15 * pSrcA, - const arm_matrix_instance_q15 * pSrcB, - arm_matrix_instance_q15 * pDst, - q15_t * pScratch); - - - /** - * @brief Q31, complex, matrix multiplication. - * @param[in] pSrcA points to the first input matrix structure - * @param[in] pSrcB points to the second input matrix structure - * @param[out] pDst points to output matrix structure - * @return The function returns either - * ARM_MATH_SIZE_MISMATCH or ARM_MATH_SUCCESS based on the outcome of size checking. - */ - arm_status arm_mat_cmplx_mult_q31( - const arm_matrix_instance_q31 * pSrcA, - const arm_matrix_instance_q31 * pSrcB, - arm_matrix_instance_q31 * pDst); - - - /** - * @brief Floating-point matrix transpose. - * @param[in] pSrc points to the input matrix - * @param[out] pDst points to the output matrix - * @return The function returns either ARM_MATH_SIZE_MISMATCH - * or ARM_MATH_SUCCESS based on the outcome of size checking. - */ - arm_status arm_mat_trans_f32( - const arm_matrix_instance_f32 * pSrc, - arm_matrix_instance_f32 * pDst); - - - /** - * @brief Q15 matrix transpose. - * @param[in] pSrc points to the input matrix - * @param[out] pDst points to the output matrix - * @return The function returns either ARM_MATH_SIZE_MISMATCH - * or ARM_MATH_SUCCESS based on the outcome of size checking. - */ - arm_status arm_mat_trans_q15( - const arm_matrix_instance_q15 * pSrc, - arm_matrix_instance_q15 * pDst); - - - /** - * @brief Q31 matrix transpose. - * @param[in] pSrc points to the input matrix - * @param[out] pDst points to the output matrix - * @return The function returns either ARM_MATH_SIZE_MISMATCH - * or ARM_MATH_SUCCESS based on the outcome of size checking. - */ - arm_status arm_mat_trans_q31( - const arm_matrix_instance_q31 * pSrc, - arm_matrix_instance_q31 * pDst); - - - /** - * @brief Floating-point matrix multiplication - * @param[in] pSrcA points to the first input matrix structure - * @param[in] pSrcB points to the second input matrix structure - * @param[out] pDst points to output matrix structure - * @return The function returns either - * ARM_MATH_SIZE_MISMATCH or ARM_MATH_SUCCESS based on the outcome of size checking. - */ - arm_status arm_mat_mult_f32( - const arm_matrix_instance_f32 * pSrcA, - const arm_matrix_instance_f32 * pSrcB, - arm_matrix_instance_f32 * pDst); - - - /** - * @brief Q15 matrix multiplication - * @param[in] pSrcA points to the first input matrix structure - * @param[in] pSrcB points to the second input matrix structure - * @param[out] pDst points to output matrix structure - * @param[in] pState points to the array for storing intermediate results - * @return The function returns either - * ARM_MATH_SIZE_MISMATCH or ARM_MATH_SUCCESS based on the outcome of size checking. - */ - arm_status arm_mat_mult_q15( - const arm_matrix_instance_q15 * pSrcA, - const arm_matrix_instance_q15 * pSrcB, - arm_matrix_instance_q15 * pDst, - q15_t * pState); - - - /** - * @brief Q15 matrix multiplication (fast variant) for Cortex-M3 and Cortex-M4 - * @param[in] pSrcA points to the first input matrix structure - * @param[in] pSrcB points to the second input matrix structure - * @param[out] pDst points to output matrix structure - * @param[in] pState points to the array for storing intermediate results - * @return The function returns either - * ARM_MATH_SIZE_MISMATCH or ARM_MATH_SUCCESS based on the outcome of size checking. - */ - arm_status arm_mat_mult_fast_q15( - const arm_matrix_instance_q15 * pSrcA, - const arm_matrix_instance_q15 * pSrcB, - arm_matrix_instance_q15 * pDst, - q15_t * pState); - - - /** - * @brief Q31 matrix multiplication - * @param[in] pSrcA points to the first input matrix structure - * @param[in] pSrcB points to the second input matrix structure - * @param[out] pDst points to output matrix structure - * @return The function returns either - * ARM_MATH_SIZE_MISMATCH or ARM_MATH_SUCCESS based on the outcome of size checking. - */ - arm_status arm_mat_mult_q31( - const arm_matrix_instance_q31 * pSrcA, - const arm_matrix_instance_q31 * pSrcB, - arm_matrix_instance_q31 * pDst); - - - /** - * @brief Q31 matrix multiplication (fast variant) for Cortex-M3 and Cortex-M4 - * @param[in] pSrcA points to the first input matrix structure - * @param[in] pSrcB points to the second input matrix structure - * @param[out] pDst points to output matrix structure - * @return The function returns either - * ARM_MATH_SIZE_MISMATCH or ARM_MATH_SUCCESS based on the outcome of size checking. - */ - arm_status arm_mat_mult_fast_q31( - const arm_matrix_instance_q31 * pSrcA, - const arm_matrix_instance_q31 * pSrcB, - arm_matrix_instance_q31 * pDst); - - - /** - * @brief Floating-point matrix subtraction - * @param[in] pSrcA points to the first input matrix structure - * @param[in] pSrcB points to the second input matrix structure - * @param[out] pDst points to output matrix structure - * @return The function returns either - * ARM_MATH_SIZE_MISMATCH or ARM_MATH_SUCCESS based on the outcome of size checking. - */ - arm_status arm_mat_sub_f32( - const arm_matrix_instance_f32 * pSrcA, - const arm_matrix_instance_f32 * pSrcB, - arm_matrix_instance_f32 * pDst); - - - /** - * @brief Q15 matrix subtraction - * @param[in] pSrcA points to the first input matrix structure - * @param[in] pSrcB points to the second input matrix structure - * @param[out] pDst points to output matrix structure - * @return The function returns either - * ARM_MATH_SIZE_MISMATCH or ARM_MATH_SUCCESS based on the outcome of size checking. - */ - arm_status arm_mat_sub_q15( - const arm_matrix_instance_q15 * pSrcA, - const arm_matrix_instance_q15 * pSrcB, - arm_matrix_instance_q15 * pDst); - - - /** - * @brief Q31 matrix subtraction - * @param[in] pSrcA points to the first input matrix structure - * @param[in] pSrcB points to the second input matrix structure - * @param[out] pDst points to output matrix structure - * @return The function returns either - * ARM_MATH_SIZE_MISMATCH or ARM_MATH_SUCCESS based on the outcome of size checking. - */ - arm_status arm_mat_sub_q31( - const arm_matrix_instance_q31 * pSrcA, - const arm_matrix_instance_q31 * pSrcB, - arm_matrix_instance_q31 * pDst); - - - /** - * @brief Floating-point matrix scaling. - * @param[in] pSrc points to the input matrix - * @param[in] scale scale factor - * @param[out] pDst points to the output matrix - * @return The function returns either - * ARM_MATH_SIZE_MISMATCH or ARM_MATH_SUCCESS based on the outcome of size checking. - */ - arm_status arm_mat_scale_f32( - const arm_matrix_instance_f32 * pSrc, - float32_t scale, - arm_matrix_instance_f32 * pDst); - - - /** - * @brief Q15 matrix scaling. - * @param[in] pSrc points to input matrix - * @param[in] scaleFract fractional portion of the scale factor - * @param[in] shift number of bits to shift the result by - * @param[out] pDst points to output matrix - * @return The function returns either - * ARM_MATH_SIZE_MISMATCH or ARM_MATH_SUCCESS based on the outcome of size checking. - */ - arm_status arm_mat_scale_q15( - const arm_matrix_instance_q15 * pSrc, - q15_t scaleFract, - int32_t shift, - arm_matrix_instance_q15 * pDst); - - - /** - * @brief Q31 matrix scaling. - * @param[in] pSrc points to input matrix - * @param[in] scaleFract fractional portion of the scale factor - * @param[in] shift number of bits to shift the result by - * @param[out] pDst points to output matrix structure - * @return The function returns either - * ARM_MATH_SIZE_MISMATCH or ARM_MATH_SUCCESS based on the outcome of size checking. - */ - arm_status arm_mat_scale_q31( - const arm_matrix_instance_q31 * pSrc, - q31_t scaleFract, - int32_t shift, - arm_matrix_instance_q31 * pDst); - - - /** - * @brief Q31 matrix initialization. - * @param[in,out] S points to an instance of the floating-point matrix structure. - * @param[in] nRows number of rows in the matrix. - * @param[in] nColumns number of columns in the matrix. - * @param[in] pData points to the matrix data array. - */ - void arm_mat_init_q31( - arm_matrix_instance_q31 * S, - uint16_t nRows, - uint16_t nColumns, - q31_t * pData); - - - /** - * @brief Q15 matrix initialization. - * @param[in,out] S points to an instance of the floating-point matrix structure. - * @param[in] nRows number of rows in the matrix. - * @param[in] nColumns number of columns in the matrix. - * @param[in] pData points to the matrix data array. - */ - void arm_mat_init_q15( - arm_matrix_instance_q15 * S, - uint16_t nRows, - uint16_t nColumns, - q15_t * pData); - - - /** - * @brief Floating-point matrix initialization. - * @param[in,out] S points to an instance of the floating-point matrix structure. - * @param[in] nRows number of rows in the matrix. - * @param[in] nColumns number of columns in the matrix. - * @param[in] pData points to the matrix data array. - */ - void arm_mat_init_f32( - arm_matrix_instance_f32 * S, - uint16_t nRows, - uint16_t nColumns, - float32_t * pData); - - - - /** - * @brief Instance structure for the Q15 PID Control. - */ - typedef struct - { - q15_t A0; /**< The derived gain, A0 = Kp + Ki + Kd . */ -#if !defined (ARM_MATH_DSP) - q15_t A1; - q15_t A2; -#else - q31_t A1; /**< The derived gain A1 = -Kp - 2Kd | Kd.*/ -#endif - q15_t state[3]; /**< The state array of length 3. */ - q15_t Kp; /**< The proportional gain. */ - q15_t Ki; /**< The integral gain. */ - q15_t Kd; /**< The derivative gain. */ - } arm_pid_instance_q15; - - /** - * @brief Instance structure for the Q31 PID Control. - */ - typedef struct - { - q31_t A0; /**< The derived gain, A0 = Kp + Ki + Kd . */ - q31_t A1; /**< The derived gain, A1 = -Kp - 2Kd. */ - q31_t A2; /**< The derived gain, A2 = Kd . */ - q31_t state[3]; /**< The state array of length 3. */ - q31_t Kp; /**< The proportional gain. */ - q31_t Ki; /**< The integral gain. */ - q31_t Kd; /**< The derivative gain. */ - } arm_pid_instance_q31; - - /** - * @brief Instance structure for the floating-point PID Control. - */ - typedef struct - { - float32_t A0; /**< The derived gain, A0 = Kp + Ki + Kd . */ - float32_t A1; /**< The derived gain, A1 = -Kp - 2Kd. */ - float32_t A2; /**< The derived gain, A2 = Kd . */ - float32_t state[3]; /**< The state array of length 3. */ - float32_t Kp; /**< The proportional gain. */ - float32_t Ki; /**< The integral gain. */ - float32_t Kd; /**< The derivative gain. */ - } arm_pid_instance_f32; - - - - /** - * @brief Initialization function for the floating-point PID Control. - * @param[in,out] S points to an instance of the PID structure. - * @param[in] resetStateFlag flag to reset the state. 0 = no change in state 1 = reset the state. - */ - void arm_pid_init_f32( - arm_pid_instance_f32 * S, - int32_t resetStateFlag); - - - /** - * @brief Reset function for the floating-point PID Control. - * @param[in,out] S is an instance of the floating-point PID Control structure - */ - void arm_pid_reset_f32( - arm_pid_instance_f32 * S); - - - /** - * @brief Initialization function for the Q31 PID Control. - * @param[in,out] S points to an instance of the Q15 PID structure. - * @param[in] resetStateFlag flag to reset the state. 0 = no change in state 1 = reset the state. - */ - void arm_pid_init_q31( - arm_pid_instance_q31 * S, - int32_t resetStateFlag); - - - /** - * @brief Reset function for the Q31 PID Control. - * @param[in,out] S points to an instance of the Q31 PID Control structure - */ - - void arm_pid_reset_q31( - arm_pid_instance_q31 * S); - - - /** - * @brief Initialization function for the Q15 PID Control. - * @param[in,out] S points to an instance of the Q15 PID structure. - * @param[in] resetStateFlag flag to reset the state. 0 = no change in state 1 = reset the state. - */ - void arm_pid_init_q15( - arm_pid_instance_q15 * S, - int32_t resetStateFlag); - - - /** - * @brief Reset function for the Q15 PID Control. - * @param[in,out] S points to an instance of the q15 PID Control structure - */ - void arm_pid_reset_q15( - arm_pid_instance_q15 * S); - - - /** - * @brief Instance structure for the floating-point Linear Interpolate function. - */ - typedef struct - { - uint32_t nValues; /**< nValues */ - float32_t x1; /**< x1 */ - float32_t xSpacing; /**< xSpacing */ - float32_t *pYData; /**< pointer to the table of Y values */ - } arm_linear_interp_instance_f32; - - /** - * @brief Instance structure for the floating-point bilinear interpolation function. - */ - typedef struct - { - uint16_t numRows; /**< number of rows in the data table. */ - uint16_t numCols; /**< number of columns in the data table. */ - float32_t *pData; /**< points to the data table. */ - } arm_bilinear_interp_instance_f32; - - /** - * @brief Instance structure for the Q31 bilinear interpolation function. - */ - typedef struct - { - uint16_t numRows; /**< number of rows in the data table. */ - uint16_t numCols; /**< number of columns in the data table. */ - q31_t *pData; /**< points to the data table. */ - } arm_bilinear_interp_instance_q31; - - /** - * @brief Instance structure for the Q15 bilinear interpolation function. - */ - typedef struct - { - uint16_t numRows; /**< number of rows in the data table. */ - uint16_t numCols; /**< number of columns in the data table. */ - q15_t *pData; /**< points to the data table. */ - } arm_bilinear_interp_instance_q15; - - /** - * @brief Instance structure for the Q15 bilinear interpolation function. - */ - typedef struct - { - uint16_t numRows; /**< number of rows in the data table. */ - uint16_t numCols; /**< number of columns in the data table. */ - q7_t *pData; /**< points to the data table. */ - } arm_bilinear_interp_instance_q7; - - - /** - * @brief Q7 vector multiplication. - * @param[in] pSrcA points to the first input vector - * @param[in] pSrcB points to the second input vector - * @param[out] pDst points to the output vector - * @param[in] blockSize number of samples in each vector - */ - void arm_mult_q7( - q7_t * pSrcA, - q7_t * pSrcB, - q7_t * pDst, - uint32_t blockSize); - - - /** - * @brief Q15 vector multiplication. - * @param[in] pSrcA points to the first input vector - * @param[in] pSrcB points to the second input vector - * @param[out] pDst points to the output vector - * @param[in] blockSize number of samples in each vector - */ - void arm_mult_q15( - q15_t * pSrcA, - q15_t * pSrcB, - q15_t * pDst, - uint32_t blockSize); - - - /** - * @brief Q31 vector multiplication. - * @param[in] pSrcA points to the first input vector - * @param[in] pSrcB points to the second input vector - * @param[out] pDst points to the output vector - * @param[in] blockSize number of samples in each vector - */ - void arm_mult_q31( - q31_t * pSrcA, - q31_t * pSrcB, - q31_t * pDst, - uint32_t blockSize); - - - /** - * @brief Floating-point vector multiplication. - * @param[in] pSrcA points to the first input vector - * @param[in] pSrcB points to the second input vector - * @param[out] pDst points to the output vector - * @param[in] blockSize number of samples in each vector - */ - void arm_mult_f32( - float32_t * pSrcA, - float32_t * pSrcB, - float32_t * pDst, - uint32_t blockSize); - - - /** - * @brief Instance structure for the Q15 CFFT/CIFFT function. - */ - typedef struct - { - uint16_t fftLen; /**< length of the FFT. */ - uint8_t ifftFlag; /**< flag that selects forward (ifftFlag=0) or inverse (ifftFlag=1) transform. */ - uint8_t bitReverseFlag; /**< flag that enables (bitReverseFlag=1) or disables (bitReverseFlag=0) bit reversal of output. */ - q15_t *pTwiddle; /**< points to the Sin twiddle factor table. */ - uint16_t *pBitRevTable; /**< points to the bit reversal table. */ - uint16_t twidCoefModifier; /**< twiddle coefficient modifier that supports different size FFTs with the same twiddle factor table. */ - uint16_t bitRevFactor; /**< bit reversal modifier that supports different size FFTs with the same bit reversal table. */ - } arm_cfft_radix2_instance_q15; - -/* Deprecated */ - arm_status arm_cfft_radix2_init_q15( - arm_cfft_radix2_instance_q15 * S, - uint16_t fftLen, - uint8_t ifftFlag, - uint8_t bitReverseFlag); - -/* Deprecated */ - void arm_cfft_radix2_q15( - const arm_cfft_radix2_instance_q15 * S, - q15_t * pSrc); - - - /** - * @brief Instance structure for the Q15 CFFT/CIFFT function. - */ - typedef struct - { - uint16_t fftLen; /**< length of the FFT. */ - uint8_t ifftFlag; /**< flag that selects forward (ifftFlag=0) or inverse (ifftFlag=1) transform. */ - uint8_t bitReverseFlag; /**< flag that enables (bitReverseFlag=1) or disables (bitReverseFlag=0) bit reversal of output. */ - q15_t *pTwiddle; /**< points to the twiddle factor table. */ - uint16_t *pBitRevTable; /**< points to the bit reversal table. */ - uint16_t twidCoefModifier; /**< twiddle coefficient modifier that supports different size FFTs with the same twiddle factor table. */ - uint16_t bitRevFactor; /**< bit reversal modifier that supports different size FFTs with the same bit reversal table. */ - } arm_cfft_radix4_instance_q15; - -/* Deprecated */ - arm_status arm_cfft_radix4_init_q15( - arm_cfft_radix4_instance_q15 * S, - uint16_t fftLen, - uint8_t ifftFlag, - uint8_t bitReverseFlag); - -/* Deprecated */ - void arm_cfft_radix4_q15( - const arm_cfft_radix4_instance_q15 * S, - q15_t * pSrc); - - /** - * @brief Instance structure for the Radix-2 Q31 CFFT/CIFFT function. - */ - typedef struct - { - uint16_t fftLen; /**< length of the FFT. */ - uint8_t ifftFlag; /**< flag that selects forward (ifftFlag=0) or inverse (ifftFlag=1) transform. */ - uint8_t bitReverseFlag; /**< flag that enables (bitReverseFlag=1) or disables (bitReverseFlag=0) bit reversal of output. */ - q31_t *pTwiddle; /**< points to the Twiddle factor table. */ - uint16_t *pBitRevTable; /**< points to the bit reversal table. */ - uint16_t twidCoefModifier; /**< twiddle coefficient modifier that supports different size FFTs with the same twiddle factor table. */ - uint16_t bitRevFactor; /**< bit reversal modifier that supports different size FFTs with the same bit reversal table. */ - } arm_cfft_radix2_instance_q31; - -/* Deprecated */ - arm_status arm_cfft_radix2_init_q31( - arm_cfft_radix2_instance_q31 * S, - uint16_t fftLen, - uint8_t ifftFlag, - uint8_t bitReverseFlag); - -/* Deprecated */ - void arm_cfft_radix2_q31( - const arm_cfft_radix2_instance_q31 * S, - q31_t * pSrc); - - /** - * @brief Instance structure for the Q31 CFFT/CIFFT function. - */ - typedef struct - { - uint16_t fftLen; /**< length of the FFT. */ - uint8_t ifftFlag; /**< flag that selects forward (ifftFlag=0) or inverse (ifftFlag=1) transform. */ - uint8_t bitReverseFlag; /**< flag that enables (bitReverseFlag=1) or disables (bitReverseFlag=0) bit reversal of output. */ - q31_t *pTwiddle; /**< points to the twiddle factor table. */ - uint16_t *pBitRevTable; /**< points to the bit reversal table. */ - uint16_t twidCoefModifier; /**< twiddle coefficient modifier that supports different size FFTs with the same twiddle factor table. */ - uint16_t bitRevFactor; /**< bit reversal modifier that supports different size FFTs with the same bit reversal table. */ - } arm_cfft_radix4_instance_q31; - -/* Deprecated */ - void arm_cfft_radix4_q31( - const arm_cfft_radix4_instance_q31 * S, - q31_t * pSrc); - -/* Deprecated */ - arm_status arm_cfft_radix4_init_q31( - arm_cfft_radix4_instance_q31 * S, - uint16_t fftLen, - uint8_t ifftFlag, - uint8_t bitReverseFlag); - - /** - * @brief Instance structure for the floating-point CFFT/CIFFT function. - */ - typedef struct - { - uint16_t fftLen; /**< length of the FFT. */ - uint8_t ifftFlag; /**< flag that selects forward (ifftFlag=0) or inverse (ifftFlag=1) transform. */ - uint8_t bitReverseFlag; /**< flag that enables (bitReverseFlag=1) or disables (bitReverseFlag=0) bit reversal of output. */ - float32_t *pTwiddle; /**< points to the Twiddle factor table. */ - uint16_t *pBitRevTable; /**< points to the bit reversal table. */ - uint16_t twidCoefModifier; /**< twiddle coefficient modifier that supports different size FFTs with the same twiddle factor table. */ - uint16_t bitRevFactor; /**< bit reversal modifier that supports different size FFTs with the same bit reversal table. */ - float32_t onebyfftLen; /**< value of 1/fftLen. */ - } arm_cfft_radix2_instance_f32; - -/* Deprecated */ - arm_status arm_cfft_radix2_init_f32( - arm_cfft_radix2_instance_f32 * S, - uint16_t fftLen, - uint8_t ifftFlag, - uint8_t bitReverseFlag); - -/* Deprecated */ - void arm_cfft_radix2_f32( - const arm_cfft_radix2_instance_f32 * S, - float32_t * pSrc); - - /** - * @brief Instance structure for the floating-point CFFT/CIFFT function. - */ - typedef struct - { - uint16_t fftLen; /**< length of the FFT. */ - uint8_t ifftFlag; /**< flag that selects forward (ifftFlag=0) or inverse (ifftFlag=1) transform. */ - uint8_t bitReverseFlag; /**< flag that enables (bitReverseFlag=1) or disables (bitReverseFlag=0) bit reversal of output. */ - float32_t *pTwiddle; /**< points to the Twiddle factor table. */ - uint16_t *pBitRevTable; /**< points to the bit reversal table. */ - uint16_t twidCoefModifier; /**< twiddle coefficient modifier that supports different size FFTs with the same twiddle factor table. */ - uint16_t bitRevFactor; /**< bit reversal modifier that supports different size FFTs with the same bit reversal table. */ - float32_t onebyfftLen; /**< value of 1/fftLen. */ - } arm_cfft_radix4_instance_f32; - -/* Deprecated */ - arm_status arm_cfft_radix4_init_f32( - arm_cfft_radix4_instance_f32 * S, - uint16_t fftLen, - uint8_t ifftFlag, - uint8_t bitReverseFlag); - -/* Deprecated */ - void arm_cfft_radix4_f32( - const arm_cfft_radix4_instance_f32 * S, - float32_t * pSrc); - - /** - * @brief Instance structure for the fixed-point CFFT/CIFFT function. - */ - typedef struct - { - uint16_t fftLen; /**< length of the FFT. */ - const q15_t *pTwiddle; /**< points to the Twiddle factor table. */ - const uint16_t *pBitRevTable; /**< points to the bit reversal table. */ - uint16_t bitRevLength; /**< bit reversal table length. */ - } arm_cfft_instance_q15; - -void arm_cfft_q15( - const arm_cfft_instance_q15 * S, - q15_t * p1, - uint8_t ifftFlag, - uint8_t bitReverseFlag); - - /** - * @brief Instance structure for the fixed-point CFFT/CIFFT function. - */ - typedef struct - { - uint16_t fftLen; /**< length of the FFT. */ - const q31_t *pTwiddle; /**< points to the Twiddle factor table. */ - const uint16_t *pBitRevTable; /**< points to the bit reversal table. */ - uint16_t bitRevLength; /**< bit reversal table length. */ - } arm_cfft_instance_q31; - -void arm_cfft_q31( - const arm_cfft_instance_q31 * S, - q31_t * p1, - uint8_t ifftFlag, - uint8_t bitReverseFlag); - - /** - * @brief Instance structure for the floating-point CFFT/CIFFT function. - */ - typedef struct - { - uint16_t fftLen; /**< length of the FFT. */ - const float32_t *pTwiddle; /**< points to the Twiddle factor table. */ - const uint16_t *pBitRevTable; /**< points to the bit reversal table. */ - uint16_t bitRevLength; /**< bit reversal table length. */ - } arm_cfft_instance_f32; - - void arm_cfft_f32( - const arm_cfft_instance_f32 * S, - float32_t * p1, - uint8_t ifftFlag, - uint8_t bitReverseFlag); - - /** - * @brief Instance structure for the Q15 RFFT/RIFFT function. - */ - typedef struct - { - uint32_t fftLenReal; /**< length of the real FFT. */ - uint8_t ifftFlagR; /**< flag that selects forward (ifftFlagR=0) or inverse (ifftFlagR=1) transform. */ - uint8_t bitReverseFlagR; /**< flag that enables (bitReverseFlagR=1) or disables (bitReverseFlagR=0) bit reversal of output. */ - uint32_t twidCoefRModifier; /**< twiddle coefficient modifier that supports different size FFTs with the same twiddle factor table. */ - q15_t *pTwiddleAReal; /**< points to the real twiddle factor table. */ - q15_t *pTwiddleBReal; /**< points to the imag twiddle factor table. */ - const arm_cfft_instance_q15 *pCfft; /**< points to the complex FFT instance. */ - } arm_rfft_instance_q15; - - arm_status arm_rfft_init_q15( - arm_rfft_instance_q15 * S, - uint32_t fftLenReal, - uint32_t ifftFlagR, - uint32_t bitReverseFlag); - - void arm_rfft_q15( - const arm_rfft_instance_q15 * S, - q15_t * pSrc, - q15_t * pDst); - - /** - * @brief Instance structure for the Q31 RFFT/RIFFT function. - */ - typedef struct - { - uint32_t fftLenReal; /**< length of the real FFT. */ - uint8_t ifftFlagR; /**< flag that selects forward (ifftFlagR=0) or inverse (ifftFlagR=1) transform. */ - uint8_t bitReverseFlagR; /**< flag that enables (bitReverseFlagR=1) or disables (bitReverseFlagR=0) bit reversal of output. */ - uint32_t twidCoefRModifier; /**< twiddle coefficient modifier that supports different size FFTs with the same twiddle factor table. */ - q31_t *pTwiddleAReal; /**< points to the real twiddle factor table. */ - q31_t *pTwiddleBReal; /**< points to the imag twiddle factor table. */ - const arm_cfft_instance_q31 *pCfft; /**< points to the complex FFT instance. */ - } arm_rfft_instance_q31; - - arm_status arm_rfft_init_q31( - arm_rfft_instance_q31 * S, - uint32_t fftLenReal, - uint32_t ifftFlagR, - uint32_t bitReverseFlag); - - void arm_rfft_q31( - const arm_rfft_instance_q31 * S, - q31_t * pSrc, - q31_t * pDst); - - /** - * @brief Instance structure for the floating-point RFFT/RIFFT function. - */ - typedef struct - { - uint32_t fftLenReal; /**< length of the real FFT. */ - uint16_t fftLenBy2; /**< length of the complex FFT. */ - uint8_t ifftFlagR; /**< flag that selects forward (ifftFlagR=0) or inverse (ifftFlagR=1) transform. */ - uint8_t bitReverseFlagR; /**< flag that enables (bitReverseFlagR=1) or disables (bitReverseFlagR=0) bit reversal of output. */ - uint32_t twidCoefRModifier; /**< twiddle coefficient modifier that supports different size FFTs with the same twiddle factor table. */ - float32_t *pTwiddleAReal; /**< points to the real twiddle factor table. */ - float32_t *pTwiddleBReal; /**< points to the imag twiddle factor table. */ - arm_cfft_radix4_instance_f32 *pCfft; /**< points to the complex FFT instance. */ - } arm_rfft_instance_f32; - - arm_status arm_rfft_init_f32( - arm_rfft_instance_f32 * S, - arm_cfft_radix4_instance_f32 * S_CFFT, - uint32_t fftLenReal, - uint32_t ifftFlagR, - uint32_t bitReverseFlag); - - void arm_rfft_f32( - const arm_rfft_instance_f32 * S, - float32_t * pSrc, - float32_t * pDst); - - /** - * @brief Instance structure for the floating-point RFFT/RIFFT function. - */ -typedef struct - { - arm_cfft_instance_f32 Sint; /**< Internal CFFT structure. */ - uint16_t fftLenRFFT; /**< length of the real sequence */ - float32_t * pTwiddleRFFT; /**< Twiddle factors real stage */ - } arm_rfft_fast_instance_f32 ; - -arm_status arm_rfft_fast_init_f32 ( - arm_rfft_fast_instance_f32 * S, - uint16_t fftLen); - -void arm_rfft_fast_f32( - arm_rfft_fast_instance_f32 * S, - float32_t * p, float32_t * pOut, - uint8_t ifftFlag); - - /** - * @brief Instance structure for the floating-point DCT4/IDCT4 function. - */ - typedef struct - { - uint16_t N; /**< length of the DCT4. */ - uint16_t Nby2; /**< half of the length of the DCT4. */ - float32_t normalize; /**< normalizing factor. */ - float32_t *pTwiddle; /**< points to the twiddle factor table. */ - float32_t *pCosFactor; /**< points to the cosFactor table. */ - arm_rfft_instance_f32 *pRfft; /**< points to the real FFT instance. */ - arm_cfft_radix4_instance_f32 *pCfft; /**< points to the complex FFT instance. */ - } arm_dct4_instance_f32; - - - /** - * @brief Initialization function for the floating-point DCT4/IDCT4. - * @param[in,out] S points to an instance of floating-point DCT4/IDCT4 structure. - * @param[in] S_RFFT points to an instance of floating-point RFFT/RIFFT structure. - * @param[in] S_CFFT points to an instance of floating-point CFFT/CIFFT structure. - * @param[in] N length of the DCT4. - * @param[in] Nby2 half of the length of the DCT4. - * @param[in] normalize normalizing factor. - * @return arm_status function returns ARM_MATH_SUCCESS if initialization is successful or ARM_MATH_ARGUMENT_ERROR if fftLenReal is not a supported transform length. - */ - arm_status arm_dct4_init_f32( - arm_dct4_instance_f32 * S, - arm_rfft_instance_f32 * S_RFFT, - arm_cfft_radix4_instance_f32 * S_CFFT, - uint16_t N, - uint16_t Nby2, - float32_t normalize); - - - /** - * @brief Processing function for the floating-point DCT4/IDCT4. - * @param[in] S points to an instance of the floating-point DCT4/IDCT4 structure. - * @param[in] pState points to state buffer. - * @param[in,out] pInlineBuffer points to the in-place input and output buffer. - */ - void arm_dct4_f32( - const arm_dct4_instance_f32 * S, - float32_t * pState, - float32_t * pInlineBuffer); - - - /** - * @brief Instance structure for the Q31 DCT4/IDCT4 function. - */ - typedef struct - { - uint16_t N; /**< length of the DCT4. */ - uint16_t Nby2; /**< half of the length of the DCT4. */ - q31_t normalize; /**< normalizing factor. */ - q31_t *pTwiddle; /**< points to the twiddle factor table. */ - q31_t *pCosFactor; /**< points to the cosFactor table. */ - arm_rfft_instance_q31 *pRfft; /**< points to the real FFT instance. */ - arm_cfft_radix4_instance_q31 *pCfft; /**< points to the complex FFT instance. */ - } arm_dct4_instance_q31; - - - /** - * @brief Initialization function for the Q31 DCT4/IDCT4. - * @param[in,out] S points to an instance of Q31 DCT4/IDCT4 structure. - * @param[in] S_RFFT points to an instance of Q31 RFFT/RIFFT structure - * @param[in] S_CFFT points to an instance of Q31 CFFT/CIFFT structure - * @param[in] N length of the DCT4. - * @param[in] Nby2 half of the length of the DCT4. - * @param[in] normalize normalizing factor. - * @return arm_status function returns ARM_MATH_SUCCESS if initialization is successful or ARM_MATH_ARGUMENT_ERROR if N is not a supported transform length. - */ - arm_status arm_dct4_init_q31( - arm_dct4_instance_q31 * S, - arm_rfft_instance_q31 * S_RFFT, - arm_cfft_radix4_instance_q31 * S_CFFT, - uint16_t N, - uint16_t Nby2, - q31_t normalize); - - - /** - * @brief Processing function for the Q31 DCT4/IDCT4. - * @param[in] S points to an instance of the Q31 DCT4 structure. - * @param[in] pState points to state buffer. - * @param[in,out] pInlineBuffer points to the in-place input and output buffer. - */ - void arm_dct4_q31( - const arm_dct4_instance_q31 * S, - q31_t * pState, - q31_t * pInlineBuffer); - - - /** - * @brief Instance structure for the Q15 DCT4/IDCT4 function. - */ - typedef struct - { - uint16_t N; /**< length of the DCT4. */ - uint16_t Nby2; /**< half of the length of the DCT4. */ - q15_t normalize; /**< normalizing factor. */ - q15_t *pTwiddle; /**< points to the twiddle factor table. */ - q15_t *pCosFactor; /**< points to the cosFactor table. */ - arm_rfft_instance_q15 *pRfft; /**< points to the real FFT instance. */ - arm_cfft_radix4_instance_q15 *pCfft; /**< points to the complex FFT instance. */ - } arm_dct4_instance_q15; - - - /** - * @brief Initialization function for the Q15 DCT4/IDCT4. - * @param[in,out] S points to an instance of Q15 DCT4/IDCT4 structure. - * @param[in] S_RFFT points to an instance of Q15 RFFT/RIFFT structure. - * @param[in] S_CFFT points to an instance of Q15 CFFT/CIFFT structure. - * @param[in] N length of the DCT4. - * @param[in] Nby2 half of the length of the DCT4. - * @param[in] normalize normalizing factor. - * @return arm_status function returns ARM_MATH_SUCCESS if initialization is successful or ARM_MATH_ARGUMENT_ERROR if N is not a supported transform length. - */ - arm_status arm_dct4_init_q15( - arm_dct4_instance_q15 * S, - arm_rfft_instance_q15 * S_RFFT, - arm_cfft_radix4_instance_q15 * S_CFFT, - uint16_t N, - uint16_t Nby2, - q15_t normalize); - - - /** - * @brief Processing function for the Q15 DCT4/IDCT4. - * @param[in] S points to an instance of the Q15 DCT4 structure. - * @param[in] pState points to state buffer. - * @param[in,out] pInlineBuffer points to the in-place input and output buffer. - */ - void arm_dct4_q15( - const arm_dct4_instance_q15 * S, - q15_t * pState, - q15_t * pInlineBuffer); - - - /** - * @brief Floating-point vector addition. - * @param[in] pSrcA points to the first input vector - * @param[in] pSrcB points to the second input vector - * @param[out] pDst points to the output vector - * @param[in] blockSize number of samples in each vector - */ - void arm_add_f32( - float32_t * pSrcA, - float32_t * pSrcB, - float32_t * pDst, - uint32_t blockSize); - - - /** - * @brief Q7 vector addition. - * @param[in] pSrcA points to the first input vector - * @param[in] pSrcB points to the second input vector - * @param[out] pDst points to the output vector - * @param[in] blockSize number of samples in each vector - */ - void arm_add_q7( - q7_t * pSrcA, - q7_t * pSrcB, - q7_t * pDst, - uint32_t blockSize); - - - /** - * @brief Q15 vector addition. - * @param[in] pSrcA points to the first input vector - * @param[in] pSrcB points to the second input vector - * @param[out] pDst points to the output vector - * @param[in] blockSize number of samples in each vector - */ - void arm_add_q15( - q15_t * pSrcA, - q15_t * pSrcB, - q15_t * pDst, - uint32_t blockSize); - - - /** - * @brief Q31 vector addition. - * @param[in] pSrcA points to the first input vector - * @param[in] pSrcB points to the second input vector - * @param[out] pDst points to the output vector - * @param[in] blockSize number of samples in each vector - */ - void arm_add_q31( - q31_t * pSrcA, - q31_t * pSrcB, - q31_t * pDst, - uint32_t blockSize); - - - /** - * @brief Floating-point vector subtraction. - * @param[in] pSrcA points to the first input vector - * @param[in] pSrcB points to the second input vector - * @param[out] pDst points to the output vector - * @param[in] blockSize number of samples in each vector - */ - void arm_sub_f32( - float32_t * pSrcA, - float32_t * pSrcB, - float32_t * pDst, - uint32_t blockSize); - - - /** - * @brief Q7 vector subtraction. - * @param[in] pSrcA points to the first input vector - * @param[in] pSrcB points to the second input vector - * @param[out] pDst points to the output vector - * @param[in] blockSize number of samples in each vector - */ - void arm_sub_q7( - q7_t * pSrcA, - q7_t * pSrcB, - q7_t * pDst, - uint32_t blockSize); - - - /** - * @brief Q15 vector subtraction. - * @param[in] pSrcA points to the first input vector - * @param[in] pSrcB points to the second input vector - * @param[out] pDst points to the output vector - * @param[in] blockSize number of samples in each vector - */ - void arm_sub_q15( - q15_t * pSrcA, - q15_t * pSrcB, - q15_t * pDst, - uint32_t blockSize); - - - /** - * @brief Q31 vector subtraction. - * @param[in] pSrcA points to the first input vector - * @param[in] pSrcB points to the second input vector - * @param[out] pDst points to the output vector - * @param[in] blockSize number of samples in each vector - */ - void arm_sub_q31( - q31_t * pSrcA, - q31_t * pSrcB, - q31_t * pDst, - uint32_t blockSize); - - - /** - * @brief Multiplies a floating-point vector by a scalar. - * @param[in] pSrc points to the input vector - * @param[in] scale scale factor to be applied - * @param[out] pDst points to the output vector - * @param[in] blockSize number of samples in the vector - */ - void arm_scale_f32( - float32_t * pSrc, - float32_t scale, - float32_t * pDst, - uint32_t blockSize); - - - /** - * @brief Multiplies a Q7 vector by a scalar. - * @param[in] pSrc points to the input vector - * @param[in] scaleFract fractional portion of the scale value - * @param[in] shift number of bits to shift the result by - * @param[out] pDst points to the output vector - * @param[in] blockSize number of samples in the vector - */ - void arm_scale_q7( - q7_t * pSrc, - q7_t scaleFract, - int8_t shift, - q7_t * pDst, - uint32_t blockSize); - - - /** - * @brief Multiplies a Q15 vector by a scalar. - * @param[in] pSrc points to the input vector - * @param[in] scaleFract fractional portion of the scale value - * @param[in] shift number of bits to shift the result by - * @param[out] pDst points to the output vector - * @param[in] blockSize number of samples in the vector - */ - void arm_scale_q15( - q15_t * pSrc, - q15_t scaleFract, - int8_t shift, - q15_t * pDst, - uint32_t blockSize); - - - /** - * @brief Multiplies a Q31 vector by a scalar. - * @param[in] pSrc points to the input vector - * @param[in] scaleFract fractional portion of the scale value - * @param[in] shift number of bits to shift the result by - * @param[out] pDst points to the output vector - * @param[in] blockSize number of samples in the vector - */ - void arm_scale_q31( - q31_t * pSrc, - q31_t scaleFract, - int8_t shift, - q31_t * pDst, - uint32_t blockSize); - - - /** - * @brief Q7 vector absolute value. - * @param[in] pSrc points to the input buffer - * @param[out] pDst points to the output buffer - * @param[in] blockSize number of samples in each vector - */ - void arm_abs_q7( - q7_t * pSrc, - q7_t * pDst, - uint32_t blockSize); - - - /** - * @brief Floating-point vector absolute value. - * @param[in] pSrc points to the input buffer - * @param[out] pDst points to the output buffer - * @param[in] blockSize number of samples in each vector - */ - void arm_abs_f32( - float32_t * pSrc, - float32_t * pDst, - uint32_t blockSize); - - - /** - * @brief Q15 vector absolute value. - * @param[in] pSrc points to the input buffer - * @param[out] pDst points to the output buffer - * @param[in] blockSize number of samples in each vector - */ - void arm_abs_q15( - q15_t * pSrc, - q15_t * pDst, - uint32_t blockSize); - - - /** - * @brief Q31 vector absolute value. - * @param[in] pSrc points to the input buffer - * @param[out] pDst points to the output buffer - * @param[in] blockSize number of samples in each vector - */ - void arm_abs_q31( - q31_t * pSrc, - q31_t * pDst, - uint32_t blockSize); - - - /** - * @brief Dot product of floating-point vectors. - * @param[in] pSrcA points to the first input vector - * @param[in] pSrcB points to the second input vector - * @param[in] blockSize number of samples in each vector - * @param[out] result output result returned here - */ - void arm_dot_prod_f32( - float32_t * pSrcA, - float32_t * pSrcB, - uint32_t blockSize, - float32_t * result); - - - /** - * @brief Dot product of Q7 vectors. - * @param[in] pSrcA points to the first input vector - * @param[in] pSrcB points to the second input vector - * @param[in] blockSize number of samples in each vector - * @param[out] result output result returned here - */ - void arm_dot_prod_q7( - q7_t * pSrcA, - q7_t * pSrcB, - uint32_t blockSize, - q31_t * result); - - - /** - * @brief Dot product of Q15 vectors. - * @param[in] pSrcA points to the first input vector - * @param[in] pSrcB points to the second input vector - * @param[in] blockSize number of samples in each vector - * @param[out] result output result returned here - */ - void arm_dot_prod_q15( - q15_t * pSrcA, - q15_t * pSrcB, - uint32_t blockSize, - q63_t * result); - - - /** - * @brief Dot product of Q31 vectors. - * @param[in] pSrcA points to the first input vector - * @param[in] pSrcB points to the second input vector - * @param[in] blockSize number of samples in each vector - * @param[out] result output result returned here - */ - void arm_dot_prod_q31( - q31_t * pSrcA, - q31_t * pSrcB, - uint32_t blockSize, - q63_t * result); - - - /** - * @brief Shifts the elements of a Q7 vector a specified number of bits. - * @param[in] pSrc points to the input vector - * @param[in] shiftBits number of bits to shift. A positive value shifts left; a negative value shifts right. - * @param[out] pDst points to the output vector - * @param[in] blockSize number of samples in the vector - */ - void arm_shift_q7( - q7_t * pSrc, - int8_t shiftBits, - q7_t * pDst, - uint32_t blockSize); - - - /** - * @brief Shifts the elements of a Q15 vector a specified number of bits. - * @param[in] pSrc points to the input vector - * @param[in] shiftBits number of bits to shift. A positive value shifts left; a negative value shifts right. - * @param[out] pDst points to the output vector - * @param[in] blockSize number of samples in the vector - */ - void arm_shift_q15( - q15_t * pSrc, - int8_t shiftBits, - q15_t * pDst, - uint32_t blockSize); - - - /** - * @brief Shifts the elements of a Q31 vector a specified number of bits. - * @param[in] pSrc points to the input vector - * @param[in] shiftBits number of bits to shift. A positive value shifts left; a negative value shifts right. - * @param[out] pDst points to the output vector - * @param[in] blockSize number of samples in the vector - */ - void arm_shift_q31( - q31_t * pSrc, - int8_t shiftBits, - q31_t * pDst, - uint32_t blockSize); - - - /** - * @brief Adds a constant offset to a floating-point vector. - * @param[in] pSrc points to the input vector - * @param[in] offset is the offset to be added - * @param[out] pDst points to the output vector - * @param[in] blockSize number of samples in the vector - */ - void arm_offset_f32( - float32_t * pSrc, - float32_t offset, - float32_t * pDst, - uint32_t blockSize); - - - /** - * @brief Adds a constant offset to a Q7 vector. - * @param[in] pSrc points to the input vector - * @param[in] offset is the offset to be added - * @param[out] pDst points to the output vector - * @param[in] blockSize number of samples in the vector - */ - void arm_offset_q7( - q7_t * pSrc, - q7_t offset, - q7_t * pDst, - uint32_t blockSize); - - - /** - * @brief Adds a constant offset to a Q15 vector. - * @param[in] pSrc points to the input vector - * @param[in] offset is the offset to be added - * @param[out] pDst points to the output vector - * @param[in] blockSize number of samples in the vector - */ - void arm_offset_q15( - q15_t * pSrc, - q15_t offset, - q15_t * pDst, - uint32_t blockSize); - - - /** - * @brief Adds a constant offset to a Q31 vector. - * @param[in] pSrc points to the input vector - * @param[in] offset is the offset to be added - * @param[out] pDst points to the output vector - * @param[in] blockSize number of samples in the vector - */ - void arm_offset_q31( - q31_t * pSrc, - q31_t offset, - q31_t * pDst, - uint32_t blockSize); - - - /** - * @brief Negates the elements of a floating-point vector. - * @param[in] pSrc points to the input vector - * @param[out] pDst points to the output vector - * @param[in] blockSize number of samples in the vector - */ - void arm_negate_f32( - float32_t * pSrc, - float32_t * pDst, - uint32_t blockSize); - - - /** - * @brief Negates the elements of a Q7 vector. - * @param[in] pSrc points to the input vector - * @param[out] pDst points to the output vector - * @param[in] blockSize number of samples in the vector - */ - void arm_negate_q7( - q7_t * pSrc, - q7_t * pDst, - uint32_t blockSize); - - - /** - * @brief Negates the elements of a Q15 vector. - * @param[in] pSrc points to the input vector - * @param[out] pDst points to the output vector - * @param[in] blockSize number of samples in the vector - */ - void arm_negate_q15( - q15_t * pSrc, - q15_t * pDst, - uint32_t blockSize); - - - /** - * @brief Negates the elements of a Q31 vector. - * @param[in] pSrc points to the input vector - * @param[out] pDst points to the output vector - * @param[in] blockSize number of samples in the vector - */ - void arm_negate_q31( - q31_t * pSrc, - q31_t * pDst, - uint32_t blockSize); - - - /** - * @brief Copies the elements of a floating-point vector. - * @param[in] pSrc input pointer - * @param[out] pDst output pointer - * @param[in] blockSize number of samples to process - */ - void arm_copy_f32( - float32_t * pSrc, - float32_t * pDst, - uint32_t blockSize); - - - /** - * @brief Copies the elements of a Q7 vector. - * @param[in] pSrc input pointer - * @param[out] pDst output pointer - * @param[in] blockSize number of samples to process - */ - void arm_copy_q7( - q7_t * pSrc, - q7_t * pDst, - uint32_t blockSize); - - - /** - * @brief Copies the elements of a Q15 vector. - * @param[in] pSrc input pointer - * @param[out] pDst output pointer - * @param[in] blockSize number of samples to process - */ - void arm_copy_q15( - q15_t * pSrc, - q15_t * pDst, - uint32_t blockSize); - - - /** - * @brief Copies the elements of a Q31 vector. - * @param[in] pSrc input pointer - * @param[out] pDst output pointer - * @param[in] blockSize number of samples to process - */ - void arm_copy_q31( - q31_t * pSrc, - q31_t * pDst, - uint32_t blockSize); - - - /** - * @brief Fills a constant value into a floating-point vector. - * @param[in] value input value to be filled - * @param[out] pDst output pointer - * @param[in] blockSize number of samples to process - */ - void arm_fill_f32( - float32_t value, - float32_t * pDst, - uint32_t blockSize); - - - /** - * @brief Fills a constant value into a Q7 vector. - * @param[in] value input value to be filled - * @param[out] pDst output pointer - * @param[in] blockSize number of samples to process - */ - void arm_fill_q7( - q7_t value, - q7_t * pDst, - uint32_t blockSize); - - - /** - * @brief Fills a constant value into a Q15 vector. - * @param[in] value input value to be filled - * @param[out] pDst output pointer - * @param[in] blockSize number of samples to process - */ - void arm_fill_q15( - q15_t value, - q15_t * pDst, - uint32_t blockSize); - - - /** - * @brief Fills a constant value into a Q31 vector. - * @param[in] value input value to be filled - * @param[out] pDst output pointer - * @param[in] blockSize number of samples to process - */ - void arm_fill_q31( - q31_t value, - q31_t * pDst, - uint32_t blockSize); - - -/** - * @brief Convolution of floating-point sequences. - * @param[in] pSrcA points to the first input sequence. - * @param[in] srcALen length of the first input sequence. - * @param[in] pSrcB points to the second input sequence. - * @param[in] srcBLen length of the second input sequence. - * @param[out] pDst points to the location where the output result is written. Length srcALen+srcBLen-1. - */ - void arm_conv_f32( - float32_t * pSrcA, - uint32_t srcALen, - float32_t * pSrcB, - uint32_t srcBLen, - float32_t * pDst); - - - /** - * @brief Convolution of Q15 sequences. - * @param[in] pSrcA points to the first input sequence. - * @param[in] srcALen length of the first input sequence. - * @param[in] pSrcB points to the second input sequence. - * @param[in] srcBLen length of the second input sequence. - * @param[out] pDst points to the block of output data Length srcALen+srcBLen-1. - * @param[in] pScratch1 points to scratch buffer of size max(srcALen, srcBLen) + 2*min(srcALen, srcBLen) - 2. - * @param[in] pScratch2 points to scratch buffer of size min(srcALen, srcBLen). - */ - void arm_conv_opt_q15( - q15_t * pSrcA, - uint32_t srcALen, - q15_t * pSrcB, - uint32_t srcBLen, - q15_t * pDst, - q15_t * pScratch1, - q15_t * pScratch2); - - -/** - * @brief Convolution of Q15 sequences. - * @param[in] pSrcA points to the first input sequence. - * @param[in] srcALen length of the first input sequence. - * @param[in] pSrcB points to the second input sequence. - * @param[in] srcBLen length of the second input sequence. - * @param[out] pDst points to the location where the output result is written. Length srcALen+srcBLen-1. - */ - void arm_conv_q15( - q15_t * pSrcA, - uint32_t srcALen, - q15_t * pSrcB, - uint32_t srcBLen, - q15_t * pDst); - - - /** - * @brief Convolution of Q15 sequences (fast version) for Cortex-M3 and Cortex-M4 - * @param[in] pSrcA points to the first input sequence. - * @param[in] srcALen length of the first input sequence. - * @param[in] pSrcB points to the second input sequence. - * @param[in] srcBLen length of the second input sequence. - * @param[out] pDst points to the block of output data Length srcALen+srcBLen-1. - */ - void arm_conv_fast_q15( - q15_t * pSrcA, - uint32_t srcALen, - q15_t * pSrcB, - uint32_t srcBLen, - q15_t * pDst); - - - /** - * @brief Convolution of Q15 sequences (fast version) for Cortex-M3 and Cortex-M4 - * @param[in] pSrcA points to the first input sequence. - * @param[in] srcALen length of the first input sequence. - * @param[in] pSrcB points to the second input sequence. - * @param[in] srcBLen length of the second input sequence. - * @param[out] pDst points to the block of output data Length srcALen+srcBLen-1. - * @param[in] pScratch1 points to scratch buffer of size max(srcALen, srcBLen) + 2*min(srcALen, srcBLen) - 2. - * @param[in] pScratch2 points to scratch buffer of size min(srcALen, srcBLen). - */ - void arm_conv_fast_opt_q15( - q15_t * pSrcA, - uint32_t srcALen, - q15_t * pSrcB, - uint32_t srcBLen, - q15_t * pDst, - q15_t * pScratch1, - q15_t * pScratch2); - - - /** - * @brief Convolution of Q31 sequences. - * @param[in] pSrcA points to the first input sequence. - * @param[in] srcALen length of the first input sequence. - * @param[in] pSrcB points to the second input sequence. - * @param[in] srcBLen length of the second input sequence. - * @param[out] pDst points to the block of output data Length srcALen+srcBLen-1. - */ - void arm_conv_q31( - q31_t * pSrcA, - uint32_t srcALen, - q31_t * pSrcB, - uint32_t srcBLen, - q31_t * pDst); - - - /** - * @brief Convolution of Q31 sequences (fast version) for Cortex-M3 and Cortex-M4 - * @param[in] pSrcA points to the first input sequence. - * @param[in] srcALen length of the first input sequence. - * @param[in] pSrcB points to the second input sequence. - * @param[in] srcBLen length of the second input sequence. - * @param[out] pDst points to the block of output data Length srcALen+srcBLen-1. - */ - void arm_conv_fast_q31( - q31_t * pSrcA, - uint32_t srcALen, - q31_t * pSrcB, - uint32_t srcBLen, - q31_t * pDst); - - - /** - * @brief Convolution of Q7 sequences. - * @param[in] pSrcA points to the first input sequence. - * @param[in] srcALen length of the first input sequence. - * @param[in] pSrcB points to the second input sequence. - * @param[in] srcBLen length of the second input sequence. - * @param[out] pDst points to the block of output data Length srcALen+srcBLen-1. - * @param[in] pScratch1 points to scratch buffer(of type q15_t) of size max(srcALen, srcBLen) + 2*min(srcALen, srcBLen) - 2. - * @param[in] pScratch2 points to scratch buffer (of type q15_t) of size min(srcALen, srcBLen). - */ - void arm_conv_opt_q7( - q7_t * pSrcA, - uint32_t srcALen, - q7_t * pSrcB, - uint32_t srcBLen, - q7_t * pDst, - q15_t * pScratch1, - q15_t * pScratch2); - - - /** - * @brief Convolution of Q7 sequences. - * @param[in] pSrcA points to the first input sequence. - * @param[in] srcALen length of the first input sequence. - * @param[in] pSrcB points to the second input sequence. - * @param[in] srcBLen length of the second input sequence. - * @param[out] pDst points to the block of output data Length srcALen+srcBLen-1. - */ - void arm_conv_q7( - q7_t * pSrcA, - uint32_t srcALen, - q7_t * pSrcB, - uint32_t srcBLen, - q7_t * pDst); - - - /** - * @brief Partial convolution of floating-point sequences. - * @param[in] pSrcA points to the first input sequence. - * @param[in] srcALen length of the first input sequence. - * @param[in] pSrcB points to the second input sequence. - * @param[in] srcBLen length of the second input sequence. - * @param[out] pDst points to the block of output data - * @param[in] firstIndex is the first output sample to start with. - * @param[in] numPoints is the number of output points to be computed. - * @return Returns either ARM_MATH_SUCCESS if the function completed correctly or ARM_MATH_ARGUMENT_ERROR if the requested subset is not in the range [0 srcALen+srcBLen-2]. - */ - arm_status arm_conv_partial_f32( - float32_t * pSrcA, - uint32_t srcALen, - float32_t * pSrcB, - uint32_t srcBLen, - float32_t * pDst, - uint32_t firstIndex, - uint32_t numPoints); - - - /** - * @brief Partial convolution of Q15 sequences. - * @param[in] pSrcA points to the first input sequence. - * @param[in] srcALen length of the first input sequence. - * @param[in] pSrcB points to the second input sequence. - * @param[in] srcBLen length of the second input sequence. - * @param[out] pDst points to the block of output data - * @param[in] firstIndex is the first output sample to start with. - * @param[in] numPoints is the number of output points to be computed. - * @param[in] pScratch1 points to scratch buffer of size max(srcALen, srcBLen) + 2*min(srcALen, srcBLen) - 2. - * @param[in] pScratch2 points to scratch buffer of size min(srcALen, srcBLen). - * @return Returns either ARM_MATH_SUCCESS if the function completed correctly or ARM_MATH_ARGUMENT_ERROR if the requested subset is not in the range [0 srcALen+srcBLen-2]. - */ - arm_status arm_conv_partial_opt_q15( - q15_t * pSrcA, - uint32_t srcALen, - q15_t * pSrcB, - uint32_t srcBLen, - q15_t * pDst, - uint32_t firstIndex, - uint32_t numPoints, - q15_t * pScratch1, - q15_t * pScratch2); - - - /** - * @brief Partial convolution of Q15 sequences. - * @param[in] pSrcA points to the first input sequence. - * @param[in] srcALen length of the first input sequence. - * @param[in] pSrcB points to the second input sequence. - * @param[in] srcBLen length of the second input sequence. - * @param[out] pDst points to the block of output data - * @param[in] firstIndex is the first output sample to start with. - * @param[in] numPoints is the number of output points to be computed. - * @return Returns either ARM_MATH_SUCCESS if the function completed correctly or ARM_MATH_ARGUMENT_ERROR if the requested subset is not in the range [0 srcALen+srcBLen-2]. - */ - arm_status arm_conv_partial_q15( - q15_t * pSrcA, - uint32_t srcALen, - q15_t * pSrcB, - uint32_t srcBLen, - q15_t * pDst, - uint32_t firstIndex, - uint32_t numPoints); - - - /** - * @brief Partial convolution of Q15 sequences (fast version) for Cortex-M3 and Cortex-M4 - * @param[in] pSrcA points to the first input sequence. - * @param[in] srcALen length of the first input sequence. - * @param[in] pSrcB points to the second input sequence. - * @param[in] srcBLen length of the second input sequence. - * @param[out] pDst points to the block of output data - * @param[in] firstIndex is the first output sample to start with. - * @param[in] numPoints is the number of output points to be computed. - * @return Returns either ARM_MATH_SUCCESS if the function completed correctly or ARM_MATH_ARGUMENT_ERROR if the requested subset is not in the range [0 srcALen+srcBLen-2]. - */ - arm_status arm_conv_partial_fast_q15( - q15_t * pSrcA, - uint32_t srcALen, - q15_t * pSrcB, - uint32_t srcBLen, - q15_t * pDst, - uint32_t firstIndex, - uint32_t numPoints); - - - /** - * @brief Partial convolution of Q15 sequences (fast version) for Cortex-M3 and Cortex-M4 - * @param[in] pSrcA points to the first input sequence. - * @param[in] srcALen length of the first input sequence. - * @param[in] pSrcB points to the second input sequence. - * @param[in] srcBLen length of the second input sequence. - * @param[out] pDst points to the block of output data - * @param[in] firstIndex is the first output sample to start with. - * @param[in] numPoints is the number of output points to be computed. - * @param[in] pScratch1 points to scratch buffer of size max(srcALen, srcBLen) + 2*min(srcALen, srcBLen) - 2. - * @param[in] pScratch2 points to scratch buffer of size min(srcALen, srcBLen). - * @return Returns either ARM_MATH_SUCCESS if the function completed correctly or ARM_MATH_ARGUMENT_ERROR if the requested subset is not in the range [0 srcALen+srcBLen-2]. - */ - arm_status arm_conv_partial_fast_opt_q15( - q15_t * pSrcA, - uint32_t srcALen, - q15_t * pSrcB, - uint32_t srcBLen, - q15_t * pDst, - uint32_t firstIndex, - uint32_t numPoints, - q15_t * pScratch1, - q15_t * pScratch2); - - - /** - * @brief Partial convolution of Q31 sequences. - * @param[in] pSrcA points to the first input sequence. - * @param[in] srcALen length of the first input sequence. - * @param[in] pSrcB points to the second input sequence. - * @param[in] srcBLen length of the second input sequence. - * @param[out] pDst points to the block of output data - * @param[in] firstIndex is the first output sample to start with. - * @param[in] numPoints is the number of output points to be computed. - * @return Returns either ARM_MATH_SUCCESS if the function completed correctly or ARM_MATH_ARGUMENT_ERROR if the requested subset is not in the range [0 srcALen+srcBLen-2]. - */ - arm_status arm_conv_partial_q31( - q31_t * pSrcA, - uint32_t srcALen, - q31_t * pSrcB, - uint32_t srcBLen, - q31_t * pDst, - uint32_t firstIndex, - uint32_t numPoints); - - - /** - * @brief Partial convolution of Q31 sequences (fast version) for Cortex-M3 and Cortex-M4 - * @param[in] pSrcA points to the first input sequence. - * @param[in] srcALen length of the first input sequence. - * @param[in] pSrcB points to the second input sequence. - * @param[in] srcBLen length of the second input sequence. - * @param[out] pDst points to the block of output data - * @param[in] firstIndex is the first output sample to start with. - * @param[in] numPoints is the number of output points to be computed. - * @return Returns either ARM_MATH_SUCCESS if the function completed correctly or ARM_MATH_ARGUMENT_ERROR if the requested subset is not in the range [0 srcALen+srcBLen-2]. - */ - arm_status arm_conv_partial_fast_q31( - q31_t * pSrcA, - uint32_t srcALen, - q31_t * pSrcB, - uint32_t srcBLen, - q31_t * pDst, - uint32_t firstIndex, - uint32_t numPoints); - - - /** - * @brief Partial convolution of Q7 sequences - * @param[in] pSrcA points to the first input sequence. - * @param[in] srcALen length of the first input sequence. - * @param[in] pSrcB points to the second input sequence. - * @param[in] srcBLen length of the second input sequence. - * @param[out] pDst points to the block of output data - * @param[in] firstIndex is the first output sample to start with. - * @param[in] numPoints is the number of output points to be computed. - * @param[in] pScratch1 points to scratch buffer(of type q15_t) of size max(srcALen, srcBLen) + 2*min(srcALen, srcBLen) - 2. - * @param[in] pScratch2 points to scratch buffer (of type q15_t) of size min(srcALen, srcBLen). - * @return Returns either ARM_MATH_SUCCESS if the function completed correctly or ARM_MATH_ARGUMENT_ERROR if the requested subset is not in the range [0 srcALen+srcBLen-2]. - */ - arm_status arm_conv_partial_opt_q7( - q7_t * pSrcA, - uint32_t srcALen, - q7_t * pSrcB, - uint32_t srcBLen, - q7_t * pDst, - uint32_t firstIndex, - uint32_t numPoints, - q15_t * pScratch1, - q15_t * pScratch2); - - -/** - * @brief Partial convolution of Q7 sequences. - * @param[in] pSrcA points to the first input sequence. - * @param[in] srcALen length of the first input sequence. - * @param[in] pSrcB points to the second input sequence. - * @param[in] srcBLen length of the second input sequence. - * @param[out] pDst points to the block of output data - * @param[in] firstIndex is the first output sample to start with. - * @param[in] numPoints is the number of output points to be computed. - * @return Returns either ARM_MATH_SUCCESS if the function completed correctly or ARM_MATH_ARGUMENT_ERROR if the requested subset is not in the range [0 srcALen+srcBLen-2]. - */ - arm_status arm_conv_partial_q7( - q7_t * pSrcA, - uint32_t srcALen, - q7_t * pSrcB, - uint32_t srcBLen, - q7_t * pDst, - uint32_t firstIndex, - uint32_t numPoints); - - - /** - * @brief Instance structure for the Q15 FIR decimator. - */ - typedef struct - { - uint8_t M; /**< decimation factor. */ - uint16_t numTaps; /**< number of coefficients in the filter. */ - q15_t *pCoeffs; /**< points to the coefficient array. The array is of length numTaps.*/ - q15_t *pState; /**< points to the state variable array. The array is of length numTaps+blockSize-1. */ - } arm_fir_decimate_instance_q15; - - /** - * @brief Instance structure for the Q31 FIR decimator. - */ - typedef struct - { - uint8_t M; /**< decimation factor. */ - uint16_t numTaps; /**< number of coefficients in the filter. */ - q31_t *pCoeffs; /**< points to the coefficient array. The array is of length numTaps.*/ - q31_t *pState; /**< points to the state variable array. The array is of length numTaps+blockSize-1. */ - } arm_fir_decimate_instance_q31; - - /** - * @brief Instance structure for the floating-point FIR decimator. - */ - typedef struct - { - uint8_t M; /**< decimation factor. */ - uint16_t numTaps; /**< number of coefficients in the filter. */ - float32_t *pCoeffs; /**< points to the coefficient array. The array is of length numTaps.*/ - float32_t *pState; /**< points to the state variable array. The array is of length numTaps+blockSize-1. */ - } arm_fir_decimate_instance_f32; - - - /** - * @brief Processing function for the floating-point FIR decimator. - * @param[in] S points to an instance of the floating-point FIR decimator structure. - * @param[in] pSrc points to the block of input data. - * @param[out] pDst points to the block of output data - * @param[in] blockSize number of input samples to process per call. - */ - void arm_fir_decimate_f32( - const arm_fir_decimate_instance_f32 * S, - float32_t * pSrc, - float32_t * pDst, - uint32_t blockSize); - - - /** - * @brief Initialization function for the floating-point FIR decimator. - * @param[in,out] S points to an instance of the floating-point FIR decimator structure. - * @param[in] numTaps number of coefficients in the filter. - * @param[in] M decimation factor. - * @param[in] pCoeffs points to the filter coefficients. - * @param[in] pState points to the state buffer. - * @param[in] blockSize number of input samples to process per call. - * @return The function returns ARM_MATH_SUCCESS if initialization is successful or ARM_MATH_LENGTH_ERROR if - * blockSize is not a multiple of M. - */ - arm_status arm_fir_decimate_init_f32( - arm_fir_decimate_instance_f32 * S, - uint16_t numTaps, - uint8_t M, - float32_t * pCoeffs, - float32_t * pState, - uint32_t blockSize); - - - /** - * @brief Processing function for the Q15 FIR decimator. - * @param[in] S points to an instance of the Q15 FIR decimator structure. - * @param[in] pSrc points to the block of input data. - * @param[out] pDst points to the block of output data - * @param[in] blockSize number of input samples to process per call. - */ - void arm_fir_decimate_q15( - const arm_fir_decimate_instance_q15 * S, - q15_t * pSrc, - q15_t * pDst, - uint32_t blockSize); - - - /** - * @brief Processing function for the Q15 FIR decimator (fast variant) for Cortex-M3 and Cortex-M4. - * @param[in] S points to an instance of the Q15 FIR decimator structure. - * @param[in] pSrc points to the block of input data. - * @param[out] pDst points to the block of output data - * @param[in] blockSize number of input samples to process per call. - */ - void arm_fir_decimate_fast_q15( - const arm_fir_decimate_instance_q15 * S, - q15_t * pSrc, - q15_t * pDst, - uint32_t blockSize); - - - /** - * @brief Initialization function for the Q15 FIR decimator. - * @param[in,out] S points to an instance of the Q15 FIR decimator structure. - * @param[in] numTaps number of coefficients in the filter. - * @param[in] M decimation factor. - * @param[in] pCoeffs points to the filter coefficients. - * @param[in] pState points to the state buffer. - * @param[in] blockSize number of input samples to process per call. - * @return The function returns ARM_MATH_SUCCESS if initialization is successful or ARM_MATH_LENGTH_ERROR if - * blockSize is not a multiple of M. - */ - arm_status arm_fir_decimate_init_q15( - arm_fir_decimate_instance_q15 * S, - uint16_t numTaps, - uint8_t M, - q15_t * pCoeffs, - q15_t * pState, - uint32_t blockSize); - - - /** - * @brief Processing function for the Q31 FIR decimator. - * @param[in] S points to an instance of the Q31 FIR decimator structure. - * @param[in] pSrc points to the block of input data. - * @param[out] pDst points to the block of output data - * @param[in] blockSize number of input samples to process per call. - */ - void arm_fir_decimate_q31( - const arm_fir_decimate_instance_q31 * S, - q31_t * pSrc, - q31_t * pDst, - uint32_t blockSize); - - /** - * @brief Processing function for the Q31 FIR decimator (fast variant) for Cortex-M3 and Cortex-M4. - * @param[in] S points to an instance of the Q31 FIR decimator structure. - * @param[in] pSrc points to the block of input data. - * @param[out] pDst points to the block of output data - * @param[in] blockSize number of input samples to process per call. - */ - void arm_fir_decimate_fast_q31( - arm_fir_decimate_instance_q31 * S, - q31_t * pSrc, - q31_t * pDst, - uint32_t blockSize); - - - /** - * @brief Initialization function for the Q31 FIR decimator. - * @param[in,out] S points to an instance of the Q31 FIR decimator structure. - * @param[in] numTaps number of coefficients in the filter. - * @param[in] M decimation factor. - * @param[in] pCoeffs points to the filter coefficients. - * @param[in] pState points to the state buffer. - * @param[in] blockSize number of input samples to process per call. - * @return The function returns ARM_MATH_SUCCESS if initialization is successful or ARM_MATH_LENGTH_ERROR if - * blockSize is not a multiple of M. - */ - arm_status arm_fir_decimate_init_q31( - arm_fir_decimate_instance_q31 * S, - uint16_t numTaps, - uint8_t M, - q31_t * pCoeffs, - q31_t * pState, - uint32_t blockSize); - - - /** - * @brief Instance structure for the Q15 FIR interpolator. - */ - typedef struct - { - uint8_t L; /**< upsample factor. */ - uint16_t phaseLength; /**< length of each polyphase filter component. */ - q15_t *pCoeffs; /**< points to the coefficient array. The array is of length L*phaseLength. */ - q15_t *pState; /**< points to the state variable array. The array is of length blockSize+phaseLength-1. */ - } arm_fir_interpolate_instance_q15; - - /** - * @brief Instance structure for the Q31 FIR interpolator. - */ - typedef struct - { - uint8_t L; /**< upsample factor. */ - uint16_t phaseLength; /**< length of each polyphase filter component. */ - q31_t *pCoeffs; /**< points to the coefficient array. The array is of length L*phaseLength. */ - q31_t *pState; /**< points to the state variable array. The array is of length blockSize+phaseLength-1. */ - } arm_fir_interpolate_instance_q31; - - /** - * @brief Instance structure for the floating-point FIR interpolator. - */ - typedef struct - { - uint8_t L; /**< upsample factor. */ - uint16_t phaseLength; /**< length of each polyphase filter component. */ - float32_t *pCoeffs; /**< points to the coefficient array. The array is of length L*phaseLength. */ - float32_t *pState; /**< points to the state variable array. The array is of length phaseLength+numTaps-1. */ - } arm_fir_interpolate_instance_f32; - - - /** - * @brief Processing function for the Q15 FIR interpolator. - * @param[in] S points to an instance of the Q15 FIR interpolator structure. - * @param[in] pSrc points to the block of input data. - * @param[out] pDst points to the block of output data. - * @param[in] blockSize number of input samples to process per call. - */ - void arm_fir_interpolate_q15( - const arm_fir_interpolate_instance_q15 * S, - q15_t * pSrc, - q15_t * pDst, - uint32_t blockSize); - - - /** - * @brief Initialization function for the Q15 FIR interpolator. - * @param[in,out] S points to an instance of the Q15 FIR interpolator structure. - * @param[in] L upsample factor. - * @param[in] numTaps number of filter coefficients in the filter. - * @param[in] pCoeffs points to the filter coefficient buffer. - * @param[in] pState points to the state buffer. - * @param[in] blockSize number of input samples to process per call. - * @return The function returns ARM_MATH_SUCCESS if initialization is successful or ARM_MATH_LENGTH_ERROR if - * the filter length numTaps is not a multiple of the interpolation factor L. - */ - arm_status arm_fir_interpolate_init_q15( - arm_fir_interpolate_instance_q15 * S, - uint8_t L, - uint16_t numTaps, - q15_t * pCoeffs, - q15_t * pState, - uint32_t blockSize); - - - /** - * @brief Processing function for the Q31 FIR interpolator. - * @param[in] S points to an instance of the Q15 FIR interpolator structure. - * @param[in] pSrc points to the block of input data. - * @param[out] pDst points to the block of output data. - * @param[in] blockSize number of input samples to process per call. - */ - void arm_fir_interpolate_q31( - const arm_fir_interpolate_instance_q31 * S, - q31_t * pSrc, - q31_t * pDst, - uint32_t blockSize); - - - /** - * @brief Initialization function for the Q31 FIR interpolator. - * @param[in,out] S points to an instance of the Q31 FIR interpolator structure. - * @param[in] L upsample factor. - * @param[in] numTaps number of filter coefficients in the filter. - * @param[in] pCoeffs points to the filter coefficient buffer. - * @param[in] pState points to the state buffer. - * @param[in] blockSize number of input samples to process per call. - * @return The function returns ARM_MATH_SUCCESS if initialization is successful or ARM_MATH_LENGTH_ERROR if - * the filter length numTaps is not a multiple of the interpolation factor L. - */ - arm_status arm_fir_interpolate_init_q31( - arm_fir_interpolate_instance_q31 * S, - uint8_t L, - uint16_t numTaps, - q31_t * pCoeffs, - q31_t * pState, - uint32_t blockSize); - - - /** - * @brief Processing function for the floating-point FIR interpolator. - * @param[in] S points to an instance of the floating-point FIR interpolator structure. - * @param[in] pSrc points to the block of input data. - * @param[out] pDst points to the block of output data. - * @param[in] blockSize number of input samples to process per call. - */ - void arm_fir_interpolate_f32( - const arm_fir_interpolate_instance_f32 * S, - float32_t * pSrc, - float32_t * pDst, - uint32_t blockSize); - - - /** - * @brief Initialization function for the floating-point FIR interpolator. - * @param[in,out] S points to an instance of the floating-point FIR interpolator structure. - * @param[in] L upsample factor. - * @param[in] numTaps number of filter coefficients in the filter. - * @param[in] pCoeffs points to the filter coefficient buffer. - * @param[in] pState points to the state buffer. - * @param[in] blockSize number of input samples to process per call. - * @return The function returns ARM_MATH_SUCCESS if initialization is successful or ARM_MATH_LENGTH_ERROR if - * the filter length numTaps is not a multiple of the interpolation factor L. - */ - arm_status arm_fir_interpolate_init_f32( - arm_fir_interpolate_instance_f32 * S, - uint8_t L, - uint16_t numTaps, - float32_t * pCoeffs, - float32_t * pState, - uint32_t blockSize); - - - /** - * @brief Instance structure for the high precision Q31 Biquad cascade filter. - */ - typedef struct - { - uint8_t numStages; /**< number of 2nd order stages in the filter. Overall order is 2*numStages. */ - q63_t *pState; /**< points to the array of state coefficients. The array is of length 4*numStages. */ - q31_t *pCoeffs; /**< points to the array of coefficients. The array is of length 5*numStages. */ - uint8_t postShift; /**< additional shift, in bits, applied to each output sample. */ - } arm_biquad_cas_df1_32x64_ins_q31; - - - /** - * @param[in] S points to an instance of the high precision Q31 Biquad cascade filter structure. - * @param[in] pSrc points to the block of input data. - * @param[out] pDst points to the block of output data - * @param[in] blockSize number of samples to process. - */ - void arm_biquad_cas_df1_32x64_q31( - const arm_biquad_cas_df1_32x64_ins_q31 * S, - q31_t * pSrc, - q31_t * pDst, - uint32_t blockSize); - - - /** - * @param[in,out] S points to an instance of the high precision Q31 Biquad cascade filter structure. - * @param[in] numStages number of 2nd order stages in the filter. - * @param[in] pCoeffs points to the filter coefficients. - * @param[in] pState points to the state buffer. - * @param[in] postShift shift to be applied to the output. Varies according to the coefficients format - */ - void arm_biquad_cas_df1_32x64_init_q31( - arm_biquad_cas_df1_32x64_ins_q31 * S, - uint8_t numStages, - q31_t * pCoeffs, - q63_t * pState, - uint8_t postShift); - - - /** - * @brief Instance structure for the floating-point transposed direct form II Biquad cascade filter. - */ - typedef struct - { - uint8_t numStages; /**< number of 2nd order stages in the filter. Overall order is 2*numStages. */ - float32_t *pState; /**< points to the array of state coefficients. The array is of length 2*numStages. */ - float32_t *pCoeffs; /**< points to the array of coefficients. The array is of length 5*numStages. */ - } arm_biquad_cascade_df2T_instance_f32; - - /** - * @brief Instance structure for the floating-point transposed direct form II Biquad cascade filter. - */ - typedef struct - { - uint8_t numStages; /**< number of 2nd order stages in the filter. Overall order is 2*numStages. */ - float32_t *pState; /**< points to the array of state coefficients. The array is of length 4*numStages. */ - float32_t *pCoeffs; /**< points to the array of coefficients. The array is of length 5*numStages. */ - } arm_biquad_cascade_stereo_df2T_instance_f32; - - /** - * @brief Instance structure for the floating-point transposed direct form II Biquad cascade filter. - */ - typedef struct - { - uint8_t numStages; /**< number of 2nd order stages in the filter. Overall order is 2*numStages. */ - float64_t *pState; /**< points to the array of state coefficients. The array is of length 2*numStages. */ - float64_t *pCoeffs; /**< points to the array of coefficients. The array is of length 5*numStages. */ - } arm_biquad_cascade_df2T_instance_f64; - - - /** - * @brief Processing function for the floating-point transposed direct form II Biquad cascade filter. - * @param[in] S points to an instance of the filter data structure. - * @param[in] pSrc points to the block of input data. - * @param[out] pDst points to the block of output data - * @param[in] blockSize number of samples to process. - */ - void arm_biquad_cascade_df2T_f32( - const arm_biquad_cascade_df2T_instance_f32 * S, - float32_t * pSrc, - float32_t * pDst, - uint32_t blockSize); - - - /** - * @brief Processing function for the floating-point transposed direct form II Biquad cascade filter. 2 channels - * @param[in] S points to an instance of the filter data structure. - * @param[in] pSrc points to the block of input data. - * @param[out] pDst points to the block of output data - * @param[in] blockSize number of samples to process. - */ - void arm_biquad_cascade_stereo_df2T_f32( - const arm_biquad_cascade_stereo_df2T_instance_f32 * S, - float32_t * pSrc, - float32_t * pDst, - uint32_t blockSize); - - - /** - * @brief Processing function for the floating-point transposed direct form II Biquad cascade filter. - * @param[in] S points to an instance of the filter data structure. - * @param[in] pSrc points to the block of input data. - * @param[out] pDst points to the block of output data - * @param[in] blockSize number of samples to process. - */ - void arm_biquad_cascade_df2T_f64( - const arm_biquad_cascade_df2T_instance_f64 * S, - float64_t * pSrc, - float64_t * pDst, - uint32_t blockSize); - - - /** - * @brief Initialization function for the floating-point transposed direct form II Biquad cascade filter. - * @param[in,out] S points to an instance of the filter data structure. - * @param[in] numStages number of 2nd order stages in the filter. - * @param[in] pCoeffs points to the filter coefficients. - * @param[in] pState points to the state buffer. - */ - void arm_biquad_cascade_df2T_init_f32( - arm_biquad_cascade_df2T_instance_f32 * S, - uint8_t numStages, - float32_t * pCoeffs, - float32_t * pState); - - - /** - * @brief Initialization function for the floating-point transposed direct form II Biquad cascade filter. - * @param[in,out] S points to an instance of the filter data structure. - * @param[in] numStages number of 2nd order stages in the filter. - * @param[in] pCoeffs points to the filter coefficients. - * @param[in] pState points to the state buffer. - */ - void arm_biquad_cascade_stereo_df2T_init_f32( - arm_biquad_cascade_stereo_df2T_instance_f32 * S, - uint8_t numStages, - float32_t * pCoeffs, - float32_t * pState); - - - /** - * @brief Initialization function for the floating-point transposed direct form II Biquad cascade filter. - * @param[in,out] S points to an instance of the filter data structure. - * @param[in] numStages number of 2nd order stages in the filter. - * @param[in] pCoeffs points to the filter coefficients. - * @param[in] pState points to the state buffer. - */ - void arm_biquad_cascade_df2T_init_f64( - arm_biquad_cascade_df2T_instance_f64 * S, - uint8_t numStages, - float64_t * pCoeffs, - float64_t * pState); - - - /** - * @brief Instance structure for the Q15 FIR lattice filter. - */ - typedef struct - { - uint16_t numStages; /**< number of filter stages. */ - q15_t *pState; /**< points to the state variable array. The array is of length numStages. */ - q15_t *pCoeffs; /**< points to the coefficient array. The array is of length numStages. */ - } arm_fir_lattice_instance_q15; - - /** - * @brief Instance structure for the Q31 FIR lattice filter. - */ - typedef struct - { - uint16_t numStages; /**< number of filter stages. */ - q31_t *pState; /**< points to the state variable array. The array is of length numStages. */ - q31_t *pCoeffs; /**< points to the coefficient array. The array is of length numStages. */ - } arm_fir_lattice_instance_q31; - - /** - * @brief Instance structure for the floating-point FIR lattice filter. - */ - typedef struct - { - uint16_t numStages; /**< number of filter stages. */ - float32_t *pState; /**< points to the state variable array. The array is of length numStages. */ - float32_t *pCoeffs; /**< points to the coefficient array. The array is of length numStages. */ - } arm_fir_lattice_instance_f32; - - - /** - * @brief Initialization function for the Q15 FIR lattice filter. - * @param[in] S points to an instance of the Q15 FIR lattice structure. - * @param[in] numStages number of filter stages. - * @param[in] pCoeffs points to the coefficient buffer. The array is of length numStages. - * @param[in] pState points to the state buffer. The array is of length numStages. - */ - void arm_fir_lattice_init_q15( - arm_fir_lattice_instance_q15 * S, - uint16_t numStages, - q15_t * pCoeffs, - q15_t * pState); - - - /** - * @brief Processing function for the Q15 FIR lattice filter. - * @param[in] S points to an instance of the Q15 FIR lattice structure. - * @param[in] pSrc points to the block of input data. - * @param[out] pDst points to the block of output data. - * @param[in] blockSize number of samples to process. - */ - void arm_fir_lattice_q15( - const arm_fir_lattice_instance_q15 * S, - q15_t * pSrc, - q15_t * pDst, - uint32_t blockSize); - - - /** - * @brief Initialization function for the Q31 FIR lattice filter. - * @param[in] S points to an instance of the Q31 FIR lattice structure. - * @param[in] numStages number of filter stages. - * @param[in] pCoeffs points to the coefficient buffer. The array is of length numStages. - * @param[in] pState points to the state buffer. The array is of length numStages. - */ - void arm_fir_lattice_init_q31( - arm_fir_lattice_instance_q31 * S, - uint16_t numStages, - q31_t * pCoeffs, - q31_t * pState); - - - /** - * @brief Processing function for the Q31 FIR lattice filter. - * @param[in] S points to an instance of the Q31 FIR lattice structure. - * @param[in] pSrc points to the block of input data. - * @param[out] pDst points to the block of output data - * @param[in] blockSize number of samples to process. - */ - void arm_fir_lattice_q31( - const arm_fir_lattice_instance_q31 * S, - q31_t * pSrc, - q31_t * pDst, - uint32_t blockSize); - - -/** - * @brief Initialization function for the floating-point FIR lattice filter. - * @param[in] S points to an instance of the floating-point FIR lattice structure. - * @param[in] numStages number of filter stages. - * @param[in] pCoeffs points to the coefficient buffer. The array is of length numStages. - * @param[in] pState points to the state buffer. The array is of length numStages. - */ - void arm_fir_lattice_init_f32( - arm_fir_lattice_instance_f32 * S, - uint16_t numStages, - float32_t * pCoeffs, - float32_t * pState); - - - /** - * @brief Processing function for the floating-point FIR lattice filter. - * @param[in] S points to an instance of the floating-point FIR lattice structure. - * @param[in] pSrc points to the block of input data. - * @param[out] pDst points to the block of output data - * @param[in] blockSize number of samples to process. - */ - void arm_fir_lattice_f32( - const arm_fir_lattice_instance_f32 * S, - float32_t * pSrc, - float32_t * pDst, - uint32_t blockSize); - - - /** - * @brief Instance structure for the Q15 IIR lattice filter. - */ - typedef struct - { - uint16_t numStages; /**< number of stages in the filter. */ - q15_t *pState; /**< points to the state variable array. The array is of length numStages+blockSize. */ - q15_t *pkCoeffs; /**< points to the reflection coefficient array. The array is of length numStages. */ - q15_t *pvCoeffs; /**< points to the ladder coefficient array. The array is of length numStages+1. */ - } arm_iir_lattice_instance_q15; - - /** - * @brief Instance structure for the Q31 IIR lattice filter. - */ - typedef struct - { - uint16_t numStages; /**< number of stages in the filter. */ - q31_t *pState; /**< points to the state variable array. The array is of length numStages+blockSize. */ - q31_t *pkCoeffs; /**< points to the reflection coefficient array. The array is of length numStages. */ - q31_t *pvCoeffs; /**< points to the ladder coefficient array. The array is of length numStages+1. */ - } arm_iir_lattice_instance_q31; - - /** - * @brief Instance structure for the floating-point IIR lattice filter. - */ - typedef struct - { - uint16_t numStages; /**< number of stages in the filter. */ - float32_t *pState; /**< points to the state variable array. The array is of length numStages+blockSize. */ - float32_t *pkCoeffs; /**< points to the reflection coefficient array. The array is of length numStages. */ - float32_t *pvCoeffs; /**< points to the ladder coefficient array. The array is of length numStages+1. */ - } arm_iir_lattice_instance_f32; - - - /** - * @brief Processing function for the floating-point IIR lattice filter. - * @param[in] S points to an instance of the floating-point IIR lattice structure. - * @param[in] pSrc points to the block of input data. - * @param[out] pDst points to the block of output data. - * @param[in] blockSize number of samples to process. - */ - void arm_iir_lattice_f32( - const arm_iir_lattice_instance_f32 * S, - float32_t * pSrc, - float32_t * pDst, - uint32_t blockSize); - - - /** - * @brief Initialization function for the floating-point IIR lattice filter. - * @param[in] S points to an instance of the floating-point IIR lattice structure. - * @param[in] numStages number of stages in the filter. - * @param[in] pkCoeffs points to the reflection coefficient buffer. The array is of length numStages. - * @param[in] pvCoeffs points to the ladder coefficient buffer. The array is of length numStages+1. - * @param[in] pState points to the state buffer. The array is of length numStages+blockSize-1. - * @param[in] blockSize number of samples to process. - */ - void arm_iir_lattice_init_f32( - arm_iir_lattice_instance_f32 * S, - uint16_t numStages, - float32_t * pkCoeffs, - float32_t * pvCoeffs, - float32_t * pState, - uint32_t blockSize); - - - /** - * @brief Processing function for the Q31 IIR lattice filter. - * @param[in] S points to an instance of the Q31 IIR lattice structure. - * @param[in] pSrc points to the block of input data. - * @param[out] pDst points to the block of output data. - * @param[in] blockSize number of samples to process. - */ - void arm_iir_lattice_q31( - const arm_iir_lattice_instance_q31 * S, - q31_t * pSrc, - q31_t * pDst, - uint32_t blockSize); - - - /** - * @brief Initialization function for the Q31 IIR lattice filter. - * @param[in] S points to an instance of the Q31 IIR lattice structure. - * @param[in] numStages number of stages in the filter. - * @param[in] pkCoeffs points to the reflection coefficient buffer. The array is of length numStages. - * @param[in] pvCoeffs points to the ladder coefficient buffer. The array is of length numStages+1. - * @param[in] pState points to the state buffer. The array is of length numStages+blockSize. - * @param[in] blockSize number of samples to process. - */ - void arm_iir_lattice_init_q31( - arm_iir_lattice_instance_q31 * S, - uint16_t numStages, - q31_t * pkCoeffs, - q31_t * pvCoeffs, - q31_t * pState, - uint32_t blockSize); - - - /** - * @brief Processing function for the Q15 IIR lattice filter. - * @param[in] S points to an instance of the Q15 IIR lattice structure. - * @param[in] pSrc points to the block of input data. - * @param[out] pDst points to the block of output data. - * @param[in] blockSize number of samples to process. - */ - void arm_iir_lattice_q15( - const arm_iir_lattice_instance_q15 * S, - q15_t * pSrc, - q15_t * pDst, - uint32_t blockSize); - - -/** - * @brief Initialization function for the Q15 IIR lattice filter. - * @param[in] S points to an instance of the fixed-point Q15 IIR lattice structure. - * @param[in] numStages number of stages in the filter. - * @param[in] pkCoeffs points to reflection coefficient buffer. The array is of length numStages. - * @param[in] pvCoeffs points to ladder coefficient buffer. The array is of length numStages+1. - * @param[in] pState points to state buffer. The array is of length numStages+blockSize. - * @param[in] blockSize number of samples to process per call. - */ - void arm_iir_lattice_init_q15( - arm_iir_lattice_instance_q15 * S, - uint16_t numStages, - q15_t * pkCoeffs, - q15_t * pvCoeffs, - q15_t * pState, - uint32_t blockSize); - - - /** - * @brief Instance structure for the floating-point LMS filter. - */ - typedef struct - { - uint16_t numTaps; /**< number of coefficients in the filter. */ - float32_t *pState; /**< points to the state variable array. The array is of length numTaps+blockSize-1. */ - float32_t *pCoeffs; /**< points to the coefficient array. The array is of length numTaps. */ - float32_t mu; /**< step size that controls filter coefficient updates. */ - } arm_lms_instance_f32; - - - /** - * @brief Processing function for floating-point LMS filter. - * @param[in] S points to an instance of the floating-point LMS filter structure. - * @param[in] pSrc points to the block of input data. - * @param[in] pRef points to the block of reference data. - * @param[out] pOut points to the block of output data. - * @param[out] pErr points to the block of error data. - * @param[in] blockSize number of samples to process. - */ - void arm_lms_f32( - const arm_lms_instance_f32 * S, - float32_t * pSrc, - float32_t * pRef, - float32_t * pOut, - float32_t * pErr, - uint32_t blockSize); - - - /** - * @brief Initialization function for floating-point LMS filter. - * @param[in] S points to an instance of the floating-point LMS filter structure. - * @param[in] numTaps number of filter coefficients. - * @param[in] pCoeffs points to the coefficient buffer. - * @param[in] pState points to state buffer. - * @param[in] mu step size that controls filter coefficient updates. - * @param[in] blockSize number of samples to process. - */ - void arm_lms_init_f32( - arm_lms_instance_f32 * S, - uint16_t numTaps, - float32_t * pCoeffs, - float32_t * pState, - float32_t mu, - uint32_t blockSize); - - - /** - * @brief Instance structure for the Q15 LMS filter. - */ - typedef struct - { - uint16_t numTaps; /**< number of coefficients in the filter. */ - q15_t *pState; /**< points to the state variable array. The array is of length numTaps+blockSize-1. */ - q15_t *pCoeffs; /**< points to the coefficient array. The array is of length numTaps. */ - q15_t mu; /**< step size that controls filter coefficient updates. */ - uint32_t postShift; /**< bit shift applied to coefficients. */ - } arm_lms_instance_q15; - - - /** - * @brief Initialization function for the Q15 LMS filter. - * @param[in] S points to an instance of the Q15 LMS filter structure. - * @param[in] numTaps number of filter coefficients. - * @param[in] pCoeffs points to the coefficient buffer. - * @param[in] pState points to the state buffer. - * @param[in] mu step size that controls filter coefficient updates. - * @param[in] blockSize number of samples to process. - * @param[in] postShift bit shift applied to coefficients. - */ - void arm_lms_init_q15( - arm_lms_instance_q15 * S, - uint16_t numTaps, - q15_t * pCoeffs, - q15_t * pState, - q15_t mu, - uint32_t blockSize, - uint32_t postShift); - - - /** - * @brief Processing function for Q15 LMS filter. - * @param[in] S points to an instance of the Q15 LMS filter structure. - * @param[in] pSrc points to the block of input data. - * @param[in] pRef points to the block of reference data. - * @param[out] pOut points to the block of output data. - * @param[out] pErr points to the block of error data. - * @param[in] blockSize number of samples to process. - */ - void arm_lms_q15( - const arm_lms_instance_q15 * S, - q15_t * pSrc, - q15_t * pRef, - q15_t * pOut, - q15_t * pErr, - uint32_t blockSize); - - - /** - * @brief Instance structure for the Q31 LMS filter. - */ - typedef struct - { - uint16_t numTaps; /**< number of coefficients in the filter. */ - q31_t *pState; /**< points to the state variable array. The array is of length numTaps+blockSize-1. */ - q31_t *pCoeffs; /**< points to the coefficient array. The array is of length numTaps. */ - q31_t mu; /**< step size that controls filter coefficient updates. */ - uint32_t postShift; /**< bit shift applied to coefficients. */ - } arm_lms_instance_q31; - - - /** - * @brief Processing function for Q31 LMS filter. - * @param[in] S points to an instance of the Q15 LMS filter structure. - * @param[in] pSrc points to the block of input data. - * @param[in] pRef points to the block of reference data. - * @param[out] pOut points to the block of output data. - * @param[out] pErr points to the block of error data. - * @param[in] blockSize number of samples to process. - */ - void arm_lms_q31( - const arm_lms_instance_q31 * S, - q31_t * pSrc, - q31_t * pRef, - q31_t * pOut, - q31_t * pErr, - uint32_t blockSize); - - - /** - * @brief Initialization function for Q31 LMS filter. - * @param[in] S points to an instance of the Q31 LMS filter structure. - * @param[in] numTaps number of filter coefficients. - * @param[in] pCoeffs points to coefficient buffer. - * @param[in] pState points to state buffer. - * @param[in] mu step size that controls filter coefficient updates. - * @param[in] blockSize number of samples to process. - * @param[in] postShift bit shift applied to coefficients. - */ - void arm_lms_init_q31( - arm_lms_instance_q31 * S, - uint16_t numTaps, - q31_t * pCoeffs, - q31_t * pState, - q31_t mu, - uint32_t blockSize, - uint32_t postShift); - - - /** - * @brief Instance structure for the floating-point normalized LMS filter. - */ - typedef struct - { - uint16_t numTaps; /**< number of coefficients in the filter. */ - float32_t *pState; /**< points to the state variable array. The array is of length numTaps+blockSize-1. */ - float32_t *pCoeffs; /**< points to the coefficient array. The array is of length numTaps. */ - float32_t mu; /**< step size that control filter coefficient updates. */ - float32_t energy; /**< saves previous frame energy. */ - float32_t x0; /**< saves previous input sample. */ - } arm_lms_norm_instance_f32; - - - /** - * @brief Processing function for floating-point normalized LMS filter. - * @param[in] S points to an instance of the floating-point normalized LMS filter structure. - * @param[in] pSrc points to the block of input data. - * @param[in] pRef points to the block of reference data. - * @param[out] pOut points to the block of output data. - * @param[out] pErr points to the block of error data. - * @param[in] blockSize number of samples to process. - */ - void arm_lms_norm_f32( - arm_lms_norm_instance_f32 * S, - float32_t * pSrc, - float32_t * pRef, - float32_t * pOut, - float32_t * pErr, - uint32_t blockSize); - - - /** - * @brief Initialization function for floating-point normalized LMS filter. - * @param[in] S points to an instance of the floating-point LMS filter structure. - * @param[in] numTaps number of filter coefficients. - * @param[in] pCoeffs points to coefficient buffer. - * @param[in] pState points to state buffer. - * @param[in] mu step size that controls filter coefficient updates. - * @param[in] blockSize number of samples to process. - */ - void arm_lms_norm_init_f32( - arm_lms_norm_instance_f32 * S, - uint16_t numTaps, - float32_t * pCoeffs, - float32_t * pState, - float32_t mu, - uint32_t blockSize); - - - /** - * @brief Instance structure for the Q31 normalized LMS filter. - */ - typedef struct - { - uint16_t numTaps; /**< number of coefficients in the filter. */ - q31_t *pState; /**< points to the state variable array. The array is of length numTaps+blockSize-1. */ - q31_t *pCoeffs; /**< points to the coefficient array. The array is of length numTaps. */ - q31_t mu; /**< step size that controls filter coefficient updates. */ - uint8_t postShift; /**< bit shift applied to coefficients. */ - q31_t *recipTable; /**< points to the reciprocal initial value table. */ - q31_t energy; /**< saves previous frame energy. */ - q31_t x0; /**< saves previous input sample. */ - } arm_lms_norm_instance_q31; - - - /** - * @brief Processing function for Q31 normalized LMS filter. - * @param[in] S points to an instance of the Q31 normalized LMS filter structure. - * @param[in] pSrc points to the block of input data. - * @param[in] pRef points to the block of reference data. - * @param[out] pOut points to the block of output data. - * @param[out] pErr points to the block of error data. - * @param[in] blockSize number of samples to process. - */ - void arm_lms_norm_q31( - arm_lms_norm_instance_q31 * S, - q31_t * pSrc, - q31_t * pRef, - q31_t * pOut, - q31_t * pErr, - uint32_t blockSize); - - - /** - * @brief Initialization function for Q31 normalized LMS filter. - * @param[in] S points to an instance of the Q31 normalized LMS filter structure. - * @param[in] numTaps number of filter coefficients. - * @param[in] pCoeffs points to coefficient buffer. - * @param[in] pState points to state buffer. - * @param[in] mu step size that controls filter coefficient updates. - * @param[in] blockSize number of samples to process. - * @param[in] postShift bit shift applied to coefficients. - */ - void arm_lms_norm_init_q31( - arm_lms_norm_instance_q31 * S, - uint16_t numTaps, - q31_t * pCoeffs, - q31_t * pState, - q31_t mu, - uint32_t blockSize, - uint8_t postShift); - - - /** - * @brief Instance structure for the Q15 normalized LMS filter. - */ - typedef struct - { - uint16_t numTaps; /**< Number of coefficients in the filter. */ - q15_t *pState; /**< points to the state variable array. The array is of length numTaps+blockSize-1. */ - q15_t *pCoeffs; /**< points to the coefficient array. The array is of length numTaps. */ - q15_t mu; /**< step size that controls filter coefficient updates. */ - uint8_t postShift; /**< bit shift applied to coefficients. */ - q15_t *recipTable; /**< Points to the reciprocal initial value table. */ - q15_t energy; /**< saves previous frame energy. */ - q15_t x0; /**< saves previous input sample. */ - } arm_lms_norm_instance_q15; - - - /** - * @brief Processing function for Q15 normalized LMS filter. - * @param[in] S points to an instance of the Q15 normalized LMS filter structure. - * @param[in] pSrc points to the block of input data. - * @param[in] pRef points to the block of reference data. - * @param[out] pOut points to the block of output data. - * @param[out] pErr points to the block of error data. - * @param[in] blockSize number of samples to process. - */ - void arm_lms_norm_q15( - arm_lms_norm_instance_q15 * S, - q15_t * pSrc, - q15_t * pRef, - q15_t * pOut, - q15_t * pErr, - uint32_t blockSize); - - - /** - * @brief Initialization function for Q15 normalized LMS filter. - * @param[in] S points to an instance of the Q15 normalized LMS filter structure. - * @param[in] numTaps number of filter coefficients. - * @param[in] pCoeffs points to coefficient buffer. - * @param[in] pState points to state buffer. - * @param[in] mu step size that controls filter coefficient updates. - * @param[in] blockSize number of samples to process. - * @param[in] postShift bit shift applied to coefficients. - */ - void arm_lms_norm_init_q15( - arm_lms_norm_instance_q15 * S, - uint16_t numTaps, - q15_t * pCoeffs, - q15_t * pState, - q15_t mu, - uint32_t blockSize, - uint8_t postShift); - - - /** - * @brief Correlation of floating-point sequences. - * @param[in] pSrcA points to the first input sequence. - * @param[in] srcALen length of the first input sequence. - * @param[in] pSrcB points to the second input sequence. - * @param[in] srcBLen length of the second input sequence. - * @param[out] pDst points to the block of output data Length 2 * max(srcALen, srcBLen) - 1. - */ - void arm_correlate_f32( - float32_t * pSrcA, - uint32_t srcALen, - float32_t * pSrcB, - uint32_t srcBLen, - float32_t * pDst); - - - /** - * @brief Correlation of Q15 sequences - * @param[in] pSrcA points to the first input sequence. - * @param[in] srcALen length of the first input sequence. - * @param[in] pSrcB points to the second input sequence. - * @param[in] srcBLen length of the second input sequence. - * @param[out] pDst points to the block of output data Length 2 * max(srcALen, srcBLen) - 1. - * @param[in] pScratch points to scratch buffer of size max(srcALen, srcBLen) + 2*min(srcALen, srcBLen) - 2. - */ - void arm_correlate_opt_q15( - q15_t * pSrcA, - uint32_t srcALen, - q15_t * pSrcB, - uint32_t srcBLen, - q15_t * pDst, - q15_t * pScratch); - - - /** - * @brief Correlation of Q15 sequences. - * @param[in] pSrcA points to the first input sequence. - * @param[in] srcALen length of the first input sequence. - * @param[in] pSrcB points to the second input sequence. - * @param[in] srcBLen length of the second input sequence. - * @param[out] pDst points to the block of output data Length 2 * max(srcALen, srcBLen) - 1. - */ - - void arm_correlate_q15( - q15_t * pSrcA, - uint32_t srcALen, - q15_t * pSrcB, - uint32_t srcBLen, - q15_t * pDst); - - - /** - * @brief Correlation of Q15 sequences (fast version) for Cortex-M3 and Cortex-M4. - * @param[in] pSrcA points to the first input sequence. - * @param[in] srcALen length of the first input sequence. - * @param[in] pSrcB points to the second input sequence. - * @param[in] srcBLen length of the second input sequence. - * @param[out] pDst points to the block of output data Length 2 * max(srcALen, srcBLen) - 1. - */ - - void arm_correlate_fast_q15( - q15_t * pSrcA, - uint32_t srcALen, - q15_t * pSrcB, - uint32_t srcBLen, - q15_t * pDst); - - - /** - * @brief Correlation of Q15 sequences (fast version) for Cortex-M3 and Cortex-M4. - * @param[in] pSrcA points to the first input sequence. - * @param[in] srcALen length of the first input sequence. - * @param[in] pSrcB points to the second input sequence. - * @param[in] srcBLen length of the second input sequence. - * @param[out] pDst points to the block of output data Length 2 * max(srcALen, srcBLen) - 1. - * @param[in] pScratch points to scratch buffer of size max(srcALen, srcBLen) + 2*min(srcALen, srcBLen) - 2. - */ - void arm_correlate_fast_opt_q15( - q15_t * pSrcA, - uint32_t srcALen, - q15_t * pSrcB, - uint32_t srcBLen, - q15_t * pDst, - q15_t * pScratch); - - - /** - * @brief Correlation of Q31 sequences. - * @param[in] pSrcA points to the first input sequence. - * @param[in] srcALen length of the first input sequence. - * @param[in] pSrcB points to the second input sequence. - * @param[in] srcBLen length of the second input sequence. - * @param[out] pDst points to the block of output data Length 2 * max(srcALen, srcBLen) - 1. - */ - void arm_correlate_q31( - q31_t * pSrcA, - uint32_t srcALen, - q31_t * pSrcB, - uint32_t srcBLen, - q31_t * pDst); - - - /** - * @brief Correlation of Q31 sequences (fast version) for Cortex-M3 and Cortex-M4 - * @param[in] pSrcA points to the first input sequence. - * @param[in] srcALen length of the first input sequence. - * @param[in] pSrcB points to the second input sequence. - * @param[in] srcBLen length of the second input sequence. - * @param[out] pDst points to the block of output data Length 2 * max(srcALen, srcBLen) - 1. - */ - void arm_correlate_fast_q31( - q31_t * pSrcA, - uint32_t srcALen, - q31_t * pSrcB, - uint32_t srcBLen, - q31_t * pDst); - - - /** - * @brief Correlation of Q7 sequences. - * @param[in] pSrcA points to the first input sequence. - * @param[in] srcALen length of the first input sequence. - * @param[in] pSrcB points to the second input sequence. - * @param[in] srcBLen length of the second input sequence. - * @param[out] pDst points to the block of output data Length 2 * max(srcALen, srcBLen) - 1. - * @param[in] pScratch1 points to scratch buffer(of type q15_t) of size max(srcALen, srcBLen) + 2*min(srcALen, srcBLen) - 2. - * @param[in] pScratch2 points to scratch buffer (of type q15_t) of size min(srcALen, srcBLen). - */ - void arm_correlate_opt_q7( - q7_t * pSrcA, - uint32_t srcALen, - q7_t * pSrcB, - uint32_t srcBLen, - q7_t * pDst, - q15_t * pScratch1, - q15_t * pScratch2); - - - /** - * @brief Correlation of Q7 sequences. - * @param[in] pSrcA points to the first input sequence. - * @param[in] srcALen length of the first input sequence. - * @param[in] pSrcB points to the second input sequence. - * @param[in] srcBLen length of the second input sequence. - * @param[out] pDst points to the block of output data Length 2 * max(srcALen, srcBLen) - 1. - */ - void arm_correlate_q7( - q7_t * pSrcA, - uint32_t srcALen, - q7_t * pSrcB, - uint32_t srcBLen, - q7_t * pDst); - - - /** - * @brief Instance structure for the floating-point sparse FIR filter. - */ - typedef struct - { - uint16_t numTaps; /**< number of coefficients in the filter. */ - uint16_t stateIndex; /**< state buffer index. Points to the oldest sample in the state buffer. */ - float32_t *pState; /**< points to the state buffer array. The array is of length maxDelay+blockSize-1. */ - float32_t *pCoeffs; /**< points to the coefficient array. The array is of length numTaps.*/ - uint16_t maxDelay; /**< maximum offset specified by the pTapDelay array. */ - int32_t *pTapDelay; /**< points to the array of delay values. The array is of length numTaps. */ - } arm_fir_sparse_instance_f32; - - /** - * @brief Instance structure for the Q31 sparse FIR filter. - */ - typedef struct - { - uint16_t numTaps; /**< number of coefficients in the filter. */ - uint16_t stateIndex; /**< state buffer index. Points to the oldest sample in the state buffer. */ - q31_t *pState; /**< points to the state buffer array. The array is of length maxDelay+blockSize-1. */ - q31_t *pCoeffs; /**< points to the coefficient array. The array is of length numTaps.*/ - uint16_t maxDelay; /**< maximum offset specified by the pTapDelay array. */ - int32_t *pTapDelay; /**< points to the array of delay values. The array is of length numTaps. */ - } arm_fir_sparse_instance_q31; - - /** - * @brief Instance structure for the Q15 sparse FIR filter. - */ - typedef struct - { - uint16_t numTaps; /**< number of coefficients in the filter. */ - uint16_t stateIndex; /**< state buffer index. Points to the oldest sample in the state buffer. */ - q15_t *pState; /**< points to the state buffer array. The array is of length maxDelay+blockSize-1. */ - q15_t *pCoeffs; /**< points to the coefficient array. The array is of length numTaps.*/ - uint16_t maxDelay; /**< maximum offset specified by the pTapDelay array. */ - int32_t *pTapDelay; /**< points to the array of delay values. The array is of length numTaps. */ - } arm_fir_sparse_instance_q15; - - /** - * @brief Instance structure for the Q7 sparse FIR filter. - */ - typedef struct - { - uint16_t numTaps; /**< number of coefficients in the filter. */ - uint16_t stateIndex; /**< state buffer index. Points to the oldest sample in the state buffer. */ - q7_t *pState; /**< points to the state buffer array. The array is of length maxDelay+blockSize-1. */ - q7_t *pCoeffs; /**< points to the coefficient array. The array is of length numTaps.*/ - uint16_t maxDelay; /**< maximum offset specified by the pTapDelay array. */ - int32_t *pTapDelay; /**< points to the array of delay values. The array is of length numTaps. */ - } arm_fir_sparse_instance_q7; - - - /** - * @brief Processing function for the floating-point sparse FIR filter. - * @param[in] S points to an instance of the floating-point sparse FIR structure. - * @param[in] pSrc points to the block of input data. - * @param[out] pDst points to the block of output data - * @param[in] pScratchIn points to a temporary buffer of size blockSize. - * @param[in] blockSize number of input samples to process per call. - */ - void arm_fir_sparse_f32( - arm_fir_sparse_instance_f32 * S, - float32_t * pSrc, - float32_t * pDst, - float32_t * pScratchIn, - uint32_t blockSize); - - - /** - * @brief Initialization function for the floating-point sparse FIR filter. - * @param[in,out] S points to an instance of the floating-point sparse FIR structure. - * @param[in] numTaps number of nonzero coefficients in the filter. - * @param[in] pCoeffs points to the array of filter coefficients. - * @param[in] pState points to the state buffer. - * @param[in] pTapDelay points to the array of offset times. - * @param[in] maxDelay maximum offset time supported. - * @param[in] blockSize number of samples that will be processed per block. - */ - void arm_fir_sparse_init_f32( - arm_fir_sparse_instance_f32 * S, - uint16_t numTaps, - float32_t * pCoeffs, - float32_t * pState, - int32_t * pTapDelay, - uint16_t maxDelay, - uint32_t blockSize); - - - /** - * @brief Processing function for the Q31 sparse FIR filter. - * @param[in] S points to an instance of the Q31 sparse FIR structure. - * @param[in] pSrc points to the block of input data. - * @param[out] pDst points to the block of output data - * @param[in] pScratchIn points to a temporary buffer of size blockSize. - * @param[in] blockSize number of input samples to process per call. - */ - void arm_fir_sparse_q31( - arm_fir_sparse_instance_q31 * S, - q31_t * pSrc, - q31_t * pDst, - q31_t * pScratchIn, - uint32_t blockSize); - - - /** - * @brief Initialization function for the Q31 sparse FIR filter. - * @param[in,out] S points to an instance of the Q31 sparse FIR structure. - * @param[in] numTaps number of nonzero coefficients in the filter. - * @param[in] pCoeffs points to the array of filter coefficients. - * @param[in] pState points to the state buffer. - * @param[in] pTapDelay points to the array of offset times. - * @param[in] maxDelay maximum offset time supported. - * @param[in] blockSize number of samples that will be processed per block. - */ - void arm_fir_sparse_init_q31( - arm_fir_sparse_instance_q31 * S, - uint16_t numTaps, - q31_t * pCoeffs, - q31_t * pState, - int32_t * pTapDelay, - uint16_t maxDelay, - uint32_t blockSize); - - - /** - * @brief Processing function for the Q15 sparse FIR filter. - * @param[in] S points to an instance of the Q15 sparse FIR structure. - * @param[in] pSrc points to the block of input data. - * @param[out] pDst points to the block of output data - * @param[in] pScratchIn points to a temporary buffer of size blockSize. - * @param[in] pScratchOut points to a temporary buffer of size blockSize. - * @param[in] blockSize number of input samples to process per call. - */ - void arm_fir_sparse_q15( - arm_fir_sparse_instance_q15 * S, - q15_t * pSrc, - q15_t * pDst, - q15_t * pScratchIn, - q31_t * pScratchOut, - uint32_t blockSize); - - - /** - * @brief Initialization function for the Q15 sparse FIR filter. - * @param[in,out] S points to an instance of the Q15 sparse FIR structure. - * @param[in] numTaps number of nonzero coefficients in the filter. - * @param[in] pCoeffs points to the array of filter coefficients. - * @param[in] pState points to the state buffer. - * @param[in] pTapDelay points to the array of offset times. - * @param[in] maxDelay maximum offset time supported. - * @param[in] blockSize number of samples that will be processed per block. - */ - void arm_fir_sparse_init_q15( - arm_fir_sparse_instance_q15 * S, - uint16_t numTaps, - q15_t * pCoeffs, - q15_t * pState, - int32_t * pTapDelay, - uint16_t maxDelay, - uint32_t blockSize); - - - /** - * @brief Processing function for the Q7 sparse FIR filter. - * @param[in] S points to an instance of the Q7 sparse FIR structure. - * @param[in] pSrc points to the block of input data. - * @param[out] pDst points to the block of output data - * @param[in] pScratchIn points to a temporary buffer of size blockSize. - * @param[in] pScratchOut points to a temporary buffer of size blockSize. - * @param[in] blockSize number of input samples to process per call. - */ - void arm_fir_sparse_q7( - arm_fir_sparse_instance_q7 * S, - q7_t * pSrc, - q7_t * pDst, - q7_t * pScratchIn, - q31_t * pScratchOut, - uint32_t blockSize); - - - /** - * @brief Initialization function for the Q7 sparse FIR filter. - * @param[in,out] S points to an instance of the Q7 sparse FIR structure. - * @param[in] numTaps number of nonzero coefficients in the filter. - * @param[in] pCoeffs points to the array of filter coefficients. - * @param[in] pState points to the state buffer. - * @param[in] pTapDelay points to the array of offset times. - * @param[in] maxDelay maximum offset time supported. - * @param[in] blockSize number of samples that will be processed per block. - */ - void arm_fir_sparse_init_q7( - arm_fir_sparse_instance_q7 * S, - uint16_t numTaps, - q7_t * pCoeffs, - q7_t * pState, - int32_t * pTapDelay, - uint16_t maxDelay, - uint32_t blockSize); - - - /** - * @brief Floating-point sin_cos function. - * @param[in] theta input value in degrees - * @param[out] pSinVal points to the processed sine output. - * @param[out] pCosVal points to the processed cos output. - */ - void arm_sin_cos_f32( - float32_t theta, - float32_t * pSinVal, - float32_t * pCosVal); - - - /** - * @brief Q31 sin_cos function. - * @param[in] theta scaled input value in degrees - * @param[out] pSinVal points to the processed sine output. - * @param[out] pCosVal points to the processed cosine output. - */ - void arm_sin_cos_q31( - q31_t theta, - q31_t * pSinVal, - q31_t * pCosVal); - - - /** - * @brief Floating-point complex conjugate. - * @param[in] pSrc points to the input vector - * @param[out] pDst points to the output vector - * @param[in] numSamples number of complex samples in each vector - */ - void arm_cmplx_conj_f32( - float32_t * pSrc, - float32_t * pDst, - uint32_t numSamples); - - /** - * @brief Q31 complex conjugate. - * @param[in] pSrc points to the input vector - * @param[out] pDst points to the output vector - * @param[in] numSamples number of complex samples in each vector - */ - void arm_cmplx_conj_q31( - q31_t * pSrc, - q31_t * pDst, - uint32_t numSamples); - - - /** - * @brief Q15 complex conjugate. - * @param[in] pSrc points to the input vector - * @param[out] pDst points to the output vector - * @param[in] numSamples number of complex samples in each vector - */ - void arm_cmplx_conj_q15( - q15_t * pSrc, - q15_t * pDst, - uint32_t numSamples); - - - /** - * @brief Floating-point complex magnitude squared - * @param[in] pSrc points to the complex input vector - * @param[out] pDst points to the real output vector - * @param[in] numSamples number of complex samples in the input vector - */ - void arm_cmplx_mag_squared_f32( - float32_t * pSrc, - float32_t * pDst, - uint32_t numSamples); - - - /** - * @brief Q31 complex magnitude squared - * @param[in] pSrc points to the complex input vector - * @param[out] pDst points to the real output vector - * @param[in] numSamples number of complex samples in the input vector - */ - void arm_cmplx_mag_squared_q31( - q31_t * pSrc, - q31_t * pDst, - uint32_t numSamples); - - - /** - * @brief Q15 complex magnitude squared - * @param[in] pSrc points to the complex input vector - * @param[out] pDst points to the real output vector - * @param[in] numSamples number of complex samples in the input vector - */ - void arm_cmplx_mag_squared_q15( - q15_t * pSrc, - q15_t * pDst, - uint32_t numSamples); - - - /** - * @ingroup groupController - */ - - /** - * @defgroup PID PID Motor Control - * - * A Proportional Integral Derivative (PID) controller is a generic feedback control - * loop mechanism widely used in industrial control systems. - * A PID controller is the most commonly used type of feedback controller. - * - * This set of functions implements (PID) controllers - * for Q15, Q31, and floating-point data types. The functions operate on a single sample - * of data and each call to the function returns a single processed value. - * S points to an instance of the PID control data structure. in - * is the input sample value. The functions return the output value. - * - * \par Algorithm: - * 
-   *    y[n] = y[n-1] + A0 * x[n] + A1 * x[n-1] + A2 * x[n-2]
-   *    A0 = Kp + Ki + Kd
-   *    A1 = (-Kp ) - (2 * Kd )
-   *    A2 = Kd
- * - * \par - * where \c Kp is proportional constant, \c Ki is Integral constant and \c Kd is Derivative constant - * - * \par - * \image html PID.gif "Proportional Integral Derivative Controller" - * - * \par - * The PID controller calculates an "error" value as the difference between - * the measured output and the reference input. - * The controller attempts to minimize the error by adjusting the process control inputs. - * The proportional value determines the reaction to the current error, - * the integral value determines the reaction based on the sum of recent errors, - * and the derivative value determines the reaction based on the rate at which the error has been changing. - * - * \par Instance Structure - * The Gains A0, A1, A2 and state variables for a PID controller are stored together in an instance data structure. - * A separate instance structure must be defined for each PID Controller. - * There are separate instance structure declarations for each of the 3 supported data types. - * - * \par Reset Functions - * There is also an associated reset function for each data type which clears the state array. - * - * \par Initialization Functions - * There is also an associated initialization function for each data type. - * The initialization function performs the following operations: - * - Initializes the Gains A0, A1, A2 from Kp,Ki, Kd gains. - * - Zeros out the values in the state buffer. - * - * \par - * Instance structure cannot be placed into a const data section and it is recommended to use the initialization function. - * - * \par Fixed-Point Behavior - * Care must be taken when using the fixed-point versions of the PID Controller functions. - * In particular, the overflow and saturation behavior of the accumulator used in each function must be considered. - * Refer to the function specific documentation below for usage guidelines. - */ - - /** - * @addtogroup PID - * @{ - */ - - /** - * @brief Process function for the floating-point PID Control. - * @param[in,out] S is an instance of the floating-point PID Control structure - * @param[in] in input sample to process - * @return out processed output sample. - */ - CMSIS_INLINE __STATIC_INLINE float32_t arm_pid_f32( - arm_pid_instance_f32 * S, - float32_t in) - { - float32_t out; - - /* y[n] = y[n-1] + A0 * x[n] + A1 * x[n-1] + A2 * x[n-2] */ - out = (S->A0 * in) + - (S->A1 * S->state[0]) + (S->A2 * S->state[1]) + (S->state[2]); - - /* Update state */ - S->state[1] = S->state[0]; - S->state[0] = in; - S->state[2] = out; - - /* return to application */ - return (out); - - } - - /** - * @brief Process function for the Q31 PID Control. - * @param[in,out] S points to an instance of the Q31 PID Control structure - * @param[in] in input sample to process - * @return out processed output sample. - * - * Scaling and Overflow Behavior: - * \par - * The function is implemented using an internal 64-bit accumulator. - * The accumulator has a 2.62 format and maintains full precision of the intermediate multiplication results but provides only a single guard bit. - * Thus, if the accumulator result overflows it wraps around rather than clip. - * In order to avoid overflows completely the input signal must be scaled down by 2 bits as there are four additions. - * After all multiply-accumulates are performed, the 2.62 accumulator is truncated to 1.32 format and then saturated to 1.31 format. - */ - CMSIS_INLINE __STATIC_INLINE q31_t arm_pid_q31( - arm_pid_instance_q31 * S, - q31_t in) - { - q63_t acc; - q31_t out; - - /* acc = A0 * x[n] */ - acc = (q63_t) S->A0 * in; - - /* acc += A1 * x[n-1] */ - acc += (q63_t) S->A1 * S->state[0]; - - /* acc += A2 * x[n-2] */ - acc += (q63_t) S->A2 * S->state[1]; - - /* convert output to 1.31 format to add y[n-1] */ - out = (q31_t) (acc >> 31U); - - /* out += y[n-1] */ - out += S->state[2]; - - /* Update state */ - S->state[1] = S->state[0]; - S->state[0] = in; - S->state[2] = out; - - /* return to application */ - return (out); - } - - - /** - * @brief Process function for the Q15 PID Control. - * @param[in,out] S points to an instance of the Q15 PID Control structure - * @param[in] in input sample to process - * @return out processed output sample. - * - * Scaling and Overflow Behavior: - * \par - * The function is implemented using a 64-bit internal accumulator. - * Both Gains and state variables are represented in 1.15 format and multiplications yield a 2.30 result. - * The 2.30 intermediate results are accumulated in a 64-bit accumulator in 34.30 format. - * There is no risk of internal overflow with this approach and the full precision of intermediate multiplications is preserved. - * After all additions have been performed, the accumulator is truncated to 34.15 format by discarding low 15 bits. - * Lastly, the accumulator is saturated to yield a result in 1.15 format. - */ - CMSIS_INLINE __STATIC_INLINE q15_t arm_pid_q15( - arm_pid_instance_q15 * S, - q15_t in) - { - q63_t acc; - q15_t out; - -#if defined (ARM_MATH_DSP) - __SIMD32_TYPE *vstate; - - /* Implementation of PID controller */ - - /* acc = A0 * x[n] */ - acc = (q31_t) __SMUAD((uint32_t)S->A0, (uint32_t)in); - - /* acc += A1 * x[n-1] + A2 * x[n-2] */ - vstate = __SIMD32_CONST(S->state); - acc = (q63_t)__SMLALD((uint32_t)S->A1, (uint32_t)*vstate, (uint64_t)acc); -#else - /* acc = A0 * x[n] */ - acc = ((q31_t) S->A0) * in; - - /* acc += A1 * x[n-1] + A2 * x[n-2] */ - acc += (q31_t) S->A1 * S->state[0]; - acc += (q31_t) S->A2 * S->state[1]; -#endif - - /* acc += y[n-1] */ - acc += (q31_t) S->state[2] << 15; - - /* saturate the output */ - out = (q15_t) (__SSAT((acc >> 15), 16)); - - /* Update state */ - S->state[1] = S->state[0]; - S->state[0] = in; - S->state[2] = out; - - /* return to application */ - return (out); - } - - /** - * @} end of PID group - */ - - - /** - * @brief Floating-point matrix inverse. - * @param[in] src points to the instance of the input floating-point matrix structure. - * @param[out] dst points to the instance of the output floating-point matrix structure. - * @return The function returns ARM_MATH_SIZE_MISMATCH, if the dimensions do not match. - * If the input matrix is singular (does not have an inverse), then the algorithm terminates and returns error status ARM_MATH_SINGULAR. - */ - arm_status arm_mat_inverse_f32( - const arm_matrix_instance_f32 * src, - arm_matrix_instance_f32 * dst); - - - /** - * @brief Floating-point matrix inverse. - * @param[in] src points to the instance of the input floating-point matrix structure. - * @param[out] dst points to the instance of the output floating-point matrix structure. - * @return The function returns ARM_MATH_SIZE_MISMATCH, if the dimensions do not match. - * If the input matrix is singular (does not have an inverse), then the algorithm terminates and returns error status ARM_MATH_SINGULAR. - */ - arm_status arm_mat_inverse_f64( - const arm_matrix_instance_f64 * src, - arm_matrix_instance_f64 * dst); - - - - /** - * @ingroup groupController - */ - - /** - * @defgroup clarke Vector Clarke Transform - * Forward Clarke transform converts the instantaneous stator phases into a two-coordinate time invariant vector. - * Generally the Clarke transform uses three-phase currents Ia, Ib and Ic to calculate currents - * in the two-phase orthogonal stator axis Ialpha and Ibeta. - * When Ialpha is superposed with Ia as shown in the figure below - * \image html clarke.gif Stator current space vector and its components in (a,b). - * and Ia + Ib + Ic = 0, in this condition Ialpha and Ibeta - * can be calculated using only Ia and Ib. - * - * The function operates on a single sample of data and each call to the function returns the processed output. - * The library provides separate functions for Q31 and floating-point data types. - * \par Algorithm - * \image html clarkeFormula.gif - * where Ia and Ib are the instantaneous stator phases and - * pIalpha and pIbeta are the two coordinates of time invariant vector. - * \par Fixed-Point Behavior - * Care must be taken when using the Q31 version of the Clarke transform. - * In particular, the overflow and saturation behavior of the accumulator used must be considered. - * Refer to the function specific documentation below for usage guidelines. - */ - - /** - * @addtogroup clarke - * @{ - */ - - /** - * - * @brief Floating-point Clarke transform - * @param[in] Ia input three-phase coordinate a - * @param[in] Ib input three-phase coordinate b - * @param[out] pIalpha points to output two-phase orthogonal vector axis alpha - * @param[out] pIbeta points to output two-phase orthogonal vector axis beta - */ - CMSIS_INLINE __STATIC_INLINE void arm_clarke_f32( - float32_t Ia, - float32_t Ib, - float32_t * pIalpha, - float32_t * pIbeta) - { - /* Calculate pIalpha using the equation, pIalpha = Ia */ - *pIalpha = Ia; - - /* Calculate pIbeta using the equation, pIbeta = (1/sqrt(3)) * Ia + (2/sqrt(3)) * Ib */ - *pIbeta = ((float32_t) 0.57735026919 * Ia + (float32_t) 1.15470053838 * Ib); - } - - - /** - * @brief Clarke transform for Q31 version - * @param[in] Ia input three-phase coordinate a - * @param[in] Ib input three-phase coordinate b - * @param[out] pIalpha points to output two-phase orthogonal vector axis alpha - * @param[out] pIbeta points to output two-phase orthogonal vector axis beta - * - * Scaling and Overflow Behavior: - * \par - * The function is implemented using an internal 32-bit accumulator. - * The accumulator maintains 1.31 format by truncating lower 31 bits of the intermediate multiplication in 2.62 format. - * There is saturation on the addition, hence there is no risk of overflow. - */ - CMSIS_INLINE __STATIC_INLINE void arm_clarke_q31( - q31_t Ia, - q31_t Ib, - q31_t * pIalpha, - q31_t * pIbeta) - { - q31_t product1, product2; /* Temporary variables used to store intermediate results */ - - /* Calculating pIalpha from Ia by equation pIalpha = Ia */ - *pIalpha = Ia; - - /* Intermediate product is calculated by (1/(sqrt(3)) * Ia) */ - product1 = (q31_t) (((q63_t) Ia * 0x24F34E8B) >> 30); - - /* Intermediate product is calculated by (2/sqrt(3) * Ib) */ - product2 = (q31_t) (((q63_t) Ib * 0x49E69D16) >> 30); - - /* pIbeta is calculated by adding the intermediate products */ - *pIbeta = __QADD(product1, product2); - } - - /** - * @} end of clarke group - */ - - /** - * @brief Converts the elements of the Q7 vector to Q31 vector. - * @param[in] pSrc input pointer - * @param[out] pDst output pointer - * @param[in] blockSize number of samples to process - */ - void arm_q7_to_q31( - q7_t * pSrc, - q31_t * pDst, - uint32_t blockSize); - - - - /** - * @ingroup groupController - */ - - /** - * @defgroup inv_clarke Vector Inverse Clarke Transform - * Inverse Clarke transform converts the two-coordinate time invariant vector into instantaneous stator phases. - * - * The function operates on a single sample of data and each call to the function returns the processed output. - * The library provides separate functions for Q31 and floating-point data types. - * \par Algorithm - * \image html clarkeInvFormula.gif - * where pIa and pIb are the instantaneous stator phases and - * Ialpha and Ibeta are the two coordinates of time invariant vector. - * \par Fixed-Point Behavior - * Care must be taken when using the Q31 version of the Clarke transform. - * In particular, the overflow and saturation behavior of the accumulator used must be considered. - * Refer to the function specific documentation below for usage guidelines. - */ - - /** - * @addtogroup inv_clarke - * @{ - */ - - /** - * @brief Floating-point Inverse Clarke transform - * @param[in] Ialpha input two-phase orthogonal vector axis alpha - * @param[in] Ibeta input two-phase orthogonal vector axis beta - * @param[out] pIa points to output three-phase coordinate a - * @param[out] pIb points to output three-phase coordinate b - */ - CMSIS_INLINE __STATIC_INLINE void arm_inv_clarke_f32( - float32_t Ialpha, - float32_t Ibeta, - float32_t * pIa, - float32_t * pIb) - { - /* Calculating pIa from Ialpha by equation pIa = Ialpha */ - *pIa = Ialpha; - - /* Calculating pIb from Ialpha and Ibeta by equation pIb = -(1/2) * Ialpha + (sqrt(3)/2) * Ibeta */ - *pIb = -0.5f * Ialpha + 0.8660254039f * Ibeta; - } - - - /** - * @brief Inverse Clarke transform for Q31 version - * @param[in] Ialpha input two-phase orthogonal vector axis alpha - * @param[in] Ibeta input two-phase orthogonal vector axis beta - * @param[out] pIa points to output three-phase coordinate a - * @param[out] pIb points to output three-phase coordinate b - * - * Scaling and Overflow Behavior: - * \par - * The function is implemented using an internal 32-bit accumulator. - * The accumulator maintains 1.31 format by truncating lower 31 bits of the intermediate multiplication in 2.62 format. - * There is saturation on the subtraction, hence there is no risk of overflow. - */ - CMSIS_INLINE __STATIC_INLINE void arm_inv_clarke_q31( - q31_t Ialpha, - q31_t Ibeta, - q31_t * pIa, - q31_t * pIb) - { - q31_t product1, product2; /* Temporary variables used to store intermediate results */ - - /* Calculating pIa from Ialpha by equation pIa = Ialpha */ - *pIa = Ialpha; - - /* Intermediate product is calculated by (1/(2*sqrt(3)) * Ia) */ - product1 = (q31_t) (((q63_t) (Ialpha) * (0x40000000)) >> 31); - - /* Intermediate product is calculated by (1/sqrt(3) * pIb) */ - product2 = (q31_t) (((q63_t) (Ibeta) * (0x6ED9EBA1)) >> 31); - - /* pIb is calculated by subtracting the products */ - *pIb = __QSUB(product2, product1); - } - - /** - * @} end of inv_clarke group - */ - - /** - * @brief Converts the elements of the Q7 vector to Q15 vector. - * @param[in] pSrc input pointer - * @param[out] pDst output pointer - * @param[in] blockSize number of samples to process - */ - void arm_q7_to_q15( - q7_t * pSrc, - q15_t * pDst, - uint32_t blockSize); - - - - /** - * @ingroup groupController - */ - - /** - * @defgroup park Vector Park Transform - * - * Forward Park transform converts the input two-coordinate vector to flux and torque components. - * The Park transform can be used to realize the transformation of the Ialpha and the Ibeta currents - * from the stationary to the moving reference frame and control the spatial relationship between - * the stator vector current and rotor flux vector. - * If we consider the d axis aligned with the rotor flux, the diagram below shows the - * current vector and the relationship from the two reference frames: - * \image html park.gif "Stator current space vector and its component in (a,b) and in the d,q rotating reference frame" - * - * The function operates on a single sample of data and each call to the function returns the processed output. - * The library provides separate functions for Q31 and floating-point data types. - * \par Algorithm - * \image html parkFormula.gif - * where Ialpha and Ibeta are the stator vector components, - * pId and pIq are rotor vector components and cosVal and sinVal are the - * cosine and sine values of theta (rotor flux position). - * \par Fixed-Point Behavior - * Care must be taken when using the Q31 version of the Park transform. - * In particular, the overflow and saturation behavior of the accumulator used must be considered. - * Refer to the function specific documentation below for usage guidelines. - */ - - /** - * @addtogroup park - * @{ - */ - - /** - * @brief Floating-point Park transform - * @param[in] Ialpha input two-phase vector coordinate alpha - * @param[in] Ibeta input two-phase vector coordinate beta - * @param[out] pId points to output rotor reference frame d - * @param[out] pIq points to output rotor reference frame q - * @param[in] sinVal sine value of rotation angle theta - * @param[in] cosVal cosine value of rotation angle theta - * - * The function implements the forward Park transform. - * - */ - CMSIS_INLINE __STATIC_INLINE void arm_park_f32( - float32_t Ialpha, - float32_t Ibeta, - float32_t * pId, - float32_t * pIq, - float32_t sinVal, - float32_t cosVal) - { - /* Calculate pId using the equation, pId = Ialpha * cosVal + Ibeta * sinVal */ - *pId = Ialpha * cosVal + Ibeta * sinVal; - - /* Calculate pIq using the equation, pIq = - Ialpha * sinVal + Ibeta * cosVal */ - *pIq = -Ialpha * sinVal + Ibeta * cosVal; - } - - - /** - * @brief Park transform for Q31 version - * @param[in] Ialpha input two-phase vector coordinate alpha - * @param[in] Ibeta input two-phase vector coordinate beta - * @param[out] pId points to output rotor reference frame d - * @param[out] pIq points to output rotor reference frame q - * @param[in] sinVal sine value of rotation angle theta - * @param[in] cosVal cosine value of rotation angle theta - * - * Scaling and Overflow Behavior: - * \par - * The function is implemented using an internal 32-bit accumulator. - * The accumulator maintains 1.31 format by truncating lower 31 bits of the intermediate multiplication in 2.62 format. - * There is saturation on the addition and subtraction, hence there is no risk of overflow. - */ - CMSIS_INLINE __STATIC_INLINE void arm_park_q31( - q31_t Ialpha, - q31_t Ibeta, - q31_t * pId, - q31_t * pIq, - q31_t sinVal, - q31_t cosVal) - { - q31_t product1, product2; /* Temporary variables used to store intermediate results */ - q31_t product3, product4; /* Temporary variables used to store intermediate results */ - - /* Intermediate product is calculated by (Ialpha * cosVal) */ - product1 = (q31_t) (((q63_t) (Ialpha) * (cosVal)) >> 31); - - /* Intermediate product is calculated by (Ibeta * sinVal) */ - product2 = (q31_t) (((q63_t) (Ibeta) * (sinVal)) >> 31); - - - /* Intermediate product is calculated by (Ialpha * sinVal) */ - product3 = (q31_t) (((q63_t) (Ialpha) * (sinVal)) >> 31); - - /* Intermediate product is calculated by (Ibeta * cosVal) */ - product4 = (q31_t) (((q63_t) (Ibeta) * (cosVal)) >> 31); - - /* Calculate pId by adding the two intermediate products 1 and 2 */ - *pId = __QADD(product1, product2); - - /* Calculate pIq by subtracting the two intermediate products 3 from 4 */ - *pIq = __QSUB(product4, product3); - } - - /** - * @} end of park group - */ - - /** - * @brief Converts the elements of the Q7 vector to floating-point vector. - * @param[in] pSrc is input pointer - * @param[out] pDst is output pointer - * @param[in] blockSize is the number of samples to process - */ - void arm_q7_to_float( - q7_t * pSrc, - float32_t * pDst, - uint32_t blockSize); - - - /** - * @ingroup groupController - */ - - /** - * @defgroup inv_park Vector Inverse Park transform - * Inverse Park transform converts the input flux and torque components to two-coordinate vector. - * - * The function operates on a single sample of data and each call to the function returns the processed output. - * The library provides separate functions for Q31 and floating-point data types. - * \par Algorithm - * \image html parkInvFormula.gif - * where pIalpha and pIbeta are the stator vector components, - * Id and Iq are rotor vector components and cosVal and sinVal are the - * cosine and sine values of theta (rotor flux position). - * \par Fixed-Point Behavior - * Care must be taken when using the Q31 version of the Park transform. - * In particular, the overflow and saturation behavior of the accumulator used must be considered. - * Refer to the function specific documentation below for usage guidelines. - */ - - /** - * @addtogroup inv_park - * @{ - */ - - /** - * @brief Floating-point Inverse Park transform - * @param[in] Id input coordinate of rotor reference frame d - * @param[in] Iq input coordinate of rotor reference frame q - * @param[out] pIalpha points to output two-phase orthogonal vector axis alpha - * @param[out] pIbeta points to output two-phase orthogonal vector axis beta - * @param[in] sinVal sine value of rotation angle theta - * @param[in] cosVal cosine value of rotation angle theta - */ - CMSIS_INLINE __STATIC_INLINE void arm_inv_park_f32( - float32_t Id, - float32_t Iq, - float32_t * pIalpha, - float32_t * pIbeta, - float32_t sinVal, - float32_t cosVal) - { - /* Calculate pIalpha using the equation, pIalpha = Id * cosVal - Iq * sinVal */ - *pIalpha = Id * cosVal - Iq * sinVal; - - /* Calculate pIbeta using the equation, pIbeta = Id * sinVal + Iq * cosVal */ - *pIbeta = Id * sinVal + Iq * cosVal; - } - - - /** - * @brief Inverse Park transform for Q31 version - * @param[in] Id input coordinate of rotor reference frame d - * @param[in] Iq input coordinate of rotor reference frame q - * @param[out] pIalpha points to output two-phase orthogonal vector axis alpha - * @param[out] pIbeta points to output two-phase orthogonal vector axis beta - * @param[in] sinVal sine value of rotation angle theta - * @param[in] cosVal cosine value of rotation angle theta - * - * Scaling and Overflow Behavior: - * \par - * The function is implemented using an internal 32-bit accumulator. - * The accumulator maintains 1.31 format by truncating lower 31 bits of the intermediate multiplication in 2.62 format. - * There is saturation on the addition, hence there is no risk of overflow. - */ - CMSIS_INLINE __STATIC_INLINE void arm_inv_park_q31( - q31_t Id, - q31_t Iq, - q31_t * pIalpha, - q31_t * pIbeta, - q31_t sinVal, - q31_t cosVal) - { - q31_t product1, product2; /* Temporary variables used to store intermediate results */ - q31_t product3, product4; /* Temporary variables used to store intermediate results */ - - /* Intermediate product is calculated by (Id * cosVal) */ - product1 = (q31_t) (((q63_t) (Id) * (cosVal)) >> 31); - - /* Intermediate product is calculated by (Iq * sinVal) */ - product2 = (q31_t) (((q63_t) (Iq) * (sinVal)) >> 31); - - - /* Intermediate product is calculated by (Id * sinVal) */ - product3 = (q31_t) (((q63_t) (Id) * (sinVal)) >> 31); - - /* Intermediate product is calculated by (Iq * cosVal) */ - product4 = (q31_t) (((q63_t) (Iq) * (cosVal)) >> 31); - - /* Calculate pIalpha by using the two intermediate products 1 and 2 */ - *pIalpha = __QSUB(product1, product2); - - /* Calculate pIbeta by using the two intermediate products 3 and 4 */ - *pIbeta = __QADD(product4, product3); - } - - /** - * @} end of Inverse park group - */ - - - /** - * @brief Converts the elements of the Q31 vector to floating-point vector. - * @param[in] pSrc is input pointer - * @param[out] pDst is output pointer - * @param[in] blockSize is the number of samples to process - */ - void arm_q31_to_float( - q31_t * pSrc, - float32_t * pDst, - uint32_t blockSize); - - /** - * @ingroup groupInterpolation - */ - - /** - * @defgroup LinearInterpolate Linear Interpolation - * - * Linear interpolation is a method of curve fitting using linear polynomials. - * Linear interpolation works by effectively drawing a straight line between two neighboring samples and returning the appropriate point along that line - * - * \par - * \image html LinearInterp.gif "Linear interpolation" - * - * \par - * A Linear Interpolate function calculates an output value(y), for the input(x) - * using linear interpolation of the input values x0, x1( nearest input values) and the output values y0 and y1(nearest output values) - * - * \par Algorithm: - * 
-   *       y = y0 + (x - x0) * ((y1 - y0)/(x1-x0))
-   *       where x0, x1 are nearest values of input x
-   *             y0, y1 are nearest values to output y
-   *
- * - * \par - * This set of functions implements Linear interpolation process - * for Q7, Q15, Q31, and floating-point data types. The functions operate on a single - * sample of data and each call to the function returns a single processed value. - * S points to an instance of the Linear Interpolate function data structure. - * x is the input sample value. The functions returns the output value. - * - * \par - * if x is outside of the table boundary, Linear interpolation returns first value of the table - * if x is below input range and returns last value of table if x is above range. - */ - - /** - * @addtogroup LinearInterpolate - * @{ - */ - - /** - * @brief Process function for the floating-point Linear Interpolation Function. - * @param[in,out] S is an instance of the floating-point Linear Interpolation structure - * @param[in] x input sample to process - * @return y processed output sample. - * - */ - CMSIS_INLINE __STATIC_INLINE float32_t arm_linear_interp_f32( - arm_linear_interp_instance_f32 * S, - float32_t x) - { - float32_t y; - float32_t x0, x1; /* Nearest input values */ - float32_t y0, y1; /* Nearest output values */ - float32_t xSpacing = S->xSpacing; /* spacing between input values */ - int32_t i; /* Index variable */ - float32_t *pYData = S->pYData; /* pointer to output table */ - - /* Calculation of index */ - i = (int32_t) ((x - S->x1) / xSpacing); - - if (i < 0) - { - /* Iniatilize output for below specified range as least output value of table */ - y = pYData[0]; - } - else if ((uint32_t)i >= S->nValues) - { - /* Iniatilize output for above specified range as last output value of table */ - y = pYData[S->nValues - 1]; - } - else - { - /* Calculation of nearest input values */ - x0 = S->x1 + i * xSpacing; - x1 = S->x1 + (i + 1) * xSpacing; - - /* Read of nearest output values */ - y0 = pYData[i]; - y1 = pYData[i + 1]; - - /* Calculation of output */ - y = y0 + (x - x0) * ((y1 - y0) / (x1 - x0)); - - } - - /* returns output value */ - return (y); - } - - - /** - * - * @brief Process function for the Q31 Linear Interpolation Function. - * @param[in] pYData pointer to Q31 Linear Interpolation table - * @param[in] x input sample to process - * @param[in] nValues number of table values - * @return y processed output sample. - * - * \par - * Input sample x is in 12.20 format which contains 12 bits for table index and 20 bits for fractional part. - * This function can support maximum of table size 2^12. - * - */ - CMSIS_INLINE __STATIC_INLINE q31_t arm_linear_interp_q31( - q31_t * pYData, - q31_t x, - uint32_t nValues) - { - q31_t y; /* output */ - q31_t y0, y1; /* Nearest output values */ - q31_t fract; /* fractional part */ - int32_t index; /* Index to read nearest output values */ - - /* Input is in 12.20 format */ - /* 12 bits for the table index */ - /* Index value calculation */ - index = ((x & (q31_t)0xFFF00000) >> 20); - - if (index >= (int32_t)(nValues - 1)) - { - return (pYData[nValues - 1]); - } - else if (index < 0) - { - return (pYData[0]); - } - else - { - /* 20 bits for the fractional part */ - /* shift left by 11 to keep fract in 1.31 format */ - fract = (x & 0x000FFFFF) << 11; - - /* Read two nearest output values from the index in 1.31(q31) format */ - y0 = pYData[index]; - y1 = pYData[index + 1]; - - /* Calculation of y0 * (1-fract) and y is in 2.30 format */ - y = ((q31_t) ((q63_t) y0 * (0x7FFFFFFF - fract) >> 32)); - - /* Calculation of y0 * (1-fract) + y1 *fract and y is in 2.30 format */ - y += ((q31_t) (((q63_t) y1 * fract) >> 32)); - - /* Convert y to 1.31 format */ - return (y << 1U); - } - } - - - /** - * - * @brief Process function for the Q15 Linear Interpolation Function. - * @param[in] pYData pointer to Q15 Linear Interpolation table - * @param[in] x input sample to process - * @param[in] nValues number of table values - * @return y processed output sample. - * - * \par - * Input sample x is in 12.20 format which contains 12 bits for table index and 20 bits for fractional part. - * This function can support maximum of table size 2^12. - * - */ - CMSIS_INLINE __STATIC_INLINE q15_t arm_linear_interp_q15( - q15_t * pYData, - q31_t x, - uint32_t nValues) - { - q63_t y; /* output */ - q15_t y0, y1; /* Nearest output values */ - q31_t fract; /* fractional part */ - int32_t index; /* Index to read nearest output values */ - - /* Input is in 12.20 format */ - /* 12 bits for the table index */ - /* Index value calculation */ - index = ((x & (int32_t)0xFFF00000) >> 20); - - if (index >= (int32_t)(nValues - 1)) - { - return (pYData[nValues - 1]); - } - else if (index < 0) - { - return (pYData[0]); - } - else - { - /* 20 bits for the fractional part */ - /* fract is in 12.20 format */ - fract = (x & 0x000FFFFF); - - /* Read two nearest output values from the index */ - y0 = pYData[index]; - y1 = pYData[index + 1]; - - /* Calculation of y0 * (1-fract) and y is in 13.35 format */ - y = ((q63_t) y0 * (0xFFFFF - fract)); - - /* Calculation of (y0 * (1-fract) + y1 * fract) and y is in 13.35 format */ - y += ((q63_t) y1 * (fract)); - - /* convert y to 1.15 format */ - return (q15_t) (y >> 20); - } - } - - - /** - * - * @brief Process function for the Q7 Linear Interpolation Function. - * @param[in] pYData pointer to Q7 Linear Interpolation table - * @param[in] x input sample to process - * @param[in] nValues number of table values - * @return y processed output sample. - * - * \par - * Input sample x is in 12.20 format which contains 12 bits for table index and 20 bits for fractional part. - * This function can support maximum of table size 2^12. - */ - CMSIS_INLINE __STATIC_INLINE q7_t arm_linear_interp_q7( - q7_t * pYData, - q31_t x, - uint32_t nValues) - { - q31_t y; /* output */ - q7_t y0, y1; /* Nearest output values */ - q31_t fract; /* fractional part */ - uint32_t index; /* Index to read nearest output values */ - - /* Input is in 12.20 format */ - /* 12 bits for the table index */ - /* Index value calculation */ - if (x < 0) - { - return (pYData[0]); - } - index = (x >> 20) & 0xfff; - - if (index >= (nValues - 1)) - { - return (pYData[nValues - 1]); - } - else - { - /* 20 bits for the fractional part */ - /* fract is in 12.20 format */ - fract = (x & 0x000FFFFF); - - /* Read two nearest output values from the index and are in 1.7(q7) format */ - y0 = pYData[index]; - y1 = pYData[index + 1]; - - /* Calculation of y0 * (1-fract ) and y is in 13.27(q27) format */ - y = ((y0 * (0xFFFFF - fract))); - - /* Calculation of y1 * fract + y0 * (1-fract) and y is in 13.27(q27) format */ - y += (y1 * fract); - - /* convert y to 1.7(q7) format */ - return (q7_t) (y >> 20); - } - } - - /** - * @} end of LinearInterpolate group - */ - - /** - * @brief Fast approximation to the trigonometric sine function for floating-point data. - * @param[in] x input value in radians. - * @return sin(x). - */ - float32_t arm_sin_f32( - float32_t x); - - - /** - * @brief Fast approximation to the trigonometric sine function for Q31 data. - * @param[in] x Scaled input value in radians. - * @return sin(x). - */ - q31_t arm_sin_q31( - q31_t x); - - - /** - * @brief Fast approximation to the trigonometric sine function for Q15 data. - * @param[in] x Scaled input value in radians. - * @return sin(x). - */ - q15_t arm_sin_q15( - q15_t x); - - - /** - * @brief Fast approximation to the trigonometric cosine function for floating-point data. - * @param[in] x input value in radians. - * @return cos(x). - */ - float32_t arm_cos_f32( - float32_t x); - - - /** - * @brief Fast approximation to the trigonometric cosine function for Q31 data. - * @param[in] x Scaled input value in radians. - * @return cos(x). - */ - q31_t arm_cos_q31( - q31_t x); - - - /** - * @brief Fast approximation to the trigonometric cosine function for Q15 data. - * @param[in] x Scaled input value in radians. - * @return cos(x). - */ - q15_t arm_cos_q15( - q15_t x); - - - /** - * @ingroup groupFastMath - */ - - - /** - * @defgroup SQRT Square Root - * - * Computes the square root of a number. - * There are separate functions for Q15, Q31, and floating-point data types. - * The square root function is computed using the Newton-Raphson algorithm. - * This is an iterative algorithm of the form: - * 
-   *      x1 = x0 - f(x0)/f'(x0)
-   *
- * where x1 is the current estimate, - * x0 is the previous estimate, and - * f'(x0) is the derivative of f() evaluated at x0. - * For the square root function, the algorithm reduces to: - * 
-   *     x0 = in/2                         [initial guess]
-   *     x1 = 1/2 * ( x0 + in / x0)        [each iteration]
-   *
- */ - - - /** - * @addtogroup SQRT - * @{ - */ - - /** - * @brief Floating-point square root function. - * @param[in] in input value. - * @param[out] pOut square root of input value. - * @return The function returns ARM_MATH_SUCCESS if input value is positive value or ARM_MATH_ARGUMENT_ERROR if - * in is negative value and returns zero output for negative values. - */ - CMSIS_INLINE __STATIC_INLINE arm_status arm_sqrt_f32( - float32_t in, - float32_t * pOut) - { - if (in >= 0.0f) - { - -#if (__FPU_USED == 1) && defined ( __CC_ARM ) - *pOut = __sqrtf(in); -#elif (__FPU_USED == 1) && (defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)) - *pOut = __builtin_sqrtf(in); -#elif (__FPU_USED == 1) && defined(__GNUC__) - *pOut = __builtin_sqrtf(in); -#elif (__FPU_USED == 1) && defined ( __ICCARM__ ) && (__VER__ >= 6040000) - __ASM("VSQRT.F32 %0,%1" : "=t"(*pOut) : "t"(in)); -#else - *pOut = sqrtf(in); -#endif - - return (ARM_MATH_SUCCESS); - } - else - { - *pOut = 0.0f; - return (ARM_MATH_ARGUMENT_ERROR); - } - } - - - /** - * @brief Q31 square root function. - * @param[in] in input value. The range of the input value is [0 +1) or 0x00000000 to 0x7FFFFFFF. - * @param[out] pOut square root of input value. - * @return The function returns ARM_MATH_SUCCESS if input value is positive value or ARM_MATH_ARGUMENT_ERROR if - * in is negative value and returns zero output for negative values. - */ - arm_status arm_sqrt_q31( - q31_t in, - q31_t * pOut); - - - /** - * @brief Q15 square root function. - * @param[in] in input value. The range of the input value is [0 +1) or 0x0000 to 0x7FFF. - * @param[out] pOut square root of input value. - * @return The function returns ARM_MATH_SUCCESS if input value is positive value or ARM_MATH_ARGUMENT_ERROR if - * in is negative value and returns zero output for negative values. - */ - arm_status arm_sqrt_q15( - q15_t in, - q15_t * pOut); - - /** - * @} end of SQRT group - */ - - - /** - * @brief floating-point Circular write function. - */ - CMSIS_INLINE __STATIC_INLINE void arm_circularWrite_f32( - int32_t * circBuffer, - int32_t L, - uint16_t * writeOffset, - int32_t bufferInc, - const int32_t * src, - int32_t srcInc, - uint32_t blockSize) - { - uint32_t i = 0U; - int32_t wOffset; - - /* Copy the value of Index pointer that points - * to the current location where the input samples to be copied */ - wOffset = *writeOffset; - - /* Loop over the blockSize */ - i = blockSize; - - while (i > 0U) - { - /* copy the input sample to the circular buffer */ - circBuffer[wOffset] = *src; - - /* Update the input pointer */ - src += srcInc; - - /* Circularly update wOffset. Watch out for positive and negative value */ - wOffset += bufferInc; - if (wOffset >= L) - wOffset -= L; - - /* Decrement the loop counter */ - i--; - } - - /* Update the index pointer */ - *writeOffset = (uint16_t)wOffset; - } - - - - /** - * @brief floating-point Circular Read function. - */ - CMSIS_INLINE __STATIC_INLINE void arm_circularRead_f32( - int32_t * circBuffer, - int32_t L, - int32_t * readOffset, - int32_t bufferInc, - int32_t * dst, - int32_t * dst_base, - int32_t dst_length, - int32_t dstInc, - uint32_t blockSize) - { - uint32_t i = 0U; - int32_t rOffset, dst_end; - - /* Copy the value of Index pointer that points - * to the current location from where the input samples to be read */ - rOffset = *readOffset; - dst_end = (int32_t) (dst_base + dst_length); - - /* Loop over the blockSize */ - i = blockSize; - - while (i > 0U) - { - /* copy the sample from the circular buffer to the destination buffer */ - *dst = circBuffer[rOffset]; - - /* Update the input pointer */ - dst += dstInc; - - if (dst == (int32_t *) dst_end) - { - dst = dst_base; - } - - /* Circularly update rOffset. Watch out for positive and negative value */ - rOffset += bufferInc; - - if (rOffset >= L) - { - rOffset -= L; - } - - /* Decrement the loop counter */ - i--; - } - - /* Update the index pointer */ - *readOffset = rOffset; - } - - - /** - * @brief Q15 Circular write function. - */ - CMSIS_INLINE __STATIC_INLINE void arm_circularWrite_q15( - q15_t * circBuffer, - int32_t L, - uint16_t * writeOffset, - int32_t bufferInc, - const q15_t * src, - int32_t srcInc, - uint32_t blockSize) - { - uint32_t i = 0U; - int32_t wOffset; - - /* Copy the value of Index pointer that points - * to the current location where the input samples to be copied */ - wOffset = *writeOffset; - - /* Loop over the blockSize */ - i = blockSize; - - while (i > 0U) - { - /* copy the input sample to the circular buffer */ - circBuffer[wOffset] = *src; - - /* Update the input pointer */ - src += srcInc; - - /* Circularly update wOffset. Watch out for positive and negative value */ - wOffset += bufferInc; - if (wOffset >= L) - wOffset -= L; - - /* Decrement the loop counter */ - i--; - } - - /* Update the index pointer */ - *writeOffset = (uint16_t)wOffset; - } - - - /** - * @brief Q15 Circular Read function. - */ - CMSIS_INLINE __STATIC_INLINE void arm_circularRead_q15( - q15_t * circBuffer, - int32_t L, - int32_t * readOffset, - int32_t bufferInc, - q15_t * dst, - q15_t * dst_base, - int32_t dst_length, - int32_t dstInc, - uint32_t blockSize) - { - uint32_t i = 0; - int32_t rOffset, dst_end; - - /* Copy the value of Index pointer that points - * to the current location from where the input samples to be read */ - rOffset = *readOffset; - - dst_end = (int32_t) (dst_base + dst_length); - - /* Loop over the blockSize */ - i = blockSize; - - while (i > 0U) - { - /* copy the sample from the circular buffer to the destination buffer */ - *dst = circBuffer[rOffset]; - - /* Update the input pointer */ - dst += dstInc; - - if (dst == (q15_t *) dst_end) - { - dst = dst_base; - } - - /* Circularly update wOffset. Watch out for positive and negative value */ - rOffset += bufferInc; - - if (rOffset >= L) - { - rOffset -= L; - } - - /* Decrement the loop counter */ - i--; - } - - /* Update the index pointer */ - *readOffset = rOffset; - } - - - /** - * @brief Q7 Circular write function. - */ - CMSIS_INLINE __STATIC_INLINE void arm_circularWrite_q7( - q7_t * circBuffer, - int32_t L, - uint16_t * writeOffset, - int32_t bufferInc, - const q7_t * src, - int32_t srcInc, - uint32_t blockSize) - { - uint32_t i = 0U; - int32_t wOffset; - - /* Copy the value of Index pointer that points - * to the current location where the input samples to be copied */ - wOffset = *writeOffset; - - /* Loop over the blockSize */ - i = blockSize; - - while (i > 0U) - { - /* copy the input sample to the circular buffer */ - circBuffer[wOffset] = *src; - - /* Update the input pointer */ - src += srcInc; - - /* Circularly update wOffset. Watch out for positive and negative value */ - wOffset += bufferInc; - if (wOffset >= L) - wOffset -= L; - - /* Decrement the loop counter */ - i--; - } - - /* Update the index pointer */ - *writeOffset = (uint16_t)wOffset; - } - - - /** - * @brief Q7 Circular Read function. - */ - CMSIS_INLINE __STATIC_INLINE void arm_circularRead_q7( - q7_t * circBuffer, - int32_t L, - int32_t * readOffset, - int32_t bufferInc, - q7_t * dst, - q7_t * dst_base, - int32_t dst_length, - int32_t dstInc, - uint32_t blockSize) - { - uint32_t i = 0; - int32_t rOffset, dst_end; - - /* Copy the value of Index pointer that points - * to the current location from where the input samples to be read */ - rOffset = *readOffset; - - dst_end = (int32_t) (dst_base + dst_length); - - /* Loop over the blockSize */ - i = blockSize; - - while (i > 0U) - { - /* copy the sample from the circular buffer to the destination buffer */ - *dst = circBuffer[rOffset]; - - /* Update the input pointer */ - dst += dstInc; - - if (dst == (q7_t *) dst_end) - { - dst = dst_base; - } - - /* Circularly update rOffset. Watch out for positive and negative value */ - rOffset += bufferInc; - - if (rOffset >= L) - { - rOffset -= L; - } - - /* Decrement the loop counter */ - i--; - } - - /* Update the index pointer */ - *readOffset = rOffset; - } - - - /** - * @brief Sum of the squares of the elements of a Q31 vector. - * @param[in] pSrc is input pointer - * @param[in] blockSize is the number of samples to process - * @param[out] pResult is output value. - */ - void arm_power_q31( - q31_t * pSrc, - uint32_t blockSize, - q63_t * pResult); - - - /** - * @brief Sum of the squares of the elements of a floating-point vector. - * @param[in] pSrc is input pointer - * @param[in] blockSize is the number of samples to process - * @param[out] pResult is output value. - */ - void arm_power_f32( - float32_t * pSrc, - uint32_t blockSize, - float32_t * pResult); - - - /** - * @brief Sum of the squares of the elements of a Q15 vector. - * @param[in] pSrc is input pointer - * @param[in] blockSize is the number of samples to process - * @param[out] pResult is output value. - */ - void arm_power_q15( - q15_t * pSrc, - uint32_t blockSize, - q63_t * pResult); - - - /** - * @brief Sum of the squares of the elements of a Q7 vector. - * @param[in] pSrc is input pointer - * @param[in] blockSize is the number of samples to process - * @param[out] pResult is output value. - */ - void arm_power_q7( - q7_t * pSrc, - uint32_t blockSize, - q31_t * pResult); - - - /** - * @brief Mean value of a Q7 vector. - * @param[in] pSrc is input pointer - * @param[in] blockSize is the number of samples to process - * @param[out] pResult is output value. - */ - void arm_mean_q7( - q7_t * pSrc, - uint32_t blockSize, - q7_t * pResult); - - - /** - * @brief Mean value of a Q15 vector. - * @param[in] pSrc is input pointer - * @param[in] blockSize is the number of samples to process - * @param[out] pResult is output value. - */ - void arm_mean_q15( - q15_t * pSrc, - uint32_t blockSize, - q15_t * pResult); - - - /** - * @brief Mean value of a Q31 vector. - * @param[in] pSrc is input pointer - * @param[in] blockSize is the number of samples to process - * @param[out] pResult is output value. - */ - void arm_mean_q31( - q31_t * pSrc, - uint32_t blockSize, - q31_t * pResult); - - - /** - * @brief Mean value of a floating-point vector. - * @param[in] pSrc is input pointer - * @param[in] blockSize is the number of samples to process - * @param[out] pResult is output value. - */ - void arm_mean_f32( - float32_t * pSrc, - uint32_t blockSize, - float32_t * pResult); - - - /** - * @brief Variance of the elements of a floating-point vector. - * @param[in] pSrc is input pointer - * @param[in] blockSize is the number of samples to process - * @param[out] pResult is output value. - */ - void arm_var_f32( - float32_t * pSrc, - uint32_t blockSize, - float32_t * pResult); - - - /** - * @brief Variance of the elements of a Q31 vector. - * @param[in] pSrc is input pointer - * @param[in] blockSize is the number of samples to process - * @param[out] pResult is output value. - */ - void arm_var_q31( - q31_t * pSrc, - uint32_t blockSize, - q31_t * pResult); - - - /** - * @brief Variance of the elements of a Q15 vector. - * @param[in] pSrc is input pointer - * @param[in] blockSize is the number of samples to process - * @param[out] pResult is output value. - */ - void arm_var_q15( - q15_t * pSrc, - uint32_t blockSize, - q15_t * pResult); - - - /** - * @brief Root Mean Square of the elements of a floating-point vector. - * @param[in] pSrc is input pointer - * @param[in] blockSize is the number of samples to process - * @param[out] pResult is output value. - */ - void arm_rms_f32( - float32_t * pSrc, - uint32_t blockSize, - float32_t * pResult); - - - /** - * @brief Root Mean Square of the elements of a Q31 vector. - * @param[in] pSrc is input pointer - * @param[in] blockSize is the number of samples to process - * @param[out] pResult is output value. - */ - void arm_rms_q31( - q31_t * pSrc, - uint32_t blockSize, - q31_t * pResult); - - - /** - * @brief Root Mean Square of the elements of a Q15 vector. - * @param[in] pSrc is input pointer - * @param[in] blockSize is the number of samples to process - * @param[out] pResult is output value. - */ - void arm_rms_q15( - q15_t * pSrc, - uint32_t blockSize, - q15_t * pResult); - - - /** - * @brief Standard deviation of the elements of a floating-point vector. - * @param[in] pSrc is input pointer - * @param[in] blockSize is the number of samples to process - * @param[out] pResult is output value. - */ - void arm_std_f32( - float32_t * pSrc, - uint32_t blockSize, - float32_t * pResult); - - - /** - * @brief Standard deviation of the elements of a Q31 vector. - * @param[in] pSrc is input pointer - * @param[in] blockSize is the number of samples to process - * @param[out] pResult is output value. - */ - void arm_std_q31( - q31_t * pSrc, - uint32_t blockSize, - q31_t * pResult); - - - /** - * @brief Standard deviation of the elements of a Q15 vector. - * @param[in] pSrc is input pointer - * @param[in] blockSize is the number of samples to process - * @param[out] pResult is output value. - */ - void arm_std_q15( - q15_t * pSrc, - uint32_t blockSize, - q15_t * pResult); - - - /** - * @brief Floating-point complex magnitude - * @param[in] pSrc points to the complex input vector - * @param[out] pDst points to the real output vector - * @param[in] numSamples number of complex samples in the input vector - */ - void arm_cmplx_mag_f32( - float32_t * pSrc, - float32_t * pDst, - uint32_t numSamples); - - - /** - * @brief Q31 complex magnitude - * @param[in] pSrc points to the complex input vector - * @param[out] pDst points to the real output vector - * @param[in] numSamples number of complex samples in the input vector - */ - void arm_cmplx_mag_q31( - q31_t * pSrc, - q31_t * pDst, - uint32_t numSamples); - - - /** - * @brief Q15 complex magnitude - * @param[in] pSrc points to the complex input vector - * @param[out] pDst points to the real output vector - * @param[in] numSamples number of complex samples in the input vector - */ - void arm_cmplx_mag_q15( - q15_t * pSrc, - q15_t * pDst, - uint32_t numSamples); - - - /** - * @brief Q15 complex dot product - * @param[in] pSrcA points to the first input vector - * @param[in] pSrcB points to the second input vector - * @param[in] numSamples number of complex samples in each vector - * @param[out] realResult real part of the result returned here - * @param[out] imagResult imaginary part of the result returned here - */ - void arm_cmplx_dot_prod_q15( - q15_t * pSrcA, - q15_t * pSrcB, - uint32_t numSamples, - q31_t * realResult, - q31_t * imagResult); - - - /** - * @brief Q31 complex dot product - * @param[in] pSrcA points to the first input vector - * @param[in] pSrcB points to the second input vector - * @param[in] numSamples number of complex samples in each vector - * @param[out] realResult real part of the result returned here - * @param[out] imagResult imaginary part of the result returned here - */ - void arm_cmplx_dot_prod_q31( - q31_t * pSrcA, - q31_t * pSrcB, - uint32_t numSamples, - q63_t * realResult, - q63_t * imagResult); - - - /** - * @brief Floating-point complex dot product - * @param[in] pSrcA points to the first input vector - * @param[in] pSrcB points to the second input vector - * @param[in] numSamples number of complex samples in each vector - * @param[out] realResult real part of the result returned here - * @param[out] imagResult imaginary part of the result returned here - */ - void arm_cmplx_dot_prod_f32( - float32_t * pSrcA, - float32_t * pSrcB, - uint32_t numSamples, - float32_t * realResult, - float32_t * imagResult); - - - /** - * @brief Q15 complex-by-real multiplication - * @param[in] pSrcCmplx points to the complex input vector - * @param[in] pSrcReal points to the real input vector - * @param[out] pCmplxDst points to the complex output vector - * @param[in] numSamples number of samples in each vector - */ - void arm_cmplx_mult_real_q15( - q15_t * pSrcCmplx, - q15_t * pSrcReal, - q15_t * pCmplxDst, - uint32_t numSamples); - - - /** - * @brief Q31 complex-by-real multiplication - * @param[in] pSrcCmplx points to the complex input vector - * @param[in] pSrcReal points to the real input vector - * @param[out] pCmplxDst points to the complex output vector - * @param[in] numSamples number of samples in each vector - */ - void arm_cmplx_mult_real_q31( - q31_t * pSrcCmplx, - q31_t * pSrcReal, - q31_t * pCmplxDst, - uint32_t numSamples); - - - /** - * @brief Floating-point complex-by-real multiplication - * @param[in] pSrcCmplx points to the complex input vector - * @param[in] pSrcReal points to the real input vector - * @param[out] pCmplxDst points to the complex output vector - * @param[in] numSamples number of samples in each vector - */ - void arm_cmplx_mult_real_f32( - float32_t * pSrcCmplx, - float32_t * pSrcReal, - float32_t * pCmplxDst, - uint32_t numSamples); - - - /** - * @brief Minimum value of a Q7 vector. - * @param[in] pSrc is input pointer - * @param[in] blockSize is the number of samples to process - * @param[out] result is output pointer - * @param[in] index is the array index of the minimum value in the input buffer. - */ - void arm_min_q7( - q7_t * pSrc, - uint32_t blockSize, - q7_t * result, - uint32_t * index); - - - /** - * @brief Minimum value of a Q15 vector. - * @param[in] pSrc is input pointer - * @param[in] blockSize is the number of samples to process - * @param[out] pResult is output pointer - * @param[in] pIndex is the array index of the minimum value in the input buffer. - */ - void arm_min_q15( - q15_t * pSrc, - uint32_t blockSize, - q15_t * pResult, - uint32_t * pIndex); - - - /** - * @brief Minimum value of a Q31 vector. - * @param[in] pSrc is input pointer - * @param[in] blockSize is the number of samples to process - * @param[out] pResult is output pointer - * @param[out] pIndex is the array index of the minimum value in the input buffer. - */ - void arm_min_q31( - q31_t * pSrc, - uint32_t blockSize, - q31_t * pResult, - uint32_t * pIndex); - - - /** - * @brief Minimum value of a floating-point vector. - * @param[in] pSrc is input pointer - * @param[in] blockSize is the number of samples to process - * @param[out] pResult is output pointer - * @param[out] pIndex is the array index of the minimum value in the input buffer. - */ - void arm_min_f32( - float32_t * pSrc, - uint32_t blockSize, - float32_t * pResult, - uint32_t * pIndex); - - -/** - * @brief Maximum value of a Q7 vector. - * @param[in] pSrc points to the input buffer - * @param[in] blockSize length of the input vector - * @param[out] pResult maximum value returned here - * @param[out] pIndex index of maximum value returned here - */ - void arm_max_q7( - q7_t * pSrc, - uint32_t blockSize, - q7_t * pResult, - uint32_t * pIndex); - - -/** - * @brief Maximum value of a Q15 vector. - * @param[in] pSrc points to the input buffer - * @param[in] blockSize length of the input vector - * @param[out] pResult maximum value returned here - * @param[out] pIndex index of maximum value returned here - */ - void arm_max_q15( - q15_t * pSrc, - uint32_t blockSize, - q15_t * pResult, - uint32_t * pIndex); - - -/** - * @brief Maximum value of a Q31 vector. - * @param[in] pSrc points to the input buffer - * @param[in] blockSize length of the input vector - * @param[out] pResult maximum value returned here - * @param[out] pIndex index of maximum value returned here - */ - void arm_max_q31( - q31_t * pSrc, - uint32_t blockSize, - q31_t * pResult, - uint32_t * pIndex); - - -/** - * @brief Maximum value of a floating-point vector. - * @param[in] pSrc points to the input buffer - * @param[in] blockSize length of the input vector - * @param[out] pResult maximum value returned here - * @param[out] pIndex index of maximum value returned here - */ - void arm_max_f32( - float32_t * pSrc, - uint32_t blockSize, - float32_t * pResult, - uint32_t * pIndex); - - - /** - * @brief Q15 complex-by-complex multiplication - * @param[in] pSrcA points to the first input vector - * @param[in] pSrcB points to the second input vector - * @param[out] pDst points to the output vector - * @param[in] numSamples number of complex samples in each vector - */ - void arm_cmplx_mult_cmplx_q15( - q15_t * pSrcA, - q15_t * pSrcB, - q15_t * pDst, - uint32_t numSamples); - - - /** - * @brief Q31 complex-by-complex multiplication - * @param[in] pSrcA points to the first input vector - * @param[in] pSrcB points to the second input vector - * @param[out] pDst points to the output vector - * @param[in] numSamples number of complex samples in each vector - */ - void arm_cmplx_mult_cmplx_q31( - q31_t * pSrcA, - q31_t * pSrcB, - q31_t * pDst, - uint32_t numSamples); - - - /** - * @brief Floating-point complex-by-complex multiplication - * @param[in] pSrcA points to the first input vector - * @param[in] pSrcB points to the second input vector - * @param[out] pDst points to the output vector - * @param[in] numSamples number of complex samples in each vector - */ - void arm_cmplx_mult_cmplx_f32( - float32_t * pSrcA, - float32_t * pSrcB, - float32_t * pDst, - uint32_t numSamples); - - - /** - * @brief Converts the elements of the floating-point vector to Q31 vector. - * @param[in] pSrc points to the floating-point input vector - * @param[out] pDst points to the Q31 output vector - * @param[in] blockSize length of the input vector - */ - void arm_float_to_q31( - float32_t * pSrc, - q31_t * pDst, - uint32_t blockSize); - - - /** - * @brief Converts the elements of the floating-point vector to Q15 vector. - * @param[in] pSrc points to the floating-point input vector - * @param[out] pDst points to the Q15 output vector - * @param[in] blockSize length of the input vector - */ - void arm_float_to_q15( - float32_t * pSrc, - q15_t * pDst, - uint32_t blockSize); - - - /** - * @brief Converts the elements of the floating-point vector to Q7 vector. - * @param[in] pSrc points to the floating-point input vector - * @param[out] pDst points to the Q7 output vector - * @param[in] blockSize length of the input vector - */ - void arm_float_to_q7( - float32_t * pSrc, - q7_t * pDst, - uint32_t blockSize); - - - /** - * @brief Converts the elements of the Q31 vector to Q15 vector. - * @param[in] pSrc is input pointer - * @param[out] pDst is output pointer - * @param[in] blockSize is the number of samples to process - */ - void arm_q31_to_q15( - q31_t * pSrc, - q15_t * pDst, - uint32_t blockSize); - - - /** - * @brief Converts the elements of the Q31 vector to Q7 vector. - * @param[in] pSrc is input pointer - * @param[out] pDst is output pointer - * @param[in] blockSize is the number of samples to process - */ - void arm_q31_to_q7( - q31_t * pSrc, - q7_t * pDst, - uint32_t blockSize); - - - /** - * @brief Converts the elements of the Q15 vector to floating-point vector. - * @param[in] pSrc is input pointer - * @param[out] pDst is output pointer - * @param[in] blockSize is the number of samples to process - */ - void arm_q15_to_float( - q15_t * pSrc, - float32_t * pDst, - uint32_t blockSize); - - - /** - * @brief Converts the elements of the Q15 vector to Q31 vector. - * @param[in] pSrc is input pointer - * @param[out] pDst is output pointer - * @param[in] blockSize is the number of samples to process - */ - void arm_q15_to_q31( - q15_t * pSrc, - q31_t * pDst, - uint32_t blockSize); - - - /** - * @brief Converts the elements of the Q15 vector to Q7 vector. - * @param[in] pSrc is input pointer - * @param[out] pDst is output pointer - * @param[in] blockSize is the number of samples to process - */ - void arm_q15_to_q7( - q15_t * pSrc, - q7_t * pDst, - uint32_t blockSize); - - - /** - * @ingroup groupInterpolation - */ - - /** - * @defgroup BilinearInterpolate Bilinear Interpolation - * - * Bilinear interpolation is an extension of linear interpolation applied to a two dimensional grid. - * The underlying function f(x, y) is sampled on a regular grid and the interpolation process - * determines values between the grid points. - * Bilinear interpolation is equivalent to two step linear interpolation, first in the x-dimension and then in the y-dimension. - * Bilinear interpolation is often used in image processing to rescale images. - * The CMSIS DSP library provides bilinear interpolation functions for Q7, Q15, Q31, and floating-point data types. - * - * Algorithm - * \par - * The instance structure used by the bilinear interpolation functions describes a two dimensional data table. - * For floating-point, the instance structure is defined as: - * 
-   *   typedef struct
-   *   {
-   *     uint16_t numRows;
-   *     uint16_t numCols;
-   *     float32_t *pData;
-   * } arm_bilinear_interp_instance_f32;
-   *
- * - * \par - * where numRows specifies the number of rows in the table; - * numCols specifies the number of columns in the table; - * and pData points to an array of size numRows*numCols values. - * The data table pTable is organized in row order and the supplied data values fall on integer indexes. - * That is, table element (x,y) is located at pTable[x + y*numCols] where x and y are integers. - * - * \par - * Let (x, y) specify the desired interpolation point. Then define: - * 
-   *     XF = floor(x)
-   *     YF = floor(y)
-   *
- * \par - * The interpolated output point is computed as: - * 
-   *  f(x, y) = f(XF, YF) * (1-(x-XF)) * (1-(y-YF))
-   *           + f(XF+1, YF) * (x-XF)*(1-(y-YF))
-   *           + f(XF, YF+1) * (1-(x-XF))*(y-YF)
-   *           + f(XF+1, YF+1) * (x-XF)*(y-YF)
-   *
- * Note that the coordinates (x, y) contain integer and fractional components. - * The integer components specify which portion of the table to use while the - * fractional components control the interpolation processor. - * - * \par - * if (x,y) are outside of the table boundary, Bilinear interpolation returns zero output. - */ - - /** - * @addtogroup BilinearInterpolate - * @{ - */ - - - /** - * - * @brief Floating-point bilinear interpolation. - * @param[in,out] S points to an instance of the interpolation structure. - * @param[in] X interpolation coordinate. - * @param[in] Y interpolation coordinate. - * @return out interpolated value. - */ - CMSIS_INLINE __STATIC_INLINE float32_t arm_bilinear_interp_f32( - const arm_bilinear_interp_instance_f32 * S, - float32_t X, - float32_t Y) - { - float32_t out; - float32_t f00, f01, f10, f11; - float32_t *pData = S->pData; - int32_t xIndex, yIndex, index; - float32_t xdiff, ydiff; - float32_t b1, b2, b3, b4; - - xIndex = (int32_t) X; - yIndex = (int32_t) Y; - - /* Care taken for table outside boundary */ - /* Returns zero output when values are outside table boundary */ - if (xIndex < 0 || xIndex > (S->numRows - 1) || yIndex < 0 || yIndex > (S->numCols - 1)) - { - return (0); - } - - /* Calculation of index for two nearest points in X-direction */ - index = (xIndex - 1) + (yIndex - 1) * S->numCols; - - - /* Read two nearest points in X-direction */ - f00 = pData[index]; - f01 = pData[index + 1]; - - /* Calculation of index for two nearest points in Y-direction */ - index = (xIndex - 1) + (yIndex) * S->numCols; - - - /* Read two nearest points in Y-direction */ - f10 = pData[index]; - f11 = pData[index + 1]; - - /* Calculation of intermediate values */ - b1 = f00; - b2 = f01 - f00; - b3 = f10 - f00; - b4 = f00 - f01 - f10 + f11; - - /* Calculation of fractional part in X */ - xdiff = X - xIndex; - - /* Calculation of fractional part in Y */ - ydiff = Y - yIndex; - - /* Calculation of bi-linear interpolated output */ - out = b1 + b2 * xdiff + b3 * ydiff + b4 * xdiff * ydiff; - - /* return to application */ - return (out); - } - - - /** - * - * @brief Q31 bilinear interpolation. - * @param[in,out] S points to an instance of the interpolation structure. - * @param[in] X interpolation coordinate in 12.20 format. - * @param[in] Y interpolation coordinate in 12.20 format. - * @return out interpolated value. - */ - CMSIS_INLINE __STATIC_INLINE q31_t arm_bilinear_interp_q31( - arm_bilinear_interp_instance_q31 * S, - q31_t X, - q31_t Y) - { - q31_t out; /* Temporary output */ - q31_t acc = 0; /* output */ - q31_t xfract, yfract; /* X, Y fractional parts */ - q31_t x1, x2, y1, y2; /* Nearest output values */ - int32_t rI, cI; /* Row and column indices */ - q31_t *pYData = S->pData; /* pointer to output table values */ - uint32_t nCols = S->numCols; /* num of rows */ - - /* Input is in 12.20 format */ - /* 12 bits for the table index */ - /* Index value calculation */ - rI = ((X & (q31_t)0xFFF00000) >> 20); - - /* Input is in 12.20 format */ - /* 12 bits for the table index */ - /* Index value calculation */ - cI = ((Y & (q31_t)0xFFF00000) >> 20); - - /* Care taken for table outside boundary */ - /* Returns zero output when values are outside table boundary */ - if (rI < 0 || rI > (S->numRows - 1) || cI < 0 || cI > (S->numCols - 1)) - { - return (0); - } - - /* 20 bits for the fractional part */ - /* shift left xfract by 11 to keep 1.31 format */ - xfract = (X & 0x000FFFFF) << 11U; - - /* Read two nearest output values from the index */ - x1 = pYData[(rI) + (int32_t)nCols * (cI) ]; - x2 = pYData[(rI) + (int32_t)nCols * (cI) + 1]; - - /* 20 bits for the fractional part */ - /* shift left yfract by 11 to keep 1.31 format */ - yfract = (Y & 0x000FFFFF) << 11U; - - /* Read two nearest output values from the index */ - y1 = pYData[(rI) + (int32_t)nCols * (cI + 1) ]; - y2 = pYData[(rI) + (int32_t)nCols * (cI + 1) + 1]; - - /* Calculation of x1 * (1-xfract ) * (1-yfract) and acc is in 3.29(q29) format */ - out = ((q31_t) (((q63_t) x1 * (0x7FFFFFFF - xfract)) >> 32)); - acc = ((q31_t) (((q63_t) out * (0x7FFFFFFF - yfract)) >> 32)); - - /* x2 * (xfract) * (1-yfract) in 3.29(q29) and adding to acc */ - out = ((q31_t) ((q63_t) x2 * (0x7FFFFFFF - yfract) >> 32)); - acc += ((q31_t) ((q63_t) out * (xfract) >> 32)); - - /* y1 * (1 - xfract) * (yfract) in 3.29(q29) and adding to acc */ - out = ((q31_t) ((q63_t) y1 * (0x7FFFFFFF - xfract) >> 32)); - acc += ((q31_t) ((q63_t) out * (yfract) >> 32)); - - /* y2 * (xfract) * (yfract) in 3.29(q29) and adding to acc */ - out = ((q31_t) ((q63_t) y2 * (xfract) >> 32)); - acc += ((q31_t) ((q63_t) out * (yfract) >> 32)); - - /* Convert acc to 1.31(q31) format */ - return ((q31_t)(acc << 2)); - } - - - /** - * @brief Q15 bilinear interpolation. - * @param[in,out] S points to an instance of the interpolation structure. - * @param[in] X interpolation coordinate in 12.20 format. - * @param[in] Y interpolation coordinate in 12.20 format. - * @return out interpolated value. - */ - CMSIS_INLINE __STATIC_INLINE q15_t arm_bilinear_interp_q15( - arm_bilinear_interp_instance_q15 * S, - q31_t X, - q31_t Y) - { - q63_t acc = 0; /* output */ - q31_t out; /* Temporary output */ - q15_t x1, x2, y1, y2; /* Nearest output values */ - q31_t xfract, yfract; /* X, Y fractional parts */ - int32_t rI, cI; /* Row and column indices */ - q15_t *pYData = S->pData; /* pointer to output table values */ - uint32_t nCols = S->numCols; /* num of rows */ - - /* Input is in 12.20 format */ - /* 12 bits for the table index */ - /* Index value calculation */ - rI = ((X & (q31_t)0xFFF00000) >> 20); - - /* Input is in 12.20 format */ - /* 12 bits for the table index */ - /* Index value calculation */ - cI = ((Y & (q31_t)0xFFF00000) >> 20); - - /* Care taken for table outside boundary */ - /* Returns zero output when values are outside table boundary */ - if (rI < 0 || rI > (S->numRows - 1) || cI < 0 || cI > (S->numCols - 1)) - { - return (0); - } - - /* 20 bits for the fractional part */ - /* xfract should be in 12.20 format */ - xfract = (X & 0x000FFFFF); - - /* Read two nearest output values from the index */ - x1 = pYData[((uint32_t)rI) + nCols * ((uint32_t)cI) ]; - x2 = pYData[((uint32_t)rI) + nCols * ((uint32_t)cI) + 1]; - - /* 20 bits for the fractional part */ - /* yfract should be in 12.20 format */ - yfract = (Y & 0x000FFFFF); - - /* Read two nearest output values from the index */ - y1 = pYData[((uint32_t)rI) + nCols * ((uint32_t)cI + 1) ]; - y2 = pYData[((uint32_t)rI) + nCols * ((uint32_t)cI + 1) + 1]; - - /* Calculation of x1 * (1-xfract ) * (1-yfract) and acc is in 13.51 format */ - - /* x1 is in 1.15(q15), xfract in 12.20 format and out is in 13.35 format */ - /* convert 13.35 to 13.31 by right shifting and out is in 1.31 */ - out = (q31_t) (((q63_t) x1 * (0xFFFFF - xfract)) >> 4U); - acc = ((q63_t) out * (0xFFFFF - yfract)); - - /* x2 * (xfract) * (1-yfract) in 1.51 and adding to acc */ - out = (q31_t) (((q63_t) x2 * (0xFFFFF - yfract)) >> 4U); - acc += ((q63_t) out * (xfract)); - - /* y1 * (1 - xfract) * (yfract) in 1.51 and adding to acc */ - out = (q31_t) (((q63_t) y1 * (0xFFFFF - xfract)) >> 4U); - acc += ((q63_t) out * (yfract)); - - /* y2 * (xfract) * (yfract) in 1.51 and adding to acc */ - out = (q31_t) (((q63_t) y2 * (xfract)) >> 4U); - acc += ((q63_t) out * (yfract)); - - /* acc is in 13.51 format and down shift acc by 36 times */ - /* Convert out to 1.15 format */ - return ((q15_t)(acc >> 36)); - } - - - /** - * @brief Q7 bilinear interpolation. - * @param[in,out] S points to an instance of the interpolation structure. - * @param[in] X interpolation coordinate in 12.20 format. - * @param[in] Y interpolation coordinate in 12.20 format. - * @return out interpolated value. - */ - CMSIS_INLINE __STATIC_INLINE q7_t arm_bilinear_interp_q7( - arm_bilinear_interp_instance_q7 * S, - q31_t X, - q31_t Y) - { - q63_t acc = 0; /* output */ - q31_t out; /* Temporary output */ - q31_t xfract, yfract; /* X, Y fractional parts */ - q7_t x1, x2, y1, y2; /* Nearest output values */ - int32_t rI, cI; /* Row and column indices */ - q7_t *pYData = S->pData; /* pointer to output table values */ - uint32_t nCols = S->numCols; /* num of rows */ - - /* Input is in 12.20 format */ - /* 12 bits for the table index */ - /* Index value calculation */ - rI = ((X & (q31_t)0xFFF00000) >> 20); - - /* Input is in 12.20 format */ - /* 12 bits for the table index */ - /* Index value calculation */ - cI = ((Y & (q31_t)0xFFF00000) >> 20); - - /* Care taken for table outside boundary */ - /* Returns zero output when values are outside table boundary */ - if (rI < 0 || rI > (S->numRows - 1) || cI < 0 || cI > (S->numCols - 1)) - { - return (0); - } - - /* 20 bits for the fractional part */ - /* xfract should be in 12.20 format */ - xfract = (X & (q31_t)0x000FFFFF); - - /* Read two nearest output values from the index */ - x1 = pYData[((uint32_t)rI) + nCols * ((uint32_t)cI) ]; - x2 = pYData[((uint32_t)rI) + nCols * ((uint32_t)cI) + 1]; - - /* 20 bits for the fractional part */ - /* yfract should be in 12.20 format */ - yfract = (Y & (q31_t)0x000FFFFF); - - /* Read two nearest output values from the index */ - y1 = pYData[((uint32_t)rI) + nCols * ((uint32_t)cI + 1) ]; - y2 = pYData[((uint32_t)rI) + nCols * ((uint32_t)cI + 1) + 1]; - - /* Calculation of x1 * (1-xfract ) * (1-yfract) and acc is in 16.47 format */ - out = ((x1 * (0xFFFFF - xfract))); - acc = (((q63_t) out * (0xFFFFF - yfract))); - - /* x2 * (xfract) * (1-yfract) in 2.22 and adding to acc */ - out = ((x2 * (0xFFFFF - yfract))); - acc += (((q63_t) out * (xfract))); - - /* y1 * (1 - xfract) * (yfract) in 2.22 and adding to acc */ - out = ((y1 * (0xFFFFF - xfract))); - acc += (((q63_t) out * (yfract))); - - /* y2 * (xfract) * (yfract) in 2.22 and adding to acc */ - out = ((y2 * (yfract))); - acc += (((q63_t) out * (xfract))); - - /* acc in 16.47 format and down shift by 40 to convert to 1.7 format */ - return ((q7_t)(acc >> 40)); - } - - /** - * @} end of BilinearInterpolate group - */ - - -/* SMMLAR */ -#define multAcc_32x32_keep32_R(a, x, y) \ - a = (q31_t) (((((q63_t) a) << 32) + ((q63_t) x * y) + 0x80000000LL ) >> 32) - -/* SMMLSR */ -#define multSub_32x32_keep32_R(a, x, y) \ - a = (q31_t) (((((q63_t) a) << 32) - ((q63_t) x * y) + 0x80000000LL ) >> 32) - -/* SMMULR */ -#define mult_32x32_keep32_R(a, x, y) \ - a = (q31_t) (((q63_t) x * y + 0x80000000LL ) >> 32) - -/* SMMLA */ -#define multAcc_32x32_keep32(a, x, y) \ - a += (q31_t) (((q63_t) x * y) >> 32) - -/* SMMLS */ -#define multSub_32x32_keep32(a, x, y) \ - a -= (q31_t) (((q63_t) x * y) >> 32) - -/* SMMUL */ -#define mult_32x32_keep32(a, x, y) \ - a = (q31_t) (((q63_t) x * y ) >> 32) - - -#if defined ( __CC_ARM ) - /* Enter low optimization region - place directly above function definition */ - #if defined( ARM_MATH_CM4 ) || defined( ARM_MATH_CM7) - #define LOW_OPTIMIZATION_ENTER \ - _Pragma ("push") \ - _Pragma ("O1") - #else - #define LOW_OPTIMIZATION_ENTER - #endif - - /* Exit low optimization region - place directly after end of function definition */ - #if defined ( ARM_MATH_CM4 ) || defined ( ARM_MATH_CM7 ) - #define LOW_OPTIMIZATION_EXIT \ - _Pragma ("pop") - #else - #define LOW_OPTIMIZATION_EXIT - #endif - - /* Enter low optimization region - place directly above function definition */ - #define IAR_ONLY_LOW_OPTIMIZATION_ENTER - - /* Exit low optimization region - place directly after end of function definition */ - #define IAR_ONLY_LOW_OPTIMIZATION_EXIT - -#elif defined (__ARMCC_VERSION ) && ( __ARMCC_VERSION >= 6010050 ) - #define LOW_OPTIMIZATION_ENTER - #define LOW_OPTIMIZATION_EXIT - #define IAR_ONLY_LOW_OPTIMIZATION_ENTER - #define IAR_ONLY_LOW_OPTIMIZATION_EXIT - -#elif defined ( __GNUC__ ) - #define LOW_OPTIMIZATION_ENTER \ - __attribute__(( optimize("-O1") )) - #define LOW_OPTIMIZATION_EXIT - #define IAR_ONLY_LOW_OPTIMIZATION_ENTER - #define IAR_ONLY_LOW_OPTIMIZATION_EXIT - -#elif defined ( __ICCARM__ ) - /* Enter low optimization region - place directly above function definition */ - #if defined ( ARM_MATH_CM4 ) || defined ( ARM_MATH_CM7 ) - #define LOW_OPTIMIZATION_ENTER \ - _Pragma ("optimize=low") - #else - #define LOW_OPTIMIZATION_ENTER - #endif - - /* Exit low optimization region - place directly after end of function definition */ - #define LOW_OPTIMIZATION_EXIT - - /* Enter low optimization region - place directly above function definition */ - #if defined ( ARM_MATH_CM4 ) || defined ( ARM_MATH_CM7 ) - #define IAR_ONLY_LOW_OPTIMIZATION_ENTER \ - _Pragma ("optimize=low") - #else - #define IAR_ONLY_LOW_OPTIMIZATION_ENTER - #endif - - /* Exit low optimization region - place directly after end of function definition */ - #define IAR_ONLY_LOW_OPTIMIZATION_EXIT - -#elif defined ( __TI_ARM__ ) - #define LOW_OPTIMIZATION_ENTER - #define LOW_OPTIMIZATION_EXIT - #define IAR_ONLY_LOW_OPTIMIZATION_ENTER - #define IAR_ONLY_LOW_OPTIMIZATION_EXIT - -#elif defined ( __CSMC__ ) - #define LOW_OPTIMIZATION_ENTER - #define LOW_OPTIMIZATION_EXIT - #define IAR_ONLY_LOW_OPTIMIZATION_ENTER - #define IAR_ONLY_LOW_OPTIMIZATION_EXIT - -#elif defined ( __TASKING__ ) - #define LOW_OPTIMIZATION_ENTER - #define LOW_OPTIMIZATION_EXIT - #define IAR_ONLY_LOW_OPTIMIZATION_ENTER - #define IAR_ONLY_LOW_OPTIMIZATION_EXIT - -#endif - - -#ifdef __cplusplus -} -#endif - -/* Compiler specific diagnostic adjustment */ -#if defined ( __CC_ARM ) - -#elif defined ( __ARMCC_VERSION ) && ( __ARMCC_VERSION >= 6010050 ) - -#elif defined ( __GNUC__ ) -#pragma GCC diagnostic pop - -#elif defined ( __ICCARM__ ) - -#elif defined ( __TI_ARM__ ) - -#elif defined ( __CSMC__ ) - -#elif defined ( __TASKING__ ) - -#else - #error Unknown compiler -#endif - -#endif /* _ARM_MATH_H */ - -/** - * - * End of file. - */ diff --git a/bsp/essemi/es32f0271/libraries/CMSIS/Include/cmsis_armcc.h b/bsp/essemi/es32f0271/libraries/CMSIS/Include/cmsis_armcc.h deleted file mode 100644 index 093d35b9e5..0000000000 --- a/bsp/essemi/es32f0271/libraries/CMSIS/Include/cmsis_armcc.h +++ /dev/null @@ -1,870 +0,0 @@ -/**************************************************************************//** - * @file cmsis_armcc.h - * @brief CMSIS compiler ARMCC (Arm Compiler 5) header file - * @version V5.0.4 - * @date 10. January 2018 - ******************************************************************************/ -/* - * Copyright (c) 2009-2018 Arm Limited. All rights reserved. - * - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed under the Apache License, Version 2.0 (the License); you may - * not use this file except in compliance with the License. - * You may obtain a copy of the License at - * - * www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an AS IS BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - */ - -#ifndef __CMSIS_ARMCC_H -#define __CMSIS_ARMCC_H - - -#if defined(__ARMCC_VERSION) && (__ARMCC_VERSION < 400677) - #error "Please use Arm Compiler Toolchain V4.0.677 or later!" -#endif - -/* CMSIS compiler control architecture macros */ -#if ((defined (__TARGET_ARCH_6_M ) && (__TARGET_ARCH_6_M == 1)) || \ - (defined (__TARGET_ARCH_6S_M ) && (__TARGET_ARCH_6S_M == 1)) ) - #define __ARM_ARCH_6M__ 1 -#endif - -#if (defined (__TARGET_ARCH_7_M ) && (__TARGET_ARCH_7_M == 1)) - #define __ARM_ARCH_7M__ 1 -#endif - -#if (defined (__TARGET_ARCH_7E_M) && (__TARGET_ARCH_7E_M == 1)) - #define __ARM_ARCH_7EM__ 1 -#endif - - /* __ARM_ARCH_8M_BASE__ not applicable */ - /* __ARM_ARCH_8M_MAIN__ not applicable */ - - -/* CMSIS compiler specific defines */ -#ifndef __ASM - #define __ASM __asm -#endif -#ifndef __INLINE - #define __INLINE __inline -#endif -#ifndef __STATIC_INLINE - #define __STATIC_INLINE static __inline -#endif -#ifndef __STATIC_FORCEINLINE - #define __STATIC_FORCEINLINE static __forceinline -#endif -#ifndef __NO_RETURN - #define __NO_RETURN __declspec(noreturn) -#endif -#ifndef __USED - #define __USED __attribute__((used)) -#endif -#ifndef __WEAK - #define __WEAK __attribute__((weak)) -#endif -#ifndef __PACKED - #define __PACKED __attribute__((packed)) -#endif -#ifndef __PACKED_STRUCT - #define __PACKED_STRUCT __packed struct -#endif -#ifndef __PACKED_UNION - #define __PACKED_UNION __packed union -#endif -#ifndef __UNALIGNED_UINT32 /* deprecated */ - #define __UNALIGNED_UINT32(x) (*((__packed uint32_t *)(x))) -#endif -#ifndef __UNALIGNED_UINT16_WRITE - #define __UNALIGNED_UINT16_WRITE(addr, val) ((*((__packed uint16_t *)(addr))) = (val)) -#endif -#ifndef __UNALIGNED_UINT16_READ - #define __UNALIGNED_UINT16_READ(addr) (*((const __packed uint16_t *)(addr))) -#endif -#ifndef __UNALIGNED_UINT32_WRITE - #define __UNALIGNED_UINT32_WRITE(addr, val) ((*((__packed uint32_t *)(addr))) = (val)) -#endif -#ifndef __UNALIGNED_UINT32_READ - #define __UNALIGNED_UINT32_READ(addr) (*((const __packed uint32_t *)(addr))) -#endif -#ifndef __ALIGNED - #define __ALIGNED(x) __attribute__((aligned(x))) -#endif -#ifndef __RESTRICT - #define __RESTRICT __restrict -#endif - -/* ########################### Core Function Access ########################### */ -/** \ingroup CMSIS_Core_FunctionInterface - \defgroup CMSIS_Core_RegAccFunctions CMSIS Core Register Access Functions - @{ - */ - -/** - \brief Enable IRQ Interrupts - \details Enables IRQ interrupts by clearing the I-bit in the CPSR. - Can only be executed in Privileged modes. - */ -/* intrinsic void __enable_irq(); */ - - -/** - \brief Disable IRQ Interrupts - \details Disables IRQ interrupts by setting the I-bit in the CPSR. - Can only be executed in Privileged modes. - */ -/* intrinsic void __disable_irq(); */ - -/** - \brief Get Control Register - \details Returns the content of the Control Register. - \return Control Register value - */ -__STATIC_INLINE uint32_t __get_CONTROL(void) -{ - register uint32_t __regControl __ASM("control"); - return(__regControl); -} - - -/** - \brief Set Control Register - \details Writes the given value to the Control Register. - \param [in] control Control Register value to set - */ -__STATIC_INLINE void __set_CONTROL(uint32_t control) -{ - register uint32_t __regControl __ASM("control"); - __regControl = control; -} - - -/** - \brief Get IPSR Register - \details Returns the content of the IPSR Register. - \return IPSR Register value - */ -__STATIC_INLINE uint32_t __get_IPSR(void) -{ - register uint32_t __regIPSR __ASM("ipsr"); - return(__regIPSR); -} - - -/** - \brief Get APSR Register - \details Returns the content of the APSR Register. - \return APSR Register value - */ -__STATIC_INLINE uint32_t __get_APSR(void) -{ - register uint32_t __regAPSR __ASM("apsr"); - return(__regAPSR); -} - - -/** - \brief Get xPSR Register - \details Returns the content of the xPSR Register. - \return xPSR Register value - */ -__STATIC_INLINE uint32_t __get_xPSR(void) -{ - register uint32_t __regXPSR __ASM("xpsr"); - return(__regXPSR); -} - - -/** - \brief Get Process Stack Pointer - \details Returns the current value of the Process Stack Pointer (PSP). - \return PSP Register value - */ -__STATIC_INLINE uint32_t __get_PSP(void) -{ - register uint32_t __regProcessStackPointer __ASM("psp"); - return(__regProcessStackPointer); -} - - -/** - \brief Set Process Stack Pointer - \details Assigns the given value to the Process Stack Pointer (PSP). - \param [in] topOfProcStack Process Stack Pointer value to set - */ -__STATIC_INLINE void __set_PSP(uint32_t topOfProcStack) -{ - register uint32_t __regProcessStackPointer __ASM("psp"); - __regProcessStackPointer = topOfProcStack; -} - - -/** - \brief Get Main Stack Pointer - \details Returns the current value of the Main Stack Pointer (MSP). - \return MSP Register value - */ -__STATIC_INLINE uint32_t __get_MSP(void) -{ - register uint32_t __regMainStackPointer __ASM("msp"); - return(__regMainStackPointer); -} - - -/** - \brief Set Main Stack Pointer - \details Assigns the given value to the Main Stack Pointer (MSP). - \param [in] topOfMainStack Main Stack Pointer value to set - */ -__STATIC_INLINE void __set_MSP(uint32_t topOfMainStack) -{ - register uint32_t __regMainStackPointer __ASM("msp"); - __regMainStackPointer = topOfMainStack; -} - - -/** - \brief Get Priority Mask - \details Returns the current state of the priority mask bit from the Priority Mask Register. - \return Priority Mask value - */ -__STATIC_INLINE uint32_t __get_PRIMASK(void) -{ - register uint32_t __regPriMask __ASM("primask"); - return(__regPriMask); -} - - -/** - \brief Set Priority Mask - \details Assigns the given value to the Priority Mask Register. - \param [in] priMask Priority Mask - */ -__STATIC_INLINE void __set_PRIMASK(uint32_t priMask) -{ - register uint32_t __regPriMask __ASM("primask"); - __regPriMask = (priMask); -} - - -#if ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \ - (defined (__ARM_ARCH_7EM__) && (__ARM_ARCH_7EM__ == 1)) ) - -/** - \brief Enable FIQ - \details Enables FIQ interrupts by clearing the F-bit in the CPSR. - Can only be executed in Privileged modes. - */ -#define __enable_fault_irq __enable_fiq - - -/** - \brief Disable FIQ - \details Disables FIQ interrupts by setting the F-bit in the CPSR. - Can only be executed in Privileged modes. - */ -#define __disable_fault_irq __disable_fiq - - -/** - \brief Get Base Priority - \details Returns the current value of the Base Priority register. - \return Base Priority register value - */ -__STATIC_INLINE uint32_t __get_BASEPRI(void) -{ - register uint32_t __regBasePri __ASM("basepri"); - return(__regBasePri); -} - - -/** - \brief Set Base Priority - \details Assigns the given value to the Base Priority register. - \param [in] basePri Base Priority value to set - */ -__STATIC_INLINE void __set_BASEPRI(uint32_t basePri) -{ - register uint32_t __regBasePri __ASM("basepri"); - __regBasePri = (basePri & 0xFFU); -} - - -/** - \brief Set Base Priority with condition - \details Assigns the given value to the Base Priority register only if BASEPRI masking is disabled, - or the new value increases the BASEPRI priority level. - \param [in] basePri Base Priority value to set - */ -__STATIC_INLINE void __set_BASEPRI_MAX(uint32_t basePri) -{ - register uint32_t __regBasePriMax __ASM("basepri_max"); - __regBasePriMax = (basePri & 0xFFU); -} - - -/** - \brief Get Fault Mask - \details Returns the current value of the Fault Mask register. - \return Fault Mask register value - */ -__STATIC_INLINE uint32_t __get_FAULTMASK(void) -{ - register uint32_t __regFaultMask __ASM("faultmask"); - return(__regFaultMask); -} - - -/** - \brief Set Fault Mask - \details Assigns the given value to the Fault Mask register. - \param [in] faultMask Fault Mask value to set - */ -__STATIC_INLINE void __set_FAULTMASK(uint32_t faultMask) -{ - register uint32_t __regFaultMask __ASM("faultmask"); - __regFaultMask = (faultMask & (uint32_t)1U); -} - -#endif /* ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \ - (defined (__ARM_ARCH_7EM__) && (__ARM_ARCH_7EM__ == 1)) ) */ - - -#if ((defined (__ARM_ARCH_7EM__) && (__ARM_ARCH_7EM__ == 1)) ) - -/** - \brief Get FPSCR - \details Returns the current value of the Floating Point Status/Control register. - \return Floating Point Status/Control register value - */ -__STATIC_INLINE uint32_t __get_FPSCR(void) -{ -#if ((defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)) && \ - (defined (__FPU_USED ) && (__FPU_USED == 1U)) ) - register uint32_t __regfpscr __ASM("fpscr"); - return(__regfpscr); -#else - return(0U); -#endif -} - - -/** - \brief Set FPSCR - \details Assigns the given value to the Floating Point Status/Control register. - \param [in] fpscr Floating Point Status/Control value to set - */ -__STATIC_INLINE void __set_FPSCR(uint32_t fpscr) -{ -#if ((defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)) && \ - (defined (__FPU_USED ) && (__FPU_USED == 1U)) ) - register uint32_t __regfpscr __ASM("fpscr"); - __regfpscr = (fpscr); -#else - (void)fpscr; -#endif -} - -#endif /* ((defined (__ARM_ARCH_7EM__) && (__ARM_ARCH_7EM__ == 1)) ) */ - - - -/*@} end of CMSIS_Core_RegAccFunctions */ - - -/* ########################## Core Instruction Access ######################### */ -/** \defgroup CMSIS_Core_InstructionInterface CMSIS Core Instruction Interface - Access to dedicated instructions - @{ -*/ - -/** - \brief No Operation - \details No Operation does nothing. This instruction can be used for code alignment purposes. - */ -#define __NOP __nop - - -/** - \brief Wait For Interrupt - \details Wait For Interrupt is a hint instruction that suspends execution until one of a number of events occurs. - */ -#define __WFI __wfi - - -/** - \brief Wait For Event - \details Wait For Event is a hint instruction that permits the processor to enter - a low-power state until one of a number of events occurs. - */ -#define __WFE __wfe - - -/** - \brief Send Event - \details Send Event is a hint instruction. It causes an event to be signaled to the CPU. - */ -#define __SEV __sev - - -/** - \brief Instruction Synchronization Barrier - \details Instruction Synchronization Barrier flushes the pipeline in the processor, - so that all instructions following the ISB are fetched from cache or memory, - after the instruction has been completed. - */ -#define __ISB() do {\ - __schedule_barrier();\ - __isb(0xF);\ - __schedule_barrier();\ - } while (0U) - -/** - \brief Data Synchronization Barrier - \details Acts as a special kind of Data Memory Barrier. - It completes when all explicit memory accesses before this instruction complete. - */ -#define __DSB() do {\ - __schedule_barrier();\ - __dsb(0xF);\ - __schedule_barrier();\ - } while (0U) - -/** - \brief Data Memory Barrier - \details Ensures the apparent order of the explicit memory operations before - and after the instruction, without ensuring their completion. - */ -#define __DMB() do {\ - __schedule_barrier();\ - __dmb(0xF);\ - __schedule_barrier();\ - } while (0U) - - -/** - \brief Reverse byte order (32 bit) - \details Reverses the byte order in unsigned integer value. For example, 0x12345678 becomes 0x78563412. - \param [in] value Value to reverse - \return Reversed value - */ -#define __REV __rev - - -/** - \brief Reverse byte order (16 bit) - \details Reverses the byte order within each halfword of a word. For example, 0x12345678 becomes 0x34127856. - \param [in] value Value to reverse - \return Reversed value - */ -#ifndef __NO_EMBEDDED_ASM -__attribute__((section(".rev16_text"))) __STATIC_INLINE __ASM uint32_t __REV16(uint32_t value) -{ - rev16 r0, r0 - bx lr -} -#endif - - -/** - \brief Reverse byte order (16 bit) - \details Reverses the byte order in a 16-bit value and returns the signed 16-bit result. For example, 0x0080 becomes 0x8000. - \param [in] value Value to reverse - \return Reversed value - */ -#ifndef __NO_EMBEDDED_ASM -__attribute__((section(".revsh_text"))) __STATIC_INLINE __ASM int16_t __REVSH(int16_t value) -{ - revsh r0, r0 - bx lr -} -#endif - - -/** - \brief Rotate Right in unsigned value (32 bit) - \details Rotate Right (immediate) provides the value of the contents of a register rotated by a variable number of bits. - \param [in] op1 Value to rotate - \param [in] op2 Number of Bits to rotate - \return Rotated value - */ -#define __ROR __ror - - -/** - \brief Breakpoint - \details Causes the processor to enter Debug state. - Debug tools can use this to investigate system state when the instruction at a particular address is reached. - \param [in] value is ignored by the processor. - If required, a debugger can use it to store additional information about the breakpoint. - */ -#define __BKPT(value) __breakpoint(value) - - -/** - \brief Reverse bit order of value - \details Reverses the bit order of the given value. - \param [in] value Value to reverse - \return Reversed value - */ -#if ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \ - (defined (__ARM_ARCH_7EM__) && (__ARM_ARCH_7EM__ == 1)) ) - #define __RBIT __rbit -#else -__attribute__((always_inline)) __STATIC_INLINE uint32_t __RBIT(uint32_t value) -{ - uint32_t result; - uint32_t s = (4U /*sizeof(v)*/ * 8U) - 1U; /* extra shift needed at end */ - - result = value; /* r will be reversed bits of v; first get LSB of v */ - for (value >>= 1U; value != 0U; value >>= 1U) - { - result <<= 1U; - result |= value & 1U; - s--; - } - result <<= s; /* shift when v's highest bits are zero */ - return result; -} -#endif - - -/** - \brief Count leading zeros - \details Counts the number of leading zeros of a data value. - \param [in] value Value to count the leading zeros - \return number of leading zeros in value - */ -#define __CLZ __clz - - -#if ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \ - (defined (__ARM_ARCH_7EM__) && (__ARM_ARCH_7EM__ == 1)) ) - -/** - \brief LDR Exclusive (8 bit) - \details Executes a exclusive LDR instruction for 8 bit value. - \param [in] ptr Pointer to data - \return value of type uint8_t at (*ptr) - */ -#if defined(__ARMCC_VERSION) && (__ARMCC_VERSION < 5060020) - #define __LDREXB(ptr) ((uint8_t ) __ldrex(ptr)) -#else - #define __LDREXB(ptr) _Pragma("push") _Pragma("diag_suppress 3731") ((uint8_t ) __ldrex(ptr)) _Pragma("pop") -#endif - - -/** - \brief LDR Exclusive (16 bit) - \details Executes a exclusive LDR instruction for 16 bit values. - \param [in] ptr Pointer to data - \return value of type uint16_t at (*ptr) - */ -#if defined(__ARMCC_VERSION) && (__ARMCC_VERSION < 5060020) - #define __LDREXH(ptr) ((uint16_t) __ldrex(ptr)) -#else - #define __LDREXH(ptr) _Pragma("push") _Pragma("diag_suppress 3731") ((uint16_t) __ldrex(ptr)) _Pragma("pop") -#endif - - -/** - \brief LDR Exclusive (32 bit) - \details Executes a exclusive LDR instruction for 32 bit values. - \param [in] ptr Pointer to data - \return value of type uint32_t at (*ptr) - */ -#if defined(__ARMCC_VERSION) && (__ARMCC_VERSION < 5060020) - #define __LDREXW(ptr) ((uint32_t ) __ldrex(ptr)) -#else - #define __LDREXW(ptr) _Pragma("push") _Pragma("diag_suppress 3731") ((uint32_t ) __ldrex(ptr)) _Pragma("pop") -#endif - - -/** - \brief STR Exclusive (8 bit) - \details Executes a exclusive STR instruction for 8 bit values. - \param [in] value Value to store - \param [in] ptr Pointer to location - \return 0 Function succeeded - \return 1 Function failed - */ -#if defined(__ARMCC_VERSION) && (__ARMCC_VERSION < 5060020) - #define __STREXB(value, ptr) __strex(value, ptr) -#else - #define __STREXB(value, ptr) _Pragma("push") _Pragma("diag_suppress 3731") __strex(value, ptr) _Pragma("pop") -#endif - - -/** - \brief STR Exclusive (16 bit) - \details Executes a exclusive STR instruction for 16 bit values. - \param [in] value Value to store - \param [in] ptr Pointer to location - \return 0 Function succeeded - \return 1 Function failed - */ -#if defined(__ARMCC_VERSION) && (__ARMCC_VERSION < 5060020) - #define __STREXH(value, ptr) __strex(value, ptr) -#else - #define __STREXH(value, ptr) _Pragma("push") _Pragma("diag_suppress 3731") __strex(value, ptr) _Pragma("pop") -#endif - - -/** - \brief STR Exclusive (32 bit) - \details Executes a exclusive STR instruction for 32 bit values. - \param [in] value Value to store - \param [in] ptr Pointer to location - \return 0 Function succeeded - \return 1 Function failed - */ -#if defined(__ARMCC_VERSION) && (__ARMCC_VERSION < 5060020) - #define __STREXW(value, ptr) __strex(value, ptr) -#else - #define __STREXW(value, ptr) _Pragma("push") _Pragma("diag_suppress 3731") __strex(value, ptr) _Pragma("pop") -#endif - - -/** - \brief Remove the exclusive lock - \details Removes the exclusive lock which is created by LDREX. - */ -#define __CLREX __clrex - - -/** - \brief Signed Saturate - \details Saturates a signed value. - \param [in] value Value to be saturated - \param [in] sat Bit position to saturate to (1..32) - \return Saturated value - */ -#define __SSAT __ssat - - -/** - \brief Unsigned Saturate - \details Saturates an unsigned value. - \param [in] value Value to be saturated - \param [in] sat Bit position to saturate to (0..31) - \return Saturated value - */ -#define __USAT __usat - - -/** - \brief Rotate Right with Extend (32 bit) - \details Moves each bit of a bitstring right by one bit. - The carry input is shifted in at the left end of the bitstring. - \param [in] value Value to rotate - \return Rotated value - */ -#ifndef __NO_EMBEDDED_ASM -__attribute__((section(".rrx_text"))) __STATIC_INLINE __ASM uint32_t __RRX(uint32_t value) -{ - rrx r0, r0 - bx lr -} -#endif - - -/** - \brief LDRT Unprivileged (8 bit) - \details Executes a Unprivileged LDRT instruction for 8 bit value. - \param [in] ptr Pointer to data - \return value of type uint8_t at (*ptr) - */ -#define __LDRBT(ptr) ((uint8_t ) __ldrt(ptr)) - - -/** - \brief LDRT Unprivileged (16 bit) - \details Executes a Unprivileged LDRT instruction for 16 bit values. - \param [in] ptr Pointer to data - \return value of type uint16_t at (*ptr) - */ -#define __LDRHT(ptr) ((uint16_t) __ldrt(ptr)) - - -/** - \brief LDRT Unprivileged (32 bit) - \details Executes a Unprivileged LDRT instruction for 32 bit values. - \param [in] ptr Pointer to data - \return value of type uint32_t at (*ptr) - */ -#define __LDRT(ptr) ((uint32_t ) __ldrt(ptr)) - - -/** - \brief STRT Unprivileged (8 bit) - \details Executes a Unprivileged STRT instruction for 8 bit values. - \param [in] value Value to store - \param [in] ptr Pointer to location - */ -#define __STRBT(value, ptr) __strt(value, ptr) - - -/** - \brief STRT Unprivileged (16 bit) - \details Executes a Unprivileged STRT instruction for 16 bit values. - \param [in] value Value to store - \param [in] ptr Pointer to location - */ -#define __STRHT(value, ptr) __strt(value, ptr) - - -/** - \brief STRT Unprivileged (32 bit) - \details Executes a Unprivileged STRT instruction for 32 bit values. - \param [in] value Value to store - \param [in] ptr Pointer to location - */ -#define __STRT(value, ptr) __strt(value, ptr) - -#else /* ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \ - (defined (__ARM_ARCH_7EM__) && (__ARM_ARCH_7EM__ == 1)) ) */ - -/** - \brief Signed Saturate - \details Saturates a signed value. - \param [in] value Value to be saturated - \param [in] sat Bit position to saturate to (1..32) - \return Saturated value - */ -__attribute__((always_inline)) __STATIC_INLINE int32_t __SSAT(int32_t val, uint32_t sat) -{ - if ((sat >= 1U) && (sat <= 32U)) - { - const int32_t max = (int32_t)((1U << (sat - 1U)) - 1U); - const int32_t min = -1 - max ; - if (val > max) - { - return max; - } - else if (val < min) - { - return min; - } - } - return val; -} - -/** - \brief Unsigned Saturate - \details Saturates an unsigned value. - \param [in] value Value to be saturated - \param [in] sat Bit position to saturate to (0..31) - \return Saturated value - */ -__attribute__((always_inline)) __STATIC_INLINE uint32_t __USAT(int32_t val, uint32_t sat) -{ - if (sat <= 31U) - { - const uint32_t max = ((1U << sat) - 1U); - if (val > (int32_t)max) - { - return max; - } - else if (val < 0) - { - return 0U; - } - } - return (uint32_t)val; -} - -#endif /* ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \ - (defined (__ARM_ARCH_7EM__) && (__ARM_ARCH_7EM__ == 1)) ) */ - -/*@}*/ /* end of group CMSIS_Core_InstructionInterface */ - - -/* ################### Compiler specific Intrinsics ########################### */ -/** \defgroup CMSIS_SIMD_intrinsics CMSIS SIMD Intrinsics - Access to dedicated SIMD instructions - @{ -*/ - -#if ((defined (__ARM_ARCH_7EM__) && (__ARM_ARCH_7EM__ == 1)) ) - -#define __SADD8 __sadd8 -#define __QADD8 __qadd8 -#define __SHADD8 __shadd8 -#define __UADD8 __uadd8 -#define __UQADD8 __uqadd8 -#define __UHADD8 __uhadd8 -#define __SSUB8 __ssub8 -#define __QSUB8 __qsub8 -#define __SHSUB8 __shsub8 -#define __USUB8 __usub8 -#define __UQSUB8 __uqsub8 -#define __UHSUB8 __uhsub8 -#define __SADD16 __sadd16 -#define __QADD16 __qadd16 -#define __SHADD16 __shadd16 -#define __UADD16 __uadd16 -#define __UQADD16 __uqadd16 -#define __UHADD16 __uhadd16 -#define __SSUB16 __ssub16 -#define __QSUB16 __qsub16 -#define __SHSUB16 __shsub16 -#define __USUB16 __usub16 -#define __UQSUB16 __uqsub16 -#define __UHSUB16 __uhsub16 -#define __SASX __sasx -#define __QASX __qasx -#define __SHASX __shasx -#define __UASX __uasx -#define __UQASX __uqasx -#define __UHASX __uhasx -#define __SSAX __ssax -#define __QSAX __qsax -#define __SHSAX __shsax -#define __USAX __usax -#define __UQSAX __uqsax -#define __UHSAX __uhsax -#define __USAD8 __usad8 -#define __USADA8 __usada8 -#define __SSAT16 __ssat16 -#define __USAT16 __usat16 -#define __UXTB16 __uxtb16 -#define __UXTAB16 __uxtab16 -#define __SXTB16 __sxtb16 -#define __SXTAB16 __sxtab16 -#define __SMUAD __smuad -#define __SMUADX __smuadx -#define __SMLAD __smlad -#define __SMLADX __smladx -#define __SMLALD __smlald -#define __SMLALDX __smlaldx -#define __SMUSD __smusd -#define __SMUSDX __smusdx -#define __SMLSD __smlsd -#define __SMLSDX __smlsdx -#define __SMLSLD __smlsld -#define __SMLSLDX __smlsldx -#define __SEL __sel -#define __QADD __qadd -#define __QSUB __qsub - -#define __PKHBT(ARG1,ARG2,ARG3) ( ((((uint32_t)(ARG1)) ) & 0x0000FFFFUL) | \ - ((((uint32_t)(ARG2)) << (ARG3)) & 0xFFFF0000UL) ) - -#define __PKHTB(ARG1,ARG2,ARG3) ( ((((uint32_t)(ARG1)) ) & 0xFFFF0000UL) | \ - ((((uint32_t)(ARG2)) >> (ARG3)) & 0x0000FFFFUL) ) - -#define __SMMLA(ARG1,ARG2,ARG3) ( (int32_t)((((int64_t)(ARG1) * (ARG2)) + \ - ((int64_t)(ARG3) << 32U) ) >> 32U)) - -#endif /* ((defined (__ARM_ARCH_7EM__) && (__ARM_ARCH_7EM__ == 1)) ) */ -/*@} end of group CMSIS_SIMD_intrinsics */ - - -#endif /* __CMSIS_ARMCC_H */ diff --git a/bsp/essemi/es32f0271/libraries/CMSIS/Include/cmsis_armclang.h b/bsp/essemi/es32f0271/libraries/CMSIS/Include/cmsis_armclang.h deleted file mode 100644 index 5c4c20e877..0000000000 --- a/bsp/essemi/es32f0271/libraries/CMSIS/Include/cmsis_armclang.h +++ /dev/null @@ -1,1877 +0,0 @@ -/**************************************************************************//** - * @file cmsis_armclang.h - * @brief CMSIS compiler armclang (Arm Compiler 6) header file - * @version V5.0.4 - * @date 10. January 2018 - ******************************************************************************/ -/* - * Copyright (c) 2009-2018 Arm Limited. All rights reserved. - * - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed under the Apache License, Version 2.0 (the License); you may - * not use this file except in compliance with the License. - * You may obtain a copy of the License at - * - * www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an AS IS BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - */ - -/*lint -esym(9058, IRQn)*/ /* disable MISRA 2012 Rule 2.4 for IRQn */ - -#ifndef __CMSIS_ARMCLANG_H -#define __CMSIS_ARMCLANG_H - -#pragma clang system_header /* treat file as system include file */ - -#ifndef __ARM_COMPAT_H -#include /* Compatibility header for Arm Compiler 5 intrinsics */ -#endif - -/* CMSIS compiler specific defines */ -#ifndef __ASM - #define __ASM __asm -#endif -#ifndef __INLINE - #define __INLINE __inline -#endif -#ifndef __STATIC_INLINE - #define __STATIC_INLINE static __inline -#endif -#ifndef __STATIC_FORCEINLINE - #define __STATIC_FORCEINLINE __attribute__((always_inline)) static __inline -#endif -#ifndef __NO_RETURN - #define __NO_RETURN __attribute__((__noreturn__)) -#endif -#ifndef __USED - #define __USED __attribute__((used)) -#endif -#ifndef __WEAK - #define __WEAK __attribute__((weak)) -#endif -#ifndef __PACKED - #define __PACKED __attribute__((packed, aligned(1))) -#endif -#ifndef __PACKED_STRUCT - #define __PACKED_STRUCT struct __attribute__((packed, aligned(1))) -#endif -#ifndef __PACKED_UNION - #define __PACKED_UNION union __attribute__((packed, aligned(1))) -#endif -#ifndef __UNALIGNED_UINT32 /* deprecated */ - #pragma clang diagnostic push - #pragma clang diagnostic ignored "-Wpacked" -/*lint -esym(9058, T_UINT32)*/ /* disable MISRA 2012 Rule 2.4 for T_UINT32 */ - struct __attribute__((packed)) T_UINT32 { uint32_t v; }; - #pragma clang diagnostic pop - #define __UNALIGNED_UINT32(x) (((struct T_UINT32 *)(x))->v) -#endif -#ifndef __UNALIGNED_UINT16_WRITE - #pragma clang diagnostic push - #pragma clang diagnostic ignored "-Wpacked" -/*lint -esym(9058, T_UINT16_WRITE)*/ /* disable MISRA 2012 Rule 2.4 for T_UINT16_WRITE */ - __PACKED_STRUCT T_UINT16_WRITE { uint16_t v; }; - #pragma clang diagnostic pop - #define __UNALIGNED_UINT16_WRITE(addr, val) (void)((((struct T_UINT16_WRITE *)(void *)(addr))->v) = (val)) -#endif -#ifndef __UNALIGNED_UINT16_READ - #pragma clang diagnostic push - #pragma clang diagnostic ignored "-Wpacked" -/*lint -esym(9058, T_UINT16_READ)*/ /* disable MISRA 2012 Rule 2.4 for T_UINT16_READ */ - __PACKED_STRUCT T_UINT16_READ { uint16_t v; }; - #pragma clang diagnostic pop - #define __UNALIGNED_UINT16_READ(addr) (((const struct T_UINT16_READ *)(const void *)(addr))->v) -#endif -#ifndef __UNALIGNED_UINT32_WRITE - #pragma clang diagnostic push - #pragma clang diagnostic ignored "-Wpacked" -/*lint -esym(9058, T_UINT32_WRITE)*/ /* disable MISRA 2012 Rule 2.4 for T_UINT32_WRITE */ - __PACKED_STRUCT T_UINT32_WRITE { uint32_t v; }; - #pragma clang diagnostic pop - #define __UNALIGNED_UINT32_WRITE(addr, val) (void)((((struct T_UINT32_WRITE *)(void *)(addr))->v) = (val)) -#endif -#ifndef __UNALIGNED_UINT32_READ - #pragma clang diagnostic push - #pragma clang diagnostic ignored "-Wpacked" -/*lint -esym(9058, T_UINT32_READ)*/ /* disable MISRA 2012 Rule 2.4 for T_UINT32_READ */ - __PACKED_STRUCT T_UINT32_READ { uint32_t v; }; - #pragma clang diagnostic pop - #define __UNALIGNED_UINT32_READ(addr) (((const struct T_UINT32_READ *)(const void *)(addr))->v) -#endif -#ifndef __ALIGNED - #define __ALIGNED(x) __attribute__((aligned(x))) -#endif -#ifndef __RESTRICT - #define __RESTRICT __restrict -#endif - - -/* ########################### Core Function Access ########################### */ -/** \ingroup CMSIS_Core_FunctionInterface - \defgroup CMSIS_Core_RegAccFunctions CMSIS Core Register Access Functions - @{ - */ - -/** - \brief Enable IRQ Interrupts - \details Enables IRQ interrupts by clearing the I-bit in the CPSR. - Can only be executed in Privileged modes. - */ -/* intrinsic void __enable_irq(); see arm_compat.h */ - - -/** - \brief Disable IRQ Interrupts - \details Disables IRQ interrupts by setting the I-bit in the CPSR. - Can only be executed in Privileged modes. - */ -/* intrinsic void __disable_irq(); see arm_compat.h */ - - -/** - \brief Get Control Register - \details Returns the content of the Control Register. - \return Control Register value - */ -__STATIC_FORCEINLINE uint32_t __get_CONTROL(void) -{ - uint32_t result; - - __ASM volatile ("MRS %0, control" : "=r" (result) ); - return(result); -} - - -#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) -/** - \brief Get Control Register (non-secure) - \details Returns the content of the non-secure Control Register when in secure mode. - \return non-secure Control Register value - */ -__STATIC_FORCEINLINE uint32_t __TZ_get_CONTROL_NS(void) -{ - uint32_t result; - - __ASM volatile ("MRS %0, control_ns" : "=r" (result) ); - return(result); -} -#endif - - -/** - \brief Set Control Register - \details Writes the given value to the Control Register. - \param [in] control Control Register value to set - */ -__STATIC_FORCEINLINE void __set_CONTROL(uint32_t control) -{ - __ASM volatile ("MSR control, %0" : : "r" (control) : "memory"); -} - - -#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) -/** - \brief Set Control Register (non-secure) - \details Writes the given value to the non-secure Control Register when in secure state. - \param [in] control Control Register value to set - */ -__STATIC_FORCEINLINE void __TZ_set_CONTROL_NS(uint32_t control) -{ - __ASM volatile ("MSR control_ns, %0" : : "r" (control) : "memory"); -} -#endif - - -/** - \brief Get IPSR Register - \details Returns the content of the IPSR Register. - \return IPSR Register value - */ -__STATIC_FORCEINLINE uint32_t __get_IPSR(void) -{ - uint32_t result; - - __ASM volatile ("MRS %0, ipsr" : "=r" (result) ); - return(result); -} - - -/** - \brief Get APSR Register - \details Returns the content of the APSR Register. - \return APSR Register value - */ -__STATIC_FORCEINLINE uint32_t __get_APSR(void) -{ - uint32_t result; - - __ASM volatile ("MRS %0, apsr" : "=r" (result) ); - return(result); -} - - -/** - \brief Get xPSR Register - \details Returns the content of the xPSR Register. - \return xPSR Register value - */ -__STATIC_FORCEINLINE uint32_t __get_xPSR(void) -{ - uint32_t result; - - __ASM volatile ("MRS %0, xpsr" : "=r" (result) ); - return(result); -} - - -/** - \brief Get Process Stack Pointer - \details Returns the current value of the Process Stack Pointer (PSP). - \return PSP Register value - */ -__STATIC_FORCEINLINE uint32_t __get_PSP(void) -{ - register uint32_t result; - - __ASM volatile ("MRS %0, psp" : "=r" (result) ); - return(result); -} - - -#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) -/** - \brief Get Process Stack Pointer (non-secure) - \details Returns the current value of the non-secure Process Stack Pointer (PSP) when in secure state. - \return PSP Register value - */ -__STATIC_FORCEINLINE uint32_t __TZ_get_PSP_NS(void) -{ - register uint32_t result; - - __ASM volatile ("MRS %0, psp_ns" : "=r" (result) ); - return(result); -} -#endif - - -/** - \brief Set Process Stack Pointer - \details Assigns the given value to the Process Stack Pointer (PSP). - \param [in] topOfProcStack Process Stack Pointer value to set - */ -__STATIC_FORCEINLINE void __set_PSP(uint32_t topOfProcStack) -{ - __ASM volatile ("MSR psp, %0" : : "r" (topOfProcStack) : ); -} - - -#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) -/** - \brief Set Process Stack Pointer (non-secure) - \details Assigns the given value to the non-secure Process Stack Pointer (PSP) when in secure state. - \param [in] topOfProcStack Process Stack Pointer value to set - */ -__STATIC_FORCEINLINE void __TZ_set_PSP_NS(uint32_t topOfProcStack) -{ - __ASM volatile ("MSR psp_ns, %0" : : "r" (topOfProcStack) : ); -} -#endif - - -/** - \brief Get Main Stack Pointer - \details Returns the current value of the Main Stack Pointer (MSP). - \return MSP Register value - */ -__STATIC_FORCEINLINE uint32_t __get_MSP(void) -{ - register uint32_t result; - - __ASM volatile ("MRS %0, msp" : "=r" (result) ); - return(result); -} - - -#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) -/** - \brief Get Main Stack Pointer (non-secure) - \details Returns the current value of the non-secure Main Stack Pointer (MSP) when in secure state. - \return MSP Register value - */ -__STATIC_FORCEINLINE uint32_t __TZ_get_MSP_NS(void) -{ - register uint32_t result; - - __ASM volatile ("MRS %0, msp_ns" : "=r" (result) ); - return(result); -} -#endif - - -/** - \brief Set Main Stack Pointer - \details Assigns the given value to the Main Stack Pointer (MSP). - \param [in] topOfMainStack Main Stack Pointer value to set - */ -__STATIC_FORCEINLINE void __set_MSP(uint32_t topOfMainStack) -{ - __ASM volatile ("MSR msp, %0" : : "r" (topOfMainStack) : ); -} - - -#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) -/** - \brief Set Main Stack Pointer (non-secure) - \details Assigns the given value to the non-secure Main Stack Pointer (MSP) when in secure state. - \param [in] topOfMainStack Main Stack Pointer value to set - */ -__STATIC_FORCEINLINE void __TZ_set_MSP_NS(uint32_t topOfMainStack) -{ - __ASM volatile ("MSR msp_ns, %0" : : "r" (topOfMainStack) : ); -} -#endif - - -#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) -/** - \brief Get Stack Pointer (non-secure) - \details Returns the current value of the non-secure Stack Pointer (SP) when in secure state. - \return SP Register value - */ -__STATIC_FORCEINLINE uint32_t __TZ_get_SP_NS(void) -{ - register uint32_t result; - - __ASM volatile ("MRS %0, sp_ns" : "=r" (result) ); - return(result); -} - - -/** - \brief Set Stack Pointer (non-secure) - \details Assigns the given value to the non-secure Stack Pointer (SP) when in secure state. - \param [in] topOfStack Stack Pointer value to set - */ -__STATIC_FORCEINLINE void __TZ_set_SP_NS(uint32_t topOfStack) -{ - __ASM volatile ("MSR sp_ns, %0" : : "r" (topOfStack) : ); -} -#endif - - -/** - \brief Get Priority Mask - \details Returns the current state of the priority mask bit from the Priority Mask Register. - \return Priority Mask value - */ -__STATIC_FORCEINLINE uint32_t __get_PRIMASK(void) -{ - uint32_t result; - - __ASM volatile ("MRS %0, primask" : "=r" (result) ); - return(result); -} - - -#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) -/** - \brief Get Priority Mask (non-secure) - \details Returns the current state of the non-secure priority mask bit from the Priority Mask Register when in secure state. - \return Priority Mask value - */ -__STATIC_FORCEINLINE uint32_t __TZ_get_PRIMASK_NS(void) -{ - uint32_t result; - - __ASM volatile ("MRS %0, primask_ns" : "=r" (result) ); - return(result); -} -#endif - - -/** - \brief Set Priority Mask - \details Assigns the given value to the Priority Mask Register. - \param [in] priMask Priority Mask - */ -__STATIC_FORCEINLINE void __set_PRIMASK(uint32_t priMask) -{ - __ASM volatile ("MSR primask, %0" : : "r" (priMask) : "memory"); -} - - -#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) -/** - \brief Set Priority Mask (non-secure) - \details Assigns the given value to the non-secure Priority Mask Register when in secure state. - \param [in] priMask Priority Mask - */ -__STATIC_FORCEINLINE void __TZ_set_PRIMASK_NS(uint32_t priMask) -{ - __ASM volatile ("MSR primask_ns, %0" : : "r" (priMask) : "memory"); -} -#endif - - -#if ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \ - (defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) || \ - (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) ) -/** - \brief Enable FIQ - \details Enables FIQ interrupts by clearing the F-bit in the CPSR. - Can only be executed in Privileged modes. - */ -#define __enable_fault_irq __enable_fiq /* see arm_compat.h */ - - -/** - \brief Disable FIQ - \details Disables FIQ interrupts by setting the F-bit in the CPSR. - Can only be executed in Privileged modes. - */ -#define __disable_fault_irq __disable_fiq /* see arm_compat.h */ - - -/** - \brief Get Base Priority - \details Returns the current value of the Base Priority register. - \return Base Priority register value - */ -__STATIC_FORCEINLINE uint32_t __get_BASEPRI(void) -{ - uint32_t result; - - __ASM volatile ("MRS %0, basepri" : "=r" (result) ); - return(result); -} - - -#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) -/** - \brief Get Base Priority (non-secure) - \details Returns the current value of the non-secure Base Priority register when in secure state. - \return Base Priority register value - */ -__STATIC_FORCEINLINE uint32_t __TZ_get_BASEPRI_NS(void) -{ - uint32_t result; - - __ASM volatile ("MRS %0, basepri_ns" : "=r" (result) ); - return(result); -} -#endif - - -/** - \brief Set Base Priority - \details Assigns the given value to the Base Priority register. - \param [in] basePri Base Priority value to set - */ -__STATIC_FORCEINLINE void __set_BASEPRI(uint32_t basePri) -{ - __ASM volatile ("MSR basepri, %0" : : "r" (basePri) : "memory"); -} - - -#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) -/** - \brief Set Base Priority (non-secure) - \details Assigns the given value to the non-secure Base Priority register when in secure state. - \param [in] basePri Base Priority value to set - */ -__STATIC_FORCEINLINE void __TZ_set_BASEPRI_NS(uint32_t basePri) -{ - __ASM volatile ("MSR basepri_ns, %0" : : "r" (basePri) : "memory"); -} -#endif - - -/** - \brief Set Base Priority with condition - \details Assigns the given value to the Base Priority register only if BASEPRI masking is disabled, - or the new value increases the BASEPRI priority level. - \param [in] basePri Base Priority value to set - */ -__STATIC_FORCEINLINE void __set_BASEPRI_MAX(uint32_t basePri) -{ - __ASM volatile ("MSR basepri_max, %0" : : "r" (basePri) : "memory"); -} - - -/** - \brief Get Fault Mask - \details Returns the current value of the Fault Mask register. - \return Fault Mask register value - */ -__STATIC_FORCEINLINE uint32_t __get_FAULTMASK(void) -{ - uint32_t result; - - __ASM volatile ("MRS %0, faultmask" : "=r" (result) ); - return(result); -} - - -#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) -/** - \brief Get Fault Mask (non-secure) - \details Returns the current value of the non-secure Fault Mask register when in secure state. - \return Fault Mask register value - */ -__STATIC_FORCEINLINE uint32_t __TZ_get_FAULTMASK_NS(void) -{ - uint32_t result; - - __ASM volatile ("MRS %0, faultmask_ns" : "=r" (result) ); - return(result); -} -#endif - - -/** - \brief Set Fault Mask - \details Assigns the given value to the Fault Mask register. - \param [in] faultMask Fault Mask value to set - */ -__STATIC_FORCEINLINE void __set_FAULTMASK(uint32_t faultMask) -{ - __ASM volatile ("MSR faultmask, %0" : : "r" (faultMask) : "memory"); -} - - -#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) -/** - \brief Set Fault Mask (non-secure) - \details Assigns the given value to the non-secure Fault Mask register when in secure state. - \param [in] faultMask Fault Mask value to set - */ -__STATIC_FORCEINLINE void __TZ_set_FAULTMASK_NS(uint32_t faultMask) -{ - __ASM volatile ("MSR faultmask_ns, %0" : : "r" (faultMask) : "memory"); -} -#endif - -#endif /* ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \ - (defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) || \ - (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) ) */ - - -#if ((defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \ - (defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1)) ) - -/** - \brief Get Process Stack Pointer Limit - Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure - Stack Pointer Limit register hence zero is returned always in non-secure - mode. - - \details Returns the current value of the Process Stack Pointer Limit (PSPLIM). - \return PSPLIM Register value - */ -__STATIC_FORCEINLINE uint32_t __get_PSPLIM(void) -{ -#if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \ - (!defined (__ARM_FEATURE_CMSE) || (__ARM_FEATURE_CMSE < 3))) - // without main extensions, the non-secure PSPLIM is RAZ/WI - return 0U; -#else - register uint32_t result; - __ASM volatile ("MRS %0, psplim" : "=r" (result) ); - return result; -#endif -} - -#if (defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3)) -/** - \brief Get Process Stack Pointer Limit (non-secure) - Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure - Stack Pointer Limit register hence zero is returned always in non-secure - mode. - - \details Returns the current value of the non-secure Process Stack Pointer Limit (PSPLIM) when in secure state. - \return PSPLIM Register value - */ -__STATIC_FORCEINLINE uint32_t __TZ_get_PSPLIM_NS(void) -{ -#if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1))) - // without main extensions, the non-secure PSPLIM is RAZ/WI - return 0U; -#else - register uint32_t result; - __ASM volatile ("MRS %0, psplim_ns" : "=r" (result) ); - return result; -#endif -} -#endif - - -/** - \brief Set Process Stack Pointer Limit - Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure - Stack Pointer Limit register hence the write is silently ignored in non-secure - mode. - - \details Assigns the given value to the Process Stack Pointer Limit (PSPLIM). - \param [in] ProcStackPtrLimit Process Stack Pointer Limit value to set - */ -__STATIC_FORCEINLINE void __set_PSPLIM(uint32_t ProcStackPtrLimit) -{ -#if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \ - (!defined (__ARM_FEATURE_CMSE) || (__ARM_FEATURE_CMSE < 3))) - // without main extensions, the non-secure PSPLIM is RAZ/WI - (void)ProcStackPtrLimit; -#else - __ASM volatile ("MSR psplim, %0" : : "r" (ProcStackPtrLimit)); -#endif -} - - -#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) -/** - \brief Set Process Stack Pointer (non-secure) - Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure - Stack Pointer Limit register hence the write is silently ignored in non-secure - mode. - - \details Assigns the given value to the non-secure Process Stack Pointer Limit (PSPLIM) when in secure state. - \param [in] ProcStackPtrLimit Process Stack Pointer Limit value to set - */ -__STATIC_FORCEINLINE void __TZ_set_PSPLIM_NS(uint32_t ProcStackPtrLimit) -{ -#if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1))) - // without main extensions, the non-secure PSPLIM is RAZ/WI - (void)ProcStackPtrLimit; -#else - __ASM volatile ("MSR psplim_ns, %0\n" : : "r" (ProcStackPtrLimit)); -#endif -} -#endif - - -/** - \brief Get Main Stack Pointer Limit - Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure - Stack Pointer Limit register hence zero is returned always. - - \details Returns the current value of the Main Stack Pointer Limit (MSPLIM). - \return MSPLIM Register value - */ -__STATIC_FORCEINLINE uint32_t __get_MSPLIM(void) -{ -#if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \ - (!defined (__ARM_FEATURE_CMSE) || (__ARM_FEATURE_CMSE < 3))) - // without main extensions, the non-secure MSPLIM is RAZ/WI - return 0U; -#else - register uint32_t result; - __ASM volatile ("MRS %0, msplim" : "=r" (result) ); - return result; -#endif -} - - -#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) -/** - \brief Get Main Stack Pointer Limit (non-secure) - Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure - Stack Pointer Limit register hence zero is returned always. - - \details Returns the current value of the non-secure Main Stack Pointer Limit(MSPLIM) when in secure state. - \return MSPLIM Register value - */ -__STATIC_FORCEINLINE uint32_t __TZ_get_MSPLIM_NS(void) -{ -#if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1))) - // without main extensions, the non-secure MSPLIM is RAZ/WI - return 0U; -#else - register uint32_t result; - __ASM volatile ("MRS %0, msplim_ns" : "=r" (result) ); - return result; -#endif -} -#endif - - -/** - \brief Set Main Stack Pointer Limit - Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure - Stack Pointer Limit register hence the write is silently ignored. - - \details Assigns the given value to the Main Stack Pointer Limit (MSPLIM). - \param [in] MainStackPtrLimit Main Stack Pointer Limit value to set - */ -__STATIC_FORCEINLINE void __set_MSPLIM(uint32_t MainStackPtrLimit) -{ -#if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \ - (!defined (__ARM_FEATURE_CMSE) || (__ARM_FEATURE_CMSE < 3))) - // without main extensions, the non-secure MSPLIM is RAZ/WI - (void)MainStackPtrLimit; -#else - __ASM volatile ("MSR msplim, %0" : : "r" (MainStackPtrLimit)); -#endif -} - - -#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) -/** - \brief Set Main Stack Pointer Limit (non-secure) - Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure - Stack Pointer Limit register hence the write is silently ignored. - - \details Assigns the given value to the non-secure Main Stack Pointer Limit (MSPLIM) when in secure state. - \param [in] MainStackPtrLimit Main Stack Pointer value to set - */ -__STATIC_FORCEINLINE void __TZ_set_MSPLIM_NS(uint32_t MainStackPtrLimit) -{ -#if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1))) - // without main extensions, the non-secure MSPLIM is RAZ/WI - (void)MainStackPtrLimit; -#else - __ASM volatile ("MSR msplim_ns, %0" : : "r" (MainStackPtrLimit)); -#endif -} -#endif - -#endif /* ((defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \ - (defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1)) ) */ - - -#if ((defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) || \ - (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) ) - -/** - \brief Get FPSCR - \details Returns the current value of the Floating Point Status/Control register. - \return Floating Point Status/Control register value - */ -#if ((defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)) && \ - (defined (__FPU_USED ) && (__FPU_USED == 1U)) ) -#define __get_FPSCR (uint32_t)__builtin_arm_get_fpscr -#else -#define __get_FPSCR() ((uint32_t)0U) -#endif - -/** - \brief Set FPSCR - \details Assigns the given value to the Floating Point Status/Control register. - \param [in] fpscr Floating Point Status/Control value to set - */ -#if ((defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)) && \ - (defined (__FPU_USED ) && (__FPU_USED == 1U)) ) -#define __set_FPSCR __builtin_arm_set_fpscr -#else -#define __set_FPSCR(x) ((void)(x)) -#endif - -#endif /* ((defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) || \ - (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) ) */ - - - -/*@} end of CMSIS_Core_RegAccFunctions */ - - -/* ########################## Core Instruction Access ######################### */ -/** \defgroup CMSIS_Core_InstructionInterface CMSIS Core Instruction Interface - Access to dedicated instructions - @{ -*/ - -/* Define macros for porting to both thumb1 and thumb2. - * For thumb1, use low register (r0-r7), specified by constraint "l" - * Otherwise, use general registers, specified by constraint "r" */ -#if defined (__thumb__) && !defined (__thumb2__) -#define __CMSIS_GCC_OUT_REG(r) "=l" (r) -#define __CMSIS_GCC_USE_REG(r) "l" (r) -#else -#define __CMSIS_GCC_OUT_REG(r) "=r" (r) -#define __CMSIS_GCC_USE_REG(r) "r" (r) -#endif - -/** - \brief No Operation - \details No Operation does nothing. This instruction can be used for code alignment purposes. - */ -#define __NOP __builtin_arm_nop - -/** - \brief Wait For Interrupt - \details Wait For Interrupt is a hint instruction that suspends execution until one of a number of events occurs. - */ -#define __WFI __builtin_arm_wfi - - -/** - \brief Wait For Event - \details Wait For Event is a hint instruction that permits the processor to enter - a low-power state until one of a number of events occurs. - */ -#define __WFE __builtin_arm_wfe - - -/** - \brief Send Event - \details Send Event is a hint instruction. It causes an event to be signaled to the CPU. - */ -#define __SEV __builtin_arm_sev - - -/** - \brief Instruction Synchronization Barrier - \details Instruction Synchronization Barrier flushes the pipeline in the processor, - so that all instructions following the ISB are fetched from cache or memory, - after the instruction has been completed. - */ -#define __ISB() __builtin_arm_isb(0xF); - -/** - \brief Data Synchronization Barrier - \details Acts as a special kind of Data Memory Barrier. - It completes when all explicit memory accesses before this instruction complete. - */ -#define __DSB() __builtin_arm_dsb(0xF); - - -/** - \brief Data Memory Barrier - \details Ensures the apparent order of the explicit memory operations before - and after the instruction, without ensuring their completion. - */ -#define __DMB() __builtin_arm_dmb(0xF); - - -/** - \brief Reverse byte order (32 bit) - \details Reverses the byte order in unsigned integer value. For example, 0x12345678 becomes 0x78563412. - \param [in] value Value to reverse - \return Reversed value - */ -#define __REV(value) __builtin_bswap32(value) - - -/** - \brief Reverse byte order (16 bit) - \details Reverses the byte order within each halfword of a word. For example, 0x12345678 becomes 0x34127856. - \param [in] value Value to reverse - \return Reversed value - */ -#define __REV16(value) __ROR(__REV(value), 16) - - -/** - \brief Reverse byte order (16 bit) - \details Reverses the byte order in a 16-bit value and returns the signed 16-bit result. For example, 0x0080 becomes 0x8000. - \param [in] value Value to reverse - \return Reversed value - */ -#define __REVSH(value) (int16_t)__builtin_bswap16(value) - - -/** - \brief Rotate Right in unsigned value (32 bit) - \details Rotate Right (immediate) provides the value of the contents of a register rotated by a variable number of bits. - \param [in] op1 Value to rotate - \param [in] op2 Number of Bits to rotate - \return Rotated value - */ -__STATIC_FORCEINLINE uint32_t __ROR(uint32_t op1, uint32_t op2) -{ - op2 %= 32U; - if (op2 == 0U) - { - return op1; - } - return (op1 >> op2) | (op1 << (32U - op2)); -} - - -/** - \brief Breakpoint - \details Causes the processor to enter Debug state. - Debug tools can use this to investigate system state when the instruction at a particular address is reached. - \param [in] value is ignored by the processor. - If required, a debugger can use it to store additional information about the breakpoint. - */ -#define __BKPT(value) __ASM volatile ("bkpt "#value) - - -/** - \brief Reverse bit order of value - \details Reverses the bit order of the given value. - \param [in] value Value to reverse - \return Reversed value - */ -#define __RBIT __builtin_arm_rbit - -/** - \brief Count leading zeros - \details Counts the number of leading zeros of a data value. - \param [in] value Value to count the leading zeros - \return number of leading zeros in value - */ -#define __CLZ (uint8_t)__builtin_clz - - -#if ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \ - (defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) || \ - (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \ - (defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1)) ) -/** - \brief LDR Exclusive (8 bit) - \details Executes a exclusive LDR instruction for 8 bit value. - \param [in] ptr Pointer to data - \return value of type uint8_t at (*ptr) - */ -#define __LDREXB (uint8_t)__builtin_arm_ldrex - - -/** - \brief LDR Exclusive (16 bit) - \details Executes a exclusive LDR instruction for 16 bit values. - \param [in] ptr Pointer to data - \return value of type uint16_t at (*ptr) - */ -#define __LDREXH (uint16_t)__builtin_arm_ldrex - - -/** - \brief LDR Exclusive (32 bit) - \details Executes a exclusive LDR instruction for 32 bit values. - \param [in] ptr Pointer to data - \return value of type uint32_t at (*ptr) - */ -#define __LDREXW (uint32_t)__builtin_arm_ldrex - - -/** - \brief STR Exclusive (8 bit) - \details Executes a exclusive STR instruction for 8 bit values. - \param [in] value Value to store - \param [in] ptr Pointer to location - \return 0 Function succeeded - \return 1 Function failed - */ -#define __STREXB (uint32_t)__builtin_arm_strex - - -/** - \brief STR Exclusive (16 bit) - \details Executes a exclusive STR instruction for 16 bit values. - \param [in] value Value to store - \param [in] ptr Pointer to location - \return 0 Function succeeded - \return 1 Function failed - */ -#define __STREXH (uint32_t)__builtin_arm_strex - - -/** - \brief STR Exclusive (32 bit) - \details Executes a exclusive STR instruction for 32 bit values. - \param [in] value Value to store - \param [in] ptr Pointer to location - \return 0 Function succeeded - \return 1 Function failed - */ -#define __STREXW (uint32_t)__builtin_arm_strex - - -/** - \brief Remove the exclusive lock - \details Removes the exclusive lock which is created by LDREX. - */ -#define __CLREX __builtin_arm_clrex - -#endif /* ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \ - (defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) || \ - (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \ - (defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1)) ) */ - - -#if ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \ - (defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) || \ - (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) ) - -/** - \brief Signed Saturate - \details Saturates a signed value. - \param [in] value Value to be saturated - \param [in] sat Bit position to saturate to (1..32) - \return Saturated value - */ -#define __SSAT __builtin_arm_ssat - - -/** - \brief Unsigned Saturate - \details Saturates an unsigned value. - \param [in] value Value to be saturated - \param [in] sat Bit position to saturate to (0..31) - \return Saturated value - */ -#define __USAT __builtin_arm_usat - - -/** - \brief Rotate Right with Extend (32 bit) - \details Moves each bit of a bitstring right by one bit. - The carry input is shifted in at the left end of the bitstring. - \param [in] value Value to rotate - \return Rotated value - */ -__STATIC_FORCEINLINE uint32_t __RRX(uint32_t value) -{ - uint32_t result; - - __ASM volatile ("rrx %0, %1" : __CMSIS_GCC_OUT_REG (result) : __CMSIS_GCC_USE_REG (value) ); - return(result); -} - - -/** - \brief LDRT Unprivileged (8 bit) - \details Executes a Unprivileged LDRT instruction for 8 bit value. - \param [in] ptr Pointer to data - \return value of type uint8_t at (*ptr) - */ -__STATIC_FORCEINLINE uint8_t __LDRBT(volatile uint8_t *ptr) -{ - uint32_t result; - - __ASM volatile ("ldrbt %0, %1" : "=r" (result) : "Q" (*ptr) ); - return ((uint8_t) result); /* Add explicit type cast here */ -} - - -/** - \brief LDRT Unprivileged (16 bit) - \details Executes a Unprivileged LDRT instruction for 16 bit values. - \param [in] ptr Pointer to data - \return value of type uint16_t at (*ptr) - */ -__STATIC_FORCEINLINE uint16_t __LDRHT(volatile uint16_t *ptr) -{ - uint32_t result; - - __ASM volatile ("ldrht %0, %1" : "=r" (result) : "Q" (*ptr) ); - return ((uint16_t) result); /* Add explicit type cast here */ -} - - -/** - \brief LDRT Unprivileged (32 bit) - \details Executes a Unprivileged LDRT instruction for 32 bit values. - \param [in] ptr Pointer to data - \return value of type uint32_t at (*ptr) - */ -__STATIC_FORCEINLINE uint32_t __LDRT(volatile uint32_t *ptr) -{ - uint32_t result; - - __ASM volatile ("ldrt %0, %1" : "=r" (result) : "Q" (*ptr) ); - return(result); -} - - -/** - \brief STRT Unprivileged (8 bit) - \details Executes a Unprivileged STRT instruction for 8 bit values. - \param [in] value Value to store - \param [in] ptr Pointer to location - */ -__STATIC_FORCEINLINE void __STRBT(uint8_t value, volatile uint8_t *ptr) -{ - __ASM volatile ("strbt %1, %0" : "=Q" (*ptr) : "r" ((uint32_t)value) ); -} - - -/** - \brief STRT Unprivileged (16 bit) - \details Executes a Unprivileged STRT instruction for 16 bit values. - \param [in] value Value to store - \param [in] ptr Pointer to location - */ -__STATIC_FORCEINLINE void __STRHT(uint16_t value, volatile uint16_t *ptr) -{ - __ASM volatile ("strht %1, %0" : "=Q" (*ptr) : "r" ((uint32_t)value) ); -} - - -/** - \brief STRT Unprivileged (32 bit) - \details Executes a Unprivileged STRT instruction for 32 bit values. - \param [in] value Value to store - \param [in] ptr Pointer to location - */ -__STATIC_FORCEINLINE void __STRT(uint32_t value, volatile uint32_t *ptr) -{ - __ASM volatile ("strt %1, %0" : "=Q" (*ptr) : "r" (value) ); -} - -#else /* ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \ - (defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) || \ - (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) ) */ - -/** - \brief Signed Saturate - \details Saturates a signed value. - \param [in] value Value to be saturated - \param [in] sat Bit position to saturate to (1..32) - \return Saturated value - */ -__STATIC_FORCEINLINE int32_t __SSAT(int32_t val, uint32_t sat) -{ - if ((sat >= 1U) && (sat <= 32U)) - { - const int32_t max = (int32_t)((1U << (sat - 1U)) - 1U); - const int32_t min = -1 - max ; - if (val > max) - { - return max; - } - else if (val < min) - { - return min; - } - } - return val; -} - -/** - \brief Unsigned Saturate - \details Saturates an unsigned value. - \param [in] value Value to be saturated - \param [in] sat Bit position to saturate to (0..31) - \return Saturated value - */ -__STATIC_FORCEINLINE uint32_t __USAT(int32_t val, uint32_t sat) -{ - if (sat <= 31U) - { - const uint32_t max = ((1U << sat) - 1U); - if (val > (int32_t)max) - { - return max; - } - else if (val < 0) - { - return 0U; - } - } - return (uint32_t)val; -} - -#endif /* ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \ - (defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) || \ - (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) ) */ - - -#if ((defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \ - (defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1)) ) -/** - \brief Load-Acquire (8 bit) - \details Executes a LDAB instruction for 8 bit value. - \param [in] ptr Pointer to data - \return value of type uint8_t at (*ptr) - */ -__STATIC_FORCEINLINE uint8_t __LDAB(volatile uint8_t *ptr) -{ - uint32_t result; - - __ASM volatile ("ldab %0, %1" : "=r" (result) : "Q" (*ptr) ); - return ((uint8_t) result); -} - - -/** - \brief Load-Acquire (16 bit) - \details Executes a LDAH instruction for 16 bit values. - \param [in] ptr Pointer to data - \return value of type uint16_t at (*ptr) - */ -__STATIC_FORCEINLINE uint16_t __LDAH(volatile uint16_t *ptr) -{ - uint32_t result; - - __ASM volatile ("ldah %0, %1" : "=r" (result) : "Q" (*ptr) ); - return ((uint16_t) result); -} - - -/** - \brief Load-Acquire (32 bit) - \details Executes a LDA instruction for 32 bit values. - \param [in] ptr Pointer to data - \return value of type uint32_t at (*ptr) - */ -__STATIC_FORCEINLINE uint32_t __LDA(volatile uint32_t *ptr) -{ - uint32_t result; - - __ASM volatile ("lda %0, %1" : "=r" (result) : "Q" (*ptr) ); - return(result); -} - - -/** - \brief Store-Release (8 bit) - \details Executes a STLB instruction for 8 bit values. - \param [in] value Value to store - \param [in] ptr Pointer to location - */ -__STATIC_FORCEINLINE void __STLB(uint8_t value, volatile uint8_t *ptr) -{ - __ASM volatile ("stlb %1, %0" : "=Q" (*ptr) : "r" ((uint32_t)value) ); -} - - -/** - \brief Store-Release (16 bit) - \details Executes a STLH instruction for 16 bit values. - \param [in] value Value to store - \param [in] ptr Pointer to location - */ -__STATIC_FORCEINLINE void __STLH(uint16_t value, volatile uint16_t *ptr) -{ - __ASM volatile ("stlh %1, %0" : "=Q" (*ptr) : "r" ((uint32_t)value) ); -} - - -/** - \brief Store-Release (32 bit) - \details Executes a STL instruction for 32 bit values. - \param [in] value Value to store - \param [in] ptr Pointer to location - */ -__STATIC_FORCEINLINE void __STL(uint32_t value, volatile uint32_t *ptr) -{ - __ASM volatile ("stl %1, %0" : "=Q" (*ptr) : "r" ((uint32_t)value) ); -} - - -/** - \brief Load-Acquire Exclusive (8 bit) - \details Executes a LDAB exclusive instruction for 8 bit value. - \param [in] ptr Pointer to data - \return value of type uint8_t at (*ptr) - */ -#define __LDAEXB (uint8_t)__builtin_arm_ldaex - - -/** - \brief Load-Acquire Exclusive (16 bit) - \details Executes a LDAH exclusive instruction for 16 bit values. - \param [in] ptr Pointer to data - \return value of type uint16_t at (*ptr) - */ -#define __LDAEXH (uint16_t)__builtin_arm_ldaex - - -/** - \brief Load-Acquire Exclusive (32 bit) - \details Executes a LDA exclusive instruction for 32 bit values. - \param [in] ptr Pointer to data - \return value of type uint32_t at (*ptr) - */ -#define __LDAEX (uint32_t)__builtin_arm_ldaex - - -/** - \brief Store-Release Exclusive (8 bit) - \details Executes a STLB exclusive instruction for 8 bit values. - \param [in] value Value to store - \param [in] ptr Pointer to location - \return 0 Function succeeded - \return 1 Function failed - */ -#define __STLEXB (uint32_t)__builtin_arm_stlex - - -/** - \brief Store-Release Exclusive (16 bit) - \details Executes a STLH exclusive instruction for 16 bit values. - \param [in] value Value to store - \param [in] ptr Pointer to location - \return 0 Function succeeded - \return 1 Function failed - */ -#define __STLEXH (uint32_t)__builtin_arm_stlex - - -/** - \brief Store-Release Exclusive (32 bit) - \details Executes a STL exclusive instruction for 32 bit values. - \param [in] value Value to store - \param [in] ptr Pointer to location - \return 0 Function succeeded - \return 1 Function failed - */ -#define __STLEX (uint32_t)__builtin_arm_stlex - -#endif /* ((defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \ - (defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1)) ) */ - -/*@}*/ /* end of group CMSIS_Core_InstructionInterface */ - - -/* ################### Compiler specific Intrinsics ########################### */ -/** \defgroup CMSIS_SIMD_intrinsics CMSIS SIMD Intrinsics - Access to dedicated SIMD instructions - @{ -*/ - -#if (defined (__ARM_FEATURE_DSP) && (__ARM_FEATURE_DSP == 1)) - -__STATIC_FORCEINLINE uint32_t __SADD8(uint32_t op1, uint32_t op2) -{ - uint32_t result; - - __ASM volatile ("sadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); - return(result); -} - -__STATIC_FORCEINLINE uint32_t __QADD8(uint32_t op1, uint32_t op2) -{ - uint32_t result; - - __ASM volatile ("qadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); - return(result); -} - -__STATIC_FORCEINLINE uint32_t __SHADD8(uint32_t op1, uint32_t op2) -{ - uint32_t result; - - __ASM volatile ("shadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); - return(result); -} - -__STATIC_FORCEINLINE uint32_t __UADD8(uint32_t op1, uint32_t op2) -{ - uint32_t result; - - __ASM volatile ("uadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); - return(result); -} - -__STATIC_FORCEINLINE uint32_t __UQADD8(uint32_t op1, uint32_t op2) -{ - uint32_t result; - - __ASM volatile ("uqadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); - return(result); -} - -__STATIC_FORCEINLINE uint32_t __UHADD8(uint32_t op1, uint32_t op2) -{ - uint32_t result; - - __ASM volatile ("uhadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); - return(result); -} - - -__STATIC_FORCEINLINE uint32_t __SSUB8(uint32_t op1, uint32_t op2) -{ - uint32_t result; - - __ASM volatile ("ssub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); - return(result); -} - -__STATIC_FORCEINLINE uint32_t __QSUB8(uint32_t op1, uint32_t op2) -{ - uint32_t result; - - __ASM volatile ("qsub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); - return(result); -} - -__STATIC_FORCEINLINE uint32_t __SHSUB8(uint32_t op1, uint32_t op2) -{ - uint32_t result; - - __ASM volatile ("shsub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); - return(result); -} - -__STATIC_FORCEINLINE uint32_t __USUB8(uint32_t op1, uint32_t op2) -{ - uint32_t result; - - __ASM volatile ("usub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); - return(result); -} - -__STATIC_FORCEINLINE uint32_t __UQSUB8(uint32_t op1, uint32_t op2) -{ - uint32_t result; - - __ASM volatile ("uqsub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); - return(result); -} - -__STATIC_FORCEINLINE uint32_t __UHSUB8(uint32_t op1, uint32_t op2) -{ - uint32_t result; - - __ASM volatile ("uhsub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); - return(result); -} - - -__STATIC_FORCEINLINE uint32_t __SADD16(uint32_t op1, uint32_t op2) -{ - uint32_t result; - - __ASM volatile ("sadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); - return(result); -} - -__STATIC_FORCEINLINE uint32_t __QADD16(uint32_t op1, uint32_t op2) -{ - uint32_t result; - - __ASM volatile ("qadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); - return(result); -} - -__STATIC_FORCEINLINE uint32_t __SHADD16(uint32_t op1, uint32_t op2) -{ - uint32_t result; - - __ASM volatile ("shadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); - return(result); -} - -__STATIC_FORCEINLINE uint32_t __UADD16(uint32_t op1, uint32_t op2) -{ - uint32_t result; - - __ASM volatile ("uadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); - return(result); -} - -__STATIC_FORCEINLINE uint32_t __UQADD16(uint32_t op1, uint32_t op2) -{ - uint32_t result; - - __ASM volatile ("uqadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); - return(result); -} - -__STATIC_FORCEINLINE uint32_t __UHADD16(uint32_t op1, uint32_t op2) -{ - uint32_t result; - - __ASM volatile ("uhadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); - return(result); -} - -__STATIC_FORCEINLINE uint32_t __SSUB16(uint32_t op1, uint32_t op2) -{ - uint32_t result; - - __ASM volatile ("ssub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); - return(result); -} - -__STATIC_FORCEINLINE uint32_t __QSUB16(uint32_t op1, uint32_t op2) -{ - uint32_t result; - - __ASM volatile ("qsub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); - return(result); -} - -__STATIC_FORCEINLINE uint32_t __SHSUB16(uint32_t op1, uint32_t op2) -{ - uint32_t result; - - __ASM volatile ("shsub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); - return(result); -} - -__STATIC_FORCEINLINE uint32_t __USUB16(uint32_t op1, uint32_t op2) -{ - uint32_t result; - - __ASM volatile ("usub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); - return(result); -} - -__STATIC_FORCEINLINE uint32_t __UQSUB16(uint32_t op1, uint32_t op2) -{ - uint32_t result; - - __ASM volatile ("uqsub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); - return(result); -} - -__STATIC_FORCEINLINE uint32_t __UHSUB16(uint32_t op1, uint32_t op2) -{ - uint32_t result; - - __ASM volatile ("uhsub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); - return(result); -} - -__STATIC_FORCEINLINE uint32_t __SASX(uint32_t op1, uint32_t op2) -{ - uint32_t result; - - __ASM volatile ("sasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); - return(result); -} - -__STATIC_FORCEINLINE uint32_t __QASX(uint32_t op1, uint32_t op2) -{ - uint32_t result; - - __ASM volatile ("qasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); - return(result); -} - -__STATIC_FORCEINLINE uint32_t __SHASX(uint32_t op1, uint32_t op2) -{ - uint32_t result; - - __ASM volatile ("shasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); - return(result); -} - -__STATIC_FORCEINLINE uint32_t __UASX(uint32_t op1, uint32_t op2) -{ - uint32_t result; - - __ASM volatile ("uasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); - return(result); -} - -__STATIC_FORCEINLINE uint32_t __UQASX(uint32_t op1, uint32_t op2) -{ - uint32_t result; - - __ASM volatile ("uqasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); - return(result); -} - -__STATIC_FORCEINLINE uint32_t __UHASX(uint32_t op1, uint32_t op2) -{ - uint32_t result; - - __ASM volatile ("uhasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); - return(result); -} - -__STATIC_FORCEINLINE uint32_t __SSAX(uint32_t op1, uint32_t op2) -{ - uint32_t result; - - __ASM volatile ("ssax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); - return(result); -} - -__STATIC_FORCEINLINE uint32_t __QSAX(uint32_t op1, uint32_t op2) -{ - uint32_t result; - - __ASM volatile ("qsax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); - return(result); -} - -__STATIC_FORCEINLINE uint32_t __SHSAX(uint32_t op1, uint32_t op2) -{ - uint32_t result; - - __ASM volatile ("shsax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); - return(result); -} - -__STATIC_FORCEINLINE uint32_t __USAX(uint32_t op1, uint32_t op2) -{ - uint32_t result; - - __ASM volatile ("usax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); - return(result); -} - -__STATIC_FORCEINLINE uint32_t __UQSAX(uint32_t op1, uint32_t op2) -{ - uint32_t result; - - __ASM volatile ("uqsax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); - return(result); -} - -__STATIC_FORCEINLINE uint32_t __UHSAX(uint32_t op1, uint32_t op2) -{ - uint32_t result; - - __ASM volatile ("uhsax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); - return(result); -} - -__STATIC_FORCEINLINE uint32_t __USAD8(uint32_t op1, uint32_t op2) -{ - uint32_t result; - - __ASM volatile ("usad8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); - return(result); -} - -__STATIC_FORCEINLINE uint32_t __USADA8(uint32_t op1, uint32_t op2, uint32_t op3) -{ - uint32_t result; - - __ASM volatile ("usada8 %0, %1, %2, %3" : "=r" (result) : "r" (op1), "r" (op2), "r" (op3) ); - return(result); -} - -#define __SSAT16(ARG1,ARG2) \ -({ \ - int32_t __RES, __ARG1 = (ARG1); \ - __ASM ("ssat16 %0, %1, %2" : "=r" (__RES) : "I" (ARG2), "r" (__ARG1) ); \ - __RES; \ - }) - -#define __USAT16(ARG1,ARG2) \ -({ \ - uint32_t __RES, __ARG1 = (ARG1); \ - __ASM ("usat16 %0, %1, %2" : "=r" (__RES) : "I" (ARG2), "r" (__ARG1) ); \ - __RES; \ - }) - -__STATIC_FORCEINLINE uint32_t __UXTB16(uint32_t op1) -{ - uint32_t result; - - __ASM volatile ("uxtb16 %0, %1" : "=r" (result) : "r" (op1)); - return(result); -} - -__STATIC_FORCEINLINE uint32_t __UXTAB16(uint32_t op1, uint32_t op2) -{ - uint32_t result; - - __ASM volatile ("uxtab16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); - return(result); -} - -__STATIC_FORCEINLINE uint32_t __SXTB16(uint32_t op1) -{ - uint32_t result; - - __ASM volatile ("sxtb16 %0, %1" : "=r" (result) : "r" (op1)); - return(result); -} - -__STATIC_FORCEINLINE uint32_t __SXTAB16(uint32_t op1, uint32_t op2) -{ - uint32_t result; - - __ASM volatile ("sxtab16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); - return(result); -} - -__STATIC_FORCEINLINE uint32_t __SMUAD (uint32_t op1, uint32_t op2) -{ - uint32_t result; - - __ASM volatile ("smuad %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); - return(result); -} - -__STATIC_FORCEINLINE uint32_t __SMUADX (uint32_t op1, uint32_t op2) -{ - uint32_t result; - - __ASM volatile ("smuadx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); - return(result); -} - -__STATIC_FORCEINLINE uint32_t __SMLAD (uint32_t op1, uint32_t op2, uint32_t op3) -{ - uint32_t result; - - __ASM volatile ("smlad %0, %1, %2, %3" : "=r" (result) : "r" (op1), "r" (op2), "r" (op3) ); - return(result); -} - -__STATIC_FORCEINLINE uint32_t __SMLADX (uint32_t op1, uint32_t op2, uint32_t op3) -{ - uint32_t result; - - __ASM volatile ("smladx %0, %1, %2, %3" : "=r" (result) : "r" (op1), "r" (op2), "r" (op3) ); - return(result); -} - -__STATIC_FORCEINLINE uint64_t __SMLALD (uint32_t op1, uint32_t op2, uint64_t acc) -{ - union llreg_u{ - uint32_t w32[2]; - uint64_t w64; - } llr; - llr.w64 = acc; - -#ifndef __ARMEB__ /* Little endian */ - __ASM volatile ("smlald %0, %1, %2, %3" : "=r" (llr.w32[0]), "=r" (llr.w32[1]): "r" (op1), "r" (op2) , "0" (llr.w32[0]), "1" (llr.w32[1]) ); -#else /* Big endian */ - __ASM volatile ("smlald %0, %1, %2, %3" : "=r" (llr.w32[1]), "=r" (llr.w32[0]): "r" (op1), "r" (op2) , "0" (llr.w32[1]), "1" (llr.w32[0]) ); -#endif - - return(llr.w64); -} - -__STATIC_FORCEINLINE uint64_t __SMLALDX (uint32_t op1, uint32_t op2, uint64_t acc) -{ - union llreg_u{ - uint32_t w32[2]; - uint64_t w64; - } llr; - llr.w64 = acc; - -#ifndef __ARMEB__ /* Little endian */ - __ASM volatile ("smlaldx %0, %1, %2, %3" : "=r" (llr.w32[0]), "=r" (llr.w32[1]): "r" (op1), "r" (op2) , "0" (llr.w32[0]), "1" (llr.w32[1]) ); -#else /* Big endian */ - __ASM volatile ("smlaldx %0, %1, %2, %3" : "=r" (llr.w32[1]), "=r" (llr.w32[0]): "r" (op1), "r" (op2) , "0" (llr.w32[1]), "1" (llr.w32[0]) ); -#endif - - return(llr.w64); -} - -__STATIC_FORCEINLINE uint32_t __SMUSD (uint32_t op1, uint32_t op2) -{ - uint32_t result; - - __ASM volatile ("smusd %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); - return(result); -} - -__STATIC_FORCEINLINE uint32_t __SMUSDX (uint32_t op1, uint32_t op2) -{ - uint32_t result; - - __ASM volatile ("smusdx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); - return(result); -} - -__STATIC_FORCEINLINE uint32_t __SMLSD (uint32_t op1, uint32_t op2, uint32_t op3) -{ - uint32_t result; - - __ASM volatile ("smlsd %0, %1, %2, %3" : "=r" (result) : "r" (op1), "r" (op2), "r" (op3) ); - return(result); -} - -__STATIC_FORCEINLINE uint32_t __SMLSDX (uint32_t op1, uint32_t op2, uint32_t op3) -{ - uint32_t result; - - __ASM volatile ("smlsdx %0, %1, %2, %3" : "=r" (result) : "r" (op1), "r" (op2), "r" (op3) ); - return(result); -} - -__STATIC_FORCEINLINE uint64_t __SMLSLD (uint32_t op1, uint32_t op2, uint64_t acc) -{ - union llreg_u{ - uint32_t w32[2]; - uint64_t w64; - } llr; - llr.w64 = acc; - -#ifndef __ARMEB__ /* Little endian */ - __ASM volatile ("smlsld %0, %1, %2, %3" : "=r" (llr.w32[0]), "=r" (llr.w32[1]): "r" (op1), "r" (op2) , "0" (llr.w32[0]), "1" (llr.w32[1]) ); -#else /* Big endian */ - __ASM volatile ("smlsld %0, %1, %2, %3" : "=r" (llr.w32[1]), "=r" (llr.w32[0]): "r" (op1), "r" (op2) , "0" (llr.w32[1]), "1" (llr.w32[0]) ); -#endif - - return(llr.w64); -} - -__STATIC_FORCEINLINE uint64_t __SMLSLDX (uint32_t op1, uint32_t op2, uint64_t acc) -{ - union llreg_u{ - uint32_t w32[2]; - uint64_t w64; - } llr; - llr.w64 = acc; - -#ifndef __ARMEB__ /* Little endian */ - __ASM volatile ("smlsldx %0, %1, %2, %3" : "=r" (llr.w32[0]), "=r" (llr.w32[1]): "r" (op1), "r" (op2) , "0" (llr.w32[0]), "1" (llr.w32[1]) ); -#else /* Big endian */ - __ASM volatile ("smlsldx %0, %1, %2, %3" : "=r" (llr.w32[1]), "=r" (llr.w32[0]): "r" (op1), "r" (op2) , "0" (llr.w32[1]), "1" (llr.w32[0]) ); -#endif - - return(llr.w64); -} - -__STATIC_FORCEINLINE uint32_t __SEL (uint32_t op1, uint32_t op2) -{ - uint32_t result; - - __ASM volatile ("sel %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); - return(result); -} - -__STATIC_FORCEINLINE int32_t __QADD( int32_t op1, int32_t op2) -{ - int32_t result; - - __ASM volatile ("qadd %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); - return(result); -} - -__STATIC_FORCEINLINE int32_t __QSUB( int32_t op1, int32_t op2) -{ - int32_t result; - - __ASM volatile ("qsub %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); - return(result); -} - -#if 0 -#define __PKHBT(ARG1,ARG2,ARG3) \ -({ \ - uint32_t __RES, __ARG1 = (ARG1), __ARG2 = (ARG2); \ - __ASM ("pkhbt %0, %1, %2, lsl %3" : "=r" (__RES) : "r" (__ARG1), "r" (__ARG2), "I" (ARG3) ); \ - __RES; \ - }) - -#define __PKHTB(ARG1,ARG2,ARG3) \ -({ \ - uint32_t __RES, __ARG1 = (ARG1), __ARG2 = (ARG2); \ - if (ARG3 == 0) \ - __ASM ("pkhtb %0, %1, %2" : "=r" (__RES) : "r" (__ARG1), "r" (__ARG2) ); \ - else \ - __ASM ("pkhtb %0, %1, %2, asr %3" : "=r" (__RES) : "r" (__ARG1), "r" (__ARG2), "I" (ARG3) ); \ - __RES; \ - }) -#endif - -#define __PKHBT(ARG1,ARG2,ARG3) ( ((((uint32_t)(ARG1)) ) & 0x0000FFFFUL) | \ - ((((uint32_t)(ARG2)) << (ARG3)) & 0xFFFF0000UL) ) - -#define __PKHTB(ARG1,ARG2,ARG3) ( ((((uint32_t)(ARG1)) ) & 0xFFFF0000UL) | \ - ((((uint32_t)(ARG2)) >> (ARG3)) & 0x0000FFFFUL) ) - -__STATIC_FORCEINLINE int32_t __SMMLA (int32_t op1, int32_t op2, int32_t op3) -{ - int32_t result; - - __ASM volatile ("smmla %0, %1, %2, %3" : "=r" (result): "r" (op1), "r" (op2), "r" (op3) ); - return(result); -} - -#endif /* (__ARM_FEATURE_DSP == 1) */ -/*@} end of group CMSIS_SIMD_intrinsics */ - - -#endif /* __CMSIS_ARMCLANG_H */ diff --git a/bsp/essemi/es32f0271/libraries/CMSIS/Include/cmsis_compiler.h b/bsp/essemi/es32f0271/libraries/CMSIS/Include/cmsis_compiler.h deleted file mode 100644 index 94212eb87a..0000000000 --- a/bsp/essemi/es32f0271/libraries/CMSIS/Include/cmsis_compiler.h +++ /dev/null @@ -1,266 +0,0 @@ -/**************************************************************************//** - * @file cmsis_compiler.h - * @brief CMSIS compiler generic header file - * @version V5.0.4 - * @date 10. January 2018 - ******************************************************************************/ -/* - * Copyright (c) 2009-2018 Arm Limited. All rights reserved. - * - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed under the Apache License, Version 2.0 (the License); you may - * not use this file except in compliance with the License. - * You may obtain a copy of the License at - * - * www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an AS IS BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - */ - -#ifndef __CMSIS_COMPILER_H -#define __CMSIS_COMPILER_H - -#include - -/* - * Arm Compiler 4/5 - */ -#if defined ( __CC_ARM ) - #include "cmsis_armcc.h" - - -/* - * Arm Compiler 6 (armclang) - */ -#elif defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) - #include "cmsis_armclang.h" - - -/* - * GNU Compiler - */ -#elif defined ( __GNUC__ ) - #include "cmsis_gcc.h" - - -/* - * IAR Compiler - */ -#elif defined ( __ICCARM__ ) - #include - - -/* - * TI Arm Compiler - */ -#elif defined ( __TI_ARM__ ) - #include - - #ifndef __ASM - #define __ASM __asm - #endif - #ifndef __INLINE - #define __INLINE inline - #endif - #ifndef __STATIC_INLINE - #define __STATIC_INLINE static inline - #endif - #ifndef __STATIC_FORCEINLINE - #define __STATIC_FORCEINLINE __STATIC_INLINE - #endif - #ifndef __NO_RETURN - #define __NO_RETURN __attribute__((noreturn)) - #endif - #ifndef __USED - #define __USED __attribute__((used)) - #endif - #ifndef __WEAK - #define __WEAK __attribute__((weak)) - #endif - #ifndef __PACKED - #define __PACKED __attribute__((packed)) - #endif - #ifndef __PACKED_STRUCT - #define __PACKED_STRUCT struct __attribute__((packed)) - #endif - #ifndef __PACKED_UNION - #define __PACKED_UNION union __attribute__((packed)) - #endif - #ifndef __UNALIGNED_UINT32 /* deprecated */ - struct __attribute__((packed)) T_UINT32 { uint32_t v; }; - #define __UNALIGNED_UINT32(x) (((struct T_UINT32 *)(x))->v) - #endif - #ifndef __UNALIGNED_UINT16_WRITE - __PACKED_STRUCT T_UINT16_WRITE { uint16_t v; }; - #define __UNALIGNED_UINT16_WRITE(addr, val) (void)((((struct T_UINT16_WRITE *)(void*)(addr))->v) = (val)) - #endif - #ifndef __UNALIGNED_UINT16_READ - __PACKED_STRUCT T_UINT16_READ { uint16_t v; }; - #define __UNALIGNED_UINT16_READ(addr) (((const struct T_UINT16_READ *)(const void *)(addr))->v) - #endif - #ifndef __UNALIGNED_UINT32_WRITE - __PACKED_STRUCT T_UINT32_WRITE { uint32_t v; }; - #define __UNALIGNED_UINT32_WRITE(addr, val) (void)((((struct T_UINT32_WRITE *)(void *)(addr))->v) = (val)) - #endif - #ifndef __UNALIGNED_UINT32_READ - __PACKED_STRUCT T_UINT32_READ { uint32_t v; }; - #define __UNALIGNED_UINT32_READ(addr) (((const struct T_UINT32_READ *)(const void *)(addr))->v) - #endif - #ifndef __ALIGNED - #define __ALIGNED(x) __attribute__((aligned(x))) - #endif - #ifndef __RESTRICT - #warning No compiler specific solution for __RESTRICT. __RESTRICT is ignored. - #define __RESTRICT - #endif - - -/* - * TASKING Compiler - */ -#elif defined ( __TASKING__ ) - /* - * The CMSIS functions have been implemented as intrinsics in the compiler. - * Please use "carm -?i" to get an up to date list of all intrinsics, - * Including the CMSIS ones. - */ - - #ifndef __ASM - #define __ASM __asm - #endif - #ifndef __INLINE - #define __INLINE inline - #endif - #ifndef __STATIC_INLINE - #define __STATIC_INLINE static inline - #endif - #ifndef __STATIC_FORCEINLINE - #define __STATIC_FORCEINLINE __STATIC_INLINE - #endif - #ifndef __NO_RETURN - #define __NO_RETURN __attribute__((noreturn)) - #endif - #ifndef __USED - #define __USED __attribute__((used)) - #endif - #ifndef __WEAK - #define __WEAK __attribute__((weak)) - #endif - #ifndef __PACKED - #define __PACKED __packed__ - #endif - #ifndef __PACKED_STRUCT - #define __PACKED_STRUCT struct __packed__ - #endif - #ifndef __PACKED_UNION - #define __PACKED_UNION union __packed__ - #endif - #ifndef __UNALIGNED_UINT32 /* deprecated */ - struct __packed__ T_UINT32 { uint32_t v; }; - #define __UNALIGNED_UINT32(x) (((struct T_UINT32 *)(x))->v) - #endif - #ifndef __UNALIGNED_UINT16_WRITE - __PACKED_STRUCT T_UINT16_WRITE { uint16_t v; }; - #define __UNALIGNED_UINT16_WRITE(addr, val) (void)((((struct T_UINT16_WRITE *)(void *)(addr))->v) = (val)) - #endif - #ifndef __UNALIGNED_UINT16_READ - __PACKED_STRUCT T_UINT16_READ { uint16_t v; }; - #define __UNALIGNED_UINT16_READ(addr) (((const struct T_UINT16_READ *)(const void *)(addr))->v) - #endif - #ifndef __UNALIGNED_UINT32_WRITE - __PACKED_STRUCT T_UINT32_WRITE { uint32_t v; }; - #define __UNALIGNED_UINT32_WRITE(addr, val) (void)((((struct T_UINT32_WRITE *)(void *)(addr))->v) = (val)) - #endif - #ifndef __UNALIGNED_UINT32_READ - __PACKED_STRUCT T_UINT32_READ { uint32_t v; }; - #define __UNALIGNED_UINT32_READ(addr) (((const struct T_UINT32_READ *)(const void *)(addr))->v) - #endif - #ifndef __ALIGNED - #define __ALIGNED(x) __align(x) - #endif - #ifndef __RESTRICT - #warning No compiler specific solution for __RESTRICT. __RESTRICT is ignored. - #define __RESTRICT - #endif - - -/* - * COSMIC Compiler - */ -#elif defined ( __CSMC__ ) - #include - - #ifndef __ASM - #define __ASM _asm - #endif - #ifndef __INLINE - #define __INLINE inline - #endif - #ifndef __STATIC_INLINE - #define __STATIC_INLINE static inline - #endif - #ifndef __STATIC_FORCEINLINE - #define __STATIC_FORCEINLINE __STATIC_INLINE - #endif - #ifndef __NO_RETURN - // NO RETURN is automatically detected hence no warning here - #define __NO_RETURN - #endif - #ifndef __USED - #warning No compiler specific solution for __USED. __USED is ignored. - #define __USED - #endif - #ifndef __WEAK - #define __WEAK __weak - #endif - #ifndef __PACKED - #define __PACKED @packed - #endif - #ifndef __PACKED_STRUCT - #define __PACKED_STRUCT @packed struct - #endif - #ifndef __PACKED_UNION - #define __PACKED_UNION @packed union - #endif - #ifndef __UNALIGNED_UINT32 /* deprecated */ - @packed struct T_UINT32 { uint32_t v; }; - #define __UNALIGNED_UINT32(x) (((struct T_UINT32 *)(x))->v) - #endif - #ifndef __UNALIGNED_UINT16_WRITE - __PACKED_STRUCT T_UINT16_WRITE { uint16_t v; }; - #define __UNALIGNED_UINT16_WRITE(addr, val) (void)((((struct T_UINT16_WRITE *)(void *)(addr))->v) = (val)) - #endif - #ifndef __UNALIGNED_UINT16_READ - __PACKED_STRUCT T_UINT16_READ { uint16_t v; }; - #define __UNALIGNED_UINT16_READ(addr) (((const struct T_UINT16_READ *)(const void *)(addr))->v) - #endif - #ifndef __UNALIGNED_UINT32_WRITE - __PACKED_STRUCT T_UINT32_WRITE { uint32_t v; }; - #define __UNALIGNED_UINT32_WRITE(addr, val) (void)((((struct T_UINT32_WRITE *)(void *)(addr))->v) = (val)) - #endif - #ifndef __UNALIGNED_UINT32_READ - __PACKED_STRUCT T_UINT32_READ { uint32_t v; }; - #define __UNALIGNED_UINT32_READ(addr) (((const struct T_UINT32_READ *)(const void *)(addr))->v) - #endif - #ifndef __ALIGNED - #warning No compiler specific solution for __ALIGNED. __ALIGNED is ignored. - #define __ALIGNED(x) - #endif - #ifndef __RESTRICT - #warning No compiler specific solution for __RESTRICT. __RESTRICT is ignored. - #define __RESTRICT - #endif - - -#else - #error Unknown compiler. -#endif - - -#endif /* __CMSIS_COMPILER_H */ - diff --git a/bsp/essemi/es32f0271/libraries/CMSIS/Include/cmsis_gcc.h b/bsp/essemi/es32f0271/libraries/CMSIS/Include/cmsis_gcc.h deleted file mode 100644 index 5d0f07e8ac..0000000000 --- a/bsp/essemi/es32f0271/libraries/CMSIS/Include/cmsis_gcc.h +++ /dev/null @@ -1,2088 +0,0 @@ -/**************************************************************************//** - * @file cmsis_gcc.h - * @brief CMSIS compiler GCC header file - * @version V5.0.3 - * @date 16. January 2018 - ******************************************************************************/ -/* - * Copyright (c) 2009-2017 ARM Limited. All rights reserved. - * - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed under the Apache License, Version 2.0 (the License); you may - * not use this file except in compliance with the License. - * You may obtain a copy of the License at - * - * www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an AS IS BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - */ - -#ifndef __CMSIS_GCC_H -#define __CMSIS_GCC_H - -/* ignore some GCC warnings */ -#pragma GCC diagnostic push -#pragma GCC diagnostic ignored "-Wsign-conversion" -#pragma GCC diagnostic ignored "-Wconversion" -#pragma GCC diagnostic ignored "-Wunused-parameter" - -/* Fallback for __has_builtin */ -#ifndef __has_builtin - #define __has_builtin(x) (0) -#endif - -/* CMSIS compiler specific defines */ -#ifndef __ASM - #define __ASM __asm -#endif -#ifndef __INLINE - #define __INLINE inline -#endif -#ifndef __STATIC_INLINE - #define __STATIC_INLINE static inline -#endif -#ifndef __STATIC_FORCEINLINE - #define __STATIC_FORCEINLINE __attribute__((always_inline)) static inline -#endif -#ifndef __NO_RETURN - #define __NO_RETURN __attribute__((__noreturn__)) -#endif -#ifndef __USED - #define __USED __attribute__((used)) -#endif -#ifndef __WEAK - #define __WEAK __attribute__((weak)) -#endif -#ifndef __PACKED - #define __PACKED __attribute__((packed, aligned(1))) -#endif -#ifndef __PACKED_STRUCT - #define __PACKED_STRUCT struct __attribute__((packed, aligned(1))) -#endif -#ifndef __PACKED_UNION - #define __PACKED_UNION union __attribute__((packed, aligned(1))) -#endif -#ifndef __UNALIGNED_UINT32 /* deprecated */ - #pragma GCC diagnostic push - #pragma GCC diagnostic ignored "-Wpacked" - #pragma GCC diagnostic ignored "-Wattributes" - struct __attribute__((packed)) T_UINT32 { uint32_t v; }; - #pragma GCC diagnostic pop - #define __UNALIGNED_UINT32(x) (((struct T_UINT32 *)(x))->v) -#endif -#ifndef __UNALIGNED_UINT16_WRITE - #pragma GCC diagnostic push - #pragma GCC diagnostic ignored "-Wpacked" - #pragma GCC diagnostic ignored "-Wattributes" - __PACKED_STRUCT T_UINT16_WRITE { uint16_t v; }; - #pragma GCC diagnostic pop - #define __UNALIGNED_UINT16_WRITE(addr, val) (void)((((struct T_UINT16_WRITE *)(void *)(addr))->v) = (val)) -#endif -#ifndef __UNALIGNED_UINT16_READ - #pragma GCC diagnostic push - #pragma GCC diagnostic ignored "-Wpacked" - #pragma GCC diagnostic ignored "-Wattributes" - __PACKED_STRUCT T_UINT16_READ { uint16_t v; }; - #pragma GCC diagnostic pop - #define __UNALIGNED_UINT16_READ(addr) (((const struct T_UINT16_READ *)(const void *)(addr))->v) -#endif -#ifndef __UNALIGNED_UINT32_WRITE - #pragma GCC diagnostic push - #pragma GCC diagnostic ignored "-Wpacked" - #pragma GCC diagnostic ignored "-Wattributes" - __PACKED_STRUCT T_UINT32_WRITE { uint32_t v; }; - #pragma GCC diagnostic pop - #define __UNALIGNED_UINT32_WRITE(addr, val) (void)((((struct T_UINT32_WRITE *)(void *)(addr))->v) = (val)) -#endif -#ifndef __UNALIGNED_UINT32_READ - #pragma GCC diagnostic push - #pragma GCC diagnostic ignored "-Wpacked" - #pragma GCC diagnostic ignored "-Wattributes" - __PACKED_STRUCT T_UINT32_READ { uint32_t v; }; - #pragma GCC diagnostic pop - #define __UNALIGNED_UINT32_READ(addr) (((const struct T_UINT32_READ *)(const void *)(addr))->v) -#endif -#ifndef __ALIGNED - #define __ALIGNED(x) __attribute__((aligned(x))) -#endif -#ifndef __RESTRICT - #define __RESTRICT __restrict -#endif - - -/* ########################### Core Function Access ########################### */ -/** \ingroup CMSIS_Core_FunctionInterface - \defgroup CMSIS_Core_RegAccFunctions CMSIS Core Register Access Functions - @{ - */ - -/** - \brief Enable IRQ Interrupts - \details Enables IRQ interrupts by clearing the I-bit in the CPSR. - Can only be executed in Privileged modes. - */ -__STATIC_FORCEINLINE void __enable_irq(void) -{ - __ASM volatile ("cpsie i" : : : "memory"); -} - - -/** - \brief Disable IRQ Interrupts - \details Disables IRQ interrupts by setting the I-bit in the CPSR. - Can only be executed in Privileged modes. - */ -__STATIC_FORCEINLINE void __disable_irq(void) -{ - __ASM volatile ("cpsid i" : : : "memory"); -} - - -/** - \brief Get Control Register - \details Returns the content of the Control Register. - \return Control Register value - */ -__STATIC_FORCEINLINE uint32_t __get_CONTROL(void) -{ - uint32_t result; - - __ASM volatile ("MRS %0, control" : "=r" (result) ); - return(result); -} - - -#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) -/** - \brief Get Control Register (non-secure) - \details Returns the content of the non-secure Control Register when in secure mode. - \return non-secure Control Register value - */ -__STATIC_FORCEINLINE uint32_t __TZ_get_CONTROL_NS(void) -{ - uint32_t result; - - __ASM volatile ("MRS %0, control_ns" : "=r" (result) ); - return(result); -} -#endif - - -/** - \brief Set Control Register - \details Writes the given value to the Control Register. - \param [in] control Control Register value to set - */ -__STATIC_FORCEINLINE void __set_CONTROL(uint32_t control) -{ - __ASM volatile ("MSR control, %0" : : "r" (control) : "memory"); -} - - -#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) -/** - \brief Set Control Register (non-secure) - \details Writes the given value to the non-secure Control Register when in secure state. - \param [in] control Control Register value to set - */ -__STATIC_FORCEINLINE void __TZ_set_CONTROL_NS(uint32_t control) -{ - __ASM volatile ("MSR control_ns, %0" : : "r" (control) : "memory"); -} -#endif - - -/** - \brief Get IPSR Register - \details Returns the content of the IPSR Register. - \return IPSR Register value - */ -__STATIC_FORCEINLINE uint32_t __get_IPSR(void) -{ - uint32_t result; - - __ASM volatile ("MRS %0, ipsr" : "=r" (result) ); - return(result); -} - - -/** - \brief Get APSR Register - \details Returns the content of the APSR Register. - \return APSR Register value - */ -__STATIC_FORCEINLINE uint32_t __get_APSR(void) -{ - uint32_t result; - - __ASM volatile ("MRS %0, apsr" : "=r" (result) ); - return(result); -} - - -/** - \brief Get xPSR Register - \details Returns the content of the xPSR Register. - \return xPSR Register value - */ -__STATIC_FORCEINLINE uint32_t __get_xPSR(void) -{ - uint32_t result; - - __ASM volatile ("MRS %0, xpsr" : "=r" (result) ); - return(result); -} - - -/** - \brief Get Process Stack Pointer - \details Returns the current value of the Process Stack Pointer (PSP). - \return PSP Register value - */ -__STATIC_FORCEINLINE uint32_t __get_PSP(void) -{ - register uint32_t result; - - __ASM volatile ("MRS %0, psp" : "=r" (result) ); - return(result); -} - - -#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) -/** - \brief Get Process Stack Pointer (non-secure) - \details Returns the current value of the non-secure Process Stack Pointer (PSP) when in secure state. - \return PSP Register value - */ -__STATIC_FORCEINLINE uint32_t __TZ_get_PSP_NS(void) -{ - register uint32_t result; - - __ASM volatile ("MRS %0, psp_ns" : "=r" (result) ); - return(result); -} -#endif - - -/** - \brief Set Process Stack Pointer - \details Assigns the given value to the Process Stack Pointer (PSP). - \param [in] topOfProcStack Process Stack Pointer value to set - */ -__STATIC_FORCEINLINE void __set_PSP(uint32_t topOfProcStack) -{ - __ASM volatile ("MSR psp, %0" : : "r" (topOfProcStack) : ); -} - - -#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) -/** - \brief Set Process Stack Pointer (non-secure) - \details Assigns the given value to the non-secure Process Stack Pointer (PSP) when in secure state. - \param [in] topOfProcStack Process Stack Pointer value to set - */ -__STATIC_FORCEINLINE void __TZ_set_PSP_NS(uint32_t topOfProcStack) -{ - __ASM volatile ("MSR psp_ns, %0" : : "r" (topOfProcStack) : ); -} -#endif - - -/** - \brief Get Main Stack Pointer - \details Returns the current value of the Main Stack Pointer (MSP). - \return MSP Register value - */ -__STATIC_FORCEINLINE uint32_t __get_MSP(void) -{ - register uint32_t result; - - __ASM volatile ("MRS %0, msp" : "=r" (result) ); - return(result); -} - - -#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) -/** - \brief Get Main Stack Pointer (non-secure) - \details Returns the current value of the non-secure Main Stack Pointer (MSP) when in secure state. - \return MSP Register value - */ -__STATIC_FORCEINLINE uint32_t __TZ_get_MSP_NS(void) -{ - register uint32_t result; - - __ASM volatile ("MRS %0, msp_ns" : "=r" (result) ); - return(result); -} -#endif - - -/** - \brief Set Main Stack Pointer - \details Assigns the given value to the Main Stack Pointer (MSP). - \param [in] topOfMainStack Main Stack Pointer value to set - */ -__STATIC_FORCEINLINE void __set_MSP(uint32_t topOfMainStack) -{ - __ASM volatile ("MSR msp, %0" : : "r" (topOfMainStack) : ); -} - - -#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) -/** - \brief Set Main Stack Pointer (non-secure) - \details Assigns the given value to the non-secure Main Stack Pointer (MSP) when in secure state. - \param [in] topOfMainStack Main Stack Pointer value to set - */ -__STATIC_FORCEINLINE void __TZ_set_MSP_NS(uint32_t topOfMainStack) -{ - __ASM volatile ("MSR msp_ns, %0" : : "r" (topOfMainStack) : ); -} -#endif - - -#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) -/** - \brief Get Stack Pointer (non-secure) - \details Returns the current value of the non-secure Stack Pointer (SP) when in secure state. - \return SP Register value - */ -__STATIC_FORCEINLINE uint32_t __TZ_get_SP_NS(void) -{ - register uint32_t result; - - __ASM volatile ("MRS %0, sp_ns" : "=r" (result) ); - return(result); -} - - -/** - \brief Set Stack Pointer (non-secure) - \details Assigns the given value to the non-secure Stack Pointer (SP) when in secure state. - \param [in] topOfStack Stack Pointer value to set - */ -__STATIC_FORCEINLINE void __TZ_set_SP_NS(uint32_t topOfStack) -{ - __ASM volatile ("MSR sp_ns, %0" : : "r" (topOfStack) : ); -} -#endif - - -/** - \brief Get Priority Mask - \details Returns the current state of the priority mask bit from the Priority Mask Register. - \return Priority Mask value - */ -__STATIC_FORCEINLINE uint32_t __get_PRIMASK(void) -{ - uint32_t result; - - __ASM volatile ("MRS %0, primask" : "=r" (result) :: "memory"); - return(result); -} - - -#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) -/** - \brief Get Priority Mask (non-secure) - \details Returns the current state of the non-secure priority mask bit from the Priority Mask Register when in secure state. - \return Priority Mask value - */ -__STATIC_FORCEINLINE uint32_t __TZ_get_PRIMASK_NS(void) -{ - uint32_t result; - - __ASM volatile ("MRS %0, primask_ns" : "=r" (result) :: "memory"); - return(result); -} -#endif - - -/** - \brief Set Priority Mask - \details Assigns the given value to the Priority Mask Register. - \param [in] priMask Priority Mask - */ -__STATIC_FORCEINLINE void __set_PRIMASK(uint32_t priMask) -{ - __ASM volatile ("MSR primask, %0" : : "r" (priMask) : "memory"); -} - - -#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) -/** - \brief Set Priority Mask (non-secure) - \details Assigns the given value to the non-secure Priority Mask Register when in secure state. - \param [in] priMask Priority Mask - */ -__STATIC_FORCEINLINE void __TZ_set_PRIMASK_NS(uint32_t priMask) -{ - __ASM volatile ("MSR primask_ns, %0" : : "r" (priMask) : "memory"); -} -#endif - - -#if ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \ - (defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) || \ - (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) ) -/** - \brief Enable FIQ - \details Enables FIQ interrupts by clearing the F-bit in the CPSR. - Can only be executed in Privileged modes. - */ -__STATIC_FORCEINLINE void __enable_fault_irq(void) -{ - __ASM volatile ("cpsie f" : : : "memory"); -} - - -/** - \brief Disable FIQ - \details Disables FIQ interrupts by setting the F-bit in the CPSR. - Can only be executed in Privileged modes. - */ -__STATIC_FORCEINLINE void __disable_fault_irq(void) -{ - __ASM volatile ("cpsid f" : : : "memory"); -} - - -/** - \brief Get Base Priority - \details Returns the current value of the Base Priority register. - \return Base Priority register value - */ -__STATIC_FORCEINLINE uint32_t __get_BASEPRI(void) -{ - uint32_t result; - - __ASM volatile ("MRS %0, basepri" : "=r" (result) ); - return(result); -} - - -#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) -/** - \brief Get Base Priority (non-secure) - \details Returns the current value of the non-secure Base Priority register when in secure state. - \return Base Priority register value - */ -__STATIC_FORCEINLINE uint32_t __TZ_get_BASEPRI_NS(void) -{ - uint32_t result; - - __ASM volatile ("MRS %0, basepri_ns" : "=r" (result) ); - return(result); -} -#endif - - -/** - \brief Set Base Priority - \details Assigns the given value to the Base Priority register. - \param [in] basePri Base Priority value to set - */ -__STATIC_FORCEINLINE void __set_BASEPRI(uint32_t basePri) -{ - __ASM volatile ("MSR basepri, %0" : : "r" (basePri) : "memory"); -} - - -#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) -/** - \brief Set Base Priority (non-secure) - \details Assigns the given value to the non-secure Base Priority register when in secure state. - \param [in] basePri Base Priority value to set - */ -__STATIC_FORCEINLINE void __TZ_set_BASEPRI_NS(uint32_t basePri) -{ - __ASM volatile ("MSR basepri_ns, %0" : : "r" (basePri) : "memory"); -} -#endif - - -/** - \brief Set Base Priority with condition - \details Assigns the given value to the Base Priority register only if BASEPRI masking is disabled, - or the new value increases the BASEPRI priority level. - \param [in] basePri Base Priority value to set - */ -__STATIC_FORCEINLINE void __set_BASEPRI_MAX(uint32_t basePri) -{ - __ASM volatile ("MSR basepri_max, %0" : : "r" (basePri) : "memory"); -} - - -/** - \brief Get Fault Mask - \details Returns the current value of the Fault Mask register. - \return Fault Mask register value - */ -__STATIC_FORCEINLINE uint32_t __get_FAULTMASK(void) -{ - uint32_t result; - - __ASM volatile ("MRS %0, faultmask" : "=r" (result) ); - return(result); -} - - -#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) -/** - \brief Get Fault Mask (non-secure) - \details Returns the current value of the non-secure Fault Mask register when in secure state. - \return Fault Mask register value - */ -__STATIC_FORCEINLINE uint32_t __TZ_get_FAULTMASK_NS(void) -{ - uint32_t result; - - __ASM volatile ("MRS %0, faultmask_ns" : "=r" (result) ); - return(result); -} -#endif - - -/** - \brief Set Fault Mask - \details Assigns the given value to the Fault Mask register. - \param [in] faultMask Fault Mask value to set - */ -__STATIC_FORCEINLINE void __set_FAULTMASK(uint32_t faultMask) -{ - __ASM volatile ("MSR faultmask, %0" : : "r" (faultMask) : "memory"); -} - - -#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) -/** - \brief Set Fault Mask (non-secure) - \details Assigns the given value to the non-secure Fault Mask register when in secure state. - \param [in] faultMask Fault Mask value to set - */ -__STATIC_FORCEINLINE void __TZ_set_FAULTMASK_NS(uint32_t faultMask) -{ - __ASM volatile ("MSR faultmask_ns, %0" : : "r" (faultMask) : "memory"); -} -#endif - -#endif /* ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \ - (defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) || \ - (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) ) */ - - -#if ((defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \ - (defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1)) ) - -/** - \brief Get Process Stack Pointer Limit - Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure - Stack Pointer Limit register hence zero is returned always in non-secure - mode. - - \details Returns the current value of the Process Stack Pointer Limit (PSPLIM). - \return PSPLIM Register value - */ -__STATIC_FORCEINLINE uint32_t __get_PSPLIM(void) -{ -#if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \ - (!defined (__ARM_FEATURE_CMSE) || (__ARM_FEATURE_CMSE < 3))) - // without main extensions, the non-secure PSPLIM is RAZ/WI - return 0U; -#else - register uint32_t result; - __ASM volatile ("MRS %0, psplim" : "=r" (result) ); - return result; -#endif -} - -#if (defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3)) -/** - \brief Get Process Stack Pointer Limit (non-secure) - Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure - Stack Pointer Limit register hence zero is returned always. - - \details Returns the current value of the non-secure Process Stack Pointer Limit (PSPLIM) when in secure state. - \return PSPLIM Register value - */ -__STATIC_FORCEINLINE uint32_t __TZ_get_PSPLIM_NS(void) -{ -#if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1))) - // without main extensions, the non-secure PSPLIM is RAZ/WI - return 0U; -#else - register uint32_t result; - __ASM volatile ("MRS %0, psplim_ns" : "=r" (result) ); - return result; -#endif -} -#endif - - -/** - \brief Set Process Stack Pointer Limit - Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure - Stack Pointer Limit register hence the write is silently ignored in non-secure - mode. - - \details Assigns the given value to the Process Stack Pointer Limit (PSPLIM). - \param [in] ProcStackPtrLimit Process Stack Pointer Limit value to set - */ -__STATIC_FORCEINLINE void __set_PSPLIM(uint32_t ProcStackPtrLimit) -{ -#if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \ - (!defined (__ARM_FEATURE_CMSE) || (__ARM_FEATURE_CMSE < 3))) - // without main extensions, the non-secure PSPLIM is RAZ/WI - (void)ProcStackPtrLimit; -#else - __ASM volatile ("MSR psplim, %0" : : "r" (ProcStackPtrLimit)); -#endif -} - - -#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) -/** - \brief Set Process Stack Pointer (non-secure) - Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure - Stack Pointer Limit register hence the write is silently ignored. - - \details Assigns the given value to the non-secure Process Stack Pointer Limit (PSPLIM) when in secure state. - \param [in] ProcStackPtrLimit Process Stack Pointer Limit value to set - */ -__STATIC_FORCEINLINE void __TZ_set_PSPLIM_NS(uint32_t ProcStackPtrLimit) -{ -#if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1))) - // without main extensions, the non-secure PSPLIM is RAZ/WI - (void)ProcStackPtrLimit; -#else - __ASM volatile ("MSR psplim_ns, %0\n" : : "r" (ProcStackPtrLimit)); -#endif -} -#endif - - -/** - \brief Get Main Stack Pointer Limit - Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure - Stack Pointer Limit register hence zero is returned always in non-secure - mode. - - \details Returns the current value of the Main Stack Pointer Limit (MSPLIM). - \return MSPLIM Register value - */ -__STATIC_FORCEINLINE uint32_t __get_MSPLIM(void) -{ -#if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \ - (!defined (__ARM_FEATURE_CMSE) || (__ARM_FEATURE_CMSE < 3))) - // without main extensions, the non-secure MSPLIM is RAZ/WI - return 0U; -#else - register uint32_t result; - __ASM volatile ("MRS %0, msplim" : "=r" (result) ); - return result; -#endif -} - - -#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) -/** - \brief Get Main Stack Pointer Limit (non-secure) - Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure - Stack Pointer Limit register hence zero is returned always. - - \details Returns the current value of the non-secure Main Stack Pointer Limit(MSPLIM) when in secure state. - \return MSPLIM Register value - */ -__STATIC_FORCEINLINE uint32_t __TZ_get_MSPLIM_NS(void) -{ -#if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1))) - // without main extensions, the non-secure MSPLIM is RAZ/WI - return 0U; -#else - register uint32_t result; - __ASM volatile ("MRS %0, msplim_ns" : "=r" (result) ); - return result; -#endif -} -#endif - - -/** - \brief Set Main Stack Pointer Limit - Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure - Stack Pointer Limit register hence the write is silently ignored in non-secure - mode. - - \details Assigns the given value to the Main Stack Pointer Limit (MSPLIM). - \param [in] MainStackPtrLimit Main Stack Pointer Limit value to set - */ -__STATIC_FORCEINLINE void __set_MSPLIM(uint32_t MainStackPtrLimit) -{ -#if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \ - (!defined (__ARM_FEATURE_CMSE) || (__ARM_FEATURE_CMSE < 3))) - // without main extensions, the non-secure MSPLIM is RAZ/WI - (void)MainStackPtrLimit; -#else - __ASM volatile ("MSR msplim, %0" : : "r" (MainStackPtrLimit)); -#endif -} - - -#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) -/** - \brief Set Main Stack Pointer Limit (non-secure) - Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure - Stack Pointer Limit register hence the write is silently ignored. - - \details Assigns the given value to the non-secure Main Stack Pointer Limit (MSPLIM) when in secure state. - \param [in] MainStackPtrLimit Main Stack Pointer value to set - */ -__STATIC_FORCEINLINE void __TZ_set_MSPLIM_NS(uint32_t MainStackPtrLimit) -{ -#if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1))) - // without main extensions, the non-secure MSPLIM is RAZ/WI - (void)MainStackPtrLimit; -#else - __ASM volatile ("MSR msplim_ns, %0" : : "r" (MainStackPtrLimit)); -#endif -} -#endif - -#endif /* ((defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \ - (defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1)) ) */ - - -#if ((defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) || \ - (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) ) - -/** - \brief Get FPSCR - \details Returns the current value of the Floating Point Status/Control register. - \return Floating Point Status/Control register value - */ -__STATIC_FORCEINLINE uint32_t __get_FPSCR(void) -{ -#if ((defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)) && \ - (defined (__FPU_USED ) && (__FPU_USED == 1U)) ) -#if __has_builtin(__builtin_arm_get_fpscr) || (__GNUC__ > 7) || (__GNUC__ == 7 && __GNUC_MINOR__ >= 2) - /* see https://gcc.gnu.org/ml/gcc-patches/2017-04/msg00443.html */ - return __builtin_arm_get_fpscr(); -#else - uint32_t result; - - __ASM volatile ("VMRS %0, fpscr" : "=r" (result) ); - return(result); -#endif -#else - return(0U); -#endif -} - - -/** - \brief Set FPSCR - \details Assigns the given value to the Floating Point Status/Control register. - \param [in] fpscr Floating Point Status/Control value to set - */ -__STATIC_FORCEINLINE void __set_FPSCR(uint32_t fpscr) -{ -#if ((defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)) && \ - (defined (__FPU_USED ) && (__FPU_USED == 1U)) ) -#if __has_builtin(__builtin_arm_set_fpscr) || (__GNUC__ > 7) || (__GNUC__ == 7 && __GNUC_MINOR__ >= 2) - /* see https://gcc.gnu.org/ml/gcc-patches/2017-04/msg00443.html */ - __builtin_arm_set_fpscr(fpscr); -#else - __ASM volatile ("VMSR fpscr, %0" : : "r" (fpscr) : "vfpcc", "memory"); -#endif -#else - (void)fpscr; -#endif -} - -#endif /* ((defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) || \ - (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) ) */ - - - -/*@} end of CMSIS_Core_RegAccFunctions */ - - -/* ########################## Core Instruction Access ######################### */ -/** \defgroup CMSIS_Core_InstructionInterface CMSIS Core Instruction Interface - Access to dedicated instructions - @{ -*/ - -/* Define macros for porting to both thumb1 and thumb2. - * For thumb1, use low register (r0-r7), specified by constraint "l" - * Otherwise, use general registers, specified by constraint "r" */ -#if defined (__thumb__) && !defined (__thumb2__) -#define __CMSIS_GCC_OUT_REG(r) "=l" (r) -#define __CMSIS_GCC_RW_REG(r) "+l" (r) -#define __CMSIS_GCC_USE_REG(r) "l" (r) -#else -#define __CMSIS_GCC_OUT_REG(r) "=r" (r) -#define __CMSIS_GCC_RW_REG(r) "+r" (r) -#define __CMSIS_GCC_USE_REG(r) "r" (r) -#endif - -/** - \brief No Operation - \details No Operation does nothing. This instruction can be used for code alignment purposes. - */ -#define __NOP() __ASM volatile ("nop") - -/** - \brief Wait For Interrupt - \details Wait For Interrupt is a hint instruction that suspends execution until one of a number of events occurs. - */ -#define __WFI() __ASM volatile ("wfi") - - -/** - \brief Wait For Event - \details Wait For Event is a hint instruction that permits the processor to enter - a low-power state until one of a number of events occurs. - */ -#define __WFE() __ASM volatile ("wfe") - - -/** - \brief Send Event - \details Send Event is a hint instruction. It causes an event to be signaled to the CPU. - */ -#define __SEV() __ASM volatile ("sev") - - -/** - \brief Instruction Synchronization Barrier - \details Instruction Synchronization Barrier flushes the pipeline in the processor, - so that all instructions following the ISB are fetched from cache or memory, - after the instruction has been completed. - */ -__STATIC_FORCEINLINE void __ISB(void) -{ - __ASM volatile ("isb 0xF":::"memory"); -} - - -/** - \brief Data Synchronization Barrier - \details Acts as a special kind of Data Memory Barrier. - It completes when all explicit memory accesses before this instruction complete. - */ -__STATIC_FORCEINLINE void __DSB(void) -{ - __ASM volatile ("dsb 0xF":::"memory"); -} - - -/** - \brief Data Memory Barrier - \details Ensures the apparent order of the explicit memory operations before - and after the instruction, without ensuring their completion. - */ -__STATIC_FORCEINLINE void __DMB(void) -{ - __ASM volatile ("dmb 0xF":::"memory"); -} - - -/** - \brief Reverse byte order (32 bit) - \details Reverses the byte order in unsigned integer value. For example, 0x12345678 becomes 0x78563412. - \param [in] value Value to reverse - \return Reversed value - */ -__STATIC_FORCEINLINE uint32_t __REV(uint32_t value) -{ -#if (__GNUC__ > 4) || (__GNUC__ == 4 && __GNUC_MINOR__ >= 5) - return __builtin_bswap32(value); -#else - uint32_t result; - - __ASM volatile ("rev %0, %1" : __CMSIS_GCC_OUT_REG (result) : __CMSIS_GCC_USE_REG (value) ); - return result; -#endif -} - - -/** - \brief Reverse byte order (16 bit) - \details Reverses the byte order within each halfword of a word. For example, 0x12345678 becomes 0x34127856. - \param [in] value Value to reverse - \return Reversed value - */ -__STATIC_FORCEINLINE uint32_t __REV16(uint32_t value) -{ - uint32_t result; - - __ASM volatile ("rev16 %0, %1" : __CMSIS_GCC_OUT_REG (result) : __CMSIS_GCC_USE_REG (value) ); - return result; -} - - -/** - \brief Reverse byte order (16 bit) - \details Reverses the byte order in a 16-bit value and returns the signed 16-bit result. For example, 0x0080 becomes 0x8000. - \param [in] value Value to reverse - \return Reversed value - */ -__STATIC_FORCEINLINE int16_t __REVSH(int16_t value) -{ -#if (__GNUC__ > 4) || (__GNUC__ == 4 && __GNUC_MINOR__ >= 8) - return (int16_t)__builtin_bswap16(value); -#else - int16_t result; - - __ASM volatile ("revsh %0, %1" : __CMSIS_GCC_OUT_REG (result) : __CMSIS_GCC_USE_REG (value) ); - return result; -#endif -} - - -/** - \brief Rotate Right in unsigned value (32 bit) - \details Rotate Right (immediate) provides the value of the contents of a register rotated by a variable number of bits. - \param [in] op1 Value to rotate - \param [in] op2 Number of Bits to rotate - \return Rotated value - */ -__STATIC_FORCEINLINE uint32_t __ROR(uint32_t op1, uint32_t op2) -{ - op2 %= 32U; - if (op2 == 0U) - { - return op1; - } - return (op1 >> op2) | (op1 << (32U - op2)); -} - - -/** - \brief Breakpoint - \details Causes the processor to enter Debug state. - Debug tools can use this to investigate system state when the instruction at a particular address is reached. - \param [in] value is ignored by the processor. - If required, a debugger can use it to store additional information about the breakpoint. - */ -#define __BKPT(value) __ASM volatile ("bkpt "#value) - - -/** - \brief Reverse bit order of value - \details Reverses the bit order of the given value. - \param [in] value Value to reverse - \return Reversed value - */ -__STATIC_FORCEINLINE uint32_t __RBIT(uint32_t value) -{ - uint32_t result; - -#if ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \ - (defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) || \ - (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) ) - __ASM volatile ("rbit %0, %1" : "=r" (result) : "r" (value) ); -#else - uint32_t s = (4U /*sizeof(v)*/ * 8U) - 1U; /* extra shift needed at end */ - - result = value; /* r will be reversed bits of v; first get LSB of v */ - for (value >>= 1U; value != 0U; value >>= 1U) - { - result <<= 1U; - result |= value & 1U; - s--; - } - result <<= s; /* shift when v's highest bits are zero */ -#endif - return result; -} - - -/** - \brief Count leading zeros - \details Counts the number of leading zeros of a data value. - \param [in] value Value to count the leading zeros - \return number of leading zeros in value - */ -#define __CLZ (uint8_t)__builtin_clz - - -#if ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \ - (defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) || \ - (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \ - (defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1)) ) -/** - \brief LDR Exclusive (8 bit) - \details Executes a exclusive LDR instruction for 8 bit value. - \param [in] ptr Pointer to data - \return value of type uint8_t at (*ptr) - */ -__STATIC_FORCEINLINE uint8_t __LDREXB(volatile uint8_t *addr) -{ - uint32_t result; - -#if (__GNUC__ > 4) || (__GNUC__ == 4 && __GNUC_MINOR__ >= 8) - __ASM volatile ("ldrexb %0, %1" : "=r" (result) : "Q" (*addr) ); -#else - /* Prior to GCC 4.8, "Q" will be expanded to [rx, #0] which is not - accepted by assembler. So has to use following less efficient pattern. - */ - __ASM volatile ("ldrexb %0, [%1]" : "=r" (result) : "r" (addr) : "memory" ); -#endif - return ((uint8_t) result); /* Add explicit type cast here */ -} - - -/** - \brief LDR Exclusive (16 bit) - \details Executes a exclusive LDR instruction for 16 bit values. - \param [in] ptr Pointer to data - \return value of type uint16_t at (*ptr) - */ -__STATIC_FORCEINLINE uint16_t __LDREXH(volatile uint16_t *addr) -{ - uint32_t result; - -#if (__GNUC__ > 4) || (__GNUC__ == 4 && __GNUC_MINOR__ >= 8) - __ASM volatile ("ldrexh %0, %1" : "=r" (result) : "Q" (*addr) ); -#else - /* Prior to GCC 4.8, "Q" will be expanded to [rx, #0] which is not - accepted by assembler. So has to use following less efficient pattern. - */ - __ASM volatile ("ldrexh %0, [%1]" : "=r" (result) : "r" (addr) : "memory" ); -#endif - return ((uint16_t) result); /* Add explicit type cast here */ -} - - -/** - \brief LDR Exclusive (32 bit) - \details Executes a exclusive LDR instruction for 32 bit values. - \param [in] ptr Pointer to data - \return value of type uint32_t at (*ptr) - */ -__STATIC_FORCEINLINE uint32_t __LDREXW(volatile uint32_t *addr) -{ - uint32_t result; - - __ASM volatile ("ldrex %0, %1" : "=r" (result) : "Q" (*addr) ); - return(result); -} - - -/** - \brief STR Exclusive (8 bit) - \details Executes a exclusive STR instruction for 8 bit values. - \param [in] value Value to store - \param [in] ptr Pointer to location - \return 0 Function succeeded - \return 1 Function failed - */ -__STATIC_FORCEINLINE uint32_t __STREXB(uint8_t value, volatile uint8_t *addr) -{ - uint32_t result; - - __ASM volatile ("strexb %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" ((uint32_t)value) ); - return(result); -} - - -/** - \brief STR Exclusive (16 bit) - \details Executes a exclusive STR instruction for 16 bit values. - \param [in] value Value to store - \param [in] ptr Pointer to location - \return 0 Function succeeded - \return 1 Function failed - */ -__STATIC_FORCEINLINE uint32_t __STREXH(uint16_t value, volatile uint16_t *addr) -{ - uint32_t result; - - __ASM volatile ("strexh %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" ((uint32_t)value) ); - return(result); -} - - -/** - \brief STR Exclusive (32 bit) - \details Executes a exclusive STR instruction for 32 bit values. - \param [in] value Value to store - \param [in] ptr Pointer to location - \return 0 Function succeeded - \return 1 Function failed - */ -__STATIC_FORCEINLINE uint32_t __STREXW(uint32_t value, volatile uint32_t *addr) -{ - uint32_t result; - - __ASM volatile ("strex %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" (value) ); - return(result); -} - - -/** - \brief Remove the exclusive lock - \details Removes the exclusive lock which is created by LDREX. - */ -__STATIC_FORCEINLINE void __CLREX(void) -{ - __ASM volatile ("clrex" ::: "memory"); -} - -#endif /* ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \ - (defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) || \ - (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \ - (defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1)) ) */ - - -#if ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \ - (defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) || \ - (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) ) -/** - \brief Signed Saturate - \details Saturates a signed value. - \param [in] ARG1 Value to be saturated - \param [in] ARG2 Bit position to saturate to (1..32) - \return Saturated value - */ -#define __SSAT(ARG1,ARG2) \ -__extension__ \ -({ \ - int32_t __RES, __ARG1 = (ARG1); \ - __ASM ("ssat %0, %1, %2" : "=r" (__RES) : "I" (ARG2), "r" (__ARG1) ); \ - __RES; \ - }) - - -/** - \brief Unsigned Saturate - \details Saturates an unsigned value. - \param [in] ARG1 Value to be saturated - \param [in] ARG2 Bit position to saturate to (0..31) - \return Saturated value - */ -#define __USAT(ARG1,ARG2) \ - __extension__ \ -({ \ - uint32_t __RES, __ARG1 = (ARG1); \ - __ASM ("usat %0, %1, %2" : "=r" (__RES) : "I" (ARG2), "r" (__ARG1) ); \ - __RES; \ - }) - - -/** - \brief Rotate Right with Extend (32 bit) - \details Moves each bit of a bitstring right by one bit. - The carry input is shifted in at the left end of the bitstring. - \param [in] value Value to rotate - \return Rotated value - */ -__STATIC_FORCEINLINE uint32_t __RRX(uint32_t value) -{ - uint32_t result; - - __ASM volatile ("rrx %0, %1" : __CMSIS_GCC_OUT_REG (result) : __CMSIS_GCC_USE_REG (value) ); - return(result); -} - - -/** - \brief LDRT Unprivileged (8 bit) - \details Executes a Unprivileged LDRT instruction for 8 bit value. - \param [in] ptr Pointer to data - \return value of type uint8_t at (*ptr) - */ -__STATIC_FORCEINLINE uint8_t __LDRBT(volatile uint8_t *ptr) -{ - uint32_t result; - -#if (__GNUC__ > 4) || (__GNUC__ == 4 && __GNUC_MINOR__ >= 8) - __ASM volatile ("ldrbt %0, %1" : "=r" (result) : "Q" (*ptr) ); -#else - /* Prior to GCC 4.8, "Q" will be expanded to [rx, #0] which is not - accepted by assembler. So has to use following less efficient pattern. - */ - __ASM volatile ("ldrbt %0, [%1]" : "=r" (result) : "r" (ptr) : "memory" ); -#endif - return ((uint8_t) result); /* Add explicit type cast here */ -} - - -/** - \brief LDRT Unprivileged (16 bit) - \details Executes a Unprivileged LDRT instruction for 16 bit values. - \param [in] ptr Pointer to data - \return value of type uint16_t at (*ptr) - */ -__STATIC_FORCEINLINE uint16_t __LDRHT(volatile uint16_t *ptr) -{ - uint32_t result; - -#if (__GNUC__ > 4) || (__GNUC__ == 4 && __GNUC_MINOR__ >= 8) - __ASM volatile ("ldrht %0, %1" : "=r" (result) : "Q" (*ptr) ); -#else - /* Prior to GCC 4.8, "Q" will be expanded to [rx, #0] which is not - accepted by assembler. So has to use following less efficient pattern. - */ - __ASM volatile ("ldrht %0, [%1]" : "=r" (result) : "r" (ptr) : "memory" ); -#endif - return ((uint16_t) result); /* Add explicit type cast here */ -} - - -/** - \brief LDRT Unprivileged (32 bit) - \details Executes a Unprivileged LDRT instruction for 32 bit values. - \param [in] ptr Pointer to data - \return value of type uint32_t at (*ptr) - */ -__STATIC_FORCEINLINE uint32_t __LDRT(volatile uint32_t *ptr) -{ - uint32_t result; - - __ASM volatile ("ldrt %0, %1" : "=r" (result) : "Q" (*ptr) ); - return(result); -} - - -/** - \brief STRT Unprivileged (8 bit) - \details Executes a Unprivileged STRT instruction for 8 bit values. - \param [in] value Value to store - \param [in] ptr Pointer to location - */ -__STATIC_FORCEINLINE void __STRBT(uint8_t value, volatile uint8_t *ptr) -{ - __ASM volatile ("strbt %1, %0" : "=Q" (*ptr) : "r" ((uint32_t)value) ); -} - - -/** - \brief STRT Unprivileged (16 bit) - \details Executes a Unprivileged STRT instruction for 16 bit values. - \param [in] value Value to store - \param [in] ptr Pointer to location - */ -__STATIC_FORCEINLINE void __STRHT(uint16_t value, volatile uint16_t *ptr) -{ - __ASM volatile ("strht %1, %0" : "=Q" (*ptr) : "r" ((uint32_t)value) ); -} - - -/** - \brief STRT Unprivileged (32 bit) - \details Executes a Unprivileged STRT instruction for 32 bit values. - \param [in] value Value to store - \param [in] ptr Pointer to location - */ -__STATIC_FORCEINLINE void __STRT(uint32_t value, volatile uint32_t *ptr) -{ - __ASM volatile ("strt %1, %0" : "=Q" (*ptr) : "r" (value) ); -} - -#else /* ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \ - (defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) || \ - (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) ) */ - -/** - \brief Signed Saturate - \details Saturates a signed value. - \param [in] value Value to be saturated - \param [in] sat Bit position to saturate to (1..32) - \return Saturated value - */ -__STATIC_FORCEINLINE int32_t __SSAT(int32_t val, uint32_t sat) -{ - if ((sat >= 1U) && (sat <= 32U)) - { - const int32_t max = (int32_t)((1U << (sat - 1U)) - 1U); - const int32_t min = -1 - max ; - if (val > max) - { - return max; - } - else if (val < min) - { - return min; - } - } - return val; -} - -/** - \brief Unsigned Saturate - \details Saturates an unsigned value. - \param [in] value Value to be saturated - \param [in] sat Bit position to saturate to (0..31) - \return Saturated value - */ -__STATIC_FORCEINLINE uint32_t __USAT(int32_t val, uint32_t sat) -{ - if (sat <= 31U) - { - const uint32_t max = ((1U << sat) - 1U); - if (val > (int32_t)max) - { - return max; - } - else if (val < 0) - { - return 0U; - } - } - return (uint32_t)val; -} - -#endif /* ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \ - (defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) || \ - (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) ) */ - - -#if ((defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \ - (defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1)) ) -/** - \brief Load-Acquire (8 bit) - \details Executes a LDAB instruction for 8 bit value. - \param [in] ptr Pointer to data - \return value of type uint8_t at (*ptr) - */ -__STATIC_FORCEINLINE uint8_t __LDAB(volatile uint8_t *ptr) -{ - uint32_t result; - - __ASM volatile ("ldab %0, %1" : "=r" (result) : "Q" (*ptr) ); - return ((uint8_t) result); -} - - -/** - \brief Load-Acquire (16 bit) - \details Executes a LDAH instruction for 16 bit values. - \param [in] ptr Pointer to data - \return value of type uint16_t at (*ptr) - */ -__STATIC_FORCEINLINE uint16_t __LDAH(volatile uint16_t *ptr) -{ - uint32_t result; - - __ASM volatile ("ldah %0, %1" : "=r" (result) : "Q" (*ptr) ); - return ((uint16_t) result); -} - - -/** - \brief Load-Acquire (32 bit) - \details Executes a LDA instruction for 32 bit values. - \param [in] ptr Pointer to data - \return value of type uint32_t at (*ptr) - */ -__STATIC_FORCEINLINE uint32_t __LDA(volatile uint32_t *ptr) -{ - uint32_t result; - - __ASM volatile ("lda %0, %1" : "=r" (result) : "Q" (*ptr) ); - return(result); -} - - -/** - \brief Store-Release (8 bit) - \details Executes a STLB instruction for 8 bit values. - \param [in] value Value to store - \param [in] ptr Pointer to location - */ -__STATIC_FORCEINLINE void __STLB(uint8_t value, volatile uint8_t *ptr) -{ - __ASM volatile ("stlb %1, %0" : "=Q" (*ptr) : "r" ((uint32_t)value) ); -} - - -/** - \brief Store-Release (16 bit) - \details Executes a STLH instruction for 16 bit values. - \param [in] value Value to store - \param [in] ptr Pointer to location - */ -__STATIC_FORCEINLINE void __STLH(uint16_t value, volatile uint16_t *ptr) -{ - __ASM volatile ("stlh %1, %0" : "=Q" (*ptr) : "r" ((uint32_t)value) ); -} - - -/** - \brief Store-Release (32 bit) - \details Executes a STL instruction for 32 bit values. - \param [in] value Value to store - \param [in] ptr Pointer to location - */ -__STATIC_FORCEINLINE void __STL(uint32_t value, volatile uint32_t *ptr) -{ - __ASM volatile ("stl %1, %0" : "=Q" (*ptr) : "r" ((uint32_t)value) ); -} - - -/** - \brief Load-Acquire Exclusive (8 bit) - \details Executes a LDAB exclusive instruction for 8 bit value. - \param [in] ptr Pointer to data - \return value of type uint8_t at (*ptr) - */ -__STATIC_FORCEINLINE uint8_t __LDAEXB(volatile uint8_t *ptr) -{ - uint32_t result; - - __ASM volatile ("ldaexb %0, %1" : "=r" (result) : "Q" (*ptr) ); - return ((uint8_t) result); -} - - -/** - \brief Load-Acquire Exclusive (16 bit) - \details Executes a LDAH exclusive instruction for 16 bit values. - \param [in] ptr Pointer to data - \return value of type uint16_t at (*ptr) - */ -__STATIC_FORCEINLINE uint16_t __LDAEXH(volatile uint16_t *ptr) -{ - uint32_t result; - - __ASM volatile ("ldaexh %0, %1" : "=r" (result) : "Q" (*ptr) ); - return ((uint16_t) result); -} - - -/** - \brief Load-Acquire Exclusive (32 bit) - \details Executes a LDA exclusive instruction for 32 bit values. - \param [in] ptr Pointer to data - \return value of type uint32_t at (*ptr) - */ -__STATIC_FORCEINLINE uint32_t __LDAEX(volatile uint32_t *ptr) -{ - uint32_t result; - - __ASM volatile ("ldaex %0, %1" : "=r" (result) : "Q" (*ptr) ); - return(result); -} - - -/** - \brief Store-Release Exclusive (8 bit) - \details Executes a STLB exclusive instruction for 8 bit values. - \param [in] value Value to store - \param [in] ptr Pointer to location - \return 0 Function succeeded - \return 1 Function failed - */ -__STATIC_FORCEINLINE uint32_t __STLEXB(uint8_t value, volatile uint8_t *ptr) -{ - uint32_t result; - - __ASM volatile ("stlexb %0, %2, %1" : "=&r" (result), "=Q" (*ptr) : "r" ((uint32_t)value) ); - return(result); -} - - -/** - \brief Store-Release Exclusive (16 bit) - \details Executes a STLH exclusive instruction for 16 bit values. - \param [in] value Value to store - \param [in] ptr Pointer to location - \return 0 Function succeeded - \return 1 Function failed - */ -__STATIC_FORCEINLINE uint32_t __STLEXH(uint16_t value, volatile uint16_t *ptr) -{ - uint32_t result; - - __ASM volatile ("stlexh %0, %2, %1" : "=&r" (result), "=Q" (*ptr) : "r" ((uint32_t)value) ); - return(result); -} - - -/** - \brief Store-Release Exclusive (32 bit) - \details Executes a STL exclusive instruction for 32 bit values. - \param [in] value Value to store - \param [in] ptr Pointer to location - \return 0 Function succeeded - \return 1 Function failed - */ -__STATIC_FORCEINLINE uint32_t __STLEX(uint32_t value, volatile uint32_t *ptr) -{ - uint32_t result; - - __ASM volatile ("stlex %0, %2, %1" : "=&r" (result), "=Q" (*ptr) : "r" ((uint32_t)value) ); - return(result); -} - -#endif /* ((defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \ - (defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1)) ) */ - -/*@}*/ /* end of group CMSIS_Core_InstructionInterface */ - - -/* ################### Compiler specific Intrinsics ########################### */ -/** \defgroup CMSIS_SIMD_intrinsics CMSIS SIMD Intrinsics - Access to dedicated SIMD instructions - @{ -*/ - -#if (defined (__ARM_FEATURE_DSP) && (__ARM_FEATURE_DSP == 1)) - -__STATIC_FORCEINLINE uint32_t __SADD8(uint32_t op1, uint32_t op2) -{ - uint32_t result; - - __ASM volatile ("sadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); - return(result); -} - -__STATIC_FORCEINLINE uint32_t __QADD8(uint32_t op1, uint32_t op2) -{ - uint32_t result; - - __ASM volatile ("qadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); - return(result); -} - -__STATIC_FORCEINLINE uint32_t __SHADD8(uint32_t op1, uint32_t op2) -{ - uint32_t result; - - __ASM volatile ("shadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); - return(result); -} - -__STATIC_FORCEINLINE uint32_t __UADD8(uint32_t op1, uint32_t op2) -{ - uint32_t result; - - __ASM volatile ("uadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); - return(result); -} - -__STATIC_FORCEINLINE uint32_t __UQADD8(uint32_t op1, uint32_t op2) -{ - uint32_t result; - - __ASM volatile ("uqadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); - return(result); -} - -__STATIC_FORCEINLINE uint32_t __UHADD8(uint32_t op1, uint32_t op2) -{ - uint32_t result; - - __ASM volatile ("uhadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); - return(result); -} - - -__STATIC_FORCEINLINE uint32_t __SSUB8(uint32_t op1, uint32_t op2) -{ - uint32_t result; - - __ASM volatile ("ssub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); - return(result); -} - -__STATIC_FORCEINLINE uint32_t __QSUB8(uint32_t op1, uint32_t op2) -{ - uint32_t result; - - __ASM volatile ("qsub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); - return(result); -} - -__STATIC_FORCEINLINE uint32_t __SHSUB8(uint32_t op1, uint32_t op2) -{ - uint32_t result; - - __ASM volatile ("shsub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); - return(result); -} - -__STATIC_FORCEINLINE uint32_t __USUB8(uint32_t op1, uint32_t op2) -{ - uint32_t result; - - __ASM volatile ("usub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); - return(result); -} - -__STATIC_FORCEINLINE uint32_t __UQSUB8(uint32_t op1, uint32_t op2) -{ - uint32_t result; - - __ASM volatile ("uqsub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); - return(result); -} - -__STATIC_FORCEINLINE uint32_t __UHSUB8(uint32_t op1, uint32_t op2) -{ - uint32_t result; - - __ASM volatile ("uhsub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); - return(result); -} - - -__STATIC_FORCEINLINE uint32_t __SADD16(uint32_t op1, uint32_t op2) -{ - uint32_t result; - - __ASM volatile ("sadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); - return(result); -} - -__STATIC_FORCEINLINE uint32_t __QADD16(uint32_t op1, uint32_t op2) -{ - uint32_t result; - - __ASM volatile ("qadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); - return(result); -} - -__STATIC_FORCEINLINE uint32_t __SHADD16(uint32_t op1, uint32_t op2) -{ - uint32_t result; - - __ASM volatile ("shadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); - return(result); -} - -__STATIC_FORCEINLINE uint32_t __UADD16(uint32_t op1, uint32_t op2) -{ - uint32_t result; - - __ASM volatile ("uadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); - return(result); -} - -__STATIC_FORCEINLINE uint32_t __UQADD16(uint32_t op1, uint32_t op2) -{ - uint32_t result; - - __ASM volatile ("uqadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); - return(result); -} - -__STATIC_FORCEINLINE uint32_t __UHADD16(uint32_t op1, uint32_t op2) -{ - uint32_t result; - - __ASM volatile ("uhadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); - return(result); -} - -__STATIC_FORCEINLINE uint32_t __SSUB16(uint32_t op1, uint32_t op2) -{ - uint32_t result; - - __ASM volatile ("ssub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); - return(result); -} - -__STATIC_FORCEINLINE uint32_t __QSUB16(uint32_t op1, uint32_t op2) -{ - uint32_t result; - - __ASM volatile ("qsub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); - return(result); -} - -__STATIC_FORCEINLINE uint32_t __SHSUB16(uint32_t op1, uint32_t op2) -{ - uint32_t result; - - __ASM volatile ("shsub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); - return(result); -} - -__STATIC_FORCEINLINE uint32_t __USUB16(uint32_t op1, uint32_t op2) -{ - uint32_t result; - - __ASM volatile ("usub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); - return(result); -} - -__STATIC_FORCEINLINE uint32_t __UQSUB16(uint32_t op1, uint32_t op2) -{ - uint32_t result; - - __ASM volatile ("uqsub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); - return(result); -} - -__STATIC_FORCEINLINE uint32_t __UHSUB16(uint32_t op1, uint32_t op2) -{ - uint32_t result; - - __ASM volatile ("uhsub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); - return(result); -} - -__STATIC_FORCEINLINE uint32_t __SASX(uint32_t op1, uint32_t op2) -{ - uint32_t result; - - __ASM volatile ("sasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); - return(result); -} - -__STATIC_FORCEINLINE uint32_t __QASX(uint32_t op1, uint32_t op2) -{ - uint32_t result; - - __ASM volatile ("qasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); - return(result); -} - -__STATIC_FORCEINLINE uint32_t __SHASX(uint32_t op1, uint32_t op2) -{ - uint32_t result; - - __ASM volatile ("shasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); - return(result); -} - -__STATIC_FORCEINLINE uint32_t __UASX(uint32_t op1, uint32_t op2) -{ - uint32_t result; - - __ASM volatile ("uasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); - return(result); -} - -__STATIC_FORCEINLINE uint32_t __UQASX(uint32_t op1, uint32_t op2) -{ - uint32_t result; - - __ASM volatile ("uqasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); - return(result); -} - -__STATIC_FORCEINLINE uint32_t __UHASX(uint32_t op1, uint32_t op2) -{ - uint32_t result; - - __ASM volatile ("uhasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); - return(result); -} - -__STATIC_FORCEINLINE uint32_t __SSAX(uint32_t op1, uint32_t op2) -{ - uint32_t result; - - __ASM volatile ("ssax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); - return(result); -} - -__STATIC_FORCEINLINE uint32_t __QSAX(uint32_t op1, uint32_t op2) -{ - uint32_t result; - - __ASM volatile ("qsax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); - return(result); -} - -__STATIC_FORCEINLINE uint32_t __SHSAX(uint32_t op1, uint32_t op2) -{ - uint32_t result; - - __ASM volatile ("shsax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); - return(result); -} - -__STATIC_FORCEINLINE uint32_t __USAX(uint32_t op1, uint32_t op2) -{ - uint32_t result; - - __ASM volatile ("usax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); - return(result); -} - -__STATIC_FORCEINLINE uint32_t __UQSAX(uint32_t op1, uint32_t op2) -{ - uint32_t result; - - __ASM volatile ("uqsax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); - return(result); -} - -__STATIC_FORCEINLINE uint32_t __UHSAX(uint32_t op1, uint32_t op2) -{ - uint32_t result; - - __ASM volatile ("uhsax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); - return(result); -} - -__STATIC_FORCEINLINE uint32_t __USAD8(uint32_t op1, uint32_t op2) -{ - uint32_t result; - - __ASM volatile ("usad8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); - return(result); -} - -__STATIC_FORCEINLINE uint32_t __USADA8(uint32_t op1, uint32_t op2, uint32_t op3) -{ - uint32_t result; - - __ASM volatile ("usada8 %0, %1, %2, %3" : "=r" (result) : "r" (op1), "r" (op2), "r" (op3) ); - return(result); -} - -#define __SSAT16(ARG1,ARG2) \ -({ \ - int32_t __RES, __ARG1 = (ARG1); \ - __ASM ("ssat16 %0, %1, %2" : "=r" (__RES) : "I" (ARG2), "r" (__ARG1) ); \ - __RES; \ - }) - -#define __USAT16(ARG1,ARG2) \ -({ \ - uint32_t __RES, __ARG1 = (ARG1); \ - __ASM ("usat16 %0, %1, %2" : "=r" (__RES) : "I" (ARG2), "r" (__ARG1) ); \ - __RES; \ - }) - -__STATIC_FORCEINLINE uint32_t __UXTB16(uint32_t op1) -{ - uint32_t result; - - __ASM volatile ("uxtb16 %0, %1" : "=r" (result) : "r" (op1)); - return(result); -} - -__STATIC_FORCEINLINE uint32_t __UXTAB16(uint32_t op1, uint32_t op2) -{ - uint32_t result; - - __ASM volatile ("uxtab16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); - return(result); -} - -__STATIC_FORCEINLINE uint32_t __SXTB16(uint32_t op1) -{ - uint32_t result; - - __ASM volatile ("sxtb16 %0, %1" : "=r" (result) : "r" (op1)); - return(result); -} - -__STATIC_FORCEINLINE uint32_t __SXTAB16(uint32_t op1, uint32_t op2) -{ - uint32_t result; - - __ASM volatile ("sxtab16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); - return(result); -} - -__STATIC_FORCEINLINE uint32_t __SMUAD (uint32_t op1, uint32_t op2) -{ - uint32_t result; - - __ASM volatile ("smuad %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); - return(result); -} - -__STATIC_FORCEINLINE uint32_t __SMUADX (uint32_t op1, uint32_t op2) -{ - uint32_t result; - - __ASM volatile ("smuadx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); - return(result); -} - -__STATIC_FORCEINLINE uint32_t __SMLAD (uint32_t op1, uint32_t op2, uint32_t op3) -{ - uint32_t result; - - __ASM volatile ("smlad %0, %1, %2, %3" : "=r" (result) : "r" (op1), "r" (op2), "r" (op3) ); - return(result); -} - -__STATIC_FORCEINLINE uint32_t __SMLADX (uint32_t op1, uint32_t op2, uint32_t op3) -{ - uint32_t result; - - __ASM volatile ("smladx %0, %1, %2, %3" : "=r" (result) : "r" (op1), "r" (op2), "r" (op3) ); - return(result); -} - -__STATIC_FORCEINLINE uint64_t __SMLALD (uint32_t op1, uint32_t op2, uint64_t acc) -{ - union llreg_u{ - uint32_t w32[2]; - uint64_t w64; - } llr; - llr.w64 = acc; - -#ifndef __ARMEB__ /* Little endian */ - __ASM volatile ("smlald %0, %1, %2, %3" : "=r" (llr.w32[0]), "=r" (llr.w32[1]): "r" (op1), "r" (op2) , "0" (llr.w32[0]), "1" (llr.w32[1]) ); -#else /* Big endian */ - __ASM volatile ("smlald %0, %1, %2, %3" : "=r" (llr.w32[1]), "=r" (llr.w32[0]): "r" (op1), "r" (op2) , "0" (llr.w32[1]), "1" (llr.w32[0]) ); -#endif - - return(llr.w64); -} - -__STATIC_FORCEINLINE uint64_t __SMLALDX (uint32_t op1, uint32_t op2, uint64_t acc) -{ - union llreg_u{ - uint32_t w32[2]; - uint64_t w64; - } llr; - llr.w64 = acc; - -#ifndef __ARMEB__ /* Little endian */ - __ASM volatile ("smlaldx %0, %1, %2, %3" : "=r" (llr.w32[0]), "=r" (llr.w32[1]): "r" (op1), "r" (op2) , "0" (llr.w32[0]), "1" (llr.w32[1]) ); -#else /* Big endian */ - __ASM volatile ("smlaldx %0, %1, %2, %3" : "=r" (llr.w32[1]), "=r" (llr.w32[0]): "r" (op1), "r" (op2) , "0" (llr.w32[1]), "1" (llr.w32[0]) ); -#endif - - return(llr.w64); -} - -__STATIC_FORCEINLINE uint32_t __SMUSD (uint32_t op1, uint32_t op2) -{ - uint32_t result; - - __ASM volatile ("smusd %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); - return(result); -} - -__STATIC_FORCEINLINE uint32_t __SMUSDX (uint32_t op1, uint32_t op2) -{ - uint32_t result; - - __ASM volatile ("smusdx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); - return(result); -} - -__STATIC_FORCEINLINE uint32_t __SMLSD (uint32_t op1, uint32_t op2, uint32_t op3) -{ - uint32_t result; - - __ASM volatile ("smlsd %0, %1, %2, %3" : "=r" (result) : "r" (op1), "r" (op2), "r" (op3) ); - return(result); -} - -__STATIC_FORCEINLINE uint32_t __SMLSDX (uint32_t op1, uint32_t op2, uint32_t op3) -{ - uint32_t result; - - __ASM volatile ("smlsdx %0, %1, %2, %3" : "=r" (result) : "r" (op1), "r" (op2), "r" (op3) ); - return(result); -} - -__STATIC_FORCEINLINE uint64_t __SMLSLD (uint32_t op1, uint32_t op2, uint64_t acc) -{ - union llreg_u{ - uint32_t w32[2]; - uint64_t w64; - } llr; - llr.w64 = acc; - -#ifndef __ARMEB__ /* Little endian */ - __ASM volatile ("smlsld %0, %1, %2, %3" : "=r" (llr.w32[0]), "=r" (llr.w32[1]): "r" (op1), "r" (op2) , "0" (llr.w32[0]), "1" (llr.w32[1]) ); -#else /* Big endian */ - __ASM volatile ("smlsld %0, %1, %2, %3" : "=r" (llr.w32[1]), "=r" (llr.w32[0]): "r" (op1), "r" (op2) , "0" (llr.w32[1]), "1" (llr.w32[0]) ); -#endif - - return(llr.w64); -} - -__STATIC_FORCEINLINE uint64_t __SMLSLDX (uint32_t op1, uint32_t op2, uint64_t acc) -{ - union llreg_u{ - uint32_t w32[2]; - uint64_t w64; - } llr; - llr.w64 = acc; - -#ifndef __ARMEB__ /* Little endian */ - __ASM volatile ("smlsldx %0, %1, %2, %3" : "=r" (llr.w32[0]), "=r" (llr.w32[1]): "r" (op1), "r" (op2) , "0" (llr.w32[0]), "1" (llr.w32[1]) ); -#else /* Big endian */ - __ASM volatile ("smlsldx %0, %1, %2, %3" : "=r" (llr.w32[1]), "=r" (llr.w32[0]): "r" (op1), "r" (op2) , "0" (llr.w32[1]), "1" (llr.w32[0]) ); -#endif - - return(llr.w64); -} - -__STATIC_FORCEINLINE uint32_t __SEL (uint32_t op1, uint32_t op2) -{ - uint32_t result; - - __ASM volatile ("sel %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); - return(result); -} - -__STATIC_FORCEINLINE int32_t __QADD( int32_t op1, int32_t op2) -{ - int32_t result; - - __ASM volatile ("qadd %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); - return(result); -} - -__STATIC_FORCEINLINE int32_t __QSUB( int32_t op1, int32_t op2) -{ - int32_t result; - - __ASM volatile ("qsub %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); - return(result); -} - -#if 0 -#define __PKHBT(ARG1,ARG2,ARG3) \ -({ \ - uint32_t __RES, __ARG1 = (ARG1), __ARG2 = (ARG2); \ - __ASM ("pkhbt %0, %1, %2, lsl %3" : "=r" (__RES) : "r" (__ARG1), "r" (__ARG2), "I" (ARG3) ); \ - __RES; \ - }) - -#define __PKHTB(ARG1,ARG2,ARG3) \ -({ \ - uint32_t __RES, __ARG1 = (ARG1), __ARG2 = (ARG2); \ - if (ARG3 == 0) \ - __ASM ("pkhtb %0, %1, %2" : "=r" (__RES) : "r" (__ARG1), "r" (__ARG2) ); \ - else \ - __ASM ("pkhtb %0, %1, %2, asr %3" : "=r" (__RES) : "r" (__ARG1), "r" (__ARG2), "I" (ARG3) ); \ - __RES; \ - }) -#endif - -#define __PKHBT(ARG1,ARG2,ARG3) ( ((((uint32_t)(ARG1)) ) & 0x0000FFFFUL) | \ - ((((uint32_t)(ARG2)) << (ARG3)) & 0xFFFF0000UL) ) - -#define __PKHTB(ARG1,ARG2,ARG3) ( ((((uint32_t)(ARG1)) ) & 0xFFFF0000UL) | \ - ((((uint32_t)(ARG2)) >> (ARG3)) & 0x0000FFFFUL) ) - -__STATIC_FORCEINLINE int32_t __SMMLA (int32_t op1, int32_t op2, int32_t op3) -{ - int32_t result; - - __ASM volatile ("smmla %0, %1, %2, %3" : "=r" (result): "r" (op1), "r" (op2), "r" (op3) ); - return(result); -} - -#endif /* (__ARM_FEATURE_DSP == 1) */ -/*@} end of group CMSIS_SIMD_intrinsics */ - - -#pragma GCC diagnostic pop - -#endif /* __CMSIS_GCC_H */ diff --git a/bsp/essemi/es32f0271/libraries/CMSIS/Include/cmsis_iccarm.h b/bsp/essemi/es32f0271/libraries/CMSIS/Include/cmsis_iccarm.h deleted file mode 100644 index edcaee3d4a..0000000000 --- a/bsp/essemi/es32f0271/libraries/CMSIS/Include/cmsis_iccarm.h +++ /dev/null @@ -1,913 +0,0 @@ -/**************************************************************************//** - * @file cmsis_iccarm.h - * @brief CMSIS compiler ICCARM (IAR Compiler for Arm) header file - * @version V5.0.5 - * @date 10. January 2018 - ******************************************************************************/ - -//------------------------------------------------------------------------------ -// -// Copyright (c) 2017-2018 IAR Systems -// -// Licensed under the Apache License, Version 2.0 (the "License") -// you may not use this file except in compliance with the License. -// You may obtain a copy of the License at -// http://www.apache.org/licenses/LICENSE-2.0 -// -// Unless required by applicable law or agreed to in writing, software -// distributed under the License is distributed on an "AS IS" BASIS, -// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. -// See the License for the specific language governing permissions and -// limitations under the License. -// -//------------------------------------------------------------------------------ - - -#ifndef __CMSIS_ICCARM_H__ -#define __CMSIS_ICCARM_H__ - -#ifndef __ICCARM__ - #error This file should only be compiled by ICCARM -#endif - -#pragma system_include - -#define __IAR_FT _Pragma("inline=forced") __intrinsic - -#if (__VER__ >= 8000000) - #define __ICCARM_V8 1 -#else - #define __ICCARM_V8 0 -#endif - -#ifndef __ALIGNED - #if __ICCARM_V8 - #define __ALIGNED(x) __attribute__((aligned(x))) - #elif (__VER__ >= 7080000) - /* Needs IAR language extensions */ - #define __ALIGNED(x) __attribute__((aligned(x))) - #else - #warning No compiler specific solution for __ALIGNED.__ALIGNED is ignored. - #define __ALIGNED(x) - #endif -#endif - - -/* Define compiler macros for CPU architecture, used in CMSIS 5. - */ -#if __ARM_ARCH_6M__ || __ARM_ARCH_7M__ || __ARM_ARCH_7EM__ || __ARM_ARCH_8M_BASE__ || __ARM_ARCH_8M_MAIN__ -/* Macros already defined */ -#else - #if defined(__ARM8M_MAINLINE__) || defined(__ARM8EM_MAINLINE__) - #define __ARM_ARCH_8M_MAIN__ 1 - #elif defined(__ARM8M_BASELINE__) - #define __ARM_ARCH_8M_BASE__ 1 - #elif defined(__ARM_ARCH_PROFILE) && __ARM_ARCH_PROFILE == 'M' - #if __ARM_ARCH == 6 - #define __ARM_ARCH_6M__ 1 - #elif __ARM_ARCH == 7 - #if __ARM_FEATURE_DSP - #define __ARM_ARCH_7EM__ 1 - #else - #define __ARM_ARCH_7M__ 1 - #endif - #endif /* __ARM_ARCH */ - #endif /* __ARM_ARCH_PROFILE == 'M' */ -#endif - -/* Alternativ core deduction for older ICCARM's */ -#if !defined(__ARM_ARCH_6M__) && !defined(__ARM_ARCH_7M__) && !defined(__ARM_ARCH_7EM__) && \ - !defined(__ARM_ARCH_8M_BASE__) && !defined(__ARM_ARCH_8M_MAIN__) - #if defined(__ARM6M__) && (__CORE__ == __ARM6M__) - #define __ARM_ARCH_6M__ 1 - #elif defined(__ARM7M__) && (__CORE__ == __ARM7M__) - #define __ARM_ARCH_7M__ 1 - #elif defined(__ARM7EM__) && (__CORE__ == __ARM7EM__) - #define __ARM_ARCH_7EM__ 1 - #elif defined(__ARM8M_BASELINE__) && (__CORE == __ARM8M_BASELINE__) - #define __ARM_ARCH_8M_BASE__ 1 - #elif defined(__ARM8M_MAINLINE__) && (__CORE == __ARM8M_MAINLINE__) - #define __ARM_ARCH_8M_MAIN__ 1 - #elif defined(__ARM8EM_MAINLINE__) && (__CORE == __ARM8EM_MAINLINE__) - #define __ARM_ARCH_8M_MAIN__ 1 - #else - #error "Unknown target." - #endif -#endif - - - -#if defined(__ARM_ARCH_6M__) && __ARM_ARCH_6M__==1 - #define __IAR_M0_FAMILY 1 -#elif defined(__ARM_ARCH_8M_BASE__) && __ARM_ARCH_8M_BASE__==1 - #define __IAR_M0_FAMILY 1 -#else - #define __IAR_M0_FAMILY 0 -#endif - - -#ifndef __ASM - #define __ASM __asm -#endif - -#ifndef __INLINE - #define __INLINE inline -#endif - -#ifndef __NO_RETURN - #if __ICCARM_V8 - #define __NO_RETURN __attribute__((__noreturn__)) - #else - #define __NO_RETURN _Pragma("object_attribute=__noreturn") - #endif -#endif - -#ifndef __PACKED - #if __ICCARM_V8 - #define __PACKED __attribute__((packed, aligned(1))) - #else - /* Needs IAR language extensions */ - #define __PACKED __packed - #endif -#endif - -#ifndef __PACKED_STRUCT - #if __ICCARM_V8 - #define __PACKED_STRUCT struct __attribute__((packed, aligned(1))) - #else - /* Needs IAR language extensions */ - #define __PACKED_STRUCT __packed struct - #endif -#endif - -#ifndef __PACKED_UNION - #if __ICCARM_V8 - #define __PACKED_UNION union __attribute__((packed, aligned(1))) - #else - /* Needs IAR language extensions */ - #define __PACKED_UNION __packed union - #endif -#endif - -#ifndef __RESTRICT - #define __RESTRICT restrict -#endif - -#ifndef __STATIC_INLINE - #define __STATIC_INLINE static inline -#endif - -#ifndef __FORCEINLINE - #define __FORCEINLINE _Pragma("inline=forced") -#endif - -#ifndef __STATIC_FORCEINLINE - #define __STATIC_FORCEINLINE __FORCEINLINE __STATIC_INLINE -#endif - -#ifndef __UNALIGNED_UINT16_READ -#pragma language=save -#pragma language=extended -__IAR_FT uint16_t __iar_uint16_read(void const *ptr) -{ - return *(__packed uint16_t*)(ptr); -} -#pragma language=restore -#define __UNALIGNED_UINT16_READ(PTR) __iar_uint16_read(PTR) -#endif - - -#ifndef __UNALIGNED_UINT16_WRITE -#pragma language=save -#pragma language=extended -__IAR_FT void __iar_uint16_write(void const *ptr, uint16_t val) -{ - *(__packed uint16_t*)(ptr) = val;; -} -#pragma language=restore -#define __UNALIGNED_UINT16_WRITE(PTR,VAL) __iar_uint16_write(PTR,VAL) -#endif - -#ifndef __UNALIGNED_UINT32_READ -#pragma language=save -#pragma language=extended -__IAR_FT uint32_t __iar_uint32_read(void const *ptr) -{ - return *(__packed uint32_t*)(ptr); -} -#pragma language=restore -#define __UNALIGNED_UINT32_READ(PTR) __iar_uint32_read(PTR) -#endif - -#ifndef __UNALIGNED_UINT32_WRITE -#pragma language=save -#pragma language=extended -__IAR_FT void __iar_uint32_write(void const *ptr, uint32_t val) -{ - *(__packed uint32_t*)(ptr) = val;; -} -#pragma language=restore -#define __UNALIGNED_UINT32_WRITE(PTR,VAL) __iar_uint32_write(PTR,VAL) -#endif - -#ifndef __UNALIGNED_UINT32 /* deprecated */ -#pragma language=save -#pragma language=extended -__packed struct __iar_u32 { uint32_t v; }; -#pragma language=restore -#define __UNALIGNED_UINT32(PTR) (((struct __iar_u32 *)(PTR))->v) -#endif - -#ifndef __USED - #if __ICCARM_V8 - #define __USED __attribute__((used)) - #else - #define __USED _Pragma("__root") - #endif -#endif - -#ifndef __WEAK - #if __ICCARM_V8 - #define __WEAK __attribute__((weak)) - #else - #define __WEAK _Pragma("__weak") - #endif -#endif - - -#ifndef __ICCARM_INTRINSICS_VERSION__ - #define __ICCARM_INTRINSICS_VERSION__ 0 -#endif - -#if __ICCARM_INTRINSICS_VERSION__ == 2 - - #if defined(__CLZ) - #undef __CLZ - #endif - #if defined(__REVSH) - #undef __REVSH - #endif - #if defined(__RBIT) - #undef __RBIT - #endif - #if defined(__SSAT) - #undef __SSAT - #endif - #if defined(__USAT) - #undef __USAT - #endif - - #include "iccarm_builtin.h" - - #define __disable_fault_irq __iar_builtin_disable_fiq - #define __disable_irq __iar_builtin_disable_interrupt - #define __enable_fault_irq __iar_builtin_enable_fiq - #define __enable_irq __iar_builtin_enable_interrupt - #define __arm_rsr __iar_builtin_rsr - #define __arm_wsr __iar_builtin_wsr - - - #define __get_APSR() (__arm_rsr("APSR")) - #define __get_BASEPRI() (__arm_rsr("BASEPRI")) - #define __get_CONTROL() (__arm_rsr("CONTROL")) - #define __get_FAULTMASK() (__arm_rsr("FAULTMASK")) - - #if ((defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)) && \ - (defined (__FPU_USED ) && (__FPU_USED == 1U)) ) - #define __get_FPSCR() (__arm_rsr("FPSCR")) - #define __set_FPSCR(VALUE) (__arm_wsr("FPSCR", (VALUE))) - #else - #define __get_FPSCR() ( 0 ) - #define __set_FPSCR(VALUE) ((void)VALUE) - #endif - - #define __get_IPSR() (__arm_rsr("IPSR")) - #define __get_MSP() (__arm_rsr("MSP")) - #if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \ - (!defined (__ARM_FEATURE_CMSE) || (__ARM_FEATURE_CMSE < 3))) - // without main extensions, the non-secure MSPLIM is RAZ/WI - #define __get_MSPLIM() (0U) - #else - #define __get_MSPLIM() (__arm_rsr("MSPLIM")) - #endif - #define __get_PRIMASK() (__arm_rsr("PRIMASK")) - #define __get_PSP() (__arm_rsr("PSP")) - - #if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \ - (!defined (__ARM_FEATURE_CMSE) || (__ARM_FEATURE_CMSE < 3))) - // without main extensions, the non-secure PSPLIM is RAZ/WI - #define __get_PSPLIM() (0U) - #else - #define __get_PSPLIM() (__arm_rsr("PSPLIM")) - #endif - - #define __get_xPSR() (__arm_rsr("xPSR")) - - #define __set_BASEPRI(VALUE) (__arm_wsr("BASEPRI", (VALUE))) - #define __set_BASEPRI_MAX(VALUE) (__arm_wsr("BASEPRI_MAX", (VALUE))) - #define __set_CONTROL(VALUE) (__arm_wsr("CONTROL", (VALUE))) - #define __set_FAULTMASK(VALUE) (__arm_wsr("FAULTMASK", (VALUE))) - #define __set_MSP(VALUE) (__arm_wsr("MSP", (VALUE))) - - #if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \ - (!defined (__ARM_FEATURE_CMSE) || (__ARM_FEATURE_CMSE < 3))) - // without main extensions, the non-secure MSPLIM is RAZ/WI - #define __set_MSPLIM(VALUE) ((void)(VALUE)) - #else - #define __set_MSPLIM(VALUE) (__arm_wsr("MSPLIM", (VALUE))) - #endif - #define __set_PRIMASK(VALUE) (__arm_wsr("PRIMASK", (VALUE))) - #define __set_PSP(VALUE) (__arm_wsr("PSP", (VALUE))) - #if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \ - (!defined (__ARM_FEATURE_CMSE) || (__ARM_FEATURE_CMSE < 3))) - // without main extensions, the non-secure PSPLIM is RAZ/WI - #define __set_PSPLIM(VALUE) ((void)(VALUE)) - #else - #define __set_PSPLIM(VALUE) (__arm_wsr("PSPLIM", (VALUE))) - #endif - - #define __TZ_get_CONTROL_NS() (__arm_rsr("CONTROL_NS")) - #define __TZ_set_CONTROL_NS(VALUE) (__arm_wsr("CONTROL_NS", (VALUE))) - #define __TZ_get_PSP_NS() (__arm_rsr("PSP_NS")) - #define __TZ_set_PSP_NS(VALUE) (__arm_wsr("PSP_NS", (VALUE))) - #define __TZ_get_MSP_NS() (__arm_rsr("MSP_NS")) - #define __TZ_set_MSP_NS(VALUE) (__arm_wsr("MSP_NS", (VALUE))) - #define __TZ_get_SP_NS() (__arm_rsr("SP_NS")) - #define __TZ_set_SP_NS(VALUE) (__arm_wsr("SP_NS", (VALUE))) - #define __TZ_get_PRIMASK_NS() (__arm_rsr("PRIMASK_NS")) - #define __TZ_set_PRIMASK_NS(VALUE) (__arm_wsr("PRIMASK_NS", (VALUE))) - #define __TZ_get_BASEPRI_NS() (__arm_rsr("BASEPRI_NS")) - #define __TZ_set_BASEPRI_NS(VALUE) (__arm_wsr("BASEPRI_NS", (VALUE))) - #define __TZ_get_FAULTMASK_NS() (__arm_rsr("FAULTMASK_NS")) - #define __TZ_set_FAULTMASK_NS(VALUE)(__arm_wsr("FAULTMASK_NS", (VALUE))) - #define __TZ_get_PSPLIM_NS() (__arm_rsr("PSPLIM_NS")) - #define __TZ_set_PSPLIM_NS(VALUE) (__arm_wsr("PSPLIM_NS", (VALUE))) - #define __TZ_get_MSPLIM_NS() (__arm_rsr("MSPLIM_NS")) - #define __TZ_set_MSPLIM_NS(VALUE) (__arm_wsr("MSPLIM_NS", (VALUE))) - - #define __NOP __iar_builtin_no_operation - - #define __CLZ __iar_builtin_CLZ - #define __CLREX __iar_builtin_CLREX - - #define __DMB __iar_builtin_DMB - #define __DSB __iar_builtin_DSB - #define __ISB __iar_builtin_ISB - - #define __LDREXB __iar_builtin_LDREXB - #define __LDREXH __iar_builtin_LDREXH - #define __LDREXW __iar_builtin_LDREX - - #define __RBIT __iar_builtin_RBIT - #define __REV __iar_builtin_REV - #define __REV16 __iar_builtin_REV16 - - __IAR_FT int16_t __REVSH(int16_t val) - { - return (int16_t) __iar_builtin_REVSH(val); - } - - #define __ROR __iar_builtin_ROR - #define __RRX __iar_builtin_RRX - - #define __SEV __iar_builtin_SEV - - #if !__IAR_M0_FAMILY - #define __SSAT __iar_builtin_SSAT - #endif - - #define __STREXB __iar_builtin_STREXB - #define __STREXH __iar_builtin_STREXH - #define __STREXW __iar_builtin_STREX - - #if !__IAR_M0_FAMILY - #define __USAT __iar_builtin_USAT - #endif - - #define __WFE __iar_builtin_WFE - #define __WFI __iar_builtin_WFI - - #if __ARM_MEDIA__ - #define __SADD8 __iar_builtin_SADD8 - #define __QADD8 __iar_builtin_QADD8 - #define __SHADD8 __iar_builtin_SHADD8 - #define __UADD8 __iar_builtin_UADD8 - #define __UQADD8 __iar_builtin_UQADD8 - #define __UHADD8 __iar_builtin_UHADD8 - #define __SSUB8 __iar_builtin_SSUB8 - #define __QSUB8 __iar_builtin_QSUB8 - #define __SHSUB8 __iar_builtin_SHSUB8 - #define __USUB8 __iar_builtin_USUB8 - #define __UQSUB8 __iar_builtin_UQSUB8 - #define __UHSUB8 __iar_builtin_UHSUB8 - #define __SADD16 __iar_builtin_SADD16 - #define __QADD16 __iar_builtin_QADD16 - #define __SHADD16 __iar_builtin_SHADD16 - #define __UADD16 __iar_builtin_UADD16 - #define __UQADD16 __iar_builtin_UQADD16 - #define __UHADD16 __iar_builtin_UHADD16 - #define __SSUB16 __iar_builtin_SSUB16 - #define __QSUB16 __iar_builtin_QSUB16 - #define __SHSUB16 __iar_builtin_SHSUB16 - #define __USUB16 __iar_builtin_USUB16 - #define __UQSUB16 __iar_builtin_UQSUB16 - #define __UHSUB16 __iar_builtin_UHSUB16 - #define __SASX __iar_builtin_SASX - #define __QASX __iar_builtin_QASX - #define __SHASX __iar_builtin_SHASX - #define __UASX __iar_builtin_UASX - #define __UQASX __iar_builtin_UQASX - #define __UHASX __iar_builtin_UHASX - #define __SSAX __iar_builtin_SSAX - #define __QSAX __iar_builtin_QSAX - #define __SHSAX __iar_builtin_SHSAX - #define __USAX __iar_builtin_USAX - #define __UQSAX __iar_builtin_UQSAX - #define __UHSAX __iar_builtin_UHSAX - #define __USAD8 __iar_builtin_USAD8 - #define __USADA8 __iar_builtin_USADA8 - #define __SSAT16 __iar_builtin_SSAT16 - #define __USAT16 __iar_builtin_USAT16 - #define __UXTB16 __iar_builtin_UXTB16 - #define __UXTAB16 __iar_builtin_UXTAB16 - #define __SXTB16 __iar_builtin_SXTB16 - #define __SXTAB16 __iar_builtin_SXTAB16 - #define __SMUAD __iar_builtin_SMUAD - #define __SMUADX __iar_builtin_SMUADX - #define __SMMLA __iar_builtin_SMMLA - #define __SMLAD __iar_builtin_SMLAD - #define __SMLADX __iar_builtin_SMLADX - #define __SMLALD __iar_builtin_SMLALD - #define __SMLALDX __iar_builtin_SMLALDX - #define __SMUSD __iar_builtin_SMUSD - #define __SMUSDX __iar_builtin_SMUSDX - #define __SMLSD __iar_builtin_SMLSD - #define __SMLSDX __iar_builtin_SMLSDX - #define __SMLSLD __iar_builtin_SMLSLD - #define __SMLSLDX __iar_builtin_SMLSLDX - #define __SEL __iar_builtin_SEL - #define __QADD __iar_builtin_QADD - #define __QSUB __iar_builtin_QSUB - #define __PKHBT __iar_builtin_PKHBT - #define __PKHTB __iar_builtin_PKHTB - #endif - -#else /* __ICCARM_INTRINSICS_VERSION__ == 2 */ - - #if __IAR_M0_FAMILY - /* Avoid clash between intrinsics.h and arm_math.h when compiling for Cortex-M0. */ - #define __CLZ __cmsis_iar_clz_not_active - #define __SSAT __cmsis_iar_ssat_not_active - #define __USAT __cmsis_iar_usat_not_active - #define __RBIT __cmsis_iar_rbit_not_active - #define __get_APSR __cmsis_iar_get_APSR_not_active - #endif - - - #if (!((defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)) && \ - (defined (__FPU_USED ) && (__FPU_USED == 1U)) )) - #define __get_FPSCR __cmsis_iar_get_FPSR_not_active - #define __set_FPSCR __cmsis_iar_set_FPSR_not_active - #endif - - #ifdef __INTRINSICS_INCLUDED - #error intrinsics.h is already included previously! - #endif - - #include - - #if __IAR_M0_FAMILY - /* Avoid clash between intrinsics.h and arm_math.h when compiling for Cortex-M0. */ - #undef __CLZ - #undef __SSAT - #undef __USAT - #undef __RBIT - #undef __get_APSR - - __STATIC_INLINE uint8_t __CLZ(uint32_t data) - { - if (data == 0U) { return 32U; } - - uint32_t count = 0U; - uint32_t mask = 0x80000000U; - - while ((data & mask) == 0U) - { - count += 1U; - mask = mask >> 1U; - } - return count; - } - - __STATIC_INLINE uint32_t __RBIT(uint32_t v) - { - uint8_t sc = 31U; - uint32_t r = v; - for (v >>= 1U; v; v >>= 1U) - { - r <<= 1U; - r |= v & 1U; - sc--; - } - return (r << sc); - } - - __STATIC_INLINE uint32_t __get_APSR(void) - { - uint32_t res; - __asm("MRS %0,APSR" : "=r" (res)); - return res; - } - - #endif - - #if (!((defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)) && \ - (defined (__FPU_USED ) && (__FPU_USED == 1U)) )) - #undef __get_FPSCR - #undef __set_FPSCR - #define __get_FPSCR() (0) - #define __set_FPSCR(VALUE) ((void)VALUE) - #endif - - #pragma diag_suppress=Pe940 - #pragma diag_suppress=Pe177 - - #define __enable_irq __enable_interrupt - #define __disable_irq __disable_interrupt - #define __NOP __no_operation - - #define __get_xPSR __get_PSR - - #if (!defined(__ARM_ARCH_6M__) || __ARM_ARCH_6M__==0) - - __IAR_FT uint32_t __LDREXW(uint32_t volatile *ptr) - { - return __LDREX((unsigned long *)ptr); - } - - __IAR_FT uint32_t __STREXW(uint32_t value, uint32_t volatile *ptr) - { - return __STREX(value, (unsigned long *)ptr); - } - #endif - - - /* __CORTEX_M is defined in core_cm0.h, core_cm3.h and core_cm4.h. */ - #if (__CORTEX_M >= 0x03) - - __IAR_FT uint32_t __RRX(uint32_t value) - { - uint32_t result; - __ASM("RRX %0, %1" : "=r"(result) : "r" (value) : "cc"); - return(result); - } - - __IAR_FT void __set_BASEPRI_MAX(uint32_t value) - { - __asm volatile("MSR BASEPRI_MAX,%0"::"r" (value)); - } - - - #define __enable_fault_irq __enable_fiq - #define __disable_fault_irq __disable_fiq - - - #endif /* (__CORTEX_M >= 0x03) */ - - __IAR_FT uint32_t __ROR(uint32_t op1, uint32_t op2) - { - return (op1 >> op2) | (op1 << ((sizeof(op1)*8)-op2)); - } - - #if ((defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \ - (defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1)) ) - - __IAR_FT uint32_t __get_MSPLIM(void) - { - uint32_t res; - #if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \ - (!defined (__ARM_FEATURE_CMSE ) || (__ARM_FEATURE_CMSE < 3))) - // without main extensions, the non-secure MSPLIM is RAZ/WI - res = 0U; - #else - __asm volatile("MRS %0,MSPLIM" : "=r" (res)); - #endif - return res; - } - - __IAR_FT void __set_MSPLIM(uint32_t value) - { - #if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \ - (!defined (__ARM_FEATURE_CMSE ) || (__ARM_FEATURE_CMSE < 3))) - // without main extensions, the non-secure MSPLIM is RAZ/WI - (void)value; - #else - __asm volatile("MSR MSPLIM,%0" :: "r" (value)); - #endif - } - - __IAR_FT uint32_t __get_PSPLIM(void) - { - uint32_t res; - #if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \ - (!defined (__ARM_FEATURE_CMSE ) || (__ARM_FEATURE_CMSE < 3))) - // without main extensions, the non-secure PSPLIM is RAZ/WI - res = 0U; - #else - __asm volatile("MRS %0,PSPLIM" : "=r" (res)); - #endif - return res; - } - - __IAR_FT void __set_PSPLIM(uint32_t value) - { - #if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \ - (!defined (__ARM_FEATURE_CMSE ) || (__ARM_FEATURE_CMSE < 3))) - // without main extensions, the non-secure PSPLIM is RAZ/WI - (void)value; - #else - __asm volatile("MSR PSPLIM,%0" :: "r" (value)); - #endif - } - - __IAR_FT uint32_t __TZ_get_CONTROL_NS(void) - { - uint32_t res; - __asm volatile("MRS %0,CONTROL_NS" : "=r" (res)); - return res; - } - - __IAR_FT void __TZ_set_CONTROL_NS(uint32_t value) - { - __asm volatile("MSR CONTROL_NS,%0" :: "r" (value)); - } - - __IAR_FT uint32_t __TZ_get_PSP_NS(void) - { - uint32_t res; - __asm volatile("MRS %0,PSP_NS" : "=r" (res)); - return res; - } - - __IAR_FT void __TZ_set_PSP_NS(uint32_t value) - { - __asm volatile("MSR PSP_NS,%0" :: "r" (value)); - } - - __IAR_FT uint32_t __TZ_get_MSP_NS(void) - { - uint32_t res; - __asm volatile("MRS %0,MSP_NS" : "=r" (res)); - return res; - } - - __IAR_FT void __TZ_set_MSP_NS(uint32_t value) - { - __asm volatile("MSR MSP_NS,%0" :: "r" (value)); - } - - __IAR_FT uint32_t __TZ_get_SP_NS(void) - { - uint32_t res; - __asm volatile("MRS %0,SP_NS" : "=r" (res)); - return res; - } - __IAR_FT void __TZ_set_SP_NS(uint32_t value) - { - __asm volatile("MSR SP_NS,%0" :: "r" (value)); - } - - __IAR_FT uint32_t __TZ_get_PRIMASK_NS(void) - { - uint32_t res; - __asm volatile("MRS %0,PRIMASK_NS" : "=r" (res)); - return res; - } - - __IAR_FT void __TZ_set_PRIMASK_NS(uint32_t value) - { - __asm volatile("MSR PRIMASK_NS,%0" :: "r" (value)); - } - - __IAR_FT uint32_t __TZ_get_BASEPRI_NS(void) - { - uint32_t res; - __asm volatile("MRS %0,BASEPRI_NS" : "=r" (res)); - return res; - } - - __IAR_FT void __TZ_set_BASEPRI_NS(uint32_t value) - { - __asm volatile("MSR BASEPRI_NS,%0" :: "r" (value)); - } - - __IAR_FT uint32_t __TZ_get_FAULTMASK_NS(void) - { - uint32_t res; - __asm volatile("MRS %0,FAULTMASK_NS" : "=r" (res)); - return res; - } - - __IAR_FT void __TZ_set_FAULTMASK_NS(uint32_t value) - { - __asm volatile("MSR FAULTMASK_NS,%0" :: "r" (value)); - } - - __IAR_FT uint32_t __TZ_get_PSPLIM_NS(void) - { - uint32_t res; - __asm volatile("MRS %0,PSPLIM_NS" : "=r" (res)); - return res; - } - __IAR_FT void __TZ_set_PSPLIM_NS(uint32_t value) - { - __asm volatile("MSR PSPLIM_NS,%0" :: "r" (value)); - } - - __IAR_FT uint32_t __TZ_get_MSPLIM_NS(void) - { - uint32_t res; - __asm volatile("MRS %0,MSPLIM_NS" : "=r" (res)); - return res; - } - - __IAR_FT void __TZ_set_MSPLIM_NS(uint32_t value) - { - __asm volatile("MSR MSPLIM_NS,%0" :: "r" (value)); - } - - #endif /* __ARM_ARCH_8M_MAIN__ or __ARM_ARCH_8M_BASE__ */ - -#endif /* __ICCARM_INTRINSICS_VERSION__ == 2 */ - -#define __BKPT(value) __asm volatile ("BKPT %0" : : "i"(value)) - -#if __IAR_M0_FAMILY - __STATIC_INLINE int32_t __SSAT(int32_t val, uint32_t sat) - { - if ((sat >= 1U) && (sat <= 32U)) - { - const int32_t max = (int32_t)((1U << (sat - 1U)) - 1U); - const int32_t min = -1 - max ; - if (val > max) - { - return max; - } - else if (val < min) - { - return min; - } - } - return val; - } - - __STATIC_INLINE uint32_t __USAT(int32_t val, uint32_t sat) - { - if (sat <= 31U) - { - const uint32_t max = ((1U << sat) - 1U); - if (val > (int32_t)max) - { - return max; - } - else if (val < 0) - { - return 0U; - } - } - return (uint32_t)val; - } -#endif - -#if (__CORTEX_M >= 0x03) /* __CORTEX_M is defined in core_cm0.h, core_cm3.h and core_cm4.h. */ - - __IAR_FT uint8_t __LDRBT(volatile uint8_t *addr) - { - uint32_t res; - __ASM("LDRBT %0, [%1]" : "=r" (res) : "r" (addr) : "memory"); - return ((uint8_t)res); - } - - __IAR_FT uint16_t __LDRHT(volatile uint16_t *addr) - { - uint32_t res; - __ASM("LDRHT %0, [%1]" : "=r" (res) : "r" (addr) : "memory"); - return ((uint16_t)res); - } - - __IAR_FT uint32_t __LDRT(volatile uint32_t *addr) - { - uint32_t res; - __ASM("LDRT %0, [%1]" : "=r" (res) : "r" (addr) : "memory"); - return res; - } - - __IAR_FT void __STRBT(uint8_t value, volatile uint8_t *addr) - { - __ASM("STRBT %1, [%0]" : : "r" (addr), "r" ((uint32_t)value) : "memory"); - } - - __IAR_FT void __STRHT(uint16_t value, volatile uint16_t *addr) - { - __ASM("STRHT %1, [%0]" : : "r" (addr), "r" ((uint32_t)value) : "memory"); - } - - __IAR_FT void __STRT(uint32_t value, volatile uint32_t *addr) - { - __ASM("STRT %1, [%0]" : : "r" (addr), "r" (value) : "memory"); - } - -#endif /* (__CORTEX_M >= 0x03) */ - -#if ((defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \ - (defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1)) ) - - - __IAR_FT uint8_t __LDAB(volatile uint8_t *ptr) - { - uint32_t res; - __ASM volatile ("LDAB %0, [%1]" : "=r" (res) : "r" (*ptr) : "memory"); - return ((uint8_t)res); - } - - __IAR_FT uint16_t __LDAH(volatile uint16_t *ptr) - { - uint32_t res; - __ASM volatile ("LDAH %0, [%1]" : "=r" (res) : "r" (*ptr) : "memory"); - return ((uint16_t)res); - } - - __IAR_FT uint32_t __LDA(volatile uint32_t *ptr) - { - uint32_t res; - __ASM volatile ("LDA %0, [%1]" : "=r" (res) : "r" (*ptr) : "memory"); - return res; - } - - __IAR_FT void __STLB(uint8_t value, volatile uint8_t *ptr) - { - __ASM volatile ("STLB %1, [%0]" :: "r" (*ptr), "r" (value) : "memory"); - } - - __IAR_FT void __STLH(uint16_t value, volatile uint16_t *ptr) - { - __ASM volatile ("STLH %1, [%0]" :: "r" (*ptr), "r" (value) : "memory"); - } - - __IAR_FT void __STL(uint32_t value, volatile uint32_t *ptr) - { - __ASM volatile ("STL %1, [%0]" :: "r" (*ptr), "r" (value) : "memory"); - } - - __IAR_FT uint8_t __LDAEXB(volatile uint8_t *ptr) - { - uint32_t res; - __ASM volatile ("LDAEXB %0, [%1]" : "=r" (res) : "r" (*ptr) : "memory"); - return ((uint8_t)res); - } - - __IAR_FT uint16_t __LDAEXH(volatile uint16_t *ptr) - { - uint32_t res; - __ASM volatile ("LDAEXH %0, [%1]" : "=r" (res) : "r" (*ptr) : "memory"); - return ((uint16_t)res); - } - - __IAR_FT uint32_t __LDAEX(volatile uint32_t *ptr) - { - uint32_t res; - __ASM volatile ("LDAEX %0, [%1]" : "=r" (res) : "r" (*ptr) : "memory"); - return res; - } - - __IAR_FT uint32_t __STLEXB(uint8_t value, volatile uint8_t *ptr) - { - uint32_t res; - __ASM volatile ("STLEXB %0, %2, [%1]" : "=r" (res) : "r" (*ptr), "r" (value) : "memory"); - return res; - } - - __IAR_FT uint32_t __STLEXH(uint16_t value, volatile uint16_t *ptr) - { - uint32_t res; - __ASM volatile ("STLEXH %0, %2, [%1]" : "=r" (res) : "r" (*ptr), "r" (value) : "memory"); - return res; - } - - __IAR_FT uint32_t __STLEX(uint32_t value, volatile uint32_t *ptr) - { - uint32_t res; - __ASM volatile ("STLEX %0, %2, [%1]" : "=r" (res) : "r" (*ptr), "r" (value) : "memory"); - return res; - } - -#endif /* __ARM_ARCH_8M_MAIN__ or __ARM_ARCH_8M_BASE__ */ - -#undef __IAR_FT -#undef __IAR_M0_FAMILY -#undef __ICCARM_V8 - -#pragma diag_default=Pe940 -#pragma diag_default=Pe177 - -#endif /* __CMSIS_ICCARM_H__ */ diff --git a/bsp/essemi/es32f0271/libraries/CMSIS/Include/cmsis_version.h b/bsp/essemi/es32f0271/libraries/CMSIS/Include/cmsis_version.h deleted file mode 100644 index 660f612aa3..0000000000 --- a/bsp/essemi/es32f0271/libraries/CMSIS/Include/cmsis_version.h +++ /dev/null @@ -1,39 +0,0 @@ -/**************************************************************************//** - * @file cmsis_version.h - * @brief CMSIS Core(M) Version definitions - * @version V5.0.2 - * @date 19. April 2017 - ******************************************************************************/ -/* - * Copyright (c) 2009-2017 ARM Limited. All rights reserved. - * - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed under the Apache License, Version 2.0 (the License); you may - * not use this file except in compliance with the License. - * You may obtain a copy of the License at - * - * www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an AS IS BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - */ - -#if defined ( __ICCARM__ ) - #pragma system_include /* treat file as system include file for MISRA check */ -#elif defined (__clang__) - #pragma clang system_header /* treat file as system include file */ -#endif - -#ifndef __CMSIS_VERSION_H -#define __CMSIS_VERSION_H - -/* CMSIS Version definitions */ -#define __CM_CMSIS_VERSION_MAIN ( 5U) /*!< [31:16] CMSIS Core(M) main version */ -#define __CM_CMSIS_VERSION_SUB ( 1U) /*!< [15:0] CMSIS Core(M) sub version */ -#define __CM_CMSIS_VERSION ((__CM_CMSIS_VERSION_MAIN << 16U) | \ - __CM_CMSIS_VERSION_SUB ) /*!< CMSIS Core(M) version number */ -#endif diff --git a/bsp/essemi/es32f0271/libraries/CMSIS/Include/core_armv8mbl.h b/bsp/essemi/es32f0271/libraries/CMSIS/Include/core_armv8mbl.h deleted file mode 100644 index 47a39893ac..0000000000 --- a/bsp/essemi/es32f0271/libraries/CMSIS/Include/core_armv8mbl.h +++ /dev/null @@ -1,1896 +0,0 @@ -/**************************************************************************//** - * @file core_armv8mbl.h - * @brief CMSIS Armv8-M Baseline Core Peripheral Access Layer Header File - * @version V5.0.4 - * @date 10. January 2018 - ******************************************************************************/ -/* - * Copyright (c) 2009-2018 Arm Limited. All rights reserved. - * - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed under the Apache License, Version 2.0 (the License); you may - * not use this file except in compliance with the License. - * You may obtain a copy of the License at - * - * www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an AS IS BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - */ - -#if defined ( __ICCARM__ ) - #pragma system_include /* treat file as system include file for MISRA check */ -#elif defined (__clang__) - #pragma clang system_header /* treat file as system include file */ -#endif - -#ifndef __CORE_ARMV8MBL_H_GENERIC -#define __CORE_ARMV8MBL_H_GENERIC - -#include - -#ifdef __cplusplus - extern "C" { -#endif - -/** - \page CMSIS_MISRA_Exceptions MISRA-C:2004 Compliance Exceptions - CMSIS violates the following MISRA-C:2004 rules: - - \li Required Rule 8.5, object/function definition in header file.
- Function definitions in header files are used to allow 'inlining'. - - \li Required Rule 18.4, declaration of union type or object of union type: '{...}'.
- Unions are used for effective representation of core registers. - - \li Advisory Rule 19.7, Function-like macro defined.
- Function-like macros are used to allow more efficient code. - */ - - -/******************************************************************************* - * CMSIS definitions - ******************************************************************************/ -/** - \ingroup Cortex_ARMv8MBL - @{ - */ - -#include "cmsis_version.h" - -/* CMSIS definitions */ -#define __ARMv8MBL_CMSIS_VERSION_MAIN (__CM_CMSIS_VERSION_MAIN) /*!< \deprecated [31:16] CMSIS HAL main version */ -#define __ARMv8MBL_CMSIS_VERSION_SUB (__CM_CMSIS_VERSION_SUB) /*!< \deprecated [15:0] CMSIS HAL sub version */ -#define __ARMv8MBL_CMSIS_VERSION ((__ARMv8MBL_CMSIS_VERSION_MAIN << 16U) | \ - __ARMv8MBL_CMSIS_VERSION_SUB ) /*!< \deprecated CMSIS HAL version number */ - -#define __CORTEX_M ( 2U) /*!< Cortex-M Core */ - -/** __FPU_USED indicates whether an FPU is used or not. - This core does not support an FPU at all -*/ -#define __FPU_USED 0U - -#if defined ( __CC_ARM ) - #if defined __TARGET_FPU_VFP - #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" - #endif - -#elif defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) - #if defined __ARM_PCS_VFP - #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" - #endif - -#elif defined ( __GNUC__ ) - #if defined (__VFP_FP__) && !defined(__SOFTFP__) - #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" - #endif - -#elif defined ( __ICCARM__ ) - #if defined __ARMVFP__ - #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" - #endif - -#elif defined ( __TI_ARM__ ) - #if defined __TI_VFP_SUPPORT__ - #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" - #endif - -#elif defined ( __TASKING__ ) - #if defined __FPU_VFP__ - #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" - #endif - -#elif defined ( __CSMC__ ) - #if ( __CSMC__ & 0x400U) - #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" - #endif - -#endif - -#include "cmsis_compiler.h" /* CMSIS compiler specific defines */ - - -#ifdef __cplusplus -} -#endif - -#endif /* __CORE_ARMV8MBL_H_GENERIC */ - -#ifndef __CMSIS_GENERIC - -#ifndef __CORE_ARMV8MBL_H_DEPENDANT -#define __CORE_ARMV8MBL_H_DEPENDANT - -#ifdef __cplusplus - extern "C" { -#endif - -/* check device defines and use defaults */ -#if defined __CHECK_DEVICE_DEFINES - #ifndef __ARMv8MBL_REV - #define __ARMv8MBL_REV 0x0000U - #warning "__ARMv8MBL_REV not defined in device header file; using default!" - #endif - - #ifndef __FPU_PRESENT - #define __FPU_PRESENT 0U - #warning "__FPU_PRESENT not defined in device header file; using default!" - #endif - - #ifndef __MPU_PRESENT - #define __MPU_PRESENT 0U - #warning "__MPU_PRESENT not defined in device header file; using default!" - #endif - - #ifndef __SAUREGION_PRESENT - #define __SAUREGION_PRESENT 0U - #warning "__SAUREGION_PRESENT not defined in device header file; using default!" - #endif - - #ifndef __VTOR_PRESENT - #define __VTOR_PRESENT 0U - #warning "__VTOR_PRESENT not defined in device header file; using default!" - #endif - - #ifndef __NVIC_PRIO_BITS - #define __NVIC_PRIO_BITS 2U - #warning "__NVIC_PRIO_BITS not defined in device header file; using default!" - #endif - - #ifndef __Vendor_SysTickConfig - #define __Vendor_SysTickConfig 0U - #warning "__Vendor_SysTickConfig not defined in device header file; using default!" - #endif - - #ifndef __ETM_PRESENT - #define __ETM_PRESENT 0U - #warning "__ETM_PRESENT not defined in device header file; using default!" - #endif - - #ifndef __MTB_PRESENT - #define __MTB_PRESENT 0U - #warning "__MTB_PRESENT not defined in device header file; using default!" - #endif - -#endif - -/* IO definitions (access restrictions to peripheral registers) */ -/** - \defgroup CMSIS_glob_defs CMSIS Global Defines - - IO Type Qualifiers are used - \li to specify the access to peripheral variables. - \li for automatic generation of peripheral register debug information. -*/ -#ifdef __cplusplus - #define __I volatile /*!< Defines 'read only' permissions */ -#else - #define __I volatile const /*!< Defines 'read only' permissions */ -#endif -#define __O volatile /*!< Defines 'write only' permissions */ -#define __IO volatile /*!< Defines 'read / write' permissions */ - -/* following defines should be used for structure members */ -#define __IM volatile const /*! Defines 'read only' structure member permissions */ -#define __OM volatile /*! Defines 'write only' structure member permissions */ -#define __IOM volatile /*! Defines 'read / write' structure member permissions */ - -/*@} end of group ARMv8MBL */ - - - -/******************************************************************************* - * Register Abstraction - Core Register contain: - - Core Register - - Core NVIC Register - - Core SCB Register - - Core SysTick Register - - Core Debug Register - - Core MPU Register - - Core SAU Register - ******************************************************************************/ -/** - \defgroup CMSIS_core_register Defines and Type Definitions - \brief Type definitions and defines for Cortex-M processor based devices. -*/ - -/** - \ingroup CMSIS_core_register - \defgroup CMSIS_CORE Status and Control Registers - \brief Core Register type definitions. - @{ - */ - -/** - \brief Union type to access the Application Program Status Register (APSR). - */ -typedef union -{ - struct - { - uint32_t _reserved0:28; /*!< bit: 0..27 Reserved */ - uint32_t V:1; /*!< bit: 28 Overflow condition code flag */ - uint32_t C:1; /*!< bit: 29 Carry condition code flag */ - uint32_t Z:1; /*!< bit: 30 Zero condition code flag */ - uint32_t N:1; /*!< bit: 31 Negative condition code flag */ - } b; /*!< Structure used for bit access */ - uint32_t w; /*!< Type used for word access */ -} APSR_Type; - -/* APSR Register Definitions */ -#define APSR_N_Pos 31U /*!< APSR: N Position */ -#define APSR_N_Msk (1UL << APSR_N_Pos) /*!< APSR: N Mask */ - -#define APSR_Z_Pos 30U /*!< APSR: Z Position */ -#define APSR_Z_Msk (1UL << APSR_Z_Pos) /*!< APSR: Z Mask */ - -#define APSR_C_Pos 29U /*!< APSR: C Position */ -#define APSR_C_Msk (1UL << APSR_C_Pos) /*!< APSR: C Mask */ - -#define APSR_V_Pos 28U /*!< APSR: V Position */ -#define APSR_V_Msk (1UL << APSR_V_Pos) /*!< APSR: V Mask */ - - -/** - \brief Union type to access the Interrupt Program Status Register (IPSR). - */ -typedef union -{ - struct - { - uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */ - uint32_t _reserved0:23; /*!< bit: 9..31 Reserved */ - } b; /*!< Structure used for bit access */ - uint32_t w; /*!< Type used for word access */ -} IPSR_Type; - -/* IPSR Register Definitions */ -#define IPSR_ISR_Pos 0U /*!< IPSR: ISR Position */ -#define IPSR_ISR_Msk (0x1FFUL /*<< IPSR_ISR_Pos*/) /*!< IPSR: ISR Mask */ - - -/** - \brief Union type to access the Special-Purpose Program Status Registers (xPSR). - */ -typedef union -{ - struct - { - uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */ - uint32_t _reserved0:15; /*!< bit: 9..23 Reserved */ - uint32_t T:1; /*!< bit: 24 Thumb bit (read 0) */ - uint32_t _reserved1:3; /*!< bit: 25..27 Reserved */ - uint32_t V:1; /*!< bit: 28 Overflow condition code flag */ - uint32_t C:1; /*!< bit: 29 Carry condition code flag */ - uint32_t Z:1; /*!< bit: 30 Zero condition code flag */ - uint32_t N:1; /*!< bit: 31 Negative condition code flag */ - } b; /*!< Structure used for bit access */ - uint32_t w; /*!< Type used for word access */ -} xPSR_Type; - -/* xPSR Register Definitions */ -#define xPSR_N_Pos 31U /*!< xPSR: N Position */ -#define xPSR_N_Msk (1UL << xPSR_N_Pos) /*!< xPSR: N Mask */ - -#define xPSR_Z_Pos 30U /*!< xPSR: Z Position */ -#define xPSR_Z_Msk (1UL << xPSR_Z_Pos) /*!< xPSR: Z Mask */ - -#define xPSR_C_Pos 29U /*!< xPSR: C Position */ -#define xPSR_C_Msk (1UL << xPSR_C_Pos) /*!< xPSR: C Mask */ - -#define xPSR_V_Pos 28U /*!< xPSR: V Position */ -#define xPSR_V_Msk (1UL << xPSR_V_Pos) /*!< xPSR: V Mask */ - -#define xPSR_T_Pos 24U /*!< xPSR: T Position */ -#define xPSR_T_Msk (1UL << xPSR_T_Pos) /*!< xPSR: T Mask */ - -#define xPSR_ISR_Pos 0U /*!< xPSR: ISR Position */ -#define xPSR_ISR_Msk (0x1FFUL /*<< xPSR_ISR_Pos*/) /*!< xPSR: ISR Mask */ - - -/** - \brief Union type to access the Control Registers (CONTROL). - */ -typedef union -{ - struct - { - uint32_t nPRIV:1; /*!< bit: 0 Execution privilege in Thread mode */ - uint32_t SPSEL:1; /*!< bit: 1 Stack-pointer select */ - uint32_t _reserved1:30; /*!< bit: 2..31 Reserved */ - } b; /*!< Structure used for bit access */ - uint32_t w; /*!< Type used for word access */ -} CONTROL_Type; - -/* CONTROL Register Definitions */ -#define CONTROL_SPSEL_Pos 1U /*!< CONTROL: SPSEL Position */ -#define CONTROL_SPSEL_Msk (1UL << CONTROL_SPSEL_Pos) /*!< CONTROL: SPSEL Mask */ - -#define CONTROL_nPRIV_Pos 0U /*!< CONTROL: nPRIV Position */ -#define CONTROL_nPRIV_Msk (1UL /*<< CONTROL_nPRIV_Pos*/) /*!< CONTROL: nPRIV Mask */ - -/*@} end of group CMSIS_CORE */ - - -/** - \ingroup CMSIS_core_register - \defgroup CMSIS_NVIC Nested Vectored Interrupt Controller (NVIC) - \brief Type definitions for the NVIC Registers - @{ - */ - -/** - \brief Structure type to access the Nested Vectored Interrupt Controller (NVIC). - */ -typedef struct -{ - __IOM uint32_t ISER[16U]; /*!< Offset: 0x000 (R/W) Interrupt Set Enable Register */ - uint32_t RESERVED0[16U]; - __IOM uint32_t ICER[16U]; /*!< Offset: 0x080 (R/W) Interrupt Clear Enable Register */ - uint32_t RSERVED1[16U]; - __IOM uint32_t ISPR[16U]; /*!< Offset: 0x100 (R/W) Interrupt Set Pending Register */ - uint32_t RESERVED2[16U]; - __IOM uint32_t ICPR[16U]; /*!< Offset: 0x180 (R/W) Interrupt Clear Pending Register */ - uint32_t RESERVED3[16U]; - __IOM uint32_t IABR[16U]; /*!< Offset: 0x200 (R/W) Interrupt Active bit Register */ - uint32_t RESERVED4[16U]; - __IOM uint32_t ITNS[16U]; /*!< Offset: 0x280 (R/W) Interrupt Non-Secure State Register */ - uint32_t RESERVED5[16U]; - __IOM uint32_t IPR[124U]; /*!< Offset: 0x300 (R/W) Interrupt Priority Register */ -} NVIC_Type; - -/*@} end of group CMSIS_NVIC */ - - -/** - \ingroup CMSIS_core_register - \defgroup CMSIS_SCB System Control Block (SCB) - \brief Type definitions for the System Control Block Registers - @{ - */ - -/** - \brief Structure type to access the System Control Block (SCB). - */ -typedef struct -{ - __IM uint32_t CPUID; /*!< Offset: 0x000 (R/ ) CPUID Base Register */ - __IOM uint32_t ICSR; /*!< Offset: 0x004 (R/W) Interrupt Control and State Register */ -#if defined (__VTOR_PRESENT) && (__VTOR_PRESENT == 1U) - __IOM uint32_t VTOR; /*!< Offset: 0x008 (R/W) Vector Table Offset Register */ -#else - uint32_t RESERVED0; -#endif - __IOM uint32_t AIRCR; /*!< Offset: 0x00C (R/W) Application Interrupt and Reset Control Register */ - __IOM uint32_t SCR; /*!< Offset: 0x010 (R/W) System Control Register */ - __IOM uint32_t CCR; /*!< Offset: 0x014 (R/W) Configuration Control Register */ - uint32_t RESERVED1; - __IOM uint32_t SHPR[2U]; /*!< Offset: 0x01C (R/W) System Handlers Priority Registers. [0] is RESERVED */ - __IOM uint32_t SHCSR; /*!< Offset: 0x024 (R/W) System Handler Control and State Register */ -} SCB_Type; - -/* SCB CPUID Register Definitions */ -#define SCB_CPUID_IMPLEMENTER_Pos 24U /*!< SCB CPUID: IMPLEMENTER Position */ -#define SCB_CPUID_IMPLEMENTER_Msk (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos) /*!< SCB CPUID: IMPLEMENTER Mask */ - -#define SCB_CPUID_VARIANT_Pos 20U /*!< SCB CPUID: VARIANT Position */ -#define SCB_CPUID_VARIANT_Msk (0xFUL << SCB_CPUID_VARIANT_Pos) /*!< SCB CPUID: VARIANT Mask */ - -#define SCB_CPUID_ARCHITECTURE_Pos 16U /*!< SCB CPUID: ARCHITECTURE Position */ -#define SCB_CPUID_ARCHITECTURE_Msk (0xFUL << SCB_CPUID_ARCHITECTURE_Pos) /*!< SCB CPUID: ARCHITECTURE Mask */ - -#define SCB_CPUID_PARTNO_Pos 4U /*!< SCB CPUID: PARTNO Position */ -#define SCB_CPUID_PARTNO_Msk (0xFFFUL << SCB_CPUID_PARTNO_Pos) /*!< SCB CPUID: PARTNO Mask */ - -#define SCB_CPUID_REVISION_Pos 0U /*!< SCB CPUID: REVISION Position */ -#define SCB_CPUID_REVISION_Msk (0xFUL /*<< SCB_CPUID_REVISION_Pos*/) /*!< SCB CPUID: REVISION Mask */ - -/* SCB Interrupt Control State Register Definitions */ -#define SCB_ICSR_PENDNMISET_Pos 31U /*!< SCB ICSR: PENDNMISET Position */ -#define SCB_ICSR_PENDNMISET_Msk (1UL << SCB_ICSR_PENDNMISET_Pos) /*!< SCB ICSR: PENDNMISET Mask */ - -#define SCB_ICSR_PENDNMICLR_Pos 30U /*!< SCB ICSR: PENDNMICLR Position */ -#define SCB_ICSR_PENDNMICLR_Msk (1UL << SCB_ICSR_PENDNMICLR_Pos) /*!< SCB ICSR: PENDNMICLR Mask */ - -#define SCB_ICSR_PENDSVSET_Pos 28U /*!< SCB ICSR: PENDSVSET Position */ -#define SCB_ICSR_PENDSVSET_Msk (1UL << SCB_ICSR_PENDSVSET_Pos) /*!< SCB ICSR: PENDSVSET Mask */ - -#define SCB_ICSR_PENDSVCLR_Pos 27U /*!< SCB ICSR: PENDSVCLR Position */ -#define SCB_ICSR_PENDSVCLR_Msk (1UL << SCB_ICSR_PENDSVCLR_Pos) /*!< SCB ICSR: PENDSVCLR Mask */ - -#define SCB_ICSR_PENDSTSET_Pos 26U /*!< SCB ICSR: PENDSTSET Position */ -#define SCB_ICSR_PENDSTSET_Msk (1UL << SCB_ICSR_PENDSTSET_Pos) /*!< SCB ICSR: PENDSTSET Mask */ - -#define SCB_ICSR_PENDSTCLR_Pos 25U /*!< SCB ICSR: PENDSTCLR Position */ -#define SCB_ICSR_PENDSTCLR_Msk (1UL << SCB_ICSR_PENDSTCLR_Pos) /*!< SCB ICSR: PENDSTCLR Mask */ - -#define SCB_ICSR_STTNS_Pos 24U /*!< SCB ICSR: STTNS Position (Security Extension) */ -#define SCB_ICSR_STTNS_Msk (1UL << SCB_ICSR_STTNS_Pos) /*!< SCB ICSR: STTNS Mask (Security Extension) */ - -#define SCB_ICSR_ISRPREEMPT_Pos 23U /*!< SCB ICSR: ISRPREEMPT Position */ -#define SCB_ICSR_ISRPREEMPT_Msk (1UL << SCB_ICSR_ISRPREEMPT_Pos) /*!< SCB ICSR: ISRPREEMPT Mask */ - -#define SCB_ICSR_ISRPENDING_Pos 22U /*!< SCB ICSR: ISRPENDING Position */ -#define SCB_ICSR_ISRPENDING_Msk (1UL << SCB_ICSR_ISRPENDING_Pos) /*!< SCB ICSR: ISRPENDING Mask */ - -#define SCB_ICSR_VECTPENDING_Pos 12U /*!< SCB ICSR: VECTPENDING Position */ -#define SCB_ICSR_VECTPENDING_Msk (0x1FFUL << SCB_ICSR_VECTPENDING_Pos) /*!< SCB ICSR: VECTPENDING Mask */ - -#define SCB_ICSR_RETTOBASE_Pos 11U /*!< SCB ICSR: RETTOBASE Position */ -#define SCB_ICSR_RETTOBASE_Msk (1UL << SCB_ICSR_RETTOBASE_Pos) /*!< SCB ICSR: RETTOBASE Mask */ - -#define SCB_ICSR_VECTACTIVE_Pos 0U /*!< SCB ICSR: VECTACTIVE Position */ -#define SCB_ICSR_VECTACTIVE_Msk (0x1FFUL /*<< SCB_ICSR_VECTACTIVE_Pos*/) /*!< SCB ICSR: VECTACTIVE Mask */ - -#if defined (__VTOR_PRESENT) && (__VTOR_PRESENT == 1U) -/* SCB Vector Table Offset Register Definitions */ -#define SCB_VTOR_TBLOFF_Pos 7U /*!< SCB VTOR: TBLOFF Position */ -#define SCB_VTOR_TBLOFF_Msk (0x1FFFFFFUL << SCB_VTOR_TBLOFF_Pos) /*!< SCB VTOR: TBLOFF Mask */ -#endif - -/* SCB Application Interrupt and Reset Control Register Definitions */ -#define SCB_AIRCR_VECTKEY_Pos 16U /*!< SCB AIRCR: VECTKEY Position */ -#define SCB_AIRCR_VECTKEY_Msk (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos) /*!< SCB AIRCR: VECTKEY Mask */ - -#define SCB_AIRCR_VECTKEYSTAT_Pos 16U /*!< SCB AIRCR: VECTKEYSTAT Position */ -#define SCB_AIRCR_VECTKEYSTAT_Msk (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos) /*!< SCB AIRCR: VECTKEYSTAT Mask */ - -#define SCB_AIRCR_ENDIANESS_Pos 15U /*!< SCB AIRCR: ENDIANESS Position */ -#define SCB_AIRCR_ENDIANESS_Msk (1UL << SCB_AIRCR_ENDIANESS_Pos) /*!< SCB AIRCR: ENDIANESS Mask */ - -#define SCB_AIRCR_PRIS_Pos 14U /*!< SCB AIRCR: PRIS Position */ -#define SCB_AIRCR_PRIS_Msk (1UL << SCB_AIRCR_PRIS_Pos) /*!< SCB AIRCR: PRIS Mask */ - -#define SCB_AIRCR_BFHFNMINS_Pos 13U /*!< SCB AIRCR: BFHFNMINS Position */ -#define SCB_AIRCR_BFHFNMINS_Msk (1UL << SCB_AIRCR_BFHFNMINS_Pos) /*!< SCB AIRCR: BFHFNMINS Mask */ - -#define SCB_AIRCR_SYSRESETREQS_Pos 3U /*!< SCB AIRCR: SYSRESETREQS Position */ -#define SCB_AIRCR_SYSRESETREQS_Msk (1UL << SCB_AIRCR_SYSRESETREQS_Pos) /*!< SCB AIRCR: SYSRESETREQS Mask */ - -#define SCB_AIRCR_SYSRESETREQ_Pos 2U /*!< SCB AIRCR: SYSRESETREQ Position */ -#define SCB_AIRCR_SYSRESETREQ_Msk (1UL << SCB_AIRCR_SYSRESETREQ_Pos) /*!< SCB AIRCR: SYSRESETREQ Mask */ - -#define SCB_AIRCR_VECTCLRACTIVE_Pos 1U /*!< SCB AIRCR: VECTCLRACTIVE Position */ -#define SCB_AIRCR_VECTCLRACTIVE_Msk (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos) /*!< SCB AIRCR: VECTCLRACTIVE Mask */ - -/* SCB System Control Register Definitions */ -#define SCB_SCR_SEVONPEND_Pos 4U /*!< SCB SCR: SEVONPEND Position */ -#define SCB_SCR_SEVONPEND_Msk (1UL << SCB_SCR_SEVONPEND_Pos) /*!< SCB SCR: SEVONPEND Mask */ - -#define SCB_SCR_SLEEPDEEPS_Pos 3U /*!< SCB SCR: SLEEPDEEPS Position */ -#define SCB_SCR_SLEEPDEEPS_Msk (1UL << SCB_SCR_SLEEPDEEPS_Pos) /*!< SCB SCR: SLEEPDEEPS Mask */ - -#define SCB_SCR_SLEEPDEEP_Pos 2U /*!< SCB SCR: SLEEPDEEP Position */ -#define SCB_SCR_SLEEPDEEP_Msk (1UL << SCB_SCR_SLEEPDEEP_Pos) /*!< SCB SCR: SLEEPDEEP Mask */ - -#define SCB_SCR_SLEEPONEXIT_Pos 1U /*!< SCB SCR: SLEEPONEXIT Position */ -#define SCB_SCR_SLEEPONEXIT_Msk (1UL << SCB_SCR_SLEEPONEXIT_Pos) /*!< SCB SCR: SLEEPONEXIT Mask */ - -/* SCB Configuration Control Register Definitions */ -#define SCB_CCR_BP_Pos 18U /*!< SCB CCR: BP Position */ -#define SCB_CCR_BP_Msk (1UL << SCB_CCR_BP_Pos) /*!< SCB CCR: BP Mask */ - -#define SCB_CCR_IC_Pos 17U /*!< SCB CCR: IC Position */ -#define SCB_CCR_IC_Msk (1UL << SCB_CCR_IC_Pos) /*!< SCB CCR: IC Mask */ - -#define SCB_CCR_DC_Pos 16U /*!< SCB CCR: DC Position */ -#define SCB_CCR_DC_Msk (1UL << SCB_CCR_DC_Pos) /*!< SCB CCR: DC Mask */ - -#define SCB_CCR_STKOFHFNMIGN_Pos 10U /*!< SCB CCR: STKOFHFNMIGN Position */ -#define SCB_CCR_STKOFHFNMIGN_Msk (1UL << SCB_CCR_STKOFHFNMIGN_Pos) /*!< SCB CCR: STKOFHFNMIGN Mask */ - -#define SCB_CCR_BFHFNMIGN_Pos 8U /*!< SCB CCR: BFHFNMIGN Position */ -#define SCB_CCR_BFHFNMIGN_Msk (1UL << SCB_CCR_BFHFNMIGN_Pos) /*!< SCB CCR: BFHFNMIGN Mask */ - -#define SCB_CCR_DIV_0_TRP_Pos 4U /*!< SCB CCR: DIV_0_TRP Position */ -#define SCB_CCR_DIV_0_TRP_Msk (1UL << SCB_CCR_DIV_0_TRP_Pos) /*!< SCB CCR: DIV_0_TRP Mask */ - -#define SCB_CCR_UNALIGN_TRP_Pos 3U /*!< SCB CCR: UNALIGN_TRP Position */ -#define SCB_CCR_UNALIGN_TRP_Msk (1UL << SCB_CCR_UNALIGN_TRP_Pos) /*!< SCB CCR: UNALIGN_TRP Mask */ - -#define SCB_CCR_USERSETMPEND_Pos 1U /*!< SCB CCR: USERSETMPEND Position */ -#define SCB_CCR_USERSETMPEND_Msk (1UL << SCB_CCR_USERSETMPEND_Pos) /*!< SCB CCR: USERSETMPEND Mask */ - -/* SCB System Handler Control and State Register Definitions */ -#define SCB_SHCSR_HARDFAULTPENDED_Pos 21U /*!< SCB SHCSR: HARDFAULTPENDED Position */ -#define SCB_SHCSR_HARDFAULTPENDED_Msk (1UL << SCB_SHCSR_HARDFAULTPENDED_Pos) /*!< SCB SHCSR: HARDFAULTPENDED Mask */ - -#define SCB_SHCSR_SVCALLPENDED_Pos 15U /*!< SCB SHCSR: SVCALLPENDED Position */ -#define SCB_SHCSR_SVCALLPENDED_Msk (1UL << SCB_SHCSR_SVCALLPENDED_Pos) /*!< SCB SHCSR: SVCALLPENDED Mask */ - -#define SCB_SHCSR_SYSTICKACT_Pos 11U /*!< SCB SHCSR: SYSTICKACT Position */ -#define SCB_SHCSR_SYSTICKACT_Msk (1UL << SCB_SHCSR_SYSTICKACT_Pos) /*!< SCB SHCSR: SYSTICKACT Mask */ - -#define SCB_SHCSR_PENDSVACT_Pos 10U /*!< SCB SHCSR: PENDSVACT Position */ -#define SCB_SHCSR_PENDSVACT_Msk (1UL << SCB_SHCSR_PENDSVACT_Pos) /*!< SCB SHCSR: PENDSVACT Mask */ - -#define SCB_SHCSR_SVCALLACT_Pos 7U /*!< SCB SHCSR: SVCALLACT Position */ -#define SCB_SHCSR_SVCALLACT_Msk (1UL << SCB_SHCSR_SVCALLACT_Pos) /*!< SCB SHCSR: SVCALLACT Mask */ - -#define SCB_SHCSR_NMIACT_Pos 5U /*!< SCB SHCSR: NMIACT Position */ -#define SCB_SHCSR_NMIACT_Msk (1UL << SCB_SHCSR_NMIACT_Pos) /*!< SCB SHCSR: NMIACT Mask */ - -#define SCB_SHCSR_HARDFAULTACT_Pos 2U /*!< SCB SHCSR: HARDFAULTACT Position */ -#define SCB_SHCSR_HARDFAULTACT_Msk (1UL << SCB_SHCSR_HARDFAULTACT_Pos) /*!< SCB SHCSR: HARDFAULTACT Mask */ - -/*@} end of group CMSIS_SCB */ - - -/** - \ingroup CMSIS_core_register - \defgroup CMSIS_SysTick System Tick Timer (SysTick) - \brief Type definitions for the System Timer Registers. - @{ - */ - -/** - \brief Structure type to access the System Timer (SysTick). - */ -typedef struct -{ - __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) SysTick Control and Status Register */ - __IOM uint32_t LOAD; /*!< Offset: 0x004 (R/W) SysTick Reload Value Register */ - __IOM uint32_t VAL; /*!< Offset: 0x008 (R/W) SysTick Current Value Register */ - __IM uint32_t CALIB; /*!< Offset: 0x00C (R/ ) SysTick Calibration Register */ -} SysTick_Type; - -/* SysTick Control / Status Register Definitions */ -#define SysTick_CTRL_COUNTFLAG_Pos 16U /*!< SysTick CTRL: COUNTFLAG Position */ -#define SysTick_CTRL_COUNTFLAG_Msk (1UL << SysTick_CTRL_COUNTFLAG_Pos) /*!< SysTick CTRL: COUNTFLAG Mask */ - -#define SysTick_CTRL_CLKSOURCE_Pos 2U /*!< SysTick CTRL: CLKSOURCE Position */ -#define SysTick_CTRL_CLKSOURCE_Msk (1UL << SysTick_CTRL_CLKSOURCE_Pos) /*!< SysTick CTRL: CLKSOURCE Mask */ - -#define SysTick_CTRL_TICKINT_Pos 1U /*!< SysTick CTRL: TICKINT Position */ -#define SysTick_CTRL_TICKINT_Msk (1UL << SysTick_CTRL_TICKINT_Pos) /*!< SysTick CTRL: TICKINT Mask */ - -#define SysTick_CTRL_ENABLE_Pos 0U /*!< SysTick CTRL: ENABLE Position */ -#define SysTick_CTRL_ENABLE_Msk (1UL /*<< SysTick_CTRL_ENABLE_Pos*/) /*!< SysTick CTRL: ENABLE Mask */ - -/* SysTick Reload Register Definitions */ -#define SysTick_LOAD_RELOAD_Pos 0U /*!< SysTick LOAD: RELOAD Position */ -#define SysTick_LOAD_RELOAD_Msk (0xFFFFFFUL /*<< SysTick_LOAD_RELOAD_Pos*/) /*!< SysTick LOAD: RELOAD Mask */ - -/* SysTick Current Register Definitions */ -#define SysTick_VAL_CURRENT_Pos 0U /*!< SysTick VAL: CURRENT Position */ -#define SysTick_VAL_CURRENT_Msk (0xFFFFFFUL /*<< SysTick_VAL_CURRENT_Pos*/) /*!< SysTick VAL: CURRENT Mask */ - -/* SysTick Calibration Register Definitions */ -#define SysTick_CALIB_NOREF_Pos 31U /*!< SysTick CALIB: NOREF Position */ -#define SysTick_CALIB_NOREF_Msk (1UL << SysTick_CALIB_NOREF_Pos) /*!< SysTick CALIB: NOREF Mask */ - -#define SysTick_CALIB_SKEW_Pos 30U /*!< SysTick CALIB: SKEW Position */ -#define SysTick_CALIB_SKEW_Msk (1UL << SysTick_CALIB_SKEW_Pos) /*!< SysTick CALIB: SKEW Mask */ - -#define SysTick_CALIB_TENMS_Pos 0U /*!< SysTick CALIB: TENMS Position */ -#define SysTick_CALIB_TENMS_Msk (0xFFFFFFUL /*<< SysTick_CALIB_TENMS_Pos*/) /*!< SysTick CALIB: TENMS Mask */ - -/*@} end of group CMSIS_SysTick */ - - -/** - \ingroup CMSIS_core_register - \defgroup CMSIS_DWT Data Watchpoint and Trace (DWT) - \brief Type definitions for the Data Watchpoint and Trace (DWT) - @{ - */ - -/** - \brief Structure type to access the Data Watchpoint and Trace Register (DWT). - */ -typedef struct -{ - __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) Control Register */ - uint32_t RESERVED0[6U]; - __IM uint32_t PCSR; /*!< Offset: 0x01C (R/ ) Program Counter Sample Register */ - __IOM uint32_t COMP0; /*!< Offset: 0x020 (R/W) Comparator Register 0 */ - uint32_t RESERVED1[1U]; - __IOM uint32_t FUNCTION0; /*!< Offset: 0x028 (R/W) Function Register 0 */ - uint32_t RESERVED2[1U]; - __IOM uint32_t COMP1; /*!< Offset: 0x030 (R/W) Comparator Register 1 */ - uint32_t RESERVED3[1U]; - __IOM uint32_t FUNCTION1; /*!< Offset: 0x038 (R/W) Function Register 1 */ - uint32_t RESERVED4[1U]; - __IOM uint32_t COMP2; /*!< Offset: 0x040 (R/W) Comparator Register 2 */ - uint32_t RESERVED5[1U]; - __IOM uint32_t FUNCTION2; /*!< Offset: 0x048 (R/W) Function Register 2 */ - uint32_t RESERVED6[1U]; - __IOM uint32_t COMP3; /*!< Offset: 0x050 (R/W) Comparator Register 3 */ - uint32_t RESERVED7[1U]; - __IOM uint32_t FUNCTION3; /*!< Offset: 0x058 (R/W) Function Register 3 */ - uint32_t RESERVED8[1U]; - __IOM uint32_t COMP4; /*!< Offset: 0x060 (R/W) Comparator Register 4 */ - uint32_t RESERVED9[1U]; - __IOM uint32_t FUNCTION4; /*!< Offset: 0x068 (R/W) Function Register 4 */ - uint32_t RESERVED10[1U]; - __IOM uint32_t COMP5; /*!< Offset: 0x070 (R/W) Comparator Register 5 */ - uint32_t RESERVED11[1U]; - __IOM uint32_t FUNCTION5; /*!< Offset: 0x078 (R/W) Function Register 5 */ - uint32_t RESERVED12[1U]; - __IOM uint32_t COMP6; /*!< Offset: 0x080 (R/W) Comparator Register 6 */ - uint32_t RESERVED13[1U]; - __IOM uint32_t FUNCTION6; /*!< Offset: 0x088 (R/W) Function Register 6 */ - uint32_t RESERVED14[1U]; - __IOM uint32_t COMP7; /*!< Offset: 0x090 (R/W) Comparator Register 7 */ - uint32_t RESERVED15[1U]; - __IOM uint32_t FUNCTION7; /*!< Offset: 0x098 (R/W) Function Register 7 */ - uint32_t RESERVED16[1U]; - __IOM uint32_t COMP8; /*!< Offset: 0x0A0 (R/W) Comparator Register 8 */ - uint32_t RESERVED17[1U]; - __IOM uint32_t FUNCTION8; /*!< Offset: 0x0A8 (R/W) Function Register 8 */ - uint32_t RESERVED18[1U]; - __IOM uint32_t COMP9; /*!< Offset: 0x0B0 (R/W) Comparator Register 9 */ - uint32_t RESERVED19[1U]; - __IOM uint32_t FUNCTION9; /*!< Offset: 0x0B8 (R/W) Function Register 9 */ - uint32_t RESERVED20[1U]; - __IOM uint32_t COMP10; /*!< Offset: 0x0C0 (R/W) Comparator Register 10 */ - uint32_t RESERVED21[1U]; - __IOM uint32_t FUNCTION10; /*!< Offset: 0x0C8 (R/W) Function Register 10 */ - uint32_t RESERVED22[1U]; - __IOM uint32_t COMP11; /*!< Offset: 0x0D0 (R/W) Comparator Register 11 */ - uint32_t RESERVED23[1U]; - __IOM uint32_t FUNCTION11; /*!< Offset: 0x0D8 (R/W) Function Register 11 */ - uint32_t RESERVED24[1U]; - __IOM uint32_t COMP12; /*!< Offset: 0x0E0 (R/W) Comparator Register 12 */ - uint32_t RESERVED25[1U]; - __IOM uint32_t FUNCTION12; /*!< Offset: 0x0E8 (R/W) Function Register 12 */ - uint32_t RESERVED26[1U]; - __IOM uint32_t COMP13; /*!< Offset: 0x0F0 (R/W) Comparator Register 13 */ - uint32_t RESERVED27[1U]; - __IOM uint32_t FUNCTION13; /*!< Offset: 0x0F8 (R/W) Function Register 13 */ - uint32_t RESERVED28[1U]; - __IOM uint32_t COMP14; /*!< Offset: 0x100 (R/W) Comparator Register 14 */ - uint32_t RESERVED29[1U]; - __IOM uint32_t FUNCTION14; /*!< Offset: 0x108 (R/W) Function Register 14 */ - uint32_t RESERVED30[1U]; - __IOM uint32_t COMP15; /*!< Offset: 0x110 (R/W) Comparator Register 15 */ - uint32_t RESERVED31[1U]; - __IOM uint32_t FUNCTION15; /*!< Offset: 0x118 (R/W) Function Register 15 */ -} DWT_Type; - -/* DWT Control Register Definitions */ -#define DWT_CTRL_NUMCOMP_Pos 28U /*!< DWT CTRL: NUMCOMP Position */ -#define DWT_CTRL_NUMCOMP_Msk (0xFUL << DWT_CTRL_NUMCOMP_Pos) /*!< DWT CTRL: NUMCOMP Mask */ - -#define DWT_CTRL_NOTRCPKT_Pos 27U /*!< DWT CTRL: NOTRCPKT Position */ -#define DWT_CTRL_NOTRCPKT_Msk (0x1UL << DWT_CTRL_NOTRCPKT_Pos) /*!< DWT CTRL: NOTRCPKT Mask */ - -#define DWT_CTRL_NOEXTTRIG_Pos 26U /*!< DWT CTRL: NOEXTTRIG Position */ -#define DWT_CTRL_NOEXTTRIG_Msk (0x1UL << DWT_CTRL_NOEXTTRIG_Pos) /*!< DWT CTRL: NOEXTTRIG Mask */ - -#define DWT_CTRL_NOCYCCNT_Pos 25U /*!< DWT CTRL: NOCYCCNT Position */ -#define DWT_CTRL_NOCYCCNT_Msk (0x1UL << DWT_CTRL_NOCYCCNT_Pos) /*!< DWT CTRL: NOCYCCNT Mask */ - -#define DWT_CTRL_NOPRFCNT_Pos 24U /*!< DWT CTRL: NOPRFCNT Position */ -#define DWT_CTRL_NOPRFCNT_Msk (0x1UL << DWT_CTRL_NOPRFCNT_Pos) /*!< DWT CTRL: NOPRFCNT Mask */ - -/* DWT Comparator Function Register Definitions */ -#define DWT_FUNCTION_ID_Pos 27U /*!< DWT FUNCTION: ID Position */ -#define DWT_FUNCTION_ID_Msk (0x1FUL << DWT_FUNCTION_ID_Pos) /*!< DWT FUNCTION: ID Mask */ - -#define DWT_FUNCTION_MATCHED_Pos 24U /*!< DWT FUNCTION: MATCHED Position */ -#define DWT_FUNCTION_MATCHED_Msk (0x1UL << DWT_FUNCTION_MATCHED_Pos) /*!< DWT FUNCTION: MATCHED Mask */ - -#define DWT_FUNCTION_DATAVSIZE_Pos 10U /*!< DWT FUNCTION: DATAVSIZE Position */ -#define DWT_FUNCTION_DATAVSIZE_Msk (0x3UL << DWT_FUNCTION_DATAVSIZE_Pos) /*!< DWT FUNCTION: DATAVSIZE Mask */ - -#define DWT_FUNCTION_ACTION_Pos 4U /*!< DWT FUNCTION: ACTION Position */ -#define DWT_FUNCTION_ACTION_Msk (0x3UL << DWT_FUNCTION_ACTION_Pos) /*!< DWT FUNCTION: ACTION Mask */ - -#define DWT_FUNCTION_MATCH_Pos 0U /*!< DWT FUNCTION: MATCH Position */ -#define DWT_FUNCTION_MATCH_Msk (0xFUL /*<< DWT_FUNCTION_MATCH_Pos*/) /*!< DWT FUNCTION: MATCH Mask */ - -/*@}*/ /* end of group CMSIS_DWT */ - - -/** - \ingroup CMSIS_core_register - \defgroup CMSIS_TPI Trace Port Interface (TPI) - \brief Type definitions for the Trace Port Interface (TPI) - @{ - */ - -/** - \brief Structure type to access the Trace Port Interface Register (TPI). - */ -typedef struct -{ - __IOM uint32_t SSPSR; /*!< Offset: 0x000 (R/ ) Supported Parallel Port Size Register */ - __IOM uint32_t CSPSR; /*!< Offset: 0x004 (R/W) Current Parallel Port Size Register */ - uint32_t RESERVED0[2U]; - __IOM uint32_t ACPR; /*!< Offset: 0x010 (R/W) Asynchronous Clock Prescaler Register */ - uint32_t RESERVED1[55U]; - __IOM uint32_t SPPR; /*!< Offset: 0x0F0 (R/W) Selected Pin Protocol Register */ - uint32_t RESERVED2[131U]; - __IM uint32_t FFSR; /*!< Offset: 0x300 (R/ ) Formatter and Flush Status Register */ - __IOM uint32_t FFCR; /*!< Offset: 0x304 (R/W) Formatter and Flush Control Register */ - __IM uint32_t FSCR; /*!< Offset: 0x308 (R/ ) Formatter Synchronization Counter Register */ - uint32_t RESERVED3[759U]; - __IM uint32_t TRIGGER; /*!< Offset: 0xEE8 (R/ ) TRIGGER */ - __IM uint32_t FIFO0; /*!< Offset: 0xEEC (R/ ) Integration ETM Data */ - __IM uint32_t ITATBCTR2; /*!< Offset: 0xEF0 (R/ ) ITATBCTR2 */ - uint32_t RESERVED4[1U]; - __IM uint32_t ITATBCTR0; /*!< Offset: 0xEF8 (R/ ) ITATBCTR0 */ - __IM uint32_t FIFO1; /*!< Offset: 0xEFC (R/ ) Integration ITM Data */ - __IOM uint32_t ITCTRL; /*!< Offset: 0xF00 (R/W) Integration Mode Control */ - uint32_t RESERVED5[39U]; - __IOM uint32_t CLAIMSET; /*!< Offset: 0xFA0 (R/W) Claim tag set */ - __IOM uint32_t CLAIMCLR; /*!< Offset: 0xFA4 (R/W) Claim tag clear */ - uint32_t RESERVED7[8U]; - __IM uint32_t DEVID; /*!< Offset: 0xFC8 (R/ ) TPIU_DEVID */ - __IM uint32_t DEVTYPE; /*!< Offset: 0xFCC (R/ ) TPIU_DEVTYPE */ -} TPI_Type; - -/* TPI Asynchronous Clock Prescaler Register Definitions */ -#define TPI_ACPR_PRESCALER_Pos 0U /*!< TPI ACPR: PRESCALER Position */ -#define TPI_ACPR_PRESCALER_Msk (0x1FFFUL /*<< TPI_ACPR_PRESCALER_Pos*/) /*!< TPI ACPR: PRESCALER Mask */ - -/* TPI Selected Pin Protocol Register Definitions */ -#define TPI_SPPR_TXMODE_Pos 0U /*!< TPI SPPR: TXMODE Position */ -#define TPI_SPPR_TXMODE_Msk (0x3UL /*<< TPI_SPPR_TXMODE_Pos*/) /*!< TPI SPPR: TXMODE Mask */ - -/* TPI Formatter and Flush Status Register Definitions */ -#define TPI_FFSR_FtNonStop_Pos 3U /*!< TPI FFSR: FtNonStop Position */ -#define TPI_FFSR_FtNonStop_Msk (0x1UL << TPI_FFSR_FtNonStop_Pos) /*!< TPI FFSR: FtNonStop Mask */ - -#define TPI_FFSR_TCPresent_Pos 2U /*!< TPI FFSR: TCPresent Position */ -#define TPI_FFSR_TCPresent_Msk (0x1UL << TPI_FFSR_TCPresent_Pos) /*!< TPI FFSR: TCPresent Mask */ - -#define TPI_FFSR_FtStopped_Pos 1U /*!< TPI FFSR: FtStopped Position */ -#define TPI_FFSR_FtStopped_Msk (0x1UL << TPI_FFSR_FtStopped_Pos) /*!< TPI FFSR: FtStopped Mask */ - -#define TPI_FFSR_FlInProg_Pos 0U /*!< TPI FFSR: FlInProg Position */ -#define TPI_FFSR_FlInProg_Msk (0x1UL /*<< TPI_FFSR_FlInProg_Pos*/) /*!< TPI FFSR: FlInProg Mask */ - -/* TPI Formatter and Flush Control Register Definitions */ -#define TPI_FFCR_TrigIn_Pos 8U /*!< TPI FFCR: TrigIn Position */ -#define TPI_FFCR_TrigIn_Msk (0x1UL << TPI_FFCR_TrigIn_Pos) /*!< TPI FFCR: TrigIn Mask */ - -#define TPI_FFCR_EnFCont_Pos 1U /*!< TPI FFCR: EnFCont Position */ -#define TPI_FFCR_EnFCont_Msk (0x1UL << TPI_FFCR_EnFCont_Pos) /*!< TPI FFCR: EnFCont Mask */ - -/* TPI TRIGGER Register Definitions */ -#define TPI_TRIGGER_TRIGGER_Pos 0U /*!< TPI TRIGGER: TRIGGER Position */ -#define TPI_TRIGGER_TRIGGER_Msk (0x1UL /*<< TPI_TRIGGER_TRIGGER_Pos*/) /*!< TPI TRIGGER: TRIGGER Mask */ - -/* TPI Integration ETM Data Register Definitions (FIFO0) */ -#define TPI_FIFO0_ITM_ATVALID_Pos 29U /*!< TPI FIFO0: ITM_ATVALID Position */ -#define TPI_FIFO0_ITM_ATVALID_Msk (0x3UL << TPI_FIFO0_ITM_ATVALID_Pos) /*!< TPI FIFO0: ITM_ATVALID Mask */ - -#define TPI_FIFO0_ITM_bytecount_Pos 27U /*!< TPI FIFO0: ITM_bytecount Position */ -#define TPI_FIFO0_ITM_bytecount_Msk (0x3UL << TPI_FIFO0_ITM_bytecount_Pos) /*!< TPI FIFO0: ITM_bytecount Mask */ - -#define TPI_FIFO0_ETM_ATVALID_Pos 26U /*!< TPI FIFO0: ETM_ATVALID Position */ -#define TPI_FIFO0_ETM_ATVALID_Msk (0x3UL << TPI_FIFO0_ETM_ATVALID_Pos) /*!< TPI FIFO0: ETM_ATVALID Mask */ - -#define TPI_FIFO0_ETM_bytecount_Pos 24U /*!< TPI FIFO0: ETM_bytecount Position */ -#define TPI_FIFO0_ETM_bytecount_Msk (0x3UL << TPI_FIFO0_ETM_bytecount_Pos) /*!< TPI FIFO0: ETM_bytecount Mask */ - -#define TPI_FIFO0_ETM2_Pos 16U /*!< TPI FIFO0: ETM2 Position */ -#define TPI_FIFO0_ETM2_Msk (0xFFUL << TPI_FIFO0_ETM2_Pos) /*!< TPI FIFO0: ETM2 Mask */ - -#define TPI_FIFO0_ETM1_Pos 8U /*!< TPI FIFO0: ETM1 Position */ -#define TPI_FIFO0_ETM1_Msk (0xFFUL << TPI_FIFO0_ETM1_Pos) /*!< TPI FIFO0: ETM1 Mask */ - -#define TPI_FIFO0_ETM0_Pos 0U /*!< TPI FIFO0: ETM0 Position */ -#define TPI_FIFO0_ETM0_Msk (0xFFUL /*<< TPI_FIFO0_ETM0_Pos*/) /*!< TPI FIFO0: ETM0 Mask */ - -/* TPI ITATBCTR2 Register Definitions */ -#define TPI_ITATBCTR2_ATREADY_Pos 0U /*!< TPI ITATBCTR2: ATREADY Position */ -#define TPI_ITATBCTR2_ATREADY_Msk (0x1UL /*<< TPI_ITATBCTR2_ATREADY_Pos*/) /*!< TPI ITATBCTR2: ATREADY Mask */ - -/* TPI Integration ITM Data Register Definitions (FIFO1) */ -#define TPI_FIFO1_ITM_ATVALID_Pos 29U /*!< TPI FIFO1: ITM_ATVALID Position */ -#define TPI_FIFO1_ITM_ATVALID_Msk (0x3UL << TPI_FIFO1_ITM_ATVALID_Pos) /*!< TPI FIFO1: ITM_ATVALID Mask */ - -#define TPI_FIFO1_ITM_bytecount_Pos 27U /*!< TPI FIFO1: ITM_bytecount Position */ -#define TPI_FIFO1_ITM_bytecount_Msk (0x3UL << TPI_FIFO1_ITM_bytecount_Pos) /*!< TPI FIFO1: ITM_bytecount Mask */ - -#define TPI_FIFO1_ETM_ATVALID_Pos 26U /*!< TPI FIFO1: ETM_ATVALID Position */ -#define TPI_FIFO1_ETM_ATVALID_Msk (0x3UL << TPI_FIFO1_ETM_ATVALID_Pos) /*!< TPI FIFO1: ETM_ATVALID Mask */ - -#define TPI_FIFO1_ETM_bytecount_Pos 24U /*!< TPI FIFO1: ETM_bytecount Position */ -#define TPI_FIFO1_ETM_bytecount_Msk (0x3UL << TPI_FIFO1_ETM_bytecount_Pos) /*!< TPI FIFO1: ETM_bytecount Mask */ - -#define TPI_FIFO1_ITM2_Pos 16U /*!< TPI FIFO1: ITM2 Position */ -#define TPI_FIFO1_ITM2_Msk (0xFFUL << TPI_FIFO1_ITM2_Pos) /*!< TPI FIFO1: ITM2 Mask */ - -#define TPI_FIFO1_ITM1_Pos 8U /*!< TPI FIFO1: ITM1 Position */ -#define TPI_FIFO1_ITM1_Msk (0xFFUL << TPI_FIFO1_ITM1_Pos) /*!< TPI FIFO1: ITM1 Mask */ - -#define TPI_FIFO1_ITM0_Pos 0U /*!< TPI FIFO1: ITM0 Position */ -#define TPI_FIFO1_ITM0_Msk (0xFFUL /*<< TPI_FIFO1_ITM0_Pos*/) /*!< TPI FIFO1: ITM0 Mask */ - -/* TPI ITATBCTR0 Register Definitions */ -#define TPI_ITATBCTR0_ATREADY_Pos 0U /*!< TPI ITATBCTR0: ATREADY Position */ -#define TPI_ITATBCTR0_ATREADY_Msk (0x1UL /*<< TPI_ITATBCTR0_ATREADY_Pos*/) /*!< TPI ITATBCTR0: ATREADY Mask */ - -/* TPI Integration Mode Control Register Definitions */ -#define TPI_ITCTRL_Mode_Pos 0U /*!< TPI ITCTRL: Mode Position */ -#define TPI_ITCTRL_Mode_Msk (0x1UL /*<< TPI_ITCTRL_Mode_Pos*/) /*!< TPI ITCTRL: Mode Mask */ - -/* TPI DEVID Register Definitions */ -#define TPI_DEVID_NRZVALID_Pos 11U /*!< TPI DEVID: NRZVALID Position */ -#define TPI_DEVID_NRZVALID_Msk (0x1UL << TPI_DEVID_NRZVALID_Pos) /*!< TPI DEVID: NRZVALID Mask */ - -#define TPI_DEVID_MANCVALID_Pos 10U /*!< TPI DEVID: MANCVALID Position */ -#define TPI_DEVID_MANCVALID_Msk (0x1UL << TPI_DEVID_MANCVALID_Pos) /*!< TPI DEVID: MANCVALID Mask */ - -#define TPI_DEVID_PTINVALID_Pos 9U /*!< TPI DEVID: PTINVALID Position */ -#define TPI_DEVID_PTINVALID_Msk (0x1UL << TPI_DEVID_PTINVALID_Pos) /*!< TPI DEVID: PTINVALID Mask */ - -#define TPI_DEVID_MinBufSz_Pos 6U /*!< TPI DEVID: MinBufSz Position */ -#define TPI_DEVID_MinBufSz_Msk (0x7UL << TPI_DEVID_MinBufSz_Pos) /*!< TPI DEVID: MinBufSz Mask */ - -#define TPI_DEVID_AsynClkIn_Pos 5U /*!< TPI DEVID: AsynClkIn Position */ -#define TPI_DEVID_AsynClkIn_Msk (0x1UL << TPI_DEVID_AsynClkIn_Pos) /*!< TPI DEVID: AsynClkIn Mask */ - -#define TPI_DEVID_NrTraceInput_Pos 0U /*!< TPI DEVID: NrTraceInput Position */ -#define TPI_DEVID_NrTraceInput_Msk (0x1FUL /*<< TPI_DEVID_NrTraceInput_Pos*/) /*!< TPI DEVID: NrTraceInput Mask */ - -/* TPI DEVTYPE Register Definitions */ -#define TPI_DEVTYPE_MajorType_Pos 4U /*!< TPI DEVTYPE: MajorType Position */ -#define TPI_DEVTYPE_MajorType_Msk (0xFUL << TPI_DEVTYPE_MajorType_Pos) /*!< TPI DEVTYPE: MajorType Mask */ - -#define TPI_DEVTYPE_SubType_Pos 0U /*!< TPI DEVTYPE: SubType Position */ -#define TPI_DEVTYPE_SubType_Msk (0xFUL /*<< TPI_DEVTYPE_SubType_Pos*/) /*!< TPI DEVTYPE: SubType Mask */ - -/*@}*/ /* end of group CMSIS_TPI */ - - -#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) -/** - \ingroup CMSIS_core_register - \defgroup CMSIS_MPU Memory Protection Unit (MPU) - \brief Type definitions for the Memory Protection Unit (MPU) - @{ - */ - -/** - \brief Structure type to access the Memory Protection Unit (MPU). - */ -typedef struct -{ - __IM uint32_t TYPE; /*!< Offset: 0x000 (R/ ) MPU Type Register */ - __IOM uint32_t CTRL; /*!< Offset: 0x004 (R/W) MPU Control Register */ - __IOM uint32_t RNR; /*!< Offset: 0x008 (R/W) MPU Region Number Register */ - __IOM uint32_t RBAR; /*!< Offset: 0x00C (R/W) MPU Region Base Address Register */ - __IOM uint32_t RLAR; /*!< Offset: 0x010 (R/W) MPU Region Limit Address Register */ - uint32_t RESERVED0[7U]; - union { - __IOM uint32_t MAIR[2]; - struct { - __IOM uint32_t MAIR0; /*!< Offset: 0x030 (R/W) MPU Memory Attribute Indirection Register 0 */ - __IOM uint32_t MAIR1; /*!< Offset: 0x034 (R/W) MPU Memory Attribute Indirection Register 1 */ - }; - }; -} MPU_Type; - -#define MPU_TYPE_RALIASES 1U - -/* MPU Type Register Definitions */ -#define MPU_TYPE_IREGION_Pos 16U /*!< MPU TYPE: IREGION Position */ -#define MPU_TYPE_IREGION_Msk (0xFFUL << MPU_TYPE_IREGION_Pos) /*!< MPU TYPE: IREGION Mask */ - -#define MPU_TYPE_DREGION_Pos 8U /*!< MPU TYPE: DREGION Position */ -#define MPU_TYPE_DREGION_Msk (0xFFUL << MPU_TYPE_DREGION_Pos) /*!< MPU TYPE: DREGION Mask */ - -#define MPU_TYPE_SEPARATE_Pos 0U /*!< MPU TYPE: SEPARATE Position */ -#define MPU_TYPE_SEPARATE_Msk (1UL /*<< MPU_TYPE_SEPARATE_Pos*/) /*!< MPU TYPE: SEPARATE Mask */ - -/* MPU Control Register Definitions */ -#define MPU_CTRL_PRIVDEFENA_Pos 2U /*!< MPU CTRL: PRIVDEFENA Position */ -#define MPU_CTRL_PRIVDEFENA_Msk (1UL << MPU_CTRL_PRIVDEFENA_Pos) /*!< MPU CTRL: PRIVDEFENA Mask */ - -#define MPU_CTRL_HFNMIENA_Pos 1U /*!< MPU CTRL: HFNMIENA Position */ -#define MPU_CTRL_HFNMIENA_Msk (1UL << MPU_CTRL_HFNMIENA_Pos) /*!< MPU CTRL: HFNMIENA Mask */ - -#define MPU_CTRL_ENABLE_Pos 0U /*!< MPU CTRL: ENABLE Position */ -#define MPU_CTRL_ENABLE_Msk (1UL /*<< MPU_CTRL_ENABLE_Pos*/) /*!< MPU CTRL: ENABLE Mask */ - -/* MPU Region Number Register Definitions */ -#define MPU_RNR_REGION_Pos 0U /*!< MPU RNR: REGION Position */ -#define MPU_RNR_REGION_Msk (0xFFUL /*<< MPU_RNR_REGION_Pos*/) /*!< MPU RNR: REGION Mask */ - -/* MPU Region Base Address Register Definitions */ -#define MPU_RBAR_BASE_Pos 5U /*!< MPU RBAR: BASE Position */ -#define MPU_RBAR_BASE_Msk (0x7FFFFFFUL << MPU_RBAR_BASE_Pos) /*!< MPU RBAR: BASE Mask */ - -#define MPU_RBAR_SH_Pos 3U /*!< MPU RBAR: SH Position */ -#define MPU_RBAR_SH_Msk (0x3UL << MPU_RBAR_SH_Pos) /*!< MPU RBAR: SH Mask */ - -#define MPU_RBAR_AP_Pos 1U /*!< MPU RBAR: AP Position */ -#define MPU_RBAR_AP_Msk (0x3UL << MPU_RBAR_AP_Pos) /*!< MPU RBAR: AP Mask */ - -#define MPU_RBAR_XN_Pos 0U /*!< MPU RBAR: XN Position */ -#define MPU_RBAR_XN_Msk (01UL /*<< MPU_RBAR_XN_Pos*/) /*!< MPU RBAR: XN Mask */ - -/* MPU Region Limit Address Register Definitions */ -#define MPU_RLAR_LIMIT_Pos 5U /*!< MPU RLAR: LIMIT Position */ -#define MPU_RLAR_LIMIT_Msk (0x7FFFFFFUL << MPU_RLAR_LIMIT_Pos) /*!< MPU RLAR: LIMIT Mask */ - -#define MPU_RLAR_AttrIndx_Pos 1U /*!< MPU RLAR: AttrIndx Position */ -#define MPU_RLAR_AttrIndx_Msk (0x7UL << MPU_RLAR_AttrIndx_Pos) /*!< MPU RLAR: AttrIndx Mask */ - -#define MPU_RLAR_EN_Pos 0U /*!< MPU RLAR: EN Position */ -#define MPU_RLAR_EN_Msk (1UL /*<< MPU_RLAR_EN_Pos*/) /*!< MPU RLAR: EN Mask */ - -/* MPU Memory Attribute Indirection Register 0 Definitions */ -#define MPU_MAIR0_Attr3_Pos 24U /*!< MPU MAIR0: Attr3 Position */ -#define MPU_MAIR0_Attr3_Msk (0xFFUL << MPU_MAIR0_Attr3_Pos) /*!< MPU MAIR0: Attr3 Mask */ - -#define MPU_MAIR0_Attr2_Pos 16U /*!< MPU MAIR0: Attr2 Position */ -#define MPU_MAIR0_Attr2_Msk (0xFFUL << MPU_MAIR0_Attr2_Pos) /*!< MPU MAIR0: Attr2 Mask */ - -#define MPU_MAIR0_Attr1_Pos 8U /*!< MPU MAIR0: Attr1 Position */ -#define MPU_MAIR0_Attr1_Msk (0xFFUL << MPU_MAIR0_Attr1_Pos) /*!< MPU MAIR0: Attr1 Mask */ - -#define MPU_MAIR0_Attr0_Pos 0U /*!< MPU MAIR0: Attr0 Position */ -#define MPU_MAIR0_Attr0_Msk (0xFFUL /*<< MPU_MAIR0_Attr0_Pos*/) /*!< MPU MAIR0: Attr0 Mask */ - -/* MPU Memory Attribute Indirection Register 1 Definitions */ -#define MPU_MAIR1_Attr7_Pos 24U /*!< MPU MAIR1: Attr7 Position */ -#define MPU_MAIR1_Attr7_Msk (0xFFUL << MPU_MAIR1_Attr7_Pos) /*!< MPU MAIR1: Attr7 Mask */ - -#define MPU_MAIR1_Attr6_Pos 16U /*!< MPU MAIR1: Attr6 Position */ -#define MPU_MAIR1_Attr6_Msk (0xFFUL << MPU_MAIR1_Attr6_Pos) /*!< MPU MAIR1: Attr6 Mask */ - -#define MPU_MAIR1_Attr5_Pos 8U /*!< MPU MAIR1: Attr5 Position */ -#define MPU_MAIR1_Attr5_Msk (0xFFUL << MPU_MAIR1_Attr5_Pos) /*!< MPU MAIR1: Attr5 Mask */ - -#define MPU_MAIR1_Attr4_Pos 0U /*!< MPU MAIR1: Attr4 Position */ -#define MPU_MAIR1_Attr4_Msk (0xFFUL /*<< MPU_MAIR1_Attr4_Pos*/) /*!< MPU MAIR1: Attr4 Mask */ - -/*@} end of group CMSIS_MPU */ -#endif - - -#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) -/** - \ingroup CMSIS_core_register - \defgroup CMSIS_SAU Security Attribution Unit (SAU) - \brief Type definitions for the Security Attribution Unit (SAU) - @{ - */ - -/** - \brief Structure type to access the Security Attribution Unit (SAU). - */ -typedef struct -{ - __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) SAU Control Register */ - __IM uint32_t TYPE; /*!< Offset: 0x004 (R/ ) SAU Type Register */ -#if defined (__SAUREGION_PRESENT) && (__SAUREGION_PRESENT == 1U) - __IOM uint32_t RNR; /*!< Offset: 0x008 (R/W) SAU Region Number Register */ - __IOM uint32_t RBAR; /*!< Offset: 0x00C (R/W) SAU Region Base Address Register */ - __IOM uint32_t RLAR; /*!< Offset: 0x010 (R/W) SAU Region Limit Address Register */ -#endif -} SAU_Type; - -/* SAU Control Register Definitions */ -#define SAU_CTRL_ALLNS_Pos 1U /*!< SAU CTRL: ALLNS Position */ -#define SAU_CTRL_ALLNS_Msk (1UL << SAU_CTRL_ALLNS_Pos) /*!< SAU CTRL: ALLNS Mask */ - -#define SAU_CTRL_ENABLE_Pos 0U /*!< SAU CTRL: ENABLE Position */ -#define SAU_CTRL_ENABLE_Msk (1UL /*<< SAU_CTRL_ENABLE_Pos*/) /*!< SAU CTRL: ENABLE Mask */ - -/* SAU Type Register Definitions */ -#define SAU_TYPE_SREGION_Pos 0U /*!< SAU TYPE: SREGION Position */ -#define SAU_TYPE_SREGION_Msk (0xFFUL /*<< SAU_TYPE_SREGION_Pos*/) /*!< SAU TYPE: SREGION Mask */ - -#if defined (__SAUREGION_PRESENT) && (__SAUREGION_PRESENT == 1U) -/* SAU Region Number Register Definitions */ -#define SAU_RNR_REGION_Pos 0U /*!< SAU RNR: REGION Position */ -#define SAU_RNR_REGION_Msk (0xFFUL /*<< SAU_RNR_REGION_Pos*/) /*!< SAU RNR: REGION Mask */ - -/* SAU Region Base Address Register Definitions */ -#define SAU_RBAR_BADDR_Pos 5U /*!< SAU RBAR: BADDR Position */ -#define SAU_RBAR_BADDR_Msk (0x7FFFFFFUL << SAU_RBAR_BADDR_Pos) /*!< SAU RBAR: BADDR Mask */ - -/* SAU Region Limit Address Register Definitions */ -#define SAU_RLAR_LADDR_Pos 5U /*!< SAU RLAR: LADDR Position */ -#define SAU_RLAR_LADDR_Msk (0x7FFFFFFUL << SAU_RLAR_LADDR_Pos) /*!< SAU RLAR: LADDR Mask */ - -#define SAU_RLAR_NSC_Pos 1U /*!< SAU RLAR: NSC Position */ -#define SAU_RLAR_NSC_Msk (1UL << SAU_RLAR_NSC_Pos) /*!< SAU RLAR: NSC Mask */ - -#define SAU_RLAR_ENABLE_Pos 0U /*!< SAU RLAR: ENABLE Position */ -#define SAU_RLAR_ENABLE_Msk (1UL /*<< SAU_RLAR_ENABLE_Pos*/) /*!< SAU RLAR: ENABLE Mask */ - -#endif /* defined (__SAUREGION_PRESENT) && (__SAUREGION_PRESENT == 1U) */ - -/*@} end of group CMSIS_SAU */ -#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */ - - -/** - \ingroup CMSIS_core_register - \defgroup CMSIS_CoreDebug Core Debug Registers (CoreDebug) - \brief Type definitions for the Core Debug Registers - @{ - */ - -/** - \brief Structure type to access the Core Debug Register (CoreDebug). - */ -typedef struct -{ - __IOM uint32_t DHCSR; /*!< Offset: 0x000 (R/W) Debug Halting Control and Status Register */ - __OM uint32_t DCRSR; /*!< Offset: 0x004 ( /W) Debug Core Register Selector Register */ - __IOM uint32_t DCRDR; /*!< Offset: 0x008 (R/W) Debug Core Register Data Register */ - __IOM uint32_t DEMCR; /*!< Offset: 0x00C (R/W) Debug Exception and Monitor Control Register */ - uint32_t RESERVED4[1U]; - __IOM uint32_t DAUTHCTRL; /*!< Offset: 0x014 (R/W) Debug Authentication Control Register */ - __IOM uint32_t DSCSR; /*!< Offset: 0x018 (R/W) Debug Security Control and Status Register */ -} CoreDebug_Type; - -/* Debug Halting Control and Status Register Definitions */ -#define CoreDebug_DHCSR_DBGKEY_Pos 16U /*!< CoreDebug DHCSR: DBGKEY Position */ -#define CoreDebug_DHCSR_DBGKEY_Msk (0xFFFFUL << CoreDebug_DHCSR_DBGKEY_Pos) /*!< CoreDebug DHCSR: DBGKEY Mask */ - -#define CoreDebug_DHCSR_S_RESTART_ST_Pos 26U /*!< CoreDebug DHCSR: S_RESTART_ST Position */ -#define CoreDebug_DHCSR_S_RESTART_ST_Msk (1UL << CoreDebug_DHCSR_S_RESTART_ST_Pos) /*!< CoreDebug DHCSR: S_RESTART_ST Mask */ - -#define CoreDebug_DHCSR_S_RESET_ST_Pos 25U /*!< CoreDebug DHCSR: S_RESET_ST Position */ -#define CoreDebug_DHCSR_S_RESET_ST_Msk (1UL << CoreDebug_DHCSR_S_RESET_ST_Pos) /*!< CoreDebug DHCSR: S_RESET_ST Mask */ - -#define CoreDebug_DHCSR_S_RETIRE_ST_Pos 24U /*!< CoreDebug DHCSR: S_RETIRE_ST Position */ -#define CoreDebug_DHCSR_S_RETIRE_ST_Msk (1UL << CoreDebug_DHCSR_S_RETIRE_ST_Pos) /*!< CoreDebug DHCSR: S_RETIRE_ST Mask */ - -#define CoreDebug_DHCSR_S_LOCKUP_Pos 19U /*!< CoreDebug DHCSR: S_LOCKUP Position */ -#define CoreDebug_DHCSR_S_LOCKUP_Msk (1UL << CoreDebug_DHCSR_S_LOCKUP_Pos) /*!< CoreDebug DHCSR: S_LOCKUP Mask */ - -#define CoreDebug_DHCSR_S_SLEEP_Pos 18U /*!< CoreDebug DHCSR: S_SLEEP Position */ -#define CoreDebug_DHCSR_S_SLEEP_Msk (1UL << CoreDebug_DHCSR_S_SLEEP_Pos) /*!< CoreDebug DHCSR: S_SLEEP Mask */ - -#define CoreDebug_DHCSR_S_HALT_Pos 17U /*!< CoreDebug DHCSR: S_HALT Position */ -#define CoreDebug_DHCSR_S_HALT_Msk (1UL << CoreDebug_DHCSR_S_HALT_Pos) /*!< CoreDebug DHCSR: S_HALT Mask */ - -#define CoreDebug_DHCSR_S_REGRDY_Pos 16U /*!< CoreDebug DHCSR: S_REGRDY Position */ -#define CoreDebug_DHCSR_S_REGRDY_Msk (1UL << CoreDebug_DHCSR_S_REGRDY_Pos) /*!< CoreDebug DHCSR: S_REGRDY Mask */ - -#define CoreDebug_DHCSR_C_MASKINTS_Pos 3U /*!< CoreDebug DHCSR: C_MASKINTS Position */ -#define CoreDebug_DHCSR_C_MASKINTS_Msk (1UL << CoreDebug_DHCSR_C_MASKINTS_Pos) /*!< CoreDebug DHCSR: C_MASKINTS Mask */ - -#define CoreDebug_DHCSR_C_STEP_Pos 2U /*!< CoreDebug DHCSR: C_STEP Position */ -#define CoreDebug_DHCSR_C_STEP_Msk (1UL << CoreDebug_DHCSR_C_STEP_Pos) /*!< CoreDebug DHCSR: C_STEP Mask */ - -#define CoreDebug_DHCSR_C_HALT_Pos 1U /*!< CoreDebug DHCSR: C_HALT Position */ -#define CoreDebug_DHCSR_C_HALT_Msk (1UL << CoreDebug_DHCSR_C_HALT_Pos) /*!< CoreDebug DHCSR: C_HALT Mask */ - -#define CoreDebug_DHCSR_C_DEBUGEN_Pos 0U /*!< CoreDebug DHCSR: C_DEBUGEN Position */ -#define CoreDebug_DHCSR_C_DEBUGEN_Msk (1UL /*<< CoreDebug_DHCSR_C_DEBUGEN_Pos*/) /*!< CoreDebug DHCSR: C_DEBUGEN Mask */ - -/* Debug Core Register Selector Register Definitions */ -#define CoreDebug_DCRSR_REGWnR_Pos 16U /*!< CoreDebug DCRSR: REGWnR Position */ -#define CoreDebug_DCRSR_REGWnR_Msk (1UL << CoreDebug_DCRSR_REGWnR_Pos) /*!< CoreDebug DCRSR: REGWnR Mask */ - -#define CoreDebug_DCRSR_REGSEL_Pos 0U /*!< CoreDebug DCRSR: REGSEL Position */ -#define CoreDebug_DCRSR_REGSEL_Msk (0x1FUL /*<< CoreDebug_DCRSR_REGSEL_Pos*/) /*!< CoreDebug DCRSR: REGSEL Mask */ - -/* Debug Exception and Monitor Control Register */ -#define CoreDebug_DEMCR_DWTENA_Pos 24U /*!< CoreDebug DEMCR: DWTENA Position */ -#define CoreDebug_DEMCR_DWTENA_Msk (1UL << CoreDebug_DEMCR_DWTENA_Pos) /*!< CoreDebug DEMCR: DWTENA Mask */ - -#define CoreDebug_DEMCR_VC_HARDERR_Pos 10U /*!< CoreDebug DEMCR: VC_HARDERR Position */ -#define CoreDebug_DEMCR_VC_HARDERR_Msk (1UL << CoreDebug_DEMCR_VC_HARDERR_Pos) /*!< CoreDebug DEMCR: VC_HARDERR Mask */ - -#define CoreDebug_DEMCR_VC_CORERESET_Pos 0U /*!< CoreDebug DEMCR: VC_CORERESET Position */ -#define CoreDebug_DEMCR_VC_CORERESET_Msk (1UL /*<< CoreDebug_DEMCR_VC_CORERESET_Pos*/) /*!< CoreDebug DEMCR: VC_CORERESET Mask */ - -/* Debug Authentication Control Register Definitions */ -#define CoreDebug_DAUTHCTRL_INTSPNIDEN_Pos 3U /*!< CoreDebug DAUTHCTRL: INTSPNIDEN, Position */ -#define CoreDebug_DAUTHCTRL_INTSPNIDEN_Msk (1UL << CoreDebug_DAUTHCTRL_INTSPNIDEN_Pos) /*!< CoreDebug DAUTHCTRL: INTSPNIDEN, Mask */ - -#define CoreDebug_DAUTHCTRL_SPNIDENSEL_Pos 2U /*!< CoreDebug DAUTHCTRL: SPNIDENSEL Position */ -#define CoreDebug_DAUTHCTRL_SPNIDENSEL_Msk (1UL << CoreDebug_DAUTHCTRL_SPNIDENSEL_Pos) /*!< CoreDebug DAUTHCTRL: SPNIDENSEL Mask */ - -#define CoreDebug_DAUTHCTRL_INTSPIDEN_Pos 1U /*!< CoreDebug DAUTHCTRL: INTSPIDEN Position */ -#define CoreDebug_DAUTHCTRL_INTSPIDEN_Msk (1UL << CoreDebug_DAUTHCTRL_INTSPIDEN_Pos) /*!< CoreDebug DAUTHCTRL: INTSPIDEN Mask */ - -#define CoreDebug_DAUTHCTRL_SPIDENSEL_Pos 0U /*!< CoreDebug DAUTHCTRL: SPIDENSEL Position */ -#define CoreDebug_DAUTHCTRL_SPIDENSEL_Msk (1UL /*<< CoreDebug_DAUTHCTRL_SPIDENSEL_Pos*/) /*!< CoreDebug DAUTHCTRL: SPIDENSEL Mask */ - -/* Debug Security Control and Status Register Definitions */ -#define CoreDebug_DSCSR_CDS_Pos 16U /*!< CoreDebug DSCSR: CDS Position */ -#define CoreDebug_DSCSR_CDS_Msk (1UL << CoreDebug_DSCSR_CDS_Pos) /*!< CoreDebug DSCSR: CDS Mask */ - -#define CoreDebug_DSCSR_SBRSEL_Pos 1U /*!< CoreDebug DSCSR: SBRSEL Position */ -#define CoreDebug_DSCSR_SBRSEL_Msk (1UL << CoreDebug_DSCSR_SBRSEL_Pos) /*!< CoreDebug DSCSR: SBRSEL Mask */ - -#define CoreDebug_DSCSR_SBRSELEN_Pos 0U /*!< CoreDebug DSCSR: SBRSELEN Position */ -#define CoreDebug_DSCSR_SBRSELEN_Msk (1UL /*<< CoreDebug_DSCSR_SBRSELEN_Pos*/) /*!< CoreDebug DSCSR: SBRSELEN Mask */ - -/*@} end of group CMSIS_CoreDebug */ - - -/** - \ingroup CMSIS_core_register - \defgroup CMSIS_core_bitfield Core register bit field macros - \brief Macros for use with bit field definitions (xxx_Pos, xxx_Msk). - @{ - */ - -/** - \brief Mask and shift a bit field value for use in a register bit range. - \param[in] field Name of the register bit field. - \param[in] value Value of the bit field. This parameter is interpreted as an uint32_t type. - \return Masked and shifted value. -*/ -#define _VAL2FLD(field, value) (((uint32_t)(value) << field ## _Pos) & field ## _Msk) - -/** - \brief Mask and shift a register value to extract a bit filed value. - \param[in] field Name of the register bit field. - \param[in] value Value of register. This parameter is interpreted as an uint32_t type. - \return Masked and shifted bit field value. -*/ -#define _FLD2VAL(field, value) (((uint32_t)(value) & field ## _Msk) >> field ## _Pos) - -/*@} end of group CMSIS_core_bitfield */ - - -/** - \ingroup CMSIS_core_register - \defgroup CMSIS_core_base Core Definitions - \brief Definitions for base addresses, unions, and structures. - @{ - */ - -/* Memory mapping of Core Hardware */ - #define SCS_BASE (0xE000E000UL) /*!< System Control Space Base Address */ - #define DWT_BASE (0xE0001000UL) /*!< DWT Base Address */ - #define TPI_BASE (0xE0040000UL) /*!< TPI Base Address */ - #define CoreDebug_BASE (0xE000EDF0UL) /*!< Core Debug Base Address */ - #define SysTick_BASE (SCS_BASE + 0x0010UL) /*!< SysTick Base Address */ - #define NVIC_BASE (SCS_BASE + 0x0100UL) /*!< NVIC Base Address */ - #define SCB_BASE (SCS_BASE + 0x0D00UL) /*!< System Control Block Base Address */ - - - #define SCB ((SCB_Type *) SCB_BASE ) /*!< SCB configuration struct */ - #define SysTick ((SysTick_Type *) SysTick_BASE ) /*!< SysTick configuration struct */ - #define NVIC ((NVIC_Type *) NVIC_BASE ) /*!< NVIC configuration struct */ - #define DWT ((DWT_Type *) DWT_BASE ) /*!< DWT configuration struct */ - #define TPI ((TPI_Type *) TPI_BASE ) /*!< TPI configuration struct */ - #define CoreDebug ((CoreDebug_Type *) CoreDebug_BASE ) /*!< Core Debug configuration struct */ - - #if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) - #define MPU_BASE (SCS_BASE + 0x0D90UL) /*!< Memory Protection Unit */ - #define MPU ((MPU_Type *) MPU_BASE ) /*!< Memory Protection Unit */ - #endif - - #if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) - #define SAU_BASE (SCS_BASE + 0x0DD0UL) /*!< Security Attribution Unit */ - #define SAU ((SAU_Type *) SAU_BASE ) /*!< Security Attribution Unit */ - #endif - -#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) - #define SCS_BASE_NS (0xE002E000UL) /*!< System Control Space Base Address (non-secure address space) */ - #define CoreDebug_BASE_NS (0xE002EDF0UL) /*!< Core Debug Base Address (non-secure address space) */ - #define SysTick_BASE_NS (SCS_BASE_NS + 0x0010UL) /*!< SysTick Base Address (non-secure address space) */ - #define NVIC_BASE_NS (SCS_BASE_NS + 0x0100UL) /*!< NVIC Base Address (non-secure address space) */ - #define SCB_BASE_NS (SCS_BASE_NS + 0x0D00UL) /*!< System Control Block Base Address (non-secure address space) */ - - #define SCB_NS ((SCB_Type *) SCB_BASE_NS ) /*!< SCB configuration struct (non-secure address space) */ - #define SysTick_NS ((SysTick_Type *) SysTick_BASE_NS ) /*!< SysTick configuration struct (non-secure address space) */ - #define NVIC_NS ((NVIC_Type *) NVIC_BASE_NS ) /*!< NVIC configuration struct (non-secure address space) */ - #define CoreDebug_NS ((CoreDebug_Type *) CoreDebug_BASE_NS) /*!< Core Debug configuration struct (non-secure address space) */ - - #if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) - #define MPU_BASE_NS (SCS_BASE_NS + 0x0D90UL) /*!< Memory Protection Unit (non-secure address space) */ - #define MPU_NS ((MPU_Type *) MPU_BASE_NS ) /*!< Memory Protection Unit (non-secure address space) */ - #endif - -#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */ -/*@} */ - - - -/******************************************************************************* - * Hardware Abstraction Layer - Core Function Interface contains: - - Core NVIC Functions - - Core SysTick Functions - - Core Register Access Functions - ******************************************************************************/ -/** - \defgroup CMSIS_Core_FunctionInterface Functions and Instructions Reference -*/ - - - -/* ########################## NVIC functions #################################### */ -/** - \ingroup CMSIS_Core_FunctionInterface - \defgroup CMSIS_Core_NVICFunctions NVIC Functions - \brief Functions that manage interrupts and exceptions via the NVIC. - @{ - */ - -#ifdef CMSIS_NVIC_VIRTUAL - #ifndef CMSIS_NVIC_VIRTUAL_HEADER_FILE - #define CMSIS_NVIC_VIRTUAL_HEADER_FILE "cmsis_nvic_virtual.h" - #endif - #include CMSIS_NVIC_VIRTUAL_HEADER_FILE -#else -/*#define NVIC_SetPriorityGrouping __NVIC_SetPriorityGrouping not available for Armv8-M Baseline */ -/*#define NVIC_GetPriorityGrouping __NVIC_GetPriorityGrouping not available for Armv8-M Baseline */ - #define NVIC_EnableIRQ __NVIC_EnableIRQ - #define NVIC_GetEnableIRQ __NVIC_GetEnableIRQ - #define NVIC_DisableIRQ __NVIC_DisableIRQ - #define NVIC_GetPendingIRQ __NVIC_GetPendingIRQ - #define NVIC_SetPendingIRQ __NVIC_SetPendingIRQ - #define NVIC_ClearPendingIRQ __NVIC_ClearPendingIRQ - #define NVIC_GetActive __NVIC_GetActive - #define NVIC_SetPriority __NVIC_SetPriority - #define NVIC_GetPriority __NVIC_GetPriority - #define NVIC_SystemReset __NVIC_SystemReset -#endif /* CMSIS_NVIC_VIRTUAL */ - -#ifdef CMSIS_VECTAB_VIRTUAL - #ifndef CMSIS_VECTAB_VIRTUAL_HEADER_FILE - #define CMSIS_VECTAB_VIRTUAL_HEADER_FILE "cmsis_vectab_virtual.h" - #endif - #include CMSIS_VECTAB_VIRTUAL_HEADER_FILE -#else - #define NVIC_SetVector __NVIC_SetVector - #define NVIC_GetVector __NVIC_GetVector -#endif /* (CMSIS_VECTAB_VIRTUAL) */ - -#define NVIC_USER_IRQ_OFFSET 16 - - -/* Interrupt Priorities are WORD accessible only under Armv6-M */ -/* The following MACROS handle generation of the register offset and byte masks */ -#define _BIT_SHIFT(IRQn) ( ((((uint32_t)(int32_t)(IRQn)) ) & 0x03UL) * 8UL) -#define _SHP_IDX(IRQn) ( (((((uint32_t)(int32_t)(IRQn)) & 0x0FUL)-8UL) >> 2UL) ) -#define _IP_IDX(IRQn) ( (((uint32_t)(int32_t)(IRQn)) >> 2UL) ) - - -/** - \brief Enable Interrupt - \details Enables a device specific interrupt in the NVIC interrupt controller. - \param [in] IRQn Device specific interrupt number. - \note IRQn must not be negative. - */ -__STATIC_INLINE void __NVIC_EnableIRQ(IRQn_Type IRQn) -{ - if ((int32_t)(IRQn) >= 0) - { - NVIC->ISER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); - } -} - - -/** - \brief Get Interrupt Enable status - \details Returns a device specific interrupt enable status from the NVIC interrupt controller. - \param [in] IRQn Device specific interrupt number. - \return 0 Interrupt is not enabled. - \return 1 Interrupt is enabled. - \note IRQn must not be negative. - */ -__STATIC_INLINE uint32_t __NVIC_GetEnableIRQ(IRQn_Type IRQn) -{ - if ((int32_t)(IRQn) >= 0) - { - return((uint32_t)(((NVIC->ISER[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); - } - else - { - return(0U); - } -} - - -/** - \brief Disable Interrupt - \details Disables a device specific interrupt in the NVIC interrupt controller. - \param [in] IRQn Device specific interrupt number. - \note IRQn must not be negative. - */ -__STATIC_INLINE void __NVIC_DisableIRQ(IRQn_Type IRQn) -{ - if ((int32_t)(IRQn) >= 0) - { - NVIC->ICER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); - __DSB(); - __ISB(); - } -} - - -/** - \brief Get Pending Interrupt - \details Reads the NVIC pending register and returns the pending bit for the specified device specific interrupt. - \param [in] IRQn Device specific interrupt number. - \return 0 Interrupt status is not pending. - \return 1 Interrupt status is pending. - \note IRQn must not be negative. - */ -__STATIC_INLINE uint32_t __NVIC_GetPendingIRQ(IRQn_Type IRQn) -{ - if ((int32_t)(IRQn) >= 0) - { - return((uint32_t)(((NVIC->ISPR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); - } - else - { - return(0U); - } -} - - -/** - \brief Set Pending Interrupt - \details Sets the pending bit of a device specific interrupt in the NVIC pending register. - \param [in] IRQn Device specific interrupt number. - \note IRQn must not be negative. - */ -__STATIC_INLINE void __NVIC_SetPendingIRQ(IRQn_Type IRQn) -{ - if ((int32_t)(IRQn) >= 0) - { - NVIC->ISPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); - } -} - - -/** - \brief Clear Pending Interrupt - \details Clears the pending bit of a device specific interrupt in the NVIC pending register. - \param [in] IRQn Device specific interrupt number. - \note IRQn must not be negative. - */ -__STATIC_INLINE void __NVIC_ClearPendingIRQ(IRQn_Type IRQn) -{ - if ((int32_t)(IRQn) >= 0) - { - NVIC->ICPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); - } -} - - -/** - \brief Get Active Interrupt - \details Reads the active register in the NVIC and returns the active bit for the device specific interrupt. - \param [in] IRQn Device specific interrupt number. - \return 0 Interrupt status is not active. - \return 1 Interrupt status is active. - \note IRQn must not be negative. - */ -__STATIC_INLINE uint32_t __NVIC_GetActive(IRQn_Type IRQn) -{ - if ((int32_t)(IRQn) >= 0) - { - return((uint32_t)(((NVIC->IABR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); - } - else - { - return(0U); - } -} - - -#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) -/** - \brief Get Interrupt Target State - \details Reads the interrupt target field in the NVIC and returns the interrupt target bit for the device specific interrupt. - \param [in] IRQn Device specific interrupt number. - \return 0 if interrupt is assigned to Secure - \return 1 if interrupt is assigned to Non Secure - \note IRQn must not be negative. - */ -__STATIC_INLINE uint32_t NVIC_GetTargetState(IRQn_Type IRQn) -{ - if ((int32_t)(IRQn) >= 0) - { - return((uint32_t)(((NVIC->ITNS[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); - } - else - { - return(0U); - } -} - - -/** - \brief Set Interrupt Target State - \details Sets the interrupt target field in the NVIC and returns the interrupt target bit for the device specific interrupt. - \param [in] IRQn Device specific interrupt number. - \return 0 if interrupt is assigned to Secure - 1 if interrupt is assigned to Non Secure - \note IRQn must not be negative. - */ -__STATIC_INLINE uint32_t NVIC_SetTargetState(IRQn_Type IRQn) -{ - if ((int32_t)(IRQn) >= 0) - { - NVIC->ITNS[(((uint32_t)IRQn) >> 5UL)] |= ((uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL))); - return((uint32_t)(((NVIC->ITNS[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); - } - else - { - return(0U); - } -} - - -/** - \brief Clear Interrupt Target State - \details Clears the interrupt target field in the NVIC and returns the interrupt target bit for the device specific interrupt. - \param [in] IRQn Device specific interrupt number. - \return 0 if interrupt is assigned to Secure - 1 if interrupt is assigned to Non Secure - \note IRQn must not be negative. - */ -__STATIC_INLINE uint32_t NVIC_ClearTargetState(IRQn_Type IRQn) -{ - if ((int32_t)(IRQn) >= 0) - { - NVIC->ITNS[(((uint32_t)IRQn) >> 5UL)] &= ~((uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL))); - return((uint32_t)(((NVIC->ITNS[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); - } - else - { - return(0U); - } -} -#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */ - - -/** - \brief Set Interrupt Priority - \details Sets the priority of a device specific interrupt or a processor exception. - The interrupt number can be positive to specify a device specific interrupt, - or negative to specify a processor exception. - \param [in] IRQn Interrupt number. - \param [in] priority Priority to set. - \note The priority cannot be set for every processor exception. - */ -__STATIC_INLINE void __NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority) -{ - if ((int32_t)(IRQn) >= 0) - { - NVIC->IPR[_IP_IDX(IRQn)] = ((uint32_t)(NVIC->IPR[_IP_IDX(IRQn)] & ~(0xFFUL << _BIT_SHIFT(IRQn))) | - (((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL) << _BIT_SHIFT(IRQn))); - } - else - { - SCB->SHPR[_SHP_IDX(IRQn)] = ((uint32_t)(SCB->SHPR[_SHP_IDX(IRQn)] & ~(0xFFUL << _BIT_SHIFT(IRQn))) | - (((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL) << _BIT_SHIFT(IRQn))); - } -} - - -/** - \brief Get Interrupt Priority - \details Reads the priority of a device specific interrupt or a processor exception. - The interrupt number can be positive to specify a device specific interrupt, - or negative to specify a processor exception. - \param [in] IRQn Interrupt number. - \return Interrupt Priority. - Value is aligned automatically to the implemented priority bits of the microcontroller. - */ -__STATIC_INLINE uint32_t __NVIC_GetPriority(IRQn_Type IRQn) -{ - - if ((int32_t)(IRQn) >= 0) - { - return((uint32_t)(((NVIC->IPR[ _IP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) & (uint32_t)0xFFUL) >> (8U - __NVIC_PRIO_BITS))); - } - else - { - return((uint32_t)(((SCB->SHPR[_SHP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) & (uint32_t)0xFFUL) >> (8U - __NVIC_PRIO_BITS))); - } -} - - -/** - \brief Set Interrupt Vector - \details Sets an interrupt vector in SRAM based interrupt vector table. - The interrupt number can be positive to specify a device specific interrupt, - or negative to specify a processor exception. - VTOR must been relocated to SRAM before. - If VTOR is not present address 0 must be mapped to SRAM. - \param [in] IRQn Interrupt number - \param [in] vector Address of interrupt handler function - */ -__STATIC_INLINE void __NVIC_SetVector(IRQn_Type IRQn, uint32_t vector) -{ -#if defined (__VTOR_PRESENT) && (__VTOR_PRESENT == 1U) - uint32_t *vectors = (uint32_t *)SCB->VTOR; -#else - uint32_t *vectors = (uint32_t *)0x0U; -#endif - vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET] = vector; -} - - -/** - \brief Get Interrupt Vector - \details Reads an interrupt vector from interrupt vector table. - The interrupt number can be positive to specify a device specific interrupt, - or negative to specify a processor exception. - \param [in] IRQn Interrupt number. - \return Address of interrupt handler function - */ -__STATIC_INLINE uint32_t __NVIC_GetVector(IRQn_Type IRQn) -{ -#if defined (__VTOR_PRESENT) && (__VTOR_PRESENT == 1U) - uint32_t *vectors = (uint32_t *)SCB->VTOR; -#else - uint32_t *vectors = (uint32_t *)0x0U; -#endif - return vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET]; -} - - -/** - \brief System Reset - \details Initiates a system reset request to reset the MCU. - */ -__STATIC_INLINE void __NVIC_SystemReset(void) -{ - __DSB(); /* Ensure all outstanding memory accesses included - buffered write are completed before reset */ - SCB->AIRCR = ((0x5FAUL << SCB_AIRCR_VECTKEY_Pos) | - SCB_AIRCR_SYSRESETREQ_Msk); - __DSB(); /* Ensure completion of memory access */ - - for(;;) /* wait until reset */ - { - __NOP(); - } -} - -#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) -/** - \brief Enable Interrupt (non-secure) - \details Enables a device specific interrupt in the non-secure NVIC interrupt controller when in secure state. - \param [in] IRQn Device specific interrupt number. - \note IRQn must not be negative. - */ -__STATIC_INLINE void TZ_NVIC_EnableIRQ_NS(IRQn_Type IRQn) -{ - if ((int32_t)(IRQn) >= 0) - { - NVIC_NS->ISER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); - } -} - - -/** - \brief Get Interrupt Enable status (non-secure) - \details Returns a device specific interrupt enable status from the non-secure NVIC interrupt controller when in secure state. - \param [in] IRQn Device specific interrupt number. - \return 0 Interrupt is not enabled. - \return 1 Interrupt is enabled. - \note IRQn must not be negative. - */ -__STATIC_INLINE uint32_t TZ_NVIC_GetEnableIRQ_NS(IRQn_Type IRQn) -{ - if ((int32_t)(IRQn) >= 0) - { - return((uint32_t)(((NVIC_NS->ISER[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); - } - else - { - return(0U); - } -} - - -/** - \brief Disable Interrupt (non-secure) - \details Disables a device specific interrupt in the non-secure NVIC interrupt controller when in secure state. - \param [in] IRQn Device specific interrupt number. - \note IRQn must not be negative. - */ -__STATIC_INLINE void TZ_NVIC_DisableIRQ_NS(IRQn_Type IRQn) -{ - if ((int32_t)(IRQn) >= 0) - { - NVIC_NS->ICER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); - } -} - - -/** - \brief Get Pending Interrupt (non-secure) - \details Reads the NVIC pending register in the non-secure NVIC when in secure state and returns the pending bit for the specified device specific interrupt. - \param [in] IRQn Device specific interrupt number. - \return 0 Interrupt status is not pending. - \return 1 Interrupt status is pending. - \note IRQn must not be negative. - */ -__STATIC_INLINE uint32_t TZ_NVIC_GetPendingIRQ_NS(IRQn_Type IRQn) -{ - if ((int32_t)(IRQn) >= 0) - { - return((uint32_t)(((NVIC_NS->ISPR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); - } - else - { - return(0U); - } -} - - -/** - \brief Set Pending Interrupt (non-secure) - \details Sets the pending bit of a device specific interrupt in the non-secure NVIC pending register when in secure state. - \param [in] IRQn Device specific interrupt number. - \note IRQn must not be negative. - */ -__STATIC_INLINE void TZ_NVIC_SetPendingIRQ_NS(IRQn_Type IRQn) -{ - if ((int32_t)(IRQn) >= 0) - { - NVIC_NS->ISPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); - } -} - - -/** - \brief Clear Pending Interrupt (non-secure) - \details Clears the pending bit of a device specific interrupt in the non-secure NVIC pending register when in secure state. - \param [in] IRQn Device specific interrupt number. - \note IRQn must not be negative. - */ -__STATIC_INLINE void TZ_NVIC_ClearPendingIRQ_NS(IRQn_Type IRQn) -{ - if ((int32_t)(IRQn) >= 0) - { - NVIC_NS->ICPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); - } -} - - -/** - \brief Get Active Interrupt (non-secure) - \details Reads the active register in non-secure NVIC when in secure state and returns the active bit for the device specific interrupt. - \param [in] IRQn Device specific interrupt number. - \return 0 Interrupt status is not active. - \return 1 Interrupt status is active. - \note IRQn must not be negative. - */ -__STATIC_INLINE uint32_t TZ_NVIC_GetActive_NS(IRQn_Type IRQn) -{ - if ((int32_t)(IRQn) >= 0) - { - return((uint32_t)(((NVIC_NS->IABR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); - } - else - { - return(0U); - } -} - - -/** - \brief Set Interrupt Priority (non-secure) - \details Sets the priority of a non-secure device specific interrupt or a non-secure processor exception when in secure state. - The interrupt number can be positive to specify a device specific interrupt, - or negative to specify a processor exception. - \param [in] IRQn Interrupt number. - \param [in] priority Priority to set. - \note The priority cannot be set for every non-secure processor exception. - */ -__STATIC_INLINE void TZ_NVIC_SetPriority_NS(IRQn_Type IRQn, uint32_t priority) -{ - if ((int32_t)(IRQn) >= 0) - { - NVIC_NS->IPR[_IP_IDX(IRQn)] = ((uint32_t)(NVIC_NS->IPR[_IP_IDX(IRQn)] & ~(0xFFUL << _BIT_SHIFT(IRQn))) | - (((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL) << _BIT_SHIFT(IRQn))); - } - else - { - SCB_NS->SHPR[_SHP_IDX(IRQn)] = ((uint32_t)(SCB_NS->SHPR[_SHP_IDX(IRQn)] & ~(0xFFUL << _BIT_SHIFT(IRQn))) | - (((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL) << _BIT_SHIFT(IRQn))); - } -} - - -/** - \brief Get Interrupt Priority (non-secure) - \details Reads the priority of a non-secure device specific interrupt or a non-secure processor exception when in secure state. - The interrupt number can be positive to specify a device specific interrupt, - or negative to specify a processor exception. - \param [in] IRQn Interrupt number. - \return Interrupt Priority. Value is aligned automatically to the implemented priority bits of the microcontroller. - */ -__STATIC_INLINE uint32_t TZ_NVIC_GetPriority_NS(IRQn_Type IRQn) -{ - - if ((int32_t)(IRQn) >= 0) - { - return((uint32_t)(((NVIC_NS->IPR[ _IP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) & (uint32_t)0xFFUL) >> (8U - __NVIC_PRIO_BITS))); - } - else - { - return((uint32_t)(((SCB_NS->SHPR[_SHP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) & (uint32_t)0xFFUL) >> (8U - __NVIC_PRIO_BITS))); - } -} -#endif /* defined (__ARM_FEATURE_CMSE) &&(__ARM_FEATURE_CMSE == 3U) */ - -/*@} end of CMSIS_Core_NVICFunctions */ - -/* ########################## MPU functions #################################### */ - -#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) - -#include "mpu_armv8.h" - -#endif - -/* ########################## FPU functions #################################### */ -/** - \ingroup CMSIS_Core_FunctionInterface - \defgroup CMSIS_Core_FpuFunctions FPU Functions - \brief Function that provides FPU type. - @{ - */ - -/** - \brief get FPU type - \details returns the FPU type - \returns - - \b 0: No FPU - - \b 1: Single precision FPU - - \b 2: Double + Single precision FPU - */ -__STATIC_INLINE uint32_t SCB_GetFPUType(void) -{ - return 0U; /* No FPU */ -} - - -/*@} end of CMSIS_Core_FpuFunctions */ - - - -/* ########################## SAU functions #################################### */ -/** - \ingroup CMSIS_Core_FunctionInterface - \defgroup CMSIS_Core_SAUFunctions SAU Functions - \brief Functions that configure the SAU. - @{ - */ - -#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) - -/** - \brief Enable SAU - \details Enables the Security Attribution Unit (SAU). - */ -__STATIC_INLINE void TZ_SAU_Enable(void) -{ - SAU->CTRL |= (SAU_CTRL_ENABLE_Msk); -} - - - -/** - \brief Disable SAU - \details Disables the Security Attribution Unit (SAU). - */ -__STATIC_INLINE void TZ_SAU_Disable(void) -{ - SAU->CTRL &= ~(SAU_CTRL_ENABLE_Msk); -} - -#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */ - -/*@} end of CMSIS_Core_SAUFunctions */ - - - - -/* ################################## SysTick function ############################################ */ -/** - \ingroup CMSIS_Core_FunctionInterface - \defgroup CMSIS_Core_SysTickFunctions SysTick Functions - \brief Functions that configure the System. - @{ - */ - -#if defined (__Vendor_SysTickConfig) && (__Vendor_SysTickConfig == 0U) - -/** - \brief System Tick Configuration - \details Initializes the System Timer and its interrupt, and starts the System Tick Timer. - Counter is in free running mode to generate periodic interrupts. - \param [in] ticks Number of ticks between two interrupts. - \return 0 Function succeeded. - \return 1 Function failed. - \note When the variable __Vendor_SysTickConfig is set to 1, then the - function SysTick_Config is not included. In this case, the file device.h - must contain a vendor-specific implementation of this function. - */ -__STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks) -{ - if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk) - { - return (1UL); /* Reload value impossible */ - } - - SysTick->LOAD = (uint32_t)(ticks - 1UL); /* set reload register */ - NVIC_SetPriority (SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */ - SysTick->VAL = 0UL; /* Load the SysTick Counter Value */ - SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk | - SysTick_CTRL_TICKINT_Msk | - SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */ - return (0UL); /* Function successful */ -} - -#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) -/** - \brief System Tick Configuration (non-secure) - \details Initializes the non-secure System Timer and its interrupt when in secure state, and starts the System Tick Timer. - Counter is in free running mode to generate periodic interrupts. - \param [in] ticks Number of ticks between two interrupts. - \return 0 Function succeeded. - \return 1 Function failed. - \note When the variable __Vendor_SysTickConfig is set to 1, then the - function TZ_SysTick_Config_NS is not included. In this case, the file device.h - must contain a vendor-specific implementation of this function. - - */ -__STATIC_INLINE uint32_t TZ_SysTick_Config_NS(uint32_t ticks) -{ - if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk) - { - return (1UL); /* Reload value impossible */ - } - - SysTick_NS->LOAD = (uint32_t)(ticks - 1UL); /* set reload register */ - TZ_NVIC_SetPriority_NS (SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */ - SysTick_NS->VAL = 0UL; /* Load the SysTick Counter Value */ - SysTick_NS->CTRL = SysTick_CTRL_CLKSOURCE_Msk | - SysTick_CTRL_TICKINT_Msk | - SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */ - return (0UL); /* Function successful */ -} -#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */ - -#endif - -/*@} end of CMSIS_Core_SysTickFunctions */ - - - - -#ifdef __cplusplus -} -#endif - -#endif /* __CORE_ARMV8MBL_H_DEPENDANT */ - -#endif /* __CMSIS_GENERIC */ diff --git a/bsp/essemi/es32f0271/libraries/CMSIS/Include/core_armv8mml.h b/bsp/essemi/es32f0271/libraries/CMSIS/Include/core_armv8mml.h deleted file mode 100644 index 0951a1f781..0000000000 --- a/bsp/essemi/es32f0271/libraries/CMSIS/Include/core_armv8mml.h +++ /dev/null @@ -1,2960 +0,0 @@ -/**************************************************************************//** - * @file core_armv8mml.h - * @brief CMSIS Armv8-M Mainline Core Peripheral Access Layer Header File - * @version V5.0.4 - * @date 10. January 2018 - ******************************************************************************/ -/* - * Copyright (c) 2009-2018 Arm Limited. All rights reserved. - * - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed under the Apache License, Version 2.0 (the License); you may - * not use this file except in compliance with the License. - * You may obtain a copy of the License at - * - * www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an AS IS BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - */ - -#if defined ( __ICCARM__ ) - #pragma system_include /* treat file as system include file for MISRA check */ -#elif defined (__clang__) - #pragma clang system_header /* treat file as system include file */ -#endif - -#ifndef __CORE_ARMV8MML_H_GENERIC -#define __CORE_ARMV8MML_H_GENERIC - -#include - -#ifdef __cplusplus - extern "C" { -#endif - -/** - \page CMSIS_MISRA_Exceptions MISRA-C:2004 Compliance Exceptions - CMSIS violates the following MISRA-C:2004 rules: - - \li Required Rule 8.5, object/function definition in header file.
- Function definitions in header files are used to allow 'inlining'. - - \li Required Rule 18.4, declaration of union type or object of union type: '{...}'.
- Unions are used for effective representation of core registers. - - \li Advisory Rule 19.7, Function-like macro defined.
- Function-like macros are used to allow more efficient code. - */ - - -/******************************************************************************* - * CMSIS definitions - ******************************************************************************/ -/** - \ingroup Cortex_ARMv8MML - @{ - */ - -#include "cmsis_version.h" - -/* CMSIS Armv8MML definitions */ -#define __ARMv8MML_CMSIS_VERSION_MAIN (__CM_CMSIS_VERSION_MAIN) /*!< \deprecated [31:16] CMSIS HAL main version */ -#define __ARMv8MML_CMSIS_VERSION_SUB (__CM_CMSIS_VERSION_SUB) /*!< \deprecated [15:0] CMSIS HAL sub version */ -#define __ARMv8MML_CMSIS_VERSION ((__ARMv8MML_CMSIS_VERSION_MAIN << 16U) | \ - __ARMv8MML_CMSIS_VERSION_SUB ) /*!< \deprecated CMSIS HAL version number */ - -#define __CORTEX_M (81U) /*!< Cortex-M Core */ - -/** __FPU_USED indicates whether an FPU is used or not. - For this, __FPU_PRESENT has to be checked prior to making use of FPU specific registers and functions. -*/ -#if defined ( __CC_ARM ) - #if defined __TARGET_FPU_VFP - #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) - #define __FPU_USED 1U - #else - #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" - #define __FPU_USED 0U - #endif - #else - #define __FPU_USED 0U - #endif - - #if defined(__ARM_FEATURE_DSP) - #if defined(__DSP_PRESENT) && (__DSP_PRESENT == 1U) - #define __DSP_USED 1U - #else - #error "Compiler generates DSP (SIMD) instructions for a devices without DSP extensions (check __DSP_PRESENT)" - #define __DSP_USED 0U - #endif - #else - #define __DSP_USED 0U - #endif - -#elif defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) - #if defined __ARM_PCS_VFP - #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) - #define __FPU_USED 1U - #else - #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" - #define __FPU_USED 0U - #endif - #else - #define __FPU_USED 0U - #endif - - #if defined(__ARM_FEATURE_DSP) - #if defined(__DSP_PRESENT) && (__DSP_PRESENT == 1U) - #define __DSP_USED 1U - #else - #error "Compiler generates DSP (SIMD) instructions for a devices without DSP extensions (check __DSP_PRESENT)" - #define __DSP_USED 0U - #endif - #else - #define __DSP_USED 0U - #endif - -#elif defined ( __GNUC__ ) - #if defined (__VFP_FP__) && !defined(__SOFTFP__) - #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) - #define __FPU_USED 1U - #else - #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" - #define __FPU_USED 0U - #endif - #else - #define __FPU_USED 0U - #endif - - #if defined(__ARM_FEATURE_DSP) - #if defined(__DSP_PRESENT) && (__DSP_PRESENT == 1U) - #define __DSP_USED 1U - #else - #error "Compiler generates DSP (SIMD) instructions for a devices without DSP extensions (check __DSP_PRESENT)" - #define __DSP_USED 0U - #endif - #else - #define __DSP_USED 0U - #endif - -#elif defined ( __ICCARM__ ) - #if defined __ARMVFP__ - #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) - #define __FPU_USED 1U - #else - #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" - #define __FPU_USED 0U - #endif - #else - #define __FPU_USED 0U - #endif - - #if defined(__ARM_FEATURE_DSP) - #if defined(__DSP_PRESENT) && (__DSP_PRESENT == 1U) - #define __DSP_USED 1U - #else - #error "Compiler generates DSP (SIMD) instructions for a devices without DSP extensions (check __DSP_PRESENT)" - #define __DSP_USED 0U - #endif - #else - #define __DSP_USED 0U - #endif - -#elif defined ( __TI_ARM__ ) - #if defined __TI_VFP_SUPPORT__ - #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) - #define __FPU_USED 1U - #else - #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" - #define __FPU_USED 0U - #endif - #else - #define __FPU_USED 0U - #endif - -#elif defined ( __TASKING__ ) - #if defined __FPU_VFP__ - #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) - #define __FPU_USED 1U - #else - #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" - #define __FPU_USED 0U - #endif - #else - #define __FPU_USED 0U - #endif - -#elif defined ( __CSMC__ ) - #if ( __CSMC__ & 0x400U) - #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) - #define __FPU_USED 1U - #else - #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" - #define __FPU_USED 0U - #endif - #else - #define __FPU_USED 0U - #endif - -#endif - -#include "cmsis_compiler.h" /* CMSIS compiler specific defines */ - - -#ifdef __cplusplus -} -#endif - -#endif /* __CORE_ARMV8MML_H_GENERIC */ - -#ifndef __CMSIS_GENERIC - -#ifndef __CORE_ARMV8MML_H_DEPENDANT -#define __CORE_ARMV8MML_H_DEPENDANT - -#ifdef __cplusplus - extern "C" { -#endif - -/* check device defines and use defaults */ -#if defined __CHECK_DEVICE_DEFINES - #ifndef __ARMv8MML_REV - #define __ARMv8MML_REV 0x0000U - #warning "__ARMv8MML_REV not defined in device header file; using default!" - #endif - - #ifndef __FPU_PRESENT - #define __FPU_PRESENT 0U - #warning "__FPU_PRESENT not defined in device header file; using default!" - #endif - - #ifndef __MPU_PRESENT - #define __MPU_PRESENT 0U - #warning "__MPU_PRESENT not defined in device header file; using default!" - #endif - - #ifndef __SAUREGION_PRESENT - #define __SAUREGION_PRESENT 0U - #warning "__SAUREGION_PRESENT not defined in device header file; using default!" - #endif - - #ifndef __DSP_PRESENT - #define __DSP_PRESENT 0U - #warning "__DSP_PRESENT not defined in device header file; using default!" - #endif - - #ifndef __NVIC_PRIO_BITS - #define __NVIC_PRIO_BITS 3U - #warning "__NVIC_PRIO_BITS not defined in device header file; using default!" - #endif - - #ifndef __Vendor_SysTickConfig - #define __Vendor_SysTickConfig 0U - #warning "__Vendor_SysTickConfig not defined in device header file; using default!" - #endif -#endif - -/* IO definitions (access restrictions to peripheral registers) */ -/** - \defgroup CMSIS_glob_defs CMSIS Global Defines - - IO Type Qualifiers are used - \li to specify the access to peripheral variables. - \li for automatic generation of peripheral register debug information. -*/ -#ifdef __cplusplus - #define __I volatile /*!< Defines 'read only' permissions */ -#else - #define __I volatile const /*!< Defines 'read only' permissions */ -#endif -#define __O volatile /*!< Defines 'write only' permissions */ -#define __IO volatile /*!< Defines 'read / write' permissions */ - -/* following defines should be used for structure members */ -#define __IM volatile const /*! Defines 'read only' structure member permissions */ -#define __OM volatile /*! Defines 'write only' structure member permissions */ -#define __IOM volatile /*! Defines 'read / write' structure member permissions */ - -/*@} end of group ARMv8MML */ - - - -/******************************************************************************* - * Register Abstraction - Core Register contain: - - Core Register - - Core NVIC Register - - Core SCB Register - - Core SysTick Register - - Core Debug Register - - Core MPU Register - - Core SAU Register - - Core FPU Register - ******************************************************************************/ -/** - \defgroup CMSIS_core_register Defines and Type Definitions - \brief Type definitions and defines for Cortex-M processor based devices. -*/ - -/** - \ingroup CMSIS_core_register - \defgroup CMSIS_CORE Status and Control Registers - \brief Core Register type definitions. - @{ - */ - -/** - \brief Union type to access the Application Program Status Register (APSR). - */ -typedef union -{ - struct - { - uint32_t _reserved0:16; /*!< bit: 0..15 Reserved */ - uint32_t GE:4; /*!< bit: 16..19 Greater than or Equal flags */ - uint32_t _reserved1:7; /*!< bit: 20..26 Reserved */ - uint32_t Q:1; /*!< bit: 27 Saturation condition flag */ - uint32_t V:1; /*!< bit: 28 Overflow condition code flag */ - uint32_t C:1; /*!< bit: 29 Carry condition code flag */ - uint32_t Z:1; /*!< bit: 30 Zero condition code flag */ - uint32_t N:1; /*!< bit: 31 Negative condition code flag */ - } b; /*!< Structure used for bit access */ - uint32_t w; /*!< Type used for word access */ -} APSR_Type; - -/* APSR Register Definitions */ -#define APSR_N_Pos 31U /*!< APSR: N Position */ -#define APSR_N_Msk (1UL << APSR_N_Pos) /*!< APSR: N Mask */ - -#define APSR_Z_Pos 30U /*!< APSR: Z Position */ -#define APSR_Z_Msk (1UL << APSR_Z_Pos) /*!< APSR: Z Mask */ - -#define APSR_C_Pos 29U /*!< APSR: C Position */ -#define APSR_C_Msk (1UL << APSR_C_Pos) /*!< APSR: C Mask */ - -#define APSR_V_Pos 28U /*!< APSR: V Position */ -#define APSR_V_Msk (1UL << APSR_V_Pos) /*!< APSR: V Mask */ - -#define APSR_Q_Pos 27U /*!< APSR: Q Position */ -#define APSR_Q_Msk (1UL << APSR_Q_Pos) /*!< APSR: Q Mask */ - -#define APSR_GE_Pos 16U /*!< APSR: GE Position */ -#define APSR_GE_Msk (0xFUL << APSR_GE_Pos) /*!< APSR: GE Mask */ - - -/** - \brief Union type to access the Interrupt Program Status Register (IPSR). - */ -typedef union -{ - struct - { - uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */ - uint32_t _reserved0:23; /*!< bit: 9..31 Reserved */ - } b; /*!< Structure used for bit access */ - uint32_t w; /*!< Type used for word access */ -} IPSR_Type; - -/* IPSR Register Definitions */ -#define IPSR_ISR_Pos 0U /*!< IPSR: ISR Position */ -#define IPSR_ISR_Msk (0x1FFUL /*<< IPSR_ISR_Pos*/) /*!< IPSR: ISR Mask */ - - -/** - \brief Union type to access the Special-Purpose Program Status Registers (xPSR). - */ -typedef union -{ - struct - { - uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */ - uint32_t _reserved0:7; /*!< bit: 9..15 Reserved */ - uint32_t GE:4; /*!< bit: 16..19 Greater than or Equal flags */ - uint32_t _reserved1:4; /*!< bit: 20..23 Reserved */ - uint32_t T:1; /*!< bit: 24 Thumb bit (read 0) */ - uint32_t IT:2; /*!< bit: 25..26 saved IT state (read 0) */ - uint32_t Q:1; /*!< bit: 27 Saturation condition flag */ - uint32_t V:1; /*!< bit: 28 Overflow condition code flag */ - uint32_t C:1; /*!< bit: 29 Carry condition code flag */ - uint32_t Z:1; /*!< bit: 30 Zero condition code flag */ - uint32_t N:1; /*!< bit: 31 Negative condition code flag */ - } b; /*!< Structure used for bit access */ - uint32_t w; /*!< Type used for word access */ -} xPSR_Type; - -/* xPSR Register Definitions */ -#define xPSR_N_Pos 31U /*!< xPSR: N Position */ -#define xPSR_N_Msk (1UL << xPSR_N_Pos) /*!< xPSR: N Mask */ - -#define xPSR_Z_Pos 30U /*!< xPSR: Z Position */ -#define xPSR_Z_Msk (1UL << xPSR_Z_Pos) /*!< xPSR: Z Mask */ - -#define xPSR_C_Pos 29U /*!< xPSR: C Position */ -#define xPSR_C_Msk (1UL << xPSR_C_Pos) /*!< xPSR: C Mask */ - -#define xPSR_V_Pos 28U /*!< xPSR: V Position */ -#define xPSR_V_Msk (1UL << xPSR_V_Pos) /*!< xPSR: V Mask */ - -#define xPSR_Q_Pos 27U /*!< xPSR: Q Position */ -#define xPSR_Q_Msk (1UL << xPSR_Q_Pos) /*!< xPSR: Q Mask */ - -#define xPSR_IT_Pos 25U /*!< xPSR: IT Position */ -#define xPSR_IT_Msk (3UL << xPSR_IT_Pos) /*!< xPSR: IT Mask */ - -#define xPSR_T_Pos 24U /*!< xPSR: T Position */ -#define xPSR_T_Msk (1UL << xPSR_T_Pos) /*!< xPSR: T Mask */ - -#define xPSR_GE_Pos 16U /*!< xPSR: GE Position */ -#define xPSR_GE_Msk (0xFUL << xPSR_GE_Pos) /*!< xPSR: GE Mask */ - -#define xPSR_ISR_Pos 0U /*!< xPSR: ISR Position */ -#define xPSR_ISR_Msk (0x1FFUL /*<< xPSR_ISR_Pos*/) /*!< xPSR: ISR Mask */ - - -/** - \brief Union type to access the Control Registers (CONTROL). - */ -typedef union -{ - struct - { - uint32_t nPRIV:1; /*!< bit: 0 Execution privilege in Thread mode */ - uint32_t SPSEL:1; /*!< bit: 1 Stack-pointer select */ - uint32_t FPCA:1; /*!< bit: 2 Floating-point context active */ - uint32_t SFPA:1; /*!< bit: 3 Secure floating-point active */ - uint32_t _reserved1:28; /*!< bit: 4..31 Reserved */ - } b; /*!< Structure used for bit access */ - uint32_t w; /*!< Type used for word access */ -} CONTROL_Type; - -/* CONTROL Register Definitions */ -#define CONTROL_SFPA_Pos 3U /*!< CONTROL: SFPA Position */ -#define CONTROL_SFPA_Msk (1UL << CONTROL_SFPA_Pos) /*!< CONTROL: SFPA Mask */ - -#define CONTROL_FPCA_Pos 2U /*!< CONTROL: FPCA Position */ -#define CONTROL_FPCA_Msk (1UL << CONTROL_FPCA_Pos) /*!< CONTROL: FPCA Mask */ - -#define CONTROL_SPSEL_Pos 1U /*!< CONTROL: SPSEL Position */ -#define CONTROL_SPSEL_Msk (1UL << CONTROL_SPSEL_Pos) /*!< CONTROL: SPSEL Mask */ - -#define CONTROL_nPRIV_Pos 0U /*!< CONTROL: nPRIV Position */ -#define CONTROL_nPRIV_Msk (1UL /*<< CONTROL_nPRIV_Pos*/) /*!< CONTROL: nPRIV Mask */ - -/*@} end of group CMSIS_CORE */ - - -/** - \ingroup CMSIS_core_register - \defgroup CMSIS_NVIC Nested Vectored Interrupt Controller (NVIC) - \brief Type definitions for the NVIC Registers - @{ - */ - -/** - \brief Structure type to access the Nested Vectored Interrupt Controller (NVIC). - */ -typedef struct -{ - __IOM uint32_t ISER[16U]; /*!< Offset: 0x000 (R/W) Interrupt Set Enable Register */ - uint32_t RESERVED0[16U]; - __IOM uint32_t ICER[16U]; /*!< Offset: 0x080 (R/W) Interrupt Clear Enable Register */ - uint32_t RSERVED1[16U]; - __IOM uint32_t ISPR[16U]; /*!< Offset: 0x100 (R/W) Interrupt Set Pending Register */ - uint32_t RESERVED2[16U]; - __IOM uint32_t ICPR[16U]; /*!< Offset: 0x180 (R/W) Interrupt Clear Pending Register */ - uint32_t RESERVED3[16U]; - __IOM uint32_t IABR[16U]; /*!< Offset: 0x200 (R/W) Interrupt Active bit Register */ - uint32_t RESERVED4[16U]; - __IOM uint32_t ITNS[16U]; /*!< Offset: 0x280 (R/W) Interrupt Non-Secure State Register */ - uint32_t RESERVED5[16U]; - __IOM uint8_t IPR[496U]; /*!< Offset: 0x300 (R/W) Interrupt Priority Register (8Bit wide) */ - uint32_t RESERVED6[580U]; - __OM uint32_t STIR; /*!< Offset: 0xE00 ( /W) Software Trigger Interrupt Register */ -} NVIC_Type; - -/* Software Triggered Interrupt Register Definitions */ -#define NVIC_STIR_INTID_Pos 0U /*!< STIR: INTLINESNUM Position */ -#define NVIC_STIR_INTID_Msk (0x1FFUL /*<< NVIC_STIR_INTID_Pos*/) /*!< STIR: INTLINESNUM Mask */ - -/*@} end of group CMSIS_NVIC */ - - -/** - \ingroup CMSIS_core_register - \defgroup CMSIS_SCB System Control Block (SCB) - \brief Type definitions for the System Control Block Registers - @{ - */ - -/** - \brief Structure type to access the System Control Block (SCB). - */ -typedef struct -{ - __IM uint32_t CPUID; /*!< Offset: 0x000 (R/ ) CPUID Base Register */ - __IOM uint32_t ICSR; /*!< Offset: 0x004 (R/W) Interrupt Control and State Register */ - __IOM uint32_t VTOR; /*!< Offset: 0x008 (R/W) Vector Table Offset Register */ - __IOM uint32_t AIRCR; /*!< Offset: 0x00C (R/W) Application Interrupt and Reset Control Register */ - __IOM uint32_t SCR; /*!< Offset: 0x010 (R/W) System Control Register */ - __IOM uint32_t CCR; /*!< Offset: 0x014 (R/W) Configuration Control Register */ - __IOM uint8_t SHPR[12U]; /*!< Offset: 0x018 (R/W) System Handlers Priority Registers (4-7, 8-11, 12-15) */ - __IOM uint32_t SHCSR; /*!< Offset: 0x024 (R/W) System Handler Control and State Register */ - __IOM uint32_t CFSR; /*!< Offset: 0x028 (R/W) Configurable Fault Status Register */ - __IOM uint32_t HFSR; /*!< Offset: 0x02C (R/W) HardFault Status Register */ - __IOM uint32_t DFSR; /*!< Offset: 0x030 (R/W) Debug Fault Status Register */ - __IOM uint32_t MMFAR; /*!< Offset: 0x034 (R/W) MemManage Fault Address Register */ - __IOM uint32_t BFAR; /*!< Offset: 0x038 (R/W) BusFault Address Register */ - __IOM uint32_t AFSR; /*!< Offset: 0x03C (R/W) Auxiliary Fault Status Register */ - __IM uint32_t ID_PFR[2U]; /*!< Offset: 0x040 (R/ ) Processor Feature Register */ - __IM uint32_t ID_DFR; /*!< Offset: 0x048 (R/ ) Debug Feature Register */ - __IM uint32_t ID_ADR; /*!< Offset: 0x04C (R/ ) Auxiliary Feature Register */ - __IM uint32_t ID_MMFR[4U]; /*!< Offset: 0x050 (R/ ) Memory Model Feature Register */ - __IM uint32_t ID_ISAR[6U]; /*!< Offset: 0x060 (R/ ) Instruction Set Attributes Register */ - __IM uint32_t CLIDR; /*!< Offset: 0x078 (R/ ) Cache Level ID register */ - __IM uint32_t CTR; /*!< Offset: 0x07C (R/ ) Cache Type register */ - __IM uint32_t CCSIDR; /*!< Offset: 0x080 (R/ ) Cache Size ID Register */ - __IOM uint32_t CSSELR; /*!< Offset: 0x084 (R/W) Cache Size Selection Register */ - __IOM uint32_t CPACR; /*!< Offset: 0x088 (R/W) Coprocessor Access Control Register */ - __IOM uint32_t NSACR; /*!< Offset: 0x08C (R/W) Non-Secure Access Control Register */ - uint32_t RESERVED3[92U]; - __OM uint32_t STIR; /*!< Offset: 0x200 ( /W) Software Triggered Interrupt Register */ - uint32_t RESERVED4[15U]; - __IM uint32_t MVFR0; /*!< Offset: 0x240 (R/ ) Media and VFP Feature Register 0 */ - __IM uint32_t MVFR1; /*!< Offset: 0x244 (R/ ) Media and VFP Feature Register 1 */ - __IM uint32_t MVFR2; /*!< Offset: 0x248 (R/ ) Media and VFP Feature Register 2 */ - uint32_t RESERVED5[1U]; - __OM uint32_t ICIALLU; /*!< Offset: 0x250 ( /W) I-Cache Invalidate All to PoU */ - uint32_t RESERVED6[1U]; - __OM uint32_t ICIMVAU; /*!< Offset: 0x258 ( /W) I-Cache Invalidate by MVA to PoU */ - __OM uint32_t DCIMVAC; /*!< Offset: 0x25C ( /W) D-Cache Invalidate by MVA to PoC */ - __OM uint32_t DCISW; /*!< Offset: 0x260 ( /W) D-Cache Invalidate by Set-way */ - __OM uint32_t DCCMVAU; /*!< Offset: 0x264 ( /W) D-Cache Clean by MVA to PoU */ - __OM uint32_t DCCMVAC; /*!< Offset: 0x268 ( /W) D-Cache Clean by MVA to PoC */ - __OM uint32_t DCCSW; /*!< Offset: 0x26C ( /W) D-Cache Clean by Set-way */ - __OM uint32_t DCCIMVAC; /*!< Offset: 0x270 ( /W) D-Cache Clean and Invalidate by MVA to PoC */ - __OM uint32_t DCCISW; /*!< Offset: 0x274 ( /W) D-Cache Clean and Invalidate by Set-way */ - uint32_t RESERVED7[6U]; - __IOM uint32_t ITCMCR; /*!< Offset: 0x290 (R/W) Instruction Tightly-Coupled Memory Control Register */ - __IOM uint32_t DTCMCR; /*!< Offset: 0x294 (R/W) Data Tightly-Coupled Memory Control Registers */ - __IOM uint32_t AHBPCR; /*!< Offset: 0x298 (R/W) AHBP Control Register */ - __IOM uint32_t CACR; /*!< Offset: 0x29C (R/W) L1 Cache Control Register */ - __IOM uint32_t AHBSCR; /*!< Offset: 0x2A0 (R/W) AHB Slave Control Register */ - uint32_t RESERVED8[1U]; - __IOM uint32_t ABFSR; /*!< Offset: 0x2A8 (R/W) Auxiliary Bus Fault Status Register */ -} SCB_Type; - -/* SCB CPUID Register Definitions */ -#define SCB_CPUID_IMPLEMENTER_Pos 24U /*!< SCB CPUID: IMPLEMENTER Position */ -#define SCB_CPUID_IMPLEMENTER_Msk (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos) /*!< SCB CPUID: IMPLEMENTER Mask */ - -#define SCB_CPUID_VARIANT_Pos 20U /*!< SCB CPUID: VARIANT Position */ -#define SCB_CPUID_VARIANT_Msk (0xFUL << SCB_CPUID_VARIANT_Pos) /*!< SCB CPUID: VARIANT Mask */ - -#define SCB_CPUID_ARCHITECTURE_Pos 16U /*!< SCB CPUID: ARCHITECTURE Position */ -#define SCB_CPUID_ARCHITECTURE_Msk (0xFUL << SCB_CPUID_ARCHITECTURE_Pos) /*!< SCB CPUID: ARCHITECTURE Mask */ - -#define SCB_CPUID_PARTNO_Pos 4U /*!< SCB CPUID: PARTNO Position */ -#define SCB_CPUID_PARTNO_Msk (0xFFFUL << SCB_CPUID_PARTNO_Pos) /*!< SCB CPUID: PARTNO Mask */ - -#define SCB_CPUID_REVISION_Pos 0U /*!< SCB CPUID: REVISION Position */ -#define SCB_CPUID_REVISION_Msk (0xFUL /*<< SCB_CPUID_REVISION_Pos*/) /*!< SCB CPUID: REVISION Mask */ - -/* SCB Interrupt Control State Register Definitions */ -#define SCB_ICSR_PENDNMISET_Pos 31U /*!< SCB ICSR: PENDNMISET Position */ -#define SCB_ICSR_PENDNMISET_Msk (1UL << SCB_ICSR_PENDNMISET_Pos) /*!< SCB ICSR: PENDNMISET Mask */ - -#define SCB_ICSR_PENDNMICLR_Pos 30U /*!< SCB ICSR: PENDNMICLR Position */ -#define SCB_ICSR_PENDNMICLR_Msk (1UL << SCB_ICSR_PENDNMICLR_Pos) /*!< SCB ICSR: PENDNMICLR Mask */ - -#define SCB_ICSR_PENDSVSET_Pos 28U /*!< SCB ICSR: PENDSVSET Position */ -#define SCB_ICSR_PENDSVSET_Msk (1UL << SCB_ICSR_PENDSVSET_Pos) /*!< SCB ICSR: PENDSVSET Mask */ - -#define SCB_ICSR_PENDSVCLR_Pos 27U /*!< SCB ICSR: PENDSVCLR Position */ -#define SCB_ICSR_PENDSVCLR_Msk (1UL << SCB_ICSR_PENDSVCLR_Pos) /*!< SCB ICSR: PENDSVCLR Mask */ - -#define SCB_ICSR_PENDSTSET_Pos 26U /*!< SCB ICSR: PENDSTSET Position */ -#define SCB_ICSR_PENDSTSET_Msk (1UL << SCB_ICSR_PENDSTSET_Pos) /*!< SCB ICSR: PENDSTSET Mask */ - -#define SCB_ICSR_PENDSTCLR_Pos 25U /*!< SCB ICSR: PENDSTCLR Position */ -#define SCB_ICSR_PENDSTCLR_Msk (1UL << SCB_ICSR_PENDSTCLR_Pos) /*!< SCB ICSR: PENDSTCLR Mask */ - -#define SCB_ICSR_STTNS_Pos 24U /*!< SCB ICSR: STTNS Position (Security Extension) */ -#define SCB_ICSR_STTNS_Msk (1UL << SCB_ICSR_STTNS_Pos) /*!< SCB ICSR: STTNS Mask (Security Extension) */ - -#define SCB_ICSR_ISRPREEMPT_Pos 23U /*!< SCB ICSR: ISRPREEMPT Position */ -#define SCB_ICSR_ISRPREEMPT_Msk (1UL << SCB_ICSR_ISRPREEMPT_Pos) /*!< SCB ICSR: ISRPREEMPT Mask */ - -#define SCB_ICSR_ISRPENDING_Pos 22U /*!< SCB ICSR: ISRPENDING Position */ -#define SCB_ICSR_ISRPENDING_Msk (1UL << SCB_ICSR_ISRPENDING_Pos) /*!< SCB ICSR: ISRPENDING Mask */ - -#define SCB_ICSR_VECTPENDING_Pos 12U /*!< SCB ICSR: VECTPENDING Position */ -#define SCB_ICSR_VECTPENDING_Msk (0x1FFUL << SCB_ICSR_VECTPENDING_Pos) /*!< SCB ICSR: VECTPENDING Mask */ - -#define SCB_ICSR_RETTOBASE_Pos 11U /*!< SCB ICSR: RETTOBASE Position */ -#define SCB_ICSR_RETTOBASE_Msk (1UL << SCB_ICSR_RETTOBASE_Pos) /*!< SCB ICSR: RETTOBASE Mask */ - -#define SCB_ICSR_VECTACTIVE_Pos 0U /*!< SCB ICSR: VECTACTIVE Position */ -#define SCB_ICSR_VECTACTIVE_Msk (0x1FFUL /*<< SCB_ICSR_VECTACTIVE_Pos*/) /*!< SCB ICSR: VECTACTIVE Mask */ - -/* SCB Vector Table Offset Register Definitions */ -#define SCB_VTOR_TBLOFF_Pos 7U /*!< SCB VTOR: TBLOFF Position */ -#define SCB_VTOR_TBLOFF_Msk (0x1FFFFFFUL << SCB_VTOR_TBLOFF_Pos) /*!< SCB VTOR: TBLOFF Mask */ - -/* SCB Application Interrupt and Reset Control Register Definitions */ -#define SCB_AIRCR_VECTKEY_Pos 16U /*!< SCB AIRCR: VECTKEY Position */ -#define SCB_AIRCR_VECTKEY_Msk (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos) /*!< SCB AIRCR: VECTKEY Mask */ - -#define SCB_AIRCR_VECTKEYSTAT_Pos 16U /*!< SCB AIRCR: VECTKEYSTAT Position */ -#define SCB_AIRCR_VECTKEYSTAT_Msk (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos) /*!< SCB AIRCR: VECTKEYSTAT Mask */ - -#define SCB_AIRCR_ENDIANESS_Pos 15U /*!< SCB AIRCR: ENDIANESS Position */ -#define SCB_AIRCR_ENDIANESS_Msk (1UL << SCB_AIRCR_ENDIANESS_Pos) /*!< SCB AIRCR: ENDIANESS Mask */ - -#define SCB_AIRCR_PRIS_Pos 14U /*!< SCB AIRCR: PRIS Position */ -#define SCB_AIRCR_PRIS_Msk (1UL << SCB_AIRCR_PRIS_Pos) /*!< SCB AIRCR: PRIS Mask */ - -#define SCB_AIRCR_BFHFNMINS_Pos 13U /*!< SCB AIRCR: BFHFNMINS Position */ -#define SCB_AIRCR_BFHFNMINS_Msk (1UL << SCB_AIRCR_BFHFNMINS_Pos) /*!< SCB AIRCR: BFHFNMINS Mask */ - -#define SCB_AIRCR_PRIGROUP_Pos 8U /*!< SCB AIRCR: PRIGROUP Position */ -#define SCB_AIRCR_PRIGROUP_Msk (7UL << SCB_AIRCR_PRIGROUP_Pos) /*!< SCB AIRCR: PRIGROUP Mask */ - -#define SCB_AIRCR_SYSRESETREQS_Pos 3U /*!< SCB AIRCR: SYSRESETREQS Position */ -#define SCB_AIRCR_SYSRESETREQS_Msk (1UL << SCB_AIRCR_SYSRESETREQS_Pos) /*!< SCB AIRCR: SYSRESETREQS Mask */ - -#define SCB_AIRCR_SYSRESETREQ_Pos 2U /*!< SCB AIRCR: SYSRESETREQ Position */ -#define SCB_AIRCR_SYSRESETREQ_Msk (1UL << SCB_AIRCR_SYSRESETREQ_Pos) /*!< SCB AIRCR: SYSRESETREQ Mask */ - -#define SCB_AIRCR_VECTCLRACTIVE_Pos 1U /*!< SCB AIRCR: VECTCLRACTIVE Position */ -#define SCB_AIRCR_VECTCLRACTIVE_Msk (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos) /*!< SCB AIRCR: VECTCLRACTIVE Mask */ - -/* SCB System Control Register Definitions */ -#define SCB_SCR_SEVONPEND_Pos 4U /*!< SCB SCR: SEVONPEND Position */ -#define SCB_SCR_SEVONPEND_Msk (1UL << SCB_SCR_SEVONPEND_Pos) /*!< SCB SCR: SEVONPEND Mask */ - -#define SCB_SCR_SLEEPDEEPS_Pos 3U /*!< SCB SCR: SLEEPDEEPS Position */ -#define SCB_SCR_SLEEPDEEPS_Msk (1UL << SCB_SCR_SLEEPDEEPS_Pos) /*!< SCB SCR: SLEEPDEEPS Mask */ - -#define SCB_SCR_SLEEPDEEP_Pos 2U /*!< SCB SCR: SLEEPDEEP Position */ -#define SCB_SCR_SLEEPDEEP_Msk (1UL << SCB_SCR_SLEEPDEEP_Pos) /*!< SCB SCR: SLEEPDEEP Mask */ - -#define SCB_SCR_SLEEPONEXIT_Pos 1U /*!< SCB SCR: SLEEPONEXIT Position */ -#define SCB_SCR_SLEEPONEXIT_Msk (1UL << SCB_SCR_SLEEPONEXIT_Pos) /*!< SCB SCR: SLEEPONEXIT Mask */ - -/* SCB Configuration Control Register Definitions */ -#define SCB_CCR_BP_Pos 18U /*!< SCB CCR: BP Position */ -#define SCB_CCR_BP_Msk (1UL << SCB_CCR_BP_Pos) /*!< SCB CCR: BP Mask */ - -#define SCB_CCR_IC_Pos 17U /*!< SCB CCR: IC Position */ -#define SCB_CCR_IC_Msk (1UL << SCB_CCR_IC_Pos) /*!< SCB CCR: IC Mask */ - -#define SCB_CCR_DC_Pos 16U /*!< SCB CCR: DC Position */ -#define SCB_CCR_DC_Msk (1UL << SCB_CCR_DC_Pos) /*!< SCB CCR: DC Mask */ - -#define SCB_CCR_STKOFHFNMIGN_Pos 10U /*!< SCB CCR: STKOFHFNMIGN Position */ -#define SCB_CCR_STKOFHFNMIGN_Msk (1UL << SCB_CCR_STKOFHFNMIGN_Pos) /*!< SCB CCR: STKOFHFNMIGN Mask */ - -#define SCB_CCR_BFHFNMIGN_Pos 8U /*!< SCB CCR: BFHFNMIGN Position */ -#define SCB_CCR_BFHFNMIGN_Msk (1UL << SCB_CCR_BFHFNMIGN_Pos) /*!< SCB CCR: BFHFNMIGN Mask */ - -#define SCB_CCR_DIV_0_TRP_Pos 4U /*!< SCB CCR: DIV_0_TRP Position */ -#define SCB_CCR_DIV_0_TRP_Msk (1UL << SCB_CCR_DIV_0_TRP_Pos) /*!< SCB CCR: DIV_0_TRP Mask */ - -#define SCB_CCR_UNALIGN_TRP_Pos 3U /*!< SCB CCR: UNALIGN_TRP Position */ -#define SCB_CCR_UNALIGN_TRP_Msk (1UL << SCB_CCR_UNALIGN_TRP_Pos) /*!< SCB CCR: UNALIGN_TRP Mask */ - -#define SCB_CCR_USERSETMPEND_Pos 1U /*!< SCB CCR: USERSETMPEND Position */ -#define SCB_CCR_USERSETMPEND_Msk (1UL << SCB_CCR_USERSETMPEND_Pos) /*!< SCB CCR: USERSETMPEND Mask */ - -/* SCB System Handler Control and State Register Definitions */ -#define SCB_SHCSR_HARDFAULTPENDED_Pos 21U /*!< SCB SHCSR: HARDFAULTPENDED Position */ -#define SCB_SHCSR_HARDFAULTPENDED_Msk (1UL << SCB_SHCSR_HARDFAULTPENDED_Pos) /*!< SCB SHCSR: HARDFAULTPENDED Mask */ - -#define SCB_SHCSR_SECUREFAULTPENDED_Pos 20U /*!< SCB SHCSR: SECUREFAULTPENDED Position */ -#define SCB_SHCSR_SECUREFAULTPENDED_Msk (1UL << SCB_SHCSR_SECUREFAULTPENDED_Pos) /*!< SCB SHCSR: SECUREFAULTPENDED Mask */ - -#define SCB_SHCSR_SECUREFAULTENA_Pos 19U /*!< SCB SHCSR: SECUREFAULTENA Position */ -#define SCB_SHCSR_SECUREFAULTENA_Msk (1UL << SCB_SHCSR_SECUREFAULTENA_Pos) /*!< SCB SHCSR: SECUREFAULTENA Mask */ - -#define SCB_SHCSR_USGFAULTENA_Pos 18U /*!< SCB SHCSR: USGFAULTENA Position */ -#define SCB_SHCSR_USGFAULTENA_Msk (1UL << SCB_SHCSR_USGFAULTENA_Pos) /*!< SCB SHCSR: USGFAULTENA Mask */ - -#define SCB_SHCSR_BUSFAULTENA_Pos 17U /*!< SCB SHCSR: BUSFAULTENA Position */ -#define SCB_SHCSR_BUSFAULTENA_Msk (1UL << SCB_SHCSR_BUSFAULTENA_Pos) /*!< SCB SHCSR: BUSFAULTENA Mask */ - -#define SCB_SHCSR_MEMFAULTENA_Pos 16U /*!< SCB SHCSR: MEMFAULTENA Position */ -#define SCB_SHCSR_MEMFAULTENA_Msk (1UL << SCB_SHCSR_MEMFAULTENA_Pos) /*!< SCB SHCSR: MEMFAULTENA Mask */ - -#define SCB_SHCSR_SVCALLPENDED_Pos 15U /*!< SCB SHCSR: SVCALLPENDED Position */ -#define SCB_SHCSR_SVCALLPENDED_Msk (1UL << SCB_SHCSR_SVCALLPENDED_Pos) /*!< SCB SHCSR: SVCALLPENDED Mask */ - -#define SCB_SHCSR_BUSFAULTPENDED_Pos 14U /*!< SCB SHCSR: BUSFAULTPENDED Position */ -#define SCB_SHCSR_BUSFAULTPENDED_Msk (1UL << SCB_SHCSR_BUSFAULTPENDED_Pos) /*!< SCB SHCSR: BUSFAULTPENDED Mask */ - -#define SCB_SHCSR_MEMFAULTPENDED_Pos 13U /*!< SCB SHCSR: MEMFAULTPENDED Position */ -#define SCB_SHCSR_MEMFAULTPENDED_Msk (1UL << SCB_SHCSR_MEMFAULTPENDED_Pos) /*!< SCB SHCSR: MEMFAULTPENDED Mask */ - -#define SCB_SHCSR_USGFAULTPENDED_Pos 12U /*!< SCB SHCSR: USGFAULTPENDED Position */ -#define SCB_SHCSR_USGFAULTPENDED_Msk (1UL << SCB_SHCSR_USGFAULTPENDED_Pos) /*!< SCB SHCSR: USGFAULTPENDED Mask */ - -#define SCB_SHCSR_SYSTICKACT_Pos 11U /*!< SCB SHCSR: SYSTICKACT Position */ -#define SCB_SHCSR_SYSTICKACT_Msk (1UL << SCB_SHCSR_SYSTICKACT_Pos) /*!< SCB SHCSR: SYSTICKACT Mask */ - -#define SCB_SHCSR_PENDSVACT_Pos 10U /*!< SCB SHCSR: PENDSVACT Position */ -#define SCB_SHCSR_PENDSVACT_Msk (1UL << SCB_SHCSR_PENDSVACT_Pos) /*!< SCB SHCSR: PENDSVACT Mask */ - -#define SCB_SHCSR_MONITORACT_Pos 8U /*!< SCB SHCSR: MONITORACT Position */ -#define SCB_SHCSR_MONITORACT_Msk (1UL << SCB_SHCSR_MONITORACT_Pos) /*!< SCB SHCSR: MONITORACT Mask */ - -#define SCB_SHCSR_SVCALLACT_Pos 7U /*!< SCB SHCSR: SVCALLACT Position */ -#define SCB_SHCSR_SVCALLACT_Msk (1UL << SCB_SHCSR_SVCALLACT_Pos) /*!< SCB SHCSR: SVCALLACT Mask */ - -#define SCB_SHCSR_NMIACT_Pos 5U /*!< SCB SHCSR: NMIACT Position */ -#define SCB_SHCSR_NMIACT_Msk (1UL << SCB_SHCSR_NMIACT_Pos) /*!< SCB SHCSR: NMIACT Mask */ - -#define SCB_SHCSR_SECUREFAULTACT_Pos 4U /*!< SCB SHCSR: SECUREFAULTACT Position */ -#define SCB_SHCSR_SECUREFAULTACT_Msk (1UL << SCB_SHCSR_SECUREFAULTACT_Pos) /*!< SCB SHCSR: SECUREFAULTACT Mask */ - -#define SCB_SHCSR_USGFAULTACT_Pos 3U /*!< SCB SHCSR: USGFAULTACT Position */ -#define SCB_SHCSR_USGFAULTACT_Msk (1UL << SCB_SHCSR_USGFAULTACT_Pos) /*!< SCB SHCSR: USGFAULTACT Mask */ - -#define SCB_SHCSR_HARDFAULTACT_Pos 2U /*!< SCB SHCSR: HARDFAULTACT Position */ -#define SCB_SHCSR_HARDFAULTACT_Msk (1UL << SCB_SHCSR_HARDFAULTACT_Pos) /*!< SCB SHCSR: HARDFAULTACT Mask */ - -#define SCB_SHCSR_BUSFAULTACT_Pos 1U /*!< SCB SHCSR: BUSFAULTACT Position */ -#define SCB_SHCSR_BUSFAULTACT_Msk (1UL << SCB_SHCSR_BUSFAULTACT_Pos) /*!< SCB SHCSR: BUSFAULTACT Mask */ - -#define SCB_SHCSR_MEMFAULTACT_Pos 0U /*!< SCB SHCSR: MEMFAULTACT Position */ -#define SCB_SHCSR_MEMFAULTACT_Msk (1UL /*<< SCB_SHCSR_MEMFAULTACT_Pos*/) /*!< SCB SHCSR: MEMFAULTACT Mask */ - -/* SCB Configurable Fault Status Register Definitions */ -#define SCB_CFSR_USGFAULTSR_Pos 16U /*!< SCB CFSR: Usage Fault Status Register Position */ -#define SCB_CFSR_USGFAULTSR_Msk (0xFFFFUL << SCB_CFSR_USGFAULTSR_Pos) /*!< SCB CFSR: Usage Fault Status Register Mask */ - -#define SCB_CFSR_BUSFAULTSR_Pos 8U /*!< SCB CFSR: Bus Fault Status Register Position */ -#define SCB_CFSR_BUSFAULTSR_Msk (0xFFUL << SCB_CFSR_BUSFAULTSR_Pos) /*!< SCB CFSR: Bus Fault Status Register Mask */ - -#define SCB_CFSR_MEMFAULTSR_Pos 0U /*!< SCB CFSR: Memory Manage Fault Status Register Position */ -#define SCB_CFSR_MEMFAULTSR_Msk (0xFFUL /*<< SCB_CFSR_MEMFAULTSR_Pos*/) /*!< SCB CFSR: Memory Manage Fault Status Register Mask */ - -/* MemManage Fault Status Register (part of SCB Configurable Fault Status Register) */ -#define SCB_CFSR_MMARVALID_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 7U) /*!< SCB CFSR (MMFSR): MMARVALID Position */ -#define SCB_CFSR_MMARVALID_Msk (1UL << SCB_CFSR_MMARVALID_Pos) /*!< SCB CFSR (MMFSR): MMARVALID Mask */ - -#define SCB_CFSR_MLSPERR_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 5U) /*!< SCB CFSR (MMFSR): MLSPERR Position */ -#define SCB_CFSR_MLSPERR_Msk (1UL << SCB_CFSR_MLSPERR_Pos) /*!< SCB CFSR (MMFSR): MLSPERR Mask */ - -#define SCB_CFSR_MSTKERR_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 4U) /*!< SCB CFSR (MMFSR): MSTKERR Position */ -#define SCB_CFSR_MSTKERR_Msk (1UL << SCB_CFSR_MSTKERR_Pos) /*!< SCB CFSR (MMFSR): MSTKERR Mask */ - -#define SCB_CFSR_MUNSTKERR_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 3U) /*!< SCB CFSR (MMFSR): MUNSTKERR Position */ -#define SCB_CFSR_MUNSTKERR_Msk (1UL << SCB_CFSR_MUNSTKERR_Pos) /*!< SCB CFSR (MMFSR): MUNSTKERR Mask */ - -#define SCB_CFSR_DACCVIOL_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 1U) /*!< SCB CFSR (MMFSR): DACCVIOL Position */ -#define SCB_CFSR_DACCVIOL_Msk (1UL << SCB_CFSR_DACCVIOL_Pos) /*!< SCB CFSR (MMFSR): DACCVIOL Mask */ - -#define SCB_CFSR_IACCVIOL_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 0U) /*!< SCB CFSR (MMFSR): IACCVIOL Position */ -#define SCB_CFSR_IACCVIOL_Msk (1UL /*<< SCB_CFSR_IACCVIOL_Pos*/) /*!< SCB CFSR (MMFSR): IACCVIOL Mask */ - -/* BusFault Status Register (part of SCB Configurable Fault Status Register) */ -#define SCB_CFSR_BFARVALID_Pos (SCB_CFSR_BUSFAULTSR_Pos + 7U) /*!< SCB CFSR (BFSR): BFARVALID Position */ -#define SCB_CFSR_BFARVALID_Msk (1UL << SCB_CFSR_BFARVALID_Pos) /*!< SCB CFSR (BFSR): BFARVALID Mask */ - -#define SCB_CFSR_LSPERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 5U) /*!< SCB CFSR (BFSR): LSPERR Position */ -#define SCB_CFSR_LSPERR_Msk (1UL << SCB_CFSR_LSPERR_Pos) /*!< SCB CFSR (BFSR): LSPERR Mask */ - -#define SCB_CFSR_STKERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 4U) /*!< SCB CFSR (BFSR): STKERR Position */ -#define SCB_CFSR_STKERR_Msk (1UL << SCB_CFSR_STKERR_Pos) /*!< SCB CFSR (BFSR): STKERR Mask */ - -#define SCB_CFSR_UNSTKERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 3U) /*!< SCB CFSR (BFSR): UNSTKERR Position */ -#define SCB_CFSR_UNSTKERR_Msk (1UL << SCB_CFSR_UNSTKERR_Pos) /*!< SCB CFSR (BFSR): UNSTKERR Mask */ - -#define SCB_CFSR_IMPRECISERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 2U) /*!< SCB CFSR (BFSR): IMPRECISERR Position */ -#define SCB_CFSR_IMPRECISERR_Msk (1UL << SCB_CFSR_IMPRECISERR_Pos) /*!< SCB CFSR (BFSR): IMPRECISERR Mask */ - -#define SCB_CFSR_PRECISERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 1U) /*!< SCB CFSR (BFSR): PRECISERR Position */ -#define SCB_CFSR_PRECISERR_Msk (1UL << SCB_CFSR_PRECISERR_Pos) /*!< SCB CFSR (BFSR): PRECISERR Mask */ - -#define SCB_CFSR_IBUSERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 0U) /*!< SCB CFSR (BFSR): IBUSERR Position */ -#define SCB_CFSR_IBUSERR_Msk (1UL << SCB_CFSR_IBUSERR_Pos) /*!< SCB CFSR (BFSR): IBUSERR Mask */ - -/* UsageFault Status Register (part of SCB Configurable Fault Status Register) */ -#define SCB_CFSR_DIVBYZERO_Pos (SCB_CFSR_USGFAULTSR_Pos + 9U) /*!< SCB CFSR (UFSR): DIVBYZERO Position */ -#define SCB_CFSR_DIVBYZERO_Msk (1UL << SCB_CFSR_DIVBYZERO_Pos) /*!< SCB CFSR (UFSR): DIVBYZERO Mask */ - -#define SCB_CFSR_UNALIGNED_Pos (SCB_CFSR_USGFAULTSR_Pos + 8U) /*!< SCB CFSR (UFSR): UNALIGNED Position */ -#define SCB_CFSR_UNALIGNED_Msk (1UL << SCB_CFSR_UNALIGNED_Pos) /*!< SCB CFSR (UFSR): UNALIGNED Mask */ - -#define SCB_CFSR_STKOF_Pos (SCB_CFSR_USGFAULTSR_Pos + 4U) /*!< SCB CFSR (UFSR): STKOF Position */ -#define SCB_CFSR_STKOF_Msk (1UL << SCB_CFSR_STKOF_Pos) /*!< SCB CFSR (UFSR): STKOF Mask */ - -#define SCB_CFSR_NOCP_Pos (SCB_CFSR_USGFAULTSR_Pos + 3U) /*!< SCB CFSR (UFSR): NOCP Position */ -#define SCB_CFSR_NOCP_Msk (1UL << SCB_CFSR_NOCP_Pos) /*!< SCB CFSR (UFSR): NOCP Mask */ - -#define SCB_CFSR_INVPC_Pos (SCB_CFSR_USGFAULTSR_Pos + 2U) /*!< SCB CFSR (UFSR): INVPC Position */ -#define SCB_CFSR_INVPC_Msk (1UL << SCB_CFSR_INVPC_Pos) /*!< SCB CFSR (UFSR): INVPC Mask */ - -#define SCB_CFSR_INVSTATE_Pos (SCB_CFSR_USGFAULTSR_Pos + 1U) /*!< SCB CFSR (UFSR): INVSTATE Position */ -#define SCB_CFSR_INVSTATE_Msk (1UL << SCB_CFSR_INVSTATE_Pos) /*!< SCB CFSR (UFSR): INVSTATE Mask */ - -#define SCB_CFSR_UNDEFINSTR_Pos (SCB_CFSR_USGFAULTSR_Pos + 0U) /*!< SCB CFSR (UFSR): UNDEFINSTR Position */ -#define SCB_CFSR_UNDEFINSTR_Msk (1UL << SCB_CFSR_UNDEFINSTR_Pos) /*!< SCB CFSR (UFSR): UNDEFINSTR Mask */ - -/* SCB Hard Fault Status Register Definitions */ -#define SCB_HFSR_DEBUGEVT_Pos 31U /*!< SCB HFSR: DEBUGEVT Position */ -#define SCB_HFSR_DEBUGEVT_Msk (1UL << SCB_HFSR_DEBUGEVT_Pos) /*!< SCB HFSR: DEBUGEVT Mask */ - -#define SCB_HFSR_FORCED_Pos 30U /*!< SCB HFSR: FORCED Position */ -#define SCB_HFSR_FORCED_Msk (1UL << SCB_HFSR_FORCED_Pos) /*!< SCB HFSR: FORCED Mask */ - -#define SCB_HFSR_VECTTBL_Pos 1U /*!< SCB HFSR: VECTTBL Position */ -#define SCB_HFSR_VECTTBL_Msk (1UL << SCB_HFSR_VECTTBL_Pos) /*!< SCB HFSR: VECTTBL Mask */ - -/* SCB Debug Fault Status Register Definitions */ -#define SCB_DFSR_EXTERNAL_Pos 4U /*!< SCB DFSR: EXTERNAL Position */ -#define SCB_DFSR_EXTERNAL_Msk (1UL << SCB_DFSR_EXTERNAL_Pos) /*!< SCB DFSR: EXTERNAL Mask */ - -#define SCB_DFSR_VCATCH_Pos 3U /*!< SCB DFSR: VCATCH Position */ -#define SCB_DFSR_VCATCH_Msk (1UL << SCB_DFSR_VCATCH_Pos) /*!< SCB DFSR: VCATCH Mask */ - -#define SCB_DFSR_DWTTRAP_Pos 2U /*!< SCB DFSR: DWTTRAP Position */ -#define SCB_DFSR_DWTTRAP_Msk (1UL << SCB_DFSR_DWTTRAP_Pos) /*!< SCB DFSR: DWTTRAP Mask */ - -#define SCB_DFSR_BKPT_Pos 1U /*!< SCB DFSR: BKPT Position */ -#define SCB_DFSR_BKPT_Msk (1UL << SCB_DFSR_BKPT_Pos) /*!< SCB DFSR: BKPT Mask */ - -#define SCB_DFSR_HALTED_Pos 0U /*!< SCB DFSR: HALTED Position */ -#define SCB_DFSR_HALTED_Msk (1UL /*<< SCB_DFSR_HALTED_Pos*/) /*!< SCB DFSR: HALTED Mask */ - -/* SCB Non-Secure Access Control Register Definitions */ -#define SCB_NSACR_CP11_Pos 11U /*!< SCB NSACR: CP11 Position */ -#define SCB_NSACR_CP11_Msk (1UL << SCB_NSACR_CP11_Pos) /*!< SCB NSACR: CP11 Mask */ - -#define SCB_NSACR_CP10_Pos 10U /*!< SCB NSACR: CP10 Position */ -#define SCB_NSACR_CP10_Msk (1UL << SCB_NSACR_CP10_Pos) /*!< SCB NSACR: CP10 Mask */ - -#define SCB_NSACR_CPn_Pos 0U /*!< SCB NSACR: CPn Position */ -#define SCB_NSACR_CPn_Msk (1UL /*<< SCB_NSACR_CPn_Pos*/) /*!< SCB NSACR: CPn Mask */ - -/* SCB Cache Level ID Register Definitions */ -#define SCB_CLIDR_LOUU_Pos 27U /*!< SCB CLIDR: LoUU Position */ -#define SCB_CLIDR_LOUU_Msk (7UL << SCB_CLIDR_LOUU_Pos) /*!< SCB CLIDR: LoUU Mask */ - -#define SCB_CLIDR_LOC_Pos 24U /*!< SCB CLIDR: LoC Position */ -#define SCB_CLIDR_LOC_Msk (7UL << SCB_CLIDR_LOC_Pos) /*!< SCB CLIDR: LoC Mask */ - -/* SCB Cache Type Register Definitions */ -#define SCB_CTR_FORMAT_Pos 29U /*!< SCB CTR: Format Position */ -#define SCB_CTR_FORMAT_Msk (7UL << SCB_CTR_FORMAT_Pos) /*!< SCB CTR: Format Mask */ - -#define SCB_CTR_CWG_Pos 24U /*!< SCB CTR: CWG Position */ -#define SCB_CTR_CWG_Msk (0xFUL << SCB_CTR_CWG_Pos) /*!< SCB CTR: CWG Mask */ - -#define SCB_CTR_ERG_Pos 20U /*!< SCB CTR: ERG Position */ -#define SCB_CTR_ERG_Msk (0xFUL << SCB_CTR_ERG_Pos) /*!< SCB CTR: ERG Mask */ - -#define SCB_CTR_DMINLINE_Pos 16U /*!< SCB CTR: DminLine Position */ -#define SCB_CTR_DMINLINE_Msk (0xFUL << SCB_CTR_DMINLINE_Pos) /*!< SCB CTR: DminLine Mask */ - -#define SCB_CTR_IMINLINE_Pos 0U /*!< SCB CTR: ImInLine Position */ -#define SCB_CTR_IMINLINE_Msk (0xFUL /*<< SCB_CTR_IMINLINE_Pos*/) /*!< SCB CTR: ImInLine Mask */ - -/* SCB Cache Size ID Register Definitions */ -#define SCB_CCSIDR_WT_Pos 31U /*!< SCB CCSIDR: WT Position */ -#define SCB_CCSIDR_WT_Msk (1UL << SCB_CCSIDR_WT_Pos) /*!< SCB CCSIDR: WT Mask */ - -#define SCB_CCSIDR_WB_Pos 30U /*!< SCB CCSIDR: WB Position */ -#define SCB_CCSIDR_WB_Msk (1UL << SCB_CCSIDR_WB_Pos) /*!< SCB CCSIDR: WB Mask */ - -#define SCB_CCSIDR_RA_Pos 29U /*!< SCB CCSIDR: RA Position */ -#define SCB_CCSIDR_RA_Msk (1UL << SCB_CCSIDR_RA_Pos) /*!< SCB CCSIDR: RA Mask */ - -#define SCB_CCSIDR_WA_Pos 28U /*!< SCB CCSIDR: WA Position */ -#define SCB_CCSIDR_WA_Msk (1UL << SCB_CCSIDR_WA_Pos) /*!< SCB CCSIDR: WA Mask */ - -#define SCB_CCSIDR_NUMSETS_Pos 13U /*!< SCB CCSIDR: NumSets Position */ -#define SCB_CCSIDR_NUMSETS_Msk (0x7FFFUL << SCB_CCSIDR_NUMSETS_Pos) /*!< SCB CCSIDR: NumSets Mask */ - -#define SCB_CCSIDR_ASSOCIATIVITY_Pos 3U /*!< SCB CCSIDR: Associativity Position */ -#define SCB_CCSIDR_ASSOCIATIVITY_Msk (0x3FFUL << SCB_CCSIDR_ASSOCIATIVITY_Pos) /*!< SCB CCSIDR: Associativity Mask */ - -#define SCB_CCSIDR_LINESIZE_Pos 0U /*!< SCB CCSIDR: LineSize Position */ -#define SCB_CCSIDR_LINESIZE_Msk (7UL /*<< SCB_CCSIDR_LINESIZE_Pos*/) /*!< SCB CCSIDR: LineSize Mask */ - -/* SCB Cache Size Selection Register Definitions */ -#define SCB_CSSELR_LEVEL_Pos 1U /*!< SCB CSSELR: Level Position */ -#define SCB_CSSELR_LEVEL_Msk (7UL << SCB_CSSELR_LEVEL_Pos) /*!< SCB CSSELR: Level Mask */ - -#define SCB_CSSELR_IND_Pos 0U /*!< SCB CSSELR: InD Position */ -#define SCB_CSSELR_IND_Msk (1UL /*<< SCB_CSSELR_IND_Pos*/) /*!< SCB CSSELR: InD Mask */ - -/* SCB Software Triggered Interrupt Register Definitions */ -#define SCB_STIR_INTID_Pos 0U /*!< SCB STIR: INTID Position */ -#define SCB_STIR_INTID_Msk (0x1FFUL /*<< SCB_STIR_INTID_Pos*/) /*!< SCB STIR: INTID Mask */ - -/* SCB D-Cache Invalidate by Set-way Register Definitions */ -#define SCB_DCISW_WAY_Pos 30U /*!< SCB DCISW: Way Position */ -#define SCB_DCISW_WAY_Msk (3UL << SCB_DCISW_WAY_Pos) /*!< SCB DCISW: Way Mask */ - -#define SCB_DCISW_SET_Pos 5U /*!< SCB DCISW: Set Position */ -#define SCB_DCISW_SET_Msk (0x1FFUL << SCB_DCISW_SET_Pos) /*!< SCB DCISW: Set Mask */ - -/* SCB D-Cache Clean by Set-way Register Definitions */ -#define SCB_DCCSW_WAY_Pos 30U /*!< SCB DCCSW: Way Position */ -#define SCB_DCCSW_WAY_Msk (3UL << SCB_DCCSW_WAY_Pos) /*!< SCB DCCSW: Way Mask */ - -#define SCB_DCCSW_SET_Pos 5U /*!< SCB DCCSW: Set Position */ -#define SCB_DCCSW_SET_Msk (0x1FFUL << SCB_DCCSW_SET_Pos) /*!< SCB DCCSW: Set Mask */ - -/* SCB D-Cache Clean and Invalidate by Set-way Register Definitions */ -#define SCB_DCCISW_WAY_Pos 30U /*!< SCB DCCISW: Way Position */ -#define SCB_DCCISW_WAY_Msk (3UL << SCB_DCCISW_WAY_Pos) /*!< SCB DCCISW: Way Mask */ - -#define SCB_DCCISW_SET_Pos 5U /*!< SCB DCCISW: Set Position */ -#define SCB_DCCISW_SET_Msk (0x1FFUL << SCB_DCCISW_SET_Pos) /*!< SCB DCCISW: Set Mask */ - -/* Instruction Tightly-Coupled Memory Control Register Definitions */ -#define SCB_ITCMCR_SZ_Pos 3U /*!< SCB ITCMCR: SZ Position */ -#define SCB_ITCMCR_SZ_Msk (0xFUL << SCB_ITCMCR_SZ_Pos) /*!< SCB ITCMCR: SZ Mask */ - -#define SCB_ITCMCR_RETEN_Pos 2U /*!< SCB ITCMCR: RETEN Position */ -#define SCB_ITCMCR_RETEN_Msk (1UL << SCB_ITCMCR_RETEN_Pos) /*!< SCB ITCMCR: RETEN Mask */ - -#define SCB_ITCMCR_RMW_Pos 1U /*!< SCB ITCMCR: RMW Position */ -#define SCB_ITCMCR_RMW_Msk (1UL << SCB_ITCMCR_RMW_Pos) /*!< SCB ITCMCR: RMW Mask */ - -#define SCB_ITCMCR_EN_Pos 0U /*!< SCB ITCMCR: EN Position */ -#define SCB_ITCMCR_EN_Msk (1UL /*<< SCB_ITCMCR_EN_Pos*/) /*!< SCB ITCMCR: EN Mask */ - -/* Data Tightly-Coupled Memory Control Register Definitions */ -#define SCB_DTCMCR_SZ_Pos 3U /*!< SCB DTCMCR: SZ Position */ -#define SCB_DTCMCR_SZ_Msk (0xFUL << SCB_DTCMCR_SZ_Pos) /*!< SCB DTCMCR: SZ Mask */ - -#define SCB_DTCMCR_RETEN_Pos 2U /*!< SCB DTCMCR: RETEN Position */ -#define SCB_DTCMCR_RETEN_Msk (1UL << SCB_DTCMCR_RETEN_Pos) /*!< SCB DTCMCR: RETEN Mask */ - -#define SCB_DTCMCR_RMW_Pos 1U /*!< SCB DTCMCR: RMW Position */ -#define SCB_DTCMCR_RMW_Msk (1UL << SCB_DTCMCR_RMW_Pos) /*!< SCB DTCMCR: RMW Mask */ - -#define SCB_DTCMCR_EN_Pos 0U /*!< SCB DTCMCR: EN Position */ -#define SCB_DTCMCR_EN_Msk (1UL /*<< SCB_DTCMCR_EN_Pos*/) /*!< SCB DTCMCR: EN Mask */ - -/* AHBP Control Register Definitions */ -#define SCB_AHBPCR_SZ_Pos 1U /*!< SCB AHBPCR: SZ Position */ -#define SCB_AHBPCR_SZ_Msk (7UL << SCB_AHBPCR_SZ_Pos) /*!< SCB AHBPCR: SZ Mask */ - -#define SCB_AHBPCR_EN_Pos 0U /*!< SCB AHBPCR: EN Position */ -#define SCB_AHBPCR_EN_Msk (1UL /*<< SCB_AHBPCR_EN_Pos*/) /*!< SCB AHBPCR: EN Mask */ - -/* L1 Cache Control Register Definitions */ -#define SCB_CACR_FORCEWT_Pos 2U /*!< SCB CACR: FORCEWT Position */ -#define SCB_CACR_FORCEWT_Msk (1UL << SCB_CACR_FORCEWT_Pos) /*!< SCB CACR: FORCEWT Mask */ - -#define SCB_CACR_ECCEN_Pos 1U /*!< SCB CACR: ECCEN Position */ -#define SCB_CACR_ECCEN_Msk (1UL << SCB_CACR_ECCEN_Pos) /*!< SCB CACR: ECCEN Mask */ - -#define SCB_CACR_SIWT_Pos 0U /*!< SCB CACR: SIWT Position */ -#define SCB_CACR_SIWT_Msk (1UL /*<< SCB_CACR_SIWT_Pos*/) /*!< SCB CACR: SIWT Mask */ - -/* AHBS Control Register Definitions */ -#define SCB_AHBSCR_INITCOUNT_Pos 11U /*!< SCB AHBSCR: INITCOUNT Position */ -#define SCB_AHBSCR_INITCOUNT_Msk (0x1FUL << SCB_AHBPCR_INITCOUNT_Pos) /*!< SCB AHBSCR: INITCOUNT Mask */ - -#define SCB_AHBSCR_TPRI_Pos 2U /*!< SCB AHBSCR: TPRI Position */ -#define SCB_AHBSCR_TPRI_Msk (0x1FFUL << SCB_AHBPCR_TPRI_Pos) /*!< SCB AHBSCR: TPRI Mask */ - -#define SCB_AHBSCR_CTL_Pos 0U /*!< SCB AHBSCR: CTL Position*/ -#define SCB_AHBSCR_CTL_Msk (3UL /*<< SCB_AHBPCR_CTL_Pos*/) /*!< SCB AHBSCR: CTL Mask */ - -/* Auxiliary Bus Fault Status Register Definitions */ -#define SCB_ABFSR_AXIMTYPE_Pos 8U /*!< SCB ABFSR: AXIMTYPE Position*/ -#define SCB_ABFSR_AXIMTYPE_Msk (3UL << SCB_ABFSR_AXIMTYPE_Pos) /*!< SCB ABFSR: AXIMTYPE Mask */ - -#define SCB_ABFSR_EPPB_Pos 4U /*!< SCB ABFSR: EPPB Position*/ -#define SCB_ABFSR_EPPB_Msk (1UL << SCB_ABFSR_EPPB_Pos) /*!< SCB ABFSR: EPPB Mask */ - -#define SCB_ABFSR_AXIM_Pos 3U /*!< SCB ABFSR: AXIM Position*/ -#define SCB_ABFSR_AXIM_Msk (1UL << SCB_ABFSR_AXIM_Pos) /*!< SCB ABFSR: AXIM Mask */ - -#define SCB_ABFSR_AHBP_Pos 2U /*!< SCB ABFSR: AHBP Position*/ -#define SCB_ABFSR_AHBP_Msk (1UL << SCB_ABFSR_AHBP_Pos) /*!< SCB ABFSR: AHBP Mask */ - -#define SCB_ABFSR_DTCM_Pos 1U /*!< SCB ABFSR: DTCM Position*/ -#define SCB_ABFSR_DTCM_Msk (1UL << SCB_ABFSR_DTCM_Pos) /*!< SCB ABFSR: DTCM Mask */ - -#define SCB_ABFSR_ITCM_Pos 0U /*!< SCB ABFSR: ITCM Position*/ -#define SCB_ABFSR_ITCM_Msk (1UL /*<< SCB_ABFSR_ITCM_Pos*/) /*!< SCB ABFSR: ITCM Mask */ - -/*@} end of group CMSIS_SCB */ - - -/** - \ingroup CMSIS_core_register - \defgroup CMSIS_SCnSCB System Controls not in SCB (SCnSCB) - \brief Type definitions for the System Control and ID Register not in the SCB - @{ - */ - -/** - \brief Structure type to access the System Control and ID Register not in the SCB. - */ -typedef struct -{ - uint32_t RESERVED0[1U]; - __IM uint32_t ICTR; /*!< Offset: 0x004 (R/ ) Interrupt Controller Type Register */ - __IOM uint32_t ACTLR; /*!< Offset: 0x008 (R/W) Auxiliary Control Register */ - __IOM uint32_t CPPWR; /*!< Offset: 0x00C (R/W) Coprocessor Power Control Register */ -} SCnSCB_Type; - -/* Interrupt Controller Type Register Definitions */ -#define SCnSCB_ICTR_INTLINESNUM_Pos 0U /*!< ICTR: INTLINESNUM Position */ -#define SCnSCB_ICTR_INTLINESNUM_Msk (0xFUL /*<< SCnSCB_ICTR_INTLINESNUM_Pos*/) /*!< ICTR: INTLINESNUM Mask */ - -/*@} end of group CMSIS_SCnotSCB */ - - -/** - \ingroup CMSIS_core_register - \defgroup CMSIS_SysTick System Tick Timer (SysTick) - \brief Type definitions for the System Timer Registers. - @{ - */ - -/** - \brief Structure type to access the System Timer (SysTick). - */ -typedef struct -{ - __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) SysTick Control and Status Register */ - __IOM uint32_t LOAD; /*!< Offset: 0x004 (R/W) SysTick Reload Value Register */ - __IOM uint32_t VAL; /*!< Offset: 0x008 (R/W) SysTick Current Value Register */ - __IM uint32_t CALIB; /*!< Offset: 0x00C (R/ ) SysTick Calibration Register */ -} SysTick_Type; - -/* SysTick Control / Status Register Definitions */ -#define SysTick_CTRL_COUNTFLAG_Pos 16U /*!< SysTick CTRL: COUNTFLAG Position */ -#define SysTick_CTRL_COUNTFLAG_Msk (1UL << SysTick_CTRL_COUNTFLAG_Pos) /*!< SysTick CTRL: COUNTFLAG Mask */ - -#define SysTick_CTRL_CLKSOURCE_Pos 2U /*!< SysTick CTRL: CLKSOURCE Position */ -#define SysTick_CTRL_CLKSOURCE_Msk (1UL << SysTick_CTRL_CLKSOURCE_Pos) /*!< SysTick CTRL: CLKSOURCE Mask */ - -#define SysTick_CTRL_TICKINT_Pos 1U /*!< SysTick CTRL: TICKINT Position */ -#define SysTick_CTRL_TICKINT_Msk (1UL << SysTick_CTRL_TICKINT_Pos) /*!< SysTick CTRL: TICKINT Mask */ - -#define SysTick_CTRL_ENABLE_Pos 0U /*!< SysTick CTRL: ENABLE Position */ -#define SysTick_CTRL_ENABLE_Msk (1UL /*<< SysTick_CTRL_ENABLE_Pos*/) /*!< SysTick CTRL: ENABLE Mask */ - -/* SysTick Reload Register Definitions */ -#define SysTick_LOAD_RELOAD_Pos 0U /*!< SysTick LOAD: RELOAD Position */ -#define SysTick_LOAD_RELOAD_Msk (0xFFFFFFUL /*<< SysTick_LOAD_RELOAD_Pos*/) /*!< SysTick LOAD: RELOAD Mask */ - -/* SysTick Current Register Definitions */ -#define SysTick_VAL_CURRENT_Pos 0U /*!< SysTick VAL: CURRENT Position */ -#define SysTick_VAL_CURRENT_Msk (0xFFFFFFUL /*<< SysTick_VAL_CURRENT_Pos*/) /*!< SysTick VAL: CURRENT Mask */ - -/* SysTick Calibration Register Definitions */ -#define SysTick_CALIB_NOREF_Pos 31U /*!< SysTick CALIB: NOREF Position */ -#define SysTick_CALIB_NOREF_Msk (1UL << SysTick_CALIB_NOREF_Pos) /*!< SysTick CALIB: NOREF Mask */ - -#define SysTick_CALIB_SKEW_Pos 30U /*!< SysTick CALIB: SKEW Position */ -#define SysTick_CALIB_SKEW_Msk (1UL << SysTick_CALIB_SKEW_Pos) /*!< SysTick CALIB: SKEW Mask */ - -#define SysTick_CALIB_TENMS_Pos 0U /*!< SysTick CALIB: TENMS Position */ -#define SysTick_CALIB_TENMS_Msk (0xFFFFFFUL /*<< SysTick_CALIB_TENMS_Pos*/) /*!< SysTick CALIB: TENMS Mask */ - -/*@} end of group CMSIS_SysTick */ - - -/** - \ingroup CMSIS_core_register - \defgroup CMSIS_ITM Instrumentation Trace Macrocell (ITM) - \brief Type definitions for the Instrumentation Trace Macrocell (ITM) - @{ - */ - -/** - \brief Structure type to access the Instrumentation Trace Macrocell Register (ITM). - */ -typedef struct -{ - __OM union - { - __OM uint8_t u8; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 8-bit */ - __OM uint16_t u16; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 16-bit */ - __OM uint32_t u32; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 32-bit */ - } PORT [32U]; /*!< Offset: 0x000 ( /W) ITM Stimulus Port Registers */ - uint32_t RESERVED0[864U]; - __IOM uint32_t TER; /*!< Offset: 0xE00 (R/W) ITM Trace Enable Register */ - uint32_t RESERVED1[15U]; - __IOM uint32_t TPR; /*!< Offset: 0xE40 (R/W) ITM Trace Privilege Register */ - uint32_t RESERVED2[15U]; - __IOM uint32_t TCR; /*!< Offset: 0xE80 (R/W) ITM Trace Control Register */ - uint32_t RESERVED3[29U]; - __OM uint32_t IWR; /*!< Offset: 0xEF8 ( /W) ITM Integration Write Register */ - __IM uint32_t IRR; /*!< Offset: 0xEFC (R/ ) ITM Integration Read Register */ - __IOM uint32_t IMCR; /*!< Offset: 0xF00 (R/W) ITM Integration Mode Control Register */ - uint32_t RESERVED4[43U]; - __OM uint32_t LAR; /*!< Offset: 0xFB0 ( /W) ITM Lock Access Register */ - __IM uint32_t LSR; /*!< Offset: 0xFB4 (R/ ) ITM Lock Status Register */ - uint32_t RESERVED5[1U]; - __IM uint32_t DEVARCH; /*!< Offset: 0xFBC (R/ ) ITM Device Architecture Register */ - uint32_t RESERVED6[4U]; - __IM uint32_t PID4; /*!< Offset: 0xFD0 (R/ ) ITM Peripheral Identification Register #4 */ - __IM uint32_t PID5; /*!< Offset: 0xFD4 (R/ ) ITM Peripheral Identification Register #5 */ - __IM uint32_t PID6; /*!< Offset: 0xFD8 (R/ ) ITM Peripheral Identification Register #6 */ - __IM uint32_t PID7; /*!< Offset: 0xFDC (R/ ) ITM Peripheral Identification Register #7 */ - __IM uint32_t PID0; /*!< Offset: 0xFE0 (R/ ) ITM Peripheral Identification Register #0 */ - __IM uint32_t PID1; /*!< Offset: 0xFE4 (R/ ) ITM Peripheral Identification Register #1 */ - __IM uint32_t PID2; /*!< Offset: 0xFE8 (R/ ) ITM Peripheral Identification Register #2 */ - __IM uint32_t PID3; /*!< Offset: 0xFEC (R/ ) ITM Peripheral Identification Register #3 */ - __IM uint32_t CID0; /*!< Offset: 0xFF0 (R/ ) ITM Component Identification Register #0 */ - __IM uint32_t CID1; /*!< Offset: 0xFF4 (R/ ) ITM Component Identification Register #1 */ - __IM uint32_t CID2; /*!< Offset: 0xFF8 (R/ ) ITM Component Identification Register #2 */ - __IM uint32_t CID3; /*!< Offset: 0xFFC (R/ ) ITM Component Identification Register #3 */ -} ITM_Type; - -/* ITM Stimulus Port Register Definitions */ -#define ITM_STIM_DISABLED_Pos 1U /*!< ITM STIM: DISABLED Position */ -#define ITM_STIM_DISABLED_Msk (0x1UL << ITM_STIM_DISABLED_Pos) /*!< ITM STIM: DISABLED Mask */ - -#define ITM_STIM_FIFOREADY_Pos 0U /*!< ITM STIM: FIFOREADY Position */ -#define ITM_STIM_FIFOREADY_Msk (0x1UL /*<< ITM_STIM_FIFOREADY_Pos*/) /*!< ITM STIM: FIFOREADY Mask */ - -/* ITM Trace Privilege Register Definitions */ -#define ITM_TPR_PRIVMASK_Pos 0U /*!< ITM TPR: PRIVMASK Position */ -#define ITM_TPR_PRIVMASK_Msk (0xFUL /*<< ITM_TPR_PRIVMASK_Pos*/) /*!< ITM TPR: PRIVMASK Mask */ - -/* ITM Trace Control Register Definitions */ -#define ITM_TCR_BUSY_Pos 23U /*!< ITM TCR: BUSY Position */ -#define ITM_TCR_BUSY_Msk (1UL << ITM_TCR_BUSY_Pos) /*!< ITM TCR: BUSY Mask */ - -#define ITM_TCR_TRACEBUSID_Pos 16U /*!< ITM TCR: ATBID Position */ -#define ITM_TCR_TRACEBUSID_Msk (0x7FUL << ITM_TCR_TRACEBUSID_Pos) /*!< ITM TCR: ATBID Mask */ - -#define ITM_TCR_GTSFREQ_Pos 10U /*!< ITM TCR: Global timestamp frequency Position */ -#define ITM_TCR_GTSFREQ_Msk (3UL << ITM_TCR_GTSFREQ_Pos) /*!< ITM TCR: Global timestamp frequency Mask */ - -#define ITM_TCR_TSPRESCALE_Pos 8U /*!< ITM TCR: TSPRESCALE Position */ -#define ITM_TCR_TSPRESCALE_Msk (3UL << ITM_TCR_TSPRESCALE_Pos) /*!< ITM TCR: TSPRESCALE Mask */ - -#define ITM_TCR_STALLENA_Pos 5U /*!< ITM TCR: STALLENA Position */ -#define ITM_TCR_STALLENA_Msk (1UL << ITM_TCR_STALLENA_Pos) /*!< ITM TCR: STALLENA Mask */ - -#define ITM_TCR_SWOENA_Pos 4U /*!< ITM TCR: SWOENA Position */ -#define ITM_TCR_SWOENA_Msk (1UL << ITM_TCR_SWOENA_Pos) /*!< ITM TCR: SWOENA Mask */ - -#define ITM_TCR_DWTENA_Pos 3U /*!< ITM TCR: DWTENA Position */ -#define ITM_TCR_DWTENA_Msk (1UL << ITM_TCR_DWTENA_Pos) /*!< ITM TCR: DWTENA Mask */ - -#define ITM_TCR_SYNCENA_Pos 2U /*!< ITM TCR: SYNCENA Position */ -#define ITM_TCR_SYNCENA_Msk (1UL << ITM_TCR_SYNCENA_Pos) /*!< ITM TCR: SYNCENA Mask */ - -#define ITM_TCR_TSENA_Pos 1U /*!< ITM TCR: TSENA Position */ -#define ITM_TCR_TSENA_Msk (1UL << ITM_TCR_TSENA_Pos) /*!< ITM TCR: TSENA Mask */ - -#define ITM_TCR_ITMENA_Pos 0U /*!< ITM TCR: ITM Enable bit Position */ -#define ITM_TCR_ITMENA_Msk (1UL /*<< ITM_TCR_ITMENA_Pos*/) /*!< ITM TCR: ITM Enable bit Mask */ - -/* ITM Integration Write Register Definitions */ -#define ITM_IWR_ATVALIDM_Pos 0U /*!< ITM IWR: ATVALIDM Position */ -#define ITM_IWR_ATVALIDM_Msk (1UL /*<< ITM_IWR_ATVALIDM_Pos*/) /*!< ITM IWR: ATVALIDM Mask */ - -/* ITM Integration Read Register Definitions */ -#define ITM_IRR_ATREADYM_Pos 0U /*!< ITM IRR: ATREADYM Position */ -#define ITM_IRR_ATREADYM_Msk (1UL /*<< ITM_IRR_ATREADYM_Pos*/) /*!< ITM IRR: ATREADYM Mask */ - -/* ITM Integration Mode Control Register Definitions */ -#define ITM_IMCR_INTEGRATION_Pos 0U /*!< ITM IMCR: INTEGRATION Position */ -#define ITM_IMCR_INTEGRATION_Msk (1UL /*<< ITM_IMCR_INTEGRATION_Pos*/) /*!< ITM IMCR: INTEGRATION Mask */ - -/* ITM Lock Status Register Definitions */ -#define ITM_LSR_ByteAcc_Pos 2U /*!< ITM LSR: ByteAcc Position */ -#define ITM_LSR_ByteAcc_Msk (1UL << ITM_LSR_ByteAcc_Pos) /*!< ITM LSR: ByteAcc Mask */ - -#define ITM_LSR_Access_Pos 1U /*!< ITM LSR: Access Position */ -#define ITM_LSR_Access_Msk (1UL << ITM_LSR_Access_Pos) /*!< ITM LSR: Access Mask */ - -#define ITM_LSR_Present_Pos 0U /*!< ITM LSR: Present Position */ -#define ITM_LSR_Present_Msk (1UL /*<< ITM_LSR_Present_Pos*/) /*!< ITM LSR: Present Mask */ - -/*@}*/ /* end of group CMSIS_ITM */ - - -/** - \ingroup CMSIS_core_register - \defgroup CMSIS_DWT Data Watchpoint and Trace (DWT) - \brief Type definitions for the Data Watchpoint and Trace (DWT) - @{ - */ - -/** - \brief Structure type to access the Data Watchpoint and Trace Register (DWT). - */ -typedef struct -{ - __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) Control Register */ - __IOM uint32_t CYCCNT; /*!< Offset: 0x004 (R/W) Cycle Count Register */ - __IOM uint32_t CPICNT; /*!< Offset: 0x008 (R/W) CPI Count Register */ - __IOM uint32_t EXCCNT; /*!< Offset: 0x00C (R/W) Exception Overhead Count Register */ - __IOM uint32_t SLEEPCNT; /*!< Offset: 0x010 (R/W) Sleep Count Register */ - __IOM uint32_t LSUCNT; /*!< Offset: 0x014 (R/W) LSU Count Register */ - __IOM uint32_t FOLDCNT; /*!< Offset: 0x018 (R/W) Folded-instruction Count Register */ - __IM uint32_t PCSR; /*!< Offset: 0x01C (R/ ) Program Counter Sample Register */ - __IOM uint32_t COMP0; /*!< Offset: 0x020 (R/W) Comparator Register 0 */ - uint32_t RESERVED1[1U]; - __IOM uint32_t FUNCTION0; /*!< Offset: 0x028 (R/W) Function Register 0 */ - uint32_t RESERVED2[1U]; - __IOM uint32_t COMP1; /*!< Offset: 0x030 (R/W) Comparator Register 1 */ - uint32_t RESERVED3[1U]; - __IOM uint32_t FUNCTION1; /*!< Offset: 0x038 (R/W) Function Register 1 */ - uint32_t RESERVED4[1U]; - __IOM uint32_t COMP2; /*!< Offset: 0x040 (R/W) Comparator Register 2 */ - uint32_t RESERVED5[1U]; - __IOM uint32_t FUNCTION2; /*!< Offset: 0x048 (R/W) Function Register 2 */ - uint32_t RESERVED6[1U]; - __IOM uint32_t COMP3; /*!< Offset: 0x050 (R/W) Comparator Register 3 */ - uint32_t RESERVED7[1U]; - __IOM uint32_t FUNCTION3; /*!< Offset: 0x058 (R/W) Function Register 3 */ - uint32_t RESERVED8[1U]; - __IOM uint32_t COMP4; /*!< Offset: 0x060 (R/W) Comparator Register 4 */ - uint32_t RESERVED9[1U]; - __IOM uint32_t FUNCTION4; /*!< Offset: 0x068 (R/W) Function Register 4 */ - uint32_t RESERVED10[1U]; - __IOM uint32_t COMP5; /*!< Offset: 0x070 (R/W) Comparator Register 5 */ - uint32_t RESERVED11[1U]; - __IOM uint32_t FUNCTION5; /*!< Offset: 0x078 (R/W) Function Register 5 */ - uint32_t RESERVED12[1U]; - __IOM uint32_t COMP6; /*!< Offset: 0x080 (R/W) Comparator Register 6 */ - uint32_t RESERVED13[1U]; - __IOM uint32_t FUNCTION6; /*!< Offset: 0x088 (R/W) Function Register 6 */ - uint32_t RESERVED14[1U]; - __IOM uint32_t COMP7; /*!< Offset: 0x090 (R/W) Comparator Register 7 */ - uint32_t RESERVED15[1U]; - __IOM uint32_t FUNCTION7; /*!< Offset: 0x098 (R/W) Function Register 7 */ - uint32_t RESERVED16[1U]; - __IOM uint32_t COMP8; /*!< Offset: 0x0A0 (R/W) Comparator Register 8 */ - uint32_t RESERVED17[1U]; - __IOM uint32_t FUNCTION8; /*!< Offset: 0x0A8 (R/W) Function Register 8 */ - uint32_t RESERVED18[1U]; - __IOM uint32_t COMP9; /*!< Offset: 0x0B0 (R/W) Comparator Register 9 */ - uint32_t RESERVED19[1U]; - __IOM uint32_t FUNCTION9; /*!< Offset: 0x0B8 (R/W) Function Register 9 */ - uint32_t RESERVED20[1U]; - __IOM uint32_t COMP10; /*!< Offset: 0x0C0 (R/W) Comparator Register 10 */ - uint32_t RESERVED21[1U]; - __IOM uint32_t FUNCTION10; /*!< Offset: 0x0C8 (R/W) Function Register 10 */ - uint32_t RESERVED22[1U]; - __IOM uint32_t COMP11; /*!< Offset: 0x0D0 (R/W) Comparator Register 11 */ - uint32_t RESERVED23[1U]; - __IOM uint32_t FUNCTION11; /*!< Offset: 0x0D8 (R/W) Function Register 11 */ - uint32_t RESERVED24[1U]; - __IOM uint32_t COMP12; /*!< Offset: 0x0E0 (R/W) Comparator Register 12 */ - uint32_t RESERVED25[1U]; - __IOM uint32_t FUNCTION12; /*!< Offset: 0x0E8 (R/W) Function Register 12 */ - uint32_t RESERVED26[1U]; - __IOM uint32_t COMP13; /*!< Offset: 0x0F0 (R/W) Comparator Register 13 */ - uint32_t RESERVED27[1U]; - __IOM uint32_t FUNCTION13; /*!< Offset: 0x0F8 (R/W) Function Register 13 */ - uint32_t RESERVED28[1U]; - __IOM uint32_t COMP14; /*!< Offset: 0x100 (R/W) Comparator Register 14 */ - uint32_t RESERVED29[1U]; - __IOM uint32_t FUNCTION14; /*!< Offset: 0x108 (R/W) Function Register 14 */ - uint32_t RESERVED30[1U]; - __IOM uint32_t COMP15; /*!< Offset: 0x110 (R/W) Comparator Register 15 */ - uint32_t RESERVED31[1U]; - __IOM uint32_t FUNCTION15; /*!< Offset: 0x118 (R/W) Function Register 15 */ - uint32_t RESERVED32[934U]; - __IM uint32_t LSR; /*!< Offset: 0xFB4 (R ) Lock Status Register */ - uint32_t RESERVED33[1U]; - __IM uint32_t DEVARCH; /*!< Offset: 0xFBC (R/ ) Device Architecture Register */ -} DWT_Type; - -/* DWT Control Register Definitions */ -#define DWT_CTRL_NUMCOMP_Pos 28U /*!< DWT CTRL: NUMCOMP Position */ -#define DWT_CTRL_NUMCOMP_Msk (0xFUL << DWT_CTRL_NUMCOMP_Pos) /*!< DWT CTRL: NUMCOMP Mask */ - -#define DWT_CTRL_NOTRCPKT_Pos 27U /*!< DWT CTRL: NOTRCPKT Position */ -#define DWT_CTRL_NOTRCPKT_Msk (0x1UL << DWT_CTRL_NOTRCPKT_Pos) /*!< DWT CTRL: NOTRCPKT Mask */ - -#define DWT_CTRL_NOEXTTRIG_Pos 26U /*!< DWT CTRL: NOEXTTRIG Position */ -#define DWT_CTRL_NOEXTTRIG_Msk (0x1UL << DWT_CTRL_NOEXTTRIG_Pos) /*!< DWT CTRL: NOEXTTRIG Mask */ - -#define DWT_CTRL_NOCYCCNT_Pos 25U /*!< DWT CTRL: NOCYCCNT Position */ -#define DWT_CTRL_NOCYCCNT_Msk (0x1UL << DWT_CTRL_NOCYCCNT_Pos) /*!< DWT CTRL: NOCYCCNT Mask */ - -#define DWT_CTRL_NOPRFCNT_Pos 24U /*!< DWT CTRL: NOPRFCNT Position */ -#define DWT_CTRL_NOPRFCNT_Msk (0x1UL << DWT_CTRL_NOPRFCNT_Pos) /*!< DWT CTRL: NOPRFCNT Mask */ - -#define DWT_CTRL_CYCDISS_Pos 23U /*!< DWT CTRL: CYCDISS Position */ -#define DWT_CTRL_CYCDISS_Msk (0x1UL << DWT_CTRL_CYCDISS_Pos) /*!< DWT CTRL: CYCDISS Mask */ - -#define DWT_CTRL_CYCEVTENA_Pos 22U /*!< DWT CTRL: CYCEVTENA Position */ -#define DWT_CTRL_CYCEVTENA_Msk (0x1UL << DWT_CTRL_CYCEVTENA_Pos) /*!< DWT CTRL: CYCEVTENA Mask */ - -#define DWT_CTRL_FOLDEVTENA_Pos 21U /*!< DWT CTRL: FOLDEVTENA Position */ -#define DWT_CTRL_FOLDEVTENA_Msk (0x1UL << DWT_CTRL_FOLDEVTENA_Pos) /*!< DWT CTRL: FOLDEVTENA Mask */ - -#define DWT_CTRL_LSUEVTENA_Pos 20U /*!< DWT CTRL: LSUEVTENA Position */ -#define DWT_CTRL_LSUEVTENA_Msk (0x1UL << DWT_CTRL_LSUEVTENA_Pos) /*!< DWT CTRL: LSUEVTENA Mask */ - -#define DWT_CTRL_SLEEPEVTENA_Pos 19U /*!< DWT CTRL: SLEEPEVTENA Position */ -#define DWT_CTRL_SLEEPEVTENA_Msk (0x1UL << DWT_CTRL_SLEEPEVTENA_Pos) /*!< DWT CTRL: SLEEPEVTENA Mask */ - -#define DWT_CTRL_EXCEVTENA_Pos 18U /*!< DWT CTRL: EXCEVTENA Position */ -#define DWT_CTRL_EXCEVTENA_Msk (0x1UL << DWT_CTRL_EXCEVTENA_Pos) /*!< DWT CTRL: EXCEVTENA Mask */ - -#define DWT_CTRL_CPIEVTENA_Pos 17U /*!< DWT CTRL: CPIEVTENA Position */ -#define DWT_CTRL_CPIEVTENA_Msk (0x1UL << DWT_CTRL_CPIEVTENA_Pos) /*!< DWT CTRL: CPIEVTENA Mask */ - -#define DWT_CTRL_EXCTRCENA_Pos 16U /*!< DWT CTRL: EXCTRCENA Position */ -#define DWT_CTRL_EXCTRCENA_Msk (0x1UL << DWT_CTRL_EXCTRCENA_Pos) /*!< DWT CTRL: EXCTRCENA Mask */ - -#define DWT_CTRL_PCSAMPLENA_Pos 12U /*!< DWT CTRL: PCSAMPLENA Position */ -#define DWT_CTRL_PCSAMPLENA_Msk (0x1UL << DWT_CTRL_PCSAMPLENA_Pos) /*!< DWT CTRL: PCSAMPLENA Mask */ - -#define DWT_CTRL_SYNCTAP_Pos 10U /*!< DWT CTRL: SYNCTAP Position */ -#define DWT_CTRL_SYNCTAP_Msk (0x3UL << DWT_CTRL_SYNCTAP_Pos) /*!< DWT CTRL: SYNCTAP Mask */ - -#define DWT_CTRL_CYCTAP_Pos 9U /*!< DWT CTRL: CYCTAP Position */ -#define DWT_CTRL_CYCTAP_Msk (0x1UL << DWT_CTRL_CYCTAP_Pos) /*!< DWT CTRL: CYCTAP Mask */ - -#define DWT_CTRL_POSTINIT_Pos 5U /*!< DWT CTRL: POSTINIT Position */ -#define DWT_CTRL_POSTINIT_Msk (0xFUL << DWT_CTRL_POSTINIT_Pos) /*!< DWT CTRL: POSTINIT Mask */ - -#define DWT_CTRL_POSTPRESET_Pos 1U /*!< DWT CTRL: POSTPRESET Position */ -#define DWT_CTRL_POSTPRESET_Msk (0xFUL << DWT_CTRL_POSTPRESET_Pos) /*!< DWT CTRL: POSTPRESET Mask */ - -#define DWT_CTRL_CYCCNTENA_Pos 0U /*!< DWT CTRL: CYCCNTENA Position */ -#define DWT_CTRL_CYCCNTENA_Msk (0x1UL /*<< DWT_CTRL_CYCCNTENA_Pos*/) /*!< DWT CTRL: CYCCNTENA Mask */ - -/* DWT CPI Count Register Definitions */ -#define DWT_CPICNT_CPICNT_Pos 0U /*!< DWT CPICNT: CPICNT Position */ -#define DWT_CPICNT_CPICNT_Msk (0xFFUL /*<< DWT_CPICNT_CPICNT_Pos*/) /*!< DWT CPICNT: CPICNT Mask */ - -/* DWT Exception Overhead Count Register Definitions */ -#define DWT_EXCCNT_EXCCNT_Pos 0U /*!< DWT EXCCNT: EXCCNT Position */ -#define DWT_EXCCNT_EXCCNT_Msk (0xFFUL /*<< DWT_EXCCNT_EXCCNT_Pos*/) /*!< DWT EXCCNT: EXCCNT Mask */ - -/* DWT Sleep Count Register Definitions */ -#define DWT_SLEEPCNT_SLEEPCNT_Pos 0U /*!< DWT SLEEPCNT: SLEEPCNT Position */ -#define DWT_SLEEPCNT_SLEEPCNT_Msk (0xFFUL /*<< DWT_SLEEPCNT_SLEEPCNT_Pos*/) /*!< DWT SLEEPCNT: SLEEPCNT Mask */ - -/* DWT LSU Count Register Definitions */ -#define DWT_LSUCNT_LSUCNT_Pos 0U /*!< DWT LSUCNT: LSUCNT Position */ -#define DWT_LSUCNT_LSUCNT_Msk (0xFFUL /*<< DWT_LSUCNT_LSUCNT_Pos*/) /*!< DWT LSUCNT: LSUCNT Mask */ - -/* DWT Folded-instruction Count Register Definitions */ -#define DWT_FOLDCNT_FOLDCNT_Pos 0U /*!< DWT FOLDCNT: FOLDCNT Position */ -#define DWT_FOLDCNT_FOLDCNT_Msk (0xFFUL /*<< DWT_FOLDCNT_FOLDCNT_Pos*/) /*!< DWT FOLDCNT: FOLDCNT Mask */ - -/* DWT Comparator Function Register Definitions */ -#define DWT_FUNCTION_ID_Pos 27U /*!< DWT FUNCTION: ID Position */ -#define DWT_FUNCTION_ID_Msk (0x1FUL << DWT_FUNCTION_ID_Pos) /*!< DWT FUNCTION: ID Mask */ - -#define DWT_FUNCTION_MATCHED_Pos 24U /*!< DWT FUNCTION: MATCHED Position */ -#define DWT_FUNCTION_MATCHED_Msk (0x1UL << DWT_FUNCTION_MATCHED_Pos) /*!< DWT FUNCTION: MATCHED Mask */ - -#define DWT_FUNCTION_DATAVSIZE_Pos 10U /*!< DWT FUNCTION: DATAVSIZE Position */ -#define DWT_FUNCTION_DATAVSIZE_Msk (0x3UL << DWT_FUNCTION_DATAVSIZE_Pos) /*!< DWT FUNCTION: DATAVSIZE Mask */ - -#define DWT_FUNCTION_ACTION_Pos 4U /*!< DWT FUNCTION: ACTION Position */ -#define DWT_FUNCTION_ACTION_Msk (0x1UL << DWT_FUNCTION_ACTION_Pos) /*!< DWT FUNCTION: ACTION Mask */ - -#define DWT_FUNCTION_MATCH_Pos 0U /*!< DWT FUNCTION: MATCH Position */ -#define DWT_FUNCTION_MATCH_Msk (0xFUL /*<< DWT_FUNCTION_MATCH_Pos*/) /*!< DWT FUNCTION: MATCH Mask */ - -/*@}*/ /* end of group CMSIS_DWT */ - - -/** - \ingroup CMSIS_core_register - \defgroup CMSIS_TPI Trace Port Interface (TPI) - \brief Type definitions for the Trace Port Interface (TPI) - @{ - */ - -/** - \brief Structure type to access the Trace Port Interface Register (TPI). - */ -typedef struct -{ - __IOM uint32_t SSPSR; /*!< Offset: 0x000 (R/ ) Supported Parallel Port Size Register */ - __IOM uint32_t CSPSR; /*!< Offset: 0x004 (R/W) Current Parallel Port Size Register */ - uint32_t RESERVED0[2U]; - __IOM uint32_t ACPR; /*!< Offset: 0x010 (R/W) Asynchronous Clock Prescaler Register */ - uint32_t RESERVED1[55U]; - __IOM uint32_t SPPR; /*!< Offset: 0x0F0 (R/W) Selected Pin Protocol Register */ - uint32_t RESERVED2[131U]; - __IM uint32_t FFSR; /*!< Offset: 0x300 (R/ ) Formatter and Flush Status Register */ - __IOM uint32_t FFCR; /*!< Offset: 0x304 (R/W) Formatter and Flush Control Register */ - __IM uint32_t FSCR; /*!< Offset: 0x308 (R/ ) Formatter Synchronization Counter Register */ - uint32_t RESERVED3[759U]; - __IM uint32_t TRIGGER; /*!< Offset: 0xEE8 (R/ ) TRIGGER */ - __IM uint32_t FIFO0; /*!< Offset: 0xEEC (R/ ) Integration ETM Data */ - __IM uint32_t ITATBCTR2; /*!< Offset: 0xEF0 (R/ ) ITATBCTR2 */ - uint32_t RESERVED4[1U]; - __IM uint32_t ITATBCTR0; /*!< Offset: 0xEF8 (R/ ) ITATBCTR0 */ - __IM uint32_t FIFO1; /*!< Offset: 0xEFC (R/ ) Integration ITM Data */ - __IOM uint32_t ITCTRL; /*!< Offset: 0xF00 (R/W) Integration Mode Control */ - uint32_t RESERVED5[39U]; - __IOM uint32_t CLAIMSET; /*!< Offset: 0xFA0 (R/W) Claim tag set */ - __IOM uint32_t CLAIMCLR; /*!< Offset: 0xFA4 (R/W) Claim tag clear */ - uint32_t RESERVED7[8U]; - __IM uint32_t DEVID; /*!< Offset: 0xFC8 (R/ ) TPIU_DEVID */ - __IM uint32_t DEVTYPE; /*!< Offset: 0xFCC (R/ ) TPIU_DEVTYPE */ -} TPI_Type; - -/* TPI Asynchronous Clock Prescaler Register Definitions */ -#define TPI_ACPR_PRESCALER_Pos 0U /*!< TPI ACPR: PRESCALER Position */ -#define TPI_ACPR_PRESCALER_Msk (0x1FFFUL /*<< TPI_ACPR_PRESCALER_Pos*/) /*!< TPI ACPR: PRESCALER Mask */ - -/* TPI Selected Pin Protocol Register Definitions */ -#define TPI_SPPR_TXMODE_Pos 0U /*!< TPI SPPR: TXMODE Position */ -#define TPI_SPPR_TXMODE_Msk (0x3UL /*<< TPI_SPPR_TXMODE_Pos*/) /*!< TPI SPPR: TXMODE Mask */ - -/* TPI Formatter and Flush Status Register Definitions */ -#define TPI_FFSR_FtNonStop_Pos 3U /*!< TPI FFSR: FtNonStop Position */ -#define TPI_FFSR_FtNonStop_Msk (0x1UL << TPI_FFSR_FtNonStop_Pos) /*!< TPI FFSR: FtNonStop Mask */ - -#define TPI_FFSR_TCPresent_Pos 2U /*!< TPI FFSR: TCPresent Position */ -#define TPI_FFSR_TCPresent_Msk (0x1UL << TPI_FFSR_TCPresent_Pos) /*!< TPI FFSR: TCPresent Mask */ - -#define TPI_FFSR_FtStopped_Pos 1U /*!< TPI FFSR: FtStopped Position */ -#define TPI_FFSR_FtStopped_Msk (0x1UL << TPI_FFSR_FtStopped_Pos) /*!< TPI FFSR: FtStopped Mask */ - -#define TPI_FFSR_FlInProg_Pos 0U /*!< TPI FFSR: FlInProg Position */ -#define TPI_FFSR_FlInProg_Msk (0x1UL /*<< TPI_FFSR_FlInProg_Pos*/) /*!< TPI FFSR: FlInProg Mask */ - -/* TPI Formatter and Flush Control Register Definitions */ -#define TPI_FFCR_TrigIn_Pos 8U /*!< TPI FFCR: TrigIn Position */ -#define TPI_FFCR_TrigIn_Msk (0x1UL << TPI_FFCR_TrigIn_Pos) /*!< TPI FFCR: TrigIn Mask */ - -#define TPI_FFCR_EnFCont_Pos 1U /*!< TPI FFCR: EnFCont Position */ -#define TPI_FFCR_EnFCont_Msk (0x1UL << TPI_FFCR_EnFCont_Pos) /*!< TPI FFCR: EnFCont Mask */ - -/* TPI TRIGGER Register Definitions */ -#define TPI_TRIGGER_TRIGGER_Pos 0U /*!< TPI TRIGGER: TRIGGER Position */ -#define TPI_TRIGGER_TRIGGER_Msk (0x1UL /*<< TPI_TRIGGER_TRIGGER_Pos*/) /*!< TPI TRIGGER: TRIGGER Mask */ - -/* TPI Integration ETM Data Register Definitions (FIFO0) */ -#define TPI_FIFO0_ITM_ATVALID_Pos 29U /*!< TPI FIFO0: ITM_ATVALID Position */ -#define TPI_FIFO0_ITM_ATVALID_Msk (0x3UL << TPI_FIFO0_ITM_ATVALID_Pos) /*!< TPI FIFO0: ITM_ATVALID Mask */ - -#define TPI_FIFO0_ITM_bytecount_Pos 27U /*!< TPI FIFO0: ITM_bytecount Position */ -#define TPI_FIFO0_ITM_bytecount_Msk (0x3UL << TPI_FIFO0_ITM_bytecount_Pos) /*!< TPI FIFO0: ITM_bytecount Mask */ - -#define TPI_FIFO0_ETM_ATVALID_Pos 26U /*!< TPI FIFO0: ETM_ATVALID Position */ -#define TPI_FIFO0_ETM_ATVALID_Msk (0x3UL << TPI_FIFO0_ETM_ATVALID_Pos) /*!< TPI FIFO0: ETM_ATVALID Mask */ - -#define TPI_FIFO0_ETM_bytecount_Pos 24U /*!< TPI FIFO0: ETM_bytecount Position */ -#define TPI_FIFO0_ETM_bytecount_Msk (0x3UL << TPI_FIFO0_ETM_bytecount_Pos) /*!< TPI FIFO0: ETM_bytecount Mask */ - -#define TPI_FIFO0_ETM2_Pos 16U /*!< TPI FIFO0: ETM2 Position */ -#define TPI_FIFO0_ETM2_Msk (0xFFUL << TPI_FIFO0_ETM2_Pos) /*!< TPI FIFO0: ETM2 Mask */ - -#define TPI_FIFO0_ETM1_Pos 8U /*!< TPI FIFO0: ETM1 Position */ -#define TPI_FIFO0_ETM1_Msk (0xFFUL << TPI_FIFO0_ETM1_Pos) /*!< TPI FIFO0: ETM1 Mask */ - -#define TPI_FIFO0_ETM0_Pos 0U /*!< TPI FIFO0: ETM0 Position */ -#define TPI_FIFO0_ETM0_Msk (0xFFUL /*<< TPI_FIFO0_ETM0_Pos*/) /*!< TPI FIFO0: ETM0 Mask */ - -/* TPI ITATBCTR2 Register Definitions */ -#define TPI_ITATBCTR2_ATREADY_Pos 0U /*!< TPI ITATBCTR2: ATREADY Position */ -#define TPI_ITATBCTR2_ATREADY_Msk (0x1UL /*<< TPI_ITATBCTR2_ATREADY_Pos*/) /*!< TPI ITATBCTR2: ATREADY Mask */ - -/* TPI Integration ITM Data Register Definitions (FIFO1) */ -#define TPI_FIFO1_ITM_ATVALID_Pos 29U /*!< TPI FIFO1: ITM_ATVALID Position */ -#define TPI_FIFO1_ITM_ATVALID_Msk (0x3UL << TPI_FIFO1_ITM_ATVALID_Pos) /*!< TPI FIFO1: ITM_ATVALID Mask */ - -#define TPI_FIFO1_ITM_bytecount_Pos 27U /*!< TPI FIFO1: ITM_bytecount Position */ -#define TPI_FIFO1_ITM_bytecount_Msk (0x3UL << TPI_FIFO1_ITM_bytecount_Pos) /*!< TPI FIFO1: ITM_bytecount Mask */ - -#define TPI_FIFO1_ETM_ATVALID_Pos 26U /*!< TPI FIFO1: ETM_ATVALID Position */ -#define TPI_FIFO1_ETM_ATVALID_Msk (0x3UL << TPI_FIFO1_ETM_ATVALID_Pos) /*!< TPI FIFO1: ETM_ATVALID Mask */ - -#define TPI_FIFO1_ETM_bytecount_Pos 24U /*!< TPI FIFO1: ETM_bytecount Position */ -#define TPI_FIFO1_ETM_bytecount_Msk (0x3UL << TPI_FIFO1_ETM_bytecount_Pos) /*!< TPI FIFO1: ETM_bytecount Mask */ - -#define TPI_FIFO1_ITM2_Pos 16U /*!< TPI FIFO1: ITM2 Position */ -#define TPI_FIFO1_ITM2_Msk (0xFFUL << TPI_FIFO1_ITM2_Pos) /*!< TPI FIFO1: ITM2 Mask */ - -#define TPI_FIFO1_ITM1_Pos 8U /*!< TPI FIFO1: ITM1 Position */ -#define TPI_FIFO1_ITM1_Msk (0xFFUL << TPI_FIFO1_ITM1_Pos) /*!< TPI FIFO1: ITM1 Mask */ - -#define TPI_FIFO1_ITM0_Pos 0U /*!< TPI FIFO1: ITM0 Position */ -#define TPI_FIFO1_ITM0_Msk (0xFFUL /*<< TPI_FIFO1_ITM0_Pos*/) /*!< TPI FIFO1: ITM0 Mask */ - -/* TPI ITATBCTR0 Register Definitions */ -#define TPI_ITATBCTR0_ATREADY_Pos 0U /*!< TPI ITATBCTR0: ATREADY Position */ -#define TPI_ITATBCTR0_ATREADY_Msk (0x1UL /*<< TPI_ITATBCTR0_ATREADY_Pos*/) /*!< TPI ITATBCTR0: ATREADY Mask */ - -/* TPI Integration Mode Control Register Definitions */ -#define TPI_ITCTRL_Mode_Pos 0U /*!< TPI ITCTRL: Mode Position */ -#define TPI_ITCTRL_Mode_Msk (0x1UL /*<< TPI_ITCTRL_Mode_Pos*/) /*!< TPI ITCTRL: Mode Mask */ - -/* TPI DEVID Register Definitions */ -#define TPI_DEVID_NRZVALID_Pos 11U /*!< TPI DEVID: NRZVALID Position */ -#define TPI_DEVID_NRZVALID_Msk (0x1UL << TPI_DEVID_NRZVALID_Pos) /*!< TPI DEVID: NRZVALID Mask */ - -#define TPI_DEVID_MANCVALID_Pos 10U /*!< TPI DEVID: MANCVALID Position */ -#define TPI_DEVID_MANCVALID_Msk (0x1UL << TPI_DEVID_MANCVALID_Pos) /*!< TPI DEVID: MANCVALID Mask */ - -#define TPI_DEVID_PTINVALID_Pos 9U /*!< TPI DEVID: PTINVALID Position */ -#define TPI_DEVID_PTINVALID_Msk (0x1UL << TPI_DEVID_PTINVALID_Pos) /*!< TPI DEVID: PTINVALID Mask */ - -#define TPI_DEVID_MinBufSz_Pos 6U /*!< TPI DEVID: MinBufSz Position */ -#define TPI_DEVID_MinBufSz_Msk (0x7UL << TPI_DEVID_MinBufSz_Pos) /*!< TPI DEVID: MinBufSz Mask */ - -#define TPI_DEVID_AsynClkIn_Pos 5U /*!< TPI DEVID: AsynClkIn Position */ -#define TPI_DEVID_AsynClkIn_Msk (0x1UL << TPI_DEVID_AsynClkIn_Pos) /*!< TPI DEVID: AsynClkIn Mask */ - -#define TPI_DEVID_NrTraceInput_Pos 0U /*!< TPI DEVID: NrTraceInput Position */ -#define TPI_DEVID_NrTraceInput_Msk (0x1FUL /*<< TPI_DEVID_NrTraceInput_Pos*/) /*!< TPI DEVID: NrTraceInput Mask */ - -/* TPI DEVTYPE Register Definitions */ -#define TPI_DEVTYPE_MajorType_Pos 4U /*!< TPI DEVTYPE: MajorType Position */ -#define TPI_DEVTYPE_MajorType_Msk (0xFUL << TPI_DEVTYPE_MajorType_Pos) /*!< TPI DEVTYPE: MajorType Mask */ - -#define TPI_DEVTYPE_SubType_Pos 0U /*!< TPI DEVTYPE: SubType Position */ -#define TPI_DEVTYPE_SubType_Msk (0xFUL /*<< TPI_DEVTYPE_SubType_Pos*/) /*!< TPI DEVTYPE: SubType Mask */ - -/*@}*/ /* end of group CMSIS_TPI */ - - -#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) -/** - \ingroup CMSIS_core_register - \defgroup CMSIS_MPU Memory Protection Unit (MPU) - \brief Type definitions for the Memory Protection Unit (MPU) - @{ - */ - -/** - \brief Structure type to access the Memory Protection Unit (MPU). - */ -typedef struct -{ - __IM uint32_t TYPE; /*!< Offset: 0x000 (R/ ) MPU Type Register */ - __IOM uint32_t CTRL; /*!< Offset: 0x004 (R/W) MPU Control Register */ - __IOM uint32_t RNR; /*!< Offset: 0x008 (R/W) MPU Region Number Register */ - __IOM uint32_t RBAR; /*!< Offset: 0x00C (R/W) MPU Region Base Address Register */ - __IOM uint32_t RLAR; /*!< Offset: 0x010 (R/W) MPU Region Limit Address Register */ - __IOM uint32_t RBAR_A1; /*!< Offset: 0x014 (R/W) MPU Region Base Address Register Alias 1 */ - __IOM uint32_t RLAR_A1; /*!< Offset: 0x018 (R/W) MPU Region Limit Address Register Alias 1 */ - __IOM uint32_t RBAR_A2; /*!< Offset: 0x01C (R/W) MPU Region Base Address Register Alias 2 */ - __IOM uint32_t RLAR_A2; /*!< Offset: 0x020 (R/W) MPU Region Limit Address Register Alias 2 */ - __IOM uint32_t RBAR_A3; /*!< Offset: 0x024 (R/W) MPU Region Base Address Register Alias 3 */ - __IOM uint32_t RLAR_A3; /*!< Offset: 0x028 (R/W) MPU Region Limit Address Register Alias 3 */ - uint32_t RESERVED0[1]; - union { - __IOM uint32_t MAIR[2]; - struct { - __IOM uint32_t MAIR0; /*!< Offset: 0x030 (R/W) MPU Memory Attribute Indirection Register 0 */ - __IOM uint32_t MAIR1; /*!< Offset: 0x034 (R/W) MPU Memory Attribute Indirection Register 1 */ - }; - }; -} MPU_Type; - -#define MPU_TYPE_RALIASES 4U - -/* MPU Type Register Definitions */ -#define MPU_TYPE_IREGION_Pos 16U /*!< MPU TYPE: IREGION Position */ -#define MPU_TYPE_IREGION_Msk (0xFFUL << MPU_TYPE_IREGION_Pos) /*!< MPU TYPE: IREGION Mask */ - -#define MPU_TYPE_DREGION_Pos 8U /*!< MPU TYPE: DREGION Position */ -#define MPU_TYPE_DREGION_Msk (0xFFUL << MPU_TYPE_DREGION_Pos) /*!< MPU TYPE: DREGION Mask */ - -#define MPU_TYPE_SEPARATE_Pos 0U /*!< MPU TYPE: SEPARATE Position */ -#define MPU_TYPE_SEPARATE_Msk (1UL /*<< MPU_TYPE_SEPARATE_Pos*/) /*!< MPU TYPE: SEPARATE Mask */ - -/* MPU Control Register Definitions */ -#define MPU_CTRL_PRIVDEFENA_Pos 2U /*!< MPU CTRL: PRIVDEFENA Position */ -#define MPU_CTRL_PRIVDEFENA_Msk (1UL << MPU_CTRL_PRIVDEFENA_Pos) /*!< MPU CTRL: PRIVDEFENA Mask */ - -#define MPU_CTRL_HFNMIENA_Pos 1U /*!< MPU CTRL: HFNMIENA Position */ -#define MPU_CTRL_HFNMIENA_Msk (1UL << MPU_CTRL_HFNMIENA_Pos) /*!< MPU CTRL: HFNMIENA Mask */ - -#define MPU_CTRL_ENABLE_Pos 0U /*!< MPU CTRL: ENABLE Position */ -#define MPU_CTRL_ENABLE_Msk (1UL /*<< MPU_CTRL_ENABLE_Pos*/) /*!< MPU CTRL: ENABLE Mask */ - -/* MPU Region Number Register Definitions */ -#define MPU_RNR_REGION_Pos 0U /*!< MPU RNR: REGION Position */ -#define MPU_RNR_REGION_Msk (0xFFUL /*<< MPU_RNR_REGION_Pos*/) /*!< MPU RNR: REGION Mask */ - -/* MPU Region Base Address Register Definitions */ -#define MPU_RBAR_ADDR_Pos 5U /*!< MPU RBAR: ADDR Position */ -#define MPU_RBAR_ADDR_Msk (0x7FFFFFFUL << MPU_RBAR_ADDR_Pos) /*!< MPU RBAR: ADDR Mask */ - -#define MPU_RBAR_SH_Pos 3U /*!< MPU RBAR: SH Position */ -#define MPU_RBAR_SH_Msk (0x3UL << MPU_RBAR_SH_Pos) /*!< MPU RBAR: SH Mask */ - -#define MPU_RBAR_AP_Pos 1U /*!< MPU RBAR: AP Position */ -#define MPU_RBAR_AP_Msk (0x3UL << MPU_RBAR_AP_Pos) /*!< MPU RBAR: AP Mask */ - -#define MPU_RBAR_XN_Pos 0U /*!< MPU RBAR: XN Position */ -#define MPU_RBAR_XN_Msk (01UL /*<< MPU_RBAR_XN_Pos*/) /*!< MPU RBAR: XN Mask */ - -/* MPU Region Limit Address Register Definitions */ -#define MPU_RLAR_LIMIT_Pos 5U /*!< MPU RLAR: LIMIT Position */ -#define MPU_RLAR_LIMIT_Msk (0x7FFFFFFUL << MPU_RLAR_LIMIT_Pos) /*!< MPU RLAR: LIMIT Mask */ - -#define MPU_RLAR_AttrIndx_Pos 1U /*!< MPU RLAR: AttrIndx Position */ -#define MPU_RLAR_AttrIndx_Msk (0x7UL << MPU_RLAR_AttrIndx_Pos) /*!< MPU RLAR: AttrIndx Mask */ - -#define MPU_RLAR_EN_Pos 0U /*!< MPU RLAR: Region enable bit Position */ -#define MPU_RLAR_EN_Msk (1UL /*<< MPU_RLAR_EN_Pos*/) /*!< MPU RLAR: Region enable bit Disable Mask */ - -/* MPU Memory Attribute Indirection Register 0 Definitions */ -#define MPU_MAIR0_Attr3_Pos 24U /*!< MPU MAIR0: Attr3 Position */ -#define MPU_MAIR0_Attr3_Msk (0xFFUL << MPU_MAIR0_Attr3_Pos) /*!< MPU MAIR0: Attr3 Mask */ - -#define MPU_MAIR0_Attr2_Pos 16U /*!< MPU MAIR0: Attr2 Position */ -#define MPU_MAIR0_Attr2_Msk (0xFFUL << MPU_MAIR0_Attr2_Pos) /*!< MPU MAIR0: Attr2 Mask */ - -#define MPU_MAIR0_Attr1_Pos 8U /*!< MPU MAIR0: Attr1 Position */ -#define MPU_MAIR0_Attr1_Msk (0xFFUL << MPU_MAIR0_Attr1_Pos) /*!< MPU MAIR0: Attr1 Mask */ - -#define MPU_MAIR0_Attr0_Pos 0U /*!< MPU MAIR0: Attr0 Position */ -#define MPU_MAIR0_Attr0_Msk (0xFFUL /*<< MPU_MAIR0_Attr0_Pos*/) /*!< MPU MAIR0: Attr0 Mask */ - -/* MPU Memory Attribute Indirection Register 1 Definitions */ -#define MPU_MAIR1_Attr7_Pos 24U /*!< MPU MAIR1: Attr7 Position */ -#define MPU_MAIR1_Attr7_Msk (0xFFUL << MPU_MAIR1_Attr7_Pos) /*!< MPU MAIR1: Attr7 Mask */ - -#define MPU_MAIR1_Attr6_Pos 16U /*!< MPU MAIR1: Attr6 Position */ -#define MPU_MAIR1_Attr6_Msk (0xFFUL << MPU_MAIR1_Attr6_Pos) /*!< MPU MAIR1: Attr6 Mask */ - -#define MPU_MAIR1_Attr5_Pos 8U /*!< MPU MAIR1: Attr5 Position */ -#define MPU_MAIR1_Attr5_Msk (0xFFUL << MPU_MAIR1_Attr5_Pos) /*!< MPU MAIR1: Attr5 Mask */ - -#define MPU_MAIR1_Attr4_Pos 0U /*!< MPU MAIR1: Attr4 Position */ -#define MPU_MAIR1_Attr4_Msk (0xFFUL /*<< MPU_MAIR1_Attr4_Pos*/) /*!< MPU MAIR1: Attr4 Mask */ - -/*@} end of group CMSIS_MPU */ -#endif - - -#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) -/** - \ingroup CMSIS_core_register - \defgroup CMSIS_SAU Security Attribution Unit (SAU) - \brief Type definitions for the Security Attribution Unit (SAU) - @{ - */ - -/** - \brief Structure type to access the Security Attribution Unit (SAU). - */ -typedef struct -{ - __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) SAU Control Register */ - __IM uint32_t TYPE; /*!< Offset: 0x004 (R/ ) SAU Type Register */ -#if defined (__SAUREGION_PRESENT) && (__SAUREGION_PRESENT == 1U) - __IOM uint32_t RNR; /*!< Offset: 0x008 (R/W) SAU Region Number Register */ - __IOM uint32_t RBAR; /*!< Offset: 0x00C (R/W) SAU Region Base Address Register */ - __IOM uint32_t RLAR; /*!< Offset: 0x010 (R/W) SAU Region Limit Address Register */ -#else - uint32_t RESERVED0[3]; -#endif - __IOM uint32_t SFSR; /*!< Offset: 0x014 (R/W) Secure Fault Status Register */ - __IOM uint32_t SFAR; /*!< Offset: 0x018 (R/W) Secure Fault Address Register */ -} SAU_Type; - -/* SAU Control Register Definitions */ -#define SAU_CTRL_ALLNS_Pos 1U /*!< SAU CTRL: ALLNS Position */ -#define SAU_CTRL_ALLNS_Msk (1UL << SAU_CTRL_ALLNS_Pos) /*!< SAU CTRL: ALLNS Mask */ - -#define SAU_CTRL_ENABLE_Pos 0U /*!< SAU CTRL: ENABLE Position */ -#define SAU_CTRL_ENABLE_Msk (1UL /*<< SAU_CTRL_ENABLE_Pos*/) /*!< SAU CTRL: ENABLE Mask */ - -/* SAU Type Register Definitions */ -#define SAU_TYPE_SREGION_Pos 0U /*!< SAU TYPE: SREGION Position */ -#define SAU_TYPE_SREGION_Msk (0xFFUL /*<< SAU_TYPE_SREGION_Pos*/) /*!< SAU TYPE: SREGION Mask */ - -#if defined (__SAUREGION_PRESENT) && (__SAUREGION_PRESENT == 1U) -/* SAU Region Number Register Definitions */ -#define SAU_RNR_REGION_Pos 0U /*!< SAU RNR: REGION Position */ -#define SAU_RNR_REGION_Msk (0xFFUL /*<< SAU_RNR_REGION_Pos*/) /*!< SAU RNR: REGION Mask */ - -/* SAU Region Base Address Register Definitions */ -#define SAU_RBAR_BADDR_Pos 5U /*!< SAU RBAR: BADDR Position */ -#define SAU_RBAR_BADDR_Msk (0x7FFFFFFUL << SAU_RBAR_BADDR_Pos) /*!< SAU RBAR: BADDR Mask */ - -/* SAU Region Limit Address Register Definitions */ -#define SAU_RLAR_LADDR_Pos 5U /*!< SAU RLAR: LADDR Position */ -#define SAU_RLAR_LADDR_Msk (0x7FFFFFFUL << SAU_RLAR_LADDR_Pos) /*!< SAU RLAR: LADDR Mask */ - -#define SAU_RLAR_NSC_Pos 1U /*!< SAU RLAR: NSC Position */ -#define SAU_RLAR_NSC_Msk (1UL << SAU_RLAR_NSC_Pos) /*!< SAU RLAR: NSC Mask */ - -#define SAU_RLAR_ENABLE_Pos 0U /*!< SAU RLAR: ENABLE Position */ -#define SAU_RLAR_ENABLE_Msk (1UL /*<< SAU_RLAR_ENABLE_Pos*/) /*!< SAU RLAR: ENABLE Mask */ - -#endif /* defined (__SAUREGION_PRESENT) && (__SAUREGION_PRESENT == 1U) */ - -/* Secure Fault Status Register Definitions */ -#define SAU_SFSR_LSERR_Pos 7U /*!< SAU SFSR: LSERR Position */ -#define SAU_SFSR_LSERR_Msk (1UL << SAU_SFSR_LSERR_Pos) /*!< SAU SFSR: LSERR Mask */ - -#define SAU_SFSR_SFARVALID_Pos 6U /*!< SAU SFSR: SFARVALID Position */ -#define SAU_SFSR_SFARVALID_Msk (1UL << SAU_SFSR_SFARVALID_Pos) /*!< SAU SFSR: SFARVALID Mask */ - -#define SAU_SFSR_LSPERR_Pos 5U /*!< SAU SFSR: LSPERR Position */ -#define SAU_SFSR_LSPERR_Msk (1UL << SAU_SFSR_LSPERR_Pos) /*!< SAU SFSR: LSPERR Mask */ - -#define SAU_SFSR_INVTRAN_Pos 4U /*!< SAU SFSR: INVTRAN Position */ -#define SAU_SFSR_INVTRAN_Msk (1UL << SAU_SFSR_INVTRAN_Pos) /*!< SAU SFSR: INVTRAN Mask */ - -#define SAU_SFSR_AUVIOL_Pos 3U /*!< SAU SFSR: AUVIOL Position */ -#define SAU_SFSR_AUVIOL_Msk (1UL << SAU_SFSR_AUVIOL_Pos) /*!< SAU SFSR: AUVIOL Mask */ - -#define SAU_SFSR_INVER_Pos 2U /*!< SAU SFSR: INVER Position */ -#define SAU_SFSR_INVER_Msk (1UL << SAU_SFSR_INVER_Pos) /*!< SAU SFSR: INVER Mask */ - -#define SAU_SFSR_INVIS_Pos 1U /*!< SAU SFSR: INVIS Position */ -#define SAU_SFSR_INVIS_Msk (1UL << SAU_SFSR_INVIS_Pos) /*!< SAU SFSR: INVIS Mask */ - -#define SAU_SFSR_INVEP_Pos 0U /*!< SAU SFSR: INVEP Position */ -#define SAU_SFSR_INVEP_Msk (1UL /*<< SAU_SFSR_INVEP_Pos*/) /*!< SAU SFSR: INVEP Mask */ - -/*@} end of group CMSIS_SAU */ -#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */ - - -/** - \ingroup CMSIS_core_register - \defgroup CMSIS_FPU Floating Point Unit (FPU) - \brief Type definitions for the Floating Point Unit (FPU) - @{ - */ - -/** - \brief Structure type to access the Floating Point Unit (FPU). - */ -typedef struct -{ - uint32_t RESERVED0[1U]; - __IOM uint32_t FPCCR; /*!< Offset: 0x004 (R/W) Floating-Point Context Control Register */ - __IOM uint32_t FPCAR; /*!< Offset: 0x008 (R/W) Floating-Point Context Address Register */ - __IOM uint32_t FPDSCR; /*!< Offset: 0x00C (R/W) Floating-Point Default Status Control Register */ - __IM uint32_t MVFR0; /*!< Offset: 0x010 (R/ ) Media and FP Feature Register 0 */ - __IM uint32_t MVFR1; /*!< Offset: 0x014 (R/ ) Media and FP Feature Register 1 */ -} FPU_Type; - -/* Floating-Point Context Control Register Definitions */ -#define FPU_FPCCR_ASPEN_Pos 31U /*!< FPCCR: ASPEN bit Position */ -#define FPU_FPCCR_ASPEN_Msk (1UL << FPU_FPCCR_ASPEN_Pos) /*!< FPCCR: ASPEN bit Mask */ - -#define FPU_FPCCR_LSPEN_Pos 30U /*!< FPCCR: LSPEN Position */ -#define FPU_FPCCR_LSPEN_Msk (1UL << FPU_FPCCR_LSPEN_Pos) /*!< FPCCR: LSPEN bit Mask */ - -#define FPU_FPCCR_LSPENS_Pos 29U /*!< FPCCR: LSPENS Position */ -#define FPU_FPCCR_LSPENS_Msk (1UL << FPU_FPCCR_LSPENS_Pos) /*!< FPCCR: LSPENS bit Mask */ - -#define FPU_FPCCR_CLRONRET_Pos 28U /*!< FPCCR: CLRONRET Position */ -#define FPU_FPCCR_CLRONRET_Msk (1UL << FPU_FPCCR_CLRONRET_Pos) /*!< FPCCR: CLRONRET bit Mask */ - -#define FPU_FPCCR_CLRONRETS_Pos 27U /*!< FPCCR: CLRONRETS Position */ -#define FPU_FPCCR_CLRONRETS_Msk (1UL << FPU_FPCCR_CLRONRETS_Pos) /*!< FPCCR: CLRONRETS bit Mask */ - -#define FPU_FPCCR_TS_Pos 26U /*!< FPCCR: TS Position */ -#define FPU_FPCCR_TS_Msk (1UL << FPU_FPCCR_TS_Pos) /*!< FPCCR: TS bit Mask */ - -#define FPU_FPCCR_UFRDY_Pos 10U /*!< FPCCR: UFRDY Position */ -#define FPU_FPCCR_UFRDY_Msk (1UL << FPU_FPCCR_UFRDY_Pos) /*!< FPCCR: UFRDY bit Mask */ - -#define FPU_FPCCR_SPLIMVIOL_Pos 9U /*!< FPCCR: SPLIMVIOL Position */ -#define FPU_FPCCR_SPLIMVIOL_Msk (1UL << FPU_FPCCR_SPLIMVIOL_Pos) /*!< FPCCR: SPLIMVIOL bit Mask */ - -#define FPU_FPCCR_MONRDY_Pos 8U /*!< FPCCR: MONRDY Position */ -#define FPU_FPCCR_MONRDY_Msk (1UL << FPU_FPCCR_MONRDY_Pos) /*!< FPCCR: MONRDY bit Mask */ - -#define FPU_FPCCR_SFRDY_Pos 7U /*!< FPCCR: SFRDY Position */ -#define FPU_FPCCR_SFRDY_Msk (1UL << FPU_FPCCR_SFRDY_Pos) /*!< FPCCR: SFRDY bit Mask */ - -#define FPU_FPCCR_BFRDY_Pos 6U /*!< FPCCR: BFRDY Position */ -#define FPU_FPCCR_BFRDY_Msk (1UL << FPU_FPCCR_BFRDY_Pos) /*!< FPCCR: BFRDY bit Mask */ - -#define FPU_FPCCR_MMRDY_Pos 5U /*!< FPCCR: MMRDY Position */ -#define FPU_FPCCR_MMRDY_Msk (1UL << FPU_FPCCR_MMRDY_Pos) /*!< FPCCR: MMRDY bit Mask */ - -#define FPU_FPCCR_HFRDY_Pos 4U /*!< FPCCR: HFRDY Position */ -#define FPU_FPCCR_HFRDY_Msk (1UL << FPU_FPCCR_HFRDY_Pos) /*!< FPCCR: HFRDY bit Mask */ - -#define FPU_FPCCR_THREAD_Pos 3U /*!< FPCCR: processor mode bit Position */ -#define FPU_FPCCR_THREAD_Msk (1UL << FPU_FPCCR_THREAD_Pos) /*!< FPCCR: processor mode active bit Mask */ - -#define FPU_FPCCR_S_Pos 2U /*!< FPCCR: Security status of the FP context bit Position */ -#define FPU_FPCCR_S_Msk (1UL << FPU_FPCCR_S_Pos) /*!< FPCCR: Security status of the FP context bit Mask */ - -#define FPU_FPCCR_USER_Pos 1U /*!< FPCCR: privilege level bit Position */ -#define FPU_FPCCR_USER_Msk (1UL << FPU_FPCCR_USER_Pos) /*!< FPCCR: privilege level bit Mask */ - -#define FPU_FPCCR_LSPACT_Pos 0U /*!< FPCCR: Lazy state preservation active bit Position */ -#define FPU_FPCCR_LSPACT_Msk (1UL /*<< FPU_FPCCR_LSPACT_Pos*/) /*!< FPCCR: Lazy state preservation active bit Mask */ - -/* Floating-Point Context Address Register Definitions */ -#define FPU_FPCAR_ADDRESS_Pos 3U /*!< FPCAR: ADDRESS bit Position */ -#define FPU_FPCAR_ADDRESS_Msk (0x1FFFFFFFUL << FPU_FPCAR_ADDRESS_Pos) /*!< FPCAR: ADDRESS bit Mask */ - -/* Floating-Point Default Status Control Register Definitions */ -#define FPU_FPDSCR_AHP_Pos 26U /*!< FPDSCR: AHP bit Position */ -#define FPU_FPDSCR_AHP_Msk (1UL << FPU_FPDSCR_AHP_Pos) /*!< FPDSCR: AHP bit Mask */ - -#define FPU_FPDSCR_DN_Pos 25U /*!< FPDSCR: DN bit Position */ -#define FPU_FPDSCR_DN_Msk (1UL << FPU_FPDSCR_DN_Pos) /*!< FPDSCR: DN bit Mask */ - -#define FPU_FPDSCR_FZ_Pos 24U /*!< FPDSCR: FZ bit Position */ -#define FPU_FPDSCR_FZ_Msk (1UL << FPU_FPDSCR_FZ_Pos) /*!< FPDSCR: FZ bit Mask */ - -#define FPU_FPDSCR_RMode_Pos 22U /*!< FPDSCR: RMode bit Position */ -#define FPU_FPDSCR_RMode_Msk (3UL << FPU_FPDSCR_RMode_Pos) /*!< FPDSCR: RMode bit Mask */ - -/* Media and FP Feature Register 0 Definitions */ -#define FPU_MVFR0_FP_rounding_modes_Pos 28U /*!< MVFR0: FP rounding modes bits Position */ -#define FPU_MVFR0_FP_rounding_modes_Msk (0xFUL << FPU_MVFR0_FP_rounding_modes_Pos) /*!< MVFR0: FP rounding modes bits Mask */ - -#define FPU_MVFR0_Short_vectors_Pos 24U /*!< MVFR0: Short vectors bits Position */ -#define FPU_MVFR0_Short_vectors_Msk (0xFUL << FPU_MVFR0_Short_vectors_Pos) /*!< MVFR0: Short vectors bits Mask */ - -#define FPU_MVFR0_Square_root_Pos 20U /*!< MVFR0: Square root bits Position */ -#define FPU_MVFR0_Square_root_Msk (0xFUL << FPU_MVFR0_Square_root_Pos) /*!< MVFR0: Square root bits Mask */ - -#define FPU_MVFR0_Divide_Pos 16U /*!< MVFR0: Divide bits Position */ -#define FPU_MVFR0_Divide_Msk (0xFUL << FPU_MVFR0_Divide_Pos) /*!< MVFR0: Divide bits Mask */ - -#define FPU_MVFR0_FP_excep_trapping_Pos 12U /*!< MVFR0: FP exception trapping bits Position */ -#define FPU_MVFR0_FP_excep_trapping_Msk (0xFUL << FPU_MVFR0_FP_excep_trapping_Pos) /*!< MVFR0: FP exception trapping bits Mask */ - -#define FPU_MVFR0_Double_precision_Pos 8U /*!< MVFR0: Double-precision bits Position */ -#define FPU_MVFR0_Double_precision_Msk (0xFUL << FPU_MVFR0_Double_precision_Pos) /*!< MVFR0: Double-precision bits Mask */ - -#define FPU_MVFR0_Single_precision_Pos 4U /*!< MVFR0: Single-precision bits Position */ -#define FPU_MVFR0_Single_precision_Msk (0xFUL << FPU_MVFR0_Single_precision_Pos) /*!< MVFR0: Single-precision bits Mask */ - -#define FPU_MVFR0_A_SIMD_registers_Pos 0U /*!< MVFR0: A_SIMD registers bits Position */ -#define FPU_MVFR0_A_SIMD_registers_Msk (0xFUL /*<< FPU_MVFR0_A_SIMD_registers_Pos*/) /*!< MVFR0: A_SIMD registers bits Mask */ - -/* Media and FP Feature Register 1 Definitions */ -#define FPU_MVFR1_FP_fused_MAC_Pos 28U /*!< MVFR1: FP fused MAC bits Position */ -#define FPU_MVFR1_FP_fused_MAC_Msk (0xFUL << FPU_MVFR1_FP_fused_MAC_Pos) /*!< MVFR1: FP fused MAC bits Mask */ - -#define FPU_MVFR1_FP_HPFP_Pos 24U /*!< MVFR1: FP HPFP bits Position */ -#define FPU_MVFR1_FP_HPFP_Msk (0xFUL << FPU_MVFR1_FP_HPFP_Pos) /*!< MVFR1: FP HPFP bits Mask */ - -#define FPU_MVFR1_D_NaN_mode_Pos 4U /*!< MVFR1: D_NaN mode bits Position */ -#define FPU_MVFR1_D_NaN_mode_Msk (0xFUL << FPU_MVFR1_D_NaN_mode_Pos) /*!< MVFR1: D_NaN mode bits Mask */ - -#define FPU_MVFR1_FtZ_mode_Pos 0U /*!< MVFR1: FtZ mode bits Position */ -#define FPU_MVFR1_FtZ_mode_Msk (0xFUL /*<< FPU_MVFR1_FtZ_mode_Pos*/) /*!< MVFR1: FtZ mode bits Mask */ - -/*@} end of group CMSIS_FPU */ - - -/** - \ingroup CMSIS_core_register - \defgroup CMSIS_CoreDebug Core Debug Registers (CoreDebug) - \brief Type definitions for the Core Debug Registers - @{ - */ - -/** - \brief Structure type to access the Core Debug Register (CoreDebug). - */ -typedef struct -{ - __IOM uint32_t DHCSR; /*!< Offset: 0x000 (R/W) Debug Halting Control and Status Register */ - __OM uint32_t DCRSR; /*!< Offset: 0x004 ( /W) Debug Core Register Selector Register */ - __IOM uint32_t DCRDR; /*!< Offset: 0x008 (R/W) Debug Core Register Data Register */ - __IOM uint32_t DEMCR; /*!< Offset: 0x00C (R/W) Debug Exception and Monitor Control Register */ - uint32_t RESERVED4[1U]; - __IOM uint32_t DAUTHCTRL; /*!< Offset: 0x014 (R/W) Debug Authentication Control Register */ - __IOM uint32_t DSCSR; /*!< Offset: 0x018 (R/W) Debug Security Control and Status Register */ -} CoreDebug_Type; - -/* Debug Halting Control and Status Register Definitions */ -#define CoreDebug_DHCSR_DBGKEY_Pos 16U /*!< CoreDebug DHCSR: DBGKEY Position */ -#define CoreDebug_DHCSR_DBGKEY_Msk (0xFFFFUL << CoreDebug_DHCSR_DBGKEY_Pos) /*!< CoreDebug DHCSR: DBGKEY Mask */ - -#define CoreDebug_DHCSR_S_RESTART_ST_Pos 26U /*!< CoreDebug DHCSR: S_RESTART_ST Position */ -#define CoreDebug_DHCSR_S_RESTART_ST_Msk (1UL << CoreDebug_DHCSR_S_RESTART_ST_Pos) /*!< CoreDebug DHCSR: S_RESTART_ST Mask */ - -#define CoreDebug_DHCSR_S_RESET_ST_Pos 25U /*!< CoreDebug DHCSR: S_RESET_ST Position */ -#define CoreDebug_DHCSR_S_RESET_ST_Msk (1UL << CoreDebug_DHCSR_S_RESET_ST_Pos) /*!< CoreDebug DHCSR: S_RESET_ST Mask */ - -#define CoreDebug_DHCSR_S_RETIRE_ST_Pos 24U /*!< CoreDebug DHCSR: S_RETIRE_ST Position */ -#define CoreDebug_DHCSR_S_RETIRE_ST_Msk (1UL << CoreDebug_DHCSR_S_RETIRE_ST_Pos) /*!< CoreDebug DHCSR: S_RETIRE_ST Mask */ - -#define CoreDebug_DHCSR_S_LOCKUP_Pos 19U /*!< CoreDebug DHCSR: S_LOCKUP Position */ -#define CoreDebug_DHCSR_S_LOCKUP_Msk (1UL << CoreDebug_DHCSR_S_LOCKUP_Pos) /*!< CoreDebug DHCSR: S_LOCKUP Mask */ - -#define CoreDebug_DHCSR_S_SLEEP_Pos 18U /*!< CoreDebug DHCSR: S_SLEEP Position */ -#define CoreDebug_DHCSR_S_SLEEP_Msk (1UL << CoreDebug_DHCSR_S_SLEEP_Pos) /*!< CoreDebug DHCSR: S_SLEEP Mask */ - -#define CoreDebug_DHCSR_S_HALT_Pos 17U /*!< CoreDebug DHCSR: S_HALT Position */ -#define CoreDebug_DHCSR_S_HALT_Msk (1UL << CoreDebug_DHCSR_S_HALT_Pos) /*!< CoreDebug DHCSR: S_HALT Mask */ - -#define CoreDebug_DHCSR_S_REGRDY_Pos 16U /*!< CoreDebug DHCSR: S_REGRDY Position */ -#define CoreDebug_DHCSR_S_REGRDY_Msk (1UL << CoreDebug_DHCSR_S_REGRDY_Pos) /*!< CoreDebug DHCSR: S_REGRDY Mask */ - -#define CoreDebug_DHCSR_C_SNAPSTALL_Pos 5U /*!< CoreDebug DHCSR: C_SNAPSTALL Position */ -#define CoreDebug_DHCSR_C_SNAPSTALL_Msk (1UL << CoreDebug_DHCSR_C_SNAPSTALL_Pos) /*!< CoreDebug DHCSR: C_SNAPSTALL Mask */ - -#define CoreDebug_DHCSR_C_MASKINTS_Pos 3U /*!< CoreDebug DHCSR: C_MASKINTS Position */ -#define CoreDebug_DHCSR_C_MASKINTS_Msk (1UL << CoreDebug_DHCSR_C_MASKINTS_Pos) /*!< CoreDebug DHCSR: C_MASKINTS Mask */ - -#define CoreDebug_DHCSR_C_STEP_Pos 2U /*!< CoreDebug DHCSR: C_STEP Position */ -#define CoreDebug_DHCSR_C_STEP_Msk (1UL << CoreDebug_DHCSR_C_STEP_Pos) /*!< CoreDebug DHCSR: C_STEP Mask */ - -#define CoreDebug_DHCSR_C_HALT_Pos 1U /*!< CoreDebug DHCSR: C_HALT Position */ -#define CoreDebug_DHCSR_C_HALT_Msk (1UL << CoreDebug_DHCSR_C_HALT_Pos) /*!< CoreDebug DHCSR: C_HALT Mask */ - -#define CoreDebug_DHCSR_C_DEBUGEN_Pos 0U /*!< CoreDebug DHCSR: C_DEBUGEN Position */ -#define CoreDebug_DHCSR_C_DEBUGEN_Msk (1UL /*<< CoreDebug_DHCSR_C_DEBUGEN_Pos*/) /*!< CoreDebug DHCSR: C_DEBUGEN Mask */ - -/* Debug Core Register Selector Register Definitions */ -#define CoreDebug_DCRSR_REGWnR_Pos 16U /*!< CoreDebug DCRSR: REGWnR Position */ -#define CoreDebug_DCRSR_REGWnR_Msk (1UL << CoreDebug_DCRSR_REGWnR_Pos) /*!< CoreDebug DCRSR: REGWnR Mask */ - -#define CoreDebug_DCRSR_REGSEL_Pos 0U /*!< CoreDebug DCRSR: REGSEL Position */ -#define CoreDebug_DCRSR_REGSEL_Msk (0x1FUL /*<< CoreDebug_DCRSR_REGSEL_Pos*/) /*!< CoreDebug DCRSR: REGSEL Mask */ - -/* Debug Exception and Monitor Control Register Definitions */ -#define CoreDebug_DEMCR_TRCENA_Pos 24U /*!< CoreDebug DEMCR: TRCENA Position */ -#define CoreDebug_DEMCR_TRCENA_Msk (1UL << CoreDebug_DEMCR_TRCENA_Pos) /*!< CoreDebug DEMCR: TRCENA Mask */ - -#define CoreDebug_DEMCR_MON_REQ_Pos 19U /*!< CoreDebug DEMCR: MON_REQ Position */ -#define CoreDebug_DEMCR_MON_REQ_Msk (1UL << CoreDebug_DEMCR_MON_REQ_Pos) /*!< CoreDebug DEMCR: MON_REQ Mask */ - -#define CoreDebug_DEMCR_MON_STEP_Pos 18U /*!< CoreDebug DEMCR: MON_STEP Position */ -#define CoreDebug_DEMCR_MON_STEP_Msk (1UL << CoreDebug_DEMCR_MON_STEP_Pos) /*!< CoreDebug DEMCR: MON_STEP Mask */ - -#define CoreDebug_DEMCR_MON_PEND_Pos 17U /*!< CoreDebug DEMCR: MON_PEND Position */ -#define CoreDebug_DEMCR_MON_PEND_Msk (1UL << CoreDebug_DEMCR_MON_PEND_Pos) /*!< CoreDebug DEMCR: MON_PEND Mask */ - -#define CoreDebug_DEMCR_MON_EN_Pos 16U /*!< CoreDebug DEMCR: MON_EN Position */ -#define CoreDebug_DEMCR_MON_EN_Msk (1UL << CoreDebug_DEMCR_MON_EN_Pos) /*!< CoreDebug DEMCR: MON_EN Mask */ - -#define CoreDebug_DEMCR_VC_HARDERR_Pos 10U /*!< CoreDebug DEMCR: VC_HARDERR Position */ -#define CoreDebug_DEMCR_VC_HARDERR_Msk (1UL << CoreDebug_DEMCR_VC_HARDERR_Pos) /*!< CoreDebug DEMCR: VC_HARDERR Mask */ - -#define CoreDebug_DEMCR_VC_INTERR_Pos 9U /*!< CoreDebug DEMCR: VC_INTERR Position */ -#define CoreDebug_DEMCR_VC_INTERR_Msk (1UL << CoreDebug_DEMCR_VC_INTERR_Pos) /*!< CoreDebug DEMCR: VC_INTERR Mask */ - -#define CoreDebug_DEMCR_VC_BUSERR_Pos 8U /*!< CoreDebug DEMCR: VC_BUSERR Position */ -#define CoreDebug_DEMCR_VC_BUSERR_Msk (1UL << CoreDebug_DEMCR_VC_BUSERR_Pos) /*!< CoreDebug DEMCR: VC_BUSERR Mask */ - -#define CoreDebug_DEMCR_VC_STATERR_Pos 7U /*!< CoreDebug DEMCR: VC_STATERR Position */ -#define CoreDebug_DEMCR_VC_STATERR_Msk (1UL << CoreDebug_DEMCR_VC_STATERR_Pos) /*!< CoreDebug DEMCR: VC_STATERR Mask */ - -#define CoreDebug_DEMCR_VC_CHKERR_Pos 6U /*!< CoreDebug DEMCR: VC_CHKERR Position */ -#define CoreDebug_DEMCR_VC_CHKERR_Msk (1UL << CoreDebug_DEMCR_VC_CHKERR_Pos) /*!< CoreDebug DEMCR: VC_CHKERR Mask */ - -#define CoreDebug_DEMCR_VC_NOCPERR_Pos 5U /*!< CoreDebug DEMCR: VC_NOCPERR Position */ -#define CoreDebug_DEMCR_VC_NOCPERR_Msk (1UL << CoreDebug_DEMCR_VC_NOCPERR_Pos) /*!< CoreDebug DEMCR: VC_NOCPERR Mask */ - -#define CoreDebug_DEMCR_VC_MMERR_Pos 4U /*!< CoreDebug DEMCR: VC_MMERR Position */ -#define CoreDebug_DEMCR_VC_MMERR_Msk (1UL << CoreDebug_DEMCR_VC_MMERR_Pos) /*!< CoreDebug DEMCR: VC_MMERR Mask */ - -#define CoreDebug_DEMCR_VC_CORERESET_Pos 0U /*!< CoreDebug DEMCR: VC_CORERESET Position */ -#define CoreDebug_DEMCR_VC_CORERESET_Msk (1UL /*<< CoreDebug_DEMCR_VC_CORERESET_Pos*/) /*!< CoreDebug DEMCR: VC_CORERESET Mask */ - -/* Debug Authentication Control Register Definitions */ -#define CoreDebug_DAUTHCTRL_INTSPNIDEN_Pos 3U /*!< CoreDebug DAUTHCTRL: INTSPNIDEN, Position */ -#define CoreDebug_DAUTHCTRL_INTSPNIDEN_Msk (1UL << CoreDebug_DAUTHCTRL_INTSPNIDEN_Pos) /*!< CoreDebug DAUTHCTRL: INTSPNIDEN, Mask */ - -#define CoreDebug_DAUTHCTRL_SPNIDENSEL_Pos 2U /*!< CoreDebug DAUTHCTRL: SPNIDENSEL Position */ -#define CoreDebug_DAUTHCTRL_SPNIDENSEL_Msk (1UL << CoreDebug_DAUTHCTRL_SPNIDENSEL_Pos) /*!< CoreDebug DAUTHCTRL: SPNIDENSEL Mask */ - -#define CoreDebug_DAUTHCTRL_INTSPIDEN_Pos 1U /*!< CoreDebug DAUTHCTRL: INTSPIDEN Position */ -#define CoreDebug_DAUTHCTRL_INTSPIDEN_Msk (1UL << CoreDebug_DAUTHCTRL_INTSPIDEN_Pos) /*!< CoreDebug DAUTHCTRL: INTSPIDEN Mask */ - -#define CoreDebug_DAUTHCTRL_SPIDENSEL_Pos 0U /*!< CoreDebug DAUTHCTRL: SPIDENSEL Position */ -#define CoreDebug_DAUTHCTRL_SPIDENSEL_Msk (1UL /*<< CoreDebug_DAUTHCTRL_SPIDENSEL_Pos*/) /*!< CoreDebug DAUTHCTRL: SPIDENSEL Mask */ - -/* Debug Security Control and Status Register Definitions */ -#define CoreDebug_DSCSR_CDS_Pos 16U /*!< CoreDebug DSCSR: CDS Position */ -#define CoreDebug_DSCSR_CDS_Msk (1UL << CoreDebug_DSCSR_CDS_Pos) /*!< CoreDebug DSCSR: CDS Mask */ - -#define CoreDebug_DSCSR_SBRSEL_Pos 1U /*!< CoreDebug DSCSR: SBRSEL Position */ -#define CoreDebug_DSCSR_SBRSEL_Msk (1UL << CoreDebug_DSCSR_SBRSEL_Pos) /*!< CoreDebug DSCSR: SBRSEL Mask */ - -#define CoreDebug_DSCSR_SBRSELEN_Pos 0U /*!< CoreDebug DSCSR: SBRSELEN Position */ -#define CoreDebug_DSCSR_SBRSELEN_Msk (1UL /*<< CoreDebug_DSCSR_SBRSELEN_Pos*/) /*!< CoreDebug DSCSR: SBRSELEN Mask */ - -/*@} end of group CMSIS_CoreDebug */ - - -/** - \ingroup CMSIS_core_register - \defgroup CMSIS_core_bitfield Core register bit field macros - \brief Macros for use with bit field definitions (xxx_Pos, xxx_Msk). - @{ - */ - -/** - \brief Mask and shift a bit field value for use in a register bit range. - \param[in] field Name of the register bit field. - \param[in] value Value of the bit field. This parameter is interpreted as an uint32_t type. - \return Masked and shifted value. -*/ -#define _VAL2FLD(field, value) (((uint32_t)(value) << field ## _Pos) & field ## _Msk) - -/** - \brief Mask and shift a register value to extract a bit filed value. - \param[in] field Name of the register bit field. - \param[in] value Value of register. This parameter is interpreted as an uint32_t type. - \return Masked and shifted bit field value. -*/ -#define _FLD2VAL(field, value) (((uint32_t)(value) & field ## _Msk) >> field ## _Pos) - -/*@} end of group CMSIS_core_bitfield */ - - -/** - \ingroup CMSIS_core_register - \defgroup CMSIS_core_base Core Definitions - \brief Definitions for base addresses, unions, and structures. - @{ - */ - -/* Memory mapping of Core Hardware */ - #define SCS_BASE (0xE000E000UL) /*!< System Control Space Base Address */ - #define ITM_BASE (0xE0000000UL) /*!< ITM Base Address */ - #define DWT_BASE (0xE0001000UL) /*!< DWT Base Address */ - #define TPI_BASE (0xE0040000UL) /*!< TPI Base Address */ - #define CoreDebug_BASE (0xE000EDF0UL) /*!< Core Debug Base Address */ - #define SysTick_BASE (SCS_BASE + 0x0010UL) /*!< SysTick Base Address */ - #define NVIC_BASE (SCS_BASE + 0x0100UL) /*!< NVIC Base Address */ - #define SCB_BASE (SCS_BASE + 0x0D00UL) /*!< System Control Block Base Address */ - - #define SCnSCB ((SCnSCB_Type *) SCS_BASE ) /*!< System control Register not in SCB */ - #define SCB ((SCB_Type *) SCB_BASE ) /*!< SCB configuration struct */ - #define SysTick ((SysTick_Type *) SysTick_BASE ) /*!< SysTick configuration struct */ - #define NVIC ((NVIC_Type *) NVIC_BASE ) /*!< NVIC configuration struct */ - #define ITM ((ITM_Type *) ITM_BASE ) /*!< ITM configuration struct */ - #define DWT ((DWT_Type *) DWT_BASE ) /*!< DWT configuration struct */ - #define TPI ((TPI_Type *) TPI_BASE ) /*!< TPI configuration struct */ - #define CoreDebug ((CoreDebug_Type *) CoreDebug_BASE ) /*!< Core Debug configuration struct */ - - #if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) - #define MPU_BASE (SCS_BASE + 0x0D90UL) /*!< Memory Protection Unit */ - #define MPU ((MPU_Type *) MPU_BASE ) /*!< Memory Protection Unit */ - #endif - - #if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) - #define SAU_BASE (SCS_BASE + 0x0DD0UL) /*!< Security Attribution Unit */ - #define SAU ((SAU_Type *) SAU_BASE ) /*!< Security Attribution Unit */ - #endif - - #define FPU_BASE (SCS_BASE + 0x0F30UL) /*!< Floating Point Unit */ - #define FPU ((FPU_Type *) FPU_BASE ) /*!< Floating Point Unit */ - -#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) - #define SCS_BASE_NS (0xE002E000UL) /*!< System Control Space Base Address (non-secure address space) */ - #define CoreDebug_BASE_NS (0xE002EDF0UL) /*!< Core Debug Base Address (non-secure address space) */ - #define SysTick_BASE_NS (SCS_BASE_NS + 0x0010UL) /*!< SysTick Base Address (non-secure address space) */ - #define NVIC_BASE_NS (SCS_BASE_NS + 0x0100UL) /*!< NVIC Base Address (non-secure address space) */ - #define SCB_BASE_NS (SCS_BASE_NS + 0x0D00UL) /*!< System Control Block Base Address (non-secure address space) */ - - #define SCnSCB_NS ((SCnSCB_Type *) SCS_BASE_NS ) /*!< System control Register not in SCB(non-secure address space) */ - #define SCB_NS ((SCB_Type *) SCB_BASE_NS ) /*!< SCB configuration struct (non-secure address space) */ - #define SysTick_NS ((SysTick_Type *) SysTick_BASE_NS ) /*!< SysTick configuration struct (non-secure address space) */ - #define NVIC_NS ((NVIC_Type *) NVIC_BASE_NS ) /*!< NVIC configuration struct (non-secure address space) */ - #define CoreDebug_NS ((CoreDebug_Type *) CoreDebug_BASE_NS) /*!< Core Debug configuration struct (non-secure address space) */ - - #if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) - #define MPU_BASE_NS (SCS_BASE_NS + 0x0D90UL) /*!< Memory Protection Unit (non-secure address space) */ - #define MPU_NS ((MPU_Type *) MPU_BASE_NS ) /*!< Memory Protection Unit (non-secure address space) */ - #endif - - #define FPU_BASE_NS (SCS_BASE_NS + 0x0F30UL) /*!< Floating Point Unit (non-secure address space) */ - #define FPU_NS ((FPU_Type *) FPU_BASE_NS ) /*!< Floating Point Unit (non-secure address space) */ - -#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */ -/*@} */ - - - -/******************************************************************************* - * Hardware Abstraction Layer - Core Function Interface contains: - - Core NVIC Functions - - Core SysTick Functions - - Core Debug Functions - - Core Register Access Functions - ******************************************************************************/ -/** - \defgroup CMSIS_Core_FunctionInterface Functions and Instructions Reference -*/ - - - -/* ########################## NVIC functions #################################### */ -/** - \ingroup CMSIS_Core_FunctionInterface - \defgroup CMSIS_Core_NVICFunctions NVIC Functions - \brief Functions that manage interrupts and exceptions via the NVIC. - @{ - */ - -#ifdef CMSIS_NVIC_VIRTUAL - #ifndef CMSIS_NVIC_VIRTUAL_HEADER_FILE - #define CMSIS_NVIC_VIRTUAL_HEADER_FILE "cmsis_nvic_virtual.h" - #endif - #include CMSIS_NVIC_VIRTUAL_HEADER_FILE -#else - #define NVIC_SetPriorityGrouping __NVIC_SetPriorityGrouping - #define NVIC_GetPriorityGrouping __NVIC_GetPriorityGrouping - #define NVIC_EnableIRQ __NVIC_EnableIRQ - #define NVIC_GetEnableIRQ __NVIC_GetEnableIRQ - #define NVIC_DisableIRQ __NVIC_DisableIRQ - #define NVIC_GetPendingIRQ __NVIC_GetPendingIRQ - #define NVIC_SetPendingIRQ __NVIC_SetPendingIRQ - #define NVIC_ClearPendingIRQ __NVIC_ClearPendingIRQ - #define NVIC_GetActive __NVIC_GetActive - #define NVIC_SetPriority __NVIC_SetPriority - #define NVIC_GetPriority __NVIC_GetPriority - #define NVIC_SystemReset __NVIC_SystemReset -#endif /* CMSIS_NVIC_VIRTUAL */ - -#ifdef CMSIS_VECTAB_VIRTUAL - #ifndef CMSIS_VECTAB_VIRTUAL_HEADER_FILE - #define CMSIS_VECTAB_VIRTUAL_HEADER_FILE "cmsis_vectab_virtual.h" - #endif - #include CMSIS_VECTAB_VIRTUAL_HEADER_FILE -#else - #define NVIC_SetVector __NVIC_SetVector - #define NVIC_GetVector __NVIC_GetVector -#endif /* (CMSIS_VECTAB_VIRTUAL) */ - -#define NVIC_USER_IRQ_OFFSET 16 - - - -/** - \brief Set Priority Grouping - \details Sets the priority grouping field using the required unlock sequence. - The parameter PriorityGroup is assigned to the field SCB->AIRCR [10:8] PRIGROUP field. - Only values from 0..7 are used. - In case of a conflict between priority grouping and available - priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set. - \param [in] PriorityGroup Priority grouping field. - */ -__STATIC_INLINE void __NVIC_SetPriorityGrouping(uint32_t PriorityGroup) -{ - uint32_t reg_value; - uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ - - reg_value = SCB->AIRCR; /* read old register configuration */ - reg_value &= ~((uint32_t)(SCB_AIRCR_VECTKEY_Msk | SCB_AIRCR_PRIGROUP_Msk)); /* clear bits to change */ - reg_value = (reg_value | - ((uint32_t)0x5FAUL << SCB_AIRCR_VECTKEY_Pos) | - (PriorityGroupTmp << 8U) ); /* Insert write key and priorty group */ - SCB->AIRCR = reg_value; -} - - -/** - \brief Get Priority Grouping - \details Reads the priority grouping field from the NVIC Interrupt Controller. - \return Priority grouping field (SCB->AIRCR [10:8] PRIGROUP field). - */ -__STATIC_INLINE uint32_t __NVIC_GetPriorityGrouping(void) -{ - return ((uint32_t)((SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) >> SCB_AIRCR_PRIGROUP_Pos)); -} - - -/** - \brief Enable Interrupt - \details Enables a device specific interrupt in the NVIC interrupt controller. - \param [in] IRQn Device specific interrupt number. - \note IRQn must not be negative. - */ -__STATIC_INLINE void __NVIC_EnableIRQ(IRQn_Type IRQn) -{ - if ((int32_t)(IRQn) >= 0) - { - NVIC->ISER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); - } -} - - -/** - \brief Get Interrupt Enable status - \details Returns a device specific interrupt enable status from the NVIC interrupt controller. - \param [in] IRQn Device specific interrupt number. - \return 0 Interrupt is not enabled. - \return 1 Interrupt is enabled. - \note IRQn must not be negative. - */ -__STATIC_INLINE uint32_t __NVIC_GetEnableIRQ(IRQn_Type IRQn) -{ - if ((int32_t)(IRQn) >= 0) - { - return((uint32_t)(((NVIC->ISER[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); - } - else - { - return(0U); - } -} - - -/** - \brief Disable Interrupt - \details Disables a device specific interrupt in the NVIC interrupt controller. - \param [in] IRQn Device specific interrupt number. - \note IRQn must not be negative. - */ -__STATIC_INLINE void __NVIC_DisableIRQ(IRQn_Type IRQn) -{ - if ((int32_t)(IRQn) >= 0) - { - NVIC->ICER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); - __DSB(); - __ISB(); - } -} - - -/** - \brief Get Pending Interrupt - \details Reads the NVIC pending register and returns the pending bit for the specified device specific interrupt. - \param [in] IRQn Device specific interrupt number. - \return 0 Interrupt status is not pending. - \return 1 Interrupt status is pending. - \note IRQn must not be negative. - */ -__STATIC_INLINE uint32_t __NVIC_GetPendingIRQ(IRQn_Type IRQn) -{ - if ((int32_t)(IRQn) >= 0) - { - return((uint32_t)(((NVIC->ISPR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); - } - else - { - return(0U); - } -} - - -/** - \brief Set Pending Interrupt - \details Sets the pending bit of a device specific interrupt in the NVIC pending register. - \param [in] IRQn Device specific interrupt number. - \note IRQn must not be negative. - */ -__STATIC_INLINE void __NVIC_SetPendingIRQ(IRQn_Type IRQn) -{ - if ((int32_t)(IRQn) >= 0) - { - NVIC->ISPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); - } -} - - -/** - \brief Clear Pending Interrupt - \details Clears the pending bit of a device specific interrupt in the NVIC pending register. - \param [in] IRQn Device specific interrupt number. - \note IRQn must not be negative. - */ -__STATIC_INLINE void __NVIC_ClearPendingIRQ(IRQn_Type IRQn) -{ - if ((int32_t)(IRQn) >= 0) - { - NVIC->ICPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); - } -} - - -/** - \brief Get Active Interrupt - \details Reads the active register in the NVIC and returns the active bit for the device specific interrupt. - \param [in] IRQn Device specific interrupt number. - \return 0 Interrupt status is not active. - \return 1 Interrupt status is active. - \note IRQn must not be negative. - */ -__STATIC_INLINE uint32_t __NVIC_GetActive(IRQn_Type IRQn) -{ - if ((int32_t)(IRQn) >= 0) - { - return((uint32_t)(((NVIC->IABR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); - } - else - { - return(0U); - } -} - - -#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) -/** - \brief Get Interrupt Target State - \details Reads the interrupt target field in the NVIC and returns the interrupt target bit for the device specific interrupt. - \param [in] IRQn Device specific interrupt number. - \return 0 if interrupt is assigned to Secure - \return 1 if interrupt is assigned to Non Secure - \note IRQn must not be negative. - */ -__STATIC_INLINE uint32_t NVIC_GetTargetState(IRQn_Type IRQn) -{ - if ((int32_t)(IRQn) >= 0) - { - return((uint32_t)(((NVIC->ITNS[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); - } - else - { - return(0U); - } -} - - -/** - \brief Set Interrupt Target State - \details Sets the interrupt target field in the NVIC and returns the interrupt target bit for the device specific interrupt. - \param [in] IRQn Device specific interrupt number. - \return 0 if interrupt is assigned to Secure - 1 if interrupt is assigned to Non Secure - \note IRQn must not be negative. - */ -__STATIC_INLINE uint32_t NVIC_SetTargetState(IRQn_Type IRQn) -{ - if ((int32_t)(IRQn) >= 0) - { - NVIC->ITNS[(((uint32_t)IRQn) >> 5UL)] |= ((uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL))); - return((uint32_t)(((NVIC->ITNS[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); - } - else - { - return(0U); - } -} - - -/** - \brief Clear Interrupt Target State - \details Clears the interrupt target field in the NVIC and returns the interrupt target bit for the device specific interrupt. - \param [in] IRQn Device specific interrupt number. - \return 0 if interrupt is assigned to Secure - 1 if interrupt is assigned to Non Secure - \note IRQn must not be negative. - */ -__STATIC_INLINE uint32_t NVIC_ClearTargetState(IRQn_Type IRQn) -{ - if ((int32_t)(IRQn) >= 0) - { - NVIC->ITNS[(((uint32_t)IRQn) >> 5UL)] &= ~((uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL))); - return((uint32_t)(((NVIC->ITNS[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); - } - else - { - return(0U); - } -} -#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */ - - -/** - \brief Set Interrupt Priority - \details Sets the priority of a device specific interrupt or a processor exception. - The interrupt number can be positive to specify a device specific interrupt, - or negative to specify a processor exception. - \param [in] IRQn Interrupt number. - \param [in] priority Priority to set. - \note The priority cannot be set for every processor exception. - */ -__STATIC_INLINE void __NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority) -{ - if ((int32_t)(IRQn) >= 0) - { - NVIC->IPR[((uint32_t)IRQn)] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL); - } - else - { - SCB->SHPR[(((uint32_t)IRQn) & 0xFUL)-4UL] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL); - } -} - - -/** - \brief Get Interrupt Priority - \details Reads the priority of a device specific interrupt or a processor exception. - The interrupt number can be positive to specify a device specific interrupt, - or negative to specify a processor exception. - \param [in] IRQn Interrupt number. - \return Interrupt Priority. - Value is aligned automatically to the implemented priority bits of the microcontroller. - */ -__STATIC_INLINE uint32_t __NVIC_GetPriority(IRQn_Type IRQn) -{ - - if ((int32_t)(IRQn) >= 0) - { - return(((uint32_t)NVIC->IPR[((uint32_t)IRQn)] >> (8U - __NVIC_PRIO_BITS))); - } - else - { - return(((uint32_t)SCB->SHPR[(((uint32_t)IRQn) & 0xFUL)-4UL] >> (8U - __NVIC_PRIO_BITS))); - } -} - - -/** - \brief Encode Priority - \details Encodes the priority for an interrupt with the given priority group, - preemptive priority value, and subpriority value. - In case of a conflict between priority grouping and available - priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set. - \param [in] PriorityGroup Used priority group. - \param [in] PreemptPriority Preemptive priority value (starting from 0). - \param [in] SubPriority Subpriority value (starting from 0). - \return Encoded priority. Value can be used in the function \ref NVIC_SetPriority(). - */ -__STATIC_INLINE uint32_t NVIC_EncodePriority (uint32_t PriorityGroup, uint32_t PreemptPriority, uint32_t SubPriority) -{ - uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ - uint32_t PreemptPriorityBits; - uint32_t SubPriorityBits; - - PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp); - SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS)); - - return ( - ((PreemptPriority & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL)) << SubPriorityBits) | - ((SubPriority & (uint32_t)((1UL << (SubPriorityBits )) - 1UL))) - ); -} - - -/** - \brief Decode Priority - \details Decodes an interrupt priority value with a given priority group to - preemptive priority value and subpriority value. - In case of a conflict between priority grouping and available - priority bits (__NVIC_PRIO_BITS) the smallest possible priority group is set. - \param [in] Priority Priority value, which can be retrieved with the function \ref NVIC_GetPriority(). - \param [in] PriorityGroup Used priority group. - \param [out] pPreemptPriority Preemptive priority value (starting from 0). - \param [out] pSubPriority Subpriority value (starting from 0). - */ -__STATIC_INLINE void NVIC_DecodePriority (uint32_t Priority, uint32_t PriorityGroup, uint32_t* const pPreemptPriority, uint32_t* const pSubPriority) -{ - uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ - uint32_t PreemptPriorityBits; - uint32_t SubPriorityBits; - - PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp); - SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS)); - - *pPreemptPriority = (Priority >> SubPriorityBits) & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL); - *pSubPriority = (Priority ) & (uint32_t)((1UL << (SubPriorityBits )) - 1UL); -} - - -/** - \brief Set Interrupt Vector - \details Sets an interrupt vector in SRAM based interrupt vector table. - The interrupt number can be positive to specify a device specific interrupt, - or negative to specify a processor exception. - VTOR must been relocated to SRAM before. - \param [in] IRQn Interrupt number - \param [in] vector Address of interrupt handler function - */ -__STATIC_INLINE void __NVIC_SetVector(IRQn_Type IRQn, uint32_t vector) -{ - uint32_t *vectors = (uint32_t *)SCB->VTOR; - vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET] = vector; -} - - -/** - \brief Get Interrupt Vector - \details Reads an interrupt vector from interrupt vector table. - The interrupt number can be positive to specify a device specific interrupt, - or negative to specify a processor exception. - \param [in] IRQn Interrupt number. - \return Address of interrupt handler function - */ -__STATIC_INLINE uint32_t __NVIC_GetVector(IRQn_Type IRQn) -{ - uint32_t *vectors = (uint32_t *)SCB->VTOR; - return vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET]; -} - - -/** - \brief System Reset - \details Initiates a system reset request to reset the MCU. - */ -__STATIC_INLINE void __NVIC_SystemReset(void) -{ - __DSB(); /* Ensure all outstanding memory accesses included - buffered write are completed before reset */ - SCB->AIRCR = (uint32_t)((0x5FAUL << SCB_AIRCR_VECTKEY_Pos) | - (SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) | - SCB_AIRCR_SYSRESETREQ_Msk ); /* Keep priority group unchanged */ - __DSB(); /* Ensure completion of memory access */ - - for(;;) /* wait until reset */ - { - __NOP(); - } -} - -#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) -/** - \brief Set Priority Grouping (non-secure) - \details Sets the non-secure priority grouping field when in secure state using the required unlock sequence. - The parameter PriorityGroup is assigned to the field SCB->AIRCR [10:8] PRIGROUP field. - Only values from 0..7 are used. - In case of a conflict between priority grouping and available - priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set. - \param [in] PriorityGroup Priority grouping field. - */ -__STATIC_INLINE void TZ_NVIC_SetPriorityGrouping_NS(uint32_t PriorityGroup) -{ - uint32_t reg_value; - uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ - - reg_value = SCB_NS->AIRCR; /* read old register configuration */ - reg_value &= ~((uint32_t)(SCB_AIRCR_VECTKEY_Msk | SCB_AIRCR_PRIGROUP_Msk)); /* clear bits to change */ - reg_value = (reg_value | - ((uint32_t)0x5FAUL << SCB_AIRCR_VECTKEY_Pos) | - (PriorityGroupTmp << 8U) ); /* Insert write key and priorty group */ - SCB_NS->AIRCR = reg_value; -} - - -/** - \brief Get Priority Grouping (non-secure) - \details Reads the priority grouping field from the non-secure NVIC when in secure state. - \return Priority grouping field (SCB->AIRCR [10:8] PRIGROUP field). - */ -__STATIC_INLINE uint32_t TZ_NVIC_GetPriorityGrouping_NS(void) -{ - return ((uint32_t)((SCB_NS->AIRCR & SCB_AIRCR_PRIGROUP_Msk) >> SCB_AIRCR_PRIGROUP_Pos)); -} - - -/** - \brief Enable Interrupt (non-secure) - \details Enables a device specific interrupt in the non-secure NVIC interrupt controller when in secure state. - \param [in] IRQn Device specific interrupt number. - \note IRQn must not be negative. - */ -__STATIC_INLINE void TZ_NVIC_EnableIRQ_NS(IRQn_Type IRQn) -{ - if ((int32_t)(IRQn) >= 0) - { - NVIC_NS->ISER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); - } -} - - -/** - \brief Get Interrupt Enable status (non-secure) - \details Returns a device specific interrupt enable status from the non-secure NVIC interrupt controller when in secure state. - \param [in] IRQn Device specific interrupt number. - \return 0 Interrupt is not enabled. - \return 1 Interrupt is enabled. - \note IRQn must not be negative. - */ -__STATIC_INLINE uint32_t TZ_NVIC_GetEnableIRQ_NS(IRQn_Type IRQn) -{ - if ((int32_t)(IRQn) >= 0) - { - return((uint32_t)(((NVIC_NS->ISER[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); - } - else - { - return(0U); - } -} - - -/** - \brief Disable Interrupt (non-secure) - \details Disables a device specific interrupt in the non-secure NVIC interrupt controller when in secure state. - \param [in] IRQn Device specific interrupt number. - \note IRQn must not be negative. - */ -__STATIC_INLINE void TZ_NVIC_DisableIRQ_NS(IRQn_Type IRQn) -{ - if ((int32_t)(IRQn) >= 0) - { - NVIC_NS->ICER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); - } -} - - -/** - \brief Get Pending Interrupt (non-secure) - \details Reads the NVIC pending register in the non-secure NVIC when in secure state and returns the pending bit for the specified device specific interrupt. - \param [in] IRQn Device specific interrupt number. - \return 0 Interrupt status is not pending. - \return 1 Interrupt status is pending. - \note IRQn must not be negative. - */ -__STATIC_INLINE uint32_t TZ_NVIC_GetPendingIRQ_NS(IRQn_Type IRQn) -{ - if ((int32_t)(IRQn) >= 0) - { - return((uint32_t)(((NVIC_NS->ISPR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); - } - else - { - return(0U); - } -} - - -/** - \brief Set Pending Interrupt (non-secure) - \details Sets the pending bit of a device specific interrupt in the non-secure NVIC pending register when in secure state. - \param [in] IRQn Device specific interrupt number. - \note IRQn must not be negative. - */ -__STATIC_INLINE void TZ_NVIC_SetPendingIRQ_NS(IRQn_Type IRQn) -{ - if ((int32_t)(IRQn) >= 0) - { - NVIC_NS->ISPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); - } -} - - -/** - \brief Clear Pending Interrupt (non-secure) - \details Clears the pending bit of a device specific interrupt in the non-secure NVIC pending register when in secure state. - \param [in] IRQn Device specific interrupt number. - \note IRQn must not be negative. - */ -__STATIC_INLINE void TZ_NVIC_ClearPendingIRQ_NS(IRQn_Type IRQn) -{ - if ((int32_t)(IRQn) >= 0) - { - NVIC_NS->ICPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); - } -} - - -/** - \brief Get Active Interrupt (non-secure) - \details Reads the active register in non-secure NVIC when in secure state and returns the active bit for the device specific interrupt. - \param [in] IRQn Device specific interrupt number. - \return 0 Interrupt status is not active. - \return 1 Interrupt status is active. - \note IRQn must not be negative. - */ -__STATIC_INLINE uint32_t TZ_NVIC_GetActive_NS(IRQn_Type IRQn) -{ - if ((int32_t)(IRQn) >= 0) - { - return((uint32_t)(((NVIC_NS->IABR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); - } - else - { - return(0U); - } -} - - -/** - \brief Set Interrupt Priority (non-secure) - \details Sets the priority of a non-secure device specific interrupt or a non-secure processor exception when in secure state. - The interrupt number can be positive to specify a device specific interrupt, - or negative to specify a processor exception. - \param [in] IRQn Interrupt number. - \param [in] priority Priority to set. - \note The priority cannot be set for every non-secure processor exception. - */ -__STATIC_INLINE void TZ_NVIC_SetPriority_NS(IRQn_Type IRQn, uint32_t priority) -{ - if ((int32_t)(IRQn) >= 0) - { - NVIC_NS->IPR[((uint32_t)IRQn)] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL); - } - else - { - SCB_NS->SHPR[(((uint32_t)IRQn) & 0xFUL)-4UL] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL); - } -} - - -/** - \brief Get Interrupt Priority (non-secure) - \details Reads the priority of a non-secure device specific interrupt or a non-secure processor exception when in secure state. - The interrupt number can be positive to specify a device specific interrupt, - or negative to specify a processor exception. - \param [in] IRQn Interrupt number. - \return Interrupt Priority. Value is aligned automatically to the implemented priority bits of the microcontroller. - */ -__STATIC_INLINE uint32_t TZ_NVIC_GetPriority_NS(IRQn_Type IRQn) -{ - - if ((int32_t)(IRQn) >= 0) - { - return(((uint32_t)NVIC_NS->IPR[((uint32_t)IRQn)] >> (8U - __NVIC_PRIO_BITS))); - } - else - { - return(((uint32_t)SCB_NS->SHPR[(((uint32_t)IRQn) & 0xFUL)-4UL] >> (8U - __NVIC_PRIO_BITS))); - } -} -#endif /* defined (__ARM_FEATURE_CMSE) &&(__ARM_FEATURE_CMSE == 3U) */ - -/*@} end of CMSIS_Core_NVICFunctions */ - -/* ########################## MPU functions #################################### */ - -#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) - -#include "mpu_armv8.h" - -#endif - -/* ########################## FPU functions #################################### */ -/** - \ingroup CMSIS_Core_FunctionInterface - \defgroup CMSIS_Core_FpuFunctions FPU Functions - \brief Function that provides FPU type. - @{ - */ - -/** - \brief get FPU type - \details returns the FPU type - \returns - - \b 0: No FPU - - \b 1: Single precision FPU - - \b 2: Double + Single precision FPU - */ -__STATIC_INLINE uint32_t SCB_GetFPUType(void) -{ - uint32_t mvfr0; - - mvfr0 = FPU->MVFR0; - if ((mvfr0 & (FPU_MVFR0_Single_precision_Msk | FPU_MVFR0_Double_precision_Msk)) == 0x220U) - { - return 2U; /* Double + Single precision FPU */ - } - else if ((mvfr0 & (FPU_MVFR0_Single_precision_Msk | FPU_MVFR0_Double_precision_Msk)) == 0x020U) - { - return 1U; /* Single precision FPU */ - } - else - { - return 0U; /* No FPU */ - } -} - - -/*@} end of CMSIS_Core_FpuFunctions */ - - - -/* ########################## SAU functions #################################### */ -/** - \ingroup CMSIS_Core_FunctionInterface - \defgroup CMSIS_Core_SAUFunctions SAU Functions - \brief Functions that configure the SAU. - @{ - */ - -#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) - -/** - \brief Enable SAU - \details Enables the Security Attribution Unit (SAU). - */ -__STATIC_INLINE void TZ_SAU_Enable(void) -{ - SAU->CTRL |= (SAU_CTRL_ENABLE_Msk); -} - - - -/** - \brief Disable SAU - \details Disables the Security Attribution Unit (SAU). - */ -__STATIC_INLINE void TZ_SAU_Disable(void) -{ - SAU->CTRL &= ~(SAU_CTRL_ENABLE_Msk); -} - -#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */ - -/*@} end of CMSIS_Core_SAUFunctions */ - - - - -/* ################################## SysTick function ############################################ */ -/** - \ingroup CMSIS_Core_FunctionInterface - \defgroup CMSIS_Core_SysTickFunctions SysTick Functions - \brief Functions that configure the System. - @{ - */ - -#if defined (__Vendor_SysTickConfig) && (__Vendor_SysTickConfig == 0U) - -/** - \brief System Tick Configuration - \details Initializes the System Timer and its interrupt, and starts the System Tick Timer. - Counter is in free running mode to generate periodic interrupts. - \param [in] ticks Number of ticks between two interrupts. - \return 0 Function succeeded. - \return 1 Function failed. - \note When the variable __Vendor_SysTickConfig is set to 1, then the - function SysTick_Config is not included. In this case, the file device.h - must contain a vendor-specific implementation of this function. - */ -__STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks) -{ - if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk) - { - return (1UL); /* Reload value impossible */ - } - - SysTick->LOAD = (uint32_t)(ticks - 1UL); /* set reload register */ - NVIC_SetPriority (SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */ - SysTick->VAL = 0UL; /* Load the SysTick Counter Value */ - SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk | - SysTick_CTRL_TICKINT_Msk | - SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */ - return (0UL); /* Function successful */ -} - -#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) -/** - \brief System Tick Configuration (non-secure) - \details Initializes the non-secure System Timer and its interrupt when in secure state, and starts the System Tick Timer. - Counter is in free running mode to generate periodic interrupts. - \param [in] ticks Number of ticks between two interrupts. - \return 0 Function succeeded. - \return 1 Function failed. - \note When the variable __Vendor_SysTickConfig is set to 1, then the - function TZ_SysTick_Config_NS is not included. In this case, the file device.h - must contain a vendor-specific implementation of this function. - - */ -__STATIC_INLINE uint32_t TZ_SysTick_Config_NS(uint32_t ticks) -{ - if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk) - { - return (1UL); /* Reload value impossible */ - } - - SysTick_NS->LOAD = (uint32_t)(ticks - 1UL); /* set reload register */ - TZ_NVIC_SetPriority_NS (SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */ - SysTick_NS->VAL = 0UL; /* Load the SysTick Counter Value */ - SysTick_NS->CTRL = SysTick_CTRL_CLKSOURCE_Msk | - SysTick_CTRL_TICKINT_Msk | - SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */ - return (0UL); /* Function successful */ -} -#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */ - -#endif - -/*@} end of CMSIS_Core_SysTickFunctions */ - - - -/* ##################################### Debug In/Output function ########################################### */ -/** - \ingroup CMSIS_Core_FunctionInterface - \defgroup CMSIS_core_DebugFunctions ITM Functions - \brief Functions that access the ITM debug interface. - @{ - */ - -extern volatile int32_t ITM_RxBuffer; /*!< External variable to receive characters. */ -#define ITM_RXBUFFER_EMPTY ((int32_t)0x5AA55AA5U) /*!< Value identifying \ref ITM_RxBuffer is ready for next character. */ - - -/** - \brief ITM Send Character - \details Transmits a character via the ITM channel 0, and - \li Just returns when no debugger is connected that has booked the output. - \li Is blocking when a debugger is connected, but the previous character sent has not been transmitted. - \param [in] ch Character to transmit. - \returns Character to transmit. - */ -__STATIC_INLINE uint32_t ITM_SendChar (uint32_t ch) -{ - if (((ITM->TCR & ITM_TCR_ITMENA_Msk) != 0UL) && /* ITM enabled */ - ((ITM->TER & 1UL ) != 0UL) ) /* ITM Port #0 enabled */ - { - while (ITM->PORT[0U].u32 == 0UL) - { - __NOP(); - } - ITM->PORT[0U].u8 = (uint8_t)ch; - } - return (ch); -} - - -/** - \brief ITM Receive Character - \details Inputs a character via the external variable \ref ITM_RxBuffer. - \return Received character. - \return -1 No character pending. - */ -__STATIC_INLINE int32_t ITM_ReceiveChar (void) -{ - int32_t ch = -1; /* no character available */ - - if (ITM_RxBuffer != ITM_RXBUFFER_EMPTY) - { - ch = ITM_RxBuffer; - ITM_RxBuffer = ITM_RXBUFFER_EMPTY; /* ready for next character */ - } - - return (ch); -} - - -/** - \brief ITM Check Character - \details Checks whether a character is pending for reading in the variable \ref ITM_RxBuffer. - \return 0 No character available. - \return 1 Character available. - */ -__STATIC_INLINE int32_t ITM_CheckChar (void) -{ - - if (ITM_RxBuffer == ITM_RXBUFFER_EMPTY) - { - return (0); /* no character available */ - } - else - { - return (1); /* character available */ - } -} - -/*@} end of CMSIS_core_DebugFunctions */ - - - - -#ifdef __cplusplus -} -#endif - -#endif /* __CORE_ARMV8MML_H_DEPENDANT */ - -#endif /* __CMSIS_GENERIC */ diff --git a/bsp/essemi/es32f0271/libraries/CMSIS/Include/core_cm0.h b/bsp/essemi/es32f0271/libraries/CMSIS/Include/core_cm0.h deleted file mode 100644 index a3f1b9ac33..0000000000 --- a/bsp/essemi/es32f0271/libraries/CMSIS/Include/core_cm0.h +++ /dev/null @@ -1,888 +0,0 @@ -/**************************************************************************//** - * @file core_cm0.h - * @brief CMSIS Cortex-M0 Core Peripheral Access Layer Header File - * @version V5.0.3 - * @date 10. January 2018 - ******************************************************************************/ -/* - * Copyright (c) 2009-2018 Arm Limited. All rights reserved. - * - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed under the Apache License, Version 2.0 (the License); you may - * not use this file except in compliance with the License. - * You may obtain a copy of the License at - * - * www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an AS IS BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - */ - -#if defined ( __ICCARM__ ) - #pragma system_include /* treat file as system include file for MISRA check */ -#elif defined (__clang__) - #pragma clang system_header /* treat file as system include file */ -#endif - -#ifndef __CORE_CM0_H_GENERIC -#define __CORE_CM0_H_GENERIC - -#include - -#ifdef __cplusplus - extern "C" { -#endif - -/** - \page CMSIS_MISRA_Exceptions MISRA-C:2004 Compliance Exceptions - CMSIS violates the following MISRA-C:2004 rules: - - \li Required Rule 8.5, object/function definition in header file.
- Function definitions in header files are used to allow 'inlining'. - - \li Required Rule 18.4, declaration of union type or object of union type: '{...}'.
- Unions are used for effective representation of core registers. - - \li Advisory Rule 19.7, Function-like macro defined.
- Function-like macros are used to allow more efficient code. - */ - - -/******************************************************************************* - * CMSIS definitions - ******************************************************************************/ -/** - \ingroup Cortex_M0 - @{ - */ - -#include "cmsis_version.h" - -/* CMSIS CM0 definitions */ -#define __CM0_CMSIS_VERSION_MAIN (__CM_CMSIS_VERSION_MAIN) /*!< \deprecated [31:16] CMSIS HAL main version */ -#define __CM0_CMSIS_VERSION_SUB (__CM_CMSIS_VERSION_SUB) /*!< \deprecated [15:0] CMSIS HAL sub version */ -#define __CM0_CMSIS_VERSION ((__CM0_CMSIS_VERSION_MAIN << 16U) | \ - __CM0_CMSIS_VERSION_SUB ) /*!< \deprecated CMSIS HAL version number */ - -#define __CORTEX_M (0U) /*!< Cortex-M Core */ - -/** __FPU_USED indicates whether an FPU is used or not. - This core does not support an FPU at all -*/ -#define __FPU_USED 0U - -#if defined ( __CC_ARM ) - #if defined __TARGET_FPU_VFP - #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" - #endif - -#elif defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) - #if defined __ARM_PCS_VFP - #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" - #endif - -#elif defined ( __GNUC__ ) - #if defined (__VFP_FP__) && !defined(__SOFTFP__) - #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" - #endif - -#elif defined ( __ICCARM__ ) - #if defined __ARMVFP__ - #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" - #endif - -#elif defined ( __TI_ARM__ ) - #if defined __TI_VFP_SUPPORT__ - #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" - #endif - -#elif defined ( __TASKING__ ) - #if defined __FPU_VFP__ - #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" - #endif - -#elif defined ( __CSMC__ ) - #if ( __CSMC__ & 0x400U) - #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" - #endif - -#endif - -#include "cmsis_compiler.h" /* CMSIS compiler specific defines */ - - -#ifdef __cplusplus -} -#endif - -#endif /* __CORE_CM0_H_GENERIC */ - -#ifndef __CMSIS_GENERIC - -#ifndef __CORE_CM0_H_DEPENDANT -#define __CORE_CM0_H_DEPENDANT - -#ifdef __cplusplus - extern "C" { -#endif - -/* check device defines and use defaults */ -#if defined __CHECK_DEVICE_DEFINES - #ifndef __CM0_REV - #define __CM0_REV 0x0000U - #warning "__CM0_REV not defined in device header file; using default!" - #endif - - #ifndef __NVIC_PRIO_BITS - #define __NVIC_PRIO_BITS 2U - #warning "__NVIC_PRIO_BITS not defined in device header file; using default!" - #endif - - #ifndef __Vendor_SysTickConfig - #define __Vendor_SysTickConfig 0U - #warning "__Vendor_SysTickConfig not defined in device header file; using default!" - #endif -#endif - -/* IO definitions (access restrictions to peripheral registers) */ -/** - \defgroup CMSIS_glob_defs CMSIS Global Defines - - IO Type Qualifiers are used - \li to specify the access to peripheral variables. - \li for automatic generation of peripheral register debug information. -*/ -#ifdef __cplusplus - #define __I volatile /*!< Defines 'read only' permissions */ -#else - #define __I volatile const /*!< Defines 'read only' permissions */ -#endif -#define __O volatile /*!< Defines 'write only' permissions */ -#define __IO volatile /*!< Defines 'read / write' permissions */ - -/* following defines should be used for structure members */ -#define __IM volatile const /*! Defines 'read only' structure member permissions */ -#define __OM volatile /*! Defines 'write only' structure member permissions */ -#define __IOM volatile /*! Defines 'read / write' structure member permissions */ - -/*@} end of group Cortex_M0 */ - - - -/******************************************************************************* - * Register Abstraction - Core Register contain: - - Core Register - - Core NVIC Register - - Core SCB Register - - Core SysTick Register - ******************************************************************************/ -/** - \defgroup CMSIS_core_register Defines and Type Definitions - \brief Type definitions and defines for Cortex-M processor based devices. -*/ - -/** - \ingroup CMSIS_core_register - \defgroup CMSIS_CORE Status and Control Registers - \brief Core Register type definitions. - @{ - */ - -/** - \brief Union type to access the Application Program Status Register (APSR). - */ -typedef union -{ - struct - { - uint32_t _reserved0:28; /*!< bit: 0..27 Reserved */ - uint32_t V:1; /*!< bit: 28 Overflow condition code flag */ - uint32_t C:1; /*!< bit: 29 Carry condition code flag */ - uint32_t Z:1; /*!< bit: 30 Zero condition code flag */ - uint32_t N:1; /*!< bit: 31 Negative condition code flag */ - } b; /*!< Structure used for bit access */ - uint32_t w; /*!< Type used for word access */ -} APSR_Type; - -/* APSR Register Definitions */ -#define APSR_N_Pos 31U /*!< APSR: N Position */ -#define APSR_N_Msk (1UL << APSR_N_Pos) /*!< APSR: N Mask */ - -#define APSR_Z_Pos 30U /*!< APSR: Z Position */ -#define APSR_Z_Msk (1UL << APSR_Z_Pos) /*!< APSR: Z Mask */ - -#define APSR_C_Pos 29U /*!< APSR: C Position */ -#define APSR_C_Msk (1UL << APSR_C_Pos) /*!< APSR: C Mask */ - -#define APSR_V_Pos 28U /*!< APSR: V Position */ -#define APSR_V_Msk (1UL << APSR_V_Pos) /*!< APSR: V Mask */ - - -/** - \brief Union type to access the Interrupt Program Status Register (IPSR). - */ -typedef union -{ - struct - { - uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */ - uint32_t _reserved0:23; /*!< bit: 9..31 Reserved */ - } b; /*!< Structure used for bit access */ - uint32_t w; /*!< Type used for word access */ -} IPSR_Type; - -/* IPSR Register Definitions */ -#define IPSR_ISR_Pos 0U /*!< IPSR: ISR Position */ -#define IPSR_ISR_Msk (0x1FFUL /*<< IPSR_ISR_Pos*/) /*!< IPSR: ISR Mask */ - - -/** - \brief Union type to access the Special-Purpose Program Status Registers (xPSR). - */ -typedef union -{ - struct - { - uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */ - uint32_t _reserved0:15; /*!< bit: 9..23 Reserved */ - uint32_t T:1; /*!< bit: 24 Thumb bit (read 0) */ - uint32_t _reserved1:3; /*!< bit: 25..27 Reserved */ - uint32_t V:1; /*!< bit: 28 Overflow condition code flag */ - uint32_t C:1; /*!< bit: 29 Carry condition code flag */ - uint32_t Z:1; /*!< bit: 30 Zero condition code flag */ - uint32_t N:1; /*!< bit: 31 Negative condition code flag */ - } b; /*!< Structure used for bit access */ - uint32_t w; /*!< Type used for word access */ -} xPSR_Type; - -/* xPSR Register Definitions */ -#define xPSR_N_Pos 31U /*!< xPSR: N Position */ -#define xPSR_N_Msk (1UL << xPSR_N_Pos) /*!< xPSR: N Mask */ - -#define xPSR_Z_Pos 30U /*!< xPSR: Z Position */ -#define xPSR_Z_Msk (1UL << xPSR_Z_Pos) /*!< xPSR: Z Mask */ - -#define xPSR_C_Pos 29U /*!< xPSR: C Position */ -#define xPSR_C_Msk (1UL << xPSR_C_Pos) /*!< xPSR: C Mask */ - -#define xPSR_V_Pos 28U /*!< xPSR: V Position */ -#define xPSR_V_Msk (1UL << xPSR_V_Pos) /*!< xPSR: V Mask */ - -#define xPSR_T_Pos 24U /*!< xPSR: T Position */ -#define xPSR_T_Msk (1UL << xPSR_T_Pos) /*!< xPSR: T Mask */ - -#define xPSR_ISR_Pos 0U /*!< xPSR: ISR Position */ -#define xPSR_ISR_Msk (0x1FFUL /*<< xPSR_ISR_Pos*/) /*!< xPSR: ISR Mask */ - - -/** - \brief Union type to access the Control Registers (CONTROL). - */ -typedef union -{ - struct - { - uint32_t _reserved0:1; /*!< bit: 0 Reserved */ - uint32_t SPSEL:1; /*!< bit: 1 Stack to be used */ - uint32_t _reserved1:30; /*!< bit: 2..31 Reserved */ - } b; /*!< Structure used for bit access */ - uint32_t w; /*!< Type used for word access */ -} CONTROL_Type; - -/* CONTROL Register Definitions */ -#define CONTROL_SPSEL_Pos 1U /*!< CONTROL: SPSEL Position */ -#define CONTROL_SPSEL_Msk (1UL << CONTROL_SPSEL_Pos) /*!< CONTROL: SPSEL Mask */ - -/*@} end of group CMSIS_CORE */ - - -/** - \ingroup CMSIS_core_register - \defgroup CMSIS_NVIC Nested Vectored Interrupt Controller (NVIC) - \brief Type definitions for the NVIC Registers - @{ - */ - -/** - \brief Structure type to access the Nested Vectored Interrupt Controller (NVIC). - */ -typedef struct -{ - __IOM uint32_t ISER[1U]; /*!< Offset: 0x000 (R/W) Interrupt Set Enable Register */ - uint32_t RESERVED0[31U]; - __IOM uint32_t ICER[1U]; /*!< Offset: 0x080 (R/W) Interrupt Clear Enable Register */ - uint32_t RSERVED1[31U]; - __IOM uint32_t ISPR[1U]; /*!< Offset: 0x100 (R/W) Interrupt Set Pending Register */ - uint32_t RESERVED2[31U]; - __IOM uint32_t ICPR[1U]; /*!< Offset: 0x180 (R/W) Interrupt Clear Pending Register */ - uint32_t RESERVED3[31U]; - uint32_t RESERVED4[64U]; - __IOM uint32_t IP[8U]; /*!< Offset: 0x300 (R/W) Interrupt Priority Register */ -} NVIC_Type; - -/*@} end of group CMSIS_NVIC */ - - -/** - \ingroup CMSIS_core_register - \defgroup CMSIS_SCB System Control Block (SCB) - \brief Type definitions for the System Control Block Registers - @{ - */ - -/** - \brief Structure type to access the System Control Block (SCB). - */ -typedef struct -{ - __IM uint32_t CPUID; /*!< Offset: 0x000 (R/ ) CPUID Base Register */ - __IOM uint32_t ICSR; /*!< Offset: 0x004 (R/W) Interrupt Control and State Register */ - uint32_t RESERVED0; - __IOM uint32_t AIRCR; /*!< Offset: 0x00C (R/W) Application Interrupt and Reset Control Register */ - __IOM uint32_t SCR; /*!< Offset: 0x010 (R/W) System Control Register */ - __IOM uint32_t CCR; /*!< Offset: 0x014 (R/W) Configuration Control Register */ - uint32_t RESERVED1; - __IOM uint32_t SHP[2U]; /*!< Offset: 0x01C (R/W) System Handlers Priority Registers. [0] is RESERVED */ - __IOM uint32_t SHCSR; /*!< Offset: 0x024 (R/W) System Handler Control and State Register */ -} SCB_Type; - -/* SCB CPUID Register Definitions */ -#define SCB_CPUID_IMPLEMENTER_Pos 24U /*!< SCB CPUID: IMPLEMENTER Position */ -#define SCB_CPUID_IMPLEMENTER_Msk (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos) /*!< SCB CPUID: IMPLEMENTER Mask */ - -#define SCB_CPUID_VARIANT_Pos 20U /*!< SCB CPUID: VARIANT Position */ -#define SCB_CPUID_VARIANT_Msk (0xFUL << SCB_CPUID_VARIANT_Pos) /*!< SCB CPUID: VARIANT Mask */ - -#define SCB_CPUID_ARCHITECTURE_Pos 16U /*!< SCB CPUID: ARCHITECTURE Position */ -#define SCB_CPUID_ARCHITECTURE_Msk (0xFUL << SCB_CPUID_ARCHITECTURE_Pos) /*!< SCB CPUID: ARCHITECTURE Mask */ - -#define SCB_CPUID_PARTNO_Pos 4U /*!< SCB CPUID: PARTNO Position */ -#define SCB_CPUID_PARTNO_Msk (0xFFFUL << SCB_CPUID_PARTNO_Pos) /*!< SCB CPUID: PARTNO Mask */ - -#define SCB_CPUID_REVISION_Pos 0U /*!< SCB CPUID: REVISION Position */ -#define SCB_CPUID_REVISION_Msk (0xFUL /*<< SCB_CPUID_REVISION_Pos*/) /*!< SCB CPUID: REVISION Mask */ - -/* SCB Interrupt Control State Register Definitions */ -#define SCB_ICSR_NMIPENDSET_Pos 31U /*!< SCB ICSR: NMIPENDSET Position */ -#define SCB_ICSR_NMIPENDSET_Msk (1UL << SCB_ICSR_NMIPENDSET_Pos) /*!< SCB ICSR: NMIPENDSET Mask */ - -#define SCB_ICSR_PENDSVSET_Pos 28U /*!< SCB ICSR: PENDSVSET Position */ -#define SCB_ICSR_PENDSVSET_Msk (1UL << SCB_ICSR_PENDSVSET_Pos) /*!< SCB ICSR: PENDSVSET Mask */ - -#define SCB_ICSR_PENDSVCLR_Pos 27U /*!< SCB ICSR: PENDSVCLR Position */ -#define SCB_ICSR_PENDSVCLR_Msk (1UL << SCB_ICSR_PENDSVCLR_Pos) /*!< SCB ICSR: PENDSVCLR Mask */ - -#define SCB_ICSR_PENDSTSET_Pos 26U /*!< SCB ICSR: PENDSTSET Position */ -#define SCB_ICSR_PENDSTSET_Msk (1UL << SCB_ICSR_PENDSTSET_Pos) /*!< SCB ICSR: PENDSTSET Mask */ - -#define SCB_ICSR_PENDSTCLR_Pos 25U /*!< SCB ICSR: PENDSTCLR Position */ -#define SCB_ICSR_PENDSTCLR_Msk (1UL << SCB_ICSR_PENDSTCLR_Pos) /*!< SCB ICSR: PENDSTCLR Mask */ - -#define SCB_ICSR_ISRPREEMPT_Pos 23U /*!< SCB ICSR: ISRPREEMPT Position */ -#define SCB_ICSR_ISRPREEMPT_Msk (1UL << SCB_ICSR_ISRPREEMPT_Pos) /*!< SCB ICSR: ISRPREEMPT Mask */ - -#define SCB_ICSR_ISRPENDING_Pos 22U /*!< SCB ICSR: ISRPENDING Position */ -#define SCB_ICSR_ISRPENDING_Msk (1UL << SCB_ICSR_ISRPENDING_Pos) /*!< SCB ICSR: ISRPENDING Mask */ - -#define SCB_ICSR_VECTPENDING_Pos 12U /*!< SCB ICSR: VECTPENDING Position */ -#define SCB_ICSR_VECTPENDING_Msk (0x1FFUL << SCB_ICSR_VECTPENDING_Pos) /*!< SCB ICSR: VECTPENDING Mask */ - -#define SCB_ICSR_VECTACTIVE_Pos 0U /*!< SCB ICSR: VECTACTIVE Position */ -#define SCB_ICSR_VECTACTIVE_Msk (0x1FFUL /*<< SCB_ICSR_VECTACTIVE_Pos*/) /*!< SCB ICSR: VECTACTIVE Mask */ - -/* SCB Application Interrupt and Reset Control Register Definitions */ -#define SCB_AIRCR_VECTKEY_Pos 16U /*!< SCB AIRCR: VECTKEY Position */ -#define SCB_AIRCR_VECTKEY_Msk (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos) /*!< SCB AIRCR: VECTKEY Mask */ - -#define SCB_AIRCR_VECTKEYSTAT_Pos 16U /*!< SCB AIRCR: VECTKEYSTAT Position */ -#define SCB_AIRCR_VECTKEYSTAT_Msk (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos) /*!< SCB AIRCR: VECTKEYSTAT Mask */ - -#define SCB_AIRCR_ENDIANESS_Pos 15U /*!< SCB AIRCR: ENDIANESS Position */ -#define SCB_AIRCR_ENDIANESS_Msk (1UL << SCB_AIRCR_ENDIANESS_Pos) /*!< SCB AIRCR: ENDIANESS Mask */ - -#define SCB_AIRCR_SYSRESETREQ_Pos 2U /*!< SCB AIRCR: SYSRESETREQ Position */ -#define SCB_AIRCR_SYSRESETREQ_Msk (1UL << SCB_AIRCR_SYSRESETREQ_Pos) /*!< SCB AIRCR: SYSRESETREQ Mask */ - -#define SCB_AIRCR_VECTCLRACTIVE_Pos 1U /*!< SCB AIRCR: VECTCLRACTIVE Position */ -#define SCB_AIRCR_VECTCLRACTIVE_Msk (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos) /*!< SCB AIRCR: VECTCLRACTIVE Mask */ - -/* SCB System Control Register Definitions */ -#define SCB_SCR_SEVONPEND_Pos 4U /*!< SCB SCR: SEVONPEND Position */ -#define SCB_SCR_SEVONPEND_Msk (1UL << SCB_SCR_SEVONPEND_Pos) /*!< SCB SCR: SEVONPEND Mask */ - -#define SCB_SCR_SLEEPDEEP_Pos 2U /*!< SCB SCR: SLEEPDEEP Position */ -#define SCB_SCR_SLEEPDEEP_Msk (1UL << SCB_SCR_SLEEPDEEP_Pos) /*!< SCB SCR: SLEEPDEEP Mask */ - -#define SCB_SCR_SLEEPONEXIT_Pos 1U /*!< SCB SCR: SLEEPONEXIT Position */ -#define SCB_SCR_SLEEPONEXIT_Msk (1UL << SCB_SCR_SLEEPONEXIT_Pos) /*!< SCB SCR: SLEEPONEXIT Mask */ - -/* SCB Configuration Control Register Definitions */ -#define SCB_CCR_STKALIGN_Pos 9U /*!< SCB CCR: STKALIGN Position */ -#define SCB_CCR_STKALIGN_Msk (1UL << SCB_CCR_STKALIGN_Pos) /*!< SCB CCR: STKALIGN Mask */ - -#define SCB_CCR_UNALIGN_TRP_Pos 3U /*!< SCB CCR: UNALIGN_TRP Position */ -#define SCB_CCR_UNALIGN_TRP_Msk (1UL << SCB_CCR_UNALIGN_TRP_Pos) /*!< SCB CCR: UNALIGN_TRP Mask */ - -/* SCB System Handler Control and State Register Definitions */ -#define SCB_SHCSR_SVCALLPENDED_Pos 15U /*!< SCB SHCSR: SVCALLPENDED Position */ -#define SCB_SHCSR_SVCALLPENDED_Msk (1UL << SCB_SHCSR_SVCALLPENDED_Pos) /*!< SCB SHCSR: SVCALLPENDED Mask */ - -/*@} end of group CMSIS_SCB */ - - -/** - \ingroup CMSIS_core_register - \defgroup CMSIS_SysTick System Tick Timer (SysTick) - \brief Type definitions for the System Timer Registers. - @{ - */ - -/** - \brief Structure type to access the System Timer (SysTick). - */ -typedef struct -{ - __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) SysTick Control and Status Register */ - __IOM uint32_t LOAD; /*!< Offset: 0x004 (R/W) SysTick Reload Value Register */ - __IOM uint32_t VAL; /*!< Offset: 0x008 (R/W) SysTick Current Value Register */ - __IM uint32_t CALIB; /*!< Offset: 0x00C (R/ ) SysTick Calibration Register */ -} SysTick_Type; - -/* SysTick Control / Status Register Definitions */ -#define SysTick_CTRL_COUNTFLAG_Pos 16U /*!< SysTick CTRL: COUNTFLAG Position */ -#define SysTick_CTRL_COUNTFLAG_Msk (1UL << SysTick_CTRL_COUNTFLAG_Pos) /*!< SysTick CTRL: COUNTFLAG Mask */ - -#define SysTick_CTRL_CLKSOURCE_Pos 2U /*!< SysTick CTRL: CLKSOURCE Position */ -#define SysTick_CTRL_CLKSOURCE_Msk (1UL << SysTick_CTRL_CLKSOURCE_Pos) /*!< SysTick CTRL: CLKSOURCE Mask */ - -#define SysTick_CTRL_TICKINT_Pos 1U /*!< SysTick CTRL: TICKINT Position */ -#define SysTick_CTRL_TICKINT_Msk (1UL << SysTick_CTRL_TICKINT_Pos) /*!< SysTick CTRL: TICKINT Mask */ - -#define SysTick_CTRL_ENABLE_Pos 0U /*!< SysTick CTRL: ENABLE Position */ -#define SysTick_CTRL_ENABLE_Msk (1UL /*<< SysTick_CTRL_ENABLE_Pos*/) /*!< SysTick CTRL: ENABLE Mask */ - -/* SysTick Reload Register Definitions */ -#define SysTick_LOAD_RELOAD_Pos 0U /*!< SysTick LOAD: RELOAD Position */ -#define SysTick_LOAD_RELOAD_Msk (0xFFFFFFUL /*<< SysTick_LOAD_RELOAD_Pos*/) /*!< SysTick LOAD: RELOAD Mask */ - -/* SysTick Current Register Definitions */ -#define SysTick_VAL_CURRENT_Pos 0U /*!< SysTick VAL: CURRENT Position */ -#define SysTick_VAL_CURRENT_Msk (0xFFFFFFUL /*<< SysTick_VAL_CURRENT_Pos*/) /*!< SysTick VAL: CURRENT Mask */ - -/* SysTick Calibration Register Definitions */ -#define SysTick_CALIB_NOREF_Pos 31U /*!< SysTick CALIB: NOREF Position */ -#define SysTick_CALIB_NOREF_Msk (1UL << SysTick_CALIB_NOREF_Pos) /*!< SysTick CALIB: NOREF Mask */ - -#define SysTick_CALIB_SKEW_Pos 30U /*!< SysTick CALIB: SKEW Position */ -#define SysTick_CALIB_SKEW_Msk (1UL << SysTick_CALIB_SKEW_Pos) /*!< SysTick CALIB: SKEW Mask */ - -#define SysTick_CALIB_TENMS_Pos 0U /*!< SysTick CALIB: TENMS Position */ -#define SysTick_CALIB_TENMS_Msk (0xFFFFFFUL /*<< SysTick_CALIB_TENMS_Pos*/) /*!< SysTick CALIB: TENMS Mask */ - -/*@} end of group CMSIS_SysTick */ - - -/** - \ingroup CMSIS_core_register - \defgroup CMSIS_CoreDebug Core Debug Registers (CoreDebug) - \brief Cortex-M0 Core Debug Registers (DCB registers, SHCSR, and DFSR) are only accessible over DAP and not via processor. - Therefore they are not covered by the Cortex-M0 header file. - @{ - */ -/*@} end of group CMSIS_CoreDebug */ - - -/** - \ingroup CMSIS_core_register - \defgroup CMSIS_core_bitfield Core register bit field macros - \brief Macros for use with bit field definitions (xxx_Pos, xxx_Msk). - @{ - */ - -/** - \brief Mask and shift a bit field value for use in a register bit range. - \param[in] field Name of the register bit field. - \param[in] value Value of the bit field. This parameter is interpreted as an uint32_t type. - \return Masked and shifted value. -*/ -#define _VAL2FLD(field, value) (((uint32_t)(value) << field ## _Pos) & field ## _Msk) - -/** - \brief Mask and shift a register value to extract a bit filed value. - \param[in] field Name of the register bit field. - \param[in] value Value of register. This parameter is interpreted as an uint32_t type. - \return Masked and shifted bit field value. -*/ -#define _FLD2VAL(field, value) (((uint32_t)(value) & field ## _Msk) >> field ## _Pos) - -/*@} end of group CMSIS_core_bitfield */ - - -/** - \ingroup CMSIS_core_register - \defgroup CMSIS_core_base Core Definitions - \brief Definitions for base addresses, unions, and structures. - @{ - */ - -/* Memory mapping of Core Hardware */ -#define SCS_BASE (0xE000E000UL) /*!< System Control Space Base Address */ -#define SysTick_BASE (SCS_BASE + 0x0010UL) /*!< SysTick Base Address */ -#define NVIC_BASE (SCS_BASE + 0x0100UL) /*!< NVIC Base Address */ -#define SCB_BASE (SCS_BASE + 0x0D00UL) /*!< System Control Block Base Address */ - -#define SCB ((SCB_Type *) SCB_BASE ) /*!< SCB configuration struct */ -#define SysTick ((SysTick_Type *) SysTick_BASE ) /*!< SysTick configuration struct */ -#define NVIC ((NVIC_Type *) NVIC_BASE ) /*!< NVIC configuration struct */ - - -/*@} */ - - - -/******************************************************************************* - * Hardware Abstraction Layer - Core Function Interface contains: - - Core NVIC Functions - - Core SysTick Functions - - Core Register Access Functions - ******************************************************************************/ -/** - \defgroup CMSIS_Core_FunctionInterface Functions and Instructions Reference -*/ - - - -/* ########################## NVIC functions #################################### */ -/** - \ingroup CMSIS_Core_FunctionInterface - \defgroup CMSIS_Core_NVICFunctions NVIC Functions - \brief Functions that manage interrupts and exceptions via the NVIC. - @{ - */ - -#ifdef CMSIS_NVIC_VIRTUAL - #ifndef CMSIS_NVIC_VIRTUAL_HEADER_FILE - #define CMSIS_NVIC_VIRTUAL_HEADER_FILE "cmsis_nvic_virtual.h" - #endif - #include CMSIS_NVIC_VIRTUAL_HEADER_FILE -#else -/*#define NVIC_SetPriorityGrouping __NVIC_SetPriorityGrouping not available for Cortex-M0 */ -/*#define NVIC_GetPriorityGrouping __NVIC_GetPriorityGrouping not available for Cortex-M0 */ - #define NVIC_EnableIRQ __NVIC_EnableIRQ - #define NVIC_GetEnableIRQ __NVIC_GetEnableIRQ - #define NVIC_DisableIRQ __NVIC_DisableIRQ - #define NVIC_GetPendingIRQ __NVIC_GetPendingIRQ - #define NVIC_SetPendingIRQ __NVIC_SetPendingIRQ - #define NVIC_ClearPendingIRQ __NVIC_ClearPendingIRQ -/*#define NVIC_GetActive __NVIC_GetActive not available for Cortex-M0 */ - #define NVIC_SetPriority __NVIC_SetPriority - #define NVIC_GetPriority __NVIC_GetPriority - #define NVIC_SystemReset __NVIC_SystemReset -#endif /* CMSIS_NVIC_VIRTUAL */ - -#ifdef CMSIS_VECTAB_VIRTUAL - #ifndef CMSIS_VECTAB_VIRTUAL_HEADER_FILE - #define CMSIS_VECTAB_VIRTUAL_HEADER_FILE "cmsis_vectab_virtual.h" - #endif - #include CMSIS_VECTAB_VIRTUAL_HEADER_FILE -#else - #define NVIC_SetVector __NVIC_SetVector - #define NVIC_GetVector __NVIC_GetVector -#endif /* (CMSIS_VECTAB_VIRTUAL) */ - -#define NVIC_USER_IRQ_OFFSET 16 - - -/* Interrupt Priorities are WORD accessible only under Armv6-M */ -/* The following MACROS handle generation of the register offset and byte masks */ -#define _BIT_SHIFT(IRQn) ( ((((uint32_t)(int32_t)(IRQn)) ) & 0x03UL) * 8UL) -#define _SHP_IDX(IRQn) ( (((((uint32_t)(int32_t)(IRQn)) & 0x0FUL)-8UL) >> 2UL) ) -#define _IP_IDX(IRQn) ( (((uint32_t)(int32_t)(IRQn)) >> 2UL) ) - - -/** - \brief Enable Interrupt - \details Enables a device specific interrupt in the NVIC interrupt controller. - \param [in] IRQn Device specific interrupt number. - \note IRQn must not be negative. - */ -__STATIC_INLINE void __NVIC_EnableIRQ(IRQn_Type IRQn) -{ - if ((int32_t)(IRQn) >= 0) - { - NVIC->ISER[0U] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); - } -} - - -/** - \brief Get Interrupt Enable status - \details Returns a device specific interrupt enable status from the NVIC interrupt controller. - \param [in] IRQn Device specific interrupt number. - \return 0 Interrupt is not enabled. - \return 1 Interrupt is enabled. - \note IRQn must not be negative. - */ -__STATIC_INLINE uint32_t __NVIC_GetEnableIRQ(IRQn_Type IRQn) -{ - if ((int32_t)(IRQn) >= 0) - { - return((uint32_t)(((NVIC->ISER[0U] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); - } - else - { - return(0U); - } -} - - -/** - \brief Disable Interrupt - \details Disables a device specific interrupt in the NVIC interrupt controller. - \param [in] IRQn Device specific interrupt number. - \note IRQn must not be negative. - */ -__STATIC_INLINE void __NVIC_DisableIRQ(IRQn_Type IRQn) -{ - if ((int32_t)(IRQn) >= 0) - { - NVIC->ICER[0U] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); - __DSB(); - __ISB(); - } -} - - -/** - \brief Get Pending Interrupt - \details Reads the NVIC pending register and returns the pending bit for the specified device specific interrupt. - \param [in] IRQn Device specific interrupt number. - \return 0 Interrupt status is not pending. - \return 1 Interrupt status is pending. - \note IRQn must not be negative. - */ -__STATIC_INLINE uint32_t __NVIC_GetPendingIRQ(IRQn_Type IRQn) -{ - if ((int32_t)(IRQn) >= 0) - { - return((uint32_t)(((NVIC->ISPR[0U] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); - } - else - { - return(0U); - } -} - - -/** - \brief Set Pending Interrupt - \details Sets the pending bit of a device specific interrupt in the NVIC pending register. - \param [in] IRQn Device specific interrupt number. - \note IRQn must not be negative. - */ -__STATIC_INLINE void __NVIC_SetPendingIRQ(IRQn_Type IRQn) -{ - if ((int32_t)(IRQn) >= 0) - { - NVIC->ISPR[0U] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); - } -} - - -/** - \brief Clear Pending Interrupt - \details Clears the pending bit of a device specific interrupt in the NVIC pending register. - \param [in] IRQn Device specific interrupt number. - \note IRQn must not be negative. - */ -__STATIC_INLINE void __NVIC_ClearPendingIRQ(IRQn_Type IRQn) -{ - if ((int32_t)(IRQn) >= 0) - { - NVIC->ICPR[0U] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); - } -} - - -/** - \brief Set Interrupt Priority - \details Sets the priority of a device specific interrupt or a processor exception. - The interrupt number can be positive to specify a device specific interrupt, - or negative to specify a processor exception. - \param [in] IRQn Interrupt number. - \param [in] priority Priority to set. - \note The priority cannot be set for every processor exception. - */ -__STATIC_INLINE void __NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority) -{ - if ((int32_t)(IRQn) >= 0) - { - NVIC->IP[_IP_IDX(IRQn)] = ((uint32_t)(NVIC->IP[_IP_IDX(IRQn)] & ~(0xFFUL << _BIT_SHIFT(IRQn))) | - (((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL) << _BIT_SHIFT(IRQn))); - } - else - { - SCB->SHP[_SHP_IDX(IRQn)] = ((uint32_t)(SCB->SHP[_SHP_IDX(IRQn)] & ~(0xFFUL << _BIT_SHIFT(IRQn))) | - (((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL) << _BIT_SHIFT(IRQn))); - } -} - - -/** - \brief Get Interrupt Priority - \details Reads the priority of a device specific interrupt or a processor exception. - The interrupt number can be positive to specify a device specific interrupt, - or negative to specify a processor exception. - \param [in] IRQn Interrupt number. - \return Interrupt Priority. - Value is aligned automatically to the implemented priority bits of the microcontroller. - */ -__STATIC_INLINE uint32_t __NVIC_GetPriority(IRQn_Type IRQn) -{ - - if ((int32_t)(IRQn) >= 0) - { - return((uint32_t)(((NVIC->IP[ _IP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) & (uint32_t)0xFFUL) >> (8U - __NVIC_PRIO_BITS))); - } - else - { - return((uint32_t)(((SCB->SHP[_SHP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) & (uint32_t)0xFFUL) >> (8U - __NVIC_PRIO_BITS))); - } -} - - -/** - \brief Set Interrupt Vector - \details Sets an interrupt vector in SRAM based interrupt vector table. - The interrupt number can be positive to specify a device specific interrupt, - or negative to specify a processor exception. - Address 0 must be mapped to SRAM. - \param [in] IRQn Interrupt number - \param [in] vector Address of interrupt handler function - */ -__STATIC_INLINE void __NVIC_SetVector(IRQn_Type IRQn, uint32_t vector) -{ - uint32_t *vectors = (uint32_t *)0x0U; - vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET] = vector; -} - - -/** - \brief Get Interrupt Vector - \details Reads an interrupt vector from interrupt vector table. - The interrupt number can be positive to specify a device specific interrupt, - or negative to specify a processor exception. - \param [in] IRQn Interrupt number. - \return Address of interrupt handler function - */ -__STATIC_INLINE uint32_t __NVIC_GetVector(IRQn_Type IRQn) -{ - uint32_t *vectors = (uint32_t *)0x0U; - return vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET]; -} - - -/** - \brief System Reset - \details Initiates a system reset request to reset the MCU. - */ -__STATIC_INLINE void __NVIC_SystemReset(void) -{ - __DSB(); /* Ensure all outstanding memory accesses included - buffered write are completed before reset */ - SCB->AIRCR = ((0x5FAUL << SCB_AIRCR_VECTKEY_Pos) | - SCB_AIRCR_SYSRESETREQ_Msk); - __DSB(); /* Ensure completion of memory access */ - - for(;;) /* wait until reset */ - { - __NOP(); - } -} - -/*@} end of CMSIS_Core_NVICFunctions */ - - -/* ########################## FPU functions #################################### */ -/** - \ingroup CMSIS_Core_FunctionInterface - \defgroup CMSIS_Core_FpuFunctions FPU Functions - \brief Function that provides FPU type. - @{ - */ - -/** - \brief get FPU type - \details returns the FPU type - \returns - - \b 0: No FPU - - \b 1: Single precision FPU - - \b 2: Double + Single precision FPU - */ -__STATIC_INLINE uint32_t SCB_GetFPUType(void) -{ - return 0U; /* No FPU */ -} - - -/*@} end of CMSIS_Core_FpuFunctions */ - - - -/* ################################## SysTick function ############################################ */ -/** - \ingroup CMSIS_Core_FunctionInterface - \defgroup CMSIS_Core_SysTickFunctions SysTick Functions - \brief Functions that configure the System. - @{ - */ - -#if defined (__Vendor_SysTickConfig) && (__Vendor_SysTickConfig == 0U) - -/** - \brief System Tick Configuration - \details Initializes the System Timer and its interrupt, and starts the System Tick Timer. - Counter is in free running mode to generate periodic interrupts. - \param [in] ticks Number of ticks between two interrupts. - \return 0 Function succeeded. - \return 1 Function failed. - \note When the variable __Vendor_SysTickConfig is set to 1, then the - function SysTick_Config is not included. In this case, the file device.h - must contain a vendor-specific implementation of this function. - */ -__STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks) -{ - if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk) - { - return (1UL); /* Reload value impossible */ - } - - SysTick->LOAD = (uint32_t)(ticks - 1UL); /* set reload register */ - NVIC_SetPriority (SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */ - SysTick->VAL = 0UL; /* Load the SysTick Counter Value */ - SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk | - SysTick_CTRL_TICKINT_Msk | - SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */ - return (0UL); /* Function successful */ -} - -#endif - -/*@} end of CMSIS_Core_SysTickFunctions */ - - - - -#ifdef __cplusplus -} -#endif - -#endif /* __CORE_CM0_H_DEPENDANT */ - -#endif /* __CMSIS_GENERIC */ diff --git a/bsp/essemi/es32f0271/libraries/CMSIS/Include/core_cm0plus.h b/bsp/essemi/es32f0271/libraries/CMSIS/Include/core_cm0plus.h deleted file mode 100644 index f8f30c3496..0000000000 --- a/bsp/essemi/es32f0271/libraries/CMSIS/Include/core_cm0plus.h +++ /dev/null @@ -1,1023 +0,0 @@ -/**************************************************************************//** - * @file core_cm0plus.h - * @brief CMSIS Cortex-M0+ Core Peripheral Access Layer Header File - * @version V5.0.4 - * @date 10. January 2018 - ******************************************************************************/ -/* - * Copyright (c) 2009-2018 Arm Limited. All rights reserved. - * - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed under the Apache License, Version 2.0 (the License); you may - * not use this file except in compliance with the License. - * You may obtain a copy of the License at - * - * www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an AS IS BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - */ - -#if defined ( __ICCARM__ ) - #pragma system_include /* treat file as system include file for MISRA check */ -#elif defined (__clang__) - #pragma clang system_header /* treat file as system include file */ -#endif - -#ifndef __CORE_CM0PLUS_H_GENERIC -#define __CORE_CM0PLUS_H_GENERIC - -#include - -#ifdef __cplusplus - extern "C" { -#endif - -/** - \page CMSIS_MISRA_Exceptions MISRA-C:2004 Compliance Exceptions - CMSIS violates the following MISRA-C:2004 rules: - - \li Required Rule 8.5, object/function definition in header file.
- Function definitions in header files are used to allow 'inlining'. - - \li Required Rule 18.4, declaration of union type or object of union type: '{...}'.
- Unions are used for effective representation of core registers. - - \li Advisory Rule 19.7, Function-like macro defined.
- Function-like macros are used to allow more efficient code. - */ - - -/******************************************************************************* - * CMSIS definitions - ******************************************************************************/ -/** - \ingroup Cortex-M0+ - @{ - */ - -#include "cmsis_version.h" - -/* CMSIS CM0+ definitions */ -#define __CM0PLUS_CMSIS_VERSION_MAIN (__CM_CMSIS_VERSION_MAIN) /*!< \deprecated [31:16] CMSIS HAL main version */ -#define __CM0PLUS_CMSIS_VERSION_SUB (__CM_CMSIS_VERSION_SUB) /*!< \deprecated [15:0] CMSIS HAL sub version */ -#define __CM0PLUS_CMSIS_VERSION ((__CM0PLUS_CMSIS_VERSION_MAIN << 16U) | \ - __CM0PLUS_CMSIS_VERSION_SUB ) /*!< \deprecated CMSIS HAL version number */ - -#define __CORTEX_M (0U) /*!< Cortex-M Core */ - -/** __FPU_USED indicates whether an FPU is used or not. - This core does not support an FPU at all -*/ -#define __FPU_USED 0U - -#if defined ( __CC_ARM ) - #if defined __TARGET_FPU_VFP - #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" - #endif - -#elif defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) - #if defined __ARM_PCS_VFP - #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" - #endif - -#elif defined ( __GNUC__ ) - #if defined (__VFP_FP__) && !defined(__SOFTFP__) - #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" - #endif - -#elif defined ( __ICCARM__ ) - #if defined __ARMVFP__ - #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" - #endif - -#elif defined ( __TI_ARM__ ) - #if defined __TI_VFP_SUPPORT__ - #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" - #endif - -#elif defined ( __TASKING__ ) - #if defined __FPU_VFP__ - #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" - #endif - -#elif defined ( __CSMC__ ) - #if ( __CSMC__ & 0x400U) - #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" - #endif - -#endif - -#include "cmsis_compiler.h" /* CMSIS compiler specific defines */ - - -#ifdef __cplusplus -} -#endif - -#endif /* __CORE_CM0PLUS_H_GENERIC */ - -#ifndef __CMSIS_GENERIC - -#ifndef __CORE_CM0PLUS_H_DEPENDANT -#define __CORE_CM0PLUS_H_DEPENDANT - -#ifdef __cplusplus - extern "C" { -#endif - -/* check device defines and use defaults */ -#if defined __CHECK_DEVICE_DEFINES - #ifndef __CM0PLUS_REV - #define __CM0PLUS_REV 0x0000U - #warning "__CM0PLUS_REV not defined in device header file; using default!" - #endif - - #ifndef __MPU_PRESENT - #define __MPU_PRESENT 0U - #warning "__MPU_PRESENT not defined in device header file; using default!" - #endif - - #ifndef __VTOR_PRESENT - #define __VTOR_PRESENT 0U - #warning "__VTOR_PRESENT not defined in device header file; using default!" - #endif - - #ifndef __NVIC_PRIO_BITS - #define __NVIC_PRIO_BITS 2U - #warning "__NVIC_PRIO_BITS not defined in device header file; using default!" - #endif - - #ifndef __Vendor_SysTickConfig - #define __Vendor_SysTickConfig 0U - #warning "__Vendor_SysTickConfig not defined in device header file; using default!" - #endif -#endif - -/* IO definitions (access restrictions to peripheral registers) */ -/** - \defgroup CMSIS_glob_defs CMSIS Global Defines - - IO Type Qualifiers are used - \li to specify the access to peripheral variables. - \li for automatic generation of peripheral register debug information. -*/ -#ifdef __cplusplus - #define __I volatile /*!< Defines 'read only' permissions */ -#else - #define __I volatile const /*!< Defines 'read only' permissions */ -#endif -#define __O volatile /*!< Defines 'write only' permissions */ -#define __IO volatile /*!< Defines 'read / write' permissions */ - -/* following defines should be used for structure members */ -#define __IM volatile const /*! Defines 'read only' structure member permissions */ -#define __OM volatile /*! Defines 'write only' structure member permissions */ -#define __IOM volatile /*! Defines 'read / write' structure member permissions */ - -/*@} end of group Cortex-M0+ */ - - - -/******************************************************************************* - * Register Abstraction - Core Register contain: - - Core Register - - Core NVIC Register - - Core SCB Register - - Core SysTick Register - - Core MPU Register - ******************************************************************************/ -/** - \defgroup CMSIS_core_register Defines and Type Definitions - \brief Type definitions and defines for Cortex-M processor based devices. -*/ - -/** - \ingroup CMSIS_core_register - \defgroup CMSIS_CORE Status and Control Registers - \brief Core Register type definitions. - @{ - */ - -/** - \brief Union type to access the Application Program Status Register (APSR). - */ -typedef union -{ - struct - { - uint32_t _reserved0:28; /*!< bit: 0..27 Reserved */ - uint32_t V:1; /*!< bit: 28 Overflow condition code flag */ - uint32_t C:1; /*!< bit: 29 Carry condition code flag */ - uint32_t Z:1; /*!< bit: 30 Zero condition code flag */ - uint32_t N:1; /*!< bit: 31 Negative condition code flag */ - } b; /*!< Structure used for bit access */ - uint32_t w; /*!< Type used for word access */ -} APSR_Type; - -/* APSR Register Definitions */ -#define APSR_N_Pos 31U /*!< APSR: N Position */ -#define APSR_N_Msk (1UL << APSR_N_Pos) /*!< APSR: N Mask */ - -#define APSR_Z_Pos 30U /*!< APSR: Z Position */ -#define APSR_Z_Msk (1UL << APSR_Z_Pos) /*!< APSR: Z Mask */ - -#define APSR_C_Pos 29U /*!< APSR: C Position */ -#define APSR_C_Msk (1UL << APSR_C_Pos) /*!< APSR: C Mask */ - -#define APSR_V_Pos 28U /*!< APSR: V Position */ -#define APSR_V_Msk (1UL << APSR_V_Pos) /*!< APSR: V Mask */ - - -/** - \brief Union type to access the Interrupt Program Status Register (IPSR). - */ -typedef union -{ - struct - { - uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */ - uint32_t _reserved0:23; /*!< bit: 9..31 Reserved */ - } b; /*!< Structure used for bit access */ - uint32_t w; /*!< Type used for word access */ -} IPSR_Type; - -/* IPSR Register Definitions */ -#define IPSR_ISR_Pos 0U /*!< IPSR: ISR Position */ -#define IPSR_ISR_Msk (0x1FFUL /*<< IPSR_ISR_Pos*/) /*!< IPSR: ISR Mask */ - - -/** - \brief Union type to access the Special-Purpose Program Status Registers (xPSR). - */ -typedef union -{ - struct - { - uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */ - uint32_t _reserved0:15; /*!< bit: 9..23 Reserved */ - uint32_t T:1; /*!< bit: 24 Thumb bit (read 0) */ - uint32_t _reserved1:3; /*!< bit: 25..27 Reserved */ - uint32_t V:1; /*!< bit: 28 Overflow condition code flag */ - uint32_t C:1; /*!< bit: 29 Carry condition code flag */ - uint32_t Z:1; /*!< bit: 30 Zero condition code flag */ - uint32_t N:1; /*!< bit: 31 Negative condition code flag */ - } b; /*!< Structure used for bit access */ - uint32_t w; /*!< Type used for word access */ -} xPSR_Type; - -/* xPSR Register Definitions */ -#define xPSR_N_Pos 31U /*!< xPSR: N Position */ -#define xPSR_N_Msk (1UL << xPSR_N_Pos) /*!< xPSR: N Mask */ - -#define xPSR_Z_Pos 30U /*!< xPSR: Z Position */ -#define xPSR_Z_Msk (1UL << xPSR_Z_Pos) /*!< xPSR: Z Mask */ - -#define xPSR_C_Pos 29U /*!< xPSR: C Position */ -#define xPSR_C_Msk (1UL << xPSR_C_Pos) /*!< xPSR: C Mask */ - -#define xPSR_V_Pos 28U /*!< xPSR: V Position */ -#define xPSR_V_Msk (1UL << xPSR_V_Pos) /*!< xPSR: V Mask */ - -#define xPSR_T_Pos 24U /*!< xPSR: T Position */ -#define xPSR_T_Msk (1UL << xPSR_T_Pos) /*!< xPSR: T Mask */ - -#define xPSR_ISR_Pos 0U /*!< xPSR: ISR Position */ -#define xPSR_ISR_Msk (0x1FFUL /*<< xPSR_ISR_Pos*/) /*!< xPSR: ISR Mask */ - - -/** - \brief Union type to access the Control Registers (CONTROL). - */ -typedef union -{ - struct - { - uint32_t nPRIV:1; /*!< bit: 0 Execution privilege in Thread mode */ - uint32_t SPSEL:1; /*!< bit: 1 Stack to be used */ - uint32_t _reserved1:30; /*!< bit: 2..31 Reserved */ - } b; /*!< Structure used for bit access */ - uint32_t w; /*!< Type used for word access */ -} CONTROL_Type; - -/* CONTROL Register Definitions */ -#define CONTROL_SPSEL_Pos 1U /*!< CONTROL: SPSEL Position */ -#define CONTROL_SPSEL_Msk (1UL << CONTROL_SPSEL_Pos) /*!< CONTROL: SPSEL Mask */ - -#define CONTROL_nPRIV_Pos 0U /*!< CONTROL: nPRIV Position */ -#define CONTROL_nPRIV_Msk (1UL /*<< CONTROL_nPRIV_Pos*/) /*!< CONTROL: nPRIV Mask */ - -/*@} end of group CMSIS_CORE */ - - -/** - \ingroup CMSIS_core_register - \defgroup CMSIS_NVIC Nested Vectored Interrupt Controller (NVIC) - \brief Type definitions for the NVIC Registers - @{ - */ - -/** - \brief Structure type to access the Nested Vectored Interrupt Controller (NVIC). - */ -typedef struct -{ - __IOM uint32_t ISER[1U]; /*!< Offset: 0x000 (R/W) Interrupt Set Enable Register */ - uint32_t RESERVED0[31U]; - __IOM uint32_t ICER[1U]; /*!< Offset: 0x080 (R/W) Interrupt Clear Enable Register */ - uint32_t RSERVED1[31U]; - __IOM uint32_t ISPR[1U]; /*!< Offset: 0x100 (R/W) Interrupt Set Pending Register */ - uint32_t RESERVED2[31U]; - __IOM uint32_t ICPR[1U]; /*!< Offset: 0x180 (R/W) Interrupt Clear Pending Register */ - uint32_t RESERVED3[31U]; - uint32_t RESERVED4[64U]; - __IOM uint32_t IP[8U]; /*!< Offset: 0x300 (R/W) Interrupt Priority Register */ -} NVIC_Type; - -/*@} end of group CMSIS_NVIC */ - - -/** - \ingroup CMSIS_core_register - \defgroup CMSIS_SCB System Control Block (SCB) - \brief Type definitions for the System Control Block Registers - @{ - */ - -/** - \brief Structure type to access the System Control Block (SCB). - */ -typedef struct -{ - __IM uint32_t CPUID; /*!< Offset: 0x000 (R/ ) CPUID Base Register */ - __IOM uint32_t ICSR; /*!< Offset: 0x004 (R/W) Interrupt Control and State Register */ -#if defined (__VTOR_PRESENT) && (__VTOR_PRESENT == 1U) - __IOM uint32_t VTOR; /*!< Offset: 0x008 (R/W) Vector Table Offset Register */ -#else - uint32_t RESERVED0; -#endif - __IOM uint32_t AIRCR; /*!< Offset: 0x00C (R/W) Application Interrupt and Reset Control Register */ - __IOM uint32_t SCR; /*!< Offset: 0x010 (R/W) System Control Register */ - __IOM uint32_t CCR; /*!< Offset: 0x014 (R/W) Configuration Control Register */ - uint32_t RESERVED1; - __IOM uint32_t SHP[2U]; /*!< Offset: 0x01C (R/W) System Handlers Priority Registers. [0] is RESERVED */ - __IOM uint32_t SHCSR; /*!< Offset: 0x024 (R/W) System Handler Control and State Register */ -} SCB_Type; - -/* SCB CPUID Register Definitions */ -#define SCB_CPUID_IMPLEMENTER_Pos 24U /*!< SCB CPUID: IMPLEMENTER Position */ -#define SCB_CPUID_IMPLEMENTER_Msk (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos) /*!< SCB CPUID: IMPLEMENTER Mask */ - -#define SCB_CPUID_VARIANT_Pos 20U /*!< SCB CPUID: VARIANT Position */ -#define SCB_CPUID_VARIANT_Msk (0xFUL << SCB_CPUID_VARIANT_Pos) /*!< SCB CPUID: VARIANT Mask */ - -#define SCB_CPUID_ARCHITECTURE_Pos 16U /*!< SCB CPUID: ARCHITECTURE Position */ -#define SCB_CPUID_ARCHITECTURE_Msk (0xFUL << SCB_CPUID_ARCHITECTURE_Pos) /*!< SCB CPUID: ARCHITECTURE Mask */ - -#define SCB_CPUID_PARTNO_Pos 4U /*!< SCB CPUID: PARTNO Position */ -#define SCB_CPUID_PARTNO_Msk (0xFFFUL << SCB_CPUID_PARTNO_Pos) /*!< SCB CPUID: PARTNO Mask */ - -#define SCB_CPUID_REVISION_Pos 0U /*!< SCB CPUID: REVISION Position */ -#define SCB_CPUID_REVISION_Msk (0xFUL /*<< SCB_CPUID_REVISION_Pos*/) /*!< SCB CPUID: REVISION Mask */ - -/* SCB Interrupt Control State Register Definitions */ -#define SCB_ICSR_NMIPENDSET_Pos 31U /*!< SCB ICSR: NMIPENDSET Position */ -#define SCB_ICSR_NMIPENDSET_Msk (1UL << SCB_ICSR_NMIPENDSET_Pos) /*!< SCB ICSR: NMIPENDSET Mask */ - -#define SCB_ICSR_PENDSVSET_Pos 28U /*!< SCB ICSR: PENDSVSET Position */ -#define SCB_ICSR_PENDSVSET_Msk (1UL << SCB_ICSR_PENDSVSET_Pos) /*!< SCB ICSR: PENDSVSET Mask */ - -#define SCB_ICSR_PENDSVCLR_Pos 27U /*!< SCB ICSR: PENDSVCLR Position */ -#define SCB_ICSR_PENDSVCLR_Msk (1UL << SCB_ICSR_PENDSVCLR_Pos) /*!< SCB ICSR: PENDSVCLR Mask */ - -#define SCB_ICSR_PENDSTSET_Pos 26U /*!< SCB ICSR: PENDSTSET Position */ -#define SCB_ICSR_PENDSTSET_Msk (1UL << SCB_ICSR_PENDSTSET_Pos) /*!< SCB ICSR: PENDSTSET Mask */ - -#define SCB_ICSR_PENDSTCLR_Pos 25U /*!< SCB ICSR: PENDSTCLR Position */ -#define SCB_ICSR_PENDSTCLR_Msk (1UL << SCB_ICSR_PENDSTCLR_Pos) /*!< SCB ICSR: PENDSTCLR Mask */ - -#define SCB_ICSR_ISRPREEMPT_Pos 23U /*!< SCB ICSR: ISRPREEMPT Position */ -#define SCB_ICSR_ISRPREEMPT_Msk (1UL << SCB_ICSR_ISRPREEMPT_Pos) /*!< SCB ICSR: ISRPREEMPT Mask */ - -#define SCB_ICSR_ISRPENDING_Pos 22U /*!< SCB ICSR: ISRPENDING Position */ -#define SCB_ICSR_ISRPENDING_Msk (1UL << SCB_ICSR_ISRPENDING_Pos) /*!< SCB ICSR: ISRPENDING Mask */ - -#define SCB_ICSR_VECTPENDING_Pos 12U /*!< SCB ICSR: VECTPENDING Position */ -#define SCB_ICSR_VECTPENDING_Msk (0x1FFUL << SCB_ICSR_VECTPENDING_Pos) /*!< SCB ICSR: VECTPENDING Mask */ - -#define SCB_ICSR_VECTACTIVE_Pos 0U /*!< SCB ICSR: VECTACTIVE Position */ -#define SCB_ICSR_VECTACTIVE_Msk (0x1FFUL /*<< SCB_ICSR_VECTACTIVE_Pos*/) /*!< SCB ICSR: VECTACTIVE Mask */ - -#if defined (__VTOR_PRESENT) && (__VTOR_PRESENT == 1U) -/* SCB Interrupt Control State Register Definitions */ -#define SCB_VTOR_TBLOFF_Pos 8U /*!< SCB VTOR: TBLOFF Position */ -#define SCB_VTOR_TBLOFF_Msk (0xFFFFFFUL << SCB_VTOR_TBLOFF_Pos) /*!< SCB VTOR: TBLOFF Mask */ -#endif - -/* SCB Application Interrupt and Reset Control Register Definitions */ -#define SCB_AIRCR_VECTKEY_Pos 16U /*!< SCB AIRCR: VECTKEY Position */ -#define SCB_AIRCR_VECTKEY_Msk (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos) /*!< SCB AIRCR: VECTKEY Mask */ - -#define SCB_AIRCR_VECTKEYSTAT_Pos 16U /*!< SCB AIRCR: VECTKEYSTAT Position */ -#define SCB_AIRCR_VECTKEYSTAT_Msk (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos) /*!< SCB AIRCR: VECTKEYSTAT Mask */ - -#define SCB_AIRCR_ENDIANESS_Pos 15U /*!< SCB AIRCR: ENDIANESS Position */ -#define SCB_AIRCR_ENDIANESS_Msk (1UL << SCB_AIRCR_ENDIANESS_Pos) /*!< SCB AIRCR: ENDIANESS Mask */ - -#define SCB_AIRCR_SYSRESETREQ_Pos 2U /*!< SCB AIRCR: SYSRESETREQ Position */ -#define SCB_AIRCR_SYSRESETREQ_Msk (1UL << SCB_AIRCR_SYSRESETREQ_Pos) /*!< SCB AIRCR: SYSRESETREQ Mask */ - -#define SCB_AIRCR_VECTCLRACTIVE_Pos 1U /*!< SCB AIRCR: VECTCLRACTIVE Position */ -#define SCB_AIRCR_VECTCLRACTIVE_Msk (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos) /*!< SCB AIRCR: VECTCLRACTIVE Mask */ - -/* SCB System Control Register Definitions */ -#define SCB_SCR_SEVONPEND_Pos 4U /*!< SCB SCR: SEVONPEND Position */ -#define SCB_SCR_SEVONPEND_Msk (1UL << SCB_SCR_SEVONPEND_Pos) /*!< SCB SCR: SEVONPEND Mask */ - -#define SCB_SCR_SLEEPDEEP_Pos 2U /*!< SCB SCR: SLEEPDEEP Position */ -#define SCB_SCR_SLEEPDEEP_Msk (1UL << SCB_SCR_SLEEPDEEP_Pos) /*!< SCB SCR: SLEEPDEEP Mask */ - -#define SCB_SCR_SLEEPONEXIT_Pos 1U /*!< SCB SCR: SLEEPONEXIT Position */ -#define SCB_SCR_SLEEPONEXIT_Msk (1UL << SCB_SCR_SLEEPONEXIT_Pos) /*!< SCB SCR: SLEEPONEXIT Mask */ - -/* SCB Configuration Control Register Definitions */ -#define SCB_CCR_STKALIGN_Pos 9U /*!< SCB CCR: STKALIGN Position */ -#define SCB_CCR_STKALIGN_Msk (1UL << SCB_CCR_STKALIGN_Pos) /*!< SCB CCR: STKALIGN Mask */ - -#define SCB_CCR_UNALIGN_TRP_Pos 3U /*!< SCB CCR: UNALIGN_TRP Position */ -#define SCB_CCR_UNALIGN_TRP_Msk (1UL << SCB_CCR_UNALIGN_TRP_Pos) /*!< SCB CCR: UNALIGN_TRP Mask */ - -/* SCB System Handler Control and State Register Definitions */ -#define SCB_SHCSR_SVCALLPENDED_Pos 15U /*!< SCB SHCSR: SVCALLPENDED Position */ -#define SCB_SHCSR_SVCALLPENDED_Msk (1UL << SCB_SHCSR_SVCALLPENDED_Pos) /*!< SCB SHCSR: SVCALLPENDED Mask */ - -/*@} end of group CMSIS_SCB */ - - -/** - \ingroup CMSIS_core_register - \defgroup CMSIS_SysTick System Tick Timer (SysTick) - \brief Type definitions for the System Timer Registers. - @{ - */ - -/** - \brief Structure type to access the System Timer (SysTick). - */ -typedef struct -{ - __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) SysTick Control and Status Register */ - __IOM uint32_t LOAD; /*!< Offset: 0x004 (R/W) SysTick Reload Value Register */ - __IOM uint32_t VAL; /*!< Offset: 0x008 (R/W) SysTick Current Value Register */ - __IM uint32_t CALIB; /*!< Offset: 0x00C (R/ ) SysTick Calibration Register */ -} SysTick_Type; - -/* SysTick Control / Status Register Definitions */ -#define SysTick_CTRL_COUNTFLAG_Pos 16U /*!< SysTick CTRL: COUNTFLAG Position */ -#define SysTick_CTRL_COUNTFLAG_Msk (1UL << SysTick_CTRL_COUNTFLAG_Pos) /*!< SysTick CTRL: COUNTFLAG Mask */ - -#define SysTick_CTRL_CLKSOURCE_Pos 2U /*!< SysTick CTRL: CLKSOURCE Position */ -#define SysTick_CTRL_CLKSOURCE_Msk (1UL << SysTick_CTRL_CLKSOURCE_Pos) /*!< SysTick CTRL: CLKSOURCE Mask */ - -#define SysTick_CTRL_TICKINT_Pos 1U /*!< SysTick CTRL: TICKINT Position */ -#define SysTick_CTRL_TICKINT_Msk (1UL << SysTick_CTRL_TICKINT_Pos) /*!< SysTick CTRL: TICKINT Mask */ - -#define SysTick_CTRL_ENABLE_Pos 0U /*!< SysTick CTRL: ENABLE Position */ -#define SysTick_CTRL_ENABLE_Msk (1UL /*<< SysTick_CTRL_ENABLE_Pos*/) /*!< SysTick CTRL: ENABLE Mask */ - -/* SysTick Reload Register Definitions */ -#define SysTick_LOAD_RELOAD_Pos 0U /*!< SysTick LOAD: RELOAD Position */ -#define SysTick_LOAD_RELOAD_Msk (0xFFFFFFUL /*<< SysTick_LOAD_RELOAD_Pos*/) /*!< SysTick LOAD: RELOAD Mask */ - -/* SysTick Current Register Definitions */ -#define SysTick_VAL_CURRENT_Pos 0U /*!< SysTick VAL: CURRENT Position */ -#define SysTick_VAL_CURRENT_Msk (0xFFFFFFUL /*<< SysTick_VAL_CURRENT_Pos*/) /*!< SysTick VAL: CURRENT Mask */ - -/* SysTick Calibration Register Definitions */ -#define SysTick_CALIB_NOREF_Pos 31U /*!< SysTick CALIB: NOREF Position */ -#define SysTick_CALIB_NOREF_Msk (1UL << SysTick_CALIB_NOREF_Pos) /*!< SysTick CALIB: NOREF Mask */ - -#define SysTick_CALIB_SKEW_Pos 30U /*!< SysTick CALIB: SKEW Position */ -#define SysTick_CALIB_SKEW_Msk (1UL << SysTick_CALIB_SKEW_Pos) /*!< SysTick CALIB: SKEW Mask */ - -#define SysTick_CALIB_TENMS_Pos 0U /*!< SysTick CALIB: TENMS Position */ -#define SysTick_CALIB_TENMS_Msk (0xFFFFFFUL /*<< SysTick_CALIB_TENMS_Pos*/) /*!< SysTick CALIB: TENMS Mask */ - -/*@} end of group CMSIS_SysTick */ - -#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) -/** - \ingroup CMSIS_core_register - \defgroup CMSIS_MPU Memory Protection Unit (MPU) - \brief Type definitions for the Memory Protection Unit (MPU) - @{ - */ - -/** - \brief Structure type to access the Memory Protection Unit (MPU). - */ -typedef struct -{ - __IM uint32_t TYPE; /*!< Offset: 0x000 (R/ ) MPU Type Register */ - __IOM uint32_t CTRL; /*!< Offset: 0x004 (R/W) MPU Control Register */ - __IOM uint32_t RNR; /*!< Offset: 0x008 (R/W) MPU Region RNRber Register */ - __IOM uint32_t RBAR; /*!< Offset: 0x00C (R/W) MPU Region Base Address Register */ - __IOM uint32_t RASR; /*!< Offset: 0x010 (R/W) MPU Region Attribute and Size Register */ -} MPU_Type; - -#define MPU_TYPE_RALIASES 1U - -/* MPU Type Register Definitions */ -#define MPU_TYPE_IREGION_Pos 16U /*!< MPU TYPE: IREGION Position */ -#define MPU_TYPE_IREGION_Msk (0xFFUL << MPU_TYPE_IREGION_Pos) /*!< MPU TYPE: IREGION Mask */ - -#define MPU_TYPE_DREGION_Pos 8U /*!< MPU TYPE: DREGION Position */ -#define MPU_TYPE_DREGION_Msk (0xFFUL << MPU_TYPE_DREGION_Pos) /*!< MPU TYPE: DREGION Mask */ - -#define MPU_TYPE_SEPARATE_Pos 0U /*!< MPU TYPE: SEPARATE Position */ -#define MPU_TYPE_SEPARATE_Msk (1UL /*<< MPU_TYPE_SEPARATE_Pos*/) /*!< MPU TYPE: SEPARATE Mask */ - -/* MPU Control Register Definitions */ -#define MPU_CTRL_PRIVDEFENA_Pos 2U /*!< MPU CTRL: PRIVDEFENA Position */ -#define MPU_CTRL_PRIVDEFENA_Msk (1UL << MPU_CTRL_PRIVDEFENA_Pos) /*!< MPU CTRL: PRIVDEFENA Mask */ - -#define MPU_CTRL_HFNMIENA_Pos 1U /*!< MPU CTRL: HFNMIENA Position */ -#define MPU_CTRL_HFNMIENA_Msk (1UL << MPU_CTRL_HFNMIENA_Pos) /*!< MPU CTRL: HFNMIENA Mask */ - -#define MPU_CTRL_ENABLE_Pos 0U /*!< MPU CTRL: ENABLE Position */ -#define MPU_CTRL_ENABLE_Msk (1UL /*<< MPU_CTRL_ENABLE_Pos*/) /*!< MPU CTRL: ENABLE Mask */ - -/* MPU Region Number Register Definitions */ -#define MPU_RNR_REGION_Pos 0U /*!< MPU RNR: REGION Position */ -#define MPU_RNR_REGION_Msk (0xFFUL /*<< MPU_RNR_REGION_Pos*/) /*!< MPU RNR: REGION Mask */ - -/* MPU Region Base Address Register Definitions */ -#define MPU_RBAR_ADDR_Pos 8U /*!< MPU RBAR: ADDR Position */ -#define MPU_RBAR_ADDR_Msk (0xFFFFFFUL << MPU_RBAR_ADDR_Pos) /*!< MPU RBAR: ADDR Mask */ - -#define MPU_RBAR_VALID_Pos 4U /*!< MPU RBAR: VALID Position */ -#define MPU_RBAR_VALID_Msk (1UL << MPU_RBAR_VALID_Pos) /*!< MPU RBAR: VALID Mask */ - -#define MPU_RBAR_REGION_Pos 0U /*!< MPU RBAR: REGION Position */ -#define MPU_RBAR_REGION_Msk (0xFUL /*<< MPU_RBAR_REGION_Pos*/) /*!< MPU RBAR: REGION Mask */ - -/* MPU Region Attribute and Size Register Definitions */ -#define MPU_RASR_ATTRS_Pos 16U /*!< MPU RASR: MPU Region Attribute field Position */ -#define MPU_RASR_ATTRS_Msk (0xFFFFUL << MPU_RASR_ATTRS_Pos) /*!< MPU RASR: MPU Region Attribute field Mask */ - -#define MPU_RASR_XN_Pos 28U /*!< MPU RASR: ATTRS.XN Position */ -#define MPU_RASR_XN_Msk (1UL << MPU_RASR_XN_Pos) /*!< MPU RASR: ATTRS.XN Mask */ - -#define MPU_RASR_AP_Pos 24U /*!< MPU RASR: ATTRS.AP Position */ -#define MPU_RASR_AP_Msk (0x7UL << MPU_RASR_AP_Pos) /*!< MPU RASR: ATTRS.AP Mask */ - -#define MPU_RASR_TEX_Pos 19U /*!< MPU RASR: ATTRS.TEX Position */ -#define MPU_RASR_TEX_Msk (0x7UL << MPU_RASR_TEX_Pos) /*!< MPU RASR: ATTRS.TEX Mask */ - -#define MPU_RASR_S_Pos 18U /*!< MPU RASR: ATTRS.S Position */ -#define MPU_RASR_S_Msk (1UL << MPU_RASR_S_Pos) /*!< MPU RASR: ATTRS.S Mask */ - -#define MPU_RASR_C_Pos 17U /*!< MPU RASR: ATTRS.C Position */ -#define MPU_RASR_C_Msk (1UL << MPU_RASR_C_Pos) /*!< MPU RASR: ATTRS.C Mask */ - -#define MPU_RASR_B_Pos 16U /*!< MPU RASR: ATTRS.B Position */ -#define MPU_RASR_B_Msk (1UL << MPU_RASR_B_Pos) /*!< MPU RASR: ATTRS.B Mask */ - -#define MPU_RASR_SRD_Pos 8U /*!< MPU RASR: Sub-Region Disable Position */ -#define MPU_RASR_SRD_Msk (0xFFUL << MPU_RASR_SRD_Pos) /*!< MPU RASR: Sub-Region Disable Mask */ - -#define MPU_RASR_SIZE_Pos 1U /*!< MPU RASR: Region Size Field Position */ -#define MPU_RASR_SIZE_Msk (0x1FUL << MPU_RASR_SIZE_Pos) /*!< MPU RASR: Region Size Field Mask */ - -#define MPU_RASR_ENABLE_Pos 0U /*!< MPU RASR: Region enable bit Position */ -#define MPU_RASR_ENABLE_Msk (1UL /*<< MPU_RASR_ENABLE_Pos*/) /*!< MPU RASR: Region enable bit Disable Mask */ - -/*@} end of group CMSIS_MPU */ -#endif - - -/** - \ingroup CMSIS_core_register - \defgroup CMSIS_CoreDebug Core Debug Registers (CoreDebug) - \brief Cortex-M0+ Core Debug Registers (DCB registers, SHCSR, and DFSR) are only accessible over DAP and not via processor. - Therefore they are not covered by the Cortex-M0+ header file. - @{ - */ -/*@} end of group CMSIS_CoreDebug */ - - -/** - \ingroup CMSIS_core_register - \defgroup CMSIS_core_bitfield Core register bit field macros - \brief Macros for use with bit field definitions (xxx_Pos, xxx_Msk). - @{ - */ - -/** - \brief Mask and shift a bit field value for use in a register bit range. - \param[in] field Name of the register bit field. - \param[in] value Value of the bit field. This parameter is interpreted as an uint32_t type. - \return Masked and shifted value. -*/ -#define _VAL2FLD(field, value) (((uint32_t)(value) << field ## _Pos) & field ## _Msk) - -/** - \brief Mask and shift a register value to extract a bit filed value. - \param[in] field Name of the register bit field. - \param[in] value Value of register. This parameter is interpreted as an uint32_t type. - \return Masked and shifted bit field value. -*/ -#define _FLD2VAL(field, value) (((uint32_t)(value) & field ## _Msk) >> field ## _Pos) - -/*@} end of group CMSIS_core_bitfield */ - - -/** - \ingroup CMSIS_core_register - \defgroup CMSIS_core_base Core Definitions - \brief Definitions for base addresses, unions, and structures. - @{ - */ - -/* Memory mapping of Core Hardware */ -#define SCS_BASE (0xE000E000UL) /*!< System Control Space Base Address */ -#define SysTick_BASE (SCS_BASE + 0x0010UL) /*!< SysTick Base Address */ -#define NVIC_BASE (SCS_BASE + 0x0100UL) /*!< NVIC Base Address */ -#define SCB_BASE (SCS_BASE + 0x0D00UL) /*!< System Control Block Base Address */ - -#define SCB ((SCB_Type *) SCB_BASE ) /*!< SCB configuration struct */ -#define SysTick ((SysTick_Type *) SysTick_BASE ) /*!< SysTick configuration struct */ -#define NVIC ((NVIC_Type *) NVIC_BASE ) /*!< NVIC configuration struct */ - -#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) - #define MPU_BASE (SCS_BASE + 0x0D90UL) /*!< Memory Protection Unit */ - #define MPU ((MPU_Type *) MPU_BASE ) /*!< Memory Protection Unit */ -#endif - -/*@} */ - - - -/******************************************************************************* - * Hardware Abstraction Layer - Core Function Interface contains: - - Core NVIC Functions - - Core SysTick Functions - - Core Register Access Functions - ******************************************************************************/ -/** - \defgroup CMSIS_Core_FunctionInterface Functions and Instructions Reference -*/ - - - -/* ########################## NVIC functions #################################### */ -/** - \ingroup CMSIS_Core_FunctionInterface - \defgroup CMSIS_Core_NVICFunctions NVIC Functions - \brief Functions that manage interrupts and exceptions via the NVIC. - @{ - */ - -#ifdef CMSIS_NVIC_VIRTUAL - #ifndef CMSIS_NVIC_VIRTUAL_HEADER_FILE - #define CMSIS_NVIC_VIRTUAL_HEADER_FILE "cmsis_nvic_virtual.h" - #endif - #include CMSIS_NVIC_VIRTUAL_HEADER_FILE -#else -/*#define NVIC_SetPriorityGrouping __NVIC_SetPriorityGrouping not available for Cortex-M0+ */ -/*#define NVIC_GetPriorityGrouping __NVIC_GetPriorityGrouping not available for Cortex-M0+ */ - #define NVIC_EnableIRQ __NVIC_EnableIRQ - #define NVIC_GetEnableIRQ __NVIC_GetEnableIRQ - #define NVIC_DisableIRQ __NVIC_DisableIRQ - #define NVIC_GetPendingIRQ __NVIC_GetPendingIRQ - #define NVIC_SetPendingIRQ __NVIC_SetPendingIRQ - #define NVIC_ClearPendingIRQ __NVIC_ClearPendingIRQ -/*#define NVIC_GetActive __NVIC_GetActive not available for Cortex-M0+ */ - #define NVIC_SetPriority __NVIC_SetPriority - #define NVIC_GetPriority __NVIC_GetPriority - #define NVIC_SystemReset __NVIC_SystemReset -#endif /* CMSIS_NVIC_VIRTUAL */ - -#ifdef CMSIS_VECTAB_VIRTUAL - #ifndef CMSIS_VECTAB_VIRTUAL_HEADER_FILE - #define CMSIS_VECTAB_VIRTUAL_HEADER_FILE "cmsis_vectab_virtual.h" - #endif - #include CMSIS_VECTAB_VIRTUAL_HEADER_FILE -#else - #define NVIC_SetVector __NVIC_SetVector - #define NVIC_GetVector __NVIC_GetVector -#endif /* (CMSIS_VECTAB_VIRTUAL) */ - -#define NVIC_USER_IRQ_OFFSET 16 - - -/* Interrupt Priorities are WORD accessible only under Armv6-M */ -/* The following MACROS handle generation of the register offset and byte masks */ -#define _BIT_SHIFT(IRQn) ( ((((uint32_t)(int32_t)(IRQn)) ) & 0x03UL) * 8UL) -#define _SHP_IDX(IRQn) ( (((((uint32_t)(int32_t)(IRQn)) & 0x0FUL)-8UL) >> 2UL) ) -#define _IP_IDX(IRQn) ( (((uint32_t)(int32_t)(IRQn)) >> 2UL) ) - - -/** - \brief Enable Interrupt - \details Enables a device specific interrupt in the NVIC interrupt controller. - \param [in] IRQn Device specific interrupt number. - \note IRQn must not be negative. - */ -__STATIC_INLINE void __NVIC_EnableIRQ(IRQn_Type IRQn) -{ - if ((int32_t)(IRQn) >= 0) - { - NVIC->ISER[0U] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); - } -} - - -/** - \brief Get Interrupt Enable status - \details Returns a device specific interrupt enable status from the NVIC interrupt controller. - \param [in] IRQn Device specific interrupt number. - \return 0 Interrupt is not enabled. - \return 1 Interrupt is enabled. - \note IRQn must not be negative. - */ -__STATIC_INLINE uint32_t __NVIC_GetEnableIRQ(IRQn_Type IRQn) -{ - if ((int32_t)(IRQn) >= 0) - { - return((uint32_t)(((NVIC->ISER[0U] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); - } - else - { - return(0U); - } -} - - -/** - \brief Disable Interrupt - \details Disables a device specific interrupt in the NVIC interrupt controller. - \param [in] IRQn Device specific interrupt number. - \note IRQn must not be negative. - */ -__STATIC_INLINE void __NVIC_DisableIRQ(IRQn_Type IRQn) -{ - if ((int32_t)(IRQn) >= 0) - { - NVIC->ICER[0U] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); - __DSB(); - __ISB(); - } -} - - -/** - \brief Get Pending Interrupt - \details Reads the NVIC pending register and returns the pending bit for the specified device specific interrupt. - \param [in] IRQn Device specific interrupt number. - \return 0 Interrupt status is not pending. - \return 1 Interrupt status is pending. - \note IRQn must not be negative. - */ -__STATIC_INLINE uint32_t __NVIC_GetPendingIRQ(IRQn_Type IRQn) -{ - if ((int32_t)(IRQn) >= 0) - { - return((uint32_t)(((NVIC->ISPR[0U] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); - } - else - { - return(0U); - } -} - - -/** - \brief Set Pending Interrupt - \details Sets the pending bit of a device specific interrupt in the NVIC pending register. - \param [in] IRQn Device specific interrupt number. - \note IRQn must not be negative. - */ -__STATIC_INLINE void __NVIC_SetPendingIRQ(IRQn_Type IRQn) -{ - if ((int32_t)(IRQn) >= 0) - { - NVIC->ISPR[0U] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); - } -} - - -/** - \brief Clear Pending Interrupt - \details Clears the pending bit of a device specific interrupt in the NVIC pending register. - \param [in] IRQn Device specific interrupt number. - \note IRQn must not be negative. - */ -__STATIC_INLINE void __NVIC_ClearPendingIRQ(IRQn_Type IRQn) -{ - if ((int32_t)(IRQn) >= 0) - { - NVIC->ICPR[0U] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); - } -} - - -/** - \brief Set Interrupt Priority - \details Sets the priority of a device specific interrupt or a processor exception. - The interrupt number can be positive to specify a device specific interrupt, - or negative to specify a processor exception. - \param [in] IRQn Interrupt number. - \param [in] priority Priority to set. - \note The priority cannot be set for every processor exception. - */ -__STATIC_INLINE void __NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority) -{ - if ((int32_t)(IRQn) >= 0) - { - NVIC->IP[_IP_IDX(IRQn)] = ((uint32_t)(NVIC->IP[_IP_IDX(IRQn)] & ~(0xFFUL << _BIT_SHIFT(IRQn))) | - (((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL) << _BIT_SHIFT(IRQn))); - } - else - { - SCB->SHP[_SHP_IDX(IRQn)] = ((uint32_t)(SCB->SHP[_SHP_IDX(IRQn)] & ~(0xFFUL << _BIT_SHIFT(IRQn))) | - (((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL) << _BIT_SHIFT(IRQn))); - } -} - - -/** - \brief Get Interrupt Priority - \details Reads the priority of a device specific interrupt or a processor exception. - The interrupt number can be positive to specify a device specific interrupt, - or negative to specify a processor exception. - \param [in] IRQn Interrupt number. - \return Interrupt Priority. - Value is aligned automatically to the implemented priority bits of the microcontroller. - */ -__STATIC_INLINE uint32_t __NVIC_GetPriority(IRQn_Type IRQn) -{ - - if ((int32_t)(IRQn) >= 0) - { - return((uint32_t)(((NVIC->IP[ _IP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) & (uint32_t)0xFFUL) >> (8U - __NVIC_PRIO_BITS))); - } - else - { - return((uint32_t)(((SCB->SHP[_SHP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) & (uint32_t)0xFFUL) >> (8U - __NVIC_PRIO_BITS))); - } -} - - -/** - \brief Set Interrupt Vector - \details Sets an interrupt vector in SRAM based interrupt vector table. - The interrupt number can be positive to specify a device specific interrupt, - or negative to specify a processor exception. - VTOR must been relocated to SRAM before. - If VTOR is not present address 0 must be mapped to SRAM. - \param [in] IRQn Interrupt number - \param [in] vector Address of interrupt handler function - */ -__STATIC_INLINE void __NVIC_SetVector(IRQn_Type IRQn, uint32_t vector) -{ -#if defined (__VTOR_PRESENT) && (__VTOR_PRESENT == 1U) - uint32_t *vectors = (uint32_t *)SCB->VTOR; -#else - uint32_t *vectors = (uint32_t *)0x0U; -#endif - vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET] = vector; -} - - -/** - \brief Get Interrupt Vector - \details Reads an interrupt vector from interrupt vector table. - The interrupt number can be positive to specify a device specific interrupt, - or negative to specify a processor exception. - \param [in] IRQn Interrupt number. - \return Address of interrupt handler function - */ -__STATIC_INLINE uint32_t __NVIC_GetVector(IRQn_Type IRQn) -{ -#if defined (__VTOR_PRESENT) && (__VTOR_PRESENT == 1U) - uint32_t *vectors = (uint32_t *)SCB->VTOR; -#else - uint32_t *vectors = (uint32_t *)0x0U; -#endif - return vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET]; - -} - - -/** - \brief System Reset - \details Initiates a system reset request to reset the MCU. - */ -__STATIC_INLINE void __NVIC_SystemReset(void) -{ - __DSB(); /* Ensure all outstanding memory accesses included - buffered write are completed before reset */ - SCB->AIRCR = ((0x5FAUL << SCB_AIRCR_VECTKEY_Pos) | - SCB_AIRCR_SYSRESETREQ_Msk); - __DSB(); /* Ensure completion of memory access */ - - for(;;) /* wait until reset */ - { - __NOP(); - } -} - -/*@} end of CMSIS_Core_NVICFunctions */ - -/* ########################## MPU functions #################################### */ - -#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) - -#include "mpu_armv7.h" - -#endif - -/* ########################## FPU functions #################################### */ -/** - \ingroup CMSIS_Core_FunctionInterface - \defgroup CMSIS_Core_FpuFunctions FPU Functions - \brief Function that provides FPU type. - @{ - */ - -/** - \brief get FPU type - \details returns the FPU type - \returns - - \b 0: No FPU - - \b 1: Single precision FPU - - \b 2: Double + Single precision FPU - */ -__STATIC_INLINE uint32_t SCB_GetFPUType(void) -{ - return 0U; /* No FPU */ -} - - -/*@} end of CMSIS_Core_FpuFunctions */ - - - -/* ################################## SysTick function ############################################ */ -/** - \ingroup CMSIS_Core_FunctionInterface - \defgroup CMSIS_Core_SysTickFunctions SysTick Functions - \brief Functions that configure the System. - @{ - */ - -#if defined (__Vendor_SysTickConfig) && (__Vendor_SysTickConfig == 0U) - -/** - \brief System Tick Configuration - \details Initializes the System Timer and its interrupt, and starts the System Tick Timer. - Counter is in free running mode to generate periodic interrupts. - \param [in] ticks Number of ticks between two interrupts. - \return 0 Function succeeded. - \return 1 Function failed. - \note When the variable __Vendor_SysTickConfig is set to 1, then the - function SysTick_Config is not included. In this case, the file device.h - must contain a vendor-specific implementation of this function. - */ -__STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks) -{ - if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk) - { - return (1UL); /* Reload value impossible */ - } - - SysTick->LOAD = (uint32_t)(ticks - 1UL); /* set reload register */ - NVIC_SetPriority (SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */ - SysTick->VAL = 0UL; /* Load the SysTick Counter Value */ - SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk | - SysTick_CTRL_TICKINT_Msk | - SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */ - return (0UL); /* Function successful */ -} - -#endif - -/*@} end of CMSIS_Core_SysTickFunctions */ - - - - -#ifdef __cplusplus -} -#endif - -#endif /* __CORE_CM0PLUS_H_DEPENDANT */ - -#endif /* __CMSIS_GENERIC */ diff --git a/bsp/essemi/es32f0271/libraries/CMSIS/Include/core_cm23.h b/bsp/essemi/es32f0271/libraries/CMSIS/Include/core_cm23.h deleted file mode 100644 index 7d1d478af2..0000000000 --- a/bsp/essemi/es32f0271/libraries/CMSIS/Include/core_cm23.h +++ /dev/null @@ -1,1899 +0,0 @@ -/**************************************************************************//** - * @file core_cm23.h - * @brief CMSIS Cortex-M23 Core Peripheral Access Layer Header File - * @version V5.0.4 - * @date 10. January 2018 - ******************************************************************************/ -/* - * Copyright (c) 2009-2018 Arm Limited. All rights reserved. - * - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed under the Apache License, Version 2.0 (the License); you may - * not use this file except in compliance with the License. - * You may obtain a copy of the License at - * - * www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an AS IS BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - */ - -#if defined ( __ICCARM__ ) - #pragma system_include /* treat file as system include file for MISRA check */ -#elif defined (__clang__) - #pragma clang system_header /* treat file as system include file */ -#endif - -#ifndef __CORE_CM23_H_GENERIC -#define __CORE_CM23_H_GENERIC - -#include - -#ifdef __cplusplus - extern "C" { -#endif - -/** - \page CMSIS_MISRA_Exceptions MISRA-C:2004 Compliance Exceptions - CMSIS violates the following MISRA-C:2004 rules: - - \li Required Rule 8.5, object/function definition in header file.
- Function definitions in header files are used to allow 'inlining'. - - \li Required Rule 18.4, declaration of union type or object of union type: '{...}'.
- Unions are used for effective representation of core registers. - - \li Advisory Rule 19.7, Function-like macro defined.
- Function-like macros are used to allow more efficient code. - */ - - -/******************************************************************************* - * CMSIS definitions - ******************************************************************************/ -/** - \ingroup Cortex_M23 - @{ - */ - -#include "cmsis_version.h" - -/* CMSIS definitions */ -#define __CM23_CMSIS_VERSION_MAIN (__CM_CMSIS_VERSION_MAIN) /*!< \deprecated [31:16] CMSIS HAL main version */ -#define __CM23_CMSIS_VERSION_SUB (__CM_CMSIS_VERSION_SUB) /*!< \deprecated [15:0] CMSIS HAL sub version */ -#define __CM23_CMSIS_VERSION ((__CM23_CMSIS_VERSION_MAIN << 16U) | \ - __CM23_CMSIS_VERSION_SUB ) /*!< \deprecated CMSIS HAL version number */ - -#define __CORTEX_M (23U) /*!< Cortex-M Core */ - -/** __FPU_USED indicates whether an FPU is used or not. - This core does not support an FPU at all -*/ -#define __FPU_USED 0U - -#if defined ( __CC_ARM ) - #if defined __TARGET_FPU_VFP - #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" - #endif - -#elif defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) - #if defined __ARM_PCS_VFP - #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" - #endif - -#elif defined ( __GNUC__ ) - #if defined (__VFP_FP__) && !defined(__SOFTFP__) - #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" - #endif - -#elif defined ( __ICCARM__ ) - #if defined __ARMVFP__ - #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" - #endif - -#elif defined ( __TI_ARM__ ) - #if defined __TI_VFP_SUPPORT__ - #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" - #endif - -#elif defined ( __TASKING__ ) - #if defined __FPU_VFP__ - #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" - #endif - -#elif defined ( __CSMC__ ) - #if ( __CSMC__ & 0x400U) - #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" - #endif - -#endif - -#include "cmsis_compiler.h" /* CMSIS compiler specific defines */ - - -#ifdef __cplusplus -} -#endif - -#endif /* __CORE_CM23_H_GENERIC */ - -#ifndef __CMSIS_GENERIC - -#ifndef __CORE_CM23_H_DEPENDANT -#define __CORE_CM23_H_DEPENDANT - -#ifdef __cplusplus - extern "C" { -#endif - -/* check device defines and use defaults */ -#if defined __CHECK_DEVICE_DEFINES - #ifndef __CM23_REV - #define __CM23_REV 0x0000U - #warning "__CM23_REV not defined in device header file; using default!" - #endif - - #ifndef __FPU_PRESENT - #define __FPU_PRESENT 0U - #warning "__FPU_PRESENT not defined in device header file; using default!" - #endif - - #ifndef __MPU_PRESENT - #define __MPU_PRESENT 0U - #warning "__MPU_PRESENT not defined in device header file; using default!" - #endif - - #ifndef __SAUREGION_PRESENT - #define __SAUREGION_PRESENT 0U - #warning "__SAUREGION_PRESENT not defined in device header file; using default!" - #endif - - #ifndef __VTOR_PRESENT - #define __VTOR_PRESENT 0U - #warning "__VTOR_PRESENT not defined in device header file; using default!" - #endif - - #ifndef __NVIC_PRIO_BITS - #define __NVIC_PRIO_BITS 2U - #warning "__NVIC_PRIO_BITS not defined in device header file; using default!" - #endif - - #ifndef __Vendor_SysTickConfig - #define __Vendor_SysTickConfig 0U - #warning "__Vendor_SysTickConfig not defined in device header file; using default!" - #endif - - #ifndef __ETM_PRESENT - #define __ETM_PRESENT 0U - #warning "__ETM_PRESENT not defined in device header file; using default!" - #endif - - #ifndef __MTB_PRESENT - #define __MTB_PRESENT 0U - #warning "__MTB_PRESENT not defined in device header file; using default!" - #endif - -#endif - -/* IO definitions (access restrictions to peripheral registers) */ -/** - \defgroup CMSIS_glob_defs CMSIS Global Defines - - IO Type Qualifiers are used - \li to specify the access to peripheral variables. - \li for automatic generation of peripheral register debug information. -*/ -#ifdef __cplusplus - #define __I volatile /*!< Defines 'read only' permissions */ -#else - #define __I volatile const /*!< Defines 'read only' permissions */ -#endif -#define __O volatile /*!< Defines 'write only' permissions */ -#define __IO volatile /*!< Defines 'read / write' permissions */ - -/* following defines should be used for structure members */ -#define __IM volatile const /*! Defines 'read only' structure member permissions */ -#define __OM volatile /*! Defines 'write only' structure member permissions */ -#define __IOM volatile /*! Defines 'read / write' structure member permissions */ - -/*@} end of group Cortex_M23 */ - - - -/******************************************************************************* - * Register Abstraction - Core Register contain: - - Core Register - - Core NVIC Register - - Core SCB Register - - Core SysTick Register - - Core Debug Register - - Core MPU Register - - Core SAU Register - ******************************************************************************/ -/** - \defgroup CMSIS_core_register Defines and Type Definitions - \brief Type definitions and defines for Cortex-M processor based devices. -*/ - -/** - \ingroup CMSIS_core_register - \defgroup CMSIS_CORE Status and Control Registers - \brief Core Register type definitions. - @{ - */ - -/** - \brief Union type to access the Application Program Status Register (APSR). - */ -typedef union -{ - struct - { - uint32_t _reserved0:28; /*!< bit: 0..27 Reserved */ - uint32_t V:1; /*!< bit: 28 Overflow condition code flag */ - uint32_t C:1; /*!< bit: 29 Carry condition code flag */ - uint32_t Z:1; /*!< bit: 30 Zero condition code flag */ - uint32_t N:1; /*!< bit: 31 Negative condition code flag */ - } b; /*!< Structure used for bit access */ - uint32_t w; /*!< Type used for word access */ -} APSR_Type; - -/* APSR Register Definitions */ -#define APSR_N_Pos 31U /*!< APSR: N Position */ -#define APSR_N_Msk (1UL << APSR_N_Pos) /*!< APSR: N Mask */ - -#define APSR_Z_Pos 30U /*!< APSR: Z Position */ -#define APSR_Z_Msk (1UL << APSR_Z_Pos) /*!< APSR: Z Mask */ - -#define APSR_C_Pos 29U /*!< APSR: C Position */ -#define APSR_C_Msk (1UL << APSR_C_Pos) /*!< APSR: C Mask */ - -#define APSR_V_Pos 28U /*!< APSR: V Position */ -#define APSR_V_Msk (1UL << APSR_V_Pos) /*!< APSR: V Mask */ - - -/** - \brief Union type to access the Interrupt Program Status Register (IPSR). - */ -typedef union -{ - struct - { - uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */ - uint32_t _reserved0:23; /*!< bit: 9..31 Reserved */ - } b; /*!< Structure used for bit access */ - uint32_t w; /*!< Type used for word access */ -} IPSR_Type; - -/* IPSR Register Definitions */ -#define IPSR_ISR_Pos 0U /*!< IPSR: ISR Position */ -#define IPSR_ISR_Msk (0x1FFUL /*<< IPSR_ISR_Pos*/) /*!< IPSR: ISR Mask */ - - -/** - \brief Union type to access the Special-Purpose Program Status Registers (xPSR). - */ -typedef union -{ - struct - { - uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */ - uint32_t _reserved0:15; /*!< bit: 9..23 Reserved */ - uint32_t T:1; /*!< bit: 24 Thumb bit (read 0) */ - uint32_t _reserved1:3; /*!< bit: 25..27 Reserved */ - uint32_t V:1; /*!< bit: 28 Overflow condition code flag */ - uint32_t C:1; /*!< bit: 29 Carry condition code flag */ - uint32_t Z:1; /*!< bit: 30 Zero condition code flag */ - uint32_t N:1; /*!< bit: 31 Negative condition code flag */ - } b; /*!< Structure used for bit access */ - uint32_t w; /*!< Type used for word access */ -} xPSR_Type; - -/* xPSR Register Definitions */ -#define xPSR_N_Pos 31U /*!< xPSR: N Position */ -#define xPSR_N_Msk (1UL << xPSR_N_Pos) /*!< xPSR: N Mask */ - -#define xPSR_Z_Pos 30U /*!< xPSR: Z Position */ -#define xPSR_Z_Msk (1UL << xPSR_Z_Pos) /*!< xPSR: Z Mask */ - -#define xPSR_C_Pos 29U /*!< xPSR: C Position */ -#define xPSR_C_Msk (1UL << xPSR_C_Pos) /*!< xPSR: C Mask */ - -#define xPSR_V_Pos 28U /*!< xPSR: V Position */ -#define xPSR_V_Msk (1UL << xPSR_V_Pos) /*!< xPSR: V Mask */ - -#define xPSR_T_Pos 24U /*!< xPSR: T Position */ -#define xPSR_T_Msk (1UL << xPSR_T_Pos) /*!< xPSR: T Mask */ - -#define xPSR_ISR_Pos 0U /*!< xPSR: ISR Position */ -#define xPSR_ISR_Msk (0x1FFUL /*<< xPSR_ISR_Pos*/) /*!< xPSR: ISR Mask */ - - -/** - \brief Union type to access the Control Registers (CONTROL). - */ -typedef union -{ - struct - { - uint32_t nPRIV:1; /*!< bit: 0 Execution privilege in Thread mode */ - uint32_t SPSEL:1; /*!< bit: 1 Stack-pointer select */ - uint32_t _reserved1:30; /*!< bit: 2..31 Reserved */ - } b; /*!< Structure used for bit access */ - uint32_t w; /*!< Type used for word access */ -} CONTROL_Type; - -/* CONTROL Register Definitions */ -#define CONTROL_SPSEL_Pos 1U /*!< CONTROL: SPSEL Position */ -#define CONTROL_SPSEL_Msk (1UL << CONTROL_SPSEL_Pos) /*!< CONTROL: SPSEL Mask */ - -#define CONTROL_nPRIV_Pos 0U /*!< CONTROL: nPRIV Position */ -#define CONTROL_nPRIV_Msk (1UL /*<< CONTROL_nPRIV_Pos*/) /*!< CONTROL: nPRIV Mask */ - -/*@} end of group CMSIS_CORE */ - - -/** - \ingroup CMSIS_core_register - \defgroup CMSIS_NVIC Nested Vectored Interrupt Controller (NVIC) - \brief Type definitions for the NVIC Registers - @{ - */ - -/** - \brief Structure type to access the Nested Vectored Interrupt Controller (NVIC). - */ -typedef struct -{ - __IOM uint32_t ISER[16U]; /*!< Offset: 0x000 (R/W) Interrupt Set Enable Register */ - uint32_t RESERVED0[16U]; - __IOM uint32_t ICER[16U]; /*!< Offset: 0x080 (R/W) Interrupt Clear Enable Register */ - uint32_t RSERVED1[16U]; - __IOM uint32_t ISPR[16U]; /*!< Offset: 0x100 (R/W) Interrupt Set Pending Register */ - uint32_t RESERVED2[16U]; - __IOM uint32_t ICPR[16U]; /*!< Offset: 0x180 (R/W) Interrupt Clear Pending Register */ - uint32_t RESERVED3[16U]; - __IOM uint32_t IABR[16U]; /*!< Offset: 0x200 (R/W) Interrupt Active bit Register */ - uint32_t RESERVED4[16U]; - __IOM uint32_t ITNS[16U]; /*!< Offset: 0x280 (R/W) Interrupt Non-Secure State Register */ - uint32_t RESERVED5[16U]; - __IOM uint32_t IPR[124U]; /*!< Offset: 0x300 (R/W) Interrupt Priority Register */ -} NVIC_Type; - -/*@} end of group CMSIS_NVIC */ - - -/** - \ingroup CMSIS_core_register - \defgroup CMSIS_SCB System Control Block (SCB) - \brief Type definitions for the System Control Block Registers - @{ - */ - -/** - \brief Structure type to access the System Control Block (SCB). - */ -typedef struct -{ - __IM uint32_t CPUID; /*!< Offset: 0x000 (R/ ) CPUID Base Register */ - __IOM uint32_t ICSR; /*!< Offset: 0x004 (R/W) Interrupt Control and State Register */ -#if defined (__VTOR_PRESENT) && (__VTOR_PRESENT == 1U) - __IOM uint32_t VTOR; /*!< Offset: 0x008 (R/W) Vector Table Offset Register */ -#else - uint32_t RESERVED0; -#endif - __IOM uint32_t AIRCR; /*!< Offset: 0x00C (R/W) Application Interrupt and Reset Control Register */ - __IOM uint32_t SCR; /*!< Offset: 0x010 (R/W) System Control Register */ - __IOM uint32_t CCR; /*!< Offset: 0x014 (R/W) Configuration Control Register */ - uint32_t RESERVED1; - __IOM uint32_t SHPR[2U]; /*!< Offset: 0x01C (R/W) System Handlers Priority Registers. [0] is RESERVED */ - __IOM uint32_t SHCSR; /*!< Offset: 0x024 (R/W) System Handler Control and State Register */ -} SCB_Type; - -/* SCB CPUID Register Definitions */ -#define SCB_CPUID_IMPLEMENTER_Pos 24U /*!< SCB CPUID: IMPLEMENTER Position */ -#define SCB_CPUID_IMPLEMENTER_Msk (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos) /*!< SCB CPUID: IMPLEMENTER Mask */ - -#define SCB_CPUID_VARIANT_Pos 20U /*!< SCB CPUID: VARIANT Position */ -#define SCB_CPUID_VARIANT_Msk (0xFUL << SCB_CPUID_VARIANT_Pos) /*!< SCB CPUID: VARIANT Mask */ - -#define SCB_CPUID_ARCHITECTURE_Pos 16U /*!< SCB CPUID: ARCHITECTURE Position */ -#define SCB_CPUID_ARCHITECTURE_Msk (0xFUL << SCB_CPUID_ARCHITECTURE_Pos) /*!< SCB CPUID: ARCHITECTURE Mask */ - -#define SCB_CPUID_PARTNO_Pos 4U /*!< SCB CPUID: PARTNO Position */ -#define SCB_CPUID_PARTNO_Msk (0xFFFUL << SCB_CPUID_PARTNO_Pos) /*!< SCB CPUID: PARTNO Mask */ - -#define SCB_CPUID_REVISION_Pos 0U /*!< SCB CPUID: REVISION Position */ -#define SCB_CPUID_REVISION_Msk (0xFUL /*<< SCB_CPUID_REVISION_Pos*/) /*!< SCB CPUID: REVISION Mask */ - -/* SCB Interrupt Control State Register Definitions */ -#define SCB_ICSR_PENDNMISET_Pos 31U /*!< SCB ICSR: PENDNMISET Position */ -#define SCB_ICSR_PENDNMISET_Msk (1UL << SCB_ICSR_PENDNMISET_Pos) /*!< SCB ICSR: PENDNMISET Mask */ - -#define SCB_ICSR_PENDNMICLR_Pos 30U /*!< SCB ICSR: PENDNMICLR Position */ -#define SCB_ICSR_PENDNMICLR_Msk (1UL << SCB_ICSR_PENDNMICLR_Pos) /*!< SCB ICSR: PENDNMICLR Mask */ - -#define SCB_ICSR_PENDSVSET_Pos 28U /*!< SCB ICSR: PENDSVSET Position */ -#define SCB_ICSR_PENDSVSET_Msk (1UL << SCB_ICSR_PENDSVSET_Pos) /*!< SCB ICSR: PENDSVSET Mask */ - -#define SCB_ICSR_PENDSVCLR_Pos 27U /*!< SCB ICSR: PENDSVCLR Position */ -#define SCB_ICSR_PENDSVCLR_Msk (1UL << SCB_ICSR_PENDSVCLR_Pos) /*!< SCB ICSR: PENDSVCLR Mask */ - -#define SCB_ICSR_PENDSTSET_Pos 26U /*!< SCB ICSR: PENDSTSET Position */ -#define SCB_ICSR_PENDSTSET_Msk (1UL << SCB_ICSR_PENDSTSET_Pos) /*!< SCB ICSR: PENDSTSET Mask */ - -#define SCB_ICSR_PENDSTCLR_Pos 25U /*!< SCB ICSR: PENDSTCLR Position */ -#define SCB_ICSR_PENDSTCLR_Msk (1UL << SCB_ICSR_PENDSTCLR_Pos) /*!< SCB ICSR: PENDSTCLR Mask */ - -#define SCB_ICSR_STTNS_Pos 24U /*!< SCB ICSR: STTNS Position (Security Extension) */ -#define SCB_ICSR_STTNS_Msk (1UL << SCB_ICSR_STTNS_Pos) /*!< SCB ICSR: STTNS Mask (Security Extension) */ - -#define SCB_ICSR_ISRPREEMPT_Pos 23U /*!< SCB ICSR: ISRPREEMPT Position */ -#define SCB_ICSR_ISRPREEMPT_Msk (1UL << SCB_ICSR_ISRPREEMPT_Pos) /*!< SCB ICSR: ISRPREEMPT Mask */ - -#define SCB_ICSR_ISRPENDING_Pos 22U /*!< SCB ICSR: ISRPENDING Position */ -#define SCB_ICSR_ISRPENDING_Msk (1UL << SCB_ICSR_ISRPENDING_Pos) /*!< SCB ICSR: ISRPENDING Mask */ - -#define SCB_ICSR_VECTPENDING_Pos 12U /*!< SCB ICSR: VECTPENDING Position */ -#define SCB_ICSR_VECTPENDING_Msk (0x1FFUL << SCB_ICSR_VECTPENDING_Pos) /*!< SCB ICSR: VECTPENDING Mask */ - -#define SCB_ICSR_RETTOBASE_Pos 11U /*!< SCB ICSR: RETTOBASE Position */ -#define SCB_ICSR_RETTOBASE_Msk (1UL << SCB_ICSR_RETTOBASE_Pos) /*!< SCB ICSR: RETTOBASE Mask */ - -#define SCB_ICSR_VECTACTIVE_Pos 0U /*!< SCB ICSR: VECTACTIVE Position */ -#define SCB_ICSR_VECTACTIVE_Msk (0x1FFUL /*<< SCB_ICSR_VECTACTIVE_Pos*/) /*!< SCB ICSR: VECTACTIVE Mask */ - -#if defined (__VTOR_PRESENT) && (__VTOR_PRESENT == 1U) -/* SCB Vector Table Offset Register Definitions */ -#define SCB_VTOR_TBLOFF_Pos 7U /*!< SCB VTOR: TBLOFF Position */ -#define SCB_VTOR_TBLOFF_Msk (0x1FFFFFFUL << SCB_VTOR_TBLOFF_Pos) /*!< SCB VTOR: TBLOFF Mask */ -#endif - -/* SCB Application Interrupt and Reset Control Register Definitions */ -#define SCB_AIRCR_VECTKEY_Pos 16U /*!< SCB AIRCR: VECTKEY Position */ -#define SCB_AIRCR_VECTKEY_Msk (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos) /*!< SCB AIRCR: VECTKEY Mask */ - -#define SCB_AIRCR_VECTKEYSTAT_Pos 16U /*!< SCB AIRCR: VECTKEYSTAT Position */ -#define SCB_AIRCR_VECTKEYSTAT_Msk (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos) /*!< SCB AIRCR: VECTKEYSTAT Mask */ - -#define SCB_AIRCR_ENDIANESS_Pos 15U /*!< SCB AIRCR: ENDIANESS Position */ -#define SCB_AIRCR_ENDIANESS_Msk (1UL << SCB_AIRCR_ENDIANESS_Pos) /*!< SCB AIRCR: ENDIANESS Mask */ - -#define SCB_AIRCR_PRIS_Pos 14U /*!< SCB AIRCR: PRIS Position */ -#define SCB_AIRCR_PRIS_Msk (1UL << SCB_AIRCR_PRIS_Pos) /*!< SCB AIRCR: PRIS Mask */ - -#define SCB_AIRCR_BFHFNMINS_Pos 13U /*!< SCB AIRCR: BFHFNMINS Position */ -#define SCB_AIRCR_BFHFNMINS_Msk (1UL << SCB_AIRCR_BFHFNMINS_Pos) /*!< SCB AIRCR: BFHFNMINS Mask */ - -#define SCB_AIRCR_SYSRESETREQS_Pos 3U /*!< SCB AIRCR: SYSRESETREQS Position */ -#define SCB_AIRCR_SYSRESETREQS_Msk (1UL << SCB_AIRCR_SYSRESETREQS_Pos) /*!< SCB AIRCR: SYSRESETREQS Mask */ - -#define SCB_AIRCR_SYSRESETREQ_Pos 2U /*!< SCB AIRCR: SYSRESETREQ Position */ -#define SCB_AIRCR_SYSRESETREQ_Msk (1UL << SCB_AIRCR_SYSRESETREQ_Pos) /*!< SCB AIRCR: SYSRESETREQ Mask */ - -#define SCB_AIRCR_VECTCLRACTIVE_Pos 1U /*!< SCB AIRCR: VECTCLRACTIVE Position */ -#define SCB_AIRCR_VECTCLRACTIVE_Msk (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos) /*!< SCB AIRCR: VECTCLRACTIVE Mask */ - -/* SCB System Control Register Definitions */ -#define SCB_SCR_SEVONPEND_Pos 4U /*!< SCB SCR: SEVONPEND Position */ -#define SCB_SCR_SEVONPEND_Msk (1UL << SCB_SCR_SEVONPEND_Pos) /*!< SCB SCR: SEVONPEND Mask */ - -#define SCB_SCR_SLEEPDEEPS_Pos 3U /*!< SCB SCR: SLEEPDEEPS Position */ -#define SCB_SCR_SLEEPDEEPS_Msk (1UL << SCB_SCR_SLEEPDEEPS_Pos) /*!< SCB SCR: SLEEPDEEPS Mask */ - -#define SCB_SCR_SLEEPDEEP_Pos 2U /*!< SCB SCR: SLEEPDEEP Position */ -#define SCB_SCR_SLEEPDEEP_Msk (1UL << SCB_SCR_SLEEPDEEP_Pos) /*!< SCB SCR: SLEEPDEEP Mask */ - -#define SCB_SCR_SLEEPONEXIT_Pos 1U /*!< SCB SCR: SLEEPONEXIT Position */ -#define SCB_SCR_SLEEPONEXIT_Msk (1UL << SCB_SCR_SLEEPONEXIT_Pos) /*!< SCB SCR: SLEEPONEXIT Mask */ - -/* SCB Configuration Control Register Definitions */ -#define SCB_CCR_BP_Pos 18U /*!< SCB CCR: BP Position */ -#define SCB_CCR_BP_Msk (1UL << SCB_CCR_BP_Pos) /*!< SCB CCR: BP Mask */ - -#define SCB_CCR_IC_Pos 17U /*!< SCB CCR: IC Position */ -#define SCB_CCR_IC_Msk (1UL << SCB_CCR_IC_Pos) /*!< SCB CCR: IC Mask */ - -#define SCB_CCR_DC_Pos 16U /*!< SCB CCR: DC Position */ -#define SCB_CCR_DC_Msk (1UL << SCB_CCR_DC_Pos) /*!< SCB CCR: DC Mask */ - -#define SCB_CCR_STKOFHFNMIGN_Pos 10U /*!< SCB CCR: STKOFHFNMIGN Position */ -#define SCB_CCR_STKOFHFNMIGN_Msk (1UL << SCB_CCR_STKOFHFNMIGN_Pos) /*!< SCB CCR: STKOFHFNMIGN Mask */ - -#define SCB_CCR_BFHFNMIGN_Pos 8U /*!< SCB CCR: BFHFNMIGN Position */ -#define SCB_CCR_BFHFNMIGN_Msk (1UL << SCB_CCR_BFHFNMIGN_Pos) /*!< SCB CCR: BFHFNMIGN Mask */ - -#define SCB_CCR_DIV_0_TRP_Pos 4U /*!< SCB CCR: DIV_0_TRP Position */ -#define SCB_CCR_DIV_0_TRP_Msk (1UL << SCB_CCR_DIV_0_TRP_Pos) /*!< SCB CCR: DIV_0_TRP Mask */ - -#define SCB_CCR_UNALIGN_TRP_Pos 3U /*!< SCB CCR: UNALIGN_TRP Position */ -#define SCB_CCR_UNALIGN_TRP_Msk (1UL << SCB_CCR_UNALIGN_TRP_Pos) /*!< SCB CCR: UNALIGN_TRP Mask */ - -#define SCB_CCR_USERSETMPEND_Pos 1U /*!< SCB CCR: USERSETMPEND Position */ -#define SCB_CCR_USERSETMPEND_Msk (1UL << SCB_CCR_USERSETMPEND_Pos) /*!< SCB CCR: USERSETMPEND Mask */ - -/* SCB System Handler Control and State Register Definitions */ -#define SCB_SHCSR_HARDFAULTPENDED_Pos 21U /*!< SCB SHCSR: HARDFAULTPENDED Position */ -#define SCB_SHCSR_HARDFAULTPENDED_Msk (1UL << SCB_SHCSR_HARDFAULTPENDED_Pos) /*!< SCB SHCSR: HARDFAULTPENDED Mask */ - -#define SCB_SHCSR_SVCALLPENDED_Pos 15U /*!< SCB SHCSR: SVCALLPENDED Position */ -#define SCB_SHCSR_SVCALLPENDED_Msk (1UL << SCB_SHCSR_SVCALLPENDED_Pos) /*!< SCB SHCSR: SVCALLPENDED Mask */ - -#define SCB_SHCSR_SYSTICKACT_Pos 11U /*!< SCB SHCSR: SYSTICKACT Position */ -#define SCB_SHCSR_SYSTICKACT_Msk (1UL << SCB_SHCSR_SYSTICKACT_Pos) /*!< SCB SHCSR: SYSTICKACT Mask */ - -#define SCB_SHCSR_PENDSVACT_Pos 10U /*!< SCB SHCSR: PENDSVACT Position */ -#define SCB_SHCSR_PENDSVACT_Msk (1UL << SCB_SHCSR_PENDSVACT_Pos) /*!< SCB SHCSR: PENDSVACT Mask */ - -#define SCB_SHCSR_SVCALLACT_Pos 7U /*!< SCB SHCSR: SVCALLACT Position */ -#define SCB_SHCSR_SVCALLACT_Msk (1UL << SCB_SHCSR_SVCALLACT_Pos) /*!< SCB SHCSR: SVCALLACT Mask */ - -#define SCB_SHCSR_NMIACT_Pos 5U /*!< SCB SHCSR: NMIACT Position */ -#define SCB_SHCSR_NMIACT_Msk (1UL << SCB_SHCSR_NMIACT_Pos) /*!< SCB SHCSR: NMIACT Mask */ - -#define SCB_SHCSR_HARDFAULTACT_Pos 2U /*!< SCB SHCSR: HARDFAULTACT Position */ -#define SCB_SHCSR_HARDFAULTACT_Msk (1UL << SCB_SHCSR_HARDFAULTACT_Pos) /*!< SCB SHCSR: HARDFAULTACT Mask */ - -/*@} end of group CMSIS_SCB */ - - -/** - \ingroup CMSIS_core_register - \defgroup CMSIS_SysTick System Tick Timer (SysTick) - \brief Type definitions for the System Timer Registers. - @{ - */ - -/** - \brief Structure type to access the System Timer (SysTick). - */ -typedef struct -{ - __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) SysTick Control and Status Register */ - __IOM uint32_t LOAD; /*!< Offset: 0x004 (R/W) SysTick Reload Value Register */ - __IOM uint32_t VAL; /*!< Offset: 0x008 (R/W) SysTick Current Value Register */ - __IM uint32_t CALIB; /*!< Offset: 0x00C (R/ ) SysTick Calibration Register */ -} SysTick_Type; - -/* SysTick Control / Status Register Definitions */ -#define SysTick_CTRL_COUNTFLAG_Pos 16U /*!< SysTick CTRL: COUNTFLAG Position */ -#define SysTick_CTRL_COUNTFLAG_Msk (1UL << SysTick_CTRL_COUNTFLAG_Pos) /*!< SysTick CTRL: COUNTFLAG Mask */ - -#define SysTick_CTRL_CLKSOURCE_Pos 2U /*!< SysTick CTRL: CLKSOURCE Position */ -#define SysTick_CTRL_CLKSOURCE_Msk (1UL << SysTick_CTRL_CLKSOURCE_Pos) /*!< SysTick CTRL: CLKSOURCE Mask */ - -#define SysTick_CTRL_TICKINT_Pos 1U /*!< SysTick CTRL: TICKINT Position */ -#define SysTick_CTRL_TICKINT_Msk (1UL << SysTick_CTRL_TICKINT_Pos) /*!< SysTick CTRL: TICKINT Mask */ - -#define SysTick_CTRL_ENABLE_Pos 0U /*!< SysTick CTRL: ENABLE Position */ -#define SysTick_CTRL_ENABLE_Msk (1UL /*<< SysTick_CTRL_ENABLE_Pos*/) /*!< SysTick CTRL: ENABLE Mask */ - -/* SysTick Reload Register Definitions */ -#define SysTick_LOAD_RELOAD_Pos 0U /*!< SysTick LOAD: RELOAD Position */ -#define SysTick_LOAD_RELOAD_Msk (0xFFFFFFUL /*<< SysTick_LOAD_RELOAD_Pos*/) /*!< SysTick LOAD: RELOAD Mask */ - -/* SysTick Current Register Definitions */ -#define SysTick_VAL_CURRENT_Pos 0U /*!< SysTick VAL: CURRENT Position */ -#define SysTick_VAL_CURRENT_Msk (0xFFFFFFUL /*<< SysTick_VAL_CURRENT_Pos*/) /*!< SysTick VAL: CURRENT Mask */ - -/* SysTick Calibration Register Definitions */ -#define SysTick_CALIB_NOREF_Pos 31U /*!< SysTick CALIB: NOREF Position */ -#define SysTick_CALIB_NOREF_Msk (1UL << SysTick_CALIB_NOREF_Pos) /*!< SysTick CALIB: NOREF Mask */ - -#define SysTick_CALIB_SKEW_Pos 30U /*!< SysTick CALIB: SKEW Position */ -#define SysTick_CALIB_SKEW_Msk (1UL << SysTick_CALIB_SKEW_Pos) /*!< SysTick CALIB: SKEW Mask */ - -#define SysTick_CALIB_TENMS_Pos 0U /*!< SysTick CALIB: TENMS Position */ -#define SysTick_CALIB_TENMS_Msk (0xFFFFFFUL /*<< SysTick_CALIB_TENMS_Pos*/) /*!< SysTick CALIB: TENMS Mask */ - -/*@} end of group CMSIS_SysTick */ - - -/** - \ingroup CMSIS_core_register - \defgroup CMSIS_DWT Data Watchpoint and Trace (DWT) - \brief Type definitions for the Data Watchpoint and Trace (DWT) - @{ - */ - -/** - \brief Structure type to access the Data Watchpoint and Trace Register (DWT). - */ -typedef struct -{ - __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) Control Register */ - uint32_t RESERVED0[6U]; - __IM uint32_t PCSR; /*!< Offset: 0x01C (R/ ) Program Counter Sample Register */ - __IOM uint32_t COMP0; /*!< Offset: 0x020 (R/W) Comparator Register 0 */ - uint32_t RESERVED1[1U]; - __IOM uint32_t FUNCTION0; /*!< Offset: 0x028 (R/W) Function Register 0 */ - uint32_t RESERVED2[1U]; - __IOM uint32_t COMP1; /*!< Offset: 0x030 (R/W) Comparator Register 1 */ - uint32_t RESERVED3[1U]; - __IOM uint32_t FUNCTION1; /*!< Offset: 0x038 (R/W) Function Register 1 */ - uint32_t RESERVED4[1U]; - __IOM uint32_t COMP2; /*!< Offset: 0x040 (R/W) Comparator Register 2 */ - uint32_t RESERVED5[1U]; - __IOM uint32_t FUNCTION2; /*!< Offset: 0x048 (R/W) Function Register 2 */ - uint32_t RESERVED6[1U]; - __IOM uint32_t COMP3; /*!< Offset: 0x050 (R/W) Comparator Register 3 */ - uint32_t RESERVED7[1U]; - __IOM uint32_t FUNCTION3; /*!< Offset: 0x058 (R/W) Function Register 3 */ - uint32_t RESERVED8[1U]; - __IOM uint32_t COMP4; /*!< Offset: 0x060 (R/W) Comparator Register 4 */ - uint32_t RESERVED9[1U]; - __IOM uint32_t FUNCTION4; /*!< Offset: 0x068 (R/W) Function Register 4 */ - uint32_t RESERVED10[1U]; - __IOM uint32_t COMP5; /*!< Offset: 0x070 (R/W) Comparator Register 5 */ - uint32_t RESERVED11[1U]; - __IOM uint32_t FUNCTION5; /*!< Offset: 0x078 (R/W) Function Register 5 */ - uint32_t RESERVED12[1U]; - __IOM uint32_t COMP6; /*!< Offset: 0x080 (R/W) Comparator Register 6 */ - uint32_t RESERVED13[1U]; - __IOM uint32_t FUNCTION6; /*!< Offset: 0x088 (R/W) Function Register 6 */ - uint32_t RESERVED14[1U]; - __IOM uint32_t COMP7; /*!< Offset: 0x090 (R/W) Comparator Register 7 */ - uint32_t RESERVED15[1U]; - __IOM uint32_t FUNCTION7; /*!< Offset: 0x098 (R/W) Function Register 7 */ - uint32_t RESERVED16[1U]; - __IOM uint32_t COMP8; /*!< Offset: 0x0A0 (R/W) Comparator Register 8 */ - uint32_t RESERVED17[1U]; - __IOM uint32_t FUNCTION8; /*!< Offset: 0x0A8 (R/W) Function Register 8 */ - uint32_t RESERVED18[1U]; - __IOM uint32_t COMP9; /*!< Offset: 0x0B0 (R/W) Comparator Register 9 */ - uint32_t RESERVED19[1U]; - __IOM uint32_t FUNCTION9; /*!< Offset: 0x0B8 (R/W) Function Register 9 */ - uint32_t RESERVED20[1U]; - __IOM uint32_t COMP10; /*!< Offset: 0x0C0 (R/W) Comparator Register 10 */ - uint32_t RESERVED21[1U]; - __IOM uint32_t FUNCTION10; /*!< Offset: 0x0C8 (R/W) Function Register 10 */ - uint32_t RESERVED22[1U]; - __IOM uint32_t COMP11; /*!< Offset: 0x0D0 (R/W) Comparator Register 11 */ - uint32_t RESERVED23[1U]; - __IOM uint32_t FUNCTION11; /*!< Offset: 0x0D8 (R/W) Function Register 11 */ - uint32_t RESERVED24[1U]; - __IOM uint32_t COMP12; /*!< Offset: 0x0E0 (R/W) Comparator Register 12 */ - uint32_t RESERVED25[1U]; - __IOM uint32_t FUNCTION12; /*!< Offset: 0x0E8 (R/W) Function Register 12 */ - uint32_t RESERVED26[1U]; - __IOM uint32_t COMP13; /*!< Offset: 0x0F0 (R/W) Comparator Register 13 */ - uint32_t RESERVED27[1U]; - __IOM uint32_t FUNCTION13; /*!< Offset: 0x0F8 (R/W) Function Register 13 */ - uint32_t RESERVED28[1U]; - __IOM uint32_t COMP14; /*!< Offset: 0x100 (R/W) Comparator Register 14 */ - uint32_t RESERVED29[1U]; - __IOM uint32_t FUNCTION14; /*!< Offset: 0x108 (R/W) Function Register 14 */ - uint32_t RESERVED30[1U]; - __IOM uint32_t COMP15; /*!< Offset: 0x110 (R/W) Comparator Register 15 */ - uint32_t RESERVED31[1U]; - __IOM uint32_t FUNCTION15; /*!< Offset: 0x118 (R/W) Function Register 15 */ -} DWT_Type; - -/* DWT Control Register Definitions */ -#define DWT_CTRL_NUMCOMP_Pos 28U /*!< DWT CTRL: NUMCOMP Position */ -#define DWT_CTRL_NUMCOMP_Msk (0xFUL << DWT_CTRL_NUMCOMP_Pos) /*!< DWT CTRL: NUMCOMP Mask */ - -#define DWT_CTRL_NOTRCPKT_Pos 27U /*!< DWT CTRL: NOTRCPKT Position */ -#define DWT_CTRL_NOTRCPKT_Msk (0x1UL << DWT_CTRL_NOTRCPKT_Pos) /*!< DWT CTRL: NOTRCPKT Mask */ - -#define DWT_CTRL_NOEXTTRIG_Pos 26U /*!< DWT CTRL: NOEXTTRIG Position */ -#define DWT_CTRL_NOEXTTRIG_Msk (0x1UL << DWT_CTRL_NOEXTTRIG_Pos) /*!< DWT CTRL: NOEXTTRIG Mask */ - -#define DWT_CTRL_NOCYCCNT_Pos 25U /*!< DWT CTRL: NOCYCCNT Position */ -#define DWT_CTRL_NOCYCCNT_Msk (0x1UL << DWT_CTRL_NOCYCCNT_Pos) /*!< DWT CTRL: NOCYCCNT Mask */ - -#define DWT_CTRL_NOPRFCNT_Pos 24U /*!< DWT CTRL: NOPRFCNT Position */ -#define DWT_CTRL_NOPRFCNT_Msk (0x1UL << DWT_CTRL_NOPRFCNT_Pos) /*!< DWT CTRL: NOPRFCNT Mask */ - -/* DWT Comparator Function Register Definitions */ -#define DWT_FUNCTION_ID_Pos 27U /*!< DWT FUNCTION: ID Position */ -#define DWT_FUNCTION_ID_Msk (0x1FUL << DWT_FUNCTION_ID_Pos) /*!< DWT FUNCTION: ID Mask */ - -#define DWT_FUNCTION_MATCHED_Pos 24U /*!< DWT FUNCTION: MATCHED Position */ -#define DWT_FUNCTION_MATCHED_Msk (0x1UL << DWT_FUNCTION_MATCHED_Pos) /*!< DWT FUNCTION: MATCHED Mask */ - -#define DWT_FUNCTION_DATAVSIZE_Pos 10U /*!< DWT FUNCTION: DATAVSIZE Position */ -#define DWT_FUNCTION_DATAVSIZE_Msk (0x3UL << DWT_FUNCTION_DATAVSIZE_Pos) /*!< DWT FUNCTION: DATAVSIZE Mask */ - -#define DWT_FUNCTION_ACTION_Pos 4U /*!< DWT FUNCTION: ACTION Position */ -#define DWT_FUNCTION_ACTION_Msk (0x3UL << DWT_FUNCTION_ACTION_Pos) /*!< DWT FUNCTION: ACTION Mask */ - -#define DWT_FUNCTION_MATCH_Pos 0U /*!< DWT FUNCTION: MATCH Position */ -#define DWT_FUNCTION_MATCH_Msk (0xFUL /*<< DWT_FUNCTION_MATCH_Pos*/) /*!< DWT FUNCTION: MATCH Mask */ - -/*@}*/ /* end of group CMSIS_DWT */ - - -/** - \ingroup CMSIS_core_register - \defgroup CMSIS_TPI Trace Port Interface (TPI) - \brief Type definitions for the Trace Port Interface (TPI) - @{ - */ - -/** - \brief Structure type to access the Trace Port Interface Register (TPI). - */ -typedef struct -{ - __IOM uint32_t SSPSR; /*!< Offset: 0x000 (R/ ) Supported Parallel Port Size Register */ - __IOM uint32_t CSPSR; /*!< Offset: 0x004 (R/W) Current Parallel Port Size Register */ - uint32_t RESERVED0[2U]; - __IOM uint32_t ACPR; /*!< Offset: 0x010 (R/W) Asynchronous Clock Prescaler Register */ - uint32_t RESERVED1[55U]; - __IOM uint32_t SPPR; /*!< Offset: 0x0F0 (R/W) Selected Pin Protocol Register */ - uint32_t RESERVED2[131U]; - __IM uint32_t FFSR; /*!< Offset: 0x300 (R/ ) Formatter and Flush Status Register */ - __IOM uint32_t FFCR; /*!< Offset: 0x304 (R/W) Formatter and Flush Control Register */ - __IM uint32_t FSCR; /*!< Offset: 0x308 (R/ ) Formatter Synchronization Counter Register */ - uint32_t RESERVED3[759U]; - __IM uint32_t TRIGGER; /*!< Offset: 0xEE8 (R/ ) TRIGGER */ - __IM uint32_t FIFO0; /*!< Offset: 0xEEC (R/ ) Integration ETM Data */ - __IM uint32_t ITATBCTR2; /*!< Offset: 0xEF0 (R/ ) ITATBCTR2 */ - uint32_t RESERVED4[1U]; - __IM uint32_t ITATBCTR0; /*!< Offset: 0xEF8 (R/ ) ITATBCTR0 */ - __IM uint32_t FIFO1; /*!< Offset: 0xEFC (R/ ) Integration ITM Data */ - __IOM uint32_t ITCTRL; /*!< Offset: 0xF00 (R/W) Integration Mode Control */ - uint32_t RESERVED5[39U]; - __IOM uint32_t CLAIMSET; /*!< Offset: 0xFA0 (R/W) Claim tag set */ - __IOM uint32_t CLAIMCLR; /*!< Offset: 0xFA4 (R/W) Claim tag clear */ - uint32_t RESERVED7[8U]; - __IM uint32_t DEVID; /*!< Offset: 0xFC8 (R/ ) TPIU_DEVID */ - __IM uint32_t DEVTYPE; /*!< Offset: 0xFCC (R/ ) TPIU_DEVTYPE */ -} TPI_Type; - -/* TPI Asynchronous Clock Prescaler Register Definitions */ -#define TPI_ACPR_PRESCALER_Pos 0U /*!< @Deprecated TPI ACPR: PRESCALER Position */ -#define TPI_ACPR_PRESCALER_Msk (0x1FFFUL /*<< TPI_ACPR_PRESCALER_Pos*/) /*!< @Deprecated TPI ACPR: PRESCALER Mask */ - -#define TPI_ACPR_SWOSCALER_Pos 0U /*!< TPI ACPR: SWOSCALER Position */ -#define TPI_ACPR_SWOSCALER_Msk (0xFFFFUL /*<< TPI_ACPR_SWOSCALER_Pos*/) /*!< TPI ACPR: SWOSCALER Mask */ - -/* TPI Selected Pin Protocol Register Definitions */ -#define TPI_SPPR_TXMODE_Pos 0U /*!< TPI SPPR: TXMODE Position */ -#define TPI_SPPR_TXMODE_Msk (0x3UL /*<< TPI_SPPR_TXMODE_Pos*/) /*!< TPI SPPR: TXMODE Mask */ - -/* TPI Formatter and Flush Status Register Definitions */ -#define TPI_FFSR_FtNonStop_Pos 3U /*!< TPI FFSR: FtNonStop Position */ -#define TPI_FFSR_FtNonStop_Msk (0x1UL << TPI_FFSR_FtNonStop_Pos) /*!< TPI FFSR: FtNonStop Mask */ - -#define TPI_FFSR_TCPresent_Pos 2U /*!< TPI FFSR: TCPresent Position */ -#define TPI_FFSR_TCPresent_Msk (0x1UL << TPI_FFSR_TCPresent_Pos) /*!< TPI FFSR: TCPresent Mask */ - -#define TPI_FFSR_FtStopped_Pos 1U /*!< TPI FFSR: FtStopped Position */ -#define TPI_FFSR_FtStopped_Msk (0x1UL << TPI_FFSR_FtStopped_Pos) /*!< TPI FFSR: FtStopped Mask */ - -#define TPI_FFSR_FlInProg_Pos 0U /*!< TPI FFSR: FlInProg Position */ -#define TPI_FFSR_FlInProg_Msk (0x1UL /*<< TPI_FFSR_FlInProg_Pos*/) /*!< TPI FFSR: FlInProg Mask */ - -/* TPI Formatter and Flush Control Register Definitions */ -#define TPI_FFCR_TrigIn_Pos 8U /*!< TPI FFCR: TrigIn Position */ -#define TPI_FFCR_TrigIn_Msk (0x1UL << TPI_FFCR_TrigIn_Pos) /*!< TPI FFCR: TrigIn Mask */ - -#define TPI_FFCR_EnFCont_Pos 1U /*!< TPI FFCR: EnFCont Position */ -#define TPI_FFCR_EnFCont_Msk (0x1UL << TPI_FFCR_EnFCont_Pos) /*!< TPI FFCR: EnFCont Mask */ - -/* TPI TRIGGER Register Definitions */ -#define TPI_TRIGGER_TRIGGER_Pos 0U /*!< TPI TRIGGER: TRIGGER Position */ -#define TPI_TRIGGER_TRIGGER_Msk (0x1UL /*<< TPI_TRIGGER_TRIGGER_Pos*/) /*!< TPI TRIGGER: TRIGGER Mask */ - -/* TPI Integration ETM Data Register Definitions (FIFO0) */ -#define TPI_FIFO0_ITM_ATVALID_Pos 29U /*!< TPI FIFO0: ITM_ATVALID Position */ -#define TPI_FIFO0_ITM_ATVALID_Msk (0x3UL << TPI_FIFO0_ITM_ATVALID_Pos) /*!< TPI FIFO0: ITM_ATVALID Mask */ - -#define TPI_FIFO0_ITM_bytecount_Pos 27U /*!< TPI FIFO0: ITM_bytecount Position */ -#define TPI_FIFO0_ITM_bytecount_Msk (0x3UL << TPI_FIFO0_ITM_bytecount_Pos) /*!< TPI FIFO0: ITM_bytecount Mask */ - -#define TPI_FIFO0_ETM_ATVALID_Pos 26U /*!< TPI FIFO0: ETM_ATVALID Position */ -#define TPI_FIFO0_ETM_ATVALID_Msk (0x3UL << TPI_FIFO0_ETM_ATVALID_Pos) /*!< TPI FIFO0: ETM_ATVALID Mask */ - -#define TPI_FIFO0_ETM_bytecount_Pos 24U /*!< TPI FIFO0: ETM_bytecount Position */ -#define TPI_FIFO0_ETM_bytecount_Msk (0x3UL << TPI_FIFO0_ETM_bytecount_Pos) /*!< TPI FIFO0: ETM_bytecount Mask */ - -#define TPI_FIFO0_ETM2_Pos 16U /*!< TPI FIFO0: ETM2 Position */ -#define TPI_FIFO0_ETM2_Msk (0xFFUL << TPI_FIFO0_ETM2_Pos) /*!< TPI FIFO0: ETM2 Mask */ - -#define TPI_FIFO0_ETM1_Pos 8U /*!< TPI FIFO0: ETM1 Position */ -#define TPI_FIFO0_ETM1_Msk (0xFFUL << TPI_FIFO0_ETM1_Pos) /*!< TPI FIFO0: ETM1 Mask */ - -#define TPI_FIFO0_ETM0_Pos 0U /*!< TPI FIFO0: ETM0 Position */ -#define TPI_FIFO0_ETM0_Msk (0xFFUL /*<< TPI_FIFO0_ETM0_Pos*/) /*!< TPI FIFO0: ETM0 Mask */ - -/* TPI ITATBCTR2 Register Definitions */ -#define TPI_ITATBCTR2_ATREADY_Pos 0U /*!< TPI ITATBCTR2: ATREADY Position */ -#define TPI_ITATBCTR2_ATREADY_Msk (0x1UL /*<< TPI_ITATBCTR2_ATREADY_Pos*/) /*!< TPI ITATBCTR2: ATREADY Mask */ - -/* TPI Integration ITM Data Register Definitions (FIFO1) */ -#define TPI_FIFO1_ITM_ATVALID_Pos 29U /*!< TPI FIFO1: ITM_ATVALID Position */ -#define TPI_FIFO1_ITM_ATVALID_Msk (0x3UL << TPI_FIFO1_ITM_ATVALID_Pos) /*!< TPI FIFO1: ITM_ATVALID Mask */ - -#define TPI_FIFO1_ITM_bytecount_Pos 27U /*!< TPI FIFO1: ITM_bytecount Position */ -#define TPI_FIFO1_ITM_bytecount_Msk (0x3UL << TPI_FIFO1_ITM_bytecount_Pos) /*!< TPI FIFO1: ITM_bytecount Mask */ - -#define TPI_FIFO1_ETM_ATVALID_Pos 26U /*!< TPI FIFO1: ETM_ATVALID Position */ -#define TPI_FIFO1_ETM_ATVALID_Msk (0x3UL << TPI_FIFO1_ETM_ATVALID_Pos) /*!< TPI FIFO1: ETM_ATVALID Mask */ - -#define TPI_FIFO1_ETM_bytecount_Pos 24U /*!< TPI FIFO1: ETM_bytecount Position */ -#define TPI_FIFO1_ETM_bytecount_Msk (0x3UL << TPI_FIFO1_ETM_bytecount_Pos) /*!< TPI FIFO1: ETM_bytecount Mask */ - -#define TPI_FIFO1_ITM2_Pos 16U /*!< TPI FIFO1: ITM2 Position */ -#define TPI_FIFO1_ITM2_Msk (0xFFUL << TPI_FIFO1_ITM2_Pos) /*!< TPI FIFO1: ITM2 Mask */ - -#define TPI_FIFO1_ITM1_Pos 8U /*!< TPI FIFO1: ITM1 Position */ -#define TPI_FIFO1_ITM1_Msk (0xFFUL << TPI_FIFO1_ITM1_Pos) /*!< TPI FIFO1: ITM1 Mask */ - -#define TPI_FIFO1_ITM0_Pos 0U /*!< TPI FIFO1: ITM0 Position */ -#define TPI_FIFO1_ITM0_Msk (0xFFUL /*<< TPI_FIFO1_ITM0_Pos*/) /*!< TPI FIFO1: ITM0 Mask */ - -/* TPI ITATBCTR0 Register Definitions */ -#define TPI_ITATBCTR0_ATREADY_Pos 0U /*!< TPI ITATBCTR0: ATREADY Position */ -#define TPI_ITATBCTR0_ATREADY_Msk (0x1UL /*<< TPI_ITATBCTR0_ATREADY_Pos*/) /*!< TPI ITATBCTR0: ATREADY Mask */ - -/* TPI Integration Mode Control Register Definitions */ -#define TPI_ITCTRL_Mode_Pos 0U /*!< TPI ITCTRL: Mode Position */ -#define TPI_ITCTRL_Mode_Msk (0x1UL /*<< TPI_ITCTRL_Mode_Pos*/) /*!< TPI ITCTRL: Mode Mask */ - -/* TPI DEVID Register Definitions */ -#define TPI_DEVID_NRZVALID_Pos 11U /*!< TPI DEVID: NRZVALID Position */ -#define TPI_DEVID_NRZVALID_Msk (0x1UL << TPI_DEVID_NRZVALID_Pos) /*!< TPI DEVID: NRZVALID Mask */ - -#define TPI_DEVID_MANCVALID_Pos 10U /*!< TPI DEVID: MANCVALID Position */ -#define TPI_DEVID_MANCVALID_Msk (0x1UL << TPI_DEVID_MANCVALID_Pos) /*!< TPI DEVID: MANCVALID Mask */ - -#define TPI_DEVID_PTINVALID_Pos 9U /*!< TPI DEVID: PTINVALID Position */ -#define TPI_DEVID_PTINVALID_Msk (0x1UL << TPI_DEVID_PTINVALID_Pos) /*!< TPI DEVID: PTINVALID Mask */ - -#define TPI_DEVID_MinBufSz_Pos 6U /*!< TPI DEVID: MinBufSz Position */ -#define TPI_DEVID_MinBufSz_Msk (0x7UL << TPI_DEVID_MinBufSz_Pos) /*!< TPI DEVID: MinBufSz Mask */ - -#define TPI_DEVID_AsynClkIn_Pos 5U /*!< TPI DEVID: AsynClkIn Position */ -#define TPI_DEVID_AsynClkIn_Msk (0x1UL << TPI_DEVID_AsynClkIn_Pos) /*!< TPI DEVID: AsynClkIn Mask */ - -#define TPI_DEVID_NrTraceInput_Pos 0U /*!< TPI DEVID: NrTraceInput Position */ -#define TPI_DEVID_NrTraceInput_Msk (0x1FUL /*<< TPI_DEVID_NrTraceInput_Pos*/) /*!< TPI DEVID: NrTraceInput Mask */ - -/* TPI DEVTYPE Register Definitions */ -#define TPI_DEVTYPE_MajorType_Pos 4U /*!< TPI DEVTYPE: MajorType Position */ -#define TPI_DEVTYPE_MajorType_Msk (0xFUL << TPI_DEVTYPE_MajorType_Pos) /*!< TPI DEVTYPE: MajorType Mask */ - -#define TPI_DEVTYPE_SubType_Pos 0U /*!< TPI DEVTYPE: SubType Position */ -#define TPI_DEVTYPE_SubType_Msk (0xFUL /*<< TPI_DEVTYPE_SubType_Pos*/) /*!< TPI DEVTYPE: SubType Mask */ - -/*@}*/ /* end of group CMSIS_TPI */ - - -#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) -/** - \ingroup CMSIS_core_register - \defgroup CMSIS_MPU Memory Protection Unit (MPU) - \brief Type definitions for the Memory Protection Unit (MPU) - @{ - */ - -/** - \brief Structure type to access the Memory Protection Unit (MPU). - */ -typedef struct -{ - __IM uint32_t TYPE; /*!< Offset: 0x000 (R/ ) MPU Type Register */ - __IOM uint32_t CTRL; /*!< Offset: 0x004 (R/W) MPU Control Register */ - __IOM uint32_t RNR; /*!< Offset: 0x008 (R/W) MPU Region Number Register */ - __IOM uint32_t RBAR; /*!< Offset: 0x00C (R/W) MPU Region Base Address Register */ - __IOM uint32_t RLAR; /*!< Offset: 0x010 (R/W) MPU Region Limit Address Register */ - uint32_t RESERVED0[7U]; - union { - __IOM uint32_t MAIR[2]; - struct { - __IOM uint32_t MAIR0; /*!< Offset: 0x030 (R/W) MPU Memory Attribute Indirection Register 0 */ - __IOM uint32_t MAIR1; /*!< Offset: 0x034 (R/W) MPU Memory Attribute Indirection Register 1 */ - }; - }; -} MPU_Type; - -#define MPU_TYPE_RALIASES 1U - -/* MPU Type Register Definitions */ -#define MPU_TYPE_IREGION_Pos 16U /*!< MPU TYPE: IREGION Position */ -#define MPU_TYPE_IREGION_Msk (0xFFUL << MPU_TYPE_IREGION_Pos) /*!< MPU TYPE: IREGION Mask */ - -#define MPU_TYPE_DREGION_Pos 8U /*!< MPU TYPE: DREGION Position */ -#define MPU_TYPE_DREGION_Msk (0xFFUL << MPU_TYPE_DREGION_Pos) /*!< MPU TYPE: DREGION Mask */ - -#define MPU_TYPE_SEPARATE_Pos 0U /*!< MPU TYPE: SEPARATE Position */ -#define MPU_TYPE_SEPARATE_Msk (1UL /*<< MPU_TYPE_SEPARATE_Pos*/) /*!< MPU TYPE: SEPARATE Mask */ - -/* MPU Control Register Definitions */ -#define MPU_CTRL_PRIVDEFENA_Pos 2U /*!< MPU CTRL: PRIVDEFENA Position */ -#define MPU_CTRL_PRIVDEFENA_Msk (1UL << MPU_CTRL_PRIVDEFENA_Pos) /*!< MPU CTRL: PRIVDEFENA Mask */ - -#define MPU_CTRL_HFNMIENA_Pos 1U /*!< MPU CTRL: HFNMIENA Position */ -#define MPU_CTRL_HFNMIENA_Msk (1UL << MPU_CTRL_HFNMIENA_Pos) /*!< MPU CTRL: HFNMIENA Mask */ - -#define MPU_CTRL_ENABLE_Pos 0U /*!< MPU CTRL: ENABLE Position */ -#define MPU_CTRL_ENABLE_Msk (1UL /*<< MPU_CTRL_ENABLE_Pos*/) /*!< MPU CTRL: ENABLE Mask */ - -/* MPU Region Number Register Definitions */ -#define MPU_RNR_REGION_Pos 0U /*!< MPU RNR: REGION Position */ -#define MPU_RNR_REGION_Msk (0xFFUL /*<< MPU_RNR_REGION_Pos*/) /*!< MPU RNR: REGION Mask */ - -/* MPU Region Base Address Register Definitions */ -#define MPU_RBAR_BASE_Pos 5U /*!< MPU RBAR: BASE Position */ -#define MPU_RBAR_BASE_Msk (0x7FFFFFFUL << MPU_RBAR_BASE_Pos) /*!< MPU RBAR: BASE Mask */ - -#define MPU_RBAR_SH_Pos 3U /*!< MPU RBAR: SH Position */ -#define MPU_RBAR_SH_Msk (0x3UL << MPU_RBAR_SH_Pos) /*!< MPU RBAR: SH Mask */ - -#define MPU_RBAR_AP_Pos 1U /*!< MPU RBAR: AP Position */ -#define MPU_RBAR_AP_Msk (0x3UL << MPU_RBAR_AP_Pos) /*!< MPU RBAR: AP Mask */ - -#define MPU_RBAR_XN_Pos 0U /*!< MPU RBAR: XN Position */ -#define MPU_RBAR_XN_Msk (01UL /*<< MPU_RBAR_XN_Pos*/) /*!< MPU RBAR: XN Mask */ - -/* MPU Region Limit Address Register Definitions */ -#define MPU_RLAR_LIMIT_Pos 5U /*!< MPU RLAR: LIMIT Position */ -#define MPU_RLAR_LIMIT_Msk (0x7FFFFFFUL << MPU_RLAR_LIMIT_Pos) /*!< MPU RLAR: LIMIT Mask */ - -#define MPU_RLAR_AttrIndx_Pos 1U /*!< MPU RLAR: AttrIndx Position */ -#define MPU_RLAR_AttrIndx_Msk (0x7UL << MPU_RLAR_AttrIndx_Pos) /*!< MPU RLAR: AttrIndx Mask */ - -#define MPU_RLAR_EN_Pos 0U /*!< MPU RLAR: EN Position */ -#define MPU_RLAR_EN_Msk (1UL /*<< MPU_RLAR_EN_Pos*/) /*!< MPU RLAR: EN Mask */ - -/* MPU Memory Attribute Indirection Register 0 Definitions */ -#define MPU_MAIR0_Attr3_Pos 24U /*!< MPU MAIR0: Attr3 Position */ -#define MPU_MAIR0_Attr3_Msk (0xFFUL << MPU_MAIR0_Attr3_Pos) /*!< MPU MAIR0: Attr3 Mask */ - -#define MPU_MAIR0_Attr2_Pos 16U /*!< MPU MAIR0: Attr2 Position */ -#define MPU_MAIR0_Attr2_Msk (0xFFUL << MPU_MAIR0_Attr2_Pos) /*!< MPU MAIR0: Attr2 Mask */ - -#define MPU_MAIR0_Attr1_Pos 8U /*!< MPU MAIR0: Attr1 Position */ -#define MPU_MAIR0_Attr1_Msk (0xFFUL << MPU_MAIR0_Attr1_Pos) /*!< MPU MAIR0: Attr1 Mask */ - -#define MPU_MAIR0_Attr0_Pos 0U /*!< MPU MAIR0: Attr0 Position */ -#define MPU_MAIR0_Attr0_Msk (0xFFUL /*<< MPU_MAIR0_Attr0_Pos*/) /*!< MPU MAIR0: Attr0 Mask */ - -/* MPU Memory Attribute Indirection Register 1 Definitions */ -#define MPU_MAIR1_Attr7_Pos 24U /*!< MPU MAIR1: Attr7 Position */ -#define MPU_MAIR1_Attr7_Msk (0xFFUL << MPU_MAIR1_Attr7_Pos) /*!< MPU MAIR1: Attr7 Mask */ - -#define MPU_MAIR1_Attr6_Pos 16U /*!< MPU MAIR1: Attr6 Position */ -#define MPU_MAIR1_Attr6_Msk (0xFFUL << MPU_MAIR1_Attr6_Pos) /*!< MPU MAIR1: Attr6 Mask */ - -#define MPU_MAIR1_Attr5_Pos 8U /*!< MPU MAIR1: Attr5 Position */ -#define MPU_MAIR1_Attr5_Msk (0xFFUL << MPU_MAIR1_Attr5_Pos) /*!< MPU MAIR1: Attr5 Mask */ - -#define MPU_MAIR1_Attr4_Pos 0U /*!< MPU MAIR1: Attr4 Position */ -#define MPU_MAIR1_Attr4_Msk (0xFFUL /*<< MPU_MAIR1_Attr4_Pos*/) /*!< MPU MAIR1: Attr4 Mask */ - -/*@} end of group CMSIS_MPU */ -#endif - - -#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) -/** - \ingroup CMSIS_core_register - \defgroup CMSIS_SAU Security Attribution Unit (SAU) - \brief Type definitions for the Security Attribution Unit (SAU) - @{ - */ - -/** - \brief Structure type to access the Security Attribution Unit (SAU). - */ -typedef struct -{ - __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) SAU Control Register */ - __IM uint32_t TYPE; /*!< Offset: 0x004 (R/ ) SAU Type Register */ -#if defined (__SAUREGION_PRESENT) && (__SAUREGION_PRESENT == 1U) - __IOM uint32_t RNR; /*!< Offset: 0x008 (R/W) SAU Region Number Register */ - __IOM uint32_t RBAR; /*!< Offset: 0x00C (R/W) SAU Region Base Address Register */ - __IOM uint32_t RLAR; /*!< Offset: 0x010 (R/W) SAU Region Limit Address Register */ -#endif -} SAU_Type; - -/* SAU Control Register Definitions */ -#define SAU_CTRL_ALLNS_Pos 1U /*!< SAU CTRL: ALLNS Position */ -#define SAU_CTRL_ALLNS_Msk (1UL << SAU_CTRL_ALLNS_Pos) /*!< SAU CTRL: ALLNS Mask */ - -#define SAU_CTRL_ENABLE_Pos 0U /*!< SAU CTRL: ENABLE Position */ -#define SAU_CTRL_ENABLE_Msk (1UL /*<< SAU_CTRL_ENABLE_Pos*/) /*!< SAU CTRL: ENABLE Mask */ - -/* SAU Type Register Definitions */ -#define SAU_TYPE_SREGION_Pos 0U /*!< SAU TYPE: SREGION Position */ -#define SAU_TYPE_SREGION_Msk (0xFFUL /*<< SAU_TYPE_SREGION_Pos*/) /*!< SAU TYPE: SREGION Mask */ - -#if defined (__SAUREGION_PRESENT) && (__SAUREGION_PRESENT == 1U) -/* SAU Region Number Register Definitions */ -#define SAU_RNR_REGION_Pos 0U /*!< SAU RNR: REGION Position */ -#define SAU_RNR_REGION_Msk (0xFFUL /*<< SAU_RNR_REGION_Pos*/) /*!< SAU RNR: REGION Mask */ - -/* SAU Region Base Address Register Definitions */ -#define SAU_RBAR_BADDR_Pos 5U /*!< SAU RBAR: BADDR Position */ -#define SAU_RBAR_BADDR_Msk (0x7FFFFFFUL << SAU_RBAR_BADDR_Pos) /*!< SAU RBAR: BADDR Mask */ - -/* SAU Region Limit Address Register Definitions */ -#define SAU_RLAR_LADDR_Pos 5U /*!< SAU RLAR: LADDR Position */ -#define SAU_RLAR_LADDR_Msk (0x7FFFFFFUL << SAU_RLAR_LADDR_Pos) /*!< SAU RLAR: LADDR Mask */ - -#define SAU_RLAR_NSC_Pos 1U /*!< SAU RLAR: NSC Position */ -#define SAU_RLAR_NSC_Msk (1UL << SAU_RLAR_NSC_Pos) /*!< SAU RLAR: NSC Mask */ - -#define SAU_RLAR_ENABLE_Pos 0U /*!< SAU RLAR: ENABLE Position */ -#define SAU_RLAR_ENABLE_Msk (1UL /*<< SAU_RLAR_ENABLE_Pos*/) /*!< SAU RLAR: ENABLE Mask */ - -#endif /* defined (__SAUREGION_PRESENT) && (__SAUREGION_PRESENT == 1U) */ - -/*@} end of group CMSIS_SAU */ -#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */ - - -/** - \ingroup CMSIS_core_register - \defgroup CMSIS_CoreDebug Core Debug Registers (CoreDebug) - \brief Type definitions for the Core Debug Registers - @{ - */ - -/** - \brief Structure type to access the Core Debug Register (CoreDebug). - */ -typedef struct -{ - __IOM uint32_t DHCSR; /*!< Offset: 0x000 (R/W) Debug Halting Control and Status Register */ - __OM uint32_t DCRSR; /*!< Offset: 0x004 ( /W) Debug Core Register Selector Register */ - __IOM uint32_t DCRDR; /*!< Offset: 0x008 (R/W) Debug Core Register Data Register */ - __IOM uint32_t DEMCR; /*!< Offset: 0x00C (R/W) Debug Exception and Monitor Control Register */ - uint32_t RESERVED4[1U]; - __IOM uint32_t DAUTHCTRL; /*!< Offset: 0x014 (R/W) Debug Authentication Control Register */ - __IOM uint32_t DSCSR; /*!< Offset: 0x018 (R/W) Debug Security Control and Status Register */ -} CoreDebug_Type; - -/* Debug Halting Control and Status Register Definitions */ -#define CoreDebug_DHCSR_DBGKEY_Pos 16U /*!< CoreDebug DHCSR: DBGKEY Position */ -#define CoreDebug_DHCSR_DBGKEY_Msk (0xFFFFUL << CoreDebug_DHCSR_DBGKEY_Pos) /*!< CoreDebug DHCSR: DBGKEY Mask */ - -#define CoreDebug_DHCSR_S_RESTART_ST_Pos 26U /*!< CoreDebug DHCSR: S_RESTART_ST Position */ -#define CoreDebug_DHCSR_S_RESTART_ST_Msk (1UL << CoreDebug_DHCSR_S_RESTART_ST_Pos) /*!< CoreDebug DHCSR: S_RESTART_ST Mask */ - -#define CoreDebug_DHCSR_S_RESET_ST_Pos 25U /*!< CoreDebug DHCSR: S_RESET_ST Position */ -#define CoreDebug_DHCSR_S_RESET_ST_Msk (1UL << CoreDebug_DHCSR_S_RESET_ST_Pos) /*!< CoreDebug DHCSR: S_RESET_ST Mask */ - -#define CoreDebug_DHCSR_S_RETIRE_ST_Pos 24U /*!< CoreDebug DHCSR: S_RETIRE_ST Position */ -#define CoreDebug_DHCSR_S_RETIRE_ST_Msk (1UL << CoreDebug_DHCSR_S_RETIRE_ST_Pos) /*!< CoreDebug DHCSR: S_RETIRE_ST Mask */ - -#define CoreDebug_DHCSR_S_LOCKUP_Pos 19U /*!< CoreDebug DHCSR: S_LOCKUP Position */ -#define CoreDebug_DHCSR_S_LOCKUP_Msk (1UL << CoreDebug_DHCSR_S_LOCKUP_Pos) /*!< CoreDebug DHCSR: S_LOCKUP Mask */ - -#define CoreDebug_DHCSR_S_SLEEP_Pos 18U /*!< CoreDebug DHCSR: S_SLEEP Position */ -#define CoreDebug_DHCSR_S_SLEEP_Msk (1UL << CoreDebug_DHCSR_S_SLEEP_Pos) /*!< CoreDebug DHCSR: S_SLEEP Mask */ - -#define CoreDebug_DHCSR_S_HALT_Pos 17U /*!< CoreDebug DHCSR: S_HALT Position */ -#define CoreDebug_DHCSR_S_HALT_Msk (1UL << CoreDebug_DHCSR_S_HALT_Pos) /*!< CoreDebug DHCSR: S_HALT Mask */ - -#define CoreDebug_DHCSR_S_REGRDY_Pos 16U /*!< CoreDebug DHCSR: S_REGRDY Position */ -#define CoreDebug_DHCSR_S_REGRDY_Msk (1UL << CoreDebug_DHCSR_S_REGRDY_Pos) /*!< CoreDebug DHCSR: S_REGRDY Mask */ - -#define CoreDebug_DHCSR_C_MASKINTS_Pos 3U /*!< CoreDebug DHCSR: C_MASKINTS Position */ -#define CoreDebug_DHCSR_C_MASKINTS_Msk (1UL << CoreDebug_DHCSR_C_MASKINTS_Pos) /*!< CoreDebug DHCSR: C_MASKINTS Mask */ - -#define CoreDebug_DHCSR_C_STEP_Pos 2U /*!< CoreDebug DHCSR: C_STEP Position */ -#define CoreDebug_DHCSR_C_STEP_Msk (1UL << CoreDebug_DHCSR_C_STEP_Pos) /*!< CoreDebug DHCSR: C_STEP Mask */ - -#define CoreDebug_DHCSR_C_HALT_Pos 1U /*!< CoreDebug DHCSR: C_HALT Position */ -#define CoreDebug_DHCSR_C_HALT_Msk (1UL << CoreDebug_DHCSR_C_HALT_Pos) /*!< CoreDebug DHCSR: C_HALT Mask */ - -#define CoreDebug_DHCSR_C_DEBUGEN_Pos 0U /*!< CoreDebug DHCSR: C_DEBUGEN Position */ -#define CoreDebug_DHCSR_C_DEBUGEN_Msk (1UL /*<< CoreDebug_DHCSR_C_DEBUGEN_Pos*/) /*!< CoreDebug DHCSR: C_DEBUGEN Mask */ - -/* Debug Core Register Selector Register Definitions */ -#define CoreDebug_DCRSR_REGWnR_Pos 16U /*!< CoreDebug DCRSR: REGWnR Position */ -#define CoreDebug_DCRSR_REGWnR_Msk (1UL << CoreDebug_DCRSR_REGWnR_Pos) /*!< CoreDebug DCRSR: REGWnR Mask */ - -#define CoreDebug_DCRSR_REGSEL_Pos 0U /*!< CoreDebug DCRSR: REGSEL Position */ -#define CoreDebug_DCRSR_REGSEL_Msk (0x1FUL /*<< CoreDebug_DCRSR_REGSEL_Pos*/) /*!< CoreDebug DCRSR: REGSEL Mask */ - -/* Debug Exception and Monitor Control Register */ -#define CoreDebug_DEMCR_DWTENA_Pos 24U /*!< CoreDebug DEMCR: DWTENA Position */ -#define CoreDebug_DEMCR_DWTENA_Msk (1UL << CoreDebug_DEMCR_DWTENA_Pos) /*!< CoreDebug DEMCR: DWTENA Mask */ - -#define CoreDebug_DEMCR_VC_HARDERR_Pos 10U /*!< CoreDebug DEMCR: VC_HARDERR Position */ -#define CoreDebug_DEMCR_VC_HARDERR_Msk (1UL << CoreDebug_DEMCR_VC_HARDERR_Pos) /*!< CoreDebug DEMCR: VC_HARDERR Mask */ - -#define CoreDebug_DEMCR_VC_CORERESET_Pos 0U /*!< CoreDebug DEMCR: VC_CORERESET Position */ -#define CoreDebug_DEMCR_VC_CORERESET_Msk (1UL /*<< CoreDebug_DEMCR_VC_CORERESET_Pos*/) /*!< CoreDebug DEMCR: VC_CORERESET Mask */ - -/* Debug Authentication Control Register Definitions */ -#define CoreDebug_DAUTHCTRL_INTSPNIDEN_Pos 3U /*!< CoreDebug DAUTHCTRL: INTSPNIDEN, Position */ -#define CoreDebug_DAUTHCTRL_INTSPNIDEN_Msk (1UL << CoreDebug_DAUTHCTRL_INTSPNIDEN_Pos) /*!< CoreDebug DAUTHCTRL: INTSPNIDEN, Mask */ - -#define CoreDebug_DAUTHCTRL_SPNIDENSEL_Pos 2U /*!< CoreDebug DAUTHCTRL: SPNIDENSEL Position */ -#define CoreDebug_DAUTHCTRL_SPNIDENSEL_Msk (1UL << CoreDebug_DAUTHCTRL_SPNIDENSEL_Pos) /*!< CoreDebug DAUTHCTRL: SPNIDENSEL Mask */ - -#define CoreDebug_DAUTHCTRL_INTSPIDEN_Pos 1U /*!< CoreDebug DAUTHCTRL: INTSPIDEN Position */ -#define CoreDebug_DAUTHCTRL_INTSPIDEN_Msk (1UL << CoreDebug_DAUTHCTRL_INTSPIDEN_Pos) /*!< CoreDebug DAUTHCTRL: INTSPIDEN Mask */ - -#define CoreDebug_DAUTHCTRL_SPIDENSEL_Pos 0U /*!< CoreDebug DAUTHCTRL: SPIDENSEL Position */ -#define CoreDebug_DAUTHCTRL_SPIDENSEL_Msk (1UL /*<< CoreDebug_DAUTHCTRL_SPIDENSEL_Pos*/) /*!< CoreDebug DAUTHCTRL: SPIDENSEL Mask */ - -/* Debug Security Control and Status Register Definitions */ -#define CoreDebug_DSCSR_CDS_Pos 16U /*!< CoreDebug DSCSR: CDS Position */ -#define CoreDebug_DSCSR_CDS_Msk (1UL << CoreDebug_DSCSR_CDS_Pos) /*!< CoreDebug DSCSR: CDS Mask */ - -#define CoreDebug_DSCSR_SBRSEL_Pos 1U /*!< CoreDebug DSCSR: SBRSEL Position */ -#define CoreDebug_DSCSR_SBRSEL_Msk (1UL << CoreDebug_DSCSR_SBRSEL_Pos) /*!< CoreDebug DSCSR: SBRSEL Mask */ - -#define CoreDebug_DSCSR_SBRSELEN_Pos 0U /*!< CoreDebug DSCSR: SBRSELEN Position */ -#define CoreDebug_DSCSR_SBRSELEN_Msk (1UL /*<< CoreDebug_DSCSR_SBRSELEN_Pos*/) /*!< CoreDebug DSCSR: SBRSELEN Mask */ - -/*@} end of group CMSIS_CoreDebug */ - - -/** - \ingroup CMSIS_core_register - \defgroup CMSIS_core_bitfield Core register bit field macros - \brief Macros for use with bit field definitions (xxx_Pos, xxx_Msk). - @{ - */ - -/** - \brief Mask and shift a bit field value for use in a register bit range. - \param[in] field Name of the register bit field. - \param[in] value Value of the bit field. This parameter is interpreted as an uint32_t type. - \return Masked and shifted value. -*/ -#define _VAL2FLD(field, value) (((uint32_t)(value) << field ## _Pos) & field ## _Msk) - -/** - \brief Mask and shift a register value to extract a bit filed value. - \param[in] field Name of the register bit field. - \param[in] value Value of register. This parameter is interpreted as an uint32_t type. - \return Masked and shifted bit field value. -*/ -#define _FLD2VAL(field, value) (((uint32_t)(value) & field ## _Msk) >> field ## _Pos) - -/*@} end of group CMSIS_core_bitfield */ - - -/** - \ingroup CMSIS_core_register - \defgroup CMSIS_core_base Core Definitions - \brief Definitions for base addresses, unions, and structures. - @{ - */ - -/* Memory mapping of Core Hardware */ - #define SCS_BASE (0xE000E000UL) /*!< System Control Space Base Address */ - #define DWT_BASE (0xE0001000UL) /*!< DWT Base Address */ - #define TPI_BASE (0xE0040000UL) /*!< TPI Base Address */ - #define CoreDebug_BASE (0xE000EDF0UL) /*!< Core Debug Base Address */ - #define SysTick_BASE (SCS_BASE + 0x0010UL) /*!< SysTick Base Address */ - #define NVIC_BASE (SCS_BASE + 0x0100UL) /*!< NVIC Base Address */ - #define SCB_BASE (SCS_BASE + 0x0D00UL) /*!< System Control Block Base Address */ - - - #define SCB ((SCB_Type *) SCB_BASE ) /*!< SCB configuration struct */ - #define SysTick ((SysTick_Type *) SysTick_BASE ) /*!< SysTick configuration struct */ - #define NVIC ((NVIC_Type *) NVIC_BASE ) /*!< NVIC configuration struct */ - #define DWT ((DWT_Type *) DWT_BASE ) /*!< DWT configuration struct */ - #define TPI ((TPI_Type *) TPI_BASE ) /*!< TPI configuration struct */ - #define CoreDebug ((CoreDebug_Type *) CoreDebug_BASE ) /*!< Core Debug configuration struct */ - - #if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) - #define MPU_BASE (SCS_BASE + 0x0D90UL) /*!< Memory Protection Unit */ - #define MPU ((MPU_Type *) MPU_BASE ) /*!< Memory Protection Unit */ - #endif - - #if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) - #define SAU_BASE (SCS_BASE + 0x0DD0UL) /*!< Security Attribution Unit */ - #define SAU ((SAU_Type *) SAU_BASE ) /*!< Security Attribution Unit */ - #endif - -#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) - #define SCS_BASE_NS (0xE002E000UL) /*!< System Control Space Base Address (non-secure address space) */ - #define CoreDebug_BASE_NS (0xE002EDF0UL) /*!< Core Debug Base Address (non-secure address space) */ - #define SysTick_BASE_NS (SCS_BASE_NS + 0x0010UL) /*!< SysTick Base Address (non-secure address space) */ - #define NVIC_BASE_NS (SCS_BASE_NS + 0x0100UL) /*!< NVIC Base Address (non-secure address space) */ - #define SCB_BASE_NS (SCS_BASE_NS + 0x0D00UL) /*!< System Control Block Base Address (non-secure address space) */ - - #define SCB_NS ((SCB_Type *) SCB_BASE_NS ) /*!< SCB configuration struct (non-secure address space) */ - #define SysTick_NS ((SysTick_Type *) SysTick_BASE_NS ) /*!< SysTick configuration struct (non-secure address space) */ - #define NVIC_NS ((NVIC_Type *) NVIC_BASE_NS ) /*!< NVIC configuration struct (non-secure address space) */ - #define CoreDebug_NS ((CoreDebug_Type *) CoreDebug_BASE_NS) /*!< Core Debug configuration struct (non-secure address space) */ - - #if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) - #define MPU_BASE_NS (SCS_BASE_NS + 0x0D90UL) /*!< Memory Protection Unit (non-secure address space) */ - #define MPU_NS ((MPU_Type *) MPU_BASE_NS ) /*!< Memory Protection Unit (non-secure address space) */ - #endif - -#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */ -/*@} */ - - - -/******************************************************************************* - * Hardware Abstraction Layer - Core Function Interface contains: - - Core NVIC Functions - - Core SysTick Functions - - Core Register Access Functions - ******************************************************************************/ -/** - \defgroup CMSIS_Core_FunctionInterface Functions and Instructions Reference -*/ - - - -/* ########################## NVIC functions #################################### */ -/** - \ingroup CMSIS_Core_FunctionInterface - \defgroup CMSIS_Core_NVICFunctions NVIC Functions - \brief Functions that manage interrupts and exceptions via the NVIC. - @{ - */ - -#ifdef CMSIS_NVIC_VIRTUAL - #ifndef CMSIS_NVIC_VIRTUAL_HEADER_FILE - #define CMSIS_NVIC_VIRTUAL_HEADER_FILE "cmsis_nvic_virtual.h" - #endif - #include CMSIS_NVIC_VIRTUAL_HEADER_FILE -#else -/*#define NVIC_SetPriorityGrouping __NVIC_SetPriorityGrouping not available for Cortex-M23 */ -/*#define NVIC_GetPriorityGrouping __NVIC_GetPriorityGrouping not available for Cortex-M23 */ - #define NVIC_EnableIRQ __NVIC_EnableIRQ - #define NVIC_GetEnableIRQ __NVIC_GetEnableIRQ - #define NVIC_DisableIRQ __NVIC_DisableIRQ - #define NVIC_GetPendingIRQ __NVIC_GetPendingIRQ - #define NVIC_SetPendingIRQ __NVIC_SetPendingIRQ - #define NVIC_ClearPendingIRQ __NVIC_ClearPendingIRQ - #define NVIC_GetActive __NVIC_GetActive - #define NVIC_SetPriority __NVIC_SetPriority - #define NVIC_GetPriority __NVIC_GetPriority - #define NVIC_SystemReset __NVIC_SystemReset -#endif /* CMSIS_NVIC_VIRTUAL */ - -#ifdef CMSIS_VECTAB_VIRTUAL - #ifndef CMSIS_VECTAB_VIRTUAL_HEADER_FILE - #define CMSIS_VECTAB_VIRTUAL_HEADER_FILE "cmsis_vectab_virtual.h" - #endif - #include CMSIS_VECTAB_VIRTUAL_HEADER_FILE -#else - #define NVIC_SetVector __NVIC_SetVector - #define NVIC_GetVector __NVIC_GetVector -#endif /* (CMSIS_VECTAB_VIRTUAL) */ - -#define NVIC_USER_IRQ_OFFSET 16 - - -/* Interrupt Priorities are WORD accessible only under Armv6-M */ -/* The following MACROS handle generation of the register offset and byte masks */ -#define _BIT_SHIFT(IRQn) ( ((((uint32_t)(int32_t)(IRQn)) ) & 0x03UL) * 8UL) -#define _SHP_IDX(IRQn) ( (((((uint32_t)(int32_t)(IRQn)) & 0x0FUL)-8UL) >> 2UL) ) -#define _IP_IDX(IRQn) ( (((uint32_t)(int32_t)(IRQn)) >> 2UL) ) - - -/** - \brief Enable Interrupt - \details Enables a device specific interrupt in the NVIC interrupt controller. - \param [in] IRQn Device specific interrupt number. - \note IRQn must not be negative. - */ -__STATIC_INLINE void __NVIC_EnableIRQ(IRQn_Type IRQn) -{ - if ((int32_t)(IRQn) >= 0) - { - NVIC->ISER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); - } -} - - -/** - \brief Get Interrupt Enable status - \details Returns a device specific interrupt enable status from the NVIC interrupt controller. - \param [in] IRQn Device specific interrupt number. - \return 0 Interrupt is not enabled. - \return 1 Interrupt is enabled. - \note IRQn must not be negative. - */ -__STATIC_INLINE uint32_t __NVIC_GetEnableIRQ(IRQn_Type IRQn) -{ - if ((int32_t)(IRQn) >= 0) - { - return((uint32_t)(((NVIC->ISER[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); - } - else - { - return(0U); - } -} - - -/** - \brief Disable Interrupt - \details Disables a device specific interrupt in the NVIC interrupt controller. - \param [in] IRQn Device specific interrupt number. - \note IRQn must not be negative. - */ -__STATIC_INLINE void __NVIC_DisableIRQ(IRQn_Type IRQn) -{ - if ((int32_t)(IRQn) >= 0) - { - NVIC->ICER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); - __DSB(); - __ISB(); - } -} - - -/** - \brief Get Pending Interrupt - \details Reads the NVIC pending register and returns the pending bit for the specified device specific interrupt. - \param [in] IRQn Device specific interrupt number. - \return 0 Interrupt status is not pending. - \return 1 Interrupt status is pending. - \note IRQn must not be negative. - */ -__STATIC_INLINE uint32_t __NVIC_GetPendingIRQ(IRQn_Type IRQn) -{ - if ((int32_t)(IRQn) >= 0) - { - return((uint32_t)(((NVIC->ISPR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); - } - else - { - return(0U); - } -} - - -/** - \brief Set Pending Interrupt - \details Sets the pending bit of a device specific interrupt in the NVIC pending register. - \param [in] IRQn Device specific interrupt number. - \note IRQn must not be negative. - */ -__STATIC_INLINE void __NVIC_SetPendingIRQ(IRQn_Type IRQn) -{ - if ((int32_t)(IRQn) >= 0) - { - NVIC->ISPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); - } -} - - -/** - \brief Clear Pending Interrupt - \details Clears the pending bit of a device specific interrupt in the NVIC pending register. - \param [in] IRQn Device specific interrupt number. - \note IRQn must not be negative. - */ -__STATIC_INLINE void __NVIC_ClearPendingIRQ(IRQn_Type IRQn) -{ - if ((int32_t)(IRQn) >= 0) - { - NVIC->ICPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); - } -} - - -/** - \brief Get Active Interrupt - \details Reads the active register in the NVIC and returns the active bit for the device specific interrupt. - \param [in] IRQn Device specific interrupt number. - \return 0 Interrupt status is not active. - \return 1 Interrupt status is active. - \note IRQn must not be negative. - */ -__STATIC_INLINE uint32_t __NVIC_GetActive(IRQn_Type IRQn) -{ - if ((int32_t)(IRQn) >= 0) - { - return((uint32_t)(((NVIC->IABR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); - } - else - { - return(0U); - } -} - - -#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) -/** - \brief Get Interrupt Target State - \details Reads the interrupt target field in the NVIC and returns the interrupt target bit for the device specific interrupt. - \param [in] IRQn Device specific interrupt number. - \return 0 if interrupt is assigned to Secure - \return 1 if interrupt is assigned to Non Secure - \note IRQn must not be negative. - */ -__STATIC_INLINE uint32_t NVIC_GetTargetState(IRQn_Type IRQn) -{ - if ((int32_t)(IRQn) >= 0) - { - return((uint32_t)(((NVIC->ITNS[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); - } - else - { - return(0U); - } -} - - -/** - \brief Set Interrupt Target State - \details Sets the interrupt target field in the NVIC and returns the interrupt target bit for the device specific interrupt. - \param [in] IRQn Device specific interrupt number. - \return 0 if interrupt is assigned to Secure - 1 if interrupt is assigned to Non Secure - \note IRQn must not be negative. - */ -__STATIC_INLINE uint32_t NVIC_SetTargetState(IRQn_Type IRQn) -{ - if ((int32_t)(IRQn) >= 0) - { - NVIC->ITNS[(((uint32_t)IRQn) >> 5UL)] |= ((uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL))); - return((uint32_t)(((NVIC->ITNS[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); - } - else - { - return(0U); - } -} - - -/** - \brief Clear Interrupt Target State - \details Clears the interrupt target field in the NVIC and returns the interrupt target bit for the device specific interrupt. - \param [in] IRQn Device specific interrupt number. - \return 0 if interrupt is assigned to Secure - 1 if interrupt is assigned to Non Secure - \note IRQn must not be negative. - */ -__STATIC_INLINE uint32_t NVIC_ClearTargetState(IRQn_Type IRQn) -{ - if ((int32_t)(IRQn) >= 0) - { - NVIC->ITNS[(((uint32_t)IRQn) >> 5UL)] &= ~((uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL))); - return((uint32_t)(((NVIC->ITNS[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); - } - else - { - return(0U); - } -} -#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */ - - -/** - \brief Set Interrupt Priority - \details Sets the priority of a device specific interrupt or a processor exception. - The interrupt number can be positive to specify a device specific interrupt, - or negative to specify a processor exception. - \param [in] IRQn Interrupt number. - \param [in] priority Priority to set. - \note The priority cannot be set for every processor exception. - */ -__STATIC_INLINE void __NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority) -{ - if ((int32_t)(IRQn) >= 0) - { - NVIC->IPR[_IP_IDX(IRQn)] = ((uint32_t)(NVIC->IPR[_IP_IDX(IRQn)] & ~(0xFFUL << _BIT_SHIFT(IRQn))) | - (((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL) << _BIT_SHIFT(IRQn))); - } - else - { - SCB->SHPR[_SHP_IDX(IRQn)] = ((uint32_t)(SCB->SHPR[_SHP_IDX(IRQn)] & ~(0xFFUL << _BIT_SHIFT(IRQn))) | - (((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL) << _BIT_SHIFT(IRQn))); - } -} - - -/** - \brief Get Interrupt Priority - \details Reads the priority of a device specific interrupt or a processor exception. - The interrupt number can be positive to specify a device specific interrupt, - or negative to specify a processor exception. - \param [in] IRQn Interrupt number. - \return Interrupt Priority. - Value is aligned automatically to the implemented priority bits of the microcontroller. - */ -__STATIC_INLINE uint32_t __NVIC_GetPriority(IRQn_Type IRQn) -{ - - if ((int32_t)(IRQn) >= 0) - { - return((uint32_t)(((NVIC->IPR[ _IP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) & (uint32_t)0xFFUL) >> (8U - __NVIC_PRIO_BITS))); - } - else - { - return((uint32_t)(((SCB->SHPR[_SHP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) & (uint32_t)0xFFUL) >> (8U - __NVIC_PRIO_BITS))); - } -} - - -/** - \brief Set Interrupt Vector - \details Sets an interrupt vector in SRAM based interrupt vector table. - The interrupt number can be positive to specify a device specific interrupt, - or negative to specify a processor exception. - VTOR must been relocated to SRAM before. - If VTOR is not present address 0 must be mapped to SRAM. - \param [in] IRQn Interrupt number - \param [in] vector Address of interrupt handler function - */ -__STATIC_INLINE void __NVIC_SetVector(IRQn_Type IRQn, uint32_t vector) -{ -#if defined (__VTOR_PRESENT) && (__VTOR_PRESENT == 1U) - uint32_t *vectors = (uint32_t *)SCB->VTOR; -#else - uint32_t *vectors = (uint32_t *)0x0U; -#endif - vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET] = vector; -} - - -/** - \brief Get Interrupt Vector - \details Reads an interrupt vector from interrupt vector table. - The interrupt number can be positive to specify a device specific interrupt, - or negative to specify a processor exception. - \param [in] IRQn Interrupt number. - \return Address of interrupt handler function - */ -__STATIC_INLINE uint32_t __NVIC_GetVector(IRQn_Type IRQn) -{ -#if defined (__VTOR_PRESENT) && (__VTOR_PRESENT == 1U) - uint32_t *vectors = (uint32_t *)SCB->VTOR; -#else - uint32_t *vectors = (uint32_t *)0x0U; -#endif - return vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET]; -} - - -/** - \brief System Reset - \details Initiates a system reset request to reset the MCU. - */ -__STATIC_INLINE void __NVIC_SystemReset(void) -{ - __DSB(); /* Ensure all outstanding memory accesses included - buffered write are completed before reset */ - SCB->AIRCR = ((0x5FAUL << SCB_AIRCR_VECTKEY_Pos) | - SCB_AIRCR_SYSRESETREQ_Msk); - __DSB(); /* Ensure completion of memory access */ - - for(;;) /* wait until reset */ - { - __NOP(); - } -} - -#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) -/** - \brief Enable Interrupt (non-secure) - \details Enables a device specific interrupt in the non-secure NVIC interrupt controller when in secure state. - \param [in] IRQn Device specific interrupt number. - \note IRQn must not be negative. - */ -__STATIC_INLINE void TZ_NVIC_EnableIRQ_NS(IRQn_Type IRQn) -{ - if ((int32_t)(IRQn) >= 0) - { - NVIC_NS->ISER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); - } -} - - -/** - \brief Get Interrupt Enable status (non-secure) - \details Returns a device specific interrupt enable status from the non-secure NVIC interrupt controller when in secure state. - \param [in] IRQn Device specific interrupt number. - \return 0 Interrupt is not enabled. - \return 1 Interrupt is enabled. - \note IRQn must not be negative. - */ -__STATIC_INLINE uint32_t TZ_NVIC_GetEnableIRQ_NS(IRQn_Type IRQn) -{ - if ((int32_t)(IRQn) >= 0) - { - return((uint32_t)(((NVIC_NS->ISER[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); - } - else - { - return(0U); - } -} - - -/** - \brief Disable Interrupt (non-secure) - \details Disables a device specific interrupt in the non-secure NVIC interrupt controller when in secure state. - \param [in] IRQn Device specific interrupt number. - \note IRQn must not be negative. - */ -__STATIC_INLINE void TZ_NVIC_DisableIRQ_NS(IRQn_Type IRQn) -{ - if ((int32_t)(IRQn) >= 0) - { - NVIC_NS->ICER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); - } -} - - -/** - \brief Get Pending Interrupt (non-secure) - \details Reads the NVIC pending register in the non-secure NVIC when in secure state and returns the pending bit for the specified device specific interrupt. - \param [in] IRQn Device specific interrupt number. - \return 0 Interrupt status is not pending. - \return 1 Interrupt status is pending. - \note IRQn must not be negative. - */ -__STATIC_INLINE uint32_t TZ_NVIC_GetPendingIRQ_NS(IRQn_Type IRQn) -{ - if ((int32_t)(IRQn) >= 0) - { - return((uint32_t)(((NVIC_NS->ISPR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); - } - else - { - return(0U); - } -} - - -/** - \brief Set Pending Interrupt (non-secure) - \details Sets the pending bit of a device specific interrupt in the non-secure NVIC pending register when in secure state. - \param [in] IRQn Device specific interrupt number. - \note IRQn must not be negative. - */ -__STATIC_INLINE void TZ_NVIC_SetPendingIRQ_NS(IRQn_Type IRQn) -{ - if ((int32_t)(IRQn) >= 0) - { - NVIC_NS->ISPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); - } -} - - -/** - \brief Clear Pending Interrupt (non-secure) - \details Clears the pending bit of a device specific interrupt in the non-secure NVIC pending register when in secure state. - \param [in] IRQn Device specific interrupt number. - \note IRQn must not be negative. - */ -__STATIC_INLINE void TZ_NVIC_ClearPendingIRQ_NS(IRQn_Type IRQn) -{ - if ((int32_t)(IRQn) >= 0) - { - NVIC_NS->ICPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); - } -} - - -/** - \brief Get Active Interrupt (non-secure) - \details Reads the active register in non-secure NVIC when in secure state and returns the active bit for the device specific interrupt. - \param [in] IRQn Device specific interrupt number. - \return 0 Interrupt status is not active. - \return 1 Interrupt status is active. - \note IRQn must not be negative. - */ -__STATIC_INLINE uint32_t TZ_NVIC_GetActive_NS(IRQn_Type IRQn) -{ - if ((int32_t)(IRQn) >= 0) - { - return((uint32_t)(((NVIC_NS->IABR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); - } - else - { - return(0U); - } -} - - -/** - \brief Set Interrupt Priority (non-secure) - \details Sets the priority of a non-secure device specific interrupt or a non-secure processor exception when in secure state. - The interrupt number can be positive to specify a device specific interrupt, - or negative to specify a processor exception. - \param [in] IRQn Interrupt number. - \param [in] priority Priority to set. - \note The priority cannot be set for every non-secure processor exception. - */ -__STATIC_INLINE void TZ_NVIC_SetPriority_NS(IRQn_Type IRQn, uint32_t priority) -{ - if ((int32_t)(IRQn) >= 0) - { - NVIC_NS->IPR[_IP_IDX(IRQn)] = ((uint32_t)(NVIC_NS->IPR[_IP_IDX(IRQn)] & ~(0xFFUL << _BIT_SHIFT(IRQn))) | - (((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL) << _BIT_SHIFT(IRQn))); - } - else - { - SCB_NS->SHPR[_SHP_IDX(IRQn)] = ((uint32_t)(SCB_NS->SHPR[_SHP_IDX(IRQn)] & ~(0xFFUL << _BIT_SHIFT(IRQn))) | - (((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL) << _BIT_SHIFT(IRQn))); - } -} - - -/** - \brief Get Interrupt Priority (non-secure) - \details Reads the priority of a non-secure device specific interrupt or a non-secure processor exception when in secure state. - The interrupt number can be positive to specify a device specific interrupt, - or negative to specify a processor exception. - \param [in] IRQn Interrupt number. - \return Interrupt Priority. Value is aligned automatically to the implemented priority bits of the microcontroller. - */ -__STATIC_INLINE uint32_t TZ_NVIC_GetPriority_NS(IRQn_Type IRQn) -{ - - if ((int32_t)(IRQn) >= 0) - { - return((uint32_t)(((NVIC_NS->IPR[ _IP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) & (uint32_t)0xFFUL) >> (8U - __NVIC_PRIO_BITS))); - } - else - { - return((uint32_t)(((SCB_NS->SHPR[_SHP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) & (uint32_t)0xFFUL) >> (8U - __NVIC_PRIO_BITS))); - } -} -#endif /* defined (__ARM_FEATURE_CMSE) &&(__ARM_FEATURE_CMSE == 3U) */ - -/*@} end of CMSIS_Core_NVICFunctions */ - -/* ########################## MPU functions #################################### */ - -#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) - -#include "mpu_armv8.h" - -#endif - -/* ########################## FPU functions #################################### */ -/** - \ingroup CMSIS_Core_FunctionInterface - \defgroup CMSIS_Core_FpuFunctions FPU Functions - \brief Function that provides FPU type. - @{ - */ - -/** - \brief get FPU type - \details returns the FPU type - \returns - - \b 0: No FPU - - \b 1: Single precision FPU - - \b 2: Double + Single precision FPU - */ -__STATIC_INLINE uint32_t SCB_GetFPUType(void) -{ - return 0U; /* No FPU */ -} - - -/*@} end of CMSIS_Core_FpuFunctions */ - - - -/* ########################## SAU functions #################################### */ -/** - \ingroup CMSIS_Core_FunctionInterface - \defgroup CMSIS_Core_SAUFunctions SAU Functions - \brief Functions that configure the SAU. - @{ - */ - -#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) - -/** - \brief Enable SAU - \details Enables the Security Attribution Unit (SAU). - */ -__STATIC_INLINE void TZ_SAU_Enable(void) -{ - SAU->CTRL |= (SAU_CTRL_ENABLE_Msk); -} - - - -/** - \brief Disable SAU - \details Disables the Security Attribution Unit (SAU). - */ -__STATIC_INLINE void TZ_SAU_Disable(void) -{ - SAU->CTRL &= ~(SAU_CTRL_ENABLE_Msk); -} - -#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */ - -/*@} end of CMSIS_Core_SAUFunctions */ - - - - -/* ################################## SysTick function ############################################ */ -/** - \ingroup CMSIS_Core_FunctionInterface - \defgroup CMSIS_Core_SysTickFunctions SysTick Functions - \brief Functions that configure the System. - @{ - */ - -#if defined (__Vendor_SysTickConfig) && (__Vendor_SysTickConfig == 0U) - -/** - \brief System Tick Configuration - \details Initializes the System Timer and its interrupt, and starts the System Tick Timer. - Counter is in free running mode to generate periodic interrupts. - \param [in] ticks Number of ticks between two interrupts. - \return 0 Function succeeded. - \return 1 Function failed. - \note When the variable __Vendor_SysTickConfig is set to 1, then the - function SysTick_Config is not included. In this case, the file device.h - must contain a vendor-specific implementation of this function. - */ -__STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks) -{ - if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk) - { - return (1UL); /* Reload value impossible */ - } - - SysTick->LOAD = (uint32_t)(ticks - 1UL); /* set reload register */ - NVIC_SetPriority (SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */ - SysTick->VAL = 0UL; /* Load the SysTick Counter Value */ - SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk | - SysTick_CTRL_TICKINT_Msk | - SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */ - return (0UL); /* Function successful */ -} - -#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) -/** - \brief System Tick Configuration (non-secure) - \details Initializes the non-secure System Timer and its interrupt when in secure state, and starts the System Tick Timer. - Counter is in free running mode to generate periodic interrupts. - \param [in] ticks Number of ticks between two interrupts. - \return 0 Function succeeded. - \return 1 Function failed. - \note When the variable __Vendor_SysTickConfig is set to 1, then the - function TZ_SysTick_Config_NS is not included. In this case, the file device.h - must contain a vendor-specific implementation of this function. - - */ -__STATIC_INLINE uint32_t TZ_SysTick_Config_NS(uint32_t ticks) -{ - if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk) - { - return (1UL); /* Reload value impossible */ - } - - SysTick_NS->LOAD = (uint32_t)(ticks - 1UL); /* set reload register */ - TZ_NVIC_SetPriority_NS (SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */ - SysTick_NS->VAL = 0UL; /* Load the SysTick Counter Value */ - SysTick_NS->CTRL = SysTick_CTRL_CLKSOURCE_Msk | - SysTick_CTRL_TICKINT_Msk | - SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */ - return (0UL); /* Function successful */ -} -#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */ - -#endif - -/*@} end of CMSIS_Core_SysTickFunctions */ - - - - -#ifdef __cplusplus -} -#endif - -#endif /* __CORE_CM23_H_DEPENDANT */ - -#endif /* __CMSIS_GENERIC */ diff --git a/bsp/essemi/es32f0271/libraries/CMSIS/Include/core_cm3.h b/bsp/essemi/es32f0271/libraries/CMSIS/Include/core_cm3.h deleted file mode 100644 index a2c0d08057..0000000000 --- a/bsp/essemi/es32f0271/libraries/CMSIS/Include/core_cm3.h +++ /dev/null @@ -1,1933 +0,0 @@ -/**************************************************************************//** - * @file core_cm3.h - * @brief CMSIS Cortex-M3 Core Peripheral Access Layer Header File - * @version V5.0.5 - * @date 08. January 2018 - ******************************************************************************/ -/* - * Copyright (c) 2009-2017 ARM Limited. All rights reserved. - * - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed under the Apache License, Version 2.0 (the License); you may - * not use this file except in compliance with the License. - * You may obtain a copy of the License at - * - * www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an AS IS BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - */ - -#if defined ( __ICCARM__ ) - #pragma system_include /* treat file as system include file for MISRA check */ -#elif defined (__clang__) - #pragma clang system_header /* treat file as system include file */ -#endif - -#ifndef __CORE_CM3_H_GENERIC -#define __CORE_CM3_H_GENERIC - -#include - -#ifdef __cplusplus - extern "C" { -#endif - -/** - \page CMSIS_MISRA_Exceptions MISRA-C:2004 Compliance Exceptions - CMSIS violates the following MISRA-C:2004 rules: - - \li Required Rule 8.5, object/function definition in header file.
- Function definitions in header files are used to allow 'inlining'. - - \li Required Rule 18.4, declaration of union type or object of union type: '{...}'.
- Unions are used for effective representation of core registers. - - \li Advisory Rule 19.7, Function-like macro defined.
- Function-like macros are used to allow more efficient code. - */ - - -/******************************************************************************* - * CMSIS definitions - ******************************************************************************/ -/** - \ingroup Cortex_M3 - @{ - */ - -#include "cmsis_version.h" - -/* CMSIS CM3 definitions */ -#define __CM3_CMSIS_VERSION_MAIN (__CM_CMSIS_VERSION_MAIN) /*!< \deprecated [31:16] CMSIS HAL main version */ -#define __CM3_CMSIS_VERSION_SUB (__CM_CMSIS_VERSION_SUB) /*!< \deprecated [15:0] CMSIS HAL sub version */ -#define __CM3_CMSIS_VERSION ((__CM3_CMSIS_VERSION_MAIN << 16U) | \ - __CM3_CMSIS_VERSION_SUB ) /*!< \deprecated CMSIS HAL version number */ - -#define __CORTEX_M (3U) /*!< Cortex-M Core */ - -/** __FPU_USED indicates whether an FPU is used or not. - This core does not support an FPU at all -*/ -#define __FPU_USED 0U - -#if defined ( __CC_ARM ) - #if defined __TARGET_FPU_VFP - #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" - #endif - -#elif defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) - #if defined __ARM_PCS_VFP - #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" - #endif - -#elif defined ( __GNUC__ ) - #if defined (__VFP_FP__) && !defined(__SOFTFP__) - #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" - #endif - -#elif defined ( __ICCARM__ ) - #if defined __ARMVFP__ - #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" - #endif - -#elif defined ( __TI_ARM__ ) - #if defined __TI_VFP_SUPPORT__ - #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" - #endif - -#elif defined ( __TASKING__ ) - #if defined __FPU_VFP__ - #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" - #endif - -#elif defined ( __CSMC__ ) - #if ( __CSMC__ & 0x400U) - #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" - #endif - -#endif - -#include "cmsis_compiler.h" /* CMSIS compiler specific defines */ - - -#ifdef __cplusplus -} -#endif - -#endif /* __CORE_CM3_H_GENERIC */ - -#ifndef __CMSIS_GENERIC - -#ifndef __CORE_CM3_H_DEPENDANT -#define __CORE_CM3_H_DEPENDANT - -#ifdef __cplusplus - extern "C" { -#endif - -/* check device defines and use defaults */ -#if defined __CHECK_DEVICE_DEFINES - #ifndef __CM3_REV - #define __CM3_REV 0x0200U - #warning "__CM3_REV not defined in device header file; using default!" - #endif - - #ifndef __MPU_PRESENT - #define __MPU_PRESENT 0U - #warning "__MPU_PRESENT not defined in device header file; using default!" - #endif - - #ifndef __NVIC_PRIO_BITS - #define __NVIC_PRIO_BITS 3U - #warning "__NVIC_PRIO_BITS not defined in device header file; using default!" - #endif - - #ifndef __Vendor_SysTickConfig - #define __Vendor_SysTickConfig 0U - #warning "__Vendor_SysTickConfig not defined in device header file; using default!" - #endif -#endif - -/* IO definitions (access restrictions to peripheral registers) */ -/** - \defgroup CMSIS_glob_defs CMSIS Global Defines - - IO Type Qualifiers are used - \li to specify the access to peripheral variables. - \li for automatic generation of peripheral register debug information. -*/ -#ifdef __cplusplus - #define __I volatile /*!< Defines 'read only' permissions */ -#else - #define __I volatile const /*!< Defines 'read only' permissions */ -#endif -#define __O volatile /*!< Defines 'write only' permissions */ -#define __IO volatile /*!< Defines 'read / write' permissions */ - -/* following defines should be used for structure members */ -#define __IM volatile const /*! Defines 'read only' structure member permissions */ -#define __OM volatile /*! Defines 'write only' structure member permissions */ -#define __IOM volatile /*! Defines 'read / write' structure member permissions */ - -/*@} end of group Cortex_M3 */ - - - -/******************************************************************************* - * Register Abstraction - Core Register contain: - - Core Register - - Core NVIC Register - - Core SCB Register - - Core SysTick Register - - Core Debug Register - - Core MPU Register - ******************************************************************************/ -/** - \defgroup CMSIS_core_register Defines and Type Definitions - \brief Type definitions and defines for Cortex-M processor based devices. -*/ - -/** - \ingroup CMSIS_core_register - \defgroup CMSIS_CORE Status and Control Registers - \brief Core Register type definitions. - @{ - */ - -/** - \brief Union type to access the Application Program Status Register (APSR). - */ -typedef union -{ - struct - { - uint32_t _reserved0:27; /*!< bit: 0..26 Reserved */ - uint32_t Q:1; /*!< bit: 27 Saturation condition flag */ - uint32_t V:1; /*!< bit: 28 Overflow condition code flag */ - uint32_t C:1; /*!< bit: 29 Carry condition code flag */ - uint32_t Z:1; /*!< bit: 30 Zero condition code flag */ - uint32_t N:1; /*!< bit: 31 Negative condition code flag */ - } b; /*!< Structure used for bit access */ - uint32_t w; /*!< Type used for word access */ -} APSR_Type; - -/* APSR Register Definitions */ -#define APSR_N_Pos 31U /*!< APSR: N Position */ -#define APSR_N_Msk (1UL << APSR_N_Pos) /*!< APSR: N Mask */ - -#define APSR_Z_Pos 30U /*!< APSR: Z Position */ -#define APSR_Z_Msk (1UL << APSR_Z_Pos) /*!< APSR: Z Mask */ - -#define APSR_C_Pos 29U /*!< APSR: C Position */ -#define APSR_C_Msk (1UL << APSR_C_Pos) /*!< APSR: C Mask */ - -#define APSR_V_Pos 28U /*!< APSR: V Position */ -#define APSR_V_Msk (1UL << APSR_V_Pos) /*!< APSR: V Mask */ - -#define APSR_Q_Pos 27U /*!< APSR: Q Position */ -#define APSR_Q_Msk (1UL << APSR_Q_Pos) /*!< APSR: Q Mask */ - - -/** - \brief Union type to access the Interrupt Program Status Register (IPSR). - */ -typedef union -{ - struct - { - uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */ - uint32_t _reserved0:23; /*!< bit: 9..31 Reserved */ - } b; /*!< Structure used for bit access */ - uint32_t w; /*!< Type used for word access */ -} IPSR_Type; - -/* IPSR Register Definitions */ -#define IPSR_ISR_Pos 0U /*!< IPSR: ISR Position */ -#define IPSR_ISR_Msk (0x1FFUL /*<< IPSR_ISR_Pos*/) /*!< IPSR: ISR Mask */ - - -/** - \brief Union type to access the Special-Purpose Program Status Registers (xPSR). - */ -typedef union -{ - struct - { - uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */ - uint32_t _reserved0:1; /*!< bit: 9 Reserved */ - uint32_t ICI_IT_1:6; /*!< bit: 10..15 ICI/IT part 1 */ - uint32_t _reserved1:8; /*!< bit: 16..23 Reserved */ - uint32_t T:1; /*!< bit: 24 Thumb bit */ - uint32_t ICI_IT_2:2; /*!< bit: 25..26 ICI/IT part 2 */ - uint32_t Q:1; /*!< bit: 27 Saturation condition flag */ - uint32_t V:1; /*!< bit: 28 Overflow condition code flag */ - uint32_t C:1; /*!< bit: 29 Carry condition code flag */ - uint32_t Z:1; /*!< bit: 30 Zero condition code flag */ - uint32_t N:1; /*!< bit: 31 Negative condition code flag */ - } b; /*!< Structure used for bit access */ - uint32_t w; /*!< Type used for word access */ -} xPSR_Type; - -/* xPSR Register Definitions */ -#define xPSR_N_Pos 31U /*!< xPSR: N Position */ -#define xPSR_N_Msk (1UL << xPSR_N_Pos) /*!< xPSR: N Mask */ - -#define xPSR_Z_Pos 30U /*!< xPSR: Z Position */ -#define xPSR_Z_Msk (1UL << xPSR_Z_Pos) /*!< xPSR: Z Mask */ - -#define xPSR_C_Pos 29U /*!< xPSR: C Position */ -#define xPSR_C_Msk (1UL << xPSR_C_Pos) /*!< xPSR: C Mask */ - -#define xPSR_V_Pos 28U /*!< xPSR: V Position */ -#define xPSR_V_Msk (1UL << xPSR_V_Pos) /*!< xPSR: V Mask */ - -#define xPSR_Q_Pos 27U /*!< xPSR: Q Position */ -#define xPSR_Q_Msk (1UL << xPSR_Q_Pos) /*!< xPSR: Q Mask */ - -#define xPSR_ICI_IT_2_Pos 25U /*!< xPSR: ICI/IT part 2 Position */ -#define xPSR_ICI_IT_2_Msk (3UL << xPSR_ICI_IT_2_Pos) /*!< xPSR: ICI/IT part 2 Mask */ - -#define xPSR_T_Pos 24U /*!< xPSR: T Position */ -#define xPSR_T_Msk (1UL << xPSR_T_Pos) /*!< xPSR: T Mask */ - -#define xPSR_ICI_IT_1_Pos 10U /*!< xPSR: ICI/IT part 1 Position */ -#define xPSR_ICI_IT_1_Msk (0x3FUL << xPSR_ICI_IT_1_Pos) /*!< xPSR: ICI/IT part 1 Mask */ - -#define xPSR_ISR_Pos 0U /*!< xPSR: ISR Position */ -#define xPSR_ISR_Msk (0x1FFUL /*<< xPSR_ISR_Pos*/) /*!< xPSR: ISR Mask */ - - -/** - \brief Union type to access the Control Registers (CONTROL). - */ -typedef union -{ - struct - { - uint32_t nPRIV:1; /*!< bit: 0 Execution privilege in Thread mode */ - uint32_t SPSEL:1; /*!< bit: 1 Stack to be used */ - uint32_t _reserved1:30; /*!< bit: 2..31 Reserved */ - } b; /*!< Structure used for bit access */ - uint32_t w; /*!< Type used for word access */ -} CONTROL_Type; - -/* CONTROL Register Definitions */ -#define CONTROL_SPSEL_Pos 1U /*!< CONTROL: SPSEL Position */ -#define CONTROL_SPSEL_Msk (1UL << CONTROL_SPSEL_Pos) /*!< CONTROL: SPSEL Mask */ - -#define CONTROL_nPRIV_Pos 0U /*!< CONTROL: nPRIV Position */ -#define CONTROL_nPRIV_Msk (1UL /*<< CONTROL_nPRIV_Pos*/) /*!< CONTROL: nPRIV Mask */ - -/*@} end of group CMSIS_CORE */ - - -/** - \ingroup CMSIS_core_register - \defgroup CMSIS_NVIC Nested Vectored Interrupt Controller (NVIC) - \brief Type definitions for the NVIC Registers - @{ - */ - -/** - \brief Structure type to access the Nested Vectored Interrupt Controller (NVIC). - */ -typedef struct -{ - __IOM uint32_t ISER[8U]; /*!< Offset: 0x000 (R/W) Interrupt Set Enable Register */ - uint32_t RESERVED0[24U]; - __IOM uint32_t ICER[8U]; /*!< Offset: 0x080 (R/W) Interrupt Clear Enable Register */ - uint32_t RSERVED1[24U]; - __IOM uint32_t ISPR[8U]; /*!< Offset: 0x100 (R/W) Interrupt Set Pending Register */ - uint32_t RESERVED2[24U]; - __IOM uint32_t ICPR[8U]; /*!< Offset: 0x180 (R/W) Interrupt Clear Pending Register */ - uint32_t RESERVED3[24U]; - __IOM uint32_t IABR[8U]; /*!< Offset: 0x200 (R/W) Interrupt Active bit Register */ - uint32_t RESERVED4[56U]; - __IOM uint8_t IP[240U]; /*!< Offset: 0x300 (R/W) Interrupt Priority Register (8Bit wide) */ - uint32_t RESERVED5[644U]; - __OM uint32_t STIR; /*!< Offset: 0xE00 ( /W) Software Trigger Interrupt Register */ -} NVIC_Type; - -/* Software Triggered Interrupt Register Definitions */ -#define NVIC_STIR_INTID_Pos 0U /*!< STIR: INTLINESNUM Position */ -#define NVIC_STIR_INTID_Msk (0x1FFUL /*<< NVIC_STIR_INTID_Pos*/) /*!< STIR: INTLINESNUM Mask */ - -/*@} end of group CMSIS_NVIC */ - - -/** - \ingroup CMSIS_core_register - \defgroup CMSIS_SCB System Control Block (SCB) - \brief Type definitions for the System Control Block Registers - @{ - */ - -/** - \brief Structure type to access the System Control Block (SCB). - */ -typedef struct -{ - __IM uint32_t CPUID; /*!< Offset: 0x000 (R/ ) CPUID Base Register */ - __IOM uint32_t ICSR; /*!< Offset: 0x004 (R/W) Interrupt Control and State Register */ - __IOM uint32_t VTOR; /*!< Offset: 0x008 (R/W) Vector Table Offset Register */ - __IOM uint32_t AIRCR; /*!< Offset: 0x00C (R/W) Application Interrupt and Reset Control Register */ - __IOM uint32_t SCR; /*!< Offset: 0x010 (R/W) System Control Register */ - __IOM uint32_t CCR; /*!< Offset: 0x014 (R/W) Configuration Control Register */ - __IOM uint8_t SHP[12U]; /*!< Offset: 0x018 (R/W) System Handlers Priority Registers (4-7, 8-11, 12-15) */ - __IOM uint32_t SHCSR; /*!< Offset: 0x024 (R/W) System Handler Control and State Register */ - __IOM uint32_t CFSR; /*!< Offset: 0x028 (R/W) Configurable Fault Status Register */ - __IOM uint32_t HFSR; /*!< Offset: 0x02C (R/W) HardFault Status Register */ - __IOM uint32_t DFSR; /*!< Offset: 0x030 (R/W) Debug Fault Status Register */ - __IOM uint32_t MMFAR; /*!< Offset: 0x034 (R/W) MemManage Fault Address Register */ - __IOM uint32_t BFAR; /*!< Offset: 0x038 (R/W) BusFault Address Register */ - __IOM uint32_t AFSR; /*!< Offset: 0x03C (R/W) Auxiliary Fault Status Register */ - __IM uint32_t PFR[2U]; /*!< Offset: 0x040 (R/ ) Processor Feature Register */ - __IM uint32_t DFR; /*!< Offset: 0x048 (R/ ) Debug Feature Register */ - __IM uint32_t ADR; /*!< Offset: 0x04C (R/ ) Auxiliary Feature Register */ - __IM uint32_t MMFR[4U]; /*!< Offset: 0x050 (R/ ) Memory Model Feature Register */ - __IM uint32_t ISAR[5U]; /*!< Offset: 0x060 (R/ ) Instruction Set Attributes Register */ - uint32_t RESERVED0[5U]; - __IOM uint32_t CPACR; /*!< Offset: 0x088 (R/W) Coprocessor Access Control Register */ -} SCB_Type; - -/* SCB CPUID Register Definitions */ -#define SCB_CPUID_IMPLEMENTER_Pos 24U /*!< SCB CPUID: IMPLEMENTER Position */ -#define SCB_CPUID_IMPLEMENTER_Msk (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos) /*!< SCB CPUID: IMPLEMENTER Mask */ - -#define SCB_CPUID_VARIANT_Pos 20U /*!< SCB CPUID: VARIANT Position */ -#define SCB_CPUID_VARIANT_Msk (0xFUL << SCB_CPUID_VARIANT_Pos) /*!< SCB CPUID: VARIANT Mask */ - -#define SCB_CPUID_ARCHITECTURE_Pos 16U /*!< SCB CPUID: ARCHITECTURE Position */ -#define SCB_CPUID_ARCHITECTURE_Msk (0xFUL << SCB_CPUID_ARCHITECTURE_Pos) /*!< SCB CPUID: ARCHITECTURE Mask */ - -#define SCB_CPUID_PARTNO_Pos 4U /*!< SCB CPUID: PARTNO Position */ -#define SCB_CPUID_PARTNO_Msk (0xFFFUL << SCB_CPUID_PARTNO_Pos) /*!< SCB CPUID: PARTNO Mask */ - -#define SCB_CPUID_REVISION_Pos 0U /*!< SCB CPUID: REVISION Position */ -#define SCB_CPUID_REVISION_Msk (0xFUL /*<< SCB_CPUID_REVISION_Pos*/) /*!< SCB CPUID: REVISION Mask */ - -/* SCB Interrupt Control State Register Definitions */ -#define SCB_ICSR_NMIPENDSET_Pos 31U /*!< SCB ICSR: NMIPENDSET Position */ -#define SCB_ICSR_NMIPENDSET_Msk (1UL << SCB_ICSR_NMIPENDSET_Pos) /*!< SCB ICSR: NMIPENDSET Mask */ - -#define SCB_ICSR_PENDSVSET_Pos 28U /*!< SCB ICSR: PENDSVSET Position */ -#define SCB_ICSR_PENDSVSET_Msk (1UL << SCB_ICSR_PENDSVSET_Pos) /*!< SCB ICSR: PENDSVSET Mask */ - -#define SCB_ICSR_PENDSVCLR_Pos 27U /*!< SCB ICSR: PENDSVCLR Position */ -#define SCB_ICSR_PENDSVCLR_Msk (1UL << SCB_ICSR_PENDSVCLR_Pos) /*!< SCB ICSR: PENDSVCLR Mask */ - -#define SCB_ICSR_PENDSTSET_Pos 26U /*!< SCB ICSR: PENDSTSET Position */ -#define SCB_ICSR_PENDSTSET_Msk (1UL << SCB_ICSR_PENDSTSET_Pos) /*!< SCB ICSR: PENDSTSET Mask */ - -#define SCB_ICSR_PENDSTCLR_Pos 25U /*!< SCB ICSR: PENDSTCLR Position */ -#define SCB_ICSR_PENDSTCLR_Msk (1UL << SCB_ICSR_PENDSTCLR_Pos) /*!< SCB ICSR: PENDSTCLR Mask */ - -#define SCB_ICSR_ISRPREEMPT_Pos 23U /*!< SCB ICSR: ISRPREEMPT Position */ -#define SCB_ICSR_ISRPREEMPT_Msk (1UL << SCB_ICSR_ISRPREEMPT_Pos) /*!< SCB ICSR: ISRPREEMPT Mask */ - -#define SCB_ICSR_ISRPENDING_Pos 22U /*!< SCB ICSR: ISRPENDING Position */ -#define SCB_ICSR_ISRPENDING_Msk (1UL << SCB_ICSR_ISRPENDING_Pos) /*!< SCB ICSR: ISRPENDING Mask */ - -#define SCB_ICSR_VECTPENDING_Pos 12U /*!< SCB ICSR: VECTPENDING Position */ -#define SCB_ICSR_VECTPENDING_Msk (0x1FFUL << SCB_ICSR_VECTPENDING_Pos) /*!< SCB ICSR: VECTPENDING Mask */ - -#define SCB_ICSR_RETTOBASE_Pos 11U /*!< SCB ICSR: RETTOBASE Position */ -#define SCB_ICSR_RETTOBASE_Msk (1UL << SCB_ICSR_RETTOBASE_Pos) /*!< SCB ICSR: RETTOBASE Mask */ - -#define SCB_ICSR_VECTACTIVE_Pos 0U /*!< SCB ICSR: VECTACTIVE Position */ -#define SCB_ICSR_VECTACTIVE_Msk (0x1FFUL /*<< SCB_ICSR_VECTACTIVE_Pos*/) /*!< SCB ICSR: VECTACTIVE Mask */ - -/* SCB Vector Table Offset Register Definitions */ -#if defined (__CM3_REV) && (__CM3_REV < 0x0201U) /* core r2p1 */ -#define SCB_VTOR_TBLBASE_Pos 29U /*!< SCB VTOR: TBLBASE Position */ -#define SCB_VTOR_TBLBASE_Msk (1UL << SCB_VTOR_TBLBASE_Pos) /*!< SCB VTOR: TBLBASE Mask */ - -#define SCB_VTOR_TBLOFF_Pos 7U /*!< SCB VTOR: TBLOFF Position */ -#define SCB_VTOR_TBLOFF_Msk (0x3FFFFFUL << SCB_VTOR_TBLOFF_Pos) /*!< SCB VTOR: TBLOFF Mask */ -#else -#define SCB_VTOR_TBLOFF_Pos 7U /*!< SCB VTOR: TBLOFF Position */ -#define SCB_VTOR_TBLOFF_Msk (0x1FFFFFFUL << SCB_VTOR_TBLOFF_Pos) /*!< SCB VTOR: TBLOFF Mask */ -#endif - -/* SCB Application Interrupt and Reset Control Register Definitions */ -#define SCB_AIRCR_VECTKEY_Pos 16U /*!< SCB AIRCR: VECTKEY Position */ -#define SCB_AIRCR_VECTKEY_Msk (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos) /*!< SCB AIRCR: VECTKEY Mask */ - -#define SCB_AIRCR_VECTKEYSTAT_Pos 16U /*!< SCB AIRCR: VECTKEYSTAT Position */ -#define SCB_AIRCR_VECTKEYSTAT_Msk (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos) /*!< SCB AIRCR: VECTKEYSTAT Mask */ - -#define SCB_AIRCR_ENDIANESS_Pos 15U /*!< SCB AIRCR: ENDIANESS Position */ -#define SCB_AIRCR_ENDIANESS_Msk (1UL << SCB_AIRCR_ENDIANESS_Pos) /*!< SCB AIRCR: ENDIANESS Mask */ - -#define SCB_AIRCR_PRIGROUP_Pos 8U /*!< SCB AIRCR: PRIGROUP Position */ -#define SCB_AIRCR_PRIGROUP_Msk (7UL << SCB_AIRCR_PRIGROUP_Pos) /*!< SCB AIRCR: PRIGROUP Mask */ - -#define SCB_AIRCR_SYSRESETREQ_Pos 2U /*!< SCB AIRCR: SYSRESETREQ Position */ -#define SCB_AIRCR_SYSRESETREQ_Msk (1UL << SCB_AIRCR_SYSRESETREQ_Pos) /*!< SCB AIRCR: SYSRESETREQ Mask */ - -#define SCB_AIRCR_VECTCLRACTIVE_Pos 1U /*!< SCB AIRCR: VECTCLRACTIVE Position */ -#define SCB_AIRCR_VECTCLRACTIVE_Msk (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos) /*!< SCB AIRCR: VECTCLRACTIVE Mask */ - -#define SCB_AIRCR_VECTRESET_Pos 0U /*!< SCB AIRCR: VECTRESET Position */ -#define SCB_AIRCR_VECTRESET_Msk (1UL /*<< SCB_AIRCR_VECTRESET_Pos*/) /*!< SCB AIRCR: VECTRESET Mask */ - -/* SCB System Control Register Definitions */ -#define SCB_SCR_SEVONPEND_Pos 4U /*!< SCB SCR: SEVONPEND Position */ -#define SCB_SCR_SEVONPEND_Msk (1UL << SCB_SCR_SEVONPEND_Pos) /*!< SCB SCR: SEVONPEND Mask */ - -#define SCB_SCR_SLEEPDEEP_Pos 2U /*!< SCB SCR: SLEEPDEEP Position */ -#define SCB_SCR_SLEEPDEEP_Msk (1UL << SCB_SCR_SLEEPDEEP_Pos) /*!< SCB SCR: SLEEPDEEP Mask */ - -#define SCB_SCR_SLEEPONEXIT_Pos 1U /*!< SCB SCR: SLEEPONEXIT Position */ -#define SCB_SCR_SLEEPONEXIT_Msk (1UL << SCB_SCR_SLEEPONEXIT_Pos) /*!< SCB SCR: SLEEPONEXIT Mask */ - -/* SCB Configuration Control Register Definitions */ -#define SCB_CCR_STKALIGN_Pos 9U /*!< SCB CCR: STKALIGN Position */ -#define SCB_CCR_STKALIGN_Msk (1UL << SCB_CCR_STKALIGN_Pos) /*!< SCB CCR: STKALIGN Mask */ - -#define SCB_CCR_BFHFNMIGN_Pos 8U /*!< SCB CCR: BFHFNMIGN Position */ -#define SCB_CCR_BFHFNMIGN_Msk (1UL << SCB_CCR_BFHFNMIGN_Pos) /*!< SCB CCR: BFHFNMIGN Mask */ - -#define SCB_CCR_DIV_0_TRP_Pos 4U /*!< SCB CCR: DIV_0_TRP Position */ -#define SCB_CCR_DIV_0_TRP_Msk (1UL << SCB_CCR_DIV_0_TRP_Pos) /*!< SCB CCR: DIV_0_TRP Mask */ - -#define SCB_CCR_UNALIGN_TRP_Pos 3U /*!< SCB CCR: UNALIGN_TRP Position */ -#define SCB_CCR_UNALIGN_TRP_Msk (1UL << SCB_CCR_UNALIGN_TRP_Pos) /*!< SCB CCR: UNALIGN_TRP Mask */ - -#define SCB_CCR_USERSETMPEND_Pos 1U /*!< SCB CCR: USERSETMPEND Position */ -#define SCB_CCR_USERSETMPEND_Msk (1UL << SCB_CCR_USERSETMPEND_Pos) /*!< SCB CCR: USERSETMPEND Mask */ - -#define SCB_CCR_NONBASETHRDENA_Pos 0U /*!< SCB CCR: NONBASETHRDENA Position */ -#define SCB_CCR_NONBASETHRDENA_Msk (1UL /*<< SCB_CCR_NONBASETHRDENA_Pos*/) /*!< SCB CCR: NONBASETHRDENA Mask */ - -/* SCB System Handler Control and State Register Definitions */ -#define SCB_SHCSR_USGFAULTENA_Pos 18U /*!< SCB SHCSR: USGFAULTENA Position */ -#define SCB_SHCSR_USGFAULTENA_Msk (1UL << SCB_SHCSR_USGFAULTENA_Pos) /*!< SCB SHCSR: USGFAULTENA Mask */ - -#define SCB_SHCSR_BUSFAULTENA_Pos 17U /*!< SCB SHCSR: BUSFAULTENA Position */ -#define SCB_SHCSR_BUSFAULTENA_Msk (1UL << SCB_SHCSR_BUSFAULTENA_Pos) /*!< SCB SHCSR: BUSFAULTENA Mask */ - -#define SCB_SHCSR_MEMFAULTENA_Pos 16U /*!< SCB SHCSR: MEMFAULTENA Position */ -#define SCB_SHCSR_MEMFAULTENA_Msk (1UL << SCB_SHCSR_MEMFAULTENA_Pos) /*!< SCB SHCSR: MEMFAULTENA Mask */ - -#define SCB_SHCSR_SVCALLPENDED_Pos 15U /*!< SCB SHCSR: SVCALLPENDED Position */ -#define SCB_SHCSR_SVCALLPENDED_Msk (1UL << SCB_SHCSR_SVCALLPENDED_Pos) /*!< SCB SHCSR: SVCALLPENDED Mask */ - -#define SCB_SHCSR_BUSFAULTPENDED_Pos 14U /*!< SCB SHCSR: BUSFAULTPENDED Position */ -#define SCB_SHCSR_BUSFAULTPENDED_Msk (1UL << SCB_SHCSR_BUSFAULTPENDED_Pos) /*!< SCB SHCSR: BUSFAULTPENDED Mask */ - -#define SCB_SHCSR_MEMFAULTPENDED_Pos 13U /*!< SCB SHCSR: MEMFAULTPENDED Position */ -#define SCB_SHCSR_MEMFAULTPENDED_Msk (1UL << SCB_SHCSR_MEMFAULTPENDED_Pos) /*!< SCB SHCSR: MEMFAULTPENDED Mask */ - -#define SCB_SHCSR_USGFAULTPENDED_Pos 12U /*!< SCB SHCSR: USGFAULTPENDED Position */ -#define SCB_SHCSR_USGFAULTPENDED_Msk (1UL << SCB_SHCSR_USGFAULTPENDED_Pos) /*!< SCB SHCSR: USGFAULTPENDED Mask */ - -#define SCB_SHCSR_SYSTICKACT_Pos 11U /*!< SCB SHCSR: SYSTICKACT Position */ -#define SCB_SHCSR_SYSTICKACT_Msk (1UL << SCB_SHCSR_SYSTICKACT_Pos) /*!< SCB SHCSR: SYSTICKACT Mask */ - -#define SCB_SHCSR_PENDSVACT_Pos 10U /*!< SCB SHCSR: PENDSVACT Position */ -#define SCB_SHCSR_PENDSVACT_Msk (1UL << SCB_SHCSR_PENDSVACT_Pos) /*!< SCB SHCSR: PENDSVACT Mask */ - -#define SCB_SHCSR_MONITORACT_Pos 8U /*!< SCB SHCSR: MONITORACT Position */ -#define SCB_SHCSR_MONITORACT_Msk (1UL << SCB_SHCSR_MONITORACT_Pos) /*!< SCB SHCSR: MONITORACT Mask */ - -#define SCB_SHCSR_SVCALLACT_Pos 7U /*!< SCB SHCSR: SVCALLACT Position */ -#define SCB_SHCSR_SVCALLACT_Msk (1UL << SCB_SHCSR_SVCALLACT_Pos) /*!< SCB SHCSR: SVCALLACT Mask */ - -#define SCB_SHCSR_USGFAULTACT_Pos 3U /*!< SCB SHCSR: USGFAULTACT Position */ -#define SCB_SHCSR_USGFAULTACT_Msk (1UL << SCB_SHCSR_USGFAULTACT_Pos) /*!< SCB SHCSR: USGFAULTACT Mask */ - -#define SCB_SHCSR_BUSFAULTACT_Pos 1U /*!< SCB SHCSR: BUSFAULTACT Position */ -#define SCB_SHCSR_BUSFAULTACT_Msk (1UL << SCB_SHCSR_BUSFAULTACT_Pos) /*!< SCB SHCSR: BUSFAULTACT Mask */ - -#define SCB_SHCSR_MEMFAULTACT_Pos 0U /*!< SCB SHCSR: MEMFAULTACT Position */ -#define SCB_SHCSR_MEMFAULTACT_Msk (1UL /*<< SCB_SHCSR_MEMFAULTACT_Pos*/) /*!< SCB SHCSR: MEMFAULTACT Mask */ - -/* SCB Configurable Fault Status Register Definitions */ -#define SCB_CFSR_USGFAULTSR_Pos 16U /*!< SCB CFSR: Usage Fault Status Register Position */ -#define SCB_CFSR_USGFAULTSR_Msk (0xFFFFUL << SCB_CFSR_USGFAULTSR_Pos) /*!< SCB CFSR: Usage Fault Status Register Mask */ - -#define SCB_CFSR_BUSFAULTSR_Pos 8U /*!< SCB CFSR: Bus Fault Status Register Position */ -#define SCB_CFSR_BUSFAULTSR_Msk (0xFFUL << SCB_CFSR_BUSFAULTSR_Pos) /*!< SCB CFSR: Bus Fault Status Register Mask */ - -#define SCB_CFSR_MEMFAULTSR_Pos 0U /*!< SCB CFSR: Memory Manage Fault Status Register Position */ -#define SCB_CFSR_MEMFAULTSR_Msk (0xFFUL /*<< SCB_CFSR_MEMFAULTSR_Pos*/) /*!< SCB CFSR: Memory Manage Fault Status Register Mask */ - -/* MemManage Fault Status Register (part of SCB Configurable Fault Status Register) */ -#define SCB_CFSR_MMARVALID_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 7U) /*!< SCB CFSR (MMFSR): MMARVALID Position */ -#define SCB_CFSR_MMARVALID_Msk (1UL << SCB_CFSR_MMARVALID_Pos) /*!< SCB CFSR (MMFSR): MMARVALID Mask */ - -#define SCB_CFSR_MSTKERR_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 4U) /*!< SCB CFSR (MMFSR): MSTKERR Position */ -#define SCB_CFSR_MSTKERR_Msk (1UL << SCB_CFSR_MSTKERR_Pos) /*!< SCB CFSR (MMFSR): MSTKERR Mask */ - -#define SCB_CFSR_MUNSTKERR_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 3U) /*!< SCB CFSR (MMFSR): MUNSTKERR Position */ -#define SCB_CFSR_MUNSTKERR_Msk (1UL << SCB_CFSR_MUNSTKERR_Pos) /*!< SCB CFSR (MMFSR): MUNSTKERR Mask */ - -#define SCB_CFSR_DACCVIOL_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 1U) /*!< SCB CFSR (MMFSR): DACCVIOL Position */ -#define SCB_CFSR_DACCVIOL_Msk (1UL << SCB_CFSR_DACCVIOL_Pos) /*!< SCB CFSR (MMFSR): DACCVIOL Mask */ - -#define SCB_CFSR_IACCVIOL_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 0U) /*!< SCB CFSR (MMFSR): IACCVIOL Position */ -#define SCB_CFSR_IACCVIOL_Msk (1UL /*<< SCB_CFSR_IACCVIOL_Pos*/) /*!< SCB CFSR (MMFSR): IACCVIOL Mask */ - -/* BusFault Status Register (part of SCB Configurable Fault Status Register) */ -#define SCB_CFSR_BFARVALID_Pos (SCB_CFSR_BUSFAULTSR_Pos + 7U) /*!< SCB CFSR (BFSR): BFARVALID Position */ -#define SCB_CFSR_BFARVALID_Msk (1UL << SCB_CFSR_BFARVALID_Pos) /*!< SCB CFSR (BFSR): BFARVALID Mask */ - -#define SCB_CFSR_STKERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 4U) /*!< SCB CFSR (BFSR): STKERR Position */ -#define SCB_CFSR_STKERR_Msk (1UL << SCB_CFSR_STKERR_Pos) /*!< SCB CFSR (BFSR): STKERR Mask */ - -#define SCB_CFSR_UNSTKERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 3U) /*!< SCB CFSR (BFSR): UNSTKERR Position */ -#define SCB_CFSR_UNSTKERR_Msk (1UL << SCB_CFSR_UNSTKERR_Pos) /*!< SCB CFSR (BFSR): UNSTKERR Mask */ - -#define SCB_CFSR_IMPRECISERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 2U) /*!< SCB CFSR (BFSR): IMPRECISERR Position */ -#define SCB_CFSR_IMPRECISERR_Msk (1UL << SCB_CFSR_IMPRECISERR_Pos) /*!< SCB CFSR (BFSR): IMPRECISERR Mask */ - -#define SCB_CFSR_PRECISERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 1U) /*!< SCB CFSR (BFSR): PRECISERR Position */ -#define SCB_CFSR_PRECISERR_Msk (1UL << SCB_CFSR_PRECISERR_Pos) /*!< SCB CFSR (BFSR): PRECISERR Mask */ - -#define SCB_CFSR_IBUSERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 0U) /*!< SCB CFSR (BFSR): IBUSERR Position */ -#define SCB_CFSR_IBUSERR_Msk (1UL << SCB_CFSR_IBUSERR_Pos) /*!< SCB CFSR (BFSR): IBUSERR Mask */ - -/* UsageFault Status Register (part of SCB Configurable Fault Status Register) */ -#define SCB_CFSR_DIVBYZERO_Pos (SCB_CFSR_USGFAULTSR_Pos + 9U) /*!< SCB CFSR (UFSR): DIVBYZERO Position */ -#define SCB_CFSR_DIVBYZERO_Msk (1UL << SCB_CFSR_DIVBYZERO_Pos) /*!< SCB CFSR (UFSR): DIVBYZERO Mask */ - -#define SCB_CFSR_UNALIGNED_Pos (SCB_CFSR_USGFAULTSR_Pos + 8U) /*!< SCB CFSR (UFSR): UNALIGNED Position */ -#define SCB_CFSR_UNALIGNED_Msk (1UL << SCB_CFSR_UNALIGNED_Pos) /*!< SCB CFSR (UFSR): UNALIGNED Mask */ - -#define SCB_CFSR_NOCP_Pos (SCB_CFSR_USGFAULTSR_Pos + 3U) /*!< SCB CFSR (UFSR): NOCP Position */ -#define SCB_CFSR_NOCP_Msk (1UL << SCB_CFSR_NOCP_Pos) /*!< SCB CFSR (UFSR): NOCP Mask */ - -#define SCB_CFSR_INVPC_Pos (SCB_CFSR_USGFAULTSR_Pos + 2U) /*!< SCB CFSR (UFSR): INVPC Position */ -#define SCB_CFSR_INVPC_Msk (1UL << SCB_CFSR_INVPC_Pos) /*!< SCB CFSR (UFSR): INVPC Mask */ - -#define SCB_CFSR_INVSTATE_Pos (SCB_CFSR_USGFAULTSR_Pos + 1U) /*!< SCB CFSR (UFSR): INVSTATE Position */ -#define SCB_CFSR_INVSTATE_Msk (1UL << SCB_CFSR_INVSTATE_Pos) /*!< SCB CFSR (UFSR): INVSTATE Mask */ - -#define SCB_CFSR_UNDEFINSTR_Pos (SCB_CFSR_USGFAULTSR_Pos + 0U) /*!< SCB CFSR (UFSR): UNDEFINSTR Position */ -#define SCB_CFSR_UNDEFINSTR_Msk (1UL << SCB_CFSR_UNDEFINSTR_Pos) /*!< SCB CFSR (UFSR): UNDEFINSTR Mask */ - -/* SCB Hard Fault Status Register Definitions */ -#define SCB_HFSR_DEBUGEVT_Pos 31U /*!< SCB HFSR: DEBUGEVT Position */ -#define SCB_HFSR_DEBUGEVT_Msk (1UL << SCB_HFSR_DEBUGEVT_Pos) /*!< SCB HFSR: DEBUGEVT Mask */ - -#define SCB_HFSR_FORCED_Pos 30U /*!< SCB HFSR: FORCED Position */ -#define SCB_HFSR_FORCED_Msk (1UL << SCB_HFSR_FORCED_Pos) /*!< SCB HFSR: FORCED Mask */ - -#define SCB_HFSR_VECTTBL_Pos 1U /*!< SCB HFSR: VECTTBL Position */ -#define SCB_HFSR_VECTTBL_Msk (1UL << SCB_HFSR_VECTTBL_Pos) /*!< SCB HFSR: VECTTBL Mask */ - -/* SCB Debug Fault Status Register Definitions */ -#define SCB_DFSR_EXTERNAL_Pos 4U /*!< SCB DFSR: EXTERNAL Position */ -#define SCB_DFSR_EXTERNAL_Msk (1UL << SCB_DFSR_EXTERNAL_Pos) /*!< SCB DFSR: EXTERNAL Mask */ - -#define SCB_DFSR_VCATCH_Pos 3U /*!< SCB DFSR: VCATCH Position */ -#define SCB_DFSR_VCATCH_Msk (1UL << SCB_DFSR_VCATCH_Pos) /*!< SCB DFSR: VCATCH Mask */ - -#define SCB_DFSR_DWTTRAP_Pos 2U /*!< SCB DFSR: DWTTRAP Position */ -#define SCB_DFSR_DWTTRAP_Msk (1UL << SCB_DFSR_DWTTRAP_Pos) /*!< SCB DFSR: DWTTRAP Mask */ - -#define SCB_DFSR_BKPT_Pos 1U /*!< SCB DFSR: BKPT Position */ -#define SCB_DFSR_BKPT_Msk (1UL << SCB_DFSR_BKPT_Pos) /*!< SCB DFSR: BKPT Mask */ - -#define SCB_DFSR_HALTED_Pos 0U /*!< SCB DFSR: HALTED Position */ -#define SCB_DFSR_HALTED_Msk (1UL /*<< SCB_DFSR_HALTED_Pos*/) /*!< SCB DFSR: HALTED Mask */ - -/*@} end of group CMSIS_SCB */ - - -/** - \ingroup CMSIS_core_register - \defgroup CMSIS_SCnSCB System Controls not in SCB (SCnSCB) - \brief Type definitions for the System Control and ID Register not in the SCB - @{ - */ - -/** - \brief Structure type to access the System Control and ID Register not in the SCB. - */ -typedef struct -{ - uint32_t RESERVED0[1U]; - __IM uint32_t ICTR; /*!< Offset: 0x004 (R/ ) Interrupt Controller Type Register */ -#if defined (__CM3_REV) && (__CM3_REV >= 0x200U) - __IOM uint32_t ACTLR; /*!< Offset: 0x008 (R/W) Auxiliary Control Register */ -#else - uint32_t RESERVED1[1U]; -#endif -} SCnSCB_Type; - -/* Interrupt Controller Type Register Definitions */ -#define SCnSCB_ICTR_INTLINESNUM_Pos 0U /*!< ICTR: INTLINESNUM Position */ -#define SCnSCB_ICTR_INTLINESNUM_Msk (0xFUL /*<< SCnSCB_ICTR_INTLINESNUM_Pos*/) /*!< ICTR: INTLINESNUM Mask */ - -/* Auxiliary Control Register Definitions */ - -#define SCnSCB_ACTLR_DISFOLD_Pos 2U /*!< ACTLR: DISFOLD Position */ -#define SCnSCB_ACTLR_DISFOLD_Msk (1UL << SCnSCB_ACTLR_DISFOLD_Pos) /*!< ACTLR: DISFOLD Mask */ - -#define SCnSCB_ACTLR_DISDEFWBUF_Pos 1U /*!< ACTLR: DISDEFWBUF Position */ -#define SCnSCB_ACTLR_DISDEFWBUF_Msk (1UL << SCnSCB_ACTLR_DISDEFWBUF_Pos) /*!< ACTLR: DISDEFWBUF Mask */ - -#define SCnSCB_ACTLR_DISMCYCINT_Pos 0U /*!< ACTLR: DISMCYCINT Position */ -#define SCnSCB_ACTLR_DISMCYCINT_Msk (1UL /*<< SCnSCB_ACTLR_DISMCYCINT_Pos*/) /*!< ACTLR: DISMCYCINT Mask */ - -/*@} end of group CMSIS_SCnotSCB */ - - -/** - \ingroup CMSIS_core_register - \defgroup CMSIS_SysTick System Tick Timer (SysTick) - \brief Type definitions for the System Timer Registers. - @{ - */ - -/** - \brief Structure type to access the System Timer (SysTick). - */ -typedef struct -{ - __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) SysTick Control and Status Register */ - __IOM uint32_t LOAD; /*!< Offset: 0x004 (R/W) SysTick Reload Value Register */ - __IOM uint32_t VAL; /*!< Offset: 0x008 (R/W) SysTick Current Value Register */ - __IM uint32_t CALIB; /*!< Offset: 0x00C (R/ ) SysTick Calibration Register */ -} SysTick_Type; - -/* SysTick Control / Status Register Definitions */ -#define SysTick_CTRL_COUNTFLAG_Pos 16U /*!< SysTick CTRL: COUNTFLAG Position */ -#define SysTick_CTRL_COUNTFLAG_Msk (1UL << SysTick_CTRL_COUNTFLAG_Pos) /*!< SysTick CTRL: COUNTFLAG Mask */ - -#define SysTick_CTRL_CLKSOURCE_Pos 2U /*!< SysTick CTRL: CLKSOURCE Position */ -#define SysTick_CTRL_CLKSOURCE_Msk (1UL << SysTick_CTRL_CLKSOURCE_Pos) /*!< SysTick CTRL: CLKSOURCE Mask */ - -#define SysTick_CTRL_TICKINT_Pos 1U /*!< SysTick CTRL: TICKINT Position */ -#define SysTick_CTRL_TICKINT_Msk (1UL << SysTick_CTRL_TICKINT_Pos) /*!< SysTick CTRL: TICKINT Mask */ - -#define SysTick_CTRL_ENABLE_Pos 0U /*!< SysTick CTRL: ENABLE Position */ -#define SysTick_CTRL_ENABLE_Msk (1UL /*<< SysTick_CTRL_ENABLE_Pos*/) /*!< SysTick CTRL: ENABLE Mask */ - -/* SysTick Reload Register Definitions */ -#define SysTick_LOAD_RELOAD_Pos 0U /*!< SysTick LOAD: RELOAD Position */ -#define SysTick_LOAD_RELOAD_Msk (0xFFFFFFUL /*<< SysTick_LOAD_RELOAD_Pos*/) /*!< SysTick LOAD: RELOAD Mask */ - -/* SysTick Current Register Definitions */ -#define SysTick_VAL_CURRENT_Pos 0U /*!< SysTick VAL: CURRENT Position */ -#define SysTick_VAL_CURRENT_Msk (0xFFFFFFUL /*<< SysTick_VAL_CURRENT_Pos*/) /*!< SysTick VAL: CURRENT Mask */ - -/* SysTick Calibration Register Definitions */ -#define SysTick_CALIB_NOREF_Pos 31U /*!< SysTick CALIB: NOREF Position */ -#define SysTick_CALIB_NOREF_Msk (1UL << SysTick_CALIB_NOREF_Pos) /*!< SysTick CALIB: NOREF Mask */ - -#define SysTick_CALIB_SKEW_Pos 30U /*!< SysTick CALIB: SKEW Position */ -#define SysTick_CALIB_SKEW_Msk (1UL << SysTick_CALIB_SKEW_Pos) /*!< SysTick CALIB: SKEW Mask */ - -#define SysTick_CALIB_TENMS_Pos 0U /*!< SysTick CALIB: TENMS Position */ -#define SysTick_CALIB_TENMS_Msk (0xFFFFFFUL /*<< SysTick_CALIB_TENMS_Pos*/) /*!< SysTick CALIB: TENMS Mask */ - -/*@} end of group CMSIS_SysTick */ - - -/** - \ingroup CMSIS_core_register - \defgroup CMSIS_ITM Instrumentation Trace Macrocell (ITM) - \brief Type definitions for the Instrumentation Trace Macrocell (ITM) - @{ - */ - -/** - \brief Structure type to access the Instrumentation Trace Macrocell Register (ITM). - */ -typedef struct -{ - __OM union - { - __OM uint8_t u8; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 8-bit */ - __OM uint16_t u16; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 16-bit */ - __OM uint32_t u32; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 32-bit */ - } PORT [32U]; /*!< Offset: 0x000 ( /W) ITM Stimulus Port Registers */ - uint32_t RESERVED0[864U]; - __IOM uint32_t TER; /*!< Offset: 0xE00 (R/W) ITM Trace Enable Register */ - uint32_t RESERVED1[15U]; - __IOM uint32_t TPR; /*!< Offset: 0xE40 (R/W) ITM Trace Privilege Register */ - uint32_t RESERVED2[15U]; - __IOM uint32_t TCR; /*!< Offset: 0xE80 (R/W) ITM Trace Control Register */ - uint32_t RESERVED3[29U]; - __OM uint32_t IWR; /*!< Offset: 0xEF8 ( /W) ITM Integration Write Register */ - __IM uint32_t IRR; /*!< Offset: 0xEFC (R/ ) ITM Integration Read Register */ - __IOM uint32_t IMCR; /*!< Offset: 0xF00 (R/W) ITM Integration Mode Control Register */ - uint32_t RESERVED4[43U]; - __OM uint32_t LAR; /*!< Offset: 0xFB0 ( /W) ITM Lock Access Register */ - __IM uint32_t LSR; /*!< Offset: 0xFB4 (R/ ) ITM Lock Status Register */ - uint32_t RESERVED5[6U]; - __IM uint32_t PID4; /*!< Offset: 0xFD0 (R/ ) ITM Peripheral Identification Register #4 */ - __IM uint32_t PID5; /*!< Offset: 0xFD4 (R/ ) ITM Peripheral Identification Register #5 */ - __IM uint32_t PID6; /*!< Offset: 0xFD8 (R/ ) ITM Peripheral Identification Register #6 */ - __IM uint32_t PID7; /*!< Offset: 0xFDC (R/ ) ITM Peripheral Identification Register #7 */ - __IM uint32_t PID0; /*!< Offset: 0xFE0 (R/ ) ITM Peripheral Identification Register #0 */ - __IM uint32_t PID1; /*!< Offset: 0xFE4 (R/ ) ITM Peripheral Identification Register #1 */ - __IM uint32_t PID2; /*!< Offset: 0xFE8 (R/ ) ITM Peripheral Identification Register #2 */ - __IM uint32_t PID3; /*!< Offset: 0xFEC (R/ ) ITM Peripheral Identification Register #3 */ - __IM uint32_t CID0; /*!< Offset: 0xFF0 (R/ ) ITM Component Identification Register #0 */ - __IM uint32_t CID1; /*!< Offset: 0xFF4 (R/ ) ITM Component Identification Register #1 */ - __IM uint32_t CID2; /*!< Offset: 0xFF8 (R/ ) ITM Component Identification Register #2 */ - __IM uint32_t CID3; /*!< Offset: 0xFFC (R/ ) ITM Component Identification Register #3 */ -} ITM_Type; - -/* ITM Trace Privilege Register Definitions */ -#define ITM_TPR_PRIVMASK_Pos 0U /*!< ITM TPR: PRIVMASK Position */ -#define ITM_TPR_PRIVMASK_Msk (0xFFFFFFFFUL /*<< ITM_TPR_PRIVMASK_Pos*/) /*!< ITM TPR: PRIVMASK Mask */ - -/* ITM Trace Control Register Definitions */ -#define ITM_TCR_BUSY_Pos 23U /*!< ITM TCR: BUSY Position */ -#define ITM_TCR_BUSY_Msk (1UL << ITM_TCR_BUSY_Pos) /*!< ITM TCR: BUSY Mask */ - -#define ITM_TCR_TraceBusID_Pos 16U /*!< ITM TCR: ATBID Position */ -#define ITM_TCR_TraceBusID_Msk (0x7FUL << ITM_TCR_TraceBusID_Pos) /*!< ITM TCR: ATBID Mask */ - -#define ITM_TCR_GTSFREQ_Pos 10U /*!< ITM TCR: Global timestamp frequency Position */ -#define ITM_TCR_GTSFREQ_Msk (3UL << ITM_TCR_GTSFREQ_Pos) /*!< ITM TCR: Global timestamp frequency Mask */ - -#define ITM_TCR_TSPrescale_Pos 8U /*!< ITM TCR: TSPrescale Position */ -#define ITM_TCR_TSPrescale_Msk (3UL << ITM_TCR_TSPrescale_Pos) /*!< ITM TCR: TSPrescale Mask */ - -#define ITM_TCR_SWOENA_Pos 4U /*!< ITM TCR: SWOENA Position */ -#define ITM_TCR_SWOENA_Msk (1UL << ITM_TCR_SWOENA_Pos) /*!< ITM TCR: SWOENA Mask */ - -#define ITM_TCR_DWTENA_Pos 3U /*!< ITM TCR: DWTENA Position */ -#define ITM_TCR_DWTENA_Msk (1UL << ITM_TCR_DWTENA_Pos) /*!< ITM TCR: DWTENA Mask */ - -#define ITM_TCR_SYNCENA_Pos 2U /*!< ITM TCR: SYNCENA Position */ -#define ITM_TCR_SYNCENA_Msk (1UL << ITM_TCR_SYNCENA_Pos) /*!< ITM TCR: SYNCENA Mask */ - -#define ITM_TCR_TSENA_Pos 1U /*!< ITM TCR: TSENA Position */ -#define ITM_TCR_TSENA_Msk (1UL << ITM_TCR_TSENA_Pos) /*!< ITM TCR: TSENA Mask */ - -#define ITM_TCR_ITMENA_Pos 0U /*!< ITM TCR: ITM Enable bit Position */ -#define ITM_TCR_ITMENA_Msk (1UL /*<< ITM_TCR_ITMENA_Pos*/) /*!< ITM TCR: ITM Enable bit Mask */ - -/* ITM Integration Write Register Definitions */ -#define ITM_IWR_ATVALIDM_Pos 0U /*!< ITM IWR: ATVALIDM Position */ -#define ITM_IWR_ATVALIDM_Msk (1UL /*<< ITM_IWR_ATVALIDM_Pos*/) /*!< ITM IWR: ATVALIDM Mask */ - -/* ITM Integration Read Register Definitions */ -#define ITM_IRR_ATREADYM_Pos 0U /*!< ITM IRR: ATREADYM Position */ -#define ITM_IRR_ATREADYM_Msk (1UL /*<< ITM_IRR_ATREADYM_Pos*/) /*!< ITM IRR: ATREADYM Mask */ - -/* ITM Integration Mode Control Register Definitions */ -#define ITM_IMCR_INTEGRATION_Pos 0U /*!< ITM IMCR: INTEGRATION Position */ -#define ITM_IMCR_INTEGRATION_Msk (1UL /*<< ITM_IMCR_INTEGRATION_Pos*/) /*!< ITM IMCR: INTEGRATION Mask */ - -/* ITM Lock Status Register Definitions */ -#define ITM_LSR_ByteAcc_Pos 2U /*!< ITM LSR: ByteAcc Position */ -#define ITM_LSR_ByteAcc_Msk (1UL << ITM_LSR_ByteAcc_Pos) /*!< ITM LSR: ByteAcc Mask */ - -#define ITM_LSR_Access_Pos 1U /*!< ITM LSR: Access Position */ -#define ITM_LSR_Access_Msk (1UL << ITM_LSR_Access_Pos) /*!< ITM LSR: Access Mask */ - -#define ITM_LSR_Present_Pos 0U /*!< ITM LSR: Present Position */ -#define ITM_LSR_Present_Msk (1UL /*<< ITM_LSR_Present_Pos*/) /*!< ITM LSR: Present Mask */ - -/*@}*/ /* end of group CMSIS_ITM */ - - -/** - \ingroup CMSIS_core_register - \defgroup CMSIS_DWT Data Watchpoint and Trace (DWT) - \brief Type definitions for the Data Watchpoint and Trace (DWT) - @{ - */ - -/** - \brief Structure type to access the Data Watchpoint and Trace Register (DWT). - */ -typedef struct -{ - __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) Control Register */ - __IOM uint32_t CYCCNT; /*!< Offset: 0x004 (R/W) Cycle Count Register */ - __IOM uint32_t CPICNT; /*!< Offset: 0x008 (R/W) CPI Count Register */ - __IOM uint32_t EXCCNT; /*!< Offset: 0x00C (R/W) Exception Overhead Count Register */ - __IOM uint32_t SLEEPCNT; /*!< Offset: 0x010 (R/W) Sleep Count Register */ - __IOM uint32_t LSUCNT; /*!< Offset: 0x014 (R/W) LSU Count Register */ - __IOM uint32_t FOLDCNT; /*!< Offset: 0x018 (R/W) Folded-instruction Count Register */ - __IM uint32_t PCSR; /*!< Offset: 0x01C (R/ ) Program Counter Sample Register */ - __IOM uint32_t COMP0; /*!< Offset: 0x020 (R/W) Comparator Register 0 */ - __IOM uint32_t MASK0; /*!< Offset: 0x024 (R/W) Mask Register 0 */ - __IOM uint32_t FUNCTION0; /*!< Offset: 0x028 (R/W) Function Register 0 */ - uint32_t RESERVED0[1U]; - __IOM uint32_t COMP1; /*!< Offset: 0x030 (R/W) Comparator Register 1 */ - __IOM uint32_t MASK1; /*!< Offset: 0x034 (R/W) Mask Register 1 */ - __IOM uint32_t FUNCTION1; /*!< Offset: 0x038 (R/W) Function Register 1 */ - uint32_t RESERVED1[1U]; - __IOM uint32_t COMP2; /*!< Offset: 0x040 (R/W) Comparator Register 2 */ - __IOM uint32_t MASK2; /*!< Offset: 0x044 (R/W) Mask Register 2 */ - __IOM uint32_t FUNCTION2; /*!< Offset: 0x048 (R/W) Function Register 2 */ - uint32_t RESERVED2[1U]; - __IOM uint32_t COMP3; /*!< Offset: 0x050 (R/W) Comparator Register 3 */ - __IOM uint32_t MASK3; /*!< Offset: 0x054 (R/W) Mask Register 3 */ - __IOM uint32_t FUNCTION3; /*!< Offset: 0x058 (R/W) Function Register 3 */ -} DWT_Type; - -/* DWT Control Register Definitions */ -#define DWT_CTRL_NUMCOMP_Pos 28U /*!< DWT CTRL: NUMCOMP Position */ -#define DWT_CTRL_NUMCOMP_Msk (0xFUL << DWT_CTRL_NUMCOMP_Pos) /*!< DWT CTRL: NUMCOMP Mask */ - -#define DWT_CTRL_NOTRCPKT_Pos 27U /*!< DWT CTRL: NOTRCPKT Position */ -#define DWT_CTRL_NOTRCPKT_Msk (0x1UL << DWT_CTRL_NOTRCPKT_Pos) /*!< DWT CTRL: NOTRCPKT Mask */ - -#define DWT_CTRL_NOEXTTRIG_Pos 26U /*!< DWT CTRL: NOEXTTRIG Position */ -#define DWT_CTRL_NOEXTTRIG_Msk (0x1UL << DWT_CTRL_NOEXTTRIG_Pos) /*!< DWT CTRL: NOEXTTRIG Mask */ - -#define DWT_CTRL_NOCYCCNT_Pos 25U /*!< DWT CTRL: NOCYCCNT Position */ -#define DWT_CTRL_NOCYCCNT_Msk (0x1UL << DWT_CTRL_NOCYCCNT_Pos) /*!< DWT CTRL: NOCYCCNT Mask */ - -#define DWT_CTRL_NOPRFCNT_Pos 24U /*!< DWT CTRL: NOPRFCNT Position */ -#define DWT_CTRL_NOPRFCNT_Msk (0x1UL << DWT_CTRL_NOPRFCNT_Pos) /*!< DWT CTRL: NOPRFCNT Mask */ - -#define DWT_CTRL_CYCEVTENA_Pos 22U /*!< DWT CTRL: CYCEVTENA Position */ -#define DWT_CTRL_CYCEVTENA_Msk (0x1UL << DWT_CTRL_CYCEVTENA_Pos) /*!< DWT CTRL: CYCEVTENA Mask */ - -#define DWT_CTRL_FOLDEVTENA_Pos 21U /*!< DWT CTRL: FOLDEVTENA Position */ -#define DWT_CTRL_FOLDEVTENA_Msk (0x1UL << DWT_CTRL_FOLDEVTENA_Pos) /*!< DWT CTRL: FOLDEVTENA Mask */ - -#define DWT_CTRL_LSUEVTENA_Pos 20U /*!< DWT CTRL: LSUEVTENA Position */ -#define DWT_CTRL_LSUEVTENA_Msk (0x1UL << DWT_CTRL_LSUEVTENA_Pos) /*!< DWT CTRL: LSUEVTENA Mask */ - -#define DWT_CTRL_SLEEPEVTENA_Pos 19U /*!< DWT CTRL: SLEEPEVTENA Position */ -#define DWT_CTRL_SLEEPEVTENA_Msk (0x1UL << DWT_CTRL_SLEEPEVTENA_Pos) /*!< DWT CTRL: SLEEPEVTENA Mask */ - -#define DWT_CTRL_EXCEVTENA_Pos 18U /*!< DWT CTRL: EXCEVTENA Position */ -#define DWT_CTRL_EXCEVTENA_Msk (0x1UL << DWT_CTRL_EXCEVTENA_Pos) /*!< DWT CTRL: EXCEVTENA Mask */ - -#define DWT_CTRL_CPIEVTENA_Pos 17U /*!< DWT CTRL: CPIEVTENA Position */ -#define DWT_CTRL_CPIEVTENA_Msk (0x1UL << DWT_CTRL_CPIEVTENA_Pos) /*!< DWT CTRL: CPIEVTENA Mask */ - -#define DWT_CTRL_EXCTRCENA_Pos 16U /*!< DWT CTRL: EXCTRCENA Position */ -#define DWT_CTRL_EXCTRCENA_Msk (0x1UL << DWT_CTRL_EXCTRCENA_Pos) /*!< DWT CTRL: EXCTRCENA Mask */ - -#define DWT_CTRL_PCSAMPLENA_Pos 12U /*!< DWT CTRL: PCSAMPLENA Position */ -#define DWT_CTRL_PCSAMPLENA_Msk (0x1UL << DWT_CTRL_PCSAMPLENA_Pos) /*!< DWT CTRL: PCSAMPLENA Mask */ - -#define DWT_CTRL_SYNCTAP_Pos 10U /*!< DWT CTRL: SYNCTAP Position */ -#define DWT_CTRL_SYNCTAP_Msk (0x3UL << DWT_CTRL_SYNCTAP_Pos) /*!< DWT CTRL: SYNCTAP Mask */ - -#define DWT_CTRL_CYCTAP_Pos 9U /*!< DWT CTRL: CYCTAP Position */ -#define DWT_CTRL_CYCTAP_Msk (0x1UL << DWT_CTRL_CYCTAP_Pos) /*!< DWT CTRL: CYCTAP Mask */ - -#define DWT_CTRL_POSTINIT_Pos 5U /*!< DWT CTRL: POSTINIT Position */ -#define DWT_CTRL_POSTINIT_Msk (0xFUL << DWT_CTRL_POSTINIT_Pos) /*!< DWT CTRL: POSTINIT Mask */ - -#define DWT_CTRL_POSTPRESET_Pos 1U /*!< DWT CTRL: POSTPRESET Position */ -#define DWT_CTRL_POSTPRESET_Msk (0xFUL << DWT_CTRL_POSTPRESET_Pos) /*!< DWT CTRL: POSTPRESET Mask */ - -#define DWT_CTRL_CYCCNTENA_Pos 0U /*!< DWT CTRL: CYCCNTENA Position */ -#define DWT_CTRL_CYCCNTENA_Msk (0x1UL /*<< DWT_CTRL_CYCCNTENA_Pos*/) /*!< DWT CTRL: CYCCNTENA Mask */ - -/* DWT CPI Count Register Definitions */ -#define DWT_CPICNT_CPICNT_Pos 0U /*!< DWT CPICNT: CPICNT Position */ -#define DWT_CPICNT_CPICNT_Msk (0xFFUL /*<< DWT_CPICNT_CPICNT_Pos*/) /*!< DWT CPICNT: CPICNT Mask */ - -/* DWT Exception Overhead Count Register Definitions */ -#define DWT_EXCCNT_EXCCNT_Pos 0U /*!< DWT EXCCNT: EXCCNT Position */ -#define DWT_EXCCNT_EXCCNT_Msk (0xFFUL /*<< DWT_EXCCNT_EXCCNT_Pos*/) /*!< DWT EXCCNT: EXCCNT Mask */ - -/* DWT Sleep Count Register Definitions */ -#define DWT_SLEEPCNT_SLEEPCNT_Pos 0U /*!< DWT SLEEPCNT: SLEEPCNT Position */ -#define DWT_SLEEPCNT_SLEEPCNT_Msk (0xFFUL /*<< DWT_SLEEPCNT_SLEEPCNT_Pos*/) /*!< DWT SLEEPCNT: SLEEPCNT Mask */ - -/* DWT LSU Count Register Definitions */ -#define DWT_LSUCNT_LSUCNT_Pos 0U /*!< DWT LSUCNT: LSUCNT Position */ -#define DWT_LSUCNT_LSUCNT_Msk (0xFFUL /*<< DWT_LSUCNT_LSUCNT_Pos*/) /*!< DWT LSUCNT: LSUCNT Mask */ - -/* DWT Folded-instruction Count Register Definitions */ -#define DWT_FOLDCNT_FOLDCNT_Pos 0U /*!< DWT FOLDCNT: FOLDCNT Position */ -#define DWT_FOLDCNT_FOLDCNT_Msk (0xFFUL /*<< DWT_FOLDCNT_FOLDCNT_Pos*/) /*!< DWT FOLDCNT: FOLDCNT Mask */ - -/* DWT Comparator Mask Register Definitions */ -#define DWT_MASK_MASK_Pos 0U /*!< DWT MASK: MASK Position */ -#define DWT_MASK_MASK_Msk (0x1FUL /*<< DWT_MASK_MASK_Pos*/) /*!< DWT MASK: MASK Mask */ - -/* DWT Comparator Function Register Definitions */ -#define DWT_FUNCTION_MATCHED_Pos 24U /*!< DWT FUNCTION: MATCHED Position */ -#define DWT_FUNCTION_MATCHED_Msk (0x1UL << DWT_FUNCTION_MATCHED_Pos) /*!< DWT FUNCTION: MATCHED Mask */ - -#define DWT_FUNCTION_DATAVADDR1_Pos 16U /*!< DWT FUNCTION: DATAVADDR1 Position */ -#define DWT_FUNCTION_DATAVADDR1_Msk (0xFUL << DWT_FUNCTION_DATAVADDR1_Pos) /*!< DWT FUNCTION: DATAVADDR1 Mask */ - -#define DWT_FUNCTION_DATAVADDR0_Pos 12U /*!< DWT FUNCTION: DATAVADDR0 Position */ -#define DWT_FUNCTION_DATAVADDR0_Msk (0xFUL << DWT_FUNCTION_DATAVADDR0_Pos) /*!< DWT FUNCTION: DATAVADDR0 Mask */ - -#define DWT_FUNCTION_DATAVSIZE_Pos 10U /*!< DWT FUNCTION: DATAVSIZE Position */ -#define DWT_FUNCTION_DATAVSIZE_Msk (0x3UL << DWT_FUNCTION_DATAVSIZE_Pos) /*!< DWT FUNCTION: DATAVSIZE Mask */ - -#define DWT_FUNCTION_LNK1ENA_Pos 9U /*!< DWT FUNCTION: LNK1ENA Position */ -#define DWT_FUNCTION_LNK1ENA_Msk (0x1UL << DWT_FUNCTION_LNK1ENA_Pos) /*!< DWT FUNCTION: LNK1ENA Mask */ - -#define DWT_FUNCTION_DATAVMATCH_Pos 8U /*!< DWT FUNCTION: DATAVMATCH Position */ -#define DWT_FUNCTION_DATAVMATCH_Msk (0x1UL << DWT_FUNCTION_DATAVMATCH_Pos) /*!< DWT FUNCTION: DATAVMATCH Mask */ - -#define DWT_FUNCTION_CYCMATCH_Pos 7U /*!< DWT FUNCTION: CYCMATCH Position */ -#define DWT_FUNCTION_CYCMATCH_Msk (0x1UL << DWT_FUNCTION_CYCMATCH_Pos) /*!< DWT FUNCTION: CYCMATCH Mask */ - -#define DWT_FUNCTION_EMITRANGE_Pos 5U /*!< DWT FUNCTION: EMITRANGE Position */ -#define DWT_FUNCTION_EMITRANGE_Msk (0x1UL << DWT_FUNCTION_EMITRANGE_Pos) /*!< DWT FUNCTION: EMITRANGE Mask */ - -#define DWT_FUNCTION_FUNCTION_Pos 0U /*!< DWT FUNCTION: FUNCTION Position */ -#define DWT_FUNCTION_FUNCTION_Msk (0xFUL /*<< DWT_FUNCTION_FUNCTION_Pos*/) /*!< DWT FUNCTION: FUNCTION Mask */ - -/*@}*/ /* end of group CMSIS_DWT */ - - -/** - \ingroup CMSIS_core_register - \defgroup CMSIS_TPI Trace Port Interface (TPI) - \brief Type definitions for the Trace Port Interface (TPI) - @{ - */ - -/** - \brief Structure type to access the Trace Port Interface Register (TPI). - */ -typedef struct -{ - __IOM uint32_t SSPSR; /*!< Offset: 0x000 (R/ ) Supported Parallel Port Size Register */ - __IOM uint32_t CSPSR; /*!< Offset: 0x004 (R/W) Current Parallel Port Size Register */ - uint32_t RESERVED0[2U]; - __IOM uint32_t ACPR; /*!< Offset: 0x010 (R/W) Asynchronous Clock Prescaler Register */ - uint32_t RESERVED1[55U]; - __IOM uint32_t SPPR; /*!< Offset: 0x0F0 (R/W) Selected Pin Protocol Register */ - uint32_t RESERVED2[131U]; - __IM uint32_t FFSR; /*!< Offset: 0x300 (R/ ) Formatter and Flush Status Register */ - __IOM uint32_t FFCR; /*!< Offset: 0x304 (R/W) Formatter and Flush Control Register */ - __IM uint32_t FSCR; /*!< Offset: 0x308 (R/ ) Formatter Synchronization Counter Register */ - uint32_t RESERVED3[759U]; - __IM uint32_t TRIGGER; /*!< Offset: 0xEE8 (R/ ) TRIGGER */ - __IM uint32_t FIFO0; /*!< Offset: 0xEEC (R/ ) Integration ETM Data */ - __IM uint32_t ITATBCTR2; /*!< Offset: 0xEF0 (R/ ) ITATBCTR2 */ - uint32_t RESERVED4[1U]; - __IM uint32_t ITATBCTR0; /*!< Offset: 0xEF8 (R/ ) ITATBCTR0 */ - __IM uint32_t FIFO1; /*!< Offset: 0xEFC (R/ ) Integration ITM Data */ - __IOM uint32_t ITCTRL; /*!< Offset: 0xF00 (R/W) Integration Mode Control */ - uint32_t RESERVED5[39U]; - __IOM uint32_t CLAIMSET; /*!< Offset: 0xFA0 (R/W) Claim tag set */ - __IOM uint32_t CLAIMCLR; /*!< Offset: 0xFA4 (R/W) Claim tag clear */ - uint32_t RESERVED7[8U]; - __IM uint32_t DEVID; /*!< Offset: 0xFC8 (R/ ) TPIU_DEVID */ - __IM uint32_t DEVTYPE; /*!< Offset: 0xFCC (R/ ) TPIU_DEVTYPE */ -} TPI_Type; - -/* TPI Asynchronous Clock Prescaler Register Definitions */ -#define TPI_ACPR_PRESCALER_Pos 0U /*!< @Deprecated TPI ACPR: PRESCALER Position */ -#define TPI_ACPR_PRESCALER_Msk (0x1FFFUL /*<< TPI_ACPR_PRESCALER_Pos*/) /*!< @Deprecated TPI ACPR: PRESCALER Mask */ - -#define TPI_ACPR_SWOSCALER_Pos 0U /*!< TPI ACPR: SWOSCALER Position */ -#define TPI_ACPR_SWOSCALER_Msk (0xFFFFUL /*<< TPI_ACPR_SWOSCALER_Pos*/) /*!< TPI ACPR: SWOSCALER Mask */ - -/* TPI Selected Pin Protocol Register Definitions */ -#define TPI_SPPR_TXMODE_Pos 0U /*!< TPI SPPR: TXMODE Position */ -#define TPI_SPPR_TXMODE_Msk (0x3UL /*<< TPI_SPPR_TXMODE_Pos*/) /*!< TPI SPPR: TXMODE Mask */ - -/* TPI Formatter and Flush Status Register Definitions */ -#define TPI_FFSR_FtNonStop_Pos 3U /*!< TPI FFSR: FtNonStop Position */ -#define TPI_FFSR_FtNonStop_Msk (0x1UL << TPI_FFSR_FtNonStop_Pos) /*!< TPI FFSR: FtNonStop Mask */ - -#define TPI_FFSR_TCPresent_Pos 2U /*!< TPI FFSR: TCPresent Position */ -#define TPI_FFSR_TCPresent_Msk (0x1UL << TPI_FFSR_TCPresent_Pos) /*!< TPI FFSR: TCPresent Mask */ - -#define TPI_FFSR_FtStopped_Pos 1U /*!< TPI FFSR: FtStopped Position */ -#define TPI_FFSR_FtStopped_Msk (0x1UL << TPI_FFSR_FtStopped_Pos) /*!< TPI FFSR: FtStopped Mask */ - -#define TPI_FFSR_FlInProg_Pos 0U /*!< TPI FFSR: FlInProg Position */ -#define TPI_FFSR_FlInProg_Msk (0x1UL /*<< TPI_FFSR_FlInProg_Pos*/) /*!< TPI FFSR: FlInProg Mask */ - -/* TPI Formatter and Flush Control Register Definitions */ -#define TPI_FFCR_TrigIn_Pos 8U /*!< TPI FFCR: TrigIn Position */ -#define TPI_FFCR_TrigIn_Msk (0x1UL << TPI_FFCR_TrigIn_Pos) /*!< TPI FFCR: TrigIn Mask */ - -#define TPI_FFCR_EnFCont_Pos 1U /*!< TPI FFCR: EnFCont Position */ -#define TPI_FFCR_EnFCont_Msk (0x1UL << TPI_FFCR_EnFCont_Pos) /*!< TPI FFCR: EnFCont Mask */ - -/* TPI TRIGGER Register Definitions */ -#define TPI_TRIGGER_TRIGGER_Pos 0U /*!< TPI TRIGGER: TRIGGER Position */ -#define TPI_TRIGGER_TRIGGER_Msk (0x1UL /*<< TPI_TRIGGER_TRIGGER_Pos*/) /*!< TPI TRIGGER: TRIGGER Mask */ - -/* TPI Integration ETM Data Register Definitions (FIFO0) */ -#define TPI_FIFO0_ITM_ATVALID_Pos 29U /*!< TPI FIFO0: ITM_ATVALID Position */ -#define TPI_FIFO0_ITM_ATVALID_Msk (0x3UL << TPI_FIFO0_ITM_ATVALID_Pos) /*!< TPI FIFO0: ITM_ATVALID Mask */ - -#define TPI_FIFO0_ITM_bytecount_Pos 27U /*!< TPI FIFO0: ITM_bytecount Position */ -#define TPI_FIFO0_ITM_bytecount_Msk (0x3UL << TPI_FIFO0_ITM_bytecount_Pos) /*!< TPI FIFO0: ITM_bytecount Mask */ - -#define TPI_FIFO0_ETM_ATVALID_Pos 26U /*!< TPI FIFO0: ETM_ATVALID Position */ -#define TPI_FIFO0_ETM_ATVALID_Msk (0x3UL << TPI_FIFO0_ETM_ATVALID_Pos) /*!< TPI FIFO0: ETM_ATVALID Mask */ - -#define TPI_FIFO0_ETM_bytecount_Pos 24U /*!< TPI FIFO0: ETM_bytecount Position */ -#define TPI_FIFO0_ETM_bytecount_Msk (0x3UL << TPI_FIFO0_ETM_bytecount_Pos) /*!< TPI FIFO0: ETM_bytecount Mask */ - -#define TPI_FIFO0_ETM2_Pos 16U /*!< TPI FIFO0: ETM2 Position */ -#define TPI_FIFO0_ETM2_Msk (0xFFUL << TPI_FIFO0_ETM2_Pos) /*!< TPI FIFO0: ETM2 Mask */ - -#define TPI_FIFO0_ETM1_Pos 8U /*!< TPI FIFO0: ETM1 Position */ -#define TPI_FIFO0_ETM1_Msk (0xFFUL << TPI_FIFO0_ETM1_Pos) /*!< TPI FIFO0: ETM1 Mask */ - -#define TPI_FIFO0_ETM0_Pos 0U /*!< TPI FIFO0: ETM0 Position */ -#define TPI_FIFO0_ETM0_Msk (0xFFUL /*<< TPI_FIFO0_ETM0_Pos*/) /*!< TPI FIFO0: ETM0 Mask */ - -/* TPI ITATBCTR2 Register Definitions */ -#define TPI_ITATBCTR2_ATREADY_Pos 0U /*!< TPI ITATBCTR2: ATREADY Position */ -#define TPI_ITATBCTR2_ATREADY_Msk (0x1UL /*<< TPI_ITATBCTR2_ATREADY_Pos*/) /*!< TPI ITATBCTR2: ATREADY Mask */ - -/* TPI Integration ITM Data Register Definitions (FIFO1) */ -#define TPI_FIFO1_ITM_ATVALID_Pos 29U /*!< TPI FIFO1: ITM_ATVALID Position */ -#define TPI_FIFO1_ITM_ATVALID_Msk (0x3UL << TPI_FIFO1_ITM_ATVALID_Pos) /*!< TPI FIFO1: ITM_ATVALID Mask */ - -#define TPI_FIFO1_ITM_bytecount_Pos 27U /*!< TPI FIFO1: ITM_bytecount Position */ -#define TPI_FIFO1_ITM_bytecount_Msk (0x3UL << TPI_FIFO1_ITM_bytecount_Pos) /*!< TPI FIFO1: ITM_bytecount Mask */ - -#define TPI_FIFO1_ETM_ATVALID_Pos 26U /*!< TPI FIFO1: ETM_ATVALID Position */ -#define TPI_FIFO1_ETM_ATVALID_Msk (0x3UL << TPI_FIFO1_ETM_ATVALID_Pos) /*!< TPI FIFO1: ETM_ATVALID Mask */ - -#define TPI_FIFO1_ETM_bytecount_Pos 24U /*!< TPI FIFO1: ETM_bytecount Position */ -#define TPI_FIFO1_ETM_bytecount_Msk (0x3UL << TPI_FIFO1_ETM_bytecount_Pos) /*!< TPI FIFO1: ETM_bytecount Mask */ - -#define TPI_FIFO1_ITM2_Pos 16U /*!< TPI FIFO1: ITM2 Position */ -#define TPI_FIFO1_ITM2_Msk (0xFFUL << TPI_FIFO1_ITM2_Pos) /*!< TPI FIFO1: ITM2 Mask */ - -#define TPI_FIFO1_ITM1_Pos 8U /*!< TPI FIFO1: ITM1 Position */ -#define TPI_FIFO1_ITM1_Msk (0xFFUL << TPI_FIFO1_ITM1_Pos) /*!< TPI FIFO1: ITM1 Mask */ - -#define TPI_FIFO1_ITM0_Pos 0U /*!< TPI FIFO1: ITM0 Position */ -#define TPI_FIFO1_ITM0_Msk (0xFFUL /*<< TPI_FIFO1_ITM0_Pos*/) /*!< TPI FIFO1: ITM0 Mask */ - -/* TPI ITATBCTR0 Register Definitions */ -#define TPI_ITATBCTR0_ATREADY_Pos 0U /*!< TPI ITATBCTR0: ATREADY Position */ -#define TPI_ITATBCTR0_ATREADY_Msk (0x1UL /*<< TPI_ITATBCTR0_ATREADY_Pos*/) /*!< TPI ITATBCTR0: ATREADY Mask */ - -/* TPI Integration Mode Control Register Definitions */ -#define TPI_ITCTRL_Mode_Pos 0U /*!< TPI ITCTRL: Mode Position */ -#define TPI_ITCTRL_Mode_Msk (0x1UL /*<< TPI_ITCTRL_Mode_Pos*/) /*!< TPI ITCTRL: Mode Mask */ - -/* TPI DEVID Register Definitions */ -#define TPI_DEVID_NRZVALID_Pos 11U /*!< TPI DEVID: NRZVALID Position */ -#define TPI_DEVID_NRZVALID_Msk (0x1UL << TPI_DEVID_NRZVALID_Pos) /*!< TPI DEVID: NRZVALID Mask */ - -#define TPI_DEVID_MANCVALID_Pos 10U /*!< TPI DEVID: MANCVALID Position */ -#define TPI_DEVID_MANCVALID_Msk (0x1UL << TPI_DEVID_MANCVALID_Pos) /*!< TPI DEVID: MANCVALID Mask */ - -#define TPI_DEVID_PTINVALID_Pos 9U /*!< TPI DEVID: PTINVALID Position */ -#define TPI_DEVID_PTINVALID_Msk (0x1UL << TPI_DEVID_PTINVALID_Pos) /*!< TPI DEVID: PTINVALID Mask */ - -#define TPI_DEVID_MinBufSz_Pos 6U /*!< TPI DEVID: MinBufSz Position */ -#define TPI_DEVID_MinBufSz_Msk (0x7UL << TPI_DEVID_MinBufSz_Pos) /*!< TPI DEVID: MinBufSz Mask */ - -#define TPI_DEVID_AsynClkIn_Pos 5U /*!< TPI DEVID: AsynClkIn Position */ -#define TPI_DEVID_AsynClkIn_Msk (0x1UL << TPI_DEVID_AsynClkIn_Pos) /*!< TPI DEVID: AsynClkIn Mask */ - -#define TPI_DEVID_NrTraceInput_Pos 0U /*!< TPI DEVID: NrTraceInput Position */ -#define TPI_DEVID_NrTraceInput_Msk (0x1FUL /*<< TPI_DEVID_NrTraceInput_Pos*/) /*!< TPI DEVID: NrTraceInput Mask */ - -/* TPI DEVTYPE Register Definitions */ -#define TPI_DEVTYPE_MajorType_Pos 4U /*!< TPI DEVTYPE: MajorType Position */ -#define TPI_DEVTYPE_MajorType_Msk (0xFUL << TPI_DEVTYPE_MajorType_Pos) /*!< TPI DEVTYPE: MajorType Mask */ - -#define TPI_DEVTYPE_SubType_Pos 0U /*!< TPI DEVTYPE: SubType Position */ -#define TPI_DEVTYPE_SubType_Msk (0xFUL /*<< TPI_DEVTYPE_SubType_Pos*/) /*!< TPI DEVTYPE: SubType Mask */ - -/*@}*/ /* end of group CMSIS_TPI */ - - -#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) -/** - \ingroup CMSIS_core_register - \defgroup CMSIS_MPU Memory Protection Unit (MPU) - \brief Type definitions for the Memory Protection Unit (MPU) - @{ - */ - -/** - \brief Structure type to access the Memory Protection Unit (MPU). - */ -typedef struct -{ - __IM uint32_t TYPE; /*!< Offset: 0x000 (R/ ) MPU Type Register */ - __IOM uint32_t CTRL; /*!< Offset: 0x004 (R/W) MPU Control Register */ - __IOM uint32_t RNR; /*!< Offset: 0x008 (R/W) MPU Region RNRber Register */ - __IOM uint32_t RBAR; /*!< Offset: 0x00C (R/W) MPU Region Base Address Register */ - __IOM uint32_t RASR; /*!< Offset: 0x010 (R/W) MPU Region Attribute and Size Register */ - __IOM uint32_t RBAR_A1; /*!< Offset: 0x014 (R/W) MPU Alias 1 Region Base Address Register */ - __IOM uint32_t RASR_A1; /*!< Offset: 0x018 (R/W) MPU Alias 1 Region Attribute and Size Register */ - __IOM uint32_t RBAR_A2; /*!< Offset: 0x01C (R/W) MPU Alias 2 Region Base Address Register */ - __IOM uint32_t RASR_A2; /*!< Offset: 0x020 (R/W) MPU Alias 2 Region Attribute and Size Register */ - __IOM uint32_t RBAR_A3; /*!< Offset: 0x024 (R/W) MPU Alias 3 Region Base Address Register */ - __IOM uint32_t RASR_A3; /*!< Offset: 0x028 (R/W) MPU Alias 3 Region Attribute and Size Register */ -} MPU_Type; - -#define MPU_TYPE_RALIASES 4U - -/* MPU Type Register Definitions */ -#define MPU_TYPE_IREGION_Pos 16U /*!< MPU TYPE: IREGION Position */ -#define MPU_TYPE_IREGION_Msk (0xFFUL << MPU_TYPE_IREGION_Pos) /*!< MPU TYPE: IREGION Mask */ - -#define MPU_TYPE_DREGION_Pos 8U /*!< MPU TYPE: DREGION Position */ -#define MPU_TYPE_DREGION_Msk (0xFFUL << MPU_TYPE_DREGION_Pos) /*!< MPU TYPE: DREGION Mask */ - -#define MPU_TYPE_SEPARATE_Pos 0U /*!< MPU TYPE: SEPARATE Position */ -#define MPU_TYPE_SEPARATE_Msk (1UL /*<< MPU_TYPE_SEPARATE_Pos*/) /*!< MPU TYPE: SEPARATE Mask */ - -/* MPU Control Register Definitions */ -#define MPU_CTRL_PRIVDEFENA_Pos 2U /*!< MPU CTRL: PRIVDEFENA Position */ -#define MPU_CTRL_PRIVDEFENA_Msk (1UL << MPU_CTRL_PRIVDEFENA_Pos) /*!< MPU CTRL: PRIVDEFENA Mask */ - -#define MPU_CTRL_HFNMIENA_Pos 1U /*!< MPU CTRL: HFNMIENA Position */ -#define MPU_CTRL_HFNMIENA_Msk (1UL << MPU_CTRL_HFNMIENA_Pos) /*!< MPU CTRL: HFNMIENA Mask */ - -#define MPU_CTRL_ENABLE_Pos 0U /*!< MPU CTRL: ENABLE Position */ -#define MPU_CTRL_ENABLE_Msk (1UL /*<< MPU_CTRL_ENABLE_Pos*/) /*!< MPU CTRL: ENABLE Mask */ - -/* MPU Region Number Register Definitions */ -#define MPU_RNR_REGION_Pos 0U /*!< MPU RNR: REGION Position */ -#define MPU_RNR_REGION_Msk (0xFFUL /*<< MPU_RNR_REGION_Pos*/) /*!< MPU RNR: REGION Mask */ - -/* MPU Region Base Address Register Definitions */ -#define MPU_RBAR_ADDR_Pos 5U /*!< MPU RBAR: ADDR Position */ -#define MPU_RBAR_ADDR_Msk (0x7FFFFFFUL << MPU_RBAR_ADDR_Pos) /*!< MPU RBAR: ADDR Mask */ - -#define MPU_RBAR_VALID_Pos 4U /*!< MPU RBAR: VALID Position */ -#define MPU_RBAR_VALID_Msk (1UL << MPU_RBAR_VALID_Pos) /*!< MPU RBAR: VALID Mask */ - -#define MPU_RBAR_REGION_Pos 0U /*!< MPU RBAR: REGION Position */ -#define MPU_RBAR_REGION_Msk (0xFUL /*<< MPU_RBAR_REGION_Pos*/) /*!< MPU RBAR: REGION Mask */ - -/* MPU Region Attribute and Size Register Definitions */ -#define MPU_RASR_ATTRS_Pos 16U /*!< MPU RASR: MPU Region Attribute field Position */ -#define MPU_RASR_ATTRS_Msk (0xFFFFUL << MPU_RASR_ATTRS_Pos) /*!< MPU RASR: MPU Region Attribute field Mask */ - -#define MPU_RASR_XN_Pos 28U /*!< MPU RASR: ATTRS.XN Position */ -#define MPU_RASR_XN_Msk (1UL << MPU_RASR_XN_Pos) /*!< MPU RASR: ATTRS.XN Mask */ - -#define MPU_RASR_AP_Pos 24U /*!< MPU RASR: ATTRS.AP Position */ -#define MPU_RASR_AP_Msk (0x7UL << MPU_RASR_AP_Pos) /*!< MPU RASR: ATTRS.AP Mask */ - -#define MPU_RASR_TEX_Pos 19U /*!< MPU RASR: ATTRS.TEX Position */ -#define MPU_RASR_TEX_Msk (0x7UL << MPU_RASR_TEX_Pos) /*!< MPU RASR: ATTRS.TEX Mask */ - -#define MPU_RASR_S_Pos 18U /*!< MPU RASR: ATTRS.S Position */ -#define MPU_RASR_S_Msk (1UL << MPU_RASR_S_Pos) /*!< MPU RASR: ATTRS.S Mask */ - -#define MPU_RASR_C_Pos 17U /*!< MPU RASR: ATTRS.C Position */ -#define MPU_RASR_C_Msk (1UL << MPU_RASR_C_Pos) /*!< MPU RASR: ATTRS.C Mask */ - -#define MPU_RASR_B_Pos 16U /*!< MPU RASR: ATTRS.B Position */ -#define MPU_RASR_B_Msk (1UL << MPU_RASR_B_Pos) /*!< MPU RASR: ATTRS.B Mask */ - -#define MPU_RASR_SRD_Pos 8U /*!< MPU RASR: Sub-Region Disable Position */ -#define MPU_RASR_SRD_Msk (0xFFUL << MPU_RASR_SRD_Pos) /*!< MPU RASR: Sub-Region Disable Mask */ - -#define MPU_RASR_SIZE_Pos 1U /*!< MPU RASR: Region Size Field Position */ -#define MPU_RASR_SIZE_Msk (0x1FUL << MPU_RASR_SIZE_Pos) /*!< MPU RASR: Region Size Field Mask */ - -#define MPU_RASR_ENABLE_Pos 0U /*!< MPU RASR: Region enable bit Position */ -#define MPU_RASR_ENABLE_Msk (1UL /*<< MPU_RASR_ENABLE_Pos*/) /*!< MPU RASR: Region enable bit Disable Mask */ - -/*@} end of group CMSIS_MPU */ -#endif - - -/** - \ingroup CMSIS_core_register - \defgroup CMSIS_CoreDebug Core Debug Registers (CoreDebug) - \brief Type definitions for the Core Debug Registers - @{ - */ - -/** - \brief Structure type to access the Core Debug Register (CoreDebug). - */ -typedef struct -{ - __IOM uint32_t DHCSR; /*!< Offset: 0x000 (R/W) Debug Halting Control and Status Register */ - __OM uint32_t DCRSR; /*!< Offset: 0x004 ( /W) Debug Core Register Selector Register */ - __IOM uint32_t DCRDR; /*!< Offset: 0x008 (R/W) Debug Core Register Data Register */ - __IOM uint32_t DEMCR; /*!< Offset: 0x00C (R/W) Debug Exception and Monitor Control Register */ -} CoreDebug_Type; - -/* Debug Halting Control and Status Register Definitions */ -#define CoreDebug_DHCSR_DBGKEY_Pos 16U /*!< CoreDebug DHCSR: DBGKEY Position */ -#define CoreDebug_DHCSR_DBGKEY_Msk (0xFFFFUL << CoreDebug_DHCSR_DBGKEY_Pos) /*!< CoreDebug DHCSR: DBGKEY Mask */ - -#define CoreDebug_DHCSR_S_RESET_ST_Pos 25U /*!< CoreDebug DHCSR: S_RESET_ST Position */ -#define CoreDebug_DHCSR_S_RESET_ST_Msk (1UL << CoreDebug_DHCSR_S_RESET_ST_Pos) /*!< CoreDebug DHCSR: S_RESET_ST Mask */ - -#define CoreDebug_DHCSR_S_RETIRE_ST_Pos 24U /*!< CoreDebug DHCSR: S_RETIRE_ST Position */ -#define CoreDebug_DHCSR_S_RETIRE_ST_Msk (1UL << CoreDebug_DHCSR_S_RETIRE_ST_Pos) /*!< CoreDebug DHCSR: S_RETIRE_ST Mask */ - -#define CoreDebug_DHCSR_S_LOCKUP_Pos 19U /*!< CoreDebug DHCSR: S_LOCKUP Position */ -#define CoreDebug_DHCSR_S_LOCKUP_Msk (1UL << CoreDebug_DHCSR_S_LOCKUP_Pos) /*!< CoreDebug DHCSR: S_LOCKUP Mask */ - -#define CoreDebug_DHCSR_S_SLEEP_Pos 18U /*!< CoreDebug DHCSR: S_SLEEP Position */ -#define CoreDebug_DHCSR_S_SLEEP_Msk (1UL << CoreDebug_DHCSR_S_SLEEP_Pos) /*!< CoreDebug DHCSR: S_SLEEP Mask */ - -#define CoreDebug_DHCSR_S_HALT_Pos 17U /*!< CoreDebug DHCSR: S_HALT Position */ -#define CoreDebug_DHCSR_S_HALT_Msk (1UL << CoreDebug_DHCSR_S_HALT_Pos) /*!< CoreDebug DHCSR: S_HALT Mask */ - -#define CoreDebug_DHCSR_S_REGRDY_Pos 16U /*!< CoreDebug DHCSR: S_REGRDY Position */ -#define CoreDebug_DHCSR_S_REGRDY_Msk (1UL << CoreDebug_DHCSR_S_REGRDY_Pos) /*!< CoreDebug DHCSR: S_REGRDY Mask */ - -#define CoreDebug_DHCSR_C_SNAPSTALL_Pos 5U /*!< CoreDebug DHCSR: C_SNAPSTALL Position */ -#define CoreDebug_DHCSR_C_SNAPSTALL_Msk (1UL << CoreDebug_DHCSR_C_SNAPSTALL_Pos) /*!< CoreDebug DHCSR: C_SNAPSTALL Mask */ - -#define CoreDebug_DHCSR_C_MASKINTS_Pos 3U /*!< CoreDebug DHCSR: C_MASKINTS Position */ -#define CoreDebug_DHCSR_C_MASKINTS_Msk (1UL << CoreDebug_DHCSR_C_MASKINTS_Pos) /*!< CoreDebug DHCSR: C_MASKINTS Mask */ - -#define CoreDebug_DHCSR_C_STEP_Pos 2U /*!< CoreDebug DHCSR: C_STEP Position */ -#define CoreDebug_DHCSR_C_STEP_Msk (1UL << CoreDebug_DHCSR_C_STEP_Pos) /*!< CoreDebug DHCSR: C_STEP Mask */ - -#define CoreDebug_DHCSR_C_HALT_Pos 1U /*!< CoreDebug DHCSR: C_HALT Position */ -#define CoreDebug_DHCSR_C_HALT_Msk (1UL << CoreDebug_DHCSR_C_HALT_Pos) /*!< CoreDebug DHCSR: C_HALT Mask */ - -#define CoreDebug_DHCSR_C_DEBUGEN_Pos 0U /*!< CoreDebug DHCSR: C_DEBUGEN Position */ -#define CoreDebug_DHCSR_C_DEBUGEN_Msk (1UL /*<< CoreDebug_DHCSR_C_DEBUGEN_Pos*/) /*!< CoreDebug DHCSR: C_DEBUGEN Mask */ - -/* Debug Core Register Selector Register Definitions */ -#define CoreDebug_DCRSR_REGWnR_Pos 16U /*!< CoreDebug DCRSR: REGWnR Position */ -#define CoreDebug_DCRSR_REGWnR_Msk (1UL << CoreDebug_DCRSR_REGWnR_Pos) /*!< CoreDebug DCRSR: REGWnR Mask */ - -#define CoreDebug_DCRSR_REGSEL_Pos 0U /*!< CoreDebug DCRSR: REGSEL Position */ -#define CoreDebug_DCRSR_REGSEL_Msk (0x1FUL /*<< CoreDebug_DCRSR_REGSEL_Pos*/) /*!< CoreDebug DCRSR: REGSEL Mask */ - -/* Debug Exception and Monitor Control Register Definitions */ -#define CoreDebug_DEMCR_TRCENA_Pos 24U /*!< CoreDebug DEMCR: TRCENA Position */ -#define CoreDebug_DEMCR_TRCENA_Msk (1UL << CoreDebug_DEMCR_TRCENA_Pos) /*!< CoreDebug DEMCR: TRCENA Mask */ - -#define CoreDebug_DEMCR_MON_REQ_Pos 19U /*!< CoreDebug DEMCR: MON_REQ Position */ -#define CoreDebug_DEMCR_MON_REQ_Msk (1UL << CoreDebug_DEMCR_MON_REQ_Pos) /*!< CoreDebug DEMCR: MON_REQ Mask */ - -#define CoreDebug_DEMCR_MON_STEP_Pos 18U /*!< CoreDebug DEMCR: MON_STEP Position */ -#define CoreDebug_DEMCR_MON_STEP_Msk (1UL << CoreDebug_DEMCR_MON_STEP_Pos) /*!< CoreDebug DEMCR: MON_STEP Mask */ - -#define CoreDebug_DEMCR_MON_PEND_Pos 17U /*!< CoreDebug DEMCR: MON_PEND Position */ -#define CoreDebug_DEMCR_MON_PEND_Msk (1UL << CoreDebug_DEMCR_MON_PEND_Pos) /*!< CoreDebug DEMCR: MON_PEND Mask */ - -#define CoreDebug_DEMCR_MON_EN_Pos 16U /*!< CoreDebug DEMCR: MON_EN Position */ -#define CoreDebug_DEMCR_MON_EN_Msk (1UL << CoreDebug_DEMCR_MON_EN_Pos) /*!< CoreDebug DEMCR: MON_EN Mask */ - -#define CoreDebug_DEMCR_VC_HARDERR_Pos 10U /*!< CoreDebug DEMCR: VC_HARDERR Position */ -#define CoreDebug_DEMCR_VC_HARDERR_Msk (1UL << CoreDebug_DEMCR_VC_HARDERR_Pos) /*!< CoreDebug DEMCR: VC_HARDERR Mask */ - -#define CoreDebug_DEMCR_VC_INTERR_Pos 9U /*!< CoreDebug DEMCR: VC_INTERR Position */ -#define CoreDebug_DEMCR_VC_INTERR_Msk (1UL << CoreDebug_DEMCR_VC_INTERR_Pos) /*!< CoreDebug DEMCR: VC_INTERR Mask */ - -#define CoreDebug_DEMCR_VC_BUSERR_Pos 8U /*!< CoreDebug DEMCR: VC_BUSERR Position */ -#define CoreDebug_DEMCR_VC_BUSERR_Msk (1UL << CoreDebug_DEMCR_VC_BUSERR_Pos) /*!< CoreDebug DEMCR: VC_BUSERR Mask */ - -#define CoreDebug_DEMCR_VC_STATERR_Pos 7U /*!< CoreDebug DEMCR: VC_STATERR Position */ -#define CoreDebug_DEMCR_VC_STATERR_Msk (1UL << CoreDebug_DEMCR_VC_STATERR_Pos) /*!< CoreDebug DEMCR: VC_STATERR Mask */ - -#define CoreDebug_DEMCR_VC_CHKERR_Pos 6U /*!< CoreDebug DEMCR: VC_CHKERR Position */ -#define CoreDebug_DEMCR_VC_CHKERR_Msk (1UL << CoreDebug_DEMCR_VC_CHKERR_Pos) /*!< CoreDebug DEMCR: VC_CHKERR Mask */ - -#define CoreDebug_DEMCR_VC_NOCPERR_Pos 5U /*!< CoreDebug DEMCR: VC_NOCPERR Position */ -#define CoreDebug_DEMCR_VC_NOCPERR_Msk (1UL << CoreDebug_DEMCR_VC_NOCPERR_Pos) /*!< CoreDebug DEMCR: VC_NOCPERR Mask */ - -#define CoreDebug_DEMCR_VC_MMERR_Pos 4U /*!< CoreDebug DEMCR: VC_MMERR Position */ -#define CoreDebug_DEMCR_VC_MMERR_Msk (1UL << CoreDebug_DEMCR_VC_MMERR_Pos) /*!< CoreDebug DEMCR: VC_MMERR Mask */ - -#define CoreDebug_DEMCR_VC_CORERESET_Pos 0U /*!< CoreDebug DEMCR: VC_CORERESET Position */ -#define CoreDebug_DEMCR_VC_CORERESET_Msk (1UL /*<< CoreDebug_DEMCR_VC_CORERESET_Pos*/) /*!< CoreDebug DEMCR: VC_CORERESET Mask */ - -/*@} end of group CMSIS_CoreDebug */ - - -/** - \ingroup CMSIS_core_register - \defgroup CMSIS_core_bitfield Core register bit field macros - \brief Macros for use with bit field definitions (xxx_Pos, xxx_Msk). - @{ - */ - -/** - \brief Mask and shift a bit field value for use in a register bit range. - \param[in] field Name of the register bit field. - \param[in] value Value of the bit field. This parameter is interpreted as an uint32_t type. - \return Masked and shifted value. -*/ -#define _VAL2FLD(field, value) (((uint32_t)(value) << field ## _Pos) & field ## _Msk) - -/** - \brief Mask and shift a register value to extract a bit filed value. - \param[in] field Name of the register bit field. - \param[in] value Value of register. This parameter is interpreted as an uint32_t type. - \return Masked and shifted bit field value. -*/ -#define _FLD2VAL(field, value) (((uint32_t)(value) & field ## _Msk) >> field ## _Pos) - -/*@} end of group CMSIS_core_bitfield */ - - -/** - \ingroup CMSIS_core_register - \defgroup CMSIS_core_base Core Definitions - \brief Definitions for base addresses, unions, and structures. - @{ - */ - -/* Memory mapping of Core Hardware */ -#define SCS_BASE (0xE000E000UL) /*!< System Control Space Base Address */ -#define ITM_BASE (0xE0000000UL) /*!< ITM Base Address */ -#define DWT_BASE (0xE0001000UL) /*!< DWT Base Address */ -#define TPI_BASE (0xE0040000UL) /*!< TPI Base Address */ -#define CoreDebug_BASE (0xE000EDF0UL) /*!< Core Debug Base Address */ -#define SysTick_BASE (SCS_BASE + 0x0010UL) /*!< SysTick Base Address */ -#define NVIC_BASE (SCS_BASE + 0x0100UL) /*!< NVIC Base Address */ -#define SCB_BASE (SCS_BASE + 0x0D00UL) /*!< System Control Block Base Address */ - -#define SCnSCB ((SCnSCB_Type *) SCS_BASE ) /*!< System control Register not in SCB */ -#define SCB ((SCB_Type *) SCB_BASE ) /*!< SCB configuration struct */ -#define SysTick ((SysTick_Type *) SysTick_BASE ) /*!< SysTick configuration struct */ -#define NVIC ((NVIC_Type *) NVIC_BASE ) /*!< NVIC configuration struct */ -#define ITM ((ITM_Type *) ITM_BASE ) /*!< ITM configuration struct */ -#define DWT ((DWT_Type *) DWT_BASE ) /*!< DWT configuration struct */ -#define TPI ((TPI_Type *) TPI_BASE ) /*!< TPI configuration struct */ -#define CoreDebug ((CoreDebug_Type *) CoreDebug_BASE) /*!< Core Debug configuration struct */ - -#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) - #define MPU_BASE (SCS_BASE + 0x0D90UL) /*!< Memory Protection Unit */ - #define MPU ((MPU_Type *) MPU_BASE ) /*!< Memory Protection Unit */ -#endif - -/*@} */ - - - -/******************************************************************************* - * Hardware Abstraction Layer - Core Function Interface contains: - - Core NVIC Functions - - Core SysTick Functions - - Core Debug Functions - - Core Register Access Functions - ******************************************************************************/ -/** - \defgroup CMSIS_Core_FunctionInterface Functions and Instructions Reference -*/ - - - -/* ########################## NVIC functions #################################### */ -/** - \ingroup CMSIS_Core_FunctionInterface - \defgroup CMSIS_Core_NVICFunctions NVIC Functions - \brief Functions that manage interrupts and exceptions via the NVIC. - @{ - */ - -#ifdef CMSIS_NVIC_VIRTUAL - #ifndef CMSIS_NVIC_VIRTUAL_HEADER_FILE - #define CMSIS_NVIC_VIRTUAL_HEADER_FILE "cmsis_nvic_virtual.h" - #endif - #include CMSIS_NVIC_VIRTUAL_HEADER_FILE -#else - #define NVIC_SetPriorityGrouping __NVIC_SetPriorityGrouping - #define NVIC_GetPriorityGrouping __NVIC_GetPriorityGrouping - #define NVIC_EnableIRQ __NVIC_EnableIRQ - #define NVIC_GetEnableIRQ __NVIC_GetEnableIRQ - #define NVIC_DisableIRQ __NVIC_DisableIRQ - #define NVIC_GetPendingIRQ __NVIC_GetPendingIRQ - #define NVIC_SetPendingIRQ __NVIC_SetPendingIRQ - #define NVIC_ClearPendingIRQ __NVIC_ClearPendingIRQ - #define NVIC_GetActive __NVIC_GetActive - #define NVIC_SetPriority __NVIC_SetPriority - #define NVIC_GetPriority __NVIC_GetPriority - #define NVIC_SystemReset __NVIC_SystemReset -#endif /* CMSIS_NVIC_VIRTUAL */ - -#ifdef CMSIS_VECTAB_VIRTUAL - #ifndef CMSIS_VECTAB_VIRTUAL_HEADER_FILE - #define CMSIS_VECTAB_VIRTUAL_HEADER_FILE "cmsis_vectab_virtual.h" - #endif - #include CMSIS_VECTAB_VIRTUAL_HEADER_FILE -#else - #define NVIC_SetVector __NVIC_SetVector - #define NVIC_GetVector __NVIC_GetVector -#endif /* (CMSIS_VECTAB_VIRTUAL) */ - -#define NVIC_USER_IRQ_OFFSET 16 - - - -/** - \brief Set Priority Grouping - \details Sets the priority grouping field using the required unlock sequence. - The parameter PriorityGroup is assigned to the field SCB->AIRCR [10:8] PRIGROUP field. - Only values from 0..7 are used. - In case of a conflict between priority grouping and available - priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set. - \param [in] PriorityGroup Priority grouping field. - */ -__STATIC_INLINE void __NVIC_SetPriorityGrouping(uint32_t PriorityGroup) -{ - uint32_t reg_value; - uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ - - reg_value = SCB->AIRCR; /* read old register configuration */ - reg_value &= ~((uint32_t)(SCB_AIRCR_VECTKEY_Msk | SCB_AIRCR_PRIGROUP_Msk)); /* clear bits to change */ - reg_value = (reg_value | - ((uint32_t)0x5FAUL << SCB_AIRCR_VECTKEY_Pos) | - (PriorityGroupTmp << SCB_AIRCR_PRIGROUP_Pos) ); /* Insert write key and priority group */ - SCB->AIRCR = reg_value; -} - - -/** - \brief Get Priority Grouping - \details Reads the priority grouping field from the NVIC Interrupt Controller. - \return Priority grouping field (SCB->AIRCR [10:8] PRIGROUP field). - */ -__STATIC_INLINE uint32_t __NVIC_GetPriorityGrouping(void) -{ - return ((uint32_t)((SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) >> SCB_AIRCR_PRIGROUP_Pos)); -} - - -/** - \brief Enable Interrupt - \details Enables a device specific interrupt in the NVIC interrupt controller. - \param [in] IRQn Device specific interrupt number. - \note IRQn must not be negative. - */ -__STATIC_INLINE void __NVIC_EnableIRQ(IRQn_Type IRQn) -{ - if ((int32_t)(IRQn) >= 0) - { - NVIC->ISER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); - } -} - - -/** - \brief Get Interrupt Enable status - \details Returns a device specific interrupt enable status from the NVIC interrupt controller. - \param [in] IRQn Device specific interrupt number. - \return 0 Interrupt is not enabled. - \return 1 Interrupt is enabled. - \note IRQn must not be negative. - */ -__STATIC_INLINE uint32_t __NVIC_GetEnableIRQ(IRQn_Type IRQn) -{ - if ((int32_t)(IRQn) >= 0) - { - return((uint32_t)(((NVIC->ISER[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); - } - else - { - return(0U); - } -} - - -/** - \brief Disable Interrupt - \details Disables a device specific interrupt in the NVIC interrupt controller. - \param [in] IRQn Device specific interrupt number. - \note IRQn must not be negative. - */ -__STATIC_INLINE void __NVIC_DisableIRQ(IRQn_Type IRQn) -{ - if ((int32_t)(IRQn) >= 0) - { - NVIC->ICER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); - __DSB(); - __ISB(); - } -} - - -/** - \brief Get Pending Interrupt - \details Reads the NVIC pending register and returns the pending bit for the specified device specific interrupt. - \param [in] IRQn Device specific interrupt number. - \return 0 Interrupt status is not pending. - \return 1 Interrupt status is pending. - \note IRQn must not be negative. - */ -__STATIC_INLINE uint32_t __NVIC_GetPendingIRQ(IRQn_Type IRQn) -{ - if ((int32_t)(IRQn) >= 0) - { - return((uint32_t)(((NVIC->ISPR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); - } - else - { - return(0U); - } -} - - -/** - \brief Set Pending Interrupt - \details Sets the pending bit of a device specific interrupt in the NVIC pending register. - \param [in] IRQn Device specific interrupt number. - \note IRQn must not be negative. - */ -__STATIC_INLINE void __NVIC_SetPendingIRQ(IRQn_Type IRQn) -{ - if ((int32_t)(IRQn) >= 0) - { - NVIC->ISPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); - } -} - - -/** - \brief Clear Pending Interrupt - \details Clears the pending bit of a device specific interrupt in the NVIC pending register. - \param [in] IRQn Device specific interrupt number. - \note IRQn must not be negative. - */ -__STATIC_INLINE void __NVIC_ClearPendingIRQ(IRQn_Type IRQn) -{ - if ((int32_t)(IRQn) >= 0) - { - NVIC->ICPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); - } -} - - -/** - \brief Get Active Interrupt - \details Reads the active register in the NVIC and returns the active bit for the device specific interrupt. - \param [in] IRQn Device specific interrupt number. - \return 0 Interrupt status is not active. - \return 1 Interrupt status is active. - \note IRQn must not be negative. - */ -__STATIC_INLINE uint32_t __NVIC_GetActive(IRQn_Type IRQn) -{ - if ((int32_t)(IRQn) >= 0) - { - return((uint32_t)(((NVIC->IABR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); - } - else - { - return(0U); - } -} - - -/** - \brief Set Interrupt Priority - \details Sets the priority of a device specific interrupt or a processor exception. - The interrupt number can be positive to specify a device specific interrupt, - or negative to specify a processor exception. - \param [in] IRQn Interrupt number. - \param [in] priority Priority to set. - \note The priority cannot be set for every processor exception. - */ -__STATIC_INLINE void __NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority) -{ - if ((int32_t)(IRQn) >= 0) - { - NVIC->IP[((uint32_t)IRQn)] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL); - } - else - { - SCB->SHP[(((uint32_t)IRQn) & 0xFUL)-4UL] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL); - } -} - - -/** - \brief Get Interrupt Priority - \details Reads the priority of a device specific interrupt or a processor exception. - The interrupt number can be positive to specify a device specific interrupt, - or negative to specify a processor exception. - \param [in] IRQn Interrupt number. - \return Interrupt Priority. - Value is aligned automatically to the implemented priority bits of the microcontroller. - */ -__STATIC_INLINE uint32_t __NVIC_GetPriority(IRQn_Type IRQn) -{ - - if ((int32_t)(IRQn) >= 0) - { - return(((uint32_t)NVIC->IP[((uint32_t)IRQn)] >> (8U - __NVIC_PRIO_BITS))); - } - else - { - return(((uint32_t)SCB->SHP[(((uint32_t)IRQn) & 0xFUL)-4UL] >> (8U - __NVIC_PRIO_BITS))); - } -} - - -/** - \brief Encode Priority - \details Encodes the priority for an interrupt with the given priority group, - preemptive priority value, and subpriority value. - In case of a conflict between priority grouping and available - priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set. - \param [in] PriorityGroup Used priority group. - \param [in] PreemptPriority Preemptive priority value (starting from 0). - \param [in] SubPriority Subpriority value (starting from 0). - \return Encoded priority. Value can be used in the function \ref NVIC_SetPriority(). - */ -__STATIC_INLINE uint32_t NVIC_EncodePriority (uint32_t PriorityGroup, uint32_t PreemptPriority, uint32_t SubPriority) -{ - uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ - uint32_t PreemptPriorityBits; - uint32_t SubPriorityBits; - - PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp); - SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS)); - - return ( - ((PreemptPriority & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL)) << SubPriorityBits) | - ((SubPriority & (uint32_t)((1UL << (SubPriorityBits )) - 1UL))) - ); -} - - -/** - \brief Decode Priority - \details Decodes an interrupt priority value with a given priority group to - preemptive priority value and subpriority value. - In case of a conflict between priority grouping and available - priority bits (__NVIC_PRIO_BITS) the smallest possible priority group is set. - \param [in] Priority Priority value, which can be retrieved with the function \ref NVIC_GetPriority(). - \param [in] PriorityGroup Used priority group. - \param [out] pPreemptPriority Preemptive priority value (starting from 0). - \param [out] pSubPriority Subpriority value (starting from 0). - */ -__STATIC_INLINE void NVIC_DecodePriority (uint32_t Priority, uint32_t PriorityGroup, uint32_t* const pPreemptPriority, uint32_t* const pSubPriority) -{ - uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ - uint32_t PreemptPriorityBits; - uint32_t SubPriorityBits; - - PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp); - SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS)); - - *pPreemptPriority = (Priority >> SubPriorityBits) & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL); - *pSubPriority = (Priority ) & (uint32_t)((1UL << (SubPriorityBits )) - 1UL); -} - - -/** - \brief Set Interrupt Vector - \details Sets an interrupt vector in SRAM based interrupt vector table. - The interrupt number can be positive to specify a device specific interrupt, - or negative to specify a processor exception. - VTOR must been relocated to SRAM before. - \param [in] IRQn Interrupt number - \param [in] vector Address of interrupt handler function - */ -__STATIC_INLINE void __NVIC_SetVector(IRQn_Type IRQn, uint32_t vector) -{ - uint32_t *vectors = (uint32_t *)SCB->VTOR; - vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET] = vector; -} - - -/** - \brief Get Interrupt Vector - \details Reads an interrupt vector from interrupt vector table. - The interrupt number can be positive to specify a device specific interrupt, - or negative to specify a processor exception. - \param [in] IRQn Interrupt number. - \return Address of interrupt handler function - */ -__STATIC_INLINE uint32_t __NVIC_GetVector(IRQn_Type IRQn) -{ - uint32_t *vectors = (uint32_t *)SCB->VTOR; - return vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET]; -} - - -/** - \brief System Reset - \details Initiates a system reset request to reset the MCU. - */ -__STATIC_INLINE void __NVIC_SystemReset(void) -{ - __DSB(); /* Ensure all outstanding memory accesses included - buffered write are completed before reset */ - SCB->AIRCR = (uint32_t)((0x5FAUL << SCB_AIRCR_VECTKEY_Pos) | - (SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) | - SCB_AIRCR_SYSRESETREQ_Msk ); /* Keep priority group unchanged */ - __DSB(); /* Ensure completion of memory access */ - - for(;;) /* wait until reset */ - { - __NOP(); - } -} - -/*@} end of CMSIS_Core_NVICFunctions */ - -/* ########################## MPU functions #################################### */ - -#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) - -#include "mpu_armv7.h" - -#endif - -/* ########################## FPU functions #################################### */ -/** - \ingroup CMSIS_Core_FunctionInterface - \defgroup CMSIS_Core_FpuFunctions FPU Functions - \brief Function that provides FPU type. - @{ - */ - -/** - \brief get FPU type - \details returns the FPU type - \returns - - \b 0: No FPU - - \b 1: Single precision FPU - - \b 2: Double + Single precision FPU - */ -__STATIC_INLINE uint32_t SCB_GetFPUType(void) -{ - return 0U; /* No FPU */ -} - - -/*@} end of CMSIS_Core_FpuFunctions */ - - - -/* ################################## SysTick function ############################################ */ -/** - \ingroup CMSIS_Core_FunctionInterface - \defgroup CMSIS_Core_SysTickFunctions SysTick Functions - \brief Functions that configure the System. - @{ - */ - -#if defined (__Vendor_SysTickConfig) && (__Vendor_SysTickConfig == 0U) - -/** - \brief System Tick Configuration - \details Initializes the System Timer and its interrupt, and starts the System Tick Timer. - Counter is in free running mode to generate periodic interrupts. - \param [in] ticks Number of ticks between two interrupts. - \return 0 Function succeeded. - \return 1 Function failed. - \note When the variable __Vendor_SysTickConfig is set to 1, then the - function SysTick_Config is not included. In this case, the file device.h - must contain a vendor-specific implementation of this function. - */ -__STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks) -{ - if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk) - { - return (1UL); /* Reload value impossible */ - } - - SysTick->LOAD = (uint32_t)(ticks - 1UL); /* set reload register */ - NVIC_SetPriority (SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */ - SysTick->VAL = 0UL; /* Load the SysTick Counter Value */ - SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk | - SysTick_CTRL_TICKINT_Msk | - SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */ - return (0UL); /* Function successful */ -} - -#endif - -/*@} end of CMSIS_Core_SysTickFunctions */ - - - -/* ##################################### Debug In/Output function ########################################### */ -/** - \ingroup CMSIS_Core_FunctionInterface - \defgroup CMSIS_core_DebugFunctions ITM Functions - \brief Functions that access the ITM debug interface. - @{ - */ - -extern volatile int32_t ITM_RxBuffer; /*!< External variable to receive characters. */ -#define ITM_RXBUFFER_EMPTY ((int32_t)0x5AA55AA5U) /*!< Value identifying \ref ITM_RxBuffer is ready for next character. */ - - -/** - \brief ITM Send Character - \details Transmits a character via the ITM channel 0, and - \li Just returns when no debugger is connected that has booked the output. - \li Is blocking when a debugger is connected, but the previous character sent has not been transmitted. - \param [in] ch Character to transmit. - \returns Character to transmit. - */ -__STATIC_INLINE uint32_t ITM_SendChar (uint32_t ch) -{ - if (((ITM->TCR & ITM_TCR_ITMENA_Msk) != 0UL) && /* ITM enabled */ - ((ITM->TER & 1UL ) != 0UL) ) /* ITM Port #0 enabled */ - { - while (ITM->PORT[0U].u32 == 0UL) - { - __NOP(); - } - ITM->PORT[0U].u8 = (uint8_t)ch; - } - return (ch); -} - - -/** - \brief ITM Receive Character - \details Inputs a character via the external variable \ref ITM_RxBuffer. - \return Received character. - \return -1 No character pending. - */ -__STATIC_INLINE int32_t ITM_ReceiveChar (void) -{ - int32_t ch = -1; /* no character available */ - - if (ITM_RxBuffer != ITM_RXBUFFER_EMPTY) - { - ch = ITM_RxBuffer; - ITM_RxBuffer = ITM_RXBUFFER_EMPTY; /* ready for next character */ - } - - return (ch); -} - - -/** - \brief ITM Check Character - \details Checks whether a character is pending for reading in the variable \ref ITM_RxBuffer. - \return 0 No character available. - \return 1 Character available. - */ -__STATIC_INLINE int32_t ITM_CheckChar (void) -{ - - if (ITM_RxBuffer == ITM_RXBUFFER_EMPTY) - { - return (0); /* no character available */ - } - else - { - return (1); /* character available */ - } -} - -/*@} end of CMSIS_core_DebugFunctions */ - - - - -#ifdef __cplusplus -} -#endif - -#endif /* __CORE_CM3_H_DEPENDANT */ - -#endif /* __CMSIS_GENERIC */ diff --git a/bsp/essemi/es32f0271/libraries/CMSIS/Include/core_cm33.h b/bsp/essemi/es32f0271/libraries/CMSIS/Include/core_cm33.h deleted file mode 100644 index b1efbcae7c..0000000000 --- a/bsp/essemi/es32f0271/libraries/CMSIS/Include/core_cm33.h +++ /dev/null @@ -1,2963 +0,0 @@ -/**************************************************************************//** - * @file core_cm33.h - * @brief CMSIS Cortex-M33 Core Peripheral Access Layer Header File - * @version V5.0.5 - * @date 08. January 2018 - ******************************************************************************/ -/* - * Copyright (c) 2009-2017 ARM Limited. All rights reserved. - * - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed under the Apache License, Version 2.0 (the License); you may - * not use this file except in compliance with the License. - * You may obtain a copy of the License at - * - * www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an AS IS BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - */ - -#if defined ( __ICCARM__ ) - #pragma system_include /* treat file as system include file for MISRA check */ -#elif defined (__clang__) - #pragma clang system_header /* treat file as system include file */ -#endif - -#ifndef __CORE_CM33_H_GENERIC -#define __CORE_CM33_H_GENERIC - -#include - -#ifdef __cplusplus - extern "C" { -#endif - -/** - \page CMSIS_MISRA_Exceptions MISRA-C:2004 Compliance Exceptions - CMSIS violates the following MISRA-C:2004 rules: - - \li Required Rule 8.5, object/function definition in header file.
- Function definitions in header files are used to allow 'inlining'. - - \li Required Rule 18.4, declaration of union type or object of union type: '{...}'.
- Unions are used for effective representation of core registers. - - \li Advisory Rule 19.7, Function-like macro defined.
- Function-like macros are used to allow more efficient code. - */ - - -/******************************************************************************* - * CMSIS definitions - ******************************************************************************/ -/** - \ingroup Cortex_M33 - @{ - */ - -#include "cmsis_version.h" - -/* CMSIS CM33 definitions */ -#define __CM33_CMSIS_VERSION_MAIN (__CM_CMSIS_VERSION_MAIN) /*!< \deprecated [31:16] CMSIS HAL main version */ -#define __CM33_CMSIS_VERSION_SUB (__CM_CMSIS_VERSION_SUB) /*!< \deprecated [15:0] CMSIS HAL sub version */ -#define __CM33_CMSIS_VERSION ((__CM33_CMSIS_VERSION_MAIN << 16U) | \ - __CM33_CMSIS_VERSION_SUB ) /*!< \deprecated CMSIS HAL version number */ - -#define __CORTEX_M (33U) /*!< Cortex-M Core */ - -/** __FPU_USED indicates whether an FPU is used or not. - For this, __FPU_PRESENT has to be checked prior to making use of FPU specific registers and functions. -*/ -#if defined ( __CC_ARM ) - #if defined (__TARGET_FPU_VFP) - #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) - #define __FPU_USED 1U - #else - #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" - #define __FPU_USED 0U - #endif - #else - #define __FPU_USED 0U - #endif - - #if defined (__ARM_FEATURE_DSP) && (__ARM_FEATURE_DSP == 1U) - #if defined (__DSP_PRESENT) && (__DSP_PRESENT == 1U) - #define __DSP_USED 1U - #else - #error "Compiler generates DSP (SIMD) instructions for a devices without DSP extensions (check __DSP_PRESENT)" - #define __DSP_USED 0U - #endif - #else - #define __DSP_USED 0U - #endif - -#elif defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) - #if defined (__ARM_PCS_VFP) - #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) - #define __FPU_USED 1U - #else - #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" - #define __FPU_USED 0U - #endif - #else - #define __FPU_USED 0U - #endif - - #if defined (__ARM_FEATURE_DSP) && (__ARM_FEATURE_DSP == 1U) - #if defined (__DSP_PRESENT) && (__DSP_PRESENT == 1U) - #define __DSP_USED 1U - #else - #error "Compiler generates DSP (SIMD) instructions for a devices without DSP extensions (check __DSP_PRESENT)" - #define __DSP_USED 0U - #endif - #else - #define __DSP_USED 0U - #endif - -#elif defined ( __GNUC__ ) - #if defined (__VFP_FP__) && !defined(__SOFTFP__) - #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) - #define __FPU_USED 1U - #else - #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" - #define __FPU_USED 0U - #endif - #else - #define __FPU_USED 0U - #endif - - #if defined (__ARM_FEATURE_DSP) && (__ARM_FEATURE_DSP == 1U) - #if defined (__DSP_PRESENT) && (__DSP_PRESENT == 1U) - #define __DSP_USED 1U - #else - #error "Compiler generates DSP (SIMD) instructions for a devices without DSP extensions (check __DSP_PRESENT)" - #define __DSP_USED 0U - #endif - #else - #define __DSP_USED 0U - #endif - -#elif defined ( __ICCARM__ ) - #if defined (__ARMVFP__) - #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) - #define __FPU_USED 1U - #else - #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" - #define __FPU_USED 0U - #endif - #else - #define __FPU_USED 0U - #endif - - #if defined (__ARM_FEATURE_DSP) && (__ARM_FEATURE_DSP == 1U) - #if defined (__DSP_PRESENT) && (__DSP_PRESENT == 1U) - #define __DSP_USED 1U - #else - #error "Compiler generates DSP (SIMD) instructions for a devices without DSP extensions (check __DSP_PRESENT)" - #define __DSP_USED 0U - #endif - #else - #define __DSP_USED 0U - #endif - -#elif defined ( __TI_ARM__ ) - #if defined (__TI_VFP_SUPPORT__) - #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) - #define __FPU_USED 1U - #else - #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" - #define __FPU_USED 0U - #endif - #else - #define __FPU_USED 0U - #endif - -#elif defined ( __TASKING__ ) - #if defined (__FPU_VFP__) - #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) - #define __FPU_USED 1U - #else - #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" - #define __FPU_USED 0U - #endif - #else - #define __FPU_USED 0U - #endif - -#elif defined ( __CSMC__ ) - #if ( __CSMC__ & 0x400U) - #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) - #define __FPU_USED 1U - #else - #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" - #define __FPU_USED 0U - #endif - #else - #define __FPU_USED 0U - #endif - -#endif - -#include "cmsis_compiler.h" /* CMSIS compiler specific defines */ - - -#ifdef __cplusplus -} -#endif - -#endif /* __CORE_CM33_H_GENERIC */ - -#ifndef __CMSIS_GENERIC - -#ifndef __CORE_CM33_H_DEPENDANT -#define __CORE_CM33_H_DEPENDANT - -#ifdef __cplusplus - extern "C" { -#endif - -/* check device defines and use defaults */ -#if defined __CHECK_DEVICE_DEFINES - #ifndef __CM33_REV - #define __CM33_REV 0x0000U - #warning "__CM33_REV not defined in device header file; using default!" - #endif - - #ifndef __FPU_PRESENT - #define __FPU_PRESENT 0U - #warning "__FPU_PRESENT not defined in device header file; using default!" - #endif - - #ifndef __MPU_PRESENT - #define __MPU_PRESENT 0U - #warning "__MPU_PRESENT not defined in device header file; using default!" - #endif - - #ifndef __SAUREGION_PRESENT - #define __SAUREGION_PRESENT 0U - #warning "__SAUREGION_PRESENT not defined in device header file; using default!" - #endif - - #ifndef __DSP_PRESENT - #define __DSP_PRESENT 0U - #warning "__DSP_PRESENT not defined in device header file; using default!" - #endif - - #ifndef __NVIC_PRIO_BITS - #define __NVIC_PRIO_BITS 3U - #warning "__NVIC_PRIO_BITS not defined in device header file; using default!" - #endif - - #ifndef __Vendor_SysTickConfig - #define __Vendor_SysTickConfig 0U - #warning "__Vendor_SysTickConfig not defined in device header file; using default!" - #endif -#endif - -/* IO definitions (access restrictions to peripheral registers) */ -/** - \defgroup CMSIS_glob_defs CMSIS Global Defines - - IO Type Qualifiers are used - \li to specify the access to peripheral variables. - \li for automatic generation of peripheral register debug information. -*/ -#ifdef __cplusplus - #define __I volatile /*!< Defines 'read only' permissions */ -#else - #define __I volatile const /*!< Defines 'read only' permissions */ -#endif -#define __O volatile /*!< Defines 'write only' permissions */ -#define __IO volatile /*!< Defines 'read / write' permissions */ - -/* following defines should be used for structure members */ -#define __IM volatile const /*! Defines 'read only' structure member permissions */ -#define __OM volatile /*! Defines 'write only' structure member permissions */ -#define __IOM volatile /*! Defines 'read / write' structure member permissions */ - -/*@} end of group Cortex_M33 */ - - - -/******************************************************************************* - * Register Abstraction - Core Register contain: - - Core Register - - Core NVIC Register - - Core SCB Register - - Core SysTick Register - - Core Debug Register - - Core MPU Register - - Core SAU Register - - Core FPU Register - ******************************************************************************/ -/** - \defgroup CMSIS_core_register Defines and Type Definitions - \brief Type definitions and defines for Cortex-M processor based devices. -*/ - -/** - \ingroup CMSIS_core_register - \defgroup CMSIS_CORE Status and Control Registers - \brief Core Register type definitions. - @{ - */ - -/** - \brief Union type to access the Application Program Status Register (APSR). - */ -typedef union -{ - struct - { - uint32_t _reserved0:16; /*!< bit: 0..15 Reserved */ - uint32_t GE:4; /*!< bit: 16..19 Greater than or Equal flags */ - uint32_t _reserved1:7; /*!< bit: 20..26 Reserved */ - uint32_t Q:1; /*!< bit: 27 Saturation condition flag */ - uint32_t V:1; /*!< bit: 28 Overflow condition code flag */ - uint32_t C:1; /*!< bit: 29 Carry condition code flag */ - uint32_t Z:1; /*!< bit: 30 Zero condition code flag */ - uint32_t N:1; /*!< bit: 31 Negative condition code flag */ - } b; /*!< Structure used for bit access */ - uint32_t w; /*!< Type used for word access */ -} APSR_Type; - -/* APSR Register Definitions */ -#define APSR_N_Pos 31U /*!< APSR: N Position */ -#define APSR_N_Msk (1UL << APSR_N_Pos) /*!< APSR: N Mask */ - -#define APSR_Z_Pos 30U /*!< APSR: Z Position */ -#define APSR_Z_Msk (1UL << APSR_Z_Pos) /*!< APSR: Z Mask */ - -#define APSR_C_Pos 29U /*!< APSR: C Position */ -#define APSR_C_Msk (1UL << APSR_C_Pos) /*!< APSR: C Mask */ - -#define APSR_V_Pos 28U /*!< APSR: V Position */ -#define APSR_V_Msk (1UL << APSR_V_Pos) /*!< APSR: V Mask */ - -#define APSR_Q_Pos 27U /*!< APSR: Q Position */ -#define APSR_Q_Msk (1UL << APSR_Q_Pos) /*!< APSR: Q Mask */ - -#define APSR_GE_Pos 16U /*!< APSR: GE Position */ -#define APSR_GE_Msk (0xFUL << APSR_GE_Pos) /*!< APSR: GE Mask */ - - -/** - \brief Union type to access the Interrupt Program Status Register (IPSR). - */ -typedef union -{ - struct - { - uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */ - uint32_t _reserved0:23; /*!< bit: 9..31 Reserved */ - } b; /*!< Structure used for bit access */ - uint32_t w; /*!< Type used for word access */ -} IPSR_Type; - -/* IPSR Register Definitions */ -#define IPSR_ISR_Pos 0U /*!< IPSR: ISR Position */ -#define IPSR_ISR_Msk (0x1FFUL /*<< IPSR_ISR_Pos*/) /*!< IPSR: ISR Mask */ - - -/** - \brief Union type to access the Special-Purpose Program Status Registers (xPSR). - */ -typedef union -{ - struct - { - uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */ - uint32_t _reserved0:7; /*!< bit: 9..15 Reserved */ - uint32_t GE:4; /*!< bit: 16..19 Greater than or Equal flags */ - uint32_t _reserved1:4; /*!< bit: 20..23 Reserved */ - uint32_t T:1; /*!< bit: 24 Thumb bit (read 0) */ - uint32_t IT:2; /*!< bit: 25..26 saved IT state (read 0) */ - uint32_t Q:1; /*!< bit: 27 Saturation condition flag */ - uint32_t V:1; /*!< bit: 28 Overflow condition code flag */ - uint32_t C:1; /*!< bit: 29 Carry condition code flag */ - uint32_t Z:1; /*!< bit: 30 Zero condition code flag */ - uint32_t N:1; /*!< bit: 31 Negative condition code flag */ - } b; /*!< Structure used for bit access */ - uint32_t w; /*!< Type used for word access */ -} xPSR_Type; - -/* xPSR Register Definitions */ -#define xPSR_N_Pos 31U /*!< xPSR: N Position */ -#define xPSR_N_Msk (1UL << xPSR_N_Pos) /*!< xPSR: N Mask */ - -#define xPSR_Z_Pos 30U /*!< xPSR: Z Position */ -#define xPSR_Z_Msk (1UL << xPSR_Z_Pos) /*!< xPSR: Z Mask */ - -#define xPSR_C_Pos 29U /*!< xPSR: C Position */ -#define xPSR_C_Msk (1UL << xPSR_C_Pos) /*!< xPSR: C Mask */ - -#define xPSR_V_Pos 28U /*!< xPSR: V Position */ -#define xPSR_V_Msk (1UL << xPSR_V_Pos) /*!< xPSR: V Mask */ - -#define xPSR_Q_Pos 27U /*!< xPSR: Q Position */ -#define xPSR_Q_Msk (1UL << xPSR_Q_Pos) /*!< xPSR: Q Mask */ - -#define xPSR_IT_Pos 25U /*!< xPSR: IT Position */ -#define xPSR_IT_Msk (3UL << xPSR_IT_Pos) /*!< xPSR: IT Mask */ - -#define xPSR_T_Pos 24U /*!< xPSR: T Position */ -#define xPSR_T_Msk (1UL << xPSR_T_Pos) /*!< xPSR: T Mask */ - -#define xPSR_GE_Pos 16U /*!< xPSR: GE Position */ -#define xPSR_GE_Msk (0xFUL << xPSR_GE_Pos) /*!< xPSR: GE Mask */ - -#define xPSR_ISR_Pos 0U /*!< xPSR: ISR Position */ -#define xPSR_ISR_Msk (0x1FFUL /*<< xPSR_ISR_Pos*/) /*!< xPSR: ISR Mask */ - - -/** - \brief Union type to access the Control Registers (CONTROL). - */ -typedef union -{ - struct - { - uint32_t nPRIV:1; /*!< bit: 0 Execution privilege in Thread mode */ - uint32_t SPSEL:1; /*!< bit: 1 Stack-pointer select */ - uint32_t FPCA:1; /*!< bit: 2 Floating-point context active */ - uint32_t SFPA:1; /*!< bit: 3 Secure floating-point active */ - uint32_t _reserved1:28; /*!< bit: 4..31 Reserved */ - } b; /*!< Structure used for bit access */ - uint32_t w; /*!< Type used for word access */ -} CONTROL_Type; - -/* CONTROL Register Definitions */ -#define CONTROL_SFPA_Pos 3U /*!< CONTROL: SFPA Position */ -#define CONTROL_SFPA_Msk (1UL << CONTROL_SFPA_Pos) /*!< CONTROL: SFPA Mask */ - -#define CONTROL_FPCA_Pos 2U /*!< CONTROL: FPCA Position */ -#define CONTROL_FPCA_Msk (1UL << CONTROL_FPCA_Pos) /*!< CONTROL: FPCA Mask */ - -#define CONTROL_SPSEL_Pos 1U /*!< CONTROL: SPSEL Position */ -#define CONTROL_SPSEL_Msk (1UL << CONTROL_SPSEL_Pos) /*!< CONTROL: SPSEL Mask */ - -#define CONTROL_nPRIV_Pos 0U /*!< CONTROL: nPRIV Position */ -#define CONTROL_nPRIV_Msk (1UL /*<< CONTROL_nPRIV_Pos*/) /*!< CONTROL: nPRIV Mask */ - -/*@} end of group CMSIS_CORE */ - - -/** - \ingroup CMSIS_core_register - \defgroup CMSIS_NVIC Nested Vectored Interrupt Controller (NVIC) - \brief Type definitions for the NVIC Registers - @{ - */ - -/** - \brief Structure type to access the Nested Vectored Interrupt Controller (NVIC). - */ -typedef struct -{ - __IOM uint32_t ISER[16U]; /*!< Offset: 0x000 (R/W) Interrupt Set Enable Register */ - uint32_t RESERVED0[16U]; - __IOM uint32_t ICER[16U]; /*!< Offset: 0x080 (R/W) Interrupt Clear Enable Register */ - uint32_t RSERVED1[16U]; - __IOM uint32_t ISPR[16U]; /*!< Offset: 0x100 (R/W) Interrupt Set Pending Register */ - uint32_t RESERVED2[16U]; - __IOM uint32_t ICPR[16U]; /*!< Offset: 0x180 (R/W) Interrupt Clear Pending Register */ - uint32_t RESERVED3[16U]; - __IOM uint32_t IABR[16U]; /*!< Offset: 0x200 (R/W) Interrupt Active bit Register */ - uint32_t RESERVED4[16U]; - __IOM uint32_t ITNS[16U]; /*!< Offset: 0x280 (R/W) Interrupt Non-Secure State Register */ - uint32_t RESERVED5[16U]; - __IOM uint8_t IPR[496U]; /*!< Offset: 0x300 (R/W) Interrupt Priority Register (8Bit wide) */ - uint32_t RESERVED6[580U]; - __OM uint32_t STIR; /*!< Offset: 0xE00 ( /W) Software Trigger Interrupt Register */ -} NVIC_Type; - -/* Software Triggered Interrupt Register Definitions */ -#define NVIC_STIR_INTID_Pos 0U /*!< STIR: INTLINESNUM Position */ -#define NVIC_STIR_INTID_Msk (0x1FFUL /*<< NVIC_STIR_INTID_Pos*/) /*!< STIR: INTLINESNUM Mask */ - -/*@} end of group CMSIS_NVIC */ - - -/** - \ingroup CMSIS_core_register - \defgroup CMSIS_SCB System Control Block (SCB) - \brief Type definitions for the System Control Block Registers - @{ - */ - -/** - \brief Structure type to access the System Control Block (SCB). - */ -typedef struct -{ - __IM uint32_t CPUID; /*!< Offset: 0x000 (R/ ) CPUID Base Register */ - __IOM uint32_t ICSR; /*!< Offset: 0x004 (R/W) Interrupt Control and State Register */ - __IOM uint32_t VTOR; /*!< Offset: 0x008 (R/W) Vector Table Offset Register */ - __IOM uint32_t AIRCR; /*!< Offset: 0x00C (R/W) Application Interrupt and Reset Control Register */ - __IOM uint32_t SCR; /*!< Offset: 0x010 (R/W) System Control Register */ - __IOM uint32_t CCR; /*!< Offset: 0x014 (R/W) Configuration Control Register */ - __IOM uint8_t SHPR[12U]; /*!< Offset: 0x018 (R/W) System Handlers Priority Registers (4-7, 8-11, 12-15) */ - __IOM uint32_t SHCSR; /*!< Offset: 0x024 (R/W) System Handler Control and State Register */ - __IOM uint32_t CFSR; /*!< Offset: 0x028 (R/W) Configurable Fault Status Register */ - __IOM uint32_t HFSR; /*!< Offset: 0x02C (R/W) HardFault Status Register */ - __IOM uint32_t DFSR; /*!< Offset: 0x030 (R/W) Debug Fault Status Register */ - __IOM uint32_t MMFAR; /*!< Offset: 0x034 (R/W) MemManage Fault Address Register */ - __IOM uint32_t BFAR; /*!< Offset: 0x038 (R/W) BusFault Address Register */ - __IOM uint32_t AFSR; /*!< Offset: 0x03C (R/W) Auxiliary Fault Status Register */ - __IM uint32_t ID_PFR[2U]; /*!< Offset: 0x040 (R/ ) Processor Feature Register */ - __IM uint32_t ID_DFR; /*!< Offset: 0x048 (R/ ) Debug Feature Register */ - __IM uint32_t ID_ADR; /*!< Offset: 0x04C (R/ ) Auxiliary Feature Register */ - __IM uint32_t ID_MMFR[4U]; /*!< Offset: 0x050 (R/ ) Memory Model Feature Register */ - __IM uint32_t ID_ISAR[6U]; /*!< Offset: 0x060 (R/ ) Instruction Set Attributes Register */ - __IM uint32_t CLIDR; /*!< Offset: 0x078 (R/ ) Cache Level ID register */ - __IM uint32_t CTR; /*!< Offset: 0x07C (R/ ) Cache Type register */ - __IM uint32_t CCSIDR; /*!< Offset: 0x080 (R/ ) Cache Size ID Register */ - __IOM uint32_t CSSELR; /*!< Offset: 0x084 (R/W) Cache Size Selection Register */ - __IOM uint32_t CPACR; /*!< Offset: 0x088 (R/W) Coprocessor Access Control Register */ - __IOM uint32_t NSACR; /*!< Offset: 0x08C (R/W) Non-Secure Access Control Register */ - uint32_t RESERVED3[92U]; - __OM uint32_t STIR; /*!< Offset: 0x200 ( /W) Software Triggered Interrupt Register */ - uint32_t RESERVED4[15U]; - __IM uint32_t MVFR0; /*!< Offset: 0x240 (R/ ) Media and VFP Feature Register 0 */ - __IM uint32_t MVFR1; /*!< Offset: 0x244 (R/ ) Media and VFP Feature Register 1 */ - __IM uint32_t MVFR2; /*!< Offset: 0x248 (R/ ) Media and VFP Feature Register 2 */ - uint32_t RESERVED5[1U]; - __OM uint32_t ICIALLU; /*!< Offset: 0x250 ( /W) I-Cache Invalidate All to PoU */ - uint32_t RESERVED6[1U]; - __OM uint32_t ICIMVAU; /*!< Offset: 0x258 ( /W) I-Cache Invalidate by MVA to PoU */ - __OM uint32_t DCIMVAC; /*!< Offset: 0x25C ( /W) D-Cache Invalidate by MVA to PoC */ - __OM uint32_t DCISW; /*!< Offset: 0x260 ( /W) D-Cache Invalidate by Set-way */ - __OM uint32_t DCCMVAU; /*!< Offset: 0x264 ( /W) D-Cache Clean by MVA to PoU */ - __OM uint32_t DCCMVAC; /*!< Offset: 0x268 ( /W) D-Cache Clean by MVA to PoC */ - __OM uint32_t DCCSW; /*!< Offset: 0x26C ( /W) D-Cache Clean by Set-way */ - __OM uint32_t DCCIMVAC; /*!< Offset: 0x270 ( /W) D-Cache Clean and Invalidate by MVA to PoC */ - __OM uint32_t DCCISW; /*!< Offset: 0x274 ( /W) D-Cache Clean and Invalidate by Set-way */ - uint32_t RESERVED7[6U]; - __IOM uint32_t ITCMCR; /*!< Offset: 0x290 (R/W) Instruction Tightly-Coupled Memory Control Register */ - __IOM uint32_t DTCMCR; /*!< Offset: 0x294 (R/W) Data Tightly-Coupled Memory Control Registers */ - __IOM uint32_t AHBPCR; /*!< Offset: 0x298 (R/W) AHBP Control Register */ - __IOM uint32_t CACR; /*!< Offset: 0x29C (R/W) L1 Cache Control Register */ - __IOM uint32_t AHBSCR; /*!< Offset: 0x2A0 (R/W) AHB Slave Control Register */ - uint32_t RESERVED8[1U]; - __IOM uint32_t ABFSR; /*!< Offset: 0x2A8 (R/W) Auxiliary Bus Fault Status Register */ -} SCB_Type; - -/* SCB CPUID Register Definitions */ -#define SCB_CPUID_IMPLEMENTER_Pos 24U /*!< SCB CPUID: IMPLEMENTER Position */ -#define SCB_CPUID_IMPLEMENTER_Msk (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos) /*!< SCB CPUID: IMPLEMENTER Mask */ - -#define SCB_CPUID_VARIANT_Pos 20U /*!< SCB CPUID: VARIANT Position */ -#define SCB_CPUID_VARIANT_Msk (0xFUL << SCB_CPUID_VARIANT_Pos) /*!< SCB CPUID: VARIANT Mask */ - -#define SCB_CPUID_ARCHITECTURE_Pos 16U /*!< SCB CPUID: ARCHITECTURE Position */ -#define SCB_CPUID_ARCHITECTURE_Msk (0xFUL << SCB_CPUID_ARCHITECTURE_Pos) /*!< SCB CPUID: ARCHITECTURE Mask */ - -#define SCB_CPUID_PARTNO_Pos 4U /*!< SCB CPUID: PARTNO Position */ -#define SCB_CPUID_PARTNO_Msk (0xFFFUL << SCB_CPUID_PARTNO_Pos) /*!< SCB CPUID: PARTNO Mask */ - -#define SCB_CPUID_REVISION_Pos 0U /*!< SCB CPUID: REVISION Position */ -#define SCB_CPUID_REVISION_Msk (0xFUL /*<< SCB_CPUID_REVISION_Pos*/) /*!< SCB CPUID: REVISION Mask */ - -/* SCB Interrupt Control State Register Definitions */ -#define SCB_ICSR_PENDNMISET_Pos 31U /*!< SCB ICSR: PENDNMISET Position */ -#define SCB_ICSR_PENDNMISET_Msk (1UL << SCB_ICSR_PENDNMISET_Pos) /*!< SCB ICSR: PENDNMISET Mask */ - -#define SCB_ICSR_PENDNMICLR_Pos 30U /*!< SCB ICSR: PENDNMICLR Position */ -#define SCB_ICSR_PENDNMICLR_Msk (1UL << SCB_ICSR_PENDNMICLR_Pos) /*!< SCB ICSR: PENDNMICLR Mask */ - -#define SCB_ICSR_PENDSVSET_Pos 28U /*!< SCB ICSR: PENDSVSET Position */ -#define SCB_ICSR_PENDSVSET_Msk (1UL << SCB_ICSR_PENDSVSET_Pos) /*!< SCB ICSR: PENDSVSET Mask */ - -#define SCB_ICSR_PENDSVCLR_Pos 27U /*!< SCB ICSR: PENDSVCLR Position */ -#define SCB_ICSR_PENDSVCLR_Msk (1UL << SCB_ICSR_PENDSVCLR_Pos) /*!< SCB ICSR: PENDSVCLR Mask */ - -#define SCB_ICSR_PENDSTSET_Pos 26U /*!< SCB ICSR: PENDSTSET Position */ -#define SCB_ICSR_PENDSTSET_Msk (1UL << SCB_ICSR_PENDSTSET_Pos) /*!< SCB ICSR: PENDSTSET Mask */ - -#define SCB_ICSR_PENDSTCLR_Pos 25U /*!< SCB ICSR: PENDSTCLR Position */ -#define SCB_ICSR_PENDSTCLR_Msk (1UL << SCB_ICSR_PENDSTCLR_Pos) /*!< SCB ICSR: PENDSTCLR Mask */ - -#define SCB_ICSR_STTNS_Pos 24U /*!< SCB ICSR: STTNS Position (Security Extension) */ -#define SCB_ICSR_STTNS_Msk (1UL << SCB_ICSR_STTNS_Pos) /*!< SCB ICSR: STTNS Mask (Security Extension) */ - -#define SCB_ICSR_ISRPREEMPT_Pos 23U /*!< SCB ICSR: ISRPREEMPT Position */ -#define SCB_ICSR_ISRPREEMPT_Msk (1UL << SCB_ICSR_ISRPREEMPT_Pos) /*!< SCB ICSR: ISRPREEMPT Mask */ - -#define SCB_ICSR_ISRPENDING_Pos 22U /*!< SCB ICSR: ISRPENDING Position */ -#define SCB_ICSR_ISRPENDING_Msk (1UL << SCB_ICSR_ISRPENDING_Pos) /*!< SCB ICSR: ISRPENDING Mask */ - -#define SCB_ICSR_VECTPENDING_Pos 12U /*!< SCB ICSR: VECTPENDING Position */ -#define SCB_ICSR_VECTPENDING_Msk (0x1FFUL << SCB_ICSR_VECTPENDING_Pos) /*!< SCB ICSR: VECTPENDING Mask */ - -#define SCB_ICSR_RETTOBASE_Pos 11U /*!< SCB ICSR: RETTOBASE Position */ -#define SCB_ICSR_RETTOBASE_Msk (1UL << SCB_ICSR_RETTOBASE_Pos) /*!< SCB ICSR: RETTOBASE Mask */ - -#define SCB_ICSR_VECTACTIVE_Pos 0U /*!< SCB ICSR: VECTACTIVE Position */ -#define SCB_ICSR_VECTACTIVE_Msk (0x1FFUL /*<< SCB_ICSR_VECTACTIVE_Pos*/) /*!< SCB ICSR: VECTACTIVE Mask */ - -/* SCB Vector Table Offset Register Definitions */ -#define SCB_VTOR_TBLOFF_Pos 7U /*!< SCB VTOR: TBLOFF Position */ -#define SCB_VTOR_TBLOFF_Msk (0x1FFFFFFUL << SCB_VTOR_TBLOFF_Pos) /*!< SCB VTOR: TBLOFF Mask */ - -/* SCB Application Interrupt and Reset Control Register Definitions */ -#define SCB_AIRCR_VECTKEY_Pos 16U /*!< SCB AIRCR: VECTKEY Position */ -#define SCB_AIRCR_VECTKEY_Msk (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos) /*!< SCB AIRCR: VECTKEY Mask */ - -#define SCB_AIRCR_VECTKEYSTAT_Pos 16U /*!< SCB AIRCR: VECTKEYSTAT Position */ -#define SCB_AIRCR_VECTKEYSTAT_Msk (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos) /*!< SCB AIRCR: VECTKEYSTAT Mask */ - -#define SCB_AIRCR_ENDIANESS_Pos 15U /*!< SCB AIRCR: ENDIANESS Position */ -#define SCB_AIRCR_ENDIANESS_Msk (1UL << SCB_AIRCR_ENDIANESS_Pos) /*!< SCB AIRCR: ENDIANESS Mask */ - -#define SCB_AIRCR_PRIS_Pos 14U /*!< SCB AIRCR: PRIS Position */ -#define SCB_AIRCR_PRIS_Msk (1UL << SCB_AIRCR_PRIS_Pos) /*!< SCB AIRCR: PRIS Mask */ - -#define SCB_AIRCR_BFHFNMINS_Pos 13U /*!< SCB AIRCR: BFHFNMINS Position */ -#define SCB_AIRCR_BFHFNMINS_Msk (1UL << SCB_AIRCR_BFHFNMINS_Pos) /*!< SCB AIRCR: BFHFNMINS Mask */ - -#define SCB_AIRCR_PRIGROUP_Pos 8U /*!< SCB AIRCR: PRIGROUP Position */ -#define SCB_AIRCR_PRIGROUP_Msk (7UL << SCB_AIRCR_PRIGROUP_Pos) /*!< SCB AIRCR: PRIGROUP Mask */ - -#define SCB_AIRCR_SYSRESETREQS_Pos 3U /*!< SCB AIRCR: SYSRESETREQS Position */ -#define SCB_AIRCR_SYSRESETREQS_Msk (1UL << SCB_AIRCR_SYSRESETREQS_Pos) /*!< SCB AIRCR: SYSRESETREQS Mask */ - -#define SCB_AIRCR_SYSRESETREQ_Pos 2U /*!< SCB AIRCR: SYSRESETREQ Position */ -#define SCB_AIRCR_SYSRESETREQ_Msk (1UL << SCB_AIRCR_SYSRESETREQ_Pos) /*!< SCB AIRCR: SYSRESETREQ Mask */ - -#define SCB_AIRCR_VECTCLRACTIVE_Pos 1U /*!< SCB AIRCR: VECTCLRACTIVE Position */ -#define SCB_AIRCR_VECTCLRACTIVE_Msk (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos) /*!< SCB AIRCR: VECTCLRACTIVE Mask */ - -/* SCB System Control Register Definitions */ -#define SCB_SCR_SEVONPEND_Pos 4U /*!< SCB SCR: SEVONPEND Position */ -#define SCB_SCR_SEVONPEND_Msk (1UL << SCB_SCR_SEVONPEND_Pos) /*!< SCB SCR: SEVONPEND Mask */ - -#define SCB_SCR_SLEEPDEEPS_Pos 3U /*!< SCB SCR: SLEEPDEEPS Position */ -#define SCB_SCR_SLEEPDEEPS_Msk (1UL << SCB_SCR_SLEEPDEEPS_Pos) /*!< SCB SCR: SLEEPDEEPS Mask */ - -#define SCB_SCR_SLEEPDEEP_Pos 2U /*!< SCB SCR: SLEEPDEEP Position */ -#define SCB_SCR_SLEEPDEEP_Msk (1UL << SCB_SCR_SLEEPDEEP_Pos) /*!< SCB SCR: SLEEPDEEP Mask */ - -#define SCB_SCR_SLEEPONEXIT_Pos 1U /*!< SCB SCR: SLEEPONEXIT Position */ -#define SCB_SCR_SLEEPONEXIT_Msk (1UL << SCB_SCR_SLEEPONEXIT_Pos) /*!< SCB SCR: SLEEPONEXIT Mask */ - -/* SCB Configuration Control Register Definitions */ -#define SCB_CCR_BP_Pos 18U /*!< SCB CCR: BP Position */ -#define SCB_CCR_BP_Msk (1UL << SCB_CCR_BP_Pos) /*!< SCB CCR: BP Mask */ - -#define SCB_CCR_IC_Pos 17U /*!< SCB CCR: IC Position */ -#define SCB_CCR_IC_Msk (1UL << SCB_CCR_IC_Pos) /*!< SCB CCR: IC Mask */ - -#define SCB_CCR_DC_Pos 16U /*!< SCB CCR: DC Position */ -#define SCB_CCR_DC_Msk (1UL << SCB_CCR_DC_Pos) /*!< SCB CCR: DC Mask */ - -#define SCB_CCR_STKOFHFNMIGN_Pos 10U /*!< SCB CCR: STKOFHFNMIGN Position */ -#define SCB_CCR_STKOFHFNMIGN_Msk (1UL << SCB_CCR_STKOFHFNMIGN_Pos) /*!< SCB CCR: STKOFHFNMIGN Mask */ - -#define SCB_CCR_BFHFNMIGN_Pos 8U /*!< SCB CCR: BFHFNMIGN Position */ -#define SCB_CCR_BFHFNMIGN_Msk (1UL << SCB_CCR_BFHFNMIGN_Pos) /*!< SCB CCR: BFHFNMIGN Mask */ - -#define SCB_CCR_DIV_0_TRP_Pos 4U /*!< SCB CCR: DIV_0_TRP Position */ -#define SCB_CCR_DIV_0_TRP_Msk (1UL << SCB_CCR_DIV_0_TRP_Pos) /*!< SCB CCR: DIV_0_TRP Mask */ - -#define SCB_CCR_UNALIGN_TRP_Pos 3U /*!< SCB CCR: UNALIGN_TRP Position */ -#define SCB_CCR_UNALIGN_TRP_Msk (1UL << SCB_CCR_UNALIGN_TRP_Pos) /*!< SCB CCR: UNALIGN_TRP Mask */ - -#define SCB_CCR_USERSETMPEND_Pos 1U /*!< SCB CCR: USERSETMPEND Position */ -#define SCB_CCR_USERSETMPEND_Msk (1UL << SCB_CCR_USERSETMPEND_Pos) /*!< SCB CCR: USERSETMPEND Mask */ - -/* SCB System Handler Control and State Register Definitions */ -#define SCB_SHCSR_HARDFAULTPENDED_Pos 21U /*!< SCB SHCSR: HARDFAULTPENDED Position */ -#define SCB_SHCSR_HARDFAULTPENDED_Msk (1UL << SCB_SHCSR_HARDFAULTPENDED_Pos) /*!< SCB SHCSR: HARDFAULTPENDED Mask */ - -#define SCB_SHCSR_SECUREFAULTPENDED_Pos 20U /*!< SCB SHCSR: SECUREFAULTPENDED Position */ -#define SCB_SHCSR_SECUREFAULTPENDED_Msk (1UL << SCB_SHCSR_SECUREFAULTPENDED_Pos) /*!< SCB SHCSR: SECUREFAULTPENDED Mask */ - -#define SCB_SHCSR_SECUREFAULTENA_Pos 19U /*!< SCB SHCSR: SECUREFAULTENA Position */ -#define SCB_SHCSR_SECUREFAULTENA_Msk (1UL << SCB_SHCSR_SECUREFAULTENA_Pos) /*!< SCB SHCSR: SECUREFAULTENA Mask */ - -#define SCB_SHCSR_USGFAULTENA_Pos 18U /*!< SCB SHCSR: USGFAULTENA Position */ -#define SCB_SHCSR_USGFAULTENA_Msk (1UL << SCB_SHCSR_USGFAULTENA_Pos) /*!< SCB SHCSR: USGFAULTENA Mask */ - -#define SCB_SHCSR_BUSFAULTENA_Pos 17U /*!< SCB SHCSR: BUSFAULTENA Position */ -#define SCB_SHCSR_BUSFAULTENA_Msk (1UL << SCB_SHCSR_BUSFAULTENA_Pos) /*!< SCB SHCSR: BUSFAULTENA Mask */ - -#define SCB_SHCSR_MEMFAULTENA_Pos 16U /*!< SCB SHCSR: MEMFAULTENA Position */ -#define SCB_SHCSR_MEMFAULTENA_Msk (1UL << SCB_SHCSR_MEMFAULTENA_Pos) /*!< SCB SHCSR: MEMFAULTENA Mask */ - -#define SCB_SHCSR_SVCALLPENDED_Pos 15U /*!< SCB SHCSR: SVCALLPENDED Position */ -#define SCB_SHCSR_SVCALLPENDED_Msk (1UL << SCB_SHCSR_SVCALLPENDED_Pos) /*!< SCB SHCSR: SVCALLPENDED Mask */ - -#define SCB_SHCSR_BUSFAULTPENDED_Pos 14U /*!< SCB SHCSR: BUSFAULTPENDED Position */ -#define SCB_SHCSR_BUSFAULTPENDED_Msk (1UL << SCB_SHCSR_BUSFAULTPENDED_Pos) /*!< SCB SHCSR: BUSFAULTPENDED Mask */ - -#define SCB_SHCSR_MEMFAULTPENDED_Pos 13U /*!< SCB SHCSR: MEMFAULTPENDED Position */ -#define SCB_SHCSR_MEMFAULTPENDED_Msk (1UL << SCB_SHCSR_MEMFAULTPENDED_Pos) /*!< SCB SHCSR: MEMFAULTPENDED Mask */ - -#define SCB_SHCSR_USGFAULTPENDED_Pos 12U /*!< SCB SHCSR: USGFAULTPENDED Position */ -#define SCB_SHCSR_USGFAULTPENDED_Msk (1UL << SCB_SHCSR_USGFAULTPENDED_Pos) /*!< SCB SHCSR: USGFAULTPENDED Mask */ - -#define SCB_SHCSR_SYSTICKACT_Pos 11U /*!< SCB SHCSR: SYSTICKACT Position */ -#define SCB_SHCSR_SYSTICKACT_Msk (1UL << SCB_SHCSR_SYSTICKACT_Pos) /*!< SCB SHCSR: SYSTICKACT Mask */ - -#define SCB_SHCSR_PENDSVACT_Pos 10U /*!< SCB SHCSR: PENDSVACT Position */ -#define SCB_SHCSR_PENDSVACT_Msk (1UL << SCB_SHCSR_PENDSVACT_Pos) /*!< SCB SHCSR: PENDSVACT Mask */ - -#define SCB_SHCSR_MONITORACT_Pos 8U /*!< SCB SHCSR: MONITORACT Position */ -#define SCB_SHCSR_MONITORACT_Msk (1UL << SCB_SHCSR_MONITORACT_Pos) /*!< SCB SHCSR: MONITORACT Mask */ - -#define SCB_SHCSR_SVCALLACT_Pos 7U /*!< SCB SHCSR: SVCALLACT Position */ -#define SCB_SHCSR_SVCALLACT_Msk (1UL << SCB_SHCSR_SVCALLACT_Pos) /*!< SCB SHCSR: SVCALLACT Mask */ - -#define SCB_SHCSR_NMIACT_Pos 5U /*!< SCB SHCSR: NMIACT Position */ -#define SCB_SHCSR_NMIACT_Msk (1UL << SCB_SHCSR_NMIACT_Pos) /*!< SCB SHCSR: NMIACT Mask */ - -#define SCB_SHCSR_SECUREFAULTACT_Pos 4U /*!< SCB SHCSR: SECUREFAULTACT Position */ -#define SCB_SHCSR_SECUREFAULTACT_Msk (1UL << SCB_SHCSR_SECUREFAULTACT_Pos) /*!< SCB SHCSR: SECUREFAULTACT Mask */ - -#define SCB_SHCSR_USGFAULTACT_Pos 3U /*!< SCB SHCSR: USGFAULTACT Position */ -#define SCB_SHCSR_USGFAULTACT_Msk (1UL << SCB_SHCSR_USGFAULTACT_Pos) /*!< SCB SHCSR: USGFAULTACT Mask */ - -#define SCB_SHCSR_HARDFAULTACT_Pos 2U /*!< SCB SHCSR: HARDFAULTACT Position */ -#define SCB_SHCSR_HARDFAULTACT_Msk (1UL << SCB_SHCSR_HARDFAULTACT_Pos) /*!< SCB SHCSR: HARDFAULTACT Mask */ - -#define SCB_SHCSR_BUSFAULTACT_Pos 1U /*!< SCB SHCSR: BUSFAULTACT Position */ -#define SCB_SHCSR_BUSFAULTACT_Msk (1UL << SCB_SHCSR_BUSFAULTACT_Pos) /*!< SCB SHCSR: BUSFAULTACT Mask */ - -#define SCB_SHCSR_MEMFAULTACT_Pos 0U /*!< SCB SHCSR: MEMFAULTACT Position */ -#define SCB_SHCSR_MEMFAULTACT_Msk (1UL /*<< SCB_SHCSR_MEMFAULTACT_Pos*/) /*!< SCB SHCSR: MEMFAULTACT Mask */ - -/* SCB Configurable Fault Status Register Definitions */ -#define SCB_CFSR_USGFAULTSR_Pos 16U /*!< SCB CFSR: Usage Fault Status Register Position */ -#define SCB_CFSR_USGFAULTSR_Msk (0xFFFFUL << SCB_CFSR_USGFAULTSR_Pos) /*!< SCB CFSR: Usage Fault Status Register Mask */ - -#define SCB_CFSR_BUSFAULTSR_Pos 8U /*!< SCB CFSR: Bus Fault Status Register Position */ -#define SCB_CFSR_BUSFAULTSR_Msk (0xFFUL << SCB_CFSR_BUSFAULTSR_Pos) /*!< SCB CFSR: Bus Fault Status Register Mask */ - -#define SCB_CFSR_MEMFAULTSR_Pos 0U /*!< SCB CFSR: Memory Manage Fault Status Register Position */ -#define SCB_CFSR_MEMFAULTSR_Msk (0xFFUL /*<< SCB_CFSR_MEMFAULTSR_Pos*/) /*!< SCB CFSR: Memory Manage Fault Status Register Mask */ - -/* MemManage Fault Status Register (part of SCB Configurable Fault Status Register) */ -#define SCB_CFSR_MMARVALID_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 7U) /*!< SCB CFSR (MMFSR): MMARVALID Position */ -#define SCB_CFSR_MMARVALID_Msk (1UL << SCB_CFSR_MMARVALID_Pos) /*!< SCB CFSR (MMFSR): MMARVALID Mask */ - -#define SCB_CFSR_MLSPERR_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 5U) /*!< SCB CFSR (MMFSR): MLSPERR Position */ -#define SCB_CFSR_MLSPERR_Msk (1UL << SCB_CFSR_MLSPERR_Pos) /*!< SCB CFSR (MMFSR): MLSPERR Mask */ - -#define SCB_CFSR_MSTKERR_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 4U) /*!< SCB CFSR (MMFSR): MSTKERR Position */ -#define SCB_CFSR_MSTKERR_Msk (1UL << SCB_CFSR_MSTKERR_Pos) /*!< SCB CFSR (MMFSR): MSTKERR Mask */ - -#define SCB_CFSR_MUNSTKERR_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 3U) /*!< SCB CFSR (MMFSR): MUNSTKERR Position */ -#define SCB_CFSR_MUNSTKERR_Msk (1UL << SCB_CFSR_MUNSTKERR_Pos) /*!< SCB CFSR (MMFSR): MUNSTKERR Mask */ - -#define SCB_CFSR_DACCVIOL_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 1U) /*!< SCB CFSR (MMFSR): DACCVIOL Position */ -#define SCB_CFSR_DACCVIOL_Msk (1UL << SCB_CFSR_DACCVIOL_Pos) /*!< SCB CFSR (MMFSR): DACCVIOL Mask */ - -#define SCB_CFSR_IACCVIOL_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 0U) /*!< SCB CFSR (MMFSR): IACCVIOL Position */ -#define SCB_CFSR_IACCVIOL_Msk (1UL /*<< SCB_CFSR_IACCVIOL_Pos*/) /*!< SCB CFSR (MMFSR): IACCVIOL Mask */ - -/* BusFault Status Register (part of SCB Configurable Fault Status Register) */ -#define SCB_CFSR_BFARVALID_Pos (SCB_CFSR_BUSFAULTSR_Pos + 7U) /*!< SCB CFSR (BFSR): BFARVALID Position */ -#define SCB_CFSR_BFARVALID_Msk (1UL << SCB_CFSR_BFARVALID_Pos) /*!< SCB CFSR (BFSR): BFARVALID Mask */ - -#define SCB_CFSR_LSPERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 5U) /*!< SCB CFSR (BFSR): LSPERR Position */ -#define SCB_CFSR_LSPERR_Msk (1UL << SCB_CFSR_LSPERR_Pos) /*!< SCB CFSR (BFSR): LSPERR Mask */ - -#define SCB_CFSR_STKERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 4U) /*!< SCB CFSR (BFSR): STKERR Position */ -#define SCB_CFSR_STKERR_Msk (1UL << SCB_CFSR_STKERR_Pos) /*!< SCB CFSR (BFSR): STKERR Mask */ - -#define SCB_CFSR_UNSTKERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 3U) /*!< SCB CFSR (BFSR): UNSTKERR Position */ -#define SCB_CFSR_UNSTKERR_Msk (1UL << SCB_CFSR_UNSTKERR_Pos) /*!< SCB CFSR (BFSR): UNSTKERR Mask */ - -#define SCB_CFSR_IMPRECISERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 2U) /*!< SCB CFSR (BFSR): IMPRECISERR Position */ -#define SCB_CFSR_IMPRECISERR_Msk (1UL << SCB_CFSR_IMPRECISERR_Pos) /*!< SCB CFSR (BFSR): IMPRECISERR Mask */ - -#define SCB_CFSR_PRECISERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 1U) /*!< SCB CFSR (BFSR): PRECISERR Position */ -#define SCB_CFSR_PRECISERR_Msk (1UL << SCB_CFSR_PRECISERR_Pos) /*!< SCB CFSR (BFSR): PRECISERR Mask */ - -#define SCB_CFSR_IBUSERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 0U) /*!< SCB CFSR (BFSR): IBUSERR Position */ -#define SCB_CFSR_IBUSERR_Msk (1UL << SCB_CFSR_IBUSERR_Pos) /*!< SCB CFSR (BFSR): IBUSERR Mask */ - -/* UsageFault Status Register (part of SCB Configurable Fault Status Register) */ -#define SCB_CFSR_DIVBYZERO_Pos (SCB_CFSR_USGFAULTSR_Pos + 9U) /*!< SCB CFSR (UFSR): DIVBYZERO Position */ -#define SCB_CFSR_DIVBYZERO_Msk (1UL << SCB_CFSR_DIVBYZERO_Pos) /*!< SCB CFSR (UFSR): DIVBYZERO Mask */ - -#define SCB_CFSR_UNALIGNED_Pos (SCB_CFSR_USGFAULTSR_Pos + 8U) /*!< SCB CFSR (UFSR): UNALIGNED Position */ -#define SCB_CFSR_UNALIGNED_Msk (1UL << SCB_CFSR_UNALIGNED_Pos) /*!< SCB CFSR (UFSR): UNALIGNED Mask */ - -#define SCB_CFSR_STKOF_Pos (SCB_CFSR_USGFAULTSR_Pos + 4U) /*!< SCB CFSR (UFSR): STKOF Position */ -#define SCB_CFSR_STKOF_Msk (1UL << SCB_CFSR_STKOF_Pos) /*!< SCB CFSR (UFSR): STKOF Mask */ - -#define SCB_CFSR_NOCP_Pos (SCB_CFSR_USGFAULTSR_Pos + 3U) /*!< SCB CFSR (UFSR): NOCP Position */ -#define SCB_CFSR_NOCP_Msk (1UL << SCB_CFSR_NOCP_Pos) /*!< SCB CFSR (UFSR): NOCP Mask */ - -#define SCB_CFSR_INVPC_Pos (SCB_CFSR_USGFAULTSR_Pos + 2U) /*!< SCB CFSR (UFSR): INVPC Position */ -#define SCB_CFSR_INVPC_Msk (1UL << SCB_CFSR_INVPC_Pos) /*!< SCB CFSR (UFSR): INVPC Mask */ - -#define SCB_CFSR_INVSTATE_Pos (SCB_CFSR_USGFAULTSR_Pos + 1U) /*!< SCB CFSR (UFSR): INVSTATE Position */ -#define SCB_CFSR_INVSTATE_Msk (1UL << SCB_CFSR_INVSTATE_Pos) /*!< SCB CFSR (UFSR): INVSTATE Mask */ - -#define SCB_CFSR_UNDEFINSTR_Pos (SCB_CFSR_USGFAULTSR_Pos + 0U) /*!< SCB CFSR (UFSR): UNDEFINSTR Position */ -#define SCB_CFSR_UNDEFINSTR_Msk (1UL << SCB_CFSR_UNDEFINSTR_Pos) /*!< SCB CFSR (UFSR): UNDEFINSTR Mask */ - -/* SCB Hard Fault Status Register Definitions */ -#define SCB_HFSR_DEBUGEVT_Pos 31U /*!< SCB HFSR: DEBUGEVT Position */ -#define SCB_HFSR_DEBUGEVT_Msk (1UL << SCB_HFSR_DEBUGEVT_Pos) /*!< SCB HFSR: DEBUGEVT Mask */ - -#define SCB_HFSR_FORCED_Pos 30U /*!< SCB HFSR: FORCED Position */ -#define SCB_HFSR_FORCED_Msk (1UL << SCB_HFSR_FORCED_Pos) /*!< SCB HFSR: FORCED Mask */ - -#define SCB_HFSR_VECTTBL_Pos 1U /*!< SCB HFSR: VECTTBL Position */ -#define SCB_HFSR_VECTTBL_Msk (1UL << SCB_HFSR_VECTTBL_Pos) /*!< SCB HFSR: VECTTBL Mask */ - -/* SCB Debug Fault Status Register Definitions */ -#define SCB_DFSR_EXTERNAL_Pos 4U /*!< SCB DFSR: EXTERNAL Position */ -#define SCB_DFSR_EXTERNAL_Msk (1UL << SCB_DFSR_EXTERNAL_Pos) /*!< SCB DFSR: EXTERNAL Mask */ - -#define SCB_DFSR_VCATCH_Pos 3U /*!< SCB DFSR: VCATCH Position */ -#define SCB_DFSR_VCATCH_Msk (1UL << SCB_DFSR_VCATCH_Pos) /*!< SCB DFSR: VCATCH Mask */ - -#define SCB_DFSR_DWTTRAP_Pos 2U /*!< SCB DFSR: DWTTRAP Position */ -#define SCB_DFSR_DWTTRAP_Msk (1UL << SCB_DFSR_DWTTRAP_Pos) /*!< SCB DFSR: DWTTRAP Mask */ - -#define SCB_DFSR_BKPT_Pos 1U /*!< SCB DFSR: BKPT Position */ -#define SCB_DFSR_BKPT_Msk (1UL << SCB_DFSR_BKPT_Pos) /*!< SCB DFSR: BKPT Mask */ - -#define SCB_DFSR_HALTED_Pos 0U /*!< SCB DFSR: HALTED Position */ -#define SCB_DFSR_HALTED_Msk (1UL /*<< SCB_DFSR_HALTED_Pos*/) /*!< SCB DFSR: HALTED Mask */ - -/* SCB Non-Secure Access Control Register Definitions */ -#define SCB_NSACR_CP11_Pos 11U /*!< SCB NSACR: CP11 Position */ -#define SCB_NSACR_CP11_Msk (1UL << SCB_NSACR_CP11_Pos) /*!< SCB NSACR: CP11 Mask */ - -#define SCB_NSACR_CP10_Pos 10U /*!< SCB NSACR: CP10 Position */ -#define SCB_NSACR_CP10_Msk (1UL << SCB_NSACR_CP10_Pos) /*!< SCB NSACR: CP10 Mask */ - -#define SCB_NSACR_CPn_Pos 0U /*!< SCB NSACR: CPn Position */ -#define SCB_NSACR_CPn_Msk (1UL /*<< SCB_NSACR_CPn_Pos*/) /*!< SCB NSACR: CPn Mask */ - -/* SCB Cache Level ID Register Definitions */ -#define SCB_CLIDR_LOUU_Pos 27U /*!< SCB CLIDR: LoUU Position */ -#define SCB_CLIDR_LOUU_Msk (7UL << SCB_CLIDR_LOUU_Pos) /*!< SCB CLIDR: LoUU Mask */ - -#define SCB_CLIDR_LOC_Pos 24U /*!< SCB CLIDR: LoC Position */ -#define SCB_CLIDR_LOC_Msk (7UL << SCB_CLIDR_LOC_Pos) /*!< SCB CLIDR: LoC Mask */ - -/* SCB Cache Type Register Definitions */ -#define SCB_CTR_FORMAT_Pos 29U /*!< SCB CTR: Format Position */ -#define SCB_CTR_FORMAT_Msk (7UL << SCB_CTR_FORMAT_Pos) /*!< SCB CTR: Format Mask */ - -#define SCB_CTR_CWG_Pos 24U /*!< SCB CTR: CWG Position */ -#define SCB_CTR_CWG_Msk (0xFUL << SCB_CTR_CWG_Pos) /*!< SCB CTR: CWG Mask */ - -#define SCB_CTR_ERG_Pos 20U /*!< SCB CTR: ERG Position */ -#define SCB_CTR_ERG_Msk (0xFUL << SCB_CTR_ERG_Pos) /*!< SCB CTR: ERG Mask */ - -#define SCB_CTR_DMINLINE_Pos 16U /*!< SCB CTR: DminLine Position */ -#define SCB_CTR_DMINLINE_Msk (0xFUL << SCB_CTR_DMINLINE_Pos) /*!< SCB CTR: DminLine Mask */ - -#define SCB_CTR_IMINLINE_Pos 0U /*!< SCB CTR: ImInLine Position */ -#define SCB_CTR_IMINLINE_Msk (0xFUL /*<< SCB_CTR_IMINLINE_Pos*/) /*!< SCB CTR: ImInLine Mask */ - -/* SCB Cache Size ID Register Definitions */ -#define SCB_CCSIDR_WT_Pos 31U /*!< SCB CCSIDR: WT Position */ -#define SCB_CCSIDR_WT_Msk (1UL << SCB_CCSIDR_WT_Pos) /*!< SCB CCSIDR: WT Mask */ - -#define SCB_CCSIDR_WB_Pos 30U /*!< SCB CCSIDR: WB Position */ -#define SCB_CCSIDR_WB_Msk (1UL << SCB_CCSIDR_WB_Pos) /*!< SCB CCSIDR: WB Mask */ - -#define SCB_CCSIDR_RA_Pos 29U /*!< SCB CCSIDR: RA Position */ -#define SCB_CCSIDR_RA_Msk (1UL << SCB_CCSIDR_RA_Pos) /*!< SCB CCSIDR: RA Mask */ - -#define SCB_CCSIDR_WA_Pos 28U /*!< SCB CCSIDR: WA Position */ -#define SCB_CCSIDR_WA_Msk (1UL << SCB_CCSIDR_WA_Pos) /*!< SCB CCSIDR: WA Mask */ - -#define SCB_CCSIDR_NUMSETS_Pos 13U /*!< SCB CCSIDR: NumSets Position */ -#define SCB_CCSIDR_NUMSETS_Msk (0x7FFFUL << SCB_CCSIDR_NUMSETS_Pos) /*!< SCB CCSIDR: NumSets Mask */ - -#define SCB_CCSIDR_ASSOCIATIVITY_Pos 3U /*!< SCB CCSIDR: Associativity Position */ -#define SCB_CCSIDR_ASSOCIATIVITY_Msk (0x3FFUL << SCB_CCSIDR_ASSOCIATIVITY_Pos) /*!< SCB CCSIDR: Associativity Mask */ - -#define SCB_CCSIDR_LINESIZE_Pos 0U /*!< SCB CCSIDR: LineSize Position */ -#define SCB_CCSIDR_LINESIZE_Msk (7UL /*<< SCB_CCSIDR_LINESIZE_Pos*/) /*!< SCB CCSIDR: LineSize Mask */ - -/* SCB Cache Size Selection Register Definitions */ -#define SCB_CSSELR_LEVEL_Pos 1U /*!< SCB CSSELR: Level Position */ -#define SCB_CSSELR_LEVEL_Msk (7UL << SCB_CSSELR_LEVEL_Pos) /*!< SCB CSSELR: Level Mask */ - -#define SCB_CSSELR_IND_Pos 0U /*!< SCB CSSELR: InD Position */ -#define SCB_CSSELR_IND_Msk (1UL /*<< SCB_CSSELR_IND_Pos*/) /*!< SCB CSSELR: InD Mask */ - -/* SCB Software Triggered Interrupt Register Definitions */ -#define SCB_STIR_INTID_Pos 0U /*!< SCB STIR: INTID Position */ -#define SCB_STIR_INTID_Msk (0x1FFUL /*<< SCB_STIR_INTID_Pos*/) /*!< SCB STIR: INTID Mask */ - -/* SCB D-Cache Invalidate by Set-way Register Definitions */ -#define SCB_DCISW_WAY_Pos 30U /*!< SCB DCISW: Way Position */ -#define SCB_DCISW_WAY_Msk (3UL << SCB_DCISW_WAY_Pos) /*!< SCB DCISW: Way Mask */ - -#define SCB_DCISW_SET_Pos 5U /*!< SCB DCISW: Set Position */ -#define SCB_DCISW_SET_Msk (0x1FFUL << SCB_DCISW_SET_Pos) /*!< SCB DCISW: Set Mask */ - -/* SCB D-Cache Clean by Set-way Register Definitions */ -#define SCB_DCCSW_WAY_Pos 30U /*!< SCB DCCSW: Way Position */ -#define SCB_DCCSW_WAY_Msk (3UL << SCB_DCCSW_WAY_Pos) /*!< SCB DCCSW: Way Mask */ - -#define SCB_DCCSW_SET_Pos 5U /*!< SCB DCCSW: Set Position */ -#define SCB_DCCSW_SET_Msk (0x1FFUL << SCB_DCCSW_SET_Pos) /*!< SCB DCCSW: Set Mask */ - -/* SCB D-Cache Clean and Invalidate by Set-way Register Definitions */ -#define SCB_DCCISW_WAY_Pos 30U /*!< SCB DCCISW: Way Position */ -#define SCB_DCCISW_WAY_Msk (3UL << SCB_DCCISW_WAY_Pos) /*!< SCB DCCISW: Way Mask */ - -#define SCB_DCCISW_SET_Pos 5U /*!< SCB DCCISW: Set Position */ -#define SCB_DCCISW_SET_Msk (0x1FFUL << SCB_DCCISW_SET_Pos) /*!< SCB DCCISW: Set Mask */ - -/* Instruction Tightly-Coupled Memory Control Register Definitions */ -#define SCB_ITCMCR_SZ_Pos 3U /*!< SCB ITCMCR: SZ Position */ -#define SCB_ITCMCR_SZ_Msk (0xFUL << SCB_ITCMCR_SZ_Pos) /*!< SCB ITCMCR: SZ Mask */ - -#define SCB_ITCMCR_RETEN_Pos 2U /*!< SCB ITCMCR: RETEN Position */ -#define SCB_ITCMCR_RETEN_Msk (1UL << SCB_ITCMCR_RETEN_Pos) /*!< SCB ITCMCR: RETEN Mask */ - -#define SCB_ITCMCR_RMW_Pos 1U /*!< SCB ITCMCR: RMW Position */ -#define SCB_ITCMCR_RMW_Msk (1UL << SCB_ITCMCR_RMW_Pos) /*!< SCB ITCMCR: RMW Mask */ - -#define SCB_ITCMCR_EN_Pos 0U /*!< SCB ITCMCR: EN Position */ -#define SCB_ITCMCR_EN_Msk (1UL /*<< SCB_ITCMCR_EN_Pos*/) /*!< SCB ITCMCR: EN Mask */ - -/* Data Tightly-Coupled Memory Control Register Definitions */ -#define SCB_DTCMCR_SZ_Pos 3U /*!< SCB DTCMCR: SZ Position */ -#define SCB_DTCMCR_SZ_Msk (0xFUL << SCB_DTCMCR_SZ_Pos) /*!< SCB DTCMCR: SZ Mask */ - -#define SCB_DTCMCR_RETEN_Pos 2U /*!< SCB DTCMCR: RETEN Position */ -#define SCB_DTCMCR_RETEN_Msk (1UL << SCB_DTCMCR_RETEN_Pos) /*!< SCB DTCMCR: RETEN Mask */ - -#define SCB_DTCMCR_RMW_Pos 1U /*!< SCB DTCMCR: RMW Position */ -#define SCB_DTCMCR_RMW_Msk (1UL << SCB_DTCMCR_RMW_Pos) /*!< SCB DTCMCR: RMW Mask */ - -#define SCB_DTCMCR_EN_Pos 0U /*!< SCB DTCMCR: EN Position */ -#define SCB_DTCMCR_EN_Msk (1UL /*<< SCB_DTCMCR_EN_Pos*/) /*!< SCB DTCMCR: EN Mask */ - -/* AHBP Control Register Definitions */ -#define SCB_AHBPCR_SZ_Pos 1U /*!< SCB AHBPCR: SZ Position */ -#define SCB_AHBPCR_SZ_Msk (7UL << SCB_AHBPCR_SZ_Pos) /*!< SCB AHBPCR: SZ Mask */ - -#define SCB_AHBPCR_EN_Pos 0U /*!< SCB AHBPCR: EN Position */ -#define SCB_AHBPCR_EN_Msk (1UL /*<< SCB_AHBPCR_EN_Pos*/) /*!< SCB AHBPCR: EN Mask */ - -/* L1 Cache Control Register Definitions */ -#define SCB_CACR_FORCEWT_Pos 2U /*!< SCB CACR: FORCEWT Position */ -#define SCB_CACR_FORCEWT_Msk (1UL << SCB_CACR_FORCEWT_Pos) /*!< SCB CACR: FORCEWT Mask */ - -#define SCB_CACR_ECCEN_Pos 1U /*!< SCB CACR: ECCEN Position */ -#define SCB_CACR_ECCEN_Msk (1UL << SCB_CACR_ECCEN_Pos) /*!< SCB CACR: ECCEN Mask */ - -#define SCB_CACR_SIWT_Pos 0U /*!< SCB CACR: SIWT Position */ -#define SCB_CACR_SIWT_Msk (1UL /*<< SCB_CACR_SIWT_Pos*/) /*!< SCB CACR: SIWT Mask */ - -/* AHBS Control Register Definitions */ -#define SCB_AHBSCR_INITCOUNT_Pos 11U /*!< SCB AHBSCR: INITCOUNT Position */ -#define SCB_AHBSCR_INITCOUNT_Msk (0x1FUL << SCB_AHBPCR_INITCOUNT_Pos) /*!< SCB AHBSCR: INITCOUNT Mask */ - -#define SCB_AHBSCR_TPRI_Pos 2U /*!< SCB AHBSCR: TPRI Position */ -#define SCB_AHBSCR_TPRI_Msk (0x1FFUL << SCB_AHBPCR_TPRI_Pos) /*!< SCB AHBSCR: TPRI Mask */ - -#define SCB_AHBSCR_CTL_Pos 0U /*!< SCB AHBSCR: CTL Position*/ -#define SCB_AHBSCR_CTL_Msk (3UL /*<< SCB_AHBPCR_CTL_Pos*/) /*!< SCB AHBSCR: CTL Mask */ - -/* Auxiliary Bus Fault Status Register Definitions */ -#define SCB_ABFSR_AXIMTYPE_Pos 8U /*!< SCB ABFSR: AXIMTYPE Position*/ -#define SCB_ABFSR_AXIMTYPE_Msk (3UL << SCB_ABFSR_AXIMTYPE_Pos) /*!< SCB ABFSR: AXIMTYPE Mask */ - -#define SCB_ABFSR_EPPB_Pos 4U /*!< SCB ABFSR: EPPB Position*/ -#define SCB_ABFSR_EPPB_Msk (1UL << SCB_ABFSR_EPPB_Pos) /*!< SCB ABFSR: EPPB Mask */ - -#define SCB_ABFSR_AXIM_Pos 3U /*!< SCB ABFSR: AXIM Position*/ -#define SCB_ABFSR_AXIM_Msk (1UL << SCB_ABFSR_AXIM_Pos) /*!< SCB ABFSR: AXIM Mask */ - -#define SCB_ABFSR_AHBP_Pos 2U /*!< SCB ABFSR: AHBP Position*/ -#define SCB_ABFSR_AHBP_Msk (1UL << SCB_ABFSR_AHBP_Pos) /*!< SCB ABFSR: AHBP Mask */ - -#define SCB_ABFSR_DTCM_Pos 1U /*!< SCB ABFSR: DTCM Position*/ -#define SCB_ABFSR_DTCM_Msk (1UL << SCB_ABFSR_DTCM_Pos) /*!< SCB ABFSR: DTCM Mask */ - -#define SCB_ABFSR_ITCM_Pos 0U /*!< SCB ABFSR: ITCM Position*/ -#define SCB_ABFSR_ITCM_Msk (1UL /*<< SCB_ABFSR_ITCM_Pos*/) /*!< SCB ABFSR: ITCM Mask */ - -/*@} end of group CMSIS_SCB */ - - -/** - \ingroup CMSIS_core_register - \defgroup CMSIS_SCnSCB System Controls not in SCB (SCnSCB) - \brief Type definitions for the System Control and ID Register not in the SCB - @{ - */ - -/** - \brief Structure type to access the System Control and ID Register not in the SCB. - */ -typedef struct -{ - uint32_t RESERVED0[1U]; - __IM uint32_t ICTR; /*!< Offset: 0x004 (R/ ) Interrupt Controller Type Register */ - __IOM uint32_t ACTLR; /*!< Offset: 0x008 (R/W) Auxiliary Control Register */ - __IOM uint32_t CPPWR; /*!< Offset: 0x00C (R/W) Coprocessor Power Control Register */ -} SCnSCB_Type; - -/* Interrupt Controller Type Register Definitions */ -#define SCnSCB_ICTR_INTLINESNUM_Pos 0U /*!< ICTR: INTLINESNUM Position */ -#define SCnSCB_ICTR_INTLINESNUM_Msk (0xFUL /*<< SCnSCB_ICTR_INTLINESNUM_Pos*/) /*!< ICTR: INTLINESNUM Mask */ - -/*@} end of group CMSIS_SCnotSCB */ - - -/** - \ingroup CMSIS_core_register - \defgroup CMSIS_SysTick System Tick Timer (SysTick) - \brief Type definitions for the System Timer Registers. - @{ - */ - -/** - \brief Structure type to access the System Timer (SysTick). - */ -typedef struct -{ - __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) SysTick Control and Status Register */ - __IOM uint32_t LOAD; /*!< Offset: 0x004 (R/W) SysTick Reload Value Register */ - __IOM uint32_t VAL; /*!< Offset: 0x008 (R/W) SysTick Current Value Register */ - __IM uint32_t CALIB; /*!< Offset: 0x00C (R/ ) SysTick Calibration Register */ -} SysTick_Type; - -/* SysTick Control / Status Register Definitions */ -#define SysTick_CTRL_COUNTFLAG_Pos 16U /*!< SysTick CTRL: COUNTFLAG Position */ -#define SysTick_CTRL_COUNTFLAG_Msk (1UL << SysTick_CTRL_COUNTFLAG_Pos) /*!< SysTick CTRL: COUNTFLAG Mask */ - -#define SysTick_CTRL_CLKSOURCE_Pos 2U /*!< SysTick CTRL: CLKSOURCE Position */ -#define SysTick_CTRL_CLKSOURCE_Msk (1UL << SysTick_CTRL_CLKSOURCE_Pos) /*!< SysTick CTRL: CLKSOURCE Mask */ - -#define SysTick_CTRL_TICKINT_Pos 1U /*!< SysTick CTRL: TICKINT Position */ -#define SysTick_CTRL_TICKINT_Msk (1UL << SysTick_CTRL_TICKINT_Pos) /*!< SysTick CTRL: TICKINT Mask */ - -#define SysTick_CTRL_ENABLE_Pos 0U /*!< SysTick CTRL: ENABLE Position */ -#define SysTick_CTRL_ENABLE_Msk (1UL /*<< SysTick_CTRL_ENABLE_Pos*/) /*!< SysTick CTRL: ENABLE Mask */ - -/* SysTick Reload Register Definitions */ -#define SysTick_LOAD_RELOAD_Pos 0U /*!< SysTick LOAD: RELOAD Position */ -#define SysTick_LOAD_RELOAD_Msk (0xFFFFFFUL /*<< SysTick_LOAD_RELOAD_Pos*/) /*!< SysTick LOAD: RELOAD Mask */ - -/* SysTick Current Register Definitions */ -#define SysTick_VAL_CURRENT_Pos 0U /*!< SysTick VAL: CURRENT Position */ -#define SysTick_VAL_CURRENT_Msk (0xFFFFFFUL /*<< SysTick_VAL_CURRENT_Pos*/) /*!< SysTick VAL: CURRENT Mask */ - -/* SysTick Calibration Register Definitions */ -#define SysTick_CALIB_NOREF_Pos 31U /*!< SysTick CALIB: NOREF Position */ -#define SysTick_CALIB_NOREF_Msk (1UL << SysTick_CALIB_NOREF_Pos) /*!< SysTick CALIB: NOREF Mask */ - -#define SysTick_CALIB_SKEW_Pos 30U /*!< SysTick CALIB: SKEW Position */ -#define SysTick_CALIB_SKEW_Msk (1UL << SysTick_CALIB_SKEW_Pos) /*!< SysTick CALIB: SKEW Mask */ - -#define SysTick_CALIB_TENMS_Pos 0U /*!< SysTick CALIB: TENMS Position */ -#define SysTick_CALIB_TENMS_Msk (0xFFFFFFUL /*<< SysTick_CALIB_TENMS_Pos*/) /*!< SysTick CALIB: TENMS Mask */ - -/*@} end of group CMSIS_SysTick */ - - -/** - \ingroup CMSIS_core_register - \defgroup CMSIS_ITM Instrumentation Trace Macrocell (ITM) - \brief Type definitions for the Instrumentation Trace Macrocell (ITM) - @{ - */ - -/** - \brief Structure type to access the Instrumentation Trace Macrocell Register (ITM). - */ -typedef struct -{ - __OM union - { - __OM uint8_t u8; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 8-bit */ - __OM uint16_t u16; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 16-bit */ - __OM uint32_t u32; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 32-bit */ - } PORT [32U]; /*!< Offset: 0x000 ( /W) ITM Stimulus Port Registers */ - uint32_t RESERVED0[864U]; - __IOM uint32_t TER; /*!< Offset: 0xE00 (R/W) ITM Trace Enable Register */ - uint32_t RESERVED1[15U]; - __IOM uint32_t TPR; /*!< Offset: 0xE40 (R/W) ITM Trace Privilege Register */ - uint32_t RESERVED2[15U]; - __IOM uint32_t TCR; /*!< Offset: 0xE80 (R/W) ITM Trace Control Register */ - uint32_t RESERVED3[29U]; - __OM uint32_t IWR; /*!< Offset: 0xEF8 ( /W) ITM Integration Write Register */ - __IM uint32_t IRR; /*!< Offset: 0xEFC (R/ ) ITM Integration Read Register */ - __IOM uint32_t IMCR; /*!< Offset: 0xF00 (R/W) ITM Integration Mode Control Register */ - uint32_t RESERVED4[43U]; - __OM uint32_t LAR; /*!< Offset: 0xFB0 ( /W) ITM Lock Access Register */ - __IM uint32_t LSR; /*!< Offset: 0xFB4 (R/ ) ITM Lock Status Register */ - uint32_t RESERVED5[1U]; - __IM uint32_t DEVARCH; /*!< Offset: 0xFBC (R/ ) ITM Device Architecture Register */ - uint32_t RESERVED6[4U]; - __IM uint32_t PID4; /*!< Offset: 0xFD0 (R/ ) ITM Peripheral Identification Register #4 */ - __IM uint32_t PID5; /*!< Offset: 0xFD4 (R/ ) ITM Peripheral Identification Register #5 */ - __IM uint32_t PID6; /*!< Offset: 0xFD8 (R/ ) ITM Peripheral Identification Register #6 */ - __IM uint32_t PID7; /*!< Offset: 0xFDC (R/ ) ITM Peripheral Identification Register #7 */ - __IM uint32_t PID0; /*!< Offset: 0xFE0 (R/ ) ITM Peripheral Identification Register #0 */ - __IM uint32_t PID1; /*!< Offset: 0xFE4 (R/ ) ITM Peripheral Identification Register #1 */ - __IM uint32_t PID2; /*!< Offset: 0xFE8 (R/ ) ITM Peripheral Identification Register #2 */ - __IM uint32_t PID3; /*!< Offset: 0xFEC (R/ ) ITM Peripheral Identification Register #3 */ - __IM uint32_t CID0; /*!< Offset: 0xFF0 (R/ ) ITM Component Identification Register #0 */ - __IM uint32_t CID1; /*!< Offset: 0xFF4 (R/ ) ITM Component Identification Register #1 */ - __IM uint32_t CID2; /*!< Offset: 0xFF8 (R/ ) ITM Component Identification Register #2 */ - __IM uint32_t CID3; /*!< Offset: 0xFFC (R/ ) ITM Component Identification Register #3 */ -} ITM_Type; - -/* ITM Stimulus Port Register Definitions */ -#define ITM_STIM_DISABLED_Pos 1U /*!< ITM STIM: DISABLED Position */ -#define ITM_STIM_DISABLED_Msk (0x1UL << ITM_STIM_DISABLED_Pos) /*!< ITM STIM: DISABLED Mask */ - -#define ITM_STIM_FIFOREADY_Pos 0U /*!< ITM STIM: FIFOREADY Position */ -#define ITM_STIM_FIFOREADY_Msk (0x1UL /*<< ITM_STIM_FIFOREADY_Pos*/) /*!< ITM STIM: FIFOREADY Mask */ - -/* ITM Trace Privilege Register Definitions */ -#define ITM_TPR_PRIVMASK_Pos 0U /*!< ITM TPR: PRIVMASK Position */ -#define ITM_TPR_PRIVMASK_Msk (0xFFFFFFFFUL /*<< ITM_TPR_PRIVMASK_Pos*/) /*!< ITM TPR: PRIVMASK Mask */ - -/* ITM Trace Control Register Definitions */ -#define ITM_TCR_BUSY_Pos 23U /*!< ITM TCR: BUSY Position */ -#define ITM_TCR_BUSY_Msk (1UL << ITM_TCR_BUSY_Pos) /*!< ITM TCR: BUSY Mask */ - -#define ITM_TCR_TRACEBUSID_Pos 16U /*!< ITM TCR: ATBID Position */ -#define ITM_TCR_TRACEBUSID_Msk (0x7FUL << ITM_TCR_TRACEBUSID_Pos) /*!< ITM TCR: ATBID Mask */ - -#define ITM_TCR_GTSFREQ_Pos 10U /*!< ITM TCR: Global timestamp frequency Position */ -#define ITM_TCR_GTSFREQ_Msk (3UL << ITM_TCR_GTSFREQ_Pos) /*!< ITM TCR: Global timestamp frequency Mask */ - -#define ITM_TCR_TSPRESCALE_Pos 8U /*!< ITM TCR: TSPRESCALE Position */ -#define ITM_TCR_TSPRESCALE_Msk (3UL << ITM_TCR_TSPRESCALE_Pos) /*!< ITM TCR: TSPRESCALE Mask */ - -#define ITM_TCR_STALLENA_Pos 5U /*!< ITM TCR: STALLENA Position */ -#define ITM_TCR_STALLENA_Msk (1UL << ITM_TCR_STALLENA_Pos) /*!< ITM TCR: STALLENA Mask */ - -#define ITM_TCR_SWOENA_Pos 4U /*!< ITM TCR: SWOENA Position */ -#define ITM_TCR_SWOENA_Msk (1UL << ITM_TCR_SWOENA_Pos) /*!< ITM TCR: SWOENA Mask */ - -#define ITM_TCR_DWTENA_Pos 3U /*!< ITM TCR: DWTENA Position */ -#define ITM_TCR_DWTENA_Msk (1UL << ITM_TCR_DWTENA_Pos) /*!< ITM TCR: DWTENA Mask */ - -#define ITM_TCR_SYNCENA_Pos 2U /*!< ITM TCR: SYNCENA Position */ -#define ITM_TCR_SYNCENA_Msk (1UL << ITM_TCR_SYNCENA_Pos) /*!< ITM TCR: SYNCENA Mask */ - -#define ITM_TCR_TSENA_Pos 1U /*!< ITM TCR: TSENA Position */ -#define ITM_TCR_TSENA_Msk (1UL << ITM_TCR_TSENA_Pos) /*!< ITM TCR: TSENA Mask */ - -#define ITM_TCR_ITMENA_Pos 0U /*!< ITM TCR: ITM Enable bit Position */ -#define ITM_TCR_ITMENA_Msk (1UL /*<< ITM_TCR_ITMENA_Pos*/) /*!< ITM TCR: ITM Enable bit Mask */ - -/* ITM Integration Write Register Definitions */ -#define ITM_IWR_ATVALIDM_Pos 0U /*!< ITM IWR: ATVALIDM Position */ -#define ITM_IWR_ATVALIDM_Msk (1UL /*<< ITM_IWR_ATVALIDM_Pos*/) /*!< ITM IWR: ATVALIDM Mask */ - -/* ITM Integration Read Register Definitions */ -#define ITM_IRR_ATREADYM_Pos 0U /*!< ITM IRR: ATREADYM Position */ -#define ITM_IRR_ATREADYM_Msk (1UL /*<< ITM_IRR_ATREADYM_Pos*/) /*!< ITM IRR: ATREADYM Mask */ - -/* ITM Integration Mode Control Register Definitions */ -#define ITM_IMCR_INTEGRATION_Pos 0U /*!< ITM IMCR: INTEGRATION Position */ -#define ITM_IMCR_INTEGRATION_Msk (1UL /*<< ITM_IMCR_INTEGRATION_Pos*/) /*!< ITM IMCR: INTEGRATION Mask */ - -/* ITM Lock Status Register Definitions */ -#define ITM_LSR_ByteAcc_Pos 2U /*!< ITM LSR: ByteAcc Position */ -#define ITM_LSR_ByteAcc_Msk (1UL << ITM_LSR_ByteAcc_Pos) /*!< ITM LSR: ByteAcc Mask */ - -#define ITM_LSR_Access_Pos 1U /*!< ITM LSR: Access Position */ -#define ITM_LSR_Access_Msk (1UL << ITM_LSR_Access_Pos) /*!< ITM LSR: Access Mask */ - -#define ITM_LSR_Present_Pos 0U /*!< ITM LSR: Present Position */ -#define ITM_LSR_Present_Msk (1UL /*<< ITM_LSR_Present_Pos*/) /*!< ITM LSR: Present Mask */ - -/*@}*/ /* end of group CMSIS_ITM */ - - -/** - \ingroup CMSIS_core_register - \defgroup CMSIS_DWT Data Watchpoint and Trace (DWT) - \brief Type definitions for the Data Watchpoint and Trace (DWT) - @{ - */ - -/** - \brief Structure type to access the Data Watchpoint and Trace Register (DWT). - */ -typedef struct -{ - __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) Control Register */ - __IOM uint32_t CYCCNT; /*!< Offset: 0x004 (R/W) Cycle Count Register */ - __IOM uint32_t CPICNT; /*!< Offset: 0x008 (R/W) CPI Count Register */ - __IOM uint32_t EXCCNT; /*!< Offset: 0x00C (R/W) Exception Overhead Count Register */ - __IOM uint32_t SLEEPCNT; /*!< Offset: 0x010 (R/W) Sleep Count Register */ - __IOM uint32_t LSUCNT; /*!< Offset: 0x014 (R/W) LSU Count Register */ - __IOM uint32_t FOLDCNT; /*!< Offset: 0x018 (R/W) Folded-instruction Count Register */ - __IM uint32_t PCSR; /*!< Offset: 0x01C (R/ ) Program Counter Sample Register */ - __IOM uint32_t COMP0; /*!< Offset: 0x020 (R/W) Comparator Register 0 */ - uint32_t RESERVED1[1U]; - __IOM uint32_t FUNCTION0; /*!< Offset: 0x028 (R/W) Function Register 0 */ - uint32_t RESERVED2[1U]; - __IOM uint32_t COMP1; /*!< Offset: 0x030 (R/W) Comparator Register 1 */ - uint32_t RESERVED3[1U]; - __IOM uint32_t FUNCTION1; /*!< Offset: 0x038 (R/W) Function Register 1 */ - uint32_t RESERVED4[1U]; - __IOM uint32_t COMP2; /*!< Offset: 0x040 (R/W) Comparator Register 2 */ - uint32_t RESERVED5[1U]; - __IOM uint32_t FUNCTION2; /*!< Offset: 0x048 (R/W) Function Register 2 */ - uint32_t RESERVED6[1U]; - __IOM uint32_t COMP3; /*!< Offset: 0x050 (R/W) Comparator Register 3 */ - uint32_t RESERVED7[1U]; - __IOM uint32_t FUNCTION3; /*!< Offset: 0x058 (R/W) Function Register 3 */ - uint32_t RESERVED8[1U]; - __IOM uint32_t COMP4; /*!< Offset: 0x060 (R/W) Comparator Register 4 */ - uint32_t RESERVED9[1U]; - __IOM uint32_t FUNCTION4; /*!< Offset: 0x068 (R/W) Function Register 4 */ - uint32_t RESERVED10[1U]; - __IOM uint32_t COMP5; /*!< Offset: 0x070 (R/W) Comparator Register 5 */ - uint32_t RESERVED11[1U]; - __IOM uint32_t FUNCTION5; /*!< Offset: 0x078 (R/W) Function Register 5 */ - uint32_t RESERVED12[1U]; - __IOM uint32_t COMP6; /*!< Offset: 0x080 (R/W) Comparator Register 6 */ - uint32_t RESERVED13[1U]; - __IOM uint32_t FUNCTION6; /*!< Offset: 0x088 (R/W) Function Register 6 */ - uint32_t RESERVED14[1U]; - __IOM uint32_t COMP7; /*!< Offset: 0x090 (R/W) Comparator Register 7 */ - uint32_t RESERVED15[1U]; - __IOM uint32_t FUNCTION7; /*!< Offset: 0x098 (R/W) Function Register 7 */ - uint32_t RESERVED16[1U]; - __IOM uint32_t COMP8; /*!< Offset: 0x0A0 (R/W) Comparator Register 8 */ - uint32_t RESERVED17[1U]; - __IOM uint32_t FUNCTION8; /*!< Offset: 0x0A8 (R/W) Function Register 8 */ - uint32_t RESERVED18[1U]; - __IOM uint32_t COMP9; /*!< Offset: 0x0B0 (R/W) Comparator Register 9 */ - uint32_t RESERVED19[1U]; - __IOM uint32_t FUNCTION9; /*!< Offset: 0x0B8 (R/W) Function Register 9 */ - uint32_t RESERVED20[1U]; - __IOM uint32_t COMP10; /*!< Offset: 0x0C0 (R/W) Comparator Register 10 */ - uint32_t RESERVED21[1U]; - __IOM uint32_t FUNCTION10; /*!< Offset: 0x0C8 (R/W) Function Register 10 */ - uint32_t RESERVED22[1U]; - __IOM uint32_t COMP11; /*!< Offset: 0x0D0 (R/W) Comparator Register 11 */ - uint32_t RESERVED23[1U]; - __IOM uint32_t FUNCTION11; /*!< Offset: 0x0D8 (R/W) Function Register 11 */ - uint32_t RESERVED24[1U]; - __IOM uint32_t COMP12; /*!< Offset: 0x0E0 (R/W) Comparator Register 12 */ - uint32_t RESERVED25[1U]; - __IOM uint32_t FUNCTION12; /*!< Offset: 0x0E8 (R/W) Function Register 12 */ - uint32_t RESERVED26[1U]; - __IOM uint32_t COMP13; /*!< Offset: 0x0F0 (R/W) Comparator Register 13 */ - uint32_t RESERVED27[1U]; - __IOM uint32_t FUNCTION13; /*!< Offset: 0x0F8 (R/W) Function Register 13 */ - uint32_t RESERVED28[1U]; - __IOM uint32_t COMP14; /*!< Offset: 0x100 (R/W) Comparator Register 14 */ - uint32_t RESERVED29[1U]; - __IOM uint32_t FUNCTION14; /*!< Offset: 0x108 (R/W) Function Register 14 */ - uint32_t RESERVED30[1U]; - __IOM uint32_t COMP15; /*!< Offset: 0x110 (R/W) Comparator Register 15 */ - uint32_t RESERVED31[1U]; - __IOM uint32_t FUNCTION15; /*!< Offset: 0x118 (R/W) Function Register 15 */ - uint32_t RESERVED32[934U]; - __IM uint32_t LSR; /*!< Offset: 0xFB4 (R ) Lock Status Register */ - uint32_t RESERVED33[1U]; - __IM uint32_t DEVARCH; /*!< Offset: 0xFBC (R/ ) Device Architecture Register */ -} DWT_Type; - -/* DWT Control Register Definitions */ -#define DWT_CTRL_NUMCOMP_Pos 28U /*!< DWT CTRL: NUMCOMP Position */ -#define DWT_CTRL_NUMCOMP_Msk (0xFUL << DWT_CTRL_NUMCOMP_Pos) /*!< DWT CTRL: NUMCOMP Mask */ - -#define DWT_CTRL_NOTRCPKT_Pos 27U /*!< DWT CTRL: NOTRCPKT Position */ -#define DWT_CTRL_NOTRCPKT_Msk (0x1UL << DWT_CTRL_NOTRCPKT_Pos) /*!< DWT CTRL: NOTRCPKT Mask */ - -#define DWT_CTRL_NOEXTTRIG_Pos 26U /*!< DWT CTRL: NOEXTTRIG Position */ -#define DWT_CTRL_NOEXTTRIG_Msk (0x1UL << DWT_CTRL_NOEXTTRIG_Pos) /*!< DWT CTRL: NOEXTTRIG Mask */ - -#define DWT_CTRL_NOCYCCNT_Pos 25U /*!< DWT CTRL: NOCYCCNT Position */ -#define DWT_CTRL_NOCYCCNT_Msk (0x1UL << DWT_CTRL_NOCYCCNT_Pos) /*!< DWT CTRL: NOCYCCNT Mask */ - -#define DWT_CTRL_NOPRFCNT_Pos 24U /*!< DWT CTRL: NOPRFCNT Position */ -#define DWT_CTRL_NOPRFCNT_Msk (0x1UL << DWT_CTRL_NOPRFCNT_Pos) /*!< DWT CTRL: NOPRFCNT Mask */ - -#define DWT_CTRL_CYCDISS_Pos 23U /*!< DWT CTRL: CYCDISS Position */ -#define DWT_CTRL_CYCDISS_Msk (0x1UL << DWT_CTRL_CYCDISS_Pos) /*!< DWT CTRL: CYCDISS Mask */ - -#define DWT_CTRL_CYCEVTENA_Pos 22U /*!< DWT CTRL: CYCEVTENA Position */ -#define DWT_CTRL_CYCEVTENA_Msk (0x1UL << DWT_CTRL_CYCEVTENA_Pos) /*!< DWT CTRL: CYCEVTENA Mask */ - -#define DWT_CTRL_FOLDEVTENA_Pos 21U /*!< DWT CTRL: FOLDEVTENA Position */ -#define DWT_CTRL_FOLDEVTENA_Msk (0x1UL << DWT_CTRL_FOLDEVTENA_Pos) /*!< DWT CTRL: FOLDEVTENA Mask */ - -#define DWT_CTRL_LSUEVTENA_Pos 20U /*!< DWT CTRL: LSUEVTENA Position */ -#define DWT_CTRL_LSUEVTENA_Msk (0x1UL << DWT_CTRL_LSUEVTENA_Pos) /*!< DWT CTRL: LSUEVTENA Mask */ - -#define DWT_CTRL_SLEEPEVTENA_Pos 19U /*!< DWT CTRL: SLEEPEVTENA Position */ -#define DWT_CTRL_SLEEPEVTENA_Msk (0x1UL << DWT_CTRL_SLEEPEVTENA_Pos) /*!< DWT CTRL: SLEEPEVTENA Mask */ - -#define DWT_CTRL_EXCEVTENA_Pos 18U /*!< DWT CTRL: EXCEVTENA Position */ -#define DWT_CTRL_EXCEVTENA_Msk (0x1UL << DWT_CTRL_EXCEVTENA_Pos) /*!< DWT CTRL: EXCEVTENA Mask */ - -#define DWT_CTRL_CPIEVTENA_Pos 17U /*!< DWT CTRL: CPIEVTENA Position */ -#define DWT_CTRL_CPIEVTENA_Msk (0x1UL << DWT_CTRL_CPIEVTENA_Pos) /*!< DWT CTRL: CPIEVTENA Mask */ - -#define DWT_CTRL_EXCTRCENA_Pos 16U /*!< DWT CTRL: EXCTRCENA Position */ -#define DWT_CTRL_EXCTRCENA_Msk (0x1UL << DWT_CTRL_EXCTRCENA_Pos) /*!< DWT CTRL: EXCTRCENA Mask */ - -#define DWT_CTRL_PCSAMPLENA_Pos 12U /*!< DWT CTRL: PCSAMPLENA Position */ -#define DWT_CTRL_PCSAMPLENA_Msk (0x1UL << DWT_CTRL_PCSAMPLENA_Pos) /*!< DWT CTRL: PCSAMPLENA Mask */ - -#define DWT_CTRL_SYNCTAP_Pos 10U /*!< DWT CTRL: SYNCTAP Position */ -#define DWT_CTRL_SYNCTAP_Msk (0x3UL << DWT_CTRL_SYNCTAP_Pos) /*!< DWT CTRL: SYNCTAP Mask */ - -#define DWT_CTRL_CYCTAP_Pos 9U /*!< DWT CTRL: CYCTAP Position */ -#define DWT_CTRL_CYCTAP_Msk (0x1UL << DWT_CTRL_CYCTAP_Pos) /*!< DWT CTRL: CYCTAP Mask */ - -#define DWT_CTRL_POSTINIT_Pos 5U /*!< DWT CTRL: POSTINIT Position */ -#define DWT_CTRL_POSTINIT_Msk (0xFUL << DWT_CTRL_POSTINIT_Pos) /*!< DWT CTRL: POSTINIT Mask */ - -#define DWT_CTRL_POSTPRESET_Pos 1U /*!< DWT CTRL: POSTPRESET Position */ -#define DWT_CTRL_POSTPRESET_Msk (0xFUL << DWT_CTRL_POSTPRESET_Pos) /*!< DWT CTRL: POSTPRESET Mask */ - -#define DWT_CTRL_CYCCNTENA_Pos 0U /*!< DWT CTRL: CYCCNTENA Position */ -#define DWT_CTRL_CYCCNTENA_Msk (0x1UL /*<< DWT_CTRL_CYCCNTENA_Pos*/) /*!< DWT CTRL: CYCCNTENA Mask */ - -/* DWT CPI Count Register Definitions */ -#define DWT_CPICNT_CPICNT_Pos 0U /*!< DWT CPICNT: CPICNT Position */ -#define DWT_CPICNT_CPICNT_Msk (0xFFUL /*<< DWT_CPICNT_CPICNT_Pos*/) /*!< DWT CPICNT: CPICNT Mask */ - -/* DWT Exception Overhead Count Register Definitions */ -#define DWT_EXCCNT_EXCCNT_Pos 0U /*!< DWT EXCCNT: EXCCNT Position */ -#define DWT_EXCCNT_EXCCNT_Msk (0xFFUL /*<< DWT_EXCCNT_EXCCNT_Pos*/) /*!< DWT EXCCNT: EXCCNT Mask */ - -/* DWT Sleep Count Register Definitions */ -#define DWT_SLEEPCNT_SLEEPCNT_Pos 0U /*!< DWT SLEEPCNT: SLEEPCNT Position */ -#define DWT_SLEEPCNT_SLEEPCNT_Msk (0xFFUL /*<< DWT_SLEEPCNT_SLEEPCNT_Pos*/) /*!< DWT SLEEPCNT: SLEEPCNT Mask */ - -/* DWT LSU Count Register Definitions */ -#define DWT_LSUCNT_LSUCNT_Pos 0U /*!< DWT LSUCNT: LSUCNT Position */ -#define DWT_LSUCNT_LSUCNT_Msk (0xFFUL /*<< DWT_LSUCNT_LSUCNT_Pos*/) /*!< DWT LSUCNT: LSUCNT Mask */ - -/* DWT Folded-instruction Count Register Definitions */ -#define DWT_FOLDCNT_FOLDCNT_Pos 0U /*!< DWT FOLDCNT: FOLDCNT Position */ -#define DWT_FOLDCNT_FOLDCNT_Msk (0xFFUL /*<< DWT_FOLDCNT_FOLDCNT_Pos*/) /*!< DWT FOLDCNT: FOLDCNT Mask */ - -/* DWT Comparator Function Register Definitions */ -#define DWT_FUNCTION_ID_Pos 27U /*!< DWT FUNCTION: ID Position */ -#define DWT_FUNCTION_ID_Msk (0x1FUL << DWT_FUNCTION_ID_Pos) /*!< DWT FUNCTION: ID Mask */ - -#define DWT_FUNCTION_MATCHED_Pos 24U /*!< DWT FUNCTION: MATCHED Position */ -#define DWT_FUNCTION_MATCHED_Msk (0x1UL << DWT_FUNCTION_MATCHED_Pos) /*!< DWT FUNCTION: MATCHED Mask */ - -#define DWT_FUNCTION_DATAVSIZE_Pos 10U /*!< DWT FUNCTION: DATAVSIZE Position */ -#define DWT_FUNCTION_DATAVSIZE_Msk (0x3UL << DWT_FUNCTION_DATAVSIZE_Pos) /*!< DWT FUNCTION: DATAVSIZE Mask */ - -#define DWT_FUNCTION_ACTION_Pos 4U /*!< DWT FUNCTION: ACTION Position */ -#define DWT_FUNCTION_ACTION_Msk (0x1UL << DWT_FUNCTION_ACTION_Pos) /*!< DWT FUNCTION: ACTION Mask */ - -#define DWT_FUNCTION_MATCH_Pos 0U /*!< DWT FUNCTION: MATCH Position */ -#define DWT_FUNCTION_MATCH_Msk (0xFUL /*<< DWT_FUNCTION_MATCH_Pos*/) /*!< DWT FUNCTION: MATCH Mask */ - -/*@}*/ /* end of group CMSIS_DWT */ - - -/** - \ingroup CMSIS_core_register - \defgroup CMSIS_TPI Trace Port Interface (TPI) - \brief Type definitions for the Trace Port Interface (TPI) - @{ - */ - -/** - \brief Structure type to access the Trace Port Interface Register (TPI). - */ -typedef struct -{ - __IOM uint32_t SSPSR; /*!< Offset: 0x000 (R/ ) Supported Parallel Port Size Register */ - __IOM uint32_t CSPSR; /*!< Offset: 0x004 (R/W) Current Parallel Port Size Register */ - uint32_t RESERVED0[2U]; - __IOM uint32_t ACPR; /*!< Offset: 0x010 (R/W) Asynchronous Clock Prescaler Register */ - uint32_t RESERVED1[55U]; - __IOM uint32_t SPPR; /*!< Offset: 0x0F0 (R/W) Selected Pin Protocol Register */ - uint32_t RESERVED2[131U]; - __IM uint32_t FFSR; /*!< Offset: 0x300 (R/ ) Formatter and Flush Status Register */ - __IOM uint32_t FFCR; /*!< Offset: 0x304 (R/W) Formatter and Flush Control Register */ - __IM uint32_t FSCR; /*!< Offset: 0x308 (R/ ) Formatter Synchronization Counter Register */ - uint32_t RESERVED3[759U]; - __IM uint32_t TRIGGER; /*!< Offset: 0xEE8 (R/ ) TRIGGER */ - __IM uint32_t FIFO0; /*!< Offset: 0xEEC (R/ ) Integration ETM Data */ - __IM uint32_t ITATBCTR2; /*!< Offset: 0xEF0 (R/ ) ITATBCTR2 */ - uint32_t RESERVED4[1U]; - __IM uint32_t ITATBCTR0; /*!< Offset: 0xEF8 (R/ ) ITATBCTR0 */ - __IM uint32_t FIFO1; /*!< Offset: 0xEFC (R/ ) Integration ITM Data */ - __IOM uint32_t ITCTRL; /*!< Offset: 0xF00 (R/W) Integration Mode Control */ - uint32_t RESERVED5[39U]; - __IOM uint32_t CLAIMSET; /*!< Offset: 0xFA0 (R/W) Claim tag set */ - __IOM uint32_t CLAIMCLR; /*!< Offset: 0xFA4 (R/W) Claim tag clear */ - uint32_t RESERVED7[8U]; - __IM uint32_t DEVID; /*!< Offset: 0xFC8 (R/ ) TPIU_DEVID */ - __IM uint32_t DEVTYPE; /*!< Offset: 0xFCC (R/ ) TPIU_DEVTYPE */ -} TPI_Type; - -/* TPI Asynchronous Clock Prescaler Register Definitions */ -#define TPI_ACPR_PRESCALER_Pos 0U /*!< @Deprecated TPI ACPR: PRESCALER Position */ -#define TPI_ACPR_PRESCALER_Msk (0x1FFFUL /*<< TPI_ACPR_PRESCALER_Pos*/) /*!< @Deprecated TPI ACPR: PRESCALER Mask */ - -#define TPI_ACPR_SWOSCALER_Pos 0U /*!< TPI ACPR: SWOSCALER Position */ -#define TPI_ACPR_SWOSCALER_Msk (0xFFFFUL /*<< TPI_ACPR_SWOSCALER_Pos*/) /*!< TPI ACPR: SWOSCALER Mask */ - -/* TPI Selected Pin Protocol Register Definitions */ -#define TPI_SPPR_TXMODE_Pos 0U /*!< TPI SPPR: TXMODE Position */ -#define TPI_SPPR_TXMODE_Msk (0x3UL /*<< TPI_SPPR_TXMODE_Pos*/) /*!< TPI SPPR: TXMODE Mask */ - -/* TPI Formatter and Flush Status Register Definitions */ -#define TPI_FFSR_FtNonStop_Pos 3U /*!< TPI FFSR: FtNonStop Position */ -#define TPI_FFSR_FtNonStop_Msk (0x1UL << TPI_FFSR_FtNonStop_Pos) /*!< TPI FFSR: FtNonStop Mask */ - -#define TPI_FFSR_TCPresent_Pos 2U /*!< TPI FFSR: TCPresent Position */ -#define TPI_FFSR_TCPresent_Msk (0x1UL << TPI_FFSR_TCPresent_Pos) /*!< TPI FFSR: TCPresent Mask */ - -#define TPI_FFSR_FtStopped_Pos 1U /*!< TPI FFSR: FtStopped Position */ -#define TPI_FFSR_FtStopped_Msk (0x1UL << TPI_FFSR_FtStopped_Pos) /*!< TPI FFSR: FtStopped Mask */ - -#define TPI_FFSR_FlInProg_Pos 0U /*!< TPI FFSR: FlInProg Position */ -#define TPI_FFSR_FlInProg_Msk (0x1UL /*<< TPI_FFSR_FlInProg_Pos*/) /*!< TPI FFSR: FlInProg Mask */ - -/* TPI Formatter and Flush Control Register Definitions */ -#define TPI_FFCR_TrigIn_Pos 8U /*!< TPI FFCR: TrigIn Position */ -#define TPI_FFCR_TrigIn_Msk (0x1UL << TPI_FFCR_TrigIn_Pos) /*!< TPI FFCR: TrigIn Mask */ - -#define TPI_FFCR_EnFCont_Pos 1U /*!< TPI FFCR: EnFCont Position */ -#define TPI_FFCR_EnFCont_Msk (0x1UL << TPI_FFCR_EnFCont_Pos) /*!< TPI FFCR: EnFCont Mask */ - -/* TPI TRIGGER Register Definitions */ -#define TPI_TRIGGER_TRIGGER_Pos 0U /*!< TPI TRIGGER: TRIGGER Position */ -#define TPI_TRIGGER_TRIGGER_Msk (0x1UL /*<< TPI_TRIGGER_TRIGGER_Pos*/) /*!< TPI TRIGGER: TRIGGER Mask */ - -/* TPI Integration ETM Data Register Definitions (FIFO0) */ -#define TPI_FIFO0_ITM_ATVALID_Pos 29U /*!< TPI FIFO0: ITM_ATVALID Position */ -#define TPI_FIFO0_ITM_ATVALID_Msk (0x3UL << TPI_FIFO0_ITM_ATVALID_Pos) /*!< TPI FIFO0: ITM_ATVALID Mask */ - -#define TPI_FIFO0_ITM_bytecount_Pos 27U /*!< TPI FIFO0: ITM_bytecount Position */ -#define TPI_FIFO0_ITM_bytecount_Msk (0x3UL << TPI_FIFO0_ITM_bytecount_Pos) /*!< TPI FIFO0: ITM_bytecount Mask */ - -#define TPI_FIFO0_ETM_ATVALID_Pos 26U /*!< TPI FIFO0: ETM_ATVALID Position */ -#define TPI_FIFO0_ETM_ATVALID_Msk (0x3UL << TPI_FIFO0_ETM_ATVALID_Pos) /*!< TPI FIFO0: ETM_ATVALID Mask */ - -#define TPI_FIFO0_ETM_bytecount_Pos 24U /*!< TPI FIFO0: ETM_bytecount Position */ -#define TPI_FIFO0_ETM_bytecount_Msk (0x3UL << TPI_FIFO0_ETM_bytecount_Pos) /*!< TPI FIFO0: ETM_bytecount Mask */ - -#define TPI_FIFO0_ETM2_Pos 16U /*!< TPI FIFO0: ETM2 Position */ -#define TPI_FIFO0_ETM2_Msk (0xFFUL << TPI_FIFO0_ETM2_Pos) /*!< TPI FIFO0: ETM2 Mask */ - -#define TPI_FIFO0_ETM1_Pos 8U /*!< TPI FIFO0: ETM1 Position */ -#define TPI_FIFO0_ETM1_Msk (0xFFUL << TPI_FIFO0_ETM1_Pos) /*!< TPI FIFO0: ETM1 Mask */ - -#define TPI_FIFO0_ETM0_Pos 0U /*!< TPI FIFO0: ETM0 Position */ -#define TPI_FIFO0_ETM0_Msk (0xFFUL /*<< TPI_FIFO0_ETM0_Pos*/) /*!< TPI FIFO0: ETM0 Mask */ - -/* TPI ITATBCTR2 Register Definitions */ -#define TPI_ITATBCTR2_ATREADY_Pos 0U /*!< TPI ITATBCTR2: ATREADY Position */ -#define TPI_ITATBCTR2_ATREADY_Msk (0x1UL /*<< TPI_ITATBCTR2_ATREADY_Pos*/) /*!< TPI ITATBCTR2: ATREADY Mask */ - -/* TPI Integration ITM Data Register Definitions (FIFO1) */ -#define TPI_FIFO1_ITM_ATVALID_Pos 29U /*!< TPI FIFO1: ITM_ATVALID Position */ -#define TPI_FIFO1_ITM_ATVALID_Msk (0x3UL << TPI_FIFO1_ITM_ATVALID_Pos) /*!< TPI FIFO1: ITM_ATVALID Mask */ - -#define TPI_FIFO1_ITM_bytecount_Pos 27U /*!< TPI FIFO1: ITM_bytecount Position */ -#define TPI_FIFO1_ITM_bytecount_Msk (0x3UL << TPI_FIFO1_ITM_bytecount_Pos) /*!< TPI FIFO1: ITM_bytecount Mask */ - -#define TPI_FIFO1_ETM_ATVALID_Pos 26U /*!< TPI FIFO1: ETM_ATVALID Position */ -#define TPI_FIFO1_ETM_ATVALID_Msk (0x3UL << TPI_FIFO1_ETM_ATVALID_Pos) /*!< TPI FIFO1: ETM_ATVALID Mask */ - -#define TPI_FIFO1_ETM_bytecount_Pos 24U /*!< TPI FIFO1: ETM_bytecount Position */ -#define TPI_FIFO1_ETM_bytecount_Msk (0x3UL << TPI_FIFO1_ETM_bytecount_Pos) /*!< TPI FIFO1: ETM_bytecount Mask */ - -#define TPI_FIFO1_ITM2_Pos 16U /*!< TPI FIFO1: ITM2 Position */ -#define TPI_FIFO1_ITM2_Msk (0xFFUL << TPI_FIFO1_ITM2_Pos) /*!< TPI FIFO1: ITM2 Mask */ - -#define TPI_FIFO1_ITM1_Pos 8U /*!< TPI FIFO1: ITM1 Position */ -#define TPI_FIFO1_ITM1_Msk (0xFFUL << TPI_FIFO1_ITM1_Pos) /*!< TPI FIFO1: ITM1 Mask */ - -#define TPI_FIFO1_ITM0_Pos 0U /*!< TPI FIFO1: ITM0 Position */ -#define TPI_FIFO1_ITM0_Msk (0xFFUL /*<< TPI_FIFO1_ITM0_Pos*/) /*!< TPI FIFO1: ITM0 Mask */ - -/* TPI ITATBCTR0 Register Definitions */ -#define TPI_ITATBCTR0_ATREADY_Pos 0U /*!< TPI ITATBCTR0: ATREADY Position */ -#define TPI_ITATBCTR0_ATREADY_Msk (0x1UL /*<< TPI_ITATBCTR0_ATREADY_Pos*/) /*!< TPI ITATBCTR0: ATREADY Mask */ - -/* TPI Integration Mode Control Register Definitions */ -#define TPI_ITCTRL_Mode_Pos 0U /*!< TPI ITCTRL: Mode Position */ -#define TPI_ITCTRL_Mode_Msk (0x1UL /*<< TPI_ITCTRL_Mode_Pos*/) /*!< TPI ITCTRL: Mode Mask */ - -/* TPI DEVID Register Definitions */ -#define TPI_DEVID_NRZVALID_Pos 11U /*!< TPI DEVID: NRZVALID Position */ -#define TPI_DEVID_NRZVALID_Msk (0x1UL << TPI_DEVID_NRZVALID_Pos) /*!< TPI DEVID: NRZVALID Mask */ - -#define TPI_DEVID_MANCVALID_Pos 10U /*!< TPI DEVID: MANCVALID Position */ -#define TPI_DEVID_MANCVALID_Msk (0x1UL << TPI_DEVID_MANCVALID_Pos) /*!< TPI DEVID: MANCVALID Mask */ - -#define TPI_DEVID_PTINVALID_Pos 9U /*!< TPI DEVID: PTINVALID Position */ -#define TPI_DEVID_PTINVALID_Msk (0x1UL << TPI_DEVID_PTINVALID_Pos) /*!< TPI DEVID: PTINVALID Mask */ - -#define TPI_DEVID_MinBufSz_Pos 6U /*!< TPI DEVID: MinBufSz Position */ -#define TPI_DEVID_MinBufSz_Msk (0x7UL << TPI_DEVID_MinBufSz_Pos) /*!< TPI DEVID: MinBufSz Mask */ - -#define TPI_DEVID_AsynClkIn_Pos 5U /*!< TPI DEVID: AsynClkIn Position */ -#define TPI_DEVID_AsynClkIn_Msk (0x1UL << TPI_DEVID_AsynClkIn_Pos) /*!< TPI DEVID: AsynClkIn Mask */ - -#define TPI_DEVID_NrTraceInput_Pos 0U /*!< TPI DEVID: NrTraceInput Position */ -#define TPI_DEVID_NrTraceInput_Msk (0x1FUL /*<< TPI_DEVID_NrTraceInput_Pos*/) /*!< TPI DEVID: NrTraceInput Mask */ - -/* TPI DEVTYPE Register Definitions */ -#define TPI_DEVTYPE_MajorType_Pos 4U /*!< TPI DEVTYPE: MajorType Position */ -#define TPI_DEVTYPE_MajorType_Msk (0xFUL << TPI_DEVTYPE_MajorType_Pos) /*!< TPI DEVTYPE: MajorType Mask */ - -#define TPI_DEVTYPE_SubType_Pos 0U /*!< TPI DEVTYPE: SubType Position */ -#define TPI_DEVTYPE_SubType_Msk (0xFUL /*<< TPI_DEVTYPE_SubType_Pos*/) /*!< TPI DEVTYPE: SubType Mask */ - -/*@}*/ /* end of group CMSIS_TPI */ - - -#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) -/** - \ingroup CMSIS_core_register - \defgroup CMSIS_MPU Memory Protection Unit (MPU) - \brief Type definitions for the Memory Protection Unit (MPU) - @{ - */ - -/** - \brief Structure type to access the Memory Protection Unit (MPU). - */ -typedef struct -{ - __IM uint32_t TYPE; /*!< Offset: 0x000 (R/ ) MPU Type Register */ - __IOM uint32_t CTRL; /*!< Offset: 0x004 (R/W) MPU Control Register */ - __IOM uint32_t RNR; /*!< Offset: 0x008 (R/W) MPU Region Number Register */ - __IOM uint32_t RBAR; /*!< Offset: 0x00C (R/W) MPU Region Base Address Register */ - __IOM uint32_t RLAR; /*!< Offset: 0x010 (R/W) MPU Region Limit Address Register */ - __IOM uint32_t RBAR_A1; /*!< Offset: 0x014 (R/W) MPU Region Base Address Register Alias 1 */ - __IOM uint32_t RLAR_A1; /*!< Offset: 0x018 (R/W) MPU Region Limit Address Register Alias 1 */ - __IOM uint32_t RBAR_A2; /*!< Offset: 0x01C (R/W) MPU Region Base Address Register Alias 2 */ - __IOM uint32_t RLAR_A2; /*!< Offset: 0x020 (R/W) MPU Region Limit Address Register Alias 2 */ - __IOM uint32_t RBAR_A3; /*!< Offset: 0x024 (R/W) MPU Region Base Address Register Alias 3 */ - __IOM uint32_t RLAR_A3; /*!< Offset: 0x028 (R/W) MPU Region Limit Address Register Alias 3 */ - uint32_t RESERVED0[1]; - union { - __IOM uint32_t MAIR[2]; - struct { - __IOM uint32_t MAIR0; /*!< Offset: 0x030 (R/W) MPU Memory Attribute Indirection Register 0 */ - __IOM uint32_t MAIR1; /*!< Offset: 0x034 (R/W) MPU Memory Attribute Indirection Register 1 */ - }; - }; -} MPU_Type; - -#define MPU_TYPE_RALIASES 4U - -/* MPU Type Register Definitions */ -#define MPU_TYPE_IREGION_Pos 16U /*!< MPU TYPE: IREGION Position */ -#define MPU_TYPE_IREGION_Msk (0xFFUL << MPU_TYPE_IREGION_Pos) /*!< MPU TYPE: IREGION Mask */ - -#define MPU_TYPE_DREGION_Pos 8U /*!< MPU TYPE: DREGION Position */ -#define MPU_TYPE_DREGION_Msk (0xFFUL << MPU_TYPE_DREGION_Pos) /*!< MPU TYPE: DREGION Mask */ - -#define MPU_TYPE_SEPARATE_Pos 0U /*!< MPU TYPE: SEPARATE Position */ -#define MPU_TYPE_SEPARATE_Msk (1UL /*<< MPU_TYPE_SEPARATE_Pos*/) /*!< MPU TYPE: SEPARATE Mask */ - -/* MPU Control Register Definitions */ -#define MPU_CTRL_PRIVDEFENA_Pos 2U /*!< MPU CTRL: PRIVDEFENA Position */ -#define MPU_CTRL_PRIVDEFENA_Msk (1UL << MPU_CTRL_PRIVDEFENA_Pos) /*!< MPU CTRL: PRIVDEFENA Mask */ - -#define MPU_CTRL_HFNMIENA_Pos 1U /*!< MPU CTRL: HFNMIENA Position */ -#define MPU_CTRL_HFNMIENA_Msk (1UL << MPU_CTRL_HFNMIENA_Pos) /*!< MPU CTRL: HFNMIENA Mask */ - -#define MPU_CTRL_ENABLE_Pos 0U /*!< MPU CTRL: ENABLE Position */ -#define MPU_CTRL_ENABLE_Msk (1UL /*<< MPU_CTRL_ENABLE_Pos*/) /*!< MPU CTRL: ENABLE Mask */ - -/* MPU Region Number Register Definitions */ -#define MPU_RNR_REGION_Pos 0U /*!< MPU RNR: REGION Position */ -#define MPU_RNR_REGION_Msk (0xFFUL /*<< MPU_RNR_REGION_Pos*/) /*!< MPU RNR: REGION Mask */ - -/* MPU Region Base Address Register Definitions */ -#define MPU_RBAR_BASE_Pos 5U /*!< MPU RBAR: ADDR Position */ -#define MPU_RBAR_BASE_Msk (0x7FFFFFFUL << MPU_RBAR_BASE_Pos) /*!< MPU RBAR: ADDR Mask */ - -#define MPU_RBAR_SH_Pos 3U /*!< MPU RBAR: SH Position */ -#define MPU_RBAR_SH_Msk (0x3UL << MPU_RBAR_SH_Pos) /*!< MPU RBAR: SH Mask */ - -#define MPU_RBAR_AP_Pos 1U /*!< MPU RBAR: AP Position */ -#define MPU_RBAR_AP_Msk (0x3UL << MPU_RBAR_AP_Pos) /*!< MPU RBAR: AP Mask */ - -#define MPU_RBAR_XN_Pos 0U /*!< MPU RBAR: XN Position */ -#define MPU_RBAR_XN_Msk (01UL /*<< MPU_RBAR_XN_Pos*/) /*!< MPU RBAR: XN Mask */ - -/* MPU Region Limit Address Register Definitions */ -#define MPU_RLAR_LIMIT_Pos 5U /*!< MPU RLAR: LIMIT Position */ -#define MPU_RLAR_LIMIT_Msk (0x7FFFFFFUL << MPU_RLAR_LIMIT_Pos) /*!< MPU RLAR: LIMIT Mask */ - -#define MPU_RLAR_AttrIndx_Pos 1U /*!< MPU RLAR: AttrIndx Position */ -#define MPU_RLAR_AttrIndx_Msk (0x7UL << MPU_RLAR_AttrIndx_Pos) /*!< MPU RLAR: AttrIndx Mask */ - -#define MPU_RLAR_EN_Pos 0U /*!< MPU RLAR: Region enable bit Position */ -#define MPU_RLAR_EN_Msk (1UL /*<< MPU_RLAR_EN_Pos*/) /*!< MPU RLAR: Region enable bit Disable Mask */ - -/* MPU Memory Attribute Indirection Register 0 Definitions */ -#define MPU_MAIR0_Attr3_Pos 24U /*!< MPU MAIR0: Attr3 Position */ -#define MPU_MAIR0_Attr3_Msk (0xFFUL << MPU_MAIR0_Attr3_Pos) /*!< MPU MAIR0: Attr3 Mask */ - -#define MPU_MAIR0_Attr2_Pos 16U /*!< MPU MAIR0: Attr2 Position */ -#define MPU_MAIR0_Attr2_Msk (0xFFUL << MPU_MAIR0_Attr2_Pos) /*!< MPU MAIR0: Attr2 Mask */ - -#define MPU_MAIR0_Attr1_Pos 8U /*!< MPU MAIR0: Attr1 Position */ -#define MPU_MAIR0_Attr1_Msk (0xFFUL << MPU_MAIR0_Attr1_Pos) /*!< MPU MAIR0: Attr1 Mask */ - -#define MPU_MAIR0_Attr0_Pos 0U /*!< MPU MAIR0: Attr0 Position */ -#define MPU_MAIR0_Attr0_Msk (0xFFUL /*<< MPU_MAIR0_Attr0_Pos*/) /*!< MPU MAIR0: Attr0 Mask */ - -/* MPU Memory Attribute Indirection Register 1 Definitions */ -#define MPU_MAIR1_Attr7_Pos 24U /*!< MPU MAIR1: Attr7 Position */ -#define MPU_MAIR1_Attr7_Msk (0xFFUL << MPU_MAIR1_Attr7_Pos) /*!< MPU MAIR1: Attr7 Mask */ - -#define MPU_MAIR1_Attr6_Pos 16U /*!< MPU MAIR1: Attr6 Position */ -#define MPU_MAIR1_Attr6_Msk (0xFFUL << MPU_MAIR1_Attr6_Pos) /*!< MPU MAIR1: Attr6 Mask */ - -#define MPU_MAIR1_Attr5_Pos 8U /*!< MPU MAIR1: Attr5 Position */ -#define MPU_MAIR1_Attr5_Msk (0xFFUL << MPU_MAIR1_Attr5_Pos) /*!< MPU MAIR1: Attr5 Mask */ - -#define MPU_MAIR1_Attr4_Pos 0U /*!< MPU MAIR1: Attr4 Position */ -#define MPU_MAIR1_Attr4_Msk (0xFFUL /*<< MPU_MAIR1_Attr4_Pos*/) /*!< MPU MAIR1: Attr4 Mask */ - -/*@} end of group CMSIS_MPU */ -#endif - - -#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) -/** - \ingroup CMSIS_core_register - \defgroup CMSIS_SAU Security Attribution Unit (SAU) - \brief Type definitions for the Security Attribution Unit (SAU) - @{ - */ - -/** - \brief Structure type to access the Security Attribution Unit (SAU). - */ -typedef struct -{ - __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) SAU Control Register */ - __IM uint32_t TYPE; /*!< Offset: 0x004 (R/ ) SAU Type Register */ -#if defined (__SAUREGION_PRESENT) && (__SAUREGION_PRESENT == 1U) - __IOM uint32_t RNR; /*!< Offset: 0x008 (R/W) SAU Region Number Register */ - __IOM uint32_t RBAR; /*!< Offset: 0x00C (R/W) SAU Region Base Address Register */ - __IOM uint32_t RLAR; /*!< Offset: 0x010 (R/W) SAU Region Limit Address Register */ -#else - uint32_t RESERVED0[3]; -#endif - __IOM uint32_t SFSR; /*!< Offset: 0x014 (R/W) Secure Fault Status Register */ - __IOM uint32_t SFAR; /*!< Offset: 0x018 (R/W) Secure Fault Address Register */ -} SAU_Type; - -/* SAU Control Register Definitions */ -#define SAU_CTRL_ALLNS_Pos 1U /*!< SAU CTRL: ALLNS Position */ -#define SAU_CTRL_ALLNS_Msk (1UL << SAU_CTRL_ALLNS_Pos) /*!< SAU CTRL: ALLNS Mask */ - -#define SAU_CTRL_ENABLE_Pos 0U /*!< SAU CTRL: ENABLE Position */ -#define SAU_CTRL_ENABLE_Msk (1UL /*<< SAU_CTRL_ENABLE_Pos*/) /*!< SAU CTRL: ENABLE Mask */ - -/* SAU Type Register Definitions */ -#define SAU_TYPE_SREGION_Pos 0U /*!< SAU TYPE: SREGION Position */ -#define SAU_TYPE_SREGION_Msk (0xFFUL /*<< SAU_TYPE_SREGION_Pos*/) /*!< SAU TYPE: SREGION Mask */ - -#if defined (__SAUREGION_PRESENT) && (__SAUREGION_PRESENT == 1U) -/* SAU Region Number Register Definitions */ -#define SAU_RNR_REGION_Pos 0U /*!< SAU RNR: REGION Position */ -#define SAU_RNR_REGION_Msk (0xFFUL /*<< SAU_RNR_REGION_Pos*/) /*!< SAU RNR: REGION Mask */ - -/* SAU Region Base Address Register Definitions */ -#define SAU_RBAR_BADDR_Pos 5U /*!< SAU RBAR: BADDR Position */ -#define SAU_RBAR_BADDR_Msk (0x7FFFFFFUL << SAU_RBAR_BADDR_Pos) /*!< SAU RBAR: BADDR Mask */ - -/* SAU Region Limit Address Register Definitions */ -#define SAU_RLAR_LADDR_Pos 5U /*!< SAU RLAR: LADDR Position */ -#define SAU_RLAR_LADDR_Msk (0x7FFFFFFUL << SAU_RLAR_LADDR_Pos) /*!< SAU RLAR: LADDR Mask */ - -#define SAU_RLAR_NSC_Pos 1U /*!< SAU RLAR: NSC Position */ -#define SAU_RLAR_NSC_Msk (1UL << SAU_RLAR_NSC_Pos) /*!< SAU RLAR: NSC Mask */ - -#define SAU_RLAR_ENABLE_Pos 0U /*!< SAU RLAR: ENABLE Position */ -#define SAU_RLAR_ENABLE_Msk (1UL /*<< SAU_RLAR_ENABLE_Pos*/) /*!< SAU RLAR: ENABLE Mask */ - -#endif /* defined (__SAUREGION_PRESENT) && (__SAUREGION_PRESENT == 1U) */ - -/* Secure Fault Status Register Definitions */ -#define SAU_SFSR_LSERR_Pos 7U /*!< SAU SFSR: LSERR Position */ -#define SAU_SFSR_LSERR_Msk (1UL << SAU_SFSR_LSERR_Pos) /*!< SAU SFSR: LSERR Mask */ - -#define SAU_SFSR_SFARVALID_Pos 6U /*!< SAU SFSR: SFARVALID Position */ -#define SAU_SFSR_SFARVALID_Msk (1UL << SAU_SFSR_SFARVALID_Pos) /*!< SAU SFSR: SFARVALID Mask */ - -#define SAU_SFSR_LSPERR_Pos 5U /*!< SAU SFSR: LSPERR Position */ -#define SAU_SFSR_LSPERR_Msk (1UL << SAU_SFSR_LSPERR_Pos) /*!< SAU SFSR: LSPERR Mask */ - -#define SAU_SFSR_INVTRAN_Pos 4U /*!< SAU SFSR: INVTRAN Position */ -#define SAU_SFSR_INVTRAN_Msk (1UL << SAU_SFSR_INVTRAN_Pos) /*!< SAU SFSR: INVTRAN Mask */ - -#define SAU_SFSR_AUVIOL_Pos 3U /*!< SAU SFSR: AUVIOL Position */ -#define SAU_SFSR_AUVIOL_Msk (1UL << SAU_SFSR_AUVIOL_Pos) /*!< SAU SFSR: AUVIOL Mask */ - -#define SAU_SFSR_INVER_Pos 2U /*!< SAU SFSR: INVER Position */ -#define SAU_SFSR_INVER_Msk (1UL << SAU_SFSR_INVER_Pos) /*!< SAU SFSR: INVER Mask */ - -#define SAU_SFSR_INVIS_Pos 1U /*!< SAU SFSR: INVIS Position */ -#define SAU_SFSR_INVIS_Msk (1UL << SAU_SFSR_INVIS_Pos) /*!< SAU SFSR: INVIS Mask */ - -#define SAU_SFSR_INVEP_Pos 0U /*!< SAU SFSR: INVEP Position */ -#define SAU_SFSR_INVEP_Msk (1UL /*<< SAU_SFSR_INVEP_Pos*/) /*!< SAU SFSR: INVEP Mask */ - -/*@} end of group CMSIS_SAU */ -#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */ - - -/** - \ingroup CMSIS_core_register - \defgroup CMSIS_FPU Floating Point Unit (FPU) - \brief Type definitions for the Floating Point Unit (FPU) - @{ - */ - -/** - \brief Structure type to access the Floating Point Unit (FPU). - */ -typedef struct -{ - uint32_t RESERVED0[1U]; - __IOM uint32_t FPCCR; /*!< Offset: 0x004 (R/W) Floating-Point Context Control Register */ - __IOM uint32_t FPCAR; /*!< Offset: 0x008 (R/W) Floating-Point Context Address Register */ - __IOM uint32_t FPDSCR; /*!< Offset: 0x00C (R/W) Floating-Point Default Status Control Register */ - __IM uint32_t MVFR0; /*!< Offset: 0x010 (R/ ) Media and FP Feature Register 0 */ - __IM uint32_t MVFR1; /*!< Offset: 0x014 (R/ ) Media and FP Feature Register 1 */ -} FPU_Type; - -/* Floating-Point Context Control Register Definitions */ -#define FPU_FPCCR_ASPEN_Pos 31U /*!< FPCCR: ASPEN bit Position */ -#define FPU_FPCCR_ASPEN_Msk (1UL << FPU_FPCCR_ASPEN_Pos) /*!< FPCCR: ASPEN bit Mask */ - -#define FPU_FPCCR_LSPEN_Pos 30U /*!< FPCCR: LSPEN Position */ -#define FPU_FPCCR_LSPEN_Msk (1UL << FPU_FPCCR_LSPEN_Pos) /*!< FPCCR: LSPEN bit Mask */ - -#define FPU_FPCCR_LSPENS_Pos 29U /*!< FPCCR: LSPENS Position */ -#define FPU_FPCCR_LSPENS_Msk (1UL << FPU_FPCCR_LSPENS_Pos) /*!< FPCCR: LSPENS bit Mask */ - -#define FPU_FPCCR_CLRONRET_Pos 28U /*!< FPCCR: CLRONRET Position */ -#define FPU_FPCCR_CLRONRET_Msk (1UL << FPU_FPCCR_CLRONRET_Pos) /*!< FPCCR: CLRONRET bit Mask */ - -#define FPU_FPCCR_CLRONRETS_Pos 27U /*!< FPCCR: CLRONRETS Position */ -#define FPU_FPCCR_CLRONRETS_Msk (1UL << FPU_FPCCR_CLRONRETS_Pos) /*!< FPCCR: CLRONRETS bit Mask */ - -#define FPU_FPCCR_TS_Pos 26U /*!< FPCCR: TS Position */ -#define FPU_FPCCR_TS_Msk (1UL << FPU_FPCCR_TS_Pos) /*!< FPCCR: TS bit Mask */ - -#define FPU_FPCCR_UFRDY_Pos 10U /*!< FPCCR: UFRDY Position */ -#define FPU_FPCCR_UFRDY_Msk (1UL << FPU_FPCCR_UFRDY_Pos) /*!< FPCCR: UFRDY bit Mask */ - -#define FPU_FPCCR_SPLIMVIOL_Pos 9U /*!< FPCCR: SPLIMVIOL Position */ -#define FPU_FPCCR_SPLIMVIOL_Msk (1UL << FPU_FPCCR_SPLIMVIOL_Pos) /*!< FPCCR: SPLIMVIOL bit Mask */ - -#define FPU_FPCCR_MONRDY_Pos 8U /*!< FPCCR: MONRDY Position */ -#define FPU_FPCCR_MONRDY_Msk (1UL << FPU_FPCCR_MONRDY_Pos) /*!< FPCCR: MONRDY bit Mask */ - -#define FPU_FPCCR_SFRDY_Pos 7U /*!< FPCCR: SFRDY Position */ -#define FPU_FPCCR_SFRDY_Msk (1UL << FPU_FPCCR_SFRDY_Pos) /*!< FPCCR: SFRDY bit Mask */ - -#define FPU_FPCCR_BFRDY_Pos 6U /*!< FPCCR: BFRDY Position */ -#define FPU_FPCCR_BFRDY_Msk (1UL << FPU_FPCCR_BFRDY_Pos) /*!< FPCCR: BFRDY bit Mask */ - -#define FPU_FPCCR_MMRDY_Pos 5U /*!< FPCCR: MMRDY Position */ -#define FPU_FPCCR_MMRDY_Msk (1UL << FPU_FPCCR_MMRDY_Pos) /*!< FPCCR: MMRDY bit Mask */ - -#define FPU_FPCCR_HFRDY_Pos 4U /*!< FPCCR: HFRDY Position */ -#define FPU_FPCCR_HFRDY_Msk (1UL << FPU_FPCCR_HFRDY_Pos) /*!< FPCCR: HFRDY bit Mask */ - -#define FPU_FPCCR_THREAD_Pos 3U /*!< FPCCR: processor mode bit Position */ -#define FPU_FPCCR_THREAD_Msk (1UL << FPU_FPCCR_THREAD_Pos) /*!< FPCCR: processor mode active bit Mask */ - -#define FPU_FPCCR_S_Pos 2U /*!< FPCCR: Security status of the FP context bit Position */ -#define FPU_FPCCR_S_Msk (1UL << FPU_FPCCR_S_Pos) /*!< FPCCR: Security status of the FP context bit Mask */ - -#define FPU_FPCCR_USER_Pos 1U /*!< FPCCR: privilege level bit Position */ -#define FPU_FPCCR_USER_Msk (1UL << FPU_FPCCR_USER_Pos) /*!< FPCCR: privilege level bit Mask */ - -#define FPU_FPCCR_LSPACT_Pos 0U /*!< FPCCR: Lazy state preservation active bit Position */ -#define FPU_FPCCR_LSPACT_Msk (1UL /*<< FPU_FPCCR_LSPACT_Pos*/) /*!< FPCCR: Lazy state preservation active bit Mask */ - -/* Floating-Point Context Address Register Definitions */ -#define FPU_FPCAR_ADDRESS_Pos 3U /*!< FPCAR: ADDRESS bit Position */ -#define FPU_FPCAR_ADDRESS_Msk (0x1FFFFFFFUL << FPU_FPCAR_ADDRESS_Pos) /*!< FPCAR: ADDRESS bit Mask */ - -/* Floating-Point Default Status Control Register Definitions */ -#define FPU_FPDSCR_AHP_Pos 26U /*!< FPDSCR: AHP bit Position */ -#define FPU_FPDSCR_AHP_Msk (1UL << FPU_FPDSCR_AHP_Pos) /*!< FPDSCR: AHP bit Mask */ - -#define FPU_FPDSCR_DN_Pos 25U /*!< FPDSCR: DN bit Position */ -#define FPU_FPDSCR_DN_Msk (1UL << FPU_FPDSCR_DN_Pos) /*!< FPDSCR: DN bit Mask */ - -#define FPU_FPDSCR_FZ_Pos 24U /*!< FPDSCR: FZ bit Position */ -#define FPU_FPDSCR_FZ_Msk (1UL << FPU_FPDSCR_FZ_Pos) /*!< FPDSCR: FZ bit Mask */ - -#define FPU_FPDSCR_RMode_Pos 22U /*!< FPDSCR: RMode bit Position */ -#define FPU_FPDSCR_RMode_Msk (3UL << FPU_FPDSCR_RMode_Pos) /*!< FPDSCR: RMode bit Mask */ - -/* Media and FP Feature Register 0 Definitions */ -#define FPU_MVFR0_FP_rounding_modes_Pos 28U /*!< MVFR0: FP rounding modes bits Position */ -#define FPU_MVFR0_FP_rounding_modes_Msk (0xFUL << FPU_MVFR0_FP_rounding_modes_Pos) /*!< MVFR0: FP rounding modes bits Mask */ - -#define FPU_MVFR0_Short_vectors_Pos 24U /*!< MVFR0: Short vectors bits Position */ -#define FPU_MVFR0_Short_vectors_Msk (0xFUL << FPU_MVFR0_Short_vectors_Pos) /*!< MVFR0: Short vectors bits Mask */ - -#define FPU_MVFR0_Square_root_Pos 20U /*!< MVFR0: Square root bits Position */ -#define FPU_MVFR0_Square_root_Msk (0xFUL << FPU_MVFR0_Square_root_Pos) /*!< MVFR0: Square root bits Mask */ - -#define FPU_MVFR0_Divide_Pos 16U /*!< MVFR0: Divide bits Position */ -#define FPU_MVFR0_Divide_Msk (0xFUL << FPU_MVFR0_Divide_Pos) /*!< MVFR0: Divide bits Mask */ - -#define FPU_MVFR0_FP_excep_trapping_Pos 12U /*!< MVFR0: FP exception trapping bits Position */ -#define FPU_MVFR0_FP_excep_trapping_Msk (0xFUL << FPU_MVFR0_FP_excep_trapping_Pos) /*!< MVFR0: FP exception trapping bits Mask */ - -#define FPU_MVFR0_Double_precision_Pos 8U /*!< MVFR0: Double-precision bits Position */ -#define FPU_MVFR0_Double_precision_Msk (0xFUL << FPU_MVFR0_Double_precision_Pos) /*!< MVFR0: Double-precision bits Mask */ - -#define FPU_MVFR0_Single_precision_Pos 4U /*!< MVFR0: Single-precision bits Position */ -#define FPU_MVFR0_Single_precision_Msk (0xFUL << FPU_MVFR0_Single_precision_Pos) /*!< MVFR0: Single-precision bits Mask */ - -#define FPU_MVFR0_A_SIMD_registers_Pos 0U /*!< MVFR0: A_SIMD registers bits Position */ -#define FPU_MVFR0_A_SIMD_registers_Msk (0xFUL /*<< FPU_MVFR0_A_SIMD_registers_Pos*/) /*!< MVFR0: A_SIMD registers bits Mask */ - -/* Media and FP Feature Register 1 Definitions */ -#define FPU_MVFR1_FP_fused_MAC_Pos 28U /*!< MVFR1: FP fused MAC bits Position */ -#define FPU_MVFR1_FP_fused_MAC_Msk (0xFUL << FPU_MVFR1_FP_fused_MAC_Pos) /*!< MVFR1: FP fused MAC bits Mask */ - -#define FPU_MVFR1_FP_HPFP_Pos 24U /*!< MVFR1: FP HPFP bits Position */ -#define FPU_MVFR1_FP_HPFP_Msk (0xFUL << FPU_MVFR1_FP_HPFP_Pos) /*!< MVFR1: FP HPFP bits Mask */ - -#define FPU_MVFR1_D_NaN_mode_Pos 4U /*!< MVFR1: D_NaN mode bits Position */ -#define FPU_MVFR1_D_NaN_mode_Msk (0xFUL << FPU_MVFR1_D_NaN_mode_Pos) /*!< MVFR1: D_NaN mode bits Mask */ - -#define FPU_MVFR1_FtZ_mode_Pos 0U /*!< MVFR1: FtZ mode bits Position */ -#define FPU_MVFR1_FtZ_mode_Msk (0xFUL /*<< FPU_MVFR1_FtZ_mode_Pos*/) /*!< MVFR1: FtZ mode bits Mask */ - -/*@} end of group CMSIS_FPU */ - - -/** - \ingroup CMSIS_core_register - \defgroup CMSIS_CoreDebug Core Debug Registers (CoreDebug) - \brief Type definitions for the Core Debug Registers - @{ - */ - -/** - \brief Structure type to access the Core Debug Register (CoreDebug). - */ -typedef struct -{ - __IOM uint32_t DHCSR; /*!< Offset: 0x000 (R/W) Debug Halting Control and Status Register */ - __OM uint32_t DCRSR; /*!< Offset: 0x004 ( /W) Debug Core Register Selector Register */ - __IOM uint32_t DCRDR; /*!< Offset: 0x008 (R/W) Debug Core Register Data Register */ - __IOM uint32_t DEMCR; /*!< Offset: 0x00C (R/W) Debug Exception and Monitor Control Register */ - uint32_t RESERVED4[1U]; - __IOM uint32_t DAUTHCTRL; /*!< Offset: 0x014 (R/W) Debug Authentication Control Register */ - __IOM uint32_t DSCSR; /*!< Offset: 0x018 (R/W) Debug Security Control and Status Register */ -} CoreDebug_Type; - -/* Debug Halting Control and Status Register Definitions */ -#define CoreDebug_DHCSR_DBGKEY_Pos 16U /*!< CoreDebug DHCSR: DBGKEY Position */ -#define CoreDebug_DHCSR_DBGKEY_Msk (0xFFFFUL << CoreDebug_DHCSR_DBGKEY_Pos) /*!< CoreDebug DHCSR: DBGKEY Mask */ - -#define CoreDebug_DHCSR_S_RESTART_ST_Pos 26U /*!< CoreDebug DHCSR: S_RESTART_ST Position */ -#define CoreDebug_DHCSR_S_RESTART_ST_Msk (1UL << CoreDebug_DHCSR_S_RESTART_ST_Pos) /*!< CoreDebug DHCSR: S_RESTART_ST Mask */ - -#define CoreDebug_DHCSR_S_RESET_ST_Pos 25U /*!< CoreDebug DHCSR: S_RESET_ST Position */ -#define CoreDebug_DHCSR_S_RESET_ST_Msk (1UL << CoreDebug_DHCSR_S_RESET_ST_Pos) /*!< CoreDebug DHCSR: S_RESET_ST Mask */ - -#define CoreDebug_DHCSR_S_RETIRE_ST_Pos 24U /*!< CoreDebug DHCSR: S_RETIRE_ST Position */ -#define CoreDebug_DHCSR_S_RETIRE_ST_Msk (1UL << CoreDebug_DHCSR_S_RETIRE_ST_Pos) /*!< CoreDebug DHCSR: S_RETIRE_ST Mask */ - -#define CoreDebug_DHCSR_S_LOCKUP_Pos 19U /*!< CoreDebug DHCSR: S_LOCKUP Position */ -#define CoreDebug_DHCSR_S_LOCKUP_Msk (1UL << CoreDebug_DHCSR_S_LOCKUP_Pos) /*!< CoreDebug DHCSR: S_LOCKUP Mask */ - -#define CoreDebug_DHCSR_S_SLEEP_Pos 18U /*!< CoreDebug DHCSR: S_SLEEP Position */ -#define CoreDebug_DHCSR_S_SLEEP_Msk (1UL << CoreDebug_DHCSR_S_SLEEP_Pos) /*!< CoreDebug DHCSR: S_SLEEP Mask */ - -#define CoreDebug_DHCSR_S_HALT_Pos 17U /*!< CoreDebug DHCSR: S_HALT Position */ -#define CoreDebug_DHCSR_S_HALT_Msk (1UL << CoreDebug_DHCSR_S_HALT_Pos) /*!< CoreDebug DHCSR: S_HALT Mask */ - -#define CoreDebug_DHCSR_S_REGRDY_Pos 16U /*!< CoreDebug DHCSR: S_REGRDY Position */ -#define CoreDebug_DHCSR_S_REGRDY_Msk (1UL << CoreDebug_DHCSR_S_REGRDY_Pos) /*!< CoreDebug DHCSR: S_REGRDY Mask */ - -#define CoreDebug_DHCSR_C_SNAPSTALL_Pos 5U /*!< CoreDebug DHCSR: C_SNAPSTALL Position */ -#define CoreDebug_DHCSR_C_SNAPSTALL_Msk (1UL << CoreDebug_DHCSR_C_SNAPSTALL_Pos) /*!< CoreDebug DHCSR: C_SNAPSTALL Mask */ - -#define CoreDebug_DHCSR_C_MASKINTS_Pos 3U /*!< CoreDebug DHCSR: C_MASKINTS Position */ -#define CoreDebug_DHCSR_C_MASKINTS_Msk (1UL << CoreDebug_DHCSR_C_MASKINTS_Pos) /*!< CoreDebug DHCSR: C_MASKINTS Mask */ - -#define CoreDebug_DHCSR_C_STEP_Pos 2U /*!< CoreDebug DHCSR: C_STEP Position */ -#define CoreDebug_DHCSR_C_STEP_Msk (1UL << CoreDebug_DHCSR_C_STEP_Pos) /*!< CoreDebug DHCSR: C_STEP Mask */ - -#define CoreDebug_DHCSR_C_HALT_Pos 1U /*!< CoreDebug DHCSR: C_HALT Position */ -#define CoreDebug_DHCSR_C_HALT_Msk (1UL << CoreDebug_DHCSR_C_HALT_Pos) /*!< CoreDebug DHCSR: C_HALT Mask */ - -#define CoreDebug_DHCSR_C_DEBUGEN_Pos 0U /*!< CoreDebug DHCSR: C_DEBUGEN Position */ -#define CoreDebug_DHCSR_C_DEBUGEN_Msk (1UL /*<< CoreDebug_DHCSR_C_DEBUGEN_Pos*/) /*!< CoreDebug DHCSR: C_DEBUGEN Mask */ - -/* Debug Core Register Selector Register Definitions */ -#define CoreDebug_DCRSR_REGWnR_Pos 16U /*!< CoreDebug DCRSR: REGWnR Position */ -#define CoreDebug_DCRSR_REGWnR_Msk (1UL << CoreDebug_DCRSR_REGWnR_Pos) /*!< CoreDebug DCRSR: REGWnR Mask */ - -#define CoreDebug_DCRSR_REGSEL_Pos 0U /*!< CoreDebug DCRSR: REGSEL Position */ -#define CoreDebug_DCRSR_REGSEL_Msk (0x1FUL /*<< CoreDebug_DCRSR_REGSEL_Pos*/) /*!< CoreDebug DCRSR: REGSEL Mask */ - -/* Debug Exception and Monitor Control Register Definitions */ -#define CoreDebug_DEMCR_TRCENA_Pos 24U /*!< CoreDebug DEMCR: TRCENA Position */ -#define CoreDebug_DEMCR_TRCENA_Msk (1UL << CoreDebug_DEMCR_TRCENA_Pos) /*!< CoreDebug DEMCR: TRCENA Mask */ - -#define CoreDebug_DEMCR_MON_REQ_Pos 19U /*!< CoreDebug DEMCR: MON_REQ Position */ -#define CoreDebug_DEMCR_MON_REQ_Msk (1UL << CoreDebug_DEMCR_MON_REQ_Pos) /*!< CoreDebug DEMCR: MON_REQ Mask */ - -#define CoreDebug_DEMCR_MON_STEP_Pos 18U /*!< CoreDebug DEMCR: MON_STEP Position */ -#define CoreDebug_DEMCR_MON_STEP_Msk (1UL << CoreDebug_DEMCR_MON_STEP_Pos) /*!< CoreDebug DEMCR: MON_STEP Mask */ - -#define CoreDebug_DEMCR_MON_PEND_Pos 17U /*!< CoreDebug DEMCR: MON_PEND Position */ -#define CoreDebug_DEMCR_MON_PEND_Msk (1UL << CoreDebug_DEMCR_MON_PEND_Pos) /*!< CoreDebug DEMCR: MON_PEND Mask */ - -#define CoreDebug_DEMCR_MON_EN_Pos 16U /*!< CoreDebug DEMCR: MON_EN Position */ -#define CoreDebug_DEMCR_MON_EN_Msk (1UL << CoreDebug_DEMCR_MON_EN_Pos) /*!< CoreDebug DEMCR: MON_EN Mask */ - -#define CoreDebug_DEMCR_VC_HARDERR_Pos 10U /*!< CoreDebug DEMCR: VC_HARDERR Position */ -#define CoreDebug_DEMCR_VC_HARDERR_Msk (1UL << CoreDebug_DEMCR_VC_HARDERR_Pos) /*!< CoreDebug DEMCR: VC_HARDERR Mask */ - -#define CoreDebug_DEMCR_VC_INTERR_Pos 9U /*!< CoreDebug DEMCR: VC_INTERR Position */ -#define CoreDebug_DEMCR_VC_INTERR_Msk (1UL << CoreDebug_DEMCR_VC_INTERR_Pos) /*!< CoreDebug DEMCR: VC_INTERR Mask */ - -#define CoreDebug_DEMCR_VC_BUSERR_Pos 8U /*!< CoreDebug DEMCR: VC_BUSERR Position */ -#define CoreDebug_DEMCR_VC_BUSERR_Msk (1UL << CoreDebug_DEMCR_VC_BUSERR_Pos) /*!< CoreDebug DEMCR: VC_BUSERR Mask */ - -#define CoreDebug_DEMCR_VC_STATERR_Pos 7U /*!< CoreDebug DEMCR: VC_STATERR Position */ -#define CoreDebug_DEMCR_VC_STATERR_Msk (1UL << CoreDebug_DEMCR_VC_STATERR_Pos) /*!< CoreDebug DEMCR: VC_STATERR Mask */ - -#define CoreDebug_DEMCR_VC_CHKERR_Pos 6U /*!< CoreDebug DEMCR: VC_CHKERR Position */ -#define CoreDebug_DEMCR_VC_CHKERR_Msk (1UL << CoreDebug_DEMCR_VC_CHKERR_Pos) /*!< CoreDebug DEMCR: VC_CHKERR Mask */ - -#define CoreDebug_DEMCR_VC_NOCPERR_Pos 5U /*!< CoreDebug DEMCR: VC_NOCPERR Position */ -#define CoreDebug_DEMCR_VC_NOCPERR_Msk (1UL << CoreDebug_DEMCR_VC_NOCPERR_Pos) /*!< CoreDebug DEMCR: VC_NOCPERR Mask */ - -#define CoreDebug_DEMCR_VC_MMERR_Pos 4U /*!< CoreDebug DEMCR: VC_MMERR Position */ -#define CoreDebug_DEMCR_VC_MMERR_Msk (1UL << CoreDebug_DEMCR_VC_MMERR_Pos) /*!< CoreDebug DEMCR: VC_MMERR Mask */ - -#define CoreDebug_DEMCR_VC_CORERESET_Pos 0U /*!< CoreDebug DEMCR: VC_CORERESET Position */ -#define CoreDebug_DEMCR_VC_CORERESET_Msk (1UL /*<< CoreDebug_DEMCR_VC_CORERESET_Pos*/) /*!< CoreDebug DEMCR: VC_CORERESET Mask */ - -/* Debug Authentication Control Register Definitions */ -#define CoreDebug_DAUTHCTRL_INTSPNIDEN_Pos 3U /*!< CoreDebug DAUTHCTRL: INTSPNIDEN, Position */ -#define CoreDebug_DAUTHCTRL_INTSPNIDEN_Msk (1UL << CoreDebug_DAUTHCTRL_INTSPNIDEN_Pos) /*!< CoreDebug DAUTHCTRL: INTSPNIDEN, Mask */ - -#define CoreDebug_DAUTHCTRL_SPNIDENSEL_Pos 2U /*!< CoreDebug DAUTHCTRL: SPNIDENSEL Position */ -#define CoreDebug_DAUTHCTRL_SPNIDENSEL_Msk (1UL << CoreDebug_DAUTHCTRL_SPNIDENSEL_Pos) /*!< CoreDebug DAUTHCTRL: SPNIDENSEL Mask */ - -#define CoreDebug_DAUTHCTRL_INTSPIDEN_Pos 1U /*!< CoreDebug DAUTHCTRL: INTSPIDEN Position */ -#define CoreDebug_DAUTHCTRL_INTSPIDEN_Msk (1UL << CoreDebug_DAUTHCTRL_INTSPIDEN_Pos) /*!< CoreDebug DAUTHCTRL: INTSPIDEN Mask */ - -#define CoreDebug_DAUTHCTRL_SPIDENSEL_Pos 0U /*!< CoreDebug DAUTHCTRL: SPIDENSEL Position */ -#define CoreDebug_DAUTHCTRL_SPIDENSEL_Msk (1UL /*<< CoreDebug_DAUTHCTRL_SPIDENSEL_Pos*/) /*!< CoreDebug DAUTHCTRL: SPIDENSEL Mask */ - -/* Debug Security Control and Status Register Definitions */ -#define CoreDebug_DSCSR_CDS_Pos 16U /*!< CoreDebug DSCSR: CDS Position */ -#define CoreDebug_DSCSR_CDS_Msk (1UL << CoreDebug_DSCSR_CDS_Pos) /*!< CoreDebug DSCSR: CDS Mask */ - -#define CoreDebug_DSCSR_SBRSEL_Pos 1U /*!< CoreDebug DSCSR: SBRSEL Position */ -#define CoreDebug_DSCSR_SBRSEL_Msk (1UL << CoreDebug_DSCSR_SBRSEL_Pos) /*!< CoreDebug DSCSR: SBRSEL Mask */ - -#define CoreDebug_DSCSR_SBRSELEN_Pos 0U /*!< CoreDebug DSCSR: SBRSELEN Position */ -#define CoreDebug_DSCSR_SBRSELEN_Msk (1UL /*<< CoreDebug_DSCSR_SBRSELEN_Pos*/) /*!< CoreDebug DSCSR: SBRSELEN Mask */ - -/*@} end of group CMSIS_CoreDebug */ - - -/** - \ingroup CMSIS_core_register - \defgroup CMSIS_core_bitfield Core register bit field macros - \brief Macros for use with bit field definitions (xxx_Pos, xxx_Msk). - @{ - */ - -/** - \brief Mask and shift a bit field value for use in a register bit range. - \param[in] field Name of the register bit field. - \param[in] value Value of the bit field. This parameter is interpreted as an uint32_t type. - \return Masked and shifted value. -*/ -#define _VAL2FLD(field, value) (((uint32_t)(value) << field ## _Pos) & field ## _Msk) - -/** - \brief Mask and shift a register value to extract a bit filed value. - \param[in] field Name of the register bit field. - \param[in] value Value of register. This parameter is interpreted as an uint32_t type. - \return Masked and shifted bit field value. -*/ -#define _FLD2VAL(field, value) (((uint32_t)(value) & field ## _Msk) >> field ## _Pos) - -/*@} end of group CMSIS_core_bitfield */ - - -/** - \ingroup CMSIS_core_register - \defgroup CMSIS_core_base Core Definitions - \brief Definitions for base addresses, unions, and structures. - @{ - */ - -/* Memory mapping of Core Hardware */ - #define SCS_BASE (0xE000E000UL) /*!< System Control Space Base Address */ - #define ITM_BASE (0xE0000000UL) /*!< ITM Base Address */ - #define DWT_BASE (0xE0001000UL) /*!< DWT Base Address */ - #define TPI_BASE (0xE0040000UL) /*!< TPI Base Address */ - #define CoreDebug_BASE (0xE000EDF0UL) /*!< Core Debug Base Address */ - #define SysTick_BASE (SCS_BASE + 0x0010UL) /*!< SysTick Base Address */ - #define NVIC_BASE (SCS_BASE + 0x0100UL) /*!< NVIC Base Address */ - #define SCB_BASE (SCS_BASE + 0x0D00UL) /*!< System Control Block Base Address */ - - #define SCnSCB ((SCnSCB_Type *) SCS_BASE ) /*!< System control Register not in SCB */ - #define SCB ((SCB_Type *) SCB_BASE ) /*!< SCB configuration struct */ - #define SysTick ((SysTick_Type *) SysTick_BASE ) /*!< SysTick configuration struct */ - #define NVIC ((NVIC_Type *) NVIC_BASE ) /*!< NVIC configuration struct */ - #define ITM ((ITM_Type *) ITM_BASE ) /*!< ITM configuration struct */ - #define DWT ((DWT_Type *) DWT_BASE ) /*!< DWT configuration struct */ - #define TPI ((TPI_Type *) TPI_BASE ) /*!< TPI configuration struct */ - #define CoreDebug ((CoreDebug_Type *) CoreDebug_BASE ) /*!< Core Debug configuration struct */ - - #if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) - #define MPU_BASE (SCS_BASE + 0x0D90UL) /*!< Memory Protection Unit */ - #define MPU ((MPU_Type *) MPU_BASE ) /*!< Memory Protection Unit */ - #endif - - #if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) - #define SAU_BASE (SCS_BASE + 0x0DD0UL) /*!< Security Attribution Unit */ - #define SAU ((SAU_Type *) SAU_BASE ) /*!< Security Attribution Unit */ - #endif - - #define FPU_BASE (SCS_BASE + 0x0F30UL) /*!< Floating Point Unit */ - #define FPU ((FPU_Type *) FPU_BASE ) /*!< Floating Point Unit */ - -#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) - #define SCS_BASE_NS (0xE002E000UL) /*!< System Control Space Base Address (non-secure address space) */ - #define CoreDebug_BASE_NS (0xE002EDF0UL) /*!< Core Debug Base Address (non-secure address space) */ - #define SysTick_BASE_NS (SCS_BASE_NS + 0x0010UL) /*!< SysTick Base Address (non-secure address space) */ - #define NVIC_BASE_NS (SCS_BASE_NS + 0x0100UL) /*!< NVIC Base Address (non-secure address space) */ - #define SCB_BASE_NS (SCS_BASE_NS + 0x0D00UL) /*!< System Control Block Base Address (non-secure address space) */ - - #define SCnSCB_NS ((SCnSCB_Type *) SCS_BASE_NS ) /*!< System control Register not in SCB(non-secure address space) */ - #define SCB_NS ((SCB_Type *) SCB_BASE_NS ) /*!< SCB configuration struct (non-secure address space) */ - #define SysTick_NS ((SysTick_Type *) SysTick_BASE_NS ) /*!< SysTick configuration struct (non-secure address space) */ - #define NVIC_NS ((NVIC_Type *) NVIC_BASE_NS ) /*!< NVIC configuration struct (non-secure address space) */ - #define CoreDebug_NS ((CoreDebug_Type *) CoreDebug_BASE_NS) /*!< Core Debug configuration struct (non-secure address space) */ - - #if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) - #define MPU_BASE_NS (SCS_BASE_NS + 0x0D90UL) /*!< Memory Protection Unit (non-secure address space) */ - #define MPU_NS ((MPU_Type *) MPU_BASE_NS ) /*!< Memory Protection Unit (non-secure address space) */ - #endif - - #define FPU_BASE_NS (SCS_BASE_NS + 0x0F30UL) /*!< Floating Point Unit (non-secure address space) */ - #define FPU_NS ((FPU_Type *) FPU_BASE_NS ) /*!< Floating Point Unit (non-secure address space) */ - -#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */ -/*@} */ - - - -/******************************************************************************* - * Hardware Abstraction Layer - Core Function Interface contains: - - Core NVIC Functions - - Core SysTick Functions - - Core Debug Functions - - Core Register Access Functions - ******************************************************************************/ -/** - \defgroup CMSIS_Core_FunctionInterface Functions and Instructions Reference -*/ - - - -/* ########################## NVIC functions #################################### */ -/** - \ingroup CMSIS_Core_FunctionInterface - \defgroup CMSIS_Core_NVICFunctions NVIC Functions - \brief Functions that manage interrupts and exceptions via the NVIC. - @{ - */ - -#ifdef CMSIS_NVIC_VIRTUAL - #ifndef CMSIS_NVIC_VIRTUAL_HEADER_FILE - #define CMSIS_NVIC_VIRTUAL_HEADER_FILE "cmsis_nvic_virtual.h" - #endif - #include CMSIS_NVIC_VIRTUAL_HEADER_FILE -#else - #define NVIC_SetPriorityGrouping __NVIC_SetPriorityGrouping - #define NVIC_GetPriorityGrouping __NVIC_GetPriorityGrouping - #define NVIC_EnableIRQ __NVIC_EnableIRQ - #define NVIC_GetEnableIRQ __NVIC_GetEnableIRQ - #define NVIC_DisableIRQ __NVIC_DisableIRQ - #define NVIC_GetPendingIRQ __NVIC_GetPendingIRQ - #define NVIC_SetPendingIRQ __NVIC_SetPendingIRQ - #define NVIC_ClearPendingIRQ __NVIC_ClearPendingIRQ - #define NVIC_GetActive __NVIC_GetActive - #define NVIC_SetPriority __NVIC_SetPriority - #define NVIC_GetPriority __NVIC_GetPriority - #define NVIC_SystemReset __NVIC_SystemReset -#endif /* CMSIS_NVIC_VIRTUAL */ - -#ifdef CMSIS_VECTAB_VIRTUAL - #ifndef CMSIS_VECTAB_VIRTUAL_HEADER_FILE - #define CMSIS_VECTAB_VIRTUAL_HEADER_FILE "cmsis_vectab_virtual.h" - #endif - #include CMSIS_VECTAB_VIRTUAL_HEADER_FILE -#else - #define NVIC_SetVector __NVIC_SetVector - #define NVIC_GetVector __NVIC_GetVector -#endif /* (CMSIS_VECTAB_VIRTUAL) */ - -#define NVIC_USER_IRQ_OFFSET 16 - - - -/** - \brief Set Priority Grouping - \details Sets the priority grouping field using the required unlock sequence. - The parameter PriorityGroup is assigned to the field SCB->AIRCR [10:8] PRIGROUP field. - Only values from 0..7 are used. - In case of a conflict between priority grouping and available - priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set. - \param [in] PriorityGroup Priority grouping field. - */ -__STATIC_INLINE void __NVIC_SetPriorityGrouping(uint32_t PriorityGroup) -{ - uint32_t reg_value; - uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ - - reg_value = SCB->AIRCR; /* read old register configuration */ - reg_value &= ~((uint32_t)(SCB_AIRCR_VECTKEY_Msk | SCB_AIRCR_PRIGROUP_Msk)); /* clear bits to change */ - reg_value = (reg_value | - ((uint32_t)0x5FAUL << SCB_AIRCR_VECTKEY_Pos) | - (PriorityGroupTmp << 8U) ); /* Insert write key and priority group */ - SCB->AIRCR = reg_value; -} - - -/** - \brief Get Priority Grouping - \details Reads the priority grouping field from the NVIC Interrupt Controller. - \return Priority grouping field (SCB->AIRCR [10:8] PRIGROUP field). - */ -__STATIC_INLINE uint32_t __NVIC_GetPriorityGrouping(void) -{ - return ((uint32_t)((SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) >> SCB_AIRCR_PRIGROUP_Pos)); -} - - -/** - \brief Enable Interrupt - \details Enables a device specific interrupt in the NVIC interrupt controller. - \param [in] IRQn Device specific interrupt number. - \note IRQn must not be negative. - */ -__STATIC_INLINE void __NVIC_EnableIRQ(IRQn_Type IRQn) -{ - if ((int32_t)(IRQn) >= 0) - { - NVIC->ISER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); - } -} - - -/** - \brief Get Interrupt Enable status - \details Returns a device specific interrupt enable status from the NVIC interrupt controller. - \param [in] IRQn Device specific interrupt number. - \return 0 Interrupt is not enabled. - \return 1 Interrupt is enabled. - \note IRQn must not be negative. - */ -__STATIC_INLINE uint32_t __NVIC_GetEnableIRQ(IRQn_Type IRQn) -{ - if ((int32_t)(IRQn) >= 0) - { - return((uint32_t)(((NVIC->ISER[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); - } - else - { - return(0U); - } -} - - -/** - \brief Disable Interrupt - \details Disables a device specific interrupt in the NVIC interrupt controller. - \param [in] IRQn Device specific interrupt number. - \note IRQn must not be negative. - */ -__STATIC_INLINE void __NVIC_DisableIRQ(IRQn_Type IRQn) -{ - if ((int32_t)(IRQn) >= 0) - { - NVIC->ICER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); - __DSB(); - __ISB(); - } -} - - -/** - \brief Get Pending Interrupt - \details Reads the NVIC pending register and returns the pending bit for the specified device specific interrupt. - \param [in] IRQn Device specific interrupt number. - \return 0 Interrupt status is not pending. - \return 1 Interrupt status is pending. - \note IRQn must not be negative. - */ -__STATIC_INLINE uint32_t __NVIC_GetPendingIRQ(IRQn_Type IRQn) -{ - if ((int32_t)(IRQn) >= 0) - { - return((uint32_t)(((NVIC->ISPR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); - } - else - { - return(0U); - } -} - - -/** - \brief Set Pending Interrupt - \details Sets the pending bit of a device specific interrupt in the NVIC pending register. - \param [in] IRQn Device specific interrupt number. - \note IRQn must not be negative. - */ -__STATIC_INLINE void __NVIC_SetPendingIRQ(IRQn_Type IRQn) -{ - if ((int32_t)(IRQn) >= 0) - { - NVIC->ISPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); - } -} - - -/** - \brief Clear Pending Interrupt - \details Clears the pending bit of a device specific interrupt in the NVIC pending register. - \param [in] IRQn Device specific interrupt number. - \note IRQn must not be negative. - */ -__STATIC_INLINE void __NVIC_ClearPendingIRQ(IRQn_Type IRQn) -{ - if ((int32_t)(IRQn) >= 0) - { - NVIC->ICPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); - } -} - - -/** - \brief Get Active Interrupt - \details Reads the active register in the NVIC and returns the active bit for the device specific interrupt. - \param [in] IRQn Device specific interrupt number. - \return 0 Interrupt status is not active. - \return 1 Interrupt status is active. - \note IRQn must not be negative. - */ -__STATIC_INLINE uint32_t __NVIC_GetActive(IRQn_Type IRQn) -{ - if ((int32_t)(IRQn) >= 0) - { - return((uint32_t)(((NVIC->IABR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); - } - else - { - return(0U); - } -} - - -#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) -/** - \brief Get Interrupt Target State - \details Reads the interrupt target field in the NVIC and returns the interrupt target bit for the device specific interrupt. - \param [in] IRQn Device specific interrupt number. - \return 0 if interrupt is assigned to Secure - \return 1 if interrupt is assigned to Non Secure - \note IRQn must not be negative. - */ -__STATIC_INLINE uint32_t NVIC_GetTargetState(IRQn_Type IRQn) -{ - if ((int32_t)(IRQn) >= 0) - { - return((uint32_t)(((NVIC->ITNS[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); - } - else - { - return(0U); - } -} - - -/** - \brief Set Interrupt Target State - \details Sets the interrupt target field in the NVIC and returns the interrupt target bit for the device specific interrupt. - \param [in] IRQn Device specific interrupt number. - \return 0 if interrupt is assigned to Secure - 1 if interrupt is assigned to Non Secure - \note IRQn must not be negative. - */ -__STATIC_INLINE uint32_t NVIC_SetTargetState(IRQn_Type IRQn) -{ - if ((int32_t)(IRQn) >= 0) - { - NVIC->ITNS[(((uint32_t)IRQn) >> 5UL)] |= ((uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL))); - return((uint32_t)(((NVIC->ITNS[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); - } - else - { - return(0U); - } -} - - -/** - \brief Clear Interrupt Target State - \details Clears the interrupt target field in the NVIC and returns the interrupt target bit for the device specific interrupt. - \param [in] IRQn Device specific interrupt number. - \return 0 if interrupt is assigned to Secure - 1 if interrupt is assigned to Non Secure - \note IRQn must not be negative. - */ -__STATIC_INLINE uint32_t NVIC_ClearTargetState(IRQn_Type IRQn) -{ - if ((int32_t)(IRQn) >= 0) - { - NVIC->ITNS[(((uint32_t)IRQn) >> 5UL)] &= ~((uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL))); - return((uint32_t)(((NVIC->ITNS[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); - } - else - { - return(0U); - } -} -#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */ - - -/** - \brief Set Interrupt Priority - \details Sets the priority of a device specific interrupt or a processor exception. - The interrupt number can be positive to specify a device specific interrupt, - or negative to specify a processor exception. - \param [in] IRQn Interrupt number. - \param [in] priority Priority to set. - \note The priority cannot be set for every processor exception. - */ -__STATIC_INLINE void __NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority) -{ - if ((int32_t)(IRQn) >= 0) - { - NVIC->IPR[((uint32_t)IRQn)] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL); - } - else - { - SCB->SHPR[(((uint32_t)IRQn) & 0xFUL)-4UL] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL); - } -} - - -/** - \brief Get Interrupt Priority - \details Reads the priority of a device specific interrupt or a processor exception. - The interrupt number can be positive to specify a device specific interrupt, - or negative to specify a processor exception. - \param [in] IRQn Interrupt number. - \return Interrupt Priority. - Value is aligned automatically to the implemented priority bits of the microcontroller. - */ -__STATIC_INLINE uint32_t __NVIC_GetPriority(IRQn_Type IRQn) -{ - - if ((int32_t)(IRQn) >= 0) - { - return(((uint32_t)NVIC->IPR[((uint32_t)IRQn)] >> (8U - __NVIC_PRIO_BITS))); - } - else - { - return(((uint32_t)SCB->SHPR[(((uint32_t)IRQn) & 0xFUL)-4UL] >> (8U - __NVIC_PRIO_BITS))); - } -} - - -/** - \brief Encode Priority - \details Encodes the priority for an interrupt with the given priority group, - preemptive priority value, and subpriority value. - In case of a conflict between priority grouping and available - priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set. - \param [in] PriorityGroup Used priority group. - \param [in] PreemptPriority Preemptive priority value (starting from 0). - \param [in] SubPriority Subpriority value (starting from 0). - \return Encoded priority. Value can be used in the function \ref NVIC_SetPriority(). - */ -__STATIC_INLINE uint32_t NVIC_EncodePriority (uint32_t PriorityGroup, uint32_t PreemptPriority, uint32_t SubPriority) -{ - uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ - uint32_t PreemptPriorityBits; - uint32_t SubPriorityBits; - - PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp); - SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS)); - - return ( - ((PreemptPriority & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL)) << SubPriorityBits) | - ((SubPriority & (uint32_t)((1UL << (SubPriorityBits )) - 1UL))) - ); -} - - -/** - \brief Decode Priority - \details Decodes an interrupt priority value with a given priority group to - preemptive priority value and subpriority value. - In case of a conflict between priority grouping and available - priority bits (__NVIC_PRIO_BITS) the smallest possible priority group is set. - \param [in] Priority Priority value, which can be retrieved with the function \ref NVIC_GetPriority(). - \param [in] PriorityGroup Used priority group. - \param [out] pPreemptPriority Preemptive priority value (starting from 0). - \param [out] pSubPriority Subpriority value (starting from 0). - */ -__STATIC_INLINE void NVIC_DecodePriority (uint32_t Priority, uint32_t PriorityGroup, uint32_t* const pPreemptPriority, uint32_t* const pSubPriority) -{ - uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ - uint32_t PreemptPriorityBits; - uint32_t SubPriorityBits; - - PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp); - SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS)); - - *pPreemptPriority = (Priority >> SubPriorityBits) & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL); - *pSubPriority = (Priority ) & (uint32_t)((1UL << (SubPriorityBits )) - 1UL); -} - - -/** - \brief Set Interrupt Vector - \details Sets an interrupt vector in SRAM based interrupt vector table. - The interrupt number can be positive to specify a device specific interrupt, - or negative to specify a processor exception. - VTOR must been relocated to SRAM before. - \param [in] IRQn Interrupt number - \param [in] vector Address of interrupt handler function - */ -__STATIC_INLINE void __NVIC_SetVector(IRQn_Type IRQn, uint32_t vector) -{ - uint32_t *vectors = (uint32_t *)SCB->VTOR; - vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET] = vector; -} - - -/** - \brief Get Interrupt Vector - \details Reads an interrupt vector from interrupt vector table. - The interrupt number can be positive to specify a device specific interrupt, - or negative to specify a processor exception. - \param [in] IRQn Interrupt number. - \return Address of interrupt handler function - */ -__STATIC_INLINE uint32_t __NVIC_GetVector(IRQn_Type IRQn) -{ - uint32_t *vectors = (uint32_t *)SCB->VTOR; - return vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET]; -} - - -/** - \brief System Reset - \details Initiates a system reset request to reset the MCU. - */ -__STATIC_INLINE void __NVIC_SystemReset(void) -{ - __DSB(); /* Ensure all outstanding memory accesses included - buffered write are completed before reset */ - SCB->AIRCR = (uint32_t)((0x5FAUL << SCB_AIRCR_VECTKEY_Pos) | - (SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) | - SCB_AIRCR_SYSRESETREQ_Msk ); /* Keep priority group unchanged */ - __DSB(); /* Ensure completion of memory access */ - - for(;;) /* wait until reset */ - { - __NOP(); - } -} - -#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) -/** - \brief Set Priority Grouping (non-secure) - \details Sets the non-secure priority grouping field when in secure state using the required unlock sequence. - The parameter PriorityGroup is assigned to the field SCB->AIRCR [10:8] PRIGROUP field. - Only values from 0..7 are used. - In case of a conflict between priority grouping and available - priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set. - \param [in] PriorityGroup Priority grouping field. - */ -__STATIC_INLINE void TZ_NVIC_SetPriorityGrouping_NS(uint32_t PriorityGroup) -{ - uint32_t reg_value; - uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ - - reg_value = SCB_NS->AIRCR; /* read old register configuration */ - reg_value &= ~((uint32_t)(SCB_AIRCR_VECTKEY_Msk | SCB_AIRCR_PRIGROUP_Msk)); /* clear bits to change */ - reg_value = (reg_value | - ((uint32_t)0x5FAUL << SCB_AIRCR_VECTKEY_Pos) | - (PriorityGroupTmp << SCB_AIRCR_PRIGROUP_Pos) ); /* Insert write key and priority group */ - SCB_NS->AIRCR = reg_value; -} - - -/** - \brief Get Priority Grouping (non-secure) - \details Reads the priority grouping field from the non-secure NVIC when in secure state. - \return Priority grouping field (SCB->AIRCR [10:8] PRIGROUP field). - */ -__STATIC_INLINE uint32_t TZ_NVIC_GetPriorityGrouping_NS(void) -{ - return ((uint32_t)((SCB_NS->AIRCR & SCB_AIRCR_PRIGROUP_Msk) >> SCB_AIRCR_PRIGROUP_Pos)); -} - - -/** - \brief Enable Interrupt (non-secure) - \details Enables a device specific interrupt in the non-secure NVIC interrupt controller when in secure state. - \param [in] IRQn Device specific interrupt number. - \note IRQn must not be negative. - */ -__STATIC_INLINE void TZ_NVIC_EnableIRQ_NS(IRQn_Type IRQn) -{ - if ((int32_t)(IRQn) >= 0) - { - NVIC_NS->ISER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); - } -} - - -/** - \brief Get Interrupt Enable status (non-secure) - \details Returns a device specific interrupt enable status from the non-secure NVIC interrupt controller when in secure state. - \param [in] IRQn Device specific interrupt number. - \return 0 Interrupt is not enabled. - \return 1 Interrupt is enabled. - \note IRQn must not be negative. - */ -__STATIC_INLINE uint32_t TZ_NVIC_GetEnableIRQ_NS(IRQn_Type IRQn) -{ - if ((int32_t)(IRQn) >= 0) - { - return((uint32_t)(((NVIC_NS->ISER[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); - } - else - { - return(0U); - } -} - - -/** - \brief Disable Interrupt (non-secure) - \details Disables a device specific interrupt in the non-secure NVIC interrupt controller when in secure state. - \param [in] IRQn Device specific interrupt number. - \note IRQn must not be negative. - */ -__STATIC_INLINE void TZ_NVIC_DisableIRQ_NS(IRQn_Type IRQn) -{ - if ((int32_t)(IRQn) >= 0) - { - NVIC_NS->ICER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); - } -} - - -/** - \brief Get Pending Interrupt (non-secure) - \details Reads the NVIC pending register in the non-secure NVIC when in secure state and returns the pending bit for the specified device specific interrupt. - \param [in] IRQn Device specific interrupt number. - \return 0 Interrupt status is not pending. - \return 1 Interrupt status is pending. - \note IRQn must not be negative. - */ -__STATIC_INLINE uint32_t TZ_NVIC_GetPendingIRQ_NS(IRQn_Type IRQn) -{ - if ((int32_t)(IRQn) >= 0) - { - return((uint32_t)(((NVIC_NS->ISPR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); - } - else - { - return(0U); - } -} - - -/** - \brief Set Pending Interrupt (non-secure) - \details Sets the pending bit of a device specific interrupt in the non-secure NVIC pending register when in secure state. - \param [in] IRQn Device specific interrupt number. - \note IRQn must not be negative. - */ -__STATIC_INLINE void TZ_NVIC_SetPendingIRQ_NS(IRQn_Type IRQn) -{ - if ((int32_t)(IRQn) >= 0) - { - NVIC_NS->ISPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); - } -} - - -/** - \brief Clear Pending Interrupt (non-secure) - \details Clears the pending bit of a device specific interrupt in the non-secure NVIC pending register when in secure state. - \param [in] IRQn Device specific interrupt number. - \note IRQn must not be negative. - */ -__STATIC_INLINE void TZ_NVIC_ClearPendingIRQ_NS(IRQn_Type IRQn) -{ - if ((int32_t)(IRQn) >= 0) - { - NVIC_NS->ICPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); - } -} - - -/** - \brief Get Active Interrupt (non-secure) - \details Reads the active register in non-secure NVIC when in secure state and returns the active bit for the device specific interrupt. - \param [in] IRQn Device specific interrupt number. - \return 0 Interrupt status is not active. - \return 1 Interrupt status is active. - \note IRQn must not be negative. - */ -__STATIC_INLINE uint32_t TZ_NVIC_GetActive_NS(IRQn_Type IRQn) -{ - if ((int32_t)(IRQn) >= 0) - { - return((uint32_t)(((NVIC_NS->IABR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); - } - else - { - return(0U); - } -} - - -/** - \brief Set Interrupt Priority (non-secure) - \details Sets the priority of a non-secure device specific interrupt or a non-secure processor exception when in secure state. - The interrupt number can be positive to specify a device specific interrupt, - or negative to specify a processor exception. - \param [in] IRQn Interrupt number. - \param [in] priority Priority to set. - \note The priority cannot be set for every non-secure processor exception. - */ -__STATIC_INLINE void TZ_NVIC_SetPriority_NS(IRQn_Type IRQn, uint32_t priority) -{ - if ((int32_t)(IRQn) >= 0) - { - NVIC_NS->IPR[((uint32_t)IRQn)] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL); - } - else - { - SCB_NS->SHPR[(((uint32_t)IRQn) & 0xFUL)-4UL] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL); - } -} - - -/** - \brief Get Interrupt Priority (non-secure) - \details Reads the priority of a non-secure device specific interrupt or a non-secure processor exception when in secure state. - The interrupt number can be positive to specify a device specific interrupt, - or negative to specify a processor exception. - \param [in] IRQn Interrupt number. - \return Interrupt Priority. Value is aligned automatically to the implemented priority bits of the microcontroller. - */ -__STATIC_INLINE uint32_t TZ_NVIC_GetPriority_NS(IRQn_Type IRQn) -{ - - if ((int32_t)(IRQn) >= 0) - { - return(((uint32_t)NVIC_NS->IPR[((uint32_t)IRQn)] >> (8U - __NVIC_PRIO_BITS))); - } - else - { - return(((uint32_t)SCB_NS->SHPR[(((uint32_t)IRQn) & 0xFUL)-4UL] >> (8U - __NVIC_PRIO_BITS))); - } -} -#endif /* defined (__ARM_FEATURE_CMSE) &&(__ARM_FEATURE_CMSE == 3U) */ - -/*@} end of CMSIS_Core_NVICFunctions */ - -/* ########################## MPU functions #################################### */ - -#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) - -#include "mpu_armv8.h" - -#endif - -/* ########################## FPU functions #################################### */ -/** - \ingroup CMSIS_Core_FunctionInterface - \defgroup CMSIS_Core_FpuFunctions FPU Functions - \brief Function that provides FPU type. - @{ - */ - -/** - \brief get FPU type - \details returns the FPU type - \returns - - \b 0: No FPU - - \b 1: Single precision FPU - - \b 2: Double + Single precision FPU - */ -__STATIC_INLINE uint32_t SCB_GetFPUType(void) -{ - uint32_t mvfr0; - - mvfr0 = FPU->MVFR0; - if ((mvfr0 & (FPU_MVFR0_Single_precision_Msk | FPU_MVFR0_Double_precision_Msk)) == 0x220U) - { - return 2U; /* Double + Single precision FPU */ - } - else if ((mvfr0 & (FPU_MVFR0_Single_precision_Msk | FPU_MVFR0_Double_precision_Msk)) == 0x020U) - { - return 1U; /* Single precision FPU */ - } - else - { - return 0U; /* No FPU */ - } -} - - -/*@} end of CMSIS_Core_FpuFunctions */ - - - -/* ########################## SAU functions #################################### */ -/** - \ingroup CMSIS_Core_FunctionInterface - \defgroup CMSIS_Core_SAUFunctions SAU Functions - \brief Functions that configure the SAU. - @{ - */ - -#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) - -/** - \brief Enable SAU - \details Enables the Security Attribution Unit (SAU). - */ -__STATIC_INLINE void TZ_SAU_Enable(void) -{ - SAU->CTRL |= (SAU_CTRL_ENABLE_Msk); -} - - - -/** - \brief Disable SAU - \details Disables the Security Attribution Unit (SAU). - */ -__STATIC_INLINE void TZ_SAU_Disable(void) -{ - SAU->CTRL &= ~(SAU_CTRL_ENABLE_Msk); -} - -#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */ - -/*@} end of CMSIS_Core_SAUFunctions */ - - - - -/* ################################## SysTick function ############################################ */ -/** - \ingroup CMSIS_Core_FunctionInterface - \defgroup CMSIS_Core_SysTickFunctions SysTick Functions - \brief Functions that configure the System. - @{ - */ - -#if defined (__Vendor_SysTickConfig) && (__Vendor_SysTickConfig == 0U) - -/** - \brief System Tick Configuration - \details Initializes the System Timer and its interrupt, and starts the System Tick Timer. - Counter is in free running mode to generate periodic interrupts. - \param [in] ticks Number of ticks between two interrupts. - \return 0 Function succeeded. - \return 1 Function failed. - \note When the variable __Vendor_SysTickConfig is set to 1, then the - function SysTick_Config is not included. In this case, the file device.h - must contain a vendor-specific implementation of this function. - */ -__STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks) -{ - if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk) - { - return (1UL); /* Reload value impossible */ - } - - SysTick->LOAD = (uint32_t)(ticks - 1UL); /* set reload register */ - NVIC_SetPriority (SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */ - SysTick->VAL = 0UL; /* Load the SysTick Counter Value */ - SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk | - SysTick_CTRL_TICKINT_Msk | - SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */ - return (0UL); /* Function successful */ -} - -#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) -/** - \brief System Tick Configuration (non-secure) - \details Initializes the non-secure System Timer and its interrupt when in secure state, and starts the System Tick Timer. - Counter is in free running mode to generate periodic interrupts. - \param [in] ticks Number of ticks between two interrupts. - \return 0 Function succeeded. - \return 1 Function failed. - \note When the variable __Vendor_SysTickConfig is set to 1, then the - function TZ_SysTick_Config_NS is not included. In this case, the file device.h - must contain a vendor-specific implementation of this function. - - */ -__STATIC_INLINE uint32_t TZ_SysTick_Config_NS(uint32_t ticks) -{ - if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk) - { - return (1UL); /* Reload value impossible */ - } - - SysTick_NS->LOAD = (uint32_t)(ticks - 1UL); /* set reload register */ - TZ_NVIC_SetPriority_NS (SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */ - SysTick_NS->VAL = 0UL; /* Load the SysTick Counter Value */ - SysTick_NS->CTRL = SysTick_CTRL_CLKSOURCE_Msk | - SysTick_CTRL_TICKINT_Msk | - SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */ - return (0UL); /* Function successful */ -} -#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */ - -#endif - -/*@} end of CMSIS_Core_SysTickFunctions */ - - - -/* ##################################### Debug In/Output function ########################################### */ -/** - \ingroup CMSIS_Core_FunctionInterface - \defgroup CMSIS_core_DebugFunctions ITM Functions - \brief Functions that access the ITM debug interface. - @{ - */ - -extern volatile int32_t ITM_RxBuffer; /*!< External variable to receive characters. */ -#define ITM_RXBUFFER_EMPTY ((int32_t)0x5AA55AA5U) /*!< Value identifying \ref ITM_RxBuffer is ready for next character. */ - - -/** - \brief ITM Send Character - \details Transmits a character via the ITM channel 0, and - \li Just returns when no debugger is connected that has booked the output. - \li Is blocking when a debugger is connected, but the previous character sent has not been transmitted. - \param [in] ch Character to transmit. - \returns Character to transmit. - */ -__STATIC_INLINE uint32_t ITM_SendChar (uint32_t ch) -{ - if (((ITM->TCR & ITM_TCR_ITMENA_Msk) != 0UL) && /* ITM enabled */ - ((ITM->TER & 1UL ) != 0UL) ) /* ITM Port #0 enabled */ - { - while (ITM->PORT[0U].u32 == 0UL) - { - __NOP(); - } - ITM->PORT[0U].u8 = (uint8_t)ch; - } - return (ch); -} - - -/** - \brief ITM Receive Character - \details Inputs a character via the external variable \ref ITM_RxBuffer. - \return Received character. - \return -1 No character pending. - */ -__STATIC_INLINE int32_t ITM_ReceiveChar (void) -{ - int32_t ch = -1; /* no character available */ - - if (ITM_RxBuffer != ITM_RXBUFFER_EMPTY) - { - ch = ITM_RxBuffer; - ITM_RxBuffer = ITM_RXBUFFER_EMPTY; /* ready for next character */ - } - - return (ch); -} - - -/** - \brief ITM Check Character - \details Checks whether a character is pending for reading in the variable \ref ITM_RxBuffer. - \return 0 No character available. - \return 1 Character available. - */ -__STATIC_INLINE int32_t ITM_CheckChar (void) -{ - - if (ITM_RxBuffer == ITM_RXBUFFER_EMPTY) - { - return (0); /* no character available */ - } - else - { - return (1); /* character available */ - } -} - -/*@} end of CMSIS_core_DebugFunctions */ - - - - -#ifdef __cplusplus -} -#endif - -#endif /* __CORE_CM33_H_DEPENDANT */ - -#endif /* __CMSIS_GENERIC */ diff --git a/bsp/essemi/es32f0271/libraries/CMSIS/Include/core_cm4.h b/bsp/essemi/es32f0271/libraries/CMSIS/Include/core_cm4.h deleted file mode 100644 index a11a3817a2..0000000000 --- a/bsp/essemi/es32f0271/libraries/CMSIS/Include/core_cm4.h +++ /dev/null @@ -1,2118 +0,0 @@ -/**************************************************************************//** - * @file core_cm4.h - * @brief CMSIS Cortex-M4 Core Peripheral Access Layer Header File - * @version V5.0.5 - * @date 08. January 2018 - ******************************************************************************/ -/* - * Copyright (c) 2009-2017 ARM Limited. All rights reserved. - * - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed under the Apache License, Version 2.0 (the License); you may - * not use this file except in compliance with the License. - * You may obtain a copy of the License at - * - * www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an AS IS BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - */ - -#if defined ( __ICCARM__ ) - #pragma system_include /* treat file as system include file for MISRA check */ -#elif defined (__clang__) - #pragma clang system_header /* treat file as system include file */ -#endif - -#ifndef __CORE_CM4_H_GENERIC -#define __CORE_CM4_H_GENERIC - -#include - -#ifdef __cplusplus - extern "C" { -#endif - -/** - \page CMSIS_MISRA_Exceptions MISRA-C:2004 Compliance Exceptions - CMSIS violates the following MISRA-C:2004 rules: - - \li Required Rule 8.5, object/function definition in header file.
- Function definitions in header files are used to allow 'inlining'. - - \li Required Rule 18.4, declaration of union type or object of union type: '{...}'.
- Unions are used for effective representation of core registers. - - \li Advisory Rule 19.7, Function-like macro defined.
- Function-like macros are used to allow more efficient code. - */ - - -/******************************************************************************* - * CMSIS definitions - ******************************************************************************/ -/** - \ingroup Cortex_M4 - @{ - */ - -#include "cmsis_version.h" - -/* CMSIS CM4 definitions */ -#define __CM4_CMSIS_VERSION_MAIN (__CM_CMSIS_VERSION_MAIN) /*!< \deprecated [31:16] CMSIS HAL main version */ -#define __CM4_CMSIS_VERSION_SUB (__CM_CMSIS_VERSION_SUB) /*!< \deprecated [15:0] CMSIS HAL sub version */ -#define __CM4_CMSIS_VERSION ((__CM4_CMSIS_VERSION_MAIN << 16U) | \ - __CM4_CMSIS_VERSION_SUB ) /*!< \deprecated CMSIS HAL version number */ - -#define __CORTEX_M (4U) /*!< Cortex-M Core */ - -/** __FPU_USED indicates whether an FPU is used or not. - For this, __FPU_PRESENT has to be checked prior to making use of FPU specific registers and functions. -*/ -#if defined ( __CC_ARM ) - #if defined __TARGET_FPU_VFP - #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) - #define __FPU_USED 1U - #else - #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" - #define __FPU_USED 0U - #endif - #else - #define __FPU_USED 0U - #endif - -#elif defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) - #if defined __ARM_PCS_VFP - #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) - #define __FPU_USED 1U - #else - #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" - #define __FPU_USED 0U - #endif - #else - #define __FPU_USED 0U - #endif - -#elif defined ( __GNUC__ ) - #if defined (__VFP_FP__) && !defined(__SOFTFP__) - #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) - #define __FPU_USED 1U - #else - #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" - #define __FPU_USED 0U - #endif - #else - #define __FPU_USED 0U - #endif - -#elif defined ( __ICCARM__ ) - #if defined __ARMVFP__ - #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) - #define __FPU_USED 1U - #else - #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" - #define __FPU_USED 0U - #endif - #else - #define __FPU_USED 0U - #endif - -#elif defined ( __TI_ARM__ ) - #if defined __TI_VFP_SUPPORT__ - #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) - #define __FPU_USED 1U - #else - #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" - #define __FPU_USED 0U - #endif - #else - #define __FPU_USED 0U - #endif - -#elif defined ( __TASKING__ ) - #if defined __FPU_VFP__ - #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) - #define __FPU_USED 1U - #else - #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" - #define __FPU_USED 0U - #endif - #else - #define __FPU_USED 0U - #endif - -#elif defined ( __CSMC__ ) - #if ( __CSMC__ & 0x400U) - #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) - #define __FPU_USED 1U - #else - #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" - #define __FPU_USED 0U - #endif - #else - #define __FPU_USED 0U - #endif - -#endif - -#include "cmsis_compiler.h" /* CMSIS compiler specific defines */ - - -#ifdef __cplusplus -} -#endif - -#endif /* __CORE_CM4_H_GENERIC */ - -#ifndef __CMSIS_GENERIC - -#ifndef __CORE_CM4_H_DEPENDANT -#define __CORE_CM4_H_DEPENDANT - -#ifdef __cplusplus - extern "C" { -#endif - -/* check device defines and use defaults */ -#if defined __CHECK_DEVICE_DEFINES - #ifndef __CM4_REV - #define __CM4_REV 0x0000U - #warning "__CM4_REV not defined in device header file; using default!" - #endif - - #ifndef __FPU_PRESENT - #define __FPU_PRESENT 0U - #warning "__FPU_PRESENT not defined in device header file; using default!" - #endif - - #ifndef __MPU_PRESENT - #define __MPU_PRESENT 0U - #warning "__MPU_PRESENT not defined in device header file; using default!" - #endif - - #ifndef __NVIC_PRIO_BITS - #define __NVIC_PRIO_BITS 3U - #warning "__NVIC_PRIO_BITS not defined in device header file; using default!" - #endif - - #ifndef __Vendor_SysTickConfig - #define __Vendor_SysTickConfig 0U - #warning "__Vendor_SysTickConfig not defined in device header file; using default!" - #endif -#endif - -/* IO definitions (access restrictions to peripheral registers) */ -/** - \defgroup CMSIS_glob_defs CMSIS Global Defines - - IO Type Qualifiers are used - \li to specify the access to peripheral variables. - \li for automatic generation of peripheral register debug information. -*/ -#ifdef __cplusplus - #define __I volatile /*!< Defines 'read only' permissions */ -#else - #define __I volatile const /*!< Defines 'read only' permissions */ -#endif -#define __O volatile /*!< Defines 'write only' permissions */ -#define __IO volatile /*!< Defines 'read / write' permissions */ - -/* following defines should be used for structure members */ -#define __IM volatile const /*! Defines 'read only' structure member permissions */ -#define __OM volatile /*! Defines 'write only' structure member permissions */ -#define __IOM volatile /*! Defines 'read / write' structure member permissions */ - -/*@} end of group Cortex_M4 */ - - - -/******************************************************************************* - * Register Abstraction - Core Register contain: - - Core Register - - Core NVIC Register - - Core SCB Register - - Core SysTick Register - - Core Debug Register - - Core MPU Register - - Core FPU Register - ******************************************************************************/ -/** - \defgroup CMSIS_core_register Defines and Type Definitions - \brief Type definitions and defines for Cortex-M processor based devices. -*/ - -/** - \ingroup CMSIS_core_register - \defgroup CMSIS_CORE Status and Control Registers - \brief Core Register type definitions. - @{ - */ - -/** - \brief Union type to access the Application Program Status Register (APSR). - */ -typedef union -{ - struct - { - uint32_t _reserved0:16; /*!< bit: 0..15 Reserved */ - uint32_t GE:4; /*!< bit: 16..19 Greater than or Equal flags */ - uint32_t _reserved1:7; /*!< bit: 20..26 Reserved */ - uint32_t Q:1; /*!< bit: 27 Saturation condition flag */ - uint32_t V:1; /*!< bit: 28 Overflow condition code flag */ - uint32_t C:1; /*!< bit: 29 Carry condition code flag */ - uint32_t Z:1; /*!< bit: 30 Zero condition code flag */ - uint32_t N:1; /*!< bit: 31 Negative condition code flag */ - } b; /*!< Structure used for bit access */ - uint32_t w; /*!< Type used for word access */ -} APSR_Type; - -/* APSR Register Definitions */ -#define APSR_N_Pos 31U /*!< APSR: N Position */ -#define APSR_N_Msk (1UL << APSR_N_Pos) /*!< APSR: N Mask */ - -#define APSR_Z_Pos 30U /*!< APSR: Z Position */ -#define APSR_Z_Msk (1UL << APSR_Z_Pos) /*!< APSR: Z Mask */ - -#define APSR_C_Pos 29U /*!< APSR: C Position */ -#define APSR_C_Msk (1UL << APSR_C_Pos) /*!< APSR: C Mask */ - -#define APSR_V_Pos 28U /*!< APSR: V Position */ -#define APSR_V_Msk (1UL << APSR_V_Pos) /*!< APSR: V Mask */ - -#define APSR_Q_Pos 27U /*!< APSR: Q Position */ -#define APSR_Q_Msk (1UL << APSR_Q_Pos) /*!< APSR: Q Mask */ - -#define APSR_GE_Pos 16U /*!< APSR: GE Position */ -#define APSR_GE_Msk (0xFUL << APSR_GE_Pos) /*!< APSR: GE Mask */ - - -/** - \brief Union type to access the Interrupt Program Status Register (IPSR). - */ -typedef union -{ - struct - { - uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */ - uint32_t _reserved0:23; /*!< bit: 9..31 Reserved */ - } b; /*!< Structure used for bit access */ - uint32_t w; /*!< Type used for word access */ -} IPSR_Type; - -/* IPSR Register Definitions */ -#define IPSR_ISR_Pos 0U /*!< IPSR: ISR Position */ -#define IPSR_ISR_Msk (0x1FFUL /*<< IPSR_ISR_Pos*/) /*!< IPSR: ISR Mask */ - - -/** - \brief Union type to access the Special-Purpose Program Status Registers (xPSR). - */ -typedef union -{ - struct - { - uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */ - uint32_t _reserved0:1; /*!< bit: 9 Reserved */ - uint32_t ICI_IT_1:6; /*!< bit: 10..15 ICI/IT part 1 */ - uint32_t GE:4; /*!< bit: 16..19 Greater than or Equal flags */ - uint32_t _reserved1:4; /*!< bit: 20..23 Reserved */ - uint32_t T:1; /*!< bit: 24 Thumb bit */ - uint32_t ICI_IT_2:2; /*!< bit: 25..26 ICI/IT part 2 */ - uint32_t Q:1; /*!< bit: 27 Saturation condition flag */ - uint32_t V:1; /*!< bit: 28 Overflow condition code flag */ - uint32_t C:1; /*!< bit: 29 Carry condition code flag */ - uint32_t Z:1; /*!< bit: 30 Zero condition code flag */ - uint32_t N:1; /*!< bit: 31 Negative condition code flag */ - } b; /*!< Structure used for bit access */ - uint32_t w; /*!< Type used for word access */ -} xPSR_Type; - -/* xPSR Register Definitions */ -#define xPSR_N_Pos 31U /*!< xPSR: N Position */ -#define xPSR_N_Msk (1UL << xPSR_N_Pos) /*!< xPSR: N Mask */ - -#define xPSR_Z_Pos 30U /*!< xPSR: Z Position */ -#define xPSR_Z_Msk (1UL << xPSR_Z_Pos) /*!< xPSR: Z Mask */ - -#define xPSR_C_Pos 29U /*!< xPSR: C Position */ -#define xPSR_C_Msk (1UL << xPSR_C_Pos) /*!< xPSR: C Mask */ - -#define xPSR_V_Pos 28U /*!< xPSR: V Position */ -#define xPSR_V_Msk (1UL << xPSR_V_Pos) /*!< xPSR: V Mask */ - -#define xPSR_Q_Pos 27U /*!< xPSR: Q Position */ -#define xPSR_Q_Msk (1UL << xPSR_Q_Pos) /*!< xPSR: Q Mask */ - -#define xPSR_ICI_IT_2_Pos 25U /*!< xPSR: ICI/IT part 2 Position */ -#define xPSR_ICI_IT_2_Msk (3UL << xPSR_ICI_IT_2_Pos) /*!< xPSR: ICI/IT part 2 Mask */ - -#define xPSR_T_Pos 24U /*!< xPSR: T Position */ -#define xPSR_T_Msk (1UL << xPSR_T_Pos) /*!< xPSR: T Mask */ - -#define xPSR_GE_Pos 16U /*!< xPSR: GE Position */ -#define xPSR_GE_Msk (0xFUL << xPSR_GE_Pos) /*!< xPSR: GE Mask */ - -#define xPSR_ICI_IT_1_Pos 10U /*!< xPSR: ICI/IT part 1 Position */ -#define xPSR_ICI_IT_1_Msk (0x3FUL << xPSR_ICI_IT_1_Pos) /*!< xPSR: ICI/IT part 1 Mask */ - -#define xPSR_ISR_Pos 0U /*!< xPSR: ISR Position */ -#define xPSR_ISR_Msk (0x1FFUL /*<< xPSR_ISR_Pos*/) /*!< xPSR: ISR Mask */ - - -/** - \brief Union type to access the Control Registers (CONTROL). - */ -typedef union -{ - struct - { - uint32_t nPRIV:1; /*!< bit: 0 Execution privilege in Thread mode */ - uint32_t SPSEL:1; /*!< bit: 1 Stack to be used */ - uint32_t FPCA:1; /*!< bit: 2 FP extension active flag */ - uint32_t _reserved0:29; /*!< bit: 3..31 Reserved */ - } b; /*!< Structure used for bit access */ - uint32_t w; /*!< Type used for word access */ -} CONTROL_Type; - -/* CONTROL Register Definitions */ -#define CONTROL_FPCA_Pos 2U /*!< CONTROL: FPCA Position */ -#define CONTROL_FPCA_Msk (1UL << CONTROL_FPCA_Pos) /*!< CONTROL: FPCA Mask */ - -#define CONTROL_SPSEL_Pos 1U /*!< CONTROL: SPSEL Position */ -#define CONTROL_SPSEL_Msk (1UL << CONTROL_SPSEL_Pos) /*!< CONTROL: SPSEL Mask */ - -#define CONTROL_nPRIV_Pos 0U /*!< CONTROL: nPRIV Position */ -#define CONTROL_nPRIV_Msk (1UL /*<< CONTROL_nPRIV_Pos*/) /*!< CONTROL: nPRIV Mask */ - -/*@} end of group CMSIS_CORE */ - - -/** - \ingroup CMSIS_core_register - \defgroup CMSIS_NVIC Nested Vectored Interrupt Controller (NVIC) - \brief Type definitions for the NVIC Registers - @{ - */ - -/** - \brief Structure type to access the Nested Vectored Interrupt Controller (NVIC). - */ -typedef struct -{ - __IOM uint32_t ISER[8U]; /*!< Offset: 0x000 (R/W) Interrupt Set Enable Register */ - uint32_t RESERVED0[24U]; - __IOM uint32_t ICER[8U]; /*!< Offset: 0x080 (R/W) Interrupt Clear Enable Register */ - uint32_t RSERVED1[24U]; - __IOM uint32_t ISPR[8U]; /*!< Offset: 0x100 (R/W) Interrupt Set Pending Register */ - uint32_t RESERVED2[24U]; - __IOM uint32_t ICPR[8U]; /*!< Offset: 0x180 (R/W) Interrupt Clear Pending Register */ - uint32_t RESERVED3[24U]; - __IOM uint32_t IABR[8U]; /*!< Offset: 0x200 (R/W) Interrupt Active bit Register */ - uint32_t RESERVED4[56U]; - __IOM uint8_t IP[240U]; /*!< Offset: 0x300 (R/W) Interrupt Priority Register (8Bit wide) */ - uint32_t RESERVED5[644U]; - __OM uint32_t STIR; /*!< Offset: 0xE00 ( /W) Software Trigger Interrupt Register */ -} NVIC_Type; - -/* Software Triggered Interrupt Register Definitions */ -#define NVIC_STIR_INTID_Pos 0U /*!< STIR: INTLINESNUM Position */ -#define NVIC_STIR_INTID_Msk (0x1FFUL /*<< NVIC_STIR_INTID_Pos*/) /*!< STIR: INTLINESNUM Mask */ - -/*@} end of group CMSIS_NVIC */ - - -/** - \ingroup CMSIS_core_register - \defgroup CMSIS_SCB System Control Block (SCB) - \brief Type definitions for the System Control Block Registers - @{ - */ - -/** - \brief Structure type to access the System Control Block (SCB). - */ -typedef struct -{ - __IM uint32_t CPUID; /*!< Offset: 0x000 (R/ ) CPUID Base Register */ - __IOM uint32_t ICSR; /*!< Offset: 0x004 (R/W) Interrupt Control and State Register */ - __IOM uint32_t VTOR; /*!< Offset: 0x008 (R/W) Vector Table Offset Register */ - __IOM uint32_t AIRCR; /*!< Offset: 0x00C (R/W) Application Interrupt and Reset Control Register */ - __IOM uint32_t SCR; /*!< Offset: 0x010 (R/W) System Control Register */ - __IOM uint32_t CCR; /*!< Offset: 0x014 (R/W) Configuration Control Register */ - __IOM uint8_t SHP[12U]; /*!< Offset: 0x018 (R/W) System Handlers Priority Registers (4-7, 8-11, 12-15) */ - __IOM uint32_t SHCSR; /*!< Offset: 0x024 (R/W) System Handler Control and State Register */ - __IOM uint32_t CFSR; /*!< Offset: 0x028 (R/W) Configurable Fault Status Register */ - __IOM uint32_t HFSR; /*!< Offset: 0x02C (R/W) HardFault Status Register */ - __IOM uint32_t DFSR; /*!< Offset: 0x030 (R/W) Debug Fault Status Register */ - __IOM uint32_t MMFAR; /*!< Offset: 0x034 (R/W) MemManage Fault Address Register */ - __IOM uint32_t BFAR; /*!< Offset: 0x038 (R/W) BusFault Address Register */ - __IOM uint32_t AFSR; /*!< Offset: 0x03C (R/W) Auxiliary Fault Status Register */ - __IM uint32_t PFR[2U]; /*!< Offset: 0x040 (R/ ) Processor Feature Register */ - __IM uint32_t DFR; /*!< Offset: 0x048 (R/ ) Debug Feature Register */ - __IM uint32_t ADR; /*!< Offset: 0x04C (R/ ) Auxiliary Feature Register */ - __IM uint32_t MMFR[4U]; /*!< Offset: 0x050 (R/ ) Memory Model Feature Register */ - __IM uint32_t ISAR[5U]; /*!< Offset: 0x060 (R/ ) Instruction Set Attributes Register */ - uint32_t RESERVED0[5U]; - __IOM uint32_t CPACR; /*!< Offset: 0x088 (R/W) Coprocessor Access Control Register */ -} SCB_Type; - -/* SCB CPUID Register Definitions */ -#define SCB_CPUID_IMPLEMENTER_Pos 24U /*!< SCB CPUID: IMPLEMENTER Position */ -#define SCB_CPUID_IMPLEMENTER_Msk (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos) /*!< SCB CPUID: IMPLEMENTER Mask */ - -#define SCB_CPUID_VARIANT_Pos 20U /*!< SCB CPUID: VARIANT Position */ -#define SCB_CPUID_VARIANT_Msk (0xFUL << SCB_CPUID_VARIANT_Pos) /*!< SCB CPUID: VARIANT Mask */ - -#define SCB_CPUID_ARCHITECTURE_Pos 16U /*!< SCB CPUID: ARCHITECTURE Position */ -#define SCB_CPUID_ARCHITECTURE_Msk (0xFUL << SCB_CPUID_ARCHITECTURE_Pos) /*!< SCB CPUID: ARCHITECTURE Mask */ - -#define SCB_CPUID_PARTNO_Pos 4U /*!< SCB CPUID: PARTNO Position */ -#define SCB_CPUID_PARTNO_Msk (0xFFFUL << SCB_CPUID_PARTNO_Pos) /*!< SCB CPUID: PARTNO Mask */ - -#define SCB_CPUID_REVISION_Pos 0U /*!< SCB CPUID: REVISION Position */ -#define SCB_CPUID_REVISION_Msk (0xFUL /*<< SCB_CPUID_REVISION_Pos*/) /*!< SCB CPUID: REVISION Mask */ - -/* SCB Interrupt Control State Register Definitions */ -#define SCB_ICSR_NMIPENDSET_Pos 31U /*!< SCB ICSR: NMIPENDSET Position */ -#define SCB_ICSR_NMIPENDSET_Msk (1UL << SCB_ICSR_NMIPENDSET_Pos) /*!< SCB ICSR: NMIPENDSET Mask */ - -#define SCB_ICSR_PENDSVSET_Pos 28U /*!< SCB ICSR: PENDSVSET Position */ -#define SCB_ICSR_PENDSVSET_Msk (1UL << SCB_ICSR_PENDSVSET_Pos) /*!< SCB ICSR: PENDSVSET Mask */ - -#define SCB_ICSR_PENDSVCLR_Pos 27U /*!< SCB ICSR: PENDSVCLR Position */ -#define SCB_ICSR_PENDSVCLR_Msk (1UL << SCB_ICSR_PENDSVCLR_Pos) /*!< SCB ICSR: PENDSVCLR Mask */ - -#define SCB_ICSR_PENDSTSET_Pos 26U /*!< SCB ICSR: PENDSTSET Position */ -#define SCB_ICSR_PENDSTSET_Msk (1UL << SCB_ICSR_PENDSTSET_Pos) /*!< SCB ICSR: PENDSTSET Mask */ - -#define SCB_ICSR_PENDSTCLR_Pos 25U /*!< SCB ICSR: PENDSTCLR Position */ -#define SCB_ICSR_PENDSTCLR_Msk (1UL << SCB_ICSR_PENDSTCLR_Pos) /*!< SCB ICSR: PENDSTCLR Mask */ - -#define SCB_ICSR_ISRPREEMPT_Pos 23U /*!< SCB ICSR: ISRPREEMPT Position */ -#define SCB_ICSR_ISRPREEMPT_Msk (1UL << SCB_ICSR_ISRPREEMPT_Pos) /*!< SCB ICSR: ISRPREEMPT Mask */ - -#define SCB_ICSR_ISRPENDING_Pos 22U /*!< SCB ICSR: ISRPENDING Position */ -#define SCB_ICSR_ISRPENDING_Msk (1UL << SCB_ICSR_ISRPENDING_Pos) /*!< SCB ICSR: ISRPENDING Mask */ - -#define SCB_ICSR_VECTPENDING_Pos 12U /*!< SCB ICSR: VECTPENDING Position */ -#define SCB_ICSR_VECTPENDING_Msk (0x1FFUL << SCB_ICSR_VECTPENDING_Pos) /*!< SCB ICSR: VECTPENDING Mask */ - -#define SCB_ICSR_RETTOBASE_Pos 11U /*!< SCB ICSR: RETTOBASE Position */ -#define SCB_ICSR_RETTOBASE_Msk (1UL << SCB_ICSR_RETTOBASE_Pos) /*!< SCB ICSR: RETTOBASE Mask */ - -#define SCB_ICSR_VECTACTIVE_Pos 0U /*!< SCB ICSR: VECTACTIVE Position */ -#define SCB_ICSR_VECTACTIVE_Msk (0x1FFUL /*<< SCB_ICSR_VECTACTIVE_Pos*/) /*!< SCB ICSR: VECTACTIVE Mask */ - -/* SCB Vector Table Offset Register Definitions */ -#define SCB_VTOR_TBLOFF_Pos 7U /*!< SCB VTOR: TBLOFF Position */ -#define SCB_VTOR_TBLOFF_Msk (0x1FFFFFFUL << SCB_VTOR_TBLOFF_Pos) /*!< SCB VTOR: TBLOFF Mask */ - -/* SCB Application Interrupt and Reset Control Register Definitions */ -#define SCB_AIRCR_VECTKEY_Pos 16U /*!< SCB AIRCR: VECTKEY Position */ -#define SCB_AIRCR_VECTKEY_Msk (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos) /*!< SCB AIRCR: VECTKEY Mask */ - -#define SCB_AIRCR_VECTKEYSTAT_Pos 16U /*!< SCB AIRCR: VECTKEYSTAT Position */ -#define SCB_AIRCR_VECTKEYSTAT_Msk (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos) /*!< SCB AIRCR: VECTKEYSTAT Mask */ - -#define SCB_AIRCR_ENDIANESS_Pos 15U /*!< SCB AIRCR: ENDIANESS Position */ -#define SCB_AIRCR_ENDIANESS_Msk (1UL << SCB_AIRCR_ENDIANESS_Pos) /*!< SCB AIRCR: ENDIANESS Mask */ - -#define SCB_AIRCR_PRIGROUP_Pos 8U /*!< SCB AIRCR: PRIGROUP Position */ -#define SCB_AIRCR_PRIGROUP_Msk (7UL << SCB_AIRCR_PRIGROUP_Pos) /*!< SCB AIRCR: PRIGROUP Mask */ - -#define SCB_AIRCR_SYSRESETREQ_Pos 2U /*!< SCB AIRCR: SYSRESETREQ Position */ -#define SCB_AIRCR_SYSRESETREQ_Msk (1UL << SCB_AIRCR_SYSRESETREQ_Pos) /*!< SCB AIRCR: SYSRESETREQ Mask */ - -#define SCB_AIRCR_VECTCLRACTIVE_Pos 1U /*!< SCB AIRCR: VECTCLRACTIVE Position */ -#define SCB_AIRCR_VECTCLRACTIVE_Msk (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos) /*!< SCB AIRCR: VECTCLRACTIVE Mask */ - -#define SCB_AIRCR_VECTRESET_Pos 0U /*!< SCB AIRCR: VECTRESET Position */ -#define SCB_AIRCR_VECTRESET_Msk (1UL /*<< SCB_AIRCR_VECTRESET_Pos*/) /*!< SCB AIRCR: VECTRESET Mask */ - -/* SCB System Control Register Definitions */ -#define SCB_SCR_SEVONPEND_Pos 4U /*!< SCB SCR: SEVONPEND Position */ -#define SCB_SCR_SEVONPEND_Msk (1UL << SCB_SCR_SEVONPEND_Pos) /*!< SCB SCR: SEVONPEND Mask */ - -#define SCB_SCR_SLEEPDEEP_Pos 2U /*!< SCB SCR: SLEEPDEEP Position */ -#define SCB_SCR_SLEEPDEEP_Msk (1UL << SCB_SCR_SLEEPDEEP_Pos) /*!< SCB SCR: SLEEPDEEP Mask */ - -#define SCB_SCR_SLEEPONEXIT_Pos 1U /*!< SCB SCR: SLEEPONEXIT Position */ -#define SCB_SCR_SLEEPONEXIT_Msk (1UL << SCB_SCR_SLEEPONEXIT_Pos) /*!< SCB SCR: SLEEPONEXIT Mask */ - -/* SCB Configuration Control Register Definitions */ -#define SCB_CCR_STKALIGN_Pos 9U /*!< SCB CCR: STKALIGN Position */ -#define SCB_CCR_STKALIGN_Msk (1UL << SCB_CCR_STKALIGN_Pos) /*!< SCB CCR: STKALIGN Mask */ - -#define SCB_CCR_BFHFNMIGN_Pos 8U /*!< SCB CCR: BFHFNMIGN Position */ -#define SCB_CCR_BFHFNMIGN_Msk (1UL << SCB_CCR_BFHFNMIGN_Pos) /*!< SCB CCR: BFHFNMIGN Mask */ - -#define SCB_CCR_DIV_0_TRP_Pos 4U /*!< SCB CCR: DIV_0_TRP Position */ -#define SCB_CCR_DIV_0_TRP_Msk (1UL << SCB_CCR_DIV_0_TRP_Pos) /*!< SCB CCR: DIV_0_TRP Mask */ - -#define SCB_CCR_UNALIGN_TRP_Pos 3U /*!< SCB CCR: UNALIGN_TRP Position */ -#define SCB_CCR_UNALIGN_TRP_Msk (1UL << SCB_CCR_UNALIGN_TRP_Pos) /*!< SCB CCR: UNALIGN_TRP Mask */ - -#define SCB_CCR_USERSETMPEND_Pos 1U /*!< SCB CCR: USERSETMPEND Position */ -#define SCB_CCR_USERSETMPEND_Msk (1UL << SCB_CCR_USERSETMPEND_Pos) /*!< SCB CCR: USERSETMPEND Mask */ - -#define SCB_CCR_NONBASETHRDENA_Pos 0U /*!< SCB CCR: NONBASETHRDENA Position */ -#define SCB_CCR_NONBASETHRDENA_Msk (1UL /*<< SCB_CCR_NONBASETHRDENA_Pos*/) /*!< SCB CCR: NONBASETHRDENA Mask */ - -/* SCB System Handler Control and State Register Definitions */ -#define SCB_SHCSR_USGFAULTENA_Pos 18U /*!< SCB SHCSR: USGFAULTENA Position */ -#define SCB_SHCSR_USGFAULTENA_Msk (1UL << SCB_SHCSR_USGFAULTENA_Pos) /*!< SCB SHCSR: USGFAULTENA Mask */ - -#define SCB_SHCSR_BUSFAULTENA_Pos 17U /*!< SCB SHCSR: BUSFAULTENA Position */ -#define SCB_SHCSR_BUSFAULTENA_Msk (1UL << SCB_SHCSR_BUSFAULTENA_Pos) /*!< SCB SHCSR: BUSFAULTENA Mask */ - -#define SCB_SHCSR_MEMFAULTENA_Pos 16U /*!< SCB SHCSR: MEMFAULTENA Position */ -#define SCB_SHCSR_MEMFAULTENA_Msk (1UL << SCB_SHCSR_MEMFAULTENA_Pos) /*!< SCB SHCSR: MEMFAULTENA Mask */ - -#define SCB_SHCSR_SVCALLPENDED_Pos 15U /*!< SCB SHCSR: SVCALLPENDED Position */ -#define SCB_SHCSR_SVCALLPENDED_Msk (1UL << SCB_SHCSR_SVCALLPENDED_Pos) /*!< SCB SHCSR: SVCALLPENDED Mask */ - -#define SCB_SHCSR_BUSFAULTPENDED_Pos 14U /*!< SCB SHCSR: BUSFAULTPENDED Position */ -#define SCB_SHCSR_BUSFAULTPENDED_Msk (1UL << SCB_SHCSR_BUSFAULTPENDED_Pos) /*!< SCB SHCSR: BUSFAULTPENDED Mask */ - -#define SCB_SHCSR_MEMFAULTPENDED_Pos 13U /*!< SCB SHCSR: MEMFAULTPENDED Position */ -#define SCB_SHCSR_MEMFAULTPENDED_Msk (1UL << SCB_SHCSR_MEMFAULTPENDED_Pos) /*!< SCB SHCSR: MEMFAULTPENDED Mask */ - -#define SCB_SHCSR_USGFAULTPENDED_Pos 12U /*!< SCB SHCSR: USGFAULTPENDED Position */ -#define SCB_SHCSR_USGFAULTPENDED_Msk (1UL << SCB_SHCSR_USGFAULTPENDED_Pos) /*!< SCB SHCSR: USGFAULTPENDED Mask */ - -#define SCB_SHCSR_SYSTICKACT_Pos 11U /*!< SCB SHCSR: SYSTICKACT Position */ -#define SCB_SHCSR_SYSTICKACT_Msk (1UL << SCB_SHCSR_SYSTICKACT_Pos) /*!< SCB SHCSR: SYSTICKACT Mask */ - -#define SCB_SHCSR_PENDSVACT_Pos 10U /*!< SCB SHCSR: PENDSVACT Position */ -#define SCB_SHCSR_PENDSVACT_Msk (1UL << SCB_SHCSR_PENDSVACT_Pos) /*!< SCB SHCSR: PENDSVACT Mask */ - -#define SCB_SHCSR_MONITORACT_Pos 8U /*!< SCB SHCSR: MONITORACT Position */ -#define SCB_SHCSR_MONITORACT_Msk (1UL << SCB_SHCSR_MONITORACT_Pos) /*!< SCB SHCSR: MONITORACT Mask */ - -#define SCB_SHCSR_SVCALLACT_Pos 7U /*!< SCB SHCSR: SVCALLACT Position */ -#define SCB_SHCSR_SVCALLACT_Msk (1UL << SCB_SHCSR_SVCALLACT_Pos) /*!< SCB SHCSR: SVCALLACT Mask */ - -#define SCB_SHCSR_USGFAULTACT_Pos 3U /*!< SCB SHCSR: USGFAULTACT Position */ -#define SCB_SHCSR_USGFAULTACT_Msk (1UL << SCB_SHCSR_USGFAULTACT_Pos) /*!< SCB SHCSR: USGFAULTACT Mask */ - -#define SCB_SHCSR_BUSFAULTACT_Pos 1U /*!< SCB SHCSR: BUSFAULTACT Position */ -#define SCB_SHCSR_BUSFAULTACT_Msk (1UL << SCB_SHCSR_BUSFAULTACT_Pos) /*!< SCB SHCSR: BUSFAULTACT Mask */ - -#define SCB_SHCSR_MEMFAULTACT_Pos 0U /*!< SCB SHCSR: MEMFAULTACT Position */ -#define SCB_SHCSR_MEMFAULTACT_Msk (1UL /*<< SCB_SHCSR_MEMFAULTACT_Pos*/) /*!< SCB SHCSR: MEMFAULTACT Mask */ - -/* SCB Configurable Fault Status Register Definitions */ -#define SCB_CFSR_USGFAULTSR_Pos 16U /*!< SCB CFSR: Usage Fault Status Register Position */ -#define SCB_CFSR_USGFAULTSR_Msk (0xFFFFUL << SCB_CFSR_USGFAULTSR_Pos) /*!< SCB CFSR: Usage Fault Status Register Mask */ - -#define SCB_CFSR_BUSFAULTSR_Pos 8U /*!< SCB CFSR: Bus Fault Status Register Position */ -#define SCB_CFSR_BUSFAULTSR_Msk (0xFFUL << SCB_CFSR_BUSFAULTSR_Pos) /*!< SCB CFSR: Bus Fault Status Register Mask */ - -#define SCB_CFSR_MEMFAULTSR_Pos 0U /*!< SCB CFSR: Memory Manage Fault Status Register Position */ -#define SCB_CFSR_MEMFAULTSR_Msk (0xFFUL /*<< SCB_CFSR_MEMFAULTSR_Pos*/) /*!< SCB CFSR: Memory Manage Fault Status Register Mask */ - -/* MemManage Fault Status Register (part of SCB Configurable Fault Status Register) */ -#define SCB_CFSR_MMARVALID_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 7U) /*!< SCB CFSR (MMFSR): MMARVALID Position */ -#define SCB_CFSR_MMARVALID_Msk (1UL << SCB_CFSR_MMARVALID_Pos) /*!< SCB CFSR (MMFSR): MMARVALID Mask */ - -#define SCB_CFSR_MLSPERR_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 5U) /*!< SCB CFSR (MMFSR): MLSPERR Position */ -#define SCB_CFSR_MLSPERR_Msk (1UL << SCB_CFSR_MLSPERR_Pos) /*!< SCB CFSR (MMFSR): MLSPERR Mask */ - -#define SCB_CFSR_MSTKERR_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 4U) /*!< SCB CFSR (MMFSR): MSTKERR Position */ -#define SCB_CFSR_MSTKERR_Msk (1UL << SCB_CFSR_MSTKERR_Pos) /*!< SCB CFSR (MMFSR): MSTKERR Mask */ - -#define SCB_CFSR_MUNSTKERR_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 3U) /*!< SCB CFSR (MMFSR): MUNSTKERR Position */ -#define SCB_CFSR_MUNSTKERR_Msk (1UL << SCB_CFSR_MUNSTKERR_Pos) /*!< SCB CFSR (MMFSR): MUNSTKERR Mask */ - -#define SCB_CFSR_DACCVIOL_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 1U) /*!< SCB CFSR (MMFSR): DACCVIOL Position */ -#define SCB_CFSR_DACCVIOL_Msk (1UL << SCB_CFSR_DACCVIOL_Pos) /*!< SCB CFSR (MMFSR): DACCVIOL Mask */ - -#define SCB_CFSR_IACCVIOL_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 0U) /*!< SCB CFSR (MMFSR): IACCVIOL Position */ -#define SCB_CFSR_IACCVIOL_Msk (1UL /*<< SCB_CFSR_IACCVIOL_Pos*/) /*!< SCB CFSR (MMFSR): IACCVIOL Mask */ - -/* BusFault Status Register (part of SCB Configurable Fault Status Register) */ -#define SCB_CFSR_BFARVALID_Pos (SCB_CFSR_BUSFAULTSR_Pos + 7U) /*!< SCB CFSR (BFSR): BFARVALID Position */ -#define SCB_CFSR_BFARVALID_Msk (1UL << SCB_CFSR_BFARVALID_Pos) /*!< SCB CFSR (BFSR): BFARVALID Mask */ - -#define SCB_CFSR_LSPERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 5U) /*!< SCB CFSR (BFSR): LSPERR Position */ -#define SCB_CFSR_LSPERR_Msk (1UL << SCB_CFSR_LSPERR_Pos) /*!< SCB CFSR (BFSR): LSPERR Mask */ - -#define SCB_CFSR_STKERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 4U) /*!< SCB CFSR (BFSR): STKERR Position */ -#define SCB_CFSR_STKERR_Msk (1UL << SCB_CFSR_STKERR_Pos) /*!< SCB CFSR (BFSR): STKERR Mask */ - -#define SCB_CFSR_UNSTKERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 3U) /*!< SCB CFSR (BFSR): UNSTKERR Position */ -#define SCB_CFSR_UNSTKERR_Msk (1UL << SCB_CFSR_UNSTKERR_Pos) /*!< SCB CFSR (BFSR): UNSTKERR Mask */ - -#define SCB_CFSR_IMPRECISERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 2U) /*!< SCB CFSR (BFSR): IMPRECISERR Position */ -#define SCB_CFSR_IMPRECISERR_Msk (1UL << SCB_CFSR_IMPRECISERR_Pos) /*!< SCB CFSR (BFSR): IMPRECISERR Mask */ - -#define SCB_CFSR_PRECISERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 1U) /*!< SCB CFSR (BFSR): PRECISERR Position */ -#define SCB_CFSR_PRECISERR_Msk (1UL << SCB_CFSR_PRECISERR_Pos) /*!< SCB CFSR (BFSR): PRECISERR Mask */ - -#define SCB_CFSR_IBUSERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 0U) /*!< SCB CFSR (BFSR): IBUSERR Position */ -#define SCB_CFSR_IBUSERR_Msk (1UL << SCB_CFSR_IBUSERR_Pos) /*!< SCB CFSR (BFSR): IBUSERR Mask */ - -/* UsageFault Status Register (part of SCB Configurable Fault Status Register) */ -#define SCB_CFSR_DIVBYZERO_Pos (SCB_CFSR_USGFAULTSR_Pos + 9U) /*!< SCB CFSR (UFSR): DIVBYZERO Position */ -#define SCB_CFSR_DIVBYZERO_Msk (1UL << SCB_CFSR_DIVBYZERO_Pos) /*!< SCB CFSR (UFSR): DIVBYZERO Mask */ - -#define SCB_CFSR_UNALIGNED_Pos (SCB_CFSR_USGFAULTSR_Pos + 8U) /*!< SCB CFSR (UFSR): UNALIGNED Position */ -#define SCB_CFSR_UNALIGNED_Msk (1UL << SCB_CFSR_UNALIGNED_Pos) /*!< SCB CFSR (UFSR): UNALIGNED Mask */ - -#define SCB_CFSR_NOCP_Pos (SCB_CFSR_USGFAULTSR_Pos + 3U) /*!< SCB CFSR (UFSR): NOCP Position */ -#define SCB_CFSR_NOCP_Msk (1UL << SCB_CFSR_NOCP_Pos) /*!< SCB CFSR (UFSR): NOCP Mask */ - -#define SCB_CFSR_INVPC_Pos (SCB_CFSR_USGFAULTSR_Pos + 2U) /*!< SCB CFSR (UFSR): INVPC Position */ -#define SCB_CFSR_INVPC_Msk (1UL << SCB_CFSR_INVPC_Pos) /*!< SCB CFSR (UFSR): INVPC Mask */ - -#define SCB_CFSR_INVSTATE_Pos (SCB_CFSR_USGFAULTSR_Pos + 1U) /*!< SCB CFSR (UFSR): INVSTATE Position */ -#define SCB_CFSR_INVSTATE_Msk (1UL << SCB_CFSR_INVSTATE_Pos) /*!< SCB CFSR (UFSR): INVSTATE Mask */ - -#define SCB_CFSR_UNDEFINSTR_Pos (SCB_CFSR_USGFAULTSR_Pos + 0U) /*!< SCB CFSR (UFSR): UNDEFINSTR Position */ -#define SCB_CFSR_UNDEFINSTR_Msk (1UL << SCB_CFSR_UNDEFINSTR_Pos) /*!< SCB CFSR (UFSR): UNDEFINSTR Mask */ - -/* SCB Hard Fault Status Register Definitions */ -#define SCB_HFSR_DEBUGEVT_Pos 31U /*!< SCB HFSR: DEBUGEVT Position */ -#define SCB_HFSR_DEBUGEVT_Msk (1UL << SCB_HFSR_DEBUGEVT_Pos) /*!< SCB HFSR: DEBUGEVT Mask */ - -#define SCB_HFSR_FORCED_Pos 30U /*!< SCB HFSR: FORCED Position */ -#define SCB_HFSR_FORCED_Msk (1UL << SCB_HFSR_FORCED_Pos) /*!< SCB HFSR: FORCED Mask */ - -#define SCB_HFSR_VECTTBL_Pos 1U /*!< SCB HFSR: VECTTBL Position */ -#define SCB_HFSR_VECTTBL_Msk (1UL << SCB_HFSR_VECTTBL_Pos) /*!< SCB HFSR: VECTTBL Mask */ - -/* SCB Debug Fault Status Register Definitions */ -#define SCB_DFSR_EXTERNAL_Pos 4U /*!< SCB DFSR: EXTERNAL Position */ -#define SCB_DFSR_EXTERNAL_Msk (1UL << SCB_DFSR_EXTERNAL_Pos) /*!< SCB DFSR: EXTERNAL Mask */ - -#define SCB_DFSR_VCATCH_Pos 3U /*!< SCB DFSR: VCATCH Position */ -#define SCB_DFSR_VCATCH_Msk (1UL << SCB_DFSR_VCATCH_Pos) /*!< SCB DFSR: VCATCH Mask */ - -#define SCB_DFSR_DWTTRAP_Pos 2U /*!< SCB DFSR: DWTTRAP Position */ -#define SCB_DFSR_DWTTRAP_Msk (1UL << SCB_DFSR_DWTTRAP_Pos) /*!< SCB DFSR: DWTTRAP Mask */ - -#define SCB_DFSR_BKPT_Pos 1U /*!< SCB DFSR: BKPT Position */ -#define SCB_DFSR_BKPT_Msk (1UL << SCB_DFSR_BKPT_Pos) /*!< SCB DFSR: BKPT Mask */ - -#define SCB_DFSR_HALTED_Pos 0U /*!< SCB DFSR: HALTED Position */ -#define SCB_DFSR_HALTED_Msk (1UL /*<< SCB_DFSR_HALTED_Pos*/) /*!< SCB DFSR: HALTED Mask */ - -/*@} end of group CMSIS_SCB */ - - -/** - \ingroup CMSIS_core_register - \defgroup CMSIS_SCnSCB System Controls not in SCB (SCnSCB) - \brief Type definitions for the System Control and ID Register not in the SCB - @{ - */ - -/** - \brief Structure type to access the System Control and ID Register not in the SCB. - */ -typedef struct -{ - uint32_t RESERVED0[1U]; - __IM uint32_t ICTR; /*!< Offset: 0x004 (R/ ) Interrupt Controller Type Register */ - __IOM uint32_t ACTLR; /*!< Offset: 0x008 (R/W) Auxiliary Control Register */ -} SCnSCB_Type; - -/* Interrupt Controller Type Register Definitions */ -#define SCnSCB_ICTR_INTLINESNUM_Pos 0U /*!< ICTR: INTLINESNUM Position */ -#define SCnSCB_ICTR_INTLINESNUM_Msk (0xFUL /*<< SCnSCB_ICTR_INTLINESNUM_Pos*/) /*!< ICTR: INTLINESNUM Mask */ - -/* Auxiliary Control Register Definitions */ -#define SCnSCB_ACTLR_DISOOFP_Pos 9U /*!< ACTLR: DISOOFP Position */ -#define SCnSCB_ACTLR_DISOOFP_Msk (1UL << SCnSCB_ACTLR_DISOOFP_Pos) /*!< ACTLR: DISOOFP Mask */ - -#define SCnSCB_ACTLR_DISFPCA_Pos 8U /*!< ACTLR: DISFPCA Position */ -#define SCnSCB_ACTLR_DISFPCA_Msk (1UL << SCnSCB_ACTLR_DISFPCA_Pos) /*!< ACTLR: DISFPCA Mask */ - -#define SCnSCB_ACTLR_DISFOLD_Pos 2U /*!< ACTLR: DISFOLD Position */ -#define SCnSCB_ACTLR_DISFOLD_Msk (1UL << SCnSCB_ACTLR_DISFOLD_Pos) /*!< ACTLR: DISFOLD Mask */ - -#define SCnSCB_ACTLR_DISDEFWBUF_Pos 1U /*!< ACTLR: DISDEFWBUF Position */ -#define SCnSCB_ACTLR_DISDEFWBUF_Msk (1UL << SCnSCB_ACTLR_DISDEFWBUF_Pos) /*!< ACTLR: DISDEFWBUF Mask */ - -#define SCnSCB_ACTLR_DISMCYCINT_Pos 0U /*!< ACTLR: DISMCYCINT Position */ -#define SCnSCB_ACTLR_DISMCYCINT_Msk (1UL /*<< SCnSCB_ACTLR_DISMCYCINT_Pos*/) /*!< ACTLR: DISMCYCINT Mask */ - -/*@} end of group CMSIS_SCnotSCB */ - - -/** - \ingroup CMSIS_core_register - \defgroup CMSIS_SysTick System Tick Timer (SysTick) - \brief Type definitions for the System Timer Registers. - @{ - */ - -/** - \brief Structure type to access the System Timer (SysTick). - */ -typedef struct -{ - __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) SysTick Control and Status Register */ - __IOM uint32_t LOAD; /*!< Offset: 0x004 (R/W) SysTick Reload Value Register */ - __IOM uint32_t VAL; /*!< Offset: 0x008 (R/W) SysTick Current Value Register */ - __IM uint32_t CALIB; /*!< Offset: 0x00C (R/ ) SysTick Calibration Register */ -} SysTick_Type; - -/* SysTick Control / Status Register Definitions */ -#define SysTick_CTRL_COUNTFLAG_Pos 16U /*!< SysTick CTRL: COUNTFLAG Position */ -#define SysTick_CTRL_COUNTFLAG_Msk (1UL << SysTick_CTRL_COUNTFLAG_Pos) /*!< SysTick CTRL: COUNTFLAG Mask */ - -#define SysTick_CTRL_CLKSOURCE_Pos 2U /*!< SysTick CTRL: CLKSOURCE Position */ -#define SysTick_CTRL_CLKSOURCE_Msk (1UL << SysTick_CTRL_CLKSOURCE_Pos) /*!< SysTick CTRL: CLKSOURCE Mask */ - -#define SysTick_CTRL_TICKINT_Pos 1U /*!< SysTick CTRL: TICKINT Position */ -#define SysTick_CTRL_TICKINT_Msk (1UL << SysTick_CTRL_TICKINT_Pos) /*!< SysTick CTRL: TICKINT Mask */ - -#define SysTick_CTRL_ENABLE_Pos 0U /*!< SysTick CTRL: ENABLE Position */ -#define SysTick_CTRL_ENABLE_Msk (1UL /*<< SysTick_CTRL_ENABLE_Pos*/) /*!< SysTick CTRL: ENABLE Mask */ - -/* SysTick Reload Register Definitions */ -#define SysTick_LOAD_RELOAD_Pos 0U /*!< SysTick LOAD: RELOAD Position */ -#define SysTick_LOAD_RELOAD_Msk (0xFFFFFFUL /*<< SysTick_LOAD_RELOAD_Pos*/) /*!< SysTick LOAD: RELOAD Mask */ - -/* SysTick Current Register Definitions */ -#define SysTick_VAL_CURRENT_Pos 0U /*!< SysTick VAL: CURRENT Position */ -#define SysTick_VAL_CURRENT_Msk (0xFFFFFFUL /*<< SysTick_VAL_CURRENT_Pos*/) /*!< SysTick VAL: CURRENT Mask */ - -/* SysTick Calibration Register Definitions */ -#define SysTick_CALIB_NOREF_Pos 31U /*!< SysTick CALIB: NOREF Position */ -#define SysTick_CALIB_NOREF_Msk (1UL << SysTick_CALIB_NOREF_Pos) /*!< SysTick CALIB: NOREF Mask */ - -#define SysTick_CALIB_SKEW_Pos 30U /*!< SysTick CALIB: SKEW Position */ -#define SysTick_CALIB_SKEW_Msk (1UL << SysTick_CALIB_SKEW_Pos) /*!< SysTick CALIB: SKEW Mask */ - -#define SysTick_CALIB_TENMS_Pos 0U /*!< SysTick CALIB: TENMS Position */ -#define SysTick_CALIB_TENMS_Msk (0xFFFFFFUL /*<< SysTick_CALIB_TENMS_Pos*/) /*!< SysTick CALIB: TENMS Mask */ - -/*@} end of group CMSIS_SysTick */ - - -/** - \ingroup CMSIS_core_register - \defgroup CMSIS_ITM Instrumentation Trace Macrocell (ITM) - \brief Type definitions for the Instrumentation Trace Macrocell (ITM) - @{ - */ - -/** - \brief Structure type to access the Instrumentation Trace Macrocell Register (ITM). - */ -typedef struct -{ - __OM union - { - __OM uint8_t u8; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 8-bit */ - __OM uint16_t u16; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 16-bit */ - __OM uint32_t u32; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 32-bit */ - } PORT [32U]; /*!< Offset: 0x000 ( /W) ITM Stimulus Port Registers */ - uint32_t RESERVED0[864U]; - __IOM uint32_t TER; /*!< Offset: 0xE00 (R/W) ITM Trace Enable Register */ - uint32_t RESERVED1[15U]; - __IOM uint32_t TPR; /*!< Offset: 0xE40 (R/W) ITM Trace Privilege Register */ - uint32_t RESERVED2[15U]; - __IOM uint32_t TCR; /*!< Offset: 0xE80 (R/W) ITM Trace Control Register */ - uint32_t RESERVED3[29U]; - __OM uint32_t IWR; /*!< Offset: 0xEF8 ( /W) ITM Integration Write Register */ - __IM uint32_t IRR; /*!< Offset: 0xEFC (R/ ) ITM Integration Read Register */ - __IOM uint32_t IMCR; /*!< Offset: 0xF00 (R/W) ITM Integration Mode Control Register */ - uint32_t RESERVED4[43U]; - __OM uint32_t LAR; /*!< Offset: 0xFB0 ( /W) ITM Lock Access Register */ - __IM uint32_t LSR; /*!< Offset: 0xFB4 (R/ ) ITM Lock Status Register */ - uint32_t RESERVED5[6U]; - __IM uint32_t PID4; /*!< Offset: 0xFD0 (R/ ) ITM Peripheral Identification Register #4 */ - __IM uint32_t PID5; /*!< Offset: 0xFD4 (R/ ) ITM Peripheral Identification Register #5 */ - __IM uint32_t PID6; /*!< Offset: 0xFD8 (R/ ) ITM Peripheral Identification Register #6 */ - __IM uint32_t PID7; /*!< Offset: 0xFDC (R/ ) ITM Peripheral Identification Register #7 */ - __IM uint32_t PID0; /*!< Offset: 0xFE0 (R/ ) ITM Peripheral Identification Register #0 */ - __IM uint32_t PID1; /*!< Offset: 0xFE4 (R/ ) ITM Peripheral Identification Register #1 */ - __IM uint32_t PID2; /*!< Offset: 0xFE8 (R/ ) ITM Peripheral Identification Register #2 */ - __IM uint32_t PID3; /*!< Offset: 0xFEC (R/ ) ITM Peripheral Identification Register #3 */ - __IM uint32_t CID0; /*!< Offset: 0xFF0 (R/ ) ITM Component Identification Register #0 */ - __IM uint32_t CID1; /*!< Offset: 0xFF4 (R/ ) ITM Component Identification Register #1 */ - __IM uint32_t CID2; /*!< Offset: 0xFF8 (R/ ) ITM Component Identification Register #2 */ - __IM uint32_t CID3; /*!< Offset: 0xFFC (R/ ) ITM Component Identification Register #3 */ -} ITM_Type; - -/* ITM Trace Privilege Register Definitions */ -#define ITM_TPR_PRIVMASK_Pos 0U /*!< ITM TPR: PRIVMASK Position */ -#define ITM_TPR_PRIVMASK_Msk (0xFFFFFFFFUL /*<< ITM_TPR_PRIVMASK_Pos*/) /*!< ITM TPR: PRIVMASK Mask */ - -/* ITM Trace Control Register Definitions */ -#define ITM_TCR_BUSY_Pos 23U /*!< ITM TCR: BUSY Position */ -#define ITM_TCR_BUSY_Msk (1UL << ITM_TCR_BUSY_Pos) /*!< ITM TCR: BUSY Mask */ - -#define ITM_TCR_TraceBusID_Pos 16U /*!< ITM TCR: ATBID Position */ -#define ITM_TCR_TraceBusID_Msk (0x7FUL << ITM_TCR_TraceBusID_Pos) /*!< ITM TCR: ATBID Mask */ - -#define ITM_TCR_GTSFREQ_Pos 10U /*!< ITM TCR: Global timestamp frequency Position */ -#define ITM_TCR_GTSFREQ_Msk (3UL << ITM_TCR_GTSFREQ_Pos) /*!< ITM TCR: Global timestamp frequency Mask */ - -#define ITM_TCR_TSPrescale_Pos 8U /*!< ITM TCR: TSPrescale Position */ -#define ITM_TCR_TSPrescale_Msk (3UL << ITM_TCR_TSPrescale_Pos) /*!< ITM TCR: TSPrescale Mask */ - -#define ITM_TCR_SWOENA_Pos 4U /*!< ITM TCR: SWOENA Position */ -#define ITM_TCR_SWOENA_Msk (1UL << ITM_TCR_SWOENA_Pos) /*!< ITM TCR: SWOENA Mask */ - -#define ITM_TCR_DWTENA_Pos 3U /*!< ITM TCR: DWTENA Position */ -#define ITM_TCR_DWTENA_Msk (1UL << ITM_TCR_DWTENA_Pos) /*!< ITM TCR: DWTENA Mask */ - -#define ITM_TCR_SYNCENA_Pos 2U /*!< ITM TCR: SYNCENA Position */ -#define ITM_TCR_SYNCENA_Msk (1UL << ITM_TCR_SYNCENA_Pos) /*!< ITM TCR: SYNCENA Mask */ - -#define ITM_TCR_TSENA_Pos 1U /*!< ITM TCR: TSENA Position */ -#define ITM_TCR_TSENA_Msk (1UL << ITM_TCR_TSENA_Pos) /*!< ITM TCR: TSENA Mask */ - -#define ITM_TCR_ITMENA_Pos 0U /*!< ITM TCR: ITM Enable bit Position */ -#define ITM_TCR_ITMENA_Msk (1UL /*<< ITM_TCR_ITMENA_Pos*/) /*!< ITM TCR: ITM Enable bit Mask */ - -/* ITM Integration Write Register Definitions */ -#define ITM_IWR_ATVALIDM_Pos 0U /*!< ITM IWR: ATVALIDM Position */ -#define ITM_IWR_ATVALIDM_Msk (1UL /*<< ITM_IWR_ATVALIDM_Pos*/) /*!< ITM IWR: ATVALIDM Mask */ - -/* ITM Integration Read Register Definitions */ -#define ITM_IRR_ATREADYM_Pos 0U /*!< ITM IRR: ATREADYM Position */ -#define ITM_IRR_ATREADYM_Msk (1UL /*<< ITM_IRR_ATREADYM_Pos*/) /*!< ITM IRR: ATREADYM Mask */ - -/* ITM Integration Mode Control Register Definitions */ -#define ITM_IMCR_INTEGRATION_Pos 0U /*!< ITM IMCR: INTEGRATION Position */ -#define ITM_IMCR_INTEGRATION_Msk (1UL /*<< ITM_IMCR_INTEGRATION_Pos*/) /*!< ITM IMCR: INTEGRATION Mask */ - -/* ITM Lock Status Register Definitions */ -#define ITM_LSR_ByteAcc_Pos 2U /*!< ITM LSR: ByteAcc Position */ -#define ITM_LSR_ByteAcc_Msk (1UL << ITM_LSR_ByteAcc_Pos) /*!< ITM LSR: ByteAcc Mask */ - -#define ITM_LSR_Access_Pos 1U /*!< ITM LSR: Access Position */ -#define ITM_LSR_Access_Msk (1UL << ITM_LSR_Access_Pos) /*!< ITM LSR: Access Mask */ - -#define ITM_LSR_Present_Pos 0U /*!< ITM LSR: Present Position */ -#define ITM_LSR_Present_Msk (1UL /*<< ITM_LSR_Present_Pos*/) /*!< ITM LSR: Present Mask */ - -/*@}*/ /* end of group CMSIS_ITM */ - - -/** - \ingroup CMSIS_core_register - \defgroup CMSIS_DWT Data Watchpoint and Trace (DWT) - \brief Type definitions for the Data Watchpoint and Trace (DWT) - @{ - */ - -/** - \brief Structure type to access the Data Watchpoint and Trace Register (DWT). - */ -typedef struct -{ - __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) Control Register */ - __IOM uint32_t CYCCNT; /*!< Offset: 0x004 (R/W) Cycle Count Register */ - __IOM uint32_t CPICNT; /*!< Offset: 0x008 (R/W) CPI Count Register */ - __IOM uint32_t EXCCNT; /*!< Offset: 0x00C (R/W) Exception Overhead Count Register */ - __IOM uint32_t SLEEPCNT; /*!< Offset: 0x010 (R/W) Sleep Count Register */ - __IOM uint32_t LSUCNT; /*!< Offset: 0x014 (R/W) LSU Count Register */ - __IOM uint32_t FOLDCNT; /*!< Offset: 0x018 (R/W) Folded-instruction Count Register */ - __IM uint32_t PCSR; /*!< Offset: 0x01C (R/ ) Program Counter Sample Register */ - __IOM uint32_t COMP0; /*!< Offset: 0x020 (R/W) Comparator Register 0 */ - __IOM uint32_t MASK0; /*!< Offset: 0x024 (R/W) Mask Register 0 */ - __IOM uint32_t FUNCTION0; /*!< Offset: 0x028 (R/W) Function Register 0 */ - uint32_t RESERVED0[1U]; - __IOM uint32_t COMP1; /*!< Offset: 0x030 (R/W) Comparator Register 1 */ - __IOM uint32_t MASK1; /*!< Offset: 0x034 (R/W) Mask Register 1 */ - __IOM uint32_t FUNCTION1; /*!< Offset: 0x038 (R/W) Function Register 1 */ - uint32_t RESERVED1[1U]; - __IOM uint32_t COMP2; /*!< Offset: 0x040 (R/W) Comparator Register 2 */ - __IOM uint32_t MASK2; /*!< Offset: 0x044 (R/W) Mask Register 2 */ - __IOM uint32_t FUNCTION2; /*!< Offset: 0x048 (R/W) Function Register 2 */ - uint32_t RESERVED2[1U]; - __IOM uint32_t COMP3; /*!< Offset: 0x050 (R/W) Comparator Register 3 */ - __IOM uint32_t MASK3; /*!< Offset: 0x054 (R/W) Mask Register 3 */ - __IOM uint32_t FUNCTION3; /*!< Offset: 0x058 (R/W) Function Register 3 */ -} DWT_Type; - -/* DWT Control Register Definitions */ -#define DWT_CTRL_NUMCOMP_Pos 28U /*!< DWT CTRL: NUMCOMP Position */ -#define DWT_CTRL_NUMCOMP_Msk (0xFUL << DWT_CTRL_NUMCOMP_Pos) /*!< DWT CTRL: NUMCOMP Mask */ - -#define DWT_CTRL_NOTRCPKT_Pos 27U /*!< DWT CTRL: NOTRCPKT Position */ -#define DWT_CTRL_NOTRCPKT_Msk (0x1UL << DWT_CTRL_NOTRCPKT_Pos) /*!< DWT CTRL: NOTRCPKT Mask */ - -#define DWT_CTRL_NOEXTTRIG_Pos 26U /*!< DWT CTRL: NOEXTTRIG Position */ -#define DWT_CTRL_NOEXTTRIG_Msk (0x1UL << DWT_CTRL_NOEXTTRIG_Pos) /*!< DWT CTRL: NOEXTTRIG Mask */ - -#define DWT_CTRL_NOCYCCNT_Pos 25U /*!< DWT CTRL: NOCYCCNT Position */ -#define DWT_CTRL_NOCYCCNT_Msk (0x1UL << DWT_CTRL_NOCYCCNT_Pos) /*!< DWT CTRL: NOCYCCNT Mask */ - -#define DWT_CTRL_NOPRFCNT_Pos 24U /*!< DWT CTRL: NOPRFCNT Position */ -#define DWT_CTRL_NOPRFCNT_Msk (0x1UL << DWT_CTRL_NOPRFCNT_Pos) /*!< DWT CTRL: NOPRFCNT Mask */ - -#define DWT_CTRL_CYCEVTENA_Pos 22U /*!< DWT CTRL: CYCEVTENA Position */ -#define DWT_CTRL_CYCEVTENA_Msk (0x1UL << DWT_CTRL_CYCEVTENA_Pos) /*!< DWT CTRL: CYCEVTENA Mask */ - -#define DWT_CTRL_FOLDEVTENA_Pos 21U /*!< DWT CTRL: FOLDEVTENA Position */ -#define DWT_CTRL_FOLDEVTENA_Msk (0x1UL << DWT_CTRL_FOLDEVTENA_Pos) /*!< DWT CTRL: FOLDEVTENA Mask */ - -#define DWT_CTRL_LSUEVTENA_Pos 20U /*!< DWT CTRL: LSUEVTENA Position */ -#define DWT_CTRL_LSUEVTENA_Msk (0x1UL << DWT_CTRL_LSUEVTENA_Pos) /*!< DWT CTRL: LSUEVTENA Mask */ - -#define DWT_CTRL_SLEEPEVTENA_Pos 19U /*!< DWT CTRL: SLEEPEVTENA Position */ -#define DWT_CTRL_SLEEPEVTENA_Msk (0x1UL << DWT_CTRL_SLEEPEVTENA_Pos) /*!< DWT CTRL: SLEEPEVTENA Mask */ - -#define DWT_CTRL_EXCEVTENA_Pos 18U /*!< DWT CTRL: EXCEVTENA Position */ -#define DWT_CTRL_EXCEVTENA_Msk (0x1UL << DWT_CTRL_EXCEVTENA_Pos) /*!< DWT CTRL: EXCEVTENA Mask */ - -#define DWT_CTRL_CPIEVTENA_Pos 17U /*!< DWT CTRL: CPIEVTENA Position */ -#define DWT_CTRL_CPIEVTENA_Msk (0x1UL << DWT_CTRL_CPIEVTENA_Pos) /*!< DWT CTRL: CPIEVTENA Mask */ - -#define DWT_CTRL_EXCTRCENA_Pos 16U /*!< DWT CTRL: EXCTRCENA Position */ -#define DWT_CTRL_EXCTRCENA_Msk (0x1UL << DWT_CTRL_EXCTRCENA_Pos) /*!< DWT CTRL: EXCTRCENA Mask */ - -#define DWT_CTRL_PCSAMPLENA_Pos 12U /*!< DWT CTRL: PCSAMPLENA Position */ -#define DWT_CTRL_PCSAMPLENA_Msk (0x1UL << DWT_CTRL_PCSAMPLENA_Pos) /*!< DWT CTRL: PCSAMPLENA Mask */ - -#define DWT_CTRL_SYNCTAP_Pos 10U /*!< DWT CTRL: SYNCTAP Position */ -#define DWT_CTRL_SYNCTAP_Msk (0x3UL << DWT_CTRL_SYNCTAP_Pos) /*!< DWT CTRL: SYNCTAP Mask */ - -#define DWT_CTRL_CYCTAP_Pos 9U /*!< DWT CTRL: CYCTAP Position */ -#define DWT_CTRL_CYCTAP_Msk (0x1UL << DWT_CTRL_CYCTAP_Pos) /*!< DWT CTRL: CYCTAP Mask */ - -#define DWT_CTRL_POSTINIT_Pos 5U /*!< DWT CTRL: POSTINIT Position */ -#define DWT_CTRL_POSTINIT_Msk (0xFUL << DWT_CTRL_POSTINIT_Pos) /*!< DWT CTRL: POSTINIT Mask */ - -#define DWT_CTRL_POSTPRESET_Pos 1U /*!< DWT CTRL: POSTPRESET Position */ -#define DWT_CTRL_POSTPRESET_Msk (0xFUL << DWT_CTRL_POSTPRESET_Pos) /*!< DWT CTRL: POSTPRESET Mask */ - -#define DWT_CTRL_CYCCNTENA_Pos 0U /*!< DWT CTRL: CYCCNTENA Position */ -#define DWT_CTRL_CYCCNTENA_Msk (0x1UL /*<< DWT_CTRL_CYCCNTENA_Pos*/) /*!< DWT CTRL: CYCCNTENA Mask */ - -/* DWT CPI Count Register Definitions */ -#define DWT_CPICNT_CPICNT_Pos 0U /*!< DWT CPICNT: CPICNT Position */ -#define DWT_CPICNT_CPICNT_Msk (0xFFUL /*<< DWT_CPICNT_CPICNT_Pos*/) /*!< DWT CPICNT: CPICNT Mask */ - -/* DWT Exception Overhead Count Register Definitions */ -#define DWT_EXCCNT_EXCCNT_Pos 0U /*!< DWT EXCCNT: EXCCNT Position */ -#define DWT_EXCCNT_EXCCNT_Msk (0xFFUL /*<< DWT_EXCCNT_EXCCNT_Pos*/) /*!< DWT EXCCNT: EXCCNT Mask */ - -/* DWT Sleep Count Register Definitions */ -#define DWT_SLEEPCNT_SLEEPCNT_Pos 0U /*!< DWT SLEEPCNT: SLEEPCNT Position */ -#define DWT_SLEEPCNT_SLEEPCNT_Msk (0xFFUL /*<< DWT_SLEEPCNT_SLEEPCNT_Pos*/) /*!< DWT SLEEPCNT: SLEEPCNT Mask */ - -/* DWT LSU Count Register Definitions */ -#define DWT_LSUCNT_LSUCNT_Pos 0U /*!< DWT LSUCNT: LSUCNT Position */ -#define DWT_LSUCNT_LSUCNT_Msk (0xFFUL /*<< DWT_LSUCNT_LSUCNT_Pos*/) /*!< DWT LSUCNT: LSUCNT Mask */ - -/* DWT Folded-instruction Count Register Definitions */ -#define DWT_FOLDCNT_FOLDCNT_Pos 0U /*!< DWT FOLDCNT: FOLDCNT Position */ -#define DWT_FOLDCNT_FOLDCNT_Msk (0xFFUL /*<< DWT_FOLDCNT_FOLDCNT_Pos*/) /*!< DWT FOLDCNT: FOLDCNT Mask */ - -/* DWT Comparator Mask Register Definitions */ -#define DWT_MASK_MASK_Pos 0U /*!< DWT MASK: MASK Position */ -#define DWT_MASK_MASK_Msk (0x1FUL /*<< DWT_MASK_MASK_Pos*/) /*!< DWT MASK: MASK Mask */ - -/* DWT Comparator Function Register Definitions */ -#define DWT_FUNCTION_MATCHED_Pos 24U /*!< DWT FUNCTION: MATCHED Position */ -#define DWT_FUNCTION_MATCHED_Msk (0x1UL << DWT_FUNCTION_MATCHED_Pos) /*!< DWT FUNCTION: MATCHED Mask */ - -#define DWT_FUNCTION_DATAVADDR1_Pos 16U /*!< DWT FUNCTION: DATAVADDR1 Position */ -#define DWT_FUNCTION_DATAVADDR1_Msk (0xFUL << DWT_FUNCTION_DATAVADDR1_Pos) /*!< DWT FUNCTION: DATAVADDR1 Mask */ - -#define DWT_FUNCTION_DATAVADDR0_Pos 12U /*!< DWT FUNCTION: DATAVADDR0 Position */ -#define DWT_FUNCTION_DATAVADDR0_Msk (0xFUL << DWT_FUNCTION_DATAVADDR0_Pos) /*!< DWT FUNCTION: DATAVADDR0 Mask */ - -#define DWT_FUNCTION_DATAVSIZE_Pos 10U /*!< DWT FUNCTION: DATAVSIZE Position */ -#define DWT_FUNCTION_DATAVSIZE_Msk (0x3UL << DWT_FUNCTION_DATAVSIZE_Pos) /*!< DWT FUNCTION: DATAVSIZE Mask */ - -#define DWT_FUNCTION_LNK1ENA_Pos 9U /*!< DWT FUNCTION: LNK1ENA Position */ -#define DWT_FUNCTION_LNK1ENA_Msk (0x1UL << DWT_FUNCTION_LNK1ENA_Pos) /*!< DWT FUNCTION: LNK1ENA Mask */ - -#define DWT_FUNCTION_DATAVMATCH_Pos 8U /*!< DWT FUNCTION: DATAVMATCH Position */ -#define DWT_FUNCTION_DATAVMATCH_Msk (0x1UL << DWT_FUNCTION_DATAVMATCH_Pos) /*!< DWT FUNCTION: DATAVMATCH Mask */ - -#define DWT_FUNCTION_CYCMATCH_Pos 7U /*!< DWT FUNCTION: CYCMATCH Position */ -#define DWT_FUNCTION_CYCMATCH_Msk (0x1UL << DWT_FUNCTION_CYCMATCH_Pos) /*!< DWT FUNCTION: CYCMATCH Mask */ - -#define DWT_FUNCTION_EMITRANGE_Pos 5U /*!< DWT FUNCTION: EMITRANGE Position */ -#define DWT_FUNCTION_EMITRANGE_Msk (0x1UL << DWT_FUNCTION_EMITRANGE_Pos) /*!< DWT FUNCTION: EMITRANGE Mask */ - -#define DWT_FUNCTION_FUNCTION_Pos 0U /*!< DWT FUNCTION: FUNCTION Position */ -#define DWT_FUNCTION_FUNCTION_Msk (0xFUL /*<< DWT_FUNCTION_FUNCTION_Pos*/) /*!< DWT FUNCTION: FUNCTION Mask */ - -/*@}*/ /* end of group CMSIS_DWT */ - - -/** - \ingroup CMSIS_core_register - \defgroup CMSIS_TPI Trace Port Interface (TPI) - \brief Type definitions for the Trace Port Interface (TPI) - @{ - */ - -/** - \brief Structure type to access the Trace Port Interface Register (TPI). - */ -typedef struct -{ - __IOM uint32_t SSPSR; /*!< Offset: 0x000 (R/ ) Supported Parallel Port Size Register */ - __IOM uint32_t CSPSR; /*!< Offset: 0x004 (R/W) Current Parallel Port Size Register */ - uint32_t RESERVED0[2U]; - __IOM uint32_t ACPR; /*!< Offset: 0x010 (R/W) Asynchronous Clock Prescaler Register */ - uint32_t RESERVED1[55U]; - __IOM uint32_t SPPR; /*!< Offset: 0x0F0 (R/W) Selected Pin Protocol Register */ - uint32_t RESERVED2[131U]; - __IM uint32_t FFSR; /*!< Offset: 0x300 (R/ ) Formatter and Flush Status Register */ - __IOM uint32_t FFCR; /*!< Offset: 0x304 (R/W) Formatter and Flush Control Register */ - __IM uint32_t FSCR; /*!< Offset: 0x308 (R/ ) Formatter Synchronization Counter Register */ - uint32_t RESERVED3[759U]; - __IM uint32_t TRIGGER; /*!< Offset: 0xEE8 (R/ ) TRIGGER */ - __IM uint32_t FIFO0; /*!< Offset: 0xEEC (R/ ) Integration ETM Data */ - __IM uint32_t ITATBCTR2; /*!< Offset: 0xEF0 (R/ ) ITATBCTR2 */ - uint32_t RESERVED4[1U]; - __IM uint32_t ITATBCTR0; /*!< Offset: 0xEF8 (R/ ) ITATBCTR0 */ - __IM uint32_t FIFO1; /*!< Offset: 0xEFC (R/ ) Integration ITM Data */ - __IOM uint32_t ITCTRL; /*!< Offset: 0xF00 (R/W) Integration Mode Control */ - uint32_t RESERVED5[39U]; - __IOM uint32_t CLAIMSET; /*!< Offset: 0xFA0 (R/W) Claim tag set */ - __IOM uint32_t CLAIMCLR; /*!< Offset: 0xFA4 (R/W) Claim tag clear */ - uint32_t RESERVED7[8U]; - __IM uint32_t DEVID; /*!< Offset: 0xFC8 (R/ ) TPIU_DEVID */ - __IM uint32_t DEVTYPE; /*!< Offset: 0xFCC (R/ ) TPIU_DEVTYPE */ -} TPI_Type; - -/* TPI Asynchronous Clock Prescaler Register Definitions */ -#define TPI_ACPR_PRESCALER_Pos 0U /*!< @Deprecated TPI ACPR: PRESCALER Position */ -#define TPI_ACPR_PRESCALER_Msk (0x1FFFUL /*<< TPI_ACPR_PRESCALER_Pos*/) /*!< @Deprecated TPI ACPR: PRESCALER Mask */ - -#define TPI_ACPR_SWOSCALER_Pos 0U /*!< TPI ACPR: SWOSCALER Position */ -#define TPI_ACPR_SWOSCALER_Msk (0xFFFFUL /*<< TPI_ACPR_SWOSCALER_Pos*/) /*!< TPI ACPR: SWOSCALER Mask */ - -/* TPI Selected Pin Protocol Register Definitions */ -#define TPI_SPPR_TXMODE_Pos 0U /*!< TPI SPPR: TXMODE Position */ -#define TPI_SPPR_TXMODE_Msk (0x3UL /*<< TPI_SPPR_TXMODE_Pos*/) /*!< TPI SPPR: TXMODE Mask */ - -/* TPI Formatter and Flush Status Register Definitions */ -#define TPI_FFSR_FtNonStop_Pos 3U /*!< TPI FFSR: FtNonStop Position */ -#define TPI_FFSR_FtNonStop_Msk (0x1UL << TPI_FFSR_FtNonStop_Pos) /*!< TPI FFSR: FtNonStop Mask */ - -#define TPI_FFSR_TCPresent_Pos 2U /*!< TPI FFSR: TCPresent Position */ -#define TPI_FFSR_TCPresent_Msk (0x1UL << TPI_FFSR_TCPresent_Pos) /*!< TPI FFSR: TCPresent Mask */ - -#define TPI_FFSR_FtStopped_Pos 1U /*!< TPI FFSR: FtStopped Position */ -#define TPI_FFSR_FtStopped_Msk (0x1UL << TPI_FFSR_FtStopped_Pos) /*!< TPI FFSR: FtStopped Mask */ - -#define TPI_FFSR_FlInProg_Pos 0U /*!< TPI FFSR: FlInProg Position */ -#define TPI_FFSR_FlInProg_Msk (0x1UL /*<< TPI_FFSR_FlInProg_Pos*/) /*!< TPI FFSR: FlInProg Mask */ - -/* TPI Formatter and Flush Control Register Definitions */ -#define TPI_FFCR_TrigIn_Pos 8U /*!< TPI FFCR: TrigIn Position */ -#define TPI_FFCR_TrigIn_Msk (0x1UL << TPI_FFCR_TrigIn_Pos) /*!< TPI FFCR: TrigIn Mask */ - -#define TPI_FFCR_EnFCont_Pos 1U /*!< TPI FFCR: EnFCont Position */ -#define TPI_FFCR_EnFCont_Msk (0x1UL << TPI_FFCR_EnFCont_Pos) /*!< TPI FFCR: EnFCont Mask */ - -/* TPI TRIGGER Register Definitions */ -#define TPI_TRIGGER_TRIGGER_Pos 0U /*!< TPI TRIGGER: TRIGGER Position */ -#define TPI_TRIGGER_TRIGGER_Msk (0x1UL /*<< TPI_TRIGGER_TRIGGER_Pos*/) /*!< TPI TRIGGER: TRIGGER Mask */ - -/* TPI Integration ETM Data Register Definitions (FIFO0) */ -#define TPI_FIFO0_ITM_ATVALID_Pos 29U /*!< TPI FIFO0: ITM_ATVALID Position */ -#define TPI_FIFO0_ITM_ATVALID_Msk (0x3UL << TPI_FIFO0_ITM_ATVALID_Pos) /*!< TPI FIFO0: ITM_ATVALID Mask */ - -#define TPI_FIFO0_ITM_bytecount_Pos 27U /*!< TPI FIFO0: ITM_bytecount Position */ -#define TPI_FIFO0_ITM_bytecount_Msk (0x3UL << TPI_FIFO0_ITM_bytecount_Pos) /*!< TPI FIFO0: ITM_bytecount Mask */ - -#define TPI_FIFO0_ETM_ATVALID_Pos 26U /*!< TPI FIFO0: ETM_ATVALID Position */ -#define TPI_FIFO0_ETM_ATVALID_Msk (0x3UL << TPI_FIFO0_ETM_ATVALID_Pos) /*!< TPI FIFO0: ETM_ATVALID Mask */ - -#define TPI_FIFO0_ETM_bytecount_Pos 24U /*!< TPI FIFO0: ETM_bytecount Position */ -#define TPI_FIFO0_ETM_bytecount_Msk (0x3UL << TPI_FIFO0_ETM_bytecount_Pos) /*!< TPI FIFO0: ETM_bytecount Mask */ - -#define TPI_FIFO0_ETM2_Pos 16U /*!< TPI FIFO0: ETM2 Position */ -#define TPI_FIFO0_ETM2_Msk (0xFFUL << TPI_FIFO0_ETM2_Pos) /*!< TPI FIFO0: ETM2 Mask */ - -#define TPI_FIFO0_ETM1_Pos 8U /*!< TPI FIFO0: ETM1 Position */ -#define TPI_FIFO0_ETM1_Msk (0xFFUL << TPI_FIFO0_ETM1_Pos) /*!< TPI FIFO0: ETM1 Mask */ - -#define TPI_FIFO0_ETM0_Pos 0U /*!< TPI FIFO0: ETM0 Position */ -#define TPI_FIFO0_ETM0_Msk (0xFFUL /*<< TPI_FIFO0_ETM0_Pos*/) /*!< TPI FIFO0: ETM0 Mask */ - -/* TPI ITATBCTR2 Register Definitions */ -#define TPI_ITATBCTR2_ATREADY_Pos 0U /*!< TPI ITATBCTR2: ATREADY Position */ -#define TPI_ITATBCTR2_ATREADY_Msk (0x1UL /*<< TPI_ITATBCTR2_ATREADY_Pos*/) /*!< TPI ITATBCTR2: ATREADY Mask */ - -/* TPI Integration ITM Data Register Definitions (FIFO1) */ -#define TPI_FIFO1_ITM_ATVALID_Pos 29U /*!< TPI FIFO1: ITM_ATVALID Position */ -#define TPI_FIFO1_ITM_ATVALID_Msk (0x3UL << TPI_FIFO1_ITM_ATVALID_Pos) /*!< TPI FIFO1: ITM_ATVALID Mask */ - -#define TPI_FIFO1_ITM_bytecount_Pos 27U /*!< TPI FIFO1: ITM_bytecount Position */ -#define TPI_FIFO1_ITM_bytecount_Msk (0x3UL << TPI_FIFO1_ITM_bytecount_Pos) /*!< TPI FIFO1: ITM_bytecount Mask */ - -#define TPI_FIFO1_ETM_ATVALID_Pos 26U /*!< TPI FIFO1: ETM_ATVALID Position */ -#define TPI_FIFO1_ETM_ATVALID_Msk (0x3UL << TPI_FIFO1_ETM_ATVALID_Pos) /*!< TPI FIFO1: ETM_ATVALID Mask */ - -#define TPI_FIFO1_ETM_bytecount_Pos 24U /*!< TPI FIFO1: ETM_bytecount Position */ -#define TPI_FIFO1_ETM_bytecount_Msk (0x3UL << TPI_FIFO1_ETM_bytecount_Pos) /*!< TPI FIFO1: ETM_bytecount Mask */ - -#define TPI_FIFO1_ITM2_Pos 16U /*!< TPI FIFO1: ITM2 Position */ -#define TPI_FIFO1_ITM2_Msk (0xFFUL << TPI_FIFO1_ITM2_Pos) /*!< TPI FIFO1: ITM2 Mask */ - -#define TPI_FIFO1_ITM1_Pos 8U /*!< TPI FIFO1: ITM1 Position */ -#define TPI_FIFO1_ITM1_Msk (0xFFUL << TPI_FIFO1_ITM1_Pos) /*!< TPI FIFO1: ITM1 Mask */ - -#define TPI_FIFO1_ITM0_Pos 0U /*!< TPI FIFO1: ITM0 Position */ -#define TPI_FIFO1_ITM0_Msk (0xFFUL /*<< TPI_FIFO1_ITM0_Pos*/) /*!< TPI FIFO1: ITM0 Mask */ - -/* TPI ITATBCTR0 Register Definitions */ -#define TPI_ITATBCTR0_ATREADY_Pos 0U /*!< TPI ITATBCTR0: ATREADY Position */ -#define TPI_ITATBCTR0_ATREADY_Msk (0x1UL /*<< TPI_ITATBCTR0_ATREADY_Pos*/) /*!< TPI ITATBCTR0: ATREADY Mask */ - -/* TPI Integration Mode Control Register Definitions */ -#define TPI_ITCTRL_Mode_Pos 0U /*!< TPI ITCTRL: Mode Position */ -#define TPI_ITCTRL_Mode_Msk (0x1UL /*<< TPI_ITCTRL_Mode_Pos*/) /*!< TPI ITCTRL: Mode Mask */ - -/* TPI DEVID Register Definitions */ -#define TPI_DEVID_NRZVALID_Pos 11U /*!< TPI DEVID: NRZVALID Position */ -#define TPI_DEVID_NRZVALID_Msk (0x1UL << TPI_DEVID_NRZVALID_Pos) /*!< TPI DEVID: NRZVALID Mask */ - -#define TPI_DEVID_MANCVALID_Pos 10U /*!< TPI DEVID: MANCVALID Position */ -#define TPI_DEVID_MANCVALID_Msk (0x1UL << TPI_DEVID_MANCVALID_Pos) /*!< TPI DEVID: MANCVALID Mask */ - -#define TPI_DEVID_PTINVALID_Pos 9U /*!< TPI DEVID: PTINVALID Position */ -#define TPI_DEVID_PTINVALID_Msk (0x1UL << TPI_DEVID_PTINVALID_Pos) /*!< TPI DEVID: PTINVALID Mask */ - -#define TPI_DEVID_MinBufSz_Pos 6U /*!< TPI DEVID: MinBufSz Position */ -#define TPI_DEVID_MinBufSz_Msk (0x7UL << TPI_DEVID_MinBufSz_Pos) /*!< TPI DEVID: MinBufSz Mask */ - -#define TPI_DEVID_AsynClkIn_Pos 5U /*!< TPI DEVID: AsynClkIn Position */ -#define TPI_DEVID_AsynClkIn_Msk (0x1UL << TPI_DEVID_AsynClkIn_Pos) /*!< TPI DEVID: AsynClkIn Mask */ - -#define TPI_DEVID_NrTraceInput_Pos 0U /*!< TPI DEVID: NrTraceInput Position */ -#define TPI_DEVID_NrTraceInput_Msk (0x1FUL /*<< TPI_DEVID_NrTraceInput_Pos*/) /*!< TPI DEVID: NrTraceInput Mask */ - -/* TPI DEVTYPE Register Definitions */ -#define TPI_DEVTYPE_MajorType_Pos 4U /*!< TPI DEVTYPE: MajorType Position */ -#define TPI_DEVTYPE_MajorType_Msk (0xFUL << TPI_DEVTYPE_MajorType_Pos) /*!< TPI DEVTYPE: MajorType Mask */ - -#define TPI_DEVTYPE_SubType_Pos 0U /*!< TPI DEVTYPE: SubType Position */ -#define TPI_DEVTYPE_SubType_Msk (0xFUL /*<< TPI_DEVTYPE_SubType_Pos*/) /*!< TPI DEVTYPE: SubType Mask */ - -/*@}*/ /* end of group CMSIS_TPI */ - - -#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) -/** - \ingroup CMSIS_core_register - \defgroup CMSIS_MPU Memory Protection Unit (MPU) - \brief Type definitions for the Memory Protection Unit (MPU) - @{ - */ - -/** - \brief Structure type to access the Memory Protection Unit (MPU). - */ -typedef struct -{ - __IM uint32_t TYPE; /*!< Offset: 0x000 (R/ ) MPU Type Register */ - __IOM uint32_t CTRL; /*!< Offset: 0x004 (R/W) MPU Control Register */ - __IOM uint32_t RNR; /*!< Offset: 0x008 (R/W) MPU Region RNRber Register */ - __IOM uint32_t RBAR; /*!< Offset: 0x00C (R/W) MPU Region Base Address Register */ - __IOM uint32_t RASR; /*!< Offset: 0x010 (R/W) MPU Region Attribute and Size Register */ - __IOM uint32_t RBAR_A1; /*!< Offset: 0x014 (R/W) MPU Alias 1 Region Base Address Register */ - __IOM uint32_t RASR_A1; /*!< Offset: 0x018 (R/W) MPU Alias 1 Region Attribute and Size Register */ - __IOM uint32_t RBAR_A2; /*!< Offset: 0x01C (R/W) MPU Alias 2 Region Base Address Register */ - __IOM uint32_t RASR_A2; /*!< Offset: 0x020 (R/W) MPU Alias 2 Region Attribute and Size Register */ - __IOM uint32_t RBAR_A3; /*!< Offset: 0x024 (R/W) MPU Alias 3 Region Base Address Register */ - __IOM uint32_t RASR_A3; /*!< Offset: 0x028 (R/W) MPU Alias 3 Region Attribute and Size Register */ -} MPU_Type; - -#define MPU_TYPE_RALIASES 4U - -/* MPU Type Register Definitions */ -#define MPU_TYPE_IREGION_Pos 16U /*!< MPU TYPE: IREGION Position */ -#define MPU_TYPE_IREGION_Msk (0xFFUL << MPU_TYPE_IREGION_Pos) /*!< MPU TYPE: IREGION Mask */ - -#define MPU_TYPE_DREGION_Pos 8U /*!< MPU TYPE: DREGION Position */ -#define MPU_TYPE_DREGION_Msk (0xFFUL << MPU_TYPE_DREGION_Pos) /*!< MPU TYPE: DREGION Mask */ - -#define MPU_TYPE_SEPARATE_Pos 0U /*!< MPU TYPE: SEPARATE Position */ -#define MPU_TYPE_SEPARATE_Msk (1UL /*<< MPU_TYPE_SEPARATE_Pos*/) /*!< MPU TYPE: SEPARATE Mask */ - -/* MPU Control Register Definitions */ -#define MPU_CTRL_PRIVDEFENA_Pos 2U /*!< MPU CTRL: PRIVDEFENA Position */ -#define MPU_CTRL_PRIVDEFENA_Msk (1UL << MPU_CTRL_PRIVDEFENA_Pos) /*!< MPU CTRL: PRIVDEFENA Mask */ - -#define MPU_CTRL_HFNMIENA_Pos 1U /*!< MPU CTRL: HFNMIENA Position */ -#define MPU_CTRL_HFNMIENA_Msk (1UL << MPU_CTRL_HFNMIENA_Pos) /*!< MPU CTRL: HFNMIENA Mask */ - -#define MPU_CTRL_ENABLE_Pos 0U /*!< MPU CTRL: ENABLE Position */ -#define MPU_CTRL_ENABLE_Msk (1UL /*<< MPU_CTRL_ENABLE_Pos*/) /*!< MPU CTRL: ENABLE Mask */ - -/* MPU Region Number Register Definitions */ -#define MPU_RNR_REGION_Pos 0U /*!< MPU RNR: REGION Position */ -#define MPU_RNR_REGION_Msk (0xFFUL /*<< MPU_RNR_REGION_Pos*/) /*!< MPU RNR: REGION Mask */ - -/* MPU Region Base Address Register Definitions */ -#define MPU_RBAR_ADDR_Pos 5U /*!< MPU RBAR: ADDR Position */ -#define MPU_RBAR_ADDR_Msk (0x7FFFFFFUL << MPU_RBAR_ADDR_Pos) /*!< MPU RBAR: ADDR Mask */ - -#define MPU_RBAR_VALID_Pos 4U /*!< MPU RBAR: VALID Position */ -#define MPU_RBAR_VALID_Msk (1UL << MPU_RBAR_VALID_Pos) /*!< MPU RBAR: VALID Mask */ - -#define MPU_RBAR_REGION_Pos 0U /*!< MPU RBAR: REGION Position */ -#define MPU_RBAR_REGION_Msk (0xFUL /*<< MPU_RBAR_REGION_Pos*/) /*!< MPU RBAR: REGION Mask */ - -/* MPU Region Attribute and Size Register Definitions */ -#define MPU_RASR_ATTRS_Pos 16U /*!< MPU RASR: MPU Region Attribute field Position */ -#define MPU_RASR_ATTRS_Msk (0xFFFFUL << MPU_RASR_ATTRS_Pos) /*!< MPU RASR: MPU Region Attribute field Mask */ - -#define MPU_RASR_XN_Pos 28U /*!< MPU RASR: ATTRS.XN Position */ -#define MPU_RASR_XN_Msk (1UL << MPU_RASR_XN_Pos) /*!< MPU RASR: ATTRS.XN Mask */ - -#define MPU_RASR_AP_Pos 24U /*!< MPU RASR: ATTRS.AP Position */ -#define MPU_RASR_AP_Msk (0x7UL << MPU_RASR_AP_Pos) /*!< MPU RASR: ATTRS.AP Mask */ - -#define MPU_RASR_TEX_Pos 19U /*!< MPU RASR: ATTRS.TEX Position */ -#define MPU_RASR_TEX_Msk (0x7UL << MPU_RASR_TEX_Pos) /*!< MPU RASR: ATTRS.TEX Mask */ - -#define MPU_RASR_S_Pos 18U /*!< MPU RASR: ATTRS.S Position */ -#define MPU_RASR_S_Msk (1UL << MPU_RASR_S_Pos) /*!< MPU RASR: ATTRS.S Mask */ - -#define MPU_RASR_C_Pos 17U /*!< MPU RASR: ATTRS.C Position */ -#define MPU_RASR_C_Msk (1UL << MPU_RASR_C_Pos) /*!< MPU RASR: ATTRS.C Mask */ - -#define MPU_RASR_B_Pos 16U /*!< MPU RASR: ATTRS.B Position */ -#define MPU_RASR_B_Msk (1UL << MPU_RASR_B_Pos) /*!< MPU RASR: ATTRS.B Mask */ - -#define MPU_RASR_SRD_Pos 8U /*!< MPU RASR: Sub-Region Disable Position */ -#define MPU_RASR_SRD_Msk (0xFFUL << MPU_RASR_SRD_Pos) /*!< MPU RASR: Sub-Region Disable Mask */ - -#define MPU_RASR_SIZE_Pos 1U /*!< MPU RASR: Region Size Field Position */ -#define MPU_RASR_SIZE_Msk (0x1FUL << MPU_RASR_SIZE_Pos) /*!< MPU RASR: Region Size Field Mask */ - -#define MPU_RASR_ENABLE_Pos 0U /*!< MPU RASR: Region enable bit Position */ -#define MPU_RASR_ENABLE_Msk (1UL /*<< MPU_RASR_ENABLE_Pos*/) /*!< MPU RASR: Region enable bit Disable Mask */ - -/*@} end of group CMSIS_MPU */ -#endif /* defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) */ - - -/** - \ingroup CMSIS_core_register - \defgroup CMSIS_FPU Floating Point Unit (FPU) - \brief Type definitions for the Floating Point Unit (FPU) - @{ - */ - -/** - \brief Structure type to access the Floating Point Unit (FPU). - */ -typedef struct -{ - uint32_t RESERVED0[1U]; - __IOM uint32_t FPCCR; /*!< Offset: 0x004 (R/W) Floating-Point Context Control Register */ - __IOM uint32_t FPCAR; /*!< Offset: 0x008 (R/W) Floating-Point Context Address Register */ - __IOM uint32_t FPDSCR; /*!< Offset: 0x00C (R/W) Floating-Point Default Status Control Register */ - __IM uint32_t MVFR0; /*!< Offset: 0x010 (R/ ) Media and FP Feature Register 0 */ - __IM uint32_t MVFR1; /*!< Offset: 0x014 (R/ ) Media and FP Feature Register 1 */ -} FPU_Type; - -/* Floating-Point Context Control Register Definitions */ -#define FPU_FPCCR_ASPEN_Pos 31U /*!< FPCCR: ASPEN bit Position */ -#define FPU_FPCCR_ASPEN_Msk (1UL << FPU_FPCCR_ASPEN_Pos) /*!< FPCCR: ASPEN bit Mask */ - -#define FPU_FPCCR_LSPEN_Pos 30U /*!< FPCCR: LSPEN Position */ -#define FPU_FPCCR_LSPEN_Msk (1UL << FPU_FPCCR_LSPEN_Pos) /*!< FPCCR: LSPEN bit Mask */ - -#define FPU_FPCCR_MONRDY_Pos 8U /*!< FPCCR: MONRDY Position */ -#define FPU_FPCCR_MONRDY_Msk (1UL << FPU_FPCCR_MONRDY_Pos) /*!< FPCCR: MONRDY bit Mask */ - -#define FPU_FPCCR_BFRDY_Pos 6U /*!< FPCCR: BFRDY Position */ -#define FPU_FPCCR_BFRDY_Msk (1UL << FPU_FPCCR_BFRDY_Pos) /*!< FPCCR: BFRDY bit Mask */ - -#define FPU_FPCCR_MMRDY_Pos 5U /*!< FPCCR: MMRDY Position */ -#define FPU_FPCCR_MMRDY_Msk (1UL << FPU_FPCCR_MMRDY_Pos) /*!< FPCCR: MMRDY bit Mask */ - -#define FPU_FPCCR_HFRDY_Pos 4U /*!< FPCCR: HFRDY Position */ -#define FPU_FPCCR_HFRDY_Msk (1UL << FPU_FPCCR_HFRDY_Pos) /*!< FPCCR: HFRDY bit Mask */ - -#define FPU_FPCCR_THREAD_Pos 3U /*!< FPCCR: processor mode bit Position */ -#define FPU_FPCCR_THREAD_Msk (1UL << FPU_FPCCR_THREAD_Pos) /*!< FPCCR: processor mode active bit Mask */ - -#define FPU_FPCCR_USER_Pos 1U /*!< FPCCR: privilege level bit Position */ -#define FPU_FPCCR_USER_Msk (1UL << FPU_FPCCR_USER_Pos) /*!< FPCCR: privilege level bit Mask */ - -#define FPU_FPCCR_LSPACT_Pos 0U /*!< FPCCR: Lazy state preservation active bit Position */ -#define FPU_FPCCR_LSPACT_Msk (1UL /*<< FPU_FPCCR_LSPACT_Pos*/) /*!< FPCCR: Lazy state preservation active bit Mask */ - -/* Floating-Point Context Address Register Definitions */ -#define FPU_FPCAR_ADDRESS_Pos 3U /*!< FPCAR: ADDRESS bit Position */ -#define FPU_FPCAR_ADDRESS_Msk (0x1FFFFFFFUL << FPU_FPCAR_ADDRESS_Pos) /*!< FPCAR: ADDRESS bit Mask */ - -/* Floating-Point Default Status Control Register Definitions */ -#define FPU_FPDSCR_AHP_Pos 26U /*!< FPDSCR: AHP bit Position */ -#define FPU_FPDSCR_AHP_Msk (1UL << FPU_FPDSCR_AHP_Pos) /*!< FPDSCR: AHP bit Mask */ - -#define FPU_FPDSCR_DN_Pos 25U /*!< FPDSCR: DN bit Position */ -#define FPU_FPDSCR_DN_Msk (1UL << FPU_FPDSCR_DN_Pos) /*!< FPDSCR: DN bit Mask */ - -#define FPU_FPDSCR_FZ_Pos 24U /*!< FPDSCR: FZ bit Position */ -#define FPU_FPDSCR_FZ_Msk (1UL << FPU_FPDSCR_FZ_Pos) /*!< FPDSCR: FZ bit Mask */ - -#define FPU_FPDSCR_RMode_Pos 22U /*!< FPDSCR: RMode bit Position */ -#define FPU_FPDSCR_RMode_Msk (3UL << FPU_FPDSCR_RMode_Pos) /*!< FPDSCR: RMode bit Mask */ - -/* Media and FP Feature Register 0 Definitions */ -#define FPU_MVFR0_FP_rounding_modes_Pos 28U /*!< MVFR0: FP rounding modes bits Position */ -#define FPU_MVFR0_FP_rounding_modes_Msk (0xFUL << FPU_MVFR0_FP_rounding_modes_Pos) /*!< MVFR0: FP rounding modes bits Mask */ - -#define FPU_MVFR0_Short_vectors_Pos 24U /*!< MVFR0: Short vectors bits Position */ -#define FPU_MVFR0_Short_vectors_Msk (0xFUL << FPU_MVFR0_Short_vectors_Pos) /*!< MVFR0: Short vectors bits Mask */ - -#define FPU_MVFR0_Square_root_Pos 20U /*!< MVFR0: Square root bits Position */ -#define FPU_MVFR0_Square_root_Msk (0xFUL << FPU_MVFR0_Square_root_Pos) /*!< MVFR0: Square root bits Mask */ - -#define FPU_MVFR0_Divide_Pos 16U /*!< MVFR0: Divide bits Position */ -#define FPU_MVFR0_Divide_Msk (0xFUL << FPU_MVFR0_Divide_Pos) /*!< MVFR0: Divide bits Mask */ - -#define FPU_MVFR0_FP_excep_trapping_Pos 12U /*!< MVFR0: FP exception trapping bits Position */ -#define FPU_MVFR0_FP_excep_trapping_Msk (0xFUL << FPU_MVFR0_FP_excep_trapping_Pos) /*!< MVFR0: FP exception trapping bits Mask */ - -#define FPU_MVFR0_Double_precision_Pos 8U /*!< MVFR0: Double-precision bits Position */ -#define FPU_MVFR0_Double_precision_Msk (0xFUL << FPU_MVFR0_Double_precision_Pos) /*!< MVFR0: Double-precision bits Mask */ - -#define FPU_MVFR0_Single_precision_Pos 4U /*!< MVFR0: Single-precision bits Position */ -#define FPU_MVFR0_Single_precision_Msk (0xFUL << FPU_MVFR0_Single_precision_Pos) /*!< MVFR0: Single-precision bits Mask */ - -#define FPU_MVFR0_A_SIMD_registers_Pos 0U /*!< MVFR0: A_SIMD registers bits Position */ -#define FPU_MVFR0_A_SIMD_registers_Msk (0xFUL /*<< FPU_MVFR0_A_SIMD_registers_Pos*/) /*!< MVFR0: A_SIMD registers bits Mask */ - -/* Media and FP Feature Register 1 Definitions */ -#define FPU_MVFR1_FP_fused_MAC_Pos 28U /*!< MVFR1: FP fused MAC bits Position */ -#define FPU_MVFR1_FP_fused_MAC_Msk (0xFUL << FPU_MVFR1_FP_fused_MAC_Pos) /*!< MVFR1: FP fused MAC bits Mask */ - -#define FPU_MVFR1_FP_HPFP_Pos 24U /*!< MVFR1: FP HPFP bits Position */ -#define FPU_MVFR1_FP_HPFP_Msk (0xFUL << FPU_MVFR1_FP_HPFP_Pos) /*!< MVFR1: FP HPFP bits Mask */ - -#define FPU_MVFR1_D_NaN_mode_Pos 4U /*!< MVFR1: D_NaN mode bits Position */ -#define FPU_MVFR1_D_NaN_mode_Msk (0xFUL << FPU_MVFR1_D_NaN_mode_Pos) /*!< MVFR1: D_NaN mode bits Mask */ - -#define FPU_MVFR1_FtZ_mode_Pos 0U /*!< MVFR1: FtZ mode bits Position */ -#define FPU_MVFR1_FtZ_mode_Msk (0xFUL /*<< FPU_MVFR1_FtZ_mode_Pos*/) /*!< MVFR1: FtZ mode bits Mask */ - -/*@} end of group CMSIS_FPU */ - - -/** - \ingroup CMSIS_core_register - \defgroup CMSIS_CoreDebug Core Debug Registers (CoreDebug) - \brief Type definitions for the Core Debug Registers - @{ - */ - -/** - \brief Structure type to access the Core Debug Register (CoreDebug). - */ -typedef struct -{ - __IOM uint32_t DHCSR; /*!< Offset: 0x000 (R/W) Debug Halting Control and Status Register */ - __OM uint32_t DCRSR; /*!< Offset: 0x004 ( /W) Debug Core Register Selector Register */ - __IOM uint32_t DCRDR; /*!< Offset: 0x008 (R/W) Debug Core Register Data Register */ - __IOM uint32_t DEMCR; /*!< Offset: 0x00C (R/W) Debug Exception and Monitor Control Register */ -} CoreDebug_Type; - -/* Debug Halting Control and Status Register Definitions */ -#define CoreDebug_DHCSR_DBGKEY_Pos 16U /*!< CoreDebug DHCSR: DBGKEY Position */ -#define CoreDebug_DHCSR_DBGKEY_Msk (0xFFFFUL << CoreDebug_DHCSR_DBGKEY_Pos) /*!< CoreDebug DHCSR: DBGKEY Mask */ - -#define CoreDebug_DHCSR_S_RESET_ST_Pos 25U /*!< CoreDebug DHCSR: S_RESET_ST Position */ -#define CoreDebug_DHCSR_S_RESET_ST_Msk (1UL << CoreDebug_DHCSR_S_RESET_ST_Pos) /*!< CoreDebug DHCSR: S_RESET_ST Mask */ - -#define CoreDebug_DHCSR_S_RETIRE_ST_Pos 24U /*!< CoreDebug DHCSR: S_RETIRE_ST Position */ -#define CoreDebug_DHCSR_S_RETIRE_ST_Msk (1UL << CoreDebug_DHCSR_S_RETIRE_ST_Pos) /*!< CoreDebug DHCSR: S_RETIRE_ST Mask */ - -#define CoreDebug_DHCSR_S_LOCKUP_Pos 19U /*!< CoreDebug DHCSR: S_LOCKUP Position */ -#define CoreDebug_DHCSR_S_LOCKUP_Msk (1UL << CoreDebug_DHCSR_S_LOCKUP_Pos) /*!< CoreDebug DHCSR: S_LOCKUP Mask */ - -#define CoreDebug_DHCSR_S_SLEEP_Pos 18U /*!< CoreDebug DHCSR: S_SLEEP Position */ -#define CoreDebug_DHCSR_S_SLEEP_Msk (1UL << CoreDebug_DHCSR_S_SLEEP_Pos) /*!< CoreDebug DHCSR: S_SLEEP Mask */ - -#define CoreDebug_DHCSR_S_HALT_Pos 17U /*!< CoreDebug DHCSR: S_HALT Position */ -#define CoreDebug_DHCSR_S_HALT_Msk (1UL << CoreDebug_DHCSR_S_HALT_Pos) /*!< CoreDebug DHCSR: S_HALT Mask */ - -#define CoreDebug_DHCSR_S_REGRDY_Pos 16U /*!< CoreDebug DHCSR: S_REGRDY Position */ -#define CoreDebug_DHCSR_S_REGRDY_Msk (1UL << CoreDebug_DHCSR_S_REGRDY_Pos) /*!< CoreDebug DHCSR: S_REGRDY Mask */ - -#define CoreDebug_DHCSR_C_SNAPSTALL_Pos 5U /*!< CoreDebug DHCSR: C_SNAPSTALL Position */ -#define CoreDebug_DHCSR_C_SNAPSTALL_Msk (1UL << CoreDebug_DHCSR_C_SNAPSTALL_Pos) /*!< CoreDebug DHCSR: C_SNAPSTALL Mask */ - -#define CoreDebug_DHCSR_C_MASKINTS_Pos 3U /*!< CoreDebug DHCSR: C_MASKINTS Position */ -#define CoreDebug_DHCSR_C_MASKINTS_Msk (1UL << CoreDebug_DHCSR_C_MASKINTS_Pos) /*!< CoreDebug DHCSR: C_MASKINTS Mask */ - -#define CoreDebug_DHCSR_C_STEP_Pos 2U /*!< CoreDebug DHCSR: C_STEP Position */ -#define CoreDebug_DHCSR_C_STEP_Msk (1UL << CoreDebug_DHCSR_C_STEP_Pos) /*!< CoreDebug DHCSR: C_STEP Mask */ - -#define CoreDebug_DHCSR_C_HALT_Pos 1U /*!< CoreDebug DHCSR: C_HALT Position */ -#define CoreDebug_DHCSR_C_HALT_Msk (1UL << CoreDebug_DHCSR_C_HALT_Pos) /*!< CoreDebug DHCSR: C_HALT Mask */ - -#define CoreDebug_DHCSR_C_DEBUGEN_Pos 0U /*!< CoreDebug DHCSR: C_DEBUGEN Position */ -#define CoreDebug_DHCSR_C_DEBUGEN_Msk (1UL /*<< CoreDebug_DHCSR_C_DEBUGEN_Pos*/) /*!< CoreDebug DHCSR: C_DEBUGEN Mask */ - -/* Debug Core Register Selector Register Definitions */ -#define CoreDebug_DCRSR_REGWnR_Pos 16U /*!< CoreDebug DCRSR: REGWnR Position */ -#define CoreDebug_DCRSR_REGWnR_Msk (1UL << CoreDebug_DCRSR_REGWnR_Pos) /*!< CoreDebug DCRSR: REGWnR Mask */ - -#define CoreDebug_DCRSR_REGSEL_Pos 0U /*!< CoreDebug DCRSR: REGSEL Position */ -#define CoreDebug_DCRSR_REGSEL_Msk (0x1FUL /*<< CoreDebug_DCRSR_REGSEL_Pos*/) /*!< CoreDebug DCRSR: REGSEL Mask */ - -/* Debug Exception and Monitor Control Register Definitions */ -#define CoreDebug_DEMCR_TRCENA_Pos 24U /*!< CoreDebug DEMCR: TRCENA Position */ -#define CoreDebug_DEMCR_TRCENA_Msk (1UL << CoreDebug_DEMCR_TRCENA_Pos) /*!< CoreDebug DEMCR: TRCENA Mask */ - -#define CoreDebug_DEMCR_MON_REQ_Pos 19U /*!< CoreDebug DEMCR: MON_REQ Position */ -#define CoreDebug_DEMCR_MON_REQ_Msk (1UL << CoreDebug_DEMCR_MON_REQ_Pos) /*!< CoreDebug DEMCR: MON_REQ Mask */ - -#define CoreDebug_DEMCR_MON_STEP_Pos 18U /*!< CoreDebug DEMCR: MON_STEP Position */ -#define CoreDebug_DEMCR_MON_STEP_Msk (1UL << CoreDebug_DEMCR_MON_STEP_Pos) /*!< CoreDebug DEMCR: MON_STEP Mask */ - -#define CoreDebug_DEMCR_MON_PEND_Pos 17U /*!< CoreDebug DEMCR: MON_PEND Position */ -#define CoreDebug_DEMCR_MON_PEND_Msk (1UL << CoreDebug_DEMCR_MON_PEND_Pos) /*!< CoreDebug DEMCR: MON_PEND Mask */ - -#define CoreDebug_DEMCR_MON_EN_Pos 16U /*!< CoreDebug DEMCR: MON_EN Position */ -#define CoreDebug_DEMCR_MON_EN_Msk (1UL << CoreDebug_DEMCR_MON_EN_Pos) /*!< CoreDebug DEMCR: MON_EN Mask */ - -#define CoreDebug_DEMCR_VC_HARDERR_Pos 10U /*!< CoreDebug DEMCR: VC_HARDERR Position */ -#define CoreDebug_DEMCR_VC_HARDERR_Msk (1UL << CoreDebug_DEMCR_VC_HARDERR_Pos) /*!< CoreDebug DEMCR: VC_HARDERR Mask */ - -#define CoreDebug_DEMCR_VC_INTERR_Pos 9U /*!< CoreDebug DEMCR: VC_INTERR Position */ -#define CoreDebug_DEMCR_VC_INTERR_Msk (1UL << CoreDebug_DEMCR_VC_INTERR_Pos) /*!< CoreDebug DEMCR: VC_INTERR Mask */ - -#define CoreDebug_DEMCR_VC_BUSERR_Pos 8U /*!< CoreDebug DEMCR: VC_BUSERR Position */ -#define CoreDebug_DEMCR_VC_BUSERR_Msk (1UL << CoreDebug_DEMCR_VC_BUSERR_Pos) /*!< CoreDebug DEMCR: VC_BUSERR Mask */ - -#define CoreDebug_DEMCR_VC_STATERR_Pos 7U /*!< CoreDebug DEMCR: VC_STATERR Position */ -#define CoreDebug_DEMCR_VC_STATERR_Msk (1UL << CoreDebug_DEMCR_VC_STATERR_Pos) /*!< CoreDebug DEMCR: VC_STATERR Mask */ - -#define CoreDebug_DEMCR_VC_CHKERR_Pos 6U /*!< CoreDebug DEMCR: VC_CHKERR Position */ -#define CoreDebug_DEMCR_VC_CHKERR_Msk (1UL << CoreDebug_DEMCR_VC_CHKERR_Pos) /*!< CoreDebug DEMCR: VC_CHKERR Mask */ - -#define CoreDebug_DEMCR_VC_NOCPERR_Pos 5U /*!< CoreDebug DEMCR: VC_NOCPERR Position */ -#define CoreDebug_DEMCR_VC_NOCPERR_Msk (1UL << CoreDebug_DEMCR_VC_NOCPERR_Pos) /*!< CoreDebug DEMCR: VC_NOCPERR Mask */ - -#define CoreDebug_DEMCR_VC_MMERR_Pos 4U /*!< CoreDebug DEMCR: VC_MMERR Position */ -#define CoreDebug_DEMCR_VC_MMERR_Msk (1UL << CoreDebug_DEMCR_VC_MMERR_Pos) /*!< CoreDebug DEMCR: VC_MMERR Mask */ - -#define CoreDebug_DEMCR_VC_CORERESET_Pos 0U /*!< CoreDebug DEMCR: VC_CORERESET Position */ -#define CoreDebug_DEMCR_VC_CORERESET_Msk (1UL /*<< CoreDebug_DEMCR_VC_CORERESET_Pos*/) /*!< CoreDebug DEMCR: VC_CORERESET Mask */ - -/*@} end of group CMSIS_CoreDebug */ - - -/** - \ingroup CMSIS_core_register - \defgroup CMSIS_core_bitfield Core register bit field macros - \brief Macros for use with bit field definitions (xxx_Pos, xxx_Msk). - @{ - */ - -/** - \brief Mask and shift a bit field value for use in a register bit range. - \param[in] field Name of the register bit field. - \param[in] value Value of the bit field. This parameter is interpreted as an uint32_t type. - \return Masked and shifted value. -*/ -#define _VAL2FLD(field, value) (((uint32_t)(value) << field ## _Pos) & field ## _Msk) - -/** - \brief Mask and shift a register value to extract a bit filed value. - \param[in] field Name of the register bit field. - \param[in] value Value of register. This parameter is interpreted as an uint32_t type. - \return Masked and shifted bit field value. -*/ -#define _FLD2VAL(field, value) (((uint32_t)(value) & field ## _Msk) >> field ## _Pos) - -/*@} end of group CMSIS_core_bitfield */ - - -/** - \ingroup CMSIS_core_register - \defgroup CMSIS_core_base Core Definitions - \brief Definitions for base addresses, unions, and structures. - @{ - */ - -/* Memory mapping of Core Hardware */ -#define SCS_BASE (0xE000E000UL) /*!< System Control Space Base Address */ -#define ITM_BASE (0xE0000000UL) /*!< ITM Base Address */ -#define DWT_BASE (0xE0001000UL) /*!< DWT Base Address */ -#define TPI_BASE (0xE0040000UL) /*!< TPI Base Address */ -#define CoreDebug_BASE (0xE000EDF0UL) /*!< Core Debug Base Address */ -#define SysTick_BASE (SCS_BASE + 0x0010UL) /*!< SysTick Base Address */ -#define NVIC_BASE (SCS_BASE + 0x0100UL) /*!< NVIC Base Address */ -#define SCB_BASE (SCS_BASE + 0x0D00UL) /*!< System Control Block Base Address */ - -#define SCnSCB ((SCnSCB_Type *) SCS_BASE ) /*!< System control Register not in SCB */ -#define SCB ((SCB_Type *) SCB_BASE ) /*!< SCB configuration struct */ -#define SysTick ((SysTick_Type *) SysTick_BASE ) /*!< SysTick configuration struct */ -#define NVIC ((NVIC_Type *) NVIC_BASE ) /*!< NVIC configuration struct */ -#define ITM ((ITM_Type *) ITM_BASE ) /*!< ITM configuration struct */ -#define DWT ((DWT_Type *) DWT_BASE ) /*!< DWT configuration struct */ -#define TPI ((TPI_Type *) TPI_BASE ) /*!< TPI configuration struct */ -#define CoreDebug ((CoreDebug_Type *) CoreDebug_BASE) /*!< Core Debug configuration struct */ - -#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) - #define MPU_BASE (SCS_BASE + 0x0D90UL) /*!< Memory Protection Unit */ - #define MPU ((MPU_Type *) MPU_BASE ) /*!< Memory Protection Unit */ -#endif - -#define FPU_BASE (SCS_BASE + 0x0F30UL) /*!< Floating Point Unit */ -#define FPU ((FPU_Type *) FPU_BASE ) /*!< Floating Point Unit */ - -/*@} */ - - - -/******************************************************************************* - * Hardware Abstraction Layer - Core Function Interface contains: - - Core NVIC Functions - - Core SysTick Functions - - Core Debug Functions - - Core Register Access Functions - ******************************************************************************/ -/** - \defgroup CMSIS_Core_FunctionInterface Functions and Instructions Reference -*/ - - - -/* ########################## NVIC functions #################################### */ -/** - \ingroup CMSIS_Core_FunctionInterface - \defgroup CMSIS_Core_NVICFunctions NVIC Functions - \brief Functions that manage interrupts and exceptions via the NVIC. - @{ - */ - -#ifdef CMSIS_NVIC_VIRTUAL - #ifndef CMSIS_NVIC_VIRTUAL_HEADER_FILE - #define CMSIS_NVIC_VIRTUAL_HEADER_FILE "cmsis_nvic_virtual.h" - #endif - #include CMSIS_NVIC_VIRTUAL_HEADER_FILE -#else - #define NVIC_SetPriorityGrouping __NVIC_SetPriorityGrouping - #define NVIC_GetPriorityGrouping __NVIC_GetPriorityGrouping - #define NVIC_EnableIRQ __NVIC_EnableIRQ - #define NVIC_GetEnableIRQ __NVIC_GetEnableIRQ - #define NVIC_DisableIRQ __NVIC_DisableIRQ - #define NVIC_GetPendingIRQ __NVIC_GetPendingIRQ - #define NVIC_SetPendingIRQ __NVIC_SetPendingIRQ - #define NVIC_ClearPendingIRQ __NVIC_ClearPendingIRQ - #define NVIC_GetActive __NVIC_GetActive - #define NVIC_SetPriority __NVIC_SetPriority - #define NVIC_GetPriority __NVIC_GetPriority - #define NVIC_SystemReset __NVIC_SystemReset -#endif /* CMSIS_NVIC_VIRTUAL */ - -#ifdef CMSIS_VECTAB_VIRTUAL - #ifndef CMSIS_VECTAB_VIRTUAL_HEADER_FILE - #define CMSIS_VECTAB_VIRTUAL_HEADER_FILE "cmsis_vectab_virtual.h" - #endif - #include CMSIS_VECTAB_VIRTUAL_HEADER_FILE -#else - #define NVIC_SetVector __NVIC_SetVector - #define NVIC_GetVector __NVIC_GetVector -#endif /* (CMSIS_VECTAB_VIRTUAL) */ - -#define NVIC_USER_IRQ_OFFSET 16 - - - -/** - \brief Set Priority Grouping - \details Sets the priority grouping field using the required unlock sequence. - The parameter PriorityGroup is assigned to the field SCB->AIRCR [10:8] PRIGROUP field. - Only values from 0..7 are used. - In case of a conflict between priority grouping and available - priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set. - \param [in] PriorityGroup Priority grouping field. - */ -__STATIC_INLINE void __NVIC_SetPriorityGrouping(uint32_t PriorityGroup) -{ - uint32_t reg_value; - uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ - - reg_value = SCB->AIRCR; /* read old register configuration */ - reg_value &= ~((uint32_t)(SCB_AIRCR_VECTKEY_Msk | SCB_AIRCR_PRIGROUP_Msk)); /* clear bits to change */ - reg_value = (reg_value | - ((uint32_t)0x5FAUL << SCB_AIRCR_VECTKEY_Pos) | - (PriorityGroupTmp << SCB_AIRCR_PRIGROUP_Pos) ); /* Insert write key and priority group */ - SCB->AIRCR = reg_value; -} - - -/** - \brief Get Priority Grouping - \details Reads the priority grouping field from the NVIC Interrupt Controller. - \return Priority grouping field (SCB->AIRCR [10:8] PRIGROUP field). - */ -__STATIC_INLINE uint32_t __NVIC_GetPriorityGrouping(void) -{ - return ((uint32_t)((SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) >> SCB_AIRCR_PRIGROUP_Pos)); -} - - -/** - \brief Enable Interrupt - \details Enables a device specific interrupt in the NVIC interrupt controller. - \param [in] IRQn Device specific interrupt number. - \note IRQn must not be negative. - */ -__STATIC_INLINE void __NVIC_EnableIRQ(IRQn_Type IRQn) -{ - if ((int32_t)(IRQn) >= 0) - { - NVIC->ISER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); - } -} - - -/** - \brief Get Interrupt Enable status - \details Returns a device specific interrupt enable status from the NVIC interrupt controller. - \param [in] IRQn Device specific interrupt number. - \return 0 Interrupt is not enabled. - \return 1 Interrupt is enabled. - \note IRQn must not be negative. - */ -__STATIC_INLINE uint32_t __NVIC_GetEnableIRQ(IRQn_Type IRQn) -{ - if ((int32_t)(IRQn) >= 0) - { - return((uint32_t)(((NVIC->ISER[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); - } - else - { - return(0U); - } -} - - -/** - \brief Disable Interrupt - \details Disables a device specific interrupt in the NVIC interrupt controller. - \param [in] IRQn Device specific interrupt number. - \note IRQn must not be negative. - */ -__STATIC_INLINE void __NVIC_DisableIRQ(IRQn_Type IRQn) -{ - if ((int32_t)(IRQn) >= 0) - { - NVIC->ICER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); - __DSB(); - __ISB(); - } -} - - -/** - \brief Get Pending Interrupt - \details Reads the NVIC pending register and returns the pending bit for the specified device specific interrupt. - \param [in] IRQn Device specific interrupt number. - \return 0 Interrupt status is not pending. - \return 1 Interrupt status is pending. - \note IRQn must not be negative. - */ -__STATIC_INLINE uint32_t __NVIC_GetPendingIRQ(IRQn_Type IRQn) -{ - if ((int32_t)(IRQn) >= 0) - { - return((uint32_t)(((NVIC->ISPR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); - } - else - { - return(0U); - } -} - - -/** - \brief Set Pending Interrupt - \details Sets the pending bit of a device specific interrupt in the NVIC pending register. - \param [in] IRQn Device specific interrupt number. - \note IRQn must not be negative. - */ -__STATIC_INLINE void __NVIC_SetPendingIRQ(IRQn_Type IRQn) -{ - if ((int32_t)(IRQn) >= 0) - { - NVIC->ISPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); - } -} - - -/** - \brief Clear Pending Interrupt - \details Clears the pending bit of a device specific interrupt in the NVIC pending register. - \param [in] IRQn Device specific interrupt number. - \note IRQn must not be negative. - */ -__STATIC_INLINE void __NVIC_ClearPendingIRQ(IRQn_Type IRQn) -{ - if ((int32_t)(IRQn) >= 0) - { - NVIC->ICPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); - } -} - - -/** - \brief Get Active Interrupt - \details Reads the active register in the NVIC and returns the active bit for the device specific interrupt. - \param [in] IRQn Device specific interrupt number. - \return 0 Interrupt status is not active. - \return 1 Interrupt status is active. - \note IRQn must not be negative. - */ -__STATIC_INLINE uint32_t __NVIC_GetActive(IRQn_Type IRQn) -{ - if ((int32_t)(IRQn) >= 0) - { - return((uint32_t)(((NVIC->IABR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); - } - else - { - return(0U); - } -} - - -/** - \brief Set Interrupt Priority - \details Sets the priority of a device specific interrupt or a processor exception. - The interrupt number can be positive to specify a device specific interrupt, - or negative to specify a processor exception. - \param [in] IRQn Interrupt number. - \param [in] priority Priority to set. - \note The priority cannot be set for every processor exception. - */ -__STATIC_INLINE void __NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority) -{ - if ((int32_t)(IRQn) >= 0) - { - NVIC->IP[((uint32_t)IRQn)] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL); - } - else - { - SCB->SHP[(((uint32_t)IRQn) & 0xFUL)-4UL] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL); - } -} - - -/** - \brief Get Interrupt Priority - \details Reads the priority of a device specific interrupt or a processor exception. - The interrupt number can be positive to specify a device specific interrupt, - or negative to specify a processor exception. - \param [in] IRQn Interrupt number. - \return Interrupt Priority. - Value is aligned automatically to the implemented priority bits of the microcontroller. - */ -__STATIC_INLINE uint32_t __NVIC_GetPriority(IRQn_Type IRQn) -{ - - if ((int32_t)(IRQn) >= 0) - { - return(((uint32_t)NVIC->IP[((uint32_t)IRQn)] >> (8U - __NVIC_PRIO_BITS))); - } - else - { - return(((uint32_t)SCB->SHP[(((uint32_t)IRQn) & 0xFUL)-4UL] >> (8U - __NVIC_PRIO_BITS))); - } -} - - -/** - \brief Encode Priority - \details Encodes the priority for an interrupt with the given priority group, - preemptive priority value, and subpriority value. - In case of a conflict between priority grouping and available - priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set. - \param [in] PriorityGroup Used priority group. - \param [in] PreemptPriority Preemptive priority value (starting from 0). - \param [in] SubPriority Subpriority value (starting from 0). - \return Encoded priority. Value can be used in the function \ref NVIC_SetPriority(). - */ -__STATIC_INLINE uint32_t NVIC_EncodePriority (uint32_t PriorityGroup, uint32_t PreemptPriority, uint32_t SubPriority) -{ - uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ - uint32_t PreemptPriorityBits; - uint32_t SubPriorityBits; - - PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp); - SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS)); - - return ( - ((PreemptPriority & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL)) << SubPriorityBits) | - ((SubPriority & (uint32_t)((1UL << (SubPriorityBits )) - 1UL))) - ); -} - - -/** - \brief Decode Priority - \details Decodes an interrupt priority value with a given priority group to - preemptive priority value and subpriority value. - In case of a conflict between priority grouping and available - priority bits (__NVIC_PRIO_BITS) the smallest possible priority group is set. - \param [in] Priority Priority value, which can be retrieved with the function \ref NVIC_GetPriority(). - \param [in] PriorityGroup Used priority group. - \param [out] pPreemptPriority Preemptive priority value (starting from 0). - \param [out] pSubPriority Subpriority value (starting from 0). - */ -__STATIC_INLINE void NVIC_DecodePriority (uint32_t Priority, uint32_t PriorityGroup, uint32_t* const pPreemptPriority, uint32_t* const pSubPriority) -{ - uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ - uint32_t PreemptPriorityBits; - uint32_t SubPriorityBits; - - PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp); - SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS)); - - *pPreemptPriority = (Priority >> SubPriorityBits) & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL); - *pSubPriority = (Priority ) & (uint32_t)((1UL << (SubPriorityBits )) - 1UL); -} - - -/** - \brief Set Interrupt Vector - \details Sets an interrupt vector in SRAM based interrupt vector table. - The interrupt number can be positive to specify a device specific interrupt, - or negative to specify a processor exception. - VTOR must been relocated to SRAM before. - \param [in] IRQn Interrupt number - \param [in] vector Address of interrupt handler function - */ -__STATIC_INLINE void __NVIC_SetVector(IRQn_Type IRQn, uint32_t vector) -{ - uint32_t *vectors = (uint32_t *)SCB->VTOR; - vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET] = vector; -} - - -/** - \brief Get Interrupt Vector - \details Reads an interrupt vector from interrupt vector table. - The interrupt number can be positive to specify a device specific interrupt, - or negative to specify a processor exception. - \param [in] IRQn Interrupt number. - \return Address of interrupt handler function - */ -__STATIC_INLINE uint32_t __NVIC_GetVector(IRQn_Type IRQn) -{ - uint32_t *vectors = (uint32_t *)SCB->VTOR; - return vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET]; -} - - -/** - \brief System Reset - \details Initiates a system reset request to reset the MCU. - */ -__STATIC_INLINE void __NVIC_SystemReset(void) -{ - __DSB(); /* Ensure all outstanding memory accesses included - buffered write are completed before reset */ - SCB->AIRCR = (uint32_t)((0x5FAUL << SCB_AIRCR_VECTKEY_Pos) | - (SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) | - SCB_AIRCR_SYSRESETREQ_Msk ); /* Keep priority group unchanged */ - __DSB(); /* Ensure completion of memory access */ - - for(;;) /* wait until reset */ - { - __NOP(); - } -} - -/*@} end of CMSIS_Core_NVICFunctions */ - -/* ########################## MPU functions #################################### */ - -#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) - -#include "mpu_armv7.h" - -#endif - - -/* ########################## FPU functions #################################### */ -/** - \ingroup CMSIS_Core_FunctionInterface - \defgroup CMSIS_Core_FpuFunctions FPU Functions - \brief Function that provides FPU type. - @{ - */ - -/** - \brief get FPU type - \details returns the FPU type - \returns - - \b 0: No FPU - - \b 1: Single precision FPU - - \b 2: Double + Single precision FPU - */ -__STATIC_INLINE uint32_t SCB_GetFPUType(void) -{ - uint32_t mvfr0; - - mvfr0 = FPU->MVFR0; - if ((mvfr0 & (FPU_MVFR0_Single_precision_Msk | FPU_MVFR0_Double_precision_Msk)) == 0x020U) - { - return 1U; /* Single precision FPU */ - } - else - { - return 0U; /* No FPU */ - } -} - - -/*@} end of CMSIS_Core_FpuFunctions */ - - - -/* ################################## SysTick function ############################################ */ -/** - \ingroup CMSIS_Core_FunctionInterface - \defgroup CMSIS_Core_SysTickFunctions SysTick Functions - \brief Functions that configure the System. - @{ - */ - -#if defined (__Vendor_SysTickConfig) && (__Vendor_SysTickConfig == 0U) - -/** - \brief System Tick Configuration - \details Initializes the System Timer and its interrupt, and starts the System Tick Timer. - Counter is in free running mode to generate periodic interrupts. - \param [in] ticks Number of ticks between two interrupts. - \return 0 Function succeeded. - \return 1 Function failed. - \note When the variable __Vendor_SysTickConfig is set to 1, then the - function SysTick_Config is not included. In this case, the file device.h - must contain a vendor-specific implementation of this function. - */ -__STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks) -{ - if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk) - { - return (1UL); /* Reload value impossible */ - } - - SysTick->LOAD = (uint32_t)(ticks - 1UL); /* set reload register */ - NVIC_SetPriority (SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */ - SysTick->VAL = 0UL; /* Load the SysTick Counter Value */ - SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk | - SysTick_CTRL_TICKINT_Msk | - SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */ - return (0UL); /* Function successful */ -} - -#endif - -/*@} end of CMSIS_Core_SysTickFunctions */ - - - -/* ##################################### Debug In/Output function ########################################### */ -/** - \ingroup CMSIS_Core_FunctionInterface - \defgroup CMSIS_core_DebugFunctions ITM Functions - \brief Functions that access the ITM debug interface. - @{ - */ - -extern volatile int32_t ITM_RxBuffer; /*!< External variable to receive characters. */ -#define ITM_RXBUFFER_EMPTY ((int32_t)0x5AA55AA5U) /*!< Value identifying \ref ITM_RxBuffer is ready for next character. */ - - -/** - \brief ITM Send Character - \details Transmits a character via the ITM channel 0, and - \li Just returns when no debugger is connected that has booked the output. - \li Is blocking when a debugger is connected, but the previous character sent has not been transmitted. - \param [in] ch Character to transmit. - \returns Character to transmit. - */ -__STATIC_INLINE uint32_t ITM_SendChar (uint32_t ch) -{ - if (((ITM->TCR & ITM_TCR_ITMENA_Msk) != 0UL) && /* ITM enabled */ - ((ITM->TER & 1UL ) != 0UL) ) /* ITM Port #0 enabled */ - { - while (ITM->PORT[0U].u32 == 0UL) - { - __NOP(); - } - ITM->PORT[0U].u8 = (uint8_t)ch; - } - return (ch); -} - - -/** - \brief ITM Receive Character - \details Inputs a character via the external variable \ref ITM_RxBuffer. - \return Received character. - \return -1 No character pending. - */ -__STATIC_INLINE int32_t ITM_ReceiveChar (void) -{ - int32_t ch = -1; /* no character available */ - - if (ITM_RxBuffer != ITM_RXBUFFER_EMPTY) - { - ch = ITM_RxBuffer; - ITM_RxBuffer = ITM_RXBUFFER_EMPTY; /* ready for next character */ - } - - return (ch); -} - - -/** - \brief ITM Check Character - \details Checks whether a character is pending for reading in the variable \ref ITM_RxBuffer. - \return 0 No character available. - \return 1 Character available. - */ -__STATIC_INLINE int32_t ITM_CheckChar (void) -{ - - if (ITM_RxBuffer == ITM_RXBUFFER_EMPTY) - { - return (0); /* no character available */ - } - else - { - return (1); /* character available */ - } -} - -/*@} end of CMSIS_core_DebugFunctions */ - - - - -#ifdef __cplusplus -} -#endif - -#endif /* __CORE_CM4_H_DEPENDANT */ - -#endif /* __CMSIS_GENERIC */ diff --git a/bsp/essemi/es32f0271/libraries/CMSIS/Include/core_cm7.h b/bsp/essemi/es32f0271/libraries/CMSIS/Include/core_cm7.h deleted file mode 100644 index 1fe53bf012..0000000000 --- a/bsp/essemi/es32f0271/libraries/CMSIS/Include/core_cm7.h +++ /dev/null @@ -1,2660 +0,0 @@ -/**************************************************************************//** - * @file core_cm7.h - * @brief CMSIS Cortex-M7 Core Peripheral Access Layer Header File - * @version V5.0.5 - * @date 08. January 2018 - ******************************************************************************/ -/* - * Copyright (c) 2009-2017 ARM Limited. All rights reserved. - * - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed under the Apache License, Version 2.0 (the License); you may - * not use this file except in compliance with the License. - * You may obtain a copy of the License at - * - * www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an AS IS BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - */ - -#if defined ( __ICCARM__ ) - #pragma system_include /* treat file as system include file for MISRA check */ -#elif defined (__clang__) - #pragma clang system_header /* treat file as system include file */ -#endif - -#ifndef __CORE_CM7_H_GENERIC -#define __CORE_CM7_H_GENERIC - -#include - -#ifdef __cplusplus - extern "C" { -#endif - -/** - \page CMSIS_MISRA_Exceptions MISRA-C:2004 Compliance Exceptions - CMSIS violates the following MISRA-C:2004 rules: - - \li Required Rule 8.5, object/function definition in header file.
- Function definitions in header files are used to allow 'inlining'. - - \li Required Rule 18.4, declaration of union type or object of union type: '{...}'.
- Unions are used for effective representation of core registers. - - \li Advisory Rule 19.7, Function-like macro defined.
- Function-like macros are used to allow more efficient code. - */ - - -/******************************************************************************* - * CMSIS definitions - ******************************************************************************/ -/** - \ingroup Cortex_M7 - @{ - */ - -#include "cmsis_version.h" - -/* CMSIS CM7 definitions */ -#define __CM7_CMSIS_VERSION_MAIN (__CM_CMSIS_VERSION_MAIN) /*!< \deprecated [31:16] CMSIS HAL main version */ -#define __CM7_CMSIS_VERSION_SUB ( __CM_CMSIS_VERSION_SUB) /*!< \deprecated [15:0] CMSIS HAL sub version */ -#define __CM7_CMSIS_VERSION ((__CM7_CMSIS_VERSION_MAIN << 16U) | \ - __CM7_CMSIS_VERSION_SUB ) /*!< \deprecated CMSIS HAL version number */ - -#define __CORTEX_M (7U) /*!< Cortex-M Core */ - -/** __FPU_USED indicates whether an FPU is used or not. - For this, __FPU_PRESENT has to be checked prior to making use of FPU specific registers and functions. -*/ -#if defined ( __CC_ARM ) - #if defined __TARGET_FPU_VFP - #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) - #define __FPU_USED 1U - #else - #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" - #define __FPU_USED 0U - #endif - #else - #define __FPU_USED 0U - #endif - -#elif defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) - #if defined __ARM_PCS_VFP - #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) - #define __FPU_USED 1U - #else - #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" - #define __FPU_USED 0U - #endif - #else - #define __FPU_USED 0U - #endif - -#elif defined ( __GNUC__ ) - #if defined (__VFP_FP__) && !defined(__SOFTFP__) - #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) - #define __FPU_USED 1U - #else - #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" - #define __FPU_USED 0U - #endif - #else - #define __FPU_USED 0U - #endif - -#elif defined ( __ICCARM__ ) - #if defined __ARMVFP__ - #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) - #define __FPU_USED 1U - #else - #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" - #define __FPU_USED 0U - #endif - #else - #define __FPU_USED 0U - #endif - -#elif defined ( __TI_ARM__ ) - #if defined __TI_VFP_SUPPORT__ - #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) - #define __FPU_USED 1U - #else - #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" - #define __FPU_USED 0U - #endif - #else - #define __FPU_USED 0U - #endif - -#elif defined ( __TASKING__ ) - #if defined __FPU_VFP__ - #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) - #define __FPU_USED 1U - #else - #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" - #define __FPU_USED 0U - #endif - #else - #define __FPU_USED 0U - #endif - -#elif defined ( __CSMC__ ) - #if ( __CSMC__ & 0x400U) - #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) - #define __FPU_USED 1U - #else - #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" - #define __FPU_USED 0U - #endif - #else - #define __FPU_USED 0U - #endif - -#endif - -#include "cmsis_compiler.h" /* CMSIS compiler specific defines */ - - -#ifdef __cplusplus -} -#endif - -#endif /* __CORE_CM7_H_GENERIC */ - -#ifndef __CMSIS_GENERIC - -#ifndef __CORE_CM7_H_DEPENDANT -#define __CORE_CM7_H_DEPENDANT - -#ifdef __cplusplus - extern "C" { -#endif - -/* check device defines and use defaults */ -#if defined __CHECK_DEVICE_DEFINES - #ifndef __CM7_REV - #define __CM7_REV 0x0000U - #warning "__CM7_REV not defined in device header file; using default!" - #endif - - #ifndef __FPU_PRESENT - #define __FPU_PRESENT 0U - #warning "__FPU_PRESENT not defined in device header file; using default!" - #endif - - #ifndef __MPU_PRESENT - #define __MPU_PRESENT 0U - #warning "__MPU_PRESENT not defined in device header file; using default!" - #endif - - #ifndef __ICACHE_PRESENT - #define __ICACHE_PRESENT 0U - #warning "__ICACHE_PRESENT not defined in device header file; using default!" - #endif - - #ifndef __DCACHE_PRESENT - #define __DCACHE_PRESENT 0U - #warning "__DCACHE_PRESENT not defined in device header file; using default!" - #endif - - #ifndef __DTCM_PRESENT - #define __DTCM_PRESENT 0U - #warning "__DTCM_PRESENT not defined in device header file; using default!" - #endif - - #ifndef __NVIC_PRIO_BITS - #define __NVIC_PRIO_BITS 3U - #warning "__NVIC_PRIO_BITS not defined in device header file; using default!" - #endif - - #ifndef __Vendor_SysTickConfig - #define __Vendor_SysTickConfig 0U - #warning "__Vendor_SysTickConfig not defined in device header file; using default!" - #endif -#endif - -/* IO definitions (access restrictions to peripheral registers) */ -/** - \defgroup CMSIS_glob_defs CMSIS Global Defines - - IO Type Qualifiers are used - \li to specify the access to peripheral variables. - \li for automatic generation of peripheral register debug information. -*/ -#ifdef __cplusplus - #define __I volatile /*!< Defines 'read only' permissions */ -#else - #define __I volatile const /*!< Defines 'read only' permissions */ -#endif -#define __O volatile /*!< Defines 'write only' permissions */ -#define __IO volatile /*!< Defines 'read / write' permissions */ - -/* following defines should be used for structure members */ -#define __IM volatile const /*! Defines 'read only' structure member permissions */ -#define __OM volatile /*! Defines 'write only' structure member permissions */ -#define __IOM volatile /*! Defines 'read / write' structure member permissions */ - -/*@} end of group Cortex_M7 */ - - - -/******************************************************************************* - * Register Abstraction - Core Register contain: - - Core Register - - Core NVIC Register - - Core SCB Register - - Core SysTick Register - - Core Debug Register - - Core MPU Register - - Core FPU Register - ******************************************************************************/ -/** - \defgroup CMSIS_core_register Defines and Type Definitions - \brief Type definitions and defines for Cortex-M processor based devices. -*/ - -/** - \ingroup CMSIS_core_register - \defgroup CMSIS_CORE Status and Control Registers - \brief Core Register type definitions. - @{ - */ - -/** - \brief Union type to access the Application Program Status Register (APSR). - */ -typedef union -{ - struct - { - uint32_t _reserved0:16; /*!< bit: 0..15 Reserved */ - uint32_t GE:4; /*!< bit: 16..19 Greater than or Equal flags */ - uint32_t _reserved1:7; /*!< bit: 20..26 Reserved */ - uint32_t Q:1; /*!< bit: 27 Saturation condition flag */ - uint32_t V:1; /*!< bit: 28 Overflow condition code flag */ - uint32_t C:1; /*!< bit: 29 Carry condition code flag */ - uint32_t Z:1; /*!< bit: 30 Zero condition code flag */ - uint32_t N:1; /*!< bit: 31 Negative condition code flag */ - } b; /*!< Structure used for bit access */ - uint32_t w; /*!< Type used for word access */ -} APSR_Type; - -/* APSR Register Definitions */ -#define APSR_N_Pos 31U /*!< APSR: N Position */ -#define APSR_N_Msk (1UL << APSR_N_Pos) /*!< APSR: N Mask */ - -#define APSR_Z_Pos 30U /*!< APSR: Z Position */ -#define APSR_Z_Msk (1UL << APSR_Z_Pos) /*!< APSR: Z Mask */ - -#define APSR_C_Pos 29U /*!< APSR: C Position */ -#define APSR_C_Msk (1UL << APSR_C_Pos) /*!< APSR: C Mask */ - -#define APSR_V_Pos 28U /*!< APSR: V Position */ -#define APSR_V_Msk (1UL << APSR_V_Pos) /*!< APSR: V Mask */ - -#define APSR_Q_Pos 27U /*!< APSR: Q Position */ -#define APSR_Q_Msk (1UL << APSR_Q_Pos) /*!< APSR: Q Mask */ - -#define APSR_GE_Pos 16U /*!< APSR: GE Position */ -#define APSR_GE_Msk (0xFUL << APSR_GE_Pos) /*!< APSR: GE Mask */ - - -/** - \brief Union type to access the Interrupt Program Status Register (IPSR). - */ -typedef union -{ - struct - { - uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */ - uint32_t _reserved0:23; /*!< bit: 9..31 Reserved */ - } b; /*!< Structure used for bit access */ - uint32_t w; /*!< Type used for word access */ -} IPSR_Type; - -/* IPSR Register Definitions */ -#define IPSR_ISR_Pos 0U /*!< IPSR: ISR Position */ -#define IPSR_ISR_Msk (0x1FFUL /*<< IPSR_ISR_Pos*/) /*!< IPSR: ISR Mask */ - - -/** - \brief Union type to access the Special-Purpose Program Status Registers (xPSR). - */ -typedef union -{ - struct - { - uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */ - uint32_t _reserved0:1; /*!< bit: 9 Reserved */ - uint32_t ICI_IT_1:6; /*!< bit: 10..15 ICI/IT part 1 */ - uint32_t GE:4; /*!< bit: 16..19 Greater than or Equal flags */ - uint32_t _reserved1:4; /*!< bit: 20..23 Reserved */ - uint32_t T:1; /*!< bit: 24 Thumb bit */ - uint32_t ICI_IT_2:2; /*!< bit: 25..26 ICI/IT part 2 */ - uint32_t Q:1; /*!< bit: 27 Saturation condition flag */ - uint32_t V:1; /*!< bit: 28 Overflow condition code flag */ - uint32_t C:1; /*!< bit: 29 Carry condition code flag */ - uint32_t Z:1; /*!< bit: 30 Zero condition code flag */ - uint32_t N:1; /*!< bit: 31 Negative condition code flag */ - } b; /*!< Structure used for bit access */ - uint32_t w; /*!< Type used for word access */ -} xPSR_Type; - -/* xPSR Register Definitions */ -#define xPSR_N_Pos 31U /*!< xPSR: N Position */ -#define xPSR_N_Msk (1UL << xPSR_N_Pos) /*!< xPSR: N Mask */ - -#define xPSR_Z_Pos 30U /*!< xPSR: Z Position */ -#define xPSR_Z_Msk (1UL << xPSR_Z_Pos) /*!< xPSR: Z Mask */ - -#define xPSR_C_Pos 29U /*!< xPSR: C Position */ -#define xPSR_C_Msk (1UL << xPSR_C_Pos) /*!< xPSR: C Mask */ - -#define xPSR_V_Pos 28U /*!< xPSR: V Position */ -#define xPSR_V_Msk (1UL << xPSR_V_Pos) /*!< xPSR: V Mask */ - -#define xPSR_Q_Pos 27U /*!< xPSR: Q Position */ -#define xPSR_Q_Msk (1UL << xPSR_Q_Pos) /*!< xPSR: Q Mask */ - -#define xPSR_ICI_IT_2_Pos 25U /*!< xPSR: ICI/IT part 2 Position */ -#define xPSR_ICI_IT_2_Msk (3UL << xPSR_ICI_IT_2_Pos) /*!< xPSR: ICI/IT part 2 Mask */ - -#define xPSR_T_Pos 24U /*!< xPSR: T Position */ -#define xPSR_T_Msk (1UL << xPSR_T_Pos) /*!< xPSR: T Mask */ - -#define xPSR_GE_Pos 16U /*!< xPSR: GE Position */ -#define xPSR_GE_Msk (0xFUL << xPSR_GE_Pos) /*!< xPSR: GE Mask */ - -#define xPSR_ICI_IT_1_Pos 10U /*!< xPSR: ICI/IT part 1 Position */ -#define xPSR_ICI_IT_1_Msk (0x3FUL << xPSR_ICI_IT_1_Pos) /*!< xPSR: ICI/IT part 1 Mask */ - -#define xPSR_ISR_Pos 0U /*!< xPSR: ISR Position */ -#define xPSR_ISR_Msk (0x1FFUL /*<< xPSR_ISR_Pos*/) /*!< xPSR: ISR Mask */ - - -/** - \brief Union type to access the Control Registers (CONTROL). - */ -typedef union -{ - struct - { - uint32_t nPRIV:1; /*!< bit: 0 Execution privilege in Thread mode */ - uint32_t SPSEL:1; /*!< bit: 1 Stack to be used */ - uint32_t FPCA:1; /*!< bit: 2 FP extension active flag */ - uint32_t _reserved0:29; /*!< bit: 3..31 Reserved */ - } b; /*!< Structure used for bit access */ - uint32_t w; /*!< Type used for word access */ -} CONTROL_Type; - -/* CONTROL Register Definitions */ -#define CONTROL_FPCA_Pos 2U /*!< CONTROL: FPCA Position */ -#define CONTROL_FPCA_Msk (1UL << CONTROL_FPCA_Pos) /*!< CONTROL: FPCA Mask */ - -#define CONTROL_SPSEL_Pos 1U /*!< CONTROL: SPSEL Position */ -#define CONTROL_SPSEL_Msk (1UL << CONTROL_SPSEL_Pos) /*!< CONTROL: SPSEL Mask */ - -#define CONTROL_nPRIV_Pos 0U /*!< CONTROL: nPRIV Position */ -#define CONTROL_nPRIV_Msk (1UL /*<< CONTROL_nPRIV_Pos*/) /*!< CONTROL: nPRIV Mask */ - -/*@} end of group CMSIS_CORE */ - - -/** - \ingroup CMSIS_core_register - \defgroup CMSIS_NVIC Nested Vectored Interrupt Controller (NVIC) - \brief Type definitions for the NVIC Registers - @{ - */ - -/** - \brief Structure type to access the Nested Vectored Interrupt Controller (NVIC). - */ -typedef struct -{ - __IOM uint32_t ISER[8U]; /*!< Offset: 0x000 (R/W) Interrupt Set Enable Register */ - uint32_t RESERVED0[24U]; - __IOM uint32_t ICER[8U]; /*!< Offset: 0x080 (R/W) Interrupt Clear Enable Register */ - uint32_t RSERVED1[24U]; - __IOM uint32_t ISPR[8U]; /*!< Offset: 0x100 (R/W) Interrupt Set Pending Register */ - uint32_t RESERVED2[24U]; - __IOM uint32_t ICPR[8U]; /*!< Offset: 0x180 (R/W) Interrupt Clear Pending Register */ - uint32_t RESERVED3[24U]; - __IOM uint32_t IABR[8U]; /*!< Offset: 0x200 (R/W) Interrupt Active bit Register */ - uint32_t RESERVED4[56U]; - __IOM uint8_t IP[240U]; /*!< Offset: 0x300 (R/W) Interrupt Priority Register (8Bit wide) */ - uint32_t RESERVED5[644U]; - __OM uint32_t STIR; /*!< Offset: 0xE00 ( /W) Software Trigger Interrupt Register */ -} NVIC_Type; - -/* Software Triggered Interrupt Register Definitions */ -#define NVIC_STIR_INTID_Pos 0U /*!< STIR: INTLINESNUM Position */ -#define NVIC_STIR_INTID_Msk (0x1FFUL /*<< NVIC_STIR_INTID_Pos*/) /*!< STIR: INTLINESNUM Mask */ - -/*@} end of group CMSIS_NVIC */ - - -/** - \ingroup CMSIS_core_register - \defgroup CMSIS_SCB System Control Block (SCB) - \brief Type definitions for the System Control Block Registers - @{ - */ - -/** - \brief Structure type to access the System Control Block (SCB). - */ -typedef struct -{ - __IM uint32_t CPUID; /*!< Offset: 0x000 (R/ ) CPUID Base Register */ - __IOM uint32_t ICSR; /*!< Offset: 0x004 (R/W) Interrupt Control and State Register */ - __IOM uint32_t VTOR; /*!< Offset: 0x008 (R/W) Vector Table Offset Register */ - __IOM uint32_t AIRCR; /*!< Offset: 0x00C (R/W) Application Interrupt and Reset Control Register */ - __IOM uint32_t SCR; /*!< Offset: 0x010 (R/W) System Control Register */ - __IOM uint32_t CCR; /*!< Offset: 0x014 (R/W) Configuration Control Register */ - __IOM uint8_t SHPR[12U]; /*!< Offset: 0x018 (R/W) System Handlers Priority Registers (4-7, 8-11, 12-15) */ - __IOM uint32_t SHCSR; /*!< Offset: 0x024 (R/W) System Handler Control and State Register */ - __IOM uint32_t CFSR; /*!< Offset: 0x028 (R/W) Configurable Fault Status Register */ - __IOM uint32_t HFSR; /*!< Offset: 0x02C (R/W) HardFault Status Register */ - __IOM uint32_t DFSR; /*!< Offset: 0x030 (R/W) Debug Fault Status Register */ - __IOM uint32_t MMFAR; /*!< Offset: 0x034 (R/W) MemManage Fault Address Register */ - __IOM uint32_t BFAR; /*!< Offset: 0x038 (R/W) BusFault Address Register */ - __IOM uint32_t AFSR; /*!< Offset: 0x03C (R/W) Auxiliary Fault Status Register */ - __IM uint32_t ID_PFR[2U]; /*!< Offset: 0x040 (R/ ) Processor Feature Register */ - __IM uint32_t ID_DFR; /*!< Offset: 0x048 (R/ ) Debug Feature Register */ - __IM uint32_t ID_AFR; /*!< Offset: 0x04C (R/ ) Auxiliary Feature Register */ - __IM uint32_t ID_MFR[4U]; /*!< Offset: 0x050 (R/ ) Memory Model Feature Register */ - __IM uint32_t ID_ISAR[5U]; /*!< Offset: 0x060 (R/ ) Instruction Set Attributes Register */ - uint32_t RESERVED0[1U]; - __IM uint32_t CLIDR; /*!< Offset: 0x078 (R/ ) Cache Level ID register */ - __IM uint32_t CTR; /*!< Offset: 0x07C (R/ ) Cache Type register */ - __IM uint32_t CCSIDR; /*!< Offset: 0x080 (R/ ) Cache Size ID Register */ - __IOM uint32_t CSSELR; /*!< Offset: 0x084 (R/W) Cache Size Selection Register */ - __IOM uint32_t CPACR; /*!< Offset: 0x088 (R/W) Coprocessor Access Control Register */ - uint32_t RESERVED3[93U]; - __OM uint32_t STIR; /*!< Offset: 0x200 ( /W) Software Triggered Interrupt Register */ - uint32_t RESERVED4[15U]; - __IM uint32_t MVFR0; /*!< Offset: 0x240 (R/ ) Media and VFP Feature Register 0 */ - __IM uint32_t MVFR1; /*!< Offset: 0x244 (R/ ) Media and VFP Feature Register 1 */ - __IM uint32_t MVFR2; /*!< Offset: 0x248 (R/ ) Media and VFP Feature Register 2 */ - uint32_t RESERVED5[1U]; - __OM uint32_t ICIALLU; /*!< Offset: 0x250 ( /W) I-Cache Invalidate All to PoU */ - uint32_t RESERVED6[1U]; - __OM uint32_t ICIMVAU; /*!< Offset: 0x258 ( /W) I-Cache Invalidate by MVA to PoU */ - __OM uint32_t DCIMVAC; /*!< Offset: 0x25C ( /W) D-Cache Invalidate by MVA to PoC */ - __OM uint32_t DCISW; /*!< Offset: 0x260 ( /W) D-Cache Invalidate by Set-way */ - __OM uint32_t DCCMVAU; /*!< Offset: 0x264 ( /W) D-Cache Clean by MVA to PoU */ - __OM uint32_t DCCMVAC; /*!< Offset: 0x268 ( /W) D-Cache Clean by MVA to PoC */ - __OM uint32_t DCCSW; /*!< Offset: 0x26C ( /W) D-Cache Clean by Set-way */ - __OM uint32_t DCCIMVAC; /*!< Offset: 0x270 ( /W) D-Cache Clean and Invalidate by MVA to PoC */ - __OM uint32_t DCCISW; /*!< Offset: 0x274 ( /W) D-Cache Clean and Invalidate by Set-way */ - uint32_t RESERVED7[6U]; - __IOM uint32_t ITCMCR; /*!< Offset: 0x290 (R/W) Instruction Tightly-Coupled Memory Control Register */ - __IOM uint32_t DTCMCR; /*!< Offset: 0x294 (R/W) Data Tightly-Coupled Memory Control Registers */ - __IOM uint32_t AHBPCR; /*!< Offset: 0x298 (R/W) AHBP Control Register */ - __IOM uint32_t CACR; /*!< Offset: 0x29C (R/W) L1 Cache Control Register */ - __IOM uint32_t AHBSCR; /*!< Offset: 0x2A0 (R/W) AHB Slave Control Register */ - uint32_t RESERVED8[1U]; - __IOM uint32_t ABFSR; /*!< Offset: 0x2A8 (R/W) Auxiliary Bus Fault Status Register */ -} SCB_Type; - -/* SCB CPUID Register Definitions */ -#define SCB_CPUID_IMPLEMENTER_Pos 24U /*!< SCB CPUID: IMPLEMENTER Position */ -#define SCB_CPUID_IMPLEMENTER_Msk (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos) /*!< SCB CPUID: IMPLEMENTER Mask */ - -#define SCB_CPUID_VARIANT_Pos 20U /*!< SCB CPUID: VARIANT Position */ -#define SCB_CPUID_VARIANT_Msk (0xFUL << SCB_CPUID_VARIANT_Pos) /*!< SCB CPUID: VARIANT Mask */ - -#define SCB_CPUID_ARCHITECTURE_Pos 16U /*!< SCB CPUID: ARCHITECTURE Position */ -#define SCB_CPUID_ARCHITECTURE_Msk (0xFUL << SCB_CPUID_ARCHITECTURE_Pos) /*!< SCB CPUID: ARCHITECTURE Mask */ - -#define SCB_CPUID_PARTNO_Pos 4U /*!< SCB CPUID: PARTNO Position */ -#define SCB_CPUID_PARTNO_Msk (0xFFFUL << SCB_CPUID_PARTNO_Pos) /*!< SCB CPUID: PARTNO Mask */ - -#define SCB_CPUID_REVISION_Pos 0U /*!< SCB CPUID: REVISION Position */ -#define SCB_CPUID_REVISION_Msk (0xFUL /*<< SCB_CPUID_REVISION_Pos*/) /*!< SCB CPUID: REVISION Mask */ - -/* SCB Interrupt Control State Register Definitions */ -#define SCB_ICSR_NMIPENDSET_Pos 31U /*!< SCB ICSR: NMIPENDSET Position */ -#define SCB_ICSR_NMIPENDSET_Msk (1UL << SCB_ICSR_NMIPENDSET_Pos) /*!< SCB ICSR: NMIPENDSET Mask */ - -#define SCB_ICSR_PENDSVSET_Pos 28U /*!< SCB ICSR: PENDSVSET Position */ -#define SCB_ICSR_PENDSVSET_Msk (1UL << SCB_ICSR_PENDSVSET_Pos) /*!< SCB ICSR: PENDSVSET Mask */ - -#define SCB_ICSR_PENDSVCLR_Pos 27U /*!< SCB ICSR: PENDSVCLR Position */ -#define SCB_ICSR_PENDSVCLR_Msk (1UL << SCB_ICSR_PENDSVCLR_Pos) /*!< SCB ICSR: PENDSVCLR Mask */ - -#define SCB_ICSR_PENDSTSET_Pos 26U /*!< SCB ICSR: PENDSTSET Position */ -#define SCB_ICSR_PENDSTSET_Msk (1UL << SCB_ICSR_PENDSTSET_Pos) /*!< SCB ICSR: PENDSTSET Mask */ - -#define SCB_ICSR_PENDSTCLR_Pos 25U /*!< SCB ICSR: PENDSTCLR Position */ -#define SCB_ICSR_PENDSTCLR_Msk (1UL << SCB_ICSR_PENDSTCLR_Pos) /*!< SCB ICSR: PENDSTCLR Mask */ - -#define SCB_ICSR_ISRPREEMPT_Pos 23U /*!< SCB ICSR: ISRPREEMPT Position */ -#define SCB_ICSR_ISRPREEMPT_Msk (1UL << SCB_ICSR_ISRPREEMPT_Pos) /*!< SCB ICSR: ISRPREEMPT Mask */ - -#define SCB_ICSR_ISRPENDING_Pos 22U /*!< SCB ICSR: ISRPENDING Position */ -#define SCB_ICSR_ISRPENDING_Msk (1UL << SCB_ICSR_ISRPENDING_Pos) /*!< SCB ICSR: ISRPENDING Mask */ - -#define SCB_ICSR_VECTPENDING_Pos 12U /*!< SCB ICSR: VECTPENDING Position */ -#define SCB_ICSR_VECTPENDING_Msk (0x1FFUL << SCB_ICSR_VECTPENDING_Pos) /*!< SCB ICSR: VECTPENDING Mask */ - -#define SCB_ICSR_RETTOBASE_Pos 11U /*!< SCB ICSR: RETTOBASE Position */ -#define SCB_ICSR_RETTOBASE_Msk (1UL << SCB_ICSR_RETTOBASE_Pos) /*!< SCB ICSR: RETTOBASE Mask */ - -#define SCB_ICSR_VECTACTIVE_Pos 0U /*!< SCB ICSR: VECTACTIVE Position */ -#define SCB_ICSR_VECTACTIVE_Msk (0x1FFUL /*<< SCB_ICSR_VECTACTIVE_Pos*/) /*!< SCB ICSR: VECTACTIVE Mask */ - -/* SCB Vector Table Offset Register Definitions */ -#define SCB_VTOR_TBLOFF_Pos 7U /*!< SCB VTOR: TBLOFF Position */ -#define SCB_VTOR_TBLOFF_Msk (0x1FFFFFFUL << SCB_VTOR_TBLOFF_Pos) /*!< SCB VTOR: TBLOFF Mask */ - -/* SCB Application Interrupt and Reset Control Register Definitions */ -#define SCB_AIRCR_VECTKEY_Pos 16U /*!< SCB AIRCR: VECTKEY Position */ -#define SCB_AIRCR_VECTKEY_Msk (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos) /*!< SCB AIRCR: VECTKEY Mask */ - -#define SCB_AIRCR_VECTKEYSTAT_Pos 16U /*!< SCB AIRCR: VECTKEYSTAT Position */ -#define SCB_AIRCR_VECTKEYSTAT_Msk (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos) /*!< SCB AIRCR: VECTKEYSTAT Mask */ - -#define SCB_AIRCR_ENDIANESS_Pos 15U /*!< SCB AIRCR: ENDIANESS Position */ -#define SCB_AIRCR_ENDIANESS_Msk (1UL << SCB_AIRCR_ENDIANESS_Pos) /*!< SCB AIRCR: ENDIANESS Mask */ - -#define SCB_AIRCR_PRIGROUP_Pos 8U /*!< SCB AIRCR: PRIGROUP Position */ -#define SCB_AIRCR_PRIGROUP_Msk (7UL << SCB_AIRCR_PRIGROUP_Pos) /*!< SCB AIRCR: PRIGROUP Mask */ - -#define SCB_AIRCR_SYSRESETREQ_Pos 2U /*!< SCB AIRCR: SYSRESETREQ Position */ -#define SCB_AIRCR_SYSRESETREQ_Msk (1UL << SCB_AIRCR_SYSRESETREQ_Pos) /*!< SCB AIRCR: SYSRESETREQ Mask */ - -#define SCB_AIRCR_VECTCLRACTIVE_Pos 1U /*!< SCB AIRCR: VECTCLRACTIVE Position */ -#define SCB_AIRCR_VECTCLRACTIVE_Msk (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos) /*!< SCB AIRCR: VECTCLRACTIVE Mask */ - -#define SCB_AIRCR_VECTRESET_Pos 0U /*!< SCB AIRCR: VECTRESET Position */ -#define SCB_AIRCR_VECTRESET_Msk (1UL /*<< SCB_AIRCR_VECTRESET_Pos*/) /*!< SCB AIRCR: VECTRESET Mask */ - -/* SCB System Control Register Definitions */ -#define SCB_SCR_SEVONPEND_Pos 4U /*!< SCB SCR: SEVONPEND Position */ -#define SCB_SCR_SEVONPEND_Msk (1UL << SCB_SCR_SEVONPEND_Pos) /*!< SCB SCR: SEVONPEND Mask */ - -#define SCB_SCR_SLEEPDEEP_Pos 2U /*!< SCB SCR: SLEEPDEEP Position */ -#define SCB_SCR_SLEEPDEEP_Msk (1UL << SCB_SCR_SLEEPDEEP_Pos) /*!< SCB SCR: SLEEPDEEP Mask */ - -#define SCB_SCR_SLEEPONEXIT_Pos 1U /*!< SCB SCR: SLEEPONEXIT Position */ -#define SCB_SCR_SLEEPONEXIT_Msk (1UL << SCB_SCR_SLEEPONEXIT_Pos) /*!< SCB SCR: SLEEPONEXIT Mask */ - -/* SCB Configuration Control Register Definitions */ -#define SCB_CCR_BP_Pos 18U /*!< SCB CCR: Branch prediction enable bit Position */ -#define SCB_CCR_BP_Msk (1UL << SCB_CCR_BP_Pos) /*!< SCB CCR: Branch prediction enable bit Mask */ - -#define SCB_CCR_IC_Pos 17U /*!< SCB CCR: Instruction cache enable bit Position */ -#define SCB_CCR_IC_Msk (1UL << SCB_CCR_IC_Pos) /*!< SCB CCR: Instruction cache enable bit Mask */ - -#define SCB_CCR_DC_Pos 16U /*!< SCB CCR: Cache enable bit Position */ -#define SCB_CCR_DC_Msk (1UL << SCB_CCR_DC_Pos) /*!< SCB CCR: Cache enable bit Mask */ - -#define SCB_CCR_STKALIGN_Pos 9U /*!< SCB CCR: STKALIGN Position */ -#define SCB_CCR_STKALIGN_Msk (1UL << SCB_CCR_STKALIGN_Pos) /*!< SCB CCR: STKALIGN Mask */ - -#define SCB_CCR_BFHFNMIGN_Pos 8U /*!< SCB CCR: BFHFNMIGN Position */ -#define SCB_CCR_BFHFNMIGN_Msk (1UL << SCB_CCR_BFHFNMIGN_Pos) /*!< SCB CCR: BFHFNMIGN Mask */ - -#define SCB_CCR_DIV_0_TRP_Pos 4U /*!< SCB CCR: DIV_0_TRP Position */ -#define SCB_CCR_DIV_0_TRP_Msk (1UL << SCB_CCR_DIV_0_TRP_Pos) /*!< SCB CCR: DIV_0_TRP Mask */ - -#define SCB_CCR_UNALIGN_TRP_Pos 3U /*!< SCB CCR: UNALIGN_TRP Position */ -#define SCB_CCR_UNALIGN_TRP_Msk (1UL << SCB_CCR_UNALIGN_TRP_Pos) /*!< SCB CCR: UNALIGN_TRP Mask */ - -#define SCB_CCR_USERSETMPEND_Pos 1U /*!< SCB CCR: USERSETMPEND Position */ -#define SCB_CCR_USERSETMPEND_Msk (1UL << SCB_CCR_USERSETMPEND_Pos) /*!< SCB CCR: USERSETMPEND Mask */ - -#define SCB_CCR_NONBASETHRDENA_Pos 0U /*!< SCB CCR: NONBASETHRDENA Position */ -#define SCB_CCR_NONBASETHRDENA_Msk (1UL /*<< SCB_CCR_NONBASETHRDENA_Pos*/) /*!< SCB CCR: NONBASETHRDENA Mask */ - -/* SCB System Handler Control and State Register Definitions */ -#define SCB_SHCSR_USGFAULTENA_Pos 18U /*!< SCB SHCSR: USGFAULTENA Position */ -#define SCB_SHCSR_USGFAULTENA_Msk (1UL << SCB_SHCSR_USGFAULTENA_Pos) /*!< SCB SHCSR: USGFAULTENA Mask */ - -#define SCB_SHCSR_BUSFAULTENA_Pos 17U /*!< SCB SHCSR: BUSFAULTENA Position */ -#define SCB_SHCSR_BUSFAULTENA_Msk (1UL << SCB_SHCSR_BUSFAULTENA_Pos) /*!< SCB SHCSR: BUSFAULTENA Mask */ - -#define SCB_SHCSR_MEMFAULTENA_Pos 16U /*!< SCB SHCSR: MEMFAULTENA Position */ -#define SCB_SHCSR_MEMFAULTENA_Msk (1UL << SCB_SHCSR_MEMFAULTENA_Pos) /*!< SCB SHCSR: MEMFAULTENA Mask */ - -#define SCB_SHCSR_SVCALLPENDED_Pos 15U /*!< SCB SHCSR: SVCALLPENDED Position */ -#define SCB_SHCSR_SVCALLPENDED_Msk (1UL << SCB_SHCSR_SVCALLPENDED_Pos) /*!< SCB SHCSR: SVCALLPENDED Mask */ - -#define SCB_SHCSR_BUSFAULTPENDED_Pos 14U /*!< SCB SHCSR: BUSFAULTPENDED Position */ -#define SCB_SHCSR_BUSFAULTPENDED_Msk (1UL << SCB_SHCSR_BUSFAULTPENDED_Pos) /*!< SCB SHCSR: BUSFAULTPENDED Mask */ - -#define SCB_SHCSR_MEMFAULTPENDED_Pos 13U /*!< SCB SHCSR: MEMFAULTPENDED Position */ -#define SCB_SHCSR_MEMFAULTPENDED_Msk (1UL << SCB_SHCSR_MEMFAULTPENDED_Pos) /*!< SCB SHCSR: MEMFAULTPENDED Mask */ - -#define SCB_SHCSR_USGFAULTPENDED_Pos 12U /*!< SCB SHCSR: USGFAULTPENDED Position */ -#define SCB_SHCSR_USGFAULTPENDED_Msk (1UL << SCB_SHCSR_USGFAULTPENDED_Pos) /*!< SCB SHCSR: USGFAULTPENDED Mask */ - -#define SCB_SHCSR_SYSTICKACT_Pos 11U /*!< SCB SHCSR: SYSTICKACT Position */ -#define SCB_SHCSR_SYSTICKACT_Msk (1UL << SCB_SHCSR_SYSTICKACT_Pos) /*!< SCB SHCSR: SYSTICKACT Mask */ - -#define SCB_SHCSR_PENDSVACT_Pos 10U /*!< SCB SHCSR: PENDSVACT Position */ -#define SCB_SHCSR_PENDSVACT_Msk (1UL << SCB_SHCSR_PENDSVACT_Pos) /*!< SCB SHCSR: PENDSVACT Mask */ - -#define SCB_SHCSR_MONITORACT_Pos 8U /*!< SCB SHCSR: MONITORACT Position */ -#define SCB_SHCSR_MONITORACT_Msk (1UL << SCB_SHCSR_MONITORACT_Pos) /*!< SCB SHCSR: MONITORACT Mask */ - -#define SCB_SHCSR_SVCALLACT_Pos 7U /*!< SCB SHCSR: SVCALLACT Position */ -#define SCB_SHCSR_SVCALLACT_Msk (1UL << SCB_SHCSR_SVCALLACT_Pos) /*!< SCB SHCSR: SVCALLACT Mask */ - -#define SCB_SHCSR_USGFAULTACT_Pos 3U /*!< SCB SHCSR: USGFAULTACT Position */ -#define SCB_SHCSR_USGFAULTACT_Msk (1UL << SCB_SHCSR_USGFAULTACT_Pos) /*!< SCB SHCSR: USGFAULTACT Mask */ - -#define SCB_SHCSR_BUSFAULTACT_Pos 1U /*!< SCB SHCSR: BUSFAULTACT Position */ -#define SCB_SHCSR_BUSFAULTACT_Msk (1UL << SCB_SHCSR_BUSFAULTACT_Pos) /*!< SCB SHCSR: BUSFAULTACT Mask */ - -#define SCB_SHCSR_MEMFAULTACT_Pos 0U /*!< SCB SHCSR: MEMFAULTACT Position */ -#define SCB_SHCSR_MEMFAULTACT_Msk (1UL /*<< SCB_SHCSR_MEMFAULTACT_Pos*/) /*!< SCB SHCSR: MEMFAULTACT Mask */ - -/* SCB Configurable Fault Status Register Definitions */ -#define SCB_CFSR_USGFAULTSR_Pos 16U /*!< SCB CFSR: Usage Fault Status Register Position */ -#define SCB_CFSR_USGFAULTSR_Msk (0xFFFFUL << SCB_CFSR_USGFAULTSR_Pos) /*!< SCB CFSR: Usage Fault Status Register Mask */ - -#define SCB_CFSR_BUSFAULTSR_Pos 8U /*!< SCB CFSR: Bus Fault Status Register Position */ -#define SCB_CFSR_BUSFAULTSR_Msk (0xFFUL << SCB_CFSR_BUSFAULTSR_Pos) /*!< SCB CFSR: Bus Fault Status Register Mask */ - -#define SCB_CFSR_MEMFAULTSR_Pos 0U /*!< SCB CFSR: Memory Manage Fault Status Register Position */ -#define SCB_CFSR_MEMFAULTSR_Msk (0xFFUL /*<< SCB_CFSR_MEMFAULTSR_Pos*/) /*!< SCB CFSR: Memory Manage Fault Status Register Mask */ - -/* MemManage Fault Status Register (part of SCB Configurable Fault Status Register) */ -#define SCB_CFSR_MMARVALID_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 7U) /*!< SCB CFSR (MMFSR): MMARVALID Position */ -#define SCB_CFSR_MMARVALID_Msk (1UL << SCB_CFSR_MMARVALID_Pos) /*!< SCB CFSR (MMFSR): MMARVALID Mask */ - -#define SCB_CFSR_MLSPERR_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 5U) /*!< SCB CFSR (MMFSR): MLSPERR Position */ -#define SCB_CFSR_MLSPERR_Msk (1UL << SCB_CFSR_MLSPERR_Pos) /*!< SCB CFSR (MMFSR): MLSPERR Mask */ - -#define SCB_CFSR_MSTKERR_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 4U) /*!< SCB CFSR (MMFSR): MSTKERR Position */ -#define SCB_CFSR_MSTKERR_Msk (1UL << SCB_CFSR_MSTKERR_Pos) /*!< SCB CFSR (MMFSR): MSTKERR Mask */ - -#define SCB_CFSR_MUNSTKERR_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 3U) /*!< SCB CFSR (MMFSR): MUNSTKERR Position */ -#define SCB_CFSR_MUNSTKERR_Msk (1UL << SCB_CFSR_MUNSTKERR_Pos) /*!< SCB CFSR (MMFSR): MUNSTKERR Mask */ - -#define SCB_CFSR_DACCVIOL_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 1U) /*!< SCB CFSR (MMFSR): DACCVIOL Position */ -#define SCB_CFSR_DACCVIOL_Msk (1UL << SCB_CFSR_DACCVIOL_Pos) /*!< SCB CFSR (MMFSR): DACCVIOL Mask */ - -#define SCB_CFSR_IACCVIOL_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 0U) /*!< SCB CFSR (MMFSR): IACCVIOL Position */ -#define SCB_CFSR_IACCVIOL_Msk (1UL /*<< SCB_CFSR_IACCVIOL_Pos*/) /*!< SCB CFSR (MMFSR): IACCVIOL Mask */ - -/* BusFault Status Register (part of SCB Configurable Fault Status Register) */ -#define SCB_CFSR_BFARVALID_Pos (SCB_CFSR_BUSFAULTSR_Pos + 7U) /*!< SCB CFSR (BFSR): BFARVALID Position */ -#define SCB_CFSR_BFARVALID_Msk (1UL << SCB_CFSR_BFARVALID_Pos) /*!< SCB CFSR (BFSR): BFARVALID Mask */ - -#define SCB_CFSR_LSPERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 5U) /*!< SCB CFSR (BFSR): LSPERR Position */ -#define SCB_CFSR_LSPERR_Msk (1UL << SCB_CFSR_LSPERR_Pos) /*!< SCB CFSR (BFSR): LSPERR Mask */ - -#define SCB_CFSR_STKERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 4U) /*!< SCB CFSR (BFSR): STKERR Position */ -#define SCB_CFSR_STKERR_Msk (1UL << SCB_CFSR_STKERR_Pos) /*!< SCB CFSR (BFSR): STKERR Mask */ - -#define SCB_CFSR_UNSTKERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 3U) /*!< SCB CFSR (BFSR): UNSTKERR Position */ -#define SCB_CFSR_UNSTKERR_Msk (1UL << SCB_CFSR_UNSTKERR_Pos) /*!< SCB CFSR (BFSR): UNSTKERR Mask */ - -#define SCB_CFSR_IMPRECISERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 2U) /*!< SCB CFSR (BFSR): IMPRECISERR Position */ -#define SCB_CFSR_IMPRECISERR_Msk (1UL << SCB_CFSR_IMPRECISERR_Pos) /*!< SCB CFSR (BFSR): IMPRECISERR Mask */ - -#define SCB_CFSR_PRECISERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 1U) /*!< SCB CFSR (BFSR): PRECISERR Position */ -#define SCB_CFSR_PRECISERR_Msk (1UL << SCB_CFSR_PRECISERR_Pos) /*!< SCB CFSR (BFSR): PRECISERR Mask */ - -#define SCB_CFSR_IBUSERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 0U) /*!< SCB CFSR (BFSR): IBUSERR Position */ -#define SCB_CFSR_IBUSERR_Msk (1UL << SCB_CFSR_IBUSERR_Pos) /*!< SCB CFSR (BFSR): IBUSERR Mask */ - -/* UsageFault Status Register (part of SCB Configurable Fault Status Register) */ -#define SCB_CFSR_DIVBYZERO_Pos (SCB_CFSR_USGFAULTSR_Pos + 9U) /*!< SCB CFSR (UFSR): DIVBYZERO Position */ -#define SCB_CFSR_DIVBYZERO_Msk (1UL << SCB_CFSR_DIVBYZERO_Pos) /*!< SCB CFSR (UFSR): DIVBYZERO Mask */ - -#define SCB_CFSR_UNALIGNED_Pos (SCB_CFSR_USGFAULTSR_Pos + 8U) /*!< SCB CFSR (UFSR): UNALIGNED Position */ -#define SCB_CFSR_UNALIGNED_Msk (1UL << SCB_CFSR_UNALIGNED_Pos) /*!< SCB CFSR (UFSR): UNALIGNED Mask */ - -#define SCB_CFSR_NOCP_Pos (SCB_CFSR_USGFAULTSR_Pos + 3U) /*!< SCB CFSR (UFSR): NOCP Position */ -#define SCB_CFSR_NOCP_Msk (1UL << SCB_CFSR_NOCP_Pos) /*!< SCB CFSR (UFSR): NOCP Mask */ - -#define SCB_CFSR_INVPC_Pos (SCB_CFSR_USGFAULTSR_Pos + 2U) /*!< SCB CFSR (UFSR): INVPC Position */ -#define SCB_CFSR_INVPC_Msk (1UL << SCB_CFSR_INVPC_Pos) /*!< SCB CFSR (UFSR): INVPC Mask */ - -#define SCB_CFSR_INVSTATE_Pos (SCB_CFSR_USGFAULTSR_Pos + 1U) /*!< SCB CFSR (UFSR): INVSTATE Position */ -#define SCB_CFSR_INVSTATE_Msk (1UL << SCB_CFSR_INVSTATE_Pos) /*!< SCB CFSR (UFSR): INVSTATE Mask */ - -#define SCB_CFSR_UNDEFINSTR_Pos (SCB_CFSR_USGFAULTSR_Pos + 0U) /*!< SCB CFSR (UFSR): UNDEFINSTR Position */ -#define SCB_CFSR_UNDEFINSTR_Msk (1UL << SCB_CFSR_UNDEFINSTR_Pos) /*!< SCB CFSR (UFSR): UNDEFINSTR Mask */ - -/* SCB Hard Fault Status Register Definitions */ -#define SCB_HFSR_DEBUGEVT_Pos 31U /*!< SCB HFSR: DEBUGEVT Position */ -#define SCB_HFSR_DEBUGEVT_Msk (1UL << SCB_HFSR_DEBUGEVT_Pos) /*!< SCB HFSR: DEBUGEVT Mask */ - -#define SCB_HFSR_FORCED_Pos 30U /*!< SCB HFSR: FORCED Position */ -#define SCB_HFSR_FORCED_Msk (1UL << SCB_HFSR_FORCED_Pos) /*!< SCB HFSR: FORCED Mask */ - -#define SCB_HFSR_VECTTBL_Pos 1U /*!< SCB HFSR: VECTTBL Position */ -#define SCB_HFSR_VECTTBL_Msk (1UL << SCB_HFSR_VECTTBL_Pos) /*!< SCB HFSR: VECTTBL Mask */ - -/* SCB Debug Fault Status Register Definitions */ -#define SCB_DFSR_EXTERNAL_Pos 4U /*!< SCB DFSR: EXTERNAL Position */ -#define SCB_DFSR_EXTERNAL_Msk (1UL << SCB_DFSR_EXTERNAL_Pos) /*!< SCB DFSR: EXTERNAL Mask */ - -#define SCB_DFSR_VCATCH_Pos 3U /*!< SCB DFSR: VCATCH Position */ -#define SCB_DFSR_VCATCH_Msk (1UL << SCB_DFSR_VCATCH_Pos) /*!< SCB DFSR: VCATCH Mask */ - -#define SCB_DFSR_DWTTRAP_Pos 2U /*!< SCB DFSR: DWTTRAP Position */ -#define SCB_DFSR_DWTTRAP_Msk (1UL << SCB_DFSR_DWTTRAP_Pos) /*!< SCB DFSR: DWTTRAP Mask */ - -#define SCB_DFSR_BKPT_Pos 1U /*!< SCB DFSR: BKPT Position */ -#define SCB_DFSR_BKPT_Msk (1UL << SCB_DFSR_BKPT_Pos) /*!< SCB DFSR: BKPT Mask */ - -#define SCB_DFSR_HALTED_Pos 0U /*!< SCB DFSR: HALTED Position */ -#define SCB_DFSR_HALTED_Msk (1UL /*<< SCB_DFSR_HALTED_Pos*/) /*!< SCB DFSR: HALTED Mask */ - -/* SCB Cache Level ID Register Definitions */ -#define SCB_CLIDR_LOUU_Pos 27U /*!< SCB CLIDR: LoUU Position */ -#define SCB_CLIDR_LOUU_Msk (7UL << SCB_CLIDR_LOUU_Pos) /*!< SCB CLIDR: LoUU Mask */ - -#define SCB_CLIDR_LOC_Pos 24U /*!< SCB CLIDR: LoC Position */ -#define SCB_CLIDR_LOC_Msk (7UL << SCB_CLIDR_LOC_Pos) /*!< SCB CLIDR: LoC Mask */ - -/* SCB Cache Type Register Definitions */ -#define SCB_CTR_FORMAT_Pos 29U /*!< SCB CTR: Format Position */ -#define SCB_CTR_FORMAT_Msk (7UL << SCB_CTR_FORMAT_Pos) /*!< SCB CTR: Format Mask */ - -#define SCB_CTR_CWG_Pos 24U /*!< SCB CTR: CWG Position */ -#define SCB_CTR_CWG_Msk (0xFUL << SCB_CTR_CWG_Pos) /*!< SCB CTR: CWG Mask */ - -#define SCB_CTR_ERG_Pos 20U /*!< SCB CTR: ERG Position */ -#define SCB_CTR_ERG_Msk (0xFUL << SCB_CTR_ERG_Pos) /*!< SCB CTR: ERG Mask */ - -#define SCB_CTR_DMINLINE_Pos 16U /*!< SCB CTR: DminLine Position */ -#define SCB_CTR_DMINLINE_Msk (0xFUL << SCB_CTR_DMINLINE_Pos) /*!< SCB CTR: DminLine Mask */ - -#define SCB_CTR_IMINLINE_Pos 0U /*!< SCB CTR: ImInLine Position */ -#define SCB_CTR_IMINLINE_Msk (0xFUL /*<< SCB_CTR_IMINLINE_Pos*/) /*!< SCB CTR: ImInLine Mask */ - -/* SCB Cache Size ID Register Definitions */ -#define SCB_CCSIDR_WT_Pos 31U /*!< SCB CCSIDR: WT Position */ -#define SCB_CCSIDR_WT_Msk (1UL << SCB_CCSIDR_WT_Pos) /*!< SCB CCSIDR: WT Mask */ - -#define SCB_CCSIDR_WB_Pos 30U /*!< SCB CCSIDR: WB Position */ -#define SCB_CCSIDR_WB_Msk (1UL << SCB_CCSIDR_WB_Pos) /*!< SCB CCSIDR: WB Mask */ - -#define SCB_CCSIDR_RA_Pos 29U /*!< SCB CCSIDR: RA Position */ -#define SCB_CCSIDR_RA_Msk (1UL << SCB_CCSIDR_RA_Pos) /*!< SCB CCSIDR: RA Mask */ - -#define SCB_CCSIDR_WA_Pos 28U /*!< SCB CCSIDR: WA Position */ -#define SCB_CCSIDR_WA_Msk (1UL << SCB_CCSIDR_WA_Pos) /*!< SCB CCSIDR: WA Mask */ - -#define SCB_CCSIDR_NUMSETS_Pos 13U /*!< SCB CCSIDR: NumSets Position */ -#define SCB_CCSIDR_NUMSETS_Msk (0x7FFFUL << SCB_CCSIDR_NUMSETS_Pos) /*!< SCB CCSIDR: NumSets Mask */ - -#define SCB_CCSIDR_ASSOCIATIVITY_Pos 3U /*!< SCB CCSIDR: Associativity Position */ -#define SCB_CCSIDR_ASSOCIATIVITY_Msk (0x3FFUL << SCB_CCSIDR_ASSOCIATIVITY_Pos) /*!< SCB CCSIDR: Associativity Mask */ - -#define SCB_CCSIDR_LINESIZE_Pos 0U /*!< SCB CCSIDR: LineSize Position */ -#define SCB_CCSIDR_LINESIZE_Msk (7UL /*<< SCB_CCSIDR_LINESIZE_Pos*/) /*!< SCB CCSIDR: LineSize Mask */ - -/* SCB Cache Size Selection Register Definitions */ -#define SCB_CSSELR_LEVEL_Pos 1U /*!< SCB CSSELR: Level Position */ -#define SCB_CSSELR_LEVEL_Msk (7UL << SCB_CSSELR_LEVEL_Pos) /*!< SCB CSSELR: Level Mask */ - -#define SCB_CSSELR_IND_Pos 0U /*!< SCB CSSELR: InD Position */ -#define SCB_CSSELR_IND_Msk (1UL /*<< SCB_CSSELR_IND_Pos*/) /*!< SCB CSSELR: InD Mask */ - -/* SCB Software Triggered Interrupt Register Definitions */ -#define SCB_STIR_INTID_Pos 0U /*!< SCB STIR: INTID Position */ -#define SCB_STIR_INTID_Msk (0x1FFUL /*<< SCB_STIR_INTID_Pos*/) /*!< SCB STIR: INTID Mask */ - -/* SCB D-Cache Invalidate by Set-way Register Definitions */ -#define SCB_DCISW_WAY_Pos 30U /*!< SCB DCISW: Way Position */ -#define SCB_DCISW_WAY_Msk (3UL << SCB_DCISW_WAY_Pos) /*!< SCB DCISW: Way Mask */ - -#define SCB_DCISW_SET_Pos 5U /*!< SCB DCISW: Set Position */ -#define SCB_DCISW_SET_Msk (0x1FFUL << SCB_DCISW_SET_Pos) /*!< SCB DCISW: Set Mask */ - -/* SCB D-Cache Clean by Set-way Register Definitions */ -#define SCB_DCCSW_WAY_Pos 30U /*!< SCB DCCSW: Way Position */ -#define SCB_DCCSW_WAY_Msk (3UL << SCB_DCCSW_WAY_Pos) /*!< SCB DCCSW: Way Mask */ - -#define SCB_DCCSW_SET_Pos 5U /*!< SCB DCCSW: Set Position */ -#define SCB_DCCSW_SET_Msk (0x1FFUL << SCB_DCCSW_SET_Pos) /*!< SCB DCCSW: Set Mask */ - -/* SCB D-Cache Clean and Invalidate by Set-way Register Definitions */ -#define SCB_DCCISW_WAY_Pos 30U /*!< SCB DCCISW: Way Position */ -#define SCB_DCCISW_WAY_Msk (3UL << SCB_DCCISW_WAY_Pos) /*!< SCB DCCISW: Way Mask */ - -#define SCB_DCCISW_SET_Pos 5U /*!< SCB DCCISW: Set Position */ -#define SCB_DCCISW_SET_Msk (0x1FFUL << SCB_DCCISW_SET_Pos) /*!< SCB DCCISW: Set Mask */ - -/* Instruction Tightly-Coupled Memory Control Register Definitions */ -#define SCB_ITCMCR_SZ_Pos 3U /*!< SCB ITCMCR: SZ Position */ -#define SCB_ITCMCR_SZ_Msk (0xFUL << SCB_ITCMCR_SZ_Pos) /*!< SCB ITCMCR: SZ Mask */ - -#define SCB_ITCMCR_RETEN_Pos 2U /*!< SCB ITCMCR: RETEN Position */ -#define SCB_ITCMCR_RETEN_Msk (1UL << SCB_ITCMCR_RETEN_Pos) /*!< SCB ITCMCR: RETEN Mask */ - -#define SCB_ITCMCR_RMW_Pos 1U /*!< SCB ITCMCR: RMW Position */ -#define SCB_ITCMCR_RMW_Msk (1UL << SCB_ITCMCR_RMW_Pos) /*!< SCB ITCMCR: RMW Mask */ - -#define SCB_ITCMCR_EN_Pos 0U /*!< SCB ITCMCR: EN Position */ -#define SCB_ITCMCR_EN_Msk (1UL /*<< SCB_ITCMCR_EN_Pos*/) /*!< SCB ITCMCR: EN Mask */ - -/* Data Tightly-Coupled Memory Control Register Definitions */ -#define SCB_DTCMCR_SZ_Pos 3U /*!< SCB DTCMCR: SZ Position */ -#define SCB_DTCMCR_SZ_Msk (0xFUL << SCB_DTCMCR_SZ_Pos) /*!< SCB DTCMCR: SZ Mask */ - -#define SCB_DTCMCR_RETEN_Pos 2U /*!< SCB DTCMCR: RETEN Position */ -#define SCB_DTCMCR_RETEN_Msk (1UL << SCB_DTCMCR_RETEN_Pos) /*!< SCB DTCMCR: RETEN Mask */ - -#define SCB_DTCMCR_RMW_Pos 1U /*!< SCB DTCMCR: RMW Position */ -#define SCB_DTCMCR_RMW_Msk (1UL << SCB_DTCMCR_RMW_Pos) /*!< SCB DTCMCR: RMW Mask */ - -#define SCB_DTCMCR_EN_Pos 0U /*!< SCB DTCMCR: EN Position */ -#define SCB_DTCMCR_EN_Msk (1UL /*<< SCB_DTCMCR_EN_Pos*/) /*!< SCB DTCMCR: EN Mask */ - -/* AHBP Control Register Definitions */ -#define SCB_AHBPCR_SZ_Pos 1U /*!< SCB AHBPCR: SZ Position */ -#define SCB_AHBPCR_SZ_Msk (7UL << SCB_AHBPCR_SZ_Pos) /*!< SCB AHBPCR: SZ Mask */ - -#define SCB_AHBPCR_EN_Pos 0U /*!< SCB AHBPCR: EN Position */ -#define SCB_AHBPCR_EN_Msk (1UL /*<< SCB_AHBPCR_EN_Pos*/) /*!< SCB AHBPCR: EN Mask */ - -/* L1 Cache Control Register Definitions */ -#define SCB_CACR_FORCEWT_Pos 2U /*!< SCB CACR: FORCEWT Position */ -#define SCB_CACR_FORCEWT_Msk (1UL << SCB_CACR_FORCEWT_Pos) /*!< SCB CACR: FORCEWT Mask */ - -#define SCB_CACR_ECCEN_Pos 1U /*!< SCB CACR: ECCEN Position */ -#define SCB_CACR_ECCEN_Msk (1UL << SCB_CACR_ECCEN_Pos) /*!< SCB CACR: ECCEN Mask */ - -#define SCB_CACR_SIWT_Pos 0U /*!< SCB CACR: SIWT Position */ -#define SCB_CACR_SIWT_Msk (1UL /*<< SCB_CACR_SIWT_Pos*/) /*!< SCB CACR: SIWT Mask */ - -/* AHBS Control Register Definitions */ -#define SCB_AHBSCR_INITCOUNT_Pos 11U /*!< SCB AHBSCR: INITCOUNT Position */ -#define SCB_AHBSCR_INITCOUNT_Msk (0x1FUL << SCB_AHBPCR_INITCOUNT_Pos) /*!< SCB AHBSCR: INITCOUNT Mask */ - -#define SCB_AHBSCR_TPRI_Pos 2U /*!< SCB AHBSCR: TPRI Position */ -#define SCB_AHBSCR_TPRI_Msk (0x1FFUL << SCB_AHBPCR_TPRI_Pos) /*!< SCB AHBSCR: TPRI Mask */ - -#define SCB_AHBSCR_CTL_Pos 0U /*!< SCB AHBSCR: CTL Position*/ -#define SCB_AHBSCR_CTL_Msk (3UL /*<< SCB_AHBPCR_CTL_Pos*/) /*!< SCB AHBSCR: CTL Mask */ - -/* Auxiliary Bus Fault Status Register Definitions */ -#define SCB_ABFSR_AXIMTYPE_Pos 8U /*!< SCB ABFSR: AXIMTYPE Position*/ -#define SCB_ABFSR_AXIMTYPE_Msk (3UL << SCB_ABFSR_AXIMTYPE_Pos) /*!< SCB ABFSR: AXIMTYPE Mask */ - -#define SCB_ABFSR_EPPB_Pos 4U /*!< SCB ABFSR: EPPB Position*/ -#define SCB_ABFSR_EPPB_Msk (1UL << SCB_ABFSR_EPPB_Pos) /*!< SCB ABFSR: EPPB Mask */ - -#define SCB_ABFSR_AXIM_Pos 3U /*!< SCB ABFSR: AXIM Position*/ -#define SCB_ABFSR_AXIM_Msk (1UL << SCB_ABFSR_AXIM_Pos) /*!< SCB ABFSR: AXIM Mask */ - -#define SCB_ABFSR_AHBP_Pos 2U /*!< SCB ABFSR: AHBP Position*/ -#define SCB_ABFSR_AHBP_Msk (1UL << SCB_ABFSR_AHBP_Pos) /*!< SCB ABFSR: AHBP Mask */ - -#define SCB_ABFSR_DTCM_Pos 1U /*!< SCB ABFSR: DTCM Position*/ -#define SCB_ABFSR_DTCM_Msk (1UL << SCB_ABFSR_DTCM_Pos) /*!< SCB ABFSR: DTCM Mask */ - -#define SCB_ABFSR_ITCM_Pos 0U /*!< SCB ABFSR: ITCM Position*/ -#define SCB_ABFSR_ITCM_Msk (1UL /*<< SCB_ABFSR_ITCM_Pos*/) /*!< SCB ABFSR: ITCM Mask */ - -/*@} end of group CMSIS_SCB */ - - -/** - \ingroup CMSIS_core_register - \defgroup CMSIS_SCnSCB System Controls not in SCB (SCnSCB) - \brief Type definitions for the System Control and ID Register not in the SCB - @{ - */ - -/** - \brief Structure type to access the System Control and ID Register not in the SCB. - */ -typedef struct -{ - uint32_t RESERVED0[1U]; - __IM uint32_t ICTR; /*!< Offset: 0x004 (R/ ) Interrupt Controller Type Register */ - __IOM uint32_t ACTLR; /*!< Offset: 0x008 (R/W) Auxiliary Control Register */ -} SCnSCB_Type; - -/* Interrupt Controller Type Register Definitions */ -#define SCnSCB_ICTR_INTLINESNUM_Pos 0U /*!< ICTR: INTLINESNUM Position */ -#define SCnSCB_ICTR_INTLINESNUM_Msk (0xFUL /*<< SCnSCB_ICTR_INTLINESNUM_Pos*/) /*!< ICTR: INTLINESNUM Mask */ - -/* Auxiliary Control Register Definitions */ -#define SCnSCB_ACTLR_DISITMATBFLUSH_Pos 12U /*!< ACTLR: DISITMATBFLUSH Position */ -#define SCnSCB_ACTLR_DISITMATBFLUSH_Msk (1UL << SCnSCB_ACTLR_DISITMATBFLUSH_Pos) /*!< ACTLR: DISITMATBFLUSH Mask */ - -#define SCnSCB_ACTLR_DISRAMODE_Pos 11U /*!< ACTLR: DISRAMODE Position */ -#define SCnSCB_ACTLR_DISRAMODE_Msk (1UL << SCnSCB_ACTLR_DISRAMODE_Pos) /*!< ACTLR: DISRAMODE Mask */ - -#define SCnSCB_ACTLR_FPEXCODIS_Pos 10U /*!< ACTLR: FPEXCODIS Position */ -#define SCnSCB_ACTLR_FPEXCODIS_Msk (1UL << SCnSCB_ACTLR_FPEXCODIS_Pos) /*!< ACTLR: FPEXCODIS Mask */ - -#define SCnSCB_ACTLR_DISFOLD_Pos 2U /*!< ACTLR: DISFOLD Position */ -#define SCnSCB_ACTLR_DISFOLD_Msk (1UL << SCnSCB_ACTLR_DISFOLD_Pos) /*!< ACTLR: DISFOLD Mask */ - -#define SCnSCB_ACTLR_DISMCYCINT_Pos 0U /*!< ACTLR: DISMCYCINT Position */ -#define SCnSCB_ACTLR_DISMCYCINT_Msk (1UL /*<< SCnSCB_ACTLR_DISMCYCINT_Pos*/) /*!< ACTLR: DISMCYCINT Mask */ - -/*@} end of group CMSIS_SCnotSCB */ - - -/** - \ingroup CMSIS_core_register - \defgroup CMSIS_SysTick System Tick Timer (SysTick) - \brief Type definitions for the System Timer Registers. - @{ - */ - -/** - \brief Structure type to access the System Timer (SysTick). - */ -typedef struct -{ - __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) SysTick Control and Status Register */ - __IOM uint32_t LOAD; /*!< Offset: 0x004 (R/W) SysTick Reload Value Register */ - __IOM uint32_t VAL; /*!< Offset: 0x008 (R/W) SysTick Current Value Register */ - __IM uint32_t CALIB; /*!< Offset: 0x00C (R/ ) SysTick Calibration Register */ -} SysTick_Type; - -/* SysTick Control / Status Register Definitions */ -#define SysTick_CTRL_COUNTFLAG_Pos 16U /*!< SysTick CTRL: COUNTFLAG Position */ -#define SysTick_CTRL_COUNTFLAG_Msk (1UL << SysTick_CTRL_COUNTFLAG_Pos) /*!< SysTick CTRL: COUNTFLAG Mask */ - -#define SysTick_CTRL_CLKSOURCE_Pos 2U /*!< SysTick CTRL: CLKSOURCE Position */ -#define SysTick_CTRL_CLKSOURCE_Msk (1UL << SysTick_CTRL_CLKSOURCE_Pos) /*!< SysTick CTRL: CLKSOURCE Mask */ - -#define SysTick_CTRL_TICKINT_Pos 1U /*!< SysTick CTRL: TICKINT Position */ -#define SysTick_CTRL_TICKINT_Msk (1UL << SysTick_CTRL_TICKINT_Pos) /*!< SysTick CTRL: TICKINT Mask */ - -#define SysTick_CTRL_ENABLE_Pos 0U /*!< SysTick CTRL: ENABLE Position */ -#define SysTick_CTRL_ENABLE_Msk (1UL /*<< SysTick_CTRL_ENABLE_Pos*/) /*!< SysTick CTRL: ENABLE Mask */ - -/* SysTick Reload Register Definitions */ -#define SysTick_LOAD_RELOAD_Pos 0U /*!< SysTick LOAD: RELOAD Position */ -#define SysTick_LOAD_RELOAD_Msk (0xFFFFFFUL /*<< SysTick_LOAD_RELOAD_Pos*/) /*!< SysTick LOAD: RELOAD Mask */ - -/* SysTick Current Register Definitions */ -#define SysTick_VAL_CURRENT_Pos 0U /*!< SysTick VAL: CURRENT Position */ -#define SysTick_VAL_CURRENT_Msk (0xFFFFFFUL /*<< SysTick_VAL_CURRENT_Pos*/) /*!< SysTick VAL: CURRENT Mask */ - -/* SysTick Calibration Register Definitions */ -#define SysTick_CALIB_NOREF_Pos 31U /*!< SysTick CALIB: NOREF Position */ -#define SysTick_CALIB_NOREF_Msk (1UL << SysTick_CALIB_NOREF_Pos) /*!< SysTick CALIB: NOREF Mask */ - -#define SysTick_CALIB_SKEW_Pos 30U /*!< SysTick CALIB: SKEW Position */ -#define SysTick_CALIB_SKEW_Msk (1UL << SysTick_CALIB_SKEW_Pos) /*!< SysTick CALIB: SKEW Mask */ - -#define SysTick_CALIB_TENMS_Pos 0U /*!< SysTick CALIB: TENMS Position */ -#define SysTick_CALIB_TENMS_Msk (0xFFFFFFUL /*<< SysTick_CALIB_TENMS_Pos*/) /*!< SysTick CALIB: TENMS Mask */ - -/*@} end of group CMSIS_SysTick */ - - -/** - \ingroup CMSIS_core_register - \defgroup CMSIS_ITM Instrumentation Trace Macrocell (ITM) - \brief Type definitions for the Instrumentation Trace Macrocell (ITM) - @{ - */ - -/** - \brief Structure type to access the Instrumentation Trace Macrocell Register (ITM). - */ -typedef struct -{ - __OM union - { - __OM uint8_t u8; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 8-bit */ - __OM uint16_t u16; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 16-bit */ - __OM uint32_t u32; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 32-bit */ - } PORT [32U]; /*!< Offset: 0x000 ( /W) ITM Stimulus Port Registers */ - uint32_t RESERVED0[864U]; - __IOM uint32_t TER; /*!< Offset: 0xE00 (R/W) ITM Trace Enable Register */ - uint32_t RESERVED1[15U]; - __IOM uint32_t TPR; /*!< Offset: 0xE40 (R/W) ITM Trace Privilege Register */ - uint32_t RESERVED2[15U]; - __IOM uint32_t TCR; /*!< Offset: 0xE80 (R/W) ITM Trace Control Register */ - uint32_t RESERVED3[29U]; - __OM uint32_t IWR; /*!< Offset: 0xEF8 ( /W) ITM Integration Write Register */ - __IM uint32_t IRR; /*!< Offset: 0xEFC (R/ ) ITM Integration Read Register */ - __IOM uint32_t IMCR; /*!< Offset: 0xF00 (R/W) ITM Integration Mode Control Register */ - uint32_t RESERVED4[43U]; - __OM uint32_t LAR; /*!< Offset: 0xFB0 ( /W) ITM Lock Access Register */ - __IM uint32_t LSR; /*!< Offset: 0xFB4 (R/ ) ITM Lock Status Register */ - uint32_t RESERVED5[6U]; - __IM uint32_t PID4; /*!< Offset: 0xFD0 (R/ ) ITM Peripheral Identification Register #4 */ - __IM uint32_t PID5; /*!< Offset: 0xFD4 (R/ ) ITM Peripheral Identification Register #5 */ - __IM uint32_t PID6; /*!< Offset: 0xFD8 (R/ ) ITM Peripheral Identification Register #6 */ - __IM uint32_t PID7; /*!< Offset: 0xFDC (R/ ) ITM Peripheral Identification Register #7 */ - __IM uint32_t PID0; /*!< Offset: 0xFE0 (R/ ) ITM Peripheral Identification Register #0 */ - __IM uint32_t PID1; /*!< Offset: 0xFE4 (R/ ) ITM Peripheral Identification Register #1 */ - __IM uint32_t PID2; /*!< Offset: 0xFE8 (R/ ) ITM Peripheral Identification Register #2 */ - __IM uint32_t PID3; /*!< Offset: 0xFEC (R/ ) ITM Peripheral Identification Register #3 */ - __IM uint32_t CID0; /*!< Offset: 0xFF0 (R/ ) ITM Component Identification Register #0 */ - __IM uint32_t CID1; /*!< Offset: 0xFF4 (R/ ) ITM Component Identification Register #1 */ - __IM uint32_t CID2; /*!< Offset: 0xFF8 (R/ ) ITM Component Identification Register #2 */ - __IM uint32_t CID3; /*!< Offset: 0xFFC (R/ ) ITM Component Identification Register #3 */ -} ITM_Type; - -/* ITM Trace Privilege Register Definitions */ -#define ITM_TPR_PRIVMASK_Pos 0U /*!< ITM TPR: PRIVMASK Position */ -#define ITM_TPR_PRIVMASK_Msk (0xFFFFFFFFUL /*<< ITM_TPR_PRIVMASK_Pos*/) /*!< ITM TPR: PRIVMASK Mask */ - -/* ITM Trace Control Register Definitions */ -#define ITM_TCR_BUSY_Pos 23U /*!< ITM TCR: BUSY Position */ -#define ITM_TCR_BUSY_Msk (1UL << ITM_TCR_BUSY_Pos) /*!< ITM TCR: BUSY Mask */ - -#define ITM_TCR_TraceBusID_Pos 16U /*!< ITM TCR: ATBID Position */ -#define ITM_TCR_TraceBusID_Msk (0x7FUL << ITM_TCR_TraceBusID_Pos) /*!< ITM TCR: ATBID Mask */ - -#define ITM_TCR_GTSFREQ_Pos 10U /*!< ITM TCR: Global timestamp frequency Position */ -#define ITM_TCR_GTSFREQ_Msk (3UL << ITM_TCR_GTSFREQ_Pos) /*!< ITM TCR: Global timestamp frequency Mask */ - -#define ITM_TCR_TSPrescale_Pos 8U /*!< ITM TCR: TSPrescale Position */ -#define ITM_TCR_TSPrescale_Msk (3UL << ITM_TCR_TSPrescale_Pos) /*!< ITM TCR: TSPrescale Mask */ - -#define ITM_TCR_SWOENA_Pos 4U /*!< ITM TCR: SWOENA Position */ -#define ITM_TCR_SWOENA_Msk (1UL << ITM_TCR_SWOENA_Pos) /*!< ITM TCR: SWOENA Mask */ - -#define ITM_TCR_DWTENA_Pos 3U /*!< ITM TCR: DWTENA Position */ -#define ITM_TCR_DWTENA_Msk (1UL << ITM_TCR_DWTENA_Pos) /*!< ITM TCR: DWTENA Mask */ - -#define ITM_TCR_SYNCENA_Pos 2U /*!< ITM TCR: SYNCENA Position */ -#define ITM_TCR_SYNCENA_Msk (1UL << ITM_TCR_SYNCENA_Pos) /*!< ITM TCR: SYNCENA Mask */ - -#define ITM_TCR_TSENA_Pos 1U /*!< ITM TCR: TSENA Position */ -#define ITM_TCR_TSENA_Msk (1UL << ITM_TCR_TSENA_Pos) /*!< ITM TCR: TSENA Mask */ - -#define ITM_TCR_ITMENA_Pos 0U /*!< ITM TCR: ITM Enable bit Position */ -#define ITM_TCR_ITMENA_Msk (1UL /*<< ITM_TCR_ITMENA_Pos*/) /*!< ITM TCR: ITM Enable bit Mask */ - -/* ITM Integration Write Register Definitions */ -#define ITM_IWR_ATVALIDM_Pos 0U /*!< ITM IWR: ATVALIDM Position */ -#define ITM_IWR_ATVALIDM_Msk (1UL /*<< ITM_IWR_ATVALIDM_Pos*/) /*!< ITM IWR: ATVALIDM Mask */ - -/* ITM Integration Read Register Definitions */ -#define ITM_IRR_ATREADYM_Pos 0U /*!< ITM IRR: ATREADYM Position */ -#define ITM_IRR_ATREADYM_Msk (1UL /*<< ITM_IRR_ATREADYM_Pos*/) /*!< ITM IRR: ATREADYM Mask */ - -/* ITM Integration Mode Control Register Definitions */ -#define ITM_IMCR_INTEGRATION_Pos 0U /*!< ITM IMCR: INTEGRATION Position */ -#define ITM_IMCR_INTEGRATION_Msk (1UL /*<< ITM_IMCR_INTEGRATION_Pos*/) /*!< ITM IMCR: INTEGRATION Mask */ - -/* ITM Lock Status Register Definitions */ -#define ITM_LSR_ByteAcc_Pos 2U /*!< ITM LSR: ByteAcc Position */ -#define ITM_LSR_ByteAcc_Msk (1UL << ITM_LSR_ByteAcc_Pos) /*!< ITM LSR: ByteAcc Mask */ - -#define ITM_LSR_Access_Pos 1U /*!< ITM LSR: Access Position */ -#define ITM_LSR_Access_Msk (1UL << ITM_LSR_Access_Pos) /*!< ITM LSR: Access Mask */ - -#define ITM_LSR_Present_Pos 0U /*!< ITM LSR: Present Position */ -#define ITM_LSR_Present_Msk (1UL /*<< ITM_LSR_Present_Pos*/) /*!< ITM LSR: Present Mask */ - -/*@}*/ /* end of group CMSIS_ITM */ - - -/** - \ingroup CMSIS_core_register - \defgroup CMSIS_DWT Data Watchpoint and Trace (DWT) - \brief Type definitions for the Data Watchpoint and Trace (DWT) - @{ - */ - -/** - \brief Structure type to access the Data Watchpoint and Trace Register (DWT). - */ -typedef struct -{ - __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) Control Register */ - __IOM uint32_t CYCCNT; /*!< Offset: 0x004 (R/W) Cycle Count Register */ - __IOM uint32_t CPICNT; /*!< Offset: 0x008 (R/W) CPI Count Register */ - __IOM uint32_t EXCCNT; /*!< Offset: 0x00C (R/W) Exception Overhead Count Register */ - __IOM uint32_t SLEEPCNT; /*!< Offset: 0x010 (R/W) Sleep Count Register */ - __IOM uint32_t LSUCNT; /*!< Offset: 0x014 (R/W) LSU Count Register */ - __IOM uint32_t FOLDCNT; /*!< Offset: 0x018 (R/W) Folded-instruction Count Register */ - __IM uint32_t PCSR; /*!< Offset: 0x01C (R/ ) Program Counter Sample Register */ - __IOM uint32_t COMP0; /*!< Offset: 0x020 (R/W) Comparator Register 0 */ - __IOM uint32_t MASK0; /*!< Offset: 0x024 (R/W) Mask Register 0 */ - __IOM uint32_t FUNCTION0; /*!< Offset: 0x028 (R/W) Function Register 0 */ - uint32_t RESERVED0[1U]; - __IOM uint32_t COMP1; /*!< Offset: 0x030 (R/W) Comparator Register 1 */ - __IOM uint32_t MASK1; /*!< Offset: 0x034 (R/W) Mask Register 1 */ - __IOM uint32_t FUNCTION1; /*!< Offset: 0x038 (R/W) Function Register 1 */ - uint32_t RESERVED1[1U]; - __IOM uint32_t COMP2; /*!< Offset: 0x040 (R/W) Comparator Register 2 */ - __IOM uint32_t MASK2; /*!< Offset: 0x044 (R/W) Mask Register 2 */ - __IOM uint32_t FUNCTION2; /*!< Offset: 0x048 (R/W) Function Register 2 */ - uint32_t RESERVED2[1U]; - __IOM uint32_t COMP3; /*!< Offset: 0x050 (R/W) Comparator Register 3 */ - __IOM uint32_t MASK3; /*!< Offset: 0x054 (R/W) Mask Register 3 */ - __IOM uint32_t FUNCTION3; /*!< Offset: 0x058 (R/W) Function Register 3 */ - uint32_t RESERVED3[981U]; - __OM uint32_t LAR; /*!< Offset: 0xFB0 ( W) Lock Access Register */ - __IM uint32_t LSR; /*!< Offset: 0xFB4 (R ) Lock Status Register */ -} DWT_Type; - -/* DWT Control Register Definitions */ -#define DWT_CTRL_NUMCOMP_Pos 28U /*!< DWT CTRL: NUMCOMP Position */ -#define DWT_CTRL_NUMCOMP_Msk (0xFUL << DWT_CTRL_NUMCOMP_Pos) /*!< DWT CTRL: NUMCOMP Mask */ - -#define DWT_CTRL_NOTRCPKT_Pos 27U /*!< DWT CTRL: NOTRCPKT Position */ -#define DWT_CTRL_NOTRCPKT_Msk (0x1UL << DWT_CTRL_NOTRCPKT_Pos) /*!< DWT CTRL: NOTRCPKT Mask */ - -#define DWT_CTRL_NOEXTTRIG_Pos 26U /*!< DWT CTRL: NOEXTTRIG Position */ -#define DWT_CTRL_NOEXTTRIG_Msk (0x1UL << DWT_CTRL_NOEXTTRIG_Pos) /*!< DWT CTRL: NOEXTTRIG Mask */ - -#define DWT_CTRL_NOCYCCNT_Pos 25U /*!< DWT CTRL: NOCYCCNT Position */ -#define DWT_CTRL_NOCYCCNT_Msk (0x1UL << DWT_CTRL_NOCYCCNT_Pos) /*!< DWT CTRL: NOCYCCNT Mask */ - -#define DWT_CTRL_NOPRFCNT_Pos 24U /*!< DWT CTRL: NOPRFCNT Position */ -#define DWT_CTRL_NOPRFCNT_Msk (0x1UL << DWT_CTRL_NOPRFCNT_Pos) /*!< DWT CTRL: NOPRFCNT Mask */ - -#define DWT_CTRL_CYCEVTENA_Pos 22U /*!< DWT CTRL: CYCEVTENA Position */ -#define DWT_CTRL_CYCEVTENA_Msk (0x1UL << DWT_CTRL_CYCEVTENA_Pos) /*!< DWT CTRL: CYCEVTENA Mask */ - -#define DWT_CTRL_FOLDEVTENA_Pos 21U /*!< DWT CTRL: FOLDEVTENA Position */ -#define DWT_CTRL_FOLDEVTENA_Msk (0x1UL << DWT_CTRL_FOLDEVTENA_Pos) /*!< DWT CTRL: FOLDEVTENA Mask */ - -#define DWT_CTRL_LSUEVTENA_Pos 20U /*!< DWT CTRL: LSUEVTENA Position */ -#define DWT_CTRL_LSUEVTENA_Msk (0x1UL << DWT_CTRL_LSUEVTENA_Pos) /*!< DWT CTRL: LSUEVTENA Mask */ - -#define DWT_CTRL_SLEEPEVTENA_Pos 19U /*!< DWT CTRL: SLEEPEVTENA Position */ -#define DWT_CTRL_SLEEPEVTENA_Msk (0x1UL << DWT_CTRL_SLEEPEVTENA_Pos) /*!< DWT CTRL: SLEEPEVTENA Mask */ - -#define DWT_CTRL_EXCEVTENA_Pos 18U /*!< DWT CTRL: EXCEVTENA Position */ -#define DWT_CTRL_EXCEVTENA_Msk (0x1UL << DWT_CTRL_EXCEVTENA_Pos) /*!< DWT CTRL: EXCEVTENA Mask */ - -#define DWT_CTRL_CPIEVTENA_Pos 17U /*!< DWT CTRL: CPIEVTENA Position */ -#define DWT_CTRL_CPIEVTENA_Msk (0x1UL << DWT_CTRL_CPIEVTENA_Pos) /*!< DWT CTRL: CPIEVTENA Mask */ - -#define DWT_CTRL_EXCTRCENA_Pos 16U /*!< DWT CTRL: EXCTRCENA Position */ -#define DWT_CTRL_EXCTRCENA_Msk (0x1UL << DWT_CTRL_EXCTRCENA_Pos) /*!< DWT CTRL: EXCTRCENA Mask */ - -#define DWT_CTRL_PCSAMPLENA_Pos 12U /*!< DWT CTRL: PCSAMPLENA Position */ -#define DWT_CTRL_PCSAMPLENA_Msk (0x1UL << DWT_CTRL_PCSAMPLENA_Pos) /*!< DWT CTRL: PCSAMPLENA Mask */ - -#define DWT_CTRL_SYNCTAP_Pos 10U /*!< DWT CTRL: SYNCTAP Position */ -#define DWT_CTRL_SYNCTAP_Msk (0x3UL << DWT_CTRL_SYNCTAP_Pos) /*!< DWT CTRL: SYNCTAP Mask */ - -#define DWT_CTRL_CYCTAP_Pos 9U /*!< DWT CTRL: CYCTAP Position */ -#define DWT_CTRL_CYCTAP_Msk (0x1UL << DWT_CTRL_CYCTAP_Pos) /*!< DWT CTRL: CYCTAP Mask */ - -#define DWT_CTRL_POSTINIT_Pos 5U /*!< DWT CTRL: POSTINIT Position */ -#define DWT_CTRL_POSTINIT_Msk (0xFUL << DWT_CTRL_POSTINIT_Pos) /*!< DWT CTRL: POSTINIT Mask */ - -#define DWT_CTRL_POSTPRESET_Pos 1U /*!< DWT CTRL: POSTPRESET Position */ -#define DWT_CTRL_POSTPRESET_Msk (0xFUL << DWT_CTRL_POSTPRESET_Pos) /*!< DWT CTRL: POSTPRESET Mask */ - -#define DWT_CTRL_CYCCNTENA_Pos 0U /*!< DWT CTRL: CYCCNTENA Position */ -#define DWT_CTRL_CYCCNTENA_Msk (0x1UL /*<< DWT_CTRL_CYCCNTENA_Pos*/) /*!< DWT CTRL: CYCCNTENA Mask */ - -/* DWT CPI Count Register Definitions */ -#define DWT_CPICNT_CPICNT_Pos 0U /*!< DWT CPICNT: CPICNT Position */ -#define DWT_CPICNT_CPICNT_Msk (0xFFUL /*<< DWT_CPICNT_CPICNT_Pos*/) /*!< DWT CPICNT: CPICNT Mask */ - -/* DWT Exception Overhead Count Register Definitions */ -#define DWT_EXCCNT_EXCCNT_Pos 0U /*!< DWT EXCCNT: EXCCNT Position */ -#define DWT_EXCCNT_EXCCNT_Msk (0xFFUL /*<< DWT_EXCCNT_EXCCNT_Pos*/) /*!< DWT EXCCNT: EXCCNT Mask */ - -/* DWT Sleep Count Register Definitions */ -#define DWT_SLEEPCNT_SLEEPCNT_Pos 0U /*!< DWT SLEEPCNT: SLEEPCNT Position */ -#define DWT_SLEEPCNT_SLEEPCNT_Msk (0xFFUL /*<< DWT_SLEEPCNT_SLEEPCNT_Pos*/) /*!< DWT SLEEPCNT: SLEEPCNT Mask */ - -/* DWT LSU Count Register Definitions */ -#define DWT_LSUCNT_LSUCNT_Pos 0U /*!< DWT LSUCNT: LSUCNT Position */ -#define DWT_LSUCNT_LSUCNT_Msk (0xFFUL /*<< DWT_LSUCNT_LSUCNT_Pos*/) /*!< DWT LSUCNT: LSUCNT Mask */ - -/* DWT Folded-instruction Count Register Definitions */ -#define DWT_FOLDCNT_FOLDCNT_Pos 0U /*!< DWT FOLDCNT: FOLDCNT Position */ -#define DWT_FOLDCNT_FOLDCNT_Msk (0xFFUL /*<< DWT_FOLDCNT_FOLDCNT_Pos*/) /*!< DWT FOLDCNT: FOLDCNT Mask */ - -/* DWT Comparator Mask Register Definitions */ -#define DWT_MASK_MASK_Pos 0U /*!< DWT MASK: MASK Position */ -#define DWT_MASK_MASK_Msk (0x1FUL /*<< DWT_MASK_MASK_Pos*/) /*!< DWT MASK: MASK Mask */ - -/* DWT Comparator Function Register Definitions */ -#define DWT_FUNCTION_MATCHED_Pos 24U /*!< DWT FUNCTION: MATCHED Position */ -#define DWT_FUNCTION_MATCHED_Msk (0x1UL << DWT_FUNCTION_MATCHED_Pos) /*!< DWT FUNCTION: MATCHED Mask */ - -#define DWT_FUNCTION_DATAVADDR1_Pos 16U /*!< DWT FUNCTION: DATAVADDR1 Position */ -#define DWT_FUNCTION_DATAVADDR1_Msk (0xFUL << DWT_FUNCTION_DATAVADDR1_Pos) /*!< DWT FUNCTION: DATAVADDR1 Mask */ - -#define DWT_FUNCTION_DATAVADDR0_Pos 12U /*!< DWT FUNCTION: DATAVADDR0 Position */ -#define DWT_FUNCTION_DATAVADDR0_Msk (0xFUL << DWT_FUNCTION_DATAVADDR0_Pos) /*!< DWT FUNCTION: DATAVADDR0 Mask */ - -#define DWT_FUNCTION_DATAVSIZE_Pos 10U /*!< DWT FUNCTION: DATAVSIZE Position */ -#define DWT_FUNCTION_DATAVSIZE_Msk (0x3UL << DWT_FUNCTION_DATAVSIZE_Pos) /*!< DWT FUNCTION: DATAVSIZE Mask */ - -#define DWT_FUNCTION_LNK1ENA_Pos 9U /*!< DWT FUNCTION: LNK1ENA Position */ -#define DWT_FUNCTION_LNK1ENA_Msk (0x1UL << DWT_FUNCTION_LNK1ENA_Pos) /*!< DWT FUNCTION: LNK1ENA Mask */ - -#define DWT_FUNCTION_DATAVMATCH_Pos 8U /*!< DWT FUNCTION: DATAVMATCH Position */ -#define DWT_FUNCTION_DATAVMATCH_Msk (0x1UL << DWT_FUNCTION_DATAVMATCH_Pos) /*!< DWT FUNCTION: DATAVMATCH Mask */ - -#define DWT_FUNCTION_CYCMATCH_Pos 7U /*!< DWT FUNCTION: CYCMATCH Position */ -#define DWT_FUNCTION_CYCMATCH_Msk (0x1UL << DWT_FUNCTION_CYCMATCH_Pos) /*!< DWT FUNCTION: CYCMATCH Mask */ - -#define DWT_FUNCTION_EMITRANGE_Pos 5U /*!< DWT FUNCTION: EMITRANGE Position */ -#define DWT_FUNCTION_EMITRANGE_Msk (0x1UL << DWT_FUNCTION_EMITRANGE_Pos) /*!< DWT FUNCTION: EMITRANGE Mask */ - -#define DWT_FUNCTION_FUNCTION_Pos 0U /*!< DWT FUNCTION: FUNCTION Position */ -#define DWT_FUNCTION_FUNCTION_Msk (0xFUL /*<< DWT_FUNCTION_FUNCTION_Pos*/) /*!< DWT FUNCTION: FUNCTION Mask */ - -/*@}*/ /* end of group CMSIS_DWT */ - - -/** - \ingroup CMSIS_core_register - \defgroup CMSIS_TPI Trace Port Interface (TPI) - \brief Type definitions for the Trace Port Interface (TPI) - @{ - */ - -/** - \brief Structure type to access the Trace Port Interface Register (TPI). - */ -typedef struct -{ - __IOM uint32_t SSPSR; /*!< Offset: 0x000 (R/ ) Supported Parallel Port Size Register */ - __IOM uint32_t CSPSR; /*!< Offset: 0x004 (R/W) Current Parallel Port Size Register */ - uint32_t RESERVED0[2U]; - __IOM uint32_t ACPR; /*!< Offset: 0x010 (R/W) Asynchronous Clock Prescaler Register */ - uint32_t RESERVED1[55U]; - __IOM uint32_t SPPR; /*!< Offset: 0x0F0 (R/W) Selected Pin Protocol Register */ - uint32_t RESERVED2[131U]; - __IM uint32_t FFSR; /*!< Offset: 0x300 (R/ ) Formatter and Flush Status Register */ - __IOM uint32_t FFCR; /*!< Offset: 0x304 (R/W) Formatter and Flush Control Register */ - __IM uint32_t FSCR; /*!< Offset: 0x308 (R/ ) Formatter Synchronization Counter Register */ - uint32_t RESERVED3[759U]; - __IM uint32_t TRIGGER; /*!< Offset: 0xEE8 (R/ ) TRIGGER */ - __IM uint32_t FIFO0; /*!< Offset: 0xEEC (R/ ) Integration ETM Data */ - __IM uint32_t ITATBCTR2; /*!< Offset: 0xEF0 (R/ ) ITATBCTR2 */ - uint32_t RESERVED4[1U]; - __IM uint32_t ITATBCTR0; /*!< Offset: 0xEF8 (R/ ) ITATBCTR0 */ - __IM uint32_t FIFO1; /*!< Offset: 0xEFC (R/ ) Integration ITM Data */ - __IOM uint32_t ITCTRL; /*!< Offset: 0xF00 (R/W) Integration Mode Control */ - uint32_t RESERVED5[39U]; - __IOM uint32_t CLAIMSET; /*!< Offset: 0xFA0 (R/W) Claim tag set */ - __IOM uint32_t CLAIMCLR; /*!< Offset: 0xFA4 (R/W) Claim tag clear */ - uint32_t RESERVED7[8U]; - __IM uint32_t DEVID; /*!< Offset: 0xFC8 (R/ ) TPIU_DEVID */ - __IM uint32_t DEVTYPE; /*!< Offset: 0xFCC (R/ ) TPIU_DEVTYPE */ -} TPI_Type; - -/* TPI Asynchronous Clock Prescaler Register Definitions */ -#define TPI_ACPR_PRESCALER_Pos 0U /*!< @Deprecated TPI ACPR: PRESCALER Position */ -#define TPI_ACPR_PRESCALER_Msk (0x1FFFUL /*<< TPI_ACPR_PRESCALER_Pos*/) /*!< @Deprecated TPI ACPR: PRESCALER Mask */ - -#define TPI_ACPR_SWOSCALER_Pos 0U /*!< TPI ACPR: SWOSCALER Position */ -#define TPI_ACPR_SWOSCALER_Msk (0xFFFFUL /*<< TPI_ACPR_SWOSCALER_Pos*/) /*!< TPI ACPR: SWOSCALER Mask */ - -/* TPI Selected Pin Protocol Register Definitions */ -#define TPI_SPPR_TXMODE_Pos 0U /*!< TPI SPPR: TXMODE Position */ -#define TPI_SPPR_TXMODE_Msk (0x3UL /*<< TPI_SPPR_TXMODE_Pos*/) /*!< TPI SPPR: TXMODE Mask */ - -/* TPI Formatter and Flush Status Register Definitions */ -#define TPI_FFSR_FtNonStop_Pos 3U /*!< TPI FFSR: FtNonStop Position */ -#define TPI_FFSR_FtNonStop_Msk (0x1UL << TPI_FFSR_FtNonStop_Pos) /*!< TPI FFSR: FtNonStop Mask */ - -#define TPI_FFSR_TCPresent_Pos 2U /*!< TPI FFSR: TCPresent Position */ -#define TPI_FFSR_TCPresent_Msk (0x1UL << TPI_FFSR_TCPresent_Pos) /*!< TPI FFSR: TCPresent Mask */ - -#define TPI_FFSR_FtStopped_Pos 1U /*!< TPI FFSR: FtStopped Position */ -#define TPI_FFSR_FtStopped_Msk (0x1UL << TPI_FFSR_FtStopped_Pos) /*!< TPI FFSR: FtStopped Mask */ - -#define TPI_FFSR_FlInProg_Pos 0U /*!< TPI FFSR: FlInProg Position */ -#define TPI_FFSR_FlInProg_Msk (0x1UL /*<< TPI_FFSR_FlInProg_Pos*/) /*!< TPI FFSR: FlInProg Mask */ - -/* TPI Formatter and Flush Control Register Definitions */ -#define TPI_FFCR_TrigIn_Pos 8U /*!< TPI FFCR: TrigIn Position */ -#define TPI_FFCR_TrigIn_Msk (0x1UL << TPI_FFCR_TrigIn_Pos) /*!< TPI FFCR: TrigIn Mask */ - -#define TPI_FFCR_EnFCont_Pos 1U /*!< TPI FFCR: EnFCont Position */ -#define TPI_FFCR_EnFCont_Msk (0x1UL << TPI_FFCR_EnFCont_Pos) /*!< TPI FFCR: EnFCont Mask */ - -/* TPI TRIGGER Register Definitions */ -#define TPI_TRIGGER_TRIGGER_Pos 0U /*!< TPI TRIGGER: TRIGGER Position */ -#define TPI_TRIGGER_TRIGGER_Msk (0x1UL /*<< TPI_TRIGGER_TRIGGER_Pos*/) /*!< TPI TRIGGER: TRIGGER Mask */ - -/* TPI Integration ETM Data Register Definitions (FIFO0) */ -#define TPI_FIFO0_ITM_ATVALID_Pos 29U /*!< TPI FIFO0: ITM_ATVALID Position */ -#define TPI_FIFO0_ITM_ATVALID_Msk (0x3UL << TPI_FIFO0_ITM_ATVALID_Pos) /*!< TPI FIFO0: ITM_ATVALID Mask */ - -#define TPI_FIFO0_ITM_bytecount_Pos 27U /*!< TPI FIFO0: ITM_bytecount Position */ -#define TPI_FIFO0_ITM_bytecount_Msk (0x3UL << TPI_FIFO0_ITM_bytecount_Pos) /*!< TPI FIFO0: ITM_bytecount Mask */ - -#define TPI_FIFO0_ETM_ATVALID_Pos 26U /*!< TPI FIFO0: ETM_ATVALID Position */ -#define TPI_FIFO0_ETM_ATVALID_Msk (0x3UL << TPI_FIFO0_ETM_ATVALID_Pos) /*!< TPI FIFO0: ETM_ATVALID Mask */ - -#define TPI_FIFO0_ETM_bytecount_Pos 24U /*!< TPI FIFO0: ETM_bytecount Position */ -#define TPI_FIFO0_ETM_bytecount_Msk (0x3UL << TPI_FIFO0_ETM_bytecount_Pos) /*!< TPI FIFO0: ETM_bytecount Mask */ - -#define TPI_FIFO0_ETM2_Pos 16U /*!< TPI FIFO0: ETM2 Position */ -#define TPI_FIFO0_ETM2_Msk (0xFFUL << TPI_FIFO0_ETM2_Pos) /*!< TPI FIFO0: ETM2 Mask */ - -#define TPI_FIFO0_ETM1_Pos 8U /*!< TPI FIFO0: ETM1 Position */ -#define TPI_FIFO0_ETM1_Msk (0xFFUL << TPI_FIFO0_ETM1_Pos) /*!< TPI FIFO0: ETM1 Mask */ - -#define TPI_FIFO0_ETM0_Pos 0U /*!< TPI FIFO0: ETM0 Position */ -#define TPI_FIFO0_ETM0_Msk (0xFFUL /*<< TPI_FIFO0_ETM0_Pos*/) /*!< TPI FIFO0: ETM0 Mask */ - -/* TPI ITATBCTR2 Register Definitions */ -#define TPI_ITATBCTR2_ATREADY_Pos 0U /*!< TPI ITATBCTR2: ATREADY Position */ -#define TPI_ITATBCTR2_ATREADY_Msk (0x1UL /*<< TPI_ITATBCTR2_ATREADY_Pos*/) /*!< TPI ITATBCTR2: ATREADY Mask */ - -/* TPI Integration ITM Data Register Definitions (FIFO1) */ -#define TPI_FIFO1_ITM_ATVALID_Pos 29U /*!< TPI FIFO1: ITM_ATVALID Position */ -#define TPI_FIFO1_ITM_ATVALID_Msk (0x3UL << TPI_FIFO1_ITM_ATVALID_Pos) /*!< TPI FIFO1: ITM_ATVALID Mask */ - -#define TPI_FIFO1_ITM_bytecount_Pos 27U /*!< TPI FIFO1: ITM_bytecount Position */ -#define TPI_FIFO1_ITM_bytecount_Msk (0x3UL << TPI_FIFO1_ITM_bytecount_Pos) /*!< TPI FIFO1: ITM_bytecount Mask */ - -#define TPI_FIFO1_ETM_ATVALID_Pos 26U /*!< TPI FIFO1: ETM_ATVALID Position */ -#define TPI_FIFO1_ETM_ATVALID_Msk (0x3UL << TPI_FIFO1_ETM_ATVALID_Pos) /*!< TPI FIFO1: ETM_ATVALID Mask */ - -#define TPI_FIFO1_ETM_bytecount_Pos 24U /*!< TPI FIFO1: ETM_bytecount Position */ -#define TPI_FIFO1_ETM_bytecount_Msk (0x3UL << TPI_FIFO1_ETM_bytecount_Pos) /*!< TPI FIFO1: ETM_bytecount Mask */ - -#define TPI_FIFO1_ITM2_Pos 16U /*!< TPI FIFO1: ITM2 Position */ -#define TPI_FIFO1_ITM2_Msk (0xFFUL << TPI_FIFO1_ITM2_Pos) /*!< TPI FIFO1: ITM2 Mask */ - -#define TPI_FIFO1_ITM1_Pos 8U /*!< TPI FIFO1: ITM1 Position */ -#define TPI_FIFO1_ITM1_Msk (0xFFUL << TPI_FIFO1_ITM1_Pos) /*!< TPI FIFO1: ITM1 Mask */ - -#define TPI_FIFO1_ITM0_Pos 0U /*!< TPI FIFO1: ITM0 Position */ -#define TPI_FIFO1_ITM0_Msk (0xFFUL /*<< TPI_FIFO1_ITM0_Pos*/) /*!< TPI FIFO1: ITM0 Mask */ - -/* TPI ITATBCTR0 Register Definitions */ -#define TPI_ITATBCTR0_ATREADY_Pos 0U /*!< TPI ITATBCTR0: ATREADY Position */ -#define TPI_ITATBCTR0_ATREADY_Msk (0x1UL /*<< TPI_ITATBCTR0_ATREADY_Pos*/) /*!< TPI ITATBCTR0: ATREADY Mask */ - -/* TPI Integration Mode Control Register Definitions */ -#define TPI_ITCTRL_Mode_Pos 0U /*!< TPI ITCTRL: Mode Position */ -#define TPI_ITCTRL_Mode_Msk (0x1UL /*<< TPI_ITCTRL_Mode_Pos*/) /*!< TPI ITCTRL: Mode Mask */ - -/* TPI DEVID Register Definitions */ -#define TPI_DEVID_NRZVALID_Pos 11U /*!< TPI DEVID: NRZVALID Position */ -#define TPI_DEVID_NRZVALID_Msk (0x1UL << TPI_DEVID_NRZVALID_Pos) /*!< TPI DEVID: NRZVALID Mask */ - -#define TPI_DEVID_MANCVALID_Pos 10U /*!< TPI DEVID: MANCVALID Position */ -#define TPI_DEVID_MANCVALID_Msk (0x1UL << TPI_DEVID_MANCVALID_Pos) /*!< TPI DEVID: MANCVALID Mask */ - -#define TPI_DEVID_PTINVALID_Pos 9U /*!< TPI DEVID: PTINVALID Position */ -#define TPI_DEVID_PTINVALID_Msk (0x1UL << TPI_DEVID_PTINVALID_Pos) /*!< TPI DEVID: PTINVALID Mask */ - -#define TPI_DEVID_MinBufSz_Pos 6U /*!< TPI DEVID: MinBufSz Position */ -#define TPI_DEVID_MinBufSz_Msk (0x7UL << TPI_DEVID_MinBufSz_Pos) /*!< TPI DEVID: MinBufSz Mask */ - -#define TPI_DEVID_AsynClkIn_Pos 5U /*!< TPI DEVID: AsynClkIn Position */ -#define TPI_DEVID_AsynClkIn_Msk (0x1UL << TPI_DEVID_AsynClkIn_Pos) /*!< TPI DEVID: AsynClkIn Mask */ - -#define TPI_DEVID_NrTraceInput_Pos 0U /*!< TPI DEVID: NrTraceInput Position */ -#define TPI_DEVID_NrTraceInput_Msk (0x1FUL /*<< TPI_DEVID_NrTraceInput_Pos*/) /*!< TPI DEVID: NrTraceInput Mask */ - -/* TPI DEVTYPE Register Definitions */ -#define TPI_DEVTYPE_MajorType_Pos 4U /*!< TPI DEVTYPE: MajorType Position */ -#define TPI_DEVTYPE_MajorType_Msk (0xFUL << TPI_DEVTYPE_MajorType_Pos) /*!< TPI DEVTYPE: MajorType Mask */ - -#define TPI_DEVTYPE_SubType_Pos 0U /*!< TPI DEVTYPE: SubType Position */ -#define TPI_DEVTYPE_SubType_Msk (0xFUL /*<< TPI_DEVTYPE_SubType_Pos*/) /*!< TPI DEVTYPE: SubType Mask */ - -/*@}*/ /* end of group CMSIS_TPI */ - - -#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) -/** - \ingroup CMSIS_core_register - \defgroup CMSIS_MPU Memory Protection Unit (MPU) - \brief Type definitions for the Memory Protection Unit (MPU) - @{ - */ - -/** - \brief Structure type to access the Memory Protection Unit (MPU). - */ -typedef struct -{ - __IM uint32_t TYPE; /*!< Offset: 0x000 (R/ ) MPU Type Register */ - __IOM uint32_t CTRL; /*!< Offset: 0x004 (R/W) MPU Control Register */ - __IOM uint32_t RNR; /*!< Offset: 0x008 (R/W) MPU Region RNRber Register */ - __IOM uint32_t RBAR; /*!< Offset: 0x00C (R/W) MPU Region Base Address Register */ - __IOM uint32_t RASR; /*!< Offset: 0x010 (R/W) MPU Region Attribute and Size Register */ - __IOM uint32_t RBAR_A1; /*!< Offset: 0x014 (R/W) MPU Alias 1 Region Base Address Register */ - __IOM uint32_t RASR_A1; /*!< Offset: 0x018 (R/W) MPU Alias 1 Region Attribute and Size Register */ - __IOM uint32_t RBAR_A2; /*!< Offset: 0x01C (R/W) MPU Alias 2 Region Base Address Register */ - __IOM uint32_t RASR_A2; /*!< Offset: 0x020 (R/W) MPU Alias 2 Region Attribute and Size Register */ - __IOM uint32_t RBAR_A3; /*!< Offset: 0x024 (R/W) MPU Alias 3 Region Base Address Register */ - __IOM uint32_t RASR_A3; /*!< Offset: 0x028 (R/W) MPU Alias 3 Region Attribute and Size Register */ -} MPU_Type; - -#define MPU_TYPE_RALIASES 4U - -/* MPU Type Register Definitions */ -#define MPU_TYPE_IREGION_Pos 16U /*!< MPU TYPE: IREGION Position */ -#define MPU_TYPE_IREGION_Msk (0xFFUL << MPU_TYPE_IREGION_Pos) /*!< MPU TYPE: IREGION Mask */ - -#define MPU_TYPE_DREGION_Pos 8U /*!< MPU TYPE: DREGION Position */ -#define MPU_TYPE_DREGION_Msk (0xFFUL << MPU_TYPE_DREGION_Pos) /*!< MPU TYPE: DREGION Mask */ - -#define MPU_TYPE_SEPARATE_Pos 0U /*!< MPU TYPE: SEPARATE Position */ -#define MPU_TYPE_SEPARATE_Msk (1UL /*<< MPU_TYPE_SEPARATE_Pos*/) /*!< MPU TYPE: SEPARATE Mask */ - -/* MPU Control Register Definitions */ -#define MPU_CTRL_PRIVDEFENA_Pos 2U /*!< MPU CTRL: PRIVDEFENA Position */ -#define MPU_CTRL_PRIVDEFENA_Msk (1UL << MPU_CTRL_PRIVDEFENA_Pos) /*!< MPU CTRL: PRIVDEFENA Mask */ - -#define MPU_CTRL_HFNMIENA_Pos 1U /*!< MPU CTRL: HFNMIENA Position */ -#define MPU_CTRL_HFNMIENA_Msk (1UL << MPU_CTRL_HFNMIENA_Pos) /*!< MPU CTRL: HFNMIENA Mask */ - -#define MPU_CTRL_ENABLE_Pos 0U /*!< MPU CTRL: ENABLE Position */ -#define MPU_CTRL_ENABLE_Msk (1UL /*<< MPU_CTRL_ENABLE_Pos*/) /*!< MPU CTRL: ENABLE Mask */ - -/* MPU Region Number Register Definitions */ -#define MPU_RNR_REGION_Pos 0U /*!< MPU RNR: REGION Position */ -#define MPU_RNR_REGION_Msk (0xFFUL /*<< MPU_RNR_REGION_Pos*/) /*!< MPU RNR: REGION Mask */ - -/* MPU Region Base Address Register Definitions */ -#define MPU_RBAR_ADDR_Pos 5U /*!< MPU RBAR: ADDR Position */ -#define MPU_RBAR_ADDR_Msk (0x7FFFFFFUL << MPU_RBAR_ADDR_Pos) /*!< MPU RBAR: ADDR Mask */ - -#define MPU_RBAR_VALID_Pos 4U /*!< MPU RBAR: VALID Position */ -#define MPU_RBAR_VALID_Msk (1UL << MPU_RBAR_VALID_Pos) /*!< MPU RBAR: VALID Mask */ - -#define MPU_RBAR_REGION_Pos 0U /*!< MPU RBAR: REGION Position */ -#define MPU_RBAR_REGION_Msk (0xFUL /*<< MPU_RBAR_REGION_Pos*/) /*!< MPU RBAR: REGION Mask */ - -/* MPU Region Attribute and Size Register Definitions */ -#define MPU_RASR_ATTRS_Pos 16U /*!< MPU RASR: MPU Region Attribute field Position */ -#define MPU_RASR_ATTRS_Msk (0xFFFFUL << MPU_RASR_ATTRS_Pos) /*!< MPU RASR: MPU Region Attribute field Mask */ - -#define MPU_RASR_XN_Pos 28U /*!< MPU RASR: ATTRS.XN Position */ -#define MPU_RASR_XN_Msk (1UL << MPU_RASR_XN_Pos) /*!< MPU RASR: ATTRS.XN Mask */ - -#define MPU_RASR_AP_Pos 24U /*!< MPU RASR: ATTRS.AP Position */ -#define MPU_RASR_AP_Msk (0x7UL << MPU_RASR_AP_Pos) /*!< MPU RASR: ATTRS.AP Mask */ - -#define MPU_RASR_TEX_Pos 19U /*!< MPU RASR: ATTRS.TEX Position */ -#define MPU_RASR_TEX_Msk (0x7UL << MPU_RASR_TEX_Pos) /*!< MPU RASR: ATTRS.TEX Mask */ - -#define MPU_RASR_S_Pos 18U /*!< MPU RASR: ATTRS.S Position */ -#define MPU_RASR_S_Msk (1UL << MPU_RASR_S_Pos) /*!< MPU RASR: ATTRS.S Mask */ - -#define MPU_RASR_C_Pos 17U /*!< MPU RASR: ATTRS.C Position */ -#define MPU_RASR_C_Msk (1UL << MPU_RASR_C_Pos) /*!< MPU RASR: ATTRS.C Mask */ - -#define MPU_RASR_B_Pos 16U /*!< MPU RASR: ATTRS.B Position */ -#define MPU_RASR_B_Msk (1UL << MPU_RASR_B_Pos) /*!< MPU RASR: ATTRS.B Mask */ - -#define MPU_RASR_SRD_Pos 8U /*!< MPU RASR: Sub-Region Disable Position */ -#define MPU_RASR_SRD_Msk (0xFFUL << MPU_RASR_SRD_Pos) /*!< MPU RASR: Sub-Region Disable Mask */ - -#define MPU_RASR_SIZE_Pos 1U /*!< MPU RASR: Region Size Field Position */ -#define MPU_RASR_SIZE_Msk (0x1FUL << MPU_RASR_SIZE_Pos) /*!< MPU RASR: Region Size Field Mask */ - -#define MPU_RASR_ENABLE_Pos 0U /*!< MPU RASR: Region enable bit Position */ -#define MPU_RASR_ENABLE_Msk (1UL /*<< MPU_RASR_ENABLE_Pos*/) /*!< MPU RASR: Region enable bit Disable Mask */ - -/*@} end of group CMSIS_MPU */ -#endif /* defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) */ - - -/** - \ingroup CMSIS_core_register - \defgroup CMSIS_FPU Floating Point Unit (FPU) - \brief Type definitions for the Floating Point Unit (FPU) - @{ - */ - -/** - \brief Structure type to access the Floating Point Unit (FPU). - */ -typedef struct -{ - uint32_t RESERVED0[1U]; - __IOM uint32_t FPCCR; /*!< Offset: 0x004 (R/W) Floating-Point Context Control Register */ - __IOM uint32_t FPCAR; /*!< Offset: 0x008 (R/W) Floating-Point Context Address Register */ - __IOM uint32_t FPDSCR; /*!< Offset: 0x00C (R/W) Floating-Point Default Status Control Register */ - __IM uint32_t MVFR0; /*!< Offset: 0x010 (R/ ) Media and FP Feature Register 0 */ - __IM uint32_t MVFR1; /*!< Offset: 0x014 (R/ ) Media and FP Feature Register 1 */ - __IM uint32_t MVFR2; /*!< Offset: 0x018 (R/ ) Media and FP Feature Register 2 */ -} FPU_Type; - -/* Floating-Point Context Control Register Definitions */ -#define FPU_FPCCR_ASPEN_Pos 31U /*!< FPCCR: ASPEN bit Position */ -#define FPU_FPCCR_ASPEN_Msk (1UL << FPU_FPCCR_ASPEN_Pos) /*!< FPCCR: ASPEN bit Mask */ - -#define FPU_FPCCR_LSPEN_Pos 30U /*!< FPCCR: LSPEN Position */ -#define FPU_FPCCR_LSPEN_Msk (1UL << FPU_FPCCR_LSPEN_Pos) /*!< FPCCR: LSPEN bit Mask */ - -#define FPU_FPCCR_MONRDY_Pos 8U /*!< FPCCR: MONRDY Position */ -#define FPU_FPCCR_MONRDY_Msk (1UL << FPU_FPCCR_MONRDY_Pos) /*!< FPCCR: MONRDY bit Mask */ - -#define FPU_FPCCR_BFRDY_Pos 6U /*!< FPCCR: BFRDY Position */ -#define FPU_FPCCR_BFRDY_Msk (1UL << FPU_FPCCR_BFRDY_Pos) /*!< FPCCR: BFRDY bit Mask */ - -#define FPU_FPCCR_MMRDY_Pos 5U /*!< FPCCR: MMRDY Position */ -#define FPU_FPCCR_MMRDY_Msk (1UL << FPU_FPCCR_MMRDY_Pos) /*!< FPCCR: MMRDY bit Mask */ - -#define FPU_FPCCR_HFRDY_Pos 4U /*!< FPCCR: HFRDY Position */ -#define FPU_FPCCR_HFRDY_Msk (1UL << FPU_FPCCR_HFRDY_Pos) /*!< FPCCR: HFRDY bit Mask */ - -#define FPU_FPCCR_THREAD_Pos 3U /*!< FPCCR: processor mode bit Position */ -#define FPU_FPCCR_THREAD_Msk (1UL << FPU_FPCCR_THREAD_Pos) /*!< FPCCR: processor mode active bit Mask */ - -#define FPU_FPCCR_USER_Pos 1U /*!< FPCCR: privilege level bit Position */ -#define FPU_FPCCR_USER_Msk (1UL << FPU_FPCCR_USER_Pos) /*!< FPCCR: privilege level bit Mask */ - -#define FPU_FPCCR_LSPACT_Pos 0U /*!< FPCCR: Lazy state preservation active bit Position */ -#define FPU_FPCCR_LSPACT_Msk (1UL /*<< FPU_FPCCR_LSPACT_Pos*/) /*!< FPCCR: Lazy state preservation active bit Mask */ - -/* Floating-Point Context Address Register Definitions */ -#define FPU_FPCAR_ADDRESS_Pos 3U /*!< FPCAR: ADDRESS bit Position */ -#define FPU_FPCAR_ADDRESS_Msk (0x1FFFFFFFUL << FPU_FPCAR_ADDRESS_Pos) /*!< FPCAR: ADDRESS bit Mask */ - -/* Floating-Point Default Status Control Register Definitions */ -#define FPU_FPDSCR_AHP_Pos 26U /*!< FPDSCR: AHP bit Position */ -#define FPU_FPDSCR_AHP_Msk (1UL << FPU_FPDSCR_AHP_Pos) /*!< FPDSCR: AHP bit Mask */ - -#define FPU_FPDSCR_DN_Pos 25U /*!< FPDSCR: DN bit Position */ -#define FPU_FPDSCR_DN_Msk (1UL << FPU_FPDSCR_DN_Pos) /*!< FPDSCR: DN bit Mask */ - -#define FPU_FPDSCR_FZ_Pos 24U /*!< FPDSCR: FZ bit Position */ -#define FPU_FPDSCR_FZ_Msk (1UL << FPU_FPDSCR_FZ_Pos) /*!< FPDSCR: FZ bit Mask */ - -#define FPU_FPDSCR_RMode_Pos 22U /*!< FPDSCR: RMode bit Position */ -#define FPU_FPDSCR_RMode_Msk (3UL << FPU_FPDSCR_RMode_Pos) /*!< FPDSCR: RMode bit Mask */ - -/* Media and FP Feature Register 0 Definitions */ -#define FPU_MVFR0_FP_rounding_modes_Pos 28U /*!< MVFR0: FP rounding modes bits Position */ -#define FPU_MVFR0_FP_rounding_modes_Msk (0xFUL << FPU_MVFR0_FP_rounding_modes_Pos) /*!< MVFR0: FP rounding modes bits Mask */ - -#define FPU_MVFR0_Short_vectors_Pos 24U /*!< MVFR0: Short vectors bits Position */ -#define FPU_MVFR0_Short_vectors_Msk (0xFUL << FPU_MVFR0_Short_vectors_Pos) /*!< MVFR0: Short vectors bits Mask */ - -#define FPU_MVFR0_Square_root_Pos 20U /*!< MVFR0: Square root bits Position */ -#define FPU_MVFR0_Square_root_Msk (0xFUL << FPU_MVFR0_Square_root_Pos) /*!< MVFR0: Square root bits Mask */ - -#define FPU_MVFR0_Divide_Pos 16U /*!< MVFR0: Divide bits Position */ -#define FPU_MVFR0_Divide_Msk (0xFUL << FPU_MVFR0_Divide_Pos) /*!< MVFR0: Divide bits Mask */ - -#define FPU_MVFR0_FP_excep_trapping_Pos 12U /*!< MVFR0: FP exception trapping bits Position */ -#define FPU_MVFR0_FP_excep_trapping_Msk (0xFUL << FPU_MVFR0_FP_excep_trapping_Pos) /*!< MVFR0: FP exception trapping bits Mask */ - -#define FPU_MVFR0_Double_precision_Pos 8U /*!< MVFR0: Double-precision bits Position */ -#define FPU_MVFR0_Double_precision_Msk (0xFUL << FPU_MVFR0_Double_precision_Pos) /*!< MVFR0: Double-precision bits Mask */ - -#define FPU_MVFR0_Single_precision_Pos 4U /*!< MVFR0: Single-precision bits Position */ -#define FPU_MVFR0_Single_precision_Msk (0xFUL << FPU_MVFR0_Single_precision_Pos) /*!< MVFR0: Single-precision bits Mask */ - -#define FPU_MVFR0_A_SIMD_registers_Pos 0U /*!< MVFR0: A_SIMD registers bits Position */ -#define FPU_MVFR0_A_SIMD_registers_Msk (0xFUL /*<< FPU_MVFR0_A_SIMD_registers_Pos*/) /*!< MVFR0: A_SIMD registers bits Mask */ - -/* Media and FP Feature Register 1 Definitions */ -#define FPU_MVFR1_FP_fused_MAC_Pos 28U /*!< MVFR1: FP fused MAC bits Position */ -#define FPU_MVFR1_FP_fused_MAC_Msk (0xFUL << FPU_MVFR1_FP_fused_MAC_Pos) /*!< MVFR1: FP fused MAC bits Mask */ - -#define FPU_MVFR1_FP_HPFP_Pos 24U /*!< MVFR1: FP HPFP bits Position */ -#define FPU_MVFR1_FP_HPFP_Msk (0xFUL << FPU_MVFR1_FP_HPFP_Pos) /*!< MVFR1: FP HPFP bits Mask */ - -#define FPU_MVFR1_D_NaN_mode_Pos 4U /*!< MVFR1: D_NaN mode bits Position */ -#define FPU_MVFR1_D_NaN_mode_Msk (0xFUL << FPU_MVFR1_D_NaN_mode_Pos) /*!< MVFR1: D_NaN mode bits Mask */ - -#define FPU_MVFR1_FtZ_mode_Pos 0U /*!< MVFR1: FtZ mode bits Position */ -#define FPU_MVFR1_FtZ_mode_Msk (0xFUL /*<< FPU_MVFR1_FtZ_mode_Pos*/) /*!< MVFR1: FtZ mode bits Mask */ - -/* Media and FP Feature Register 2 Definitions */ - -/*@} end of group CMSIS_FPU */ - - -/** - \ingroup CMSIS_core_register - \defgroup CMSIS_CoreDebug Core Debug Registers (CoreDebug) - \brief Type definitions for the Core Debug Registers - @{ - */ - -/** - \brief Structure type to access the Core Debug Register (CoreDebug). - */ -typedef struct -{ - __IOM uint32_t DHCSR; /*!< Offset: 0x000 (R/W) Debug Halting Control and Status Register */ - __OM uint32_t DCRSR; /*!< Offset: 0x004 ( /W) Debug Core Register Selector Register */ - __IOM uint32_t DCRDR; /*!< Offset: 0x008 (R/W) Debug Core Register Data Register */ - __IOM uint32_t DEMCR; /*!< Offset: 0x00C (R/W) Debug Exception and Monitor Control Register */ -} CoreDebug_Type; - -/* Debug Halting Control and Status Register Definitions */ -#define CoreDebug_DHCSR_DBGKEY_Pos 16U /*!< CoreDebug DHCSR: DBGKEY Position */ -#define CoreDebug_DHCSR_DBGKEY_Msk (0xFFFFUL << CoreDebug_DHCSR_DBGKEY_Pos) /*!< CoreDebug DHCSR: DBGKEY Mask */ - -#define CoreDebug_DHCSR_S_RESET_ST_Pos 25U /*!< CoreDebug DHCSR: S_RESET_ST Position */ -#define CoreDebug_DHCSR_S_RESET_ST_Msk (1UL << CoreDebug_DHCSR_S_RESET_ST_Pos) /*!< CoreDebug DHCSR: S_RESET_ST Mask */ - -#define CoreDebug_DHCSR_S_RETIRE_ST_Pos 24U /*!< CoreDebug DHCSR: S_RETIRE_ST Position */ -#define CoreDebug_DHCSR_S_RETIRE_ST_Msk (1UL << CoreDebug_DHCSR_S_RETIRE_ST_Pos) /*!< CoreDebug DHCSR: S_RETIRE_ST Mask */ - -#define CoreDebug_DHCSR_S_LOCKUP_Pos 19U /*!< CoreDebug DHCSR: S_LOCKUP Position */ -#define CoreDebug_DHCSR_S_LOCKUP_Msk (1UL << CoreDebug_DHCSR_S_LOCKUP_Pos) /*!< CoreDebug DHCSR: S_LOCKUP Mask */ - -#define CoreDebug_DHCSR_S_SLEEP_Pos 18U /*!< CoreDebug DHCSR: S_SLEEP Position */ -#define CoreDebug_DHCSR_S_SLEEP_Msk (1UL << CoreDebug_DHCSR_S_SLEEP_Pos) /*!< CoreDebug DHCSR: S_SLEEP Mask */ - -#define CoreDebug_DHCSR_S_HALT_Pos 17U /*!< CoreDebug DHCSR: S_HALT Position */ -#define CoreDebug_DHCSR_S_HALT_Msk (1UL << CoreDebug_DHCSR_S_HALT_Pos) /*!< CoreDebug DHCSR: S_HALT Mask */ - -#define CoreDebug_DHCSR_S_REGRDY_Pos 16U /*!< CoreDebug DHCSR: S_REGRDY Position */ -#define CoreDebug_DHCSR_S_REGRDY_Msk (1UL << CoreDebug_DHCSR_S_REGRDY_Pos) /*!< CoreDebug DHCSR: S_REGRDY Mask */ - -#define CoreDebug_DHCSR_C_SNAPSTALL_Pos 5U /*!< CoreDebug DHCSR: C_SNAPSTALL Position */ -#define CoreDebug_DHCSR_C_SNAPSTALL_Msk (1UL << CoreDebug_DHCSR_C_SNAPSTALL_Pos) /*!< CoreDebug DHCSR: C_SNAPSTALL Mask */ - -#define CoreDebug_DHCSR_C_MASKINTS_Pos 3U /*!< CoreDebug DHCSR: C_MASKINTS Position */ -#define CoreDebug_DHCSR_C_MASKINTS_Msk (1UL << CoreDebug_DHCSR_C_MASKINTS_Pos) /*!< CoreDebug DHCSR: C_MASKINTS Mask */ - -#define CoreDebug_DHCSR_C_STEP_Pos 2U /*!< CoreDebug DHCSR: C_STEP Position */ -#define CoreDebug_DHCSR_C_STEP_Msk (1UL << CoreDebug_DHCSR_C_STEP_Pos) /*!< CoreDebug DHCSR: C_STEP Mask */ - -#define CoreDebug_DHCSR_C_HALT_Pos 1U /*!< CoreDebug DHCSR: C_HALT Position */ -#define CoreDebug_DHCSR_C_HALT_Msk (1UL << CoreDebug_DHCSR_C_HALT_Pos) /*!< CoreDebug DHCSR: C_HALT Mask */ - -#define CoreDebug_DHCSR_C_DEBUGEN_Pos 0U /*!< CoreDebug DHCSR: C_DEBUGEN Position */ -#define CoreDebug_DHCSR_C_DEBUGEN_Msk (1UL /*<< CoreDebug_DHCSR_C_DEBUGEN_Pos*/) /*!< CoreDebug DHCSR: C_DEBUGEN Mask */ - -/* Debug Core Register Selector Register Definitions */ -#define CoreDebug_DCRSR_REGWnR_Pos 16U /*!< CoreDebug DCRSR: REGWnR Position */ -#define CoreDebug_DCRSR_REGWnR_Msk (1UL << CoreDebug_DCRSR_REGWnR_Pos) /*!< CoreDebug DCRSR: REGWnR Mask */ - -#define CoreDebug_DCRSR_REGSEL_Pos 0U /*!< CoreDebug DCRSR: REGSEL Position */ -#define CoreDebug_DCRSR_REGSEL_Msk (0x1FUL /*<< CoreDebug_DCRSR_REGSEL_Pos*/) /*!< CoreDebug DCRSR: REGSEL Mask */ - -/* Debug Exception and Monitor Control Register Definitions */ -#define CoreDebug_DEMCR_TRCENA_Pos 24U /*!< CoreDebug DEMCR: TRCENA Position */ -#define CoreDebug_DEMCR_TRCENA_Msk (1UL << CoreDebug_DEMCR_TRCENA_Pos) /*!< CoreDebug DEMCR: TRCENA Mask */ - -#define CoreDebug_DEMCR_MON_REQ_Pos 19U /*!< CoreDebug DEMCR: MON_REQ Position */ -#define CoreDebug_DEMCR_MON_REQ_Msk (1UL << CoreDebug_DEMCR_MON_REQ_Pos) /*!< CoreDebug DEMCR: MON_REQ Mask */ - -#define CoreDebug_DEMCR_MON_STEP_Pos 18U /*!< CoreDebug DEMCR: MON_STEP Position */ -#define CoreDebug_DEMCR_MON_STEP_Msk (1UL << CoreDebug_DEMCR_MON_STEP_Pos) /*!< CoreDebug DEMCR: MON_STEP Mask */ - -#define CoreDebug_DEMCR_MON_PEND_Pos 17U /*!< CoreDebug DEMCR: MON_PEND Position */ -#define CoreDebug_DEMCR_MON_PEND_Msk (1UL << CoreDebug_DEMCR_MON_PEND_Pos) /*!< CoreDebug DEMCR: MON_PEND Mask */ - -#define CoreDebug_DEMCR_MON_EN_Pos 16U /*!< CoreDebug DEMCR: MON_EN Position */ -#define CoreDebug_DEMCR_MON_EN_Msk (1UL << CoreDebug_DEMCR_MON_EN_Pos) /*!< CoreDebug DEMCR: MON_EN Mask */ - -#define CoreDebug_DEMCR_VC_HARDERR_Pos 10U /*!< CoreDebug DEMCR: VC_HARDERR Position */ -#define CoreDebug_DEMCR_VC_HARDERR_Msk (1UL << CoreDebug_DEMCR_VC_HARDERR_Pos) /*!< CoreDebug DEMCR: VC_HARDERR Mask */ - -#define CoreDebug_DEMCR_VC_INTERR_Pos 9U /*!< CoreDebug DEMCR: VC_INTERR Position */ -#define CoreDebug_DEMCR_VC_INTERR_Msk (1UL << CoreDebug_DEMCR_VC_INTERR_Pos) /*!< CoreDebug DEMCR: VC_INTERR Mask */ - -#define CoreDebug_DEMCR_VC_BUSERR_Pos 8U /*!< CoreDebug DEMCR: VC_BUSERR Position */ -#define CoreDebug_DEMCR_VC_BUSERR_Msk (1UL << CoreDebug_DEMCR_VC_BUSERR_Pos) /*!< CoreDebug DEMCR: VC_BUSERR Mask */ - -#define CoreDebug_DEMCR_VC_STATERR_Pos 7U /*!< CoreDebug DEMCR: VC_STATERR Position */ -#define CoreDebug_DEMCR_VC_STATERR_Msk (1UL << CoreDebug_DEMCR_VC_STATERR_Pos) /*!< CoreDebug DEMCR: VC_STATERR Mask */ - -#define CoreDebug_DEMCR_VC_CHKERR_Pos 6U /*!< CoreDebug DEMCR: VC_CHKERR Position */ -#define CoreDebug_DEMCR_VC_CHKERR_Msk (1UL << CoreDebug_DEMCR_VC_CHKERR_Pos) /*!< CoreDebug DEMCR: VC_CHKERR Mask */ - -#define CoreDebug_DEMCR_VC_NOCPERR_Pos 5U /*!< CoreDebug DEMCR: VC_NOCPERR Position */ -#define CoreDebug_DEMCR_VC_NOCPERR_Msk (1UL << CoreDebug_DEMCR_VC_NOCPERR_Pos) /*!< CoreDebug DEMCR: VC_NOCPERR Mask */ - -#define CoreDebug_DEMCR_VC_MMERR_Pos 4U /*!< CoreDebug DEMCR: VC_MMERR Position */ -#define CoreDebug_DEMCR_VC_MMERR_Msk (1UL << CoreDebug_DEMCR_VC_MMERR_Pos) /*!< CoreDebug DEMCR: VC_MMERR Mask */ - -#define CoreDebug_DEMCR_VC_CORERESET_Pos 0U /*!< CoreDebug DEMCR: VC_CORERESET Position */ -#define CoreDebug_DEMCR_VC_CORERESET_Msk (1UL /*<< CoreDebug_DEMCR_VC_CORERESET_Pos*/) /*!< CoreDebug DEMCR: VC_CORERESET Mask */ - -/*@} end of group CMSIS_CoreDebug */ - - -/** - \ingroup CMSIS_core_register - \defgroup CMSIS_core_bitfield Core register bit field macros - \brief Macros for use with bit field definitions (xxx_Pos, xxx_Msk). - @{ - */ - -/** - \brief Mask and shift a bit field value for use in a register bit range. - \param[in] field Name of the register bit field. - \param[in] value Value of the bit field. This parameter is interpreted as an uint32_t type. - \return Masked and shifted value. -*/ -#define _VAL2FLD(field, value) (((uint32_t)(value) << field ## _Pos) & field ## _Msk) - -/** - \brief Mask and shift a register value to extract a bit filed value. - \param[in] field Name of the register bit field. - \param[in] value Value of register. This parameter is interpreted as an uint32_t type. - \return Masked and shifted bit field value. -*/ -#define _FLD2VAL(field, value) (((uint32_t)(value) & field ## _Msk) >> field ## _Pos) - -/*@} end of group CMSIS_core_bitfield */ - - -/** - \ingroup CMSIS_core_register - \defgroup CMSIS_core_base Core Definitions - \brief Definitions for base addresses, unions, and structures. - @{ - */ - -/* Memory mapping of Core Hardware */ -#define SCS_BASE (0xE000E000UL) /*!< System Control Space Base Address */ -#define ITM_BASE (0xE0000000UL) /*!< ITM Base Address */ -#define DWT_BASE (0xE0001000UL) /*!< DWT Base Address */ -#define TPI_BASE (0xE0040000UL) /*!< TPI Base Address */ -#define CoreDebug_BASE (0xE000EDF0UL) /*!< Core Debug Base Address */ -#define SysTick_BASE (SCS_BASE + 0x0010UL) /*!< SysTick Base Address */ -#define NVIC_BASE (SCS_BASE + 0x0100UL) /*!< NVIC Base Address */ -#define SCB_BASE (SCS_BASE + 0x0D00UL) /*!< System Control Block Base Address */ - -#define SCnSCB ((SCnSCB_Type *) SCS_BASE ) /*!< System control Register not in SCB */ -#define SCB ((SCB_Type *) SCB_BASE ) /*!< SCB configuration struct */ -#define SysTick ((SysTick_Type *) SysTick_BASE ) /*!< SysTick configuration struct */ -#define NVIC ((NVIC_Type *) NVIC_BASE ) /*!< NVIC configuration struct */ -#define ITM ((ITM_Type *) ITM_BASE ) /*!< ITM configuration struct */ -#define DWT ((DWT_Type *) DWT_BASE ) /*!< DWT configuration struct */ -#define TPI ((TPI_Type *) TPI_BASE ) /*!< TPI configuration struct */ -#define CoreDebug ((CoreDebug_Type *) CoreDebug_BASE) /*!< Core Debug configuration struct */ - -#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) - #define MPU_BASE (SCS_BASE + 0x0D90UL) /*!< Memory Protection Unit */ - #define MPU ((MPU_Type *) MPU_BASE ) /*!< Memory Protection Unit */ -#endif - -#define FPU_BASE (SCS_BASE + 0x0F30UL) /*!< Floating Point Unit */ -#define FPU ((FPU_Type *) FPU_BASE ) /*!< Floating Point Unit */ - -/*@} */ - - - -/******************************************************************************* - * Hardware Abstraction Layer - Core Function Interface contains: - - Core NVIC Functions - - Core SysTick Functions - - Core Debug Functions - - Core Register Access Functions - ******************************************************************************/ -/** - \defgroup CMSIS_Core_FunctionInterface Functions and Instructions Reference -*/ - - - -/* ########################## NVIC functions #################################### */ -/** - \ingroup CMSIS_Core_FunctionInterface - \defgroup CMSIS_Core_NVICFunctions NVIC Functions - \brief Functions that manage interrupts and exceptions via the NVIC. - @{ - */ - -#ifdef CMSIS_NVIC_VIRTUAL - #ifndef CMSIS_NVIC_VIRTUAL_HEADER_FILE - #define CMSIS_NVIC_VIRTUAL_HEADER_FILE "cmsis_nvic_virtual.h" - #endif - #include CMSIS_NVIC_VIRTUAL_HEADER_FILE -#else - #define NVIC_SetPriorityGrouping __NVIC_SetPriorityGrouping - #define NVIC_GetPriorityGrouping __NVIC_GetPriorityGrouping - #define NVIC_EnableIRQ __NVIC_EnableIRQ - #define NVIC_GetEnableIRQ __NVIC_GetEnableIRQ - #define NVIC_DisableIRQ __NVIC_DisableIRQ - #define NVIC_GetPendingIRQ __NVIC_GetPendingIRQ - #define NVIC_SetPendingIRQ __NVIC_SetPendingIRQ - #define NVIC_ClearPendingIRQ __NVIC_ClearPendingIRQ - #define NVIC_GetActive __NVIC_GetActive - #define NVIC_SetPriority __NVIC_SetPriority - #define NVIC_GetPriority __NVIC_GetPriority - #define NVIC_SystemReset __NVIC_SystemReset -#endif /* CMSIS_NVIC_VIRTUAL */ - -#ifdef CMSIS_VECTAB_VIRTUAL - #ifndef CMSIS_VECTAB_VIRTUAL_HEADER_FILE - #define CMSIS_VECTAB_VIRTUAL_HEADER_FILE "cmsis_vectab_virtual.h" - #endif - #include CMSIS_VECTAB_VIRTUAL_HEADER_FILE -#else - #define NVIC_SetVector __NVIC_SetVector - #define NVIC_GetVector __NVIC_GetVector -#endif /* (CMSIS_VECTAB_VIRTUAL) */ - -#define NVIC_USER_IRQ_OFFSET 16 - - - -/** - \brief Set Priority Grouping - \details Sets the priority grouping field using the required unlock sequence. - The parameter PriorityGroup is assigned to the field SCB->AIRCR [10:8] PRIGROUP field. - Only values from 0..7 are used. - In case of a conflict between priority grouping and available - priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set. - \param [in] PriorityGroup Priority grouping field. - */ -__STATIC_INLINE void __NVIC_SetPriorityGrouping(uint32_t PriorityGroup) -{ - uint32_t reg_value; - uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ - - reg_value = SCB->AIRCR; /* read old register configuration */ - reg_value &= ~((uint32_t)(SCB_AIRCR_VECTKEY_Msk | SCB_AIRCR_PRIGROUP_Msk)); /* clear bits to change */ - reg_value = (reg_value | - ((uint32_t)0x5FAUL << SCB_AIRCR_VECTKEY_Pos) | - (PriorityGroupTmp << SCB_AIRCR_PRIGROUP_Pos) ); /* Insert write key and priority group */ - SCB->AIRCR = reg_value; -} - - -/** - \brief Get Priority Grouping - \details Reads the priority grouping field from the NVIC Interrupt Controller. - \return Priority grouping field (SCB->AIRCR [10:8] PRIGROUP field). - */ -__STATIC_INLINE uint32_t __NVIC_GetPriorityGrouping(void) -{ - return ((uint32_t)((SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) >> SCB_AIRCR_PRIGROUP_Pos)); -} - - -/** - \brief Enable Interrupt - \details Enables a device specific interrupt in the NVIC interrupt controller. - \param [in] IRQn Device specific interrupt number. - \note IRQn must not be negative. - */ -__STATIC_INLINE void __NVIC_EnableIRQ(IRQn_Type IRQn) -{ - if ((int32_t)(IRQn) >= 0) - { - NVIC->ISER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); - } -} - - -/** - \brief Get Interrupt Enable status - \details Returns a device specific interrupt enable status from the NVIC interrupt controller. - \param [in] IRQn Device specific interrupt number. - \return 0 Interrupt is not enabled. - \return 1 Interrupt is enabled. - \note IRQn must not be negative. - */ -__STATIC_INLINE uint32_t __NVIC_GetEnableIRQ(IRQn_Type IRQn) -{ - if ((int32_t)(IRQn) >= 0) - { - return((uint32_t)(((NVIC->ISER[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); - } - else - { - return(0U); - } -} - - -/** - \brief Disable Interrupt - \details Disables a device specific interrupt in the NVIC interrupt controller. - \param [in] IRQn Device specific interrupt number. - \note IRQn must not be negative. - */ -__STATIC_INLINE void __NVIC_DisableIRQ(IRQn_Type IRQn) -{ - if ((int32_t)(IRQn) >= 0) - { - NVIC->ICER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); - __DSB(); - __ISB(); - } -} - - -/** - \brief Get Pending Interrupt - \details Reads the NVIC pending register and returns the pending bit for the specified device specific interrupt. - \param [in] IRQn Device specific interrupt number. - \return 0 Interrupt status is not pending. - \return 1 Interrupt status is pending. - \note IRQn must not be negative. - */ -__STATIC_INLINE uint32_t __NVIC_GetPendingIRQ(IRQn_Type IRQn) -{ - if ((int32_t)(IRQn) >= 0) - { - return((uint32_t)(((NVIC->ISPR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); - } - else - { - return(0U); - } -} - - -/** - \brief Set Pending Interrupt - \details Sets the pending bit of a device specific interrupt in the NVIC pending register. - \param [in] IRQn Device specific interrupt number. - \note IRQn must not be negative. - */ -__STATIC_INLINE void __NVIC_SetPendingIRQ(IRQn_Type IRQn) -{ - if ((int32_t)(IRQn) >= 0) - { - NVIC->ISPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); - } -} - - -/** - \brief Clear Pending Interrupt - \details Clears the pending bit of a device specific interrupt in the NVIC pending register. - \param [in] IRQn Device specific interrupt number. - \note IRQn must not be negative. - */ -__STATIC_INLINE void __NVIC_ClearPendingIRQ(IRQn_Type IRQn) -{ - if ((int32_t)(IRQn) >= 0) - { - NVIC->ICPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); - } -} - - -/** - \brief Get Active Interrupt - \details Reads the active register in the NVIC and returns the active bit for the device specific interrupt. - \param [in] IRQn Device specific interrupt number. - \return 0 Interrupt status is not active. - \return 1 Interrupt status is active. - \note IRQn must not be negative. - */ -__STATIC_INLINE uint32_t __NVIC_GetActive(IRQn_Type IRQn) -{ - if ((int32_t)(IRQn) >= 0) - { - return((uint32_t)(((NVIC->IABR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); - } - else - { - return(0U); - } -} - - -/** - \brief Set Interrupt Priority - \details Sets the priority of a device specific interrupt or a processor exception. - The interrupt number can be positive to specify a device specific interrupt, - or negative to specify a processor exception. - \param [in] IRQn Interrupt number. - \param [in] priority Priority to set. - \note The priority cannot be set for every processor exception. - */ -__STATIC_INLINE void __NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority) -{ - if ((int32_t)(IRQn) >= 0) - { - NVIC->IP[((uint32_t)IRQn)] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL); - } - else - { - SCB->SHPR[(((uint32_t)IRQn) & 0xFUL)-4UL] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL); - } -} - - -/** - \brief Get Interrupt Priority - \details Reads the priority of a device specific interrupt or a processor exception. - The interrupt number can be positive to specify a device specific interrupt, - or negative to specify a processor exception. - \param [in] IRQn Interrupt number. - \return Interrupt Priority. - Value is aligned automatically to the implemented priority bits of the microcontroller. - */ -__STATIC_INLINE uint32_t __NVIC_GetPriority(IRQn_Type IRQn) -{ - - if ((int32_t)(IRQn) >= 0) - { - return(((uint32_t)NVIC->IP[((uint32_t)IRQn)] >> (8U - __NVIC_PRIO_BITS))); - } - else - { - return(((uint32_t)SCB->SHPR[(((uint32_t)IRQn) & 0xFUL)-4UL] >> (8U - __NVIC_PRIO_BITS))); - } -} - - -/** - \brief Encode Priority - \details Encodes the priority for an interrupt with the given priority group, - preemptive priority value, and subpriority value. - In case of a conflict between priority grouping and available - priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set. - \param [in] PriorityGroup Used priority group. - \param [in] PreemptPriority Preemptive priority value (starting from 0). - \param [in] SubPriority Subpriority value (starting from 0). - \return Encoded priority. Value can be used in the function \ref NVIC_SetPriority(). - */ -__STATIC_INLINE uint32_t NVIC_EncodePriority (uint32_t PriorityGroup, uint32_t PreemptPriority, uint32_t SubPriority) -{ - uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ - uint32_t PreemptPriorityBits; - uint32_t SubPriorityBits; - - PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp); - SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS)); - - return ( - ((PreemptPriority & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL)) << SubPriorityBits) | - ((SubPriority & (uint32_t)((1UL << (SubPriorityBits )) - 1UL))) - ); -} - - -/** - \brief Decode Priority - \details Decodes an interrupt priority value with a given priority group to - preemptive priority value and subpriority value. - In case of a conflict between priority grouping and available - priority bits (__NVIC_PRIO_BITS) the smallest possible priority group is set. - \param [in] Priority Priority value, which can be retrieved with the function \ref NVIC_GetPriority(). - \param [in] PriorityGroup Used priority group. - \param [out] pPreemptPriority Preemptive priority value (starting from 0). - \param [out] pSubPriority Subpriority value (starting from 0). - */ -__STATIC_INLINE void NVIC_DecodePriority (uint32_t Priority, uint32_t PriorityGroup, uint32_t* const pPreemptPriority, uint32_t* const pSubPriority) -{ - uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ - uint32_t PreemptPriorityBits; - uint32_t SubPriorityBits; - - PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp); - SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS)); - - *pPreemptPriority = (Priority >> SubPriorityBits) & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL); - *pSubPriority = (Priority ) & (uint32_t)((1UL << (SubPriorityBits )) - 1UL); -} - - -/** - \brief Set Interrupt Vector - \details Sets an interrupt vector in SRAM based interrupt vector table. - The interrupt number can be positive to specify a device specific interrupt, - or negative to specify a processor exception. - VTOR must been relocated to SRAM before. - \param [in] IRQn Interrupt number - \param [in] vector Address of interrupt handler function - */ -__STATIC_INLINE void __NVIC_SetVector(IRQn_Type IRQn, uint32_t vector) -{ - uint32_t *vectors = (uint32_t *)SCB->VTOR; - vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET] = vector; -} - - -/** - \brief Get Interrupt Vector - \details Reads an interrupt vector from interrupt vector table. - The interrupt number can be positive to specify a device specific interrupt, - or negative to specify a processor exception. - \param [in] IRQn Interrupt number. - \return Address of interrupt handler function - */ -__STATIC_INLINE uint32_t __NVIC_GetVector(IRQn_Type IRQn) -{ - uint32_t *vectors = (uint32_t *)SCB->VTOR; - return vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET]; -} - - -/** - \brief System Reset - \details Initiates a system reset request to reset the MCU. - */ -__STATIC_INLINE void __NVIC_SystemReset(void) -{ - __DSB(); /* Ensure all outstanding memory accesses included - buffered write are completed before reset */ - SCB->AIRCR = (uint32_t)((0x5FAUL << SCB_AIRCR_VECTKEY_Pos) | - (SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) | - SCB_AIRCR_SYSRESETREQ_Msk ); /* Keep priority group unchanged */ - __DSB(); /* Ensure completion of memory access */ - - for(;;) /* wait until reset */ - { - __NOP(); - } -} - -/*@} end of CMSIS_Core_NVICFunctions */ - -/* ########################## MPU functions #################################### */ - -#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) - -#include "mpu_armv7.h" - -#endif - -/* ########################## FPU functions #################################### */ -/** - \ingroup CMSIS_Core_FunctionInterface - \defgroup CMSIS_Core_FpuFunctions FPU Functions - \brief Function that provides FPU type. - @{ - */ - -/** - \brief get FPU type - \details returns the FPU type - \returns - - \b 0: No FPU - - \b 1: Single precision FPU - - \b 2: Double + Single precision FPU - */ -__STATIC_INLINE uint32_t SCB_GetFPUType(void) -{ - uint32_t mvfr0; - - mvfr0 = SCB->MVFR0; - if ((mvfr0 & (FPU_MVFR0_Single_precision_Msk | FPU_MVFR0_Double_precision_Msk)) == 0x220U) - { - return 2U; /* Double + Single precision FPU */ - } - else if ((mvfr0 & (FPU_MVFR0_Single_precision_Msk | FPU_MVFR0_Double_precision_Msk)) == 0x020U) - { - return 1U; /* Single precision FPU */ - } - else - { - return 0U; /* No FPU */ - } -} - - -/*@} end of CMSIS_Core_FpuFunctions */ - - - -/* ########################## Cache functions #################################### */ -/** - \ingroup CMSIS_Core_FunctionInterface - \defgroup CMSIS_Core_CacheFunctions Cache Functions - \brief Functions that configure Instruction and Data cache. - @{ - */ - -/* Cache Size ID Register Macros */ -#define CCSIDR_WAYS(x) (((x) & SCB_CCSIDR_ASSOCIATIVITY_Msk) >> SCB_CCSIDR_ASSOCIATIVITY_Pos) -#define CCSIDR_SETS(x) (((x) & SCB_CCSIDR_NUMSETS_Msk ) >> SCB_CCSIDR_NUMSETS_Pos ) - - -/** - \brief Enable I-Cache - \details Turns on I-Cache - */ -__STATIC_INLINE void SCB_EnableICache (void) -{ - #if defined (__ICACHE_PRESENT) && (__ICACHE_PRESENT == 1U) - __DSB(); - __ISB(); - SCB->ICIALLU = 0UL; /* invalidate I-Cache */ - __DSB(); - __ISB(); - SCB->CCR |= (uint32_t)SCB_CCR_IC_Msk; /* enable I-Cache */ - __DSB(); - __ISB(); - #endif -} - - -/** - \brief Disable I-Cache - \details Turns off I-Cache - */ -__STATIC_INLINE void SCB_DisableICache (void) -{ - #if defined (__ICACHE_PRESENT) && (__ICACHE_PRESENT == 1U) - __DSB(); - __ISB(); - SCB->CCR &= ~(uint32_t)SCB_CCR_IC_Msk; /* disable I-Cache */ - SCB->ICIALLU = 0UL; /* invalidate I-Cache */ - __DSB(); - __ISB(); - #endif -} - - -/** - \brief Invalidate I-Cache - \details Invalidates I-Cache - */ -__STATIC_INLINE void SCB_InvalidateICache (void) -{ - #if defined (__ICACHE_PRESENT) && (__ICACHE_PRESENT == 1U) - __DSB(); - __ISB(); - SCB->ICIALLU = 0UL; - __DSB(); - __ISB(); - #endif -} - - -/** - \brief Enable D-Cache - \details Turns on D-Cache - */ -__STATIC_INLINE void SCB_EnableDCache (void) -{ - #if defined (__DCACHE_PRESENT) && (__DCACHE_PRESENT == 1U) - uint32_t ccsidr; - uint32_t sets; - uint32_t ways; - - SCB->CSSELR = 0U; /*(0U << 1U) | 0U;*/ /* Level 1 data cache */ - __DSB(); - - ccsidr = SCB->CCSIDR; - - /* invalidate D-Cache */ - sets = (uint32_t)(CCSIDR_SETS(ccsidr)); - do { - ways = (uint32_t)(CCSIDR_WAYS(ccsidr)); - do { - SCB->DCISW = (((sets << SCB_DCISW_SET_Pos) & SCB_DCISW_SET_Msk) | - ((ways << SCB_DCISW_WAY_Pos) & SCB_DCISW_WAY_Msk) ); - #if defined ( __CC_ARM ) - __schedule_barrier(); - #endif - } while (ways-- != 0U); - } while(sets-- != 0U); - __DSB(); - - SCB->CCR |= (uint32_t)SCB_CCR_DC_Msk; /* enable D-Cache */ - - __DSB(); - __ISB(); - #endif -} - - -/** - \brief Disable D-Cache - \details Turns off D-Cache - */ -__STATIC_INLINE void SCB_DisableDCache (void) -{ - #if defined (__DCACHE_PRESENT) && (__DCACHE_PRESENT == 1U) - register uint32_t ccsidr; - register uint32_t sets; - register uint32_t ways; - - SCB->CSSELR = 0U; /*(0U << 1U) | 0U;*/ /* Level 1 data cache */ - __DSB(); - - SCB->CCR &= ~(uint32_t)SCB_CCR_DC_Msk; /* disable D-Cache */ - __DSB(); - - ccsidr = SCB->CCSIDR; - - /* clean & invalidate D-Cache */ - sets = (uint32_t)(CCSIDR_SETS(ccsidr)); - do { - ways = (uint32_t)(CCSIDR_WAYS(ccsidr)); - do { - SCB->DCCISW = (((sets << SCB_DCCISW_SET_Pos) & SCB_DCCISW_SET_Msk) | - ((ways << SCB_DCCISW_WAY_Pos) & SCB_DCCISW_WAY_Msk) ); - #if defined ( __CC_ARM ) - __schedule_barrier(); - #endif - } while (ways-- != 0U); - } while(sets-- != 0U); - - __DSB(); - __ISB(); - #endif -} - - -/** - \brief Invalidate D-Cache - \details Invalidates D-Cache - */ -__STATIC_INLINE void SCB_InvalidateDCache (void) -{ - #if defined (__DCACHE_PRESENT) && (__DCACHE_PRESENT == 1U) - uint32_t ccsidr; - uint32_t sets; - uint32_t ways; - - SCB->CSSELR = 0U; /*(0U << 1U) | 0U;*/ /* Level 1 data cache */ - __DSB(); - - ccsidr = SCB->CCSIDR; - - /* invalidate D-Cache */ - sets = (uint32_t)(CCSIDR_SETS(ccsidr)); - do { - ways = (uint32_t)(CCSIDR_WAYS(ccsidr)); - do { - SCB->DCISW = (((sets << SCB_DCISW_SET_Pos) & SCB_DCISW_SET_Msk) | - ((ways << SCB_DCISW_WAY_Pos) & SCB_DCISW_WAY_Msk) ); - #if defined ( __CC_ARM ) - __schedule_barrier(); - #endif - } while (ways-- != 0U); - } while(sets-- != 0U); - - __DSB(); - __ISB(); - #endif -} - - -/** - \brief Clean D-Cache - \details Cleans D-Cache - */ -__STATIC_INLINE void SCB_CleanDCache (void) -{ - #if defined (__DCACHE_PRESENT) && (__DCACHE_PRESENT == 1U) - uint32_t ccsidr; - uint32_t sets; - uint32_t ways; - - SCB->CSSELR = 0U; /*(0U << 1U) | 0U;*/ /* Level 1 data cache */ - __DSB(); - - ccsidr = SCB->CCSIDR; - - /* clean D-Cache */ - sets = (uint32_t)(CCSIDR_SETS(ccsidr)); - do { - ways = (uint32_t)(CCSIDR_WAYS(ccsidr)); - do { - SCB->DCCSW = (((sets << SCB_DCCSW_SET_Pos) & SCB_DCCSW_SET_Msk) | - ((ways << SCB_DCCSW_WAY_Pos) & SCB_DCCSW_WAY_Msk) ); - #if defined ( __CC_ARM ) - __schedule_barrier(); - #endif - } while (ways-- != 0U); - } while(sets-- != 0U); - - __DSB(); - __ISB(); - #endif -} - - -/** - \brief Clean & Invalidate D-Cache - \details Cleans and Invalidates D-Cache - */ -__STATIC_INLINE void SCB_CleanInvalidateDCache (void) -{ - #if defined (__DCACHE_PRESENT) && (__DCACHE_PRESENT == 1U) - uint32_t ccsidr; - uint32_t sets; - uint32_t ways; - - SCB->CSSELR = 0U; /*(0U << 1U) | 0U;*/ /* Level 1 data cache */ - __DSB(); - - ccsidr = SCB->CCSIDR; - - /* clean & invalidate D-Cache */ - sets = (uint32_t)(CCSIDR_SETS(ccsidr)); - do { - ways = (uint32_t)(CCSIDR_WAYS(ccsidr)); - do { - SCB->DCCISW = (((sets << SCB_DCCISW_SET_Pos) & SCB_DCCISW_SET_Msk) | - ((ways << SCB_DCCISW_WAY_Pos) & SCB_DCCISW_WAY_Msk) ); - #if defined ( __CC_ARM ) - __schedule_barrier(); - #endif - } while (ways-- != 0U); - } while(sets-- != 0U); - - __DSB(); - __ISB(); - #endif -} - - -/** - \brief D-Cache Invalidate by address - \details Invalidates D-Cache for the given address - \param[in] addr address (aligned to 32-byte boundary) - \param[in] dsize size of memory block (in number of bytes) -*/ -__STATIC_INLINE void SCB_InvalidateDCache_by_Addr (uint32_t *addr, int32_t dsize) -{ - #if defined (__DCACHE_PRESENT) && (__DCACHE_PRESENT == 1U) - int32_t op_size = dsize; - uint32_t op_addr = (uint32_t)addr; - int32_t linesize = 32; /* in Cortex-M7 size of cache line is fixed to 8 words (32 bytes) */ - - __DSB(); - - while (op_size > 0) { - SCB->DCIMVAC = op_addr; - op_addr += (uint32_t)linesize; - op_size -= linesize; - } - - __DSB(); - __ISB(); - #endif -} - - -/** - \brief D-Cache Clean by address - \details Cleans D-Cache for the given address - \param[in] addr address (aligned to 32-byte boundary) - \param[in] dsize size of memory block (in number of bytes) -*/ -__STATIC_INLINE void SCB_CleanDCache_by_Addr (uint32_t *addr, int32_t dsize) -{ - #if defined (__DCACHE_PRESENT) && (__DCACHE_PRESENT == 1U) - int32_t op_size = dsize; - uint32_t op_addr = (uint32_t) addr; - int32_t linesize = 32; /* in Cortex-M7 size of cache line is fixed to 8 words (32 bytes) */ - - __DSB(); - - while (op_size > 0) { - SCB->DCCMVAC = op_addr; - op_addr += (uint32_t)linesize; - op_size -= linesize; - } - - __DSB(); - __ISB(); - #endif -} - - -/** - \brief D-Cache Clean and Invalidate by address - \details Cleans and invalidates D_Cache for the given address - \param[in] addr address (aligned to 32-byte boundary) - \param[in] dsize size of memory block (in number of bytes) -*/ -__STATIC_INLINE void SCB_CleanInvalidateDCache_by_Addr (uint32_t *addr, int32_t dsize) -{ - #if defined (__DCACHE_PRESENT) && (__DCACHE_PRESENT == 1U) - int32_t op_size = dsize; - uint32_t op_addr = (uint32_t) addr; - int32_t linesize = 32; /* in Cortex-M7 size of cache line is fixed to 8 words (32 bytes) */ - - __DSB(); - - while (op_size > 0) { - SCB->DCCIMVAC = op_addr; - op_addr += (uint32_t)linesize; - op_size -= linesize; - } - - __DSB(); - __ISB(); - #endif -} - - -/*@} end of CMSIS_Core_CacheFunctions */ - - - -/* ################################## SysTick function ############################################ */ -/** - \ingroup CMSIS_Core_FunctionInterface - \defgroup CMSIS_Core_SysTickFunctions SysTick Functions - \brief Functions that configure the System. - @{ - */ - -#if defined (__Vendor_SysTickConfig) && (__Vendor_SysTickConfig == 0U) - -/** - \brief System Tick Configuration - \details Initializes the System Timer and its interrupt, and starts the System Tick Timer. - Counter is in free running mode to generate periodic interrupts. - \param [in] ticks Number of ticks between two interrupts. - \return 0 Function succeeded. - \return 1 Function failed. - \note When the variable __Vendor_SysTickConfig is set to 1, then the - function SysTick_Config is not included. In this case, the file device.h - must contain a vendor-specific implementation of this function. - */ -__STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks) -{ - if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk) - { - return (1UL); /* Reload value impossible */ - } - - SysTick->LOAD = (uint32_t)(ticks - 1UL); /* set reload register */ - NVIC_SetPriority (SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */ - SysTick->VAL = 0UL; /* Load the SysTick Counter Value */ - SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk | - SysTick_CTRL_TICKINT_Msk | - SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */ - return (0UL); /* Function successful */ -} - -#endif - -/*@} end of CMSIS_Core_SysTickFunctions */ - - - -/* ##################################### Debug In/Output function ########################################### */ -/** - \ingroup CMSIS_Core_FunctionInterface - \defgroup CMSIS_core_DebugFunctions ITM Functions - \brief Functions that access the ITM debug interface. - @{ - */ - -extern volatile int32_t ITM_RxBuffer; /*!< External variable to receive characters. */ -#define ITM_RXBUFFER_EMPTY ((int32_t)0x5AA55AA5U) /*!< Value identifying \ref ITM_RxBuffer is ready for next character. */ - - -/** - \brief ITM Send Character - \details Transmits a character via the ITM channel 0, and - \li Just returns when no debugger is connected that has booked the output. - \li Is blocking when a debugger is connected, but the previous character sent has not been transmitted. - \param [in] ch Character to transmit. - \returns Character to transmit. - */ -__STATIC_INLINE uint32_t ITM_SendChar (uint32_t ch) -{ - if (((ITM->TCR & ITM_TCR_ITMENA_Msk) != 0UL) && /* ITM enabled */ - ((ITM->TER & 1UL ) != 0UL) ) /* ITM Port #0 enabled */ - { - while (ITM->PORT[0U].u32 == 0UL) - { - __NOP(); - } - ITM->PORT[0U].u8 = (uint8_t)ch; - } - return (ch); -} - - -/** - \brief ITM Receive Character - \details Inputs a character via the external variable \ref ITM_RxBuffer. - \return Received character. - \return -1 No character pending. - */ -__STATIC_INLINE int32_t ITM_ReceiveChar (void) -{ - int32_t ch = -1; /* no character available */ - - if (ITM_RxBuffer != ITM_RXBUFFER_EMPTY) - { - ch = ITM_RxBuffer; - ITM_RxBuffer = ITM_RXBUFFER_EMPTY; /* ready for next character */ - } - - return (ch); -} - - -/** - \brief ITM Check Character - \details Checks whether a character is pending for reading in the variable \ref ITM_RxBuffer. - \return 0 No character available. - \return 1 Character available. - */ -__STATIC_INLINE int32_t ITM_CheckChar (void) -{ - - if (ITM_RxBuffer == ITM_RXBUFFER_EMPTY) - { - return (0); /* no character available */ - } - else - { - return (1); /* character available */ - } -} - -/*@} end of CMSIS_core_DebugFunctions */ - - - - -#ifdef __cplusplus -} -#endif - -#endif /* __CORE_CM7_H_DEPENDANT */ - -#endif /* __CMSIS_GENERIC */ diff --git a/bsp/essemi/es32f0271/libraries/CMSIS/Include/core_sc000.h b/bsp/essemi/es32f0271/libraries/CMSIS/Include/core_sc000.h deleted file mode 100644 index 9aab5e5b3e..0000000000 --- a/bsp/essemi/es32f0271/libraries/CMSIS/Include/core_sc000.h +++ /dev/null @@ -1,1016 +0,0 @@ -/**************************************************************************//** - * @file core_sc000.h - * @brief CMSIS SC000 Core Peripheral Access Layer Header File - * @version V5.0.3 - * @date 10. January 2018 - ******************************************************************************/ -/* - * Copyright (c) 2009-2018 Arm Limited. All rights reserved. - * - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed under the Apache License, Version 2.0 (the License); you may - * not use this file except in compliance with the License. - * You may obtain a copy of the License at - * - * www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an AS IS BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - */ - -#if defined ( __ICCARM__ ) - #pragma system_include /* treat file as system include file for MISRA check */ -#elif defined (__clang__) - #pragma clang system_header /* treat file as system include file */ -#endif - -#ifndef __CORE_SC000_H_GENERIC -#define __CORE_SC000_H_GENERIC - -#include - -#ifdef __cplusplus - extern "C" { -#endif - -/** - \page CMSIS_MISRA_Exceptions MISRA-C:2004 Compliance Exceptions - CMSIS violates the following MISRA-C:2004 rules: - - \li Required Rule 8.5, object/function definition in header file.
- Function definitions in header files are used to allow 'inlining'. - - \li Required Rule 18.4, declaration of union type or object of union type: '{...}'.
- Unions are used for effective representation of core registers. - - \li Advisory Rule 19.7, Function-like macro defined.
- Function-like macros are used to allow more efficient code. - */ - - -/******************************************************************************* - * CMSIS definitions - ******************************************************************************/ -/** - \ingroup SC000 - @{ - */ - -#include "cmsis_version.h" - -/* CMSIS SC000 definitions */ -#define __SC000_CMSIS_VERSION_MAIN (__CM_CMSIS_VERSION_MAIN) /*!< \deprecated [31:16] CMSIS HAL main version */ -#define __SC000_CMSIS_VERSION_SUB (__CM_CMSIS_VERSION_SUB) /*!< \deprecated [15:0] CMSIS HAL sub version */ -#define __SC000_CMSIS_VERSION ((__SC000_CMSIS_VERSION_MAIN << 16U) | \ - __SC000_CMSIS_VERSION_SUB ) /*!< \deprecated CMSIS HAL version number */ - -#define __CORTEX_SC (000U) /*!< Cortex secure core */ - -/** __FPU_USED indicates whether an FPU is used or not. - This core does not support an FPU at all -*/ -#define __FPU_USED 0U - -#if defined ( __CC_ARM ) - #if defined __TARGET_FPU_VFP - #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" - #endif - -#elif defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) - #if defined __ARM_PCS_VFP - #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" - #endif - -#elif defined ( __GNUC__ ) - #if defined (__VFP_FP__) && !defined(__SOFTFP__) - #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" - #endif - -#elif defined ( __ICCARM__ ) - #if defined __ARMVFP__ - #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" - #endif - -#elif defined ( __TI_ARM__ ) - #if defined __TI_VFP_SUPPORT__ - #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" - #endif - -#elif defined ( __TASKING__ ) - #if defined __FPU_VFP__ - #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" - #endif - -#elif defined ( __CSMC__ ) - #if ( __CSMC__ & 0x400U) - #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" - #endif - -#endif - -#include "cmsis_compiler.h" /* CMSIS compiler specific defines */ - - -#ifdef __cplusplus -} -#endif - -#endif /* __CORE_SC000_H_GENERIC */ - -#ifndef __CMSIS_GENERIC - -#ifndef __CORE_SC000_H_DEPENDANT -#define __CORE_SC000_H_DEPENDANT - -#ifdef __cplusplus - extern "C" { -#endif - -/* check device defines and use defaults */ -#if defined __CHECK_DEVICE_DEFINES - #ifndef __SC000_REV - #define __SC000_REV 0x0000U - #warning "__SC000_REV not defined in device header file; using default!" - #endif - - #ifndef __MPU_PRESENT - #define __MPU_PRESENT 0U - #warning "__MPU_PRESENT not defined in device header file; using default!" - #endif - - #ifndef __NVIC_PRIO_BITS - #define __NVIC_PRIO_BITS 2U - #warning "__NVIC_PRIO_BITS not defined in device header file; using default!" - #endif - - #ifndef __Vendor_SysTickConfig - #define __Vendor_SysTickConfig 0U - #warning "__Vendor_SysTickConfig not defined in device header file; using default!" - #endif -#endif - -/* IO definitions (access restrictions to peripheral registers) */ -/** - \defgroup CMSIS_glob_defs CMSIS Global Defines - - IO Type Qualifiers are used - \li to specify the access to peripheral variables. - \li for automatic generation of peripheral register debug information. -*/ -#ifdef __cplusplus - #define __I volatile /*!< Defines 'read only' permissions */ -#else - #define __I volatile const /*!< Defines 'read only' permissions */ -#endif -#define __O volatile /*!< Defines 'write only' permissions */ -#define __IO volatile /*!< Defines 'read / write' permissions */ - -/* following defines should be used for structure members */ -#define __IM volatile const /*! Defines 'read only' structure member permissions */ -#define __OM volatile /*! Defines 'write only' structure member permissions */ -#define __IOM volatile /*! Defines 'read / write' structure member permissions */ - -/*@} end of group SC000 */ - - - -/******************************************************************************* - * Register Abstraction - Core Register contain: - - Core Register - - Core NVIC Register - - Core SCB Register - - Core SysTick Register - - Core MPU Register - ******************************************************************************/ -/** - \defgroup CMSIS_core_register Defines and Type Definitions - \brief Type definitions and defines for Cortex-M processor based devices. -*/ - -/** - \ingroup CMSIS_core_register - \defgroup CMSIS_CORE Status and Control Registers - \brief Core Register type definitions. - @{ - */ - -/** - \brief Union type to access the Application Program Status Register (APSR). - */ -typedef union -{ - struct - { - uint32_t _reserved0:28; /*!< bit: 0..27 Reserved */ - uint32_t V:1; /*!< bit: 28 Overflow condition code flag */ - uint32_t C:1; /*!< bit: 29 Carry condition code flag */ - uint32_t Z:1; /*!< bit: 30 Zero condition code flag */ - uint32_t N:1; /*!< bit: 31 Negative condition code flag */ - } b; /*!< Structure used for bit access */ - uint32_t w; /*!< Type used for word access */ -} APSR_Type; - -/* APSR Register Definitions */ -#define APSR_N_Pos 31U /*!< APSR: N Position */ -#define APSR_N_Msk (1UL << APSR_N_Pos) /*!< APSR: N Mask */ - -#define APSR_Z_Pos 30U /*!< APSR: Z Position */ -#define APSR_Z_Msk (1UL << APSR_Z_Pos) /*!< APSR: Z Mask */ - -#define APSR_C_Pos 29U /*!< APSR: C Position */ -#define APSR_C_Msk (1UL << APSR_C_Pos) /*!< APSR: C Mask */ - -#define APSR_V_Pos 28U /*!< APSR: V Position */ -#define APSR_V_Msk (1UL << APSR_V_Pos) /*!< APSR: V Mask */ - - -/** - \brief Union type to access the Interrupt Program Status Register (IPSR). - */ -typedef union -{ - struct - { - uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */ - uint32_t _reserved0:23; /*!< bit: 9..31 Reserved */ - } b; /*!< Structure used for bit access */ - uint32_t w; /*!< Type used for word access */ -} IPSR_Type; - -/* IPSR Register Definitions */ -#define IPSR_ISR_Pos 0U /*!< IPSR: ISR Position */ -#define IPSR_ISR_Msk (0x1FFUL /*<< IPSR_ISR_Pos*/) /*!< IPSR: ISR Mask */ - - -/** - \brief Union type to access the Special-Purpose Program Status Registers (xPSR). - */ -typedef union -{ - struct - { - uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */ - uint32_t _reserved0:15; /*!< bit: 9..23 Reserved */ - uint32_t T:1; /*!< bit: 24 Thumb bit (read 0) */ - uint32_t _reserved1:3; /*!< bit: 25..27 Reserved */ - uint32_t V:1; /*!< bit: 28 Overflow condition code flag */ - uint32_t C:1; /*!< bit: 29 Carry condition code flag */ - uint32_t Z:1; /*!< bit: 30 Zero condition code flag */ - uint32_t N:1; /*!< bit: 31 Negative condition code flag */ - } b; /*!< Structure used for bit access */ - uint32_t w; /*!< Type used for word access */ -} xPSR_Type; - -/* xPSR Register Definitions */ -#define xPSR_N_Pos 31U /*!< xPSR: N Position */ -#define xPSR_N_Msk (1UL << xPSR_N_Pos) /*!< xPSR: N Mask */ - -#define xPSR_Z_Pos 30U /*!< xPSR: Z Position */ -#define xPSR_Z_Msk (1UL << xPSR_Z_Pos) /*!< xPSR: Z Mask */ - -#define xPSR_C_Pos 29U /*!< xPSR: C Position */ -#define xPSR_C_Msk (1UL << xPSR_C_Pos) /*!< xPSR: C Mask */ - -#define xPSR_V_Pos 28U /*!< xPSR: V Position */ -#define xPSR_V_Msk (1UL << xPSR_V_Pos) /*!< xPSR: V Mask */ - -#define xPSR_T_Pos 24U /*!< xPSR: T Position */ -#define xPSR_T_Msk (1UL << xPSR_T_Pos) /*!< xPSR: T Mask */ - -#define xPSR_ISR_Pos 0U /*!< xPSR: ISR Position */ -#define xPSR_ISR_Msk (0x1FFUL /*<< xPSR_ISR_Pos*/) /*!< xPSR: ISR Mask */ - - -/** - \brief Union type to access the Control Registers (CONTROL). - */ -typedef union -{ - struct - { - uint32_t _reserved0:1; /*!< bit: 0 Reserved */ - uint32_t SPSEL:1; /*!< bit: 1 Stack to be used */ - uint32_t _reserved1:30; /*!< bit: 2..31 Reserved */ - } b; /*!< Structure used for bit access */ - uint32_t w; /*!< Type used for word access */ -} CONTROL_Type; - -/* CONTROL Register Definitions */ -#define CONTROL_SPSEL_Pos 1U /*!< CONTROL: SPSEL Position */ -#define CONTROL_SPSEL_Msk (1UL << CONTROL_SPSEL_Pos) /*!< CONTROL: SPSEL Mask */ - -/*@} end of group CMSIS_CORE */ - - -/** - \ingroup CMSIS_core_register - \defgroup CMSIS_NVIC Nested Vectored Interrupt Controller (NVIC) - \brief Type definitions for the NVIC Registers - @{ - */ - -/** - \brief Structure type to access the Nested Vectored Interrupt Controller (NVIC). - */ -typedef struct -{ - __IOM uint32_t ISER[1U]; /*!< Offset: 0x000 (R/W) Interrupt Set Enable Register */ - uint32_t RESERVED0[31U]; - __IOM uint32_t ICER[1U]; /*!< Offset: 0x080 (R/W) Interrupt Clear Enable Register */ - uint32_t RSERVED1[31U]; - __IOM uint32_t ISPR[1U]; /*!< Offset: 0x100 (R/W) Interrupt Set Pending Register */ - uint32_t RESERVED2[31U]; - __IOM uint32_t ICPR[1U]; /*!< Offset: 0x180 (R/W) Interrupt Clear Pending Register */ - uint32_t RESERVED3[31U]; - uint32_t RESERVED4[64U]; - __IOM uint32_t IP[8U]; /*!< Offset: 0x300 (R/W) Interrupt Priority Register */ -} NVIC_Type; - -/*@} end of group CMSIS_NVIC */ - - -/** - \ingroup CMSIS_core_register - \defgroup CMSIS_SCB System Control Block (SCB) - \brief Type definitions for the System Control Block Registers - @{ - */ - -/** - \brief Structure type to access the System Control Block (SCB). - */ -typedef struct -{ - __IM uint32_t CPUID; /*!< Offset: 0x000 (R/ ) CPUID Base Register */ - __IOM uint32_t ICSR; /*!< Offset: 0x004 (R/W) Interrupt Control and State Register */ - __IOM uint32_t VTOR; /*!< Offset: 0x008 (R/W) Vector Table Offset Register */ - __IOM uint32_t AIRCR; /*!< Offset: 0x00C (R/W) Application Interrupt and Reset Control Register */ - __IOM uint32_t SCR; /*!< Offset: 0x010 (R/W) System Control Register */ - __IOM uint32_t CCR; /*!< Offset: 0x014 (R/W) Configuration Control Register */ - uint32_t RESERVED0[1U]; - __IOM uint32_t SHP[2U]; /*!< Offset: 0x01C (R/W) System Handlers Priority Registers. [0] is RESERVED */ - __IOM uint32_t SHCSR; /*!< Offset: 0x024 (R/W) System Handler Control and State Register */ - uint32_t RESERVED1[154U]; - __IOM uint32_t SFCR; /*!< Offset: 0x290 (R/W) Security Features Control Register */ -} SCB_Type; - -/* SCB CPUID Register Definitions */ -#define SCB_CPUID_IMPLEMENTER_Pos 24U /*!< SCB CPUID: IMPLEMENTER Position */ -#define SCB_CPUID_IMPLEMENTER_Msk (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos) /*!< SCB CPUID: IMPLEMENTER Mask */ - -#define SCB_CPUID_VARIANT_Pos 20U /*!< SCB CPUID: VARIANT Position */ -#define SCB_CPUID_VARIANT_Msk (0xFUL << SCB_CPUID_VARIANT_Pos) /*!< SCB CPUID: VARIANT Mask */ - -#define SCB_CPUID_ARCHITECTURE_Pos 16U /*!< SCB CPUID: ARCHITECTURE Position */ -#define SCB_CPUID_ARCHITECTURE_Msk (0xFUL << SCB_CPUID_ARCHITECTURE_Pos) /*!< SCB CPUID: ARCHITECTURE Mask */ - -#define SCB_CPUID_PARTNO_Pos 4U /*!< SCB CPUID: PARTNO Position */ -#define SCB_CPUID_PARTNO_Msk (0xFFFUL << SCB_CPUID_PARTNO_Pos) /*!< SCB CPUID: PARTNO Mask */ - -#define SCB_CPUID_REVISION_Pos 0U /*!< SCB CPUID: REVISION Position */ -#define SCB_CPUID_REVISION_Msk (0xFUL /*<< SCB_CPUID_REVISION_Pos*/) /*!< SCB CPUID: REVISION Mask */ - -/* SCB Interrupt Control State Register Definitions */ -#define SCB_ICSR_NMIPENDSET_Pos 31U /*!< SCB ICSR: NMIPENDSET Position */ -#define SCB_ICSR_NMIPENDSET_Msk (1UL << SCB_ICSR_NMIPENDSET_Pos) /*!< SCB ICSR: NMIPENDSET Mask */ - -#define SCB_ICSR_PENDSVSET_Pos 28U /*!< SCB ICSR: PENDSVSET Position */ -#define SCB_ICSR_PENDSVSET_Msk (1UL << SCB_ICSR_PENDSVSET_Pos) /*!< SCB ICSR: PENDSVSET Mask */ - -#define SCB_ICSR_PENDSVCLR_Pos 27U /*!< SCB ICSR: PENDSVCLR Position */ -#define SCB_ICSR_PENDSVCLR_Msk (1UL << SCB_ICSR_PENDSVCLR_Pos) /*!< SCB ICSR: PENDSVCLR Mask */ - -#define SCB_ICSR_PENDSTSET_Pos 26U /*!< SCB ICSR: PENDSTSET Position */ -#define SCB_ICSR_PENDSTSET_Msk (1UL << SCB_ICSR_PENDSTSET_Pos) /*!< SCB ICSR: PENDSTSET Mask */ - -#define SCB_ICSR_PENDSTCLR_Pos 25U /*!< SCB ICSR: PENDSTCLR Position */ -#define SCB_ICSR_PENDSTCLR_Msk (1UL << SCB_ICSR_PENDSTCLR_Pos) /*!< SCB ICSR: PENDSTCLR Mask */ - -#define SCB_ICSR_ISRPREEMPT_Pos 23U /*!< SCB ICSR: ISRPREEMPT Position */ -#define SCB_ICSR_ISRPREEMPT_Msk (1UL << SCB_ICSR_ISRPREEMPT_Pos) /*!< SCB ICSR: ISRPREEMPT Mask */ - -#define SCB_ICSR_ISRPENDING_Pos 22U /*!< SCB ICSR: ISRPENDING Position */ -#define SCB_ICSR_ISRPENDING_Msk (1UL << SCB_ICSR_ISRPENDING_Pos) /*!< SCB ICSR: ISRPENDING Mask */ - -#define SCB_ICSR_VECTPENDING_Pos 12U /*!< SCB ICSR: VECTPENDING Position */ -#define SCB_ICSR_VECTPENDING_Msk (0x1FFUL << SCB_ICSR_VECTPENDING_Pos) /*!< SCB ICSR: VECTPENDING Mask */ - -#define SCB_ICSR_VECTACTIVE_Pos 0U /*!< SCB ICSR: VECTACTIVE Position */ -#define SCB_ICSR_VECTACTIVE_Msk (0x1FFUL /*<< SCB_ICSR_VECTACTIVE_Pos*/) /*!< SCB ICSR: VECTACTIVE Mask */ - -/* SCB Interrupt Control State Register Definitions */ -#define SCB_VTOR_TBLOFF_Pos 7U /*!< SCB VTOR: TBLOFF Position */ -#define SCB_VTOR_TBLOFF_Msk (0x1FFFFFFUL << SCB_VTOR_TBLOFF_Pos) /*!< SCB VTOR: TBLOFF Mask */ - -/* SCB Application Interrupt and Reset Control Register Definitions */ -#define SCB_AIRCR_VECTKEY_Pos 16U /*!< SCB AIRCR: VECTKEY Position */ -#define SCB_AIRCR_VECTKEY_Msk (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos) /*!< SCB AIRCR: VECTKEY Mask */ - -#define SCB_AIRCR_VECTKEYSTAT_Pos 16U /*!< SCB AIRCR: VECTKEYSTAT Position */ -#define SCB_AIRCR_VECTKEYSTAT_Msk (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos) /*!< SCB AIRCR: VECTKEYSTAT Mask */ - -#define SCB_AIRCR_ENDIANESS_Pos 15U /*!< SCB AIRCR: ENDIANESS Position */ -#define SCB_AIRCR_ENDIANESS_Msk (1UL << SCB_AIRCR_ENDIANESS_Pos) /*!< SCB AIRCR: ENDIANESS Mask */ - -#define SCB_AIRCR_SYSRESETREQ_Pos 2U /*!< SCB AIRCR: SYSRESETREQ Position */ -#define SCB_AIRCR_SYSRESETREQ_Msk (1UL << SCB_AIRCR_SYSRESETREQ_Pos) /*!< SCB AIRCR: SYSRESETREQ Mask */ - -#define SCB_AIRCR_VECTCLRACTIVE_Pos 1U /*!< SCB AIRCR: VECTCLRACTIVE Position */ -#define SCB_AIRCR_VECTCLRACTIVE_Msk (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos) /*!< SCB AIRCR: VECTCLRACTIVE Mask */ - -/* SCB System Control Register Definitions */ -#define SCB_SCR_SEVONPEND_Pos 4U /*!< SCB SCR: SEVONPEND Position */ -#define SCB_SCR_SEVONPEND_Msk (1UL << SCB_SCR_SEVONPEND_Pos) /*!< SCB SCR: SEVONPEND Mask */ - -#define SCB_SCR_SLEEPDEEP_Pos 2U /*!< SCB SCR: SLEEPDEEP Position */ -#define SCB_SCR_SLEEPDEEP_Msk (1UL << SCB_SCR_SLEEPDEEP_Pos) /*!< SCB SCR: SLEEPDEEP Mask */ - -#define SCB_SCR_SLEEPONEXIT_Pos 1U /*!< SCB SCR: SLEEPONEXIT Position */ -#define SCB_SCR_SLEEPONEXIT_Msk (1UL << SCB_SCR_SLEEPONEXIT_Pos) /*!< SCB SCR: SLEEPONEXIT Mask */ - -/* SCB Configuration Control Register Definitions */ -#define SCB_CCR_STKALIGN_Pos 9U /*!< SCB CCR: STKALIGN Position */ -#define SCB_CCR_STKALIGN_Msk (1UL << SCB_CCR_STKALIGN_Pos) /*!< SCB CCR: STKALIGN Mask */ - -#define SCB_CCR_UNALIGN_TRP_Pos 3U /*!< SCB CCR: UNALIGN_TRP Position */ -#define SCB_CCR_UNALIGN_TRP_Msk (1UL << SCB_CCR_UNALIGN_TRP_Pos) /*!< SCB CCR: UNALIGN_TRP Mask */ - -/* SCB System Handler Control and State Register Definitions */ -#define SCB_SHCSR_SVCALLPENDED_Pos 15U /*!< SCB SHCSR: SVCALLPENDED Position */ -#define SCB_SHCSR_SVCALLPENDED_Msk (1UL << SCB_SHCSR_SVCALLPENDED_Pos) /*!< SCB SHCSR: SVCALLPENDED Mask */ - -/*@} end of group CMSIS_SCB */ - - -/** - \ingroup CMSIS_core_register - \defgroup CMSIS_SCnSCB System Controls not in SCB (SCnSCB) - \brief Type definitions for the System Control and ID Register not in the SCB - @{ - */ - -/** - \brief Structure type to access the System Control and ID Register not in the SCB. - */ -typedef struct -{ - uint32_t RESERVED0[2U]; - __IOM uint32_t ACTLR; /*!< Offset: 0x008 (R/W) Auxiliary Control Register */ -} SCnSCB_Type; - -/* Auxiliary Control Register Definitions */ -#define SCnSCB_ACTLR_DISMCYCINT_Pos 0U /*!< ACTLR: DISMCYCINT Position */ -#define SCnSCB_ACTLR_DISMCYCINT_Msk (1UL /*<< SCnSCB_ACTLR_DISMCYCINT_Pos*/) /*!< ACTLR: DISMCYCINT Mask */ - -/*@} end of group CMSIS_SCnotSCB */ - - -/** - \ingroup CMSIS_core_register - \defgroup CMSIS_SysTick System Tick Timer (SysTick) - \brief Type definitions for the System Timer Registers. - @{ - */ - -/** - \brief Structure type to access the System Timer (SysTick). - */ -typedef struct -{ - __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) SysTick Control and Status Register */ - __IOM uint32_t LOAD; /*!< Offset: 0x004 (R/W) SysTick Reload Value Register */ - __IOM uint32_t VAL; /*!< Offset: 0x008 (R/W) SysTick Current Value Register */ - __IM uint32_t CALIB; /*!< Offset: 0x00C (R/ ) SysTick Calibration Register */ -} SysTick_Type; - -/* SysTick Control / Status Register Definitions */ -#define SysTick_CTRL_COUNTFLAG_Pos 16U /*!< SysTick CTRL: COUNTFLAG Position */ -#define SysTick_CTRL_COUNTFLAG_Msk (1UL << SysTick_CTRL_COUNTFLAG_Pos) /*!< SysTick CTRL: COUNTFLAG Mask */ - -#define SysTick_CTRL_CLKSOURCE_Pos 2U /*!< SysTick CTRL: CLKSOURCE Position */ -#define SysTick_CTRL_CLKSOURCE_Msk (1UL << SysTick_CTRL_CLKSOURCE_Pos) /*!< SysTick CTRL: CLKSOURCE Mask */ - -#define SysTick_CTRL_TICKINT_Pos 1U /*!< SysTick CTRL: TICKINT Position */ -#define SysTick_CTRL_TICKINT_Msk (1UL << SysTick_CTRL_TICKINT_Pos) /*!< SysTick CTRL: TICKINT Mask */ - -#define SysTick_CTRL_ENABLE_Pos 0U /*!< SysTick CTRL: ENABLE Position */ -#define SysTick_CTRL_ENABLE_Msk (1UL /*<< SysTick_CTRL_ENABLE_Pos*/) /*!< SysTick CTRL: ENABLE Mask */ - -/* SysTick Reload Register Definitions */ -#define SysTick_LOAD_RELOAD_Pos 0U /*!< SysTick LOAD: RELOAD Position */ -#define SysTick_LOAD_RELOAD_Msk (0xFFFFFFUL /*<< SysTick_LOAD_RELOAD_Pos*/) /*!< SysTick LOAD: RELOAD Mask */ - -/* SysTick Current Register Definitions */ -#define SysTick_VAL_CURRENT_Pos 0U /*!< SysTick VAL: CURRENT Position */ -#define SysTick_VAL_CURRENT_Msk (0xFFFFFFUL /*<< SysTick_VAL_CURRENT_Pos*/) /*!< SysTick VAL: CURRENT Mask */ - -/* SysTick Calibration Register Definitions */ -#define SysTick_CALIB_NOREF_Pos 31U /*!< SysTick CALIB: NOREF Position */ -#define SysTick_CALIB_NOREF_Msk (1UL << SysTick_CALIB_NOREF_Pos) /*!< SysTick CALIB: NOREF Mask */ - -#define SysTick_CALIB_SKEW_Pos 30U /*!< SysTick CALIB: SKEW Position */ -#define SysTick_CALIB_SKEW_Msk (1UL << SysTick_CALIB_SKEW_Pos) /*!< SysTick CALIB: SKEW Mask */ - -#define SysTick_CALIB_TENMS_Pos 0U /*!< SysTick CALIB: TENMS Position */ -#define SysTick_CALIB_TENMS_Msk (0xFFFFFFUL /*<< SysTick_CALIB_TENMS_Pos*/) /*!< SysTick CALIB: TENMS Mask */ - -/*@} end of group CMSIS_SysTick */ - -#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) -/** - \ingroup CMSIS_core_register - \defgroup CMSIS_MPU Memory Protection Unit (MPU) - \brief Type definitions for the Memory Protection Unit (MPU) - @{ - */ - -/** - \brief Structure type to access the Memory Protection Unit (MPU). - */ -typedef struct -{ - __IM uint32_t TYPE; /*!< Offset: 0x000 (R/ ) MPU Type Register */ - __IOM uint32_t CTRL; /*!< Offset: 0x004 (R/W) MPU Control Register */ - __IOM uint32_t RNR; /*!< Offset: 0x008 (R/W) MPU Region RNRber Register */ - __IOM uint32_t RBAR; /*!< Offset: 0x00C (R/W) MPU Region Base Address Register */ - __IOM uint32_t RASR; /*!< Offset: 0x010 (R/W) MPU Region Attribute and Size Register */ -} MPU_Type; - -/* MPU Type Register Definitions */ -#define MPU_TYPE_IREGION_Pos 16U /*!< MPU TYPE: IREGION Position */ -#define MPU_TYPE_IREGION_Msk (0xFFUL << MPU_TYPE_IREGION_Pos) /*!< MPU TYPE: IREGION Mask */ - -#define MPU_TYPE_DREGION_Pos 8U /*!< MPU TYPE: DREGION Position */ -#define MPU_TYPE_DREGION_Msk (0xFFUL << MPU_TYPE_DREGION_Pos) /*!< MPU TYPE: DREGION Mask */ - -#define MPU_TYPE_SEPARATE_Pos 0U /*!< MPU TYPE: SEPARATE Position */ -#define MPU_TYPE_SEPARATE_Msk (1UL /*<< MPU_TYPE_SEPARATE_Pos*/) /*!< MPU TYPE: SEPARATE Mask */ - -/* MPU Control Register Definitions */ -#define MPU_CTRL_PRIVDEFENA_Pos 2U /*!< MPU CTRL: PRIVDEFENA Position */ -#define MPU_CTRL_PRIVDEFENA_Msk (1UL << MPU_CTRL_PRIVDEFENA_Pos) /*!< MPU CTRL: PRIVDEFENA Mask */ - -#define MPU_CTRL_HFNMIENA_Pos 1U /*!< MPU CTRL: HFNMIENA Position */ -#define MPU_CTRL_HFNMIENA_Msk (1UL << MPU_CTRL_HFNMIENA_Pos) /*!< MPU CTRL: HFNMIENA Mask */ - -#define MPU_CTRL_ENABLE_Pos 0U /*!< MPU CTRL: ENABLE Position */ -#define MPU_CTRL_ENABLE_Msk (1UL /*<< MPU_CTRL_ENABLE_Pos*/) /*!< MPU CTRL: ENABLE Mask */ - -/* MPU Region Number Register Definitions */ -#define MPU_RNR_REGION_Pos 0U /*!< MPU RNR: REGION Position */ -#define MPU_RNR_REGION_Msk (0xFFUL /*<< MPU_RNR_REGION_Pos*/) /*!< MPU RNR: REGION Mask */ - -/* MPU Region Base Address Register Definitions */ -#define MPU_RBAR_ADDR_Pos 8U /*!< MPU RBAR: ADDR Position */ -#define MPU_RBAR_ADDR_Msk (0xFFFFFFUL << MPU_RBAR_ADDR_Pos) /*!< MPU RBAR: ADDR Mask */ - -#define MPU_RBAR_VALID_Pos 4U /*!< MPU RBAR: VALID Position */ -#define MPU_RBAR_VALID_Msk (1UL << MPU_RBAR_VALID_Pos) /*!< MPU RBAR: VALID Mask */ - -#define MPU_RBAR_REGION_Pos 0U /*!< MPU RBAR: REGION Position */ -#define MPU_RBAR_REGION_Msk (0xFUL /*<< MPU_RBAR_REGION_Pos*/) /*!< MPU RBAR: REGION Mask */ - -/* MPU Region Attribute and Size Register Definitions */ -#define MPU_RASR_ATTRS_Pos 16U /*!< MPU RASR: MPU Region Attribute field Position */ -#define MPU_RASR_ATTRS_Msk (0xFFFFUL << MPU_RASR_ATTRS_Pos) /*!< MPU RASR: MPU Region Attribute field Mask */ - -#define MPU_RASR_XN_Pos 28U /*!< MPU RASR: ATTRS.XN Position */ -#define MPU_RASR_XN_Msk (1UL << MPU_RASR_XN_Pos) /*!< MPU RASR: ATTRS.XN Mask */ - -#define MPU_RASR_AP_Pos 24U /*!< MPU RASR: ATTRS.AP Position */ -#define MPU_RASR_AP_Msk (0x7UL << MPU_RASR_AP_Pos) /*!< MPU RASR: ATTRS.AP Mask */ - -#define MPU_RASR_TEX_Pos 19U /*!< MPU RASR: ATTRS.TEX Position */ -#define MPU_RASR_TEX_Msk (0x7UL << MPU_RASR_TEX_Pos) /*!< MPU RASR: ATTRS.TEX Mask */ - -#define MPU_RASR_S_Pos 18U /*!< MPU RASR: ATTRS.S Position */ -#define MPU_RASR_S_Msk (1UL << MPU_RASR_S_Pos) /*!< MPU RASR: ATTRS.S Mask */ - -#define MPU_RASR_C_Pos 17U /*!< MPU RASR: ATTRS.C Position */ -#define MPU_RASR_C_Msk (1UL << MPU_RASR_C_Pos) /*!< MPU RASR: ATTRS.C Mask */ - -#define MPU_RASR_B_Pos 16U /*!< MPU RASR: ATTRS.B Position */ -#define MPU_RASR_B_Msk (1UL << MPU_RASR_B_Pos) /*!< MPU RASR: ATTRS.B Mask */ - -#define MPU_RASR_SRD_Pos 8U /*!< MPU RASR: Sub-Region Disable Position */ -#define MPU_RASR_SRD_Msk (0xFFUL << MPU_RASR_SRD_Pos) /*!< MPU RASR: Sub-Region Disable Mask */ - -#define MPU_RASR_SIZE_Pos 1U /*!< MPU RASR: Region Size Field Position */ -#define MPU_RASR_SIZE_Msk (0x1FUL << MPU_RASR_SIZE_Pos) /*!< MPU RASR: Region Size Field Mask */ - -#define MPU_RASR_ENABLE_Pos 0U /*!< MPU RASR: Region enable bit Position */ -#define MPU_RASR_ENABLE_Msk (1UL /*<< MPU_RASR_ENABLE_Pos*/) /*!< MPU RASR: Region enable bit Disable Mask */ - -/*@} end of group CMSIS_MPU */ -#endif - - -/** - \ingroup CMSIS_core_register - \defgroup CMSIS_CoreDebug Core Debug Registers (CoreDebug) - \brief SC000 Core Debug Registers (DCB registers, SHCSR, and DFSR) are only accessible over DAP and not via processor. - Therefore they are not covered by the SC000 header file. - @{ - */ -/*@} end of group CMSIS_CoreDebug */ - - -/** - \ingroup CMSIS_core_register - \defgroup CMSIS_core_bitfield Core register bit field macros - \brief Macros for use with bit field definitions (xxx_Pos, xxx_Msk). - @{ - */ - -/** - \brief Mask and shift a bit field value for use in a register bit range. - \param[in] field Name of the register bit field. - \param[in] value Value of the bit field. This parameter is interpreted as an uint32_t type. - \return Masked and shifted value. -*/ -#define _VAL2FLD(field, value) (((uint32_t)(value) << field ## _Pos) & field ## _Msk) - -/** - \brief Mask and shift a register value to extract a bit filed value. - \param[in] field Name of the register bit field. - \param[in] value Value of register. This parameter is interpreted as an uint32_t type. - \return Masked and shifted bit field value. -*/ -#define _FLD2VAL(field, value) (((uint32_t)(value) & field ## _Msk) >> field ## _Pos) - -/*@} end of group CMSIS_core_bitfield */ - - -/** - \ingroup CMSIS_core_register - \defgroup CMSIS_core_base Core Definitions - \brief Definitions for base addresses, unions, and structures. - @{ - */ - -/* Memory mapping of Core Hardware */ -#define SCS_BASE (0xE000E000UL) /*!< System Control Space Base Address */ -#define SysTick_BASE (SCS_BASE + 0x0010UL) /*!< SysTick Base Address */ -#define NVIC_BASE (SCS_BASE + 0x0100UL) /*!< NVIC Base Address */ -#define SCB_BASE (SCS_BASE + 0x0D00UL) /*!< System Control Block Base Address */ - -#define SCnSCB ((SCnSCB_Type *) SCS_BASE ) /*!< System control Register not in SCB */ -#define SCB ((SCB_Type *) SCB_BASE ) /*!< SCB configuration struct */ -#define SysTick ((SysTick_Type *) SysTick_BASE ) /*!< SysTick configuration struct */ -#define NVIC ((NVIC_Type *) NVIC_BASE ) /*!< NVIC configuration struct */ - -#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) - #define MPU_BASE (SCS_BASE + 0x0D90UL) /*!< Memory Protection Unit */ - #define MPU ((MPU_Type *) MPU_BASE ) /*!< Memory Protection Unit */ -#endif - -/*@} */ - - - -/******************************************************************************* - * Hardware Abstraction Layer - Core Function Interface contains: - - Core NVIC Functions - - Core SysTick Functions - - Core Register Access Functions - ******************************************************************************/ -/** - \defgroup CMSIS_Core_FunctionInterface Functions and Instructions Reference -*/ - - - -/* ########################## NVIC functions #################################### */ -/** - \ingroup CMSIS_Core_FunctionInterface - \defgroup CMSIS_Core_NVICFunctions NVIC Functions - \brief Functions that manage interrupts and exceptions via the NVIC. - @{ - */ - -#ifdef CMSIS_NVIC_VIRTUAL - #ifndef CMSIS_NVIC_VIRTUAL_HEADER_FILE - #define CMSIS_NVIC_VIRTUAL_HEADER_FILE "cmsis_nvic_virtual.h" - #endif - #include CMSIS_NVIC_VIRTUAL_HEADER_FILE -#else -/*#define NVIC_SetPriorityGrouping __NVIC_SetPriorityGrouping not available for SC000 */ -/*#define NVIC_GetPriorityGrouping __NVIC_GetPriorityGrouping not available for SC000 */ - #define NVIC_EnableIRQ __NVIC_EnableIRQ - #define NVIC_GetEnableIRQ __NVIC_GetEnableIRQ - #define NVIC_DisableIRQ __NVIC_DisableIRQ - #define NVIC_GetPendingIRQ __NVIC_GetPendingIRQ - #define NVIC_SetPendingIRQ __NVIC_SetPendingIRQ - #define NVIC_ClearPendingIRQ __NVIC_ClearPendingIRQ -/*#define NVIC_GetActive __NVIC_GetActive not available for SC000 */ - #define NVIC_SetPriority __NVIC_SetPriority - #define NVIC_GetPriority __NVIC_GetPriority - #define NVIC_SystemReset __NVIC_SystemReset -#endif /* CMSIS_NVIC_VIRTUAL */ - -#ifdef CMSIS_VECTAB_VIRTUAL - #ifndef CMSIS_VECTAB_VIRTUAL_HEADER_FILE - #define CMSIS_VECTAB_VIRTUAL_HEADER_FILE "cmsis_vectab_virtual.h" - #endif - #include CMSIS_VECTAB_VIRTUAL_HEADER_FILE -#else - #define NVIC_SetVector __NVIC_SetVector - #define NVIC_GetVector __NVIC_GetVector -#endif /* (CMSIS_VECTAB_VIRTUAL) */ - -#define NVIC_USER_IRQ_OFFSET 16 - - -/* Interrupt Priorities are WORD accessible only under Armv6-M */ -/* The following MACROS handle generation of the register offset and byte masks */ -#define _BIT_SHIFT(IRQn) ( ((((uint32_t)(int32_t)(IRQn)) ) & 0x03UL) * 8UL) -#define _SHP_IDX(IRQn) ( (((((uint32_t)(int32_t)(IRQn)) & 0x0FUL)-8UL) >> 2UL) ) -#define _IP_IDX(IRQn) ( (((uint32_t)(int32_t)(IRQn)) >> 2UL) ) - - -/** - \brief Enable Interrupt - \details Enables a device specific interrupt in the NVIC interrupt controller. - \param [in] IRQn Device specific interrupt number. - \note IRQn must not be negative. - */ -__STATIC_INLINE void __NVIC_EnableIRQ(IRQn_Type IRQn) -{ - if ((int32_t)(IRQn) >= 0) - { - NVIC->ISER[0U] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); - } -} - - -/** - \brief Get Interrupt Enable status - \details Returns a device specific interrupt enable status from the NVIC interrupt controller. - \param [in] IRQn Device specific interrupt number. - \return 0 Interrupt is not enabled. - \return 1 Interrupt is enabled. - \note IRQn must not be negative. - */ -__STATIC_INLINE uint32_t __NVIC_GetEnableIRQ(IRQn_Type IRQn) -{ - if ((int32_t)(IRQn) >= 0) - { - return((uint32_t)(((NVIC->ISER[0U] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); - } - else - { - return(0U); - } -} - - -/** - \brief Disable Interrupt - \details Disables a device specific interrupt in the NVIC interrupt controller. - \param [in] IRQn Device specific interrupt number. - \note IRQn must not be negative. - */ -__STATIC_INLINE void __NVIC_DisableIRQ(IRQn_Type IRQn) -{ - if ((int32_t)(IRQn) >= 0) - { - NVIC->ICER[0U] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); - __DSB(); - __ISB(); - } -} - - -/** - \brief Get Pending Interrupt - \details Reads the NVIC pending register and returns the pending bit for the specified device specific interrupt. - \param [in] IRQn Device specific interrupt number. - \return 0 Interrupt status is not pending. - \return 1 Interrupt status is pending. - \note IRQn must not be negative. - */ -__STATIC_INLINE uint32_t __NVIC_GetPendingIRQ(IRQn_Type IRQn) -{ - if ((int32_t)(IRQn) >= 0) - { - return((uint32_t)(((NVIC->ISPR[0U] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); - } - else - { - return(0U); - } -} - - -/** - \brief Set Pending Interrupt - \details Sets the pending bit of a device specific interrupt in the NVIC pending register. - \param [in] IRQn Device specific interrupt number. - \note IRQn must not be negative. - */ -__STATIC_INLINE void __NVIC_SetPendingIRQ(IRQn_Type IRQn) -{ - if ((int32_t)(IRQn) >= 0) - { - NVIC->ISPR[0U] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); - } -} - - -/** - \brief Clear Pending Interrupt - \details Clears the pending bit of a device specific interrupt in the NVIC pending register. - \param [in] IRQn Device specific interrupt number. - \note IRQn must not be negative. - */ -__STATIC_INLINE void __NVIC_ClearPendingIRQ(IRQn_Type IRQn) -{ - if ((int32_t)(IRQn) >= 0) - { - NVIC->ICPR[0U] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); - } -} - - -/** - \brief Set Interrupt Priority - \details Sets the priority of a device specific interrupt or a processor exception. - The interrupt number can be positive to specify a device specific interrupt, - or negative to specify a processor exception. - \param [in] IRQn Interrupt number. - \param [in] priority Priority to set. - \note The priority cannot be set for every processor exception. - */ -__STATIC_INLINE void __NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority) -{ - if ((int32_t)(IRQn) >= 0) - { - NVIC->IP[_IP_IDX(IRQn)] = ((uint32_t)(NVIC->IP[_IP_IDX(IRQn)] & ~(0xFFUL << _BIT_SHIFT(IRQn))) | - (((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL) << _BIT_SHIFT(IRQn))); - } - else - { - SCB->SHP[_SHP_IDX(IRQn)] = ((uint32_t)(SCB->SHP[_SHP_IDX(IRQn)] & ~(0xFFUL << _BIT_SHIFT(IRQn))) | - (((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL) << _BIT_SHIFT(IRQn))); - } -} - - -/** - \brief Get Interrupt Priority - \details Reads the priority of a device specific interrupt or a processor exception. - The interrupt number can be positive to specify a device specific interrupt, - or negative to specify a processor exception. - \param [in] IRQn Interrupt number. - \return Interrupt Priority. - Value is aligned automatically to the implemented priority bits of the microcontroller. - */ -__STATIC_INLINE uint32_t __NVIC_GetPriority(IRQn_Type IRQn) -{ - - if ((int32_t)(IRQn) >= 0) - { - return((uint32_t)(((NVIC->IP[ _IP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) & (uint32_t)0xFFUL) >> (8U - __NVIC_PRIO_BITS))); - } - else - { - return((uint32_t)(((SCB->SHP[_SHP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) & (uint32_t)0xFFUL) >> (8U - __NVIC_PRIO_BITS))); - } -} - - -/** - \brief Set Interrupt Vector - \details Sets an interrupt vector in SRAM based interrupt vector table. - The interrupt number can be positive to specify a device specific interrupt, - or negative to specify a processor exception. - VTOR must been relocated to SRAM before. - \param [in] IRQn Interrupt number - \param [in] vector Address of interrupt handler function - */ -__STATIC_INLINE void __NVIC_SetVector(IRQn_Type IRQn, uint32_t vector) -{ - uint32_t *vectors = (uint32_t *)SCB->VTOR; - vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET] = vector; -} - - -/** - \brief Get Interrupt Vector - \details Reads an interrupt vector from interrupt vector table. - The interrupt number can be positive to specify a device specific interrupt, - or negative to specify a processor exception. - \param [in] IRQn Interrupt number. - \return Address of interrupt handler function - */ -__STATIC_INLINE uint32_t __NVIC_GetVector(IRQn_Type IRQn) -{ - uint32_t *vectors = (uint32_t *)SCB->VTOR; - return vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET]; -} - - -/** - \brief System Reset - \details Initiates a system reset request to reset the MCU. - */ -__STATIC_INLINE void __NVIC_SystemReset(void) -{ - __DSB(); /* Ensure all outstanding memory accesses included - buffered write are completed before reset */ - SCB->AIRCR = ((0x5FAUL << SCB_AIRCR_VECTKEY_Pos) | - SCB_AIRCR_SYSRESETREQ_Msk); - __DSB(); /* Ensure completion of memory access */ - - for(;;) /* wait until reset */ - { - __NOP(); - } -} - -/*@} end of CMSIS_Core_NVICFunctions */ - - -/* ########################## FPU functions #################################### */ -/** - \ingroup CMSIS_Core_FunctionInterface - \defgroup CMSIS_Core_FpuFunctions FPU Functions - \brief Function that provides FPU type. - @{ - */ - -/** - \brief get FPU type - \details returns the FPU type - \returns - - \b 0: No FPU - - \b 1: Single precision FPU - - \b 2: Double + Single precision FPU - */ -__STATIC_INLINE uint32_t SCB_GetFPUType(void) -{ - return 0U; /* No FPU */ -} - - -/*@} end of CMSIS_Core_FpuFunctions */ - - - -/* ################################## SysTick function ############################################ */ -/** - \ingroup CMSIS_Core_FunctionInterface - \defgroup CMSIS_Core_SysTickFunctions SysTick Functions - \brief Functions that configure the System. - @{ - */ - -#if defined (__Vendor_SysTickConfig) && (__Vendor_SysTickConfig == 0U) - -/** - \brief System Tick Configuration - \details Initializes the System Timer and its interrupt, and starts the System Tick Timer. - Counter is in free running mode to generate periodic interrupts. - \param [in] ticks Number of ticks between two interrupts. - \return 0 Function succeeded. - \return 1 Function failed. - \note When the variable __Vendor_SysTickConfig is set to 1, then the - function SysTick_Config is not included. In this case, the file device.h - must contain a vendor-specific implementation of this function. - */ -__STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks) -{ - if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk) - { - return (1UL); /* Reload value impossible */ - } - - SysTick->LOAD = (uint32_t)(ticks - 1UL); /* set reload register */ - NVIC_SetPriority (SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */ - SysTick->VAL = 0UL; /* Load the SysTick Counter Value */ - SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk | - SysTick_CTRL_TICKINT_Msk | - SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */ - return (0UL); /* Function successful */ -} - -#endif - -/*@} end of CMSIS_Core_SysTickFunctions */ - - - - -#ifdef __cplusplus -} -#endif - -#endif /* __CORE_SC000_H_DEPENDANT */ - -#endif /* __CMSIS_GENERIC */ diff --git a/bsp/essemi/es32f0271/libraries/CMSIS/Include/core_sc300.h b/bsp/essemi/es32f0271/libraries/CMSIS/Include/core_sc300.h deleted file mode 100644 index a569ef2ace..0000000000 --- a/bsp/essemi/es32f0271/libraries/CMSIS/Include/core_sc300.h +++ /dev/null @@ -1,1903 +0,0 @@ -/**************************************************************************//** - * @file core_sc300.h - * @brief CMSIS SC300 Core Peripheral Access Layer Header File - * @version V5.0.3 - * @date 10. January 2018 - ******************************************************************************/ -/* - * Copyright (c) 2009-2018 Arm Limited. All rights reserved. - * - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed under the Apache License, Version 2.0 (the License); you may - * not use this file except in compliance with the License. - * You may obtain a copy of the License at - * - * www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an AS IS BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - */ - -#if defined ( __ICCARM__ ) - #pragma system_include /* treat file as system include file for MISRA check */ -#elif defined (__clang__) - #pragma clang system_header /* treat file as system include file */ -#endif - -#ifndef __CORE_SC300_H_GENERIC -#define __CORE_SC300_H_GENERIC - -#include - -#ifdef __cplusplus - extern "C" { -#endif - -/** - \page CMSIS_MISRA_Exceptions MISRA-C:2004 Compliance Exceptions - CMSIS violates the following MISRA-C:2004 rules: - - \li Required Rule 8.5, object/function definition in header file.
- Function definitions in header files are used to allow 'inlining'. - - \li Required Rule 18.4, declaration of union type or object of union type: '{...}'.
- Unions are used for effective representation of core registers. - - \li Advisory Rule 19.7, Function-like macro defined.
- Function-like macros are used to allow more efficient code. - */ - - -/******************************************************************************* - * CMSIS definitions - ******************************************************************************/ -/** - \ingroup SC3000 - @{ - */ - -#include "cmsis_version.h" - -/* CMSIS SC300 definitions */ -#define __SC300_CMSIS_VERSION_MAIN (__CM_CMSIS_VERSION_MAIN) /*!< \deprecated [31:16] CMSIS HAL main version */ -#define __SC300_CMSIS_VERSION_SUB (__CM_CMSIS_VERSION_SUB) /*!< \deprecated [15:0] CMSIS HAL sub version */ -#define __SC300_CMSIS_VERSION ((__SC300_CMSIS_VERSION_MAIN << 16U) | \ - __SC300_CMSIS_VERSION_SUB ) /*!< \deprecated CMSIS HAL version number */ - -#define __CORTEX_SC (300U) /*!< Cortex secure core */ - -/** __FPU_USED indicates whether an FPU is used or not. - This core does not support an FPU at all -*/ -#define __FPU_USED 0U - -#if defined ( __CC_ARM ) - #if defined __TARGET_FPU_VFP - #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" - #endif - -#elif defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) - #if defined __ARM_PCS_VFP - #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" - #endif - -#elif defined ( __GNUC__ ) - #if defined (__VFP_FP__) && !defined(__SOFTFP__) - #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" - #endif - -#elif defined ( __ICCARM__ ) - #if defined __ARMVFP__ - #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" - #endif - -#elif defined ( __TI_ARM__ ) - #if defined __TI_VFP_SUPPORT__ - #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" - #endif - -#elif defined ( __TASKING__ ) - #if defined __FPU_VFP__ - #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" - #endif - -#elif defined ( __CSMC__ ) - #if ( __CSMC__ & 0x400U) - #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" - #endif - -#endif - -#include "cmsis_compiler.h" /* CMSIS compiler specific defines */ - - -#ifdef __cplusplus -} -#endif - -#endif /* __CORE_SC300_H_GENERIC */ - -#ifndef __CMSIS_GENERIC - -#ifndef __CORE_SC300_H_DEPENDANT -#define __CORE_SC300_H_DEPENDANT - -#ifdef __cplusplus - extern "C" { -#endif - -/* check device defines and use defaults */ -#if defined __CHECK_DEVICE_DEFINES - #ifndef __SC300_REV - #define __SC300_REV 0x0000U - #warning "__SC300_REV not defined in device header file; using default!" - #endif - - #ifndef __MPU_PRESENT - #define __MPU_PRESENT 0U - #warning "__MPU_PRESENT not defined in device header file; using default!" - #endif - - #ifndef __NVIC_PRIO_BITS - #define __NVIC_PRIO_BITS 3U - #warning "__NVIC_PRIO_BITS not defined in device header file; using default!" - #endif - - #ifndef __Vendor_SysTickConfig - #define __Vendor_SysTickConfig 0U - #warning "__Vendor_SysTickConfig not defined in device header file; using default!" - #endif -#endif - -/* IO definitions (access restrictions to peripheral registers) */ -/** - \defgroup CMSIS_glob_defs CMSIS Global Defines - - IO Type Qualifiers are used - \li to specify the access to peripheral variables. - \li for automatic generation of peripheral register debug information. -*/ -#ifdef __cplusplus - #define __I volatile /*!< Defines 'read only' permissions */ -#else - #define __I volatile const /*!< Defines 'read only' permissions */ -#endif -#define __O volatile /*!< Defines 'write only' permissions */ -#define __IO volatile /*!< Defines 'read / write' permissions */ - -/* following defines should be used for structure members */ -#define __IM volatile const /*! Defines 'read only' structure member permissions */ -#define __OM volatile /*! Defines 'write only' structure member permissions */ -#define __IOM volatile /*! Defines 'read / write' structure member permissions */ - -/*@} end of group SC300 */ - - - -/******************************************************************************* - * Register Abstraction - Core Register contain: - - Core Register - - Core NVIC Register - - Core SCB Register - - Core SysTick Register - - Core Debug Register - - Core MPU Register - ******************************************************************************/ -/** - \defgroup CMSIS_core_register Defines and Type Definitions - \brief Type definitions and defines for Cortex-M processor based devices. -*/ - -/** - \ingroup CMSIS_core_register - \defgroup CMSIS_CORE Status and Control Registers - \brief Core Register type definitions. - @{ - */ - -/** - \brief Union type to access the Application Program Status Register (APSR). - */ -typedef union -{ - struct - { - uint32_t _reserved0:27; /*!< bit: 0..26 Reserved */ - uint32_t Q:1; /*!< bit: 27 Saturation condition flag */ - uint32_t V:1; /*!< bit: 28 Overflow condition code flag */ - uint32_t C:1; /*!< bit: 29 Carry condition code flag */ - uint32_t Z:1; /*!< bit: 30 Zero condition code flag */ - uint32_t N:1; /*!< bit: 31 Negative condition code flag */ - } b; /*!< Structure used for bit access */ - uint32_t w; /*!< Type used for word access */ -} APSR_Type; - -/* APSR Register Definitions */ -#define APSR_N_Pos 31U /*!< APSR: N Position */ -#define APSR_N_Msk (1UL << APSR_N_Pos) /*!< APSR: N Mask */ - -#define APSR_Z_Pos 30U /*!< APSR: Z Position */ -#define APSR_Z_Msk (1UL << APSR_Z_Pos) /*!< APSR: Z Mask */ - -#define APSR_C_Pos 29U /*!< APSR: C Position */ -#define APSR_C_Msk (1UL << APSR_C_Pos) /*!< APSR: C Mask */ - -#define APSR_V_Pos 28U /*!< APSR: V Position */ -#define APSR_V_Msk (1UL << APSR_V_Pos) /*!< APSR: V Mask */ - -#define APSR_Q_Pos 27U /*!< APSR: Q Position */ -#define APSR_Q_Msk (1UL << APSR_Q_Pos) /*!< APSR: Q Mask */ - - -/** - \brief Union type to access the Interrupt Program Status Register (IPSR). - */ -typedef union -{ - struct - { - uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */ - uint32_t _reserved0:23; /*!< bit: 9..31 Reserved */ - } b; /*!< Structure used for bit access */ - uint32_t w; /*!< Type used for word access */ -} IPSR_Type; - -/* IPSR Register Definitions */ -#define IPSR_ISR_Pos 0U /*!< IPSR: ISR Position */ -#define IPSR_ISR_Msk (0x1FFUL /*<< IPSR_ISR_Pos*/) /*!< IPSR: ISR Mask */ - - -/** - \brief Union type to access the Special-Purpose Program Status Registers (xPSR). - */ -typedef union -{ - struct - { - uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */ - uint32_t _reserved0:1; /*!< bit: 9 Reserved */ - uint32_t ICI_IT_1:6; /*!< bit: 10..15 ICI/IT part 1 */ - uint32_t _reserved1:8; /*!< bit: 16..23 Reserved */ - uint32_t T:1; /*!< bit: 24 Thumb bit */ - uint32_t ICI_IT_2:2; /*!< bit: 25..26 ICI/IT part 2 */ - uint32_t Q:1; /*!< bit: 27 Saturation condition flag */ - uint32_t V:1; /*!< bit: 28 Overflow condition code flag */ - uint32_t C:1; /*!< bit: 29 Carry condition code flag */ - uint32_t Z:1; /*!< bit: 30 Zero condition code flag */ - uint32_t N:1; /*!< bit: 31 Negative condition code flag */ - } b; /*!< Structure used for bit access */ - uint32_t w; /*!< Type used for word access */ -} xPSR_Type; - -/* xPSR Register Definitions */ -#define xPSR_N_Pos 31U /*!< xPSR: N Position */ -#define xPSR_N_Msk (1UL << xPSR_N_Pos) /*!< xPSR: N Mask */ - -#define xPSR_Z_Pos 30U /*!< xPSR: Z Position */ -#define xPSR_Z_Msk (1UL << xPSR_Z_Pos) /*!< xPSR: Z Mask */ - -#define xPSR_C_Pos 29U /*!< xPSR: C Position */ -#define xPSR_C_Msk (1UL << xPSR_C_Pos) /*!< xPSR: C Mask */ - -#define xPSR_V_Pos 28U /*!< xPSR: V Position */ -#define xPSR_V_Msk (1UL << xPSR_V_Pos) /*!< xPSR: V Mask */ - -#define xPSR_Q_Pos 27U /*!< xPSR: Q Position */ -#define xPSR_Q_Msk (1UL << xPSR_Q_Pos) /*!< xPSR: Q Mask */ - -#define xPSR_ICI_IT_2_Pos 25U /*!< xPSR: ICI/IT part 2 Position */ -#define xPSR_ICI_IT_2_Msk (3UL << xPSR_ICI_IT_2_Pos) /*!< xPSR: ICI/IT part 2 Mask */ - -#define xPSR_T_Pos 24U /*!< xPSR: T Position */ -#define xPSR_T_Msk (1UL << xPSR_T_Pos) /*!< xPSR: T Mask */ - -#define xPSR_ICI_IT_1_Pos 10U /*!< xPSR: ICI/IT part 1 Position */ -#define xPSR_ICI_IT_1_Msk (0x3FUL << xPSR_ICI_IT_1_Pos) /*!< xPSR: ICI/IT part 1 Mask */ - -#define xPSR_ISR_Pos 0U /*!< xPSR: ISR Position */ -#define xPSR_ISR_Msk (0x1FFUL /*<< xPSR_ISR_Pos*/) /*!< xPSR: ISR Mask */ - - -/** - \brief Union type to access the Control Registers (CONTROL). - */ -typedef union -{ - struct - { - uint32_t nPRIV:1; /*!< bit: 0 Execution privilege in Thread mode */ - uint32_t SPSEL:1; /*!< bit: 1 Stack to be used */ - uint32_t _reserved1:30; /*!< bit: 2..31 Reserved */ - } b; /*!< Structure used for bit access */ - uint32_t w; /*!< Type used for word access */ -} CONTROL_Type; - -/* CONTROL Register Definitions */ -#define CONTROL_SPSEL_Pos 1U /*!< CONTROL: SPSEL Position */ -#define CONTROL_SPSEL_Msk (1UL << CONTROL_SPSEL_Pos) /*!< CONTROL: SPSEL Mask */ - -#define CONTROL_nPRIV_Pos 0U /*!< CONTROL: nPRIV Position */ -#define CONTROL_nPRIV_Msk (1UL /*<< CONTROL_nPRIV_Pos*/) /*!< CONTROL: nPRIV Mask */ - -/*@} end of group CMSIS_CORE */ - - -/** - \ingroup CMSIS_core_register - \defgroup CMSIS_NVIC Nested Vectored Interrupt Controller (NVIC) - \brief Type definitions for the NVIC Registers - @{ - */ - -/** - \brief Structure type to access the Nested Vectored Interrupt Controller (NVIC). - */ -typedef struct -{ - __IOM uint32_t ISER[8U]; /*!< Offset: 0x000 (R/W) Interrupt Set Enable Register */ - uint32_t RESERVED0[24U]; - __IOM uint32_t ICER[8U]; /*!< Offset: 0x080 (R/W) Interrupt Clear Enable Register */ - uint32_t RSERVED1[24U]; - __IOM uint32_t ISPR[8U]; /*!< Offset: 0x100 (R/W) Interrupt Set Pending Register */ - uint32_t RESERVED2[24U]; - __IOM uint32_t ICPR[8U]; /*!< Offset: 0x180 (R/W) Interrupt Clear Pending Register */ - uint32_t RESERVED3[24U]; - __IOM uint32_t IABR[8U]; /*!< Offset: 0x200 (R/W) Interrupt Active bit Register */ - uint32_t RESERVED4[56U]; - __IOM uint8_t IP[240U]; /*!< Offset: 0x300 (R/W) Interrupt Priority Register (8Bit wide) */ - uint32_t RESERVED5[644U]; - __OM uint32_t STIR; /*!< Offset: 0xE00 ( /W) Software Trigger Interrupt Register */ -} NVIC_Type; - -/* Software Triggered Interrupt Register Definitions */ -#define NVIC_STIR_INTID_Pos 0U /*!< STIR: INTLINESNUM Position */ -#define NVIC_STIR_INTID_Msk (0x1FFUL /*<< NVIC_STIR_INTID_Pos*/) /*!< STIR: INTLINESNUM Mask */ - -/*@} end of group CMSIS_NVIC */ - - -/** - \ingroup CMSIS_core_register - \defgroup CMSIS_SCB System Control Block (SCB) - \brief Type definitions for the System Control Block Registers - @{ - */ - -/** - \brief Structure type to access the System Control Block (SCB). - */ -typedef struct -{ - __IM uint32_t CPUID; /*!< Offset: 0x000 (R/ ) CPUID Base Register */ - __IOM uint32_t ICSR; /*!< Offset: 0x004 (R/W) Interrupt Control and State Register */ - __IOM uint32_t VTOR; /*!< Offset: 0x008 (R/W) Vector Table Offset Register */ - __IOM uint32_t AIRCR; /*!< Offset: 0x00C (R/W) Application Interrupt and Reset Control Register */ - __IOM uint32_t SCR; /*!< Offset: 0x010 (R/W) System Control Register */ - __IOM uint32_t CCR; /*!< Offset: 0x014 (R/W) Configuration Control Register */ - __IOM uint8_t SHP[12U]; /*!< Offset: 0x018 (R/W) System Handlers Priority Registers (4-7, 8-11, 12-15) */ - __IOM uint32_t SHCSR; /*!< Offset: 0x024 (R/W) System Handler Control and State Register */ - __IOM uint32_t CFSR; /*!< Offset: 0x028 (R/W) Configurable Fault Status Register */ - __IOM uint32_t HFSR; /*!< Offset: 0x02C (R/W) HardFault Status Register */ - __IOM uint32_t DFSR; /*!< Offset: 0x030 (R/W) Debug Fault Status Register */ - __IOM uint32_t MMFAR; /*!< Offset: 0x034 (R/W) MemManage Fault Address Register */ - __IOM uint32_t BFAR; /*!< Offset: 0x038 (R/W) BusFault Address Register */ - __IOM uint32_t AFSR; /*!< Offset: 0x03C (R/W) Auxiliary Fault Status Register */ - __IM uint32_t PFR[2U]; /*!< Offset: 0x040 (R/ ) Processor Feature Register */ - __IM uint32_t DFR; /*!< Offset: 0x048 (R/ ) Debug Feature Register */ - __IM uint32_t ADR; /*!< Offset: 0x04C (R/ ) Auxiliary Feature Register */ - __IM uint32_t MMFR[4U]; /*!< Offset: 0x050 (R/ ) Memory Model Feature Register */ - __IM uint32_t ISAR[5U]; /*!< Offset: 0x060 (R/ ) Instruction Set Attributes Register */ - uint32_t RESERVED0[5U]; - __IOM uint32_t CPACR; /*!< Offset: 0x088 (R/W) Coprocessor Access Control Register */ - uint32_t RESERVED1[129U]; - __IOM uint32_t SFCR; /*!< Offset: 0x290 (R/W) Security Features Control Register */ -} SCB_Type; - -/* SCB CPUID Register Definitions */ -#define SCB_CPUID_IMPLEMENTER_Pos 24U /*!< SCB CPUID: IMPLEMENTER Position */ -#define SCB_CPUID_IMPLEMENTER_Msk (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos) /*!< SCB CPUID: IMPLEMENTER Mask */ - -#define SCB_CPUID_VARIANT_Pos 20U /*!< SCB CPUID: VARIANT Position */ -#define SCB_CPUID_VARIANT_Msk (0xFUL << SCB_CPUID_VARIANT_Pos) /*!< SCB CPUID: VARIANT Mask */ - -#define SCB_CPUID_ARCHITECTURE_Pos 16U /*!< SCB CPUID: ARCHITECTURE Position */ -#define SCB_CPUID_ARCHITECTURE_Msk (0xFUL << SCB_CPUID_ARCHITECTURE_Pos) /*!< SCB CPUID: ARCHITECTURE Mask */ - -#define SCB_CPUID_PARTNO_Pos 4U /*!< SCB CPUID: PARTNO Position */ -#define SCB_CPUID_PARTNO_Msk (0xFFFUL << SCB_CPUID_PARTNO_Pos) /*!< SCB CPUID: PARTNO Mask */ - -#define SCB_CPUID_REVISION_Pos 0U /*!< SCB CPUID: REVISION Position */ -#define SCB_CPUID_REVISION_Msk (0xFUL /*<< SCB_CPUID_REVISION_Pos*/) /*!< SCB CPUID: REVISION Mask */ - -/* SCB Interrupt Control State Register Definitions */ -#define SCB_ICSR_NMIPENDSET_Pos 31U /*!< SCB ICSR: NMIPENDSET Position */ -#define SCB_ICSR_NMIPENDSET_Msk (1UL << SCB_ICSR_NMIPENDSET_Pos) /*!< SCB ICSR: NMIPENDSET Mask */ - -#define SCB_ICSR_PENDSVSET_Pos 28U /*!< SCB ICSR: PENDSVSET Position */ -#define SCB_ICSR_PENDSVSET_Msk (1UL << SCB_ICSR_PENDSVSET_Pos) /*!< SCB ICSR: PENDSVSET Mask */ - -#define SCB_ICSR_PENDSVCLR_Pos 27U /*!< SCB ICSR: PENDSVCLR Position */ -#define SCB_ICSR_PENDSVCLR_Msk (1UL << SCB_ICSR_PENDSVCLR_Pos) /*!< SCB ICSR: PENDSVCLR Mask */ - -#define SCB_ICSR_PENDSTSET_Pos 26U /*!< SCB ICSR: PENDSTSET Position */ -#define SCB_ICSR_PENDSTSET_Msk (1UL << SCB_ICSR_PENDSTSET_Pos) /*!< SCB ICSR: PENDSTSET Mask */ - -#define SCB_ICSR_PENDSTCLR_Pos 25U /*!< SCB ICSR: PENDSTCLR Position */ -#define SCB_ICSR_PENDSTCLR_Msk (1UL << SCB_ICSR_PENDSTCLR_Pos) /*!< SCB ICSR: PENDSTCLR Mask */ - -#define SCB_ICSR_ISRPREEMPT_Pos 23U /*!< SCB ICSR: ISRPREEMPT Position */ -#define SCB_ICSR_ISRPREEMPT_Msk (1UL << SCB_ICSR_ISRPREEMPT_Pos) /*!< SCB ICSR: ISRPREEMPT Mask */ - -#define SCB_ICSR_ISRPENDING_Pos 22U /*!< SCB ICSR: ISRPENDING Position */ -#define SCB_ICSR_ISRPENDING_Msk (1UL << SCB_ICSR_ISRPENDING_Pos) /*!< SCB ICSR: ISRPENDING Mask */ - -#define SCB_ICSR_VECTPENDING_Pos 12U /*!< SCB ICSR: VECTPENDING Position */ -#define SCB_ICSR_VECTPENDING_Msk (0x1FFUL << SCB_ICSR_VECTPENDING_Pos) /*!< SCB ICSR: VECTPENDING Mask */ - -#define SCB_ICSR_RETTOBASE_Pos 11U /*!< SCB ICSR: RETTOBASE Position */ -#define SCB_ICSR_RETTOBASE_Msk (1UL << SCB_ICSR_RETTOBASE_Pos) /*!< SCB ICSR: RETTOBASE Mask */ - -#define SCB_ICSR_VECTACTIVE_Pos 0U /*!< SCB ICSR: VECTACTIVE Position */ -#define SCB_ICSR_VECTACTIVE_Msk (0x1FFUL /*<< SCB_ICSR_VECTACTIVE_Pos*/) /*!< SCB ICSR: VECTACTIVE Mask */ - -/* SCB Vector Table Offset Register Definitions */ -#define SCB_VTOR_TBLBASE_Pos 29U /*!< SCB VTOR: TBLBASE Position */ -#define SCB_VTOR_TBLBASE_Msk (1UL << SCB_VTOR_TBLBASE_Pos) /*!< SCB VTOR: TBLBASE Mask */ - -#define SCB_VTOR_TBLOFF_Pos 7U /*!< SCB VTOR: TBLOFF Position */ -#define SCB_VTOR_TBLOFF_Msk (0x3FFFFFUL << SCB_VTOR_TBLOFF_Pos) /*!< SCB VTOR: TBLOFF Mask */ - -/* SCB Application Interrupt and Reset Control Register Definitions */ -#define SCB_AIRCR_VECTKEY_Pos 16U /*!< SCB AIRCR: VECTKEY Position */ -#define SCB_AIRCR_VECTKEY_Msk (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos) /*!< SCB AIRCR: VECTKEY Mask */ - -#define SCB_AIRCR_VECTKEYSTAT_Pos 16U /*!< SCB AIRCR: VECTKEYSTAT Position */ -#define SCB_AIRCR_VECTKEYSTAT_Msk (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos) /*!< SCB AIRCR: VECTKEYSTAT Mask */ - -#define SCB_AIRCR_ENDIANESS_Pos 15U /*!< SCB AIRCR: ENDIANESS Position */ -#define SCB_AIRCR_ENDIANESS_Msk (1UL << SCB_AIRCR_ENDIANESS_Pos) /*!< SCB AIRCR: ENDIANESS Mask */ - -#define SCB_AIRCR_PRIGROUP_Pos 8U /*!< SCB AIRCR: PRIGROUP Position */ -#define SCB_AIRCR_PRIGROUP_Msk (7UL << SCB_AIRCR_PRIGROUP_Pos) /*!< SCB AIRCR: PRIGROUP Mask */ - -#define SCB_AIRCR_SYSRESETREQ_Pos 2U /*!< SCB AIRCR: SYSRESETREQ Position */ -#define SCB_AIRCR_SYSRESETREQ_Msk (1UL << SCB_AIRCR_SYSRESETREQ_Pos) /*!< SCB AIRCR: SYSRESETREQ Mask */ - -#define SCB_AIRCR_VECTCLRACTIVE_Pos 1U /*!< SCB AIRCR: VECTCLRACTIVE Position */ -#define SCB_AIRCR_VECTCLRACTIVE_Msk (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos) /*!< SCB AIRCR: VECTCLRACTIVE Mask */ - -#define SCB_AIRCR_VECTRESET_Pos 0U /*!< SCB AIRCR: VECTRESET Position */ -#define SCB_AIRCR_VECTRESET_Msk (1UL /*<< SCB_AIRCR_VECTRESET_Pos*/) /*!< SCB AIRCR: VECTRESET Mask */ - -/* SCB System Control Register Definitions */ -#define SCB_SCR_SEVONPEND_Pos 4U /*!< SCB SCR: SEVONPEND Position */ -#define SCB_SCR_SEVONPEND_Msk (1UL << SCB_SCR_SEVONPEND_Pos) /*!< SCB SCR: SEVONPEND Mask */ - -#define SCB_SCR_SLEEPDEEP_Pos 2U /*!< SCB SCR: SLEEPDEEP Position */ -#define SCB_SCR_SLEEPDEEP_Msk (1UL << SCB_SCR_SLEEPDEEP_Pos) /*!< SCB SCR: SLEEPDEEP Mask */ - -#define SCB_SCR_SLEEPONEXIT_Pos 1U /*!< SCB SCR: SLEEPONEXIT Position */ -#define SCB_SCR_SLEEPONEXIT_Msk (1UL << SCB_SCR_SLEEPONEXIT_Pos) /*!< SCB SCR: SLEEPONEXIT Mask */ - -/* SCB Configuration Control Register Definitions */ -#define SCB_CCR_STKALIGN_Pos 9U /*!< SCB CCR: STKALIGN Position */ -#define SCB_CCR_STKALIGN_Msk (1UL << SCB_CCR_STKALIGN_Pos) /*!< SCB CCR: STKALIGN Mask */ - -#define SCB_CCR_BFHFNMIGN_Pos 8U /*!< SCB CCR: BFHFNMIGN Position */ -#define SCB_CCR_BFHFNMIGN_Msk (1UL << SCB_CCR_BFHFNMIGN_Pos) /*!< SCB CCR: BFHFNMIGN Mask */ - -#define SCB_CCR_DIV_0_TRP_Pos 4U /*!< SCB CCR: DIV_0_TRP Position */ -#define SCB_CCR_DIV_0_TRP_Msk (1UL << SCB_CCR_DIV_0_TRP_Pos) /*!< SCB CCR: DIV_0_TRP Mask */ - -#define SCB_CCR_UNALIGN_TRP_Pos 3U /*!< SCB CCR: UNALIGN_TRP Position */ -#define SCB_CCR_UNALIGN_TRP_Msk (1UL << SCB_CCR_UNALIGN_TRP_Pos) /*!< SCB CCR: UNALIGN_TRP Mask */ - -#define SCB_CCR_USERSETMPEND_Pos 1U /*!< SCB CCR: USERSETMPEND Position */ -#define SCB_CCR_USERSETMPEND_Msk (1UL << SCB_CCR_USERSETMPEND_Pos) /*!< SCB CCR: USERSETMPEND Mask */ - -#define SCB_CCR_NONBASETHRDENA_Pos 0U /*!< SCB CCR: NONBASETHRDENA Position */ -#define SCB_CCR_NONBASETHRDENA_Msk (1UL /*<< SCB_CCR_NONBASETHRDENA_Pos*/) /*!< SCB CCR: NONBASETHRDENA Mask */ - -/* SCB System Handler Control and State Register Definitions */ -#define SCB_SHCSR_USGFAULTENA_Pos 18U /*!< SCB SHCSR: USGFAULTENA Position */ -#define SCB_SHCSR_USGFAULTENA_Msk (1UL << SCB_SHCSR_USGFAULTENA_Pos) /*!< SCB SHCSR: USGFAULTENA Mask */ - -#define SCB_SHCSR_BUSFAULTENA_Pos 17U /*!< SCB SHCSR: BUSFAULTENA Position */ -#define SCB_SHCSR_BUSFAULTENA_Msk (1UL << SCB_SHCSR_BUSFAULTENA_Pos) /*!< SCB SHCSR: BUSFAULTENA Mask */ - -#define SCB_SHCSR_MEMFAULTENA_Pos 16U /*!< SCB SHCSR: MEMFAULTENA Position */ -#define SCB_SHCSR_MEMFAULTENA_Msk (1UL << SCB_SHCSR_MEMFAULTENA_Pos) /*!< SCB SHCSR: MEMFAULTENA Mask */ - -#define SCB_SHCSR_SVCALLPENDED_Pos 15U /*!< SCB SHCSR: SVCALLPENDED Position */ -#define SCB_SHCSR_SVCALLPENDED_Msk (1UL << SCB_SHCSR_SVCALLPENDED_Pos) /*!< SCB SHCSR: SVCALLPENDED Mask */ - -#define SCB_SHCSR_BUSFAULTPENDED_Pos 14U /*!< SCB SHCSR: BUSFAULTPENDED Position */ -#define SCB_SHCSR_BUSFAULTPENDED_Msk (1UL << SCB_SHCSR_BUSFAULTPENDED_Pos) /*!< SCB SHCSR: BUSFAULTPENDED Mask */ - -#define SCB_SHCSR_MEMFAULTPENDED_Pos 13U /*!< SCB SHCSR: MEMFAULTPENDED Position */ -#define SCB_SHCSR_MEMFAULTPENDED_Msk (1UL << SCB_SHCSR_MEMFAULTPENDED_Pos) /*!< SCB SHCSR: MEMFAULTPENDED Mask */ - -#define SCB_SHCSR_USGFAULTPENDED_Pos 12U /*!< SCB SHCSR: USGFAULTPENDED Position */ -#define SCB_SHCSR_USGFAULTPENDED_Msk (1UL << SCB_SHCSR_USGFAULTPENDED_Pos) /*!< SCB SHCSR: USGFAULTPENDED Mask */ - -#define SCB_SHCSR_SYSTICKACT_Pos 11U /*!< SCB SHCSR: SYSTICKACT Position */ -#define SCB_SHCSR_SYSTICKACT_Msk (1UL << SCB_SHCSR_SYSTICKACT_Pos) /*!< SCB SHCSR: SYSTICKACT Mask */ - -#define SCB_SHCSR_PENDSVACT_Pos 10U /*!< SCB SHCSR: PENDSVACT Position */ -#define SCB_SHCSR_PENDSVACT_Msk (1UL << SCB_SHCSR_PENDSVACT_Pos) /*!< SCB SHCSR: PENDSVACT Mask */ - -#define SCB_SHCSR_MONITORACT_Pos 8U /*!< SCB SHCSR: MONITORACT Position */ -#define SCB_SHCSR_MONITORACT_Msk (1UL << SCB_SHCSR_MONITORACT_Pos) /*!< SCB SHCSR: MONITORACT Mask */ - -#define SCB_SHCSR_SVCALLACT_Pos 7U /*!< SCB SHCSR: SVCALLACT Position */ -#define SCB_SHCSR_SVCALLACT_Msk (1UL << SCB_SHCSR_SVCALLACT_Pos) /*!< SCB SHCSR: SVCALLACT Mask */ - -#define SCB_SHCSR_USGFAULTACT_Pos 3U /*!< SCB SHCSR: USGFAULTACT Position */ -#define SCB_SHCSR_USGFAULTACT_Msk (1UL << SCB_SHCSR_USGFAULTACT_Pos) /*!< SCB SHCSR: USGFAULTACT Mask */ - -#define SCB_SHCSR_BUSFAULTACT_Pos 1U /*!< SCB SHCSR: BUSFAULTACT Position */ -#define SCB_SHCSR_BUSFAULTACT_Msk (1UL << SCB_SHCSR_BUSFAULTACT_Pos) /*!< SCB SHCSR: BUSFAULTACT Mask */ - -#define SCB_SHCSR_MEMFAULTACT_Pos 0U /*!< SCB SHCSR: MEMFAULTACT Position */ -#define SCB_SHCSR_MEMFAULTACT_Msk (1UL /*<< SCB_SHCSR_MEMFAULTACT_Pos*/) /*!< SCB SHCSR: MEMFAULTACT Mask */ - -/* SCB Configurable Fault Status Register Definitions */ -#define SCB_CFSR_USGFAULTSR_Pos 16U /*!< SCB CFSR: Usage Fault Status Register Position */ -#define SCB_CFSR_USGFAULTSR_Msk (0xFFFFUL << SCB_CFSR_USGFAULTSR_Pos) /*!< SCB CFSR: Usage Fault Status Register Mask */ - -#define SCB_CFSR_BUSFAULTSR_Pos 8U /*!< SCB CFSR: Bus Fault Status Register Position */ -#define SCB_CFSR_BUSFAULTSR_Msk (0xFFUL << SCB_CFSR_BUSFAULTSR_Pos) /*!< SCB CFSR: Bus Fault Status Register Mask */ - -#define SCB_CFSR_MEMFAULTSR_Pos 0U /*!< SCB CFSR: Memory Manage Fault Status Register Position */ -#define SCB_CFSR_MEMFAULTSR_Msk (0xFFUL /*<< SCB_CFSR_MEMFAULTSR_Pos*/) /*!< SCB CFSR: Memory Manage Fault Status Register Mask */ - -/* MemManage Fault Status Register (part of SCB Configurable Fault Status Register) */ -#define SCB_CFSR_MMARVALID_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 7U) /*!< SCB CFSR (MMFSR): MMARVALID Position */ -#define SCB_CFSR_MMARVALID_Msk (1UL << SCB_CFSR_MMARVALID_Pos) /*!< SCB CFSR (MMFSR): MMARVALID Mask */ - -#define SCB_CFSR_MSTKERR_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 4U) /*!< SCB CFSR (MMFSR): MSTKERR Position */ -#define SCB_CFSR_MSTKERR_Msk (1UL << SCB_CFSR_MSTKERR_Pos) /*!< SCB CFSR (MMFSR): MSTKERR Mask */ - -#define SCB_CFSR_MUNSTKERR_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 3U) /*!< SCB CFSR (MMFSR): MUNSTKERR Position */ -#define SCB_CFSR_MUNSTKERR_Msk (1UL << SCB_CFSR_MUNSTKERR_Pos) /*!< SCB CFSR (MMFSR): MUNSTKERR Mask */ - -#define SCB_CFSR_DACCVIOL_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 1U) /*!< SCB CFSR (MMFSR): DACCVIOL Position */ -#define SCB_CFSR_DACCVIOL_Msk (1UL << SCB_CFSR_DACCVIOL_Pos) /*!< SCB CFSR (MMFSR): DACCVIOL Mask */ - -#define SCB_CFSR_IACCVIOL_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 0U) /*!< SCB CFSR (MMFSR): IACCVIOL Position */ -#define SCB_CFSR_IACCVIOL_Msk (1UL /*<< SCB_CFSR_IACCVIOL_Pos*/) /*!< SCB CFSR (MMFSR): IACCVIOL Mask */ - -/* BusFault Status Register (part of SCB Configurable Fault Status Register) */ -#define SCB_CFSR_BFARVALID_Pos (SCB_CFSR_BUSFAULTSR_Pos + 7U) /*!< SCB CFSR (BFSR): BFARVALID Position */ -#define SCB_CFSR_BFARVALID_Msk (1UL << SCB_CFSR_BFARVALID_Pos) /*!< SCB CFSR (BFSR): BFARVALID Mask */ - -#define SCB_CFSR_STKERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 4U) /*!< SCB CFSR (BFSR): STKERR Position */ -#define SCB_CFSR_STKERR_Msk (1UL << SCB_CFSR_STKERR_Pos) /*!< SCB CFSR (BFSR): STKERR Mask */ - -#define SCB_CFSR_UNSTKERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 3U) /*!< SCB CFSR (BFSR): UNSTKERR Position */ -#define SCB_CFSR_UNSTKERR_Msk (1UL << SCB_CFSR_UNSTKERR_Pos) /*!< SCB CFSR (BFSR): UNSTKERR Mask */ - -#define SCB_CFSR_IMPRECISERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 2U) /*!< SCB CFSR (BFSR): IMPRECISERR Position */ -#define SCB_CFSR_IMPRECISERR_Msk (1UL << SCB_CFSR_IMPRECISERR_Pos) /*!< SCB CFSR (BFSR): IMPRECISERR Mask */ - -#define SCB_CFSR_PRECISERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 1U) /*!< SCB CFSR (BFSR): PRECISERR Position */ -#define SCB_CFSR_PRECISERR_Msk (1UL << SCB_CFSR_PRECISERR_Pos) /*!< SCB CFSR (BFSR): PRECISERR Mask */ - -#define SCB_CFSR_IBUSERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 0U) /*!< SCB CFSR (BFSR): IBUSERR Position */ -#define SCB_CFSR_IBUSERR_Msk (1UL << SCB_CFSR_IBUSERR_Pos) /*!< SCB CFSR (BFSR): IBUSERR Mask */ - -/* UsageFault Status Register (part of SCB Configurable Fault Status Register) */ -#define SCB_CFSR_DIVBYZERO_Pos (SCB_CFSR_USGFAULTSR_Pos + 9U) /*!< SCB CFSR (UFSR): DIVBYZERO Position */ -#define SCB_CFSR_DIVBYZERO_Msk (1UL << SCB_CFSR_DIVBYZERO_Pos) /*!< SCB CFSR (UFSR): DIVBYZERO Mask */ - -#define SCB_CFSR_UNALIGNED_Pos (SCB_CFSR_USGFAULTSR_Pos + 8U) /*!< SCB CFSR (UFSR): UNALIGNED Position */ -#define SCB_CFSR_UNALIGNED_Msk (1UL << SCB_CFSR_UNALIGNED_Pos) /*!< SCB CFSR (UFSR): UNALIGNED Mask */ - -#define SCB_CFSR_NOCP_Pos (SCB_CFSR_USGFAULTSR_Pos + 3U) /*!< SCB CFSR (UFSR): NOCP Position */ -#define SCB_CFSR_NOCP_Msk (1UL << SCB_CFSR_NOCP_Pos) /*!< SCB CFSR (UFSR): NOCP Mask */ - -#define SCB_CFSR_INVPC_Pos (SCB_CFSR_USGFAULTSR_Pos + 2U) /*!< SCB CFSR (UFSR): INVPC Position */ -#define SCB_CFSR_INVPC_Msk (1UL << SCB_CFSR_INVPC_Pos) /*!< SCB CFSR (UFSR): INVPC Mask */ - -#define SCB_CFSR_INVSTATE_Pos (SCB_CFSR_USGFAULTSR_Pos + 1U) /*!< SCB CFSR (UFSR): INVSTATE Position */ -#define SCB_CFSR_INVSTATE_Msk (1UL << SCB_CFSR_INVSTATE_Pos) /*!< SCB CFSR (UFSR): INVSTATE Mask */ - -#define SCB_CFSR_UNDEFINSTR_Pos (SCB_CFSR_USGFAULTSR_Pos + 0U) /*!< SCB CFSR (UFSR): UNDEFINSTR Position */ -#define SCB_CFSR_UNDEFINSTR_Msk (1UL << SCB_CFSR_UNDEFINSTR_Pos) /*!< SCB CFSR (UFSR): UNDEFINSTR Mask */ - -/* SCB Hard Fault Status Register Definitions */ -#define SCB_HFSR_DEBUGEVT_Pos 31U /*!< SCB HFSR: DEBUGEVT Position */ -#define SCB_HFSR_DEBUGEVT_Msk (1UL << SCB_HFSR_DEBUGEVT_Pos) /*!< SCB HFSR: DEBUGEVT Mask */ - -#define SCB_HFSR_FORCED_Pos 30U /*!< SCB HFSR: FORCED Position */ -#define SCB_HFSR_FORCED_Msk (1UL << SCB_HFSR_FORCED_Pos) /*!< SCB HFSR: FORCED Mask */ - -#define SCB_HFSR_VECTTBL_Pos 1U /*!< SCB HFSR: VECTTBL Position */ -#define SCB_HFSR_VECTTBL_Msk (1UL << SCB_HFSR_VECTTBL_Pos) /*!< SCB HFSR: VECTTBL Mask */ - -/* SCB Debug Fault Status Register Definitions */ -#define SCB_DFSR_EXTERNAL_Pos 4U /*!< SCB DFSR: EXTERNAL Position */ -#define SCB_DFSR_EXTERNAL_Msk (1UL << SCB_DFSR_EXTERNAL_Pos) /*!< SCB DFSR: EXTERNAL Mask */ - -#define SCB_DFSR_VCATCH_Pos 3U /*!< SCB DFSR: VCATCH Position */ -#define SCB_DFSR_VCATCH_Msk (1UL << SCB_DFSR_VCATCH_Pos) /*!< SCB DFSR: VCATCH Mask */ - -#define SCB_DFSR_DWTTRAP_Pos 2U /*!< SCB DFSR: DWTTRAP Position */ -#define SCB_DFSR_DWTTRAP_Msk (1UL << SCB_DFSR_DWTTRAP_Pos) /*!< SCB DFSR: DWTTRAP Mask */ - -#define SCB_DFSR_BKPT_Pos 1U /*!< SCB DFSR: BKPT Position */ -#define SCB_DFSR_BKPT_Msk (1UL << SCB_DFSR_BKPT_Pos) /*!< SCB DFSR: BKPT Mask */ - -#define SCB_DFSR_HALTED_Pos 0U /*!< SCB DFSR: HALTED Position */ -#define SCB_DFSR_HALTED_Msk (1UL /*<< SCB_DFSR_HALTED_Pos*/) /*!< SCB DFSR: HALTED Mask */ - -/*@} end of group CMSIS_SCB */ - - -/** - \ingroup CMSIS_core_register - \defgroup CMSIS_SCnSCB System Controls not in SCB (SCnSCB) - \brief Type definitions for the System Control and ID Register not in the SCB - @{ - */ - -/** - \brief Structure type to access the System Control and ID Register not in the SCB. - */ -typedef struct -{ - uint32_t RESERVED0[1U]; - __IM uint32_t ICTR; /*!< Offset: 0x004 (R/ ) Interrupt Controller Type Register */ - uint32_t RESERVED1[1U]; -} SCnSCB_Type; - -/* Interrupt Controller Type Register Definitions */ -#define SCnSCB_ICTR_INTLINESNUM_Pos 0U /*!< ICTR: INTLINESNUM Position */ -#define SCnSCB_ICTR_INTLINESNUM_Msk (0xFUL /*<< SCnSCB_ICTR_INTLINESNUM_Pos*/) /*!< ICTR: INTLINESNUM Mask */ - -/*@} end of group CMSIS_SCnotSCB */ - - -/** - \ingroup CMSIS_core_register - \defgroup CMSIS_SysTick System Tick Timer (SysTick) - \brief Type definitions for the System Timer Registers. - @{ - */ - -/** - \brief Structure type to access the System Timer (SysTick). - */ -typedef struct -{ - __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) SysTick Control and Status Register */ - __IOM uint32_t LOAD; /*!< Offset: 0x004 (R/W) SysTick Reload Value Register */ - __IOM uint32_t VAL; /*!< Offset: 0x008 (R/W) SysTick Current Value Register */ - __IM uint32_t CALIB; /*!< Offset: 0x00C (R/ ) SysTick Calibration Register */ -} SysTick_Type; - -/* SysTick Control / Status Register Definitions */ -#define SysTick_CTRL_COUNTFLAG_Pos 16U /*!< SysTick CTRL: COUNTFLAG Position */ -#define SysTick_CTRL_COUNTFLAG_Msk (1UL << SysTick_CTRL_COUNTFLAG_Pos) /*!< SysTick CTRL: COUNTFLAG Mask */ - -#define SysTick_CTRL_CLKSOURCE_Pos 2U /*!< SysTick CTRL: CLKSOURCE Position */ -#define SysTick_CTRL_CLKSOURCE_Msk (1UL << SysTick_CTRL_CLKSOURCE_Pos) /*!< SysTick CTRL: CLKSOURCE Mask */ - -#define SysTick_CTRL_TICKINT_Pos 1U /*!< SysTick CTRL: TICKINT Position */ -#define SysTick_CTRL_TICKINT_Msk (1UL << SysTick_CTRL_TICKINT_Pos) /*!< SysTick CTRL: TICKINT Mask */ - -#define SysTick_CTRL_ENABLE_Pos 0U /*!< SysTick CTRL: ENABLE Position */ -#define SysTick_CTRL_ENABLE_Msk (1UL /*<< SysTick_CTRL_ENABLE_Pos*/) /*!< SysTick CTRL: ENABLE Mask */ - -/* SysTick Reload Register Definitions */ -#define SysTick_LOAD_RELOAD_Pos 0U /*!< SysTick LOAD: RELOAD Position */ -#define SysTick_LOAD_RELOAD_Msk (0xFFFFFFUL /*<< SysTick_LOAD_RELOAD_Pos*/) /*!< SysTick LOAD: RELOAD Mask */ - -/* SysTick Current Register Definitions */ -#define SysTick_VAL_CURRENT_Pos 0U /*!< SysTick VAL: CURRENT Position */ -#define SysTick_VAL_CURRENT_Msk (0xFFFFFFUL /*<< SysTick_VAL_CURRENT_Pos*/) /*!< SysTick VAL: CURRENT Mask */ - -/* SysTick Calibration Register Definitions */ -#define SysTick_CALIB_NOREF_Pos 31U /*!< SysTick CALIB: NOREF Position */ -#define SysTick_CALIB_NOREF_Msk (1UL << SysTick_CALIB_NOREF_Pos) /*!< SysTick CALIB: NOREF Mask */ - -#define SysTick_CALIB_SKEW_Pos 30U /*!< SysTick CALIB: SKEW Position */ -#define SysTick_CALIB_SKEW_Msk (1UL << SysTick_CALIB_SKEW_Pos) /*!< SysTick CALIB: SKEW Mask */ - -#define SysTick_CALIB_TENMS_Pos 0U /*!< SysTick CALIB: TENMS Position */ -#define SysTick_CALIB_TENMS_Msk (0xFFFFFFUL /*<< SysTick_CALIB_TENMS_Pos*/) /*!< SysTick CALIB: TENMS Mask */ - -/*@} end of group CMSIS_SysTick */ - - -/** - \ingroup CMSIS_core_register - \defgroup CMSIS_ITM Instrumentation Trace Macrocell (ITM) - \brief Type definitions for the Instrumentation Trace Macrocell (ITM) - @{ - */ - -/** - \brief Structure type to access the Instrumentation Trace Macrocell Register (ITM). - */ -typedef struct -{ - __OM union - { - __OM uint8_t u8; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 8-bit */ - __OM uint16_t u16; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 16-bit */ - __OM uint32_t u32; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 32-bit */ - } PORT [32U]; /*!< Offset: 0x000 ( /W) ITM Stimulus Port Registers */ - uint32_t RESERVED0[864U]; - __IOM uint32_t TER; /*!< Offset: 0xE00 (R/W) ITM Trace Enable Register */ - uint32_t RESERVED1[15U]; - __IOM uint32_t TPR; /*!< Offset: 0xE40 (R/W) ITM Trace Privilege Register */ - uint32_t RESERVED2[15U]; - __IOM uint32_t TCR; /*!< Offset: 0xE80 (R/W) ITM Trace Control Register */ - uint32_t RESERVED3[29U]; - __OM uint32_t IWR; /*!< Offset: 0xEF8 ( /W) ITM Integration Write Register */ - __IM uint32_t IRR; /*!< Offset: 0xEFC (R/ ) ITM Integration Read Register */ - __IOM uint32_t IMCR; /*!< Offset: 0xF00 (R/W) ITM Integration Mode Control Register */ - uint32_t RESERVED4[43U]; - __OM uint32_t LAR; /*!< Offset: 0xFB0 ( /W) ITM Lock Access Register */ - __IM uint32_t LSR; /*!< Offset: 0xFB4 (R/ ) ITM Lock Status Register */ - uint32_t RESERVED5[6U]; - __IM uint32_t PID4; /*!< Offset: 0xFD0 (R/ ) ITM Peripheral Identification Register #4 */ - __IM uint32_t PID5; /*!< Offset: 0xFD4 (R/ ) ITM Peripheral Identification Register #5 */ - __IM uint32_t PID6; /*!< Offset: 0xFD8 (R/ ) ITM Peripheral Identification Register #6 */ - __IM uint32_t PID7; /*!< Offset: 0xFDC (R/ ) ITM Peripheral Identification Register #7 */ - __IM uint32_t PID0; /*!< Offset: 0xFE0 (R/ ) ITM Peripheral Identification Register #0 */ - __IM uint32_t PID1; /*!< Offset: 0xFE4 (R/ ) ITM Peripheral Identification Register #1 */ - __IM uint32_t PID2; /*!< Offset: 0xFE8 (R/ ) ITM Peripheral Identification Register #2 */ - __IM uint32_t PID3; /*!< Offset: 0xFEC (R/ ) ITM Peripheral Identification Register #3 */ - __IM uint32_t CID0; /*!< Offset: 0xFF0 (R/ ) ITM Component Identification Register #0 */ - __IM uint32_t CID1; /*!< Offset: 0xFF4 (R/ ) ITM Component Identification Register #1 */ - __IM uint32_t CID2; /*!< Offset: 0xFF8 (R/ ) ITM Component Identification Register #2 */ - __IM uint32_t CID3; /*!< Offset: 0xFFC (R/ ) ITM Component Identification Register #3 */ -} ITM_Type; - -/* ITM Trace Privilege Register Definitions */ -#define ITM_TPR_PRIVMASK_Pos 0U /*!< ITM TPR: PRIVMASK Position */ -#define ITM_TPR_PRIVMASK_Msk (0xFUL /*<< ITM_TPR_PRIVMASK_Pos*/) /*!< ITM TPR: PRIVMASK Mask */ - -/* ITM Trace Control Register Definitions */ -#define ITM_TCR_BUSY_Pos 23U /*!< ITM TCR: BUSY Position */ -#define ITM_TCR_BUSY_Msk (1UL << ITM_TCR_BUSY_Pos) /*!< ITM TCR: BUSY Mask */ - -#define ITM_TCR_TraceBusID_Pos 16U /*!< ITM TCR: ATBID Position */ -#define ITM_TCR_TraceBusID_Msk (0x7FUL << ITM_TCR_TraceBusID_Pos) /*!< ITM TCR: ATBID Mask */ - -#define ITM_TCR_GTSFREQ_Pos 10U /*!< ITM TCR: Global timestamp frequency Position */ -#define ITM_TCR_GTSFREQ_Msk (3UL << ITM_TCR_GTSFREQ_Pos) /*!< ITM TCR: Global timestamp frequency Mask */ - -#define ITM_TCR_TSPrescale_Pos 8U /*!< ITM TCR: TSPrescale Position */ -#define ITM_TCR_TSPrescale_Msk (3UL << ITM_TCR_TSPrescale_Pos) /*!< ITM TCR: TSPrescale Mask */ - -#define ITM_TCR_SWOENA_Pos 4U /*!< ITM TCR: SWOENA Position */ -#define ITM_TCR_SWOENA_Msk (1UL << ITM_TCR_SWOENA_Pos) /*!< ITM TCR: SWOENA Mask */ - -#define ITM_TCR_DWTENA_Pos 3U /*!< ITM TCR: DWTENA Position */ -#define ITM_TCR_DWTENA_Msk (1UL << ITM_TCR_DWTENA_Pos) /*!< ITM TCR: DWTENA Mask */ - -#define ITM_TCR_SYNCENA_Pos 2U /*!< ITM TCR: SYNCENA Position */ -#define ITM_TCR_SYNCENA_Msk (1UL << ITM_TCR_SYNCENA_Pos) /*!< ITM TCR: SYNCENA Mask */ - -#define ITM_TCR_TSENA_Pos 1U /*!< ITM TCR: TSENA Position */ -#define ITM_TCR_TSENA_Msk (1UL << ITM_TCR_TSENA_Pos) /*!< ITM TCR: TSENA Mask */ - -#define ITM_TCR_ITMENA_Pos 0U /*!< ITM TCR: ITM Enable bit Position */ -#define ITM_TCR_ITMENA_Msk (1UL /*<< ITM_TCR_ITMENA_Pos*/) /*!< ITM TCR: ITM Enable bit Mask */ - -/* ITM Integration Write Register Definitions */ -#define ITM_IWR_ATVALIDM_Pos 0U /*!< ITM IWR: ATVALIDM Position */ -#define ITM_IWR_ATVALIDM_Msk (1UL /*<< ITM_IWR_ATVALIDM_Pos*/) /*!< ITM IWR: ATVALIDM Mask */ - -/* ITM Integration Read Register Definitions */ -#define ITM_IRR_ATREADYM_Pos 0U /*!< ITM IRR: ATREADYM Position */ -#define ITM_IRR_ATREADYM_Msk (1UL /*<< ITM_IRR_ATREADYM_Pos*/) /*!< ITM IRR: ATREADYM Mask */ - -/* ITM Integration Mode Control Register Definitions */ -#define ITM_IMCR_INTEGRATION_Pos 0U /*!< ITM IMCR: INTEGRATION Position */ -#define ITM_IMCR_INTEGRATION_Msk (1UL /*<< ITM_IMCR_INTEGRATION_Pos*/) /*!< ITM IMCR: INTEGRATION Mask */ - -/* ITM Lock Status Register Definitions */ -#define ITM_LSR_ByteAcc_Pos 2U /*!< ITM LSR: ByteAcc Position */ -#define ITM_LSR_ByteAcc_Msk (1UL << ITM_LSR_ByteAcc_Pos) /*!< ITM LSR: ByteAcc Mask */ - -#define ITM_LSR_Access_Pos 1U /*!< ITM LSR: Access Position */ -#define ITM_LSR_Access_Msk (1UL << ITM_LSR_Access_Pos) /*!< ITM LSR: Access Mask */ - -#define ITM_LSR_Present_Pos 0U /*!< ITM LSR: Present Position */ -#define ITM_LSR_Present_Msk (1UL /*<< ITM_LSR_Present_Pos*/) /*!< ITM LSR: Present Mask */ - -/*@}*/ /* end of group CMSIS_ITM */ - - -/** - \ingroup CMSIS_core_register - \defgroup CMSIS_DWT Data Watchpoint and Trace (DWT) - \brief Type definitions for the Data Watchpoint and Trace (DWT) - @{ - */ - -/** - \brief Structure type to access the Data Watchpoint and Trace Register (DWT). - */ -typedef struct -{ - __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) Control Register */ - __IOM uint32_t CYCCNT; /*!< Offset: 0x004 (R/W) Cycle Count Register */ - __IOM uint32_t CPICNT; /*!< Offset: 0x008 (R/W) CPI Count Register */ - __IOM uint32_t EXCCNT; /*!< Offset: 0x00C (R/W) Exception Overhead Count Register */ - __IOM uint32_t SLEEPCNT; /*!< Offset: 0x010 (R/W) Sleep Count Register */ - __IOM uint32_t LSUCNT; /*!< Offset: 0x014 (R/W) LSU Count Register */ - __IOM uint32_t FOLDCNT; /*!< Offset: 0x018 (R/W) Folded-instruction Count Register */ - __IM uint32_t PCSR; /*!< Offset: 0x01C (R/ ) Program Counter Sample Register */ - __IOM uint32_t COMP0; /*!< Offset: 0x020 (R/W) Comparator Register 0 */ - __IOM uint32_t MASK0; /*!< Offset: 0x024 (R/W) Mask Register 0 */ - __IOM uint32_t FUNCTION0; /*!< Offset: 0x028 (R/W) Function Register 0 */ - uint32_t RESERVED0[1U]; - __IOM uint32_t COMP1; /*!< Offset: 0x030 (R/W) Comparator Register 1 */ - __IOM uint32_t MASK1; /*!< Offset: 0x034 (R/W) Mask Register 1 */ - __IOM uint32_t FUNCTION1; /*!< Offset: 0x038 (R/W) Function Register 1 */ - uint32_t RESERVED1[1U]; - __IOM uint32_t COMP2; /*!< Offset: 0x040 (R/W) Comparator Register 2 */ - __IOM uint32_t MASK2; /*!< Offset: 0x044 (R/W) Mask Register 2 */ - __IOM uint32_t FUNCTION2; /*!< Offset: 0x048 (R/W) Function Register 2 */ - uint32_t RESERVED2[1U]; - __IOM uint32_t COMP3; /*!< Offset: 0x050 (R/W) Comparator Register 3 */ - __IOM uint32_t MASK3; /*!< Offset: 0x054 (R/W) Mask Register 3 */ - __IOM uint32_t FUNCTION3; /*!< Offset: 0x058 (R/W) Function Register 3 */ -} DWT_Type; - -/* DWT Control Register Definitions */ -#define DWT_CTRL_NUMCOMP_Pos 28U /*!< DWT CTRL: NUMCOMP Position */ -#define DWT_CTRL_NUMCOMP_Msk (0xFUL << DWT_CTRL_NUMCOMP_Pos) /*!< DWT CTRL: NUMCOMP Mask */ - -#define DWT_CTRL_NOTRCPKT_Pos 27U /*!< DWT CTRL: NOTRCPKT Position */ -#define DWT_CTRL_NOTRCPKT_Msk (0x1UL << DWT_CTRL_NOTRCPKT_Pos) /*!< DWT CTRL: NOTRCPKT Mask */ - -#define DWT_CTRL_NOEXTTRIG_Pos 26U /*!< DWT CTRL: NOEXTTRIG Position */ -#define DWT_CTRL_NOEXTTRIG_Msk (0x1UL << DWT_CTRL_NOEXTTRIG_Pos) /*!< DWT CTRL: NOEXTTRIG Mask */ - -#define DWT_CTRL_NOCYCCNT_Pos 25U /*!< DWT CTRL: NOCYCCNT Position */ -#define DWT_CTRL_NOCYCCNT_Msk (0x1UL << DWT_CTRL_NOCYCCNT_Pos) /*!< DWT CTRL: NOCYCCNT Mask */ - -#define DWT_CTRL_NOPRFCNT_Pos 24U /*!< DWT CTRL: NOPRFCNT Position */ -#define DWT_CTRL_NOPRFCNT_Msk (0x1UL << DWT_CTRL_NOPRFCNT_Pos) /*!< DWT CTRL: NOPRFCNT Mask */ - -#define DWT_CTRL_CYCEVTENA_Pos 22U /*!< DWT CTRL: CYCEVTENA Position */ -#define DWT_CTRL_CYCEVTENA_Msk (0x1UL << DWT_CTRL_CYCEVTENA_Pos) /*!< DWT CTRL: CYCEVTENA Mask */ - -#define DWT_CTRL_FOLDEVTENA_Pos 21U /*!< DWT CTRL: FOLDEVTENA Position */ -#define DWT_CTRL_FOLDEVTENA_Msk (0x1UL << DWT_CTRL_FOLDEVTENA_Pos) /*!< DWT CTRL: FOLDEVTENA Mask */ - -#define DWT_CTRL_LSUEVTENA_Pos 20U /*!< DWT CTRL: LSUEVTENA Position */ -#define DWT_CTRL_LSUEVTENA_Msk (0x1UL << DWT_CTRL_LSUEVTENA_Pos) /*!< DWT CTRL: LSUEVTENA Mask */ - -#define DWT_CTRL_SLEEPEVTENA_Pos 19U /*!< DWT CTRL: SLEEPEVTENA Position */ -#define DWT_CTRL_SLEEPEVTENA_Msk (0x1UL << DWT_CTRL_SLEEPEVTENA_Pos) /*!< DWT CTRL: SLEEPEVTENA Mask */ - -#define DWT_CTRL_EXCEVTENA_Pos 18U /*!< DWT CTRL: EXCEVTENA Position */ -#define DWT_CTRL_EXCEVTENA_Msk (0x1UL << DWT_CTRL_EXCEVTENA_Pos) /*!< DWT CTRL: EXCEVTENA Mask */ - -#define DWT_CTRL_CPIEVTENA_Pos 17U /*!< DWT CTRL: CPIEVTENA Position */ -#define DWT_CTRL_CPIEVTENA_Msk (0x1UL << DWT_CTRL_CPIEVTENA_Pos) /*!< DWT CTRL: CPIEVTENA Mask */ - -#define DWT_CTRL_EXCTRCENA_Pos 16U /*!< DWT CTRL: EXCTRCENA Position */ -#define DWT_CTRL_EXCTRCENA_Msk (0x1UL << DWT_CTRL_EXCTRCENA_Pos) /*!< DWT CTRL: EXCTRCENA Mask */ - -#define DWT_CTRL_PCSAMPLENA_Pos 12U /*!< DWT CTRL: PCSAMPLENA Position */ -#define DWT_CTRL_PCSAMPLENA_Msk (0x1UL << DWT_CTRL_PCSAMPLENA_Pos) /*!< DWT CTRL: PCSAMPLENA Mask */ - -#define DWT_CTRL_SYNCTAP_Pos 10U /*!< DWT CTRL: SYNCTAP Position */ -#define DWT_CTRL_SYNCTAP_Msk (0x3UL << DWT_CTRL_SYNCTAP_Pos) /*!< DWT CTRL: SYNCTAP Mask */ - -#define DWT_CTRL_CYCTAP_Pos 9U /*!< DWT CTRL: CYCTAP Position */ -#define DWT_CTRL_CYCTAP_Msk (0x1UL << DWT_CTRL_CYCTAP_Pos) /*!< DWT CTRL: CYCTAP Mask */ - -#define DWT_CTRL_POSTINIT_Pos 5U /*!< DWT CTRL: POSTINIT Position */ -#define DWT_CTRL_POSTINIT_Msk (0xFUL << DWT_CTRL_POSTINIT_Pos) /*!< DWT CTRL: POSTINIT Mask */ - -#define DWT_CTRL_POSTPRESET_Pos 1U /*!< DWT CTRL: POSTPRESET Position */ -#define DWT_CTRL_POSTPRESET_Msk (0xFUL << DWT_CTRL_POSTPRESET_Pos) /*!< DWT CTRL: POSTPRESET Mask */ - -#define DWT_CTRL_CYCCNTENA_Pos 0U /*!< DWT CTRL: CYCCNTENA Position */ -#define DWT_CTRL_CYCCNTENA_Msk (0x1UL /*<< DWT_CTRL_CYCCNTENA_Pos*/) /*!< DWT CTRL: CYCCNTENA Mask */ - -/* DWT CPI Count Register Definitions */ -#define DWT_CPICNT_CPICNT_Pos 0U /*!< DWT CPICNT: CPICNT Position */ -#define DWT_CPICNT_CPICNT_Msk (0xFFUL /*<< DWT_CPICNT_CPICNT_Pos*/) /*!< DWT CPICNT: CPICNT Mask */ - -/* DWT Exception Overhead Count Register Definitions */ -#define DWT_EXCCNT_EXCCNT_Pos 0U /*!< DWT EXCCNT: EXCCNT Position */ -#define DWT_EXCCNT_EXCCNT_Msk (0xFFUL /*<< DWT_EXCCNT_EXCCNT_Pos*/) /*!< DWT EXCCNT: EXCCNT Mask */ - -/* DWT Sleep Count Register Definitions */ -#define DWT_SLEEPCNT_SLEEPCNT_Pos 0U /*!< DWT SLEEPCNT: SLEEPCNT Position */ -#define DWT_SLEEPCNT_SLEEPCNT_Msk (0xFFUL /*<< DWT_SLEEPCNT_SLEEPCNT_Pos*/) /*!< DWT SLEEPCNT: SLEEPCNT Mask */ - -/* DWT LSU Count Register Definitions */ -#define DWT_LSUCNT_LSUCNT_Pos 0U /*!< DWT LSUCNT: LSUCNT Position */ -#define DWT_LSUCNT_LSUCNT_Msk (0xFFUL /*<< DWT_LSUCNT_LSUCNT_Pos*/) /*!< DWT LSUCNT: LSUCNT Mask */ - -/* DWT Folded-instruction Count Register Definitions */ -#define DWT_FOLDCNT_FOLDCNT_Pos 0U /*!< DWT FOLDCNT: FOLDCNT Position */ -#define DWT_FOLDCNT_FOLDCNT_Msk (0xFFUL /*<< DWT_FOLDCNT_FOLDCNT_Pos*/) /*!< DWT FOLDCNT: FOLDCNT Mask */ - -/* DWT Comparator Mask Register Definitions */ -#define DWT_MASK_MASK_Pos 0U /*!< DWT MASK: MASK Position */ -#define DWT_MASK_MASK_Msk (0x1FUL /*<< DWT_MASK_MASK_Pos*/) /*!< DWT MASK: MASK Mask */ - -/* DWT Comparator Function Register Definitions */ -#define DWT_FUNCTION_MATCHED_Pos 24U /*!< DWT FUNCTION: MATCHED Position */ -#define DWT_FUNCTION_MATCHED_Msk (0x1UL << DWT_FUNCTION_MATCHED_Pos) /*!< DWT FUNCTION: MATCHED Mask */ - -#define DWT_FUNCTION_DATAVADDR1_Pos 16U /*!< DWT FUNCTION: DATAVADDR1 Position */ -#define DWT_FUNCTION_DATAVADDR1_Msk (0xFUL << DWT_FUNCTION_DATAVADDR1_Pos) /*!< DWT FUNCTION: DATAVADDR1 Mask */ - -#define DWT_FUNCTION_DATAVADDR0_Pos 12U /*!< DWT FUNCTION: DATAVADDR0 Position */ -#define DWT_FUNCTION_DATAVADDR0_Msk (0xFUL << DWT_FUNCTION_DATAVADDR0_Pos) /*!< DWT FUNCTION: DATAVADDR0 Mask */ - -#define DWT_FUNCTION_DATAVSIZE_Pos 10U /*!< DWT FUNCTION: DATAVSIZE Position */ -#define DWT_FUNCTION_DATAVSIZE_Msk (0x3UL << DWT_FUNCTION_DATAVSIZE_Pos) /*!< DWT FUNCTION: DATAVSIZE Mask */ - -#define DWT_FUNCTION_LNK1ENA_Pos 9U /*!< DWT FUNCTION: LNK1ENA Position */ -#define DWT_FUNCTION_LNK1ENA_Msk (0x1UL << DWT_FUNCTION_LNK1ENA_Pos) /*!< DWT FUNCTION: LNK1ENA Mask */ - -#define DWT_FUNCTION_DATAVMATCH_Pos 8U /*!< DWT FUNCTION: DATAVMATCH Position */ -#define DWT_FUNCTION_DATAVMATCH_Msk (0x1UL << DWT_FUNCTION_DATAVMATCH_Pos) /*!< DWT FUNCTION: DATAVMATCH Mask */ - -#define DWT_FUNCTION_CYCMATCH_Pos 7U /*!< DWT FUNCTION: CYCMATCH Position */ -#define DWT_FUNCTION_CYCMATCH_Msk (0x1UL << DWT_FUNCTION_CYCMATCH_Pos) /*!< DWT FUNCTION: CYCMATCH Mask */ - -#define DWT_FUNCTION_EMITRANGE_Pos 5U /*!< DWT FUNCTION: EMITRANGE Position */ -#define DWT_FUNCTION_EMITRANGE_Msk (0x1UL << DWT_FUNCTION_EMITRANGE_Pos) /*!< DWT FUNCTION: EMITRANGE Mask */ - -#define DWT_FUNCTION_FUNCTION_Pos 0U /*!< DWT FUNCTION: FUNCTION Position */ -#define DWT_FUNCTION_FUNCTION_Msk (0xFUL /*<< DWT_FUNCTION_FUNCTION_Pos*/) /*!< DWT FUNCTION: FUNCTION Mask */ - -/*@}*/ /* end of group CMSIS_DWT */ - - -/** - \ingroup CMSIS_core_register - \defgroup CMSIS_TPI Trace Port Interface (TPI) - \brief Type definitions for the Trace Port Interface (TPI) - @{ - */ - -/** - \brief Structure type to access the Trace Port Interface Register (TPI). - */ -typedef struct -{ - __IOM uint32_t SSPSR; /*!< Offset: 0x000 (R/ ) Supported Parallel Port Size Register */ - __IOM uint32_t CSPSR; /*!< Offset: 0x004 (R/W) Current Parallel Port Size Register */ - uint32_t RESERVED0[2U]; - __IOM uint32_t ACPR; /*!< Offset: 0x010 (R/W) Asynchronous Clock Prescaler Register */ - uint32_t RESERVED1[55U]; - __IOM uint32_t SPPR; /*!< Offset: 0x0F0 (R/W) Selected Pin Protocol Register */ - uint32_t RESERVED2[131U]; - __IM uint32_t FFSR; /*!< Offset: 0x300 (R/ ) Formatter and Flush Status Register */ - __IOM uint32_t FFCR; /*!< Offset: 0x304 (R/W) Formatter and Flush Control Register */ - __IM uint32_t FSCR; /*!< Offset: 0x308 (R/ ) Formatter Synchronization Counter Register */ - uint32_t RESERVED3[759U]; - __IM uint32_t TRIGGER; /*!< Offset: 0xEE8 (R/ ) TRIGGER */ - __IM uint32_t FIFO0; /*!< Offset: 0xEEC (R/ ) Integration ETM Data */ - __IM uint32_t ITATBCTR2; /*!< Offset: 0xEF0 (R/ ) ITATBCTR2 */ - uint32_t RESERVED4[1U]; - __IM uint32_t ITATBCTR0; /*!< Offset: 0xEF8 (R/ ) ITATBCTR0 */ - __IM uint32_t FIFO1; /*!< Offset: 0xEFC (R/ ) Integration ITM Data */ - __IOM uint32_t ITCTRL; /*!< Offset: 0xF00 (R/W) Integration Mode Control */ - uint32_t RESERVED5[39U]; - __IOM uint32_t CLAIMSET; /*!< Offset: 0xFA0 (R/W) Claim tag set */ - __IOM uint32_t CLAIMCLR; /*!< Offset: 0xFA4 (R/W) Claim tag clear */ - uint32_t RESERVED7[8U]; - __IM uint32_t DEVID; /*!< Offset: 0xFC8 (R/ ) TPIU_DEVID */ - __IM uint32_t DEVTYPE; /*!< Offset: 0xFCC (R/ ) TPIU_DEVTYPE */ -} TPI_Type; - -/* TPI Asynchronous Clock Prescaler Register Definitions */ -#define TPI_ACPR_PRESCALER_Pos 0U /*!< TPI ACPR: PRESCALER Position */ -#define TPI_ACPR_PRESCALER_Msk (0x1FFFUL /*<< TPI_ACPR_PRESCALER_Pos*/) /*!< TPI ACPR: PRESCALER Mask */ - -/* TPI Selected Pin Protocol Register Definitions */ -#define TPI_SPPR_TXMODE_Pos 0U /*!< TPI SPPR: TXMODE Position */ -#define TPI_SPPR_TXMODE_Msk (0x3UL /*<< TPI_SPPR_TXMODE_Pos*/) /*!< TPI SPPR: TXMODE Mask */ - -/* TPI Formatter and Flush Status Register Definitions */ -#define TPI_FFSR_FtNonStop_Pos 3U /*!< TPI FFSR: FtNonStop Position */ -#define TPI_FFSR_FtNonStop_Msk (0x1UL << TPI_FFSR_FtNonStop_Pos) /*!< TPI FFSR: FtNonStop Mask */ - -#define TPI_FFSR_TCPresent_Pos 2U /*!< TPI FFSR: TCPresent Position */ -#define TPI_FFSR_TCPresent_Msk (0x1UL << TPI_FFSR_TCPresent_Pos) /*!< TPI FFSR: TCPresent Mask */ - -#define TPI_FFSR_FtStopped_Pos 1U /*!< TPI FFSR: FtStopped Position */ -#define TPI_FFSR_FtStopped_Msk (0x1UL << TPI_FFSR_FtStopped_Pos) /*!< TPI FFSR: FtStopped Mask */ - -#define TPI_FFSR_FlInProg_Pos 0U /*!< TPI FFSR: FlInProg Position */ -#define TPI_FFSR_FlInProg_Msk (0x1UL /*<< TPI_FFSR_FlInProg_Pos*/) /*!< TPI FFSR: FlInProg Mask */ - -/* TPI Formatter and Flush Control Register Definitions */ -#define TPI_FFCR_TrigIn_Pos 8U /*!< TPI FFCR: TrigIn Position */ -#define TPI_FFCR_TrigIn_Msk (0x1UL << TPI_FFCR_TrigIn_Pos) /*!< TPI FFCR: TrigIn Mask */ - -#define TPI_FFCR_EnFCont_Pos 1U /*!< TPI FFCR: EnFCont Position */ -#define TPI_FFCR_EnFCont_Msk (0x1UL << TPI_FFCR_EnFCont_Pos) /*!< TPI FFCR: EnFCont Mask */ - -/* TPI TRIGGER Register Definitions */ -#define TPI_TRIGGER_TRIGGER_Pos 0U /*!< TPI TRIGGER: TRIGGER Position */ -#define TPI_TRIGGER_TRIGGER_Msk (0x1UL /*<< TPI_TRIGGER_TRIGGER_Pos*/) /*!< TPI TRIGGER: TRIGGER Mask */ - -/* TPI Integration ETM Data Register Definitions (FIFO0) */ -#define TPI_FIFO0_ITM_ATVALID_Pos 29U /*!< TPI FIFO0: ITM_ATVALID Position */ -#define TPI_FIFO0_ITM_ATVALID_Msk (0x3UL << TPI_FIFO0_ITM_ATVALID_Pos) /*!< TPI FIFO0: ITM_ATVALID Mask */ - -#define TPI_FIFO0_ITM_bytecount_Pos 27U /*!< TPI FIFO0: ITM_bytecount Position */ -#define TPI_FIFO0_ITM_bytecount_Msk (0x3UL << TPI_FIFO0_ITM_bytecount_Pos) /*!< TPI FIFO0: ITM_bytecount Mask */ - -#define TPI_FIFO0_ETM_ATVALID_Pos 26U /*!< TPI FIFO0: ETM_ATVALID Position */ -#define TPI_FIFO0_ETM_ATVALID_Msk (0x3UL << TPI_FIFO0_ETM_ATVALID_Pos) /*!< TPI FIFO0: ETM_ATVALID Mask */ - -#define TPI_FIFO0_ETM_bytecount_Pos 24U /*!< TPI FIFO0: ETM_bytecount Position */ -#define TPI_FIFO0_ETM_bytecount_Msk (0x3UL << TPI_FIFO0_ETM_bytecount_Pos) /*!< TPI FIFO0: ETM_bytecount Mask */ - -#define TPI_FIFO0_ETM2_Pos 16U /*!< TPI FIFO0: ETM2 Position */ -#define TPI_FIFO0_ETM2_Msk (0xFFUL << TPI_FIFO0_ETM2_Pos) /*!< TPI FIFO0: ETM2 Mask */ - -#define TPI_FIFO0_ETM1_Pos 8U /*!< TPI FIFO0: ETM1 Position */ -#define TPI_FIFO0_ETM1_Msk (0xFFUL << TPI_FIFO0_ETM1_Pos) /*!< TPI FIFO0: ETM1 Mask */ - -#define TPI_FIFO0_ETM0_Pos 0U /*!< TPI FIFO0: ETM0 Position */ -#define TPI_FIFO0_ETM0_Msk (0xFFUL /*<< TPI_FIFO0_ETM0_Pos*/) /*!< TPI FIFO0: ETM0 Mask */ - -/* TPI ITATBCTR2 Register Definitions */ -#define TPI_ITATBCTR2_ATREADY_Pos 0U /*!< TPI ITATBCTR2: ATREADY Position */ -#define TPI_ITATBCTR2_ATREADY_Msk (0x1UL /*<< TPI_ITATBCTR2_ATREADY_Pos*/) /*!< TPI ITATBCTR2: ATREADY Mask */ - -/* TPI Integration ITM Data Register Definitions (FIFO1) */ -#define TPI_FIFO1_ITM_ATVALID_Pos 29U /*!< TPI FIFO1: ITM_ATVALID Position */ -#define TPI_FIFO1_ITM_ATVALID_Msk (0x3UL << TPI_FIFO1_ITM_ATVALID_Pos) /*!< TPI FIFO1: ITM_ATVALID Mask */ - -#define TPI_FIFO1_ITM_bytecount_Pos 27U /*!< TPI FIFO1: ITM_bytecount Position */ -#define TPI_FIFO1_ITM_bytecount_Msk (0x3UL << TPI_FIFO1_ITM_bytecount_Pos) /*!< TPI FIFO1: ITM_bytecount Mask */ - -#define TPI_FIFO1_ETM_ATVALID_Pos 26U /*!< TPI FIFO1: ETM_ATVALID Position */ -#define TPI_FIFO1_ETM_ATVALID_Msk (0x3UL << TPI_FIFO1_ETM_ATVALID_Pos) /*!< TPI FIFO1: ETM_ATVALID Mask */ - -#define TPI_FIFO1_ETM_bytecount_Pos 24U /*!< TPI FIFO1: ETM_bytecount Position */ -#define TPI_FIFO1_ETM_bytecount_Msk (0x3UL << TPI_FIFO1_ETM_bytecount_Pos) /*!< TPI FIFO1: ETM_bytecount Mask */ - -#define TPI_FIFO1_ITM2_Pos 16U /*!< TPI FIFO1: ITM2 Position */ -#define TPI_FIFO1_ITM2_Msk (0xFFUL << TPI_FIFO1_ITM2_Pos) /*!< TPI FIFO1: ITM2 Mask */ - -#define TPI_FIFO1_ITM1_Pos 8U /*!< TPI FIFO1: ITM1 Position */ -#define TPI_FIFO1_ITM1_Msk (0xFFUL << TPI_FIFO1_ITM1_Pos) /*!< TPI FIFO1: ITM1 Mask */ - -#define TPI_FIFO1_ITM0_Pos 0U /*!< TPI FIFO1: ITM0 Position */ -#define TPI_FIFO1_ITM0_Msk (0xFFUL /*<< TPI_FIFO1_ITM0_Pos*/) /*!< TPI FIFO1: ITM0 Mask */ - -/* TPI ITATBCTR0 Register Definitions */ -#define TPI_ITATBCTR0_ATREADY_Pos 0U /*!< TPI ITATBCTR0: ATREADY Position */ -#define TPI_ITATBCTR0_ATREADY_Msk (0x1UL /*<< TPI_ITATBCTR0_ATREADY_Pos*/) /*!< TPI ITATBCTR0: ATREADY Mask */ - -/* TPI Integration Mode Control Register Definitions */ -#define TPI_ITCTRL_Mode_Pos 0U /*!< TPI ITCTRL: Mode Position */ -#define TPI_ITCTRL_Mode_Msk (0x1UL /*<< TPI_ITCTRL_Mode_Pos*/) /*!< TPI ITCTRL: Mode Mask */ - -/* TPI DEVID Register Definitions */ -#define TPI_DEVID_NRZVALID_Pos 11U /*!< TPI DEVID: NRZVALID Position */ -#define TPI_DEVID_NRZVALID_Msk (0x1UL << TPI_DEVID_NRZVALID_Pos) /*!< TPI DEVID: NRZVALID Mask */ - -#define TPI_DEVID_MANCVALID_Pos 10U /*!< TPI DEVID: MANCVALID Position */ -#define TPI_DEVID_MANCVALID_Msk (0x1UL << TPI_DEVID_MANCVALID_Pos) /*!< TPI DEVID: MANCVALID Mask */ - -#define TPI_DEVID_PTINVALID_Pos 9U /*!< TPI DEVID: PTINVALID Position */ -#define TPI_DEVID_PTINVALID_Msk (0x1UL << TPI_DEVID_PTINVALID_Pos) /*!< TPI DEVID: PTINVALID Mask */ - -#define TPI_DEVID_MinBufSz_Pos 6U /*!< TPI DEVID: MinBufSz Position */ -#define TPI_DEVID_MinBufSz_Msk (0x7UL << TPI_DEVID_MinBufSz_Pos) /*!< TPI DEVID: MinBufSz Mask */ - -#define TPI_DEVID_AsynClkIn_Pos 5U /*!< TPI DEVID: AsynClkIn Position */ -#define TPI_DEVID_AsynClkIn_Msk (0x1UL << TPI_DEVID_AsynClkIn_Pos) /*!< TPI DEVID: AsynClkIn Mask */ - -#define TPI_DEVID_NrTraceInput_Pos 0U /*!< TPI DEVID: NrTraceInput Position */ -#define TPI_DEVID_NrTraceInput_Msk (0x1FUL /*<< TPI_DEVID_NrTraceInput_Pos*/) /*!< TPI DEVID: NrTraceInput Mask */ - -/* TPI DEVTYPE Register Definitions */ -#define TPI_DEVTYPE_MajorType_Pos 4U /*!< TPI DEVTYPE: MajorType Position */ -#define TPI_DEVTYPE_MajorType_Msk (0xFUL << TPI_DEVTYPE_MajorType_Pos) /*!< TPI DEVTYPE: MajorType Mask */ - -#define TPI_DEVTYPE_SubType_Pos 0U /*!< TPI DEVTYPE: SubType Position */ -#define TPI_DEVTYPE_SubType_Msk (0xFUL /*<< TPI_DEVTYPE_SubType_Pos*/) /*!< TPI DEVTYPE: SubType Mask */ - -/*@}*/ /* end of group CMSIS_TPI */ - - -#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) -/** - \ingroup CMSIS_core_register - \defgroup CMSIS_MPU Memory Protection Unit (MPU) - \brief Type definitions for the Memory Protection Unit (MPU) - @{ - */ - -/** - \brief Structure type to access the Memory Protection Unit (MPU). - */ -typedef struct -{ - __IM uint32_t TYPE; /*!< Offset: 0x000 (R/ ) MPU Type Register */ - __IOM uint32_t CTRL; /*!< Offset: 0x004 (R/W) MPU Control Register */ - __IOM uint32_t RNR; /*!< Offset: 0x008 (R/W) MPU Region RNRber Register */ - __IOM uint32_t RBAR; /*!< Offset: 0x00C (R/W) MPU Region Base Address Register */ - __IOM uint32_t RASR; /*!< Offset: 0x010 (R/W) MPU Region Attribute and Size Register */ - __IOM uint32_t RBAR_A1; /*!< Offset: 0x014 (R/W) MPU Alias 1 Region Base Address Register */ - __IOM uint32_t RASR_A1; /*!< Offset: 0x018 (R/W) MPU Alias 1 Region Attribute and Size Register */ - __IOM uint32_t RBAR_A2; /*!< Offset: 0x01C (R/W) MPU Alias 2 Region Base Address Register */ - __IOM uint32_t RASR_A2; /*!< Offset: 0x020 (R/W) MPU Alias 2 Region Attribute and Size Register */ - __IOM uint32_t RBAR_A3; /*!< Offset: 0x024 (R/W) MPU Alias 3 Region Base Address Register */ - __IOM uint32_t RASR_A3; /*!< Offset: 0x028 (R/W) MPU Alias 3 Region Attribute and Size Register */ -} MPU_Type; - -/* MPU Type Register Definitions */ -#define MPU_TYPE_IREGION_Pos 16U /*!< MPU TYPE: IREGION Position */ -#define MPU_TYPE_IREGION_Msk (0xFFUL << MPU_TYPE_IREGION_Pos) /*!< MPU TYPE: IREGION Mask */ - -#define MPU_TYPE_DREGION_Pos 8U /*!< MPU TYPE: DREGION Position */ -#define MPU_TYPE_DREGION_Msk (0xFFUL << MPU_TYPE_DREGION_Pos) /*!< MPU TYPE: DREGION Mask */ - -#define MPU_TYPE_SEPARATE_Pos 0U /*!< MPU TYPE: SEPARATE Position */ -#define MPU_TYPE_SEPARATE_Msk (1UL /*<< MPU_TYPE_SEPARATE_Pos*/) /*!< MPU TYPE: SEPARATE Mask */ - -/* MPU Control Register Definitions */ -#define MPU_CTRL_PRIVDEFENA_Pos 2U /*!< MPU CTRL: PRIVDEFENA Position */ -#define MPU_CTRL_PRIVDEFENA_Msk (1UL << MPU_CTRL_PRIVDEFENA_Pos) /*!< MPU CTRL: PRIVDEFENA Mask */ - -#define MPU_CTRL_HFNMIENA_Pos 1U /*!< MPU CTRL: HFNMIENA Position */ -#define MPU_CTRL_HFNMIENA_Msk (1UL << MPU_CTRL_HFNMIENA_Pos) /*!< MPU CTRL: HFNMIENA Mask */ - -#define MPU_CTRL_ENABLE_Pos 0U /*!< MPU CTRL: ENABLE Position */ -#define MPU_CTRL_ENABLE_Msk (1UL /*<< MPU_CTRL_ENABLE_Pos*/) /*!< MPU CTRL: ENABLE Mask */ - -/* MPU Region Number Register Definitions */ -#define MPU_RNR_REGION_Pos 0U /*!< MPU RNR: REGION Position */ -#define MPU_RNR_REGION_Msk (0xFFUL /*<< MPU_RNR_REGION_Pos*/) /*!< MPU RNR: REGION Mask */ - -/* MPU Region Base Address Register Definitions */ -#define MPU_RBAR_ADDR_Pos 5U /*!< MPU RBAR: ADDR Position */ -#define MPU_RBAR_ADDR_Msk (0x7FFFFFFUL << MPU_RBAR_ADDR_Pos) /*!< MPU RBAR: ADDR Mask */ - -#define MPU_RBAR_VALID_Pos 4U /*!< MPU RBAR: VALID Position */ -#define MPU_RBAR_VALID_Msk (1UL << MPU_RBAR_VALID_Pos) /*!< MPU RBAR: VALID Mask */ - -#define MPU_RBAR_REGION_Pos 0U /*!< MPU RBAR: REGION Position */ -#define MPU_RBAR_REGION_Msk (0xFUL /*<< MPU_RBAR_REGION_Pos*/) /*!< MPU RBAR: REGION Mask */ - -/* MPU Region Attribute and Size Register Definitions */ -#define MPU_RASR_ATTRS_Pos 16U /*!< MPU RASR: MPU Region Attribute field Position */ -#define MPU_RASR_ATTRS_Msk (0xFFFFUL << MPU_RASR_ATTRS_Pos) /*!< MPU RASR: MPU Region Attribute field Mask */ - -#define MPU_RASR_XN_Pos 28U /*!< MPU RASR: ATTRS.XN Position */ -#define MPU_RASR_XN_Msk (1UL << MPU_RASR_XN_Pos) /*!< MPU RASR: ATTRS.XN Mask */ - -#define MPU_RASR_AP_Pos 24U /*!< MPU RASR: ATTRS.AP Position */ -#define MPU_RASR_AP_Msk (0x7UL << MPU_RASR_AP_Pos) /*!< MPU RASR: ATTRS.AP Mask */ - -#define MPU_RASR_TEX_Pos 19U /*!< MPU RASR: ATTRS.TEX Position */ -#define MPU_RASR_TEX_Msk (0x7UL << MPU_RASR_TEX_Pos) /*!< MPU RASR: ATTRS.TEX Mask */ - -#define MPU_RASR_S_Pos 18U /*!< MPU RASR: ATTRS.S Position */ -#define MPU_RASR_S_Msk (1UL << MPU_RASR_S_Pos) /*!< MPU RASR: ATTRS.S Mask */ - -#define MPU_RASR_C_Pos 17U /*!< MPU RASR: ATTRS.C Position */ -#define MPU_RASR_C_Msk (1UL << MPU_RASR_C_Pos) /*!< MPU RASR: ATTRS.C Mask */ - -#define MPU_RASR_B_Pos 16U /*!< MPU RASR: ATTRS.B Position */ -#define MPU_RASR_B_Msk (1UL << MPU_RASR_B_Pos) /*!< MPU RASR: ATTRS.B Mask */ - -#define MPU_RASR_SRD_Pos 8U /*!< MPU RASR: Sub-Region Disable Position */ -#define MPU_RASR_SRD_Msk (0xFFUL << MPU_RASR_SRD_Pos) /*!< MPU RASR: Sub-Region Disable Mask */ - -#define MPU_RASR_SIZE_Pos 1U /*!< MPU RASR: Region Size Field Position */ -#define MPU_RASR_SIZE_Msk (0x1FUL << MPU_RASR_SIZE_Pos) /*!< MPU RASR: Region Size Field Mask */ - -#define MPU_RASR_ENABLE_Pos 0U /*!< MPU RASR: Region enable bit Position */ -#define MPU_RASR_ENABLE_Msk (1UL /*<< MPU_RASR_ENABLE_Pos*/) /*!< MPU RASR: Region enable bit Disable Mask */ - -/*@} end of group CMSIS_MPU */ -#endif - - -/** - \ingroup CMSIS_core_register - \defgroup CMSIS_CoreDebug Core Debug Registers (CoreDebug) - \brief Type definitions for the Core Debug Registers - @{ - */ - -/** - \brief Structure type to access the Core Debug Register (CoreDebug). - */ -typedef struct -{ - __IOM uint32_t DHCSR; /*!< Offset: 0x000 (R/W) Debug Halting Control and Status Register */ - __OM uint32_t DCRSR; /*!< Offset: 0x004 ( /W) Debug Core Register Selector Register */ - __IOM uint32_t DCRDR; /*!< Offset: 0x008 (R/W) Debug Core Register Data Register */ - __IOM uint32_t DEMCR; /*!< Offset: 0x00C (R/W) Debug Exception and Monitor Control Register */ -} CoreDebug_Type; - -/* Debug Halting Control and Status Register Definitions */ -#define CoreDebug_DHCSR_DBGKEY_Pos 16U /*!< CoreDebug DHCSR: DBGKEY Position */ -#define CoreDebug_DHCSR_DBGKEY_Msk (0xFFFFUL << CoreDebug_DHCSR_DBGKEY_Pos) /*!< CoreDebug DHCSR: DBGKEY Mask */ - -#define CoreDebug_DHCSR_S_RESET_ST_Pos 25U /*!< CoreDebug DHCSR: S_RESET_ST Position */ -#define CoreDebug_DHCSR_S_RESET_ST_Msk (1UL << CoreDebug_DHCSR_S_RESET_ST_Pos) /*!< CoreDebug DHCSR: S_RESET_ST Mask */ - -#define CoreDebug_DHCSR_S_RETIRE_ST_Pos 24U /*!< CoreDebug DHCSR: S_RETIRE_ST Position */ -#define CoreDebug_DHCSR_S_RETIRE_ST_Msk (1UL << CoreDebug_DHCSR_S_RETIRE_ST_Pos) /*!< CoreDebug DHCSR: S_RETIRE_ST Mask */ - -#define CoreDebug_DHCSR_S_LOCKUP_Pos 19U /*!< CoreDebug DHCSR: S_LOCKUP Position */ -#define CoreDebug_DHCSR_S_LOCKUP_Msk (1UL << CoreDebug_DHCSR_S_LOCKUP_Pos) /*!< CoreDebug DHCSR: S_LOCKUP Mask */ - -#define CoreDebug_DHCSR_S_SLEEP_Pos 18U /*!< CoreDebug DHCSR: S_SLEEP Position */ -#define CoreDebug_DHCSR_S_SLEEP_Msk (1UL << CoreDebug_DHCSR_S_SLEEP_Pos) /*!< CoreDebug DHCSR: S_SLEEP Mask */ - -#define CoreDebug_DHCSR_S_HALT_Pos 17U /*!< CoreDebug DHCSR: S_HALT Position */ -#define CoreDebug_DHCSR_S_HALT_Msk (1UL << CoreDebug_DHCSR_S_HALT_Pos) /*!< CoreDebug DHCSR: S_HALT Mask */ - -#define CoreDebug_DHCSR_S_REGRDY_Pos 16U /*!< CoreDebug DHCSR: S_REGRDY Position */ -#define CoreDebug_DHCSR_S_REGRDY_Msk (1UL << CoreDebug_DHCSR_S_REGRDY_Pos) /*!< CoreDebug DHCSR: S_REGRDY Mask */ - -#define CoreDebug_DHCSR_C_SNAPSTALL_Pos 5U /*!< CoreDebug DHCSR: C_SNAPSTALL Position */ -#define CoreDebug_DHCSR_C_SNAPSTALL_Msk (1UL << CoreDebug_DHCSR_C_SNAPSTALL_Pos) /*!< CoreDebug DHCSR: C_SNAPSTALL Mask */ - -#define CoreDebug_DHCSR_C_MASKINTS_Pos 3U /*!< CoreDebug DHCSR: C_MASKINTS Position */ -#define CoreDebug_DHCSR_C_MASKINTS_Msk (1UL << CoreDebug_DHCSR_C_MASKINTS_Pos) /*!< CoreDebug DHCSR: C_MASKINTS Mask */ - -#define CoreDebug_DHCSR_C_STEP_Pos 2U /*!< CoreDebug DHCSR: C_STEP Position */ -#define CoreDebug_DHCSR_C_STEP_Msk (1UL << CoreDebug_DHCSR_C_STEP_Pos) /*!< CoreDebug DHCSR: C_STEP Mask */ - -#define CoreDebug_DHCSR_C_HALT_Pos 1U /*!< CoreDebug DHCSR: C_HALT Position */ -#define CoreDebug_DHCSR_C_HALT_Msk (1UL << CoreDebug_DHCSR_C_HALT_Pos) /*!< CoreDebug DHCSR: C_HALT Mask */ - -#define CoreDebug_DHCSR_C_DEBUGEN_Pos 0U /*!< CoreDebug DHCSR: C_DEBUGEN Position */ -#define CoreDebug_DHCSR_C_DEBUGEN_Msk (1UL /*<< CoreDebug_DHCSR_C_DEBUGEN_Pos*/) /*!< CoreDebug DHCSR: C_DEBUGEN Mask */ - -/* Debug Core Register Selector Register Definitions */ -#define CoreDebug_DCRSR_REGWnR_Pos 16U /*!< CoreDebug DCRSR: REGWnR Position */ -#define CoreDebug_DCRSR_REGWnR_Msk (1UL << CoreDebug_DCRSR_REGWnR_Pos) /*!< CoreDebug DCRSR: REGWnR Mask */ - -#define CoreDebug_DCRSR_REGSEL_Pos 0U /*!< CoreDebug DCRSR: REGSEL Position */ -#define CoreDebug_DCRSR_REGSEL_Msk (0x1FUL /*<< CoreDebug_DCRSR_REGSEL_Pos*/) /*!< CoreDebug DCRSR: REGSEL Mask */ - -/* Debug Exception and Monitor Control Register Definitions */ -#define CoreDebug_DEMCR_TRCENA_Pos 24U /*!< CoreDebug DEMCR: TRCENA Position */ -#define CoreDebug_DEMCR_TRCENA_Msk (1UL << CoreDebug_DEMCR_TRCENA_Pos) /*!< CoreDebug DEMCR: TRCENA Mask */ - -#define CoreDebug_DEMCR_MON_REQ_Pos 19U /*!< CoreDebug DEMCR: MON_REQ Position */ -#define CoreDebug_DEMCR_MON_REQ_Msk (1UL << CoreDebug_DEMCR_MON_REQ_Pos) /*!< CoreDebug DEMCR: MON_REQ Mask */ - -#define CoreDebug_DEMCR_MON_STEP_Pos 18U /*!< CoreDebug DEMCR: MON_STEP Position */ -#define CoreDebug_DEMCR_MON_STEP_Msk (1UL << CoreDebug_DEMCR_MON_STEP_Pos) /*!< CoreDebug DEMCR: MON_STEP Mask */ - -#define CoreDebug_DEMCR_MON_PEND_Pos 17U /*!< CoreDebug DEMCR: MON_PEND Position */ -#define CoreDebug_DEMCR_MON_PEND_Msk (1UL << CoreDebug_DEMCR_MON_PEND_Pos) /*!< CoreDebug DEMCR: MON_PEND Mask */ - -#define CoreDebug_DEMCR_MON_EN_Pos 16U /*!< CoreDebug DEMCR: MON_EN Position */ -#define CoreDebug_DEMCR_MON_EN_Msk (1UL << CoreDebug_DEMCR_MON_EN_Pos) /*!< CoreDebug DEMCR: MON_EN Mask */ - -#define CoreDebug_DEMCR_VC_HARDERR_Pos 10U /*!< CoreDebug DEMCR: VC_HARDERR Position */ -#define CoreDebug_DEMCR_VC_HARDERR_Msk (1UL << CoreDebug_DEMCR_VC_HARDERR_Pos) /*!< CoreDebug DEMCR: VC_HARDERR Mask */ - -#define CoreDebug_DEMCR_VC_INTERR_Pos 9U /*!< CoreDebug DEMCR: VC_INTERR Position */ -#define CoreDebug_DEMCR_VC_INTERR_Msk (1UL << CoreDebug_DEMCR_VC_INTERR_Pos) /*!< CoreDebug DEMCR: VC_INTERR Mask */ - -#define CoreDebug_DEMCR_VC_BUSERR_Pos 8U /*!< CoreDebug DEMCR: VC_BUSERR Position */ -#define CoreDebug_DEMCR_VC_BUSERR_Msk (1UL << CoreDebug_DEMCR_VC_BUSERR_Pos) /*!< CoreDebug DEMCR: VC_BUSERR Mask */ - -#define CoreDebug_DEMCR_VC_STATERR_Pos 7U /*!< CoreDebug DEMCR: VC_STATERR Position */ -#define CoreDebug_DEMCR_VC_STATERR_Msk (1UL << CoreDebug_DEMCR_VC_STATERR_Pos) /*!< CoreDebug DEMCR: VC_STATERR Mask */ - -#define CoreDebug_DEMCR_VC_CHKERR_Pos 6U /*!< CoreDebug DEMCR: VC_CHKERR Position */ -#define CoreDebug_DEMCR_VC_CHKERR_Msk (1UL << CoreDebug_DEMCR_VC_CHKERR_Pos) /*!< CoreDebug DEMCR: VC_CHKERR Mask */ - -#define CoreDebug_DEMCR_VC_NOCPERR_Pos 5U /*!< CoreDebug DEMCR: VC_NOCPERR Position */ -#define CoreDebug_DEMCR_VC_NOCPERR_Msk (1UL << CoreDebug_DEMCR_VC_NOCPERR_Pos) /*!< CoreDebug DEMCR: VC_NOCPERR Mask */ - -#define CoreDebug_DEMCR_VC_MMERR_Pos 4U /*!< CoreDebug DEMCR: VC_MMERR Position */ -#define CoreDebug_DEMCR_VC_MMERR_Msk (1UL << CoreDebug_DEMCR_VC_MMERR_Pos) /*!< CoreDebug DEMCR: VC_MMERR Mask */ - -#define CoreDebug_DEMCR_VC_CORERESET_Pos 0U /*!< CoreDebug DEMCR: VC_CORERESET Position */ -#define CoreDebug_DEMCR_VC_CORERESET_Msk (1UL /*<< CoreDebug_DEMCR_VC_CORERESET_Pos*/) /*!< CoreDebug DEMCR: VC_CORERESET Mask */ - -/*@} end of group CMSIS_CoreDebug */ - - -/** - \ingroup CMSIS_core_register - \defgroup CMSIS_core_bitfield Core register bit field macros - \brief Macros for use with bit field definitions (xxx_Pos, xxx_Msk). - @{ - */ - -/** - \brief Mask and shift a bit field value for use in a register bit range. - \param[in] field Name of the register bit field. - \param[in] value Value of the bit field. This parameter is interpreted as an uint32_t type. - \return Masked and shifted value. -*/ -#define _VAL2FLD(field, value) (((uint32_t)(value) << field ## _Pos) & field ## _Msk) - -/** - \brief Mask and shift a register value to extract a bit filed value. - \param[in] field Name of the register bit field. - \param[in] value Value of register. This parameter is interpreted as an uint32_t type. - \return Masked and shifted bit field value. -*/ -#define _FLD2VAL(field, value) (((uint32_t)(value) & field ## _Msk) >> field ## _Pos) - -/*@} end of group CMSIS_core_bitfield */ - - -/** - \ingroup CMSIS_core_register - \defgroup CMSIS_core_base Core Definitions - \brief Definitions for base addresses, unions, and structures. - @{ - */ - -/* Memory mapping of Core Hardware */ -#define SCS_BASE (0xE000E000UL) /*!< System Control Space Base Address */ -#define ITM_BASE (0xE0000000UL) /*!< ITM Base Address */ -#define DWT_BASE (0xE0001000UL) /*!< DWT Base Address */ -#define TPI_BASE (0xE0040000UL) /*!< TPI Base Address */ -#define CoreDebug_BASE (0xE000EDF0UL) /*!< Core Debug Base Address */ -#define SysTick_BASE (SCS_BASE + 0x0010UL) /*!< SysTick Base Address */ -#define NVIC_BASE (SCS_BASE + 0x0100UL) /*!< NVIC Base Address */ -#define SCB_BASE (SCS_BASE + 0x0D00UL) /*!< System Control Block Base Address */ - -#define SCnSCB ((SCnSCB_Type *) SCS_BASE ) /*!< System control Register not in SCB */ -#define SCB ((SCB_Type *) SCB_BASE ) /*!< SCB configuration struct */ -#define SysTick ((SysTick_Type *) SysTick_BASE ) /*!< SysTick configuration struct */ -#define NVIC ((NVIC_Type *) NVIC_BASE ) /*!< NVIC configuration struct */ -#define ITM ((ITM_Type *) ITM_BASE ) /*!< ITM configuration struct */ -#define DWT ((DWT_Type *) DWT_BASE ) /*!< DWT configuration struct */ -#define TPI ((TPI_Type *) TPI_BASE ) /*!< TPI configuration struct */ -#define CoreDebug ((CoreDebug_Type *) CoreDebug_BASE) /*!< Core Debug configuration struct */ - -#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) - #define MPU_BASE (SCS_BASE + 0x0D90UL) /*!< Memory Protection Unit */ - #define MPU ((MPU_Type *) MPU_BASE ) /*!< Memory Protection Unit */ -#endif - -/*@} */ - - - -/******************************************************************************* - * Hardware Abstraction Layer - Core Function Interface contains: - - Core NVIC Functions - - Core SysTick Functions - - Core Debug Functions - - Core Register Access Functions - ******************************************************************************/ -/** - \defgroup CMSIS_Core_FunctionInterface Functions and Instructions Reference -*/ - - - -/* ########################## NVIC functions #################################### */ -/** - \ingroup CMSIS_Core_FunctionInterface - \defgroup CMSIS_Core_NVICFunctions NVIC Functions - \brief Functions that manage interrupts and exceptions via the NVIC. - @{ - */ - -#ifdef CMSIS_NVIC_VIRTUAL - #ifndef CMSIS_NVIC_VIRTUAL_HEADER_FILE - #define CMSIS_NVIC_VIRTUAL_HEADER_FILE "cmsis_nvic_virtual.h" - #endif - #include CMSIS_NVIC_VIRTUAL_HEADER_FILE -#else - #define NVIC_SetPriorityGrouping __NVIC_SetPriorityGrouping - #define NVIC_GetPriorityGrouping __NVIC_GetPriorityGrouping - #define NVIC_EnableIRQ __NVIC_EnableIRQ - #define NVIC_GetEnableIRQ __NVIC_GetEnableIRQ - #define NVIC_DisableIRQ __NVIC_DisableIRQ - #define NVIC_GetPendingIRQ __NVIC_GetPendingIRQ - #define NVIC_SetPendingIRQ __NVIC_SetPendingIRQ - #define NVIC_ClearPendingIRQ __NVIC_ClearPendingIRQ - #define NVIC_GetActive __NVIC_GetActive - #define NVIC_SetPriority __NVIC_SetPriority - #define NVIC_GetPriority __NVIC_GetPriority - #define NVIC_SystemReset __NVIC_SystemReset -#endif /* CMSIS_NVIC_VIRTUAL */ - -#ifdef CMSIS_VECTAB_VIRTUAL - #ifndef CMSIS_VECTAB_VIRTUAL_HEADER_FILE - #define CMSIS_VECTAB_VIRTUAL_HEADER_FILE "cmsis_vectab_virtual.h" - #endif - #include CMSIS_VECTAB_VIRTUAL_HEADER_FILE -#else - #define NVIC_SetVector __NVIC_SetVector - #define NVIC_GetVector __NVIC_GetVector -#endif /* (CMSIS_VECTAB_VIRTUAL) */ - -#define NVIC_USER_IRQ_OFFSET 16 - - - -/** - \brief Set Priority Grouping - \details Sets the priority grouping field using the required unlock sequence. - The parameter PriorityGroup is assigned to the field SCB->AIRCR [10:8] PRIGROUP field. - Only values from 0..7 are used. - In case of a conflict between priority grouping and available - priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set. - \param [in] PriorityGroup Priority grouping field. - */ -__STATIC_INLINE void __NVIC_SetPriorityGrouping(uint32_t PriorityGroup) -{ - uint32_t reg_value; - uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ - - reg_value = SCB->AIRCR; /* read old register configuration */ - reg_value &= ~((uint32_t)(SCB_AIRCR_VECTKEY_Msk | SCB_AIRCR_PRIGROUP_Msk)); /* clear bits to change */ - reg_value = (reg_value | - ((uint32_t)0x5FAUL << SCB_AIRCR_VECTKEY_Pos) | - (PriorityGroupTmp << 8U) ); /* Insert write key and priorty group */ - SCB->AIRCR = reg_value; -} - - -/** - \brief Get Priority Grouping - \details Reads the priority grouping field from the NVIC Interrupt Controller. - \return Priority grouping field (SCB->AIRCR [10:8] PRIGROUP field). - */ -__STATIC_INLINE uint32_t __NVIC_GetPriorityGrouping(void) -{ - return ((uint32_t)((SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) >> SCB_AIRCR_PRIGROUP_Pos)); -} - - -/** - \brief Enable Interrupt - \details Enables a device specific interrupt in the NVIC interrupt controller. - \param [in] IRQn Device specific interrupt number. - \note IRQn must not be negative. - */ -__STATIC_INLINE void __NVIC_EnableIRQ(IRQn_Type IRQn) -{ - if ((int32_t)(IRQn) >= 0) - { - NVIC->ISER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); - } -} - - -/** - \brief Get Interrupt Enable status - \details Returns a device specific interrupt enable status from the NVIC interrupt controller. - \param [in] IRQn Device specific interrupt number. - \return 0 Interrupt is not enabled. - \return 1 Interrupt is enabled. - \note IRQn must not be negative. - */ -__STATIC_INLINE uint32_t __NVIC_GetEnableIRQ(IRQn_Type IRQn) -{ - if ((int32_t)(IRQn) >= 0) - { - return((uint32_t)(((NVIC->ISER[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); - } - else - { - return(0U); - } -} - - -/** - \brief Disable Interrupt - \details Disables a device specific interrupt in the NVIC interrupt controller. - \param [in] IRQn Device specific interrupt number. - \note IRQn must not be negative. - */ -__STATIC_INLINE void __NVIC_DisableIRQ(IRQn_Type IRQn) -{ - if ((int32_t)(IRQn) >= 0) - { - NVIC->ICER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); - __DSB(); - __ISB(); - } -} - - -/** - \brief Get Pending Interrupt - \details Reads the NVIC pending register and returns the pending bit for the specified device specific interrupt. - \param [in] IRQn Device specific interrupt number. - \return 0 Interrupt status is not pending. - \return 1 Interrupt status is pending. - \note IRQn must not be negative. - */ -__STATIC_INLINE uint32_t __NVIC_GetPendingIRQ(IRQn_Type IRQn) -{ - if ((int32_t)(IRQn) >= 0) - { - return((uint32_t)(((NVIC->ISPR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); - } - else - { - return(0U); - } -} - - -/** - \brief Set Pending Interrupt - \details Sets the pending bit of a device specific interrupt in the NVIC pending register. - \param [in] IRQn Device specific interrupt number. - \note IRQn must not be negative. - */ -__STATIC_INLINE void __NVIC_SetPendingIRQ(IRQn_Type IRQn) -{ - if ((int32_t)(IRQn) >= 0) - { - NVIC->ISPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); - } -} - - -/** - \brief Clear Pending Interrupt - \details Clears the pending bit of a device specific interrupt in the NVIC pending register. - \param [in] IRQn Device specific interrupt number. - \note IRQn must not be negative. - */ -__STATIC_INLINE void __NVIC_ClearPendingIRQ(IRQn_Type IRQn) -{ - if ((int32_t)(IRQn) >= 0) - { - NVIC->ICPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); - } -} - - -/** - \brief Get Active Interrupt - \details Reads the active register in the NVIC and returns the active bit for the device specific interrupt. - \param [in] IRQn Device specific interrupt number. - \return 0 Interrupt status is not active. - \return 1 Interrupt status is active. - \note IRQn must not be negative. - */ -__STATIC_INLINE uint32_t __NVIC_GetActive(IRQn_Type IRQn) -{ - if ((int32_t)(IRQn) >= 0) - { - return((uint32_t)(((NVIC->IABR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); - } - else - { - return(0U); - } -} - - -/** - \brief Set Interrupt Priority - \details Sets the priority of a device specific interrupt or a processor exception. - The interrupt number can be positive to specify a device specific interrupt, - or negative to specify a processor exception. - \param [in] IRQn Interrupt number. - \param [in] priority Priority to set. - \note The priority cannot be set for every processor exception. - */ -__STATIC_INLINE void __NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority) -{ - if ((int32_t)(IRQn) >= 0) - { - NVIC->IP[((uint32_t)IRQn)] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL); - } - else - { - SCB->SHP[(((uint32_t)IRQn) & 0xFUL)-4UL] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL); - } -} - - -/** - \brief Get Interrupt Priority - \details Reads the priority of a device specific interrupt or a processor exception. - The interrupt number can be positive to specify a device specific interrupt, - or negative to specify a processor exception. - \param [in] IRQn Interrupt number. - \return Interrupt Priority. - Value is aligned automatically to the implemented priority bits of the microcontroller. - */ -__STATIC_INLINE uint32_t __NVIC_GetPriority(IRQn_Type IRQn) -{ - - if ((int32_t)(IRQn) >= 0) - { - return(((uint32_t)NVIC->IP[((uint32_t)IRQn)] >> (8U - __NVIC_PRIO_BITS))); - } - else - { - return(((uint32_t)SCB->SHP[(((uint32_t)IRQn) & 0xFUL)-4UL] >> (8U - __NVIC_PRIO_BITS))); - } -} - - -/** - \brief Encode Priority - \details Encodes the priority for an interrupt with the given priority group, - preemptive priority value, and subpriority value. - In case of a conflict between priority grouping and available - priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set. - \param [in] PriorityGroup Used priority group. - \param [in] PreemptPriority Preemptive priority value (starting from 0). - \param [in] SubPriority Subpriority value (starting from 0). - \return Encoded priority. Value can be used in the function \ref NVIC_SetPriority(). - */ -__STATIC_INLINE uint32_t NVIC_EncodePriority (uint32_t PriorityGroup, uint32_t PreemptPriority, uint32_t SubPriority) -{ - uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ - uint32_t PreemptPriorityBits; - uint32_t SubPriorityBits; - - PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp); - SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS)); - - return ( - ((PreemptPriority & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL)) << SubPriorityBits) | - ((SubPriority & (uint32_t)((1UL << (SubPriorityBits )) - 1UL))) - ); -} - - -/** - \brief Decode Priority - \details Decodes an interrupt priority value with a given priority group to - preemptive priority value and subpriority value. - In case of a conflict between priority grouping and available - priority bits (__NVIC_PRIO_BITS) the smallest possible priority group is set. - \param [in] Priority Priority value, which can be retrieved with the function \ref NVIC_GetPriority(). - \param [in] PriorityGroup Used priority group. - \param [out] pPreemptPriority Preemptive priority value (starting from 0). - \param [out] pSubPriority Subpriority value (starting from 0). - */ -__STATIC_INLINE void NVIC_DecodePriority (uint32_t Priority, uint32_t PriorityGroup, uint32_t* const pPreemptPriority, uint32_t* const pSubPriority) -{ - uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ - uint32_t PreemptPriorityBits; - uint32_t SubPriorityBits; - - PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp); - SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS)); - - *pPreemptPriority = (Priority >> SubPriorityBits) & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL); - *pSubPriority = (Priority ) & (uint32_t)((1UL << (SubPriorityBits )) - 1UL); -} - - -/** - \brief Set Interrupt Vector - \details Sets an interrupt vector in SRAM based interrupt vector table. - The interrupt number can be positive to specify a device specific interrupt, - or negative to specify a processor exception. - VTOR must been relocated to SRAM before. - \param [in] IRQn Interrupt number - \param [in] vector Address of interrupt handler function - */ -__STATIC_INLINE void __NVIC_SetVector(IRQn_Type IRQn, uint32_t vector) -{ - uint32_t *vectors = (uint32_t *)SCB->VTOR; - vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET] = vector; -} - - -/** - \brief Get Interrupt Vector - \details Reads an interrupt vector from interrupt vector table. - The interrupt number can be positive to specify a device specific interrupt, - or negative to specify a processor exception. - \param [in] IRQn Interrupt number. - \return Address of interrupt handler function - */ -__STATIC_INLINE uint32_t __NVIC_GetVector(IRQn_Type IRQn) -{ - uint32_t *vectors = (uint32_t *)SCB->VTOR; - return vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET]; -} - - -/** - \brief System Reset - \details Initiates a system reset request to reset the MCU. - */ -__STATIC_INLINE void __NVIC_SystemReset(void) -{ - __DSB(); /* Ensure all outstanding memory accesses included - buffered write are completed before reset */ - SCB->AIRCR = (uint32_t)((0x5FAUL << SCB_AIRCR_VECTKEY_Pos) | - (SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) | - SCB_AIRCR_SYSRESETREQ_Msk ); /* Keep priority group unchanged */ - __DSB(); /* Ensure completion of memory access */ - - for(;;) /* wait until reset */ - { - __NOP(); - } -} - -/*@} end of CMSIS_Core_NVICFunctions */ - - -/* ########################## FPU functions #################################### */ -/** - \ingroup CMSIS_Core_FunctionInterface - \defgroup CMSIS_Core_FpuFunctions FPU Functions - \brief Function that provides FPU type. - @{ - */ - -/** - \brief get FPU type - \details returns the FPU type - \returns - - \b 0: No FPU - - \b 1: Single precision FPU - - \b 2: Double + Single precision FPU - */ -__STATIC_INLINE uint32_t SCB_GetFPUType(void) -{ - return 0U; /* No FPU */ -} - - -/*@} end of CMSIS_Core_FpuFunctions */ - - - -/* ################################## SysTick function ############################################ */ -/** - \ingroup CMSIS_Core_FunctionInterface - \defgroup CMSIS_Core_SysTickFunctions SysTick Functions - \brief Functions that configure the System. - @{ - */ - -#if defined (__Vendor_SysTickConfig) && (__Vendor_SysTickConfig == 0U) - -/** - \brief System Tick Configuration - \details Initializes the System Timer and its interrupt, and starts the System Tick Timer. - Counter is in free running mode to generate periodic interrupts. - \param [in] ticks Number of ticks between two interrupts. - \return 0 Function succeeded. - \return 1 Function failed. - \note When the variable __Vendor_SysTickConfig is set to 1, then the - function SysTick_Config is not included. In this case, the file device.h - must contain a vendor-specific implementation of this function. - */ -__STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks) -{ - if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk) - { - return (1UL); /* Reload value impossible */ - } - - SysTick->LOAD = (uint32_t)(ticks - 1UL); /* set reload register */ - NVIC_SetPriority (SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */ - SysTick->VAL = 0UL; /* Load the SysTick Counter Value */ - SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk | - SysTick_CTRL_TICKINT_Msk | - SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */ - return (0UL); /* Function successful */ -} - -#endif - -/*@} end of CMSIS_Core_SysTickFunctions */ - - - -/* ##################################### Debug In/Output function ########################################### */ -/** - \ingroup CMSIS_Core_FunctionInterface - \defgroup CMSIS_core_DebugFunctions ITM Functions - \brief Functions that access the ITM debug interface. - @{ - */ - -extern volatile int32_t ITM_RxBuffer; /*!< External variable to receive characters. */ -#define ITM_RXBUFFER_EMPTY ((int32_t)0x5AA55AA5U) /*!< Value identifying \ref ITM_RxBuffer is ready for next character. */ - - -/** - \brief ITM Send Character - \details Transmits a character via the ITM channel 0, and - \li Just returns when no debugger is connected that has booked the output. - \li Is blocking when a debugger is connected, but the previous character sent has not been transmitted. - \param [in] ch Character to transmit. - \returns Character to transmit. - */ -__STATIC_INLINE uint32_t ITM_SendChar (uint32_t ch) -{ - if (((ITM->TCR & ITM_TCR_ITMENA_Msk) != 0UL) && /* ITM enabled */ - ((ITM->TER & 1UL ) != 0UL) ) /* ITM Port #0 enabled */ - { - while (ITM->PORT[0U].u32 == 0UL) - { - __NOP(); - } - ITM->PORT[0U].u8 = (uint8_t)ch; - } - return (ch); -} - - -/** - \brief ITM Receive Character - \details Inputs a character via the external variable \ref ITM_RxBuffer. - \return Received character. - \return -1 No character pending. - */ -__STATIC_INLINE int32_t ITM_ReceiveChar (void) -{ - int32_t ch = -1; /* no character available */ - - if (ITM_RxBuffer != ITM_RXBUFFER_EMPTY) - { - ch = ITM_RxBuffer; - ITM_RxBuffer = ITM_RXBUFFER_EMPTY; /* ready for next character */ - } - - return (ch); -} - - -/** - \brief ITM Check Character - \details Checks whether a character is pending for reading in the variable \ref ITM_RxBuffer. - \return 0 No character available. - \return 1 Character available. - */ -__STATIC_INLINE int32_t ITM_CheckChar (void) -{ - - if (ITM_RxBuffer == ITM_RXBUFFER_EMPTY) - { - return (0); /* no character available */ - } - else - { - return (1); /* character available */ - } -} - -/*@} end of CMSIS_core_DebugFunctions */ - - - - -#ifdef __cplusplus -} -#endif - -#endif /* __CORE_SC300_H_DEPENDANT */ - -#endif /* __CMSIS_GENERIC */ diff --git a/bsp/essemi/es32f0271/libraries/CMSIS/Include/mpu_armv7.h b/bsp/essemi/es32f0271/libraries/CMSIS/Include/mpu_armv7.h deleted file mode 100644 index aa180c9e59..0000000000 --- a/bsp/essemi/es32f0271/libraries/CMSIS/Include/mpu_armv7.h +++ /dev/null @@ -1,197 +0,0 @@ -/****************************************************************************** - * @file mpu_armv7.h - * @brief CMSIS MPU API for Armv7-M MPU - * @version V5.0.4 - * @date 10. January 2018 - ******************************************************************************/ -/* - * Copyright (c) 2017-2018 Arm Limited. All rights reserved. - * - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed under the Apache License, Version 2.0 (the License); you may - * not use this file except in compliance with the License. - * You may obtain a copy of the License at - * - * www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an AS IS BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - */ - -#if defined ( __ICCARM__ ) - #pragma system_include /* treat file as system include file for MISRA check */ -#elif defined (__clang__) - #pragma clang system_header /* treat file as system include file */ -#endif - -#ifndef ARM_MPU_ARMV7_H -#define ARM_MPU_ARMV7_H - -#define ARM_MPU_REGION_SIZE_32B ((uint8_t)0x04U) -#define ARM_MPU_REGION_SIZE_64B ((uint8_t)0x05U) -#define ARM_MPU_REGION_SIZE_128B ((uint8_t)0x06U) -#define ARM_MPU_REGION_SIZE_256B ((uint8_t)0x07U) -#define ARM_MPU_REGION_SIZE_512B ((uint8_t)0x08U) -#define ARM_MPU_REGION_SIZE_1KB ((uint8_t)0x09U) -#define ARM_MPU_REGION_SIZE_2KB ((uint8_t)0x0AU) -#define ARM_MPU_REGION_SIZE_4KB ((uint8_t)0x0BU) -#define ARM_MPU_REGION_SIZE_8KB ((uint8_t)0x0CU) -#define ARM_MPU_REGION_SIZE_16KB ((uint8_t)0x0DU) -#define ARM_MPU_REGION_SIZE_32KB ((uint8_t)0x0EU) -#define ARM_MPU_REGION_SIZE_64KB ((uint8_t)0x0FU) -#define ARM_MPU_REGION_SIZE_128KB ((uint8_t)0x10U) -#define ARM_MPU_REGION_SIZE_256KB ((uint8_t)0x11U) -#define ARM_MPU_REGION_SIZE_512KB ((uint8_t)0x12U) -#define ARM_MPU_REGION_SIZE_1MB ((uint8_t)0x13U) -#define ARM_MPU_REGION_SIZE_2MB ((uint8_t)0x14U) -#define ARM_MPU_REGION_SIZE_4MB ((uint8_t)0x15U) -#define ARM_MPU_REGION_SIZE_8MB ((uint8_t)0x16U) -#define ARM_MPU_REGION_SIZE_16MB ((uint8_t)0x17U) -#define ARM_MPU_REGION_SIZE_32MB ((uint8_t)0x18U) -#define ARM_MPU_REGION_SIZE_64MB ((uint8_t)0x19U) -#define ARM_MPU_REGION_SIZE_128MB ((uint8_t)0x1AU) -#define ARM_MPU_REGION_SIZE_256MB ((uint8_t)0x1BU) -#define ARM_MPU_REGION_SIZE_512MB ((uint8_t)0x1CU) -#define ARM_MPU_REGION_SIZE_1GB ((uint8_t)0x1DU) -#define ARM_MPU_REGION_SIZE_2GB ((uint8_t)0x1EU) -#define ARM_MPU_REGION_SIZE_4GB ((uint8_t)0x1FU) - -#define ARM_MPU_AP_NONE 0U -#define ARM_MPU_AP_PRIV 1U -#define ARM_MPU_AP_URO 2U -#define ARM_MPU_AP_FULL 3U -#define ARM_MPU_AP_PRO 5U -#define ARM_MPU_AP_RO 6U - -/** MPU Region Base Address Register Value -* -* \param Region The region to be configured, number 0 to 15. -* \param BaseAddress The base address for the region. -*/ -#define ARM_MPU_RBAR(Region, BaseAddress) \ - (((BaseAddress) & MPU_RBAR_ADDR_Msk) | \ - ((Region) & MPU_RBAR_REGION_Msk) | \ - (MPU_RBAR_VALID_Msk)) - -/** -* MPU Region Attribute and Size Register Value -* -* \param DisableExec Instruction access disable bit, 1= disable instruction fetches. -* \param AccessPermission Data access permissions, allows you to configure read/write access for User and Privileged mode. -* \param TypeExtField Type extension field, allows you to configure memory access type, for example strongly ordered, peripheral. -* \param IsShareable Region is shareable between multiple bus masters. -* \param IsCacheable Region is cacheable, i.e. its value may be kept in cache. -* \param IsBufferable Region is bufferable, i.e. using write-back caching. Cacheable but non-bufferable regions use write-through policy. -* \param SubRegionDisable Sub-region disable field. -* \param Size Region size of the region to be configured, for example 4K, 8K. -*/ -#define ARM_MPU_RASR(DisableExec, AccessPermission, TypeExtField, IsShareable, IsCacheable, IsBufferable, SubRegionDisable, Size) \ - ((((DisableExec ) << MPU_RASR_XN_Pos) & MPU_RASR_XN_Msk) | \ - (((AccessPermission) << MPU_RASR_AP_Pos) & MPU_RASR_AP_Msk) | \ - (((TypeExtField ) << MPU_RASR_TEX_Pos) & MPU_RASR_TEX_Msk) | \ - (((IsShareable ) << MPU_RASR_S_Pos) & MPU_RASR_S_Msk) | \ - (((IsCacheable ) << MPU_RASR_C_Pos) & MPU_RASR_C_Msk) | \ - (((IsBufferable ) << MPU_RASR_B_Pos) & MPU_RASR_B_Msk) | \ - (((SubRegionDisable) << MPU_RASR_SRD_Pos) & MPU_RASR_SRD_Msk) | \ - (((Size ) << MPU_RASR_SIZE_Pos) & MPU_RASR_SIZE_Msk) | \ - (MPU_RASR_ENABLE_Msk)) - - -/** -* Struct for a single MPU Region -*/ -typedef struct { - uint32_t RBAR; //!< The region base address register value (RBAR) - uint32_t RASR; //!< The region attribute and size register value (RASR) \ref MPU_RASR -} ARM_MPU_Region_t; - -/** Enable the MPU. -* \param MPU_Control Default access permissions for unconfigured regions. -*/ -__STATIC_INLINE void ARM_MPU_Enable(uint32_t MPU_Control) -{ - __DSB(); - __ISB(); - MPU->CTRL = MPU_Control | MPU_CTRL_ENABLE_Msk; -#ifdef SCB_SHCSR_MEMFAULTENA_Msk - SCB->SHCSR |= SCB_SHCSR_MEMFAULTENA_Msk; -#endif -} - -/** Disable the MPU. -*/ -__STATIC_INLINE void ARM_MPU_Disable(void) -{ - __DSB(); - __ISB(); -#ifdef SCB_SHCSR_MEMFAULTENA_Msk - SCB->SHCSR &= ~SCB_SHCSR_MEMFAULTENA_Msk; -#endif - MPU->CTRL &= ~MPU_CTRL_ENABLE_Msk; -} - -/** Clear and disable the given MPU region. -* \param rnr Region number to be cleared. -*/ -__STATIC_INLINE void ARM_MPU_ClrRegion(uint32_t rnr) -{ - MPU->RNR = rnr; - MPU->RASR = 0U; -} - -/** Configure an MPU region. -* \param rbar Value for RBAR register. -* \param rsar Value for RSAR register. -*/ -__STATIC_INLINE void ARM_MPU_SetRegion(uint32_t rbar, uint32_t rasr) -{ - MPU->RBAR = rbar; - MPU->RASR = rasr; -} - -/** Configure the given MPU region. -* \param rnr Region number to be configured. -* \param rbar Value for RBAR register. -* \param rsar Value for RSAR register. -*/ -__STATIC_INLINE void ARM_MPU_SetRegionEx(uint32_t rnr, uint32_t rbar, uint32_t rasr) -{ - MPU->RNR = rnr; - MPU->RBAR = rbar; - MPU->RASR = rasr; -} - -/** Memcopy with strictly ordered memory access, e.g. for register targets. -* \param dst Destination data is copied to. -* \param src Source data is copied from. -* \param len Amount of data words to be copied. -*/ -__STATIC_INLINE void orderedCpy(volatile uint32_t* dst, const uint32_t* __RESTRICT src, uint32_t len) -{ - uint32_t i; - for (i = 0U; i < len; ++i) - { - dst[i] = src[i]; - } -} - -/** Load the given number of MPU regions from a table. -* \param table Pointer to the MPU configuration table. -* \param cnt Amount of regions to be configured. -*/ -__STATIC_INLINE void ARM_MPU_Load(ARM_MPU_Region_t const* table, uint32_t cnt) -{ - const uint32_t rowWordSize = sizeof(ARM_MPU_Region_t)/4U; - while (cnt > MPU_TYPE_RALIASES) { - orderedCpy(&(MPU->RBAR), &(table->RBAR), MPU_TYPE_RALIASES*rowWordSize); - table += MPU_TYPE_RALIASES; - cnt -= MPU_TYPE_RALIASES; - } - orderedCpy(&(MPU->RBAR), &(table->RBAR), cnt*rowWordSize); -} - -#endif diff --git a/bsp/essemi/es32f0271/libraries/CMSIS/Include/mpu_armv8.h b/bsp/essemi/es32f0271/libraries/CMSIS/Include/mpu_armv8.h deleted file mode 100644 index 0ccfc74fe5..0000000000 --- a/bsp/essemi/es32f0271/libraries/CMSIS/Include/mpu_armv8.h +++ /dev/null @@ -1,333 +0,0 @@ -/****************************************************************************** - * @file mpu_armv8.h - * @brief CMSIS MPU API for Armv8-M MPU - * @version V5.0.4 - * @date 10. January 2018 - ******************************************************************************/ -/* - * Copyright (c) 2017-2018 Arm Limited. All rights reserved. - * - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed under the Apache License, Version 2.0 (the License); you may - * not use this file except in compliance with the License. - * You may obtain a copy of the License at - * - * www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an AS IS BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - */ - -#if defined ( __ICCARM__ ) - #pragma system_include /* treat file as system include file for MISRA check */ -#elif defined (__clang__) - #pragma clang system_header /* treat file as system include file */ -#endif - -#ifndef ARM_MPU_ARMV8_H -#define ARM_MPU_ARMV8_H - -/** \brief Attribute for device memory (outer only) */ -#define ARM_MPU_ATTR_DEVICE ( 0U ) - -/** \brief Attribute for non-cacheable, normal memory */ -#define ARM_MPU_ATTR_NON_CACHEABLE ( 4U ) - -/** \brief Attribute for normal memory (outer and inner) -* \param NT Non-Transient: Set to 1 for non-transient data. -* \param WB Write-Back: Set to 1 to use write-back update policy. -* \param RA Read Allocation: Set to 1 to use cache allocation on read miss. -* \param WA Write Allocation: Set to 1 to use cache allocation on write miss. -*/ -#define ARM_MPU_ATTR_MEMORY_(NT, WB, RA, WA) \ - (((NT & 1U) << 3U) | ((WB & 1U) << 2U) | ((RA & 1U) << 1U) | (WA & 1U)) - -/** \brief Device memory type non Gathering, non Re-ordering, non Early Write Acknowledgement */ -#define ARM_MPU_ATTR_DEVICE_nGnRnE (0U) - -/** \brief Device memory type non Gathering, non Re-ordering, Early Write Acknowledgement */ -#define ARM_MPU_ATTR_DEVICE_nGnRE (1U) - -/** \brief Device memory type non Gathering, Re-ordering, Early Write Acknowledgement */ -#define ARM_MPU_ATTR_DEVICE_nGRE (2U) - -/** \brief Device memory type Gathering, Re-ordering, Early Write Acknowledgement */ -#define ARM_MPU_ATTR_DEVICE_GRE (3U) - -/** \brief Memory Attribute -* \param O Outer memory attributes -* \param I O == ARM_MPU_ATTR_DEVICE: Device memory attributes, else: Inner memory attributes -*/ -#define ARM_MPU_ATTR(O, I) (((O & 0xFU) << 4U) | (((O & 0xFU) != 0U) ? (I & 0xFU) : ((I & 0x3U) << 2U))) - -/** \brief Normal memory non-shareable */ -#define ARM_MPU_SH_NON (0U) - -/** \brief Normal memory outer shareable */ -#define ARM_MPU_SH_OUTER (2U) - -/** \brief Normal memory inner shareable */ -#define ARM_MPU_SH_INNER (3U) - -/** \brief Memory access permissions -* \param RO Read-Only: Set to 1 for read-only memory. -* \param NP Non-Privileged: Set to 1 for non-privileged memory. -*/ -#define ARM_MPU_AP_(RO, NP) (((RO & 1U) << 1U) | (NP & 1U)) - -/** \brief Region Base Address Register value -* \param BASE The base address bits [31:5] of a memory region. The value is zero extended. Effective address gets 32 byte aligned. -* \param SH Defines the Shareability domain for this memory region. -* \param RO Read-Only: Set to 1 for a read-only memory region. -* \param NP Non-Privileged: Set to 1 for a non-privileged memory region. -* \oaram XN eXecute Never: Set to 1 for a non-executable memory region. -*/ -#define ARM_MPU_RBAR(BASE, SH, RO, NP, XN) \ - ((BASE & MPU_RBAR_BASE_Pos) | \ - ((SH << MPU_RBAR_SH_Pos) & MPU_RBAR_SH_Msk) | \ - ((ARM_MPU_AP_(RO, NP) << MPU_RBAR_AP_Pos) & MPU_RBAR_AP_Msk) | \ - ((XN << MPU_RBAR_XN_Pos) & MPU_RBAR_XN_Msk)) - -/** \brief Region Limit Address Register value -* \param LIMIT The limit address bits [31:5] for this memory region. The value is one extended. -* \param IDX The attribute index to be associated with this memory region. -*/ -#define ARM_MPU_RLAR(LIMIT, IDX) \ - ((LIMIT & MPU_RLAR_LIMIT_Msk) | \ - ((IDX << MPU_RLAR_AttrIndx_Pos) & MPU_RLAR_AttrIndx_Msk) | \ - (MPU_RLAR_EN_Msk)) - -/** -* Struct for a single MPU Region -*/ -typedef struct { - uint32_t RBAR; /*!< Region Base Address Register value */ - uint32_t RLAR; /*!< Region Limit Address Register value */ -} ARM_MPU_Region_t; - -/** Enable the MPU. -* \param MPU_Control Default access permissions for unconfigured regions. -*/ -__STATIC_INLINE void ARM_MPU_Enable(uint32_t MPU_Control) -{ - __DSB(); - __ISB(); - MPU->CTRL = MPU_Control | MPU_CTRL_ENABLE_Msk; -#ifdef SCB_SHCSR_MEMFAULTENA_Msk - SCB->SHCSR |= SCB_SHCSR_MEMFAULTENA_Msk; -#endif -} - -/** Disable the MPU. -*/ -__STATIC_INLINE void ARM_MPU_Disable(void) -{ - __DSB(); - __ISB(); -#ifdef SCB_SHCSR_MEMFAULTENA_Msk - SCB->SHCSR &= ~SCB_SHCSR_MEMFAULTENA_Msk; -#endif - MPU->CTRL &= ~MPU_CTRL_ENABLE_Msk; -} - -#ifdef MPU_NS -/** Enable the Non-secure MPU. -* \param MPU_Control Default access permissions for unconfigured regions. -*/ -__STATIC_INLINE void ARM_MPU_Enable_NS(uint32_t MPU_Control) -{ - __DSB(); - __ISB(); - MPU_NS->CTRL = MPU_Control | MPU_CTRL_ENABLE_Msk; -#ifdef SCB_SHCSR_MEMFAULTENA_Msk - SCB_NS->SHCSR |= SCB_SHCSR_MEMFAULTENA_Msk; -#endif -} - -/** Disable the Non-secure MPU. -*/ -__STATIC_INLINE void ARM_MPU_Disable_NS(void) -{ - __DSB(); - __ISB(); -#ifdef SCB_SHCSR_MEMFAULTENA_Msk - SCB_NS->SHCSR &= ~SCB_SHCSR_MEMFAULTENA_Msk; -#endif - MPU_NS->CTRL &= ~MPU_CTRL_ENABLE_Msk; -} -#endif - -/** Set the memory attribute encoding to the given MPU. -* \param mpu Pointer to the MPU to be configured. -* \param idx The attribute index to be set [0-7] -* \param attr The attribute value to be set. -*/ -__STATIC_INLINE void ARM_MPU_SetMemAttrEx(MPU_Type* mpu, uint8_t idx, uint8_t attr) -{ - const uint8_t reg = idx / 4U; - const uint32_t pos = ((idx % 4U) * 8U); - const uint32_t mask = 0xFFU << pos; - - if (reg >= (sizeof(mpu->MAIR) / sizeof(mpu->MAIR[0]))) { - return; // invalid index - } - - mpu->MAIR[reg] = ((mpu->MAIR[reg] & ~mask) | ((attr << pos) & mask)); -} - -/** Set the memory attribute encoding. -* \param idx The attribute index to be set [0-7] -* \param attr The attribute value to be set. -*/ -__STATIC_INLINE void ARM_MPU_SetMemAttr(uint8_t idx, uint8_t attr) -{ - ARM_MPU_SetMemAttrEx(MPU, idx, attr); -} - -#ifdef MPU_NS -/** Set the memory attribute encoding to the Non-secure MPU. -* \param idx The attribute index to be set [0-7] -* \param attr The attribute value to be set. -*/ -__STATIC_INLINE void ARM_MPU_SetMemAttr_NS(uint8_t idx, uint8_t attr) -{ - ARM_MPU_SetMemAttrEx(MPU_NS, idx, attr); -} -#endif - -/** Clear and disable the given MPU region of the given MPU. -* \param mpu Pointer to MPU to be used. -* \param rnr Region number to be cleared. -*/ -__STATIC_INLINE void ARM_MPU_ClrRegionEx(MPU_Type* mpu, uint32_t rnr) -{ - mpu->RNR = rnr; - mpu->RLAR = 0U; -} - -/** Clear and disable the given MPU region. -* \param rnr Region number to be cleared. -*/ -__STATIC_INLINE void ARM_MPU_ClrRegion(uint32_t rnr) -{ - ARM_MPU_ClrRegionEx(MPU, rnr); -} - -#ifdef MPU_NS -/** Clear and disable the given Non-secure MPU region. -* \param rnr Region number to be cleared. -*/ -__STATIC_INLINE void ARM_MPU_ClrRegion_NS(uint32_t rnr) -{ - ARM_MPU_ClrRegionEx(MPU_NS, rnr); -} -#endif - -/** Configure the given MPU region of the given MPU. -* \param mpu Pointer to MPU to be used. -* \param rnr Region number to be configured. -* \param rbar Value for RBAR register. -* \param rlar Value for RLAR register. -*/ -__STATIC_INLINE void ARM_MPU_SetRegionEx(MPU_Type* mpu, uint32_t rnr, uint32_t rbar, uint32_t rlar) -{ - mpu->RNR = rnr; - mpu->RBAR = rbar; - mpu->RLAR = rlar; -} - -/** Configure the given MPU region. -* \param rnr Region number to be configured. -* \param rbar Value for RBAR register. -* \param rlar Value for RLAR register. -*/ -__STATIC_INLINE void ARM_MPU_SetRegion(uint32_t rnr, uint32_t rbar, uint32_t rlar) -{ - ARM_MPU_SetRegionEx(MPU, rnr, rbar, rlar); -} - -#ifdef MPU_NS -/** Configure the given Non-secure MPU region. -* \param rnr Region number to be configured. -* \param rbar Value for RBAR register. -* \param rlar Value for RLAR register. -*/ -__STATIC_INLINE void ARM_MPU_SetRegion_NS(uint32_t rnr, uint32_t rbar, uint32_t rlar) -{ - ARM_MPU_SetRegionEx(MPU_NS, rnr, rbar, rlar); -} -#endif - -/** Memcopy with strictly ordered memory access, e.g. for register targets. -* \param dst Destination data is copied to. -* \param src Source data is copied from. -* \param len Amount of data words to be copied. -*/ -__STATIC_INLINE void orderedCpy(volatile uint32_t* dst, const uint32_t* __RESTRICT src, uint32_t len) -{ - uint32_t i; - for (i = 0U; i < len; ++i) - { - dst[i] = src[i]; - } -} - -/** Load the given number of MPU regions from a table to the given MPU. -* \param mpu Pointer to the MPU registers to be used. -* \param rnr First region number to be configured. -* \param table Pointer to the MPU configuration table. -* \param cnt Amount of regions to be configured. -*/ -__STATIC_INLINE void ARM_MPU_LoadEx(MPU_Type* mpu, uint32_t rnr, ARM_MPU_Region_t const* table, uint32_t cnt) -{ - const uint32_t rowWordSize = sizeof(ARM_MPU_Region_t)/4U; - if (cnt == 1U) { - mpu->RNR = rnr; - orderedCpy(&(mpu->RBAR), &(table->RBAR), rowWordSize); - } else { - uint32_t rnrBase = rnr & ~(MPU_TYPE_RALIASES-1U); - uint32_t rnrOffset = rnr % MPU_TYPE_RALIASES; - - mpu->RNR = rnrBase; - while ((rnrOffset + cnt) > MPU_TYPE_RALIASES) { - uint32_t c = MPU_TYPE_RALIASES - rnrOffset; - orderedCpy(&(mpu->RBAR)+(rnrOffset*2U), &(table->RBAR), c*rowWordSize); - table += c; - cnt -= c; - rnrOffset = 0U; - rnrBase += MPU_TYPE_RALIASES; - mpu->RNR = rnrBase; - } - - orderedCpy(&(mpu->RBAR)+(rnrOffset*2U), &(table->RBAR), cnt*rowWordSize); - } -} - -/** Load the given number of MPU regions from a table. -* \param rnr First region number to be configured. -* \param table Pointer to the MPU configuration table. -* \param cnt Amount of regions to be configured. -*/ -__STATIC_INLINE void ARM_MPU_Load(uint32_t rnr, ARM_MPU_Region_t const* table, uint32_t cnt) -{ - ARM_MPU_LoadEx(MPU, rnr, table, cnt); -} - -#ifdef MPU_NS -/** Load the given number of MPU regions from a table to the Non-secure MPU. -* \param rnr First region number to be configured. -* \param table Pointer to the MPU configuration table. -* \param cnt Amount of regions to be configured. -*/ -__STATIC_INLINE void ARM_MPU_Load_NS(uint32_t rnr, ARM_MPU_Region_t const* table, uint32_t cnt) -{ - ARM_MPU_LoadEx(MPU_NS, rnr, table, cnt); -} -#endif - -#endif - diff --git a/bsp/essemi/es32f0271/libraries/CMSIS/Include/tz_context.h b/bsp/essemi/es32f0271/libraries/CMSIS/Include/tz_context.h deleted file mode 100644 index 0d09749f3a..0000000000 --- a/bsp/essemi/es32f0271/libraries/CMSIS/Include/tz_context.h +++ /dev/null @@ -1,70 +0,0 @@ -/****************************************************************************** - * @file tz_context.h - * @brief Context Management for Armv8-M TrustZone - * @version V1.0.1 - * @date 10. January 2018 - ******************************************************************************/ -/* - * Copyright (c) 2017-2018 Arm Limited. All rights reserved. - * - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed under the Apache License, Version 2.0 (the License); you may - * not use this file except in compliance with the License. - * You may obtain a copy of the License at - * - * www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an AS IS BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - */ - -#if defined ( __ICCARM__ ) - #pragma system_include /* treat file as system include file for MISRA check */ -#elif defined (__clang__) - #pragma clang system_header /* treat file as system include file */ -#endif - -#ifndef TZ_CONTEXT_H -#define TZ_CONTEXT_H - -#include - -#ifndef TZ_MODULEID_T -#define TZ_MODULEID_T -/// \details Data type that identifies secure software modules called by a process. -typedef uint32_t TZ_ModuleId_t; -#endif - -/// \details TZ Memory ID identifies an allocated memory slot. -typedef uint32_t TZ_MemoryId_t; - -/// Initialize secure context memory system -/// \return execution status (1: success, 0: error) -uint32_t TZ_InitContextSystem_S (void); - -/// Allocate context memory for calling secure software modules in TrustZone -/// \param[in] module identifies software modules called from non-secure mode -/// \return value != 0 id TrustZone memory slot identifier -/// \return value 0 no memory available or internal error -TZ_MemoryId_t TZ_AllocModuleContext_S (TZ_ModuleId_t module); - -/// Free context memory that was previously allocated with \ref TZ_AllocModuleContext_S -/// \param[in] id TrustZone memory slot identifier -/// \return execution status (1: success, 0: error) -uint32_t TZ_FreeModuleContext_S (TZ_MemoryId_t id); - -/// Load secure context (called on RTOS thread context switch) -/// \param[in] id TrustZone memory slot identifier -/// \return execution status (1: success, 0: error) -uint32_t TZ_LoadContext_S (TZ_MemoryId_t id); - -/// Store secure context (called on RTOS thread context switch) -/// \param[in] id TrustZone memory slot identifier -/// \return execution status (1: success, 0: error) -uint32_t TZ_StoreContext_S (TZ_MemoryId_t id); - -#endif // TZ_CONTEXT_H diff --git a/bsp/essemi/es32f0271/libraries/CMSIS/RTOS/Template/cmsis_os.h b/bsp/essemi/es32f0271/libraries/CMSIS/RTOS/Template/cmsis_os.h deleted file mode 100644 index 02930af3e6..0000000000 --- a/bsp/essemi/es32f0271/libraries/CMSIS/RTOS/Template/cmsis_os.h +++ /dev/null @@ -1,707 +0,0 @@ -/* ---------------------------------------------------------------------- - * $Date: 5. February 2013 - * $Revision: V1.02 - * - * Project: CMSIS-RTOS API - * Title: cmsis_os.h template header file - * - * Version 0.02 - * Initial Proposal Phase - * Version 0.03 - * osKernelStart added, optional feature: main started as thread - * osSemaphores have standard behavior - * osTimerCreate does not start the timer, added osTimerStart - * osThreadPass is renamed to osThreadYield - * Version 1.01 - * Support for C++ interface - * - const attribute removed from the osXxxxDef_t typedef's - * - const attribute added to the osXxxxDef macros - * Added: osTimerDelete, osMutexDelete, osSemaphoreDelete - * Added: osKernelInitialize - * Version 1.02 - * Control functions for short timeouts in microsecond resolution: - * Added: osKernelSysTick, osKernelSysTickFrequency, osKernelSysTickMicroSec - * Removed: osSignalGet - *---------------------------------------------------------------------------- - * - * Copyright (c) 2013 ARM LIMITED - * All rights reserved. - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * - Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * - Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the distribution. - * - Neither the name of ARM nor the names of its contributors may be used - * to endorse or promote products derived from this software without - * specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" - * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE - * ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE - * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR - * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF - * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS - * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN - * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) - * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE - * POSSIBILITY OF SUCH DAMAGE. - *---------------------------------------------------------------------------*/ - - -#ifndef _CMSIS_OS_H -#define _CMSIS_OS_H - -/// \note MUST REMAIN UNCHANGED: \b osCMSIS identifies the CMSIS-RTOS API version. -#define osCMSIS 0x10002 ///< API version (main [31:16] .sub [15:0]) - -/// \note CAN BE CHANGED: \b osCMSIS_KERNEL identifies the underlying RTOS kernel and version number. -#define osCMSIS_KERNEL 0x10000 ///< RTOS identification and version (main [31:16] .sub [15:0]) - -/// \note MUST REMAIN UNCHANGED: \b osKernelSystemId shall be consistent in every CMSIS-RTOS. -#define osKernelSystemId "KERNEL V1.00" ///< RTOS identification string - -/// \note MUST REMAIN UNCHANGED: \b osFeature_xxx shall be consistent in every CMSIS-RTOS. -#define osFeature_MainThread 1 ///< main thread 1=main can be thread, 0=not available -#define osFeature_Pool 1 ///< Memory Pools: 1=available, 0=not available -#define osFeature_MailQ 1 ///< Mail Queues: 1=available, 0=not available -#define osFeature_MessageQ 1 ///< Message Queues: 1=available, 0=not available -#define osFeature_Signals 8 ///< maximum number of Signal Flags available per thread -#define osFeature_Semaphore 30 ///< maximum count for \ref osSemaphoreCreate function -#define osFeature_Wait 1 ///< osWait function: 1=available, 0=not available -#define osFeature_SysTick 1 ///< osKernelSysTick functions: 1=available, 0=not available - -#include -#include - -#ifdef __cplusplus -extern "C" -{ -#endif - - -// ==== Enumeration, structures, defines ==== - -/// Priority used for thread control. -/// \note MUST REMAIN UNCHANGED: \b osPriority shall be consistent in every CMSIS-RTOS. -typedef enum { - osPriorityIdle = -3, ///< priority: idle (lowest) - osPriorityLow = -2, ///< priority: low - osPriorityBelowNormal = -1, ///< priority: below normal - osPriorityNormal = 0, ///< priority: normal (default) - osPriorityAboveNormal = +1, ///< priority: above normal - osPriorityHigh = +2, ///< priority: high - osPriorityRealtime = +3, ///< priority: realtime (highest) - osPriorityError = 0x84 ///< system cannot determine priority or thread has illegal priority -} osPriority; - -/// Timeout value. -/// \note MUST REMAIN UNCHANGED: \b osWaitForever shall be consistent in every CMSIS-RTOS. -#define osWaitForever 0xFFFFFFFF ///< wait forever timeout value - -/// Status code values returned by CMSIS-RTOS functions. -/// \note MUST REMAIN UNCHANGED: \b osStatus shall be consistent in every CMSIS-RTOS. -typedef enum { - osOK = 0, ///< function completed; no error or event occurred. - osEventSignal = 0x08, ///< function completed; signal event occurred. - osEventMessage = 0x10, ///< function completed; message event occurred. - osEventMail = 0x20, ///< function completed; mail event occurred. - osEventTimeout = 0x40, ///< function completed; timeout occurred. - osErrorParameter = 0x80, ///< parameter error: a mandatory parameter was missing or specified an incorrect object. - osErrorResource = 0x81, ///< resource not available: a specified resource was not available. - osErrorTimeoutResource = 0xC1, ///< resource not available within given time: a specified resource was not available within the timeout period. - osErrorISR = 0x82, ///< not allowed in ISR context: the function cannot be called from interrupt service routines. - osErrorISRRecursive = 0x83, ///< function called multiple times from ISR with same object. - osErrorPriority = 0x84, ///< system cannot determine priority or thread has illegal priority. - osErrorNoMemory = 0x85, ///< system is out of memory: it was impossible to allocate or reserve memory for the operation. - osErrorValue = 0x86, ///< value of a parameter is out of range. - osErrorOS = 0xFF, ///< unspecified RTOS error: run-time error but no other error message fits. - os_status_reserved = 0x7FFFFFFF ///< prevent from enum down-size compiler optimization. -} osStatus; - - -/// Timer type value for the timer definition. -/// \note MUST REMAIN UNCHANGED: \b os_timer_type shall be consistent in every CMSIS-RTOS. -typedef enum { - osTimerOnce = 0, ///< one-shot timer - osTimerPeriodic = 1 ///< repeating timer -} os_timer_type; - -/// Entry point of a thread. -/// \note MUST REMAIN UNCHANGED: \b os_pthread shall be consistent in every CMSIS-RTOS. -typedef void (*os_pthread) (void const *argument); - -/// Entry point of a timer call back function. -/// \note MUST REMAIN UNCHANGED: \b os_ptimer shall be consistent in every CMSIS-RTOS. -typedef void (*os_ptimer) (void const *argument); - -// >>> the following data type definitions may shall adapted towards a specific RTOS - -/// Thread ID identifies the thread (pointer to a thread control block). -/// \note CAN BE CHANGED: \b os_thread_cb is implementation specific in every CMSIS-RTOS. -typedef struct os_thread_cb *osThreadId; - -/// Timer ID identifies the timer (pointer to a timer control block). -/// \note CAN BE CHANGED: \b os_timer_cb is implementation specific in every CMSIS-RTOS. -typedef struct os_timer_cb *osTimerId; - -/// Mutex ID identifies the mutex (pointer to a mutex control block). -/// \note CAN BE CHANGED: \b os_mutex_cb is implementation specific in every CMSIS-RTOS. -typedef struct os_mutex_cb *osMutexId; - -/// Semaphore ID identifies the semaphore (pointer to a semaphore control block). -/// \note CAN BE CHANGED: \b os_semaphore_cb is implementation specific in every CMSIS-RTOS. -typedef struct os_semaphore_cb *osSemaphoreId; - -/// Pool ID identifies the memory pool (pointer to a memory pool control block). -/// \note CAN BE CHANGED: \b os_pool_cb is implementation specific in every CMSIS-RTOS. -typedef struct os_pool_cb *osPoolId; - -/// Message ID identifies the message queue (pointer to a message queue control block). -/// \note CAN BE CHANGED: \b os_messageQ_cb is implementation specific in every CMSIS-RTOS. -typedef struct os_messageQ_cb *osMessageQId; - -/// Mail ID identifies the mail queue (pointer to a mail queue control block). -/// \note CAN BE CHANGED: \b os_mailQ_cb is implementation specific in every CMSIS-RTOS. -typedef struct os_mailQ_cb *osMailQId; - - -/// Thread Definition structure contains startup information of a thread. -/// \note CAN BE CHANGED: \b os_thread_def is implementation specific in every CMSIS-RTOS. -typedef struct os_thread_def { - os_pthread pthread; ///< start address of thread function - osPriority tpriority; ///< initial thread priority - uint32_t instances; ///< maximum number of instances of that thread function - uint32_t stacksize; ///< stack size requirements in bytes; 0 is default stack size -} osThreadDef_t; - -/// Timer Definition structure contains timer parameters. -/// \note CAN BE CHANGED: \b os_timer_def is implementation specific in every CMSIS-RTOS. -typedef struct os_timer_def { - os_ptimer ptimer; ///< start address of a timer function -} osTimerDef_t; - -/// Mutex Definition structure contains setup information for a mutex. -/// \note CAN BE CHANGED: \b os_mutex_def is implementation specific in every CMSIS-RTOS. -typedef struct os_mutex_def { - uint32_t dummy; ///< dummy value. -} osMutexDef_t; - -/// Semaphore Definition structure contains setup information for a semaphore. -/// \note CAN BE CHANGED: \b os_semaphore_def is implementation specific in every CMSIS-RTOS. -typedef struct os_semaphore_def { - uint32_t dummy; ///< dummy value. -} osSemaphoreDef_t; - -/// Definition structure for memory block allocation. -/// \note CAN BE CHANGED: \b os_pool_def is implementation specific in every CMSIS-RTOS. -typedef struct os_pool_def { - uint32_t pool_sz; ///< number of items (elements) in the pool - uint32_t item_sz; ///< size of an item - void *pool; ///< pointer to memory for pool -} osPoolDef_t; - -/// Definition structure for message queue. -/// \note CAN BE CHANGED: \b os_messageQ_def is implementation specific in every CMSIS-RTOS. -typedef struct os_messageQ_def { - uint32_t queue_sz; ///< number of elements in the queue - uint32_t item_sz; ///< size of an item - void *pool; ///< memory array for messages -} osMessageQDef_t; - -/// Definition structure for mail queue. -/// \note CAN BE CHANGED: \b os_mailQ_def is implementation specific in every CMSIS-RTOS. -typedef struct os_mailQ_def { - uint32_t queue_sz; ///< number of elements in the queue - uint32_t item_sz; ///< size of an item - void *pool; ///< memory array for mail -} osMailQDef_t; - -/// Event structure contains detailed information about an event. -/// \note MUST REMAIN UNCHANGED: \b os_event shall be consistent in every CMSIS-RTOS. -/// However the struct may be extended at the end. -typedef struct { - osStatus status; ///< status code: event or error information - union { - uint32_t v; ///< message as 32-bit value - void *p; ///< message or mail as void pointer - int32_t signals; ///< signal flags - } value; ///< event value - union { - osMailQId mail_id; ///< mail id obtained by \ref osMailCreate - osMessageQId message_id; ///< message id obtained by \ref osMessageCreate - } def; ///< event definition -} osEvent; - - -// ==== Kernel Control Functions ==== - -/// Initialize the RTOS Kernel for creating objects. -/// \return status code that indicates the execution status of the function. -/// \note MUST REMAIN UNCHANGED: \b osKernelInitialize shall be consistent in every CMSIS-RTOS. -osStatus osKernelInitialize (void); - -/// Start the RTOS Kernel. -/// \return status code that indicates the execution status of the function. -/// \note MUST REMAIN UNCHANGED: \b osKernelStart shall be consistent in every CMSIS-RTOS. -osStatus osKernelStart (void); - -/// Check if the RTOS kernel is already started. -/// \note MUST REMAIN UNCHANGED: \b osKernelRunning shall be consistent in every CMSIS-RTOS. -/// \return 0 RTOS is not started, 1 RTOS is started. -int32_t osKernelRunning(void); - -#if (defined (osFeature_SysTick) && (osFeature_SysTick != 0)) // System Timer available - -/// Get the RTOS kernel system timer counter -/// \note MUST REMAIN UNCHANGED: \b osKernelSysTick shall be consistent in every CMSIS-RTOS. -/// \return RTOS kernel system timer as 32-bit value -uint32_t osKernelSysTick (void); - -/// The RTOS kernel system timer frequency in Hz -/// \note Reflects the system timer setting and is typically defined in a configuration file. -#define osKernelSysTickFrequency 100000000 - -/// Convert a microseconds value to a RTOS kernel system timer value. -/// \param microsec time value in microseconds. -/// \return time value normalized to the \ref osKernelSysTickFrequency -#define osKernelSysTickMicroSec(microsec) (((uint64_t)microsec * (osKernelSysTickFrequency)) / 1000000) - -#endif // System Timer available - -// ==== Thread Management ==== - -/// Create a Thread Definition with function, priority, and stack requirements. -/// \param name name of the thread function. -/// \param priority initial priority of the thread function. -/// \param instances number of possible thread instances. -/// \param stacksz stack size (in bytes) requirements for the thread function. -/// \note CAN BE CHANGED: The parameters to \b osThreadDef shall be consistent but the -/// macro body is implementation specific in every CMSIS-RTOS. -#if defined (osObjectsExternal) // object is external -#define osThreadDef(name, priority, instances, stacksz) \ -extern const osThreadDef_t os_thread_def_##name -#else // define the object -#define osThreadDef(name, priority, instances, stacksz) \ -const osThreadDef_t os_thread_def_##name = \ -{ (name), (priority), (instances), (stacksz) } -#endif - -/// Access a Thread definition. -/// \param name name of the thread definition object. -/// \note CAN BE CHANGED: The parameter to \b osThread shall be consistent but the -/// macro body is implementation specific in every CMSIS-RTOS. -#define osThread(name) \ -&os_thread_def_##name - -/// Create a thread and add it to Active Threads and set it to state READY. -/// \param[in] thread_def thread definition referenced with \ref osThread. -/// \param[in] argument pointer that is passed to the thread function as start argument. -/// \return thread ID for reference by other functions or NULL in case of error. -/// \note MUST REMAIN UNCHANGED: \b osThreadCreate shall be consistent in every CMSIS-RTOS. -osThreadId osThreadCreate (const osThreadDef_t *thread_def, void *argument); - -/// Return the thread ID of the current running thread. -/// \return thread ID for reference by other functions or NULL in case of error. -/// \note MUST REMAIN UNCHANGED: \b osThreadGetId shall be consistent in every CMSIS-RTOS. -osThreadId osThreadGetId (void); - -/// Terminate execution of a thread and remove it from Active Threads. -/// \param[in] thread_id thread ID obtained by \ref osThreadCreate or \ref osThreadGetId. -/// \return status code that indicates the execution status of the function. -/// \note MUST REMAIN UNCHANGED: \b osThreadTerminate shall be consistent in every CMSIS-RTOS. -osStatus osThreadTerminate (osThreadId thread_id); - -/// Pass control to next thread that is in state \b READY. -/// \return status code that indicates the execution status of the function. -/// \note MUST REMAIN UNCHANGED: \b osThreadYield shall be consistent in every CMSIS-RTOS. -osStatus osThreadYield (void); - -/// Change priority of an active thread. -/// \param[in] thread_id thread ID obtained by \ref osThreadCreate or \ref osThreadGetId. -/// \param[in] priority new priority value for the thread function. -/// \return status code that indicates the execution status of the function. -/// \note MUST REMAIN UNCHANGED: \b osThreadSetPriority shall be consistent in every CMSIS-RTOS. -osStatus osThreadSetPriority (osThreadId thread_id, osPriority priority); - -/// Get current priority of an active thread. -/// \param[in] thread_id thread ID obtained by \ref osThreadCreate or \ref osThreadGetId. -/// \return current priority value of the thread function. -/// \note MUST REMAIN UNCHANGED: \b osThreadGetPriority shall be consistent in every CMSIS-RTOS. -osPriority osThreadGetPriority (osThreadId thread_id); - - -// ==== Generic Wait Functions ==== - -/// Wait for Timeout (Time Delay). -/// \param[in] millisec time delay value -/// \return status code that indicates the execution status of the function. -osStatus osDelay (uint32_t millisec); - -#if (defined (osFeature_Wait) && (osFeature_Wait != 0)) // Generic Wait available - -/// Wait for Signal, Message, Mail, or Timeout. -/// \param[in] millisec timeout value or 0 in case of no time-out -/// \return event that contains signal, message, or mail information or error code. -/// \note MUST REMAIN UNCHANGED: \b osWait shall be consistent in every CMSIS-RTOS. -osEvent osWait (uint32_t millisec); - -#endif // Generic Wait available - - -// ==== Timer Management Functions ==== -/// Define a Timer object. -/// \param name name of the timer object. -/// \param function name of the timer call back function. -/// \note CAN BE CHANGED: The parameter to \b osTimerDef shall be consistent but the -/// macro body is implementation specific in every CMSIS-RTOS. -#if defined (osObjectsExternal) // object is external -#define osTimerDef(name, function) \ -extern const osTimerDef_t os_timer_def_##name -#else // define the object -#define osTimerDef(name, function) \ -const osTimerDef_t os_timer_def_##name = \ -{ (function) } -#endif - -/// Access a Timer definition. -/// \param name name of the timer object. -/// \note CAN BE CHANGED: The parameter to \b osTimer shall be consistent but the -/// macro body is implementation specific in every CMSIS-RTOS. -#define osTimer(name) \ -&os_timer_def_##name - -/// Create a timer. -/// \param[in] timer_def timer object referenced with \ref osTimer. -/// \param[in] type osTimerOnce for one-shot or osTimerPeriodic for periodic behavior. -/// \param[in] argument argument to the timer call back function. -/// \return timer ID for reference by other functions or NULL in case of error. -/// \note MUST REMAIN UNCHANGED: \b osTimerCreate shall be consistent in every CMSIS-RTOS. -osTimerId osTimerCreate (const osTimerDef_t *timer_def, os_timer_type type, void *argument); - -/// Start or restart a timer. -/// \param[in] timer_id timer ID obtained by \ref osTimerCreate. -/// \param[in] millisec time delay value of the timer. -/// \return status code that indicates the execution status of the function. -/// \note MUST REMAIN UNCHANGED: \b osTimerStart shall be consistent in every CMSIS-RTOS. -osStatus osTimerStart (osTimerId timer_id, uint32_t millisec); - -/// Stop the timer. -/// \param[in] timer_id timer ID obtained by \ref osTimerCreate. -/// \return status code that indicates the execution status of the function. -/// \note MUST REMAIN UNCHANGED: \b osTimerStop shall be consistent in every CMSIS-RTOS. -osStatus osTimerStop (osTimerId timer_id); - -/// Delete a timer that was created by \ref osTimerCreate. -/// \param[in] timer_id timer ID obtained by \ref osTimerCreate. -/// \return status code that indicates the execution status of the function. -/// \note MUST REMAIN UNCHANGED: \b osTimerDelete shall be consistent in every CMSIS-RTOS. -osStatus osTimerDelete (osTimerId timer_id); - - -// ==== Signal Management ==== - -/// Set the specified Signal Flags of an active thread. -/// \param[in] thread_id thread ID obtained by \ref osThreadCreate or \ref osThreadGetId. -/// \param[in] signals specifies the signal flags of the thread that should be set. -/// \return previous signal flags of the specified thread or 0x80000000 in case of incorrect parameters. -/// \note MUST REMAIN UNCHANGED: \b osSignalSet shall be consistent in every CMSIS-RTOS. -int32_t osSignalSet (osThreadId thread_id, int32_t signals); - -/// Clear the specified Signal Flags of an active thread. -/// \param[in] thread_id thread ID obtained by \ref osThreadCreate or \ref osThreadGetId. -/// \param[in] signals specifies the signal flags of the thread that shall be cleared. -/// \return previous signal flags of the specified thread or 0x80000000 in case of incorrect parameters or call from ISR. -/// \note MUST REMAIN UNCHANGED: \b osSignalClear shall be consistent in every CMSIS-RTOS. -int32_t osSignalClear (osThreadId thread_id, int32_t signals); - -/// Wait for one or more Signal Flags to become signaled for the current \b RUNNING thread. -/// \param[in] signals wait until all specified signal flags set or 0 for any single signal flag. -/// \param[in] millisec timeout value or 0 in case of no time-out. -/// \return event flag information or error code. -/// \note MUST REMAIN UNCHANGED: \b osSignalWait shall be consistent in every CMSIS-RTOS. -osEvent osSignalWait (int32_t signals, uint32_t millisec); - - -// ==== Mutex Management ==== - -/// Define a Mutex. -/// \param name name of the mutex object. -/// \note CAN BE CHANGED: The parameter to \b osMutexDef shall be consistent but the -/// macro body is implementation specific in every CMSIS-RTOS. -#if defined (osObjectsExternal) // object is external -#define osMutexDef(name) \ -extern const osMutexDef_t os_mutex_def_##name -#else // define the object -#define osMutexDef(name) \ -const osMutexDef_t os_mutex_def_##name = { 0 } -#endif - -/// Access a Mutex definition. -/// \param name name of the mutex object. -/// \note CAN BE CHANGED: The parameter to \b osMutex shall be consistent but the -/// macro body is implementation specific in every CMSIS-RTOS. -#define osMutex(name) \ -&os_mutex_def_##name - -/// Create and Initialize a Mutex object. -/// \param[in] mutex_def mutex definition referenced with \ref osMutex. -/// \return mutex ID for reference by other functions or NULL in case of error. -/// \note MUST REMAIN UNCHANGED: \b osMutexCreate shall be consistent in every CMSIS-RTOS. -osMutexId osMutexCreate (const osMutexDef_t *mutex_def); - -/// Wait until a Mutex becomes available. -/// \param[in] mutex_id mutex ID obtained by \ref osMutexCreate. -/// \param[in] millisec timeout value or 0 in case of no time-out. -/// \return status code that indicates the execution status of the function. -/// \note MUST REMAIN UNCHANGED: \b osMutexWait shall be consistent in every CMSIS-RTOS. -osStatus osMutexWait (osMutexId mutex_id, uint32_t millisec); - -/// Release a Mutex that was obtained by \ref osMutexWait. -/// \param[in] mutex_id mutex ID obtained by \ref osMutexCreate. -/// \return status code that indicates the execution status of the function. -/// \note MUST REMAIN UNCHANGED: \b osMutexRelease shall be consistent in every CMSIS-RTOS. -osStatus osMutexRelease (osMutexId mutex_id); - -/// Delete a Mutex that was created by \ref osMutexCreate. -/// \param[in] mutex_id mutex ID obtained by \ref osMutexCreate. -/// \return status code that indicates the execution status of the function. -/// \note MUST REMAIN UNCHANGED: \b osMutexDelete shall be consistent in every CMSIS-RTOS. -osStatus osMutexDelete (osMutexId mutex_id); - - -// ==== Semaphore Management Functions ==== - -#if (defined (osFeature_Semaphore) && (osFeature_Semaphore != 0)) // Semaphore available - -/// Define a Semaphore object. -/// \param name name of the semaphore object. -/// \note CAN BE CHANGED: The parameter to \b osSemaphoreDef shall be consistent but the -/// macro body is implementation specific in every CMSIS-RTOS. -#if defined (osObjectsExternal) // object is external -#define osSemaphoreDef(name) \ -extern const osSemaphoreDef_t os_semaphore_def_##name -#else // define the object -#define osSemaphoreDef(name) \ -const osSemaphoreDef_t os_semaphore_def_##name = { 0 } -#endif - -/// Access a Semaphore definition. -/// \param name name of the semaphore object. -/// \note CAN BE CHANGED: The parameter to \b osSemaphore shall be consistent but the -/// macro body is implementation specific in every CMSIS-RTOS. -#define osSemaphore(name) \ -&os_semaphore_def_##name - -/// Create and Initialize a Semaphore object used for managing resources. -/// \param[in] semaphore_def semaphore definition referenced with \ref osSemaphore. -/// \param[in] count number of available resources. -/// \return semaphore ID for reference by other functions or NULL in case of error. -/// \note MUST REMAIN UNCHANGED: \b osSemaphoreCreate shall be consistent in every CMSIS-RTOS. -osSemaphoreId osSemaphoreCreate (const osSemaphoreDef_t *semaphore_def, int32_t count); - -/// Wait until a Semaphore token becomes available. -/// \param[in] semaphore_id semaphore object referenced with \ref osSemaphoreCreate. -/// \param[in] millisec timeout value or 0 in case of no time-out. -/// \return number of available tokens, or -1 in case of incorrect parameters. -/// \note MUST REMAIN UNCHANGED: \b osSemaphoreWait shall be consistent in every CMSIS-RTOS. -int32_t osSemaphoreWait (osSemaphoreId semaphore_id, uint32_t millisec); - -/// Release a Semaphore token. -/// \param[in] semaphore_id semaphore object referenced with \ref osSemaphoreCreate. -/// \return status code that indicates the execution status of the function. -/// \note MUST REMAIN UNCHANGED: \b osSemaphoreRelease shall be consistent in every CMSIS-RTOS. -osStatus osSemaphoreRelease (osSemaphoreId semaphore_id); - -/// Delete a Semaphore that was created by \ref osSemaphoreCreate. -/// \param[in] semaphore_id semaphore object referenced with \ref osSemaphoreCreate. -/// \return status code that indicates the execution status of the function. -/// \note MUST REMAIN UNCHANGED: \b osSemaphoreDelete shall be consistent in every CMSIS-RTOS. -osStatus osSemaphoreDelete (osSemaphoreId semaphore_id); - -#endif // Semaphore available - - -// ==== Memory Pool Management Functions ==== - -#if (defined (osFeature_Pool) && (osFeature_Pool != 0)) // Memory Pool Management available - -/// \brief Define a Memory Pool. -/// \param name name of the memory pool. -/// \param no maximum number of blocks (objects) in the memory pool. -/// \param type data type of a single block (object). -/// \note CAN BE CHANGED: The parameter to \b osPoolDef shall be consistent but the -/// macro body is implementation specific in every CMSIS-RTOS. -#if defined (osObjectsExternal) // object is external -#define osPoolDef(name, no, type) \ -extern const osPoolDef_t os_pool_def_##name -#else // define the object -#define osPoolDef(name, no, type) \ -const osPoolDef_t os_pool_def_##name = \ -{ (no), sizeof(type), NULL } -#endif - -/// \brief Access a Memory Pool definition. -/// \param name name of the memory pool -/// \note CAN BE CHANGED: The parameter to \b osPool shall be consistent but the -/// macro body is implementation specific in every CMSIS-RTOS. -#define osPool(name) \ -&os_pool_def_##name - -/// Create and Initialize a memory pool. -/// \param[in] pool_def memory pool definition referenced with \ref osPool. -/// \return memory pool ID for reference by other functions or NULL in case of error. -/// \note MUST REMAIN UNCHANGED: \b osPoolCreate shall be consistent in every CMSIS-RTOS. -osPoolId osPoolCreate (const osPoolDef_t *pool_def); - -/// Allocate a memory block from a memory pool. -/// \param[in] pool_id memory pool ID obtain referenced with \ref osPoolCreate. -/// \return address of the allocated memory block or NULL in case of no memory available. -/// \note MUST REMAIN UNCHANGED: \b osPoolAlloc shall be consistent in every CMSIS-RTOS. -void *osPoolAlloc (osPoolId pool_id); - -/// Allocate a memory block from a memory pool and set memory block to zero. -/// \param[in] pool_id memory pool ID obtain referenced with \ref osPoolCreate. -/// \return address of the allocated memory block or NULL in case of no memory available. -/// \note MUST REMAIN UNCHANGED: \b osPoolCAlloc shall be consistent in every CMSIS-RTOS. -void *osPoolCAlloc (osPoolId pool_id); - -/// Return an allocated memory block back to a specific memory pool. -/// \param[in] pool_id memory pool ID obtain referenced with \ref osPoolCreate. -/// \param[in] block address of the allocated memory block that is returned to the memory pool. -/// \return status code that indicates the execution status of the function. -/// \note MUST REMAIN UNCHANGED: \b osPoolFree shall be consistent in every CMSIS-RTOS. -osStatus osPoolFree (osPoolId pool_id, void *block); - -#endif // Memory Pool Management available - - -// ==== Message Queue Management Functions ==== - -#if (defined (osFeature_MessageQ) && (osFeature_MessageQ != 0)) // Message Queues available - -/// \brief Create a Message Queue Definition. -/// \param name name of the queue. -/// \param queue_sz maximum number of messages in the queue. -/// \param type data type of a single message element (for debugger). -/// \note CAN BE CHANGED: The parameter to \b osMessageQDef shall be consistent but the -/// macro body is implementation specific in every CMSIS-RTOS. -#if defined (osObjectsExternal) // object is external -#define osMessageQDef(name, queue_sz, type) \ -extern const osMessageQDef_t os_messageQ_def_##name -#else // define the object -#define osMessageQDef(name, queue_sz, type) \ -const osMessageQDef_t os_messageQ_def_##name = \ -{ (queue_sz), sizeof (type) } -#endif - -/// \brief Access a Message Queue Definition. -/// \param name name of the queue -/// \note CAN BE CHANGED: The parameter to \b osMessageQ shall be consistent but the -/// macro body is implementation specific in every CMSIS-RTOS. -#define osMessageQ(name) \ -&os_messageQ_def_##name - -/// Create and Initialize a Message Queue. -/// \param[in] queue_def queue definition referenced with \ref osMessageQ. -/// \param[in] thread_id thread ID (obtained by \ref osThreadCreate or \ref osThreadGetId) or NULL. -/// \return message queue ID for reference by other functions or NULL in case of error. -/// \note MUST REMAIN UNCHANGED: \b osMessageCreate shall be consistent in every CMSIS-RTOS. -osMessageQId osMessageCreate (const osMessageQDef_t *queue_def, osThreadId thread_id); - -/// Put a Message to a Queue. -/// \param[in] queue_id message queue ID obtained with \ref osMessageCreate. -/// \param[in] info message information. -/// \param[in] millisec timeout value or 0 in case of no time-out. -/// \return status code that indicates the execution status of the function. -/// \note MUST REMAIN UNCHANGED: \b osMessagePut shall be consistent in every CMSIS-RTOS. -osStatus osMessagePut (osMessageQId queue_id, uint32_t info, uint32_t millisec); - -/// Get a Message or Wait for a Message from a Queue. -/// \param[in] queue_id message queue ID obtained with \ref osMessageCreate. -/// \param[in] millisec timeout value or 0 in case of no time-out. -/// \return event information that includes status code. -/// \note MUST REMAIN UNCHANGED: \b osMessageGet shall be consistent in every CMSIS-RTOS. -osEvent osMessageGet (osMessageQId queue_id, uint32_t millisec); - -#endif // Message Queues available - - -// ==== Mail Queue Management Functions ==== - -#if (defined (osFeature_MailQ) && (osFeature_MailQ != 0)) // Mail Queues available - -/// \brief Create a Mail Queue Definition. -/// \param name name of the queue -/// \param queue_sz maximum number of messages in queue -/// \param type data type of a single message element -/// \note CAN BE CHANGED: The parameter to \b osMailQDef shall be consistent but the -/// macro body is implementation specific in every CMSIS-RTOS. -#if defined (osObjectsExternal) // object is external -#define osMailQDef(name, queue_sz, type) \ -extern const osMailQDef_t os_mailQ_def_##name -#else // define the object -#define osMailQDef(name, queue_sz, type) \ -const osMailQDef_t os_mailQ_def_##name = \ -{ (queue_sz), sizeof (type) } -#endif - -/// \brief Access a Mail Queue Definition. -/// \param name name of the queue -/// \note CAN BE CHANGED: The parameter to \b osMailQ shall be consistent but the -/// macro body is implementation specific in every CMSIS-RTOS. -#define osMailQ(name) \ -&os_mailQ_def_##name - -/// Create and Initialize mail queue. -/// \param[in] queue_def reference to the mail queue definition obtain with \ref osMailQ -/// \param[in] thread_id thread ID (obtained by \ref osThreadCreate or \ref osThreadGetId) or NULL. -/// \return mail queue ID for reference by other functions or NULL in case of error. -/// \note MUST REMAIN UNCHANGED: \b osMailCreate shall be consistent in every CMSIS-RTOS. -osMailQId osMailCreate (const osMailQDef_t *queue_def, osThreadId thread_id); - -/// Allocate a memory block from a mail. -/// \param[in] queue_id mail queue ID obtained with \ref osMailCreate. -/// \param[in] millisec timeout value or 0 in case of no time-out -/// \return pointer to memory block that can be filled with mail or NULL in case of error. -/// \note MUST REMAIN UNCHANGED: \b osMailAlloc shall be consistent in every CMSIS-RTOS. -void *osMailAlloc (osMailQId queue_id, uint32_t millisec); - -/// Allocate a memory block from a mail and set memory block to zero. -/// \param[in] queue_id mail queue ID obtained with \ref osMailCreate. -/// \param[in] millisec timeout value or 0 in case of no time-out -/// \return pointer to memory block that can be filled with mail or NULL in case of error. -/// \note MUST REMAIN UNCHANGED: \b osMailCAlloc shall be consistent in every CMSIS-RTOS. -void *osMailCAlloc (osMailQId queue_id, uint32_t millisec); - -/// Put a mail to a queue. -/// \param[in] queue_id mail queue ID obtained with \ref osMailCreate. -/// \param[in] mail memory block previously allocated with \ref osMailAlloc or \ref osMailCAlloc. -/// \return status code that indicates the execution status of the function. -/// \note MUST REMAIN UNCHANGED: \b osMailPut shall be consistent in every CMSIS-RTOS. -osStatus osMailPut (osMailQId queue_id, void *mail); - -/// Get a mail from a queue. -/// \param[in] queue_id mail queue ID obtained with \ref osMailCreate. -/// \param[in] millisec timeout value or 0 in case of no time-out -/// \return event that contains mail information or error code. -/// \note MUST REMAIN UNCHANGED: \b osMailGet shall be consistent in every CMSIS-RTOS. -osEvent osMailGet (osMailQId queue_id, uint32_t millisec); - -/// Free a memory block from a mail. -/// \param[in] queue_id mail queue ID obtained with \ref osMailCreate. -/// \param[in] mail pointer to the memory block that was obtained with \ref osMailGet. -/// \return status code that indicates the execution status of the function. -/// \note MUST REMAIN UNCHANGED: \b osMailFree shall be consistent in every CMSIS-RTOS. -osStatus osMailFree (osMailQId queue_id, void *mail); - -#endif // Mail Queues available - - -#ifdef __cplusplus -} -#endif - -#endif // _CMSIS_OS_H diff --git a/bsp/essemi/es32f0271/libraries/CMSIS/index.html b/bsp/essemi/es32f0271/libraries/CMSIS/index.html deleted file mode 100644 index c6da0802b4..0000000000 --- a/bsp/essemi/es32f0271/libraries/CMSIS/index.html +++ /dev/null @@ -1,14 +0,0 @@ - - - -Redirect to the CMSIS main page after 0 seconds - - - - - - -If the automatic redirection is failing, click open CMSIS Documentation. - - - diff --git a/bsp/essemi/es32f0271/libraries/ES32F027x_MD_StdPeriph_Driver/Include/md_ad16c4t.h b/bsp/essemi/es32f0271/libraries/ES32F027x_MD_StdPeriph_Driver/Include/md_ad16c4t.h deleted file mode 100644 index 672719a20b..0000000000 --- a/bsp/essemi/es32f0271/libraries/ES32F027x_MD_StdPeriph_Driver/Include/md_ad16c4t.h +++ /dev/null @@ -1,4484 +0,0 @@ -/** - ************************************************************************************** - * @file md_AD16C4T.h - * @brief ES32F0271 Header file of MD AD16C4T module. - * - * @version V0.01 - * @date 3/12/2018 - * @author Eastsoft AE Team - * @note - * - * Copyright (C) 2018 Shanghai Eastsoft Microelectronics Co., Ltd. AMD rights reserved. - * - ************************************************************************************** - */ - /* Define to prevent recursive inclusion -------------------------------------*/ -#ifndef __MD_AD16C4T_H__ -#define __MD_AD16C4T_H__ - -#ifdef __cplusplus -extern "C"{ -#endif - -/* Includes -------------------------------------------------------*/ -#include "es32f0271.h" -#include "reg_ad16c4t.h" - - -/** @addtogroup Micro_Driver - * @{ - */ -#if defined (AD16C4T1) - -/** @defgroup AD16C4T AD16C4T - * @brief AD16C4T module driver - * @{ - */ - - -/* Private types --------------------------------------------------------------*/ -/* Private variables ----------------------------------------------------------*/ -/* Private constants ----------------------------------------------------------*/ -/* Private Macros ----------------------------------------------------------*/ - - - -/* Public Constants -----------------------------------------------------------*/ - -/** @defgroup MD_AD16C4T_Public_Constants Public Constants - * @brief AD16C4T module driver - * @{ - */ -/* AD16C4T_CON1 macros define*/ -#define MD_AD16C4T_DEBUGSELECT_INPUT (0 << AD16C4T_CON1_DBGSEL_POS) /*!< Channel input*/ -#define MD_AD16C4T_DEBUGSELECT_OUTPUT (1 << AD16C4T_CON1_DBGSEL_POS) /*!< Channel output*/ - -#define MD_AD16C4T_COMPAREINPUT_DISABLE (0 << AD16C4T_CON1_CMPSEL_POSS) /*!< Compare input is disabled*/ -#define MD_AD16C4T_COMPAREINPUT_0 (1 << AD16C4T_CON1_CMPSEL_POSS) /*!< Compare input(CMP_IN)=Compare output 0*/ -#define MD_AD16C4T_COMPAREINPUT_1 (2 << AD16C4T_CON1_CMPSEL_POSS) /*!< Compare input(CMP_IN)=Compare output 1*/ -#define MD_AD16C4T_COMPAREINPUT_2 (3 << AD16C4T_CON1_CMPSEL_POSS) /*!< Compare input(CMP_IN)=Compare output 2*/ -#define MD_AD16C4T_COMPAREINPUT_3 (4 << AD16C4T_CON1_CMPSEL_POSS) /*!< Compare input(CMP_IN)=Compare output 3*/ - -#define MD_AD16C4T_COMPAREPOLARITY_LOW (0 << AD16C4T_CON1_CMPSELP_POS) /*!< Compare input is active low*/ -#define MD_AD16C4T_COMPAREPOLARITY_HIGH (1 << AD16C4T_CON1_CMPSELP_POS) /*!< Compare input is active high*/ - -#define MD_AD16C4T_CLOCKDIVSION_DIV1 (0 << AD16C4T_CON1_DFCKSEL_POSS) /*!< tDTS=tCK_INT*/ -#define MD_AD16C4T_CLOCKDIVSION_DIV2 (1 << AD16C4T_CON1_DFCKSEL_POSS) /*!< tDTS=2*tCK_INT*/ -#define MD_AD16C4T_CLOCKDIVSION_DIV4 (2 << AD16C4T_CON1_DFCKSEL_POSS) /*!< tDTS=4*tCK_INT*/ - -#define MD_AD16C4T_CENTERALIGNED_DISABLE (0 << AD16C4T_CON1_CMSEL_POSS) /*!< Edge-aligned mode*/ -#define MD_AD16C4T_CENTERALIGNED_DOWN (1 << AD16C4T_CON1_CMSEL_POSS) /*!< Center-aligned mode 1*/ -#define MD_AD16C4T_CENTERALIGNED_UP (2 << AD16C4T_CON1_CMSEL_POSS) /*!< Center-aligned mode 2*/ -#define MD_AD16C4T_CENTERALIGNED_BOTH (3 << AD16C4T_CON1_CMSEL_POSS) /*!< Center-aligned mode 3*/ - -#define MD_AD16C4T_UPCOUNTER (0 << AD16C4T_CON1_DIRSEL_POS) /*!< Counter used as upcounter*/ -#define MD_AD16C4T_DOWNCOUNTER (1 << AD16C4T_CON1_DIRSEL_POS) /*!< Counter used as downcounter*/ - -#define MD_AD16C4T_ONEPULSEMODE_DISABLE (0 << AD16C4T_CON1_SPMEN_POS) /*!< Counter is not stopped at update event*/ -#define MD_AD16C4T_ONEPULSEMODE_ENABLE (1 << AD16C4T_CON1_SPMEN_POS) /*!< Counter stops counting at the next update event*/ - -#define MD_AD16C4T_UPDATESOURCE_NORMAL (0 << AD16C4T_CON1_UERSEL_POS) /*!< Counter overflow/underflow, Setting the UG bit, Update generation through the slave mode controller generate an update interrupt*/ -#define MD_AD16C4T_UPDATESOURCE_COUNTER (1 << AD16C4T_CON1_UERSEL_POS) /*!< Only counter overflow/underflow generates an update interrupt or DMA request if Enabled*/ - -/* AD16C4T_CON2 macros define*/ -#define MD_AD16C4T_IDLEOUTPUT_LOW 0 /*!< OC1=0 (after a dead-time if OC1N is implemented) when MOE=0*/ -#define MD_AD16C4T_IDLEOUTPUT_HIGH 1 /*!< OC1=1 (after a dead-time if OC1N is implemented) when MOE=0*/ - -#define MD_AD16C4T_TI1INPUT_CH1 (0 << AD16C4T_CON2_I1SEL_POS) /*!< The TIMx_CH1 pin is connected to TI1 input*/ -#define MD_AD16C4T_TI1INPUT_XOR (1 << AD16C4T_CON2_I1SEL_POS) /*!< The TIMx_CH1, CH2 and CH3 pins are connected to the TI1 input (XOR combination)*/ - -#define MD_AD16C4T_MASTERMODE_RESET (0 << AD16C4T_CON2_MMSEL_POSS) /*!< Reset mode*/ -#define MD_AD16C4T_MASTERMODE_ENABLE (1 << AD16C4T_CON2_MMSEL_POSS) /*!< Enable mode*/ -#define MD_AD16C4T_MASTERMODE_UPDATE (2 << AD16C4T_CON2_MMSEL_POSS) /*!< Update mode*/ -#define MD_AD16C4T_MASTERMODE_COMPAREPULSE (3 << AD16C4T_CON2_MMSEL_POSS) /*!< Compare Pulse mode*/ -#define MD_AD16C4T_MASTERMODE_COMPARE1 (4 << AD16C4T_CON2_MMSEL_POSS) /*!< Compare 1 mode*/ -#define MD_AD16C4T_MASTERMODE_COMPARE2 (5 << AD16C4T_CON2_MMSEL_POSS) /*!< Compare 2 mode*/ -#define MD_AD16C4T_MASTERMODE_COMPARE3 (6 << AD16C4T_CON2_MMSEL_POSS) /*!< Compare 3 mode*/ -#define MD_AD16C4T_MASTERMODE_COMPARE4 (7 << AD16C4T_CON2_MMSEL_POSS) /*!< Compare 4 mode*/ - -#define MD_AD16C4T_DMASELECTION_COMPARE (0 << AD16C4T_CON2_CCDMASEL_POS) /*!< CCx DMA request sent when CCx event occurs*/ -#define MD_AD16C4T_DMASELECTION_UPDATE (1 << AD16C4T_CON2_CCDMASEL_POS) /*!< CCx DMA requests sent when update event occurs*/ - -#define MD_AD16C4T_UPDATESELECTION_COMG (0 << AD16C4T_CON2_CCUSEL_POS) /*!< When capture/compare control bits are preloaded (CCPC=1), they are updated by setting the COMG bit only*/ -#define MD_AD16C4T_UPDATESELECTION_BOTH (1 << AD16C4T_CON2_CCUSEL_POS) /*!< When capture/compare control bits are preloaded (CCPC=1), they are updated by setting the COMG bit or when an rising edge occurs on TRGI*/ - -#define MD_AD16C4T_CCPRELOAD_DISABLE (0 << AD16C4T_CON2_CCPCEN_POS) /*!< CCxE, CCxNE and OCxM bits are not preloaded*/ -#define MD_AD16C4T_CCPRELOAD_ENABLE (1 << AD16C4T_CON2_CCPCEN_POS) /*!< CCxE, CCxNE and OCxM bits are preloaded*/ - -/* AD16C4T_SMCON macros define*/ -#define MD_AD16C4T_ETRPOLARITY_NONINVERTED (0 << AD16C4T_SMCON_ETPOL_POS) /*!< ETR is non-inverted*/ -#define MD_AD16C4T_ETRPOLARITY_INVERTED (1 << AD16C4T_SMCON_ETPOL_POS) /*!< ETR is inverted*/ - -#define MD_AD16C4T_ETRFILTER_FDIV1 (0 << AD16C4T_SMCON_ETFLT_POSS) /*!< No filter*/ -#define MD_AD16C4T_ETRFILTER_FDIV1N2 (1 << AD16C4T_SMCON_ETFLT_POSS) /*!< fSAMPLING = fCK_INT, N = 2*/ -#define MD_AD16C4T_ETRFILTER_FDIV1N4 (2 << AD16C4T_SMCON_ETFLT_POSS) /*!< fSAMPLING = fCK_INT, N = 4*/ -#define MD_AD16C4T_ETRFILTER_FDIV1N8 (3 << AD16C4T_SMCON_ETFLT_POSS) /*!< fSAMPLING = fCK_INT, N = 8*/ -#define MD_AD16C4T_ETRFILTER_FDIV2N6 (4 << AD16C4T_SMCON_ETFLT_POSS) /*!< fSAMPLING = fDTS / 2, N = 6*/ -#define MD_AD16C4T_ETRFILTER_FDIV2N8 (5 << AD16C4T_SMCON_ETFLT_POSS) /*!< fSAMPLING = fDTS / 2, N = 8*/ -#define MD_AD16C4T_ETRFILTER_FDIV4N6 (6 << AD16C4T_SMCON_ETFLT_POSS) /*!< fSAMPLING = fDTS / 4, N = 6*/ -#define MD_AD16C4T_ETRFILTER_FDIV4N8 (7 << AD16C4T_SMCON_ETFLT_POSS) /*!< fSAMPLING = fDTS / 4, N = 8*/ -#define MD_AD16C4T_ETRFILTER_FDIV8N6 (8 << AD16C4T_SMCON_ETFLT_POSS) /*!< fSAMPLING = fDTS / 8, N = 6*/ -#define MD_AD16C4T_ETRFILTER_FDIV8N8 (9 << AD16C4T_SMCON_ETFLT_POSS) /*!< fSAMPLING = fDTS / 8, N = 8*/ -#define MD_AD16C4T_ETRFILTER_FDIV16N5 (10 << AD16C4T_SMCON_ETFLT_POSS) /*!< fSAMPLING = fDTS / 16, N = 5*/ -#define MD_AD16C4T_ETRFILTER_FDIV16N6 (11 << AD16C4T_SMCON_ETFLT_POSS) /*!< fSAMPLING = fDTS / 16, N = 6*/ -#define MD_AD16C4T_ETRFILTER_FDIV16N8 (12 << AD16C4T_SMCON_ETFLT_POSS) /*!< fSAMPLING = fDTS / 16, N = 8*/ -#define MD_AD16C4T_ETRFILTER_FDIV32N5 (13 << AD16C4T_SMCON_ETFLT_POSS) /*!< fSAMPLING = fDTS / 32, N = 5*/ -#define MD_AD16C4T_ETRFILTER_FDIV32N6 (14 << AD16C4T_SMCON_ETFLT_POSS) /*!< fSAMPLING = fDTS / 32, N = 6*/ -#define MD_AD16C4T_ETRFILTER_FDIV32N8 (15 << AD16C4T_SMCON_ETFLT_POSS) /*!< fSAMPLING = fDTS / 32, N = 8*/ - -#define MD_AD16C4T_MASTERSLAVE_NODELAY (0 << AD16C4T_SMCON_MSCFG_POS) /*!< No action*/ -#define MD_AD16C4T_MASTERSLAVE_DELAY (1 << AD16C4T_SMCON_MSCFG_POS) /*!< The effect of an event on the trigger input (TRGI) is delayed to allow a perfect*/ - -#define MD_AD16C4T_TRIGGERSELECT_ITR0 (0 << AD16C4T_SMCON_TSSEL_POSS) /*!< Internal Trigger 0*/ -#define MD_AD16C4T_TRIGGERSELECT_ITR1 (1 << AD16C4T_SMCON_TSSEL_POSS) /*!< Internal Trigger 1*/ -#define MD_AD16C4T_TRIGGERSELECT_ITR2 (2 << AD16C4T_SMCON_TSSEL_POSS) /*!< Internal Trigger 2*/ -#define MD_AD16C4T_TRIGGERSELECT_ITR3 (3 << AD16C4T_SMCON_TSSEL_POSS) /*!< Internal Trigger 3*/ -#define MD_AD16C4T_TRIGGERSELECT_TI1FED (4 << AD16C4T_SMCON_TSSEL_POSS) /*!< TI1 Edge Detector*/ -#define MD_AD16C4T_TRIGGERSELECT_TI1FP1 (5 << AD16C4T_SMCON_TSSEL_POSS) /*!< Filtered Timer Input 1*/ -#define MD_AD16C4T_TRIGGERSELECT_TI2FP2 (6 << AD16C4T_SMCON_TSSEL_POSS) /*!< Filtered Timer Input 2*/ -#define MD_AD16C4T_TRIGGERSELECT_ETRF (7 << AD16C4T_SMCON_TSSEL_POSS) /*!< External Trigger input*/ - -#define MD_AD16C4T_OCREFCLEAR_CMP (0 << AD16C4T_SMCON_CHCSEL_POS) /*!< OCREF_CLR is connected to the CMP_IN input*/ -#define MD_AD16C4T_OCREFCLEAR_ETRF (1 << AD16C4T_SMCON_CHCSEL_POS) /*!< OCREF_CLR is connected to ETRF*/ - -#define MD_AD16C4T_SLAVEMODE_DISABLE (0 << AD16C4T_SMCON_SMODS_POSS) /*!< Slave mode disabled*/ -#define MD_AD16C4T_SLAVEMODE_ENCODER1 (1 << AD16C4T_SMCON_SMODS_POSS) /*!< Encoder mode 1*/ -#define MD_AD16C4T_SLAVEMODE_ENCODER2 (2 << AD16C4T_SMCON_SMODS_POSS) /*!< Encoder mode 2*/ -#define MD_AD16C4T_SLAVEMODE_ENCODER3 (3 << AD16C4T_SMCON_SMODS_POSS) /*!< Encoder mode 3*/ -#define MD_AD16C4T_SLAVEMODE_RESET (4 << AD16C4T_SMCON_SMODS_POSS) /*!< Reset Mode*/ -#define MD_AD16C4T_SLAVEMODE_GATED (5 << AD16C4T_SMCON_SMODS_POSS) /*!< Gated Mode*/ -#define MD_AD16C4T_SLAVEMODE_TRIGGER (6 << AD16C4T_SMCON_SMODS_POSS) /*!< Trigger Mode*/ -#define MD_AD16C4T_SLAVEMODE_EXTERNALCLOCK (7 << AD16C4T_SMCON_SMODS_POSS) /*!< External Clock Mode 1*/ - -/* AD16C4T_IER IDR IVS RIF IFM ICR macros define*/ -#define MD_AD16C4T_INTERRUPTFALG_CC4OI (1 << AD16C4T_IER_CH4OVI_POS) /*!< Capture/Compare 4 overcapture interrupt*/ -#define MD_AD16C4T_INTERRUPTFALG_CC3OI (1 << AD16C4T_IER_CH3OVI_POS) /*!< Capture/Compare 3 overcapture interrupt*/ -#define MD_AD16C4T_INTERRUPTFALG_CC2OI (1 << AD16C4T_IER_CH2OVI_POS) /*!< Capture/Compare 2 overcapture interrupt*/ -#define MD_AD16C4T_INTERRUPTFALG_CC1OI (1 << AD16C4T_IER_CH1OVI_POS) /*!< Capture/Compare 1 overcapture interrupt*/ -#define MD_AD16C4T_INTERRUPTFALG_BI (1 << AD16C4T_IER_BRKI_POS) /*!< Break interrupt*/ -#define MD_AD16C4T_INTERRUPTFALG_TI (1 << AD16C4T_IER_TRGI_POS) /*!< Trigger interrupt*/ -#define MD_AD16C4T_INTERRUPTFALG_COMI (1 << AD16C4T_IER_COMI_POS) /*!< COM interrupt*/ -#define MD_AD16C4T_INTERRUPTFALG_CC4I (1 << AD16C4T_IER_CH4I_POS) /*!< Capture/Compare 4 interrupt*/ -#define MD_AD16C4T_INTERRUPTFALG_CC3I (1 << AD16C4T_IER_CH3I_POS) /*!< Capture/Compare 3 interrupt*/ -#define MD_AD16C4T_INTERRUPTFALG_CC2I (1 << AD16C4T_IER_CH2I_POS) /*!< Capture/Compare 2 interrupt*/ -#define MD_AD16C4T_INTERRUPTFALG_CC1I (1 << AD16C4T_IER_CH1I_POS) /*!< Capture/Compare 1 interrupt*/ -#define MD_AD16C4T_INTERRUPTFALG_UI (1 << AD16C4T_IER_UI_POS) /*!< Update interrupt*/ - -/* AD16C4T_SGE macros define*/ -#define MD_AD16C4T_EVENTGENERATION_BG (1 << AD16C4T_SGE_SGBRK_POS) /*!< Break generation*/ -#define MD_AD16C4T_EVENTGENERATION_TG (1 << AD16C4T_SGE_SGTRG_POS) /*!< Trigger generation*/ -#define MD_AD16C4T_EVENTGENERATION_COMG (1 << AD16C4T_SGE_SGCOM_POS) /*!< Capture/Compare control update generation*/ -#define MD_AD16C4T_EVENTGENERATION_CC4G (1 << AD16C4T_SGE_SGCH4_POS) /*!< Capture/Compare 4 generation*/ -#define MD_AD16C4T_EVENTGENERATION_CC3G (1 << AD16C4T_SGE_SGCH3_POS) /*!< Capture/Compare 3 generation*/ -#define MD_AD16C4T_EVENTGENERATION_CC2G (1 << AD16C4T_SGE_SGCH2_POS) /*!< Capture/Compare 2 generation*/ -#define MD_AD16C4T_EVENTGENERATION_CC1G (1 << AD16C4T_SGE_SGCH1_POS) /*!< Capture/Compare 1 generation*/ -#define MD_AD16C4T_EVENTGENERATION_UG (1 << AD16C4T_SGE_SGU_POS) /*!< Update generation*/ - -/* AD16C4T_CHMR1 CHMR2 output macros define*/ -#define MD_AD16C4T_OUTPUTMODE_DISABLE 0 /*!< Frozen*/ -#define MD_AD16C4T_OUTPUTMODE_HIGHONMSTCH 1 /*!< Set channel 1 to active level on match*/ -#define MD_AD16C4T_OUTPUTMODE_LOWONMSTCH 2 /*!< Set channel 1 to inactive level on match*/ -#define MD_AD16C4T_OUTPUTMODE_TOGGLE 3 /*!< Toggle*/ -#define MD_AD16C4T_OUTPUTMODE_FORCELOW 4 /*!< Force inactive level*/ -#define MD_AD16C4T_OUTPUTMODE_FORCEHIGH 5 /*!< Force active level*/ -#define MD_AD16C4T_OUTPUTMODE_PWMMODE1 6 /*!< PWM mode 1*/ -#define MD_AD16C4T_OUTPUTMODE_PWMMODE2 7 /*!< PWM mode 2*/ - -#define MD_AD16C4T_CHMODE_OUTPUT 0 /*!< CCx channel is configured as output*/ -#define MD_AD16C4T_CHMODE_INPUT_DIRECT 1 /*!< CCx channel is configured as input, ICx is mapped direct*/ -#define MD_AD16C4T_CHMODE_INPUT_INDIRECT 2 /*!< CCx channel is configured as input, ICx is mapped indirect*/ -#define MD_AD16C4T_CHMODE_INPUT_TRC 3 /*!< CCx channel is configured as input, ICx is mapped TRC*/ - -/* AD16C4T_CHMR1 CHMR2 input macros define*/ -#define MD_AD16C4T_INPUTFILTER_FDIV1 0 /*!< No filter*/ -#define MD_AD16C4T_INPUTFILTER_FDIV1N2 1 /*!< fSAMPLING = fCK_INT, N = 2*/ -#define MD_AD16C4T_INPUTFILTER_FDIV1N4 2 /*!< fSAMPLING = fCK_INT, N = 4*/ -#define MD_AD16C4T_INPUTFILTER_FDIV1N8 3 /*!< fSAMPLING = fCK_INT, N = 8*/ -#define MD_AD16C4T_INPUTFILTER_FDIV2N6 4 /*!< fSAMPLING = fDTS / 2, N = 6*/ -#define MD_AD16C4T_INPUTFILTER_FDIV2N8 5 /*!< fSAMPLING = fDTS / 2, N = 8*/ -#define MD_AD16C4T_INPUTFILTER_FDIV4N6 6 /*!< fSAMPLING = fDTS / 4, N = 6*/ -#define MD_AD16C4T_INPUTFILTER_FDIV4N8 7 /*!< fSAMPLING = fDTS / 4, N = 8*/ -#define MD_AD16C4T_INPUTFILTER_FDIV8N6 8 /*!< fSAMPLING = fDTS / 8, N = 6*/ -#define MD_AD16C4T_INPUTFILTER_FDIV8N8 9 /*!< fSAMPLING = fDTS / 8, N = 8*/ -#define MD_AD16C4T_INPUTFILTER_FDIV16N5 10 /*!< fSAMPLING = fDTS / 16, N = 5*/ -#define MD_AD16C4T_INPUTFILTER_FDIV16N6 11 /*!< fSAMPLING = fDTS / 16, N = 6*/ -#define MD_AD16C4T_INPUTFILTER_FDIV16N8 12 /*!< fSAMPLING = fDTS / 16, N = 8*/ -#define MD_AD16C4T_INPUTFILTER_FDIV32N5 13 /*!< fSAMPLING = fDTS / 32, N = 5*/ -#define MD_AD16C4T_INPUTFILTER_FDIV32N6 14 /*!< fSAMPLING = fDTS / 32, N = 6*/ -#define MD_AD16C4T_INPUTFILTER_FDIV32N8 15 /*!< fSAMPLING = fDTS / 32, N = 8*/ - -#define MD_AD16C4T_INPUTPRESCALE_DIV1 0 /*!< no prescaler*/ -#define MD_AD16C4T_INPUTPRESCALE_DIV2 1 /*!< capture is done once every 2 events*/ -#define MD_AD16C4T_INPUTPRESCALE_DIV4 2 /*!< capture is done once every 4 events*/ -#define MD_AD16C4T_INPUTPRESCALE_DIV8 3 /*!< capture is done once every 8 events*/ - -/* AD16C4T_CCEP input macros define*/ -#define MD_AD16C4T_OUTPUTPOLARITY_HIGH 0 /*!< active high*/ -#define MD_AD16C4T_OUTPUTPOLARITY_LOW 1 /*!< active low*/ - -/* AD16C4T_BDCFG input macros define*/ -#define MD_AD16C4T_BREAKPOLARITY_LOW (0 << AD16C4T_BDCFG_BRKP_POS) /*!< Break input BRK is active low*/ -#define MD_AD16C4T_BREAKPOLARITY_HIGH (1 << AD16C4T_BDCFG_BRKP_POS) /*!< Break input BRK is active high */ - -#define MD_AD16C4T_OFFSTATERUN_DISABLE (0 << AD16C4T_BDCFG_OFFSSR_POS) /*!< This bit is used when MOE=1, when inactive, OC/OCN outputs are disabled*/ -#define MD_AD16C4T_OFFSTATERUN_ENABLE (1 << AD16C4T_BDCFG_OFFSSR_POS) /*!< This bit is used when MOE=1, when inactive, OC/OCN outputs are enabled*/ - -#define MD_AD16C4T_OFFSTATEIDLE_DISABLE (0 << AD16C4T_BDCFG_OFFSSI_POS) /*!< This bit is used when MOE=0, when inactive, OC/OCN outputs are disabled*/ -#define MD_AD16C4T_OFFSTATEIDLE_ENABLE (1 << AD16C4T_BDCFG_OFFSSI_POS) /*!< This bit is used when MOE=0, when inactive, OC/OCN outputs are forced*/ - -#define MD_AD16C4T_LOCKLEVEL_0 (0 << AD16C4T_BDCFG_LOCKLVL_POSS) /*!< LOCK OFF*/ -#define MD_AD16C4T_LOCKLEVEL_1 (1 << AD16C4T_BDCFG_LOCKLVL_POSS) /*!< LOCK Level 1*/ -#define MD_AD16C4T_LOCKLEVEL_2 (2 << AD16C4T_BDCFG_LOCKLVL_POSS) /*!< LOCK Level 2*/ -#define MD_AD16C4T_LOCKLEVEL_3 (3 << AD16C4T_BDCFG_LOCKLVL_POSS) /*!< LOCK Level 3*/ - -/** - * @} MD_AD16C4T_Public_Constants - */ - -/* Public Macro ------------------------------------------------------------*/ -/** @defgroup MD_AD16C4T_Public_Macro Public Macro - * @brief AD16C4T module driver - * @{ - */ - -/** - * @brief Timer CON1 setup. - * @param timx AD16C4T instance - * @param value (DBGSEL | CMPSEL | CMPSELP | DFCKSEL | ARPEN | CMSEL | DIRSEL | SPMEN | UERSEL | DISUE | CNTEN) - * @retval None - */ - -__STATIC_INLINE void md_ad16c4t_set_con1(AD16C4T_TypeDef *timx, uint32_t value) -{ - WRITE_REG(timx->CON1, value); -} - -/** - * @brief GET Timer CON1 register value. - * @param timx AD16C4T instance - * @retval Timer CON1 register value. - */ - -__STATIC_INLINE uint32_t md_ad16c4t_get_con1(AD16C4T_TypeDef *timx) -{ - return (READ_REG(timx->CON1)); -} - -/** - * @brief Timer debug mode select. - * @param timx AD16C4T instance - * @param DebugSelect Debug mode output select - @arg @ref MD_AD16C4T_DEBUGSELECT_INPUT - @arg @ref MD_AD16C4T_DEBUGSELECT_OUTPUT - * @retval None - */ - -__STATIC_INLINE void md_ad16c4t_set_con1_dbgsel(AD16C4T_TypeDef *timx, uint32_t DebugSelect) -{ - MODIFY_REG(timx->CON1, AD16C4T_CON1_DBGSEL_MSK, DebugSelect); -} - -/** - * @brief Get timer debug mode select. - * @param timx AD16C4T instance - * @retval Timer debug mode select. - */ - -__STATIC_INLINE uint32_t md_ad16c4t_get_con1_dbgsel(AD16C4T_TypeDef *timx) -{ - return (READ_BIT(timx->CON1, AD16C4T_CON1_DBGSEL_MSK) >> AD16C4T_CON1_DBGSEL_POS); -} - -/** - * @brief Timer compare input selection. - * @param timx AD16C4T instance - * @param CompareSelection Compare input selection - @arg @ref MD_AD16C4T_COMPAREINPUT_DISABLE - @arg @ref MD_AD16C4T_COMPAREINPUT_0 - @arg @ref MD_AD16C4T_COMPAREINPUT_1 - @arg @ref MD_AD16C4T_COMPAREINPUT_2 - @arg @ref MD_AD16C4T_COMPAREINPUT_3 - * @retval None - */ - -__STATIC_INLINE void md_ad16c4t_set_con1_cmpsel(AD16C4T_TypeDef *timx, uint32_t CompareSelection) -{ - MODIFY_REG(timx->CON1, AD16C4T_CON1_CMPSEL_MSK, CompareSelection); -} - -/** - * @brief Get timer compare input selection. - * @param timx AD16C4T instance - * @retval Timer compare input selection. - */ - -__STATIC_INLINE uint32_t md_ad16c4t_get_con1_cmpsel(AD16C4T_TypeDef *timx) -{ - return (READ_BIT(timx->CON1, AD16C4T_CON1_CMPSEL_MSK) >> AD16C4T_CON1_CMPSEL_POSS); -} - -/** - * @brief Timer compare input selection polarity setup. - * @param timx AD16C4T instance - * @param ComparePolarity compare input selection polarity - @arg @ref MD_AD16C4T_COMPAREPOLARITY_LOW - @arg @ref MD_AD16C4T_COMPAREPOLARITY_HIGH - * @retval None - */ - -__STATIC_INLINE void md_ad16c4t_set_con1_cmpselp(AD16C4T_TypeDef *timx, uint32_t ComparePolarity) -{ - MODIFY_REG(timx->CON1, AD16C4T_CON1_CMPSELP_MSK, ComparePolarity); -} - -/** - * @brief Get timer compare input selection polarity. - * @param timx AD16C4T instance - * @retval Timer compare input selection polarity. - */ - -__STATIC_INLINE uint32_t md_ad16c4t_get_con1_cmpselp(AD16C4T_TypeDef *timx) -{ - return (READ_BIT(timx->CON1, AD16C4T_CON1_CMPSELP_MSK) >> AD16C4T_CON1_CMPSELP_POS); -} - -/** - * @brief Timer clock division setup. - * @param timx AD16C4T instance - * @param ClockDivision Clock division - @arg @ref MD_AD16C4T_CLOCKDIVSION_DIV1 - @arg @ref MD_AD16C4T_CLOCKDIVSION_DIV2 - @arg @ref MD_AD16C4T_CLOCKDIVSION_DIV4 - * @retval None - */ - -__STATIC_INLINE void md_ad16c4t_set_con1_dfcksel(AD16C4T_TypeDef *timx, uint32_t ClockDivision) -{ - MODIFY_REG(timx->CON1, AD16C4T_CON1_DFCKSEL_MSK, ClockDivision); -} - -/** - * @brief Get timer Clock division. - * @param timx AD16C4T instance - * @retval Timer Clock division. - */ - -__STATIC_INLINE uint32_t md_ad16c4t_get_con1_dfcksel(AD16C4T_TypeDef *timx) -{ - return (READ_BIT(timx->CON1, AD16C4T_CON1_DFCKSEL_MSK) >> AD16C4T_CON1_DFCKSEL_POSS); -} - -/** - * @brief Timer auto-reload preload enable. - * @param timx AD16C4T instance - * @retval None - */ - -__STATIC_INLINE void md_ad16c4t_enable_con1_arpen(AD16C4T_TypeDef *timx) -{ - SET_BIT(timx->CON1, AD16C4T_CON1_ARPEN_MSK); -} - -/** - * @brief Timer auto-reload preload disable. - * @param timx AD16C4T instance - * @retval None - */ - -__STATIC_INLINE void md_ad16c4t_disable_con1_arpen(AD16C4T_TypeDef *timx) -{ - CLEAR_BIT(timx->CON1, AD16C4T_CON1_ARPEN_MSK); -} - -/** - * @brief Indicates whether the timer auto-reload preload is enabled. - * @param timx AD16C4T instance - * @retval State of bit (1 or 0). - */ - -__STATIC_INLINE uint32_t md_ad16c4t_is_enabled_con1_arpen(AD16C4T_TypeDef *timx) -{ - return (READ_BIT(timx->CON1, AD16C4T_CON1_ARPEN_MSK) == (AD16C4T_CON1_ARPEN_MSK)); -} - -/** - * @brief Timer center-aligned mode selection setup. - * @param timx AD16C4T instance - * @param CenterAlignedMode center-aligned mode selection - @arg @ref MD_AD16C4T_CENTERALIGNED_DISABLE - @arg @ref MD_AD16C4T_CENTERALIGNED_DOWN - @arg @ref MD_AD16C4T_CENTERALIGNED_UP - @arg @ref MD_AD16C4T_CENTERALIGNED_BOTH - * @retval None - */ - -__STATIC_INLINE void md_ad16c4t_set_con1_cmsel(AD16C4T_TypeDef *timx, uint32_t CenterAlignedMode) -{ - MODIFY_REG(timx->CON1, AD16C4T_CON1_CMSEL_MSK, CenterAlignedMode); -} - -/** - * @brief Get timer center-aligned mode selection. - * @param timx AD16C4T instance - * @retval Timer center-aligned mode selection. - */ - -__STATIC_INLINE uint32_t md_ad16c4t_get_con1_cmsel(AD16C4T_TypeDef *timx) -{ - return (READ_BIT(timx->CON1, AD16C4T_CON1_CMSEL_MSK) >> AD16C4T_CON1_CMSEL_POSS); -} - -/** - * @brief Timer counting direction setup. - * @param timx AD16C4T instance - * @param direction Counting direction - @arg @ref MD_AD16C4T_UPCOUNTER - @arg @ref MD_AD16C4T_DOWNCOUNTER - * @retval None - */ - -__STATIC_INLINE void md_ad16c4t_set_con1_dirsel(AD16C4T_TypeDef *timx, uint32_t direction) -{ - MODIFY_REG(timx->CON1, AD16C4T_CON1_DIRSEL_MSK, direction); -} - -/** - * @brief Get timer counting direction. - * @param timx AD16C4T instance - * @retval Timer counting direction. - */ - -__STATIC_INLINE uint32_t md_ad16c4t_get_con1_dirsel(AD16C4T_TypeDef *timx) -{ - return (READ_BIT(timx->CON1, AD16C4T_CON1_DIRSEL_MSK) >> AD16C4T_CON1_DIRSEL_POS); -} - -/** - * @brief Timer one pulse mode enable. - * @param timx AD16C4T instance - * @retval None - */ - -__STATIC_INLINE void md_ad16c4t_enable_con1_spmen(AD16C4T_TypeDef *timx) -{ - SET_BIT(timx->CON1, AD16C4T_CON1_SPMEN_MSK); -} - -/** - * @brief Timer one pulse mode disable. - * @param timx AD16C4T instance - * @retval None. - */ - -__STATIC_INLINE void md_ad16c4t_disable_con1_spmen(AD16C4T_TypeDef *timx) -{ - CLEAR_BIT(timx->CON1, AD16C4T_CON1_SPMEN_MSK); -} - -/** - * @brief Indicates whether the timer one pulse mode is enabled. - * @param timx AD16C4T instance - * @retval State of bit (1 or 0). - */ - -__STATIC_INLINE uint32_t md_ad16c4t_is_enabled_con1_spmen(AD16C4T_TypeDef *timx) -{ - return (READ_BIT(timx->CON1, AD16C4T_CON1_SPMEN_MSK) == (AD16C4T_CON1_SPMEN_MSK)); -} - -/** - * @brief Timer update request source setup. - * @param timx AD16C4T instance - * @param UpdateSource Update request source select - @arg @ref MD_AD16C4T_UPDATESOURCE_NORMAL - @arg @ref MD_AD16C4T_UPDATESOURCE_COUNTER - * @retval None - */ - -__STATIC_INLINE void md_ad16c4t_set_con1_uersel(AD16C4T_TypeDef *timx, uint32_t UpdateSource) -{ - MODIFY_REG(timx->CON1, AD16C4T_CON1_UERSEL_MSK, UpdateSource); -} - -/** - * @brief Get timer update request source. - * @param timx AD16C4T instance - * @retval Timer update request source. - */ - -__STATIC_INLINE uint32_t md_ad16c4t_get_con1_uersel(AD16C4T_TypeDef *timx) -{ - return (READ_BIT(timx->CON1, AD16C4T_CON1_UERSEL_MSK) >> AD16C4T_CON1_UERSEL_POS); -} - -/** - * @brief Timer update event enable. - * @param timx AD16C4T instance - * @retval None - */ - -__STATIC_INLINE void md_ad16c4t_enable_con1_disue(AD16C4T_TypeDef *timx) -{ - CLEAR_BIT(timx->CON1, AD16C4T_CON1_DISUE_MSK); -} - -/** - * @brief Timer update event disable. - * @param timx AD16C4T instance - * @retval None - */ - -__STATIC_INLINE void md_ad16c4t_disble_con1_disue(AD16C4T_TypeDef *timx) -{ - SET_BIT(timx->CON1, AD16C4T_CON1_DISUE_MSK); -} - -/** - * @brief Indicates whether the timer update event is enabled. - * @param timx AD16C4T instance - * @retval State of bit (1 or 0). - */ - -__STATIC_INLINE uint32_t md_ad16c4t_is_enabled_con1_disue(AD16C4T_TypeDef *timx) -{ - return (READ_BIT(timx->CON1, AD16C4T_CON1_DISUE_MSK) == (AD16C4T_CON1_DISUE_MSK)); -} - -/** - * @brief Timer counter enable. - * @param timx AD16C4T instance - * @retval None - */ - -__STATIC_INLINE void md_ad16c4t_enable_con1_cnten(AD16C4T_TypeDef *timx) -{ - SET_BIT(timx->CON1, AD16C4T_CON1_CNTEN_MSK); -} - - -/** - * @brief Timer counter disable. - * @param timx AD16C4T instance - * @retval None - */ - -__STATIC_INLINE void md_ad16c4t_disable_con1_cnten(AD16C4T_TypeDef *timx) -{ - CLEAR_BIT(timx->CON1, AD16C4T_CON1_CNTEN_MSK); -} - -/** - * @brief Indicates whether the timer counter is enabled. - * @param timx AD16C4T instance - * @retval State of bit (1 or 0). - */ - -__STATIC_INLINE uint32_t md_ad16c4t_is_enabled_con1_cnten(AD16C4T_TypeDef *timx) -{ - return (READ_BIT(timx->CON1, AD16C4T_CON1_CNTEN_MSK) == (AD16C4T_CON1_CNTEN_MSK)); -} - -/** - * @brief Timer CON2 setup. - * @param timx AD16C4T instance - * @param value (OISS4 | OISS3N | OISS3 | OISS2N | OISS2 | OISS1N | OISS1 | I1SEL | MMSEL | CCDMASEL | CCUSEL | CCPCEN) - * @retval None - */ - -__STATIC_INLINE void md_ad16c4t_set_con2(AD16C4T_TypeDef *timx, uint32_t value) -{ - WRITE_REG(timx->CON2, value); -} - -/** - * @brief GET Timer CON2 register value. - * @param timx AD16C4T instance - * @retval Timer CON2 register value. - */ - -__STATIC_INLINE uint32_t md_ad16c4t_get_con2(AD16C4T_TypeDef *timx) -{ - return (READ_REG(timx->CON2)); -} - -/** - * @brief Timer output idle state 4 setup. - * @param timx AD16C4T instance - * @param IdleOutput Output idle state - @arg @ref MD_AD16C4T_IDLEOUTPUT_LOW - @arg @ref MD_AD16C4T_IDLEOUTPUT_HIGH - * @retval None - */ - -__STATIC_INLINE void md_ad16c4t_set_con2_oiss4(AD16C4T_TypeDef *timx, uint32_t IdleOutput) -{ - MODIFY_REG(timx->CON2, AD16C4T_CON2_OISS4_MSK, (IdleOutput << AD16C4T_CON2_OISS4_POS)); -} - -/** - * @brief Get timer output idle state 4. - * @param timx AD16C4T instance - * @retval Timer output idle state 4. - */ - -__STATIC_INLINE uint32_t md_ad16c4t_get_con2_oiss4(AD16C4T_TypeDef *timx) -{ - return (READ_BIT(timx->CON2, AD16C4T_CON2_OISS4_MSK) >> AD16C4T_CON2_OISS4_POS); -} - -/** - * @brief Timer output idle state 3N setup. - * @param timx AD16C4T instance - * @param IdleOutput Output idle state - @arg @ref MD_AD16C4T_IDLEOUTPUT_LOW - @arg @ref MD_AD16C4T_IDLEOUTPUT_HIGH - * @retval None - */ - -__STATIC_INLINE void md_ad16c4t_set_con2_oiss3n(AD16C4T_TypeDef *timx, uint32_t IdleOutput) -{ - MODIFY_REG(timx->CON2, AD16C4T_CON2_OISS3N_MSK, (IdleOutput << AD16C4T_CON2_OISS3N_POS)); -} - -/** - * @brief Get timer output idle state 3N. - * @param timx AD16C4T instance - * @retval Timer output idle state 3N. - */ - -__STATIC_INLINE uint32_t md_ad16c4t_get_con2_oiss3n(AD16C4T_TypeDef *timx) -{ - return (READ_BIT(timx->CON2, AD16C4T_CON2_OISS3N_MSK) >> AD16C4T_CON2_OISS3N_POS); -} - -/** - * @brief Timer output idle state 3 setup. - * @param timx AD16C4T instance - * @param IdleOutput Output idle state - @arg @ref MD_AD16C4T_IDLEOUTPUT_LOW - @arg @ref MD_AD16C4T_IDLEOUTPUT_HIGH - * @retval None - */ - -__STATIC_INLINE void md_ad16c4t_set_con2_oiss3(AD16C4T_TypeDef *timx, uint32_t IdleOutput) -{ - MODIFY_REG(timx->CON2, AD16C4T_CON2_OISS3_MSK, (IdleOutput << AD16C4T_CON2_OISS3_POS)); -} - -/** - * @brief Get timer output idle state 3. - * @param timx AD16C4T instance - * @retval Timer output idle state 3. - */ - -__STATIC_INLINE uint32_t md_ad16c4t_get_con2_oiss3(AD16C4T_TypeDef *timx) -{ - return (READ_BIT(timx->CON2, AD16C4T_CON2_OISS3_MSK) >> AD16C4T_CON2_OISS3_POS); -} - -/** - * @brief Timer output idle state 2N setup. - * @param timx AD16C4T instance - * @param IdleOutput Output idle state - @arg @ref MD_AD16C4T_IDLEOUTPUT_LOW - @arg @ref MD_AD16C4T_IDLEOUTPUT_HIGH - * @retval None - */ - -__STATIC_INLINE void md_ad16c4t_set_con2_oiss2n(AD16C4T_TypeDef *timx, uint32_t IdleOutput) -{ - MODIFY_REG(timx->CON2, AD16C4T_CON2_OISS2N_MSK, (IdleOutput << AD16C4T_CON2_OISS2N_POS)); -} - -/** - * @brief Get timer output idle state 2N. - * @param timx AD16C4T instance - * @retval Timer output idle state 2N. - */ - -__STATIC_INLINE uint32_t md_ad16c4t_get_con2_oiss2n(AD16C4T_TypeDef *timx) -{ - return (READ_BIT(timx->CON2, AD16C4T_CON2_OISS2N_MSK) >> AD16C4T_CON2_OISS2N_POS); -} - -/** - * @brief Timer output idle state 2 setup. - * @param timx AD16C4T instance - * @param IdleOutput Output idle state - @arg @ref MD_AD16C4T_IDLEOUTPUT_LOW - @arg @ref MD_AD16C4T_IDLEOUTPUT_HIGH - * @retval None - */ - -__STATIC_INLINE void md_ad16c4t_set_con2_oiss2(AD16C4T_TypeDef *timx, uint32_t IdleOutput) -{ - MODIFY_REG(timx->CON2, AD16C4T_CON2_OISS2_MSK, (IdleOutput << AD16C4T_CON2_OISS2_POS)); -} - -/** - * @brief Get timer output idle state 2. - * @param timx AD16C4T instance - * @retval Timer output idle state 2. - */ - -__STATIC_INLINE uint32_t md_ad16c4t_get_con2_oiss2(AD16C4T_TypeDef *timx) -{ - return (READ_BIT(timx->CON2, AD16C4T_CON2_OISS2_MSK) >> AD16C4T_CON2_OISS2_POS); -} - -/** - * @brief Timer output idle state 1N setup. - * @param timx AD16C4T instance - * @param IdleOutput Output idle state - @arg @ref MD_AD16C4T_IDLEOUTPUT_LOW - @arg @ref MD_AD16C4T_IDLEOUTPUT_HIGH - * @retval None - */ - -__STATIC_INLINE void md_ad16c4t_set_con2_oiss1n(AD16C4T_TypeDef *timx, uint32_t IdleOutput) -{ - MODIFY_REG(timx->CON2, AD16C4T_CON2_OISS1N_MSK, (IdleOutput << AD16C4T_CON2_OISS1N_POS)); -} - -/** - * @brief Get timer output idle state 1N. - * @param timx AD16C4T instance - * @retval Timer output idle state 1N. - */ - -__STATIC_INLINE uint32_t md_ad16c4t_get_con2_oiss1n(AD16C4T_TypeDef *timx) -{ - return (READ_BIT(timx->CON2, AD16C4T_CON2_OISS1N_MSK) >> AD16C4T_CON2_OISS1N_POS); -} - -/** - * @brief Timer output idle state 1 setup. - * @param timx AD16C4T instance - * @param IdleOutput Output idle state - @arg @ref MD_AD16C4T_IDLEOUTPUT_LOW - @arg @ref MD_AD16C4T_IDLEOUTPUT_HIGH - * @retval None - */ - -__STATIC_INLINE void md_ad16c4t_set_con2_oiss1(AD16C4T_TypeDef *timx, uint32_t IdleOutput) -{ - MODIFY_REG(timx->CON2, AD16C4T_CON2_OISS1_MSK, (IdleOutput << AD16C4T_CON2_OISS1_POS)); -} - -/** - * @brief Get timer output idle state 1. - * @param timx AD16C4T instance - * @retval Timer output idle state 1. - */ - -__STATIC_INLINE uint32_t md_ad16c4t_get_con2_oiss1(AD16C4T_TypeDef *timx) -{ - return (READ_BIT(timx->CON2, AD16C4T_CON2_OISS1_MSK) >> AD16C4T_CON2_OISS1_POS); -} - -/** - * @brief Timer TI1 selection setup. - * @param timx AD16C4T instance - * @param TI1Input TI1 input select - @arg @ref MD_AD16C4T_TI1INPUT_CH1 - @arg @ref MD_AD16C4T_TI1INPUT_XOR - * @retval None - */ - -__STATIC_INLINE void md_ad16c4t_set_con2_i1sel(AD16C4T_TypeDef *timx, uint32_t TI1Input) -{ - MODIFY_REG(timx->CON2, AD16C4T_CON2_I1SEL_MSK, TI1Input); -} - -/** - * @brief Get timer TI1 selection. - * @param timx AD16C4T instance - * @retval Timer TI1 selection. - */ - -__STATIC_INLINE uint32_t md_ad16c4t_get_con2_i1sel(AD16C4T_TypeDef *timx) -{ - return (READ_BIT(timx->CON2, AD16C4T_CON2_I1SEL_MSK) >> AD16C4T_CON2_I1SEL_POS); -} - -/** - * @brief Timer master mode selection setup. - * @param timx AD16C4T instance - * @param MasterMode Master mode selection - @arg @ref MD_AD16C4T_MASTERMODE_RESET - @arg @ref MD_AD16C4T_MASTERMODE_ENABLE - @arg @ref MD_AD16C4T_MASTERMODE_UPDATE - @arg @ref MD_AD16C4T_MASTERMODE_COMPAREPULSE - @arg @ref MD_AD16C4T_MASTERMODE_COMPARE1 - @arg @ref MD_AD16C4T_MASTERMODE_COMPARE2 - @arg @ref MD_AD16C4T_MASTERMODE_COMPARE3 - @arg @ref MD_AD16C4T_MASTERMODE_COMPARE4 - * @retval None - */ - -__STATIC_INLINE void md_ad16c4t_set_con2_mmsel(AD16C4T_TypeDef *timx, uint32_t MasterMode) -{ - MODIFY_REG(timx->CON2, AD16C4T_CON2_MMSEL_MSK, MasterMode); -} - -/** - * @brief Get timer master mode selection. - * @param timx AD16C4T instance - * @retval Timer master mode selection. - */ - -__STATIC_INLINE uint32_t md_ad16c4t_get_con2_mmsel(AD16C4T_TypeDef *timx) -{ - return (READ_BIT(timx->CON2, AD16C4T_CON2_MMSEL_MSK) >> AD16C4T_CON2_MMSEL_POSS); -} - -/** - * @brief Timer capture/compare DMA selection setup. - * @param timx AD16C4T instance - * @param DMASelection Capture/compare DMA selection - @arg @ref MD_AD16C4T_DMASELECTION_COMPARE - @arg @ref MD_AD16C4T_DMASELECTION_UPDATE - * @retval None - */ - -__STATIC_INLINE void md_ad16c4t_set_con2_ccdmasel(AD16C4T_TypeDef *timx, uint32_t DMASelection) -{ - MODIFY_REG(timx->CON2, AD16C4T_CON2_CCDMASEL_MSK, DMASelection); -} - -/** - * @brief Get timer capture/compare DMA selection. - * @param timx AD16C4T instance - * @retval Timer capture/compare DMA selection. - */ - -__STATIC_INLINE uint32_t md_ad16c4t_get_con2_ccdmasel(AD16C4T_TypeDef *timx) -{ - return (READ_BIT(timx->CON2, AD16C4T_CON2_CCDMASEL_MSK) >> AD16C4T_CON2_CCDMASEL_POS); -} - -/** - * @brief Timer capture/compare control update selection setup. - * @param timx AD16C4T instance - * @param UpdateSelection Capture/compare control update selection - @arg @ref MD_AD16C4T_UPDATESELECTION_COMG - @arg @ref MD_AD16C4T_UPDATESELECTION_BOTH - * @retval None - */ - -__STATIC_INLINE void md_ad16c4t_set_con2_ccusel(AD16C4T_TypeDef *timx, uint32_t UpdateSelection) -{ - MODIFY_REG(timx->CON2, AD16C4T_CON2_CCUSEL_MSK, UpdateSelection); -} - -/** - * @brief Get timer capture/compare control update selection. - * @param timx AD16C4T instance - * @retval Timer capture/compare control update selection. - */ - -__STATIC_INLINE uint32_t md_ad16c4t_get_con2_ccusel(AD16C4T_TypeDef *timx) -{ - return (READ_BIT(timx->CON2, AD16C4T_CON2_CCUSEL_MSK) >> AD16C4T_CON2_CCUSEL_POS); -} - -/** - * @brief Timer capture/compare preloaded control enable. - * @param timx AD16C4T instance - * @retval None - */ - -__STATIC_INLINE void md_ad16c4t_enable_con2_ccpcen(AD16C4T_TypeDef *timx) -{ - SET_BIT(timx->CON2, AD16C4T_CON2_CCPCEN_MSK); -} - -/** - * @brief Timer capture/compare preloaded control disable. - * @param timx AD16C4T instance - * @retval None. - */ - -__STATIC_INLINE void md_ad16c4t_disable_con2_ccpcen(AD16C4T_TypeDef *timx) -{ - CLEAR_BIT(timx->CON2, AD16C4T_CON2_CCPCEN_MSK); -} - -/** - * @brief Indicates whether the timer capture/compare preloaded control is enabled. - * @param timx AD16C4T instance - * @retval State of bit (1 or 0). - */ - -__STATIC_INLINE uint32_t md_ad16c4t_is_enabled_con2_ccpcen(AD16C4T_TypeDef *timx) -{ - return (READ_BIT(timx->CON2, AD16C4T_CON2_CCPCEN_MSK) == (AD16C4T_CON2_CCPCEN_MSK)); -} - -/** - * @brief Timer SMCON setup. - * @param timx AD16C4T instance - * @param value (ETPOL | ECM2EN | ETFLT | MSCFG | TSSEL | CHCSEL | SMODS) - * @retval None - */ - -__STATIC_INLINE void md_ad16c4t_set_smcon(AD16C4T_TypeDef *timx, uint32_t value) -{ - WRITE_REG(timx->SMCON, value); -} - -/** - * @brief GET Timer SMCON register value. - * @param timx AD16C4T instance - * @retval Timer SMCON register value. - */ - -__STATIC_INLINE uint32_t md_ad16c4t_get_smcon(AD16C4T_TypeDef *timx) -{ - return (READ_REG(timx->SMCON)); -} - -/** - * @brief Timer external trigger polarity setup. - * @param timx AD16C4T instance - * @param ETRPolarity External trigger polarity - @arg @ref MD_AD16C4T_ETRPOLARITY_NONINVERTED - @arg @ref MD_AD16C4T_ETRPOLARITY_INVERTED - * @retval None - */ - -__STATIC_INLINE void md_ad16c4t_set_smcon_etpol(AD16C4T_TypeDef *timx, uint32_t ETRPolarity) -{ - MODIFY_REG(timx->SMCON, AD16C4T_SMCON_ETPOL_MSK, ETRPolarity); -} - -/** - * @brief Get timer external trigger polarity. - * @param timx AD16C4T instance - * @retval Timer external trigger polarity. - */ - -__STATIC_INLINE uint32_t md_ad16c4t_get_smcon_etpol(AD16C4T_TypeDef *timx) -{ - return (READ_BIT(timx->SMCON, AD16C4T_SMCON_ETPOL_MSK) >> AD16C4T_SMCON_ETPOL_POS); -} - -/** - * @brief Timer external clock enable. - * @param timx AD16C4T instance - * @retval None - */ - -__STATIC_INLINE void md_ad16c4t_enable_smcon_ecm2en(AD16C4T_TypeDef *timx) -{ - SET_BIT(timx->SMCON, AD16C4T_SMCON_ECM2EN_MSK); -} - - -/** - * @brief Timer external clock disable. - * @param timx AD16C4T instance - * @retval None - */ - -__STATIC_INLINE void md_ad16c4t_disable_smcon_ecm2en(AD16C4T_TypeDef *timx) -{ - CLEAR_BIT(timx->SMCON, AD16C4T_SMCON_ECM2EN_MSK); -} - -/** - * @brief Indicates whether the timer external clock is enabled. - * @param timx AD16C4T instance - * @retval State of bit (1 or 0). - */ - -__STATIC_INLINE uint32_t md_ad16c4t_is_enabled_smcon_ecm2en(AD16C4T_TypeDef *timx) -{ - return (READ_BIT(timx->SMCON, AD16C4T_SMCON_ECM2EN_MSK) == (AD16C4T_SMCON_ECM2EN_MSK)); -} - -/** - * @brief Timer external trigger filter setup. - * @param timx AD16C4T instance - * @param ETRFilter External trigger filter - @arg @ref MD_AD16C4T_ETRFILTER_FDIV1 - @arg @ref MD_AD16C4T_ETRFILTER_FDIV1N2 - @arg @ref MD_AD16C4T_ETRFILTER_FDIV1N4 - @arg @ref MD_AD16C4T_ETRFILTER_FDIV1N8 - @arg @ref MD_AD16C4T_ETRFILTER_FDIV2N6 - @arg @ref MD_AD16C4T_ETRFILTER_FDIV2N8 - @arg @ref MD_AD16C4T_ETRFILTER_FDIV4N6 - @arg @ref MD_AD16C4T_ETRFILTER_FDIV4N8 - @arg @ref MD_AD16C4T_ETRFILTER_FDIV8N6 - @arg @ref MD_AD16C4T_ETRFILTER_FDIV8N8 - @arg @ref MD_AD16C4T_ETRFILTER_FDIV16N5 - @arg @ref MD_AD16C4T_ETRFILTER_FDIV16N6 - @arg @ref MD_AD16C4T_ETRFILTER_FDIV16N8 - @arg @ref MD_AD16C4T_ETRFILTER_FDIV32N5 - @arg @ref MD_AD16C4T_ETRFILTER_FDIV32N6 - @arg @ref MD_AD16C4T_ETRFILTER_FDIV32N8 - * @retval None - */ - -__STATIC_INLINE void md_ad16c4t_set_smcon_etflt(AD16C4T_TypeDef *timx, uint32_t ETRFilter) -{ - MODIFY_REG(timx->SMCON, AD16C4T_SMCON_ETFLT_MSK, ETRFilter); -} - -/** - * @brief Get timer external trigger filter. - * @param timx AD16C4T instance - * @retval Timer external trigger filter. - */ - -__STATIC_INLINE uint32_t md_ad16c4t_get_smcon_etflt(AD16C4T_TypeDef *timx) -{ - return (READ_BIT(timx->SMCON, AD16C4T_SMCON_ETFLT_MSK) >> AD16C4T_SMCON_ETFLT_POSS); -} - -/** - * @brief Timer master/slave mode setup. - * @param timx AD16C4T instance - * @param MSMode master/slave mode - @arg @ref MD_AD16C4T_MASTERSLAVE_NODELAY - @arg @ref MD_AD16C4T_MASTERSLAVE_DELAY - * @retval None - */ - -__STATIC_INLINE void md_ad16c4t_set_smcon_mscfg(AD16C4T_TypeDef *timx, uint32_t MSMode) -{ - MODIFY_REG(timx->SMCON, AD16C4T_SMCON_MSCFG_MSK, MSMode); -} - -/** - * @brief Get timer master/slave mode. - * @param timx AD16C4T instance - * @retval Timer master/slave mode. - */ - -__STATIC_INLINE uint32_t md_ad16c4t_get_smcon_mscfg(AD16C4T_TypeDef *timx) -{ - return (READ_BIT(timx->SMCON, AD16C4T_SMCON_MSCFG_MSK) >> AD16C4T_SMCON_MSCFG_POS); -} - -/** - * @brief Timer trigger selection setup. - * @param timx AD16C4T instance - * @param TriggerSelect Trigger selection - @arg @ref MD_AD16C4T_TRIGGERSELECT_ITR0 - @arg @ref MD_AD16C4T_TRIGGERSELECT_ITR1 - @arg @ref MD_AD16C4T_TRIGGERSELECT_ITR2 - @arg @ref MD_AD16C4T_TRIGGERSELECT_ITR3 - @arg @ref MD_AD16C4T_TRIGGERSELECT_TI1FED - @arg @ref MD_AD16C4T_TRIGGERSELECT_TI1FP1 - @arg @ref MD_AD16C4T_TRIGGERSELECT_TI2FP2 - @arg @ref MD_AD16C4T_TRIGGERSELECT_ETRF - * @retval None - */ - -__STATIC_INLINE void md_ad16c4t_set_smcon_tssel(AD16C4T_TypeDef *timx, uint32_t TriggerSelect) -{ - MODIFY_REG(timx->SMCON, AD16C4T_SMCON_TSSEL_MSK, TriggerSelect); -} - -/** - * @brief Get timer trigger selection. - * @param timx AD16C4T instance - * @retval Timer trigger selection. - */ - -__STATIC_INLINE uint32_t md_ad16c4t_get_smcon_tssel(AD16C4T_TypeDef *timx) -{ - return (READ_BIT(timx->SMCON, AD16C4T_SMCON_TSSEL_MSK) >> AD16C4T_SMCON_TSSEL_POSS); -} - -/** - * @brief Timer OCREF clear selection setup. - * @param timx AD16C4T instance - * @param OCREFSelect OCREF clear selection - @arg @ref MD_AD16C4T_OCREFCLEAR_CMP - @arg @ref MD_AD16C4T_OCREFCLEAR_ETRF - * @retval None - */ - -__STATIC_INLINE void md_ad16c4t_set_smcon_chcsel(AD16C4T_TypeDef *timx, uint32_t OCREFSelect) -{ - MODIFY_REG(timx->SMCON, AD16C4T_SMCON_CHCSEL_MSK, OCREFSelect); -} - -/** - * @brief Get timer OCREF clear selection. - * @param timx AD16C4T instance - * @retval Timer OCREF clear selection. - */ - -__STATIC_INLINE uint32_t md_ad16c4t_get_smcon_chcsel(AD16C4T_TypeDef *timx) -{ - return (READ_BIT(timx->SMCON, AD16C4T_SMCON_CHCSEL_MSK) >> AD16C4T_SMCON_CHCSEL_POS); -} - -/** - * @brief Timer slave mode selection setup. - * @param timx AD16C4T instance - * @param SlaveMode Slave mode selection - @arg @ref MD_AD16C4T_SLAVEMODE_DISABLE - @arg @ref MD_AD16C4T_SLAVEMODE_ENCODER1 - @arg @ref MD_AD16C4T_SLAVEMODE_ENCODER2 - @arg @ref MD_AD16C4T_SLAVEMODE_ENCODER3 - @arg @ref MD_AD16C4T_SLAVEMODE_RESET - @arg @ref MD_AD16C4T_SLAVEMODE_GATED - @arg @ref MD_AD16C4T_SLAVEMODE_TRIGGER - @arg @ref MD_AD16C4T_SLAVEMODE_EXTERNALCLOCK - * @retval None - */ - -__STATIC_INLINE void md_ad16c4t_set_smcon_smods(AD16C4T_TypeDef *timx, uint32_t SlaveMode) -{ - MODIFY_REG(timx->SMCON, AD16C4T_SMCON_SMODS_MSK, SlaveMode); -} - -/** - * @brief Get timer slave mode selection. - * @param timx AD16C4T instance - * @retval Timer slave mode selection. - */ - -__STATIC_INLINE uint32_t md_ad16c4t_get_smcon_smods(AD16C4T_TypeDef *timx) -{ - return (READ_BIT(timx->SMCON, AD16C4T_SMCON_SMODS_MSK) >> AD16C4T_SMCON_SMODS_POSS); -} - -/** - * @brief Timer IER setup. - * @param timx AD16C4T instance - * @param value (CH4OVI | CH3OVI | CH2OVI | CH1OVI | BRKI | TRGI | COMI | CH4I | CH3I | CH2I | CH1I | UI) - * @retval None - */ - -__STATIC_INLINE void md_ad16c4t_set_ier(AD16C4T_TypeDef *timx, uint32_t value) -{ - WRITE_REG(timx->IER, value); -} - -/** - * @brief Timer cpture/compare 4 overcapture interrupt enable. - * @param timx AD16C4T instance - * @retval None - */ - -__STATIC_INLINE void md_ad16c4t_enable_ier_ch4ovi(AD16C4T_TypeDef *timx) -{ - SET_BIT(timx->IER, AD16C4T_IER_CH4OVI_MSK); -} - -/** - * @brief Timer cpture/compare 3 overcapture interrupt enable. - * @param timx AD16C4T instance - * @retval None - */ - -__STATIC_INLINE void md_ad16c4t_enable_ier_ch3ovi(AD16C4T_TypeDef *timx) -{ - SET_BIT(timx->IER, AD16C4T_IER_CH3OVI_MSK); -} - -/** - * @brief Timer cpture/compare 2 overcapture interrupt enable. - * @param timx AD16C4T instance - * @retval None - */ - -__STATIC_INLINE void md_ad16c4t_enable_ier_ch2ovi(AD16C4T_TypeDef *timx) -{ - SET_BIT(timx->IER, AD16C4T_IER_CH2OVI_MSK); -} - -/** - * @brief Timer cpture/compare 1 overcapture interrupt enable. - * @param timx AD16C4T instance - * @retval None - */ - -__STATIC_INLINE void md_ad16c4t_enable_ier_ch1ovi(AD16C4T_TypeDef *timx) -{ - SET_BIT(timx->IER, AD16C4T_IER_CH1OVI_MSK); -} - -/** - * @brief Timer break interrupt enable. - * @param timx AD16C4T instance - * @retval None - */ - -__STATIC_INLINE void md_ad16c4t_enable_ier_brki(AD16C4T_TypeDef *timx) -{ - SET_BIT(timx->IER, AD16C4T_IER_BRKI_MSK); -} - -/** - * @brief Timer trigger interrupt enable. - * @param timx AD16C4T instance - * @retval None - */ - -__STATIC_INLINE void md_ad16c4t_enable_ier_trgi(AD16C4T_TypeDef *timx) -{ - SET_BIT(timx->IER, AD16C4T_IER_TRGI_MSK); -} - -/** - * @brief Timer COM interrupt enable. - * @param timx AD16C4T instance - * @retval None - */ - -__STATIC_INLINE void md_ad16c4t_enable_ier_comi(AD16C4T_TypeDef *timx) -{ - SET_BIT(timx->IER, AD16C4T_IER_COMI_MSK); -} - -/** - * @brief Timer capture/compare 4 interrupt enable. - * @param timx AD16C4T instance - * @retval None - */ - -__STATIC_INLINE void md_ad16c4t_enable_ier_ch4i(AD16C4T_TypeDef *timx) -{ - SET_BIT(timx->IER, AD16C4T_IER_CH4I_MSK); -} - -/** - * @brief Timer capture/compare 3 interrupt enable. - * @param timx AD16C4T instance - * @retval None - */ - -__STATIC_INLINE void md_ad16c4t_enable_ier_ch3i(AD16C4T_TypeDef *timx) -{ - SET_BIT(timx->IER, AD16C4T_IER_CH3I_MSK); -} - -/** - * @brief Timer capture/compare 2 interrupt enable. - * @param timx AD16C4T instance - * @retval None - */ - -__STATIC_INLINE void md_ad16c4t_enable_ier_ch2i(AD16C4T_TypeDef *timx) -{ - SET_BIT(timx->IER, AD16C4T_IER_CH2I_MSK); -} - -/** - * @brief Timer capture/compare 1 interrupt enable. - * @param timx AD16C4T instance - * @retval None - */ - -__STATIC_INLINE void md_ad16c4t_enable_ier_ch1i(AD16C4T_TypeDef *timx) -{ - SET_BIT(timx->IER, AD16C4T_IER_CH1I_MSK); -} - -/** - * @brief Timer update interrupt enable. - * @param timx AD16C4T instance - * @retval None - */ - -__STATIC_INLINE void md_ad16c4t_enable_ier_ui(AD16C4T_TypeDef *timx) -{ - SET_BIT(timx->IER, AD16C4T_IER_UI_MSK); -} - -/** - * @brief Timer IDR setup. - * @param timx AD16C4T instance - * @param value (CH4OVI | CH3OVI | CH2OVI | CH1OVI | BRKI | TRGI | COMI | CH4I | CH3I | CH2I | CH1I | UI) - * @retval None - */ - -__STATIC_INLINE void md_ad16c4t_set_idr(AD16C4T_TypeDef *timx, uint32_t value) -{ - WRITE_REG(timx->IDR, value); -} - -/** - * @brief Timer cpture/compare 4 overcapture interrupt disable. - * @param timx AD16C4T instance - * @retval None - */ - -__STATIC_INLINE void md_ad16c4t_disable_idr_ch4ovi(AD16C4T_TypeDef *timx) -{ - SET_BIT(timx->IDR, AD16C4T_IDR_CH4OVI_MSK); -} - -/** - * @brief Timer cpture/compare 3 overcapture interrupt disable. - * @param timx AD16C4T instance - * @retval None - */ - -__STATIC_INLINE void md_ad16c4t_disable_idr_ch3ovi(AD16C4T_TypeDef *timx) -{ - SET_BIT(timx->IDR, AD16C4T_IDR_CH3OVI_MSK); -} - -/** - * @brief Timer cpture/compare 2 overcapture interrupt disable. - * @param timx AD16C4T instance - * @retval None - */ - -__STATIC_INLINE void md_ad16c4t_disable_idr_ch2ovi(AD16C4T_TypeDef *timx) -{ - SET_BIT(timx->IDR, AD16C4T_IDR_CH2OVI_MSK); -} - -/** - * @brief Timer cpture/compare 1 overcapture interrupt disable. - * @param timx AD16C4T instance - * @retval None - */ - -__STATIC_INLINE void md_ad16c4t_disable_idr_ch1ovi(AD16C4T_TypeDef *timx) -{ - SET_BIT(timx->IDR, AD16C4T_IDR_CH1OVI_MSK); -} - -/** - * @brief Timer break interrupt disable. - * @param timx AD16C4T instance - * @retval None - */ - -__STATIC_INLINE void md_ad16c4t_disable_idr_brki(AD16C4T_TypeDef *timx) -{ - SET_BIT(timx->IDR, AD16C4T_IDR_BRKI_MSK); -} - -/** - * @brief Timer trigger interrupt disable. - * @param timx AD16C4T instance - * @retval None - */ - -__STATIC_INLINE void md_ad16c4t_disable_idr_trgi(AD16C4T_TypeDef *timx) -{ - SET_BIT(timx->IDR, AD16C4T_IDR_TRGI_MSK); -} - -/** - * @brief Timer COM interrupt disable. - * @param timx AD16C4T instance - * @retval None - */ - -__STATIC_INLINE void md_ad16c4t_disable_idr_comi(AD16C4T_TypeDef *timx) -{ - SET_BIT(timx->IDR, AD16C4T_IDR_COMI_MSK); -} - -/** - * @brief Timer capture/compare 4 interrupt disable. - * @param timx AD16C4T instance - * @retval None - */ - -__STATIC_INLINE void md_ad16c4t_disable_idr_ch4i(AD16C4T_TypeDef *timx) -{ - SET_BIT(timx->IDR, AD16C4T_IDR_CH4I_MSK); -} - -/** - * @brief Timer capture/compare 3 interrupt disable. - * @param timx AD16C4T instance - * @retval None - */ - -__STATIC_INLINE void md_ad16c4t_disable_idr_ch3i(AD16C4T_TypeDef *timx) -{ - SET_BIT(timx->IDR, AD16C4T_IDR_CH3I_MSK); -} - -/** - * @brief Timer capture/compare 2 interrupt disable. - * @param timx AD16C4T instance - * @retval None - */ - -__STATIC_INLINE void md_ad16c4t_disable_idr_ch2i(AD16C4T_TypeDef *timx) -{ - SET_BIT(timx->IDR, AD16C4T_IDR_CH2I_MSK); -} - -/** - * @brief Timer capture/compare 1 interrupt disable. - * @param timx AD16C4T instance - * @retval None - */ - -__STATIC_INLINE void md_ad16c4t_disable_idr_ch1i(AD16C4T_TypeDef *timx) -{ - SET_BIT(timx->IDR, AD16C4T_IDR_CH1I_MSK); -} - -/** - * @brief Timer update interrupt disable. - * @param timx AD16C4T instance - * @retval None - */ - -__STATIC_INLINE void md_ad16c4t_disable_idr_ui(AD16C4T_TypeDef *timx) -{ - SET_BIT(timx->IDR, AD16C4T_IDR_UI_MSK); -} - -/** - * @brief Get timer IVS setup. - * @param timx AD16C4T instance - * @retval Timer IVS setup. - */ - -__STATIC_INLINE uint32_t md_ad16c4t_get_ivs(AD16C4T_TypeDef *timx) -{ - return (READ_REG(timx->IVS)); -} - -/** - * @brief Indicates whether the timer capture/compare 4 overcapture interrupt is enabled. - * @param timx AD16C4T instance - * @retval State of bit (1 or 0). - */ - -__STATIC_INLINE uint32_t md_ad16c4t_is_enabled_ivs_ch4ovi(AD16C4T_TypeDef *timx) -{ - return (READ_BIT(timx->IVS, AD16C4T_IVS_CH4OVI_MSK) == (AD16C4T_IVS_CH4OVI_MSK)); -} - -/** - * @brief Indicates whether the timer capture/compare 3 overcapture interrupt is enabled. - * @param timx AD16C4T instance - * @retval State of bit (1 or 0). - */ - -__STATIC_INLINE uint32_t md_ad16c4t_is_enabled_ivs_ch3ovi(AD16C4T_TypeDef *timx) -{ - return (READ_BIT(timx->IVS, AD16C4T_IVS_CH3OVI_MSK) == (AD16C4T_IVS_CH3OVI_MSK)); -} - -/** - * @brief Indicates whether the timer cpture/compare 2 overcapture interrupt is enabled. - * @param timx AD16C4T instance - * @retval State of bit (1 or 0). - */ - -__STATIC_INLINE uint32_t md_ad16c4t_is_enabled_ivs_ch2ovi(AD16C4T_TypeDef *timx) -{ - return (READ_BIT(timx->IVS, AD16C4T_IVS_CH2OVI_MSK) == (AD16C4T_IVS_CH2OVI_MSK)); -} - -/** - * @brief Indicates whether the timer capture/compare 1 overcapture interrupt is enabled. - * @param timx AD16C4T instance - * @retval State of bit (1 or 0). - */ - -__STATIC_INLINE uint32_t md_ad16c4t_is_enabled_ivs_ch1ovi(AD16C4T_TypeDef *timx) -{ - return (READ_BIT(timx->IVS, AD16C4T_IVS_CH1OVI_MSK) == (AD16C4T_IVS_CH1OVI_MSK)); -} - -/** - * @brief Indicates whether the timer break interrupt is enabled. - * @param timx AD16C4T instance - * @retval State of bit (1 or 0). - */ - -__STATIC_INLINE uint32_t md_ad16c4t_is_enabled_ivs_brki(AD16C4T_TypeDef *timx) -{ - return (READ_BIT(timx->IVS, AD16C4T_IVS_BRKI_MSK) == (AD16C4T_IVS_BRKI_MSK)); -} - -/** - * @brief Indicates whether the timer trigger interrupt is enabled. - * @param timx AD16C4T instance - * @retval State of bit (1 or 0). - */ - -__STATIC_INLINE uint32_t md_ad16c4t_is_enabled_ivs_trgi(AD16C4T_TypeDef *timx) -{ - return (READ_BIT(timx->IVS, AD16C4T_IVS_TRGI_MSK) == (AD16C4T_IVS_TRGI_MSK)); -} - -/** - * @brief Indicates whether the timer COM interrupt is enabled. - * @param timx AD16C4T instance - * @retval State of bit (1 or 0). - */ - -__STATIC_INLINE uint32_t md_ad16c4t_is_enabled_ivs_comi(AD16C4T_TypeDef *timx) -{ - return (READ_BIT(timx->IVS, AD16C4T_IVS_COMI_MSK) == (AD16C4T_IVS_COMI_MSK)); -} - -/** - * @brief Indicates whether the timer Capture/Compare 4 interrupt is enabled. - * @param timx AD16C4T instance - * @retval State of bit (1 or 0). - */ - -__STATIC_INLINE uint32_t md_ad16c4t_is_enabled_ivs_ch4i(AD16C4T_TypeDef *timx) -{ - return (READ_BIT(timx->IVS, AD16C4T_IVS_CH4I_MSK) == (AD16C4T_IVS_CH4I_MSK)); -} - -/** - * @brief Indicates whether the timer Capture/Compare 3 interrupt is enabled. - * @param timx AD16C4T instance - * @retval State of bit (1 or 0). - */ - -__STATIC_INLINE uint32_t md_ad16c4t_is_enabled_ivs_ch3i(AD16C4T_TypeDef *timx) -{ - return (READ_BIT(timx->IVS, AD16C4T_IVS_CH3I_MSK) == (AD16C4T_IVS_CH3I_MSK)); -} - -/** - * @brief Indicates whether the timer Capture/Compare 2 interrupt is enabled. - * @param timx AD16C4T instance - * @retval State of bit (1 or 0). - */ - -__STATIC_INLINE uint32_t md_ad16c4t_is_enabled_ivs_ch2i(AD16C4T_TypeDef *timx) -{ - return (READ_BIT(timx->IVS, AD16C4T_IVS_CH2I_MSK) == (AD16C4T_IVS_CH2I_MSK)); -} - -/** - * @brief Indicates whether the timer Capture/Compare 1 interrupt is enabled. - * @param timx AD16C4T instance - * @retval State of bit (1 or 0). - */ - -__STATIC_INLINE uint32_t md_ad16c4t_is_enabled_ivs_ch1i(AD16C4T_TypeDef *timx) -{ - return (READ_BIT(timx->IVS, AD16C4T_IVS_CH1I_MSK) == (AD16C4T_IVS_CH1I_MSK)); -} - -/** - * @brief Indicates whether the timer update interrupt is enabled. - * @param timx AD16C4T instance - * @retval State of bit (1 or 0). - */ - -__STATIC_INLINE uint32_t md_ad16c4t_is_enabled_ivs_ui(AD16C4T_TypeDef *timx) -{ - return (READ_BIT(timx->IVS, AD16C4T_IVS_UI_MSK) == (AD16C4T_IVS_UI_MSK)); -} - -/** - * @brief Get timer RIF flag. - * @param timx AD16C4T instance - * @retval Timer RIF flag. - */ - -__STATIC_INLINE uint32_t md_ad16c4t_get_rif(AD16C4T_TypeDef *timx) -{ - return (READ_REG(timx->RIF)); -} - -/** - * @brief Get timer capture/compare 4 overcapture interrupt flag. - * @param timx AD16C4T instance - * @retval State of bit (1 or 0). - */ -__STATIC_INLINE uint32_t md_ad16c4t_is_active_flag_rif_ch4ovi(AD16C4T_TypeDef *timx) -{ - return (READ_BIT(timx->RIF, AD16C4T_RIF_CH4OVI_MSK) == (AD16C4T_RIF_CH4OVI_MSK)); -} - -/** - * @brief Get timer capture/compare 3 overcapture interrupt flag. - * @param timx AD16C4T instance - * @retval State of bit (1 or 0). - */ -__STATIC_INLINE uint32_t md_ad16c4t_is_active_flag_rif_ch3ovi(AD16C4T_TypeDef *timx) -{ - return (READ_BIT(timx->RIF, AD16C4T_RIF_CH3OVI_MSK) == (AD16C4T_RIF_CH3OVI_MSK)); -} - -/** - * @brief Get timer capture/compare 2 overcapture interrupt flag. - * @param timx AD16C4T instance - * @retval State of bit (1 or 0). - */ -__STATIC_INLINE uint32_t md_ad16c4t_is_active_flag_rif_ch2ovi(AD16C4T_TypeDef *timx) -{ - return (READ_BIT(timx->RIF, AD16C4T_RIF_CH2OVI_MSK) == (AD16C4T_RIF_CH2OVI_MSK)); -} - -/** - * @brief Get timer capture/compare 1 overcapture interrupt flag. - * @param timx AD16C4T instance - * @retval State of bit (1 or 0). - */ -__STATIC_INLINE uint32_t md_ad16c4t_is_active_flag_rif_ch1ovi(AD16C4T_TypeDef *timx) -{ - return (READ_BIT(timx->RIF, AD16C4T_RIF_CH1OVI_MSK) == (AD16C4T_RIF_CH1OVI_MSK)); -} - -/** - * @brief Get timer break interrupt flag. - * @param timx AD16C4T instance - * @retval State of bit (1 or 0). - */ -__STATIC_INLINE uint32_t md_ad16c4t_is_active_flag_rif_brki(AD16C4T_TypeDef *timx) -{ - return (READ_BIT(timx->RIF, AD16C4T_RIF_BRKI_MSK) == (AD16C4T_RIF_BRKI_MSK)); -} - -/** - * @brief Get timer trigger interrupt flag. - * @param timx AD16C4T instance - * @retval State of bit (1 or 0). - */ -__STATIC_INLINE uint32_t md_ad16c4t_is_active_flag_rif_trgi(AD16C4T_TypeDef *timx) -{ - return (READ_BIT(timx->RIF, AD16C4T_RIF_TRGI_MSK) == (AD16C4T_RIF_TRGI_MSK)); -} - -/** - * @brief Get timer COM interrupt flag. - * @param timx AD16C4T instance - * @retval State of bit (1 or 0). - */ -__STATIC_INLINE uint32_t md_ad16c4t_is_active_flag_rif_comi(AD16C4T_TypeDef *timx) -{ - return (READ_BIT(timx->RIF, AD16C4T_RIF_COMI_MSK) == (AD16C4T_RIF_COMI_MSK)); -} - -/** - * @brief Get timer capture/compare 4 interrupt flag. - * @param timx AD16C4T instance - * @retval State of bit (1 or 0). - */ -__STATIC_INLINE uint32_t md_ad16c4t_is_active_flag_rif_ch4i(AD16C4T_TypeDef *timx) -{ - return (READ_BIT(timx->RIF, AD16C4T_RIF_CH4I_MSK) == (AD16C4T_RIF_CH4I_MSK)); -} - -/** - * @brief Get timer capture/compare 3 interrupt flag. - * @param timx AD16C4T instance - * @retval State of bit (1 or 0). - */ -__STATIC_INLINE uint32_t md_ad16c4t_is_active_flag_rif_ch3i(AD16C4T_TypeDef *timx) -{ - return (READ_BIT(timx->RIF, AD16C4T_RIF_CH3I_MSK) == (AD16C4T_RIF_CH3I_MSK)); -} - -/** - * @brief Get timer capture/compare 2 interrupt flag. - * @param timx AD16C4T instance - * @retval State of bit (1 or 0). - */ -__STATIC_INLINE uint32_t md_ad16c4t_is_active_flag_rif_ch2i(AD16C4T_TypeDef *timx) -{ - return (READ_BIT(timx->RIF, AD16C4T_RIF_CH2I_MSK) == (AD16C4T_RIF_CH2I_MSK)); -} - -/** - * @brief Get timer capture/compare 1 interrupt flag. - * @param timx AD16C4T instance - * @retval State of bit (1 or 0). - */ -__STATIC_INLINE uint32_t md_ad16c4t_is_active_flag_rif_ch1i(AD16C4T_TypeDef *timx) -{ - return (READ_BIT(timx->RIF, AD16C4T_RIF_CH1I_MSK) == (AD16C4T_RIF_CH1I_MSK)); -} - -/** - * @brief Get timer update interrupt flag. - * @param timx AD16C4T instance - * @retval State of bit (1 or 0). - */ -__STATIC_INLINE uint32_t md_ad16c4t_is_active_flag_rif_ui(AD16C4T_TypeDef *timx) -{ - return (READ_BIT(timx->RIF, AD16C4T_RIF_UI_MSK) == (AD16C4T_RIF_UI_MSK)); -} - -/** - * @brief Get timer IFM flag. - * @param timx AD16C4T instance - * @retval Timer IFM flag. - */ - -__STATIC_INLINE uint32_t md_ad16c4t_get_ifm(AD16C4T_TypeDef *timx) -{ - return (READ_REG(timx->IFM)); -} - -/** - * @brief Get timer capture/compare 4 overcapture interrupt flag masked. - * @param timx AD16C4T instance - * @retval State of bit (1 or 0). - */ -__STATIC_INLINE uint32_t md_ad16c4t_is_active_flag_ifm_ch4ovi(AD16C4T_TypeDef *timx) -{ - return (READ_BIT(timx->IFM, AD16C4T_IFM_CH4OVI_MSK) == (AD16C4T_IFM_CH4OVI_MSK)); -} - -/** - * @brief Get timer capture/compare 3 overcapture interrupt flag masked. - * @param timx AD16C4T instance - * @retval State of bit (1 or 0). - */ -__STATIC_INLINE uint32_t md_ad16c4t_is_active_flag_ifm_ch3ovi(AD16C4T_TypeDef *timx) -{ - return (READ_BIT(timx->IFM, AD16C4T_IFM_CH3OVI_MSK) == (AD16C4T_IFM_CH3OVI_MSK)); -} - -/** - * @brief Get timer capture/compare 2 overcapture interrupt flag masked. - * @param timx AD16C4T instance - * @retval State of bit (1 or 0). - */ -__STATIC_INLINE uint32_t md_ad16c4t_is_active_flag_ifm_ch2ovi(AD16C4T_TypeDef *timx) -{ - return (READ_BIT(timx->IFM, AD16C4T_IFM_CH2OVI_MSK) == (AD16C4T_IFM_CH2OVI_MSK)); -} - -/** - * @brief Get timer capture/compare 1 overcapture interrupt flag masked. - * @param timx AD16C4T instance - * @retval State of bit (1 or 0). - */ -__STATIC_INLINE uint32_t md_ad16c4t_is_active_flag_ifm_ch1ovi(AD16C4T_TypeDef *timx) -{ - return (READ_BIT(timx->IFM, AD16C4T_IFM_CH1OVI_MSK) == (AD16C4T_IFM_CH1OVI_MSK)); -} - -/** - * @brief Get timer break interrupt flag masked. - * @param timx AD16C4T instance - * @retval State of bit (1 or 0). - */ -__STATIC_INLINE uint32_t md_ad16c4t_is_active_flag_ifm_brki(AD16C4T_TypeDef *timx) -{ - return (READ_BIT(timx->IFM, AD16C4T_IFM_BRKI_MSK) == (AD16C4T_IFM_BRKI_MSK)); -} - -/** - * @brief Get timer trigger interrupt flag masked. - * @param timx AD16C4T instance - * @retval State of bit (1 or 0). - */ -__STATIC_INLINE uint32_t md_ad16c4t_is_active_flag_ifm_trgi(AD16C4T_TypeDef *timx) -{ - return (READ_BIT(timx->IFM, AD16C4T_IFM_TRGI_MSK) == (AD16C4T_IFM_TRGI_MSK)); -} - -/** - * @brief Get timer COM interrupt flag masked. - * @param timx AD16C4T instance - * @retval State of bit (1 or 0). - */ -__STATIC_INLINE uint32_t md_ad16c4t_is_active_flag_ifm_comi(AD16C4T_TypeDef *timx) -{ - return (READ_BIT(timx->IFM, AD16C4T_IFM_COMI_MSK) == (AD16C4T_IFM_COMI_MSK)); -} - -/** - * @brief Get timer capture/compare 4 interrupt flag masked. - * @param timx AD16C4T instance - * @retval State of bit (1 or 0). - */ -__STATIC_INLINE uint32_t md_ad16c4t_is_active_flag_ifm_ch4i(AD16C4T_TypeDef *timx) -{ - return (READ_BIT(timx->IFM, AD16C4T_IFM_CH4I_MSK) == (AD16C4T_IFM_CH4I_MSK)); -} - -/** - * @brief Get timer capture/compare 3 interrupt flag masked. - * @param timx AD16C4T instance - * @retval State of bit (1 or 0). - */ -__STATIC_INLINE uint32_t md_ad16c4t_is_active_flag_ifm_ch3i(AD16C4T_TypeDef *timx) -{ - return (READ_BIT(timx->IFM, AD16C4T_IFM_CH3I_MSK) == (AD16C4T_IFM_CH3I_MSK)); -} - -/** - * @brief Get timer capture/compare 2 interrupt flag masked. - * @param timx AD16C4T instance - * @retval State of bit (1 or 0). - */ -__STATIC_INLINE uint32_t md_ad16c4t_is_active_flag_ifm_ch2i(AD16C4T_TypeDef *timx) -{ - return (READ_BIT(timx->IFM, AD16C4T_IFM_CH2I_MSK) == (AD16C4T_IFM_CH2I_MSK)); -} - -/** - * @brief Get timer capture/compare 1 interrupt flag masked. - * @param timx AD16C4T instance - * @retval State of bit (1 or 0). - */ -__STATIC_INLINE uint32_t md_ad16c4t_is_active_flag_ifm_ch1i(AD16C4T_TypeDef *timx) -{ - return (READ_BIT(timx->IFM, AD16C4T_IFM_CH1I_MSK) == (AD16C4T_IFM_CH1I_MSK)); -} - -/** - * @brief Get timer update interrupt flag masked. - * @param timx AD16C4T instance - * @retval State of bit (1 or 0). - */ -__STATIC_INLINE uint32_t md_ad16c4t_is_active_flag_ifm_ui(AD16C4T_TypeDef *timx) -{ - return (READ_BIT(timx->IFM, AD16C4T_IFM_UI_MSK) == (AD16C4T_IFM_UI_MSK)); -} - -/** - * @brief Timer ICR setup. - * @param timx AD16C4T instance - * @param value (CC4OI | CC3OI | CC2OI | CC1OI | BI | TI | COMI | CC4I | CC3I | CC2I | CC1I | UI) - * @retval None - */ - -__STATIC_INLINE void md_ad16c4t_set_icr(AD16C4T_TypeDef *timx, uint32_t value) -{ - WRITE_REG(timx->ICR, value); -} - -/** - * @brief Clear timer cpture/compare 4 overcapture interrupt flag. - * @param timx AD16C4T instance - * @retval None - */ - -__STATIC_INLINE void md_ad16c4t_clear_flag_icr_ch4ovi(AD16C4T_TypeDef *timx) -{ - SET_BIT(timx->ICR, AD16C4T_ICR_CH4OVI_MSK); -} - -/** - * @brief Clear timer cpture/compare 3 overcapture interrupt flag. - * @param timx AD16C4T instance - * @retval None - */ - -__STATIC_INLINE void md_ad16c4t_clear_flag_icr_ch3ovi(AD16C4T_TypeDef *timx) -{ - SET_BIT(timx->ICR, AD16C4T_ICR_CH3OVI_MSK); -} - -/** - * @brief Clear timer cpture/compare 2 overcapture interrupt flag. - * @param timx AD16C4T instance - * @retval None - */ - -__STATIC_INLINE void md_ad16c4t_clear_flag_icr_ch2ovi(AD16C4T_TypeDef *timx) -{ - SET_BIT(timx->ICR, AD16C4T_ICR_CH2OVI_MSK); -} - -/** - * @brief Clear timer cpture/compare 1 overcapture interrupt flag. - * @param timx AD16C4T instance - * @retval None - */ - -__STATIC_INLINE void md_ad16c4t_clear_flag_icr_ch1ovi(AD16C4T_TypeDef *timx) -{ - SET_BIT(timx->ICR, AD16C4T_ICR_CH1OVI_MSK); -} - -/** - * @brief Clear timer break interrupt flag. - * @param timx AD16C4T instance - * @retval None - */ - -__STATIC_INLINE void md_ad16c4t_clear_flag_icr_brki(AD16C4T_TypeDef *timx) -{ - SET_BIT(timx->ICR, AD16C4T_ICR_BRKI_MSK); -} - -/** - * @brief Clear timer trigger interrupt flag. - * @param timx AD16C4T instance - * @retval None - */ - -__STATIC_INLINE void md_ad16c4t_clear_flag_icr_trgi(AD16C4T_TypeDef *timx) -{ - SET_BIT(timx->ICR, AD16C4T_ICR_TRGI_MSK); -} - -/** - * @brief Clear timer COM interrupt flag. - * @param timx AD16C4T instance - * @retval None - */ - -__STATIC_INLINE void md_ad16c4t_clear_flag_icr_comi(AD16C4T_TypeDef *timx) -{ - SET_BIT(timx->ICR, AD16C4T_ICR_COMI_MSK); -} - -/** - * @brief Clear timer capture/compare 4 interrupt flag. - * @param timx AD16C4T instance - * @retval None - */ - -__STATIC_INLINE void md_ad16c4t_clear_flag_icr_ch4i(AD16C4T_TypeDef *timx) -{ - SET_BIT(timx->ICR, AD16C4T_ICR_CH4I_MSK); -} - -/** - * @brief Clear timer capture/compare 3 interrupt flag. - * @param timx AD16C4T instance - * @retval None - */ - -__STATIC_INLINE void md_ad16c4t_clear_flag_icr_ch3i(AD16C4T_TypeDef *timx) -{ - SET_BIT(timx->ICR, AD16C4T_ICR_CH3I_MSK); -} - -/** - * @brief Clear timer capture/compare 2 interrupt flag. - * @param timx AD16C4T instance - * @retval None - */ - -__STATIC_INLINE void md_ad16c4t_clear_flag_icr_ch2i(AD16C4T_TypeDef *timx) -{ - SET_BIT(timx->ICR, AD16C4T_ICR_CH2I_MSK); -} - -/** - * @brief Clear timer capture/compare 1 interrupt flag. - * @param timx AD16C4T instance - * @retval None - */ - -__STATIC_INLINE void md_ad16c4t_clear_flag_icr_ch1i(AD16C4T_TypeDef *timx) -{ - SET_BIT(timx->ICR, AD16C4T_ICR_CH1I_MSK); -} - -/** - * @brief Clear timer upadte flag. - * @param timx AD16C4T instance - * @retval None - */ - -__STATIC_INLINE void md_ad16c4t_clear_flag_icr_ui(AD16C4T_TypeDef *timx) -{ - SET_BIT(timx->ICR, AD16C4T_ICR_UI_MSK); -} - -/** - * @brief Timer SGE setup. - * @param timx AD16C4T instance - * @param value (SGBRK | SGTRG | SGCOM | SGCH4 | SGCH3 | SGCH2 | SGCH1 | SGU) - * @retval None - */ - -__STATIC_INLINE void md_ad16c4t_set_sge(AD16C4T_TypeDef *timx, uint32_t value) -{ - WRITE_REG(timx->SGE, value); -} - -/** - * @brief Timer break generation. - * @param timx AD16C4T instance - * @retval None - */ - -__STATIC_INLINE void md_ad16c4t_set_sge_sgbrk(AD16C4T_TypeDef *timx) -{ - SET_BIT(timx->SGE, AD16C4T_SGE_SGBRK_MSK); -} - -/** - * @brief Timer trigger generation. - * @param timx AD16C4T instance - * @retval None - */ - -__STATIC_INLINE void md_ad16c4t_set_sge_sgtrg(AD16C4T_TypeDef *timx) -{ - SET_BIT(timx->SGE, AD16C4T_SGE_SGTRG_MSK); -} - -/** - * @brief Timer COM generation. - * @param timx AD16C4T instance - * @retval None - */ - -__STATIC_INLINE void md_ad16c4t_set_sge_sgcom(AD16C4T_TypeDef *timx) -{ - SET_BIT(timx->SGE, AD16C4T_SGE_SGCOM_MSK); -} - -/** - * @brief Timer Capture/Compare 4 generation. - * @param timx AD16C4T instance - * @retval None - */ - -__STATIC_INLINE void md_ad16c4t_set_sge_sgch4(AD16C4T_TypeDef *timx) -{ - SET_BIT(timx->SGE, AD16C4T_SGE_SGCH4_MSK); -} - -/** - * @brief Timer Capture/Compare 3 generation. - * @param timx AD16C4T instance - * @retval None - */ - -__STATIC_INLINE void md_ad16c4t_set_sge_sgch3(AD16C4T_TypeDef *timx) -{ - SET_BIT(timx->SGE, AD16C4T_SGE_SGCH3_MSK); -} - -/** - * @brief Timer Capture/Compare 2 generation. - * @param timx AD16C4T instance - * @retval None - */ - -__STATIC_INLINE void md_ad16c4t_set_sge_sgch2(AD16C4T_TypeDef *timx) -{ - SET_BIT(timx->SGE, AD16C4T_SGE_SGCH2_MSK); -} - -/** - * @brief Timer Capture/Compare 1 generation. - * @param timx AD16C4T instance - * @retval None - */ - -__STATIC_INLINE void md_ad16c4t_set_sge_sgch1(AD16C4T_TypeDef *timx) -{ - SET_BIT(timx->SGE, AD16C4T_SGE_SGCH1_MSK); -} - -/** - * @brief Timer update generation. - * @param timx AD16C4T instance - * @retval None - */ - -__STATIC_INLINE void md_ad16c4t_set_sge_sgu(AD16C4T_TypeDef *timx) -{ - SET_BIT(timx->SGE, AD16C4T_SGE_SGU_MSK); -} - -/** - * @brief Timer CHMR1 setup. - * @param timx AD16C4T instance - * @param value output (CH2OCLREN | CH2MOD | CH2PEN | CH2FEN | CC2SSEL | CH1OCLREN | CH1MOD | CH1PEN | CH1FEN | CC1SSEL) - * input (I2FLT | I2PRES | CC2SSEL | I1FLT | I1PRES | CC1SSEL) - * @retval None - */ - -__STATIC_INLINE void md_ad16c4t_set_chmr1(AD16C4T_TypeDef *timx, uint32_t value) -{ - WRITE_REG(timx->CHMR1, value); -} - -/** - * @brief GET Timer CHMR1 register value. - * @param timx AD16C4T instance - * @retval Timer CHMR1 register value. - */ - -__STATIC_INLINE uint32_t md_ad16c4t_get_chmr1(AD16C4T_TypeDef *timx) -{ - return (READ_REG(timx->CHMR1)); -} - -/** - * @brief Timer output compare 2 clear enable. - * @param timx AD16C4T instance - * @retval None - */ - -__STATIC_INLINE void md_ad16c4t_enable_chmr1_output_ch2oclren(AD16C4T_TypeDef *timx) -{ - SET_BIT(timx->CHMR1, AD16C4T_CHMR1_OUTPUT_CH2OCLREN_MSK); -} - -/** - * @brief Timer output compare 2 clear disable. - * @param timx AD16C4T instance - * @retval None - */ - -__STATIC_INLINE void md_ad16c4t_disable_chmr1_output_ch2oclren(AD16C4T_TypeDef *timx) -{ - CLEAR_BIT(timx->CHMR1, AD16C4T_CHMR1_OUTPUT_CH2OCLREN_MSK); -} - -/** - * @brief Indicates whether the timer output compare 2 clear is enabled. - * @param timx AD16C4T instance - * @retval State of bit (1 or 0). - */ - -__STATIC_INLINE uint32_t md_ad16c4t_is_enabled_chmr1_output_ch2oclren(AD16C4T_TypeDef *timx) -{ - return (READ_BIT(timx->CHMR1, AD16C4T_CHMR1_OUTPUT_CH2OCLREN_MSK) == (AD16C4T_CHMR1_OUTPUT_CH2OCLREN_MSK)); -} - -/** - * @brief Timer output compare 2 mode setup. - * @param timx AD16C4T instance - * @param OutputMode Output compare mode - @arg @ref MD_AD16C4T_OUTPUTMODE_DISABLE - @arg @ref MD_AD16C4T_OUTPUTMODE_HIGHONMSTCH - @arg @ref MD_AD16C4T_OUTPUTMODE_LOWONMSTCH - @arg @ref MD_AD16C4T_OUTPUTMODE_TOGGLE - @arg @ref MD_AD16C4T_OUTPUTMODE_FORCELOW - @arg @ref MD_AD16C4T_OUTPUTMODE_FORCEHIGH - @arg @ref MD_AD16C4T_OUTPUTMODE_PWMMODE1 - @arg @ref MD_AD16C4T_OUTPUTMODE_PWMMODE2 - * @retval None - */ - -__STATIC_INLINE void md_ad16c4t_set_chmr1_output_ch2mod(AD16C4T_TypeDef *timx, uint32_t OutputMode) -{ - MODIFY_REG(timx->CHMR1, AD16C4T_CHMR1_OUTPUT_CH2MOD_MSK, (OutputMode << AD16C4T_CHMR1_OUTPUT_CH2MOD_POSS)); -} - -/** - * @brief Get timer output compare 2 mode. - * @param timx AD16C4T instance - * @retval Timer output compare 2 mode. - */ - -__STATIC_INLINE uint32_t md_ad16c4t_get_chmr1_output_ch2mod(AD16C4T_TypeDef *timx) -{ - return (READ_BIT(timx->CHMR1, AD16C4T_CHMR1_OUTPUT_CH2MOD_MSK) >> AD16C4T_CHMR1_OUTPUT_CH2MOD_POSS); -} - -/** - * @brief Timer output compare 2 preload enable. - * @param timx AD16C4T instance - * @retval None - */ - -__STATIC_INLINE void md_ad16c4t_enable_chmr1_output_ch2pen(AD16C4T_TypeDef *timx) -{ - SET_BIT(timx->CHMR1, AD16C4T_CHMR1_OUTPUT_CH2PEN_MSK); -} - -/** - * @brief Timer output compare 2 preload disable. - * @param timx AD16C4T instance - * @retval None - */ - -__STATIC_INLINE void md_ad16c4t_disable_chmr1_output_ch2pen(AD16C4T_TypeDef *timx) -{ - CLEAR_BIT(timx->CHMR1, AD16C4T_CHMR1_OUTPUT_CH2PEN_MSK); -} - -/** - * @brief Indicates whether the timer output compare 2 preload is enabled. - * @param timx AD16C4T instance - * @retval State of bit (1 or 0). - */ - -__STATIC_INLINE uint32_t md_ad16c4t_is_enabled_chmr1_output_ch2pen(AD16C4T_TypeDef *timx) -{ - return (READ_BIT(timx->CHMR1, AD16C4T_CHMR1_OUTPUT_CH2PEN_MSK) == (AD16C4T_CHMR1_OUTPUT_CH2PEN_MSK)); -} - -/** - * @brief Timer output compare 2 fast enable. - * @param timx AD16C4T instance - * @retval None - */ - -__STATIC_INLINE void md_ad16c4t_enable_chmr1_output_ch2fen(AD16C4T_TypeDef *timx) -{ - SET_BIT(timx->CHMR1, AD16C4T_CHMR1_OUTPUT_CH2FEN_MSK); -} - -/** - * @brief Timer output compare 2 fast disable. - * @param timx AD16C4T instance - * @retval None - */ - -__STATIC_INLINE void md_ad16c4t_disable_chmr1_output_ch2fen(AD16C4T_TypeDef *timx) -{ - CLEAR_BIT(timx->CHMR1, AD16C4T_CHMR1_OUTPUT_CH2FEN_MSK); -} - -/** - * @brief Indicates whether the timer output compare 2 fast is enabled. - * @param timx AD16C4T instance - * @retval State of bit (1 or 0). - */ - -__STATIC_INLINE uint32_t md_ad16c4t_is_enabled_chmr1_output_ch2fen(AD16C4T_TypeDef *timx) -{ - return (READ_BIT(timx->CHMR1, AD16C4T_CHMR1_OUTPUT_CH2FEN_MSK) == (AD16C4T_CHMR1_OUTPUT_CH2FEN_MSK)); -} - -/** - * @brief Timer cpture/compare 2 selection setup. - * @param timx AD16C4T instance - * @param ChannelMode Channel mode selection - @arg @ref MD_AD16C4T_CHMODE_OUTPUT - @arg @ref MD_AD16C4T_CHMODE_INPUT_DIRECT - @arg @ref MD_AD16C4T_CHMODE_INPUT_INDIRECT - @arg @ref MD_AD16C4T_CHMODE_INPUT_TRC - * @retval None - */ - -__STATIC_INLINE void md_ad16c4t_set_chmr1_output_cc2ssel(AD16C4T_TypeDef *timx, uint32_t ChannelMode) -{ - MODIFY_REG(timx->CHMR1, AD16C4T_CHMR1_OUTPUT_CC2SSEL_MSK, (ChannelMode << AD16C4T_CHMR1_OUTPUT_CC2SSEL_POSS)); -} - -/** - * @brief Get timer cpture/compare 2 selection. - * @param timx AD16C4T instance - * @retval Timer cpture/compare 2 selection. - */ - -__STATIC_INLINE uint32_t md_ad16c4t_get_chmr1_output_cc2ssel(AD16C4T_TypeDef *timx) -{ - return (READ_BIT(timx->CHMR1, AD16C4T_CHMR1_OUTPUT_CC2SSEL_MSK) >> AD16C4T_CHMR1_OUTPUT_CC2SSEL_POSS); -} - -/** - * @brief Timer output compare 1 clear enable. - * @param timx AD16C4T instance - * @retval None - */ - -__STATIC_INLINE void md_ad16c4t_enable_chmr1_output_ch1oclren(AD16C4T_TypeDef *timx) -{ - SET_BIT(timx->CHMR1, AD16C4T_CHMR1_OUTPUT_CH1OCLREN_MSK); -} - -/** - * @brief Timer output compare 1 clear disable. - * @param timx AD16C4T instance - * @retval None - */ - -__STATIC_INLINE void md_ad16c4t_disable_chmr1_output_ch1oclren(AD16C4T_TypeDef *timx) -{ - CLEAR_BIT(timx->CHMR1, AD16C4T_CHMR1_OUTPUT_CH1OCLREN_MSK); -} - -/** - * @brief Indicates whether the timer output compare 1 clear is enabled. - * @param timx AD16C4T instance - * @retval State of bit (1 or 0). - */ - -__STATIC_INLINE uint32_t md_ad16c4t_is_enabled_chmr1_output_ch1oclren(AD16C4T_TypeDef *timx) -{ - return (READ_BIT(timx->CHMR1, AD16C4T_CHMR1_OUTPUT_CH1OCLREN_MSK) == (AD16C4T_CHMR1_OUTPUT_CH1OCLREN_MSK)); -} - -/** - * @brief Timer output compare 1 mode setup. - * @param timx AD16C4T instance - * @param OutputMode Output compare mode - @arg @ref MD_AD16C4T_OUTPUTMODE_DISABLE - @arg @ref MD_AD16C4T_OUTPUTMODE_HIGHONMSTCH - @arg @ref MD_AD16C4T_OUTPUTMODE_LOWONMSTCH - @arg @ref MD_AD16C4T_OUTPUTMODE_TOGGLE - @arg @ref MD_AD16C4T_OUTPUTMODE_FORCELOW - @arg @ref MD_AD16C4T_OUTPUTMODE_FORCEHIGH - @arg @ref MD_AD16C4T_OUTPUTMODE_PWMMODE1 - @arg @ref MD_AD16C4T_OUTPUTMODE_PWMMODE2 - * @retval None - */ - -__STATIC_INLINE void md_ad16c4t_set_chmr1_output_ch1mod(AD16C4T_TypeDef *timx, uint32_t OutputMode) -{ - MODIFY_REG(timx->CHMR1, AD16C4T_CHMR1_OUTPUT_CH1MOD_MSK, (OutputMode << AD16C4T_CHMR1_OUTPUT_CH1MOD_POSS)); -} - -/** - * @brief Get timer output compare 1 mode. - * @param timx AD16C4T instance - * @retval Timer output compare 1 mode. - */ - -__STATIC_INLINE uint32_t md_ad16c4t_get_chmr1_output_ch1mod(AD16C4T_TypeDef *timx) -{ - return (READ_BIT(timx->CHMR1, AD16C4T_CHMR1_OUTPUT_CH1MOD_MSK) >> AD16C4T_CHMR1_OUTPUT_CH1MOD_POSS); -} - -/** - * @brief Timer output compare 1 preload enable. - * @param timx AD16C4T instance - * @retval None - */ - -__STATIC_INLINE void md_ad16c4t_enable_chmr1_output_ch1pen(AD16C4T_TypeDef *timx) -{ - SET_BIT(timx->CHMR1, AD16C4T_CHMR1_OUTPUT_CH1PEN_MSK); -} - -/** - * @brief Timer output compare 1 preload disable. - * @param timx AD16C4T instance - * @retval None - */ - -__STATIC_INLINE void md_ad16c4t_disable_chmr1_output_ch1pen(AD16C4T_TypeDef *timx) -{ - CLEAR_BIT(timx->CHMR1, AD16C4T_CHMR1_OUTPUT_CH1PEN_MSK); -} - -/** - * @brief Indicates whether the timer output compare 1 preload is enabled. - * @param timx AD16C4T instance - * @retval State of bit (1 or 0). - */ - -__STATIC_INLINE uint32_t md_ad16c4t_is_enabled_chmr1_output_ch1pen(AD16C4T_TypeDef *timx) -{ - return (READ_BIT(timx->CHMR1, AD16C4T_CHMR1_OUTPUT_CH1PEN_MSK) == (AD16C4T_CHMR1_OUTPUT_CH1PEN_MSK)); -} - -/** - * @brief Timer output compare 1 fast enable. - * @param timx AD16C4T instance - * @retval None - */ - -__STATIC_INLINE void md_ad16c4t_enable_chmr1_output_ch1fen(AD16C4T_TypeDef *timx) -{ - SET_BIT(timx->CHMR1, AD16C4T_CHMR1_OUTPUT_CH1FEN_MSK); -} - -/** - * @brief Timer output compare 1 fast disable. - * @param timx AD16C4T instance - * @retval None - */ - -__STATIC_INLINE void md_ad16c4t_disable_chmr1_output_ch1fen(AD16C4T_TypeDef *timx) -{ - CLEAR_BIT(timx->CHMR1, AD16C4T_CHMR1_OUTPUT_CH1FEN_MSK); -} - -/** - * @brief Indicates whether the timer output compare 1 fast is enabled. - * @param timx AD16C4T instance - * @retval State of bit (1 or 0). - */ - -__STATIC_INLINE uint32_t md_ad16c4t_is_enabled_chmr1_output_ch1fen(AD16C4T_TypeDef *timx) -{ - return (READ_BIT(timx->CHMR1, AD16C4T_CHMR1_OUTPUT_CH1FEN_MSK) == (AD16C4T_CHMR1_OUTPUT_CH1FEN_MSK)); -} - -/** - * @brief Timer cpture/compare 1 selection setup. - * @param timx AD16C4T instance - * @param ChannelMode Channel mode selection - @arg @ref MD_AD16C4T_CHMODE_OUTPUT - @arg @ref MD_AD16C4T_CHMODE_INPUT_DIRECT - @arg @ref MD_AD16C4T_CHMODE_INPUT_INDIRECT - @arg @ref MD_AD16C4T_CHMODE_INPUT_TRC - * @retval None - */ - -__STATIC_INLINE void md_ad16c4t_set_chmr1_output_cc1ssel(AD16C4T_TypeDef *timx, uint32_t ChannelMode) -{ - MODIFY_REG(timx->CHMR1, AD16C4T_CHMR1_OUTPUT_CC1SSEL_MSK, (ChannelMode << AD16C4T_CHMR1_OUTPUT_CC1SSEL_POSS)); -} - -/** - * @brief Get timer cpture/compare 1 selection. - * @param timx AD16C4T instance - * @retval Timer cpture/compare 1 selection. - */ - -__STATIC_INLINE uint32_t md_ad16c4t_get_chmr1_output_cc1ssel(AD16C4T_TypeDef *timx) -{ - return (READ_BIT(timx->CHMR1, AD16C4T_CHMR1_OUTPUT_CC1SSEL_MSK) >> AD16C4T_CHMR1_OUTPUT_CC1SSEL_POSS); -} - -/** - * @brief Timer input capture 2 filter setup. - * @param timx AD16C4T instance - * @param InputFliter Input capture filter - @arg @ref MD_AD16C4T_INPUTFILTER_FDIV1 - @arg @ref MD_AD16C4T_INPUTFILTER_FDIV1N2 - @arg @ref MD_AD16C4T_INPUTFILTER_FDIV1N4 - @arg @ref MD_AD16C4T_INPUTFILTER_FDIV1N8 - @arg @ref MD_AD16C4T_INPUTFILTER_FDIV2N6 - @arg @ref MD_AD16C4T_INPUTFILTER_FDIV2N8 - @arg @ref MD_AD16C4T_INPUTFILTER_FDIV4N6 - @arg @ref MD_AD16C4T_INPUTFILTER_FDIV4N8 - @arg @ref MD_AD16C4T_INPUTFILTER_FDIV8N6 - @arg @ref MD_AD16C4T_INPUTFILTER_FDIV8N8 - @arg @ref MD_AD16C4T_INPUTFILTER_FDIV16N5 - @arg @ref MD_AD16C4T_INPUTFILTER_FDIV16N6 - @arg @ref MD_AD16C4T_INPUTFILTER_FDIV16N8 - @arg @ref MD_AD16C4T_INPUTFILTER_FDIV32N5 - @arg @ref MD_AD16C4T_INPUTFILTER_FDIV32N6 - @arg @ref MD_AD16C4T_INPUTFILTER_FDIV32N8 - * @retval None - */ - -__STATIC_INLINE void md_ad16c4t_set_chmr1_input_i2flt(AD16C4T_TypeDef *timx, uint32_t InputFliter) -{ - MODIFY_REG(timx->CHMR1, AD16C4T_CHMR1_INPUT_I2FLT_MSK, (InputFliter << AD16C4T_CHMR1_INPUT_I2FLT_POSS)); -} - -/** - * @brief Get timer input capture 2 filter. - * @param timx AD16C4T instance - * @retval Timer input capture 2 filter. - */ - -__STATIC_INLINE uint32_t md_ad16c4t_get_chmr1_input_i2flt(AD16C4T_TypeDef *timx) -{ - return (READ_BIT(timx->CHMR1, AD16C4T_CHMR1_INPUT_I2FLT_MSK) >> AD16C4T_CHMR1_INPUT_I2FLT_POSS); -} - -/** - * @brief Timer input capture 2 prescaler setup. - * @param timx AD16C4T instance - * @param InputPrescale Input capture prescaler - @arg @ref MD_AD16C4T_INPUTPRESCALE_DIV1 - @arg @ref MD_AD16C4T_INPUTPRESCALE_DIV2 - @arg @ref MD_AD16C4T_INPUTPRESCALE_DIV4 - @arg @ref MD_AD16C4T_INPUTPRESCALE_DIV8 - * @retval None - */ - -__STATIC_INLINE void md_ad16c4t_set_chmr1_input_i2pres(AD16C4T_TypeDef *timx, uint32_t InputPrescale) -{ - MODIFY_REG(timx->CHMR1, AD16C4T_CHMR1_INPUT_I2PRES_MSK, (InputPrescale << AD16C4T_CHMR1_INPUT_I2PRES_POSS)); -} - -/** - * @brief Get timer input capture 2 prescaler. - * @param timx AD16C4T instance - * @retval Timer input capture 2 prescaler. - */ - -__STATIC_INLINE uint32_t md_ad16c4t_get_chmr1_input_i2pres(AD16C4T_TypeDef *timx) -{ - return (READ_BIT(timx->CHMR1, AD16C4T_CHMR1_INPUT_I2PRES_MSK) >> AD16C4T_CHMR1_INPUT_I2PRES_POSS); -} - -/** - * @brief Timer cpture/compare 2 selection setup. - * @param timx AD16C4T instance - * @param ChannelMode Channel mode selection - @arg @ref MD_AD16C4T_CHMODE_OUTPUT - @arg @ref MD_AD16C4T_CHMODE_INPUT_DIRECT - @arg @ref MD_AD16C4T_CHMODE_INPUT_INDIRECT - @arg @ref MD_AD16C4T_CHMODE_INPUT_TRC - * @retval None - */ - -__STATIC_INLINE void md_ad16c4t_set_chmr1_input_cc2ssel(AD16C4T_TypeDef *timx, uint32_t ChannelMode) -{ - MODIFY_REG(timx->CHMR1, AD16C4T_CHMR1_INPUT_CC2SSEL_MSK, (ChannelMode << AD16C4T_CHMR1_INPUT_CC2SSEL_POSS)); -} - -/** - * @brief Get timer cpture/compare 2 selection. - * @param timx AD16C4T instance - * @retval Timer cpture/compare 2 selection. - */ - -__STATIC_INLINE uint32_t md_ad16c4t_get_chmr1_input_cc2ssel(AD16C4T_TypeDef *timx) -{ - return (READ_BIT(timx->CHMR1, AD16C4T_CHMR1_INPUT_CC2SSEL_MSK) >> AD16C4T_CHMR1_INPUT_CC2SSEL_POSS); -} - -/** - * @brief Timer input capture 1 filter setup. - * @param timx AD16C4T instance - * @param InputFliter Input capture filter - @arg @ref MD_AD16C4T_INPUTFILTER_FDIV1 - @arg @ref MD_AD16C4T_INPUTFILTER_FDIV1N2 - @arg @ref MD_AD16C4T_INPUTFILTER_FDIV1N4 - @arg @ref MD_AD16C4T_INPUTFILTER_FDIV1N8 - @arg @ref MD_AD16C4T_INPUTFILTER_FDIV2N6 - @arg @ref MD_AD16C4T_INPUTFILTER_FDIV2N8 - @arg @ref MD_AD16C4T_INPUTFILTER_FDIV4N6 - @arg @ref MD_AD16C4T_INPUTFILTER_FDIV4N8 - @arg @ref MD_AD16C4T_INPUTFILTER_FDIV8N6 - @arg @ref MD_AD16C4T_INPUTFILTER_FDIV8N8 - @arg @ref MD_AD16C4T_INPUTFILTER_FDIV16N5 - @arg @ref MD_AD16C4T_INPUTFILTER_FDIV16N6 - @arg @ref MD_AD16C4T_INPUTFILTER_FDIV16N8 - @arg @ref MD_AD16C4T_INPUTFILTER_FDIV32N5 - @arg @ref MD_AD16C4T_INPUTFILTER_FDIV32N6 - @arg @ref MD_AD16C4T_INPUTFILTER_FDIV32N8 - * @retval None - */ - -__STATIC_INLINE void md_ad16c4t_set_chmr1_input_i1flt(AD16C4T_TypeDef *timx, uint32_t InputFliter) -{ - MODIFY_REG(timx->CHMR1, AD16C4T_CHMR1_INPUT_I1FLT_MSK, (InputFliter << AD16C4T_CHMR1_INPUT_I1FLT_POSS)); -} - -/** - * @brief Get timer input capture 1 filter. - * @param timx AD16C4T instance - * @retval Timer input capture 1 filter. - */ - -__STATIC_INLINE uint32_t md_ad16c4t_get_chmr1_input_i1flt(AD16C4T_TypeDef *timx) -{ - return (READ_BIT(timx->CHMR1, AD16C4T_CHMR1_INPUT_I1FLT_MSK) >> AD16C4T_CHMR1_INPUT_I1FLT_POSS); -} - -/** - * @brief Timer input capture 1 prescaler setup. - * @param timx AD16C4T instance - * @param InputPrescale Input capture prescaler - @arg @ref MD_AD16C4T_INPUTPRESCALE_DIV1 - @arg @ref MD_AD16C4T_INPUTPRESCALE_DIV2 - @arg @ref MD_AD16C4T_INPUTPRESCALE_DIV4 - @arg @ref MD_AD16C4T_INPUTPRESCALE_DIV8 - * @retval None - */ - -__STATIC_INLINE void md_ad16c4t_set_chmr1_input_i1pres(AD16C4T_TypeDef *timx, uint32_t InputPrescale) -{ - MODIFY_REG(timx->CHMR1, AD16C4T_CHMR1_INPUT_I1PRES_MSK, (InputPrescale << AD16C4T_CHMR1_INPUT_I1PRES_POSS)); -} - -/** - * @brief Get timer input capture 1 prescaler. - * @param timx AD16C4T instance - * @retval Timer input capture 1 prescaler. - */ - -__STATIC_INLINE uint32_t md_ad16c4t_get_chmr1_input_i1pres(AD16C4T_TypeDef *timx) -{ - return (READ_BIT(timx->CHMR1, AD16C4T_CHMR1_INPUT_I1PRES_MSK) >> AD16C4T_CHMR1_INPUT_I1PRES_POSS); -} - -/** - * @brief Timer cpture/compare 1 selection setup. - * @param timx AD16C4T instance - * @param ChannelMode Channel mode selection - @arg @ref MD_AD16C4T_CHMODE_OUTPUT - @arg @ref MD_AD16C4T_CHMODE_INPUT_DIRECT - @arg @ref MD_AD16C4T_CHMODE_INPUT_INDIRECT - @arg @ref MD_AD16C4T_CHMODE_INPUT_TRC - * @retval None - */ - -__STATIC_INLINE void md_ad16c4t_set_chmr1_input_cc1ssel(AD16C4T_TypeDef *timx, uint32_t ChannelMode) -{ - MODIFY_REG(timx->CHMR1, AD16C4T_CHMR1_INPUT_CC1SSEL_MSK, (ChannelMode << AD16C4T_CHMR1_INPUT_CC1SSEL_POSS)); -} - -/** - * @brief Get timer cpture/compare 1 selection. - * @param timx AD16C4T instance - * @retval Timer cpture/compare 1 selection. - */ - -__STATIC_INLINE uint32_t md_ad16c4t_get_chmr1_input_cc1ssel(AD16C4T_TypeDef *timx) -{ - return (READ_BIT(timx->CHMR1, AD16C4T_CHMR1_INPUT_CC1SSEL_MSK) >> AD16C4T_CHMR1_INPUT_CC1SSEL_POSS); -} - -/** - * @brief Timer CHMR2 setup. - - * @param timx AD16C4T instance - * @param value output (CH4OCLREN | CH4MOD | CH4PEN | CH4FEN | CC4SSEL | CH3OCLREN | CH3MOD | CH3PEN | CH3FEN | CC3SSEL) - * input (I4FLT | I4PRES | CC4SSEL | I3FLT | I3PRES | CC3SSEL) - * @retval None - */ - -__STATIC_INLINE void md_ad16c4t_set_chmr2(AD16C4T_TypeDef *timx, uint32_t value) -{ - WRITE_REG(timx->CHMR2, value); -} - -/** - * @brief GET Timer CHMR2 register value. - * @param timx AD16C4T instance - * @retval Timer CHMR2 register value. - */ - -__STATIC_INLINE uint32_t md_ad16c4t_get_chmr2(AD16C4T_TypeDef *timx) -{ - return (READ_REG(timx->CHMR2)); -} - -/** - * @brief Timer output compare 4 clear enable. - * @param timx AD16C4T instance - * @retval None - */ - -__STATIC_INLINE void md_ad16c4t_enable_chmr2_output_ch4oclren(AD16C4T_TypeDef *timx) -{ - SET_BIT(timx->CHMR2, AD16C4T_CHMR2_OUTPUT_CH4OCLREN_MSK); -} - -/** - * @brief Timer output compare 4 clear disable. - * @param timx AD16C4T instance - * @retval None - */ - -__STATIC_INLINE void md_ad16c4t_disable_chmr2_output_ch4oclren(AD16C4T_TypeDef *timx) -{ - CLEAR_BIT(timx->CHMR2, AD16C4T_CHMR2_OUTPUT_CH4OCLREN_MSK); -} - -/** - * @brief Indicates whether the timer output compare 4 clear is enabled. - * @param timx AD16C4T instance - * @retval State of bit (1 or 0). - */ - -__STATIC_INLINE uint32_t md_ad16c4t_is_enabled_chmr2_output_ch4oclren(AD16C4T_TypeDef *timx) -{ - return (READ_BIT(timx->CHMR2, AD16C4T_CHMR2_OUTPUT_CH4OCLREN_MSK) == (AD16C4T_CHMR2_OUTPUT_CH4OCLREN_MSK)); -} - -/** - * @brief Timer output compare 4 mode setup. - * @param timx AD16C4T instance - * @param OutputMode Output compare mode - @arg @ref MD_AD16C4T_OUTPUTMODE_DISABLE - @arg @ref MD_AD16C4T_OUTPUTMODE_HIGHONMSTCH - @arg @ref MD_AD16C4T_OUTPUTMODE_LOWONMSTCH - @arg @ref MD_AD16C4T_OUTPUTMODE_TOGGLE - @arg @ref MD_AD16C4T_OUTPUTMODE_FORCELOW - @arg @ref MD_AD16C4T_OUTPUTMODE_FORCEHIGH - @arg @ref MD_AD16C4T_OUTPUTMODE_PWMMODE1 - @arg @ref MD_AD16C4T_OUTPUTMODE_PWMMODE2 - * @retval None - */ - -__STATIC_INLINE void md_ad16c4t_set_chmr2_output_ch4mod(AD16C4T_TypeDef *timx, uint32_t OutputMode) -{ - MODIFY_REG(timx->CHMR2, AD16C4T_CHMR2_OUTPUT_CH4MOD_MSK, (OutputMode << AD16C4T_CHMR2_OUTPUT_CH4MOD_POSS)); -} - -/** - * @brief Get timer output compare 4 mode. - * @param timx AD16C4T instance - * @retval Timer output compare 4 mode. - */ - -__STATIC_INLINE uint32_t md_ad16c4t_get_chmr2_output_ch4mod(AD16C4T_TypeDef *timx) -{ - return (READ_BIT(timx->CHMR2, AD16C4T_CHMR2_OUTPUT_CH4MOD_MSK) >> AD16C4T_CHMR2_OUTPUT_CH4MOD_POSS); -} - -/** - * @brief Timer output compare 4 preload enable. - * @param timx AD16C4T instance - * @retval None - */ - -__STATIC_INLINE void md_ad16c4t_enable_chmr2_output_ch4pen(AD16C4T_TypeDef *timx) -{ - SET_BIT(timx->CHMR2, AD16C4T_CHMR2_OUTPUT_CH4PEN_MSK); -} - -/** - * @brief Timer output compare 4 preload disable. - * @param timx AD16C4T instance - * @retval None - */ - -__STATIC_INLINE void md_ad16c4t_disable_chmr2_output_ch4pen(AD16C4T_TypeDef *timx) -{ - CLEAR_BIT(timx->CHMR2, AD16C4T_CHMR2_OUTPUT_CH4PEN_MSK); -} - -/** - * @brief Indicates whether the timer output compare 4 preload is enabled. - * @param timx AD16C4T instance - * @retval State of bit (1 or 0). - */ - -__STATIC_INLINE uint32_t md_ad16c4t_is_enabled_chmr2_output_ch4pen(AD16C4T_TypeDef *timx) -{ - return (READ_BIT(timx->CHMR2, AD16C4T_CHMR2_OUTPUT_CH4PEN_MSK) == (AD16C4T_CHMR2_OUTPUT_CH4PEN_MSK)); -} - -/** - * @brief Timer output compare 4 fast enable. - * @param timx AD16C4T instance - * @retval None - */ - -__STATIC_INLINE void md_ad16c4t_enable_chmr2_output_ch4fen(AD16C4T_TypeDef *timx) -{ - SET_BIT(timx->CHMR2, AD16C4T_CHMR2_OUTPUT_CH4FEN_MSK); -} - -/** - * @brief Timer output compare 4 fast disable. - * @param timx AD16C4T instance - * @retval None - */ - -__STATIC_INLINE void md_ad16c4t_disable_chmr2_output_ch4fen(AD16C4T_TypeDef *timx) -{ - CLEAR_BIT(timx->CHMR2, AD16C4T_CHMR2_OUTPUT_CH4FEN_MSK); -} - -/** - * @brief Indicates whether the timer output compare 4 fast is enabled. - * @param timx AD16C4T instance - * @retval State of bit (1 or 0). - */ - -__STATIC_INLINE uint32_t md_ad16c4t_is_enabled_chmr2_output_ch4fen(AD16C4T_TypeDef *timx) -{ - return (READ_BIT(timx->CHMR2, AD16C4T_CHMR2_OUTPUT_CH4FEN_MSK) == (AD16C4T_CHMR2_OUTPUT_CH4FEN_MSK)); -} - -/** - * @brief Timer cpture/compare 4 selection setup. - * @param timx AD16C4T instance - * @param ChannelMode Channel mode selection - @arg @ref MD_AD16C4T_CHMODE_OUTPUT - @arg @ref MD_AD16C4T_CHMODE_INPUT_DIRECT - @arg @ref MD_AD16C4T_CHMODE_INPUT_INDIRECT - @arg @ref MD_AD16C4T_CHMODE_INPUT_TRC - * @retval None - */ - -__STATIC_INLINE void md_ad16c4t_set_chmr2_output_cc4ssel(AD16C4T_TypeDef *timx, uint32_t ChannelMode) -{ - MODIFY_REG(timx->CHMR2, AD16C4T_CHMR2_OUTPUT_CC4SSEL_MSK, (ChannelMode << AD16C4T_CHMR2_OUTPUT_CC4SSEL_POSS)); -} - -/** - * @brief Get timer cpture/compare 4 selection. - * @param timx AD16C4T instance - * @retval Timer cpture/compare 4 selection. - */ - -__STATIC_INLINE uint32_t md_ad16c4t_get_chmr2_output_cc4ssel(AD16C4T_TypeDef *timx) -{ - return (READ_BIT(timx->CHMR2, AD16C4T_CHMR2_OUTPUT_CC4SSEL_MSK) >> AD16C4T_CHMR2_OUTPUT_CC4SSEL_POSS); -} - -/** - * @brief Timer output compare 3 clear enable. - * @param timx AD16C4T instance - * @retval None - */ - -__STATIC_INLINE void md_ad16c4t_enable_chmr2_output_ch3oclren(AD16C4T_TypeDef *timx) -{ - SET_BIT(timx->CHMR2, AD16C4T_CHMR2_OUTPUT_CH3OCLREN_MSK); -} - -/** - * @brief Timer output compare 3 clear disable. - * @param timx AD16C4T instance - * @retval None - */ - -__STATIC_INLINE void md_ad16c4t_disable_chmr2_output_ch3oclren(AD16C4T_TypeDef *timx) -{ - CLEAR_BIT(timx->CHMR2, AD16C4T_CHMR2_OUTPUT_CH3OCLREN_MSK); -} - -/** - * @brief Indicates whether the timer output compare 3 clear is enabled. - * @param timx AD16C4T instance - * @retval State of bit (1 or 0). - */ - -__STATIC_INLINE uint32_t md_ad16c4t_is_enabled_chmr2_output_ch3oclren(AD16C4T_TypeDef *timx) -{ - return (READ_BIT(timx->CHMR2, AD16C4T_CHMR2_OUTPUT_CH3OCLREN_MSK) == (AD16C4T_CHMR2_OUTPUT_CH3OCLREN_MSK)); -} - -/** - * @brief Timer output compare 3 mode setup. - * @param timx AD16C4T instance - * @param OutputMode Output compare mode - @arg @ref MD_AD16C4T_OUTPUTMODE_DISABLE - @arg @ref MD_AD16C4T_OUTPUTMODE_HIGHONMSTCH - @arg @ref MD_AD16C4T_OUTPUTMODE_LOWONMSTCH - @arg @ref MD_AD16C4T_OUTPUTMODE_TOGGLE - @arg @ref MD_AD16C4T_OUTPUTMODE_FORCELOW - @arg @ref MD_AD16C4T_OUTPUTMODE_FORCEHIGH - @arg @ref MD_AD16C4T_OUTPUTMODE_PWMMODE1 - @arg @ref MD_AD16C4T_OUTPUTMODE_PWMMODE2 - * @retval None - */ - -__STATIC_INLINE void md_ad16c4t_set_chmr2_output_ch3mod(AD16C4T_TypeDef *timx, uint32_t OutputMode) -{ - MODIFY_REG(timx->CHMR2, AD16C4T_CHMR2_OUTPUT_CH3MOD_MSK, (OutputMode << AD16C4T_CHMR2_OUTPUT_CH3MOD_POSS)); -} - -/** - * @brief Get timer output compare 3 mode. - * @param timx AD16C4T instance - * @retval Timer output compare 3 mode. - */ - -__STATIC_INLINE uint32_t md_ad16c4t_get_chmr2_output_ch3mod(AD16C4T_TypeDef *timx) -{ - return (READ_BIT(timx->CHMR2, AD16C4T_CHMR2_OUTPUT_CH3MOD_MSK) >> AD16C4T_CHMR2_OUTPUT_CH3MOD_POSS); -} - -/** - * @brief Timer output compare 3 preload enable. - * @param timx AD16C4T instance - * @retval None - */ - -__STATIC_INLINE void md_ad16c4t_enable_chmr2_output_ch3pen(AD16C4T_TypeDef *timx) -{ - SET_BIT(timx->CHMR2, AD16C4T_CHMR2_OUTPUT_CH3PEN_MSK); -} - -/** - * @brief Timer output compare 3 preload disable. - * @param timx AD16C4T instance - * @retval None - */ - -__STATIC_INLINE void md_ad16c4t_disable_chmr2_output_ch3pen(AD16C4T_TypeDef *timx) -{ - CLEAR_BIT(timx->CHMR2, AD16C4T_CHMR2_OUTPUT_CH3PEN_MSK); -} - -/** - * @brief Indicates whether the timer output compare 3 preload is enabled. - * @param timx AD16C4T instance - * @retval State of bit (1 or 0). - */ - -__STATIC_INLINE uint32_t md_ad16c4t_is_enabled_chmr2_output_ch3pen(AD16C4T_TypeDef *timx) -{ - return (READ_BIT(timx->CHMR2, AD16C4T_CHMR2_OUTPUT_CH3PEN_MSK) == (AD16C4T_CHMR2_OUTPUT_CH3PEN_MSK)); -} - -/** - * @brief Timer output compare 3 fast enable. - * @param timx AD16C4T instance - * @retval None - */ - -__STATIC_INLINE void md_ad16c4t_enable_chmr2_output_ch3fen(AD16C4T_TypeDef *timx) -{ - SET_BIT(timx->CHMR2, AD16C4T_CHMR2_OUTPUT_CH3FEN_MSK); -} - -/** - * @brief Timer output compare 3 fast disable. - * @param timx AD16C4T instance - * @retval None - */ - -__STATIC_INLINE void md_ad16c4t_disable_chmr2_output_ch3fen(AD16C4T_TypeDef *timx) -{ - CLEAR_BIT(timx->CHMR2, AD16C4T_CHMR2_OUTPUT_CH3FEN_MSK); -} - -/** - * @brief Indicates whether the timer output compare 3 fast is enabled. - * @param timx AD16C4T instance - * @retval State of bit (1 or 0). - */ - -__STATIC_INLINE uint32_t md_ad16c4t_is_enabled_chmr2_output_ch3fen(AD16C4T_TypeDef *timx) -{ - return (READ_BIT(timx->CHMR2, AD16C4T_CHMR2_OUTPUT_CH3FEN_MSK) == (AD16C4T_CHMR2_OUTPUT_CH3FEN_MSK)); -} - -/** - * @brief Timer cpture/compare 3 selection setup. - * @param timx AD16C4T instance - * @param ChannelMode Channel mode selection - @arg @ref MD_AD16C4T_CHMODE_OUTPUT - @arg @ref MD_AD16C4T_CHMODE_INPUT_DIRECT - @arg @ref MD_AD16C4T_CHMODE_INPUT_INDIRECT - @arg @ref MD_AD16C4T_CHMODE_INPUT_TRC - * @retval None - */ - -__STATIC_INLINE void md_ad16c4t_set_chmr2_output_cc3ssel(AD16C4T_TypeDef *timx, uint32_t ChannelMode) -{ - MODIFY_REG(timx->CHMR2, AD16C4T_CHMR2_OUTPUT_CC3SSEL_MSK, (ChannelMode << AD16C4T_CHMR2_OUTPUT_CC3SSEL_POSS)); -} - -/** - * @brief Get timer cpture/compare 3 selection. - * @param timx AD16C4T instance - * @retval Timer cpture/compare 3 selection. - */ - -__STATIC_INLINE uint32_t md_ad16c4t_get_chmr2_output_cc3ssel(AD16C4T_TypeDef *timx) -{ - return (READ_BIT(timx->CHMR2, AD16C4T_CHMR2_OUTPUT_CC3SSEL_MSK) >> AD16C4T_CHMR2_OUTPUT_CC3SSEL_POSS); -} - -/** - * @brief Timer input capture 4 filter setup. - * @param timx AD16C4T instance - * @param InputFliter Input capture filter - @arg @ref MD_AD16C4T_INPUTFILTER_FDIV1 - @arg @ref MD_AD16C4T_INPUTFILTER_FDIV1N2 - @arg @ref MD_AD16C4T_INPUTFILTER_FDIV1N4 - @arg @ref MD_AD16C4T_INPUTFILTER_FDIV1N8 - @arg @ref MD_AD16C4T_INPUTFILTER_FDIV2N6 - @arg @ref MD_AD16C4T_INPUTFILTER_FDIV2N8 - @arg @ref MD_AD16C4T_INPUTFILTER_FDIV4N6 - @arg @ref MD_AD16C4T_INPUTFILTER_FDIV4N8 - @arg @ref MD_AD16C4T_INPUTFILTER_FDIV8N6 - @arg @ref MD_AD16C4T_INPUTFILTER_FDIV8N8 - @arg @ref MD_AD16C4T_INPUTFILTER_FDIV16N5 - @arg @ref MD_AD16C4T_INPUTFILTER_FDIV16N6 - @arg @ref MD_AD16C4T_INPUTFILTER_FDIV16N8 - @arg @ref MD_AD16C4T_INPUTFILTER_FDIV32N5 - @arg @ref MD_AD16C4T_INPUTFILTER_FDIV32N6 - @arg @ref MD_AD16C4T_INPUTFILTER_FDIV32N8 - * @retval None - */ - -__STATIC_INLINE void md_ad16c4t_set_chmr2_input_i4flt(AD16C4T_TypeDef *timx, uint32_t InputFliter) -{ - MODIFY_REG(timx->CHMR2, AD16C4T_CHMR2_INPUT_I4FLT_MSK, (InputFliter << AD16C4T_CHMR2_INPUT_I4FLT_POSS)); -} - -/** - * @brief Get timer input capture 4 filter. - * @param timx AD16C4T instance - * @retval Timer input capture 4 filter. - */ - -__STATIC_INLINE uint32_t md_ad16c4t_get_chmr2_input_i4flt(AD16C4T_TypeDef *timx) -{ - return (READ_BIT(timx->CHMR2, AD16C4T_CHMR2_INPUT_I4FLT_MSK) >> AD16C4T_CHMR2_INPUT_I4FLT_POSS); -} - -/** - * @brief Timer input capture 4 prescaler setup. - * @param timx AD16C4T instance - * @param InputPrescale Input capture prescaler - @arg @ref MD_AD16C4T_INPUTPRESCALE_DIV1 - @arg @ref MD_AD16C4T_INPUTPRESCALE_DIV2 - @arg @ref MD_AD16C4T_INPUTPRESCALE_DIV4 - @arg @ref MD_AD16C4T_INPUTPRESCALE_DIV8 - * @retval None - */ - -__STATIC_INLINE void md_ad16c4t_set_chmr2_input_i4pres(AD16C4T_TypeDef *timx, uint32_t InputPrescale) -{ - MODIFY_REG(timx->CHMR2, AD16C4T_CHMR2_INPUT_I4PRES_MSK, (InputPrescale << AD16C4T_CHMR2_INPUT_I4PRES_POSS)); -} - -/** - * @brief Get timer input capture 4 prescaler. - * @param timx AD16C4T instance - * @retval Timer input capture 4 prescaler. - */ - -__STATIC_INLINE uint32_t md_ad16c4t_get_chmr2_input_i4pres(AD16C4T_TypeDef *timx) -{ - return (READ_BIT(timx->CHMR2, AD16C4T_CHMR2_INPUT_I4PRES_MSK) >> AD16C4T_CHMR2_INPUT_I4PRES_POSS); -} - -/** - * @brief Timer cpture/compare 4 selection setup. - * @param timx AD16C4T instance - * @param ChannelMode Channel mode selection - @arg @ref MD_AD16C4T_CHMODE_OUTPUT - @arg @ref MD_AD16C4T_CHMODE_INPUT_DIRECT - @arg @ref MD_AD16C4T_CHMODE_INPUT_INDIRECT - @arg @ref MD_AD16C4T_CHMODE_INPUT_TRC - * @retval None - */ - -__STATIC_INLINE void md_ad16c4t_set_chmr2_input_cc4ssel(AD16C4T_TypeDef *timx, uint32_t ChannelMode) -{ - MODIFY_REG(timx->CHMR2, AD16C4T_CHMR2_INPUT_CC4SSEL_MSK, (ChannelMode << AD16C4T_CHMR2_INPUT_CC4SSEL_POSS)); -} - -/** - * @brief Get timer cpture/compare 4 selection. - * @param timx AD16C4T instance - * @retval Timer cpture/compare 4 selection. - */ - -__STATIC_INLINE uint32_t md_ad16c4t_get_chmr2_input_cc4ssel(AD16C4T_TypeDef *timx) -{ - return (READ_BIT(timx->CHMR2, AD16C4T_CHMR2_INPUT_CC4SSEL_MSK) >> AD16C4T_CHMR2_INPUT_CC4SSEL_POSS); -} - -/** - * @brief Timer input capture 3 filter setup. - * @param timx AD16C4T instance - * @param InputFliter Input capture filter - @arg @ref MD_AD16C4T_INPUTFILTER_FDIV1 - @arg @ref MD_AD16C4T_INPUTFILTER_FDIV1N2 - @arg @ref MD_AD16C4T_INPUTFILTER_FDIV1N4 - @arg @ref MD_AD16C4T_INPUTFILTER_FDIV1N8 - @arg @ref MD_AD16C4T_INPUTFILTER_FDIV2N6 - @arg @ref MD_AD16C4T_INPUTFILTER_FDIV2N8 - @arg @ref MD_AD16C4T_INPUTFILTER_FDIV4N6 - @arg @ref MD_AD16C4T_INPUTFILTER_FDIV4N8 - @arg @ref MD_AD16C4T_INPUTFILTER_FDIV8N6 - @arg @ref MD_AD16C4T_INPUTFILTER_FDIV8N8 - @arg @ref MD_AD16C4T_INPUTFILTER_FDIV16N5 - @arg @ref MD_AD16C4T_INPUTFILTER_FDIV16N6 - @arg @ref MD_AD16C4T_INPUTFILTER_FDIV16N8 - @arg @ref MD_AD16C4T_INPUTFILTER_FDIV32N5 - @arg @ref MD_AD16C4T_INPUTFILTER_FDIV32N6 - @arg @ref MD_AD16C4T_INPUTFILTER_FDIV32N8 - * @retval None - */ - -__STATIC_INLINE void md_ad16c4t_set_chmr2_input_i3flt(AD16C4T_TypeDef *timx, uint32_t InputFliter) -{ - MODIFY_REG(timx->CHMR2, AD16C4T_CHMR2_INPUT_I3FLT_MSK, (InputFliter << AD16C4T_CHMR2_INPUT_I3FLT_POSS)); -} - -/** - * @brief Get timer input capture 3 filter. - * @param timx AD16C4T instance - * @retval Timer input capture 3 filter. - */ - -__STATIC_INLINE uint32_t md_ad16c4t_get_chmr2_input_i3flt(AD16C4T_TypeDef *timx) -{ - return (READ_BIT(timx->CHMR2, AD16C4T_CHMR2_INPUT_I3FLT_MSK) >> AD16C4T_CHMR2_INPUT_I3FLT_POSS); -} - -/** - * @brief Timer input capture 3 prescaler setup. - * @param timx AD16C4T instance - * @param InputPrescale Input capture prescaler - @arg @ref MD_AD16C4T_INPUTPRESCALE_DIV1 - @arg @ref MD_AD16C4T_INPUTPRESCALE_DIV2 - @arg @ref MD_AD16C4T_INPUTPRESCALE_DIV4 - @arg @ref MD_AD16C4T_INPUTPRESCALE_DIV8 - * @retval None - */ - -__STATIC_INLINE void md_ad16c4t_set_chmr2_input_i3pres(AD16C4T_TypeDef *timx, uint32_t InputPrescale) -{ - MODIFY_REG(timx->CHMR2, AD16C4T_CHMR2_INPUT_I3PRES_MSK, (InputPrescale << AD16C4T_CHMR2_INPUT_I3PRES_POSS)); -} - -/** - * @brief Get timer input capture 3 prescaler. - * @param timx AD16C4T instance - * @retval Timer input capture 3 prescaler. - */ - -__STATIC_INLINE uint32_t md_ad16c4t_get_chmr2_input_i3pres(AD16C4T_TypeDef *timx) -{ - return (READ_BIT(timx->CHMR2, AD16C4T_CHMR2_INPUT_I3PRES_MSK) >> AD16C4T_CHMR2_INPUT_I3PRES_POSS); -} - -/** - * @brief Timer cpture/compare 3 selection setup. - * @param timx AD16C4T instance - * @param ChannelMode Channel mode selection - @arg @ref MD_AD16C4T_CHMODE_OUTPUT - @arg @ref MD_AD16C4T_CHMODE_INPUT_DIRECT - @arg @ref MD_AD16C4T_CHMODE_INPUT_INDIRECT - @arg @ref MD_AD16C4T_CHMODE_INPUT_TRC - * @retval None - */ - -__STATIC_INLINE void md_ad16c4t_set_chmr2_input_cc3ssel(AD16C4T_TypeDef *timx, uint32_t ChannelMode) -{ - MODIFY_REG(timx->CHMR2, AD16C4T_CHMR2_INPUT_CC3SSEL_MSK, (ChannelMode << AD16C4T_CHMR2_INPUT_CC3SSEL_POSS)); -} - -/** - * @brief Get timer cpture/compare 3 selection. - * @param timx AD16C4T instance - * @retval Timer cpture/compare 3 selection. - */ - -__STATIC_INLINE uint32_t md_ad16c4t_get_chmr2_input_cc3ssel(AD16C4T_TypeDef *timx) -{ - return (READ_BIT(timx->CHMR2, AD16C4T_CHMR2_INPUT_CC3SSEL_MSK) >> AD16C4T_CHMR2_INPUT_CC3SSEL_POSS); -} - -/** - * @brief Timer CCEP setup. - * @param timx AD16C4T instance - * @param value (CC4NPOL | CC4POL | CC4EN | CC3NPOL | CC3NEN | CC3POL | CC3EN | CC2NPOL | - * CC2NEN | CC2POL | CC2EN | CC1NPOL | CC1NEN | CC1POL | CC1EN ) - * @retval None - */ - -__STATIC_INLINE void md_ad16c4t_set_ccep(AD16C4T_TypeDef *timx, uint32_t value) -{ - WRITE_REG(timx->CCEP, value); -} - -/** - * @brief GET Timer CCEP register value. - * @param timx AD16C4T instance - * @retval Timer CCEP register value. - */ - -__STATIC_INLINE uint32_t md_ad16c4t_get_ccep(AD16C4T_TypeDef *timx) -{ - return (READ_REG(timx->CCEP)); -} - -/** - * @brief Timer capture/compare 4 complementary output polarity setup. - * @param timx AD16C4T instance - * @param OutputPolarity Output polarity - @arg @ref MD_AD16C4T_OUTPUTPOLARITY_HIGH - @arg @ref MD_AD16C4T_OUTPUTPOLARITY_LOW - * @retval None - */ - -__STATIC_INLINE void md_ad16c4t_set_ccep_cc4npol(AD16C4T_TypeDef *timx, uint32_t OutputPolarity) -{ - MODIFY_REG(timx->CCEP, AD16C4T_CCEP_CC4NPOL_MSK, (OutputPolarity << AD16C4T_CCEP_CC4NPOL_POS)); -} - -/** - * @brief Get timer capture/compare 4 complementary output polarity. - * @param timx AD16C4T instance - * @retval Timer capture/compare 4 complementary output polarity. - */ - -__STATIC_INLINE uint32_t md_ad16c4t_get_ccep_cc4npol(AD16C4T_TypeDef *timx) -{ - return (READ_BIT(timx->CCEP, AD16C4T_CCEP_CC4NPOL_MSK) >> AD16C4T_CCEP_CC4NPOL_POS); -} - -/** - * @brief Timer capture/compare 4 output polarity setup. - * @param timx AD16C4T instance - * @param OutputPolarity Output polarity - @arg @ref MD_AD16C4T_OUTPUTPOLARITY_HIGH - @arg @ref MD_AD16C4T_OUTPUTPOLARITY_LOW - * @retval None - */ - -__STATIC_INLINE void md_ad16c4t_set_ccep_cc4pol(AD16C4T_TypeDef *timx, uint32_t OutputPolarity) -{ - MODIFY_REG(timx->CCEP, AD16C4T_CCEP_CC4POL_MSK, (OutputPolarity << AD16C4T_CCEP_CC4POL_POS)); -} - -/** - * @brief Get timer capture/compare 4 output polarity. - * @param timx AD16C4T instance - * @retval Timer capture/compare 4 output polarity. - */ - -__STATIC_INLINE uint32_t md_ad16c4t_get_ccep_cc4pol(AD16C4T_TypeDef *timx) -{ - return (READ_BIT(timx->CCEP, AD16C4T_CCEP_CC4POL_MSK) >> AD16C4T_CCEP_CC4POL_POS); -} - -/** - * @brief Timer Capture/Compare 4 output enable. - * @param timx AD16C4T instance - * @retval None - */ - -__STATIC_INLINE void md_ad16c4t_enable_ccep_cc4en(AD16C4T_TypeDef *timx) -{ - SET_BIT(timx->CCEP, AD16C4T_CCEP_CC4EN_MSK); -} - -/** - * @brief Timer Capture/Compare 4 output disable. - * @param timx AD16C4T instance - * @retval None - */ - -__STATIC_INLINE void md_ad16c4t_disable_ccep_cc4en(AD16C4T_TypeDef *timx) -{ - CLEAR_BIT(timx->CCEP, AD16C4T_CCEP_CC4EN_MSK); -} - -/** - * @brief Indicates whether the timer Capture/Compare 4 output is enabled. - * @param timx AD16C4T instance - * @retval State of bit (1 or 0). - */ - -__STATIC_INLINE uint32_t md_ad16c4t_is_enabled_ccep_cc4en(AD16C4T_TypeDef *timx) -{ - return (READ_BIT(timx->CCEP, AD16C4T_CCEP_CC4EN_MSK) == (AD16C4T_CCEP_CC4EN_MSK)); -} - -/** - * @brief Timer capture/compare 3 complementary output polarity setup. - * @param timx AD16C4T instance - * @param OutputPolarity Output polarity - @arg @ref MD_AD16C4T_OUTPUTPOLARITY_HIGH - @arg @ref MD_AD16C4T_OUTPUTPOLARITY_LOW - * @retval None - */ - -__STATIC_INLINE void md_ad16c4t_set_ccep_cc3npol(AD16C4T_TypeDef *timx, uint32_t OutputPolarity) -{ - MODIFY_REG(timx->CCEP, AD16C4T_CCEP_CC3NPOL_MSK, (OutputPolarity << AD16C4T_CCEP_CC3NPOL_POS)); -} - -/** - * @brief Get timer capture/compare 3 complementary output polarity. - * @param timx AD16C4T instance - * @retval Timer capture/compare 3 complementary output polarity. - */ - -__STATIC_INLINE uint32_t md_ad16c4t_get_ccep_cc3npol(AD16C4T_TypeDef *timx) -{ - return (READ_BIT(timx->CCEP, AD16C4T_CCEP_CC3NPOL_MSK) >> AD16C4T_CCEP_CC3NPOL_POS); -} - -/** - * @brief Timer Capture/Compare 3 complementary output enable. - * @param timx AD16C4T instance - * @retval None - */ - -__STATIC_INLINE void md_ad16c4t_enable_ccep_cc3nen(AD16C4T_TypeDef *timx) -{ - SET_BIT(timx->CCEP, AD16C4T_CCEP_CC3NEN_MSK); -} - -/** - * @brief Timer Capture/Compare 3 complementary output disable. - * @param timx AD16C4T instance - * @retval None - */ - -__STATIC_INLINE void md_ad16c4t_disable_ccep_cc3nen(AD16C4T_TypeDef *timx) -{ - CLEAR_BIT(timx->CCEP, AD16C4T_CCEP_CC3NEN_MSK); -} - -/** - * @brief Indicates whether the timer Capture/Compare 3 complementary output is enabled. - * @param timx AD16C4T instance - * @retval State of bit (1 or 0). - */ - -__STATIC_INLINE uint32_t md_ad16c4t_is_enabled_ccep_cc3nen(AD16C4T_TypeDef *timx) -{ - return (READ_BIT(timx->CCEP, AD16C4T_CCEP_CC3NEN_MSK) == (AD16C4T_CCEP_CC3NEN_MSK)); -} - -/** - * @brief Timer capture/compare 3 output polarity setup. - * @param timx AD16C4T instance - * @param OutputPolarity Output polarity - @arg @ref MD_AD16C4T_OUTPUTPOLARITY_HIGH - @arg @ref MD_AD16C4T_OUTPUTPOLARITY_LOW - * @retval None - */ - -__STATIC_INLINE void md_ad16c4t_set_ccep_cc3pol(AD16C4T_TypeDef *timx, uint32_t OutputPolarity) -{ - MODIFY_REG(timx->CCEP, AD16C4T_CCEP_CC3POL_MSK, (OutputPolarity << AD16C4T_CCEP_CC3POL_POS)); -} - -/** - * @brief Get timer capture/compare 3 output polarity. - * @param timx AD16C4T instance - * @retval Timer capture/compare 3 output polarity. - */ - -__STATIC_INLINE uint32_t md_ad16c4t_get_ccep_cc3pol(AD16C4T_TypeDef *timx) -{ - return (READ_BIT(timx->CCEP, AD16C4T_CCEP_CC3POL_MSK) >> AD16C4T_CCEP_CC3POL_POS); -} - -/** - * @brief Timer Capture/Compare 3 output enable. - * @param timx AD16C4T instance - * @retval None - */ - -__STATIC_INLINE void md_ad16c4t_enable_ccep_cc3en(AD16C4T_TypeDef *timx) -{ - SET_BIT(timx->CCEP, AD16C4T_CCEP_CC3EN_MSK); -} - -/** - * @brief Timer Capture/Compare 3 output disable. - * @param timx AD16C4T instance - * @retval None - */ - -__STATIC_INLINE void md_ad16c4t_disable_ccep_cc3en(AD16C4T_TypeDef *timx) -{ - CLEAR_BIT(timx->CCEP, AD16C4T_CCEP_CC3EN_MSK); -} - -/** - * @brief Indicates whether the timer Capture/Compare 3 output is enabled. - * @param timx AD16C4T instance - * @retval State of bit (1 or 0). - */ - -__STATIC_INLINE uint32_t md_ad16c4t_is_enabled_ccep_cc3en(AD16C4T_TypeDef *timx) -{ - return (READ_BIT(timx->CCEP, AD16C4T_CCEP_CC3EN_MSK) == (AD16C4T_CCEP_CC3EN_MSK)); -} - -/** - * @brief Timer capture/compare 2 complementary output polarity setup. - * @param timx AD16C4T instance - * @param OutputPolarity Output polarity - @arg @ref MD_AD16C4T_OUTPUTPOLARITY_HIGH - @arg @ref MD_AD16C4T_OUTPUTPOLARITY_LOW - * @retval None - */ - -__STATIC_INLINE void md_ad16c4t_set_ccep_cc2npol(AD16C4T_TypeDef *timx, uint32_t OutputPolarity) -{ - MODIFY_REG(timx->CCEP, AD16C4T_CCEP_CC2NPOL_MSK, (OutputPolarity << AD16C4T_CCEP_CC2NPOL_POS)); -} - -/** - * @brief Get timer capture/compare 2 complementary output polarity. - * @param timx AD16C4T instance - * @retval Timer capture/compare 2 complementary output polarity. - */ - -__STATIC_INLINE uint32_t md_ad16c4t_get_ccep_cc2npol(AD16C4T_TypeDef *timx) -{ - return (READ_BIT(timx->CCEP, AD16C4T_CCEP_CC2NPOL_MSK) >> AD16C4T_CCEP_CC2NPOL_POS); -} - -/** - * @brief Timer Capture/Compare 2 complementary output enable. - * @param timx AD16C4T instance - * @retval None - */ - -__STATIC_INLINE void md_ad16c4t_enable_ccep_cc2nen(AD16C4T_TypeDef *timx) -{ - SET_BIT(timx->CCEP, AD16C4T_CCEP_CC2NEN_MSK); -} - -/** - * @brief Timer Capture/Compare 2 complementary output disable. - * @param timx AD16C4T instance - * @retval None - */ - -__STATIC_INLINE void md_ad16c4t_disable_ccep_cc2nen(AD16C4T_TypeDef *timx) -{ - CLEAR_BIT(timx->CCEP, AD16C4T_CCEP_CC2NEN_MSK); -} - -/** - * @brief Indicates whether the timer Capture/Compare 2 complementary output is enabled. - * @param timx AD16C4T instance - * @retval State of bit (1 or 0). - */ - -__STATIC_INLINE uint32_t md_ad16c4t_is_enabled_ccep_cc2nen(AD16C4T_TypeDef *timx) -{ - return (READ_BIT(timx->CCEP, AD16C4T_CCEP_CC2NEN_MSK) == (AD16C4T_CCEP_CC2NEN_MSK)); -} - -/** - * @brief Timer capture/compare 2 output polarity setup. - * @param timx AD16C4T instance - * @param OutputPolarity Output polarity - @arg @ref MD_AD16C4T_OUTPUTPOLARITY_HIGH - @arg @ref MD_AD16C4T_OUTPUTPOLARITY_LOW - * @retval None - */ - -__STATIC_INLINE void md_ad16c4t_set_ccep_cc2pol(AD16C4T_TypeDef *timx, uint32_t OutputPolarity) -{ - MODIFY_REG(timx->CCEP, AD16C4T_CCEP_CC2POL_MSK, (OutputPolarity << AD16C4T_CCEP_CC2POL_POS)); -} - -/** - * @brief Get timer capture/compare 2 output polarity. - * @param timx AD16C4T instance - * @retval Timer capture/compare 2 output polarity. - */ - -__STATIC_INLINE uint32_t md_ad16c4t_get_ccep_cc2pol(AD16C4T_TypeDef *timx) -{ - return (READ_BIT(timx->CCEP, AD16C4T_CCEP_CC2POL_MSK) >> AD16C4T_CCEP_CC2POL_POS); -} - -/** - * @brief Timer Capture/Compare 2 output enable. - * @param timx AD16C4T instance - * @retval None - */ - -__STATIC_INLINE void md_ad16c4t_enable_ccep_cc2en(AD16C4T_TypeDef *timx) -{ - SET_BIT(timx->CCEP, AD16C4T_CCEP_CC2EN_MSK); -} - -/** - * @brief Timer Capture/Compare 2 output disable. - * @param timx AD16C4T instance - * @retval None - */ - -__STATIC_INLINE void md_ad16c4t_disable_ccep_cc2en(AD16C4T_TypeDef *timx) -{ - CLEAR_BIT(timx->CCEP, AD16C4T_CCEP_CC2EN_MSK); -} - -/** - * @brief Indicates whether the timer Capture/Compare 2 output is enabled. - * @param timx AD16C4T instance - * @retval State of bit (1 or 0). - */ - -__STATIC_INLINE uint32_t md_ad16c4t_is_enabled_ccep_cc2en(AD16C4T_TypeDef *timx) -{ - return (READ_BIT(timx->CCEP, AD16C4T_CCEP_CC2EN_MSK) == (AD16C4T_CCEP_CC2EN_MSK)); -} - -/** - * @brief Timer capture/compare 1 complementary output polarity setup. - * @param timx AD16C4T instance - * @param OutputPolarity Output polarity - @arg @ref MD_AD16C4T_OUTPUTPOLARITY_HIGH - @arg @ref MD_AD16C4T_OUTPUTPOLARITY_LOW - * @retval None - */ - -__STATIC_INLINE void md_ad16c4t_set_ccep_cc1npol(AD16C4T_TypeDef *timx, uint32_t OutputPolarity) -{ - MODIFY_REG(timx->CCEP, AD16C4T_CCEP_CC1NPOL_MSK, (OutputPolarity << AD16C4T_CCEP_CC1NPOL_POS)); -} - -/** - * @brief Get timer capture/compare 1 complementary output polarity. - * @param timx AD16C4T instance - * @retval Timer capture/compare 1 complementary output polarity. - */ - -__STATIC_INLINE uint32_t md_ad16c4t_get_ccep_cc1npol(AD16C4T_TypeDef *timx) -{ - return (READ_BIT(timx->CCEP, AD16C4T_CCEP_CC1NPOL_MSK) >> AD16C4T_CCEP_CC1NPOL_POS); -} - -/** - * @brief Timer Capture/Compare 1 complementary output enable. - * @param timx AD16C4T instance - * @retval None - */ - -__STATIC_INLINE void md_ad16c4t_enable_ccep_cc1nen(AD16C4T_TypeDef *timx) -{ - SET_BIT(timx->CCEP, AD16C4T_CCEP_CC1NEN_MSK); -} - -/** - * @brief Timer Capture/Compare 1 complementary output disable. - * @param timx AD16C4T instance - * @retval None - */ - -__STATIC_INLINE void md_ad16c4t_disable_ccep_cc1nen(AD16C4T_TypeDef *timx) -{ - CLEAR_BIT(timx->CCEP, AD16C4T_CCEP_CC1NEN_MSK); -} - -/** - * @brief Indicates whether the timer Capture/Compare 1 complementary output is enabled. - * @param timx AD16C4T instance - * @retval State of bit (1 or 0). - */ - -__STATIC_INLINE uint32_t md_ad16c4t_is_enabled_ccep_cc1nen(AD16C4T_TypeDef *timx) -{ - return (READ_BIT(timx->CCEP, AD16C4T_CCEP_CC1NEN_MSK) == (AD16C4T_CCEP_CC1NEN_MSK)); -} - -/** - * @brief Timer capture/compare 1 output polarity setup. - * @param timx AD16C4T instance - * @param OutputPolarity Output polarity - @arg @ref MD_AD16C4T_OUTPUTPOLARITY_HIGH - @arg @ref MD_AD16C4T_OUTPUTPOLARITY_LOW - * @retval None - */ - -__STATIC_INLINE void md_ad16c4t_set_ccep_cc1pol(AD16C4T_TypeDef *timx, uint32_t OutputPolarity) -{ - MODIFY_REG(timx->CCEP, AD16C4T_CCEP_CC1POL_MSK, (OutputPolarity << AD16C4T_CCEP_CC1POL_POS)); -} - -/** - * @brief Get timer capture/compare 1 output polarity. - * @param timx AD16C4T instance - * @retval Timer capture/compare 1 output polarity. - */ - -__STATIC_INLINE uint32_t md_ad16c4t_get_ccep_cc1pol(AD16C4T_TypeDef *timx) -{ - return (READ_BIT(timx->CCEP, AD16C4T_CCEP_CC1POL_MSK) >> AD16C4T_CCEP_CC1POL_POS); -} - -/** - * @brief Timer Capture/Compare 1 output enable. - * @param timx AD16C4T instance - * @retval None - */ - -__STATIC_INLINE void md_ad16c4t_enable_ccep_cc1en(AD16C4T_TypeDef *timx) -{ - SET_BIT(timx->CCEP, AD16C4T_CCEP_CC1EN_MSK); -} - -/** - * @brief Timer Capture/Compare 1 output disable. - * @param timx AD16C4T instance - * @retval None - */ - -__STATIC_INLINE void md_ad16c4t_disable_ccep_cc1en(AD16C4T_TypeDef *timx) -{ - CLEAR_BIT(timx->CCEP, AD16C4T_CCEP_CC1EN_MSK); -} - -/** - * @brief Indicates whether the timer Capture/Compare 1 output is enabled. - * @param timx AD16C4T instance - * @retval State of bit (1 or 0). - */ - -__STATIC_INLINE uint32_t md_ad16c4t_is_enabled_ccep_cc1en(AD16C4T_TypeDef *timx) -{ - return (READ_BIT(timx->CCEP, AD16C4T_CCEP_CC1EN_MSK) == (AD16C4T_CCEP_CC1EN_MSK)); -} - -/** - * @brief Timer COUNT setup. - * @param timx AD16C4T instance - * @param value COUNT - * @retval None - */ - -__STATIC_INLINE void md_ad16c4t_set_count(AD16C4T_TypeDef *timx, uint32_t value) -{ - WRITE_REG(timx->COUNT, value); -} - -/** - * @brief GET Timer COUNT register value. - * @param timx AD16C4T instance - * @retval Timer COUNT register value. - */ - -__STATIC_INLINE uint32_t md_ad16c4t_get_count(AD16C4T_TypeDef *timx) -{ - return (READ_REG(timx->COUNT)); -} - -/** - * @brief Timer counter value setup. - * @param timx AD16C4T instance - * @param counter Counter value (between Min_Data=0 and Max_Data=0xFFFF) - * @retval None - */ - -__STATIC_INLINE void md_ad16c4t_set_count_cntv(AD16C4T_TypeDef *timx, uint32_t counter) -{ - MODIFY_REG(timx->COUNT, AD16C4T_COUNT_CNTV_MSK, counter); -} - -/** - * @brief Get timer counter value. - * @param timx AD16C4T instance - * @retval Timer counter value. - */ - -__STATIC_INLINE uint32_t md_ad16c4t_get_cnt_cntv(AD16C4T_TypeDef *timx) -{ - return (READ_BIT(timx->COUNT, AD16C4T_COUNT_CNTV_MSK) >> AD16C4T_COUNT_CNTV_POSS); -} - -/** - * @brief Timer PRES setup. - * @param timx AD16C4T instance - * @param value PRES - * @retval None - */ - -__STATIC_INLINE void md_ad16c4t_set_pres(AD16C4T_TypeDef *timx, uint32_t value) -{ - WRITE_REG(timx->PRES, value); -} - -/** - * @brief GET Timer PRES register value. - * @param timx AD16C4T instance - * @retval Timer PRES register value. - */ - -__STATIC_INLINE uint32_t md_ad16c4t_get_pres(AD16C4T_TypeDef *timx) -{ - return (READ_REG(timx->PRES)); -} - -/** - * @brief Timer prescaler value setup. - * @param timx AD16C4T instance - * @param prescaler Prescaler value (between Min_Data=0 and Max_Data=0xFFFF) - * @retval None - */ - -__STATIC_INLINE void md_ad16c4t_set_pres_pscv(AD16C4T_TypeDef *timx, uint32_t prescaler) -{ - MODIFY_REG(timx->PRES, AD16C4T_PRES_PSCV_MSK, prescaler); -} - -/** - * @brief Get timer prescaler value. - * @param timx AD16C4T instance - * @retval Timer prescaler value. - */ - -__STATIC_INLINE uint32_t md_ad16c4t_get_pres_pscv(AD16C4T_TypeDef *timx) -{ - return (READ_BIT(timx->PRES, AD16C4T_PRES_PSCV_MSK) >> AD16C4T_PRES_PSCV_POSS); -} - -/** - * @brief Timer AR setup. - * @param timx AD16C4T instance - * @param value AR - * @retval None - */ - -__STATIC_INLINE void md_ad16c4t_set_ar(AD16C4T_TypeDef *timx, uint32_t value) -{ - WRITE_REG(timx->AR, value); -} - -/** - * @brief GET Timer AR register value. - * @param timx AD16C4T instance - * @retval Timer AR register value. - */ - -__STATIC_INLINE uint32_t md_ad16c4t_get_ar(AD16C4T_TypeDef *timx) -{ - return (READ_REG(timx->AR)); -} - -/** - * @brief Timer auto-reload value setup. - * @param timx AD16C4T instance - * @param reload Auto-reload value (between Min_Data=0 and Max_Data=0xFFFF) - * @retval None - */ - -__STATIC_INLINE void md_ad16c4t_set_ar_arv(AD16C4T_TypeDef *timx, uint32_t reload) -{ - MODIFY_REG(timx->AR, AD16C4T_AR_ARV_MSK, reload); -} - -/** - * @brief Get timer auto-reload value. - * @param timx AD16C4T instance - * @retval Timer auto-reload value. - */ - -__STATIC_INLINE uint32_t md_ad16c4t_get_ar_arv(AD16C4T_TypeDef *timx) -{ - return (READ_BIT(timx->AR, AD16C4T_AR_ARV_MSK) >> AD16C4T_AR_ARV_POSS); -} - -/** - * @brief Timer REPAR setup. - * @param timx AD16C4T instance - * @param value REPAR - * @retval None - */ - -__STATIC_INLINE void md_ad16c4t_set_rcr(AD16C4T_TypeDef *timx, uint32_t value) -{ - WRITE_REG(timx->REPAR, value); -} - -/** - * @brief GET Timer REPAR register value. - * @param timx AD16C4T instance - * @retval Timer REPAR register value. - */ - -__STATIC_INLINE uint32_t md_ad16c4t_get_repar(AD16C4T_TypeDef *timx) -{ - return (READ_REG(timx->REPAR)); -} - -/** - * @brief Timer repetition counter value setup. - * @param timx AD16C4T instance - * @param repetition Repetition counter value (between Min_Data=0 and Max_Data=0xFF) - * @retval None - */ - -__STATIC_INLINE void md_ad16c4t_set_repar_repv(AD16C4T_TypeDef *timx, uint32_t repetition) -{ - MODIFY_REG(timx->REPAR, AD16C4T_REPAR_REPV_MSK, repetition); -} - -/** - * @brief Get timer repetition counter value. - * @param timx AD16C4T instance - * @retval Timer repetition counter value. - */ - -__STATIC_INLINE uint32_t md_ad16c4t_get_repar_repv(AD16C4T_TypeDef *timx) -{ - return (READ_BIT(timx->REPAR, AD16C4T_REPAR_REPV_MSK) >> AD16C4T_REPAR_REPV_POSS); -} - -/** - * @brief Timer CCVAL1 setup. - * @param timx AD16C4T instance - * @param value CCVAL1 - * @retval None - */ - -__STATIC_INLINE void md_ad16c4t_set_ccval1(AD16C4T_TypeDef *timx, uint32_t value) -{ - WRITE_REG(timx->CCVAL1, value); -} - -/** - * @brief GET Timer CCVAL1 register value. - * @param timx AD16C4T instance - * @retval Timer CCVAL1 register value. - */ - -__STATIC_INLINE uint32_t md_ad16c4t_get_ccval1(AD16C4T_TypeDef *timx) -{ - return (READ_REG(timx->CCVAL1)); -} - -/** - * @brief Timer capture/compare value 1 setup. - * @param timx AD16C4T instance - * @param CapCompValue Capture/Compare value 1 (between Min_Data=0 and Max_Data=0xFFFF) - * @retval None - */ - -__STATIC_INLINE void md_ad16c4t_set_ccval1_ccrv1(AD16C4T_TypeDef *timx, uint32_t CapCompValue) -{ - MODIFY_REG(timx->CCVAL1, AD16C4T_CCVAL1_CCRV1_MSK, CapCompValue); -} - -/** - * @brief Get timer capture/compare value 1. - * @param timx AD16C4T instance - * @retval Timer capture/compare value 1. - */ - -__STATIC_INLINE uint32_t md_ad16c4t_get_ccval1_ccrv1(AD16C4T_TypeDef *timx) -{ - return (READ_BIT(timx->CCVAL1, AD16C4T_CCVAL1_CCRV1_MSK) >> AD16C4T_CCVAL1_CCRV1_POSS); -} - -/** - * @brief Timer CCVAL2 setup. - * @param timx AD16C4T instance - * @param value CCVAL2 - * @retval None - */ - -__STATIC_INLINE void md_ad16c4t_set_ccval2(AD16C4T_TypeDef *timx, uint32_t value) -{ - WRITE_REG(timx->CCVAL2, value); -} - -/** - * @brief GET Timer CCVAL2 register value. - * @param timx AD16C4T instance - * @retval Timer CCVAL2 register value. - */ - -__STATIC_INLINE uint32_t md_ad16c4t_get_ccval2(AD16C4T_TypeDef *timx) -{ - return (READ_REG(timx->CCVAL2)); -} - -/** - * @brief Timer capture/compare value 2 setup. - * @param timx AD16C4T instance - * @param CapCompValue Capture/Compare value 2 (between Min_Data=0 and Max_Data=0xFFFF) - * @retval None - */ - -__STATIC_INLINE void md_ad16c4t_set_ccval2_ccrv2(AD16C4T_TypeDef *timx, uint32_t CapCompValue) -{ - MODIFY_REG(timx->CCVAL2, AD16C4T_CCVAL2_CCRV2_MSK, CapCompValue); -} - -/** - * @brief Get timer capture/compare value 2. - * @param timx AD16C4T instance - * @retval Timer capture/compare value 2. - */ - -__STATIC_INLINE uint32_t md_ad16c4t_get_ccval2_ccrv2(AD16C4T_TypeDef *timx) -{ - return (READ_BIT(timx->CCVAL2, AD16C4T_CCVAL2_CCRV2_MSK) >> AD16C4T_CCVAL2_CCRV2_POSS); -} - -/** - * @brief Timer CCVAL3 setup. - * @param timx AD16C4T instance - * @param value CCVAL3 - * @retval None - */ - -__STATIC_INLINE void md_ad16c4t_set_ccval3(AD16C4T_TypeDef *timx, uint32_t value) -{ - WRITE_REG(timx->CCVAL3, value); -} - -/** - * @brief GET Timer CCVAL3 register value. - * @param timx AD16C4T instance - * @retval Timer CCVAL3 register value. - */ - -__STATIC_INLINE uint32_t md_ad16c4t_get_ccval3(AD16C4T_TypeDef *timx) -{ - return (READ_REG(timx->CCVAL3)); -} - -/** - * @brief Timer capture/compare value 3 setup. - * @param timx AD16C4T instance - * @param CapCompValue Capture/Compare value 3 (between Min_Data=0 and Max_Data=0xFFFF) - * @retval None - */ - -__STATIC_INLINE void md_ad16c4t_set_ccval3_ccrv3(AD16C4T_TypeDef *timx, uint32_t CapCompValue) -{ - MODIFY_REG(timx->CCVAL3, AD16C4T_CCVAL3_CCRV3_MSK, CapCompValue); -} - -/** - * @brief Get timer capture/compare value 3. - * @param timx AD16C4T instance - * @retval Timer capture/compare value 3. - */ - -__STATIC_INLINE uint32_t md_ad16c4t_get_ccval3_ccrv3(AD16C4T_TypeDef *timx) -{ - return (READ_BIT(timx->CCVAL3, AD16C4T_CCVAL3_CCRV3_MSK) >> AD16C4T_CCVAL3_CCRV3_POSS); -} - -/** - * @brief Timer CCVAL4 setup. - * @param timx AD16C4T instance - * @param value CCVAL4 - * @retval None - */ - -__STATIC_INLINE void md_ad16c4t_set_ccval4(AD16C4T_TypeDef *timx, uint32_t value) -{ - WRITE_REG(timx->CCVAL4, value); -} - -/** - * @brief GET Timer CCVAL4 register value. - * @param timx AD16C4T instance - * @retval Timer CCVAL4 register value. - */ - -__STATIC_INLINE uint32_t md_ad16c4t_get_ccval4(AD16C4T_TypeDef *timx) -{ - return (READ_REG(timx->CCVAL4)); -} - -/** - * @brief Timer capture/compare value 4 setup. - * @param timx AD16C4T instance - * @param CapCompValue Capture/Compare value 4 (between Min_Data=0 and Max_Data=0xFFFF) - * @retval None - */ - -__STATIC_INLINE void md_ad16c4t_set_ccval4_ccrv4(AD16C4T_TypeDef *timx, uint32_t CapCompValue) -{ - MODIFY_REG(timx->CCVAL4, AD16C4T_CCVAL4_CCRV4_MSK, CapCompValue); -} - -/** - * @brief Get timer capture/compare value 4. - * @param timx AD16C4T instance - * @retval Timer capture/compare value 4. - */ - -__STATIC_INLINE uint32_t md_ad16c4t_get_ccval4_ccrv4(AD16C4T_TypeDef *timx) -{ - return (READ_BIT(timx->CCVAL4, AD16C4T_CCVAL4_CCRV4_MSK) >> AD16C4T_CCVAL4_CCRV4_POSS); -} - -/** - * @brief Timer BDCFG setup. - * @param timx AD16C4T instance - * @param value (GOEN | AOEN | BRKP | BRKEN | OFFSSR | OFFSSI | LOCKLVL | DT) - * @retval None - */ - -__STATIC_INLINE void md_ad16c4t_set_bdcfg(AD16C4T_TypeDef *timx, uint32_t value) -{ - WRITE_REG(timx->BDCFG, value); -} - -/** - * @brief GET Timer BDCFG register value. - * @param timx AD16C4T instance - * @retval Timer BDCFG register value. - */ - -__STATIC_INLINE uint32_t md_ad16c4t_get_bdcfg(AD16C4T_TypeDef *timx) -{ - return (READ_REG(timx->BDCFG)); -} - -/** - * @brief Timer main output enable. - * @param timx AD16C4T instance - * @retval None - */ - -__STATIC_INLINE void md_ad16c4t_enable_bdcfg_goen(AD16C4T_TypeDef *timx) -{ - SET_BIT(timx->BDCFG, AD16C4T_BDCFG_GOEN_MSK); -} - -/** - * @brief Timer main output disable. - * @param timx AD16C4T instance - * @retval None - */ - -__STATIC_INLINE void md_ad16c4t_disable_bdcfg_goen(AD16C4T_TypeDef *timx) -{ - CLEAR_BIT(timx->BDCFG, AD16C4T_BDCFG_GOEN_MSK); -} - -/** - * @brief Indicates whether the timer main output is enabled. - * @param timx AD16C4T instance - * @retval State of bit (1 or 0). - */ - -__STATIC_INLINE uint32_t md_ad16c4t_is_enabled_bdcfg_goen(AD16C4T_TypeDef *timx) -{ - return (READ_BIT(timx->BDCFG, AD16C4T_BDCFG_GOEN_MSK) == (AD16C4T_BDCFG_GOEN_MSK)); -} - -/** - * @brief Timer automatic output enable. - * @param timx AD16C4T instance - * @retval None - */ - -__STATIC_INLINE void md_ad16c4t_enable_bdcfg_aoen(AD16C4T_TypeDef *timx) -{ - SET_BIT(timx->BDCFG, AD16C4T_BDCFG_AOEN_MSK); -} - -/** - * @brief Timer automatic output disable. - * @param timx AD16C4T instance - * @retval None - */ - -__STATIC_INLINE void md_ad16c4t_disable_bdcfg_aoen(AD16C4T_TypeDef *timx) -{ - CLEAR_BIT(timx->BDCFG, AD16C4T_BDCFG_AOEN_MSK); -} - -/** - * @brief Indicates whether the timer automatic output is enabled. - * @param timx AD16C4T instance - * @retval State of bit (1 or 0). - */ - -__STATIC_INLINE uint32_t md_ad16c4t_is_enabled_bdcfg_aoen(AD16C4T_TypeDef *timx) -{ - return (READ_BIT(timx->BDCFG, AD16C4T_BDCFG_AOEN_MSK) == (AD16C4T_BDCFG_AOEN_MSK)); -} - -/** - * @brief Timer break polarity setup. - * @param timx AD16C4T instance - * @param BreakPolarity Break polarity - * @arg @ref MD_AD16C4T_BREAKPOLARITY_LOW - * @arg @ref MD_AD16C4T_BREAKPOLARITY_HIGH - * @retval None - */ - -__STATIC_INLINE void md_ad16c4t_set_bdcfg_brkp(AD16C4T_TypeDef *timx, uint32_t BreakPolarity) -{ - MODIFY_REG(timx->BDCFG, AD16C4T_BDCFG_BRKP_MSK, BreakPolarity); -} - -/** - * @brief Get timer break polarity. - * @param timx AD16C4T instance - * @retval Timer break polarity. - */ - -__STATIC_INLINE uint32_t md_ad16c4t_get_bdcfg_brkp(AD16C4T_TypeDef *timx) -{ - return (READ_BIT(timx->BDCFG, AD16C4T_BDCFG_BRKP_MSK) >> AD16C4T_BDCFG_BRKP_POS); -} - -/** - * @brief Timer break enable. - * @param timx AD16C4T instance - * @retval None - */ - -__STATIC_INLINE void md_ad16c4t_enable_bdcfg_brken(AD16C4T_TypeDef *timx) -{ - SET_BIT(timx->BDCFG, AD16C4T_BDCFG_BRKEN_MSK); -} - -/** - * @brief Timer break disable. - * @param timx AD16C4T instance - * @retval None - */ - -__STATIC_INLINE void md_ad16c4t_disable_bdcfg_brken(AD16C4T_TypeDef *timx) -{ - CLEAR_BIT(timx->BDCFG, AD16C4T_BDCFG_BRKEN_MSK); -} - -/** - * @brief Indicates whether the timer break is enabled. - * @param timx AD16C4T instance - * @retval State of bit (1 or 0). - */ - -__STATIC_INLINE uint32_t md_ad16c4t_is_enabled_bdcfg_brken(AD16C4T_TypeDef *timx) -{ - return (READ_BIT(timx->BDCFG, AD16C4T_BDCFG_BRKEN_MSK) == (AD16C4T_BDCFG_BRKEN_MSK)); -} - -/** - * @brief Timer off-state selection for run mode setup. - * @param timx AD16C4T instance - * @param OffStateRun Off-state selection for run mode - * @arg @ref MD_AD16C4T_OFFSTATERUN_DISABLE - * @arg @ref MD_AD16C4T_OFFSTATERUN_ENABLE - * @retval None - */ - -__STATIC_INLINE void md_ad16c4t_set_bdcfg_offssr(AD16C4T_TypeDef *timx, uint32_t OffStateRun) -{ - MODIFY_REG(timx->BDCFG, AD16C4T_BDCFG_OFFSSR_MSK, OffStateRun); -} - -/** - * @brief Get timer off-state selection for run mode. - * @param timx AD16C4T instance - * @retval Timer off-state selection for run mode. - */ - -__STATIC_INLINE uint32_t md_ad16c4t_get_bdcfg_offssr(AD16C4T_TypeDef *timx) -{ - return (READ_BIT(timx->BDCFG, AD16C4T_BDCFG_OFFSSR_MSK) >> AD16C4T_BDCFG_OFFSSR_POS); -} - -/** - * @brief Timer off-state selection for idle mode setup. - * @param timx AD16C4T instance - * @param OffStateIdle Off-state selection for idle mode - * @arg @ref MD_AD16C4T_OFFSTATEIDLE_DISABLE - * @arg @ref MD_AD16C4T_OFFSTATEIDLE_ENABLE - * @retval None - */ - -__STATIC_INLINE void md_ad16c4t_set_bdcfg_offssi(AD16C4T_TypeDef *timx, uint32_t OffStateIdle) -{ - MODIFY_REG(timx->BDCFG, AD16C4T_BDCFG_OFFSSI_MSK, OffStateIdle); -} - -/** - * @brief Get timer off-state selection for idle mode. - * @param timx AD16C4T instance - * @retval Timer off-state selection for idle mode. - */ - -__STATIC_INLINE uint32_t md_ad16c4t_get_bdcfg_offssi(AD16C4T_TypeDef *timx) -{ - return (READ_BIT(timx->BDCFG, AD16C4T_BDCFG_OFFSSI_MSK) >> AD16C4T_BDCFG_OFFSSI_POS); -} - -/** - * @brief Timer lock configuration setup. - * @param timx AD16C4T instance - * @param LockLevel Lock configuration - * @arg @ref MD_AD16C4T_LOCKLEVEL_0 - * @arg @ref MD_AD16C4T_LOCKLEVEL_1 - * @arg @ref MD_AD16C4T_LOCKLEVEL_2 - * @arg @ref MD_AD16C4T_LOCKLEVEL_3 - * @retval None - */ - -__STATIC_INLINE void md_ad16c4t_set_bdcfg_locklvl(AD16C4T_TypeDef *timx, uint32_t LockLevel) -{ - MODIFY_REG(timx->BDCFG, AD16C4T_BDCFG_LOCKLVL_MSK, LockLevel); -} - -/** - * @brief Get timer lock configuration. - * @param timx AD16C4T instance - * @retval Timer lock configuration. - */ - -__STATIC_INLINE uint32_t md_ad16c4t_get_bdcfg_locklvl(AD16C4T_TypeDef *timx) -{ - return (READ_BIT(timx->BDCFG, AD16C4T_BDCFG_LOCKLVL_MSK) >> AD16C4T_BDCFG_LOCKLVL_POSS); -} - -/** - * @brief Timer dead-time generator setup. - * @param timx AD16C4T instance - * @param DeadTime Dead-time generator (between Min_Data=0 and Max_Data=0xFF) - * @retval None - */ - -__STATIC_INLINE void md_ad16c4t_set_bdcfg_dt(AD16C4T_TypeDef *timx, uint32_t DeadTime) -{ - MODIFY_REG(timx->BDCFG, AD16C4T_BDCFG_DT_MSK, DeadTime); -} - -/** - * @brief Get timer dead-time generator. - * @param timx AD16C4T instance - * @retval Timer dead-time generator. - */ - -__STATIC_INLINE uint32_t md_ad16c4t_get_bdcfg_dt(AD16C4T_TypeDef *timx) -{ - return (READ_BIT(timx->BDCFG, AD16C4T_BDCFG_DT_MSK) >> AD16C4T_BDCFG_DT_POSS); -} - -/** - * @brief Timer DMAEN setup. - * @param timx AD16C4T instance - * @param value (TRGIDE | COMDE | CH4DE | CH3DE | CH2DE | CH1DE | UDE) - * @retval None - */ - -__STATIC_INLINE void md_ad16c4t_set_dmaen(AD16C4T_TypeDef *timx, uint32_t value) -{ - WRITE_REG(timx->DMAEN, value); -} - -/** - * @brief GET Timer DMAEN register value. - * @param timx AD16C4T instance - * @retval Timer DMAEN register value. - */ - -__STATIC_INLINE uint32_t md_ad16c4t_get_dmaen(AD16C4T_TypeDef *timx) -{ - return (READ_REG(timx->DMAEN)); -} - -/** - * @brief Timer trigger DMA request enable. - * @param timx AD16C4T instance - * @retval None - */ - -__STATIC_INLINE void md_ad16c4t_enable_dmaen_trgide(AD16C4T_TypeDef *timx) -{ - SET_BIT(timx->DMAEN, AD16C4T_DMAEN_TRGIDE_MSK); -} - -/** - * @brief Timer trigger DMA request disable. - * @param timx AD16C4T instance - * @retval None - */ - -__STATIC_INLINE void md_ad16c4t_disable_dmaen_trgide(AD16C4T_TypeDef *timx) -{ - CLEAR_BIT(timx->DMAEN, AD16C4T_DMAEN_TRGIDE_MSK); -} - -/** - * @brief Indicates whether the timer trigger DMA request is enabled. - * @param timx AD16C4T instance - * @retval State of bit (1 or 0). - */ - -__STATIC_INLINE uint32_t md_ad16c4t_is_enabled_dmaen_trgide(AD16C4T_TypeDef *timx) -{ - return (READ_BIT(timx->DMAEN, AD16C4T_DMAEN_TRGIDE_MSK) == (AD16C4T_DMAEN_TRGIDE_MSK)); -} - -/** - * @brief Timer COM DMA request enable. - * @param timx AD16C4T instance - * @retval None - */ - -__STATIC_INLINE void md_ad16c4t_enable_dmaen_comde(AD16C4T_TypeDef *timx) -{ - SET_BIT(timx->DMAEN, AD16C4T_DMAEN_COMDE_MSK); -} - -/** - * @brief Timer COM DMA request disable. - * @param timx AD16C4T instance - * @retval None - */ - -__STATIC_INLINE void md_ad16c4t_disable_dmaen_comde(AD16C4T_TypeDef *timx) -{ - CLEAR_BIT(timx->DMAEN, AD16C4T_DMAEN_COMDE_MSK); -} - -/** - * @brief Indicates whether the timer trigger COM request is enabled. - * @param timx AD16C4T instance - * @retval State of bit (1 or 0). - */ - -__STATIC_INLINE uint32_t md_ad16c4t_is_enabled_dmaen_comde(AD16C4T_TypeDef *timx) -{ - return (READ_BIT(timx->DMAEN, AD16C4T_DMAEN_COMDE_MSK) == (AD16C4T_DMAEN_COMDE_MSK)); -} - -/** - * @brief Timer Capture/Compare 4 DMA request enable. - * @param timx AD16C4T instance - * @retval None - */ - -__STATIC_INLINE void md_ad16c4t_enable_dmaen_ch4de(AD16C4T_TypeDef *timx) -{ - SET_BIT(timx->DMAEN, AD16C4T_DMAEN_CH4DE_MSK); -} - -/** - * @brief Timer Capture/Compare 4 DMA request disable. - * @param timx AD16C4T instance - * @retval None - */ - -__STATIC_INLINE void md_ad16c4t_disable_dmaen_ch4de(AD16C4T_TypeDef *timx) -{ - CLEAR_BIT(timx->DMAEN, AD16C4T_DMAEN_CH4DE_MSK); -} - -/** - * @brief Indicates whether the timer Capture/Compare 4 DMA request is enabled. - * @param timx AD16C4T instance - * @retval State of bit (1 or 0). - */ - -__STATIC_INLINE uint32_t md_ad16c4t_is_enabled_dmaen_ch4de(AD16C4T_TypeDef *timx) -{ - return (READ_BIT(timx->DMAEN, AD16C4T_DMAEN_CH4DE_MSK) == (AD16C4T_DMAEN_CH4DE_MSK)); -} - -/** - * @brief Timer Capture/Compare 3 DMA request enable. - * @param timx AD16C4T instance - * @retval None - */ - -__STATIC_INLINE void md_ad16c4t_enable_dmaen_ch3de(AD16C4T_TypeDef *timx) -{ - SET_BIT(timx->DMAEN, AD16C4T_DMAEN_CH3DE_MSK); -} - -/** - * @brief Timer Capture/Compare 3 DMA request disable. - * @param timx AD16C4T instance - * @retval None - */ - -__STATIC_INLINE void md_ad16c4t_disable_dmaen_ch3de(AD16C4T_TypeDef *timx) -{ - CLEAR_BIT(timx->DMAEN, AD16C4T_DMAEN_CH3DE_MSK); -} - -/** - * @brief Indicates whether the timer Capture/Compare 3 DMA request is enabled. - * @param timx AD16C4T instance - * @retval State of bit (1 or 0). - */ - -__STATIC_INLINE uint32_t md_ad16c4t_is_enabled_dmaen_ch3de(AD16C4T_TypeDef *timx) -{ - return (READ_BIT(timx->DMAEN, AD16C4T_DMAEN_CH3DE_MSK) == (AD16C4T_DMAEN_CH3DE_MSK)); -} - -/** - * @brief Timer Capture/Compare 2 DMA request enable. - * @param timx AD16C4T instance - * @retval None - */ - -__STATIC_INLINE void md_ad16c4t_enable_dmaen_ch2de(AD16C4T_TypeDef *timx) -{ - SET_BIT(timx->DMAEN, AD16C4T_DMAEN_CH2DE_MSK); -} - -/** - * @brief Timer Capture/Compare 2 DMA request disable. - * @param timx AD16C4T instance - * @retval None - */ - -__STATIC_INLINE void md_ad16c4t_disable_dmaen_ch2de(AD16C4T_TypeDef *timx) -{ - CLEAR_BIT(timx->DMAEN, AD16C4T_DMAEN_CH2DE_MSK); -} - -/** - * @brief Indicates whether the timer Capture/Compare 2 DMA request is enabled. - * @param timx AD16C4T instance - * @retval State of bit (1 or 0). - */ - -__STATIC_INLINE uint32_t md_ad16c4t_is_enabled_dmaen_ch2de(AD16C4T_TypeDef *timx) -{ - return (READ_BIT(timx->DMAEN, AD16C4T_DMAEN_CH2DE_MSK) == (AD16C4T_DMAEN_CH2DE_MSK)); -} - -/** - * @brief Timer Capture/Compare 1 DMA request enable. - * @param timx AD16C4T instance - * @retval None - */ - -__STATIC_INLINE void md_ad16c4t_enable_dmaen_ch1de(AD16C4T_TypeDef *timx) -{ - SET_BIT(timx->DMAEN, AD16C4T_DMAEN_CH1DE_MSK); -} - -/** - * @brief Timer Capture/Compare 1 DMA request disable. - * @param timx AD16C4T instance - * @retval None - */ - -__STATIC_INLINE void md_ad16c4t_disable_dmaen_ch1de(AD16C4T_TypeDef *timx) -{ - CLEAR_BIT(timx->DMAEN, AD16C4T_DMAEN_CH1DE_MSK); -} - -/** - * @brief Indicates whether the timer Capture/Compare 1 DMA request is enabled. - * @param timx AD16C4T instance - * @retval State of bit (1 or 0). - */ - -__STATIC_INLINE uint32_t md_ad16c4t_is_enabled_dmaen_ch1de(AD16C4T_TypeDef *timx) -{ - return (READ_BIT(timx->DMAEN, AD16C4T_DMAEN_CH1DE_MSK) == (AD16C4T_DMAEN_CH1DE_MSK)); -} - -/** - * @brief Timer update DMA request enable. - * @param timx AD16C4T instance - * @retval None - */ - -__STATIC_INLINE void md_ad16c4t_enable_dmaen_ude(AD16C4T_TypeDef *timx) -{ - SET_BIT(timx->DMAEN, AD16C4T_DMAEN_UDE_MSK); -} - -/** - * @brief Timer update DMA request disable. - * @param timx AD16C4T instance - * @retval None - */ - -__STATIC_INLINE void md_ad16c4t_disable_dmaen_ude(AD16C4T_TypeDef *timx) -{ - CLEAR_BIT(timx->DMAEN, AD16C4T_DMAEN_UDE_MSK); -} - -/** - * @brief Indicates whether the timer Capture/Compare update DMA request is enabled. - * @param timx AD16C4T instance - * @retval State of bit (1 or 0). - */ - -__STATIC_INLINE uint32_t md_ad16c4t_is_enabled_dmaen_ude(AD16C4T_TypeDef *timx) -{ - return (READ_BIT(timx->DMAEN, AD16C4T_DMAEN_UDE_MSK) == (AD16C4T_DMAEN_UDE_MSK)); -} -/** - * @} MD_AD16C4T_Public_Macro - */ - -/* Public functions -----------------------------------------------------------*/ - - - -/** - * @} AD16C4T - */ - - -#endif - -/** - * @} Micro_Driver - */ - - -#ifdef __cplusplus -} -#endif - -#endif diff --git a/bsp/essemi/es32f0271/libraries/ES32F027x_MD_StdPeriph_Driver/Include/md_adc.h b/bsp/essemi/es32f0271/libraries/ES32F027x_MD_StdPeriph_Driver/Include/md_adc.h deleted file mode 100644 index 3c3bdbc5f8..0000000000 --- a/bsp/essemi/es32f0271/libraries/ES32F027x_MD_StdPeriph_Driver/Include/md_adc.h +++ /dev/null @@ -1,6109 +0,0 @@ -/** - ****************************************************************************** - * @file md_ADC.h - * @brief ES32F0271 ADC Header File. - * - * @version V1.00.01 - * @date 04/12/2018 - * @author Eastsoft AE Team - * @note - * - * Copyright (C) 2018 Shanghai Eastsoft Microelectronics Co., Ltd. ALL rights reserved. - * - ******************************************************************************* - */ - -/* Define to prevent recursive inclusion -------------------------------------*/ -#ifndef __MD_ADC_H__ -#define __MD_ADC_H__ - -#ifdef __cplusplus -extern "C" { -#endif - -/* Includes -------------------------------------------------------------------*/ -#include "es32f0271.h" -#include "reg_adc.h" - -/** @addtogroup Micro_Driver - * @{ - */ - -#if defined ADC - -/** @defgroup ADC ADC - * @brief ADC micro driver - * @{ - */ - -/* Private types --------------------------------------------------------------*/ -/* Private variables ----------------------------------------------------------*/ -/* Private constants ----------------------------------------------------------*/ -/* Private macros -------------------------------------------------------------*/ -/* Public types ---------------------------------------------------------------*/ -/* Public constants -----------------------------------------------------------*/ -/* Public functions -----------------------------------------------------------*/ - -/** @defgroup MD_ADC_Public_Constants ADC Public Constants - * @{ - */ - -/** - * @brief ADC Init structure. - */ -typedef struct -{ - uint8_t VRLS; - uint8_t SSx; - uint32_t Sel; - uint32_t Type; - uint32_t Cntini; - uint32_t Cnt; - uint8_t End; - uint8_t Ckdiv; -} md_adc_inittypedef; -/** @defgroup MD_ADC_CFG ADC_CFG Register - * @{ - */ -#define MD_ADC_CFG_TESTEN (0xEDU) /** @brief data ADC Test Enable */ - -#define MD_ADC_CFG_MODE_NORMAL (0x00000000U<CFG, ADC_CFG_TESTEN_MSK, MD_ADC_CFG_TESTEN<CFG, ADC_CFG_MODE_MSK, Mode<CFG, ADC_CFG_MODE_MSK))>>ADC_CFG_MODE_POS); -} - -/** - * @brief Set ADC Wait Counter Value. - * @note Set the wait cycle between each ADC sample. - * @param ADCx ADC Instance - * @param CNT Value between Min_Value=0x00 and Max_Value=0xFF - * @retval None - */ -__STATIC_INLINE void md_adc_set_srate_cnt(ADC_TypeDef *ADCx, uint32_t cnt) -{ - MODIFY_REG(ADCx->SRATE, ADC_SRATE_CNT_MSK, cnt<SRATE, ADC_SRATE_CNT_MSK))>>ADC_SRATE_CNT_POSS); -} - -/** - * @brief Set ADC Wait Counter Initial Value. - * @note Set the Initial Value of ADC wait counter. - * @param ADCx ADC Instance - * @param CNTINI - * @arg @ref CNTINI Value between Min_Value=0x00 and Max_Value=0xFF - * @retval None - */ -__STATIC_INLINE void md_adc_set_srate_cntini(ADC_TypeDef *adcx, uint32_t cntini) -{ - MODIFY_REG(adcx->SRATE, ADC_SRATE_CNTINI_MSK, cntini<SRATE, ADC_SRATE_CNTINI_MSK))>>ADC_SRATE_CNTINI_POSS); -} - -/** - * @brief Set ADC Converter Clock Division. - * @note Get the division ratio of ADC converter clock. 0 to 15 division ratio - * where 0 indicates no division is implemented. To modify CLKDIV, user - * should first set CLKEN to 0 and re-enable this bit after modification - * on CLKDIV. - * @param ADCx ADC Instance - * @param ADC Converter Clock Division - * @arg @ref MD_ADC_SRATE_CKDIV1 - * @arg @ref MD_ADC_SRATE_CKDIV2 - * @arg @ref MD_ADC_SRATE_CKDIV4 - * @arg @ref MD_ADC_SRATE_CKDIV6 - * @arg @ref MD_ADC_SRATE_CKDIV8 - * @arg @ref MD_ADC_SRATE_CKDIV10 - * @arg @ref MD_ADC_SRATE_CKDIV12 - * @arg @ref MD_ADC_SRATE_CKDIV14 - * @arg @ref MD_ADC_SRATE_CKDIV16 - * @arg @ref MD_ADC_SRATE_CKDIV18 - * @arg @ref MD_ADC_SRATE_CKDIV20 - * @arg @ref MD_ADC_SRATE_CKDIV22 - * @arg @ref MD_ADC_SRATE_CKDIV24 - * @arg @ref MD_ADC_SRATE_CKDIV26 - * @arg @ref MD_ADC_SRATE_CKDIV28 - * @arg @ref MD_ADC_SRATE_CKDIV30 - * @retval None - */ -__STATIC_INLINE void md_adc_set_srate_clkdiv(ADC_TypeDef *ADCx, uint32_t clkdiv) -{ - MODIFY_REG(ADCx->SRATE, ADC_SRATE_CKDIV_MSK, clkdiv<SRATE, ADC_SRATE_CKDIV_MSK))>>ADC_SRATE_CKDIV_POSS); -} - -/** - * @brief ADC clock enable. - * @param ADCx ADC Instance - * @retval None - */ -__STATIC_INLINE void md_adc_enable_srate_clken(ADC_TypeDef *ADCx) -{ - SET_BIT(ADCx->SRATE, ADC_SRATE_CKEN_MSK); -} - -/** - * @brief ADC clock sisable. - * @param ADCx ADC Instance - * @retval None - */ -__STATIC_INLINE void md_adc_disable_srate_clken(ADC_TypeDef *ADCx) -{ - CLEAR_BIT(ADCx->SRATE, ADC_SRATE_CKEN_MSK); -} - -/** - * @brief Check if ADC clock is enabled. - * @param ADCx ADC Instance - * @retval State of bit (1 or 0). - */ -__STATIC_INLINE uint32_t md_adc_is_enabled_srate_clken(ADC_TypeDef *ADCx) -{ - return (READ_BIT(ADCx->SRATE, ADC_SRATE_CKEN_MSK) == (ADC_SRATE_CKEN_MSK)); -} - -/** - * @brief Channel 15 Invert Control enable. - * @note This is used to invert the data of channel 15. - * @param ADCx ADC Instance - * @retval None - */ -__STATIC_INLINE void md_adc_enable_srate_ch15inv(ADC_TypeDef *ADCx) -{ - SET_BIT(ADCx->SRATE, ADC_CHINV_CH15INV_MSK); -} - -/** - * @brief Channel 15 Invert Control disable. - * @note This is used to invert the data of channel 15. - * @param ADCx ADC Instance - * @retval None - */ -__STATIC_INLINE void md_adc_disable_srate_ch15inv(ADC_TypeDef *ADCx) -{ - CLEAR_BIT(ADCx->SRATE, ADC_CHINV_CH15INV_MSK); -} - -/** - * @brief Check if Channel 15 Invert Control is enabled. - * @note This is used to invert the data of channel 15. - * @param ADCx ADC Instance - * @retval State of bit (1 or 0). - */ -__STATIC_INLINE uint32_t md_adc_is_enabled_srate_ch15inv(ADC_TypeDef *ADCx) -{ - return (READ_BIT(ADCx->SRATE, ADC_CHINV_CH15INV_MSK) == (ADC_CHINV_CH15INV_MSK)); -} - -/** - * @brief Channel 14 Invert Control enable. - * @note This is used to invert the data of channel 14. - * @param ADCx ADC Instance - * @retval None - */ -__STATIC_INLINE void md_adc_enable_srate_ch14inv(ADC_TypeDef *ADCx) -{ - SET_BIT(ADCx->SRATE, ADC_CHINV_CH14INV_MSK); -} - -/** - * @brief Channel 14 Invert Control disable. - * @note This is used to invert the data of channel 14. - * @param ADCx ADC Instance - * @retval None - */ -__STATIC_INLINE void md_adc_disable_srate_ch14inv(ADC_TypeDef *ADCx) -{ - CLEAR_BIT(ADCx->SRATE, ADC_CHINV_CH14INV_MSK); -} - -/** - * @brief Check if Channel 14 Invert Control is enabled. - * @note This is used to invert the data of channel 14. - * @param ADCx ADC Instance - * @retval State of bit (1 or 0). - */ -__STATIC_INLINE uint32_t md_adc_is_enabled_srate_ch14inv(ADC_TypeDef *ADCx) -{ - return (READ_BIT(ADCx->SRATE, ADC_CHINV_CH14INV_MSK) == (ADC_CHINV_CH14INV_MSK)); -} - -/** - * @brief Channel 13 Invert Control enable. - * @note This is used to invert the data of channel 13. - * @param ADCx ADC Instance - * @retval None - */ -__STATIC_INLINE void md_adc_enable_srate_ch13inv(ADC_TypeDef *ADCx) -{ - SET_BIT(ADCx->SRATE, ADC_CHINV_CH13INV_MSK); -} - -/** - * @brief Channel 13 Invert Control disable. - * @note This is used to invert the data of channel 13. - * @param ADCx ADC Instance - * @retval None - */ -__STATIC_INLINE void md_adc_disable_srate_ch13inv(ADC_TypeDef *ADCx) -{ - CLEAR_BIT(ADCx->SRATE, ADC_CHINV_CH13INV_MSK); -} - -/** - * @brief Check if Channel 13 Invert Control is enabled. - * @note This is used to invert the data of channel 13. - * @param ADCx ADC Instance - * @retval State of bit (1 or 0). - */ -__STATIC_INLINE uint32_t md_adc_is_enabled_srate_ch13inv(ADC_TypeDef *ADCx) -{ - return (READ_BIT(ADCx->SRATE, ADC_CHINV_CH13INV_MSK) == (ADC_CHINV_CH13INV_MSK)); -} - -/** - * @brief Channel 12 Invert Control enable. - * @note This is used to invert the data of channel 12. - * @param ADCx ADC Instance - * @retval None - */ -__STATIC_INLINE void md_adc_enable_srate_ch12inv(ADC_TypeDef *ADCx) -{ - SET_BIT(ADCx->SRATE, ADC_CHINV_CH12INV_MSK); -} - -/** - * @brief Channel 12 Invert Control disable. - * @note This is used to invert the data of channel 12. - * @param ADCx ADC Instance - * @retval None - */ -__STATIC_INLINE void md_adc_disable_srate_ch12inv(ADC_TypeDef *ADCx) -{ - CLEAR_BIT(ADCx->SRATE, ADC_CHINV_CH12INV_MSK); -} - -/** - * @brief Check if Channel 12 Invert Control is enabled. - * @note This is used to invert the data of channel 12. - * @param ADCx ADC Instance - * @retval State of bit (1 or 0). - */ -__STATIC_INLINE uint32_t md_adc_is_enabled_srate_ch12inv(ADC_TypeDef *ADCx) -{ - return (READ_BIT(ADCx->SRATE, ADC_CHINV_CH12INV_MSK) == (ADC_CHINV_CH12INV_MSK)); -} - -/** - * @brief Channel 11 Invert Control enable. - * @note This is used to invert the data of channel 11. - * @param ADCx ADC Instance - * @retval None - */ -__STATIC_INLINE void md_adc_enable_srate_ch11inv(ADC_TypeDef *ADCx) -{ - SET_BIT(ADCx->SRATE, ADC_CHINV_CH15INV_MSK); -} - -/** - * @brief Channel 11 Invert Control disable. - * @note This is used to invert the data of channel 11. - * @param ADCx ADC Instance - * @retval None - */ -__STATIC_INLINE void md_adc_disable_srate_ch11inv(ADC_TypeDef *ADCx) -{ - CLEAR_BIT(ADCx->SRATE, ADC_CHINV_CH11INV_MSK); -} - -/** - * @brief Check if Channel 11 Invert Control is enabled. - * @note This is used to invert the data of channel 11. - * @param ADCx ADC Instance - * @retval State of bit (1 or 0). - */ -__STATIC_INLINE uint32_t md_adc_is_enabled_srate_ch11inv(ADC_TypeDef *ADCx) -{ - return (READ_BIT(ADCx->SRATE, ADC_CHINV_CH11INV_MSK) == (ADC_CHINV_CH11INV_MSK)); -} - -/** - * @brief Channel 10 Invert Control enable. - * @note This is used to invert the data of channel 10. - * @param ADCx ADC Instance - * @retval None - */ -__STATIC_INLINE void md_adc_enable_srate_ch10inv(ADC_TypeDef *ADCx) -{ - SET_BIT(ADCx->SRATE, ADC_CHINV_CH10INV_MSK); -} - -/** - * @brief Channel 10 Invert Control disable. - * @note This is used to invert the data of channel 10. - * @param ADCx ADC Instance - * @retval None - */ -__STATIC_INLINE void md_adc_disable_srate_ch10inv(ADC_TypeDef *ADCx) -{ - CLEAR_BIT(ADCx->SRATE, ADC_CHINV_CH10INV_MSK); -} - -/** - * @brief Check if Channel 10 Invert Control is enabled. - * @note This is used to invert the data of channel 10. - * @param ADCx ADC Instance - * @retval State of bit (1 or 0). - */ -__STATIC_INLINE uint32_t md_adc_is_enabled_srate_ch10inv(ADC_TypeDef *ADCx) -{ - return (READ_BIT(ADCx->SRATE, ADC_CHINV_CH10INV_MSK) == (ADC_CHINV_CH10INV_MSK)); -} - -/** - * @brief Channel 9 Invert Control enable. - * @note This is used to invert the data of channel 9. - * @param ADCx ADC Instance - * @retval None - */ -__STATIC_INLINE void md_adc_enable_srate_ch9inv(ADC_TypeDef *ADCx) -{ - SET_BIT(ADCx->SRATE, ADC_CHINV_CH9INV_MSK); -} - -/** - * @brief Channel 9 Invert Control disable. - * @note This is used to invert the data of channel 9. - * @param ADCx ADC Instance - * @retval None - */ -__STATIC_INLINE void md_adc_disable_srate_ch9inv(ADC_TypeDef *ADCx) -{ - CLEAR_BIT(ADCx->SRATE, ADC_CHINV_CH9INV_MSK); -} - -/** - * @brief Check if Channel 9 Invert Control is enabled. - * @note This is used to invert the data of channel 9. - * @param ADCx ADC Instance - * @retval State of bit (1 or 0). - */ -__STATIC_INLINE uint32_t md_adc_is_enabled_srate_ch9inv(ADC_TypeDef *ADCx) -{ - return (READ_BIT(ADCx->SRATE, ADC_CHINV_CH9INV_MSK) == (ADC_CHINV_CH9INV_MSK)); -} - -/** - * @brief Channel 8 Invert Control enable. - * @note This is used to invert the data of channel 8. - * @param ADCx ADC Instance - * @retval None - */ -__STATIC_INLINE void md_adc_enable_srate_ch8inv(ADC_TypeDef *ADCx) -{ - SET_BIT(ADCx->SRATE, ADC_CHINV_CH8INV_MSK); -} - -/** - * @brief Channel 8 Invert Control disable. - * @note This is used to invert the data of channel 8. - * @param ADCx ADC Instance - * @retval None - */ -__STATIC_INLINE void md_adc_disable_srate_ch8inv(ADC_TypeDef *ADCx) -{ - CLEAR_BIT(ADCx->SRATE, ADC_CHINV_CH8INV_MSK); -} - -/** - * @brief Check if Channel 8 Invert Control is enabled. - * @note This is used to invert the data of channel 8. - * @param ADCx ADC Instance - * @retval State of bit (1 or 0). - */ -__STATIC_INLINE uint32_t md_adc_is_enabled_srate_ch8inv(ADC_TypeDef *ADCx) -{ - return (READ_BIT(ADCx->SRATE, ADC_CHINV_CH8INV_MSK) == (ADC_CHINV_CH8INV_MSK)); -} - -/** - * @brief Channel 7 Invert Control enable. - * @note This is used to invert the data of channel 7. - * @param ADCx ADC Instance - * @retval None - */ -__STATIC_INLINE void md_adc_enable_srate_ch7inv(ADC_TypeDef *ADCx) -{ - SET_BIT(ADCx->SRATE, ADC_CHINV_CH7INV_MSK); -} - -/** - * @brief Channel 7 Invert Control disable. - * @note Disable invert data channel 7. - * @param ADCx ADC Instance - * @retval None - */ -__STATIC_INLINE void md_adc_disable_srate_ch7inv(ADC_TypeDef *ADCx) -{ - CLEAR_BIT(ADCx->SRATE, ADC_CHINV_CH7INV_MSK); -} - -/** - * @brief Check if Channel 7 Invert Control is enabled. - * @note Check invert state of data channel 7. - * @param ADCx ADC Instance - * @retval State of bit (1 or 0). - */ -__STATIC_INLINE uint32_t md_adc_is_enabled_srate_ch7inv(ADC_TypeDef *ADCx) -{ - return (READ_BIT(ADCx->SRATE, ADC_CHINV_CH7INV_MSK) == (ADC_CHINV_CH7INV_MSK)); -} - -/** - * @brief Channel 6 Invert Control enable. - * @note This is used to invert the data of channel 6. - * @param ADCx ADC Instance - * @retval None - */ -__STATIC_INLINE void md_adc_enable_srate_ch6inv(ADC_TypeDef *ADCx) -{ - SET_BIT(ADCx->SRATE, ADC_CHINV_CH6INV_MSK); -} - -/** - * @brief Channel 6 Invert Control disable. - * @note Disable invert data channel 6. - * @param ADCx ADC Instance - * @retval None - */ -__STATIC_INLINE void md_adc_disable_srate_ch6inv(ADC_TypeDef *ADCx) -{ - CLEAR_BIT(ADCx->SRATE, ADC_CHINV_CH6INV_MSK); -} - -/** - * @brief Check if Channel 6 Invert Control is enabled. - * @note Check invert state of data channel 6. - * @param ADCx ADC Instance - * @retval State of bit (1 or 0). - */ -__STATIC_INLINE uint32_t md_adc_is_enabled_srate_ch6inv(ADC_TypeDef *ADCx) -{ - return (READ_BIT(ADCx->SRATE, ADC_CHINV_CH6INV_MSK) == (ADC_CHINV_CH6INV_MSK)); -} - -/** - * @brief Channel 5 Invert Control enable. - * @note This is used to invert the data of channel 5. - * @param ADCx ADC Instance - * @retval None - */ -__STATIC_INLINE void md_adc_enable_srate_ch5inv(ADC_TypeDef *ADCx) -{ - SET_BIT(ADCx->SRATE, ADC_CHINV_CH5INV_MSK); -} - -/** - * @brief Channel 5 Invert Control disable. - * @note Disable invert data channel 5. - * @param ADCx ADC Instance - * @retval None - */ -__STATIC_INLINE void md_adc_disable_srate_ch5inv(ADC_TypeDef *ADCx) -{ - CLEAR_BIT(ADCx->SRATE, ADC_CHINV_CH5INV_MSK); -} - -/** - * @brief Check if Channel 5 Invert Control is enabled. - * @note Check invert state of data channel 5. - * @param ADCx ADC Instance - * @retval State of bit (1 or 0). - */ -__STATIC_INLINE uint32_t md_adc_is_enabled_srate_ch5inv(ADC_TypeDef *ADCx) -{ - return (READ_BIT(ADCx->SRATE, ADC_CHINV_CH5INV_MSK) == (ADC_CHINV_CH5INV_MSK)); -} - -/** - * @brief Channel 4 Invert Control enable. - * @note This is used to invert the data of channel 4. - * @param ADCx ADC Instance - * @retval None - */ -__STATIC_INLINE void md_adc_enable_srate_ch4inv(ADC_TypeDef *ADCx) -{ - SET_BIT(ADCx->SRATE, ADC_CHINV_CH4INV_MSK); -} - -/** - * @brief Channel 4 Invert Control disable. - * @note Disable invert data channel 4. - * @param ADCx ADC Instance - * @retval None - */ -__STATIC_INLINE void md_adc_disable_srate_ch4inv(ADC_TypeDef *ADCx) -{ - CLEAR_BIT(ADCx->SRATE, ADC_CHINV_CH4INV_MSK); -} - -/** - * @brief Check if Channel 4 Invert Control is enabled. - * @note Check invert state of data channel 4. - * @param ADCx ADC Instance - * @retval State of bit (1 or 0). - */ -__STATIC_INLINE uint32_t md_adc_is_enabled_srate_ch4inv(ADC_TypeDef *ADCx) -{ - return (READ_BIT(ADCx->SRATE, ADC_CHINV_CH4INV_MSK) == (ADC_CHINV_CH4INV_MSK)); -} - -/** - * @brief Channel 3 Invert Control enable. - * @note This is used to invert the data of channel 3. - * @param ADCx ADC Instance - * @retval None - */ -__STATIC_INLINE void md_adc_enable_srate_ch3inv(ADC_TypeDef *ADCx) -{ - SET_BIT(ADCx->SRATE, ADC_CHINV_CH3INV_MSK); -} - -/** - * @brief Channel 3 Invert Control disable. - * @note Disable invert data channel 3. - * @param ADCx ADC Instance - * @retval None - */ -__STATIC_INLINE void md_adc_disable_srate_ch3inv(ADC_TypeDef *ADCx) -{ - CLEAR_BIT(ADCx->SRATE, ADC_CHINV_CH3INV_MSK); -} - -/** - * @brief Check if Channel 3 Invert Control is enabled. - * @note Check invert state of data of channel 3. - * @param ADCx ADC Instance - * @retval State of bit (1 or 0). - */ -__STATIC_INLINE uint32_t md_adc_is_enabled_srate_ch3inv(ADC_TypeDef *ADCx) -{ - return (READ_BIT(ADCx->SRATE, ADC_CHINV_CH3INV_MSK) == (ADC_CHINV_CH3INV_MSK)); -} - -/** - * @brief Channel 2 Invert Control enable. - * @note This is used to invert the data of channel 2. - * @param ADCx ADC Instance - * @retval None - */ -__STATIC_INLINE void md_adc_enable_srate_ch2inv(ADC_TypeDef *ADCx) -{ - SET_BIT(ADCx->SRATE, ADC_CHINV_CH2INV_MSK); -} - -/** - * @brief Channel 2 Invert Control disable. - * @note Disable invert data channel 2. - * @param ADCx ADC Instance - * @retval None - */ -__STATIC_INLINE void md_adc_disable_srate_ch2inv(ADC_TypeDef *ADCx) -{ - CLEAR_BIT(ADCx->SRATE, ADC_CHINV_CH2INV_MSK); -} - -/** - * @brief Check if Channel 2 Invert Control is enabled. - * @note Check invert state of data of channel 2. - * @param ADCx ADC Instance - * @retval State of bit (1 or 0). - */ -__STATIC_INLINE uint32_t md_adc_is_enabled_srate_ch2inv(ADC_TypeDef *ADCx) -{ - return (READ_BIT(ADCx->SRATE, ADC_CHINV_CH2INV_MSK) == (ADC_CHINV_CH2INV_MSK)); -} - -/** - * @brief Channel 1 Invert Control enable. - * @note This is used to invert the data of channel 1. - * @param ADCx ADC Instance - * @retval None - */ -__STATIC_INLINE void md_adc_enable_srate_ch1inv(ADC_TypeDef *ADCx) -{ - SET_BIT(ADCx->SRATE, ADC_CHINV_CH1INV_MSK); -} - -/** - * @brief Channel 1 Invert Control disable. - * @note Disable invert data channel 1. - * @param ADCx ADC Instance - * @retval None - */ -__STATIC_INLINE void md_adc_disable_srate_ch1inv(ADC_TypeDef *ADCx) -{ - CLEAR_BIT(ADCx->SRATE, ADC_CHINV_CH1INV_MSK); -} - -/** - * @brief Check if Channel 1 Invert Control is enabled. - * @note Check invert of data of channel 1. - * @param ADCx ADC Instance - * @retval State of bit (1 or 0). - */ -__STATIC_INLINE uint32_t md_adc_is_enabled_srate_ch1inv(ADC_TypeDef *ADCx) -{ - return (READ_BIT(ADCx->SRATE, ADC_CHINV_CH1INV_MSK) == (ADC_CHINV_CH1INV_MSK)); -} - -/** - * @brief Channel 0 Invert Control enable. - * @note This is used to invert the data of channel 0. - * @param ADCx ADC Instance - * @retval None - */ -__STATIC_INLINE void md_adc_enable_srate_ch0inv(ADC_TypeDef *ADCx) -{ - SET_BIT(ADCx->SRATE, ADC_CHINV_CH0INV_MSK); -} - -/** - * @brief Channel 0 Invert Control disable. - * @note Disable invert data channel 0. - * @param ADCx ADC Instance - * @retval None - */ -__STATIC_INLINE void md_adc_disable_srate_ch0inv(ADC_TypeDef *ADCx) -{ - CLEAR_BIT(ADCx->SRATE, ADC_CHINV_CH0INV_MSK); -} - -/** - * @brief Check if Channel 0 Invert Control is enabled. - * @note Check invert state of data of channel 0. - * @param ADCx ADC Instance - * @retval State of bit (1 or 0). - */ -__STATIC_INLINE uint32_t md_adc_is_enabled_srate_ch0inv(ADC_TypeDef *ADCx) -{ - return (READ_BIT(ADCx->SRATE, ADC_CHINV_CH0INV_MSK) == (ADC_CHINV_CH0INV_MSK)); -} - -/** - * @brief Set ADC SRATE register. - * @note This is used to set SRATE register. - * @param ADCx ADC Instance - * @param SRATE - * @retval NONE. - */ -__STATIC_INLINE void md_adc_set_srate(ADC_TypeDef *adcx, uint32_t srate) -{ - WRITE_REG(adcx->SRATE, srate); -} - -/** - * @brief Get ADC SRATE register. - * @note This is used to read SRATE register. - * @param ADCx ADC Instance - * @param SRATE - * @retval SRATE Register Value. - */ -__STATIC_INLINE uint32_t md_adc_get_srate(ADC_TypeDef *adcx) -{ - return READ_REG(adcx->SRATE); -} - -/** - * @brief Set ADC Channel 7 PGA Gain. - * @note This is used to select channel 7 PGA gain. - * @param ADCx ADC Instance - * @param ADC PGA Gain - * @param Gain parameter can be one of the following values: - * @arg @ref MD_ADC_PGA_GAIN_X1 - * @arg @ref MD_ADC_PGA_GAIN_X2 - * @arg @ref MD_ADC_PGA_GAIN_X3 - * @arg @ref MD_ADC_PGA_GAIN_X4 - * @arg @ref MD_ADC_PGA_GAIN_X5 - * @arg @ref MD_ADC_PGA_GAIN_X6 - * @arg @ref MD_ADC_PGA_GAIN_X7 - * @arg @ref MD_ADC_PGA_GAIN_X8 - * @retval None - */ -__STATIC_INLINE void md_adc_set_gainl_ch7pga(ADC_TypeDef *ADCx, uint32_t Gain) -{ - MODIFY_REG(ADCx->GAINL, ADC_GAINL_CH7PGA_MSK, Gain<GAINL, ADC_GAINL_CH7PGA_MSK)>>ADC_GAINL_CH7PGA_POSS); -} - -/** - * @brief Set ADC Channel 6 PGA Gain. - * @note This is used to select channel 6 PGA gain. - * @param ADCx ADC Instance - * @param ADC PGA Gain - * @param Gain parameter can be one of the following values: - * @arg @ref MD_ADC_PGA_GAIN_X1 - * @arg @ref MD_ADC_PGA_GAIN_X2 - * @arg @ref MD_ADC_PGA_GAIN_X3 - * @arg @ref MD_ADC_PGA_GAIN_X4 - * @arg @ref MD_ADC_PGA_GAIN_X5 - * @arg @ref MD_ADC_PGA_GAIN_X6 - * @arg @ref MD_ADC_PGA_GAIN_X7 - * @arg @ref MD_ADC_PGA_GAIN_X8 - * @retval None - */ -__STATIC_INLINE void md_adc_set_gainl_ch6pga(ADC_TypeDef *ADCx, uint32_t Gain) -{ - MODIFY_REG(ADCx->GAINL, ADC_GAINL_CH6PGA_MSK, Gain<GAINL, ADC_GAINL_CH6PGA_MSK)>>ADC_GAINL_CH6PGA_POSS); -} - -/** - * @brief Set ADC Channel 5 PGA Gain. - * @note This is used to select channel 5 PGA gain. - * @param ADCx ADC Instance - * @param ADC PGA Gain - * @param Gain parameter can be one of the following values: - * @arg @ref MD_ADC_PGA_GAIN_X1 - * @arg @ref MD_ADC_PGA_GAIN_X2 - * @arg @ref MD_ADC_PGA_GAIN_X3 - * @arg @ref MD_ADC_PGA_GAIN_X4 - * @arg @ref MD_ADC_PGA_GAIN_X5 - * @arg @ref MD_ADC_PGA_GAIN_X6 - * @arg @ref MD_ADC_PGA_GAIN_X7 - * @arg @ref MD_ADC_PGA_GAIN_X8 - * @retval None - */ -__STATIC_INLINE void md_adc_set_gainl_ch5pga(ADC_TypeDef *ADCx, uint32_t Gain) -{ - MODIFY_REG(ADCx->GAINL, ADC_GAINL_CH5PGA_MSK, Gain<GAINL, ADC_GAINL_CH5PGA_MSK)>>ADC_GAINL_CH5PGA_POSS); -} - -/** - * @brief Set ADC Channel 4 PGA Gain. - * @note This is used to select channel 4 PGA gain. - * @param ADCx ADC Instance - * @param ADC PGA Gain - * @param Gain parameter can be one of the following values: - * @arg @ref MD_ADC_PGA_GAIN_X1 - * @arg @ref MD_ADC_PGA_GAIN_X2 - * @arg @ref MD_ADC_PGA_GAIN_X3 - * @arg @ref MD_ADC_PGA_GAIN_X4 - * @arg @ref MD_ADC_PGA_GAIN_X5 - * @arg @ref MD_ADC_PGA_GAIN_X6 - * @arg @ref MD_ADC_PGA_GAIN_X7 - * @arg @ref MD_ADC_PGA_GAIN_X8 - * @retval None - */ -__STATIC_INLINE void md_adc_set_gainl_ch4pga(ADC_TypeDef *ADCx, uint32_t Gain) -{ - MODIFY_REG(ADCx->GAINL, ADC_GAINL_CH4PGA_MSK, Gain<GAINL, ADC_GAINL_CH4PGA_MSK)>>ADC_GAINL_CH4PGA_POSS); -} - -/** - * @brief Set ADC Channel 3 PGA Gain. - * @note This is used to select channel 3 PGA gain. - * @param ADCx ADC Instance - * @param ADC PGA Gain - * @param Gain parameter can be one of the following values: - * @arg @ref MD_ADC_PGA_GAIN_X1 - * @arg @ref MD_ADC_PGA_GAIN_X2 - * @arg @ref MD_ADC_PGA_GAIN_X3 - * @arg @ref MD_ADC_PGA_GAIN_X4 - * @arg @ref MD_ADC_PGA_GAIN_X5 - * @arg @ref MD_ADC_PGA_GAIN_X6 - * @arg @ref MD_ADC_PGA_GAIN_X7 - * @arg @ref MD_ADC_PGA_GAIN_X8 - * @retval None - */ -__STATIC_INLINE void md_adc_set_gainl_ch3pga(ADC_TypeDef *ADCx, uint32_t Gain) -{ - MODIFY_REG(ADCx->GAINL, ADC_GAINL_CH3PGA_MSK, Gain<GAINL, ADC_GAINL_CH3PGA_MSK)>>ADC_GAINL_CH3PGA_POSS); -} - -/** - * @brief Set ADC Channel 2 PGA Gain. - * @note This is used to select channel 2 PGA gain. - * @param ADCx ADC Instance - * @param ADC PGA Gain - * @param Gain parameter can be one of the following values: - * @arg @ref MD_ADC_PGA_GAIN_X1 - * @arg @ref MD_ADC_PGA_GAIN_X2 - * @arg @ref MD_ADC_PGA_GAIN_X3 - * @arg @ref MD_ADC_PGA_GAIN_X4 - * @arg @ref MD_ADC_PGA_GAIN_X5 - * @arg @ref MD_ADC_PGA_GAIN_X6 - * @arg @ref MD_ADC_PGA_GAIN_X7 - * @arg @ref MD_ADC_PGA_GAIN_X8 - * @retval None - */ -__STATIC_INLINE void md_adc_set_gainl_ch2pga(ADC_TypeDef *ADCx, uint32_t Gain) -{ - MODIFY_REG(ADCx->GAINL, ADC_GAINL_CH2PGA_MSK, Gain<GAINL, ADC_GAINL_CH2PGA_MSK)>>ADC_GAINL_CH2PGA_POSS); -} - -/** - * @brief Set ADC Channel 1 PGA Gain. - * @note This is used to select channel 1 PGA gain. - * @param ADCx ADC Instance - * @param ADC PGA Gain - * @param Gain parameter can be one of the following values: - * @arg @ref MD_ADC_PGA_GAIN_X1 - * @arg @ref MD_ADC_PGA_GAIN_X2 - * @arg @ref MD_ADC_PGA_GAIN_X3 - * @arg @ref MD_ADC_PGA_GAIN_X4 - * @arg @ref MD_ADC_PGA_GAIN_X5 - * @arg @ref MD_ADC_PGA_GAIN_X6 - * @arg @ref MD_ADC_PGA_GAIN_X7 - * @arg @ref MD_ADC_PGA_GAIN_X8 - * @retval None - */ -__STATIC_INLINE void md_adc_set_gainl_ch1pga(ADC_TypeDef *ADCx, uint32_t Gain) -{ - MODIFY_REG(ADCx->GAINL, ADC_GAINL_CH1PGA_MSK, Gain<GAINL, ADC_GAINL_CH1PGA_MSK)>>ADC_GAINL_CH1PGA_POSS); -} - -/** - * @brief Set ADC Channel 0 PGA Gain. - * @note This is used to select channel 0 PGA gain. - * @param ADCx ADC Instance - * @param ADC PGA Gain - * @param Gain parameter can be one of the following values: - * @arg @ref MD_ADC_PGA_GAIN_X1 - * @arg @ref MD_ADC_PGA_GAIN_X2 - * @arg @ref MD_ADC_PGA_GAIN_X3 - * @arg @ref MD_ADC_PGA_GAIN_X4 - * @arg @ref MD_ADC_PGA_GAIN_X5 - * @arg @ref MD_ADC_PGA_GAIN_X6 - * @arg @ref MD_ADC_PGA_GAIN_X7 - * @arg @ref MD_ADC_PGA_GAIN_X8 - * @retval None - */ -__STATIC_INLINE void md_adc_set_gainl_ch0pga(ADC_TypeDef *ADCx, uint32_t Gain) -{ - MODIFY_REG(ADCx->GAINL, ADC_GAINL_CH0PGA_MSK, Gain<GAINL, ADC_GAINL_CH0PGA_MSK)>>ADC_GAINL_CH0PGA_POSS); -} - -/** - * @brief Set ADC Channels 0~7 PGA Gain. - * @note This is used to select channels 0-7 PGA gain. - * @param ADCx ADC Instance - * @param GainL Register Values for CH0~CH7. - * @retval None - */ -__STATIC_INLINE void md_adc_set_gainl(ADC_TypeDef *ADCx, uint32_t GainL) -{ - WRITE_REG(ADCx->GAINL, GainL); -} - -/** - * @brief Get ADC Channels 0~7 PGA Gain. - * @note This is used to read channels 0-7 PGA gain. - * @param ADCx ADC Instance - * @retval GainL Register Values for CH0~CH7. - */ -__STATIC_INLINE uint32_t md_adc_get_gainl(ADC_TypeDef *ADCx) -{ - return READ_REG(ADCx->GAINL); -} - -/** - * @brief Set ADC Channel 15 PGA Gain. - * @note This is used to select channel 15 PGA gain. - * @param ADCx ADC Instance - * @param ADC PGA Gain - * @param Gain parameter can be one of the following values: - * @arg @ref MD_ADC_PGA_GAIN_X1 - * @arg @ref MD_ADC_PGA_GAIN_X2 - * @arg @ref MD_ADC_PGA_GAIN_X3 - * @arg @ref MD_ADC_PGA_GAIN_X4 - * @arg @ref MD_ADC_PGA_GAIN_X5 - * @arg @ref MD_ADC_PGA_GAIN_X6 - * @arg @ref MD_ADC_PGA_GAIN_X7 - * @arg @ref MD_ADC_PGA_GAIN_X8 - * @retval None - */ -__STATIC_INLINE void md_adc_set_gainh_ch15pga(ADC_TypeDef *ADCx, uint32_t Gain) -{ - MODIFY_REG(ADCx->GAINH, ADC_GAINH_CH15PGA_MSK, Gain<GAINH, ADC_GAINH_CH15PGA_MSK)>>ADC_GAINH_CH15PGA_POSS); -} - -/** - * @brief Set ADC Channel 14 PGA Gain. - * @note This is used to select channel 14 PGA gain. - * @param ADCx ADC Instance - * @param ADC PGA Gain - * @param Gain parameter can be one of the following values: - * @arg @ref MD_ADC_PGA_GAIN_X1 - * @arg @ref MD_ADC_PGA_GAIN_X2 - * @arg @ref MD_ADC_PGA_GAIN_X3 - * @arg @ref MD_ADC_PGA_GAIN_X4 - * @arg @ref MD_ADC_PGA_GAIN_X5 - * @arg @ref MD_ADC_PGA_GAIN_X6 - * @arg @ref MD_ADC_PGA_GAIN_X7 - * @arg @ref MD_ADC_PGA_GAIN_X8 - * @retval None - */ -__STATIC_INLINE void md_adc_set_gainh_ch14pga(ADC_TypeDef *ADCx, uint32_t Gain) -{ - MODIFY_REG(ADCx->GAINH, ADC_GAINH_CH14PGA_MSK, Gain<GAINH, ADC_GAINH_CH14PGA_MSK)>>ADC_GAINH_CH14PGA_POSS); -} - -/** - * @brief Set ADC Channel 13 PGA Gain. - * @note This is used to select channel 13 PGA gain. - * @param ADCx ADC Instance - * @param ADC PGA Gain - * @param Gain parameter can be one of the following values: - * @arg @ref MD_ADC_PGA_GAIN_X1 - * @arg @ref MD_ADC_PGA_GAIN_X2 - * @arg @ref MD_ADC_PGA_GAIN_X3 - * @arg @ref MD_ADC_PGA_GAIN_X4 - * @arg @ref MD_ADC_PGA_GAIN_X5 - * @arg @ref MD_ADC_PGA_GAIN_X6 - * @arg @ref MD_ADC_PGA_GAIN_X7 - * @arg @ref MD_ADC_PGA_GAIN_X8 - * @retval None - */ -__STATIC_INLINE void md_adc_set_gainh_ch13pga(ADC_TypeDef *ADCx, uint32_t Gain) -{ - MODIFY_REG(ADCx->GAINH, ADC_GAINH_CH13PGA_MSK, Gain<GAINH, ADC_GAINH_CH13PGA_MSK)>>ADC_GAINH_CH13PGA_POSS); -} - -/** - * @brief Set ADC Channel 12 PGA Gain. - * @note This is used to select channel 12 PGA gain. - * @param ADCx ADC Instance - * @param ADC PGA Gain - * @param Gain parameter can be one of the following values: - * @arg @ref MD_ADC_PGA_GAIN_X1 - * @arg @ref MD_ADC_PGA_GAIN_X2 - * @arg @ref MD_ADC_PGA_GAIN_X3 - * @arg @ref MD_ADC_PGA_GAIN_X4 - * @arg @ref MD_ADC_PGA_GAIN_X5 - * @arg @ref MD_ADC_PGA_GAIN_X6 - * @arg @ref MD_ADC_PGA_GAIN_X7 - * @arg @ref MD_ADC_PGA_GAIN_X8 - * @retval None - */ -__STATIC_INLINE void md_adc_set_gainh_ch12pga(ADC_TypeDef *ADCx, uint32_t Gain) -{ - MODIFY_REG(ADCx->GAINH, ADC_GAINH_CH12PGA_MSK, Gain<GAINH, ADC_GAINH_CH12PGA_MSK)>>ADC_GAINH_CH12PGA_POSS); -} - -/** - * @brief Set ADC Channel 11 PGA Gain. - * @note This is used to select channel 11 PGA gain. - * @param ADCx ADC Instance - * @param ADC PGA Gain - * @param Gain parameter can be one of the following values: - * @arg @ref MD_ADC_PGA_GAIN_X1 - * @arg @ref MD_ADC_PGA_GAIN_X2 - * @arg @ref MD_ADC_PGA_GAIN_X3 - * @arg @ref MD_ADC_PGA_GAIN_X4 - * @arg @ref MD_ADC_PGA_GAIN_X5 - * @arg @ref MD_ADC_PGA_GAIN_X6 - * @arg @ref MD_ADC_PGA_GAIN_X7 - * @arg @ref MD_ADC_PGA_GAIN_X8 - * @retval None - */ -__STATIC_INLINE void md_adc_set_gainh_ch11pga(ADC_TypeDef *ADCx, uint32_t Gain) -{ - MODIFY_REG(ADCx->GAINH, ADC_GAINH_CH11PGA_MSK, Gain<GAINH, ADC_GAINH_CH11PGA_MSK)>>ADC_GAINH_CH11PGA_POSS); -} - -/** - * @brief Set ADC Channel 10 PGA Gain. - * @note This is used to select channel 10 PGA gain. - * @param ADCx ADC Instance - * @param ADC PGA Gain - * @param Gain parameter can be one of the following values: - * @arg @ref MD_ADC_PGA_GAIN_X1 - * @arg @ref MD_ADC_PGA_GAIN_X2 - * @arg @ref MD_ADC_PGA_GAIN_X3 - * @arg @ref MD_ADC_PGA_GAIN_X4 - * @arg @ref MD_ADC_PGA_GAIN_X5 - * @arg @ref MD_ADC_PGA_GAIN_X6 - * @arg @ref MD_ADC_PGA_GAIN_X7 - * @arg @ref MD_ADC_PGA_GAIN_X8 - * @retval None - */ -__STATIC_INLINE void md_adc_set_gainh_ch10pga(ADC_TypeDef *ADCx, uint32_t Gain) -{ - MODIFY_REG(ADCx->GAINH, ADC_GAINH_CH10PGA_MSK, Gain<GAINH, ADC_GAINH_CH10PGA_MSK)>>ADC_GAINH_CH10PGA_POSS); -} - -/** - * @brief Set ADC Channel 9 PGA Gain. - * @note This is used to select channel 9 PGA gain. - * @param ADCx ADC Instance - * @param ADC PGA Gain - * @param Gain parameter can be one of the following values: - * @arg @ref MD_ADC_PGA_GAIN_X1 - * @arg @ref MD_ADC_PGA_GAIN_X2 - * @arg @ref MD_ADC_PGA_GAIN_X3 - * @arg @ref MD_ADC_PGA_GAIN_X4 - * @arg @ref MD_ADC_PGA_GAIN_X5 - * @arg @ref MD_ADC_PGA_GAIN_X6 - * @arg @ref MD_ADC_PGA_GAIN_X7 - * @arg @ref MD_ADC_PGA_GAIN_X8 - * @retval None - */ -__STATIC_INLINE void md_adc_set_gainh_ch9pga(ADC_TypeDef *ADCx, uint32_t Gain) -{ - MODIFY_REG(ADCx->GAINH, ADC_GAINH_CH9PGA_MSK, Gain<GAINH, ADC_GAINH_CH9PGA_MSK)>>ADC_GAINH_CH9PGA_POSS); -} - -/** - * @brief Set ADC Channel 8 PGA Gain. - * @note This is used to select channel 8 PGA gain. - * @param ADCx ADC Instance - * @param ADC PGA Gain - * @param Gain parameter can be one of the following values: - * @arg @ref MD_ADC_PGA_GAIN_X1 - * @arg @ref MD_ADC_PGA_GAIN_X2 - * @arg @ref MD_ADC_PGA_GAIN_X3 - * @arg @ref MD_ADC_PGA_GAIN_X4 - * @arg @ref MD_ADC_PGA_GAIN_X5 - * @arg @ref MD_ADC_PGA_GAIN_X6 - * @arg @ref MD_ADC_PGA_GAIN_X7 - * @arg @ref MD_ADC_PGA_GAIN_X8 - * @retval None - */ -__STATIC_INLINE void md_adc_set_gainh_ch8pga(ADC_TypeDef *ADCx, uint32_t Gain) -{ - MODIFY_REG(ADCx->GAINH, ADC_GAINH_CH8PGA_MSK, Gain<GAINH, ADC_GAINH_CH8PGA_MSK)>>ADC_GAINH_CH8PGA_POSS); -} - -/** - * @brief Set ADC Channels 8~15 PGA Gain. - * @note This register is used to select channels 8-15 PGA gain. - * @param GainH Register Values for CH8~CH15. - * @retval None - */ -__STATIC_INLINE void md_adc_set_gainh(ADC_TypeDef *ADCx, uint32_t GainH) -{ - WRITE_REG(ADCx->GAINH, GainH); -} - -/** - * @brief Get ADC Channels 8~15 PGA Gain. - * @note This register is used to read channels 8-15 PGA gain. - * @param ADCx ADC Instance - * @retval GainH Register Values for CH8~CH15. - */ -__STATIC_INLINE uint32_t md_adc_get_gainh(ADC_TypeDef *ADCx) -{ - return READ_REG(ADCx->GAINH); -} - -/** - * @brief Refresh ADC FIFOs SS0~SS3. - * @note This register allowed users to reset ADC FIFO when starting a - * new Sample Sequencer. - * @param ADCx ADC Instance - * @param Value if bit (1 or 0) - * @retval None - */ -__STATIC_INLINE void md_adc_set_frf_ffrst(ADC_TypeDef *ADCx) -{ - SET_BIT(ADCx->FRF, ADC_FRF_FFRST_MSK); -} - -/** - * @brief Get ADC FIFO Refresh Status. - * @param ADCx ADC Instance - * @retval State of bit (1 or 0). - */ -__STATIC_INLINE uint32_t md_adc_get_frf_ffrst(ADC_TypeDef *ADCx) -{ - return (READ_BIT(ADCx->FRF, ADC_FRF_FFRST_MSK)>>ADC_FRF_FFRST_POS); -} - -/** - * @brief Refresh ADC SS3 FIFO. - * @note This register is used to refresh the FIFO of sequencer 3 at any - * time. This bit will cleared by itself. - * @param ADCx ADC Instance - * @retval None - */ -__STATIC_INLINE void md_adc_set_frf_ss3rf(ADC_TypeDef *ADCx) -{ - SET_BIT(ADCx->FRF, ADC_FRF_SS3RF_MSK); -} - -/** - * @brief Refresh ADC SS32 FIFO. - * @note This register is used to refresh the FIFO of sequencer 2 at any - * time. This bit will cleared by itself. - * @param ADCx ADC Instance - * @retval None - */ -__STATIC_INLINE void md_adc_set_frf_ss2rf(ADC_TypeDef *ADCx) -{ - SET_BIT(ADCx->FRF, ADC_FRF_SS2RF_MSK); -} - -/** - * @brief Refresh ADC SS1 FIFO. - * @note This register is used to refresh the FIFO of sequencer 1 at any - * time. This bit will cleared by itself. - * @param ADCx ADC Instance - * @retval None - */ -__STATIC_INLINE void md_adc_set_frf_ss1rf(ADC_TypeDef *ADCx) -{ - SET_BIT(ADCx->FRF, ADC_FRF_SS1RF_MSK); -} - -/** - * @brief Refresh ADC SS0 FIFO. - * @note This register is used to refresh the FIFO of sequencer 0 at any - * time. This bit will cleared by itself. - * @param ADCx ADC Instance - * @retval None - */ -__STATIC_INLINE void md_adc_set_frf_ss0rf(ADC_TypeDef *ADCx) -{ - SET_BIT(ADCx->FRF, ADC_FRF_SS0RF_MSK); -} - -/** - * @brief Refresh ADC FIFO Register. - * @note This is used to set RFR register. - * @param ADCx ADC Instance - * @param Register Value - * @retval None - */ -__STATIC_INLINE void md_adc_set_frf(ADC_TypeDef *ADCx, uint32_t Value) -{ - WRITE_REG(ADCx->FRF, Value); -} - -/** - * @brief Get ADC FIFO Refresh Register. - * @note This is used to get RFR register. - * @param ADCx ADC Instance - * @retval Register Value - */ -__STATIC_INLINE uint32_t md_adc_get_frf(ADC_TypeDef *ADCx) -{ - return READ_REG(ADCx->FRF); -} - -/** - * @brief Check if all ADC Sequencer is idle. - * @note Check if SS0~SS3 is idle. - * @param ADCx ADC Instance - * @retval State of bit (1 or 0). - */ -__STATIC_INLINE uint32_t md_adc_is_idle(ADC_TypeDef *ADCx) -{ - return (READ_BIT(ADCx->SSEN, ADC_SSEN_IDLE_MSK) == (ADC_SSEN_IDLE_MSK)); -} - -/** - * @brief ADC Sample Sequencer 3 (SS3) Enable. - * @note User can set this bit to enable sample sequencer 3 (SS3). - * This bit will cleared by itself. - * @param ADCx ADC Instance - * @retval None. - */ -__STATIC_INLINE void md_adc_enable_ssen_ss3en(ADC_TypeDef *ADCx) -{ - SET_BIT(ADCx->SSEN, ADC_SSEN_SS3EN_MSK); -} - -/** - * @brief ADC Sample Sequencer 3 (SS3) Disable. - * @note Disable sample sequencer 3 (SS3). - * @param ADCx ADC Instance - * @retval None. - */ -__STATIC_INLINE void md_adc_disable_ssen_ss3en(ADC_TypeDef *ADCx) -{ - CLEAR_BIT(ADCx->SSEN, ADC_SSEN_SS3EN_MSK); -} - -/** - * @brief Check if ADC Sample Sequencer 3 (SS3) is enabled. - * @param ADCx ADC Instance - * @retval State of bit (1 or 0). - */ -__STATIC_INLINE uint32_t md_adc_is_enabled_ssen_ss3en(ADC_TypeDef *ADCx) -{ - return (READ_BIT(ADCx->SSEN, ADC_SSEN_SS3EN_MSK) == (ADC_SSEN_SS3EN_MSK)); -} - -/** - * @brief ADC Sample Sequencer 2 (SS2) Enable. - * @note User can set this bit to enable sample sequencer 2 (SS2). - * This bit will cleared by itself. - * @param ADCx ADC Instance - * @retval None. - */ -__STATIC_INLINE void md_adc_enable_ssen_ss2en(ADC_TypeDef *ADCx) -{ - SET_BIT(ADCx->SSEN, ADC_SSEN_SS2EN_MSK); -} - -/** - * @brief ADC Sample Sequencer 2 (SS2) Disable. - * @note Disable sample sequencer 2 (SS2). - * @param ADCx ADC Instance - * @retval None. - */ -__STATIC_INLINE void md_adc_disable_ssen_ss2en(ADC_TypeDef *ADCx) -{ - CLEAR_BIT(ADCx->SSEN, ADC_SSEN_SS2EN_MSK); -} - -/** - * @brief Check if ADC Sample Sequencer 2 (SS2) is enabled. - * @param ADCx ADC Instance - * @retval State of bit (1 or 0). - */ -__STATIC_INLINE uint32_t md_adc_is_enabled_ssen_ss2en(ADC_TypeDef *ADCx) -{ - return (READ_BIT(ADCx->SSEN, ADC_SSEN_SS2EN_MSK) == (ADC_SSEN_SS2EN_MSK)); -} - -/** - * @brief ADC Sample Sequencer 1 (SS1) Enable. - * @note User can set this bit to enable sample sequencer 1 (SS1). - * This bit will cleared by itself. - * @param ADCx ADC Instance - * @retval None. - */ -__STATIC_INLINE void md_adc_enable_ssen_ss1en(ADC_TypeDef *ADCx) -{ - SET_BIT(ADCx->SSEN, ADC_SSEN_SS1EN_MSK); -} - -/** - * @brief ADC Sample Sequencer 1 (SS1) Disable. - * @note Disable sample sequencer 1 (SS1). - * @param ADCx ADC Instance - * @retval None. - */ -__STATIC_INLINE void md_adc_disable_ssen_ss1en(ADC_TypeDef *ADCx) -{ - CLEAR_BIT(ADCx->SSEN, ADC_SSEN_SS1EN_MSK); -} - -/** - * @brief Check if ADC Sample Sequencer 1 (SS1) is enabled. - * @param ADCx ADC Instance - * @retval State of bit (1 or 0). - */ -__STATIC_INLINE uint32_t md_adc_is_enabled_ssen_ss1en(ADC_TypeDef *ADCx) -{ - return (READ_BIT(ADCx->SSEN, ADC_SSEN_SS1EN_MSK) == (ADC_SSEN_SS1EN_MSK)); -} - -/** - * @brief ADC Sample Sequencer 0 (SS0) Enable. - * @note User can set this bit to enable sequencer 0 (SS0). - * This bit will cleared by itself. - * @param ADCx ADC Instance - * @retval None. - */ -__STATIC_INLINE void md_adc_enable_ssen_ss0en(ADC_TypeDef *ADCx) -{ - SET_BIT(ADCx->SSEN, ADC_SSEN_SS0EN_MSK); -} - -/** - * @brief AADC Sample Sequencer 0 (SS0) Disable. - * @note Disable sample sequencer 0 (SS0). - * @param ADCx ADC Instance - * @retval None. - */ -__STATIC_INLINE void md_adc_disable_ssen_ss0en(ADC_TypeDef *ADCx) -{ - CLEAR_BIT(ADCx->SSEN, ADC_SSEN_SS0EN_MSK); -} - -/** - * @brief Check if ADC Sample Sequencer 0 (SS0) is enabled. - * @param ADCx ADC Instance - * @retval State of bit (1 or 0). - */ -__STATIC_INLINE uint32_t md_adc_is_enabled_ssen_ss0en(ADC_TypeDef *ADCx) -{ - return (READ_BIT(ADCx->SSEN, ADC_SSEN_SS0EN_MSK) == (ADC_SSEN_SS0EN_MSK)); -} - -/** - * @brief ADC Sample Sequencer 3 (SS3) Initiate. - * @note Triggers smapling on SS3 if the sequencer is enabled in the ADC_SSEN_SS3EN. - * This bit will cleared by itself. - * @param ADCx ADC Instance - * @retval None. - */ -__STATIC_INLINE void md_adc_set_swtri_ss3(ADC_TypeDef *ADCx) -{ - SET_BIT(ADCx->SWTRI, ADC_SWTRI_SS3_MSK); -} - -/** - * @brief ADC Sample Sequencer 2 (SS2) Initiate. - * @note Triggers smapling on SS2 if the sequencer is enabled in the ADC_SSEN_SS2EN. - * This bit will cleared by itself. - * @param ADCx ADC Instance - * @retval None. - */ -__STATIC_INLINE void md_adc_set_swtri_ss2(ADC_TypeDef *ADCx) -{ - SET_BIT(ADCx->SWTRI, ADC_SWTRI_SS2_MSK); -} - -/** - * @brief ADC Sample Sequencer 1 (SS1) Initiate. - * @note Triggers smapling on SS1 if the sequencer is enabled in the ADC_SSEN_SS1EN. - * This bit will cleared by itself. - * @param ADCx ADC Instance - * @retval None. - */ -__STATIC_INLINE void md_adc_set_swtri_ss1(ADC_TypeDef *ADCx) -{ - SET_BIT(ADCx->SWTRI, ADC_SWTRI_SS1_MSK); -} - -/** - * @brief ADC Sample Sequencer 0 (SS0) Initiate. - * @note Triggers smapling on SS0 if the sequencer is enabled in the ADC_SSEN_SS0EN. - * This bit will cleared by itself. - * @param ADCx ADC Instance - * @retval None. - */ -__STATIC_INLINE void md_adc_set_swtri_ss0(ADC_TypeDef *ADCx) -{ - SET_BIT(ADCx->SWTRI, ADC_SWTRI_SS0_MSK); -} - -/** - * @brief ADC Timeout Interrupt Enable. - * @note User can set this bit to enable timeout Interrupt function. - * @param ADCx ADC Instance - * @retval None. - */ -__STATIC_INLINE void md_adc_enable_ier_toie(ADC_TypeDef *ADCx) -{ - SET_BIT(ADCx->IER, ADC_IER_TOIE_MSK); -} - -/** - * @brief ADC Sample Sequencer 3 (SS3) Interrupt Enable. - * @note User can set this bit to enable sequencer 3 Interrupt function. - * @param ADCx ADC Instance - * @retval None. - */ -__STATIC_INLINE void md_adc_enable_ier_ss3ie(ADC_TypeDef *ADCx) -{ - SET_BIT(ADCx->IER, ADC_IER_SS3IE_MSK); -} - -/** - * @brief ADC Sample Sequencer 2 (SS2) Interrupt Enable. - * @note User can set this bit to enable sequencer 2 Interrupt function. - * @param ADCx ADC Instance - * @retval None. - */ -__STATIC_INLINE void md_adc_enable_ier_ss2ie(ADC_TypeDef *ADCx) -{ - SET_BIT(ADCx->IER, ADC_IER_SS2IE_MSK); -} - -/** - * @brief ADC Sample Sequencer 1 (SS1) Interrupt Enable. - * @note User can set this bit to enable sequencer 1 Interrupt function. - * @param ADCx ADC Instance - * @retval None. - */ -__STATIC_INLINE void md_adc_enable_ier_ss1ie(ADC_TypeDef *ADCx) -{ - SET_BIT(ADCx->IER, ADC_IER_SS1IE_MSK); -} - -/** - * @brief ADC Sample Sequencer 0 (SS0) Interrupt Enable. - * @note User can set this bit to enable sequencer 0 Interrupt function. - * @param ADCx ADC Instance - * @retval None. - */ -__STATIC_INLINE void md_adc_enable_ier_ss0ie(ADC_TypeDef *ADCx) -{ - SET_BIT(ADCx->IER, ADC_IER_SS0IE_MSK); -} - -/** - * @brief ADC Timeout Interrupt Disable. - * @note User can set this bit to disable timeout Interrupt function. - * @param ADCx ADC Instance - * @retval None. - */ -__STATIC_INLINE void md_adc_disable_idr_toid(ADC_TypeDef *ADCx) -{ - SET_BIT(ADCx->IDR, ADC_IDR_TOID_MSK); -} - -/** - * @brief ADC Sample Sequencer 3 (SS3) Interrupt Disable. - * @note User can set this bit to disable sequencer 3 Interrupt function. - * @param ADCx ADC Instance - * @retval None. - */ -__STATIC_INLINE void md_adc_disable_idr_ss3id(ADC_TypeDef *ADCx) -{ - SET_BIT(ADCx->IDR, ADC_IDR_SS3ID_MSK); -} - -/** - * @brief ADC Sample Sequencer 2 (SS2) Interrupt Disable. - * @note User can set this bit to disable sequencer 2 Interrupt function. - * @param ADCx ADC Instance - * @retval None. - */ -__STATIC_INLINE void md_adc_disable_idr_ss2id(ADC_TypeDef *ADCx) -{ - SET_BIT(ADCx->IDR, ADC_IDR_SS2ID_MSK); -} - -/** - * @brief ADC Sample Sequencer 1 (SS1) Interrupt Disable. - * @note User can set this bit to disable sequencer 1 Interrupt function. - * @param ADCx ADC Instance - * @retval None. - */ -__STATIC_INLINE void md_adc_disable_idr_ss1id(ADC_TypeDef *ADCx) -{ - SET_BIT(ADCx->IDR, ADC_IDR_SS1ID_MSK); -} - -/** - * @brief ADC Sample Sequencer 0 (SS0) Interrupt Disable. - * @note User can set this bit to disable sequencer 0 Interrupt function. - * @param ADCx ADC Instance - * @retval None. - */ -__STATIC_INLINE void md_adc_disable_idr_ss0id(ADC_TypeDef *ADCx) -{ - SET_BIT(ADCx->IDR, ADC_IDR_SS0ID_MSK); -} - -/** - * @brief Check if ADC Timeout Interrupt is Enabled. - * @param ADCx ADC Instance - * @retval State of bit (1 or 0). - */ -__STATIC_INLINE uint32_t md_adc_is_enabled_ivs_toivs(ADC_TypeDef *ADCx) -{ - return (READ_BIT(ADCx->IVS, ADC_IVS_TOIVS_MSK) == (ADC_IVS_TOIVS_MSK)); -} - -/** - * @brief Check if ADC Sample Sequencer 3 (SS3) Interrupt is Enabled. - * @param ADCx ADC Instance - * @retval State of bit (1 or 0). - */ -__STATIC_INLINE uint32_t md_adc_is_enabled_ivs_ss3ivs(ADC_TypeDef *ADCx) -{ - return (READ_BIT(ADCx->IVS, ADC_IVS_SS3IVS_MSK) == (ADC_IVS_SS3IVS_MSK)); -} - -/** - * @brief Check if ADC Sample Sequencer 2 (SS2) Interrupt is Enabled. - * @param ADCx ADC Instance - * @retval State of bit (1 or 0). - */ -__STATIC_INLINE uint32_t md_adc_is_enabled_ivs_ss2ivs(ADC_TypeDef *ADCx) -{ - return (READ_BIT(ADCx->IVS, ADC_IVS_SS2IVS_MSK) == (ADC_IVS_SS2IVS_MSK)); -} - -/** - * @brief Check if ADC Sample Sequencer 1 (SS1) Interrupt is Enabled. - * @param ADCx ADC Instance - * @retval State of bit (1 or 0). - */ -__STATIC_INLINE uint32_t md_adc_is_enabled_ivs_ss1ivs(ADC_TypeDef *ADCx) -{ - return (READ_BIT(ADCx->IVS, ADC_IVS_SS1IVS_MSK) == (ADC_IVS_SS1IVS_MSK)); -} - -/** - * @brief Check if ADC Sample Sequencer 0 (SS0) Interrupt is Enabled. - * @param ADCx ADC Instance. - * @retval State of bit (1 or 0). - */ -__STATIC_INLINE uint32_t md_adc_is_enabled_ivs_ss0ivs(ADC_TypeDef *ADCx) -{ - return (READ_BIT(ADCx->IVS, ADC_IVS_SS0IVS_MSK) == (ADC_IVS_SS0IVS_MSK)); -} - -/** - * @brief Check Timeout Raw Interrupt Flag Status. - * @param ADCx ADC Instance. - * @retval State of bit (1 or 0). - */ -__STATIC_INLINE uint32_t md_adc_is_active_flag_rif_torif(ADC_TypeDef *ADCx) -{ - return (READ_BIT(ADCx->RIF, ADC_RIF_TORIF_MSK) == (ADC_RIF_TORIF_MSK)); -} - -/** - * @brief Check ADC Sample Sequencer 3 (SS3) Raw Interrupt Flag Status. - * @param ADCx ADC Instance. - * @retval State of bit (1 or 0). - */ -__STATIC_INLINE uint32_t md_adc_is_active_flag_rif_ss3rif(ADC_TypeDef *ADCx) -{ - return (READ_BIT(ADCx->RIF, ADC_RIF_SS3RIF_MSK) == (ADC_RIF_SS3RIF_MSK)); -} - -/** - * @brief Check ADC Sample Sequencer 2 (SS2) Raw Interrupt Flag Status. - * @param ADCx ADC Instance. - * @retval State of bit (1 or 0). - */ -__STATIC_INLINE uint32_t md_adc_is_active_flag_rif_ss2rif(ADC_TypeDef *ADCx) -{ - return (READ_BIT(ADCx->RIF, ADC_RIF_SS2RIF_MSK) == (ADC_RIF_SS2RIF_MSK)); -} - -/** - * @brief Check ADC Sample Sequencer 1 (SS1) Raw Interrupt Flag Status. - * @param ADCx ADC Instance. - * @retval State of bit (1 or 0). - */ -__STATIC_INLINE uint32_t md_adc_is_active_flag_rif_ss1rif(ADC_TypeDef *ADCx) -{ - return (READ_BIT(ADCx->RIF, ADC_RIF_SS1RIF_MSK) == (ADC_RIF_SS1RIF_MSK)); -} - -/** - * @brief Check ADC Sample Sequencer 0 (SS0) Raw Interrupt Flag Status. - * @param ADCx ADC Instance. - * @retval State of bit (1 or 0). - */ -__STATIC_INLINE uint32_t md_adc_is_active_flag_rif_ss0rif(ADC_TypeDef *ADCx) -{ - return (READ_BIT(ADCx->RIF, ADC_RIF_SS0RIF_MSK) == (ADC_RIF_SS0RIF_MSK)); -} - -/** - * @brief Check Timeout Interrupt Flag Masked Status. - * @param ADCx ADC Instance. - * @retval State of bit (1 or 0). - */ -__STATIC_INLINE uint32_t md_adc_is_active_flag_ifm_torif(ADC_TypeDef *ADCx) -{ - return (READ_BIT(ADCx->IFM, ADC_IFM_TOIFM_MSK) == (ADC_IFM_TOIFM_MSK)); -} - -/** - * @brief Check ADC Sample Sequencer 3 (SS3) Interrupt Flag Masked Status. - * @param ADCx ADC Instance. - * @retval State of bit (1 or 0). - */ -__STATIC_INLINE uint32_t md_adc_is_active_flag_ifm_ss3rif(ADC_TypeDef *ADCx) -{ - return (READ_BIT(ADCx->IFM, ADC_IFM_SS3IFM_MSK) == (ADC_IFM_SS3IFM_MSK)); -} - -/** - * @brief Check ADC Sample Sequencer 2 (SS2) Interrupt Flag Masked Status. - * @param ADCx ADC Instance. - * @retval State of bit (1 or 0). - */ -__STATIC_INLINE uint32_t md_adc_is_active_flag_ifm_ss2rif(ADC_TypeDef *ADCx) -{ - return (READ_BIT(ADCx->IFM, ADC_IFM_SS2IFM_MSK) == (ADC_IFM_SS2IFM_MSK)); -} - -/** - * @brief Check ADC Sample Sequencer 1 (SS1) Interrupt Flag Masked Status. - * @param ADCx ADC Instance. - * @retval State of bit (1 or 0). - */ -__STATIC_INLINE uint32_t md_adc_is_active_flag_ifm_ss1rif(ADC_TypeDef *ADCx) -{ - return (READ_BIT(ADCx->IFM, ADC_IFM_SS1IFM_MSK) == (ADC_IFM_SS1IFM_MSK)); -} - -/** - * @brief Check ADC Sample Sequencer 0 (SS0) Interrupt Flag Masked Status. - * @param ADCx ADC Instance. - * @retval State of bit (1 or 0). - */ -__STATIC_INLINE uint32_t md_adc_is_active_flag_ifm_ss0rif(ADC_TypeDef *ADCx) -{ - return (READ_BIT(ADCx->IFM, ADC_IFM_SS0IFM_MSK) == (ADC_IFM_SS0IFM_MSK)); -} - -/** - * @brief ADC Timeout Interrupt Clear. - * @note User can set this bit to clear timeout interrupt status. - * @param ADCx ADC Instance - * @retval None. - */ -__STATIC_INLINE void md_uart_clear_flag_icr_toicr(ADC_TypeDef *ADCx) -{ - SET_BIT(ADCx->ICR, ADC_ICR_TOICR_MSK); -} - -/** - * @brief ADC Sample Sequencer 3 (SS3) Interrupt Clear. - * @note User can set this bit to clear SS3 interrupt status. - * @param ADCx ADC Instance. - * @retval None. - */ -__STATIC_INLINE void md_uart_clear_flag_icr_ss3icr(ADC_TypeDef *ADCx) -{ - SET_BIT(ADCx->ICR, ADC_ICR_SS3ICR_MSK); -} - -/** - * @brief ADC Sample Sequencer 2 (SS2) Interrupt Clear. - * @note User can set this bit to clear SS2 interrupt status. - * @param ADCx ADC Instance. - * @retval None. - */ -__STATIC_INLINE void md_uart_clear_flag_icr_ss2icr(ADC_TypeDef *ADCx) -{ - SET_BIT(ADCx->ICR, ADC_ICR_SS2ICR_MSK); -} - -/** - * @brief ADC Sample Sequencer 1 (SS1) Interrupt Clear. - * @note User can set this bit to clear SS1 interrupt status. - * @param ADCx ADC Instance. - * @retval None. - */ -__STATIC_INLINE void md_uart_clear_flag_icr_ss1icr(ADC_TypeDef *ADCx) -{ - SET_BIT(ADCx->ICR, ADC_ICR_SS1ICR_MSK); -} - -/** - * @brief ADC Sample Sequencer 0 (SS0) Interrupt Clear. - * @note User can set this bit to clear SS0 interrupt status. - * @param ADCx ADC Instance. - * @retval None. - */ -__STATIC_INLINE void md_uart_clear_flag_icr_ss0icr(ADC_TypeDef *ADCx) -{ - SET_BIT(ADCx->ICR, ADC_ICR_SS0ICR_MSK); -} - -/** - * @brief ADC SS3 DMA Function Enable. - * @note User can set this register to enable DMA function. - * For S3, if set when FIFO is not empty, DMA Single REQ will rise. - * @param UARTx UART Instance - * @retval None. - */ -__STATIC_INLINE void md_adc_enable_dma_ss3dmaen(ADC_TypeDef *ADCx) -{ - SET_BIT(ADCx->DMA, ADC_DMA_SS3_DMAEN_MSK); -} - -/** - * @brief ADC SS3 DMA Function Disable. - * @param UARTx UART Instance. - * @retval None. - */ -__STATIC_INLINE void md_adc_disable_dma_ss3dmaen(ADC_TypeDef *ADCx) -{ - CLEAR_BIT(ADCx->DMA, ADC_DMA_SS3_DMAEN_MSK); -} - -/** - * @brief Check if ADC SS3 DMA is enabled. - * @param ADCx ADC Instance. - * @retval State of bit (1 or 0). - */ -__STATIC_INLINE uint32_t md_adc_is_enabled_dma_ss3dmaen(ADC_TypeDef *ADCx) -{ - return (uint32_t)(READ_BIT(ADCx->DMA, ADC_DMA_SS3_DMAEN_MSK) == (ADC_DMA_SS3_DMAEN_MSK)); -} - -/** - * @brief ADC SS2 DMA Function Enable. - * @note User can set this register to enable DMA function. - * For S2, if set when FIFO is not empty, DMA Single REQ will rise. - * @param UARTx UART Instance. - * @retval None. - */ -__STATIC_INLINE void md_adc_enable_dma_ss2dmaen(ADC_TypeDef *ADCx) -{ - SET_BIT(ADCx->DMA, ADC_DMA_SS2_DMAEN_MSK); -} - -/** - * @brief ADC SS2 DMA Function Disable. - * @param UARTx UART Instance. - * @retval None. - */ -__STATIC_INLINE void md_adc_disable_dma_ss2dmaen(ADC_TypeDef *ADCx) -{ - CLEAR_BIT(ADCx->DMA, ADC_DMA_SS2_DMAEN_MSK); -} - -/** - * @brief Check if ADC SS2 DMA is enabled. - * @param ADCx ADC Instance. - * @retval State of bit (1 or 0). - */ -__STATIC_INLINE uint32_t md_adc_is_enabled_dma_ss2dmaen(ADC_TypeDef *ADCx) -{ - return (uint32_t)(READ_BIT(ADCx->DMA, ADC_DMA_SS2_DMAEN_MSK) == (ADC_DMA_SS2_DMAEN_MSK)); -} - -/** - * @brief ADC SS1 DMA Function Enable. - * @note User can set this register to enable DMA function. - * For S1, if set when FIFO is not empty, DMA Single REQ will rise. - * @param UARTx UART Instance. - * @retval None. - */ -__STATIC_INLINE void md_adc_enable_dma_ss1dmaen(ADC_TypeDef *ADCx) -{ - SET_BIT(ADCx->DMA, ADC_DMA_SS1_DMAEN_MSK); -} - -/** - * @brief ADC SS1 DMA Function Disable. - * @param UARTx UART Instance. - * @retval None. - */ -__STATIC_INLINE void md_adc_disable_dma_ss1dmaen(ADC_TypeDef *ADCx) -{ - CLEAR_BIT(ADCx->DMA, ADC_DMA_SS1_DMAEN_MSK); -} - -/** - * @brief Check if ADC SS1 DMA is enabled. - * @param ADCx ADC Instance. - * @retval State of bit (1 or 0). - */ -__STATIC_INLINE uint32_t md_adc_is_enabled_dma_ss1dmaen(ADC_TypeDef *ADCx) -{ - return (uint32_t)(READ_BIT(ADCx->DMA, ADC_DMA_SS1_DMAEN_MSK) == (ADC_DMA_SS1_DMAEN_MSK)); -} - -/** - * @brief ADC SS0 DMA Function Enable. - * @note User can set this register to enable DMA function. - * For S0, if set when FIFO is not empty, DMA Single REQ will rise. - * @param UARTx UART Instance. - * @retval None. - */ -__STATIC_INLINE void md_adc_enable_dma_ss0dmaen(ADC_TypeDef *ADCx) -{ - SET_BIT(ADCx->DMA, ADC_DMA_SS0_DMAEN_MSK); -} - -/** - * @brief ADC SS0 DMA Function Disable. - * @param UARTx UART Instance. - * @retval None. - */ -__STATIC_INLINE void md_adc_disable_dma_ss0dmaen(ADC_TypeDef *ADCx) -{ - CLEAR_BIT(ADCx->DMA, ADC_DMA_SS0_DMAEN_MSK); -} - -/** - * @brief Check if ADC SS3 DMA is enabled. - * @param ADCx ADC Instance. - * @retval State of bit (1 or 0). - */ -__STATIC_INLINE uint32_t md_adc_is_enabled_dma_ss0dmaen(ADC_TypeDef *ADCx) -{ - return (uint32_t)(READ_BIT(ADCx->DMA, ADC_DMA_SS0_DMAEN_MSK) == (ADC_DMA_SS0_DMAEN_MSK)); -} - -/** - * @brief Set SS0 Trigger Select. - * @note This field selects the trigger source for Sample Sequencer 0. - * @param ADCx ADC Instance. - * @param Sample sequencer trigger sources. - * @param This parameter can be one of the following values: - * @arg @ref MD_ADC_SS_CON_SEL_SW - * @arg @ref MD_ADC_SS_CON_SEL_BS16T1 - * @arg @ref MD_ADC_SS_CON_SEL_ALWAYS - * @arg @ref MD_ADC_SS_CON_SEL_GP32C4T1 - * @arg @ref MD_ADC_SS_CON_SEL_GP16C4T1 - * @arg @ref MD_ADC_SS_CON_SEL_GP16C4T2 - * @arg @ref MD_ADC_SS_CON_SEL_GP16C4T3 - * @arg @ref MD_ADC_SS_CON_SEL_GP32C4T1 - * @arg @ref MD_ADC_SS_CON_SEL_GP16C2T1 - * @arg @ref MD_ADC_SS_CON_SEL_GP16C2T2 - * @arg @ref MD_ADC_SS_CON_SEL_GP16C2T3 - * @arg @ref MD_ADC_SS_CON_SEL_GP32C4T1 - * @arg @ref MD_ADC_SS_CON_SEL_GP16C2T4 - * @arg @ref MD_ADC_SS_CON_SEL_AD16C4T1 - * @arg @ref MD_ADC_SS_CON_SEL_GPIO - * @arg @ref MD_ADC_SS_CON_SEL_CMP0 - * @arg @ref MD_ADC_SS_CON_SEL_CMP1 - * @arg @ref MD_ADC_SS_CON_SEL_CMP2 - * @arg @ref MD_ADC_SS_CON_SEL_CMP3 - * @retval None - */ -__STATIC_INLINE void md_adc_set_ss0_con_sel(ADC_TypeDef *ADCx, uint32_t TrigSource) -{ - MODIFY_REG(ADCx->SS0_CON, ADC_SS0_CON_SEL_MSK, TrigSource<SS0_CON, ADC_SS0_CON_SEL_MSK)>>ADC_SS0_CON_SEL_POSS); -} - -/** - * @brief Set ADC Sample Sequencer 0 (SS0) Trigger Type select. - * @note User can set this bit to select the type of trigger. - * @param Sample sequencer trigger types. - * @param This parameter can be one of the following values: - * @arg @ref MD_ADC_SS_CON_TYP_EDGE - * @arg @ref MD_ADC_SS_COM_TYP_LEVEL - * @retval None - */ -__STATIC_INLINE void md_adc_set_ss0_con_type(ADC_TypeDef *ADCx, uint32_t TrigType) -{ - MODIFY_REG(ADCx->SS0_CON, ADC_SS0_CON_TYP_MSK, TrigType<SS0_CON, ADC_SS0_CON_TYP_MSK)>>ADC_SS0_CON_TYP_POS); -} - -/** - * @brief Set ADC Sample Sequencer 0 (SS0) Priority. - * @note This field contains a binary-encoded value specifying the - * priority encoding of SS0. The prioriteies assigned to the - * sequencers must be uniquely mapped. - * @param ADCx ADC Instance. - * @param Sample sequencer trigger priorities. - * @param This parameter can be one of the following values: - * @arg @ref MD_ADC_SS0_CON_PRI_HIGHEST - * @arg @ref MD_ADC_SS0_CON_PRI_SECOND - * @arg @ref MD_ADC_SS0_CON_PRI_THIRD - * @arg @ref MD_ADC_SS0_CON_PRI_LOWEST - * @retval None - */ -__STATIC_INLINE void md_adc_set_ss0_con_pri(ADC_TypeDef *ADCx, uint32_t priority) -{ - MODIFY_REG(ADCx->SS0_CON, ADC_SS0_CON_PRI_MSK, priority<SS0_CON, ADC_SS0_CON_PRI_MSK)>>ADC_SS0_CON_PRI_POSS); -} - -/** - * @brief Enable One Shot Trigger Mode. - * @note When set HIGH, each trigger will only sample once and use one slot in FIFO. - * @param ADCx ADC Instance. - * @retval None - */ -__STATIC_INLINE void md_adc_enable_ss0_con_one(ADC_TypeDef *adcx) -{ - SET_BIT(adcx->SS0_CON, ADC_SS0_CON_ONE_MSK); -} - -/** - * @brief Disable One Shot Trigger Mode. - * @param ADCx ADC Instance. - * @retval None - */ -__STATIC_INLINE void md_adc_disable_ss0_con_one(ADC_TypeDef *adcx) -{ - CLEAR_BIT(adcx->SS0_CON, ADC_SS0_CON_ONE_MSK); -} - -/** - * @brief Set 8th Sample Input Select. - * @note User can set this register to select which channel will be - * sampled. For example, a value of n indicates the input is - * channel n. - * @param ADCx ADC Instance - * @param ADIN Pin: - * @arg @ref MD_ADC_SS_MUX_ADIN15 - * @arg @ref MD_ADC_SS_MUX_ADIN14 - * @arg @ref MD_ADC_SS_MUX_ADIN13 - * @arg @ref MD_ADC_SS_MUX_ADIN12 - * @arg @ref MD_ADC_SS_MUX_ADIN11 - * @arg @ref MD_ADC_SS_MUX_ADIN10 - * @arg @ref MD_ADC_SS_MUX_ADIN9 - * @arg @ref MD_ADC_SS_MUX_ADIN8 - * @arg @ref MD_ADC_SS_MUX_ADIN7 - * @arg @ref MD_ADC_SS_MUX_ADIN6 - * @arg @ref MD_ADC_SS_MUX_ADIN5 - * @arg @ref MD_ADC_SS_MUX_ADIN4 - * @arg @ref MD_ADC_SS_MUX_ADIN3 - * @arg @ref MD_ADC_SS_MUX_ADIN2 - * @arg @ref MD_ADC_SS_MUX_ADIN1 - * @arg @ref MD_ADC_SS_MUX_ADIN0 - */ -__STATIC_INLINE void md_adc_set_ss0_mux0_mux7(ADC_TypeDef *ADCx, uint32_t AdinPin) -{ - MODIFY_REG(ADCx->SS0_MUX0, ADC_SS0_MUX0_MUX7_MSK, AdinPin<SS0_MUX0, ADC_SS0_MUX0_MUX7_MSK)>>ADC_SS0_MUX0_MUX7_POSS); -} - -/** - * @brief Set 7th Sample Input Select. - * @note User can set this register to select which channel will be - * sampled. For example, a value of n indicates the input is - * channel n. - * @param ADCx ADC Instance - * @param ADIN Pin: - * @arg @ref MD_ADC_SS_MUX_ADIN15 - * @arg @ref MD_ADC_SS_MUX_ADIN14 - * @arg @ref MD_ADC_SS_MUX_ADIN13 - * @arg @ref MD_ADC_SS_MUX_ADIN12 - * @arg @ref MD_ADC_SS_MUX_ADIN11 - * @arg @ref MD_ADC_SS_MUX_ADIN10 - * @arg @ref MD_ADC_SS_MUX_ADIN9 - * @arg @ref MD_ADC_SS_MUX_ADIN8 - * @arg @ref MD_ADC_SS_MUX_ADIN7 - * @arg @ref MD_ADC_SS_MUX_ADIN6 - * @arg @ref MD_ADC_SS_MUX_ADIN5 - * @arg @ref MD_ADC_SS_MUX_ADIN4 - * @arg @ref MD_ADC_SS_MUX_ADIN3 - * @arg @ref MD_ADC_SS_MUX_ADIN2 - * @arg @ref MD_ADC_SS_MUX_ADIN1 - * @arg @ref MD_ADC_SS_MUX_ADIN0 - */ -__STATIC_INLINE void md_adc_set_ss0_mux0_mux6(ADC_TypeDef *ADCx, uint32_t AdinPin) -{ - MODIFY_REG(ADCx->SS0_MUX0, ADC_SS0_MUX0_MUX6_MSK, AdinPin<SS0_MUX0, ADC_SS0_MUX0_MUX6_MSK)>>ADC_SS0_MUX0_MUX6_POSS); -} - -/** - * @brief Set 6th Sample Input Select. - * @note User can set this register to select which channel will be - * sampled. For example, a value of n indicates the input is - * channel n. - * @param ADCx ADC Instance - * @param ADIN Pin: - * @arg @ref MD_ADC_SS_MUX_ADIN15 - * @arg @ref MD_ADC_SS_MUX_ADIN14 - * @arg @ref MD_ADC_SS_MUX_ADIN13 - * @arg @ref MD_ADC_SS_MUX_ADIN12 - * @arg @ref MD_ADC_SS_MUX_ADIN11 - * @arg @ref MD_ADC_SS_MUX_ADIN10 - * @arg @ref MD_ADC_SS_MUX_ADIN9 - * @arg @ref MD_ADC_SS_MUX_ADIN8 - * @arg @ref MD_ADC_SS_MUX_ADIN7 - * @arg @ref MD_ADC_SS_MUX_ADIN6 - * @arg @ref MD_ADC_SS_MUX_ADIN5 - * @arg @ref MD_ADC_SS_MUX_ADIN4 - * @arg @ref MD_ADC_SS_MUX_ADIN3 - * @arg @ref MD_ADC_SS_MUX_ADIN2 - * @arg @ref MD_ADC_SS_MUX_ADIN1 - * @arg @ref MD_ADC_SS_MUX_ADIN0 - */ -__STATIC_INLINE void md_adc_set_ss0_mux0_mux5(ADC_TypeDef *ADCx, uint32_t AdinPin) -{ - MODIFY_REG(ADCx->SS0_MUX0, ADC_SS0_MUX0_MUX5_MSK, AdinPin<SS0_MUX0, ADC_SS0_MUX0_MUX5_MSK)>>ADC_SS0_MUX0_MUX5_POSS); -} - -/** - * @brief Set 5th Sample Input Select. - * @note User can set this register to select which channel will be - * sampled. For example, a value of n indicates the input is - * channel n. - * @param ADCx ADC Instance - * @param ADIN Pin: - * @arg @ref MD_ADC_SS_MUX_ADIN15 - * @arg @ref MD_ADC_SS_MUX_ADIN14 - * @arg @ref MD_ADC_SS_MUX_ADIN13 - * @arg @ref MD_ADC_SS_MUX_ADIN12 - * @arg @ref MD_ADC_SS_MUX_ADIN11 - * @arg @ref MD_ADC_SS_MUX_ADIN10 - * @arg @ref MD_ADC_SS_MUX_ADIN9 - * @arg @ref MD_ADC_SS_MUX_ADIN8 - * @arg @ref MD_ADC_SS_MUX_ADIN7 - * @arg @ref MD_ADC_SS_MUX_ADIN6 - * @arg @ref MD_ADC_SS_MUX_ADIN5 - * @arg @ref MD_ADC_SS_MUX_ADIN4 - * @arg @ref MD_ADC_SS_MUX_ADIN3 - * @arg @ref MD_ADC_SS_MUX_ADIN2 - * @arg @ref MD_ADC_SS_MUX_ADIN1 - * @arg @ref MD_ADC_SS_MUX_ADIN0 - */ -__STATIC_INLINE void md_adc_set_ss0_mux0_mux4(ADC_TypeDef *ADCx, uint32_t AdinPin) -{ - MODIFY_REG(ADCx->SS0_MUX0, ADC_SS0_MUX0_MUX4_MSK, AdinPin<SS0_MUX0, ADC_SS0_MUX0_MUX4_MSK)>>ADC_SS0_MUX0_MUX4_POSS); -} - -/** - * @brief Set 4th Sample Input Select. - * @note User can set this register to select which channel will be - * sampled. For example, a value of n indicates the input is - * channel n. - * @param ADCx ADC Instance - * @param ADIN Pin: - * @arg @ref MD_ADC_SS_MUX_ADIN15 - * @arg @ref MD_ADC_SS_MUX_ADIN14 - * @arg @ref MD_ADC_SS_MUX_ADIN13 - * @arg @ref MD_ADC_SS_MUX_ADIN12 - * @arg @ref MD_ADC_SS_MUX_ADIN11 - * @arg @ref MD_ADC_SS_MUX_ADIN10 - * @arg @ref MD_ADC_SS_MUX_ADIN9 - * @arg @ref MD_ADC_SS_MUX_ADIN8 - * @arg @ref MD_ADC_SS_MUX_ADIN7 - * @arg @ref MD_ADC_SS_MUX_ADIN6 - * @arg @ref MD_ADC_SS_MUX_ADIN5 - * @arg @ref MD_ADC_SS_MUX_ADIN4 - * @arg @ref MD_ADC_SS_MUX_ADIN3 - * @arg @ref MD_ADC_SS_MUX_ADIN2 - * @arg @ref MD_ADC_SS_MUX_ADIN1 - * @arg @ref MD_ADC_SS_MUX_ADIN0 - */ -__STATIC_INLINE void md_adc_set_ss0_mux0_mux3(ADC_TypeDef *ADCx, uint32_t AdinPin) -{ - MODIFY_REG(ADCx->SS0_MUX0, ADC_SS0_MUX0_MUX3_MSK, AdinPin<SS0_MUX0, ADC_SS0_MUX0_MUX3_MSK)>>ADC_SS0_MUX0_MUX3_POSS); -} - -/** - * @brief Set 3rd Sample Input Select. - * @note User can set this register to select which channel will be - * sampled. For example, a value of n indicates the input is - * channel n. - * @param ADCx ADC Instance - * @param ADIN Pin: - * @arg @ref MD_ADC_SS_MUX_ADIN15 - * @arg @ref MD_ADC_SS_MUX_ADIN14 - * @arg @ref MD_ADC_SS_MUX_ADIN13 - * @arg @ref MD_ADC_SS_MUX_ADIN12 - * @arg @ref MD_ADC_SS_MUX_ADIN11 - * @arg @ref MD_ADC_SS_MUX_ADIN10 - * @arg @ref MD_ADC_SS_MUX_ADIN9 - * @arg @ref MD_ADC_SS_MUX_ADIN8 - * @arg @ref MD_ADC_SS_MUX_ADIN7 - * @arg @ref MD_ADC_SS_MUX_ADIN6 - * @arg @ref MD_ADC_SS_MUX_ADIN5 - * @arg @ref MD_ADC_SS_MUX_ADIN4 - * @arg @ref MD_ADC_SS_MUX_ADIN3 - * @arg @ref MD_ADC_SS_MUX_ADIN2 - * @arg @ref MD_ADC_SS_MUX_ADIN1 - * @arg @ref MD_ADC_SS_MUX_ADIN0 - */ -__STATIC_INLINE void md_adc_set_ss0_mux0_mux2(ADC_TypeDef *ADCx, uint32_t AdinPin) -{ - MODIFY_REG(ADCx->SS0_MUX0, ADC_SS0_MUX0_MUX2_MSK, AdinPin<SS0_MUX0, ADC_SS0_MUX0_MUX2_MSK)>>ADC_SS0_MUX0_MUX2_POSS); -} - -/** - * @brief Set 2nd Sample Input Select. - * @note User can set this register to select which channel will be - * sampled. For example, a value of n indicates the input is - * channel n. - * @param ADCx ADC Instance - * @param ADIN Pin: - * @arg @ref MD_ADC_SS_MUX_ADIN15 - * @arg @ref MD_ADC_SS_MUX_ADIN14 - * @arg @ref MD_ADC_SS_MUX_ADIN13 - * @arg @ref MD_ADC_SS_MUX_ADIN12 - * @arg @ref MD_ADC_SS_MUX_ADIN11 - * @arg @ref MD_ADC_SS_MUX_ADIN10 - * @arg @ref MD_ADC_SS_MUX_ADIN9 - * @arg @ref MD_ADC_SS_MUX_ADIN8 - * @arg @ref MD_ADC_SS_MUX_ADIN7 - * @arg @ref MD_ADC_SS_MUX_ADIN6 - * @arg @ref MD_ADC_SS_MUX_ADIN5 - * @arg @ref MD_ADC_SS_MUX_ADIN4 - * @arg @ref MD_ADC_SS_MUX_ADIN3 - * @arg @ref MD_ADC_SS_MUX_ADIN2 - * @arg @ref MD_ADC_SS_MUX_ADIN1 - * @arg @ref MD_ADC_SS_MUX_ADIN0 - */ -__STATIC_INLINE void md_adc_set_ss0_mux0_mux1(ADC_TypeDef *ADCx, uint32_t AdinPin) -{ - MODIFY_REG(ADCx->SS0_MUX0, ADC_SS0_MUX0_MUX1_MSK, AdinPin<SS0_MUX0, ADC_SS0_MUX0_MUX1_MSK)>>ADC_SS0_MUX0_MUX1_POSS); -} - -/** - * @brief Set 1st Sample Input Select. - * @note User can set this register to select which channel will be - * sampled. For example, a value of n indicates the input is - * channel n. - * @param ADCx ADC Instance - * @param ADIN Pin: - * @arg @ref MD_ADC_SS_MUX_ADIN15 - * @arg @ref MD_ADC_SS_MUX_ADIN14 - * @arg @ref MD_ADC_SS_MUX_ADIN13 - * @arg @ref MD_ADC_SS_MUX_ADIN12 - * @arg @ref MD_ADC_SS_MUX_ADIN11 - * @arg @ref MD_ADC_SS_MUX_ADIN10 - * @arg @ref MD_ADC_SS_MUX_ADIN9 - * @arg @ref MD_ADC_SS_MUX_ADIN8 - * @arg @ref MD_ADC_SS_MUX_ADIN7 - * @arg @ref MD_ADC_SS_MUX_ADIN6 - * @arg @ref MD_ADC_SS_MUX_ADIN5 - * @arg @ref MD_ADC_SS_MUX_ADIN4 - * @arg @ref MD_ADC_SS_MUX_ADIN3 - * @arg @ref MD_ADC_SS_MUX_ADIN2 - * @arg @ref MD_ADC_SS_MUX_ADIN1 - * @arg @ref MD_ADC_SS_MUX_ADIN0 - */ -__STATIC_INLINE void md_adc_set_ss0_mux0_mux0(ADC_TypeDef *ADCx, uint32_t AdinPin) -{ - MODIFY_REG(ADCx->SS0_MUX0, ADC_SS0_MUX0_MUX0_MSK, AdinPin<SS0_MUX0, ADC_SS0_MUX0_MUX0_MSK)>>ADC_SS0_MUX0_MUX0_POSS); -} - -/** - * @brief Set ADC channels MUX 0~7. - * @note Set ADC SS0_MUX0 register. - * @note Mapping ADINx to ADC channels 0~7. - - * @param ADC Channel - * @param MUX Register - * @retval None - */ -__STATIC_INLINE void md_adc_set_ss0_mux0(ADC_TypeDef *ADCx, uint32_t RegValue) -{ - WRITE_REG(ADCx->SS0_MUX0, RegValue); -} - -/** - * @brief Get ADC channels MUX 0~7. - * @note Get ADC SS0_MUX0 register. - * @param ADCx ADC Instance - * @retval SS0_MUX0 Register Value - */ -__STATIC_INLINE uint32_t md_adc_get_ss0_mux0(ADC_TypeDef *ADCx) -{ - return READ_REG(ADCx->SS0_MUX0); -} - -/** - * @brief Set 16th Sample Input Select. - * @note User can set this register to select which channel will be - * sampled. For example, a value of n indicates the input is - * channel n. - * @param ADCx ADC Instance - * @param ADIN Pin: - * @arg @ref MD_ADC_SS_MUX_ADIN15 - * @arg @ref MD_ADC_SS_MUX_ADIN14 - * @arg @ref MD_ADC_SS_MUX_ADIN13 - * @arg @ref MD_ADC_SS_MUX_ADIN12 - * @arg @ref MD_ADC_SS_MUX_ADIN11 - * @arg @ref MD_ADC_SS_MUX_ADIN10 - * @arg @ref MD_ADC_SS_MUX_ADIN9 - * @arg @ref MD_ADC_SS_MUX_ADIN8 - * @arg @ref MD_ADC_SS_MUX_ADIN7 - * @arg @ref MD_ADC_SS_MUX_ADIN6 - * @arg @ref MD_ADC_SS_MUX_ADIN5 - * @arg @ref MD_ADC_SS_MUX_ADIN4 - * @arg @ref MD_ADC_SS_MUX_ADIN3 - * @arg @ref MD_ADC_SS_MUX_ADIN2 - * @arg @ref MD_ADC_SS_MUX_ADIN1 - * @arg @ref MD_ADC_SS_MUX_ADIN0 - */ -__STATIC_INLINE void md_adc_set_ss0_mux1_mux15(ADC_TypeDef *ADCx, uint32_t AdinPin) -{ - MODIFY_REG(ADCx->SS0_MUX1, ADC_SS0_MUX1_MUX15_MSK, AdinPin<SS0_MUX0, ADC_SS0_MUX1_MUX15_MSK)>>ADC_SS0_MUX1_MUX15_POSS); -} - -/** - * @brief Set 15th Sample Input Select. - * @note User can set this register to select which channel will be - * sampled. For example, a value of n indicates the input is - * channel n. - * @param ADCx ADC Instance - * @param ADIN Pin: - * @arg @ref MD_ADC_SS_MUX_ADIN15 - * @arg @ref MD_ADC_SS_MUX_ADIN14 - * @arg @ref MD_ADC_SS_MUX_ADIN13 - * @arg @ref MD_ADC_SS_MUX_ADIN12 - * @arg @ref MD_ADC_SS_MUX_ADIN11 - * @arg @ref MD_ADC_SS_MUX_ADIN10 - * @arg @ref MD_ADC_SS_MUX_ADIN9 - * @arg @ref MD_ADC_SS_MUX_ADIN8 - * @arg @ref MD_ADC_SS_MUX_ADIN7 - * @arg @ref MD_ADC_SS_MUX_ADIN6 - * @arg @ref MD_ADC_SS_MUX_ADIN5 - * @arg @ref MD_ADC_SS_MUX_ADIN4 - * @arg @ref MD_ADC_SS_MUX_ADIN3 - * @arg @ref MD_ADC_SS_MUX_ADIN2 - * @arg @ref MD_ADC_SS_MUX_ADIN1 - * @arg @ref MD_ADC_SS_MUX_ADIN0 - */ -__STATIC_INLINE void md_adc_set_ss0_mux1_mux14(ADC_TypeDef *ADCx, uint32_t AdinPin) -{ - MODIFY_REG(ADCx->SS0_MUX1, ADC_SS0_MUX1_MUX14_MSK, AdinPin<SS0_MUX0, ADC_SS0_MUX1_MUX14_MSK)>>ADC_SS0_MUX1_MUX14_POSS); -} - -/** - * @brief Set 14th Sample Input Select. - * @note User can set this register to select which channel will be - * sampled. For example, a value of n indicates the input is - * channel n. - * @param ADCx ADC Instance - * @param ADIN Pin: - * @arg @ref MD_ADC_SS_MUX_ADIN15 - * @arg @ref MD_ADC_SS_MUX_ADIN14 - * @arg @ref MD_ADC_SS_MUX_ADIN13 - * @arg @ref MD_ADC_SS_MUX_ADIN12 - * @arg @ref MD_ADC_SS_MUX_ADIN11 - * @arg @ref MD_ADC_SS_MUX_ADIN10 - * @arg @ref MD_ADC_SS_MUX_ADIN9 - * @arg @ref MD_ADC_SS_MUX_ADIN8 - * @arg @ref MD_ADC_SS_MUX_ADIN7 - * @arg @ref MD_ADC_SS_MUX_ADIN6 - * @arg @ref MD_ADC_SS_MUX_ADIN5 - * @arg @ref MD_ADC_SS_MUX_ADIN4 - * @arg @ref MD_ADC_SS_MUX_ADIN3 - * @arg @ref MD_ADC_SS_MUX_ADIN2 - * @arg @ref MD_ADC_SS_MUX_ADIN1 - * @arg @ref MD_ADC_SS_MUX_ADIN0 - */ -__STATIC_INLINE void md_adc_set_ss0_mux1_mux13(ADC_TypeDef *ADCx, uint32_t AdinPin) -{ - MODIFY_REG(ADCx->SS0_MUX1, ADC_SS0_MUX1_MUX13_MSK, AdinPin<SS0_MUX0, ADC_SS0_MUX1_MUX13_MSK)>>ADC_SS0_MUX1_MUX13_POSS); -} - -/** - * @brief Set 13th Sample Input Select. - * @note User can set this register to select which channel will be - * sampled. For example, a value of n indicates the input is - * channel n. - * @param ADCx ADC Instance - * @param ADIN Pin: - * @arg @ref MD_ADC_SS_MUX_ADIN15 - * @arg @ref MD_ADC_SS_MUX_ADIN14 - * @arg @ref MD_ADC_SS_MUX_ADIN13 - * @arg @ref MD_ADC_SS_MUX_ADIN12 - * @arg @ref MD_ADC_SS_MUX_ADIN11 - * @arg @ref MD_ADC_SS_MUX_ADIN10 - * @arg @ref MD_ADC_SS_MUX_ADIN9 - * @arg @ref MD_ADC_SS_MUX_ADIN8 - * @arg @ref MD_ADC_SS_MUX_ADIN7 - * @arg @ref MD_ADC_SS_MUX_ADIN6 - * @arg @ref MD_ADC_SS_MUX_ADIN5 - * @arg @ref MD_ADC_SS_MUX_ADIN4 - * @arg @ref MD_ADC_SS_MUX_ADIN3 - * @arg @ref MD_ADC_SS_MUX_ADIN2 - * @arg @ref MD_ADC_SS_MUX_ADIN1 - * @arg @ref MD_ADC_SS_MUX_ADIN0 - */ -__STATIC_INLINE void md_adc_set_ss0_mux1_mux12(ADC_TypeDef *ADCx, uint32_t AdinPin) -{ - MODIFY_REG(ADCx->SS0_MUX1, ADC_SS0_MUX1_MUX12_MSK, AdinPin<SS0_MUX0, ADC_SS0_MUX1_MUX12_MSK)>>ADC_SS0_MUX1_MUX12_POSS); -} - -/** - * @brief Set 12th Sample Input Select. - * @note User can set this register to select which channel will be - * sampled. For example, a value of n indicates the input is - * channel n. - * @param ADCx ADC Instance - * @param ADIN Pin: - * @arg @ref MD_ADC_SS_MUX_ADIN15 - * @arg @ref MD_ADC_SS_MUX_ADIN14 - * @arg @ref MD_ADC_SS_MUX_ADIN13 - * @arg @ref MD_ADC_SS_MUX_ADIN12 - * @arg @ref MD_ADC_SS_MUX_ADIN11 - * @arg @ref MD_ADC_SS_MUX_ADIN10 - * @arg @ref MD_ADC_SS_MUX_ADIN9 - * @arg @ref MD_ADC_SS_MUX_ADIN8 - * @arg @ref MD_ADC_SS_MUX_ADIN7 - * @arg @ref MD_ADC_SS_MUX_ADIN6 - * @arg @ref MD_ADC_SS_MUX_ADIN5 - * @arg @ref MD_ADC_SS_MUX_ADIN4 - * @arg @ref MD_ADC_SS_MUX_ADIN3 - * @arg @ref MD_ADC_SS_MUX_ADIN2 - * @arg @ref MD_ADC_SS_MUX_ADIN1 - * @arg @ref MD_ADC_SS_MUX_ADIN0 - */ -__STATIC_INLINE void md_adc_set_ss0_mux1_mux11(ADC_TypeDef *ADCx, uint32_t AdinPin) -{ - MODIFY_REG(ADCx->SS0_MUX1, ADC_SS0_MUX1_MUX11_MSK, AdinPin<SS0_MUX0, ADC_SS0_MUX1_MUX11_MSK)>>ADC_SS0_MUX1_MUX11_POSS); -} - -/** - * @brief Set 11th Sample Input Select. - * @note User can set this register to select which channel will be - * sampled. For example, a value of n indicates the input is - * channel n. - * @param ADCx ADC Instance - * @param ADIN Pin: - * @arg @ref MD_ADC_SS_MUX_ADIN15 - * @arg @ref MD_ADC_SS_MUX_ADIN14 - * @arg @ref MD_ADC_SS_MUX_ADIN13 - * @arg @ref MD_ADC_SS_MUX_ADIN12 - * @arg @ref MD_ADC_SS_MUX_ADIN11 - * @arg @ref MD_ADC_SS_MUX_ADIN10 - * @arg @ref MD_ADC_SS_MUX_ADIN9 - * @arg @ref MD_ADC_SS_MUX_ADIN8 - * @arg @ref MD_ADC_SS_MUX_ADIN7 - * @arg @ref MD_ADC_SS_MUX_ADIN6 - * @arg @ref MD_ADC_SS_MUX_ADIN5 - * @arg @ref MD_ADC_SS_MUX_ADIN4 - * @arg @ref MD_ADC_SS_MUX_ADIN3 - * @arg @ref MD_ADC_SS_MUX_ADIN2 - * @arg @ref MD_ADC_SS_MUX_ADIN1 - * @arg @ref MD_ADC_SS_MUX_ADIN0 - */ -__STATIC_INLINE void md_adc_set_ss0_mux1_mux10(ADC_TypeDef *ADCx, uint32_t AdinPin) -{ - MODIFY_REG(ADCx->SS0_MUX1, ADC_SS0_MUX1_MUX10_MSK, AdinPin<SS0_MUX0, ADC_SS0_MUX1_MUX10_MSK)>>ADC_SS0_MUX1_MUX10_POSS); -} - -/** - * @brief Set 10th Sample Input Select. - * @note User can set this register to select which channel will be - * sampled. For example, a value of n indicates the input is - * channel n. - * @param ADCx ADC Instance - * @param ADIN Pin: - * @arg @ref MD_ADC_SS_MUX_ADIN15 - * @arg @ref MD_ADC_SS_MUX_ADIN14 - * @arg @ref MD_ADC_SS_MUX_ADIN13 - * @arg @ref MD_ADC_SS_MUX_ADIN12 - * @arg @ref MD_ADC_SS_MUX_ADIN11 - * @arg @ref MD_ADC_SS_MUX_ADIN10 - * @arg @ref MD_ADC_SS_MUX_ADIN9 - * @arg @ref MD_ADC_SS_MUX_ADIN8 - * @arg @ref MD_ADC_SS_MUX_ADIN7 - * @arg @ref MD_ADC_SS_MUX_ADIN6 - * @arg @ref MD_ADC_SS_MUX_ADIN5 - * @arg @ref MD_ADC_SS_MUX_ADIN4 - * @arg @ref MD_ADC_SS_MUX_ADIN3 - * @arg @ref MD_ADC_SS_MUX_ADIN2 - * @arg @ref MD_ADC_SS_MUX_ADIN1 - * @arg @ref MD_ADC_SS_MUX_ADIN0 - */ -__STATIC_INLINE void md_adc_set_ss0_mux1_mux9(ADC_TypeDef *ADCx, uint32_t AdinPin) -{ - MODIFY_REG(ADCx->SS0_MUX1, ADC_SS0_MUX1_MUX9_MSK, AdinPin<SS0_MUX0, ADC_SS0_MUX1_MUX9_MSK)>>ADC_SS0_MUX1_MUX9_POSS); -} - -/** - * @brief Set 9th Sample Input Select. - * @note User can set this register to select which channel will be - * sampled. For example, a value of n indicates the input is - * channel n. - * @param ADCx ADC Instance - * @param ADIN Pin: - * @arg @ref MD_ADC_SS_MUX_ADIN15 - * @arg @ref MD_ADC_SS_MUX_ADIN14 - * @arg @ref MD_ADC_SS_MUX_ADIN13 - * @arg @ref MD_ADC_SS_MUX_ADIN12 - * @arg @ref MD_ADC_SS_MUX_ADIN11 - * @arg @ref MD_ADC_SS_MUX_ADIN10 - * @arg @ref MD_ADC_SS_MUX_ADIN9 - * @arg @ref MD_ADC_SS_MUX_ADIN8 - * @arg @ref MD_ADC_SS_MUX_ADIN7 - * @arg @ref MD_ADC_SS_MUX_ADIN6 - * @arg @ref MD_ADC_SS_MUX_ADIN5 - * @arg @ref MD_ADC_SS_MUX_ADIN4 - * @arg @ref MD_ADC_SS_MUX_ADIN3 - * @arg @ref MD_ADC_SS_MUX_ADIN2 - * @arg @ref MD_ADC_SS_MUX_ADIN1 - * @arg @ref MD_ADC_SS_MUX_ADIN0 - */ -__STATIC_INLINE void md_adc_set_ss0_mux1_mux8(ADC_TypeDef *ADCx, uint32_t AdinPin) -{ - MODIFY_REG(ADCx->SS0_MUX1, ADC_SS0_MUX1_MUX8_MSK, AdinPin<SS0_MUX0, ADC_SS0_MUX1_MUX8_MSK)>>ADC_SS0_MUX1_MUX8_POSS); -} - -/** - * @brief Set ADC channels MUX 8~15. - * @note Set SS0_MUX1 register for channels 8~15. - * @param ADCx ADC Instance. - * @param SS0 MUX1 Register. - * @retval None - */ -__STATIC_INLINE void md_adc_set_ss0_mux1(ADC_TypeDef *ADCx, uint32_t RegValue) -{ - WRITE_REG(ADCx->SS0_MUX1, RegValue); -} - -/** - * @brief Get ADC channels MUX 8~15. - * @note Get SS0_MUX1 register for channels 8~15. - * @param ADCx ADC Instance. - * @retval SS0 MUX1 Register. - */ -__STATIC_INLINE uint32_t md_adc_get_ss0_mux1(ADC_TypeDef *ADCx) -{ - return READ_REG(ADCx->SS0_MUX1); -} - -/** - * @brief 16th Sample Interrupt Enable. - * @param ADCx ADC Instance. - * @retval None. - */ -__STATIC_INLINE void md_adc_enable_ss0_end_ie15(ADC_TypeDef *ADCx) -{ - SET_BIT(ADCx->SS0_END, ADC_SS0_END_IE15_MSK); -} - -/** - * @brief 16th Sample Interrupt Disable. - * @param ADCx ADC Instance. - * @retval None. - */ -__STATIC_INLINE void md_adc_disable_ss0_end_ie15(ADC_TypeDef *ADCx) -{ - CLEAR_BIT(ADCx->SS0_END, ADC_SS0_END_IE15_MSK); -} - -/** - * @brief Check if 16th Sample Interrupt is Enabled. - * @param ADCx ADC Instance. - * @retval State of bit (1 or 0). - */ -__STATIC_INLINE uint32_t md_adc_is_enabled_ss0_end_ie15(ADC_TypeDef *ADCx) -{ - return (READ_BIT(ADCx->SS0_END, ADC_SS0_END_IE15_MSK) == (ADC_SS0_END_IE15_MSK)); -} - -/** - * @brief 15th Sample Interrupt Enable. - * @param ADCx ADC Instance. - * @retval None. - */ -__STATIC_INLINE void md_adc_enable_ss0_end_ie14(ADC_TypeDef *ADCx) -{ - SET_BIT(ADCx->SS0_END, ADC_SS0_END_IE14_MSK); -} - -/** - * @brief 15th Sample Interrupt Disable. - * @param ADCx ADC Instance. - * @retval None. - */ -__STATIC_INLINE void md_adc_disable_ss0_end_ie14(ADC_TypeDef *ADCx) -{ - CLEAR_BIT(ADCx->SS0_END, ADC_SS0_END_IE14_MSK); -} - -/** - * @brief Check if 15th Sample Interrupt is Enabled. - * @param ADCx ADC Instance. - * @retval State of bit (1 or 0). - */ -__STATIC_INLINE uint32_t md_adc_is_enabled_ss0_end_ie14(ADC_TypeDef *ADCx) -{ - return (READ_BIT(ADCx->SS0_END, ADC_SS0_END_IE14_MSK) == (ADC_SS0_END_IE14_MSK)); -} - -/** - * @brief 14th Sample Interrupt Enable. - * @param ADCx ADC Instance. - * @retval None. - */ -__STATIC_INLINE void md_adc_enable_ss0_end_ie13(ADC_TypeDef *ADCx) -{ - SET_BIT(ADCx->SS0_END, ADC_SS0_END_IE13_MSK); -} - -/** - * @brief 14th Sample Interrupt Disable. - * @param ADCx ADC Instance. - * @retval None. - */ -__STATIC_INLINE void md_adc_disable_ss0_end_ie13(ADC_TypeDef *ADCx) -{ - CLEAR_BIT(ADCx->SS0_END, ADC_SS0_END_IE13_MSK); -} - -/** - * @brief Check if 14th Sample Interrupt is Enabled. - * @param ADCx ADC Instance. - * @retval State of bit (1 or 0). - */ -__STATIC_INLINE uint32_t md_adc_is_enabled_ss0_end_ie13(ADC_TypeDef *ADCx) -{ - return (READ_BIT(ADCx->SS0_END, ADC_SS0_END_IE13_MSK) == (ADC_SS0_END_IE13_MSK)); -} - -/** - * @brief 13th Sample Interrupt Enable. - * @param ADCx ADC Instance. - * @retval None. - */ -__STATIC_INLINE void md_adc_enable_ss0_end_ie12(ADC_TypeDef *ADCx) -{ - SET_BIT(ADCx->SS0_END, ADC_SS0_END_IE12_MSK); -} - -/** - * @brief 13th Sample Interrupt Disable. - * @param ADCx ADC Instance. - * @retval None. - */ -__STATIC_INLINE void md_adc_disable_ss0_end_ie12(ADC_TypeDef *ADCx) -{ - CLEAR_BIT(ADCx->SS0_END, ADC_SS0_END_IE12_MSK); -} - -/** - * @brief Check if 13th Sample Interrupt is Enabled. - * @param ADCx ADC Instance. - * @retval State of bit (1 or 0). - */ -__STATIC_INLINE uint32_t md_adc_is_enabled_ss0_end_ie12(ADC_TypeDef *ADCx) -{ - return (READ_BIT(ADCx->SS0_END, ADC_SS0_END_IE12_MSK) == (ADC_SS0_END_IE12_MSK)); -} - -/** - * @brief 12th Sample Interrupt Enable. - * @param ADCx ADC Instance. - * @retval None. - */ -__STATIC_INLINE void md_adc_enable_ss0_end_ie11(ADC_TypeDef *ADCx) -{ - SET_BIT(ADCx->SS0_END, ADC_SS0_END_IE11_MSK); -} - -/** - * @brief 12th Sample Interrupt Enable. - * @param ADCx ADC Instance. - * @retval None. - */ -__STATIC_INLINE void md_adc_disable_ss0_end_ie11(ADC_TypeDef *ADCx) -{ - CLEAR_BIT(ADCx->SS0_END, ADC_SS0_END_IE11_MSK); -} - -/** - * @brief Check 12th Sample Interrupt is Enabled. - * @param ADCx ADC Instance. - * @retval State of bit (1 or 0). - */ -__STATIC_INLINE uint32_t md_adc_is_enabled_ss0_end_ie11(ADC_TypeDef *ADCx) -{ - return (READ_BIT(ADCx->SS0_END, ADC_SS0_END_IE11_MSK) == (ADC_SS0_END_IE11_MSK)); -} - -/** - * @brief 11th Sample Interrupt Enable. - * @param ADCx ADC Instance. - * @retval None. - */ -__STATIC_INLINE void md_adc_enable_ss0_end_ie10(ADC_TypeDef *ADCx) -{ - SET_BIT(ADCx->SS0_END, ADC_SS0_END_IE10_MSK); -} - -/** - * @brief 11th Sample Interrupt Disable. - * @param ADCx ADC Instance. - * @retval None. - */ -__STATIC_INLINE void md_adc_disable_ss0_end_ie10(ADC_TypeDef *ADCx) -{ - CLEAR_BIT(ADCx->SS0_END, ADC_SS0_END_IE10_MSK); -} - -/** - * @brief Check if 11th Sample Interrupt is Enabled. - * @param ADCx ADC Instance. - * @retval State of bit (1 or 0). - */ -__STATIC_INLINE uint32_t md_adc_is_enabled_ss0_end_ie10(ADC_TypeDef *ADCx) -{ - return (READ_BIT(ADCx->SS0_END, ADC_SS0_END_IE10_MSK) == (ADC_SS0_END_IE10_MSK)); -} - -/** - * @brief 10th Sample Interrupt Enable. - * @param ADCx ADC Instance. - * @retval None. - */ -__STATIC_INLINE void md_adc_enable_ss0_end_ie9(ADC_TypeDef *ADCx) -{ - SET_BIT(ADCx->SS0_END, ADC_SS0_END_IE9_MSK); -} - -/** - * @brief 10th Sample Interrupt Disable. - * @param ADCx ADC Instance. - * @retval None. - */ -__STATIC_INLINE void md_adc_disable_ss0_end_ie9(ADC_TypeDef *ADCx) -{ - CLEAR_BIT(ADCx->SS0_END, ADC_SS0_END_IE9_MSK); -} - -/** - * @brief Check if 10th Sample Interrupt is Enabled. - * @param ADCx ADC Instance. - * @retval State of bit (1 or 0). - */ -__STATIC_INLINE uint32_t md_adc_is_enabled_ss0_end_ie9(ADC_TypeDef *ADCx) -{ - return (READ_BIT(ADCx->SS0_END, ADC_SS0_END_IE9_MSK) == (ADC_SS0_END_IE9_MSK)); -} - -/** - * @brief 9th Sample Interrupt Enable. - * @param ADCx ADC Instance. - * @retval None. - */ -__STATIC_INLINE void md_adc_enable_ss0_end_ie8(ADC_TypeDef *ADCx) -{ - SET_BIT(ADCx->SS0_END, ADC_SS0_END_IE8_MSK); -} - -/** - * @brief 9th Sample Interrupt Disable. - * @param ADCx ADC Instance. - * @retval None. - */ -__STATIC_INLINE void md_adc_disable_ss0_end_ie8(ADC_TypeDef *ADCx) -{ - CLEAR_BIT(ADCx->SS0_END, ADC_SS0_END_IE8_MSK); -} - -/** - * @brief Check if 9th Sample Interrupt is Enable. - * @param ADCx ADC Instance. - * @retval State of bit (1 or 0). - */ -__STATIC_INLINE uint32_t md_adc_is_enabled_ss0_end_ie8(ADC_TypeDef *ADCx) -{ - return (READ_BIT(ADCx->SS0_END, ADC_SS0_END_IE8_MSK) == (ADC_SS0_END_IE8_MSK)); -} - -/** - * @brief 8th Sample Interrupt Enable. - * @param ADCx ADC Instance. - * @retval None. - */ -__STATIC_INLINE void md_adc_enable_ss0_end_ie7(ADC_TypeDef *ADCx) -{ - SET_BIT(ADCx->SS0_END, ADC_SS0_END_IE7_MSK); -} - -/** - * @brief 8th Sample Interrupt Disable - * @param ADCx ADC Instance. - * @retval None. - */ -__STATIC_INLINE void md_adc_disable_ss0_end_ie7(ADC_TypeDef *ADCx) -{ - CLEAR_BIT(ADCx->SS0_END, ADC_SS0_END_IE7_MSK); -} - -/** - * @brief Check if 8th Sample Interrupt is Enabled. - * @param ADCx ADC Instance. - * @retval State of bit (1 or 0). - */ -__STATIC_INLINE uint32_t md_adc_is_enabled_ss0_end_ie7(ADC_TypeDef *ADCx) -{ - return (READ_BIT(ADCx->SS0_END, ADC_SS0_END_IE7_MSK) == (ADC_SS0_END_IE7_MSK)); -} - -/** - * @brief 7th Sample Interrupt Enable. - * @param ADCx ADC Instance. - * @retval None. - */ -__STATIC_INLINE void md_adc_enable_ss0_end_ie6(ADC_TypeDef *ADCx) -{ - SET_BIT(ADCx->SS0_END, ADC_SS0_END_IE6_MSK); -} - -/** - * @brief 7th Sample Interrupt Disable. - * @param ADCx ADC Instance. - * @retval None. - */ -__STATIC_INLINE void md_adc_disable_ss0_end_ie6(ADC_TypeDef *ADCx) -{ - CLEAR_BIT(ADCx->SS0_END, ADC_SS0_END_IE6_MSK); -} - -/** - * @brief Check if 7th Sample Interrupt is Enabled. - * @param ADCx ADC Instance. - * @retval State of bit (1 or 0). - */ -__STATIC_INLINE uint32_t md_adc_is_enabled_ss0_end_ie6(ADC_TypeDef *ADCx) -{ - return (READ_BIT(ADCx->SS0_END, ADC_SS0_END_IE6_MSK) == (ADC_SS0_END_IE6_MSK)); -} - - -/** - * @brief 6th Sample Interrupt Enable. - * @param ADCx ADC Instance. - * @retval None. - */ -__STATIC_INLINE void md_adc_enable_ss0_end_ie5(ADC_TypeDef *ADCx) -{ - SET_BIT(ADCx->SS0_END, ADC_SS0_END_IE5_MSK); -} - -/** - * @brief 6th Sample Interrupt Disable. - * @param ADCx ADC Instance. - * @retval None. - */ -__STATIC_INLINE void md_adc_disable_ss0_end_ie5(ADC_TypeDef *ADCx) -{ - CLEAR_BIT(ADCx->SS0_END, ADC_SS0_END_IE5_MSK); -} - -/** - * @brief Check if 6th Sample Interrupt is Enabled. - * @param ADCx ADC Instance. - * @retval State of bit (1 or 0). - */ -__STATIC_INLINE uint32_t md_adc_is_enabled_ss0_end_ie5(ADC_TypeDef *ADCx) -{ - return (READ_BIT(ADCx->SS0_END, ADC_SS0_END_IE5_MSK) == (ADC_SS0_END_IE5_MSK)); -} - -/** - * @brief 5th Sample Interrupt Enable. - * @param ADCx ADC Instance. - * @retval None. - */ -__STATIC_INLINE void md_adc_enable_ss0_end_ie4(ADC_TypeDef *ADCx) -{ - SET_BIT(ADCx->SS0_END, ADC_SS0_END_IE4_MSK); -} - -/** - * @brief 5th Sample Interrupt Disable. - * @param ADCx ADC Instance. - * @retval None. - */ -__STATIC_INLINE void md_adc_disable_ss0_end_ie4(ADC_TypeDef *ADCx) -{ - CLEAR_BIT(ADCx->SS0_END, ADC_SS0_END_IE4_MSK); -} - -/** - * @brief Check if 5th Sample Interrupt is Enabled. - * @param ADCx ADC Instance. - * @retval State of bit (1 or 0). - */ -__STATIC_INLINE uint32_t md_adc_is_enabled_ss0_end_ie4(ADC_TypeDef *ADCx) -{ - return (READ_BIT(ADCx->SS0_END, ADC_SS0_END_IE4_MSK) == (ADC_SS0_END_IE4_MSK)); -} - -/** - * @brief 4th Sample Interrupt Enable. - * @param ADCx ADC Instance. - * @retval None. - */ -__STATIC_INLINE void md_adc_enable_ss0_end_ie3(ADC_TypeDef *ADCx) -{ - SET_BIT(ADCx->SS0_END, ADC_SS0_END_IE3_MSK); -} - -/** - * @brief 4th Sample Interrupt Disable. - * @param ADCx ADC Instance. - * @retval None. - */ -__STATIC_INLINE void md_adc_disable_ss0_end_ie3(ADC_TypeDef *ADCx) -{ - CLEAR_BIT(ADCx->SS0_END, ADC_SS0_END_IE3_MSK); -} - -/** - * @brief Check if 4th Sample Interrupt is Enabled. - * @param ADCx ADC Instance. - * @retval State of bit (1 or 0). - */ -__STATIC_INLINE uint32_t md_adc_is_enabled_ss0_end_ie3(ADC_TypeDef *ADCx) -{ - return (READ_BIT(ADCx->SS0_END, ADC_SS0_END_IE3_MSK) == (ADC_SS0_END_IE3_MSK)); -} - -/** - * @brief 3rd Sample Interrupt Enable. - * @param ADCx ADC Instance. - * @retval None. - */ -__STATIC_INLINE void md_adc_enable_ss0_end_ie2(ADC_TypeDef *ADCx) -{ - SET_BIT(ADCx->SS0_END, ADC_SS0_END_IE2_MSK); -} - -/** - * @brief 3rd Sample Interrupt Disable. - * @param ADCx ADC Instance. - * @retval None. - */ -__STATIC_INLINE void md_adc_disable_ss0_end_ie2(ADC_TypeDef *ADCx) -{ - CLEAR_BIT(ADCx->SS0_END, ADC_SS0_END_IE2_MSK); -} - -/** - * @brief Check if 3rd Sample Interrupt is Enabled. - * @param ADCx ADC Instance. - * @retval State of bit (1 or 0). - */ -__STATIC_INLINE uint32_t md_adc_is_enabled_ss0_end_ie2(ADC_TypeDef *ADCx) -{ - return (READ_BIT(ADCx->SS0_END, ADC_SS0_END_IE2_MSK) == (ADC_SS0_END_IE2_MSK)); -} - -/** - * @brief 2nd Sample Interrupt Enable. - * @param ADCx ADC Instance. - * @retval None. - */ -__STATIC_INLINE void md_adc_enable_ss0_end_ie1(ADC_TypeDef *ADCx) -{ - SET_BIT(ADCx->SS0_END, ADC_SS0_END_IE1_MSK); -} - -/** - * @brief 2nd Sample Interrupt Disable. - * @param ADCx ADC Instance. - * @retval None. - */ -__STATIC_INLINE void md_adc_disable_ss0_end_ie1(ADC_TypeDef *ADCx) -{ - CLEAR_BIT(ADCx->SS0_END, ADC_SS0_END_IE1_MSK); -} - -/** - * @brief Check if 2nd Sample Interrupt is Enabled. - * @param ADCx ADC Instance. - * @retval State of bit (1 or 0). - */ -__STATIC_INLINE uint32_t md_adc_is_enabled_ss0_end_ie1(ADC_TypeDef *ADCx) -{ - return (READ_BIT(ADCx->SS0_END, ADC_SS0_END_IE1_MSK) == (ADC_SS0_END_IE1_MSK)); -} - -/** - * @brief 1st Sample Interrupt Enable. - * @param ADCx ADC Instance. - * @retval None. - */ -__STATIC_INLINE void md_adc_enable_ss0_end_ie0(ADC_TypeDef *ADCx) -{ - SET_BIT(ADCx->SS0_END, ADC_SS0_END_IE0_MSK); -} - -/** - * @brief 1st Sample Interrupt Disable. - * @param ADCx ADC Instance. - * @retval None. - */ -__STATIC_INLINE void md_adc_disable_ss0_end_ie0(ADC_TypeDef *ADCx) -{ - CLEAR_BIT(ADCx->SS0_END, ADC_SS0_END_IE0_MSK); -} - -/** - * @brief Check if 1st Sample Interrupt is Enabled. - * @param ADCx ADC Instance. - * @retval State of bit (1 or 0). - */ -__STATIC_INLINE uint32_t md_adc_is_enabled_ss0_end_ie0(ADC_TypeDef *ADCx) -{ - return (READ_BIT(ADCx->SS0_END, ADC_SS0_END_IE0_MSK) == (ADC_SS0_END_IE0_MSK)); -} - -/** - * @brief Set ADC SS0 sample counts. - * @note User can set this register to select how many times will ADC samples data. - * @param ADCx ADC Instance. - * @param End Value Min_Value=0x00 Max_Value=0x0F. - * @retval None. - */ -__STATIC_INLINE void md_adc_set_ss0_end_end(ADC_TypeDef *ADCx, uint32_t EndValue) -{ - MODIFY_REG(ADCx->SS0_END, ADC_SS0_END_END_MSK, EndValue<SS0_END, ADC_SS0_END_END_MSK)>>ADC_SS0_END_END_POSS); -} - -/** - * @brief Set ADC Sample Sequence 0 End Control Register. - * @note Set ADC_SS0_END register - * @param ADCx ADC Instance - * @param ADC_SS0_END Register Value - * @retval None - */ -__STATIC_INLINE void md_adc_set_ss0_end(ADC_TypeDef *ADCx, uint32_t RegValue) -{ - MODIFY_REG(ADCx->SS0_END, ADC_SS0_END_END_MSK, RegValue); -} - -/** - * @brief Get ADC Sample Sequence 0 End Control Register. - * @param ADCx ADC Instance - * @retval ADC_SS0_END Register Value - */ -__STATIC_INLINE uint32_t md_adc_get_ss0_end(ADC_TypeDef *ADCx) -{ - return READ_REG(ADCx->SS0_END); -} - -/** - * @brief Set ADC Sample Sequencer 0 (SS0) FIFO Overflow status - * @note When the FIFO is full and a write was requested. - * When an overflow is detected, the most recent write is dropped. - * @param ADCx ADC Instance - * @retval None - */ -__STATIC_INLINE void md_adc_set_ss0_fstat_ov(ADC_TypeDef *ADCx) -{ - SET_BIT(ADCx->SS0_END, ADC_SS0_FSTAT_OV_MSK); -} - -/** - * @brief Get ADC Sample Sequencer 0 (SS0) FIFO Overflow status - * @param ADCx ADC Instance - * @retval 1 or 0 - */ -__STATIC_INLINE uint32_t md_adc_get_ss0_fstat_ov(ADC_TypeDef *ADCx) -{ - return (READ_BIT(ADCx->SS0_FSTAT, ADC_SS0_FSTAT_OV_MSK)>>ADC_SS0_FSTAT_OV_POS); -} - -/** - * @brief Check if ADC SS0 FSTAT OV is actived. - * @param ADCx ADC Instance - * @retval State of bit (1 or 0). - */ -__STATIC_INLINE uint32_t md_adc_is_active_flag_ss0_fstat_ov(ADC_TypeDef *ADCx) -{ - return (READ_BIT(ADCx->SS0_FSTAT, ADC_SS0_FSTAT_OV_MSK) == (ADC_SS0_FSTAT_OV_MSK)); -} - -/** - * @brief Get ADC SS0 FSTAT FULL - * @param ADCx ADC Instance - * @retval State of bit (1 or 0). - */ -__STATIC_INLINE uint32_t md_adc_get_ss0_fstat_full(ADC_TypeDef *ADCx) -{ - return (READ_BIT(ADCx->SS0_FSTAT, ADC_SS0_FSTAT_FULL_MSK)>>ADC_SS0_FSTAT_FULL_POS); -} - -/** - * @brief Check if ADC SS0 FSTAT FULL is actived. - * @param ADCx ADC Instance - * @retval State of bit (1 or 0). - */ -__STATIC_INLINE uint32_t md_adc_is_active_flag_ss0_fstat_full(ADC_TypeDef *ADCx) -{ - return (READ_BIT(ADCx->SS0_FSTAT, ADC_SS0_FSTAT_FULL_MSK) == (ADC_SS0_FSTAT_FULL_MSK)); -} - -/** - * @brief Set ADC SS0 FSTAT UV. - * @note When the FIFO is empty and a read was requested. - * The problematic read does not move the FIFO pointers, and 0s are returned. - * @param ADCx ADC Instance. - * @retval None. - */ -__STATIC_INLINE void md_adc_set_ss0_fstat_uv(ADC_TypeDef *ADCx) -{ - SET_BIT(ADCx->SS0_END, ADC_SS0_FSTAT_UV_MSK); -} - -/** - * @brief Get ADC SS0 FSTAT UV - * @param ADCx ADC Instance - * @retval 1 or 0 - */ -__STATIC_INLINE uint32_t md_adc_get_ss0_fstat_uv(ADC_TypeDef *ADCx) -{ - return (READ_BIT(ADCx->SS0_FSTAT, ADC_SS0_FSTAT_UV_MSK)>>ADC_SS0_FSTAT_UV_POS); -} - -/** - * @brief Check if ADC SS0 FSTAT UV is actived. - * @param ADCx ADC Instance - * @retval State of bit (1 or 0). - */ -__STATIC_INLINE uint32_t md_adc_is_active_flag_ss0_fstat_uv(ADC_TypeDef *ADCx) -{ - return (READ_BIT(ADCx->SS0_FSTAT, ADC_SS0_FSTAT_UV_MSK) == (ADC_SS0_FSTAT_UV_MSK)); -} - -/** - * @brief Get ADC SS0 FSTAT EMPTY - * @param ADCx ADC Instance - * @retval 1 or 0 - */ -__STATIC_INLINE uint32_t md_adc_get_ss0_fstat_empty(ADC_TypeDef *ADCx) -{ - return (READ_BIT(ADCx->SS0_FSTAT, ADC_SS0_FSTAT_EMPTY_MSK)>>ADC_SS0_FSTAT_EMPTY_POS); -} - -/** - * @brief Check if ADC SS0 FSTAT EMPTY is actived. - * @param ADCx ADC Instance - * @retval State of bit (1 or 0). - */ -__STATIC_INLINE uint32_t md_adc_is_active_flag_ss0_fstat_empty(ADC_TypeDef *ADCx) -{ - return (READ_BIT(ADCx->SS0_FSTAT, ADC_SS0_FSTAT_EMPTY_MSK) == (ADC_SS0_FSTAT_EMPTY_MSK)); -} - -/** - * @brief Get ADC SS0 FSTAT HPTR - * @note The field contains the current head pointer index, which is the - * next entry to be written to FIFO. - * @param ADCx ADC Instance - * @retval 1 or 0 - */ -__STATIC_INLINE uint32_t md_adc_get_ss0_fstat_hptr(ADC_TypeDef *ADCx) -{ - return (READ_BIT(ADCx->SS0_FSTAT, ADC_SS0_FSTAT_HPTR_MSK)>>ADC_SS0_FSTAT_HPTR_POSS); -} - -/** - * @brief Get ADC SS0 FSTAT TPTR - * @note The field contains the current tail pointer index, which is the - * next entry to be read from FIFO. - * @param ADCx ADC Instance - * @retval 1 or 0 - */ -__STATIC_INLINE uint32_t md_adc_get_ss0_fstat_tptr(ADC_TypeDef *ADCx) -{ - return (READ_BIT(ADCx->SS0_FSTAT, ADC_SS0_FSTAT_TPTR_MSK)>>ADC_SS0_FSTAT_TPTR_POSS); -} - -/** - * @brief Get ADC sample sequencer 0(SS0) result FIFO data. - * @note User can read conversion result data by reading this register. - * @param ADCx ADC Instance - * @retval ADC Sampled Data - */ -__STATIC_INLINE uint32_t md_adc_get_ss0_data(ADC_TypeDef *ADCx) -{ - return (uint32_t)(READ_REG(ADC->SS0_DATA)); -} - -/** - * @brief Set SS1 Trigger Select. - * @note This field selects the trigger source for Sample Sequencer 1. - * @param ADCx ADC Instance - * @param Sample sequencer trigger sources. - * This parameter can be one of the following values: - * @arg @ref MD_ADC_SS_CON_SEL_SW - * @arg @ref MD_ADC_SS_CON_SEL_BS16T1 - * @arg @ref MD_ADC_SS_CON_SEL_ALWAYS - * @arg @ref MD_ADC_SS_CON_SEL_GP32C4T1 - * @arg @ref MD_ADC_SS_CON_SEL_GP16C4T1 - * @arg @ref MD_ADC_SS_CON_SEL_GP16C4T2 - * @arg @ref MD_ADC_SS_CON_SEL_GP16C4T3 - * @arg @ref MD_ADC_SS_CON_SEL_GP32C4T1 - * @arg @ref MD_ADC_SS_CON_SEL_GP16C2T1 - * @arg @ref MD_ADC_SS_CON_SEL_GP16C2T2 - * @arg @ref MD_ADC_SS_CON_SEL_GP16C2T3 - * @arg @ref MD_ADC_SS_CON_SEL_GP32C4T1 - * @arg @ref MD_ADC_SS_CON_SEL_GP16C2T4 - * @arg @ref MD_ADC_SS_CON_SEL_AD16C4T1 - * @arg @ref MD_ADC_SS_CON_SEL_GPIO - * @arg @ref MD_ADC_SS_CON_SEL_CMP0 - * @arg @ref MD_ADC_SS_CON_SEL_CMP1 - * @arg @ref MD_ADC_SS_CON_SEL_CMP2 - * @arg @ref MD_ADC_SS_CON_SEL_CMP3 - * @retval None - */ -__STATIC_INLINE void md_adc_set_ss1_con_sel(ADC_TypeDef *ADCx, uint32_t TrigSource) -{ - MODIFY_REG(ADCx->SS1_CON, ADC_SS1_CON_SEL_MSK, TrigSource<SS1_CON, ADC_SS1_CON_SEL_MSK)>>ADC_SS1_CON_SEL_POSS); -} - -/** - * @brief ADC Sample Sequencer 1 (SS1) Trigger Type select. - * @note User can set this bit to select the type of trigger. - * @param ADCx ADC Instance. - * @param This parameter can be one of the following values: - * @arg @ref MD_ADC_SS_CON_TYP_EDGE - * @arg @ref MD_ADC_SS_COM_TYP_LEVEL - * @retval None - */ -__STATIC_INLINE void md_adc_set_ss1_con_type(ADC_TypeDef *ADCx, uint32_t TrigType) -{ - MODIFY_REG(ADCx->SS1_CON, ADC_SS1_CON_TYP_MSK, TrigType<SS1_CON, ADC_SS1_CON_TYP_MSK)>>ADC_SS1_CON_TYP_POS); -} - -/** - * @brief Set ADC Sample Sequencer 1 (SS1) Priority. - * @note This field contains a binary-encoded value specifying the - * priority encoding of SS1. The prioriteies assigned to the - * sequencers must be uniquely mapped. - * @param ADCx ADC Instance. - * @param This parameter can be one of the following values: - * @arg @ref MD_ADC_SS0_CON_PRI_HIGHEST - * @arg @ref MD_ADC_SS0_CON_PRI_SECOND - * @arg @ref MD_ADC_SS0_CON_PRI_THIRD - * @arg @ref MD_ADC_SS0_CON_PRI_LOWEST - * @retval None - */ -__STATIC_INLINE void md_adc_set_ss1_con_pri(ADC_TypeDef *adcx, uint32_t priority) -{ - MODIFY_REG(adcx->SS1_CON, ADC_SS1_CON_PRI_MSK, priority<SS1_CON, ADC_SS1_CON_PRI_MSK)>>ADC_SS1_CON_PRI_POSS); -} - -/** - * @brief One Shot Trigger Mode enable. - * @note When set HIGH, each trigger will only sample once and use one - * slot in FIFO. - * @param ADCx ADC Instance. - * @retval None - */ -__STATIC_INLINE void md_adc_enable_ss1_con_one(ADC_TypeDef *adcx) -{ - SET_BIT(adcx->SS1_CON, ADC_SS1_CON_ONE_MSK); -} - -/** - * @brief One Shot Trigger Mode disable. - * @param ADCx ADC Instance. - * @retval None - */ -__STATIC_INLINE void md_adc_disable_ss1_con_one(ADC_TypeDef *adcx) -{ - CLEAR_BIT(adcx->SS1_CON, ADC_SS1_CON_ONE_MSK); -} - -/** - * @brief Set ADC SS1 MUX7 ADINx Input Pin. - * @note 8th Sample Input Select. - * @param ADCx ADC Instance - * @param ADIN Pin: - * @arg @ref MD_ADC_SS_MUX_ADIN15 - * @arg @ref MD_ADC_SS_MUX_ADIN14 - * @arg @ref MD_ADC_SS_MUX_ADIN13 - * @arg @ref MD_ADC_SS_MUX_ADIN12 - * @arg @ref MD_ADC_SS_MUX_ADIN11 - * @arg @ref MD_ADC_SS_MUX_ADIN10 - * @arg @ref MD_ADC_SS_MUX_ADIN9 - * @arg @ref MD_ADC_SS_MUX_ADIN8 - * @arg @ref MD_ADC_SS_MUX_ADIN7 - * @arg @ref MD_ADC_SS_MUX_ADIN6 - * @arg @ref MD_ADC_SS_MUX_ADIN5 - * @arg @ref MD_ADC_SS_MUX_ADIN4 - * @arg @ref MD_ADC_SS_MUX_ADIN3 - * @arg @ref MD_ADC_SS_MUX_ADIN2 - * @arg @ref MD_ADC_SS_MUX_ADIN1 - * @arg @ref MD_ADC_SS_MUX_ADIN0 - */ -__STATIC_INLINE void md_adc_set_ss1_mux0_mux7(ADC_TypeDef *ADCx, uint32_t AdinPin) -{ - MODIFY_REG(ADCx->SS1_MUX0, ADC_SS1_MUX0_MUX7_MSK, AdinPin<SS1_MUX0, ADC_SS1_MUX0_MUX7_MSK)>>ADC_SS1_MUX0_MUX7_POSS); -} - -/** - * @brief Set ADC SS1 MUX6 Input ADIN Pin. - * @note 7th Sample Input Select. - * @param ADCx ADC Instance - * @param ADIN Pin: - * @arg @ref MD_ADC_SS_MUX_ADIN15 - * @arg @ref MD_ADC_SS_MUX_ADIN14 - * @arg @ref MD_ADC_SS_MUX_ADIN13 - * @arg @ref MD_ADC_SS_MUX_ADIN12 - * @arg @ref MD_ADC_SS_MUX_ADIN11 - * @arg @ref MD_ADC_SS_MUX_ADIN10 - * @arg @ref MD_ADC_SS_MUX_ADIN9 - * @arg @ref MD_ADC_SS_MUX_ADIN8 - * @arg @ref MD_ADC_SS_MUX_ADIN7 - * @arg @ref MD_ADC_SS_MUX_ADIN6 - * @arg @ref MD_ADC_SS_MUX_ADIN5 - * @arg @ref MD_ADC_SS_MUX_ADIN4 - * @arg @ref MD_ADC_SS_MUX_ADIN3 - * @arg @ref MD_ADC_SS_MUX_ADIN2 - * @arg @ref MD_ADC_SS_MUX_ADIN1 - * @arg @ref MD_ADC_SS_MUX_ADIN0 - */ -__STATIC_INLINE void md_adc_set_ss1_mux0_mux6(ADC_TypeDef *ADCx, uint32_t AdinPin) -{ - MODIFY_REG(ADCx->SS1_MUX0, ADC_SS1_MUX0_MUX6_MSK, AdinPin<SS1_MUX0, ADC_SS1_MUX0_MUX6_MSK)>>ADC_SS1_MUX0_MUX6_POSS); -} - -/** - * @brief Set ADC SS1 MUX0 MUX5 Input ADIN Pin. - * @note 6th Sample Input Select. - * @param ADCx ADC Instance - * @param ADIN Pin: - * @arg @ref MD_ADC_SS_MUX_ADIN15 - * @arg @ref MD_ADC_SS_MUX_ADIN14 - * @arg @ref MD_ADC_SS_MUX_ADIN13 - * @arg @ref MD_ADC_SS_MUX_ADIN12 - * @arg @ref MD_ADC_SS_MUX_ADIN11 - * @arg @ref MD_ADC_SS_MUX_ADIN10 - * @arg @ref MD_ADC_SS_MUX_ADIN9 - * @arg @ref MD_ADC_SS_MUX_ADIN8 - * @arg @ref MD_ADC_SS_MUX_ADIN7 - * @arg @ref MD_ADC_SS_MUX_ADIN6 - * @arg @ref MD_ADC_SS_MUX_ADIN5 - * @arg @ref MD_ADC_SS_MUX_ADIN4 - * @arg @ref MD_ADC_SS_MUX_ADIN3 - * @arg @ref MD_ADC_SS_MUX_ADIN2 - * @arg @ref MD_ADC_SS_MUX_ADIN1 - * @arg @ref MD_ADC_SS_MUX_ADIN0 - */ -__STATIC_INLINE void md_adc_set_ss1_mux0_mux5(ADC_TypeDef *ADCx, uint32_t AdinPin) -{ - MODIFY_REG(ADCx->SS1_MUX0, ADC_SS1_MUX0_MUX5_MSK, AdinPin<SS1_MUX0, ADC_SS1_MUX0_MUX5_MSK)>>ADC_SS1_MUX0_MUX5_POSS); -} - -/** - * @brief Set ADC SS1 MUX0 MUX4 Input ADIN Pin. - * @note 5th Sample Input Select. - * @param ADCx ADC Instance - * @param ADIN Pin: - * @arg @ref MD_ADC_SS_MUX_ADIN15 - * @arg @ref MD_ADC_SS_MUX_ADIN14 - * @arg @ref MD_ADC_SS_MUX_ADIN13 - * @arg @ref MD_ADC_SS_MUX_ADIN12 - * @arg @ref MD_ADC_SS_MUX_ADIN11 - * @arg @ref MD_ADC_SS_MUX_ADIN10 - * @arg @ref MD_ADC_SS_MUX_ADIN9 - * @arg @ref MD_ADC_SS_MUX_ADIN8 - * @arg @ref MD_ADC_SS_MUX_ADIN7 - * @arg @ref MD_ADC_SS_MUX_ADIN6 - * @arg @ref MD_ADC_SS_MUX_ADIN5 - * @arg @ref MD_ADC_SS_MUX_ADIN4 - * @arg @ref MD_ADC_SS_MUX_ADIN3 - * @arg @ref MD_ADC_SS_MUX_ADIN2 - * @arg @ref MD_ADC_SS_MUX_ADIN1 - * @arg @ref MD_ADC_SS_MUX_ADIN0 - */ -__STATIC_INLINE void md_adc_set_ss1_mux0_mux4(ADC_TypeDef *ADCx, uint32_t AdinPin) -{ - MODIFY_REG(ADCx->SS1_MUX0, ADC_SS1_MUX0_MUX4_MSK, AdinPin<SS1_MUX0, ADC_SS1_MUX0_MUX4_MSK)>>ADC_SS1_MUX0_MUX4_POSS); -} - -/** - * @brief Set ADC SS1 MUX0 MUX3 Input ADIN Pin. - * @note 4th Sample Input Select. - * @param ADCx ADC Instance - * @param ADIN Pin: - * @arg @ref MD_ADC_SS_MUX_ADIN15 - * @arg @ref MD_ADC_SS_MUX_ADIN14 - * @arg @ref MD_ADC_SS_MUX_ADIN13 - * @arg @ref MD_ADC_SS_MUX_ADIN12 - * @arg @ref MD_ADC_SS_MUX_ADIN11 - * @arg @ref MD_ADC_SS_MUX_ADIN10 - * @arg @ref MD_ADC_SS_MUX_ADIN9 - * @arg @ref MD_ADC_SS_MUX_ADIN8 - * @arg @ref MD_ADC_SS_MUX_ADIN7 - * @arg @ref MD_ADC_SS_MUX_ADIN6 - * @arg @ref MD_ADC_SS_MUX_ADIN5 - * @arg @ref MD_ADC_SS_MUX_ADIN4 - * @arg @ref MD_ADC_SS_MUX_ADIN3 - * @arg @ref MD_ADC_SS_MUX_ADIN2 - * @arg @ref MD_ADC_SS_MUX_ADIN1 - * @arg @ref MD_ADC_SS_MUX_ADIN0 - */ -__STATIC_INLINE void md_adc_set_ss1_mux0_mux3(ADC_TypeDef *ADCx, uint32_t AdinPin) -{ - MODIFY_REG(ADCx->SS1_MUX0, ADC_SS1_MUX0_MUX3_MSK, AdinPin<SS1_MUX0, ADC_SS1_MUX0_MUX3_MSK)>>ADC_SS1_MUX0_MUX3_POSS); -} - -/** - * @brief Set ADC SS1 MUX0 MUX2 Input ADIN Pin. - * @note 3rd Sample Input Select. - * @param ADCx ADC Instance - * @param ADIN Pin: - * @arg @ref MD_ADC_SS_MUX_ADIN15 - * @arg @ref MD_ADC_SS_MUX_ADIN14 - * @arg @ref MD_ADC_SS_MUX_ADIN13 - * @arg @ref MD_ADC_SS_MUX_ADIN12 - * @arg @ref MD_ADC_SS_MUX_ADIN11 - * @arg @ref MD_ADC_SS_MUX_ADIN10 - * @arg @ref MD_ADC_SS_MUX_ADIN9 - * @arg @ref MD_ADC_SS_MUX_ADIN8 - * @arg @ref MD_ADC_SS_MUX_ADIN7 - * @arg @ref MD_ADC_SS_MUX_ADIN6 - * @arg @ref MD_ADC_SS_MUX_ADIN5 - * @arg @ref MD_ADC_SS_MUX_ADIN4 - * @arg @ref MD_ADC_SS_MUX_ADIN3 - * @arg @ref MD_ADC_SS_MUX_ADIN2 - * @arg @ref MD_ADC_SS_MUX_ADIN1 - * @arg @ref MD_ADC_SS_MUX_ADIN0 - */ -__STATIC_INLINE void md_adc_set_ss1_mux0_mux2(ADC_TypeDef *ADCx, uint32_t AdinPin) -{ - MODIFY_REG(ADCx->SS1_MUX0, ADC_SS1_MUX0_MUX2_MSK, AdinPin<SS1_MUX0, ADC_SS1_MUX0_MUX2_MSK)>>ADC_SS1_MUX0_MUX2_POSS); -} - -/** - * @brief Set ADC SS1 MUX0 MUX1 Input ADIN Pin. - * @note 2nd Sample Input Select. - * @param ADCx ADC Instance - * @param ADIN Pin: - * @arg @ref MD_ADC_SS_MUX_ADIN15 - * @arg @ref MD_ADC_SS_MUX_ADIN14 - * @arg @ref MD_ADC_SS_MUX_ADIN13 - * @arg @ref MD_ADC_SS_MUX_ADIN12 - * @arg @ref MD_ADC_SS_MUX_ADIN11 - * @arg @ref MD_ADC_SS_MUX_ADIN10 - * @arg @ref MD_ADC_SS_MUX_ADIN9 - * @arg @ref MD_ADC_SS_MUX_ADIN8 - * @arg @ref MD_ADC_SS_MUX_ADIN7 - * @arg @ref MD_ADC_SS_MUX_ADIN6 - * @arg @ref MD_ADC_SS_MUX_ADIN5 - * @arg @ref MD_ADC_SS_MUX_ADIN4 - * @arg @ref MD_ADC_SS_MUX_ADIN3 - * @arg @ref MD_ADC_SS_MUX_ADIN2 - * @arg @ref MD_ADC_SS_MUX_ADIN1 - * @arg @ref MD_ADC_SS_MUX_ADIN0 - */ -__STATIC_INLINE void md_adc_set_ss1_mux0_mux1(ADC_TypeDef *ADCx, uint32_t AdinPin) -{ - MODIFY_REG(ADCx->SS1_MUX0, ADC_SS1_MUX0_MUX1_MSK, AdinPin<SS1_MUX0, ADC_SS1_MUX0_MUX1_MSK)>>ADC_SS1_MUX0_MUX1_POSS); -} - -/** - * @brief Set ADC SS1 MUX0 MUX0 Input ADIN Pin. - * @note 1st Sample Input Select. - * @param ADCx ADC Instance - * @param ADIN Pin: - * @arg @ref MD_ADC_SS_MUX_ADIN15 - * @arg @ref MD_ADC_SS_MUX_ADIN14 - * @arg @ref MD_ADC_SS_MUX_ADIN13 - * @arg @ref MD_ADC_SS_MUX_ADIN12 - * @arg @ref MD_ADC_SS_MUX_ADIN11 - * @arg @ref MD_ADC_SS_MUX_ADIN10 - * @arg @ref MD_ADC_SS_MUX_ADIN9 - * @arg @ref MD_ADC_SS_MUX_ADIN8 - * @arg @ref MD_ADC_SS_MUX_ADIN7 - * @arg @ref MD_ADC_SS_MUX_ADIN6 - * @arg @ref MD_ADC_SS_MUX_ADIN5 - * @arg @ref MD_ADC_SS_MUX_ADIN4 - * @arg @ref MD_ADC_SS_MUX_ADIN3 - * @arg @ref MD_ADC_SS_MUX_ADIN2 - * @arg @ref MD_ADC_SS_MUX_ADIN1 - * @arg @ref MD_ADC_SS_MUX_ADIN0 - */ -__STATIC_INLINE void md_adc_set_ss1_mux0_mux0(ADC_TypeDef *ADCx, uint32_t AdinPin) -{ - MODIFY_REG(ADCx->SS1_MUX0, ADC_SS1_MUX0_MUX0_MSK, AdinPin<SS1_MUX0, ADC_SS1_MUX0_MUX0_MSK)>>ADC_SS1_MUX0_MUX0_POSS); -} - -/** - * @brief Set ADC_SS1_MUX0 register. - * @note Set ADC_SS1_MUX0 channels 0~7. - * @param ADCx ADC Instance. - * @param ADC_SS1_MUX0 register value. - * @retval None. - */ -__STATIC_INLINE void md_adc_set_ss1_mux0(ADC_TypeDef *ADCx, uint32_t RegValue) -{ - WRITE_REG(ADCx->SS1_MUX0, RegValue); -} - -/** - * @brief Get ADC_SS1_MUX0 register. - * @param ADCx ADC Instance. - * @retval ADC_SS1_MUX0 register value. - */ -__STATIC_INLINE uint32_t md_adc_get_ss1_mux0(ADC_TypeDef *ADCx) -{ - return READ_REG(ADCx->SS1_MUX0); -} - -/** - * @brief 8th Sample Interrupt Enable. - * @param ADCx ADC Instance - * @retval None - */ -__STATIC_INLINE void md_adc_enable_ss1_end_ie7(ADC_TypeDef *ADCx) -{ - SET_BIT(ADCx->SS1_END, ADC_SS1_END_IE7_MSK); -} - -/** - * @brief 8th Sample Interrupt Disable. - * @param ADCx ADC Instance - * @retval None - */ -__STATIC_INLINE void md_adc_disable_ss1_end_ie7(ADC_TypeDef *ADCx) -{ - CLEAR_BIT(ADCx->SS1_END, ADC_SS1_END_IE7_MSK); -} - -/** - * @brief Check if 8th Sample Interrupt is enabled. - * @param ADCx ADC Instance. - * @retval State of bit (1 or 0). - */ -__STATIC_INLINE uint32_t md_adc_is_enabled_ss1_end_ie7(ADC_TypeDef *ADCx) -{ - return (READ_BIT(ADCx->SS1_END, ADC_SS1_END_IE7_MSK) == (ADC_SS1_END_IE7_MSK)); -} - -/** - * @brief 7th Sample Interrupt Enable. - * @param ADCx ADC Instance. - * @retval None. - */ -__STATIC_INLINE void md_adc_enable_ss1_end_ie6(ADC_TypeDef *ADCx) -{ - SET_BIT(ADCx->SS1_END, ADC_SS1_END_IE6_MSK); -} - -/** - * @brief 7th Sample Interrupt Disable. - * @param ADCx ADC Instance. - * @retval None. - */ -__STATIC_INLINE void md_adc_disable_ss1_end_ie6(ADC_TypeDef *ADCx) -{ - CLEAR_BIT(ADCx->SS1_END, ADC_SS1_END_IE6_MSK); -} - -/** - * @brief Check if 7th Sample Interrupt is enabled. - * @param ADCx ADC Instance. - * @retval State of bit (1 or 0). - */ -__STATIC_INLINE uint32_t md_adc_is_enabled_ss1_end_ie6(ADC_TypeDef *ADCx) -{ - return (READ_BIT(ADCx->SS1_END, ADC_SS1_END_IE6_MSK) == (ADC_SS1_END_IE6_MSK)); -} - - -/** - * @brief 6th Sample Interrupt Enable. - * @param ADCx ADC Instance. - * @retval None. - */ -__STATIC_INLINE void md_adc_enable_ss10_end_ie5(ADC_TypeDef *ADCx) -{ - SET_BIT(ADCx->SS1_END, ADC_SS1_END_IE5_MSK); -} - -/** - * @brief 8th Sample Interrupt Disable. - * @param ADCx ADC Instance. - * @retval None. - */ -__STATIC_INLINE void md_adc_disable_ss1_end_ie5(ADC_TypeDef *ADCx) -{ - CLEAR_BIT(ADCx->SS1_END, ADC_SS1_END_IE5_MSK); -} - -/** - * @brief Check if 6th Sample Interrupt is enabled. - * @param ADCx ADC Instance - * @retval State of bit (1 or 0). - */ -__STATIC_INLINE uint32_t md_adc_is_enabled_ss1_end_ie5(ADC_TypeDef *ADCx) -{ - return (READ_BIT(ADCx->SS1_END, ADC_SS1_END_IE5_MSK) == (ADC_SS1_END_IE5_MSK)); -} - -/** - * @brief 5th Sample Interrupt Enable. - * @param ADCx ADC Instance. - * @retval None. - */ -__STATIC_INLINE void md_adc_enable_ss1_end_ie4(ADC_TypeDef *ADCx) -{ - SET_BIT(ADCx->SS1_END, ADC_SS1_END_IE4_MSK); -} - -/** - * @brief 5th Sample Interrupt Disable. - * @param ADCx ADC Instance - * @retval None - */ -__STATIC_INLINE void md_adc_disable_ss1_end_ie4(ADC_TypeDef *ADCx) -{ - CLEAR_BIT(ADCx->SS1_END, ADC_SS1_END_IE4_MSK); -} - -/** - * @brief Check if 5th Sample Interrupt is enabled. - * @param ADCx ADC Instance - * @retval State of bit (1 or 0). - */ -__STATIC_INLINE uint32_t md_adc_is_enabled_ss1_end_ie4(ADC_TypeDef *ADCx) -{ - return (READ_BIT(ADCx->SS1_END, ADC_SS1_END_IE4_MSK) == (ADC_SS1_END_IE4_MSK)); -} - -/** - * @brief 4th Sample Interrupt Enable. - * @param ADCx ADC Instance. - * @retval None. - */ -__STATIC_INLINE void md_adc_enable_ss1_end_ie3(ADC_TypeDef *ADCx) -{ - SET_BIT(ADCx->SS1_END, ADC_SS1_END_IE3_MSK); -} - -/** - * @brief 8th Sample Interrupt Disable. - * @param ADCx ADC Instance. - * @retval None. - */ -__STATIC_INLINE void md_adc_disable_ss1_end_ie3(ADC_TypeDef *ADCx) -{ - CLEAR_BIT(ADCx->SS1_END, ADC_SS1_END_IE3_MSK); -} - -/** - * @brief Check if 4th Sample Interrupt is enabled. - * @param ADCx ADC Instance - * @retval State of bit (1 or 0). - */ -__STATIC_INLINE uint32_t md_adc_is_enabled_ss1_end_ie3(ADC_TypeDef *ADCx) -{ - return (READ_BIT(ADCx->SS1_END, ADC_SS1_END_IE3_MSK) == (ADC_SS1_END_IE3_MSK)); -} - -/** - * @brief 3rd Sample Interrupt Enable. - * @param ADCx ADC Instance. - * @retval None. - */ -__STATIC_INLINE void md_adc_enable_ss1_end_ie2(ADC_TypeDef *ADCx) -{ - SET_BIT(ADCx->SS1_END, ADC_SS1_END_IE2_MSK); -} - -/** - * @brief 3rd Sample Interrupt Enable. - * @param ADCx ADC Instance. - * @retval None. - */ -__STATIC_INLINE void md_adc_disable_ss1_end_ie2(ADC_TypeDef *ADCx) -{ - CLEAR_BIT(ADCx->SS1_END, ADC_SS1_END_IE2_MSK); -} - -/** - * @brief Check if 3rd Sample Interrupt is enabled. - * @param ADCx ADC Instance. - * @retval State of bit (1 or 0). - */ -__STATIC_INLINE uint32_t md_adc_is_enabled_ss1_end_ie2(ADC_TypeDef *ADCx) -{ - return (READ_BIT(ADCx->SS1_END, ADC_SS1_END_IE2_MSK) == (ADC_SS1_END_IE2_MSK)); -} - -/** - * @brief 2nd Sample Interrupt Enable. - * @param ADCx ADC Instance. - * @retval None. - */ -__STATIC_INLINE void md_adc_enable_ss1_end_ie1(ADC_TypeDef *ADCx) -{ - SET_BIT(ADCx->SS1_END, ADC_SS1_END_IE1_MSK); -} - -/** - * @brief 2nd Sample Interrupt Disable. - * @param ADCx ADC Instance. - * @retval None. - */ -__STATIC_INLINE void md_adc_disable_ss1_end_ie1(ADC_TypeDef *ADCx) -{ - CLEAR_BIT(ADCx->SS1_END, ADC_SS1_END_IE1_MSK); -} - -/** - * @brief Check if 2nd Sample Interrupt is enabled. - * @param ADCx ADC Instance. - * @retval State of bit (1 or 0). - */ -__STATIC_INLINE uint32_t md_adc_is_enabled_ss1_end_ie1(ADC_TypeDef *ADCx) -{ - return (READ_BIT(ADCx->SS1_END, ADC_SS1_END_IE1_MSK) == (ADC_SS1_END_IE1_MSK)); -} - -/** - * @brief 1st Sample Interrupt Enable. - * @param ADCx ADC Instance. - * @retval None. - */ -__STATIC_INLINE void md_adc_enable_ss1_end_ie0(ADC_TypeDef *ADCx) -{ - SET_BIT(ADCx->SS1_END, ADC_SS1_END_IE0_MSK); -} - -/** - * @brief 1st Sample Interrupt Disable. - * @param ADCx ADC Instance. - * @retval None. - */ -__STATIC_INLINE void md_adc_disable_ss1_end_ie0(ADC_TypeDef *ADCx) -{ - CLEAR_BIT(ADCx->SS1_END, ADC_SS1_END_IE0_MSK); -} - -/** - * @brief Check if 1st Sample Interrupt is enabled. - * @param ADCx ADC Instance. - * @retval State of bit (1 or 0). - */ -__STATIC_INLINE uint32_t md_adc_is_enabled_ss1_end_ie0(ADC_TypeDef *ADCx) -{ - return (READ_BIT(ADCx->SS1_END, ADC_SS1_END_IE0_MSK) == (ADC_SS1_END_IE0_MSK)); -} - -/** - * @brief Set end sample counts. - * @note User can set this register to select how many times will ADC - * samples data. - * @param ADCx ADC Instance. - * @param End Value Min_Value=0x00 Max_Value=0x07. - * @retval None. - */ -__STATIC_INLINE void md_adc_set_ss1_end_end(ADC_TypeDef *ADCx, uint32_t EndValue) -{ - MODIFY_REG(ADCx->SS1_END, ADC_SS1_END_END_MSK, EndValue<SS1_END, ADC_SS1_END_END_MSK)>>ADC_SS1_END_END_POSS); -} - -/** - * @brief Set ADC_SS1_END Control Register - * @param ADCx ADC Instance. - * @param ADC_SS1_END register value. - * @retval None. - */ -__STATIC_INLINE void md_adc_set_ss1_end(ADC_TypeDef *ADCx, uint32_t RegValue) -{ - MODIFY_REG(ADCx->SS1_END, ADC_SS1_END_END_MSK, RegValue); -} - -/** - * @brief Get ADC_SS1_End Control Register - * @param ADCx ADC Instance. - * @retval ADC_SS1_END register value. - */ -__STATIC_INLINE uint32_t md_adc_get_ss1_end(ADC_TypeDef *ADCx) -{ - return READ_REG(ADCx->SS1_END); -} - -/** - * @brief Set ADC Sample Sequencer 1 (SS1) FIFO Overflow status. - * @note When the FIFO is full and a write was requested, the - * most recent write is dropped. - * @param ADCx ADC Instance. - * @retval None. - */ -__STATIC_INLINE void md_adc_set_ss1_fstat_ov(ADC_TypeDef *ADCx) -{ - SET_BIT(ADCx->SS1_END, ADC_SS1_FSTAT_OV_MSK); -} - -/** - * @brief Get ADC Sample Sequencer 1 (SS1) FIFO Overflow status. - * @param ADCx ADC Instance. - * @retval State of bit (1 or 0). - */ -__STATIC_INLINE uint32_t md_adc_get_ss1_fstat_ov(ADC_TypeDef *ADCx) -{ - return (READ_BIT(ADCx->SS1_FSTAT, ADC_SS1_FSTAT_OV_MSK)>>ADC_SS1_FSTAT_OV_POS); -} - -/** - * @brief Check if ADC Sample Sequencer 1 (SS1) FIFO Overflow is actived. - * @param ADCx ADC Instance - * @retval State of bit (1 or 0). - */ -__STATIC_INLINE uint32_t md_adc_is_active_flag_ss1_fstat_ov(ADC_TypeDef *ADCx) -{ - return (READ_BIT(ADCx->SS1_FSTAT, ADC_SS1_FSTAT_OV_MSK) == (ADC_SS1_FSTAT_OV_MSK)); -} - -/** - * @brief Get ADC SS1 FIFO Full status - * @param ADCx ADC Instance. - * @retval State of bit (1 or 0). - */ -__STATIC_INLINE uint32_t md_adc_get_ss1_fstat_full(ADC_TypeDef *ADCx) -{ - return (READ_BIT(ADCx->SS1_FSTAT, ADC_SS1_FSTAT_FULL_MSK)>>ADC_SS1_FSTAT_FULL_POS); -} - -/** - * @brief Check if ADC SS1 FIFO Full is actived. - * @param ADCx ADC Instance - * @retval State of bit (1 or 0). - */ -__STATIC_INLINE uint32_t md_adc_is_active_flag_ss1_fstat_full(ADC_TypeDef *ADCx) -{ - return (READ_BIT(ADCx->SS1_FSTAT, ADC_SS1_FSTAT_FULL_MSK) == (ADC_SS1_FSTAT_FULL_MSK)); -} - -/** - * @brief Set ADC Sample Sequencer 1 (SS1) FIFO Underflow status. - * @note When the FIFO is empty and a read was requested. - * The problematic read does not move the FIFO pointers, and 0s are returned. - * @param ADCx ADC Instance - * @retval None - */ -__STATIC_INLINE void md_adc_set_ss1_fstat_uv(ADC_TypeDef *ADCx) -{ - SET_BIT(ADCx->SS1_END, ADC_SS1_FSTAT_UV_MSK); -} - -/** - * @brief Get ADC Sample Sequencer 1 (SS1) FIFO Underflow status. - * @param ADCx ADC Instance. - * @retval State of bit (1 or 0). - */ -__STATIC_INLINE uint32_t md_adc_get_ss1_fstat_uv(ADC_TypeDef *ADCx) -{ - return (READ_BIT(ADCx->SS1_FSTAT, ADC_SS1_FSTAT_UV_MSK)>>ADC_SS1_FSTAT_UV_POS); -} - -/** - * @brief Check if ADC Sample Sequencer 1 (SS1) FIFO Underflow status is actived. - * @param ADCx ADC Instance. - * @retval State of bit (1 or 0). - */ -__STATIC_INLINE uint32_t md_adc_is_active_flag_ss1_fstat_uv(ADC_TypeDef *ADCx) -{ - return (READ_BIT(ADCx->SS1_FSTAT, ADC_SS1_FSTAT_UV_MSK) == (ADC_SS1_FSTAT_UV_MSK)); -} - -/** - * @brief Get ADC SS1 FIFO Empty status. - * @param ADCx ADC Instance. - * @retval State of bit (1 or 0). - */ -__STATIC_INLINE uint32_t md_adc_get_ss1_fstat_empty(ADC_TypeDef *ADCx) -{ - return (READ_BIT(ADCx->SS1_FSTAT, ADC_SS1_FSTAT_EMPTY_MSK)>>ADC_SS1_FSTAT_EMPTY_POS); -} - -/** - * @brief Check if ADC SS1 FIFO Empty is actived. - * @param ADCx ADC Instance. - * @retval State of bit (1 or 0). - */ -__STATIC_INLINE uint32_t md_adc_is_active_flag_ss1_fstat_empty(ADC_TypeDef *ADCx) -{ - return (READ_BIT(ADCx->SS1_FSTAT, ADC_SS1_FSTAT_EMPTY_MSK) == (ADC_SS1_FSTAT_EMPTY_MSK)); -} - -/** - * @brief Get ADC SS1 FIFO Head Pointer. - * @note The field contains the current head pointer index, which is the - * next entry to be written to FIFO. - * @param ADCx ADC Instance. - * @retval Value between Min_Data=0x00 and Max_Data=0x0F - */ -__STATIC_INLINE uint32_t md_adc_get_ss1_fstat_hptr(ADC_TypeDef *ADCx) -{ - return (READ_BIT(ADCx->SS1_FSTAT, ADC_SS1_FSTAT_HPTR_MSK)>>ADC_SS1_FSTAT_HPTR_POSS); -} - -/** - * @brief Get ADC SS1 FIFO Tail Pointer. - * @note The field contains the current tail pointer index, which is the - * next entry to be read from FIFO. - * @param ADCx ADC Instance. - * @retval Value between Min_Data=0x00 and Max_Data=0x0F - */ -__STATIC_INLINE uint32_t md_adc_get_ss1_fstat_tptr(ADC_TypeDef *ADCx) -{ - return (READ_BIT(ADCx->SS1_FSTAT, ADC_SS1_FSTAT_TPTR_MSK)>>ADC_SS1_FSTAT_TPTR_POSS); -} - -/** - * @brief Get ADC sample sequencer 1(SS1) Conversion Result Data. - * @note User can read conversion result data by reading this register. - * @param ADCx ADC Instance. - * @retval ADC Sampled Data. - */ -__STATIC_INLINE uint32_t md_adc_get_ss1_data(ADC_TypeDef *ADCx) -{ - return (uint32_t)(READ_REG(ADC->SS1_DATA)); -} - -/** - * @brief Set ADC SS2 Trigger Select. - * @note This field selects the trigger source for Sample Sequencer 1. - * @param ADCx ADC Instance. - * @param This parameter can be one of the following values: - * @arg @ref MD_ADC_SS_CON_SEL_SW - * @arg @ref MD_ADC_SS_CON_SEL_BS16T1 - * @arg @ref MD_ADC_SS_CON_SEL_ALWAYS - * @arg @ref MD_ADC_SS_CON_SEL_GP32C4T1 - * @arg @ref MD_ADC_SS_CON_SEL_GP16C4T1 - * @arg @ref MD_ADC_SS_CON_SEL_GP16C4T2 - * @arg @ref MD_ADC_SS_CON_SEL_GP16C4T3 - * @arg @ref MD_ADC_SS_CON_SEL_GP32C4T1 - * @arg @ref MD_ADC_SS_CON_SEL_GP16C2T1 - * @arg @ref MD_ADC_SS_CON_SEL_GP16C2T2 - * @arg @ref MD_ADC_SS_CON_SEL_GP16C2T3 - * @arg @ref MD_ADC_SS_CON_SEL_GP32C4T1 - * @arg @ref MD_ADC_SS_CON_SEL_GP16C2T4 - * @arg @ref MD_ADC_SS_CON_SEL_AD16C4T1 - * @arg @ref MD_ADC_SS_CON_SEL_GPIO - * @arg @ref MD_ADC_SS_CON_SEL_CMP0 - * @arg @ref MD_ADC_SS_CON_SEL_CMP1 - * @arg @ref MD_ADC_SS_CON_SEL_CMP2 - * @arg @ref MD_ADC_SS_CON_SEL_CMP3 - * @retval None - */ -__STATIC_INLINE void md_adc_set_ss2_con_sel(ADC_TypeDef *ADCx, uint32_t TrigSource) -{ - MODIFY_REG(ADCx->SS2_CON, ADC_SS2_CON_SEL_MSK, TrigSource<SS2_CON, ADC_SS2_CON_SEL_MSK)>>ADC_SS2_CON_SEL_POSS); -} - -/** - * @brief ADC Sample Sequencer 2 (SS2) Trigger Type select. - * @param ADCx ADC Instance. - * @param This parameter can be one of the following values: - * @arg @ref MD_ADC_SS_CON_TYP_EDGE - * @arg @ref MD_ADC_SS_COM_TYP_LEVEL - * @retval None - */ -__STATIC_INLINE void md_adc_set_ss2_con_type(ADC_TypeDef *ADCx, uint32_t TrigType) -{ - MODIFY_REG(ADCx->SS2_CON, ADC_SS2_CON_TYP_MSK, TrigType<SS2_CON, ADC_SS2_CON_TYP_MSK)>>ADC_SS2_CON_TYP_POS); -} - -/** - * @brief Set ADC Sample Sequencer 2(SS2) Priority. - * @note This field contains a binary-encoded value specifying the - * priority encoding of SS2. The prioriteies assigned to the - * sequencers must be uniquely mapped. - * @param ADCx ADC Instance. - * @param This parameter can be one of the following values: - * @arg @ref MD_ADC_SS_CON_PRI_HIGHEST - * @arg @ref MD_ADC_SS_CON_PRI_SECOND - * @arg @ref MD_ADC_SS_CON_PRI_THIRD - * @arg @ref MD_ADC_SS_CON_PRI_LOWEST - * @retval None - */ -__STATIC_INLINE void md_adc_set_ss2_con_pri(ADC_TypeDef *adcx, uint32_t priority) -{ - MODIFY_REG(adcx->SS2_CON, ADC_SS2_CON_PRI_MSK, priority<SS2_CON, ADC_SS2_CON_PRI_MSK)>>ADC_SS2_CON_PRI_POSS); -} - -/** - * @brief Enable One Shot Trigger Mode. - * @note When set HIGH, each trigger will only sample once and use one - * slot in FIFO. - * @param ADCx ADC Instance. - * @retval None. - */ -__STATIC_INLINE void md_adc_enable_ss2_con_one(ADC_TypeDef *adcx) -{ - SET_BIT(adcx->SS2_CON, ADC_SS2_CON_ONE_MSK); -} - -/** - * @brief Disable One Shot Trigger Mode. - * @param ADCx ADC Instance. - * @retval None. - */ -__STATIC_INLINE void md_adc_disable_ss2_con_one(ADC_TypeDef *adcx) -{ - CLEAR_BIT(adcx->SS2_CON, ADC_SS2_CON_ONE_MSK); -} - -/** - * @brief 4th Sample Input Select.. - * @param ADCx ADC Instance - * @param ADIN Pin: - * @arg @ref MD_ADC_SS_MUX_ADIN15 - * @arg @ref MD_ADC_SS_MUX_ADIN14 - * @arg @ref MD_ADC_SS_MUX_ADIN13 - * @arg @ref MD_ADC_SS_MUX_ADIN12 - * @arg @ref MD_ADC_SS_MUX_ADIN11 - * @arg @ref MD_ADC_SS_MUX_ADIN10 - * @arg @ref MD_ADC_SS_MUX_ADIN9 - * @arg @ref MD_ADC_SS_MUX_ADIN8 - * @arg @ref MD_ADC_SS_MUX_ADIN7 - * @arg @ref MD_ADC_SS_MUX_ADIN6 - * @arg @ref MD_ADC_SS_MUX_ADIN5 - * @arg @ref MD_ADC_SS_MUX_ADIN4 - * @arg @ref MD_ADC_SS_MUX_ADIN3 - * @arg @ref MD_ADC_SS_MUX_ADIN2 - * @arg @ref MD_ADC_SS_MUX_ADIN1 - * @arg @ref MD_ADC_SS_MUX_ADIN0 - */ -__STATIC_INLINE void md_adc_set_ss2_mux0_mux3(ADC_TypeDef *ADCx, uint32_t AdinPin) -{ - MODIFY_REG(ADCx->SS2_MUX0, ADC_SS2_MUX0_MUX3_MSK, AdinPin<SS2_MUX0, ADC_SS2_MUX0_MUX3_MSK)>>ADC_SS2_MUX0_MUX3_POSS); -} - -/** - * @brief 3rd Sample Input Select. - * @param ADCx ADC Instance. - * @param ADIN Pin: - * @arg @ref MD_ADC_SS_MUX_ADIN15 - * @arg @ref MD_ADC_SS_MUX_ADIN14 - * @arg @ref MD_ADC_SS_MUX_ADIN13 - * @arg @ref MD_ADC_SS_MUX_ADIN12 - * @arg @ref MD_ADC_SS_MUX_ADIN11 - * @arg @ref MD_ADC_SS_MUX_ADIN10 - * @arg @ref MD_ADC_SS_MUX_ADIN9 - * @arg @ref MD_ADC_SS_MUX_ADIN8 - * @arg @ref MD_ADC_SS_MUX_ADIN7 - * @arg @ref MD_ADC_SS_MUX_ADIN6 - * @arg @ref MD_ADC_SS_MUX_ADIN5 - * @arg @ref MD_ADC_SS_MUX_ADIN4 - * @arg @ref MD_ADC_SS_MUX_ADIN3 - * @arg @ref MD_ADC_SS_MUX_ADIN2 - * @arg @ref MD_ADC_SS_MUX_ADIN1 - * @arg @ref MD_ADC_SS_MUX_ADIN0 - */ -__STATIC_INLINE void md_adc_set_ss2_mux0_mux2(ADC_TypeDef *ADCx, uint32_t AdinPin) -{ - MODIFY_REG(ADCx->SS2_MUX0, ADC_SS2_MUX0_MUX2_MSK, AdinPin<SS2_MUX0, ADC_SS2_MUX0_MUX2_MSK)>>ADC_SS2_MUX0_MUX2_POSS); -} - -/** - * @brief 2nd Sample Input Select. - * @param ADCx ADC Instance. - * @param ADIN Pin: - * @arg @ref MD_ADC_SS_MUX_ADIN15 - * @arg @ref MD_ADC_SS_MUX_ADIN14 - * @arg @ref MD_ADC_SS_MUX_ADIN13 - * @arg @ref MD_ADC_SS_MUX_ADIN12 - * @arg @ref MD_ADC_SS_MUX_ADIN11 - * @arg @ref MD_ADC_SS_MUX_ADIN10 - * @arg @ref MD_ADC_SS_MUX_ADIN9 - * @arg @ref MD_ADC_SS_MUX_ADIN8 - * @arg @ref MD_ADC_SS_MUX_ADIN7 - * @arg @ref MD_ADC_SS_MUX_ADIN6 - * @arg @ref MD_ADC_SS_MUX_ADIN5 - * @arg @ref MD_ADC_SS_MUX_ADIN4 - * @arg @ref MD_ADC_SS_MUX_ADIN3 - * @arg @ref MD_ADC_SS_MUX_ADIN2 - * @arg @ref MD_ADC_SS_MUX_ADIN1 - * @arg @ref MD_ADC_SS_MUX_ADIN0 - */ -__STATIC_INLINE void md_adc_set_ss2_mux0_mux1(ADC_TypeDef *ADCx, uint32_t AdinPin) -{ - MODIFY_REG(ADCx->SS2_MUX0, ADC_SS2_MUX0_MUX1_MSK, AdinPin<SS2_MUX0, ADC_SS2_MUX0_MUX1_MSK)>>ADC_SS2_MUX0_MUX1_POSS); -} - -/** - * @brief 1st Sample Input Select. - * @param ADCx ADC Instance. - * @param ADIN Pin: - * @arg @ref MD_ADC_SS_MUX_ADIN15 - * @arg @ref MD_ADC_SS_MUX_ADIN14 - * @arg @ref MD_ADC_SS_MUX_ADIN13 - * @arg @ref MD_ADC_SS_MUX_ADIN12 - * @arg @ref MD_ADC_SS_MUX_ADIN11 - * @arg @ref MD_ADC_SS_MUX_ADIN10 - * @arg @ref MD_ADC_SS_MUX_ADIN9 - * @arg @ref MD_ADC_SS_MUX_ADIN8 - * @arg @ref MD_ADC_SS_MUX_ADIN7 - * @arg @ref MD_ADC_SS_MUX_ADIN6 - * @arg @ref MD_ADC_SS_MUX_ADIN5 - * @arg @ref MD_ADC_SS_MUX_ADIN4 - * @arg @ref MD_ADC_SS_MUX_ADIN3 - * @arg @ref MD_ADC_SS_MUX_ADIN2 - * @arg @ref MD_ADC_SS_MUX_ADIN1 - * @arg @ref MD_ADC_SS_MUX_ADIN0 - */ -__STATIC_INLINE void md_adc_set_ss2_mux0_mux0(ADC_TypeDef *ADCx, uint32_t AdinPin) -{ - MODIFY_REG(ADCx->SS2_MUX0, ADC_SS2_MUX0_MUX0_MSK, AdinPin<SS2_MUX0, ADC_SS2_MUX0_MUX0_MSK)>>ADC_SS2_MUX0_MUX0_POSS); -} - -/** - * @brief Set ADC_SS2_MUX0 register value. - * @param ADCx ADC Instance. - * @param ADC_SS2_MUX0 Register - * @retval None - */ -__STATIC_INLINE void md_adc_set_ss2_mux0(ADC_TypeDef *ADCx, uint32_t RegValue) -{ - WRITE_REG(ADCx->SS2_MUX0, RegValue); -} - -/** - * @brief Get ADC_SS2_MUX0 register value. - * @param ADCx ADC Instance. - * @retval ADC_SS2_MUX0 Register - */ -__STATIC_INLINE uint32_t md_adc_get_ss2_mux0(ADC_TypeDef *ADCx) -{ - return READ_REG(ADCx->SS2_MUX0); -} - -/** - * @brief 4th Sample Interrupt Enable. - * @param ADCx ADC Instance. - * @retval None. - */ -__STATIC_INLINE void md_adc_enable_ss2_end_ie3(ADC_TypeDef *ADCx) -{ - SET_BIT(ADCx->SS2_END, ADC_SS2_END_IE3_MSK); -} - -/** - * @brief 4th Sample Interrupt Disable. - * @param ADCx ADC Instance. - * @retval None. - */ -__STATIC_INLINE void md_adc_disable_ss2_end_ie3(ADC_TypeDef *ADCx) -{ - CLEAR_BIT(ADCx->SS2_END, ADC_SS2_END_IE3_MSK); -} - -/** - * @brief Check if 4th Sample Interrupt is enabled. - * @param ADCx ADC Instance. - * @retval State of bit (1 or 0). - */ -__STATIC_INLINE uint32_t md_adc_is_enabled_ss2_end_ie3(ADC_TypeDef *ADCx) -{ - return (READ_BIT(ADCx->SS2_END, ADC_SS2_END_IE3_MSK) == (ADC_SS2_END_IE3_MSK)); -} - -/** - * @brief 3rd Sample Interrupt Enable. - * @param ADCx ADC Instance. - * @retval None. - */ -__STATIC_INLINE void md_adc_enable_ss2_end_ie2(ADC_TypeDef *ADCx) -{ - SET_BIT(ADCx->SS2_END, ADC_SS2_END_IE2_MSK); -} - -/** - * @brief 3rd Sample Interrupt Disable. - * @param ADCx ADC Instance. - * @retval None. - */ -__STATIC_INLINE void md_adc_disable_ss2_end_ie2(ADC_TypeDef *ADCx) -{ - CLEAR_BIT(ADCx->SS2_END, ADC_SS2_END_IE2_MSK); -} - -/** - * @brief Check if 3rd Sample Interrupt is enabled. - * @param ADCx ADC Instance. - * @retval State of bit (1 or 0). - */ -__STATIC_INLINE uint32_t md_adc_is_enabled_ss2_end_ie2(ADC_TypeDef *ADCx) -{ - return (READ_BIT(ADCx->SS2_END, ADC_SS2_END_IE2_MSK) == (ADC_SS2_END_IE2_MSK)); -} - -/** - * @brief 2nd Sample Interrupt Enable. - * @param ADCx ADC Instance. - * @retval None. - */ -__STATIC_INLINE void md_adc_enable_ss2_end_ie1(ADC_TypeDef *ADCx) -{ - SET_BIT(ADCx->SS1_END, ADC_SS2_END_IE1_MSK); -} - -/** - * @brief 2nd Sample Interrupt Enable. - * @param ADCx ADC Instance. - * @retval None. - */ -__STATIC_INLINE void md_adc_disable_ss2_end_ie1(ADC_TypeDef *ADCx) -{ - CLEAR_BIT(ADCx->SS2_END, ADC_SS2_END_IE1_MSK); -} - -/** - * @brief Check if 2nd Sample Interrupt Enable is enabled. - * @param ADCx ADC Instance. - * @retval State of bit (1 or 0). - */ -__STATIC_INLINE uint32_t md_adc_is_enabled_ss2_end_ie1(ADC_TypeDef *ADCx) -{ - return (READ_BIT(ADCx->SS1_END, ADC_SS2_END_IE1_MSK) == (ADC_SS2_END_IE1_MSK)); -} - -/** - * @brief 1st Sample Interrupt Enable - * @param ADCx ADC Instance. - * @retval None. - */ -__STATIC_INLINE void md_adc_enable_ss2_end_ie0(ADC_TypeDef *ADCx) -{ - SET_BIT(ADCx->SS2_END, ADC_SS2_END_IE0_MSK); -} - -/** - * @brief 4th Sample Interrupt Disable. - * @param ADCx ADC Instance. - * @retval None. - */ -__STATIC_INLINE void md_adc_disable_ss2_end_ie0(ADC_TypeDef *ADCx) -{ - CLEAR_BIT(ADCx->SS2_END, ADC_SS2_END_IE0_MSK); -} - -/** - * @brief Check if 1st Sample Interrupt is enabled. - * @param ADCx ADC Instance. - * @retval State of bit (1 or 0). - */ -__STATIC_INLINE uint32_t md_adc_is_enabled_ss2_end_ie0(ADC_TypeDef *ADCx) -{ - return (READ_BIT(ADCx->SS2_END, ADC_SS2_END_IE0_MSK) == (ADC_SS2_END_IE0_MSK)); -} - -/** - * @brief Set ADC SS2 END sample. - * @param ADCx ADC Instance. - * @param End Value Min_Value=0x00 Max_Value=0x03 - * @retval None - */ -__STATIC_INLINE void md_adc_set_ss2_end_end(ADC_TypeDef *ADCx, uint32_t EndValue) -{ - MODIFY_REG(ADCx->SS2_END, ADC_SS2_END_END_MSK, EndValue<SS2_END, ADC_SS2_END_END_MSK)>>ADC_SS2_END_END_POSS); -} - -/** - * @brief Set ADC_SS2_End Control Register. - * @param ADCx ADC Instance. - * @param ADC_SS2_End Register Value. - * @retval None. - */ -__STATIC_INLINE void md_adc_set_ss2_end(ADC_TypeDef *ADCx, uint32_t RegValue) -{ - MODIFY_REG(ADCx->SS2_END, ADC_SS2_END_END_MSK, RegValue); -} - -/** - * @brief Get ADC_SS2_End Control Register. - * @param ADCx ADC Instance. - * @retval ADC_SS2_End Register Value. - */ -__STATIC_INLINE uint32_t md_adc_get_ss2_end(ADC_TypeDef *ADCx) -{ - return READ_REG(ADCx->SS2_END); -} - -/** - * @brief Set ADC Sample Sequencer 2(SS2) FIFO Overflow status. - * @note When the FIFO is full and a write was requested, the - * most recent write is dropped. - * @param ADCx ADC Instance. - * @retval None. - */ -__STATIC_INLINE void md_adc_set_ss2_fstat_ov(ADC_TypeDef *ADCx) -{ - SET_BIT(ADCx->SS2_END, ADC_SS2_FSTAT_OV_MSK); -} - -/** - * @brief Get ADC Sample Sequencer 2(SS2) FIFO Overflow status. - * @param ADCx ADC Instance. - * @retval State of bit (1 or 0). - */ -__STATIC_INLINE uint32_t md_adc_get_ss2_fstat_ov(ADC_TypeDef *ADCx) -{ - return (READ_BIT(ADCx->SS2_FSTAT, ADC_SS2_FSTAT_OV_MSK)>>ADC_SS2_FSTAT_OV_POS); -} - -/** - * @brief Check if ADC Sample Sequencer 2(SS2) FIFO Overflow status is actived. - * @param ADCx ADC Instance. - * @retval State of bit (1 or 0). - */ -__STATIC_INLINE uint32_t md_adc_is_active_flag_ss2_fstat_ov(ADC_TypeDef *ADCx) -{ - return (READ_BIT(ADCx->SS2_FSTAT, ADC_SS2_FSTAT_OV_MSK) == (ADC_SS2_FSTAT_OV_MSK)); -} - -/** - * @brief Get ADC SS2 FIFO Full status. - * @param ADCx ADC Instance. - * @retval State of bit (1 or 0). - */ -__STATIC_INLINE uint32_t md_adc_get_ss2_fstat_full(ADC_TypeDef *ADCx) -{ - return (READ_BIT(ADCx->SS2_FSTAT, ADC_SS2_FSTAT_FULL_MSK)>>ADC_SS2_FSTAT_FULL_POS); -} - -/** - * @brief Check if ADC SS2 FIFO Full is actived. - * @param ADCx ADC Instance. - * @retval State of bit (1 or 0). - */ -__STATIC_INLINE uint32_t md_adc_is_active_flag_ss2_fstat_full(ADC_TypeDef *ADCx) -{ - return (READ_BIT(ADCx->SS2_FSTAT, ADC_SS2_FSTAT_FULL_MSK) == (ADC_SS2_FSTAT_FULL_MSK)); -} - -/** - * @brief Set ADC Sample Sequencer 2(SS2) FIFO Underflow status. - * @note When the FIFO is empty and a read was requested. - * The problematic read does not move the FIFO pointers, and 0s are returned. - * @param ADCx ADC Instance. - * @retval None. - */ -__STATIC_INLINE void md_adc_set_ss2_fstat_uv(ADC_TypeDef *ADCx) -{ - SET_BIT(ADCx->SS2_END, ADC_SS2_FSTAT_UV_MSK); -} - -/** - * @brief Get ADC Sample Sequencer 2(SS2) FIFO Underflow status. - * @param ADCx ADC Instance. - * @retval State of bit (1 or 0). - */ -__STATIC_INLINE uint32_t md_adc_get_ss2_fstat_uv(ADC_TypeDef *ADCx) -{ - return (READ_BIT(ADCx->SS2_FSTAT, ADC_SS2_FSTAT_UV_MSK)>>ADC_SS2_FSTAT_UV_POS); -} - -/** - * @brief Check if ADC Sample Sequencer 2(SS2) FIFO Underflow status is actived. - * @param ADCx ADC Instance. - * @retval State of bit (1 or 0). - */ -__STATIC_INLINE uint32_t md_adc_is_active_flag_ss2_fstat_uv(ADC_TypeDef *ADCx) -{ - return (READ_BIT(ADCx->SS2_FSTAT, ADC_SS2_FSTAT_UV_MSK) == (ADC_SS2_FSTAT_UV_MSK)); -} - -/** - * @brief Get ADC SS2 FIFO Empty status. - * @param ADCx ADC Instance. - * @retval State of bit (1 or 0). - */ -__STATIC_INLINE uint32_t md_adc_get_ss2_fstat_empty(ADC_TypeDef *ADCx) -{ - return (READ_BIT(ADCx->SS2_FSTAT, ADC_SS2_FSTAT_EMPTY_MSK)>>ADC_SS2_FSTAT_EMPTY_POS); -} - -/** - * @brief Check if ADC SS2 FIFO Empty is actived. - * @param ADCx ADC Instance - * @retval State of bit (1 or 0). - */ -__STATIC_INLINE uint32_t md_adc_is_active_flag_ss2_fstat_empty(ADC_TypeDef *ADCx) -{ - return (READ_BIT(ADCx->SS2_FSTAT, ADC_SS2_FSTAT_EMPTY_MSK) == (ADC_SS2_FSTAT_EMPTY_MSK)); -} - -/** - * @brief Get ADC SS2 FIFO Head Pointer. - * @param ADCx ADC Instance. - * @retval Return value between Min_Data=0x00 and Max_Data=0x0F. - */ -__STATIC_INLINE uint32_t md_adc_get_ss2_fstat_hptr(ADC_TypeDef *ADCx) -{ - return (READ_BIT(ADCx->SS2_FSTAT, ADC_SS2_FSTAT_HPTR_MSK)>>ADC_SS2_FSTAT_HPTR_POSS); -} - -/** - * @brief Get ADC SS2 FSTAT TPTR - * @param ADCx ADC Instance - * @retval Return value between Min_Data=0x00 and Max_Data=0x0F. - */ -__STATIC_INLINE uint32_t md_adc_get_ss2_fstat_tptr(ADC_TypeDef *ADCx) -{ - return (READ_BIT(ADCx->SS2_FSTAT, ADC_SS2_FSTAT_TPTR_MSK)>>ADC_SS2_FSTAT_TPTR_POSS); -} - -/** - * @brief Get ADC sample sequencer 2(SS2) Conversion Result Data. - * @note User can read conversion result data by reading this register. - * @param ADCx ADC Instance. - * @retval ADC Sampled Data. - */ -__STATIC_INLINE uint32_t md_adc_get_ss2_data(ADC_TypeDef *ADCx) -{ - return (uint32_t)(READ_REG(ADC->SS2_DATA)); -} - -/** - * @brief Set SS3 Trigger Select. - * @note This field selects the trigger source for Sample Sequencer 3. - * @param ADCx ADC Instance. - * @param This parameter can be one of the following values: - * @arg @ref MD_ADC_SS_CON_SEL_SW - * @arg @ref MD_ADC_SS_CON_SEL_BS16T1 - * @arg @ref MD_ADC_SS_CON_SEL_ALWAYS - * @arg @ref MD_ADC_SS_CON_SEL_GP32C4T1 - * @arg @ref MD_ADC_SS_CON_SEL_GP16C4T1 - * @arg @ref MD_ADC_SS_CON_SEL_GP16C4T2 - * @arg @ref MD_ADC_SS_CON_SEL_GP16C4T3 - * @arg @ref MD_ADC_SS_CON_SEL_GP32C4T1 - * @arg @ref MD_ADC_SS_CON_SEL_GP16C2T1 - * @arg @ref MD_ADC_SS_CON_SEL_GP16C2T2 - * @arg @ref MD_ADC_SS_CON_SEL_GP16C2T3 - * @arg @ref MD_ADC_SS_CON_SEL_GP32C4T1 - * @arg @ref MD_ADC_SS_CON_SEL_GP16C2T4 - * @arg @ref MD_ADC_SS_CON_SEL_AD16C4T1 - * @arg @ref MD_ADC_SS_CON_SEL_GPIO - * @arg @ref MD_ADC_SS_CON_SEL_CMP0 - * @arg @ref MD_ADC_SS_CON_SEL_CMP1 - * @arg @ref MD_ADC_SS_CON_SEL_CMP2 - * @arg @ref MD_ADC_SS_CON_SEL_CMP3 - * @retval None - */ -__STATIC_INLINE void md_adc_set_ss3_con_sel(ADC_TypeDef *ADCx, uint32_t TrigSource) -{ - MODIFY_REG(ADCx->SS3_CON, ADC_SS3_CON_SEL_MSK, TrigSource<SS3_CON, ADC_SS3_CON_SEL_MSK)>>ADC_SS3_CON_SEL_POSS); -} - -/** - * @brief ADC Sample Sequencer 2 (SS2) Trigger Type select. - * @param ADCx ADC Instance. - * @param This parameter can be one of the following values: - * @arg @ref MD_ADC_SS_CON_TYP_EDGE - * @arg @ref MD_ADC_SS_COM_TYP_LEVEL - * @retval None - */ -__STATIC_INLINE void md_adc_set_ss3_con_type(ADC_TypeDef *ADCx, uint32_t TrigType) -{ - MODIFY_REG(ADCx->SS3_CON, ADC_SS3_CON_TYP_MSK, TrigType<SS3_CON, ADC_SS3_CON_TYP_MSK)>>ADC_SS3_CON_TYP_POS); -} - -/** - * @brief Set ADC Sample Sequencer 3(SS3) Priority. - * @note This field contains a binary-encoded value specifying the - * priority encoding of SS2. The prioriteies assigned to the - * sequencers must be uniquely mapped. - * @param ADCx ADC Instance. - * @param This parameter can be one of the following values: - * @arg @ref MD_ADC_SS_CON_PRI_HIGHEST - * @arg @ref MD_ADC_SS_CON_PRI_SECOND - * @arg @ref MD_ADC_SS_CON_PRI_THIRD - * @arg @ref MD_ADC_SS_CON_PRI_LOWEST - * @retval None - */ -__STATIC_INLINE void md_adc_set_ss3_con_pri(ADC_TypeDef *adcx, uint32_t priority) -{ - MODIFY_REG(adcx->SS3_CON, ADC_SS3_CON_PRI_MSK, priority<SS3_CON, ADC_SS3_CON_PRI_MSK)>>ADC_SS3_CON_PRI_POSS); -} - -/** - * @brief Enable ADC sample sequencer 3(SS3) one shot mode. - * @note When set HIGH, each trigger will only sample once and use one - * slot in FIFO. - * @param ADCx ADC Instance. - * @retval None. - */ -__STATIC_INLINE void md_adc_enable_ss3_con_one(ADC_TypeDef *adcx) -{ - SET_BIT(adcx->SS3_CON, ADC_SS3_CON_ONE_MSK); -} - -/** - * @brief Disable ADC sample sequencer 3(SS3) one shot mode. - * @param ADCx ADC Instance. - * @retval None. - */ -__STATIC_INLINE void md_adc_disable_ss3_con_one(ADC_TypeDef *adcx) -{ - CLEAR_BIT(adcx->SS3_CON, ADC_SS3_CON_ONE_MSK); -} - -/** - * @brief Enable ADC SS3 1th Sample Interrupt Enable. - * @param ADCx ADC Instance. - * @retval None. - */ -__STATIC_INLINE void md_adc_enable_ss3_end_ie0(ADC_TypeDef *ADCx) -{ - SET_BIT(ADCx->SS3_END, ADC_SS3_END_IE0_MSK); -} - -/** - * @brief Disable ADC SS3 1th Sample Interrupt Enable. - * @param ADCx ADC Instance. - * @retval None. - */ -__STATIC_INLINE void md_adc_disable_ss3_end_ie0(ADC_TypeDef *ADCx) -{ - CLEAR_BIT(ADCx->SS3_END, ADC_SS3_END_IE0_MSK); -} - -/** - * @brief Check if ADC SS3 1th Sample Interrupt is enabled. - * @param ADCx ADC Instance. - * @retval State of bit (1 or 0). - */ -__STATIC_INLINE uint32_t md_adc_is_enabled_ss3_end_ie0(ADC_TypeDef *ADCx) -{ - return (READ_BIT(ADCx->SS3_END, ADC_SS3_END_IE0_MSK) == (ADC_SS3_END_IE0_MSK)); -} - -/** - * @brief Set ADC SS3 END sample. - * @param ADCx ADC Instance. - * @param End Value Min_Value=0x00 Max_Value=0x01. - * @retval None. - */ -__STATIC_INLINE void md_adc_set_ss3_end_end(ADC_TypeDef *ADCx, uint32_t EndValue) -{ - MODIFY_REG(ADCx->SS3_END, ADC_SS3_END_END_MSK, EndValue<SS3_END, ADC_SS3_END_END_MSK)>>ADC_SS3_END_END_POS); -} - -/** - * @brief Set ADC_SS3_End Control Register. - * @param ADCx ADC Instance. - * @param ADC_SS3_END Register Value. - * @retval None. - */ -__STATIC_INLINE void md_adc_set_ss3_end(ADC_TypeDef *ADCx, uint32_t RegValue) -{ - MODIFY_REG(ADCx->SS2_END, ADC_SS3_END_END_MSK, RegValue); -} - -/** - * @brief Get ADC_SS3_End Control Register - * @param ADCx ADC Instance. - * @retval ADC_SS3_End Register Value. - */ -__STATIC_INLINE uint32_t md_adc_get_ss3_end(ADC_TypeDef *ADCx) -{ - return READ_REG(ADCx->SS3_END); -} - -/** - * @brief Set ADC Sample Sequencer 3 (SS3) FIFO Overflow status. - * @note When the FIFO is full and a write was requested, the - * most recent write is dropped. - * @param ADCx ADC Instance. - * @retval None. - */ -__STATIC_INLINE void md_adc_set_ss3_fstat_ov(ADC_TypeDef *ADCx) -{ - SET_BIT(ADCx->SS3_END, ADC_SS3_FSTAT_OV_MSK); -} - -/** - * @brief Get ADC Sample Sequencer 3 (SS3) FIFO Overflow status. - * @param ADCx ADC Instance. - * @retval State of bit (1 or 0). - */ -__STATIC_INLINE uint32_t md_adc_get_ss3_fstat_ov(ADC_TypeDef *ADCx) -{ - return (READ_BIT(ADCx->SS3_FSTAT, ADC_SS3_FSTAT_OV_MSK)>>ADC_SS3_FSTAT_OV_POS); -} - -/** - * @brief Check if ADC Sample Sequencer 3 (SS3) FIFO Overflow status is actived. - * @param ADCx ADC Instance. - * @retval State of bit (1 or 0). - */ -__STATIC_INLINE uint32_t md_adc_is_active_flag_ss3_fstat_ov(ADC_TypeDef *ADCx) -{ - return (READ_BIT(ADCx->SS3_FSTAT, ADC_SS3_FSTAT_OV_MSK) == (ADC_SS3_FSTAT_OV_MSK)); -} - -/** - * @brief Get ADC SS3 FIFO Full status. - * @param ADCx ADC Instance. - * @retval State of bit (1 or 0). - */ -__STATIC_INLINE uint32_t md_adc_get_ss3_fstat_full(ADC_TypeDef *ADCx) -{ - return (READ_BIT(ADCx->SS3_FSTAT, ADC_SS3_FSTAT_FULL_MSK)>>ADC_SS3_FSTAT_FULL_POS); -} - -/** - * @brief Check if ADC SS3 FIFO Full status is actived. - * @param ADCx ADC Instance. - * @retval State of bit (1 or 0). - */ -__STATIC_INLINE uint32_t md_adc_is_active_flag_ss3_fstat_full(ADC_TypeDef *ADCx) -{ - return (READ_BIT(ADCx->SS3_FSTAT, ADC_SS3_FSTAT_FULL_MSK) == (ADC_SS3_FSTAT_FULL_MSK)); -} - -/** - * @brief Set ADC Sample Sequencer 3 (SS3) FIFO Underflow status. - * @note When the FIFO is empty and a read was requested. - * The problematic read does not move the FIFO pointers, and 0s are returned. - * @param ADCx ADC Instance. - * @retval None. - */ -__STATIC_INLINE void md_adc_set_ss3_fstat_uv(ADC_TypeDef *ADCx) -{ - SET_BIT(ADCx->SS3_END, ADC_SS3_FSTAT_UV_MSK); -} - -/** - * @brief Get ADC Sample Sequencer 3 (SS3) FIFO Underflow status. - * @param ADCx ADC Instance. - * @retval State of bit (1 or 0). - */ -__STATIC_INLINE uint32_t md_adc_get_ss3_fstat_uv(ADC_TypeDef *ADCx) -{ - return (READ_BIT(ADCx->SS3_FSTAT, ADC_SS3_FSTAT_UV_MSK)>>ADC_SS3_FSTAT_UV_POS); -} - -/** - * @brief Check if ADC Sample Sequencer 3 (SS3) FIFO Underflow status is actived. - * @param ADCx ADC Instance. - * @retval State of bit (1 or 0). - */ -__STATIC_INLINE uint32_t md_adc_is_active_flag_ss3_fstat_uv(ADC_TypeDef *ADCx) -{ - return (READ_BIT(ADCx->SS3_FSTAT, ADC_SS3_FSTAT_UV_MSK) == (ADC_SS3_FSTAT_UV_MSK)); -} - -/** - * @brief Get ADC SS3 FIFO Empty. - * @param ADCx ADC Instance. - * @retval State of bit (1 or 0). - */ -__STATIC_INLINE uint32_t md_adc_get_ss3_fstat_empty(ADC_TypeDef *ADCx) -{ - return (READ_BIT(ADCx->SS3_FSTAT, ADC_SS3_FSTAT_EMPTY_MSK)>>ADC_SS3_FSTAT_EMPTY_POS); -} - -/** - * @brief Check if ADC SS3 FIFO Empty is actived. - * @param ADCx ADC Instance. - * @retval State of bit (1 or 0). - */ -__STATIC_INLINE uint32_t md_adc_is_active_flag_ss3_fstat_empty(ADC_TypeDef *ADCx) -{ - return (READ_BIT(ADCx->SS3_FSTAT, ADC_SS3_FSTAT_EMPTY_MSK) == (ADC_SS3_FSTAT_EMPTY_MSK)); -} - -/** - * @brief Get ADC SS3 FIFO Head Pointer. - * @param ADCx ADC Instance. - * @retval Value between Min_Data=0x00 and Max_Data=0x01. - */ -__STATIC_INLINE uint32_t md_adc_get_ss23_fstat_hptr(ADC_TypeDef *ADCx) -{ - return (READ_BIT(ADCx->SS3_FSTAT, ADC_SS3_FSTAT_HPTR_MSK)>>ADC_SS3_FSTAT_HPTR_POSS); -} - -/** - * @brief Get ADC SS3 FIFO Tail Pointer. - * @param ADCx ADC Instance. - * @retval Value between Min_Data=0x00 and Max_Data=0x01. - */ -__STATIC_INLINE uint32_t md_adc_get_ss3_fstat_tptr(ADC_TypeDef *ADCx) -{ - return (READ_BIT(ADCx->SS3_FSTAT, ADC_SS3_FSTAT_TPTR_MSK)>>ADC_SS3_FSTAT_TPTR_POSS); -} - -/** - * @brief Get ADC sample sequencer 3(SS3) Conversion Result Data. - * @note User can read conversion result data by reading this register. - * @param ADCx ADC Instance. - * @retval ADC Sampled Data. - */ -__STATIC_INLINE uint32_t md_adc_get_ss3_data(ADC_TypeDef *ADCx) -{ - return (uint32_t)(READ_REG(ADC->SS3_DATA)); -} - -/** @defgroup MD_ADC_PM_WRITE_READ Common Write and read registers Macros - * @} - */ -#endif - -void md_adc_init(ADC_TypeDef *ADCx, md_adc_inittypedef *ADC_InitStruct,uint8_t *); -void md_adc_calibration_data(double, double ,double * ,double *); -void md_adc_get_data(uint8_t, double, double, uint16_t *); -/** - * @} MD_ADC_Public_Macros - */ - -/** @} ADC - */ - -/** - * @} Micro_Driver - */ - - -#ifdef __cplusplus -} -#endif - -#endif - -/******************* (C) COPYRIGHT Eastsoft Microelectronics *****END OF FILE****/ diff --git a/bsp/essemi/es32f0271/libraries/ES32F027x_MD_StdPeriph_Driver/Include/md_aes.h b/bsp/essemi/es32f0271/libraries/ES32F027x_MD_StdPeriph_Driver/Include/md_aes.h deleted file mode 100644 index e4e16693d5..0000000000 --- a/bsp/essemi/es32f0271/libraries/ES32F027x_MD_StdPeriph_Driver/Include/md_aes.h +++ /dev/null @@ -1,941 +0,0 @@ -/** - ****************************************************************************** - * @file md_aes.h - * @brief M601 AES Head File. - * - * @version V0.01 - * @date 28/11/2018 - * @author Eastsoft AE Team - * @note - * detailed description - * - * Copyright (C) 2018 Shanghai Eastsoft Microelectronics Co., Ltd. ALL rights reserved. - ******************************************************************************* - */ - -/* Define to prevent recursive inclusion -------------------------------------*/ -#ifndef __MD_AES_H__ -#define __MD_AES_H__ - -#ifdef __cplusplus -extern "C" { -#endif - -/* Includes -------------------------------------------------------------------*/ -#include "es32f0271.h" - -/** @addtogroup Micro_Driver - * @{ - */ - -#if defined (AES) - -/** @defgroup AES AES - * @brief AES micro driver - * @{ - */ - -/* Private Types --------------------------------------------------------------*/ -/* Private Variables ----------------------------------------------------------*/ -/* Private Macros -------------------------------------------------------------*/ -/* Public Types ---------------------------------------------------------------*/ -/** @defgroup MD_AES_INIT AES public init structure - * @brief - * @{ - */ -typedef struct -{ - volatile uint8_t aes_con_bl; - volatile uint8_t aes_con_mode; - volatile uint32_t aes_key[4]; - volatile uint32_t aes_iv[4]; - volatile uint32_t aes_din[4]; - volatile uint32_t aes_dout[4]; -} md_aes_init_typedef; -/** - * @} MD_AES_INIT - */ - -/* Public constants -----------------------------------------------------------*/ -/** @defgroup MD_AES_Public_Constants AES Public Constants - * @brief - * @{ - */ - -/** @defgroup MD_AES_CON_registers AES Control Registers - * @brief - * @{ - */ -#define MD_AES_CON_READY_BUSY 0 /*!< This allow user to read AES Encryption/Decryption Ready Status. */ -#define MD_AES_CON_READY_READY 1 /*!< This allow user to read AES Encryption/Decryption Ready Status. */ -#define MD_AES_CON_OT_DMA_ST_PASS 1 /*!< This allow user to read AES DMA Output Status. */ -#define MD_AES_CON_OT_DMA_ST_FAIL 0 /*!< This allow user to read AES DMA Output Status. */ -#define MD_AES_CON_IT_DMA_ST_PASS 1 /*!< This allow user to read AES DMA Input Status. */ -#define MD_AES_CON_IT_DMA_ST_FAIL 0 /*!< This allow user to read AES DMA Input Status. */ -#define MD_AES_CON_OT_DEPTH_0 0 /*!< This allow user to read AES DIO data depth status (X=0). */ -#define MD_AES_CON_OT_DEPTH_1 1 /*!< This allow user to read AES DIO data depth status (X=1). */ -#define MD_AES_CON_OT_DEPTH_2 2 /*!< This allow user to read AES DIO data depth status (X=2). */ -#define MD_AES_CON_OT_DEPTH_3 3 /*!< This allow user to read AES DIO data depth status (X=3). */ -#define MD_AES_CON_IT_DEPTH_0 0 /*!< This allow user to read AES DIO data depth status (X=0). */ -#define MD_AES_CON_IT_DEPTH_1 1 /*!< This allow user to read AES DIO data depth status (X=1). */ -#define MD_AES_CON_IT_DEPTH_2 2 /*!< This allow user to read AES DIO data depth status (X=2). */ -#define MD_AES_CON_IT_DEPTH_3 3 /*!< This allow user to read AES DIO data depth status (X=3). */ -#define MD_AES_CON_RE_INIT_SET 1 /*!< This allow user to set AES Re-initial. */ -#define MD_AES_CON_RE_INIT_UNSET 0 /*!< This allow user to set AES Re-initial. */ -#define MD_AES_CON_DMA_EN_INPUT_ENABLE (1 << 0) /*!< This allow user to set AES DMA Function Enable. 0:AES input DMA disable */ -#define MD_AES_CON_DMA_EN_INPUT_DISABLE (0 << 0) /*!< This allow user to set AES DMA Function Enable. 1:AES input DMA enable */ -#define MD_AES_CON_DMA_EN_OUTPUT_ENABLE (1 << 1 /*!< This allow user to set AES DMA Function Enable. 0:AES output DMA disable */ -#define MD_AES_CON_DMA_EN_OUTPUT_DISABLE (0 << 1) /*!< This allow user to set AES DMA Function Enable. 1:AES outut DMA enable */ -#define MD_AES_CON_BL_CBC 0 /*!< This allow user to set Block Cipher Encryption / Decryption Mode. 000:CBC */ -#define MD_AES_CON_BL_CFB 1 /*!< This allow user to set Block Cipher Encryption / Decryption Mode. 001:CFB */ -#define MD_AES_CON_BL_OFB 2 /*!< This allow user to set Block Cipher Encryption / Decryption Mode. 010:OFB */ -#define MD_AES_CON_BL_CTR 3 /*!< This allow user to set Block Cipher Encryption / Decryption Mode. 011:CTR */ -#define MD_AES_CON_BL_ECB 4 /*!< This allow user to set Block Cipher Encryption / Decryption Mode. 100:ECB */ -#define MD_AES_CON_BL_GCM 5 /*!< This allow user to set Block Cipher Encryption / Decryption Mode. 101:GCM */ -#define MD_AES_CON_REV_NORMAL 0 /*!< This allow user to set AES Input Reverse. 0:Normal Mode */ -#define MD_AES_CON_REV_REVERSE 1 /*!< This allow user to set AES Input Reverse. 1:KEY, IV, DI, DO Byte Reverse Mode */ -#define MD_AES_CON_MODE_ENCRYPT 0 /*!< This allow user to set AES Mode Control. 0:Encryption Mode */ -#define MD_AES_CON_MODE_DECRYPT 1 /*!< This allow user to set AES Mode Control. 1:Decryption Mode */ -#define MD_AES_CON_START 1 /*!< This allow user to set AES Start. AES function will start after this bit is set to 1. */ -/** - * @} MD_AES_CON_registers - */ - -/** @defgroup MD_AES_IER_registers AES Interrupt Enable Registers - * @brief - * @{ - */ -#define MD_AES_IER_DECIE 1 /*!< This allow user to set AES Decryption Interrupt Enable. */ -#define MD_AES_IER_ENCIE 1 /*!< This allow user to set AES Encryption Interrupt Enable. */ -/** - * @} MD_AES_IER_registers - */ - -/** @defgroup MD_AES_IDR_registers AES Interrupt Disable Registers - * @brief - * @{ - */ -#define MD_AES_IDR_DECID 1 /*!< This allow user to set AES Decryption Interrupt Disable. */ -#define MD_AES_IDR_ENCID 1 /*!< This allow user to set AES Encryption Interrupt Disable. */ -/** - * @} MD_AES_IDR_registers - */ - -/** @defgroup MD_AES_IVS_registers AES Interrupt Valid Status Registers - * @brief - * @{ - */ -#define MD_AES_IVS_DECIVS_DISABLE 0 /*!< This allow user to set AES Decryption Interrupt Valid Status. 0:AES Decryption interrupt is disabled. */ -#define MD_AES_IVS_DECIVS_ENABLE 1 /*!< This allow user to set AES Decryption Interrupt Valid Status. 1:AES Decryption interrupt is enabled. */ -#define MD_AES_IVS_ENCIVS_DISABLE 0 /*!< This allow user to set AES Encryption Interrupt Valid Status. 0:AES Encryption interrupt is disabled. */ -#define MD_AES_IVS_ENCIVS_ENABLE 1 /*!< This allow user to set AES Encryption Interrupt Valid Status. 1:AES Encryption interrupt is enabled. */ -/** - * @} MD_AES_IVS_registers - */ - -/** @defgroup MD_AES_RIF_registers AES Raw Interrupt Flag Registers - * @brief - * @{ - */ -#define MD_AES_RIF_DECRIF_NO_INTERRUPT 0 /*!< This allow user to set AES Decryption Raw Interrupt Flag Status. 0: No interrupt. */ -#define MD_AES_RIF_DECRIF_INTERRUPT 1 /*!< This allow user to set AES Decryption Raw Interrupt Flag Status. 1: AES Decryption interrupt is asserting. */ -#define MD_AES_RIF_ENCRIF_NO_INTERRUPT 0 /*!< This allow user to set AES Encryption Raw Interrupt Flag Status. 0: No interrupt. */ -#define MD_AES_RIF_ENCRIF_INTERRUPT 1 /*!< This allow user to set AES Encryption Raw Interrupt Flag Status. 1: AES Encryption interrupt is asserting. */ -/** - * @} MD_AES_RIF_registers - */ - -/** @defgroup MD_AES_IFM_registers AES Interrupt Flag Mask Registers - * @brief - * @{ - */ -#define MD_AES_IFM_DECRIF_MASK 0 /*!< This allow user to set AES Decryption Interrupt Flag Masked Status. 0: No interrupt or the interrupt has been masked. */ -#define MD_AES_IFM_DECRIF_SIGNAL 1 /*!< This allow user to set AES Decryption Interrupt Flag Masked Status. 1: AES Decryption interrupt has been signalled. */ -#define MD_AES_IFM_ENCRIF_MASK 0 /*!< This allow user to set AES Encryption Interrupt Flag Masked Status. 0: No interrupt or the interrupt has been masked. */ -#define MD_AES_IFM_ENCRIF_SIGNAL 1 /*!< This allow user to set AES Encryption Interrupt Flag Masked Status. 1: AES Encryption interrupt has been signalled. */ -/** - * @} MD_AES_IFM_registers - */ - -/** @defgroup MD_AES_ICR_registers AES Interrupt Clear Registers - * @brief - * @{ - */ -#define MD_AES_ICR_DECICR 1 /*!< This allow user to set AES Decryption Interrupt Clear. User can set this bit to clear AES Decryption interrupt status. */ -#define MD_AES_ICR_ENCICR 1 /*!< This allow user to set AES Decryption Interrupt Clear. User can set this bit to clear AES Encryption interrupt status. */ -/** - * @} MD_AES_ICR_registers - */ - -/** - * @} MD_AES_Public_Constants - */ - -/* Public macro ---------------------------------------------------------------*/ -/** @defgroup MD_AES_Public_Macros AES Public Macros - * @brief - * @{ - */ - -/** - * @brief AES Control Register - * @param AES Instance - * @param value This parameter can be one of the following values: - * @arg @ref MD_AES_CON_READY_BUSY 0 - * @arg @ref MD_AES_CON_READY_READY 1 - * @arg @ref MD_AES_CON_OT_DMA_ST_PASS 1 - * @arg @ref MD_AES_CON_OT_DMA_ST_FAIL 0 - * @arg @ref MD_AES_CON_IT_DMA_ST_PASS 1 - * @arg @ref MD_AES_CON_IT_DMA_ST_FAIL 0 - * @arg @ref MD_AES_CON_OT_DEPTH_0 0 - * @arg @ref MD_AES_CON_OT_DEPTH_1 1 - * @arg @ref MD_AES_CON_OT_DEPTH_2 2 - * @arg @ref MD_AES_CON_OT_DEPTH_3 3 - * @arg @ref MD_AES_CON_IT_DEPTH_0 0 - * @arg @ref MD_AES_CON_IT_DEPTH_1 1 - * @arg @ref MD_AES_CON_IT_DEPTH_2 2 - * @arg @ref MD_AES_CON_IT_DEPTH_3 3 - * @arg @ref MD_AES_CON_RE_INIT_SET 1 - * @arg @ref MD_AES_CON_RE_INIT_UNSET 0 - * @arg @ref MD_AES_CON_DMA_EN_INPUT_ENABLE (1 << 0) - * @arg @ref MD_AES_CON_DMA_EN_INPUT_DISABLE (0 << 0) - * @arg @ref MD_AES_CON_DMA_EN_OUTPUT_ENABLE (1 << 1) - * @arg @ref MD_AES_CON_DMA_EN_OUTPUT_DISABLE (0 << 1) - * @arg @ref MD_AES_CON_BL_CBC 0 - * @arg @ref MD_AES_CON_BL_CFB 1 - * @arg @ref MD_AES_CON_BL_OFB 2 - * @arg @ref MD_AES_CON_BL_CTR 3 - * @arg @ref MD_AES_CON_BL_ECB 4 - * @arg @ref MD_AES_CON_BL_GCM 5 - * @arg @ref MD_AES_CON_REV_NORMAL 0 - * @arg @ref MD_AES_CON_REV_REVERSE 1 - * @arg @ref MD_AES_CON_MODE_ENCRYPT 0 - * @arg @ref MD_AES_CON_MODE_DECRYPT 1 - * @arg @ref MD_AES_CON_START 1 - * @retval None. - */ -__STATIC_INLINE void md_aes_set_con(AES_TypeDef *aes, uint32_t value) -{ - WRITE_REG(aes->CON, value); -} - -/** - * @brief AES Control Register - * @param AES Instance - * @retval value This parameter can be one of the following values: - * @arg @ref MD_AES_CON_READY_BUSY 0 - * @arg @ref MD_AES_CON_READY_READY 1 - * @arg @ref MD_AES_CON_OT_DMA_ST_PASS 1 - * @arg @ref MD_AES_CON_OT_DMA_ST_FAIL 0 - * @arg @ref MD_AES_CON_IT_DMA_ST_PASS 1 - * @arg @ref MD_AES_CON_IT_DMA_ST_FAIL 0 - * @arg @ref MD_AES_CON_OT_DEPTH_0 0 - * @arg @ref MD_AES_CON_OT_DEPTH_1 1 - * @arg @ref MD_AES_CON_OT_DEPTH_2 2 - * @arg @ref MD_AES_CON_OT_DEPTH_3 3 - * @arg @ref MD_AES_CON_IT_DEPTH_0 0 - * @arg @ref MD_AES_CON_IT_DEPTH_1 1 - * @arg @ref MD_AES_CON_IT_DEPTH_2 2 - * @arg @ref MD_AES_CON_IT_DEPTH_3 3 - * @arg @ref MD_AES_CON_RE_INIT_SET 1 - * @arg @ref MD_AES_CON_RE_INIT_UNSET 0 - * @arg @ref MD_AES_CON_DMA_EN_INPUT_ENABLE (1 << 0) - * @arg @ref MD_AES_CON_DMA_EN_INPUT_DISABLE (0 << 0) - * @arg @ref MD_AES_CON_DMA_EN_OUTPUT_ENABLE (1 << 1) - * @arg @ref MD_AES_CON_DMA_EN_OUTPUT_DISABLE (0 << 1) - * @arg @ref MD_AES_CON_BL_CBC 0 - * @arg @ref MD_AES_CON_BL_CFB 1 - * @arg @ref MD_AES_CON_BL_OFB 2 - * @arg @ref MD_AES_CON_BL_CTR 3 - * @arg @ref MD_AES_CON_BL_ECB 4 - * @arg @ref MD_AES_CON_BL_GCM 5 - * @arg @ref MD_AES_CON_REV_NORMAL 0 - * @arg @ref MD_AES_CON_REV_REVERSE 1 - * @arg @ref MD_AES_CON_MODE_ENCRYPT 0 - * @arg @ref MD_AES_CON_MODE_DECRYPT 1 - * @arg @ref MD_AES_CON_START 1 - */ -__STATIC_INLINE uint32_t md_aes_get_con(AES_TypeDef *aes) -{ - return (READ_REG(aes->CON)); -} - -/** - * @brief AES Encryption / Decryption Ready Status - * @param AES Instance - * @retval value This parameter can be one of the following values: - * @arg @ref MD_AES_CON_READY_BUSY 0 - * @arg @ref MD_AES_CON_READY_READY 1 - */ -__STATIC_INLINE uint32_t md_aes_get_con_ready(AES_TypeDef *aes) -{ - return ((READ_BIT(aes->CON, AES_CON_READY_MSK) >> AES_CON_READY_POS) & 0x1); -} - -/** - * @brief AES DMA Output Status - * @param AES Instance - * @retval value This parameter can be one of the following values: - * @arg @ref MD_AES_CON_OT_DMA_ST_PASS 0 - * @arg @ref MD_AES_CON_OT_DMA_ST_FAIL 1 - */ -__STATIC_INLINE uint32_t md_aes_get_con_ot_dma_st(AES_TypeDef *aes) -{ - return ((READ_BIT(aes->CON, AES_CON_OT_DMA_ST_MSK) >> AES_CON_OT_DMA_ST_POS) & 0x1); -} - -/** - * @brief AES DMA Intput Status - * @param AES Instance - * @retval value This parameter can be one of the following values: - * @arg @ref MD_AES_CON_IT_DMA_ST_PASS 0 - * @arg @ref MD_AES_CON_IT_DMA_ST_FAIL 1 - */ -__STATIC_INLINE uint32_t md_aes_get_con_it_dma_st(AES_TypeDef *aes, uint32_t value) -{ - return ((READ_BIT(aes->CON, AES_CON_IT_DMA_ST_MSK) >> AES_CON_IT_DMA_ST_POS) & 0x1); -} - -/** - * @brief AES DIO data depth status (X=0,1,2,3) - * @param AES Instance - * @retval value This parameter can be one of the following values: - * @arg @ref MD_AES_CON_OT_DEPTH_0 0 - * @arg @ref MD_AES_CON_OT_DEPTH_1 1 - * @arg @ref MD_AES_CON_OT_DEPTH_2 2 - * @arg @ref MD_AES_CON_OT_DEPTH_3 3 - */ -__STATIC_INLINE uint32_t md_aes_get_con_ot_depth(AES_TypeDef *aes) -{ - return ((READ_BIT(aes->CON, AES_CON_OT_DEPTH_MSK) >> AES_CON_OT_DEPTH_POSS) & 0x3); -} - -/** - * @brief AES DIO data depth status (X=0,1,2,3) - * @param AES Instance - * @retval value This parameter can be one of the following values: - * @arg @ref MD_AES_CON_IT_DEPTH_0 0 - * @arg @ref MD_AES_CON_IT_DEPTH_1 1 - * @arg @ref MD_AES_CON_IT_DEPTH_2 2 - * @arg @ref MD_AES_CON_IT_DEPTH_3 3 - */ -__STATIC_INLINE uint32_t md_aes_get_con_it_depth(AES_TypeDef *aes) -{ - return ((READ_BIT(aes->CON, AES_CON_IT_DEPTH_MSK) >> AES_CON_IT_DEPTH_POSS) & 0x3); -} - -/** - * @brief AES Re-initial - * @param AES Instance - * @param value This parameter can be one of the following values: - * @arg @ref MD_AES_CON_RE_INIT_SET 1 - * @arg @ref MD_AES_CON_RE_INIT_UNSET 0 - * @retval None. - */ -__STATIC_INLINE void md_aes_set_con_re_init(AES_TypeDef *aes, uint32_t value) -{ - MODIFY_REG(aes->CON, AES_CON_RE_INIT_MSK, (value << AES_CON_RE_INIT_POS)); -} - -/** - * @brief AES Re-initial - * @param AES Instance - * @retval value This parameter can be one of the following values: - * @arg @ref MD_AES_CON_RE_INIT_SET 1 - * @arg @ref MD_AES_CON_RE_INIT_UNSET 0 - */ -__STATIC_INLINE uint32_t md_aes_get_con_re_init(AES_TypeDef *aes) -{ - - return ((READ_BIT(aes->CON, AES_CON_RE_INIT_MSK) >> AES_CON_RE_INIT_POS) & 0x1); -} - -/** - * @brief AES DMA Function Enable - * @param AES Instance - * @param value This parameter can be one of the following values: - * @arg @ref MD_AES_CON_DMA_EN_INPUT_ENABLE (1 << 0) - * @arg @ref MD_AES_CON_DMA_EN_INPUT_DISABLE (0 << 0) - * @arg @ref MD_AES_CON_DMA_EN_OUTPUT_ENABLE (1 << 1) - * @arg @ref MD_AES_CON_DMA_EN_OUTPUT_DISABLE (0 << 1) - * @retval None. - */ -__STATIC_INLINE void md_aes_set_con_dma_en(AES_TypeDef *aes, uint32_t value) -{ - MODIFY_REG(aes->CON, AES_CON_DMA_EN_MSK, (value << AES_CON_DMA_EN_POSS)); -} - -/** - * @brief AES DMA Function Enable - * @param AES Instance - * @retval value This parameter can be one of the following values: - * @arg @ref MD_AES_CON_DMA_EN_INPUT_ENABLE (1 << 0) - * @arg @ref MD_AES_CON_DMA_EN_INPUT_DISABLE (0 << 0) - * @arg @ref MD_AES_CON_DMA_EN_OUTPUT_ENABLE (1 << 1) - * @arg @ref MD_AES_CON_DMA_EN_OUTPUT_DISABLE (0 << 1) - */ -__STATIC_INLINE uint32_t md_aes_get_con_dma_en(AES_TypeDef *aes) -{ - return ((READ_BIT(aes->CON, AES_CON_DMA_EN_MSK) >> AES_CON_DMA_EN_POSS) & 0x3); -} - -/** - * @brief Block Cipher Encryption / Decryption Mode - * @param AES Instance - * @param value This parameter can be one of the following values: - * @arg @ref MD_AES_CON_BL_CBC 0 - * @arg @ref MD_AES_CON_BL_CFB 1 - * @arg @ref MD_AES_CON_BL_OFB 2 - * @arg @ref MD_AES_CON_BL_CTR 3 - * @arg @ref MD_AES_CON_BL_ECB 4 - * @arg @ref MD_AES_CON_BL_GCM 5 - * @retval None. - */ -__STATIC_INLINE void md_aes_set_con_bl(AES_TypeDef *aes, uint32_t value) -{ - MODIFY_REG(aes->CON, AES_CON_BL_MSK, (value << AES_CON_BL_POSS)); -} - -/** - * @brief Block Cipher Encryption / Decryption Mode - * @param AES Instance - * @retval value This parameter can be one of the following values: - * @arg @ref MD_AES_CON_BL_CBC 0 - * @arg @ref MD_AES_CON_BL_CFB 1 - * @arg @ref MD_AES_CON_BL_OFB 2 - * @arg @ref MD_AES_CON_BL_CTR 3 - * @arg @ref MD_AES_CON_BL_ECB 4 - * @arg @ref MD_AES_CON_BL_GCM 5 - */ -__STATIC_INLINE uint32_t md_aes_get_con_bl(AES_TypeDef *aes) -{ - return ((READ_BIT(aes->CON, AES_CON_BL_MSK) >> AES_CON_BL_POSS) & 0x7); -} - -/** - * @brief AES Input Reverse - * @param AES Instance - * @param value This parameter can be one of the following values: - * @arg @ref MD_AES_CON_REV_NORMAL 0 - * @arg @ref MD_AES_CON_REV_REVERSE 1 - * @retval None. - */ -__STATIC_INLINE void md_aes_set_con_rev(AES_TypeDef *aes, uint32_t value) -{ - MODIFY_REG(aes->CON, AES_CON_REV_MSK, (value << AES_CON_REV_POS)); -} - -/** - * @brief AES Input Reverse - * @param AES Instance - * @retval value This parameter can be one of the following values: - * @arg @ref MD_AES_CON_REV_NORMAL 0 - * @arg @ref MD_AES_CON_REV_REVERSE 1 - */ -__STATIC_INLINE uint32_t md_aes_get_con_rev(AES_TypeDef *aes) -{ - return ((READ_BIT(aes->CON, AES_CON_REV_MSK) >> AES_CON_REV_POS) & 0x1); -} - -/** - * @brief AES Mode Control - * @param AES Instance - * @param value This parameter can be one of the following values: - * @arg @ref MD_AES_CON_MODE_ENCRYPT 0 - * @arg @ref MD_AES_CON_MODE_DECRYPT 1 - * @retval None. - */ -__STATIC_INLINE void md_aes_set_con_mode(AES_TypeDef *aes, uint32_t value) -{ - MODIFY_REG(aes->CON, AES_CON_MODE_MSK, (value << AES_CON_MODE_POS)); -} - -/** - * @brief AES Mode Control - * @param AES Instance - * @retval value This parameter can be one of the following values: - * @arg @ref MD_AES_CON_MODE_ENCRYPT 0 - * @arg @ref MD_AES_CON_MODE_DECRYPT 1 - */ -__STATIC_INLINE uint32_t md_aes_get_con_mode(AES_TypeDef *aes) -{ - return ((READ_BIT(aes->CON, AES_CON_MODE_MSK) >> AES_CON_MODE_POS) & 0x1); -} - -/** - * @brief AES Start - * @param AES Instance - * @param value This parameter can be one of the following values: - * @arg @ref MD_AES_CON_START 1 - * @retval None. - */ -__STATIC_INLINE void md_aes_set_con_start(AES_TypeDef *aes, uint32_t value) -{ - MODIFY_REG(aes->CON, AES_CON_START_MSK, (value << AES_CON_START_POS)); -} - -/** - * @brief AES Start - * @param AES Instance - * @retval value This parameter can be one of the following values: - * @arg @ref MD_AES_CON_START 1 - */ -__STATIC_INLINE uint32_t md_aes_get_con_start(AES_TypeDef *aes) -{ - return ((READ_BIT(aes->CON, AES_CON_START_MSK) >> AES_CON_START_POS) & 0x1); -} - -/** - * @brief AES Interrupt Enable Register - * @param AES Instance - * @param value This parameter can be one of the following values: - * @arg @ref MD_AES_IER_DECIE 1 - * @arg @ref MD_AES_IER_ENCIE 1 - * @retval None. - */ -__STATIC_INLINE void md_aes_set_ier(AES_TypeDef *aes, uint32_t value) -{ - WRITE_REG(aes->IER, value); -} - -/** - * @brief AES Decryption Interrupt Enable - * @param AES Instance - * @retval None. - */ -__STATIC_INLINE void md_aes_enable_ier_decie(AES_TypeDef *aes) -{ - MODIFY_REG(aes->IER, AES_IER_DECIE_MSK, (1 << AES_IER_DECIE_POS)); -} - -/** - * @brief AES Encryption Interrupt Enable - * @param AES Instance - * @retval None. - */ -__STATIC_INLINE void md_aes_enable_ier_encie(AES_TypeDef *aes) -{ - MODIFY_REG(aes->IER, AES_IER_ENCIE_MSK, (1 << AES_IER_ENCIE_POS)); -} - -/** - * @brief AES Interrupt Disable Register - * @param AES Instance - * @param value This parameter can be one of the following values: - * @arg @ref MD_AES_IDR_DECID 1 - * @arg @ref MD_AES_IDR_ENCID 1 - * @retval None. - */ -__STATIC_INLINE void md_aes_set_idr(AES_TypeDef *aes, uint32_t value) -{ - WRITE_REG(aes->IDR, value); -} - -/** - * @brief AES Decryption Interrupt Disable - * @param AES Instance - * @retval None. - */ -__STATIC_INLINE void md_aes_disable_idr_decid(AES_TypeDef *aes) -{ - MODIFY_REG(aes->IDR, AES_IDR_DECID_MSK, (1 << AES_IDR_DECID_POS)); -} - -/** - * @brief AES Encryption Interrupt Disable - * @param AES Instance - * @retval None. - */ -__STATIC_INLINE void md_aes_disable_idr_encid(AES_TypeDef *aes) -{ - MODIFY_REG(aes->IDR, AES_IDR_DECID_MSK, (1 << AES_IDR_DECID_POS)); -} - -/** - * @brief AES Interrupt Valid Status Register - * @param AES Instance - * @retval value This parameter can be one of the following values: - * @arg @ref MD_AES_IVS_DECIVS_DISABLE 0 - * @arg @ref MD_AES_IVS_DECIVS_ENABLE 1 - * @arg @ref MD_AES_IVS_ENCIVS_DISABLE 0 - * @arg @ref MD_AES_IVS_ENCIVS_ENABLE 1 - */ -__STATIC_INLINE uint32_t md_aes_get_ivs(AES_TypeDef *aes) -{ - return (READ_REG(aes->IVS)); -} - -/** - * @brief AES Decryption Interrupt Valid Status - * @param AES Instance - * @retval value This parameter can be one of the following values: - * @arg value true, false - */ -__STATIC_INLINE bool md_aes_is_enabled_ivs_decivs(AES_TypeDef *aes) -{ - return ((READ_BIT(aes->IVS, AES_IVS_DECIVS_MSK) >> AES_IVS_DECIVS_POS) & 0x1) ? true : false; -} - -/** - * @brief AES Encryption Interrupt Valid Status - * @param AES Instance - * @retval value This parameter can be one of the following values: - * @arg value true, false - */ -__STATIC_INLINE bool md_aes_is_enabled_ivs_encivs(AES_TypeDef *aes) -{ - return ((READ_BIT(aes->IVS, AES_IVS_ENCIVS_MSK) >> AES_IVS_ENCIVS_POS) & 0x1) ? true : false; -} - -/** - * @brief AES Raw Interrupt Flag Status - * @param AES Instance - * @retval value This parameter can be one of the following values: - * @arg @reg MD_AES_RIF_DECRIF_NO_INTERRUPT 0 - * @arg @reg MD_AES_RIF_DECRIF_INTERRUPT 1 - */ -__STATIC_INLINE uint32_t md_aes_get_rif(AES_TypeDef *aes) -{ - return (READ_REG(aes->RIF)); -} - -/** - * @brief AES Encryption Raw Interrupt Flag Status - * @param AES Instance - * @retval value This parameter can be one of the following values: - * @arg value true, false - */ -__STATIC_INLINE bool md_aes_is_active_rif_decrif(AES_TypeDef *aes) -{ - return ((READ_BIT(aes->RIF, AES_RIF_DECRIF_MSK) >> AES_RIF_DECRIF_POS) & 0x1) ? true : false; -} - -/** - * @brief AES Encryption Raw Interrupt Flag Status - * @param Mode This parameter can be one of the following values: - * @arg value true, false - * @retval None. - */ -__STATIC_INLINE bool md_aes_is_active_rif_encrif(AES_TypeDef *aes) -{ - return ((READ_BIT(aes->RIF, AES_RIF_ENCRIF_MSK) >> AES_RIF_ENCRIF_POS) & 0x1) ? true : false; -} - -/** - * @brief AES Interrupt Flag Mask Status Register - * @param AES Instance - * @retval value This parameter can be one of the following values: - * @arg @reg MD_AES_IFM_DECRIF_MASK 0 - * @arg @reg MD_AES_IFM_DECRIF_SIGNAL 1 - * @arg @reg MD_AES_IFM_ENCRIF_MASK 0 - * @arg @reg MD_AES_IFM_ENCRIF_SIGNAL 1 - */ -__STATIC_INLINE uint32_t md_aes_get_ifm(AES_TypeDef *aes) -{ - return (READ_REG(aes->IFM)); -} - -/** - * @brief AES Interrupt Flag Mask Status Register - * @param AES Instance - * @retval value This parameter can be one of the following values: - * @arg value true, false - */ -__STATIC_INLINE bool md_aes_is_active_ifm_decifm(AES_TypeDef *aes) -{ - return ((READ_BIT(aes->IFM, AES_IFM_DECIFM_MSK) >> AES_IFM_DECIFM_POS) & 0x1) ? true : false; -} - -/** - * @brief AES Interrupt Flag Mask Status Register - * @param AES Instance - * @retval value This parameter can be one of the following values: - * @arg value true, false - */ -__STATIC_INLINE bool md_aes_is_active_ifm_encifm(AES_TypeDef *aes) -{ - return ((READ_BIT(aes->IFM, AES_IFM_ENCIFM_MSK) >> AES_IFM_ENCIFM_POS) & 0x1) ? true : false; -} - -/** - * @brief AES Interrupt Clear Register - * @param AES Instance - * @param value This parameter can be one of the following values: - * @arg @reg MD_AES_ICR_DECICR 1 - * @arg @reg MD_AES_ICR_ENCICR 1 - * @retval None. - */ -__STATIC_INLINE void md_aes_set_icr(AES_TypeDef *aes, uint32_t value) -{ - WRITE_REG(aes->ICR, value); -} - -/** - * @brief AES Decryption Interrupt Clear - * @param AES Instance - * @retval None. - */ -__STATIC_INLINE void md_aes_clear_icr_decicr(AES_TypeDef *aes) -{ - MODIFY_REG(aes->ICR, AES_ICR_DECICR_MSK, (1 << AES_ICR_DECICR_POS)); -} - -/** - * @brief AES Encryption Interrupt Clear - * @param AES Instance - * @retval None. - */ -__STATIC_INLINE void md_aes_clear_icr_encicr(AES_TypeDef *aes) -{ - MODIFY_REG(aes->ICR, AES_ICR_ENCICR_MSK, (1 << AES_ICR_ENCICR_POS)); -} - -/** - * @brief AES 128-bit Input / Ouput Data Register - * @param AES Instance - * @param value This parameter can be one of the following values: - * @arg Minimum 0x0000000 - * @arg Maximum 0xFFFFFFF - * @retval None. - */ -__STATIC_INLINE void md_aes_set_dio(AES_TypeDef *aes, uint32_t value) -{ - WRITE_REG(aes->DIO, value); -} - -/** - * @brief AES 128-bit Input / Ouput Data Register - * @param AES Instance - * @retval value - * @arg Minimum 0x0000000 - * @arg Maximum 0xFFFFFFF - */ -//#pragma push -//#pragma O0 -__STATIC_INLINE uint32_t md_aes_get_dio(AES_TypeDef *aes) -{ - return (READ_REG(aes->DIO)); -} -//#pragma pop - -/** - * @brief AES 128-bit Keyword Register 0 - * @param AES Instance - * @param value This parameter can be one of the following values: - * @arg Minimum 0x0000000 - * @arg Maximum 0xFFFFFFF - * @retval None. - */ -__STATIC_INLINE void md_aes_set_key0(AES_TypeDef *aes, uint32_t value) -{ - WRITE_REG(aes->KEY0, value); -} - -/** - * @brief AES 128-bit Keyword Register 0 - * @param AES Instance - * @retval value - * @arg Minimum 0x0000000 - * @arg Maximum 0xFFFFFFF - */ -__STATIC_INLINE uint32_t md_aes_get_key0(AES_TypeDef *aes) -{ - return (READ_REG(aes->KEY0)); -} - -/** - * @brief AES 128-bit Keyword Register 1 - * @param AES Instance - * @param value This parameter can be one of the following values: - * @arg Minimum 0x0000000 - * @arg Maximum 0xFFFFFFF - * @retval None. - */ -__STATIC_INLINE void md_aes_set_key1(AES_TypeDef *aes, uint32_t value) -{ - WRITE_REG(aes->KEY1, value); -} - -/** - * @brief AES 128-bit Keyword Register 1 - * @param AES Instance - * @retval value - * @arg Minimum 0x0000000 - * @arg Maximum 0xFFFFFFF - */ -__STATIC_INLINE uint32_t md_aes_get_key1(AES_TypeDef *aes) -{ - return (READ_REG(aes->KEY1)); -} - -/** - * @brief AES 128-bit Keyword Register 2 - * @param AES Instance - * @param value This parameter can be one of the following values: - * @arg Minimum 0x0000000 - * @arg Maximum 0xFFFFFFF - * @retval None. - */ -__STATIC_INLINE void md_aes_set_key2(AES_TypeDef *aes, uint32_t value) -{ - WRITE_REG(aes->KEY2, value); -} - -/** - * @brief AES 128-bit Keyword Register 2 - * @param AES Instance - * @retval value - * @arg Minimum 0x0000000 - * @arg Maximum 0xFFFFFFF - */ -__STATIC_INLINE uint32_t md_aes_get_key2(AES_TypeDef *aes) -{ - return (READ_REG(aes->KEY2)); -} - -/** - * @brief AES 128-bit Keyword Register 3 - * @param AES Instance - * @param value This parameter can be one of the following values: - * @arg Minimum 0x0000000 - * @arg Maximum 0xFFFFFFF - * @retval None. - */ -__STATIC_INLINE void md_aes_set_key3(AES_TypeDef *aes, uint32_t value) -{ - WRITE_REG(aes->KEY3, value); -} - -/** - * @brief AES 128-bit Keyword Register 3 - * @param AES Instance - * @retval value - * @arg Minimum 0x0000000 - * @arg Maximum 0xFFFFFFF - */ -__STATIC_INLINE uint32_t md_aes_get_key3(AES_TypeDef *aes) -{ - return (READ_REG(aes->KEY3)); -} - -/** - * @brief AES 128-bit Initial Vector Register 0 - * @param AES Instance - * @param value This parameter can be one of the following values: - * @arg Minimum 0x0000000 - * @arg Maximum 0xFFFFFFF - * @retval None. - */ -__STATIC_INLINE void md_aes_set_iv0(AES_TypeDef *aes, uint32_t value) -{ - WRITE_REG(aes->IV0, value); -} - -/** - * @brief AES 128-bit Initial Vector Register 0 - * @param AES Instance - * @retval value - * @arg Minimum 0x0000000 - * @arg Maximum 0xFFFFFFF - */ -__STATIC_INLINE uint32_t md_aes_get_iv0(AES_TypeDef *aes) -{ - return (READ_REG(aes->IV0)); -} - -/** - * @brief AES 128-bit Initial Vector Register 1 - * @param AES Instance - * @param value This parameter can be one of the following values: - * @arg Minimum 0x0000000 - * @arg Maximum 0xFFFFFFF - * @retval None. - */ -__STATIC_INLINE void md_aes_set_iv1(AES_TypeDef *aes, uint32_t value) -{ - WRITE_REG(aes->IV1, value); -} - -/** - * @brief AES 128-bit Initial Vector Register 1 - * @param AES Instance - * @retval value - * @arg Minimum 0x0000000 - * @arg Maximum 0xFFFFFFF - */ -__STATIC_INLINE uint32_t md_aes_get_iv1(AES_TypeDef *aes) -{ - return (READ_REG(aes->IV1)); -} - -/** - * @brief AES 128-bit Initial Vector Register 2 - * @param AES Instance - * @param value This parameter can be one of the following values: - * @arg Minimum 0x0000000 - * @arg Maximum 0xFFFFFFF - * @retval None. - */ -__STATIC_INLINE void md_aes_set_iv2(AES_TypeDef *aes, uint32_t value) -{ - WRITE_REG(aes->IV2, value); -} - -/** - * @brief AES 128-bit Initial Vector Register 2 - * @param AES Instance - * @retval value - * @arg Minimum 0x0000000 - * @arg Maximum 0xFFFFFFF - */ -__STATIC_INLINE uint32_t md_aes_get_iv2(AES_TypeDef *aes) -{ - return (READ_REG(aes->IV2)); -} - -/** - * @brief AES 128-bit Initial Vector Register 3 - * @param AES Instance - * @param value This parameter can be one of the following values: - * @arg Minimum 0x0000000 - * @arg Maximum 0xFFFFFFF - * @retval None. - */ -__STATIC_INLINE void md_aes_set_iv3(AES_TypeDef *aes, uint32_t value) -{ - WRITE_REG(aes->IV3, value); -} - -/** - * @brief AES 128-bit Initial Vector Register 3 - * @param AES Instance - * @retval value - * @arg Minimum 0x0000000 - * @arg Maximum 0xFFFFFFF - */ -__STATIC_INLINE uint32_t md_aes_get_iv3(AES_TypeDef *aes) -{ - return (READ_REG(aes->IV3)); -} - -/** - * @} MD_AES_Public_Macros - */ - -/** - * @} AES - */ - -#endif - -/** - * @} Micro_Driver - */ - -#ifdef __cplusplus -} -#endif - -#endif - -/******************* (C) COPYRIGHT Eastsoft Microelectronics *****END OF FILE****/ diff --git a/bsp/essemi/es32f0271/libraries/ES32F027x_MD_StdPeriph_Driver/Include/md_cmp.h b/bsp/essemi/es32f0271/libraries/ES32F027x_MD_StdPeriph_Driver/Include/md_cmp.h deleted file mode 100644 index b2b6d2b2e0..0000000000 --- a/bsp/essemi/es32f0271/libraries/ES32F027x_MD_StdPeriph_Driver/Include/md_cmp.h +++ /dev/null @@ -1,573 +0,0 @@ -/** - ****************************************************************************** - * @file md_CMP.h - * @brief ES32F0271 CMP Head File. - * - * @version V1.00.01 - * @date 11/23/2018 - * @author Eastsoft AE Team - * @note - * detailed description - * - * Copyright (C) 2018 Shanghai Eastsoft Microelectronics Co., Ltd. ALL rights reserved. - ******************************************************************************* - */ - - /* Define to prevent recursive inclusion -------------------------------------*/ -#ifndef __MD_CMP_H__ -#define __MD_CMP_H__ - -#ifdef __cplusplus -extern "C" { -#endif - -/* Includes -------------------------------------------------------------------*/ -#include "es32f0271.h" -#include "reg_cmp.h" - -/** @addtogroup Micro_Driver - * @{ - */ - -#if defined (CMP) -/** @defgroup CMP CMP - * @brief CMP micro driver - * @{ - */ - - -/* Private types --------------------------------------------------------------*/ -/* Private variables ----------------------------------------------------------*/ -/* Private constants ----------------------------------------------------------*/ -/* Private macros -------------------------------------------------------------*/ -/* Public types ---------------------------------------------------------------*/ -/* Public constants -----------------------------------------------------------*/ - -/** @defgroup MD_CMP_Public_Constants CMP Public Constants - * @{ - */ - -/** @defgroup MD_CMP_PC_CARS CMP Reference voltage - * @{ - */ -#define MD_CMP_CARS_1_25V (0x00000000UL) /*!< @brief Select CARS for 0.25*5V */ -#define MD_CMP_CARS_2_50V (0x00000001UL) /*!< @brief Select CARS for 0.5*5V */ -#define MD_CMP_CARS_3_75V (0x00000002UL) /*!< @brief Select CARS for 0.75*5V */ -#define MD_CMP_CARS_5_00V (0x00000003UL) /*!< @brief Select CARS for 5V */ - -/** - * @} MD_CMP_PC_CARS - */ - - -/** - * @} MD_CMP_Public_Constants - */ - -/* Public macro ---------------------------------------------------------------*/ -/** @defgroup MD_CMP_Public_Macros CMP Public Macros - * @{ - */ - -/** @defgroup MD_CMP_PF_CON CMP Control Register - * @{ - */ -/** - * @brief Set CMP control register (CMP_CON) - * @param cmp CMP Instance - * @param value The value write in CMP_CON - * @retval None - */ -__STATIC_INLINE void md_cmp_set_con(CMP_TypeDef *cmp, uint32_t value) -{ - WRITE_REG(cmp->CON, value); -} - -/** - * @brief Get CMP control register (CMP_CON) - * @param cmp CMP Instance - * @retval None - */ -__STATIC_INLINE uint32_t md_cmp_get_con(CMP_TypeDef *cmp) -{ - return (uint32_t)(READ_REG(cmp->CON)); -} - -/** - * @brief Enable Comparator 1 enable set - * @param cmp CMP Instance - * @retval None - */ -__STATIC_INLINE void md_cmp_enable_con_cmpon1(CMP_TypeDef *cmp) -{ - SET_BIT(cmp->CON, CMP_CON_CMPON1_MSK); -} -/** - * @brief Disable Comparator 1 enable set - * @param cmp CMP Instance - * @retval None - */ -__STATIC_INLINE void md_cmp_disable_con_cmpon1(CMP_TypeDef *cmp) -{ - CLEAR_BIT(cmp->CON, CMP_CON_CMPON1_MSK); -} - -/** - * @brief Check if Comparator 1 enable set is enable - * @param cmp CMP Instance - * @retval State of bit (1 or 0). - */ -__STATIC_INLINE uint32_t md_cmp_is_enable_con_cmpon1(CMP_TypeDef *cmp) -{ - return (READ_BIT(cmp->CON, CMP_CON_CMPON1_MSK)); -} - -/** - * @brief Enable Comparator 2 enable set - * @param cmp CMP Instance - * @retval None - */ -__STATIC_INLINE void md_cmp_enable_con_cmpon2(CMP_TypeDef *cmp) -{ - SET_BIT(cmp->CON, CMP_CON_CMPON2_MSK); -} -/** - * @brief Disable Comparator 2 enable set - * @param cmp CMP Instance - * @retval None - */ -__STATIC_INLINE void md_cmp_disable_con_cmpon2(CMP_TypeDef *cmp) -{ - CLEAR_BIT(cmp->CON, CMP_CON_CMPON2_MSK); -} - -/** - * @brief Check if Comparator 2 enable set is enable - * @param cmp CMP Instance - * @retval State of bit (1 or 0). - */ -__STATIC_INLINE uint32_t md_cmp_is_enable_con_caon2(CMP_TypeDef *cmp) -{ - return (READ_BIT(cmp->CON, CMP_CON_CMPON2_MSK)); -} - -/** - * @} MD_CMP_PF_CON - */ - - -/** @defgroup MD_CMP_PF_Configuration CMP Configuration Manangement - * @{ - */ - - -/** - * @brief Set CMP control register 1(CMP_CFG1) - * @param cmp CMP Instance - * @param value The value write in CMP_CFG1 - * @retval None - */ -__STATIC_INLINE void md_cmp_set_cfg1(CMP_TypeDef *cmp, uint32_t value) -{ - WRITE_REG(cmp->CFG1, value); -} -/** - * @brief Get CMP control register 1(CMP_CFG1) - * @param cmp CMP Instance - * @retval None - */ -__STATIC_INLINE uint32_t md_cmp_get_cfg1(CMP_TypeDef *cmp) -{ - return (uint32_t)(READ_REG(cmp->CFG1)); -} - - -/** - * @brief Set Comparator 1 reference voltage selection. - * @param cmp CMP Instance - * @param RefVol This parameter can be one of the following values: - * @arg MD_CMP_CARS_1_25V - * @arg MD_CMP_CARS_2_50V - * @arg MD_CMP_CARS_3_75V - * @arg MD_CMP_CARS_5_00V - * @retval None - */ -__STATIC_INLINE void md_cmp_set_cfg1_rs(CMP_TypeDef *cmp, uint32_t RefVol) -{ - MODIFY_REG(cmp->CFG1, CMP_CFG1_RS_MSK, RefVol<CFG1, CMP_CFG1_RS_MSK) >> CMP_CFG1_RS_POSS); -} - - -/** - * @brief Enable Comparator 1 Filter circuit - * @param cmp CMP Instance - * @retval None - */ -__STATIC_INLINE void md_cmp_enable_cfg1_fen(CMP_TypeDef *cmp) -{ - SET_BIT(cmp->CFG1, CMP_CFG1_FEN_MSK); -} -/** - * @brief Disable Comparator 1 Filter circuit - * @param cmp CMP Instance - * @retval None - */ -__STATIC_INLINE void md_cmp_disable_cfg1_fen(CMP_TypeDef *cmp) -{ - CLEAR_BIT(cmp->CFG1, CMP_CFG1_FEN_MSK); -} - -/** - * @brief Check if Comparator 1 Filter circuit is enable - * @param cmp CMP Instance - * @retval None - */ -__STATIC_INLINE uint32_t md_cmp_is_enable_cfg1_fen(CMP_TypeDef *cmp) -{ - return (READ_BIT(cmp->CFG1, CMP_CFG1_FEN_MSK) == (CMP_CFG1_FEN_MSK)); -} - - -/** - * @brief Enable comparator 1 reverse circuit enable - * @param cmp CMP Instance - * @retval None - */ -__STATIC_INLINE void md_cmp_enable_cfg1_psen(CMP_TypeDef *cmp) -{ - SET_BIT(cmp->CFG1, CMP_CFG1_PSEN_MSK); -} -/** - * @brief Disable comparator 1 reverse circuit enable - * @param cmp CMP Instance - * @retval None - */ -__STATIC_INLINE void md_cmp_disable_cfg1_psen(CMP_TypeDef *cmp) -{ - CLEAR_BIT(cmp->CFG1, CMP_CFG1_PSEN_MSK); -} - -/** - * @brief Check if comparator 1 reverse circuit enable is enable - * @param cmp CMP Instance - * @retval None - */ -__STATIC_INLINE uint32_t md_cmp_is_enable_cfg1_capsen(CMP_TypeDef *cmp) -{ - return (READ_BIT(cmp->CFG1, CMP_CFG1_PSEN_MSK) == (CMP_CFG1_PSEN_MSK) ); -} - - -/** - * @brief Enable Comparator 1 Negative input select - * @param cmp CMP Instance - * @retval None - */ -__STATIC_INLINE void md_cmp_enable_cfg1_insel(CMP_TypeDef *cmp) -{ - SET_BIT(cmp->CFG1, CMP_CFG1_INSEL_MSK); -} -/** - * @brief Disable Comparator 1 Negative input select - * @param cmp CMP Instance - * @retval None - */ -__STATIC_INLINE void md_cmp_disable_cfg1_insel(CMP_TypeDef *cmp) -{ - CLEAR_BIT(cmp->CFG1, CMP_CFG1_INSEL_MSK); -} - -/** - * @brief Check if comparator 1 Negative input select is enable - * @param cmp CMP Instance - * @retval None - */ -__STATIC_INLINE uint32_t md_cmp_is_enable_cfg1_insel(CMP_TypeDef *cmp) -{ - return (READ_BIT(cmp->CFG1, CMP_CFG1_INSEL_MSK) == (CMP_CFG1_INSEL_MSK)); -} - - -/** - * @brief Enable comparator 1 Positive input select - * @param cmp CMP Instance - * @retval None - */ -__STATIC_INLINE void md_cmp_enable_cfg1_ipsel(CMP_TypeDef *cmp) -{ - SET_BIT(cmp->CFG1, CMP_CFG1_IPSEL_MSK); -} -/** - * @brief Disable comparator 1 Positive input select - * @param cmp CMP Instance - * @retval None - */ -__STATIC_INLINE void md_cmp_disable_cfg1_ipsel(CMP_TypeDef *cmp) -{ - CLEAR_BIT(cmp->CFG1, CMP_CFG1_IPSEL_MSK); -} - -/** - * @brief Check if comparator 1 Positive input select is enable - * @param cmp CMP Instance - * @retval None - */ -__STATIC_INLINE uint32_t md_cmp_is_enable_cfg1_ipsel(CMP_TypeDef *cmp) -{ - return (READ_BIT(cmp->CFG1, CMP_CFG1_IPSEL_MSK) == (CMP_CFG1_IPSEL_MSK)); -} - - -/** - * @brief Set CMP control register 2(CMP_CFG2) - * @param cmp CMP Instance - * @param value The value write in CMP_CFG2 - * @retval None - */ -__STATIC_INLINE void md_cmp_set_cfg2(CMP_TypeDef *cmp, uint32_t value) -{ - WRITE_REG(cmp->CFG2, value); -} -/** - * @brief Get CMP control register 2(CMP_CFG2) - * @param cmp CMP Instance - * @retval None - */ -__STATIC_INLINE uint32_t md_cmp_get_cfg2(CMP_TypeDef *cmp) -{ - return (uint32_t)(READ_REG(cmp->CFG2)); -} - - -/** - * @brief Set Comparator 2 reference voltage selection. - * @param cmp CMP Instance - * @param RefVol This parameter can be one of the following values: - * @arg MD_CMP_CARS_1_25V - * @arg MD_CMP_CARS_2_50V - * @arg MD_CMP_CARS_3_75V - * @arg MD_CMP_CARS_5_00V - * @retval None - */ -__STATIC_INLINE void md_cmp_set_cfg2_rs(CMP_TypeDef *cmp, uint32_t RefVol) -{ - MODIFY_REG(cmp->CFG2, CMP_CFG2_RS_MSK, RefVol << CMP_CFG2_RS_POSS); -} - -/** - * @brief Return Comparator 2 reference voltage - * @param cmp CMP Instance - * @retval None - * @arg MD_CMP_CARS_1_25V - * @arg MD_CMP_CARS_2_50V - * @arg MD_CMP_CARS_3_75V - * @arg MD_CMP_CARS_5_00V - */ -__STATIC_INLINE uint32_t md_cmp_get_cfg2_rs(CMP_TypeDef *cmp) -{ - return (uint32_t)(READ_BIT(cmp->CFG2, CMP_CFG2_RS_MSK) >> CMP_CFG2_RS_POSS); -} - - -/** - * @brief Enable Comparator 2 Filter circuit - * @param cmp CMP Instance - * @retval None - */ -__STATIC_INLINE void md_cmp_enable_cfg2_fen(CMP_TypeDef *cmp) -{ - SET_BIT(cmp->CFG2, CMP_CFG2_FEN_MSK); -} -/** - * @brief Disable Comparator 2 Filter circuit - * @param cmp CMP Instance - * @retval None - */ -__STATIC_INLINE void md_cmp_disable_cfg2_fen(CMP_TypeDef *cmp) -{ - CLEAR_BIT(cmp->CFG2, CMP_CFG2_FEN_MSK); -} - -/** - * @brief Check if Comparator 2 Filter circuit is enable - * @param cmp CMP Instance - * @retval None - */ -__STATIC_INLINE uint32_t md_cmp_is_enable_cfg2_fen(CMP_TypeDef *cmp) -{ - return (READ_BIT(cmp->CFG2, CMP_CFG2_FEN_MSK) == (CMP_CFG2_FEN_MSK)) ; -} - - -/** - * @brief Enable comparator 2 reverse circuit enable - * @param cmp CMP Instance - * @retval None - */ -__STATIC_INLINE void md_cmp_enable_cfg2_psen(CMP_TypeDef *cmp) -{ - SET_BIT(cmp->CFG2, CMP_CFG2_PSEN_MSK); -} -/** - * @brief Disable comparator 2 reverse circuit enable - * @param cmp CMP Instance - * @retval None - */ -__STATIC_INLINE void md_cmp_disable_cfg2_psen(CMP_TypeDef *cmp) -{ - CLEAR_BIT(cmp->CFG2, CMP_CFG2_PSEN_MSK); -} - -/** - * @brief Check if comparator 2 reverse circuit enable is enable - * @param cmp CMP Instance - * @retval None - */ -__STATIC_INLINE uint32_t md_cmp_is_enable_cfg2_psen(CMP_TypeDef *cmp) -{ - return (READ_BIT(cmp->CFG2, CMP_CFG2_PSEN_MSK) == (CMP_CFG2_PSEN_MSK)); -} - - -/** - * @brief Enable Comparator 2 Negative input select - * @param cmp CMP Instance - * @retval None - */ -__STATIC_INLINE void md_cmp_enable_cfg2_insel(CMP_TypeDef *cmp) -{ - SET_BIT(cmp->CFG2, CMP_CFG2_INSEL_MSK); -} -/** - * @brief Disable Comparator 2 Negative input select - * @param cmp CMP Instance - * @retval None - */ -__STATIC_INLINE void md_cmp_disable_cfg2_insel(CMP_TypeDef *cmp) -{ - CLEAR_BIT(cmp->CFG2, CMP_CFG2_INSEL_MSK); -} - -/** - * @brief Check if comparator 2 Negative input select is enable - * @param cmp CMP Instance - * @retval None - */ -__STATIC_INLINE uint32_t md_cmp_is_enable_cfg2_insel(CMP_TypeDef *cmp) -{ - return (READ_BIT(cmp->CFG2, CMP_CFG2_INSEL_MSK) == (CMP_CFG2_INSEL_MSK)); -} - - -/** - * @brief Enable comparator 2 Positive input select - * @param cmp CMP Instance - * @retval None - */ -__STATIC_INLINE void md_cmp_enable_cfg2_ipsel(CMP_TypeDef *cmp) -{ - SET_BIT(cmp->CFG2, CMP_CFG2_IPSEL_MSK); -} -/** - * @brief Disable comparator 2 Positive input select - * @param cmp CMP Instance - * @retval None - */ -__STATIC_INLINE void md_cmp_disable_cfg2_ipsel(CMP_TypeDef *cmp) -{ - CLEAR_BIT(cmp->CFG2, CMP_CFG2_IPSEL_MSK); -} - -/** - * @brief Check if comparator 2 Positive input select is enable - * @param cmp CMP Instance - * @retval None - */ -__STATIC_INLINE uint32_t md_cmp_is_enable_cfg2_ipsel(CMP_TypeDef *cmp) -{ - return (READ_BIT(cmp->CFG2, CMP_CFG2_IPSEL_MSK) == (CMP_CFG2_IPSEL_MSK)); -} - - -/** - * @} MD_CMP_PF_Configuration - */ - -/** @defgroup MD_CMP_PC_RULT CMP Comparator Output Register. - * @{ - */ - -/** - * @brief Return Comparator output result(CMP_RULT) - * @param cmp CMP Instance - * @retval The state of 1 or 0 - */ -__STATIC_INLINE uint32_t md_cmp_get_rult(CMP_TypeDef *cmp) -{ - return (uint32_t)(READ_REG(cmp->RULT)); -} - -/** - * @brief Return Comparator 1 output result - * @param cmp CMP Instance - * @retval The state of 1 or 0 - */ -__STATIC_INLINE uint32_t md_cmp_get_rult_cmpo1(CMP_TypeDef *cmp) -{ - return (uint32_t)(READ_BIT(cmp->RULT, CMP_RULT_CMPO1_MSK)); -} -/** - * @brief Return Comparator 2 output result - * @param cmp CMP Instance - * @retval The state of 1 or 0 - */ -__STATIC_INLINE uint32_t md_cmp_get_rult_cmpo2(CMP_TypeDef *cmp) -{ - return (uint32_t)(READ_BIT(cmp->RULT, CMP_RULT_CMPO2_MSK)); -} - - -/** - * @} MD_CMP_PC_RULT - */ - - -/** - * @} MD_CMP_Public_Macros - */ - -/* Public functions -----------------------------------------------------------*/ - -/** - * @} CMP - */ - -#endif - - -/** - * @} Micro_Driver - */ - -#endif - -#ifdef __cplusplus -} -#endif - - -/******************* (C) COPYRIGHT Eastsoft Microelectronics *****END OF FILE****/ diff --git a/bsp/essemi/es32f0271/libraries/ES32F027x_MD_StdPeriph_Driver/Include/md_crc.h b/bsp/essemi/es32f0271/libraries/ES32F027x_MD_StdPeriph_Driver/Include/md_crc.h deleted file mode 100644 index f1b65692e7..0000000000 --- a/bsp/essemi/es32f0271/libraries/ES32F027x_MD_StdPeriph_Driver/Include/md_crc.h +++ /dev/null @@ -1,519 +0,0 @@ -/** - ****************************************************************************** - * @file md_crc.h - * @brief M601 CRC Head File. - * - * @version V0.01 - * @date 28/11/2018 - * @author Eastsoft AE Team - * @note - * detailed description - * - * Copyright (C) 2018 Shanghai Eastsoft Microelectronics Co., Ltd. ALL rights reserved. - ******************************************************************************* - */ - -/* Define to prevent recursive inclusion -------------------------------------*/ -#ifndef __MD_CRC_H__ -#define __MD_CRC_H__ - -#ifdef __cplusplus -extern "C" { -#endif - -/* Includes -------------------------------------------------------------------*/ -#include "es32f0271.h" - -/** @addtogroup Micro_Driver - * @{ - */ - -#if defined (CRC) - -/** @defgroup CRC CRC - * @brief CRC module driver - * @{ - */ - -/* Private Types --------------------------------------------------------------*/ -/* Private Variables ----------------------------------------------------------*/ -/* Private Macros -------------------------------------------------------------*/ -/* Public Types ---------------------------------------------------------------*/ -/** @defgroup MD_CRC_INIT CRC public init structure - * @brief - * @{ - */ -typedef struct -{ - uint32_t xorout; - uint32_t refout; - uint32_t refin; - uint32_t byte; - uint32_t mode; - uint32_t req; - uint32_t ds; - uint32_t rst; -} md_crc_init_typedef; -/** - * @} MD_CRC_INIT - */ - -/* Public Constants -----------------------------------------------------------*/ -/** @defgroup MD_CRC_Public_Constants CRC Public Constants - * @brief - * @{ - */ - -/** @defgroup MD_CRC_CON_registers CRC Control Registers - * @brief - * @{ - */ -#define MD_CRC_CON_DMA_ON 1 /*!< This allow user to enable DMA function. */ -#define MD_CRC_CON_DMA_OFF 0 /*!< This allow user to disable DMA function. */ -#define MD_CRC_CON_MSB_ON 1 /*!< User can set this bit to change the 'byte' order of input data. */ -#define MD_CRC_CON_MSB_OFF 1 /*!< User can set this bit to change the 'byte' order of input data. */ -#define MD_CRC_CON_REOUT 0 /*!< This allow user to reverse the order of CRC output data. */ -#define MD_CRC_CON_REOUT_REV 1 /*!< This allow user to reverse the order of CRC output data. */ -#define MD_CRC_CON_REIN 0 /*!< This allow user to reverse the order of CRC input data. */ -#define MD_CRC_CON_REIN_REV 1 /*!< This allow user to reverse the order of CRC input data. */ -#define MD_CRC_CON_SIZE_POLY32 0 /*!< This allow user to select polynomial size. */ -#define MD_CRC_CON_SIZE_POLY16 1 /*!< This allow user to select polynomial size. */ -#define MD_CRC_CON_SIZE_POLY8 2 /*!< This allow user to select polynomial size. */ -#define MD_CRC_CON_MODE_COMP_DISABLE 0 /*!< This allow user to check CRC result. */ -#define MD_CRC_CON_MODE_COMP_ZERO 1 /*!< This allow user to check CRC result. */ -#define MD_CRC_CON_MODE_COMP_ENABLE 2 /*!< This allow user to check CRC result. */ -#define MD_CRC_CON_RESET 1 /*!< User can set this bit to reset CRC function. */ -/** - * @} MD_CRC_CON_registers - */ - -/** @defgroup MD_CRC_STAT_registers CRC Status Registers - * @brief - * @{ - */ -#define MD_CRC_STAT_FAIL 1 /*!< This bit is set when CRC result is not correct. */ -#define MD_CRC_STAT_EMPTY 1 /*!< This bit is cleaned after an CRC calculation. */ -#define MD_CRC_STAT_BUSY 1 /*!< This bit is set when CRC module is calculating result. */ -#define MD_CRC_STAT_DONE 1 /*!< This bit is set when CRC calculation is finish. */ -/** - * @} MD_CRC_STAT_registers - */ - -/** - * @} MD_CRC_Public_Constants - */ - -/* Public Macros --------------------------------------------------------------*/ -/** @defgroup MD_CRC_Public_Macros CRC Public Macros - * @brief - * @{ - */ - -/** - * @brief This register is used to write the CRC initial data. - * @param CRC Instance - * @param value This parameter can be one of the following values: - * @arg Minimum 0x00000000 - * @arg Maximum 0xFFFFFFFF - * @retval None. - */ -__STATIC_INLINE void md_crc_set_init(CRC_TypeDef *crc, uint32_t value) -{ - WRITE_REG(crc->INIT, value); -} - -/** - * @brief This register is used to read the CRC initial data. - * @param CRC Instance - * @retval value 0x00000000 ~ 0xffffffff. - */ -__STATIC_INLINE uint32_t md_crc_get_init(CRC_TypeDef *crc) -{ - return (READ_REG(crc->INIT)); -} - -/** - * @brief This register is used to write the coefficient of the CRC polynomial. Default coefficient is for CRC32. - * @param CRC Instance - * @param value This parameter can be one of the following values: - * @arg Minimum 0x00000000 - * @arg Maximum 0xFFFFFFFF - * @retval None. - */ -__STATIC_INLINE void md_crc_set_poly(CRC_TypeDef *crc, uint32_t value) -{ - WRITE_REG(crc->POLY, value); -} - -/** - * @brief This register is used to read the coefficient of the CRC polynomial. Default coefficient is for CRC32. - * @param CRC Instance - * @retval value 0x00000000 ~ 0xffffffff. - */ -__STATIC_INLINE uint32_t md_crc_get_poly(CRC_TypeDef *crc) -{ - return (READ_REG(crc->POLY)); -} - -/** - * @brief This register is used to write the CRC input data. CRC will start to calculate result after this register is written. - * @param CRC Instance - * @param value This parameter can be one of the following values: - * @arg Minimum 0x00000000 - * @arg Maximum 0xFFFFFFFF - * @retval None. - */ -__STATIC_INLINE void md_crc_set_data(CRC_TypeDef *crc, uint32_t value) -{ - WRITE_REG(crc->DATA, value); -} - -/** - * @brief This register is used to read the CRC input data. CRC will start to calculate result after this register is written. - * @param CRC Instance - * @retval value 0x00000000 ~ 0xffffffff. - */ -__STATIC_INLINE uint32_t md_crc_get_data(CRC_TypeDef *crc) -{ - return (READ_REG(crc->DATA)); -} - -/** - * @brief This register is used to compare with the CRC output data. - * @param CRC Instance - * @param value This parameter can be one of the following values: - * @arg Minimum 0x00000000 - * @arg Maximum 0xFFFFFFFF - * @retval None. - */ -__STATIC_INLINE void md_crc_set_comp(CRC_TypeDef *crc, uint32_t value) -{ - WRITE_REG(crc->COMP, value); -} - -/** - * @brief This register is used to compare with the CRC output data. - * @param CRC Instance - * @retval value 0x00000000 ~ 0xffffffff. - */ -__STATIC_INLINE uint32_t md_crc_get_comp(CRC_TypeDef *crc) -{ - return (READ_REG(crc->COMP)); -} - -/** - * @brief This register is used to set a parameter to do exclusive OR with CRC output data. - * @param CRC Instance - * @param value This parameter can be one of the following values: - * @arg Minimum 0x00000000 - * @arg Maximum 0xFFFFFFFF - * @retval None. - */ -__STATIC_INLINE void md_crc_set_rema(CRC_TypeDef *crc, uint32_t value) -{ - WRITE_REG(crc->REMA, value); -} - -/** - * @brief This register is used to set a parameter to do exclusive OR with CRC output data. - * @param CRC Instance - * @retval value 0x00000000 ~ 0xffffffff. - */ -__STATIC_INLINE uint32_t md_crc_get_rema(CRC_TypeDef *crc) -{ - return (READ_REG(crc->REMA)); -} - -/** - * @brief This register is used to set a parameter. - * @param CRC Instance - * @param value This parameter can be one of the following values: - * @arg @ref MD_CRC_CON_DMA_ON 1 - * @arg @ref MD_CRC_CON_DMA_OFF 0 - * @arg @ref MD_CRC_CON_MSB_ON 1 - * @arg @ref MD_CRC_CON_MSB_OFF 0 - * @arg @ref MD_CRC_CON_REOUT 0 - * @arg @ref MD_CRC_CON_REOUT_REV 1 - * @arg @ref MD_CRC_CON_REIN 0 - * @arg @ref MD_CRC_CON_REIN_REV 1 - * @arg @ref MD_CRC_CON_SIZE_POLY32 0 - * @arg @ref MD_CRC_CON_SIZE_POLY16 1 - * @arg @ref MD_CRC_CON_SIZE_POLY8 2 - * @arg @ref MD_CRC_CON_MODE_COMP_DISABLE 0 - * @arg @ref MD_CRC_CON_MODE_COMP_ZERO 1 - * @arg @ref MD_CRC_CON_MODE_COMP_ENABLE 2 - * @arg @ref MD_CRC_CON_RESET 1 - * @retval None. - */ -__STATIC_INLINE void md_crc_set_con(CRC_TypeDef *crc, uint32_t value) -{ - WRITE_REG(crc->CON, value); -} - -/** - * @brief This register is used to get a parameter. - * @param CRC Instance - * @retval value 0x00000000 ~ 0xffffffff. - */ -__STATIC_INLINE uint32_t md_crc_get_con(CRC_TypeDef *crc) -{ - return (READ_REG(crc->CON)); -} - -/** - * @brief This function allow user to enable DMA function. - * @param CRC Instance - * @param value This parameter can be one of the following values: - * @arg @ref MD_CRC_CON_DMA_ON 1 - * @arg @ref MD_CRC_CON_DMA_OFF 0 - * @retval None. - */ -__STATIC_INLINE void md_crc_set_con_dma(CRC_TypeDef *crc, uint32_t value) -{ - MODIFY_REG(crc->CON, CRC_CON_DMA_MSK, value << CRC_CON_DMA_POS); -} - -/** - * @brief This function allow user to enable DMA function. - * @param CRC Instance - * @retval value 0: disable, 1: enable. - */ -__STATIC_INLINE uint32_t md_crc_get_con_dma(CRC_TypeDef *crc) -{ - return ((READ_BIT(crc->CON, CRC_CON_DMA_MSK) >> CRC_CON_DMA_POS) & 0x1); -} - -/** - * @brief User can set this bit to change the 'byte' order of input data. - * @param CRC Instance - * @param value This parameter can be one of the following values: - * @arg @ref MD_CRC_CON_MSB_ON 1 - * @arg @ref MD_CRC_CON_MSB_OFF 0 - * @retval None. - */ -__STATIC_INLINE void md_crc_set_con_msb(CRC_TypeDef *crc, uint32_t value) -{ - MODIFY_REG(crc->CON, CRC_CON_MSB_MSK, value << CRC_CON_MSB_POS); -} - -/** - * @brief User can set this bit to change the 'byte' order of input data. - * @param CRC Instance - * @retval value 0: disable, 1: enable. - */ -__STATIC_INLINE uint32_t md_crc_get_con_msb(CRC_TypeDef *crc) -{ - return ((READ_BIT(crc->CON, CRC_CON_MSB_MSK) >> CRC_CON_MSB_POS) & 0x1); -} - -/** - * @brief This function allow user to reverse the order of CRC output data. - * @param CRC Instance - * @param value This parameter can be one of the following values: - * @arg @reg MD_CRC_CON_REOUT 0 - * @arg @reg MD_CRC_CON_REOUT_REV 1 - * @retval None. - */ -__STATIC_INLINE void md_crc_set_con_reout(CRC_TypeDef *crc, uint32_t value) -{ - MODIFY_REG(crc->CON, CRC_CON_REOUT_MSK, value << CRC_CON_REOUT_POS); -} - -/** - * @brief This function allow user to reverse the order of CRC output data. - * @param CRC Instance - * @retval value 0: Disable reverse operation, 1: Reverse output data. - */ -__STATIC_INLINE uint32_t md_crc_get_con_reout(CRC_TypeDef *crc) -{ - return ((READ_BIT(crc->CON, CRC_CON_REOUT_MSK) >> CRC_CON_REOUT_POS) & 0x1); -} - -/** - * @brief This function allow user to reverse the order of CRC input data. - * @param CRC Instance - * @param value This parameter can be one of the following values: - * @arg @reg MD_CRC_CON_REIN 0 - * @arg @reg MD_CRC_CON_REIN_REV 1 - * @retval None. - */ -__STATIC_INLINE void md_crc_set_con_rein(CRC_TypeDef *crc, uint32_t value) -{ - MODIFY_REG(crc->CON, CRC_CON_REIN_MSK, value << CRC_CON_REIN_POS); -} - -/** - * @brief User can set this bit to change the 'byte' order of input data. - * @param CRC Instance - * @retval value 0: Disable reverse operation, 1: Bit reversal done by byte. - */ -__STATIC_INLINE uint32_t md_crc_get_con_rein(CRC_TypeDef *crc) -{ - return ((READ_BIT(crc->CON, CRC_CON_REIN_MSK) >> CRC_CON_REIN_POS) & 0x1); -} - -/** - * @brief User can set this bit to change the 'byte' order of input data. - * @param CRC Instance - * @param value This parameter can be one of the following values: - * @arg @ref MD_CRC_CON_SIZE_POLY32 0 - * @arg @ref MD_CRC_CON_SIZE_POLY16 1 - * @arg @ref MD_CRC_CON_SIZE_POLY8 2 - * @retval None. - */ -__STATIC_INLINE void md_crc_set_con_size(CRC_TypeDef *crc, uint32_t value) -{ - MODIFY_REG(crc->CON, CRC_CON_SIZE_MSK, value << CRC_CON_SIZE_POSS); -} - -/** - * @brief User can set this bit to change the 'byte' order of input data. - * @param CRC Instance - * @retval value 00: 32 bit polynomial, 01: 16 bit polynomial, 10: 8 bit polynomial. - */ -__STATIC_INLINE uint32_t md_crc_get_con_size(CRC_TypeDef *crc) -{ - return ((READ_BIT(crc->CON, CRC_CON_SIZE_MSK) >> CRC_CON_SIZE_POSS) & 0x3); -} - -/** - * @brief This function allow user to check CRC result. If CRC result is not correct, the status “FAIL” in CRC_STA will be set to 1. - * @param CRC Instance - * @param value This parameter can be one of the following values: - * @arg @ref MD_CRC_CON_MODE_COMP_DISABLE 0 - * @arg @ref MD_CRC_CON_MODE_COMP_ZERO 1 - * @arg @ref MD_CRC_CON_MODE_COMP_ENABLE 2 - * @retval None. - */ -__STATIC_INLINE void md_crc_set_con_mode(CRC_TypeDef *crc, uint32_t value) -{ - MODIFY_REG(crc->CON, CRC_CON_MODE_MSK, value << CRC_CON_MODE_POSS); -} - -/** - * @brief This function allow user to check CRC result. If CRC result is not correct, the status “FAIL” in CRC_STA will be set to 1. - * @param CRC Instance - * @retval value 00: Disable compare function, 01: Compare CRC result with 32’h0000_0000, 10: Compare CRC result with CRC_COMP. - */ -__STATIC_INLINE uint32_t md_crc_get_con_mode(CRC_TypeDef *crc) -{ - return ((READ_BIT(crc->CON, CRC_CON_MODE_MSK) >> CRC_CON_MODE_POSS) & 0x3); -} - -/** - * @brief User can set this bit to reset CRC function. This bit will be cleared by itself. - * @param CRC Instance - * @param value This parameter can be one of the following values: - * @arg @ref MD_CRC_CON_RESET 1 - * @retval None. - */ -__STATIC_INLINE void md_crc_set_con_reset(CRC_TypeDef *crc, uint32_t value) -{ - MODIFY_REG(crc->CON, CRC_CON_RESET_MSK, value << CRC_CON_RESET_POS); -} - -/** - * @brief User can set this bit to reset CRC function. This bit will be cleared by itself. - * @param CRC Instance - * @retval value 0. - */ -__STATIC_INLINE uint32_t md_crc_get_con_reset(CRC_TypeDef *crc) -{ - return ((READ_BIT(crc->CON, CRC_CON_RESET_MSK) >> CRC_CON_RESET_POS) & 0x1); -} - -/** - * @brief This register is used to show the CRC calculation result. - * @param CRC Instance - * @retval value: 0x00000000 ~ 0xffffffff. - */ -__STATIC_INLINE uint32_t md_crc_get_dout(CRC_TypeDef *crc) -{ - return (READ_REG(crc->DOUT)); -} - -/** - * @brief This register is used to show the CRC calculation exculsive OR result. - * @param CRC Instance - * @retval value: 0x00000000 ~ 0xffffffff. - */ -__STATIC_INLINE uint32_t md_crc_get_dout_xor(CRC_TypeDef *crc) -{ - return (READ_REG(crc->DOUT_XOR)); -} - -/** - * @brief This register is used to show the CRC calculation exculsive OR result. - * @param CRC Instance - * @retval value: 0x00000000 ~ 0xffffffff. - */ -__STATIC_INLINE uint32_t md_crc_get_stat(CRC_TypeDef *crc) -{ - return (READ_REG(crc->STAT)); -} - -/** - * @brief This bit is set when CRC result is not correct. - * @param CRC Instance - * @retval value: 1 = FAIL, 0 = PASS. - @arg @ref MD_CRC_STAT_FAIL 1 - */ -__STATIC_INLINE uint32_t md_crc_get_stat_fail(CRC_TypeDef *crc) -{ - return ((READ_BIT(crc->STAT, CRC_STAT_FAIL_MSK) >> CRC_STAT_FAIL_POS) & 0x1); -} - -/** - * @brief This bit is cleaned after an CRC calculation. - * @param CRC Instance - * @retval value: 1 = FAIL, 0 = PASS. - @arg @ref MD_CRC_STAT_EMPTY 1 - */ -__STATIC_INLINE uint32_t md_crc_get_stat_empty(CRC_TypeDef *crc) -{ - return ((READ_BIT(crc->STAT, CRC_STAT_EMPTY_MSK) >> CRC_STAT_EMPTY_POS) & 0x1); -} - -/** - * @brief This bit is set when CRC module is calculating result. - * @param CRC Instance - * @retval value: 1 = FAIL, 0 = PASS. - @arg @ref MD_CRC_STAT_BUSY 1 - */ -__STATIC_INLINE uint32_t md_crc_get_stat_busy(CRC_TypeDef *crc) -{ - return ((READ_BIT(crc->STAT, CRC_STAT_BUSY_MSK) >> CRC_STAT_BUSY_POS) & 0x1); -} - -/** - * @brief This bit is set when CRC module is calculating result. - * @param CRC Instance - * @retval value: 1 = FAIL, 0 = PASS. - @arg @ref MD_CRC_STAT_DONE 1 - */ -__STATIC_INLINE uint32_t md_crc_get_stat_done(CRC_TypeDef *crc) -{ - return (READ_BIT(crc->STAT, CRC_STAT_DONE_MSK) >> CRC_STAT_DONE_POS); -} - -/** - * @} MD_CRC_Public_Macros - */ - -/** - * @} CRC - */ - -#endif - -/** - * @} Micro_Driver - */ - -#ifdef __cplusplus -} -#endif - -#endif - -/******************* (C) COPYRIGHT Eastsoft Microelectronics *****END OF FILE****/ diff --git a/bsp/essemi/es32f0271/libraries/ES32F027x_MD_StdPeriph_Driver/Include/md_dac.h b/bsp/essemi/es32f0271/libraries/ES32F027x_MD_StdPeriph_Driver/Include/md_dac.h deleted file mode 100644 index 199fc195b1..0000000000 --- a/bsp/essemi/es32f0271/libraries/ES32F027x_MD_StdPeriph_Driver/Include/md_dac.h +++ /dev/null @@ -1,290 +0,0 @@ -/** - ****************************************************************************** - * @file md_ADC.h - * @brief ES32F0271 DAC Header File. - * - * @version V1.00.01 - * @date 01/14/2019 - * @author Eastsoft AE Team - * @note - * - * Copyright (C) 2018 Shanghai Eastsoft Microelectronics Co., Ltd. ALL rights reserved. - * - ******************************************************************************* - */ - -/* Define to prevent recursive inclusion -------------------------------------*/ -#ifndef __MD_DAC_H__ -#define __MD_DAC_H__ - -#ifdef __cplusplus -extern "C" { -#endif - -/* Includes -------------------------------------------------------------------*/ -#include "es32f0271.h" -#include "reg_dac.h" - -/** @addtogroup Micro_Driver - * @{ - */ - -#if defined DAC - -/** @defgroup DAC DAC - * @brief DAC micro driver - * @{ - */ - -/* Private types --------------------------------------------------------------*/ -/* Private variables ----------------------------------------------------------*/ -/* Private constants ----------------------------------------------------------*/ -/* Private macros -------------------------------------------------------------*/ -/* Public types ---------------------------------------------------------------*/ -/* Public constants -----------------------------------------------------------*/ -/* Public functions -----------------------------------------------------------*/ - -/** @defgroup MD_DAC_Public_Constants DAC Public Constants - * @{ - */ - -/** @defgroup MD_DAC_CON DAC_CON Register - * @{ - */ - -#define MD_ADC_CON_TSEL_SW (0x00000000U<CON, DAC_CON_INVREN_MSK); -} - -/** - * @brief DAC INVREN Disable. - * @param None - * @retval None - */ -__STATIC_INLINE void md_dac_disable_con_invren(DAC_TypeDef *DACx) -{ - CLEAR_BIT(DACx->CON, DAC_CON_INVREN_MSK); -} - -/** - * @brief Check if DAC INVREN is enabled. - * @param None - * @retval State of bit (1 or 0). - */ -__STATIC_INLINE uint32_t md_dac_is_enabled_con_invren(DAC_TypeDef *DACx) -{ - return (READ_BIT(DACx->CON, DAC_CON_INVREN_MSK) == (DAC_CON_INVREN_MSK)); -} - -/** - * @brief TRIGGER enable. - * @param DACx DAC Instance - * @retval None - */ -__STATIC_INLINE void md_dac_enable_con_trien(DAC_TypeDef *DACx) -{ - SET_BIT(DACx->CON, DAC_CON_TRIEN_MSK); -} - -/** - * @brief TRIGGER Disable. - * @param DACx DAC Instance - * @retval None - */ -__STATIC_INLINE void md_dac_disable_en_trien(DAC_TypeDef *DACx) -{ - CLEAR_BIT(DACx->CON, DAC_CON_TRIEN_MSK); -} - -/** - * @brief Check if DAC TRIGGER is enabled. - * @param DACx DAC Instance - * @retval State of bit (1 or 0). - */ -__STATIC_INLINE uint32_t md_dac_is_enabled_con_trien(DAC_TypeDef *DACx) -{ - return (READ_BIT(DACx->EN, DAC_CON_TRIEN_MSK) == (DAC_CON_TRIEN_MSK)); -} - -/** - * @brief Set DACx DIV register. - * @note This bits can only be written none zero value. - * @param DACx DAC Instance. - * @param DIV value. - * @retval None - */ -__STATIC_INLINE void md_dac_set_div(DAC_TypeDef *DACx, uint32_t div) -{ - WRITE_REG(DACx->DIV, div); -} - -/** - * @brief Set DACx DAC_CON WAVE value. - * @param DACx DAC Instance. - * @param WAVE value. - * @retval None - */ -__STATIC_INLINE void md_dac_set_con_wave(DAC_TypeDef *DACx, uint32_t wave) -{ - MODIFY_REG(DACx->CON, DAC_CON_MAMP_MSK, wave<CON, DAC_CON_MAMP_MSK, mamp<CON, DAC_CON_T_SEL_MSK, tsel<TRIG, DAC_TRIG_S_TRIG_MSK); -} - -/** - * @brief Check if Transmit FIFO full. - * @note This bit is set and cleared by hardware when the TX FIFO is no - * longer full. - * @param DACx DAC Instance - * @retval State of bit (1 or 0). - */ -__STATIC_INLINE uint32_t md_dac_is_active_flag_stat_txfull(DAC_TypeDef *DACx) -{ - return (READ_BIT(DACx->STAT, DAC_STAT_TX_FULL_MSK) == (DAC_STAT_TX_FULL_MSK)); -} - -/** - * @brief Check if Transmit DAC is busy. - * @param DACx DAC Instance - * @retval State of bit (1 or 0). - */ -__STATIC_INLINE uint32_t md_dac_is_active_flag_stat_busy(DAC_TypeDef *DACx) -{ - return (READ_BIT(DACx->STAT, DAC_STAT_BUSY_MSK) == (DAC_STAT_BUSY_MSK)); -} - -/** - * @brief DAC enable. - * @param DACx DAC Instance - * @retval None - */ -__STATIC_INLINE void md_dac_enable_en_dacen(DAC_TypeDef *DACx) -{ - SET_BIT(DACx->EN, DAC_EN_DAC_EN_MSK); -} - -/** - * @brief DAC Disable. - * @param DACx DAC Instance - * @retval None - */ -__STATIC_INLINE void md_dac_disable_en_dacen(DAC_TypeDef *DACx) -{ - CLEAR_BIT(DACx->EN, DAC_EN_DAC_EN_MSK); -} - -/** - * @brief Set DACx data register. - * @param DACx DAC Instance. - * @param Tx data value. - * @retval None - */ -__STATIC_INLINE void md_dac_set_txdata(DAC_TypeDef *DACx, uint32_t data) -{ - WRITE_REG(DACx->DATA, data); -} - -#endif - -/** - * @} MD_GPIO_Public_Macros - */ - -/** @} ADC - */ - -/** - * @} Micro_Driver - */ - - -#ifdef __cplusplus -} -#endif - -#endif - -/******************* (C) COPYRIGHT Eastsoft Microelectronics *****END OF FILE****/ diff --git a/bsp/essemi/es32f0271/libraries/ES32F027x_MD_StdPeriph_Driver/Include/md_dma.h b/bsp/essemi/es32f0271/libraries/ES32F027x_MD_StdPeriph_Driver/Include/md_dma.h deleted file mode 100644 index 521ce1e61e..0000000000 --- a/bsp/essemi/es32f0271/libraries/ES32F027x_MD_StdPeriph_Driver/Include/md_dma.h +++ /dev/null @@ -1,5561 +0,0 @@ -/** - ****************************************************************************** - * @file md_DMA.h - * @brief ES32F0271 DMA HEAD File. - * - * @version V1.00.02 - * @date 30/11/2018 - * @author Eastsoft AE Team - * @note - * detailed description - * - * Copyright (C) 2018 Shanghai Eastsoft Microelectronics Co., Ltd. ALL rights reserved. - ******************************************************************************* - */ - -/* Define to prevent recursive inclusion -------------------------------------*/ -#ifndef __MD_DMA_H__ -#define __MD_DMA_H__ - -#ifdef __cplusplus -extern "C" { -#endif - -/* Includes -------------------------------------------------------------------*/ -#include "es32f0271.h" -#include "reg_dma.h" - -/** @addtogroup Micro_Driver - * @{ - */ - -#if defined (DMA1) - -/** @defgroup DMA DMA - * @brief DMA micro driver - * @{ - */ - -/* Private types --------------------------------------------------------------*/ -/* Private variables ----------------------------------------------------------*/ -/* Private constants ----------------------------------------------------------*/ -/* Private macros -------------------------------------------------------------*/ - -/* Public types ---------------------------------------------------------------*/ -/** @defgroup MD_DMA_PT_INIT DMA Public Init structures - * @{ - */ - -/** - * @brief MD DMA Init Structure definition - */ - - -/** - * @} MD_DMA_PT_INIT - */ - -/* Public constants -----------------------------------------------------------*/ -/** @defgroup MD_DMA_Public_Constants DMA Public Constants - * @{ - */ - -/** @defgroup MD_DMA_DINCOS Destination Increment Offset Size - * @{ - */ -#define MD_DMA_DINCOS_LINKED_DWSEL (0x00000000UL) /** @brief The offset size for the peripheral address calculation is - linked to the DWSEL */ -#define MD_DMA_DINCOS_FIXED_TO_4 (0X00000001UL) /** @brief The offset size for the peripheral address calculation is - fixed to 4 (32-bit alignment). */ -/** - * @} MD_DMA_DINCOS - */ - -/** @defgroup MD_DMA_DBUSEL Destination Transfer Burst Selection - * @{ - */ -#define MD_DMA_DBUSEL_SINGLE (0x00000000U) -#define MD_DMA_DBUSEL_WRAP4 (0x00000002U) -#define MD_DMA_DBUSEL_INCR4 (0x00000003U) -#define MD_DMA_DBUSEL_WRAP8 (0x00000004U) -#define MD_DMA_DBUSEL_INCR8 (0x00000005U) -#define MD_DMA_DBUSEL_WRAP16 (0x00000006U) -#define MD_DMA_DBUSEL_INCR16 (0x00000007U) -/** - * @} MD_DMA_DBUSEL - */ - -/** @defgroup MD_DMA_DDWSEL Destination Transfer Data Width Selection. - * @{ - */ -#define MD_DMA_DDWSEL_ONE_BYTE (0x00000000UL) /** @brief One byte (8-bit) is transferred for every DMA operation. */ -#define MD_DMA_DDWSEL_ONE_HALF_WORD (0x00000001UL) /** @brief One half-word (16-bit) is transferred for every DMA operation. */ -#define MD_DMA_DDWSEL_ONE_WORD (0x00000002UL) /** @brief One word (32-bit) is transferred for every DMA operation. */ -/** - * @} MD_DMA_DDWSEL - */ - -/** @defgroup MD_DMA_SINCOS Source Increment Offset Size - * @{ - */ -#define MD_DMA_SINCOS_LINKED_SWSEL (0x00000000UL) /** @brief The offset size for the peripheral address calculation is - linked to the SWSEL */ -#define MD_DMA_SINCOS_FIXED_TO_4 (0X00000001UL) /** @brief The offset size for the peripheral address calculation is - fixed to 4 (32-bit alignment). */ -/** - * @} MD_DMA_SINCOS - */ - -/** @defgroup MD_DMA_SBUSEL Source Transfer Burst Selection. - * @{ - */ -#define MD_DMA_SBUSEL_SINGLE (0x00000000U) -#define MD_DMA_SBUSEL_WRAP4 (0x00000002U) -#define MD_DMA_SBUSEL_INCR4 (0x00000003U) -#define MD_DMA_SBUSEL_WRAP8 (0x00000004U) -#define MD_DMA_SBUSEL_INCR8 (0x00000005U) -#define MD_DMA_SBUSEL_WRAP16 (0x00000006U) -#define MD_DMA_SBUSEL_INCR16 (0x00000007U) -/** - * @} MD_DMA_SBUSEL - */ - -/** @defgroup MD_DMA_SDWSEL Source Transfer Data Width Selection. - * @{ - */ -#define MD_DMA_SDWSEL_ONE_BYTE (0x00000000UL) /** @brief One byte (8-bit) is transferred for every DMA operation. */ -#define MD_DMA_SDWSEL_ONE_HALF_WORD (0x00000001UL) /** @brief One half-word (16-bit) is transferred for every DMA operation. */ -#define MD_DMA_SDWSEL_ONE_WORD (0x00000002UL) /** @brief One word (32-bit) is transferred for every DMA operation. */ -/** - * @} MD_DMA_SDWSEL - */ - -/** @defgroup MD_DMA_CHPRI DMA Channel Priority. - * @{ - */ -#define MD_DMA_CHPRI_LV0 (0x00000000U) -#define MD_DMA_CHPRI_LV1 (0x00000001U) -#define MD_DMA_CHPRI_LV2 (0x00000002U) -#define MD_DMA_CHPRI_LV3 (0x00000003U) -#define MD_DMA_CHPRI_LV4 (0x00000004U) -#define MD_DMA_CHPRI_LV5 (0x00000005U) -/** - * @} MD_DMA_CHPRI - */ - -/** @defgroup MD_DMA_MODESEL DMA Mode Select. - * @{ - */ -#define MD_DMA_MODESEL_MEM_TO_MEM (0x0000000UL) /** @brief Memory to Memory mode (Memory-to-Memory). */ -#define MD_DMA_MODESEL_PER_TO_MEM (0x0000001UL) /** @brief Peripheral to Memory mode (Peripheral-to-Memory). */ -#define MD_DMA_MODESEL_MEM_TO_PER (0x0000002UL) /** @brief Memory to Peripheral mode (Memory-to-Peripheral). */ -/** - * @} MD_DMA_MODESEL - */ - -/** @defgroup MD_DMA_PFCTRL Peripheral flow controller - * @{ - */ -#define MD_DMA_PFCTRL_DMA_CTRL (0x0000000UL) /** @brief The DMA is the flow controller */ -#define MD_DMA_PFCTRL_PER_CTRL (0x0000001UL) /** @brief The peripheral is the flow controller */ -/** - * @} MD_DMA_PFCTRL - */ - -/** @defgroup MD_DMA_PHSS Peripheral Handshake Software Select - * @{ - */ -#define MD_DMA_PHSS_UART1_TX (0x0000000UL) -#define MD_DMA_PHSS_UART2_TX (0x0000001UL) -#define MD_DMA_PHSS_UART3_TX (0x0000002UL) -#define MD_DMA_PHSS_SUART1_TX (0x0000003UL) -#define MD_DMA_PHSS_SUART2_TX (0x0000004UL) -#define MD_DMA_PHSS_SPI1_TX (0x0000005UL) -#define MD_DMA_PHSS_SPI2_TX (0x0000006UL) -#define MD_DMA_PHSS_I2C1_TX (0x0000007UL) -#define MD_DMA_PHSS_I2C2_TX (0x0000008UL) -#define MD_DMA_PHSS_AES_IN (0x0000009UL) -#define MD_DMA_PHSS_DAC (0x000000AUL) -#define MD_DMA_PHSS_CRC (0x000000BUL) -#define MD_DMA_PHSS_UART1_RX (0x000000FUL) -#define MD_DMA_PHSS_UART2_RX (0x0000010UL) -#define MD_DMA_PHSS_UART3_RX (0x0000011UL) -#define MD_DMA_PHSS_SUART1_RX (0x0000012UL) -#define MD_DMA_PHSS_SUART2_RX (0x0000013UL) -#define MD_DMA_PHSS_SPI1_RTX (0x0000014UL) -#define MD_DMA_PHSS_SPI2_RX (0x0000015UL) -#define MD_DMA_PHSS_I2C1_RX (0x0000016UL) -#define MD_DMA_PHSS_I2C2_RX (0x0000017UL) -#define MD_DMA_PHSS_AES_OUT (0x0000018UL) -#define MD_DMA_PHSS_ADCSS0 (0x0000019UL) -#define MD_DMA_PHSS_ADCSS1 (0x000001AUL) -#define MD_DMA_PHSS_ADCSS2 (0x000001BUL) -#define MD_DMA_PHSS_ADCSS3 (0x000001CUL) -#define MD_DMA_PHSS_BS16T1_UP (0x0000020UL) -#define MD_DMA_PHSS_AD16C4T1_CH1 (0x0000021UL) -#define MD_DMA_PHSS_AD16C4T1_CH2 (0x0000022UL) -#define MD_DMA_PHSS_AD16C4T1_CH3 (0x0000023UL) -#define MD_DMA_PHSS_AD16C4T1_CH4 (0x0000024UL) -#define MD_DMA_PHSS_AD16C4T1_UP (0x0000025UL) -#define MD_DMA_PHSS_AD16C4T1_TRIG (0x0000026UL) -#define MD_DMA_PHSS_AD16C4T1_COM (0x0000027UL) -#define MD_DMA_PHSS_GP32C4T1_CH1 (0x0000028UL) -#define MD_DMA_PHSS_GP32C4T1_CH2 (0x0000029UL) -#define MD_DMA_PHSS_GP32C4T1_CH3 (0x000002AUL) -#define MD_DMA_PHSS_GP32C4T1_CH4 (0x000002BUL) -#define MD_DMA_PHSS_GP32C4T1_UP (0x000002CUL) -#define MD_DMA_PHSS_GP32C4T1_TRIG (0x000002DUL) -#define MD_DMA_PHSS_GP16C4T1_CH1 (0x000002EUL) -#define MD_DMA_PHSS_GP16C4T1_CH2 (0x000002FUL) -#define MD_DMA_PHSS_GP16C4T1_CH3 (0x0000030UL) -#define MD_DMA_PHSS_GP16C4T1_CH4 (0x0000031UL) -#define MD_DMA_PHSS_GP16C4T1_UP (0x0000032UL) -#define MD_DMA_PHSS_GP16C4T1_TRIG (0x0000033UL) -#define MD_DMA_PHSS_GP16C4T2_CH1 (0x0000034UL) -#define MD_DMA_PHSS_GP16C4T2_CH2 (0x0000035UL) -#define MD_DMA_PHSS_GP16C4T2_CH3 (0x0000036UL) -#define MD_DMA_PHSS_GP16C4T2_CH4 (0x0000037UL) -#define MD_DMA_PHSS_GP16C4T2_UP (0x0000038UL) -#define MD_DMA_PHSS_GP16C4T2_TRIG (0x0000039UL) -#define MD_DMA_PHSS_GP16C4T3_CH1 (0x000003AUL) -#define MD_DMA_PHSS_GP16C4T3_CH2 (0x000003BUL) -#define MD_DMA_PHSS_GP16C4T3_CH3 (0x000003CUL) -#define MD_DMA_PHSS_GP16C4T3_CH4 (0x000003DUL) -#define MD_DMA_PHSS_GP16C4T3_UP (0x000003EUL) -#define MD_DMA_PHSS_GP16C4T3_TRIG (0x000003FUL) -#define MD_DMA_PHSS_GP16C2T1_CH1 (0x0000040UL) -#define MD_DMA_PHSS_GP16C2T1_CH2 (0x0000041UL) -#define MD_DMA_PHSS_GP16C2T1_UP (0x0000042UL) -#define MD_DMA_PHSS_GP16C2T1_TRIG (0x0000043UL) -#define MD_DMA_PHSS_GP16C2T1_COM (0x0000044UL) -#define MD_DMA_PHSS_GP16C2T2_CH1 (0x0000046UL) -#define MD_DMA_PHSS_GP16C2T2_CH2 (0x0000047UL) -#define MD_DMA_PHSS_GP16C2T2_UP (0x0000048UL) -#define MD_DMA_PHSS_GP16C2T2_TRIG (0x0000049UL) -#define MD_DMA_PHSS_GP16C2T2_COM (0x000004AUL) -#define MD_DMA_PHSS_GP16C2T3_CH1 (0x000004CUL) -#define MD_DMA_PHSS_GP16C2T3_CH2 (0x000004DUL) -#define MD_DMA_PHSS_GP16C2T3_UP (0x000004EUL) -#define MD_DMA_PHSS_GP16C2T3_TRIG (0x000004FUL) -#define MD_DMA_PHSS_GP16C2T3_COM (0x0000050UL) -#define MD_DMA_PHSS_GP16C2T4_CH1 (0x0000052UL) -#define MD_DMA_PHSS_GP16C2T4_CH2 (0x0000053UL) -#define MD_DMA_PHSS_GP16C2T4_UP (0x0000054UL) -#define MD_DMA_PHSS_GP16C2T4_TRIG (0x0000055UL) -#define MD_DMA_PHSS_GP16C2T4_COM (0x0000056UL) -/** - * @} MD_DMA_PHSS - */ - -/** - * @} MD_DMA_Public_Constants - */ - -/* Public macro ---------------------------------------------------------------*/ -/** @defgroup MD_DMA_Public_Macros DMA Public Macros - * @{ - */ - -/** - * @brief DMA Channel 5 TABORT Interrupt Enable bit. - * @param dma DMA Instance - * @retval None - */ -__STATIC_INLINE void md_dma_enable_ier_ch5tabie(DMA_TypeDef *dma) -{ - SET_BIT(dma->IER, DMA_IER_CH5TABIE_MSK); -} -/** - * @brief DMA Channel 5 Block Transmit Done Interrupt Enable bit. - * @param dma DMA Instance - * @retval None - */ -__STATIC_INLINE void md_dma_enable_ier_ch5btdie(DMA_TypeDef *dma) -{ - SET_BIT(dma->IER, DMA_IER_CH5BTDIE_MSK); -} -/** - * @brief DMA Channel 4 TABORT Interrupt Enable bit. - * @param dma DMA Instance - * @retval None - */ -__STATIC_INLINE void md_dma_enable_ier_ch4tabie(DMA_TypeDef *dma) -{ - SET_BIT(dma->IER, DMA_IER_CH4TABIE_MSK); -} -/** - * @brief DMA Channel 4 Block Transmit Done Interrupt Enable bit. - * @param dma DMA Instance - * @retval None - */ -__STATIC_INLINE void md_dma_enable_ier_ch4btdie(DMA_TypeDef *dma) -{ - SET_BIT(dma->IER, DMA_IER_CH4BTDIE_MSK); -} -/** - * @brief DMA Channel 3 TABORT Interrupt Enable bit. - * @param dma DMA Instance - * @retval None - */ -__STATIC_INLINE void md_dma_enable_ier_ch3tabie(DMA_TypeDef *dma) -{ - SET_BIT(dma->IER, DMA_IER_CH3TABIE_MSK); -} -/** - * @brief DMA Channel 3 Block Transmit Done Interrupt Enable bit. - * @param dma DMA Instance - * @retval None - */ -__STATIC_INLINE void md_dma_enable_ier_ch3btdie(DMA_TypeDef *dma) -{ - SET_BIT(dma->IER, DMA_IER_CH3BTDIE_MSK); -} -/** - * @brief DMA Channel 2 TABORT Interrupt Enable bit. - * @param dma DMA Instance - * @retval None - */ -__STATIC_INLINE void md_dma_enable_ier_ch2tabie(DMA_TypeDef *dma) -{ - SET_BIT(dma->IER, DMA_IER_CH2TABIE_MSK); -} -/** - * @brief DMA Channel 2 Block Transmit Done Interrupt Enable bit. - * @param dma DMA Instance - * @retval None - */ -__STATIC_INLINE void md_dma_enable_ier_ch2btdie(DMA_TypeDef *dma) -{ - SET_BIT(dma->IER, DMA_IER_CH2BTDIE_MSK); -} -/** - * @brief DMA Channel 1 TABORT Interrupt Enable bit. - * @param dma DMA Instance - * @retval None - */ -__STATIC_INLINE void md_dma_enable_ier_ch1tabie(DMA_TypeDef *dma) -{ - SET_BIT(dma->IER, DMA_IER_CH1TABIE_MSK); -} -/** - * @brief DMA Channel 1 Block Transmit Done Interrupt Enable bit. - * @param dma DMA Instance - * @retval None - */ -__STATIC_INLINE void md_dma_enable_ier_ch1btdie(DMA_TypeDef *dma) -{ - SET_BIT(dma->IER, DMA_IER_CH1BTDIE_MSK); -} -/** - * @brief DMA Channel 0 TABORT Interrupt Enable bit. - * @param dma DMA Instance - * @retval None - */ -__STATIC_INLINE void md_dma_enable_ier_ch0tabie(DMA_TypeDef *dma) -{ - SET_BIT(dma->IER, DMA_IER_CH0TABIE_MSK); -} -/** - * @brief DMA Channel 0 Block Transmit Done Interrupt Enable bit. - * @param dma DMA Instance - * @retval None - */ -__STATIC_INLINE void md_dma_enable_ier_ch0btdie(DMA_TypeDef *dma) -{ - SET_BIT(dma->IER, DMA_IER_CH0BTDIE_MSK); -} - -/** @defgroup MD_DMA_IER_CH5TABIE CH5TABIE - * @brief Set DMA Channel 5 TABORT Interrupt Enable bit for md_dma_set_ier() function used - * @param ch5tabie This parameter can be one of the following values: - * @arg @ref DISABLE - * @arg @ref ENABLE - * @{ - */ -#define md_dma_set_ier_ch5tabie_fun(ch5tabie) (ch5tabie<IER, (ch5tabie|ch5btdie|ch4tabie|ch4btdie|ch3tabie|ch3btdie|ch2tabie|ch2btdie|ch1tabie|ch1btdie|ch0tabie|ch0btdie)); -} - -/** - * @brief DMA Channel 5 TABORT Interrupt Disable bit. - * @param dma DMA Instance - * @retval None - */ -__STATIC_INLINE void md_dma_enable_idr_ch5tabid(DMA_TypeDef *dma) -{ - SET_BIT(dma->IDR, DMA_IDR_CH5TABID_MSK); -} -/** - * @brief DMA Channel 5 Block Transmit Done Interrupt Disable bit. - * @param dma DMA Instance - * @retval None - */ -__STATIC_INLINE void md_dma_enable_idr_ch5btdid(DMA_TypeDef *dma) -{ - SET_BIT(dma->IDR, DMA_IDR_CH5BTDID_MSK); -} -/** - * @brief DMA Channel 4 TABORT Interrupt Disable bit. - * @param dma DMA Instance - * @retval None - */ -__STATIC_INLINE void md_dma_enable_idr_ch4tabid(DMA_TypeDef *dma) -{ - SET_BIT(dma->IDR, DMA_IDR_CH4TABID_MSK); -} -/** - * @brief DMA Channel 4 Block Transmit Done Interrupt Disable bit. - * @param dma DMA Instance - * @retval None - */ -__STATIC_INLINE void md_dma_enable_idr_ch4btdid(DMA_TypeDef *dma) -{ - SET_BIT(dma->IDR, DMA_IDR_CH4BTDID_MSK); -} -/** - * @brief DMA Channel 3 TABORT Interrupt Disable bit. - * @param dma DMA Instance - * @retval None - */ -__STATIC_INLINE void md_dma_enable_idr_ch3tabid(DMA_TypeDef *dma) -{ - SET_BIT(dma->IDR, DMA_IDR_CH3TABID_MSK); -} -/** - * @brief DMA Channel 3 Block Transmit Done Interrupt Disable bit. - * @param dma DMA Instance - * @retval None - */ -__STATIC_INLINE void md_dma_enable_idr_ch3btdid(DMA_TypeDef *dma) -{ - SET_BIT(dma->IDR, DMA_IDR_CH3BTDID_MSK); -} -/** - * @brief DMA Channel 2 TABORT Interrupt Disable bit. - * @param dma DMA Instance - * @retval None - */ -__STATIC_INLINE void md_dma_enable_idr_ch2tabid(DMA_TypeDef *dma) -{ - SET_BIT(dma->IDR, DMA_IDR_CH2TABID_MSK); -} -/** - * @brief DMA Channel 2 Block Transmit Done Interrupt Disable bit. - * @param dma DMA Instance - * @retval None - */ -__STATIC_INLINE void md_dma_enable_idr_ch2btdid(DMA_TypeDef *dma) -{ - SET_BIT(dma->IDR, DMA_IDR_CH2BTDID_MSK); -} -/** - * @brief DMA Channel 1 TABORT Interrupt Disable bit. - * @param dma DMA Instance - * @retval None - */ -__STATIC_INLINE void md_dma_enable_idr_ch1tabid(DMA_TypeDef *dma) -{ - SET_BIT(dma->IDR, DMA_IDR_CH1TABID_MSK); -} -/** - * @brief DMA Channel 1 Block Transmit Done Interrupt Disable bit. - * @param dma DMA Instance - * @retval None - */ -__STATIC_INLINE void md_dma_enable_idr_ch1btdid(DMA_TypeDef *dma) -{ - SET_BIT(dma->IDR, DMA_IDR_CH1BTDID_MSK); -} -/** - * @brief DMA Channel 0 TABORT Interrupt Disable bit. - * @param dma DMA Instance - * @retval None - */ -__STATIC_INLINE void md_dma_enable_idr_ch0tabid(DMA_TypeDef *dma) -{ - SET_BIT(dma->IDR, DMA_IDR_CH0TABID_MSK); -} -/** - * @brief DMA Channel 0 Block Transmit Done Interrupt Disable bit. - * @param dma DMA Instance - * @retval None - */ -__STATIC_INLINE void md_dma_enable_idr_ch0btdid(DMA_TypeDef *dma) -{ - SET_BIT(dma->IDR, DMA_IDR_CH0BTDID_MSK); -} - - -/** - * @brief DMA Channel 5 TABORT Interrupt Valid Status bit - * @param dma DMA Instance - * @retval State of bit (1 or 0). - */ -__STATIC_INLINE uint32_t md_dma_get_ivs_ch5tabivs(DMA_TypeDef *dma) -{ - return (READ_BIT(dma->IVS, DMA_IVS_CH5TABIVS_MSK)>>DMA_IVS_CH5TABIVS_POS); -} -/** - * @brief DMA Channel 5 Block Transmit Done Interrupt Valid Status bit. - * @param dma DMA Instance - * @retval State of bit (1 or 0). - */ -__STATIC_INLINE uint32_t md_dma_get_ivs_ch5btdivs(DMA_TypeDef *dma) -{ - return (READ_BIT(dma->IVS, DMA_IVS_CH5BTDIVS_MSK)>>DMA_IVS_CH5BTDIVS_POS); -} -/** - * @brief DMA Channel 4 TABORT Interrupt Valid Status bit - * @param dma DMA Instance - * @retval State of bit (1 or 0). - */ -__STATIC_INLINE uint32_t md_dma_get_ivs_ch4tabivs(DMA_TypeDef *dma) -{ - return (READ_BIT(dma->IVS, DMA_IVS_CH4TABIVS_MSK)>>DMA_IVS_CH4TABIVS_POS); -} -/** - * @brief DMA Channel 4 Block Transmit Done Interrupt Valid Status bit. - * @param dma DMA Instance - * @retval State of bit (1 or 0). - */ -__STATIC_INLINE uint32_t md_dma_get_ivs_ch4btdivs(DMA_TypeDef *dma) -{ - return (READ_BIT(dma->IVS, DMA_IVS_CH4BTDIVS_MSK)>>DMA_IVS_CH4BTDIVS_POS); -} -/** - * @brief DMA Channel 3 TABORT Interrupt Valid Status bit - * @param dma DMA Instance - * @retval State of bit (1 or 0). - */ -__STATIC_INLINE uint32_t md_dma_get_ivs_ch3tabivs(DMA_TypeDef *dma) -{ - return (READ_BIT(dma->IVS, DMA_IVS_CH3TABIVS_MSK)>>DMA_IVS_CH3TABIVS_POS); -} -/** - * @brief DMA Channel 3 Block Transmit Done Interrupt Valid Status bit. - * @param dma DMA Instance - * @retval State of bit (1 or 0). - */ -__STATIC_INLINE uint32_t md_dma_get_ivs_ch3btdivs(DMA_TypeDef *dma) -{ - return (READ_BIT(dma->IVS, DMA_IVS_CH3BTDIVS_MSK)>>DMA_IVS_CH3BTDIVS_POS); -} -/** - * @brief DMA Channel 2 TABORT Interrupt Valid Status bit - * @param dma DMA Instance - * @retval State of bit (1 or 0). - */ -__STATIC_INLINE uint32_t md_dma_get_ivs_ch2tabivs(DMA_TypeDef *dma) -{ - return (READ_BIT(dma->IVS, DMA_IVS_CH2TABIVS_MSK)>>DMA_IVS_CH2TABIVS_POS); -} -/** - * @brief DMA Channel 2 Block Transmit Done Interrupt Valid Status bit. - * @param dma DMA Instance - * @retval State of bit (1 or 0). - */ -__STATIC_INLINE uint32_t md_dma_get_ivs_ch2btdivs(DMA_TypeDef *dma) -{ - return (READ_BIT(dma->IVS, DMA_IVS_CH2BTDIVS_MSK)>>DMA_IVS_CH2BTDIVS_POS); -} -/** - * @brief DMA Channel 1 TABORT Interrupt Valid Status bit - * @param dma DMA Instance - * @retval State of bit (1 or 0). - */ -__STATIC_INLINE uint32_t md_dma_get_ivs_ch1tabivs(DMA_TypeDef *dma) -{ - return (READ_BIT(dma->IVS, DMA_IVS_CH1TABIVS_MSK)>>DMA_IVS_CH1TABIVS_POS); -} -/** - * @brief DMA Channel 1 Block Transmit Done Interrupt Valid Status bit. - * @param dma DMA Instance - * @retval State of bit (1 or 0). - */ -__STATIC_INLINE uint32_t md_dma_get_ivs_ch1btdivs(DMA_TypeDef *dma) -{ - return (READ_BIT(dma->IVS, DMA_IVS_CH1BTDIVS_MSK)>>DMA_IVS_CH1BTDIVS_POS); -} -/** - * @brief DMA Channel 0 TABORT Interrupt Valid Status bit - * @param dma DMA Instance - * @retval State of bit (1 or 0). - */ -__STATIC_INLINE uint32_t md_dma_get_ivs_ch0tabivs(DMA_TypeDef *dma) -{ - return (READ_BIT(dma->IVS, DMA_IVS_CH0TABIVS_MSK)>>DMA_IVS_CH0TABIVS_POS); -} -/** - * @brief DMA Channel 0 Block Transmit Done Interrupt Valid Status bit. - * @param dma DMA Instance - * @retval State of bit (1 or 0). - */ -__STATIC_INLINE uint32_t md_dma_get_ivs_ch0btdivs(DMA_TypeDef *dma) -{ - return (READ_BIT(dma->IVS, DMA_IVS_CH0BTDIVS_MSK)>>DMA_IVS_CH0BTDIVS_POS); -} -/** - * @brief Get DMA interrupt valid status register - * @param dma DMA Instance - * @retval DMA channel interrupt valid status - */ -__STATIC_INLINE uint32_t md_dma_get_ivs(DMA_TypeDef *dma) -{ - return (READ_REG(dma->IVS)); -} - -/** - * @brief DMA Channel 5 TABORT Raw Interrupt Flag Status bit - * @param dma DMA Instance - * @retval State of bit (1 or 0). - */ -__STATIC_INLINE uint32_t md_dma_get_ivs_ch5tabrif(DMA_TypeDef *dma) -{ - return (READ_BIT(dma->RIF, DMA_RIF_CH5TABRIF_MSK)>>DMA_RIF_CH5TABRIF_POS); -} -/** - * @brief DMA Channel 5 Block Transmit Done Raw Interrupt Flag Status bit. - * @param dma DMA Instance - * @retval State of bit (1 or 0). - */ -__STATIC_INLINE uint32_t md_dma_get_ivs_ch5btdrif(DMA_TypeDef *dma) -{ - return (READ_BIT(dma->RIF, DMA_RIF_CH5BTDRIF_MSK)>>DMA_RIF_CH5BTDRIF_POS); -} -/** - * @brief DMA Channel 4 TABORT Raw Interrupt Flag Status bit - * @param dma DMA Instance - * @retval State of bit (1 or 0). - */ -__STATIC_INLINE uint32_t md_dma_get_ivs_ch4tabrif(DMA_TypeDef *dma) -{ - return (READ_BIT(dma->RIF, DMA_RIF_CH4TABRIF_MSK)>>DMA_RIF_CH4TABRIF_POS); -} -/** - * @brief DMA Channel 4 Block Transmit Done Raw Interrupt Flag Status bit. - * @param dma DMA Instance - * @retval State of bit (1 or 0). - */ -__STATIC_INLINE uint32_t md_dma_get_ivs_ch4btdrif(DMA_TypeDef *dma) -{ - return (READ_BIT(dma->RIF, DMA_RIF_CH4BTDRIF_MSK)>>DMA_RIF_CH4BTDRIF_POS); -} -/** - * @brief DMA Channel 3 TABORT Raw Interrupt Flag Status bit - * @param dma DMA Instance - * @retval State of bit (1 or 0). - */ -__STATIC_INLINE uint32_t md_dma_get_ivs_ch3tabrif(DMA_TypeDef *dma) -{ - return (READ_BIT(dma->RIF, DMA_RIF_CH3TABRIF_MSK)>>DMA_RIF_CH3TABRIF_POS); -} -/** - * @brief DMA Channel 3 Block Transmit Done Raw Interrupt Flag Status bit. - * @param dma DMA Instance - * @retval State of bit (1 or 0). - */ -__STATIC_INLINE uint32_t md_dma_get_ivs_ch3btdrif(DMA_TypeDef *dma) -{ - return (READ_BIT(dma->RIF, DMA_RIF_CH3BTDRIF_MSK)>>DMA_RIF_CH3BTDRIF_POS); -} -/** - * @brief DMA Channel 2 TABORT Raw Interrupt Flag Status bit - * @param dma DMA Instance - * @retval State of bit (1 or 0). - */ -__STATIC_INLINE uint32_t md_dma_get_ivs_ch2tabrif(DMA_TypeDef *dma) -{ - return (READ_BIT(dma->RIF, DMA_RIF_CH2TABRIF_MSK)>>DMA_RIF_CH2TABRIF_POS); -} -/** - * @brief DMA Channel 2 Block Transmit Done Raw Interrupt Flag Status bit. - * @param dma DMA Instance - * @retval State of bit (1 or 0). - */ -__STATIC_INLINE uint32_t md_dma_get_ivs_ch2btdrif(DMA_TypeDef *dma) -{ - return (READ_BIT(dma->RIF, DMA_RIF_CH2BTDRIF_MSK)>>DMA_RIF_CH2BTDRIF_POS); -} -/** - * @brief DMA Channel 1 TABORT Raw Interrupt Flag Status bit - * @param dma DMA Instance - * @retval State of bit (1 or 0). - */ -__STATIC_INLINE uint32_t md_dma_get_ivs_ch1tabrif(DMA_TypeDef *dma) -{ - return (READ_BIT(dma->RIF, DMA_RIF_CH1TABRIF_MSK)>>DMA_RIF_CH1TABRIF_POS); -} -/** - * @brief DMA Channel 1 Block Transmit Done Raw Interrupt Flag Status bit. - * @param dma DMA Instance - * @retval State of bit (1 or 0). - */ -__STATIC_INLINE uint32_t md_dma_get_ivs_ch1btdrif(DMA_TypeDef *dma) -{ - return (READ_BIT(dma->RIF, DMA_RIF_CH1BTDRIF_MSK)>>DMA_RIF_CH1BTDRIF_POS); -} -/** - * @brief DMA Channel 0 TABORT Raw Interrupt Flag Status bit - * @param dma DMA Instance - * @retval State of bit (1 or 0). - */ -__STATIC_INLINE uint32_t md_dma_get_ivs_ch0tabrif(DMA_TypeDef *dma) -{ - return (READ_BIT(dma->RIF, DMA_RIF_CH0TABRIF_MSK)>>DMA_RIF_CH0TABRIF_POS); -} -/** - * @brief DMA Channel 0 Block Transmit Done Raw Interrupt Flag Status bit. - * @param dma DMA Instance - * @retval State of bit (1 or 0). - */ -__STATIC_INLINE uint32_t md_dma_get_ivs_ch0btdrif(DMA_TypeDef *dma) -{ - return (READ_BIT(dma->RIF, DMA_RIF_CH0BTDRIF_MSK)>>DMA_RIF_CH0BTDRIF_POS); -} -/** - * @brief Get DMA raw interrupt flag status register - * @param dma DMA Instance - * @retval DMA channel raw interrupt flag status - */ -__STATIC_INLINE uint32_t md_dma_get_rif(DMA_TypeDef *dma) -{ - return (READ_REG(dma->RIF)); -} - -/** - * @brief DMA Channel 5 TABORT Interrupt Flag Masked Status bit - * @param dma DMA Instance - * @retval State of bit (1 or 0). - */ -__STATIC_INLINE uint32_t md_dma_get_ifm_ch5tabifm(DMA_TypeDef *dma) -{ - return (READ_BIT(dma->IFM, DMA_IFM_CH5TABIFM_MSK)>>DMA_IFM_CH5TABIFM_POS); -} -/** - * @brief DMA Channel 5 Block Transmit Done Interrupt Flag Masked Status bit. - * @param dma DMA Instance - * @retval State of bit (1 or 0). - */ -__STATIC_INLINE uint32_t md_dma_get_ifm_ch5btdifm(DMA_TypeDef *dma) -{ - return (READ_BIT(dma->IFM, DMA_IFM_CH5BTDIFM_MSK)>>DMA_IFM_CH5BTDIFM_POS); -} -/** - * @brief DMA Channel 4 TABORT Interrupt Flag Masked Status bit - * @param dma DMA Instance - * @retval State of bit (1 or 0). - */ -__STATIC_INLINE uint32_t md_dma_get_ifm_ch4tabifm(DMA_TypeDef *dma) -{ - return (READ_BIT(dma->IFM, DMA_IFM_CH4TABIFM_MSK)>>DMA_IFM_CH4TABIFM_POS); -} -/** - * @brief DMA Channel 4 Block Transmit Done Interrupt Flag Masked Status bit. - * @param dma DMA Instance - * @retval State of bit (1 or 0). - */ -__STATIC_INLINE uint32_t md_dma_get_ifm_ch4btdifm(DMA_TypeDef *dma) -{ - return (READ_BIT(dma->IFM, DMA_IFM_CH4BTDIFM_MSK)>>DMA_IFM_CH4BTDIFM_POS); -} -/** - * @brief DMA Channel 3 TABORT Interrupt Flag Masked Status bit - * @param dma DMA Instance - * @retval State of bit (1 or 0). - */ -__STATIC_INLINE uint32_t md_dma_get_ifm_ch3tabifm(DMA_TypeDef *dma) -{ - return (READ_BIT(dma->IFM, DMA_IFM_CH3TABIFM_MSK)>>DMA_IFM_CH3TABIFM_POS); -} -/** - * @brief DMA Channel 3 Block Transmit Done Interrupt Flag Masked Status bit. - * @param dma DMA Instance - * @retval State of bit (1 or 0). - */ -__STATIC_INLINE uint32_t md_dma_get_ifm_ch3btdifm(DMA_TypeDef *dma) -{ - return (READ_BIT(dma->IFM, DMA_IFM_CH3BTDIFM_MSK)>>DMA_IFM_CH3BTDIFM_POS); -} -/** - * @brief DMA Channel 2 TABORT Interrupt Flag Masked Status bit - * @param dma DMA Instance - * @retval State of bit (1 or 0). - */ -__STATIC_INLINE uint32_t md_dma_get_ifm_ch2tabifm(DMA_TypeDef *dma) -{ - return (READ_BIT(dma->IFM, DMA_IFM_CH2TABIFM_MSK)>>DMA_IFM_CH2TABIFM_POS); -} -/** - * @brief DMA Channel 2 Block Transmit Done Interrupt Flag Masked Status bit. - * @param dma DMA Instance - * @retval State of bit (1 or 0). - */ -__STATIC_INLINE uint32_t md_dma_get_ifm_ch2btdifm(DMA_TypeDef *dma) -{ - return (READ_BIT(dma->IFM, DMA_IFM_CH2BTDIFM_MSK)>>DMA_IFM_CH2BTDIFM_POS); -} -/** - * @brief DMA Channel 1 TABORT Interrupt Flag Masked Status bit - * @param dma DMA Instance - * @retval State of bit (1 or 0). - */ -__STATIC_INLINE uint32_t md_dma_get_ifm_ch1tabifm(DMA_TypeDef *dma) -{ - return (READ_BIT(dma->IFM, DMA_IFM_CH1TABIFM_MSK)>>DMA_IFM_CH1TABIFM_POS); -} -/** - * @brief DMA Channel 1 Block Transmit Done Interrupt Flag Masked Status bit. - * @param dma DMA Instance - * @retval State of bit (1 or 0). - */ -__STATIC_INLINE uint32_t md_dma_get_ifm_ch1btdifm(DMA_TypeDef *dma) -{ - return (READ_BIT(dma->IFM, DMA_IFM_CH1BTDIFM_MSK)>>DMA_IFM_CH1BTDIFM_POS); -} -/** - * @brief DMA Channel 0 TABORT Interrupt Flag Masked Status bit - * @param dma DMA Instance - * @retval State of bit (1 or 0). - */ -__STATIC_INLINE uint32_t md_dma_get_ifm_ch0tabifm(DMA_TypeDef *dma) -{ - return (READ_BIT(dma->IFM, DMA_IFM_CH0TABIFM_MSK)>>DMA_IFM_CH0TABIFM_POS); -} -/** - * @brief DMA Channel 0 Block Transmit Done Interrupt Flag Masked Status bit. - * @param dma DMA Instance - * @retval State of bit (1 or 0). - */ -__STATIC_INLINE uint32_t md_dma_get_ifm_ch0btdifm(DMA_TypeDef *dma) -{ - return (READ_BIT(dma->IFM, DMA_IFM_CH0BTDIFM_MSK)>>DMA_IFM_CH0BTDIFM_POS); -} -/** - * @brief Get DMA interrupt flag masked status register - * @param dma DMA Instance - * @retval DMA channel interrupt flag masked status - */ -__STATIC_INLINE uint32_t md_dma_get_ifm(DMA_TypeDef *dma) -{ - return (READ_REG(dma->IFM)); -} - - -/** - * @brief DMA Channel 5 TABORT Interrupt Clear bit - * @param dma DMA Instance - * @retval None - */ -__STATIC_INLINE void md_dma_clear_icr_ch5tabicr(DMA_TypeDef *dma) -{ - SET_BIT(dma->ICR, DMA_ICR_CH5TABICR_MSK); -} -/** - * @brief DMA Channel 5 Block Transmit Done Interrupt Clear bit. - * @param dma DMA Instance - * @retval None - */ -__STATIC_INLINE void md_dma_clear_icr_ch5btdicr(DMA_TypeDef *dma) -{ - SET_BIT(dma->ICR, DMA_ICR_CH5BTDICR_MSK); -} -/** - * @brief DMA Channel 4 TABORT Interrupt Clear bit - * @param dma DMA Instance - * @retval None - */ -__STATIC_INLINE void md_dma_clear_icr_ch4tabicr(DMA_TypeDef *dma) -{ - SET_BIT(dma->ICR, DMA_ICR_CH4TABICR_MSK); -} -/** - * @brief DMA Channel 4 Block Transmit Done Interrupt Clear bit. - * @param dma DMA Instance - * @retval None - */ -__STATIC_INLINE void md_dma_clear_icr_ch4btdicr(DMA_TypeDef *dma) -{ - SET_BIT(dma->ICR, DMA_ICR_CH4BTDICR_MSK); -} -/** - * @brief DMA Channel 3 TABORT Interrupt Clear bit - * @param dma DMA Instance - * @retval None - */ -__STATIC_INLINE void md_dma_clear_icr_ch3tabicr(DMA_TypeDef *dma) -{ - SET_BIT(dma->ICR, DMA_ICR_CH3TABICR_MSK); -} -/** - * @brief DMA Channel 3 Block Transmit Done Interrupt Clear bit. - * @param dma DMA Instance - * @retval None - */ -__STATIC_INLINE void md_dma_clear_icr_ch3btdicr(DMA_TypeDef *dma) -{ - SET_BIT(dma->ICR, DMA_ICR_CH3BTDICR_MSK); -} -/** - * @brief DMA Channel 2 TABORT Interrupt Clear bit - * @param dma DMA Instance - * @retval None - */ -__STATIC_INLINE void md_dma_clear_icr_ch2tabicr(DMA_TypeDef *dma) -{ - SET_BIT(dma->ICR, DMA_ICR_CH2TABICR_MSK); -} -/** - * @brief DMA Channel 2 Block Transmit Done Interrupt Clear bit. - * @param dma DMA Instance - * @retval None - */ -__STATIC_INLINE void md_dma_clear_icr_ch2btdicr(DMA_TypeDef *dma) -{ - SET_BIT(dma->ICR, DMA_ICR_CH2BTDICR_MSK); -} -/** - * @brief DMA Channel 1 TABORT Interrupt Clear bit - * @param dma DMA Instance - * @retval None - */ -__STATIC_INLINE void md_dma_clear_icr_ch1tabicr(DMA_TypeDef *dma) -{ - SET_BIT(dma->ICR, DMA_ICR_CH1TABICR_MSK); -} -/** - * @brief DMA Channel 1 Block Transmit Done Interrupt Clear bit. - * @param dma DMA Instance - * @retval None - */ -__STATIC_INLINE void md_dma_clear_icr_ch1btdicr(DMA_TypeDef *dma) -{ - SET_BIT(dma->ICR, DMA_ICR_CH1BTDICR_MSK); -} -/** - * @brief DMA Channel 0 TABORT Interrupt Clear bit - * @param dma DMA Instance - * @retval None - */ -__STATIC_INLINE void md_dma_clear_icr_ch0tabicr(DMA_TypeDef *dma) -{ - SET_BIT(dma->ICR, DMA_ICR_CH0TABICR_MSK); -} -/** - * @brief DMA Channel 0 Block Transmit Done Interrupt Clear bit. - * @param dma DMA Instance - * @retval None - */ -__STATIC_INLINE void md_dma_clear_icr_ch0btdicr(DMA_TypeDef *dma) -{ - SET_BIT(dma->ICR, DMA_ICR_CH0BTDICR_MSK); -} - -/** @defgroup MD_DMA_ICR_CH5TABICR CH5TABICR - * @brief Set DMA Channel 5 TABORT Interrupt Clear bit for md_dma_set_icr() function used - * @param ch5tabicr This parameter can be one of the following values: - * @arg @ref DISABLE - * @arg @ref ENABLE - * @{ - */ -#define md_dma_set_icr_ch5tabicr_fun(ch5tabicr) (ch5tabicr<ICR, ( ch5tabicr|ch5btdicr|ch4tabicr|ch4btdicr|ch3tabicr|ch3btdicr|ch2tabicr|ch2btdicr| - ch1tabicr|ch1btdicr|ch0tabicr|ch0btdicr)); -} -/** - * @brief Set DMA interrupt clear register(2) - * @param dma DMA Instance - * @param icr is interrupt clear register - * @retval None - */ -__STATIC_INLINE void md_dma_set_icr_icr(DMA_TypeDef *dma, uint32_t icr) -{ - WRITE_REG(dma->ICR, icr); -} - - -/** - * @brief DMA Channel 5 PFCTRL Size not match,last data have error Status bit. - * @param dma DMA Instance - * @retval State of bit (1 or 0). - */ -__STATIC_INLINE uint32_t md_dma_get_emsg_ch5pfser(DMA_TypeDef *dma) -{ - return (READ_BIT(dma->EMSG, DMA_EMSG_CH5PFSER_MSK)>>DMA_EMSG_CH5PFSER_POS); -} -/** - * @brief DMA Channel 5 PFCTRL Over run Status bit. - * @param dma DMA Instance - * @retval State of bit (1 or 0). - */ -__STATIC_INLINE uint32_t md_dma_get_emsg_ch5pfov(DMA_TypeDef *dma) -{ - return (READ_BIT(dma->EMSG, DMA_EMSG_CH5PFOV_MSK)>>DMA_EMSG_CH5PFOV_POS); -} -/** - * @brief DMA Channel 5 Setting Burst Error Status bit. - * @param dma DMA Instance - * @retval State of bit (1 or 0). - */ -__STATIC_INLINE uint32_t md_dma_get_emsg_ch5setbuer(DMA_TypeDef *dma) -{ - return (READ_BIT(dma->EMSG, DMA_EMSG_CH5SETBUER_MSK)>>DMA_EMSG_CH5SETBUER_POS); -} -/** - * @brief DMA Channel 5 Setting BCR Error Status bit. - * @param dma DMA Instance - * @retval State of bit (1 or 0). - */ -__STATIC_INLINE uint32_t md_dma_get_emsg_ch5setbcer(DMA_TypeDef *dma) -{ - return (READ_BIT(dma->EMSG, DMA_EMSG_CH5SETBCER_MSK)>>DMA_EMSG_CH5SETBCER_POS); -} -/** - * @brief DMA Channel 4 PFCTRL Size not match,last data have error Status bit. - * @param dma DMA Instance - * @retval State of bit (1 or 0). - */ -__STATIC_INLINE uint32_t md_dma_get_emsg_ch4pfser(DMA_TypeDef *dma) -{ - return (READ_BIT(dma->EMSG, DMA_EMSG_CH4PFSER_MSK)>>DMA_EMSG_CH4PFSER_POS); -} -/** - * @brief DMA Channel 4 PFCTRL Over run Status bit. - * @param dma DMA Instance - * @retval State of bit (1 or 0). - */ -__STATIC_INLINE uint32_t md_dma_get_emsg_ch4pfov(DMA_TypeDef *dma) -{ - return (READ_BIT(dma->EMSG, DMA_EMSG_CH4PFOV_MSK)>>DMA_EMSG_CH4PFOV_POS); -} -/** - * @brief DMA Channel 4 Setting Burst Error Status bit. - * @param dma DMA Instance - * @retval State of bit (1 or 0). - */ -__STATIC_INLINE uint32_t md_dma_get_emsg_ch4setbuer(DMA_TypeDef *dma) -{ - return (READ_BIT(dma->EMSG, DMA_EMSG_CH4SETBUER_MSK)>>DMA_EMSG_CH4SETBUER_POS); -} -/** - * @brief DMA Channel 4 Setting BCR Error Status bit. - * @param dma DMA Instance - * @retval State of bit (1 or 0). - */ -__STATIC_INLINE uint32_t md_dma_get_emsg_ch4setbcer(DMA_TypeDef *dma) -{ - return (READ_BIT(dma->EMSG, DMA_EMSG_CH4SETBCER_MSK)>>DMA_EMSG_CH4SETBCER_POS); -} -/** - * @brief DMA Channel 3 PFCTRL Size not match,last data have error Status bit. - * @param dma DMA Instance - * @retval State of bit (1 or 0). - */ -__STATIC_INLINE uint32_t md_dma_get_emsg_ch3pfser(DMA_TypeDef *dma) -{ - return (READ_BIT(dma->EMSG, DMA_EMSG_CH3PFSER_MSK)>>DMA_EMSG_CH3PFSER_POS); -} -/** - * @brief DMA Channel 3 PFCTRL Over run Status bit. - * @param dma DMA Instance - * @retval State of bit (1 or 0). - */ -__STATIC_INLINE uint32_t md_dma_get_emsg_ch3pfov(DMA_TypeDef *dma) -{ - return (READ_BIT(dma->EMSG, DMA_EMSG_CH3PFOV_MSK)>>DMA_EMSG_CH3PFOV_POS); -} -/** - * @brief DMA Channel 3 Setting Burst Error Status bit. - * @param dma DMA Instance - * @retval State of bit (1 or 0). - */ -__STATIC_INLINE uint32_t md_dma_get_emsg_ch3setbuer(DMA_TypeDef *dma) -{ - return (READ_BIT(dma->EMSG, DMA_EMSG_CH3SETBUER_MSK)>>DMA_EMSG_CH3SETBUER_POS); -} -/** - * @brief DMA Channel 3 Setting BCR Error Status bit. - * @param dma DMA Instance - * @retval State of bit (1 or 0). - */ -__STATIC_INLINE uint32_t md_dma_get_emsg_ch3setbcer(DMA_TypeDef *dma) -{ - return (READ_BIT(dma->EMSG, DMA_EMSG_CH3SETBCER_MSK)>>DMA_EMSG_CH3SETBCER_POS); -} -/** - * @brief DMA Channel 2 PFCTRL Size not match,last data have error Status bit. - * @param dma DMA Instance - * @retval State of bit (1 or 0). - */ -__STATIC_INLINE uint32_t md_dma_get_emsg_ch2pfser(DMA_TypeDef *dma) -{ - return (READ_BIT(dma->EMSG, DMA_EMSG_CH2PFSER_MSK)>>DMA_EMSG_CH2PFSER_POS); -} -/** - * @brief DMA Channel 2 PFCTRL Over run Status bit. - * @param dma DMA Instance - * @retval State of bit (1 or 0). - */ -__STATIC_INLINE uint32_t md_dma_get_emsg_ch2pfov(DMA_TypeDef *dma) -{ - return (READ_BIT(dma->EMSG, DMA_EMSG_CH2PFOV_MSK)>>DMA_EMSG_CH2PFOV_POS); -} -/** - * @brief DMA Channel 2 Setting Burst Error Status bit. - * @param dma DMA Instance - * @retval State of bit (1 or 0). - */ -__STATIC_INLINE uint32_t md_dma_get_emsg_ch2setbuer(DMA_TypeDef *dma) -{ - return (READ_BIT(dma->EMSG, DMA_EMSG_CH2SETBUER_MSK)>>DMA_EMSG_CH2SETBUER_POS); -} -/** - * @brief DMA Channel 2 Setting BCR Error Status bit. - * @param dma DMA Instance - * @retval State of bit (1 or 0). - */ -__STATIC_INLINE uint32_t md_dma_get_emsg_ch2setbcer(DMA_TypeDef *dma) -{ - return (READ_BIT(dma->EMSG, DMA_EMSG_CH2SETBCER_MSK)>>DMA_EMSG_CH2SETBCER_POS); -} -/** - * @brief DMA Channel 1 PFCTRL Size not match,last data have error Status bit. - * @param dma DMA Instance - * @retval State of bit (1 or 0). - */ -__STATIC_INLINE uint32_t md_dma_get_emsg_ch1pfser(DMA_TypeDef *dma) -{ - return (READ_BIT(dma->EMSG, DMA_EMSG_CH1PFSER_MSK)>>DMA_EMSG_CH1PFSER_POS); -} -/** - * @brief DMA Channel 1 PFCTRL Over run Status bit. - * @param dma DMA Instance - * @retval State of bit (1 or 0). - */ -__STATIC_INLINE uint32_t md_dma_get_emsg_ch1pfov(DMA_TypeDef *dma) -{ - return (READ_BIT(dma->EMSG, DMA_EMSG_CH1PFOV_MSK)>>DMA_EMSG_CH1PFOV_POS); -} -/** - * @brief DMA Channel 1 Setting Burst Error Status bit. - * @param dma DMA Instance - * @retval State of bit (1 or 0). - */ -__STATIC_INLINE uint32_t md_dma_get_emsg_ch1setbuer(DMA_TypeDef *dma) -{ - return (READ_BIT(dma->EMSG, DMA_EMSG_CH1SETBUER_MSK)>>DMA_EMSG_CH1SETBUER_POS); -} -/** - * @brief DMA Channel 1 Setting BCR Error Status bit. - * @param dma DMA Instance - * @retval State of bit (1 or 0). - */ -__STATIC_INLINE uint32_t md_dma_get_emsg_ch1setbcer(DMA_TypeDef *dma) -{ - return (READ_BIT(dma->EMSG, DMA_EMSG_CH1SETBCER_MSK)>>DMA_EMSG_CH1SETBCER_POS); -} -/** - * @brief DMA Channel 0 PFCTRL Size not match,last data have error Status bit. - * @param dma DMA Instance - * @retval State of bit (1 or 0). - */ -__STATIC_INLINE uint32_t md_dma_get_emsg_ch0pfser(DMA_TypeDef *dma) -{ - return (READ_BIT(dma->EMSG, DMA_EMSG_CH0PFSER_MSK)>>DMA_EMSG_CH0PFSER_POS); -} -/** - * @brief DMA Channel 0 PFCTRL Over run Status bit. - * @param dma DMA Instance - * @retval State of bit (1 or 0). - */ -__STATIC_INLINE uint32_t md_dma_get_emsg_ch0pfov(DMA_TypeDef *dma) -{ - return (READ_BIT(dma->EMSG, DMA_EMSG_CH0PFOV_MSK)>>DMA_EMSG_CH0PFOV_POS); -} -/** - * @brief DMA Channel 0 Setting Burst Error Status bit. - * @param dma DMA Instance - * @retval State of bit (1 or 0). - */ -__STATIC_INLINE uint32_t md_dma_get_emsg_ch0setbuer(DMA_TypeDef *dma) -{ - return (READ_BIT(dma->EMSG, DMA_EMSG_CH0SETBUER_MSK)>>DMA_EMSG_CH0SETBUER_POS); -} -/** - * @brief DMA Channel 0 Setting BCR Error Status bit. - * @param dma DMA Instance - * @retval State of bit (1 or 0). - */ -__STATIC_INLINE uint32_t md_dma_get_emsg_ch0setbcer(DMA_TypeDef *dma) -{ - return (READ_BIT(dma->EMSG, DMA_EMSG_CH0SETBCER_MSK)>>DMA_EMSG_CH0SETBCER_POS); -} -/** - * @brief Get DMA error message register - * @param dma DMA Instance - * @retval DMA channel error message status - */ -__STATIC_INLINE uint32_t md_dma_get_emsg(DMA_TypeDef *dma) -{ - return (READ_REG(dma->EMSG)); -} - -/** - * @brief Set Destination Increment Offset Size bit. - * @note This bit has no meaning if bit DINC = '0'. - * This bit is protected and can be written only if EN = '0'. - * This bit is forced low by hardware when the stream is enabled (bit EN = '1') if the direct mode is selected or - * if DBUSEL are different from 00. - * @param dma DMA Instance - * @param dincos can be one of the following values: - * @arg @ref MD_DMA_DINCOS_LINKED_DWSEL - * @arg @ref MD_DMA_DINCOS_FIXED_TO_4 - * @retval None - */ -__STATIC_INLINE void md_dma_set_csr0_dincos(DMA_TypeDef *dma, uint32_t dincos) -{ - MODIFY_REG(dma->CSR0, DMA_CSR0_DINCOS_MSK, (dincos<CSR0, DMA_CSR0_DINCOS_MSK)>>DMA_CSR0_DINCOS_POS); -} -/** - * @brief Set Destination Transfer Burst Selection. - * @param dma DMA Instance - * @param dbusel can be one of the following values: - * @arg @ref MD_DMA_DBUSEL_SINGLE - * @arg @ref MD_DMA_DBUSEL_WRAP4 - * @arg @ref MD_DMA_DBUSEL_INCR4 - * @arg @ref MD_DMA_DBUSEL_WRAP8 - * @arg @ref MD_DMA_DBUSEL_INCR8 - * @arg @ref MD_DMA_DBUSEL_WRAP16 - * @arg @ref MD_DMA_DBUSEL_INCR16 - * @retval None - */ -__STATIC_INLINE void md_dma_set_csr0_dbusel(DMA_TypeDef *dma, uint32_t dbusel) -{ - MODIFY_REG(dma->CSR0, DMA_CSR0_DBUSEL_MSK, (dbusel<CSR0, DMA_CSR0_DBUSEL_MSK)>>DMA_CSR0_DBUSEL_POSS); -} -/** - * @brief Set Destination Transfer Data Width Selection. - * @param dma DMA Instance - * @param ddwsel can be one of the following values: - * @arg @ref MD_DMA_DDWSEL_ONE_BYTE - * @arg @ref MD_DMA_DDWSEL_ONE_HALF_WORD - * @arg @ref MD_DMA_DDWSEL_ONE_WORD - * @retval None - */ -__STATIC_INLINE void md_dma_set_csr0_ddwsel(DMA_TypeDef *dma, uint32_t ddwsel) -{ - MODIFY_REG(dma->CSR0, DMA_CSR0_DDWSEL_MSK, (ddwsel<CSR0, DMA_CSR0_DDWSEL_MSK)>>DMA_CSR0_DDWSEL_POSS); -} -/** - * @brief Set Destination Transfer Increment Mode - * @param dma DMA Instance - * @param dinc can be one of the following values: - * @arg DISABLE - * @arg ENABLE - * @retval None - */ -__STATIC_INLINE void md_dma_set_csr0_dinc(DMA_TypeDef *dma, uint32_t dinc) -{ - MODIFY_REG(dma->CSR0, DMA_CSR0_DINC_MSK, (dinc<CSR0, DMA_CSR0_DINC_MSK)>>DMA_CSR0_DINC_POS); -} -/** - * @brief Set Source Increment Offset Size bit. - * @note This bit has no meaning if bit SINC = '0'. - * This bit is protected and can be written only if EN = '0'. - * This bit is forced low by hardware when the stream is enabled (bit EN = '1') if the direct mode is selected or - * if SBUSEL are different from 00. - * @param dma DMA Instance - * @param sincos can be one of the following values: - * @arg @ref MD_DMA_SINCOS_LINKED_SWSEL - * @arg @ref MD_DMA_SINCOS_FIXED_TO_4 - * @retval None - */ -__STATIC_INLINE void md_dma_set_csr0_sincos(DMA_TypeDef *dma, uint32_t sincos) -{ - MODIFY_REG(dma->CSR0, DMA_CSR0_SINCOS_MSK, (sincos<CSR0, DMA_CSR0_SINCOS_MSK)>>DMA_CSR0_SINCOS_POS); -} -/** - * @brief Set Source Transfer Burst Selection. - * @param dma DMA Instance - * @param sbusel can be one of the following values: - * @arg @ref MD_DMA_SBUSEL_SINGLE - * @arg @ref MD_DMA_SBUSEL_WRAP4 - * @arg @ref MD_DMA_SBUSEL_INCR4 - * @arg @ref MD_DMA_SBUSEL_WRAP8 - * @arg @ref MD_DMA_SBUSEL_INCR8 - * @arg @ref MD_DMA_SBUSEL_WRAP16 - * @arg @ref MD_DMA_SBUSEL_INCR16 - * @retval None - */ -__STATIC_INLINE void md_dma_set_csr0_sbusel(DMA_TypeDef *dma, uint32_t sbusel) -{ - MODIFY_REG(dma->CSR0, DMA_CSR0_SBUSEL_MSK, (sbusel<CSR0, DMA_CSR0_SBUSEL_MSK)>>DMA_CSR0_SBUSEL_POSS); -} -/** - * @brief Set Source Transfer Data Width Selection. - * @param dma DMA Instance - * @param sdwsel can be one of the following values: - * @arg @ref MD_DMA_SDWSEL_ONE_BYTE - * @arg @ref MD_DMA_SDWSEL_ONE_HALF_WORD - * @arg @ref MD_DMA_SDWSEL_ONE_WORD - * @retval None - */ -__STATIC_INLINE void md_dma_set_csr0_sdwsel(DMA_TypeDef *dma, uint32_t sdwsel) -{ - MODIFY_REG(dma->CSR0, DMA_CSR0_SDWSEL_MSK, (sdwsel<CSR0, DMA_CSR0_SDWSEL_MSK)>>DMA_CSR0_SDWSEL_POSS); -} -/** - * @brief Set Source Transfer Increment Mode - * @param dma DMA Instance - * @param sinc can be one of the following values: - * @arg DISABLE - * @arg ENABLE - * @retval None - */ -__STATIC_INLINE void md_dma_set_csr0_sinc(DMA_TypeDef *dma, uint32_t sinc) -{ - MODIFY_REG(dma->CSR0, DMA_CSR0_SINC_MSK, (sinc<CSR0, DMA_CSR0_SINC_MSK)>>DMA_CSR0_SINC_POS); -} -/** - * @brief Set Peripheral Handshake Software Select - * @param dma DMA Instance - * @param phss can be one of the following values: - * @arg @ref MD_DMA_PHSS_UART1_TX - * @arg @ref MD_DMA_PHSS_UART2_TX - * @arg @ref MD_DMA_PHSS_UART3_TX - * @arg @ref MD_DMA_PHSS_SUART1_TX - * @arg @ref MD_DMA_PHSS_SUART2_TX - * @arg @ref MD_DMA_PHSS_SPI1_TX - * @arg @ref MD_DMA_PHSS_SPI2_TX - * @arg @ref MD_DMA_PHSS_I2C1_TX - * @arg @ref MD_DMA_PHSS_I2C2_TX - * @arg @ref MD_DMA_PHSS_AES_IN - * @arg @ref MD_DMA_PHSS_DAC - * @arg @ref MD_DMA_PHSS_CRC - * @arg @ref MD_DMA_PHSS_UART1_RX - * @arg @ref MD_DMA_PHSS_UART2_RX - * @arg @ref MD_DMA_PHSS_UART3_RX - * @arg @ref MD_DMA_PHSS_SUART1_RX - * @arg @ref MD_DMA_PHSS_SUART2_RX - * @arg @ref MD_DMA_PHSS_SPI1_RTX - * @arg @ref MD_DMA_PHSS_SPI2_RX - * @arg @ref MD_DMA_PHSS_I2C1_RX - * @arg @ref MD_DMA_PHSS_I2C2_RX - * @arg @ref MD_DMA_PHSS_AES_OUT - * @arg @ref MD_DMA_PHSS_ADCSS0 - * @arg @ref MD_DMA_PHSS_ADCSS1 - * @arg @ref MD_DMA_PHSS_ADCSS2 - * @arg @ref MD_DMA_PHSS_ADCSS3 - * @arg @ref MD_DMA_PHSS_BS16T1_UP - * @arg @ref MD_DMA_PHSS_AD16C4T1_CH1 - * @arg @ref MD_DMA_PHSS_AD16C4T1_CH2 - * @arg @ref MD_DMA_PHSS_AD16C4T1_CH3 - * @arg @ref MD_DMA_PHSS_AD16C4T1_CH4 - * @arg @ref MD_DMA_PHSS_AD16C4T1_UP - * @arg @ref MD_DMA_PHSS_AD16C4T1_TRIG - * @arg @ref MD_DMA_PHSS_AD16C4T1_COM - * @arg @ref MD_DMA_PHSS_GP32C4T1_CH1 - * @arg @ref MD_DMA_PHSS_GP32C4T1_CH2 - * @arg @ref MD_DMA_PHSS_GP32C4T1_CH3 - * @arg @ref MD_DMA_PHSS_GP32C4T1_CH4 - * @arg @ref MD_DMA_PHSS_GP32C4T1_UP - * @arg @ref MD_DMA_PHSS_GP32C4T1_TRIG - * @arg @ref MD_DMA_PHSS_GP16C4T1_CH1 - * @arg @ref MD_DMA_PHSS_GP16C4T1_CH2 - * @arg @ref MD_DMA_PHSS_GP16C4T1_CH3 - * @arg @ref MD_DMA_PHSS_GP16C4T1_CH4 - * @arg @ref MD_DMA_PHSS_GP16C4T1_UP - * @arg @ref MD_DMA_PHSS_GP16C4T1_TRIG - * @arg @ref MD_DMA_PHSS_GP16C4T2_CH1 - * @arg @ref MD_DMA_PHSS_GP16C4T2_CH2 - * @arg @ref MD_DMA_PHSS_GP16C4T2_CH3 - * @arg @ref MD_DMA_PHSS_GP16C4T2_CH4 - * @arg @ref MD_DMA_PHSS_GP16C4T2_UP - * @arg @ref MD_DMA_PHSS_GP16C4T2_TRIG - * @arg @ref MD_DMA_PHSS_GP16C4T3_CH1 - * @arg @ref MD_DMA_PHSS_GP16C4T3_CH2 - * @arg @ref MD_DMA_PHSS_GP16C4T3_CH3 - * @arg @ref MD_DMA_PHSS_GP16C4T3_CH4 - * @arg @ref MD_DMA_PHSS_GP16C4T3_UP - * @arg @ref MD_DMA_PHSS_GP16C4T3_TRIG - * @arg @ref MD_DMA_PHSS_GP16C2T1_CH1 - * @arg @ref MD_DMA_PHSS_GP16C2T1_CH2 - * @arg @ref MD_DMA_PHSS_GP16C2T1_UP - * @arg @ref MD_DMA_PHSS_GP16C2T1_TRIG - * @arg @ref MD_DMA_PHSS_GP16C2T1_COM - * @arg @ref MD_DMA_PHSS_GP16C2T2_CH1 - * @arg @ref MD_DMA_PHSS_GP16C2T2_CH2 - * @arg @ref MD_DMA_PHSS_GP16C2T2_UP - * @arg @ref MD_DMA_PHSS_GP16C2T2_TRIG - * @arg @ref MD_DMA_PHSS_GP16C2T2_COM - * @arg @ref MD_DMA_PHSS_GP16C2T3_CH1 - * @arg @ref MD_DMA_PHSS_GP16C2T3_CH2 - * @arg @ref MD_DMA_PHSS_GP16C2T3_UP - * @arg @ref MD_DMA_PHSS_GP16C2T3_TRIG - * @arg @ref MD_DMA_PHSS_GP16C2T3_COM - * @arg @ref MD_DMA_PHSS_GP16C2T4_CH1 - * @arg @ref MD_DMA_PHSS_GP16C2T4_CH2 - * @arg @ref MD_DMA_PHSS_GP16C2T4_UP - * @arg @ref MD_DMA_PHSS_GP16C2T4_TRIG - * @arg @ref MD_DMA_PHSS_GP16C2T4_COM - * @retval None - */ -__STATIC_INLINE void md_dma_set_csr0_phss(DMA_TypeDef *dma, uint32_t phss) -{ - MODIFY_REG(dma->CSR0, DMA_CSR0_PHSS_MSK, (phss<CSR0, DMA_CSR0_PHSS_MSK)>>DMA_CSR0_PHSS_POSS); -} -/** - * @brief Set DMA Channel Priority. - * @param dma DMA Instance - * @param chpri can be one of the following values: - * @arg @ref MD_DMA_CHPRI_LV0 - * @arg @ref MD_DMA_CHPRI_LV1 - * @arg @ref MD_DMA_CHPRI_LV2 - * @arg @ref MD_DMA_CHPRI_LV3 - * @arg @ref MD_DMA_CHPRI_LV4 - * @arg @ref MD_DMA_CHPRI_LV5 - * @retval None - */ -__STATIC_INLINE void md_dma_set_csr0_chpri(DMA_TypeDef *dma, uint32_t chpri) -{ - MODIFY_REG(dma->CSR0, DMA_CSR0_CHPRI_MSK, (chpri<CSR0, DMA_CSR0_CHPRI_MSK)>>DMA_CSR0_CHPRI_POSS); -} -/** - * @brief Set DMA Mode Select. - * @param dma DMA Instance - * @param modesel can be one of the following values: - * @arg @ref MD_DMA_MODESEL_MEM_TO_MEM - * @arg @ref MD_DMA_MODESEL_PER_TO_MEM - * @arg @ref MD_DMA_MODESEL_MEM_TO_PER - * @retval None - */ -__STATIC_INLINE void md_dma_set_csr0_modesel(DMA_TypeDef *dma, uint32_t modesel) -{ - MODIFY_REG(dma->CSR0, DMA_CSR0_MODESEL_MSK, (modesel<CSR0, DMA_CSR0_MODESEL_MSK)>>DMA_CSR0_MODESEL_POSS); -} -/** - * @brief Set Direct Mode Enable. - * @param dma DMA Instance - * @param dirmden can be one of the following values: - * @arg Disable - * @arg Enable - * @retval None - */ -__STATIC_INLINE void md_dma_set_csr0_dirmden(DMA_TypeDef *dma, uint32_t dirmden) -{ - MODIFY_REG(dma->CSR0, DMA_CSR0_DIRMDEN_MSK, (dirmden<CSR0, DMA_CSR0_DIRMDEN_MSK)>>DMA_CSR0_DIRMDEN_POS); -} -/** - * @brief Set Peripheral flow controller - * @param dma DMA Instance - * @param pfctrl can be one of the following values: - * @arg @ref MD_DMA_PFCTRL_DMA_CTRL - * @arg @ref MD_DMA_PFCTRL_PER_CTRL - * @retval None - */ -__STATIC_INLINE void md_dma_set_csr0_pfctrl(DMA_TypeDef *dma, uint32_t pfctrl) -{ - MODIFY_REG(dma->CSR0, DMA_CSR0_PFCTRL_MSK, (pfctrl<CSR0, DMA_CSR0_PFCTRL_MSK)>>DMA_CSR0_PFCTRL_POS); -} -/** - * @brief Set Circular mode - * @param dma DMA Instance - * @param circ can be one of the following values: - * @arg Disable - * @arg Enable - * @retval None - */ -__STATIC_INLINE void md_dma_set_csr0_circ(DMA_TypeDef *dma, uint32_t circ) -{ - MODIFY_REG(dma->CSR0, DMA_CSR0_CIRC_MSK, (circ<CSR0, DMA_CSR0_CIRC_MSK)>>DMA_CSR0_CIRC_POS); -} -/** - * @brief Set DMA Channel Enable. - * @param dma DMA Instance - * @param chen can be one of the following values: - * @arg Disable - * @arg Enable - * @retval None - */ -__STATIC_INLINE void md_dma_set_csr0_chen(DMA_TypeDef *dma, uint32_t chen) -{ - MODIFY_REG(dma->CSR0, DMA_CSR0_CHEN_MSK, (chen<CSR0, DMA_CSR0_CHEN_MSK)>>DMA_CSR0_CHEN_POS); -} - -/** @defgroup MD_DMA_CSR0_DINCOS DINCOS - * @brief Set Destination Increment Offset Size bit for md_dma_set_cs0() function used - * @param dincos This parameter can be one of the following values: - * @arg @ref MD_DMA_DINCOS_LINKED_DWSEL - * @arg @ref MD_DMA_DINCOS_FIXED_TO_4 - * @{ - */ -#define md_dma_set_csr0_dincos_fun(dincos) (dincos<CSR0, (dincos|dbusel|ddwsel|dinc|sincos|sbusel|sdwsel|sinc| - phss|chpri|modesel|dirmden|pfctrl|circ|chen)); -} - - -/** - * @brief Set DMA Transfer Source Address Register - * @note These bits are write-protected and can be written only when bit EN = '0' - * @param dma DMA Instance - * @param sar This field indicates a 32-bit source address of DMA. - * @retval None - */ -__STATIC_INLINE void md_dma_set_sar0_sar(DMA_TypeDef *dma, uint32_t sar) -{ - MODIFY_REG(dma->SAR0, DMA_SAR0_SAR_MSK, (sar<SAR0, DMA_SAR0_SAR_MSK)>>DMA_SAR0_SAR_POSS); -} - -/** - * @brief Set DMA Transfer Destination Address Register - * @note These bits are write-protected and can be written only when bit EN = '0' - * @param dma DMA Instance - * @param dar This field indicates a 32-bit source address of DMA. - * @retval None - */ -__STATIC_INLINE void md_dma_set_dar0_dar(DMA_TypeDef *dma, uint32_t dar) -{ - MODIFY_REG(dma->DAR0, DMA_DAR0_DAR_MSK, (dar<DAR0, DMA_DAR0_DAR_MSK)>>DMA_DAR0_DAR_POSS); -} - -/** - * @brief Get DMA Current Transfer Byte Count - * @param dma DMA Instance - * @retval The retval can be one of the following values: - * @arg Max Value 65535 - * @arg Min Value 0 - */ -__STATIC_INLINE uint32_t md_dma_get_bcr0_cbcr(DMA_TypeDef *dma) -{ - return (READ_BIT(dma->BCR0, DMA_BCR0_CBCR_MSK)>>DMA_BCR0_CBCR_POSS); -} -/** - * @brief Set DMA Transfer Byte Count Register - * @note These bits are write-protected and can be written only when bit EN = '0' - * @param dma DMA Instance - * @param bcr This field indicates a 16-bit transfer byte count of DMA. - * @retval None - */ -__STATIC_INLINE void md_dma_set_bcr0_bcr(DMA_TypeDef *dma, uint32_t bcr) -{ - MODIFY_REG(dma->BCR0, DMA_BCR0_BCR_MSK, (bcr<BCR0, DMA_BCR0_BCR_MSK)>>DMA_BCR0_BCR_POSS); -} - -/** - * @brief Set Destination Increment Offset Size bit. - * @note This bit has no meaning if bit DINC = '0'. - * This bit is protected and can be written only if EN = '0'. - * This bit is forced low by hardware when the stream is enabled (bit EN = '1') if the direct mode is selected or - * if DBUSEL are different from 00. - * @param dma DMA Instance - * @param dincos can be one of the following values: - * @arg @ref MD_DMA_DINCOS_LINKED_DWSEL - * @arg @ref MD_DMA_DINCOS_FIXED_TO_4 - * @retval None - */ -__STATIC_INLINE void md_dma_set_csr1_dincos(DMA_TypeDef *dma, uint32_t dincos) -{ - MODIFY_REG(dma->CSR1, DMA_CSR1_DINCOS_MSK, (dincos<CSR1, DMA_CSR1_DINCOS_MSK)>>DMA_CSR1_DINCOS_POS); -} -/** - * @brief Set Destination Transfer Burst Selection. - * @param dma DMA Instance - * @param dbusel can be one of the following values: - * @arg @ref MD_DMA_DBUSEL_SINGLE - * @arg @ref MD_DMA_DBUSEL_WRAP4 - * @arg @ref MD_DMA_DBUSEL_INCR4 - * @arg @ref MD_DMA_DBUSEL_WRAP8 - * @arg @ref MD_DMA_DBUSEL_INCR8 - * @arg @ref MD_DMA_DBUSEL_WRAP16 - * @arg @ref MD_DMA_DBUSEL_INCR16 - * @retval None - */ -__STATIC_INLINE void md_dma_set_csr1_dbusel(DMA_TypeDef *dma, uint32_t dbusel) -{ - MODIFY_REG(dma->CSR1, DMA_CSR1_DBUSEL_MSK, (dbusel<CSR1, DMA_CSR1_DBUSEL_MSK)>>DMA_CSR1_DBUSEL_POSS); -} -/** - * @brief Set Destination Transfer Data Width Selection. - * @param dma DMA Instance - * @param ddwsel can be one of the following values: - * @arg @ref MD_DMA_DDWSEL_ONE_BYTE - * @arg @ref MD_DMA_DDWSEL_ONE_HALF_WORD - * @arg @ref MD_DMA_DDWSEL_ONE_WORD - * @retval None - */ -__STATIC_INLINE void md_dma_set_csr1_ddwsel(DMA_TypeDef *dma, uint32_t ddwsel) -{ - MODIFY_REG(dma->CSR1, DMA_CSR1_DDWSEL_MSK, (ddwsel<CSR1, DMA_CSR1_DDWSEL_MSK)>>DMA_CSR1_DDWSEL_POSS); -} -/** - * @brief Set Destination Transfer Increment Mode - * @param dma DMA Instance - * @param dinc can be one of the following values: - * @arg @ref DISABLE - * @arg @ref ENABLE - * @retval None - */ -__STATIC_INLINE void md_dma_set_csr1_dinc(DMA_TypeDef *dma, uint32_t dinc) -{ - MODIFY_REG(dma->CSR1, DMA_CSR1_DINC_MSK, (dinc<CSR1, DMA_CSR1_DINC_MSK)>>DMA_CSR1_DINC_POS); -} -/** - * @brief Set Source Increment Offset Size bit. - * @note This bit has no meaning if bit SINC = '0'. - * This bit is protected and can be written only if EN = '0'. - * This bit is forced low by hardware when the stream is enabled (bit EN = '1') if the direct mode is selected or - * if SBUSEL are different from 00. - * @param dma DMA Instance - * @param sincos can be one of the following values: - * @arg @ref MD_DMA_SINCOS_LINKED_SWSEL - * @arg @ref MD_DMA_SINCOS_FIXED_TO_4 - * @retval None - */ -__STATIC_INLINE void md_dma_set_csr1_sincos(DMA_TypeDef *dma, uint32_t sincos) -{ - MODIFY_REG(dma->CSR1, DMA_CSR1_SINCOS_MSK, (sincos<CSR1, DMA_CSR1_SINCOS_MSK)>>DMA_CSR1_SINCOS_POS); -} -/** - * @brief Set Source Transfer Burst Selection. - * @param dma DMA Instance - * @param sbusel can be one of the following values: - * @arg @ref MD_DMA_SBUSEL_SINGLE - * @arg @ref MD_DMA_SBUSEL_WRAP4 - * @arg @ref MD_DMA_SBUSEL_INCR4 - * @arg @ref MD_DMA_SBUSEL_WRAP8 - * @arg @ref MD_DMA_SBUSEL_INCR8 - * @arg @ref MD_DMA_SBUSEL_WRAP16 - * @arg @ref MD_DMA_SBUSEL_INCR16 - * @retval None - */ -__STATIC_INLINE void md_dma_set_csr1_sbusel(DMA_TypeDef *dma, uint32_t sbusel) -{ - MODIFY_REG(dma->CSR1, DMA_CSR1_SBUSEL_MSK, (sbusel<CSR1, DMA_CSR1_SBUSEL_MSK)>>DMA_CSR1_SBUSEL_POSS); -} -/** - * @brief Set Source Transfer Data Width Selection. - * @param dma DMA Instance - * @param sdwsel can be one of the following values: - * @arg @ref MD_DMA_SDWSEL_ONE_BYTE - * @arg @ref MD_DMA_SDWSEL_ONE_HALF_WORD - * @arg @ref MD_DMA_SDWSEL_ONE_WORD - * @retval None - */ -__STATIC_INLINE void md_dma_set_csr1_sdwsel(DMA_TypeDef *dma, uint32_t sdwsel) -{ - MODIFY_REG(dma->CSR1, DMA_CSR1_SDWSEL_MSK, (sdwsel<CSR1, DMA_CSR1_SDWSEL_MSK)>>DMA_CSR1_SDWSEL_POSS); -} -/** - * @brief Set Source Transfer Increment Mode - * @param dma DMA Instance - * @param dinc can be one of the following values: - * @arg @ref DISABLE - * @arg @ref ENABLE - * @retval None - */ -__STATIC_INLINE void md_dma_set_csr1_sinc(DMA_TypeDef *dma, uint32_t dinc) -{ - MODIFY_REG(dma->CSR1, DMA_CSR1_SINC_MSK, (dinc<CSR1, DMA_CSR1_SINC_MSK)>>DMA_CSR1_SINC_POS); -} -/** - * @brief Set Peripheral Handshake Software Select - * @param dma DMA Instance - * @param phss can be one of the following values: - * @arg @ref MD_DMA_PHSS_UART1_TX - * @arg @ref MD_DMA_PHSS_UART2_TX - * @arg @ref MD_DMA_PHSS_UART3_TX - * @arg @ref MD_DMA_PHSS_SUART1_TX - * @arg @ref MD_DMA_PHSS_SUART2_TX - * @arg @ref MD_DMA_PHSS_SPI1_TX - * @arg @ref MD_DMA_PHSS_SPI2_TX - * @arg @ref MD_DMA_PHSS_I2C1_TX - * @arg @ref MD_DMA_PHSS_I2C2_TX - * @arg @ref MD_DMA_PHSS_AES_IN - * @arg @ref MD_DMA_PHSS_DAC - * @arg @ref MD_DMA_PHSS_CRC - * @arg @ref MD_DMA_PHSS_UART1_RX - * @arg @ref MD_DMA_PHSS_UART2_RX - * @arg @ref MD_DMA_PHSS_UART3_RX - * @arg @ref MD_DMA_PHSS_SUART1_RX - * @arg @ref MD_DMA_PHSS_SUART2_RX - * @arg @ref MD_DMA_PHSS_SPI1_RTX - * @arg @ref MD_DMA_PHSS_SPI2_RX - * @arg @ref MD_DMA_PHSS_I2C1_RX - * @arg @ref MD_DMA_PHSS_I2C2_RX - * @arg @ref MD_DMA_PHSS_AES_OUT - * @arg @ref MD_DMA_PHSS_ADCSS0 - * @arg @ref MD_DMA_PHSS_ADCSS1 - * @arg @ref MD_DMA_PHSS_ADCSS2 - * @arg @ref MD_DMA_PHSS_ADCSS3 - * @arg @ref MD_DMA_PHSS_BS16T1_UP - * @arg @ref MD_DMA_PHSS_AD16C4T1_CH1 - * @arg @ref MD_DMA_PHSS_AD16C4T1_CH2 - * @arg @ref MD_DMA_PHSS_AD16C4T1_CH3 - * @arg @ref MD_DMA_PHSS_AD16C4T1_CH4 - * @arg @ref MD_DMA_PHSS_AD16C4T1_UP - * @arg @ref MD_DMA_PHSS_AD16C4T1_TRIG - * @arg @ref MD_DMA_PHSS_AD16C4T1_COM - * @arg @ref MD_DMA_PHSS_GP32C4T1_CH1 - * @arg @ref MD_DMA_PHSS_GP32C4T1_CH2 - * @arg @ref MD_DMA_PHSS_GP32C4T1_CH3 - * @arg @ref MD_DMA_PHSS_GP32C4T1_CH4 - * @arg @ref MD_DMA_PHSS_GP32C4T1_UP - * @arg @ref MD_DMA_PHSS_GP32C4T1_TRIG - * @arg @ref MD_DMA_PHSS_GP16C4T1_CH1 - * @arg @ref MD_DMA_PHSS_GP16C4T1_CH2 - * @arg @ref MD_DMA_PHSS_GP16C4T1_CH3 - * @arg @ref MD_DMA_PHSS_GP16C4T1_CH4 - * @arg @ref MD_DMA_PHSS_GP16C4T1_UP - * @arg @ref MD_DMA_PHSS_GP16C4T1_TRIG - * @arg @ref MD_DMA_PHSS_GP16C4T2_CH1 - * @arg @ref MD_DMA_PHSS_GP16C4T2_CH2 - * @arg @ref MD_DMA_PHSS_GP16C4T2_CH3 - * @arg @ref MD_DMA_PHSS_GP16C4T2_CH4 - * @arg @ref MD_DMA_PHSS_GP16C4T2_UP - * @arg @ref MD_DMA_PHSS_GP16C4T2_TRIG - * @arg @ref MD_DMA_PHSS_GP16C4T3_CH1 - * @arg @ref MD_DMA_PHSS_GP16C4T3_CH2 - * @arg @ref MD_DMA_PHSS_GP16C4T3_CH3 - * @arg @ref MD_DMA_PHSS_GP16C4T3_CH4 - * @arg @ref MD_DMA_PHSS_GP16C4T3_UP - * @arg @ref MD_DMA_PHSS_GP16C4T3_TRIG - * @arg @ref MD_DMA_PHSS_GP16C2T1_CH1 - * @arg @ref MD_DMA_PHSS_GP16C2T1_CH2 - * @arg @ref MD_DMA_PHSS_GP16C2T1_UP - * @arg @ref MD_DMA_PHSS_GP16C2T1_TRIG - * @arg @ref MD_DMA_PHSS_GP16C2T1_COM - * @arg @ref MD_DMA_PHSS_GP16C2T2_CH1 - * @arg @ref MD_DMA_PHSS_GP16C2T2_CH2 - * @arg @ref MD_DMA_PHSS_GP16C2T2_UP - * @arg @ref MD_DMA_PHSS_GP16C2T2_TRIG - * @arg @ref MD_DMA_PHSS_GP16C2T2_COM - * @arg @ref MD_DMA_PHSS_GP16C2T3_CH1 - * @arg @ref MD_DMA_PHSS_GP16C2T3_CH2 - * @arg @ref MD_DMA_PHSS_GP16C2T3_UP - * @arg @ref MD_DMA_PHSS_GP16C2T3_TRIG - * @arg @ref MD_DMA_PHSS_GP16C2T3_COM - * @arg @ref MD_DMA_PHSS_GP16C2T4_CH1 - * @arg @ref MD_DMA_PHSS_GP16C2T4_CH2 - * @arg @ref MD_DMA_PHSS_GP16C2T4_UP - * @arg @ref MD_DMA_PHSS_GP16C2T4_TRIG - * @arg @ref MD_DMA_PHSS_GP16C2T4_COM - * @retval None - */ -__STATIC_INLINE void md_dma_set_csr1_phss(DMA_TypeDef *dma, uint32_t phss) -{ - MODIFY_REG(dma->CSR1, DMA_CSR1_PHSS_MSK, (phss<CSR1, DMA_CSR1_PHSS_MSK)>>DMA_CSR1_PHSS_POSS); -} -/** - * @brief Set DMA Channel Priority. - * @param dma DMA Instance - * @param chpri can be one of the following values: - * @arg @ref MD_DMA_CHPRI_LV0 - * @arg @ref MD_DMA_CHPRI_LV1 - * @arg @ref MD_DMA_CHPRI_LV2 - * @arg @ref MD_DMA_CHPRI_LV3 - * @arg @ref MD_DMA_CHPRI_LV4 - * @arg @ref MD_DMA_CHPRI_LV5 - * @retval None - */ -__STATIC_INLINE void md_dma_set_csr1_chpri(DMA_TypeDef *dma, uint32_t chpri) -{ - MODIFY_REG(dma->CSR1, DMA_CSR1_CHPRI_MSK, (chpri<CSR1, DMA_CSR1_CHPRI_MSK)>>DMA_CSR1_CHPRI_POSS); -} -/** - * @brief Set DMA Mode Select. - * @param dma DMA Instance - * @param modesel can be one of the following values: - * @arg @ref MD_DMA_MODESEL_MEM_TO_MEM - * @arg @ref MD_DMA_MODESEL_PER_TO_MEM - * @arg @ref MD_DMA_MODESEL_MEM_TO_PER - * @retval None - */ -__STATIC_INLINE void md_dma_set_csr1_modesel(DMA_TypeDef *dma, uint32_t modesel) -{ - MODIFY_REG(dma->CSR1, DMA_CSR1_MODESEL_MSK, (modesel<CSR1, DMA_CSR1_MODESEL_MSK)>>DMA_CSR1_MODESEL_POSS); -} -/** - * @brief Set Direct Mode Enable. - * @param dma DMA Instance - * @param dirmden can be one of the following values: - * @arg Disable - * @arg Enable - * @retval None - */ -__STATIC_INLINE void md_dma_set_csr1_dirmden(DMA_TypeDef *dma, uint32_t dirmden) -{ - MODIFY_REG(dma->CSR1, DMA_CSR1_DIRMDEN_MSK, (dirmden<CSR1, DMA_CSR1_DIRMDEN_MSK)>>DMA_CSR1_DIRMDEN_POS); -} -/** - * @brief Set Peripheral flow controller - * @param dma DMA Instance - * @param pfctrl can be one of the following values: - * @arg @ref MD_DMA_PFCTRL_DMA_CTRL - * @arg @ref MD_DMA_PFCTRL_PER_CTRL - * @retval None - */ -__STATIC_INLINE void md_dma_set_csr1_pfctrl(DMA_TypeDef *dma, uint32_t pfctrl) -{ - MODIFY_REG(dma->CSR1, DMA_CSR1_PFCTRL_MSK, (pfctrl<CSR1, DMA_CSR1_PFCTRL_MSK)>>DMA_CSR1_PFCTRL_POS); -} -/** - * @brief Set Circular mode - * @param dma DMA Instance - * @param circ can be one of the following values: - * @arg Disable - * @arg Enable - * @retval None - */ -__STATIC_INLINE void md_dma_set_csr1_circ(DMA_TypeDef *dma, uint32_t circ) -{ - MODIFY_REG(dma->CSR1, DMA_CSR1_CIRC_MSK, (circ<CSR1, DMA_CSR1_CIRC_MSK)>>DMA_CSR1_CIRC_POS); -} -/** - * @brief Set DMA Channel Enable. - * @param dma DMA Instance - * @param chen can be one of the following values: - * @arg Disable - * @arg Enable - * @retval None - */ -__STATIC_INLINE void md_dma_set_csr1_chen(DMA_TypeDef *dma, uint32_t chen) -{ - MODIFY_REG(dma->CSR1, DMA_CSR1_CHEN_MSK, (chen<CSR1, DMA_CSR1_CHEN_MSK)>>DMA_CSR1_CHEN_POS); -} - -/** - * @brief Set DMA Transfer Source Address Register - * @note These bits are write-protected and can be written only when bit EN = '0' - * @param dma DMA Instance - * @param sar This field indicates a 32-bit source address of DMA. - * @retval None - */ -__STATIC_INLINE void md_dma_set_sar1_sar(DMA_TypeDef *dma, uint32_t sar) -{ - MODIFY_REG(dma->SAR1, DMA_SAR1_SAR_MSK, (sar<SAR1, DMA_SAR1_SAR_MSK)>>DMA_SAR1_SAR_POSS); -} - -/** - * @brief Set DMA Transfer Destination Address Register - * @note These bits are write-protected and can be written only when bit EN = '0' - * @param dma DMA Instance - * @param dar This field indicates a 32-bit source address of DMA. - * @retval None - */ -__STATIC_INLINE void md_dma_set_dar1_dar(DMA_TypeDef *dma, uint32_t dar) -{ - MODIFY_REG(dma->DAR1, DMA_DAR1_DAR_MSK, (dar<DAR1, DMA_DAR1_DAR_MSK)>>DMA_DAR1_DAR_POSS); -} - -/** - * @brief Get DMA Current Transfer Byte Count - * @param dma DMA Instance - * @retval The retval can be one of the following values: - * @arg Max Value 65535 - * @arg Min Value 0 - */ -__STATIC_INLINE uint32_t md_dma_get_bcr1_cbcr(DMA_TypeDef *dma) -{ - return (READ_BIT(dma->BCR1, DMA_BCR1_CBCR_MSK)>>DMA_BCR1_CBCR_POSS); -} -/** - * @brief Set DMA Transfer Byte Count Register - * @note These bits are write-protected and can be written only when bit EN = '0' - * @param dma DMA Instance - * @param bcr This field indicates a 16-bit transfer byte count of DMA. - * @retval None - */ -__STATIC_INLINE void md_dma_set_bcr1_bcr(DMA_TypeDef *dma, uint32_t bcr) -{ - MODIFY_REG(dma->BCR1, DMA_BCR1_BCR_MSK, (bcr<BCR1, DMA_BCR1_BCR_MSK)>>DMA_BCR1_BCR_POSS); -} - -/** - * @brief Set Destination Increment Offset Size bit. - * @note This bit has no meaning if bit DINC = '0'. - * This bit is protected and can be written only if EN = '0'. - * This bit is forced low by hardware when the stream is enabled (bit EN = '1') if the direct mode is selected or - * if DBUSEL are different from 00. - * @param dma DMA Instance - * @param dincos can be one of the following values: - * @arg @ref MD_DMA_DINCOS_LINKED_DWSEL - * @arg @ref MD_DMA_DINCOS_FIXED_TO_4 - * @retval None - */ -__STATIC_INLINE void md_dma_set_csr2_dincos(DMA_TypeDef *dma, uint32_t dincos) -{ - MODIFY_REG(dma->CSR2, DMA_CSR2_DINCOS_MSK, (dincos<CSR2, DMA_CSR2_DINCOS_MSK)>>DMA_CSR2_DINCOS_POS); -} -/** - * @brief Set Destination Transfer Burst Selection. - * @param dma DMA Instance - * @param dbusel can be one of the following values: - * @arg @ref MD_DMA_DBUSEL_SINGLE - * @arg @ref MD_DMA_DBUSEL_WRAP4 - * @arg @ref MD_DMA_DBUSEL_INCR4 - * @arg @ref MD_DMA_DBUSEL_WRAP8 - * @arg @ref MD_DMA_DBUSEL_INCR8 - * @arg @ref MD_DMA_DBUSEL_WRAP16 - * @arg @ref MD_DMA_DBUSEL_INCR16 - * @retval None - */ -__STATIC_INLINE void md_dma_set_csr2_dbusel(DMA_TypeDef *dma, uint32_t dbusel) -{ - MODIFY_REG(dma->CSR2, DMA_CSR2_DBUSEL_MSK, (dbusel<CSR2, DMA_CSR2_DBUSEL_MSK)>>DMA_CSR2_DBUSEL_POSS); -} -/** - * @brief Set Destination Transfer Data Width Selection. - * @param dma DMA Instance - * @param ddwsel can be one of the following values: - * @arg @ref MD_DMA_DDWSEL_ONE_BYTE - * @arg @ref MD_DMA_DDWSEL_ONE_HALF_WORD - * @arg @ref MD_DMA_DDWSEL_ONE_WORD - * @retval None - */ -__STATIC_INLINE void md_dma_set_csr2_ddwsel(DMA_TypeDef *dma, uint32_t ddwsel) -{ - MODIFY_REG(dma->CSR2, DMA_CSR2_DDWSEL_MSK, (ddwsel<CSR2, DMA_CSR2_DDWSEL_MSK)>>DMA_CSR2_DDWSEL_POSS); -} -/** - * @brief Set Destination Transfer Increment Mode - * @param dma DMA Instance - * @param dinc can be one of the following values: - * @arg @ref DISABLE - * @arg @ref ENABLE - * @retval None - */ -__STATIC_INLINE void md_dma_set_csr2_dinc(DMA_TypeDef *dma, uint32_t dinc) -{ - MODIFY_REG(dma->CSR2, DMA_CSR2_DINC_MSK, (dinc<CSR2, DMA_CSR2_DINC_MSK)>>DMA_CSR2_DINC_POS); -} -/** - * @brief Set Source Increment Offset Size bit. - * @note This bit has no meaning if bit SINC = '0'. - * This bit is protected and can be written only if EN = '0'. - * This bit is forced low by hardware when the stream is enabled (bit EN = '1') if the direct mode is selected or - * if SBUSEL are different from 00. - * @param dma DMA Instance - * @param sincos can be one of the following values: - * @arg @ref MD_DMA_SINCOS_LINKED_SWSEL - * @arg @ref MD_DMA_SINCOS_FIXED_TO_4 - * @retval None - */ -__STATIC_INLINE void md_dma_set_csr2_sincos(DMA_TypeDef *dma, uint32_t sincos) -{ - MODIFY_REG(dma->CSR2, DMA_CSR2_SINCOS_MSK, (sincos<CSR2, DMA_CSR2_SINCOS_MSK)>>DMA_CSR2_SINCOS_POS); -} -/** - * @brief Set Source Transfer Burst Selection. - * @param dma DMA Instance - * @param sbusel can be one of the following values: - * @arg @ref MD_DMA_SBUSEL_SINGLE - * @arg @ref MD_DMA_SBUSEL_WRAP4 - * @arg @ref MD_DMA_SBUSEL_INCR4 - * @arg @ref MD_DMA_SBUSEL_WRAP8 - * @arg @ref MD_DMA_SBUSEL_INCR8 - * @arg @ref MD_DMA_SBUSEL_WRAP16 - * @arg @ref MD_DMA_SBUSEL_INCR16 - * @retval None - */ -__STATIC_INLINE void md_dma_set_csr2_sbusel(DMA_TypeDef *dma, uint32_t sbusel) -{ - MODIFY_REG(dma->CSR2, DMA_CSR2_SBUSEL_MSK, (sbusel<CSR2, DMA_CSR2_SBUSEL_MSK)>>DMA_CSR2_SBUSEL_POSS); -} -/** - * @brief Set Source Transfer Data Width Selection. - * @param dma DMA Instance - * @param sdwsel can be one of the following values: - * @arg @ref MD_DMA_SDWSEL_ONE_BYTE - * @arg @ref MD_DMA_SDWSEL_ONE_HALF_WORD - * @arg @ref MD_DMA_SDWSEL_ONE_WORD - * @retval None - */ -__STATIC_INLINE void md_dma_set_csr2_sdwsel(DMA_TypeDef *dma, uint32_t sdwsel) -{ - MODIFY_REG(dma->CSR2, DMA_CSR2_SDWSEL_MSK, (sdwsel<CSR2, DMA_CSR2_SDWSEL_MSK)>>DMA_CSR2_SDWSEL_POSS); -} -/** - * @brief Set Source Transfer Increment Mode - * @param dma DMA Instance - * @param dinc can be one of the following values: - * @arg @ref DISABLE - * @arg @ref ENABLE - * @retval None - */ -__STATIC_INLINE void md_dma_set_csr2_sinc(DMA_TypeDef *dma, uint32_t dinc) -{ - MODIFY_REG(dma->CSR2, DMA_CSR2_SINC_MSK, (dinc<CSR2, DMA_CSR2_SINC_MSK)>>DMA_CSR2_SINC_POS); -} -/** - * @brief Set Peripheral Handshake Software Select - * @param dma DMA Instance - * @param phss can be one of the following values: - * @arg @ref MD_DMA_PHSS_UART1_TX - * @arg @ref MD_DMA_PHSS_UART2_TX - * @arg @ref MD_DMA_PHSS_UART3_TX - * @arg @ref MD_DMA_PHSS_SUART1_TX - * @arg @ref MD_DMA_PHSS_SUART2_TX - * @arg @ref MD_DMA_PHSS_SPI1_TX - * @arg @ref MD_DMA_PHSS_SPI2_TX - * @arg @ref MD_DMA_PHSS_I2C1_TX - * @arg @ref MD_DMA_PHSS_I2C2_TX - * @arg @ref MD_DMA_PHSS_AES_IN - * @arg @ref MD_DMA_PHSS_DAC - * @arg @ref MD_DMA_PHSS_CRC - * @arg @ref MD_DMA_PHSS_UART1_RX - * @arg @ref MD_DMA_PHSS_UART2_RX - * @arg @ref MD_DMA_PHSS_UART3_RX - * @arg @ref MD_DMA_PHSS_SUART1_RX - * @arg @ref MD_DMA_PHSS_SUART2_RX - * @arg @ref MD_DMA_PHSS_SPI1_RTX - * @arg @ref MD_DMA_PHSS_SPI2_RX - * @arg @ref MD_DMA_PHSS_I2C1_RX - * @arg @ref MD_DMA_PHSS_I2C2_RX - * @arg @ref MD_DMA_PHSS_AES_OUT - * @arg @ref MD_DMA_PHSS_ADCSS0 - * @arg @ref MD_DMA_PHSS_ADCSS1 - * @arg @ref MD_DMA_PHSS_ADCSS2 - * @arg @ref MD_DMA_PHSS_ADCSS3 - * @arg @ref MD_DMA_PHSS_BS16T1_UP - * @arg @ref MD_DMA_PHSS_AD16C4T1_CH1 - * @arg @ref MD_DMA_PHSS_AD16C4T1_CH2 - * @arg @ref MD_DMA_PHSS_AD16C4T1_CH3 - * @arg @ref MD_DMA_PHSS_AD16C4T1_CH4 - * @arg @ref MD_DMA_PHSS_AD16C4T1_UP - * @arg @ref MD_DMA_PHSS_AD16C4T1_TRIG - * @arg @ref MD_DMA_PHSS_AD16C4T1_COM - * @arg @ref MD_DMA_PHSS_GP32C4T1_CH1 - * @arg @ref MD_DMA_PHSS_GP32C4T1_CH2 - * @arg @ref MD_DMA_PHSS_GP32C4T1_CH3 - * @arg @ref MD_DMA_PHSS_GP32C4T1_CH4 - * @arg @ref MD_DMA_PHSS_GP32C4T1_UP - * @arg @ref MD_DMA_PHSS_GP32C4T1_TRIG - * @arg @ref MD_DMA_PHSS_GP16C4T1_CH1 - * @arg @ref MD_DMA_PHSS_GP16C4T1_CH2 - * @arg @ref MD_DMA_PHSS_GP16C4T1_CH3 - * @arg @ref MD_DMA_PHSS_GP16C4T1_CH4 - * @arg @ref MD_DMA_PHSS_GP16C4T1_UP - * @arg @ref MD_DMA_PHSS_GP16C4T1_TRIG - * @arg @ref MD_DMA_PHSS_GP16C4T2_CH1 - * @arg @ref MD_DMA_PHSS_GP16C4T2_CH2 - * @arg @ref MD_DMA_PHSS_GP16C4T2_CH3 - * @arg @ref MD_DMA_PHSS_GP16C4T2_CH4 - * @arg @ref MD_DMA_PHSS_GP16C4T2_UP - * @arg @ref MD_DMA_PHSS_GP16C4T2_TRIG - * @arg @ref MD_DMA_PHSS_GP16C4T3_CH1 - * @arg @ref MD_DMA_PHSS_GP16C4T3_CH2 - * @arg @ref MD_DMA_PHSS_GP16C4T3_CH3 - * @arg @ref MD_DMA_PHSS_GP16C4T3_CH4 - * @arg @ref MD_DMA_PHSS_GP16C4T3_UP - * @arg @ref MD_DMA_PHSS_GP16C4T3_TRIG - * @arg @ref MD_DMA_PHSS_GP16C2T1_CH1 - * @arg @ref MD_DMA_PHSS_GP16C2T1_CH2 - * @arg @ref MD_DMA_PHSS_GP16C2T1_UP - * @arg @ref MD_DMA_PHSS_GP16C2T1_TRIG - * @arg @ref MD_DMA_PHSS_GP16C2T1_COM - * @arg @ref MD_DMA_PHSS_GP16C2T2_CH1 - * @arg @ref MD_DMA_PHSS_GP16C2T2_CH2 - * @arg @ref MD_DMA_PHSS_GP16C2T2_UP - * @arg @ref MD_DMA_PHSS_GP16C2T2_TRIG - * @arg @ref MD_DMA_PHSS_GP16C2T2_COM - * @arg @ref MD_DMA_PHSS_GP16C2T3_CH1 - * @arg @ref MD_DMA_PHSS_GP16C2T3_CH2 - * @arg @ref MD_DMA_PHSS_GP16C2T3_UP - * @arg @ref MD_DMA_PHSS_GP16C2T3_TRIG - * @arg @ref MD_DMA_PHSS_GP16C2T3_COM - * @arg @ref MD_DMA_PHSS_GP16C2T4_CH1 - * @arg @ref MD_DMA_PHSS_GP16C2T4_CH2 - * @arg @ref MD_DMA_PHSS_GP16C2T4_UP - * @arg @ref MD_DMA_PHSS_GP16C2T4_TRIG - * @arg @ref MD_DMA_PHSS_GP16C2T4_COM - * @retval None - */ -__STATIC_INLINE void md_dma_set_csr2_phss(DMA_TypeDef *dma, uint32_t phss) -{ - MODIFY_REG(dma->CSR2, DMA_CSR2_PHSS_MSK, (phss<CSR2, DMA_CSR2_PHSS_MSK)>>DMA_CSR2_PHSS_POSS); -} -/** - * @brief Set DMA Channel Priority. - * @param dma DMA Instance - * @param chpri can be one of the following values: - * @arg @ref MD_DMA_CHPRI_LV0 - * @arg @ref MD_DMA_CHPRI_LV1 - * @arg @ref MD_DMA_CHPRI_LV2 - * @arg @ref MD_DMA_CHPRI_LV3 - * @arg @ref MD_DMA_CHPRI_LV4 - * @arg @ref MD_DMA_CHPRI_LV5 - * @retval None - */ -__STATIC_INLINE void md_dma_set_csr2_chpri(DMA_TypeDef *dma, uint32_t chpri) -{ - MODIFY_REG(dma->CSR2, DMA_CSR2_CHPRI_MSK, (chpri<CSR2, DMA_CSR2_CHPRI_MSK)>>DMA_CSR2_CHPRI_POSS); -} -/** - * @brief Set DMA Mode Select. - * @param dma DMA Instance - * @param modesel can be one of the following values: - * @arg @ref MD_DMA_MODESEL_MEM_TO_MEM - * @arg @ref MD_DMA_MODESEL_PER_TO_MEM - * @arg @ref MD_DMA_MODESEL_MEM_TO_PER - * @retval None - */ -__STATIC_INLINE void md_dma_set_csr2_modesel(DMA_TypeDef *dma, uint32_t modesel) -{ - MODIFY_REG(dma->CSR2, DMA_CSR2_MODESEL_MSK, (modesel<CSR2, DMA_CSR2_MODESEL_MSK)>>DMA_CSR2_MODESEL_POSS); -} -/** - * @brief Set Direct Mode Enable. - * @param dma DMA Instance - * @param dirmden can be one of the following values: - * @arg Disable - * @arg Enable - * @retval None - */ -__STATIC_INLINE void md_dma_set_csr2_dirmden(DMA_TypeDef *dma, uint32_t dirmden) -{ - MODIFY_REG(dma->CSR2, DMA_CSR2_DIRMDEN_MSK, (dirmden<CSR2, DMA_CSR2_DIRMDEN_MSK)>>DMA_CSR2_DIRMDEN_POS); -} -/** - * @brief Set Peripheral flow controller - * @param dma DMA Instance - * @param pfctrl can be one of the following values: - * @arg @ref MD_DMA_PFCTRL_DMA_CTRL - * @arg @ref MD_DMA_PFCTRL_PER_CTRL - * @retval None - */ -__STATIC_INLINE void md_dma_set_csr2_pfctrl(DMA_TypeDef *dma, uint32_t pfctrl) -{ - MODIFY_REG(dma->CSR2, DMA_CSR2_PFCTRL_MSK, (pfctrl<CSR2, DMA_CSR2_PFCTRL_MSK)>>DMA_CSR2_PFCTRL_POS); -} -/** - * @brief Set Circular mode - * @param dma DMA Instance - * @param circ can be one of the following values: - * @arg Disable - * @arg Enable - * @retval None - */ -__STATIC_INLINE void md_dma_set_csr2_circ(DMA_TypeDef *dma, uint32_t circ) -{ - MODIFY_REG(dma->CSR2, DMA_CSR2_CIRC_MSK, (circ<CSR2, DMA_CSR2_CIRC_MSK)>>DMA_CSR2_CIRC_POS); -} -/** - * @brief Set DMA Channel Enable. - * @param dma DMA Instance - * @param chen can be one of the following values: - * @arg Disable - * @arg Enable - * @retval None - */ -__STATIC_INLINE void md_dma_set_csr2_chen(DMA_TypeDef *dma, uint32_t chen) -{ - MODIFY_REG(dma->CSR2, DMA_CSR2_CHEN_MSK, (chen<CSR2, DMA_CSR2_CHEN_MSK)>>DMA_CSR2_CHEN_POS); -} - -/** - * @brief Set DMA Transfer Source Address Register - * @note These bits are write-protected and can be written only when bit EN = '0' - * @param dma DMA Instance - * @param sar This field indicates a 32-bit source address of DMA. - * @retval None - */ -__STATIC_INLINE void md_dma_set_sar2_sar(DMA_TypeDef *dma, uint32_t sar) -{ - MODIFY_REG(dma->SAR2, DMA_SAR2_SAR_MSK, (sar<SAR2, DMA_SAR2_SAR_MSK)>>DMA_SAR2_SAR_POSS); -} - -/** - * @brief Set DMA Transfer Destination Address Register - * @note These bits are write-protected and can be written only when bit EN = '0' - * @param dma DMA Instance - * @param dar This field indicates a 32-bit source address of DMA. - * @retval None - */ -__STATIC_INLINE void md_dma_set_dar2_dar(DMA_TypeDef *dma, uint32_t dar) -{ - MODIFY_REG(dma->DAR2, DMA_DAR2_DAR_MSK, (dar<DAR2, DMA_DAR2_DAR_MSK)>>DMA_DAR2_DAR_POSS); -} - -/** - * @brief Get DMA Current Transfer Byte Count - * @param dma DMA Instance - * @retval The retval can be one of the following values: - * @arg Max Value 65535 - * @arg Min Value 0 - */ -__STATIC_INLINE uint32_t md_dma_get_bcr2_cbcr(DMA_TypeDef *dma) -{ - return (READ_BIT(dma->BCR2, DMA_BCR2_CBCR_MSK)>>DMA_BCR2_CBCR_POSS); -} -/** - * @brief Set DMA Transfer Byte Count Register - * @note These bits are write-protected and can be written only when bit EN = '0' - * @param dma DMA Instance - * @param bcr This field indicates a 16-bit transfer byte count of DMA. - * @retval None - */ -__STATIC_INLINE void md_dma_set_bcr2_bcr(DMA_TypeDef *dma, uint32_t bcr) -{ - MODIFY_REG(dma->BCR2, DMA_BCR2_BCR_MSK, (bcr<BCR2, DMA_BCR2_BCR_MSK)>>DMA_BCR2_BCR_POSS); -} - -/** - * @brief Set Destination Increment Offset Size bit. - * @note This bit has no meaning if bit DINC = '0'. - * This bit is protected and can be written only if EN = '0'. - * This bit is forced low by hardware when the stream is enabled (bit EN = '1') if the direct mode is selected or - * if DBUSEL are different from 00. - * @param dma DMA Instance - * @param dincos can be one of the following values: - * @arg @ref MD_DMA_DINCOS_LINKED_DWSEL - * @arg @ref MD_DMA_DINCOS_FIXED_TO_4 - * @retval None - */ -__STATIC_INLINE void md_dma_set_csr3_dincos(DMA_TypeDef *dma, uint32_t dincos) -{ - MODIFY_REG(dma->CSR3, DMA_CSR3_DINCOS_MSK, (dincos<CSR3, DMA_CSR3_DINCOS_MSK)>>DMA_CSR3_DINCOS_POS); -} -/** - * @brief Set Destination Transfer Burst Selection. - * @param dma DMA Instance - * @param dbusel can be one of the following values: - * @arg @ref MD_DMA_DBUSEL_SINGLE - * @arg @ref MD_DMA_DBUSEL_WRAP4 - * @arg @ref MD_DMA_DBUSEL_INCR4 - * @arg @ref MD_DMA_DBUSEL_WRAP8 - * @arg @ref MD_DMA_DBUSEL_INCR8 - * @arg @ref MD_DMA_DBUSEL_WRAP16 - * @arg @ref MD_DMA_DBUSEL_INCR16 - * @retval None - */ -__STATIC_INLINE void md_dma_set_csr3_dbusel(DMA_TypeDef *dma, uint32_t dbusel) -{ - MODIFY_REG(dma->CSR3, DMA_CSR3_DBUSEL_MSK, (dbusel<CSR3, DMA_CSR3_DBUSEL_MSK)>>DMA_CSR3_DBUSEL_POSS); -} -/** - * @brief Set Destination Transfer Data Width Selection. - * @param dma DMA Instance - * @param ddwsel can be one of the following values: - * @arg @ref MD_DMA_DDWSEL_ONE_BYTE - * @arg @ref MD_DMA_DDWSEL_ONE_HALF_WORD - * @arg @ref MD_DMA_DDWSEL_ONE_WORD - * @retval None - */ -__STATIC_INLINE void md_dma_set_csr3_ddwsel(DMA_TypeDef *dma, uint32_t ddwsel) -{ - MODIFY_REG(dma->CSR3, DMA_CSR3_DDWSEL_MSK, (ddwsel<CSR3, DMA_CSR3_DDWSEL_MSK)>>DMA_CSR3_DDWSEL_POSS); -} -/** - * @brief Set Destination Transfer Increment Mode - * @param dma DMA Instance - * @param dinc can be one of the following values: - * @arg @ref DISABLE - * @arg @ref ENABLE - * @retval None - */ -__STATIC_INLINE void md_dma_set_csr3_dinc(DMA_TypeDef *dma, uint32_t dinc) -{ - MODIFY_REG(dma->CSR3, DMA_CSR3_DINC_MSK, (dinc<CSR3, DMA_CSR3_DINC_MSK)>>DMA_CSR3_DINC_POS); -} -/** - * @brief Set Source Increment Offset Size bit. - * @note This bit has no meaning if bit SINC = '0'. - * This bit is protected and can be written only if EN = '0'. - * This bit is forced low by hardware when the stream is enabled (bit EN = '1') if the direct mode is selected or - * if SBUSEL are different from 00. - * @param dma DMA Instance - * @param sincos can be one of the following values: - * @arg @ref MD_DMA_SINCOS_LINKED_SWSEL - * @arg @ref MD_DMA_SINCOS_FIXED_TO_4 - * @retval None - */ -__STATIC_INLINE void md_dma_set_csr3_sincos(DMA_TypeDef *dma, uint32_t sincos) -{ - MODIFY_REG(dma->CSR3, DMA_CSR3_SINCOS_MSK, (sincos<CSR3, DMA_CSR3_SINCOS_MSK)>>DMA_CSR3_SINCOS_POS); -} -/** - * @brief Set Source Transfer Burst Selection. - * @param dma DMA Instance - * @param sbusel can be one of the following values: - * @arg @ref MD_DMA_SBUSEL_SINGLE - * @arg @ref MD_DMA_SBUSEL_WRAP4 - * @arg @ref MD_DMA_SBUSEL_INCR4 - * @arg @ref MD_DMA_SBUSEL_WRAP8 - * @arg @ref MD_DMA_SBUSEL_INCR8 - * @arg @ref MD_DMA_SBUSEL_WRAP16 - * @arg @ref MD_DMA_SBUSEL_INCR16 - * @retval None - */ -__STATIC_INLINE void md_dma_set_csr3_sbusel(DMA_TypeDef *dma, uint32_t sbusel) -{ - MODIFY_REG(dma->CSR3, DMA_CSR3_SBUSEL_MSK, (sbusel<CSR3, DMA_CSR3_SBUSEL_MSK)>>DMA_CSR3_SBUSEL_POSS); -} -/** - * @brief Set Source Transfer Data Width Selection. - * @param dma DMA Instance - * @param sdwsel can be one of the following values: - * @arg @ref MD_DMA_SDWSEL_ONE_BYTE - * @arg @ref MD_DMA_SDWSEL_ONE_HALF_WORD - * @arg @ref MD_DMA_SDWSEL_ONE_WORD - * @retval None - */ -__STATIC_INLINE void md_dma_set_csr3_sdwsel(DMA_TypeDef *dma, uint32_t sdwsel) -{ - MODIFY_REG(dma->CSR3, DMA_CSR3_SDWSEL_MSK, (sdwsel<CSR3, DMA_CSR3_SDWSEL_MSK)>>DMA_CSR3_SDWSEL_POSS); -} -/** - * @brief Set Source Transfer Increment Mode - * @param dma DMA Instance - * @param dinc can be one of the following values: - * @arg @ref DISABLE - * @arg @ref ENABLE - * @retval None - */ -__STATIC_INLINE void md_dma_set_csr3_sinc(DMA_TypeDef *dma, uint32_t dinc) -{ - MODIFY_REG(dma->CSR3, DMA_CSR3_SINC_MSK, (dinc<CSR3, DMA_CSR3_SINC_MSK)>>DMA_CSR3_SINC_POS); -} -/** - * @brief Set Peripheral Handshake Software Select - * @param dma DMA Instance - * @param phss can be one of the following values: - * @arg @ref MD_DMA_PHSS_UART1_TX - * @arg @ref MD_DMA_PHSS_UART2_TX - * @arg @ref MD_DMA_PHSS_UART3_TX - * @arg @ref MD_DMA_PHSS_SUART1_TX - * @arg @ref MD_DMA_PHSS_SUART2_TX - * @arg @ref MD_DMA_PHSS_SPI1_TX - * @arg @ref MD_DMA_PHSS_SPI2_TX - * @arg @ref MD_DMA_PHSS_I2C1_TX - * @arg @ref MD_DMA_PHSS_I2C2_TX - * @arg @ref MD_DMA_PHSS_AES_IN - * @arg @ref MD_DMA_PHSS_DAC - * @arg @ref MD_DMA_PHSS_CRC - * @arg @ref MD_DMA_PHSS_UART1_RX - * @arg @ref MD_DMA_PHSS_UART2_RX - * @arg @ref MD_DMA_PHSS_UART3_RX - * @arg @ref MD_DMA_PHSS_SUART1_RX - * @arg @ref MD_DMA_PHSS_SUART2_RX - * @arg @ref MD_DMA_PHSS_SPI1_RTX - * @arg @ref MD_DMA_PHSS_SPI2_RX - * @arg @ref MD_DMA_PHSS_I2C1_RX - * @arg @ref MD_DMA_PHSS_I2C2_RX - * @arg @ref MD_DMA_PHSS_AES_OUT - * @arg @ref MD_DMA_PHSS_ADCSS0 - * @arg @ref MD_DMA_PHSS_ADCSS1 - * @arg @ref MD_DMA_PHSS_ADCSS2 - * @arg @ref MD_DMA_PHSS_ADCSS3 - * @arg @ref MD_DMA_PHSS_BS16T1_UP - * @arg @ref MD_DMA_PHSS_AD16C4T1_CH1 - * @arg @ref MD_DMA_PHSS_AD16C4T1_CH2 - * @arg @ref MD_DMA_PHSS_AD16C4T1_CH3 - * @arg @ref MD_DMA_PHSS_AD16C4T1_CH4 - * @arg @ref MD_DMA_PHSS_AD16C4T1_UP - * @arg @ref MD_DMA_PHSS_AD16C4T1_TRIG - * @arg @ref MD_DMA_PHSS_AD16C4T1_COM - * @arg @ref MD_DMA_PHSS_GP32C4T1_CH1 - * @arg @ref MD_DMA_PHSS_GP32C4T1_CH2 - * @arg @ref MD_DMA_PHSS_GP32C4T1_CH3 - * @arg @ref MD_DMA_PHSS_GP32C4T1_CH4 - * @arg @ref MD_DMA_PHSS_GP32C4T1_UP - * @arg @ref MD_DMA_PHSS_GP32C4T1_TRIG - * @arg @ref MD_DMA_PHSS_GP16C4T1_CH1 - * @arg @ref MD_DMA_PHSS_GP16C4T1_CH2 - * @arg @ref MD_DMA_PHSS_GP16C4T1_CH3 - * @arg @ref MD_DMA_PHSS_GP16C4T1_CH4 - * @arg @ref MD_DMA_PHSS_GP16C4T1_UP - * @arg @ref MD_DMA_PHSS_GP16C4T1_TRIG - * @arg @ref MD_DMA_PHSS_GP16C4T2_CH1 - * @arg @ref MD_DMA_PHSS_GP16C4T2_CH2 - * @arg @ref MD_DMA_PHSS_GP16C4T2_CH3 - * @arg @ref MD_DMA_PHSS_GP16C4T2_CH4 - * @arg @ref MD_DMA_PHSS_GP16C4T2_UP - * @arg @ref MD_DMA_PHSS_GP16C4T2_TRIG - * @arg @ref MD_DMA_PHSS_GP16C4T3_CH1 - * @arg @ref MD_DMA_PHSS_GP16C4T3_CH2 - * @arg @ref MD_DMA_PHSS_GP16C4T3_CH3 - * @arg @ref MD_DMA_PHSS_GP16C4T3_CH4 - * @arg @ref MD_DMA_PHSS_GP16C4T3_UP - * @arg @ref MD_DMA_PHSS_GP16C4T3_TRIG - * @arg @ref MD_DMA_PHSS_GP16C2T1_CH1 - * @arg @ref MD_DMA_PHSS_GP16C2T1_CH2 - * @arg @ref MD_DMA_PHSS_GP16C2T1_UP - * @arg @ref MD_DMA_PHSS_GP16C2T1_TRIG - * @arg @ref MD_DMA_PHSS_GP16C2T1_COM - * @arg @ref MD_DMA_PHSS_GP16C2T2_CH1 - * @arg @ref MD_DMA_PHSS_GP16C2T2_CH2 - * @arg @ref MD_DMA_PHSS_GP16C2T2_UP - * @arg @ref MD_DMA_PHSS_GP16C2T2_TRIG - * @arg @ref MD_DMA_PHSS_GP16C2T2_COM - * @arg @ref MD_DMA_PHSS_GP16C2T3_CH1 - * @arg @ref MD_DMA_PHSS_GP16C2T3_CH2 - * @arg @ref MD_DMA_PHSS_GP16C2T3_UP - * @arg @ref MD_DMA_PHSS_GP16C2T3_TRIG - * @arg @ref MD_DMA_PHSS_GP16C2T3_COM - * @arg @ref MD_DMA_PHSS_GP16C2T4_CH1 - * @arg @ref MD_DMA_PHSS_GP16C2T4_CH2 - * @arg @ref MD_DMA_PHSS_GP16C2T4_UP - * @arg @ref MD_DMA_PHSS_GP16C2T4_TRIG - * @arg @ref MD_DMA_PHSS_GP16C2T4_COM - * @retval None - */ -__STATIC_INLINE void md_dma_set_csr3_phss(DMA_TypeDef *dma, uint32_t phss) -{ - MODIFY_REG(dma->CSR3, DMA_CSR3_PHSS_MSK, (phss<CSR3, DMA_CSR3_PHSS_MSK)>>DMA_CSR3_PHSS_POSS); -} -/** - * @brief Set DMA Channel Priority. - * @param dma DMA Instance - * @param chpri can be one of the following values: - * @arg @ref MD_DMA_CHPRI_LV0 - * @arg @ref MD_DMA_CHPRI_LV1 - * @arg @ref MD_DMA_CHPRI_LV2 - * @arg @ref MD_DMA_CHPRI_LV3 - * @arg @ref MD_DMA_CHPRI_LV4 - * @arg @ref MD_DMA_CHPRI_LV5 - * @retval None - */ -__STATIC_INLINE void md_dma_set_csr3_chpri(DMA_TypeDef *dma, uint32_t chpri) -{ - MODIFY_REG(dma->CSR3, DMA_CSR3_CHPRI_MSK, (chpri<CSR3, DMA_CSR3_CHPRI_MSK)>>DMA_CSR3_CHPRI_POSS); -} -/** - * @brief Set DMA Mode Select. - * @param dma DMA Instance - * @param modesel can be one of the following values: - * @arg @ref MD_DMA_MODESEL_MEM_TO_MEM - * @arg @ref MD_DMA_MODESEL_PER_TO_MEM - * @arg @ref MD_DMA_MODESEL_MEM_TO_PER - * @retval None - */ -__STATIC_INLINE void md_dma_set_csr3_modesel(DMA_TypeDef *dma, uint32_t modesel) -{ - MODIFY_REG(dma->CSR3, DMA_CSR3_MODESEL_MSK, (modesel<CSR3, DMA_CSR3_MODESEL_MSK)>>DMA_CSR3_MODESEL_POSS); -} -/** - * @brief Set Direct Mode Enable. - * @param dma DMA Instance - * @param dirmden can be one of the following values: - * @arg Disable - * @arg Enable - * @retval None - */ -__STATIC_INLINE void md_dma_set_csr3_dirmden(DMA_TypeDef *dma, uint32_t dirmden) -{ - MODIFY_REG(dma->CSR3, DMA_CSR3_DIRMDEN_MSK, (dirmden<CSR3, DMA_CSR3_DIRMDEN_MSK)>>DMA_CSR3_DIRMDEN_POS); -} -/** - * @brief Set Peripheral flow controller - * @param dma DMA Instance - * @param pfctrl can be one of the following values: - * @arg @ref MD_DMA_PFCTRL_DMA_CTRL - * @arg @ref MD_DMA_PFCTRL_PER_CTRL - * @retval None - */ -__STATIC_INLINE void md_dma_set_csr3_pfctrl(DMA_TypeDef *dma, uint32_t pfctrl) -{ - MODIFY_REG(dma->CSR3, DMA_CSR3_PFCTRL_MSK, (pfctrl<CSR3, DMA_CSR3_PFCTRL_MSK)>>DMA_CSR3_PFCTRL_POS); -} -/** - * @brief Set Circular mode - * @param dma DMA Instance - * @param circ can be one of the following values: - * @arg Disable - * @arg Enable - * @retval None - */ -__STATIC_INLINE void md_dma_set_csr3_circ(DMA_TypeDef *dma, uint32_t circ) -{ - MODIFY_REG(dma->CSR3, DMA_CSR3_CIRC_MSK, (circ<CSR3, DMA_CSR3_CIRC_MSK)>>DMA_CSR3_CIRC_POS); -} -/** - * @brief Set DMA Channel Enable. - * @param dma DMA Instance - * @param chen can be one of the following values: - * @arg Disable - * @arg Enable - * @retval None - */ -__STATIC_INLINE void md_dma_set_csr3_chen(DMA_TypeDef *dma, uint32_t chen) -{ - MODIFY_REG(dma->CSR3, DMA_CSR3_CHEN_MSK, (chen<CSR3, DMA_CSR3_CHEN_MSK)>>DMA_CSR3_CHEN_POS); -} - -/** - * @brief Set DMA Transfer Source Address Register - * @note These bits are write-protected and can be written only when bit EN = '0' - * @param dma DMA Instance - * @param sar This field indicates a 32-bit source address of DMA. - * @retval None - */ -__STATIC_INLINE void md_dma_set_sar3_sar(DMA_TypeDef *dma, uint32_t sar) -{ - MODIFY_REG(dma->SAR3, DMA_SAR3_SAR_MSK, (sar<SAR3, DMA_SAR3_SAR_MSK)>>DMA_SAR3_SAR_POSS); -} - -/** - * @brief Set DMA Transfer Destination Address Register - * @note These bits are write-protected and can be written only when bit EN = '0' - * @param dma DMA Instance - * @param dar This field indicates a 32-bit source address of DMA. - * @retval None - */ -__STATIC_INLINE void md_dma_set_dar3_dar(DMA_TypeDef *dma, uint32_t dar) -{ - MODIFY_REG(dma->DAR3, DMA_DAR3_DAR_MSK, (dar<DAR3, DMA_DAR3_DAR_MSK)>>DMA_DAR3_DAR_POSS); -} - -/** - * @brief Get DMA Current Transfer Byte Count - * @param dma DMA Instance - * @retval The retval can be one of the following values: - * @arg Max Value 65535 - * @arg Min Value 0 - */ -__STATIC_INLINE uint32_t md_dma_get_bcr3_cbcr(DMA_TypeDef *dma) -{ - return (READ_BIT(dma->BCR3, DMA_BCR3_CBCR_MSK)>>DMA_BCR3_CBCR_POSS); -} -/** - * @brief Set DMA Transfer Byte Count Register - * @note These bits are write-protected and can be written only when bit EN = '0' - * @param dma DMA Instance - * @param bcr This field indicates a 16-bit transfer byte count of DMA. - * @retval None - */ -__STATIC_INLINE void md_dma_set_bcr3_bcr(DMA_TypeDef *dma, uint32_t bcr) -{ - MODIFY_REG(dma->BCR3, DMA_BCR3_BCR_MSK, (bcr<BCR3, DMA_BCR3_BCR_MSK)>>DMA_BCR3_BCR_POSS); -} - -/** - * @brief Set Destination Increment Offset Size bit. - * @note This bit has no meaning if bit DINC = '0'. - * This bit is protected and can be written only if EN = '0'. - * This bit is forced low by hardware when the stream is enabled (bit EN = '1') if the direct mode is selected or - * if DBUSEL are different from 00. - * @param dma DMA Instance - * @param dincos can be one of the following values: - * @arg @ref MD_DMA_DINCOS_LINKED_DWSEL - * @arg @ref MD_DMA_DINCOS_FIXED_TO_4 - * @retval None - */ -__STATIC_INLINE void md_dma_set_csr4_dincos(DMA_TypeDef *dma, uint32_t dincos) -{ - MODIFY_REG(dma->CSR4, DMA_CSR4_DINCOS_MSK, (dincos<CSR4, DMA_CSR4_DINCOS_MSK)>>DMA_CSR4_DINCOS_POS); -} -/** - * @brief Set Destination Transfer Burst Selection. - * @param dma DMA Instance - * @param dbusel can be one of the following values: - * @arg @ref MD_DMA_DBUSEL_SINGLE - * @arg @ref MD_DMA_DBUSEL_WRAP4 - * @arg @ref MD_DMA_DBUSEL_INCR4 - * @arg @ref MD_DMA_DBUSEL_WRAP8 - * @arg @ref MD_DMA_DBUSEL_INCR8 - * @arg @ref MD_DMA_DBUSEL_WRAP16 - * @arg @ref MD_DMA_DBUSEL_INCR16 - * @retval None - */ -__STATIC_INLINE void md_dma_set_csr4_dbusel(DMA_TypeDef *dma, uint32_t dbusel) -{ - MODIFY_REG(dma->CSR4, DMA_CSR4_DBUSEL_MSK, (dbusel<CSR4, DMA_CSR4_DBUSEL_MSK)>>DMA_CSR4_DBUSEL_POSS); -} -/** - * @brief Set Destination Transfer Data Width Selection. - * @param dma DMA Instance - * @param ddwsel can be one of the following values: - * @arg @ref MD_DMA_DDWSEL_ONE_BYTE - * @arg @ref MD_DMA_DDWSEL_ONE_HALF_WORD - * @arg @ref MD_DMA_DDWSEL_ONE_WORD - * @retval None - */ -__STATIC_INLINE void md_dma_set_csr4_ddwsel(DMA_TypeDef *dma, uint32_t ddwsel) -{ - MODIFY_REG(dma->CSR4, DMA_CSR4_DDWSEL_MSK, (ddwsel<CSR4, DMA_CSR4_DDWSEL_MSK)>>DMA_CSR4_DDWSEL_POSS); -} -/** - * @brief Set Destination Transfer Increment Mode - * @param dma DMA Instance - * @param dinc can be one of the following values: - * @arg @ref DISABLE - * @arg @ref ENABLE - * @retval None - */ -__STATIC_INLINE void md_dma_set_csr4_dinc(DMA_TypeDef *dma, uint32_t dinc) -{ - MODIFY_REG(dma->CSR4, DMA_CSR4_DINC_MSK, (dinc<CSR4, DMA_CSR4_DINC_MSK)>>DMA_CSR4_DINC_POS); -} -/** - * @brief Set Source Increment Offset Size bit. - * @note This bit has no meaning if bit SINC = '0'. - * This bit is protected and can be written only if EN = '0'. - * This bit is forced low by hardware when the stream is enabled (bit EN = '1') if the direct mode is selected or - * if SBUSEL are different from 00. - * @param dma DMA Instance - * @param sincos can be one of the following values: - * @arg @ref MD_DMA_SINCOS_LINKED_SWSEL - * @arg @ref MD_DMA_SINCOS_FIXED_TO_4 - * @retval None - */ -__STATIC_INLINE void md_dma_set_csr4_sincos(DMA_TypeDef *dma, uint32_t sincos) -{ - MODIFY_REG(dma->CSR4, DMA_CSR4_SINCOS_MSK, (sincos<CSR4, DMA_CSR4_SINCOS_MSK)>>DMA_CSR4_SINCOS_POS); -} -/** - * @brief Set Source Transfer Burst Selection. - * @param dma DMA Instance - * @param sbusel can be one of the following values: - * @arg @ref MD_DMA_SBUSEL_SINGLE - * @arg @ref MD_DMA_SBUSEL_WRAP4 - * @arg @ref MD_DMA_SBUSEL_INCR4 - * @arg @ref MD_DMA_SBUSEL_WRAP8 - * @arg @ref MD_DMA_SBUSEL_INCR8 - * @arg @ref MD_DMA_SBUSEL_WRAP16 - * @arg @ref MD_DMA_SBUSEL_INCR16 - * @retval None - */ -__STATIC_INLINE void md_dma_set_csr4_sbusel(DMA_TypeDef *dma, uint32_t sbusel) -{ - MODIFY_REG(dma->CSR4, DMA_CSR4_SBUSEL_MSK, (sbusel<CSR4, DMA_CSR4_SBUSEL_MSK)>>DMA_CSR4_SBUSEL_POSS); -} -/** - * @brief Set Source Transfer Data Width Selection. - * @param dma DMA Instance - * @param sdwsel can be one of the following values: - * @arg @ref MD_DMA_SDWSEL_ONE_BYTE - * @arg @ref MD_DMA_SDWSEL_ONE_HALF_WORD - * @arg @ref MD_DMA_SDWSEL_ONE_WORD - * @retval None - */ -__STATIC_INLINE void md_dma_set_csr4_sdwsel(DMA_TypeDef *dma, uint32_t sdwsel) -{ - MODIFY_REG(dma->CSR4, DMA_CSR4_SDWSEL_MSK, (sdwsel<CSR4, DMA_CSR4_SDWSEL_MSK)>>DMA_CSR4_SDWSEL_POSS); -} -/** - * @brief Set Source Transfer Increment Mode - * @param dma DMA Instance - * @param dinc can be one of the following values: - * @arg @ref DISABLE - * @arg @ref ENABLE - * @retval None - */ -__STATIC_INLINE void md_dma_set_csr4_sinc(DMA_TypeDef *dma, uint32_t dinc) -{ - MODIFY_REG(dma->CSR4, DMA_CSR4_SINC_MSK, (dinc<CSR4, DMA_CSR4_SINC_MSK)>>DMA_CSR4_SINC_POS); -} -/** - * @brief Set Peripheral Handshake Software Select - * @param dma DMA Instance - * @param phss can be one of the following values: - * @arg @ref MD_DMA_PHSS_UART1_TX - * @arg @ref MD_DMA_PHSS_UART2_TX - * @arg @ref MD_DMA_PHSS_UART3_TX - * @arg @ref MD_DMA_PHSS_SUART1_TX - * @arg @ref MD_DMA_PHSS_SUART2_TX - * @arg @ref MD_DMA_PHSS_SPI1_TX - * @arg @ref MD_DMA_PHSS_SPI2_TX - * @arg @ref MD_DMA_PHSS_I2C1_TX - * @arg @ref MD_DMA_PHSS_I2C2_TX - * @arg @ref MD_DMA_PHSS_AES_IN - * @arg @ref MD_DMA_PHSS_DAC - * @arg @ref MD_DMA_PHSS_CRC - * @arg @ref MD_DMA_PHSS_UART1_RX - * @arg @ref MD_DMA_PHSS_UART2_RX - * @arg @ref MD_DMA_PHSS_UART3_RX - * @arg @ref MD_DMA_PHSS_SUART1_RX - * @arg @ref MD_DMA_PHSS_SUART2_RX - * @arg @ref MD_DMA_PHSS_SPI1_RTX - * @arg @ref MD_DMA_PHSS_SPI2_RX - * @arg @ref MD_DMA_PHSS_I2C1_RX - * @arg @ref MD_DMA_PHSS_I2C2_RX - * @arg @ref MD_DMA_PHSS_AES_OUT - * @arg @ref MD_DMA_PHSS_ADCSS0 - * @arg @ref MD_DMA_PHSS_ADCSS1 - * @arg @ref MD_DMA_PHSS_ADCSS2 - * @arg @ref MD_DMA_PHSS_ADCSS3 - * @arg @ref MD_DMA_PHSS_BS16T1_UP - * @arg @ref MD_DMA_PHSS_AD16C4T1_CH1 - * @arg @ref MD_DMA_PHSS_AD16C4T1_CH2 - * @arg @ref MD_DMA_PHSS_AD16C4T1_CH3 - * @arg @ref MD_DMA_PHSS_AD16C4T1_CH4 - * @arg @ref MD_DMA_PHSS_AD16C4T1_UP - * @arg @ref MD_DMA_PHSS_AD16C4T1_TRIG - * @arg @ref MD_DMA_PHSS_AD16C4T1_COM - * @arg @ref MD_DMA_PHSS_GP32C4T1_CH1 - * @arg @ref MD_DMA_PHSS_GP32C4T1_CH2 - * @arg @ref MD_DMA_PHSS_GP32C4T1_CH3 - * @arg @ref MD_DMA_PHSS_GP32C4T1_CH4 - * @arg @ref MD_DMA_PHSS_GP32C4T1_UP - * @arg @ref MD_DMA_PHSS_GP32C4T1_TRIG - * @arg @ref MD_DMA_PHSS_GP16C4T1_CH1 - * @arg @ref MD_DMA_PHSS_GP16C4T1_CH2 - * @arg @ref MD_DMA_PHSS_GP16C4T1_CH3 - * @arg @ref MD_DMA_PHSS_GP16C4T1_CH4 - * @arg @ref MD_DMA_PHSS_GP16C4T1_UP - * @arg @ref MD_DMA_PHSS_GP16C4T1_TRIG - * @arg @ref MD_DMA_PHSS_GP16C4T2_CH1 - * @arg @ref MD_DMA_PHSS_GP16C4T2_CH2 - * @arg @ref MD_DMA_PHSS_GP16C4T2_CH3 - * @arg @ref MD_DMA_PHSS_GP16C4T2_CH4 - * @arg @ref MD_DMA_PHSS_GP16C4T2_UP - * @arg @ref MD_DMA_PHSS_GP16C4T2_TRIG - * @arg @ref MD_DMA_PHSS_GP16C4T3_CH1 - * @arg @ref MD_DMA_PHSS_GP16C4T3_CH2 - * @arg @ref MD_DMA_PHSS_GP16C4T3_CH3 - * @arg @ref MD_DMA_PHSS_GP16C4T3_CH4 - * @arg @ref MD_DMA_PHSS_GP16C4T3_UP - * @arg @ref MD_DMA_PHSS_GP16C4T3_TRIG - * @arg @ref MD_DMA_PHSS_GP16C2T1_CH1 - * @arg @ref MD_DMA_PHSS_GP16C2T1_CH2 - * @arg @ref MD_DMA_PHSS_GP16C2T1_UP - * @arg @ref MD_DMA_PHSS_GP16C2T1_TRIG - * @arg @ref MD_DMA_PHSS_GP16C2T1_COM - * @arg @ref MD_DMA_PHSS_GP16C2T2_CH1 - * @arg @ref MD_DMA_PHSS_GP16C2T2_CH2 - * @arg @ref MD_DMA_PHSS_GP16C2T2_UP - * @arg @ref MD_DMA_PHSS_GP16C2T2_TRIG - * @arg @ref MD_DMA_PHSS_GP16C2T2_COM - * @arg @ref MD_DMA_PHSS_GP16C2T3_CH1 - * @arg @ref MD_DMA_PHSS_GP16C2T3_CH2 - * @arg @ref MD_DMA_PHSS_GP16C2T3_UP - * @arg @ref MD_DMA_PHSS_GP16C2T3_TRIG - * @arg @ref MD_DMA_PHSS_GP16C2T3_COM - * @arg @ref MD_DMA_PHSS_GP16C2T4_CH1 - * @arg @ref MD_DMA_PHSS_GP16C2T4_CH2 - * @arg @ref MD_DMA_PHSS_GP16C2T4_UP - * @arg @ref MD_DMA_PHSS_GP16C2T4_TRIG - * @arg @ref MD_DMA_PHSS_GP16C2T4_COM - * @retval None - */ -__STATIC_INLINE void md_dma_set_csr4_phss(DMA_TypeDef *dma, uint32_t phss) -{ - MODIFY_REG(dma->CSR4, DMA_CSR4_PHSS_MSK, (phss<CSR4, DMA_CSR4_PHSS_MSK)>>DMA_CSR4_PHSS_POSS); -} -/** - * @brief Set DMA Channel Priority. - * @param dma DMA Instance - * @param chpri can be one of the following values: - * @arg @ref MD_DMA_CHPRI_LV0 - * @arg @ref MD_DMA_CHPRI_LV1 - * @arg @ref MD_DMA_CHPRI_LV2 - * @arg @ref MD_DMA_CHPRI_LV3 - * @arg @ref MD_DMA_CHPRI_LV4 - * @arg @ref MD_DMA_CHPRI_LV5 - * @retval None - */ -__STATIC_INLINE void md_dma_set_csr4_chpri(DMA_TypeDef *dma, uint32_t chpri) -{ - MODIFY_REG(dma->CSR4, DMA_CSR4_CHPRI_MSK, (chpri<CSR4, DMA_CSR4_CHPRI_MSK)>>DMA_CSR4_CHPRI_POSS); -} -/** - * @brief Set DMA Mode Select. - * @param dma DMA Instance - * @param modesel can be one of the following values: - * @arg @ref MD_DMA_MODESEL_MEM_TO_MEM - * @arg @ref MD_DMA_MODESEL_PER_TO_MEM - * @arg @ref MD_DMA_MODESEL_MEM_TO_PER - * @retval None - */ -__STATIC_INLINE void md_dma_set_csr4_modesel(DMA_TypeDef *dma, uint32_t modesel) -{ - MODIFY_REG(dma->CSR4, DMA_CSR4_MODESEL_MSK, (modesel<CSR4, DMA_CSR4_MODESEL_MSK)>>DMA_CSR4_MODESEL_POSS); -} -/** - * @brief Set Direct Mode Enable. - * @param dma DMA Instance - * @param dirmden can be one of the following values: - * @arg Disable - * @arg Enable - * @retval None - */ -__STATIC_INLINE void md_dma_set_csr4_dirmden(DMA_TypeDef *dma, uint32_t dirmden) -{ - MODIFY_REG(dma->CSR4, DMA_CSR4_DIRMDEN_MSK, (dirmden<CSR4, DMA_CSR4_DIRMDEN_MSK)>>DMA_CSR4_DIRMDEN_POS); -} -/** - * @brief Set Peripheral flow controller - * @param dma DMA Instance - * @param pfctrl can be one of the following values: - * @arg @ref MD_DMA_PFCTRL_DMA_CTRL - * @arg @ref MD_DMA_PFCTRL_PER_CTRL - * @retval None - */ -__STATIC_INLINE void md_dma_set_csr4_pfctrl(DMA_TypeDef *dma, uint32_t pfctrl) -{ - MODIFY_REG(dma->CSR4, DMA_CSR4_PFCTRL_MSK, (pfctrl<CSR4, DMA_CSR4_PFCTRL_MSK)>>DMA_CSR4_PFCTRL_POS); -} -/** - * @brief Set Circular mode - * @param dma DMA Instance - * @param circ can be one of the following values: - * @arg Disable - * @arg Enable - * @retval None - */ -__STATIC_INLINE void md_dma_set_csr4_circ(DMA_TypeDef *dma, uint32_t circ) -{ - MODIFY_REG(dma->CSR4, DMA_CSR4_CIRC_MSK, (circ<CSR4, DMA_CSR4_CIRC_MSK)>>DMA_CSR4_CIRC_POS); -} -/** - * @brief Set DMA Channel Enable. - * @param dma DMA Instance - * @param chen can be one of the following values: - * @arg Disable - * @arg Enable - * @retval None - */ -__STATIC_INLINE void md_dma_set_csr4_chen(DMA_TypeDef *dma, uint32_t chen) -{ - MODIFY_REG(dma->CSR4, DMA_CSR4_CHEN_MSK, (chen<CSR4, DMA_CSR4_CHEN_MSK)>>DMA_CSR4_CHEN_POS); -} - -/** - * @brief Set DMA Transfer Source Address Register - * @note These bits are write-protected and can be written only when bit EN = '0' - * @param dma DMA Instance - * @param sar This field indicates a 32-bit source address of DMA. - * @retval None - */ -__STATIC_INLINE void md_dma_set_sar4_sar(DMA_TypeDef *dma, uint32_t sar) -{ - MODIFY_REG(dma->SAR4, DMA_SAR4_SAR_MSK, (sar<SAR4, DMA_SAR4_SAR_MSK)>>DMA_SAR4_SAR_POSS); -} - -/** - * @brief Set DMA Transfer Destination Address Register - * @note These bits are write-protected and can be written only when bit EN = '0' - * @param dma DMA Instance - * @param dar This field indicates a 32-bit source address of DMA. - * @retval None - */ -__STATIC_INLINE void md_dma_set_dar4_dar(DMA_TypeDef *dma, uint32_t dar) -{ - MODIFY_REG(dma->DAR4, DMA_DAR4_DAR_MSK, (dar<DAR4, DMA_DAR4_DAR_MSK)>>DMA_DAR4_DAR_POSS); -} - -/** - * @brief Get DMA Current Transfer Byte Count - * @param dma DMA Instance - * @retval The retval can be one of the following values: - * @arg Max Value 65535 - * @arg Min Value 0 - */ -__STATIC_INLINE uint32_t md_dma_get_bcr4_cbcr(DMA_TypeDef *dma) -{ - return (READ_BIT(dma->BCR4, DMA_BCR4_CBCR_MSK)>>DMA_BCR4_CBCR_POSS); -} -/** - * @brief Set DMA Transfer Byte Count Register - * @note These bits are write-protected and can be written only when bit EN = '0' - * @param dma DMA Instance - * @param bcr This field indicates a 16-bit transfer byte count of DMA. - * @retval None - */ -__STATIC_INLINE void md_dma_set_bcr4_bcr(DMA_TypeDef *dma, uint32_t bcr) -{ - MODIFY_REG(dma->BCR4, DMA_BCR4_BCR_MSK, (bcr<BCR4, DMA_BCR4_BCR_MSK)>>DMA_BCR4_BCR_POSS); -} - -/** - * @brief Set Destination Increment Offset Size bit. - * @note This bit has no meaning if bit DINC = '0'. - * This bit is protected and can be written only if EN = '0'. - * This bit is forced low by hardware when the stream is enabled (bit EN = '1') if the direct mode is selected or - * if DBUSEL are different from 00. - * @param dma DMA Instance - * @param dincos can be one of the following values: - * @arg @ref MD_DMA_DINCOS_LINKED_DWSEL - * @arg @ref MD_DMA_DINCOS_FIXED_TO_4 - * @retval None - */ -__STATIC_INLINE void md_dma_set_csr5_dincos(DMA_TypeDef *dma, uint32_t dincos) -{ - MODIFY_REG(dma->CSR5, DMA_CSR5_DINCOS_MSK, (dincos<CSR5, DMA_CSR5_DINCOS_MSK)>>DMA_CSR5_DINCOS_POS); -} -/** - * @brief Set Destination Transfer Burst Selection. - * @param dma DMA Instance - * @param dbusel can be one of the following values: - * @arg @ref MD_DMA_DBUSEL_SINGLE - * @arg @ref MD_DMA_DBUSEL_WRAP4 - * @arg @ref MD_DMA_DBUSEL_INCR4 - * @arg @ref MD_DMA_DBUSEL_WRAP8 - * @arg @ref MD_DMA_DBUSEL_INCR8 - * @arg @ref MD_DMA_DBUSEL_WRAP16 - * @arg @ref MD_DMA_DBUSEL_INCR16 - * @retval None - */ -__STATIC_INLINE void md_dma_set_csr5_dbusel(DMA_TypeDef *dma, uint32_t dbusel) -{ - MODIFY_REG(dma->CSR5, DMA_CSR5_DBUSEL_MSK, (dbusel<CSR5, DMA_CSR5_DBUSEL_MSK)>>DMA_CSR5_DBUSEL_POSS); -} -/** - * @brief Set Destination Transfer Data Width Selection. - * @param dma DMA Instance - * @param ddwsel can be one of the following values: - * @arg @ref MD_DMA_DDWSEL_ONE_BYTE - * @arg @ref MD_DMA_DDWSEL_ONE_HALF_WORD - * @arg @ref MD_DMA_DDWSEL_ONE_WORD - * @retval None - */ -__STATIC_INLINE void md_dma_set_csr5_ddwsel(DMA_TypeDef *dma, uint32_t ddwsel) -{ - MODIFY_REG(dma->CSR5, DMA_CSR5_DDWSEL_MSK, (ddwsel<CSR5, DMA_CSR5_DDWSEL_MSK)>>DMA_CSR5_DDWSEL_POSS); -} -/** - * @brief Set Destination Transfer Increment Mode - * @param dma DMA Instance - * @param dinc can be one of the following values: - * @arg @ref DISABLE - * @arg @ref ENABLE - * @retval None - */ -__STATIC_INLINE void md_dma_set_csr5_dinc(DMA_TypeDef *dma, uint32_t dinc) -{ - MODIFY_REG(dma->CSR5, DMA_CSR5_DINC_MSK, (dinc<CSR5, DMA_CSR5_DINC_MSK)>>DMA_CSR5_DINC_POS); -} -/** - * @brief Set Source Increment Offset Size bit. - * @note This bit has no meaning if bit SINC = '0'. - * This bit is protected and can be written only if EN = '0'. - * This bit is forced low by hardware when the stream is enabled (bit EN = '1') if the direct mode is selected or - * if SBUSEL are different from 00. - * @param dma DMA Instance - * @param sincos can be one of the following values: - * @arg @ref MD_DMA_SINCOS_LINKED_SWSEL - * @arg @ref MD_DMA_SINCOS_FIXED_TO_4 - * @retval None - */ -__STATIC_INLINE void md_dma_set_csr5_sincos(DMA_TypeDef *dma, uint32_t sincos) -{ - MODIFY_REG(dma->CSR5, DMA_CSR5_SINCOS_MSK, (sincos<CSR5, DMA_CSR5_SINCOS_MSK)>>DMA_CSR5_SINCOS_POS); -} -/** - * @brief Set Source Transfer Burst Selection. - * @param dma DMA Instance - * @param sbusel can be one of the following values: - * @arg @ref MD_DMA_SBUSEL_SINGLE - * @arg @ref MD_DMA_SBUSEL_WRAP4 - * @arg @ref MD_DMA_SBUSEL_INCR4 - * @arg @ref MD_DMA_SBUSEL_WRAP8 - * @arg @ref MD_DMA_SBUSEL_INCR8 - * @arg @ref MD_DMA_SBUSEL_WRAP16 - * @arg @ref MD_DMA_SBUSEL_INCR16 - * @retval None - */ -__STATIC_INLINE void md_dma_set_csr5_sbusel(DMA_TypeDef *dma, uint32_t sbusel) -{ - MODIFY_REG(dma->CSR5, DMA_CSR5_SBUSEL_MSK, (sbusel<CSR5, DMA_CSR5_SBUSEL_MSK)>>DMA_CSR5_SBUSEL_POSS); -} -/** - * @brief Set Source Transfer Data Width Selection. - * @param dma DMA Instance - * @param sdwsel can be one of the following values: - * @arg @ref MD_DMA_SDWSEL_ONE_BYTE - * @arg @ref MD_DMA_SDWSEL_ONE_HALF_WORD - * @arg @ref MD_DMA_SDWSEL_ONE_WORD - * @retval None - */ -__STATIC_INLINE void md_dma_set_csr5_sdwsel(DMA_TypeDef *dma, uint32_t sdwsel) -{ - MODIFY_REG(dma->CSR5, DMA_CSR5_SDWSEL_MSK, (sdwsel<CSR5, DMA_CSR5_SDWSEL_MSK)>>DMA_CSR5_SDWSEL_POSS); -} -/** - * @brief Set Source Transfer Increment Mode - * @param dma DMA Instance - * @param dinc can be one of the following values: - * @arg @ref DISABLE - * @arg @ref ENABLE - * @retval None - */ -__STATIC_INLINE void md_dma_set_csr5_sinc(DMA_TypeDef *dma, uint32_t dinc) -{ - MODIFY_REG(dma->CSR5, DMA_CSR5_SINC_MSK, (dinc<CSR5, DMA_CSR5_SINC_MSK)>>DMA_CSR5_SINC_POS); -} -/** - * @brief Set Peripheral Handshake Software Select - * @param dma DMA Instance - * @param phss can be one of the following values: - * @arg @ref MD_DMA_PHSS_UART1_TX - * @arg @ref MD_DMA_PHSS_UART2_TX - * @arg @ref MD_DMA_PHSS_UART3_TX - * @arg @ref MD_DMA_PHSS_SUART1_TX - * @arg @ref MD_DMA_PHSS_SUART2_TX - * @arg @ref MD_DMA_PHSS_SPI1_TX - * @arg @ref MD_DMA_PHSS_SPI2_TX - * @arg @ref MD_DMA_PHSS_I2C1_TX - * @arg @ref MD_DMA_PHSS_I2C2_TX - * @arg @ref MD_DMA_PHSS_AES_IN - * @arg @ref MD_DMA_PHSS_DAC - * @arg @ref MD_DMA_PHSS_CRC - * @arg @ref MD_DMA_PHSS_UART1_RX - * @arg @ref MD_DMA_PHSS_UART2_RX - * @arg @ref MD_DMA_PHSS_UART3_RX - * @arg @ref MD_DMA_PHSS_SUART1_RX - * @arg @ref MD_DMA_PHSS_SUART2_RX - * @arg @ref MD_DMA_PHSS_SPI1_RTX - * @arg @ref MD_DMA_PHSS_SPI2_RX - * @arg @ref MD_DMA_PHSS_I2C1_RX - * @arg @ref MD_DMA_PHSS_I2C2_RX - * @arg @ref MD_DMA_PHSS_AES_OUT - * @arg @ref MD_DMA_PHSS_ADCSS0 - * @arg @ref MD_DMA_PHSS_ADCSS1 - * @arg @ref MD_DMA_PHSS_ADCSS2 - * @arg @ref MD_DMA_PHSS_ADCSS3 - * @arg @ref MD_DMA_PHSS_BS16T1_UP - * @arg @ref MD_DMA_PHSS_AD16C4T1_CH1 - * @arg @ref MD_DMA_PHSS_AD16C4T1_CH2 - * @arg @ref MD_DMA_PHSS_AD16C4T1_CH3 - * @arg @ref MD_DMA_PHSS_AD16C4T1_CH4 - * @arg @ref MD_DMA_PHSS_AD16C4T1_UP - * @arg @ref MD_DMA_PHSS_AD16C4T1_TRIG - * @arg @ref MD_DMA_PHSS_AD16C4T1_COM - * @arg @ref MD_DMA_PHSS_GP32C4T1_CH1 - * @arg @ref MD_DMA_PHSS_GP32C4T1_CH2 - * @arg @ref MD_DMA_PHSS_GP32C4T1_CH3 - * @arg @ref MD_DMA_PHSS_GP32C4T1_CH4 - * @arg @ref MD_DMA_PHSS_GP32C4T1_UP - * @arg @ref MD_DMA_PHSS_GP32C4T1_TRIG - * @arg @ref MD_DMA_PHSS_GP16C4T1_CH1 - * @arg @ref MD_DMA_PHSS_GP16C4T1_CH2 - * @arg @ref MD_DMA_PHSS_GP16C4T1_CH3 - * @arg @ref MD_DMA_PHSS_GP16C4T1_CH4 - * @arg @ref MD_DMA_PHSS_GP16C4T1_UP - * @arg @ref MD_DMA_PHSS_GP16C4T1_TRIG - * @arg @ref MD_DMA_PHSS_GP16C4T2_CH1 - * @arg @ref MD_DMA_PHSS_GP16C4T2_CH2 - * @arg @ref MD_DMA_PHSS_GP16C4T2_CH3 - * @arg @ref MD_DMA_PHSS_GP16C4T2_CH4 - * @arg @ref MD_DMA_PHSS_GP16C4T2_UP - * @arg @ref MD_DMA_PHSS_GP16C4T2_TRIG - * @arg @ref MD_DMA_PHSS_GP16C4T3_CH1 - * @arg @ref MD_DMA_PHSS_GP16C4T3_CH2 - * @arg @ref MD_DMA_PHSS_GP16C4T3_CH3 - * @arg @ref MD_DMA_PHSS_GP16C4T3_CH4 - * @arg @ref MD_DMA_PHSS_GP16C4T3_UP - * @arg @ref MD_DMA_PHSS_GP16C4T3_TRIG - * @arg @ref MD_DMA_PHSS_GP16C2T1_CH1 - * @arg @ref MD_DMA_PHSS_GP16C2T1_CH2 - * @arg @ref MD_DMA_PHSS_GP16C2T1_UP - * @arg @ref MD_DMA_PHSS_GP16C2T1_TRIG - * @arg @ref MD_DMA_PHSS_GP16C2T1_COM - * @arg @ref MD_DMA_PHSS_GP16C2T2_CH1 - * @arg @ref MD_DMA_PHSS_GP16C2T2_CH2 - * @arg @ref MD_DMA_PHSS_GP16C2T2_UP - * @arg @ref MD_DMA_PHSS_GP16C2T2_TRIG - * @arg @ref MD_DMA_PHSS_GP16C2T2_COM - * @arg @ref MD_DMA_PHSS_GP16C2T3_CH1 - * @arg @ref MD_DMA_PHSS_GP16C2T3_CH2 - * @arg @ref MD_DMA_PHSS_GP16C2T3_UP - * @arg @ref MD_DMA_PHSS_GP16C2T3_TRIG - * @arg @ref MD_DMA_PHSS_GP16C2T3_COM - * @arg @ref MD_DMA_PHSS_GP16C2T4_CH1 - * @arg @ref MD_DMA_PHSS_GP16C2T4_CH2 - * @arg @ref MD_DMA_PHSS_GP16C2T4_UP - * @arg @ref MD_DMA_PHSS_GP16C2T4_TRIG - * @arg @ref MD_DMA_PHSS_GP16C2T4_COM - * @retval None - */ -__STATIC_INLINE void md_dma_set_csr5_phss(DMA_TypeDef *dma, uint32_t phss) -{ - MODIFY_REG(dma->CSR5, DMA_CSR5_PHSS_MSK, (phss<CSR5, DMA_CSR5_PHSS_MSK)>>DMA_CSR5_PHSS_POSS); -} -/** - * @brief Set DMA Channel Priority. - * @param dma DMA Instance - * @param chpri can be one of the following values: - * @arg @ref MD_DMA_CHPRI_LV0 - * @arg @ref MD_DMA_CHPRI_LV1 - * @arg @ref MD_DMA_CHPRI_LV2 - * @arg @ref MD_DMA_CHPRI_LV3 - * @arg @ref MD_DMA_CHPRI_LV4 - * @arg @ref MD_DMA_CHPRI_LV5 - * @retval None - */ -__STATIC_INLINE void md_dma_set_csr5_chpri(DMA_TypeDef *dma, uint32_t chpri) -{ - MODIFY_REG(dma->CSR5, DMA_CSR5_CHPRI_MSK, (chpri<CSR5, DMA_CSR5_CHPRI_MSK)>>DMA_CSR5_CHPRI_POSS); -} -/** - * @brief Set DMA Mode Select. - * @param dma DMA Instance - * @param modesel can be one of the following values: - * @arg @ref MD_DMA_MODESEL_MEM_TO_MEM - * @arg @ref MD_DMA_MODESEL_PER_TO_MEM - * @arg @ref MD_DMA_MODESEL_MEM_TO_PER - * @retval None - */ -__STATIC_INLINE void md_dma_set_csr5_modesel(DMA_TypeDef *dma, uint32_t modesel) -{ - MODIFY_REG(dma->CSR5, DMA_CSR5_MODESEL_MSK, (modesel<CSR5, DMA_CSR5_MODESEL_MSK)>>DMA_CSR5_MODESEL_POSS); -} -/** - * @brief Set Direct Mode Enable. - * @param dma DMA Instance - * @param dirmden can be one of the following values: - * @arg Disable - * @arg Enable - * @retval None - */ -__STATIC_INLINE void md_dma_set_csr5_dirmden(DMA_TypeDef *dma, uint32_t dirmden) -{ - MODIFY_REG(dma->CSR5, DMA_CSR5_DIRMDEN_MSK, (dirmden<CSR5, DMA_CSR5_DIRMDEN_MSK)>>DMA_CSR5_DIRMDEN_POS); -} -/** - * @brief Set Peripheral flow controller - * @param dma DMA Instance - * @param pfctrl can be one of the following values: - * @arg @ref MD_DMA_PFCTRL_DMA_CTRL - * @arg @ref MD_DMA_PFCTRL_PER_CTRL - * @retval None - */ -__STATIC_INLINE void md_dma_set_csr5_pfctrl(DMA_TypeDef *dma, uint32_t pfctrl) -{ - MODIFY_REG(dma->CSR5, DMA_CSR5_PFCTRL_MSK, (pfctrl<CSR5, DMA_CSR5_PFCTRL_MSK)>>DMA_CSR5_PFCTRL_POS); -} -/** - * @brief Set Circular mode - * @param dma DMA Instance - * @param circ can be one of the following values: - * @arg Disable - * @arg Enable - * @retval None - */ -__STATIC_INLINE void md_dma_set_csr5_circ(DMA_TypeDef *dma, uint32_t circ) -{ - MODIFY_REG(dma->CSR5, DMA_CSR5_CIRC_MSK, (circ<CSR5, DMA_CSR5_CIRC_MSK)>>DMA_CSR5_CIRC_POS); -} -/** - * @brief Set DMA Channel Enable. - * @param dma DMA Instance - * @param chen can be one of the following values: - * @arg Disable - * @arg Enable - * @retval None - */ -__STATIC_INLINE void md_dma_set_csr5_chen(DMA_TypeDef *dma, uint32_t chen) -{ - MODIFY_REG(dma->CSR5, DMA_CSR5_CHEN_MSK, (chen<CSR5, DMA_CSR5_CHEN_MSK)>>DMA_CSR5_CHEN_POS); -} - -/** - * @brief Set DMA Transfer Source Address Register - * @note These bits are write-protected and can be written only when bit EN = '0' - * @param dma DMA Instance - * @param sar This field indicates a 32-bit source address of DMA. - * @retval None - */ -__STATIC_INLINE void md_dma_set_sar5_sar(DMA_TypeDef *dma, uint32_t sar) -{ - MODIFY_REG(dma->SAR5, DMA_SAR5_SAR_MSK, (sar<SAR5, DMA_SAR5_SAR_MSK)>>DMA_SAR5_SAR_POSS); -} - -/** - * @brief Set DMA Transfer Destination Address Register - * @note These bits are write-protected and can be written only when bit EN = '0' - * @param dma DMA Instance - * @param dar This field indicates a 32-bit source address of DMA. - * @retval None - */ -__STATIC_INLINE void md_dma_set_dar5_dar(DMA_TypeDef *dma, uint32_t dar) -{ - MODIFY_REG(dma->DAR5, DMA_DAR5_DAR_MSK, (dar<DAR5, DMA_DAR5_DAR_MSK)>>DMA_DAR5_DAR_POSS); -} - -/** - * @brief Get DMA Current Transfer Byte Count - * @param dma DMA Instance - * @retval The retval can be one of the following values: - * @arg Max Value 65535 - * @arg Min Value 0 - */ -__STATIC_INLINE uint32_t md_dma_get_bcr5_cbcr(DMA_TypeDef *dma) -{ - return (READ_BIT(dma->BCR5, DMA_BCR5_CBCR_MSK)>>DMA_BCR5_CBCR_POSS); -} -/** - * @brief Set DMA Transfer Byte Count Register - * @note These bits are write-protected and can be written only when bit EN = '0' - * @param dma DMA Instance - * @param bcr This field indicates a 16-bit transfer byte count of DMA. - * @retval None - */ -__STATIC_INLINE void md_dma_set_bcr5_bcr(DMA_TypeDef *dma, uint32_t bcr) -{ - MODIFY_REG(dma->BCR5, DMA_BCR5_BCR_MSK, (bcr<BCR5, DMA_BCR5_BCR_MSK)>>DMA_BCR5_BCR_POSS); -} - -/** - * @} MD_DMA_Public_Macros - */ - -/* Public functions -----------------------------------------------------------*/ -/** @defgroup MD_DMA_Public_Functions DMA Public Functions - * @{ - */ - -/** @defgroup MD_DMA_Basic_Configuration Basic Configuration - * @{ - */ - -/** - * @} MD_DMA_Basic_Configuration - */ - - -/** - * @} MD_DMA_Public_Functions - */ - -#endif - -/** - * @} DMA - */ - -/** - * @} Micro_Driver - */ - - -#ifdef __cplusplus -} -#endif - -#endif - -/******************* (C) COPYRIGHT Eastsoft Microelectronics *****END OF FILE****/ diff --git a/bsp/essemi/es32f0271/libraries/ES32F027x_MD_StdPeriph_Driver/Include/md_exti.h b/bsp/essemi/es32f0271/libraries/ES32F027x_MD_StdPeriph_Driver/Include/md_exti.h deleted file mode 100644 index 7f00f8320e..0000000000 --- a/bsp/essemi/es32f0271/libraries/ES32F027x_MD_StdPeriph_Driver/Include/md_exti.h +++ /dev/null @@ -1,5167 +0,0 @@ -/** - ****************************************************************************** - * @file md_EXTI.h - * @brief ES32F0271 EXTI HEAD File. - * - * @version V1.00.01 - * @date 22/11/2018 - * @author Eastsoft AE Team - * @note - * detailed description - * - * Copyright (C) 2018 Shanghai Eastsoft Microelectronics Co., Ltd. ALL rights reserved. - ******************************************************************************* - */ - -/* Define to prevent recursive inclusion -------------------------------------*/ -#ifndef __MD_EXTI_H__ -#define __MD_EXTI_H__ - -#ifdef __cplusplus -extern "C" { -#endif - -/* Includes -------------------------------------------------------------------*/ -#include "es32f0271.h" -#include "reg_exti.h" - -/** @addtogroup Micro_Driver - * @{ - */ - -#if defined (EXTI) -/** @defgroup EXTI EXTI - * @brief EXTI micro driver - * @{ - */ - - -/* Private types --------------------------------------------------------------*/ -/* Private variables ----------------------------------------------------------*/ -/* Private constants ----------------------------------------------------------*/ -/* Private macros -------------------------------------------------------------*/ -/* Public types ---------------------------------------------------------------*/ -/* Public constants -----------------------------------------------------------*/ - -/** @defgroup MD_EXTI_Public_Constants EXTI Public Constants - * @{ - */ - -/** @defgroup MD_EXTI_PC_Source EXTI Line Source - * @{ - */ -#define MD_EXTI_Pin_GPIOA (0x00000000UL) /*!< @brief Select GPIOA for EXTIx */ -#define MD_EXTI_Pin_GPIOB (0x00000001UL) /*!< @brief Select GPIOB for EXTIx */ -#define MD_EXTI_Pin_GPIOC (0x00000002UL) /*!< @brief Select GPIOC for EXTIx */ -#define MD_EXTI_Pin_GPIOD (0x00000003UL) /*!< @brief Select GPIOD for EXTIx */ - - /** - * @} MD_EXTI_PC_Source - */ - -/** -* @} MD_EXTI_Public_Constants -*/ - - - -/* Public macro ---------------------------------------------------------------*/ -/** @defgroup MD_EXTI_Public_Macros EXTI Public Macros - * @{ - */ - - - -/** @defgroup MD_EXTI_PF_Basic_Configuration EXTI Configuration Management - * @{ - */ -/** - * @brief Set EXTI interrupt configuration register 1 - * @param exti EXTI Instance - * @param value The value write in EXTI->ICFG1 - * @retval None - */ -__STATIC_INLINE void md_exti_set_icfg1(EXTI_TypeDef *exti, uint32_t value) -{ - WRITE_REG(exti->ICFG1, value); -} - -/** - * @brief Get EXTI interrupt configuration register 1 - * @param exti EXTI Instance - * @retval None - */ -__STATIC_INLINE uint32_t md_exti_get_icfg1(EXTI_TypeDef *exti) -{ - return (uint32_t)(READ_REG(exti->ICFG1)); -} - -/** - * @brief Set EXTI interrupt configuration register 2 - * @param exti EXTI Instance - * @param value The value write in EXTI->ICFG2 - * @retval None - */ -__STATIC_INLINE void md_exti_set_icfg2(EXTI_TypeDef *exti, uint32_t value) -{ - WRITE_REG(exti->ICFG2, value); -} - -/** - * @brief Get EXTI interrupt configuration register 2 - * @param exti EXTI Instance - * @retval None - */ -__STATIC_INLINE uint32_t md_exti_get_icfg2(EXTI_TypeDef *exti) -{ - return (uint32_t)(READ_REG(exti->ICFG2)); -} - -/** - * @brief Set EXTI0 configuration - * @param exti EXTI Instance - * @param Source This parameter can be one of the following values: - * @arg @ref MD_EXTI_Pin_GPIOA - * @arg @ref MD_EXTI_Pin_GPIOB - * @arg @ref MD_EXTI_Pin_GPIOC - * @arg @ref MD_EXTI_Pin_GPIOD - * @retval None - */ -__STATIC_INLINE void md_exti_set_icfg1_gpio0(EXTI_TypeDef *exti, uint32_t Source) -{ - MODIFY_REG(exti->ICFG1, EXTI_ICFG1_GPIO0_MSK, Source); -} - -/** - * @brief Get EXTI0 configuration - * @param exti EXTI Instance - * @retval Returned value can be one of the following values: - * @arg @ref MD_EXTI_Pin_GPIOA - * @arg @ref MD_EXTI_Pin_GPIOB - * @arg @ref MD_EXTI_Pin_GPIOC - * @arg @ref MD_EXTI_Pin_GPIOD - */ -__STATIC_INLINE uint32_t md_exti_get_icfg1_gpio0(EXTI_TypeDef *exti) -{ - return (uint32_t)(READ_BIT(exti->ICFG1, EXTI_ICFG1_GPIO0_MSK)>>EXTI_ICFG1_GPIO0_POSS); -} - -/** - * @brief Set EXTI1 configuration - * @param exti EXTI Instance - * @param Source This parameter can be one of the following values: - * @arg @ref MD_EXTI_Pin_GPIOA - * @arg @ref MD_EXTI_Pin_GPIOB - * @arg @ref MD_EXTI_Pin_GPIOC - * @arg @ref MD_EXTI_Pin_GPIOD - * @retval None - */ -__STATIC_INLINE void md_exti_set_icfg1_gpio1(EXTI_TypeDef *exti, uint32_t Source) -{ - MODIFY_REG(exti->ICFG1, EXTI_ICFG1_GPIO1_MSK, Source << EXTI_ICFG1_GPIO1_POSS); -} - -/** - * @brief Get EXTI1 configuration - * @param exti EXTI Instance - * @retval Returned value can be one of the following values: - * @arg @ref MD_EXTI_Pin_GPIOA - * @arg @ref MD_EXTI_Pin_GPIOB - * @arg @ref MD_EXTI_Pin_GPIOC - * @arg @ref MD_EXTI_Pin_GPIOD - */ -__STATIC_INLINE uint32_t md_exti_get_icfg1_gpio1(EXTI_TypeDef *exti) -{ - return (uint32_t)(READ_BIT(exti->ICFG1, EXTI_ICFG1_GPIO1_MSK)>>EXTI_ICFG1_GPIO1_POSS); -} - -/** - * @brief Set EXTI2 configuration - * @param exti EXTI Instance - * @param Source This parameter can be one of the following values: - * @arg @ref MD_EXTI_Pin_GPIOA - * @arg @ref MD_EXTI_Pin_GPIOB - * @arg @ref MD_EXTI_Pin_GPIOC - * @arg @ref MD_EXTI_Pin_GPIOD - * @retval None - */ -__STATIC_INLINE void md_exti_set_icfg1_gpio2(EXTI_TypeDef *exti, uint32_t Source) -{ - MODIFY_REG(exti->ICFG1, EXTI_ICFG1_GPIO2_MSK, Source << EXTI_ICFG1_GPIO2_POSS); -} - -/** - * @brief Get EXTI2 configuration - * @param exti EXTI Instance - * @retval Returned value can be one of the following values: - * @arg @ref MD_EXTI_Pin_GPIOA - * @arg @ref MD_EXTI_Pin_GPIOB - * @arg @ref MD_EXTI_Pin_GPIOC - * @arg @ref MD_EXTI_Pin_GPIOD - */ -__STATIC_INLINE uint32_t md_exti_get_icfg1_gpio2(EXTI_TypeDef *exti) -{ - return (uint32_t)(READ_BIT(exti->ICFG1, EXTI_ICFG1_GPIO2_MSK)>>EXTI_ICFG1_GPIO2_POSS); -} - -/** - * @brief Set EXTI3 configuration - * @param exti EXTI Instance - * @param Source This parameter can be one of the following values: - * @arg @ref MD_EXTI_Pin_GPIOA - * @arg @ref MD_EXTI_Pin_GPIOB - * @arg @ref MD_EXTI_Pin_GPIOC - * @arg @ref MD_EXTI_Pin_GPIOD - * @retval None - */ -__STATIC_INLINE void md_exti_set_icfg1_gpio3(EXTI_TypeDef *exti, uint32_t Source) -{ - MODIFY_REG(exti->ICFG1, EXTI_ICFG1_GPIO3_MSK, Source << EXTI_ICFG1_GPIO3_POSS); -} - -/** - * @brief Get EXTI3 configuration - * @param exti EXTI Instance - * @retval Returned value can be one of the following values: - * @arg @ref MD_EXTI_Pin_GPIOA - * @arg @ref MD_EXTI_Pin_GPIOB - * @arg @ref MD_EXTI_Pin_GPIOC - * @arg @ref MD_EXTI_Pin_GPIOD - */ -__STATIC_INLINE uint32_t md_exti_get_icfg1_gpio3(EXTI_TypeDef *exti) -{ - return (uint32_t)(READ_BIT(exti->ICFG1, EXTI_ICFG1_GPIO3_MSK)>>EXTI_ICFG1_GPIO0_POSS); -} - -/** - * @brief Set EXTI4 configuration - * @param exti EXTI Instance - * @param Source This parameter can be one of the following values: - * @arg @ref MD_EXTI_Pin_GPIOA - * @arg @ref MD_EXTI_Pin_GPIOB - * @arg @ref MD_EXTI_Pin_GPIOC - * @arg @ref MD_EXTI_Pin_GPIOD - * @retval None - */ -__STATIC_INLINE void md_exti_set_icfg1_gpio4(EXTI_TypeDef *exti, uint32_t Source) -{ - MODIFY_REG(exti->ICFG1, EXTI_ICFG1_GPIO4_MSK, Source << EXTI_ICFG1_GPIO4_POSS); -} - -/** - * @brief Get EXTI4 configuration - * @param exti EXTI Instance - * @retval Returned value can be one of the following values: - * @arg @ref MD_EXTI_Pin_GPIOA - * @arg @ref MD_EXTI_Pin_GPIOB - * @arg @ref MD_EXTI_Pin_GPIOC - * @arg @ref MD_EXTI_Pin_GPIOD - */ -__STATIC_INLINE uint32_t md_exti_get_icfg1_gpio4(EXTI_TypeDef *exti) -{ - return (uint32_t)(READ_BIT(exti->ICFG1, EXTI_ICFG1_GPIO4_MSK)>>EXTI_ICFG1_GPIO4_POSS); -} - -/** - * @brief Set EXTI5 configuration - * @param exti EXTI Instance - * @param Source This parameter can be one of the following values: - * @arg @ref MD_EXTI_Pin_GPIOA - * @arg @ref MD_EXTI_Pin_GPIOB - * @arg @ref MD_EXTI_Pin_GPIOC - * @arg @ref MD_EXTI_Pin_GPIOD - * @retval None - */ -__STATIC_INLINE void md_exti_set_icfg1_gpio5(EXTI_TypeDef *exti, uint32_t Source) -{ - MODIFY_REG(exti->ICFG1, EXTI_ICFG1_GPIO5_MSK, Source << EXTI_ICFG1_GPIO5_POSS); -} - -/** - * @brief Get EXTI5 configuration - * @param exti EXTI Instance - * @retval Returned value can be one of the following values: - * @arg @ref MD_EXTI_Pin_GPIOA - * @arg @ref MD_EXTI_Pin_GPIOB - * @arg @ref MD_EXTI_Pin_GPIOC - * @arg @ref MD_EXTI_Pin_GPIOD - */ -__STATIC_INLINE uint32_t md_exti_get_icfg1_gpio5(EXTI_TypeDef *exti) -{ - return (uint32_t)(READ_BIT(exti->ICFG1, EXTI_ICFG1_GPIO5_MSK)>>EXTI_ICFG1_GPIO5_POSS); -} - -/** - * @brief Set EXTI6 configuration - * @param exti EXTI Instance - * @param Source This parameter can be one of the following values: - * @arg @ref MD_EXTI_Pin_GPIOA - * @arg @ref MD_EXTI_Pin_GPIOB - * @arg @ref MD_EXTI_Pin_GPIOC - * @arg @ref MD_EXTI_Pin_GPIOD - * @retval None - */ -__STATIC_INLINE void md_exti_set_icfg1_gpio6(EXTI_TypeDef *exti, uint32_t Source) -{ - MODIFY_REG(exti->ICFG1, EXTI_ICFG1_GPIO6_MSK, Source << EXTI_ICFG1_GPIO6_POSS); -} - -/** - * @brief Get EXTI6 configuration - * @param exti EXTI Instance - * @retval Returned value can be one of the following values: - * @arg @ref MD_EXTI_Pin_GPIOA - * @arg @ref MD_EXTI_Pin_GPIOB - * @arg @ref MD_EXTI_Pin_GPIOC - * @arg @ref MD_EXTI_Pin_GPIOD - */ -__STATIC_INLINE uint32_t md_exti_get_icfg1_gpio6(EXTI_TypeDef *exti) -{ - return (uint32_t)(READ_BIT(exti->ICFG1, EXTI_ICFG1_GPIO6_MSK)>>EXTI_ICFG1_GPIO6_POSS); -} - -/** - * @brief Set EXTI7 configuration - * @param exti EXTI Instance - * @param Source This parameter can be one of the following values: - * @arg @ref MD_EXTI_Pin_GPIOA - * @arg @ref MD_EXTI_Pin_GPIOB - * @arg @ref MD_EXTI_Pin_GPIOC - * @arg @ref MD_EXTI_Pin_GPIOD - * @retval None - */ -__STATIC_INLINE void md_exti_set_icfg1_gpio7(EXTI_TypeDef *exti, uint32_t Source) -{ - MODIFY_REG(exti->ICFG1, EXTI_ICFG1_GPIO7_MSK, Source << EXTI_ICFG1_GPIO7_POSS); -} - -/** - * @brief Get EXTI7 configuration - * @param exti EXTI Instance - * @retval Returned value can be one of the following values: - * @arg @ref MD_EXTI_Pin_GPIOA - * @arg @ref MD_EXTI_Pin_GPIOB - * @arg @ref MD_EXTI_Pin_GPIOC - * @arg @ref MD_EXTI_Pin_GPIOD - */ -__STATIC_INLINE uint32_t md_exti_get_icfg1_gpio7(EXTI_TypeDef *exti) -{ - return (uint32_t)(READ_BIT(exti->ICFG1, EXTI_ICFG1_GPIO7_MSK)>>EXTI_ICFG1_GPIO7_POSS); -} - - -/** - * @brief Set EXTI8 configuration - * @param exti EXTI Instance - * @param Source This parameter can be one of the following values: - * @arg @ref MD_EXTI_Pin_GPIOA - * @arg @ref MD_EXTI_Pin_GPIOB - * @arg @ref MD_EXTI_Pin_GPIOC - * @arg @ref MD_EXTI_Pin_GPIOD - * @retval None - */ -__STATIC_INLINE void md_exti_set_icfg2_gpio8(EXTI_TypeDef *exti, uint32_t Source) -{ - MODIFY_REG(exti->ICFG2, EXTI_ICFG2_GPIO8_MSK, Source << EXTI_ICFG2_GPIO8_POSS); -} - -/** - * @brief Get EXTI8 configuration - * @param exti EXTI Instance - * @retval Returned value can be one of the following values: - * @arg @ref MD_EXTI_Pin_GPIOA - * @arg @ref MD_EXTI_Pin_GPIOB - * @arg @ref MD_EXTI_Pin_GPIOC - * @arg @ref MD_EXTI_Pin_GPIOD - */ -__STATIC_INLINE uint32_t md_exti_get_icfg2_gpio8(EXTI_TypeDef *exti) -{ - return (uint32_t)(READ_BIT(exti->ICFG2, EXTI_ICFG2_GPIO8_MSK)>>EXTI_ICFG2_GPIO8_POSS); -} - -/** - * @brief Set EXTI9 configuration - * @param exti EXTI Instance - * @param Source This parameter can be one of the following values: - * @arg @ref MD_EXTI_Pin_GPIOA - * @arg @ref MD_EXTI_Pin_GPIOB - * @arg @ref MD_EXTI_Pin_GPIOC - * @arg @ref MD_EXTI_Pin_GPIOD - * @retval None - */ -__STATIC_INLINE void md_exti_set_icfg2_gpio9(EXTI_TypeDef *exti, uint32_t Source) -{ - MODIFY_REG(exti->ICFG2, EXTI_ICFG2_GPIO9_MSK, Source << EXTI_ICFG2_GPIO9_POSS); -} - -/** - * @brief Get EXTI9 configuration - * @param exti EXTI Instance - * @retval Returned value can be one of the following values: - * @arg @ref MD_EXTI_Pin_GPIOA - * @arg @ref MD_EXTI_Pin_GPIOB - * @arg @ref MD_EXTI_Pin_GPIOC - * @arg @ref MD_EXTI_Pin_GPIOD - */ -__STATIC_INLINE uint32_t md_exti_get_icfg2_gpio9(EXTI_TypeDef *exti) -{ - return (uint32_t)(READ_BIT(exti->ICFG2, EXTI_ICFG2_GPIO9_MSK)>>EXTI_ICFG2_GPIO9_POSS); -} - -/** - * @brief Set EXTI10 configuration - * @param exti EXTI Instance - * @param Source This parameter can be one of the following values: - * @arg @ref MD_EXTI_Pin_GPIOA - * @arg @ref MD_EXTI_Pin_GPIOB - * @arg @ref MD_EXTI_Pin_GPIOC - * @arg @ref MD_EXTI_Pin_GPIOD - * @retval None - */ -__STATIC_INLINE void md_exti_set_icfg2_gpio10(EXTI_TypeDef *exti, uint32_t Source) -{ - MODIFY_REG(exti->ICFG2, EXTI_ICFG2_GPIO10_MSK, Source << EXTI_ICFG2_GPIO10_POSS); -} - -/** - * @brief Get EXTI10 configuration - * @param exti EXTI Instance - * @retval Returned value can be one of the following values: - * @arg @ref MD_EXTI_Pin_GPIOA - * @arg @ref MD_EXTI_Pin_GPIOB - * @arg @ref MD_EXTI_Pin_GPIOC - * @arg @ref MD_EXTI_Pin_GPIOD - */ -__STATIC_INLINE uint32_t md_exti_get_icfg2_gpio10(EXTI_TypeDef *exti) -{ - return (uint32_t)(READ_BIT(exti->ICFG2, EXTI_ICFG2_GPIO10_MSK)>>EXTI_ICFG2_GPIO10_POSS); -} - -/** - * @brief Set EXTI11 configuration - * @param exti EXTI Instance - * @param Source This parameter can be one of the following values: - * @arg @ref MD_EXTI_Pin_GPIOA - * @arg @ref MD_EXTI_Pin_GPIOB - * @arg @ref MD_EXTI_Pin_GPIOC - * @arg @ref MD_EXTI_Pin_GPIOD - * @retval None - */ -__STATIC_INLINE void md_exti_set_icfg2_gpio11(EXTI_TypeDef *exti, uint32_t Source) -{ - MODIFY_REG(exti->ICFG2, EXTI_ICFG2_GPIO11_MSK, Source << EXTI_ICFG2_GPIO11_POSS); -} - -/** - * @brief Get EXTI11 configuration - * @param exti EXTI Instance - * @retval Returned value can be one of the following values: - * @arg @ref MD_EXTI_Pin_GPIOA - * @arg @ref MD_EXTI_Pin_GPIOB - * @arg @ref MD_EXTI_Pin_GPIOC - * @arg @ref MD_EXTI_Pin_GPIOD - */ -__STATIC_INLINE uint32_t md_exti_get_icfg2_gpio11(EXTI_TypeDef *exti) -{ - return (uint32_t)(READ_BIT(exti->ICFG2, EXTI_ICFG2_GPIO11_MSK)>>EXTI_ICFG2_GPIO11_POSS); -} - -/** - * @brief Set EXTI12 configuration - * @param exti EXTI Instance - * @param Source This parameter can be one of the following values: - * @arg @ref MD_EXTI_Pin_GPIOA - * @arg @ref MD_EXTI_Pin_GPIOB - * @arg @ref MD_EXTI_Pin_GPIOC - * @arg @ref MD_EXTI_Pin_GPIOD - * @retval None - */ -__STATIC_INLINE void md_exti_set_icfg2_gpio12(EXTI_TypeDef *exti, uint32_t Source) -{ - MODIFY_REG(exti->ICFG2, EXTI_ICFG2_GPIO12_MSK, Source << EXTI_ICFG2_GPIO12_POSS); -} - -/** - * @brief Get EXTI12 configuration - * @param exti EXTI Instance - * @retval Returned value can be one of the following values: - * @arg @ref MD_EXTI_Pin_GPIOA - * @arg @ref MD_EXTI_Pin_GPIOB - * @arg @ref MD_EXTI_Pin_GPIOC - * @arg @ref MD_EXTI_Pin_GPIOD - */ -__STATIC_INLINE uint32_t md_exti_get_icfg2_gpio12(EXTI_TypeDef *exti) -{ - return (uint32_t)(READ_BIT(exti->ICFG2, EXTI_ICFG2_GPIO12_MSK)>>EXTI_ICFG2_GPIO12_POSS); -} - -/** - * @brief Set EXTI13 configuration - * @param exti EXTI Instance - * @param Source This parameter can be one of the following values: - * @arg @ref MD_EXTI_Pin_GPIOA - * @arg @ref MD_EXTI_Pin_GPIOB - * @arg @ref MD_EXTI_Pin_GPIOC - * @arg @ref MD_EXTI_Pin_GPIOD - * @retval None - */ -__STATIC_INLINE void md_exti_set_icfg2_gpio13(EXTI_TypeDef *exti, uint32_t Source) -{ - MODIFY_REG(exti->ICFG2, EXTI_ICFG2_GPIO13_MSK, Source << EXTI_ICFG2_GPIO13_POSS); -} - -/** - * @brief Get EXTI13 configuration - * @param exti EXTI Instance - * @retval Returned value can be one of the following values: - * @arg @ref MD_EXTI_Pin_GPIOA - * @arg @ref MD_EXTI_Pin_GPIOB - * @arg @ref MD_EXTI_Pin_GPIOC - * @arg @ref MD_EXTI_Pin_GPIOD - */ -__STATIC_INLINE uint32_t md_exti_get_icfg2_gpio13(EXTI_TypeDef *exti) -{ - return (uint32_t)(READ_BIT(exti->ICFG2, EXTI_ICFG2_GPIO13_MSK)>>EXTI_ICFG2_GPIO13_POSS); -} - -/** - * @brief Set EXTI14 configuration - * @param exti EXTI Instance - * @param Source This parameter can be one of the following values: - * @arg @ref MD_EXTI_Pin_GPIOA - * @arg @ref MD_EXTI_Pin_GPIOB - * @arg @ref MD_EXTI_Pin_GPIOC - * @arg @ref MD_EXTI_Pin_GPIOD - * @retval None - */ -__STATIC_INLINE void md_exti_set_icfg2_gpio14(EXTI_TypeDef *exti, uint32_t Source) -{ - MODIFY_REG(exti->ICFG2, EXTI_ICFG2_GPIO14_MSK, Source << EXTI_ICFG2_GPIO14_POSS); -} - -/** - * @brief Get EXTI14 configuration - * @param exti EXTI Instance - * @retval Returned value can be one of the following values: - * @arg @ref MD_EXTI_Pin_GPIOA - * @arg @ref MD_EXTI_Pin_GPIOB - * @arg @ref MD_EXTI_Pin_GPIOC - * @arg @ref MD_EXTI_Pin_GPIOD - */ -__STATIC_INLINE uint32_t md_exti_get_icfg2_gpio14(EXTI_TypeDef *exti) -{ - return (uint32_t)(READ_BIT(exti->ICFG2, EXTI_ICFG2_GPIO14_MSK)>>EXTI_ICFG2_GPIO14_POSS); -} - -/** - * @brief Set EXTI15 configuration - * @param exti EXTI Instance - * @param Source This parameter can be one of the following values: - * @arg @ref MD_EXTI_Pin_GPIOA - * @arg @ref MD_EXTI_Pin_GPIOB - * @arg @ref MD_EXTI_Pin_GPIOC - * @arg @ref MD_EXTI_Pin_GPIOD - * @retval None - */ -__STATIC_INLINE void md_exti_set_icfg2_gpio15(EXTI_TypeDef *exti, uint32_t Source) -{ - MODIFY_REG(exti->ICFG2, EXTI_ICFG2_GPIO15_MSK, Source << EXTI_ICFG2_GPIO15_POSS); -} - -/** - * @brief Get EXTI15 configuration - * @param exti EXTI Instance - * @retval Returned value can be one of the following values: - * @arg @ref MD_EXTI_Pin_GPIOA - * @arg @ref MD_EXTI_Pin_GPIOB - * @arg @ref MD_EXTI_Pin_GPIOC - * @arg @ref MD_EXTI_Pin_GPIOD - */ -__STATIC_INLINE uint32_t md_exti_get_icfg2_gpio15(EXTI_TypeDef *exti) -{ - return (uint32_t)(READ_BIT(exti->ICFG2, EXTI_ICFG2_GPIO15_MSK)>>EXTI_ICFG2_GPIO15_POSS); -} - -/** - * @} MD_EXTI_PF_Basic_Configuration - */ - -/** @defgroup MD_EXTI_PF_RTS EXTI Rising Edge Trigger Selection Register - * @{ - */ - -/** - * @brief Set rising trigger event configuration bit of line - * @param exti EXTI Instance - * @param value The value write in EXTI->RTS - * @retval None - */ -__STATIC_INLINE void md_exti_set_rts(EXTI_TypeDef *exti, uint32_t value) -{ - WRITE_REG(exti->RTS, value); -} - -/** - * @brief Get rising trigger event configuration bit of line - * @param exti EXTI Instance - * @retval None - */ -__STATIC_INLINE uint32_t md_exti_get_rts(EXTI_TypeDef *exti) -{ - return (uint32_t)(READ_REG(exti->RTS)); -} - -/** - * @brief Enable rising trigger event configuration bit of line 0 - * @param exti EXTI Instance - * @retval None - */ -__STATIC_INLINE void md_exti_enable_rts_gpio0(EXTI_TypeDef *exti) -{ - SET_BIT(exti->RTS, EXTI_RTS_GPIO0_MSK); -} - -/** - * @brief Disable rising trigger event configuration bit of line 0 - * @param exti EXTI Instance - * @retval None - */ -__STATIC_INLINE void md_exti_disable_rts_gpio0(EXTI_TypeDef *exti) -{ - CLEAR_BIT(exti->RTS, EXTI_RTS_GPIO0_MSK); -} - -/** - * @brief Check if rising trigger event configuration bit of line 0 is enabled - * @param exti EXTI Instance - * @retval State of bit (1 or 0). - */ -__STATIC_INLINE uint32_t md_exti_is_enable_rts_gpio0(EXTI_TypeDef *exti) -{ - return (READ_BIT(exti->RTS, EXTI_RTS_GPIO0_MSK) == (EXTI_RTS_GPIO0_MSK)); -} - -/** - * @brief Enable rising trigger event configuration bit of line 1 - * @param exti EXTI Instance - * @retval None - */ -__STATIC_INLINE void md_exti_enable_rts_gpio1(EXTI_TypeDef *exti) -{ - SET_BIT(exti->RTS, EXTI_RTS_GPIO1_MSK); -} - -/** - * @brief Disable rising trigger event configuration bit of line 1 - * @param exti EXTI Instance - * @retval None - */ -__STATIC_INLINE void md_exti_disable_rts_gpio1(EXTI_TypeDef *exti) -{ - CLEAR_BIT(exti->RTS, EXTI_RTS_GPIO1_MSK); -} - -/** - * @brief Check if rising trigger event configuration bit of line 1 is enabled - * @param exti EXTI Instance - * @retval State of bit (1 or 0). - */ -__STATIC_INLINE uint32_t md_exti_is_enable_rts_gpio1(EXTI_TypeDef *exti) -{ - return (READ_BIT(exti->RTS, EXTI_RTS_GPIO1_MSK) == (EXTI_RTS_GPIO1_MSK)); -} - -/** - * @brief Enable rising trigger event configuration bit of line 2 - * @param exti EXTI Instance - * @retval None - */ -__STATIC_INLINE void md_exti_enable_rts_gpio2(EXTI_TypeDef *exti) -{ - SET_BIT(exti->RTS, EXTI_RTS_GPIO2_MSK); -} - -/** - * @brief Disable rising trigger event configuration bit of line 2 - * @param exti EXTI Instance - * @retval None - */ -__STATIC_INLINE void md_exti_disable_rts_gpio2(EXTI_TypeDef *exti) -{ - CLEAR_BIT(exti->RTS, EXTI_RTS_GPIO2_MSK); -} - -/** - * @brief Check if rising trigger event configuration bit of line 2 is enabled - * @param exti EXTI Instance - * @retval State of bit (1 or 0). - */ -__STATIC_INLINE uint32_t md_exti_is_enable_rts_gpio2(EXTI_TypeDef *exti) -{ - return (READ_BIT(exti->RTS, EXTI_RTS_GPIO2_MSK) == (EXTI_RTS_GPIO2_MSK)); -} - -/** - * @brief Enable rising trigger event configuration bit of line 3 - * @param exti EXTI Instance - * @retval None - */ -__STATIC_INLINE void md_exti_enable_rts_gpio3(EXTI_TypeDef *exti) -{ - SET_BIT(exti->RTS, EXTI_RTS_GPIO3_MSK); -} - -/** - * @brief Disable rising trigger event configuration bit of line 3 - * @param exti EXTI Instance - * @retval None - */ -__STATIC_INLINE void md_exti_disable_rts_gpio3(EXTI_TypeDef *exti) -{ - CLEAR_BIT(exti->RTS, EXTI_RTS_GPIO3_MSK); -} - -/** - * @brief Check if rising trigger event configuration bit of line 3 is enabled - * @param exti EXTI Instance - * @retval State of bit (1 or 0). - */ -__STATIC_INLINE uint32_t md_exti_is_enable_rts_gpio3(EXTI_TypeDef *exti) -{ - return (READ_BIT(exti->RTS, EXTI_RTS_GPIO3_MSK) == (EXTI_RTS_GPIO3_MSK)); -} - -/** - * @brief Enable rising trigger event configuration bit of line 4 - * @param exti EXTI Instance - * @retval None - */ -__STATIC_INLINE void md_exti_enable_rts_gpio4(EXTI_TypeDef *exti) -{ - SET_BIT(exti->RTS, EXTI_RTS_GPIO4_MSK); -} - -/** - * @brief Disable rising trigger event configuration bit of line 4 - * @param exti EXTI Instance - * @retval None - */ -__STATIC_INLINE void md_exti_disable_rts_gpio4(EXTI_TypeDef *exti) -{ - CLEAR_BIT(exti->RTS, EXTI_RTS_GPIO4_MSK); -} - -/** - * @brief Check if rising trigger event configuration bit of line 4 is enabled - * @param exti EXTI Instance - * @retval State of bit (1 or 0). - */ -__STATIC_INLINE uint32_t md_exti_is_enable_rts_gpio4(EXTI_TypeDef *exti) -{ - return (READ_BIT(exti->RTS, EXTI_RTS_GPIO4_MSK) == (EXTI_RTS_GPIO4_MSK)); -} - -/** - * @brief Enable rising trigger event configuration bit of line 5 - * @param exti EXTI Instance - * @retval None - */ -__STATIC_INLINE void md_exti_enable_rts_gpio5(EXTI_TypeDef *exti) -{ - SET_BIT(exti->RTS, EXTI_RTS_GPIO5_MSK); -} - -/** - * @brief Disable rising trigger event configuration bit of line 5 - * @param exti EXTI Instance - * @retval None - */ -__STATIC_INLINE void md_exti_disable_rts_gpio5(EXTI_TypeDef *exti) -{ - CLEAR_BIT(exti->RTS, EXTI_RTS_GPIO5_MSK); -} - -/** - * @brief Check if rising trigger event configuration bit of line 5 is enabled - * @param exti EXTI Instance - * @retval State of bit (1 or 0). - */ -__STATIC_INLINE uint32_t md_exti_is_enable_rts_gpio5(EXTI_TypeDef *exti) -{ - return (READ_BIT(exti->RTS, EXTI_RTS_GPIO5_MSK) == (EXTI_RTS_GPIO5_MSK)); -} - -/** - * @brief Enable rising trigger event configuration bit of line 6 - * @param exti EXTI Instance - * @retval None - */ -__STATIC_INLINE void md_exti_enable_rts_gpio6(EXTI_TypeDef *exti) -{ - SET_BIT(exti->RTS, EXTI_RTS_GPIO6_MSK); -} - -/** - * @brief Disable rising trigger event configuration bit of line 6 - * @param exti EXTI Instance - * @retval None - */ -__STATIC_INLINE void md_exti_disable_rts_gpio6(EXTI_TypeDef *exti) -{ - CLEAR_BIT(exti->RTS, EXTI_RTS_GPIO6_MSK); -} - -/** - * @brief Check if rising trigger event configuration bit of line 1 is enabled - * @param exti EXTI Instance - * @retval State of bit (1 or 0). - */ -__STATIC_INLINE uint32_t md_exti_is_enable_rts_gpio6(EXTI_TypeDef *exti) -{ - return (READ_BIT(exti->RTS, EXTI_RTS_GPIO6_MSK) == (EXTI_RTS_GPIO6_MSK)); -} - -/** - * @brief Enable rising trigger event configuration bit of line 7 - * @param exti EXTI Instance - * @retval None - */ -__STATIC_INLINE void md_exti_enable_rts_gpio7(EXTI_TypeDef *exti) -{ - SET_BIT(exti->RTS, EXTI_RTS_GPIO7_MSK); -} - -/** - * @brief Disable rising trigger event configuration bit of line 7 - * @param exti EXTI Instance - * @retval None - */ -__STATIC_INLINE void md_exti_disable_rts_gpio7(EXTI_TypeDef *exti) -{ - CLEAR_BIT(exti->RTS, EXTI_RTS_GPIO7_MSK); -} - -/** - * @brief Check if rising trigger event configuration bit of line 7 is enabled - * @param exti EXTI Instance - * @retval State of bit (1 or 0). - */ -__STATIC_INLINE uint32_t md_exti_is_enable_rts_gpio7(EXTI_TypeDef *exti) -{ - return (READ_BIT(exti->RTS, EXTI_RTS_GPIO7_MSK) == (EXTI_RTS_GPIO7_MSK)); -} - -/** - * @brief Enable rising trigger event configuration bit of line 8 - * @param exti EXTI Instance - * @retval None - */ -__STATIC_INLINE void md_exti_enable_rts_gpio8(EXTI_TypeDef *exti) -{ - SET_BIT(exti->RTS, EXTI_RTS_GPIO8_MSK); -} - -/** - * @brief Disable rising trigger event configuration bit of line 8 - * @param exti EXTI Instance - * @retval None - */ -__STATIC_INLINE void md_exti_disable_rts_gpio8(EXTI_TypeDef *exti) -{ - CLEAR_BIT(exti->RTS, EXTI_RTS_GPIO8_MSK); -} - -/** - * @brief Check if rising trigger event configuration bit of line 8 is enabled - * @param exti EXTI Instance - * @retval State of bit (1 or 0). - */ -__STATIC_INLINE uint32_t md_exti_is_enable_rts_gpio8(EXTI_TypeDef *exti) -{ - return (READ_BIT(exti->RTS, EXTI_RTS_GPIO8_MSK) == (EXTI_RTS_GPIO8_MSK)); -} - -/** - * @brief Enable rising trigger event configuration bit of line 9 - * @param exti EXTI Instance - * @retval None - */ -__STATIC_INLINE void md_exti_enable_rts_gpio9(EXTI_TypeDef *exti) -{ - SET_BIT(exti->RTS, EXTI_RTS_GPIO9_MSK); -} - -/** - * @brief Disable rising trigger event configuration bit of line 9 - * @param exti EXTI Instance - * @retval None - */ -__STATIC_INLINE void md_exti_disable_rts_gpio9(EXTI_TypeDef *exti) -{ - CLEAR_BIT(exti->RTS, EXTI_RTS_GPIO9_MSK); -} - -/** - * @brief Check if rising trigger event configuration bit of line 9 is enabled - * @param exti EXTI Instance - * @retval State of bit (1 or 0). - */ -__STATIC_INLINE uint32_t md_exti_is_enable_rts_gpio9(EXTI_TypeDef *exti) -{ - return (READ_BIT(exti->RTS, EXTI_RTS_GPIO9_MSK) == (EXTI_RTS_GPIO9_MSK)); -} - -/** - * @brief Enable rising trigger event configuration bit of line 10 - * @param exti EXTI Instance - * @retval None - */ -__STATIC_INLINE void md_exti_enable_rts_gpio10(EXTI_TypeDef *exti) -{ - SET_BIT(exti->RTS, EXTI_RTS_GPIO10_MSK); -} - -/** - * @brief Disable rising trigger event configuration bit of line 10 - * @param exti EXTI Instance - * @retval None - */ -__STATIC_INLINE void md_exti_disable_rts_gpio10(EXTI_TypeDef *exti) -{ - CLEAR_BIT(exti->RTS, EXTI_RTS_GPIO10_MSK); -} - -/** - * @brief Check if rising trigger event configuration bit of line 10 is enabled - * @param exti EXTI Instance - * @retval State of bit (1 or 0). - */ -__STATIC_INLINE uint32_t md_exti_is_enable_rts_gpio10(EXTI_TypeDef *exti) -{ - return (READ_BIT(exti->RTS, EXTI_RTS_GPIO10_MSK) == (EXTI_RTS_GPIO10_MSK)); -} - -/** - * @brief Enable rising trigger event configuration bit of line 11 - * @param exti EXTI Instance - * @retval None - */ -__STATIC_INLINE void md_exti_enable_rts_gpio11(EXTI_TypeDef *exti) -{ - SET_BIT(exti->RTS, EXTI_RTS_GPIO11_MSK); -} - -/** - * @brief Disable rising trigger event configuration bit of line 11 - * @param exti EXTI Instance - * @retval None - */ -__STATIC_INLINE void md_exti_disable_rts_gpio11(EXTI_TypeDef *exti) -{ - CLEAR_BIT(exti->RTS, EXTI_RTS_GPIO11_MSK); -} - -/** - * @brief Check if rising trigger event configuration bit of line 11 is enabled - * @param exti EXTI Instance - * @retval State of bit (1 or 0). - */ -__STATIC_INLINE uint32_t md_exti_is_enable_rts_gpio11(EXTI_TypeDef *exti) -{ - return (READ_BIT(exti->RTS, EXTI_RTS_GPIO11_MSK) == (EXTI_RTS_GPIO11_MSK)); -} - -/** - * @brief Enable rising trigger event configuration bit of line 12 - * @param exti EXTI Instance - * @retval None - */ -__STATIC_INLINE void md_exti_enable_rts_gpio12(EXTI_TypeDef *exti) -{ - SET_BIT(exti->RTS, EXTI_RTS_GPIO12_MSK); -} - -/** - * @brief Disable rising trigger event configuration bit of line 12 - * @param exti EXTI Instance - * @retval None - */ -__STATIC_INLINE void md_exti_disable_rts_gpio12(EXTI_TypeDef *exti) -{ - CLEAR_BIT(exti->RTS, EXTI_RTS_GPIO12_MSK); -} - -/** - * @brief Check if rising trigger event configuration bit of line 12 is enabled - * @param exti EXTI Instance - * @retval State of bit (1 or 0). - */ -__STATIC_INLINE uint32_t md_exti_is_enable_rts_gpio12(EXTI_TypeDef *exti) -{ - return (READ_BIT(exti->RTS, EXTI_RTS_GPIO12_MSK) == (EXTI_RTS_GPIO12_MSK)); -} - -/** - * @brief Enable rising trigger event configuration bit of line 13 - * @param exti EXTI Instance - * @retval None - */ -__STATIC_INLINE void md_exti_enable_rts_gpio13(EXTI_TypeDef *exti) -{ - SET_BIT(exti->RTS, EXTI_RTS_GPIO13_MSK); -} - -/** - * @brief Disable rising trigger event configuration bit of line 13 - * @param exti EXTI Instance - * @retval None - */ -__STATIC_INLINE void md_exti_disable_rts_gpio13(EXTI_TypeDef *exti) -{ - CLEAR_BIT(exti->RTS, EXTI_RTS_GPIO13_MSK); -} - -/** - * @brief Check if rising trigger event configuration bit of line 13 is enabled - * @param exti EXTI Instance - * @retval State of bit (1 or 0). - */ -__STATIC_INLINE uint32_t md_exti_is_enable_rts_gpio13(EXTI_TypeDef *exti) -{ - return (READ_BIT(exti->RTS, EXTI_RTS_GPIO13_MSK) == (EXTI_RTS_GPIO13_MSK)); -} - -/** - * @brief Enable rising trigger event configuration bit of line 14 - * @param exti EXTI Instance - * @retval None - */ -__STATIC_INLINE void md_exti_enable_rts_gpio14(EXTI_TypeDef *exti) -{ - SET_BIT(exti->RTS, EXTI_RTS_GPIO14_MSK); -} - -/** - * @brief Disable rising trigger event configuration bit of line 14 - * @param exti EXTI Instance - * @retval None - */ -__STATIC_INLINE void md_exti_disable_rts_gpio14(EXTI_TypeDef *exti) -{ - CLEAR_BIT(exti->RTS, EXTI_RTS_GPIO14_MSK); -} - -/** - * @brief Check if rising trigger event configuration bit of line 14 is enabled - * @param exti EXTI Instance - * @retval State of bit (1 or 0). - */ -__STATIC_INLINE uint32_t md_exti_is_enable_rts_gpio14(EXTI_TypeDef *exti) -{ - return (READ_BIT(exti->RTS, EXTI_RTS_GPIO14_MSK) == (EXTI_RTS_GPIO14_MSK)); -} - -/** - * @brief Enable rising trigger event configuration bit of line 15 - * @param exti EXTI Instance - * @retval None - */ -__STATIC_INLINE void md_exti_enable_rts_gpio15(EXTI_TypeDef *exti) -{ - SET_BIT(exti->RTS, EXTI_RTS_GPIO15_MSK); -} - -/** - * @brief Disable rising trigger event configuration bit of line 15 - * @param exti EXTI Instance - * @retval None - */ -__STATIC_INLINE void md_exti_disable_rts_gpio15(EXTI_TypeDef *exti) -{ - CLEAR_BIT(exti->RTS, EXTI_RTS_GPIO15_MSK); -} - -/** - * @brief Check if rising trigger event configuration bit of line 15 is enabled - * @param exti EXTI Instance - * @retval State of bit (1 or 0). - */ -__STATIC_INLINE uint32_t md_exti_is_enable_rts_gpio15(EXTI_TypeDef *exti) -{ - return (READ_BIT(exti->RTS, EXTI_RTS_GPIO15_MSK) == (EXTI_RTS_GPIO15_MSK)); -} - - -/** - * @brief Enable rising trigger event configuration bit of line 16 - * @param exti EXTI Instance - * @retval None - */ -__STATIC_INLINE void md_exti_enable_rts_cmp1(EXTI_TypeDef *exti) -{ - SET_BIT(exti->RTS, EXTI_RTS_CMP1_MSK); -} - -/** - * @brief Disable rising trigger event configuration bit of line 16 - * @param exti EXTI Instance - * @retval None - */ -__STATIC_INLINE void md_exti_disable_rts_cmp1(EXTI_TypeDef *exti) -{ - CLEAR_BIT(exti->RTS, EXTI_RTS_CMP1_MSK); -} - -/** - * @brief Check if rising trigger event configuration bit of line 16 is enabled - * @param exti EXTI Instance - * @retval State of bit (1 or 0). - */ -__STATIC_INLINE uint32_t md_exti_is_enable_rts_cmp1(EXTI_TypeDef *exti) -{ - return (READ_BIT(exti->RTS, EXTI_RTS_CMP1_MSK) == (EXTI_RTS_CMP1_MSK)); -} - -/** - * @brief Enable rising trigger event configuration bit of line 17 - * @param exti EXTI Instance - * @retval None - */ -__STATIC_INLINE void md_exti_enable_rts_cmp2(EXTI_TypeDef *exti) -{ - SET_BIT(exti->RTS, EXTI_RTS_CMP2_MSK); -} - -/** - * @brief Disable rising trigger event configuration bit of line 17 - * @param exti EXTI Instance - * @retval None - */ -__STATIC_INLINE void md_exti_disable_rts_cmp2(EXTI_TypeDef *exti) -{ - CLEAR_BIT(exti->RTS, EXTI_RTS_CMP2_MSK); -} - -/** - * @brief Check if rising trigger event configuration bit of line 17 is enabled - * @param exti EXTI Instance - * @retval State of bit (1 or 0). - */ -__STATIC_INLINE uint32_t md_exti_is_enable_rts_cmp2(EXTI_TypeDef *exti) -{ - return (READ_BIT(exti->RTS, EXTI_RTS_CMP2_MSK) == (EXTI_RTS_CMP2_MSK)); -} - -/** - * @brief Enable rising trigger event configuration bit of line 20 - * @param exti EXTI Instance - * @retval None - */ -__STATIC_INLINE void md_exti_enable_rts_pvd0(EXTI_TypeDef *exti) -{ - SET_BIT(exti->RTS, EXTI_RTS_PVD0_MSK); -} - -/** - * @brief Disable rising trigger event configuration bit of line 20 - * @param exti EXTI Instance - * @retval None - */ -__STATIC_INLINE void md_exti_disable_rts_pvd0(EXTI_TypeDef *exti) -{ - CLEAR_BIT(exti->RTS, EXTI_RTS_PVD0_MSK); -} - -/** - * @brief Check if rising trigger event configuration bit of line 20 is enabled - * @param exti EXTI Instance - * @retval State of bit (1 or 0). - */ -__STATIC_INLINE uint32_t md_exti_is_enable_rts_pvd0(EXTI_TypeDef *exti) -{ - return (READ_BIT(exti->RTS, EXTI_RTS_PVD0_MSK) == (EXTI_RTS_PVD0_MSK)); -} - -/** - * @brief Enable rising trigger event configuration bit of line 21 - * @param exti EXTI Instance - * @retval None - */ -__STATIC_INLINE void md_exti_enable_rts_wakeup(EXTI_TypeDef *exti) -{ - SET_BIT(exti->RTS, EXTI_RTS_WAKEUP_MSK); -} - -/** - * @brief Disable rising trigger event configuration bit of line 21 - * @param exti EXTI Instance - * @retval None - */ -__STATIC_INLINE void md_exti_disable_rts_wakeup(EXTI_TypeDef *exti) -{ - CLEAR_BIT(exti->RTS, EXTI_RTS_WAKEUP_MSK); -} - -/** - * @brief Check if rising trigger event configuration bit of line 21 is enabled - * @param exti EXTI Instance - * @retval State of bit (1 or 0). - */ -__STATIC_INLINE uint32_t md_exti_is_enable_rts_wakeup(EXTI_TypeDef *exti) -{ - return (READ_BIT(exti->RTS, EXTI_RTS_WAKEUP_MSK) == (EXTI_RTS_WAKEUP_MSK)); -} - -/** - * @} MD_EXTI_PF_RTS - */ - -/** @defgroup MD_EXTI_PF_FTS EXTI Falling Edge Trigger Selection Register - * @{ - */ - -/** - * @brief Set falling trigger event configuration bit of line - * @param exti EXTI Instance - * @param value The value write in EXTI->FTS - * @retval None - */ -__STATIC_INLINE void md_exti_set_fts(EXTI_TypeDef *exti, uint32_t value) -{ - WRITE_REG(exti->FTS, value); -} - -/** - * @brief Get falling trigger event configuration bit of line - * @param exti EXTI Instance - * @retval None - */ -__STATIC_INLINE uint32_t md_exti_get_fts(EXTI_TypeDef *exti) -{ - return (uint32_t)(READ_REG(exti->FTS)); -} - -/** - * @brief Enable falling trigger event configuration bit of line 0 - * @param exti EXTI Instance - * @retval None - */ -__STATIC_INLINE void md_exti_enable_fts_gpio0(EXTI_TypeDef *exti) -{ - SET_BIT(exti->FTS, EXTI_FTS_GPIO0_MSK); -} - -/** - * @brief Disable falling trigger event configuration bit of line 0 - * @param exti EXTI Instance - * @retval None - */ -__STATIC_INLINE void md_exti_disable_fts_gpio0(EXTI_TypeDef *exti) -{ - CLEAR_BIT(exti->FTS, EXTI_FTS_GPIO0_MSK); -} - -/** - * @brief Check if falling trigger event configuration bit of line 0 is enabled - * @param exti EXTI Instance - * @retval State of bit (1 or 0). - */ -__STATIC_INLINE uint32_t md_exti_is_enable_fts_gpio0(EXTI_TypeDef *exti) -{ - return (READ_BIT(exti->FTS, EXTI_FTS_GPIO0_MSK) == (EXTI_FTS_GPIO0_MSK)); -} - -/** - * @brief Enable falling trigger event configuration bit of line 1 - * @param exti EXTI Instance - * @retval None - */ -__STATIC_INLINE void md_exti_enable_fts_gpio1(EXTI_TypeDef *exti) -{ - SET_BIT(exti->FTS, EXTI_FTS_GPIO1_MSK); -} - -/** - * @brief Disable falling trigger event configuration bit of line 1 - * @param exti EXTI Instance - * @retval None - */ -__STATIC_INLINE void md_exti_disable_fts_gpio1(EXTI_TypeDef *exti) -{ - CLEAR_BIT(exti->FTS, EXTI_FTS_GPIO1_MSK); -} - -/** - * @brief Check if falling trigger event configuration bit of line 1 is enabled - * @param exti EXTI Instance - * @retval State of bit (1 or 0). - */ -__STATIC_INLINE uint32_t md_exti_is_enable_fts_gpio1(EXTI_TypeDef *exti) -{ - return (READ_BIT(exti->FTS, EXTI_FTS_GPIO1_MSK) == (EXTI_FTS_GPIO1_MSK)); -} - -/** - * @brief Enable falling trigger event configuration bit of line 2 - * @param exti EXTI Instance - * @retval None - */ -__STATIC_INLINE void md_exti_enable_fts_gpio2(EXTI_TypeDef *exti) -{ - SET_BIT(exti->FTS, EXTI_FTS_GPIO2_MSK); -} - -/** - * @brief Disable falling trigger event configuration bit of line 2 - * @param exti EXTI Instance - * @retval None - */ -__STATIC_INLINE void md_exti_disable_fts_gpio2(EXTI_TypeDef *exti) -{ - CLEAR_BIT(exti->FTS, EXTI_FTS_GPIO2_MSK); -} - -/** - * @brief Check if falling trigger event configuration bit of line 2 is enabled - * @param exti EXTI Instance - * @retval State of bit (1 or 0). - */ -__STATIC_INLINE uint32_t md_exti_is_enable_fts_gpio2(EXTI_TypeDef *exti) -{ - return (READ_BIT(exti->FTS, EXTI_FTS_GPIO2_MSK) == (EXTI_FTS_GPIO2_MSK)); -} - -/** - * @brief Enable falling trigger event configuration bit of line 3 - * @param exti EXTI Instance - * @retval None - */ -__STATIC_INLINE void md_exti_enable_fts_gpio3(EXTI_TypeDef *exti) -{ - SET_BIT(exti->FTS, EXTI_FTS_GPIO3_MSK); -} - -/** - * @brief Disable falling trigger event configuration bit of line 3 - * @param exti EXTI Instance - * @retval None - */ -__STATIC_INLINE void md_exti_disable_fts_gpio3(EXTI_TypeDef *exti) -{ - CLEAR_BIT(exti->FTS, EXTI_FTS_GPIO3_MSK); -} - -/** - * @brief Check if falling trigger event configuration bit of line 3 is enabled - * @param exti EXTI Instance - * @retval State of bit (1 or 0). - */ -__STATIC_INLINE uint32_t md_exti_is_enable_fts_gpio3(EXTI_TypeDef *exti) -{ - return (READ_BIT(exti->FTS, EXTI_FTS_GPIO3_MSK) == (EXTI_FTS_GPIO3_MSK)); -} - -/** - * @brief Enable falling trigger event configuration bit of line 4 - * @param exti EXTI Instance - * @retval None - */ -__STATIC_INLINE void md_exti_enable_fts_gpio4(EXTI_TypeDef *exti) -{ - SET_BIT(exti->FTS, EXTI_FTS_GPIO4_MSK); -} - -/** - * @brief Disable falling trigger event configuration bit of line 4 - * @param exti EXTI Instance - * @retval None - */ -__STATIC_INLINE void md_exti_disable_fts_gpio4(EXTI_TypeDef *exti) -{ - CLEAR_BIT(exti->FTS, EXTI_FTS_GPIO4_MSK); -} - -/** - * @brief Check if falling trigger event configuration bit of line 4 is enabled - * @param exti EXTI Instance - * @retval State of bit (1 or 0). - */ -__STATIC_INLINE uint32_t md_exti_is_enable_fts_gpio4(EXTI_TypeDef *exti) -{ - return (READ_BIT(exti->FTS, EXTI_FTS_GPIO4_MSK) == (EXTI_FTS_GPIO4_MSK)); -} - -/** - * @brief Enable falling trigger event configuration bit of line 5 - * @param exti EXTI Instance - * @retval None - */ -__STATIC_INLINE void md_exti_enable_fts_gpio5(EXTI_TypeDef *exti) -{ - SET_BIT(exti->FTS, EXTI_FTS_GPIO5_MSK); -} - -/** - * @brief Disable falling trigger event configuration bit of line 5 - * @param exti EXTI Instance - * @retval None - */ -__STATIC_INLINE void md_exti_disable_fts_gpio5(EXTI_TypeDef *exti) -{ - CLEAR_BIT(exti->FTS, EXTI_FTS_GPIO5_MSK); -} - -/** - * @brief Check if falling trigger event configuration bit of line 5 is enabled - * @param exti EXTI Instance - * @retval State of bit (1 or 0). - */ -__STATIC_INLINE uint32_t md_exti_is_enable_fts_gpio5(EXTI_TypeDef *exti) -{ - return (READ_BIT(exti->FTS, EXTI_FTS_GPIO5_MSK) == (EXTI_FTS_GPIO5_MSK)); -} - -/** - * @brief Enable falling trigger event configuration bit of line 6 - * @param exti EXTI Instance - * @retval None - */ -__STATIC_INLINE void md_exti_enable_fts_gpio6(EXTI_TypeDef *exti) -{ - SET_BIT(exti->FTS, EXTI_FTS_GPIO6_MSK); -} - -/** - * @brief Disable falling trigger event configuration bit of line 6 - * @param exti EXTI Instance - * @retval None - */ -__STATIC_INLINE void md_exti_disable_fts_gpio6(EXTI_TypeDef *exti) -{ - CLEAR_BIT(exti->FTS, EXTI_FTS_GPIO6_MSK); -} - -/** - * @brief Check if falling trigger event configuration bit of line 6 is enabled - * @param exti EXTI Instance - * @retval State of bit (1 or 0). - */ -__STATIC_INLINE uint32_t md_exti_is_enable_fts_gpio6(EXTI_TypeDef *exti) -{ - return (READ_BIT(exti->FTS, EXTI_FTS_GPIO6_MSK) == (EXTI_FTS_GPIO6_MSK)); -} - -/** - * @brief Enable falling trigger event configuration bit of line 7 - * @param exti EXTI Instance - * @retval None - */ -__STATIC_INLINE void md_exti_enable_fts_gpio7(EXTI_TypeDef *exti) -{ - SET_BIT(exti->FTS, EXTI_FTS_GPIO7_MSK); -} - -/** - * @brief Disable falling trigger event configuration bit of line 7 - * @param exti EXTI Instance - * @retval None - */ -__STATIC_INLINE void md_exti_disable_fts_gpio7(EXTI_TypeDef *exti) -{ - CLEAR_BIT(exti->FTS, EXTI_FTS_GPIO7_MSK); -} - -/** - * @brief Check if falling trigger event configuration bit of line 7 is enabled - * @param exti EXTI Instance - * @retval State of bit (1 or 0). - */ -__STATIC_INLINE uint32_t md_exti_is_enable_fts_gpio7(EXTI_TypeDef *exti) -{ - return (READ_BIT(exti->FTS, EXTI_FTS_GPIO7_MSK) == (EXTI_FTS_GPIO7_MSK)); -} - -/** - * @brief Enable falling trigger event configuration bit of line 8 - * @param exti EXTI Instance - * @retval None - */ -__STATIC_INLINE void md_exti_enable_fts_gpio8(EXTI_TypeDef *exti) -{ - SET_BIT(exti->FTS, EXTI_FTS_GPIO8_MSK); -} - -/** - * @brief Disable falling trigger event configuration bit of line 8 - * @param exti EXTI Instance - * @retval None - */ -__STATIC_INLINE void md_exti_disable_fts_gpio8(EXTI_TypeDef *exti) -{ - CLEAR_BIT(exti->FTS, EXTI_FTS_GPIO8_MSK); -} - -/** - * @brief Check if falling trigger event configuration bit of line 8 is enabled - * @param exti EXTI Instance - * @retval State of bit (1 or 0). - */ -__STATIC_INLINE uint32_t md_exti_is_enable_fts_gpio8(EXTI_TypeDef *exti) -{ - return (READ_BIT(exti->FTS, EXTI_FTS_GPIO8_MSK) == (EXTI_FTS_GPIO8_MSK)); -} - -/** - * @brief Enable falling trigger event configuration bit of line 9 - * @param exti EXTI Instance - * @retval None - */ -__STATIC_INLINE void md_exti_enable_fts_gpio9(EXTI_TypeDef *exti) -{ - SET_BIT(exti->FTS, EXTI_FTS_GPIO9_MSK); -} - -/** - * @brief Disable falling trigger event configuration bit of line 9 - * @param exti EXTI Instance - * @retval None - */ -__STATIC_INLINE void md_exti_disable_fts_gpio9(EXTI_TypeDef *exti) -{ - CLEAR_BIT(exti->FTS, EXTI_FTS_GPIO9_MSK); -} - -/** - * @brief Check if falling trigger event configuration bit of line 9 is enabled - * @param exti EXTI Instance - * @retval State of bit (1 or 0). - */ -__STATIC_INLINE uint32_t md_exti_is_enable_fts_gpio9(EXTI_TypeDef *exti) -{ - return (READ_BIT(exti->FTS, EXTI_FTS_GPIO9_MSK) == (EXTI_FTS_GPIO9_MSK)); -} - -/** - * @brief Enable falling trigger event configuration bit of line 10 - * @param exti EXTI Instance - * @retval None - */ -__STATIC_INLINE void md_exti_enable_fts_gpio10(EXTI_TypeDef *exti) -{ - SET_BIT(exti->FTS, EXTI_FTS_GPIO10_MSK); -} - -/** - * @brief Disable falling trigger event configuration bit of line 10 - * @param exti EXTI Instance - * @retval None - */ -__STATIC_INLINE void md_exti_disable_fts_gpio10(EXTI_TypeDef *exti) -{ - CLEAR_BIT(exti->FTS, EXTI_FTS_GPIO10_MSK); -} - -/** - * @brief Check if falling trigger event configuration bit of line 10 is enabled - * @param exti EXTI Instance - * @retval State of bit (1 or 0). - */ -__STATIC_INLINE uint32_t md_exti_is_enable_fts_gpio10(EXTI_TypeDef *exti) -{ - return (READ_BIT(exti->FTS, EXTI_FTS_GPIO10_MSK) == (EXTI_FTS_GPIO10_MSK)); -} - -/** - * @brief Enable falling trigger event configuration bit of line 11 - * @param exti EXTI Instance - * @retval None - */ -__STATIC_INLINE void md_exti_enable_fts_gpio11(EXTI_TypeDef *exti) -{ - SET_BIT(exti->FTS, EXTI_FTS_GPIO11_MSK); -} - -/** - * @brief Disable falling trigger event configuration bit of line 11 - * @param exti EXTI Instance - * @retval None - */ -__STATIC_INLINE void md_exti_disable_fts_gpio11(EXTI_TypeDef *exti) -{ - CLEAR_BIT(exti->FTS, EXTI_FTS_GPIO11_MSK); -} - -/** - * @brief Check if falling trigger event configuration bit of line 11 is enabled - * @param exti EXTI Instance - * @retval State of bit (1 or 0). - */ -__STATIC_INLINE uint32_t md_exti_is_enable_fts_gpio11(EXTI_TypeDef *exti) -{ - return (READ_BIT(exti->FTS, EXTI_FTS_GPIO11_MSK) == (EXTI_FTS_GPIO11_MSK)); -} - -/** - * @brief Enable falling trigger event configuration bit of line 12 - * @param exti EXTI Instance - * @retval None - */ -__STATIC_INLINE void md_exti_enable_fts_gpio12(EXTI_TypeDef *exti) -{ - SET_BIT(exti->FTS, EXTI_FTS_GPIO12_MSK); -} - -/** - * @brief Disable falling trigger event configuration bit of line 12 - * @param exti EXTI Instance - * @retval None - */ -__STATIC_INLINE void md_exti_disable_fts_gpio12(EXTI_TypeDef *exti) -{ - CLEAR_BIT(exti->FTS, EXTI_FTS_GPIO12_MSK); -} - -/** - * @brief Check if falling trigger event configuration bit of line 12 is enabled - * @param exti EXTI Instance - * @retval State of bit (1 or 0). - */ -__STATIC_INLINE uint32_t md_exti_is_enable_fts_gpio12(EXTI_TypeDef *exti) -{ - return (READ_BIT(exti->FTS, EXTI_FTS_GPIO12_MSK) == (EXTI_FTS_GPIO12_MSK)); -} - -/** - * @brief Enable falling trigger event configuration bit of line 13 - * @param exti EXTI Instance - * @retval None - */ -__STATIC_INLINE void md_exti_enable_fts_gpio13(EXTI_TypeDef *exti) -{ - SET_BIT(exti->FTS, EXTI_FTS_GPIO13_MSK); -} - -/** - * @brief Disable falling trigger event configuration bit of line 13 - * @param exti EXTI Instance - * @retval None - */ -__STATIC_INLINE void md_exti_disable_fts_gpio13(EXTI_TypeDef *exti) -{ - CLEAR_BIT(exti->FTS, EXTI_FTS_GPIO13_MSK); -} - -/** - * @brief Check if falling trigger event configuration bit of line 13 is enabled - * @param exti EXTI Instance - * @retval State of bit (1 or 0). - */ -__STATIC_INLINE uint32_t md_exti_is_enable_fts_gpio13(EXTI_TypeDef *exti) -{ - return (READ_BIT(exti->FTS, EXTI_FTS_GPIO13_MSK) == (EXTI_FTS_GPIO13_MSK)); -} - -/** - * @brief Enable falling trigger event configuration bit of line 14 - * @param exti EXTI Instance - * @retval None - */ -__STATIC_INLINE void md_exti_enable_fts_gpio14(EXTI_TypeDef *exti) -{ - SET_BIT(exti->FTS, EXTI_FTS_GPIO14_MSK); -} - -/** - * @brief Disable falling trigger event configuration bit of line 14 - * @param exti EXTI Instance - * @retval None - */ -__STATIC_INLINE void md_exti_disable_fts_gpio14(EXTI_TypeDef *exti) -{ - CLEAR_BIT(exti->FTS, EXTI_FTS_GPIO14_MSK); -} - -/** - * @brief Check if falling trigger event configuration bit of line 14 is enabled - * @param exti EXTI Instance - * @retval State of bit (1 or 0). - */ -__STATIC_INLINE uint32_t md_exti_is_enable_fts_gpio14(EXTI_TypeDef *exti) -{ - return (READ_BIT(exti->FTS, EXTI_FTS_GPIO14_MSK) == (EXTI_FTS_GPIO14_MSK)); -} - -/** - * @brief Enable falling trigger event configuration bit of line 15 - * @param exti EXTI Instance - * @retval None - */ -__STATIC_INLINE void md_exti_enable_fts_gpio15(EXTI_TypeDef *exti) -{ - SET_BIT(exti->FTS, EXTI_FTS_GPIO15_MSK); -} - -/** - * @brief Disable falling trigger event configuration bit of line 15 - * @param exti EXTI Instance - * @retval None - */ -__STATIC_INLINE void md_exti_disable_fts_gpio15(EXTI_TypeDef *exti) -{ - CLEAR_BIT(exti->FTS, EXTI_FTS_GPIO15_MSK); -} - -/** - * @brief Check if falling trigger event configuration bit of line 15 is enabled - * @param exti EXTI Instance - * @retval State of bit (1 or 0). - */ -__STATIC_INLINE uint32_t md_exti_is_enable_fts_gpio15(EXTI_TypeDef *exti) -{ - return (READ_BIT(exti->FTS, EXTI_FTS_GPIO15_MSK) == (EXTI_FTS_GPIO15_MSK)); -} - - - -/** - * @brief Enable falling trigger event configuration bit of line 16 - * @param exti EXTI Instance - * @retval None - */ -__STATIC_INLINE void md_exti_enable_fts_cmp1(EXTI_TypeDef *exti) -{ - SET_BIT(exti->FTS, EXTI_FTS_CMP1_MSK); -} - -/** - * @brief Disable falling trigger event configuration bit of line 16 - * @param exti EXTI Instance - * @retval None - */ -__STATIC_INLINE void md_exti_disable_fts_cmp1(EXTI_TypeDef *exti) -{ - CLEAR_BIT(exti->FTS, EXTI_FTS_CMP1_MSK); -} - -/** - * @brief Check if falling trigger event configuration bit of line 16 is enabled - * @param exti EXTI Instance - * @retval State of bit (1 or 0). - */ -__STATIC_INLINE uint32_t md_exti_is_enable_fts_cmp1(EXTI_TypeDef *exti) -{ - return (READ_BIT(exti->FTS, EXTI_FTS_CMP1_MSK) == (EXTI_FTS_CMP1_MSK)); -} - -/** - * @brief Enable falling trigger event configuration bit of line 1 - * @param exti EXTI Instance - * @retval None - */ -__STATIC_INLINE void md_exti_enable_fts_cmp2(EXTI_TypeDef *exti) -{ - SET_BIT(exti->FTS, EXTI_FTS_CMP2_MSK); -} - -/** - * @brief Disable falling trigger event configuration bit of line 18 - * @param exti EXTI Instance - * @retval None - */ -__STATIC_INLINE void md_exti_disable_fts_cmp2(EXTI_TypeDef *exti) -{ - CLEAR_BIT(exti->FTS, EXTI_FTS_CMP2_MSK); -} - -/** - * @brief Check if falling trigger event configuration bit of line 18 is enabled - * @param exti EXTI Instance - * @retval State of bit (1 or 0). - */ -__STATIC_INLINE uint32_t md_exti_is_enable_fts_cmp2(EXTI_TypeDef *exti) -{ - return (READ_BIT(exti->FTS, EXTI_FTS_CMP2_MSK) == (EXTI_RTS_CMP2_MSK)); -} - - -/** - * @brief Enable falling trigger event configuration bit of line 17 - * @param exti EXTI Instance - * @retval None - */ -__STATIC_INLINE void md_exti_enable_fts_pvd0(EXTI_TypeDef *exti) -{ - SET_BIT(exti->FTS, EXTI_FTS_PVD0_MSK); -} - -/** - * @brief Disable falling trigger event configuration bit of line 17 - * @param exti EXTI Instance - * @retval None - */ -__STATIC_INLINE void md_exti_disable_fts_pvd0(EXTI_TypeDef *exti) -{ - CLEAR_BIT(exti->FTS, EXTI_FTS_PVD0_MSK); -} - -/** - * @brief Check if falling trigger event configuration bit of line 17 is enabled - * @param exti EXTI Instance - * @retval State of bit (1 or 0). - */ -__STATIC_INLINE uint32_t md_exti_is_enable_fts_pvd0(EXTI_TypeDef *exti) -{ - return (READ_BIT(exti->FTS, EXTI_FTS_PVD0_MSK) == (EXTI_FTS_PVD0_MSK)); -} - -/** - * @brief Enable falling trigger event configuration bit of line 21 - * @param exti EXTI Instance - * @retval None - */ -__STATIC_INLINE void md_exti_enable_fts_wakeup(EXTI_TypeDef *exti) -{ - SET_BIT(exti->FTS, EXTI_FTS_WAKEUP_MSK); -} - -/** - * @brief Disable falling trigger event configuration bit of line 21 - * @param exti EXTI Instance - * @retval None - */ -__STATIC_INLINE void md_exti_disable_fts_wakeup(EXTI_TypeDef *exti) -{ - CLEAR_BIT(exti->FTS, EXTI_FTS_WAKEUP_MSK); -} - -/** - * @brief Check if falling trigger event configuration bit of line 21 is enabled - * @param exti EXTI Instance - * @retval State of bit (1 or 0). - */ -__STATIC_INLINE uint32_t md_exti_is_enable_fts_wakeup(EXTI_TypeDef *exti) -{ - return (READ_BIT(exti->FTS, EXTI_FTS_WAKEUP_MSK) == (EXTI_FTS_WAKEUP_MSK)); -} - - - -/** - * @} MD_EXTI_PF_FTS - */ - -/** @defgroup MD_EXTI_PF_SWI EXTI Software Interrupt Event register - * @{ - */ - -/** - * @brief Set software interrupt on line - * @param exti EXTI Instance - * @param value The value write in EXTI->SWI - * @retval None - */ -__STATIC_INLINE void md_exti_set_swi(EXTI_TypeDef *exti, uint32_t value) -{ - WRITE_REG(exti->SWI, value); -} - -/** - * @brief Get software interrupt on line - * @param exti EXTI Instance - * @retval None - */ -__STATIC_INLINE uint32_t md_exti_get_swi(EXTI_TypeDef *exti) -{ - return (uint32_t)(READ_REG(exti->SWI)); -} - -/** - * @brief Enable falling trigger event configuration bit of line 0 - * @param exti EXTI Instance - * @retval None - */ -__STATIC_INLINE void md_exti_enable_swi_gpio0(EXTI_TypeDef *exti) -{ - SET_BIT(exti->SWI, EXTI_SWI_GPIO0_MSK); -} - -/** - * @brief Disable software interrupt on line 0 - * @param exti EXTI Instance - * @retval None - */ -__STATIC_INLINE void md_exti_disable_swi_gpio0(EXTI_TypeDef *exti) -{ - CLEAR_BIT(exti->SWI, EXTI_SWI_GPIO0_MSK); -} - -/** - * @brief Check if software interrupt on line 0 is enabled - * @param exti EXTI Instance - * @retval State of bit (1 or 0). - */ -__STATIC_INLINE uint32_t md_exti_is_enable_swi_gpio0(EXTI_TypeDef *exti) -{ - return (READ_BIT(exti->SWI, EXTI_SWI_GPIO0_MSK) == (EXTI_SWI_GPIO0_MSK)); -} - -/** - * @brief Enable software interrupt on line 1 - * @param exti EXTI Instance - * @retval None - */ -__STATIC_INLINE void md_exti_enable_swi_gpio1(EXTI_TypeDef *exti) -{ - SET_BIT(exti->SWI, EXTI_SWI_GPIO1_MSK); -} - -/** - * @brief Disable software interrupt on line 1 - * @param exti EXTI Instance - * @retval None - */ -__STATIC_INLINE void md_exti_disable_swi_gpio1(EXTI_TypeDef *exti) -{ - CLEAR_BIT(exti->SWI, EXTI_SWI_GPIO1_MSK); -} - -/** - * @brief Check if software interrupt on line 1 is enabled - * @param exti EXTI Instance - * @retval State of bit (1 or 0). - */ -__STATIC_INLINE uint32_t md_exti_is_enable_swi_gpio1(EXTI_TypeDef *exti) -{ - return (READ_BIT(exti->SWI, EXTI_SWI_GPIO1_MSK) == (EXTI_SWI_GPIO1_MSK)); -} - -/** - * @brief Enable software interrupt on line 2 - * @param exti EXTI Instance - * @retval None - */ -__STATIC_INLINE void md_exti_enable_swi_gpio2(EXTI_TypeDef *exti) -{ - SET_BIT(exti->SWI, EXTI_SWI_GPIO2_MSK); -} - -/** - * @brief Disable software interrupt on line 2 - * @param exti EXTI Instance - * @retval None - */ -__STATIC_INLINE void md_exti_disable_swi_gpio2(EXTI_TypeDef *exti) -{ - CLEAR_BIT(exti->SWI, EXTI_SWI_GPIO2_MSK); -} - -/** - * @brief Check if software interrupt on line 2 is enabled - * @param exti EXTI Instance - * @retval State of bit (1 or 0). - */ -__STATIC_INLINE uint32_t md_exti_is_enable_swi_gpio2(EXTI_TypeDef *exti) -{ - return (READ_BIT(exti->SWI, EXTI_SWI_GPIO2_MSK) == (EXTI_SWI_GPIO2_MSK)); -} - -/** - * @brief Enable software interrupt on line 3 - * @param exti EXTI Instance - * @retval None - */ -__STATIC_INLINE void md_exti_enable_swi_gpio3(EXTI_TypeDef *exti) -{ - SET_BIT(exti->SWI, EXTI_SWI_GPIO3_MSK); -} - -/** - * @brief Disable software interrupt on line 3 - * @param exti EXTI Instance - * @retval None - */ -__STATIC_INLINE void md_exti_disable_swi_gpio3(EXTI_TypeDef *exti) -{ - CLEAR_BIT(exti->SWI, EXTI_SWI_GPIO3_MSK); -} - -/** - * @brief Check if software interrupt on line 3 is enabled - * @param exti EXTI Instance - * @retval State of bit (1 or 0). - */ -__STATIC_INLINE uint32_t md_exti_is_enable_swi_gpio3(EXTI_TypeDef *exti) -{ - return (READ_BIT(exti->SWI, EXTI_SWI_GPIO3_MSK) == (EXTI_SWI_GPIO3_MSK)); -} - -/** - * @brief Enable software interrupt on line 4 - * @param exti EXTI Instance - * @retval None - */ -__STATIC_INLINE void md_exti_enable_swi_gpio4(EXTI_TypeDef *exti) -{ - SET_BIT(exti->SWI, EXTI_SWI_GPIO4_MSK); -} - -/** - * @brief Disable falling trigger event configuration bit of line 4 - * @param exti EXTI Instance - * @retval None - */ -__STATIC_INLINE void md_exti_disable_swi_gpio4(EXTI_TypeDef *exti) -{ - CLEAR_BIT(exti->SWI, EXTI_SWI_GPIO4_MSK); -} - -/** - * @brief Check if software interrupt on line 4 is enabled - * @param exti EXTI Instance - * @retval State of bit (1 or 0). - */ -__STATIC_INLINE uint32_t md_exti_is_enable_swi_gpio4(EXTI_TypeDef *exti) -{ - return (READ_BIT(exti->SWI, EXTI_SWI_GPIO4_MSK) == (EXTI_SWI_GPIO4_MSK)); -} - -/** - * @brief Enable software interrupt on line 5 - * @param exti EXTI Instance - * @retval None - */ -__STATIC_INLINE void md_exti_enable_swi_gpio5(EXTI_TypeDef *exti) -{ - SET_BIT(exti->SWI, EXTI_SWI_GPIO5_MSK); -} - -/** - * @brief Disable software interrupt on line 5 - * @param exti EXTI Instance - * @retval None - */ -__STATIC_INLINE void md_exti_disable_swi_gpio5(EXTI_TypeDef *exti) -{ - CLEAR_BIT(exti->SWI, EXTI_SWI_GPIO5_MSK); -} - -/** - * @brief Check if software interrupt on line 5 is enabled - * @param exti EXTI Instance - * @retval State of bit (1 or 0). - */ -__STATIC_INLINE uint32_t md_exti_is_enable_swi_gpio5(EXTI_TypeDef *exti) -{ - return (READ_BIT(exti->SWI, EXTI_SWI_GPIO5_MSK) == (EXTI_SWI_GPIO5_MSK)); -} - -/** - * @brief Enable software interrupt on line 6 - * @param exti EXTI Instance - * @retval None - */ -__STATIC_INLINE void md_exti_enable_swi_gpio6(EXTI_TypeDef *exti) -{ - SET_BIT(exti->SWI, EXTI_SWI_GPIO6_MSK); -} - -/** - * @brief Disable software interrupt on line 6 - * @param exti EXTI Instance - * @retval None - */ -__STATIC_INLINE void md_exti_disable_swi_gpio6(EXTI_TypeDef *exti) -{ - CLEAR_BIT(exti->SWI, EXTI_SWI_GPIO6_MSK); -} - -/** - * @brief Check if software interrupt on line 6 is enabled - * @param exti EXTI Instance - * @retval State of bit (1 or 0). - */ -__STATIC_INLINE uint32_t md_exti_is_enable_swi_gpio6(EXTI_TypeDef *exti) -{ - return (READ_BIT(exti->SWI, EXTI_SWI_GPIO6_MSK) == (EXTI_SWI_GPIO6_MSK)); -} - -/** - * @brief Enable software interrupt on line 7 - * @param exti EXTI Instance - * @retval None - */ -__STATIC_INLINE void md_exti_enable_swi_gpio7(EXTI_TypeDef *exti) -{ - SET_BIT(exti->SWI, EXTI_SWI_GPIO7_MSK); -} - -/** - * @brief Disable software interrupt on line 7 - * @param exti EXTI Instance - * @retval None - */ -__STATIC_INLINE void md_exti_disable_swi_gpio7(EXTI_TypeDef *exti) -{ - CLEAR_BIT(exti->SWI, EXTI_SWI_GPIO7_MSK); -} - -/** - * @brief Check if software interrupt on line 7 is enabled - * @param exti EXTI Instance - * @retval State of bit (1 or 0). - */ -__STATIC_INLINE uint32_t md_exti_is_enable_swi_gpio7(EXTI_TypeDef *exti) -{ - return (READ_BIT(exti->SWI, EXTI_SWI_GPIO7_MSK) == (EXTI_SWI_GPIO7_MSK)); -} - -/** - * @brief Enable software interrupt on line 8 - * @param exti EXTI Instance - * @retval None - */ -__STATIC_INLINE void md_exti_enable_swi_gpio8(EXTI_TypeDef *exti) -{ - SET_BIT(exti->SWI, EXTI_SWI_GPIO8_MSK); -} - -/** - * @brief Disable software interrupt on line 8 - * @param exti EXTI Instance - * @retval None - */ -__STATIC_INLINE void md_exti_disable_swi_gpio8(EXTI_TypeDef *exti) -{ - CLEAR_BIT(exti->SWI, EXTI_SWI_GPIO8_MSK); -} - -/** - * @brief Check if software interrupt on line 8 is enabled - * @param exti EXTI Instance - * @retval State of bit (1 or 0). - */ -__STATIC_INLINE uint32_t md_exti_is_enable_swi_gpio8(EXTI_TypeDef *exti) -{ - return (READ_BIT(exti->SWI, EXTI_SWI_GPIO8_MSK) == (EXTI_SWI_GPIO8_MSK)); -} - -/** - * @brief Enable software interrupt on line 9 - * @param exti EXTI Instance - * @retval None - */ -__STATIC_INLINE void md_exti_enable_swi_gpio9(EXTI_TypeDef *exti) -{ - SET_BIT(exti->SWI, EXTI_SWI_GPIO9_MSK); -} - -/** - * @brief Disable software interrupt on line 9 - * @param exti EXTI Instance - * @retval None - */ -__STATIC_INLINE void md_exti_disable_swi_gpio9(EXTI_TypeDef *exti) -{ - CLEAR_BIT(exti->SWI, EXTI_SWI_GPIO9_MSK); -} - -/** - * @brief Check if software interrupt on line 9 is enabled - * @param exti EXTI Instance - * @retval State of bit (1 or 0). - */ -__STATIC_INLINE uint32_t md_exti_is_enable_swi_gpio9(EXTI_TypeDef *exti) -{ - return (READ_BIT(exti->SWI, EXTI_SWI_GPIO9_MSK) == (EXTI_SWI_GPIO9_MSK)); -} - -/** - * @brief Enable software interrupt on line 10 - * @param exti EXTI Instance - * @retval None - */ -__STATIC_INLINE void md_exti_enable_swi_gpio10(EXTI_TypeDef *exti) -{ - SET_BIT(exti->SWI, EXTI_SWI_GPIO10_MSK); -} - -/** - * @brief Disable software interrupt on line 10 - * @param exti EXTI Instance - * @retval None - */ -__STATIC_INLINE void md_exti_disable_swi_gpio10(EXTI_TypeDef *exti) -{ - CLEAR_BIT(exti->SWI, EXTI_SWI_GPIO10_MSK); -} - -/** - * @brief Check if software interrupt on line 10 is enabled - * @param exti EXTI Instance - * @retval State of bit (1 or 0). - */ -__STATIC_INLINE uint32_t md_exti_is_enable_swi_gpio10(EXTI_TypeDef *exti) -{ - return (READ_BIT(exti->SWI, EXTI_SWI_GPIO10_MSK) == (EXTI_SWI_GPIO10_MSK)); -} - -/** - * @brief Enable software interrupt on line 11 - * @param exti EXTI Instance - * @retval None - */ -__STATIC_INLINE void md_exti_enable_swi_gpio11(EXTI_TypeDef *exti) -{ - SET_BIT(exti->SWI, EXTI_SWI_GPIO11_MSK); -} - -/** - * @brief Disable falling trigger event configuration bit of line 11 - * @param exti EXTI Instance - * @retval None - */ -__STATIC_INLINE void md_exti_disable_swi_gpio11(EXTI_TypeDef *exti) -{ - CLEAR_BIT(exti->FTS, EXTI_FTS_GPIO11_MSK); -} - -/** - * @brief Check if software interrupt on line 11 is enabled - * @param exti EXTI Instance - * @retval State of bit (1 or 0). - */ -__STATIC_INLINE uint32_t md_exti_is_enable_swi_gpio11(EXTI_TypeDef *exti) -{ - return (READ_BIT(exti->SWI, EXTI_SWI_GPIO11_MSK) == (EXTI_SWI_GPIO11_MSK)); -} - -/** - * @brief Enable software interrupt on line 12 - * @param exti EXTI Instance - * @retval None - */ -__STATIC_INLINE void md_exti_enable_swi_gpio12(EXTI_TypeDef *exti) -{ - SET_BIT(exti->SWI, EXTI_SWI_GPIO12_MSK); -} - -/** - * @brief Disable software interrupt on line 12 - * @param exti EXTI Instance - * @retval None - */ -__STATIC_INLINE void md_exti_disable_swi_gpio12(EXTI_TypeDef *exti) -{ - CLEAR_BIT(exti->SWI, EXTI_SWI_GPIO12_MSK); -} - -/** - * @brief Check if software interrupt on line 12 is enabled - * @param exti EXTI Instance - * @retval State of bit (1 or 0). - */ -__STATIC_INLINE uint32_t md_exti_is_enable_swi_gpio12(EXTI_TypeDef *exti) -{ - return (READ_BIT(exti->SWI, EXTI_SWI_GPIO12_MSK) == (EXTI_SWI_GPIO12_MSK)); -} - -/** - * @brief Enable software interrupt on line 13 - * @param exti EXTI Instance - * @retval None - */ -__STATIC_INLINE void md_exti_enable_swi_gpio13(EXTI_TypeDef *exti) -{ - SET_BIT(exti->SWI, EXTI_SWI_GPIO13_MSK); -} - -/** - * @brief Disable software interrupt on line 13 - * @param exti EXTI Instance - * @retval None - */ -__STATIC_INLINE void md_exti_disable_swi_gpio13(EXTI_TypeDef *exti) -{ - CLEAR_BIT(exti->SWI, EXTI_SWI_GPIO13_MSK); -} - -/** - * @brief Check if software interrupt on line 13 is enabled - * @param exti EXTI Instance - * @retval State of bit (1 or 0). - */ -__STATIC_INLINE uint32_t md_exti_is_enable_swi_gpio13(EXTI_TypeDef *exti) -{ - return (READ_BIT(exti->SWI, EXTI_SWI_GPIO13_MSK) == (EXTI_SWI_GPIO13_MSK)); -} - -/** - * @brief Enable software interrupt on line 14 - * @param exti EXTI Instance - * @retval None - */ -__STATIC_INLINE void md_exti_enable_swi_gpio14(EXTI_TypeDef *exti) -{ - SET_BIT(exti->SWI, EXTI_SWI_GPIO14_MSK); -} - -/** - * @brief Disable software interrupt on line 14 - * @param exti EXTI Instance - * @retval None - */ -__STATIC_INLINE void md_exti_disable_swi_gpio14(EXTI_TypeDef *exti) -{ - CLEAR_BIT(exti->SWI, EXTI_SWI_GPIO14_MSK); -} - -/** - * @brief Check if software interrupt on line 14 is enabled - * @param exti EXTI Instance - * @retval State of bit (1 or 0). - */ -__STATIC_INLINE uint32_t md_exti_is_enable_swi_gpio14(EXTI_TypeDef *exti) -{ - return (READ_BIT(exti->SWI, EXTI_SWI_GPIO14_MSK) == (EXTI_SWI_GPIO14_MSK)); -} - -/** - * @brief Enable software interrupt on line 15 - * @param exti EXTI Instance - * @retval None - */ -__STATIC_INLINE void md_exti_enable_swi_gpio15(EXTI_TypeDef *exti) -{ - SET_BIT(exti->SWI, EXTI_SWI_GPIO15_MSK); -} - -/** - * @brief Disable software interrupt on line 15 - * @param exti EXTI Instance - * @retval None - */ -__STATIC_INLINE void md_exti_disable_swi_gpio15(EXTI_TypeDef *exti) -{ - CLEAR_BIT(exti->SWI, EXTI_SWI_GPIO15_MSK); -} - -/** - * @brief Check if software interrupt on line is enabled - * @param exti EXTI Instance - * @retval State of bit (1 or 0). - */ -__STATIC_INLINE uint32_t md_exti_is_enable_swi_gpio15(EXTI_TypeDef *exti) -{ - return (READ_BIT(exti->SWI, EXTI_SWI_GPIO15_MSK) == (EXTI_SWI_GPIO15_MSK)); -} - -/** - * @brief Enable software interrupt on line 16 - * @param exti EXTI Instance - * @retval None - */ -__STATIC_INLINE void md_exti_enable_swi_cmp1(EXTI_TypeDef *exti) -{ - SET_BIT(exti->SWI, EXTI_SWI_CMP1_MSK); -} - -/** - * @brief Disable software interrupt on line 16 - * @param exti EXTI Instance - * @retval None - */ -__STATIC_INLINE void md_exti_disable_swi_cmp1(EXTI_TypeDef *exti) -{ - CLEAR_BIT(exti->SWI, EXTI_SWI_CMP1_MSK); -} - -/** - * @brief Check if software interrupt on line 16 is enabled - * @param exti EXTI Instance - * @retval State of bit (1 or 0). - */ -__STATIC_INLINE uint32_t md_exti_is_enable_swi_cmp1(EXTI_TypeDef *exti) -{ - return (READ_BIT(exti->SWI, EXTI_SWI_CMP1_MSK) == (EXTI_SWI_CMP1_MSK)); -} - -/** - * @brief Enable software interrupt on line 17 - * @param exti EXTI Instance - * @retval None - */ -__STATIC_INLINE void md_exti_enable_swi_cmp2(EXTI_TypeDef *exti) -{ - SET_BIT(exti->SWI, EXTI_SWI_CMP2_MSK); -} - -/** - * @brief Disable software interrupt on line 17 - * @param exti EXTI Instance - * @retval None - */ -__STATIC_INLINE void md_exti_disable_swi_cmp2(EXTI_TypeDef *exti) -{ - CLEAR_BIT(exti->SWI, EXTI_SWI_CMP2_MSK); -} - -/** - * @brief Check if software interrupt on line 17 is enabled - * @param exti EXTI Instance - * @retval State of bit (1 or 0). - */ -__STATIC_INLINE uint32_t md_exti_is_enable_swi_cmp2(EXTI_TypeDef *exti) -{ - return (READ_BIT(exti->SWI, EXTI_SWI_CMP2_MSK) == (EXTI_SWI_CMP2_MSK)); -} - - -/** - * @brief Enable software interrupt on line 20 - * @param exti EXTI Instance - * @retval None - */ -__STATIC_INLINE void md_exti_enable_swi_pvd0(EXTI_TypeDef *exti) -{ - SET_BIT(exti->SWI, EXTI_SWI_PVD0_MSK); -} - -/** - * @brief Disable software interrupt on line 20 - * @param exti EXTI Instance - * @retval None - */ -__STATIC_INLINE void md_exti_disable_swi_pvd0(EXTI_TypeDef *exti) -{ - CLEAR_BIT(exti->SWI, EXTI_SWI_PVD0_MSK); -} - -/** - * @brief Check if software interrupt on line 20 is enabled - * @param exti EXTI Instance - * @retval State of bit (1 or 0). - */ -__STATIC_INLINE uint32_t md_exti_is_enable_swi_pvd0(EXTI_TypeDef *exti) -{ - return (READ_BIT(exti->SWI, EXTI_SWI_PVD0_MSK) == (EXTI_SWI_PVD0_MSK)); -} - -/** - * @brief Enable software interrupt on line 21 - * @param exti EXTI Instance - * @retval None - */ -__STATIC_INLINE void md_exti_enable_swi_wakeup(EXTI_TypeDef *exti) -{ - SET_BIT(exti->SWI, EXTI_SWI_WAKEUP_MSK); -} - -/** - * @brief Disable software interrupt on line 21 - * @param exti EXTI Instance - * @retval None - */ -__STATIC_INLINE void md_exti_disable_swi_wakeup(EXTI_TypeDef *exti) -{ - CLEAR_BIT(exti->SWI, EXTI_SWI_WAKEUP_MSK); -} - -/** - * @brief Check if software interrupt on line 21 is enabled - * @param exti EXTI Instance - * @retval State of bit (1 or 0). - */ -__STATIC_INLINE uint32_t md_exti_is_enable_swi_wakeup(EXTI_TypeDef *exti) -{ - return (READ_BIT(exti->SWI, EXTI_SWI_WAKEUP_MSK) == (EXTI_SWI_WAKEUP_MSK)); -} - -/** - * @} MD_EXTI_PF_SWI - */ - - -/** @defgroup MD_EXTI_PF_ADTE EXTI ADC Trigger Enable Register - * @{ - */ -/** - * @brief Set ADC trigger enable on line - * @param exti EXTI Instance - * @param value The value write in EXTI->ADTE - * @retval None - */ -__STATIC_INLINE void md_exti_set_adte(EXTI_TypeDef *exti, uint32_t value) -{ - WRITE_REG(exti->ADTE, value); -} - -/** - * @brief Get ADC trigger enable on line - * @param exti EXTI Instance - * @retval None - */ -__STATIC_INLINE uint32_t md_exti_get_adte(EXTI_TypeDef *exti) -{ - return (uint32_t)(READ_REG(exti->ADTE)); -} - -/** - * @brief Enable ADC trigger on line 0 - * @param exti EXTI Instance - * @retval None - */ -__STATIC_INLINE void md_exti_enable_adte_gpio0(EXTI_TypeDef *exti) -{ - SET_BIT(exti->ADTE, EXTI_ADTE_GPIO0_MSK); -} - -/** - * @brief Disable ADC trigger on line 0 - * @param exti EXTI Instance - * @retval None - */ -__STATIC_INLINE void md_exti_disable_adte_gpio0(EXTI_TypeDef *exti) -{ - CLEAR_BIT(exti->ADTE, EXTI_ADTE_GPIO0_MSK); -} - -/** - * @brief Check if ADC trigger on line 0 is enabled - * @param exti EXTI Instance - * @retval State of bit (1 or 0). - */ -__STATIC_INLINE uint32_t md_exti_is_enable_adte_gpio0(EXTI_TypeDef *exti) -{ - return (READ_BIT(exti->ADTE, EXTI_ADTE_GPIO0_MSK) == (EXTI_ADTE_GPIO0_MSK)); -} - -/** - * @brief Enable ADC trigger on line 1 - * @param exti EXTI Instance - * @retval None - */ -__STATIC_INLINE void md_exti_enable_adte_gpio1(EXTI_TypeDef *exti) -{ - SET_BIT(exti->ADTE, EXTI_ADTE_GPIO1_MSK); -} - -/** - * @brief Disable ADC trigger on line 1 - * @param exti EXTI Instance - * @retval None - */ -__STATIC_INLINE void md_exti_disable_adte_gpio1(EXTI_TypeDef *exti) -{ - CLEAR_BIT(exti->ADTE, EXTI_ADTE_GPIO1_MSK); -} - -/** - * @brief Check if ADC trigger on line 1 is enabled - * @param exti EXTI Instance - * @retval State of bit (1 or 0). - */ -__STATIC_INLINE uint32_t md_exti_is_enable_adte_gpio1(EXTI_TypeDef *exti) -{ - return (READ_BIT(exti->ADTE, EXTI_ADTE_GPIO1_MSK) == (EXTI_ADTE_GPIO1_MSK)); -} - -/** - * @brief Enable ADC trigger on line 2 - * @param exti EXTI Instance - * @retval None - */ -__STATIC_INLINE void md_exti_enable_adte_gpio2(EXTI_TypeDef *exti) -{ - SET_BIT(exti->ADTE, EXTI_ADTE_GPIO2_MSK); -} - -/** - * @brief Disable ADC trigger on line 2 - * @param exti EXTI Instance - * @retval None - */ -__STATIC_INLINE void md_exti_disable_adte_gpio2(EXTI_TypeDef *exti) -{ - CLEAR_BIT(exti->ADTE, EXTI_ADTE_GPIO2_MSK); -} - -/** - * @brief Check if ADC trigger on line 2 is enabled - * @param exti EXTI Instance - * @retval State of bit (1 or 0). - */ -__STATIC_INLINE uint32_t md_exti_is_enable_adte_gpio2(EXTI_TypeDef *exti) -{ - return (READ_BIT(exti->ADTE, EXTI_ADTE_GPIO2_MSK) == (EXTI_ADTE_GPIO2_MSK)); -} - -/** - * @brief Enable ADC trigger on line 3 - * @param exti EXTI Instance - * @retval None - */ -__STATIC_INLINE void md_exti_enable_adte_gpio3(EXTI_TypeDef *exti) -{ - SET_BIT(exti->ADTE, EXTI_ADTE_GPIO3_MSK); -} - -/** - * @brief Disable ADC trigger on line 3 - * @param exti EXTI Instance - * @retval None - */ -__STATIC_INLINE void md_exti_disable_adte_gpio3(EXTI_TypeDef *exti) -{ - CLEAR_BIT(exti->ADTE, EXTI_ADTE_GPIO3_MSK); -} - -/** - * @brief Check if ADC trigger on line 3 is enabled - * @param exti EXTI Instance - * @retval State of bit (1 or 0). - */ -__STATIC_INLINE uint32_t md_exti_is_enable_adte_gpio3(EXTI_TypeDef *exti) -{ - return (READ_BIT(exti->ADTE, EXTI_ADTE_GPIO3_MSK) == (EXTI_ADTE_GPIO3_MSK)); -} - -/** - * @brief Enable ADC trigger on line 4 - * @param exti EXTI Instance - * @retval None - */ -__STATIC_INLINE void md_exti_enable_adte_gpio4(EXTI_TypeDef *exti) -{ - SET_BIT(exti->ADTE, EXTI_ADTE_GPIO4_MSK); -} - -/** - * @brief Disable ADC trigger on line 4 - * @param exti EXTI Instance - * @retval None - */ -__STATIC_INLINE void md_exti_disable_adte_gpio4(EXTI_TypeDef *exti) -{ - CLEAR_BIT(exti->ADTE, EXTI_ADTE_GPIO4_MSK); -} - -/** - * @brief Check if ADC trigger on line 4 is enabled - * @param exti EXTI Instance - * @retval State of bit (1 or 0). - */ -__STATIC_INLINE uint32_t md_exti_is_enable_adte_gpio4(EXTI_TypeDef *exti) -{ - return (READ_BIT(exti->ADTE, EXTI_ADTE_GPIO4_MSK) == (EXTI_ADTE_GPIO4_MSK)); -} - -/** - * @brief Enable ADC trigger on line 5 - * @param exti EXTI Instance - * @retval None - */ -__STATIC_INLINE void md_exti_enable_adte_gpio5(EXTI_TypeDef *exti) -{ - SET_BIT(exti->ADTE, EXTI_ADTE_GPIO5_MSK); -} - -/** - * @brief Disable ADC trigger on line 5 - * @param exti EXTI Instance - * @retval None - */ -__STATIC_INLINE void md_exti_disable_adte_gpio5(EXTI_TypeDef *exti) -{ - CLEAR_BIT(exti->ADTE, EXTI_ADTE_GPIO5_MSK); -} - -/** - * @brief Check if ADC trigger on line 5 is enabled - * @param exti EXTI Instance - * @retval State of bit (1 or 0). - */ -__STATIC_INLINE uint32_t md_exti_is_enable_adte_gpio5(EXTI_TypeDef *exti) -{ - return (READ_BIT(exti->ADTE, EXTI_ADTE_GPIO5_MSK) == (EXTI_ADTE_GPIO5_MSK)); -} - -/** - * @brief Enable ADC trigger on line 6 - * @param exti EXTI Instance - * @retval None - */ -__STATIC_INLINE void md_exti_enable_adte_gpio6(EXTI_TypeDef *exti) -{ - SET_BIT(exti->ADTE, EXTI_ADTE_GPIO6_MSK); -} - -/** - * @brief Disable ADC trigger on line 6 - * @param exti EXTI Instance - * @retval None - */ -__STATIC_INLINE void md_exti_disable_adte_gpio6(EXTI_TypeDef *exti) -{ - CLEAR_BIT(exti->ADTE, EXTI_ADTE_GPIO6_MSK); -} - -/** - * @brief Check if ADC trigger on line 6 is enabled - * @param exti EXTI Instance - * @retval State of bit (1 or 0). - */ -__STATIC_INLINE uint32_t md_exti_is_enable_adte_gpio6(EXTI_TypeDef *exti) -{ - return (READ_BIT(exti->ADTE, EXTI_ADTE_GPIO6_MSK) == (EXTI_ADTE_GPIO6_MSK)); -} - -/** - * @brief Enable ADC trigger on line 7 - * @param exti EXTI Instance - * @retval None - */ -__STATIC_INLINE void md_exti_enable_adte_gpio7(EXTI_TypeDef *exti) -{ - SET_BIT(exti->ADTE, EXTI_ADTE_GPIO7_MSK); -} - -/** - * @brief Disable ADC trigger on line 7 - * @param exti EXTI Instance - * @retval None - */ -__STATIC_INLINE void md_exti_disable_adte_gpio7(EXTI_TypeDef *exti) -{ - CLEAR_BIT(exti->ADTE, EXTI_ADTE_GPIO7_MSK); -} - -/** - * @brief Check if ADC trigger on line 7 is enabled - * @param exti EXTI Instance - * @retval State of bit (1 or 0). - */ -__STATIC_INLINE uint32_t md_exti_is_enable_adte_gpio7(EXTI_TypeDef *exti) -{ - return (READ_BIT(exti->ADTE, EXTI_ADTE_GPIO7_MSK) == (EXTI_ADTE_GPIO7_MSK)); -} - -/** - * @brief Enable ADC trigger on line 8 - * @param exti EXTI Instance - * @retval None - */ -__STATIC_INLINE void md_exti_enable_adte_gpio8(EXTI_TypeDef *exti) -{ - SET_BIT(exti->ADTE, EXTI_ADTE_GPIO8_MSK); -} - -/** - * @brief Disable ADC trigger on line 8 - * @param exti EXTI Instance - * @retval None - */ -__STATIC_INLINE void md_exti_disable_adte_gpio8(EXTI_TypeDef *exti) -{ - CLEAR_BIT(exti->ADTE, EXTI_ADTE_GPIO8_MSK); -} - -/** - * @brief Check if ADC trigger on line 8 is enabled - * @param exti EXTI Instance - * @retval State of bit (1 or 0). - */ -__STATIC_INLINE uint32_t md_exti_is_enable_adte_gpio8(EXTI_TypeDef *exti) -{ - return (READ_BIT(exti->ADTE, EXTI_ADTE_GPIO8_MSK) == (EXTI_ADTE_GPIO8_MSK)); -} - -/** - * @brief Enable ADC trigger on line 9 - * @param exti EXTI Instance - * @retval None - */ -__STATIC_INLINE void md_exti_enable_adte_gpio9(EXTI_TypeDef *exti) -{ - SET_BIT(exti->ADTE, EXTI_ADTE_GPIO9_MSK); -} - -/** - * @brief Disable ADC trigger on line 9 - * @param exti EXTI Instance - * @retval None - */ -__STATIC_INLINE void md_exti_disable_adte_gpio9(EXTI_TypeDef *exti) -{ - CLEAR_BIT(exti->ADTE, EXTI_ADTE_GPIO9_MSK); -} - -/** - * @brief Check if ADC trigger on line 9 is enabled - * @param exti EXTI Instance - * @retval State of bit (1 or 0). - */ -__STATIC_INLINE uint32_t md_exti_is_enable_adte_gpio9(EXTI_TypeDef *exti) -{ - return (READ_BIT(exti->ADTE, EXTI_ADTE_GPIO9_MSK) == (EXTI_ADTE_GPIO9_MSK)); -} - -/** - * @brief Enable ADC trigger on line 10 - * @param exti EXTI Instance - * @retval None - */ -__STATIC_INLINE void md_exti_enable_adte_gpio10(EXTI_TypeDef *exti) -{ - SET_BIT(exti->ADTE, EXTI_ADTE_GPIO10_MSK); -} - -/** - * @brief Disable ADC trigger on line 10 - * @param exti EXTI Instance - * @retval None - */ -__STATIC_INLINE void md_exti_disable_adte_gpio10(EXTI_TypeDef *exti) -{ - CLEAR_BIT(exti->ADTE, EXTI_ADTE_GPIO10_MSK); -} - -/** - * @brief Check if ADC trigger on line 10 is enabled - * @param exti EXTI Instance - * @retval State of bit (1 or 0). - */ -__STATIC_INLINE uint32_t md_exti_is_enable_adte_gpio10(EXTI_TypeDef *exti) -{ - return (READ_BIT(exti->ADTE, EXTI_ADTE_GPIO10_MSK) == (EXTI_ADTE_GPIO10_MSK)); -} - -/** - * @brief Enable ADC trigger on line 11 - * @param exti EXTI Instance - * @retval None - */ -__STATIC_INLINE void md_exti_enable_adte_gpio11(EXTI_TypeDef *exti) -{ - SET_BIT(exti->ADTE, EXTI_ADTE_GPIO11_MSK); -} - -/** - * @brief Disable ADC trigger on line 11 - * @param exti EXTI Instance - * @retval None - */ -__STATIC_INLINE void md_exti_disable_adte_gpio11(EXTI_TypeDef *exti) -{ - CLEAR_BIT(exti->ADTE, EXTI_ADTE_GPIO11_MSK); -} - -/** - * @brief Check if ADC trigger on line 11 is enabled - * @param exti EXTI Instance - * @retval State of bit (1 or 0). - */ -__STATIC_INLINE uint32_t md_exti_is_enable_adte_gpio11(EXTI_TypeDef *exti) -{ - return (READ_BIT(exti->ADTE, EXTI_ADTE_GPIO11_MSK) == (EXTI_ADTE_GPIO11_MSK)); -} - -/** - * @brief Enable ADC trigger on line 12 - * @param exti EXTI Instance - * @retval None - */ -__STATIC_INLINE void md_exti_enable_adte_gpio12(EXTI_TypeDef *exti) -{ - SET_BIT(exti->ADTE, EXTI_ADTE_GPIO12_MSK); -} - -/** - * @brief Disable ADC trigger on line 12 - * @param exti EXTI Instance - * @retval None - */ -__STATIC_INLINE void md_exti_disable_adte_gpio12(EXTI_TypeDef *exti) -{ - CLEAR_BIT(exti->ADTE, EXTI_ADTE_GPIO12_MSK); -} - -/** - * @brief Check if ADC trigger on line 12 is enabled - * @param exti EXTI Instance - * @retval State of bit (1 or 0). - */ -__STATIC_INLINE uint32_t md_exti_is_enable_adte_gpio12(EXTI_TypeDef *exti) -{ - return (READ_BIT(exti->ADTE, EXTI_ADTE_GPIO12_MSK) == (EXTI_ADTE_GPIO12_MSK)); -} - -/** - * @brief Enable ADC trigger on line 13 - * @param exti EXTI Instance - * @retval None - */ -__STATIC_INLINE void md_exti_enable_adte_gpio13(EXTI_TypeDef *exti) -{ - SET_BIT(exti->ADTE, EXTI_ADTE_GPIO13_MSK); -} - -/** - * @brief Disable ADC trigger on line 13 - * @param exti EXTI Instance - * @retval None - */ -__STATIC_INLINE void md_exti_disable_adte_gpio13(EXTI_TypeDef *exti) -{ - CLEAR_BIT(exti->ADTE, EXTI_ADTE_GPIO13_MSK); -} - -/** - * @brief Check if ADC trigger on line 13 is enabled - * @param exti EXTI Instance - * @retval State of bit (1 or 0). - */ -__STATIC_INLINE uint32_t md_exti_is_enable_adte_gpio13(EXTI_TypeDef *exti) -{ - return (READ_BIT(exti->ADTE, EXTI_ADTE_GPIO13_MSK) == (EXTI_ADTE_GPIO13_MSK)); -} - -/** - * @brief Enable ADC trigger on line 14 - * @param exti EXTI Instance - * @retval None - */ -__STATIC_INLINE void md_exti_enable_adte_gpio14(EXTI_TypeDef *exti) -{ - SET_BIT(exti->ADTE, EXTI_ADTE_GPIO14_MSK); -} - -/** - * @brief Disable ADC trigger on line 14 - * @param exti EXTI Instance - * @retval None - */ -__STATIC_INLINE void md_exti_disable_adte_gpio14(EXTI_TypeDef *exti) -{ - CLEAR_BIT(exti->ADTE, EXTI_ADTE_GPIO14_MSK); -} - -/** - * @brief Check if ADC trigger on line 14 is enabled - * @param exti EXTI Instance - * @retval State of bit (1 or 0). - */ -__STATIC_INLINE uint32_t md_exti_is_enable_adte_gpio14(EXTI_TypeDef *exti) -{ - return (READ_BIT(exti->ADTE, EXTI_ADTE_GPIO14_MSK) == (EXTI_ADTE_GPIO14_MSK)); -} - -/** - * @brief Enable ADC trigger on line 15 - * @param exti EXTI Instance - * @retval None - */ -__STATIC_INLINE void md_exti_enable_adte_gpio15(EXTI_TypeDef *exti) -{ - SET_BIT(exti->ADTE, EXTI_ADTE_GPIO15_MSK); -} - -/** - * @brief Disable ADC trigger on line 15 - * @param exti EXTI Instance - * @retval None - */ -__STATIC_INLINE void md_exti_disable_adte_gpio15(EXTI_TypeDef *exti) -{ - CLEAR_BIT(exti->ADTE, EXTI_ADTE_GPIO15_MSK); -} - -/** - * @brief Check if ADC trigger on line is enabled - * @param exti EXTI Instance - * @retval State of bit (1 or 0). - */ -__STATIC_INLINE uint32_t md_exti_is_enable_adte_gpio15(EXTI_TypeDef *exti) -{ - return (READ_BIT(exti->ADTE, EXTI_ADTE_GPIO15_MSK) == (EXTI_ADTE_GPIO15_MSK)); -} - -/** - * @brief Enable ADC trigger on line 16 - * @param exti EXTI Instance - * @retval None - */ -__STATIC_INLINE void md_exti_enable_adte_cmp1(EXTI_TypeDef *exti) -{ - SET_BIT(exti->ADTE, EXTI_ADTE_CMP1_MSK); -} - -/** - * @brief Disable ADC trigger on line 16 - * @param exti EXTI Instance - * @retval None - */ -__STATIC_INLINE void md_exti_disable_adte_cmp1(EXTI_TypeDef *exti) -{ - CLEAR_BIT(exti->ADTE, EXTI_ADTE_CMP1_MSK); -} - -/** - * @brief Check if ADC trigger on line 16 is enabled - * @param exti EXTI Instance - * @retval State of bit (1 or 0). - */ -__STATIC_INLINE uint32_t md_exti_is_enable_adte_cmp1(EXTI_TypeDef *exti) -{ - return (READ_BIT(exti->ADTE, EXTI_ADTE_CMP1_MSK) == (EXTI_ADTE_CMP1_MSK)); -} - -/** - * @brief Enable ADC trigger on line 17 - * @param exti EXTI Instance - * @retval None - */ -__STATIC_INLINE void md_exti_enable_adte_cmp2(EXTI_TypeDef *exti) -{ - SET_BIT(exti->ADTE, EXTI_ADTE_CMP2_MSK); -} - -/** - * @brief Disable ADC trigger on line 17 - * @param exti EXTI Instance - * @retval None - */ -__STATIC_INLINE void md_exti_disable_adte_cmp2(EXTI_TypeDef *exti) -{ - CLEAR_BIT(exti->ADTE, EXTI_ADTE_CMP2_MSK); -} - -/** - * @brief Check if ADC trigger on line 17 is enabled - * @param exti EXTI Instance - * @retval State of bit (1 or 0). - */ -__STATIC_INLINE uint32_t md_exti_is_enable_adte_cmp2(EXTI_TypeDef *exti) -{ - return (READ_BIT(exti->ADTE, EXTI_ADTE_CMP2_MSK) == (EXTI_ADTE_CMP2_MSK)); -} - -/** - * @brief Enable ADC trigger on line 20 - * @param exti EXTI Instance - * @retval None - */ -__STATIC_INLINE void md_exti_enable_adte_pvd0(EXTI_TypeDef *exti) -{ - SET_BIT(exti->ADTE, EXTI_ADTE_PVD0_MSK); -} - -/** - * @brief Disable ADC trigger on line 20 - * @param exti EXTI Instance - * @retval None - */ -__STATIC_INLINE void md_exti_disable_adte_pvd0(EXTI_TypeDef *exti) -{ - CLEAR_BIT(exti->ADTE, EXTI_ADTE_PVD0_MSK); -} - -/** - * @brief Check if ADC trigger on line 20 is enabled - * @param exti EXTI Instance - * @retval State of bit (1 or 0). - */ -__STATIC_INLINE uint32_t md_exti_is_enable_adte_pvd0(EXTI_TypeDef *exti) -{ - return (READ_BIT(exti->ADTE, EXTI_ADTE_PVD0_MSK) == (EXTI_ADTE_PVD0_MSK)); -} - -/** - * @brief Enable ADC trigger on line 21 - * @param exti EXTI Instance - * @retval None - */ -__STATIC_INLINE void md_exti_enable_adte_wakeup(EXTI_TypeDef *exti) -{ - SET_BIT(exti->ADTE, EXTI_ADTE_WAKEUP_MSK); -} - -/** - * @brief Disable ADC trigger on line 21 - * @param exti EXTI Instance - * @retval None - */ -__STATIC_INLINE void md_exti_disable_adte_wakeup(EXTI_TypeDef *exti) -{ - CLEAR_BIT(exti->ADTE, EXTI_ADTE_WAKEUP_MSK); -} - -/** - * @brief Check if ADC trigger on line 21 is enabled - * @param exti EXTI Instance - * @retval State of bit (1 or 0). - */ -__STATIC_INLINE uint32_t md_exti_is_enable_adte_wakeup(EXTI_TypeDef *exti) -{ - return (READ_BIT(exti->ADTE, EXTI_ADTE_WAKEUP_MSK) == (EXTI_ADTE_WAKEUP_MSK)); -} - - -/** - * @} MD_EXTI_PF_ADTE - */ - -/** @defgroup MD_EXTI_PF_INTERRUNPT_MANAGEMENT EXTI Interrupt Management - * @{ - */ - -/** @defgroup MD_EXTI_PF_IER EXTI Interrupt Enable Register - * @{ - */ - - -/** - * @brief Set interrupt enable on line - * @param exti EXTI Instance - * @param value The value write in EXTI->IER - * @retval None - */ -__STATIC_INLINE void md_spi_set_exti_ier(EXTI_TypeDef *exti, uint32_t value) -{ - WRITE_REG(exti->IER, value); -} - -/** - * @brief Enable interrupt on line 0 - * @param exti EXTI Instance - * @retval None - */ -__STATIC_INLINE void md_exti_enable_ier_gpio0(EXTI_TypeDef *exti) -{ - SET_BIT(exti->IER, EXTI_IER_GPIO0_MSK); -} - -/** - * @brief Enable interrupt on line 1 - * @param exti EXTI Instance - * @retval None - */ -__STATIC_INLINE void md_exti_enable_ier_gpio1(EXTI_TypeDef *exti) -{ - SET_BIT(exti->IER, EXTI_IER_GPIO1_MSK); -} - -/** - * @brief Enable interrupt on line 2 - * @param exti EXTI Instance - * @retval None - */ -__STATIC_INLINE void md_exti_enable_ier_gpio2(EXTI_TypeDef *exti) -{ - SET_BIT(exti->IER, EXTI_IER_GPIO2_MSK); -} - -/** - * @brief Enable interrupt on line 3 - * @param exti EXTI Instance - * @retval None - */ -__STATIC_INLINE void md_exti_enable_ier_gpio3(EXTI_TypeDef *exti) -{ - SET_BIT(exti->IER, EXTI_IER_GPIO3_MSK); -} - -/** - * @brief Enable interrupt on line 4 - * @param exti EXTI Instance - * @retval None - */ -__STATIC_INLINE void md_exti_enable_ier_gpio4(EXTI_TypeDef *exti) -{ - SET_BIT(exti->IER, EXTI_IER_GPIO4_MSK); -} - -/** - * @brief Enable interrupt on line 5 - * @param exti EXTI Instance - * @retval None - */ -__STATIC_INLINE void md_exti_enable_ier_gpio5(EXTI_TypeDef *exti) -{ - SET_BIT(exti->IER, EXTI_IER_GPIO5_MSK); -} - -/** - * @brief Enable interrupt on line 6 - * @param exti EXTI Instance - * @retval None - */ -__STATIC_INLINE void md_exti_enable_ier_gpio6(EXTI_TypeDef *exti) -{ - SET_BIT(exti->IER, EXTI_IER_GPIO6_MSK); -} - -/** - * @brief Enable interrupt on line 7 - * @param exti EXTI Instance - * @retval None - */ -__STATIC_INLINE void md_exti_enable_ier_gpio7(EXTI_TypeDef *exti) -{ - SET_BIT(exti->IER, EXTI_IER_GPIO7_MSK); -} - -/** - * @brief Enable interrupt on line 8 - * @param exti EXTI Instance - * @retval None - */ -__STATIC_INLINE void md_exti_enable_ier_gpio8(EXTI_TypeDef *exti) -{ - SET_BIT(exti->IER, EXTI_IER_GPIO8_MSK); -} - -/** - * @brief Enable interrupt on line 9 - * @param exti EXTI Instance - * @retval None - */ -__STATIC_INLINE void md_exti_enable_ier_gpio9(EXTI_TypeDef *exti) -{ - SET_BIT(exti->IER, EXTI_IER_GPIO9_MSK); -} - -/** - * @brief Enable interrupt on line 10 - * @param exti EXTI Instance - * @retval None - */ -__STATIC_INLINE void md_exti_enable_ier_gpio10(EXTI_TypeDef *exti) -{ - SET_BIT(exti->IER, EXTI_IER_GPIO10_MSK); -} - -/** - * @brief Enable interrupt on line 11 - * @param exti EXTI Instance - * @retval None - */ -__STATIC_INLINE void md_exti_enable_ier_gpio11(EXTI_TypeDef *exti) -{ - SET_BIT(exti->IER, EXTI_IER_GPIO11_MSK); -} - -/** - * @brief Enable interrupt on line 12 - * @param exti EXTI Instance - * @retval None - */ -__STATIC_INLINE void md_exti_enable_ier_gpio12(EXTI_TypeDef *exti) -{ - SET_BIT(exti->IER, EXTI_IER_GPIO12_MSK); -} - -/** - * @brief Enable interrupt on line 13 - * @param exti EXTI Instance - * @retval None - */ -__STATIC_INLINE void md_exti_enable_ier_gpio13(EXTI_TypeDef *exti) -{ - SET_BIT(exti->IER, EXTI_IER_GPIO13_MSK); -} - -/** - * @brief Enable interrupt on line 14 - * @param exti EXTI Instance - * @retval None - */ -__STATIC_INLINE void md_exti_enable_ier_gpio14(EXTI_TypeDef *exti) -{ - SET_BIT(exti->IER, EXTI_IER_GPIO14_MSK); -} - -/** - * @brief Enable interrupt on line 15 - * @param exti EXTI Instance - * @retval None - */ -__STATIC_INLINE void md_exti_enable_ier_gpio15(EXTI_TypeDef *exti) -{ - SET_BIT(exti->IER, EXTI_IER_GPIO15_MSK); -} - - -/** - * @brief Enable interrupt on line 16 - * @param exti EXTI Instance - * @retval None - */ -__STATIC_INLINE void md_exti_enable_ier_cmp1(EXTI_TypeDef *exti) -{ - SET_BIT(exti->IER, EXTI_IER_CMP1_MSK); -} - -/** - * @brief Enable interrupt on line 17 - * @param exti EXTI Instance - * @retval None - */ -__STATIC_INLINE void md_exti_enable_ier_cmp2(EXTI_TypeDef *exti) -{ - SET_BIT(exti->IER, EXTI_IER_CMP2_MSK); -} - -/** - * @brief Enable interrupt on line 20 - * @param exti EXTI Instance - * @retval None - */ -__STATIC_INLINE void md_exti_enable_ier_pvd0(EXTI_TypeDef *exti) -{ - SET_BIT(exti->IER, EXTI_IER_PVD0_MSK); -} - -/** - * @brief Enable interrupt on line 21 - * @param exti EXTI Instance - * @retval None - */ -__STATIC_INLINE void md_exti_enable_ier_wakeup(EXTI_TypeDef *exti) -{ - SET_BIT(exti->IER, EXTI_IER_WAKEUP_MSK); -} - -/** - * @} MD_EXTI_PF_IER - */ - -/** @defgroup MD_EXTI_PF_IDR EXTI Interrupt Disable Register - * @{ - */ - -/** - * @brief Disable interrupt on line - * @param exti EXTI Instance - * @param value The value write in EXTI->IDR - * @retval None - */ -__STATIC_INLINE void md_exti_disable_idr(EXTI_TypeDef *exti, uint32_t value) -{ - WRITE_REG(exti->IDR, value); -} - - -/** - * @brief Disable interrupt on line 0 - * @param exti EXTI Instance - * @retval None - */ -__STATIC_INLINE void md_exti_disable_idr_gpio0(EXTI_TypeDef *exti) -{ - SET_BIT(exti->IDR, EXTI_IDR_GPIO0_MSK); -} - -/** - * @brief Disable interrupt on line 1 - * @param exti EXTI Instance - * @retval None - */ -__STATIC_INLINE void md_exti_disable_idr_gpio1(EXTI_TypeDef *exti) -{ - SET_BIT(exti->IDR, EXTI_IDR_GPIO1_MSK); -} - -/** - * @brief Disable interrupt on line 2 - * @param exti EXTI Instance - * @retval None - */ -__STATIC_INLINE void md_exti_disable_idr_gpio2(EXTI_TypeDef *exti) -{ - SET_BIT(exti->IDR, EXTI_IDR_GPIO2_MSK); -} - -/** - * @brief Disable interrupt on line 3 - * @param exti EXTI Instance - * @retval None - */ -__STATIC_INLINE void md_exti_disable_idr_gpio3(EXTI_TypeDef *exti) -{ - SET_BIT(exti->IDR, EXTI_IDR_GPIO3_MSK); -} - -/** - * @brief Disable interrupt on line 4 - * @param exti EXTI Instance - * @retval None - */ -__STATIC_INLINE void md_exti_disable_idr_gpio4(EXTI_TypeDef *exti) -{ - SET_BIT(exti->IDR, EXTI_IDR_GPIO4_MSK); -} - -/** - * @brief Disable interrupt on line 5 - * @param exti EXTI Instance - * @retval None - */ -__STATIC_INLINE void md_exti_disable_idr_gpio5(EXTI_TypeDef *exti) -{ - SET_BIT(exti->IDR, EXTI_IDR_GPIO5_MSK); -} - -/** - * @brief Disable interrupt on line 6 - * @param exti EXTI Instance - * @retval None - */ -__STATIC_INLINE void md_exti_disable_idr_gpio6(EXTI_TypeDef *exti) -{ - SET_BIT(exti->IDR, EXTI_IDR_GPIO6_MSK); -} - -/** - * @brief Disable interrupt on line 7 - * @param exti EXTI Instance - * @retval None - */ -__STATIC_INLINE void md_exti_disable_idr_gpio7(EXTI_TypeDef *exti) -{ - SET_BIT(exti->IDR, EXTI_IDR_GPIO7_MSK); -} - -/** - * @brief Disable interrupt on line 8 - * @param exti EXTI Instance - * @retval None - */ -__STATIC_INLINE void md_exti_disable_idr_gpio8(EXTI_TypeDef *exti) -{ - SET_BIT(exti->IDR, EXTI_IDR_GPIO8_MSK); -} - -/** - * @brief Disable interrupt on line 9 - * @param exti EXTI Instance - * @retval None - */ -__STATIC_INLINE void md_exti_disable_idr_gpio9(EXTI_TypeDef *exti) -{ - SET_BIT(exti->IDR, EXTI_IDR_GPIO9_MSK); -} - -/** - * @brief Disable interrupt on line 10 - * @param exti EXTI Instance - * @retval None - */ -__STATIC_INLINE void md_exti_disable_idr_gpio10(EXTI_TypeDef *exti) -{ - SET_BIT(exti->IDR, EXTI_IDR_GPIO10_MSK); -} - -/** - * @brief Disable interrupt on line 11 - * @param exti EXTI Instance - * @retval None - */ -__STATIC_INLINE void md_exti_disable_idr_gpio11(EXTI_TypeDef *exti) -{ - SET_BIT(exti->IDR, EXTI_IDR_GPIO11_MSK); -} - -/** - * @brief Disable interrupt on line 12 - * @param exti EXTI Instance - * @retval None - */ -__STATIC_INLINE void md_exti_disable_idr_gpio12(EXTI_TypeDef *exti) -{ - SET_BIT(exti->IDR, EXTI_IDR_GPIO12_MSK); -} - -/** - * @brief Disable interrupt on line 13 - * @param exti EXTI Instance - * @retval None - */ -__STATIC_INLINE void md_exti_disable_idr_gpio13(EXTI_TypeDef *exti) -{ - SET_BIT(exti->IDR, EXTI_IDR_GPIO13_MSK); -} - -/** - * @brief Disable interrupt on line 14 - * @param exti EXTI Instance - * @retval None - */ -__STATIC_INLINE void md_exti_disable_idr_gpio14(EXTI_TypeDef *exti) -{ - CLEAR_BIT(exti->IDR, EXTI_IDR_GPIO14_MSK); -} - -/** - * @brief Disable interrupt on line 15 - * @param exti EXTI Instance - * @retval None - */ -__STATIC_INLINE void md_exti_disable_idr_gpio15(EXTI_TypeDef *exti) -{ - SET_BIT(exti->IDR, EXTI_IDR_GPIO15_MSK); -} - -/** - * @brief Disable interrupt on line 16 - * @param exti EXTI Instance - * @retval None - */ -__STATIC_INLINE void md_exti_disable_idr_cmp1(EXTI_TypeDef *exti) -{ - CLEAR_BIT(exti->IDR, EXTI_IDR_CMP1_MSK); -} - -/** - * @brief Disable interrupt on line 17 - * @param exti EXTI Instance - * @retval None - */ -__STATIC_INLINE void md_exti_disable_idr_cmp2(EXTI_TypeDef *exti) -{ - SET_BIT(exti->IDR, EXTI_IDR_CMP2_MSK); -} - -/** - * @brief Disable interrupt on line 20 - * @param exti EXTI Instance - * @retval None - */ -__STATIC_INLINE void md_exti_disable_idr_pvd0(EXTI_TypeDef *exti) -{ - SET_BIT(exti->IDR, EXTI_IDR_PVD0_MSK); -} - -/** - * @brief Disable interrupt on line 21 - * @param exti EXTI Instance - * @retval None - */ -__STATIC_INLINE void md_exti_disable_idr_wakeup(EXTI_TypeDef *exti) -{ - SET_BIT(exti->IDR, EXTI_IDR_WAKEUP_MSK); -} - - -/** - * @} MD_EXTI_PF_IDR - */ - -/** @defgroup MD_EXTI_PF_ICR EXTI Interrupt Clear Register - * @{ - */ - -/** - * @brief Interrupt Clear on line - * @param exti EXTI Instance - * @param value The value write in EXTI->ICR - * @retval None - */ -__STATIC_INLINE void md_exti_clear_icr(EXTI_TypeDef *exti, uint32_t value) -{ - WRITE_REG(exti->ICR, value); -} - -/** - * @brief Interrupt Clear on line 0 - * @param exti EXTI Instance - * @retval None - */ -__STATIC_INLINE void md_exti_clear_icr_gpio0(EXTI_TypeDef *exti) -{ - SET_BIT(exti->ICR, EXTI_ICR_GPIO0_MSK); -} - -/** - * @brief Interrupt Clear on line 1 - * @param exti EXTI Instance - * @retval None - */ -__STATIC_INLINE void md_exti_clear_icr_gpio1(EXTI_TypeDef *exti) -{ - SET_BIT(exti->ICR, EXTI_ICR_GPIO1_MSK); -} - -/** - * @brief Interrupt Clear on line 2 - * @param exti EXTI Instance - * @retval None - */ -__STATIC_INLINE void md_exti_clear_icr_gpio2(EXTI_TypeDef *exti) -{ - SET_BIT(exti->ICR, EXTI_ICR_GPIO2_MSK); -} - -/** - * @brief Interrupt Clear on line 3 - * @param exti EXTI Instance - * @retval None - */ -__STATIC_INLINE void md_exti_clear_icr_gpio3(EXTI_TypeDef *exti) -{ - SET_BIT(exti->ICR, EXTI_ICR_GPIO3_MSK); -} - -/** - * @brief Interrupt Clear on line 4 - * @param exti EXTI Instance - * @retval None - */ -__STATIC_INLINE void md_exti_clear_icr_gpio4(EXTI_TypeDef *exti) -{ - SET_BIT(exti->ICR, EXTI_ICR_GPIO4_MSK); -} - -/** - * @brief Interrupt Clear on line 5 - * @param exti EXTI Instance - * @retval None - */ -__STATIC_INLINE void md_exti_clear_icr_gpio5(EXTI_TypeDef *exti) -{ - SET_BIT(exti->ICR, EXTI_ICR_GPIO5_MSK); -} - -/** - * @brief Interrupt Clear on line 6 - * @param exti EXTI Instance - * @retval None - */ -__STATIC_INLINE void md_exti_clear_icr_gpio6(EXTI_TypeDef *exti) -{ - SET_BIT(exti->ICR, EXTI_ICR_GPIO6_MSK); -} - -/** - * @brief Interrupt Clear on line 7 - * @param exti EXTI Instance - * @retval None - */ -__STATIC_INLINE void md_exti_clear_icr_gpio7(EXTI_TypeDef *exti) -{ - SET_BIT(exti->ICR, EXTI_ICR_GPIO7_MSK); -} - -/** - * @brief Interrupt Clear on line 8 - * @param exti EXTI Instance - * @retval None - */ -__STATIC_INLINE void md_exti_clear_icr_gpio8(EXTI_TypeDef *exti) -{ - SET_BIT(exti->ICR, EXTI_ICR_GPIO8_MSK); -} - -/** - * @brief Interrupt Clear on line 9 - * @param exti EXTI Instance - * @retval None - */ -__STATIC_INLINE void md_exti_clear_icr_gpio9(EXTI_TypeDef *exti) -{ - SET_BIT(exti->ICR, EXTI_ICR_GPIO9_MSK); -} - -/** - * @brief Interrupt Clear on line 10 - * @param exti EXTI Instance - * @retval None - */ -__STATIC_INLINE void md_exti_clear_icr_gpio10(EXTI_TypeDef *exti) -{ - SET_BIT(exti->ICR, EXTI_ICR_GPIO10_MSK); -} - -/** - * @brief Interrupt Clear on line 11 - * @param exti EXTI Instance - * @retval None - */ -__STATIC_INLINE void md_exti_clear_icr_gpio11(EXTI_TypeDef *exti) -{ - SET_BIT(exti->ICR, EXTI_ICR_GPIO11_MSK); -} - -/** - * @brief Interrupt Clear on line 12 - * @param exti EXTI Instance - * @retval None - */ -__STATIC_INLINE void md_exti_clear_icr_gpio12(EXTI_TypeDef *exti) -{ - SET_BIT(exti->ICR, EXTI_ICR_GPIO12_MSK); -} - -/** - * @brief Interrupt Clear on line 13 - * @param exti EXTI Instance - * @retval None - */ -__STATIC_INLINE void md_exti_clear_icr_gpio13(EXTI_TypeDef *exti) -{ - SET_BIT(exti->ICR, EXTI_ICR_GPIO13_MSK); -} - -/** - * @brief Interrupt Clear on line 14 - * @param exti EXTI Instance - * @retval None - */ -__STATIC_INLINE void md_exti_clear_icr_gpio14(EXTI_TypeDef *exti) -{ - SET_BIT(exti->ICR, EXTI_ICR_GPIO14_MSK); -} - -/** - * @brief Interrupt Clear on line 15 - * @param exti EXTI Instance - * @retval None - */ -__STATIC_INLINE void md_exti_clear_icr_gpio15(EXTI_TypeDef *exti) -{ - SET_BIT(exti->ICR, EXTI_ICR_GPIO15_MSK); -} - - -/** - * @brief Interrupt Clear on line 16 - * @param exti EXTI Instance - * @retval None - */ -__STATIC_INLINE void md_exti_clear_icr_cmp1(EXTI_TypeDef *exti) -{ - SET_BIT(exti->ICR, EXTI_ICR_CMP1_MSK); -} - -/** - * @brief Interrupt Clear on line 17 - * @param exti EXTI Instance - * @retval None - */ -__STATIC_INLINE void md_exti_clear_icr_cmp2(EXTI_TypeDef *exti) -{ - SET_BIT(exti->ICR, EXTI_ICR_CMP2_MSK); -} - - -/** - * @brief Interrupt Clear on line 20 - * @param exti EXTI Instance - * @retval None - */ -__STATIC_INLINE void md_exti_clear_icr_pvd0(EXTI_TypeDef *exti) -{ - SET_BIT(exti->ICR, EXTI_ICR_PVD0_MSK); -} - -/** - * @brief Interrupt Clear on line 21 - * @param exti EXTI Instance - * @retval None - */ -__STATIC_INLINE void md_exti_clear_icr_wakeup(EXTI_TypeDef *exti) -{ - SET_BIT(exti->ICR, EXTI_ICR_WAKEUP_MSK); -} - -/** - * @} MD_EXTI_PF_ICR - */ - -/** @defgroup MD_EXTI_PF_IVS EXTI Interrupt Valid Status Register - * @{ - */ - -/** - * @brief Interrupt Valid Status on line - * @param exti EXTI Instance - * @param value The value write in EXTI->IVS - * @retval None - */ -__STATIC_INLINE uint32_t md_exti_is_enable_ivs(EXTI_TypeDef *exti, uint32_t value) -{ - return (READ_REG(exti->IVS)); -} - -/** - * @brief Interrupt Valid Status on line 0 - * @param exti EXTI Instance - * @retval None - */ -__STATIC_INLINE uint32_t md_exti_is_enable_ivs_gpio0(EXTI_TypeDef *exti) -{ - return (READ_BIT(exti->IVS, EXTI_IVS_GPIO0_MSK) == EXTI_IVS_GPIO0_POS); -} - -/** - * @brief Interrupt Valid Status on line 1 - * @param exti EXTI Instance - * @retval None - */ -__STATIC_INLINE uint32_t md_exti_is_enable_ivs_gpio1(EXTI_TypeDef *exti) -{ - return (READ_BIT(exti->IVS, EXTI_IVS_GPIO1_MSK) == EXTI_IVS_GPIO1_POS); -} - -/** - * @brief Interrupt Valid Status on line 2 - * @param exti EXTI Instance - * @retval None - */ -__STATIC_INLINE uint32_t md_exti_is_enable_ivs_gpio2(EXTI_TypeDef *exti) -{ - return (READ_BIT(exti->IVS, EXTI_IVS_GPIO2_MSK) == EXTI_IVS_GPIO2_POS); -} - -/** - * @brief Interrupt Valid Status on line 3 - * @param exti EXTI Instance - * @retval None - */ -__STATIC_INLINE uint32_t md_exti_is_enable_ivs_gpio3(EXTI_TypeDef *exti) -{ - return (READ_BIT(exti->IVS, EXTI_IVS_GPIO3_MSK) == EXTI_IVS_GPIO3_POS); -} - -/** - * @brief Interrupt Valid Status on line 4 - * @param exti EXTI Instance - * @retval None - */ -__STATIC_INLINE uint32_t md_exti_is_enable_ivs_gpio4(EXTI_TypeDef *exti) -{ - return (READ_BIT(exti->IVS, EXTI_IVS_GPIO4_MSK) == EXTI_IVS_GPIO4_POS); -} - -/** - * @brief Interrupt Valid Status on line 5 - * @param exti EXTI Instance - * @retval None - */ -__STATIC_INLINE uint32_t md_exti_is_enable_ivs_gpio5(EXTI_TypeDef *exti) -{ - return (READ_BIT(exti->IVS, EXTI_IVS_GPIO5_MSK)>>EXTI_IVS_GPIO5_POS); -} - -/** - * @brief Interrupt Valid Status on line 6 - * @param exti EXTI Instance - * @retval None - */ -__STATIC_INLINE uint32_t md_exti_is_enable_ivs_gpio6(EXTI_TypeDef *exti) -{ - return (READ_BIT(exti->IVS, EXTI_IVS_GPIO6_MSK) == EXTI_IVS_GPIO6_POS); -} - -/** - * @brief Interrupt Valid Status on line 7 - * @param exti EXTI Instance - * @retval None - */ -__STATIC_INLINE uint32_t md_exti_is_enable_ivs_gpio7(EXTI_TypeDef *exti) -{ - return (READ_BIT(exti->IVS, EXTI_IVS_GPIO7_MSK) == EXTI_IVS_GPIO7_POS); -} - -/** - * @brief Interrupt Valid Status on line 8 - * @param exti EXTI Instance - * @retval None - */ -__STATIC_INLINE uint32_t md_exti_is_enable_ivs_gpio8(EXTI_TypeDef *exti) -{ - return (READ_BIT(exti->IVS, EXTI_IVS_GPIO8_MSK) == EXTI_IVS_GPIO8_POS); -} - -/** - * @brief Interrupt Valid Status on line 9 - * @param exti EXTI Instance - * @retval None - */ -__STATIC_INLINE uint32_t md_exti_is_enable_ivs_gpio9(EXTI_TypeDef *exti) -{ - return (READ_BIT(exti->IVS, EXTI_IVS_GPIO9_MSK) == EXTI_IVS_GPIO9_POS); -} - -/** - * @brief Interrupt Valid Status on line 10 - * @param exti EXTI Instance - * @retval None - */ -__STATIC_INLINE uint32_t md_exti_is_enable_ivs_gpio10(EXTI_TypeDef *exti) -{ - return (READ_BIT(exti->IVS, EXTI_IVS_GPIO10_MSK) == EXTI_IVS_GPIO10_POS); -} - -/** - * @brief Interrupt Valid Status on line 11 - * @param exti EXTI Instance - * @retval None - */ -__STATIC_INLINE uint32_t md_exti_is_enable_ivs_gpio11(EXTI_TypeDef *exti) -{ - return (READ_BIT(exti->IVS, EXTI_IVS_GPIO11_MSK) == EXTI_IVS_GPIO11_POS); -} - -/** - * @brief Interrupt Valid Status on line 12 - * @param exti EXTI Instance - * @retval None - */ -__STATIC_INLINE uint32_t md_exti_is_enable_ivs_gpio12(EXTI_TypeDef *exti) -{ - return (READ_BIT(exti->IVS, EXTI_IVS_GPIO12_MSK) == EXTI_IVS_GPIO12_POS); -} - -/** - * @brief Interrupt Valid Status on line 13 - * @param exti EXTI Instance - * @retval None - */ -__STATIC_INLINE uint32_t md_exti_is_enable_ivs_gpio13(EXTI_TypeDef *exti) -{ - return (READ_BIT(exti->IVS, EXTI_IVS_GPIO13_MSK) == EXTI_IVS_GPIO13_POS); -} - -/** - * @brief Interrupt Valid Status on line 14 - * @param exti EXTI Instance - * @retval None - */ -__STATIC_INLINE uint32_t md_exti_is_enable_ivs_gpio14(EXTI_TypeDef *exti) -{ - return (READ_BIT(exti->IVS, EXTI_IVS_GPIO14_MSK) == EXTI_IVS_GPIO14_POS); -} - -/** - * @brief Interrupt Valid Status on line 15 - * @param exti EXTI Instance - * @retval None - */ -__STATIC_INLINE uint32_t md_exti_is_enable_ivs_gpio15(EXTI_TypeDef *exti) -{ - return (READ_BIT(exti->IVS, EXTI_IVS_GPIO15_MSK) == EXTI_IVS_GPIO15_POS); -} - -/** - * @brief Interrupt Valid Status on line 16 - * @param exti EXTI Instance - * @retval None - */ -__STATIC_INLINE uint32_t md_exti_is_enable_ivs_cmp1(EXTI_TypeDef *exti) -{ - return (READ_BIT(exti->IVS, EXTI_IVS_CMP1_MSK) == EXTI_IVS_CMP1_POS); -} - -/** - * @brief Interrupt Valid Status on line 17 - * @param exti EXTI Instance - * @retval None - */ -__STATIC_INLINE uint32_t md_exti_is_enable_ivs_cmp2(EXTI_TypeDef *exti) -{ - return (READ_BIT(exti->IVS, EXTI_IVS_CMP2_MSK) == EXTI_IVS_CMP2_POS); -} - - -/** - * @brief Interrupt Valid Status on line 20 - * @param exti EXTI Instance - * @retval None - */ -__STATIC_INLINE uint32_t md_exti_is_enable_ivs_pvd0(EXTI_TypeDef *exti) -{ - return (READ_BIT(exti->IVS, EXTI_IVS_PVD0_MSK) == EXTI_IVS_PVD0_POS); -} - -/** - * @brief Interrupt Valid Status on line 21 - * @param exti EXTI Instance - * @retval None - */ - -__STATIC_INLINE uint32_t md_exti_is_enable_ivs_wakeup(EXTI_TypeDef *exti) -{ - return (READ_BIT(exti->IVS, EXTI_IVS_WAKEUP_MSK) == EXTI_IVS_WAKEUP_POS); -} - - -/** - * @} MD_EXTI_PF_IVS - */ - -/** @defgroup MD_EXTI_PF_IFM EXTI Interrupt Flag Masked Status Register - * @{ - */ - -/** - * @brief Check if Interrupt Flag Masked Status on line is actived - * @param exti EXTI Instance - * @retval None - */ -__STATIC_INLINE uint32_t md_exti_is_active_flag_ifm(EXTI_TypeDef *exti) -{ - return (uint32_t)(READ_REG(exti->IFM)); -} - - -/** - * @brief Check if Interrupt Flag Masked Status on line 0 is actived - * @param exti EXTI Instance - * @retval None - */ -__STATIC_INLINE uint32_t md_exti_is_active_flag_ifm_gpio0(EXTI_TypeDef *exti) -{ - return (uint32_t)(READ_BIT(exti->IFM, EXTI_IFM_GPIO0_MSK) == EXTI_IFM_GPIO0_POS); -} - -/** - * @brief Check if Interrupt Flag Masked Status on line 1 is actived - * @param exti EXTI Instance - * @retval None - */ -__STATIC_INLINE uint32_t md_exti_is_active_flag_ifm_gpio1(EXTI_TypeDef *exti) -{ - return (uint32_t)(READ_BIT(exti->IFM, EXTI_IFM_GPIO1_MSK) == EXTI_IFM_GPIO1_POS); -} - -/** - * @brief Check if Interrupt Flag Masked Status on line 2 is actived - * @param exti EXTI Instance - * @retval None - */ -__STATIC_INLINE uint32_t md_exti_is_active_flag_ifm_gpio2(EXTI_TypeDef *exti) -{ - return (uint32_t)(READ_BIT(exti->IFM, EXTI_IFM_GPIO2_MSK) == EXTI_IFM_GPIO2_POS); -} - -/** - * @brief Check if Interrupt Flag Masked Status on line 3 is actived - * @param exti EXTI Instance - * @retval None - */ -__STATIC_INLINE uint32_t md_exti_is_active_flag_ifm_gpio3(EXTI_TypeDef *exti) -{ - return (uint32_t)(READ_BIT(exti->IFM, EXTI_IFM_GPIO3_MSK) == EXTI_IFM_GPIO3_POS); -} - -/** - * @brief Check if Interrupt Flag Masked Status on line 4 is actived - * @param exti EXTI Instance - * @retval None - */ -__STATIC_INLINE uint32_t md_exti_is_active_flag_ifm_gpio4(EXTI_TypeDef *exti) -{ - return (uint32_t)(READ_BIT(exti->IFM, EXTI_IFM_GPIO4_MSK) == EXTI_IFM_GPIO4_POS); -} - -/** - * @brief Check if Interrupt Flag Masked Status on line 5 is actived - * @param exti EXTI Instance - * @retval None - */ -__STATIC_INLINE uint32_t md_exti_is_active_flag_ifm_gpio5(EXTI_TypeDef *exti) -{ - return (uint32_t)(READ_BIT(exti->IFM, EXTI_IFM_GPIO5_MSK) == EXTI_IFM_GPIO5_POS); -} - -/** - * @brief Check if Interrupt Flag Masked Status on line 6 is actived - * @param exti EXTI Instance - * @retval None - */ -__STATIC_INLINE uint32_t md_exti_is_active_flag_ifm_gpio6(EXTI_TypeDef *exti) -{ - return (uint32_t)(READ_BIT(exti->IFM, EXTI_IFM_GPIO6_MSK) == EXTI_IFM_GPIO6_POS); -} - -/** - * @brief Check if Interrupt Flag Masked Status on line 7 is actived - * @param exti EXTI Instance - * @retval None - */ -__STATIC_INLINE uint32_t md_exti_is_active_flag_ifm_gpio7(EXTI_TypeDef *exti) -{ - return (uint32_t)(READ_BIT(exti->IFM, EXTI_IFM_GPIO7_MSK) == EXTI_IFM_GPIO7_POS); -} - -/** - * @brief Check if Interrupt Flag Masked Status on line 8 is actived - * @param exti EXTI Instance - * @retval None - */ -__STATIC_INLINE uint32_t md_exti_is_active_flag_ifm_gpio8(EXTI_TypeDef *exti) -{ - return (uint32_t)(READ_BIT(exti->IFM, EXTI_IFM_GPIO8_MSK) == EXTI_IFM_GPIO8_POS); -} - -/** - * @brief Check if Interrupt Flag Masked Status on line 9 is actived - * @param exti EXTI Instance - * @retval None - */ -__STATIC_INLINE uint32_t md_exti_is_active_flag_ifm_gpio9(EXTI_TypeDef *exti) -{ - return (uint32_t)(READ_BIT(exti->IFM, EXTI_IFM_GPIO9_MSK) == EXTI_IFM_GPIO9_POS); -} - -/** - * @brief Check if Interrupt Flag Masked Status on line 10 is actived - * @param exti EXTI Instance - * @retval None - */ -__STATIC_INLINE uint32_t md_exti_is_active_flag_ifm_gpio10(EXTI_TypeDef *exti) -{ - return (uint32_t)(READ_BIT(exti->IFM, EXTI_IFM_GPIO10_MSK) == EXTI_IFM_GPIO10_POS); -} - -/** - * @brief Check if Interrupt Flag Masked Status on line 11 is actived - * @param exti EXTI Instance - * @retval None - */ -__STATIC_INLINE uint32_t md_exti_is_active_flag_ifm_gpio11(EXTI_TypeDef *exti) -{ - return (uint32_t)(READ_BIT(exti->IFM, EXTI_IFM_GPIO11_MSK) == EXTI_IFM_GPIO11_POS); -} - -/** - * @brief Check if Interrupt Flag Masked Status on line 12 is actived - * @param exti EXTI Instance - * @retval None - */ -__STATIC_INLINE uint32_t md_exti_is_active_flag_ifm_gpio12(EXTI_TypeDef *exti) -{ - return (uint32_t)(READ_BIT(exti->IFM, EXTI_IFM_GPIO12_MSK) == EXTI_IFM_GPIO12_POS); -} - -/** - * @brief Check if Interrupt Flag Masked Status on line 13 is actived - * @param exti EXTI Instance - * @retval None - */ -__STATIC_INLINE uint32_t md_exti_is_active_flag_ifm_gpio13(EXTI_TypeDef *exti) -{ - return (uint32_t)(READ_BIT(exti->IFM, EXTI_IFM_GPIO13_MSK) == EXTI_IFM_GPIO13_POS); -} - -/** - * @brief Check if Interrupt Flag Masked Status on line 14 is actived - * @param exti EXTI Instance - * @retval None - */ -__STATIC_INLINE uint32_t md_exti_is_active_flag_ifm_gpio14(EXTI_TypeDef *exti) -{ - return (uint32_t)(READ_BIT(exti->IFM, EXTI_IFM_GPIO14_MSK) == EXTI_IFM_GPIO14_POS); -} - -/** - * @brief Check if Interrupt Flag Masked Status on line 15 is actived - * @param exti EXTI Instance - * @retval None - */ -__STATIC_INLINE uint32_t md_exti_is_active_flag_ifm_gpio15(EXTI_TypeDef *exti) -{ - return (uint32_t)(READ_BIT(exti->IFM, EXTI_IFM_GPIO15_MSK) == EXTI_IFM_GPIO15_POS); -} - - -/** - * @brief Check if Interrupt Flag Masked Status on line 16 is actived - * @param exti EXTI Instance - * @retval None - */ -__STATIC_INLINE uint32_t md_exti_is_active_flag_ifm_cmp1(EXTI_TypeDef *exti) -{ - return (uint32_t)(READ_BIT(exti->IFM, EXTI_IFM_CMP1_MSK) == EXTI_IFM_CMP1_POS); -} - -/** - * @brief Check if Interrupt Flag Masked Status on line 17 is actived - * @param exti EXTI Instance - * @retval None - */ -__STATIC_INLINE uint32_t md_exti_is_active_flag_ifm_cmp2(EXTI_TypeDef *exti) -{ - return (uint32_t)(READ_BIT(exti->IFM, EXTI_IFM_CMP2_MSK) == EXTI_IFM_CMP2_POS); -} - - -/** - * @brief Check if Interrupt Flag Masked Status on line 20 is actived - * @param exti EXTI Instance - * @retval None - */ -__STATIC_INLINE uint32_t md_exti_is_active_flag_ifm_pvd0(EXTI_TypeDef *exti) -{ - return (uint32_t)(READ_BIT(exti->IFM, EXTI_IFM_PVD0_MSK) == EXTI_IFM_PVD0_POS); -} - -/** - * @brief Check if Interrupt Flag Masked Status on line 21 is actived - * @param exti EXTI Instance - * @retval None - */ -__STATIC_INLINE uint32_t md_exti_is_active_flag_ifm_WAKEUP(EXTI_TypeDef *exti) -{ - return (uint32_t)(READ_BIT(exti->IFM, EXTI_IFM_WAKEUP_MSK) == EXTI_IFM_WAKEUP_POS); -} - -/** - * @} MD_EXTI_PF_IFM - */ - -/** @defgroup MD_EXTI_PF_RIF EXTI Raw Interrupt Flag Status Register - * @{ - */ - - -/** - * @brief Check if Raw interrupt flag Status on line is actived - * @param exti EXTI Instance - * @retval None - */ -__STATIC_INLINE uint32_t md_exti_is_active_flag_rif(EXTI_TypeDef *exti) -{ - return (uint32_t)(READ_REG(exti->RIF)); -} - - -/** - * @brief Check if Raw interrupt flag Status on line 0 is actived - * @param exti EXTI Instance - * @retval None - */ -__STATIC_INLINE uint32_t md_exti_is_active_flag_rif_gpio0(EXTI_TypeDef *exti) -{ - return (uint32_t)(READ_BIT(exti->RIF, EXTI_RIF_GPIO0_MSK) == EXTI_RIF_GPIO0_POS); -} - -/** - * @brief Check if Raw interrupt flag Status on line 1 is actived - * @param exti EXTI Instance - * @retval None - */ -__STATIC_INLINE uint32_t md_exti_is_active_flag_rif_gpio1(EXTI_TypeDef *exti) -{ - return (uint32_t)(READ_BIT(exti->RIF, EXTI_RIF_GPIO1_MSK) == EXTI_RIF_GPIO1_POS); -} - -/** - * @brief Check if Raw interrupt flag Status on line 2 is actived - * @param exti EXTI Instance - * @retval None - */ -__STATIC_INLINE uint32_t md_exti_is_active_flag_rif_gpio2(EXTI_TypeDef *exti) -{ - return (uint32_t)(READ_BIT(exti->RIF, EXTI_RIF_GPIO2_MSK) == EXTI_RIF_GPIO2_POS); -} - -/** - * @brief Check if Raw interrupt flag Status on line 3 is actived - * @param exti EXTI Instance - * @retval None - */ -__STATIC_INLINE uint32_t md_exti_is_active_flag_rif_gpio3(EXTI_TypeDef *exti) -{ - return (uint32_t)(READ_BIT(exti->RIF, EXTI_RIF_GPIO3_MSK) == EXTI_RIF_GPIO3_POS); -} - -/** - * @brief Check if Raw interrupt flag Status on line 4 is actived - * @param exti EXTI Instance - * @retval None - */ -__STATIC_INLINE uint32_t md_exti_is_active_flag_rif_gpio4(EXTI_TypeDef *exti) -{ - return (uint32_t)(READ_BIT(exti->RIF, EXTI_RIF_GPIO4_MSK) == EXTI_RIF_GPIO4_POS); -} - -/** - * @brief Check if Raw interrupt flag Status on line 5 is actived - * @param exti EXTI Instance - * @retval None - */ -__STATIC_INLINE uint32_t md_exti_is_active_flag_rif_gpio5(EXTI_TypeDef *exti) -{ - return (uint32_t)(READ_BIT(exti->RIF, EXTI_RIF_GPIO5_MSK) == EXTI_RIF_GPIO5_POS); -} - -/** - * @brief Check if Raw interrupt flag Status on line 6 is actived - * @param exti EXTI Instance - * @retval None - */ -__STATIC_INLINE uint32_t md_exti_is_active_flag_rif_gpio6(EXTI_TypeDef *exti) -{ - return (uint32_t)(READ_BIT(exti->RIF, EXTI_RIF_GPIO6_MSK) == EXTI_RIF_GPIO6_POS); -} - -/** - * @brief Check if Raw interrupt flag Status on line 7 is actived - * @param exti EXTI Instance - * @retval None - */ -__STATIC_INLINE uint32_t md_exti_is_active_flag_rif_gpio7(EXTI_TypeDef *exti) -{ - return (uint32_t)(READ_BIT(exti->RIF, EXTI_RIF_GPIO7_MSK) == EXTI_RIF_GPIO7_POS); -} - -/** - * @brief Check if Raw interrupt flag Status on line 8 is actived - * @param exti EXTI Instance - * @retval None - */ -__STATIC_INLINE uint32_t md_exti_is_active_flag_rif_gpio8(EXTI_TypeDef *exti) -{ - return (uint32_t)(READ_BIT(exti->RIF, EXTI_RIF_GPIO8_MSK) == EXTI_RIF_GPIO8_POS); -} - -/** - * @brief Check if Raw interrupt flag Status on line 9 is actived - * @param exti EXTI Instance - * @retval None - */ -__STATIC_INLINE uint32_t md_exti_is_active_flag_rif_gpio9(EXTI_TypeDef *exti) -{ - return (uint32_t)(READ_BIT(exti->RIF, EXTI_RIF_GPIO9_MSK) == EXTI_RIF_GPIO9_POS); -} - -/** - * @brief Check if Raw interrupt flag Status on line 10 is actived - * @param exti EXTI Instance - * @retval None - */ -__STATIC_INLINE uint32_t md_exti_is_active_flag_rif_gpio10(EXTI_TypeDef *exti) -{ - return (uint32_t)(READ_BIT(exti->RIF, EXTI_RIF_GPIO10_MSK) == EXTI_RIF_GPIO10_POS); -} - -/** - * @brief Check if Raw interrupt flag Status on line 11 is actived - * @param exti EXTI Instance - * @retval None - */ -__STATIC_INLINE uint32_t md_exti_is_active_flag_rif_gpio11(EXTI_TypeDef *exti) -{ - return (uint32_t)(READ_BIT(exti->RIF, EXTI_RIF_GPIO11_MSK) == EXTI_RIF_GPIO11_POS); -} - -/** - * @brief Check if Raw interrupt flag Status on line 12 is actived - * @param exti EXTI Instance - * @retval None - */ -__STATIC_INLINE uint32_t md_exti_is_active_flag_rif_gpio12(EXTI_TypeDef *exti) -{ - return (uint32_t)(READ_BIT(exti->RIF, EXTI_RIF_GPIO12_MSK) == EXTI_RIF_GPIO12_POS); -} - -/** - * @brief Check if Raw interrupt flag Status on line 13 is actived - * @param exti EXTI Instance - * @retval None - */ -__STATIC_INLINE uint32_t md_exti_is_active_flag_rif_gpio13(EXTI_TypeDef *exti) -{ - return (uint32_t)(READ_BIT(exti->RIF, EXTI_RIF_GPIO13_MSK) == EXTI_RIF_GPIO13_POS); -} - -/** - * @brief Check if Raw interrupt flag Status on line 14 is actived - * @param exti EXTI Instance - * @retval None - */ -__STATIC_INLINE uint32_t md_exti_is_active_flag_rif_gpio14(EXTI_TypeDef *exti) -{ - return (uint32_t)(READ_BIT(exti->RIF, EXTI_RIF_GPIO14_MSK) == EXTI_RIF_GPIO14_POS); -} - -/** - * @brief Check if Raw interrupt flag Status on line 15 is actived - * @param exti EXTI Instance - * @retval None - */ -__STATIC_INLINE uint32_t md_exti_is_active_flag_rif_gpio15(EXTI_TypeDef *exti) -{ - return (uint32_t)(READ_BIT(exti->RIF, EXTI_RIF_GPIO15_MSK) == EXTI_RIF_GPIO15_POS); -} - - -/** - * @brief Check if Raw interrupt flag Status on line 16 is actived - * @param exti EXTI Instance - * @retval None - */ -__STATIC_INLINE uint32_t md_exti_is_active_flag_rif_cmp1(EXTI_TypeDef *exti) -{ - return (uint32_t)(READ_BIT(exti->RIF, EXTI_RIF_CMP1_MSK) == EXTI_RIF_CMP1_POS); -} - -/** - * @brief Check if Raw interrupt flag Status on line 17 is actived - * @param exti EXTI Instance - * @retval None - */ -__STATIC_INLINE uint32_t md_exti_is_active_flag_rif_cmp2(EXTI_TypeDef *exti) -{ - return (uint32_t)(READ_BIT(exti->RIF, EXTI_RIF_CMP2_MSK) == EXTI_RIF_CMP2_POS); -} - - -/** - * @brief Check if Raw interrupt flag Status on line 20 is actived - * @param exti EXTI Instance - * @retval None - */ -__STATIC_INLINE uint32_t md_exti_is_active_flag_rif_pvd0(EXTI_TypeDef *exti) -{ - return (uint32_t)(READ_BIT(exti->RIF, EXTI_RIF_PVD0_MSK) == EXTI_RIF_PVD0_POS); -} - -/** - * @brief Check if Raw interrupt flag Status on line 21 is actived - * @param exti EXTI Instance - * @retval None - */ -__STATIC_INLINE uint32_t md_exti_is_active_flag_rif_WAKEUP(EXTI_TypeDef *exti) -{ - return (uint32_t)(READ_BIT(exti->RIF, EXTI_RIF_WAKEUP_MSK) == EXTI_RIF_WAKEUP_POS); -} - - -/** - * @} MD_EXTI_PF_RIF - */ - - - - -/** - * @} MD_EXTI_PF_INTERRUNPT_MANAGEMENT - */ - - - - - - -/** @defgroup MD_EXTI_PF_DEBOUNCE_SETTING EXTI Debounce Management - * @{ - */ -/** - * @brief Set debounce enable bit of line - * @param exti EXTI Instance - * @param value The value write in EXTI->DB - * @retval None - */ -__STATIC_INLINE void md_spi_set_exti_db(EXTI_TypeDef *exti, uint32_t value) -{ - WRITE_REG(exti->DB, value); -} - -/** - * @brief Get debounce enable bit of line - * @param exti EXTI Instance - * @retval None - */ -__STATIC_INLINE uint32_t md_spi_get_exti_db(EXTI_TypeDef *exti) -{ - return (uint32_t)(READ_REG(exti->DB)); -} - -/** - * @brief Enable debounce enable bit of line 0 - * @param exti EXTI Instance - * @retval None - */ -__STATIC_INLINE void md_exti_enable_db_gpio0(EXTI_TypeDef *exti) -{ - SET_BIT(exti->DB, EXTI_DB_GPIO0_MSK); -} - -/** - * @brief Disable debounce enable bit of line 0 - * @param exti EXTI Instance - * @retval None - */ -__STATIC_INLINE void md_exti_disable_db_gpio0(EXTI_TypeDef *exti) -{ - CLEAR_BIT(exti->DB, EXTI_DB_GPIO0_MSK); -} - -/** - * @brief Check if debounce enable bit of line 0 is enabled - * @param exti EXTI Instance - * @retval State of bit (1 or 0). - */ -__STATIC_INLINE uint32_t md_exti_is_enable_db_gpio0(EXTI_TypeDef *exti) -{ - return (READ_BIT(exti->DB, EXTI_DB_GPIO0_MSK) == (EXTI_DB_GPIO0_MSK)); -} - -/** - * @brief Enable debounce enable bit of line 1 - * @param exti EXTI Instance - * @retval None - */ -__STATIC_INLINE void md_exti_enable_db_gpio1(EXTI_TypeDef *exti) -{ - SET_BIT(exti->DB, EXTI_DB_GPIO1_MSK); -} - -/** - * @brief Disable debounce enable bit of line 1 - * @param exti EXTI Instance - * @retval None - */ -__STATIC_INLINE void md_exti_disable_db_gpio1(EXTI_TypeDef *exti) -{ - CLEAR_BIT(exti->DB, EXTI_DB_GPIO1_MSK); -} - -/** - * @brief Check if debounce enable bit of line 1 is enabled - * @param exti EXTI Instance - * @retval State of bit (1 or 0). - */ -__STATIC_INLINE uint32_t md_exti_is_enable_db_gpio1(EXTI_TypeDef *exti) -{ - return (READ_BIT(exti->DB, EXTI_DB_GPIO1_MSK) == (EXTI_DB_GPIO1_MSK)); -} - -/** - * @brief Enable debounce enable bit of line 2 - * @param exti EXTI Instance - * @retval None - */ -__STATIC_INLINE void md_exti_enable_db_gpio2(EXTI_TypeDef *exti) -{ - SET_BIT(exti->DB, EXTI_DB_GPIO2_MSK); -} - -/** - * @brief Disable debounce enable bit of line 2 - * @param exti EXTI Instance - * @retval None - */ -__STATIC_INLINE void md_exti_disable_db_gpio2(EXTI_TypeDef *exti) -{ - CLEAR_BIT(exti->DB, EXTI_DB_GPIO2_MSK); -} - -/** - * @brief Check if debounce enable bit of line 2 is enabled - * @param exti EXTI Instance - * @retval State of bit (1 or 0). - */ -__STATIC_INLINE uint32_t md_exti_is_enable_db_gpio2(EXTI_TypeDef *exti) -{ - return (READ_BIT(exti->DB, EXTI_DB_GPIO2_MSK) == (EXTI_DB_GPIO2_MSK)); -} - -/** - * @brief Enable debounce enable bit of line 3 - * @param exti EXTI Instance - * @retval None - */ -__STATIC_INLINE void md_exti_enable_db_gpio3(EXTI_TypeDef *exti) -{ - SET_BIT(exti->DB, EXTI_DB_GPIO3_MSK); -} - -/** - * @brief Disable debounce enable bit of line 3 - * @param exti EXTI Instance - * @retval None - */ -__STATIC_INLINE void md_exti_disable_db_gpio3(EXTI_TypeDef *exti) -{ - CLEAR_BIT(exti->DB, EXTI_DB_GPIO3_MSK); -} - -/** - * @brief Check if debounce enable bit of line 3 is enabled - * @param exti EXTI Instance - * @retval State of bit (1 or 0). - */ -__STATIC_INLINE uint32_t md_exti_is_enable_db_gpio3(EXTI_TypeDef *exti) -{ - return (READ_BIT(exti->DB, EXTI_DB_GPIO3_MSK) == (EXTI_DB_GPIO3_MSK)); -} - -/** - * @brief Enable debounce enable bit of line 4 - * @param exti EXTI Instance - * @retval None - */ -__STATIC_INLINE void md_exti_enable_db_gpio4(EXTI_TypeDef *exti) -{ - SET_BIT(exti->DB, EXTI_DB_GPIO4_MSK); -} - -/** - * @brief Disable debounce enable bit of line 4 - * @param exti EXTI Instance - * @retval None - */ -__STATIC_INLINE void md_exti_disable_db_gpio4(EXTI_TypeDef *exti) -{ - CLEAR_BIT(exti->DB, EXTI_DB_GPIO4_MSK); -} - -/** - * @brief Check if debounce enable bit of line 4 is enabled - * @param exti EXTI Instance - * @retval State of bit (1 or 0). - */ -__STATIC_INLINE uint32_t md_exti_is_enable_db_gpio4(EXTI_TypeDef *exti) -{ - return (READ_BIT(exti->DB, EXTI_DB_GPIO4_MSK) == (EXTI_DB_GPIO4_MSK)); -} - -/** - * @brief Enable debounce enable bit of line 5 - * @param exti EXTI Instance - * @retval None - */ -__STATIC_INLINE void md_exti_enable_db_gpio5(EXTI_TypeDef *exti) -{ - SET_BIT(exti->DB, EXTI_DB_GPIO5_MSK); -} - -/** - * @brief Disable debounce enable bit of line 5 - * @param exti EXTI Instance - * @retval None - */ -__STATIC_INLINE void md_exti_disable_db_gpio5(EXTI_TypeDef *exti) -{ - CLEAR_BIT(exti->DB, EXTI_DB_GPIO5_MSK); -} - -/** - * @brief Check if debounce enable bit of line 5 is enabled - * @param exti EXTI Instance - * @retval State of bit (1 or 0). - */ -__STATIC_INLINE uint32_t md_exti_is_enable_db_gpio5(EXTI_TypeDef *exti) -{ - return (READ_BIT(exti->DB, EXTI_DB_GPIO5_MSK) == (EXTI_DB_GPIO5_MSK)); -} - -/** - * @brief Enable debounce enable bit of line 6 - * @param exti EXTI Instance - * @retval None - */ -__STATIC_INLINE void md_exti_enable_db_gpio6(EXTI_TypeDef *exti) -{ - SET_BIT(exti->DB, EXTI_DB_GPIO6_MSK); -} - -/** - * @brief Disable debounce enable bit of line 6 - * @param exti EXTI Instance - * @retval None - */ -__STATIC_INLINE void md_exti_disable_db_gpio6(EXTI_TypeDef *exti) -{ - CLEAR_BIT(exti->DB, EXTI_DB_GPIO6_MSK); -} - -/** - * @brief Check if debounce enable bit of line 6 is enabled - * @param exti EXTI Instance - * @retval State of bit (1 or 0). - */ -__STATIC_INLINE uint32_t md_exti_is_enable_db_gpio6(EXTI_TypeDef *exti) -{ - return (READ_BIT(exti->DB, EXTI_DB_GPIO6_MSK) == (EXTI_DB_GPIO6_MSK)); -} - -/** - * @brief Enable debounce enable bit of line 7 - * @param exti EXTI Instance - * @retval None - */ -__STATIC_INLINE void md_exti_enable_db_gpio7(EXTI_TypeDef *exti) -{ - SET_BIT(exti->DB, EXTI_DB_GPIO7_MSK); -} - -/** - * @brief Disable debounce enable bit of line 7 - * @param exti EXTI Instance - * @retval None - */ -__STATIC_INLINE void md_exti_disable_db_gpio7(EXTI_TypeDef *exti) -{ - CLEAR_BIT(exti->DB, EXTI_DB_GPIO7_MSK); -} - -/** - * @brief Check if debounce enable bit of line 7 is enabled - * @param exti EXTI Instance - * @retval State of bit (1 or 0). - */ -__STATIC_INLINE uint32_t md_exti_is_enable_db_gpio7(EXTI_TypeDef *exti) -{ - return (READ_BIT(exti->DB, EXTI_DB_GPIO7_MSK) == (EXTI_DB_GPIO7_MSK)); -} - -/** - * @brief Enable debounce enable bit of line 8 - * @param exti EXTI Instance - * @retval None - */ -__STATIC_INLINE void md_exti_enable_db_gpio8(EXTI_TypeDef *exti) -{ - SET_BIT(exti->DB, EXTI_DB_GPIO8_MSK); -} - -/** - * @brief Disable debounce enable bit of line 8 - * @param exti EXTI Instance - * @retval None - */ -__STATIC_INLINE void md_exti_disable_db_gpio8(EXTI_TypeDef *exti) -{ - CLEAR_BIT(exti->DB, EXTI_DB_GPIO1_MSK); -} - -/** - * @brief Check if debounce enable bit of line 8 is enabled - * @param exti EXTI Instance - * @retval State of bit (1 or 0). - */ -__STATIC_INLINE uint32_t md_exti_is_enable_db_gpio8(EXTI_TypeDef *exti) -{ - return (READ_BIT(exti->DB, EXTI_DB_GPIO8_MSK) == (EXTI_DB_GPIO8_MSK)); -} - -/** - * @brief Enable debounce enable bit of line 9 - * @param exti EXTI Instance - * @retval None - */ -__STATIC_INLINE void md_exti_enable_db_gpio9(EXTI_TypeDef *exti) -{ - SET_BIT(exti->DB, EXTI_DB_GPIO9_MSK); -} - -/** - * @brief Disable debounce enable bit of line 9 - * @param exti EXTI Instance - * @retval None - */ -__STATIC_INLINE void md_exti_disable_db_gpio9(EXTI_TypeDef *exti) -{ - CLEAR_BIT(exti->DB, EXTI_DB_GPIO9_MSK); -} - -/** - * @brief Check if debounce enable bit of line 9 is enabled - * @param exti EXTI Instance - * @retval State of bit (1 or 0). - */ -__STATIC_INLINE uint32_t md_exti_is_enable_db_gpio9(EXTI_TypeDef *exti) -{ - return (READ_BIT(exti->DB, EXTI_DB_GPIO9_MSK) == (EXTI_DB_GPIO9_MSK)); -} - -/** - * @brief Enable debounce enable bit of line 10 - * @param exti EXTI Instance - * @retval None - */ -__STATIC_INLINE void md_exti_enable_db_gpio10(EXTI_TypeDef *exti) -{ - SET_BIT(exti->DB, EXTI_DB_GPIO10_MSK); -} - -/** - * @brief Disable debounce enable bit of line 10 - * @param exti EXTI Instance - * @retval None - */ -__STATIC_INLINE void md_exti_disable_db_gpio10(EXTI_TypeDef *exti) -{ - CLEAR_BIT(exti->DB, EXTI_DB_GPIO10_MSK); -} - -/** - * @brief Check if debounce enable bit of line 10 is enabled - * @param exti EXTI Instance - * @retval State of bit (1 or 0). - */ -__STATIC_INLINE uint32_t md_exti_is_enable_db_gpio10(EXTI_TypeDef *exti) -{ - return (READ_BIT(exti->DB, EXTI_DB_GPIO10_MSK) == (EXTI_DB_GPIO10_MSK)); -} - -/** - * @brief Enable debounce enable bit of line 11 - * @param exti EXTI Instance - * @retval None - */ -__STATIC_INLINE void md_exti_enable_db_gpio11(EXTI_TypeDef *exti) -{ - SET_BIT(exti->DB, EXTI_DB_GPIO11_MSK); -} - -/** - * @brief Disable debounce enable bit of line 11 - * @param exti EXTI Instance - * @retval None - */ -__STATIC_INLINE void md_exti_disable_db_gpio11(EXTI_TypeDef *exti) -{ - CLEAR_BIT(exti->DB, EXTI_DB_GPIO11_MSK); -} - -/** - * @brief Check if debounce enable bit of line 11 is enabled - * @param exti EXTI Instance - * @retval State of bit (1 or 0). - */ -__STATIC_INLINE uint32_t md_exti_is_enable_db_gpio11(EXTI_TypeDef *exti) -{ - return (READ_BIT(exti->DB, EXTI_DB_GPIO11_MSK) == (EXTI_DB_GPIO11_MSK)); -} - -/** - * @brief Enable debounce enable bit of line 12 - * @param exti EXTI Instance - * @retval None - */ -__STATIC_INLINE void md_exti_enable_db_gpio12(EXTI_TypeDef *exti) -{ - SET_BIT(exti->DB, EXTI_DB_GPIO12_MSK); -} - -/** - * @brief Disable debounce enable bit of line 12 - * @param exti EXTI Instance - * @retval None - */ -__STATIC_INLINE void md_exti_disable_db_gpio12(EXTI_TypeDef *exti) -{ - CLEAR_BIT(exti->DB, EXTI_DB_GPIO12_MSK); -} - -/** - * @brief Check if debounce enable bit of line 12 is enabled - * @param exti EXTI Instance - * @retval State of bit (1 or 0). - */ -__STATIC_INLINE uint32_t md_exti_is_enable_db_gpio12(EXTI_TypeDef *exti) -{ - return (READ_BIT(exti->DB, EXTI_DB_GPIO12_MSK) == (EXTI_DB_GPIO12_MSK)); -} - -/** - * @brief Enable debounce enable bit of line 13 - * @param exti EXTI Instance - * @retval None - */ -__STATIC_INLINE void md_exti_enable_db_gpio13(EXTI_TypeDef *exti) -{ - SET_BIT(exti->DB, EXTI_DB_GPIO13_MSK); -} - -/** - * @brief Disable debounce enable bit of line 13 - * @param exti EXTI Instance - * @retval None - */ -__STATIC_INLINE void md_exti_disable_db_gpio13(EXTI_TypeDef *exti) -{ - CLEAR_BIT(exti->DB, EXTI_DB_GPIO13_MSK); -} - -/** - * @brief Check if debounce enable bit of line 13 is enabled - * @param exti EXTI Instance - * @retval State of bit (1 or 0). - */ -__STATIC_INLINE uint32_t md_exti_is_enable_db_gpio13(EXTI_TypeDef *exti) -{ - return (READ_BIT(exti->DB, EXTI_DB_GPIO13_MSK) == (EXTI_DB_GPIO13_MSK)); -} - -/** - * @brief Enable debounce enable bit of line 14 - * @param exti EXTI Instance - * @retval None - */ -__STATIC_INLINE void md_exti_enable_db_gpio14(EXTI_TypeDef *exti) -{ - SET_BIT(exti->DB, EXTI_DB_GPIO14_MSK); -} - -/** - * @brief Disable debounce enable bit of line 14 - * @param exti EXTI Instance - * @retval None - */ -__STATIC_INLINE void md_exti_disable_db_gpio14(EXTI_TypeDef *exti) -{ - CLEAR_BIT(exti->DB, EXTI_DB_GPIO14_MSK); -} - -/** - * @brief Check if debounce enable bit of line 14 is enabled - * @param exti EXTI Instance - * @retval State of bit (1 or 0). - */ -__STATIC_INLINE uint32_t md_exti_is_enable_db_gpio14(EXTI_TypeDef *exti) -{ - return (READ_BIT(exti->DB, EXTI_DB_GPIO14_MSK) == (EXTI_DB_GPIO14_MSK)); -} - -/** - * @brief Enable debounce enable bit of line 1 - * @param exti EXTI Instance - * @retval None - */ -__STATIC_INLINE void md_exti_enable_db_gpio15(EXTI_TypeDef *exti) -{ - SET_BIT(exti->DB, EXTI_DB_GPIO15_MSK); -} - -/** - * @brief Disable debounce enable bit of line 15 - * @param exti EXTI Instance - * @retval None - */ -__STATIC_INLINE void md_exti_disable_db_gpio15(EXTI_TypeDef *exti) -{ - CLEAR_BIT(exti->DB, EXTI_DB_GPIO15_MSK); -} - -/** - * @brief Check if debounce enable bit of line 15 is enabled - * @param exti EXTI Instance - * @retval State of bit (1 or 0). - */ -__STATIC_INLINE uint32_t md_exti_is_enable_db_gpio15(EXTI_TypeDef *exti) -{ - return (READ_BIT(exti->DB, EXTI_DB_GPIO15_MSK) == (EXTI_DB_GPIO15_MSK)); -} - - -/** - * @brief Enable debounce enable bit of line 16 - * @param exti EXTI Instance - * @retval None - */ -__STATIC_INLINE void md_exti_enable_db_cmp1(EXTI_TypeDef *exti) -{ - SET_BIT(exti->DB, EXTI_DB_CMP1_MSK); -} - -/** - * @brief Disable debounce enable bit of line 16 - * @param exti EXTI Instance - * @retval None - */ -__STATIC_INLINE void md_exti_disable_db_cmp1(EXTI_TypeDef *exti) -{ - CLEAR_BIT(exti->DB, EXTI_DB_CMP1_MSK); -} - -/** - * @brief Check if debounce enable bit of line 16 is enabled - * @param exti EXTI Instance - * @retval State of bit (1 or 0). - */ -__STATIC_INLINE uint32_t md_exti_is_enable_db_cmp1(EXTI_TypeDef *exti) -{ - return (READ_BIT(exti->DB, EXTI_DB_CMP1_MSK) == (EXTI_DB_CMP1_MSK)); -} - -/** - * @brief Enable debounce enable bit of line 17 - * @param exti EXTI Instance - * @retval None - */ -__STATIC_INLINE void md_exti_enable_db_cmp2(EXTI_TypeDef *exti) -{ - SET_BIT(exti->DB, EXTI_DB_CMP2_MSK); -} - -/** - * @brief Disable debounce enable bit of line 17 - * @param exti EXTI Instance - * @retval None - */ -__STATIC_INLINE void md_exti_disable_db_cmp2(EXTI_TypeDef *exti) -{ - CLEAR_BIT(exti->DB, EXTI_DB_CMP2_MSK); -} - -/** - * @brief Check if debounce enable bit of line 17 is enabled - * @param exti EXTI Instance - * @retval State of bit (1 or 0). - */ -__STATIC_INLINE uint32_t md_exti_is_enable_db_cmp2(EXTI_TypeDef *exti) -{ - return (READ_BIT(exti->DB, EXTI_DB_CMP2_MSK) == (EXTI_DB_CMP2_MSK)); -} - -/** - * @brief Enable debounce enable bit of line 20 - * @param exti EXTI Instance - * @retval None - */ -__STATIC_INLINE void md_exti_enable_db_pvd0(EXTI_TypeDef *exti) -{ - SET_BIT(exti->DB, EXTI_DB_PVD0_MSK); -} - -/** - * @brief Disable debounce enable bit of line 20 - * @param exti EXTI Instance - * @retval None - */ -__STATIC_INLINE void md_exti_disable_db_pvd0(EXTI_TypeDef *exti) -{ - CLEAR_BIT(exti->DB, EXTI_DB_PVD0_MSK); -} - -/** - * @brief Check if debounce enable bit of line 20 is enabled - * @param exti EXTI Instance - * @retval State of bit (1 or 0). - */ -__STATIC_INLINE uint32_t md_exti_is_enable_db_pvd0(EXTI_TypeDef *exti) -{ - return (READ_BIT(exti->DB, EXTI_DB_PVD0_MSK) == (EXTI_DB_PVD0_MSK)); -} - -/** - * @brief Enable debounce enable bit of line 21 - * @param exti EXTI Instance - * @retval None - */ -__STATIC_INLINE void md_exti_enable_db_wakeup(EXTI_TypeDef *exti) -{ - SET_BIT(exti->DB, EXTI_DB_WAKEUP_MSK); -} - -/** - * @brief Disable debounce enable bit of line 21 - * @param exti EXTI Instance - * @retval None - */ -__STATIC_INLINE void md_exti_disable_db_wakeup(EXTI_TypeDef *exti) -{ - CLEAR_BIT(exti->DB, EXTI_DB_WAKEUP_MSK); -} - -/** - * @brief Check if debounce enable bit of line 21 is enabled - * @param exti EXTI Instance - * @retval State of bit (1 or 0). - */ -__STATIC_INLINE uint32_t md_exti_is_enable_db_wakeup(EXTI_TypeDef *exti) -{ - return (READ_BIT(exti->DB, EXTI_DB_WAKEUP_MSK) == (EXTI_DB_WAKEUP_MSK)); -} - -/** - * @brief Set Debounce counter - * @param exti EXTI Port - * @param dbcnt This bit can be one of following valus: - * @arg Max Value 7 - * @arg Min Value 0 - * @retval None - */ -__STATIC_INLINE void md_exti_set_dbcon_dbcnt(EXTI_TypeDef *exti, uint32_t dbcnt) -{ - MODIFY_REG(exti->DBCON, EXTI_DBCON_DBCNT_MSK, (dbcnt<DBCON, EXTI_DBCON_DBCNT_MSK)>>EXTI_DBCON_DBCNT_POSS); -} - -/** - * @brief Set Debounce prescale - * @param exti EXTI Port - * @param prescale This bit can be one of following valus: - * @arg Max Value 255 - * @arg Min Value 0 - * @retval None - */ -__STATIC_INLINE void md_exti_set_dbcon_dbpre(EXTI_TypeDef *exti, uint32_t prescale) -{ - MODIFY_REG(exti->DBCON, EXTI_DBCON_DBPRE_MSK, (prescale<DBCON, EXTI_DBCON_DBPRE_MSK)>>EXTI_DBCON_DBPRE_POSS); -} - - -/** - * @} MD_EXTI_PF_DEBOUNCE_SETTING - */ - - - - - - -/** - * @} MD_EXTI_Public_Macros - */ - - - - -/* Public functions -----------------------------------------------------------*/ - - - -/** - * @} EXTI - */ - -#endif - - - -/** - * @} Micro_Driver - */ - -#endif - -#ifdef __cplusplus -} -#endif - - -/******************* (C) COPYRIGHT Eastsoft Microelectronics *****END OF FILE****/ diff --git a/bsp/essemi/es32f0271/libraries/ES32F027x_MD_StdPeriph_Driver/Include/md_fc.h b/bsp/essemi/es32f0271/libraries/ES32F027x_MD_StdPeriph_Driver/Include/md_fc.h deleted file mode 100644 index a7d85653bd..0000000000 --- a/bsp/essemi/es32f0271/libraries/ES32F027x_MD_StdPeriph_Driver/Include/md_fc.h +++ /dev/null @@ -1,832 +0,0 @@ -/** - ****************************************************************************** - * @file md_FC.h - * @brief ES32F0271 FC HEAD File. - * - * @version V1.00.01 - * @date 11/20/2018 - * @author Eastsoft AE Team - * @note - * detailed description - * - * Copyright (C) 2018 Shanghai Eastsoft Microelectronics Co., Ltd. ALL rights reserved. - ******************************************************************************* - */ - -/* Define to prevent recursive inclusion -------------------------------------*/ -#ifndef __MD_FC_H__ -#define __MD_FC_H__ - -#ifdef __cplusplus -extern "C" { -#endif - -/* Includes -------------------------------------------------------------------*/ -#include "es32f0271.h" -#include "reg_fc.h" - -/** @addtogroup Micro_Driver - * @{ - */ - -#if defined (FC) - -/** @defgroup FC FC - * @brief FC micro driver - * @{ - */ - -/* Private types --------------------------------------------------------------*/ -/* Private variables ----------------------------------------------------------*/ -/* Private constants ----------------------------------------------------------*/ -/* Private macros -------------------------------------------------------------*/ - -/* Public types ---------------------------------------------------------------*/ -/** @defgroup MD_FC_Public_Types FC Public Types - * @{ - */ - -/** - * @brief MD FC Parameter Structure definition - */ -typedef struct -{ - uint32_t SAddr; /*!< Specifies the FC sector address to be erased. - This parameter should be aligned with 0x400*/ - - uint32_t SAddrC; /*!< Specifies the complement of FC sector address to be erased. - This parameter should be the complement of FC page address*/ - - uint16_t BCnt; /*!< Specifies the control byte count. - For program, this parameter should be aligned with 8 and smaller than 0x400 - For read, this parameter should be aligned with 4*/ - - uint32_t *pU32Buf; /*!< Specifies the uint32_t data buffer to program. - This parameter should be the pointer to uint32_t*/ - -} md_fc_ControlTypeDef; - -/** - * @brief MD FC Update Protect Level Structure definition - */ -typedef struct -{ - uint32_t UpdateL; /*!< Specifies the protect page bit mapping low byte (page 31~0) (0=protect, 1=unprotect). - This parameter can be any value between 0~65535*/ - - uint32_t UpdateH; /*!< Specifies the protect page bit mapping high byte (page 63~32) (0=protect, 1=unprotect). - This parameter can be any value between 0~65535*/ - - uint32_t ClearL; /*!< Specifies the reserve page bit mapping low byte (page 31~0) (0=reserve, 1=erase). - This parameter can be any value between 0~65535*/ - - uint32_t ClearH; /*!< Specifies the reserve page bit mapping high byte (page 63~32) (0=reserve, 1=erase). - This parameter can be any value between 0~65535*/ - -} md_fc_UpdProtTypeDef; - -/** - * @} MD_FC_Public_Types - */ - -/* Public constants -----------------------------------------------------------*/ -/** @defgroup MD_FC_Public_Constants FC Public Constants - * @{ - */ - -#define MD_FC_PC_EF_MPAGESZ (0x00000400UL) /** @brief Select main page size */ -#define MD_FC_PC_EF_IPAGESZ (0x00000400UL) /** @brief Select information page size */ -#define MD_FC_PC_EF_MERASEID (0xA5A5AA55UL) /** @brief Select main erase ID */ - -#define MD_FC_PC_CMD_PROG_EFLASH (0xF0) /** @brief Program EFlash */ -#define MD_FC_PC_CMD_SECTOR_ERASE (0xF1) /** @brief Sector Erase */ -#define MD_FC_PC_CMD_MACRO_ERASE (0xF2) /** @brief Macro Erase */ -#define MD_FC_PC_CMD_UPDATE_LV1_PROTECT (0xF3) /** @brief Update Lv1 Protect */ -#define MD_FC_PC_CMD_UPDATE_LV2_PROTECT (0xF4) /** @brief Update Lv2 Protect */ -#define MD_FC_PC_CMD_OPTION_BYTE_ERASE (0xF5) /** @brief Option Byte Erase(Only for ISP) */ - -#define MD_FC_PC_SREMAP_MAIN (0x00) /** @brief Main Flash memory mapped at 0x0000 0000 */ -#define MD_FC_PC_SREMAP_SYSTEM (0x01) /** @brief System Flash memory mapped at 0x0000 0000 */ -#define MD_FC_PC_SREMAP_SRAM (0x02) /** @brief SRAM mapped at 0x0000 0000 */ - -/** - * @} MD_FC_Public_Constants - */ - -/* Public macro ---------------------------------------------------------------*/ -/** @defgroup MD_FC_Public_Macros FC Public Macros - * @{ - */ - -/** @defgroup MD_FC_PM_WRITE_READ Common write and read registers Macros - * @{ - */ - -/** - * @brief Write a value in FC register - * @param __INSTANCE__ FC Instance - * @param __REG__ Register to be written - * @param __VALUE__ Value to be written in the register - * @retval None - */ -#define MD_FC_WRITEREG(__INSTANCE__, __REG__, __VALUE__) WRITE_REG(__INSTANCE__->__REG__, (__VALUE__)) - -/** - * @brief Read a value in FC register - * @param __INSTANCE__ FC Instance - * @param __REG__ Register to be read - * @retval Register value - */ -#define MD_FC_READREG(__INSTANCE__, __REG__) READ_REG(__INSTANCE__->__REG__) - -/** - * @brief Modify value in FC register - * @param __INSTANCE__ FC Instance - * @param __REG__ Register to be written - * @param __MASK__ Mask value to be written in the register - * @param __VALUE__ Value to be written in the register - * @retval None - */ -#define MD_FC_MODIFYREG(__INSTANCE__, __REG__, __MASK__, __VALUE__) MODIFY_REG(__INSTANCE__->__REG__, __MASK__, (__VALUE__)) - -/** - * @brief Set bit value in FC register - * @param __INSTANCE__ FC Instance - * @param __REG__ Register to be written - * @param __MASK__ Mask value to be set in the register - * @retval None - */ -#define MD_FC_SET_BIT(__INSTANCE__, __REG__, __MASK__) SET_BIT(__INSTANCE__->__REG__, __MASK__) - -/** - * @brief Clear bit value in FC register - * @param __INSTANCE__ FC Instance - * @param __REG__ Register to be written - * @param __MASK__ Mask value to be cleared in the register - * @retval None - */ -#define MD_FC_CLEAR_BIT(__INSTANCE__, __REG__, __MASK__) CLEAR_BIT(__INSTANCE__->__REG__, __MASK__) - -/** - * @brief Read bit value in FC register - * @param __INSTANCE__ FC Instance - * @param __REG__ Register to be read - * @param __MASK__ Mask value to be read in the register - * @retval Register bit value - */ -#define MD_FC_READBIT(__INSTANCE__, __REG__, __MASK__) READ_BIT(__INSTANCE__->__REG__, __MASK__) - -/** - * @} MD_FC_PM_WRITE_READ - */ - -/** @defgroup MD_FC_Macro_Drivers FC Public Macro Drivers - * @{ - */ - -/** - * @brief Set FC CMD - * @param @arg Max Value 0xffffffff - * @arg Min Value 0x0 - * @retval None - */ -__STATIC_INLINE void md_fc_set_cmd(uint32_t U32) -{ - MD_FC_WRITEREG(FC, CMD, U32); -} - -/** - * @brief Get FC CMD - * @param None - * @retval The retval can be one of the following values: - * @arg Max Value 0xffffffff - * @arg Min Value 0x0 - */ -__STATIC_INLINE uint32_t md_fc_get_cmd(void) -{ - return (MD_FC_READREG(FC, CMD)); -} - -/** - * @brief Set FC CMD Flash Command - * @note After procedure is finished, Flash command will be cleaned by itself - * @param @arg @ref MD_FC_PC_CMD_PROG_EFLASH(0xF0) : Program EFlash - * @arg @ref MD_FC_PC_CMD_SECTOR_ERASE(0xF1) : Sector Erase - * @arg @ref MD_FC_PC_CMD_MACRO_ERASE(0xF2) : Macro Erase - * @arg @ref MD_FC_PC_CMD_UPDATE_LV1_PROTECT(0xF3) : Update Lv1 Protect - * @arg @ref MD_FC_PC_CMD_UPDATE_LV2_PROTECT(0xF4) : Update Lv2 Protect - * @arg @ref MD_FC_PC_CMD_OPTION_BYTE_ERASE(0xF5) : Option Byte Erase(Only for ISP) - * @arg Else : Reserved - * @retval None - */ -__STATIC_INLINE void md_fc_set_fc_cmd(uint32_t Cmd) -{ - MD_FC_MODIFYREG(FC, CMD, FC_CMD_FC_CMD_MSK, (Cmd<>FC_CMD_FC_CMD_POSS); -} - -/** - * @brief Set FC PA - * @param @arg Max Value 0xffffffff - * @arg Min Value 0x0 - * @retval None - */ -__STATIC_INLINE void md_fc_set_pa(uint32_t U32) -{ - MD_FC_WRITEREG(FC, PA, U32); -} - -/** - * @brief Get FC PA - * @param None - * @retval The retval can be one of the following values: - * @arg Max Value 0xffffffff - * @arg Min Value 0x0 - */ -__STATIC_INLINE uint32_t md_fc_get_pa(void) -{ - return (MD_FC_READREG(FC, PA)); -} - -/** - * @brief Set FC Program Counter - * @note Provide maximum 128 times continuous program - * @note Meanwhile user needs to fill out FC_PLD, FC_PHD and FC_CMD only - * @param @arg Max Value 0x7f - * @arg Min Value 0x0 - * @retval None - */ -__STATIC_INLINE void md_fc_set_pa_pcnt(uint32_t PCnt) -{ - MD_FC_MODIFYREG(FC, PA, FC_PA_PCNT_MSK, (((PCnt>>3)-1)<>FC_PA_PCNT_POSS); -} - -/** - * @brief Enable FC Information Block - * @note User can program/erase Info. Block page 7 when Flash protect is disable - * @param None - * @retval None - */ -__STATIC_INLINE void md_fc_enable_pa_ifren(void) -{ - MD_FC_SET_BIT(FC, PA, FC_PA_IFREN_MSK); -} - -/** - * @brief Disable FC Information Block - * @param None - * @retval None - */ -__STATIC_INLINE void md_fc_disble_pa_ifren(void) -{ - MD_FC_CLEAR_BIT(FC, PA, FC_PA_IFREN_MSK); -} - -/** - * @brief Is FC Information Block Enabled - * @param None - * @retval The retval can be one of the following values: - * @arg 0x1 : Enable - * @arg 0x0 : Disable - */ -__STATIC_INLINE uint8_t md_fc_is_enabled_pa_ifren(void) -{ - return (MD_FC_READBIT(FC, PA, FC_PA_IFREN_MSK)>>FC_PA_IFREN_POS); -} - -/** - * @brief Set FC Program/Erase Address - * @note Program : PROG_ADDR[15:3] is double word address - * @note Sector Erase : PROG_ADDR[15:10] is page address, and PROG_ADDR[9:0] dont care - * @note Macro Erase : PROG_ADDR[15:0] dont care - * @param @arg Max Value 0xffc0 - * @arg Min Value 0x0 - * @retval None - */ -__STATIC_INLINE void md_fc_set_pa_prog_addr(uint32_t PAddr) -{ - MD_FC_MODIFYREG(FC, PA, FC_PA_PROG_ADDR_MSK, (PAddr<>FC_PA_PROG_ADDR_POSS); -} - -/** - * @brief Set FC Program Low Data - * @note Eflash supports 64 bits data program, this register provides Low 32 bits data - * @param @arg Max Value 0xffffffff - * @arg Min Value 0x0 - * @retval None - */ -__STATIC_INLINE void md_fc_set_pld(uint32_t U32) -{ - MD_FC_WRITEREG(FC, PLD, U32); -} - -/** - * @brief Get FC Program Low Data - * @note Eflash supports 64 bits data program, this register provides Low 32 bits data - * @param None - * @retval The retval can be one of the following values: - * @arg Max Value 0xffffffff - * @arg Min Value 0x0 - */ -__STATIC_INLINE uint32_t md_fc_get_pld(void) -{ - return (MD_FC_READREG(FC, PLD)); -} - -/** - * @brief Set FC Program High Data - * @note Eflash supports 64 bits data program, this register provides high 32 bits data - * @param @arg Max Value 0xffffffff - * @arg Min Value 0x0 - * @retval None - */ -__STATIC_INLINE void md_fc_set_phd(uint32_t U32) -{ - MD_FC_WRITEREG(FC, PHD, U32); -} - -/** - * @brief Get FC Program High Data - * @note Eflash supports 64 bits data program, this register provides high 32 bits data - * @param None - * @retval The retval can be one of the following values: - * @arg Max Value 0xffffffff - * @arg Min Value 0x0 - */ -__STATIC_INLINE uint32_t md_fc_get_phd(void) -{ - return (MD_FC_READREG(FC, PHD)); -} - -/** - * @brief Set FC CON - * @param @arg Max Value 0xffffffff - * @arg Min Value 0x0 - * @retval None - */ -__STATIC_INLINE void md_fc_set_con(uint32_t U32) -{ - MD_FC_WRITEREG(FC, CON, U32); -} - -/** - * @brief Get FC CON - * @param None - * @retval The retval can be one of the following values: - * @arg Max Value 0xffffffff - * @arg Min Value 0x0 - */ -__STATIC_INLINE uint32_t md_fc_get_con(void) -{ - return (MD_FC_READREG(FC, CON)); -} - -/** - * @brief Enable FC Control Sleep - * @note When receive sleep or deep sleep from CPU, controller will mask Eflash control signal when this option is selected. - * @param None - * @retval None - */ -__STATIC_INLINE void md_fc_enable_con_sleep(void) -{ - MD_FC_SET_BIT(FC, CON, FC_CON_SLEEP_MSK); -} - -/** - * @brief Disable FC Control Sleep - * @note When receive sleep or deep sleep from CPU, controller will mask Eflash control signal when this option is selected. - * @param None - * @retval None - */ -__STATIC_INLINE void md_fc_disable_con_sleep(void) -{ - MD_FC_CLEAR_BIT(FC, CON, FC_CON_SLEEP_MSK); -} - -/** - * @brief Is FC Control Sleep Enabled - * @note When receive sleep or deep sleep from CPU, controller will mask Eflash control signal when this option is selected. - * @param None - * @retval The retval can be one of the following values: - * 0x0:Disable Flash sleep mask function - * 0x1:Enable Flash sleep mask function - */ -__STATIC_INLINE uint8_t md_fc_is_enabled_con_sleep(void) -{ - return (MD_FC_READBIT(FC, CON, FC_CON_SLEEP_MSK)>>FC_CON_SLEEP_POS); -} - -/** - * @brief Enable FC Control PreFetch - * @note This function allow user to pre-fetch 64 bits data from Eflash when the last 32bits data in data buffer has been read - * @param None - * @retval None - */ -__STATIC_INLINE void md_fc_enable_con_pfen(void) -{ - MD_FC_SET_BIT(FC, CON, FC_CON_PFEN_MSK); -} - -/** - * @brief Disable FC Control PreFetch - * @note This function allow user to pre-fetch 64 bits data from Eflash when the last 32bits data in data buffer has been read - * @param None - * @retval None - */ -__STATIC_INLINE void md_fc_disable_con_pfen(void) -{ - MD_FC_CLEAR_BIT(FC, CON, FC_CON_PFEN_MSK); -} - -/** - * @brief Is FC Control PreFetch Enabled - * @note This function allow user to pre-fetch 64 bits data from Eflash when the last 32bits data in data buffer has been read - * @param None - * @retval The retval can be one of the following values: - * 0x0:Disable pre-fetch function - * 0x1:Enable pre-fetch function - */ -__STATIC_INLINE uint8_t md_fc_is_enabled_con_pfen(void) -{ - return (MD_FC_READBIT(FC, CON, FC_CON_PFEN_MSK)>>FC_CON_PFEN_POS); -} - -/** - * @brief Set FC Control Wait Cycle - * @note Eflash supports 64 bits data program, this register provides high 32 bits data - * @param @arg Max Value 0x3 - * @arg Min Value 0x0 - * @retval None - */ -__STATIC_INLINE void md_fc_set_con_wait(uint32_t Wait) -{ - MD_FC_MODIFYREG(FC, CON, FC_CON_WAIT_MSK, (Wait<>FC_CON_WAIT_POSS); -} - -/** - * @brief Get FC STAT - * @param None - * @retval The retval can be one of the following values: - * @arg Max Value 0xffffffff - * @arg Min Value 0x0 - */ -__STATIC_INLINE uint32_t md_fc_get_sta(void) -{ - return (MD_FC_READREG(FC, STAT)); -} - -/** - * @brief Get FC Status Option Valid - * @note This bit is set when Option Byte Data is valid - * @param None - * @retval The retval can be one of the following values: - * @arg Max Value 0x1 : Option Byte Data is valid - * @arg Min Value 0x0 : Option Byte Data is invalid - */ -__STATIC_INLINE uint8_t md_fc_get_stat_opvd(void) -{ - return (MD_FC_READBIT(FC, STAT, FC_STAT_OPVD_MSK)>>FC_STAT_OPVD_POS); -} - -/** - * @brief Get FC Status Main Unprotect Level2 Status - * @note This bit is set when Flash main block is unprotect - * @param None - * @retval The retval can be one of the following values: - * @arg Max Value 0x1 : Lv2 Protect Function is disabled - * @arg Min Value 0x0 : Lv2 Protect Function is enabled - */ -__STATIC_INLINE uint8_t md_fc_get_stat_munp2(void) -{ - return (MD_FC_READBIT(FC, STAT, FC_STAT_MUNP2_MSK)>>FC_STAT_MUNP2_POS); -} - -/** - * @brief Get FC Status Main Unprotect Level1 Status - * @note This bit is set when Flash main block is unprotect - * @param None - * @retval The retval can be one of the following values: - * @arg Max Value 0x1 : Lv1 Protect Function is disabled - * @arg Min Value 0x0 : Lv1 Protect Function is enabled - */ -__STATIC_INLINE uint8_t md_fc_get_stat_munp1(void) -{ - return (MD_FC_READBIT(FC, STAT, FC_STAT_MUNP1_MSK)>>FC_STAT_MUNP1_POS); -} - -/** - * @brief Set FC Protect Update Low Data - * @note Update main block Lv2 Protect Page 0 ~ Page 31 - * @param @arg Max Value 0xffffffff - * @arg Min Value 0x0 - * @retval None - */ -__STATIC_INLINE void md_fc_set_upl(uint32_t U32) -{ - MD_FC_WRITEREG(FC, UPL, U32); -} - -/** - * @brief Get FC Protect Update Low Data - * @note Update main block Lv2 Protect Page 0 ~ Page 31 - * @param None - * @retval The retval can be one of the following values: - * @arg Max Value 0xffffffff - * @arg Min Value 0x0 - */ -__STATIC_INLINE uint32_t md_fc_get_upl(void) -{ - return (MD_FC_READREG(FC, UPL)); -} - -/** - * @brief Set FC Protect Update High Data - * @note Update main block Lv2 Protect Page 63 ~ Page 32 - * @param @arg Max Value 0xffffffff - * @arg Min Value 0x0 - * @retval None - */ -__STATIC_INLINE void md_fc_set_uph(uint32_t U32) -{ - MD_FC_WRITEREG(FC, UPH, U32); -} - -/** - * @brief Get FC Protect Update High Data - * @note Update main block Lv2 Protect Page 63 ~ Page 32 - * @param None - * @retval The retval can be one of the following values: - * @arg Max Value 0xffffffff - * @arg Min Value 0x0 - */ -__STATIC_INLINE uint32_t md_fc_get_uph(void) -{ - return (MD_FC_READREG(FC, UPH)); -} - -/** - * @brief Get FC OP_TRIM - * @param None - * @retval The retval can be one of the following values: - * @arg Max Value 0xffffffff - * @arg Min Value 0x0 - */ -__STATIC_INLINE uint32_t md_fc_get_op_trim(void) -{ - return (MD_FC_READREG(FC, OP_TRIM)); -} - -/** - * @brief Get FC OP_TRIM BangGap trim valid - * @param None - * @retval The retval can be one of the following values: - * @arg Max Value 0xff - * @arg Min Value 0x0 - * @arg Value 0xa5 BG Trim is Valid - */ -__STATIC_INLINE uint32_t md_fc_get_op_trim_bgtrimvd(void) -{ - return (MD_FC_READBIT(FC, OP_TRIM, FC_OP_TRIM_BGTRIMVD_MSK)>>FC_OP_TRIM_BGTRIMVD_POSS); -} - -/** - * @brief Get FC Trim BangGap trim value - * @param None - * @retval The retval can be one of the following values: - * @arg Max Value 0xff - * @arg Min Value 0x0 - */ -__STATIC_INLINE uint32_t md_fc_get_op_trim_bgtrim(void) -{ - return (MD_FC_READBIT(FC, OP_TRIM, FC_OP_TRIM_BGTRIM_MSK)>>FC_OP_TRIM_BGTRIM_POSS); -} - -/** - * @brief Get FC Trim HRC calibration value valid - * @param None - * @retval The retval can be one of the following values: - * @arg Max Value 0xff - * @arg Min Value 0x0 - * @arg Value 0xa5 BG Trim is Valid - */ -__STATIC_INLINE uint32_t md_fc_get_op_trim_hrctrimvd(void) -{ - return (MD_FC_READBIT(FC, OP_TRIM, FC_OP_TRIM_HRCTRIMVD_MSK)>>FC_OP_TRIM_HRCTRIMVD_POSS); -} - -/** - * @brief Get FC Trim HRC calibration value - * @param None - * @retval The retval can be one of the following values: - * @arg Max Value 0xff - * @arg Min Value 0x0 - */ -__STATIC_INLINE uint32_t md_fc_get_op_trim_hrctrim(void) -{ - return (MD_FC_READBIT(FC, OP_TRIM, FC_OP_TRIM_HRCTRIM_MSK)>>FC_OP_TRIM_HRCTRIM_POSS); -} - -/** - * @brief Get FC Lv2 Protect Low 32 bits - * @note Lv2 Protect Page 0 ~ Page 31.The Bit is set to 0 when the page is protected - * @param None - * @retval The retval can be one of the following values: - * @arg Max Value 0xffffffff - * @arg Min Value 0x0 - */ -__STATIC_INLINE uint32_t md_fc_get_op_prt2l(void) -{ - return (MD_FC_READREG(FC, OP_PRT2L)); -} - -/** - * @brief Get FC Lv2 Protect High 32 bits - * @note Lv2 Protect Page 63 ~ Page 32.The Bit is set to 0 when the page is protected - * @param None - * @retval The retval can be one of the following values: - * @arg Max Value 0xffffffff - * @arg Min Value 0x0 - */ -__STATIC_INLINE uint32_t md_fc_get_op_prt2h(void) -{ - return (MD_FC_READREG(FC, OP_PRT2H)); -} - -/** - * @brief Get FC Lv1 Protect Low 32 bits - * @note Lv1 Protect Page 0 ~ Page 31.The Bit is set to 0 when the page is protected - * @param None - * @retval The retval can be one of the following values: - * @arg Max Value 0xffffffff - * @arg Min Value 0x0 - */ -__STATIC_INLINE uint32_t md_fc_get_op_prt1l(void) -{ - return (MD_FC_READREG(FC, OP_PRT1L)); -} - -/** - * @brief Get FC Lv1 Protect High 32 bits - * @note Lv1 Protect Page 63 ~ Page 32.The Bit is set to 0 when the page is protected - * @param None - * @retval The retval can be one of the following values: - * @arg Max Value 0xffffffff - * @arg Min Value 0x0 - */ -__STATIC_INLINE uint32_t md_fc_get_op_prt1h(void) -{ - return (MD_FC_READREG(FC, OP_PRT1H)); -} - -/** - * @brief Get FC OP_REMAP - * @param None - * @retval The retval can be one of the following values: - * @arg Max Value 0xffffffff - * @arg Min Value 0x0 - */ -__STATIC_INLINE uint32_t md_fc_get_op_remap(void) -{ - return (MD_FC_READREG(FC, OP_REMAP)); -} - -/** - * @brief Get FC Hardware Remap Option - * @param None - * @retval The retval can be one of the following values: - * @arg Max Value 0xff - * @arg Min Value 0x0 - * @arg Value 0xa5 skip boot loader - */ -__STATIC_INLINE uint8_t md_fc_get_op_remap_hremap(void) -{ - return (MD_FC_READBIT(FC, OP_REMAP, FC_OP_REMAP_HREMAP_MSK)>>FC_OP_REMAP_HREMAP_POSS); -} - -/** - * @brief Get FC Software Remap Option - * @param None - * @retval The retval can be one of the following values: - * @arg @ref MD_FC_PC_SREMAP_MAIN(0x0) : Main Flash memory mapped at 0x0000 0000 - * @arg @ref MD_FC_PC_SREMAP_SYSTEM(0x1) : System Flash memory mapped at 0x0000 0000 - * @arg @ref MD_FC_PC_SREMAP_SRAM(0x2) : SRAM mapped at 0x0000 0000 - * @arg Else : Reserved - */ -__STATIC_INLINE uint8_t md_fc_get_op_remap_sremap(void) -{ - return (MD_FC_READBIT(FC, OP_REMAP, FC_OP_REMAP_SREMAP_MSK)>>FC_OP_REMAP_SREMAP_POSS); -} - -/** - * @brief Get FC Software Remap Base Address Settng Data - * @note If set 0x1, it means second 4k Byte, If set 0x2, it means third 4k Byte, and so on - * @param None - * @retval The retval can be one of the following values: - * @arg Max Value 0xf - * @arg Min Value 0x0 - * @note This value is invalid if the value in SREMAP field is 0x3 - */ -__STATIC_INLINE uint8_t md_fc_get_op_remap_sefbase(void) -{ - return (MD_FC_READBIT(FC, OP_REMAP, FC_OP_REMAP_SEFBASE_MSK)>>FC_OP_REMAP_SEFBASE_POSS); -} - -/** - * @} MD_FC_Macro_Drivers - */ - -/** - * @} MD_FC_Public_Macros - */ - -/* Public functions -----------------------------------------------------------*/ -/** @defgroup MD_FC_Public_Functions FC Public Functions - * @{ - */ -ErrorStatus md_fc_merase(uint32_t MEraseID); -ErrorStatus md_fc_serase(md_fc_ControlTypeDef *pSErasePara); -ErrorStatus md_fc_program(md_fc_ControlTypeDef *pProgramPara); -ErrorStatus md_fc_read(md_fc_ControlTypeDef *pReadPara); -ErrorStatus md_fc_updprotl1(md_fc_UpdProtTypeDef *pUpdPL1Para); -ErrorStatus md_fc_updprotl2(md_fc_UpdProtTypeDef *pUpdPL2Para); -ErrorStatus md_fc_updremap(uint8_t UpdRemap); -/** - * @} MD_FC_Public_Functions - */ - -#endif - -/** - * @} FC - */ - -/** - * @} Micro_Driver - */ - -#ifdef __cplusplus -} -#endif - -#endif - -/******************* (C) COPYRIGHT Eastsoft Microelectronics *****END OF FILE****/ - diff --git a/bsp/essemi/es32f0271/libraries/ES32F027x_MD_StdPeriph_Driver/Include/md_gpio.h b/bsp/essemi/es32f0271/libraries/ES32F027x_MD_StdPeriph_Driver/Include/md_gpio.h deleted file mode 100644 index a096fa7a01..0000000000 --- a/bsp/essemi/es32f0271/libraries/ES32F027x_MD_StdPeriph_Driver/Include/md_gpio.h +++ /dev/null @@ -1,2873 +0,0 @@ -/** - ****************************************************************************** - * @file md_GPIO.h - * @brief ES32F0271 GPIO HEAD File. - * - * @version V1.00.02 - * @date 30/11/2018 - * @author Eastsoft AE Team - * @note - * detailed description - * - * Copyright (C) 2018 Shanghai Eastsoft Microelectronics Co., Ltd. ALL rights reserved. - ******************************************************************************* - */ - - -/* Define to prevent recursive inclusion -------------------------------------*/ -#ifndef __MD_GPIO_H__ -#define __MD_GPIO_H__ - -#ifdef __cplusplus -extern "C" { -#endif - -/* Includes -------------------------------------------------------------------*/ -#include "es32f0271.h" -#include "reg_gpio.h" - -/** @addtogroup Micro_Driver - * @{ - */ - -#if defined (GPIOA) || defined (GPIOB) || defined (GPIOC) || defined (GPIOD) - -/** @defgroup GPIO GPIO - * @brief GPIO micro driver - * @{ - */ - -/* Private types --------------------------------------------------------------*/ -/* Private variables ----------------------------------------------------------*/ -/* Private constants ----------------------------------------------------------*/ -/* Private macros -------------------------------------------------------------*/ - -/* Public types ---------------------------------------------------------------*/ -/** @defgroup MD_GPIO_PT_INIT GPIO Public Init structures - * @{ - */ - -/** - * @brief MD GPIO Init Structure definition - */ -typedef struct -{ - uint32_t Pin; /*!< Specifies the GPIO pins to be configured. - This parameter can be any value of @ref MD_GPIO_PC_PIN */ - - uint32_t Mode; /*!< Specifies the operating mode for the selected pins. - This parameter can be a value of @ref MD_GPIO_PC_MODE. - - GPIO HW configuration can be modified afterwards using unitary function @ref md_gpio_set_mode().*/ - - uint32_t OutputType; /*!< Specifies the operating output type for the selected pins. - This parameter can be a value of @ref MD_GPIO_PC_OT. - - GPIO HW configuration can be modified afterwards using unitary function @ref md_gpio_set_output_type().*/ - - - uint32_t Pull; /*!< Specifies the operating Pull-up/Pull down for the selected pins. - This parameter can be a value of @ref MD_GPIO_PC_PULL. - - GPIO HW configuration can be modified afterwards using unitary function @ref md_gpio_set_pull().*/ - - uint32_t OutDrive; /*!< Specifies the output driving current for the selected pins. - This parameter can be a value of @ref MD_GPIO_PC_DS. - - GPIO HW configuration can be modified afterwards using unitary function @ref md_gpio_get_ds().*/ - - uint32_t Function; /*!< Specifies the Peripheral to be connected to the selected pins. - This parameter can be a value of @ref MD_GPIO_PC_FUNCTION. - - GPIO HW configuration can be modified afterwards using unitary function @ref md_gpio_set_function0_7() and md_gpio_set_function8_15().*/ -} md_gpio_inittypedef; - -/** - * @} MD_GPIO_PT_INIT - */ - -/* Public constants -----------------------------------------------------------*/ -/** @defgroup MD_GPIO_Public_Constants GPIO Public Constants - * @{ - */ - -/** @defgroup MD_GPIO_PC_PIN PIN - * @{ - */ -#define MD_GPIO_PIN_0 (0X1<<0) /*!< Select pin 0 */ -#define MD_GPIO_PIN_1 (0X1<<1) /*!< Select pin 1 */ -#define MD_GPIO_PIN_2 (0X1<<2) /*!< Select pin 2 */ -#define MD_GPIO_PIN_3 (0X1<<3) /*!< Select pin 3 */ -#define MD_GPIO_PIN_4 (0X1<<4) /*!< Select pin 4 */ -#define MD_GPIO_PIN_5 (0X1<<5) /*!< Select pin 5 */ -#define MD_GPIO_PIN_6 (0X1<<6) /*!< Select pin 6 */ -#define MD_GPIO_PIN_7 (0X1<<7) /*!< Select pin 7 */ -#define MD_GPIO_PIN_8 (0X1<<8) /*!< Select pin 8 */ -#define MD_GPIO_PIN_9 (0X1<<9) /*!< Select pin 9 */ -#define MD_GPIO_PIN_10 (0X1<<10) /*!< Select pin 10 */ -#define MD_GPIO_PIN_11 (0X1<<11) /*!< Select pin 11 */ -#define MD_GPIO_PIN_12 (0X1<<12) /*!< Select pin 12 */ -#define MD_GPIO_PIN_13 (0X1<<13) /*!< Select pin 13 */ -#define MD_GPIO_PIN_14 (0X1<<14) /*!< Select pin 14 */ -#define MD_GPIO_PIN_15 (0X1<<15) /*!< Select pin 15 */ -#define MD_GPIO_PIN_ALL (MD_GPIO_PIN_0 | MD_GPIO_PIN_1 | MD_GPIO_PIN_2 | \ - MD_GPIO_PIN_3 | MD_GPIO_PIN_4 | MD_GPIO_PIN_5 | \ - MD_GPIO_PIN_6 | MD_GPIO_PIN_7 | MD_GPIO_PIN_8 | \ - MD_GPIO_PIN_9 | MD_GPIO_PIN_10 | MD_GPIO_PIN_11 | \ - MD_GPIO_PIN_12 | MD_GPIO_PIN_13 | MD_GPIO_PIN_14 | \ - MD_GPIO_PIN_15) /*!< Select all pins */ -/** - * @} MD_GPIO_PC_PIN - */ - -/** @defgroup MD_GPIO_PC_MODE Mode - * @{ - */ -#define MD_GPIO_MODE_INPUT (0x00000000UL) /** @brief Select input mode */ -#define MD_GPIO_MODE_OUTPUT (0X00000001UL) /** @brief Select output mode */ -#define MD_GPIO_MODE_FUNCTION (0X00000002UL) /** @brief Select function mode */ -#define MD_GPIO_MODE_ANALOG (0x00000003UL) /** @brief Select analog mode */ -/** - * @} MD_GPIO_PC_MODE - */ - -/** @defgroup MD_GPIO_PC_OT Output Type - * @{ - */ -#define MD_GPIO_OUTPUT_PUSHPULL (0x00000000U) /** @brief Select push-pull as output type */ -#define MD_GPIO_OUTPUT_OPENDRAIN (0x00000001U) /** @brief Select open-drain as output type */ -/** - * @} MD_GPIO_PC_OT - */ - -/** @defgroup MD_GPIO_PC_PULL Pull Up Pull Down - * @{ - */ -#define MD_GPIO_PULL_FLOATING (0x00000000UL) /** @brief Select I/O no pull */ -#define MD_GPIO_PULL_UP (0x00000001UL) /** @brief Select I/O pull up */ -#define MD_GPIO_PULL_DOWN (0x00000002UL) /** @brief Select I/O pull down */ -/** - * @} MD_GPIO_PC_PULL - */ - -/** @defgroup MD_GPIO_PC_DS Output driving/sinking current - * @{ - */ -#define MD_GPIO_DS_16mA (0x00000001U) /** @brief Select I/O 16mA driving/sinking current */ -#define MD_GPIO_DS_8mA (0x00000000U) /** @brief Select I/O 8mA driving/sinking current */ -/** - * @} MD_GPIO_PC_DS - */ - -/** @defgroup MD_GPIO_PC_FUNCTION Alternate Function - * @{ - */ -#define MD_GPIO_AF0 (0x00000000UL) /** @brief Select alternate function 0 */ -#define MD_GPIO_AF1 (0x00000001UL) /** @brief Select alternate function 1 */ -#define MD_GPIO_AF2 (0x00000002UL) /** @brief Select alternate function 2 */ -#define MD_GPIO_AF3 (0x00000003UL) /** @brief Select alternate function 3 */ -#define MD_GPIO_AF4 (0x00000004UL) /** @brief Select alternate function 4 */ -#define MD_GPIO_AF5 (0x00000005UL) /** @brief Select alternate function 5 */ -#define MD_GPIO_AF6 (0x00000006UL) /** @brief Select alternate function 6 */ -#define MD_GPIO_AF7 (0x00000007UL) /** @brief Select alternate function 7 */ -#define MD_GPIO_AF8 (0x00000008UL) /** @brief Select alternate function 8 */ -/** - * @} MD_GPIO_PC_FUNCTION - */ - -/** @defgroup MD_GPIO_PC_FILTER Input Filter - * @{ - */ -#define MD_GPIO_FILTER_BYPASS (0x00000000UL) /** @brief Select bypass */ -#define MD_GPIO_FILTER_GLITCH (0x00000001UL) /** @brief Select glitch free for 20ns plus */ -/** - * @} MD_GPIO_PC_FILTER - */ - -/** @defgroup MD_GPIO_PC_IST Input Schmitt Trigger - * @{ - */ -#define MD_GPIO_IST_TTL (0x00000000UL) /** @brief Select TTL IO Level */ -#define MD_GPIO_IST_CMOS (0x00000001UL) /** @brief Select CMOS IO Level */ -/** - * @} MD_GPIO_PC_IST - */ - -/** @defgroup MD_GPIO_ODATA_SEL GPIO Output Select - * @{ - */ -#define MD_GPIO_OUTPUT_LOW (0x00000000UL) /** @brief Select GPIO Output Low*/ -#define MD_GPIO_OUTPUT_HIGH (0x00000001UL) /** @brief Select GPIO Output High*/ -/** - * @} MD_GPIO_ODATA_SEL - */ - -/** - * @} MD_GPIO_Public_Constants - */ - -/* Public macro ---------------------------------------------------------------*/ -/** @defgroup MD_GPIO_Public_Macros GPIO Public Macros - * @{ - */ - -/** @defgroup MD_GPIO_MOD_MOD15 MOD15 - * @brief Set MOD15 configure I/O mode bit for md_gpio_set_mod() function used - * @param mod15 This parameter can be one of the following values: - * @arg @ref MD_GPIO_MODE_INPUT - * @arg @ref MD_GPIO_MODE_OUTPUT - * @arg @ref MD_GPIO_MODE_FUNCTION - * @arg @ref MD_GPIO_MODE_ANALOG - * @{ - */ -#define md_gpio_set_mod_mod15_fun(mod15) (mod15<MOD, (mod15|mod14|mod13|mod12|mod11|mod10|mod9|mod8|mod7|mod6|mod5|mod4|mod3|mod2|mod1|mod0)); -} - - - - -/** - * @brief Configure gpio mode for a dedicated pin on dedicated port. - * @note I/O mode can be Input mode, output mode, Alternate function mode, or Analog mode. - * @note Warning: only one pin can be passed as parameter. - * @param GPIOx GPIO Port - * @param Pin This parameter can be one of the following values: - * @arg @ref MD_GPIO_PIN_0 - * @arg @ref MD_GPIO_PIN_1 - * @arg @ref MD_GPIO_PIN_2 - * @arg @ref MD_GPIO_PIN_3 - * @arg @ref MD_GPIO_PIN_4 - * @arg @ref MD_GPIO_PIN_5 - * @arg @ref MD_GPIO_PIN_6 - * @arg @ref MD_GPIO_PIN_7 - * @arg @ref MD_GPIO_PIN_8 - * @arg @ref MD_GPIO_PIN_9 - * @arg @ref MD_GPIO_PIN_10 - * @arg @ref MD_GPIO_PIN_11 - * @arg @ref MD_GPIO_PIN_12 - * @arg @ref MD_GPIO_PIN_13 - * @arg @ref MD_GPIO_PIN_14 - * @arg @ref MD_GPIO_PIN_15 - * @param Mode This parameter can be one of the following values: - * @arg @ref MD_GPIO_MODE_INPUT - * @arg @ref MD_GPIO_MODE_OUTPUT - * @arg @ref MD_GPIO_MODE_FUNCTION - * @arg @ref MD_GPIO_MODE_ANALOG - * @retval None - */ -__STATIC_INLINE void md_gpio_set_mode(GPIO_TypeDef *GPIOx, uint32_t Pin, uint32_t Mode) -{ - MODIFY_REG(GPIOx->MOD, (GPIO_MOD_MOD0_MSK << (POSITION_VAL(Pin) * 2U)), (Mode << (POSITION_VAL(Pin) * 2U))); -} - -/** - * @brief Return gpio mode for a dedicated pin on dedicated port. - * @note I/O mode can be Input mode, output mode, Alternate function mode, or Analog mode. - * @note Warning: only one pin can be passed as parameter. - * @param GPIOx GPIO Port - * @param Pin This parameter can be one of the following values: - * @arg @ref MD_GPIO_PIN_0 - * @arg @ref MD_GPIO_PIN_1 - * @arg @ref MD_GPIO_PIN_2 - * @arg @ref MD_GPIO_PIN_3 - * @arg @ref MD_GPIO_PIN_4 - * @arg @ref MD_GPIO_PIN_5 - * @arg @ref MD_GPIO_PIN_6 - * @arg @ref MD_GPIO_PIN_7 - * @arg @ref MD_GPIO_PIN_8 - * @arg @ref MD_GPIO_PIN_9 - * @arg @ref MD_GPIO_PIN_10 - * @arg @ref MD_GPIO_PIN_11 - * @arg @ref MD_GPIO_PIN_12 - * @arg @ref MD_GPIO_PIN_13 - * @arg @ref MD_GPIO_PIN_14 - * @retval Returned value can be one of the following values: - * @arg @ref MD_GPIO_MODE_INPUT - * @arg @ref MD_GPIO_MODE_OUTPUT - * @arg @ref MD_GPIO_MODE_FUNCTION - * @arg @ref MD_GPIO_MODE_ANALOG - */ -__STATIC_INLINE uint32_t md_gpio_get_mode(GPIO_TypeDef *GPIOx, uint32_t Pin) -{ - return (uint32_t)(READ_BIT(GPIOx->MOD, - (GPIO_MOD_MOD0_MSK << (POSITION_VAL(Pin) * 2U))) >> (POSITION_VAL(Pin) * 2U)); -} - -/** @defgroup MD_GPIO_OT_OT15 OT15 - * @brief Set OT15 output data bit for md_gpio_set_ot() function used - * @param ot15 This parameter can be one of the following values: - * @arg @ref MD_GPIO_OUTPUT_PUSHPULL - * @arg @ref MD_GPIO_OUTPUT_OPENDRAIN - * @{ - */ -#define md_gpio_set_ot_ot15_fun(ot15) (ot15<OT, (ot15|ot14|ot13|ot12|ot11|ot10|ot9|ot8|ot7|ot6|ot5|ot4|ot3|ot2|ot1|ot0)); -} - - -/** - * @brief Configure gpio output type for several pins on dedicated port. - * @note Output type as to be set when gpio pin is in output or - * alternate modes. Possible type are Push-pull or Open-drain. - * @param GPIOx GPIO Port - * @param Pin This parameter can be a combination of the following values: - * @arg @ref MD_GPIO_PIN_0 - * @arg @ref MD_GPIO_PIN_1 - * @arg @ref MD_GPIO_PIN_2 - * @arg @ref MD_GPIO_PIN_3 - * @arg @ref MD_GPIO_PIN_4 - * @arg @ref MD_GPIO_PIN_5 - * @arg @ref MD_GPIO_PIN_6 - * @arg @ref MD_GPIO_PIN_7 - * @arg @ref MD_GPIO_PIN_8 - * @arg @ref MD_GPIO_PIN_9 - * @arg @ref MD_GPIO_PIN_10 - * @arg @ref MD_GPIO_PIN_11 - * @arg @ref MD_GPIO_PIN_12 - * @arg @ref MD_GPIO_PIN_13 - * @arg @ref MD_GPIO_PIN_14 - * @arg @ref MD_GPIO_PIN_15 - * @param OutputType This parameter can be one of the following values: - * @arg @ref MD_GPIO_OUTPUT_PUSHPULL - * @arg @ref MD_GPIO_OUTPUT_OPENDRAIN - * @retval None - */ -__STATIC_INLINE void md_gpio_set_output_type(GPIO_TypeDef *GPIOx, uint32_t Pin, uint32_t OutputType) -{ - MODIFY_REG(GPIOx->OT, (GPIO_OT_OT0_MSK << (POSITION_VAL(Pin))), (OutputType << (POSITION_VAL(Pin)))); -} - -/** - * @brief Return gpio output type for several pins on dedicated port. - * @note Output type as to be set when gpio pin is in output or - * alternate modes. Possible type are Push-pull or Open-drain. - * @param GPIOx GPIO Port - * @param Pin This parameter can be one of the following values: - * @arg @ref MD_GPIO_PIN_0 - * @arg @ref MD_GPIO_PIN_1 - * @arg @ref MD_GPIO_PIN_2 - * @arg @ref MD_GPIO_PIN_3 - * @arg @ref MD_GPIO_PIN_4 - * @arg @ref MD_GPIO_PIN_5 - * @arg @ref MD_GPIO_PIN_6 - * @arg @ref MD_GPIO_PIN_7 - * @arg @ref MD_GPIO_PIN_8 - * @arg @ref MD_GPIO_PIN_9 - * @arg @ref MD_GPIO_PIN_10 - * @arg @ref MD_GPIO_PIN_11 - * @arg @ref MD_GPIO_PIN_12 - * @arg @ref MD_GPIO_PIN_13 - * @arg @ref MD_GPIO_PIN_14 - * @arg @ref MD_GPIO_PIN_15 - * @retval Returned value can be one of the following values: - * @arg @ref MD_GPIO_OUTPUT_PUSHPULL - * @arg @ref MD_GPIO_OUTPUT_OPENDRAIN - */ -__STATIC_INLINE uint32_t md_gpio_get_output_type(GPIO_TypeDef *GPIOx, uint32_t Pin) -{ - return (uint32_t)((READ_BIT(GPIOx->OT, - (GPIO_OT_OT_MSK << (POSITION_VAL(Pin)))) >> (POSITION_VAL(Pin))) & (0x1U)); -} - - -/** @defgroup MD_GPIO_PUD_PUD15 PUD15 - * @brief Set PUD15 I/O pull-up or pull-down bit for md_gpio_set_pud() function used - * @param pud15 This parameter can be one of the following values: - * @arg @ref MD_GPIO_PULL_FLOATING - * @arg @ref MD_GPIO_PULL_UP - * @arg @ref MD_GPIO_PULL_DOWN - * @{ - */ -#define md_gpio_set_pud_pud15_fun(pud15) (pud15<PUD, (pud15|pud14|pud13|pud12|pud11|pud10|pud9|pud8|pud7|pud6|pud5|pud4|pud3|pud2|pud1|pud0)); -} - -/** - * @brief Configure gpio pull-up or pull-down for a dedicated pin on a dedicated port. - * @note Warning: only one pin can be passed as parameter. - * @param GPIOx GPIO Port - * @param Pin This parameter can be one of the following values: - * @arg @ref MD_GPIO_PIN_0 - * @arg @ref MD_GPIO_PIN_1 - * @arg @ref MD_GPIO_PIN_2 - * @arg @ref MD_GPIO_PIN_3 - * @arg @ref MD_GPIO_PIN_4 - * @arg @ref MD_GPIO_PIN_5 - * @arg @ref MD_GPIO_PIN_6 - * @arg @ref MD_GPIO_PIN_7 - * @arg @ref MD_GPIO_PIN_8 - * @arg @ref MD_GPIO_PIN_9 - * @arg @ref MD_GPIO_PIN_10 - * @arg @ref MD_GPIO_PIN_11 - * @arg @ref MD_GPIO_PIN_12 - * @arg @ref MD_GPIO_PIN_13 - * @arg @ref MD_GPIO_PIN_14 - * @arg @ref MD_GPIO_PIN_15 - * @param Pull This parameter can be one of the following values: - * @arg @ref MD_GPIO_PULL_FLOATING - * @arg @ref MD_GPIO_PULL_UP - * @arg @ref MD_GPIO_PULL_DOWN - * @retval None - */ -__STATIC_INLINE void md_gpio_set_pull(GPIO_TypeDef *GPIOx, uint32_t Pin, uint32_t Pull) -{ - MODIFY_REG(GPIOx->PUD, (GPIO_PUD_PUD0_MSK << (POSITION_VAL(Pin) * 2U)), (Pull << (POSITION_VAL(Pin) * 2U))); -} - -/** - * @brief Return gpio pull-up or pull-down for a dedicated pin on a dedicated port - * @note Warning: only one pin can be passed as parameter. - * @param GPIOx GPIO Port - * @param Pin This parameter can be one of the following values: - * @arg @ref MD_GPIO_PIN_0 - * @arg @ref MD_GPIO_PIN_1 - * @arg @ref MD_GPIO_PIN_2 - * @arg @ref MD_GPIO_PIN_3 - * @arg @ref MD_GPIO_PIN_4 - * @arg @ref MD_GPIO_PIN_5 - * @arg @ref MD_GPIO_PIN_6 - * @arg @ref MD_GPIO_PIN_7 - * @arg @ref MD_GPIO_PIN_8 - * @arg @ref MD_GPIO_PIN_9 - * @arg @ref MD_GPIO_PIN_10 - * @arg @ref MD_GPIO_PIN_11 - * @arg @ref MD_GPIO_PIN_12 - * @arg @ref MD_GPIO_PIN_13 - * @arg @ref MD_GPIO_PIN_14 - * @arg @ref MD_GPIO_PIN_15 - * @retval Returned value can be one of the following values: - * @arg @ref MD_GPIO_PULL_FLOATING - * @arg @ref MD_GPIO_PULL_UP - * @arg @ref MD_GPIO_PULL_DOWN - */ -__STATIC_INLINE uint32_t md_gpio_get_pull(GPIO_TypeDef *GPIOx, uint32_t Pin) -{ - return (uint32_t)(READ_BIT(GPIOx->PUD, - (GPIO_PUD_PUD0_MSK << (POSITION_VAL(Pin) * 2U))) >> (POSITION_VAL(Pin) * 2U)); -} - - -/** @defgroup MD_GPIO_DS_DS15 DS15 - * @brief Set DS15 I/O Driving/Sinking current bit for md_gpio_set_ds() function used - * @param ds15 This parameter can be one of the following values: - * @arg @ref MD_GPIO_DS_8mA - * @arg @ref MD_GPIO_DS_16mA - * @{ - */ -#define md_gpio_set_ds_ds15_fun(ds15) (ds15<DS, (ds15|ds14|ds13|ds12|ds11|ds10|ds9|ds8|ds7|ds6|ds5|ds4|ds3|ds2|ds1|ds0)); -} - - -/** - * @brief Configure gpio output driving/sinking current a dedicated pin on a dedicated port. - * @note Warning: only one pin can be passed as parameter. - * @param GPIOx GPIO Port - * @param Pin This parameter can be one of the following values: - * @arg @ref MD_GPIO_PIN_0 - * @arg @ref MD_GPIO_PIN_1 - * @arg @ref MD_GPIO_PIN_2 - * @arg @ref MD_GPIO_PIN_3 - * @arg @ref MD_GPIO_PIN_4 - * @arg @ref MD_GPIO_PIN_5 - * @arg @ref MD_GPIO_PIN_6 - * @arg @ref MD_GPIO_PIN_7 - * @arg @ref MD_GPIO_PIN_8 - * @arg @ref MD_GPIO_PIN_9 - * @arg @ref MD_GPIO_PIN_10 - * @arg @ref MD_GPIO_PIN_11 - * @arg @ref MD_GPIO_PIN_12 - * @arg @ref MD_GPIO_PIN_13 - * @arg @ref MD_GPIO_PIN_14 - * @arg @ref MD_GPIO_PIN_15 - * @param Odrv This parameter can be one of the following values: - * @arg @ref MD_GPIO_DS_8mA - * @arg @ref MD_GPIO_DS_16mA - * @retval None - */ -__STATIC_INLINE void md_gpio_set_ds(GPIO_TypeDef *GPIOx, uint32_t Pin, uint32_t Odrv) -{ - MODIFY_REG(GPIOx->DS, (GPIO_DS_DS_MSK << (POSITION_VAL(Pin))), (Odrv << (POSITION_VAL(Pin)))); -} - -/** - * @brief Return gpio output driving/sinking current a dedicated pin on a dedicated port. - * @param GPIOx GPIO Port - * @param Pin This parameter can be one of the following values: - * @arg @ref MD_GPIO_PIN_0 - * @arg @ref MD_GPIO_PIN_1 - * @arg @ref MD_GPIO_PIN_2 - * @arg @ref MD_GPIO_PIN_3 - * @arg @ref MD_GPIO_PIN_4 - * @arg @ref MD_GPIO_PIN_5 - * @arg @ref MD_GPIO_PIN_6 - * @arg @ref MD_GPIO_PIN_7 - * @arg @ref MD_GPIO_PIN_8 - * @arg @ref MD_GPIO_PIN_9 - * @arg @ref MD_GPIO_PIN_10 - * @arg @ref MD_GPIO_PIN_11 - * @arg @ref MD_GPIO_PIN_12 - * @arg @ref MD_GPIO_PIN_13 - * @arg @ref MD_GPIO_PIN_14 - * @arg @ref MD_GPIO_PIN_15 - * @retval Returned value can be one of the following values: - * @arg @ref MD_GPIO_DS_8mA - * @arg @ref MD_GPIO_DS_16mA - */ -__STATIC_INLINE uint32_t md_gpio_get_ds(GPIO_TypeDef *GPIOx, uint32_t Pin) -{ - return (uint32_t)(READ_BIT(GPIOx->DS, - (GPIO_DS_DS_MSK << (POSITION_VAL(Pin)))) >> (POSITION_VAL(Pin))); -} - -/** @defgroup MD_GPIO_AFL_AF0 AF0 - * @brief Set AF0 Alternate function selection bit for md_gpio_set_afl() function used - * @param af0 This parameter can be one of the following values: - * @arg @ref MD_GPIO_AF0 - * @arg @ref MD_GPIO_AF1 - * @arg @ref MD_GPIO_AF2 - * @arg @ref MD_GPIO_AF3 - * @arg @ref MD_GPIO_AF4 - * @arg @ref MD_GPIO_AF5 - * @arg @ref MD_GPIO_AF6 - * @arg @ref MD_GPIO_AF7 - * @{ - */ -#define md_gpio_set_afl_af0_fun(af0) (af0<AFL, (af7|af6|af5|af4|af3|af2|af1|af0)); -} - -/** - * @brief Configure gpio alternate function of a dedicated pin from 0 to 7 for a dedicated port. - * @note Possible values are from FUNCTION0 to FUNCTION7 depending on target. - * @note Warning: only one pin can be passed as parameter. - * @param GPIOx GPIO Port - * @param Pin This parameter can be one of the following values: - * @arg @ref MD_GPIO_PIN_0 - * @arg @ref MD_GPIO_PIN_1 - * @arg @ref MD_GPIO_PIN_2 - * @arg @ref MD_GPIO_PIN_3 - * @arg @ref MD_GPIO_PIN_4 - * @arg @ref MD_GPIO_PIN_5 - * @arg @ref MD_GPIO_PIN_6 - * @arg @ref MD_GPIO_PIN_7 - * @param Function This parameter can be one of the following values: - * @arg @ref MD_GPIO_AF0 - * @arg @ref MD_GPIO_AF1 - * @arg @ref MD_GPIO_AF2 - * @arg @ref MD_GPIO_AF3 - * @arg @ref MD_GPIO_AF4 - * @arg @ref MD_GPIO_AF5 - * @arg @ref MD_GPIO_AF6 - * @arg @ref MD_GPIO_AF7 - * @retval None - */ -__STATIC_INLINE void md_gpio_set_function0_7(GPIO_TypeDef *GPIOx, uint32_t Pin, uint32_t Function) -{ - MODIFY_REG(GPIOx->AFL, (GPIO_AFL_AF0_MSK << (POSITION_VAL(Pin) * 4U)), - (Function << (POSITION_VAL(Pin) * 4U))); -} - -/** - * @brief Return gpio alternate function of a dedicated pin from 0 to 7 for a dedicated port. - * @param GPIOx GPIO Port - * @param Pin This parameter can be one of the following values: - * @arg @ref MD_GPIO_PIN_0 - * @arg @ref MD_GPIO_PIN_1 - * @arg @ref MD_GPIO_PIN_2 - * @arg @ref MD_GPIO_PIN_3 - * @arg @ref MD_GPIO_PIN_4 - * @arg @ref MD_GPIO_PIN_5 - * @arg @ref MD_GPIO_PIN_6 - * @arg @ref MD_GPIO_PIN_7 - * @retval Returned value can be one of the following values: - * @arg @ref MD_GPIO_AF0 - * @arg @ref MD_GPIO_AF1 - * @arg @ref MD_GPIO_AF2 - * @arg @ref MD_GPIO_AF3 - * @arg @ref MD_GPIO_AF4 - * @arg @ref MD_GPIO_AF5 - * @arg @ref MD_GPIO_AF6 - * @arg @ref MD_GPIO_AF7 - */ -__STATIC_INLINE uint32_t md_gpio_get_function0_7(GPIO_TypeDef *GPIOx, uint32_t Pin) -{ - return (uint32_t)(READ_BIT(GPIOx->AFL, - (GPIO_AFL_AF0_MSK << (POSITION_VAL(Pin) * 4U))) >> (POSITION_VAL(Pin) * 4U)); -} - - -/** @defgroup MD_GPIO_AFH_AF8 AF8 - * @brief Set AF8 Alternate function selection bit for md_gpio_set_afh() function used - * @param af8 This parameter can be one of the following values: - * @arg @ref MD_GPIO_AF0 - * @arg @ref MD_GPIO_AF1 - * @arg @ref MD_GPIO_AF2 - * @arg @ref MD_GPIO_AF3 - * @arg @ref MD_GPIO_AF4 - * @arg @ref MD_GPIO_AF5 - * @arg @ref MD_GPIO_AF6 - * @arg @ref MD_GPIO_AF7 - * @{ - */ -#define md_gpio_set_afh_af8_fun(af8) (af8<AFH, (af15|af14|af13|af12|af11|af10|af9|af8)); -} - -/** - * @brief Configure gpio alternate function of a dedicated pin from 8 to 15 for a dedicated port. - * @note Possible values are from FUNCTION0 to FUNCTION7 depending on target. - * @note Warning: only one pin can be passed as parameter. - * @param GPIOx GPIO Port - * @param Pin This parameter can be one of the following values: - * @arg @ref MD_GPIO_PIN_8 - * @arg @ref MD_GPIO_PIN_9 - * @arg @ref MD_GPIO_PIN_10 - * @arg @ref MD_GPIO_PIN_11 - * @arg @ref MD_GPIO_PIN_12 - * @arg @ref MD_GPIO_PIN_13 - * @arg @ref MD_GPIO_PIN_14 - * @arg @ref MD_GPIO_PIN_15 - * @param Function This parameter can be one of the following values: - * @arg @ref MD_GPIO_AF0 - * @arg @ref MD_GPIO_AF1 - * @arg @ref MD_GPIO_AF2 - * @arg @ref MD_GPIO_AF3 - * @arg @ref MD_GPIO_AF4 - * @arg @ref MD_GPIO_AF5 - * @arg @ref MD_GPIO_AF6 - * @arg @ref MD_GPIO_AF7 - * @retval None - */ -__STATIC_INLINE void md_gpio_set_function8_15(GPIO_TypeDef *GPIOx, uint32_t Pin, uint32_t Function) -{ - MODIFY_REG(GPIOx->AFH, (GPIO_AFH_AF8_MSK << (POSITION_VAL(Pin >> 8U) * 4U)), - (Function << (POSITION_VAL(Pin >> 8U) * 4U))); -} - -/** - * @brief Return gpio alternate function of a dedicated pin from 0 to 7 for a dedicated port. - * @param GPIOx GPIO Port - * @param Pin This parameter can be one of the following values: - * @arg @ref MD_GPIO_PIN_8 - * @arg @ref MD_GPIO_PIN_9 - * @arg @ref MD_GPIO_PIN_10 - * @arg @ref MD_GPIO_PIN_11 - * @arg @ref MD_GPIO_PIN_12 - * @arg @ref MD_GPIO_PIN_13 - * @arg @ref MD_GPIO_PIN_14 - * @arg @ref MD_GPIO_PIN_15 - * @retval Returned value can be one of the following values: - * @arg @ref MD_GPIO_AF0 - * @arg @ref MD_GPIO_AF1 - * @arg @ref MD_GPIO_AF2 - * @arg @ref MD_GPIO_AF3 - * @arg @ref MD_GPIO_AF4 - * @arg @ref MD_GPIO_AF5 - * @arg @ref MD_GPIO_AF6 - * @arg @ref MD_GPIO_AF7 - */ -__STATIC_INLINE uint32_t md_gpio_get_function8_15(GPIO_TypeDef *GPIOx, uint32_t Pin) -{ - return (uint32_t)(READ_BIT(GPIOx->AFH, - (GPIO_AFH_AF8_MSK << (POSITION_VAL(Pin >> 8U) * 4U))) >> (POSITION_VAL(Pin >> 8U) * 4U)); -} - -/** - * @brief Lock configuration of several pins for a dedicated port. - * @note When the lock sequence has been applied on a port bit, the - * value of this port bit can no longer be modified until the - * next reset. - * @note LOCK key write sequence: - * WR GPIOx_LCK = (~LCK[15:0]<<16) + LCK[15:0] - * WR GPIOx_LCK = (~LCK[15:0]<<16) + LCK[15:0] - * @param GPIOx GPIO Port - * @param PinMask This parameter can be a combination of the following values: - * @arg @ref MD_GPIO_PIN_0 - * @arg @ref MD_GPIO_PIN_1 - * @arg @ref MD_GPIO_PIN_2 - * @arg @ref MD_GPIO_PIN_3 - * @arg @ref MD_GPIO_PIN_4 - * @arg @ref MD_GPIO_PIN_5 - * @arg @ref MD_GPIO_PIN_6 - * @arg @ref MD_GPIO_PIN_7 - * @arg @ref MD_GPIO_PIN_8 - * @arg @ref MD_GPIO_PIN_9 - * @arg @ref MD_GPIO_PIN_10 - * @arg @ref MD_GPIO_PIN_11 - * @arg @ref MD_GPIO_PIN_12 - * @arg @ref MD_GPIO_PIN_13 - * @arg @ref MD_GPIO_PIN_14 - * @arg @ref MD_GPIO_PIN_15 - * @arg @ref MD_GPIO_PIN_ALL - * @retval None - */ -__STATIC_INLINE void md_gpio_set_lock(GPIO_TypeDef *GPIOx, uint32_t PinMask) -{ - SET_BIT(GPIOx->LCK, PinMask); -} - -/** - * @brief Return 1 if all pins passed as parameter, of a dedicated port, are locked. else Return 0. - * @param GPIOx GPIO Port - * @param PinMask This parameter can be a combination of the following values: - * @arg @ref MD_GPIO_PIN_0 - * @arg @ref MD_GPIO_PIN_1 - * @arg @ref MD_GPIO_PIN_2 - * @arg @ref MD_GPIO_PIN_3 - * @arg @ref MD_GPIO_PIN_4 - * @arg @ref MD_GPIO_PIN_5 - * @arg @ref MD_GPIO_PIN_6 - * @arg @ref MD_GPIO_PIN_7 - * @arg @ref MD_GPIO_PIN_8 - * @arg @ref MD_GPIO_PIN_9 - * @arg @ref MD_GPIO_PIN_10 - * @arg @ref MD_GPIO_PIN_11 - * @arg @ref MD_GPIO_PIN_12 - * @arg @ref MD_GPIO_PIN_13 - * @arg @ref MD_GPIO_PIN_14 - * @arg @ref MD_GPIO_PIN_15 - * @arg @ref MD_GPIO_PIN_ALL - * @retval State of bit (1 or 0). - */ -__STATIC_INLINE uint32_t md_gpio_get_lock(GPIO_TypeDef *GPIOx, uint32_t PinMask) -{ - return (READ_BIT(GPIOx->LCK, PinMask) == (PinMask)); -} - - - -/** @defgroup MD_GPIO_IST_IST15 IST15 - * @brief Set IST15 configure the input schmitt trigger level bit for md_gpio_set_ist_fun() function used - * @param ist15 This parameter can be one of the following values: - * @arg @ref MD_GPIO_IST_TTL - * @arg @ref MD_GPIO_IST_CMOS - * @{ - */ -#define md_gpio_set_ist_ist15_fun(ist15) (ist15<IST, (ist15|ist14|ist13|ist12|ist11|ist10|ist9|ist8|ist7|ist6|ist5|ist4|ist3|ist2|ist1|ist0)); -} - -/** - * @brief Configure GPIOx port Input Schmitt Trigger Register. - * @note Warning: only one pin can be passed as parameter. - * @param GPIOx GPIO Port - * @param Pin This parameter can be one of the following values: - * @arg @ref MD_GPIO_PIN_0 - * @arg @ref MD_GPIO_PIN_1 - * @arg @ref MD_GPIO_PIN_2 - * @arg @ref MD_GPIO_PIN_3 - * @arg @ref MD_GPIO_PIN_4 - * @arg @ref MD_GPIO_PIN_5 - * @arg @ref MD_GPIO_PIN_6 - * @arg @ref MD_GPIO_PIN_7 - * @arg @ref MD_GPIO_PIN_8 - * @arg @ref MD_GPIO_PIN_9 - * @arg @ref MD_GPIO_PIN_10 - * @arg @ref MD_GPIO_PIN_11 - * @arg @ref MD_GPIO_PIN_12 - * @arg @ref MD_GPIO_PIN_13 - * @arg @ref MD_GPIO_PIN_14 - * @arg @ref MD_GPIO_PIN_15 - * @param Iolev This parameter can be one of the following values: - * @arg @ref MD_GPIO_IST_TTL - * @arg @ref MD_GPIO_IST_CMOS - * @retval None - */ -__STATIC_INLINE void md_gpio_set_ist(GPIO_TypeDef *GPIOx, uint32_t Pin, uint32_t Iolev) -{ - MODIFY_REG(GPIOx->IST, (GPIO_IST_IST_MSK << (POSITION_VAL(Pin))), (Iolev << (POSITION_VAL(Pin)))); -} - -/** - * @brief Return GPIOx port Input Schmitt Trigger Register - * @param GPIOx GPIO Port - * @param Pin This parameter can be one of the following values: - * @arg @ref MD_GPIO_PIN_0 - * @arg @ref MD_GPIO_PIN_1 - * @arg @ref MD_GPIO_PIN_2 - * @arg @ref MD_GPIO_PIN_3 - * @arg @ref MD_GPIO_PIN_4 - * @arg @ref MD_GPIO_PIN_5 - * @arg @ref MD_GPIO_PIN_6 - * @arg @ref MD_GPIO_PIN_7 - * @arg @ref MD_GPIO_PIN_8 - * @arg @ref MD_GPIO_PIN_9 - * @arg @ref MD_GPIO_PIN_10 - * @arg @ref MD_GPIO_PIN_11 - * @arg @ref MD_GPIO_PIN_12 - * @arg @ref MD_GPIO_PIN_13 - * @arg @ref MD_GPIO_PIN_14 - * @arg @ref MD_GPIO_PIN_15 - * @retval The retval can be one of the following values: - * @arg @ref MD_GPIO_IST_TTL - * @arg @ref MD_GPIO_IST_CMOS - */ -__STATIC_INLINE uint32_t md_gpio_get_ist(GPIO_TypeDef *GPIOx, uint32_t Pin) -{ - return (uint32_t)(READ_BIT(GPIOx->IST, (GPIO_IST_IST_MSK << (POSITION_VAL(Pin)))) >> (POSITION_VAL(Pin))); -} - -/** - * @brief Return full input data register value for a dedicated port. - * @param GPIOx GPIO Port - * @retval Input data register value of port - */ -__STATIC_INLINE uint32_t md_gpio_get_input_port(GPIO_TypeDef *GPIOx) -{ - return (uint32_t)(READ_REG(GPIOx->IDATA)); -} - - - - -/** @defgroup MD_GPIO_ODATA_OD15 OD15 - * @brief Set OD15 set/reset bit for md_gpio_set_bsbr() function used - * @param od15 This parameter can be one of the following values: - * @arg @ref MD_GPIO_OUTPUT_LOW - * @arg @ref MD_GPIO_OUTPUT_HIGH - * @{ - */ -#define md_gpio_set_odata_od15_fun(od15) (od15<ODATA, (od15|od14|od13|od12|od11|od10|od9|od8|od7|od6|od5|od4|od3|od2|od1|od0)); -} - - - - - -/** - * @brief Write output data register for the port. - * @param GPIOx GPIO Port - * @param PortValue Level value for each pin of the port - * @retval None - */ -__STATIC_INLINE void md_gpio_set_output_port(GPIO_TypeDef *GPIOx, uint32_t PortValue) -{ - WRITE_REG(GPIOx->ODATA, PortValue); -} - -/** - * @brief Return full output data register value for a dedicated port. - * @param GPIOx GPIO Port - * @retval Output data register value of port - */ -__STATIC_INLINE uint32_t md_gpio_get_output_port(GPIO_TypeDef *GPIOx) -{ - return (uint32_t)(READ_REG(GPIOx->ODATA)); -} - -/** - * @brief Set several pins to high level on dedicated gpio port. - * @param GPIOx GPIO Port - * @param PinMask This parameter can be a combination of the following values: - * @arg @ref MD_GPIO_PIN_0 - * @arg @ref MD_GPIO_PIN_1 - * @arg @ref MD_GPIO_PIN_2 - * @arg @ref MD_GPIO_PIN_3 - * @arg @ref MD_GPIO_PIN_4 - * @arg @ref MD_GPIO_PIN_5 - * @arg @ref MD_GPIO_PIN_6 - * @arg @ref MD_GPIO_PIN_7 - * @arg @ref MD_GPIO_PIN_8 - * @arg @ref MD_GPIO_PIN_9 - * @arg @ref MD_GPIO_PIN_10 - * @arg @ref MD_GPIO_PIN_11 - * @arg @ref MD_GPIO_PIN_12 - * @arg @ref MD_GPIO_PIN_13 - * @arg @ref MD_GPIO_PIN_14 - * @arg @ref MD_GPIO_PIN_15 - * @arg @ref MD_GPIO_PIN_ALL - * @retval None - */ -__STATIC_INLINE void md_gpio_set_pin_high(GPIO_TypeDef *GPIOx, uint32_t PinMask) -{ - WRITE_REG(GPIOx->BSBR, PinMask); -} - -/** - * @brief Reset several pins to low level on dedicated gpio port. - * @param GPIOx GPIO Port - * @param PinMask This parameter can be a combination of the following values: - * @arg @ref MD_GPIO_PIN_0 - * @arg @ref MD_GPIO_PIN_1 - * @arg @ref MD_GPIO_PIN_2 - * @arg @ref MD_GPIO_PIN_3 - * @arg @ref MD_GPIO_PIN_4 - * @arg @ref MD_GPIO_PIN_5 - * @arg @ref MD_GPIO_PIN_6 - * @arg @ref MD_GPIO_PIN_7 - * @arg @ref MD_GPIO_PIN_8 - * @arg @ref MD_GPIO_PIN_9 - * @arg @ref MD_GPIO_PIN_10 - * @arg @ref MD_GPIO_PIN_11 - * @arg @ref MD_GPIO_PIN_12 - * @arg @ref MD_GPIO_PIN_13 - * @arg @ref MD_GPIO_PIN_14 - * @arg @ref MD_GPIO_PIN_15 - * @arg @ref MD_GPIO_PIN_ALL - * @retval None - */ -__STATIC_INLINE void md_gpio_set_pin_low(GPIO_TypeDef *GPIOx, uint32_t PinMask) -{ - WRITE_REG(GPIOx->BSBR, (PinMask << 16)); -} - - -/** @defgroup MD_GPIO_FIR_FIR15 FIR15 - * @brief Set FIR15 configure the input signal over thought a glitch filter bit for md_gpio_set_fir() function used - * @param fir15 This parameter can be one of the following values: - * @arg @ref MD_GPIO_FILTER_BYPASS - * @arg @ref MD_GPIO_FILTER_GLITCH - * @{ - */ -#define md_gpio_set_fir_fir15_fun(fir15) (fir15<FIR, (fir15|fir14|fir13|fir12|fir11|fir10|fir9|fir8|fir7|fir6|fir5|fir4|fir3|fir2|fir1|fir0)); -} - - -/** - * @brief Write input filter register for the port. - * @note These bits are written by software to configure - * the input signal over thought a glitch filter. - * @param GPIOx GPIO Port - * @param PinMask This parameter can be a combination of the following values: - * @arg @ref MD_GPIO_PIN_0 - * @arg @ref MD_GPIO_PIN_1 - * @arg @ref MD_GPIO_PIN_2 - * @arg @ref MD_GPIO_PIN_3 - * @arg @ref MD_GPIO_PIN_4 - * @arg @ref MD_GPIO_PIN_5 - * @arg @ref MD_GPIO_PIN_6 - * @arg @ref MD_GPIO_PIN_7 - * @arg @ref MD_GPIO_PIN_8 - * @arg @ref MD_GPIO_PIN_9 - * @arg @ref MD_GPIO_PIN_10 - * @arg @ref MD_GPIO_PIN_11 - * @arg @ref MD_GPIO_PIN_12 - * @arg @ref MD_GPIO_PIN_13 - * @arg @ref MD_GPIO_PIN_14 - * @arg @ref MD_GPIO_PIN_15 - * @arg @ref MD_GPIO_PIN_ALL - * @retval None - */ -__STATIC_INLINE void md_gpio_set_filter(GPIO_TypeDef *GPIOx, uint32_t PinMask) -{ - WRITE_REG(GPIOx->FIR, PinMask); -} - -/** - * @brief Return full input filter data register value for a dedicated port. - * @param GPIOx GPIO Port - * @param PinMask This parameter can be a combination of the following values: - * @arg @ref MD_GPIO_PIN_0 - * @arg @ref MD_GPIO_PIN_1 - * @arg @ref MD_GPIO_PIN_2 - * @arg @ref MD_GPIO_PIN_3 - * @arg @ref MD_GPIO_PIN_4 - * @arg @ref MD_GPIO_PIN_5 - * @arg @ref MD_GPIO_PIN_6 - * @arg @ref MD_GPIO_PIN_7 - * @arg @ref MD_GPIO_PIN_8 - * @arg @ref MD_GPIO_PIN_9 - * @arg @ref MD_GPIO_PIN_10 - * @arg @ref MD_GPIO_PIN_11 - * @arg @ref MD_GPIO_PIN_12 - * @arg @ref MD_GPIO_PIN_13 - * @arg @ref MD_GPIO_PIN_14 - * @arg @ref MD_GPIO_PIN_15 - * @arg @ref MD_GPIO_PIN_ALL - * @retval State of bit (1 or 0). - */ -__STATIC_INLINE uint32_t md_gpio_get_filter(GPIO_TypeDef *GPIOx, uint32_t PinMask) -{ - return (READ_BIT(GPIOx->FIR, PinMask) == (PinMask)); -} - -/** - * @} MD_GPIO_Public_Macros - */ - -/* Public functions -----------------------------------------------------------*/ -/** @defgroup MD_GPIO_Public_Functions GPIO Public Functions - * @{ - */ - -/** @defgroup MD_GPIO_PF_Port_Configuration Port Configuration - * @{ - */ - -/** - * @} MD_GPIO_PF_Port_Configuration - */ - -/** @defgroup MD_GPIO_PF_Data_Access Data Access - * @{ - */ - -/** - * @} MD_GPIO_PF_Data_Access - */ - - -/** @defgroup MD_GPIO_PF_Init Initialization and de-initialization functions - * @{ - */ - -ErrorStatus md_gpio_deinit(GPIO_TypeDef *GPIOx); -ErrorStatus md_gpio_init(GPIO_TypeDef *GPIOx, md_gpio_inittypedef *GPIO_InitStruct); -void md_gpio_struct_init(md_gpio_inittypedef *GPIO_InitStruct); - -/** - * @} MD_GPIO_PF_Init - */ - -/** - * @} MD_GPIO_Public_Functions - */ - -#endif - -/** - * @} GPIO - */ - -/** - * @} Micro_Driver - */ - - -#ifdef __cplusplus -} -#endif - -#endif - -/******************* (C) COPYRIGHT Eastsoft Microelectronics *****END OF FILE****/ diff --git a/bsp/essemi/es32f0271/libraries/ES32F027x_MD_StdPeriph_Driver/Include/md_hdiv.h b/bsp/essemi/es32f0271/libraries/ES32F027x_MD_StdPeriph_Driver/Include/md_hdiv.h deleted file mode 100644 index 5baf2d5d23..0000000000 --- a/bsp/essemi/es32f0271/libraries/ES32F027x_MD_StdPeriph_Driver/Include/md_hdiv.h +++ /dev/null @@ -1,292 +0,0 @@ -/** - ****************************************************************************** - * @file md_HDIV.h - * @brief ES32F0271 HDIV HEAD File. - * - * @version V1.00.01 - * @date 11/20/2018 - * @author Eastsoft AE Team - * @note - * detailed description - * - * Copyright (C) 2018 Shanghai Eastsoft Microelectronics Co., Ltd. ALL rights reserved. - * - ******************************************************************************* - */ - -/* Define to prevent recursive inclusion -------------------------------------*/ -#ifndef __MD_HDIV_H__ -#define __MD_HDIV_H__ - -#ifdef __cplusplus -extern "C" { -#endif - -/* Includes -------------------------------------------------------------------*/ -#include "es32f0271.h" -#include "reg_hdiv.h" - -/** @addtogroup Micro_Driver - * @{ - */ - -#if defined (HDIV) - -/** @defgroup HDIV HDIV - * @brief HDIV micro driver - * @{ - */ - -/* Private types --------------------------------------------------------------*/ -/* Private variables ----------------------------------------------------------*/ -/* Private constants ----------------------------------------------------------*/ -/* Private macros -------------------------------------------------------------*/ - -/* Public types ---------------------------------------------------------------*/ - -/** - * @brief MD HDIV Parameter Structure definition - */ - -/* Public constants -----------------------------------------------------------*/ -/** @defgroup MD_HDIV_Public_Constants HDIV Public Constants - * @{ - */ - -/** - * @} MD_HDIV_Public_Constants - */ - -/* Public macro ---------------------------------------------------------------*/ -/** @defgroup MD_HDIV_Public_Macros HDIV Public Macros - * @{ - */ - -/** @defgroup MD_HDIV_PM_WRITE_READ Common write and read registers Macros - * @{ - */ - -/** - * @brief Write a value in HDIV register - * @param __INSTANCE__ HDIV Instance - * @param __REG__ Register to be written - * @param __VALUE__ Value to be written in the register - * @retval None - */ -#define MD_HDIV_WRITEREG(__INSTANCE__, __REG__, __VALUE__) WRITE_REG(__INSTANCE__->__REG__, (__VALUE__)) - -/** - * @brief Read a value in HDIV register - * @param __INSTANCE__ HDIV Instance - * @param __REG__ Register to be read - * @retval Register value - */ -#define MD_HDIV_READREG(__INSTANCE__, __REG__) READ_REG(__INSTANCE__->__REG__) - -/** - * @brief Modify value in HDIV register - * @param __INSTANCE__ HDIV Instance - * @param __REG__ Register to be written - * @param __MASK__ Mask value to be written in the register - * @param __VALUE__ Value to be written in the register - * @retval None - */ -#define MD_HDIV_MODIFYREG(__INSTANCE__, __REG__, __MASK__, __VALUE__) MODIFY_REG(__INSTANCE__->__REG__, __MASK__, (__VALUE__)) - -/** - * @brief Set bit value in HDIV register - * @param __INSTANCE__ HDIV Instance - * @param __REG__ Register to be read - * @param __MASK__ Mask value to be set in the register - * @retval None - */ -#define MD_HDIV_SET_BIT(__INSTANCE__, __REG__, __MASK__) SET_BIT(__INSTANCE__->__REG__, __MASK__) - -/** - * @brief Clear bit value in HDIV register - * @param __INSTANCE__ HDIV Instance - * @param __REG__ Register to be read - * @param __MASK__ Mask value to be cleased in the register - * @retval None - */ -#define MD_HDIV_CLEAR_BIT(__INSTANCE__, __REG__, __MASK__) CLEAR_BIT(__INSTANCE__->__REG__, __MASK__) - -/** - * @brief Read bit value in HDIV register - * @param __INSTANCE__ HDIV Instance - * @param __REG__ Register to be read - * @param __MASK__ Mask value to be read in the register - * @retval Register bit value - */ -#define MD_HDIV_READBIT(__INSTANCE__, __REG__, __MASK__) READ_BIT(__INSTANCE__->__REG__, __MASK__) - -/** - * @} MD_HDIV_PM_WRITE_READ - */ - -/** @defgroup MD_HDIV_Macro_Drivers HDIV Public Macro Drivers - * @{ - */ - -/** - * @brief Set HDIV DIVDR - * @note This register is given the dividend of divider before calculation starting - * @note When this register is written, hardware divider will start calculate - * @param @arg Max Value 0xffffffff - * @arg Min Value 0x0 - * @retval None - */ -__STATIC_INLINE void md_hdiv_set_divdr(uint32_t U32) -{ - MD_HDIV_WRITEREG(HDIV, DIVDR, U32); -} - -/** - * @brief Get HDIV DIVIDEND - * @note This register is given the dividend of divider before calculation starting - * @note When this register is written, hardware divider will start calculate - * @param None - * @retval The retval can be one of the following values: - * @arg Max Value 0xffffffff - * @arg Min Value 0x0 - */ -__STATIC_INLINE uint32_t md_hdiv_get_divdr(void) -{ - return (MD_HDIV_READREG(HDIV, DIVDR)); -} - -/** - * @brief Set HDIV DIVSR - * @note This register is given the divisor of divider before calculation starts - * @note When this register is written, hardware divider will start calculate - * @param @arg Max Value 0xffffffff - * @arg Min Value 0x0 - * @retval None - */ -__STATIC_INLINE void md_hdiv_set_divsr(uint32_t U32) -{ - MD_HDIV_WRITEREG(HDIV, DIVSR, U32); -} - -/** - * @brief Get HDIV DIVSR - * @note This register is given the divisor of divider before calculation starts. - * @note When this register is written, hardware divider will start calculate - * @param None - * @retval The retval can be one of the following values: - * @arg Max Value 0xffffffff - * @arg Min Value 0x0 - */ -__STATIC_INLINE uint32_t md_hdiv_get_divsr(void) -{ - return (MD_HDIV_READREG(HDIV, DIVSR)); -} - -/** - * @brief Get HDIV DIVQR - * @note This register holds the quotient result of divider after calculation complete - * @param None - * @retval The retval can be one of the following values: - * @arg Max Value 0xffffffff - * @arg Min Value 0x0 - */ -__STATIC_INLINE uint32_t md_hdiv_get_divqr(void) -{ - return (MD_HDIV_READREG(HDIV, DIVQR)); -} - -/** - * @brief Get HDIV DIVRR - * @note This register holds the remainder result of divider after calculation complete - * @param None - * @retval The retval can be one of the following values: - * @arg Max Value 0xffffffff - * @arg Min Value 0x0 - */ -__STATIC_INLINE uint32_t md_hdiv_get_divrr(void) -{ - return (MD_HDIV_READREG(HDIV, DIVRR)); -} - -/** - * @brief Get HDIV DIVSTAT - * @param None - * @retval The retval can be one of the following values: - * @arg Max Value 0x7 - * @arg Min Value 0x0 - */ -__STATIC_INLINE uint32_t md_hdiv_get_divstat(void) -{ - return (MD_HDIV_READREG(HDIV, DIVSTAT)); -} - -/** - * @brief Is HDIV DIVSTAT SIGN Active - * @param None - * @retval The retval can be one of the following values: - * @arg Max Value 0x1 : Signed - * @arg Min Value 0x0 : Unsigned - */ -__STATIC_INLINE uint8_t md_hdiv_get_divsts_sign(void) -{ - return (MD_HDIV_READBIT(HDIV, DIVSTAT, HDIV_DIVSTAT_SIGN_MSK)>>HDIV_DIVSTAT_SIGN_POS); -} - -/** - * @brief Is HDIV DIVSTAT DIV0 Active - * @param None - * @retval The retval can be one of the following values: - * @arg Max Value 0x1 : The divisor is 0 - * @arg Min Value 0x0 : The divisor is not 0 - */ -__STATIC_INLINE uint8_t md_hdiv_get_divsts_div0(void) -{ - return (MD_HDIV_READBIT(HDIV, DIVSTAT, HDIV_DIVSTAT_DIV0_MSK)>>HDIV_DIVSTAT_DIV0_POS); -} - -/** - * @brief Is HDIV DIVSTAT BUSY Active - * @param None - * @retval The retval can be one of the following values: - * @arg Max Value 0x1 : The divider is busy - * @arg Min Value 0x0 : The divider is not busy - */ -__STATIC_INLINE uint8_t md_hdiv_get_divsts_busy(void) -{ - return (MD_HDIV_READBIT(HDIV, DIVSTAT, HDIV_DIVSTAT_BUSY_MSK)>>HDIV_DIVSTAT_BUSY_POS); -} - -/** - * @} MD_HDIV_Macro_Drivers - */ - -/** - * @} MD_HDIV_Public_Macros - */ - -/* Public functions -----------------------------------------------------------*/ -/** @defgroup MD_HDIV_Public_Functions HDIV Public Functions - * @{ - */ - -/** - * @} MD_HDIV_Public_Functions - */ - -#endif - -/** - * @} HDIV - */ - -/** - * @} Micro_Driver - */ - -#ifdef __cplusplus -} -#endif - -#endif - -/******************* (C) COPYRIGHT Eastsoft Microelectronics *****END OF FILE****/ diff --git a/bsp/essemi/es32f0271/libraries/ES32F027x_MD_StdPeriph_Driver/Include/md_i2c.h b/bsp/essemi/es32f0271/libraries/ES32F027x_MD_StdPeriph_Driver/Include/md_i2c.h deleted file mode 100644 index 9f2e2ff964..0000000000 --- a/bsp/essemi/es32f0271/libraries/ES32F027x_MD_StdPeriph_Driver/Include/md_i2c.h +++ /dev/null @@ -1,3273 +0,0 @@ -/** - ****************************************************************************** - * @file md_i2c.h - * @brief ES32F0271 I2C HEAD File. - * - * @version V0.01 - * @date 4/12/2018 - * @author Eastsoft AE Team - * @note - * detailed description - * - * Copyright (C) 2018 Shanghai Eastsoft Microelectronics Co., Ltd. ALL rights reserved. - ******************************************************************************* - */ - -/* Define to prevent recursive inclusion -------------------------------------*/ -#ifndef __MD_I2C_H__ -#define __MD_I2C_H__ - -#ifdef __cplusplus -extern "C" { -#endif - -/* Includes -------------------------------------------------------------------*/ -#include "es32f0271.h" -#include "reg_i2c.h" - -/** @addtogroup Micro_Driver - * @{ - */ - -#if defined (I2C1) | defined (I2C2) - -/** @defgroup I2C I2C - * @brief I2C micro driver - * @{ - */ - -/* Private types --------------------------------------------------------------*/ -/* Private variables ----------------------------------------------------------*/ -/* Private constants ----------------------------------------------------------*/ -/* Private macros -------------------------------------------------------------*/ - - -/* Public Init Structure ------------------------------------------------------*/ -/** @defgroup MD_I2C_PT_INIT I2C Public Init structure - * @brief I2C Init structure. - * @{ - */ -typedef struct -{ - uint32_t Timing; /*!< Specifies the I2C_TIMINGR_register value. - This parameter calculated by referring to I2C initialization section in Reference manual */ - - uint32_t Address1; /*!< Specifies the first device address. - This parameter can be a 7-bit or 10-bit address. */ - - uint32_t AddrSize; /*!< Specifies the device address 1 size (7-bit or 10-bit). - This parameter can be a value of @ref I2C_LL_EC_OWNADDRESS1 - - This feature can be modified afterwards using unitary function @ref LL_I2C_SetOwnAddress1(). */ - - uint32_t DualAddressMode; /*!< Specifies if dual addressing mode is selected. - This parameter can be a value of @ref I2C_DUAL_ADDRESSING_MODE */ - - uint32_t Address2; /*!< Specifies the second device own address if dual addressing mode is selected - This parameter can be a 7-bit address. */ - - uint32_t Address2Masks; /*!< Specifies the acknowledge mask address second device own address if dual addressing mode is selected - This parameter can be a value of @ref I2C_OWN_ADDRESS2_MASKS */ -} md_i2c_inittypedef; -/** - * @} MD_I2C_PT_INIT - */ - -/* Public constants -----------------------------------------------------------*/ -/** @defgroup MD_I2C_Public_Constants I2C Public Constants - * @{ - */ - -/** @defgroup MD_I2C_ADDRESSING_MODE I2C Addressing Mode - * @{ - */ -#define MD_I2C_ADDRESSINGMODE_7BIT (0x00000000U) /*!< DISABLE */ -#define MD_I2C_ADDRESSINGMODE_10BIT (I2C_CON2_ADD10_MSK) /*!< I2C_CON2_ADD10_MSK = 1<<11 */ -/** - * @} MD_I2C_ADDRESSING_MODE - */ - -/** @defgroup MD_I2C_DUAL_ADDRESSING_MODE I2C Dual Addressing Mode - * @{ - */ -#define MD_I2C_DUALADDRESS_DISABLE (0x00000000U) /*!< DISABLE */ -#define MD_I2C_DUALADDRESS_ENABLE (I2C_ADDR2_OA2EN_MSK) /*!< I2C_ADDR2_OA2EN_MSK = 1<<15 */ -/** - * @} MD_I2C_DUAL_ADDRESSING_MODE - */ - -/** @defgroup MD_I2C_TIMING_CONFIG I2C Timing Config - * @note pllmul<<28|presc<<24|scll<<16|sclh<<8|sdadel<<4|scldel - * @{ - */ -/* pllmul presc scll sclh sdadel scldel */ -#define CLK10kHz8M (1<<28) |(1<<24) |(0xC7<<16)|(0xC3<<8)|(2<<4)|(4) /*!< APB = 8MHz; CLK = 10kHz */ -#define CLK100kHz8M (1<<28) |(1<<24) |(0x13<<16)|(0xF<<8) |(2<<4)|(4) /*!< APB = 8MHz; CLK = 100kHz */ -#define CLK400kHz8M (1<<28) |(0<<24) |(9<<16) |(3<<8) |(1<<4)|(3) /*!< APB = 8MHz; CLK = 400kHz */ -#define CLK500kHz8M (1<<28) |(0<<24) |(6<<16) |(3<<8) |(0<<4)|(1) /*!< APB = 8MHz; CLK = 500kHz */ -#define CLK10kHz16M (3<<28) |(3<<24) |(0xC7<<16)|(0xC3<<8)|(2<<4)|(4) /*!< APB = 16MHz; CLK = 10kHz */ -#define CLK100kHz16M (3<<28) |(3<<24) |(0x13<<16)|(0xF<<8) |(2<<4)|(4) /*!< APB = 16MHz; CLK = 100kHz */ -#define CLK400kHz16M (3<<28) |(1<<24) |(9<<16) |(3<<8) |(2<<4)|(3) /*!< APB = 16MHz; CLK = 400kHz */ -#define CLK1000kHz16M (3<<28) |(0<<24) |(4<<16) |(2<<8) |(0<<4)|(2) /*!< APB = 16MHz; CLK = 1000kHz */ -#define CLK10kHz48M (11U<<28)|(0xB<<24)|(0xC7<<16)|(0xC3<<8)|(2<<4)|(4) /*!< APB = 48MHz; CLK = 10kHz */ -#define CLK100kHz48M (11U<<28)|(0xB<<24)|(0x13<<16)|(0xF<<8) |(2<<4)|(4) /*!< APB = 48MHz; CLK = 100kHz */ -#define CLK400kHz48M (11U<<28)|(5<<24) |(9<<16) |(3<<8) |(3<<4)|(3) /*!< APB = 48MHz; CLK = 400kHz */ -#define CLK1000kHz48M (11U<<28)|(5<<24) |(3<<16) |(1<<8) |(0<<4)|(1) /*!< APB = 48MHz; CLK = 1000kHz */ -/** - * @} MD_I2C_TIMING_CONFIG - */ - -/** @defgroup MD_I2C_ADDRESS2_MASKS I2C Address2 Masks - * @{ - */ -#define MD_I2C_ADDR2_NOMASK (0x0000U) /*!< NOMASK */ -#define MD_I2C_ADDR2_MASK01 (0x0100U) /*!< MASK01 */ -#define MD_I2C_ADDR2_MASK02 (0x0200U) /*!< MASK02 */ -#define MD_I2C_ADDR2_MASK03 (0x0300U) /*!< MASK03 */ -#define MD_I2C_ADDR2_MASK04 (0x0400U) /*!< MASK04 */ -#define MD_I2C_ADDR2_MASK05 (0x0500U) /*!< MASK05 */ -#define MD_I2C_ADDR2_MASK06 (0x0600U) /*!< MASK06 */ -#define MD_I2C_ADDR2_MASK07 (0x0700U) /*!< MASK07 */ -/** - * @} MD_I2C_ADDRESS2_MASKS - */ - -/** @defgroup MD_I2C_GENERAL_CALL_ADDRESSING_MODE I2C General Call Addressing Mode - * @{ - */ -#define MD_I2C_GENERALCALL_DISABLE (0x00000000U) /*!< DISABLE */ -#define MD_I2C_GENERALCALL_ENABLE (I2C_CON1_GCEN_MSK) /*!< I2C_CON1_GCEN_MSK = 1<<19 */ -/** - * @} MD_I2C_GENERAL_CALL_ADDRESSING_MODE - */ - -/** @defgroup MD_I2C_NOSTRETCH_MODE I2C No-Stretch Mode - * @{ - */ -#define MD_I2C_NOSTRETCH_DISABLE (0x00000000U) /*!< DISABLE */ -#define MD_I2C_NOSTRETCH_ENABLE (I2C_CON1_NOSTRETCH_MSK) /*!< I2C_CON1_NOSTRETCH_MSK = 1<<17 */ -/** - * @} MD_I2C_NOSTRETCH_MODE - */ - -/** @defgroup MD_I2C_MODE I2C Mode - * @{ - */ -#define MD_I2C_MODE_NONE ((uint8_t)0x00U /*!< None */ -#define MD_I2C_MODE_MASTER ((uint8_t)0x10U) /*!< Master */ -#define MD_I2C_MODE_SLAVE ((uint8_t)0x20U) /*!< Slave */ -#define MD_I2C_MODE_MEM ((uint8_t)0x40U) /*!< Mem */ -/** - * @} MD_I2C_MODE - */ - -/** @defgroup MD_I2C_PECBYTE_ENABLE Pecbyte Enable - * @{ - */ -#define MD_I2C_PECBYTE_ENABLE I2C_CON2_PECBYTE_MSK /*!< I2C_CON2_PECBYTE_MSK = 1<<26 */ -/** - * @} MD_I2C_PECBYTE_ENABLE - */ - -/** @defgroup MD_I2C_AUTOEND_ENABLE I2C Autoend Enable - * @{ - */ -#define MD_I2C_SOFTEND_MODE (0x00000000U) /*!< DISABLE */ -#define MD_I2C_AUTOEND_MODE (I2C_CON2_AUTOEND_MSK) /*!< I2C_CON2_AUTOEND_MSK = 1<<25 */ -/** - * @} MD_I2C_AUTOEND_ENABLE - */ - -/** @defgroup MD_I2C_RELOAD_MODE I2C Reload Mode - * @{ - */ -#define MD_I2C_NORELOAD_MODE (0x00000000U) /*!< DISABLE */ -#define MD_I2C_RELOAD_MODE (I2C_CON2_RELOAD_MSK) /*!< I2C_CON2_RELOAD_MSK = 1<<24 */ -/** - * @} MD_I2C_RELOAD_MODE - */ - -/** @defgroup MD_I2C_NACKNOWLEDGE Acknowledge Generation - * @{ - */ -#define MD_I2C_ACK 0x00000000U /*!< ACK is sent after current received byte. */ -#define MD_I2C_NACK I2C_CON2_NACK_MSK /*!< NACK is sent after current received byte, I2C_CON2_NACK_MSK = 1<<15 */ -/** - * @} MD_I2C_NACKNOWLEDGE - */ - -/** @defgroup MD_I2C_STOP_GENERATION Stop Generation - * @{ - */ -#define MD_I2C_STOP_GENERATION I2C_CON2_STOP_MSK /*!< I2C_CON2_STOP_MSK = 1<<14 */ -/** - * @} MD_I2C_STOP_GENERATION - */ - -/** @defgroup MD_I2C_START_GENERATION Start Generation - * @{ - */ -#define MD_I2C_START_GENERATION I2C_CON2_START_MSK /*!< I2C_CON2_PECBYTE_MSK = 1<<13 */ -/** - * @} MD_I2C_START_GENERATION - */ - -/** @defgroup MD_I2C_HEAD10R Acknowledge Generation - * @{ - */ -#define MD_I2C_GENERAL_10BIT_READ 0x00000000U /*!< DISABLE */ -#define MD_I2C_SIMPLIFIED_10BIT_READ I2C_CON2_HEAD10R_MSK /*!< I2C_CON2_HEAD10R_MSK = 1<<12 */ -/** - * @} MD_I2C_HEAD10R - */ - -/** @defgroup MD_I2C_TRANSFER_DIRECTION Transfer direction (master mode) - * @{ - */ -#define MD_I2C_MASTER_WRITE 0x00000000U /*!< Master Write */ -#define MD_I2C_MASTER_READ I2C_CON2_RD_WRN_MSK /*!< I2C_CON2_RD_WRN_MSK = 1<<10 */ -/** - * @} MD_I2C_TRANSFER_DIRECTION - */ - -/** @defgroup MD_I2C_OA1_MODE Own Address 1 mode - * @{ - */ -#define MD_I2C_OA1_7BIT 0x00000000U /*!< OA1 7-bit mode */ -#define MD_I2C_OA1_10BIT I2C_ADDR1_OA1MODE_MSK /*!< I2C_ADDR1_OA1MODE_MSK = 1<<10 */ -/** - * @} MD_I2C_OA1_MODE - */ - -/** @defgroup MD_I2C_TIDLE_MODE Tidle mode - * @{ - */ -#define MD_I2C_LOW_TIMEOUTA 0x00000000U /*!< TIMEOUTA is used to detect SCL low timeout */ -#define MD_I2C_IDLE_TIMEOUTA I2C_TIMEOUTR_TIDLE_MSK /*!< TIMEOUTA is used to detectbus idle condition, I2C_TIMEOUTR_TIDLE_MSK = 1<<12 */ -/** - * @} MD_I2C_TIDLE_MODE - */ - -/** @defgroup MD_I2C_RXFIFO_THRESHOLD FIFO Threshold - * @{ - */ -#define MD_I2C_RXFIFO_THRESHOLD_RX1 0U<CON1, Reg_Value); -} - -/** - * @brief I2C Get CON1 - * @note None - * @param I2Cx I2C Instance - * @retval a 32-bit value - */ -__STATIC_INLINE uint32_t md_i2c_get_con1(I2C_TypeDef *I2Cx) -{ - return (uint32_t) (READ_REG(I2Cx->CON1)); -} - -/** - * @brief I2C PEC Enable - * @note If the SMBus feature is not supported,this bit is reserved and forced by hardware to 0. - * This register must be configured when the I2C is disabled (PE = 0). - * @param I2Cx I2C Instance - * @retval None - */ -__STATIC_INLINE void md_i2c_enable_con1_pecen(I2C_TypeDef *I2Cx) -{ - SET_BIT(I2Cx->CON1, I2C_CON1_PECEN_MSK); -} - -/** - * @brief I2C PEC Disable - * @note If the SMBus feature is not supported,this bit is reserved and forced by hardware to 0. - * This register must be configured when the I2C is disabled (PE = 0). - * @param I2Cx I2C Instance - * @retval None - */ -__STATIC_INLINE void md_i2c_disable_con1_pecen(I2C_TypeDef *I2Cx) -{ - CLEAR_BIT(I2Cx->CON1, I2C_CON1_PECEN_MSK); -} - -/** - * @brief Indicate if I2C PEC is enabled - * @note If the SMBus feature is not supported,this bit is reserved and forced by hardware to '0' - * @param I2Cx I2C Instance - * @retval State of bit (1 or 0). - */ -__STATIC_INLINE uint32_t md_i2c_is_enabled_con1_pecen(I2C_TypeDef *I2Cx) -{ - return (uint32_t)(READ_BIT(I2Cx->CON1, I2C_CON1_PECEN_MSK) == (I2C_CON1_PECEN_MSK)); -} - -/** - * @brief I2C Alert Enable - * @note When ALERTEN = 0, the SMBA pin can be used as a standard GPIO.If the SMBus feature is not supported, this bit is reserved and forced by hardware to 0. - * This register must be configured when the I2C is disabled (PE = 0). - * @param I2Cx I2C Instance - * @retval None - */ -__STATIC_INLINE void md_i2c_enable_con1_alerten(I2C_TypeDef *I2Cx) -{ - SET_BIT(I2Cx->CON1, I2C_CON1_ALERTEN_MSK); -} - -/** - * @brief I2C Alert Disable - * @note When ALERTEN = 0, the SMBA pin can be used as a standard GPIO.If the SMBus feature is not supported, this bit is reserved and forced by hardware to 0. - * This register must be configured when the I2C is disabled (PE = 0). - * @param I2Cx I2C Instance - * @retval None - */ -__STATIC_INLINE void md_i2c_disable_con1_alerten(I2C_TypeDef *I2Cx) -{ - CLEAR_BIT(I2Cx->CON1, I2C_CON1_ALERTEN_MSK); -} - -/** - * @brief Indicate if I2C PEC is enabled - * @note When ALERTEN = 0, the SMBA pin can be used as a standard GPIO.If the SMBus feature is not supported, this bit is reserved and forced by hardware to 0. - * @param I2Cx I2C Instance - * @retval State of bit (1 or 0). - */ -__STATIC_INLINE uint32_t md_i2c_is_enabled_con1_alerten(I2C_TypeDef *I2Cx) -{ - return (uint32_t)(READ_BIT(I2Cx->CON1, I2C_CON1_ALERTEN_MSK) == (I2C_CON1_ALERTEN_MSK)); -} - -/** - * @brief I2C SMBus Device Default address Enable - * @note If the SMBus feature is not supported,this bit is reserved and forced by hardware to 0. Device default address 0b1100 001. - * This register must be configured when the I2C is disabled (PE = 0). - * @param I2Cx I2C Instance - * @retval None - */ -__STATIC_INLINE void md_i2c_enable_con1_smbden(I2C_TypeDef *I2Cx) -{ - SET_BIT(I2Cx->CON1, I2C_CON1_SMBDEN_MSK); -} - -/** - * @brief I2C SMBus Device Default address Disable - * @note If the SMBus feature is not supported,this bit is reserved and forced by hardware to 0. Device default address 0b1100 001. - * This register must be configured when the I2C is disabled (PE = 0). - * @param I2Cx I2C Instance - * @retval None - */ -__STATIC_INLINE void md_i2c_disable_con1_smbden(I2C_TypeDef *I2Cx) -{ - CLEAR_BIT(I2Cx->CON1, I2C_CON1_SMBDEN_MSK); -} - -/** - * @brief Indicate if I2C SMBus Device Default address is enabled - * @note If the SMBus feature is not supported,this bit is reserved and forced by hardware to 0. Device default address 0b1100 001. - * @param I2Cx I2C Instance - * @retval State of bit (1 or 0). - */ -__STATIC_INLINE uint32_t md_i2c_is_enabled_con1_smbden(I2C_TypeDef *I2Cx) -{ - return (uint32_t)(READ_BIT(I2Cx->CON1, I2C_CON1_SMBDEN_MSK) == (I2C_CON1_SMBDEN_MSK)); -} - -/** - * @brief I2C SMBus Host address Enable - * @note If the SMBus feature is not supported,this bit is reserved and forced by hardware to 0. Host default address 0b0001 000. - * This register must be configured when the I2C is disabled (PE = 0). - * @param I2Cx I2C Instance - * @retval None - */ -__STATIC_INLINE void md_i2c_enable_con1_smbhen(I2C_TypeDef *I2Cx) -{ - SET_BIT(I2Cx->CON1, I2C_CON1_SMBHEN_MSK); -} - -/** - * @brief I2C SMBus Host address Disable - * @note If the SMBus feature is not supported,this bit is reserved and forced by hardware to 0. Host default address 0b0001 000. - * This register must be configured when the I2C is disabled (PE = 0). - * @param I2Cx I2C Instance - * @retval None - */ -__STATIC_INLINE void md_i2c_disable_con1_smbhen(I2C_TypeDef *I2Cx) -{ - CLEAR_BIT(I2Cx->CON1, I2C_CON1_SMBHEN_MSK); -} - -/** - * @brief Indicate if I2C SMBus Host address is enabled - * @note If the SMBus feature is not supported,this bit is reserved and forced by hardware to 0. Host default address 0b0001 000. - * @param I2Cx I2C Instance - * @retval State of bit (1 or 0). - */ -__STATIC_INLINE uint32_t md_i2c_is_enabled_con1_smbhen(I2C_TypeDef *I2Cx) -{ - return (uint32_t)(READ_BIT(I2Cx->CON1, I2C_CON1_SMBHEN_MSK) == (I2C_CON1_SMBHEN_MSK)); -} - -/** - * @brief I2C general call Enable - * @note This register must be configured when the I2C is disabled (PE = 0). - * @param I2Cx I2C Instance - * @retval None - */ -__STATIC_INLINE void md_i2c_enable_con1_gcen(I2C_TypeDef *I2Cx) -{ - SET_BIT(I2Cx->CON1, I2C_CON1_GCEN_MSK); -} - -/** - * @brief I2C general call Disable - * @note This register must be configured when the I2C is disabled (PE = 0). - * @param I2Cx I2C Instance - * @retval None - */ -__STATIC_INLINE void md_i2c_disable_con1_gcen(I2C_TypeDef *I2Cx) -{ - CLEAR_BIT(I2Cx->CON1, I2C_CON1_GCEN_MSK); -} - -/** - * @brief Indicate if I2C general call is enabled - * @note None - * @param I2Cx I2C Instance - * @retval State of bit (1 or 0). - */ -__STATIC_INLINE uint32_t md_i2c_is_enabled_con1_gcen(I2C_TypeDef *I2Cx) -{ - return (uint32_t)(READ_BIT(I2Cx->CON1, I2C_CON1_GCEN_MSK) == (I2C_CON1_GCEN_MSK)); -} - -/** - * @brief I2C clock stretching Disable - * @note Clock stretching disables. This bit can only be programmed when the I2C is disabled(PE = 0) - * @param I2Cx I2C Instance - * @retval None - */ -__STATIC_INLINE void md_i2c_enable_con1_nostretch(I2C_TypeDef *I2Cx) -{ - SET_BIT(I2Cx->CON1, I2C_CON1_NOSTRETCH_MSK); -} - -/** - * @brief I2C clock stretching Enable - * @note Clock stretching enables.This bit can only be programmed when the I2C is disabled(PE = 0) - * @param I2Cx I2C Instance - * @retval None - */ -__STATIC_INLINE void md_i2c_disable_con1_nostretch(I2C_TypeDef *I2Cx) -{ - CLEAR_BIT(I2Cx->CON1, I2C_CON1_NOSTRETCH_MSK); -} - -/** - * @brief Indicate if I2C clock nostretching is enabled - * @note This bit can only be programmed when the I2C is disabled(PE = 0) - * @param I2Cx I2C Instance - * @retval State of bit (1 or 0). - */ -__STATIC_INLINE uint32_t md_i2c_is_enabled_con1_nostretch(I2C_TypeDef *I2Cx) -{ - return (uint32_t)(READ_BIT(I2Cx->CON1, I2C_CON1_NOSTRETCH_MSK) == (I2C_CON1_NOSTRETCH_MSK)); -} - -/** - * @brief I2C slave byte control Enable - * @note This bit can only be programmed when the I2C is disabled(PE = 0) - * @param I2Cx I2C Instance - * @retval None - */ -__STATIC_INLINE void md_i2c_enable_con1_sbc(I2C_TypeDef *I2Cx) -{ - SET_BIT(I2Cx->CON1, I2C_CON1_SBC_MSK); -} - -/** - * @brief I2C slave byte control Disable - * @note This bit can only be programmed when the I2C is disabled(PE = 0) - * @param I2Cx I2C Instance - * @retval None - */ -__STATIC_INLINE void md_i2c_disable_con1_sbc(I2C_TypeDef *I2Cx) -{ - CLEAR_BIT(I2Cx->CON1, I2C_CON1_SBC_MSK); -} - -/** - * @brief Indicate if I2C slave byte control is enabled - * @note None - * @param I2Cx I2C Instance - * @retval State of bit (1 or 0). - */ -__STATIC_INLINE uint32_t md_i2c_is_enabled_con1_sbc(I2C_TypeDef *I2Cx) -{ - return (uint32_t)(READ_BIT(I2Cx->CON1, I2C_CON1_SBC_MSK) == (I2C_CON1_SBC_MSK)); -} - -/** - * @brief I2C DMA reception requests Enable - * @note None - * @param I2Cx I2C Instance - * @retval None - */ -__STATIC_INLINE void md_i2c_enable_con1_rxdmaen(I2C_TypeDef *I2Cx) -{ - SET_BIT(I2Cx->CON1, I2C_CON1_RXDMAEN_MSK); -} - -/** - * @brief I2C DMA reception requests Disable - * @note None - * @param I2Cx I2C Instance - * @retval None - */ -__STATIC_INLINE void md_i2c_disable_con1_rxdmaen(I2C_TypeDef *I2Cx) -{ - CLEAR_BIT(I2Cx->CON1, I2C_CON1_RXDMAEN_MSK); -} - -/** - * @brief Indicate if I2C DMA reception requests is enabled - * @note None - * @param I2Cx I2C Instance - * @retval State of bit (1 or 0). - */ -__STATIC_INLINE uint32_t md_i2c_is_enabled_con1_rxdmaen(I2C_TypeDef *I2Cx) -{ - return (uint32_t)(READ_BIT(I2Cx->CON1, I2C_CON1_RXDMAEN_MSK) == (I2C_CON1_RXDMAEN_MSK)); -} - -/** - * @brief I2C DMA transmission requests Enable - * @note None - * @param I2Cx I2C Instance - * @retval None - */ -__STATIC_INLINE void md_i2c_enable_con1_txdmaen(I2C_TypeDef *I2Cx) -{ - SET_BIT(I2Cx->CON1, I2C_CON1_TXDMAEN_MSK); -} - -/** - * @brief I2C DMA transmission requests Disable - * @note None - * @param I2Cx I2C Instance - * @retval None - */ -__STATIC_INLINE void md_i2c_disable_con1_txdmaen(I2C_TypeDef *I2Cx) -{ - CLEAR_BIT(I2Cx->CON1, I2C_CON1_TXDMAEN_MSK); -} - -/** - * @brief Indicate if I2C DMA transmission requests is enabled - * @note None - * @param I2Cx I2C Instance - * @retval State of bit (1 or 0). - */ -__STATIC_INLINE uint32_t md_i2c_is_enabled_con1_txdmaen(I2C_TypeDef *I2Cx) -{ - return (uint32_t)(READ_BIT(I2Cx->CON1, I2C_CON1_TXDMAEN_MSK) == (I2C_CON1_TXDMAEN_MSK)); -} - -/** - * @brief Set I2C digital noise filter - * @note If the analog filter is also enabled,the digital filter is added to the analog filter. - * This filter can only be programmed when the I2C is disabled(PE = 0) - * @param I2Cx I2C Instance - * @param filter_capability digital noise filter capability - * @arg Max Value 0xFF - * @arg Min Value 0 - * @retval None - */ -__STATIC_INLINE void md_i2c_set_con1_dnf(I2C_TypeDef *I2Cx, uint32_t filter_capability) -{ - MODIFY_REG(I2Cx->CON1, I2C_CON1_DNF_MSK, filter_capability<CON1, I2C_CON1_DNF_MSK)>>I2C_CON1_DNF_POSS); -} - -/** - * @brief I2C Peripheral Enable - * @note When PE = 0, the I2C SCL and SDA lines are released. - * Internal state machines and status bits are put back to their reset value. - * When cleared, PE must be kept low for at least 3 APB clock cycles. - * @param I2Cx I2C Instance - * @retval None - */ -__STATIC_INLINE void md_i2c_enable_con1_pe(I2C_TypeDef *I2Cx) -{ - SET_BIT(I2Cx->CON1, I2C_CON1_PE_MSK); -} - -/** - * @brief I2C Peripheral Disable - * @note When PE = 0, the I2C SCL and SDA lines are released.Internal state machines and status bits are put back to their reset value.When cleared,PE must be kept low for at least 3 APB clock cycles - * @param I2Cx I2C Instance - * @retval None - */ -__STATIC_INLINE void md_i2c_disable_con1_pe(I2C_TypeDef *I2Cx) -{ - CLEAR_BIT(I2Cx->CON1, I2C_CON1_PE_MSK); -} - -/** - * @brief Indicate if Peripheral is enabled - * @note When PE = 0, the I2C SCL and SDA lines are released.Internal state machines and status bits are put back to their reset value.When cleared,PE must be kept low for at least 3 APB clock cycles - * @param I2Cx I2C Instance - * @retval State of bit (1 or 0). - */ -__STATIC_INLINE uint32_t md_i2c_is_enabled_con1_pe(I2C_TypeDef *I2Cx) -{ - return (uint32_t)(READ_BIT(I2Cx->CON1, I2C_CON1_PE_MSK) == (I2C_CON1_PE_MSK)); -} - -/** - * @brief I2C Set CON2 - * @note None - * @param I2Cx I2C Instance - * @param Reg_Value is a 32-bit value - * @retval None - */ -__STATIC_INLINE void md_i2c_set_con2(I2C_TypeDef *I2Cx, uint32_t Reg_Value) -{ - WRITE_REG(I2Cx->CON2, Reg_Value); -} - -/** - * @brief I2C Get CON2 - * @note None - * @param I2Cx I2C Instance - * @retval a 32-bit value - */ -__STATIC_INLINE uint32_t md_i2c_get_con2(I2C_TypeDef *I2Cx) -{ - return (uint32_t) (READ_REG(I2Cx->CON2)); -} - -/** - * @brief I2C Set ACK Update - * @note None - * @param I2Cx I2C Instance - * @retval None - */ -__STATIC_INLINE void md_i2c_set_con2_ack_upd(I2C_TypeDef *I2Cx) -{ - SET_BIT(I2Cx->CON2, I2C_CON2_ACK_UPD_MSK); -} - -/** - * @brief I2C Hold Ack Enable - * @note None - * @param I2Cx I2C Instance - * @retval None - */ -__STATIC_INLINE void md_i2c_enable_con2_holdack(I2C_TypeDef *I2Cx) -{ - SET_BIT(I2Cx->CON2, I2C_CON2_HOLDACK_MSK); -} - -/** - * @brief I2C Hold Ack Disable - * @note None - * @param I2Cx I2C Instance - * @retval None - */ -__STATIC_INLINE void md_i2c_disable_con2_holdack(I2C_TypeDef *I2Cx) -{ - CLEAR_BIT(I2Cx->CON2, I2C_CON2_HOLDACK_MSK); -} - -/** - * @brief Indicate if I2C Hold Ack is enabled - * @param I2Cx I2C Instance - * @retval State of bit (1 or 0). - */ -__STATIC_INLINE uint32_t md_i2c_is_enabled_con2_holdack(I2C_TypeDef *I2Cx) -{ - return (uint32_t)(READ_BIT(I2Cx->CON2, I2C_CON2_HOLDACK_MSK) == (I2C_CON2_HOLDACK_MSK)); -} - -/** - * @brief Set I2C Packet error checking byte - * @note This bit is set by software, and cleared by hardware when the PEC is transferred, - * or when a STOP condition or an Address matched is received, also when PE=0. - * Writing 0 to this bit has no effet. This bit has no effect when RELOAD is set, - * and when SBC is 0 in the slave mode. - * If the SMBus feature is not supported, this bit is reserved and forced by hardware to 0. - * @param I2Cx I2C Instance - * @param setbit - * @arg @ref MD_I2C_PECBYTE_ENABLE - * @retval None - */ -__STATIC_INLINE void md_i2c_set_con2_pecbyte(I2C_TypeDef *I2Cx, uint32_t setbit) -{ - MODIFY_REG(I2Cx->CON2, I2C_CON2_PECBYTE_MSK, setbit); -} - -/** - * @brief Get I2C Packet error checking byte - * @note This bit is set by software, and cleared by hardware when the PEC is transferred, - * or when a STOP condition or an Address matched is received, also when PE=0. - * Writing 0 to this bit has no effet. This bit has no effect when RELOAD is set, - * and when SBC is 0 in the slave mode. - * If the SMBus feature is not supported, this bit is reserved and forced by hardware to 0. - * @param I2Cx I2C Instance - * @retval State of bit (1 or 0). - */ -__STATIC_INLINE uint32_t md_i2c_get_con2_pecbyte(I2C_TypeDef *I2Cx) -{ - return (READ_BIT(I2Cx->CON2, I2C_CON2_PECBYTE_MSK)>>I2C_CON2_PECBYTE_POS); -} - -/** - * @brief Set I2C automatic end mode or software end mode(master mode) - * @note This bit has no effect in slave mode or when the RELOAD bit is set. - * Software end mode: TC flag is set when NBYTES data are transferred, stretching SCL low. - * Automatic end mode: a STOP condition is automatically sent when NBYTES data are transferred. - * @param I2Cx I2C Instance - * @param setbit - * @arg @ref MD_I2C_SOFTEND_MODE - * @arg @ref MD_I2C_AUTOEND_MODE - * @retval None - */ -__STATIC_INLINE void md_i2c_set_con2_autoend(I2C_TypeDef *I2Cx, uint32_t setbit) -{ - MODIFY_REG(I2Cx->CON2, I2C_CON2_AUTOEND_MSK, setbit); -} - -/** - * @brief Get I2C automatic or software end mode(master mode) - * @note This bit has no effect in slave mode or when the RELOAD bit is set. - * Software end mode: TC flag is set when NBYTES data are transferred, stretching SCL low. - * Automatic end mode: a STOP condition is automatically sent when NBYTES data are transferred. - * @param I2Cx I2C Instance - * @retval State of bit (1 or 0). - */ -__STATIC_INLINE uint32_t md_i2c_get_con2_autoend(I2C_TypeDef *I2Cx) -{ - return (READ_BIT(I2Cx->CON2, I2C_CON2_AUTOEND_MSK)>>I2C_CON2_AUTOEND_POS); -} - -/** - * @brief Set I2C NBYTES reload mode or not - * @note RELOAD = 0: The transfer is completed after the NBYTES data transfer (STOP or RESTART will follow). - * RELOAD = 1: The transfer is not completed after the NBYTES data transfer (NBYTES will be reloaded). - * TCR flag is set when NBYTES data are transferred, stretching SCL low. - * @param I2Cx I2C Instance - * @param setbit - * @arg @ref MD_I2C_NORELOAD_MODE - * @arg @ref MD_I2C_RELOAD_MODE - * @retval None - */ -__STATIC_INLINE void md_i2c_set_con2_reload(I2C_TypeDef *I2Cx, uint32_t setbit) -{ - MODIFY_REG(I2Cx->CON2, I2C_CON2_RELOAD_MSK, setbit); -} - -/** - * @brief Get I2C RELOAD value - * @note RELOAD = 0: The transfer is completed after the NBYTES data transfer (STOP or RESTART will follow). - * RELOAD = 1: The transfer is not completed after the NBYTES data transfer (NBYTES will be reloaded). - * TCR flag is set when NBYTES data are transferred, stretching SCL low. - * @param I2Cx I2C Instance - * @retval State of bit (1 or 0). - */ -__STATIC_INLINE uint32_t md_i2c_get_con2_reload(I2C_TypeDef *I2Cx) -{ - return (READ_BIT(I2Cx->CON2, I2C_CON2_RELOAD_MSK)>>I2C_CON2_RELOAD_POS); -} - -/** - * @brief Set I2C number of bytes - * @note The number of bytes to be transmitted/received is programmed there. - * This field is dont care in slave mode with SBC=0. - * Changing these bits when the START bit is set is not allowed. - * @param I2Cx I2C Instance - * @param nbytes number of bytes - * @arg Max Value 0xFF - * @arg Min Value 0x0 - * @retval None - */ -__STATIC_INLINE void md_i2c_set_con2_nbytes(I2C_TypeDef *I2Cx, uint32_t nbytes) -{ - MODIFY_REG(I2Cx->CON2, I2C_CON2_NBYTES_MSK, nbytes<CON2, I2C_CON2_NBYTES_MSK)>>I2C_CON2_NBYTES_POSS); -} - -/** - * @brief Set I2C NACK generation(slave mode) - * @note Writing 0 to this bit has no effect. This bit is used in slave mode only. - * When an overrun occurs in slave receiver NOSTRETCH mode,a NACK is automatically generated whatever the NACK bit value. - * When hardware PEC checking is enabled(PECBYTE = 1),the PEC acknowledge value does not depend on the NACK value. - * @param I2Cx I2C Instance - * @param nack nack generation - * @arg @ref MD_I2C_NACK - * @retval None - */ -__STATIC_INLINE void md_i2c_set_con2_nack(I2C_TypeDef *I2Cx, uint32_t nack) -{ - MODIFY_REG(I2Cx->CON2, I2C_CON2_NACK_MSK, nack); -} - -/** - * @brief Get I2C NACK bit state(slave mode) - * @note NACK=1: will generate NACK - * NACK=0: will generate ACK - * @param I2Cx I2C Instance - * @retval State of bit (1 or 0). - */ -__STATIC_INLINE uint32_t md_i2c_get_con2_nack(I2C_TypeDef *I2Cx) -{ - return (READ_BIT(I2Cx->CON2, I2C_CON2_NACK_MSK)>>I2C_CON2_NACK_POS); -} - -/** - * @brief Set I2C Stop generation(master mode) - * @note Writing 0 to this bit has no effect. - * @param I2Cx I2C Instance - * @param stop_generate stop generate - * @arg MD_I2C_STOP_GENERATION - * @retval None - */ -__STATIC_INLINE void md_i2c_set_con2_stop(I2C_TypeDef *I2Cx, uint32_t stop_generate) -{ - MODIFY_REG(I2Cx->CON2, I2C_CON2_STOP_MSK, stop_generate); -} - -/** - * @brief Get I2C state of STOP bit(master mode) - * @note Writing 0 to this bit has no effect. - * @param I2Cx I2C Instance - * @retval State of bit (1 or 0). - */ -__STATIC_INLINE uint32_t md_i2c_get_con2_stop(I2C_TypeDef *I2Cx) -{ - return (READ_BIT(I2Cx->CON2, I2C_CON2_STOP_MSK)>>I2C_CON2_STOP_POS); -} - -/** - * @brief Set I2C Start generation - * @note Writing 0 to this bit has no effect.The START bit can be set even if the bus is BUSY or I2C is in slave mode. - * In 10-bit addressing mode, if a NACK is received on the first part of the address, - * the START bit is not cleared by hardware and the master will resend the address sequence. - * @param I2Cx I2C Instance - * @param start_generate stop generate - * @arg MD_I2C_START_GENERATION - * @retval None - */ -__STATIC_INLINE void md_i2c_set_con2_start(I2C_TypeDef *I2Cx, uint32_t start_generate) -{ - MODIFY_REG(I2Cx->CON2, I2C_CON2_START_MSK, start_generate); -} - -/** - * @brief Get I2C state of START bit - * @note None - * @param I2Cx I2C Instance - * @retval State of bit (1 or 0). - */ -__STATIC_INLINE uint32_t md_i2c_get_con2_start(I2C_TypeDef *I2Cx) -{ - return (READ_BIT(I2Cx->CON2, I2C_CON2_START_MSK)>>I2C_CON2_START_POS); -} - -/** - * @brief Set the master operates in 10-bit addressing mode(master receiver mode) - * @note Changing this bit when the START bit is set is not allowed. - * It can be used when the 10-bit transmission was done before. - * @param I2Cx I2C Instance - * @param read_header format of read header - * @arg @ref MD_I2C_GENERAL_10BIT_READ - * @arg @ref MD_I2C_SIMPLIFIED_10BIT_READ - * @retval None - */ -__STATIC_INLINE void md_i2c_set_con2_head10r(I2C_TypeDef *I2Cx, uint32_t read_header) -{ - MODIFY_REG(I2Cx->CON2, I2C_CON2_HEAD10R_MSK, read_header); -} - -/** - * @brief Indicate if I2C 10-bit address header only read direction is enabled(master receiver mode) - * @note None - * @param I2Cx I2C Instance - * @retval State of bit (1 or 0). - */ -__STATIC_INLINE uint32_t md_i2c_get_con2_head10r(I2C_TypeDef *I2Cx) -{ - return (READ_BIT(I2Cx->CON2, I2C_CON2_HEAD10R_MSK)>>I2C_CON2_HEAD10R_POS); -} - -/** - * @brief I2C 10-bit addressing mode Enable(master mode) - * @note Changing this bit when the START bit is set is not allowed. - * @param I2Cx I2C Instance - * @param addrmode - @arg @ref MD_I2C_ADDRESSINGMODE_7BIT - @arg @ref MD_I2C_ADDRESSINGMODE_10BIT - * @retval None - */ -__STATIC_INLINE void md_i2c_set_con2_add10(I2C_TypeDef *I2Cx, uint32_t addrmode) -{ - MODIFY_REG(I2Cx->CON2, I2C_CON2_ADD10_MSK, addrmode); -} - -/** - * @brief Get I2C addressing mode is 10-bit or 7-bit mode(master mode) - * @note ADD10=1: 10-bit mode - * ADD10=0: 7-bit mode - * @param I2Cx I2C Instance - * @retval State of bit (1 or 0). - */ -__STATIC_INLINE uint32_t md_i2c_get_con2_add10(I2C_TypeDef *I2Cx) -{ - return (READ_BIT(I2Cx->CON2, I2C_CON2_ADD10_MSK)>>I2C_CON2_ADD10_POS); -} - -/** - * @brief Set Master transfer direction(master mode) - * @note Changing this bit when the START bit is set is not allowed. - * @param I2Cx I2C Instance - * @param direction - * @arg @ref MD_I2C_MASTER_WRITE - * @arg @ref MD_I2C_MASTER_READ - * @retval None - */ -__STATIC_INLINE void md_i2c_set_con2_rd_wrn(I2C_TypeDef *I2Cx, uint32_t direction) -{ - MODIFY_REG(I2Cx->CON2, I2C_CON2_RD_WRN_MSK, direction); -} - -/** - * @brief Get Master transfer direction(master mode) - * @note None - * @param I2Cx I2C Instance - * @retval State of bit (1 or 0). - */ -__STATIC_INLINE uint32_t md_i2c_get_con2_rd_wrn(I2C_TypeDef *I2Cx) -{ - return (READ_BIT(I2Cx->CON2, I2C_CON2_RD_WRN_MSK)>>I2C_CON2_RD_WRN_POS); -} - -/** - * @brief Set I2C slave address(master mode) - * @note Changing these bits when the START bit is set is not allowed - * For 7-bit mode, bit 7 to 1 are valid; for 10-bit mode, all 10 bits are valid. - * @param I2Cx I2C Instance - * @param slave_addr I2C slave address - * @arg Max Value 7-bit: 0xFF / 10-bit: 0x3FF - * @arg Min Value 7-bit: 0x2 / 10-bit: 0x1 - * @retval None - */ -__STATIC_INLINE void md_i2c_set_con2_sadd(I2C_TypeDef *I2Cx, uint32_t slave_addr) -{ - MODIFY_REG(I2Cx->CON2, I2C_CON2_SADD_MSK, slave_addr); -} - -/** - * @brief Get I2C slave address(master mode) - * @note Changing these bits when the START bit is set is not allowed - * For 7-bit mode, bit 7 to 1 are valid; for 10-bit mode, all 10 bits are valid. - * @param I2Cx I2C Instance - * @retval I2C slave address - * @arg Max Value 7-bit: 0xFF / 10-bit: 0x3FF - * @arg Min Value 7-bit: 0x2 / 10-bit: 0x1 - */ -__STATIC_INLINE uint32_t md_i2c_get_sadd_7bit(I2C_TypeDef *I2Cx) -{ - return (READ_BIT(I2Cx->CON2, I2C_CON2_SADD_MSK)); -} - -/** - * @brief Set I2C ADDR1 - * @note These bits can be written only when OA1EN=0 except OA1EN. - * @param I2Cx I2C Instance - * @param Reg_Value is a 32-bit value - * @retval None - */ -__STATIC_INLINE void md_i2c_set_addr1(I2C_TypeDef *I2Cx, uint32_t Reg_Value) -{ - WRITE_REG(I2Cx->ADDR1, Reg_Value); -} - -/** - * @brief Get I2C ADDR1 - * @note None - * @param I2Cx I2C Instance - * @retval a 32-bit value - */ -__STATIC_INLINE uint32_t md_i2c_get_addr1(I2C_TypeDef *I2Cx) -{ - return (uint32_t) (READ_REG(I2Cx->ADDR1)); -} - -/** - * @brief I2C address register 1 Enable - * @note None - * @param I2Cx I2C Instance - * @retval None - */ -__STATIC_INLINE void md_i2c_enable_addr1_oa1en(I2C_TypeDef *I2Cx) -{ - SET_BIT(I2Cx->ADDR1, I2C_ADDR1_OA1EN_MSK); -} - -/** - * @brief I2C address register 1 Disable - * @note None - * @param I2Cx I2C Instance - * @retval None - */ -__STATIC_INLINE void md_i2c_disable_addr1_oa1en(I2C_TypeDef *I2Cx) -{ - CLEAR_BIT(I2Cx->ADDR1, I2C_ADDR1_OA1EN_MSK); -} - -/** - * @brief Indicate if address register 1 is enabled - * @param I2Cx I2C Instance - * @retval State of bit (1 or 0). - */ -__STATIC_INLINE uint32_t md_i2c_is_enabled_addr1_oa1en(I2C_TypeDef *I2Cx) -{ - return (uint32_t)(READ_BIT(I2Cx->ADDR1, I2C_ADDR1_OA1EN_MSK) == (I2C_ADDR1_OA1EN_MSK)); -} - -/** - * @brief Set I2C OA1 bit mode - * @param I2Cx I2C Instance - * @param oa1mode - * @arg @ref MD_I2C_OA1_7BIT - * @arg @ref MD_I2C_OA1_10BIT - * @retval None - */ -__STATIC_INLINE void md_i2c_set_addr1_oa1mode(I2C_TypeDef *I2Cx, uint32_t oa1mode) -{ - MODIFY_REG(I2Cx->ADDR1, I2C_ADDR1_OA1MODE_MSK, oa1mode); -} - -/** - * @brief Get I2C own address 1 mode - * @param I2Cx I2C Instance - * @retval State of bit (1 or 0). - */ -__STATIC_INLINE uint32_t md_i2c_get_addr1_oa1mode(I2C_TypeDef *I2Cx) -{ - return (READ_BIT(I2Cx->ADDR1, I2C_ADDR1_OA1MODE_MSK)>>I2C_ADDR1_OA1MODE_POS); -} - -/** - * @brief Set I2C address1 - * @note For 7-bit mode, bit 7 to 1 are valid; for 10-bit mode, all 10 bits are valid. - * @param I2Cx I2C Instance - * @param own_addr I2C own address1 - * @arg Max Value 7-bit: 0xFF / 10-bit: 0x3FF - * @arg Min Value 7-bit: 0x2 / 10-bit: 0x1 - * @retval None - */ -__STATIC_INLINE void md_i2c_set_addr1_oa1(I2C_TypeDef *I2Cx, uint32_t own_addr) -{ - MODIFY_REG(I2Cx->ADDR1, I2C_ADDR1_OA1_MSK, own_addr); -} - -/** - * @brief Get I2C address1 - * @note For 7-bit mode, bit 7 to 1 are valid; for 10-bit mode, all 10 bits are valid. - * @param I2Cx I2C Instance - * @retval I2C own address1 - * @arg Max Value 7-bit: 0xFF / 10-bit: 0x3FF - * @arg Min Value 7-bit: 0x2 / 10-bit: 0x1 - */ -__STATIC_INLINE uint32_t md_i2c_get_addr1_oa1(I2C_TypeDef *I2Cx) -{ - return (READ_BIT(I2Cx->ADDR1, I2C_ADDR1_OA1_MSK)); -} - -/** - * @brief Set I2C ADDR2 - * @note These bits can be written only when OA2EN=0 except OA2EN. - * @param I2Cx I2C Instance - * @param Reg_Value is a 32-bit value - * @retval None - */ -__STATIC_INLINE void md_i2c_set_addr2(I2C_TypeDef *I2Cx, uint32_t Reg_Value) -{ - WRITE_REG(I2Cx->ADDR2, Reg_Value); -} - -/** - * @brief Get I2C ADDR2 - * @note None - * @param I2Cx I2C Instance - * @retval a 32-bit value - */ -__STATIC_INLINE uint32_t md_i2c_get_addr2(I2C_TypeDef *I2Cx) -{ - return (uint32_t) (READ_REG(I2Cx->ADDR2)); -} - -/** - * @brief I2C own address register 2 Enable - * @param I2Cx I2C Instance - * @retval None - */ -__STATIC_INLINE void md_i2c_enable_addr2_oa2en(I2C_TypeDef *I2Cx) -{ - SET_BIT(I2Cx->ADDR2, I2C_ADDR2_OA2EN_MSK); -} - -/** - * @brief I2C own address register 2 Disable - * @param I2Cx I2C Instance - * @retval None - */ -__STATIC_INLINE void md_i2c_disable_addr2_oa2en(I2C_TypeDef *I2Cx) -{ - CLEAR_BIT(I2Cx->ADDR2, I2C_ADDR2_OA2EN_MSK); -} - -/** - * @brief Indicate if address register 2 is enabled - * @param I2Cx I2C Instance - * @retval State of bit (1 or 0). - */ -__STATIC_INLINE uint32_t md_i2c_is_enabled_addr2_oa2en(I2C_TypeDef *I2Cx) -{ - return (uint32_t)(READ_BIT(I2Cx->ADDR2, I2C_ADDR2_OA2EN_MSK) == (I2C_ADDR2_OA2EN_MSK)); -} - -/** - * @brief Set I2C own address2 mask - * @note These bits can be written only when OA2EN=0. - * As soon as OA2MSK is not equal to 0,the reserved I2C addresses(0b0000xxx and 0b1111xxx) are not acknowledged even if the comparison matches. - * @param I2Cx I2C Instance - * @param oa2_mask I2C own address2 mask - * @arg @ref MD_I2C_ADDR2_NOMASK - * @arg @ref MD_I2C_ADDR2_MASK01 - * @arg @ref MD_I2C_ADDR2_MASK02 - * @arg @ref MD_I2C_ADDR2_MASK03 - * @arg @ref MD_I2C_ADDR2_MASK04 - * @arg @ref MD_I2C_ADDR2_MASK05 - * @arg @ref MD_I2C_ADDR2_MASK06 - * @arg @ref MD_I2C_ADDR2_MASK07 - * @retval None - */ -__STATIC_INLINE void md_i2c_set_addr2_oa2mask(I2C_TypeDef *I2Cx, uint32_t oa2_mask) -{ - MODIFY_REG(I2Cx->ADDR2, I2C_ADDR2_OA2MSK_MSK, oa2_mask); -} - -/** - * @brief Get I2C address2 mask - * @note None - * As soon as OA2MSK is not equal to 0,the reserved I2C addresses(0b0000xxx and 0b1111xxx) are not acknowledged even if the comparison matches. - * @param I2Cx I2C Instance - * @retval I2C own address2 mask(value 0 to 7) - */ -__STATIC_INLINE uint32_t md_i2c_get_addr2_oa2mask(I2C_TypeDef *I2Cx) -{ - return (READ_BIT(I2Cx->ADDR2, I2C_ADDR2_OA2MSK_MSK)>>I2C_ADDR2_OA2MSK_POSS); -} - -/** - * @brief Set I2C own address2 - * @note These bits can be written only when OA2EN=0. - * @param I2Cx I2C Instance - * @param own_addr I2C own address2 - * @arg Max Value 0x7F - * @arg Min Value 0x1 - * @retval None - */ -__STATIC_INLINE void md_i2c_set_addr2_oa2(I2C_TypeDef *I2Cx, uint32_t own_addr) -{ - MODIFY_REG(I2Cx->ADDR2, I2C_ADDR2_OA2_MSK, own_addr <ADDR2, I2C_ADDR2_OA2_MSK)>>I2C_ADDR2_OA2_POSS); -} - -/** - * @brief Set I2C TIMINGR - * @note These bits must be configured when the I2C is disabled (PE = 0). - * @param I2Cx I2C Instance - * @param Reg_Value is a 32-bit value - * @retval None - */ -__STATIC_INLINE void md_i2c_set_timingr(I2C_TypeDef *I2Cx, uint32_t Reg_Value) -{ - WRITE_REG(I2Cx->TIMINGR, Reg_Value); -} - -/** - * @brief Get I2C TIMINGR - * @note None - * @param I2Cx I2C Instance - * @retval a 32-bit value - */ -__STATIC_INLINE uint32_t md_i2c_get_timingr(I2C_TypeDef *I2Cx) -{ - return (uint32_t) (READ_REG(I2Cx->TIMINGR)); -} - -/** - * @brief Set I2C Timing prescaler - * @note This register must be configured when the I2C is disabled(PE = 0) - * @param I2Cx I2C Instance - * @param timing_prescaler - * @arg Max Value 0xF - * @arg Min Value 0x0 - * @retval None - */ -__STATIC_INLINE void md_i2c_set_timingr_presc(I2C_TypeDef *I2Cx, uint32_t timing_prescaler) -{ - MODIFY_REG(I2Cx->TIMINGR, I2C_TIMINGR_PRESC_MSK, timing_prescaler << I2C_TIMINGR_PRESC_POSS); -} - -/** - * @brief Get I2C Timing prescaler - * @note This register must be configured when the I2C is disabled(PE = 0) - * @param I2Cx I2C Instance - * @retval timing_prescaler - * @arg Max Value 0xF - * @arg Min Value 0x0 - */ -__STATIC_INLINE uint32_t md_i2c_get_timingr_presc(I2C_TypeDef *I2Cx) -{ - return (READ_BIT(I2Cx->TIMINGR, I2C_TIMINGR_PRESC_MSK)>>I2C_TIMINGR_PRESC_POSS); -} - -/** - * @brief Set I2C date setup time - * @note This register must be configured when the I2C is disabled(PE = 0) - * @param I2Cx I2C Instance - * @param data_setup_time - * @arg Max Value 0xF - * @arg Min Value 0x0 - * @retval None - */ -__STATIC_INLINE void md_i2c_set_timingr_scldel(I2C_TypeDef *I2Cx, uint32_t data_setup_time) -{ - MODIFY_REG(I2Cx->TIMINGR, I2C_TIMINGR_SCLDEL_MSK, data_setup_time <TIMINGR, I2C_TIMINGR_SCLDEL_MSK)>>I2C_TIMINGR_SCLDEL_POSS); -} - -/** - * @brief Set I2C date hold time - * @note This register must be configured when the I2C is disabled(PE = 0) - * @param I2Cx I2C Instance - * @param data_hold_time - * @arg Max Value 0xF - * @arg Min Value 0x0 - * @retval None - */ -__STATIC_INLINE void md_i2c_set_timingr_sdadel(I2C_TypeDef *I2Cx, uint32_t data_hold_time) -{ - MODIFY_REG(I2Cx->TIMINGR, I2C_TIMINGR_SDADEL_MSK, data_hold_time << I2C_TIMINGR_SDADEL_POSS); -} - -/** - * @brief Get I2C date hold time - * @note This register must be configured when the I2C is disabled(PE = 0) - * @param I2Cx I2C Instance - * @retval data_hold_time - * @arg Max Value 0xF - * @arg Min Value 0x0 - */ -__STATIC_INLINE uint32_t md_i2c_get_timingr_sdadel(I2C_TypeDef *I2Cx) -{ - return (READ_BIT(I2Cx->TIMINGR, I2C_TIMINGR_SDADEL_MSK)>>I2C_TIMINGR_SDADEL_POSS); -} - -/** - * @brief Set I2C SCL high period(master mode) - * @note This register must be configured when the I2C is disabled(PE = 0) - * @param I2Cx I2C Instance - * @param SCL_hperiod - * @arg Max Value 0xFF - * @arg Min Value 0x0 - * @retval None - */ -__STATIC_INLINE void md_i2c_set_timingr_sclh(I2C_TypeDef *I2Cx, uint32_t SCL_hperiod) -{ - MODIFY_REG(I2Cx->TIMINGR, I2C_TIMINGR_SCLH_MSK, SCL_hperiod << I2C_TIMINGR_SCLH_POSS); -} - -/** - * @brief Get I2C SCL high period(master mode) - * @note This register must be configured when the I2C is disabled(PE = 0) - * @param I2Cx I2C Instance - * @retval SCL_hperiod - * @arg Max Value 0xFF - * @arg Min Value 0x0 - */ -__STATIC_INLINE uint32_t md_i2c_get_timingr_sclh(I2C_TypeDef *I2Cx) -{ - return (READ_BIT(I2Cx->TIMINGR, I2C_TIMINGR_SCLH_MSK)>>I2C_TIMINGR_SCLH_POSS); -} - -/** - * @brief Set I2C SCL low period(master mode) - * @note This register must be configured when the I2C is disabled(PE = 0) - * @param I2Cx I2C Instance - * @param SCL_lperiod - * @arg Max Value 0xFF - * @arg Min Value 0x0 - * @retval None - */ -__STATIC_INLINE void md_i2c_set_timingr_scll(I2C_TypeDef *I2Cx, uint32_t SCL_lperiod) -{ - MODIFY_REG(I2Cx->TIMINGR, I2C_TIMINGR_SCLL_MSK, SCL_lperiod << I2C_TIMINGR_SCLL_POSS); -} - -/** - * @brief Get I2C SCL low period(master mode) - * @note This register must be configured when the I2C is disabled(PE = 0) - * @param I2Cx I2C Instance - * @retval SCL_lperiod - * @arg Max Value 0xFF - * @arg Min Value 0x0 - */ -__STATIC_INLINE uint32_t md_i2c_get_timingr_scll(I2C_TypeDef *I2Cx) -{ - return (READ_BIT(I2Cx->TIMINGR, I2C_TIMINGR_SCLL_MSK)); -} - -/** - * @brief Set I2C TIMEOUTR - * @note These bits can be written only when TEXTEN=0 and TIMEOUTEN=0 except TEXTEN and TIMEOUTEN. - * @param I2Cx I2C Instance - * @param Reg_Value is a 32-bit value - * @retval None - */ -__STATIC_INLINE void md_i2c_set_timeoutr(I2C_TypeDef *I2Cx, uint32_t Reg_Value) -{ - WRITE_REG(I2Cx->TIMEOUTR, Reg_Value); -} - -/** - * @brief Get I2C TIMEOUTR - * @note None - * @param I2Cx I2C Instance - * @retval a 32-bit value - */ -__STATIC_INLINE uint32_t md_i2c_get_timeoutr(I2C_TypeDef *I2Cx) -{ - return (uint32_t) (READ_REG(I2Cx->TIMEOUTR)); -} - -/** - * @brief I2C Extended clock timeout Enable - * @note None - * @param I2Cx I2C Instance - * @retval None - */ -__STATIC_INLINE void md_i2c_enable_timeoutr_texten(I2C_TypeDef *I2Cx) -{ - SET_BIT(I2Cx->TIMEOUTR, I2C_TIMEOUTR_TEXTEN_MSK); -} - -/** - * @brief I2C Extended clock timeout Disable - * @note None - * @param I2Cx I2C Instance - * @retval None - */ -__STATIC_INLINE void md_i2c_disable_timeoutr_texten(I2C_TypeDef *I2Cx) -{ - CLEAR_BIT(I2Cx->TIMEOUTR, I2C_TIMEOUTR_TEXTEN_MSK); -} - -/** - * @brief Indicate if I2C Extended clock timeout is enabled - * @note None - * @param I2Cx I2C Instance - * @retval State of bit (1 or 0). - */ -__STATIC_INLINE uint32_t md_i2c_is_enabled_timeoutr_texten(I2C_TypeDef *I2Cx) -{ - return (uint32_t)(READ_BIT(I2Cx->TIMEOUTR, I2C_TIMEOUTR_TEXTEN_MSK) == (I2C_TIMEOUTR_TEXTEN_MSK)); -} - -/** - * @brief Set I2C Bus timeout B - * @note These bits can be written only when TEXTEN = 0 - * @param I2Cx I2C Instance - * @param timeoutb Bus timeout B - * @arg Max Value 0xFFFFFF - * @arg Min Value 0x0 - * @retval None - */ -__STATIC_INLINE void md_i2c_set_timeoutr_timeoutb(I2C_TypeDef *I2Cx, uint32_t timeoutb) -{ - MODIFY_REG(I2Cx->TIMEOUTR, I2C_TIMEOUTR_TIMEOUTB_MSK, timeoutb << I2C_TIMEOUTR_TIMEOUTB_POSS); -} - -/** - * @brief Get I2C Bus timeout B - * @note These bits can be written only when TEXTEN = 0 - * @param I2Cx I2C Instance - * @retval Bus timeout B - * @arg Max Value 0xFFFFFF - * @arg Min Value 0x0 - */ -__STATIC_INLINE uint32_t md_i2c_get_timeoutr_timeoutb(I2C_TypeDef *I2Cx) -{ - return (READ_BIT(I2Cx->TIMEOUTR, I2C_TIMEOUTR_TIMEOUTB_MSK)>>I2C_TIMEOUTR_TIMEOUTB_POSS); -} - -/** - * @brief I2C clock timeout Enable - * @note None - * @param I2Cx I2C Instance - * @retval None - */ -__STATIC_INLINE void md_i2c_enable_timeoutr_timeouten(I2C_TypeDef *I2Cx) -{ - SET_BIT(I2Cx->TIMEOUTR, I2C_TIMEOUTR_TIMEOUTEN_MSK); -} - -/** - * @brief I2C clock timeout Disable - * @note None - * @param I2Cx I2C Instance - * @retval None - */ -__STATIC_INLINE void md_i2c_disable_timeoutr_timeouten(I2C_TypeDef *I2Cx) -{ - CLEAR_BIT(I2Cx->TIMEOUTR, I2C_TIMEOUTR_TIMEOUTEN_MSK); -} - -/** - * @brief Indicate if I2C clock timeout is enabled - * @note None - * @param I2Cx I2C Instance - * @retval State of bit (1 or 0). - */ -__STATIC_INLINE uint32_t md_i2c_is_enabled_timeoutr_timeouten(I2C_TypeDef *I2Cx) -{ - return (uint32_t)(READ_BIT(I2Cx->TIMEOUTR, I2C_TIMEOUTR_TIMEOUTEN_MSK) == (I2C_TIMEOUTR_TIMEOUTEN_MSK)); -} - -/** - * @brief Set I2C Tidle to decide a timeouta mode - * @note This bit can be written only when TIMOUTEN = 0 - * @param I2Cx I2C Instance - * @param tidle_mode - * @arg @ref MD_I2C_LOW_TIMEOUTA - * @arg @ref MD_I2C_IDLE_TIMEOUTA - * @retval None - */ -__STATIC_INLINE void md_i2c_set_timeoutr_tidle(I2C_TypeDef *I2Cx, uint32_t tidle_mode) -{ - MODIFY_REG(I2Cx->TIMEOUTR, I2C_TIMEOUTR_TIDLE_MSK, tidle_mode); -} - -/** - * @brief Get I2C Tidle to know a timeouta mode - * @note None - * @param I2Cx I2C Instance - * @retval State of bit (1 or 0). - */ -__STATIC_INLINE uint32_t md_i2c_get_timeoutr_tidle(I2C_TypeDef *I2Cx) -{ - return (READ_BIT(I2Cx->TIMEOUTR, I2C_TIMEOUTR_TIDLE_MSK)>>I2C_TIMEOUTR_TIDLE_POS); -} - -/** - * @brief Set I2C Bus timeout A - * @note These bits can be written only when TIMOUTEN = 0 - * @param I2Cx I2C Instance - * @param timeouta Bus timeout A - * @arg Max Value 0xFFFFFF - * @arg Min Value 0x0 - * @retval None - */ -__STATIC_INLINE void md_i2c_set_timeoutr_timeouta(I2C_TypeDef *I2Cx, uint32_t timeouta) -{ - MODIFY_REG(I2Cx->TIMEOUTR, I2C_TIMEOUTR_TIMEOUTA_MSK, timeouta << I2C_TIMEOUTR_TIMEOUTA_POSS); -} - -/** - * @brief Get I2C Bus timeout A - * @note These bits can be written only when TIMOUTEN = 0 - * @param I2Cx I2C Instance - * @retval Bus timeout A - * @arg Max Value 0xFFFFFF - * @arg Min Value 0x0 - */ -__STATIC_INLINE uint32_t md_i2c_get_timeoutr_timeouta(I2C_TypeDef *I2Cx) -{ - return (READ_BIT(I2Cx->TIMEOUTR, I2C_TIMEOUTR_TIMEOUTA_MSK)); -} - -/** - * @brief Get I2C STAT - * @note All bits are read-only - * @param I2Cx I2C Instance - * @retval a 32-bit value - */ -__STATIC_INLINE uint32_t md_i2c_get_stat(I2C_TypeDef *I2Cx) -{ - return (uint32_t) (READ_REG(I2Cx->STAT)); -} - -/** - * @brief Get address match code(slave mode) - * @note These bits are updated with the received address when an address match event occurs(ADDR=1). - * @param I2Cx I2C Instance - * @retval 7-bit received address value - */ -__STATIC_INLINE uint32_t md_i2c_get_stat_addcode(I2C_TypeDef *I2Cx) -{ - return (READ_BIT(I2Cx->STAT, I2C_STAT_ADDCODE_MSK)>>I2C_STAT_ADDCODE_POSS); -} - -/** - * @brief Get transfer direction(slave mode) - * @param I2Cx I2C Instance - * @retval State of bit (1 or 0). - */ -__STATIC_INLINE uint32_t md_i2c_get_stat_dir(I2C_TypeDef *I2Cx) -{ - return (READ_BIT(I2Cx->STAT, I2C_STAT_DIR_MSK)>>I2C_STAT_DIR_POS); -} - -/** - * @brief Indicate if I2C busy flag is active - * @param I2Cx I2C Instance - * @retval State of bit (1 or 0). - */ -__STATIC_INLINE uint32_t md_i2c_is_active_stat_busy(I2C_TypeDef *I2Cx) -{ - return (uint32_t)(READ_BIT(I2Cx->STAT, I2C_STAT_BUSY_MSK) == (I2C_STAT_BUSY_MSK)); -} - -/** - * @brief Indicate if I2C transfer complete reload flag (TCR) is active - * @note This bit is cleared by hardware when PE = 0. - * This flag is only for master mode,or for slave mode when the SBC bit is set - * @param I2Cx I2C Instance - * @retval State of bit (1 or 0). - */ -__STATIC_INLINE uint32_t md_i2c_is_active_stat_tcr(I2C_TypeDef *I2Cx) -{ - return (uint32_t)(READ_BIT(I2Cx->STAT, I2C_STAT_TCR_MSK) == (I2C_STAT_TCR_MSK)); -} - -/** - * @brief Indicate if I2C transfer complete flag (TC) is active - * @note This bit is cleared by hardware when PE = 0. - * @param I2Cx I2C Instance - * @retval State of bit (1 or 0). - */ -__STATIC_INLINE uint32_t md_i2c_is_active_stat_tc(I2C_TypeDef *I2Cx) -{ - return (uint32_t)(READ_BIT(I2Cx->STAT, I2C_STAT_TC_MSK) == (I2C_STAT_TC_MSK)); -} - -/** - * @brief Indicate if I2C Rx FIFO level over threshold flag (RXTH) is active - * @param I2Cx I2C Instance - * @retval State of bit (1 or 0). - */ -__STATIC_INLINE uint32_t md_i2c_is_active_stat_rxth(I2C_TypeDef *I2Cx) -{ - return (uint32_t)(READ_BIT(I2Cx->STAT, I2C_STAT_RXTH_MSK) == (I2C_STAT_RXTH_MSK)); -} - -/** - * @brief Indicate if I2C Rx buffer underflow flag (RXUD) is active - * @param I2Cx I2C Instance - * @retval State of bit (1 or 0). - */ -__STATIC_INLINE uint32_t md_i2c_is_active_stat_rxud(I2C_TypeDef *I2Cx) -{ - return (uint32_t)(READ_BIT(I2Cx->STAT, I2C_STAT_RXUD_MSK) == (I2C_STAT_RXUD_MSK)); -} - -/** - * @brief Indicate if I2C Rx buffer overflow flag (RXOV) is active - * @param I2Cx I2C Instance - * @retval State of bit (1 or 0). - */ -__STATIC_INLINE uint32_t md_i2c_is_active_stat_rxov(I2C_TypeDef *I2Cx) -{ - return (uint32_t)(READ_BIT(I2Cx->STAT, I2C_STAT_RXOV_MSK) == (I2C_STAT_RXOV_MSK)); -} - -/** - * @brief Indicate if I2C Rx buffer full flag (RXF) is active - * @param I2Cx I2C Instance - * @retval State of bit (1 or 0). - */ -__STATIC_INLINE uint32_t md_i2c_is_active_stat_rxf(I2C_TypeDef *I2Cx) -{ - return (uint32_t)(READ_BIT(I2Cx->STAT, I2C_STAT_RXF_MSK) == (I2C_STAT_RXF_MSK)); -} - -/** - * @brief Indicate if I2C Rx buffer empty flag (RXE) is active - * @param I2Cx I2C Instance - * @retval State of bit (1 or 0). - */ -__STATIC_INLINE uint32_t md_i2c_is_active_stat_rxe(I2C_TypeDef *I2Cx) -{ - return (uint32_t)(READ_BIT(I2Cx->STAT, I2C_STAT_RXE_MSK) == (I2C_STAT_RXE_MSK)); -} - -/** - * @brief Indicate if I2C Tx FIFO level over threshold flag (TXTH) is active - * @param I2Cx I2C Instance - * @retval State of bit (1 or 0). - */ -__STATIC_INLINE uint32_t md_i2c_is_active_stat_txth(I2C_TypeDef *I2Cx) -{ - return (uint32_t)(READ_BIT(I2Cx->STAT, I2C_STAT_TXTH_MSK) == (I2C_STAT_TXTH_MSK)); -} - -/** - * @brief Indicate if I2C Tx buffer underflow flag (TXUD) is active - * @param I2Cx I2C Instance - * @retval State of bit (1 or 0). - */ -__STATIC_INLINE uint32_t md_i2c_is_active_is_active_stat_txud(I2C_TypeDef *I2Cx) -{ - return (uint32_t)(READ_BIT(I2Cx->STAT, I2C_STAT_TXUD_MSK) == (I2C_STAT_TXUD_MSK)); -} - -/** - * @brief Indicate if I2C Tx buffer overflow flag (TXOV) is active - * @param I2Cx I2C Instance - * @retval State of bit (1 or 0). - */ -__STATIC_INLINE uint32_t md_i2c_is_active_stat_txov(I2C_TypeDef *I2Cx) -{ - return (uint32_t)(READ_BIT(I2Cx->STAT, I2C_STAT_TXOV_MSK) == (I2C_STAT_TXOV_MSK)); -} - -/** - * @brief Indicate if I2C Tx buffer full flag (TXF) is active - * @param I2Cx I2C Instance - * @retval State of bit (1 or 0). - */ -__STATIC_INLINE uint32_t md_i2c_is_active_stat_txf(I2C_TypeDef *I2Cx) -{ - return (uint32_t)(READ_BIT(I2Cx->STAT, I2C_STAT_TXF_MSK) == (I2C_STAT_TXF_MSK)); -} - -/** - * @brief Indicate if I2C Tx buffer empty flag (TXE) is active - * @param I2Cx I2C Instance - * @retval State of bit (1 or 0). - */ -__STATIC_INLINE uint32_t md_i2c_is_active_stat_txe(I2C_TypeDef *I2Cx) -{ - return (uint32_t)(READ_BIT(I2Cx->STAT, I2C_STAT_TXE_MSK) == (I2C_STAT_TXE_MSK)); -} - -/** - * @brief Set I2C FCON - * @note FIFO trigger threshold must be configured when the I2C is disabled (PE = 0). - * @param I2Cx I2C Instance - * @param Reg_Value is a 32-bit value - * @retval None - */ -__STATIC_INLINE void md_i2c_set_fcon(I2C_TypeDef *I2Cx, uint32_t Reg_Value) -{ - WRITE_REG(I2Cx->FCON, Reg_Value); -} - -/** - * @brief Get I2C FCON - * @note None - * @param I2Cx I2C Instance - * @retval a 32-bit value - */ -__STATIC_INLINE uint32_t md_i2c_get_fcon(I2C_TypeDef *I2Cx) -{ - return (uint32_t) (READ_REG(I2Cx->FCON)); -} - -/** - * @brief Set RXFIFO trigger threshold - * @note Receive FIFO trigger threshold must be configured when the I2C is disabled (PE = 0). - * @param I2Cx I2C Instance - * @param rxfifo_trigger_threshold This parameter can be one of the following values: - * @arg @ref MD_I2C_RXFIFO_THRESHOLD_RX1 - * @arg @ref MD_I2C_RXFIFO_THRESHOLD_RX4 - * @arg @ref MD_I2C_RXFIFO_THRESHOLD_RX8 - * @arg @ref MD_I2C_RXFIFO_THRESHOLD_RX14 - * @retval None - */ -__STATIC_INLINE void md_i2c_set_fcon_rxfth(I2C_TypeDef *I2Cx, uint32_t rxfifo_trigger_threshold) -{ - MODIFY_REG(I2Cx->FCON, I2C_FCON_RXFTH_MSK, rxfifo_trigger_threshold); -} - -/** - * @brief Get RXFIFO trigger threshold - * @note None - * @param I2Cx I2C Instance - * @retval The retval can be 0 to 3 - */ -__STATIC_INLINE uint32_t md_i2c_get_fcon_rxfth(I2C_TypeDef *I2Cx) -{ - return (READ_BIT(I2Cx->FCON, I2C_FCON_RXFTH_MSK)>>I2C_FCON_RXFTH_POSS); -} - -/** - * @brief Set I2C RXFIFO reset - * @note None - * @param I2Cx I2C Instance - * @arg @ref MD_I2C_RXFIFO_RESET - * @retval None - */ -__STATIC_INLINE void md_i2c_set_fcon_rxfrst(I2C_TypeDef *I2Cx, uint32_t reset) -{ - MODIFY_REG(I2Cx->FCON, I2C_FCON_RXFRST_MSK, reset); -} - -/** - * @brief Get I2C RXFIFO level - * @note None - * @param I2Cx I2C Instance - * @retval It's from 0 to 16 - */ -__STATIC_INLINE uint32_t md_i2c_get_rxfifo_level(I2C_TypeDef *I2Cx) -{ - return (READ_BIT(I2Cx->FCON, I2C_FCON_RXFLV_MSK)>>I2C_FCON_RXFLV_POSS); -} - -/** - * @brief Set TXFIFO trigger threshold - * @param I2Cx I2C Instance - * @param txfifo_trigger_threshold This parameter can be one of the following values: - * @arg @ref MD_I2C_TXFIFO_THRESHOLD_TX0 - * @arg @ref MD_I2C_TXFIFO_THRESHOLD_TX2 - * @arg @ref MD_I2C_TXFIFO_THRESHOLD_TX4 - * @arg @ref MD_I2C_TXFIFO_THRESHOLD_TX8 - * @retval None - */ -__STATIC_INLINE void md_i2c_set_fcon_txfth(I2C_TypeDef *I2Cx, uint32_t txfifo_trigger_threshold) -{ - MODIFY_REG(I2Cx->FCON, I2C_FCON_TXFTH_MSK, txfifo_trigger_threshold); -} - -/** - * @brief Get TXFIFO trigger threshold - * @param I2Cx I2C Instance - * @retval It's from 0 to 3 - */ -__STATIC_INLINE uint32_t md_i2c_get_txfifo_trigger_threshold(I2C_TypeDef *I2Cx) -{ - return (READ_BIT(I2Cx->FCON, I2C_FCON_TXFTH_MSK)>>I2C_FCON_TXFTH_POSS); -} - -/** - * @brief I2C TXFIFO reset - * @note None - * @param I2Cx I2C Instance - * @arg @ref MD_I2C_TXFIFO_RESET - * @retval None - */ -__STATIC_INLINE void md_i2c_set_fcon_txfrst(I2C_TypeDef *I2Cx, uint32_t reset) -{ - MODIFY_REG(I2Cx->FCON, I2C_FCON_TXFRST_MSK, reset); -} - -/** - * @brief Get TXFIFO level - * @note None - * @param I2Cx I2C Instance - * @retval It's from 0 to 16 - */ -__STATIC_INLINE uint32_t md_i2c_get_txfifo_level(I2C_TypeDef *I2Cx) -{ - return (READ_BIT(I2Cx->FCON, I2C_FCON_TXFLV_MSK)); -} - -/** - * @brief Get packet error checking register - * @note None - * @param I2Cx I2C Instance - * @retval 8-bit pec value - */ -__STATIC_INLINE uint32_t md_i2c_get_pecr_pec(I2C_TypeDef *I2Cx) -{ - return (READ_BIT(I2Cx->PECR, I2C_PECR_PEC_MSK)); -} - -/** - * @brief 8-bit receive data - * @note None - * @param I2Cx I2C Instance - * @retval 8-bit receive data - */ -__STATIC_INLINE uint32_t md_i2c_recv(I2C_TypeDef *I2Cx) -{ - return (READ_BIT(I2Cx->RXDATA, I2C_RXDATA_RXDATA_MSK)); -} - -/** - * @brief 8-bit transmit data - * @note These bits can be written only when TXE = 1. - * @param I2Cx I2C Instance - * @param txdata Transmit Data - * @arg Max value 0xFF - * @arg Min value 0 - * @retval None - */ -__STATIC_INLINE void md_i2c_send(I2C_TypeDef *I2Cx, uint32_t txdata) -{ - MODIFY_REG(I2Cx->TXDATA, I2C_TXDATA_TXDATA_MSK, txdata); -} - -/** - * @brief Set I2C IER - * @note None - * @param I2Cx I2C Instance - * @param ier - * @retval None - */ -__STATIC_INLINE void md_i2c_set_ier(I2C_TypeDef *I2Cx, uint32_t ier) -{ - WRITE_REG(I2Cx->IER, ier); -} - -/** - * @brief Enable SMBus alert interrupt - * @note None - * @param I2Cx I2C Instance - * @retval None - */ -__STATIC_INLINE void md_i2c_enable_ier_alertie(I2C_TypeDef *I2Cx) -{ - SET_BIT(I2Cx->IER, I2C_IER_ALERTIE_MSK); -} - -/** - * @brief Enable timeout interrupt - * @note None - * @param I2Cx I2C Instance - * @retval None - */ -__STATIC_INLINE void md_i2c_enable_ier_toutie(I2C_TypeDef *I2Cx) -{ - SET_BIT(I2Cx->IER, I2C_IER_TOUTIE_MSK); -} - -/** - * @brief Enable PEC error interrupt - * @note None - * @param I2Cx I2C Instance - * @retval None - */ -__STATIC_INLINE void md_i2c_enable_ier_peceie(I2C_TypeDef *I2Cx) -{ - SET_BIT(I2Cx->IER, I2C_IER_PECEIE_MSK); -} - -/** - * @brief Enable arbitration loss interrupt - * @note None - * @param I2Cx I2C Instance - * @retval None - */ -__STATIC_INLINE void md_i2c_enable_ier_arloie(I2C_TypeDef *I2Cx) -{ - SET_BIT(I2Cx->IER, I2C_IER_ARLOIE_MSK); -} - -/** - * @brief Enable bus error interrupt - * @note None - * @param I2Cx I2C Instance - * @retval None - */ -__STATIC_INLINE void md_i2c_enable_ier_berrie(I2C_TypeDef *I2Cx) -{ - SET_BIT(I2Cx->IER, I2C_IER_BERRIE_MSK); -} - -/** - * @brief Enable stop detection interrupt - * @note None - * @param I2Cx I2C Instance - * @retval None - */ -__STATIC_INLINE void md_i2c_enable_ier_stopie(I2C_TypeDef *I2Cx) -{ - SET_BIT(I2Cx->IER, I2C_IER_STOPIE_MSK); -} - -/** - * @brief Enable NACK reception interrupt - * @note None - * @param I2Cx I2C Instance - * @retval None - */ -__STATIC_INLINE void md_i2c_enable_ier_nackie(I2C_TypeDef *I2Cx) -{ - SET_BIT(I2Cx->IER, I2C_IER_NACKIE_MSK); -} - -/** - * @brief Enable address matched interrupt - * @note None - * @param I2Cx I2C Instance - * @retval None - */ -__STATIC_INLINE void md_i2c_enable_ier_addrie(I2C_TypeDef *I2Cx) -{ - SET_BIT(I2Cx->IER, I2C_IER_ADDRIE_MSK); -} - -/** - * @brief Enable transfer complete and reload interrupt - * @note None - * @param I2Cx I2C Instance - * @retval None - */ -__STATIC_INLINE void md_i2c_enable_ier_tcrie(I2C_TypeDef *I2Cx) -{ - SET_BIT(I2Cx->IER, I2C_IER_TCRIE_MSK); -} - -/** - * @brief Enable transfer complete interrupt - * @note None - * @param I2Cx I2C Instance - * @retval None - */ -__STATIC_INLINE void md_i2c_enable_ier_tcie(I2C_TypeDef *I2Cx) -{ - SET_BIT(I2Cx->IER, I2C_IER_TCIE_MSK); -} - -/** - * @brief Enable receive buffer over threshold interrupt - * @note None - * @param I2Cx I2C Instance - * @retval None - */ -__STATIC_INLINE void md_i2c_enable_ier_rxthie(I2C_TypeDef *I2Cx) -{ - SET_BIT(I2Cx->IER, I2C_IER_RXTHIE_MSK); -} - -/** - * @brief Enable receive buffer underrun interrupt - * @note None - * @param I2Cx I2C Instance - * @retval None - */ -__STATIC_INLINE void md_i2c_enable_ier_rxudie(I2C_TypeDef *I2Cx) -{ - SET_BIT(I2Cx->IER, I2C_IER_RXUDIE_MSK); -} - -/** - * @brief Enable receive buffer ovrun interrupt - * @note None - * @param I2Cx I2C Instance - * @retval None - */ -__STATIC_INLINE void md_i2c_enable_ier_rxovie(I2C_TypeDef *I2Cx) -{ - SET_BIT(I2Cx->IER, I2C_IER_RXOVIE_MSK); -} - -/** - * @brief Enable receive buffer full interrupt - * @note None - * @param I2Cx I2C Instance - * @retval None - */ -__STATIC_INLINE void md_i2c_enable_ier_rxfie(I2C_TypeDef *I2Cx) -{ - SET_BIT(I2Cx->IER, I2C_IER_RXFIE_MSK); -} - -/** - * @brief Enable transmit buffer under threshold interrupt - * @note None - * @param I2Cx I2C Instance - * @retval None - */ -__STATIC_INLINE void md_i2c_enable_ier_txthie(I2C_TypeDef *I2Cx) -{ - SET_BIT(I2Cx->IER, I2C_IER_TXTHIE_MSK); -} - -/** - * @brief Enable transmit buffer underrun interrupt - * @note None - * @param I2Cx I2C Instance - * @retval None - */ -__STATIC_INLINE void md_i2c_enable_ier_txudie(I2C_TypeDef *I2Cx) -{ - SET_BIT(I2Cx->IER, I2C_IER_TXUDIE_MSK); -} - -/** - * @brief Enable transmit buffer ovrun interrupt - * @note None - * @param I2Cx I2C Instance - * @retval None - */ -__STATIC_INLINE void md_i2c_enable_ier_txovie(I2C_TypeDef *I2Cx) -{ - SET_BIT(I2Cx->IER, I2C_IER_TXOVIE_MSK); -} - -/** - * @brief Enable transmit buffer empty interrupt - * @note None - * @param I2Cx I2C Instance - * @retval None - */ -__STATIC_INLINE void md_i2c_enable_ier_txeie(I2C_TypeDef *I2Cx) -{ - SET_BIT(I2Cx->IER, I2C_IER_TXEIE_MSK); -} - -/** - * @brief Set I2C IDR - * @note None - * @param I2Cx I2C Instance - * @param ier - * @retval None - */ -__STATIC_INLINE void md_i2c_set_idr(I2C_TypeDef *I2Cx, uint32_t idr) -{ - WRITE_REG(I2Cx->IDR, idr); -} - -/** - * @brief Disable SMBus alert interrupt - * @note None - * @param I2Cx I2C Instance - * @retval None - */ -__STATIC_INLINE void md_i2c_disable_idr_alertid(I2C_TypeDef *I2Cx) -{ - CLEAR_BIT(I2Cx->IDR, I2C_IDR_ALERTID_MSK); -} - -/** - * @brief Disable timeout interrupt - * @note None - * @param I2Cx I2C Instance - * @retval None - */ -__STATIC_INLINE void md_i2c_disable_idr_toutid(I2C_TypeDef *I2Cx) -{ - CLEAR_BIT(I2Cx->IDR, I2C_IDR_TOUTID_MSK); -} - -/** - * @brief Disable PEC error interrupt - * @note None - * @param I2Cx I2C Instance - * @retval None - */ -__STATIC_INLINE void md_i2c_disable_idr_peceid(I2C_TypeDef *I2Cx) -{ - CLEAR_BIT(I2Cx->IDR, I2C_IDR_PECEID_MSK); -} - -/** - * @brief Disable arbitration loss interrupt - * @note None - * @param I2Cx I2C Instance - * @retval None - */ -__STATIC_INLINE void md_i2c_disable_idr_arloid(I2C_TypeDef *I2Cx) -{ - CLEAR_BIT(I2Cx->IDR, I2C_IDR_ARLOID_MSK); -} - -/** - * @brief Disable bus error interrupt. - * @note None - * @param I2Cx I2C Instance - * @retval None - */ -__STATIC_INLINE void md_i2c_disable_idr_berrid(I2C_TypeDef *I2Cx) -{ - CLEAR_BIT(I2Cx->IDR, I2C_IDR_BERRID_MSK); -} - -/** - * @brief Disable stop detection interrupt - * @note None - * @param I2Cx I2C Instance - * @retval None - */ -__STATIC_INLINE void md_i2c_disable_idr_stopid(I2C_TypeDef *I2Cx) -{ - CLEAR_BIT(I2Cx->IDR, I2C_IDR_STOPID_MSK); -} - -/** - * @brief Disable NACK reception interrupt - * @note None - * @param I2Cx I2C Instance - * @retval None - */ -__STATIC_INLINE void md_i2c_disable_idr_nackid(I2C_TypeDef *I2Cx) -{ - CLEAR_BIT(I2Cx->IDR, I2C_IDR_NACKID_MSK); -} - -/** - * @brief Disable address matched interrupt - * @note None - * @param I2Cx I2C Instance - * @retval None - */ -__STATIC_INLINE void md_i2c_disable_idr_addrid(I2C_TypeDef *I2Cx) -{ - CLEAR_BIT(I2Cx->IDR, I2C_IDR_ADDRID_MSK); -} - -/** - * @brief Disable transfer complete and reload interrupt - * @note None - * @param I2Cx I2C Instance - * @retval None - */ -__STATIC_INLINE void md_i2c_disable_idr_tcrid(I2C_TypeDef *I2Cx) -{ - CLEAR_BIT(I2Cx->IDR, I2C_IDR_TCRID_MSK); -} - -/** - * @brief Disable transfer complete interrupt - * @note None - * @param I2Cx I2C Instance - * @retval None - */ -__STATIC_INLINE void md_i2c_disable_idr_tcid(I2C_TypeDef *I2Cx) -{ - CLEAR_BIT(I2Cx->IDR, I2C_IDR_TCID_MSK); -} - -/** - * @brief Disable receive buffer over threshold interrupt - * @note None - * @param I2Cx I2C Instance - * @retval None - */ -__STATIC_INLINE void md_i2c_disable_idr_rxthid(I2C_TypeDef *I2Cx) -{ - CLEAR_BIT(I2Cx->IDR, I2C_IDR_RXTHID_MSK); -} - -/** - * @brief Disable receive buffer underrun interrupt - * @note None - * @param I2Cx I2C Instance - * @retval None - */ -__STATIC_INLINE void md_i2c_disable_idr_rxudid(I2C_TypeDef *I2Cx) -{ - CLEAR_BIT(I2Cx->IDR, I2C_IDR_RXUDID_MSK); -} - -/** - * @brief Disable receive buffer ovrun interrupt - * @note None - * @param I2Cx I2C Instance - * @retval None - */ -__STATIC_INLINE void md_i2c_disable_idr_rxovid(I2C_TypeDef *I2Cx) -{ - CLEAR_BIT(I2Cx->IDR, I2C_IDR_RXOVID_MSK); -} - -/** - * @brief Disable receive buffer full interrupt - * @note None - * @param I2Cx I2C Instance - * @retval None - */ -__STATIC_INLINE void md_i2c_disable_idr_rxfid(I2C_TypeDef *I2Cx) -{ - CLEAR_BIT(I2Cx->IDR, I2C_IDR_RXFID_MSK); -} - -/** - * @brief Disable transmit buffer under threshold interrupt - * @note None - * @param I2Cx I2C Instance - * @retval None - */ -__STATIC_INLINE void md_i2c_disable_idr_txthid(I2C_TypeDef *I2Cx) -{ - CLEAR_BIT(I2Cx->IDR, I2C_IDR_TXTHID_MSK); -} - -/** - * @brief Disable transmit buffer underrun interrupt - * @note None - * @param I2Cx I2C Instance - * @retval None - */ -__STATIC_INLINE void md_i2c_disable_idr_txudid(I2C_TypeDef *I2Cx) -{ - CLEAR_BIT(I2Cx->IDR, I2C_IDR_TXUDID_MSK); -} - -/** - * @brief Disable transmit buffer ovrun interrupt - * @note None - * @param I2Cx I2C Instance - * @retval None - */ -__STATIC_INLINE void md_i2c_disable_idr_txovid(I2C_TypeDef *I2Cx) -{ - CLEAR_BIT(I2Cx->IDR, I2C_IDR_TXOVID_MSK); -} - -/** - * @brief Disable transmit buffer empty interrupt - * @note None - * @param I2Cx I2C Instance - * @retval None - */ -__STATIC_INLINE void md_i2c_disable_idr_txeid(I2C_TypeDef *I2Cx) -{ - CLEAR_BIT(I2Cx->IDR, I2C_IDR_TXEID_MSK); -} - -/** - * @brief Get I2C IVS - * @note None - * @param I2Cx I2C Instance - * @retval a 32-bit value - */ -__STATIC_INLINE uint32_t md_i2c_get_ivs(I2C_TypeDef *I2Cx) -{ - return (uint32_t) (READ_REG(I2Cx->IVS)); -} - -/** - * @brief Check if SMBus alert interrupt is enabled - * @note None - * @param I2Cx I2C Instance - * @retval State of bit (1 or 0). - */ -__STATIC_INLINE uint32_t md_i2c_is_enabled_ivs_alertiv(I2C_TypeDef *I2Cx) -{ - return (READ_BIT(I2Cx->IVS, I2C_IVS_ALERTIV_MSK) == (I2C_IVS_ALERTIV_MSK)); -} - -/** - * @brief Check if timeout interrupt is enabled - * @note None - * @param I2Cx I2C Instance - * @retval State of bit (1 or 0). - */ -__STATIC_INLINE uint32_t md_i2c_is_enabled_ivs_toutiv(I2C_TypeDef *I2Cx) -{ - return (READ_BIT(I2Cx->IVS, I2C_IVS_TOUTIV_MSK) == (I2C_IVS_TOUTIV_MSK)); -} - -/** - * @brief Check if PEC error interrupt is enabled - * @note None - * @param I2Cx I2C Instance - * @retval State of bit (1 or 0). - */ -__STATIC_INLINE uint32_t md_i2c_is_enabled_ivs_peceiv(I2C_TypeDef *I2Cx) -{ - return (READ_BIT(I2Cx->IVS, I2C_IVS_PECEIV_MSK) == (I2C_IVS_PECEIV_MSK)); -} - -/** - * @brief Check if arbitration loss interrupt is enabled - * @note None - * @param I2Cx I2C Instance - * @retval State of bit (1 or 0). - */ -__STATIC_INLINE uint32_t md_i2c_is_enabled_ivs_arloiv(I2C_TypeDef *I2Cx) -{ - return (READ_BIT(I2Cx->IVS, I2C_IVS_ARLOIV_MSK) == (I2C_IVS_ARLOIV_MSK)); -} - -/** - * @brief Check if bus error interrupt is enabled - * @note None - * @param I2Cx I2C Instance - * @retval State of bit (1 or 0). - */ -__STATIC_INLINE uint32_t md_i2c_is_enabled_ivs_berriv(I2C_TypeDef *I2Cx) -{ - return (READ_BIT(I2Cx->IVS, I2C_IVS_BERRIV_MSK) == (I2C_IVS_BERRIV_MSK)); -} - -/** - * @brief Check if stop detection interrupt is enabled - * @note None - * @param I2Cx I2C Instance - * @retval State of bit (1 or 0). - */ -__STATIC_INLINE uint32_t md_i2c_is_enabled_ivs_stopiv(I2C_TypeDef *I2Cx) -{ - return (READ_BIT(I2Cx->IVS, I2C_IVS_STOPIV_MSK) == (I2C_IVS_STOPIV_MSK)); -} - -/** - * @brief Check if NACK reception interrupt is enabled - * @note None - * @param I2Cx I2C Instance - * @retval State of bit (1 or 0). - */ -__STATIC_INLINE uint32_t md_i2c_is_enabled_ivs_nackiv(I2C_TypeDef *I2Cx) -{ - return (READ_BIT(I2Cx->IVS, I2C_IVS_NACKIV_MSK) == (I2C_IVS_NACKIV_MSK)); -} - -/** - * @brief Check if address matched interrupt is enabled - * @note None - * @param I2Cx I2C Instance - * @retval State of bit (1 or 0). - */ -__STATIC_INLINE uint32_t md_i2c_is_enabled_ivs_addriv(I2C_TypeDef *I2Cx) -{ - return (READ_BIT(I2Cx->IVS, I2C_IVS_ADDRIV_MSK) == (I2C_IVS_ADDRIV_MSK)); -} - -/** - * @brief Check if transfer complete and reload interrupt is enabled - * @note None - * @param I2Cx I2C Instance - * @retval State of bit (1 or 0). - */ -__STATIC_INLINE uint32_t md_i2c_is_enabled_ivs_tcriv(I2C_TypeDef *I2Cx) -{ - return (READ_BIT(I2Cx->IVS, I2C_IVS_TCRIV_MSK) == (I2C_IVS_TCRIV_MSK)); -} - -/** - * @brief Check if transfer complete interrupt is enabled - * @note None - * @param I2Cx I2C Instance - * @retval State of bit (1 or 0). - */ -__STATIC_INLINE uint32_t md_i2c_is_enabled_ivs_tciv(I2C_TypeDef *I2Cx) -{ - return (READ_BIT(I2Cx->IVS, I2C_IVS_TCIV_MSK) == (I2C_IVS_TCIV_MSK)); -} - -/** - * @brief Check if receive buffer over threshold interrupt is enabled - * @note None - * @param I2Cx I2C Instance - * @retval State of bit (1 or 0). - */ -__STATIC_INLINE uint32_t md_i2c_is_enabled_ivs_rxthiv(I2C_TypeDef *I2Cx) -{ - return (READ_BIT(I2Cx->IVS, I2C_IVS_RXTHIV_MSK) == (I2C_IVS_RXTHIV_MSK)); -} - -/** - * @brief Check if receive buffer underrun interrupt is enabled - * @note None - * @param I2Cx I2C Instance - * @retval State of bit (1 or 0). - */ -__STATIC_INLINE uint32_t md_i2c_is_enabled_ivs_rxudiv(I2C_TypeDef *I2Cx) -{ - return (READ_BIT(I2Cx->IVS, I2C_IVS_RXUDIV_MSK) == (I2C_IVS_RXUDIV_MSK)); -} - -/** - * @brief Check if receive buffer ovrun interrupt is enabled - * @note None - * @param I2Cx I2C Instance - * @retval State of bit (1 or 0). - */ -__STATIC_INLINE uint32_t md_i2c_is_enabled_ivs_rxoviv(I2C_TypeDef *I2Cx) -{ - return (READ_BIT(I2Cx->IVS, I2C_IVS_RXOVIV_MSK) == (I2C_IVS_RXOVIV_MSK)); -} - -/** - * @brief Check if receive buffer full interrupt is enabled - * @note None - * @param I2Cx I2C Instance - * @retval State of bit (1 or 0). - */ -__STATIC_INLINE uint32_t md_i2c_is_enabled_ivs_rxfiv(I2C_TypeDef *I2Cx) -{ - return (READ_BIT(I2Cx->IVS, I2C_IVS_RXFIV_MSK) == (I2C_IVS_RXFIV_MSK)); -} - -/** - * @brief Check if transmit buffer under threshold interrupt is enabled - * @note None - * @param I2Cx I2C Instance - * @retval State of bit (1 or 0). - */ -__STATIC_INLINE uint32_t md_i2c_is_enabled_ivs_txthiv(I2C_TypeDef *I2Cx) -{ - return (READ_BIT(I2Cx->IVS, I2C_IVS_TXTHIV_MSK) == (I2C_IVS_TXTHIV_MSK)); -} - -/** - * @brief Check if transmit buffer underrun interrupt is enabled - * @note None - * @param I2Cx I2C Instance - * @retval State of bit (1 or 0). - */ -__STATIC_INLINE uint32_t md_i2c_is_enabled_ivs_txudiv(I2C_TypeDef *I2Cx) -{ - return (READ_BIT(I2Cx->IVS, I2C_IVS_TXUDIV_MSK) == (I2C_IVS_TXUDIV_MSK)); -} - -/** - * @brief Check if transmit buffer ovrun interrupt is enabled - * @note None - * @param I2Cx I2C Instance - * @retval State of bit (1 or 0). - */ -__STATIC_INLINE uint32_t md_i2c_is_enabled_ivs_txoviv(I2C_TypeDef *I2Cx) -{ - return (READ_BIT(I2Cx->IVS, I2C_IVS_TXOVIV_MSK) == (I2C_IVS_TXOVIV_MSK)); -} - -/** - * @brief Check if transmit buffer empty interrupt is enabled - * @note None - * @param I2Cx I2C Instance - * @retval State of bit (1 or 0). - */ -__STATIC_INLINE uint32_t md_i2c_is_enabled_ivs_txeiv(I2C_TypeDef *I2Cx) -{ - return (READ_BIT(I2Cx->IVS, I2C_IVS_TXEIV_MSK) == (I2C_IVS_TXEIV_MSK)); -} - -/** - * @brief Get I2C RIF - * @note None - * @param I2Cx I2C Instance - * @retval a 32-bit value - */ -__STATIC_INLINE uint32_t md_i2c_get_rif(I2C_TypeDef *I2Cx) -{ - return (uint32_t) (READ_REG(I2Cx->RIF)); -} - -/** - * @brief Get SMBus alert raw interrupt flag - * @note None - * @param I2Cx I2C Instance - * @retval State of bit (1 or 0). - */ -__STATIC_INLINE uint32_t md_i2c_is_active_rif_alertri(I2C_TypeDef *I2Cx) -{ - return (READ_BIT(I2Cx->RIF, I2C_RIF_ALERTRI_MSK) == (I2C_RIF_ALERTRI_MSK)); -} - -/** - * @brief Get timeout raw interrupt flag - * @note None - * @param I2Cx I2C Instance - * @retval State of bit (1 or 0). - */ -__STATIC_INLINE uint32_t md_i2c_is_active_rif_toutri(I2C_TypeDef *I2Cx) -{ - return (READ_BIT(I2Cx->RIF, I2C_RIF_TOUTRI_MSK) == (I2C_RIF_TOUTRI_MSK)); -} - -/** - * @brief Get PEC error raw interrupt flag - * @note None - * @param I2Cx I2C Instance - * @retval State of bit (1 or 0). - */ -__STATIC_INLINE uint32_t md_i2c_is_active_rif_peceri(I2C_TypeDef *I2Cx) -{ - return (READ_BIT(I2Cx->RIF, I2C_RIF_PECERI_MSK) == (I2C_RIF_PECERI_MSK)); -} - -/** - * @brief Get arbitration loss raw interrupt flag - * @note None - * @param I2Cx I2C Instance - * @retval State of bit (1 or 0). - */ -__STATIC_INLINE uint32_t md_i2c_is_active_rif_arlori(I2C_TypeDef *I2Cx) -{ - return (READ_BIT(I2Cx->RIF, I2C_RIF_ARLORI_MSK) == (I2C_RIF_ARLORI_MSK)); -} - -/** - * @brief Get bus error raw interrupt flag - * @note None - * @param I2Cx I2C Instance - * @retval State of bit (1 or 0). - */ -__STATIC_INLINE uint32_t md_i2c_is_active_rif_berrri(I2C_TypeDef *I2Cx) -{ - return (READ_BIT(I2Cx->RIF, I2C_RIF_BERRRI_MSK) == (I2C_RIF_BERRRI_MSK)); -} - -/** - * @brief Get stop detection raw interrupt flag - * @note None - * @param I2Cx I2C Instance - * @retval State of bit (1 or 0). - */ -__STATIC_INLINE uint32_t md_i2c_is_active_rif_stopri(I2C_TypeDef *I2Cx) -{ - return (READ_BIT(I2Cx->RIF, I2C_RIF_STOPRI_MSK) == (I2C_RIF_STOPRI_MSK)); -} - -/** - * @brief Get NACK reception raw interrupt flag - * @note None - * @param I2Cx I2C Instance - * @retval State of bit (1 or 0). - */ -__STATIC_INLINE uint32_t md_i2c_is_active_rif_nackri(I2C_TypeDef *I2Cx) -{ - return (READ_BIT(I2Cx->RIF, I2C_RIF_NACKRI_MSK) == (I2C_RIF_NACKRI_MSK)); -} - -/** - * @brief Get address matched raw interrupt flag - * @note None - * @param I2Cx I2C Instance - * @retval State of bit (1 or 0). - */ -__STATIC_INLINE uint32_t md_i2c_is_active_rif_addrri(I2C_TypeDef *I2Cx) -{ - return (READ_BIT(I2Cx->RIF, I2C_RIF_ADDRRI_MSK) == (I2C_RIF_ADDRRI_MSK)); -} - -/** - * @brief Get transfer complete and reload raw interrupt flag - * @note None - * @param I2Cx I2C Instance - * @retval State of bit (1 or 0). - */ -__STATIC_INLINE uint32_t md_i2c_is_active_rif_tcrri(I2C_TypeDef *I2Cx) -{ - return (READ_BIT(I2Cx->RIF, I2C_RIF_TCRRI_MSK) == (I2C_RIF_TCRRI_MSK)); -} - -/** - * @brief Get transfer complete raw interrupt flag - * @note None - * @param I2Cx I2C Instance - * @retval State of bit (1 or 0). - */ -__STATIC_INLINE uint32_t md_i2c_is_active_rif_tcri(I2C_TypeDef *I2Cx) -{ - return (READ_BIT(I2Cx->RIF, I2C_RIF_TCRI_MSK) == (I2C_RIF_TCRI_MSK)); -} - -/** - * @brief Get receive buffer over threshold raw interrupt flag - * @note None - * @param I2Cx I2C Instance - * @retval State of bit (1 or 0). - */ -__STATIC_INLINE uint32_t md_i2c_is_active_rif_rxthri(I2C_TypeDef *I2Cx) -{ - return (READ_BIT(I2Cx->RIF, I2C_RIF_RXTHRI_MSK) == (I2C_RIF_RXTHRI_MSK)); -} - -/** - * @brief Get receive buffer underrun raw interrupt flag - * @note None - * @param I2Cx I2C Instance - * @retval State of bit (1 or 0). - */ -__STATIC_INLINE uint32_t md_i2c_is_active_rif_rxudri(I2C_TypeDef *I2Cx) -{ - return (READ_BIT(I2Cx->RIF, I2C_RIF_RXUDRI_MSK) == (I2C_RIF_RXUDRI_MSK)); -} - -/** - * @brief Get receive buffer ovrun raw interrupt flag - * @note None - * @param I2Cx I2C Instance - * @retval State of bit (1 or 0). - */ -__STATIC_INLINE uint32_t md_i2c_is_active_rif_rxovri(I2C_TypeDef *I2Cx) -{ - return (READ_BIT(I2Cx->RIF, I2C_RIF_RXOVRI_MSK) == (I2C_RIF_RXOVRI_MSK)); -} - -/** - * @brief Get receive buffer full raw interrupt flag - * @note None - * @param I2Cx I2C Instance - * @retval State of bit (1 or 0). - */ -__STATIC_INLINE uint32_t md_i2c_is_active_rif_rxfri(I2C_TypeDef *I2Cx) -{ - return (READ_BIT(I2Cx->RIF, I2C_RIF_RXFRI_MSK) == (I2C_RIF_RXFRI_MSK)); -} - -/** - * @brief Get transmit buffer under threshold raw interrupt flag - * @note None - * @param I2Cx I2C Instance - * @retval State of bit (1 or 0). - */ -__STATIC_INLINE uint32_t md_i2c_is_active_rif_txthri(I2C_TypeDef *I2Cx) -{ - return (READ_BIT(I2Cx->RIF, I2C_RIF_TXTHRI_MSK) == (I2C_RIF_TXTHRI_MSK)); -} - -/** - * @brief Get transmit buffer underrun raw interrupt flag - * @note None - * @param I2Cx I2C Instance - * @retval State of bit (1 or 0). - */ -__STATIC_INLINE uint32_t md_i2c_is_active_rif_txudri(I2C_TypeDef *I2Cx) -{ - return (READ_BIT(I2Cx->RIF, I2C_RIF_TXUDRI_MSK) == (I2C_RIF_TXUDRI_MSK)); -} - -/** - * @brief Get transmit buffer ovrun raw interrupt flag - * @note None - * @param I2Cx I2C Instance - * @retval State of bit (1 or 0). - */ -__STATIC_INLINE uint32_t md_i2c_is_active_rif_txovri(I2C_TypeDef *I2Cx) -{ - return (READ_BIT(I2Cx->RIF, I2C_RIF_TXOVRI_MSK) == (I2C_RIF_TXOVRI_MSK)); -} - -/** - * @brief Get transmit buffer empty raw interrupt flag - * @note None - * @param I2Cx I2C Instance - * @retval State of bit (1 or 0). - */ -__STATIC_INLINE uint32_t md_i2c_is_active_rif_txeri(I2C_TypeDef *I2Cx) -{ - return (READ_BIT(I2Cx->RIF, I2C_RIF_TXERI_MSK) == (I2C_RIF_TXERI_MSK)); -} - -/** - * @brief Set I2C ICR - * @note None - * @param I2Cx I2C Instance - * @param icr - * @retval None - */ -__STATIC_INLINE void md_i2c_set_icr(I2C_TypeDef *I2Cx, uint32_t icr) -{ - WRITE_REG(I2Cx->ICR, icr); -} - -/** - * @brief Clear SMBus alert raw interrupt flag - * @note None - * @param I2Cx I2C Instance - * @retval None - */ -__STATIC_INLINE void md_i2c_clear_icr_alertic(I2C_TypeDef *I2Cx) -{ - SET_BIT(I2Cx->ICR, I2C_ICR_ALERTIC_MSK); -} - -/** - * @brief Clear timeout raw interrupt flag - * @note None - * @param I2Cx I2C Instance - * @retval None - */ -__STATIC_INLINE void md_i2c_clear_icr_toutic(I2C_TypeDef *I2Cx) -{ - SET_BIT(I2Cx->ICR, I2C_ICR_TOUTIC_MSK); -} - -/** - * @brief Clear PEC error raw interrupt flag - * @note None - * @param I2Cx I2C Instance - * @retval None - */ -__STATIC_INLINE void md_i2c_clear_icr_peceic(I2C_TypeDef *I2Cx) -{ - SET_BIT(I2Cx->ICR, I2C_ICR_PECEIC_MSK); -} - -/** - * @brief Clear arbitration loss raw interrupt flag - * @note None - * @param I2Cx I2C Instance - * @retval None - */ -__STATIC_INLINE void md_i2c_clear_icr_arloic(I2C_TypeDef *I2Cx) -{ - SET_BIT(I2Cx->ICR, I2C_ICR_ARLOIC_MSK); -} - -/** - * @brief Clear bus error raw interrupt flag - * @note None - * @param I2Cx I2C Instance - * @retval None - */ -__STATIC_INLINE void md_i2c_clear_icr_berric(I2C_TypeDef *I2Cx) -{ - SET_BIT(I2Cx->ICR, I2C_ICR_BERRIC_MSK); -} - -/** - * @brief Clear stop detection raw interrupt flag - * @note None - * @param I2Cx I2C Instance - * @retval None - */ -__STATIC_INLINE void md_i2c_clear_icr_stopic(I2C_TypeDef *I2Cx) -{ - SET_BIT(I2Cx->ICR, I2C_ICR_STOPIC_MSK); -} - -/** - * @brief Clear NACK reception raw interrupt flag - * @note None - * @param I2Cx I2C Instance - * @retval None - */ -__STATIC_INLINE void md_i2c_clear_icr_nackic(I2C_TypeDef *I2Cx) -{ - SET_BIT(I2Cx->ICR, I2C_ICR_NACKIC_MSK); -} - -/** - * @brief Clear address matched raw interrupt flag - * @note None - * @param I2Cx I2C Instance - * @retval None - */ -__STATIC_INLINE void md_i2c_clear_icr_addric(I2C_TypeDef *I2Cx) -{ - SET_BIT(I2Cx->ICR, I2C_ICR_ADDRIC_MSK); -} - -/** - * @brief Clear transfer complete and reload raw interrupt flag - * @note None - * @param I2Cx I2C Instance - * @retval None - */ -__STATIC_INLINE void md_i2c_clear_icr_tcric(I2C_TypeDef *I2Cx) -{ - SET_BIT(I2Cx->ICR, I2C_ICR_TCRIC_MSK); -} - -/** - * @brief Clear transfer complete raw interrupt flag - * @note None - * @param I2Cx I2C Instance - * @retval None - */ -__STATIC_INLINE void md_i2c_clear_icr_tcic(I2C_TypeDef *I2Cx) -{ - SET_BIT(I2Cx->ICR, I2C_ICR_TCIC_MSK); -} - -/** - * @brief Clear receive buffer over threshold raw interrupt flag - * @note None - * @param I2Cx I2C Instance - * @retval None - */ -__STATIC_INLINE void md_i2c_clear_icr_rxthic(I2C_TypeDef *I2Cx) -{ - SET_BIT(I2Cx->ICR, I2C_ICR_RXTHIC_MSK); -} - -/** - * @brief Clear receive buffer underrun raw interrupt flag - * @note None - * @param I2Cx I2C Instance - * @retval None - */ -__STATIC_INLINE void md_i2c_clear_icr_rxudic(I2C_TypeDef *I2Cx) -{ - SET_BIT(I2Cx->ICR, I2C_ICR_RXUDIC_MSK); -} - -/** - * @brief Clear receive buffer ovrun raw interrupt flag - * @note None - * @param I2Cx I2C Instance - * @retval None - */ -__STATIC_INLINE void md_i2c_clear_icr_rxovic(I2C_TypeDef *I2Cx) -{ - SET_BIT(I2Cx->ICR, I2C_ICR_RXOVIC_MSK); -} - -/** - * @brief Clear receive buffer full raw interrupt flag - * @note None - * @param I2Cx I2C Instance - * @retval None - */ -__STATIC_INLINE void md_i2c_clear_icr_rxfic(I2C_TypeDef *I2Cx) -{ - SET_BIT(I2Cx->ICR, I2C_ICR_RXFIC_MSK); -} - -/** - * @brief Clear transmit buffer under threshold raw interrupt flag - * @note None - * @param I2Cx I2C Instance - * @retval None - */ -__STATIC_INLINE void md_i2c_clear_icr_txthic(I2C_TypeDef *I2Cx) -{ - SET_BIT(I2Cx->ICR, I2C_ICR_TXTHIC_MSK); -} - -/** - * @brief Clear transmit buffer underrun raw interrupt flag - * @note None - * @param I2Cx I2C Instance - * @retval None - */ -__STATIC_INLINE void md_i2c_clear_icr_txudic(I2C_TypeDef *I2Cx) -{ - SET_BIT(I2Cx->ICR, I2C_ICR_TXUDIC_MSK); -} - -/** - * @brief Clear transmit buffer ovrun raw interrupt flag - * @note None - * @param I2Cx I2C Instance - * @retval None - */ -__STATIC_INLINE void md_i2c_clear_icr_txovic(I2C_TypeDef *I2Cx) -{ - SET_BIT(I2Cx->ICR, I2C_ICR_TXOVIC_MSK); -} - -/** - * @brief Clear transmit buffer empty raw interrupt flag - * @note None - * @param I2Cx I2C Instance - * @retval None - */ -__STATIC_INLINE void md_i2c_clear_icr_txeic(I2C_TypeDef *I2Cx) -{ - SET_BIT(I2Cx->ICR, I2C_ICR_TXEIC_MSK); -} - -/** - * @brief Get I2C IFM - * @note None - * @param I2Cx I2C Instance - * @retval a 32-bit value - */ -__STATIC_INLINE uint32_t md_i2c_get_ifm(I2C_TypeDef *I2Cx) -{ - return (uint32_t) (READ_REG(I2Cx->IFM)); -} - -/** - * @brief Get SMBus alert interrupt flag massked status - * @note None - * @param I2Cx I2C Instance - * @retval State of bit (1 or 0). - */ -__STATIC_INLINE uint32_t md_i2c_is_active_ifm_alertfm(I2C_TypeDef *I2Cx) -{ - return (READ_BIT(I2Cx->IFM, I2C_IFM_ALERTFM_MSK) == (I2C_IFM_ALERTFM_MSK)); -} - -/** - * @brief Get timeout interrupt flag masked status - * @note None - * @param I2Cx I2C Instance - * @retval State of bit (1 or 0). - */ -__STATIC_INLINE uint32_t md_i2c_is_active_ifm_toutfm(I2C_TypeDef *I2Cx) -{ - return (READ_BIT(I2Cx->IFM, I2C_IFM_TOUTFM_MSK) == (I2C_IFM_TOUTFM_MSK)); -} - -/** - * @brief Get PEC error interrupt flag masked status - * @note None - * @param I2Cx I2C Instance - * @retval State of bit (1 or 0). - */ -__STATIC_INLINE uint32_t md_i2c_is_active_ifm_pecefm(I2C_TypeDef *I2Cx) -{ - return (READ_BIT(I2Cx->IFM, I2C_IFM_PECEFM_MSK) == (I2C_IFM_PECEFM_MSK)); -} - -/** - * @brief Get arbitration loss interrupt flag masked status - * @note None - * @param I2Cx I2C Instance - * @retval State of bit (1 or 0). - */ -__STATIC_INLINE uint32_t md_i2c_is_active_ifm_arlofm(I2C_TypeDef *I2Cx) -{ - return (READ_BIT(I2Cx->IFM, I2C_IFM_ARLOFM_MSK) == (I2C_IFM_ARLOFM_MSK)); -} - -/** - * @brief Get bus error interrupt flag masked status - * @note None - * @param I2Cx I2C Instance - * @retval State of bit (1 or 0). - */ -__STATIC_INLINE uint32_t md_i2c_is_active_ifm_berrfm(I2C_TypeDef *I2Cx) -{ - return (READ_BIT(I2Cx->IFM, I2C_IFM_BERRFM_MSK) == (I2C_IFM_BERRFM_MSK)); -} - -/** - * @brief Get stop detection interrupt flag masked status - * @note None - * @param I2Cx I2C Instance - * @retval State of bit (1 or 0). - */ -__STATIC_INLINE uint32_t md_i2c_is_active_ifm_stopfm(I2C_TypeDef *I2Cx) -{ - return (READ_BIT(I2Cx->IFM, I2C_IFM_STOPFM_MSK) == (I2C_IFM_STOPFM_MSK)); -} - -/** - * @brief Get NACK reception interrupt flag masked status - * @note None - * @param I2Cx I2C Instance - * @retval State of bit (1 or 0). - */ -__STATIC_INLINE uint32_t md_i2c_is_active_ifm_nackfm(I2C_TypeDef *I2Cx) -{ - return (READ_BIT(I2Cx->IFM, I2C_IFM_NACKFM_MSK) == (I2C_IFM_NACKFM_MSK)); -} - -/** - * @brief Get address matched interrupt flag masked status - * @note None - * @param I2Cx I2C Instance - * @retval State of bit (1 or 0). - */ -__STATIC_INLINE uint32_t md_i2c_is_active_ifm_addrfm(I2C_TypeDef *I2Cx) -{ - return (READ_BIT(I2Cx->IFM, I2C_IFM_ADDRFM_MSK) == (I2C_IFM_ADDRFM_MSK)); -} - -/** - * @brief Get transfer complete and reload interrupt flag masked status - * @note None - * @param I2Cx I2C Instance - * @retval State of bit (1 or 0). - */ -__STATIC_INLINE uint32_t md_i2c_is_active_ifm_tcrfm(I2C_TypeDef *I2Cx) -{ - return (READ_BIT(I2Cx->IFM, I2C_IFM_TCRFM_MSK) == (I2C_IFM_TCRFM_MSK)); -} - -/** - * @brief Get transfer complete interrupt flag masked status - * @note None - * @param I2Cx I2C Instance - * @retval State of bit (1 or 0). - */ -__STATIC_INLINE uint32_t md_i2c_is_active_ifm_tcfm(I2C_TypeDef *I2Cx) -{ - return (READ_BIT(I2Cx->IFM, I2C_IFM_TCFM_MSK) == (I2C_IFM_TCFM_MSK)); -} - -/** - * @brief Get receive buffer over threshold interrupt flag masked status - * @note None - * @param I2Cx I2C Instance - * @retval State of bit (1 or 0). - */ -__STATIC_INLINE uint32_t md_i2c_is_active_ifm_rxthfm(I2C_TypeDef *I2Cx) -{ - return (READ_BIT(I2Cx->IFM, I2C_IFM_RXTHFM_MSK) == (I2C_IFM_RXTHFM_MSK)); -} - -/** - * @brief Get receive buffer underrun interrupt flag masked status - * @note None - * @param I2Cx I2C Instance - * @retval State of bit (1 or 0). - */ -__STATIC_INLINE uint32_t md_i2c_is_active_ifm_rxudfm(I2C_TypeDef *I2Cx) -{ - return (READ_BIT(I2Cx->IFM, I2C_IFM_RXUDFM_MSK) == (I2C_IFM_RXUDFM_MSK)); -} - -/** - * @brief Get receive buffer ovrun interrupt flag masked status - * @note None - * @param I2Cx I2C Instance - * @retval State of bit (1 or 0). - */ -__STATIC_INLINE uint32_t md_i2c_is_active_ifm_rxovfm(I2C_TypeDef *I2Cx) -{ - return (READ_BIT(I2Cx->IFM, I2C_IFM_RXOVFM_MSK) == (I2C_IFM_RXOVFM_MSK)); -} - -/** - * @brief Get receive buffer full interrupt flag masked status - * @note None - * @param I2Cx I2C Instance - * @retval State of bit (1 or 0). - */ -__STATIC_INLINE uint32_t md_i2c_is_active_ifm_rxffm(I2C_TypeDef *I2Cx) -{ - return (READ_BIT(I2Cx->IFM, I2C_IFM_RXFFM_MSK) == (I2C_IFM_RXFFM_MSK)); -} - -/** - * @brief Get transmit buffer under threshold interrupt flag masked status - * @note None - * @param I2Cx I2C Instance - * @retval State of bit (1 or 0). - */ -__STATIC_INLINE uint32_t md_i2c_is_active_ifm_txthfm(I2C_TypeDef *I2Cx) -{ - return (READ_BIT(I2Cx->IFM, I2C_IFM_TXTHFM_MSK) == (I2C_IFM_TXTHFM_MSK)); -} - -/** - * @brief Get transmit buffer underrun interrupt flag masked status - * @note None - * @param I2Cx I2C Instance - * @retval State of bit (1 or 0). - */ -__STATIC_INLINE uint32_t md_i2c_is_active_ifm_txudfm(I2C_TypeDef *I2Cx) -{ - return (READ_BIT(I2Cx->IFM, I2C_IFM_TXUDFM_MSK) == (I2C_IFM_TXUDFM_MSK)); -} - -/** - * @brief Get transmit buffer ovrun interrupt flag masked status - * @note None - * @param I2Cx I2C Instance - * @retval State of bit (1 or 0). - */ -__STATIC_INLINE uint32_t md_i2c_is_active_ifm_txovfm(I2C_TypeDef *I2Cx) -{ - return (READ_BIT(I2Cx->IFM, I2C_IFM_TXOVFM_MSK) == (I2C_IFM_TXOVFM_MSK)); -} - -/** - * @brief Get transmit buffer empty interrupt flag masked status - * @note None - * @param I2Cx I2C Instance - * @retval State of bit (1 or 0). - */ -__STATIC_INLINE uint32_t md_i2c_is_active_ifm_txefm(I2C_TypeDef *I2Cx) -{ - return (READ_BIT(I2Cx->IFM, I2C_IFM_TXEFM_MSK) == (I2C_IFM_TXEFM_MSK)); -} - -/** - * @} MD_I2C_Public_Macros - */ - - - - - - -/* Public functions -----------------------------------------------------------*/ -/** @defgroup MD_I2C_Public_Functions I2C Public Functions - * @{ - */ - -/** @defgroup MD_I2C_PF_Basic_Configuration I2C Configuration - * @{ - */ - -//ErrorStatus md_i2c_deinit(I2C_TypeDef *I2Cx); -ErrorStatus md_i2c_init(I2C_TypeDef *I2Cx, md_i2c_inittypedef *I2C_InitStruct); -void md_i2c_struct_init(md_i2c_inittypedef *I2C_InitStruct); -void md_i2c_master_send(I2C_TypeDef *I2Cx, uint8_t Nbyte, uint32_t addr10, uint16_t DevAddr, uint8_t *txbuf); -void md_i2c_master_rece(I2C_TypeDef *I2Cx, uint8_t Nbyte, uint32_t addr10, uint16_t DevAddr, uint8_t *rxbuf); -void md_i2c_slave_send(I2C_TypeDef *I2Cx, uint8_t Num, uint8_t *txbuf); -void md_i2c_slave_rece(I2C_TypeDef *I2Cx, uint8_t Num, uint8_t *rxbuf); - -/** - * @} MD_I2C_PF_Init - */ - -/** - * @} MD_I2C_Public_Functions - */ - -#endif - -/* Private macros ------------------------------------------------------------*/ -/** @defgroup MD_I2C_Private_Macro I2C Private Macros - * @{ - */ -#define IS_MD_I2C_ALL_INSTANCE(__INSTANCE__) ((__INSTANCE__ == I2C1) \ - || (__INSTANCE__ == I2C2) \ - || (__INSTANCE__ == I2C3)) - -#define IS_MD_I2C_TIMING(__VALUE__) ((__VALUE__ == CLK10kHz8M) \ - || (__VALUE__ == CLK100kHz8M)) \ - || (__VALUE__ == CLK400kHz8M)) \ - || (__VALUE__ == CLK500kHz8M)) \ - || (__VALUE__ == CLK10kHz16M)) \ - || (__VALUE__ == CLK100kHz16M)) \ - || (__VALUE__ == CLK400kHz16M)) \ - || (__VALUE__ == CLK1000kHz16M)) \ - || (__VALUE__ == CLK10kHz48M)) \ - || (__VALUE__ == CLK100kHz48M)) \ - || (__VALUE__ == CLK400kHz48M)) \ - || (__VALUE__ == CLK1000kHz48M)) - -#define IS_MD_I2C_ADDRSIZE(__VALUE__) ((__VALUE__ == MD_I2C_ADDRESSINGMODE_7BIT) \ - || (__VALUE__ == MD_I2C_ADDRESSINGMODE_10BIT)) - -#define IS_MD_I2C_ADDRESS1(__VALUE__) (__VALUE__ <= 0x000003FFU) -#define IS_MD_I2C_ADDRESS2(__VALUE__) (__VALUE__ <= (uint16_t)0x00FFU) - -#define IS_MD_I2C_DUALADDRESSMODE(__VALUE__) ((__VALUE__ == MD_I2C_DUALADDRESS_DISABLE) \ - || (__VALUE__ == MD_I2C_DUALADDRESS_ENABLE)) -#define IS_MD_I2C_ADDRESS2MASKS(__VALUE__) ((__VALUE__ == MD_I2C_ADDR2_NOMASK) \ - || (__VALUE__ == MD_I2C_ADDR2_MASK01) \ - || (__VALUE__ == MD_I2C_ADDR2_MASK02) \ - || (__VALUE__ == MD_I2C_ADDR2_MASK03) \ - || (__VALUE__ == MD_I2C_ADDR2_MASK04) \ - || (__VALUE__ == MD_I2C_ADDR2_MASK05) \ - || (__VALUE__ == MD_I2C_ADDR2_MASK06) \ - || (__VALUE__ == MD_I2C_ADDR2_MASK07)) - -/** - * @} MD_I2C_Private_Macro - */ - -/** - * @} I2C - */ - -/** - * @} Micro_Driver - */ - -#ifdef __cplusplus -} -#endif - -#endif - -/******************* (C) COPYRIGHT Eastsoft Microelectronics *****END OF FILE****/ diff --git a/bsp/essemi/es32f0271/libraries/ES32F027x_MD_StdPeriph_Driver/Include/md_rcu.h b/bsp/essemi/es32f0271/libraries/ES32F027x_MD_StdPeriph_Driver/Include/md_rcu.h deleted file mode 100644 index 1b9b6ff09b..0000000000 --- a/bsp/essemi/es32f0271/libraries/ES32F027x_MD_StdPeriph_Driver/Include/md_rcu.h +++ /dev/null @@ -1,5804 +0,0 @@ -/** - ****************************************************************************** - * @file md_RCU.h - * @brief ES32F0271 RCU HEAD File. - * - * @version V1.00.02 - * @date 30/11/2018 - * @author Eastsoft AE Team - * @note - * detailed description - * - * Copyright (C) 2018 Shanghai Eastsoft Microelectronics Co., Ltd. ALL rights reserved. - ******************************************************************************* - */ - -/* Define to prevent recursive inclusion -------------------------------------*/ -#ifndef __MD_RCU_H__ -#define __MD_RCU_H__ - -#ifdef __cplusplus -extern "C" { -#endif - -/* Includes -------------------------------------------------------------------*/ -#include -#include "es32f0271.h" -#include "reg_rcu.h" - -/** @addtogroup Micro_Driver - * @{ - */ - -#if defined (RCU) - -/** @defgroup RCU RCU - * @brief RCU micro driver - * @{ - */ - -/* Private types --------------------------------------------------------------*/ -/* Private variables ----------------------------------------------------------*/ -/* Private constants ----------------------------------------------------------*/ -/** @defgroup MD_RCU_Private_Constants RCU Private Constants - * @{ - */ - -#define __HOSC (8000000UL) -#define __HRC (4000000UL) -#define __LOSC ( 32768UL) -#define __LRC ( 32000UL) -#define __PLL1 (48000000UL) - -/** - * @} MD_RCU_Private_Constants - */ -/* Private macros -------------------------------------------------------------*/ -/* Public types ---------------------------------------------------------------*/ -/* Public types ---------------------------------------------------------------*/ -/** @defgroup MD_RCU_Public_Types RCU Public Init Type - * @{ - */ - -typedef struct -{ - uint32_t Mpre; /*! MCO clock prescaler */ - uint32_t Msw; /*! MCO clock output */ - uint32_t PllMul; /*! PLL multiplication factor */ - uint32_t PllSrc; /*! PLL clock source */ - uint32_t HoscDiv; /*! PLL base clock 4MHz HOSC clock prescale */ - uint32_t Ppre; /*! APB clock prescaler */ - uint32_t Hpre; /*! AHB clock prescaler */ - uint32_t Sw; /*! system clock */ - uint8_t SysClock;/*! system clock enable */ -} md_rcu_init_typedef; - -/** - * @} MD_RCU_Public_Types - */ -/* Public constants -----------------------------------------------------------*/ -/** @defgroup MD_RCU_Public_Constants RCU Public Constants - * @{ - */ - -/** @defgroup MD_RCU_SWRDY_FLAG System clock switch ready flag - * @{ - */ -#define MD_RCU_SWRDY_NOT_READY (0x00000000UL) /** @brief System clock not ready */ -#define MD_RCU_SWRDY_READY (0x00000001UL) /** @brief System clock ready */ -/** - * @} MD_RCU_SWRDY_FLAG - */ - -/** @defgroup MD_RCU_CSSFLG_FLAG Clock Security System flag - * @{ - */ -#define MD_RCU_CSSFLG_NO_FAIL (0x00000000UL) /** @brief No clock security event caused by HOSC clock failure */ -#define MD_RCU_CSSFLG_FAIL (0x00000001UL) /** @brief Clock security event caused by HOSC clock failure */ -/** - * @} MD_RCU_CSSFLG_FLAG - */ - -/** @defgroup MD_RCU_PLL1_FLAG PLL1 clock ready flag - * @{ - */ -#define MD_RCU_PLL1_NOT_READY (0x00000000UL) /** @brief PLL1 not ready */ -#define MD_RCU_PLL1_READY (0x00000001UL) /** @brief PLL1 ready */ -/** - * @} MD_RCU_PLL1_FLAG - */ - -/** @defgroup MD_RCU_PLL0_FLAG PLL0 clock ready flag - * @{ - */ -#define MD_RCU_PLL0_NOT_READY (0x00000000UL) /** @brief PLL0 not ready */ -#define MD_RCU_PLL0_READY (0x00000001UL) /** @brief PLL0 ready */ -/** - * @} MD_RCU_PLL0_FLAG - */ - -/** @defgroup MD_RCU_LOSCRDY_FLAG LOSC clock ready flag - * @{ - */ -#define MD_RCU_LOSCRDY_NOT_READY (0x00000000UL) /** @brief LOSC oscillator not ready */ -#define MD_RCU_LOSCRDY_READY (0x00000001UL) /** @brief LOSC oscillator ready */ -/** - * @} MD_RCU_LOSCRDY_FLAG - */ - -/** @defgroup MD_RCU_LRCRDY_FLAG LRC clock ready flag - * @{ - */ -#define MD_RCU_LRCRDY_NOT_READY (0x00000000UL) /** @brief LRC oscillator not ready */ -#define MD_RCU_LRCRDY_READY (0x00000001UL) /** @brief LRC oscillator ready */ -/** - * @} MD_RCU_LRCRDY_FLAG - */ - -/** @defgroup MD_RCU_HOSCRDY_FLAG HOSC clock ready flag - * @{ - */ -#define MD_RCU_HOSCRDY_NOT_READY (0x00000000UL) /** @brief HOSC oscillator not ready */ -#define MD_RCU_HOSCRDY_READY (0x00000001UL) /** @brief HOSC oscillator ready */ -/** - * @} MD_RCU_HOSCRDY_FLAG - */ - -/** @defgroup MD_RCU_HRCRDY_FLAG HRC clock ready flag - * @{ - */ -#define MD_RCU_HRCRDY_NOT_READY (0x00000000UL) /** @brief HRC oscillator not ready */ -#define MD_RCU_HRCRDY_READY (0x00000001UL) /** @brief HRC oscillator ready */ -/** - * @} MD_RCU_HRCRDY_FLAG - */ - -/** @defgroup MD_RCU_MCO_OUTPUT Microcontroller clock output select - * @{ - */ -#define MD_RCU_MCO_DISABLE (0x00000000UL) /** @brief MCO output disabled, no clock on MCO */ -#define MD_RCU_MCO_LRC (0x00000001UL) /** @brief Internal low speed (LRC) oscillator clock selected */ -#define MD_RCU_MCO_LOSC (0x00000002UL) /** @brief External low speed (LOSC) oscillator clock selected */ -#define MD_RCU_MCO_HRC (0x00000003UL) /** @brief Internal high speed (HRC) oscillator clock selected */ -#define MD_RCU_MCO_HOSC (0x00000004UL) /** @brief External high speed (HOSC) oscillator clock selected */ -#define MD_RCU_MCO_PLL0 (0x00000005UL) /** @brief PLL0 clock selected */ -#define MD_RCU_MCO_PLL1 (0x00000006UL) /** @brief PLL1 clock selected */ -#define MD_RCU_MCO_SYSCLK (0x00000007UL) /** @brief System clock selected(SYSCLK) */ -#define MD_RCU_MCO_HCLK (0x00000008UL) /** @brief AHB clock selected(HCLK) */ -#define MD_RCU_MCO_PCLK (0x00000009UL) /** @brief APB clock selected(PCLK) */ -/** - * @} MD_RCU_MCO_OUTPUT - */ - -/** @defgroup MD_RCU_PLL_SRC PLL0/1 reference clock source - * @{ - */ -#define MD_RCU_PLL_SRC_HRC (0x00000000UL) /** @brief HRC selected as PLL0/1 reference clock */ -#define MD_RCU_PLL_SRC_HOSCDIV (0x00000001UL) /** @brief HOSC/HOSCDIV selected as PLL reference clock */ -/** - * @} MD_RCU_PLL_SRC - */ - -/** @defgroup MD_RCU_APB_CLK_DIV APB clock prescaler(PCLK) - * @{ - */ -#define MD_RCU_PPRE_HCLK_DIV_1 (0x00000000UL) /** @brief HCLK not divided */ -#define MD_RCU_PPRE_HCLK_DIV_2 (0x00000004UL) /** @brief HCLK divided by 2 */ -#define MD_RCU_PPRE_HCLK_DIV_4 (0x00000005UL) /** @brief HCLK divided by 4 */ -#define MD_RCU_PPRE_HCLK_DIV_8 (0x00000006UL) /** @brief HCLK divided by 8 */ -#define MD_RCU_PPRE_HCLK_DIV_16 (0x00000007UL) /** @brief HCLK divided by 16 */ -/** - * @} MD_RCU_APB_CLK_DIV - */ - -/** @defgroup MD_RCU_AHB_CLK_DIV AHB clock prescaler(HCLK) - * @{ - */ -#define MD_RCU_HPRE_SYSCLK_DIV_1 (0x00000000UL) /** @brief SYSCLK not divided */ -#define MD_RCU_HPRE_SYSCLK_DIV_2 (0x00000008UL) /** @brief SYSCLK divided by 2 */ -#define MD_RCU_HPRE_SYSCLK_DIV_4 (0x00000009UL) /** @brief SYSCLK divided by 4 */ -#define MD_RCU_HPRE_SYSCLK_DIV_8 (0x0000000AUL) /** @brief SYSCLK divided by 8 */ -#define MD_RCU_HPRE_SYSCLK_DIV_16 (0x0000000BUL) /** @brief SYSCLK divided by 16 */ -/** - * @} MD_RCU_AHB_CLK_DIV - */ - -/** @defgroup MD_RCU_SYS_CLK_SW System clock switch(SYSCLK) - * @{ - */ -#define MD_RCU_SYSCLK_HRC (0x00000000UL) /** @brief HRC selected as system clock */ -#define MD_RCU_SYSCLK_HOSC (0x00000001UL) /** @brief HOSC selected as system clock */ -#define MD_RCU_SYSCLK_LRC (0x00000002UL) /** @brief LRC selected as system clock */ -#define MD_RCU_SYSCLK_LOSC (0x00000003UL) /** @brief LOSC selected as system clock */ -#define MD_RCU_SYSCLK_PLL0 (0x00000004UL) /** @brief PLL0 selected as system clock */ -/** - * @} MD_RCU_SYS_CLK_SW - */ - -/** @defgroup MD_RCU_PSCK_I2S2CKSL SPI2/I2S2 External Clock Source Select - * @{ - */ -#define MD_RCU_PSCK_I2S2CKSL_DISABLE (0x00000000UL) /** @brief Disable External Clock (default value) */ -#define MD_RCU_PSCK_I2S2CKSL_I2SCLK1 (0x00000001UL) -#define MD_RCU_PSCK_I2S2CKSL_I2SCLK2 (0x00000002UL) -/** - * @} MD_RCU_PSCK_I2S2CKSL - */ - -/** @defgroup MD_RCU_PSCK_I2S1CKSL SPI1/I2S1 External Clock Source Select - * @{ - */ -#define MD_RCU_PSCK_I2S1CKSL_DISABLE (0x00000000UL) /** @brief Disable External Clock (default value) */ -#define MD_RCU_PSCK_I2S1CKSL_I2SCLK1 (0x00000001UL) -#define MD_RCU_PSCK_I2S1CKSL_I2SCLK2 (0x00000002UL) -/** - * @} MD_RCU_PSCK_I2S1CKSL - */ - - -/** - * @} MD_RCU_Public_Constants - */ - -/* Public macro ---------------------------------------------------------------*/ -/** @defgroup MD_RCU_Public_Macros RCU Public Macros - * @{ - */ - -/** - * @brief Get System clock switch ready flag - * @note This bit is set by hardware to indicate that the system clock change is stable. - * When the CKCFG bit was set and finish configuartion process. - * @param rcu RCU Instance - * @retval The retval can be one of the following values: - * @arg @ref MD_RCU_SWRDY_NOT_READY - * @arg @ref MD_RCU_SWRDY_READY - */ -__STATIC_INLINE uint32_t md_rcu_get_con_swrdy(RCU_TypeDef *rcu) -{ - return (READ_BIT(rcu->CON, RCU_CON_SWRDY_MSK)>>RCU_CON_SWRDY_POS); -} -/** - * @brief Get Clock Security System flag - * @note This bit is reset by software by writing the CSSON bit. - * It is set by hardware in case of HOSC clock failure. - * @param rcu RCU Instance - * @retval The retval can be one of the following values: - * @arg @ref MD_RCU_CSSFLG_NO_FAIL - * @arg @ref MD_RCU_CSSFLG_FAIL - */ -__STATIC_INLINE uint32_t md_rcu_get_con_cssflg(RCU_TypeDef *rcu) -{ - return (READ_BIT(rcu->CON, RCU_CON_CSSFLG_MSK)>>RCU_CON_CSSFLG_POS); -} -/** - * @brief Get PLL1 clock ready flag - * @note This bit is set by hardware to indicate that the PLL1 oscillator is stable. - * @param rcu RCU Instance - * @retval The retval can be one of the following values: - * @arg @ref MD_RCU_PLL1_NOT_READY - * @arg @ref MD_RCU_PLL1_READY - */ -__STATIC_INLINE uint32_t md_rcu_get_con_pll1rdy(RCU_TypeDef *rcu) -{ - return (READ_BIT(rcu->CON, RCU_CON_PLL1RDY_MSK)>>RCU_CON_PLL1RDY_POS); -} -/** - * @brief Get PLL0 clock ready flag - * @note This bit is set by hardware to indicate that the PLL0 oscillator is stable. - * @param rcu RCU Instance - * @retval The retval can be one of the following values: - * @arg @ref MD_RCU_PLL0_NOT_READY - * @arg @ref MD_RCU_PLL0_READY - */ -__STATIC_INLINE uint32_t md_rcu_get_con_pll0rdy(RCU_TypeDef *rcu) -{ - return (READ_BIT(rcu->CON, RCU_CON_PLL0RDY_MSK)>>RCU_CON_PLL0RDY_POS); -} -/** - * @brief Get LOSCRDY clock ready flag - * @note This bit is set by hardware to indicate that the LOSC oscillator is stable. - * @param rcu RCU Instance - * @retval The retval can be one of the following values: - * @arg @ref MD_RCU_LOSCRDY_NOT_READY - * @arg @ref MD_RCU_LOSCRDY_READY - */ -__STATIC_INLINE uint32_t md_rcu_get_con_loscrdy(RCU_TypeDef *rcu) -{ - return (READ_BIT(rcu->CON, RCU_CON_LOSCRDY_MSK)>>RCU_CON_LOSCRDY_POS); -} -/** - * @brief Get LRCRDY clock ready flag - * @note This bit is set by hardware to indicate that the LRC oscillator is stable. - * @param rcu RCU Instance - * @retval The retval can be one of the following values: - * @arg @ref MD_RCU_LRCRDY_NOT_READY - * @arg @ref MD_RCU_LRCRDY_READY - */ -__STATIC_INLINE uint32_t md_rcu_get_con_lrcrdy(RCU_TypeDef *rcu) -{ - return (READ_BIT(rcu->CON, RCU_CON_LRCRDY_MSK)>>RCU_CON_LRCRDY_POS); -} -/** - * @brief Get HOSCRDY clock ready flag - * @note This bit is set by hardware to indicate that the HOSC oscillator is stable. - * @param rcu RCU Instance - * @retval The retval can be one of the following values: - * @arg @ref MD_RCU_HOSCRDY_NOT_READY - * @arg @ref MD_RCU_HOSCRDY_READY - */ -__STATIC_INLINE uint32_t md_rcu_get_con_hoscrdy(RCU_TypeDef *rcu) -{ - return (READ_BIT(rcu->CON, RCU_CON_HOSCRDY_MSK)>>RCU_CON_HOSCRDY_POS); -} -/** - * @brief Get HRCRDY clock ready flag - * @note This bit is set by hardware to indicate that the HRC oscillator is stable. - * @param rcu RCU Instance - * @retval The retval can be one of the following values: - * @arg @ref MD_RCU_HRCRDY_NOT_READY - * @arg @ref MD_RCU_HRCRDY_READY - */ -__STATIC_INLINE uint32_t md_rcu_get_con_hrcrdy(RCU_TypeDef *rcu) -{ - return (READ_BIT(rcu->CON, RCU_CON_HRCRDY_MSK)>>RCU_CON_HRCRDY_POS); -} -/** - * @brief Clock security system enable(CSS) - * @note Set and cleared by software to enable the clock security system. - * When CSSON is set, the clock detector is enabled by hardware when the HOSC oscillator is ready, - * and disabled by hardware if a HOSC clock failure is detected. - * @param rcu RCU Instance - * @retval None - */ -__STATIC_INLINE void md_rcu_enable_con_csson(RCU_TypeDef *rcu) -{ - SET_BIT(rcu->CON, RCU_CON_CSSON_MSK); -} -/** - * @brief Clock security system disable(CSS) - * @note Set and cleared by software to enable the clock security system. - * When CSSON is set, the clock detector is enabled by hardware when the HOSC oscillator is ready, - * and disabled by hardware if a HOSC clock failure is detected. - * @param rcu RCU Instance - * @retval None - */ -__STATIC_INLINE void md_rcu_disable_con_csson(RCU_TypeDef *rcu) -{ - CLEAR_BIT(rcu->CON, RCU_CON_CSSON_MSK); -} -/** - * @brief Get Clock security system (CSS) - * @note Set and cleared by software to enable the clock security system. - * When CSSON is set, the clock detector is enabled by hardware when the HOSC oscillator is ready, - * and disabled by hardware if a HOSC clock failure is detected. - * @param rcu RCU Instance - * @retval State of bit (1 or 0). - */ -__STATIC_INLINE uint32_t md_rcu_get_con_csson(RCU_TypeDef *rcu) -{ - return (READ_BIT(rcu->CON, RCU_CON_CSSON_MSK)>>RCU_CON_CSSON_POS); -} -/** - * @brief PLL1 enable bit(for USB PHY) - * @param rcu RCU Instance - * @retval None - */ -__STATIC_INLINE void md_rcu_enable_con_pll1on(RCU_TypeDef *rcu) -{ - SET_BIT(rcu->CON, RCU_CON_PLL1ON_MSK); -} -/** - * @brief PLL1 disable bit(for USB PHY) - * @param rcu RCU Instance - * @retval None - */ -__STATIC_INLINE void md_rcu_disable_con_pll1on(RCU_TypeDef *rcu) -{ - CLEAR_BIT(rcu->CON, RCU_CON_PLL1ON_MSK); -} -/** - * @brief Get PLL1 bit(for USB PHY) - * @param rcu RCU Instance - * @retval State of bit (1 or 0). - */ -__STATIC_INLINE uint32_t md_rcu_get_con_pll1on(RCU_TypeDef *rcu) -{ - return (READ_BIT(rcu->CON, RCU_CON_PLL1ON_MSK)>>RCU_CON_PLL1ON_POS); -} -/** - * @brief PLL0 enable bit - * @param rcu RCU Instance - * @retval None - */ -__STATIC_INLINE void md_rcu_enable_con_pll0on(RCU_TypeDef *rcu) -{ - SET_BIT(rcu->CON, RCU_CON_PLL0ON_MSK); -} -/** - * @brief PLL0 disable bit - * @param rcu RCU Instance - * @retval None - */ -__STATIC_INLINE void md_rcu_disable_con_pll0on(RCU_TypeDef *rcu) -{ - CLEAR_BIT(rcu->CON, RCU_CON_PLL0ON_MSK); -} -/** - * @brief Get PLL0 bit - * @param rcu RCU Instance - * @retval State of bit (1 or 0). - */ -__STATIC_INLINE uint32_t md_rcu_get_con_pll0on(RCU_TypeDef *rcu) -{ - return (READ_BIT(rcu->CON, RCU_CON_PLL0ON_MSK)>>RCU_CON_PLL0ON_POS); -} -/** - * @brief External low speed oscillator clock enbale bit - * @param rcu RCU Instance - * @retval None - */ -__STATIC_INLINE void md_rcu_enable_con_loscon(RCU_TypeDef *rcu) -{ - SET_BIT(rcu->CON, RCU_CON_LOSCON_MSK); -} -/** - * @brief External low speed oscillator clock disable bit - * @param rcu RCU Instance - * @retval None - */ -__STATIC_INLINE void md_rcu_disable_con_loscon(RCU_TypeDef *rcu) -{ - CLEAR_BIT(rcu->CON, RCU_CON_LOSCON_MSK); -} -/** - * @brief Get External low speed oscillator clock bit - * @param rcu RCU Instance - * @retval State of bit (1 or 0). - */ -__STATIC_INLINE uint32_t md_rcu_get_con_loscon(RCU_TypeDef *rcu) -{ - return (READ_BIT(rcu->CON, RCU_CON_LOSCON_MSK)>>RCU_CON_LOSCON_POS); -} -/** - * @brief Internal low speed oscillator clock enbale bit - * @param rcu RCU Instance - * @retval None - */ -__STATIC_INLINE void md_rcu_enable_con_lrcon(RCU_TypeDef *rcu) -{ - SET_BIT(rcu->CON, RCU_CON_LRCON_MSK); -} -/** - * @brief Internal low speed oscillator clock disable bit - * @param rcu RCU Instance - * @retval None - */ -__STATIC_INLINE void md_rcu_disable_con_lrcon(RCU_TypeDef *rcu) -{ - CLEAR_BIT(rcu->CON, RCU_CON_LRCON_MSK); -} -/** - * @brief Get Internal low speed oscillator clock bit - * @param rcu RCU Instance - * @retval State of bit (1 or 0). - */ -__STATIC_INLINE uint32_t md_rcu_get_con_lrcon(RCU_TypeDef *rcu) -{ - return (READ_BIT(rcu->CON, RCU_CON_LRCON_MSK)>>RCU_CON_LRCON_POS); -} -/** - * @brief External high speed oscillator clock enbale bit - * @param rcu RCU Instance - * @retval None - */ -__STATIC_INLINE void md_rcu_enable_con_hoscon(RCU_TypeDef *rcu) -{ - SET_BIT(rcu->CON, RCU_CON_HOSCON_MSK); -} -/** - * @brief External high speed oscillator clock disable bit - * @param rcu RCU Instance - * @retval None - */ -__STATIC_INLINE void md_rcu_disable_con_hoscon(RCU_TypeDef *rcu) -{ - CLEAR_BIT(rcu->CON, RCU_CON_HOSCON_MSK); -} -/** - * @brief Get External high speed oscillator clock bit - * @param rcu RCU Instance - * @retval State of bit (1 or 0). - */ -__STATIC_INLINE uint32_t md_rcu_get_con_hoscon(RCU_TypeDef *rcu) -{ - return (READ_BIT(rcu->CON, RCU_CON_HOSCON_MSK)>>RCU_CON_HOSCON_POS); -} -/** - * @brief Internal high speed oscillator clock enbale bit - * @param rcu RCU Instance - * @retval None - */ -__STATIC_INLINE void md_rcu_enable_con_hrcon(RCU_TypeDef *rcu) -{ - SET_BIT(rcu->CON, RCU_CON_HRCON_MSK); -} -/** - * @brief Internal high speed oscillator clock disable bit - * @param rcu RCU Instance - * @retval None - */ -__STATIC_INLINE void md_rcu_disable_con_hrcon(RCU_TypeDef *rcu) -{ - CLEAR_BIT(rcu->CON, RCU_CON_HRCON_MSK); -} -/** - * @brief Get Internal high speed oscillator clock bit - * @param rcu RCU Instance - * @retval State of bit (1 or 0). - */ -__STATIC_INLINE uint32_t md_rcu_get_con_hrcon(RCU_TypeDef *rcu) -{ - return (READ_BIT(rcu->CON, RCU_CON_HRCON_MSK)>>RCU_CON_HRCON_POS); -} - -/** @defgroup MD_RCU_CON_CSSON CSSON - * @brief Set Clock security system bit for md_rcu_set_con() function used - * @param csson This parameter can be one of the following values: - * @arg @ref DISABLE - * @arg @ref ENABLE - * @{ - */ -#define md_rcu_set_con_csson_fun(csson) (csson<CON, (csson|pll1on|pll0on|loscon|lrcon|hoscon|hrcon)); -} - -/** - * @brief Clock configuration set bit - * @note This bit is write-only. A read to this bit returns the value 0. - * If set is bit to high, start to configurate clock setting. - * When the clock configuration process was finished, this bit was clear to zero by self. - * @param rcu RCU Instance - * @retval None - */ -__STATIC_INLINE void md_rcu_set_cfg_ckcfg(RCU_TypeDef *rcu) -{ - SET_BIT(rcu->CFG, RCU_CFG_CKCFG_MSK); -} -/** - * @brief Set Microcontroller clock output prescaler - * @note Output Frequency = MCO/(MPRE+1) - * @param rcu RCU Instance - * @param mpre This parameter can be one of the following values: - * @arg Max Value 7 - * @arg Min Value 0 - * @retval None - */ -__STATIC_INLINE void md_rcu_set_cfg_mpre(RCU_TypeDef *rcu, uint32_t mpre) -{ - MODIFY_REG(rcu->CFG, RCU_CFG_MPRE_MSK, (mpre<CFG, RCU_CFG_MPRE_MSK)>>RCU_CFG_MPRE_POSS); -} -/** - * @brief Set Microcontroller clock output (MCO) - * @param rcu RCU Instance - * @param msw This parameter can be one of the following values: - * @arg @ref MD_RCU_MCO_DISABLE - * @arg @ref MD_RCU_MCO_LRC - * @arg @ref MD_RCU_MCO_LOSC - * @arg @ref MD_RCU_MCO_HRC - * @arg @ref MD_RCU_MCO_HOSC - * @arg @ref MD_RCU_MCO_PLL0 - * @arg @ref MD_RCU_MCO_PLL1 - * @arg @ref MD_RCU_MCO_SYSCLK - * @arg @ref MD_RCU_MCO_HCLK - * @arg @ref MD_RCU_MCO_PCLK - * @retval None - */ -__STATIC_INLINE void md_rcu_set_cfg_msw(RCU_TypeDef *rcu, uint32_t msw) -{ - MODIFY_REG(rcu->CFG, RCU_CFG_MSW_MSK, (msw<CFG, RCU_CFG_MSW_MSK)>>RCU_CFG_MSW_POSS); -} -/** - * @brief Set PLL0 multiplication factor - * @note PLL0 output clock frequency is 4*(PLL0MUL+1)MHz - * @param rcu RCU Instance - * @param pllmul can be one of the following values: - * @arg Max Value 31 - * @arg Min Value 0 - * @retval None - */ -__STATIC_INLINE void md_rcu_set_cfg_pllmul(RCU_TypeDef *rcu, uint32_t pllmul) -{ - MODIFY_REG(rcu->CFG, RCU_CFG_PLLMUL_MSK, (pllmul<CFG, RCU_CFG_PLLMUL_MSK)>>RCU_CFG_PLLMUL_POSS); -} -/** - * @brief Set PLL0/1 reference clock source - * @param rcu RCU Instance - * @param pllsrc This parameter can be one of the following values: - * @arg @ref MD_RCU_PLL_SRC_HRC - * @arg @ref MD_RCU_PLL_SRC_HOSCDIV - * @retval None - */ -__STATIC_INLINE void md_rcu_set_cfg_pllsrc(RCU_TypeDef *rcu, uint32_t pllsrc) -{ - MODIFY_REG(rcu->CFG, RCU_CFG_PLLSRC_MSK, (pllsrc<CFG, RCU_CFG_PLLSRC_MSK)>>RCU_CFG_PLLSRC_POS); -} -/** - * @brief Set HOSC clock division factor for PLL0/1 reference clock 4 MHz - * @note These bits are set and cleared by software to select HOSCDIV division factor. - * @note PLL_reference_clock (4 MHz) = HOSC / (HOSCDIV+1) - * @param rcu RCU Instance - * @param hoscdiv can be one of the following values: - * @arg Max Value 7 - * @arg Min Value 0 - * @retval None - */ -__STATIC_INLINE void md_rcu_set_cfg_hoscdiv(RCU_TypeDef *rcu, uint32_t hoscdiv) -{ - MODIFY_REG(rcu->CFG, RCU_CFG_HOSCDIV_MSK, (hoscdiv<CFG, RCU_CFG_HOSCDIV_MSK)>>RCU_CFG_HOSCDIV_POSS); -} -/** - * @brief Set APB clock prescaler(PCLK) - * @param rcu RCU Instance - * @param ppre The retval can be one of the following values: - * @arg @ref MD_RCU_PPRE_HCLK_DIV_1 - * @arg @ref MD_RCU_PPRE_HCLK_DIV_2 - * @arg @ref MD_RCU_PPRE_HCLK_DIV_4 - * @arg @ref MD_RCU_PPRE_HCLK_DIV_8 - * @arg @ref MD_RCU_PPRE_HCLK_DIV_16 - * @retval None - */ -__STATIC_INLINE void md_rcu_set_cfg_ppre(RCU_TypeDef *rcu, uint32_t ppre) -{ - MODIFY_REG(rcu->CFG, RCU_CFG_PPRE_MSK, (ppre<CFG, RCU_CFG_PPRE_MSK)>>RCU_CFG_PPRE_POSS); -} -/** - * @brief Set AHB clock prescaler(HCLK) - * @param rcu RCU Instance - * @param hpre can be one of the following values: - * @arg @ref MD_RCU_HPRE_SYSCLK_DIV_1 - * @arg @ref MD_RCU_HPRE_SYSCLK_DIV_2 - * @arg @ref MD_RCU_HPRE_SYSCLK_DIV_4 - * @arg @ref MD_RCU_HPRE_SYSCLK_DIV_8 - * @arg @ref MD_RCU_HPRE_SYSCLK_DIV_16 - * @retval None - */ -__STATIC_INLINE void md_rcu_set_cfg_hpre(RCU_TypeDef *rcu, uint32_t hpre) -{ - MODIFY_REG(rcu->CFG, RCU_CFG_HPRE_MSK, (hpre<CFG, RCU_CFG_HPRE_MSK)>>RCU_CFG_HPRE_POSS); -} -/** - * @brief Set System clock switch(SYSCLK) - * @param rcu RCU Instance - * @param sw can be one of the following values: - * @arg @ref MD_RCU_SYSCLK_HRC - * @arg @ref MD_RCU_SYSCLK_HOSC - * @arg @ref MD_RCU_SYSCLK_LRC - * @arg @ref MD_RCU_SYSCLK_LOSC - * @arg @ref MD_RCU_SYSCLK_PLL0 - * @retval None - */ -__STATIC_INLINE void md_rcu_set_cfg_sw(RCU_TypeDef *rcu, uint32_t sw) -{ - MODIFY_REG(rcu->CFG, RCU_CFG_SW_MSK, (sw<CFG, RCU_CFG_SW_MSK)>>RCU_CFG_SW_POSS); -} -/** @defgroup MD_RCU_CFG_MPRE MPRE - * @brief Set Microcontroller clock output prescaler bit for md_rcu_set_cfg() function used - * @param mpre This parameter can be one of the following values: - * @arg Max Value 7 - * @arg Min Value 0 - * @{ - */ -#define md_rcu_set_cfg_mpre_fun(mpre) (mpre<CFG, (mpre|msw|pllmul|pllsrc|hoscdiv|ppre|hpre|sw)); -} - -/** - * @brief Set SPI2/I2S2 External Clock Source Select - * @param rcu RCU Instance - * @param i2s2ckdl This parameter can be one of the following values: - * @arg @ref MD_RCU_PSCK_I2S2CKSL_DISABLE - * @arg @ref MD_RCU_PSCK_I2S2CKSL_I2SCLK1 - * @arg @ref MD_RCU_PSCK_I2S2CKSL_I2SCLK2 - * @retval None - */ -__STATIC_INLINE void md_rcu_set_psck_i2s2ckdl(RCU_TypeDef *rcu, uint32_t i2s2ckdl) -{ - MODIFY_REG(rcu->PSCK, RCU_PSCK_I2S2CKSL_MSK, (i2s2ckdl<PSCK, RCU_PSCK_I2S2CKSL_MSK)>>RCU_PSCK_I2S2CKSL_POSS); -} -/** - * @brief Set SPI1/I2S1 External Clock Source Select - * @param rcu RCU Instance - * @param i2s1ckdl This parameter can be one of the following values: - * @arg @ref MD_RCU_PSCK_I2S1CKSL_DISABLE - * @arg @ref MD_RCU_PSCK_I2S1CKSL_I2SCLK1 - * @arg @ref MD_RCU_PSCK_I2S1CKSL_I2SCLK2 - * @retval None - */ -__STATIC_INLINE void md_rcu_set_psck_i2s1ckdl(RCU_TypeDef *rcu, uint32_t i2s1ckdl) -{ - MODIFY_REG(rcu->PSCK, RCU_PSCK_I2S1CKSL_MSK, (i2s1ckdl<PSCK, RCU_PSCK_I2S1CKSL_MSK)>>RCU_PSCK_I2S1CKSL_POSS); -} - -/** @defgroup MD_RCU_PSCK_I2S2CKSL_ I2S2CKSL - * @brief Set SPI2/I2S2 External Clock Source Select bit for md_rcu_set_psck() function used - * @param i2s2ckdl This parameter can be one of the following values: - * @arg @ref MD_RCU_PSCK_I2S2CKSL_DISABLE - * @arg @ref MD_RCU_PSCK_I2S2CKSL_I2SCLK1 - * @arg @ref MD_RCU_PSCK_I2S2CKSL_I2SCLK2 - * @{ - */ -#define md_rcu_set_psck_i2s2ckdl_fun(i2s2ckdl) (i2s2ckdl<PSCK, (i2s2ckdl|i2s1ckdl)); -} - -/** - * @brief GPIOD reset request enable bit - * @param rcu RCU Instance - * @retval None - */ -__STATIC_INLINE void md_rcu_enable_ahbrst_gpden(RCU_TypeDef *rcu) -{ - SET_BIT(rcu->AHBRST, RCU_AHBRST_GPDEN_MSK); -} -/** - * @brief GPIOD reset request disable bit - * @param rcu RCU Instance - * @retval None - */ -__STATIC_INLINE void md_rcu_disable_ahbrst_gpden(RCU_TypeDef *rcu) -{ - CLEAR_BIT(rcu->AHBRST, RCU_AHBRST_GPDEN_MSK); -} -/** - * @brief Get GPIOD reset request bit - * @param rcu RCU Instance - * @retval State of bit (1 or 0). - */ -__STATIC_INLINE uint32_t md_rcu_get_ahbrst_gpden(RCU_TypeDef *rcu) -{ - return (READ_BIT(rcu->AHBRST, RCU_AHBRST_GPDEN_MSK)>>RCU_AHBRST_GPDEN_POS); -} -/** - * @brief GPIOC reset request enable bit - * @param rcu RCU Instance - * @retval None - */ -__STATIC_INLINE void md_rcu_enable_ahbrst_gpcen(RCU_TypeDef *rcu) -{ - SET_BIT(rcu->AHBRST, RCU_AHBRST_GPCEN_MSK); -} -/** - * @brief GPIOC reset request disable bit - * @param rcu RCU Instance - * @retval None - */ -__STATIC_INLINE void md_rcu_disable_ahbrst_gpcen(RCU_TypeDef *rcu) -{ - CLEAR_BIT(rcu->AHBRST, RCU_AHBRST_GPCEN_MSK); -} -/** - * @brief Get GPIOC reset request bit - * @param rcu RCU Instance - * @retval State of bit (1 or 0). - */ -__STATIC_INLINE uint32_t md_rcu_get_ahbrst_gpcen(RCU_TypeDef *rcu) -{ - return (READ_BIT(rcu->AHBRST, RCU_AHBRST_GPCEN_MSK)>>RCU_AHBRST_GPCEN_POS); -} -/** - * @brief GPIOB reset request enable bit - * @param rcu RCU Instance - * @retval None - */ -__STATIC_INLINE void md_rcu_enable_ahbrst_gpben(RCU_TypeDef *rcu) -{ - SET_BIT(rcu->AHBRST, RCU_AHBRST_GPBEN_MSK); -} -/** - * @brief GPIOB reset request disable bit - * @param rcu RCU Instance - * @retval None - */ -__STATIC_INLINE void md_rcu_disable_ahbrst_gpben(RCU_TypeDef *rcu) -{ - CLEAR_BIT(rcu->AHBRST, RCU_AHBRST_GPBEN_MSK); -} -/** - * @brief Get GPIOB reset request bit - * @param rcu RCU Instance - * @retval State of bit (1 or 0). - */ -__STATIC_INLINE uint32_t md_rcu_get_ahbrst_gpben(RCU_TypeDef *rcu) -{ - return (READ_BIT(rcu->AHBRST, RCU_AHBRST_GPBEN_MSK)>>RCU_AHBRST_GPBEN_POS); -} -/** - * @brief GPIOA reset request enable bit - * @param rcu RCU Instance - * @retval None - */ -__STATIC_INLINE void md_rcu_enable_ahbrst_gpaen(RCU_TypeDef *rcu) -{ - SET_BIT(rcu->AHBRST, RCU_AHBRST_GPAEN_MSK); -} -/** - * @brief GPIOA reset request disable bit - * @param rcu RCU Instance - * @retval None - */ -__STATIC_INLINE void md_rcu_disable_ahbrst_gpaen(RCU_TypeDef *rcu) -{ - CLEAR_BIT(rcu->AHBRST, RCU_AHBRST_GPAEN_MSK); -} -/** - * @brief Get GPIOA reset request bit - * @param rcu RCU Instance - * @retval State of bit (1 or 0). - */ -__STATIC_INLINE uint32_t md_rcu_get_ahbrst_gpaen(RCU_TypeDef *rcu) -{ - return (READ_BIT(rcu->AHBRST, RCU_AHBRST_GPAEN_MSK)>>RCU_AHBRST_GPAEN_POS); -} -/** - * @brief HDIV reset request enable bit - * @param rcu RCU Instance - * @retval None - */ -__STATIC_INLINE void md_rcu_enable_ahbrst_hdiven(RCU_TypeDef *rcu) -{ - SET_BIT(rcu->AHBRST, RCU_AHBRST_HDIVEN_MSK); -} -/** - * @brief HDIV reset request disable bit - * @param rcu RCU Instance - * @retval None - */ -__STATIC_INLINE void md_rcu_disable_ahbrst_hdiven(RCU_TypeDef *rcu) -{ - CLEAR_BIT(rcu->AHBRST, RCU_AHBRST_HDIVEN_MSK); -} -/** - * @brief Get HDIV reset request bit - * @param rcu RCU Instance - * @retval State of bit (1 or 0). - */ -__STATIC_INLINE uint32_t md_rcu_get_ahbrst_hdiven(RCU_TypeDef *rcu) -{ - return (READ_BIT(rcu->AHBRST, RCU_AHBRST_HDIVEN_MSK)>>RCU_AHBRST_HDIVEN_POS); -} -/** - * @brief USB reset request enable bit - * @param rcu RCU Instance - * @retval None - */ -__STATIC_INLINE void md_rcu_enable_ahbrst_usben(RCU_TypeDef *rcu) -{ - SET_BIT(rcu->AHBRST, RCU_AHBRST_USBEN_MSK); -} -/** - * @brief USB reset request disable bit - * @param rcu RCU Instance - * @retval None - */ -__STATIC_INLINE void md_rcu_disable_ahbrst_usben(RCU_TypeDef *rcu) -{ - CLEAR_BIT(rcu->AHBRST, RCU_AHBRST_USBEN_MSK); -} -/** - * @brief Get USB reset request bit - * @param rcu RCU Instance - * @retval State of bit (1 or 0). - */ -__STATIC_INLINE uint32_t md_rcu_get_ahbrst_usben(RCU_TypeDef *rcu) -{ - return (READ_BIT(rcu->AHBRST, RCU_AHBRST_USBEN_MSK)>>RCU_AHBRST_USBEN_POS); -} -/** - * @brief AES reset request enable bit - * @param rcu RCU Instance - * @retval None - */ -__STATIC_INLINE void md_rcu_enable_ahbrst_aesen(RCU_TypeDef *rcu) -{ - SET_BIT(rcu->AHBRST, RCU_AHBRST_AESEN_MSK); -} -/** - * @brief AES reset request disable bit - * @param rcu RCU Instance - * @retval None - */ -__STATIC_INLINE void md_rcu_disable_ahbrst_aesen(RCU_TypeDef *rcu) -{ - CLEAR_BIT(rcu->AHBRST, RCU_AHBRST_AESEN_MSK); -} -/** - * @brief Get AES reset request bit - * @param rcu RCU Instance - * @retval State of bit (1 or 0). - */ -__STATIC_INLINE uint32_t md_rcu_get_ahbrst_aesen(RCU_TypeDef *rcu) -{ - return (READ_BIT(rcu->AHBRST, RCU_AHBRST_AESEN_MSK)>>RCU_AHBRST_AESEN_POS); -} -/** - * @brief CRC reset request enable bit - * @param rcu RCU Instance - * @retval None - */ -__STATIC_INLINE void md_rcu_enable_ahbrst_crcen(RCU_TypeDef *rcu) -{ - SET_BIT(rcu->AHBRST, RCU_AHBRST_CRCEN_MSK); -} -/** - * @brief CRC reset request disable bit - * @param rcu RCU Instance - * @retval None - */ -__STATIC_INLINE void md_rcu_disable_ahbrst_crcen(RCU_TypeDef *rcu) -{ - CLEAR_BIT(rcu->AHBRST, RCU_AHBRST_CRCEN_MSK); -} -/** - * @brief Get CRC reset request bit - * @param rcu RCU Instance - * @retval State of bit (1 or 0). - */ -__STATIC_INLINE uint32_t md_rcu_get_ahbrst_crcen(RCU_TypeDef *rcu) -{ - return (READ_BIT(rcu->AHBRST, RCU_AHBRST_CRCEN_MSK)>>RCU_AHBRST_CRCEN_POS); -} -/** - * @brief RTC reset request enable bit - * @param rcu RCU Instance - * @retval None - */ -__STATIC_INLINE void md_rcu_enable_ahbrst_rtcen(RCU_TypeDef *rcu) -{ - SET_BIT(rcu->AHBRST, RCU_AHBRST_RTCEN_MSK); -} -/** - * @brief RTC reset request disable bit - * @param rcu RCU Instance - * @retval None - */ -__STATIC_INLINE void md_rcu_disable_ahbrst_rtcen(RCU_TypeDef *rcu) -{ - CLEAR_BIT(rcu->AHBRST, RCU_AHBRST_RTCEN_MSK); -} -/** - * @brief Get RTC reset request bit - * @param rcu RCU Instance - * @retval State of bit (1 or 0). - */ -__STATIC_INLINE uint32_t md_rcu_get_ahbrst_rtcen(RCU_TypeDef *rcu) -{ - return (READ_BIT(rcu->AHBRST, RCU_AHBRST_RTCEN_MSK)>>RCU_AHBRST_RTCEN_POS); -} -/** - * @brief DMA1 reset request enable bit - * @param rcu RCU Instance - * @retval None - */ -__STATIC_INLINE void md_rcu_enable_ahbrst_dma1en(RCU_TypeDef *rcu) -{ - SET_BIT(rcu->AHBRST, RCU_AHBRST_DMA1EN_MSK); -} -/** - * @brief DMA1 reset request disable bit - * @param rcu RCU Instance - * @retval None - */ -__STATIC_INLINE void md_rcu_disable_ahbrst_dma1en(RCU_TypeDef *rcu) -{ - CLEAR_BIT(rcu->AHBRST, RCU_AHBRST_DMA1EN_MSK); -} -/** - * @brief Get DMA1 reset request bit - * @param rcu RCU Instance - * @retval State of bit (1 or 0). - */ -__STATIC_INLINE uint32_t md_rcu_get_ahbrst_dma1en(RCU_TypeDef *rcu) -{ - return (READ_BIT(rcu->AHBRST, RCU_AHBRST_DMA1EN_MSK)>>RCU_AHBRST_DMA1EN_POS); -} - -/** @defgroup MD_RCU_AHBRST_GPDEN GPDEN - * @brief Set GPIOD reset request bit for md_rcu_set_ahbrst() function used - * @param gpden This parameter can be one of the following values: - * @arg @ref DISABLE - * @arg @ref ENABLE - * @{ - */ -#define md_rcu_set_ahbrst_gpden_fun(gpden) (gpden<AHBRST, (gpden|gpcen|gpben|gpaen|hdiven|usben|aesen|crcen|rtcen|dma1en)); -} - -/** - * @brief DAC reset request enable bit - * @param rcu RCU Instance - * @retval None - */ -__STATIC_INLINE void md_rcu_enable_apb1rst_dacen(RCU_TypeDef *rcu) -{ - SET_BIT(rcu->APB1RST, RCU_APB1RST_DACEN_MSK); -} -/** - * @brief DAC reset request disable bit - * @param rcu RCU Instance - * @retval None - */ -__STATIC_INLINE void md_rcu_disable_apb1rst_dacen(RCU_TypeDef *rcu) -{ - CLEAR_BIT(rcu->APB1RST, RCU_APB1RST_DACEN_MSK); -} -/** - * @brief Get DAC reset request bit - * @param rcu RCU Instance - * @retval State of bit (1 or 0). - */ -__STATIC_INLINE uint32_t md_rcu_get_apb1rst_dacen(RCU_TypeDef *rcu) -{ - return (READ_BIT(rcu->APB1RST, RCU_APB1RST_DACEN_MSK)>>RCU_APB1RST_DACEN_POS); -} -/** - * @brief I2C2 reset request enable bit - * @param rcu RCU Instance - * @retval None - */ -__STATIC_INLINE void md_rcu_enable_apb1rst_i2c2en(RCU_TypeDef *rcu) -{ - SET_BIT(rcu->APB1RST, RCU_APB1RST_I2C2EN_MSK); -} -/** - * @brief I2C2 reset request disable bit - * @param rcu RCU Instance - * @retval None - */ -__STATIC_INLINE void md_rcu_disable_apb1rst_i2c2en(RCU_TypeDef *rcu) -{ - CLEAR_BIT(rcu->APB1RST, RCU_APB1RST_I2C2EN_MSK); -} -/** - * @brief Get I2C2 reset request bit - * @param rcu RCU Instance - * @retval State of bit (1 or 0). - */ -__STATIC_INLINE uint32_t md_rcu_get_apb1rst_i2c2en(RCU_TypeDef *rcu) -{ - return (READ_BIT(rcu->APB1RST, RCU_APB1RST_I2C2EN_MSK)>>RCU_APB1RST_I2C2EN_POS); -} -/** - * @brief I2C1 reset request enable bit - * @param rcu RCU Instance - * @retval None - */ -__STATIC_INLINE void md_rcu_enable_apb1rst_i2c1en(RCU_TypeDef *rcu) -{ - SET_BIT(rcu->APB1RST, RCU_APB1RST_I2C1EN_MSK); -} -/** - * @brief I2C1 reset request disable bit - * @param rcu RCU Instance - * @retval None - */ -__STATIC_INLINE void md_rcu_disable_apb1rst_i2c1en(RCU_TypeDef *rcu) -{ - CLEAR_BIT(rcu->APB1RST, RCU_APB1RST_I2C1EN_MSK); -} -/** - * @brief Get I2C1 reset request bit - * @param rcu RCU Instance - * @retval State of bit (1 or 0). - */ -__STATIC_INLINE uint32_t md_rcu_get_apb1rst_i2c1en(RCU_TypeDef *rcu) -{ - return (READ_BIT(rcu->APB1RST, RCU_APB1RST_I2C1EN_MSK)>>RCU_APB1RST_I2C1EN_POS); -} -/** - * @brief SUART2 reset request enable bit - * @param rcu RCU Instance - * @retval None - */ -__STATIC_INLINE void md_rcu_enable_apb1rst_suart2en(RCU_TypeDef *rcu) -{ - SET_BIT(rcu->APB1RST, RCU_APB1RST_SUART2EN_MSK); -} -/** - * @brief SUART2 reset request disable bit - * @param rcu RCU Instance - * @retval None - */ -__STATIC_INLINE void md_rcu_disable_apb1rst_suart2en(RCU_TypeDef *rcu) -{ - CLEAR_BIT(rcu->APB1RST, RCU_APB1RST_SUART2EN_MSK); -} -/** - * @brief Get SUART2 reset request bit - * @param rcu RCU Instance - * @retval State of bit (1 or 0). - */ -__STATIC_INLINE uint32_t md_rcu_get_apb1rst_suart2en(RCU_TypeDef *rcu) -{ - return (READ_BIT(rcu->APB1RST, RCU_APB1RST_SUART2EN_MSK)>>RCU_APB1RST_SUART2EN_POS); -} -/** - * @brief SUART1 reset request enable bit - * @param rcu RCU Instance - * @retval None - */ -__STATIC_INLINE void md_rcu_enable_apb1rst_suart1en(RCU_TypeDef *rcu) -{ - SET_BIT(rcu->APB1RST, RCU_APB1RST_SUART1EN_MSK); -} -/** - * @brief SUART1 reset request disable bit - * @param rcu RCU Instance - * @retval None - */ -__STATIC_INLINE void md_rcu_disable_apb1rst_suart1en(RCU_TypeDef *rcu) -{ - CLEAR_BIT(rcu->APB1RST, RCU_APB1RST_SUART1EN_MSK); -} -/** - * @brief Get SUART1 reset request bit - * @param rcu RCU Instance - * @retval State of bit (1 or 0). - */ -__STATIC_INLINE uint32_t md_rcu_get_apb1rst_suart1en(RCU_TypeDef *rcu) -{ - return (READ_BIT(rcu->APB1RST, RCU_APB1RST_SUART1EN_MSK)>>RCU_APB1RST_SUART1EN_POS); -} -/** - * @brief UART3 reset request enable bit - * @param rcu RCU Instance - * @retval None - */ -__STATIC_INLINE void md_rcu_enable_apb1rst_uart3en(RCU_TypeDef *rcu) -{ - SET_BIT(rcu->APB1RST, RCU_APB1RST_UART3EN_MSK); -} -/** - * @brief UART3 reset request disable bit - * @param rcu RCU Instance - * @retval None - */ -__STATIC_INLINE void md_rcu_disable_apb1rst_uart3en(RCU_TypeDef *rcu) -{ - CLEAR_BIT(rcu->APB1RST, RCU_APB1RST_UART3EN_MSK); -} -/** - * @brief Get UART3 reset request bit - * @param rcu RCU Instance - * @retval State of bit (1 or 0). - */ -__STATIC_INLINE uint32_t md_rcu_get_apb1rst_uart3en(RCU_TypeDef *rcu) -{ - return (READ_BIT(rcu->APB1RST, RCU_APB1RST_UART3EN_MSK)>>RCU_APB1RST_UART3EN_POS); -} -/** - * @brief UART2 reset request enable bit - * @param rcu RCU Instance - * @retval None - */ -__STATIC_INLINE void md_rcu_enable_apb1rst_uart2en(RCU_TypeDef *rcu) -{ - SET_BIT(rcu->APB1RST, RCU_APB1RST_UART2EN_MSK); -} -/** - * @brief UART2 reset request disable bit - * @param rcu RCU Instance - * @retval None - */ -__STATIC_INLINE void md_rcu_disable_apb1rst_uart2en(RCU_TypeDef *rcu) -{ - CLEAR_BIT(rcu->APB1RST, RCU_APB1RST_UART2EN_MSK); -} -/** - * @brief Get UART2 reset request bit - * @param rcu RCU Instance - * @retval State of bit (1 or 0). - */ -__STATIC_INLINE uint32_t md_rcu_get_apb1rst_uart2en(RCU_TypeDef *rcu) -{ - return (READ_BIT(rcu->APB1RST, RCU_APB1RST_UART2EN_MSK)>>RCU_APB1RST_UART2EN_POS); -} -/** - * @brief SPI2 reset request enable bit - * @param rcu RCU Instance - * @retval None - */ -__STATIC_INLINE void md_rcu_enable_apb1rst_spi2en(RCU_TypeDef *rcu) -{ - SET_BIT(rcu->APB1RST, RCU_APB1RST_SPI2EN_MSK); -} -/** - * @brief SPI2 reset request disable bit - * @param rcu RCU Instance - * @retval None - */ -__STATIC_INLINE void md_rcu_disable_apb1rst_spi2en(RCU_TypeDef *rcu) -{ - CLEAR_BIT(rcu->APB1RST, RCU_APB1RST_SPI2EN_MSK); -} -/** - * @brief Get SPI2 reset request bit - * @param rcu RCU Instance - * @retval State of bit (1 or 0). - */ -__STATIC_INLINE uint32_t md_rcu_get_apb1rst_spi2en(RCU_TypeDef *rcu) -{ - return (READ_BIT(rcu->APB1RST, RCU_APB1RST_SPI2EN_MSK)>>RCU_APB1RST_SPI2EN_POS); -} -/** - * @brief IWDT reset request enable bit - * @param rcu RCU Instance - * @retval None - */ -__STATIC_INLINE void md_rcu_enable_apb1rst_iwdten(RCU_TypeDef *rcu) -{ - SET_BIT(rcu->APB1RST, RCU_APB1RST_IWDTEN_MSK); -} -/** - * @brief IWDT reset request disable bit - * @param rcu RCU Instance - * @retval None - */ -__STATIC_INLINE void md_rcu_disable_apb1rst_iwdten(RCU_TypeDef *rcu) -{ - CLEAR_BIT(rcu->APB1RST, RCU_APB1RST_IWDTEN_MSK); -} -/** - * @brief Get IWDT reset request bit - * @param rcu RCU Instance - * @retval State of bit (1 or 0). - */ -__STATIC_INLINE uint32_t md_rcu_get_apb1rst_iwdten(RCU_TypeDef *rcu) -{ - return (READ_BIT(rcu->APB1RST, RCU_APB1RST_IWDTEN_MSK)>>RCU_APB1RST_IWDTEN_POS); -} -/** - * @brief WWDT reset request enable bit - * @param rcu RCU Instance - * @retval None - */ -__STATIC_INLINE void md_rcu_enable_apb1rst_wwdten(RCU_TypeDef *rcu) -{ - SET_BIT(rcu->APB1RST, RCU_APB1RST_WWDTEN_MSK); -} -/** - * @brief WWDT reset request disable bit - * @param rcu RCU Instance - * @retval None - */ -__STATIC_INLINE void md_rcu_disable_apb1rst_wwdten(RCU_TypeDef *rcu) -{ - CLEAR_BIT(rcu->APB1RST, RCU_APB1RST_WWDTEN_MSK); -} -/** - * @brief Get WWDT reset request bit - * @param rcu RCU Instance - * @retval State of bit (1 or 0). - */ -__STATIC_INLINE uint32_t md_rcu_get_apb1rst_wwdten(RCU_TypeDef *rcu) -{ - return (READ_BIT(rcu->APB1RST, RCU_APB1RST_WWDTEN_MSK)>>RCU_APB1RST_WWDTEN_POS); -} -/** - * @brief BS16T1 reset request enable bit - * @param rcu RCU Instance - * @retval None - */ -__STATIC_INLINE void md_rcu_enable_apb1rst_bs16t1en(RCU_TypeDef *rcu) -{ - SET_BIT(rcu->APB1RST, RCU_APB1RST_BS16T1EN_MSK); -} -/** - * @brief BS16T1 reset request disable bit - * @param rcu RCU Instance - * @retval None - */ -__STATIC_INLINE void md_rcu_disable_apb1rst_bs16t1en(RCU_TypeDef *rcu) -{ - CLEAR_BIT(rcu->APB1RST, RCU_APB1RST_BS16T1EN_MSK); -} -/** - * @brief Get BS16T1 reset request bit - * @param rcu RCU Instance - * @retval State of bit (1 or 0). - */ -__STATIC_INLINE uint32_t md_rcu_get_apb1rst_bs16t1en(RCU_TypeDef *rcu) -{ - return (READ_BIT(rcu->APB1RST, RCU_APB1RST_BS16T1EN_MSK)>>RCU_APB1RST_BS16T1EN_POS); -} -/** - * @brief GP16C4T3 reset request enable bit - * @param rcu RCU Instance - * @retval None - */ -__STATIC_INLINE void md_rcu_enable_apb1rst_gp16c4t3en(RCU_TypeDef *rcu) -{ - SET_BIT(rcu->APB1RST, RCU_APB1RST_GP16C4T3EN_MSK); -} -/** - * @brief GP16C4T3 reset request disable bit - * @param rcu RCU Instance - * @retval None - */ -__STATIC_INLINE void md_rcu_disable_apb1rst_gp16c4t3en(RCU_TypeDef *rcu) -{ - CLEAR_BIT(rcu->APB1RST, RCU_APB1RST_GP16C4T3EN_MSK); -} -/** - * @brief Get GP16C4T3 reset request bit - * @param rcu RCU Instance - * @retval State of bit (1 or 0). - */ -__STATIC_INLINE uint32_t md_rcu_get_apb1rst_gp16c4t3en(RCU_TypeDef *rcu) -{ - return (READ_BIT(rcu->APB1RST, RCU_APB1RST_GP16C4T3EN_MSK)>>RCU_APB1RST_GP16C4T3EN_POS); -} -/** - * @brief GP16C4T2 reset request enable bit - * @param rcu RCU Instance - * @retval None - */ -__STATIC_INLINE void md_rcu_enable_apb1rst_gp16c4t2en(RCU_TypeDef *rcu) -{ - SET_BIT(rcu->APB1RST, RCU_APB1RST_GP16C4T2EN_MSK); -} -/** - * @brief GP16C4T2 reset request disable bit - * @param rcu RCU Instance - * @retval None - */ -__STATIC_INLINE void md_rcu_disable_apb1rst_gp16c4t2en(RCU_TypeDef *rcu) -{ - CLEAR_BIT(rcu->APB1RST, RCU_APB1RST_GP16C4T2EN_MSK); -} -/** - * @brief Get GP16C4T2 reset request bit - * @param rcu RCU Instance - * @retval State of bit (1 or 0). - */ -__STATIC_INLINE uint32_t md_rcu_get_apb1rst_gp16c4t2en(RCU_TypeDef *rcu) -{ - return (READ_BIT(rcu->APB1RST, RCU_APB1RST_GP16C4T2EN_MSK)>>RCU_APB1RST_GP16C4T2EN_POS); -} -/** - * @brief GP16C4T1 reset request enable bit - * @param rcu RCU Instance - * @retval None - */ -__STATIC_INLINE void md_rcu_enable_apb1rst_gp16c4t1en(RCU_TypeDef *rcu) -{ - SET_BIT(rcu->APB1RST, RCU_APB1RST_GP16C4T1EN_MSK); -} -/** - * @brief GP16C4T1 reset request disable bit - * @param rcu RCU Instance - * @retval None - */ -__STATIC_INLINE void md_rcu_disable_apb1rst_gp16c4t1en(RCU_TypeDef *rcu) -{ - CLEAR_BIT(rcu->APB1RST, RCU_APB1RST_GP16C4T1EN_MSK); -} -/** - * @brief Get GP16C4T1 reset request bit - * @param rcu RCU Instance - * @retval State of bit (1 or 0). - */ -__STATIC_INLINE uint32_t md_rcu_get_apb1rst_gp16c4t1en(RCU_TypeDef *rcu) -{ - return (READ_BIT(rcu->APB1RST, RCU_APB1RST_GP16C4T1EN_MSK)>>RCU_APB1RST_GP16C4T1EN_POS); -} -/** - * @brief GP32C4T1 reset request enable bit - * @param rcu RCU Instance - * @retval None - */ -__STATIC_INLINE void md_rcu_enable_apb1rst_gp32c4t1en(RCU_TypeDef *rcu) -{ - SET_BIT(rcu->APB1RST, RCU_APB1RST_GP32C4T1EN_MSK); -} -/** - * @brief GP32C4T1 reset request disable bit - * @param rcu RCU Instance - * @retval None - */ -__STATIC_INLINE void md_rcu_disable_apb1rst_gp32c4t1en(RCU_TypeDef *rcu) -{ - CLEAR_BIT(rcu->APB1RST, RCU_APB1RST_GP32C4T1EN_MSK); -} -/** - * @brief Get GP32C4T1 reset request bit - * @param rcu RCU Instance - * @retval State of bit (1 or 0). - */ -__STATIC_INLINE uint32_t md_rcu_get_apb1rst_gp32c4t1en(RCU_TypeDef *rcu) -{ - return (READ_BIT(rcu->APB1RST, RCU_APB1RST_GP32C4T1EN_MSK)>>RCU_APB1RST_GP32C4T1EN_POS); -} - -/** @defgroup MD_RCU_APB1RST_DACEN DACEN - * @brief Set DAC reset request bit for md_rcu_set_apb1rst() function used - * @param dacen This parameter can be one of the following values: - * @arg @ref DISABLE - * @arg @ref ENABLE - * @{ - */ -#define md_rcu_set_apb1rst_dacen_fun(dacen) (dacen<APB1RST, (dacen|i2c2en|i2c1en|suart2en|suart1en|uart3en|uart2en|spi2en|iwdten|wwdten| - bs16t1en|gp16c4t3en|gp16c4t2en|gp16c4t1en|gp32c4t1en)); -} - -/** - * @brief CMP reset request enable bit - * @param rcu RCU Instance - * @retval None - */ -__STATIC_INLINE void md_rcu_enable_apb2rst_cmpen(RCU_TypeDef *rcu) -{ - SET_BIT(rcu->APB2RST, RCU_APB2RST_CMPEN_MSK); -} -/** - * @brief CMP reset request disable bit - * @param rcu RCU Instance - * @retval None - */ -__STATIC_INLINE void md_rcu_disable_apb2rst_cmpen(RCU_TypeDef *rcu) -{ - CLEAR_BIT(rcu->APB2RST, RCU_APB2RST_CMPEN_MSK); -} -/** - * @brief Get CMP reset request bit - * @param rcu RCU Instance - * @retval State of bit (1 or 0). - */ -__STATIC_INLINE uint32_t md_rcu_get_apb2rst_cmpen(RCU_TypeDef *rcu) -{ - return (READ_BIT(rcu->APB2RST, RCU_APB2RST_CMPEN_MSK)>>RCU_APB2RST_CMPEN_POS); -} -/** - * @brief GP16C2T4 reset request enable bit - * @param rcu RCU Instance - * @retval None - */ -__STATIC_INLINE void md_rcu_enable_apb2rst_gp16c2t4en(RCU_TypeDef *rcu) -{ - SET_BIT(rcu->APB2RST, RCU_APB2RST_GP16C2T4EN_MSK); -} -/** - * @brief GP16C2T4 reset request disable bit - * @param rcu RCU Instance - * @retval None - */ -__STATIC_INLINE void md_rcu_disable_apb2rst_gp16c2t4en(RCU_TypeDef *rcu) -{ - CLEAR_BIT(rcu->APB2RST, RCU_APB2RST_GP16C2T4EN_MSK); -} -/** - * @brief Get GP16C2T4 reset request bit - * @param rcu RCU Instance - * @retval State of bit (1 or 0). - */ -__STATIC_INLINE uint32_t md_rcu_get_apb2rst_gp16c2t4en(RCU_TypeDef *rcu) -{ - return (READ_BIT(rcu->APB2RST, RCU_APB2RST_GP16C2T4EN_MSK)>>RCU_APB2RST_GP16C2T4EN_POS); -} -/** - * @brief GP16C2T3 reset request enable bit - * @param rcu RCU Instance - * @retval None - */ -__STATIC_INLINE void md_rcu_enable_apb2rst_gp16c2t3en(RCU_TypeDef *rcu) -{ - SET_BIT(rcu->APB2RST, RCU_APB2RST_GP16C2T3EN_MSK); -} -/** - * @brief GP16C2T3 reset request disable bit - * @param rcu RCU Instance - * @retval None - */ -__STATIC_INLINE void md_rcu_disable_apb2rst_gp16c2t3en(RCU_TypeDef *rcu) -{ - CLEAR_BIT(rcu->APB2RST, RCU_APB2RST_GP16C2T3EN_MSK); -} -/** - * @brief Get GP16C2T3 reset request bit - * @param rcu RCU Instance - * @retval State of bit (1 or 0). - */ -__STATIC_INLINE uint32_t md_rcu_get_apb2rst_gp16c2t3en(RCU_TypeDef *rcu) -{ - return (READ_BIT(rcu->APB2RST, RCU_APB2RST_GP16C2T3EN_MSK)>>RCU_APB2RST_GP16C2T3EN_POS); -} -/** - * @brief GP16C2T2 reset request enable bit - * @param rcu RCU Instance - * @retval None - */ -__STATIC_INLINE void md_rcu_enable_apb2rst_gp16c2t2en(RCU_TypeDef *rcu) -{ - SET_BIT(rcu->APB2RST, RCU_APB2RST_GP16C2T2EN_MSK); -} -/** - * @brief GP16C2T2 reset request disable bit - * @param rcu RCU Instance - * @retval None - */ -__STATIC_INLINE void md_rcu_disable_apb2rst_gp16c2t2en(RCU_TypeDef *rcu) -{ - CLEAR_BIT(rcu->APB2RST, RCU_APB2RST_GP16C2T2EN_MSK); -} -/** - * @brief Get GP16C2T2 reset request bit - * @param rcu RCU Instance - * @retval State of bit (1 or 0). - */ -__STATIC_INLINE uint32_t md_rcu_get_apb2rst_gp16c2t2en(RCU_TypeDef *rcu) -{ - return (READ_BIT(rcu->APB2RST, RCU_APB2RST_GP16C2T2EN_MSK)>>RCU_APB2RST_GP16C2T2EN_POS); -} -/** - * @brief GP16C2T1 reset request enable bit - * @param rcu RCU Instance - * @retval None - */ -__STATIC_INLINE void md_rcu_enable_apb2rst_gp16c2t1en(RCU_TypeDef *rcu) -{ - SET_BIT(rcu->APB2RST, RCU_APB2RST_GP16C2T1EN_MSK); -} -/** - * @brief GP16C2T1 reset request disable bit - * @param rcu RCU Instance - * @retval None - */ -__STATIC_INLINE void md_rcu_disable_apb2rst_gp16c2t1en(RCU_TypeDef *rcu) -{ - CLEAR_BIT(rcu->APB2RST, RCU_APB2RST_GP16C2T1EN_MSK); -} -/** - * @brief Get GP16C2T1 reset request bit - * @param rcu RCU Instance - * @retval State of bit (1 or 0). - */ -__STATIC_INLINE uint32_t md_rcu_get_apb2rst_gp16c2t1en(RCU_TypeDef *rcu) -{ - return (READ_BIT(rcu->APB2RST, RCU_APB2RST_GP16C2T1EN_MSK)>>RCU_APB2RST_GP16C2T1EN_POS); -} -/** - * @brief UART1 reset request enable bit - * @param rcu RCU Instance - * @retval None - */ -__STATIC_INLINE void md_rcu_enable_apb2rst_uart1en(RCU_TypeDef *rcu) -{ - SET_BIT(rcu->APB2RST, RCU_APB2RST_UART1EN_MSK); -} -/** - * @brief UART1 reset request disable bit - * @param rcu RCU Instance - * @retval None - */ -__STATIC_INLINE void md_rcu_disable_apb2rst_uart1en(RCU_TypeDef *rcu) -{ - CLEAR_BIT(rcu->APB2RST, RCU_APB2RST_UART1EN_MSK); -} -/** - * @brief Get UART1 reset request bit - * @param rcu RCU Instance - * @retval State of bit (1 or 0). - */ -__STATIC_INLINE uint32_t md_rcu_get_apb2rst_uart1en(RCU_TypeDef *rcu) -{ - return (READ_BIT(rcu->APB2RST, RCU_APB2RST_UART1EN_MSK)>>RCU_APB2RST_UART1EN_POS); -} -/** - * @brief SPI1 reset request enable bit - * @param rcu RCU Instance - * @retval None - */ -__STATIC_INLINE void md_rcu_enable_apb2rst_spi1en(RCU_TypeDef *rcu) -{ - SET_BIT(rcu->APB2RST, RCU_APB2RST_SPI1EN_MSK); -} -/** - * @brief SPI1 reset request disable bit - * @param rcu RCU Instance - * @retval None - */ -__STATIC_INLINE void md_rcu_disable_apb2rst_spi1en(RCU_TypeDef *rcu) -{ - CLEAR_BIT(rcu->APB2RST, RCU_APB2RST_SPI1EN_MSK); -} -/** - * @brief Get SPI1 reset request bit - * @param rcu RCU Instance - * @retval State of bit (1 or 0). - */ -__STATIC_INLINE uint32_t md_rcu_get_apb2rst_spi1en(RCU_TypeDef *rcu) -{ - return (READ_BIT(rcu->APB2RST, RCU_APB2RST_SPI1EN_MSK)>>RCU_APB2RST_SPI1EN_POS); -} -/** - * @brief AD16C4T1 reset request enable bit - * @param rcu RCU Instance - * @retval None - */ -__STATIC_INLINE void md_rcu_enable_apb2rst_ad16c4t1en(RCU_TypeDef *rcu) -{ - SET_BIT(rcu->APB2RST, RCU_APB2RST_AD16C4T1EN_MSK); -} -/** - * @brief AD16C4T1 reset request disable bit - * @param rcu RCU Instance - * @retval None - */ -__STATIC_INLINE void md_rcu_disable_apb2rst_ad16c4t1en(RCU_TypeDef *rcu) -{ - CLEAR_BIT(rcu->APB2RST, RCU_APB2RST_AD16C4T1EN_MSK); -} -/** - * @brief Get AD16C4T1 reset request bit - * @param rcu RCU Instance - * @retval State of bit (1 or 0). - */ -__STATIC_INLINE uint32_t md_rcu_get_apb2rst_ad16c4t1en(RCU_TypeDef *rcu) -{ - return (READ_BIT(rcu->APB2RST, RCU_APB2RST_AD16C4T1EN_MSK)>>RCU_APB2RST_AD16C4T1EN_POS); -} -/** - * @brief ADC reset request enable bit - * @param rcu RCU Instance - * @retval None - */ -__STATIC_INLINE void md_rcu_enable_apb2rst_adcen(RCU_TypeDef *rcu) -{ - SET_BIT(rcu->APB2RST, RCU_APB2RST_ADCEN_MSK); -} -/** - * @brief ADC reset request disable bit - * @param rcu RCU Instance - * @retval None - */ -__STATIC_INLINE void md_rcu_disable_apb2rst_adcen(RCU_TypeDef *rcu) -{ - CLEAR_BIT(rcu->APB2RST, RCU_APB2RST_ADCEN_MSK); -} -/** - * @brief Get ADC reset request bit - * @param rcu RCU Instance - * @retval State of bit (1 or 0). - */ -__STATIC_INLINE uint32_t md_rcu_get_apb2rst_adcen(RCU_TypeDef *rcu) -{ - return (READ_BIT(rcu->APB2RST, RCU_APB2RST_ADCEN_MSK)>>RCU_APB2RST_ADCEN_POS); -} - -/** @defgroup MD_RCU_APB2RST_CMPEN CMPEN - * @brief Set CMP reset request bit for md_rcu_set_apb2rst() function used - * @param cmpen This parameter can be one of the following values: - * @arg @ref DISABLE - * @arg @ref ENABLE - * @{ - */ -#define md_rcu_set_apb2rst_cmpen_fun(cmpen) (cmpen<APB2RST, (cmpen|gp16c2t4en|gp16c2t3en|gp16c2t2en|gp16c2t1en|uart1en|spi1en|ad16c4t1en|adcen)); -} - -/** - * @brief GPIOD clock enable bit. - * @param rcu RCU Instance - * @retval None - */ -__STATIC_INLINE void md_rcu_enable_ahben_gpden(RCU_TypeDef *rcu) -{ - SET_BIT(rcu->AHBEN, RCU_AHBEN_GPDEN_MSK); -} -/** - * @brief GPIOD Clock disable bit - * @param rcu RCU Instance - * @retval None - */ -__STATIC_INLINE void md_rcu_disable_ahben_gpden(RCU_TypeDef *rcu) -{ - CLEAR_BIT(rcu->AHBEN, RCU_AHBEN_GPDEN_MSK); -} -/** - * @brief Get GPIOD Clock bit - * @param rcu RCU Instance - * @retval State of bit (1 or 0). - */ -__STATIC_INLINE uint32_t md_rcu_get_ahben_gpden(RCU_TypeDef *rcu) -{ - return (READ_BIT(rcu->AHBEN, RCU_AHBEN_GPDEN_MSK)>>RCU_AHBEN_GPDEN_POS); -} -/** - * @brief GPIOC clock enable bit. - * @param rcu RCU Instance - * @retval None - */ -__STATIC_INLINE void md_rcu_enable_ahben_gpcen(RCU_TypeDef *rcu) -{ - SET_BIT(rcu->AHBEN, RCU_AHBEN_GPCEN_MSK); -} -/** - * @brief GPIOC Clock disable bit - * @param rcu RCU Instance - * @retval None - */ -__STATIC_INLINE void md_rcu_disable_ahben_gpcen(RCU_TypeDef *rcu) -{ - CLEAR_BIT(rcu->AHBEN, RCU_AHBEN_GPCEN_MSK); -} -/** - * @brief Get GPIOC Clock bit - * @param rcu RCU Instance - * @retval State of bit (1 or 0). - */ -__STATIC_INLINE uint32_t md_rcu_get_ahben_gpcen(RCU_TypeDef *rcu) -{ - return (READ_BIT(rcu->AHBEN, RCU_AHBEN_GPCEN_MSK)>>RCU_AHBEN_GPCEN_POS); -} -/** - * @brief GPIOB clock enable bit. - * @param rcu RCU Instance - * @retval None - */ -__STATIC_INLINE void md_rcu_enable_ahben_gpben(RCU_TypeDef *rcu) -{ - SET_BIT(rcu->AHBEN, RCU_AHBEN_GPBEN_MSK); -} -/** - * @brief GPIOB Clock disable bit - * @param rcu RCU Instance - * @retval None - */ -__STATIC_INLINE void md_rcu_disable_ahben_gpben(RCU_TypeDef *rcu) -{ - CLEAR_BIT(rcu->AHBEN, RCU_AHBEN_GPBEN_MSK); -} -/** - * @brief Get GPIOB Clock bit - * @param rcu RCU Instance - * @retval State of bit (1 or 0). - */ -__STATIC_INLINE uint32_t md_rcu_get_ahben_gpben(RCU_TypeDef *rcu) -{ - return (READ_BIT(rcu->AHBEN, RCU_AHBEN_GPBEN_MSK)>>RCU_AHBEN_GPBEN_POS); -} -/** - * @brief GPIOA clock enable bit. - * @param rcu RCU Instance - * @retval None - */ -__STATIC_INLINE void md_rcu_enable_ahben_gpaen(RCU_TypeDef *rcu) -{ - SET_BIT(rcu->AHBEN, RCU_AHBEN_GPAEN_MSK); -} -/** - * @brief GPIOA Clock disable bit - * @param rcu RCU Instance - * @retval None - */ -__STATIC_INLINE void md_rcu_disable_ahben_gpaen(RCU_TypeDef *rcu) -{ - CLEAR_BIT(rcu->AHBEN, RCU_AHBEN_GPAEN_MSK); -} -/** - * @brief Get GPIOA Clock bit - * @param rcu RCU Instance - * @retval State of bit (1 or 0). - */ -__STATIC_INLINE uint32_t md_rcu_get_ahben_gpaen(RCU_TypeDef *rcu) -{ - return (READ_BIT(rcu->AHBEN, RCU_AHBEN_GPAEN_MSK)>>RCU_AHBEN_GPAEN_POS); -} -/** - * @brief HDIV clock enable bit. - * @param rcu RCU Instance - * @retval None - */ -__STATIC_INLINE void md_rcu_enable_ahben_hdiven(RCU_TypeDef *rcu) -{ - SET_BIT(rcu->AHBEN, RCU_AHBEN_HDIVEN_MSK); -} -/** - * @brief HDIV Clock disable bit - * @param rcu RCU Instance - * @retval None - */ -__STATIC_INLINE void md_rcu_disable_ahben_hdiven(RCU_TypeDef *rcu) -{ - CLEAR_BIT(rcu->AHBEN, RCU_AHBEN_HDIVEN_MSK); -} -/** - * @brief Get HDIV Clock bit - * @param rcu RCU Instance - * @retval State of bit (1 or 0). - */ -__STATIC_INLINE uint32_t md_rcu_get_ahben_hdiven(RCU_TypeDef *rcu) -{ - return (READ_BIT(rcu->AHBEN, RCU_AHBEN_HDIVEN_MSK)>>RCU_AHBEN_HDIVEN_POS); -} -/** - * @brief USB clock enable bit. - * @param rcu RCU Instance - * @retval None - */ -__STATIC_INLINE void md_rcu_enable_ahben_usben(RCU_TypeDef *rcu) -{ - SET_BIT(rcu->AHBEN, RCU_AHBEN_USBEN_MSK); -} -/** - * @brief USB Clock disable bit - * @param rcu RCU Instance - * @retval None - */ -__STATIC_INLINE void md_rcu_disable_ahben_usben(RCU_TypeDef *rcu) -{ - CLEAR_BIT(rcu->AHBEN, RCU_AHBEN_USBEN_MSK); -} -/** - * @brief Get USB Clock bit - * @param rcu RCU Instance - * @retval State of bit (1 or 0). - */ -__STATIC_INLINE uint32_t md_rcu_get_ahben_usben(RCU_TypeDef *rcu) -{ - return (READ_BIT(rcu->AHBEN, RCU_AHBEN_USBEN_MSK)>>RCU_AHBEN_USBEN_POS); -} -/** - * @brief AES clock enable bit. - * @param rcu RCU Instance - * @retval None - */ -__STATIC_INLINE void md_rcu_enable_ahben_aesen(RCU_TypeDef *rcu) -{ - SET_BIT(rcu->AHBEN, RCU_AHBEN_AESEN_MSK); -} -/** - * @brief AES Clock disable bit - * @param rcu RCU Instance - * @retval None - */ -__STATIC_INLINE void md_rcu_disable_ahben_aesen(RCU_TypeDef *rcu) -{ - CLEAR_BIT(rcu->AHBEN, RCU_AHBEN_AESEN_MSK); -} -/** - * @brief Get AES Clock bit - * @param rcu RCU Instance - * @retval State of bit (1 or 0). - */ -__STATIC_INLINE uint32_t md_rcu_get_ahben_aesen(RCU_TypeDef *rcu) -{ - return (READ_BIT(rcu->AHBEN, RCU_AHBEN_AESEN_MSK)>>RCU_AHBEN_AESEN_POS); -} -/** - * @brief CRC clock enable bit. - * @param rcu RCU Instance - * @retval None - */ -__STATIC_INLINE void md_rcu_enable_ahben_crcen(RCU_TypeDef *rcu) -{ - SET_BIT(rcu->AHBEN, RCU_AHBEN_CRCEN_MSK); -} -/** - * @brief CRC Clock disable bit - * @param rcu RCU Instance - * @retval None - */ -__STATIC_INLINE void md_rcu_disable_ahben_crcen(RCU_TypeDef *rcu) -{ - CLEAR_BIT(rcu->AHBEN, RCU_AHBEN_CRCEN_MSK); -} -/** - * @brief Get CRC Clock bit - * @param rcu RCU Instance - * @retval State of bit (1 or 0). - */ -__STATIC_INLINE uint32_t md_rcu_get_ahben_crcen(RCU_TypeDef *rcu) -{ - return (READ_BIT(rcu->AHBEN, RCU_AHBEN_CRCEN_MSK)>>RCU_AHBEN_CRCEN_POS); -} -/** - * @brief RTC clock enable bit. - * @param rcu RCU Instance - * @retval None - */ -__STATIC_INLINE void md_rcu_enable_ahben_rtcen(RCU_TypeDef *rcu) -{ - SET_BIT(rcu->AHBEN, RCU_AHBEN_RTCEN_MSK); -} -/** - * @brief RTC Clock disable bit - * @param rcu RCU Instance - * @retval None - */ -__STATIC_INLINE void md_rcu_disable_ahben_rtcen(RCU_TypeDef *rcu) -{ - CLEAR_BIT(rcu->AHBEN, RCU_AHBEN_RTCEN_MSK); -} -/** - * @brief Get RTC Clock bit - * @param rcu RCU Instance - * @retval State of bit (1 or 0). - */ -__STATIC_INLINE uint32_t md_rcu_get_ahben_rtcen(RCU_TypeDef *rcu) -{ - return (READ_BIT(rcu->AHBEN, RCU_AHBEN_RTCEN_MSK)>>RCU_AHBEN_RTCEN_POS); -} -/** - * @brief DMA1 clock enable bit. - * @param rcu RCU Instance - * @retval None - */ -__STATIC_INLINE void md_rcu_enable_ahben_dma1en(RCU_TypeDef *rcu) -{ - SET_BIT(rcu->AHBEN, RCU_AHBEN_DMA1EN_MSK); -} -/** - * @brief DMA1 Clock disable bit - * @param rcu RCU Instance - * @retval None - */ -__STATIC_INLINE void md_rcu_disable_ahben_dma1en(RCU_TypeDef *rcu) -{ - CLEAR_BIT(rcu->AHBEN, RCU_AHBEN_DMA1EN_MSK); -} -/** - * @brief Get DMA1 Clock bit - * @param rcu RCU Instance - * @retval State of bit (1 or 0). - */ -__STATIC_INLINE uint32_t md_rcu_get_ahben_dma1en(RCU_TypeDef *rcu) -{ - return (READ_BIT(rcu->AHBEN, RCU_AHBEN_DMA1EN_MSK)>>RCU_AHBEN_DMA1EN_POS); -} - -/** @defgroup MD_RCU_AHBEN_GPDEN GPDEN - * @brief Set GPIOD clock bit for md_rcu_set_ahben() function used - * @param gpden This parameter can be one of the following values: - * @arg @ref DISABLE - * @arg @ref ENABLE - * @{ - */ -#define md_rcu_set_ahben_gpden_fun(gpden) (gpden<AHBEN, (gpden|gpcen|gpben|gpaen|hdiven|usben|aesen|crcen|rtcen|dma1en)); -} - -/** - * @brief DAC clock enable bit. - * @param rcu RCU Instance - * @retval None - */ -__STATIC_INLINE void md_rcu_enable_apb1en_dacen(RCU_TypeDef *rcu) -{ - SET_BIT(rcu->APB1EN, RCU_APB1EN_DACEN_MSK); -} -/** - * @brief DAC Clock disable bit - * @param rcu RCU Instance - * @retval None - */ -__STATIC_INLINE void md_rcu_disable_apb1en_dacen(RCU_TypeDef *rcu) -{ - CLEAR_BIT(rcu->APB1EN, RCU_APB1EN_DACEN_MSK); -} -/** - * @brief Get DAC Clock bit - * @param rcu RCU Instance - * @retval State of bit (1 or 0). - */ -__STATIC_INLINE uint32_t md_rcu_get_apb1en_dacen(RCU_TypeDef *rcu) -{ - return (READ_BIT(rcu->APB1EN, RCU_APB1EN_DACEN_MSK)>>RCU_APB1EN_DACEN_POS); -} -/** - * @brief I2C2 clock enable bit. - * @param rcu RCU Instance - * @retval None - */ -__STATIC_INLINE void md_rcu_enable_apb1en_i2c2en(RCU_TypeDef *rcu) -{ - SET_BIT(rcu->APB1EN, RCU_APB1EN_I2C2EN_MSK); -} -/** - * @brief I2C2 Clock disable bit - * @param rcu RCU Instance - * @retval None - */ -__STATIC_INLINE void md_rcu_disable_apb1en_i2c2en(RCU_TypeDef *rcu) -{ - CLEAR_BIT(rcu->APB1EN, RCU_APB1EN_I2C2EN_MSK); -} -/** - * @brief Get I2C2 Clock bit - * @param rcu RCU Instance - * @retval State of bit (1 or 0). - */ -__STATIC_INLINE uint32_t md_rcu_get_apb1en_i2c2en(RCU_TypeDef *rcu) -{ - return (READ_BIT(rcu->APB1EN, RCU_APB1EN_I2C2EN_MSK)>>RCU_APB1EN_I2C2EN_POS); -} -/** - * @brief I2C1 clock enable bit. - * @param rcu RCU Instance - * @retval None - */ -__STATIC_INLINE void md_rcu_enable_apb1en_i2c1en(RCU_TypeDef *rcu) -{ - SET_BIT(rcu->APB1EN, RCU_APB1EN_I2C1EN_MSK); -} -/** - * @brief I2C1 Clock disable bit - * @param rcu RCU Instance - * @retval None - */ -__STATIC_INLINE void md_rcu_disable_apb1en_i2c1en(RCU_TypeDef *rcu) -{ - CLEAR_BIT(rcu->APB1EN, RCU_APB1EN_I2C1EN_MSK); -} -/** - * @brief Get I2C1 Clock bit - * @param rcu RCU Instance - * @retval State of bit (1 or 0). - */ -__STATIC_INLINE uint32_t md_rcu_get_apb1en_i2c1en(RCU_TypeDef *rcu) -{ - return (READ_BIT(rcu->APB1EN, RCU_APB1EN_I2C1EN_MSK)>>RCU_APB1EN_I2C1EN_POS); -} -/** - * @brief SUART2 clock enable bit. - * @param rcu RCU Instance - * @retval None - */ -__STATIC_INLINE void md_rcu_enable_apb1en_suart2en(RCU_TypeDef *rcu) -{ - SET_BIT(rcu->APB1EN, RCU_APB1EN_SUART2EN_MSK); -} -/** - * @brief SUART2 Clock disable bit - * @param rcu RCU Instance - * @retval None - */ -__STATIC_INLINE void md_rcu_disable_apb1en_suart2en(RCU_TypeDef *rcu) -{ - CLEAR_BIT(rcu->APB1EN, RCU_APB1EN_SUART2EN_MSK); -} -/** - * @brief Get SUART2 Clock bit - * @param rcu RCU Instance - * @retval State of bit (1 or 0). - */ -__STATIC_INLINE uint32_t md_rcu_get_apb1en_suart2en(RCU_TypeDef *rcu) -{ - return (READ_BIT(rcu->APB1EN, RCU_APB1EN_SUART2EN_MSK)>>RCU_APB1EN_SUART2EN_POS); -} -/** - * @brief SUART1 clock enable bit. - * @param rcu RCU Instance - * @retval None - */ -__STATIC_INLINE void md_rcu_enable_apb1en_suart1en(RCU_TypeDef *rcu) -{ - SET_BIT(rcu->APB1EN, RCU_APB1EN_SUART1EN_MSK); -} -/** - * @brief SUART1 Clock disable bit - * @param rcu RCU Instance - * @retval None - */ -__STATIC_INLINE void md_rcu_disable_apb1en_suart1en(RCU_TypeDef *rcu) -{ - CLEAR_BIT(rcu->APB1EN, RCU_APB1EN_SUART1EN_MSK); -} -/** - * @brief Get SUART1 Clock bit - * @param rcu RCU Instance - * @retval State of bit (1 or 0). - */ -__STATIC_INLINE uint32_t md_rcu_get_apb1en_suart1en(RCU_TypeDef *rcu) -{ - return (READ_BIT(rcu->APB1EN, RCU_APB1EN_SUART1EN_MSK)>>RCU_APB1EN_SUART1EN_POS); -} -/** - * @brief UART3 clock enable bit. - * @param rcu RCU Instance - * @retval None - */ -__STATIC_INLINE void md_rcu_enable_apb1en_uart3en(RCU_TypeDef *rcu) -{ - SET_BIT(rcu->APB1EN, RCU_APB1EN_UART3EN_MSK); -} -/** - * @brief UART3 Clock disable bit - * @param rcu RCU Instance - * @retval None - */ -__STATIC_INLINE void md_rcu_disable_apb1en_uart3en(RCU_TypeDef *rcu) -{ - CLEAR_BIT(rcu->APB1EN, RCU_APB1EN_UART3EN_MSK); -} -/** - * @brief Get UART3 Clock bit - * @param rcu RCU Instance - * @retval State of bit (1 or 0). - */ -__STATIC_INLINE uint32_t md_rcu_get_apb1en_uart3en(RCU_TypeDef *rcu) -{ - return (READ_BIT(rcu->APB1EN, RCU_APB1EN_UART3EN_MSK)>>RCU_APB1EN_UART3EN_POS); -} -/** - * @brief UART2 clock enable bit. - * @param rcu RCU Instance - * @retval None - */ -__STATIC_INLINE void md_rcu_enable_apb1en_uart2en(RCU_TypeDef *rcu) -{ - SET_BIT(rcu->APB1EN, RCU_APB1EN_UART2EN_MSK); -} -/** - * @brief UART2 Clock disable bit - * @param rcu RCU Instance - * @retval None - */ -__STATIC_INLINE void md_rcu_disable_apb1en_uart2en(RCU_TypeDef *rcu) -{ - CLEAR_BIT(rcu->APB1EN, RCU_APB1EN_UART2EN_MSK); -} -/** - * @brief Get UART2 Clock bit - * @param rcu RCU Instance - * @retval State of bit (1 or 0). - */ -__STATIC_INLINE uint32_t md_rcu_get_apb1en_uart2en(RCU_TypeDef *rcu) -{ - return (READ_BIT(rcu->APB1EN, RCU_APB1EN_UART2EN_MSK)>>RCU_APB1EN_UART2EN_POS); -} -/** - * @brief SPI2 clock enable bit. - * @param rcu RCU Instance - * @retval None - */ -__STATIC_INLINE void md_rcu_enable_apb1en_spi2en(RCU_TypeDef *rcu) -{ - SET_BIT(rcu->APB1EN, RCU_APB1EN_SPI2EN_MSK); -} -/** - * @brief SPI2 Clock disable bit - * @param rcu RCU Instance - * @retval None - */ -__STATIC_INLINE void md_rcu_disable_apb1en_spi2en(RCU_TypeDef *rcu) -{ - CLEAR_BIT(rcu->APB1EN, RCU_APB1EN_SPI2EN_MSK); -} -/** - * @brief Get SPI2 Clock bit - * @param rcu RCU Instance - * @retval State of bit (1 or 0). - */ -__STATIC_INLINE uint32_t md_rcu_get_apb1en_spi2en(RCU_TypeDef *rcu) -{ - return (READ_BIT(rcu->APB1EN, RCU_APB1EN_SPI2EN_MSK)>>RCU_APB1EN_SPI2EN_POS); -} -/** - * @brief IWDT clock enable bit. - * @param rcu RCU Instance - * @retval None - */ -__STATIC_INLINE void md_rcu_enable_apb1en_iwdten(RCU_TypeDef *rcu) -{ - SET_BIT(rcu->APB1EN, RCU_APB1EN_IWDTEN_MSK); -} -/** - * @brief IWDT Clock disable bit - * @param rcu RCU Instance - * @retval None - */ -__STATIC_INLINE void md_rcu_disable_apb1en_iwdten(RCU_TypeDef *rcu) -{ - CLEAR_BIT(rcu->APB1EN, RCU_APB1EN_IWDTEN_MSK); -} -/** - * @brief Get IWDT Clock bit - * @param rcu RCU Instance - * @retval State of bit (1 or 0). - */ -__STATIC_INLINE uint32_t md_rcu_get_apb1en_iwdten(RCU_TypeDef *rcu) -{ - return (READ_BIT(rcu->APB1EN, RCU_APB1EN_IWDTEN_MSK)>>RCU_APB1EN_IWDTEN_POS); -} -/** - * @brief WWDT clock enable bit. - * @param rcu RCU Instance - * @retval None - */ -__STATIC_INLINE void md_rcu_enable_apb1en_wwdten(RCU_TypeDef *rcu) -{ - SET_BIT(rcu->APB1EN, RCU_APB1EN_WWDTEN_MSK); -} -/** - * @brief WWDT Clock disable bit - * @param rcu RCU Instance - * @retval None - */ -__STATIC_INLINE void md_rcu_disable_apb1en_wwdten(RCU_TypeDef *rcu) -{ - CLEAR_BIT(rcu->APB1EN, RCU_APB1EN_WWDTEN_MSK); -} -/** - * @brief Get WWDT Clock bit - * @param rcu RCU Instance - * @retval State of bit (1 or 0). - */ -__STATIC_INLINE uint32_t md_rcu_get_apb1en_wwdten(RCU_TypeDef *rcu) -{ - return (READ_BIT(rcu->APB1EN, RCU_APB1EN_WWDTEN_MSK)>>RCU_APB1EN_WWDTEN_POS); -} -/** - * @brief BS16T1 clock enable bit. - * @param rcu RCU Instance - * @retval None - */ -__STATIC_INLINE void md_rcu_enable_apb1en_bs16t1en(RCU_TypeDef *rcu) -{ - SET_BIT(rcu->APB1EN, RCU_APB1EN_BS16T1EN_MSK); -} -/** - * @brief BS16T1 Clock disable bit - * @param rcu RCU Instance - * @retval None - */ -__STATIC_INLINE void md_rcu_disable_apb1en_bs16t1en(RCU_TypeDef *rcu) -{ - CLEAR_BIT(rcu->APB1EN, RCU_APB1EN_BS16T1EN_MSK); -} -/** - * @brief Get BS16T1 Clock bit - * @param rcu RCU Instance - * @retval State of bit (1 or 0). - */ -__STATIC_INLINE uint32_t md_rcu_get_apb1en_bs16t1en(RCU_TypeDef *rcu) -{ - return (READ_BIT(rcu->APB1EN, RCU_APB1EN_BS16T1EN_MSK)>>RCU_APB1EN_BS16T1EN_POS); -} -/** - * @brief GP16C4T3 clock enable bit. - * @param rcu RCU Instance - * @retval None - */ -__STATIC_INLINE void md_rcu_enable_apb1en_gp16c4t3en(RCU_TypeDef *rcu) -{ - SET_BIT(rcu->APB1EN, RCU_APB1EN_GP16C4T3EN_MSK); -} -/** - * @brief GP16C4T3 Clock disable bit - * @param rcu RCU Instance - * @retval None - */ -__STATIC_INLINE void md_rcu_disable_apb1en_gp16c4t3en(RCU_TypeDef *rcu) -{ - CLEAR_BIT(rcu->APB1EN, RCU_APB1EN_GP16C4T3EN_MSK); -} -/** - * @brief Get GP16C4T3 Clock bit - * @param rcu RCU Instance - * @retval State of bit (1 or 0). - */ -__STATIC_INLINE uint32_t md_rcu_get_apb1en_gp16c4t3en(RCU_TypeDef *rcu) -{ - return (READ_BIT(rcu->APB1EN, RCU_APB1EN_GP16C4T3EN_MSK)>>RCU_APB1EN_GP16C4T3EN_POS); -} -/** - * @brief GP16C4T2 clock enable bit. - * @param rcu RCU Instance - * @retval None - */ -__STATIC_INLINE void md_rcu_enable_apb1en_gp16c4t2en(RCU_TypeDef *rcu) -{ - SET_BIT(rcu->APB1EN, RCU_APB1EN_GP16C4T2EN_MSK); -} -/** - * @brief GP16C4T2 Clock disable bit - * @param rcu RCU Instance - * @retval None - */ -__STATIC_INLINE void md_rcu_disable_apb1en_gp16c4t2en(RCU_TypeDef *rcu) -{ - CLEAR_BIT(rcu->APB1EN, RCU_APB1EN_GP16C4T2EN_MSK); -} -/** - * @brief Get GP16C4T2 Clock bit - * @param rcu RCU Instance - * @retval State of bit (1 or 0). - */ -__STATIC_INLINE uint32_t md_rcu_get_apb1en_gp16c4t2en(RCU_TypeDef *rcu) -{ - return (READ_BIT(rcu->APB1EN, RCU_APB1EN_GP16C4T2EN_MSK)>>RCU_APB1EN_GP16C4T2EN_POS); -} -/** - * @brief GP16C4T1 clock enable bit. - * @param rcu RCU Instance - * @retval None - */ -__STATIC_INLINE void md_rcu_enable_apb1en_gp16c4t1en(RCU_TypeDef *rcu) -{ - SET_BIT(rcu->APB1EN, RCU_APB1EN_GP16C4T1EN_MSK); -} -/** - * @brief GP16C4T1 Clock disable bit - * @param rcu RCU Instance - * @retval None - */ -__STATIC_INLINE void md_rcu_disable_apb1en_gp16c4t1en(RCU_TypeDef *rcu) -{ - CLEAR_BIT(rcu->APB1EN, RCU_APB1EN_GP16C4T1EN_MSK); -} -/** - * @brief Get GP16C4T1 Clock bit - * @param rcu RCU Instance - * @retval State of bit (1 or 0). - */ -__STATIC_INLINE uint32_t md_rcu_get_apb1en_gp16c4t1en(RCU_TypeDef *rcu) -{ - return (READ_BIT(rcu->APB1EN, RCU_APB1EN_GP16C4T1EN_MSK)>>RCU_APB1EN_GP16C4T1EN_POS); -} -/** - * @brief GP32C4T1 clock enable bit. - * @param rcu RCU Instance - * @retval None - */ -__STATIC_INLINE void md_rcu_enable_apb1en_gp32c4t1en(RCU_TypeDef *rcu) -{ - SET_BIT(rcu->APB1EN, RCU_APB1EN_GP32C4T1EN_MSK); -} -/** - * @brief GP32C4T1 Clock disable bit - * @param rcu RCU Instance - * @retval None - */ -__STATIC_INLINE void md_rcu_disable_apb1en_gp32c4t1en(RCU_TypeDef *rcu) -{ - CLEAR_BIT(rcu->APB1EN, RCU_APB1EN_GP32C4T1EN_MSK); -} -/** - * @brief Get GP32C4T1 Clock bit - * @param rcu RCU Instance - * @retval State of bit (1 or 0). - */ -__STATIC_INLINE uint32_t md_rcu_get_apb1en_gp32c4t1en(RCU_TypeDef *rcu) -{ - return (READ_BIT(rcu->APB1EN, RCU_APB1EN_GP32C4T1EN_MSK)>>RCU_APB1EN_GP32C4T1EN_POS); -} - -/** @defgroup MD_RCU_APB1EN_DACEN DACEN - * @brief Set DAC clock bit for md_rcu_set_apb1en() function used - * @param dacen This parameter can be one of the following values: - * @arg @ref DISABLE - * @arg @ref ENABLE - * @{ - */ -#define md_rcu_set_apb1en_dacen_fun(dacen) (dacen<APB1EN, (dacen|i2c2en|i2c1en|suart2en|suart1en|uart3en|uart2en|spi2en|iwdten|wwdten| - bs16t1en|gp16c4t3en|gp16c4t2en|gp16c4t1en|gp32c4t1en)); -} - -/** - * @brief CMP clock enable bit. - * @param rcu RCU Instance - * @retval None - */ -__STATIC_INLINE void md_rcu_enable_apb2en_cmpen(RCU_TypeDef *rcu) -{ - SET_BIT(rcu->APB2EN, RCU_APB2EN_CMPEN_MSK); -} -/** - * @brief CMP Clock disable bit - * @param rcu RCU Instance - * @retval None - */ -__STATIC_INLINE void md_rcu_disable_apb2en_cmpen(RCU_TypeDef *rcu) -{ - CLEAR_BIT(rcu->APB2EN, RCU_APB2EN_CMPEN_MSK); -} -/** - * @brief Get CMP Clock bit - * @param rcu RCU Instance - * @retval State of bit (1 or 0). - */ -__STATIC_INLINE uint32_t md_rcu_get_apb2en_cmpen(RCU_TypeDef *rcu) -{ - return (READ_BIT(rcu->APB2EN, RCU_APB2EN_CMPEN_MSK)>>RCU_APB2EN_CMPEN_POS); -} -/** - * @brief GP16C2T4EN clock enable bit. - * @param rcu RCU Instance - * @retval None - */ -__STATIC_INLINE void md_rcu_enable_apb2en_gp16c2t4en(RCU_TypeDef *rcu) -{ - SET_BIT(rcu->APB2EN, RCU_APB2EN_GP16C2T4EN_MSK); -} -/** - * @brief GP16C2T4EN Clock disable bit - * @param rcu RCU Instance - * @retval None - */ -__STATIC_INLINE void md_rcu_disable_apb2en_gp16c2t4en(RCU_TypeDef *rcu) -{ - CLEAR_BIT(rcu->APB2EN, RCU_APB2EN_GP16C2T4EN_MSK); -} -/** - * @brief Get GP16C2T4EN Clock bit - * @param rcu RCU Instance - * @retval State of bit (1 or 0). - */ -__STATIC_INLINE uint32_t md_rcu_get_apb2en_gp16c2t4en(RCU_TypeDef *rcu) -{ - return (READ_BIT(rcu->APB2EN, RCU_APB2EN_GP16C2T4EN_MSK)>>RCU_APB2EN_GP16C2T4EN_POS); -} -/** - * @brief GP16C2T3EN clock enable bit. - * @param rcu RCU Instance - * @retval None - */ -__STATIC_INLINE void md_rcu_enable_apb2en_gp16c2t3en(RCU_TypeDef *rcu) -{ - SET_BIT(rcu->APB2EN, RCU_APB2EN_GP16C2T3EN_MSK); -} -/** - * @brief GP16C2T3EN Clock disable bit - * @param rcu RCU Instance - * @retval None - */ -__STATIC_INLINE void md_rcu_disable_apb2en_gp16c2t3en(RCU_TypeDef *rcu) -{ - CLEAR_BIT(rcu->APB2EN, RCU_APB2EN_GP16C2T3EN_MSK); -} -/** - * @brief Get GP16C2T3EN Clock bit - * @param rcu RCU Instance - * @retval State of bit (1 or 0). - */ -__STATIC_INLINE uint32_t md_rcu_get_apb2en_gp16c2t3en(RCU_TypeDef *rcu) -{ - return (READ_BIT(rcu->APB2EN, RCU_APB2EN_GP16C2T3EN_MSK)>>RCU_APB2EN_GP16C2T3EN_POS); -} -/** - * @brief GP16C2T2EN clock enable bit. - * @param rcu RCU Instance - * @retval None - */ -__STATIC_INLINE void md_rcu_enable_apb2en_gp16c2t2en(RCU_TypeDef *rcu) -{ - SET_BIT(rcu->APB2EN, RCU_APB2EN_GP16C2T2EN_MSK); -} -/** - * @brief GP16C2T2EN Clock disable bit - * @param rcu RCU Instance - * @retval None - */ -__STATIC_INLINE void md_rcu_disable_apb2en_gp16c2t2en(RCU_TypeDef *rcu) -{ - CLEAR_BIT(rcu->APB2EN, RCU_APB2EN_GP16C2T2EN_MSK); -} -/** - * @brief Get GP16C2T2EN Clock bit - * @param rcu RCU Instance - * @retval State of bit (1 or 0). - */ -__STATIC_INLINE uint32_t md_rcu_get_apb2en_gp16c2t2en(RCU_TypeDef *rcu) -{ - return (READ_BIT(rcu->APB2EN, RCU_APB2EN_GP16C2T2EN_MSK)>>RCU_APB2EN_GP16C2T2EN_POS); -} -/** - * @brief GP16C2T1EN clock enable bit. - * @param rcu RCU Instance - * @retval None - */ -__STATIC_INLINE void md_rcu_enable_apb2en_gp16c2t1en(RCU_TypeDef *rcu) -{ - SET_BIT(rcu->APB2EN, RCU_APB2EN_GP16C2T1EN_MSK); -} -/** - * @brief GP16C2T1EN Clock disable bit - * @param rcu RCU Instance - * @retval None - */ -__STATIC_INLINE void md_rcu_disable_apb2en_gp16c2t1en(RCU_TypeDef *rcu) -{ - CLEAR_BIT(rcu->APB2EN, RCU_APB2EN_GP16C2T1EN_MSK); -} -/** - * @brief Get GP16C2T1EN Clock bit - * @param rcu RCU Instance - * @retval State of bit (1 or 0). - */ -__STATIC_INLINE uint32_t md_rcu_get_apb2en_gp16c2t1en(RCU_TypeDef *rcu) -{ - return (READ_BIT(rcu->APB2EN, RCU_APB2EN_GP16C2T1EN_MSK)>>RCU_APB2EN_GP16C2T1EN_POS); -} -/** - * @brief UART1EN clock enable bit. - * @param rcu RCU Instance - * @retval None - */ -__STATIC_INLINE void md_rcu_enable_apb2en_uart1en(RCU_TypeDef *rcu) -{ - SET_BIT(rcu->APB2EN, RCU_APB2EN_UART1EN_MSK); -} -/** - * @brief UART1EN Clock disable bit - * @param rcu RCU Instance - * @retval None - */ -__STATIC_INLINE void md_rcu_disable_apb2en_uart1en(RCU_TypeDef *rcu) -{ - CLEAR_BIT(rcu->APB2EN, RCU_APB2EN_UART1EN_MSK); -} -/** - * @brief Get UART1EN Clock bit - * @param rcu RCU Instance - * @retval State of bit (1 or 0). - */ -__STATIC_INLINE uint32_t md_rcu_get_apb2en_uart1en(RCU_TypeDef *rcu) -{ - return (READ_BIT(rcu->APB2EN, RCU_APB2EN_UART1EN_MSK)>>RCU_APB2EN_UART1EN_POS); -} -/** - * @brief SPI1EN clock enable bit. - * @param rcu RCU Instance - * @retval None - */ -__STATIC_INLINE void md_rcu_enable_apb2en_spi1en(RCU_TypeDef *rcu) -{ - SET_BIT(rcu->APB2EN, RCU_APB2EN_SPI1EN_MSK); -} -/** - * @brief SPI1EN Clock disable bit - * @param rcu RCU Instance - * @retval None - */ -__STATIC_INLINE void md_rcu_disable_apb2en_spi1en(RCU_TypeDef *rcu) -{ - CLEAR_BIT(rcu->APB2EN, RCU_APB2EN_SPI1EN_MSK); -} -/** - * @brief Get SPI1EN Clock bit - * @param rcu RCU Instance - * @retval State of bit (1 or 0). - */ -__STATIC_INLINE uint32_t md_rcu_get_apb2en_spi1en(RCU_TypeDef *rcu) -{ - return (READ_BIT(rcu->APB2EN, RCU_APB2EN_SPI1EN_MSK)>>RCU_APB2EN_SPI1EN_POS); -} -/** - * @brief AD16C4T1EN clock enable bit. - * @param rcu RCU Instance - * @retval None - */ -__STATIC_INLINE void md_rcu_enable_apb2en_ad16c4t1en(RCU_TypeDef *rcu) -{ - SET_BIT(rcu->APB2EN, RCU_APB2EN_AD16C4T1EN_MSK); -} -/** - * @brief AD16C4T1EN Clock disable bit - * @param rcu RCU Instance - * @retval None - */ -__STATIC_INLINE void md_rcu_disable_apb2en_ad16c4t1en(RCU_TypeDef *rcu) -{ - CLEAR_BIT(rcu->APB2EN, RCU_APB2EN_AD16C4T1EN_MSK); -} -/** - * @brief Get AD16C4T1EN Clock bit - * @param rcu RCU Instance - * @retval State of bit (1 or 0). - */ -__STATIC_INLINE uint32_t md_rcu_get_apb2en_ad16c4t1en(RCU_TypeDef *rcu) -{ - return (READ_BIT(rcu->APB2EN, RCU_APB2EN_AD16C4T1EN_MSK)>>RCU_APB2EN_AD16C4T1EN_POS); -} -/** - * @brief ADCEN clock enable bit. - * @param rcu RCU Instance - * @retval None - */ -__STATIC_INLINE void md_rcu_enable_apb2en_adcen(RCU_TypeDef *rcu) -{ - SET_BIT(rcu->APB2EN, RCU_APB2EN_ADCEN_MSK); -} -/** - * @brief ADCEN Clock disable bit - * @param rcu RCU Instance - * @retval None - */ -__STATIC_INLINE void md_rcu_disable_apb2en_adcen(RCU_TypeDef *rcu) -{ - CLEAR_BIT(rcu->APB2EN, RCU_APB2EN_ADCEN_MSK); -} -/** - * @brief Get ADCEN Clock bit - * @param rcu RCU Instance - * @retval State of bit (1 or 0). - */ -__STATIC_INLINE uint32_t md_rcu_get_apb2en_adcen(RCU_TypeDef *rcu) -{ - return (READ_BIT(rcu->APB2EN, RCU_APB2EN_ADCEN_MSK)>>RCU_APB2EN_ADCEN_POS); -} - -/** @defgroup MD_RCU_APB2EN_CMPEN CMPEN - * @brief Set CMP clock bit for md_rcu_set_apb2en() function used - * @param cmpen This parameter can be one of the following values: - * @arg @ref DISABLE - * @arg @ref ENABLE - * @{ - */ -#define md_rcu_set_apb2en_cmpen_fun(cmpen) (cmpen<APB2EN, (cmpen|gp16c2t4en|gp16c2t3en|gp16c2t2en|gp16c2t1en|uart1en|spi1en|ad16c4t1en|adcen)); -} - - - - - - - - - - -/** - * @brief GPDEN clock enable during Sleep mode bit. - * @param rcu RCU Instance - * @retval None - */ -__STATIC_INLINE void md_rcu_enable_ahbsl_gpden(RCU_TypeDef *rcu) -{ - SET_BIT(rcu->AHBSL, RCU_AHBSL_GPDEN_MSK); -} -/** - * @brief GPDEN clock disable during Sleep mode bit. - * @param rcu RCU Instance - * @retval None - */ -__STATIC_INLINE void md_rcu_disable_ahbsl_gpden(RCU_TypeDef *rcu) -{ - CLEAR_BIT(rcu->AHBSL, RCU_AHBSL_GPDEN_MSK); -} -/** - * @brief Get GPDEN clock during Sleep mode bit. - * @param rcu RCU Instance - * @retval State of bit (1 or 0). - */ -__STATIC_INLINE uint32_t md_rcu_get_ahbsl_gpden(RCU_TypeDef *rcu) -{ - return (READ_BIT(rcu->AHBSL, RCU_AHBSL_GPDEN_MSK)>>RCU_AHBSL_GPDEN_POS); -} -/** - * @brief GPCEN clock enable during Sleep mode bit. - * @param rcu RCU Instance - * @retval None - */ -__STATIC_INLINE void md_rcu_enable_ahbsl_gpcen(RCU_TypeDef *rcu) -{ - SET_BIT(rcu->AHBSL, RCU_AHBSL_GPCEN_MSK); -} -/** - * @brief GPCEN clock disable during Sleep mode bit. - * @param rcu RCU Instance - * @retval None - */ -__STATIC_INLINE void md_rcu_disable_ahbsl_gpcen(RCU_TypeDef *rcu) -{ - CLEAR_BIT(rcu->AHBSL, RCU_AHBSL_GPCEN_MSK); -} -/** - * @brief Get GPCEN clock during Sleep mode bit. - * @param rcu RCU Instance - * @retval State of bit (1 or 0). - */ -__STATIC_INLINE uint32_t md_rcu_get_ahbsl_gpcen(RCU_TypeDef *rcu) -{ - return (READ_BIT(rcu->AHBSL, RCU_AHBSL_GPCEN_MSK)>>RCU_AHBSL_GPCEN_POS); -} -/** - * @brief GPBEN clock enable during Sleep mode bit. - * @param rcu RCU Instance - * @retval None - */ -__STATIC_INLINE void md_rcu_enable_ahbsl_gpben(RCU_TypeDef *rcu) -{ - SET_BIT(rcu->AHBSL, RCU_AHBSL_GPBEN_MSK); -} -/** - * @brief GPBEN clock disable during Sleep mode bit. - * @param rcu RCU Instance - * @retval None - */ -__STATIC_INLINE void md_rcu_disable_ahbsl_gpben(RCU_TypeDef *rcu) -{ - CLEAR_BIT(rcu->AHBSL, RCU_AHBSL_GPBEN_MSK); -} -/** - * @brief Get GPBEN clock during Sleep mode bit. - * @param rcu RCU Instance - * @retval State of bit (1 or 0). - */ -__STATIC_INLINE uint32_t md_rcu_get_ahbsl_gpben(RCU_TypeDef *rcu) -{ - return (READ_BIT(rcu->AHBSL, RCU_AHBSL_GPBEN_MSK)>>RCU_AHBSL_GPBEN_POS); -} -/** - * @brief GPAEN clock enable during Sleep mode bit. - * @param rcu RCU Instance - * @retval None - */ -__STATIC_INLINE void md_rcu_enable_ahbsl_gpaen(RCU_TypeDef *rcu) -{ - SET_BIT(rcu->AHBSL, RCU_AHBSL_GPAEN_MSK); -} -/** - * @brief GPAEN clock disable during Sleep mode bit. - * @param rcu RCU Instance - * @retval None - */ -__STATIC_INLINE void md_rcu_disable_ahbsl_gpaen(RCU_TypeDef *rcu) -{ - CLEAR_BIT(rcu->AHBSL, RCU_AHBSL_GPAEN_MSK); -} -/** - * @brief Get GPAEN clock during Sleep mode bit. - * @param rcu RCU Instance - * @retval State of bit (1 or 0). - */ -__STATIC_INLINE uint32_t md_rcu_get_ahbsl_gpaen(RCU_TypeDef *rcu) -{ - return (READ_BIT(rcu->AHBSL, RCU_AHBSL_GPAEN_MSK)>>RCU_AHBSL_GPAEN_POS); -} -/** - * @brief HDIVEN clock enable during Sleep mode bit. - * @param rcu RCU Instance - * @retval None - */ -__STATIC_INLINE void md_rcu_enable_ahbsl_hdiven(RCU_TypeDef *rcu) -{ - SET_BIT(rcu->AHBSL, RCU_AHBSL_HDIVEN_MSK); -} -/** - * @brief HDIVEN clock disable during Sleep mode bit. - * @param rcu RCU Instance - * @retval None - */ -__STATIC_INLINE void md_rcu_disable_ahbsl_hdiven(RCU_TypeDef *rcu) -{ - CLEAR_BIT(rcu->AHBSL, RCU_AHBSL_HDIVEN_MSK); -} -/** - * @brief Get HDIVEN clock during Sleep mode bit. - * @param rcu RCU Instance - * @retval State of bit (1 or 0). - */ -__STATIC_INLINE uint32_t md_rcu_get_ahbsl_hdiven(RCU_TypeDef *rcu) -{ - return (READ_BIT(rcu->AHBSL, RCU_AHBSL_HDIVEN_MSK)>>RCU_AHBSL_HDIVEN_POS); -} -/** - * @brief USBEN clock enable during Sleep mode bit. - * @param rcu RCU Instance - * @retval None - */ -__STATIC_INLINE void md_rcu_enable_ahbsl_usben(RCU_TypeDef *rcu) -{ - SET_BIT(rcu->AHBSL, RCU_AHBSL_USBEN_MSK); -} -/** - * @brief USBEN clock disable during Sleep mode bit. - * @param rcu RCU Instance - * @retval None - */ -__STATIC_INLINE void md_rcu_disable_ahbsl_usben(RCU_TypeDef *rcu) -{ - CLEAR_BIT(rcu->AHBSL, RCU_AHBSL_USBEN_MSK); -} -/** - * @brief Get USBEN clock during Sleep mode bit. - * @param rcu RCU Instance - * @retval State of bit (1 or 0). - */ -__STATIC_INLINE uint32_t md_rcu_get_ahbsl_usben(RCU_TypeDef *rcu) -{ - return (READ_BIT(rcu->AHBSL, RCU_AHBSL_USBEN_MSK)>>RCU_AHBSL_USBEN_POS); -} -/** - * @brief AESEN clock enable during Sleep mode bit. - * @param rcu RCU Instance - * @retval None - */ -__STATIC_INLINE void md_rcu_enable_ahbsl_aesen(RCU_TypeDef *rcu) -{ - SET_BIT(rcu->AHBSL, RCU_AHBSL_AESEN_MSK); -} -/** - * @brief AESEN clock disable during Sleep mode bit. - * @param rcu RCU Instance - * @retval None - */ -__STATIC_INLINE void md_rcu_disable_ahbsl_aesen(RCU_TypeDef *rcu) -{ - CLEAR_BIT(rcu->AHBSL, RCU_AHBSL_AESEN_MSK); -} -/** - * @brief Get AESEN clock during Sleep mode bit. - * @param rcu RCU Instance - * @retval State of bit (1 or 0). - */ -__STATIC_INLINE uint32_t md_rcu_get_ahbsl_aesen(RCU_TypeDef *rcu) -{ - return (READ_BIT(rcu->AHBSL, RCU_AHBSL_AESEN_MSK)>>RCU_AHBSL_AESEN_POS); -} -/** - * @brief CRCEN clock enable during Sleep mode bit. - * @param rcu RCU Instance - * @retval None - */ -__STATIC_INLINE void md_rcu_enable_ahbsl_crcen(RCU_TypeDef *rcu) -{ - SET_BIT(rcu->AHBSL, RCU_AHBSL_CRCEN_MSK); -} -/** - * @brief CRCEN clock disable during Sleep mode bit. - * @param rcu RCU Instance - * @retval None - */ -__STATIC_INLINE void md_rcu_disable_ahbsl_crcen(RCU_TypeDef *rcu) -{ - CLEAR_BIT(rcu->AHBSL, RCU_AHBSL_CRCEN_MSK); -} -/** - * @brief Get CRCEN clock during Sleep mode bit. - * @param rcu RCU Instance - * @retval State of bit (1 or 0). - */ -__STATIC_INLINE uint32_t md_rcu_get_ahbsl_crcen(RCU_TypeDef *rcu) -{ - return (READ_BIT(rcu->AHBSL, RCU_AHBSL_CRCEN_MSK)>>RCU_AHBSL_CRCEN_POS); -} -/** - * @brief RTCEN clock enable during Sleep mode bit. - * @param rcu RCU Instance - * @retval None - */ -__STATIC_INLINE void md_rcu_enable_ahbsl_rtcen(RCU_TypeDef *rcu) -{ - SET_BIT(rcu->AHBSL, RCU_AHBSL_RTCEN_MSK); -} -/** - * @brief RTCEN clock disable during Sleep mode bit. - * @param rcu RCU Instance - * @retval None - */ -__STATIC_INLINE void md_rcu_disable_ahbsl_rtcen(RCU_TypeDef *rcu) -{ - CLEAR_BIT(rcu->AHBSL, RCU_AHBSL_RTCEN_MSK); -} -/** - * @brief Get RTCEN clock during Sleep mode bit. - * @param rcu RCU Instance - * @retval State of bit (1 or 0). - */ -__STATIC_INLINE uint32_t md_rcu_get_ahbsl_rtcen(RCU_TypeDef *rcu) -{ - return (READ_BIT(rcu->AHBSL, RCU_AHBSL_RTCEN_MSK)>>RCU_AHBSL_RTCEN_POS); -} -/** - * @brief DMA1EN clock enable during Sleep mode bit. - * @param rcu RCU Instance - * @retval None - */ -__STATIC_INLINE void md_rcu_enable_ahbsl_dma1en(RCU_TypeDef *rcu) -{ - SET_BIT(rcu->AHBSL, RCU_AHBSL_DMA1EN_MSK); -} -/** - * @brief DMA1EN clock disable during Sleep mode bit. - * @param rcu RCU Instance - * @retval None - */ -__STATIC_INLINE void md_rcu_disable_ahbsl_dma1en(RCU_TypeDef *rcu) -{ - CLEAR_BIT(rcu->AHBSL, RCU_AHBSL_DMA1EN_MSK); -} -/** - * @brief Get DMA1EN clock during Sleep mode bit. - * @param rcu RCU Instance - * @retval State of bit (1 or 0). - */ -__STATIC_INLINE uint32_t md_rcu_get_ahbsl_dma1en(RCU_TypeDef *rcu) -{ - return (READ_BIT(rcu->AHBSL, RCU_AHBSL_DMA1EN_MSK)>>RCU_AHBSL_DMA1EN_POS); -} - -/** - * @brief DAC clock enable during Sleep mode bit. - * @param rcu RCU Instance - * @retval None - */ -__STATIC_INLINE void md_rcu_enable_apb1sl_dacen(RCU_TypeDef *rcu) -{ - SET_BIT(rcu->APB1SL, RCU_APB1SL_DACEN_MSK); -} -/** - * @brief DAC clock disable during Sleep mode bit. - * @param rcu RCU Instance - * @retval None - */ -__STATIC_INLINE void md_rcu_disable_apb1sl_dacen(RCU_TypeDef *rcu) -{ - CLEAR_BIT(rcu->APB1SL, RCU_APB1SL_DACEN_MSK); -} -/** - * @brief Get DAC clock during Sleep mode bit. - * @param rcu RCU Instance - * @retval State of bit (1 or 0). - */ -__STATIC_INLINE uint32_t md_rcu_get_apb1sl_dacen(RCU_TypeDef *rcu) -{ - return (READ_BIT(rcu->APB1SL, RCU_APB1SL_DACEN_MSK)>>RCU_APB1SL_DACEN_POS); -} -/** - * @brief I2C2EN clock enable during Sleep mode bit. - * @param rcu RCU Instance - * @retval None - */ -__STATIC_INLINE void md_rcu_enable_apb1sl_i2c2en(RCU_TypeDef *rcu) -{ - SET_BIT(rcu->APB1SL, RCU_APB1SL_I2C2EN_MSK); -} -/** - * @brief I2C2EN clock disable during Sleep mode bit. - * @param rcu RCU Instance - * @retval None - */ -__STATIC_INLINE void md_rcu_disable_apb1sl_i2c2en(RCU_TypeDef *rcu) -{ - CLEAR_BIT(rcu->APB1SL, RCU_APB1SL_I2C2EN_MSK); -} -/** - * @brief Get I2C2EN clock during Sleep mode bit. - * @param rcu RCU Instance - * @retval State of bit (1 or 0). - */ -__STATIC_INLINE uint32_t md_rcu_get_apb1sl_i2c2en(RCU_TypeDef *rcu) -{ - return (READ_BIT(rcu->APB1SL, RCU_APB1SL_I2C2EN_MSK)>>RCU_APB1SL_I2C2EN_POS); -} -/** - * @brief I2C1EN clock enable during Sleep mode bit. - * @param rcu RCU Instance - * @retval None - */ -__STATIC_INLINE void md_rcu_enable_apb1sl_i2c1en(RCU_TypeDef *rcu) -{ - SET_BIT(rcu->APB1SL, RCU_APB1SL_I2C1EN_MSK); -} -/** - * @brief I2C1EN clock disable during Sleep mode bit. - * @param rcu RCU Instance - * @retval None - */ -__STATIC_INLINE void md_rcu_disable_apb1sl_i2c1en(RCU_TypeDef *rcu) -{ - CLEAR_BIT(rcu->APB1SL, RCU_APB1SL_I2C1EN_MSK); -} -/** - * @brief Get I2C1EN clock during Sleep mode bit. - * @param rcu RCU Instance - * @retval State of bit (1 or 0). - */ -__STATIC_INLINE uint32_t md_rcu_get_apb1sl_i2c1en(RCU_TypeDef *rcu) -{ - return (READ_BIT(rcu->APB1SL, RCU_APB1SL_I2C1EN_MSK)>>RCU_APB1SL_I2C1EN_POS); -} -/** - * @brief SUART2EN clock enable during Sleep mode bit. - * @param rcu RCU Instance - * @retval None - */ -__STATIC_INLINE void md_rcu_enable_apb1sl_suart2en(RCU_TypeDef *rcu) -{ - SET_BIT(rcu->APB1SL, RCU_APB1SL_SUART2EN_MSK); -} -/** - * @brief SUART2EN clock disable during Sleep mode bit. - * @param rcu RCU Instance - * @retval None - */ -__STATIC_INLINE void md_rcu_disable_apb1sl_suart2en(RCU_TypeDef *rcu) -{ - CLEAR_BIT(rcu->APB1SL, RCU_APB1SL_SUART2EN_MSK); -} -/** - * @brief Get SUART2EN clock during Sleep mode bit. - * @param rcu RCU Instance - * @retval State of bit (1 or 0). - */ -__STATIC_INLINE uint32_t md_rcu_get_apb1sl_suart2en(RCU_TypeDef *rcu) -{ - return (READ_BIT(rcu->APB1SL, RCU_APB1SL_SUART2EN_MSK)>>RCU_APB1SL_SUART2EN_POS); -} -/** - * @brief SUART1EN clock enable during Sleep mode bit. - * @param rcu RCU Instance - * @retval None - */ -__STATIC_INLINE void md_rcu_enable_apb1sl_suart1en(RCU_TypeDef *rcu) -{ - SET_BIT(rcu->APB1SL, RCU_APB1SL_SUART1EN_MSK); -} -/** - * @brief SUART1EN clock disable during Sleep mode bit. - * @param rcu RCU Instance - * @retval None - */ -__STATIC_INLINE void md_rcu_disable_apb1sl_suart1en(RCU_TypeDef *rcu) -{ - CLEAR_BIT(rcu->APB1SL, RCU_APB1SL_SUART1EN_MSK); -} -/** - * @brief Get SUART1EN clock during Sleep mode bit. - * @param rcu RCU Instance - * @retval State of bit (1 or 0). - */ -__STATIC_INLINE uint32_t md_rcu_get_apb1sl_suart1en(RCU_TypeDef *rcu) -{ - return (READ_BIT(rcu->APB1SL, RCU_APB1SL_SUART1EN_MSK)>>RCU_APB1SL_SUART1EN_POS); -} -/** - * @brief UART3EN clock enable during Sleep mode bit. - * @param rcu RCU Instance - * @retval None - */ -__STATIC_INLINE void md_rcu_enable_apb1sl_uart3en(RCU_TypeDef *rcu) -{ - SET_BIT(rcu->APB1SL, RCU_APB1SL_UART3EN_MSK); -} -/** - * @brief UART3EN clock disable during Sleep mode bit. - * @param rcu RCU Instance - * @retval None - */ -__STATIC_INLINE void md_rcu_disable_apb1sl_uart3en(RCU_TypeDef *rcu) -{ - CLEAR_BIT(rcu->APB1SL, RCU_APB1SL_UART3EN_MSK); -} -/** - * @brief Get UART3EN clock during Sleep mode bit. - * @param rcu RCU Instance - * @retval State of bit (1 or 0). - */ -__STATIC_INLINE uint32_t md_rcu_get_apb1sl_uart3en(RCU_TypeDef *rcu) -{ - return (READ_BIT(rcu->APB1SL, RCU_APB1SL_UART3EN_MSK)>>RCU_APB1SL_UART3EN_POS); -} -/** - * @brief UART2EN clock enable during Sleep mode bit. - * @param rcu RCU Instance - * @retval None - */ -__STATIC_INLINE void md_rcu_enable_apb1sl_uart2en(RCU_TypeDef *rcu) -{ - SET_BIT(rcu->APB1SL, RCU_APB1SL_UART2EN_MSK); -} -/** - * @brief UART2EN clock disable during Sleep mode bit. - * @param rcu RCU Instance - * @retval None - */ -__STATIC_INLINE void md_rcu_disable_apb1sl_uart2en(RCU_TypeDef *rcu) -{ - CLEAR_BIT(rcu->APB1SL, RCU_APB1SL_UART2EN_MSK); -} -/** - * @brief Get UART2EN clock during Sleep mode bit. - * @param rcu RCU Instance - * @retval State of bit (1 or 0). - */ -__STATIC_INLINE uint32_t md_rcu_get_apb1sl_uart2en(RCU_TypeDef *rcu) -{ - return (READ_BIT(rcu->APB1SL, RCU_APB1SL_UART2EN_MSK)>>RCU_APB1SL_UART2EN_POS); -} -/** - * @brief SPI2EN clock enable during Sleep mode bit. - * @param rcu RCU Instance - * @retval None - */ -__STATIC_INLINE void md_rcu_enable_apb1sl_spi2en(RCU_TypeDef *rcu) -{ - SET_BIT(rcu->APB1SL, RCU_APB1SL_SPI2EN_MSK); -} -/** - * @brief SPI2EN clock disable during Sleep mode bit. - * @param rcu RCU Instance - * @retval None - */ -__STATIC_INLINE void md_rcu_disable_apb1sl_spi2en(RCU_TypeDef *rcu) -{ - CLEAR_BIT(rcu->APB1SL, RCU_APB1SL_SPI2EN_MSK); -} -/** - * @brief Get SPI2EN clock during Sleep mode bit. - * @param rcu RCU Instance - * @retval State of bit (1 or 0). - */ -__STATIC_INLINE uint32_t md_rcu_get_apb1sl_spi2en(RCU_TypeDef *rcu) -{ - return (READ_BIT(rcu->APB1SL, RCU_APB1SL_SPI2EN_MSK)>>RCU_APB1SL_SPI2EN_POS); -} -/** - * @brief IWDTEN clock enable during Sleep mode bit. - * @param rcu RCU Instance - * @retval None - */ -__STATIC_INLINE void md_rcu_enable_apb1sl_iwdten(RCU_TypeDef *rcu) -{ - SET_BIT(rcu->APB1SL, RCU_APB1SL_IWDTEN_MSK); -} -/** - * @brief IWDTEN clock disable during Sleep mode bit. - * @param rcu RCU Instance - * @retval None - */ -__STATIC_INLINE void md_rcu_disable_apb1sl_iwdgen(RCU_TypeDef *rcu) -{ - CLEAR_BIT(rcu->APB1SL, RCU_APB1SL_IWDTEN_MSK); -} -/** - * @brief Get IWDTEN clock during Sleep mode bit. - * @param rcu RCU Instance - * @retval State of bit (1 or 0). - */ -__STATIC_INLINE uint32_t md_rcu_get_apb1sl_iwdten(RCU_TypeDef *rcu) -{ - return (READ_BIT(rcu->APB1SL, RCU_APB1SL_IWDTEN_MSK)>>RCU_APB1SL_IWDTEN_POS); -} -/** - * @brief WWDTEN clock enable during Sleep mode bit. - * @param rcu RCU Instance - * @retval None - */ -__STATIC_INLINE void md_rcu_enable_apb1sl_wwdten(RCU_TypeDef *rcu) -{ - SET_BIT(rcu->APB1SL, RCU_APB1SL_WWDTEN_MSK); -} -/** - * @brief WWDTEN clock disable during Sleep mode bit. - * @param rcu RCU Instance - * @retval None - */ -__STATIC_INLINE void md_rcu_disable_apb1sl_wwdten(RCU_TypeDef *rcu) -{ - CLEAR_BIT(rcu->APB1SL, RCU_APB1SL_WWDTEN_MSK); -} -/** - * @brief Get WWDTEN clock during Sleep mode bit. - * @param rcu RCU Instance - * @retval State of bit (1 or 0). - */ -__STATIC_INLINE uint32_t md_rcu_get_apb1sl_wwdten(RCU_TypeDef *rcu) -{ - return (READ_BIT(rcu->APB1SL, RCU_APB1SL_WWDTEN_MSK)>>RCU_APB1SL_WWDTEN_POS); -} -/** - * @brief BS16T1EN clock enable during Sleep mode bit. - * @param rcu RCU Instance - * @retval None - */ -__STATIC_INLINE void md_rcu_enable_apb1sl_bs16t1en(RCU_TypeDef *rcu) -{ - SET_BIT(rcu->APB1SL, RCU_APB1SL_BS16T1EN_MSK); -} -/** - * @brief BS16T1EN clock disable during Sleep mode bit. - * @param rcu RCU Instance - * @retval None - */ -__STATIC_INLINE void md_rcu_disable_apb1sl_bs16t1en(RCU_TypeDef *rcu) -{ - CLEAR_BIT(rcu->APB1SL, RCU_APB1SL_BS16T1EN_MSK); -} -/** - * @brief Get BS16T1EN clock during Sleep mode bit. - * @param rcu RCU Instance - * @retval State of bit (1 or 0). - */ -__STATIC_INLINE uint32_t md_rcu_get_apb1sl_bs16t1en(RCU_TypeDef *rcu) -{ - return (READ_BIT(rcu->APB1SL, RCU_APB1SL_BS16T1EN_MSK)>>RCU_APB1SL_BS16T1EN_POS); -} -/** - * @brief GP16C4T3EN clock enable during Sleep mode bit. - * @param rcu RCU Instance - * @retval None - */ -__STATIC_INLINE void md_rcu_enable_apb1sl_gp16c4t3en(RCU_TypeDef *rcu) -{ - SET_BIT(rcu->APB1SL, RCU_APB1SL_GP16C4T3EN_MSK); -} -/** - * @brief GP16C4T3EN clock disable during Sleep mode bit. - * @param rcu RCU Instance - * @retval None - */ -__STATIC_INLINE void md_rcu_disable_apb1sl_gp16c4t3en(RCU_TypeDef *rcu) -{ - CLEAR_BIT(rcu->APB1SL, RCU_APB1SL_GP16C4T3EN_MSK); -} -/** - * @brief Get GP16C4T3EN clock during Sleep mode bit. - * @param rcu RCU Instance - * @retval State of bit (1 or 0). - */ -__STATIC_INLINE uint32_t md_rcu_get_apb1sl_gp16c4t3en(RCU_TypeDef *rcu) -{ - return (READ_BIT(rcu->APB1SL, RCU_APB1SL_GP16C4T3EN_MSK)>>RCU_APB1SL_GP16C4T3EN_POS); -} -/** - * @brief GP16C4T2EN clock enable during Sleep mode bit. - * @param rcu RCU Instance - * @retval None - */ -__STATIC_INLINE void md_rcu_enable_apb1sl_gp16c4t2en(RCU_TypeDef *rcu) -{ - SET_BIT(rcu->APB1SL, RCU_APB1SL_GP16C4T2EN_MSK); -} -/** - * @brief GP16C4T2EN clock disable during Sleep mode bit. - * @param rcu RCU Instance - * @retval None - */ -__STATIC_INLINE void md_rcu_disable_apb1sl_gp16c4t2en(RCU_TypeDef *rcu) -{ - CLEAR_BIT(rcu->APB1SL, RCU_APB1SL_GP16C4T2EN_MSK); -} -/** - * @brief Get GP16C4T2EN clock during Sleep mode bit. - * @param rcu RCU Instance - * @retval State of bit (1 or 0). -y*/ -__STATIC_INLINE uint32_t md_rcu_get_apb1sl_gp16c4t2en(RCU_TypeDef *rcu) -{ - return (READ_BIT(rcu->APB1SL, RCU_APB1SL_GP16C4T2EN_MSK)>>RCU_APB1SL_GP16C4T2EN_POS); -} -/** - * @brief GP16C4T1EN clock enable during Sleep mode bit. - * @param rcu RCU Instance - * @retval None - */ -__STATIC_INLINE void md_rcu_enable_apb1sl_gp16c4t1en(RCU_TypeDef *rcu) -{ - SET_BIT(rcu->APB1SL, RCU_APB1SL_GP16C4T1EN_MSK); -} -/** - * @brief GP16C4T1EN clock disable during Sleep mode bit. - * @param rcu RCU Instance - * @retval None - */ -__STATIC_INLINE void md_rcu_disable_apb1sl_gp16c4t1en(RCU_TypeDef *rcu) -{ - CLEAR_BIT(rcu->APB1SL, RCU_APB1SL_GP16C4T1EN_MSK); -} -/** - * @brief Get GP16C4T1EN clock during Sleep mode bit. - * @param rcu RCU Instance - * @retval State of bit (1 or 0). - */ -__STATIC_INLINE uint32_t md_rcu_get_apb1sl_gp16c4t1en(RCU_TypeDef *rcu) -{ - return (READ_BIT(rcu->APB1SL, RCU_APB1SL_GP16C4T1EN_MSK)>>RCU_APB1SL_GP16C4T1EN_POS); -} -/** - * @brief GP32C4T1EN clock enable during Sleep mode bit. - * @param rcu RCU Instance - * @retval None - */ -__STATIC_INLINE void md_rcu_enable_apb1sl_gp32c4t1en(RCU_TypeDef *rcu) -{ - SET_BIT(rcu->APB1SL, RCU_APB1SL_GP32C4T1EN_MSK); -} -/** - * @brief GP32C4T1EN clock disable during Sleep mode bit. - * @param rcu RCU Instance - * @retval None - */ -__STATIC_INLINE void md_rcu_disable_apb1sl_gp32c4t1en(RCU_TypeDef *rcu) -{ - CLEAR_BIT(rcu->APB1SL, RCU_APB1SL_GP32C4T1EN_MSK); -} -/** - * @brief Get GP32C4T1EN clock during Sleep mode bit. - * @param rcu RCU Instance - * @retval State of bit (1 or 0). - */ -__STATIC_INLINE uint32_t md_rcu_get_apb1sl_gp32c4t1en(RCU_TypeDef *rcu) -{ - return (READ_BIT(rcu->APB1SL, RCU_APB1SL_GP32C4T1EN_MSK)>>RCU_APB1SL_GP32C4T1EN_POS); -} - -/** - * @brief CMP clock enable during Sleep mode bit. - * @param rcu RCU Instance - * @retval None - */ -__STATIC_INLINE void md_rcu_enable_apb2sl_cmpen(RCU_TypeDef *rcu) -{ - SET_BIT(rcu->APB2SL, RCU_APB2SL_CMPEN_MSK); -} -/** - * @brief CMP clock disable during Sleep mode bit. - * @param rcu RCU Instance - * @retval None - */ -__STATIC_INLINE void md_rcu_disable_apb2sl_cmpen(RCU_TypeDef *rcu) -{ - CLEAR_BIT(rcu->APB2SL, RCU_APB2SL_CMPEN_MSK); -} -/** - * @brief Get CMP clock during Sleep mode bit. - * @param rcu RCU Instance - * @retval State of bit (1 or 0). - */ -__STATIC_INLINE uint32_t md_rcu_get_apb2sl_cmpen(RCU_TypeDef *rcu) -{ - return (READ_BIT(rcu->APB2SL, RCU_APB2SL_CMPEN_MSK)>>RCU_APB2SL_CMPEN_POS); -} -/** - * @brief GP16C2T4EN clock enable during Sleep mode bit. - * @param rcu RCU Instance - * @retval None - */ -__STATIC_INLINE void md_rcu_enable_apb2sl_gp16c2t4en(RCU_TypeDef *rcu) -{ - SET_BIT(rcu->APB2SL, RCU_APB2SL_GP16C2T4EN_MSK); -} -/** - * @brief GP16C2T4EN clock disable during Sleep mode bit. - * @param rcu RCU Instance - * @retval None - */ -__STATIC_INLINE void md_rcu_disable_apb2sl_gp16c2t4en(RCU_TypeDef *rcu) -{ - CLEAR_BIT(rcu->APB2SL, RCU_APB2SL_GP16C2T4EN_MSK); -} -/** - * @brief Get GP16C2T4EN clock during Sleep mode bit. - * @param rcu RCU Instance - * @retval State of bit (1 or 0). - */ -__STATIC_INLINE uint32_t md_rcu_get_apb2sl_gp16c2t4en(RCU_TypeDef *rcu) -{ - return (READ_BIT(rcu->APB2SL, RCU_APB2SL_GP16C2T4EN_MSK)>>RCU_APB2SL_GP16C2T4EN_POS); -} -/** - * @brief GP16C2T3EN clock enable during Sleep mode bit. - * @param rcu RCU Instance - * @retval None - */ -__STATIC_INLINE void md_rcu_enable_apb2sl_gp16c2t3en(RCU_TypeDef *rcu) -{ - SET_BIT(rcu->APB2SL, RCU_APB2SL_GP16C2T3EN_MSK); -} -/** - * @brief GP16C2T3EN clock disable during Sleep mode bit. - * @param rcu RCU Instance - * @retval None - */ -__STATIC_INLINE void md_rcu_disable_apb2sl_gp16c2t3en(RCU_TypeDef *rcu) -{ - CLEAR_BIT(rcu->APB2SL, RCU_APB2SL_GP16C2T3EN_MSK); -} -/** - * @brief Get GP16C2T3EN clock during Sleep mode bit. - * @param rcu RCU Instance - * @retval State of bit (1 or 0). - */ -__STATIC_INLINE uint32_t md_rcu_get_apb2sl_gp16c2t3en(RCU_TypeDef *rcu) -{ - return (READ_BIT(rcu->APB2SL, RCU_APB2SL_GP16C2T3EN_MSK)>>RCU_APB2SL_GP16C2T3EN_POS); -} -/** - * @brief GP16C2T2EN clock enable during Sleep mode bit. - * @param rcu RCU Instance - * @retval None - */ -__STATIC_INLINE void md_rcu_enable_apb2sl_gp16c2t2en(RCU_TypeDef *rcu) -{ - SET_BIT(rcu->APB2SL, RCU_APB2SL_GP16C2T2EN_MSK); -} -/** - * @brief GP16C2T2EN clock disable during Sleep mode bit. - * @param rcu RCU Instance - * @retval None - */ -__STATIC_INLINE void md_rcu_disable_apb2sl_gp16c2t2en(RCU_TypeDef *rcu) -{ - CLEAR_BIT(rcu->APB2SL, RCU_APB2SL_GP16C2T2EN_MSK); -} -/** - * @brief Get GP16C2T2EN clock during Sleep mode bit. - * @param rcu RCU Instance - * @retval State of bit (1 or 0). - */ -__STATIC_INLINE uint32_t md_rcu_get_apb2sl_gp16c2t2en(RCU_TypeDef *rcu) -{ - return (READ_BIT(rcu->APB2SL, RCU_APB2SL_GP16C2T2EN_MSK)>>RCU_APB2SL_GP16C2T2EN_POS); -} -/** - * @brief GP16C2T1EN clock enable during Sleep mode bit. - * @param rcu RCU Instance - * @retval None - */ -__STATIC_INLINE void md_rcu_enable_apb2sl_gp16c2t1en(RCU_TypeDef *rcu) -{ - SET_BIT(rcu->APB2SL, RCU_APB2SL_GP16C2T1EN_MSK); -} -/** - * @brief GP16C2T1EN clock disable during Sleep mode bit. - * @param rcu RCU Instance - * @retval None - */ -__STATIC_INLINE void md_rcu_disable_apb2sl_gp16c2t1en(RCU_TypeDef *rcu) -{ - CLEAR_BIT(rcu->APB2SL, RCU_APB2SL_GP16C2T1EN_MSK); -} -/** - * @brief Get GP16C2T1EN clock during Sleep mode bit. - * @param rcu RCU Instance - * @retval State of bit (1 or 0). - */ -__STATIC_INLINE uint32_t md_rcu_get_apb2sl_gp16c2t1en(RCU_TypeDef *rcu) -{ - return (READ_BIT(rcu->APB2SL, RCU_APB2SL_GP16C2T1EN_MSK)>>RCU_APB2SL_GP16C2T1EN_POS); -} -/** - * @brief UART1EN clock enable during Sleep mode bit. - * @param rcu RCU Instance - * @retval None - */ -__STATIC_INLINE void md_rcu_enable_apb2sl_uart1en(RCU_TypeDef *rcu) -{ - SET_BIT(rcu->APB2SL, RCU_APB2SL_UART1EN_MSK); -} -/** - * @brief UART1EN clock disable during Sleep mode bit. - * @param rcu RCU Instance - * @retval None - */ -__STATIC_INLINE void md_rcu_disable_apb2sl_uart1en(RCU_TypeDef *rcu) -{ - CLEAR_BIT(rcu->APB2SL, RCU_APB2SL_UART1EN_MSK); -} -/** - * @brief Get UART1EN clock during Sleep mode bit. - * @param rcu RCU Instance - * @retval State of bit (1 or 0). - */ -__STATIC_INLINE uint32_t md_rcu_get_apb2sl_uart1en(RCU_TypeDef *rcu) -{ - return (READ_BIT(rcu->APB2SL, RCU_APB2SL_UART1EN_MSK)>>RCU_APB2SL_UART1EN_POS); -} -/** - * @brief SPI1EN clock enable during Sleep mode bit. - * @param rcu RCU Instance - * @retval None - */ -__STATIC_INLINE void md_rcu_enable_apb2sl_spi1en(RCU_TypeDef *rcu) -{ - SET_BIT(rcu->APB2SL, RCU_APB2SL_SPI1EN_MSK); -} -/** - * @brief SPI1EN clock disable during Sleep mode bit. - * @param rcu RCU Instance - * @retval None - */ -__STATIC_INLINE void md_rcu_disable_apb2sl_spi1en(RCU_TypeDef *rcu) -{ - CLEAR_BIT(rcu->APB2SL, RCU_APB2SL_SPI1EN_MSK); -} -/** - * @brief Get SPI1EN clock during Sleep mode bit. - * @param rcu RCU Instance - * @retval State of bit (1 or 0). - */ -__STATIC_INLINE uint32_t md_rcu_get_apb2sl_spi1en(RCU_TypeDef *rcu) -{ - return (READ_BIT(rcu->APB2SL, RCU_APB2SL_SPI1EN_MSK)>>RCU_APB2SL_SPI1EN_POS); -} -/** - * @brief AD16C4T1EN clock enable during Sleep mode bit. - * @param rcu RCU Instance - * @retval None - */ -__STATIC_INLINE void md_rcu_enable_apb2sl_ad16c4t1en(RCU_TypeDef *rcu) -{ - SET_BIT(rcu->APB2SL, RCU_APB2SL_AD16C4T1EN_MSK); -} -/** - * @brief AD16C4T1EN clock disable during Sleep mode bit. - * @param rcu RCU Instance - * @retval None - */ -__STATIC_INLINE void md_rcu_disable_apb2sl_ad16c4t1en(RCU_TypeDef *rcu) -{ - CLEAR_BIT(rcu->APB2SL, RCU_APB2SL_AD16C4T1EN_MSK); -} -/** - * @brief Get AD16C4T1EN clock during Sleep mode bit. - * @param rcu RCU Instance - * @retval State of bit (1 or 0). - */ -__STATIC_INLINE uint32_t md_rcu_get_apb2sl_ad16c4t1en(RCU_TypeDef *rcu) -{ - return (READ_BIT(rcu->APB2SL, RCU_APB2SL_AD16C4T1EN_MSK)>>RCU_APB2SL_AD16C4T1EN_POS); -} -/** - * @brief ADCEN clock enable during Sleep mode bit. - * @param rcu RCU Instance - * @retval None - */ -__STATIC_INLINE void md_rcu_enable_apb2sl_adcen(RCU_TypeDef *rcu) -{ - SET_BIT(rcu->APB2SL, RCU_APB2SL_ADCEN_MSK); -} -/** - * @brief ADCEN clock disable during Sleep mode bit. - * @param rcu RCU Instance - * @retval None - */ -__STATIC_INLINE void md_rcu_disable_apb2sl_adcen(RCU_TypeDef *rcu) -{ - CLEAR_BIT(rcu->APB2SL, RCU_APB2SL_ADCEN_MSK); -} -/** - * @brief Get ADCEN clock during Sleep mode bit. - * @param rcu RCU Instance - * @retval State of bit (1 or 0). - */ -__STATIC_INLINE uint32_t md_rcu_get_apb2sl_adcen(RCU_TypeDef *rcu) -{ - return (READ_BIT(rcu->APB2SL, RCU_APB2SL_ADCEN_MSK)>>RCU_APB2SL_ADCEN_POS); -} - -/** - * @brief GPIOD clock enable during Deep Sleep mode bit. - * @param rcu RCU Instance - * @retval None - */ -__STATIC_INLINE void md_rcu_enable_ahbdsl_gpden(RCU_TypeDef *rcu) -{ - SET_BIT(rcu->AHBDSL, RCU_AHBDSL_GPDEN_MSK); -} -/** - * @brief GPIOD clock disable during Deep Sleep mode bit. - * @param rcu RCU Instance - * @retval None - */ -__STATIC_INLINE void md_rcu_disable_ahbdsl_gpden(RCU_TypeDef *rcu) -{ - CLEAR_BIT(rcu->AHBDSL, RCU_AHBDSL_GPDEN_MSK); -} -/** - * @brief Get GPIOD clock during Deep Sleep mode bit. - * @param rcu RCU Instance - * @retval State of bit (1 or 0). - */ -__STATIC_INLINE uint32_t md_rcu_get_ahbdsl_gpden(RCU_TypeDef *rcu) -{ - return (READ_BIT(rcu->AHBDSL, RCU_AHBDSL_GPDEN_MSK)>>RCU_AHBDSL_GPDEN_POS); -} -/** - * @brief GPIOC clock enable during Deep Sleep mode bit. - * @param rcu RCU Instance - * @retval None - */ -__STATIC_INLINE void md_rcu_enable_ahbdsl_gpcen(RCU_TypeDef *rcu) -{ - SET_BIT(rcu->AHBDSL, RCU_AHBDSL_GPCEN_MSK); -} -/** - * @brief GPIOC clock disable during Deep Sleep mode bit. - * @param rcu RCU Instance - * @retval None - */ -__STATIC_INLINE void md_rcu_disable_ahbdsl_gpcen(RCU_TypeDef *rcu) -{ - CLEAR_BIT(rcu->AHBDSL, RCU_AHBDSL_GPCEN_MSK); -} -/** - * @brief Get GPIOC clock during Deep Sleep mode bit. - * @param rcu RCU Instance - * @retval State of bit (1 or 0). - */ -__STATIC_INLINE uint32_t md_rcu_get_ahbdsl_gpcen(RCU_TypeDef *rcu) -{ - return (READ_BIT(rcu->AHBDSL, RCU_AHBDSL_GPCEN_MSK)>>RCU_AHBDSL_GPCEN_POS); -} -/** - * @brief GPIOB clock enable during Deep Sleep mode bit. - * @param rcu RCU Instance - * @retval None - */ -__STATIC_INLINE void md_rcu_enable_ahbdsl_gpben(RCU_TypeDef *rcu) -{ - SET_BIT(rcu->AHBDSL, RCU_AHBDSL_GPBEN_MSK); -} -/** - * @brief GPIOB clock disable during Deep Sleep mode bit. - * @param rcu RCU Instance - * @retval None - */ -__STATIC_INLINE void md_rcu_disable_ahbdsl_gpben(RCU_TypeDef *rcu) -{ - CLEAR_BIT(rcu->AHBDSL, RCU_AHBDSL_GPBEN_MSK); -} -/** - * @brief Get GPIOB clock during Deep Sleep mode bit. - * @param rcu RCU Instance - * @retval State of bit (1 or 0). - */ -__STATIC_INLINE uint32_t md_rcu_get_ahbdsl_gpben(RCU_TypeDef *rcu) -{ - return (READ_BIT(rcu->AHBDSL, RCU_AHBDSL_GPBEN_MSK)>>RCU_AHBDSL_GPBEN_POS); -} -/** - * @brief GPIOA clock enable during Deep Sleep mode bit. - * @param rcu RCU Instance - * @retval None - */ -__STATIC_INLINE void md_rcu_enable_ahbdsl_gpaen(RCU_TypeDef *rcu) -{ - SET_BIT(rcu->AHBDSL, RCU_AHBDSL_GPAEN_MSK); -} -/** - * @brief GPIOA clock disable during Deep Sleep mode bit. - * @param rcu RCU Instance - * @retval None - */ -__STATIC_INLINE void md_rcu_disable_ahbdsl_gpaen(RCU_TypeDef *rcu) -{ - CLEAR_BIT(rcu->AHBDSL, RCU_AHBDSL_GPAEN_MSK); -} -/** - * @brief Get GPIOA clock during Deep Sleep mode bit. - * @param rcu RCU Instance - * @retval State of bit (1 or 0). - */ -__STATIC_INLINE uint32_t md_rcu_get_ahbdsl_gpaen(RCU_TypeDef *rcu) -{ - return (READ_BIT(rcu->AHBDSL, RCU_AHBDSL_GPAEN_MSK)>>RCU_AHBDSL_GPAEN_POS); -} -/** - * @brief HDIV clock enable during Deep Sleep mode bit. - * @param rcu RCU Instance - * @retval None - */ -__STATIC_INLINE void md_rcu_enable_ahbdsl_hdiven(RCU_TypeDef *rcu) -{ - SET_BIT(rcu->AHBDSL, RCU_AHBDSL_HDIVEN_MSK); -} -/** - * @brief HDIV clock disable during Deep Sleep mode bit. - * @param rcu RCU Instance - * @retval None - */ -__STATIC_INLINE void md_rcu_disable_ahbdsl_hdiven(RCU_TypeDef *rcu) -{ - CLEAR_BIT(rcu->AHBDSL, RCU_AHBDSL_HDIVEN_MSK); -} -/** - * @brief Get HDIV clock during Deep Sleep mode bit. - * @param rcu RCU Instance - * @retval State of bit (1 or 0). - */ -__STATIC_INLINE uint32_t md_rcu_get_ahbdsl_hdiven(RCU_TypeDef *rcu) -{ - return (READ_BIT(rcu->AHBDSL, RCU_AHBDSL_HDIVEN_MSK)>>RCU_AHBDSL_HDIVEN_POS); -} -/** - * @brief USB clock enable during Deep Sleep mode bit. - * @param rcu RCU Instance - * @retval None - */ -__STATIC_INLINE void md_rcu_enable_ahbdsl_usben(RCU_TypeDef *rcu) -{ - SET_BIT(rcu->AHBDSL, RCU_AHBDSL_USBEN_MSK); -} -/** - * @brief USB clock disable during Deep Sleep mode bit. - * @param rcu RCU Instance - * @retval None - */ -__STATIC_INLINE void md_rcu_disable_ahbdsl_usben(RCU_TypeDef *rcu) -{ - CLEAR_BIT(rcu->AHBDSL, RCU_AHBDSL_USBEN_MSK); -} -/** - * @brief Get USB clock during Deep Sleep mode bit. - * @param rcu RCU Instance - * @retval State of bit (1 or 0). - */ -__STATIC_INLINE uint32_t md_rcu_get_ahbdsl_usben(RCU_TypeDef *rcu) -{ - return (READ_BIT(rcu->AHBDSL, RCU_AHBDSL_USBEN_MSK)>>RCU_AHBDSL_USBEN_POS); -} -/** - * @brief AES clock enable during Deep Sleep mode bit. - * @param rcu RCU Instance - * @retval None - */ -__STATIC_INLINE void md_rcu_enable_ahbdsl_aesen(RCU_TypeDef *rcu) -{ - SET_BIT(rcu->AHBDSL, RCU_AHBDSL_AESEN_MSK); -} -/** - * @brief AES clock disable during Deep Sleep mode bit. - * @param rcu RCU Instance - * @retval None - */ -__STATIC_INLINE void md_rcu_disable_ahbdsl_aesen(RCU_TypeDef *rcu) -{ - CLEAR_BIT(rcu->AHBDSL, RCU_AHBDSL_AESEN_MSK); -} -/** - * @brief Get AES clock during Deep Sleep mode bit. - * @param rcu RCU Instance - * @retval State of bit (1 or 0). - */ -__STATIC_INLINE uint32_t md_rcu_get_ahbdsl_aesen(RCU_TypeDef *rcu) -{ - return (READ_BIT(rcu->AHBDSL, RCU_AHBDSL_AESEN_MSK)>>RCU_AHBDSL_AESEN_POS); -} -/** - * @brief CRC clock enable during Deep Sleep mode bit. - * @param rcu RCU Instance - * @retval None - */ -__STATIC_INLINE void md_rcu_enable_ahbdsl_crcen(RCU_TypeDef *rcu) -{ - SET_BIT(rcu->AHBDSL, RCU_AHBDSL_CRCEN_MSK); -} -/** - * @brief CRC clock disable during Deep Sleep mode bit. - * @param rcu RCU Instance - * @retval None - */ -__STATIC_INLINE void md_rcu_disable_ahbdsl_crcen(RCU_TypeDef *rcu) -{ - CLEAR_BIT(rcu->AHBDSL, RCU_AHBDSL_CRCEN_MSK); -} -/** - * @brief Get CRC clock during Deep Sleep mode bit. - * @param rcu RCU Instance - * @retval State of bit (1 or 0). - */ -__STATIC_INLINE uint32_t md_rcu_get_ahbdsl_crcen(RCU_TypeDef *rcu) -{ - return (READ_BIT(rcu->AHBDSL, RCU_AHBDSL_CRCEN_MSK)>>RCU_AHBDSL_CRCEN_POS); -} -/** - * @brief RTC clock enable during Deep Sleep mode bit. - * @param rcu RCU Instance - * @retval None - */ -__STATIC_INLINE void md_rcu_enable_ahbdsl_rtcen(RCU_TypeDef *rcu) -{ - SET_BIT(rcu->AHBDSL, RCU_AHBDSL_RTCEN_MSK); -} -/** - * @brief RTC clock disable during Deep Sleep mode bit. - * @param rcu RCU Instance - * @retval None - */ -__STATIC_INLINE void md_rcu_disable_ahbdsl_rtcen(RCU_TypeDef *rcu) -{ - CLEAR_BIT(rcu->AHBDSL, RCU_AHBDSL_RTCEN_MSK); -} -/** - * @brief Get RTC clock during Deep Sleep mode bit. - * @param rcu RCU Instance - * @retval State of bit (1 or 0). - */ -__STATIC_INLINE uint32_t md_rcu_get_ahbdsl_rtcen(RCU_TypeDef *rcu) -{ - return (READ_BIT(rcu->AHBDSL, RCU_AHBDSL_RTCEN_MSK)>>RCU_AHBDSL_RTCEN_POS); -} -/** - * @brief DMA1 clock enable during Deep Sleep mode bit. - * @param rcu RCU Instance - * @retval None - */ -__STATIC_INLINE void md_rcu_enable_ahbdsl_dma1en(RCU_TypeDef *rcu) -{ - SET_BIT(rcu->AHBDSL, RCU_AHBDSL_DMA1EN_MSK); -} -/** - * @brief DMA1 clock disable during Deep Sleep mode bit. - * @param rcu RCU Instance - * @retval None - */ -__STATIC_INLINE void md_rcu_disable_ahbdsl_dma1en(RCU_TypeDef *rcu) -{ - CLEAR_BIT(rcu->AHBDSL, RCU_AHBDSL_DMA1EN_MSK); -} -/** - * @brief Get DMA1 clock during Deep Sleep mode bit. - * @param rcu RCU Instance - * @retval State of bit (1 or 0). - */ -__STATIC_INLINE uint32_t md_rcu_get_ahbdsl_dma1en(RCU_TypeDef *rcu) -{ - return (READ_BIT(rcu->AHBDSL, RCU_AHBDSL_DMA1EN_MSK)>>RCU_AHBDSL_DMA1EN_POS); -} - -/** - * @brief DAC clock enable during Deep Sleep mode bit. - * @param rcu RCU Instance - * @retval None - */ -__STATIC_INLINE void md_rcu_enable_apb1dsl_dacen(RCU_TypeDef *rcu) -{ - SET_BIT(rcu->APB1DSL, RCU_APB1DSL_DACEN_MSK); -} -/** - * @brief DAC clock disable during Deep Sleep mode bit. - * @param rcu RCU Instance - * @retval None - */ -__STATIC_INLINE void md_rcu_disable_apb1dsl_dacen(RCU_TypeDef *rcu) -{ - CLEAR_BIT(rcu->APB1DSL, RCU_APB1DSL_DACEN_MSK); -} -/** - * @brief Get DAC clock during Deep Sleep mode bit. - * @param rcu RCU Instance - * @retval State of bit (1 or 0). - */ -__STATIC_INLINE uint32_t md_rcu_get_apb1dsl_dacen(RCU_TypeDef *rcu) -{ - return (READ_BIT(rcu->APB1DSL, RCU_APB1DSL_DACEN_MSK)>>RCU_APB1DSL_DACEN_POS); -} -/** - * @brief I2C2 clock enable during Deep Sleep mode bit. - * @param rcu RCU Instance - * @retval None - */ -__STATIC_INLINE void md_rcu_enable_apb1dsl_apb1dslen(RCU_TypeDef *rcu) -{ - SET_BIT(rcu->APB1DSL, RCU_APB1DSL_I2C2EN_MSK); -} -/** - * @brief I2C2 clock disable during Deep Sleep mode bit. - * @param rcu RCU Instance - * @retval None - */ -__STATIC_INLINE void md_rcu_disable_apb1dsl_apb1dslen(RCU_TypeDef *rcu) -{ - CLEAR_BIT(rcu->APB1DSL, RCU_APB1DSL_I2C2EN_MSK); -} -/** - * @brief Get I2C2 clock during Deep Sleep mode bit. - * @param rcu RCU Instance - * @retval State of bit (1 or 0). - */ -__STATIC_INLINE uint32_t md_rcu_get_apb1dsl_apb1dslen(RCU_TypeDef *rcu) -{ - return (READ_BIT(rcu->APB1DSL, RCU_APB1DSL_I2C2EN_MSK)>>RCU_APB1DSL_I2C2EN_POS); -} -/** - * @brief I2C1 clock enable during Deep Sleep mode bit. - * @param rcu RCU Instance - * @retval None - */ -__STATIC_INLINE void md_rcu_enable_apb1dsl_i2c1en(RCU_TypeDef *rcu) -{ - SET_BIT(rcu->APB1DSL, RCU_APB1DSL_I2C1EN_MSK); -} -/** - * @brief I2C1 clock disable during Deep Sleep mode bit. - * @param rcu RCU Instance - * @retval None - */ -__STATIC_INLINE void md_rcu_disable_apb1dsl_i2c1en(RCU_TypeDef *rcu) -{ - CLEAR_BIT(rcu->APB1DSL, RCU_APB1DSL_I2C1EN_MSK); -} -/** - * @brief Get I2C1 clock during Deep Sleep mode bit. - * @param rcu RCU Instance - * @retval State of bit (1 or 0). - */ -__STATIC_INLINE uint32_t md_rcu_get_apb1dsl_i2c1en(RCU_TypeDef *rcu) -{ - return (READ_BIT(rcu->APB1DSL, RCU_APB1DSL_I2C1EN_MSK)>>RCU_APB1DSL_I2C1EN_POS); -} -/** - * @brief SUART2 clock enable during Deep Sleep mode bit. - * @param rcu RCU Instance - * @retval None - */ -__STATIC_INLINE void md_rcu_enable_apb1dsl_suart2en(RCU_TypeDef *rcu) -{ - SET_BIT(rcu->APB1DSL, RCU_APB1DSL_SUART2EN_MSK); -} -/** - * @brief SUART2 clock disable during Deep Sleep mode bit. - * @param rcu RCU Instance - * @retval None - */ -__STATIC_INLINE void md_rcu_disable_apb1dsl_suart2en(RCU_TypeDef *rcu) -{ - CLEAR_BIT(rcu->APB1DSL, RCU_APB1DSL_SUART2EN_MSK); -} -/** - * @brief Get SUART2 clock during Deep Sleep mode bit. - * @param rcu RCU Instance - * @retval State of bit (1 or 0). - */ -__STATIC_INLINE uint32_t md_rcu_get_apb1dsl_suart2en(RCU_TypeDef *rcu) -{ - return (READ_BIT(rcu->APB1DSL, RCU_APB1DSL_SUART2EN_MSK)>>RCU_APB1DSL_SUART2EN_POS); -} -/** - * @brief SUART1 clock enable during Deep Sleep mode bit. - * @param rcu RCU Instance - * @retval None - */ -__STATIC_INLINE void md_rcu_enable_apb1dsl_suart1en(RCU_TypeDef *rcu) -{ - SET_BIT(rcu->APB1DSL, RCU_APB1DSL_SUART1EN_MSK); -} -/** - * @brief SUART1 clock disable during Deep Sleep mode bit. - * @param rcu RCU Instance - * @retval None - */ -__STATIC_INLINE void md_rcu_disable_apb1dsl_suart1en(RCU_TypeDef *rcu) -{ - CLEAR_BIT(rcu->APB1DSL, RCU_APB1DSL_SUART1EN_MSK); -} -/** - * @brief Get SUART1 clock during Deep Sleep mode bit. - * @param rcu RCU Instance - * @retval State of bit (1 or 0). - */ -__STATIC_INLINE uint32_t md_rcu_get_apb1dsl_suart1en(RCU_TypeDef *rcu) -{ - return (READ_BIT(rcu->APB1DSL, RCU_APB1DSL_SUART1EN_MSK)>>RCU_APB1DSL_SUART1EN_POS); -} -/** - * @brief UART3 clock enable during Deep Sleep mode bit. - * @param rcu RCU Instance - * @retval None - */ -__STATIC_INLINE void md_rcu_enable_apb1dsl_uart3en(RCU_TypeDef *rcu) -{ - SET_BIT(rcu->APB1DSL, RCU_APB1DSL_UART3EN_MSK); -} -/** - * @brief UART3 clock disable during Deep Sleep mode bit. - * @param rcu RCU Instance - * @retval None - */ -__STATIC_INLINE void md_rcu_disable_apb1dsl_uart3en(RCU_TypeDef *rcu) -{ - CLEAR_BIT(rcu->APB1DSL, RCU_APB1DSL_UART3EN_MSK); -} -/** - * @brief Get UART3 clock during Deep Sleep mode bit. - * @param rcu RCU Instance - * @retval State of bit (1 or 0). - */ -__STATIC_INLINE uint32_t md_rcu_get_apb1dsl_uart3en(RCU_TypeDef *rcu) -{ - return (READ_BIT(rcu->APB1DSL, RCU_APB1DSL_UART3EN_MSK)>>RCU_APB1DSL_UART3EN_POS); -} -/** - * @brief UART2 clock enable during Deep Sleep mode bit. - * @param rcu RCU Instance - * @retval None - */ -__STATIC_INLINE void md_rcu_enable_apb1dsl_uart2en(RCU_TypeDef *rcu) -{ - SET_BIT(rcu->APB1DSL, RCU_APB1DSL_UART2EN_MSK); -} -/** - * @brief UART2 clock disable during Deep Sleep mode bit. - * @param rcu RCU Instance - * @retval None - */ -__STATIC_INLINE void md_rcu_disable_apb1dsl_uart2en(RCU_TypeDef *rcu) -{ - CLEAR_BIT(rcu->APB1DSL, RCU_APB1DSL_UART2EN_MSK); -} -/** - * @brief Get UART2 clock during Deep Sleep mode bit. - * @param rcu RCU Instance - * @retval State of bit (1 or 0). - */ -__STATIC_INLINE uint32_t md_rcu_get_apb1dsl_uart2en(RCU_TypeDef *rcu) -{ - return (READ_BIT(rcu->APB1DSL, RCU_APB1DSL_UART2EN_MSK)>>RCU_APB1DSL_UART2EN_POS); -} -/** - * @brief SPI2 clock enable during Deep Sleep mode bit. - * @param rcu RCU Instance - * @retval None - */ -__STATIC_INLINE void md_rcu_enable_apb1dsl_spi2en(RCU_TypeDef *rcu) -{ - SET_BIT(rcu->APB1DSL, RCU_APB1DSL_SPI2EN_MSK); -} -/** - * @brief SPI2 clock disable during Deep Sleep mode bit. - * @param rcu RCU Instance - * @retval None - */ -__STATIC_INLINE void md_rcu_disable_apb1dsl_spi2en(RCU_TypeDef *rcu) -{ - CLEAR_BIT(rcu->APB1DSL, RCU_APB1DSL_SPI2EN_MSK); -} -/** - * @brief Get SPI2 clock during Deep Sleep mode bit. - * @param rcu RCU Instance - * @retval State of bit (1 or 0). - */ -__STATIC_INLINE uint32_t md_rcu_get_apb1dsl_spi2en(RCU_TypeDef *rcu) -{ - return (READ_BIT(rcu->APB1DSL, RCU_APB1DSL_SPI2EN_MSK)>>RCU_APB1DSL_SPI2EN_POS); -} -/** - * @brief IWDT clock enable during Deep Sleep mode bit. - * @param rcu RCU Instance - * @retval None - */ -__STATIC_INLINE void md_rcu_enable_apb1dsl_iwdten(RCU_TypeDef *rcu) -{ - SET_BIT(rcu->APB1DSL, RCU_APB1DSL_IWDTEN_MSK); -} -/** - * @brief IWDT clock disable during Deep Sleep mode bit. - * @param rcu RCU Instance - * @retval None - */ -__STATIC_INLINE void md_rcu_disable_apb1dsl_iwdten(RCU_TypeDef *rcu) -{ - CLEAR_BIT(rcu->APB1DSL, RCU_APB1DSL_IWDTEN_MSK); -} -/** - * @brief Get IWDT clock during Deep Sleep mode bit. - * @param rcu RCU Instance - * @retval State of bit (1 or 0). - */ -__STATIC_INLINE uint32_t md_rcu_get_apb1dsl_iwdten(RCU_TypeDef *rcu) -{ - return (READ_BIT(rcu->APB1DSL, RCU_APB1DSL_IWDTEN_MSK)>>RCU_APB1DSL_IWDTEN_POS); -} -/** - * @brief WWDT clock enable during Deep Sleep mode bit. - * @param rcu RCU Instance - * @retval None - */ -__STATIC_INLINE void md_rcu_enable_apb1dsl_wwdten(RCU_TypeDef *rcu) -{ - SET_BIT(rcu->APB1DSL, RCU_APB1DSL_WWDTEN_MSK); -} -/** - * @brief WWDT clock disable during Deep Sleep mode bit. - * @param rcu RCU Instance - * @retval None - */ -__STATIC_INLINE void md_rcu_disable_apb1dsl_wwdten(RCU_TypeDef *rcu) -{ - CLEAR_BIT(rcu->APB1DSL, RCU_APB1DSL_WWDTEN_MSK); -} -/** - * @brief Get WWDT clock during Deep Sleep mode bit. - * @param rcu RCU Instance - * @retval State of bit (1 or 0). - */ -__STATIC_INLINE uint32_t md_rcu_get_apb1dsl_wwdten(RCU_TypeDef *rcu) -{ - return (READ_BIT(rcu->APB1DSL, RCU_APB1DSL_WWDTEN_MSK)>>RCU_APB1DSL_WWDTEN_POS); -} -/** - * @brief BS16T1 clock enable during Deep Sleep mode bit. - * @param rcu RCU Instance - * @retval None - */ -__STATIC_INLINE void md_rcu_enable_apb1dsl_bs16t1en(RCU_TypeDef *rcu) -{ - SET_BIT(rcu->APB1DSL, RCU_APB1DSL_BS16T1EN_MSK); -} -/** - * @brief BS16T1 clock disable during Deep Sleep mode bit. - * @param rcu RCU Instance - * @retval None - */ -__STATIC_INLINE void md_rcu_disable_apb1dsl_bs16t1en(RCU_TypeDef *rcu) -{ - CLEAR_BIT(rcu->APB1DSL, RCU_APB1DSL_BS16T1EN_MSK); -} -/** - * @brief Get BS16T1 clock during Deep Sleep mode bit. - * @param rcu RCU Instance - * @retval State of bit (1 or 0). - */ -__STATIC_INLINE uint32_t md_rcu_get_apb1dsl_bs16t1en(RCU_TypeDef *rcu) -{ - return (READ_BIT(rcu->APB1DSL, RCU_APB1DSL_BS16T1EN_MSK)>>RCU_APB1DSL_BS16T1EN_POS); -} -/** - * @brief GP16C4T3 clock enable during Deep Sleep mode bit. - * @param rcu RCU Instance - * @retval None - */ -__STATIC_INLINE void md_rcu_enable_apb1dsl_gp16c4t3en(RCU_TypeDef *rcu) -{ - SET_BIT(rcu->APB1DSL, RCU_APB1DSL_GP16C4T3EN_MSK); -} -/** - * @brief GP16C4T3 clock disable during Deep Sleep mode bit. - * @param rcu RCU Instance - * @retval None - */ -__STATIC_INLINE void md_rcu_disable_apb1dsl_gp16c4t3en(RCU_TypeDef *rcu) -{ - CLEAR_BIT(rcu->APB1DSL, RCU_APB1DSL_GP16C4T3EN_MSK); -} -/** - * @brief Get GP16C4T3 clock during Deep Sleep mode bit. - * @param rcu RCU Instance - * @retval State of bit (1 or 0). - */ -__STATIC_INLINE uint32_t md_rcu_get_apb1dsl_gp16c4t3en(RCU_TypeDef *rcu) -{ - return (READ_BIT(rcu->APB1DSL, RCU_APB1DSL_GP16C4T3EN_MSK)>>RCU_APB1DSL_GP16C4T3EN_POS); -} -/** - * @brief GP16C4T2 clock enable during Deep Sleep mode bit. - * @param rcu RCU Instance - * @retval None - */ -__STATIC_INLINE void md_rcu_enable_apb1dsl_gp16c4t2en(RCU_TypeDef *rcu) -{ - SET_BIT(rcu->APB1DSL, RCU_APB1DSL_GP16C4T2EN_MSK); -} -/** - * @brief GP16C4T2 clock disable during Deep Sleep mode bit. - * @param rcu RCU Instance - * @retval None - */ -__STATIC_INLINE void md_rcu_disable_apb1dsl_gp16c4t2en(RCU_TypeDef *rcu) -{ - CLEAR_BIT(rcu->APB1DSL, RCU_APB1DSL_GP16C4T2EN_MSK); -} -/** - * @brief Get GP16C4T2 clock during Deep Sleep mode bit. - * @param rcu RCU Instance - * @retval State of bit (1 or 0). - */ -__STATIC_INLINE uint32_t md_rcu_get_apb1dsl_gp16c4t2en(RCU_TypeDef *rcu) -{ - return (READ_BIT(rcu->APB1DSL, RCU_APB1DSL_GP16C4T2EN_MSK)>>RCU_APB1DSL_GP16C4T2EN_POS); -} -/** - * @brief GP16C4T1 clock enable during Deep Sleep mode bit. - * @param rcu RCU Instance - * @retval None - */ -__STATIC_INLINE void md_rcu_enable_apb1dsl_gp16c4t1en(RCU_TypeDef *rcu) -{ - SET_BIT(rcu->APB1DSL, RCU_APB1DSL_GP16C4T1EN_MSK); -} -/** - * @brief GP16C4T1 clock disable during Deep Sleep mode bit. - * @param rcu RCU Instance - * @retval None - */ -__STATIC_INLINE void md_rcu_disable_apb1dsl_gp16c4t1en(RCU_TypeDef *rcu) -{ - CLEAR_BIT(rcu->APB1DSL, RCU_APB1DSL_GP16C4T1EN_MSK); -} -/** - * @brief Get GP16C4T1 clock during Deep Sleep mode bit. - * @param rcu RCU Instance - * @retval State of bit (1 or 0). - */ -__STATIC_INLINE uint32_t md_rcu_get_apb1dsl_gp16c4t1en(RCU_TypeDef *rcu) -{ - return (READ_BIT(rcu->APB1DSL, RCU_APB1DSL_GP16C4T1EN_MSK)>>RCU_APB1DSL_GP16C4T1EN_POS); -} -/** - * @brief GP32C4T1 clock enable during Deep Sleep mode bit. - * @param rcu RCU Instance - * @retval None - */ -__STATIC_INLINE void md_rcu_enable_apb1dsl_gp32c4t1en(RCU_TypeDef *rcu) -{ - SET_BIT(rcu->APB1DSL, RCU_APB1DSL_GP32C4T1EN_MSK); -} -/** - * @brief GP32C4T1 clock disable during Deep Sleep mode bit. - * @param rcu RCU Instance - * @retval None - */ -__STATIC_INLINE void md_rcu_disable_apb1dsl_gp32c4t1en(RCU_TypeDef *rcu) -{ - CLEAR_BIT(rcu->APB1DSL, RCU_APB1DSL_GP32C4T1EN_MSK); -} -/** - * @brief Get GP32C4T1 clock during Deep Sleep mode bit. - * @param rcu RCU Instance - * @retval State of bit (1 or 0). - */ -__STATIC_INLINE uint32_t md_rcu_get_apb1dsl_gp32c4t1en(RCU_TypeDef *rcu) -{ - return (READ_BIT(rcu->APB1DSL, RCU_APB1DSL_GP32C4T1EN_MSK)>>RCU_APB1DSL_GP32C4T1EN_POS); -} - -/** - * @brief CMP clock enable during Deep Sleep mode bit. - * @param rcu RCU Instance - * @retval None - */ -__STATIC_INLINE void md_rcu_enable_apb2dsl_cmpen(RCU_TypeDef *rcu) -{ - SET_BIT(rcu->APB2DSL, RCU_APB2DSL_CMPEN_MSK); -} -/** - * @brief CMP clock disable during Deep Sleep mode bit. - * @param rcu RCU Instance - * @retval None - */ -__STATIC_INLINE void md_rcu_disable_apb2dsl_cmpen(RCU_TypeDef *rcu) -{ - CLEAR_BIT(rcu->APB2DSL, RCU_APB2DSL_CMPEN_MSK); -} -/** - * @brief Get CMP clock during Deep Sleep mode bit. - * @param rcu RCU Instance - * @retval State of bit (1 or 0). - */ -__STATIC_INLINE uint32_t md_rcu_get_apb2dsl_cmpen(RCU_TypeDef *rcu) -{ - return (READ_BIT(rcu->APB2DSL, RCU_APB2DSL_CMPEN_MSK)>>RCU_APB2DSL_CMPEN_POS); -} -/** - * @brief GP16C2T4 clock enable during Deep Sleep mode bit. - * @param rcu RCU Instance - * @retval None - */ -__STATIC_INLINE void md_rcu_enable_apb2dsl_gp16c2t4en(RCU_TypeDef *rcu) -{ - SET_BIT(rcu->APB2DSL, RCU_APB2DSL_GP16C2T4EN_MSK); -} -/** - * @brief GP16C2T4 clock disable during Deep Sleep mode bit. - * @param rcu RCU Instance - * @retval None - */ -__STATIC_INLINE void md_rcu_disable_apb2dsl_gp16c2t4en(RCU_TypeDef *rcu) -{ - CLEAR_BIT(rcu->APB2DSL, RCU_APB2DSL_GP16C2T4EN_MSK); -} -/** - * @brief Get GP16C2T4 clock during Deep Sleep mode bit. - * @param rcu RCU Instance - * @retval State of bit (1 or 0). - */ -__STATIC_INLINE uint32_t md_rcu_get_apb2dsl_gp16c2t4en(RCU_TypeDef *rcu) -{ - return (READ_BIT(rcu->APB2DSL, RCU_APB2DSL_GP16C2T4EN_MSK)>>RCU_APB2DSL_GP16C2T4EN_POS); -} -/** - * @brief GP16C2T3 clock enable during Deep Sleep mode bit. - * @param rcu RCU Instance - * @retval None - */ -__STATIC_INLINE void md_rcu_enable_apb2dsl_gp16c2t3en(RCU_TypeDef *rcu) -{ - SET_BIT(rcu->APB2DSL, RCU_APB2DSL_GP16C2T3EN_MSK); -} -/** - * @brief GP16C2T3 clock disable during Deep Sleep mode bit. - * @param rcu RCU Instance - * @retval None - */ -__STATIC_INLINE void md_rcu_disable_apb2dsl_gp16c2t3en(RCU_TypeDef *rcu) -{ - CLEAR_BIT(rcu->APB2DSL, RCU_APB2DSL_GP16C2T3EN_MSK); -} -/** - * @brief Get GP16C2T3 clock during Deep Sleep mode bit. - * @param rcu RCU Instance - * @retval State of bit (1 or 0). - */ -__STATIC_INLINE uint32_t md_rcu_get_apb2dsl_gp16c2t3en(RCU_TypeDef *rcu) -{ - return (READ_BIT(rcu->APB2DSL, RCU_APB2DSL_GP16C2T3EN_MSK)>>RCU_APB2DSL_GP16C2T3EN_POS); -} -/** - * @brief GP16C2T2 clock enable during Deep Sleep mode bit. - * @param rcu RCU Instance - * @retval None - */ -__STATIC_INLINE void md_rcu_enable_apb2dsl_gp16c2t2en(RCU_TypeDef *rcu) -{ - SET_BIT(rcu->APB2DSL, RCU_APB2DSL_GP16C2T2EN_MSK); -} -/** - * @brief GP16C2T2 clock disable during Deep Sleep mode bit. - * @param rcu RCU Instance - * @retval None - */ -__STATIC_INLINE void md_rcu_disable_apb2dsl_gp16c2t2en(RCU_TypeDef *rcu) -{ - CLEAR_BIT(rcu->APB2DSL, RCU_APB2DSL_GP16C2T2EN_MSK); -} -/** - * @brief Get GP16C2T2 clock during Deep Sleep mode bit. - * @param rcu RCU Instance - * @retval State of bit (1 or 0). - */ -__STATIC_INLINE uint32_t md_rcu_get_apb2dsl_gp16c2t2en(RCU_TypeDef *rcu) -{ - return (READ_BIT(rcu->APB2DSL, RCU_APB2DSL_GP16C2T2EN_MSK)>>RCU_APB2DSL_GP16C2T2EN_POS); -} -/** - * @brief GP16C2T1 clock enable during Deep Sleep mode bit. - * @param rcu RCU Instance - * @retval None - */ -__STATIC_INLINE void md_rcu_enable_apb2dsl_gp16c2t1en(RCU_TypeDef *rcu) -{ - SET_BIT(rcu->APB2DSL, RCU_APB2DSL_GP16C2T1EN_MSK); -} -/** - * @brief GP16C2T1 clock disable during Deep Sleep mode bit. - * @param rcu RCU Instance - * @retval None - */ -__STATIC_INLINE void md_rcu_disable_apb2dsl_gp16c2t1en(RCU_TypeDef *rcu) -{ - CLEAR_BIT(rcu->APB2DSL, RCU_APB2DSL_GP16C2T1EN_MSK); -} -/** - * @brief Get GP16C2T1 clock during Deep Sleep mode bit. - * @param rcu RCU Instance - * @retval State of bit (1 or 0). - */ -__STATIC_INLINE uint32_t md_rcu_get_apb2dsl_gp16c2t1en(RCU_TypeDef *rcu) -{ - return (READ_BIT(rcu->APB2DSL, RCU_APB2DSL_GP16C2T1EN_MSK)>>RCU_APB2DSL_GP16C2T1EN_POS); -} -/** - * @brief UART1 clock enable during Deep Sleep mode bit. - * @param rcu RCU Instance - * @retval None - */ -__STATIC_INLINE void md_rcu_enable_apb2dsl_uart1en(RCU_TypeDef *rcu) -{ - SET_BIT(rcu->APB2DSL, RCU_APB2DSL_UART1EN_MSK); -} -/** - * @brief UART1 clock disable during Deep Sleep mode bit. - * @param rcu RCU Instance - * @retval None - */ -__STATIC_INLINE void md_rcu_disable_apb2dsl_uart1en(RCU_TypeDef *rcu) -{ - CLEAR_BIT(rcu->APB2DSL, RCU_APB2DSL_UART1EN_MSK); -} -/** - * @brief Get UART1 clock during Deep Sleep mode bit. - * @param rcu RCU Instance - * @retval State of bit (1 or 0). - */ -__STATIC_INLINE uint32_t md_rcu_get_apb2dsl_uart1en(RCU_TypeDef *rcu) -{ - return (READ_BIT(rcu->APB2DSL, RCU_APB2DSL_UART1EN_MSK)>>RCU_APB2DSL_UART1EN_POS); -} -/** - * @brief SPI1 clock enable during Deep Sleep mode bit. - * @param rcu RCU Instance - * @retval None - */ -__STATIC_INLINE void md_rcu_enable_apb2dsl_spi1en(RCU_TypeDef *rcu) -{ - SET_BIT(rcu->APB2DSL, RCU_APB2DSL_SPI1EN_MSK); -} -/** - * @brief SPI1 clock disable during Deep Sleep mode bit. - * @param rcu RCU Instance - * @retval None - */ -__STATIC_INLINE void md_rcu_disable_apb2dsl_spi1en(RCU_TypeDef *rcu) -{ - CLEAR_BIT(rcu->APB2DSL, RCU_APB2DSL_SPI1EN_MSK); -} -/** - * @brief Get SPI1 clock during Deep Sleep mode bit. - * @param rcu RCU Instance - * @retval State of bit (1 or 0). - */ -__STATIC_INLINE uint32_t md_rcu_get_apb2dsl_spi1en(RCU_TypeDef *rcu) -{ - return (READ_BIT(rcu->APB2DSL, RCU_APB2DSL_SPI1EN_MSK)>>RCU_APB2DSL_SPI1EN_POS); -} -/** - * @brief AD16C4T1 clock enable during Deep Sleep mode bit. - * @param rcu RCU Instance - * @retval None - */ -__STATIC_INLINE void md_rcu_enable_apb2dsl_ad16c4t1en(RCU_TypeDef *rcu) -{ - SET_BIT(rcu->APB2DSL, RCU_APB2DSL_AD16C4T1EN_MSK); -} -/** - * @brief AD16C4T1 clock disable during Deep Sleep mode bit. - * @param rcu RCU Instance - * @retval None - */ -__STATIC_INLINE void md_rcu_disable_apb2dsl_ad16c4t1en(RCU_TypeDef *rcu) -{ - CLEAR_BIT(rcu->APB2DSL, RCU_APB2DSL_AD16C4T1EN_MSK); -} -/** - * @brief Get AD16C4T1 clock during Deep Sleep mode bit. - * @param rcu RCU Instance - * @retval State of bit (1 or 0). - */ -__STATIC_INLINE uint32_t md_rcu_get_apb2dsl_ad16c4t1en(RCU_TypeDef *rcu) -{ - return (READ_BIT(rcu->APB2DSL, RCU_APB2DSL_AD16C4T1EN_MSK)>>RCU_APB2DSL_AD16C4T1EN_POS); -} -/** - * @brief ADC clock enable during Deep Sleep mode bit. - * @param rcu RCU Instance - * @retval None - */ -__STATIC_INLINE void md_rcu_enable_apb2dsl_adcen(RCU_TypeDef *rcu) -{ - SET_BIT(rcu->APB2DSL, RCU_APB2DSL_ADCEN_MSK); -} -/** - * @brief ADC clock disable during Deep Sleep mode bit. - * @param rcu RCU Instance - * @retval None - */ -__STATIC_INLINE void md_rcu_disable_apb2dsl_adcen(RCU_TypeDef *rcu) -{ - CLEAR_BIT(rcu->APB2DSL, RCU_APB2DSL_ADCEN_MSK); -} -/** - * @brief Get ADC clock during Deep Sleep mode bit. - * @param rcu RCU Instance - * @retval State of bit (1 or 0). - */ -__STATIC_INLINE uint32_t md_rcu_get_apb2dsl_adcen(RCU_TypeDef *rcu) -{ - return (READ_BIT(rcu->APB2DSL, RCU_APB2DSL_ADCEN_MSK)>>RCU_APB2DSL_ADCEN_POS); -} - -/** - * @} MD_RCU_Public_Macros - */ - -/* Public functions -----------------------------------------------------------*/ -/** @defgroup MD_RCU_Public_Functions RCU Public Functions - * @{ - */ - -/** @defgroup MD_RCU_PF_Basic_Configuration Basic Configuration - * @{ - */ -void md_rcu_init(void); -void md_rcu_init_set(RCU_TypeDef *, md_rcu_init_typedef *); -void md_rcu_pllreinit(uint8_t); -/** - * @} MD_RCU_PF_Basic_Configuration - */ - -/** - * @} MD_RCU_Public_Functions - */ - -#endif - -/** - * @} RCU - */ - -/** - * @} Micro_Driver - */ -#ifdef __cplusplus -} - -#endif - -#endif - -/******************* (C) COPYRIGHT Eastsoft Microelectronics *****END OF FILE****/ diff --git a/bsp/essemi/es32f0271/libraries/ES32F027x_MD_StdPeriph_Driver/Include/md_rtc.h b/bsp/essemi/es32f0271/libraries/ES32F027x_MD_StdPeriph_Driver/Include/md_rtc.h deleted file mode 100644 index 4de23ae628..0000000000 --- a/bsp/essemi/es32f0271/libraries/ES32F027x_MD_StdPeriph_Driver/Include/md_rtc.h +++ /dev/null @@ -1,2785 +0,0 @@ -/** - ****************************************************************************** - * @file md_RTC.h - * @brief ES32F0271 RTC HEAD File. - * - * @version V1.00.02 - * @date 30/11/2018 - * @author Eastsoft AE Team - * @note - * detailed description - * - * Copyright (C) 2018 Shanghai Eastsoft Microelectronics Co., Ltd. ALL rights reserved. - ******************************************************************************* - */ - -/* Define to prevent recursive inclusion -------------------------------------*/ -#ifndef __MD_RTC_H__ -#define __MD_RTC_H__ - -#ifdef __cplusplus -extern "C" { -#endif - -/* Includes -------------------------------------------------------------------*/ -#include -#include "es32f0271.h" -#include "reg_rtc.h" - -/** @addtogroup Micro_Driver - * @{ - */ - -#if defined (RTC) - -/** @defgroup RTC RTC - * @brief RTC micro driver - * @{ - */ - -/* Private types --------------------------------------------------------------*/ -/* Private variables ----------------------------------------------------------*/ -/* Private constants ----------------------------------------------------------*/ -/* Private macros -------------------------------------------------------------*/ - -/* Public types ---------------------------------------------------------------*/ -/** @defgroup MD_RTC_PT_INIT RTC Public Init structures - * @{ - */ - -/** - * @brief MD RTC Init Structure definition - */ - - -/** - * @} MD_RTC_PT_INIT - */ - -/* Public constants -----------------------------------------------------------*/ -/** @defgroup MD_RTC_Public_Constants RTC Public Constants - * @{ - */ - -/** @defgroup MD_RTC_CON_MODE_ RTC Clock Calibration Mode - * @{ - */ -#define MD_RTC_CON_MODE_INCR (0x00000000UL) /** @brief Increase calibration value when match calibration cycle. */ -#define MD_RTC_CON_MODE_DECR (0X00000001UL) /** @brief DMA Decrease calibration value when match calibration cycle. */ -/** - * @} MD_RTC_CON_MODE_ - */ - -/** @defgroup MD_RTC_CON_CYCLE_ RTC Calibration Cycle Select - * @{ - */ -#define MD_RTC_CON_CYCLE_60S (0x00000000UL) /** @brief When enable Calibration Function, the calibrate cycle is 60s. */ -#define MD_RTC_CON_CYCLE_1S (0X00000001UL) /** @brief When enable Calibration Function, the calibrate cycle is 1s. */ -/** - * @} MD_RTC_CON_CYCLE_ - */ - -/** @defgroup MD_RTC_CON_CKSEL_ RTC Clock Source Selection - * @{ - */ -#define MD_RTC_CON_CKSEL_NO (0x00000000UL) /** @brief No clock */ -#define MD_RTC_CON_CKSEL_LOSC (0X00000001UL) /** @brief LOSC oscillator clock used as RTC clock */ -#define MD_RTC_CON_CKSEL_LRC (0x00000002UL) /** @brief LRC oscillator clock used as RTC clock */ -#define MD_RTC_CON_CKSEL_PLL (0X00000003UL) /** @brief PLL Reference clock source divided by 128 used as RTC clock */ -/** - * @} MD_RTC_CON_CKSEL_ - */ - -/** @defgroup MD_RTC_WKUP_WKSCAL RTC Wakeup Counter Scale Value - * @{ - */ -#define MD_RTC_WKUP_WKSCAL_DIV1 (0x00000000UL) /** @brief Divide 1, wakeup counter will count each second. */ -#define MD_RTC_WKUP_WKSCAL_DIV2 (0X00000001UL) /** @brief Divide 2, wakeup counter will count each 1/2 second. */ -#define MD_RTC_WKUP_WKSCAL_DIV4 (0x00000002UL) /** @brief Divide 4, wakeup counter will count each 1/4 second. */ -#define MD_RTC_WKUP_WKSCAL_DIV8 (0X00000003UL) /** @brief Divide 8, wakeup counter will count each 1/8 second. */ -#define MD_RTC_WKUP_WKSCAL_DIV16 (0X00000004UL) /** @brief Divide 16, wakeup counter will count each 1/16 second. */ -/** - * @} MD_RTC_WKUP_WKSCAL - */ - -/** @defgroup MD_RTC_WKUP_WKSEL RTC Wakeup Counter Events Select - * @{ - */ -#define MD_RTC_WKUP_WKSEL_OFF (0x00000000UL) /** @brief OFF */ -#define MD_RTC_WKUP_WKSEL_RTC (0X00000001UL) /** @brief Start counter when RTC start. */ -#define MD_RTC_WKUP_WKSEL_SLEEP (0x00000002UL) /** @brief Start counter when receive sleep flag. */ -/** - * @} MD_RTC_WKUP_WKSEL - */ - -/** @defgroup MD_RTC_STAT_SYNDONE RTC Calendar Synchronization status - * @{ - */ -#define MD_RTC_STAT_SYNDONE_UNDER (0x00000000UL) /** @brief RTC is under Synchronization procedure */ -#define MD_RTC_STAT_SYNDONE_CMP (0X00000001UL) /** @brief RTC Synchronization procedure is Completed */ -/** - * @} MD_RTC_STAT_SYNDONE - */ - -/** @defgroup MD_RTC_BKEN_BKEN Read RTC Backup Register Enable - * @{ - */ -#define MD_RTC_BKEN_BKEN_CONTROL (0x00000000UL) /** @brief Read RTCTIME & RTCCAL From control register. */ -#define MD_RTC_BKEN_BKEN_BACKUP (0X00000001UL) /** @brief Read RTCTIME & RTCCAL From backup register. */ -/** - * @} MD_RTC_BKEN_BKEN - */ - -/** - * @} MD_RTC_Public_Constants - */ - -/* Public macro ---------------------------------------------------------------*/ -/** @defgroup MD_RTC_Public_Macros RTC Public Macros - * @{ - */ - -/** - * @brief Set RTC Clock Calibration Mode - * @param rtc RTC Instance - * @param mode can be one of the following values: - * @arg @ref MD_RTC_CON_MODE_INCR - * @arg @ref MD_RTC_CON_MODE_DECR - * @retval None - */ -__STATIC_INLINE void md_rtc_set_con_mode(RTC_TypeDef *rtc, uint32_t mode) -{ - MODIFY_REG(rtc->CON, RTC_CON_MODE_MSK, (mode<CON, RTC_CON_MODE_MSK)>>RTC_CON_MODE_POS); -} -/** - * @brief Set RTC Clock Calibration Value - * @param rtc RTC Instance - * @param calval Max calibration value is CALV. - * @retval None - */ -__STATIC_INLINE void md_rtc_set_con_calval(RTC_TypeDef *rtc, uint32_t calval) -{ - MODIFY_REG(rtc->CON, RTC_CON_CALVAL_MSK, (calval<CON, RTC_CON_CALVAL_MSK)>>RTC_CON_CALVAL_POSS); -} -/** - * @brief Set RTC Clock Counter Scale - * @param rtc RTC Instance - * @param scale Max divider of This counter is (SCALE+1). - * @retval None - */ -__STATIC_INLINE void md_rtc_set_con_scale(RTC_TypeDef *rtc, uint32_t scale) -{ - MODIFY_REG(rtc->CON, RTC_CON_SCALE_MSK, (scale<CON, RTC_CON_SCALE_MSK)>>RTC_CON_SCALE_POSS); -} -/** - * @brief Set RTC Clock Counter Prescale - * @param rtc RTC Instance - * @param pscale Max divider of This counter is (PSCALE+1). - * @retval None - */ -__STATIC_INLINE void md_rtc_set_con_pscale(RTC_TypeDef *rtc, uint32_t pscale) -{ - MODIFY_REG(rtc->CON, RTC_CON_PSCALE_MSK, (pscale<CON, RTC_CON_PSCALE_MSK)>>RTC_CON_PSCALE_POSS); -} -/** - * @brief Set RTC Calibration Cycle Select - * @param rtc RTC Instance - * @param cycle This parameter can be one of the following values: - * @arg @ref MD_RTC_CON_CYCLE_60S - * @arg @ref MD_RTC_CON_CYCLE_1S - * @retval None - */ -__STATIC_INLINE void md_rtc_set_con_cycle(RTC_TypeDef *rtc, uint32_t cycle) -{ - MODIFY_REG(rtc->CON, RTC_CON_CYCLE_MSK, (cycle<CON, RTC_CON_CYCLE_MSK)>>RTC_CON_CYCLE_POS); -} -/** - * @brief Set RTC Calibration Function Enable - * @param rtc RTC Instance - * @param calib This parameter can be one of the following values: - * @arg DISABLE - * @arg ENABLE - * @retval None - */ -__STATIC_INLINE void md_rtc_set_con_calib(RTC_TypeDef *rtc, uint32_t calib) -{ - MODIFY_REG(rtc->CON, RTC_CON_CALIB_MSK, (calib<CON, RTC_CON_CALIB_MSK)>>RTC_CON_CALIB_POS); -} -/** - * @brief Set RTC Clock Source Selection - * @param rtc RTC Instance - * @param cksel This parameter can be one of the following values: - * @arg @ref MD_RTC_CON_CKSEL_NO - * @arg @ref MD_RTC_CON_CKSEL_LOSC - * @arg @ref MD_RTC_CON_CKSEL_LRC - * @arg @ref MD_RTC_CON_CKSEL_PLL - * @retval None - */ -__STATIC_INLINE void md_rtc_set_con_cksel(RTC_TypeDef *rtc, uint32_t cksel) -{ - MODIFY_REG(rtc->CON, RTC_CON_CKSEL_MSK, (cksel<CON, RTC_CON_CKSEL_MSK)>>RTC_CON_CKSEL_POSS); -} -/** - * @brief Set RTC Counter Enable bit - * @param rtc RTC Instance - * @param rtcen This parameter can be one of the following values: - * @arg DISABLE - * @arg ENABLE - * @retval None - */ -__STATIC_INLINE void md_rtc_set_con_rtcen(RTC_TypeDef *rtc, uint32_t rtcen) -{ - MODIFY_REG(rtc->CON, RTC_CON_RTCEN_MSK, (rtcen<CON, RTC_CON_RTCEN_MSK)>>RTC_CON_RTCEN_POS); -} - -/** @defgroup MD_RTC_CON_MODE MODE - * @brief Set RTC Clock Calibration Mode bit for md_rtc_set_con() function used - * @param mode This parameter can be one of the following values: - * @arg @ref MD_RTC_CON_MODE_INCR - * @arg @ref MD_RTC_CON_MODE_DECR - * @{ - */ -#define md_rtc_set_con_mode_fun(mode) (mode<CON, (mode|calval|scale|pscale|cycle|calib|cksel|rtcen)); -} - - -/** - * @brief Set RTC Wakeup Counter Scale Value - * @param rtc RTC Instance - * @param wkscal This parameter can be one of the following values: - * @arg @ref MD_RTC_WKUP_WKSCAL_DIV1 - * @arg @ref MD_RTC_WKUP_WKSCAL_DIV2 - * @arg @ref MD_RTC_WKUP_WKSCAL_DIV4 - * @arg @ref MD_RTC_WKUP_WKSCAL_DIV8 - * @arg @ref MD_RTC_WKUP_WKSCAL_DIV16 - * @retval None - */ -__STATIC_INLINE void md_rtc_set_wkup_wkscal(RTC_TypeDef *rtc, uint32_t wkscal) -{ - MODIFY_REG(rtc->WKUP, RTC_WKUP_WKSCAL_MSK, (wkscal<WKUP, RTC_WKUP_WKSCAL_MSK)>>RTC_WKUP_WKSCAL_POSS); -} -/** - * @brief Set RTC Wakeup Counter Events Select - * @param rtc RTC Instance - * @param wksel This parameter can be one of the following values: - * @arg @ref MD_RTC_WKUP_WKSEL_OFF - * @arg @ref MD_RTC_WKUP_WKSEL_RTC - * @arg @ref MD_RTC_WKUP_WKSEL_SLEEP - * @retval None - */ -__STATIC_INLINE void md_rtc_set_wkup_wksel(RTC_TypeDef *rtc, uint32_t wksel) -{ - MODIFY_REG(rtc->WKUP, RTC_WKUP_WKSEL_MSK, (wksel<WKUP, RTC_WKUP_WKSEL_MSK)>>RTC_WKUP_WKSEL_POSS); -} -/** - * @brief Set RTC Wakeup Counter setting value - * @param rtc RTC Instance - * @param wkcal Max value is WKCAL seconds - * @retval None - */ -__STATIC_INLINE void md_rtc_set_wkup_wkcal(RTC_TypeDef *rtc, uint32_t wkcal) -{ - MODIFY_REG(rtc->WKUP, RTC_WKUP_WKCAL_MSK, (wkcal<WKUP, RTC_WKUP_WKCAL_MSK)>>RTC_WKUP_WKCAL_POSS); -} - - -/** - * @brief Set Week Value - * @param rtc RTC Instance - * @param week value in RTC timer, in BCD format. - * @retval None - */ -__STATIC_INLINE void md_rtc_set_time_week(RTC_TypeDef *rtc, uint32_t week) -{ - MODIFY_REG(rtc->TIME, RTC_TIME_WEEK_MSK, (week<TIME, RTC_TIME_WEEK_MSK)>>RTC_TIME_WEEK_POSS); -} -/** - * @brief Set Hour Tens Value - * @param rtc RTC Instance - * @param hour_t Hour tens value in RTC timer, in BCD format. - * @retval None - */ -__STATIC_INLINE void md_rtc_set_time_hour_t(RTC_TypeDef *rtc, uint32_t hour_t) -{ - MODIFY_REG(rtc->TIME, RTC_TIME_HOUR_T_MSK, (hour_t<TIME, RTC_TIME_HOUR_T_MSK)>>RTC_TIME_HOUR_T_POSS); -} -/** - * @brief Set Hour Units Value - * @param rtc RTC Instance - * @param hour_u Hour units value in RTC timer, in BCD format. - * @retval None - */ -__STATIC_INLINE void md_rtc_set_time_hour_u(RTC_TypeDef *rtc, uint32_t hour_u) -{ - MODIFY_REG(rtc->TIME, RTC_TIME_HOUR_U_MSK, (hour_u<TIME, RTC_TIME_HOUR_U_MSK)>>RTC_TIME_HOUR_U_POSS); -} -/** - * @brief Set Minute Tens Value - * @param rtc RTC Instance - * @param min_t Minute tens value in RTC timer, in BCD format. - * @retval None - */ -__STATIC_INLINE void md_rtc_set_time_min_t(RTC_TypeDef *rtc, uint32_t min_t) -{ - MODIFY_REG(rtc->TIME, RTC_TIME_MIN_T_MSK, (min_t<TIME, RTC_TIME_MIN_T_MSK)>>RTC_TIME_MIN_T_POSS); -} -/** - * @brief Set Minute Units Value - * @param rtc RTC Instance - * @param min_u Minute units value in RTC timer, in BCD format. - * @retval None - */ -__STATIC_INLINE void md_rtc_set_time_min_u(RTC_TypeDef *rtc, uint32_t min_u) -{ - MODIFY_REG(rtc->TIME, RTC_TIME_MIN_U_MSK, (min_u<TIME, RTC_TIME_MIN_U_MSK)>>RTC_TIME_MIN_U_POSS); -} -/** - * @brief Set Second Tens Value - * @param rtc RTC Instance - * @param sec_t Second tens value in RTC timer, in BCD format. - * @retval None - */ -__STATIC_INLINE void md_rtc_set_time_sec_t(RTC_TypeDef *rtc, uint32_t sec_t) -{ - MODIFY_REG(rtc->TIME, RTC_TIME_SEC_T_MSK, (sec_t<TIME, RTC_TIME_SEC_T_MSK)>>RTC_TIME_SEC_T_POSS); -} -/** - * @brief Set Second Units Value - * @param rtc RTC Instance - * @param sec_u Second units value in RTC timer, in BCD format. - * @retval None - */ -__STATIC_INLINE void md_rtc_set_time_sec_u(RTC_TypeDef *rtc, uint32_t sec_u) -{ - MODIFY_REG(rtc->TIME, RTC_TIME_SEC_U_MSK, (sec_u<TIME, RTC_TIME_SEC_U_MSK)>>RTC_TIME_SEC_U_POSS); -} - -/** @defgroup MD_RTC_TIME_WEEK WEEK - * @brief Set Week Value bit bit for md_rtc_set_time() function used - * @param week value in RTC timer, in BCD format. - * @{ - */ -#define md_rtc_set_time_week_fun(week) (week<TIME, (week|hour_t|hour_u|min_t|min_u|sec_t|sec_u)); -} - - - - - - - - - - -/** - * @brief Set Year Tens Value - * @param rtc RTC Instance - * @param year_t Year tens value in RTC timer, in BCD format. - * @retval None - */ -__STATIC_INLINE void md_rtc_set_cal_year_t(RTC_TypeDef *rtc, uint32_t year_t) -{ - MODIFY_REG(rtc->CAL, RTC_CAL_YEAR_T_MSK, (year_t<CAL, RTC_CAL_YEAR_T_MSK)>>RTC_CAL_YEAR_T_POSS); -} -/** - * @brief Set Year Units Value - * @param rtc RTC Instance - * @param year_u Year units value in RTC timer, in BCD format. - * @retval None - */ -__STATIC_INLINE void md_rtc_set_cal_year_u(RTC_TypeDef *rtc, uint32_t year_u) -{ - MODIFY_REG(rtc->CAL, RTC_CAL_YEAR_U_MSK, (year_u<CAL, RTC_CAL_YEAR_U_MSK)>>RTC_CAL_YEAR_U_POSS); -} -/** - * @brief Set Month Tens Value - * @param rtc RTC Instance - * @param mon_t Month tens value in RTC timer, in BCD format. - * @retval None - */ -__STATIC_INLINE void md_rtc_set_cal_mon_t(RTC_TypeDef *rtc, uint32_t mon_t) -{ - MODIFY_REG(rtc->CAL, RTC_CAL_MON_T_MSK, (mon_t<CAL, RTC_CAL_MON_T_MSK)>>RTC_CAL_MON_T_POS); -} -/** - * @brief Set Month Units Value - * @param rtc RTC Instance - * @param mon_u Month units value in RTC timer, in BCD format. - * @retval None - */ -__STATIC_INLINE void md_rtc_set_cal_mon_u(RTC_TypeDef *rtc, uint32_t mon_u) -{ - MODIFY_REG(rtc->CAL, RTC_CAL_MON_U_MSK, (mon_u<CAL, RTC_CAL_MON_U_MSK)>>RTC_CAL_MON_U_POSS); -} -/** - * @brief Set Date Tens Value - * @param rtc RTC Instance - * @param date_t Date tens value in RTC timer, in BCD format. - * @retval None - */ -__STATIC_INLINE void md_rtc_set_cal_date_t(RTC_TypeDef *rtc, uint32_t date_t) -{ - MODIFY_REG(rtc->CAL, RTC_CAL_DATE_T_MSK, (date_t<CAL, RTC_CAL_DATE_T_MSK)>>RTC_CAL_DATE_T_POSS); -} -/** - * @brief Set Date Units Value - * @param rtc RTC Instance - * @param date_u Date units value in RTC timer, in BCD format. - * @retval None - */ -__STATIC_INLINE void md_rtc_set_cal_date_u(RTC_TypeDef *rtc, uint32_t date_u) -{ - MODIFY_REG(rtc->CAL, RTC_CAL_DATE_U_MSK, (date_u<CAL, RTC_CAL_DATE_U_MSK)>>RTC_CAL_DATE_U_POSS); -} - -/** - * @brief Set Alarm Week Value - * @param rtc RTC Instance - * @param week Alarm Week value in RTC timer, in BCD format. - * @retval None - */ -__STATIC_INLINE void md_rtc_set_altime_week(RTC_TypeDef *rtc, uint32_t week) -{ - MODIFY_REG(rtc->ALTIME, RTC_ALTIME_WEEK_MSK, (week<ALTIME, RTC_ALTIME_WEEK_MSK)>>RTC_ALTIME_WEEK_POSS); -} -/** - * @brief Set Alarm Hour Tens Value - * @param rtc RTC Instance - * @param hour_t Alarm Hour tens value in RTC timer, in BCD format. - * @retval None - */ -__STATIC_INLINE void md_rtc_set_altime_hour_t(RTC_TypeDef *rtc, uint32_t hour_t) -{ - MODIFY_REG(rtc->ALTIME, RTC_ALTIME_HOUR_T_MSK, (hour_t<ALTIME, RTC_ALTIME_HOUR_T_MSK)>>RTC_ALTIME_HOUR_T_POSS); -} -/** - * @brief Set Alarm Hour Units Value - * @param rtc RTC Instance - * @param hour_u Alarm Hour units value in RTC timer, in BCD format. - * @retval None - */ -__STATIC_INLINE void md_rtc_set_altime_hour_u(RTC_TypeDef *rtc, uint32_t hour_u) -{ - MODIFY_REG(rtc->ALTIME, RTC_ALTIME_HOUR_U_MSK, (hour_u<ALTIME, RTC_ALTIME_HOUR_U_MSK)>>RTC_ALTIME_HOUR_U_POSS); -} -/** - * @brief Set Alarm Minute Tens Value - * @param rtc RTC Instance - * @param min_t Alarm Minute tens value in RTC timer, in BCD format. - * @retval None - */ -__STATIC_INLINE void md_rtc_set_altime_min_t(RTC_TypeDef *rtc, uint32_t min_t) -{ - MODIFY_REG(rtc->ALTIME, RTC_ALTIME_MIN_T_MSK, (min_t<ALTIME, RTC_ALTIME_MIN_T_MSK)>>RTC_ALTIME_MIN_T_POSS); -} -/** - * @brief Set Alarm Minute Units Value - * @param rtc RTC Instance - * @param min_u Alarm Minute units value in RTC timer, in BCD format. - * @retval None - */ -__STATIC_INLINE void md_rtc_set_altime_min_u(RTC_TypeDef *rtc, uint32_t min_u) -{ - MODIFY_REG(rtc->ALTIME, RTC_ALTIME_MIN_U_MSK, (min_u<ALTIME, RTC_ALTIME_MIN_U_MSK)>>RTC_ALTIME_MIN_U_POSS); -} -/** - * @brief Set Alarm Second Tens Value - * @param rtc RTC Instance - * @param sec_t Alarm Second tens value in RTC timer, in BCD format. - * @retval None - */ -__STATIC_INLINE void md_rtc_set_altime_sec_t(RTC_TypeDef *rtc, uint32_t sec_t) -{ - MODIFY_REG(rtc->ALTIME, RTC_ALTIME_SEC_T_MSK, (sec_t<ALTIME, RTC_ALTIME_SEC_T_MSK)>>RTC_ALTIME_SEC_T_POSS); -} -/** - * @brief Set Alarm Second Units Value - * @param rtc RTC Instance - * @param sec_u Alarm Second units value in RTC timer, in BCD format. - * @retval None - */ -__STATIC_INLINE void md_rtc_set_altime_sec_u(RTC_TypeDef *rtc, uint32_t sec_u) -{ - MODIFY_REG(rtc->ALTIME, RTC_ALTIME_SEC_U_MSK, (sec_u<ALTIME, RTC_ALTIME_SEC_U_MSK)>>RTC_ALTIME_SEC_U_POSS); -} - -/** - * @brief Set Alarm Year Tens Value - * @param rtc RTC Instance - * @param year_t Alarm Year tens value in RTC timer, in BCD format. - * @retval None - */ -__STATIC_INLINE void md_rtc_set_alcal_year_t(RTC_TypeDef *rtc, uint32_t year_t) -{ - MODIFY_REG(rtc->ALCAL, RTC_ALCAL_YEAR_T_MSK, (year_t<ALCAL, RTC_ALCAL_YEAR_T_MSK)>>RTC_ALCAL_YEAR_T_POSS); -} -/** - * @brief Set Alarm Year Units Value - * @param rtc RTC Instance - * @param year_u Alarm Year units value in RTC timer, in BCD format. - * @retval None - */ -__STATIC_INLINE void md_rtc_set_alcal_year_u(RTC_TypeDef *rtc, uint32_t year_u) -{ - MODIFY_REG(rtc->ALCAL, RTC_ALCAL_YEAR_U_MSK, (year_u<ALCAL, RTC_ALCAL_YEAR_U_MSK)>>RTC_ALCAL_YEAR_U_POSS); -} -/** - * @brief Set Alarm Month Tens Value - * @param rtc RTC Instance - * @param mon_t Alarm Month tens value in RTC timer, in BCD format. - * @retval None - */ -__STATIC_INLINE void md_rtc_set_alcal_mon_t(RTC_TypeDef *rtc, uint32_t mon_t) -{ - MODIFY_REG(rtc->ALCAL, RTC_ALCAL_MON_T_MSK, (mon_t<ALCAL, RTC_ALCAL_MON_T_MSK)>>RTC_ALCAL_MON_T_POS); -} -/** - * @brief Set Alarm Month Units Value - * @param rtc RTC Instance - * @param mon_u Alarm Month units value in RTC timer, in BCD format. - * @retval None - */ -__STATIC_INLINE void md_rtc_set_alcal_mon_u(RTC_TypeDef *rtc, uint32_t mon_u) -{ - MODIFY_REG(rtc->ALCAL, RTC_ALCAL_MON_U_MSK, (mon_u<ALCAL, RTC_ALCAL_MON_U_MSK)>>RTC_ALCAL_MON_U_POSS); -} -/** - * @brief Set Alarm Date Tens Value - * @param rtc RTC Instance - * @param date_t Alarm Date tens value in RTC timer, in BCD format. - * @retval None - */ -__STATIC_INLINE void md_rtc_set_alcal_date_t(RTC_TypeDef *rtc, uint32_t date_t) -{ - MODIFY_REG(rtc->ALCAL, RTC_ALCAL_DATE_T_MSK, (date_t<ALCAL, RTC_ALCAL_DATE_T_MSK)>>RTC_ALCAL_DATE_T_POSS); -} -/** - * @brief Set Alarm Date Units Value - * @param rtc RTC Instance - * @param date_u Alarm Date units value in RTC timer, in BCD format. - * @retval None - */ -__STATIC_INLINE void md_rtc_set_alcal_date_u(RTC_TypeDef *rtc, uint32_t date_u) -{ - MODIFY_REG(rtc->ALCAL, RTC_ALCAL_DATE_U_MSK, (date_u<ALCAL, RTC_ALCAL_DATE_U_MSK)>>RTC_ALCAL_DATE_U_POSS); -} - -/** - * @brief Set Year Alarm Function Enable - * @param rtc RTC Instance - * @param year can be one of the following values: - * @arg DISABLE - * @arg ENABLE - * @retval None - */ -__STATIC_INLINE void md_rtc_set_alen_year(RTC_TypeDef *rtc, uint32_t year) -{ - MODIFY_REG(rtc->ALEN, RTC_ALEN_YEAR_MSK, (year<ALEN, RTC_ALEN_YEAR_MSK)>>RTC_ALEN_YEAR_POS); -} -/** - * @brief Set Month Alarm Function Enable - * @param rtc RTC Instance - * @param month can be one of the following values: - * @arg DISABLE - * @arg ENABLE - * @retval None - */ -__STATIC_INLINE void md_rtc_set_alen_month(RTC_TypeDef *rtc, uint32_t month) -{ - MODIFY_REG(rtc->ALEN, RTC_ALEN_MONTH_MSK, (month<ALEN, RTC_ALEN_MONTH_MSK)>>RTC_ALEN_MONTH_POS); -} -/** - * @brief Set Date Alarm Function Enable - * @param rtc RTC Instance - * @param date can be one of the following values: - * @arg DISABLE - * @arg ENABLE - * @retval None - */ -__STATIC_INLINE void md_rtc_set_alen_date(RTC_TypeDef *rtc, uint32_t date) -{ - MODIFY_REG(rtc->ALEN, RTC_ALEN_DATE_MSK, (date<ALEN, RTC_ALEN_DATE_MSK)>>RTC_ALEN_DATE_POS); -} -/** - * @brief Set Week Alarm Function Enable - * @param rtc RTC Instance - * @param week can be one of the following values: - * @arg DISABLE - * @arg ENABLE - * @retval None - */ -__STATIC_INLINE void md_rtc_set_alen_week(RTC_TypeDef *rtc, uint32_t week) -{ - MODIFY_REG(rtc->ALEN, RTC_ALEN_WEEK_MSK, (week<ALEN, RTC_ALEN_WEEK_MSK)>>RTC_ALEN_WEEK_POS); -} -/** - * @brief Set Hour Alarm Function Enable - * @param rtc RTC Instance - * @param hour can be one of the following values: - * @arg DISABLE - * @arg ENABLE - * @retval None - */ -__STATIC_INLINE void md_rtc_set_alen_hour(RTC_TypeDef *rtc, uint32_t hour) -{ - MODIFY_REG(rtc->ALEN, RTC_ALEN_HOUR_MSK, (hour<ALEN, RTC_ALEN_HOUR_MSK)>>RTC_ALEN_HOUR_POS); -} -/** - * @brief Set Minute Alarm Function Enable - * @param rtc RTC Instance - * @param min can be one of the following values: - * @arg DISABLE - * @arg ENABLE - * @retval None - */ -__STATIC_INLINE void md_rtc_set_alen_min(RTC_TypeDef *rtc, uint32_t min) -{ - MODIFY_REG(rtc->ALEN, RTC_ALEN_MIN_MSK, (min<ALEN, RTC_ALEN_MIN_MSK)>>RTC_ALEN_MIN_POS); -} -/** - * @brief Set Second Alarm Function Enable - * @param rtc RTC Instance - * @param sec can be one of the following values: - * @arg DISABLE - * @arg ENABLE - * @retval None - */ -__STATIC_INLINE void md_rtc_set_alen_sec(RTC_TypeDef *rtc, uint32_t sec) -{ - MODIFY_REG(rtc->ALEN, RTC_ALEN_SEC_MSK, (sec<ALEN, RTC_ALEN_SEC_MSK)>>RTC_ALEN_SEC_POS); -} - -/** - * @brief Set RTC Wakeup Counter Match Trigger Enable - * @param rtc RTC Instance - * @param wktm can be one of the following values: - * @arg DISABLE - * @arg ENABLE - * @retval None - */ -__STATIC_INLINE void md_rtc_set_trig_wktm(RTC_TypeDef *rtc, uint32_t wktm) -{ - MODIFY_REG(rtc->TRIG, RTC_TRIG_WKTM_MSK, (wktm<TRIG, RTC_TRIG_WKTM_MSK)>>RTC_TRIG_WKTM_POS); -} -/** - * @brief Set RTC 1 Hz Trigger Enable - * @param rtc RTC Instance - * @param f1hz can be one of the following values: - * @arg DISABLE - * @arg ENABLE - * @retval None - */ -__STATIC_INLINE void md_rtc_set_trig_f1hz(RTC_TypeDef *rtc, uint32_t f1hz) -{ - MODIFY_REG(rtc->TRIG, RTC_TRIG_F1HZ_MSK, (f1hz<TRIG, RTC_TRIG_F1HZ_MSK)>>RTC_TRIG_F1HZ_POS); -} -/** - * @brief Set RTC Year Roll Alarm Trigger Enable - * @param rtc RTC Instance - * @param ryear can be one of the following values: - * @arg DISABLE - * @arg ENABLE - * @retval None - */ -__STATIC_INLINE void md_rtc_set_trig_ryear(RTC_TypeDef *rtc, uint32_t ryear) -{ - MODIFY_REG(rtc->TRIG, RTC_TRIG_RYEAR_MSK, (ryear<TRIG, RTC_TRIG_RYEAR_MSK)>>RTC_TRIG_RYEAR_POS); -} -/** - * @brief Set RTC Month Roll Alarm Trigger Enable - * @param rtc RTC Instance - * @param rmon can be one of the following values: - * @arg DISABLE - * @arg ENABLE - * @retval None - */ -__STATIC_INLINE void md_rtc_set_trig_rmon(RTC_TypeDef *rtc, uint32_t rmon) -{ - MODIFY_REG(rtc->TRIG, RTC_TRIG_RMON_MSK, (rmon<TRIG, RTC_TRIG_RMON_MSK)>>RTC_TRIG_RMON_POS); -} -/** - * @brief Set RTC Date Roll Alarm Trigger Enable - * @param rtc RTC Instance - * @param rdate can be one of the following values: - * @arg DISABLE - * @arg ENABLE - * @retval None - */ -__STATIC_INLINE void md_rtc_set_trig_rdate(RTC_TypeDef *rtc, uint32_t rdate) -{ - MODIFY_REG(rtc->TRIG, RTC_TRIG_RDATE_MSK, (rdate<TRIG, RTC_TRIG_RDATE_MSK)>>RTC_TRIG_RDATE_POS); -} -/** - * @brief Set RTC Week Roll Alarm Trigger Enable - * @param rtc RTC Instance - * @param rweek can be one of the following values: - * @arg DISABLE - * @arg ENABLE - * @retval None - */ -__STATIC_INLINE void md_rtc_set_trig_rweek(RTC_TypeDef *rtc, uint32_t rweek) -{ - MODIFY_REG(rtc->TRIG, RTC_TRIG_RWEEK_MSK, (rweek<TRIG, RTC_TRIG_RWEEK_MSK)>>RTC_TRIG_RWEEK_POS); -} -/** - * @brief Set RTC Hour Roll Alarm Trigger Enable - * @param rtc RTC Instance - * @param rhour can be one of the following values: - * @arg DISABLE - * @arg ENABLE - * @retval None - */ -__STATIC_INLINE void md_rtc_set_trig_rhour(RTC_TypeDef *rtc, uint32_t rhour) -{ - MODIFY_REG(rtc->TRIG, RTC_TRIG_RHOUR_MSK, (rhour<TRIG, RTC_TRIG_RHOUR_MSK)>>RTC_TRIG_RHOUR_POS); -} -/** - * @brief Set RTC Minute Roll Alarm Trigger Enable - * @param rtc RTC Instance - * @param rmin can be one of the following values: - * @arg DISABLE - * @arg ENABLE - * @retval None - */ -__STATIC_INLINE void md_rtc_set_trig_rmin(RTC_TypeDef *rtc, uint32_t rmin) -{ - MODIFY_REG(rtc->TRIG, RTC_TRIG_RMIN_MSK, (rmin<TRIG, RTC_TRIG_RMIN_MSK)>>RTC_TRIG_RMIN_POS); -} -/** - * @brief Set RTC Second Roll Alarm Trigger Enable - * @param rtc RTC Instance - * @param rsec can be one of the following values: - * @arg DISABLE - * @arg ENABLE - * @retval None - */ -__STATIC_INLINE void md_rtc_set_trig_rsec(RTC_TypeDef *rtc, uint32_t rsec) -{ - MODIFY_REG(rtc->TRIG, RTC_TRIG_RSEC_MSK, (rsec<TRIG, RTC_TRIG_RSEC_MSK)>>RTC_TRIG_RSEC_POS); -} -/** - * @brief Set RTC Match All Alarm Trigger Enable - * @param rtc RTC Instance - * @param amall can be one of the following values: - * @arg DISABLE - * @arg ENABLE - * @retval None - */ -__STATIC_INLINE void md_rtc_set_trig_amall(RTC_TypeDef *rtc, uint32_t amall) -{ - MODIFY_REG(rtc->TRIG, RTC_TRIG_AMALL_MSK, (amall<TRIG, RTC_TRIG_AMALL_MSK)>>RTC_TRIG_AMALL_POS); -} -/** - * @brief Set RTC Match Year Alarm Trigger Enable - * @param rtc RTC Instance - * @param ayear can be one of the following values: - * @arg DISABLE - * @arg ENABLE - * @retval None - */ -__STATIC_INLINE void md_rtc_set_trig_ayear(RTC_TypeDef *rtc, uint32_t ayear) -{ - MODIFY_REG(rtc->TRIG, RTC_TRIG_AYEAR_MSK, (ayear<TRIG, RTC_TRIG_AYEAR_MSK)>>RTC_TRIG_AYEAR_POS); -} -/** - * @brief Set RTC Match Month Alarm Trigger Enable - * @param rtc RTC Instance - * @param amon can be one of the following values: - * @arg DISABLE - * @arg ENABLE - * @retval None - */ -__STATIC_INLINE void md_rtc_set_trig_amon(RTC_TypeDef *rtc, uint32_t amon) -{ - MODIFY_REG(rtc->TRIG, RTC_TRIG_AMON_MSK, (amon<TRIG, RTC_TRIG_AMON_MSK)>>RTC_TRIG_AMON_POS); -} -/** - * @brief Set RTC Match Date Alarm Trigger Enable - * @param rtc RTC Instance - * @param adate can be one of the following values: - * @arg DISABLE - * @arg ENABLE - * @retval None - */ -__STATIC_INLINE void md_rtc_set_trig_adate(RTC_TypeDef *rtc, uint32_t adate) -{ - MODIFY_REG(rtc->TRIG, RTC_TRIG_ADTAE_MSK, (adate<TRIG, RTC_TRIG_ADTAE_MSK)>>RTC_TRIG_ADTAE_POS); -} -/** - * @brief Set RTC Match Week Alarm Trigger Enable - * @param rtc RTC Instance - * @param aweek can be one of the following values: - * @arg DISABLE - * @arg ENABLE - * @retval None - */ -__STATIC_INLINE void md_rtc_set_trig_aweek(RTC_TypeDef *rtc, uint32_t aweek) -{ - MODIFY_REG(rtc->TRIG, RTC_TRIG_AWEEK_MSK, (aweek<TRIG, RTC_TRIG_AWEEK_MSK)>>RTC_TRIG_AWEEK_POS); -} -/** - * @brief Set RTC Match Hour Alarm Trigger Enable - * @param rtc RTC Instance - * @param ahour can be one of the following values: - * @arg DISABLE - * @arg ENABLE - * @retval None - */ -__STATIC_INLINE void md_rtc_set_trig_ahour(RTC_TypeDef *rtc, uint32_t ahour) -{ - MODIFY_REG(rtc->TRIG, RTC_TRIG_AHOUR_MSK, (ahour<TRIG, RTC_TRIG_AHOUR_MSK)>>RTC_TRIG_AHOUR_POS); -} -/** - * @brief Set RTC Match Minute Alarm Trigger Enable - * @param rtc RTC Instance - * @param amin can be one of the following values: - * @arg DISABLE - * @arg ENABLE - * @retval None - */ -__STATIC_INLINE void md_rtc_set_trig_amin(RTC_TypeDef *rtc, uint32_t amin) -{ - MODIFY_REG(rtc->TRIG, RTC_TRIG_AMIN_MSK, (amin<TRIG, RTC_TRIG_AMIN_MSK)>>RTC_TRIG_AMIN_POS); -} -/** - * @brief Set RTC Match Second Alarm Trigger Enable - * @param rtc RTC Instance - * @param asec can be one of the following values: - * @arg DISABLE - * @arg ENABLE - * @retval None - */ -__STATIC_INLINE void md_rtc_set_trig_asec(RTC_TypeDef *rtc, uint32_t asec) -{ - MODIFY_REG(rtc->TRIG, RTC_TRIG_ASEC_MSK, (asec<TRIG, RTC_TRIG_ASEC_MSK)>>RTC_TRIG_ASEC_POS); -} - -/** - * @brief Set RTC Wakeup Counter Match Interrupt Enable bit - * @param rtc RTC Instance - * @retval None - */ -__STATIC_INLINE void md_rtc_enable_ier_wktm(RTC_TypeDef *rtc) -{ - SET_BIT(rtc->IER, RTC_IER_WKTM_MSK); -} -/** - * @brief Set RTC 1 Hz Interrupt Enable bit - * @param rtc RTC Instance - * @retval None - */ -__STATIC_INLINE void md_rtc_enable_ier_f1hz(RTC_TypeDef *rtc) -{ - SET_BIT(rtc->IER, RTC_IER_F1HZ_MSK); -} -/** - * @brief Set RTC Year Roll Alarm Interrupt Enable bit - * @param rtc RTC Instance - * @retval None - */ -__STATIC_INLINE void md_rtc_enable_ier_ryear(RTC_TypeDef *rtc) -{ - SET_BIT(rtc->IER, RTC_IER_RYEAR_MSK); -} -/** - * @brief Set RTC Month Roll Alarm Interrupt Enable bit - * @param rtc RTC Instance - * @retval None - */ -__STATIC_INLINE void md_rtc_enable_ier_rmon(RTC_TypeDef *rtc) -{ - SET_BIT(rtc->IER, RTC_IER_RMON_MSK); -} -/** - * @brief Set RTC Date Roll Alarm Interrupt Enable bit - * @param rtc RTC Instance - * @retval None - */ -__STATIC_INLINE void md_rtc_enable_ier_rdate(RTC_TypeDef *rtc) -{ - SET_BIT(rtc->IER, RTC_IER_RDATE_MSK); -} -/** - * @brief Set RTC Week Roll Alarm Interrupt Enable bit - * @param rtc RTC Instance - * @retval None - */ -__STATIC_INLINE void md_rtc_enable_ier_rweek(RTC_TypeDef *rtc) -{ - SET_BIT(rtc->IER, RTC_IER_RWEEK_MSK); -} -/** - * @brief Set RTC Hour Roll Alarm Interrupt Enable bit - * @param rtc RTC Instance - * @retval None - */ -__STATIC_INLINE void md_rtc_enable_ier_rhour(RTC_TypeDef *rtc) -{ - SET_BIT(rtc->IER, RTC_IER_RHOUR_MSK); -} -/** - * @brief Set RTC Minute Roll Alarm Interrupt Enable bit - * @param rtc RTC Instance - * @retval None - */ -__STATIC_INLINE void md_rtc_enable_ier_rmin(RTC_TypeDef *rtc) -{ - SET_BIT(rtc->IER, RTC_IER_RMIN_MSK); -} -/** - * @brief Set RTC Second Roll Alarm Interrupt Enable bit - * @param rtc RTC Instance - * @retval None - */ -__STATIC_INLINE void md_rtc_enable_ier_rsec(RTC_TypeDef *rtc) -{ - SET_BIT(rtc->IER, RTC_IER_RSEC_MSK); -} -/** - * @brief Set RTC Match All Alarm Interrupt Enable bit - * @param rtc RTC Instance - * @retval None - */ -__STATIC_INLINE void md_rtc_enable_ier_amall(RTC_TypeDef *rtc) -{ - SET_BIT(rtc->IER, RTC_IER_AMALL_MSK); -} -/** - * @brief Set RTC Match Year Alarm Interrupt Enable bit - * @param rtc RTC Instance - * @retval None - */ -__STATIC_INLINE void md_rtc_enable_ier_ayear(RTC_TypeDef *rtc) -{ - SET_BIT(rtc->IER, RTC_IER_AYEAR_MSK); -} -/** - * @brief Set RTC Match Month Alarm Interrupt Enable bit - * @param rtc RTC Instance - * @retval None - */ -__STATIC_INLINE void md_rtc_enable_ier_amon(RTC_TypeDef *rtc) -{ - SET_BIT(rtc->IER, RTC_IER_AMON_MSK); -} -/** - * @brief Set RTC Match Date Alarm Interrupt Enable bit - * @param rtc RTC Instance - * @retval None - */ -__STATIC_INLINE void md_rtc_enable_ier_adate(RTC_TypeDef *rtc) -{ - SET_BIT(rtc->IER, RTC_IER_ADTAE_MSK); -} -/** - * @brief Set RTC Match Week Alarm Interrupt Enable bit - * @param rtc RTC Instance - * @retval None - */ -__STATIC_INLINE void md_rtc_enable_ier_aweek(RTC_TypeDef *rtc) -{ - SET_BIT(rtc->IER, RTC_IER_AWEEK_MSK); -} -/** - * @brief Set RTC Match Hour Alarm Interrupt Enable bit - * @param rtc RTC Instance - * @retval None - */ -__STATIC_INLINE void md_rtc_enable_ier_ahour(RTC_TypeDef *rtc) -{ - SET_BIT(rtc->IER, RTC_IER_AHOUR_MSK); -} -/** - * @brief Set RTC Match Minute Alarm Interrupt Enable bit - * @param rtc RTC Instance - * @retval None - */ -__STATIC_INLINE void md_rtc_enable_ier_amin(RTC_TypeDef *rtc) -{ - SET_BIT(rtc->IER, RTC_IER_AMIN_MSK); -} -/** - * @brief Set RTC Match Second Alarm Interrupt Enable bit - * @param rtc RTC Instance - * @retval None - */ -__STATIC_INLINE void md_rtc_enable_ier_asec(RTC_TypeDef *rtc) -{ - SET_BIT(rtc->IER, RTC_IER_ASEC_MSK); -} - -/** - * @brief Set RTC Wakeup Counter Match Interrupt Disable bit - * @param rtc RTC Instance - * @retval None - */ -__STATIC_INLINE void md_rtc_enable_idr_wktm(RTC_TypeDef *rtc) -{ - SET_BIT(rtc->IDR, RTC_IDR_WKTM_MSK); -} -/** - * @brief Set RTC 1 Hz Interrupt Disable bit - * @param rtc RTC Instance - * @retval None - */ -__STATIC_INLINE void md_rtc_enable_idr_f1hz(RTC_TypeDef *rtc) -{ - SET_BIT(rtc->IDR, RTC_IDR_F1HZ_MSK); -} -/** - * @brief Set RTC Year Roll Alarm Interrupt Disable bit - * @param rtc RTC Instance - * @retval None - */ -__STATIC_INLINE void md_rtc_enable_idr_ryear(RTC_TypeDef *rtc) -{ - SET_BIT(rtc->IDR, RTC_IDR_RYEAR_MSK); -} -/** - * @brief Set RTC Month Roll Alarm Interrupt Disable bit - * @param rtc RTC Instance - * @retval None - */ -__STATIC_INLINE void md_rtc_enable_idr_rmon(RTC_TypeDef *rtc) -{ - SET_BIT(rtc->IDR, RTC_IDR_RMON_MSK); -} -/** - * @brief Set RTC Date Roll Alarm Interrupt Disable bit - * @param rtc RTC Instance - * @retval None - */ -__STATIC_INLINE void md_rtc_enable_idr_rdate(RTC_TypeDef *rtc) -{ - SET_BIT(rtc->IDR, RTC_IDR_RDATE_MSK); -} -/** - * @brief Set RTC Week Roll Alarm Interrupt Disable bit - * @param rtc RTC Instance - * @retval None - */ -__STATIC_INLINE void md_rtc_enable_idr_rweek(RTC_TypeDef *rtc) -{ - SET_BIT(rtc->IDR, RTC_IDR_RWEEK_MSK); -} -/** - * @brief Set RTC Hour Roll Alarm Interrupt Disable bit - * @param rtc RTC Instance - * @retval None - */ -__STATIC_INLINE void md_rtc_enable_idr_rhour(RTC_TypeDef *rtc) -{ - SET_BIT(rtc->IDR, RTC_IDR_RHOUR_MSK); -} -/** - * @brief Set RTC Minute Roll Alarm Interrupt Disable bit - * @param rtc RTC Instance - * @retval None - */ -__STATIC_INLINE void md_rtc_enable_idr_rmin(RTC_TypeDef *rtc) -{ - SET_BIT(rtc->IDR, RTC_IDR_RMIN_MSK); -} -/** - * @brief Set RTC Second Roll Alarm Interrupt Disable bit - * @param rtc RTC Instance - * @retval None - */ -__STATIC_INLINE void md_rtc_enable_idr_rsec(RTC_TypeDef *rtc) -{ - SET_BIT(rtc->IDR, RTC_IDR_RSEC_MSK); -} -/** - * @brief Set RTC Match All Alarm Interrupt Disable bit - * @param rtc RTC Instance - * @retval None - */ -__STATIC_INLINE void md_rtc_enable_idr_amall(RTC_TypeDef *rtc) -{ - SET_BIT(rtc->IDR, RTC_IDR_AMALL_MSK); -} -/** - * @brief Set RTC Match Year Alarm Interrupt Disable bit - * @param rtc RTC Instance - * @retval None - */ -__STATIC_INLINE void md_rtc_enable_idr_ayear(RTC_TypeDef *rtc) -{ - SET_BIT(rtc->IDR, RTC_IDR_AYEAR_MSK); -} -/** - * @brief Set RTC Match Month Alarm Interrupt Disable bit - * @param rtc RTC Instance - * @retval None - */ -__STATIC_INLINE void md_rtc_enable_idr_amon(RTC_TypeDef *rtc) -{ - SET_BIT(rtc->IDR, RTC_IDR_AMON_MSK); -} -/** - * @brief Set RTC Match Date Alarm Interrupt Disable bit - * @param rtc RTC Instance - * @retval None - */ -__STATIC_INLINE void md_rtc_enable_idr_adate(RTC_TypeDef *rtc) -{ - SET_BIT(rtc->IDR, RTC_IDR_ADTAE_MSK); -} -/** - * @brief Set RTC Match Week Alarm Interrupt Disable bit - * @param rtc RTC Instance - * @retval None - */ -__STATIC_INLINE void md_rtc_enable_idr_aweek(RTC_TypeDef *rtc) -{ - SET_BIT(rtc->IDR, RTC_IDR_AWEEK_MSK); -} -/** - * @brief Set RTC Match Hour Alarm Interrupt Disable bit - * @param rtc RTC Instance - * @retval None - */ -__STATIC_INLINE void md_rtc_enable_idr_ahour(RTC_TypeDef *rtc) -{ - SET_BIT(rtc->IDR, RTC_IDR_AHOUR_MSK); -} -/** - * @brief Set RTC Match Minute Alarm Interrupt Disable bit - * @param rtc RTC Instance - * @retval None - */ -__STATIC_INLINE void md_rtc_enable_idr_amin(RTC_TypeDef *rtc) -{ - SET_BIT(rtc->IDR, RTC_IDR_AMIN_MSK); -} -/** - * @brief Set RTC Match Second Alarm Interrupt Disable bit - * @param rtc RTC Instance - * @retval None - */ -__STATIC_INLINE void md_rtc_enable_idr_asec(RTC_TypeDef *rtc) -{ - SET_BIT(rtc->IDR, RTC_IDR_ASEC_MSK); -} - -/** - * @brief Get RTC Wakeup Counter Match Interrupt Valid Status bit - * @param rtc RTC Instance - * @retval The retval can be one of the following values: - * @arg DISABLE - * @arg ENABLE - */ -__STATIC_INLINE uint32_t md_rtc_get_ivs_wktm(RTC_TypeDef *rtc) -{ - return (READ_BIT(rtc->IVS, RTC_IVS_WKTM_MSK)>>RTC_IVS_WKTM_POS); -} -/** - * @brief Get RTC 1 Hz Interrupt Valid Status bit - * @param rtc RTC Instance - * @retval The retval can be one of the following values: - * @arg DISABLE - * @arg ENABLE - */ -__STATIC_INLINE uint32_t md_rtc_get_ivs_f1hz(RTC_TypeDef *rtc) -{ - return (READ_BIT(rtc->IVS, RTC_IVS_F1HZ_MSK)>>RTC_IVS_F1HZ_POS); -} -/** - * @brief Get RTC Year Roll Alarm Interrupt Valid Status bit - * @param rtc RTC Instance - * @retval The retval can be one of the following values: - * @arg DISABLE - * @arg ENABLE - */ -__STATIC_INLINE uint32_t md_rtc_get_ivs_ryear(RTC_TypeDef *rtc) -{ - return (READ_BIT(rtc->IVS, RTC_IVS_RYEAR_MSK)>>RTC_IVS_RYEAR_POS); -} -/** - * @brief Get RTC Month Roll Alarm Interrupt Valid Status bit - * @param rtc RTC Instance - * @retval The retval can be one of the following values: - * @arg DISABLE - * @arg ENABLE - */ -__STATIC_INLINE uint32_t md_rtc_get_ivs_rmon(RTC_TypeDef *rtc) -{ - return (READ_BIT(rtc->IVS, RTC_IVS_RMON_MSK)>>RTC_IVS_RMON_POS); -} -/** - * @brief Get RTC Date Roll Alarm Interrupt Valid Status bit - * @param rtc RTC Instance - * @retval The retval can be one of the following values: - * @arg DISABLE - * @arg ENABLE - */ -__STATIC_INLINE uint32_t md_rtc_get_ivs_rdate(RTC_TypeDef *rtc) -{ - return (READ_BIT(rtc->IVS, RTC_IVS_RDATE_MSK)>>RTC_IVS_RDATE_POS); -} -/** - * @brief Get RTC Week Roll Alarm Interrupt Valid Status bit - * @param rtc RTC Instance - * @retval The retval can be one of the following values: - * @arg DISABLE - * @arg ENABLE - */ -__STATIC_INLINE uint32_t md_rtc_get_ivs_rweek(RTC_TypeDef *rtc) -{ - return (READ_BIT(rtc->IVS, RTC_IVS_RWEEK_MSK)>>RTC_IVS_RWEEK_POS); -} -/** - * @brief Get RTC Hour Roll Alarm Interrupt Valid Status bit - * @param rtc RTC Instance - * @retval The retval can be one of the following values: - * @arg DISABLE - * @arg ENABLE - */ -__STATIC_INLINE uint32_t md_rtc_get_ivs_rhour(RTC_TypeDef *rtc) -{ - return (READ_BIT(rtc->IVS, RTC_IVS_RHOUR_MSK)>>RTC_IVS_RHOUR_POS); -} -/** - * @brief Get RTC Minute Roll Alarm Interrupt Valid Status bit - * @param rtc RTC Instance - * @retval The retval can be one of the following values: - * @arg DISABLE - * @arg ENABLE - */ -__STATIC_INLINE uint32_t md_rtc_get_ivs_rmin(RTC_TypeDef *rtc) -{ - return (READ_BIT(rtc->IVS, RTC_IVS_RMIN_MSK)>>RTC_IVS_RMIN_POS); -} -/** - * @brief Get RTC Second Roll Alarm Interrupt Valid Status bit - * @param rtc RTC Instance - * @retval The retval can be one of the following values: - * @arg DISABLE - * @arg ENABLE - */ -__STATIC_INLINE uint32_t md_rtc_get_ivs_rsec(RTC_TypeDef *rtc) -{ - return (READ_BIT(rtc->IVS, RTC_IVS_RSEC_MSK)>>RTC_IVS_RSEC_POS); -} -/** - * @brief Get RTC Match All Alarm Interrupt Valid Status bit - * @param rtc RTC Instance - * @retval The retval can be one of the following values: - * @arg DISABLE - * @arg ENABLE - */ -__STATIC_INLINE uint32_t md_rtc_get_ivs_amall(RTC_TypeDef *rtc) -{ - return (READ_BIT(rtc->IVS, RTC_IVS_AMALL_MSK)>>RTC_IVS_AMALL_POS); -} -/** - * @brief Get RTC Match Year Alarm Interrupt Valid Status bit - * @param rtc RTC Instance - * @retval The retval can be one of the following values: - * @arg DISABLE - * @arg ENABLE - */ -__STATIC_INLINE uint32_t md_rtc_get_ivs_ayear(RTC_TypeDef *rtc) -{ - return (READ_BIT(rtc->IVS, RTC_IVS_AYEAR_MSK)>>RTC_IVS_AYEAR_POS); -} -/** - * @brief Get RTC Match Month Alarm Interrupt Valid Status bit - * @param rtc RTC Instance - * @retval The retval can be one of the following values: - * @arg DISABLE - * @arg ENABLE - */ -__STATIC_INLINE uint32_t md_rtc_get_ivs_amon(RTC_TypeDef *rtc) -{ - return (READ_BIT(rtc->IVS, RTC_IVS_AMON_MSK)>>RTC_IVS_AMON_POS); -} -/** - * @brief Get RTC Match Date Alarm Interrupt Valid Status bit - * @param rtc RTC Instance - * @retval The retval can be one of the following values: - * @arg DISABLE - * @arg ENABLE - */ -__STATIC_INLINE uint32_t md_rtc_get_ivs_adate(RTC_TypeDef *rtc) -{ - return (READ_BIT(rtc->IVS, RTC_IVS_ADTAE_MSK)>>RTC_IVS_ADTAE_POS); -} -/** - * @brief Get RTC Match Week Alarm Interrupt Valid Status bit - * @param rtc RTC Instance - * @retval The retval can be one of the following values: - * @arg DISABLE - * @arg ENABLE - */ -__STATIC_INLINE uint32_t md_rtc_get_ivs_aweek(RTC_TypeDef *rtc) -{ - return (READ_BIT(rtc->IVS, RTC_IVS_AWEEK_MSK)>>RTC_IVS_AWEEK_POS); -} -/** - * @brief Get RTC Match Hour Alarm Interrupt Valid Status bit - * @param rtc RTC Instance - * @retval The retval can be one of the following values: - * @arg DISABLE - * @arg ENABLE - */ -__STATIC_INLINE uint32_t md_rtc_get_ivs_ahour(RTC_TypeDef *rtc) -{ - return (READ_BIT(rtc->IVS, RTC_IVS_AHOUR_MSK)>>RTC_IVS_AHOUR_POS); -} -/** - * @brief Get RTC Match Minute Alarm Interrupt Valid Status bit - * @param rtc RTC Instance - * @retval The retval can be one of the following values: - * @arg DISABLE - * @arg ENABLE - */ -__STATIC_INLINE uint32_t md_rtc_get_ivs_amin(RTC_TypeDef *rtc) -{ - return (READ_BIT(rtc->IVS, RTC_IVS_AMIN_MSK)>>RTC_IVS_AMIN_POS); -} -/** - * @brief Get RTC Match Second Alarm Interrupt Valid Status bit - * @param rtc RTC Instance - * @retval The retval can be one of the following values: - * @arg DISABLE - * @arg ENABLE - */ -__STATIC_INLINE uint32_t md_rtc_get_ivs_asec(RTC_TypeDef *rtc) -{ - return (READ_BIT(rtc->IVS, RTC_IVS_ASEC_MSK)>>RTC_IVS_ASEC_POS); -} - -/** - * @brief Get RTC Wakeup Counter Match Raw Interrupt Flag Status bit - * @param rtc RTC Instance - * @retval The retval can be one of the following values: - * @arg DISABLE - * @arg ENABLE - */ -__STATIC_INLINE uint32_t md_rtc_get_rif_wktm(RTC_TypeDef *rtc) -{ - return (READ_BIT(rtc->RIF, RTC_RIF_WKTM_MSK)>>RTC_RIF_WKTM_POS); -} -/** - * @brief Get RTC 1 Hz Raw Interrupt Flag Status bit - * @param rtc RTC Instance - * @retval The retval can be one of the following values: - * @arg DISABLE - * @arg ENABLE - */ -__STATIC_INLINE uint32_t md_rtc_get_rif_f1hz(RTC_TypeDef *rtc) -{ - return (READ_BIT(rtc->RIF, RTC_RIF_F1HZ_MSK)>>RTC_RIF_F1HZ_POS); -} -/** - * @brief Get RTC Year Roll Alarm Raw Interrupt Flag Status bit - * @param rtc RTC Instance - * @retval The retval can be one of the following values: - * @arg DISABLE - * @arg ENABLE - */ -__STATIC_INLINE uint32_t md_rtc_get_rif_ryear(RTC_TypeDef *rtc) -{ - return (READ_BIT(rtc->RIF, RTC_RIF_RYEAR_MSK)>>RTC_RIF_RYEAR_POS); -} -/** - * @brief Get RTC Month Roll Alarm Raw Interrupt Flag Status bit - * @param rtc RTC Instance - * @retval The retval can be one of the following values: - * @arg DISABLE - * @arg ENABLE - */ -__STATIC_INLINE uint32_t md_rtc_get_rif_rmon(RTC_TypeDef *rtc) -{ - return (READ_BIT(rtc->RIF, RTC_RIF_RMON_MSK)>>RTC_RIF_RMON_POS); -} -/** - * @brief Get RTC Date Roll Alarm Raw Interrupt Flag Status bit - * @param rtc RTC Instance - * @retval The retval can be one of the following values: - * @arg DISABLE - * @arg ENABLE - */ -__STATIC_INLINE uint32_t md_rtc_get_rif_rdate(RTC_TypeDef *rtc) -{ - return (READ_BIT(rtc->RIF, RTC_RIF_RDATE_MSK)>>RTC_RIF_RDATE_POS); -} -/** - * @brief Get RTC Week Roll Alarm Raw Interrupt Flag Status bit - * @param rtc RTC Instance - * @retval The retval can be one of the following values: - * @arg DISABLE - * @arg ENABLE - */ -__STATIC_INLINE uint32_t md_rtc_get_rif_rweek(RTC_TypeDef *rtc) -{ - return (READ_BIT(rtc->RIF, RTC_RIF_RWEEK_MSK)>>RTC_RIF_RWEEK_POS); -} -/** - * @brief Get RTC Hour Roll Alarm Raw Interrupt Flag Status bit - * @param rtc RTC Instance - * @retval The retval can be one of the following values: - * @arg DISABLE - * @arg ENABLE - */ -__STATIC_INLINE uint32_t md_rtc_get_rif_rhour(RTC_TypeDef *rtc) -{ - return (READ_BIT(rtc->RIF, RTC_RIF_RHOUR_MSK)>>RTC_RIF_RHOUR_POS); -} -/** - * @brief Get RTC Minute Roll Alarm Raw Interrupt Flag Status bit - * @param rtc RTC Instance - * @retval The retval can be one of the following values: - * @arg DISABLE - * @arg ENABLE - */ -__STATIC_INLINE uint32_t md_rtc_get_rif_rmin(RTC_TypeDef *rtc) -{ - return (READ_BIT(rtc->RIF, RTC_RIF_RMIN_MSK)>>RTC_RIF_RMIN_POS); -} -/** - * @brief Get RTC Second Roll Alarm Raw Interrupt Flag Status bit - * @param rtc RTC Instance - * @retval The retval can be one of the following values: - * @arg DISABLE - * @arg ENABLE - */ -__STATIC_INLINE uint32_t md_rtc_get_rif_rsec(RTC_TypeDef *rtc) -{ - return (READ_BIT(rtc->RIF, RTC_RIF_RSEC_MSK)>>RTC_RIF_RSEC_POS); -} -/** - * @brief Get RTC Match All Alarm Raw Interrupt Flag Status bit - * @param rtc RTC Instance - * @retval The retval can be one of the following values: - * @arg DISABLE - * @arg ENABLE - */ -__STATIC_INLINE uint32_t md_rtc_get_rif_amall(RTC_TypeDef *rtc) -{ - return (READ_BIT(rtc->RIF, RTC_RIF_AMALL_MSK)>>RTC_RIF_AMALL_POS); -} -/** - * @brief Get RTC Match Year Alarm Raw Interrupt Flag Status bit - * @param rtc RTC Instance - * @retval The retval can be one of the following values: - * @arg DISABLE - * @arg ENABLE - */ -__STATIC_INLINE uint32_t md_rtc_get_rif_ayear(RTC_TypeDef *rtc) -{ - return (READ_BIT(rtc->RIF, RTC_RIF_AYEAR_MSK)>>RTC_RIF_AYEAR_POS); -} -/** - * @brief Get RTC Match Month Alarm Raw Interrupt Flag Status bit - * @param rtc RTC Instance - * @retval The retval can be one of the following values: - * @arg DISABLE - * @arg ENABLE - */ -__STATIC_INLINE uint32_t md_rtc_get_rif_amon(RTC_TypeDef *rtc) -{ - return (READ_BIT(rtc->RIF, RTC_RIF_AMON_MSK)>>RTC_RIF_AMON_POS); -} -/** - * @brief Get RTC Match Date Alarm Raw Interrupt Flag Status bit - * @param rtc RTC Instance - * @retval The retval can be one of the following values: - * @arg DISABLE - * @arg ENABLE - */ -__STATIC_INLINE uint32_t md_rtc_get_rif_adate(RTC_TypeDef *rtc) -{ - return (READ_BIT(rtc->RIF, RTC_RIF_ADTAE_MSK)>>RTC_RIF_ADTAE_POS); -} -/** - * @brief Get RTC Match Week Alarm Raw Interrupt Flag Status bit - * @param rtc RTC Instance - * @retval The retval can be one of the following values: - * @arg DISABLE - * @arg ENABLE - */ -__STATIC_INLINE uint32_t md_rtc_get_rif_aweek(RTC_TypeDef *rtc) -{ - return (READ_BIT(rtc->RIF, RTC_RIF_AWEEK_MSK)>>RTC_RIF_AWEEK_POS); -} -/** - * @brief Get RTC Match Hour Alarm Raw Interrupt Flag Status bit - * @param rtc RTC Instance - * @retval The retval can be one of the following values: - * @arg DISABLE - * @arg ENABLE - */ -__STATIC_INLINE uint32_t md_rtc_get_rif_ahour(RTC_TypeDef *rtc) -{ - return (READ_BIT(rtc->RIF, RTC_RIF_AHOUR_MSK)>>RTC_RIF_AHOUR_POS); -} -/** - * @brief Get RTC Match Minute Alarm Raw Interrupt Flag Status bit - * @param rtc RTC Instance - * @retval The retval can be one of the following values: - * @arg DISABLE - * @arg ENABLE - */ -__STATIC_INLINE uint32_t md_rtc_get_rif_amin(RTC_TypeDef *rtc) -{ - return (READ_BIT(rtc->RIF, RTC_RIF_AMIN_MSK)>>RTC_RIF_AMIN_POS); -} -/** - * @brief Get RTC Match Second Alarm Raw Interrupt Flag Status bit - * @param rtc RTC Instance - * @retval The retval can be one of the following values: - * @arg DISABLE - * @arg ENABLE - */ -__STATIC_INLINE uint32_t md_rtc_get_rif_asec(RTC_TypeDef *rtc) -{ - return (READ_BIT(rtc->RIF, RTC_RIF_ASEC_MSK)>>RTC_RIF_ASEC_POS); -} - -/** - * @brief Get RTC Wakeup Counter Match Interrupt Flag Masked Status bit - * @param rtc RTC Instance - * @retval The retval can be one of the following values: - * @arg DISABLE - * @arg ENABLE - */ -__STATIC_INLINE uint32_t md_rtc_get_ifm_wktm(RTC_TypeDef *rtc) -{ - return (READ_BIT(rtc->IFM, RTC_IFM_WKTM_MSK)>>RTC_IFM_WKTM_POS); -} -/** - * @brief Get RTC 1 Hz Interrupt Flag Masked Status bit - * @param rtc RTC Instance - * @retval The retval can be one of the following values: - * @arg DISABLE - * @arg ENABLE - */ -__STATIC_INLINE uint32_t md_rtc_get_ifm_f1hz(RTC_TypeDef *rtc) -{ - return (READ_BIT(rtc->IFM, RTC_IFM_F1HZ_MSK)>>RTC_IFM_F1HZ_POS); -} -/** - * @brief Get RTC Year Roll Alarm Interrupt Flag Masked Status bit - * @param rtc RTC Instance - * @retval The retval can be one of the following values: - * @arg DISABLE - * @arg ENABLE - */ -__STATIC_INLINE uint32_t md_rtc_get_ifm_ryear(RTC_TypeDef *rtc) -{ - return (READ_BIT(rtc->IFM, RTC_IFM_RYEAR_MSK)>>RTC_IFM_RYEAR_POS); -} -/** - * @brief Get RTC Month Roll Alarm Interrupt Flag Masked Status bit - * @param rtc RTC Instance - * @retval The retval can be one of the following values: - * @arg DISABLE - * @arg ENABLE - */ -__STATIC_INLINE uint32_t md_rtc_get_ifm_rmon(RTC_TypeDef *rtc) -{ - return (READ_BIT(rtc->IFM, RTC_IFM_RMON_MSK)>>RTC_IFM_RMON_POS); -} -/** - * @brief Get RTC Date Roll Alarm Interrupt Flag Masked Status bit - * @param rtc RTC Instance - * @retval The retval can be one of the following values: - * @arg DISABLE - * @arg ENABLE - */ -__STATIC_INLINE uint32_t md_rtc_get_ifm_rdate(RTC_TypeDef *rtc) -{ - return (READ_BIT(rtc->IFM, RTC_IFM_RDATE_MSK)>>RTC_IFM_RDATE_POS); -} -/** - * @brief Get RTC Week Roll Alarm Interrupt Flag Masked Status bit - * @param rtc RTC Instance - * @retval The retval can be one of the following values: - * @arg DISABLE - * @arg ENABLE - */ -__STATIC_INLINE uint32_t md_rtc_get_ifm_rweek(RTC_TypeDef *rtc) -{ - return (READ_BIT(rtc->IFM, RTC_IFM_RWEEK_MSK)>>RTC_IFM_RWEEK_POS); -} -/** - * @brief Get RTC Hour Roll Alarm Interrupt Flag Masked Status bit - * @param rtc RTC Instance - * @retval The retval can be one of the following values: - * @arg DISABLE - * @arg ENABLE - */ -__STATIC_INLINE uint32_t md_rtc_get_ifm_rhour(RTC_TypeDef *rtc) -{ - return (READ_BIT(rtc->IFM, RTC_IFM_RHOUR_MSK)>>RTC_IFM_RHOUR_POS); -} -/** - * @brief Get RTC Minute Roll Alarm Interrupt Flag Masked Status bit - * @param rtc RTC Instance - * @retval The retval can be one of the following values: - * @arg DISABLE - * @arg ENABLE - */ -__STATIC_INLINE uint32_t md_rtc_get_ifm_rmin(RTC_TypeDef *rtc) -{ - return (READ_BIT(rtc->IFM, RTC_IFM_RMIN_MSK)>>RTC_IFM_RMIN_POS); -} -/** - * @brief Get RTC Second Roll Alarm Interrupt Flag Masked Status bit - * @param rtc RTC Instance - * @retval The retval can be one of the following values: - * @arg DISABLE - * @arg ENABLE - */ -__STATIC_INLINE uint32_t md_rtc_get_ifm_rsec(RTC_TypeDef *rtc) -{ - return (READ_BIT(rtc->IFM, RTC_IFM_RSEC_MSK)>>RTC_IFM_RSEC_POS); -} -/** - * @brief Get RTC Match All Alarm Interrupt Flag Masked Status bit - * @param rtc RTC Instance - * @retval The retval can be one of the following values: - * @arg DISABLE - * @arg ENABLE - */ -__STATIC_INLINE uint32_t md_rtc_get_ifm_amall(RTC_TypeDef *rtc) -{ - return (READ_BIT(rtc->IFM, RTC_IFM_AMALL_MSK)>>RTC_IFM_AMALL_POS); -} -/** - * @brief Get RTC Match Year Alarm Interrupt Flag Masked Status bit - * @param rtc RTC Instance - * @retval The retval can be one of the following values: - * @arg DISABLE - * @arg ENABLE - */ -__STATIC_INLINE uint32_t md_rtc_get_ifm_ayear(RTC_TypeDef *rtc) -{ - return (READ_BIT(rtc->IFM, RTC_IFM_AYEAR_MSK)>>RTC_IFM_AYEAR_POS); -} -/** - * @brief Get RTC Match Month Alarm Interrupt Flag Masked Status bit - * @param rtc RTC Instance - * @retval The retval can be one of the following values: - * @arg DISABLE - * @arg ENABLE - */ -__STATIC_INLINE uint32_t md_rtc_get_ifm_amon(RTC_TypeDef *rtc) -{ - return (READ_BIT(rtc->IFM, RTC_IFM_AMON_MSK)>>RTC_IFM_AMON_POS); -} -/** - * @brief Get RTC Match Date Alarm Interrupt Flag Masked Status bit - * @param rtc RTC Instance - * @retval The retval can be one of the following values: - * @arg DISABLE - * @arg ENABLE - */ -__STATIC_INLINE uint32_t md_rtc_get_ifm_adate(RTC_TypeDef *rtc) -{ - return (READ_BIT(rtc->IFM, RTC_IFM_ADTAE_MSK)>>RTC_IFM_ADTAE_POS); -} -/** - * @brief Get RTC Match Week Alarm Interrupt Flag Masked Status bit - * @param rtc RTC Instance - * @retval The retval can be one of the following values: - * @arg DISABLE - * @arg ENABLE - */ -__STATIC_INLINE uint32_t md_rtc_get_ifm_aweek(RTC_TypeDef *rtc) -{ - return (READ_BIT(rtc->IFM, RTC_IFM_AWEEK_MSK)>>RTC_IFM_AWEEK_POS); -} -/** - * @brief Get RTC Match Hour Alarm Interrupt Flag Masked Status bit - * @param rtc RTC Instance - * @retval The retval can be one of the following values: - * @arg DISABLE - * @arg ENABLE - */ -__STATIC_INLINE uint32_t md_rtc_get_ifm_ahour(RTC_TypeDef *rtc) -{ - return (READ_BIT(rtc->IFM, RTC_IFM_AHOUR_MSK)>>RTC_IFM_AHOUR_POS); -} -/** - * @brief Get RTC Match Minute Alarm Interrupt Flag Masked Status bit - * @param rtc RTC Instance - * @retval The retval can be one of the following values: - * @arg DISABLE - * @arg ENABLE - */ -__STATIC_INLINE uint32_t md_rtc_get_ifm_amin(RTC_TypeDef *rtc) -{ - return (READ_BIT(rtc->IFM, RTC_IFM_AMIN_MSK)>>RTC_IFM_AMIN_POS); -} -/** - * @brief Get RTC Match Second Alarm Interrupt Flag Masked Status bit - * @param rtc RTC Instance - * @retval The retval can be one of the following values: - * @arg DISABLE - * @arg ENABLE - */ -__STATIC_INLINE uint32_t md_rtc_get_ifm_asec(RTC_TypeDef *rtc) -{ - return (READ_BIT(rtc->IFM, RTC_IFM_ASEC_MSK)>>RTC_IFM_ASEC_POS); -} - -/** - * @brief Set RTC Wakeup Counter Match Interrupt Clear bit - * @param rtc RTC Instance - * @retval None - */ -__STATIC_INLINE void md_rtc_clear_icr_wktm(RTC_TypeDef *rtc) -{ - SET_BIT(rtc->ICR, RTC_ICR_WKTM_MSK); -} -/** - * @brief Set RTC 1 Hz Interrupt Clear bit - * @param rtc RTC Instance - * @retval None - */ -__STATIC_INLINE void md_rtc_clear_icr_f1hz(RTC_TypeDef *rtc) -{ - SET_BIT(rtc->ICR, RTC_ICR_F1HZ_MSK); -} -/** - * @brief Set RTC Year Roll Alarm Interrupt Clear bit - * @param rtc RTC Instance - * @retval None - */ -__STATIC_INLINE void md_rtc_clear_icr_ryear(RTC_TypeDef *rtc) -{ - SET_BIT(rtc->ICR, RTC_ICR_RYEAR_MSK); -} -/** - * @brief Set RTC Month Roll Alarm Interrupt Clear bit - * @param rtc RTC Instance - * @retval None - */ -__STATIC_INLINE void md_rtc_clear_icr_rmon(RTC_TypeDef *rtc) -{ - SET_BIT(rtc->ICR, RTC_ICR_RMON_MSK); -} -/** - * @brief Set RTC Date Roll Alarm Interrupt Clear bit - * @param rtc RTC Instance - * @retval None - */ -__STATIC_INLINE void md_rtc_clear_icr_rdate(RTC_TypeDef *rtc) -{ - SET_BIT(rtc->ICR, RTC_ICR_RDATE_MSK); -} -/** - * @brief Set RTC Week Roll Alarm Interrupt Clear bit - * @param rtc RTC Instance - * @retval None - */ -__STATIC_INLINE void md_rtc_clear_icr_rweek(RTC_TypeDef *rtc) -{ - SET_BIT(rtc->ICR, RTC_ICR_RWEEK_MSK); -} -/** - * @brief Set RTC Hour Roll Alarm Interrupt Clear bit - * @param rtc RTC Instance - * @retval None - */ -__STATIC_INLINE void md_rtc_clear_icr_rhour(RTC_TypeDef *rtc) -{ - SET_BIT(rtc->ICR, RTC_ICR_RHOUR_MSK); -} -/** - * @brief Set RTC Minute Roll Alarm Interrupt Clear bit - * @param rtc RTC Instance - * @retval None - */ -__STATIC_INLINE void md_rtc_clear_icr_rmin(RTC_TypeDef *rtc) -{ - SET_BIT(rtc->ICR, RTC_ICR_RMIN_MSK); -} -/** - * @brief Set RTC Second Roll Alarm Interrupt Clear bit - * @param rtc RTC Instance - * @retval None - */ -__STATIC_INLINE void md_rtc_clear_icr_rsec(RTC_TypeDef *rtc) -{ - SET_BIT(rtc->ICR, RTC_ICR_RSEC_MSK); -} -/** - * @brief Set RTC Match All Alarm Interrupt Clear bit - * @param rtc RTC Instance - * @retval None - */ -__STATIC_INLINE void md_rtc_clear_icr_amall(RTC_TypeDef *rtc) -{ - SET_BIT(rtc->ICR, RTC_ICR_AMALL_MSK); -} -/** - * @brief Set RTC Match Year Alarm Interrupt Clear bit - * @param rtc RTC Instance - * @retval None - */ -__STATIC_INLINE void md_rtc_clear_icr_ayear(RTC_TypeDef *rtc) -{ - SET_BIT(rtc->ICR, RTC_ICR_AYEAR_MSK); -} -/** - * @brief Set RTC Match Month Alarm Interrupt Clear bit - * @param rtc RTC Instance - * @retval None - */ -__STATIC_INLINE void md_rtc_clear_icr_amon(RTC_TypeDef *rtc) -{ - SET_BIT(rtc->ICR, RTC_ICR_AMON_MSK); -} -/** - * @brief Set RTC Match Date Alarm Interrupt Clear bit - * @param rtc RTC Instance - * @retval None - */ -__STATIC_INLINE void md_rtc_clear_icr_adate(RTC_TypeDef *rtc) -{ - SET_BIT(rtc->ICR, RTC_ICR_ADTAE_MSK); -} -/** - * @brief Set RTC Match Week Alarm Interrupt Clear bit - * @param rtc RTC Instance - * @retval None - */ -__STATIC_INLINE void md_rtc_clear_icr_aweek(RTC_TypeDef *rtc) -{ - SET_BIT(rtc->ICR, RTC_ICR_AWEEK_MSK); -} -/** - * @brief Set RTC Match Hour Alarm Interrupt Clear bit - * @param rtc RTC Instance - * @retval None - */ -__STATIC_INLINE void md_rtc_clear_icr_ahour(RTC_TypeDef *rtc) -{ - SET_BIT(rtc->ICR, RTC_ICR_AHOUR_MSK); -} -/** - * @brief Set RTC Match Minute Alarm Interrupt Clear bit - * @param rtc RTC Instance - * @retval None - */ -__STATIC_INLINE void md_rtc_clear_icr_amin(RTC_TypeDef *rtc) -{ - SET_BIT(rtc->ICR, RTC_ICR_AMIN_MSK); -} -/** - * @brief Set RTC Match Second Alarm Interrupt Clear bit - * @param rtc RTC Instance - * @retval None - */ -__STATIC_INLINE void md_rtc_clear_icr_asec(RTC_TypeDef *rtc) -{ - SET_BIT(rtc->ICR, RTC_ICR_ASEC_MSK); -} - -/** - * @brief Get RTC Calendar Synchronization status bit - * @param rtc RTC Instance - * @retval The retval can be one of the following values: - * @arg @ref MD_RTC_STAT_SYNDONE_UNDER - * @arg @ref MD_RTC_STAT_SYNDONE_CMP - */ -__STATIC_INLINE uint32_t md_rtc_get_stat_syndone(RTC_TypeDef *rtc) -{ - return (READ_BIT(rtc->STAT, RTC_STAT_SYNDONE_MSK)>>RTC_STAT_SYNDONE_POS); -} -/** - * @brief Get RTC Calendar Status bit - * @param rtc RTC Instance - * @retval State of bit (1 or 0). - * @note 0 = RTC calendar is not empty - * 1 = RTC calendar is empty - */ -__STATIC_INLINE uint32_t md_rtc_get_stat_empty(RTC_TypeDef *rtc) -{ - return (READ_BIT(rtc->STAT, RTC_STAT_EMPTY_MSK)>>RTC_STAT_EMPTY_POS); -} - -/** - * @brief Set Read RTC Backup Register Enable bit - * @param rtc RTC Instance - * @param bken can be one of the following values: - * @arg @ref MD_RTC_BKEN_BKEN_CONTROL - * @arg @ref MD_RTC_BKEN_BKEN_BACKUP - * @retval None - */ -__STATIC_INLINE void md_rtc_set_bken_bken(RTC_TypeDef *rtc, uint32_t bken) -{ - MODIFY_REG(rtc->BKEN, RTC_BKEN_BKEN_MSK, (bken<BKEN, RTC_BKEN_BKEN_MSK)>>RTC_BKEN_BKEN_POS); -} - -/** - * @} MD_RTC_Public_Macros - */ - -/* Public functions -----------------------------------------------------------*/ -/** @defgroup MD_RTC_Public_Functions RTC Public Functions - * @{ - */ - -/** @defgroup MD_RTC_PF_Basic_Configuration Basic Configuration - * @{ - */ - -/** - * @} MD_RTC_PF_Basic_Configuration - */ - -/** @defgroup MD_RTC_PF_Data_Access Data Access - * @{ - */ - -/** - * @} MD_RTC_PF_Data_Access - */ - -/** @defgroup MD_RTC_PF_Init Initialization and de-initialization functions - * @{ - */ - -/** - * @} MD_RTC_PF_Init - */ - -/** - * @} MD_RTC_Public_Functions - */ - -#endif - -/** - * @} RTC - */ - -/** - * @} Micro_Driver - */ - - -#ifdef __cplusplus -} - -#endif - -#endif - -/******************* (C) COPYRIGHT Eastsoft Microelectronics *****END OF FILE****/ diff --git a/bsp/essemi/es32f0271/libraries/ES32F027x_MD_StdPeriph_Driver/Include/md_spi.h b/bsp/essemi/es32f0271/libraries/ES32F027x_MD_StdPeriph_Driver/Include/md_spi.h deleted file mode 100644 index 74f01e6312..0000000000 --- a/bsp/essemi/es32f0271/libraries/ES32F027x_MD_StdPeriph_Driver/Include/md_spi.h +++ /dev/null @@ -1,2523 +0,0 @@ -/** - ****************************************************************************** - * @file md_spi.h - * @brief ES32F0271 SPI Head File. - * - * @version V1.00.01 - * @date 06/11/2018 - * @author Eastsoft AE Team - * @note - * detailed description - * - * Copyright (C) 2018 Shanghai Eastsoft Microelectronics Co., Ltd. ALL rights reserved. - ******************************************************************************* - */ - -/* Define to prevent recursive inclusion -------------------------------------*/ -#ifndef __MD_SPI_H__ -#define __MD_SPI_H__ - -#ifdef __cplusplus -extern "C" { -#endif - -/* Includes -------------------------------------------------------------------*/ -#include "es32f0271.h" -#include "reg_spi.h" - -/** @addtogroup Micro_Driver - * @{ - */ - -#if defined (SPI1) || defined (SPI2) - -/** @defgroup SPI SPI - * @brief SPI micro driver - * @{ - */ - -/* Private types --------------------------------------------------------------*/ -/* Private variables ----------------------------------------------------------*/ -/* Private macros -------------------------------------------------------------*/ - -/* Public types ---------------------------------------------------------------*/ -/** @defgroup MD_SPI_Public_Types SPI Public Types - * @{ - */ - -/** @defgroup MD_SPI_PT_INIT SPI Public Init structure - * @{ - */ - -/** - * @brief SPI Init structure. - */ -typedef struct -{ - uint32_t Mode; /*!< Specifies the SPI mode (Master/Slave). - This parameter can be a value of @ref MD_SPI_PC_MODE. - - This feature can be modified afterwards using unitary function @ref md_spi_set_con1_mstren().*/ - - uint32_t ClockPhase; /*!< Specifies the clock active edge for the bit capture. - This parameter can be a value of @ref MD_SPI_PC_PHASE. - - This feature can be modified afterwards using unitary function @ref md_spi_set_con1_cpha().*/ - - uint32_t ClockPolarity; /*!< Specifies the serial clock steady state. - This parameter can be a value of @ref MD_SPI_PC_POLARITY. - - This feature can be modified afterwards using unitary function @ref md_spi_get_con1_cpol().*/ - - uint32_t BaudRate; /*!< Specifies the BaudRate prescaler value which will be used to configure the transmit and receive SCK clock. - This parameter can be a value of @ref MD_SPI_PC_BAUDRATEPRESCALER. - @note The communication clock is derived from the master clock. The slave clock does not need to be set. - - This feature can be modified afterwards using unitary function @ref md_spi_set_con1_baud().*/ - - uint32_t BitOrder; /*!< Specifies whether data transfers start from MSB or LSB bit. - This parameter can be a value of @ref MD_SPI_PC_BIT_ORDER. - - This feature can be modified afterwards using unitary function @ref md_spi_set_con1_lsbfirst().*/ - - uint32_t TransferDirection; /*!< Specifies the SPI unidirectional or bidirectional data mode. - This parameter can be a value of @ref MD_SPI_PC_TRANSFER_DIRECTION. - - This feature can be modified afterwards using unitary function @ref md_spi_set_con1_bidimode().*/ - - uint32_t DataWidth; /*!< Specifies the SPI data width. - This parameter can be a value of @ref MD_SPI_PC_FRAME_FORMAT. - - This feature can be modified afterwards using unitary function @ref md_spi_set_con1_dlen().*/ - - uint32_t NSS; /*!< Specifies whether the NSS signal is managed by hardware (NSS pin) or by software using the SSI bit. - This parameter can be a value of @ref MD_SPI_PC_NSS_MODE. - - This feature can be modified afterwards using unitary function @ref md_spi_set_con1_ssout().*/ - - uint32_t CRCCalculation; /*!< Specifies if the CRC calculation is enabled or not. - This parameter can be a value of @ref MD_SPI_EC_CRC_CALCULATION. - - This feature can be modified afterwards using unitary functions @ref md_spi_enable_con1_crcen() and @ref md_spi_disable_con1_crcen().*/ - - uint32_t CRCPoly; /*!< Specifies the polynomial used for the CRC calculation. - This parameter must be a number between Min_Data = 0x00 and Max_Data = 0xFFFF. - - This feature can be modified afterwards using unitary function.*/ - -} md_spi_inittypedef; - - - - -/** - * @} MD_SPI_PT_INIT - */ - -/** - * @} MD_SPI_Public_Types - */ - -/* Public constants -----------------------------------------------------------*/ -/** @defgroup MD_SPI_Public_Constants SPI Public Constants - * @{ - */ - -/** @defgroup MD_SPI_PC_MODE SPI Operation Mode - * @{ - */ -#define MD_SPI_MODE_SLAVE 0x00000000U /*!< Slave configuration */ -#define MD_SPI_MODE_MASTER (SPI_CON1_MSTREN_MSK) /*!< Master configuration */ -/** - * @} MD_SPI_PC_MODE - */ - -/** @defgroup MD_SPI_PC_PROTOCOL SPI Serial Protocol - * @{ - */ -#define MD_SPI_PROTOCOL_MOTOROLA 0x00000000U /*!< Motorola mode. Used as default value */ -#define MD_SPI_PROTOCOL_TI (SPI_CON2_FRF_MSK) /*!< TI mode */ -/** - * @} MD_SPI_PC_PROTOCOL - */ - -/** @defgroup MD_SPI_PC_PHASE SPI Clock Phase - * @{ - */ -#define MD_SPI_PHASE_1EDGE 0x00000000U /*!< First clock transition is the first data capture edge */ -#define MD_SPI_PHASE_2EDGE (SPI_CON1_CPHA_MSK) /*!< Second clock transition is the first data capture edge */ -/** - * @} MD_SPI_PC_PHASE - */ - -/** @defgroup MD_SPI_PC_POLARITY SPI Clock Polarity - * @{ - */ -#define MD_SPI_POLARITY_LOW 0x00000000U /*!< Clock to 0 when idle */ -#define MD_SPI_POLARITY_HIGH (SPI_CON1_CPOL_MSK) /*!< Clock to 1 when idle */ -/** - * @} MD_SPI_PC_POLARITY - */ - -/** @defgroup MD_SPI_PC_BAUDRATEPRESCALER SPI Baud Rate Prescaler - * @{ - */ -#define MD_SPI_BAUDRATEPRESCALER_DIV2 0x00000000U /*!< BaudRate control equal to fPCLK/2 */ -#define MD_SPI_BAUDRATEPRESCALER_DIV4 (0x1U<CON1, value); -} - -/** - * @brief Get SPI control register (SPIx_CON1) - * @param SPIx SPI Instance - * @retval None - */ -__STATIC_INLINE uint32_t md_spi_get_con1(SPI_TypeDef *SPIx) -{ - return (uint32_t)(READ_REG(SPIx->CON1)); -} - -/** - - * @brief Set SPI clock phase - * @note This bit should not be changed when communication is ongoing. \n - This bit is not used in SPI TI mode. - * @param SPIx SPI Instance - * @param ClockPhase This parameter can be one of the following values: - * @arg @ref MD_SPI_PHASE_1EDGE - * @arg @ref MD_SPI_PHASE_2EDGE - * @retval None - - */ -__STATIC_INLINE void md_spi_set_con1_cpha(SPI_TypeDef *SPIx, uint32_t ClockPhase) -{ - MODIFY_REG(SPIx->CON1, SPI_CON1_CPHA_MSK, ClockPhase); -} - -/** - * @brief Get SPI clock phase - * @param SPIx SPI Instance - * @retval Returned value can be one of the following values: - * @arg @ref MD_SPI_PHASE_1EDGE - * @arg @ref MD_SPI_PHASE_2EDGE - */ -__STATIC_INLINE uint32_t md_spi_get_con1_cpha(SPI_TypeDef *SPIx) -{ - return (uint32_t)(READ_BIT(SPIx->CON1, SPI_CON1_CPHA_MSK)>>SPI_CON1_CPHA_POS); -} - -/** - * @brief Set SPI clock polarity - * @note This bit should not be changed when communication is ongoing. - * This bit is not used in SPI TI mode. - * @param SPIx SPI Instance - * @param ClockPolarity This parameter can be one of the following values: - * @arg @ref MD_SPI_POLARITY_LOW - * @arg @ref MD_SPI_POLARITY_HIGH - * @retval None - */ -__STATIC_INLINE void md_spi_set_con1_cpol(SPI_TypeDef *SPIx, uint32_t ClockPolarity) -{ - MODIFY_REG(SPIx->CON1, SPI_CON1_CPOL_MSK, ClockPolarity); -} - -/** - * @brief Get SPI clock polarity - * @param SPIx SPI Instance - * @retval Returned value can be one of the following values: - * @arg @ref MD_SPI_POLARITY_LOW - * @arg @ref MD_SPI_POLARITY_HIGH - */ -__STATIC_INLINE uint32_t md_spi_get_con1_cpol(SPI_TypeDef *SPIx) -{ - return (uint32_t)(READ_BIT(SPIx->CON1, SPI_CON1_CPOL_MSK)>>SPI_CON1_CPOL_POS); -} - -/** - * @brief Set SPI master selection - * @note This bit should not be changed when communication is ongoing. - * @param SPIx SPI Instance - * @param Mode This parameter can be one of the following values: - * @arg @ref MD_SPI_MODE_MASTER - * @arg @ref MD_SPI_MODE_SLAVE - * @retval None - */ -__STATIC_INLINE void md_spi_set_con1_mstren(SPI_TypeDef *SPIx, uint32_t Mode) -{ - MODIFY_REG(SPIx->CON1, SPI_CON1_MSTREN_MSK, Mode); -} - -/** - * @brief Get SPI SPI operation mode (Master or Slave) - * @param SPIx SPI Instance - * @retval Returned value can be one of the following values: - * @arg @ref MD_SPI_MODE_MASTER - * @arg @ref MD_SPI_MODE_SLAVE - */ -__STATIC_INLINE uint32_t md_spi_get_con1_mstren(SPI_TypeDef *SPIx) -{ - return (uint32_t)(READ_BIT(SPIx->CON1, SPI_CON1_MSTREN_MSK )>>SPI_CON1_MSTREN_POS); -} - -/** - * @brief Set SPI baud rate control - * @note These bits should not be changed when communication is ongoing. SPI BaudRate = fPCLK/Prescaler. - * @param SPIx SPI Instance - * @param BaudRate This parameter can be one of the following values: - * @arg @ref MD_SPI_BAUDRATEPRESCALER_DIV2 - * @arg @ref MD_SPI_BAUDRATEPRESCALER_DIV4 - * @arg @ref MD_SPI_BAUDRATEPRESCALER_DIV8 - * @arg @ref MD_SPI_BAUDRATEPRESCALER_DIV16 - * @arg @ref MD_SPI_BAUDRATEPRESCALER_DIV32 - * @arg @ref MD_SPI_BAUDRATEPRESCALER_DIV64 - * @arg @ref MD_SPI_BAUDRATEPRESCALER_DIV128 - * @arg @ref MD_SPI_BAUDRATEPRESCALER_DIV256 - * @retval None - */ -__STATIC_INLINE void md_spi_set_con1_baud(SPI_TypeDef *SPIx, uint32_t BaudRate) -{ - MODIFY_REG(SPIx->CON1, SPI_CON1_BAUD_MSK, BaudRate); -} - -/** - * @brief Get SPI baud rate prescaler - * @param SPIx SPI Instance - * @retval Returned value can be one of the following values: - * @arg @ref MD_SPI_BAUDRATEPRESCALER_DIV2 - * @arg @ref MD_SPI_BAUDRATEPRESCALER_DIV4 - * @arg @ref MD_SPI_BAUDRATEPRESCALER_DIV8 - * @arg @ref MD_SPI_BAUDRATEPRESCALER_DIV16 - * @arg @ref MD_SPI_BAUDRATEPRESCALER_DIV32 - * @arg @ref MD_SPI_BAUDRATEPRESCALER_DIV64 - * @arg @ref MD_SPI_BAUDRATEPRESCALER_DIV128 - * @arg @ref MD_SPI_BAUDRATEPRESCALER_DIV256 - */ -__STATIC_INLINE uint32_t md_spi_get_con1_baud(SPI_TypeDef *SPIx) -{ - return (uint32_t)(READ_BIT(SPIx->CON1, SPI_CON1_BAUD_MSK)>>SPI_CON1_BAUD_POSS); -} - -/** - * @brief Enable SPI peripheral - * @param SPIx SPI Instance - * @retval None - */ -__STATIC_INLINE void md_spi_enable_con1_spien(SPI_TypeDef *SPIx) -{ - SET_BIT(SPIx->CON1, SPI_CON1_SPIEN_MSK); -} - -/** - * @brief Disable SPI peripheral - * @note When disabling the SPI, follow the procedure described in the Reference Manual. - * @param SPIx SPI Instance - * @retval None - */ -__STATIC_INLINE void md_spi_disable_con1_spien(SPI_TypeDef *SPIx) -{ - CLEAR_BIT(SPIx->CON1, SPI_CON1_SPIEN_MSK); -} - -/** - * @brief Check if SPI peripheral is enabled - * @param SPIx SPI Instance - * @retval State of bit (1 or 0). - */ -__STATIC_INLINE uint32_t md_spi_is_enable_con1_spien(SPI_TypeDef *SPIx) -{ - return (READ_BIT(SPIx->CON1, SPI_CON1_SPIEN_MSK) == (SPI_CON1_SPIEN_MSK)); -} - -/** - * @brief Set SPI frame format - * @note This bit should not be changed when communication is ongoing. This bit is not used in SPI TI mode. - * @param SPIx SPI Instance - * @param BitOrder This parameter can be one of the following values: - * @arg @ref MD_SPI_LSB_FIRST - * @arg @ref MD_SPI_MSB_FIRST - * @retval None - */ -__STATIC_INLINE void md_spi_set_con1_lsbfirst(SPI_TypeDef *SPIx, uint32_t BitOrder) -{ - MODIFY_REG(SPIx->CON1, SPI_CON1_LSBFST_MSK, BitOrder); -} - -/** - * @brief Get SPI transfer bit order - * @param SPIx SPI Instance - * @retval Returned value can be one of the following values: - * @arg @ref MD_SPI_LSB_FIRST - * @arg @ref MD_SPI_MSB_FIRST - */ -__STATIC_INLINE uint32_t md_spi_get_con1_lsbfirst(SPI_TypeDef *SPIx) -{ - return (uint32_t)(READ_BIT(SPIx->CON1, SPI_CON1_LSBFST_MSK)>>SPI_CON1_LSBFST_POS); -} - -/** - * @brief Set SPI Internal slave select - * @note This bit has an effect only when the SSEN bit is set. The value of this bit is forced onto the NSS pin. - * @param SPIx SPI Instance - * @param value This bit can be set to: - * @arg BIT_SET - * @arg BIT_RESET - * @retval None - */ -__STATIC_INLINE void md_spi_set_con1_ssout(SPI_TypeDef *SPIx, uint32_t value) -{ - MODIFY_REG(SPIx->CON1, SPI_CON1_SSOUT_MSK , value); -} - -/** - * @brief Get SPI Internal slave select - * @param SPIx SPI Instance - * @retval State of 1 or 0 - */ -__STATIC_INLINE uint32_t md_spi_get_con1_ssout(SPI_TypeDef *SPIx) -{ - return (uint32_t)(READ_BIT(SPIx->CON1, SPI_CON1_SSOUT_MSK)>>SPI_CON1_SSOUT_POS); -} - -/** - * @brief Enable SPI software slave management - * @note When the SSEN bit is set, the NSS pin input is replaced with the value from the SSOUT bit. - * @param SPIx SPI Instance - * @retval None - */ -__STATIC_INLINE void md_spi_enable_con1_ssen(SPI_TypeDef *SPIx) -{ - SET_BIT(SPIx->CON1, SPI_CON1_SSEN_MSK); -} - -/** - * @brief Disable SPI software slave management - * @param SPIx SPI Instance - * @retval None - */ -__STATIC_INLINE void md_spi_disable_con1_ssen(SPI_TypeDef *SPIx) -{ - CLEAR_BIT(SPIx->CON1, SPI_CON1_SSEN_MSK); -} - -/** - * @brief Check if SPI peripheral is software slave management - * @param SPIx SPI Instance - * @retval State of bit (1 or 0). - */ -__STATIC_INLINE uint32_t md_spi_is_enable_con1_ssen(SPI_TypeDef *SPIx) -{ - return (READ_BIT(SPIx->CON1, SPI_CON1_SSEN_MSK) == (SPI_CON1_SSEN_MSK)); -} - -/** - * @brief Set SPI receive only mode enable - * @note This bit enables simplex communication using a single unidirectional line to receive data exclusively. \n - Keep BIDEN bit clear when receive only mode is active.This bit is also useful in a multislave system \n - in which this particular slave is not accessed, the output from the accessed slave is not corrupted. - * @param SPIx SPI Instance - * @param value This bit can be set to: - * @arg BIT_SET - * @arg BIT_RESET - * @retval None - */ -__STATIC_INLINE void md_spi_set_con1_rxo(SPI_TypeDef *SPIx, uint32_t value) -{ - MODIFY_REG(SPIx->CON1, SPI_CON1_RXO_MSK , value); -} - -/** - * @brief Set SPI receive only mode enable - * @param SPIx SPI Instance - * @retval State of 1 or 0 - */ -__STATIC_INLINE uint32_t md_spi_get_con1_rxo(SPI_TypeDef *SPIx) -{ - return (uint32_t)(READ_BIT(SPIx->CON1, SPI_CON1_RXO_MSK)>>SPI_CON1_RXO_POS); -} - -/** - * @brief Set data frame format - * @param SPIx SPI Instance - * @param DataWidth This parameter can be one of the following values: - * @arg @ref MD_SPI_FRAME_FORMAT_8BIT - * @arg @ref MD_SPI_FRAME_FORMAT_16BIT - * @retval None - */ -__STATIC_INLINE void md_spi_set_con1_flen(SPI_TypeDef *SPIx, uint32_t DataWidth) -{ - MODIFY_REG(SPIx->CON1, SPI_CON1_FLEN_MSK, DataWidth); -} - -/** - * @brief Get data frame format - * @param SPIx SPI Instance - * @retval Returned value can be one of the following values: - * @arg @ref MD_SPI_FRAME_FORMAT_8BIT - * @arg @ref MD_SPI_FRAME_FORMAT_16BIT - */ -__STATIC_INLINE uint32_t md_spi_get_con1_flen(SPI_TypeDef *SPIx) -{ - return (uint32_t)(READ_BIT(SPIx->CON1, SPI_CON1_FLEN_MSK)>>SPI_CON1_FLEN_POS); -} - -/** - * @brief Set CRCNext to transfer CRC on the line - * @note This bit has to be written as soon as the last data is written in the SPIx_DATA register. - * @param SPIx SPI Instance - * @param value This bit can be set to: - * @arg BIT_SET - * @arg BIT_RESET - * @retval None - */ -__STATIC_INLINE void md_spi_set_con1_crcnext(SPI_TypeDef *SPIx, uint32_t value) -{ - MODIFY_REG(SPIx->CON1, SPI_CON1_NXTCRC_MSK, value); -} - -/** - * @brief Get CRCNext to transfer CRC on the line - * @param SPIx SPI Instance - * @retval Returned value can be one of the following values: - * @retval State of 1 or 0 - */ -__STATIC_INLINE uint32_t md_spi_get_con1_crcnext(SPI_TypeDef *SPIx) -{ - return (uint32_t)(READ_BIT(SPIx->CON1, SPI_CON1_NXTCRC_MSK)>>SPI_CON1_NXTCRC_POS); -} - -/** - * @brief Enable SPI hardware CRC calculation - * @param SPIx SPI Instance - * @retval None - */ -__STATIC_INLINE void md_spi_enable_con1_crcen(SPI_TypeDef *SPIx) -{ - SET_BIT(SPIx->CON1, SPI_CON1_CRCEN_MSK); -} - -/** - * @brief Disable SPI hardware CRC calculation - * @note When disabling the SPI, follow the procedure described in the Reference Manual. - * @param SPIx SPI Instance - * @retval None - */ -__STATIC_INLINE void md_spi_disable_con1_crcen(SPI_TypeDef *SPIx) -{ - CLEAR_BIT(SPIx->CON1, SPI_CON1_CRCEN_MSK); -} - -/** - * @brief Check if hardware CRC calculation is enabled - * @param SPIx SPI Instance - * @retval State of bit (1 or 0). - */ -__STATIC_INLINE uint32_t md_spi_is_enable_con1_crcen(SPI_TypeDef *SPIx) -{ - return (READ_BIT(SPIx->CON1, SPI_CON1_CRCEN_MSK) == (SPI_CON1_CRCEN_MSK)); -} - -/** - * @brief Enable SPI Output enable in bidirectional mode - * @note Output enable in bidirectional mode. This bit combined with the BIDEN bit selects the direction of \n - transfer in bidirectional mode - * @param SPIx SPI Instance - * @retval None - */ -__STATIC_INLINE void md_spi_enable_con1_bidoen(SPI_TypeDef *SPIx) -{ - SET_BIT(SPIx->CON1, SPI_CON1_BIDOEN_MSK); -} - -/** - * @brief Disable Output enable in bidirectional mode - * @param SPIx SPI Instance - * @retval None - */ -__STATIC_INLINE void md_spi_disable_con1_bidoen(SPI_TypeDef *SPIx) -{ - CLEAR_BIT(SPIx->CON1, SPI_CON1_BIDOEN_MSK); -} - -/** - * @brief Check if Output enable in bidirectional mode is enabled - * @param SPIx SPI Instance - * @retval State of bit (1 or 0). - */ -__STATIC_INLINE uint32_t md_spi_is_enable_con1_bidoen(SPI_TypeDef *SPIx) -{ - return (READ_BIT(SPIx->CON1, SPI_CON1_BIDOEN_MSK) == (SPI_CON1_BIDOEN_MSK)); -} - -/** - * @brief Set Bidirectional data mode enable - * @note Bidirectional data mode enable. This bit enables half-duplex communication using common single bidirectional \n - data line. Keep RXO bit clear when bidirectional mode is active. - * @param SPIx SPI Instance - * @param value This bit can be set to: - * @arg @ref MD_SPI_FULL_DUPLEX - * @arg @ref MD_SPI_HALF_DUPLEX - * @retval None - */ -__STATIC_INLINE void md_spi_set_con1_bidimode(SPI_TypeDef *SPIx, uint32_t value) -{ - MODIFY_REG(SPIx->CON1, SPI_CON1_BIDEN_MSK, value); -} - -/** - * @brief Get Bidirectional data mode enable - * @param SPIx SPI Instance - * @retval Returned value can be one of the following values: - * @retval Return follow: - * @arg @ref MD_SPI_FULL_DUPLEX - * @arg @ref MD_SPI_HALF_DUPLEX - */ -__STATIC_INLINE uint32_t md_spi_get_con1_bidimode(SPI_TypeDef *SPIx) -{ - return (uint32_t)(READ_BIT(SPIx->CON1, SPI_CON1_BIDEN_MSK)>>SPI_CON1_BIDEN_POS); -} - - -/** - * @} MD_SPI_CON1 - */ - - - -/** @defgroup MD_SPI_CON2 SPI Control Register 2 - * @{ - */ - -/** - * @brief Set SPI control register 2 (SPIx_CON2) - * @param SPIx SPI Instance - * @param value The value write in SPIx_CON2 - * @retval None - */ -__STATIC_INLINE void md_spi_set_con2(SPI_TypeDef *SPIx, uint32_t value) -{ - WRITE_REG(SPIx->CON2, value); -} - -/** - * @brief Get SPI control register 2(SPIx_CON2) - * @param SPIx SPI Instance - * @retval None - */ -__STATIC_INLINE uint32_t md_spi_get_con2(SPI_TypeDef *SPIx) -{ - return (uint32_t)(READ_REG(SPIx->CON2)); -} - - -/** - * @brief Enable Rx buffer DMA - * @note When this bit is set, a DMA request is generated whenever the RXTH flag is set. - * @param SPIx SPI Instance - * @retval None - */ -__STATIC_INLINE void md_spi_enable_con2_rxdmaen(SPI_TypeDef *SPIx) -{ - SET_BIT(SPIx->CON2, SPI_CON2_RXDMA_MSK); -} - -/** - * @brief Disable Rx buffer DMA - * @param SPIx SPI Instance - * @retval None - */ -__STATIC_INLINE void md_spi_disable_con2_rxdmaen(SPI_TypeDef *SPIx) -{ - CLEAR_BIT(SPIx->CON2, SPI_CON2_RXDMA_MSK); -} - -/** - * @brief Check if Rx buffer DMA is enabled - * @param SPIx SPI Instance - * @retval State of bit (1 or 0). - */ -__STATIC_INLINE uint32_t md_spi_is_enabled_con2_rxdmaen(SPI_TypeDef *SPIx) -{ - return (READ_BIT(SPIx->CON2, SPI_CON2_RXDMA_MSK) == (SPI_CON2_RXDMA_MSK)); -} - -/** - * @brief Enable Tx buffer DMA enable - * @note When this bit is set, a DMA request is generated whenever the TXTH flag is set. - * @param SPIx SPI Instance - * @retval None - */ -__STATIC_INLINE void md_spi_enable_con2_txdmaen(SPI_TypeDef *SPIx) -{ - SET_BIT(SPIx->CON2, SPI_CON2_TXDMA_MSK); -} - -/** - * @brief Disable Tx buffer DMA enable - * @param SPIx SPI Instance - * @retval None - */ -__STATIC_INLINE void md_spi_disable_con2_txdmaen(SPI_TypeDef *SPIx) -{ - CLEAR_BIT(SPIx->CON2, SPI_CON2_TXDMA_MSK); -} - -/** - * @brief Check if Tx buffer DMA enable is enabled - * @param SPIx SPI Instance - * @retval State of bit (1 or 0). - */ -__STATIC_INLINE uint32_t md_spi_is_enabled_con2_txdmaen(SPI_TypeDef *SPIx) -{ - return (READ_BIT(SPIx->CON2, SPI_CON2_TXDMA_MSK) == (SPI_CON2_TXDMA_MSK)); -} - -/** - * @brief Enable SS output enable - * @note SS output is enabled in master mode and when the SPI interface is enabled. The SPI interface cannot \n - work in a multimaster environment. - * @param SPIx SPI Instance - * @retval None - */ -__STATIC_INLINE void md_spi_enable_con2_ssoe(SPI_TypeDef *SPIx) -{ - SET_BIT(SPIx->CON2, SPI_CON2_NSSOE_MSK); -} - -/** - * @brief Disable SS output enable - * @param SPIx SPI Instance - * @retval None - */ -__STATIC_INLINE void md_spi_disable_con2_ssoe(SPI_TypeDef *SPIx) -{ - CLEAR_BIT(SPIx->CON2, SPI_CON2_NSSOE_MSK); -} - -/** - * @brief Check if SS output enable is enabled - * @param SPIx SPI Instance - * @retval State of bit (1 or 0). - */ -__STATIC_INLINE uint32_t md_spi_is_enabled_con2_ssoe(SPI_TypeDef *SPIx) -{ - return (READ_BIT(SPIx->CON2, SPI_CON2_NSSOE_MSK) == (SPI_CON2_NSSOE_MSK)); -} - -/** - * @brief Enable NSS pulse management - * @note This bit is used in master mode only. It allow the SPI to generate an NSS pulse between two consecutive \n - data when doing continuous transfers. In the case of a single data transfer, it forces the NSS pin high \n - level after the transfer. It has no meaning if CPHA = ’1’, or FRF = ’1’.This bit should not be changed \n - when communication is ongoing. This bit is not used in SPI TI mode. - * @param SPIx SPI Instance - * @retval None - */ -__STATIC_INLINE void md_spi_enable_con2_nssp(SPI_TypeDef *SPIx) -{ - SET_BIT(SPIx->CON2, SPI_CON2_NSSP_MSK); -} - -/** - * @brief Disable NSS pulse management - * @note This bit should not be changed when communication is ongoing. This bit is not used in SPI TI mode. - * @param SPIx SPI Instance - * @retval None - */ -__STATIC_INLINE void md_spi_disable_con2_nssp(SPI_TypeDef *SPIx) -{ - CLEAR_BIT(SPIx->CON2, SPI_CON2_NSSP_MSK); -} - -/** - * @brief Check if NSS pulse is enabled - * @note This bit should not be changed when communication is ongoing. This bit is not used in SPI TI mode. - * @param SPIx SPI Instance - * @retval State of bit (1 or 0). - */ -__STATIC_INLINE uint32_t md_spi_is_enabled_con2_nssp(SPI_TypeDef *SPIx) -{ - return (READ_BIT(SPIx->CON2, SPI_CON2_NSSP_MSK) == (SPI_CON2_NSSP_MSK)); -} - -/** - * @brief Set frame format - * @note This bit should be written only when SPI is disabled (SPE = 0) for correct operation. - * @param SPIx SPI Instance - * @param Standard This parameter can be one of the following values: - * @arg @ref MD_SPI_PROTOCOL_MOTOROLA - * @arg @ref MD_SPI_PROTOCOL_TI - * @retval None - */ -__STATIC_INLINE void md_spi_set_con2_frf(SPI_TypeDef *SPIx, uint32_t Standard) -{ - MODIFY_REG(SPIx->CON2, SPI_CON2_FRF_MSK, Standard); -} - -/** - * @brief Get frame format - * @param SPIx SPI Instance - * @retval Returned value can be one of the following values: - * @arg @ref MD_SPI_PROTOCOL_MOTOROLA - * @arg @ref MD_SPI_PROTOCOL_TI - */ -__STATIC_INLINE uint32_t md_spi_get_con2_frf(SPI_TypeDef *SPIx) -{ - return (uint32_t)(READ_BIT(SPIx->CON2, SPI_CON2_FRF_MSK)>>SPI_CON2_FRF_POS); -} - - -/** - * @brief Set transmit FIFO trigger threshold - * @note This is used to select the threshold level in the transmit FIFO at which the Transmit FIFO \n - trigger threshold flag is generated. - * @param SPIx SPI Instance - * @param Threshold This parameter can be one of the following values: - * @arg @ref MD_SPI_TX_FIFO_TH_0BIT - * @arg @ref MD_SPI_TX_FIFO_TH_2BIT - * @arg @ref MD_SPI_TX_FIFO_TH_4BIT - * @arg @ref MD_SPI_TX_FIFO_TH_8BIT - * @retval None - */ -__STATIC_INLINE void md_spi_set_con2_txfth(SPI_TypeDef *SPIx, uint32_t Threshold) -{ - MODIFY_REG(SPIx->CON2, SPI_CON2_TXFTH_MSK, Threshold<CON2, SPI_CON2_TXFTH_MSK)>>SPI_CON2_TXFTH_POSS); -} - -/** - * @brief Set receive FIFO trigger threshold - * @note This is used to select the threshold level in the receiver FIFO at which the Receive FIFO \n - trigger threshold flag is generated. - * @param SPIx SPI Instance - * @param Threshold This parameter can be one of the following values: - * @arg @ref MD_SPI_RX_FIFO_TH_1BIT - * @arg @ref MD_SPI_RX_FIFO_TH_4BIT - * @arg @ref MD_SPI_RX_FIFO_TH_8BIT - * @arg @ref MD_SPI_RX_FIFO_TH_14BIT - * @retval None - */ -__STATIC_INLINE void md_spi_set_con2_rxfth(SPI_TypeDef *SPIx, uint32_t Threshold) -{ - MODIFY_REG(SPIx->CON2, SPI_CON2_RXFTH_MSK, Threshold<CON2, SPI_CON2_RXFTH_MSK)>>SPI_CON2_RXFTH_POSS); -} - - -/** - * @} MD_SPI_CON2 - */ - -/** - * @defgroup MD_SPI_STAT SPI Status Register - * @{ - */ - - -/** - * @brief Get SPI status register(SPIx_STAT) - * @param SPIx SPI Instance - * @retval None - */ -__STATIC_INLINE uint32_t md_spi_get_stat(SPI_TypeDef *SPIx) -{ - return (uint32_t)(READ_REG(SPIx->STAT)); -} - -/** - * @brief Check if SPI transmit buffer empty is actived - * @param SPIx SPI Instance - * @retval None - */ -__STATIC_INLINE uint32_t md_spi_is_active_flag_stat_txe(SPI_TypeDef *SPIx) -{ - return (uint32_t)(READ_BIT(SPIx->STAT, SPI_STAT_TXE_MSK)== (SPI_STAT_TXE_MSK)); -} - -/** - * @brief Check if SPI transmit buffer full is actived - * @param SPIx SPI Instance - * @retval None - */ -__STATIC_INLINE uint32_t md_spi_is_active_flag_stat_txf(SPI_TypeDef *SPIx) -{ - return (uint32_t)(READ_BIT(SPIx->STAT, SPI_STAT_TXF_MSK)== (SPI_STAT_TXF_MSK)); -} - -/** - * @brief Check if SPI transmit buffer overflow is actived - * @param SPIx SPI Instance - * @retval None - */ -__STATIC_INLINE uint32_t md_spi_is_active_flag_stat_txov(SPI_TypeDef *SPIx) -{ - return (uint32_t)(READ_BIT(SPIx->STAT, SPI_STAT_TXOV_MSK)== (SPI_STAT_TXOV_MSK)); -} - -/** - * @brief Check if SPI transmit buffer underflow is actived - * @param SPIx SPI Instance - * @retval None - */ -__STATIC_INLINE uint32_t md_spi_is_active_flag_stat_txud(SPI_TypeDef *SPIx) -{ - return (uint32_t)(READ_BIT(SPIx->STAT, SPI_STAT_TXUD_MSK) == (SPI_STAT_TXUD_MSK)); -} - -/** - * @brief Check if SPI Tx FIFO level under threshold is actived - * @param SPIx SPI Instance - * @retval None - */ -__STATIC_INLINE uint32_t md_spi_is_active_flag_stat_txth(SPI_TypeDef *SPIx) -{ - return (uint32_t)(READ_BIT(SPIx->STAT, SPI_STAT_TXTH_MSK) == (SPI_STAT_TXTH_MSK)); -} - -/** - * @brief Check if SPI receive buffer empty is actived - * @param SPIx SPI Instance - * @retval None - */ -__STATIC_INLINE uint32_t md_spi_is_active_flag_stat_rxe(SPI_TypeDef *SPIx) -{ - return (uint32_t)(READ_BIT(SPIx->STAT, SPI_STAT_RXE_MSK) == (SPI_STAT_RXE_MSK)); -} - -/** - * @brief Check if SPI receive buffer full is actived - * @param SPIx SPI Instance - * @retval None - */ -__STATIC_INLINE uint32_t md_spi_is_active_flag_stat_rxf(SPI_TypeDef *SPIx) -{ - return (uint32_t)(READ_BIT(SPIx->STAT, SPI_STAT_RXF_MSK)== (SPI_STAT_RXF_MSK)); -} - -/** - * @brief Get SPI receive buffer overflow - * @param SPIx SPI Instance - * @retval None - */ -__STATIC_INLINE uint32_t md_spi_is_active_flag_stat_rxov(SPI_TypeDef *SPIx) -{ - return (uint32_t)(READ_BIT(SPIx->CON2, SPI_STAT_RXOV_MSK)== (SPI_STAT_RXOV_MSK)); -} - -/** - * @brief Check if SPI receive buffer underflow is actived - * @param SPIx SPI Instance - * @retval None - */ -__STATIC_INLINE uint32_t md_spi_is_active_flag_stat_rxud(SPI_TypeDef *SPIx) -{ - return (uint32_t)(READ_BIT(SPIx->STAT, SPI_STAT_RXUD_MSK)== (SPI_STAT_RXUD_MSK)); -} - -/** - * @brief Check if SPI Rx FIFO level over threshold is actived - * @param SPIx SPI Instance - * @retval None - */ -__STATIC_INLINE uint32_t md_spi_is_active_flag_stat_rxth(SPI_TypeDef *SPIx) -{ - return (uint32_t)(READ_BIT(SPIx->STAT, SPI_STAT_RXTH_MSK)== (SPI_STAT_RXTH_MSK)); -} - -/** - * @brief Check if SPI channel side is actived - * @param SPIx SPI Instance - * @retval None - */ -__STATIC_INLINE uint32_t md_spi_is_active_flag_stat_chside(SPI_TypeDef *SPIx) -{ - return (uint32_t)(READ_BIT(SPIx->STAT, SPI_STAT_CHSIDE_MSK)== (SPI_STAT_CHSIDE_MSK)); -} - -/** - * @brief Check if SPI busy flag is actived - * @param SPIx SPI Instance - * @retval None - */ -__STATIC_INLINE uint32_t md_spi_is_active_flag_stat_busy(SPI_TypeDef *SPIx) -{ - return (uint32_t)(READ_BIT(SPIx->STAT, SPI_STAT_BUSY_MSK)== (SPI_STAT_BUSY_MSK)); -} - -/** - * @brief Get SPI Tx FIFO level - * @param SPIx SPI Instance - * @retval None - */ -__STATIC_INLINE uint32_t md_spi_get_stat_txflv(SPI_TypeDef *SPIx) -{ - return (uint32_t)(READ_BIT(SPIx->STAT, SPI_STAT_TXFLV_MSK) >> SPI_STAT_TXFLV_POSS); -} - -/** - * @brief Get SPI Rx FIFO level - * @param SPIx SPI Instance - * @retval None - */ -__STATIC_INLINE uint32_t md_spi_get_stat_rxflv(SPI_TypeDef *SPIx) -{ - return (uint32_t)(READ_BIT(SPIx->STAT, SPI_STAT_RXFLV_MSK) >> SPI_STAT_RXFLV_POSS); -} - -/** - * @} MD_SPI_STAT - */ - - -/** @defgroup MD_SPI_DATA SPI Data Register - * @{ - */ - -/** - * @brief Read 8-Bits in the data register - * @param SPIx SPI Instance - * @retval RxData Value between Min_Data=0x00 and Max_Data=0xFF - */ -__STATIC_INLINE uint8_t md_spi_recv_data8(SPI_TypeDef *SPIx) -{ - return (uint8_t)(READ_REG(SPIx->DATA)); -} - -/** - * @brief Read 16-Bits in the data register - * @param SPIx SPI Instance - * @retval RxData Value between Min_Data=0x00 and Max_Data=0xFFFF - */ -__STATIC_INLINE uint16_t md_spi_recv_data16(SPI_TypeDef *SPIx) -{ - return (uint16_t)(READ_REG(SPIx->DATA)); -} - -/** - * @brief Write 8-Bits in the data register - * @param SPIx SPI Instance - * @param TxData Value between Min_Data=0x00 and Max_Data=0xFF - * @retval None - */ -__STATIC_INLINE void md_spi_send_data8(SPI_TypeDef *SPIx, uint8_t TxData) -{ - SPIx->DATA = (uint8_t)TxData; -} - -/** - * @brief Write 16-Bits in the data register - * @param SPIx SPI Instance - * @param TxData Value between Min_Data=0x0000 and Max_Data=0xFFFF - * @retval None - */ -__STATIC_INLINE void md_spi_send_data16(SPI_TypeDef *SPIx, uint16_t TxData) -{ - SPIx->DATA = (uint16_t)TxData; -} - -/** - * @} MD_SPI_DATA - */ - -/** @defgroup MD_SPI_CRC SPI CRC Manangement - * @{ MD_SPI_CRC - */ - -/** - * @brief Set CRC polynmomial register (SPIx_CRCPLOY) - * @note When CRC calculation is enabled, the RxCRC[15:0] bits contain the computed CRC value of the subsequently \n - received bytes. This register is reset when the CRCEN bit in SPIx_CR1 register is written to 1. The CRC is \n - calculated serially using the polynomial programmed in the SPIx_CRCPLOY register. Only the 8 LSB bits are \n - considered when the CRC frame format is set to be 8-bit length (CRCL bit in the SPIx_CON1 is cleared). CRC \n - calculation is done based on any CRC8 standard. The entire 16-bits of this register are considered when a \n - 16-bit CRC frame format is selected (CRCL bit in the SPIx_CR1 register is set). CRC calculation is done based \n - on any CRC16 standard. - Note: A read to this register when the BSY Flag is set could return an incorrect value. These bits are not \n - used in I2S mode. - * @param SPIx SPI Instance - * @param CRCPoly This parameter must be a number between Min_Data = 0x00 and Max_Data = 0xFFFF - * @retval None - */ -__STATIC_INLINE void md_spi_set_crcploy(SPI_TypeDef *SPIx, uint32_t CRCPoly) -{ - WRITE_REG(SPIx->CRCPOLY, (uint16_t)CRCPoly); -} - -/** - * @brief Get CRC polynmomial register (SPIx_CRCPLOY) - * @param SPIx SPI Instance - * @retval Returned value is a number between Min_Data = 0x00 and Max_Data = 0xFFFF - */ -__STATIC_INLINE uint32_t md_spi_get_crcploy(SPI_TypeDef *SPIx) -{ - return (uint32_t)(READ_REG(SPIx->CRCPOLY)); -} - -/** - * @brief Get Rx CRC register - * @note When CRC calculation is enabled, the RxCRC[7:0] bits contain the computed CRC value of the subsequently \n - transmitted bytes. This register is reset when the CRCEN bit of SPIx_CON1 is written to 1. The CRC is calculated \n - serially using the polynomial programmed in the SPIx_CRCPLOY register. Only the 8 LSB bits are considered \n - when the CRC frame format is set to be 8-bit length (FLEN bit in the SPIx_CON1 is cleared). CRC calculation is \n - done based on any CRC8 standard. The entire 16-bits of this register are considered when a 16-bit CRC frame \n - format is selected (CRCL bit in the SPIx_CR1 register is set). CRC calculation is done based on any CRC16 standard. \n - Note: A read to this register when the BSY flag is set could return an incorrect value. These bits are not used \n - in I2S mode. - * @param SPIx SPI Instance - * @retval Returned value is a number between Min_Data = 0x00 and Max_Data = 0xFFFF - */ -__STATIC_INLINE uint32_t md_spi_get_rxcrc(SPI_TypeDef *SPIx) -{ - return (uint32_t)(READ_REG(SPIx->RXCRC)); -} - -/** - * @brief Get Tx CRC register - * @note When CRC calculation is enabled, the TxCRC[7:0] bits contain the computed CRC value of the subsequently \n - transmitted bytes. This register is reset when the CRCEN bit of SPIx_CON1 is written to 1. The CRC is calculated \n - serially using the polynomial programmed in the SPIx_CRCPLOY register. Only the 8 LSB bits are considered \n - when the CRC frame format is set to be 8-bit length (FLEN bit in the SPIx_CR1 is cleared). CRC calculation is \n - done based on any CRC8 standard. The entire 16-bits of this register are considered when a 16-bit CRC frame \n - format is selected (CRCL bit in the SPIx_CR1 register is set). CRC calculation is done based on any CRC16 standard. \n - Note: A read to this register when the BSY flag is set could return an incorrect value. These bits are not used \n - in I2S mode. - * @param SPIx SPI Instance - * @retval Returned value is a number between Min_Data = 0x00 and Max_Data = 0xFFFF - */ -__STATIC_INLINE uint32_t md_spi_get_txcrc(SPI_TypeDef *SPIx) -{ - return (uint32_t)(READ_REG(SPIx->TXCRC)); -} - -/** - * @} MD_SPI_CRC - */ - - - -/** @defgroup MD_SPI_I2S I2S Configuration Management - * @{ - */ - - -/** @defgroup MD_SPI_I2SCFG I2S Configuration register - * @{ - */ - -/** - * @brief Set SPI I2S configuration register(SPIx_I2SCFG) - * @param SPIx SPI Instance - * @param value The value write in SPIx_I2SCFG - * @retval None - */ -__STATIC_INLINE void md_spi_set_I2SCFG(SPI_TypeDef *SPIx, uint32_t value) -{ - WRITE_REG(SPIx->I2SCFG, value); -} - -/** - * @brief Get SPI I2S configuration register (SPIx_I2SCFG) - * @param SPIx SPI Instance - * @retval None - */ -__STATIC_INLINE uint32_t md_spi_get_I2SCFG(SPI_TypeDef *SPIx) -{ - return (uint32_t)(READ_REG(SPIx->I2SCFG)); -} - -/** - * @brief Set channel legth(number of bits per audio channel) - * @note The bit write operation has a meaning only if DATLEN = 00 otherwise the channel length is fixed to 32-bit by \n - hardware whatever the value filled in. - Note: For correct operation, this bit should be configured when the I2S is disabled. It is not used in SPI mode. - * @param SPIx SPI Instance - * @param value This bit can be set to: - * @arg @ref MD_I2S_CHANNEL_LENGTH_16BIT - * @arg @ref MD_I2S_CHANNEL_LENGTH_32BIT - * @retval None - */ -__STATIC_INLINE void md_spi_set_i2scfg_chlen(SPI_TypeDef *SPIx, uint32_t value) -{ - MODIFY_REG(SPIx->I2SCFG, SPI_I2SCFG_CHLEN_MSK, value); -} - -/** - * @brief Get channel legth(number of bits per audio channel) - * @param SPIx SPI Instance - * @retval Returned value can be one of the following values: - * @retval Return: - * @arg @ref MD_I2S_CHANNEL_LENGTH_16BIT - * @arg @ref MD_I2S_CHANNEL_LENGTH_32BIT - */ -__STATIC_INLINE uint32_t md_spi_get_i2scfg_chlen(SPI_TypeDef *SPIx) -{ - return (uint32_t)(READ_BIT(SPIx->I2SCFG, SPI_I2SCFG_CHLEN_MSK)); -} - -/** - * @brief Set Data length to be transferred - * @param SPIx SPI Instance - * @param value This bit can be set to: - * @arg @ref MD_I2S_DATA_LENGTH_16BIT - * @arg @ref MD_I2S_DATA_LENGTH_24BIT - * @arg @ref MD_I2S_DATA_LENGTH_32BIT - * @arg @ref MD_I2S_DATA_LENGTH_NOT_ALLOWED - * @retval None - */ -__STATIC_INLINE void md_spi_set_i2scfg_datlen(SPI_TypeDef *SPIx, uint32_t value) -{ - MODIFY_REG(SPIx->I2SCFG, SPI_I2SCFG_DATLEN_MSK, value); -} - -/** - * @brief Get Data length to be transferred - * @param SPIx SPI Instance - * @retval Returned value can be one of the following values: - * @arg @ref MD_I2S_DATA_LENGTH_16BIT - * @arg @ref MD_I2S_DATA_LENGTH_24BIT - * @arg @ref MD_I2S_DATA_LENGTH_32BIT - * @arg @ref MD_I2S_DATA_LENGTH_NOT_ALLOWED - */ -__STATIC_INLINE uint32_t md_spi_get_i2scfg_datlen(SPI_TypeDef *SPIx) -{ - return (uint32_t)(READ_BIT(SPIx->I2SCFG, SPI_I2SCFG_DATLEN_MSK)>>SPI_I2SCFG_DATLEN_POSS); -} - -/** - * @brief Set Inactive state clock polarity - * @note Note: For correct operation, this bit should be configured when the I2S is disabled. It is not used \n - in SPI mode. The bit CKPOL does not affect the CK edge sensitivity used to receive or transmit the SD \n - and WS signals. - * @param SPIx SPI Instance - * @param value This bit can be set to: - * @arg @ref MD_I2S_POLARITY_LOW - * @arg @ref MD_I2S_POLARITY_HIGH - * @retval None - */ -__STATIC_INLINE void md_spi_set_i2scfg_ckpol(SPI_TypeDef *SPIx, uint32_t value) -{ - MODIFY_REG(SPIx->I2SCFG, SPI_I2SCFG_CKPOL_MSK, value); -} - -/** - * @brief Get Inactive state clock polarity - * @param SPIx SPI Instance - * @retval Returned value can be one of the following values: - * @retval Return follow : - * @arg @ref MD_I2S_POLARITY_LOW - * @arg @ref MD_I2S_POLARITY_HIGH - */ -__STATIC_INLINE uint32_t md_spi_get_i2scfg_ckpol(SPI_TypeDef *SPIx) -{ - return (uint32_t)(READ_BIT(SPIx->I2SCFG, SPI_I2SCFG_CKPOL_MSK)>>SPI_I2SCFG_CKPOL_POS); -} - -/** - * @brief Set I2S standard selection - * @param SPIx SPI Instance - * @param value This bit can be set to: - * @arg @ref MD_I2S_PHILIPS_STANDARD - * @arg @ref MD_I2S_MSB_STANDARD - * @arg @ref MD_I2S_LSB_STANDARD - * @arg @ref MD_I2S_PCM_STANDARD - * @retval None - */ -__STATIC_INLINE void md_spi_set_i2scfg_i2sstd(SPI_TypeDef *SPIx, uint32_t value) -{ - MODIFY_REG(SPIx->I2SCFG, SPI_I2SCFG_I2SSTD_MSK, value); -} - -/** - * @brief Get I2S standard selection - * @param SPIx SPI Instance - * @retval Returned value can be one of the following values: - * @retval Return follow : - * @arg @ref MD_I2S_PHILIPS_STANDARD - * @arg @ref MD_I2S_MSB_STANDARD - * @arg @ref MD_I2S_LSB_STANDARD - * @arg @ref MD_I2S_PCM_STANDARD - */ -__STATIC_INLINE uint32_t md_spi_get_i2scfg_i2sstd(SPI_TypeDef *SPIx) -{ - return (uint32_t)(READ_BIT(SPIx->I2SCFG, SPI_I2SCFG_I2SSTD_MSK)>>SPI_I2SCFG_I2SSTD_POSS); -} - -/** - * @brief Set PCM frame synchronization - * @param SPIx SPI Instance - * @param value This bit can be set to: - * @arg @ref MD_I2S_FRAME_SYN_SHORT - * @arg @ref MD_I2S_FRAME_SYN_LONG - * @retval None - */ -__STATIC_INLINE void md_spi_set_i2scfg_pcmsync(SPI_TypeDef *SPIx, uint32_t value) -{ - MODIFY_REG(SPIx->I2SCFG, SPI_I2SCFG_PCMSYNC_MSK, value); -} - -/** - * @brief Get PCM frame synchronization - * @param SPIx SPI Instance - * @retval Returned value can be one of the following values: - * @retval Return follow : - * @arg @ref MD_I2S_FRAME_SYN_SHORT - * @arg @ref MD_I2S_FRAME_SYN_LONG - */ -__STATIC_INLINE uint32_t md_spi_get_i2scfg_pcmsync(SPI_TypeDef *SPIx) -{ - return (uint32_t)(READ_BIT(SPIx->I2SCFG, SPI_I2SCFG_PCMSYNC_MSK)>>SPI_I2SCFG_PCMSYNC_POS); -} - -/** - * @brief Set I2S configuration mode - * @param SPIx SPI Instance - * @param value This bit can be set to: - * @arg @ref MD_I2S_SLAVE_TX - * @arg @ref MD_I2S_SLAVE_RX - * @arg @ref MD_I2S_MASTER_TX - * @arg @ref MD_I2S_MASTER_RX - * @retval None - */ -__STATIC_INLINE void md_spi_set_i2scfg_i2scfg(SPI_TypeDef *SPIx, uint32_t value) -{ - MODIFY_REG(SPIx->I2SCFG, SPI_I2SCFG_I2SCFG_MSK, value); -} - -/** - * @brief Get I2S configuration mode - * @param SPIx SPI Instance - * @retval Returned value can be one of the following values: - * @retval Return follow : - * @arg @ref MD_I2S_SLAVE_TX - * @arg @ref MD_I2S_SLAVE_RX - * @arg @ref MD_I2S_MASTER_TX - * @arg @ref MD_I2S_MASTER_RX - */ -__STATIC_INLINE uint32_t md_spi_get_i2scfg_i2scfg(SPI_TypeDef *SPIx) -{ - return (uint32_t)(READ_BIT(SPIx->I2SCFG, SPI_I2SCFG_I2SCFG_MSK)>>SPI_I2SCFG_I2SCFG_POSS); -} - -/** - * @brief Enable I2S enable - * @param SPIx SPI Instance - * @retval None - */ -__STATIC_INLINE void md_spi_enable_i2scfg_i2se(SPI_TypeDef *SPIx) -{ - SET_BIT(SPIx->I2SCFG, SPI_I2SCFG_I2SE_MSK); -} - -/** - * @brief Disable I2S enable - * @note When disabling the I2S, follow the procedure described in the Reference Manual. - * @param SPIx SPI Instance - * @retval None - */ -__STATIC_INLINE void md_spi_disable_i2scfg_i2se(SPI_TypeDef *SPIx) -{ - CLEAR_BIT(SPIx->I2SCFG, SPI_I2SCFG_I2SE_MSK); -} - -/** - * @brief Check if I2S enable is enabled - * @param SPIx SPI Instance - * @retval State of bit (1 or 0). - */ -__STATIC_INLINE uint32_t md_spi_is_enable_i2scfg_i2se(SPI_TypeDef *SPIx) -{ - return (READ_BIT(SPIx->I2SCFG, SPI_I2SCFG_I2SE_MSK) == (SPI_I2SCFG_I2SE_MSK)); -} - -/** - * @brief Set I2S mode selection - * @param SPIx SPI Instance - * @param value This bit can be set to: - * @arg @ref MD_I2S_MODE_SPI - * @arg @ref MD_I2S_MODE_I2S - * @retval None - */ -__STATIC_INLINE void md_spi_set_i2scfg_i2smod(SPI_TypeDef *SPIx, uint32_t value) -{ - MODIFY_REG(SPIx->I2SCFG, SPI_I2SCFG_I2SMOD_MSK, value); -} - -/** - * @brief Get I2S mode selection - * @param SPIx SPI Instance - * @retval Returned value can be one of the following values: - * @retval Return follow : - * @arg @ref MD_I2S_MODE_SPI - * @arg @ref MD_I2S_MODE_I2S - */ -__STATIC_INLINE uint32_t md_spi_get_i2scfg_i2smod(SPI_TypeDef *SPIx) -{ - return (uint32_t)(READ_BIT(SPIx->I2SCFG, SPI_I2SCFG_I2SMOD_MSK)>>SPI_I2SCFG_I2SMOD_POS); -} - - -/** - * @} MD_SPI_I2SCFG - */ - -/**@defgroup MD_SPI_I2SPR I2S Prescaler register - * @{ - */ - - - -/** - * @brief Set SPI I2S configuration register(SPIx_I2SPR) - * @param SPIx SPI Instance - * @param value The value write in SPIx_I2SPR - * @retval None - */ -__STATIC_INLINE void md_spi_set_I2SPR(SPI_TypeDef *SPIx, uint32_t value) -{ - WRITE_REG(SPIx->I2SPR, value); -} - -/** - * @brief Get SPI I2S configuration register (SPIx_I2SPR) - * @param SPIx SPI Instance - * @retval None - */ -__STATIC_INLINE uint32_t md_spi_get_I2SPR(SPI_TypeDef *SPIx) -{ - return (uint32_t)(READ_REG(SPIx->I2SPR)); -} - -/** - * @brief Set I2S linear prescaler - * @note I2SDIV [7:0] = 0 or I2SDIV [7:0] = 1 are forbidden values. \n - Note: These bits should be configured when the I2S is disabled. \n - They are used only when the I2S is in master mode. They are not used in SPI mode. - * @param SPIx SPI Instance - * @param value This bit can be set to: - * @arg Max:255 - * @arg Min:2 - * @retval None - */ -__STATIC_INLINE void md_spi_set_i2spr_i2sdiv(SPI_TypeDef *SPIx, uint32_t value) -{ - MODIFY_REG(SPIx->I2SPR, SPI_I2SPR_I2SDIV_MSK, value); -} - -/** - * @brief Get I2S linear prescaler - * @note 0 or 1 are forbidden values - * @param SPIx SPI Instance - * @retval Returned value can be one of the following values: - * @retval Return follow : - * @arg Max:255 - * @arg Min:2 - */ -__STATIC_INLINE uint32_t md_spi_get_i2spr_i2sdiv(SPI_TypeDef *SPIx) -{ - return (uint32_t)(READ_BIT(SPIx->I2SPR, SPI_I2SPR_I2SDIV_MSK)>>SPI_I2SPR_I2SDIV_POSS); -} - -/** - * @brief Set Odd factor for the prescaler - * @note 0 or 1 are forbidden values - * @param SPIx SPI Instance - * @param value This bit can be set to: - * @arg MD_I2S_EVEN - * @arg MD_I2S_ODD - * @retval None - */ -__STATIC_INLINE void md_spi_set_i2spr_odd(SPI_TypeDef *SPIx, uint32_t value) -{ - MODIFY_REG(SPIx->I2SPR, SPI_I2SPR_ODD_MSK, value); -} - -/** - * @brief Get Odd factor for the prescaler - * @note 0 or 1 are forbidden values - * @param SPIx SPI Instance - * @retval Returned value can be one of the following values: - * @retval Return follow : - * @arg MD_I2S_EVEN - * @arg MD_I2S_ODD - */ -__STATIC_INLINE uint32_t md_spi_get_i2spr_odd(SPI_TypeDef *SPIx) -{ - return (uint32_t)(READ_BIT(SPIx->I2SPR, SPI_I2SPR_ODD_MSK)>>SPI_I2SPR_ODD_POS); -} - -/** - * @brief Master clock output enable - * @param SPIx SPI Instance - * @retval None - */ -__STATIC_INLINE void md_spi_enable_i2spr_mckoe(SPI_TypeDef *SPIx) -{ - SET_BIT(SPIx->I2SPR, SPI_I2SPR_MCKOE_MSK); -} - -/** - * @brief Master clock output disable - * @note When disabling the I2S, follow the procedure described in the Reference Manual. - * @param SPIx SPI Instance - * @retval None - */ -__STATIC_INLINE void md_spi_disable_i2spr_mckoe(SPI_TypeDef *SPIx) -{ - CLEAR_BIT(SPIx->I2SCFG, SPI_I2SPR_MCKOE_MSK); -} - -/** - * @brief Check if Master clock output enable is enabled - * @param SPIx SPI Instance - * @retval State of bit (1 or 0). - */ -__STATIC_INLINE uint32_t md_spi_is_enable_i2spr_mckoe(SPI_TypeDef *SPIx) -{ - return (READ_BIT(SPIx->I2SPR, SPI_I2SPR_MCKOE_MSK) == (SPI_I2SPR_MCKOE_MSK)); -} - -/** - * @brief Set External I2S Clock Enable - * @note 0 or 1 are forbidden values - * @param SPIx SPI Instance - * @param value This bit can be set to: - * @arg MD_I2S_APB_CLOCK - * @arg MD_I2S_EXTERNAL_CLOCK - * @retval None - */ -__STATIC_INLINE void md_spi_set_i2spr_extcken(SPI_TypeDef *SPIx, uint32_t value) -{ - MODIFY_REG(SPIx->I2SPR, SPI_I2SPR_EXTCKEN_MSK, value); -} - -/** - * @brief Get External I2S Clock Enable - * @note 0 or 1 are forbidden values - * @param SPIx SPI Instance - * @retval Returned value can be one of the following values: - * @retval Return follow : - * @arg MD_I2S_APB_CLOCK - * @arg MD_I2S_EXTERNAL_CLOCK - */ -__STATIC_INLINE uint32_t md_spi_get_i2spr_extcken(SPI_TypeDef *SPIx) -{ - return (uint32_t)(READ_BIT(SPIx->I2SPR, SPI_I2SPR_EXTCKEN_MSK)>>SPI_I2SPR_EXTCKEN_POS); -} - - - - - - -/** - * @} MD_SPI_I2SPR - */ - - - -/** - * @} MD_SPI_I2S - */ - - -/** @defgroup MD_SPI_PF_Interrupt_Management SPI Interrupt Management - * @{ - */ - -/** @defgroup MD_SPI_IER SPI Interrupt Enable Register - * @{ - */ - - -/** - * @brief Frame format error interrupt enable - * @note This bit controls the generation of an interrupt when an error condition occurs (CRCERR, OVR, MODF in SPI mode, FRE at TI mode). - * @param SPIx SPI Instance - * @retval None - */ -__STATIC_INLINE void md_spi_enable_ier_freie(SPI_TypeDef *SPIx) -{ - SET_BIT(SPIx->IER, SPI_IER_FREIE_MSK); -} - -/** - * @brief Mode fault interrupt enable - * @note This bit controls the generation of an interrupt when an error condition occurs (CRCERR, OVR, MODF in SPI mode, FRE at TI mode). - * @param SPIx SPI Instance - * @retval None - */ -__STATIC_INLINE void md_spi_enable_ier_modfie(SPI_TypeDef *SPIx) -{ - SET_BIT(SPIx->IER, SPI_IER_MODFIE_MSK); -} - -/** - * @brief CRC error interrupt enable - * @param SPIx SPI Instance - * @retval None - */ -__STATIC_INLINE void md_spi_enable_ier_crcerrie(SPI_TypeDef *SPIx) -{ - SET_BIT(SPIx->IER, SPI_IER_CRCERRIE_MSK); -} - -/** - * @brief Receive buffer over threshold interrupt enable - * @note This bit controls the generation of an interrupt when an error condition occurs (CRCERR, OVR, MODF in SPI mode, FRE at TI mode). - * @param SPIx SPI Instance - * @retval None - */ -__STATIC_INLINE void md_spi_enable_ier_rxthie(SPI_TypeDef *SPIx) -{ - SET_BIT(SPIx->IER, SPI_IER_RXTHIE_MSK); -} - -/** - * @brief Transmit buffer over threshold interrupt enable - * @param SPIx SPI Instance - * @retval None - */ -__STATIC_INLINE void md_spi_enable_ier_txthie(SPI_TypeDef *SPIx) -{ - SET_BIT(SPIx->IER, SPI_IER_TXTHIE_MSK); -} - -/** - * @brief Receive buffer underrun interrupt enable - * @param SPIx SPI Instance - * @retval None - */ -__STATIC_INLINE void md_spi_enable_ier_rxudie(SPI_TypeDef *SPIx) -{ - SET_BIT(SPIx->IER, SPI_IER_RXUDIE_MSK); -} - -/** - * @brief Transmit buffer underrun interrupt enable - * @param SPIx SPI Instance - * @retval None - */ -__STATIC_INLINE void md_spi_enable_ier_txudie(SPI_TypeDef *SPIx) -{ - SET_BIT(SPIx->IER, SPI_IER_TXUDIE_MSK); -} - -/** - * @brief Receive buffer overrun interrupt enable - * @param SPIx SPI Instance - * @retval None - */ -__STATIC_INLINE void md_spi_enable_ier_rxovie(SPI_TypeDef *SPIx) -{ - SET_BIT(SPIx->IER, SPI_IER_RXOVIE_MSK); -} - -/** - * @brief Transmit buffer overrun interrupt enable - * @param SPIx SPI Instance - * @retval None - */ -__STATIC_INLINE void md_spi_enable_ier_txovie(SPI_TypeDef *SPIx) -{ - SET_BIT(SPIx->IER, SPI_IER_TXOVIE_MSK); -} - -/** - * @brief Receive buffer full interrupt enable - * @param SPIx SPI Instance - * @retval None - */ -__STATIC_INLINE void md_spi_enable_ier_rxfie(SPI_TypeDef *SPIx) -{ - SET_BIT(SPIx->IER, SPI_IER_RXFIE_MSK); -} - -/** - * @brief Transmit buffer empty interrupt enable - * @param SPIx SPI Instance - * @retval None - */ -__STATIC_INLINE void md_spi_enable_ier_txeie(SPI_TypeDef *SPIx) -{ - SET_BIT(SPIx->IER, SPI_IER_TXEIE_MSK); -} - -/** - * @} MD_SPI_IER - */ - - -/** @defgroup MD_SPI_IDR SPI Interrupt Disable Register - * @{ - */ - -/** - * @brief Frame format error interrupt disable - * @param SPIx SPI Instance - * @retval None - */ -__STATIC_INLINE void md_spi_disable_idr_freid(SPI_TypeDef *SPIx) -{ - SET_BIT(SPIx->IDR, SPI_IDR_FREID_MSK); -} - -/** - * @brief Mode fault interrupt disable - * @param SPIx SPI Instance - * @retval None - */ -__STATIC_INLINE void md_spi_disable_idr_modfid(SPI_TypeDef *SPIx) -{ - SET_BIT(SPIx->IDR, SPI_IDR_MODFID_MSK); -} - -/** - * @brief CRC error interrupt disable - * @param SPIx SPI Instance - * @retval None - */ -__STATIC_INLINE void md_spi_disable_idr_crcerrid(SPI_TypeDef *SPIx) -{ - SET_BIT(SPIx->IDR, SPI_IDR_CRCERRID_MSK); -} - -/** - * @brief Receive buffer under threshold interrupt disable - * @param SPIx SPI Instance - * @retval None - */ -__STATIC_INLINE void md_spi_disable_idr_rxthid(SPI_TypeDef *SPIx) -{ - SET_BIT(SPIx->IDR, SPI_IDR_RXTHID_MSK); -} - -/** - * @brief Transmit buffer under threshold interrupt disable - * @param SPIx SPI Instance - * @retval None - */ -__STATIC_INLINE void md_spi_disable_idr_txthid(SPI_TypeDef *SPIx) -{ - SET_BIT(SPIx->IDR, SPI_IDR_TXTHID_MSK); -} - -/** - * @brief Receive buffer underrun interrupt disable - * @param SPIx SPI Instance - * @retval None - */ -__STATIC_INLINE void md_spi_disable_idr_rxudid(SPI_TypeDef *SPIx) -{ - SET_BIT(SPIx->IDR, SPI_IDR_RXUDID_MSK); -} - -/** - * @brief Transmit buffer underrun interrupt disable - * @param SPIx SPI Instance - * @retval None - */ -__STATIC_INLINE void md_spi_disable_idr_txudid(SPI_TypeDef *SPIx) -{ - SET_BIT(SPIx->IDR, SPI_IDR_TXUDID_MSK); -} - -/** - * @brief Receive buffer overrun interrupt disable - * @param SPIx SPI Instance - * @retval None - */ -__STATIC_INLINE void md_spi_disable_idr_rxovid(SPI_TypeDef *SPIx) -{ - SET_BIT(SPIx->IDR, SPI_IDR_RXOVID_MSK); -} - -/** - * @brief Transmit buffer overrun interrupt disable - * @param SPIx SPI Instance - * @retval None - */ -__STATIC_INLINE void md_spi_disable_idr_txovid(SPI_TypeDef *SPIx) -{ - SET_BIT(SPIx->IDR, SPI_IDR_TXOVID_MSK); -} - -/** - * @brief Receive buffer full interrupt disable - * @param SPIx SPI Instance - * @retval None - */ -__STATIC_INLINE void md_spi_disable_idr_rxfid(SPI_TypeDef *SPIx) -{ - SET_BIT(SPIx->IDR, SPI_IDR_RXFID_MSK); -} - -/** - * @brief Transmit buffer empty interrupt disable - * @param SPIx SPI Instance - * @retval None - */ -__STATIC_INLINE void md_spi_disable_idr_txeid(SPI_TypeDef *SPIx) -{ - SET_BIT(SPIx->IDR, SPI_IDR_TXEID_MSK); -} - -/** - * @} MD_SPI_IDR - */ - -/** @defgroup MD_SPI_ICR SPI Interrupt Clear Status Register - * @{ - */ - -/** - * @brief Frame format error interrupt clear - * @param SPIx SPI Instance - * @retval State of bit (1 or 0). - */ -__STATIC_INLINE void md_spi_clear_icr_freic(SPI_TypeDef *SPIx) -{ - SET_BIT(SPIx->ICR, SPI_ICR_FREIC_MSK); -} - -/** - * @brief Mode fault interrupt clear - * @param SPIx SPI Instance - * @retval State of bit (1 or 0). - */ -__STATIC_INLINE void md_spi_clear_icr_modfic(SPI_TypeDef *SPIx) -{ - SET_BIT(SPIx->ICR, SPI_ICR_MODFIC_MSK); -} - -/** - * @brief CRC error interrupt clear - * @param SPIx SPI Instance - * @retval State of bit (1 or 0). - */ -__STATIC_INLINE void md_spi_clear_icr_crcerric(SPI_TypeDef *SPIx) -{ - SET_BIT(SPIx->ICR, SPI_ICR_CRCERRIC_MSK); -} - -/** - * @brief Receive buffer over threshold interrupt clear - * @param SPIx SPI Instance - * @retval State of bit (1 or 0). - */ -__STATIC_INLINE void md_spi_clear_icr_rxthic(SPI_TypeDef *SPIx) -{ - SET_BIT(SPIx->ICR, SPI_ICR_RXTHIC_MSK); -} - -/** - * @brief Transmit buffer over threshold interrupt clear - * @param SPIx SPI Instance - * @retval State of bit (1 or 0). - */ -__STATIC_INLINE void md_spi_clear_icr_txthic(SPI_TypeDef *SPIx) -{ - SET_BIT(SPIx->ICR, SPI_ICR_TXTHIC_MSK); -} - -/** - * @brief Receive buffer underrun interrupt clear - * @param SPIx SPI Instance - * @retval State of bit (1 or 0). - */ -__STATIC_INLINE void md_spi_clear_icr_rxudic(SPI_TypeDef *SPIx) -{ - SET_BIT(SPIx->ICR, SPI_ICR_RXUDIC_MSK); -} - -/** - * @brief Transmit buffer underrun interrupt clear - * @param SPIx SPI Instance - * @retval State of bit (1 or 0). - */ -__STATIC_INLINE void md_spi_clear_icr_txudic(SPI_TypeDef *SPIx) -{ - SET_BIT(SPIx->ICR, SPI_ICR_TXUDIC_MSK); -} - -/** - * @brief Receive buffer overrun interrupt clear - * @param SPIx SPI Instance - * @retval State of bit (1 or 0). - */ -__STATIC_INLINE void md_spi_clear_icr_rxovic(SPI_TypeDef *SPIx) -{ - SET_BIT(SPIx->ICR, SPI_ICR_RXOVIC_MSK); -} - -/** - * @brief Transmit buffer overrun interrupt clear - * @param SPIx SPI Instance - * @retval State of bit (1 or 0). - */ -__STATIC_INLINE void md_spi_clear_icr_txovic(SPI_TypeDef *SPIx) -{ - SET_BIT(SPIx->ICR, SPI_ICR_TXOVIC_MSK); -} - -/** - * @brief Receive buffer full interrupt clear - * @param SPIx SPI Instance - * @retval State of bit (1 or 0). - */ -__STATIC_INLINE void md_spi_clear_icr_rxfic(SPI_TypeDef *SPIx) -{ - SET_BIT(SPIx->ICR, SPI_ICR_RXFIC_MSK); -} - -/** - * @brief Transmit buffer empty interrupt clear - * @param SPIx SPI Instance - * @retval State of bit (1 or 0). - */ -__STATIC_INLINE void md_spi_clear_icr_txeic(SPI_TypeDef *SPIx) -{ - SET_BIT(SPIx->ICR, SPI_ICR_TXEIC_MSK); -} - -/** - * @} MD_SPI_ICR - */ - -/** @defgroup MD_SPI_IVS SPI Interrupt Valid Status Register - * @{ - */ - - -/** - * @brief Check if Frame format error interrupt valid is enabled - * @param SPIx SPI Instance - * @retval State of bit (1 or 0). - */ -__STATIC_INLINE uint32_t md_spi_is_enabled_ivs_freiv(SPI_TypeDef *SPIx) -{ - return (READ_BIT(SPIx->IVS, SPI_IVS_FREIV_MSK) == (SPI_IVS_FREIV_MSK)); -} - -/** - * @brief Check if Mode fault interrupt valid is enabled - * @param SPIx SPI Instance - * @retval State of bit (1 or 0). - */ -__STATIC_INLINE uint32_t md_spi_is_enabled_ivs_modfiv(SPI_TypeDef *SPIx) -{ - return (READ_BIT(SPIx->IVS, SPI_IVS_MODFIV_MSK) == (SPI_IVS_MODFIV_MSK)); -} - -/** - * @brief Check if CRC error interrupt valid is enabled - * @param SPIx SPI Instance - * @retval State of bit (1 or 0). - */ -__STATIC_INLINE uint32_t md_spi_is_enabled_ivs_crcerriv(SPI_TypeDef *SPIx) -{ - return (READ_BIT(SPIx->IVS, SPI_IVS_CRCERRIV_MSK) == (SPI_IVS_CRCERRIV_MSK)); -} - -/** - * @brief Check if Receive buffer under threshold interrupt valid is enabled - * @param SPIx SPI Instance - * @retval State of bit (1 or 0). - */ -__STATIC_INLINE uint32_t md_spi_is_enabled_ivs_rxthiv(SPI_TypeDef *SPIx) -{ - return (READ_BIT(SPIx->IVS, SPI_IVS_RXTHIV_MSK) == (SPI_IVS_RXTHIV_MSK)); -} - -/** - * @brief Check if Transmit buffer under threshold interrupt valid is enabled - * @param SPIx SPI Instance - * @retval State of bit (1 or 0). - */ -__STATIC_INLINE uint32_t md_spi_is_enabled_it_txthiv(SPI_TypeDef *SPIx) -{ - return (READ_BIT(SPIx->IVS, SPI_IVS_TXTHIV_MSK) == (SPI_IVS_TXTHIV_MSK)); -} - -/** - * @brief Check if Receive buffer under underrun interrupt valid is enabled - * @param SPIx SPI Instance - * @retval State of bit (1 or 0). - */ -__STATIC_INLINE uint32_t md_spi_is_enabled_ivs_rxudiv(SPI_TypeDef *SPIx) -{ - return (READ_BIT(SPIx->IVS, SPI_IVS_RXUDIV_MSK) == (SPI_IVS_RXUDIV_MSK)); -} - -/** - * @brief Check if Transmit buffer underrun interrupt valid is enabled - * @param SPIx SPI Instance - * @retval State of bit (1 or 0). - */ -__STATIC_INLINE uint32_t md_spi_is_enabled_it_txudiv(SPI_TypeDef *SPIx) -{ - return (READ_BIT(SPIx->IVS, SPI_IVS_TXUDIV_MSK) == (SPI_IVS_TXUDIV_MSK)); -} - -/** - * @brief Check if Receive buffer overrun interrupt valid is enabled - * @param SPIx SPI Instance - * @retval State of bit (1 or 0). - */ -__STATIC_INLINE uint32_t md_spi_is_enabled_ivs_rxoviv(SPI_TypeDef *SPIx) -{ - return (READ_BIT(SPIx->IVS, SPI_IVS_RXOVIV_MSK) == (SPI_IVS_RXOVIV_MSK)); -} - -/** - * @brief Check if Transmit buffer overrun interrupt valid is enabled - * @param SPIx SPI Instance - * @retval State of bit (1 or 0). - */ -__STATIC_INLINE uint32_t md_spi_is_enabled_ivs_txoviv(SPI_TypeDef *SPIx) -{ - return (READ_BIT(SPIx->IVS, SPI_IVS_TXOVIV_MSK) == (SPI_IVS_TXOVIV_MSK)); -} - -/** - * @brief Check if Receive buffer full interrupt valid is enabled - * @param SPIx SPI Instance - * @retval State of bit (1 or 0). - */ -__STATIC_INLINE uint32_t md_spi_is_enabled_ivs_rxfiv(SPI_TypeDef *SPIx) -{ - return (READ_BIT(SPIx->IVS, SPI_IVS_RXFIV_MSK) == (SPI_IVS_RXFIV_MSK)); -} - -/** - * @brief Check if Transmit buffer empty interrupt valid is enabled - * @param SPIx SPI Instance - * @retval State of bit (1 or 0). - */ -__STATIC_INLINE uint32_t md_spi_is_enabled_ivs_txeiv(SPI_TypeDef *SPIx) -{ - return (READ_BIT(SPIx->IVS, SPI_IVS_TXEIV_MSK) == (SPI_IVS_TXEIV_MSK)); -} - - -/** - * @} MD_SPI_IVS - */ - - -/** @defgroup MD_SPI_RIF SPI Raw Interrupt Flag Status Register - * @{ - */ - -/** - * @brief Check if Transmit buffer empty interrupt flag status is actived - * @param SPIx SPI Instance - * @retval None - */ -__STATIC_INLINE uint32_t md_spi_is_active_flag_rif_txeri(SPI_TypeDef *SPIx) -{ - return (uint32_t)(READ_BIT(SPIx->RIF, SPI_RIF_TXERI_MSK)==(SPI_RIF_TXERI_MSK)); -} - -/** - * @brief Check if Transmit buffer overrun interrupt flag status is actived - * @param SPIx SPI Instance - * @retval None - */ -__STATIC_INLINE uint32_t md_spi_is_active_flag_rif_txovri(SPI_TypeDef *SPIx) -{ - return (uint32_t)(READ_BIT(SPIx->RIF, SPI_RIF_TXOVRI_MSK)==(SPI_RIF_TXOVRI_MSK)); -} - -/** - * @brief Check if Transmit buffer underrun interrupt flag status is actived - * @param SPIx SPI Instance - * @retval None - */ -__STATIC_INLINE uint32_t md_spi_is_active_flag_rif_txudri(SPI_TypeDef *SPIx) -{ - return (uint32_t)(READ_BIT(SPIx->RIF, SPI_RIF_TXUDRI_MSK)==(SPI_RIF_TXUDRI_MSK)); -} - -/** - * @brief Check if Transmit buffer under threshold interrupt flag status is actived - * @param SPIx SPI Instance - * @retval None - */ -__STATIC_INLINE uint32_t md_spi_is_active_flag_rif_txthri(SPI_TypeDef *SPIx) -{ - return (uint32_t)(READ_BIT(SPIx->RIF, SPI_RIF_TXTHRI_MSK)==(SPI_RIF_TXTHRI_MSK)); -} - -/** - * @brief Check if Receive buffer full interrupt flag status is actived - * @param SPIx SPI Instance - * @retval None - */ -__STATIC_INLINE uint32_t md_spi_is_active_flag_rif_rxfri(SPI_TypeDef *SPIx) -{ - return (uint32_t)(READ_BIT(SPIx->RIF, SPI_RIF_RXFRI_MSK)==(SPI_RIF_RXFRI_MSK)); -} - -/** - * @brief Check if Receive buffer overrun interrupt flag status is actived - * @param SPIx SPI Instance - * @retval None - */ -__STATIC_INLINE uint32_t md_spi_is_active_flag_rif_rxovri(SPI_TypeDef *SPIx) -{ - return (uint32_t)(READ_BIT(SPIx->RIF, SPI_RIF_RXOVRI_MSK)==(SPI_RIF_RXOVRI_MSK)); -} - -/** - * @brief Check if Receive buffer underrun interrupt flag status is actived - * @param SPIx SPI Instance - * @retval None - */ -__STATIC_INLINE uint32_t md_spi_is_active_flag_rif_rxudri(SPI_TypeDef *SPIx) -{ - return (uint32_t)(READ_BIT(SPIx->RIF, SPI_RIF_RXUDRI_MSK)==(SPI_RIF_RXUDRI_MSK)); -} - -/** - * @brief Check if Receive buffer over threshold interrupt flag status is actived - * @param SPIx SPI Instance - * @retval None - */ -__STATIC_INLINE uint32_t md_spi_is_active_flag_rif_rxthri(SPI_TypeDef *SPIx) -{ - return (uint32_t)(READ_BIT(SPIx->RIF, SPI_RIF_RXTHRI_MSK)==(SPI_RIF_RXTHRI_MSK)); -} - -/** - * @brief Check if CRC error interrupt flag status is actived - * @param SPIx SPI Instance - * @retval None - */ -__STATIC_INLINE uint32_t md_spi_is_active_flag_rif_crcerrri(SPI_TypeDef *SPIx) -{ - return (uint32_t)(READ_BIT(SPIx->RIF, SPI_RIF_CRCERRRI_MSK)==(SPI_RIF_CRCERRRI_MSK)); -} - -/** - * @brief Check if Mode fault interrupt flag status is actived - * @param SPIx SPI Instance - * @retval None - */ -__STATIC_INLINE uint32_t md_spi_is_active_flag_rif_modfri(SPI_TypeDef *SPIx) -{ - return (uint32_t)(READ_BIT(SPIx->RIF, SPI_RIF_MODFRI_MSK)==(SPI_RIF_MODFRI_MSK)); -} - -/** - * @brief Check if Frame format error interrupt flag status is actived - * @param SPIx SPI Instance - * @retval None - */ -__STATIC_INLINE uint32_t md_spi_is_active_flag_rif_freri(SPI_TypeDef *SPIx) -{ - return (uint32_t)(READ_BIT(SPIx->RIF, SPI_RIF_FRERI_MSK)==(SPI_RIF_FRERI_MSK)); -} - -/** - * @} MD_SPI_RIF - */ - -/** @defgroup MD_SPI_IFM SPI Interrupt Masked Flag Status Register - * @{ - */ - -/** - * @brief Check if Transmit buffer empty interrupt flag status is actived - * @param SPIx SPI Instance - * @retval None - */ -__STATIC_INLINE uint32_t md_spi_is_active_flag_ifm_txefm(SPI_TypeDef *SPIx) -{ - return (uint32_t)(READ_BIT(SPIx->IFM, SPI_IFM_TXEFM_MSK)==(SPI_IFM_TXEFM_MSK)); -} - -/** - * @brief Check if Transmit buffer overrun interrupt flag status is actived - * @param SPIx SPI Instance - * @retval None - */ -__STATIC_INLINE uint32_t md_spi_is_active_flag_ifm_txovfm(SPI_TypeDef *SPIx) -{ - return (uint32_t)(READ_BIT(SPIx->IFM, SPI_IFM_TXOVFM_MSK)==(SPI_IFM_TXOVFM_MSK)); -} - -/** - * @brief Check if Transmit buffer underrun interrupt flag status is actived - * @param SPIx SPI Instance - * @retval None - */ -__STATIC_INLINE uint32_t md_spi_is_active_flag_ifm_txudfm(SPI_TypeDef *SPIx) -{ - return (uint32_t)(READ_BIT(SPIx->IFM, SPI_IFM_TXUDFM_MSK)==(SPI_IFM_TXUDFM_MSK)); -} - -/** - * @brief Check if Transmit buffer under threshold interrupt flag status is actived - * @param SPIx SPI Instance - * @retval None - */ -__STATIC_INLINE uint32_t md_spi_is_active_flag_ifm_txthfm(SPI_TypeDef *SPIx) -{ - return (uint32_t)(READ_BIT(SPIx->IFM, SPI_IFM_TXTHFM_MSK)==(SPI_IFM_TXTHFM_MSK)); -} - -/** - * @brief Check if Receive buffer full interrupt flag status is actived - * @param SPIx SPI Instance - * @retval None - */ -__STATIC_INLINE uint32_t md_spi_is_active_flag_ifm_rxffm(SPI_TypeDef *SPIx) -{ - return (uint32_t)(READ_BIT(SPIx->IFM, SPI_IFM_RXFFM_MSK)==(SPI_IFM_RXFFM_MSK)); -} - -/** - * @brief Check if Receive buffer overrun interrupt flag status is actived - * @param SPIx SPI Instance - * @retval None - */ -__STATIC_INLINE uint32_t md_spi_is_active_flag_ifm_rxovfm(SPI_TypeDef *SPIx) -{ - return (uint32_t)(READ_BIT(SPIx->IFM, SPI_IFM_RXOVFM_MSK)==(SPI_IFM_RXOVFM_MSK)); -} - -/** - * @brief Check if Receive buffer underrun interrupt flag status is actived - * @param SPIx SPI Instance - * @retval None - */ -__STATIC_INLINE uint32_t md_spi_is_active_flag_ifm_rxudfm(SPI_TypeDef *SPIx) -{ - return (uint32_t)(READ_BIT(SPIx->IFM, SPI_IFM_RXUDFM_MSK)==(SPI_IFM_RXUDFM_MSK)); -} - -/** - * @brief Check if Receive buffer over threshold interrupt flag status is actived - * @param SPIx SPI Instance - * @retval None - */ -__STATIC_INLINE uint32_t md_spi_is_active_flag_ifm_rxthfm(SPI_TypeDef *SPIx) -{ - return (uint32_t)(READ_BIT(SPIx->IFM, SPI_IFM_RXTHFM_MSK)==(SPI_IFM_RXTHFM_MSK)); -} - -/** - * @brief Check if CRC error interrupt flag status is actived - * @param SPIx SPI Instance - * @retval None - */ -__STATIC_INLINE uint32_t md_spi_is_active_flag_ifm_crcerrfm(SPI_TypeDef *SPIx) -{ - return (uint32_t)(READ_BIT(SPIx->IFM, SPI_IFM_CRCERRFM_MSK)==(SPI_IFM_CRCERRFM_MSK)); -} - -/** - * @brief Check if Mode fault interrupt flag status is actived - * @param SPIx SPI Instance - * @retval None - */ -__STATIC_INLINE uint32_t md_spi_is_active_flag_ifm_modffm(SPI_TypeDef *SPIx) -{ - return (uint32_t)(READ_BIT(SPIx->IFM, SPI_IFM_MODFFM_MSK)==(SPI_IFM_MODFFM_MSK)); -} - -/** - * @brief Check if Frame format error interrupt flag status is actived - * @param SPIx SPI Instance - * @retval None - */ -__STATIC_INLINE uint32_t md_spi_is_active_flag_ifm_frefm(SPI_TypeDef *SPIx) -{ - return (uint32_t)(READ_BIT(SPIx->IFM, SPI_IFM_FREFM_MSK)==(SPI_IFM_FREFM_MSK)); -} - -/** - * @} MD_SPI_IFM - */ - - - -/** - * @} MD_SPI_PF_Interrupt_Management - */ - - - -/** - * @} MD_SPI_Public_Macros - */ - -/* Public functions -----------------------------------------------------------*/ -/** @defgroup MD_SPI_Public_Functions SPI Public Functions - * @{ - */ - - - - -/** @defgroup MD_SPI_PF_Init SPI Initialization and De-Initialization functions - * @{ - */ - -ErrorStatus md_spi_init(SPI_TypeDef *SPIx, md_spi_inittypedef *SPI_InitStruct); -void md_spi_struct_init(md_spi_inittypedef *SPI_InitStruct); -void SPISingleWr(SPI_TypeDef *SPIx, uint8_t data); -uint8_t SPISSingleRd(SPI_TypeDef *SPIx); -/** - * @} MD_SPI_PF_Init - */ - -/** - * @} MD_SPI_Public_Functions - */ - -/** - * @} SPI - */ - -#endif - -/** - * @} Micro_Driver - */ - -#ifdef __cplusplus -} -#endif - -#endif - -/******************* (C) COPYRIGHT Eastsoft Microelectronics *****END OF FILE****/ diff --git a/bsp/essemi/es32f0271/libraries/ES32F027x_MD_StdPeriph_Driver/Include/md_syscfg.h b/bsp/essemi/es32f0271/libraries/ES32F027x_MD_StdPeriph_Driver/Include/md_syscfg.h deleted file mode 100644 index 0da1bfc14d..0000000000 --- a/bsp/essemi/es32f0271/libraries/ES32F027x_MD_StdPeriph_Driver/Include/md_syscfg.h +++ /dev/null @@ -1,1249 +0,0 @@ -/** - ****************************************************************************** - * @file md_SYSCFG.h - * @brief ES32F0271 SYSCFG HEAD File. - * - * @version V1.00.02 - * @date 30/11/2018 - * @author Eastsoft AE Team - * @note - * detailed description - * - * Copyright (C) 2018 Shanghai Eastsoft Microelectronics Co., Ltd. ALL rights reserved. - ******************************************************************************* - */ - -/* Define to prevent recursive inclusion -------------------------------------*/ -#ifndef __MD_SYSCFG_H__ -#define __MD_SYSCFG_H__ - -#ifdef __cplusplus -extern "C" { -#endif - -/* Includes -------------------------------------------------------------------*/ -#include -#include "es32f0271.h" -#include "reg_syscfg.h" - -/** @addtogroup Micro_Driver - * @{ - */ - -#if defined (SYSCFG) - -/** @defgroup SYSCFG SYSCFG - * @brief SYSCFG micro driver - * @{ - */ - -/* Private types --------------------------------------------------------------*/ -/* Private variables ----------------------------------------------------------*/ -/* Private constants ----------------------------------------------------------*/ -/* Private macros -------------------------------------------------------------*/ - -/* Public types ---------------------------------------------------------------*/ -/** @defgroup MD_SYSCFG_PT_INIT RCC Public Init structures - * @{ - */ - -/** - * @brief MD SYSCFG Init Structure definition - */ - - -/** - * @} MD_SYSCFG_PT_INIT - */ - -/* Public constants -----------------------------------------------------------*/ -/** @defgroup MD_SYSCFG_Public_Constants SYSCFG Public Constants - * @{ - */ - -/** @defgroup MD_SYSCFG_REMAP_REALMOD_FLAG Current Memory mapping Status - * @{ - */ -#define MD_SYSCFG_REALMOD_MAIN (0x00000000UL) /** @brief Main Flash memory mapped at 0x00000000 */ -#define MD_SYSCFG_REALMOD_SYSTEM (0x00000001UL) /** @brief System Flash memory mapped at 0x00000000 */ -#define MD_SYSCFG_REALMOD_SRAM (0x00000002UL) /** @brief SRAM mapped at 0x00000000 */ -/** - * @} MD_SYSCFG_REMAP_REALMOD_FLAG - */ - -/** @defgroup MD_SYSCFG_REMAP_MEMMOD_FLAG Memory mapping selection bits - * @{ - */ -#define MD_SYSCFG_MEMMOD_MAIN (0x00000000UL) /** @brief Main Flash memory mapped at 0x00000000 */ -#define MD_SYSCFG_MEMMOD_SYSTEM (0x00000001UL) /** @brief System Flash memory mapped at 0x00000000 */ -#define MD_SYSCFG_MEMMOD_SRAM (0x00000002UL) /** @brief SRAM mapped at 0x00000000 */ -/** - * @} MD_SYSCFG_REMAP_MEMMOD_FLAG - */ - -/** @defgroup MD_SYSCFG_IRSEL_PLR_FLAG IR Polarity - * @{ - */ -#define MD_SYSCFG_PLR_INV_SEL1_AND_SEL2 (0x00000000UL) /** @brief IR out = ~(SEL1 & SEL2) */ -#define MD_SYSCFG_PLR_SEL1_AND_SEL2 (0x00000001UL) /** @brief IR out = SEL1 & SEL2 */ -/** - * @} MD_SYSCFG_IRSEL_PLR_FLAG - */ - -/** @defgroup MD_SYSCFG_IRSEL_SEL2 IR Select 2 - * @{ - */ -#define MD_SYSCFG_SEL2_OFF (0x00000000UL) /** @brief 0000: OFF */ -#define MD_SYSCFG_SEL2_GP16C2T4_CH1 (0x00000001UL) /** @brief 0001: GP16C2T4_CH1 */ -#define MD_SYSCFG_SEL2_GP16C2T4_CH2 (0x00000002UL) /** @brief 0010: GP16C2T4_CH2 */ -#define MD_SYSCFG_SEL2_UART3_TX (0x00000003UL) /** @brief 0100: UART3_TX */ -#define MD_SYSCFG_SEL2_SUART2_TX (0x00000004UL) /** @brief 1000: SUART2_TX */ -/** - * @} MD_SYSCFG_IRSEL_SEL2 - */ - -/** @defgroup MD_SYSCFG_IRSEL_SEL1 IR Select 1 - * @{ - */ -#define MD_SYSCFG_SEL1_OFF (0x00000000UL) /** @brief 0000: OFF */ -#define MD_SYSCFG_SEL1_GP16C2T2_CH1 (0x00000001UL) /** @brief 0001: GP16C2T2_CH1 */ -#define MD_SYSCFG_SEL1_GP16C2T2_CH2 (0x00000002UL) /** @brief 0010: GP16C2T2_CH2 */ -#define MD_SYSCFG_SEL1_GP16C2T3_CH1 (0x00000003UL) /** @brief 0100: GP16C2T3_CH1 */ -#define MD_SYSCFG_SEL1_GP16C2T3_CH2 (0x00000004UL) /** @brief 1000: GP16C2T3_CH2 */ -/** - * @} MD_SYSCFG_IRSEL_SEL1 - */ - -/** @defgroup MD_SYSCFG_CFG_DBGH_EN DBG Halt enable bit - * @{ - */ -#define MD_SYSCFG_DBGH_EN_IWDT (0x00002000UL) -#define MD_SYSCFG_DBGH_EN_WWDT (0x00001000UL) -#define MD_SYSCFG_DBGH_EN_BS16T1 (0x00000200UL) -#define MD_SYSCFG_DBGH_EN_GP16C4T3 (0x00000100UL) -#define MD_SYSCFG_DBGH_EN_GP16C4T2 (0x00000080UL) -#define MD_SYSCFG_DBGH_EN_GP16C4T1 (0x00000040UL) -#define MD_SYSCFG_DBGH_EN_GP32C4T1 (0x00000020UL) -#define MD_SYSCFG_DBGH_EN_GP16C2T4 (0x00000010UL) -#define MD_SYSCFG_DBGH_EN_GP16C2T3 (0x00000008UL) -#define MD_SYSCFG_DBGH_EN_GP16C2T2 (0x00000004UL) -#define MD_SYSCFG_DBGH_EN_GP16C2T1 (0x00000002UL) -#define MD_SYSCFG_DBGH_EN_AD16C4T1 (0x00000001UL) -/** - * @} MD_SYSCFG_CFG_DBGH_EN - */ - -/** @defgroup MD_SYSCFG_CFG_VTST Voltage testing - * @{ - */ -#define MD_SYSCFG_VTST_LDO (0x00000000UL) /** @brief 00: LDO Buffer Voltage */ -#define MD_SYSCFG_VTST_BANDGAP_REF (0x00000001UL) /** @brief 01: BandGap Reference Voltage */ -#define MD_SYSCFG_VTST_LDO1V2 (0x00000002UL) /** @brief 10: LDO1V2 Voltage */ -#define MD_SYSCFG_VTST_LDO1V5 (0x00000003UL) /** @brief 11: LDO1V5 Voltage */ -/** - * @} MD_SYSCFG_CFG_VTST - */ - -/** @defgroup MD_SYSCFG_CFG_VRLS These bits are written by software to select the voltage reference level by the ADC/DAC - * @{ - */ -#define MD_SYSCFG_VRLS_1V5 (0x00000000UL) /** @brief 000: 1.5V */ -#define MD_SYSCFG_VRLS_2V (0x00000001UL) /** @brief 001: 2.0V */ -#define MD_SYSCFG_VRLS_2V5 (0x00000002UL) /** @brief 010: 2.5V */ -#define MD_SYSCFG_VRLS_3V (0x00000003UL) /** @brief 011: 3.0V */ -#define MD_SYSCFG_VRLS_3V5 (0x00000004UL) /** @brief 100: 3.5V */ -#define MD_SYSCFG_VRLS_4V (0x00000005UL) /** @brief 101: 4.0V */ -#define MD_SYSCFG_VRLS_4V5 (0x00000006UL) /** @brief 110: 4.5V */ -#define MD_SYSCFG_VRLS_5V (0x00000007UL) /** @brief 111: 5.0V(VDD5) */ -/** - * @} MD_SYSCFG_CFG_VRLS - */ - -/** @defgroup MD_SYSCFG_PWCON_PVLS These bits are written by software to select the voltage reference level by the ADC/DAC - * @{ - */ -#define MD_SYSCFG_PVLS_R1V9_F2V (0x00000000UL) /** @brief 0000: R-1.9V, F-2.0V */ -#define MD_SYSCFG_PVLS_R2V1_F2V2 (0x00000001UL) /** @brief 0001: R-2.1V, F-2.2V */ -#define MD_SYSCFG_PVLS_R2V3_F2V4 (0x00000002UL) /** @brief 0010: R-2.3V, F-2.4V */ -#define MD_SYSCFG_PVLS_R2V5_F2V6 (0x00000003UL) /** @brief 0011: R-2.5V, F-2.6V */ -#define MD_SYSCFG_PVLS_R2V7_F2V8 (0x00000004UL) /** @brief 0100: R-2.7V, F-2.8V */ -#define MD_SYSCFG_PVLS_R2V9_F3V (0x00000005UL) /** @brief 0101: R-2.9V, F-3.0V */ -#define MD_SYSCFG_PVLS_R3V1_F3V2 (0x00000006UL) /** @brief 0110: R-3.1V, F-3.2V */ -#define MD_SYSCFG_PVLS_R3V3_F3V4 (0x00000007UL) /** @brief 0111: R-3.3V, F-3.4V */ -#define MD_SYSCFG_PVLS_R3V5_F3V6 (0x00000008UL) /** @brief 1000: R-3.5V, F-3.6V */ -#define MD_SYSCFG_PVLS_R3V7_F3V8 (0x00000009UL) /** @brief 1001: R-3.7V, F-3.8V */ -#define MD_SYSCFG_PVLS_R3V9_F4V (0x0000000AUL) /** @brief 1010: R-3.9V, F-4.0V */ -#define MD_SYSCFG_PVLS_R4V1_F4V2 (0x0000000BUL) /** @brief 1011: R-4.1V, F-4.2V */ -#define MD_SYSCFG_PVLS_R4V3_F4V4 (0x0000000CUL) /** @brief 1100: R-4.3V, F-4.4V */ -#define MD_SYSCFG_PVLS_R4V5_F4V6 (0x0000000DUL) /** @brief 1101: R-4.5V, F-4.6V */ -#define MD_SYSCFG_PVLS_R4V7_F4V8 (0x0000000EUL) /** @brief 1110: R-4.7V, F-4.8V */ -#define MD_SYSCFG_PVLS_R4V9_F5V (0x0000000FUL) /** @brief 1111: R-4.9V, F-5.0V */ -/** - * @} MD_SYSCFG_PWCON_PVLS - */ - -/** @defgroup MD_SYSCFG_WKCON_LPLS Low Power Level Select - * @{ - */ -#define MD_SYSCFG_LPLS_LV0 (0x00000000UL) /** @brief 0 : Level 0, Sleep Mode (Normal) */ -#define MD_SYSCFG_LPLS_LV1 (0x00000001UL) /** @brief 1 : Level 1, Stop Mode (All Clock OFF) */ -#define MD_SYSCFG_LPLS_LV2 (0x00000002UL) /** @brief 2 : Level 2, Standby Mode (SRAM retention) */ -#define MD_SYSCFG_LPLS_LV3 (0x00000003UL) /** @brief 3 : Level 3, Low Power Mode (LDO off) */ -#define MD_SYSCFG_LPLS_LV4 (0x00000004UL) /** @brief 4 : Level 3, Ultra Low Power Mode(LDO off/BandGap off) */ -/** - * @} MD_SYSCFG_WKCON_LPLS - */ - -/** @defgroup MD_SYSCFG_WKCON_WKEG WKEGx:WKUPx pin edge sensitive type select - * @{ - */ -#define MD_SYSCFG_WKCON_WKEG_NRST (0x00000800UL) -#define MD_SYSCFG_WKCON_WKEG_PVD (0x00000400UL) -#define MD_SYSCFG_WKCON_WKEG_CMP0 (0x00000200UL) -#define MD_SYSCFG_WKCON_WKEG_RTC (0x00000100UL) -#define MD_SYSCFG_WKCON_WKEG_PIN7 (0x00000080UL) -#define MD_SYSCFG_WKCON_WKEG_PIN6 (0x00000040UL) -#define MD_SYSCFG_WKCON_WKEG_PIN5 (0x00000020UL) -#define MD_SYSCFG_WKCON_WKEG_PIN4 (0x00000010UL) -#define MD_SYSCFG_WKCON_WKEG_PIN3 (0x00000008UL) -#define MD_SYSCFG_WKCON_WKEG_PIN2 (0x00000004UL) -#define MD_SYSCFG_WKCON_WKEG_PIN1 (0x00000002UL) -#define MD_SYSCFG_WKCON_WKEG_PIN0 (0x00000001UL) -/** - * @} MD_SYSCFG_WKCON_WKEG - */ - -/** @defgroup MD_SYSCFG_WKCON_WKEN WKENx: Enable WKUPx pin or wakeup event - * @{ - */ -#define MD_SYSCFG_WKCON_WKEN_NRST (0x00000800UL) -#define MD_SYSCFG_WKCON_WKEN_PVD (0x00000400UL) -#define MD_SYSCFG_WKCON_WKEN_CMP0 (0x00000200UL) -#define MD_SYSCFG_WKCON_WKEN_RTC (0x00000100UL) -#define MD_SYSCFG_WKCON_WKEN_PIN7 (0x00000080UL) -#define MD_SYSCFG_WKCON_WKEN_PIN6 (0x00000040UL) -#define MD_SYSCFG_WKCON_WKEN_PIN5 (0x00000020UL) -#define MD_SYSCFG_WKCON_WKEN_PIN4 (0x00000010UL) -#define MD_SYSCFG_WKCON_WKEN_PIN3 (0x00000008UL) -#define MD_SYSCFG_WKCON_WKEN_PIN2 (0x00000004UL) -#define MD_SYSCFG_WKCON_WKEN_PIN1 (0x00000002UL) -#define MD_SYSCFG_WKCON_WKEN_PIN0 (0x00000001UL) -/** - * @} MD_SYSCFG_WKCON_WKEN - */ - -/** @defgroup MD_SYSCFG_WKSTAT_FG FGx: WKUPx pin or wakeup event flag - * @{ - */ -#define MD_SYSCFG_WKSTAT_FG_NRST (0x00000800UL) -#define MD_SYSCFG_WKSTAT_FG_PVD (0x00000400UL) -#define MD_SYSCFG_WKSTAT_FG_CMP0 (0x00000200UL) -#define MD_SYSCFG_WKSTAT_FG_RTC (0x00000100UL) -#define MD_SYSCFG_WKSTAT_FG_PIN7 (0x00000080UL) -#define MD_SYSCFG_WKSTAT_FG_PIN6 (0x00000040UL) -#define MD_SYSCFG_WKSTAT_FG_PIN5 (0x00000020UL) -#define MD_SYSCFG_WKSTAT_FG_PIN4 (0x00000010UL) -#define MD_SYSCFG_WKSTAT_FG_PIN3 (0x00000008UL) -#define MD_SYSCFG_WKSTAT_FG_PIN2 (0x00000004UL) -#define MD_SYSCFG_WKSTAT_FG_PIN1 (0x00000002UL) -#define MD_SYSCFG_WKSTAT_FG_PIN0 (0x00000001UL) -/** - * @} MD_SYSCFG_WKSTAT_FG - */ - -/** - * @} MD_SYSCFG_Public_Constants - */ - -/* Public macro ---------------------------------------------------------------*/ -/** @defgroup MD_SYSCFG_Public_Macros SYSCFG Public Macros - * @{ - */ - -/** - * @brief Get Current Memory mapping Status - * @param syscfg SYSCFG Instance - * @retval The retval can be one of the following values: - * @arg @ref MD_SYSCFG_REALMOD_MAIN - * @arg @ref MD_SYSCFG_REALMOD_SYSTEM - * @arg @ref MD_SYSCFG_REALMOD_SRAM - */ -__STATIC_INLINE uint32_t md_syscfg_get_remap_REALMOD(SYSCFG_TypeDef *syscfg) -{ - return (READ_BIT(syscfg->REMAP, SYSCFG_REMAP_REALMOD_MSK)>>SYSCFG_REMAP_REALMOD_POSS); -} -/** - * @brief Set Remap Main Flash Base Address Selection - * @note If set 0x1, it means second 4k Byte, If set 0x2, it means third 4k Byte, and so on. - * @param syscfg SYSCFG Instance - * @param efbase This parameter can be one of the following values: - * @arg Max Value 15 - * @arg Min Value 0 - * @retval None - */ -__STATIC_INLINE void md_syscfg_set_remap_efbase(SYSCFG_TypeDef *syscfg, uint32_t efbase) -{ - MODIFY_REG(syscfg->REMAP, SYSCFG_REMAP_EFBASE_MSK, (efbase<REMAP, SYSCFG_REMAP_EFBASE_MSK)>>SYSCFG_REMAP_EFBASE_POSS); -} -/** - * @brief Set Memory mapping selection bits - * @param syscfg SYSCFG Instance - * @param memmod This parameter can be one of the following values: - * @arg @ref MD_SYSCFG_MEMMOD_MAIN - * @arg @ref MD_SYSCFG_MEMMOD_SYSTEM - * @arg @ref MD_SYSCFG_MEMMOD_SRAM - * @retval None - */ -__STATIC_INLINE void md_syscfg_set_remap_memmod(SYSCFG_TypeDef *syscfg, uint32_t memmod) -{ - MODIFY_REG(syscfg->REMAP, SYSCFG_REMAP_MEMMOD_MSK, (memmod<REMAP, SYSCFG_REMAP_MEMMOD_MSK)>>SYSCFG_REMAP_MEMMOD_POSS); -} -/** - * @brief Set Start Remap bit - * @note This bit set High to start remapping process, that will be auto clear when process was finish. - * @param syscfg SYSCFG Instance - * @retval None - */ -__STATIC_INLINE void md_syscfg_enable_remap_remap(SYSCFG_TypeDef *syscfg) -{ - SET_BIT(syscfg->REMAP, SYSCFG_REMAP_REMAP_MSK); -} -/** - * @brief Get Start Remap bit - * @param syscfg SYSCFG Instance - * @retval State of bit (1 or 0). - */ -__STATIC_INLINE uint32_t md_syscfg_get_remap_remap(SYSCFG_TypeDef *syscfg) -{ - return (READ_BIT(syscfg->REMAP, SYSCFG_REMAP_REMAP_MSK)>>SYSCFG_REMAP_REMAP_POS); -} - -/** - * @brief Set IR Polarity - * @param syscfg SYSCFG Instance - * @param plr This parameter can be one of the following values: - * @arg @ref MD_SYSCFG_PLR_INV_SEL1_AND_SEL2 - * @arg @ref MD_SYSCFG_PLR_SEL1_AND_SEL2 - * @retval None - */ -__STATIC_INLINE void md_syscfg_set_irsel_plr(SYSCFG_TypeDef *syscfg, uint32_t plr) -{ - MODIFY_REG(syscfg->IRSEL, SYSCFG_IRSEL_PLR_MSK, (plr<IRSEL, SYSCFG_IRSEL_PLR_MSK)>>SYSCFG_IRSEL_PLR_POS); -} -/** - * @brief Set IR Select 2 - * @param syscfg SYSCFG Instance - * @param sel2 This parameter can be one of the following values: - * @arg @ref MD_SYSCFG_SEL2_OFF - * @arg @ref MD_SYSCFG_SEL2_GP16C2T4_CH1 - * @arg @ref MD_SYSCFG_SEL2_GP16C2T4_CH2 - * @arg @ref MD_SYSCFG_SEL2_UART3_TX - * @arg @ref MD_SYSCFG_SEL2_SUART2_TX - * @retval None - */ -__STATIC_INLINE void md_syscfg_set_irsel_sel2(SYSCFG_TypeDef *syscfg, uint32_t sel2) -{ - MODIFY_REG(syscfg->IRSEL, SYSCFG_IRSEL_SEL2_MSK, (sel2<IRSEL, SYSCFG_IRSEL_SEL2_MSK)>>SYSCFG_IRSEL_SEL2_POSS); -} -/** - * @brief Set IR Select 1 - * @param syscfg SYSCFG Instance - * @param sel1 This parameter can be one of the following values: - * @arg @ref MD_SYSCFG_SEL1_OFF - * @arg @ref MD_SYSCFG_SEL1_GP16C2T2_CH1 - * @arg @ref MD_SYSCFG_SEL1_GP16C2T2_CH2 - * @arg @ref MD_SYSCFG_SEL1_GP16C2T3_CH1 - * @arg @ref MD_SYSCFG_SEL1_GP16C2T3_CH2 - * @retval None - */ -__STATIC_INLINE void md_syscfg_set_irsel_sel1(SYSCFG_TypeDef *syscfg, uint32_t sel1) -{ - MODIFY_REG(syscfg->IRSEL, SYSCFG_IRSEL_SEL1_MSK, (sel1<IRSEL, SYSCFG_IRSEL_SEL1_MSK)>>SYSCFG_IRSEL_SEL1_POSS); -} - -/** - * @brief Set DBG Halt enable bit - * @note 0: The counter clock is fed even if the core is halted - * 1: The counter clock is stopped when the core is halted - * @param syscfg SYSCFG Instance - * @param sel1 This parameter can be one of the following values: - * @arg @ref MD_SYSCFG_DBGH_EN_IWDT - * @arg @ref MD_SYSCFG_DBGH_EN_WWDT - * @arg @ref MD_SYSCFG_DBGH_EN_BS16T1 - * @arg @ref MD_SYSCFG_DBGH_EN_GP16C4T3 - * @arg @ref MD_SYSCFG_DBGH_EN_GP16C4T2 - * @arg @ref MD_SYSCFG_DBGH_EN_GP16C4T1 - * @arg @ref MD_SYSCFG_DBGH_EN_GP32C4T1 - * @arg @ref MD_SYSCFG_DBGH_EN_GP16C2T4 - * @arg @ref MD_SYSCFG_DBGH_EN_GP16C2T3 - * @arg @ref MD_SYSCFG_DBGH_EN_GP16C2T2 - * @arg @ref MD_SYSCFG_DBGH_EN_GP16C2T1 - * @arg @ref MD_SYSCFG_DBGH_EN_AD16C4T1 - * @retval None - */ -__STATIC_INLINE void md_syscfg_set_cfg_dbgh_en(SYSCFG_TypeDef *syscfg, uint32_t sel1) -{ - MODIFY_REG(syscfg->CFG, SYSCFG_CFG_DBGH_EN_MSK, (sel1<CFG, SYSCFG_CFG_DBGH_EN_MSK)>>SYSCFG_CFG_DBGH_EN_POSS); -} -/** - * @brief PVD lock enable bit - * @param syscfg SYSCFG Instance - * @retval None - */ -__STATIC_INLINE void md_syscfg_enable_cfg_pvdlck(SYSCFG_TypeDef *syscfg) -{ - SET_BIT(syscfg->CFG, SYSCFG_CFG_PVD_LCK_MSK); -} -/** - * @brief PVD lock disable bit - * @param syscfg SYSCFG Instance - * @retval None - */ -__STATIC_INLINE void md_syscfg_disable_cfg_pvdlck(SYSCFG_TypeDef *syscfg) -{ - CLEAR_BIT(syscfg->CFG, SYSCFG_CFG_PVD_LCK_MSK); -} -/** - * @brief Get PVD lock bit - * @param syscfg SYSCFG Instance - * @retval State of bit (1 or 0). - */ -__STATIC_INLINE uint32_t md_syscfg_get_cfg_pvdlck(SYSCFG_TypeDef *syscfg) -{ - return (READ_BIT(syscfg->CFG, SYSCFG_CFG_PVD_LCK_MSK)>>SYSCFG_CFG_PVD_LCK_POS); -} -/** - * @brief Clock security system lock enable bit - * @param syscfg SYSCFG Instance - * @retval None - */ -__STATIC_INLINE void md_syscfg_enable_cfg_csslck(SYSCFG_TypeDef *syscfg) -{ - SET_BIT(syscfg->CFG, SYSCFG_CFG_CSS_LCK_MSK); -} -/** - * @brief Clock security system lock enable bit - * @param syscfg SYSCFG Instance - * @retval None - */ -__STATIC_INLINE void md_syscfg_disable_cfg_csslck(SYSCFG_TypeDef *syscfg) -{ - CLEAR_BIT(syscfg->CFG, SYSCFG_CFG_CSS_LCK_MSK); -} -/** - * @brief Clock security system lock enable bit - * @param syscfg SYSCFG Instance - * @retval State of bit (1 or 0). - */ -__STATIC_INLINE uint32_t md_syscfg_get_cfg_csslck(SYSCFG_TypeDef *syscfg) -{ - return (READ_BIT(syscfg->CFG, SYSCFG_CFG_CSS_LCK_MSK)>>SYSCFG_CFG_CSS_LCK_POS); -} -/** - * @brief Cortex-M0 LOCKUP bit enable bit - * @note This bit is set by software and cleared by a system reset. - * It can be use to enable and lock the connection of Cortex-M0 LOCKUP (Hardfault) output to AD16C4T/GP16C2T1-4 Break input. - * @note 1: Cortex-M0 LOCKUP output connected to AD16C4T/GP16C2T1/GP16C2T2/GP16C2T3/GP16C2T4 Break input - * @param syscfg SYSCFG Instance - * @retval None - */ -__STATIC_INLINE void md_syscfg_enable_cfg_cpulck(SYSCFG_TypeDef *syscfg) -{ - SET_BIT(syscfg->CFG, SYSCFG_CFG_CPU_LCK_MSK); -} -/** - * @brief Cortex-M0 LOCKUP bit disable bit - * @note 0: Cortex-M0 LOCKUP output disconnected from AD16C4T / GP16C2T1-4 Break input - * @param syscfg SYSCFG Instance - * @retval None - */ -__STATIC_INLINE void md_syscfg_disable_cfg_cpulck(SYSCFG_TypeDef *syscfg) -{ - CLEAR_BIT(syscfg->CFG, SYSCFG_CFG_CPU_LCK_MSK); -} -/** - * @brief Get Cortex-M0 LOCKUP bit - * @param syscfg SYSCFG Instance - * @retval State of bit (1 or 0). - */ -__STATIC_INLINE uint32_t md_syscfg_get_cfg_cpulck(SYSCFG_TypeDef *syscfg) -{ - return (READ_BIT(syscfg->CFG, SYSCFG_CFG_CPU_LCK_MSK)>>SYSCFG_CFG_CPU_LCK_POS); -} -/** - * @brief Set Voltage testing, This bit is set and cleared by software. - * @param syscfg SYSCFG Instance - * @param vtst This parameter can be one of the following values: - * @arg @ref MD_SYSCFG_VTST_LDO - * @arg @ref MD_SYSCFG_VTST_BANDGAP_REF - * @arg @ref MD_SYSCFG_VTST_LDO1V2 - * @arg @ref MD_SYSCFG_VTST_LDO1V5 - * @retval None - */ -__STATIC_INLINE void md_syscfg_set_cfg_vtst(SYSCFG_TypeDef *syscfg, uint32_t vtst) -{ - MODIFY_REG(syscfg->CFG, SYSCFG_CFG_VTST_MSK, (vtst<CFG, SYSCFG_CFG_VTST_MSK)>>SYSCFG_CFG_VTST_POSS); -} -/** - * @brief Enable External NRST Pin reset request - * @param syscfg SYSCFG Instance - * @retval None - */ -__STATIC_INLINE void md_syscfg_enable_cfg_nrstreq(SYSCFG_TypeDef *syscfg) -{ - SET_BIT(syscfg->CFG, SYSCFG_CFG_NRSTREQ_MSK); -} -/** - * @brief Disable External NRST Pin reset request - * @param syscfg SYSCFG Instance - * @retval None - */ -__STATIC_INLINE void md_syscfg_disable_cfg_nrstreq(SYSCFG_TypeDef *syscfg) -{ - CLEAR_BIT(syscfg->CFG, SYSCFG_CFG_NRSTREQ_MSK); -} -/** - * @brief External NRST Pin reset request - * @param syscfg SYSCFG Instance - * @retval State of bit (1 or 0). - */ -__STATIC_INLINE uint32_t md_syscfg_get_cfg_nrstreq(SYSCFG_TypeDef *syscfg) -{ - return (READ_BIT(syscfg->CFG, SYSCFG_CFG_NRSTREQ_MSK)>>SYSCFG_CFG_NRSTREQ_POS); -} -/** - * @brief ADC/DAC current generator enabled - * @param syscfg SYSCFG Instance - * @retval None - */ -__STATIC_INLINE void md_syscfg_enable_cfg_currgen(SYSCFG_TypeDef *syscfg) -{ - SET_BIT(syscfg->CFG, SYSCFG_CFG_CURRGEN_MSK); -} -/** - * @brief ADC/DAC current generator disabled - * @param syscfg SYSCFG Instance - * @retval None - */ -__STATIC_INLINE void md_syscfg_disable_cfg_currgen(SYSCFG_TypeDef *syscfg) -{ - CLEAR_BIT(syscfg->CFG, SYSCFG_CFG_CURRGEN_MSK); -} -/** - * @brief ADC/DAC current generator status - * @param syscfg SYSCFG Instance - * @retval State of bit (1 or 0). - */ -__STATIC_INLINE uint32_t md_syscfg_get_cfg_currgen(SYSCFG_TypeDef *syscfg) -{ - return (READ_BIT(syscfg->CFG, SYSCFG_CFG_CURRGEN_MSK)>>SYSCFG_CFG_CURRGEN_POS); -} -/** - * @brief Temperature sensor enabled - * @param syscfg SYSCFG Instance - * @retval None - */ -__STATIC_INLINE void md_syscfg_enable_cfg_tempen(SYSCFG_TypeDef *syscfg) -{ - SET_BIT(syscfg->CFG, SYSCFG_CFG_TEMPEN_MSK); -} -/** - * @brief Temperature sensor disabled - * @param syscfg SYSCFG Instance - * @retval None - */ -__STATIC_INLINE void md_syscfg_disable_cfg_tempen(SYSCFG_TypeDef *syscfg) -{ - CLEAR_BIT(syscfg->CFG, SYSCFG_CFG_TEMPEN_MSK); -} -/** - * @brief Get Temperature sensor status - * @param syscfg SYSCFG Instance - * @retval State of bit (1 or 0). - */ -__STATIC_INLINE uint32_t md_syscfg_get_cfg_tempen(SYSCFG_TypeDef *syscfg) -{ - return (READ_BIT(syscfg->CFG, SYSCFG_CFG_TEMPEN_MSK)>>SYSCFG_CFG_TEMPEN_POS); -} -/** - * @brief Voltage reference enabled - * @param syscfg SYSCFG Instance - * @retval None - */ -__STATIC_INLINE void md_syscfg_enable_cfg_vrefen(SYSCFG_TypeDef *syscfg) -{ - SET_BIT(syscfg->CFG, SYSCFG_CFG_VREFEN_MSK); -} -/** - * @brief Voltage reference disabled - * @param syscfg SYSCFG Instance - * @retval None - */ -__STATIC_INLINE void md_syscfg_disable_cfg_vrefen(SYSCFG_TypeDef *syscfg) -{ - CLEAR_BIT(syscfg->CFG, SYSCFG_CFG_VREFEN_MSK); -} -/** - * @brief Get Voltage reference status - * @param syscfg SYSCFG Instance - * @retval State of bit (1 or 0). - */ -__STATIC_INLINE uint32_t md_syscfg_get_cfg_vrefen(SYSCFG_TypeDef *syscfg) -{ - return (READ_BIT(syscfg->CFG, SYSCFG_CFG_VREFEN_MSK)>>SYSCFG_CFG_VREFEN_POS); -} -/** - * @brief Set These bits are written by software to select the voltage reference level by the ADC/DAC: - * @param syscfg SYSCFG Instance - * @param vlrs This parameter can be one of the following values: - * @arg @ref MD_SYSCFG_VRLS_1V5 - * @arg @ref MD_SYSCFG_VRLS_2V - * @arg @ref MD_SYSCFG_VRLS_2V5 - * @arg @ref MD_SYSCFG_VRLS_3V - * @arg @ref MD_SYSCFG_VRLS_3V5 - * @arg @ref MD_SYSCFG_VRLS_4V - * @arg @ref MD_SYSCFG_VRLS_4V5 - * @arg @ref MD_SYSCFG_VRLS_5V - * @retval None - */ -__STATIC_INLINE void md_syscfg_set_cfg_vlrs(SYSCFG_TypeDef *syscfg, uint32_t vlrs) -{ - MODIFY_REG(syscfg->CFG, SYSCFG_CFG_VRLS_MSK, (vlrs<CFG, SYSCFG_CFG_VRLS_MSK)>>SYSCFG_CFG_VRLS_POSS); -} - -/** - * @brief WKCON0-7 IO Setting Value LOCKED enabled - * @param syscfg SYSCFG Instance - * @retval None - */ -__STATIC_INLINE void md_syscfg_enable_pwcon_iolock(SYSCFG_TypeDef *syscfg) -{ - MODIFY_REG(syscfg->PWCON, SYSCFG_PWCON_IOLOCK_MSK, (ENABLE<PWCON, SYSCFG_PWCON_IOLOCK_MSK, (DISABLE<PWCON, SYSCFG_PWCON_IOLOCK_MSK)>>SYSCFG_PWCON_IOLOCK_POS); -} -/** - * @brief Set BandGap Trimming Value - * @param syscfg SYSCFG Instance - * @param bgtrim This parameter can be one of the following values: - * @arg Max Value 15 - * @arg Min Value 0 - * @retval None - */ -__STATIC_INLINE void md_syscfg_set_pwcon_bgtrim(SYSCFG_TypeDef *syscfg, uint32_t bgtrim) -{ - MODIFY_REG(syscfg->PWCON, SYSCFG_PWCON_BGTRIM_MSK, (bgtrim<PWCON, SYSCFG_PWCON_BGTRIM_MSK)>>SYSCFG_PWCON_BGTRIM_POSS); -} -/** - * @brief HSI auto calibration result value LOCK - * @param syscfg SYSCFG Instance - * @retval None - */ -__STATIC_INLINE void md_syscfg_enable_pwcon_hrclock(SYSCFG_TypeDef *syscfg) -{ - SET_BIT(syscfg->PWCON, SYSCFG_PWCON_HRCLOCK_MSK); -} -/** - * @brief HSI auto calibration result value unLOCK - * @param syscfg SYSCFG Instance - * @retval None - */ -__STATIC_INLINE void md_syscfg_disable_pwcon_hrclock(SYSCFG_TypeDef *syscfg) -{ - CLEAR_BIT(syscfg->PWCON, SYSCFG_PWCON_HRCLOCK_MSK); -} -/** - * @brief Get HSI auto calibration result value - * @param syscfg SYSCFG Instance - * @retval State of bit (1 or 0). - */ -__STATIC_INLINE uint32_t md_syscfg_get_pwcon_hrclock(SYSCFG_TypeDef *syscfg) -{ - return (READ_BIT(syscfg->PWCON, SYSCFG_PWCON_HRCLOCK_MSK)>>SYSCFG_PWCON_HRCLOCK_POS); -} -/** - * @brief Set HSI auto calibration result value - * @param syscfg SYSCFG Instance - * @param hsitrim This parameter can be one of the following values: - * @arg Max Value 255 - * @arg Min Value 0 - * @retval None - */ -__STATIC_INLINE void md_syscfg_set_pwcon_hrctrim(SYSCFG_TypeDef *syscfg, uint32_t hsitrim) -{ - MODIFY_REG(syscfg->PWCON, SYSCFG_PWCON_HRCTRIM_MSK, (hsitrim<PWCON, SYSCFG_PWCON_HRCTRIM_MSK)>>SYSCFG_PWCON_HRCTRIM_POSS); -} -/** - * @brief Set LSI Driver Select - * @param syscfg SYSCFG Instance - * @param loscdrv This parameter can be one of the following values: - * @arg Max Value 7 - * @arg Min Value 0 - * @retval None - */ -__STATIC_INLINE void md_syscfg_set_pwcon_loscdrv(SYSCFG_TypeDef *syscfg, uint32_t loscdrv) -{ - MODIFY_REG(syscfg->PWCON, SYSCFG_PWCON_LOSCDRV_MSK, (loscdrv<PWCON, SYSCFG_PWCON_LOSCDRV_MSK)>>SYSCFG_PWCON_LOSCDRV_POSS); -} -/** - * @brief Power voltage detector(PVD) enable - * @param syscfg SYSCFG Instance - * @retval None - */ -__STATIC_INLINE void md_syscfg_enable_pwcon_pvden(SYSCFG_TypeDef *syscfg) -{ - SET_BIT(syscfg->PWCON, SYSCFG_PWCON_PVDEN_MSK); -} -/** - * @brief Power voltage detector(PVD) disable - * @param syscfg SYSCFG Instance - * @retval None - */ -__STATIC_INLINE void md_syscfg_disable_pwcon_pvden(SYSCFG_TypeDef *syscfg) -{ - CLEAR_BIT(syscfg->PWCON, SYSCFG_PWCON_PVDEN_MSK); -} -/** - * @brief Get Power voltage detector(PVD) status - * @param syscfg SYSCFG Instance - * @retval State of bit (1 or 0). - */ -__STATIC_INLINE uint32_t md_syscfg_get_pwcon_pvden(SYSCFG_TypeDef *syscfg) -{ - return (READ_BIT(syscfg->PWCON, SYSCFG_PWCON_PVDEN_MSK)>>SYSCFG_PWCON_PVDEN_POS); -} -/** - * @brief Set power voltage detector - * @note These bits are written by software to select the voltage threshold detected by the power voltage detector - * @param syscfg SYSCFG Instance - * @param pvls This parameter can be one of the following values: - * @arg @ref MD_SYSCFG_PVLS_R1V9_F2V - * @arg @ref MD_SYSCFG_PVLS_R2V1_F2V2 - * @arg @ref MD_SYSCFG_PVLS_R2V3_F2V4 - * @arg @ref MD_SYSCFG_PVLS_R2V5_F2V6 - * @arg @ref MD_SYSCFG_PVLS_R2V7_F2V8 - * @arg @ref MD_SYSCFG_PVLS_R2V9_F3V - * @arg @ref MD_SYSCFG_PVLS_R3V1_F3V2 - * @arg @ref MD_SYSCFG_PVLS_R3V3_F3V4 - * @arg @ref MD_SYSCFG_PVLS_R3V5_F3V6 - * @arg @ref MD_SYSCFG_PVLS_R3V7_F3V8 - * @arg @ref MD_SYSCFG_PVLS_R3V9_F4V - * @arg @ref MD_SYSCFG_PVLS_R4V1_F4V2 - * @arg @ref MD_SYSCFG_PVLS_R4V3_F4V4 - * @arg @ref MD_SYSCFG_PVLS_R4V5_F4V6 - * @arg @ref MD_SYSCFG_PVLS_R4V7_F4V8 - * @arg @ref MD_SYSCFG_PVLS_R4V9_F5V - * @retval None - */ -__STATIC_INLINE void md_syscfg_set_pwcon_pvls(SYSCFG_TypeDef *syscfg, uint32_t pvls) -{ - MODIFY_REG(syscfg->PWCON, SYSCFG_PWCON_PVLS_MSK, (pvls<PWCON, SYSCFG_PWCON_PVLS_MSK)>>SYSCFG_PWCON_PVLS_POSS); -} - -/** - * @brief Clear Wake Flag enable - * @param syscfg SYSCFG Instance - * @retval None - */ -__STATIC_INLINE void md_syscfg_enable_wkcon_wkclr(SYSCFG_TypeDef *syscfg) -{ - SET_BIT(syscfg->WKCON, SYSCFG_WKCON_WKCLR_MSK); -} -/** - * @brief Set Low Power Level Select - * @param syscfg SYSCFG Instance - * @param lpls The parameter can be one of the following values: - * @arg @ref MD_SYSCFG_LPLS_LV0 - * @arg @ref MD_SYSCFG_LPLS_LV1 - * @arg @ref MD_SYSCFG_LPLS_LV2 - * @arg @ref MD_SYSCFG_LPLS_LV3 - * @arg @ref MD_SYSCFG_LPLS_LV4 - * @retval None - */ -__STATIC_INLINE void md_syscfg_set_wkcon_lpls(SYSCFG_TypeDef *syscfg, uint32_t lpls) -{ - MODIFY_REG(syscfg->WKCON, SYSCFG_WKCON_LPLS_MSK, (lpls<WKCON, SYSCFG_WKCON_LPLS_MSK)>>SYSCFG_WKCON_LPLS_POSS); -} -/** - * @brief Set WKUPx pin edge sensitive type select - * @note 0 : Falling Edge-sensitive (default) - * 1 : Rising Edge-sensitive - * @param syscfg SYSCFG Instance - * @param wkeg This parameter can be one of the following values: - * @arg @ref MD_SYSCFG_WKCON_WKEG_NRST - * @arg @ref MD_SYSCFG_WKCON_WKEG_PVD - * @arg @ref MD_SYSCFG_WKCON_WKEG_CMP0 - * @arg @ref MD_SYSCFG_WKCON_WKEG_RTC - * @arg @ref MD_SYSCFG_WKCON_WKEG_PIN7 - * @arg @ref MD_SYSCFG_WKCON_WKEG_PIN6 - * @arg @ref MD_SYSCFG_WKCON_WKEG_PIN5 - * @arg @ref MD_SYSCFG_WKCON_WKEG_PIN4 - * @arg @ref MD_SYSCFG_WKCON_WKEG_PIN3 - * @arg @ref MD_SYSCFG_WKCON_WKEG_PIN2 - * @arg @ref MD_SYSCFG_WKCON_WKEG_PIN1 - * @arg @ref MD_SYSCFG_WKCON_WKEG_PIN0 - * @retval None - */ -__STATIC_INLINE void md_syscfg_set_wkcon_wkeg(SYSCFG_TypeDef *syscfg, uint32_t wkeg) -{ - MODIFY_REG(syscfg->WKCON, SYSCFG_WKCON_WKEG_MSK, (wkeg<WKCON, SYSCFG_WKCON_WKEG_MSK)>>SYSCFG_WKCON_WKEG_POSS); -} - -/** - * @brief Set Enable WKUPx pin or wakeup event - * @note 0: WKUPx pin is used for general purpose I/Os. An event on the WKUPx pin does not wakeup the device from Standby mode. - * 1: WKUPx pin is used for wakeup from Standby mode. - * @param syscfg SYSCFG Instance - * @param wken This parameter can be one of the following values: - * @arg @ref MD_SYSCFG_WKCON_WKEN_NRST - * @arg @ref MD_SYSCFG_WKCON_WKEN_PVD - * @arg @ref MD_SYSCFG_WKCON_WKEN_CMP0 - * @arg @ref MD_SYSCFG_WKCON_WKEN_RTC - * @arg @ref MD_SYSCFG_WKCON_WKEN_PIN7 - * @arg @ref MD_SYSCFG_WKCON_WKEN_PIN6 - * @arg @ref MD_SYSCFG_WKCON_WKEN_PIN5 - * @arg @ref MD_SYSCFG_WKCON_WKEN_PIN4 - * @arg @ref MD_SYSCFG_WKCON_WKEN_PIN3 - * @arg @ref MD_SYSCFG_WKCON_WKEN_PIN2 - * @arg @ref MD_SYSCFG_WKCON_WKEN_PIN1 - * @arg @ref MD_SYSCFG_WKCON_WKEN_PIN0 - * @retval None - */ -__STATIC_INLINE void md_syscfg_set_wkcon_wken(SYSCFG_TypeDef *syscfg, uint32_t wken) -{ - MODIFY_REG(syscfg->WKCON, SYSCFG_WKCON_WKEN_MSK, (wken<WKCON, SYSCFG_WKCON_WKEN_MSK)>>SYSCFG_WKCON_WKEN_POSS); -} -/** - * @brief Set SYSCFG WCON register - * @param syscfg SYSCFG Instance - * @param uint32_t wcon - * @retval None - */ -__STATIC_INLINE void md_syscfg_set_wkcon(SYSCFG_TypeDef *syscfg, uint32_t wcon) -{ - WRITE_REG(syscfg->WKCON, wcon); -} - -/** - * @brief Get Wakeup Flag - * @param syscfg SYSCFG Instance - * @retval State of bit (1 or 0). - */ -__STATIC_INLINE uint32_t md_syscfg_get_wkstat_flag(SYSCFG_TypeDef *syscfg) -{ - return (READ_BIT(syscfg->WKSTAT, SYSCFG_WKSTAT_FLAG_MSK)>>SYSCFG_WKSTAT_FLAG_POS); -} -/** - * @brief Get WKCON pin0 or wakeup event flag. - * @note When this bit was set to 1, a wakeup event occurs. - * @param syscfg SYSCFG Instance - * @retval State of bit. - * @arg @ref MD_SYSCFG_WKSTAT_FG_NRST - * @arg @ref MD_SYSCFG_WKSTAT_FG_PVD - * @arg @ref MD_SYSCFG_WKSTAT_FG_CMP0 - * @arg @ref MD_SYSCFG_WKSTAT_FG_RTC - * @arg @ref MD_SYSCFG_WKSTAT_FG_PIN7 - * @arg @ref MD_SYSCFG_WKSTAT_FG_PIN6 - * @arg @ref MD_SYSCFG_WKSTAT_FG_PIN5 - * @arg @ref MD_SYSCFG_WKSTAT_FG_PIN4 - * @arg @ref MD_SYSCFG_WKSTAT_FG_PIN3 - * @arg @ref MD_SYSCFG_WKSTAT_FG_PIN2 - * @arg @ref MD_SYSCFG_WKSTAT_FG_PIN1 - * @arg @ref MD_SYSCFG_WKSTAT_FG_PIN0 - */ -__STATIC_INLINE uint32_t md_syscfg_get_wkstat_fg(SYSCFG_TypeDef *syscfg) -{ - return (READ_BIT(syscfg->WKSTAT, SYSCFG_WKSTAT_FG_MSK)>>SYSCFG_WKSTAT_FG_POSS); -} - - -/** - * @brief Set Backup Register 0. - * @note This field was saved in the always on block, reset by power reset. - * @param syscfg SYSCFG Instance - * @param bkreg0 This parameter can be one of the following values: - * @arg Max Value 0xFFFFFFFF - * @arg Min Value 0 - * @retval None - */ -__STATIC_INLINE void md_syscfg_set_bkreg0(SYSCFG_TypeDef *syscfg, uint32_t bkreg0) -{ - MODIFY_REG(syscfg->BKREG0, SYSCFG_BKREG0_BKREG0_MSK, (bkreg0<BKREG0, SYSCFG_BKREG0_BKREG0_MSK)>>SYSCFG_BKREG0_BKREG0_POSS); -} - -/** - * @brief Set Backup Register 1. - * @note This field was saved in the always on block, reset by power reset. - * @param syscfg SYSCFG Instance - * @param bkreg1 This parameter can be one of the following values: - * @arg Max Value 0xFFFFFFFF - * @arg Min Value 0 - * @retval None - */ -__STATIC_INLINE void md_syscfg_set_bkreg1(SYSCFG_TypeDef *syscfg, uint32_t bkreg1) -{ - MODIFY_REG(syscfg->BKREG1, SYSCFG_BKREG1_BKREG1_MSK, (bkreg1<BKREG1, SYSCFG_BKREG1_BKREG1_MSK)>>SYSCFG_BKREG1_BKREG1_POSS); -} - -/** - * @brief Set Backup Register 2. - * @note This field was saved in the always on block, reset by power reset. - * @param syscfg SYSCFG Instance - * @param bkreg2 This parameter can be one of the following values: - * @arg Max Value 0xFFFFFFFF - * @arg Min Value 0 - * @retval None - */ -__STATIC_INLINE void md_syscfg_set_bkreg2(SYSCFG_TypeDef *syscfg, uint32_t bkreg2) -{ - MODIFY_REG(syscfg->BKREG2, SYSCFG_BKREG2_BKREG2_MSK, (bkreg2<BKREG2, SYSCFG_BKREG2_BKREG2_MSK)>>SYSCFG_BKREG2_BKREG2_POSS); -} - -/** - * @brief Set Backup Register 3. - * @note This field was saved in the always on block, reset by power reset. - * @param syscfg SYSCFG Instance - * @param bkreg3 This parameter can be one of the following values: - * @arg Max Value 0xFFFFFFFF - * @arg Min Value 0 - * @retval None - */ -__STATIC_INLINE void md_syscfg_set_bkreg3(SYSCFG_TypeDef *syscfg, uint32_t bkreg3) -{ - MODIFY_REG(syscfg->BKREG3, SYSCFG_BKREG3_BKREG3_MSK, (bkreg3<BKREG3, SYSCFG_BKREG3_BKREG3_MSK)>>SYSCFG_BKREG3_BKREG3_POSS); -} - -/** - * @} MD_SYSCFG_Public_Macros - */ - -/* Public functions -----------------------------------------------------------*/ -/** @defgroup MD_SYSCFG_Public_Functions SYSCFG Public Functions - * @{ - */ - -/** @defgroup MD_SYSCFG_PF_Basic_Configuration Basic Configuration - * @{ - */ - -/** - * @} MD_SYSCFG_PF_Basic_Configuration - */ - -/** @defgroup MD_SYSCFG_PF_Data_Access Data Access - * @{ - */ - -/** - * @} MD_SYSCFG_PF_Data_Access - */ - -/** @defgroup MD_SYSCFG_PF_Init Initialization and de-initialization functions - * @{ - */ - -/** - * @} MD_SYSCFG_PF_Init - */ - -/** - * @} MD_SYSCFG_Public_Functions - */ - -#endif - -/** - * @} SYSCFG - */ - -/** - * @} Micro_Driver - */ - - -#ifdef __cplusplus -} - -#endif - -#endif - -/******************* (C) COPYRIGHT Eastsoft Microelectronics *****END OF FILE****/ diff --git a/bsp/essemi/es32f0271/libraries/ES32F027x_MD_StdPeriph_Driver/Include/md_tick.h b/bsp/essemi/es32f0271/libraries/ES32F027x_MD_StdPeriph_Driver/Include/md_tick.h deleted file mode 100644 index f8570471e9..0000000000 --- a/bsp/essemi/es32f0271/libraries/ES32F027x_MD_StdPeriph_Driver/Include/md_tick.h +++ /dev/null @@ -1,433 +0,0 @@ -/** - ****************************************************************************** - * @file md_TICK.h - * @brief ES32F0271 TICK HEAD File. - * - * @version V1.00.01 - * @date 11/20/2018 - * @author Eastsoft AE Team - * @note - * detailed description - * - * Copyright (C) 2018 Shanghai Eastsoft Microelectronics Co., Ltd. ALL rights reserved. - * - ******************************************************************************* - */ - -/* Define to prevent recursive inclusion -------------------------------------*/ -#ifndef __MD_TICK_H__ -#define __MD_TICK_H__ - -#ifdef __cplusplus -extern "C" { -#endif - -/* Includes -------------------------------------------------------------------*/ -#include "es32f0271.h" -#include "reg_tick.h" - -/** @addtogroup Micro_Driver - * @{ - */ - -#if defined (TICK) - -/** @defgroup TICK TICK - * @brief TICK micro driver - * @{ - */ - -/* Private types --------------------------------------------------------------*/ -/* Private variables ----------------------------------------------------------*/ -/* Private constants ----------------------------------------------------------*/ -/* Private macros -------------------------------------------------------------*/ - -/* Public types ---------------------------------------------------------------*/ - -/** - * @brief MD TICK Parameter Structure definition - */ - -/* Public constants -----------------------------------------------------------*/ -/** @defgroup MD_TICK_Public_Constants TICK Public Constants - * @{ - */ - -/** - * @} MD_TICK_Public_Constants - */ - -/* Public macro ---------------------------------------------------------------*/ -/** @defgroup MD_TICK_Public_Macros TICK Public Macros - * @{ - */ - -/** @defgroup MD_TICK_PM_WRITE_READ Common write and read registers Macros - * @{ - */ - -/** - * @brief Write a value in TICK register - * @param __INSTANCE__ TICK Instance - * @param __REG__ Register to be written - * @param __VALUE__ Value to be written in the register - * @retval None - */ -#define MD_TICK_WRITEREG(__INSTANCE__, __REG__, __VALUE__) WRITE_REG(__INSTANCE__->__REG__, (__VALUE__)) - -/** - * @brief Read a value in TICK register - * @param __INSTANCE__ TICK Instance - * @param __REG__ Register to be read - * @retval Register value - */ -#define MD_TICK_READREG(__INSTANCE__, __REG__) READ_REG(__INSTANCE__->__REG__) - -/** - * @brief Modify value in TICK register - * @param __INSTANCE__ TICK Instance - * @param __REG__ Register to be written - * @param __MASK__ Mask value to be written in the register - * @param __VALUE__ Value to be written in the register - * @retval None - */ -#define MD_TICK_MODIFYREG(__INSTANCE__, __REG__, __MASK__, __VALUE__) MODIFY_REG(__INSTANCE__->__REG__, __MASK__, (__VALUE__)) - -/** - * @brief Set bit value in TICK register - * @param __INSTANCE__ TICK Instance - * @param __REG__ Register to be read - * @param __MASK__ Mask value to be set in the register - * @retval None - */ -#define MD_TICK_SET_BIT(__INSTANCE__, __REG__, __MASK__) SET_BIT(__INSTANCE__->__REG__, __MASK__) - -/** - * @brief Clear bit value in TICK register - * @param __INSTANCE__ TICK Instance - * @param __REG__ Register to be read - * @param __MASK__ Mask value to be cleased in the register - * @retval None - */ -#define MD_TICK_CLEAR_BIT(__INSTANCE__, __REG__, __MASK__) CLEAR_BIT(__INSTANCE__->__REG__, __MASK__) - -/** - * @brief Read bit value in TICK register - * @param __INSTANCE__ TICK Instance - * @param __REG__ Register to be read - * @param __MASK__ Mask value to be read in the register - * @retval Register bit value - */ -#define MD_TICK_READBIT(__INSTANCE__, __REG__, __MASK__) READ_BIT(__INSTANCE__->__REG__, __MASK__) - -/** - * @} MD_TICK_PM_WRITE_READ - */ - -/** @defgroup MD_TICK_Macro_Drivers TICK Public Macro Drivers - * @{ - */ - -/** - * @brief Set TICK CSR - * @param @arg Max Value 0x7 - * @arg Min Value 0x0 - * @retval None - */ -__STATIC_INLINE void md_tick_set_csr(uint32_t U32) -{ - MD_TICK_WRITEREG(TICK, CSR, U32); -} - -/** - * @brief Get TICK CSR - * @param None - * @retval The retval can be one of the following values: - * @arg Max Value 0x10007 - * @arg Min Value 0x0 - */ -__STATIC_INLINE uint32_t md_tick_get_csr(void) -{ - return (MD_TICK_READREG(TICK, CSR)); -} - -/** - * @brief Get TICK CSR Count Flag - * @param None - * @retval The retval can be one of the following values: - * @arg Max Value 0x1 - * @arg Min Value 0x0 - */ -__STATIC_INLINE uint8_t md_tick_is_active_csr_countflag(void) -{ - return (MD_TICK_READBIT(TICK, CSR, TICK_CSR_COUNTFLAG_MSK)>>TICK_CSR_COUNTFLAG_POS); -} - -/** - * @brief Set TICK CSR Clock Source - * @param @arg Max Value 0x1 - * @arg Min Value 0x0 - * @retval None - */ -__STATIC_INLINE void md_tick_set_csr_clksource(uint32_t ClkSource) -{ - MD_TICK_MODIFYREG(TICK, CSR, TICK_CSR_CLKSOURCE_MSK, (ClkSource<>TICK_CSR_CLKSOURCE_POS); -} - -/** - * @brief Enable TICK CSR Tick Interrupt - * @param None - * @retval None - */ -__STATIC_INLINE void md_tick_enable_csr_tickint(void) -{ - MD_TICK_SET_BIT(TICK, CSR, TICK_CSR_TICKINT_MSK); -} - -/** - * @brief Disable TICK CSR Tick Interrupt - * @param None - * @retval None - */ -__STATIC_INLINE void md_tick_disable_csr_tickint(void) -{ - MD_TICK_CLEAR_BIT(TICK, CSR, TICK_CSR_TICKINT_MSK); -} - -/** - * @brief is TICK CSR Tick Interrupt Enabled - * @param None - * @retval The retval can be one of the following values: - * @arg Max Value 0x1 - * @arg Min Value 0x0 - */ -__STATIC_INLINE uint8_t md_tick_is_enabled_csr_tickint(void) -{ - return (MD_TICK_READBIT(TICK, CSR, TICK_CSR_TICKINT_MSK)>>TICK_CSR_TICKINT_POS); -} - -/** - * @brief Enable TICK CSR Enable - * @param None - * @retval None - */ -__STATIC_INLINE void md_tick_enable_csr_enable(void) -{ - MD_TICK_SET_BIT(TICK, CSR, TICK_CSR_ENABLE_MSK); -} - -/** - * @brief Disable TICK CSR Enable - * @param None - * @retval None - */ -__STATIC_INLINE void md_tick_disable_csr_enable(void) -{ - MD_TICK_CLEAR_BIT(TICK, CSR, TICK_CSR_ENABLE_MSK); -} - -/** - * @brief is TICK CSR Enable Enabled - * @param None - * @retval The retval can be one of the following values: - * @arg Max Value 0x1 - * @arg Min Value 0x0 - */ -__STATIC_INLINE uint8_t md_tick_is_enabled_csr_enable(void) -{ - return (MD_TICK_READBIT(TICK, CSR, TICK_CSR_ENABLE_MSK)>>TICK_CSR_ENABLE_POS); -} - -/** - * @brief Set TICK RVR - * @param @arg Max Value 0xffffff - * @arg Min Value 0x0 - * @retval None - */ -__STATIC_INLINE void md_tick_set_rvr(uint32_t U32) -{ - MD_TICK_WRITEREG(TICK, RVR, U32); -} - -/** - * @brief Get TICK RVR - * @param None - * @retval The retval can be one of the following values: - * @arg Max Value 0xffffff - * @arg Min Value 0x0 - */ -__STATIC_INLINE uint32_t md_tick_get_rvr(void) -{ - return (MD_TICK_READREG(TICK, RVR)); -} - -/** - * @brief Set TICK RVR Reload - * @param @arg Max Value 0xfffffff - * @arg Min Value 0x0 - * @retval None - */ -__STATIC_INLINE void md_tick_set_rvr_reload(uint32_t Reload) -{ - MD_TICK_MODIFYREG(TICK, RVR, TICK_RVR_RELOAD_MSK, (Reload<>TICK_RVR_RELOAD_POSS); -} - -/** - * @brief Set TICK CVR - * @param @arg Max Value 0xffffff - * @arg Min Value 0x0 - * @retval None - */ -__STATIC_INLINE void md_tick_set_cvr(uint32_t U32) -{ - MD_TICK_WRITEREG(TICK, CVR, U32); -} - -/** - * @brief Get TICK CVR - * @param None - * @retval The retval can be one of the following values: - * @arg Max Value 0xffffff - * @arg Min Value 0x0 - */ -__STATIC_INLINE uint32_t md_tick_get_cvr(void) -{ - return (MD_TICK_READREG(TICK, CVR)); -} - -/** - * @brief Set TICK CVR Current - * @param @arg Max Value 0xfffffff - * @arg Min Value 0x0 - * @retval None - */ -__STATIC_INLINE void md_tick_set_cvr_current(uint32_t Current) -{ - MD_TICK_MODIFYREG(TICK, CVR, TICK_CVR_CURRENT_MSK, (Current<>TICK_CVR_CURRENT_POSS); -} - -/** - * @brief Get TICK CALIB - * @param None - * @retval The retval can be one of the following values: - * @arg Max Value 0xffffffff - * @arg Min Value 0x0 - */ -__STATIC_INLINE uint32_t md_tick_get_calib(void) -{ - return (MD_TICK_READREG(TICK, CALIB)); -} - -/** - * @brief Get TICK CALIB NOREF - * @param None - * @retval The retval can be one of the following values: - * @arg Max Value 0x1 - * @arg Min Value 0x0 - */ -__STATIC_INLINE uint8_t md_tick_get_calib_noref(void) -{ - return (MD_TICK_READBIT(TICK, CALIB, TICK_CALIB_NOREF_MSK)>>TICK_CALIB_NOREF_POS); -} - -/** - * @brief Get TICK CALIB SKEW - * @param None - * @retval The retval can be one of the following values: - * @arg Max Value 0x1 - * @arg Min Value 0x0 - */ -__STATIC_INLINE uint8_t md_tick_get_calib_skew(void) -{ - return (MD_TICK_READBIT(TICK, CALIB, TICK_CALIB_SKEW_MSK)>>TICK_CALIB_SKEW_POS); -} - -/** - * @brief Get TICK CALIB 10ms Value - * @param None - * @retval The retval can be one of the following values: - * @arg Max Value 0xfffffff - * @arg Min Value 0x0 - */ -__STATIC_INLINE uint32_t md_tick_get_calib_tenms(void) -{ - return (MD_TICK_READBIT(TICK, CALIB, TICK_CALIB_TENMS_MSK)>>TICK_CALIB_TENMS_POSS); -} - - -/** - * @} MD_TICK_Macro_Drivers - */ - -/** - * @} MD_TICK_Public_Macros - */ - -/* Public functions -----------------------------------------------------------*/ -/** @defgroup MD_TICK_Public_Functions TICK Public Functions - * @{ - */ -void md_tick_init(void); -uint32_t md_tick_get_mscnt(void); -uint32_t md_tick_get_100uscnt(void); -uint32_t md_tick_get_10uscnt(void); -void md_tick_waitms(uint8_t Unit, uint16_t msCnt); -void md_tick_wait100us(uint16_t Unit, uint16_t usCnt); -void md_tick_wait10us(uint16_t Unit, uint16_t usCnt); -/** - * @} MD_TICK_Public_Functions - */ - -#endif - -/** - * @} TICK - */ - -/** - * @} Micro_Driver - */ - -#ifdef __cplusplus -} -#endif - -#endif - -/******************* (C) COPYRIGHT Eastsoft Microelectronics *****END OF FILE****/ diff --git a/bsp/essemi/es32f0271/libraries/ES32F027x_MD_StdPeriph_Driver/Include/md_uart.h b/bsp/essemi/es32f0271/libraries/ES32F027x_MD_StdPeriph_Driver/Include/md_uart.h deleted file mode 100644 index e638ab0a7a..0000000000 --- a/bsp/essemi/es32f0271/libraries/ES32F027x_MD_StdPeriph_Driver/Include/md_uart.h +++ /dev/null @@ -1,2874 +0,0 @@ -/** - ****************************************************************************** - * @file md_UART.h - * @brief ES32F0271 UART Header File. - * - * @version V1.00.01 - * @date 04/12/2018 - * @author Eastsoft AE Team - * @note - * detailed description - * - * Copyright (C) 2018 Shanghai Eastsoft Microelectronics Co., Ltd. ALL rights reserved. - ******************************************************************************* - */ - -/* Define to prevent recursive inclusion -------------------------------------*/ -#ifndef __MD_UART_H__ -#define __MD_UART_H__ - -#ifdef __cplusplus -extern "C" { -#endif - -/* Includes -------------------------------------------------------------------*/ -#include -#include "es32f0271.h" -#include "reg_uart.h" - -/** @addtogroup Micro_Driver - * @{ - */ - -#if defined (UART1) | defined (UART2) | defined (UART3) | defined (SUART1) | defined (SUART2) - -/** @defgroup UART UART - * @brief UART micro driver - * @{ - */ - -/* Private types --------------------------------------------------------------*/ -/* Private variables ----------------------------------------------------------*/ -/* Private constants ----------------------------------------------------------*/ -/* Private macros -------------------------------------------------------------*/ - -/* Public types ---------------------------------------------------------------*/ -/** @defgroup MD_UART_Public_Types UART Public Init Type - * @{ - */ - -typedef struct -{ - uint32_t BaudRate; /*!< This field defines expected Usart communication baud rate.*/ - - uint32_t BitOrder; /*!< Specifies the MSB of data bits will be transmitted or received first. - This parameter can be a value of @ref MD_UART_LCON_MSB_FIRST.*/ - - uint32_t Parity; /*!< Specifies the parity mode. - This parameter can be a value of @ref MD_UART_LCON_PS_EVEN.*/ - - uint32_t StopBits; /*!< Specifies the number of stop bits transmitted. - This parameter can be a value of @ref MD_UART_LCON_STOP_1.*/ - - uint32_t DataWidth; /*!< Specifies the number of data bits transmitted or received in a frame. - This parameter can be a value of @ref MD_UART_LCON_DLS_8.*/ - -} md_uart_init_typedef; - -/** - * @} MD_UART_Public_Types - */ - -/* Private variables ----------------------------------------------------------*/ -/* Private constants ----------------------------------------------------------*/ -/* Private macros -------------------------------------------------------------*/ -/* Public functions -----------------------------------------------------------*/ -/* Public constants -----------------------------------------------------------*/ -/** @defgroup MD_UART_Public_Constants UART Public Constants - * @{ - */ - -/** @defgroup UART_BAUDRATE UART Baudrate Definitation - * @{ - */ -#define MD_UART_BAUDRATE_1200 (1200U) /* baud rate=1200 bps */ -#define MD_UART_BAUDRATE_2400 (2400U) /* baud rate=2400 bps */ -#define MD_UART_BAUDRATE_4800 (4800U) /* baud rate=4800 bps */ -#define MD_UART_BAUDRATE_9600 (9600U) /* baud rate=9600 bps */ -#define MD_UART_BAUDRATE_19200 (19200U) /* baud rate=19200 bps */ -#define MD_UART_BAUDRATE_38400 (38400U) /* baud rate=38400 bps */ -#define MD_UART_BAUDRATE_57600 (57600U) /* baud rate=57600 bps */ -#define MD_UART_BAUDRATE_115200 (115200U) /* baud rate=115200 bps */ -#define MD_UART_BAUDRATE_230400 (230400U) /* baud rate=230400 bps */ -#define MD_UART_BAUDRATE_460800 (460800U) /* baud rate=460800 bps */ -#define MD_UART_BAUDRATE_512000 (512000U) /* baud rate=512000 bps */ -#define MD_UART_BAUDRATE_921600 (921600U) /* baud rate=921600 bps */ -/** - * @} UART_BAUDRATE UART Baudrate Definitation - */ - -/** @defgroup UART_LCON UART_LCON Register - * @{ - */ -#define MD_UART_LCON_MSB_FIRST (1U) /** @brief data Most significant bit first */ -#define MD_UART_LCON_LSB_FIRST (0U) /** @brief data Least significant bit first */ -#define MD_UART_LCON_PS_EVEN (1U) /** @brief data Even parity bit selection */ -#define MD_UART_LCON_PS_ODD (0U) /** @brief data Odd parity bit selection */ -#define MD_UART_LCON_STOP_2 (1U) /** @brief data 2(1.5) Stop bit */ -#define MD_UART_LCON_STOP_1 (0U) /** @brief data 2(1.5) Stop bit */ -#define MD_UART_LCON_DLS_8 (0U) /** @brief data Date length 8 */ -#define MD_UART_LCON_DLS_7 (1U) /** @brief data Date length 7 */ -#define MD_UART_LCON_DLS_6 (2U) /** @brief data Date length 6 */ -#define MD_UART_LCON_DLS_5 (3U) /** @brief data Date length 5 */ -/** - * @} UART_LCON UART_LCON Register - */ - -/** @defgroup UART_MCON UART_MCON Register - * @{ - */ -#define MD_UART_MCON_ABRMOD_0 (0U) /** @brief data Receiver DMA disable */ -#define MD_UART_MCON_ABRMOD_1 (1U) /** @brief data Repeat auto-baud rate detection after timeout enable */ -#define MD_UART_MCON_ABRMOD_2 (2U) /** @brief data Repeat auto-baud rate detection after timeout disable */ -#define MD_UART_MCON_RTSSET_LOW (1U) /** @brief data RTSn set control bit RTSn level is 0 */ -#define MD_UART_MCON_RTSSET_HIGH (0U) /** @brief data RTSn set control bit RTSn level is 1 */ -/** - * @} UART_MCON UART_MCON Register - */ - -/** @defgroup UART_MCON UART_MCON Register - * @{ - */ -#define MD_UART_RS485_AADINV_LOW (0U) /** @brief data Low : Transfering data, High: Idle */ -#define MD_UART_RS485_AADINV_HIGH (1U) /** @brief data High: Transfering data, Low : Idle */ -/** - * @} UART_MCON UART_MCON Register - */ - -/** @defgroup UART_FCON UART_FCON Register - * @{ - */ -#define MD_UART_FCON_TXTH_0 (0U) /** @brief data Transmit FIFO trigger threshold: FIFO empty */ -#define MD_UART_FCON_TXTH_2 (1U) /** @brief data Transmit FIFO trigger threshold: 2 characters in the FIFO */ -#define MD_UART_FCON_TXTH_4 (2U) /** @brief data Transmit FIFO trigger threshold: 4 characters in the FIFO */ -#define MD_UART_FCON_TXTH_8 (3U) /** @brief data Transmit FIFO trigger threshold: 8 characters in the FIFO */ -#define MD_UART_FCON_TFRST (1U) /** @brief data Transmitter FIFO reset */ -#define MD_UART_FCON_RXTH_1 (0U) /** @brief data Receive FIFO trigger threshold: 1 character in the FIFO */ -#define MD_UART_FCON_RXTH_4 (1U) /** @brief data Receive FIFO trigger threshold: 4 characters in the FIFO */ -#define MD_UART_FCON_RXTH_8 (2U) /** @brief data Receive FIFO trigger threshold: 8 characters in the FIFO */ -#define MD_UART_FCON_RXTH_14 (3U) /** @brief data Receive FIFO trigger threshold: 14 characters in the FIFO */ -#define MD_UART_FCON_RFRST (1U) /** @brief data Receive FIFO reset */ -/** - * @} UART_FCON UART_FCON Register - */ - -/** - * @} MD_UART_Public_Constants UART Public Constants - */ - -/* Public macro ---------------------------------------------------------------*/ -/** @defgroup MD_UART_Public_Macros UART Public Macros - * @{ - */ - -/** - * @brief Read Receiver Buffer Register - * @note Contains the received data character. - * The RXBR register provides the parallel interface between the - * input shift register and the internal bus. - * When receiving with the parity enabled, the value read in the - * MSB bit is the received parity bit. - * @param UARTx UART Instance - * @retval RxData Value between Min_Data=0x00 and Max_Data=0x1FF - */ -__STATIC_INLINE uint16_t md_uart_get_rxbuf(UART_TypeDef *UARTx) -{ - return (uint16_t) ((READ_REG(UARTx->RXBUF))>>UART_RXBUF_RXBUF_POSS); -} - -/** - * @brief Write Transmit buffer register - * @note Contains the data character to be transmitted. - * The TXBR register provides the parallel interface between the - * internal bus and the output shift register. - * When transmitting with the parity enabled the value written in - * the MSB (bit 7 or bit 8 depending on the data length) has no - * effect because it is replaced by the parity. - * @param UARTx UART Instance - * @param TxData Value between Min_Data=0x00 and Max_Data=0xFF - * @retval None - */ -__STATIC_INLINE void md_uart_send_txbuf(UART_TypeDef *UARTx, uint8_t TxData) -{ - WRITE_REG (UARTx->TXBUF, (uint8_t)TxData); -} - -/** - * @brief Set UARTx Baud rate register. - * @note This bits can only be written when the UART is disabled. - * (RXEN and TXEN=0 in the LCR register). - * @param UARTx UART Instance. - * @param UART buad rate value. - * @retval None - */ -__STATIC_INLINE void md_uart_set_brr(UART_TypeDef *UARTx, uint32_t baudrate) -{ - WRITE_REG(UARTx->BRR, baudrate); -} - -/** - * @brief Get UARTx baud rate. - * @note This bit can only be written when UART is disabled(TXEN and RXEN=0). - * @param UARTx UART Instance. - * @retval UARTx Baudrate. - */ -__STATIC_INLINE uint32_t md_uart_get_brr(UART_TypeDef *UARTx) -{ - return (uint32_t) (READ_REG(UARTx->BRR)>>UART_BRR_BRR_POSS); -} - -/** - * @brief UARTx Transmitter enable. - * @note This bit enables the transmitter. It is set and cleared by - * software. - * @param UARTx UART Instance - * @retval None. - */ -__STATIC_INLINE void md_uart_enable_lcon_txen(UART_TypeDef *UARTx) -{ - SET_BIT(UARTx->LCON, UART_LCON_TXEN_MSK); -} - -/** - * @brief UARTx Transmitter disable. - * @param UARTx UART Instance. - * @retval None. - */ -__STATIC_INLINE void md_uart_disable_lcon_txen(UART_TypeDef *UARTx) -{ - CLEAR_BIT(UARTx->LCON, UART_LCON_TXEN_MSK); -} - -/** - * @brief Check if UART Transmitter is enabled. - * @param UARTx UART Instance. - * @retval State of bit (1 or 0). - */ -__STATIC_INLINE uint32_t md_uart_is_enabled_lcon_tx(UART_TypeDef *UARTx) -{ - return (uint32_t)(READ_BIT(UARTx->LCON, UART_LCON_TXEN_MSK) == (UART_LCON_TXEN_MSK)); -} - -/** - * @brief UARTx Receiver enable - * @note This bit enables the receiver. It is set and cleared by software. - * @param UARTx UART Instance - * @retval None - */ -__STATIC_INLINE void md_uart_enable_lcon_rxen(UART_TypeDef *UARTx) -{ - SET_BIT(UARTx->LCON, UART_LCON_RXEN_MSK); -} - -/** - * @brief UARTx Receiver Disable - * @param UARTx UART Instance - * @retval None - */ -__STATIC_INLINE void md_uart_disable_lcon_rxen(UART_TypeDef *UARTx) -{ - CLEAR_BIT(UARTx->LCON, UART_LCON_RXEN_MSK); -} - -/** - * @brief Check if UARTx Receiver is enabled. - * @param UARTx UART Instance. - * @retval State of bit (1 or 0). - */ -__STATIC_INLINE uint32_t md_uart_is_enabled_lcon_rxen(UART_TypeDef *UARTx) -{ - return (uint32_t)(READ_BIT(UARTx->LCON, UART_LCON_RXEN_MSK) == (UART_LCON_RXEN_MSK)); -} - -/** - * @brief UARTx Debounce Enable. - * @note This bit enables the debounce. It is set and cleared by software. - * @param UARTx UART Instance. - * @retval None. - */ -__STATIC_INLINE void md_uart_enable_lcon_decen(UART_TypeDef *UARTx) -{ - SET_BIT(UARTx->LCON, UART_LCON_DBCEN_MSK); -} - -/** - * @brief UART Debounce Disable. - * @param UARTx UART Instance. - * @retval None. - */ -__STATIC_INLINE void md_uart_disable_lcon_dbcen(UART_TypeDef *UARTx) -{ - CLEAR_BIT(UARTx->LCON, UART_LCON_DBCEN_MSK); -} - -/** - * @brief Check if UART Debounce is enabled. - * @param UARTx UART Instance. - * @retval State of bit (1 or 0). - */ -__STATIC_INLINE uint32_t md_uart_is_enabled_lcon_dbcen(UART_TypeDef *UARTx) -{ - return (uint32_t)(READ_BIT(UARTx->LCON, UART_LCON_DBCEN_MSK) == (UART_LCON_DBCEN_MSK)); -} - -/** - * @brief Enable UARTx Break control bit. - * @note This is used to cause a break condition to be transmitted to the - * receiving device. The serial data output (Tx) is forced to the - * Spacing State (logic 0). - * This bit can only be written when the UART is disabled. - * (RXENand TXEN=0). - * @param UARTx UART Instance - * @retval None - */ -__STATIC_INLINE void md_uart_enable_lcon_break(UART_TypeDef *UARTx) -{ - SET_BIT(UARTx->LCON, UART_LCON_BREAK_MSK); -} - -/** - * @brief Disable UARTx Break control bit. - * @param UARTx UART Instance. - * @retval None. - */ -__STATIC_INLINE void md_uart_disable_lcon_break(UART_TypeDef *UARTx) -{ - CLEAR_BIT(UARTx->LCON, UART_LCON_BREAK_MSK); -} - -/** - * @brief Check if UARTx Break control bit is enabled. - * @param UARTx UART Instance - * @retval State of bit (1 or 0). - */ -__STATIC_INLINE uint32_t md_uart_is_enabled_lcon_break(UART_TypeDef *UARTx) -{ - return (uint32_t)(READ_BIT(UARTx->LCON, UART_LCON_BREAK_MSK) == (UART_LCON_BREAK_MSK)); -} - -/** - * @brief UARTx Swap TX/RX pins. - * @note This allows to work in the case of a cross-wired connection to another UART. - * This bit can only be written when the UART is disabled (RXEN and TXEN=0). - * @param UARTx UART Instance. - * @retval None. - */ -__STATIC_INLINE void md_uart_enable_lcon_swap(UART_TypeDef *UARTx) -{ - SET_BIT(UARTx->LCON, UART_LCON_SWAP_MSK); -} - -/** - * @brief UARTx Swap TX/RX pins disabl. - * @param UARTx UART Instance. - * @retval State of bit (1 or 0). - */ -__STATIC_INLINE void md_uart_disable_lcon_swap(UART_TypeDef *UARTx) -{ - CLEAR_BIT(UARTx->LCON, UART_LCON_SWAP_MSK); -} - -/** - * @brief Check if UART Swap TX/RX pins is enabled. - * @param UARTx UART Instance. - * @retval State of bit (1 or 0). - */ -__STATIC_INLINE uint32_t md_uart_is_enabled_lcon_swap(UART_TypeDef *UARTx) -{ - return (uint32_t)(READ_BIT(UARTx->LCON, UART_LCON_SWAP_MSK) == (UART_LCON_SWAP_MSK)); -} - -/** - * @brief UARTx TX pin active level inversion. - * @note This allows the use of an external inverter on the TX line. - * This bit can only be written when the UART is disabled (RXEN and TXEN=0). - * @param UARTx UART Instance. - * @retval None. - */ -__STATIC_INLINE void md_uart_enable_lcon_txinv(UART_TypeDef *UARTx) -{ - SET_BIT(UARTx->LCON, UART_LCON_TXINV_MSK); -} - -/** - * @brief UARTx TX pin active level inversion disable. - * @note This bit can only be written when UART is disabled(TXEN and RXEN=0). - * @param UARTx UART Instance. - * @retval None. - */ -__STATIC_INLINE void md_uart_disable_lcon_txinv(UART_TypeDef *UARTx) -{ - CLEAR_BIT(UARTx->LCON, UART_LCON_TXINV_MSK); -} - -/** - * @brief Check if UARTx TX pin active level is inverted. - * @param UARTx UART Instance. - * @retval State of bit (1 or 0). - */ -__STATIC_INLINE uint32_t md_uart_is_enabled_lcon_txinv(UART_TypeDef *UARTx) -{ - return (uint32_t)(READ_BIT(UARTx->LCON, UART_LCON_TXINV_MSK) == (UART_LCON_TXINV_MSK)); -} - -/** - * @brief UARTx RX pin active level inversion. - * @note This allows the use of an external inverter on the RX line. - * @param UARTx UART Instance. - * @retval None. - */ -__STATIC_INLINE void md_uart_enable_lcon_rxinv(UART_TypeDef *UARTx) -{ - SET_BIT(UARTx->LCON, UART_LCON_RXINV_MSK); -} - -/** - * @brief UARTx RX pin active level inversion disable. - * @param UARTx UART Instance. - * @retval None. - */ -__STATIC_INLINE void md_uart_disable_lcon_rxinv(UART_TypeDef *UARTx) -{ - CLEAR_BIT(UARTx->LCON, UART_LCON_RXINV_MSK); -} - -/** - * @brief Check if UART RX pin active level is inverted. - * @param UARTx UART Instance. - * @retval State of bit (1 or 0). - */ -__STATIC_INLINE uint32_t md_uart_is_enabled_lcon_rxinv(UART_TypeDef *UARTx) -{ - return (uint32_t)(READ_BIT(UARTx->LCON, UART_LCON_RXINV_MSK) == (UART_LCON_RXINV_MSK)); -} - -/** - * @brief UARTx Binary data inversion. - * @note This bit can only be written when UART is disabled(TXEN and RXEN=0). - * The parity bit is also inverted. - * @param UARTx UART Instance. - * @retval None. - */ -__STATIC_INLINE void md_uart_enable_lcon_datainv(UART_TypeDef *UARTx) -{ - SET_BIT(UARTx->LCON, UART_LCON_RXINV_MSK); -} - -/** - * @brief UARTx Binary data inverted disable. - * @note This bit can only be written when UART is disabled(TXEN and RXEN=0). - * @param UARTx UART Instance. - * @retval None. - */ -__STATIC_INLINE void md_uart_disable_lcon_datainv(UART_TypeDef *UARTx) -{ - CLEAR_BIT(UARTx->LCON, UART_LCON_RXINV_MSK); -} - -/** - * @brief Check if UARTx Binary data is inverted. - * @param UARTx UART Instance. - * @retval State of bit (1 or 0). - */ -__STATIC_INLINE uint32_t md_uart_is_enabled_lcon_datainv(UART_TypeDef *UARTx) -{ - return (uint32_t)(READ_BIT(UARTx->LCON, UART_LCON_DATAINV_MSK) == (UART_LCON_DATAINV_MSK)); -} - -/** - * @brief Set UARTx Most significant bit first. - * @note This bit can only be written when UART is disabled(TXEN and RXEN=0). - * @param UARTx UART Instance. - * @param msb This parameter can be one of the following values: - * @arg @ref MD_UART_LCON_LSB_FIRST - * @arg @ref MD_UART_LCON_MSB_FIRST - * @retval None - */ -__STATIC_INLINE void md_uart_set_lcon_msb(UART_TypeDef *UARTx, uint32_t msb) -{ - MODIFY_REG(UARTx->LCON, UART_LCON_MSB_MSK, msb<LCON, UART_LCON_MSB_MSK))>>UART_LCON_MSB_POS); -} - -/** - * @brief UARTx Parity bit selection. - * @note This bit can only be written when UART is disabled(TXEN and RXEN=0). - * @param UARTx UART Instance. - * @param parity This parameter can be one of the following values: - * @arg @ref MD_UART_LCON_PS_ODD - * @arg @ref MD_UART_LCON_PS_EVEN - * @retval None - */ -__STATIC_INLINE void md_uart_set_lcon_ps(UART_TypeDef *UARTx, uint32_t parity) -{ - MODIFY_REG(UARTx->LCON, UART_LCON_PS_MSK, parity<LCON, UART_LCON_PS_MSK))>>UART_LCON_PS_POS); -} - -/** - * @brief UARTx Parity enable. - * @note This bit can only be written when UART is disabled(TXEN and RXEN=0). - * @param UARTx UART Instance. - * @retval None. - */ -__STATIC_INLINE void md_uart_enable_lcon_pe(UART_TypeDef *UARTx) -{ - SET_BIT(UARTx->LCON, UART_LCON_PE_MSK); -} - -/** - * @brief UARTx Parity disable. - * @note This bit can only be written when UART is disabled(TXEN and RXEN=0). - * @param UARTx UART Instance. - * @retval None. - */ -__STATIC_INLINE void md_uart_disable_lcon_pe(UART_TypeDef *UARTx) -{ - CLEAR_BIT(UARTx->LCON, UART_LCON_PE_MSK); -} - -/** - * @brief Check if UARTx Parity is enabled. - * @param UARTx UART Instance. - * @retval State of bit (1 or 0). - */ -__STATIC_INLINE uint32_t md_uart_is_enabled_lcon_pe(UART_TypeDef *UARTx) -{ - return (uint32_t)(READ_BIT(UARTx->LCON, UART_LCON_PE_MSK) == (UART_LCON_PE_MSK)); -} - -/** - * @brief Set UARTx Stop bit. - * @note This bit can only be written when UART is disabled(TXEN and RXEN=0) - * @param UARTx UART Instance. - * @param stop This parameter can be one of the following values: - * @arg @ref MD_UART_LCON_STOP_1 - * @arg @ref MD_UART_LCON_STOP_2 - * @retval None - */ -__STATIC_INLINE void md_uart_set_lcon_stop(UART_TypeDef *UARTx, uint32_t stop) -{ - MODIFY_REG(UARTx->LCON, UART_LCON_STOP_MSK, stop<LCON, UART_LCON_STOP_MSK))>>UART_LCON_STOP_POS); -} - -/** - * @brief UARTx Date length selection. - * @note This bit can only be written when UART is disabled(TXEN and RXEN=0). - * @param UARTx UART Instance. - * @param width This parameter can be one of the following values: - * @arg @ref MD_UART_LCON_DLS_8 - * @arg @ref MD_UART_LCON_DLS_7 - * @arg @ref MD_UART_LCON_DLS_6 - * @arg @ref MD_UART_LCON_DLS_5 - * @retval None - */ -__STATIC_INLINE void md_uart_set_lcon_dls(UART_TypeDef *UARTx, uint32_t width) -{ - MODIFY_REG(UARTx->LCON, UART_LCON_DLS_MSK, width<LCON, UART_LCON_DLS_MSK))>>UART_LCON_DLS_POSS); -} - -/** - * @brief UARTx Transmitter DMA enable. - * @note This bit is set and cleared by software. This bit enables the DMA transmitter. - * @param UARTx UART Instance. - * @retval None. - */ -__STATIC_INLINE void md_uart_enable_mcon_txdmaen(UART_TypeDef *UARTx) -{ - SET_BIT(UARTx->MCON, UART_MCON_TXDMAEN_MSK); -} - -/** - * @brief UARTx Transmitter DMA enable disable. - * @param UARTx UART Instance. - * @retval None. - */ -__STATIC_INLINE void md_uart_disable_mcon_txdmaen(UART_TypeDef *UARTx) -{ - CLEAR_BIT(UARTx->MCON, UART_MCON_TXDMAEN_MSK); -} - -/** - * @brief Check if UARTx Transmitter DMA is enabled. - * @param UARTx UART Instance. - * @retval State of bit (1 or 0). - */ -__STATIC_INLINE uint32_t md_uart_is_enabled_mcon_txdmaen(UART_TypeDef *UARTx) -{ - return (READ_BIT(UARTx->MCON, UART_MCON_TXDMAEN_MSK) == (UART_MCON_TXDMAEN_MSK)); -} - -/** - * @brief UARTx Receiver DMA enable. - * @note This bit is set and cleared by software. This bit enables the DMA Receiver. - * @param UARTx UART Instance. - * @retval None. - */ -__STATIC_INLINE void md_uart_enable_mcon_rxdmaen(UART_TypeDef *UARTx) -{ - SET_BIT(UARTx->MCON, UART_MCON_RXDMAEN_MSK); -} - -/** - * @brief UARTx Receiver DMA disable. - * @param UARTx UART Instance. - * @retval None. - */ -__STATIC_INLINE void md_uart_disable_mcon_rxdmaen(UART_TypeDef *UARTx) -{ - CLEAR_BIT(UARTx->MCON, UART_MCON_RXDMAEN_MSK); -} - -/** - * @brief Check if UARTx UARTx Receiver DMA is enabled. - * @param UARTx UART Instance. - * @retval State of bit (1 or 0). - */ -__STATIC_INLINE uint32_t md_uart_is_enabled_mcon_rxdmaen(UART_TypeDef *UARTx) -{ - return (READ_BIT(UARTx->MCON, UART_MCON_RXDMAEN_MSK) == (UART_MCON_RXDMAEN_MSK)); -} - -/** - * @brief UARTx Auto baud rate detection repeat enable. - * @note This bit is set to enable baud rate detection repeat one more time - * after the first failure of auto-baud rate detection. - * @param UARTx UART Instance. - * @retval None. - */ -__STATIC_INLINE void md_uart_enable_mcon_abrrept(UART_TypeDef *UARTx) -{ - SET_BIT(UARTx->LCON, UART_MCON_ABRREPT_MSK); -} - -/** - * @brief UARTx Auto baud rate detection repeat disable. - * @param UARTx UART Instance. - * @retval None. - */ -__STATIC_INLINE void md_uart_disable_mcon_abrrept(UART_TypeDef *UARTx) -{ - CLEAR_BIT(UARTx->LCON, UART_MCON_ABRREPT_MSK); -} - -/** - * @brief Check if UARTx Auto baud rate detection repeat is enabled. - * @param UARTx UART Instance. - * @retval State of bit (1 or 0). - */ -__STATIC_INLINE uint32_t md_uart_is_enabled_mcon_abrrept(UART_TypeDef *UARTx) -{ - return (uint32_t)(READ_BIT(UARTx->MCON, UART_MCON_ABRREPT_MSK) == (UART_MCON_ABRREPT_MSK)); -} - -/** - * @brief Set UARTx Auto baud rate mode. - * @note MD_UART_MCON_ABRMOD_0: Mode 0 detect falling edge to second falling edge (detect 2 Bps). - * MD_UART_MCON_ABRMOD_1: Mode 1 detect falling edge to first rising edge (detect 1 Bps). - * MD_UART_MCON_ABRMOD_2: Mode 2 detect falling edge to first rising edge (detect 2 Bps). - * @param UARTx UART Instance. - * @param mode This parameter can be one of the following values: - * @arg @ref MD_UART_MCON_ABRMOD_0 - * @arg @ref MD_UART_MCON_ABRMOD_1 - * @arg @ref MD_UART_MCON_ABRMOD_2 - * @retval None - */ -__STATIC_INLINE void md_uart_set_mcon_abrmod(UART_TypeDef *UARTx, uint32_t mode) -{ - MODIFY_REG(UARTx->MCON, UART_MCON_ABRMOD_MSK, mode<MCON, UART_MCON_ABRMOD_MSK))>>UART_MCON_ABRMOD_POSS); -} - -/** - * @brief UARTx Auto baud rate enable. - * @note This bit is set by software and cleared by hardware after the - * auto-baud rate finish. - * @param UARTx UART Instance. - * @retval None. - */ -__STATIC_INLINE void md_uart_enable_mcon_abren(UART_TypeDef *UARTx) -{ - SET_BIT(UARTx->LCON, UART_MCON_ABREN_MSK); -} - -/** - * @brief UARTx Auto baud rate disable. - * @param UARTx UART Instance. - * @retval None. - */ -__STATIC_INLINE void md_uart_disable_mcon_abren(UART_TypeDef *UARTx) -{ - CLEAR_BIT(UARTx->LCON, UART_MCON_ABREN_MSK); -} - -/** - * @brief Check if UARTx Auto baud rate is enabled. - * @param UARTx UART Instance. - * @retval State of bit (1 or 0). - */ -__STATIC_INLINE uint32_t md_uart_is_enabled_mcon_abren(UART_TypeDef *UARTx) -{ - return (uint32_t)(READ_BIT(UARTx->MCON, UART_MCON_ABREN_MSK) == (UART_MCON_ABREN_MSK)); -} - -/** - * @brief UARTx break request enable. - * @note This bit is set by software and automatically cleared by - * hardware in the next clock cycle. - * @param UARTx UART Instance. - * @retval None. - */ -__STATIC_INLINE void md_uart_enable_mcon_bkreq(UART_TypeDef *UARTx) -{ - SET_BIT(UARTx->MCON, UART_MCON_BKREQ_MSK); -} - -/** - * @brief UARTx break request disable. - * @param UARTx UART Instance. - * @retval None. - */ -__STATIC_INLINE void md_uart_disable_mcon_bkreq(UART_TypeDef *UARTx) -{ - CLEAR_BIT(UARTx->MCON, UART_MCON_BKREQ_MSK); -} - -/** - * @brief Check if UARTx break request is enabled - * @param UARTx UART Instance. - * @retval State of bit (1 or 0). - */ -__STATIC_INLINE uint32_t md_uart_is_enabled_mcon_bkreq(UART_TypeDef *UARTx) -{ - return (uint32_t)(READ_BIT(UARTx->MCON, UART_MCON_BKREQ_MSK) == (UART_MCON_BKREQ_MSK)); -} - -/** - * @brief UARTx Half-duplex enable(Only UART). - * @param UARTx UART Instance. - * @retval None. - */ -__STATIC_INLINE void md_uart_enable_mcon_hden(UART_TypeDef *UARTx) -{ - SET_BIT(UARTx->MCON, UART_MCON_HDEN_MSK); -} - -/** - * @brief UARTx Half-duplex disable(Only UART). - * @param UARTx UART Instance. - * @retval None. - */ -__STATIC_INLINE void md_uart_disable_mcon_hden(UART_TypeDef *UARTx) -{ - CLEAR_BIT(UARTx->MCON, UART_MCON_HDEN_MSK); -} - -/** - * @brief Check if UARTx Half-duplex is enabled. - * @param UARTx UART Instance - * @retval State of bit (1 or 0). - */ -__STATIC_INLINE uint32_t md_uart_is_enabled_mcon_hden(UART_TypeDef *UARTx) -{ - return (uint32_t)(READ_BIT(UARTx->MCON, UART_MCON_HDEN_MSK) == (UART_MCON_HDEN_MSK)); -} - -/** - * @brief UARTx IrDA mode enable(Only UART). - * @param UARTx UART Instance. - * @retval None. - */ -__STATIC_INLINE void md_uart_enable_mcon_iren(UART_TypeDef *UARTx) -{ - SET_BIT(UARTx->MCON, UART_MCON_IREN_MSK); -} - -/** - * @brief UARTx IrDA mode disable. - * @param UARTx UART Instance. - * @retval None. - */ -__STATIC_INLINE void md_uart_disable_mcon_iren(UART_TypeDef *UARTx) -{ - CLEAR_BIT(UARTx->MCON, UART_MCON_IREN_MSK); -} - -/** - * @brief Check if UARTx IrDA mode is enabled. - * @param UARTx UART Instance. - * @retval State of bit (1 or 0). - */ -__STATIC_INLINE uint32_t md_uart_is_enabled_mcon_iren(UART_TypeDef *UARTx) -{ - return (uint32_t)(READ_BIT(UARTx->MCON, UART_MCON_IREN_MSK) == (UART_MCON_IREN_MSK)); -} - -/** - * @brief UARTx Auto flow control enable. - * @param UARTx UART Instance - * @retval None - */ -__STATIC_INLINE void md_uart_enable_mcon_afcen(UART_TypeDef *UARTx) -{ - SET_BIT(UARTx->MCON, UART_MCON_AFCEN_MSK); -} - -/** - * @brief UARTx Auto flow control disable. - * @param UARTx UART Instance - * @retval None - */ -__STATIC_INLINE void md_uart_disable_mcon_afcen(UART_TypeDef *UARTx) -{ - CLEAR_BIT(UARTx->MCON, UART_MCON_AFCEN_MSK); -} - -/** - * @brief Check if Auto flow control is enabled. - * @param UARTx UART Instance. - * @retval State of bit (1 or 0). - */ -__STATIC_INLINE uint32_t md_uart_is_enabled_mcon_afcen(UART_TypeDef *UARTx) -{ - return (uint32_t)(READ_BIT(UARTx->MCON, UART_MCON_AFCEN_MSK) == (UART_MCON_AFCEN_MSK)); -} - -/** - * @brief Set UARTx RTSn set control bit. - * @note If Auto flow control disable, user can control RTSn output level by this bit. - * MD_UART_MCON_RTSSET_LOW : RTSn level is 0 - * MD_UART_MCON_RTSSET_HIGH: RTSn level is 1 - * @param UARTx UART Instance. - * @param This parameter can be one of the following values: - * @arg @ref MD_UART_MCON_RTSSET_LOW - * @arg @ref MD_UART_MCON_RTSSET_HIGH - * @retval None - */ -__STATIC_INLINE void md_uart_set_mcon_rtsset(UART_TypeDef *UARTx, uint32_t level) -{ - MODIFY_REG(UARTx->MCON, UART_MCON_RTSSET_MSK, level<MCON, UART_MCON_RTSSET_MSK))>>UART_MCON_RTSSET_POS); -} - -/** - * @brief UARTx LoopBack enable. - * @note This is used to put the UART into a diagnostic mode for test purpose. - * If operating in UART mode, data on the TXD line is held high, - * while serial data output is looped back to the RXD line, internally. - * In this mode, all the interrupts are fully functional. - * If operating in infrared mode, data on the TXD with IrDA line is held low, - * while serial data output is inverted and looped back to the RXD line. - * @param UARTx UART Instance. - * @retval None. - */ -__STATIC_INLINE void md_uart_enable_mcon_lpbken(UART_TypeDef *UARTx) -{ - SET_BIT(UARTx->MCON, UART_MCON_LPBKEN_MSK); -} - -/** - * @brief UARTx LoopBack disable. - * @param UARTx UART Instance. - * @retval None. - */ -__STATIC_INLINE void md_uart_disable_mcon_lpbken(UART_TypeDef *UARTx) -{ - CLEAR_BIT(UARTx->MCON, UART_MCON_LPBKEN_MSK); -} - -/** - * @brief Check if UARTx LoopBack is enabled. - * @param UARTx UART Instance. - * @retval State of bit (1 or 0). - */ -__STATIC_INLINE uint32_t md_uart_is_enabled_lpbken(UART_TypeDef *UARTx) -{ - return (uint32_t)(READ_BIT(UARTx->MCON, UART_MCON_LPBKEN_MSK) == (UART_MCON_LPBKEN_MSK)); -} - -/** - * @brief Set UARTx Delay value. - * @note Contains a direction control RTSn Delay value. This register - * works in conjunction with an 8-bit counter in terms of number of - * DIVISOR bit duration. - * @param UARTx UART Instance. - * @param UARTx Delay value. - * @retval None. - */ -__STATIC_INLINE void md_uart_set_rs485_dly(UART_TypeDef *UARTx, uint32_t delay) -{ - MODIFY_REG(UARTx->RS485, UART_RS485_DLY_MSK, delay<RS485, UART_RS485_DLY_MSK))>>UART_RS485_DLY_POSS); -} - -/** - * @brief Set UARTx Address match value. - * @param UARTx UART Instance. - * @param UARTx Address match value. - * @retval None - */ -__STATIC_INLINE void md_uart_set_rs485_addr(UART_TypeDef *UARTx, uint32_t address) -{ - MODIFY_REG(UARTx->RS485, UART_RS485_ADDR_MSK, address<RS485, UART_RS485_ADDR_MSK))>>UART_RS485_ADDR_POSS); -} - -/** - * @brief Set UARTx Automatic address detection invert. - * @note This bit retains the DE(RTSn) polarity direction control signal on pin. - * @param UARTx UART Instance. - * @param aadinv can be one of the following value: - * @arg @ref MD_UART_RS485_AADINV_LOW (Low : Transfering data, High: Idle) - * @arg @ref MD_UART_RS485_AADINV_HIGH (High: Transfering data, Low : Idle) - * @retval None - */ -__STATIC_INLINE void md_uart_set_rs485_aadinv(UART_TypeDef *UARTx, uint32_t aadinv) -{ - MODIFY_REG(UARTx->RS485, UART_RS485_AADINV_MSK, aadinv<RS485, UART_RS485_AADINV_MSK))>>UART_RS485_AADINV_POS); -} - -/** - * @brief UARTx Automatic address detection auto-control enable. - * @param UARTx UART Instance. - * @retval None. - */ -__STATIC_INLINE void md_uart_enable_rs485_aadacen(UART_TypeDef *UARTx) -{ - SET_BIT(UARTx->RS485, UART_RS485_AADACEN_MSK); -} - -/** - * @brief UARTx Automatic address detection auto-control disable - * @param UARTx UART Instance. - * @retval None. - */ -__STATIC_INLINE void md_uart_disable_rs485_aadacen(UART_TypeDef *UARTx) -{ - CLEAR_BIT(UARTx->RS485, UART_RS485_AADACEN_MSK); -} - -/** - * @brief Check if UARTx Automatic address detection auto-control is enabled. - * @param UARTx UART Instance. - * @retval State of bit (1 or 0). - */ -__STATIC_INLINE uint32_t md_uart_is_enabled_rs485_aadacen(UART_TypeDef *UARTx) -{ - return (uint32_t)(READ_BIT(UARTx->RS485, UART_RS485_AADACEN_MSK) == (UART_RS485_AADACEN_MSK)); -} - -/** - * @brief UARTx Automatic address detection normal mode enable. - * @note Note that it can be active with RS-485 AAD operation mode. - * @param UARTx UART Instance. - * @retval None. - */ -__STATIC_INLINE void md_uart_enable_rs485_aadnen(UART_TypeDef *UARTx) -{ - SET_BIT(UARTx->RS485, UART_RS485_AADNEN_MSK); -} - -/** - * @brief UARTx Automatic address detection normal mode disable. - * @param UARTx UART Instance. - * @retval None. - */ -__STATIC_INLINE void md_uart_disable_rs485_aadnen(UART_TypeDef *UARTx) -{ - CLEAR_BIT(UARTx->RS485, UART_RS485_AADNEN_MSK); -} - -/** - * @brief Check if Automatic address detection normal mode is enabled. - * @param UARTx UART Instance. - * @retval State of bit (1 or 0). - */ -__STATIC_INLINE uint32_t md_uart_is_enabled_rs485_aadnen(UART_TypeDef *UARTx) -{ - return (uint32_t)(READ_BIT(UARTx->RS485, UART_RS485_AADNEN_MSK) == (UART_RS485_AADNEN_MSK)); -} - -/** - * @brief UARTx Automatic address detection operation mode enable. - * @param UARTx UART Instance. - * @retval None. - */ -__STATIC_INLINE void md_uart_enable_rs485_aaden(UART_TypeDef *UARTx) -{ - SET_BIT(UARTx->RS485, UART_RS485_AADEN_MSK); -} - -/** - * @brief UARTx Automatic address detection operation mode disable. - * @param UARTx UART Instance. - * @retval None. - */ -__STATIC_INLINE void md_uart_disable_rs485_aaden(UART_TypeDef *UARTx) -{ - CLEAR_BIT(UARTx->RS485, UART_RS485_AADEN_MSK); -} - -/** - * @brief Check if UARTx Automatic address detection operation mode is enabled. - * @param UARTx UART Instance. - * @retval State of bit (1 or 0). - */ -__STATIC_INLINE uint32_t md_uart_is_enabled_rs485_aaden(UART_TypeDef *UARTx) -{ - return (uint32_t)(READ_BIT(UARTx->RS485, UART_RS485_AADEN_MSK) == (UART_RS485_AADEN_MSK)); -} - -/** - * @brief Set UARTx Block Length (Only UART). - * @note This bit-field gives the Block length in Smartcard T=1 - * Reception. Its value equals the number of information - * characters + the length of the Epilogue Field (1-LEC/2-CRC) - 1. - * This bit-field can be used also in other modes. In this case, the - * Block length counter is reset when RXEN=0 (receiver disabled). - * @param UARTx UART Instance. - * @param Block Length. - * @retval None. - */ -__STATIC_INLINE void md_uart_set_scard_blen(UART_TypeDef *UARTx, uint32_t blocklength) -{ - MODIFY_REG(UARTx->SCARD, UART_SCARD_BLEN_MSK, blocklength<SCARD, UART_SCARD_BLEN_MSK))>>UART_SCARD_BLEN_POSS); -} - -/** - * @brief Set UARTx Guard time value(Only UART). - * @param UARTx UART Instance. - * @param Guard time value. - * @retval None. - */ -__STATIC_INLINE void md_uart_set_scard_gt(UART_TypeDef *UARTx, uint32_t guardtime) -{ - MODIFY_REG(UARTx->SCARD, UART_SCARD_GT_MSK, guardtime<SCARD, UART_SCARD_GT_MSK))>>UART_SCARD_GT_POSS); -} - -/** - * @brief Set UARTx Prescaler value (Only UART). - * @note In IrDA Low-power and normal IrDA mode: - * Used for programming the prescaler for dividing the UART - * source clock to achieve the low-power frequency. - * The source clock is divided by the value given in the register (8 - * significant bits) - * In Smartcard mode: - * Used for programming the prescaler for dividing the UART - * source clock to provide the Smartcard clock. - * The value given in the register (5 significant bits) is multiplied by - * 2 to give the division factor of the source clock frequency. - * @param UARTx UART Instance. - * @param Prescaler value. - * @retval None - */ -__STATIC_INLINE void md_uart_set_scard_psc(UART_TypeDef *UARTx, uint32_t prescaler) -{ - MODIFY_REG(UARTx->SCARD, UART_SCARD_PSC_MSK, prescaler<SCARD, UART_SCARD_PSC_MSK))>>UART_SCARD_PSC_POSS); -} - -/** - * @brief Set UARTx Smartcard auto-retry count (Only UART). - * @note This bit-field specifies the number of retries in transmit and - * receive, in Smartcard mode. - * In transmission mode, it specifies the number of automatic - * retransmission retries, before generating a transmission error - * (FE bit set). - * In reception mode, it specifies the number or erroneous - * reception trials, before generating a reception error (RXNE and - * PE bits set). - * @param UARTx UART Instance. - * @param smartcard auto-retry count Min_Value=0x00 Max_Value=0x07. - * @retval None. - */ -__STATIC_INLINE void md_uart_set_scard_sccnt(UART_TypeDef *UARTx, uint32_t count) -{ - MODIFY_REG(UARTx->SCARD, UART_SCARD_SCCNT_MSK, count<SCARD, UART_SCARD_SCCNT_MSK))>>UART_SCARD_SCCNT_POSS); -} - -/** - * @brief Smartcard clock enable(Only UART). - * @note This bit allows the user to enable the SCK pin. - * @param UARTx UART Instance. - * @retval None. - */ -__STATIC_INLINE void md_uart_enable_scard_sclken(UART_TypeDef *UARTx) -{ - SET_BIT(UARTx->SCARD, UART_SCARD_SCLKEN_MSK); -} - -/** - * @brief Smartcard clock disable(Only UART). - * @param UARTx UART Instance. - * @retval None. - */ -__STATIC_INLINE void md_uart_disable_scard_sclken(UART_TypeDef *UARTx) -{ - CLEAR_BIT(UARTx->SCARD, UART_SCARD_SCLKEN_MSK); -} - -/** - * @brief Check if Smartcard clock is enable. - * @param UARTx UART Instance. - * @retval State of bit (1 or 0). - */ -__STATIC_INLINE uint32_t md_uart_is_enabled_scard_sclken(UART_TypeDef *UARTx) -{ - return (uint32_t)(READ_BIT(UARTx->SCARD, UART_SCARD_SCLKEN_MSK) == (UART_SCARD_SCLKEN_MSK)); -} - -/** - * @brief Smartcard NACK enable(Only UART). - * @note This bit allows the user to enable nack detection. - * @param UARTx UART Instance. - * @retval None. - */ -__STATIC_INLINE void md_uart_enable_scard_scnack(UART_TypeDef *UARTx) -{ - SET_BIT(UARTx->SCARD, UART_SCARD_SCNACK_MSK); -} - -/** - * @brief Smartcard NACK disable(Only UART). - * @param UARTx UART Instance. - * @retval None. - */ -__STATIC_INLINE void md_uart_disable_scard_scnack(UART_TypeDef *UARTx) -{ - CLEAR_BIT(UARTx->SCARD, UART_SCARD_SCNACK_MSK); -} - -/** - * @brief Check if Smartcard NACK is enabled. - * @param UARTx UART Instance. - * @retval State of bit (1 or 0). - */ -__STATIC_INLINE uint32_t md_uart_is_enabled_scard_scnack(UART_TypeDef *UARTx) -{ - return (uint32_t)(READ_BIT(UARTx->SCARD, UART_SCARD_SCNACK_MSK) == (UART_SCARD_SCNACK_MSK)); -} - -/** - * @brief Smartcard mode enable(Only UART). - * @param UARTx UART Instance. - * @retval None. - */ -__STATIC_INLINE void md_uart_enable_scard_scen(UART_TypeDef *UARTx) -{ - SET_BIT(UARTx->SCARD, UART_SCARD_SCEN_MSK); -} - -/** - * @brief Smartcard mode disable(Only UART). - * @param UARTx UART Instance. - * @retval None. - */ -__STATIC_INLINE void md_uart_disable_scard_scen(UART_TypeDef *UARTx) -{ - CLEAR_BIT(UARTx->SCARD, UART_SCARD_SCEN_MSK); -} - -/** - * @brief Check if Smartcard mode is enabled. - * @param UARTx UART Instance. - * @retval State of bit (1 or 0). - */ -__STATIC_INLINE uint32_t md_uart_is_enabled_scard_scen(UART_TypeDef *UARTx) -{ - return (uint32_t)(READ_BIT(UARTx->SCARD, UART_SCARD_SCEN_MSK) == (UART_SCARD_SCEN_MSK)); -} - -/** - * @brief Enable LIN mode break request. - * @note This bit is set by software and automatically cleared by - * hardware in the next clock cycle. - * Writing 1 to this bit sets request to send a BREAK on the line, as - * soon as the transmit machine is available. - * It generates 13 bits rate low pulse in Lin mode. - * @param UARTx UART Instance - * @retval None - */ -__STATIC_INLINE void md_uart_enable_lin_linbkreq(UART_TypeDef *UARTx) -{ - SET_BIT(UARTx->LIN, UART_LIN_LINBKREQ_MSK); -} - -/** - * @brief Disable LIN mode break request. - * @param UARTx UART Instance. - * @retval None. - */ -__STATIC_INLINE void md_uart_disable_linbkreq(UART_TypeDef *UARTx) -{ - CLEAR_BIT(UARTx->LIN, UART_LIN_LINBKREQ_MSK); -} - -/** - * @brief Check if LIN break is enabled - * @param None - * @retval State of bit (1 or 0). - */ -__STATIC_INLINE uint32_t md_uart_is_enable_linbkreq(UART_TypeDef *UARTx) -{ - return (READ_BIT(UARTx->LIN, UART_LIN_LINBKREQ_MSK) == (UART_LIN_LINBKREQ_MSK)); -} - -/** - * @brief UARTx LIN mode enable. - * @param UARTx UART Instance. - * @retval None. - */ -__STATIC_INLINE void md_uart_enable_lin_linen(UART_TypeDef *UARTx) -{ - SET_BIT(UARTx->LIN, UART_LIN_LINEN_MSK); -} - -/** - * @brief UART LIN mode disable. - * @param UARTx UART Instance. - * @retval None. - */ -__STATIC_INLINE void md_uart_disable_lin_linen(UART_TypeDef *UARTx) -{ - CLEAR_BIT(UARTx->LIN, UART_LIN_LINEN_MSK); -} - -/** - * @brief Check if UARTx LIN mode is enabled. - * @param UARTx UART Instance. - * @retval State of bit (1 or 0). - */ -__STATIC_INLINE uint32_t md_uart_is_enabled_lin_linen(UART_TypeDef *UARTx) -{ - return (uint32_t)(READ_BIT(UARTx->LIN, UART_LIN_LINEN_MSK) == (UART_LIN_LINEN_MSK)); -} - -/** - * @brief UARTx receive timeout enable. - * @note When this feature is enabled, the RTOIF flag in the UART_RIF - * register is set if the RX line is idle (no reception) for the duration - * programmed in the RTOR (receiver timeout register). - * @param UARTx UART Instance - * @retval None - */ -__STATIC_INLINE void md_uart_enable_rtor_rtoen(UART_TypeDef *UARTx) -{ - SET_BIT(UARTx->RTOR, UART_RTOR_RTOEN_MSK); -} - -/** - * @brief UARTx receive timeout disable. - * @param UARTx UART Instance. - * @retval None. - */ -__STATIC_INLINE void md_uart_disable_rtor_rtoen(UART_TypeDef *UARTx) -{ - CLEAR_BIT(UARTx->RTOR, UART_RTOR_RTOEN_MSK); -} - -/** - * @brief Check if UARTx receive timeout is enabled. - * @param UARTx UART Instance. - * @retval State of bit (1 or 0). - */ -__STATIC_INLINE uint32_t md_uart_is_enabled_rtor_rtoen(UART_TypeDef *UARTx) -{ - return (uint32_t)(READ_BIT(UARTx->RTOR, UART_RTOR_RTOEN_MSK) == (UART_RTOR_RTOEN_MSK)); -} - -/** - * @brief Set UARTx receiver timeout value. - * @note This bit-field gives the Receiver timeout value in terms of number of bit duration. - * In standard mode: - * the RTOF flag is set if, after the last received character, - * no new start bit is detected for more than the RTO value. - * In Smartcard mode: - * this value is used to implement the CWT and BWT. See Smartcard section for more details. - * In this case, the timeout measurement is done starting from the Stop Bit of the last - * received character. - * @param UARTx UART Instance. - * @param timeout UART timeout value. - * @retval None. - */ -__STATIC_INLINE void md_uart_set_rtor_rto(UART_TypeDef *UARTx, uint32_t timeout) -{ - MODIFY_REG(UARTx->RTOR, UART_RTOR_RTO_MSK, timeout<RTOR, UART_RTOR_RTO_MSK))>>UART_RTOR_RTO_POSS); -} - -/** - * @brief Set UARTx Transmit FIFO level. - * @note This is used to indicate the number of data entries in the Transmit FIFO. - * It's value from 0 to 16. - * @param UARTx UART Instance. - * @param Value between Min_Data=0x00 and Max_Data=0x010. - * @retval None. - */ -__STATIC_INLINE void md_uart_set_fcon_txfl(UART_TypeDef *UARTx, uint32_t level) -{ - MODIFY_REG(UARTx->FCON, UART_FCON_TXFL_MSK, level<FCON, UART_FCON_TXFL_MSK))>>UART_FCON_TXFL_POSS); -} - -/** - * @brief Set UARTx Transmit FIFO trigger threshold. - * @note This is used to select the threshold level in the transmit FIFO at - * which the Transmit FIFO trigger threshold flag is generated. - * @param UARTx UART Instance - * @param level This parameter can be one of the following values: - * @arg @ref MD_UART_FCON_TXTH_0 - * @arg @ref MD_UART_FCON_TXTH_2 - * @arg @ref MD_UART_FCON_TXTH_4 - * @arg @ref MD_UART_FCON_TXTH_8 - * @retval None - */ -__STATIC_INLINE void md_uart_set_fcon_txth(UART_TypeDef *UARTx, uint32_t level) -{ - MODIFY_REG(UARTx->FCON, UART_FCON_TXTH_MSK, level<FCON, UART_FCON_TXTH_MSK))>>UART_FCON_TXTH_POSS); -} - -/** - * @brief Transmit FIFO reset. - * @note When FIFO is set, all the byte in the transmit FIFO are cleared - * and treats the FIFO as empty. Note that this bit will return to 0 in - * the next clock cycle. - * @param UARTx UART Instance. - * @retval None. - */ -__STATIC_INLINE void md_uart_set_fcon_tfrst(UART_TypeDef *UARTx) -{ - SET_BIT(UARTx->FCON, UART_FCON_TFRST_MSK); -} - -/** - * @brief Set UARTx Receive FIFO level. - * @note This bit is set by hardware. This is used to indicate the number - * of data entries in the Receive FIFO. It's value from 0 to 16. - * @param UARTx UART Instance. - * @param Value between Min_Data=0x00 and Max_Data=0x010. - * @retval None. - */ -__STATIC_INLINE void md_uart_set_fcon_rxfl(UART_TypeDef *UARTx, uint32_t level) -{ - MODIFY_REG(UARTx->FCON, UART_FCON_RXFL_MSK, level<FCON, UART_FCON_RXFL_MSK))>>UART_FCON_TXFL_POSS); -} - -/** - * @brief Set UARTx Receive FIFO trigger threshold. - * @note This is used to select the threshold level in the receiver FIFO at - * which the Receive FIFO trigger threshold flag is generated. - * @param UARTx UART Instance. - * @param level This parameter can be one of the following values: - * @arg @ref MD_UART_FCON_RXTH_1 - * @arg @ref MD_UART_FCON_RXTH_4 - * @arg @ref MD_UART_FCON_RXTH_8 - * @arg @ref MD_UART_FCON_RXTH_14 - * @retval None - */ -__STATIC_INLINE void md_uart_set_fcon_rxth(UART_TypeDef *UARTx, uint32_t level) -{ - MODIFY_REG(UARTx->FCON, UART_FCON_RXTH_MSK, level<FCON, UART_FCON_RXTH_MSK))>>UART_FCON_RXTH_POSS); -} - -/** - * @brief Receive FIFO reset - * @note When FIFO is set, all the byte in the receiver FIFO are cleared - * and treats the FIFO as empty. Note that this bit will return to 0 in - * the next clock cycle. - * @param UARTx UART Instance. - * @retval None. - */ -__STATIC_INLINE void md_uart_set_fcon_rfrst(UART_TypeDef *UARTx) -{ - SET_BIT(UARTx->FCON, UART_FCON_RFRST_MSK); -} - -/** - * @brief Check if Transmit FIFO overrun error. - * @note This bit is set and cleared by hardware Tx line start transmit - * data. An overrun error occurs when the FIFO is full and a new - * character write at the Transmit. The data in the FIFO is retained - * and the data in the TXBR register is lost. - * @param UARTx UART Instance. - * @retval State of bit (1 or 0). - */ -__STATIC_INLINE uint32_t md_uart_is_active_flag_stat_tfoerr(UART_TypeDef *UARTx) -{ - return (READ_BIT(UARTx->STAT, UART_STAT_TFOERR_MSK) == (UART_STAT_TFOERR_MSK)); -} - -/** - * @brief Check if Transmit FIFO full. - * @note This bit is set and cleared by hardware when the TX FIFO is no - * longer full. - * @param UARTx UART Instance - * @retval State of bit (1 or 0). - */ -__STATIC_INLINE uint32_t md_uart_is_active_flag_stat_tffull(UART_TypeDef *UARTx) -{ - return (READ_BIT(UARTx->STAT, UART_STAT_TFFULL_MSK) == (UART_STAT_TFFULL_MSK)); -} - -/** - * @brief Check if Transmit FIFO empty. - * @note This bit is set and cleared by hardware when the TX FIFO is no - * longer empty. - * @param UARTx UART Instance. - * @retval State of bit (1 or 0). - */ -__STATIC_INLINE uint32_t md_uart_is_active_flag_stat_tfempty(UART_TypeDef *UARTx) -{ - return (READ_BIT(UARTx->STAT, UART_STAT_TFEMPTY_MSK) == (UART_STAT_TFEMPTY_MSK)); -} - -/** - * @brief Check if Transmit FIFO trigger threshold flag. - * @note This bit is set and cleared by hardware when transmit FIFO - * arrived threshold level in the FCR register. - * @param UARTx UART Instance. - * @retval State of bit (1 or 0). - */ -__STATIC_INLINE uint32_t md_uart_is_active_flag_stat_tfth(UART_TypeDef *UARTx) -{ - return (READ_BIT(UARTx->STAT, UART_STAT_TFTH_MSK) == (UART_STAT_TFTH_MSK)); -} - -/** - * @brief Check if Transmit shift register busy. - * @note This bit is cleared by hardware. - * @param UARTx UART Instance. - * @retval State of bit (1 or 0). - */ -__STATIC_INLINE uint32_t md_uart_is_active_flag_stat_tsbsy(UART_TypeDef *UARTx) -{ - return (READ_BIT(UARTx->STAT, UART_STAT_TSBUSY_MSK) == (UART_STAT_TSBUSY_MSK)); -} - -/** - * @brief Check if Receive FIFO underrun error. - * @note This bit is set and cleared by hardware when receive a new - * data. An underrun error occurs when the FIFO is empty at the - * receive. The data in the FIFO is read 0 in the RXBR register. - * @param UARTx UART Instance - * @retval State of bit (1 or 0). - */ -__STATIC_INLINE uint32_t md_uart_is_active_flag_stat_rfuerr(UART_TypeDef *UARTx) -{ - return (READ_BIT(UARTx->STAT, UART_STAT_RFUERR_MSK) == (UART_STAT_RFUERR_MSK)); -} - -/** - * @brief Check if Receive FIFO overrun error. - * @note This bit is set and cleared by hardware when read data in the - * RXBR register. An overrun error occurs when the FIFO is full - * and a new character arrives at the receiver. The data in the - * FIFO is retained and the data in the RXBR register is lost. - * @param UARTx UART Instance. - * @retval State of bit (1 or 0). - */ -__STATIC_INLINE uint32_t md_uart_is_active_flag_stat_rfoerr(UART_TypeDef *UARTx) -{ - return (READ_BIT(UARTx->STAT, UART_STAT_RFOERR_MSK) == (UART_STAT_RFOERR_MSK)); -} - -/** - * @brief Check if Receive FIFO full. - * @note This bit is set and cleared by hardware when the RX FIFO is no - * longer full. - * @param UARTx UART Instance. - * @retval State of bit (1 or 0). - */ -__STATIC_INLINE uint32_t md_uart_is_active_flag_stat_rffull(UART_TypeDef *UARTx) -{ - return (READ_BIT(UARTx->STAT, UART_STAT_RFFULL_MSK) == (UART_STAT_RFFULL_MSK)); -} - -/** - * @brief Check if Receive FIFO empty. - * @note This bit is cleared when the RX FIFO is no longer empty. - * @param UARTx UART Instance. - * @retval State of bit (1 or 0). - */ -__STATIC_INLINE uint32_t md_uart_is_active_flag_stat_rfempty(UART_TypeDef *UARTx) -{ - return (READ_BIT(UARTx->STAT, UART_STAT_RFEMPTY_MSK) == (UART_STAT_RFEMPTY_MSK)); -} - -/** - * @brief Check if Receive FIFO trigger threshold flag. - * @note This bit is set and cleared by hardware when receive FIFO - * arrived threshold level in the FCR register. - * @param UARTx UART Instance. - * @retval State of bit (1 or 0). - */ -__STATIC_INLINE uint32_t md_uart_is_active_flag_stat_rfth(UART_TypeDef *UARTx) -{ - return (READ_BIT(UARTx->STAT, UART_STAT_RFTH_MSK) == (UART_STAT_RFTH_MSK)); -} - -/** - * @brief Check if Receive shiftregister busy. - * @note This bit is set and cleared by hardware. - * @param UARTx UART Instance. - * @retval State of bit (1 or 0). - */ -__STATIC_INLINE uint32_t md_uart_is_active_flag_stat_rsbsy(UART_TypeDef *UARTx) -{ - return (READ_BIT(UARTx->STAT, UART_STAT_RSBUSY_MSK) == (UART_STAT_RSBUSY_MSK)); -} - -/** - * @brief Get UARTx Clear to send status. - * @note This bit is the complement of CTSn. When CTSn is asserted, it - * is an indication that the modem or data set is ready to exchange - * data with UART. - * @param ADCx ADC Instance. - * @retval State of bit (1 or 0). - */ -__STATIC_INLINE uint32_t md_uart_get_stat_ctssta(UART_TypeDef *UARTx) -{ - return (READ_BIT(UARTx->STAT, UART_STAT_CTSSTA_MSK)>>UART_STAT_CTSSTA_POS); -} - -/** - * @brief Check if Break error. - * @note This bit is used to indicate the detection of a break sequence on - * the serial input data. - * This error is associated with the character at the top of the FIFO. - * @param UARTx UART Instance. - * @retval State of bit (1 or 0). - */ -__STATIC_INLINE uint32_t md_uart_is_active_flag_stat_bkerr(UART_TypeDef *UARTx) -{ - return (READ_BIT(UARTx->STAT, UART_STAT_BKERR_MSK) == (UART_STAT_BKERR_MSK)); -} - -/** - * @brief Check if Framing Error. - * @note When the received characters stop bit is a logic 0(i.e. the - * receiver did not have a valid stop bit), a framing error occurs. - * This error is associated with the character at the top of the FIFO. - * @param UARTx UART Instance - * @retval State of bit (1 or 0). - */ -__STATIC_INLINE uint32_t md_uart_is_active_flag_stat_ferr(UART_TypeDef *UARTx) -{ - return (READ_BIT(UARTx->STAT, UART_STAT_FERR_MSK) == (UART_STAT_FERR_MSK)); -} - -/** - * @brief Check if Parity Error. - * @note When the receive character does not have correct parity - * information and is suspect, a parity error occurs. - * This error is associated with the character at the top of the FIFO. - * @param UARTx UART Instance - * @retval State of bit (1 or 0). - */ -__STATIC_INLINE uint32_t md_uart_is_active_flag_stat_perr(UART_TypeDef *UARTx) -{ - return (READ_BIT(UARTx->STAT, UART_STAT_PERR_MSK) == (UART_STAT_PERR_MSK)); -} - -/** - * @brief Transmit FIFO overrun interrupt enable. - * @param UARTx UART Instance. - * @retval None. - */ -__STATIC_INLINE void md_uart_enable_ier_tfover(UART_TypeDef *UARTx) -{ - SET_BIT(UARTx->IER, UART_IER_TFOVER_MSK); -} - -/** - * @brief Transmit FIFO empty interrupt enable. - * @param UARTx UART Instance. - * @retval None. - */ -__STATIC_INLINE void md_uart_enable_ier_tfempty(UART_TypeDef *UARTx) -{ - SET_BIT(UARTx->IER, UART_IER_TFEMPTY_MSK); -} - -/** - * @brief Transmit FIFO trigger threshold interrupt enable. - * @param UARTx UART Instance. - * @retval None. - */ -__STATIC_INLINE void md_uart_enable_ier_tfth(UART_TypeDef *UARTx) -{ - SET_BIT(UARTx->IER, UART_IER_TFTH_MSK); -} - -/** - * @brief Transmission byte complete enable. - * @param UARTx UART Instance. - * @retval None. - */ -__STATIC_INLINE void md_uart_enable_ier_tbc(UART_TypeDef *UARTx) -{ - SET_BIT(UARTx->IER, UART_IER_TBC_MSK); -} - -/** - * @brief Receive FIFO underrun interrupt enable. - * @param UARTx UART Instance. - * @retval None. - */ -__STATIC_INLINE void md_uart_enable_ier_rfuerr(UART_TypeDef *UARTx) -{ - SET_BIT(UARTx->IER, UART_IER_RFUERR_MSK); -} - -/** - * @brief Receive FIFO overrun interrupt enable. - * @param UARTx UART Instance. - * @retval None. - */ -__STATIC_INLINE void md_uart_enable_ier_rfoerr(UART_TypeDef *UARTx) -{ - SET_BIT(UARTx->IER, UART_IER_RFOERR_MSK); -} - -/** - * @brief Receive FIFO full interrupt enable. - * @param UARTx UART Instance. - * @retval None. - */ -__STATIC_INLINE void md_uart_enable_ier_rffull(UART_TypeDef *UARTx) -{ - SET_BIT(UARTx->IER, UART_IER_RFFULL_MSK); -} - -/** - * @brief Receive FIFO trigger threshold interrupt enable. - * @param UARTx UART Instance. - * @retval None. - */ -__STATIC_INLINE void md_uart_enable_ier_rfth(UART_TypeDef *UARTx) -{ - SET_BIT(UARTx->IER, UART_IER_RFTH_MSK); -} - -/** - * @brief Bit Noise detection enable. - * @param UARTx UART Instance. - * @retval None. - */ -__STATIC_INLINE void md_uart_enable_ier_noise(UART_TypeDef *UARTx) -{ - SET_BIT(UARTx->IER, UART_IER_NOISE_MSK); -} - -/** - * @brief End of block interrupt enable(Only UART). - * @param UARTx UART Instance. - * @retval None. - */ -__STATIC_INLINE void md_uart_enable_ier_eob(UART_TypeDef *UARTx) -{ - SET_BIT(UARTx->IER, UART_IER_EOB_MSK); -} - -/** - * @brief LINBK: LIN break detection interrupt enable(Only UART). - * @param UARTx UART Instance. - * @retval None. - */ -__STATIC_INLINE void md_uart_enable_ier_linbk(UART_TypeDef *UARTx) -{ - SET_BIT(UARTx->IER, UART_IER_LINBK_MSK); -} - -/** - * @brief Address match interrupt enable. - * @param UARTx UART Instance. - * @retval None. - */ -__STATIC_INLINE void md_uart_enable_ier_addrm(UART_TypeDef *UARTx) -{ - SET_BIT(UARTx->IER, UART_IER_ADDRM_MSK); -} - -/** - * @brief Receiver Timeout interrupt enable. - * @param UARTx UART Instance. - * @retval None. - */ -__STATIC_INLINE void md_uart_enable_ier_rxto(UART_TypeDef *UARTx) -{ - SET_BIT(UARTx->IER, UART_IER_RXTO_MSK); -} - -/** - * @brief Delta CTS status interrupt enable. - * @param UARTx UART Instance. - * @retval None. - */ -__STATIC_INLINE void md_uart_enable_ier_dcts(UART_TypeDef *UARTx) -{ - SET_BIT(UARTx->IER, UART_IER_DCTS_MSK); -} - -/** - * @brief Auto-Baud rate detection Timeout interrupt enable. - * @param UARTx UART Instance. - * @retval None. - */ -__STATIC_INLINE void md_uart_enable_ier_abto(UART_TypeDef *UARTx) -{ - SET_BIT(UARTx->IER, UART_IER_ABTO_MSK); -} - -/** - * @brief Auto-Baud rate detection End interrupt enable. - * @param UARTx UART Instance. - * @retval None. - */ -__STATIC_INLINE void md_uart_enable_ier_abend(UART_TypeDef *UARTx) -{ - SET_BIT(UARTx->IER, UART_IER_ABEND_MSK); -} - -/** - * @brief Receiver byte error interrupt enable. - * @param UARTx UART Instance. - * @retval None. - */ -__STATIC_INLINE void md_uart_enable_ier_rxberr(UART_TypeDef *UARTx) -{ - SET_BIT(UARTx->IER, UART_IER_RXBERR_MSK); -} - -/** - * @brief Transmit FIFO overrun interrupt disable. - * @param UARTx UART Instance. - * @retval None. - */ -__STATIC_INLINE void md_uart_disable_idr_tfover(UART_TypeDef *UARTx) -{ - SET_BIT(UARTx->IDR, UART_IDR_TFOVER_MSK); -} - -/** - * @brief Transmit FIFO empty interrupt disable. - * @param UARTx UART Instance. - * @retval None. - */ -__STATIC_INLINE void md_uart_disable_idr_tfempty(UART_TypeDef *UARTx) -{ - SET_BIT(UARTx->IDR, UART_IDR_TFEMPTY_MSK); -} - -/** - * @brief Transmit FIFO trigger threshold interrupt disable. - * @param UARTx UART Instance. - * @retval None. - */ -__STATIC_INLINE void md_uart_disable_idr_tfth(UART_TypeDef *UARTx) -{ - SET_BIT(UARTx->IDR, UART_IDR_TFTH_MSK); -} - -/** - * @brief Transmission byte complete interrupt disable. - * @param UARTx UART Instance. - * @retval None. - */ -__STATIC_INLINE void md_uart_disable_idr_tbc(UART_TypeDef *UARTx) -{ - SET_BIT(UARTx->IDR, UART_IDR_TBC_MSK); -} - -/** - * @brief Receive FIFO underrun interrupt disable. - * @param UARTx UART Instance. - * @retval None. - */ -__STATIC_INLINE void md_uart_disable_idr_rfuerr(UART_TypeDef *UARTx) -{ - SET_BIT(UARTx->IDR, UART_IDR_RFUERR_MSK); -} - -/** - * @brief Receive FIFO overrun interrupt disable. - * @param UARTx UART Instance. - * @retval None. - */ -__STATIC_INLINE void md_uart_disable_idr_rfoerr(UART_TypeDef *UARTx) -{ - SET_BIT(UARTx->IDR, UART_IDR_RFOERR_MSK); -} - -/** - * @brief Receive FIFO full interrupt disable. - * @param UARTx UART Instance. - * @retval None. - */ -__STATIC_INLINE void md_uart_disable_idr_rffull(UART_TypeDef *UARTx) -{ - SET_BIT(UARTx->IDR, UART_IDR_RFFULL_MSK); -} - -/** - * @brief Receive FIFO trigger threshold interrupt disable. - * @param UARTx UART Instance. - * @retval None. - */ -__STATIC_INLINE void md_uart_disable_idr_rfth(UART_TypeDef *UARTx) -{ - SET_BIT(UARTx->IDR, UART_IDR_RFTH_MSK); -} - -/** - * @brief Bit Noise detection disable. - * @param UARTx UART Instance. - * @retval None. - */ -__STATIC_INLINE void md_uart_disable_idr_noise(UART_TypeDef *UARTx) -{ - SET_BIT(UARTx->IDR, UART_IDR_NOISE_MSK); -} - -/** - * @brief End of block interrupt disable(Only UART). - * @param UARTx UART Instance. - * @retval None. - */ -__STATIC_INLINE void md_uart_disable_idr_eob(UART_TypeDef *UARTx) -{ - SET_BIT(UARTx->IDR, UART_IDR_EOB_MSK); -} - -/** - * @brief LIN break detection interrupt disable(Only UART). - * @param UARTx UART Instance. - * @retval None. - */ -__STATIC_INLINE void md_uart_disable_idr_linbk(UART_TypeDef *UARTx) -{ - SET_BIT(UARTx->IDR, UART_IDR_LINBK_MSK); -} - -/** - * @brief Address match interrupt disable. - * @param UARTx UART Instance. - * @retval None. - */ -__STATIC_INLINE void md_uart_disable_idr_addrm(UART_TypeDef *UARTx) -{ - SET_BIT(UARTx->IDR, UART_IDR_ADDRM_MSK); -} - -/** - * @brief Receiver Timeout interrupt disable. - * @param UARTx UART Instance. - * @retval None. - */ -__STATIC_INLINE void md_uart_disable_idr_rxto(UART_TypeDef *UARTx) -{ - SET_BIT(UARTx->IDR, UART_IDR_RXTO_MSK); -} - -/** - * @brief Delta CTS status interrupt disable. - * @param UARTx UART Instance. - * @retval None. - */ -__STATIC_INLINE void md_uart_disable_idr_dcts(UART_TypeDef *UARTx) -{ - SET_BIT(UARTx->IDR, UART_IDR_DCTS_MSK); -} - -/** - * @brief Auto-Baud rate detection Timeout interrupt disable. - * @param UARTx UART Instance. - * @retval None. - */ -__STATIC_INLINE void md_uart_disable_idr_abto(UART_TypeDef *UARTx) -{ - SET_BIT(UARTx->IDR, UART_IDR_ABTO_MSK); -} - -/** - * @brief Auto-Baud rate detection End interrupt disable. - * @param UARTx UART Instance. - * @retval None. - */ -__STATIC_INLINE void md_uart_disable_idr_abend(UART_TypeDef *UARTx) -{ - SET_BIT(UARTx->IDR, UART_IDR_ABEND_MSK); -} - -/** - * @brief Receiver byte error interrupt disable. - * @param UARTx UART Instance. - * @retval None. - */ -__STATIC_INLINE void md_uart_disable_idr_rxberr(UART_TypeDef *UARTx) -{ - SET_BIT(UARTx->IDR, UART_IDR_RXBERR_MSK); -} - -/** - * @brief Check if Tx FIFO overrun interrupt is enabled. - * @param UARTx UART Instance. - * @retval State of bit (1 or 0). - */ -__STATIC_INLINE uint32_t md_uart_is_enabled_ivs_tfover(UART_TypeDef *UARTx) -{ - return (READ_BIT(UARTx->IVS, UART_IVS_TFOVER_MSK) == (UART_IVS_TFOVER_MSK)); -} - -/** - * @brief Check if Tx FIFO empty interrupt is enabled. - * @param UARTx UART Instance. - * @retval State of bit (1 or 0). - */ -__STATIC_INLINE uint32_t md_uart_is_enabled_ivs_tfempty(UART_TypeDef *UARTx) -{ - return (READ_BIT(UARTx->IVS, UART_IVS_TFEMPTY_MSK) == (UART_IVS_TFEMPTY_MSK)); -} - -/** - * @brief Check if Tx FIFO trigger threshold interrupt is enabled. - * @param UARTx UART Instance. - * @retval State of bit (1 or 0). - */ -__STATIC_INLINE uint32_t md_uart_is_enabled_ivs_tfth(UART_TypeDef *UARTx) -{ - return (READ_BIT(UARTx->IVS, UART_IVS_TFTH_MSK) == (UART_IVS_TFTH_MSK)); -} - -/** - * @brief Check if Tx complete interrupt is enabled. - * @param UARTx UART Instance. - * @retval State of bit (1 or 0). - */ -__STATIC_INLINE uint32_t md_uart_is_enabled_ivs_tbc(UART_TypeDef *UARTx) -{ - return (READ_BIT(UARTx->IVS, UART_IVS_TBC_MSK) == (UART_IVS_TBC_MSK)); -} - -/** - * @brief Check if Rx FIFO underrun interrupt is enabled. - * @param UARTx UART Instance. - * @retval State of bit (1 or 0). - */ -__STATIC_INLINE uint32_t md_uart_is_enabled_ivs_rfuerr(UART_TypeDef *UARTx) -{ - return (READ_BIT(UARTx->IVS, UART_IVS_RFUERR_MSK) == (UART_IVS_RFUERR_MSK)); -} - -/** - * @brief Check if Rx FIFO overrun interrupt is enabled. - * @param UARTx UART Instance. - * @retval State of bit (1 or 0). - */ -__STATIC_INLINE uint32_t md_uart_is_enabled_ivs_rfoerr(UART_TypeDef *UARTx) -{ - return (READ_BIT(UARTx->IVS, UART_IVS_RFOERR_MSK) == (UART_IVS_RFOERR_MSK)); -} - -/** - * @brief Check if Rx FIFO full interrupt is enabled. - * @param UARTx UART Instance. - * @retval State of bit (1 or 0). - */ -__STATIC_INLINE uint32_t md_uart_is_enabled_ivs_rffull(UART_TypeDef *UARTx) -{ - return (READ_BIT(UARTx->IVS, UART_IVS_RFFULL_MSK) == (UART_IVS_RFFULL_MSK)); -} - -/** - * @brief Check if Rx FIFO trigger threshold interrupt is enabled. - * @param UARTx UART Instance. - * @retval State of bit (1 or 0). - */ -__STATIC_INLINE uint32_t md_uart_is_enabled_ivs_rfth(UART_TypeDef *UARTx) -{ - return (READ_BIT(UARTx->IVS, UART_IVS_RFTH_MSK) == (UART_IVS_RFTH_MSK)); -} - -/** - * @brief Check if noise detection interrupt is enabled. - * @param UARTx UART Instance. - * @retval State of bit (1 or 0). - */ -__STATIC_INLINE uint32_t md_uart_is_enabled_ivs_noise(UART_TypeDef *UARTx) -{ - return (READ_BIT(UARTx->IVS, UART_IVS_NOISE_MSK) == (UART_IVS_NOISE_MSK)); -} - -/** - * @brief Check if end of block detection interrupt is enabled. - * @param UARTx UART Instance. - * @retval State of bit (1 or 0). - */ -__STATIC_INLINE uint32_t md_uart_is_enabled_ivs_eob(UART_TypeDef *UARTx) -{ - return (READ_BIT(UARTx->IVS, UART_IVS_EOB_MSK) == (UART_IVS_EOB_MSK)); -} - -/** - * @brief Check if LIN break detection interrupt is enabled. - * @param UARTx UART Instance. - * @retval State of bit (1 or 0). - */ -__STATIC_INLINE uint32_t md_uart_is_enabled_ivs_linbk(UART_TypeDef *UARTx) -{ - return (READ_BIT(UARTx->IVS, UART_IVS_LINBK_MSK) == (UART_IVS_LINBK_MSK)); -} - -/** - * @brief Check if address match interrupt is enabled. - * @param UARTx UART Instance. - * @retval State of bit (1 or 0). - */ -__STATIC_INLINE uint32_t md_uart_is_enabled_ivs_addrm(UART_TypeDef *UARTx) -{ - return (READ_BIT(UARTx->IVS, UART_IVS_ADDRM_MSK) == (UART_IVS_ADDRM_MSK)); -} - -/** - * @brief Check if RX timeout interrupt is enabled. - * @param UARTx UART Instance. - * @retval State of bit (1 or 0). - */ -__STATIC_INLINE uint32_t md_uart_is_enabled_ivs_rxto(UART_TypeDef *UARTx) -{ - return (READ_BIT(UARTx->IVS, UART_IVS_RXTO_MSK) == (UART_IVS_RXTO_MSK)); -} - -/** - * @brief Check if delta CTS status interrupt is enabled. - * @param UARTx UART Instance. - * @retval State of bit (1 or 0). - */ -__STATIC_INLINE uint32_t md_uart_is_enabled_ivs_dcts(UART_TypeDef *UARTx) -{ - return (READ_BIT(UARTx->IVS, UART_IVS_DCTS_MSK) == (UART_IVS_DCTS_MSK)); -} - -/** - * @brief Check if auto-baud rate detection interrupt is enabled. - * @param UARTx UART Instance. - * @retval State of bit (1 or 0). - */ -__STATIC_INLINE uint32_t md_uart_is_enabled_ivs_abto(UART_TypeDef *UARTx) -{ - return (READ_BIT(UARTx->IVS, UART_IVS_ABTO_MSK) == (UART_IVS_ABTO_MSK)); -} - -/** - * @brief Check if auto-baud rate detection end interrupt is enabled. - * @param UARTx UART Instance. - * @retval State of bit (1 or 0). - */ -__STATIC_INLINE uint32_t md_uart_is_enabled_ivs_abend(UART_TypeDef *UARTx) -{ - return (READ_BIT(UARTx->IVS, UART_IVS_ABEND_MSK) == (UART_IVS_ABEND_MSK)); -} - -/** - * @brief Check if RX byte error interrupt is enabled. - * @param UARTx UART Instance. - * @retval State of bit (1 or 0). - */ -__STATIC_INLINE uint32_t md_uart_is_enabled_ivs_rxberr(UART_TypeDef *UARTx) -{ - return (READ_BIT(UARTx->IVS, UART_IVS_RXBERR_MSK) == (UART_IVS_RXBERR_MSK)); -} - -/** - * @brief Get Transmit FIFO overrun interrupt flag. - * @note This bit is set by hardware when an overrun error occurs that - * the FIFO is full and a new character write at the Transmit. - * @param UARTx UART Instance. - * @retval State of bit (1 or 0). - */ -__STATIC_INLINE uint32_t md_uart_is_active_flag_rif_tfover(UART_TypeDef *UARTx) -{ - return (READ_BIT(UARTx->RIF, UART_RIF_TFOVER_MSK) == (UART_RIF_TFOVER_MSK)); -} - -/** - * @brief Get Transmit FIFO empty interrupt flag. - * @note This bit is set by hardware when transmit FIFO is empty from - * have data to empty. - * @param UARTx UART Instance. - * @retval State of bit (1 or 0). - */ -__STATIC_INLINE uint32_t md_uart_is_active_flag_rif_txempty(UART_TypeDef *UARTx) -{ - return (READ_BIT(UARTx->RIF, UART_RIF_TFEMPTY_MSK) == (UART_RIF_TFEMPTY_MSK)); -} - -/** - * @brief Get Transmit FIFO trigger threshold interrupt flag - * @note This bit is set by hardware when transmit FIFO arrived - * threshold level in the FCR register. - * @param UARTx UART Instance - * @retval State of bit (1 or 0). - */ -__STATIC_INLINE uint32_t md_uart_is_active_flag_rif_tfth(UART_TypeDef *UARTx) -{ - return (READ_BIT(UARTx->RIF, UART_RIF_TFTH_MSK) == (UART_RIF_TFTH_MSK)); -} - -/** - * @brief Get Transmission byte complete interrupt flag. - * @note This bit is set by hardware when transmission byte complete. - * @param UARTx UART Instance - * @retval State of bit (1 or 0). - */ -__STATIC_INLINE uint32_t md_uart_is_active_flag_rif_tbc(UART_TypeDef *UARTx) -{ - return (READ_BIT(UARTx->RIF, UART_RIF_TBC_MSK) == (UART_RIF_TBC_MSK)); -} - -/** - * @brief Get Receive FIFO underrun interrupt flag - * @note This bit is set by hardware when an underrun error occurs that - * the FIFO is empty and a new character read at the Receive. - * @param UARTx UART Instance - * @retval State of bit (1 or 0). - */ -__STATIC_INLINE uint32_t md_uart_is_active_flag_rif_rfuerr(UART_TypeDef *UARTx) -{ - return (READ_BIT(UARTx->RIF, UART_RIF_RFUERR_MSK) == (UART_RIF_RFUERR_MSK)); -} - -/** - * @brief Get Receive FIFO overrun interrupt flag. - * @note This bit is set by hardware when an overrun error occurs that - * the FIFO is full and a new character arrive at the Receive. - * @param UARTx UART Instance - * @retval State of bit (1 or 0). - */ -__STATIC_INLINE uint32_t md_uart_is_active_flag_rif_rfoerr(UART_TypeDef *UARTx) -{ - return (READ_BIT(UARTx->RIF, UART_RIF_RFOERR_MSK) == (UART_RIF_RFOERR_MSK)); -} - -/** - * @brief Get Receive FIFO full interrupt flag. - * @note This bit is set by hardware when receive FIFO is full. - * @param UARTx UART Instance. - * @retval State of bit (1 or 0). - */ -__STATIC_INLINE uint32_t md_uart_is_active_flag_rif_rffull(UART_TypeDef *UARTx) -{ - return (READ_BIT(UARTx->RIF, UART_RIF_RFFULL_MSK) == (UART_RIF_RFFULL_MSK)); -} - -/** - * @brief Get Receive FIFO trigger threshold interrupt flag. - * @note This bit is set by hardware when receive FIFO arrived threshold - * level in the FCR register. - * @param UARTx UART Instance. - * @retval State of bit (1 or 0). - */ -__STATIC_INLINE uint32_t md_uart_is_active_flag_rif_rfth(UART_TypeDef *UARTx) -{ - return (READ_BIT(UARTx->RIF, UART_RIF_RFTH_MSK) == (UART_RIF_RFTH_MSK)); -} - -/** - * @brief Get Bit Noise detection interrupt flag. - * @note This bit is set by hardware when START bit Noise is detected. - * @param UARTx UART Instance. - * @retval State of bit (1 or 0). - */ -__STATIC_INLINE uint32_t md_uart_is_active_flag_rif_noise(UART_TypeDef *UARTx) -{ - return (READ_BIT(UARTx->RIF, UART_RIF_NOISE_MSK) == (UART_RIF_NOISE_MSK)); -} - -/** - * @brief Get End of block interrupt flag(Only UART). - * @note This bit is set by hardware when blcok length value equals the - * number of data byte. - * @param UARTx UART Instance. - * @retval State of bit (1 or 0). - */ -__STATIC_INLINE uint32_t md_uart_is_active_flag_rif_eob(UART_TypeDef *UARTx) -{ - return (READ_BIT(UARTx->RIF, UART_RIF_EOB_MSK) == (UART_RIF_EOB_MSK)); -} - -/** - * @brief Get LIN break detection interrupt flag(Only UART). - * @note This bit is set by hardware when lin break is detected. - * @param UARTx UART Instance. - * @retval State of bit (1 or 0). - */ -__STATIC_INLINE uint32_t md_uart_is_active_flag_rif_linbk(UART_TypeDef *UARTx) -{ - return (READ_BIT(UARTx->RIF, UART_RIF_LINBK_MSK) == (UART_RIF_LINBK_MSK)); -} - -/** - * @brief Get Address match interrupt flag. - * @note This bit is set by hardware when the data in the RXBR register - * defined by ADD[7:0] in the RS485 register is received. - * @param UARTx UART Instance - * @retval State of bit (1 or 0). - */ -__STATIC_INLINE uint32_t md_uart_is_active_flag_rif_addrm(UART_TypeDef *UARTx) -{ - return (READ_BIT(UARTx->RIF, UART_RIF_ADDRM_MSK) == (UART_RIF_ADDRM_MSK)); -} - -/** - * @brief Get Receiver Timeout interrupt flag. - * @note This bit is set by hardware when the timeout value, - * programmed in the RTOR register has lapsed, without any - * communication. - * @param UARTx UART Instance - * @retval State of bit (1 or 0). - */ -__STATIC_INLINE uint32_t md_uart_is_active_flag_rif_rxto(UART_TypeDef *UARTx) -{ - return (READ_BIT(UARTx->RIF, UART_RIF_RXTO_MSK) == (UART_RIF_RXTO_MSK)); -} - -/** - * @brief Get Delta CTS status interrupt flag. - * @note This bit is set by hardware when the CTS input toggles. - * @param UARTx UART Instance - * @retval State of bit (1 or 0). - */ -__STATIC_INLINE uint32_t md_uart_is_active_flag_rif_dcts(UART_TypeDef *UARTx) -{ - return (READ_BIT(UARTx->RIF, UART_RIF_DCTS_MSK) == (UART_RIF_DCTS_MSK)); -} - -/** - * @brief Get Auto-Baud rate detection timeout interrupt flag. - * @note This bit is set by hardware when the baud rate detection timeout. - * @param UARTx UART Instance. - * @retval State of bit (1 or 0). - */ -__STATIC_INLINE uint32_t md_uart_is_active_flag_rif_abto(UART_TypeDef *UARTx) -{ - return (READ_BIT(UARTx->RIF, UART_RIF_ABTO_MSK) == (UART_RIF_ABTO_MSK)); -} - -/** - * @brief Get Auto-Baud rate detection end interrupt flag. - * @note This bit is set by hardware when the baud rate detection end. - * @param UARTx UART Instance. - * @retval State of bit (1 or 0). - */ -__STATIC_INLINE uint32_t md_uart_is_active_flag_rif_abend(UART_TypeDef *UARTx) -{ - return (READ_BIT(UARTx->RIF, UART_RIF_ABEND_MSK) == (UART_RIF_ABEND_MSK)); -} - -/** - * @brief Get Receiver byte error flag. - * @note This bit is set by hardware when a parity error or frame error - * occurs in receiver. - * @param UARTx UART Instance. - * @retval State of bit (1 or 0). - */ -__STATIC_INLINE uint32_t md_uart_is_active_flag_rif_rxberr(UART_TypeDef *UARTx) -{ - return (READ_BIT(UARTx->RIF, UART_RIF_RXBERR_MSK) == (UART_RIF_RXBERR_MSK)); -} - -/** - * @brief Get Transmit FIFO overrun interrupt flag masked. - * @note This bit is set by hardware when an overrun error occurs that - * the FIFO is full and a new character write at the Transmit. - * @param UARTx UART Instance - * @retval State of bit (1 or 0). - */ -__STATIC_INLINE uint32_t md_uart_is_active_flag_ifm_tfover(UART_TypeDef *UARTx) -{ - return (READ_BIT(UARTx->RIF, UART_IFM_TFOVER_MSK) == (UART_IFM_TFOVER_MSK)); -} - -/** - * @brief Get Transmit FIFO empty interrupt flag masked. - * @note This bit is set by hardware when transmit FIFO is empty from - * have data to empty. - * @param UARTx UART Instance. - * @retval State of bit (1 or 0). - */ -__STATIC_INLINE uint32_t md_uart_is_active_flag_ifm_txempty(UART_TypeDef *UARTx) -{ - return (READ_BIT(UARTx->RIF, UART_IFM_TFEMPTY_MSK) == (UART_IFM_TFEMPTY_MSK)); -} - -/** - * @brief Get Transmit FIFO trigger threshold interrupt flag masked. - * @note This bit is set by hardware when transmit FIFO arrived - * threshold level in the FCR register. - * @param UARTx UART Instance - * @retval State of bit (1 or 0). - */ -__STATIC_INLINE uint32_t md_uart_is_active_flag_ifm_tfth(UART_TypeDef *UARTx) -{ - return (READ_BIT(UARTx->RIF, UART_IFM_TFTH_MSK) == (UART_IFM_TFTH_MSK)); -} - -/** - * @brief Get Transmission byte complete interrupt flag masked. - * @note This bit is set by hardware when transmission byte complete. - * @param UARTx UART Instance. - * @retval State of bit (1 or 0). - */ -__STATIC_INLINE uint32_t md_uart_is_active_flag_ifm_tbc(UART_TypeDef *UARTx) -{ - return (READ_BIT(UARTx->RIF, UART_IFM_TBC_MSK) == (UART_IFM_TBC_MSK)); -} - -/** - * @brief Get Receive FIFO underrun interrupt flag masked. - * @note This bit is set by hardware when an underrun error occurs that - * the FIFO is empty and a new character read at the Receive. - * @param UARTx UART Instance - * @retval State of bit (1 or 0). - */ -__STATIC_INLINE uint32_t md_uart_is_active_flag_ifm_rfuerr(UART_TypeDef *UARTx) -{ - return (READ_BIT(UARTx->RIF, UART_IFM_RFUERR_MSK) == (UART_IFM_RFUERR_MSK)); -} - -/** - * @brief Get Receive FIFO overrun interrupt flag masked. - * @note This bit is set by hardware when an overrun error occurs that - * the FIFO is full and a new character arrive at the Receive. - * @param UARTx UART Instance - * @retval State of bit (1 or 0). - */ -__STATIC_INLINE uint32_t md_uart_is_active_flag_ifm_rfoerr(UART_TypeDef *UARTx) -{ - return (READ_BIT(UARTx->RIF, UART_IFM_RFOERR_MSK) == (UART_IFM_RFOERR_MSK)); -} - -/** - * @brief Get Receive FIFO full interrupt flag masked. - * @note This bit is set by hardware when receive FIFO is full. - * @param UARTx UART Instance. - * @retval State of bit (1 or 0). - */ -__STATIC_INLINE uint32_t md_uart_is_active_flag_ifm_rffull(UART_TypeDef *UARTx) -{ - return (READ_BIT(UARTx->RIF, UART_IFM_RFFULL_MSK) == (UART_IFM_RFFULL_MSK)); -} - -/** - * @brief Get Receive FIFO trigger threshold interrupt flag masked. - * @note This bit is set by hardware when receive FIFO arrived threshold - * level in the FCR register. - * @param UARTx UART Instance - * @retval State of bit (1 or 0). - */ -__STATIC_INLINE uint32_t md_uart_is_active_flag_ifm_rfth(UART_TypeDef *UARTx) -{ - return (READ_BIT(UARTx->RIF, UART_IFM_RFTH_MSK) == (UART_IFM_RFTH_MSK)); -} - -/** - * @brief Get Bit Noise detection interrupt flag masked. - * @note This bit is set by hardware when START bit Noise is detected. - * @param UARTx UART Instance - * @retval State of bit (1 or 0). - */ -__STATIC_INLINE uint32_t md_uart_is_active_flag_ifm_noise(UART_TypeDef *UARTx) -{ - return (READ_BIT(UARTx->RIF, UART_IFM_NOISE_MSK) == (UART_IFM_NOISE_MSK)); -} - -/** - * @brief Get End of block interrupt flag masked(Only UART). - * @note This bit is set by hardware when block length value equals the - * number of data byte. - * @param UARTx UART Instance. - * @retval State of bit (1 or 0). - */ -__STATIC_INLINE uint32_t md_uart_is_active_flag_ifm_eob(UART_TypeDef *UARTx) -{ - return (READ_BIT(UARTx->RIF, UART_IFM_EOB_MSK) == (UART_IFM_EOB_MSK)); -} - -/** - * @brief Get LIN break detection interrupt flag masked(Only UART). - * @note This bit is set by hardware when lin break is detected. - * @param UARTx UART Instance - * @retval State of bit (1 or 0). - */ -__STATIC_INLINE uint32_t md_uart_is_active_flag_ifm_linbk(UART_TypeDef *UARTx) -{ - return (READ_BIT(UARTx->RIF, UART_IFM_LINBK_MSK) == (UART_IFM_LINBK_MSK)); -} - -/** - * @brief Get Address match interrupt flag masked. - * @note This bit is set by hardware when the data in the RXBR register - * defined by ADD[7:0] in the RS485 register is received. - * @param UARTx UART Instance. - * @retval State of bit (1 or 0). - */ -__STATIC_INLINE uint32_t md_uart_is_active_flag_ifm_addrm(UART_TypeDef *UARTx) -{ - return (READ_BIT(UARTx->RIF, UART_IFM_ADDRM_MSK) == (UART_IFM_ADDRM_MSK)); -} - -/** - * @brief Get Receiver Timeout interrupt flag masked. - * @note This bit is set by hardware when the timeout value, - * programmed in the RTOR register has lapsed, without any - * communication. - * @param UARTx UART Instance - * @retval State of bit (1 or 0). - */ -__STATIC_INLINE uint32_t md_uart_is_active_flag_ifm_rxto(UART_TypeDef *UARTx) -{ - return (READ_BIT(UARTx->RIF, UART_IFM_RXTO_MSK) == (UART_IFM_RXTO_MSK)); -} - -/** - * @brief Get Delta CTS status interrupt flag masked. - * @note This bit is set by hardware when the CTS input toggles. - * @param UARTx UART Instance. - * @retval State of bit (1 or 0). - */ -__STATIC_INLINE uint32_t md_uart_is_active_flag_ifm_dcts(UART_TypeDef *UARTx) -{ - return (READ_BIT(UARTx->IFM, UART_RIF_DCTS_MSK) == (UART_IFM_DCTS_MSK)); -} - -/** - * @brief Get Auto-Baud rate detection timeout interrupt flag masked. - * @note This bit is set by hardware when the baud rate detection timeout. - * @param UARTx UART Instance. - * @retval State of bit (1 or 0). - */ -__STATIC_INLINE uint32_t md_uart_is_active_flag_ifm_abto(UART_TypeDef *UARTx) -{ - return (READ_BIT(UARTx->RIF, UART_IFM_ABTO_MSK) == (UART_IFM_ABTO_MSK)); -} - -/** - * @brief Get Auto-Baud rate detection end interrupt flag masked. - * @note This bit is set by hardware when the baud rate detection end. - * @param UARTx UART Instance - * @retval State of bit (1 or 0). - */ -__STATIC_INLINE uint32_t md_uart_is_active_flag_ifm_abend(UART_TypeDef *UARTx) -{ - return (READ_BIT(UARTx->RIF, UART_IFM_ABEND_MSK) == (UART_IFM_ABEND_MSK)); -} - -/** - * @brief Get Receiver byte error interrupt flag masked. - * @note This bit is set by hardware when a parity error, frame error or - * break error occurs in receiver. - * @param UARTx UART Instance. - * @retval State of bit (1 or 0). - */ -__STATIC_INLINE uint32_t md_uart_is_active_flag_ifm_rxberr(UART_TypeDef *UARTx) -{ - return (READ_BIT(UARTx->RIF, UART_IFM_RXBERR_MSK) == (UART_IFM_RXBERR_MSK)); -} - -/** - * @brief Transmit FIFO overrun interrupt flag clear. - * @param UARTx UART Instance. - * @retval State of bit (1 or 0). - */ -__STATIC_INLINE void md_uart_clear_flag_txover(UART_TypeDef *UARTx) -{ - SET_BIT(UARTx->ICR, UART_ICR_TFOVER_MSK); -} - -/** - * @brief Transmit FIFO empty interrupt flag clear. - * @param UARTx UART Instance. - * @retval State of bit (1 or 0). - */ -__STATIC_INLINE void md_uart_clear_flag_txempty(UART_TypeDef *UARTx) -{ - SET_BIT(UARTx->ICR, UART_ICR_TFEMPTY_MSK); -} - -/** - * @brief Transmit FIFO trigger threshold interrupt flag clear. - * @param UARTx UART Instance. - * @retval State of bit (1 or 0). - */ -__STATIC_INLINE void md_uart_clear_flag_tfth(UART_TypeDef *UARTx) -{ - SET_BIT(UARTx->ICR, UART_ICR_TFTH_MSK); -} - -/** - * @brief Transmission byte complete interrupt flag clear. - * @param UARTx UART Instance. - * @retval State of bit (1 or 0). - */ -__STATIC_INLINE void md_uart_clear_flag_tbc(UART_TypeDef *UARTx) -{ - SET_BIT(UARTx->ICR, UART_ICR_TBC_MSK); -} - -/** - * @brief Receive FIFO underrun interrupt flag clear. - * @param UARTx UART Instance. - * @retval State of bit (1 or 0). - */ -__STATIC_INLINE void md_uart_clear_flag_rfuerr(UART_TypeDef *UARTx) -{ - SET_BIT(UARTx->ICR, UART_ICR_RFUERR_MSK); -} - -/** - * @brief Receive FIFO overrun interrupt flag clear. - * @param UARTx UART Instance. - * @retval State of bit (1 or 0). - */ -__STATIC_INLINE void md_uart_clear_flag_rfoerr(UART_TypeDef *UARTx) -{ - SET_BIT(UARTx->ICR, UART_ICR_RFOERR_MSK); -} - -/** - * @brief Receive FIFO full interrupt flag clear. - * @param UARTx UART Instance. - * @retval State of bit (1 or 0). - */ -__STATIC_INLINE void md_uart_clear_flag_rffull(UART_TypeDef *UARTx) -{ - SET_BIT(UARTx->ICR, UART_ICR_RFFULL_MSK); -} - -/** - * @brief Receive FIFO trigger threshold interrupt flag clear. - * @param UARTx UART Instance. - * @retval State of bit (1 or 0). - */ -__STATIC_INLINE void md_uart_clear_flag_rfth(UART_TypeDef *UARTx) -{ - SET_BIT(UARTx->ICR, UART_ICR_RFTH_MSK); -} - -/** - * @brief Bit Noise detection interrupt flag clear. - * @param UARTx UART Instance. - * @retval State of bit (1 or 0). - */ -__STATIC_INLINE void md_uart_clear_flag_noise(UART_TypeDef *UARTx) -{ - SET_BIT(UARTx->ICR, UART_ICR_NOISE_MSK); -} - -/** - * @brief End of block interrupt flag clear(Only UART). - * @param UARTx UART Instance. - * @retval State of bit (1 or 0). - */ -__STATIC_INLINE void md_uart_clear_flag_eob(UART_TypeDef *UARTx) -{ - SET_BIT(UARTx->ICR, UART_ICR_EOB_MSK); -} - -/** - * @brief LIN break detection interrupt flag clear(Only UART). - * @param UARTx UART Instance. - * @retval State of bit (1 or 0). - */ -__STATIC_INLINE void md_uart_clear_flag_linbk(UART_TypeDef *UARTx) -{ - SET_BIT(UARTx->ICR, UART_ICR_LINBK_MSK); -} - -/** - * @brief Address match interrupt flag clear. - * @param UARTx UART Instance. - * @retval State of bit (1 or 0). - */ -__STATIC_INLINE void md_uart_clear_flag_addrm(UART_TypeDef *UARTx) -{ - SET_BIT(UARTx->ICR, UART_ICR_ADDRM_MSK); -} - -/** - * @brief Receiver Timeout interrupt flag clear. - * @param UARTx UART Instance. - * @retval State of bit (1 or 0). - */ -__STATIC_INLINE void md_uart_clear_flag_rxto(UART_TypeDef *UARTx) -{ - SET_BIT(UARTx->ICR, UART_ICR_RXTO_MSK); -} - -/** - * @brief Delta CTS status interrupt flag clear. - * @param UARTx UART Instance. - * @retval State of bit (1 or 0). - */ -__STATIC_INLINE void md_uart_clear_flag_dcts(UART_TypeDef *UARTx) -{ - SET_BIT(UARTx->ICR, UART_ICR_DCTS_MSK); -} - -/** - * @brief Auto-Baud rate detection timeout interrupt flag clear. - * @param UARTx UART Instance. - * @retval State of bit (1 or 0). - */ -__STATIC_INLINE void md_uart_clear_flag_abto(UART_TypeDef *UARTx) -{ - SET_BIT(UARTx->ICR, UART_ICR_ABTO_MSK); -} - -/** - * @brief Auto-Baud rate detection end interrupt flag clear. - * @param UARTx UART Instance. - * @retval State of bit (1 or 0). - */ -__STATIC_INLINE void md_uart_clear_flag_abend(UART_TypeDef *UARTx) -{ - SET_BIT(UARTx->ICR, UART_ICR_ABEND_MSK); -} - -/** - * @brief Receiver byte error interrupt flag clear. - * @param UARTx UART Instance. - * @retval State of bit (1 or 0). - */ -__STATIC_INLINE void md_uart_clear_flag_rxberr(UART_TypeDef *UARTx) -{ - SET_BIT(UARTx->ICR, UART_ICR_RXBERR_MSK); -} - -/** - * @} MD_UART_Public_Macros UART Public Macros - */ - -/* Public functions -----------------------------------------------------------*/ -void md_uart_set_baudrate (UART_TypeDef *UARTx, uint32_t baudrate); -void md_uart_init(UART_TypeDef *UARTx, md_uart_init_typedef *UART_InitStruct); -void md_uart_send (UART_TypeDef *UARTx, uint8_t ch); -uint8_t md_uart_recv (UART_TypeDef *UARTx); -uint32_t md_uart_get_baudrate (UART_TypeDef *UARTx); - -/** - * @} UART - */ - -#endif - -/** - * @} Micro_Driver - */ - - -#ifdef __cplusplus -} - -#endif - -#endif - -/******************* (C) COPYRIGHT Eastsoft Microelectronics *****END OF FILE****/ diff --git a/bsp/essemi/es32f0271/libraries/ES32F027x_MD_StdPeriph_Driver/Include/md_wwdt.h b/bsp/essemi/es32f0271/libraries/ES32F027x_MD_StdPeriph_Driver/Include/md_wwdt.h deleted file mode 100644 index f2f1a86a29..0000000000 --- a/bsp/essemi/es32f0271/libraries/ES32F027x_MD_StdPeriph_Driver/Include/md_wwdt.h +++ /dev/null @@ -1,382 +0,0 @@ -/** - ****************************************************************************** - * @file md_wwdt.h - * @brief ES32F0271 WWDT HEAD File. - * - * @version V0.01 - * @date 4/12/2018 - * @author Eastsoft AE Team - * @note - * detailed description - * - * Copyright (C) 2018 Shanghai Eastsoft Microelectronics Co., Ltd. ALL rights reserved. - ******************************************************************************* - */ - -/* Define to prevent recursive inclusion -------------------------------------*/ -#ifndef __MD_WWDT_H__ -#define __MD_WWDT_H__ - -#ifdef __cplusplus -extern "C" { -#endif - -/* Includes -------------------------------------------------------------------*/ -#include "es32f0271.h" -#include "reg_wwdt.h" - -/** @addtogroup Micro_Driver - * @{ - */ - -#if defined (WWDT) -/** @defgroup WWDT WWDT - * @brief WWDT micro driver - * @{ - */ - -/* Public Init Structure ------------------------------------------------------*/ -/** @defgroup MD_WWDT_PT_INIT WWDT Public Init Structure - * @brief WWDT Init Structure. - * @{ - */ -typedef struct -{ - uint32_t Prescaler; /*!< Specifies the prescaler value of the WWDT. - This parameter can be a value of @ref WWDT_Prescaler */ - - uint32_t Window; /*!< Specifies the WWDT window value to be compared to the downcounter. - This parameter must be a number a minimum, 0x40 and a maximum, 0x7F */ - - uint32_t Counter; /*!< Specifies the WWDT free-running downcounter value. - This parameter must be a number between a minimum, 0x40 and a maximum, 0x7F */ - - uint32_t EWIMode ; /*!< Specifies if WWDT Early Wakeup Interupt is enable or not. - This parameter can be a value of @ref WWDT_EWI_Mode */ - -} md_wwdt_inittypedef; -/** - * @} MD_WWDT_PT_INIT - */ - -/* Public constants -----------------------------------------------------------*/ -/** @defgroup MD_WWDT_PUBLIC_CONSTANTS WWDT Public Constants - * @{ - */ - -/** @defgroup MD_WWDT_Prescaler WWDT Prescaler - * @{ - */ -#define WWDT_PRESCALER_1 0x00000000U /*!< WWDT counter clock = (PCLK1/4096)/1 */ -#define WWDT_PRESCALER_2 1U<CON, Reg_Value); -} - -/** - * @brief Get the WWDT_CON value - * @note None. - * @param WWD WWDT Instance - * @retval a 32-bit value - */ -__STATIC_INLINE uint32_t md_wwdt_get_con(WWDT_TypeDef *WWD) -{ - return (uint32_t) (READ_REG(WWD->CON)); -} - -/** - * @brief WWDT WDG Enable - * @note This bit is set by software and only cleared by hardware after a reset. - * A write of 0 has no effect. When WDGA=1, the watchdog can generate a reset. - * @param WWD WWDT Instance - * @retval None - */ -__STATIC_INLINE void md_wwdt_enable_con_wdga(WWDT_TypeDef *WWD) -{ - SET_BIT(WWD->CON, WWDT_CON_WDGA_MSK); -} - -/** - * @brief Indicate if WWDT WDG is enabled - * @note This bit is set by software and only cleared by hardware after a reset. - * A write of 0 has no effect. When WDGA=1, the watchdog can generate a reset. - * @param WWD WWDT Instance - * @retval State of bit (1 or 0). - */ -__STATIC_INLINE uint32_t md_wwdt_is_enabled_wdga(WWDT_TypeDef *WWD) -{ - return (uint32_t)(READ_BIT(WWD->CON, WWDT_CON_WDGA_MSK) == (WWDT_CON_WDGA_MSK)); -} - -/** - * @brief Set WWDT T 7-bit counter - * @note These bits contain the value of the watchdog counter. - * It is decremented every (4096 x 2^WDGTB[1:0]) PCLK cycles. - * A reset is produced when it is decremented from 0x40 to 0x3F(T6 becomes cleared), - * and when it is renewed on the condition the value is more than the window value and the WDGA bit is enabled. - * @param WWD WWDT Instance - * @param counter is a 7-bit number - * @arg Max Value 0x7F - * @arg Min Value 0x40 - * @retval None - */ -__STATIC_INLINE void md_wwdt_set_con_t(WWDT_TypeDef *WWD, uint32_t counter) -{ - MODIFY_REG(WWD->CON, WWDT_CON_T_MSK, counter); -} - -/** - * @brief Get WWDT T 7-bit counter - * @note These bits contain the value of the watchdog counter. - * It is decremented every (4096 x 2^WDGTB[1:0]) PCLK cycles. - * A reset is produced when it is decremented from 0x40 to 0x3F(T6 becomes cleared), - * and when it is renewed on the condition the value is more than the window value and the WDGA bit is enabled. - * @param WWD WWDT Instance - * @retval The retval can be a value of the area: - * @arg Max Value 0x7F - * @arg Min Value 0x40 - */ -__STATIC_INLINE uint32_t md_wwdt_get_con_t(WWDT_TypeDef *WWD) -{ - return (READ_BIT(WWD->CON, WWDT_CON_T_MSK)>>WWDT_CON_T_POSS); -} - -/** - * @brief Set the WWDT_CFG value - * @note None. - * @param WWD WWDT Instance - * @param Reg_Value is a 32-bit value - * @retval None - */ -__STATIC_INLINE void md_wwdt_set_cfg(WWDT_TypeDef *WWD, uint32_t Reg_Value) -{ - WRITE_REG(WWD->CFG, Reg_Value); -} - -/** - * @brief Get the WWDT_CFG value - * @note None. - * @param WWD WWDT Instance - * @retval a 32-bit value - */ -__STATIC_INLINE uint32_t md_wwdt_get_cfg(WWDT_TypeDef *WWD) -{ - return (uint32_t) (READ_REG(WWD->CFG)); -} - -/** - * @brief Set WWDT WDGTB 2-bit prescaler value - * @note The time base of the prescaler can be modified as follows: - * 00: CK Counter Clock (PCLK div 4096) div 1 - * 01: CK Counter Clock (PCLK div 4096) div 2 - * 10: CK Counter Clock (PCLK div 4096) div 4 - * 11: CK Counter Clock (PCLK div 4096) div 8 - * @param WWD WWDT Instance - * @param prescaler is a 2-bit number - * @arg @ref WWDT_PRESCALER_1 - * @arg @ref WWDT_PRESCALER_2 - * @arg @ref WWDT_PRESCALER_4 - * @arg @ref WWDT_PRESCALER_8 - * @retval None - */ -__STATIC_INLINE void md_wwdt_set_cfg_wdgtb(WWDT_TypeDef *WWD, uint32_t prescaler) -{ - MODIFY_REG(WWD->CFG, WWDT_CFG_WDGTB_MSK, prescaler); -} - -/** - * @brief Get WWDT WDGTB 2-bit prescaler value - * @note The time base of the prescaler can be modified as follows: - 00: CK Counter Clock (PCLK div 4096) div 1 - 01: CK Counter Clock (PCLK div 4096) div 2 - 10: CK Counter Clock (PCLK div 4096) div 4 - 11: CK Counter Clock (PCLK div 4096) div 8 - * @param WWD WWDT Instance - * @retval The retval can be one of the following values: - * @arg @ref WWDT_PRESCALER_1 - * @arg @ref WWDT_PRESCALER_2 - * @arg @ref WWDT_PRESCALER_4 - * @arg @ref WWDT_PRESCALER_8 - */ -__STATIC_INLINE uint32_t md_wwdt_get_cfg_wdgtb(WWDT_TypeDef *WWD) -{ - return (READ_BIT(WWD->CFG, WWDT_CFG_WDGTB_MSK)>>WWDT_CFG_WDGTB_POSS); -} - -/** - * @brief Set WWDT W 7-bit window - * @note These bits contain the window value to be compared to the downcounter. - * @param WWD WWDT Instance - * @param window is a 7-bit number - * @arg Max Value 0x7F - * @arg Min Value 0x40 - * @retval None - */ -__STATIC_INLINE void md_wwdt_set_cfg_w(WWDT_TypeDef *WWD, uint32_t window) -{ - MODIFY_REG(WWD->CFG, WWDT_CFG_W_MSK, window); -} - -/** - * @brief Get WWDT W 7-bit window - * @note These bits contain the window value to be compared to the downcounter. - * @param WWD WWDT Instance - * @retval The retval can be a value of the area: - * @arg Max Value 0x7F - * @arg Min Value 0x40 - */ -__STATIC_INLINE uint32_t md_wwdt_get_cfg_w(WWDT_TypeDef *WWD) -{ - return (READ_BIT(WWD->CFG, WWDT_CFG_W_MSK)>>WWDT_CFG_W_POSS); -} - -/** - * @brief WWDT Early wakeup interrupt Enable - * @note A write of 1 in IER to enable this interrupt. - * @param WWD WWDT Instance - * @retval None - */ -__STATIC_INLINE void md_wwdt_enable_ier_ewis(WWDT_TypeDef *WWD) -{ - SET_BIT(WWD->IER, WWDT_IER_EWIS_MSK); -} - -/** - * @brief WWDT Early wakeup interrupt Disable - * @note A write of 1 in IDR to disable this interrupt. - * @param WWD WWDT Instance - * @retval None - */ -__STATIC_INLINE void md_wwdt_disable_idr_ewis(WWDT_TypeDef *WWD) -{ - SET_BIT(WWD->IDR, WWDT_IDR_EWIS_MSK); -} - -/** - * @brief Indicate if WWDT EWI is enabled - * @note To check EWI enable or not. - * @param WWD WWDT Instance - * @retval State of bit (1 or 0). - */ -__STATIC_INLINE uint32_t md_wwdt_is_enabled_ivs_ewis(WWDT_TypeDef *WWD) -{ - return (uint32_t) (READ_BIT(WWD->IVS, WWDT_IVS_EWIS_MSK) == (WWDT_IVS_EWIS_MSK)); -} - -/** - * @brief Get the early wakeup interrupt flag status - * @note This bit is set by hardware when the counter has reached the value 0x40. - It can be cleared by software by writing 1 in WWDT_ICR. This bit is - also set if the interrupt is not enabled. - * @param WWD WWDT Instance - * @retval State of bit (1 or 0). - */ -__STATIC_INLINE uint32_t md_wwdt_is_active_rif_ewif(WWDT_TypeDef *WWD) -{ - return (uint32_t) (READ_BIT(WWD->RIF, WWDT_RIF_EWIF_MSK) == (WWDT_RIF_EWIF_MSK)); -} - -/** - * @brief Get the early wakeup interrupt flag masked status - * @note This bit is set by hardware when the counter has reached the value 0x40 - and the interrupt is enabled. - * @param WWD WWDT Instance - * @retval State of bit (1 or 0). - */ -__STATIC_INLINE uint32_t md_wwdt_is_active_ifm_ewim(WWDT_TypeDef *WWD) -{ - return (uint32_t) (READ_BIT(WWD->IFM, WWDT_IFM_EWIM_MSK) == (WWDT_IFM_EWIM_MSK)); -} - -/** - * @brief Clear the early wakeup interrupt flag - * @param WWD WWDT Instance - * @retval None - */ -__STATIC_INLINE void md_wwdt_clear_icr_ewic(WWDT_TypeDef *WWD) -{ - SET_BIT(WWD->ICR, WWDT_ICR_EWIC_MSK); -} - -/** - * @} MD_WWDT_Public_Macros - */ - -/** @defgroup MD_WWDT_PF_Init WWDT Init Function - * @{ - */ -void md_wwdt_init(WWDT_TypeDef *WWD, md_wwdt_inittypedef *WWDT_InitStruct); -/** - * @} MD_WWDT_PF_Init - */ - -#endif - -/* Private macros ------------------------------------------------------------*/ - -/** @defgroup MD_WWDT_Private_Macros WWDG Private Macros - * @{ - */ -#define IS_MD_WWDT_ALL_INSTANCE(__INSTANCE__) (__INSTANCE__ == WWDT) - -#define IS_MD_WWDT_PRESCALER(__VALUE__) (((__VALUE__) == WWDT_PRESCALER_1) \ - || ((__VALUE__) == WWDT_PRESCALER_2) \ - || ((__VALUE__) == WWDT_PRESCALER_4) \ - || ((__VALUE__) == WWDT_PRESCALER_8)) - -#define IS_MD_WWDT_WINDOW(__VALUE__) (((__VALUE__) >= 0x40) && ((__VALUE__) <= 0x7F)) - -#define IS_MD_WWDT_COUNTER(__VALUE__) (((__VALUE__) >= 0x40) && ((__VALUE__) <= 0x7F)) - -#define IS_MD_WWDT_EWI_MODE(__VALUE__) (((__VALUE__) == WWDT_EWI_ENABLE) \ - || ((__VALUE__) == WWDT_EWI_DISABLE)) -/** - * @} MD_WWDT_Private_Macros - */ - -/** - * @} WWDT - */ -/** - * @} Micro_Driver - */ - -#ifdef __cplusplus -} -#endif - -#endif - -/******************* (C) COPYRIGHT Eastsoft Microelectronics *****END OF FILE****/ diff --git a/bsp/essemi/es32f0271/libraries/ES32F027x_MD_StdPeriph_Driver/Include/usb_lowlayer_api.h b/bsp/essemi/es32f0271/libraries/ES32F027x_MD_StdPeriph_Driver/Include/usb_lowlayer_api.h deleted file mode 100644 index 5fee2e973e..0000000000 --- a/bsp/essemi/es32f0271/libraries/ES32F027x_MD_StdPeriph_Driver/Include/usb_lowlayer_api.h +++ /dev/null @@ -1,728 +0,0 @@ -/** - ************************************************************************************** - * @file usb_lowlayer_api.h - * @brief USB library lower layer api - * @data 11/9/2018 - * @author Eastsoft AE Team - * @note - * - * Copyright (C) 2018 Shanghai Eastsoft Microelectronics Co., Ltd. ALL rights reserved. - * - ************************************************************************************** - */ - -/* Includes-------------------------------------------------------------------*/ -#include "stdint.h" -#include - -#ifndef __USB_LOWLAYER_API_H__ -#define __USB_LOWLAYER_API_H__ - - -/** - * If building with a C++ compiler, make all of the definitions in this header - * have a C binding. - */ -#ifdef __cplusplus -extern "C" -{ -#endif - -/* Public constants -----------------------------------------------------------*/ - -//***************************************************************************** -// -// The following are values that can be passed to md_usb_hosdev_int_enable() and -// md_usb_hosdev_int_disable() as the ui32Flags parameter, and are returned from -// md_usb_hosdev_int_status(). -// -//***************************************************************************** -#define USB_INTCTRL_ALL 0x000003FF // All control interrupt sources -#define USB_INTCTRL_STATUS 0x000000FF // Status Interrupts -#define USB_INTCTRL_VBUS_ERR 0x00000080 // VBUS Error -#define USB_INTCTRL_SESSION 0x00000040 // Session Start Detected -#define USB_INTCTRL_SESSION_END 0x00000040 // Session End Detected -#define USB_INTCTRL_DISCONNECT 0x00000020 // Disconnect Detected -#define USB_INTCTRL_CONNECT 0x00000010 // Device Connect Detected -#define USB_INTCTRL_SOF 0x00000008 // Start of Frame Detected -#define USB_INTCTRL_BABBLE 0x00000004 // Babble signaled -#define USB_INTCTRL_RESET 0x00000004 // Reset signaled -#define USB_INTCTRL_RESUME 0x00000002 // Resume detected -#define USB_INTCTRL_SUSPEND 0x00000001 // Suspend detected -#define USB_INTCTRL_MODE_DETECT 0x00000200 // Mode value valid -#define USB_INTCTRL_POWER_FAULT 0x00000100 // Power Fault detected - -//***************************************************************************** -// -// The following are values that can be passed to md_usb_hosdev_endpoint_int_enable() -// and md_usb_hosdev_endpoint_int_disable() as the ui32Flags parameter, and -// are returned from md_usb_hosdev_endpoint_int_status(). -// -//***************************************************************************** -#define USB_INTEP_ALL 0xFFFFFFFF // Host IN Interrupts -#define USB_INTEP_HOST_IN 0xFFFE0000 // Host IN Interrupts -#define USB_INTEP_HOST_IN_15 0x80000000 // Endpoint 15 Host IN Interrupt -#define USB_INTEP_HOST_IN_14 0x40000000 // Endpoint 14 Host IN Interrupt -#define USB_INTEP_HOST_IN_13 0x20000000 // Endpoint 13 Host IN Interrupt -#define USB_INTEP_HOST_IN_12 0x10000000 // Endpoint 12 Host IN Interrupt -#define USB_INTEP_HOST_IN_11 0x08000000 // Endpoint 11 Host IN Interrupt -#define USB_INTEP_HOST_IN_10 0x04000000 // Endpoint 10 Host IN Interrupt -#define USB_INTEP_HOST_IN_9 0x02000000 // Endpoint 9 Host IN Interrupt -#define USB_INTEP_HOST_IN_8 0x01000000 // Endpoint 8 Host IN Interrupt -#define USB_INTEP_HOST_IN_7 0x00800000 // Endpoint 7 Host IN Interrupt -#define USB_INTEP_HOST_IN_6 0x00400000 // Endpoint 6 Host IN Interrupt -#define USB_INTEP_HOST_IN_5 0x00200000 // Endpoint 5 Host IN Interrupt -#define USB_INTEP_HOST_IN_4 0x00100000 // Endpoint 4 Host IN Interrupt -#define USB_INTEP_HOST_IN_3 0x00080000 // Endpoint 3 Host IN Interrupt -#define USB_INTEP_HOST_IN_2 0x00040000 // Endpoint 2 Host IN Interrupt -#define USB_INTEP_HOST_IN_1 0x00020000 // Endpoint 1 Host IN Interrupt - -#define USB_INTEP_DEV_OUT 0xFFFE0000 // Device OUT Interrupts -#define USB_INTEP_DEV_OUT_15 0x80000000 // Endpoint 15 Device OUT Interrupt -#define USB_INTEP_DEV_OUT_14 0x40000000 // Endpoint 14 Device OUT Interrupt -#define USB_INTEP_DEV_OUT_13 0x20000000 // Endpoint 13 Device OUT Interrupt -#define USB_INTEP_DEV_OUT_12 0x10000000 // Endpoint 12 Device OUT Interrupt -#define USB_INTEP_DEV_OUT_11 0x08000000 // Endpoint 11 Device OUT Interrupt -#define USB_INTEP_DEV_OUT_10 0x04000000 // Endpoint 10 Device OUT Interrupt -#define USB_INTEP_DEV_OUT_9 0x02000000 // Endpoint 9 Device OUT Interrupt -#define USB_INTEP_DEV_OUT_8 0x01000000 // Endpoint 8 Device OUT Interrupt -#define USB_INTEP_DEV_OUT_7 0x00800000 // Endpoint 7 Device OUT Interrupt -#define USB_INTEP_DEV_OUT_6 0x00400000 // Endpoint 6 Device OUT Interrupt -#define USB_INTEP_DEV_OUT_5 0x00200000 // Endpoint 5 Device OUT Interrupt -#define USB_INTEP_DEV_OUT_4 0x00100000 // Endpoint 4 Device OUT Interrupt -#define USB_INTEP_DEV_OUT_3 0x00080000 // Endpoint 3 Device OUT Interrupt -#define USB_INTEP_DEV_OUT_2 0x00040000 // Endpoint 2 Device OUT Interrupt -#define USB_INTEP_DEV_OUT_1 0x00020000 // Endpoint 1 Device OUT Interrupt - -#define USB_INTEP_HOST_OUT 0x0000FFFE // Host OUT Interrupts -#define USB_INTEP_HOST_OUT_15 0x00008000 // Endpoint 15 Host OUT Interrupt -#define USB_INTEP_HOST_OUT_14 0x00004000 // Endpoint 14 Host OUT Interrupt -#define USB_INTEP_HOST_OUT_13 0x00002000 // Endpoint 13 Host OUT Interrupt -#define USB_INTEP_HOST_OUT_12 0x00001000 // Endpoint 12 Host OUT Interrupt -#define USB_INTEP_HOST_OUT_11 0x00000800 // Endpoint 11 Host OUT Interrupt -#define USB_INTEP_HOST_OUT_10 0x00000400 // Endpoint 10 Host OUT Interrupt -#define USB_INTEP_HOST_OUT_9 0x00000200 // Endpoint 9 Host OUT Interrupt -#define USB_INTEP_HOST_OUT_8 0x00000100 // Endpoint 8 Host OUT Interrupt -#define USB_INTEP_HOST_OUT_7 0x00000080 // Endpoint 7 Host OUT Interrupt -#define USB_INTEP_HOST_OUT_6 0x00000040 // Endpoint 6 Host OUT Interrupt -#define USB_INTEP_HOST_OUT_5 0x00000020 // Endpoint 5 Host OUT Interrupt -#define USB_INTEP_HOST_OUT_4 0x00000010 // Endpoint 4 Host OUT Interrupt -#define USB_INTEP_HOST_OUT_3 0x00000008 // Endpoint 3 Host OUT Interrupt -#define USB_INTEP_HOST_OUT_2 0x00000004 // Endpoint 2 Host OUT Interrupt -#define USB_INTEP_HOST_OUT_1 0x00000002 // Endpoint 1 Host OUT Interrupt - -#define USB_INTEP_DEV_IN 0x0000FFFE // Device IN Interrupts -#define USB_INTEP_DEV_IN_15 0x00008000 // Endpoint 15 Device IN Interrupt -#define USB_INTEP_DEV_IN_14 0x00004000 // Endpoint 14 Device IN Interrupt -#define USB_INTEP_DEV_IN_13 0x00002000 // Endpoint 13 Device IN Interrupt -#define USB_INTEP_DEV_IN_12 0x00001000 // Endpoint 12 Device IN Interrupt -#define USB_INTEP_DEV_IN_11 0x00000800 // Endpoint 11 Device IN Interrupt -#define USB_INTEP_DEV_IN_10 0x00000400 // Endpoint 10 Device IN Interrupt -#define USB_INTEP_DEV_IN_9 0x00000200 // Endpoint 9 Device IN Interrupt -#define USB_INTEP_DEV_IN_8 0x00000100 // Endpoint 8 Device IN Interrupt -#define USB_INTEP_DEV_IN_7 0x00000080 // Endpoint 7 Device IN Interrupt -#define USB_INTEP_DEV_IN_6 0x00000040 // Endpoint 6 Device IN Interrupt -#define USB_INTEP_DEV_IN_5 0x00000020 // Endpoint 5 Device IN Interrupt -#define USB_INTEP_DEV_IN_4 0x00000010 // Endpoint 4 Device IN Interrupt -#define USB_INTEP_DEV_IN_3 0x00000008 // Endpoint 3 Device IN Interrupt -#define USB_INTEP_DEV_IN_2 0x00000004 // Endpoint 2 Device IN Interrupt -#define USB_INTEP_DEV_IN_1 0x00000002 // Endpoint 1 Device IN Interrupt - -#define USB_INTEP_0 0x00000001 // Endpoint 0 Interrupt - -//***************************************************************************** -// -// The following are values that are returned from md_usb_hos_speed_get() 0r -// md_usb_dev_speed_get(). -// -//***************************************************************************** -#define USB_UNDEF_SPEED 0x80000000 // Current speed is undefined -#define USB_HIGH_SPEED 0x00000002 // Current speed is High Speed -#define USB_FULL_SPEED 0x00000001 // Current speed is Full Speed -#define USB_LOW_SPEED 0x00000000 // Current speed is Low Speed - -//***************************************************************************** -// -// The following are values that are returned from md_usb_hosdev_endpoint_status(). The -// USB_HOST_* values are used when the USB controller is in host mode and the -// USB_DEV_* values are used when the USB controller is in device mode. -// -//***************************************************************************** -#define USB_HOST_IN_STATUS 0x114F0000 // Mask of all host IN interrupts -#define USB_HOST_IN_PID_ERROR 0x10000000 // Stall on this endpoint received -#define USB_HOST_IN_NOT_COMP 0x01000000 // Device failed to respond -#define USB_HOST_IN_STALL 0x00400000 // Stall on this endpoint received -#define USB_HOST_IN_DATA_ERROR 0x00080000 // CRC or bit-stuff error -// (ISOC Mode) -#define USB_HOST_IN_NAK_TO 0x00080000 // NAK received for more than the -// specified timeout period -#define USB_HOST_IN_ERROR 0x00040000 // Failed to communicate with a -// device -#define USB_HOST_IN_FIFO_FULL 0x00020000 // RX FIFO full -#define USB_HOST_IN_PKTRDY 0x00010000 // Data packet ready -#define USB_HOST_OUT_STATUS 0x000000A7 // Mask of all host OUT interrupts -#define USB_HOST_OUT_NAK_TO 0x00000080 // NAK received for more than the -// specified timeout period -#define USB_HOST_OUT_NOT_COMP 0x00000080 // No response from device -// (ISOC mode) -#define USB_HOST_OUT_STALL 0x00000020 // Stall on this endpoint received -#define USB_HOST_OUT_ERROR 0x00000004 // Failed to communicate with a -// device -#define USB_HOST_OUT_FIFO_NE 0x00000002 // TX FIFO is not empty -#define USB_HOST_OUT_PKTPEND 0x00000001 // Transmit still being transmitted -#define USB_HOST_EP0_NAK_TO 0x00000080 // NAK received for more than the -// specified timeout period -#define USB_HOST_EP0_STATUS 0x00000040 // This was a status packet -#define USB_HOST_EP0_ERROR 0x00000010 // Failed to communicate with a -// device -#define USB_HOST_EP0_RX_STALL 0x00000004 // Stall on this endpoint received -#define USB_HOST_EP0_RXPKTRDY 0x00000001 // Receive data packet ready -#define USB_DEV_RX_PID_ERROR 0x01000000 // PID error in isochronous -// transfer -#define USB_DEV_RX_SENT_STALL 0x00400000 // Stall was sent on this endpoint -#define USB_DEV_RX_DATA_ERROR 0x00080000 // CRC error on the data -#define USB_DEV_RX_OVERRUN 0x00040000 // OUT packet was not loaded due to -// a full FIFO -#define USB_DEV_RX_FIFO_FULL 0x00020000 // RX FIFO full -#define USB_DEV_RX_PKT_RDY 0x00010000 // Data packet ready -#define USB_DEV_TX_NOT_COMP 0x00000080 // Large packet split up, more data -// to come -#define USB_DEV_TX_SENT_STALL 0x00000020 // Stall was sent on this endpoint -#define USB_DEV_TX_UNDERRUN 0x00000004 // IN received with no data ready -#define USB_DEV_TX_FIFO_NE 0x00000002 // The TX FIFO is not empty -#define USB_DEV_TX_TXPKTRDY 0x00000001 // Transmit still being transmitted -#define USB_DEV_EP0_SETUP_END 0x00000010 // Control transaction ended before -// Data End seen -#define USB_DEV_EP0_SENT_STALL 0x00000004 // Stall was sent on this endpoint -#define USB_DEV_EP0_IN_PKTPEND 0x00000002 // Transmit data packet pending -#define USB_DEV_EP0_OUT_PKTRDY 0x00000001 // Receive data packet ready - -//***************************************************************************** -// -// The following are values that can be passed to md_usb_hos_endpoint_config_set() and -// md_usb_dev_endpoint_config_set() as the ui32Flags parameter. -// -//***************************************************************************** -#define USB_EP_AUTO_SET 0x00000001 // Auto set feature enabled -#define USB_EP_AUTO_REQUEST 0x00000002 // Auto request feature enabled -#define USB_EP_AUTO_CLEAR 0x00000004 // Auto clear feature enabled -#define USB_EP_DUAL_BUFFERING 0x00000008 // Dual buffering enabled -#define USB_EP_DMA_MODE_0 0x00000008 // Enable DMA access using mode 0 -#define USB_EP_DMA_MODE_1 0x00000010 // Enable DMA access using mode 1 -#define USB_EP_DIS_NYET 0x00000020 // Disable NYET response for -// high-speed Bulk and Interrupt -// endpoints in device mode. -#define USB_EP_MODE_ISOC 0x00000000 // Isochronous endpoint -#define USB_EP_MODE_BULK 0x00000100 // Bulk endpoint -#define USB_EP_MODE_INT 0x00000200 // Interrupt endpoint -#define USB_EP_MODE_CTRL 0x00000300 // Control endpoint -#define USB_EP_MODE_MASK 0x00000300 // Mode Mask -#define USB_EP_SPEED_LOW 0x00000000 // Low Speed -#define USB_EP_SPEED_FULL 0x00001000 // Full Speed -#define USB_EP_SPEED_HIGH 0x00004000 // High Speed -#define USB_EP_HOST_IN 0x00000000 // Host IN endpoint -#define USB_EP_HOST_OUT 0x00002000 // Host OUT endpoint -#define USB_EP_DEV_IN 0x00002000 // Device IN endpoint -#define USB_EP_DEV_OUT 0x00000000 // Device OUT endpoint - -//***************************************************************************** -// -// The following are values that can be passed to md_usb_hos_pwr_config() as the -// ui32Flags parameter. -// -//***************************************************************************** -#define USB_HOST_PWRFLT_LOW 0x00000010 -#define USB_HOST_PWRFLT_HIGH 0x00000030 -#define USB_HOST_PWRFLT_EP_NONE 0x00000000 -#define USB_HOST_PWRFLT_EP_TRI 0x00000140 -#define USB_HOST_PWRFLT_EP_LOW 0x00000240 -#define USB_HOST_PWRFLT_EP_HIGH 0x00000340 -#define USB_HOST_PWREN_MAN_LOW 0x00000000 -#define USB_HOST_PWREN_MAN_HIGH 0x00000001 -#define USB_HOST_PWREN_AUTOLOW 0x00000002 -#define USB_HOST_PWREN_AUTOHIGH 0x00000003 -#define USB_HOST_PWREN_FILTER 0x00010000 - -//***************************************************************************** -// -// The following are the valid values that can be passed to the -// md_usb_hos_lpm_config() function in the ui32Config parameter. -// -//***************************************************************************** -#define USB_HOST_LPM_RMTWAKE 0x00000100 -#define USB_HOST_LPM_L1 0x00000001 - -//***************************************************************************** -// -// The following are the valid values that can be passed to the -// md_usb_dev_lpm_config() function in the ui32Config parameter. -// -//***************************************************************************** -#define USB_DEV_LPM_NAK 0x00000010 -#define USB_DEV_LPM_NONE 0x00000000 -#define USB_DEV_LPM_EN 0x0000000c -#define USB_DEV_LPM_EXTONLY 0x00000004 - -//***************************************************************************** -// -// The following are the valid values that are returned from the -// md_usb_lpm_link_state_get() function. -// -//***************************************************************************** -#define USB_DEV_LPM_LS_RMTWAKE 0x00000100 -#define USB_DEV_LPM_LS_L1 0x00000001 - -//***************************************************************************** -// -// The following are the valid values that are passed to the md_usb_lpm_int_enable() -// or md_usb_lpm_int_disable() functions or are returned from the md_usb_lpm_status() -// function. -// -//***************************************************************************** -#define USB_INTLPM_ERROR 0x00000020 -#define USB_INTLPM_RESUME 0x00000010 -#define USB_INTLPM_INCOMPLETE 0x00000008 -#define USB_INTLPM_ACK 0x00000004 -#define USB_INTLPM_NYET 0x00000002 -#define USB_INTLPM_STALL 0x00000001 - -//***************************************************************************** -// -// The following are the valid values that are passed to the md_usb_clock_enable() -// functions. -// -//***************************************************************************** -#define USB_CLOCK_INTERNAL 0x00000200 -#define USB_CLOCK_EXTERNAL 0x00000300 - -//***************************************************************************** -// -// The configuration options used with the md_usb_ulpi_config() API. -// -//***************************************************************************** -#define USB_ULPI_EXTVBUS 0x00000001 -#define USB_ULPI_EXTVBUS_IND 0x00000002 - -//***************************************************************************** -// -// The following are special values that can be passed to -// md_usb_hos_endpoint_config_set() as the ui32NAKPollInterval parameter. -// -//***************************************************************************** -#define MAX_NAK_LIMIT 31 // Maximum NAK interval -#define DISABLE_NAK_LIMIT 0 // No NAK timeouts - -//***************************************************************************** -// -// This value specifies the maximum size of transfers on endpoint 0 as 64 -// bytes. This value is fixed in hardware as the FIFO size for endpoint 0. -// -//***************************************************************************** -#define MAX_PACKET_SIZE_EP0 64 - -//***************************************************************************** -// -// These values are used to indicate which endpoint to access. -// -//***************************************************************************** -#define USB_EP_0 0x00000000 // Endpoint 0 -#define USB_EP_1 0x00000010 // Endpoint 1 -#define USB_EP_2 0x00000020 // Endpoint 2 -#define USB_EP_3 0x00000030 // Endpoint 3 -#define USB_EP_4 0x00000040 // Endpoint 4 -#define USB_EP_5 0x00000050 // Endpoint 5 -#define USB_EP_6 0x00000060 // Endpoint 6 -#define USB_EP_7 0x00000070 // Endpoint 7 -#define NUM_USB_EP 8 // Number of supported endpoints - -//***************************************************************************** -// -// These macros allow conversion between 0-based endpoint indices and the -// USB_EP_x values required when calling various USB APIs. -// -//***************************************************************************** -#define IndexToUSBEP(x) ((x) << 4) -#define USBEPToIndex(x) ((x) >> 4) - -//***************************************************************************** -// -// The following are values that can be passed to md_usb_hosdev_fifo_config_set() as the -// ui32FIFOSize parameter. -// -//***************************************************************************** -#define USB_FIFO_SZ_8 0x00000000 // 8 byte FIFO -#define USB_FIFO_SZ_16 0x00000001 // 16 byte FIFO -#define USB_FIFO_SZ_32 0x00000002 // 32 byte FIFO -#define USB_FIFO_SZ_64 0x00000003 // 64 byte FIFO -#define USB_FIFO_SZ_128 0x00000004 // 128 byte FIFO -#define USB_FIFO_SZ_256 0x00000005 // 256 byte FIFO -#define USB_FIFO_SZ_512 0x00000006 // 512 byte FIFO -#define USB_FIFO_SZ_1024 0x00000007 // 1024 byte FIFO -#define USB_FIFO_SZ_2048 0x00000008 // 2048 byte FIFO - -//***************************************************************************** -// -// This macro allow conversion from a FIFO size label as defined above to -// a number of bytes -// -//***************************************************************************** -#define USBFIFOSizeToBytes(x) (8 << (x)) - -//***************************************************************************** -// -// The following are values that can be passed to md_usb_hosdev_endpoint_data_send() -// as the ui32TransType parameter. -// -//***************************************************************************** -#define USB_TRANS_OUT 0x00000102 // Normal OUT transaction -#define USB_TRANS_IN 0x00000102 // Normal IN transaction -#define USB_TRANS_IN_LAST 0x0000010a // Final IN transaction (for -// endpoint 0 in device mode) -#define USB_TRANS_SETUP 0x0000110a // Setup transaction (for endpoint -// 0) -#define USB_TRANS_STATUS 0x00000142 // Status transaction (for endpoint -// 0) - -//***************************************************************************** -// -// The following are values are returned by the md_usb_hosdev_mode_get() function. -// -//***************************************************************************** -#define USB_DUAL_MODE_HOST 0x00000001 // Dual mode controller is in Host -// mode. -#define USB_DUAL_MODE_DEVICE 0x00000081 // Dual mode controller is in -// Device mode. -#define USB_DUAL_MODE_NONE 0x00000080 // Dual mode controller mode is not -// set. -#define USB_OTG_MODE_ASIDE_HOST 0x0000001d // OTG controller on the A side of -// the cable. -#define USB_OTG_MODE_ASIDE_NPWR 0x00000001 // OTG controller on the A side of -// the cable. -#define USB_OTG_MODE_ASIDE_SESS 0x00000009 // OTG controller on the A side of -// the cable Session Valid. -#define USB_OTG_MODE_ASIDE_AVAL 0x00000011 // OTG controller on the A side of -// the cable A valid. -#define USB_OTG_MODE_ASIDE_DEV 0x00000019 // OTG controller on the A side of -// the cable. -#define USB_OTG_MODE_BSIDE_HOST 0x0000009d // OTG controller on the B side of -// the cable. -#define USB_OTG_MODE_BSIDE_DEV 0x00000099 // OTG controller on the B side of -// the cable. -#define USB_OTG_MODE_BSIDE_NPWR 0x00000081 // OTG controller on the B side of -// the cable. -#define USB_OTG_MODE_NONE 0x00000080 // OTG controller mode is not set. - -//***************************************************************************** -// -// Channel configuration values. -// -//***************************************************************************** -#define DMA_DST_INC_8 0x00000000 -#define DMA_DST_INC_16 0x40000000 -#define DMA_DST_INC_32 0x80000000 -#define DMA_DST_INC_NONE 0xc0000000 -#define DMA_SRC_INC_8 0x00000000 -#define DMA_SRC_INC_16 0x04000000 -#define DMA_SRC_INC_32 0x08000000 -#define DMA_SRC_INC_NONE 0x0c000000 -#define DMA_SIZE_8 0x00000000 -#define DMA_SIZE_16 0x11000000 -#define DMA_SIZE_32 0x22000000 -#define DMA_DST_PROT_PRIV 0x00200000 -#define DMA_SRC_PROT_PRIV 0x00040000 -#define DMA_ARB_1 0x00000000 -#define DMA_ARB_2 0x00004000 -#define DMA_ARB_4 0x00008000 -#define DMA_ARB_8 0x0000c000 -#define DMA_ARB_16 0x00010000 -#define DMA_ARB_32 0x00014000 -#define DMA_ARB_64 0x00018000 -#define DMA_ARB_128 0x0001c000 -#define DMA_ARB_256 0x00020000 -#define DMA_ARB_512 0x00024000 -#define DMA_ARB_1024 0x00028000 -#define DMA_NEXT_USEBURST 0x00000008 - -//***************************************************************************** -// -// The values for the md_usb_dma_channel_int_enable() and md_usb_dma_channel_int_status() -// APIs. -// -//***************************************************************************** -#define USB_DMA_INT_CH8 0x00000080 -#define USB_DMA_INT_CH7 0x00000040 -#define USB_DMA_INT_CH6 0x00000020 -#define USB_DMA_INT_CH5 0x00000010 -#define USB_DMA_INT_CH4 0x00000008 -#define USB_DMA_INT_CH3 0x00000004 -#define USB_DMA_INT_CH2 0x00000002 -#define USB_DMA_INT_CH1 0x00000001 - -//***************************************************************************** -// -// The values for the md_usb_dma_channel_status() API. -// -//***************************************************************************** -#define USB_DMA_STATUS_ERROR 0x00000100 - -//***************************************************************************** -// -// The valid return values for the USBDMAModeSet() and USBDMAModeGet() APIs or -// USBDMAChannelConfig(). -// -//***************************************************************************** -#define USB_DMA_CFG_BURST_NONE 0x00000000 -#define USB_DMA_CFG_BURST_4 0x00000200 -#define USB_DMA_CFG_BURST_8 0x00000400 -#define USB_DMA_CFG_BURST_16 0x00000600 -#define USB_DMA_CFG_INT_EN 0x00000008 -#define USB_DMA_CFG_MODE_0 0x00000000 -#define USB_DMA_CFG_MODE_1 0x00000004 -#define USB_DMA_CFG_DIR_RX 0x00000000 -#define USB_DMA_CFG_DIR_TX 0x00000002 -#define USB_DMA_CFG_EN 0x00000001 - -//***************************************************************************** -// -// The following are values that can be passed to md_usb_mode_config() as the -// ui3Mode parameter. -// -//***************************************************************************** -#define USB_MODE_HOST_VBUS 0x00000004 -#define USB_MODE_HOST 0x00000002 -#define USB_MODE_DEV_VBUS 0x00000005 -#define USB_MODE_DEV 0x00000003 -#define USB_MODE_OTG 0x00000000 - -//***************************************************************************** -// -// Flags that can be passed to DMAChannelAttributeEnable(), -// DMAChannelAttributeDisable(), and returned from DMAChannelAttributeGet(). -// -//***************************************************************************** -#define DMA_ATTR_USEBURST 0x00000001 -#define DMA_ATTR_ALTSELECT 0x00000002 -#define DMA_ATTR_HIGH_PRIORITY 0x00000004 -#define DMA_ATTR_REQMASK 0x00000008 -#define DMA_ATTR_ALL 0x0000000F - -/* Public functions -----------------------------------------------------------*/ -/** - * @{ SYSTEM API. - */ -extern void md_usb_system_int_disable(void); -extern void md_usb_system_int_enable(void); -extern void md_usb_re_config(bool Device); /* Weak defination */ -extern void md_usb_system_delayms(uint32_t delayms); /* Weak defination */ -extern void md_usb_systic_disable(void); -extern void md_usb_controller_reset(void); -extern void md_usb_controller_enable(void); -extern void md_usb_controller_disable(void); -extern void md_usb_clk_phy_enable(void); -extern void md_usb_clk_phy_disable(void); -extern uint32_t md_usb_nvic_number_get(void); -extern void md_usb_nvic_config(uint32_t NvicNum); /* Weak defination */ -extern void md_usb_nvic_enable(void); -extern void md_usb_nvic_disable(void); -/** - * @} SYSTEM API. - */ - -/** - * @{ USB basic API. - */ -/* Host Mode */ -extern void md_usb_hos_reset(bool bStart); -extern void md_usb_hos_resume(bool bStart); -extern void md_usb_hos_suspend(void); -extern void md_usb_hos_request_status(void); -extern void md_usb_hos_request_in(uint32_t ui32Endpoint); -extern void md_usb_hos_request_in_clear(uint32_t ui32Endpoint); -extern uint32_t md_usb_hos_speed_get(void); -extern uint32_t md_usb_hos_addr_get(uint32_t ui32Endpoint, uint32_t ui32Flags); -extern void md_usb_hos_addr_set(uint32_t ui32Endpoint, - uint32_t ui32Addr, - uint32_t ui32Flags); -extern uint32_t md_usb_hos_hub_addr_get(uint32_t ui32Endpoint, - uint32_t ui32Flags); -extern void md_usb_hos_hub_addr_set(uint32_t ui32Endpoint, - uint32_t ui32Addr, - uint32_t ui32Flags); -/* Device Mode */ -extern void md_usb_dev_addr_set(uint8_t ui32Address); -extern uint8_t md_usb_dev_addr_get(void); -extern void md_usb_dev_connect(void); -extern void md_usb_dev_disconnect(void); -extern uint32_t md_usb_dev_speed_get(void); -/* Host/Device Mode */ -extern uint32_t md_usb_hosdev_frame_get(void); -extern void md_usb_hosdev_int_disable(uint32_t ui32IntFlags); -extern void md_usb_hosdev_int_enable(uint32_t ui32IntFlags); -extern uint32_t md_usb_hosdev_int_status(void); -extern uint32_t md_usb_hosdev_mode_get(void); -/* otg Mode */ -extern void md_usb_otg_session_request(bool bStart); -extern void md_usb_force_host_mode(void); -extern void md_usb_force_device_mode(void); -extern void md_usb_force_otg_mode(void); -extern void md_usb_mode_config(uint32_t ui32Mode); -/** - * @} USB basic API. - */ - -/** - * @{ USB endpoint API. - */ -/* Host Mode */ -extern void md_usb_hos_endpoint_config_set(uint32_t ui32Endpoint, - uint32_t ui32MaxPacketSize, - uint32_t ui32NAKPollInterval, - uint32_t ui32TargetEndpoint, - uint32_t ui32Flags); -extern void md_usb_hos_endpoint_data_ack(uint32_t ui32Endpoint); -extern void md_usb_hos_endpoint_data_toggle(uint32_t ui32Endpoint, - bool bDataToggle, - uint32_t ui32Flags); -extern void md_usb_hos_endpoint_status_clear(uint32_t ui32Endpoint, - uint32_t ui32Flags); -extern void md_usb_hos_endpoint_speed(uint32_t ui32Endpoint, - uint32_t ui32Flags); -extern void md_usb_hos_endpoint_ping(uint32_t ui32Endpoint, - bool bEnable); -/* Device Mode */ -extern void md_usb_dev_endpoint_config_set(uint32_t ui32Endpoint, - uint32_t ui32MaxPacketSize, - uint32_t ui32Flags); -extern void md_usb_dev_endpoint_config_get(uint32_t ui32Endpoint, - uint32_t *pui32MaxPacketSize, - uint32_t *pui32Flags); -extern void md_usb_dev_endpoint_ack(uint32_t ui32Endpoint, - bool bIsLastPacket); -extern void md_usb_dev_endpoint_stall(uint32_t ui32Endpoint, - uint32_t ui32Flags); -extern void md_usb_dev_endpoint_stall_clear(uint32_t ui32Endpoint, - uint32_t ui32Flags); -extern void md_usb_dev_endpoint_status_clear(uint32_t ui32Endpoint, - uint32_t ui32Flags); -/* Host/Device Mode */ -extern uint32_t md_usb_hosdev_endpoint_datavai(uint32_t ui32Endpoint); -extern int32_t md_usb_hosdev_endpoint_data_get(uint32_t ui32Endpoint, - uint8_t *pui8Data, uint32_t *pui32Size); -extern int32_t md_usb_hosdev_endpoint_data_put(uint32_t ui32Endpoint, - uint8_t *pui8Data, - uint32_t ui32Size); -extern int32_t md_usb_hosdev_endpoint_data_send(uint32_t ui32Endpoint, - uint32_t ui32TransType); -extern void md_usb_hosdev_endpoint_data_togglec(uint32_t ui32Endpoint, - uint32_t ui32Flags); -extern void md_usb_hosdev_endpoint_pkcount_set(uint32_t ui32Endpoint, - uint32_t ui32Count); -extern uint32_t md_usb_hosdev_endpoint_status(uint32_t ui32Endpoint); -extern void md_usb_hosdev_endpoint_int_disable(uint32_t ui32IntFlags); -extern void md_usb_hosdev_endpoint_int_enable(uint32_t ui32IntFlags); -extern uint32_t md_usb_hosdev_endpoint_int_status(void); -extern uint32_t md_usb_endpoint_number_get(void); -/** - * @} USB endpoint API. - */ - -/** - * @{ USB FIFO API. - */ -extern uint32_t md_usb_hosdev_fifo_addr_get(uint32_t ui32Endpoint); -extern void md_usb_hosdev_fifo_config_get(uint32_t ui32Endpoint, uint32_t *pui32FIFOAddress, - uint32_t *pui32FIFOSize, uint32_t ui32Flags); -extern void md_usb_hosdev_fifo_config_set(uint32_t ui32Endpoint, uint32_t ui32FIFOAddress, - uint32_t ui32FIFOSize, uint32_t ui32Flags); -extern void md_usb_hosdev_fifo_flush(uint32_t ui32Endpoint, uint32_t ui32Flags); -/** - * @} USB FIFO API. - */ - -/** - * @{ USB PWR API.it is not supported by es32f0271. - */ -extern void md_usb_hos_pwr_disable(void); -extern void md_usb_hos_pwr_enable(void); -extern void md_usb_hos_pwr_config(uint32_t ui32Flags); -extern void md_usb_hos_pwrfault_disable(void); -extern void md_usb_hos_pwrfault_enable(void); -/** - * @} USB PWR API. - */ - -/** - * @{ USB LPM API.it is not supported by es32f0271. - */ -extern void md_usb_hos_lpm_send(uint32_t ui32Address, - uint32_t uiEndpoint); -extern void md_usb_hos_lpm_config(uint32_t ui32ResumeTime, - uint32_t ui32Config); -extern bool md_usb_lpm_remotewake_is_enabled(void); -extern void md_usb_hos_lpm_resume(void); -extern void md_usb_dev_lpm_remotewake(void); -extern void md_usb_dev_lpm_config(uint32_t ui32Config); -extern void md_usb_dev_lpm_enable(void); -extern void md_usb_dev_lpm_disable(void); -extern uint32_t md_usb_lpm_link_state_get(void); -extern uint32_t md_usb_lpm_endpoint_get(void); -extern uint32_t md_usb_lpm_status(void); -extern void md_usb_lpm_int_disable(uint32_t ui32Ints); -extern void md_usb_lpm_int_enable(uint32_t ui32Ints); -/** - * @} USB LPM API. - */ - -/** - * @{ USB ULPI API.it is not supported by es32f0271. - */ -extern void md_usb_ulpi_config(uint32_t ui32Config); -extern void md_usb_ulpi_enable(void); -extern void md_usb_ulpi_disable(void); -extern uint8_t md_usb_ulpi_reg_read(uint8_t ui8Reg); -extern void md_usb_ulpi_reg_write(uint8_t ui8Reg, - uint8_t ui8Data); -/** - * @} USB ULPI API. - */ - -/** - * @{ USB DMA API.it is not supported by es32f0271. - */ -extern void md_usb_dma_endpoint_channel_set(uint32_t ui32Endpoint, - uint32_t ui32Channel); -extern void md_usb_dma_endpoint_enable(uint32_t ui32Endpoint, - uint32_t ui32Flags); -extern void md_usb_dma_endpoint_disable(uint32_t ui32Endpoint, - uint32_t ui32Flags); -extern void md_usb_dma_endpoint_config(uint32_t ui32Endpoint, - uint32_t ui32Config); -extern void md_usb_dma_channel_config(uint32_t ui32Channel, - uint32_t ui32Endpoint, - uint32_t ui32Config); -extern void md_usb_dma_channel_address_set(uint32_t ui32Channel, - void *pvAddress); -extern void *md_usb_dma_channel_address_get(uint32_t ui32Channel); -extern void md_usb_dma_channel_count_set(uint32_t ui32Count, - uint32_t ui32Channel); -extern uint32_t md_usb_dma_channel_count_get(uint32_t ui32Channel); -extern void md_usb_dma_channel_int_enable(uint32_t ui32Channel); -extern void md_usb_dma_channel_int_disable(uint32_t ui32Channel); -extern uint32_t md_usb_dma_channel_int_status(void); -extern void md_usb_dma_channel_enable(uint32_t ui32Channel); -extern void md_usb_dma_channel_disable(uint32_t ui32Channel); -extern uint32_t md_usb_dma_channel_isenabled(uint32_t ui32Channel); -extern uint32_t md_usb_dma_channel_status(uint32_t ui32Channel); -extern void md_usb_dma_channel_status_clear(uint32_t ui32Channel, - uint32_t ui32Status); -/** - * @} USB DMA API. - */ - -#ifdef __cplusplus -} -#endif - -#endif - -/******************* (C) COPYRIGHT Eastsoft Microelectronics Co., Ltd. *** END OF FILE ****/ diff --git a/bsp/essemi/es32f0271/libraries/ES32F027x_MD_StdPeriph_Driver/ReleaseNote.html b/bsp/essemi/es32f0271/libraries/ES32F027x_MD_StdPeriph_Driver/ReleaseNote.html deleted file mode 100644 index de5a1aada3..0000000000 --- a/bsp/essemi/es32f0271/libraries/ES32F027x_MD_StdPeriph_Driver/ReleaseNote.html +++ /dev/null @@ -1,17 +0,0 @@ - - - - -ReleaseNote -

ES32F0271 MD Release Note

-

V1.00 2019-1-4

-

初版发布

-

V1.01 2019-5-7

-

1.修改USB MD库相关接口

-

V1.03 2019-09-23

-
    -
  1. 增加ADC校準函數
    2. - -
- - \ No newline at end of file diff --git a/bsp/essemi/es32f0271/libraries/ES32F027x_MD_StdPeriph_Driver/Source/md_adc.c b/bsp/essemi/es32f0271/libraries/ES32F027x_MD_StdPeriph_Driver/Source/md_adc.c deleted file mode 100644 index d8571b0912..0000000000 --- a/bsp/essemi/es32f0271/libraries/ES32F027x_MD_StdPeriph_Driver/Source/md_adc.c +++ /dev/null @@ -1,298 +0,0 @@ -/** - ****************************************************************************** - * @file md_adc.c - * @brief ES32F0271 ADC Source File. - * - * @version V1.00.01 - * @data 7/01/2019 - * @author Taipei AE Team - * @note - * detailed description - * - * Copyright (C) 2018 Shanghai Eastsoft Microelectronics Co., Ltd. ALL rights reserved. - ******************************************************************************* - */ - - -/* Includes -------------------------------------------------------------------*/ -#include "md_adc.h" -#include "md_syscfg.h" -#include - - -/** @addtogroup Micro_Driver - * @{ - */ - - -/** @defgroup ADC ADC - * @brief ADC micro driver - * @{ - */ - -/* Private types --------------------------------------------------------------*/ -/* Private variables ----------------------------------------------------------*/ -/* Private constants ----------------------------------------------------------*/ -/* Private macros -------------------------------------------------------------*/ -#define Reference_V1 1 //First reference point -#define Reference_V2 2 //Second reference point - -double Ideal_V1; -double Ideal_V2; -double Reference_V1_ADCValue ; -double Reference_V2_ADCValue ; - -/* Private function prototypes ------------------------------------------------*/ -void (*md_adc_SS0_sample[])(ADC_TypeDef *, uint32_t) = -{ - md_adc_set_ss0_mux0_mux0, - md_adc_set_ss0_mux0_mux1, - md_adc_set_ss0_mux0_mux2, - md_adc_set_ss0_mux0_mux3, - md_adc_set_ss0_mux0_mux4, - md_adc_set_ss0_mux0_mux5, - md_adc_set_ss0_mux0_mux6, - md_adc_set_ss0_mux0_mux7, - md_adc_set_ss0_mux1_mux8, - md_adc_set_ss0_mux1_mux9, - md_adc_set_ss0_mux1_mux10, - md_adc_set_ss0_mux1_mux11, - md_adc_set_ss0_mux1_mux12, - md_adc_set_ss0_mux1_mux13, - md_adc_set_ss0_mux1_mux14, - md_adc_set_ss0_mux1_mux15 -}; - -void (*md_adc_SS1_sample[])(ADC_TypeDef *, uint32_t) = -{ - md_adc_set_ss0_mux0_mux0, - md_adc_set_ss0_mux0_mux1, - md_adc_set_ss0_mux0_mux2, - md_adc_set_ss0_mux0_mux3, - md_adc_set_ss0_mux0_mux4, - md_adc_set_ss0_mux0_mux5, - md_adc_set_ss0_mux0_mux6, - md_adc_set_ss0_mux0_mux7, -}; - -void (*md_adc_SS2_sample[])(ADC_TypeDef *, uint32_t) = -{ - md_adc_set_ss0_mux0_mux0, - md_adc_set_ss0_mux0_mux1, - md_adc_set_ss0_mux0_mux2, - md_adc_set_ss0_mux0_mux3, -}; - -/* Public functions -----------------------------------------------------------*/ -/** @defgroup ADC_PUB_FUNC ADC Public Functions - * @brief ADC Public Functions - * @{ - */ -/** - * @brief ADC Initialization Function. - * @param ADC Instance. - * @param channel - * @retval None - */ -void md_adc_init(ADC_TypeDef *ADCx, md_adc_inittypedef *ADC_InitStruct, uint8_t *channel) -{ - uint8_t i = 0; - - md_syscfg_enable_cfg_currgen(SYSCFG); - md_syscfg_set_cfg_vlrs(SYSCFG, ADC_InitStruct->VRLS); - md_syscfg_enable_cfg_vrefen(SYSCFG); - - if (ADC_InitStruct->SSx == 0) - { - md_adc_set_ss0_con_sel(ADC, ADC_InitStruct->Sel); - md_adc_set_ss0_con_type(ADC, ADC_InitStruct->Type); - - md_adc_set_srate_cntini(ADC, ADC_InitStruct->Cntini); - md_adc_set_srate_cnt(ADC, ADC_InitStruct->Cnt); - md_adc_set_frf_ffrst(ADC); - - - for (i = 0; i < 16; i++) - md_adc_SS0_sample[i](ADC, channel[i]); - - md_adc_enable_ier_ss0ie(ADC); - md_adc_set_ss0_end_end(ADC, ADC_InitStruct->End); - md_adc_enable_ss0_end_ie15(ADC); - md_adc_set_gainh_ch8pga(ADC, MD_ADC_GAIN_CHPGA_X1); - - - md_adc_set_srate(ADC, (ADC_InitStruct->Ckdiv) | ADC_SRATE_CKEN_MSK); - md_adc_enable_ssen_ss0en(ADC); - } - else if (ADC_InitStruct->SSx == 1) - { - md_adc_set_ss1_con_sel(ADC, ADC_InitStruct->Sel); - md_adc_set_ss1_con_type(ADC, ADC_InitStruct->Type); - - md_adc_set_srate_cntini(ADC, ADC_InitStruct->Cntini); - md_adc_set_srate_cnt(ADC, ADC_InitStruct->Cnt); - md_adc_set_frf_ffrst(ADC); - - for (i = 0; i < 8; i++) - md_adc_SS1_sample[i](ADC, channel[i]); - - md_adc_enable_ier_ss1ie(ADC); - md_adc_set_ss1_end_end(ADC, ADC_InitStruct->End); - md_adc_enable_ss1_end_ie7(ADC); - md_adc_set_gainh_ch8pga(ADC, MD_ADC_GAIN_CHPGA_X1); - - md_adc_set_srate(ADC, (ADC_InitStruct->Ckdiv) | ADC_SRATE_CKEN_MSK); - md_adc_enable_ssen_ss1en(ADC); - } - else if (ADC_InitStruct->SSx == 2) - { - md_adc_set_ss2_con_sel(ADC, ADC_InitStruct->Sel); - md_adc_set_ss2_con_type(ADC, ADC_InitStruct->Type); - - md_adc_set_srate_cntini(ADC, ADC_InitStruct->Cntini); - md_adc_set_srate_cnt(ADC, ADC_InitStruct->Cnt); - md_adc_set_frf_ffrst(ADC); - - for (i = 0; i < 4; i++) - md_adc_SS2_sample[i](ADC, channel[i]); - - md_adc_enable_ier_ss2ie(ADC); - md_adc_set_ss2_end_end(ADC, ADC_InitStruct->End); - md_adc_enable_ss2_end_ie3(ADC); - md_adc_set_gainh_ch8pga(ADC, MD_ADC_GAIN_CHPGA_X1); - - md_adc_set_srate(ADC, (ADC_InitStruct->Ckdiv) | ADC_SRATE_CKEN_MSK); - md_adc_enable_ssen_ss2en(ADC); - } - else - { - md_adc_set_ss3_con_sel(ADC, ADC_InitStruct->Sel); - md_adc_set_ss3_con_type(ADC, ADC_InitStruct->Type); - - md_adc_set_srate_cntini(ADC, ADC_InitStruct->Cntini); - md_adc_set_srate_cnt(ADC, ADC_InitStruct->Cnt); - md_adc_set_frf_ffrst(ADC); - - MODIFY_REG(ADC->SS3_MUX0, ADC_SS3_MUX0_MUX0_MSK, MD_ADC_SS_MUX_ADIN8 << ADC_SS3_MUX0_MUX0_POSS); - - md_adc_enable_ier_ss3ie(ADC); - md_adc_set_ss3_end_end(ADC, ADC_InitStruct->End); - md_adc_enable_ss3_end_ie0(ADC); - md_adc_set_gainh_ch8pga(ADC, MD_ADC_GAIN_CHPGA_X1); - - md_adc_set_srate(ADC, (ADC_InitStruct->Ckdiv) | ADC_SRATE_CKEN_MSK); - md_adc_enable_ssen_ss3en(ADC); - } -} - - -/** - * @brief Get the ADC calibration offset data - * @param vref: reference v - * @param vdd: external v - * @param offset: Get Offset - * @param coefficient: Get Coefficient - * @retval None - */ -void md_adc_calibration_data(double vdd, double vref,double *offset,double *coefficient) -{ - Ideal_V1 = Reference_V1 / vref * 4096; - Ideal_V2 = Reference_V2 / vref * 4096; - if (vdd == 5 && vref == 5) - { - if ((FC->ADCTRIM_VDD5V_VREF5V >> 24) == 0xA5) - { - Reference_V1_ADCValue = FC->ADCTRIM_VDD5V_VREF5V & 0xFFF; - Reference_V2_ADCValue = (FC->ADCTRIM_VDD5V_VREF5V >> 12) & 0xFFF; - } - } - else if (vdd == 3.3 && vref == 3.3) - { - if ((FC->ADCTRIM_VDD3V3_VREF3V3 >> 24) == 0xA5) - { - Reference_V1_ADCValue = FC->ADCTRIM_VDD3V3_VREF3V3 & 0xFFF; - Reference_V2_ADCValue = (FC->ADCTRIM_VDD3V3_VREF3V3 >> 12) & 0xFFF; - } - } - else if ((vdd == 5 && vref == 2.5) || (vdd == 3.3 && vref == 2.5)) - { - if ((FC->ADCTRIM_VDD5V_VREF2V5 >> 24) == 0xA5) - { - Reference_V1_ADCValue = FC->ADCTRIM_VDD5V_VREF2V5 & 0xFFF; - Reference_V2_ADCValue = (FC->ADCTRIM_VDD5V_VREF2V5 >> 12) & 0xFFF; - } - } - else - { - - } - -// Reference_V1_ADCValue = 115 ; -// Reference_V2_ADCValue = 365 ; - - printf("Ideal_V1:%.2f\r\n", Ideal_V1); - printf("Ideal_V2:%.2f\r\n", Ideal_V2); - printf("Reference_V1_ADCValue:%.2f\r\n", Reference_V1_ADCValue); - printf("Reference_V2_ADCValue:%.2f\r\n", Reference_V2_ADCValue); - - *offset = (Reference_V2 * Reference_V1_ADCValue - Reference_V1 * Reference_V2_ADCValue) / (Reference_V2 - Reference_V1); - printf("Offset=%.2f\r\n", *offset); - *coefficient = Ideal_V1 / (Reference_V1_ADCValue - *offset); - printf("Coefficient=%.2f\r\n", *coefficient); -} - -/** - * @brief Get the ADC fixed data - * @param SSx: Sequence SSx - * @param offset:input offset - * @param coefficient: input coefficient - * @param calibration :get calibration result - * @retval None - */ - -void md_adc_get_data(uint8_t SSx,double offset,double coefficient, uint16_t *calibration) -{ - uint16_t i, data, s_times; - double calibration_value = 0; - - if (SSx == 0) - s_times = 16; - else if (SSx == 1) - s_times = 8; - else if (SSx == 2) - s_times = 4; - else - s_times = 1; - - for (i = 0; i < s_times; i++) - { - if(SSx == 0) - data = md_adc_get_ss0_data(ADC); - else if(SSx == 1) - data = md_adc_get_ss1_data(ADC); - else if(SSx == 2) - data = md_adc_get_ss2_data(ADC); - else - data = md_adc_get_ss3_data(ADC); - if(data >= 4095) - data = 4095; - printf("data = %4d\r\n",data); - calibration_value = (data - offset) * coefficient; - if (calibration_value >= 4095) - calibration_value = 4095; - *calibration++=(uint16_t)calibration_value; - } -} -/** - * @} ADC_PUB_FUNC ADC Public Functions - */ - -/** - * @} ADC - */ - -/** - * @} Micro_Driver - */ - -/******************* (C) COPYRIGHT Eastsoft Microelectronics *****END OF FILE****/ diff --git a/bsp/essemi/es32f0271/libraries/ES32F027x_MD_StdPeriph_Driver/Source/md_fc.c b/bsp/essemi/es32f0271/libraries/ES32F027x_MD_StdPeriph_Driver/Source/md_fc.c deleted file mode 100644 index ce5d644209..0000000000 --- a/bsp/essemi/es32f0271/libraries/ES32F027x_MD_StdPeriph_Driver/Source/md_fc.c +++ /dev/null @@ -1,300 +0,0 @@ -/** - ****************************************************************************** - * @file md_fc.c - * @brief ES32F0271 FC Source File. - * - * @version V1.00.01 - * @date day/mon/year - * @author Eastsoft AE Team - * @note - * detailed description - * - * Copyright (C) 2018 Shanghai Eastsoft Microelectronics Co., Ltd. ALL rights reserved. - ******************************************************************************* - */ - -/* Includes -------------------------------------------------------------------*/ -#include "md_syscfg.h" -#include "md_fc.h" - -/** @addtogroup Micro_Driver - * @{ - */ - -#if defined (FC) - -/** @defgroup FC FC - * @brief FC micro driver - * @{ - */ - -/* Private types --------------------------------------------------------------*/ -/* Private variables ----------------------------------------------------------*/ -/* Private macros -------------------------------------------------------------*/ - -/* Private constants ----------------------------------------------------------*/ -/** @defgroup MD_FC_Private_Constants FC Private Constants - * @{ - */ - -#define REMAPDATA_BASE (( uint32_t)0x00000000) /* FLASH Main (64K Bytes) */ -#define REMAPINFO_BASE (( uint32_t)0x00000000) /* FLASH Info ( 6K Bytes) - Boot Loader Memory */ - -#define EFOPT_PAGE6_OFFSET (MD_FC_PC_EF_IPAGESZ*6) -#define EFOPT_PAGE7_OFFSET (MD_FC_PC_EF_IPAGESZ*7) -#define EFOPT_PL1_OFFSET (MD_FC_PC_EF_IPAGESZ*7+0x0) -#define EFOPT_PL2_OFFSET (MD_FC_PC_EF_IPAGESZ*6+0x28) -#define EFOPT_REMAP_OFFSET (MD_FC_PC_EF_IPAGESZ*7+0x8) - -/** - * @} MD_FC_Private_Constants - */ - -/* Private function prototypes ------------------------------------------------*/ - -/* Public functions -----------------------------------------------------------*/ -/** @defgroup MD_FC_Public_Functions FC Public Functions - * @{ - */ - -/** - * @brief FC main erase. - * @note To prevent unexpected code branch, the main erase function must specify a dedicated main erase ID - * @param MEraseID Key for main erase, must be 0xA5A5AA55 - * @retval An ErrorStatus enumeration value: - * - SUCCESS: Main flash erased - * - ERROR: Main erase ID mismatch - */ -ErrorStatus md_fc_merase(uint32_t MEraseID) -{ - ErrorStatus status = ERROR; - - /* Check the ID */ - if (MEraseID != MD_FC_PC_EF_MERASEID) - return status; - - /* Write MERASE to CMD*/ - md_fc_set_fc_cmd(MD_FC_PC_CMD_MACRO_ERASE); - - status = SUCCESS; - return status; -} - -/** - * @brief FC Sector Erase - * @note To prevent unexpected code branch, the page erase function must specify the complement start address - * @param pSErasePara Pointer to structure md_fc_ControlTypeDef - * @retval An ErrorStatus enumeration value. - * - SUCCESS: Specified page address erased - * - ERROR: Complement of start address mismatch - */ -ErrorStatus md_fc_serase(md_fc_ControlTypeDef *pSErasePara) -{ - ErrorStatus status = ERROR; - - /* Check the start address and complement of start address*/ - if (pSErasePara->SAddr & pSErasePara->SAddrC) - return status; - - /* Write sector address to PA*/ - md_fc_set_pa_prog_addr(pSErasePara->SAddr); - /* Write SERASE to CMD*/ - md_fc_set_fc_cmd(MD_FC_PC_CMD_SECTOR_ERASE); - - status = SUCCESS; - return status; -} - -/** - * @brief FC Page Program - * @note To prevent unexpected code branch, the page program function must specify the complement start address - * @param pProgramPara Pointer to structure md_fc_ControlTypeDef - * @retval An ErrorStatus enumeration value. - * - SUCCESS: Data in data buffer programed to specified page address - * - ERROR: Complement of start address mismatch - */ -ErrorStatus md_fc_program(md_fc_ControlTypeDef *pProgramPara) -{ - ErrorStatus status = ERROR; - uint16_t BCnt; - - md_fc_set_pa_pcnt(pProgramPara->BCnt); - md_fc_set_pa_prog_addr(pProgramPara->SAddr); - BCnt = pProgramPara->BCnt; - BCnt >>= 3; - - while (BCnt--) - { - /* Check the start address and complement of start address*/ - if (pProgramPara->SAddr & pProgramPara->SAddrC) - return status; - - /* Write lower 32bit program data to PLD*/ - md_fc_set_pld(*pProgramPara->pU32Buf++); - /* Write higher 32bit program data to PHD*/ - md_fc_set_phd(*pProgramPara->pU32Buf++); - /* Write PROGRAM to CMD*/ - md_fc_set_fc_cmd(MD_FC_PC_CMD_PROG_EFLASH); - } - - status = SUCCESS; - return status; -} - -/** - * @brief FC Page Read - * @param pReadPara Pointer to structure md_fc_ControlTypeDef - * @retval Always return SUCCESS - * - Data in specified page address read to data buffer - */ -ErrorStatus md_fc_read(md_fc_ControlTypeDef *pReadPara) -{ - ErrorStatus status = SUCCESS; - uint32_t *EFAddr; - uint16_t BCnt; - - if (md_syscfg_get_remap_memmod(SYSCFG) == MD_SYSCFG_MEMMOD_MAIN) /* Reamp from Main */ - EFAddr = (uint32_t *)(REMAPDATA_BASE + pReadPara->SAddr); - else - EFAddr = (uint32_t *)(FLASH_BASE + pReadPara->SAddr); - - BCnt = pReadPara->BCnt; - BCnt >>= 2; - - while (BCnt--) - *pReadPara->pU32Buf++ = *EFAddr++; - - return status; -} - -/** - * @brief FC Update Protect Level 1 Setting - * @param pUpdPL1Para Pointer to structure md_fc_UpdProtTypeDdef - * @retval Always return SUCCESS - */ -ErrorStatus md_fc_updprotl1(md_fc_UpdProtTypeDef *pUpdPL1Para) -{ - ErrorStatus status = SUCCESS; - uint32_t EFProtL1L, EFProtL1H; - - EFProtL1L = FC->OP_PRT1L; - EFProtL1H = FC->OP_PRT1H; - - if ((EFProtL1L == 0xffffffffUL) && (EFProtL1H == 0xffffffffUL)) /* First Time to Set Level1 */ - { - /* Write offset address to PA*/ - md_fc_set_pa_prog_addr(EFOPT_PL1_OFFSET); - md_fc_enable_pa_ifren(); - /* Write lower 32bit update data to PLD*/ - md_fc_set_pld(pUpdPL1Para->UpdateL); - /* Write higher 32bit update data to PHD*/ - md_fc_set_phd(pUpdPL1Para->UpdateH); - - /* Write PROGRAM to CMD*/ - md_fc_set_fc_cmd(MD_FC_PC_CMD_PROG_EFLASH); - } - else - { - /* Write lower 32bit clear data to PLD*/ - md_fc_set_pld(pUpdPL1Para->ClearL); - /* Write higher 32bit clear data to PHD*/ - md_fc_set_phd(pUpdPL1Para->ClearH); - - /* Write lower 32bit data to UPL*/ - md_fc_set_upl(pUpdPL1Para->UpdateL); - /* Write higher 32bit data to UPH*/ - md_fc_set_uph(pUpdPL1Para->UpdateH); - - /* Write UPDPL1 to CMD*/ - md_fc_set_fc_cmd(MD_FC_PC_CMD_UPDATE_LV1_PROTECT); - } - - return status; -} - -/** - * @brief FC Update Protect Level 2 Setting - * @param pUpdPL2Para Pointer to structure md_fc_UpdProtTypeDdef - * @retval Always return SUCCESS - */ -ErrorStatus md_fc_updprotl2(md_fc_UpdProtTypeDef *pUpdPL2Para) -{ - ErrorStatus status = SUCCESS; - uint32_t EFProtL2L, EFProtL2H; - - EFProtL2L = FC->OP_PRT2L; - EFProtL2H = FC->OP_PRT2H; - - if ((EFProtL2L == 0xffffffffUL) && (EFProtL2H == 0xffffffffUL)) /* First Time to Set Level2 */ - { - /* Write offset address to PA*/ - md_fc_set_pa_prog_addr(EFOPT_PL2_OFFSET); - md_fc_enable_pa_ifren(); - /* Write lower 32bit update data to PLD*/ - md_fc_set_pld(pUpdPL2Para->UpdateL); - /* Write higher 32bit update data to PHD*/ - md_fc_set_phd(pUpdPL2Para->UpdateH); - - /* Write PROGRAM to CMD*/ - md_fc_set_fc_cmd(MD_FC_PC_CMD_PROG_EFLASH); - } - else - { - /* Write lower 32bit clear data to PLD*/ - md_fc_set_pld(pUpdPL2Para->ClearL); - /* Write higher 32bit clear data to PHD*/ - md_fc_set_phd(pUpdPL2Para->ClearH); - - /* Write lower 32bit data to UPL*/ - md_fc_set_upl(pUpdPL2Para->UpdateL); - /* Write higher 32bit data to UPH*/ - md_fc_set_uph(pUpdPL2Para->UpdateH); - - /* Write UPDPL2 to CMD*/ - md_fc_set_fc_cmd(MD_FC_PC_CMD_UPDATE_LV2_PROTECT); - } - - return status; -} - -/** - * @brief FC Update Remap Option - * @param UpdRemap New remap setting value (remap address=valus(0x0~0xf)*0x1000, 0x10=BootLoader) - * @retval Always return SUCCESS - */ -ErrorStatus md_fc_updremap(uint8_t UpdRemap) -{ - ErrorStatus status = SUCCESS; - - /* Write sector address to PA*/ - md_fc_enable_pa_ifren(); - md_fc_set_pa_prog_addr(EFOPT_PAGE7_OFFSET); - /* Write SERASE to CMD*/ - md_fc_set_fc_cmd(MD_FC_PC_CMD_SECTOR_ERASE); - /* Write remap offset address to PA*/ - md_fc_set_pa_prog_addr(EFOPT_REMAP_OFFSET); - md_fc_enable_pa_ifren(); - /* Write lower 32bit remap data to PLD*/ - md_fc_set_pld(0xffffff00UL | UpdRemap); - /* Write higher 32bit remap data to PHD*/ - md_fc_set_phd(0xffffffffUL); - /* Write PROGRAM to CMD*/ - md_fc_set_fc_cmd(MD_FC_PC_CMD_PROG_EFLASH); - - return status; -} - -/** - * @} MD_FC_Public_Functions - */ - -/** - * @} FC - */ -#endif - -/** - * @} Micro_Driver - */ - -/******************* (C) COPYRIGHT Eastsoft Microelectronics *****END OF FILE****/ diff --git a/bsp/essemi/es32f0271/libraries/ES32F027x_MD_StdPeriph_Driver/Source/md_gpio.c b/bsp/essemi/es32f0271/libraries/ES32F027x_MD_StdPeriph_Driver/Source/md_gpio.c deleted file mode 100644 index 0fa1126bab..0000000000 --- a/bsp/essemi/es32f0271/libraries/ES32F027x_MD_StdPeriph_Driver/Source/md_gpio.c +++ /dev/null @@ -1,215 +0,0 @@ -/** - ****************************************************************************** - * @file md_gpio.c - * @brief ES32F0271 GPIO Source File. - * - * @version V1.00.01 - * @data day/mon/year - * @author Eastsoft AE Team - * @note - * detailed description - * - * Copyright (C) 2018 Shanghai Eastsoft Microelectronics Co., Ltd. ALL rights reserved. - ******************************************************************************* - */ - -/* Includes -------------------------------------------------------------------*/ -#include "md_rcu.h" -#include "md_gpio.h" - -/** @addtogroup Micro_Driver - * @{ - */ - -#if defined (GPIOA) || defined (GPIOB) || defined (GPIOC) || defined (GPIOD) - -/** @defgroup GPIO GPIO - * @brief GPIO micro driver - * @{ - */ - -/* Private types --------------------------------------------------------------*/ -/* Private variables ----------------------------------------------------------*/ -/* Private constants ----------------------------------------------------------*/ -/* Private macros -------------------------------------------------------------*/ -/** @defgroup MD_GPIO_Private_Macros GPIO Private Macros - * @{ - */ -#define IS_MD_GPIO_ALL_INSTANCE(__INSTANCE__) ((__INSTANCE__ == GPIOA) \ - || (__INSTANCE__ == GPIOB)) \ -|| (__INSTANCE__ == GPIOC)) \ -|| (__INSTANCE__ == GPIOD)) - -#define IS_MD_GPIO_PIN(__VALUE__) (((__VALUE__) == MD_GPIO_PIN_0) \ - || ((__VALUE__) == MD_GPIO_PIN_1) \ - || ((__VALUE__) == MD_GPIO_PIN_2) \ - || ((__VALUE__) == MD_GPIO_PIN_3) \ - || ((__VALUE__) == MD_GPIO_PIN_4) \ - || ((__VALUE__) == MD_GPIO_PIN_5) \ - || ((__VALUE__) == MD_GPIO_PIN_6) \ - || ((__VALUE__) == MD_GPIO_PIN_7) \ - || ((__VALUE__) == MD_GPIO_PIN_8) \ - || ((__VALUE__) == MD_GPIO_PIN_9) \ - || ((__VALUE__) == MD_GPIO_PIN_10) \ - || ((__VALUE__) == MD_GPIO_PIN_11) \ - || ((__VALUE__) == MD_GPIO_PIN_12) \ - || ((__VALUE__) == MD_GPIO_PIN_13) \ - || ((__VALUE__) == MD_GPIO_PIN_14) \ - || ((__VALUE__) == MD_GPIO_PIN_15)) \ - -#define IS_MD_GPIO_MODE(__VALUE__) (((__VALUE__) == MD_GPIO_MODE_INPUT) \ - || ((__VALUE__) == MD_GPIO_MODE_OUTPUT) \ - || ((__VALUE__) == MD_GPIO_MODE_FUNCTION) \ - || ((__VALUE__) == MD_GPIO_MODE_ANALOG)) - -#define IS_MD_GPIO_OUTPUT_TYPE(__VALUE__) (((__VALUE__) == MD_GPIO_OUTPUT_PUSHPULL) \ - || ((__VALUE__) == MD_GPIO_OUTPUT_OPENDRAIN)) - -#define IS_MD_GPIO_PULL(__VALUE__) (((__VALUE__) == MD_GPIO_PULL_FLOATING) \ - || ((__VALUE__) == MD_GPIO_PULL_UP) \ - || ((__VALUE__) == MD_GPIO_PULL_DOWN) - -#define IS_MD_GPIO_DS(__VALUE__) (((__VALUE__) == MD_GPIO_DS_8mA) \ - || ((__VALUE__) == MD_GPIO_DS_16mA)) - -#define IS_MD_GPIO_FUNCTION(__VALUE__) (((__VALUE__) == MD_GPIO_AF0) \ - || ((__VALUE__) == MD_GPIO_AF1) \ - || ((__VALUE__) == MD_GPIO_AF2) \ - || ((__VALUE__) == MD_GPIO_AF3) \ - || ((__VALUE__) == MD_GPIO_AF4) \ - || ((__VALUE__) == MD_GPIO_AF5) \ - || ((__VALUE__) == MD_GPIO_AF6) \ - || ((__VALUE__) == MD_GPIO_AF7)) - -#define IS_MD_GPIO_IST(__VALUE__) (((__VALUE__) == MD_GPIO_IST_TTL) \ - || ((__VALUE__) == MD_GPIO_IST_CMOS)) - -/** - * @} MD_GPIO_Private_Macros - */ - -/* Private function prototypes ------------------------------------------------*/ - -/* Public functions -----------------------------------------------------------*/ -/** @addtogroup MD_GPIO_Public_Functions GPIO Public Functions - * @{ - */ - -/** @addtogroup MD_GPIO_PF_Init GPIO Public Init Functions - * @{ - */ - -/** - * @brief De-initialize the GPIO registers to their default reset values. - * @param GPIOx GPIO Instance - * @retval An ErrorStatus enumeration value: - * - SUCCESS: GPIO registers are de-initialized - * - ERROR: GPIO registers are not de-initialized - */ -ErrorStatus md_gpio_deinit(GPIO_TypeDef *GPIOx) -{ - ErrorStatus status = ERROR; - - /* Check the parameters */ - assert_param(IS_MD_GPIO_ALL_INSTANCE(GPIOx)); - - /* Force reset of GPIO clock */ - if (GPIOx == GPIOA) - { - md_rcu_enable_ahbrst_gpaen(RCU); - } - else if (GPIOx == GPIOB) - { - md_rcu_enable_ahbrst_gpben(RCU); - } - else if (GPIOx == GPIOC) - { - md_rcu_enable_ahbrst_gpcen(RCU); - } - else /* if(GPIOx==GPIOD) */ - { - md_rcu_enable_ahbrst_gpden(RCU); - } - - status = SUCCESS; - - return status; -} - -/** - * @brief Initialize the GPIO registers according to the specified parameters in GPIO_InitStruct. - * @note As some bits in GPIO configuration registers can only be written when the GPIO is disabled (GPIO_CR1_SPE bit =0), - * GPIO IP should be in disabled state prior calling this function. Otherwise, ERROR result will be returned. - * @param GPIOx GPIO Instance - * @param GPIO_InitStruct pointer to a @ref md_gpio_inittypedef structure - * @retval An ErrorStatus enumeration value. (Return always SUCCESS) - */ -ErrorStatus md_gpio_init(GPIO_TypeDef *GPIOx, md_gpio_inittypedef *GPIO_InitStruct) -{ - ErrorStatus status = ERROR; - - /* Check the GPIO Instance GPIOx*/ - assert_param(IS_MD_GPIO_ALL_INSTANCE(GPIOx)); - - /* Check the GPIO parameters from GPIO_InitStruct*/ - assert_param(IS_MD_GPIO_PIN(GPIO_InitStruct->Pin)); - assert_param(IS_MD_GPIO_MODE(GPIO_InitStruct->Mode)); - assert_param(IS_MD_GPIO_OUTPUT_TYPE(GPIO_InitStruct->OutputType)); - assert_param(IS_MD_GPIO_PULL(GPIO_InitStruct->Pull)); - assert_param(IS_MD_GPIO_DS(GPIO_InitStruct->OutDrive)); - assert_param(IS_MD_GPIO_FUNCTION(GPIO_InitStruct->Function)); - - if (POSITION_VAL(GPIO_InitStruct->Pin) <= 7) - { - md_gpio_set_function0_7(GPIOx, GPIO_InitStruct->Pin, GPIO_InitStruct->Function); - } - else - { - md_gpio_set_function8_15(GPIOx, GPIO_InitStruct->Pin, GPIO_InitStruct->Function); - } - - md_gpio_set_mode(GPIOx, GPIO_InitStruct->Pin, GPIO_InitStruct->Mode); - md_gpio_set_output_type(GPIOx, GPIO_InitStruct->Pin, GPIO_InitStruct->OutputType); - md_gpio_set_pull(GPIOx, GPIO_InitStruct->Pin, GPIO_InitStruct->Pull); - md_gpio_set_ds(GPIOx, GPIO_InitStruct->Pin, GPIO_InitStruct->OutDrive); - - status = SUCCESS; - - return status; -} - -/** - * @brief Set each @ref md_gpio_inittypedef field to default value. - * @param GPIO_InitStruct pointer to a @ref md_gpio_inittypedef structure - * whose fields will be set to default values. - * @retval None - */ -void md_gpio_struct_init(md_gpio_inittypedef *GPIO_InitStruct) -{ - /* Set GPIO_InitStruct fields to default values */ - GPIO_InitStruct->Function = MD_GPIO_AF0; - GPIO_InitStruct->Mode = MD_GPIO_MODE_ANALOG; - GPIO_InitStruct->OutDrive = MD_GPIO_DS_8mA; - GPIO_InitStruct->OutputType = MD_GPIO_OUTPUT_PUSHPULL; - GPIO_InitStruct->Pull = MD_GPIO_PULL_FLOATING; - GPIO_InitStruct->Pin = MD_GPIO_PIN_ALL; -} - -/** - * @} MD_GPIO_PF_Init - */ - -/** - * @} MD_GPIO_Public_Functions - */ - -/** - * @} GPIO - */ -#endif - -/** - * @} Micro_Driver - */ - -/******************* (C) COPYRIGHT Eastsoft Microelectronics *****END OF FILE****/ diff --git a/bsp/essemi/es32f0271/libraries/ES32F027x_MD_StdPeriph_Driver/Source/md_i2c.c b/bsp/essemi/es32f0271/libraries/ES32F027x_MD_StdPeriph_Driver/Source/md_i2c.c deleted file mode 100644 index e2dab7dc57..0000000000 --- a/bsp/essemi/es32f0271/libraries/ES32F027x_MD_StdPeriph_Driver/Source/md_i2c.c +++ /dev/null @@ -1,245 +0,0 @@ -/** - ****************************************************************************** - * @file md_i2c.c - * @brief ES32F0271 I2C Source File. - * - * @version V1.00.01 - * @date 4/12/2018 - * @author Eastsoft AE Team - * @note - * detailed description - * - * Copyright (C) 2018 Shanghai Eastsoft Microelectronics Co., Ltd. ALL rights reserved. - ******************************************************************************* - */ - -/* Includes -------------------------------------------------------------------*/ -#include "md_i2c.h" -#include "md_rcu.h" -#include -#include "stdint.h" -/** @addtogroup Micro_Driver - * @{ - */ - -/* Private types --------------------------------------------------------------*/ -/* Private variables ----------------------------------------------------------*/ -/* Private constants ----------------------------------------------------------*/ -/* Private macros -------------------------------------------------------------*/ - -/** - * @brief Initialize the I2C registers according to the specified parameters in I2C_InitStruct. - * @note The parameters in md_i2c_init should be expected values. Otherwise, ERROR result will be returned. - * @param I2Cx I2C Instance - * @param I2C_InitStruct pointer to a @ref md_i2c_inittypedef structure - * @retval An ErrorStatus enumeration value. (Return always SUCCESS) - */ -ErrorStatus md_i2c_init(I2C_TypeDef *I2Cx, md_i2c_inittypedef *I2C_InitStruct) -{ - ErrorStatus status = ERROR; - uint8_t pllmulnow; - - /* Check the I2C Instance I2Cx */ - assert_param(IS_MD_I2C_ALL_INSTANCE(I2Cx)); - - /* Check the I2C parameters from I2C_InitStruct */ - assert_param(IS_MD_I2C_TIMING(I2C_InitStruct->Timing)); - assert_param(IS_MD_I2C_ADDRSIZE(I2C_InitStruct->AddrSize)); - assert_param(IS_MD_I2C_ADDRESS1(I2C_InitStruct->Address1)); - assert_param(IS_MD_I2C_DUALADDRESSMODE(I2C_InitStruct->DualAddressMode)); - assert_param(IS_MD_I2C_ADDRESS2(I2C_InitStruct->Address2)); - assert_param(IS_MD_I2C_ADDRESS2MASKS(I2C_InitStruct->Address2Masks)); - /* Check the PLL clock, if not corrt, modify it */ - pllmulnow = md_rcu_get_cfg_pllmul(RCU); - - if (pllmulnow != (uint8_t)((I2C_InitStruct->Timing) >> 28)) - { - md_rcu_pllreinit((uint8_t)((I2C_InitStruct->Timing) >> 28)); - } - - md_i2c_disable_con1_pe(I2Cx); - md_i2c_set_timingr_presc(I2Cx, ((I2C_InitStruct->Timing) >> 24) & 0xF); - md_i2c_set_timingr_scll(I2Cx, ((I2C_InitStruct->Timing) >> 16) & 0xFF); - md_i2c_set_timingr_sclh(I2Cx, ((I2C_InitStruct->Timing) >> 8) & 0xFF); - md_i2c_set_timingr_sdadel(I2Cx, ((I2C_InitStruct->Timing) >> 4) & 0xF); - md_i2c_set_timingr_scldel(I2Cx, (I2C_InitStruct->Timing) & 0xF); - md_i2c_enable_con1_pe(I2Cx); - - md_i2c_disable_addr1_oa1en(I2Cx); - md_i2c_set_addr1_oa1(I2Cx, I2C_InitStruct->Address1); - - if (I2C_InitStruct->AddrSize == MD_I2C_OA1_10BIT) - md_i2c_set_addr1_oa1mode(I2Cx, MD_I2C_OA1_10BIT); - else - md_i2c_set_addr1_oa1mode(I2Cx, MD_I2C_OA1_7BIT); - - md_i2c_enable_addr1_oa1en(I2Cx); - - if (I2C_InitStruct->DualAddressMode == MD_I2C_DUALADDRESS_ENABLE) - { - md_i2c_disable_addr2_oa2en(I2Cx); - md_i2c_set_addr2_oa2mask(I2Cx, I2C_InitStruct->Address2Masks); - md_i2c_set_addr2_oa2(I2Cx, I2C_InitStruct->Address2); - md_i2c_enable_addr2_oa2en(I2Cx); - } - - status = SUCCESS; - - return status; -} - -/** - * @brief Set each @ref md_i2c_inittypedef field to default value. - * @param UART_InitStruct pointer to a @ref md_i2c_inittypedef structure - * whose fields will be set to default values. - * @retval None - */ -void md_i2c_struct_init(md_i2c_inittypedef *I2C_InitStruct) -{ - /* Set UART_InitStruct fields to default values */ - I2C_InitStruct->Timing = CLK100kHz48M; - I2C_InitStruct->AddrSize = MD_I2C_ADDRESSINGMODE_7BIT; - I2C_InitStruct->Address1 = 0x50 << 1; - I2C_InitStruct->DualAddressMode = MD_I2C_DUALADDRESS_DISABLE; - I2C_InitStruct->Address2 = 0x70 << 1; - I2C_InitStruct->Address2Masks = MD_I2C_ADDR2_NOMASK; -} - -/** - * @brief Transmits in master mode an amount of data in blocking mode. - * @param I2Cx I2C Instance - * @param The number of bytes to be transmitted - * @param Enable/Disable 10-bit addressing mode - * @param Device(slave) address - * @param The pointer to a data buffer - * @retval None - */ -void md_i2c_master_send(I2C_TypeDef *I2Cx, uint8_t Nbyte, uint32_t addr10, uint16_t DevAddr, uint8_t *txbuf) -{ - uint8_t index; - - /* Config Device(slave) address */ - if (addr10 == MD_I2C_ADDRESSINGMODE_10BIT) - md_i2c_set_con2_add10(I2Cx, MD_I2C_ADDRESSINGMODE_10BIT); - else - md_i2c_set_con2_add10(I2Cx, MD_I2C_ADDRESSINGMODE_7BIT); - - md_i2c_set_con2_sadd(I2Cx, DevAddr); - md_i2c_set_con2_nbytes(I2Cx, Nbyte); - md_i2c_set_fcon_txfrst(I2Cx, MD_I2C_TXFIFO_RESET); - md_i2c_set_con2_rd_wrn(I2Cx, MD_I2C_MASTER_WRITE); - md_i2c_set_con2_reload(I2Cx, MD_I2C_NORELOAD_MODE); - /* When NBYTES is matched, the communication will be automatically stop */ - md_i2c_set_con2_autoend(I2Cx, MD_I2C_AUTOEND_MODE); - - if (Nbyte <= 8) - { - for (index = 0; index < Nbyte; index++) - md_i2c_send(I2Cx, *txbuf++); - - Nbyte = 0; - } - else - { - for (index = 0; index < 8; index++) - md_i2c_send(I2Cx, *txbuf++); - - Nbyte -= 8; - } - - /* Start the I2C communication */ - md_i2c_set_con2_start(I2Cx, MD_I2C_START_GENERATION); - - while (Nbyte > 0) - { - while (md_i2c_is_active_stat_txf(I2Cx)); - - md_i2c_send(I2Cx, *txbuf++); - Nbyte--; - } -} - -/** - * @brief Receives in master mode an amount of data in blocking mode. - * @param I2Cx I2C Instance - * @param The number of bytes to be received - * @param Enable/Disable 10-bit addressing mode - * @param Device(slave) address - * @param The pointer to a data buffer - * @retval None - */ -void md_i2c_master_rece(I2C_TypeDef *I2Cx, uint8_t Nbyte, uint32_t addr10, uint16_t DevAddr, uint8_t *rxbuf) -{ - /* Config Device(slave) address */ - if (addr10 == MD_I2C_ADDRESSINGMODE_10BIT) - md_i2c_set_con2_add10(I2Cx, MD_I2C_ADDRESSINGMODE_10BIT); - else - md_i2c_set_con2_add10(I2Cx, MD_I2C_ADDRESSINGMODE_7BIT); - - md_i2c_set_con2_sadd(I2Cx, DevAddr); - md_i2c_set_con2_nbytes(I2Cx, Nbyte); - md_i2c_set_fcon_rxfrst(I2Cx, MD_I2C_RXFIFO_RESET); - md_i2c_set_con2_rd_wrn(I2Cx, MD_I2C_MASTER_READ); - md_i2c_set_con2_reload(I2Cx, MD_I2C_NORELOAD_MODE); - /* When NBYTES is matched, the communication will be automatically stop */ - md_i2c_set_con2_autoend(I2Cx, MD_I2C_AUTOEND_MODE); - /* Start the I2C communication */ - md_i2c_set_con2_start(I2Cx, MD_I2C_START_GENERATION); - - while (Nbyte > 0) - { - /* Wait Rx FIFO non-empty */ - while (md_i2c_is_active_stat_rxe(I2Cx)); - - *rxbuf++ = md_i2c_recv(I2Cx); - Nbyte--; - } -} - -/** - * @brief Transmits in slave mode an amount of data in blocking mode. - * @param I2Cx I2C Instance - * @param The number of bytes to be transmitted, not for NBYTES - * @param The pointer to a data buffer - * @retval None - */ -void md_i2c_slave_send(I2C_TypeDef *I2Cx, uint8_t Num, uint8_t *txbuf) -{ - md_i2c_set_fcon_txfrst(I2Cx, MD_I2C_TXFIFO_RESET); - - while (!(md_i2c_is_active_stat_busy(I2Cx))); - - while (Num > 0) - { - while (md_i2c_is_active_stat_txf(I2Cx)); - - md_i2c_send(I2Cx, *txbuf++); - Num--; - } -} - -/** - * @brief Receives in slave mode an amount of data in blocking mode. - * @param I2Cx I2C Instance - * @param The number of bytes to be transmitted, not for NBYTES - * @param The pointer to a data buffer - * @retval None - */ -void md_i2c_slave_rece(I2C_TypeDef *I2Cx, uint8_t Num, uint8_t *rxbuf) -{ - md_i2c_set_fcon_rxfrst(I2Cx, MD_I2C_RXFIFO_RESET); - - while (!(md_i2c_is_active_stat_busy(I2Cx))); - - while (Num > 0) - { - while (md_i2c_is_active_stat_rxe(I2Cx)); - - *rxbuf++ = md_i2c_recv(I2Cx); - Num--; - } -} - -/** - * @} Micro_Driver - */ diff --git a/bsp/essemi/es32f0271/libraries/ES32F027x_MD_StdPeriph_Driver/Source/md_rcu.c b/bsp/essemi/es32f0271/libraries/ES32F027x_MD_StdPeriph_Driver/Source/md_rcu.c deleted file mode 100644 index 99ac22cf91..0000000000 --- a/bsp/essemi/es32f0271/libraries/ES32F027x_MD_StdPeriph_Driver/Source/md_rcu.c +++ /dev/null @@ -1,378 +0,0 @@ -/** - ****************************************************************************** - * @file md_rcu.c - * @brief ES32F0271 RCU Source File. - * - * @version V1.00.01 - * @data 6/12/2018 - * @author Eastsoft AE Team - * @note - * detailed description - * - * Copyright (C) 2018 Shanghai Eastsoft Microelectronics Co., Ltd. ALL rights reserved. - ******************************************************************************* - */ - -/* Includes -------------------------------------------------------------------*/ -#include "md_rcu.h" -#include "md_fc.h" -#include "system_es32f027x.h" - -/** @addtogroup Micro_Driver - * @{ - */ - - -/** @defgroup RCU RCU - * @brief RCU micro driver - * @{ - */ - - -/* Private types --------------------------------------------------------------*/ -/* Private variables ----------------------------------------------------------*/ -/* Private constants ----------------------------------------------------------*/ -/* Private macros -------------------------------------------------------------*/ -/** @defgroup MD_RCU_Private_Macros RCU Private Macros - * @{ - */ - - -/** - * @} MD_RCU_Private_Macros - */ - -/* Private function prototypes ------------------------------------------------*/ - -/* Public functions -----------------------------------------------------------*/ -/** @addtogroup MD_RCU_Public_Functions RCU Public Functions - * @{ - */ - -/** @addtogroup MD_RCU_PF_Init RCU Public Init Functions - * @{ - */ - -/** - * @brief - * @param - * @retval None - */ -void md_rcu_init(void) -{ - uint8_t pllmux; - - md_fc_set_con_wait(3); - - md_rcu_set_cfg_mpre(RCU, 0UL); - md_rcu_set_cfg_msw(RCU, MD_RCU_MCO_DISABLE); - md_rcu_set_cfg_pllmul(RCU, 12 - 1); - md_rcu_set_cfg_pllsrc(RCU, MD_RCU_PLL_SRC_HRC); - md_rcu_set_cfg_hoscdiv(RCU, 2 - 1); - md_rcu_set_cfg_ppre(RCU, MD_RCU_PPRE_HCLK_DIV_1); - md_rcu_set_cfg_hpre(RCU, MD_RCU_HPRE_SYSCLK_DIV_1); - md_rcu_set_cfg_sw(RCU, MD_RCU_SYSCLK_PLL0); - - md_rcu_disable_con_csson(RCU); - md_rcu_disable_con_pll1on(RCU); - md_rcu_enable_con_pll0on(RCU); - md_rcu_disable_con_loscon(RCU); - md_rcu_disable_con_lrcon(RCU); - md_rcu_disable_con_hoscon(RCU); - md_rcu_enable_con_hrcon(RCU); - - md_rcu_set_cfg_ckcfg(RCU); - - /* while(md_rcu_get_con_hoscrdy(RCU)==0) {} */ - - /* while(md_rcu_get_con_pll0rdy(RCU)==0) {} */ - - - if (RCU->CON & RCU_CON_HRCON_MSK) /* if HRC enbale */ - while (md_rcu_get_con_hrcrdy(RCU) == 0); /* Wait for HRCRDY = 1 (HRC is ready)*/ - - - if (RCU->CON & RCU_CON_HOSCON_MSK) /* if HOSC enbale */ - while (md_rcu_get_con_hoscrdy(RCU) == 0); /* Wait for HOSCRDY = 1 (HOSC is ready)*/ - - - if (RCU->CON & RCU_CON_LRCON_MSK) /* if LRC enbale */ - while (md_rcu_get_con_lrcrdy(RCU) == 0); /* Wait for LRCRDY = 1 (LRC is ready)*/ - - - if (RCU->CON & RCU_CON_LOSCON_MSK) /* if LOSC enbale */ - while (md_rcu_get_con_loscrdy(RCU) == 0); /* Wait for LOSCRDY = 1 (LOSC is ready)*/ - - if (RCU->CON & RCU_CON_PLL0ON_MSK) /* if PLL enbale */ - while (md_rcu_get_con_pll0rdy(RCU) == 0); /* Wait for PLLRDY = 1 (PLL is ready)*/ - - - - /* PLL Reference Clock Source*/ - if (md_rcu_get_cfg_pllsrc(RCU)) - PLL0Frequency = (uint32_t)(__HOSC / (md_rcu_get_cfg_pllsrc(RCU) + 1)); - else - PLL0Frequency = (uint32_t)(__HRC); - - /* System Frequency */ - switch (md_rcu_get_cfg_sw(RCU)) /* System clock switch(SYSCLK) */ - { - case 0: /*================= HRC selected as system clock*/ - SystemCoreClock = (uint32_t)(__HRC); - break; - - case 1: /*================= HOSC selected as system clock*/ - SystemCoreClock = (uint32_t)(__HOSC); - break; - - case 2: /*================= LRC selected as system clock*/ - SystemCoreClock = (uint32_t)(__LRC); - break; - - case 3: /*================= LOSC selected as system clock*/ - SystemCoreClock = (uint32_t)(__LOSC); - break; - - case 4: /*================= PLL selected as system clock*/ - pllmux = md_rcu_get_cfg_pllmul(RCU) + 1; - - if (pllmux >= 18) pllmux = 18; - - SystemCoreClock = (uint32_t)(PLL0Frequency * pllmux); - break; - - default: - SystemCoreClock = (uint32_t)(__HRC); - break; - } - - /* Core Frequency */ - if (md_rcu_get_cfg_hpre(RCU)) - SystemFrequency_SysClk = SystemCoreClock >> ((md_rcu_get_cfg_hpre(RCU) & 0x07) + 1); - else - SystemFrequency_SysClk = SystemCoreClock; - - /* AHB Frequency */ - SystemFrequency_AHBClk = SystemFrequency_SysClk; - - /* APB Frequency */ - if (md_rcu_get_cfg_ppre(RCU)) - SystemFrequency_APBClk = SystemFrequency_SysClk >> ((md_rcu_get_cfg_ppre(RCU) & 0x03) + 1); - else - SystemFrequency_APBClk = SystemFrequency_SysClk; - - - if (SystemFrequency_AHBClk / 1000000 > 72) - md_fc_set_con_wait(3); - else if (SystemFrequency_AHBClk / 1000000 > 48) - md_fc_set_con_wait(2); - else if (SystemFrequency_AHBClk / 1000000 > 24) - md_fc_set_con_wait(1); - else - md_fc_set_con_wait(0); -} - -void md_rcu_init_set(RCU_TypeDef *rcu, md_rcu_init_typedef *RCU_InitStruct) -{ - uint8_t pllmux; - - md_fc_set_con_wait(3); - - md_rcu_set_cfg_mpre(rcu, RCU_InitStruct->Mpre); - md_rcu_set_cfg_msw(rcu, RCU_InitStruct->Msw); - md_rcu_set_cfg_pllmul(rcu, (RCU_InitStruct->PllMul) - 1); - md_rcu_set_cfg_pllsrc(rcu, RCU_InitStruct->PllSrc); - md_rcu_set_cfg_hoscdiv(rcu, (RCU_InitStruct->HoscDiv) - 1); - md_rcu_set_cfg_ppre(rcu, RCU_InitStruct->Ppre); - md_rcu_set_cfg_hpre(rcu, RCU_InitStruct->Hpre); - md_rcu_set_cfg_sw(rcu, RCU_InitStruct->Sw); - - if(RCU_InitStruct->SysClock & RCU_CON_CSSON_MSK) - md_rcu_enable_con_csson(rcu); - else - md_rcu_disable_con_csson(rcu); - - if(RCU_InitStruct->SysClock & RCU_CON_PLL1ON_MSK) - md_rcu_enable_con_pll1on(rcu); - else - md_rcu_disable_con_pll1on(rcu); - - if(RCU_InitStruct->SysClock & RCU_CON_PLL0ON_MSK) - md_rcu_enable_con_pll0on(rcu); - else - md_rcu_disable_con_pll0on(rcu); - - if(RCU_InitStruct->SysClock & RCU_CON_LOSCON_MSK) - md_rcu_enable_con_loscon(rcu); - else - md_rcu_disable_con_loscon(rcu); - - if(RCU_InitStruct->SysClock & RCU_CON_LRCON_MSK) - md_rcu_enable_con_lrcon(rcu); - else - md_rcu_disable_con_lrcon(rcu); - - if(RCU_InitStruct->SysClock & RCU_CON_HOSCON_MSK) - md_rcu_enable_con_hoscon(rcu); - else - md_rcu_disable_con_hoscon(rcu); - - if(RCU_InitStruct->SysClock & RCU_CON_HRCON_MSK) - md_rcu_enable_con_hrcon(rcu); - else - md_rcu_disable_con_hrcon(rcu); - - md_rcu_set_cfg_ckcfg(rcu); - - /* while(md_rcu_get_con_hoscrdy(RCU)==0) {} */ - - /* while(md_rcu_get_con_pll0rdy(RCU)==0) {} */ - - - if (RCU->CON & RCU_CON_HRCON_MSK) /* if HRC enbale */ - while (md_rcu_get_con_hrcrdy(rcu) == 0); /* Wait for HRCRDY = 1 (HRC is ready)*/ - - - if (RCU->CON & RCU_CON_HOSCON_MSK) /* if HOSC enbale */ - while (md_rcu_get_con_hoscrdy(rcu) == 0); /* Wait for HOSCRDY = 1 (HOSC is ready)*/ - - - if (RCU->CON & RCU_CON_LRCON_MSK) /* if LRC enbale */ - while (md_rcu_get_con_lrcrdy(rcu) == 0); /* Wait for LRCRDY = 1 (LRC is ready)*/ - - - if (RCU->CON & RCU_CON_LOSCON_MSK) /* if LOSC enbale */ - while (md_rcu_get_con_loscrdy(rcu) == 0); /* Wait for LOSCRDY = 1 (LOSC is ready)*/ - - if (RCU->CON & RCU_CON_PLL0ON_MSK) /* if PLL enbale */ - while (md_rcu_get_con_pll0rdy(rcu) == 0); /* Wait for PLLRDY = 1 (PLL is ready)*/ - - - - /* PLL Reference Clock Source*/ - if (md_rcu_get_cfg_pllsrc(rcu)) - PLL0Frequency = (uint32_t)(__HOSC / (md_rcu_get_cfg_pllsrc(rcu) + 1)); - else - PLL0Frequency = (uint32_t)(__HRC); - - /* System Frequency */ - switch (md_rcu_get_cfg_sw(rcu)) /* System clock switch(SYSCLK) */ - { - case 0: /*================= HRC selected as system clock*/ - SystemCoreClock = (uint32_t)(__HRC); - break; - - case 1: /*================= HOSC selected as system clock*/ - SystemCoreClock = (uint32_t)(__HOSC); - break; - - case 2: /*================= LRC selected as system clock*/ - SystemCoreClock = (uint32_t)(__LRC); - break; - - case 3: /*================= LOSC selected as system clock*/ - SystemCoreClock = (uint32_t)(__LOSC); - break; - - case 4: /*================= PLL selected as system clock*/ - pllmux = md_rcu_get_cfg_pllmul(rcu) + 1; - - if (pllmux >= 18) pllmux = 18; - - SystemCoreClock = (uint32_t)(PLL0Frequency * pllmux); - break; - - default: - SystemCoreClock = (uint32_t)(__HRC); - break; - } - - /* Core Frequency */ - if (md_rcu_get_cfg_hpre(rcu)) - SystemFrequency_SysClk = SystemCoreClock >> ((md_rcu_get_cfg_hpre(rcu) & 0x07) + 1); - else - SystemFrequency_SysClk = SystemCoreClock; - - /* AHB Frequency */ - SystemFrequency_AHBClk = SystemFrequency_SysClk; - - /* APB Frequency */ - if (md_rcu_get_cfg_ppre(rcu)) - SystemFrequency_APBClk = SystemFrequency_SysClk >> ((md_rcu_get_cfg_ppre(rcu) & 0x03) + 1); - else - SystemFrequency_APBClk = SystemFrequency_SysClk; - - - if (SystemFrequency_AHBClk / 1000000 > 72) - md_fc_set_con_wait(3); - else if (SystemFrequency_AHBClk / 1000000 > 48) - md_fc_set_con_wait(2); - else if (SystemFrequency_AHBClk / 1000000 > 24) - md_fc_set_con_wait(1); - else - md_fc_set_con_wait(0); -} - - -/** - * @brief - * @param - * @retval None - */ -void md_rcu_pllreinit(uint8_t pllmul) -{ - md_rcu_set_cfg_pllmul(RCU, pllmul); - md_rcu_set_cfg_ckcfg(RCU); - - /* PLL Reference Clock Source */ - if (md_rcu_get_cfg_pllsrc(RCU)) - PLL0Frequency = (uint32_t)(__HOSC / (md_rcu_get_cfg_pllsrc(RCU) + 1)); - else - PLL0Frequency = (uint32_t)(__HRC); - - SystemCoreClock = (uint32_t)(PLL0Frequency * (pllmul + 1)); - - /* Core Frequency */ - if (md_rcu_get_cfg_hpre(RCU)) - SystemFrequency_SysClk = SystemCoreClock >> ((md_rcu_get_cfg_hpre(RCU) & 0x07) + 1); - else - SystemFrequency_SysClk = SystemCoreClock; - - /* AHB Frequency */ - SystemFrequency_AHBClk = SystemFrequency_SysClk; - - /* APB Frequency */ - if (md_rcu_get_cfg_ppre(RCU)) - SystemFrequency_APBClk = SystemFrequency_SysClk >> ((md_rcu_get_cfg_ppre(RCU) & 0x03) + 1); - else - SystemFrequency_APBClk = SystemFrequency_SysClk; - - md_fc_set_con_wait(3); - - if (SystemFrequency_AHBClk / 1000000 > 72) - md_fc_set_con_wait(3); - else if (SystemFrequency_AHBClk / 1000000 > 48) - md_fc_set_con_wait(2); - else if (SystemFrequency_AHBClk / 1000000 > 24) - md_fc_set_con_wait(1); - else - md_fc_set_con_wait(0); -} - -/** - * @} MD_RCU_PF_Init - */ - -/** - * @} MD_RCU_Public_Functions - */ - -/** - * @} RCU - */ - -/** - * @} Micro_Driver - */ - -/******************* (C) COPYRIGHT Eastsoft Microelectronics *****END OF FILE****/ diff --git a/bsp/essemi/es32f0271/libraries/ES32F027x_MD_StdPeriph_Driver/Source/md_spi.c b/bsp/essemi/es32f0271/libraries/ES32F027x_MD_StdPeriph_Driver/Source/md_spi.c deleted file mode 100644 index c29bb54be6..0000000000 --- a/bsp/essemi/es32f0271/libraries/ES32F027x_MD_StdPeriph_Driver/Source/md_spi.c +++ /dev/null @@ -1,108 +0,0 @@ -/** - ****************************************************************************** - * @file md_spi.c - * @brief ES32F0271 I2C Source File. - * - * @version V1.00.01 - * @date 4/12/2018 - * @author Eastsoft AE Team - * @note - * detailed description - * - * Copyright (C) 2018 Shanghai Eastsoft Microelectronics Co., Ltd. ALL rights reserved. - ******************************************************************************* - */ - -/* Includes -------------------------------------------------------------------*/ -#include "md_spi.h" -#include "md_rcu.h" -#include -#include "stdint.h" -/** @addtogroup Micro_Driver - * @{ - */ - -/* Private types --------------------------------------------------------------*/ -/* Private variables ----------------------------------------------------------*/ -/* Private constants ----------------------------------------------------------*/ -/* Private macros -------------------------------------------------------------*/ - -/** - * @brief Initialize the SPI registers according to the specified parameters in SPI_initStruct. - * @note The parameters in md_spi_init should be expected values. Otherwise, ERROR result will be returned. - * @param SPIx SPI Instance - * @param SPI_initStruct pointer to a @ref SPI_initStruct structure - * @retval An ErrorStatus enumeration value. (Return always SUCCESS) - */ -void md_spi_struct_init(md_spi_inittypedef *SPI_initStruct) -{ - SPI_initStruct->Mode = MD_SPI_MODE_MASTER; - SPI_initStruct->ClockPhase = MD_SPI_PHASE_1EDGE; - SPI_initStruct->ClockPolarity = MD_SPI_POLARITY_LOW; - SPI_initStruct->BaudRate = MD_SPI_BAUDRATEPRESCALER_DIV256; - SPI_initStruct->BitOrder = MD_SPI_MSB_FIRST; - SPI_initStruct->TransferDirection = MD_SPI_FULL_DUPLEX; - SPI_initStruct->DataWidth = MD_SPI_FRAME_FORMAT_8BIT; - SPI_initStruct->CRCCalculation = MD_SPI_CRCCALCULATION_DISABLE; - SPI_initStruct->CRCPoly = 0x7; - SPI_initStruct->NSS = MD_SPI_NSS_HARD; -} - -/** - * @brief Initialize the SPI registers according to the specified parameters in SPI_initStruct. - * @note The parameters in md_i2c_init should be expected values. Otherwise, ERROR result will be returned. - * @param SPIx SPI Instance - * @param SPI_initStruct pointer to a @ref SPI_initStruct structure - * @retval An ErrorStatus enumeration value. (Return always SUCCESS) - */ -ErrorStatus md_spi_init(SPI_TypeDef *SPIx, md_spi_inittypedef *SPI_InitStruct) -{ - ErrorStatus status = ERROR; - - md_spi_disable_con1_spien(SPIx); - - md_spi_set_con1_mstren(SPIx, SPI_InitStruct->Mode); - md_spi_set_con1_cpha(SPIx, SPI_InitStruct->ClockPhase); - md_spi_set_con1_cpol(SPIx, SPI_InitStruct->ClockPolarity); - md_spi_set_con1_baud(SPIx, SPI_InitStruct->BaudRate); - md_spi_set_con1_lsbfirst(SPIx, SPI_InitStruct->BitOrder); - md_spi_set_con1_bidimode(SPIx, SPI_InitStruct->TransferDirection); - md_spi_set_con1_ssout(SPIx, SPI_InitStruct->NSS); - md_spi_enable_con2_ssoe(SPIx); - - md_spi_enable_con1_spien(SPIx); - - status = SUCCESS; - - return status; -} - -/** - * @brief use to receive single one byte data. - * @note SPI Slave receive data - * @param SPIx SPI Instance - */ -uint8_t SPISSingleRd(SPI_TypeDef *SPIx) -{ - while (md_spi_is_active_flag_stat_rxe(SPIx)); - - return (md_spi_recv_data8(SPIx)); -} - - -/** - * @brief use to send single one byte data. - * @note SPI receive data - * @param SPIx SPI Instance - * @param data SPI send one byte data. - */ -void SPISingleWr(SPI_TypeDef *SPIx, uint8_t data) -{ - while (md_spi_is_active_flag_stat_txf(SPIx)); - - md_spi_send_data8(SPIx, data); -} - -/** - * @} Micro_Driver - */ diff --git a/bsp/essemi/es32f0271/libraries/ES32F027x_MD_StdPeriph_Driver/Source/md_tick.c b/bsp/essemi/es32f0271/libraries/ES32F027x_MD_StdPeriph_Driver/Source/md_tick.c deleted file mode 100644 index f1420c6eb3..0000000000 --- a/bsp/essemi/es32f0271/libraries/ES32F027x_MD_StdPeriph_Driver/Source/md_tick.c +++ /dev/null @@ -1,207 +0,0 @@ -/** - ****************************************************************************** - * @file md_tick.c - * @brief ES32F0271 TICK Source File. - * - * @version V1.00.01 - * @date day/mon/year - * @author Eastsoft AE Team - * @note - * detailed description - * - * Copyright (C) 2018 Shanghai Eastsoft Microelectronics Co., Ltd. ALL rights reserved. - * - ******************************************************************************* - */ - -/* Includes -------------------------------------------------------------------*/ -#include "md_rcu.h" -#include "md_tick.h" - -/** @addtogroup Micro_Driver - * @{ - */ - -#if defined (TICK) - -/** @addtogroup TICK TICK - * @brief TICK micro driver - * @{ - */ - -/* Private types --------------------------------------------------------------*/ -/* Private constants ----------------------------------------------------------*/ -/* Private macros -------------------------------------------------------------*/ - -/* Private function prototypes ------------------------------------------------*/ - -#define HDIVON 0 - -/* Private variables ----------------------------------------------------------*/ -/** @defgroup MD_TICK_Private_Variables TICK Private Variables - * @{ - */ -static uint32_t TICKms; -static uint32_t TICK100us; -static uint32_t TICK10us; - -/** - * @} MD_TICK_Private_Variables - */ -/* Public functions -----------------------------------------------------------*/ -/** @defgroup MD_TICK_Public_Functions TICK Public Functions - * @{ - */ - -/** - * @brief Tick Initialization - * @note This function set the maximun load and enable TICK counter - * @note This function also calculate ms, 100us ans 10us counter - * @param None - * @retval None - */ -void md_tick_init(void) -{ -#if HDIVON - HDIV->DIVIDEND = SystemFrequency_SysClk; - HDIV->DIVISOR = 1000; - TICKms = HDIV->QUOTIENT; - HDIV->DIVISOR = 10000; - TICK100us = HDIV->QUOTIENT; - HDIV->DIVISOR = 100000; - TICK10us = HDIV->QUOTIENT; -#else - TICKms = SystemFrequency_SysClk / 1000; - TICK100us = SystemFrequency_SysClk / 10000; - TICK10us = SystemFrequency_SysClk / 100000; -#endif - - md_tick_set_rvr_reload((1 << 24) - 1); /* Maximun ReLoad */ - md_tick_set_cvr_current(0); /* Reset CVR */ - md_tick_set_csr_clksource(1); /* MCU Clock */ - md_tick_enable_csr_enable(); /* Counter Enable */ -} - -/** - * @brief Retrive the TICK counter and converted to millisecond - * @param None - * @retval The ms value converted by TICK counter - */ -uint32_t md_tick_get_mscnt(void) -{ -#if HDIVON - HDIV->DIVIDEND = md_tick_get_cvr_current(); - HDIV->DIVISOR = TICKms; - return (HDIV->QUOTIENT); -#else - return (md_tick_get_cvr_current() / TICKms); -#endif -} - -/** - * @brief Retrive the TICK counter and converted to 100 microseconds - * @param None - * @retval The 100 microseconds value converted by TICK counter - */ -uint32_t md_tick_get_100uscnt(void) -{ -#if HDIVON - HDIV->DIVIDEND = md_tick_get_cvr_current(); - HDIV->DIVISOR = TICK100us; - return (HDIV->QUOTIENT); -#else - return (md_tick_get_cvr_current() / TICK100us); -#endif -} - -/** - * @brief Retrive the TICK counter and converted to 10 microseconds - * @param None - * @retval The 10 microseconds value converted by TICK counter - */ -uint32_t md_tick_get_10uscnt(void) -{ -#if HDIVON - HDIV->DIVIDEND = md_tick_get_cvr_current(); - HDIV->DIVISOR = TICK10us; - return (HDIV->QUOTIENT); -#else - return (md_tick_get_cvr_current() / TICK10us); -#endif -} - -/** - * @brief Delay based on milliseconds - * @param Unit The number of ms in one delay period - * @param msCnt The counter of delay period - * @etVal None - */ -void md_tick_waitms(uint8_t Unit, uint16_t msCnt) -{ - uint32_t mstime; - - mstime = (1 << 24) - (Unit * TICKms); - - while (msCnt--) - { - md_tick_set_cvr_current((1 << 24) - 1); /* Reset CVR */ - - while (md_tick_get_cvr_current() > mstime); - } -} - -/** - * @brief Delay based on 100 microseconds - * @param Unit The number of 100 microseconds in one delay period - * @param msCnt The counter of delay period - * @etVal None - */ -void md_tick_wait100us(uint16_t Unit, uint16_t usCnt) -{ - uint32_t ustime; - - ustime = (1 << 24) - (Unit * TICK100us); - - while (usCnt--) - { - md_tick_set_cvr_current((1 << 24) - 1); /* Reset CVR */ - - while (md_tick_get_cvr_current() > ustime); - } -} - -/** - * @brief Delay based on 10 microseconds - * @param Unit The number of 10 microseconds in one delay period - * @param msCnt The counter of delay period - * @etVal None - */ -void md_tick_wait10us(uint16_t Unit, uint16_t usCnt) -{ - uint32_t ustime; - - ustime = (1 << 24) - (Unit * TICK10us); - - while (usCnt--) - { - md_tick_set_cvr_current((1 << 24) - 1); /* Reset CVR */ - - while (md_tick_get_cvr_current() > ustime); - } -} - - -/** - * @} MD_TICK_Public_Functions - */ - -/** - * @} TICK - */ -#endif - -/** - * @} Micro_Driver - */ - -/******************* (C) COPYRIGHT Eastsoft Microelectronics *****END OF FILE****/ diff --git a/bsp/essemi/es32f0271/libraries/ES32F027x_MD_StdPeriph_Driver/Source/md_uart.c b/bsp/essemi/es32f0271/libraries/ES32F027x_MD_StdPeriph_Driver/Source/md_uart.c deleted file mode 100644 index 5ec9ccf3af..0000000000 --- a/bsp/essemi/es32f0271/libraries/ES32F027x_MD_StdPeriph_Driver/Source/md_uart.c +++ /dev/null @@ -1,127 +0,0 @@ -/** - ****************************************************************************** - * @file md_uart.c - * @brief ES32F0271 UART Source File. - * - * @version V1.00.01 - * @date 04/12/2018 - * @author Eastsoft AE Team - * @note UART Public Functions - * - * Copyright (C) 2018 Shanghai Eastsoft Microelectronics Co., Ltd. ALL rights reserved. - ******************************************************************************* - */ - -/* Includes -------------------------------------------------------------------*/ -#include "system_es32f027x.h" -#include "md_uart.h" - -/** @addtogroup Micro_Driver - * @{ - */ - -/** @defgroup UART UART - * @brief UART micro driver - * @{ - */ - -/* Private types --------------------------------------------------------------*/ -/* Private variables ----------------------------------------------------------*/ -/* Private constants ----------------------------------------------------------*/ -/* Private macros -------------------------------------------------------------*/ -/* Private function prototypes ------------------------------------------------*/ - -/* Public functions -----------------------------------------------------------*/ - -/** @defgroup UART_PUB_FUNC UART Public Functions - * @brief UART Public Functions - * @{ - */ -/** - * @brief Set UART1 baudrate. - * @param UARTx UART Instance. - * @param Baudrate - * @retval None. - */ -void md_uart_set_baudrate(UART_TypeDef *UARTx, uint32_t baudrate) -{ - uint32_t brr; - brr = ((SystemFrequency_APBClk + (baudrate >> 1)) / baudrate); - md_uart_set_brr(UARTx, brr); -} - -/** - * @brief UART Initialization - * @param UART Init Structure - * @retval None - */ -void md_uart_init(UART_TypeDef *UARTx, md_uart_init_typedef *UART_InitStruct) -{ - /* Check the UART_InitStruct */ - assert_param((UART_InitStruct != NULL)); - - md_uart_set_baudrate(UARTx, MD_UART_BAUDRATE_115200); - md_uart_disable_lcon_txen(UARTx); - md_uart_disable_lcon_rxen(UARTx); - md_uart_set_lcon_dls(UARTx, UART_InitStruct->DataWidth); - md_uart_set_lcon_stop(UARTx, UART_InitStruct->StopBits); - md_uart_set_lcon_ps(UARTx, UART_InitStruct->Parity); - md_uart_enable_lcon_pe(UARTx); - md_uart_set_fcon_tfrst(UARTx); - md_uart_set_fcon_rfrst(UARTx); - md_uart_enable_lcon_txen(UARTx); - md_uart_enable_lcon_rxen(UARTx); -} - -/** - * @brief UART1 send character - * @param Character - * @retval None - */ -void md_uart_send(UART_TypeDef *UARTx, uint8_t ch) -{ - while (md_uart_is_active_flag_stat_tffull(UARTx)); // Tx FIFO full - - md_uart_send_txbuf(UART1, ch); // Sent byte -} - -/** - * @brief UART1 receive character. - * @param UART_TypeDef *UARTx. - * @retval unsigned char. - */ -uint8_t md_uart_recv(UART_TypeDef *UARTx) -{ - while (md_uart_is_active_flag_stat_rfempty(UART1)); // Rx FIFO empty - - return (md_uart_get_rxbuf(UART1)); -} - -/** - * @brief Get UARTx baudrate. - * @param UART_TypeDef *UARTx. - * @retval Baudrate. - */ -uint32_t md_uart_get_baudrate(UART_TypeDef *UARTx) -{ - uint32_t brr, baudrate; - - brr = md_uart_get_brr(UARTx); - baudrate = SystemFrequency_APBClk / brr; - return baudrate; -} - - -/** - * @} UART_PUB_FUNC UART Public Functions - */ - -/** - * @} UART - */ - -/** - * @} Micro_Driver - */ - -/******************* (C) COPYRIGHT Eastsoft Microelectronics *****END OF FILE****/ diff --git a/bsp/essemi/es32f0271/libraries/ES32F027x_MD_StdPeriph_Driver/Source/md_usb.c b/bsp/essemi/es32f0271/libraries/ES32F027x_MD_StdPeriph_Driver/Source/md_usb.c deleted file mode 100644 index b3ae9ce6d5..0000000000 --- a/bsp/essemi/es32f0271/libraries/ES32F027x_MD_StdPeriph_Driver/Source/md_usb.c +++ /dev/null @@ -1,3804 +0,0 @@ -/** - ************************************************************************************** - * @file md_usb.c - * @brief USB Source File of MD Library. - * @data 03/12/2018 - * @author Eastsoft AE Team - * @note - * - * Copyright (C) 2018 Shanghai Eastsoft Microelectronics Co., Ltd. ALL rights reserved. - * - ************************************************************************************** - */ - -/* Incudes -------------------------------------------------------------------*/ -#include "es32f0271.h" -#include "stdint.h" -#include -#include "usblib\drivers\usb_lowlayer_api.h" - -/** @addtogroup Micro_Driver - * @{ - */ - -#if defined (USB) - -/** @defgroup USB USB - * @brief USB micro driver - * @{ - */ - -/* Private types --------------------------------------------------------------*/ -/* Private variables ----------------------------------------------------------*/ -/* Private constants ----------------------------------------------------------*/ -#define INTERRUPT_MASK_HOST 0x7e -#define INTERRUPT_MASK_DEV 0x6f - -/* Private macros -------------------------------------------------------------*/ -/* Private function prototypes ------------------------------------------------*/ - -/* Public functions -----------------------------------------------------------*/ -/** @addtogroup USB_MD_Public_Functions USB Public Functions - * @{ - */ - -/** @addtogroup USB_MD_PF_SYS USB Public System Functions - * @{ - */ - -/** - * @brief Mask all interrupts except NMI and Hardfault. - * @param None. - * @retval None. - */ -void md_usb_system_int_disable(void) -{ - __set_PRIMASK(1); -} - -/** - * @brief Enable all interrupts. - * @param None. - * @retval None. - */ -void md_usb_system_int_enable(void) -{ - __set_PRIMASK(0); -} - -/** - * @brief Reconfig USB. - * - * This config USB clock to xx MHz as the default configuration. - * If user want to change the clock,just redefine the - * md_usb_re_config() function. - * @param Device Chose device is in device mode or host mode. - * @retval None. - */ -__weak void md_usb_re_config(bool Device) -{ - // - // Config FIFO size of endpoint 0. - // No configuration required for ES32F0271. - // - - // - // For ES32F0271,full-speed is supported in device mode, - // Both full-speeed and low-speed is supported in host mode. - // - if (Device == true) - { - // - // DP pin pull up, in full-speed mode. - // - USB->DPDMCTRL |= (0X01 << USB_DPDMCTL_DPPUD_POSS); - - // - // Enable CID hardware control. - // - USB->SWCID &= ~USB_SWCID_CIDCTRL_MSK; - } - else - { - // - // DM\DP pin pull down, in host mode. - // Connect USN PHY power. - // - USB->DPDMCTRL = (0X02 << USB_DPDMCTL_DPPUD_POSS) | - (0X02 << USB_DPDMCTL_DMPUD_POSS) | - (USB_DPDMCTL_PHYPWREN_MSK); - // - // Enable CID hardware control. - // - USB->SWCID &= ~USB_SWCID_HOST_MSK; - - // - // Enable CID hardware control. - // - USB->SWCID &= ~USB_SWCID_CIDCTRL_MSK; - } -} - -/** - * @brief Delay ticks ms. - * @param ticks The delay ticks. - * @retval None. - */ -__weak void md_usb_system_delayms(uint32_t ticks) -{ - -} - -/** - * @brief Disable systic. - * @param None. - * @retval None. - */ -void md_usb_systic_disable(void) -{ - SysTick->CTRL &= (~SysTick_CTRL_ENABLE_Msk); -} - -/** - * @brief Reset colck of USB controller. - * @param None. - * @retval None. - */ -void md_usb_controller_reset(void) -{ - RCU->AHBRST |= RCU_AHBRST_USBEN_MSK; - RCU->AHBRST &= ~RCU_AHBRST_USBEN_MSK; -} - -/** - * @brief Enable colck of USB controller. - * @param None. - * @retval None. - */ -void md_usb_controller_enable(void) -{ - RCU->AHBEN |= RCU_AHBEN_USBEN_MSK; -} - -/** - * @brief Disable colck of USB controller. - * @param None. - * @retval None. - */ -void md_usb_controller_disable(void) -{ - RCU->AHBEN &= ~RCU_AHBEN_USBEN_MSK; -} - -/** - * @brief Enable phy colck of USB controller. - * - * This function enables clock of USB.To use USB,first, - * open its clock,then enable USB peripheral by clock - * clock manage peripheral. - * - * @param None. - * @retval None. - */ -void md_usb_clk_phy_enable(void) -{ - // - // Make sure the PLL1 has not been enabled. - // - if ((RCU->CON & RCU_CON_PLL1RDY_MSK) - && (RCU->CON & RCU_CON_PLL1ON_MSK)) - { - return; - } - - // - //Open PLL1 and wait it is ready. - // - RCU->CON |= RCU_CON_PLL1ON_MSK; - - while ((RCU->CON & RCU_CON_PLL1RDY_MSK) == 0); -} - -/** - * @brief Disable phy colck of USB controller. - * @param None. - * @retval None. - */ -void md_usb_clk_phy_disable(void) -{ - // - // Close PLL1. - // - RCU->CON &= ~RCU_CON_PLL1ON_MSK; -} - -/** - * @brief Get the USB interrupt number of NVIC. - * @param None. - * @retval None. - */ -uint32_t md_usb_nvic_number_get(void) -{ - return (uint32_t)USB_IRQn; -} - -/** - * @brief Config the USB interrupt of NVIC. - * @note The default priority is 1. - * @param None. - * @retval None. - */ -__weak void md_usb_nvic_config(uint32_t NvicNum) -{ - NVIC_SetPriority((IRQn_Type)NvicNum, 1); -} - -/** - * @brief Enable the USB interrupt of NVIC. - * @param None. - * @retval None. - */ -void md_usb_nvic_enable(void) -{ - NVIC_EnableIRQ((IRQn_Type)USB_IRQn); -} - -/** - * @brief Disable the USB interrupt of NVIC. - * @param None. - * @retval None. - */ -void md_usb_nvic_disable(void) -{ - NVIC_DisableIRQ((IRQn_Type)USB_IRQn); -} - -/** - * @} USB_MD_PF_SYS - */ - -/** @addtogroup USB_MD_PF_BASIC USB Public Basic Functions - * @{ - */ - -/** - * @brief Handles the USB bus reset condition. - * - * When this function is called with the \e bStart parameter set to \b true, - * this function causes the start of a reset condition on the USB bus. - * The caller must then delay at least 20ms before calling this function - * again with the \e bStart parameter set to \b false. - * - * @param bStart specifies whether to start or stop signaling reset on the USB - * bus. - * @note This function must only be called in host mode. - * @retval None. - */ -void md_usb_hos_reset(bool bStart) -{ - // - // Send a reset signal to the bus. - // - if (bStart) - { - USB->POWER |= USB_POWER_RESET_MSK; - } - else - { - USB->POWER &= ~USB_POWER_RESET_MSK; - } -} - -/** - * @brief Handles the USB bus resume condition. - * - * When in device mode, this function brings the USB controller out of the - * suspend state. This call must first be made with the \e bStart parameter - * set to \b true to start resume signaling. The device application must - * then delay at least 10ms but not more than 15ms before calling this - * function with the \e bStart parameter set to \b false. - * - * When in host mode, this function signals devices to leave the suspend - * state. This call must first be made with the \e bStart parameter set to - * \b true to start resume signaling. The host application must then delay - * at least 20ms before calling this function with the \e bStart parameter set - * to \b false. This action causes the controller to complete the resume - * signaling on the USB bus. - * - * @param bStart specifies if the USB controller is entering or leaving the - * resume signaling state. - * @note This function must only be called in host mode. - * @retval None. - */ -void md_usb_hos_resume(bool bStart) -{ - // - // Send a resume signal to the bus. - // - if (bStart) - { - USB->POWER |= USB_POWER_RESUME_MSK; - } - else - { - USB->POWER &= ~USB_POWER_RESUME_MSK; - } -} - -/** - * @brief Puts the USB bus in a suspended state. - * - * When used in host mode, this function puts the USB bus in the suspended - * state. - * - * @note This function must only be called in host mode. - * @retval Returns one of the following: \b USB_LOW_SPEED, \b USB_FULL_SPEED, - * \b USB_HIGH_SPEED, or \b USB_UNDEF_SPEED. - */ -void md_usb_hos_suspend(void) -{ - // - // Send the suspend signaling to the USB bus. - // - USB->POWER |= USB_POWER_SUSPEND_MSK; -} - -/** - * @brief Issues a request for a status IN transaction on endpoint zero. - * - * This function is used to cause a request for a status IN transaction from - * a device on endpoint zero. This function can only be used with endpoint - * zero as that is the only control endpoint that supports this ability. This - * function is used to complete the last phase of a control transaction to a - * device and an interrupt is signaled when the status packet has been - * received. - * - * @note This function must only be called in host mode. - * @retval None. - */ -void md_usb_hos_request_status(void) -{ - // - // Set the request for a status IN transaction. - // - USB->CSR0L_TXCSRL |= USB_CSR0L_TXCSRL_REQPKT_MSK | USB_CSR0L_TXCSRL_STATUSPKT_MSK; -} - -/** - * @brief Schedules a request for an IN transaction on an endpoint in host mode. - * - * This function schedules a request for an IN transaction. When the USB - * device being communicated with responds with the data, the data can be - * retrieved by calling md_usb_hosdev_endpoint_data_get() or via a DMA - * transfer. - * - * @note This function must only be called in host mode and only for IN - * endpoints. - * @param ui32Endpoint is the endpoint to access. - * @retval None. - */ -void md_usb_hos_request_in(uint32_t ui32Endpoint) -{ - // - //Chose endpoint. - // - USB->INDEX = (uint8_t)USBEPToIndex(ui32Endpoint); - - if (ui32Endpoint == USB_EP_0) - { - // - // Set the request for an IN transaction. - // - USB->CSR0L_TXCSRL |= USB_CSR0L_TXCSRL_REQPKT_MSK; - } - else - { - // - // Set the request for an IN transaction. - // - USB->RXCSR1 |= USB_RXCSRL_REQPKT_MSK; - } -} - -/** - * @brief Clears a scheduled IN transaction for an endpoint in host mode. - * - * This function clears a previously scheduled IN transaction if it is still - * pending. This function is used to safely disable any scheduled IN - * transactions if the endpoint specified by \e ui32Endpoint is reconfigured - * for communications with other devices. - * - * @note This function must only be called in host mode and only for IN - * endpoints. - * @param ui32Endpoint is the endpoint to access. - * @retval None. - */ -void md_usb_hos_request_in_clear(uint32_t ui32Endpoint) -{ - // - //Chose endpoint. - // - USB->INDEX = (uint8_t)USBEPToIndex(ui32Endpoint); - - // - // Set the request for an IN transaction. - // For es32f0271,setup packet is only supported by endpoint0. - // - USB->CSR0L_TXCSRL &= ~USB_CSR0L_TXCSRL_REQPKT_MSK; -} - -/** - * @brief Returns the current speed of the USB device connected. - * - * This function returns the current speed of the USB bus in host mode. - * - * @note This function must only be called in host mode. - * @retval Returns one of the following: \b USB_LOW_SPEED, \b USB_FULL_SPEED, - * \b USB_HIGH_SPEED, or \b USB_UNDEF_SPEED. - */ -uint32_t md_usb_hos_speed_get(void) -{ - // - // If the Full Speed device bit is set, then this is a full speed device. - // - if (USB->DEVCTRL & USB_DEVCTRL_FSDEV_MSK) - { - return (USB_FULL_SPEED); - } - - // - // If the Low Speed device bit is set, then this is a low speed device. - // - if (USB->DEVCTRL & USB_DEVCTRL_LSDEV_MSK) - { - return (USB_LOW_SPEED); - } - - // - // The device speed is not known. - // - return (USB_UNDEF_SPEED); -} - -/** - * @brief Gets the current functional device address for an endpoint. - * - * This function returns the current functional address that an endpoint is - * using to communicate with a device. The \e ui32Flags parameter determines - * if the IN or OUT endpoint's device address is returned. - * - * @param ui32Endpoint is the endpoint to access. - * @param ui32Flags determines if this is an IN or an OUT endpoint. - * @note This function must only be called in host mode. - * @retval Returns the current function address being used by an endpoint. - */ -uint32_t md_usb_hos_addr_get(uint32_t ui32Endpoint, uint32_t ui32Flags) -{ - // - //Chose endpoint. - // - USB->INDEX = (uint8_t)USBEPToIndex(ui32Endpoint); - - // - // Because es32f0271 can not read device function address, - // the return value can always be 0. - // - - // - // See if the transmit or receive address is returned. - // - if (ui32Flags & USB_EP_HOST_OUT) - { - // - // Return this endpoint's transmit address. - // - return (USB->FADDR); - } - else - { - // - // Return this endpoint's receive address. - // - return (USB->FADDR); - } -} - -/** - * @brief Sets the functional address for the device that is connected to an - * endpoint in host mode. - * - * This function configures the functional address for a device that is using - * this endpoint for communication. This \e ui32Addr parameter is the address - * of the target device that this endpoint is communicating with. The - * \e ui32Flags parameter indicates if the IN or OUT endpoint is set. - * - * @param ui32Endpoint is the endpoint to access. - * @param ui32Flags determines if this is an IN or an OUT endpoint. - * @param ui32Addr is the functional address for the controller to use for - * this endpoint. - * @note This function must only be called in host mode. - * @retval None. - */ -void md_usb_hos_addr_set(uint32_t ui32Endpoint, - uint32_t ui32Addr, uint32_t ui32Flags) -{ - // - //Chose endpoint. - // - -// USB->INDEX = (uint8_t)USBEPToIndex(ui32Endpoint); - - // - // See if the transmit or receive address is set. - // - if (ui32Flags & USB_EP_HOST_OUT) - { - // - // Set the transmit address. - // - USB->FADDR = ui32Addr; - } - else - { - // - // Set the receive address. - // - USB->FADDR = ui32Addr; - } -} - -/** - * @brief Gets the current device hub address for this endpoint. - * - * This function returns the current hub address that an endpoint is using - * to communicate with a device. The \e ui32Flags parameter determines if the - * device address for the IN or OUT endpoint is returned. - * - * @param ui32Endpoint is the endpoint to access. - * @param ui32Flags determines if this is an IN or an OUT endpoint. - * @note This function must only be called in host mode. - * @retval None. - */ -uint32_t md_usb_hos_hub_addr_get(uint32_t ui32Endpoint, uint32_t ui32Flags) -{ - // - // es32f0271 does not support - // - return 0; -} - -/** - * @brief Sets the hub address for the device that is connected to an endpoint. - * - * This function configures the hub address for a device that is using this - * endpoint for communication. The \e ui32Flags parameter determines if the - * device address for the IN or the OUT endpoint is configured by this call - * and sets the speed of the downstream device. Valid values are one of - * \b USB_EP_HOST_OUT or \b USB_EP_HOST_IN optionally ORed with - * \b USB_EP_SPEED_LOW. - * - * @param ui32Endpoint is the endpoint to access. - * @param ui32Flags determines if this is an IN or an OUT endpoint. - * @param ui32Addr is the hub address and port for the device using this - * endpoint. The hub address must be defined in bits 0 through 6 with the - * port number in bits 8 through 14. - * @note This function must only be called in host mode. - * @retval None. - */ -void md_usb_hos_hub_addr_set(uint32_t ui32Endpoint, - uint32_t ui32Addr, uint32_t ui32Flags) -{ - // - // es32f0271 does not support - // -} - -/** - * @brief Get USB address. - * @param None. - * @retval USB address. - */ -uint8_t md_usb_dev_addr_get(void) -{ - return (USB->FADDR); -} - -/** - * @brief Set USB address. - * @param ui8Address USB address. - * @retval None. - */ -void md_usb_dev_addr_set(uint8_t ui8Address) -{ - USB->FADDR = ui8Address; -} - -/** - * @brief USB soft connect. - * @param None. - * @retval None. - */ -void md_usb_dev_connect(void) -{ - // - // Enable connection to the USB bus. - // - USB->DPDMCTRL |= USB_DPDMCTL_PHYPWREN_MSK; -} - -/** - * @brief USB soft disconnect. - * @param None. - * @retval None. - */ -void md_usb_dev_disconnect(void) -{ - // - // Disable connection to the USB bus. - // - USB->DPDMCTRL &= ~USB_DPDMCTL_PHYPWREN_MSK; -} - -/** - * @brief Returns the current speed of the USB device connected. - * - * This function returns the current speed of the USB bus in device mode. - * - * @note This function must only be called in device mode. - * @retval Returns one of the following: \b USB_LOW_SPEED, \b USB_FULL_SPEED, - * \b USB_HIGH_SPEED, or \b USB_UNDEF_SPEED. - */ -uint32_t md_usb_dev_speed_get(void) -{ - if (USB->DPDMCTRL & USB_DPDMCTL_DPPUD_MSK) - return USB_FULL_SPEED; - else if (USB->DPDMCTRL & USB_DPDMCTL_DMPUD_MSK) - return USB_LOW_SPEED; - - return USB_UNDEF_SPEED; -} - -/** - * @brief Gets the current frame number. - * - * This function returns the last frame number received. - * - * @param None. - * @retval The last frame number received. - */ -uint32_t md_usb_hosdev_frame_get(void) -{ - uint8_t temp = USB->FRAME1 & 0xff; - return (temp | (uint32_t)((USB->FRAME2 & 0x07) << 8)); -} - -/** - * @brief Disables control interrupts on a specified USB controller. - * - * This function disables the control interrupts for the USB controller - * specified by the \e ui32Base parameter. The \e ui32Flags parameter - * specifies which control interrupts to disable. The flags passed in the - * \e ui32Flags parameters must be the definitions that start with - * \b USB_INTCTRL_* and not any other \b USB_INT flags. - * - * @param ui32IntFlags specifies which control interrupts to disable. - * @retval None. - */ -void md_usb_hosdev_int_disable(uint32_t ui32IntFlags) -{ - // - // Check the arguments. - // - assert_param((ui32IntFlags & ~(USB_INTCTRL_ALL)) == 0); - - // - // If any general interrupts were disabled then write the general interrupt - // settings out to the hardware. - // - if (ui32IntFlags & USB_INTCTRL_STATUS) - { - USB->IDR &= ~(ui32IntFlags & USB_INTCTRL_STATUS); - } -} - -/** - * @brief Enables control interrupts on a specified USB controller. - * - * This function Enables the control interrupts for the USB controller - * specified by the \e ui32Base parameter. The \e ui32Flags parameter - * specifies which control interrupts to disable. The flags passed in the - * \e ui32Flags parameters must be the definitions that start with - * \b USB_INTCTRL_* and not any other \b USB_INT flags. - * - * @param ui32IntFlags specifies which control interrupts to Enable. - * @retval None. - */ -void md_usb_hosdev_int_enable(uint32_t ui32IntFlags) -{ - // - // Check the arguments. - // - assert_param((ui32IntFlags & ~(USB_INTCTRL_ALL)) == 0); - - // - // If any general interrupts were disabled then write the general interrupt - // settings out to the hardware. - // - if (ui32IntFlags & USB_INTCTRL_STATUS) - { - USB->IER |= ui32IntFlags & USB_INTCTRL_STATUS; - } -} - -/** - * @brief Returns the control interrupt status on a specified USB controller. - * - * This function reads control interrupt status for a USB controller. This - * call returns the current status for control interrupts only, the endpoint - * interrupt status is retrieved by calling md_usb_hosdev_endpoint_int_status(). - * The bit values returned are compared against the \b USB_INTCTRL_* values. - * - * The following are the meanings of all \b USB_INCTRL_ flags and the modes - * for which they are valid. These values apply to any calls to - * md_usb_hosdev_int_status(), md_usb_hosdev_int_enable(), - * and md_usb_hosdev_int_disable(). - * Some of these flags are only valid in the following modes as indicated in - * the parentheses: Host, Device, and OTG. - * - * - \b USB_INTCTRL_ALL - A full mask of all control interrupt sources. - * - \b USB_INTCTRL_VBUS_ERR - A VBUS error has occurred (Host Only). - * - \b USB_INTCTRL_SESSION - Session Start Detected on A-side of cable - * (OTG Only). - * - \b USB_INTCTRL_SESSION_END - Session End Detected (Device Only) - * - \b USB_INTCTRL_DISCONNECT - Device Disconnect Detected (Host Only) - * - \b USB_INTCTRL_CONNECT - Device Connect Detected (Host Only) - * - \b USB_INTCTRL_SOF - Start of Frame Detected. - * - \b USB_INTCTRL_BABBLE - USB controller detected a device signaling past - * the end of a frame (Host Only) - * - \b USB_INTCTRL_RESET - Reset signaling detected by device (Device Only) - * - \b USB_INTCTRL_RESUME - Resume signaling detected. - * - \b USB_INTCTRL_SUSPEND - Suspend signaling detected by device (Device - * Only) - * - \b USB_INTCTRL_MODE_DETECT - OTG cable mode detection has completed - * (OTG Only) - * - \b USB_INTCTRL_POWER_FAULT - Power Fault detected (Host Only) - * - * @param ui32IntFlags specifies which control interrupts to Enable. - * @note This call clears the source of all of the control status interrupts. - * @retval Returns the status of the control interrupts for a USB controller. - */ -uint32_t md_usb_hosdev_int_status(void) -{ - uint32_t ui32Status; - - // - // Get the general interrupt status, these bits go into the upper 8 bits - // of the returned value. - // - ui32Status = USB->RIF & 0x7F; - - // - // Clear all the general interrupt status. - // - USB->ICR = 0xff; - - // - // Return the combined interrupt status. - // - return (ui32Status); -} - -/** - * @brief Returns the current operating mode of the controller. - * - * This function returns the current operating mode on USB controllers with - * OTG or Dual mode functionality. - * - * For OTG controllers: - * - * The function returns one of the following values on OTG controllers: - * - * \b USB_OTG_MODE_ASIDE_HOST indicates that the controller is in host mode - * on the A-side of the cable. - * - * \b USB_OTG_MODE_ASIDE_DEV indicates that the controller is in device mode - * on the A-side of the cable. - * - * \b USB_OTG_MODE_BSIDE_HOST indicates that the controller is in host mode - * on the B-side of the cable. - * - * \b USB_OTG_MODE_BSIDE_DEV indicates that the controller is in device mode - * on the B-side of the cable. If an OTG session request is started with no - * cable in place, this mode is the default. - * - * \b USB_OTG_MODE_NONE indicates that the controller is not attempting to - * determine its role in the system. - * - * For Dual Mode controllers: - * - * The function returns one of the following values: - * - * \b USB_DUAL_MODE_HOST indicates that the controller is acting as a host. - * - * \b USB_DUAL_MODE_DEVICE indicates that the controller acting as a device. - * - * \b USB_DUAL_MODE_NONE indicates that the controller is not active as - * either a host or device. - * - * @param None. - * @retval Returns \b USB_OTG_MODE_ASIDE_HOST, \b USB_OTG_MODE_ASIDE_DEV, - * \b USB_OTG_MODE_BSIDE_HOST, \b USB_OTG_MODE_BSIDE_DEV, - * \b USB_OTG_MODE_NONE, \b USB_DUAL_MODE_HOST, \b USB_DUAL_MODE_DEVICE, or - * \b USB_DUAL_MODE_NONE. - */ -uint32_t md_usb_hosdev_mode_get(void) -{ - // - // It will not be called for es32f0271,because OTG is not supported. - // - // Checks the current mode in the USB_O_DEVCTL and returns the current - // mode. - // - // USB_OTG_MODE_ASIDE_HOST: USB_DEVCTL_HOST | USB_DEVCTL_SESSION - // USB_OTG_MODE_ASIDE_DEV: USB_DEVCTL_SESSION - // USB_OTG_MODE_BSIDE_HOST: USB_DEVCTL_DEV | USB_DEVCTL_SESSION | - // USB_DEVCTL_HOST - // USB_OTG_MODE_BSIDE_DEV: USB_DEVCTL_DEV | USB_DEVCTL_SESSION - // USB_OTG_MODE_NONE: USB_DEVCTL_DEV - // - return (USB->DEVCTRL & (USB_DEVCTRL_HOST_MSK | USB_DEVCTRL_SESSION_MSK)); -} - -/** - * @brief Starts or ends a session. - * - * This function is used in OTG mode to start a session request or end a - * session. If the \e bStart parameter is set to \b true, then this function - * starts a session and if it is \b false it ends a session. - * - * @param bStart specifies if this call starts or ends a session. - * @retval None. - */ -void md_usb_otg_session_request(bool bStart) -{ - // - // Start or end the session as directed. - // - if (bStart) - { - USB->DEVCTRL |= USB_DEVCTRL_SESSION_MSK; - } - else - { - USB->DEVCTRL &= ~USB_DEVCTRL_SESSION_MSK; - } -} - -/** - * @brief Change the mode of the USB controller to host. - * - * This function changes the mode of the USB controller to host mode. - * - * @note This function must only be called on microcontrollers that support - * OTG operation. - * @param None. - * @retval None. - */ -void md_usb_force_host_mode(void) -{ - unsigned int i; - // - // Force host mode. - // - USB->SWCID &= ~USB_SWCID_HOST_MSK; - USB->SWCID |= USB_SWCID_CIDCTRL_MSK; - USB->DEVCTRL = USB_DEVCTRL_HOSTREQ_MSK; - - i = 20; - - while ((!(USB->DEVCTRL & USB_DEVCTRL_HOST_MSK)) && (i != 0)) - { - i--; - } -} - -/** - * @brief Change the mode of the USB controller to device. - * - * This function changes the mode of the USB controller to device mode. - * - * @note This function must only be called on microcontrollers that support - * OTG operation. - * @param None. - * @retval None. - */ -void md_usb_force_device_mode(void) -{ - // - // Force mode in OTG parts that support forcing USB controller mode. - // This bit is not writable in USB controllers that do not support - // forcing the mode. Not setting the USB_GPCS_DEVMOD bit makes this a - // force of device mode. - // - USB->SWCID |= USB_SWCID_HOST_MSK; - USB->SWCID |= USB_SWCID_CIDCTRL_MSK; -} - -/** - * @brief Change the mode of the USB controller to OTG. - * - * This function changes the mode of the USB controller to OTG mode. - * - * @note This function must only be called on microcontrollers that support - * OTG operation. - * @param None. - * @retval None. - */ -void md_usb_force_otg_mode(void) -{ - // - // Force mode in OTG parts that support forcing USB controller mode. - // This bit is not writable in USB controllers that do not support - // forcing the mode. Not setting the USB_GPCS_DEVMOD bit makes this a - // force of OTG mode. - // - USB->SWCID |= USB_SWCID_HOST_MSK; - USB->SWCID &= ~USB_SWCID_CIDCTRL_MSK; -} - -/** - * @brief Change the operating mode of the USB controller. - * - * This function changes the operating modes of the USB controller. When - * operating in full OTG mode, the USB controller uses the VBUS and ID pins to - * detect mode and voltage changes. While these pins are primarily used in - * OTG mode, they can also affect the operation of host and device modes. In - * device mode, the USB controller can be configured to monitor or ignore - * VBUS. Monitoring VBUS allows the controller to determine if it has been - * disconnected from the host. In host mode, the USB controller uses the - * VBUS pin to detect loss of VBUS caused by excessive power draw due to a - * drop in the VBUS voltage. This call takes the place of - * md_usb_force_host_mode(),md_usb_force_device_mode(), - * and md_usb_force_otg_mode(). - * The \e ui32Mode value should be one of the following values: - * - * - \b USB_MODE_OTG enables operating in full OTG mode, VBUS and ID are - * used by the controller. - * - \b USB_MODE_HOST enables operating only as a host with no monitoring of - * VBUS or ID pins. - * - \b USB_MODE_HOST_VBUS enables operating only as a host with monitoring of - * VBUS pin. This configuration enables detection of VBUS droop while still - * forcing host mode. - * - \b USB_MODE_DEVICE enables operating only as a device with no monitoring - * of VBUS or ID pins. - * - \b USB_MODE_DEVICE_VBUS enables operating only as a device with - * monitoring of VBUS pin. This configuration enables disconnect detection - * while still forcing device mode. - * - * @note Some of the options above are not available on some ES32 devices. - * Please check the data sheet to determine if the USB controller supports a - * particular mode. - * @param ui32Mode specifies the operating mode of the USB OTG pins. - * @retval None. - */ -void md_usb_mode_config(uint32_t ui32Mode) -{ - // - // It is not supported by es32f0271. - // -} - -/** - * @} USB_MD_PF_BASIC - */ - -/** @addtogroup USB_MD_PF_ENDPOINT USB Public Endpoint Functions - * @{ - */ - -/** - * @brief Sets the base configuration for a host endpoint. - * - * This function sets the basic configuration for the transmit or receive - * portion of an endpoint in host mode. The \e ui32Flags parameter determines - * some of the configuration while the other parameters provide the rest. The - * \e ui32Flags parameter determines whether this is an IN endpoint - * (\b USB_EP_HOST_IN or \b USB_EP_DEV_IN) or an OUT endpoint - * (\b USB_EP_HOST_OUT or \b USB_EP_DEV_OUT), whether this is a Full speed - * endpoint (\b USB_EP_SPEED_FULL) or a Low speed endpoint - * (\b USB_EP_SPEED_LOW). - * - * The \b USB_EP_MODE_ flags control the type of the endpoint. - * - \b USB_EP_MODE_CTRL is a control endpoint. - * - \b USB_EP_MODE_ISOC is an isochronous endpoint. - * - \b USB_EP_MODE_BULK is a bulk endpoint. - * - \b USB_EP_MODE_INT is an interrupt endpoint. - * - * The \e ui32NAKPollInterval parameter has different meanings based on the - * \b USB_EP_MODE value and whether or not this call is being made for - * endpoint zero or another endpoint. For endpoint zero or any Bulk - * endpoints, this value always indicates the number of frames to allow a - * device to NAK before considering it a timeout. If this endpoint is an - * isochronous or interrupt endpoint, this value is the polling interval for - * this endpoint. - * - * For interrupt endpoints, the polling interval is the number of frames - * between interrupt IN requests to an endpoint and has a range of 1 to 255. - * For isochronous endpoints this value represents a polling interval of - * 2 ^ (\e ui32NAKPollInterval - 1) frames. When used as a NAK timeout, the - * \e ui32NAKPollInterval value specifies 2 ^ (\e ui32NAKPollInterval - 1) - * frames before issuing a time out. - * - * There are two special time out values that can be specified when setting - * the \e ui32NAKPollInterval value. The first is \b MAX_NAK_LIMIT, which is - * the maximum value that can be passed in this variable. The other is - * \b DISABLE_NAK_LIMIT, which indicates that there is no limit on the - * number of NAKs. - * - * The \b USB_EP_DMA_MODE_ flags determine the type of DMA access to the - * endpoint data FIFOs. The choice of the DMA mode depends on how the DMA - * controller is configured and how it is being used. See the ``Using USB - * with the DMA Controller'' or the ''Using the integrated USB DMA - * Controller'' section for more information on DMA configuration depending - * on the type of DMA that is supported by the USB controller. - * - * When configuring the OUT portion of an endpoint, the \b USB_EP_AUTO_SET bit - * is specified to cause the transmission of data on the USB bus to start - * as soon as the number of bytes specified by \e ui32MaxPayload has been - * written into the OUT FIFO for this endpoint. - * - * When configuring the IN portion of an endpoint, the \b USB_EP_AUTO_REQUEST - * bit can be specified to trigger the request for more data once the FIFO has - * been drained enough to fit \e ui32MaxPayload bytes. The - * \b USB_EP_AUTO_CLEAR bit can be used to clear the data packet ready flag - * automatically once the data has been read from the FIFO. If this option is - * not used, this flag must be manually cleared via a call to - * md_usb_dev_endpoint_status_clear() or md_usb_hos_endpoint_status_clear(). - * - * For interrupt endpoints in low or full speed mode, the polling interval - * (\e ui32NAKPollInterval) is the number of frames between interrupt IN - * requests to an endpoint and has a range of 1 to 255. For interrupt - * endpoints in high speed mode the polling interval is - * 2 ^ (\e ui32NAKPollInterval - 1) microframes between interrupt IN requests - * to an endpoint and has a range of 1 to 16. - * @param ui32Endpoint is the endpoint to access. - * @param ui32Flags are the status bits that are cleared. - * @param ui32MaxPacketSize is the maximum payload for this endpoint. - * @param ui32NAKPollInterval is the either the NAK timeout limit or the - * polling interval, depending on the type of endpoint. - * @param ui32TargetEndpoint is the endpoint that the host endpoint is - * targeting. - * @param ui32Flags are used to configure other endpoint settings. - * @note This function must only be called in host mode. - * @retval None. - */ -void md_usb_hos_endpoint_config_set(uint32_t ui32Endpoint, - uint32_t ui32MaxPacketSize, - uint32_t ui32NAKPollInterval, - uint32_t ui32TargetEndpoint, - uint32_t ui32Flags) -{ - uint32_t ui32Register; - - // - //Chose endpoint. - // - USB->INDEX = (uint8_t)USBEPToIndex(ui32Endpoint); - - // - // Endpoint zero is configured differently than the other endpoints, so see - // if this is endpoint zero. - // - if (ui32Endpoint == USB_EP_0) - { - // - // Set the NAK timeout. - // - USB->NAKLIMIT0_TXINTERVAL = (uint8_t)ui32NAKPollInterval; - - // - // Set the transfer type information. - // - - // - // Set the speed of this endpoint. - // - if (ui32Flags & USB_EP_SPEED_HIGH) - { - // - // es32f0271 does not support high sepeed - // - } - else if (ui32Flags & USB_EP_SPEED_FULL) - { - } - else - { - } - } - else - { - // - // Start with the target endpoint. - // - ui32Register = ui32TargetEndpoint; - - // - // Set the speed for the device using this endpoint. - // - if (ui32Flags & USB_EP_SPEED_HIGH) - { - // - // es32f0271 does not support high sepeed - // - } - else if (ui32Flags & USB_EP_SPEED_FULL) - { - - } - else - { - - } - - // - // Set the protocol for the device using this endpoint. - // - switch (ui32Flags & USB_EP_MODE_MASK) - { - // - // The bulk protocol is being used. - // - case USB_EP_MODE_BULK: - { - ui32Register |= 0x20; - break; - } - - // - // The isochronous protocol is being used. - // - case USB_EP_MODE_ISOC: - { - ui32Register |= 0x10; - break; - } - - // - // The interrupt protocol is being used. - // - case USB_EP_MODE_INT: - { - ui32Register |= 0x30; - break; - } - - // - // The control protocol is being used. - // - case USB_EP_MODE_CTRL: - { - ui32Register |= 0x00; - break; - } - } - - // - // See if the transmit or receive endpoint is being configured. - // - if (ui32Flags & USB_EP_HOST_OUT) - { - // - // Set the transfer type information. - // - USB->TXTYPE = ui32Register; - - // - // Set the NAK timeout or polling interval. - // - USB->NAKLIMIT0_TXINTERVAL = ui32NAKPollInterval; - - // - // Set the Maximum Payload per transaction. - // - USB->TXMAXP = ui32MaxPacketSize; - - // - // Set the transmit control value to zero. - // - ui32Register = 0; - - // - // Allow auto setting of TxPktRdy when max packet size has been - // loaded into the FIFO. - // - if (ui32Flags & USB_EP_AUTO_SET) - { - ui32Register |= USB_CSR0H_TXCSRH_AUTOSET_MSK; - } - -// // -// // Configure the DMA Mode. -// // -// if(ui32Flags & USB_EP_DMA_MODE_1) -// { -// ui32Register |= USB_TXCSRH1_DMAEN | USB_TXCSRH1_DMAMOD; -// } -// else if(ui32Flags & USB_EP_DMA_MODE_0) -// { -// ui32Register |= USB_TXCSRH1_DMAEN; -// } - - // - // Write out the transmit control value. - // - USB->CSR0H_TXCSRH = (uint8_t)ui32Register; - } - else - { - // - // Set the transfer type information. - // - USB->RXTYPE = ui32Register; - - // - // Set the NAK timeout or polling interval. - // - USB->RXINTERVAL = ui32NAKPollInterval; - - // - // Set the Maximum Payload per transaction. - // - USB->RXMAXP = ui32MaxPacketSize; - - // - // Set the receive control value to zero. - // - ui32Register = 0; - - // - // Allow auto clearing of RxPktRdy when packet of size max packet - // has been unloaded from the FIFO. - // - if (ui32Flags & USB_EP_AUTO_CLEAR) - { - ui32Register |= USB_RXCSRH_AUTOCLR_MSK; - } - - // - // Allow auto generation of DMA requests. - // - if (ui32Flags & USB_EP_AUTO_REQUEST) - { - ui32Register |= USB_RXCSRH_AUTOREQ_MSK; - } - -// // -// // Configure the DMA Mode. -// // -// if(ui32Flags & USB_EP_DMA_MODE_1) -// { -// ui32Register |= USB_RXCSRH1_DMAEN | USB_RXCSRH1_DMAMOD; -// } -// else if(ui32Flags & USB_EP_DMA_MODE_0) -// { -// ui32Register |= USB_RXCSRH1_DMAEN; -// } - - // - // Write out the receive control value. - // - USB->RXCSR2 = (uint8_t)ui32Register; - - -// USB->RXFIFO1=0x18; //Start Address=0x18 -// USB->RXFIFO2=(3<<5); //Size=64, No Double-Packet Buffering -// USB->RXCSR1|=USB_RXCSRL_FLUSH_MSK; //Flush FIFO - } - } -} - -/** - * @brief Acknowledge that data was read from the specified endpoint's FIFO in host mode. - * - * This function acknowledges that the data was read from the endpoint's FIFO. - * This call is used if processing is required between reading the data and - * acknowledging that the data has been read. - * @param ui32Endpoint is the endpoint to access. - * @note This function must only be called in host mode. - * @retval None. - */ -void md_usb_hos_endpoint_data_ack(uint32_t ui32Endpoint) -{ - // - //Chose endpoint. - // - USB->INDEX = (uint8_t)USBEPToIndex(ui32Endpoint); - - // - // Clear RxPktRdy. - // - if (ui32Endpoint == USB_EP_0) - { - USB->CSR0L_TXCSRL &= ~USB_CSR0L_TXCSRL_RXRDY_MSK; - } - else - { - USB->RXCSR1 &= ~(USB_RXCSRL_RXRDY_MSK); - } -} - -/** - * @brief Sets the value data toggle on an endpoint in host mode. - * - * This function is used to force the state of the data toggle in host mode. - * If the value passed in the \e bDataToggle parameter is \b false, then the - * data toggle is set to the DATA0 state, and if it is \b true it is set to - * the DATA1 state. The \e ui32Flags parameter can be \b USB_EP_HOST_IN or - * \b USB_EP_HOST_OUT to access the desired portion of this endpoint. The - * \e ui32Flags parameter is ignored for endpoint zero. - * @param ui32Endpoint is the endpoint to access. - * @param bDataToggle specifies whether to set the state to DATA0 or DATA1. - * @param ui32Flags specifies whether to set the IN or OUT endpoint. - * @note This function must only be called in host mode. - * @retval None. - */ -void md_usb_hos_endpoint_data_toggle(uint32_t ui32Endpoint, - bool bDataToggle, uint32_t ui32Flags) -{ - // - // It is not supported by es32f0271. - // - UNUSED(ui32Endpoint); - UNUSED(bDataToggle); - UNUSED(ui32Flags); -} - -/** - * @brief Clears the status bits in this endpoint in host mode. - * - * This function clears the status of any bits that are passed in the - * \e ui32Flags parameter. The \e ui32Flags parameter can take the value - * returned from the md_usb_hosdev_endpoint_status() call. - * @param ui32Endpoint is the endpoint to access. - * @param ui32Flags are the status bits that are cleared. - * @note This function must only be called in host mode. - * @retval None. - */ -void md_usb_hos_endpoint_status_clear(uint32_t ui32Endpoint, - uint32_t ui32Flags) -{ - // - //Chose endpoint. - // - USB->INDEX = (uint8_t)USBEPToIndex(ui32Endpoint); - - // - // Clear the specified flags for the endpoint. - // - if (ui32Endpoint == USB_EP_0) - { - USB->CSR0L_TXCSRL &= ~(ui32Flags & 0xff); - } - else - { - USB->CSR0L_TXCSRL &= ~(ui32Flags & 0xff); - USB->RXCSR1 &= ~((ui32Flags >> 16) & 0xff); - } -} - -/** - * @brief Changes the speed of the connection for a host endpoint. - * - * This function sets the USB speed for an IN or OUT endpoint in host mode. - * The \e ui32Flags parameter specifies the speed using one of the following - * values: \b USB_EP_SPEED_LOW, \b USB_EP_SPEED_FULL, or \b USB_EP_SPEED_HIGH. - * The \e ui32Flags parameter also specifies which direction is set by - * adding the logical OR in either \b USB_EP_HOST_IN or \b USB_EP_HOST_OUT. - * All other flags are ignored. This function is typically only used for - * endpoint 0, but could be used with other endpoints as well. - * @param ui32Endpoint is the endpoint to access. - * @param ui32Flags are used to configure other endpoint settings. - * @note This function must only be called in host mode. - * @retval None. - */ -void md_usb_hos_endpoint_speed(uint32_t ui32Endpoint, - uint32_t ui32Flags) -{ - // - // For es32f0271,we can not config endpoint speed. - // - UNUSED(ui32Endpoint); - UNUSED(ui32Flags); -} - -/** - * @brief Enables or disables ping tokens for an endpoint using high-speed control - * transfers in host mode. - * - * This function configures the USB controller to either send or not send ping - * tokens during the data and status phase of high speed control transfers. - * The only supported value for \e ui32Endpoint is \b USB_EP_0 because all - * control transfers are handled using this endpoint. If the \e bEnable is - * \b true then ping tokens are enabled, if \b false then ping tokens are - * disabled. This must be used if the controller must support - * communications with devices that do not support ping tokens in high speed - * mode. - * @param ui32Endpoint specifies the endpoint to enable/disable ping tokens. - * @param bEnable specifies whether enable or disable ping tokens. - * @note This function must only be called in host mode. - * @retval None. - */ -void md_usb_hos_endpoint_ping(uint32_t ui32Endpoint, - bool bEnable) -{ - // - // It is not supported by es32f0271. - // - UNUSED(ui32Endpoint); - UNUSED(bEnable); -} - -/** - * @brief USB endpoint configuration. - * - * This function sets the basic configuration for an endpoint in device mode. - * Endpoint zero does not have a dynamic configuration, so this function - * must not be called for endpoint zero. The \e ui32Flags parameter - * determines some of the configuration while the other parameters provide the - * rest. - * - * When configuring an IN endpoint, the \b USB_EP_AUTO_SET bit can be - * specified to cause the automatic transmission of data on the USB bus as - * soon as \e ui32MaxPacketSize bytes of data are written into the FIFO for - * this endpoint. This option is commonly used with DMA as no interaction - * is required to start the transmission of data. - * - * The \b USB_EP_MODE_ flags define what the type is for the specified endpoint. - * USB_EP_MODE_CTRL is a control endpoint. - * USB_EP_MODE_ISOC is an isochronous endpoint. - * USB_EP_MODE_BULK is a bulk endpoint. - * USB_EP_MODE_INT is an interrupt endpoint. - * - * When configuring an OUT endpoint, the \b USB_EP_AUTO_REQUEST bit is - * specified to trigger the request for more data once the FIFO has been - * drained enough to receive \e ui32MaxPacketSize more bytes of data. Also - * for OUT endpoints, the \b USB_EP_AUTO_CLEAR bit can be used to clear the - * data packet ready flag automatically once the data has been read from the - * FIFO. If this option is not used, this flag must be manually cleared via a - * call to md_usb_dev_endpoint_status_clear(). Both of these settings can be - * used to remove the need for extra calls when using the controller with DMA. - * - * @param ui32Endpoint The USB endpoint. - * @param ui32MaxPacketSize is the maximum packet size for this endpoint. - * @param ui32Flags are used to configure other endpoint settings. - * @retval None. - */ -void md_usb_dev_endpoint_config_set(uint32_t ui32Endpoint, - uint32_t ui32MaxPacketSize, - uint32_t ui32Flags) -{ - uint32_t ui32Register; - - // - //Chose endpoint. - // - USB->INDEX = (uint8_t)USBEPToIndex(ui32Endpoint); - - // - // Determine if a transmit or receive endpoint is being configured. - // - if (ui32Flags & USB_EP_DEV_IN) /*IN*/ - { - // - // Set the max packet size. - // - USB->TXMAXP = ui32MaxPacketSize; - - // - // The transmit control value is zero unless options are enabled. - // - ui32Register = 0; - - // - // Allow auto setting of TxPktRdy when max packet size has been loaded - // into the FIFO. - // - if (ui32Flags & USB_EP_AUTO_SET) - { - ui32Register |= USB_CSR0H_TXCSRH_AUTOSET_MSK; - } - - // - // Configure the DMA mode. - // - /* es32f0271 does not support DMA */ - - // - // Enable isochronous mode if requested. - // - if ((ui32Flags & USB_EP_MODE_MASK) == USB_EP_MODE_ISOC) - { - ui32Register |= USB_CSR0H_TXCSRH_ISO_MSK; - } - - // - // Write the transmit control value. - // - USB->CSR0H_TXCSRH = (uint8_t)ui32Register; - - // - // Reset the Data toggle to zero. - // - USB->CSR0L_TXCSRL = USB_CSR0L_TXCSRL_CLRDATAT_MSK; - } - else /*OUT*/ - { - // - // Set the MaxPacketSize. - // - USB->RXMAXP = ui32MaxPacketSize; - - // - // The receive control value is zero unless options are enabled. - // - ui32Register = 0; - - // - // Allow auto clearing of RxPktRdy when packet of size max packet - // has been unloaded from the FIFO. - // - if (ui32Flags & USB_EP_AUTO_CLEAR) - { - ui32Register = USB_RXCSRH_AUTOCLR_MSK; - } - -// // -// // Configure the DMA mode. -// // - -// // -// // If requested, disable NYET responses for high-speed bulk and -// // interrupt endpoints. -// // - /*es32f0271 does not support*/ - - // - // Enable isochronous mode if requested. - // - if ((ui32Flags & USB_EP_MODE_MASK) == USB_EP_MODE_ISOC) - { - ui32Register |= USB_RXCSRH_ISO_MSK; - } - - // - // Write the receive control value. - // - USB->RXCSR2 = ui32Register; - - // - // Reset the Data toggle to zero. - // - USB->RXCSR1 = USB_RXCSRL_CLRDT_MSK; - } -} - -/** - * @brief Gets the current configuration for an endpoint. - * - * This function returns the basic configuration for an endpoint in device - * mode. The values returned in \e *pui32MaxPacketSize and \e *pui32Flags are - * equivalent to the \e ui32MaxPacketSize and \e ui32Flags previously passed - * to md_usb_dev_endpoint_config_get() for this endpoint. - * - * @note This function must only be called in device mode. - * @param ui32Endpoint is the endpoint to access. - * @param pui32MaxPacketSize is a pointer which is written with the maximum - * packet size for this endpoint. - * @param pui32Flags is a pointer which is written with the current endpoint - * settings. On entry to the function, this pointer must contain either - * \b USB_EP_DEV_IN or \b USB_EP_DEV_OUT to indicate whether the IN or OUT - * endpoint is to be queried. - * @retval None. - */ -void md_usb_dev_endpoint_config_get(uint32_t ui32Endpoint, - uint32_t *pui32MaxPacketSize, - uint32_t *pui32Flags) -{ - uint32_t ui32Register; - - // - //Chose endpoint. - // - USB->INDEX = (uint8_t)USBEPToIndex(ui32Endpoint); - - // - // Determine if a transmit or receive endpoint is being queried. - // - if (*pui32Flags & USB_EP_DEV_IN) - { - // - // Clear the flags other than the direction bit. - // - *pui32Flags = USB_EP_DEV_IN; - - // - // Get the maximum packet size. - // - *pui32MaxPacketSize = (uint32_t)USB->TXMAXP; - - // - // Get the current transmit control register value.` - // - ui32Register = (uint32_t)(USB->CSR0H_TXCSRH); - - // - // Are we allowing auto setting of TxPktRdy when max packet size has - // been loaded into the FIFO? - // - if (ui32Register & USB_CSR0H_TXCSRH_AUTOSET_MSK) - { - *pui32Flags |= USB_EP_AUTO_SET; - } - - // - // Get the DMA mode. - // - - // - // Are we in isochronous mode? - // - if (ui32Register & USB_CSR0H_TXCSRH_ISO_MSK) - { - *pui32Flags |= USB_EP_MODE_ISOC; - } - else - { - // - // The hardware doesn't differentiate between bulk, interrupt - // and control mode for the endpoint so we just set something - // that isn't isochronous. This protocol ensures that anyone - // modifying the returned flags in preparation for a call to - // USBDevEndpointConfigSet do not see an unexpected mode change. - // If they decode the returned mode, however, they may be in for - // a surprise. - // - *pui32Flags |= USB_EP_MODE_BULK; - } - } - else - { - // - // Clear the flags other than the direction bit. - // - *pui32Flags = USB_EP_DEV_OUT; - - // - // Get the MaxPacketSize. - // - *pui32MaxPacketSize = (uint32_t)USB->RXMAXP; - - // - // Get the current receive control register value. - // - ui32Register = (uint32_t)(USB->RXCSR2); - - // - // Are we allowing auto clearing of RxPktRdy when packet of size max - // packet has been unloaded from the FIFO? - // - if (ui32Register & USB_RXCSRH_AUTOCLR_MSK) - { - *pui32Flags |= USB_EP_AUTO_CLEAR; - } - - // - // Get the DMA mode. - // - - // - // Are we in isochronous mode? - // - if (ui32Register & USB_RXCSRH_ISO_MSK) - { - *pui32Flags |= USB_EP_MODE_ISOC; - } - else - { - // - // The hardware doesn't differentiate between bulk, interrupt - // and control mode for the endpoint so we just set something - // that isn't isochronous. This protocol ensures that anyone - // modifying the returned flags in preparation for a call to - // USBDevEndpointConfigSet do not see an unexpected mode change. - // If they decode the returned mode, however, they may be in for - // a surprise. - // - *pui32Flags |= USB_EP_MODE_BULK; - } - } -} - -/** - * @brief Acknowledge that data was read from the specified endpoint's FIFO in device - * mode. - * - * This function acknowledges that the data was read from the endpoint's FIFO. - * The \e bIsLastPacket parameter is set to a \b true value if this is the - * last in a series of data packets on endpoint zero. The \e bIsLastPacket - * parameter is not used for endpoints other than endpoint zero. This call - * can be used if processing is required between reading the data and - * acknowledging that the data has been read. - * @param ui32Endpoint is the endpoint to access. - * @param bIsLastPacket indicates if this packet is the last one. - * @note This function must only be called in device mode. - * @retval None. - */ -void md_usb_dev_endpoint_ack(uint32_t ui32Endpoint, - bool bIsLastPacket) -{ - // - //Chose endpoint. - // - USB->INDEX = (uint8_t)USBEPToIndex(ui32Endpoint); - - // - // Determine which endpoint is being acked. - // - if (ui32Endpoint == USB_EP_0) - { - // - // Clear RxPktRdy, and optionally DataEnd, on endpoint zero. - // - USB->CSR0L_TXCSRL = USB_CSR0L_TXCSRL_RXRDYC_MSK | (bIsLastPacket ? USB_CSR0L_TXCSRL_DATAEND_MSK : 0); - } - else - { - // - // Clear RxPktRdy on all other endpoints. - // - USB->RXCSR1 &= ~USB_RXCSRL_RXRDY_MSK; - } -} - -/** - * @brief Stalls the specified endpoint in device mode. - * - * This function causes the endpoint number passed in to go into a stall - * condition. If the \e ui32Flags parameter is \b USB_EP_DEV_IN, then the - * stall is issued on the IN portion of this endpoint. If the \e ui32Flags - * parameter is \b USB_EP_DEV_OUT, then the stall is issued on the OUT portion - * of this endpoint. - * @param ui32Endpoint is the endpoint to access. - * @param ui32Flags specifies whether to stall the IN or OUT endpoint. - * @note This function must only be called in device mode. - * @retval None. - */ -void md_usb_dev_endpoint_stall(uint32_t ui32Endpoint, uint32_t ui32Flags) -{ - // - //Chose endpoint. - // - USB->INDEX = (uint8_t)USBEPToIndex(ui32Endpoint); - - // - // Determine how to stall this endpoint. - // - if (ui32Endpoint == USB_EP_0) - { - // - // Perform a stall on endpoint zero. - // - USB->CSR0L_TXCSRL |= USB_CSR0L_TXCSRL_RXRDYC_MSK | USB_CSR0L_TXCSRL_STALL_MSK; - } - else if (ui32Flags == USB_EP_DEV_IN) - { - // - // Perform a stall on an IN endpoint. - // - USB->CSR0L_TXCSRL |= USB_CSR0L_TXCSRL_STALL_MSK; - } - else - { - // - // Perform a stall on an OUT endpoint. - // - USB->RXCSR1 |= USB_RXCSRL_STALL_MSK; - } -} - -/** - * @brief Clears the stall condition on the specified endpoint in device mode. - * - * This function causes the endpoint number passed in to exit the stall - * condition. If the \e ui32Flags parameter is \b USB_EP_DEV_IN, then the - * stall is cleared on the IN portion of this endpoint. If the \e ui32Flags - * parameter is \b USB_EP_DEV_OUT, then the stall is cleared on the OUT - * portion of this endpoint. - * @param ui32Endpoint is the endpoint to access. - * @param ui32Flags specifies whether to stall the IN or OUT endpoint. - * @note This function must only be called in device mode. - * @retval None. - */ -void md_usb_dev_endpoint_stall_clear(uint32_t ui32Endpoint, uint32_t ui32Flags) -{ - // - //Chose endpoint. - // - USB->INDEX = (uint8_t)USBEPToIndex(ui32Endpoint); - - // - // Determine how to clear the stall on this endpoint. - // - if (ui32Endpoint == USB_EP_0) - { - // - // Clear the stall on endpoint zero. - // - USB->CSR0L_TXCSRL &= ~USB_CSR0L_TXCSRL_STALLED_MSK; - } - else if (ui32Flags == USB_EP_DEV_IN) - { - // - // Clear the stall on an IN endpoint. - // - USB->CSR0L_TXCSRL &= ~(USB_CSR0L_TXCSRL_SENTSTALL_MSK | USB_CSR0L_TXCSRL_SENDSTALL_MSK); - - // - // Reset the data toggle. - // - /* @yuzr es32f0271 can not realize */ - USB->CSR0L_TXCSRL |= USB_CSR0L_TXCSRL_CLRDATAT_MSK; - } - else - { - // - // Clear the stall on an OUT endpoint. - // -// HWREGB(ui32Base + USB_O_RXCSRL1 + EP_OFFSET(ui32Endpoint)) &= -// ~(USB_RXCSRL1_STALL | USB_RXCSRL1_STALLED); - USB->RXCSR1 &= ~(USB_RXCSRL_STALL_MSK | USB_RXCSRL_STALLED_MSK); - - // - // Reset the data toggle. - // - USB->RXCSR1 |= USB_RXCSRL_CLRDT_MSK; - } -} - -/** - * @brief Clears the status bits in this endpoint in device mode. - * - * This function clears the status of any bits that are passed in the - * \e ui32Flags parameter. The \e ui32Flags parameter can take the value - * returned from the USBEndpointStatus() call. - * @param ui32Endpoint is the endpoint to access. - * @param ui32Flags are the status bits that are cleared. - * @note This function must only be called in device mode. - * @retval None. - */ -void md_usb_dev_endpoint_status_clear(uint32_t ui32Endpoint, uint32_t ui32Flags) -{ - // - //Chose endpoint. - // - USB->INDEX = (uint8_t)USBEPToIndex(ui32Endpoint); - - // - // If this is endpoint 0, then the bits have different meaning and map - // into the TX memory location. - // - if (ui32Endpoint == USB_EP_0) - { - // - // Set the Serviced RxPktRdy bit to clear the RxPktRdy. - // - if (ui32Flags & USB_DEV_EP0_OUT_PKTRDY) - { - USB->CSR0L_TXCSRL |= USB_CSR0L_TXCSRL_RXRDYC_MSK; - } - - // - // Set the serviced Setup End bit to clear the SetupEnd status. - // - if (ui32Flags & USB_DEV_EP0_SETUP_END) - { - USB->CSR0L_TXCSRL |= USB_CSR0L_TXCSRL_SETENDC_MSK; - } - - // - // Clear the Sent Stall status flag. - // - if (ui32Flags & USB_DEV_EP0_SENT_STALL) - { - USB->CSR0L_TXCSRL &= ~(USB_CSR0L_TXCSRL_STALLED_MSK); - } - } - else - { - // - // Clear out any TX flags that were passed in. Only - // USB_DEV_TX_SENT_STALL and USB_DEV_TX_UNDERRUN must be cleared. - // - USB->CSR0L_TXCSRL &= ~(ui32Flags & (USB_CSR0L_TXCSRL_STALL_MSK | USB_DEV_TX_UNDERRUN)); - - // - // Clear out valid RX flags that were passed in. Only - // USB_DEV_RX_SENT_STALL, USB_DEV_RX_DATA_ERROR, and USB_DEV_RX_OVERRUN - // must be cleared. - // - USB->RXCSR1 &= ~((ui32Flags & (USB_DEV_RX_SENT_STALL | USB_DEV_RX_DATA_ERROR | - USB_DEV_RX_OVERRUN)) >> 16); - } -} - -/** - * @brief Determines the number of bytes of data available in a specified endpoint's - * FIFO. - * - * This function returns the number of bytes of data currently available in the - * FIFO for the specified receive (OUT) endpoint. It may be used prior to calling - * md_usb_hosdev_endpoint_data_get() to determine the size of buffer required to - * hold the newly-received packet. - * @param ui32Endpoint is the endpoint to access. - * @retval This call returns the number of bytes available in a specified endpoint - * FIFO. - */ -uint32_t md_usb_hosdev_endpoint_datavai(uint32_t ui32Endpoint) -{ - uint8_t temp; //use to clear warning in IAR system - // - //Chose endpoint. - // - USB->INDEX = (uint8_t)USBEPToIndex(ui32Endpoint); - - // - // Get the address of the receive status register to use, based on the - // endpoint. - // - if (ui32Endpoint == USB_EP_0) - { - // - // Is there a packet ready in the FIFO? - // - if (USB->CSR0L_TXCSRL & USB_CSR0L_TXCSRL_RXRDY_MSK) - { - // - // Return the byte count in the FIFO. - // - return (uint32_t)(USB->RXCOUNT1); - } - - return (0); - } - else - { - // - // Is there a packet ready in the FIFO? - // - if (USB->RXCSR1 & USB_RXCSRL_RXRDY_MSK) - { - // - // Return the byte count in the FIFO. - // - temp = USB->RXCOUNT1; - return (uint32_t)(temp | USB->RXCOUNT2 << 8); - } - - return (0); - } -} - -/** - * @brief Retrieves data from the specified endpoint's FIFO. - * - * This function returns the data from the FIFO for the specified endpoint. - * The \e pui32Size parameter indicates the size of the buffer passed in - * the \e pui32Data parameter. The data in the \e pui32Size parameter is - * changed to match the amount of data returned in the \e pui8Data parameter. - * If a zero-byte packet is received, this call does not return an error but - * instead just returns a zero in the \e pui32Size parameter. The only error - * case occurs when there is no data packet available. - * @param ui32Endpoint is the endpoint to access. - * @param pui8Data is a pointer to the data area used to return the data from - * the FIFO. - * @param pui32Size is initially the size of the buffer passed into this call - * via the \e pui8Data parameter. It is set to the amount of data returned in - * the buffer. - * @retval This call returns 0, or -1 if no packet was received. - */ -int32_t md_usb_hosdev_endpoint_data_get(uint32_t ui32Endpoint, - uint8_t *pui8Data, - uint32_t *pui32Size) -{ - uint32_t ui32ByteCount, ui32FIFO; - uint8_t temp; //use to clear warning in IAR system - // - //Chose endpoint. - // - USB->INDEX = (uint8_t)USBEPToIndex(ui32Endpoint); - - // - // Don't allow reading of data if the RxPktRdy bit is not set. - // - if (ui32Endpoint == USB_EP_0) - { - if ((USB->CSR0L_TXCSRL & USB_CSR0L_TXCSRL_RXRDY_MSK) == 0) - { - // - // Can't read the data because none is available. - // - *pui32Size = 0; - - // - // Return a failure since there is no data to read. - // - return (-1); - } - } - else - { - if ((USB->RXCSR1 & USB_RXCSRL_RXRDY_MSK) == 0) - { - // - // Can't read the data because none is available. - // - *pui32Size = 0; - - // - // Return a failure since there is no data to read. - // - return (-1); - } - } - - // - // Get the byte count in the FIFO. - // - if (ui32Endpoint == USB_EP_0) - { - ui32ByteCount = (uint32_t)(USB->RXCOUNT1); - } - else - { - temp = USB->RXCOUNT1; - ui32ByteCount = (uint32_t)(temp | (USB->RXCOUNT2 << 8)); - } - - // - // Determine how many bytes are copied. - // - ui32ByteCount = (ui32ByteCount < *pui32Size) ? ui32ByteCount : *pui32Size; - - // - // Return the number of bytes we are going to read. - // - *pui32Size = ui32ByteCount; - - // - // Calculate the FIFO address. - // - ui32FIFO = (uint32_t)(&USB->EP0FIFO) + 4 * (uint32_t)USBEPToIndex(ui32Endpoint); - - // - // Read the data out of the FIFO. - // - for (; ui32ByteCount > 0; ui32ByteCount--) - { - // - // Read a byte at a time from the FIFO. - // - *pui8Data++ = *((volatile uint8_t *)(ui32FIFO)); - } - - // - // Success. - // - return (0); -} - -/** - * @brief Puts data into the specified endpoint's FIFO. - * - * This function puts the data from the \e pui8Data parameter into the FIFO - * for this endpoint. If a packet is already pending for transmission, then - * this call does not put any of the data into the FIFO and returns -1. Care - * must be taken to not write more data than can fit into the FIFO - * allocated by the call to md_usb_dev_endpoint_config_set(). - * @param ui32Endpoint is the endpoint to access. - * @param pui8Data is a pointer to the data area used as the source for the - * data to put into the FIFO. - * @param ui32Size is the amount of data to put into the FIFO. - * @retval This call returns 0 on success, or -1 to indicate that the FIFO - * is in use and cannot be written. - */ -int32_t md_usb_hosdev_endpoint_data_put(uint32_t ui32Endpoint, - uint8_t *pui8Data, uint32_t ui32Size) -{ - uint32_t ui32FIFO; - - // - //Chose endpoint. - // - USB->INDEX = (uint8_t)USBEPToIndex(ui32Endpoint); - - // - // Don't allow transmit of data if the TxPktRdy bit is already set. - // - if (ui32Endpoint == USB_EP_0) - { - if (USB->CSR0L_TXCSRL & USB_CSR0L_TXCSRL_TXRDY_MSK) - return (-1); - } - else - { - if (USB->CSR0L_TXCSRL & USB_CSR0L_TXCSRL_TXPKTRDY_MSK) - return (-1); - } - - // - // Calculate the FIFO address. - // - ui32FIFO = (uint32_t)(&USB->EP0FIFO) + 4 * (uint32_t)USBEPToIndex(ui32Endpoint); - - // - // Write the data to the FIFO. - // - for (; ui32Size > 0; ui32Size--) - { - *((volatile uint8_t *)(ui32FIFO)) = *pui8Data++; - } - - // - // Success. - // - return (0); -} - -/** - * @brief Starts the transfer of data from an endpoint's FIFO. - * - * This function starts the transfer of data from the FIFO for a specified - * endpoint. This function is called if the \b USB_EP_AUTO_SET bit was - * not enabled for the endpoint. Setting the \e ui32TransType parameter - * allows the appropriate signaling on the USB bus for the type of transaction - * being requested. The \e ui32TransType parameter must be one of the - * following: - * - * - \b USB_TRANS_OUT for OUT transaction on any endpoint in host mode. - * - \b USB_TRANS_IN for IN transaction on any endpoint in device mode. - * - \b USB_TRANS_IN_LAST for the last IN transaction on endpoint zero in a - * sequence of IN transactions. - * \b USB_TRANS_SETUP for setup transactions on endpoint zero. - * \b USB_TRANS_STATUS for status results on endpoint zero. - * @param ui32Endpoint is the endpoint to access. - * @param ui32TransType is set to indicate what type of data is being sent. - * @retval This call returns 0 on success, or -1 if a transmission is already - * in progress. - */ -int32_t md_usb_hosdev_endpoint_data_send(uint32_t ui32Endpoint, - uint32_t ui32TransType) -{ - uint32_t ui32TxPktRdy; - - // - //Chose endpoint. - // - USB->INDEX = (uint8_t)USBEPToIndex(ui32Endpoint); - - // - // Get the bit position of TxPktRdy based on the endpoint. - // - if (ui32Endpoint == USB_EP_0) - { - // - // Don't allow transmit of data if the TxPktRdy bit is already set. - // - if (USB->CSR0L_TXCSRL & USB_CSR0L_TXCSRL_TXRDY_MSK) - { - return (-1); - } - - ui32TxPktRdy = ui32TransType & 0xff; - } - else - { - // - // Don't allow transmit of data if the TxPktRdy bit is already set. - // - if (USB->CSR0L_TXCSRL & USB_CSR0L_TXCSRL_TXPKTRDY_MSK) - { - return (-1); - } - - ui32TxPktRdy = (ui32TransType >> 8) & 0xff; - } - - // - // Set TxPktRdy in order to send the data. - // - USB->CSR0L_TXCSRL = ui32TxPktRdy; - - // - // Success. - // - return (0); -} - -/** - * @brief Forces a flush of an endpoint's FIFO. - * - * This function forces the USB controller to flush out the data in the FIFO. - * The function can be called with either host or device controllers and - * requires the \e ui32Flags parameter be one of \b USB_EP_HOST_OUT, - * \b USB_EP_HOST_IN, \b USB_EP_DEV_OUT, or \b USB_EP_DEV_IN. - * @param ui32Endpoint is the endpoint to access. - * @param ui32Flags specifies if the IN or OUT endpoint is accessed. - * @retval None. - */ -void md_usb_hosdev_endpoint_data_togglec(uint32_t ui32Endpoint, - uint32_t ui32Flags) -{ - // - //Chose endpoint. - // - USB->INDEX = (uint8_t)USBEPToIndex(ui32Endpoint); - - if (ui32Flags & (USB_EP_HOST_OUT | USB_EP_DEV_IN)) - { - USB->CSR0L_TXCSRL |= USB_CSR0L_TXCSRL_CLRDATAT_MSK; - } - else - { - USB->RXCSR1 |= USB_RXCSRL_CLRDT_MSK; - } -} - -/** - * @brief Sets the number of packets to request when transferring multiple bulk - * packets. - * - * This function sets the number of consecutive bulk packets to request - * when transferring multiple bulk packets with DMA. - * - * @param ui32Endpoint is the endpoint to access. - * @param ui32Count is the number of packets to request. - * @retval None. - */ -void md_usb_hosdev_endpoint_pkcount_set(uint32_t ui32Endpoint, - uint32_t ui32Count) -{ - /* It's not supported by es32f0271 */ -} - -/** - * @brief Returns the current status of an endpoint. - * - * This function returns the status of a specified endpoint. If any of these - * status bits must be cleared, then the md_usb_dev_endpoint_status_clear() or the - * md_usb_hos_endpoint_status_clear() functions must be called. - * - * The following are the status flags for host mode: - * - * - \b USB_HOST_IN_PID_ERROR - PID error on the specified endpoint. - * - \b USB_HOST_IN_NOT_COMP - The device failed to respond to an IN request. - * - \b USB_HOST_IN_STALL - A stall was received on an IN endpoint. - * - \b USB_HOST_IN_DATA_ERROR - There was a CRC or bit-stuff error on an IN - * endpoint in Isochronous mode. - * - \b USB_HOST_IN_NAK_TO - NAKs received on this IN endpoint for more than - * the specified timeout period. - * - \b USB_HOST_IN_ERROR - Failed to communicate with a device using this IN - * endpoint. - * - \b USB_HOST_IN_FIFO_FULL - This IN endpoint's FIFO is full. - * - \b USB_HOST_IN_PKTRDY - Data packet ready on this IN endpoint. - * - \b USB_HOST_OUT_NAK_TO - NAKs received on this OUT endpoint for more than - * the specified timeout period. - * - \b USB_HOST_OUT_NOT_COMP - The device failed to respond to an OUT - * request. - * - \b USB_HOST_OUT_STALL - A stall was received on this OUT endpoint. - * - \b USB_HOST_OUT_ERROR - Failed to communicate with a device using this - * OUT endpoint. - * - \b USB_HOST_OUT_FIFO_NE - This endpoint's OUT FIFO is not empty. - * - \b USB_HOST_OUT_PKTPEND - The data transfer on this OUT endpoint has not - * completed. - * - \b USB_HOST_EP0_NAK_TO - NAKs received on endpoint zero for more than the - * specified timeout period. - * - \b USB_HOST_EP0_ERROR - The device failed to respond to a request on - * endpoint zero. - * - \b USB_HOST_EP0_IN_STALL - A stall was received on endpoint zero for an - * IN transaction. - * - \b USB_HOST_EP0_IN_PKTRDY - Data packet ready on endpoint zero for an IN - * transaction. - * - * The following are the status flags for device mode: - * - * - \b USB_DEV_OUT_SENT_STALL - A stall was sent on this OUT endpoint. - * - \b USB_DEV_OUT_DATA_ERROR - There was a CRC or bit-stuff error on an OUT - * endpoint. - * - \b USB_DEV_OUT_OVERRUN - An OUT packet was not loaded due to a full FIFO. - * - \b USB_DEV_OUT_FIFO_FULL - The OUT endpoint's FIFO is full. - * - \b USB_DEV_OUT_PKTRDY - There is a data packet ready in the OUT - * endpoint's FIFO. - * - \b USB_DEV_IN_NOT_COMP - A larger packet was split up, more data to come. - * - \b USB_DEV_IN_SENT_STALL - A stall was sent on this IN endpoint. - * - \b USB_DEV_IN_UNDERRUN - Data was requested on the IN endpoint and no - * data was ready. - * - \b USB_DEV_IN_FIFO_NE - The IN endpoint's FIFO is not empty. - * - \b USB_DEV_IN_PKTPEND - The data transfer on this IN endpoint has not - * completed. - * - \b USB_DEV_EP0_SETUP_END - A control transaction ended before Data End - * condition was sent. - * - \b USB_DEV_EP0_SENT_STALL - A stall was sent on endpoint zero. - * - \b USB_DEV_EP0_IN_PKTPEND - The data transfer on endpoint zero has not - * completed. - * - \b USB_DEV_EP0_OUT_PKTRDY - There is a data packet ready in endpoint - * zero's OUT FIFO. - * - * @param The current status flags for the endpoint depending on mode. - * @retval None. - */ -uint32_t md_usb_hosdev_endpoint_status(uint32_t ui32Endpoint) -{ - uint32_t ui32Status; - - // - //Chose endpoint. - // - USB->INDEX = (uint8_t)USBEPToIndex(ui32Endpoint); - - // - // Get the TX portion of the endpoint status. - // - ui32Status = USB->CSR0L_TXCSRL; - - // - // Get the RX portion of the endpoint status. - // Return zero if ui32Endpoint is equal to USB_EP_0. - // - ui32Status |= (((ui32Endpoint == USB_EP_0) ? 0x00 : USB->RXCSR1) << 16); - - // - // Return the endpoint status. - // - return (ui32Status); -} - -/** - * @brief Disables endpoint interrupts on a specified USB controller. - * - * This function disables endpoint interrupts for the USB controller specified - * by the \e ui32Base parameter. The \e ui32Flags parameter specifies which - * endpoint interrupts to disable. The flags passed in the \e ui32Flags - * parameters must be the definitions that start with \b USB_INTEP_* and not - * any other \b USB_INT flags. - * @param ui32IntFlags specifies which endpoint interrupts to disable. - * @retval None. - */ -void md_usb_hosdev_endpoint_int_disable(uint32_t ui32IntFlags) -{ - // - // If any transmit interrupts were disabled, then write the transmit - // interrupt settings out to the hardware. - // - USB->TXIER &= - ~(ui32IntFlags & (USB_INTEP_HOST_OUT | USB_INTEP_DEV_IN | USB_INTEP_0)); - - // - // If any receive interrupts were disabled, then write the receive - // interrupt settings out to the hardware. - // - USB->RXIER &= - ~((ui32IntFlags & (USB_INTEP_HOST_IN | USB_INTEP_DEV_OUT)) >> 16); -} - -/** - * @brief Enable endpoint interrupts on a specified USB controller. - * - * This function Enable endpoint interrupts for the USB controller specified - * by the \e ui32Base parameter. The \e ui32Flags parameter specifies which - * endpoint interrupts to disable. The flags passed in the \e ui32Flags - * parameters must be the definitions that start with \b USB_INTEP_* and not - * any other \b USB_INT flags. - * @param ui32IntFlags specifies which endpoint interrupts to Enable. - * @retval None. - */ -void md_usb_hosdev_endpoint_int_enable(uint32_t ui32IntFlags) -{ - // - // If any transmit interrupts were disabled, then write the transmit - // interrupt settings out to the hardware. - // - USB->TXIER |= - ui32IntFlags & (USB_INTEP_HOST_OUT | USB_INTEP_DEV_IN | USB_INTEP_0); - - // - // If any receive interrupts were disabled, then write the receive - // interrupt settings out to the hardware. - // - USB->RXIER |= - ((ui32IntFlags & (USB_INTEP_HOST_IN | USB_INTEP_DEV_OUT)) >> 16); -} - -/** - * @brief Returns the endpoint interrupt status on a specified USB controller. - * - * This function reads endpoint interrupt status for a USB controller. This - * call returns the current status for endpoint interrupts only, the control - * interrupt status is retrieved by calling md_usb_hosdev_int_status(). The bit - * values returned are compared against the \b USB_INTEP_* values. - * These values are grouped into classes for \b USB_INTEP_HOST_* and - * \b USB_INTEP_DEV_* values to handle both host and device modes with all - * endpoints. - * @param None. - * @note This call clears the source of all of the endpoint interrupts. - * @retval Returns the status of the endpoint interrupts for a USB controller. - */ -uint32_t md_usb_hosdev_endpoint_int_status(void) -{ - uint32_t ui32Status; - - // - // Get the transmit interrupt status. - // - ui32Status = USB->TXRIF; - ui32Status |= (USB->RXRIF << 16); - - // - // Clear the transmit interrupt status. - // - USB->TXICR = 0xff; - USB->RXICR = 0xff; - - // - // Return the combined interrupt status. - // - return (ui32Status); -} - -/** - * @brief Change the mode of the USB controller to OTG. - * - * This function changes the mode of the USB controller to OTG mode. - * - * @note This function must only be called on microcontrollers that support - * OTG operation. - * @param None. - * @retval None. - */ -uint32_t md_usb_endpoint_number_get(void) -{ - return 13; -} - -/** - * @} USB_MD_PF_ENDPOINT - */ - -/** @addtogroup USB_MD_PF_FIFO USB Public FIFO Functions - * @{ - */ - -/** - * @brief Returns the absolute FIFO address for a specified endpoint. - * - * This function returns the actual physical address of the FIFO. This - * address is needed when the USB is going to be used with the DMA - * controller and the source or destination address must be set to the - * physical FIFO address for a specified endpoint. This function can also be - * used to provide the physical address to manually read data from an - * endpoints FIFO. - * - * @param ui32Endpoint specifies which endpoint's FIFO address to return. - * @retval None. - */ -uint32_t md_usb_hosdev_fifo_addr_get(uint32_t ui32Endpoint) -{ - return (uint32_t)((uint32_t)(&USB->EP0FIFO) + ((uint32_t)USBEPToIndex(ui32Endpoint) << 2)); -} - -/** - * @brief Returns the FIFO configuration for an endpoint. - * - * This function returns the starting address and size of the FIFO for a - * specified endpoint. Endpoint zero does not have a dynamically configurable - * FIFO, so this function must not be called for endpoint zero. The - * \e ui32Flags parameter specifies whether the endpoint's OUT or IN FIFO must - * be read. If in host mode, the \e ui32Flags parameter must be - * \b USB_EP_HOST_OUT or \b USB_EP_HOST_IN, and if in device mode, the - * \e ui32Flags parameter must be either \b USB_EP_DEV_OUT or - * \b USB_EP_DEV_IN. - * - * @param ui32Endpoint is the endpoint to access. - * @param ui32FIFOAddress is the starting address for the FIFO. - * @param ui32FIFOSize is the size of the FIFO specified by one of the - * USB_FIFO_SZ_ values. - * @param ui32Flags specifies what information to set in the FIFO - * configuration. - * @retval None. - */ -void md_usb_hosdev_fifo_config_get(uint32_t ui32Endpoint, uint32_t *pui32FIFOAddress, - uint32_t *pui32FIFOSize, uint32_t ui32Flags) -{ - uint8_t temp; //use to clear warning in IAR system - // - //Chose endpoint. - // - USB->INDEX = (uint8_t)USBEPToIndex(ui32Endpoint); - - // - // See if the transmit or receive FIFO is being configured. - // - if (ui32Flags & (USB_EP_HOST_OUT | USB_EP_DEV_IN)) - { - temp = USB->TXFIFO1 & 0xff; - // - // Get the transmit FIFO location and size for this endpoint. - // - *pui32FIFOAddress = (temp | ((USB->TXFIFO2 & 0x0f) << 8)) << 3; - *pui32FIFOSize = (USB->TXFIFO2 & 0xe0) >> USB_TXFIFO2_MAXPKTSIZE_POSS; - } - else - { - temp = USB->RXFIFO1 & 0xff; - // - // Get the receive FIFO location and size for this endpoint. - // - *pui32FIFOAddress = (temp | ((USB->TXFIFO2 & 0x0f) << 8)) << 3; - - *pui32FIFOSize = (USB->RXFIFO2 & 0xe0) >> USB_RXFIFO2_MAXPKTSIZE_POSS; - } -} - -/** - * @brief Sets the FIFO configuration for an endpoint. - * - * This function configures the starting FIFO RAM address and size of the FIFO - * for a specified endpoint. Endpoint zero does not have a dynamically - * configurable FIFO, so this function must not be called for endpoint zero. - * The \e ui32FIFOSize parameter must be one of the values in the - * \b USB_FIFO_SZ_ values. - * - * The \e ui32FIFOAddress value must be a multiple of 8 bytes and directly - * indicates the starting address in the USB controller's FIFO RAM. For - * example, a value of 64 indicates that the FIFO starts 64 bytes into - * the USB controller's FIFO memory. The \e ui32Flags value specifies whether - * the endpoint's OUT or IN FIFO must be configured. If in host mode, use - * \b USB_EP_HOST_OUT or \b USB_EP_HOST_IN, and if in device mode, use - * \b USB_EP_DEV_OUT or \b USB_EP_DEV_IN. - * - * @param ui32Endpoint is the endpoint to access. - * @param ui32FIFOAddress is the starting address for the FIFO. - * @param ui32FIFOSize is the size of the FIFO specified by one of the - * USB_FIFO_SZ_ values. - * @param ui32Flags specifies what information to set in the FIFO - * configuration. - * @retval None. - */ -void md_usb_hosdev_fifo_config_set(uint32_t ui32Endpoint, uint32_t ui32FIFOAddress, - uint32_t ui32FIFOSize, uint32_t ui32Flags) -{ - // - //Chose endpoint. - // - USB->INDEX = (uint8_t)USBEPToIndex(ui32Endpoint); - - // - // See if the transmit or receive FIFO is being configured. - // - if (ui32Flags & (USB_EP_HOST_OUT | USB_EP_DEV_IN)) - { - // - // Set the transmit FIFO location and size for this endpoint. - // - USB->TXFIFO1 = (uint8_t)((ui32FIFOAddress & 0xffff) >> 3); - - USB->TXFIFO2 = (uint8_t)((((ui32FIFOAddress & 0xffff) >> 3 >> 8) & 0x0f) - | (ui32FIFOSize) << USB_TXFIFO2_MAXPKTSIZE_POSS); - USB->CSR0L_TXCSRL |= USB_CSR0L_TXCSRL_FLUSHFIFO_MSK; - } - else - { - // - // Set the receive FIFO location and size for this endpoint. - // - USB->RXFIFO1 = (uint8_t)((ui32FIFOAddress & 0xffff) >> 3); - - USB->RXFIFO2 = (uint8_t)((((ui32FIFOAddress & 0xffff) >> 3 >> 8) & 0x0f) - | (ui32FIFOSize) << USB_RXFIFO2_MAXPKTSIZE_POSS); - USB->RXCSR1 |= USB_RXCSRL_FLUSH_MSK; - } -} - -/** - * @brief Forces a flush of an endpoint's FIFO. - * - * This function forces the USB controller to flush out the data in the FIFO. - * The function can be called with either host or device controllers and - * requires the \e ui32Flags parameter be one of \b USB_EP_HOST_OUT, - * \b USB_EP_HOST_IN, \b USB_EP_DEV_OUT, or \b USB_EP_DEV_IN. - * - * @param ui32Endpoint is the endpoint to access. - * @param ui32Flags specifies if the IN or OUT endpoint is accessed. - * @retval None. - */ -void md_usb_hosdev_fifo_flush(uint32_t ui32Endpoint, uint32_t ui32Flags) -{ - // - //Chose endpoint. - // - USB->INDEX = (uint8_t)USBEPToIndex(ui32Endpoint); - - // - // Endpoint zero has a different register set for FIFO flushing. - // - if (ui32Endpoint == USB_EP_0) - { - // - // Nothing in the FIFO if neither of these bits are set. - // - if ((USB->CSR0L_TXCSRL - & (USB_CSR0L_TXCSRL_TXRDY_MSK | USB_CSR0L_TXCSRL_RXRDY_MSK)) != 0) - { - // - // Hit the Flush FIFO bit. - // - USB->CSR0H_TXCSRH |= USB_CSR0H_TXCSRH_FLUSH_MSK; - } - } - else - { - // - // Only reset the IN or OUT FIFO. - // - if (ui32Flags & (USB_EP_HOST_OUT | USB_EP_DEV_IN)) - { - // - // Make sure the FIFO is not empty. - // - if (USB->CSR0L_TXCSRL & USB_CSR0L_TXCSRL_TXPKTRDY_MSK) - { - // - // Hit the Flush FIFO bit. - // - USB->CSR0L_TXCSRL |= USB_CSR0L_TXCSRL_FLUSHFIFO_MSK; - } - } - else - { - // - // Make sure that the FIFO is not empty. - // - if (USB->RXCSR1 & USB_RXCSRL_RXRDY_MSK) - { - // - // Hit the Flush FIFO bit. - // - USB->RXCSR1 |= USB_RXCSRL_FLUSH_MSK; - } - } - } -} - -/** - * @} USB_MD_PF_FIFO - */ - - -/** @addtogroup USB_MD_PF_EXPWR USB Public External Power Functions - * @{ - */ - -// -// The following pwr function is not supported by es32f0271 -// -/** - * @brief Disables the external power pin. - * - * This function disables the USBnEPEN signal, which disables an external - * power supply in host mode operation. - * - * @note This function must only be called in host mode. - * @retval None. - */ -__weak void md_usb_hos_pwr_disable(void) -{ -} - -/** - * @brief Enable the external power pin. - * - * This function disables the USBnEPEN signal, which disables an external - * power supply in host mode operation. - * - * @note This function must only be called in host mode. - * @retval None. - */ -__weak void md_usb_hos_pwr_enable(void) -{ - // - // Although Vbus is not supported by es32f0271,we provide Vbus - // from outside. - // - -} - -/** - * @brief Sets the configuration for USB power fault. - * - * This function controls how the USB controller uses its external power - * control pins (USBnPFLT and USBnEPEN). The flags specify the power - * fault level sensitivity, the power fault action, and the power enable level - * and source. - * - * One of the following can be selected as the power fault level sensitivity: - * - * - \b USB_HOST_PWRFLT_LOW - An external power fault is indicated by the pin - * being driven low. - * - \b USB_HOST_PWRFLT_HIGH - An external power fault is indicated by the pin - * being driven high. - * - * One of the following can be selected as the power fault action: - * - * - \b USB_HOST_PWRFLT_EP_NONE - No automatic action when power fault - * detected. - * - \b USB_HOST_PWRFLT_EP_TRI - Automatically tri-state the USBnEPEN pin on a - * power fault. - * - \b USB_HOST_PWRFLT_EP_LOW - Automatically drive USBnEPEN pin low on a - * power fault. - * - \b USB_HOST_PWRFLT_EP_HIGH - Automatically drive USBnEPEN pin high on a - * power fault. - * - * One of the following can be selected as the power enable level and source: - * - * - \b USB_HOST_PWREN_MAN_LOW - USBnEPEN is driven low by the USB controller - * when USBHostPwrEnable() is called. - * - \b USB_HOST_PWREN_MAN_HIGH - USBnEPEN is driven high by the USB - * controller when USBHostPwrEnable() is - * called. - * - \b USB_HOST_PWREN_AUTOLOW - USBnEPEN is driven low by the USB controller - * automatically if USBOTGSessionRequest() has - * enabled a session. - * - \b USB_HOST_PWREN_AUTOHIGH - USBnEPEN is driven high by the USB - * controller automatically if - * USBOTGSessionRequest() has enabled a - * session. - * - * When using the VBUS glitch filter, the \b USB_HOST_PWREN_FILTER can be - * addded to ignore small, short drops in VBUS level caused by high power - * consumption. This feature is mainly used to avoid causing VBUS errors - * caused by devices with high in-rush current. - * - * @note This function must only be called on microcontrollers that support - * host mode or OTG operation. The \b USB_HOST_PWREN_AUTOLOW and - * \b USB_HOST_PWREN_AUTOHIGH parameters can only be specified on devices that - * support OTG operation. - * @retval None. - */ -void md_usb_hos_pwr_config(uint32_t ui32Flags) -{ -} - -/** - * @brief Disable power fault detection. - * - * This function enables power fault detection in the USB controller. If the - * USBnPFLT pin is not in use, this function must not be used. - * - * @note This function must only be called in host mode. - * @retval None. - */ -void md_usb_hos_pwrfault_disable(void) -{ -} - -/** - * @brief Enable power fault detection. - * - * This function enables power fault detection in the USB controller. If the - * USBnPFLT pin is not in use, this function must not be used. - * - * @note This function must only be called in host mode. - * @retval None. - */ -void md_usb_hos_pwrfault_enable(void) -{ -} - -/** - * @} USB_MD_PF_EXPWR - */ - -/** @addtogroup USB_MD_PF_LPM USB Public LPM Functions - * @{ - */ - -// -// LPM is not supported by es32f0271 -// - -/** - * @brief Sends an LPM request to a device at a specified address and endpoint number. - * - * This function sends an LPM request to a connected device in host mode. - * The \e ui32Address parameter specifies the device address and has a range - * of values from 1 to 127. The \e ui32Endpoint parameter specifies the - * endpoint on the device to which to send the LPM request and must be one of - * the \b USB_EP_* values. The function returns before the LPM request is - * sent, requiring the caller to poll the md_usb_lpm_status() function or wait - * for an interrupt to signal completion of the LPM transaction. This - * function must only be called after the md_usb_hos_lpm_config() has configured - * the LPM transaction settings. - * - * @note This function must only be called in host mode. The USB LPM feature - * is not available on all ES32 devices. Please consult the data sheet for - * the ES32 device that you are using to determine if this feature is - * available. - * @param ui32Address is the target device address for the LPM request. - * @param ui32Endpoint is the target endpoint for the LPM request. - * @retval None. - */ -void md_usb_hos_lpm_send(uint32_t ui32Address, - uint32_t uiEndpoint) -{ -} - -/** - * @brief Sets the global configuration for all LPM requests. - * - * This function sets the global configuration options for LPM transactions - * and must be called at least once before ever calling md_usb_hos_lpm_send(). The - * \e ui32ResumeTime specifies the length of time that the host drives resume - * signaling on the bus in microseconds. The valid values - * for \e ui32ResumeTime are from 50us to 1175us in 75us increments. The - * remaining configuration is specified by the \e ui32Config parameter and - * includes the following options: - * - * - \b USB_HOST_LPM_RMTWAKE allows the device to signal a remote wake from - * the LPM state. - * - \b USB_HOST_LPM_L1 is the LPM mode to enter and must always be included - * in the configuration. - * - * @note This function must only be called in host mode. The USB LPM feature - * is not available on all ES32 devices. Please consult the data sheet for - * the ES32 device that you are using to determine if this feature is - * available. - * @param ui32Address is the target device address for the LPM request. - * @param ui32Endpoint is the target endpoint for the LPM request. - * @retval None. - */ -void md_usb_hos_lpm_config(uint32_t ui32ResumeTime, - uint32_t ui32Config) -{ -} - -/** - * @brief Returns if remote wake is currently enabled. - * - * This function returns the current state of the remote wake setting for host - * or device mode operation. If the controller is acting as a host this - * returns the current setting that is sent to devices when LPM requests are - * sent to a device. If the controller is in device mode, this function - * returns the state of the last LPM request sent from the host and indicates - * if the host enabled remote wakeup. - * - * @note This function must only be called in host mode. The USB LPM feature - * is not available on all ES32 devices. Please consult the data sheet for - * the ES32 device that you are using to determine if this feature is - * available. - * @param None. - * @retval The \b true if remote wake is enabled or \b false if it is not. - */ -bool md_usb_lpm_remotewake_is_enabled(void) -{ - return 0; -} - -/** - * @brief Initiates resume signaling to wake a device from LPM suspend mode. - * - * In host mode, this function initiates resume signaling to wake a device - * that has entered an LPM-triggered low power mode. This LPM-triggered low - * power mode is entered when the md_usb_hos_lpm_send() is called to put a specific - * device into a low power state. - * - * @note This function must only be called in host mode. The USB LPM feature - * is not available on all ES32 devices. Please consult the data sheet for - * the ES32 device that you are using to determine if this feature is - * available. - * @param None. - * @retval None. - */ -void md_usb_hos_lpm_resume(void) -{ -} - -/** - * @brief Initiates remote wake signaling to request the device to leave LPM - * suspend mode. - * - * This function initiates remote wake signaling to request that the host - * wake a device that has entered an LPM-triggered low power mode. - * - * @note This function must only be called in host mode. The USB LPM feature - * is not available on all ES32 devices. Please consult the data sheet for - * the ES32 device that you are using to determine if this feature is - * available. - * @param None. - * @retval None. - */ -void md_usb_dev_lpm_remotewake(void) -{ -} - -/** - * @brief Configures the USB device mode response to LPM requests. - * - * This function sets the global configuration options for LPM - * transactions in device mode and must be called before ever calling - * md_usb_dev_lpm_enable() to set the configuration for LPM transactions. The - * configuration options in device mode are specified in the \e ui32Config - * parameter and include one of the following: - * - * - \b USB_DEV_LPM_NONE disables the USB controller from responding to LPM - * transactions. - * - \b USB_DEV_LPM_EN enables the USB controller to respond to LPM - * and extended transactions. - * - \b USB_DEV_LPM_EXTONLY enables the USB controller to respond to - * extended transactions, but not LPM transactions. - * - * The \e ui32Config option can also optionally include the - * \b USB_DEV_LPM_NAK value to cause the USB controller to NAK all - * transactions other than an LPM transaction once the USB controller is in - * LPM suspend mode. If this value is not included in the \e ui32Config - * parameter, the USB controller does not respond in suspend mode. - * - * The USB controller does not enter LPM suspend mode until the application - * calls the md_usb_dev_lpm_enable() function. - * - * @note This function must only be called in host mode. The USB LPM feature - * is not available on all ES32 devices. Please consult the data sheet for - * the ES32 device that you are using to determine if this feature is - * available. - * @param ui32Config is the combination of configuration options for LPM - * transactions in device mode. - * @retval None. - */ -void md_usb_dev_lpm_config(uint32_t ui32Config) -{ -} - -/** - * @brief Enables the USB controller to respond to LPM suspend requests. - * - * This function is used to automatically respond to an LPM sleep request from - * the USB host controller. If there is no data pending in any transmit - * FIFOs, then the USB controller acknowledges the packet and enters the - * LPM L1 state and generates the \b USB_INTLPM_ACK interrupt. If the USB - * controller has pending transmit data in at least one FIFO, then the USB - * controller responds with NYET and signals the \b USB_INTLPM_INCOMPLETE or - * \b USB_INTLPM_NYET depending on if data is pending in receive or transmit - * FIFOs. A call to md_usb_dev_lpm_enable() is required after every - * LPM resume event to re-enable LPM mode. - * - * @note This function must only be called in host mode. The USB LPM feature - * is not available on all ES32 devices. Please consult the data sheet for - * the ES32 device that you are using to determine if this feature is - * available. - * @param None. - * @retval None. - */ -void md_usb_dev_lpm_enable(void) -{ -} - -/** - * @brief Disables the USB controller to respond to LPM suspend requests. - * - * This function disables the USB controller from responding to LPM - * transactions. When the device enters LPM L1 mode, the USB controller - * automatically disables responding to further LPM transactions. - * - * @note This function must only be called in host mode. The USB LPM feature - * is not available on all ES32 devices. Please consult the data sheet for - * the ES32 device that you are using to determine if this feature is - * available. - * @param None. - * @retval None. - */ -void md_usb_dev_lpm_disable(void) -{ -} - -/** - * @brief Returns the current link state setting. - * - * This function returns the current link state setting for the USB - * controller. When the controller is operating as a host, this link - * state is sent with an LPM request. When the controller is acting - * as a device, this link state was received by the last LPM transaction - * whether it was acknowledged or stalled because the requested - * LPM mode is not supported. - * - * @note This function must only be called in host mode. The USB LPM feature - * is not available on all ES32 devices. Please consult the data sheet for - * the ES32 device that you are using to determine if this feature is - * available. - * @param None. - * @retval The current LPM link state. - */ -uint32_t md_usb_lpm_link_state_get(void) -{ - return 0; -} - -/** - * @brief Returns the current LPM endpoint value. - * - * This function returns the current LPM endpoint value. The meaning of the - * value depends on the mode of operation of the USB controller. When in - * device mode, the value returned is the endpoint that received the last - * LPM transaction. When in host mode this is the endpoint that was last - * sent an LPM transaction, or the endpoint that is configured to be sent when - * the LPM transaction is triggered. The value returned is in the - * \b USB_EP_[0-7] value and a direct endpoint index. - * - * @note This function must only be called in host mode. The USB LPM feature - * is not available on all ES32 devices. Please consult the data sheet for - * the ES32 device that you are using to determine if this feature is - * available. - * @param None. - * @retval The last endpoint to receive an LPM request in device mode or the - * endpoint that the host sends an LPM request as one of the \b USB_EP_[0-7] - * values. - */ -uint32_t md_usb_lpm_endpoint_get(void) -{ - return 0; -} - -/** - * @brief Returns the current LPM interrupt status. - * - * This function returns the current LPM interrupt status for the USB - * controller. - * - * The valid interrupt status bits when the USB controller is acting as a host - * are the following: - * - * - \b USB_INTLPM_ERROR a bus error occurred in the transmission of an LPM - * transaction. - * - \b USB_INTLPM_RESUME the USB controller has resumed from the LPM low - * power state. - * - \b USB_INTLPM_INCOMPLETE the LPM transaction failed because a timeout - * occurred or there were bit errors in the response for three attempts. - * - \b USB_INTLPM_ACK the device has acknowledged an LPM transaction. - * - \b USB_INTLPM_NYET the device has responded with a NYET to an LPM - * transaction. - * - \b USB_INTLPM_STALL the device has stalled an LPM transaction. - * - * The valid interrupt status bits when the USB controller is acting as a - * device are the following: - * - * - \b USB_INTLPM_ERROR an LPM transaction was received that has an - * unsupported link state field. The transaction was stalled, but the - * requested link state can still be read using the md_usb_lpm_link_state_get() - * function. - * - \b USB_INTLPM_RESUME the USB controller has resumed from the LPM low - * power state. - * - \b USB_INTLPM_INCOMPLETE the USB controller responded to an LPM - * transaction with a NYET because data was still in the transmit FIFOs. - * - \b USB_INTLPM_ACK the USB controller acknowledged an LPM transaction and - * is now in the LPM suspend mode. - * - \b USB_INTLPM_NYET the USB controller responded to an LPM transaction - * with a NYET because LPM transactions are not yet enabled by a call to - * md_usb_dev_lpm_enable(). - * - \b USB_INTLPM_STALL the USB controller has stalled an incoming LPM - * transaction. - * - * @note This function must only be called in host mode. The USB LPM feature - * is not available on all ES32 devices. Please consult the data sheet for - * the ES32 device that you are using to determine if this feature is - * available. - * @param None. - * @retval The \b true if remote wake is enabled or \b false if it is not. - */ -uint32_t md_usb_lpm_status(void) -{ - return 0; -} - -/** - * @brief Enables LPM interrupts. - * - * This function enables a set of LPM interrupts so that they can trigger a - * USB interrupt. The \e ui32Ints parameter specifies which of the - * \b USB_INTLPM_* to enable. - * - * The valid interrupt status bits when the USB controller is acting as a host - * are the following: - * - * - \b USB_INTLPM_ERROR a bus error occurred in the transmission of an LPM - * transaction. - * - \b USB_INTLPM_RESUME the USB controller has resumed from LPM low power - * state. - * - \b USB_INTLPM_INCOMPLETE the LPM transaction failed because a timeout - * occurred or there were bit errors in the response for three attempts. - * - \b USB_INTLPM_ACK the device has acknowledged an LPM transaction. - * - \b USB_INTLPM_NYET the device has responded with a NYET to an LPM - * transaction. - * - \b USB_INTLPM_STALL the device has stalled an LPM transaction. - * - * The valid interrupt status bits when the USB controller is acting as a - * device are the following: - * - * - \b USB_INTLPM_ERROR an LPM transaction was received that has an - * unsupported link state field. The transaction was stalled, but the - * requested link state can still be read using the md_usb_lpm_link_state_get() - * function. - * - \b USB_INTLPM_RESUME the USB controller has resumed from the LPM low - * power state. - * - \b USB_INTLPM_INCOMPLETE the USB controller responded to an LPM - * transaction with a NYET because data was still in the transmit FIFOs. - * - \b USB_INTLPM_ACK the USB controller acknowledged an LPM transaction and - * is now in the LPM suspend mode. - * - \b USB_INTLPM_NYET the USB controller responded to an LPM transaction - * with a NYET because LPM transactions are not yet enabled by a call to - * md_usb_dev_lpm_enable(). - * - \b USB_INTLPM_STALL the USB controller has stalled an incoming LPM - * transaction. - * - * @note This function must only be called in host mode. The USB LPM feature - * is not available on all ES32 devices. Please consult the data sheet for - * the ES32 device that you are using to determine if this feature is - * available. - * @param ui32Ints specifies which LPM interrupts to enable. - * @retval None. - */ -void md_usb_lpm_int_enable(uint32_t ui32Ints) -{ -} - -/** - * @brief Disables LPM interrupts. - * - * This function disables the LPM interrupts specified in the \e ui32Ints - * parameter, preventing them from triggering a USB interrupt. - * - * The valid interrupt status bits when the USB controller is acting as a host - * are the following: - * - * - \b USB_INTLPM_ERROR a bus error occurred in the transmission of an LPM - * transaction. - * - \b USB_INTLPM_RESUME the USB controller has resumed from LPM low power - * state. - * - \b USB_INTLPM_INCOMPLETE the LPM transaction failed because a timeout - * occurred or there were bit errors in the response for three attempts. - * - \b USB_INTLPM_ACK the device has acknowledged an LPM transaction. - * - \b USB_INTLPM_NYET the device has responded with a NYET to an LPM - * transaction. - * - \b USB_INTLPM_STALL the device has stalled an LPM transaction. - * - * The valid interrupt status bits when the USB controller is acting as a - * device are the following: - * - * - \b USB_INTLPM_ERROR an LPM transaction was received that has an - * unsupported link state field. The transaction was stalled, but the - * requested link state can still be read using the md_usb_lpm_link_state_get() - * function. - * - \b USB_INTLPM_RESUME the USB controller has resumed from the LPM low - * power state. - * - \b USB_INTLPM_INCOMPLETE the USB controller responded to an LPM - * transaction with a NYET because data was still in the transmit FIFOs. - * - \b USB_INTLPM_ACK the USB controller acknowledged an LPM transaction and - * is now in the LPM suspend mode. - * - \b USB_INTLPM_NYET the USB controller responded to an LPM transaction - * with a NYET because LPM transactions are not yet enabled by a call to - * md_usb_dev_lpm_enable(). - * - \b USB_INTLPM_STALL the USB controller has stalled an incoming LPM - * transaction. - * - * @note This function must only be called in host mode. The USB LPM feature - * is not available on all ES32 devices. Please consult the data sheet for - * the ES32 device that you are using to determine if this feature is - * available. - * @param ui32Ints specifies which LPM interrupts to disable. - * @retval None. - */ -void md_usb_lpm_int_disable(uint32_t ui32Ints) -{ -} - -/** - * @} USB_MD_PF_LPM - */ - -/** @addtogroup USB_MD_PF_ULPI USB Public ULPI Functions - * @{ - */ - -// -// ULPI is not supported by es32f0271 -// - -/** - * @brief Configures the USB controller's ULPI function. - * - * This function is used to configure the USB controller's ULPI function. - * The configuration options are set in the \e ui32Config parameter and are a - * logical OR of the following values: - * - * - \b USB_ULPI_EXTVBUS enables the external ULPI PHY as the source for VBUS - * signaling. - * - \b USB_ULPI_EXTVBUS_IND enables the external ULPI PHY to detect external - * VBUS over-current condition. - * - * @note The USB ULPI feature is not available on all Tiva devices. - * Please consult the data sheet for the Tiva device that you - * are using to determine if this feature is available. - * @param ui32Config contains the configuration options. - * @retval None. - */ -void md_usb_ulpi_config(uint32_t ui32Config) -{ -} - -/** - * @brief Enables the USB controller's ULPI function. - * - * This function enables the USB controller's ULPI function and must be - * called before attempting to access an external ULPI-connected USB PHY. - * - * @note The USB ULPI feature is not available on all Tiva devices. - * Please consult the data sheet for the Tiva device that you - * are using to determine if this feature is available. - * @param None. - * @retval None. - */ -void md_usb_ulpi_enable(void) -{ -} - -/** - * @brief Disables the USB controller's ULPI function. - * - * This function Disables the USB controller's ULPI function and must be - * called before attempting to access an external ULPI-connected USB PHY. - * - * @note The USB ULPI feature is not available on all Tiva devices. - * Please consult the data sheet for the Tiva device that you - * are using to determine if this feature is available. - * @param None. - * @retval None. - */ -void md_usb_ulpi_disable(void) -{ -} - -/** - * @brief Disables the USB controller's ULPI function. - * - * This function Disables the USB controller's ULPI function and must be - * called before attempting to access an external ULPI-connected USB PHY. - * - * @note The USB ULPI feature is not available on all Tiva devices. - * Please consult the data sheet for the Tiva device that you - * are using to determine if this feature is available. - * @param None. - * @retval None. - */ -uint8_t md_usb_ulpi_reg_read(uint8_t ui8Reg) -{ - return 0; -} - -/** - * @brief Writes a value to a register on an external ULPI-connected USB PHY. - * - * This function writes the register address specified in the \e ui8Reg - * parameter with the value specified in the \e ui8Data parameter using the - * ULPI function. This function is blocking and only returns when the - * write access completes. The function does not return if there is not a - * ULPI-connected USB PHY present. - * - * @note The USB ULPI feature is not available on all Tiva devices. - * Please consult the data sheet for the Tiva device that you - * are using to determine if this feature is available. - * @param ui8Reg specifies the register address to write. - * @param ui8Data specifies the data to write. - * @retval None. - */ -void md_usb_ulpi_reg_write(uint8_t ui8Reg, - uint8_t ui8Data) -{ -} - -/** - * @} USB_MD_PF_ULPI - */ - -/** @addtogroup USB_MD_PF_DMA USB Public DMA Functions - * @{ - */ - -// -// USB DMA is not supported by es32f0271 -// - -/** - * @brief Sets the DMA channel to use for a specified endpoint. - * - * This function is used to configure which DMA channel to use with a specified - * endpoint. Receive DMA channels can only be used with receive endpoints - * and transmit DMA channels can only be used with transmit endpoints. - * - * @note This function only has an effect on microcontrollers that have the - * ability to change the DMA channel for an endpoint. Calling this function - * on other devices has no effect. - * @param ui32Endpoint specifies which endpoint's FIFO address to return. - * @param ui32Channel specifies which DMA channel to use for which endpoint. - * @retval None. - */ -void md_usb_dma_endpoint_channel_set(uint32_t ui32Endpoint, - uint32_t ui32Channel) -{ - // - // It is not supported by es32f0271 - // - return; -} - -/** - * @brief Enable DMA on a specified endpoint. - * - * This function enables DMA on a specified endpoint and configures the mode - * according to the values in the \e ui32Flags parameter. The \e ui32Flags - * parameter must have \b USB_EP_DEV_IN or \b USB_EP_DEV_OUT set. Once this - * function is called the only DMA or error interrupts are generated by the - * USB controller. - * - * @note This function only has an effect on microcontrollers that have the - * ability to change the DMA channel for an endpoint. Calling this function - * on other devices has no effect. - * @param ui32Endpoint is the endpoint to access. - * @param ui32Flags specifies which direction and what mode to use when - * enabling DMA. - * @retval None. - */ -void md_usb_dma_endpoint_enable(uint32_t ui32Endpoint, - uint32_t ui32Flags) -{ - // - // It is not supported by es32f0271 - // - return; -} - -/** - * @brief Disable DMA on a specified endpoint. - * - * This function disables DMA on a specified endpoint to allow non-DMA USB - * transactions to generate interrupts normally. The \e ui32Flags parameter - * must be \b USB_EP_DEV_IN or \b USB_EP_DEV_OUT; all other bits are ignored. - * - * @note This function only has an effect on microcontrollers that have the - * ability to change the DMA channel for an endpoint. Calling this function - * on other devices has no effect. - * @param ui32Endpoint is the endpoint to access. - * @param ui32Flags specifies which direction to disable. - * @retval None. - */ -void md_usb_dma_endpoint_disable(uint32_t ui32Endpoint, - uint32_t ui32Flags) -{ - // - // It is not supported by es32f0271 - // - return; -} - -/** - * @brief Configure the DMA settings for an endpoint. - * - * This function configures the DMA settings for a specified endpoint without - * changing other options that may already be configured. In order for the - * DMA transfer to be enabled, the md_usb_dma_endpoint_enable() function must be - * called before starting the DMA transfer. The configuration - * options are passed in the \e ui32Config parameter and can have the values - * described below. - * - * One of the following values to specify direction: - * - \b USB_EP_HOST_OUT or \b USB_EP_DEV_IN - This setting is used with - * DMA transfers from memory to the USB controller. - * - \b USB_EP_HOST_IN or \b USB_EP_DEV_OUT - This setting is used with - * DMA transfers from the USB controller to memory. - * - * One of the following values: - * - \b USB_EP_DMA_MODE_0(default) - This setting is typically used for - * transfers that do not span multiple packets or when interrupts are - * required for each packet. - * - \b USB_EP_DMA_MODE_1 - This setting is typically used for - * transfers that span multiple packets and do not require interrupts - * between packets. - * - * Values only used with \b USB_EP_HOST_OUT or \b USB_EP_DEV_IN: - * - \b USB_EP_AUTO_SET - This setting is used to allow transmit DMA transfers - * to automatically be sent when a full packet is loaded into a FIFO. - * This is needed with \b USB_EP_DMA_MODE_1 to ensure that packets go - * out when the FIFO becomes full and the DMA has more data to send. - * - * Values only used with \b USB_EP_HOST_IN or \b USB_EP_DEV_OUT: - * - \b USB_EP_AUTO_CLEAR - This setting is used to allow receive DMA - * transfers to automatically be acknowledged as they are received. This is - * needed with \b USB_EP_DMA_MODE_1 to ensure that packets continue to - * be received and acknowledged when the FIFO is emptied by the DMA - * transfer. - * - * Values only used with \b USB_EP_HOST_IN: - * - \b USB_EP_AUTO_REQUEST - This setting is used to allow receive DMA - * transfers to automatically request a new IN transaction when the - * previous transfer has emptied the FIFO. This is typically used in - * conjunction with \b USB_EP_AUTO_CLEAR so that receive DMA transfers - * can continue without interrupting the main processor. - * - * @note This function only has an effect on microcontrollers that have the - * ability to change the DMA channel for an endpoint. Calling this function - * on other devices has no effect. - * @param ui32Endpoint is the endpoint to access. - * @param ui32Config specifies the configuration options for an endpoint. - * @retval None. - */ -void md_usb_dma_endpoint_config(uint32_t ui32Endpoint, uint32_t ui32Config) -{ - // - //Chose endpoint. - // - USB->INDEX = (uint8_t)USBEPToIndex(ui32Endpoint); - - // - // Host out or device in. - // - if ((ui32Config & USB_EP_HOST_OUT) && (ui32Config & USB_EP_AUTO_SET)) - { - USB->CSR0H_TXCSRH |= USB_CSR0H_TXCSRH_AUTOSET_MSK; - } - else - { - if (ui32Config & USB_EP_AUTO_REQUEST) - { - USB->RXCSR2 |= USB_RXCSRH_AUTOREQ_MSK; - } - - if (ui32Config & USB_EP_AUTO_CLEAR) - { - USB->RXCSR2 |= USB_RXCSRH_AUTOCLR_MSK; - } - } -} - -/** - * @brief Assigns and configures an endpoint to a specified integrated USB DMA - * channel. - * - * This function assigns an endpoint and configures the settings for a - * USB DMA channel. The \e ui32Endpoint parameter is one of the - * \b USB_EP_* values and the \e ui32Channel value is a zero-based index of - * the DMA channel to configure. The \e ui32Config parameter is a combination - * of the \b USB_DMA_CFG_* values using the following guidelines. - * - * Use one of the following to set the DMA burst mode: - * - \b USB_DMA_CFG_BURST_NONE disables bursting. - * - \b USB_DMA_CFG_BURST_4 sets the DMA burst size to 4 words. - * - \b USB_DMA_CFG_BURST_8 sets the DMA burst size to 8 words. - * - \b USB_DMA_CFG_BURST_16 sets the DMA burst size to 16 words. - * - * Use one of the following to set the DMA mode: - * - \b USB_DMA_CFG_MODE_0 is typically used when only a single packet is - * being sent via DMA and triggers one completion interrupt per packet. - * - \b USB_DMA_CFG_MODE_1 is typically used when multiple packets are being - * sent via DMA and triggers one completion interrupt per transfer. - * - * Use one of the following to set the direction of the transfer: - * - \b USB_DMA_CFG_DIR_RX selects a DMA transfer from the endpoint to a - * memory location. - * - \b USB_DMA_CFG_DIR_TX selects a DMA transfer to the endpoint from a - * memory location. - * - * The following two optional settings allow an application to immediately - * enable the DMA transfer and/or DMA interrupts when configuring the DMA - * channel: - * - \b USB_DMA_CFG_INT_EN enables interrupts for this channel immediately so - * that an added call to md_usb_dma_channel_int_enable() is not necessary. - * - \b USB_DMA_CFG_EN enables the DMA channel immediately so that an added - * call to md_usb_dma_channel_enable() is not necessary. - * - * @note This feature is not available on all ES32 devices. Please - * check the data sheet to determine if the USB controller has a DMA - * controller or if it must use the DMA controller for DMA transfers. - * @param ui32Channel specifies which DMA channel to access. - * @param ui32Endpoint is the endpoint to assign to the USB DMA channel. - * @param ui32Config is used to specify the configuration of the USB DMA channel. - * @retval None. - */ -void md_usb_dma_channel_config(uint32_t ui32Channel, - uint32_t ui32Endpoint, uint32_t ui32Config) -{ - // - // It is not supported by es32f0271 - // -} - -/** - * @brief Sets the source or destination address for an integrated USB DMA transfer - * on a specified channel. - * - * This function sets the source or destination address for the USB DMA - * channel number specified in the \e ui32Channel parameter. The - * \e ui32Channel value is a zero-based index of the USB DMA channel. The - * \e pvAddress parameter is a source address if the transfer type for the DMA - * channel is transmit and a destination address if the transfer type is - * receive. - * - * @note This feature is not available on all ES32 devices. Please - * check the data sheet to determine if the USB controller has a DMA - * controller or if it must use the DMA controller for DMA transfers. - * @param ui32Channel specifies which DMA channel to access. - * @param pvAddress specifies the source or destination address for the USB - * DMA transfer. - * @retval None. - */ -void md_usb_dma_channel_address_set(uint32_t ui32Channel, - void *pvAddress) -{ - // - // It is not supported by es32f0271 - // - return; -} - -/** - * @brief Returns the source or destination address for the specified integrated USB - * DMA channel. - * - * This function returns the DMA address for the channel number specified - * in the \e ui32Channel parameter. The \e ui32Channel value is a zero-based - * index of the DMA channel to query. This function must not be used on - * devices that return \b USB_CONTROLLER_VER_0 from the USBControllerVersion() - * function. - * - * @note This feature is not available on all ES32 devices. Please - * check the data sheet to determine if the USB controller has a DMA - * controller or if it must use the DMA controller for DMA transfers. - * @param ui32Channel specifies which DMA channel to access. - * @retval The current DMA address for a USB DMA channel. - */ -void *md_usb_dma_channel_address_get(uint32_t ui32Channel) -{ - // - // It is not supported by es32f0271 - // - return 0; -} - -/** - * @brief Sets the transfer count for an integrated USB DMA channel. - * - * This function sets the USB DMA transfer count in bytes for the channel - * number specified in the \e ui32Channel parameter. The \e ui32Channel - * value is a zero-based index of the DMA channel. - * - * @note This feature is not available on all ES32 devices. Please - * check the data sheet to determine if the USB controller has a DMA - * controller or if it must use the DMA controller for DMA transfers. - * @param ui32Count specifies the number of bytes to transfer. - * @param ui32Channel specifies which DMA channel to access. - * @retval None. - */ -void md_usb_dma_channel_count_set(uint32_t ui32Count, - uint32_t ui32Channel) -{ - // - // It is not supported by es32f0271 - // - return; -} - -/** - * @brief Returns the transfer count for an integrated USB DMA channel. - * - * This function returns the USB DMA transfer count in bytes for the channel - * number specified in the \e ui32Channel parameter. The \e ui32Channel value - * is a zero-based index of the DMA channel to query. - * - * @note This feature is not available on all ES32 devices. Please - * check the data sheet to determine if the USB controller has a DMA - * controller or if it must use the DMA controller for DMA transfers. - * @param ui32Channel specifies which DMA channel to access. - * @retval The current count for a USB DMA channel. - */ -uint32_t md_usb_dma_channel_count_get(uint32_t ui32Channel) -{ - // - // It is not supported by es32f0271 - // - return 0; -} - -/** - * @brief Returns the available number of integrated USB DMA channels. - * - * This function returns the total number of DMA channels available when using - * the integrated USB DMA controller. This function returns 0 if the - * integrated controller is not present. - * - * @note The number of integrated USB DMA channels or zero if the - * integrated USB DMA controller is not present. - * @param None. - * @retval The number of integrated USB DMA channels or zero if the - * integrated USB DMA controller is not present. - */ -uint32_t md_usb_dma_channel_number(void) -{ - // - // It is not supported by es32f0271 - // - return 0; -} - -/** - * @brief Enable interrupts for a specified integrated USB DMA channel. - * - * This function enables the USB DMA channel interrupt based on the - * \e ui32Channel parameter. The \e ui32Channel value is a zero-based - * index of the USB DMA channel. Once enabled, the md_usb_dma_channel_int_status() - * function returns if a DMA channel has generated an interrupt. - * - * @note The number of integrated USB DMA channels or zero if the - * integrated USB DMA controller is not present. - * @param ui32Channel specifies which DMA channel interrupt to enable. - * @retval None. - */ -void md_usb_dma_channel_int_enable(uint32_t ui32Channel) -{ - // - // It is not supported by es32f0271 - // -} - -/** - * @brief Return the current status of the integrated USB DMA interrupts. - * - * This function returns the current bit-mapped interrupt status for all USB - * DMA channel interrupt sources. Calling this function automatically clears - * all currently pending USB DMA interrupts. - * - * @param None. - * @retval None. - */ -uint32_t md_usb_dma_channel_int_status(void) -{ - return 0; -} - -/** - * @brief Enables USB DMA for a specified channel. - * - * This function enables the USB DMA channel passed in the \e ui32Channel - * parameter. The \e ui32Channel value is a zero-based index of the USB DMA - * channel. - * - * @note This feature is not available on all ES32 devices. Please - * check the data sheet to determine if the USB controller has a DMA - * controller. - * @param ui32Channel specifies the USB DMA channel to enable. - * @retval None. - */ -void md_usb_dma_channel_enable(uint32_t ui32Channel) -{ - // - // DMA1 will be used by es32f0271 - // - SET_BIT(*(&DMA1->CSR0 + 4 * ui32Channel), DMA_CSR0_CHEN_MSK); -} - -/** - * @brief Disables USB DMA for a specified channel. - * - * This function Disables the USB DMA channel passed in the \e ui32Channel - * parameter. The \e ui32Channel value is a zero-based index of the USB DMA - * channel. - * - * @note This feature is not available on all ES32 devices. Please - * check the data sheet to determine if the USB controller has a DMA - * controller. - * @param ui32Channel specifies the USB DMA channel to Disable. - * @retval None. - */ -void md_usb_dma_channel_disable(uint32_t ui32Channel) -{ - // - // DMA1 will be used by es32f0271 - // - CLEAR_BIT(*(&DMA1->CSR0 + 4 * ui32Channel), DMA_CSR0_CHEN_MSK); -} - -/** - * @brief Check if the USB channel is enabled. - * - * @note This feature is not available on all ES32 devices. Please - * check the data sheet to determine if the USB controller has a DMA - * controller. - * @param ui32Channel specifies the USB DMA channel. - * @retval Return 1 if the channel is enabled. - */ -uint32_t md_usb_dma_channel_isenabled(uint32_t ui32Channel) -{ - if (*((uint32_t *)(&DMA1->CSR0 + ui32Channel * 4)) & DMA_CSR0_CHEN_MSK) - return 1; - - return 0; -} - -/** - * @brief Returns the current status for an integrated USB DMA channel. - * - * This function returns the current status for the USB DMA channel specified - * by the \e ui32Channel parameter. The \e ui32Channel value is a zero-based - * index of the USB DMA channel to query. - * - * @note This feature is not available on all ES32 devices. Please - * check the data sheet to determine if the USB controller has a DMA - * controller or if it must use the DMA controller for DMA transfers. - * @param ui32Channel specifies the USB DMA channel to Disable. - * @retval Returns zero or \b USB_DMACTL0_ERR if there is a pending error - * condition on a DMA channel. - */ -uint32_t md_usb_dma_channel_status(uint32_t ui32Channel) -{ - // - // It is not supported by es32f0271 - // - return 0; -} - -/** - * @brief Clears the integrated USB DMA status for a specified channel. - * - * This function clears the USB DMA channel status for the channel specified - * by the \e ui32Channel parameter. The \e ui32Channel value is a zero-based - * index of the USB DMA channel to query. The \e ui32Status parameter - * specifies the status bits to clear and must be the valid values that are - * returned from a call to the md_usb_dma_channel_status() function. - * - * @note This feature is not available on all ES32 devices. Please - * check the data sheet to determine if the USB controller has a DMA - * controller or if it must use the DMA controller for DMA transfers. - * @param ui32Channel specifies the USB DMA channel to Disable. - * @retval None. - */ -void md_usb_dma_channel_status_clear(uint32_t ui32Channel, - uint32_t ui32Status) -{ - // - // It is not supported by es32f0271 - // -} - -/** - * @} USB_MD_PF_DMA - */ - -/** - * @} USB_MD_Public_Functions - */ - -/** - * @} USB - */ - -#endif - -/** - * @} Micro_Driver - */ - -/******************* (C) COPYRIGHT Eastsoft Microelectronics END OF MAIN.C****/ diff --git a/bsp/essemi/es32f0271/libraries/ES32F027x_MD_StdPeriph_Driver/Source/md_wwdt.c b/bsp/essemi/es32f0271/libraries/ES32F027x_MD_StdPeriph_Driver/Source/md_wwdt.c deleted file mode 100644 index fdba390e17..0000000000 --- a/bsp/essemi/es32f0271/libraries/ES32F027x_MD_StdPeriph_Driver/Source/md_wwdt.c +++ /dev/null @@ -1,86 +0,0 @@ -/** - ****************************************************************************** - * @file md_wwdt.c - * @brief ES32F0271 WWDT Source File. - * - * @version V1.00.01 - * @date 4/12/2018 - * @author Eastsoft AE Team - * @note - * detailed description - * - * Copyright (C) 2018 Shanghai Eastsoft Microelectronics Co., Ltd. ALL rights reserved. - ******************************************************************************* - */ - -/* Includes -------------------------------------------------------------------*/ -#include "md_rcu.h" -#include "md_wwdt.h" - -/** @addtogroup Micro_Driver - * @{ - */ - -#if defined (WWDT) - -/** @defgroup WWDT WWDT - * @brief WWDT micro driver - * @{ - */ - -/* Private types --------------------------------------------------------------*/ -/* Private variables ----------------------------------------------------------*/ -/* Private constants ----------------------------------------------------------*/ -/* Private macros -------------------------------------------------------------*/ - -/* Public functions -----------------------------------------------------------*/ -/** @addtogroup MD_RCU_Public_Functions RCU Public Functions - * @{ - */ -/** - * @brief De-initialize the GPIO registers to their default reset values. - * @param GPIOx GPIO Instance - * @retval An ErrorStatus enumeration value: - * - SUCCESS: GPIO registers are de-initialized - * - ERROR: GPIO registers are not de-initialized - */ -void md_wwdt_init(WWDT_TypeDef *WWD, md_wwdt_inittypedef *WWDT_InitStruct) -{ - /* Check the parameters */ - assert_param(IS_MD_WWDT_ALL_INSTANCE(WWD)); - assert_param(IS_MD_WWDT_PRESCALER(WWDT_InitStruct->Prescaler)); - assert_param(IS_MD_WWDT_WINDOW(WWDT_InitStruct->Window)); - assert_param(IS_MD_WWDT_COUNTER(WWDT_InitStruct->Counter)); - assert_param(IS_MD_WWDT_EWI_MODE(WWDT_InitStruct->EWIMode)); - - if (WWDT_InitStruct->EWIMode == WWDT_EWI_ENABLE) - md_wwdt_enable_ier_ewis(WWD); - else - md_wwdt_disable_idr_ewis(WWD); - - md_wwdt_set_con_t(WWD, WWDT_InitStruct->Counter); - md_wwdt_set_cfg_wdgtb(WWD, WWDT_InitStruct->Prescaler); - md_wwdt_set_cfg_w(WWD, WWDT_InitStruct->Window); - md_wwdt_enable_con_wdga(WWD); -} - - - - - - - - - - - -/** - * @} GPIO - */ -#endif - -/** - * @} Micro_Driver - */ - -/******************* (C) COPYRIGHT Eastsoft Microelectronics *****END OF FILE****/ diff --git a/bsp/essemi/es32f0271/libraries/SConscript b/bsp/essemi/es32f0271/libraries/SConscript deleted file mode 100644 index 00008f5fca..0000000000 --- a/bsp/essemi/es32f0271/libraries/SConscript +++ /dev/null @@ -1,32 +0,0 @@ -import rtconfig -Import('RTT_ROOT') -from building import * - -# get current directory -cwd = GetCurrentDir() - -# The set of source files associated with this SConscript file. -src = [] - -src += Glob('ES32F027x_MD_StdPeriph_Driver/Source/*.c') - -#add for startup script -if rtconfig.CROSS_TOOL == 'gcc': - src = src + ['CMSIS/Device/EastSoft/ES32F0271/Startup/gcc/startup_es32f027x.s'] -elif rtconfig.CROSS_TOOL == 'keil': - src = src + ['CMSIS/Device/EastSoft/ES32F0271/Startup/keil/startup_es32f027x.s'] -elif rtconfig.CROSS_TOOL == 'iar': - src = src + ['CMSIS/Device/EastSoft/ES32F0271/Startup/iar/startup_es32f027x.s'] - -src = src + ['CMSIS/Device/EastSoft/ES32F0271/System/system_es32f027x.c'] - -path = [cwd + '/CMSIS/Device/EastSoft/ES32F0271/Include', - cwd + '/CMSIS/Device/EastSoft/ES32F0271/Include/ES32F0271', - cwd + '/CMSIS/Device/EastSoft/ES32F0271/System', - cwd + '/CMSIS/Include', - cwd + '/', - cwd + '/ES32F027x_MD_StdPeriph_Driver/Include'] - -group = DefineGroup('Libraries', src, depend = [''], CPPPATH = path) - -Return('group') diff --git a/bsp/essemi/es32f0271/libraries/usblib/drivers/type.h b/bsp/essemi/es32f0271/libraries/usblib/drivers/type.h deleted file mode 100644 index 3d6a812bf6..0000000000 --- a/bsp/essemi/es32f0271/libraries/usblib/drivers/type.h +++ /dev/null @@ -1,41 +0,0 @@ -/** - ************************************************************************************** - * @file type.h - * @brief Common types and macros. - * @data 12/21/2018 - * @author Eastsoft AE Team - * @note - * - * Copyright (C) 2018 Shanghai Eastsoft Microelectronics Co., Ltd. ALL rights reserved. - * - ************************************************************************************** - */ - -#ifndef __TYPES_H__ -#define __TYPES_H__ - -//***************************************************************************** -// -// Macros for hardware access. -// -//***************************************************************************** -#define HWREG(x) \ - (*((volatile uint32_t *)(x))) -#define HWREGH(x) \ - (*((volatile uint16_t *)(x))) -#define HWREGB(x) \ - (*((volatile uint8_t *)(x))) -#define HWREGBITW(x, b) \ - HWREG(((uint32_t)(x) & 0xF0000000) | 0x02000000 | \ - (((uint32_t)(x) & 0x000FFFFF) << 5) | ((b) << 2)) -#define HWREGBITH(x, b) \ - HWREGH(((uint32_t)(x) & 0xF0000000) | 0x02000000 | \ - (((uint32_t)(x) & 0x000FFFFF) << 5) | ((b) << 2)) -#define HWREGBITB(x, b) \ - HWREGB(((uint32_t)(x) & 0xF0000000) | 0x02000000 | \ - (((uint32_t)(x) & 0x000FFFFF) << 5) | ((b) << 2)) - - -#endif - -/******************* (C) COPYRIGHT Eastsoft Microelectronics Co., Ltd. *** END OF FILE ****/ diff --git a/bsp/essemi/es32f0271/libraries/usblib/drivers/usb_lowlayer_api.h b/bsp/essemi/es32f0271/libraries/usblib/drivers/usb_lowlayer_api.h deleted file mode 100644 index 5fee2e973e..0000000000 --- a/bsp/essemi/es32f0271/libraries/usblib/drivers/usb_lowlayer_api.h +++ /dev/null @@ -1,728 +0,0 @@ -/** - ************************************************************************************** - * @file usb_lowlayer_api.h - * @brief USB library lower layer api - * @data 11/9/2018 - * @author Eastsoft AE Team - * @note - * - * Copyright (C) 2018 Shanghai Eastsoft Microelectronics Co., Ltd. ALL rights reserved. - * - ************************************************************************************** - */ - -/* Includes-------------------------------------------------------------------*/ -#include "stdint.h" -#include - -#ifndef __USB_LOWLAYER_API_H__ -#define __USB_LOWLAYER_API_H__ - - -/** - * If building with a C++ compiler, make all of the definitions in this header - * have a C binding. - */ -#ifdef __cplusplus -extern "C" -{ -#endif - -/* Public constants -----------------------------------------------------------*/ - -//***************************************************************************** -// -// The following are values that can be passed to md_usb_hosdev_int_enable() and -// md_usb_hosdev_int_disable() as the ui32Flags parameter, and are returned from -// md_usb_hosdev_int_status(). -// -//***************************************************************************** -#define USB_INTCTRL_ALL 0x000003FF // All control interrupt sources -#define USB_INTCTRL_STATUS 0x000000FF // Status Interrupts -#define USB_INTCTRL_VBUS_ERR 0x00000080 // VBUS Error -#define USB_INTCTRL_SESSION 0x00000040 // Session Start Detected -#define USB_INTCTRL_SESSION_END 0x00000040 // Session End Detected -#define USB_INTCTRL_DISCONNECT 0x00000020 // Disconnect Detected -#define USB_INTCTRL_CONNECT 0x00000010 // Device Connect Detected -#define USB_INTCTRL_SOF 0x00000008 // Start of Frame Detected -#define USB_INTCTRL_BABBLE 0x00000004 // Babble signaled -#define USB_INTCTRL_RESET 0x00000004 // Reset signaled -#define USB_INTCTRL_RESUME 0x00000002 // Resume detected -#define USB_INTCTRL_SUSPEND 0x00000001 // Suspend detected -#define USB_INTCTRL_MODE_DETECT 0x00000200 // Mode value valid -#define USB_INTCTRL_POWER_FAULT 0x00000100 // Power Fault detected - -//***************************************************************************** -// -// The following are values that can be passed to md_usb_hosdev_endpoint_int_enable() -// and md_usb_hosdev_endpoint_int_disable() as the ui32Flags parameter, and -// are returned from md_usb_hosdev_endpoint_int_status(). -// -//***************************************************************************** -#define USB_INTEP_ALL 0xFFFFFFFF // Host IN Interrupts -#define USB_INTEP_HOST_IN 0xFFFE0000 // Host IN Interrupts -#define USB_INTEP_HOST_IN_15 0x80000000 // Endpoint 15 Host IN Interrupt -#define USB_INTEP_HOST_IN_14 0x40000000 // Endpoint 14 Host IN Interrupt -#define USB_INTEP_HOST_IN_13 0x20000000 // Endpoint 13 Host IN Interrupt -#define USB_INTEP_HOST_IN_12 0x10000000 // Endpoint 12 Host IN Interrupt -#define USB_INTEP_HOST_IN_11 0x08000000 // Endpoint 11 Host IN Interrupt -#define USB_INTEP_HOST_IN_10 0x04000000 // Endpoint 10 Host IN Interrupt -#define USB_INTEP_HOST_IN_9 0x02000000 // Endpoint 9 Host IN Interrupt -#define USB_INTEP_HOST_IN_8 0x01000000 // Endpoint 8 Host IN Interrupt -#define USB_INTEP_HOST_IN_7 0x00800000 // Endpoint 7 Host IN Interrupt -#define USB_INTEP_HOST_IN_6 0x00400000 // Endpoint 6 Host IN Interrupt -#define USB_INTEP_HOST_IN_5 0x00200000 // Endpoint 5 Host IN Interrupt -#define USB_INTEP_HOST_IN_4 0x00100000 // Endpoint 4 Host IN Interrupt -#define USB_INTEP_HOST_IN_3 0x00080000 // Endpoint 3 Host IN Interrupt -#define USB_INTEP_HOST_IN_2 0x00040000 // Endpoint 2 Host IN Interrupt -#define USB_INTEP_HOST_IN_1 0x00020000 // Endpoint 1 Host IN Interrupt - -#define USB_INTEP_DEV_OUT 0xFFFE0000 // Device OUT Interrupts -#define USB_INTEP_DEV_OUT_15 0x80000000 // Endpoint 15 Device OUT Interrupt -#define USB_INTEP_DEV_OUT_14 0x40000000 // Endpoint 14 Device OUT Interrupt -#define USB_INTEP_DEV_OUT_13 0x20000000 // Endpoint 13 Device OUT Interrupt -#define USB_INTEP_DEV_OUT_12 0x10000000 // Endpoint 12 Device OUT Interrupt -#define USB_INTEP_DEV_OUT_11 0x08000000 // Endpoint 11 Device OUT Interrupt -#define USB_INTEP_DEV_OUT_10 0x04000000 // Endpoint 10 Device OUT Interrupt -#define USB_INTEP_DEV_OUT_9 0x02000000 // Endpoint 9 Device OUT Interrupt -#define USB_INTEP_DEV_OUT_8 0x01000000 // Endpoint 8 Device OUT Interrupt -#define USB_INTEP_DEV_OUT_7 0x00800000 // Endpoint 7 Device OUT Interrupt -#define USB_INTEP_DEV_OUT_6 0x00400000 // Endpoint 6 Device OUT Interrupt -#define USB_INTEP_DEV_OUT_5 0x00200000 // Endpoint 5 Device OUT Interrupt -#define USB_INTEP_DEV_OUT_4 0x00100000 // Endpoint 4 Device OUT Interrupt -#define USB_INTEP_DEV_OUT_3 0x00080000 // Endpoint 3 Device OUT Interrupt -#define USB_INTEP_DEV_OUT_2 0x00040000 // Endpoint 2 Device OUT Interrupt -#define USB_INTEP_DEV_OUT_1 0x00020000 // Endpoint 1 Device OUT Interrupt - -#define USB_INTEP_HOST_OUT 0x0000FFFE // Host OUT Interrupts -#define USB_INTEP_HOST_OUT_15 0x00008000 // Endpoint 15 Host OUT Interrupt -#define USB_INTEP_HOST_OUT_14 0x00004000 // Endpoint 14 Host OUT Interrupt -#define USB_INTEP_HOST_OUT_13 0x00002000 // Endpoint 13 Host OUT Interrupt -#define USB_INTEP_HOST_OUT_12 0x00001000 // Endpoint 12 Host OUT Interrupt -#define USB_INTEP_HOST_OUT_11 0x00000800 // Endpoint 11 Host OUT Interrupt -#define USB_INTEP_HOST_OUT_10 0x00000400 // Endpoint 10 Host OUT Interrupt -#define USB_INTEP_HOST_OUT_9 0x00000200 // Endpoint 9 Host OUT Interrupt -#define USB_INTEP_HOST_OUT_8 0x00000100 // Endpoint 8 Host OUT Interrupt -#define USB_INTEP_HOST_OUT_7 0x00000080 // Endpoint 7 Host OUT Interrupt -#define USB_INTEP_HOST_OUT_6 0x00000040 // Endpoint 6 Host OUT Interrupt -#define USB_INTEP_HOST_OUT_5 0x00000020 // Endpoint 5 Host OUT Interrupt -#define USB_INTEP_HOST_OUT_4 0x00000010 // Endpoint 4 Host OUT Interrupt -#define USB_INTEP_HOST_OUT_3 0x00000008 // Endpoint 3 Host OUT Interrupt -#define USB_INTEP_HOST_OUT_2 0x00000004 // Endpoint 2 Host OUT Interrupt -#define USB_INTEP_HOST_OUT_1 0x00000002 // Endpoint 1 Host OUT Interrupt - -#define USB_INTEP_DEV_IN 0x0000FFFE // Device IN Interrupts -#define USB_INTEP_DEV_IN_15 0x00008000 // Endpoint 15 Device IN Interrupt -#define USB_INTEP_DEV_IN_14 0x00004000 // Endpoint 14 Device IN Interrupt -#define USB_INTEP_DEV_IN_13 0x00002000 // Endpoint 13 Device IN Interrupt -#define USB_INTEP_DEV_IN_12 0x00001000 // Endpoint 12 Device IN Interrupt -#define USB_INTEP_DEV_IN_11 0x00000800 // Endpoint 11 Device IN Interrupt -#define USB_INTEP_DEV_IN_10 0x00000400 // Endpoint 10 Device IN Interrupt -#define USB_INTEP_DEV_IN_9 0x00000200 // Endpoint 9 Device IN Interrupt -#define USB_INTEP_DEV_IN_8 0x00000100 // Endpoint 8 Device IN Interrupt -#define USB_INTEP_DEV_IN_7 0x00000080 // Endpoint 7 Device IN Interrupt -#define USB_INTEP_DEV_IN_6 0x00000040 // Endpoint 6 Device IN Interrupt -#define USB_INTEP_DEV_IN_5 0x00000020 // Endpoint 5 Device IN Interrupt -#define USB_INTEP_DEV_IN_4 0x00000010 // Endpoint 4 Device IN Interrupt -#define USB_INTEP_DEV_IN_3 0x00000008 // Endpoint 3 Device IN Interrupt -#define USB_INTEP_DEV_IN_2 0x00000004 // Endpoint 2 Device IN Interrupt -#define USB_INTEP_DEV_IN_1 0x00000002 // Endpoint 1 Device IN Interrupt - -#define USB_INTEP_0 0x00000001 // Endpoint 0 Interrupt - -//***************************************************************************** -// -// The following are values that are returned from md_usb_hos_speed_get() 0r -// md_usb_dev_speed_get(). -// -//***************************************************************************** -#define USB_UNDEF_SPEED 0x80000000 // Current speed is undefined -#define USB_HIGH_SPEED 0x00000002 // Current speed is High Speed -#define USB_FULL_SPEED 0x00000001 // Current speed is Full Speed -#define USB_LOW_SPEED 0x00000000 // Current speed is Low Speed - -//***************************************************************************** -// -// The following are values that are returned from md_usb_hosdev_endpoint_status(). The -// USB_HOST_* values are used when the USB controller is in host mode and the -// USB_DEV_* values are used when the USB controller is in device mode. -// -//***************************************************************************** -#define USB_HOST_IN_STATUS 0x114F0000 // Mask of all host IN interrupts -#define USB_HOST_IN_PID_ERROR 0x10000000 // Stall on this endpoint received -#define USB_HOST_IN_NOT_COMP 0x01000000 // Device failed to respond -#define USB_HOST_IN_STALL 0x00400000 // Stall on this endpoint received -#define USB_HOST_IN_DATA_ERROR 0x00080000 // CRC or bit-stuff error -// (ISOC Mode) -#define USB_HOST_IN_NAK_TO 0x00080000 // NAK received for more than the -// specified timeout period -#define USB_HOST_IN_ERROR 0x00040000 // Failed to communicate with a -// device -#define USB_HOST_IN_FIFO_FULL 0x00020000 // RX FIFO full -#define USB_HOST_IN_PKTRDY 0x00010000 // Data packet ready -#define USB_HOST_OUT_STATUS 0x000000A7 // Mask of all host OUT interrupts -#define USB_HOST_OUT_NAK_TO 0x00000080 // NAK received for more than the -// specified timeout period -#define USB_HOST_OUT_NOT_COMP 0x00000080 // No response from device -// (ISOC mode) -#define USB_HOST_OUT_STALL 0x00000020 // Stall on this endpoint received -#define USB_HOST_OUT_ERROR 0x00000004 // Failed to communicate with a -// device -#define USB_HOST_OUT_FIFO_NE 0x00000002 // TX FIFO is not empty -#define USB_HOST_OUT_PKTPEND 0x00000001 // Transmit still being transmitted -#define USB_HOST_EP0_NAK_TO 0x00000080 // NAK received for more than the -// specified timeout period -#define USB_HOST_EP0_STATUS 0x00000040 // This was a status packet -#define USB_HOST_EP0_ERROR 0x00000010 // Failed to communicate with a -// device -#define USB_HOST_EP0_RX_STALL 0x00000004 // Stall on this endpoint received -#define USB_HOST_EP0_RXPKTRDY 0x00000001 // Receive data packet ready -#define USB_DEV_RX_PID_ERROR 0x01000000 // PID error in isochronous -// transfer -#define USB_DEV_RX_SENT_STALL 0x00400000 // Stall was sent on this endpoint -#define USB_DEV_RX_DATA_ERROR 0x00080000 // CRC error on the data -#define USB_DEV_RX_OVERRUN 0x00040000 // OUT packet was not loaded due to -// a full FIFO -#define USB_DEV_RX_FIFO_FULL 0x00020000 // RX FIFO full -#define USB_DEV_RX_PKT_RDY 0x00010000 // Data packet ready -#define USB_DEV_TX_NOT_COMP 0x00000080 // Large packet split up, more data -// to come -#define USB_DEV_TX_SENT_STALL 0x00000020 // Stall was sent on this endpoint -#define USB_DEV_TX_UNDERRUN 0x00000004 // IN received with no data ready -#define USB_DEV_TX_FIFO_NE 0x00000002 // The TX FIFO is not empty -#define USB_DEV_TX_TXPKTRDY 0x00000001 // Transmit still being transmitted -#define USB_DEV_EP0_SETUP_END 0x00000010 // Control transaction ended before -// Data End seen -#define USB_DEV_EP0_SENT_STALL 0x00000004 // Stall was sent on this endpoint -#define USB_DEV_EP0_IN_PKTPEND 0x00000002 // Transmit data packet pending -#define USB_DEV_EP0_OUT_PKTRDY 0x00000001 // Receive data packet ready - -//***************************************************************************** -// -// The following are values that can be passed to md_usb_hos_endpoint_config_set() and -// md_usb_dev_endpoint_config_set() as the ui32Flags parameter. -// -//***************************************************************************** -#define USB_EP_AUTO_SET 0x00000001 // Auto set feature enabled -#define USB_EP_AUTO_REQUEST 0x00000002 // Auto request feature enabled -#define USB_EP_AUTO_CLEAR 0x00000004 // Auto clear feature enabled -#define USB_EP_DUAL_BUFFERING 0x00000008 // Dual buffering enabled -#define USB_EP_DMA_MODE_0 0x00000008 // Enable DMA access using mode 0 -#define USB_EP_DMA_MODE_1 0x00000010 // Enable DMA access using mode 1 -#define USB_EP_DIS_NYET 0x00000020 // Disable NYET response for -// high-speed Bulk and Interrupt -// endpoints in device mode. -#define USB_EP_MODE_ISOC 0x00000000 // Isochronous endpoint -#define USB_EP_MODE_BULK 0x00000100 // Bulk endpoint -#define USB_EP_MODE_INT 0x00000200 // Interrupt endpoint -#define USB_EP_MODE_CTRL 0x00000300 // Control endpoint -#define USB_EP_MODE_MASK 0x00000300 // Mode Mask -#define USB_EP_SPEED_LOW 0x00000000 // Low Speed -#define USB_EP_SPEED_FULL 0x00001000 // Full Speed -#define USB_EP_SPEED_HIGH 0x00004000 // High Speed -#define USB_EP_HOST_IN 0x00000000 // Host IN endpoint -#define USB_EP_HOST_OUT 0x00002000 // Host OUT endpoint -#define USB_EP_DEV_IN 0x00002000 // Device IN endpoint -#define USB_EP_DEV_OUT 0x00000000 // Device OUT endpoint - -//***************************************************************************** -// -// The following are values that can be passed to md_usb_hos_pwr_config() as the -// ui32Flags parameter. -// -//***************************************************************************** -#define USB_HOST_PWRFLT_LOW 0x00000010 -#define USB_HOST_PWRFLT_HIGH 0x00000030 -#define USB_HOST_PWRFLT_EP_NONE 0x00000000 -#define USB_HOST_PWRFLT_EP_TRI 0x00000140 -#define USB_HOST_PWRFLT_EP_LOW 0x00000240 -#define USB_HOST_PWRFLT_EP_HIGH 0x00000340 -#define USB_HOST_PWREN_MAN_LOW 0x00000000 -#define USB_HOST_PWREN_MAN_HIGH 0x00000001 -#define USB_HOST_PWREN_AUTOLOW 0x00000002 -#define USB_HOST_PWREN_AUTOHIGH 0x00000003 -#define USB_HOST_PWREN_FILTER 0x00010000 - -//***************************************************************************** -// -// The following are the valid values that can be passed to the -// md_usb_hos_lpm_config() function in the ui32Config parameter. -// -//***************************************************************************** -#define USB_HOST_LPM_RMTWAKE 0x00000100 -#define USB_HOST_LPM_L1 0x00000001 - -//***************************************************************************** -// -// The following are the valid values that can be passed to the -// md_usb_dev_lpm_config() function in the ui32Config parameter. -// -//***************************************************************************** -#define USB_DEV_LPM_NAK 0x00000010 -#define USB_DEV_LPM_NONE 0x00000000 -#define USB_DEV_LPM_EN 0x0000000c -#define USB_DEV_LPM_EXTONLY 0x00000004 - -//***************************************************************************** -// -// The following are the valid values that are returned from the -// md_usb_lpm_link_state_get() function. -// -//***************************************************************************** -#define USB_DEV_LPM_LS_RMTWAKE 0x00000100 -#define USB_DEV_LPM_LS_L1 0x00000001 - -//***************************************************************************** -// -// The following are the valid values that are passed to the md_usb_lpm_int_enable() -// or md_usb_lpm_int_disable() functions or are returned from the md_usb_lpm_status() -// function. -// -//***************************************************************************** -#define USB_INTLPM_ERROR 0x00000020 -#define USB_INTLPM_RESUME 0x00000010 -#define USB_INTLPM_INCOMPLETE 0x00000008 -#define USB_INTLPM_ACK 0x00000004 -#define USB_INTLPM_NYET 0x00000002 -#define USB_INTLPM_STALL 0x00000001 - -//***************************************************************************** -// -// The following are the valid values that are passed to the md_usb_clock_enable() -// functions. -// -//***************************************************************************** -#define USB_CLOCK_INTERNAL 0x00000200 -#define USB_CLOCK_EXTERNAL 0x00000300 - -//***************************************************************************** -// -// The configuration options used with the md_usb_ulpi_config() API. -// -//***************************************************************************** -#define USB_ULPI_EXTVBUS 0x00000001 -#define USB_ULPI_EXTVBUS_IND 0x00000002 - -//***************************************************************************** -// -// The following are special values that can be passed to -// md_usb_hos_endpoint_config_set() as the ui32NAKPollInterval parameter. -// -//***************************************************************************** -#define MAX_NAK_LIMIT 31 // Maximum NAK interval -#define DISABLE_NAK_LIMIT 0 // No NAK timeouts - -//***************************************************************************** -// -// This value specifies the maximum size of transfers on endpoint 0 as 64 -// bytes. This value is fixed in hardware as the FIFO size for endpoint 0. -// -//***************************************************************************** -#define MAX_PACKET_SIZE_EP0 64 - -//***************************************************************************** -// -// These values are used to indicate which endpoint to access. -// -//***************************************************************************** -#define USB_EP_0 0x00000000 // Endpoint 0 -#define USB_EP_1 0x00000010 // Endpoint 1 -#define USB_EP_2 0x00000020 // Endpoint 2 -#define USB_EP_3 0x00000030 // Endpoint 3 -#define USB_EP_4 0x00000040 // Endpoint 4 -#define USB_EP_5 0x00000050 // Endpoint 5 -#define USB_EP_6 0x00000060 // Endpoint 6 -#define USB_EP_7 0x00000070 // Endpoint 7 -#define NUM_USB_EP 8 // Number of supported endpoints - -//***************************************************************************** -// -// These macros allow conversion between 0-based endpoint indices and the -// USB_EP_x values required when calling various USB APIs. -// -//***************************************************************************** -#define IndexToUSBEP(x) ((x) << 4) -#define USBEPToIndex(x) ((x) >> 4) - -//***************************************************************************** -// -// The following are values that can be passed to md_usb_hosdev_fifo_config_set() as the -// ui32FIFOSize parameter. -// -//***************************************************************************** -#define USB_FIFO_SZ_8 0x00000000 // 8 byte FIFO -#define USB_FIFO_SZ_16 0x00000001 // 16 byte FIFO -#define USB_FIFO_SZ_32 0x00000002 // 32 byte FIFO -#define USB_FIFO_SZ_64 0x00000003 // 64 byte FIFO -#define USB_FIFO_SZ_128 0x00000004 // 128 byte FIFO -#define USB_FIFO_SZ_256 0x00000005 // 256 byte FIFO -#define USB_FIFO_SZ_512 0x00000006 // 512 byte FIFO -#define USB_FIFO_SZ_1024 0x00000007 // 1024 byte FIFO -#define USB_FIFO_SZ_2048 0x00000008 // 2048 byte FIFO - -//***************************************************************************** -// -// This macro allow conversion from a FIFO size label as defined above to -// a number of bytes -// -//***************************************************************************** -#define USBFIFOSizeToBytes(x) (8 << (x)) - -//***************************************************************************** -// -// The following are values that can be passed to md_usb_hosdev_endpoint_data_send() -// as the ui32TransType parameter. -// -//***************************************************************************** -#define USB_TRANS_OUT 0x00000102 // Normal OUT transaction -#define USB_TRANS_IN 0x00000102 // Normal IN transaction -#define USB_TRANS_IN_LAST 0x0000010a // Final IN transaction (for -// endpoint 0 in device mode) -#define USB_TRANS_SETUP 0x0000110a // Setup transaction (for endpoint -// 0) -#define USB_TRANS_STATUS 0x00000142 // Status transaction (for endpoint -// 0) - -//***************************************************************************** -// -// The following are values are returned by the md_usb_hosdev_mode_get() function. -// -//***************************************************************************** -#define USB_DUAL_MODE_HOST 0x00000001 // Dual mode controller is in Host -// mode. -#define USB_DUAL_MODE_DEVICE 0x00000081 // Dual mode controller is in -// Device mode. -#define USB_DUAL_MODE_NONE 0x00000080 // Dual mode controller mode is not -// set. -#define USB_OTG_MODE_ASIDE_HOST 0x0000001d // OTG controller on the A side of -// the cable. -#define USB_OTG_MODE_ASIDE_NPWR 0x00000001 // OTG controller on the A side of -// the cable. -#define USB_OTG_MODE_ASIDE_SESS 0x00000009 // OTG controller on the A side of -// the cable Session Valid. -#define USB_OTG_MODE_ASIDE_AVAL 0x00000011 // OTG controller on the A side of -// the cable A valid. -#define USB_OTG_MODE_ASIDE_DEV 0x00000019 // OTG controller on the A side of -// the cable. -#define USB_OTG_MODE_BSIDE_HOST 0x0000009d // OTG controller on the B side of -// the cable. -#define USB_OTG_MODE_BSIDE_DEV 0x00000099 // OTG controller on the B side of -// the cable. -#define USB_OTG_MODE_BSIDE_NPWR 0x00000081 // OTG controller on the B side of -// the cable. -#define USB_OTG_MODE_NONE 0x00000080 // OTG controller mode is not set. - -//***************************************************************************** -// -// Channel configuration values. -// -//***************************************************************************** -#define DMA_DST_INC_8 0x00000000 -#define DMA_DST_INC_16 0x40000000 -#define DMA_DST_INC_32 0x80000000 -#define DMA_DST_INC_NONE 0xc0000000 -#define DMA_SRC_INC_8 0x00000000 -#define DMA_SRC_INC_16 0x04000000 -#define DMA_SRC_INC_32 0x08000000 -#define DMA_SRC_INC_NONE 0x0c000000 -#define DMA_SIZE_8 0x00000000 -#define DMA_SIZE_16 0x11000000 -#define DMA_SIZE_32 0x22000000 -#define DMA_DST_PROT_PRIV 0x00200000 -#define DMA_SRC_PROT_PRIV 0x00040000 -#define DMA_ARB_1 0x00000000 -#define DMA_ARB_2 0x00004000 -#define DMA_ARB_4 0x00008000 -#define DMA_ARB_8 0x0000c000 -#define DMA_ARB_16 0x00010000 -#define DMA_ARB_32 0x00014000 -#define DMA_ARB_64 0x00018000 -#define DMA_ARB_128 0x0001c000 -#define DMA_ARB_256 0x00020000 -#define DMA_ARB_512 0x00024000 -#define DMA_ARB_1024 0x00028000 -#define DMA_NEXT_USEBURST 0x00000008 - -//***************************************************************************** -// -// The values for the md_usb_dma_channel_int_enable() and md_usb_dma_channel_int_status() -// APIs. -// -//***************************************************************************** -#define USB_DMA_INT_CH8 0x00000080 -#define USB_DMA_INT_CH7 0x00000040 -#define USB_DMA_INT_CH6 0x00000020 -#define USB_DMA_INT_CH5 0x00000010 -#define USB_DMA_INT_CH4 0x00000008 -#define USB_DMA_INT_CH3 0x00000004 -#define USB_DMA_INT_CH2 0x00000002 -#define USB_DMA_INT_CH1 0x00000001 - -//***************************************************************************** -// -// The values for the md_usb_dma_channel_status() API. -// -//***************************************************************************** -#define USB_DMA_STATUS_ERROR 0x00000100 - -//***************************************************************************** -// -// The valid return values for the USBDMAModeSet() and USBDMAModeGet() APIs or -// USBDMAChannelConfig(). -// -//***************************************************************************** -#define USB_DMA_CFG_BURST_NONE 0x00000000 -#define USB_DMA_CFG_BURST_4 0x00000200 -#define USB_DMA_CFG_BURST_8 0x00000400 -#define USB_DMA_CFG_BURST_16 0x00000600 -#define USB_DMA_CFG_INT_EN 0x00000008 -#define USB_DMA_CFG_MODE_0 0x00000000 -#define USB_DMA_CFG_MODE_1 0x00000004 -#define USB_DMA_CFG_DIR_RX 0x00000000 -#define USB_DMA_CFG_DIR_TX 0x00000002 -#define USB_DMA_CFG_EN 0x00000001 - -//***************************************************************************** -// -// The following are values that can be passed to md_usb_mode_config() as the -// ui3Mode parameter. -// -//***************************************************************************** -#define USB_MODE_HOST_VBUS 0x00000004 -#define USB_MODE_HOST 0x00000002 -#define USB_MODE_DEV_VBUS 0x00000005 -#define USB_MODE_DEV 0x00000003 -#define USB_MODE_OTG 0x00000000 - -//***************************************************************************** -// -// Flags that can be passed to DMAChannelAttributeEnable(), -// DMAChannelAttributeDisable(), and returned from DMAChannelAttributeGet(). -// -//***************************************************************************** -#define DMA_ATTR_USEBURST 0x00000001 -#define DMA_ATTR_ALTSELECT 0x00000002 -#define DMA_ATTR_HIGH_PRIORITY 0x00000004 -#define DMA_ATTR_REQMASK 0x00000008 -#define DMA_ATTR_ALL 0x0000000F - -/* Public functions -----------------------------------------------------------*/ -/** - * @{ SYSTEM API. - */ -extern void md_usb_system_int_disable(void); -extern void md_usb_system_int_enable(void); -extern void md_usb_re_config(bool Device); /* Weak defination */ -extern void md_usb_system_delayms(uint32_t delayms); /* Weak defination */ -extern void md_usb_systic_disable(void); -extern void md_usb_controller_reset(void); -extern void md_usb_controller_enable(void); -extern void md_usb_controller_disable(void); -extern void md_usb_clk_phy_enable(void); -extern void md_usb_clk_phy_disable(void); -extern uint32_t md_usb_nvic_number_get(void); -extern void md_usb_nvic_config(uint32_t NvicNum); /* Weak defination */ -extern void md_usb_nvic_enable(void); -extern void md_usb_nvic_disable(void); -/** - * @} SYSTEM API. - */ - -/** - * @{ USB basic API. - */ -/* Host Mode */ -extern void md_usb_hos_reset(bool bStart); -extern void md_usb_hos_resume(bool bStart); -extern void md_usb_hos_suspend(void); -extern void md_usb_hos_request_status(void); -extern void md_usb_hos_request_in(uint32_t ui32Endpoint); -extern void md_usb_hos_request_in_clear(uint32_t ui32Endpoint); -extern uint32_t md_usb_hos_speed_get(void); -extern uint32_t md_usb_hos_addr_get(uint32_t ui32Endpoint, uint32_t ui32Flags); -extern void md_usb_hos_addr_set(uint32_t ui32Endpoint, - uint32_t ui32Addr, - uint32_t ui32Flags); -extern uint32_t md_usb_hos_hub_addr_get(uint32_t ui32Endpoint, - uint32_t ui32Flags); -extern void md_usb_hos_hub_addr_set(uint32_t ui32Endpoint, - uint32_t ui32Addr, - uint32_t ui32Flags); -/* Device Mode */ -extern void md_usb_dev_addr_set(uint8_t ui32Address); -extern uint8_t md_usb_dev_addr_get(void); -extern void md_usb_dev_connect(void); -extern void md_usb_dev_disconnect(void); -extern uint32_t md_usb_dev_speed_get(void); -/* Host/Device Mode */ -extern uint32_t md_usb_hosdev_frame_get(void); -extern void md_usb_hosdev_int_disable(uint32_t ui32IntFlags); -extern void md_usb_hosdev_int_enable(uint32_t ui32IntFlags); -extern uint32_t md_usb_hosdev_int_status(void); -extern uint32_t md_usb_hosdev_mode_get(void); -/* otg Mode */ -extern void md_usb_otg_session_request(bool bStart); -extern void md_usb_force_host_mode(void); -extern void md_usb_force_device_mode(void); -extern void md_usb_force_otg_mode(void); -extern void md_usb_mode_config(uint32_t ui32Mode); -/** - * @} USB basic API. - */ - -/** - * @{ USB endpoint API. - */ -/* Host Mode */ -extern void md_usb_hos_endpoint_config_set(uint32_t ui32Endpoint, - uint32_t ui32MaxPacketSize, - uint32_t ui32NAKPollInterval, - uint32_t ui32TargetEndpoint, - uint32_t ui32Flags); -extern void md_usb_hos_endpoint_data_ack(uint32_t ui32Endpoint); -extern void md_usb_hos_endpoint_data_toggle(uint32_t ui32Endpoint, - bool bDataToggle, - uint32_t ui32Flags); -extern void md_usb_hos_endpoint_status_clear(uint32_t ui32Endpoint, - uint32_t ui32Flags); -extern void md_usb_hos_endpoint_speed(uint32_t ui32Endpoint, - uint32_t ui32Flags); -extern void md_usb_hos_endpoint_ping(uint32_t ui32Endpoint, - bool bEnable); -/* Device Mode */ -extern void md_usb_dev_endpoint_config_set(uint32_t ui32Endpoint, - uint32_t ui32MaxPacketSize, - uint32_t ui32Flags); -extern void md_usb_dev_endpoint_config_get(uint32_t ui32Endpoint, - uint32_t *pui32MaxPacketSize, - uint32_t *pui32Flags); -extern void md_usb_dev_endpoint_ack(uint32_t ui32Endpoint, - bool bIsLastPacket); -extern void md_usb_dev_endpoint_stall(uint32_t ui32Endpoint, - uint32_t ui32Flags); -extern void md_usb_dev_endpoint_stall_clear(uint32_t ui32Endpoint, - uint32_t ui32Flags); -extern void md_usb_dev_endpoint_status_clear(uint32_t ui32Endpoint, - uint32_t ui32Flags); -/* Host/Device Mode */ -extern uint32_t md_usb_hosdev_endpoint_datavai(uint32_t ui32Endpoint); -extern int32_t md_usb_hosdev_endpoint_data_get(uint32_t ui32Endpoint, - uint8_t *pui8Data, uint32_t *pui32Size); -extern int32_t md_usb_hosdev_endpoint_data_put(uint32_t ui32Endpoint, - uint8_t *pui8Data, - uint32_t ui32Size); -extern int32_t md_usb_hosdev_endpoint_data_send(uint32_t ui32Endpoint, - uint32_t ui32TransType); -extern void md_usb_hosdev_endpoint_data_togglec(uint32_t ui32Endpoint, - uint32_t ui32Flags); -extern void md_usb_hosdev_endpoint_pkcount_set(uint32_t ui32Endpoint, - uint32_t ui32Count); -extern uint32_t md_usb_hosdev_endpoint_status(uint32_t ui32Endpoint); -extern void md_usb_hosdev_endpoint_int_disable(uint32_t ui32IntFlags); -extern void md_usb_hosdev_endpoint_int_enable(uint32_t ui32IntFlags); -extern uint32_t md_usb_hosdev_endpoint_int_status(void); -extern uint32_t md_usb_endpoint_number_get(void); -/** - * @} USB endpoint API. - */ - -/** - * @{ USB FIFO API. - */ -extern uint32_t md_usb_hosdev_fifo_addr_get(uint32_t ui32Endpoint); -extern void md_usb_hosdev_fifo_config_get(uint32_t ui32Endpoint, uint32_t *pui32FIFOAddress, - uint32_t *pui32FIFOSize, uint32_t ui32Flags); -extern void md_usb_hosdev_fifo_config_set(uint32_t ui32Endpoint, uint32_t ui32FIFOAddress, - uint32_t ui32FIFOSize, uint32_t ui32Flags); -extern void md_usb_hosdev_fifo_flush(uint32_t ui32Endpoint, uint32_t ui32Flags); -/** - * @} USB FIFO API. - */ - -/** - * @{ USB PWR API.it is not supported by es32f0271. - */ -extern void md_usb_hos_pwr_disable(void); -extern void md_usb_hos_pwr_enable(void); -extern void md_usb_hos_pwr_config(uint32_t ui32Flags); -extern void md_usb_hos_pwrfault_disable(void); -extern void md_usb_hos_pwrfault_enable(void); -/** - * @} USB PWR API. - */ - -/** - * @{ USB LPM API.it is not supported by es32f0271. - */ -extern void md_usb_hos_lpm_send(uint32_t ui32Address, - uint32_t uiEndpoint); -extern void md_usb_hos_lpm_config(uint32_t ui32ResumeTime, - uint32_t ui32Config); -extern bool md_usb_lpm_remotewake_is_enabled(void); -extern void md_usb_hos_lpm_resume(void); -extern void md_usb_dev_lpm_remotewake(void); -extern void md_usb_dev_lpm_config(uint32_t ui32Config); -extern void md_usb_dev_lpm_enable(void); -extern void md_usb_dev_lpm_disable(void); -extern uint32_t md_usb_lpm_link_state_get(void); -extern uint32_t md_usb_lpm_endpoint_get(void); -extern uint32_t md_usb_lpm_status(void); -extern void md_usb_lpm_int_disable(uint32_t ui32Ints); -extern void md_usb_lpm_int_enable(uint32_t ui32Ints); -/** - * @} USB LPM API. - */ - -/** - * @{ USB ULPI API.it is not supported by es32f0271. - */ -extern void md_usb_ulpi_config(uint32_t ui32Config); -extern void md_usb_ulpi_enable(void); -extern void md_usb_ulpi_disable(void); -extern uint8_t md_usb_ulpi_reg_read(uint8_t ui8Reg); -extern void md_usb_ulpi_reg_write(uint8_t ui8Reg, - uint8_t ui8Data); -/** - * @} USB ULPI API. - */ - -/** - * @{ USB DMA API.it is not supported by es32f0271. - */ -extern void md_usb_dma_endpoint_channel_set(uint32_t ui32Endpoint, - uint32_t ui32Channel); -extern void md_usb_dma_endpoint_enable(uint32_t ui32Endpoint, - uint32_t ui32Flags); -extern void md_usb_dma_endpoint_disable(uint32_t ui32Endpoint, - uint32_t ui32Flags); -extern void md_usb_dma_endpoint_config(uint32_t ui32Endpoint, - uint32_t ui32Config); -extern void md_usb_dma_channel_config(uint32_t ui32Channel, - uint32_t ui32Endpoint, - uint32_t ui32Config); -extern void md_usb_dma_channel_address_set(uint32_t ui32Channel, - void *pvAddress); -extern void *md_usb_dma_channel_address_get(uint32_t ui32Channel); -extern void md_usb_dma_channel_count_set(uint32_t ui32Count, - uint32_t ui32Channel); -extern uint32_t md_usb_dma_channel_count_get(uint32_t ui32Channel); -extern void md_usb_dma_channel_int_enable(uint32_t ui32Channel); -extern void md_usb_dma_channel_int_disable(uint32_t ui32Channel); -extern uint32_t md_usb_dma_channel_int_status(void); -extern void md_usb_dma_channel_enable(uint32_t ui32Channel); -extern void md_usb_dma_channel_disable(uint32_t ui32Channel); -extern uint32_t md_usb_dma_channel_isenabled(uint32_t ui32Channel); -extern uint32_t md_usb_dma_channel_status(uint32_t ui32Channel); -extern void md_usb_dma_channel_status_clear(uint32_t ui32Channel, - uint32_t ui32Status); -/** - * @} USB DMA API. - */ - -#ifdef __cplusplus -} -#endif - -#endif - -/******************* (C) COPYRIGHT Eastsoft Microelectronics Co., Ltd. *** END OF FILE ****/ -- cgit v1.3.1 From aa55441a03db8199f9bcbcb38e5b922fc257a067 Mon Sep 17 00:00:00 2001 From: liuhy Date: Fri, 10 Sep 2021 18:03:02 +0800 Subject: delete essemi bsp es32f0271 (all) --- bsp/essemi/es32f0271/.config | 439 ------------ bsp/essemi/es32f0271/Kconfig | 27 - bsp/essemi/es32f0271/README.md | 95 --- bsp/essemi/es32f0271/SConscript | 14 - bsp/essemi/es32f0271/SConstruct | 39 - bsp/essemi/es32f0271/applications/SConscript | 11 - bsp/essemi/es32f0271/applications/main.c | 28 - bsp/essemi/es32f0271/drivers/Kconfig | 102 --- bsp/essemi/es32f0271/drivers/SConscript | 45 -- bsp/essemi/es32f0271/drivers/board.c | 136 ---- bsp/essemi/es32f0271/drivers/board.h | 35 - bsp/essemi/es32f0271/drivers/drv_adc.c | 148 ---- bsp/essemi/es32f0271/drivers/drv_adc.h | 16 - bsp/essemi/es32f0271/drivers/drv_gpio.c | 533 -------------- bsp/essemi/es32f0271/drivers/drv_gpio.h | 16 - bsp/essemi/es32f0271/drivers/drv_hwtimer.c | 174 ----- bsp/essemi/es32f0271/drivers/drv_hwtimer.h | 16 - bsp/essemi/es32f0271/drivers/drv_i2c.c | 275 ------- bsp/essemi/es32f0271/drivers/drv_i2c.h | 16 - bsp/essemi/es32f0271/drivers/drv_pwm.c | 208 ------ bsp/essemi/es32f0271/drivers/drv_pwm.h | 16 - bsp/essemi/es32f0271/drivers/drv_rtc.c | 253 ------- bsp/essemi/es32f0271/drivers/drv_rtc.h | 16 - bsp/essemi/es32f0271/drivers/drv_spi.c | 439 ------------ bsp/essemi/es32f0271/drivers/drv_spi.h | 22 - bsp/essemi/es32f0271/drivers/drv_uart.c | 296 -------- bsp/essemi/es32f0271/drivers/drv_uart.h | 16 - .../es32f0271/drivers/linker_scripts/link.sct | 14 - bsp/essemi/es32f0271/project.uvoptx | 797 --------------------- bsp/essemi/es32f0271/project.uvprojx | 662 ----------------- bsp/essemi/es32f0271/rtconfig.h | 183 ----- bsp/essemi/es32f0271/rtconfig.py | 135 ---- bsp/essemi/es32f0271/template.uvoptx | 177 ----- bsp/essemi/es32f0271/template.uvprojx | 389 ---------- 34 files changed, 5788 deletions(-) delete mode 100644 bsp/essemi/es32f0271/.config delete mode 100644 bsp/essemi/es32f0271/Kconfig delete mode 100644 bsp/essemi/es32f0271/README.md delete mode 100644 bsp/essemi/es32f0271/SConscript delete mode 100644 bsp/essemi/es32f0271/SConstruct delete mode 100644 bsp/essemi/es32f0271/applications/SConscript delete mode 100644 bsp/essemi/es32f0271/applications/main.c delete mode 100644 bsp/essemi/es32f0271/drivers/Kconfig delete mode 100644 bsp/essemi/es32f0271/drivers/SConscript delete mode 100644 bsp/essemi/es32f0271/drivers/board.c delete mode 100644 bsp/essemi/es32f0271/drivers/board.h delete mode 100644 bsp/essemi/es32f0271/drivers/drv_adc.c delete mode 100644 bsp/essemi/es32f0271/drivers/drv_adc.h delete mode 100644 bsp/essemi/es32f0271/drivers/drv_gpio.c delete mode 100644 bsp/essemi/es32f0271/drivers/drv_gpio.h delete mode 100644 bsp/essemi/es32f0271/drivers/drv_hwtimer.c delete mode 100644 bsp/essemi/es32f0271/drivers/drv_hwtimer.h delete mode 100644 bsp/essemi/es32f0271/drivers/drv_i2c.c delete mode 100644 bsp/essemi/es32f0271/drivers/drv_i2c.h delete mode 100644 bsp/essemi/es32f0271/drivers/drv_pwm.c delete mode 100644 bsp/essemi/es32f0271/drivers/drv_pwm.h delete mode 100644 bsp/essemi/es32f0271/drivers/drv_rtc.c delete mode 100644 bsp/essemi/es32f0271/drivers/drv_rtc.h delete mode 100644 bsp/essemi/es32f0271/drivers/drv_spi.c delete mode 100644 bsp/essemi/es32f0271/drivers/drv_spi.h delete mode 100644 bsp/essemi/es32f0271/drivers/drv_uart.c delete mode 100644 bsp/essemi/es32f0271/drivers/drv_uart.h delete mode 100644 bsp/essemi/es32f0271/drivers/linker_scripts/link.sct delete mode 100644 bsp/essemi/es32f0271/project.uvoptx delete mode 100644 bsp/essemi/es32f0271/project.uvprojx delete mode 100644 bsp/essemi/es32f0271/rtconfig.h delete mode 100644 bsp/essemi/es32f0271/rtconfig.py delete mode 100644 bsp/essemi/es32f0271/template.uvoptx delete mode 100644 bsp/essemi/es32f0271/template.uvprojx (limited to 'bsp') diff --git a/bsp/essemi/es32f0271/.config b/bsp/essemi/es32f0271/.config deleted file mode 100644 index 15ed9fadcd..0000000000 --- a/bsp/essemi/es32f0271/.config +++ /dev/null @@ -1,439 +0,0 @@ -# -# Automatically generated file; DO NOT EDIT. -# RT-Thread Configuration -# - -# -# RT-Thread Kernel -# -CONFIG_RT_NAME_MAX=8 -# CONFIG_RT_USING_ARCH_DATA_TYPE is not set -# CONFIG_RT_USING_SMP is not set -CONFIG_RT_ALIGN_SIZE=4 -# CONFIG_RT_THREAD_PRIORITY_8 is not set -CONFIG_RT_THREAD_PRIORITY_32=y -# CONFIG_RT_THREAD_PRIORITY_256 is not set -CONFIG_RT_THREAD_PRIORITY_MAX=32 -CONFIG_RT_TICK_PER_SECOND=100 -CONFIG_RT_USING_OVERFLOW_CHECK=y -CONFIG_RT_USING_HOOK=y -CONFIG_RT_USING_IDLE_HOOK=y -CONFIG_RT_IDLE_HOOK_LIST_SIZE=4 -CONFIG_IDLE_THREAD_STACK_SIZE=256 -# CONFIG_RT_USING_TIMER_SOFT is not set -CONFIG_RT_DEBUG=y -CONFIG_RT_DEBUG_COLOR=y -# CONFIG_RT_DEBUG_INIT_CONFIG is not set -# CONFIG_RT_DEBUG_THREAD_CONFIG is not set -# CONFIG_RT_DEBUG_SCHEDULER_CONFIG is not set -# CONFIG_RT_DEBUG_IPC_CONFIG is not set -# CONFIG_RT_DEBUG_TIMER_CONFIG is not set -# CONFIG_RT_DEBUG_IRQ_CONFIG is not set -# CONFIG_RT_DEBUG_MEM_CONFIG is not set -# CONFIG_RT_DEBUG_SLAB_CONFIG is not set -# CONFIG_RT_DEBUG_MEMHEAP_CONFIG is not set -# CONFIG_RT_DEBUG_MODULE_CONFIG is not set - -# -# Inter-Thread communication -# -CONFIG_RT_USING_SEMAPHORE=y -CONFIG_RT_USING_MUTEX=y -CONFIG_RT_USING_EVENT=y -CONFIG_RT_USING_MAILBOX=y -CONFIG_RT_USING_MESSAGEQUEUE=y -# CONFIG_RT_USING_SIGNALS is not set - -# -# Memory Management -# -CONFIG_RT_USING_MEMPOOL=y -# CONFIG_RT_USING_MEMHEAP is not set -# CONFIG_RT_USING_NOHEAP is not set -CONFIG_RT_USING_SMALL_MEM=y -# CONFIG_RT_USING_SLAB is not set -# CONFIG_RT_USING_MEMTRACE is not set -CONFIG_RT_USING_HEAP=y - -# -# Kernel Device Object -# -CONFIG_RT_USING_DEVICE=y -# CONFIG_RT_USING_DEVICE_OPS is not set -# CONFIG_RT_USING_INTERRUPT_INFO is not set -CONFIG_RT_USING_CONSOLE=y -CONFIG_RT_CONSOLEBUF_SIZE=128 -CONFIG_RT_CONSOLE_DEVICE_NAME="uart1" -CONFIG_RT_VER_NUM=0x40002 -# CONFIG_RT_USING_CPU_FFS is not set -# CONFIG_ARCH_CPU_STACK_GROWS_UPWARD is not set - -# -# RT-Thread Components -# -CONFIG_RT_USING_COMPONENTS_INIT=y -CONFIG_RT_USING_USER_MAIN=y -CONFIG_RT_MAIN_THREAD_STACK_SIZE=1024 -CONFIG_RT_MAIN_THREAD_PRIORITY=10 - -# -# C++ features -# -# CONFIG_RT_USING_CPLUSPLUS is not set - -# -# Command shell -# -CONFIG_RT_USING_FINSH=y -CONFIG_FINSH_THREAD_NAME="tshell" -CONFIG_FINSH_USING_HISTORY=y -CONFIG_FINSH_HISTORY_LINES=5 -CONFIG_FINSH_USING_SYMTAB=y -CONFIG_FINSH_USING_DESCRIPTION=y -# CONFIG_FINSH_ECHO_DISABLE_DEFAULT is not set -CONFIG_FINSH_THREAD_PRIORITY=20 -CONFIG_FINSH_THREAD_STACK_SIZE=2048 -CONFIG_FINSH_CMD_SIZE=80 -# CONFIG_FINSH_USING_AUTH is not set -CONFIG_FINSH_USING_MSH=y -CONFIG_FINSH_USING_MSH_DEFAULT=y -CONFIG_FINSH_USING_MSH_ONLY=y -CONFIG_FINSH_ARG_MAX=10 - -# -# Device virtual file system -# -# CONFIG_RT_USING_DFS is not set - -# -# Device Drivers -# -CONFIG_RT_USING_DEVICE_IPC=y -CONFIG_RT_PIPE_BUFSZ=512 -# CONFIG_RT_USING_SYSTEM_WORKQUEUE is not set -CONFIG_RT_USING_SERIAL=y -# CONFIG_RT_SERIAL_USING_DMA is not set -CONFIG_RT_SERIAL_RB_BUFSZ=64 -# CONFIG_RT_USING_CAN is not set -# CONFIG_RT_USING_HWTIMER is not set -# CONFIG_RT_USING_CPUTIME is not set -# CONFIG_RT_USING_I2C is not set -CONFIG_RT_USING_PIN=y -# CONFIG_RT_USING_ADC is not set -# CONFIG_RT_USING_PWM is not set -# CONFIG_RT_USING_MTD_NOR is not set -# CONFIG_RT_USING_MTD_NAND is not set -# CONFIG_RT_USING_PM is not set -# CONFIG_RT_USING_RTC is not set -# CONFIG_RT_USING_SDIO is not set -# CONFIG_RT_USING_SPI is not set -# CONFIG_RT_USING_WDT is not set -# CONFIG_RT_USING_AUDIO is not set -# CONFIG_RT_USING_SENSOR is not set -# CONFIG_RT_USING_TOUCH is not set -# CONFIG_RT_USING_HWCRYPTO is not set -# CONFIG_RT_USING_PULSE_ENCODER is not set -# CONFIG_RT_USING_INPUT_CAPTURE is not set -# CONFIG_RT_USING_WIFI is not set - -# -# Using USB -# -# CONFIG_RT_USING_USB_HOST is not set -# CONFIG_RT_USING_USB_DEVICE is not set - -# -# POSIX layer and C standard library -# -# CONFIG_RT_USING_LIBC is not set -# CONFIG_RT_USING_PTHREADS is not set -# CONFIG_RT_LIBC_USING_TIME is not set - -# -# Network -# - -# -# Socket abstraction layer -# -# CONFIG_RT_USING_SAL is not set - -# -# Network interface device -# -# CONFIG_RT_USING_NETDEV is not set - -# -# light weight TCP/IP stack -# -# CONFIG_RT_USING_LWIP is not set - -# -# AT commands -# -# CONFIG_RT_USING_AT is not set - -# -# VBUS(Virtual Software BUS) -# -# CONFIG_RT_USING_VBUS is not set - -# -# Utilities -# -# CONFIG_RT_USING_RYM is not set -# CONFIG_RT_USING_ULOG is not set -# CONFIG_RT_USING_UTEST is not set - -# -# RT-Thread online packages -# - -# -# IoT - internet of things -# -# CONFIG_PKG_USING_PAHOMQTT is not set -# CONFIG_PKG_USING_WEBCLIENT is not set -# CONFIG_PKG_USING_WEBNET is not set -# CONFIG_PKG_USING_MONGOOSE is not set -# CONFIG_PKG_USING_MYMQTT is not set -# CONFIG_PKG_USING_WEBTERMINAL is not set -# CONFIG_PKG_USING_CJSON is not set -# CONFIG_PKG_USING_JSMN is not set -# CONFIG_PKG_USING_LIBMODBUS is not set -# CONFIG_PKG_USING_FREEMODBUS is not set -# CONFIG_PKG_USING_LJSON is not set -# CONFIG_PKG_USING_EZXML is not set -# CONFIG_PKG_USING_NANOPB is not set - -# -# Wi-Fi -# - -# -# Marvell WiFi -# -# CONFIG_PKG_USING_WLANMARVELL is not set - -# -# Wiced WiFi -# -# CONFIG_PKG_USING_WLAN_WICED is not set -# CONFIG_PKG_USING_RW007 is not set -# CONFIG_PKG_USING_COAP is not set -# CONFIG_PKG_USING_NOPOLL is not set -# CONFIG_PKG_USING_NETUTILS is not set -# CONFIG_PKG_USING_PPP_DEVICE is not set -# CONFIG_PKG_USING_AT_DEVICE is not set -# CONFIG_PKG_USING_ATSRV_SOCKET is not set -# CONFIG_PKG_USING_WIZNET is not set - -# -# IoT Cloud -# -# CONFIG_PKG_USING_ONENET is not set -# CONFIG_PKG_USING_GAGENT_CLOUD is not set -# CONFIG_PKG_USING_ALI_IOTKIT is not set -# CONFIG_PKG_USING_AZURE is not set -# CONFIG_PKG_USING_TENCENT_IOTHUB is not set -# CONFIG_PKG_USING_JIOT-C-SDK is not set -# CONFIG_PKG_USING_NIMBLE is not set -# CONFIG_PKG_USING_OTA_DOWNLOADER is not set -# CONFIG_PKG_USING_IPMSG is not set -# CONFIG_PKG_USING_LSSDP is not set -# CONFIG_PKG_USING_AIRKISS_OPEN is not set -# CONFIG_PKG_USING_LIBRWS is not set -# CONFIG_PKG_USING_TCPSERVER is not set -# CONFIG_PKG_USING_PROTOBUF_C is not set -# CONFIG_PKG_USING_ONNX_PARSER is not set -# CONFIG_PKG_USING_ONNX_BACKEND is not set -# CONFIG_PKG_USING_DLT645 is not set -# CONFIG_PKG_USING_QXWZ is not set -# CONFIG_PKG_USING_SMTP_CLIENT is not set -# CONFIG_PKG_USING_ABUP_FOTA is not set - -# -# security packages -# -# CONFIG_PKG_USING_MBEDTLS is not set -# CONFIG_PKG_USING_libsodium is not set -# CONFIG_PKG_USING_TINYCRYPT is not set - -# -# language packages -# -# CONFIG_PKG_USING_LUA is not set -# CONFIG_PKG_USING_JERRYSCRIPT is not set -# CONFIG_PKG_USING_MICROPYTHON is not set - -# -# multimedia packages -# -# CONFIG_PKG_USING_OPENMV is not set -# CONFIG_PKG_USING_MUPDF is not set -# CONFIG_PKG_USING_STEMWIN is not set -# CONFIG_PKG_USING_WAVPLAYER is not set -# CONFIG_PKG_USING_TJPGD is not set - -# -# tools packages -# -# CONFIG_PKG_USING_CMBACKTRACE is not set -# CONFIG_PKG_USING_EASYFLASH is not set -# CONFIG_PKG_USING_EASYLOGGER is not set -# CONFIG_PKG_USING_SYSTEMVIEW is not set -# CONFIG_PKG_USING_RDB is not set -# CONFIG_PKG_USING_QRCODE is not set -# CONFIG_PKG_USING_ULOG_EASYFLASH is not set -# CONFIG_PKG_USING_ADBD is not set -# CONFIG_PKG_USING_COREMARK is not set -# CONFIG_PKG_USING_DHRYSTONE is not set -# CONFIG_PKG_USING_NR_MICRO_SHELL is not set - -# -# system packages -# -# CONFIG_PKG_USING_GUIENGINE is not set -# CONFIG_PKG_USING_CAIRO is not set -# CONFIG_PKG_USING_PIXMAN is not set -# CONFIG_PKG_USING_LWEXT4 is not set -# CONFIG_PKG_USING_PARTITION is not set -# CONFIG_PKG_USING_FAL is not set -# CONFIG_PKG_USING_SQLITE is not set -# CONFIG_PKG_USING_RTI is not set -# CONFIG_PKG_USING_LITTLEVGL2RTT is not set -# CONFIG_PKG_USING_CMSIS is not set -# CONFIG_PKG_USING_DFS_YAFFS is not set -# CONFIG_PKG_USING_LITTLEFS is not set -# CONFIG_PKG_USING_THREAD_POOL is not set -# CONFIG_PKG_USING_ROBOTS is not set - -# -# peripheral libraries and drivers -# -# CONFIG_PKG_USING_SENSORS_DRIVERS is not set -# CONFIG_PKG_USING_REALTEK_AMEBA is not set -# CONFIG_PKG_USING_SHT2X is not set -# CONFIG_PKG_USING_SHT3X is not set -# CONFIG_PKG_USING_STM32_SDIO is not set -# CONFIG_PKG_USING_ICM20608 is not set -# CONFIG_PKG_USING_U8G2 is not set -# CONFIG_PKG_USING_BUTTON is not set -# CONFIG_PKG_USING_PCF8574 is not set -# CONFIG_PKG_USING_SX12XX is not set -# CONFIG_PKG_USING_SIGNAL_LED is not set -# CONFIG_PKG_USING_LEDBLINK is not set -# CONFIG_PKG_USING_WM_LIBRARIES is not set -# CONFIG_PKG_USING_KENDRYTE_SDK is not set -# CONFIG_PKG_USING_INFRARED is not set -# CONFIG_PKG_USING_ROSSERIAL is not set -# CONFIG_PKG_USING_AGILE_BUTTON is not set -# CONFIG_PKG_USING_AGILE_LED is not set -# CONFIG_PKG_USING_AT24CXX is not set -# CONFIG_PKG_USING_MOTIONDRIVER2RTT is not set -# CONFIG_PKG_USING_AD7746 is not set -# CONFIG_PKG_USING_PCA9685 is not set -# CONFIG_PKG_USING_I2C_TOOLS is not set -# CONFIG_PKG_USING_NRF24L01 is not set -# CONFIG_PKG_USING_TOUCH_DRIVERS is not set -# CONFIG_PKG_USING_LCD_DRIVERS is not set -# CONFIG_PKG_USING_MAX17048 is not set -# CONFIG_PKG_USING_RPLIDAR is not set - -# -# miscellaneous packages -# -# CONFIG_PKG_USING_LIBCSV is not set -# CONFIG_PKG_USING_OPTPARSE is not set -# CONFIG_PKG_USING_FASTLZ is not set -# CONFIG_PKG_USING_MINILZO is not set -# CONFIG_PKG_USING_QUICKLZ is not set -# CONFIG_PKG_USING_MULTIBUTTON is not set -# CONFIG_PKG_USING_FLEXIBLE_BUTTON is not set -# CONFIG_PKG_USING_CANFESTIVAL is not set -# CONFIG_PKG_USING_ZLIB is not set -# CONFIG_PKG_USING_DSTR is not set -# CONFIG_PKG_USING_TINYFRAME is not set -# CONFIG_PKG_USING_KENDRYTE_DEMO is not set -# CONFIG_PKG_USING_DIGITALCTRL is not set -# CONFIG_PKG_USING_UPACKER is not set -# CONFIG_PKG_USING_UPARAM is not set - -# -# samples: kernel and components samples -# -# CONFIG_PKG_USING_KERNEL_SAMPLES is not set -# CONFIG_PKG_USING_FILESYSTEM_SAMPLES is not set -# CONFIG_PKG_USING_NETWORK_SAMPLES is not set -# CONFIG_PKG_USING_PERIPHERAL_SAMPLES is not set -# CONFIG_PKG_USING_HELLO is not set -# CONFIG_PKG_USING_VI is not set -# CONFIG_PKG_USING_NNOM is not set -# CONFIG_PKG_USING_LIBANN is not set -# CONFIG_PKG_USING_ELAPACK is not set -# CONFIG_PKG_USING_ARMv7M_DWT is not set -# CONFIG_PKG_USING_VT100 is not set -# CONFIG_PKG_USING_ULAPACK is not set -# CONFIG_PKG_USING_UKAL is not set -CONFIG_SOC_ES32F0271LT=y - -# -# Hardware Drivers Config -# - -# -# On-chip Peripheral Drivers -# - -# -# PIN Drivers -# -CONFIG_BSP_USING_GPIO=y - -# -# UART Drivers -# -CONFIG_BSP_USING_UART1=y -# CONFIG_BSP_USING_UART2 is not set -# CONFIG_BSP_USING_UART3 is not set - -# -# SPI Drivers -# -# CONFIG_BSP_USING_SPI1 is not set -# CONFIG_BSP_USING_SPI2 is not set - -# -# I2C Drivers -# -# CONFIG_BSP_USING_I2C1 is not set -# CONFIG_BSP_USING_I2C2 is not set - -# -# HWtimer Drivers -# -# CONFIG_BSP_USING_HWTIMER1 is not set - -# -# PWM Drivers -# -# CONFIG_BSP_USING_PWM_GP16C2T1 is not set -# CONFIG_BSP_USING_PWM_GP16C2T4 is not set - -# -# RTC Drivers -# -# CONFIG_BSP_USING_RTC is not set - -# -# ADC Drivers -# -# CONFIG_BSP_USING_ADC is not set - -# -# Onboard Peripheral Drivers -# - -# -# Offboard Peripheral Drivers -# diff --git a/bsp/essemi/es32f0271/Kconfig b/bsp/essemi/es32f0271/Kconfig deleted file mode 100644 index 2065783042..0000000000 --- a/bsp/essemi/es32f0271/Kconfig +++ /dev/null @@ -1,27 +0,0 @@ -mainmenu "RT-Thread Configuration" - -config BSP_DIR - string - option env="BSP_ROOT" - default "." - -config RTT_DIR - string - option env="RTT_ROOT" - default "../../.." - -config PKGS_DIR - string - option env="PKGS_ROOT" - default "packages" - -source "$RTT_DIR/Kconfig" -source "$PKGS_DIR/Kconfig" - -config SOC_ES32F0271LT - bool - select RT_USING_COMPONENTS_INIT - select RT_USING_USER_MAIN - default y - -source "drivers/Kconfig" diff --git a/bsp/essemi/es32f0271/README.md b/bsp/essemi/es32f0271/README.md deleted file mode 100644 index c50443466b..0000000000 --- a/bsp/essemi/es32f0271/README.md +++ /dev/null @@ -1,95 +0,0 @@ -# ES-PDS-ES32F0271 开发板 BSP 说明 -标签： EastSoft、国产MCU、Cortex-M0、ES32F0271LT - -## 1. 简介 - -本文档为上海东软载波微电子开发团队为 ES-PDS-ES32F0271 开发板提供的 BSP (板级支持包) 说明。 -通过阅读本文档，开发者可以快速地上手该 BSP，将 RT-Thread 运行在开发板上。 - -### 1.1 开发板介绍 - -主要内容如下： -ES-PDS-ES32F0271 是东软载波微电子官方推出的一款基于 ARM Cortex-M0 内核的开发板，最高主频为 48MHz，可满足基础功能测试及高端功能扩展等开发需求。 - -ES-PDS-ES32F0271-V1.1 - -该开发板常用 **板载资源** 如下： - -- MCU：ES32F0271LT，主频 48MHz，8KB SRAM，64KB FLASH -- 外部模块：SPI FLASH (MX25L64，8MB)、I2C EEPROM (M24C04，512B) -- 常用外设 - - 可调电阻：1个，(PC03) - - LED：2个，(PD03/PB08) - - 五轴按键： -- 常用接口：GPIO、UART、SPI、I2C -- 调试接口，ESLinkⅡ(EastSoft 官方推出的开发工具，有标准版和mini版两种版本，均自带 CDC 串口功能) SWD 下载 - -外设支持: - -本 BSP 目前对外设的支持情况如下： - -| **板载外设** | **支持情况** | **备注** | -| :---------------- | :----------: | :------------------------------------| -| **片上外设** | **支持情况** | **备注** | -| GPIO | 支持 | GPIOs | -| UART | 支持 | UART1/2/3 | -| SPI | 支持 | SPI1/2 | -| I2C | 支持 | I2C1/2 | -| PWM | 支持 | PWM1/2 | -| TIMER | 支持 | TIMER1 | -| RTC | 支持 | RTC | -| ADC | 支持 | ADC | - -### 1.2 注意事项 - -- 本BSP中，SPI2和PWM2不能同时使用 - -更多详细信息请咨询[上海东软载波微电子技术支持](http://www.essemi.com/) - -## 2. 快速上手 - -本 BSP 为开发者提供 MDK5 工程。下面以 MDK5 开发环境为例，介绍如何将系统运行起来。 - -### 硬件连接 - -使用 ESLinkⅡ (自带 CDC 串口)或 Jlink 等调试工具连接开发板到 PC端，拨动开关选择使用调试工具供电或使用外部电源供电。若使用 Jlink 等调试工具，还需要将 UART1_TX(PB06)、UART1_RX(PB07)、GND 接到串口工具上。 - -ESLinkⅡ(mini) + ES-PDS-ES32F0271-V1.1 - -### 编译下载 - -双击 project.uvprojx 文件，打开 MDK5 工程，工程默认配置使用 JLink 下载程序，在通过 JLink 连接开发板的基础上，点击下载按钮即可下载程序到开发板，如果使用 ESLinkⅡ，则选择 "CMSIS-DAP Debugger"，连接正常后即可编译并下载程序到开发板。 - -### 运行结果 - -下载程序成功之后，系统会自动运行，观察串口输出的信息，同时开发板LED闪烁。 - -```bash - \ | / -- RT - Thread Operating System - / | \ 4.0.2 build Oct 31 2019 - 2006 - 2019 Copyright by rt-thread team -msh > -``` -## 3. 进阶使用 - -此 BSP 默认只开启了 GPIO 和 uart1 的功能，如果需使用 Flash 等更多高级功能，需要利用 ENV 工具对 BSP 进行配置，步骤如下： - -1. 在 bsp 下打开 env 工具。 - -2. 输入`menuconfig`命令配置工程，配置好之后保存退出。 - -3. 输入`pkgs --update`命令更新软件包。 - -4. 输入`scons --target=mdk5/iar` 命令重新生成工程。 - -更多 Env 工具的详细介绍请参考 [RT-Thread 文档中心](https://www.rt-thread.org/document/site/) - -## 4. 联系人信息 - -- [yuzr](https://github.com/essemi-yuzr) - -## 5. 参考 - -- [ EastSoft 官网](http://www.essemi.com) - diff --git a/bsp/essemi/es32f0271/SConscript b/bsp/essemi/es32f0271/SConscript deleted file mode 100644 index 468297b6a9..0000000000 --- a/bsp/essemi/es32f0271/SConscript +++ /dev/null @@ -1,14 +0,0 @@ -# for module compiling -import os -Import('RTT_ROOT') - -objs = [] -cwd = str(Dir('#')) -list = os.listdir(cwd) - -for d in list: - path = os.path.join(cwd, d) - if os.path.isfile(os.path.join(path, 'SConscript')): - objs = objs + SConscript(os.path.join(d, 'SConscript')) - -Return('objs') diff --git a/bsp/essemi/es32f0271/SConstruct b/bsp/essemi/es32f0271/SConstruct deleted file mode 100644 index 164265293d..0000000000 --- a/bsp/essemi/es32f0271/SConstruct +++ /dev/null @@ -1,39 +0,0 @@ -import os -import sys -import rtconfig - -if os.getenv('RTT_ROOT'): - RTT_ROOT = os.getenv('RTT_ROOT') -else: - RTT_ROOT = os.path.normpath(os.getcwd() + '/../../..') - -sys.path = sys.path + [os.path.join(RTT_ROOT, 'tools')] -try: - from building import * -except: - print('Cannot found RT-Thread root directory, please check RTT_ROOT') - print(RTT_ROOT) - exit(-1) - -TARGET = 'rtthread.' + rtconfig.TARGET_EXT - -env = Environment(tools = ['mingw'], - AS = rtconfig.AS, ASFLAGS = rtconfig.AFLAGS, - CC = rtconfig.CC, CCFLAGS = rtconfig.CFLAGS, - AR = rtconfig.AR, ARFLAGS = '-rc', - LINK = rtconfig.LINK, LINKFLAGS = rtconfig.LFLAGS) -env.PrependENVPath('PATH', rtconfig.EXEC_PATH) - -if rtconfig.PLATFORM == 'iar': - env.Replace(CCCOM = ['$CC $CCFLAGS $CPPFLAGS $_CPPDEFFLAGS $_CPPINCFLAGS -o $TARGET $SOURCES']) - env.Replace(ARFLAGS = ['']) - env.Replace(LINKCOM = env["LINKCOM"] + ' --map project.map') - -Export('RTT_ROOT') -Export('rtconfig') - -# prepare building environment -objs = PrepareBuilding(env, RTT_ROOT, has_libcpu=False) - -# make a building -DoBuilding(TARGET, objs) diff --git a/bsp/essemi/es32f0271/applications/SConscript b/bsp/essemi/es32f0271/applications/SConscript deleted file mode 100644 index e0c84e8f14..0000000000 --- a/bsp/essemi/es32f0271/applications/SConscript +++ /dev/null @@ -1,11 +0,0 @@ -Import('RTT_ROOT') -Import('rtconfig') -from building import * - -cwd = os.path.join(str(Dir('#')), 'applications') -src = Glob('*.c') - -CPPPATH = [cwd, str(Dir('#'))] -group = DefineGroup('Applications', src, depend = [''], CPPPATH = CPPPATH) - -Return('group') diff --git a/bsp/essemi/es32f0271/applications/main.c b/bsp/essemi/es32f0271/applications/main.c deleted file mode 100644 index 31e31d355d..0000000000 --- a/bsp/essemi/es32f0271/applications/main.c +++ /dev/null @@ -1,28 +0,0 @@ -/* - * Copyright (C) 2018 Shanghai Eastsoft Microelectronics Co., Ltd. - * - * SPDX-License-Identifier: Apache-2.0 - * - * Change Logs: - * Date Author Notes - * 2019-10-23 yuzrain the first version - */ - -#include -#include - -#define LED_PIN 61 - -int main(void) -{ - /* LED pin configuration */ - rt_pin_mode(LED_PIN, PIN_MODE_OUTPUT); - - while (1) - { - rt_pin_write(LED_PIN, PIN_HIGH); - rt_thread_mdelay(1000); - rt_pin_write(LED_PIN, PIN_LOW); - rt_thread_mdelay(1000); - } -} diff --git a/bsp/essemi/es32f0271/drivers/Kconfig b/bsp/essemi/es32f0271/drivers/Kconfig deleted file mode 100644 index 37265a5ba8..0000000000 --- a/bsp/essemi/es32f0271/drivers/Kconfig +++ /dev/null @@ -1,102 +0,0 @@ -menu "Hardware Drivers Config" - - menu "On-chip Peripheral Drivers" - menu "PIN Drivers" - config BSP_USING_GPIO - bool "Enable GPIO" - select RT_USING_PIN - default y - endmenu - - menu "UART Drivers" - config BSP_USING_UART1 - bool "Enable UART1 PB06/PB07(T/R)" - select RT_USING_SERIAL - default y - - config BSP_USING_UART2 - bool "Enable UART2 PA02/PA03(T/R)" - select RT_USING_SERIAL - default n - - config BSP_USING_UART3 - bool "Enable UART3 PC06/PC07(T/R)" - select RT_USING_SERIAL - default n - endmenu - - menu "SPI Drivers" - config BSP_USING_SPI1 - bool "Enable SPI1 BUS PB03/PB04/PB05(CLK/MISO/MOSI)" - select RT_USING_SPI - select RT_USING_PIN - default n - - config BSP_USING_SPI2 - bool "Enable SPI2 BUS PB13/PB14/PB15(CLK/MISO/MOSI)" - select RT_USING_SPI - select RT_USING_PIN - default n - depends on !BSP_USING_PWM_GP16C2T4 - endmenu - - menu "I2C Drivers" - config BSP_USING_I2C1 - bool "Enable I2C1 BUS PC12/PD02(SCL/SDA)" - select RT_USING_I2C - default n - - config BSP_USING_I2C2 - bool "Enable I2C2 BUS PB10/PB11(SCL/SDA)" - select RT_USING_I2C - default n - endmenu - - menu "HWtimer Drivers" - - config BSP_USING_HWTIMER1 - bool "Using timer1" - select RT_USING_HWTIMER - default n - endmenu - - menu "PWM Drivers" - - config BSP_USING_PWM_GP16C2T1 - bool "Using PWM_1(GP16C2T1) PB01/PB02" - select RT_USING_PWM - default n - - config BSP_USING_PWM_GP16C2T4 - bool "Using PWM2(GP16C2T4) PB12/PB14" - select RT_USING_PWM - default n - depends on !BSP_USING_SPI2 - - endmenu - - menu "RTC Drivers" - config BSP_USING_RTC - bool "Using RTC" - select RT_USING_RTC - default n - endmenu - - menu "ADC Drivers" - config BSP_USING_ADC - bool "Using ADC" - select RT_USING_ADC - default n - endmenu - - endmenu - - menu "Onboard Peripheral Drivers" - - endmenu - - menu "Offboard Peripheral Drivers" - - endmenu - -endmenu diff --git a/bsp/essemi/es32f0271/drivers/SConscript b/bsp/essemi/es32f0271/drivers/SConscript deleted file mode 100644 index 3be3df80c5..0000000000 --- a/bsp/essemi/es32f0271/drivers/SConscript +++ /dev/null @@ -1,45 +0,0 @@ -from building import * - -cwd = GetCurrentDir() - -# add the general drivers. -src = Split(''' -board.c -''') - -# add gpio code -if GetDepend('RT_USING_PIN'): - src += ['drv_gpio.c'] - -# add serial driver code -if GetDepend('BSP_USING_UART1') or GetDepend('BSP_USING_UART2') or GetDepend('BSP_USING_UART3'): - src += ['drv_uart.c'] - -# add spi driver code -if GetDepend('BSP_USING_SPI1') or GetDepend('BSP_USING_SPI2'): - src += ['drv_spi.c'] - -# add i2c driver code -if GetDepend('BSP_USING_I2C1') or GetDepend('BSP_USING_I2C2'): - src += ['drv_i2c.c'] - -# add pwm driver code -if GetDepend('BSP_USING_PWM1') or GetDepend('BSP_USING_PWM2') or GetDepend('BSP_USING_PWM3') or GetDepend('BSP_USING_PWM4') or GetDepend('BSP_USING_PWM_GP16C2T1') or GetDepend('BSP_USING_PWM_GP16C2T4'): - src += ['drv_pwm.c'] - -# add hwtimer driver code -if GetDepend('BSP_USING_HWTIMER1'): - src += ['drv_hwtimer.c'] - -# add rtc driver code -if GetDepend(['BSP_USING_RTC']): - src += ['drv_rtc.c'] - -# add adc driver code -if GetDepend(['BSP_USING_ADC']): - src += ['drv_adc.c'] - -CPPPATH = [cwd] -group = DefineGroup('Drivers', src, depend = [''], CPPPATH = CPPPATH) - -Return('group') diff --git a/bsp/essemi/es32f0271/drivers/board.c b/bsp/essemi/es32f0271/drivers/board.c deleted file mode 100644 index 8ebc351ff1..0000000000 --- a/bsp/essemi/es32f0271/drivers/board.c +++ /dev/null @@ -1,136 +0,0 @@ -/* - * Copyright (C) 2018 Shanghai Eastsoft Microelectronics Co., Ltd. - * - * SPDX-License-Identifier: Apache-2.0 - * - * Change Logs: - * Date Author Notes - * 2019-10-23 yuzrain the first version - */ - -#include -#include -#include "board.h" -#include "drv_uart.h" -#include "drv_gpio.h" -#include "md_gpio.h" - -/** - * @addtogroup es32f0 - */ - -/*@{*/ - -/******************************************************************************* -* Function Name : NVIC_Configuration -* Description : Configures Vector Table base location. -* Input : None -* Output : None -* Return : None -*******************************************************************************/ -void NVIC_Configuration(void) -{ -} - -/******************************************************************************* - * Function Name : SystemClock_Configuration - * Description : Configures the System Clock. - * Input : None - * Output : None - * Return : None - *******************************************************************************/ -void SystemClock_Config(void) -{ - /*-------------------------Clock Config-------------------------/ - * Config system clock to 48MHz of which the clock source - * is PLL0. - */ - - // - // Open PLL0/HRC then wait it ready. - // - SET_BIT(RCU->CON, RCU_CON_PLL0ON_MSK); - SET_BIT(RCU->CON, RCU_CON_HRCON_MSK); - - /* Wait HRC clock steady. */ - while (!READ_BIT(RCU->CON, RCU_CON_HRCRDY_MSK)); - - // - // Change system clock source,PLL0,48MHz. - // - /* Chose PLL0 as system clock. */ - MODIFY_REG(RCU->CFG, RCU_CFG_SW_MSK, (0x4 << RCU_CFG_SW_POSS)); - /* Config mul of PLL0. */ - MODIFY_REG(RCU->CFG, RCU_CFG_PLLMUL_MSK, (11 << RCU_CFG_PLLMUL_POSS)); - - // - // Start to change system clock and wait it ready. - // - /* Config flash read wait time. */ - MODIFY_REG(FC->CON, FC_CON_WAIT_MSK, (0X2 << FC_CON_WAIT_POSS)); - /* Start to change. */ - SET_BIT(RCU->CFG, RCU_CFG_CKCFG_MSK); - - /* Wait system clock ready. */ - while (!READ_BIT(RCU->CON, RCU_CON_SWRDY_MSK)); - - // - // Remember the system clock. - // - SystemCoreClock = 48000000; -} - -/******************************************************************************* - * Function Name : SysTick_Configuration - * Description : Configures the SysTick for OS tick. - * Input : None - * Output : None - * Return : None - *******************************************************************************/ -void SysTick_Configuration(void) -{ - /* ticks = sysclk / RT_TICK_PER_SECOND */ - SysTick_Config(SystemCoreClock / RT_TICK_PER_SECOND); -} - -/** - * This is the timer interrupt service routine. - * - */ -void SysTick_Handler(void) -{ - /* enter interrupt */ - rt_interrupt_enter(); - - rt_tick_increase(); - - /* leave interrupt */ - rt_interrupt_leave(); -} - -/*@}*/ -/** - * This function will initial ES32F0 board. - */ -void rt_hw_board_init(void) -{ - /* NVIC Configuration */ - NVIC_Configuration(); - - /*System Clock Configuration */ - SystemClock_Config(); - - /* Configure the SysTick */ - SysTick_Configuration(); - -#ifdef RT_USING_HEAP - rt_system_heap_init((void *)HEAP_BEGIN, (void *)HEAP_END); -#endif -#ifdef RT_USING_COMPONENTS_INIT - rt_components_board_init(); -#endif -#ifdef RT_USING_CONSOLE - rt_console_set_device(RT_CONSOLE_DEVICE_NAME); -#endif -} - diff --git a/bsp/essemi/es32f0271/drivers/board.h b/bsp/essemi/es32f0271/drivers/board.h deleted file mode 100644 index b1cb44890d..0000000000 --- a/bsp/essemi/es32f0271/drivers/board.h +++ /dev/null @@ -1,35 +0,0 @@ -/* - * Copyright (C) 2018 Shanghai Eastsoft Microelectronics Co., Ltd. - * - * SPDX-License-Identifier: Apache-2.0 - * - * Change Logs: - * Date Author Notes - * 2019-10-23 yuzrain the first version - */ - -// <<< Use Configuration Wizard in Context Menu >>> -#ifndef __BOARD_H__ -#define __BOARD_H__ - -#include "es32f0271.h" - -#define ES32F0_SRAM_SIZE 0x2000 -#define ES32F0_SRAM_END (0x20000000 + ES32F0_SRAM_SIZE) - -#if defined(__CC_ARM) || defined(__CLANG_ARM) - extern int Image$$RW_IRAM1$$ZI$$Limit; - #define HEAP_BEGIN ((void *)&Image$$RW_IRAM1$$ZI$$Limit) -#elif __ICCARM__ - #pragma section="HEAP" - #define HEAP_BEGIN (__segment_end("HEAP")) -#else - extern int __bss_end; - #define HEAP_BEGIN ((void *)&__bss_end) -#endif - -#define HEAP_END ES32F0_SRAM_END - -void rt_hw_board_init(void); - -#endif diff --git a/bsp/essemi/es32f0271/drivers/drv_adc.c b/bsp/essemi/es32f0271/drivers/drv_adc.c deleted file mode 100644 index d111b54f22..0000000000 --- a/bsp/essemi/es32f0271/drivers/drv_adc.c +++ /dev/null @@ -1,148 +0,0 @@ -/* - * Copyright (C) 2018 Shanghai Eastsoft Microelectronics Co., Ltd. - * - * SPDX-License-Identifier: Apache-2.0 - * - * Change Logs: - * Date Author Notes - * 2019-10-23 yuzrain the first version - */ - -#include -#include -#include -#include "board.h" -#include "drv_adc.h" -#include "md_gpio.h" -#include "md_adc.h" -#include "md_rcu.h" -#include "md_syscfg.h" - -#ifdef RT_USING_ADC - -#define BSP_ADC_CHANNEL_NUM 8 - -/* define adc instance */ -static struct rt_adc_device _device_adc0; - -/* enable or disable adc */ -static rt_err_t es32f0_adc_enabled(struct rt_adc_device *device, rt_uint32_t channel, rt_bool_t enabled) -{ - RT_ASSERT(device != RT_NULL); - - if (enabled) - { - md_adc_enable_ssen_ss0en(ADC); - } - else - { - md_adc_disable_ssen_ss0en(ADC); - } - - return RT_EOK; -} - -static void _adc_channel_config(rt_uint32_t channel) -{ - /* select gpio pin as adc function */ - switch (channel) - { - case 0: - md_gpio_set_mode(GPIOA, MD_GPIO_PIN_0, MD_GPIO_MODE_ANALOG); - break; - case 1: - md_gpio_set_mode(GPIOA, MD_GPIO_PIN_1, MD_GPIO_MODE_ANALOG); - break; - case 2: - md_gpio_set_mode(GPIOA, MD_GPIO_PIN_2, MD_GPIO_MODE_ANALOG); - break; - case 3: - md_gpio_set_mode(GPIOA, MD_GPIO_PIN_3, MD_GPIO_MODE_ANALOG); - break; - case 4: - md_gpio_set_mode(GPIOA, MD_GPIO_PIN_4, MD_GPIO_MODE_ANALOG); - break; - case 5: - md_gpio_set_mode(GPIOA, MD_GPIO_PIN_5, MD_GPIO_MODE_ANALOG); - break; - case 6: - md_gpio_set_mode(GPIOA, MD_GPIO_PIN_6, MD_GPIO_MODE_ANALOG); - break; - case 7: - md_gpio_set_mode(GPIOA, MD_GPIO_PIN_7, MD_GPIO_MODE_ANALOG); - break; - default: - break; - } -} - -static rt_err_t es32f0_get_adc_value(struct rt_adc_device *device, rt_uint32_t channel, rt_uint32_t *value) -{ - rt_uint32_t chn_data[BSP_ADC_CHANNEL_NUM]; - rt_uint32_t i; - - RT_ASSERT(device != RT_NULL); - RT_ASSERT(value != RT_NULL); - - /* config adc channel */ - _adc_channel_config(channel); - - md_adc_set_swtri_ss0(ADC); - - while ((ADC->RIF & ADC_RIF_SS0RIF_MSK) == 0); - - for (i=0; i -#include -#include "board.h" -#include "drv_gpio.h" - -#ifdef RT_USING_PIN - -#define __ES32F0_PIN(index, gpio, gpio_index) {index, GPIO##gpio, gpio_index} -#define __ES32F0_PIN_DEFAULT {-1, 0, 0} - -/* ES32F0 GPIO driver */ -struct pin_index -{ - int index; - GPIO_TypeDef *gpio; - uint32_t pin; -}; - -static const struct pin_index pins[] = -{ - __ES32F0_PIN_DEFAULT, - __ES32F0_PIN_DEFAULT, - __ES32F0_PIN(2, C, 13), - __ES32F0_PIN(3, C, 14), - __ES32F0_PIN(4, C, 15), - __ES32F0_PIN(5, D, 14), - __ES32F0_PIN(6, D, 15), - __ES32F0_PIN(7, D, 13), - __ES32F0_PIN(8, C, 0), - __ES32F0_PIN(9, C, 1), - __ES32F0_PIN(10, C, 2), - __ES32F0_PIN(11, C, 3), - __ES32F0_PIN_DEFAULT, - __ES32F0_PIN_DEFAULT, - __ES32F0_PIN(14, A, 0), - __ES32F0_PIN(15, A, 1), - __ES32F0_PIN(16, A, 2), - __ES32F0_PIN(17, A, 3), - __ES32F0_PIN(18, D, 0), - __ES32F0_PIN(19, D, 1), - __ES32F0_PIN(20, A, 4), - __ES32F0_PIN(21, A, 5), - __ES32F0_PIN(22, A, 6), - __ES32F0_PIN(23, A, 7), - __ES32F0_PIN(24, C, 4), - __ES32F0_PIN(25, C, 5), - __ES32F0_PIN(26, B, 0), - __ES32F0_PIN(27, B, 1), - __ES32F0_PIN(28, B, 2), - __ES32F0_PIN(29, B, 10), - __ES32F0_PIN(30, B, 11), - __ES32F0_PIN_DEFAULT, - __ES32F0_PIN_DEFAULT, - __ES32F0_PIN(33, B, 12), - __ES32F0_PIN(34, B, 13), - __ES32F0_PIN(35, B, 14), - __ES32F0_PIN(36, B, 15), - __ES32F0_PIN(37, C, 6), - __ES32F0_PIN(38, C, 7), - __ES32F0_PIN(39, C, 8), - __ES32F0_PIN(40, C, 9), - __ES32F0_PIN(41, A, 8), - __ES32F0_PIN(42, A, 9), - __ES32F0_PIN(43, A, 10), - __ES32F0_PIN(44, A, 11), - __ES32F0_PIN(45, A, 12), - __ES32F0_PIN(46, A, 13), - __ES32F0_PIN_DEFAULT, - __ES32F0_PIN_DEFAULT, - __ES32F0_PIN(49, A, 14), - __ES32F0_PIN(50, A, 15), - __ES32F0_PIN(51, C, 10), - __ES32F0_PIN(52, C, 11), - __ES32F0_PIN(53, C, 12), - __ES32F0_PIN(54, D, 2), - __ES32F0_PIN(55, B, 3), - __ES32F0_PIN(56, B, 4), - __ES32F0_PIN(57, B, 5), - __ES32F0_PIN(58, B, 6), - __ES32F0_PIN(59, B, 7), - __ES32F0_PIN(60, D, 3), - __ES32F0_PIN(61, B, 8), - __ES32F0_PIN(62, B, 9), - __ES32F0_PIN_DEFAULT, - __ES32F0_PIN_DEFAULT, -}; - -struct pin_irq_map -{ - rt_uint16_t pinbit; - IRQn_Type irqno; -}; -static const struct pin_irq_map pin_irq_map[] = -{ - {0, EXTI_0to1_IRQn}, - {1, EXTI_0to1_IRQn}, - {2, EXTI_2to3_IRQn}, - {3, EXTI_2to3_IRQn}, - {4, EXTI_4to15_IRQn}, - {5, EXTI_4to15_IRQn}, - {6, EXTI_4to15_IRQn}, - {7, EXTI_4to15_IRQn}, - {8, EXTI_4to15_IRQn}, - {9, EXTI_4to15_IRQn}, - {10, EXTI_4to15_IRQn}, - {11, EXTI_4to15_IRQn}, - {12, EXTI_4to15_IRQn}, - {13, EXTI_4to15_IRQn}, - {14, EXTI_4to15_IRQn}, - {15, EXTI_4to15_IRQn}, -}; - -struct rt_pin_irq_hdr pin_irq_hdr_tab[] = -{ - { -1, 0, RT_NULL, RT_NULL}, - { -1, 0, RT_NULL, RT_NULL}, - { -1, 0, RT_NULL, RT_NULL}, - { -1, 0, RT_NULL, RT_NULL}, - { -1, 0, RT_NULL, RT_NULL}, - { -1, 0, RT_NULL, RT_NULL}, - { -1, 0, RT_NULL, RT_NULL}, - { -1, 0, RT_NULL, RT_NULL}, - { -1, 0, RT_NULL, RT_NULL}, - { -1, 0, RT_NULL, RT_NULL}, - { -1, 0, RT_NULL, RT_NULL}, - { -1, 0, RT_NULL, RT_NULL}, - { -1, 0, RT_NULL, RT_NULL}, - { -1, 0, RT_NULL, RT_NULL}, - { -1, 0, RT_NULL, RT_NULL}, - { -1, 0, RT_NULL, RT_NULL}, -}; - -#define ITEM_NUM(items) sizeof(items) / sizeof(items[0]) -const struct pin_index *get_pin(uint8_t pin) -{ - const struct pin_index *index; - if (pin < ITEM_NUM(pins)) - { - index = &pins[pin]; - if (index->index == -1) - index = RT_NULL; - } - else - { - index = RT_NULL; - } - return index; -}; - -void es32f0_pin_write(rt_device_t dev, rt_base_t pin, rt_base_t value) -{ - const struct pin_index *index; - index = get_pin(pin); - if (index == RT_NULL) - { - return; - } - - /* Write GPIO */ - if (value == 0) - SET_BIT(index->gpio->BSBR, 0x1<<(index->pin+16)); - else - SET_BIT(index->gpio->BSBR, 0x1<pin); -} - -int es32f0_pin_read(rt_device_t dev, rt_base_t pin) -{ - int value; - const struct pin_index *index; - value = PIN_LOW; - index = get_pin(pin); - if (index == RT_NULL) - { - return value; - } - - /* Read the GPIO value with the spcified index */ - value = (index->gpio->IDATA & (0x1<pin)) != 0; - - return value; -} - -void es32f0_pin_mode(rt_device_t dev, rt_base_t pin, rt_base_t mode) -{ - const struct pin_index *index; - GPIO_TypeDef *gpiox; - index = get_pin(pin); - if (index == RT_NULL) - { - return; - } - - /* Get the IO port */ - gpiox = index->gpio; - - /* Config GPIO */ - switch(mode) - { - case PIN_MODE_OUTPUT: - { - /* pushpull & output & 16mA */ - MODIFY_REG(gpiox->MOD, (0x3<<(index->pin*2)), (0x1<<(index->pin*2))); - CLEAR_BIT(gpiox->OT, (0x1<pin)); - CLEAR_BIT(gpiox->DS, (0x1<pin)); - break; - } - case PIN_MODE_OUTPUT_OD: - { - /* opendrain & output & 16mA */ - MODIFY_REG(gpiox->MOD, (0x3<pin), (0x1<pin)); - SET_BIT(gpiox->OT, (0x1<pin)); - CLEAR_BIT(gpiox->DS, (0x1<pin)); - break; - } - case PIN_MODE_INPUT: - { - /* input & no pull & CMOS & filter */ - MODIFY_REG(gpiox->MOD, (0x3<pin), (0x0<pin)); - MODIFY_REG(gpiox->PUD, (0x3<pin), (0x0<pin)); - SET_BIT(gpiox->IST, (0x1<pin)); - SET_BIT(gpiox->FIR, (0x1<pin)); - break; - } - case PIN_MODE_INPUT_PULLUP: - { - /* input & pull up & CMOS & filter */ - MODIFY_REG(gpiox->MOD, (0x3<pin), (0x0<pin)); - MODIFY_REG(gpiox->PUD, (0x3<pin), (0x1<pin)); - SET_BIT(gpiox->IST, (0x1<pin)); - SET_BIT(gpiox->FIR, (0x1<pin)); - break; - } - case PIN_MODE_INPUT_PULLDOWN: - { - /* input & pull down & CMOS & filter */ - MODIFY_REG(gpiox->MOD, (0x3<pin), (0x0<pin)); - MODIFY_REG(gpiox->PUD, (0x3<pin), (0x2<pin)); - SET_BIT(gpiox->IST, (0x1<pin)); - SET_BIT(gpiox->FIR, (0x1<pin)); - break; - } - default: - { - /* output */ - MODIFY_REG(gpiox->MOD, (0x3<pin), (0x1<pin)); - } - } -} - -rt_inline const struct pin_irq_map *get_pin_irq_map(rt_uint16_t gpio_pin) -{ - rt_int32_t mapindex = gpio_pin & 0x00FF; - if (mapindex < 0 || mapindex >= ITEM_NUM(pin_irq_map)) - { - return RT_NULL; - } - return &pin_irq_map[mapindex]; -}; - -rt_err_t es32f0_pin_attach_irq(struct rt_device *device, rt_int32_t pin, - rt_uint32_t mode, void (*hdr)(void *args), void *args) -{ - const struct pin_index *index; - rt_base_t level; - rt_int32_t irqindex; - index = get_pin(pin); - if (index == RT_NULL) - { - return RT_ENOSYS; - } - /* pin no. convert to dec no. */ - for (irqindex = 0; irqindex < 16; irqindex++) - { - if ((0x01 << irqindex) == index->pin) - { - break; - } - } - if (irqindex < 0 || irqindex >= ITEM_NUM(pin_irq_map)) - { - return RT_ENOSYS; - } - level = rt_hw_interrupt_disable(); - if (pin_irq_hdr_tab[irqindex].pin == pin && - pin_irq_hdr_tab[irqindex].hdr == hdr && - pin_irq_hdr_tab[irqindex].mode == mode && - pin_irq_hdr_tab[irqindex].args == args) - { - rt_hw_interrupt_enable(level); - return RT_EOK; - } - if (pin_irq_hdr_tab[irqindex].pin != -1) - { - rt_hw_interrupt_enable(level); - return RT_EBUSY; - } - pin_irq_hdr_tab[irqindex].pin = pin; - pin_irq_hdr_tab[irqindex].hdr = hdr; - pin_irq_hdr_tab[irqindex].mode = mode; - pin_irq_hdr_tab[irqindex].args = args; - rt_hw_interrupt_enable(level); - return RT_EOK; -} - -rt_err_t es32f0_pin_detach_irq(struct rt_device *device, rt_int32_t pin) -{ - const struct pin_index *index; - rt_base_t level; - rt_int32_t irqindex = -1; - index = get_pin(pin); - if (index == RT_NULL) - { - return RT_ENOSYS; - } - irqindex = index->pin & 0x00FF; - if (irqindex < 0 || irqindex >= ITEM_NUM(pin_irq_map)) - { - return RT_ENOSYS; - } - level = rt_hw_interrupt_disable(); - if (pin_irq_hdr_tab[irqindex].pin == -1) - { - rt_hw_interrupt_enable(level); - return RT_EOK; - } - pin_irq_hdr_tab[irqindex].pin = -1; - pin_irq_hdr_tab[irqindex].hdr = RT_NULL; - pin_irq_hdr_tab[irqindex].mode = 0; - pin_irq_hdr_tab[irqindex].args = RT_NULL; - rt_hw_interrupt_enable(level); - return RT_EOK; -} - -rt_err_t es32f0_pin_irq_enable(struct rt_device *device, rt_base_t pin, - rt_uint32_t enabled) -{ - const struct pin_index *index; - const struct pin_irq_map *irqmap; - GPIO_TypeDef *gpiox; - rt_base_t level; - rt_int32_t irqindex = -1; - - index = get_pin(pin); - if (index == RT_NULL) - { - return RT_ENOSYS; - } - - /* Get the IO port */ - gpiox = index->gpio; - - if (enabled == PIN_IRQ_ENABLE) - { - /* pin no. convert to dec no. */ - for (irqindex = 0; irqindex < 16; irqindex++) - { - if ((0x01 << irqindex) == index->pin) - { - break; - } - } - if (irqindex < 0 || irqindex >= ITEM_NUM(pin_irq_map)) - { - return RT_ENOSYS; - } - level = rt_hw_interrupt_disable(); - if (pin_irq_hdr_tab[irqindex].pin == -1) - { - rt_hw_interrupt_enable(level); - return RT_ENOSYS; - } - irqmap = &pin_irq_map[irqindex]; - - /* Config EXTI */ - MODIFY_REG(gpiox->MOD, (0x3<pin), (0x0<pin)); - SET_BIT(gpiox->FIR, index->pin); - SET_BIT(gpiox->IST, index->pin); - MODIFY_REG(((uint32_t *)(&EXTI->ICFG1))[index->pin/8], - 0xF<<(index->pin%8), - (((uint32_t)(index->gpio) - AHB2_BASE)/0x400)<<(index->pin%8)); - SET_BIT(EXTI->DB, 0x1<pin); - - switch (pin_irq_hdr_tab[irqindex].mode) - { - case PIN_IRQ_MODE_RISING: - { - /* pull down the pin */ - MODIFY_REG(gpiox->PUD, (0x3<pin), (0x2<pin)); - /* Enable EXTI rising interrupt and disable falling interrupt */ - SET_BIT(EXTI->RTS, (0x1<pin)); - CLEAR_BIT(EXTI->FTS, (0x1<pin)); - break; - } - case PIN_IRQ_MODE_FALLING: - { - /* pull up the pin */ - MODIFY_REG(gpiox->PUD, (0x3<pin), (0x1<pin)); - /* Enable EXTI falling interrupt and disable rising interrupt */ - CLEAR_BIT(EXTI->RTS, (0x1<pin)); - SET_BIT(EXTI->FTS, (0x1<pin)); - break; - } - case PIN_IRQ_MODE_RISING_FALLING: - { - /* pull up the pin */ - MODIFY_REG(gpiox->PUD, (0x3<pin), (0x1<pin)); - /* Enable EXTI falling interrupt and enable rising interrupt */ - SET_BIT(EXTI->RTS, (0x1<pin)); - SET_BIT(EXTI->FTS, (0x1<pin)); - break; - } - } - - /* Enable EXTI interrupt */ - SET_BIT(EXTI->IER, (0x1<pin)); - NVIC_EnableIRQ(irqmap->irqno); - rt_hw_interrupt_enable(level); - } - else if (enabled == PIN_IRQ_DISABLE) - { - irqmap = get_pin_irq_map(index->pin); - if (irqmap == RT_NULL) - { - return RT_ENOSYS; - } - NVIC_DisableIRQ(irqmap->irqno); - } - else - { - return RT_ENOSYS; - } - return RT_EOK; -} - -const static struct rt_pin_ops _es32f0_pin_ops = -{ - es32f0_pin_mode, - es32f0_pin_write, - es32f0_pin_read, - es32f0_pin_attach_irq, - es32f0_pin_detach_irq, - es32f0_pin_irq_enable, - RT_NULL, -}; - -int rt_hw_pin_init(void) -{ - int result; - - /* Open IO clock */ - SET_BIT(RCU->AHBEN, RCU_AHBEN_GPDEN_MSK|RCU_AHBEN_GPCEN_MSK \ - |RCU_AHBEN_GPBEN_MSK|RCU_AHBEN_GPAEN_MSK); - - /* register IO device */ - result = rt_device_pin_register("pin", &_es32f0_pin_ops, RT_NULL); - return result; -} -INIT_BOARD_EXPORT(rt_hw_pin_init); - -rt_inline void pin_irq_hdr(uint16_t GPIO_Pin) -{ - uint16_t irqno; - /* pin no. convert to dec no. */ - for (irqno = 0; irqno < 16; irqno++) - { - if ((0x01 << irqno) == GPIO_Pin) - { - break; - } - } - if (irqno == 16) - return; - if (pin_irq_hdr_tab[irqno].hdr) - { - pin_irq_hdr_tab[irqno].hdr(pin_irq_hdr_tab[irqno].args); - } -} - -void GPIO_EXTI_Callback(uint16_t GPIO_Pin) -{ - /* Read the exti interrupt then clear the flag */ - if ((EXTI->RIF & (0x1<ICR, 0x1< -#include -#include -#include -#include -#include "md_ad16c4t.h" -#include "md_rcu.h" - -#ifdef RT_USING_HWTIMER - -/* Defien the hardware timer control struct */ -struct es32f0_hwtimer_dev -{ - rt_hwtimer_t parent; - AD16C4T_TypeDef *hwtimer_periph; - IRQn_Type IRQn; -}; - -#ifdef BSP_USING_HWTIMER1 -static struct es32f0_hwtimer_dev hwtimer1; - -void BS16T1_IRQHandler(void) -{ - /* if BS16T1 IT */ - if (BS16T1->IFM & AD16C4T_RIF_UI_MSK) - { - SET_BIT(BS16T1->ICR, AD16C4T_ICR_UI_MSK); - rt_device_hwtimer_isr(&hwtimer1.parent); - - if (HWTIMER_MODE_ONESHOT == hwtimer1.parent.mode) - { - CLEAR_BIT(BS16T1->CON1, AD16C4T_CON1_CNTEN_MSK); - } - } -} -#endif - -static struct rt_hwtimer_info es32f0_hwtimer_info = -{ - 48000000, /* maximum count frequency */ - 1, /* minimum count frequency */ - 65535, /* counter maximum value */ - HWTIMER_CNTMODE_UP -}; - -static void es32f0_hwtimer_init(rt_hwtimer_t *timer, rt_uint32_t state) -{ - struct es32f0_hwtimer_dev *hwtimer = (struct es32f0_hwtimer_dev *)timer->parent.user_data; - - RT_ASSERT(hwtimer != RT_NULL); - - if (1 == state) - { - /* Set frequency */ - WRITE_REG(hwtimer->hwtimer_periph->PRES, (SystemCoreClock/hwtimer->parent.freq - 1)); - /* Enable timer IT */ - SET_BIT(hwtimer->hwtimer_periph->IER, AD16C4T_IER_UI_MSK); - NVIC_EnableIRQ(hwtimer->IRQn); - } - else - { - /* Dsiable timer IT */ - SET_BIT(hwtimer->hwtimer_periph->IDR, AD16C4T_IER_UI_MSK); - } -} - -static rt_err_t es32f0_hwtimer_start(rt_hwtimer_t *timer, - rt_uint32_t cnt, - rt_hwtimer_mode_t mode) -{ - struct es32f0_hwtimer_dev *hwtimer = (struct es32f0_hwtimer_dev *)timer->parent.user_data; - - RT_ASSERT(hwtimer != RT_NULL); - - WRITE_REG(hwtimer->hwtimer_periph->AR, cnt); - SET_BIT(hwtimer->hwtimer_periph->CON1, AD16C4T_CON1_CNTEN_MSK); - - return RT_EOK; -} - -static void es32f0_hwtimer_stop(rt_hwtimer_t *timer) -{ - struct es32f0_hwtimer_dev *hwtimer = (struct es32f0_hwtimer_dev *)timer->parent.user_data; - - RT_ASSERT(hwtimer != RT_NULL); - - CLEAR_BIT(hwtimer->hwtimer_periph->CON1, AD16C4T_CON1_CNTEN_MSK); -} - -static rt_uint32_t es32f0_hwtimer_count_get(rt_hwtimer_t *timer) -{ - struct es32f0_hwtimer_dev *hwtimer = (struct es32f0_hwtimer_dev *)timer->parent.user_data; - uint32_t hwtimer_count = 0; - - RT_ASSERT(hwtimer != RT_NULL); - - hwtimer_count = READ_REG(hwtimer->hwtimer_periph->COUNT); - - return hwtimer_count; -} - -static rt_err_t es32f0_hwtimer_control(rt_hwtimer_t *timer, - rt_uint32_t cmd, - void *args) -{ - rt_err_t ret = RT_EOK; - rt_uint32_t freq = 0; - struct es32f0_hwtimer_dev *hwtimer = (struct es32f0_hwtimer_dev *)timer->parent.user_data; - - RT_ASSERT(hwtimer != RT_NULL); - - switch (cmd) - { - case HWTIMER_CTRL_FREQ_SET: - freq = *(rt_uint32_t *)args; - if ((freq < hwtimer->parent.info->minfreq) || (freq > hwtimer->parent.info->maxfreq)) - { - ret = RT_EINVAL; - } - /* Set frequency */ - WRITE_REG(hwtimer->hwtimer_periph->PRES, (SystemCoreClock/freq - 1)); - break; - - case HWTIMER_CTRL_STOP: - CLEAR_BIT(hwtimer->hwtimer_periph->CON1, AD16C4T_CON1_CNTEN_MSK); - break; - - default: - ret = RT_EINVAL; - break; - } - - return ret; -} - -static struct rt_hwtimer_ops es32f0_hwtimer_ops = -{ - es32f0_hwtimer_init, - es32f0_hwtimer_start, - es32f0_hwtimer_stop, - es32f0_hwtimer_count_get, - es32f0_hwtimer_control -}; - -int rt_hw_hwtimer_init(void) -{ - rt_err_t ret = RT_EOK; - -#ifdef BSP_USING_HWTIMER1 - /*Open clock*/ - SET_BIT(RCU->APB1EN, RCU_APB1EN_BS16T1EN_MSK); - - hwtimer1.hwtimer_periph = BS16T1; - hwtimer1.IRQn = BS16T1_IRQn; - hwtimer1.parent.info = &es32f0_hwtimer_info; - hwtimer1.parent.ops = &es32f0_hwtimer_ops; - ret = rt_device_hwtimer_register(&hwtimer1.parent, "timer1", &hwtimer1); -#endif - - return ret; -} -INIT_BOARD_EXPORT(rt_hw_hwtimer_init); - -#endif diff --git a/bsp/essemi/es32f0271/drivers/drv_hwtimer.h b/bsp/essemi/es32f0271/drivers/drv_hwtimer.h deleted file mode 100644 index 576671e735..0000000000 --- a/bsp/essemi/es32f0271/drivers/drv_hwtimer.h +++ /dev/null @@ -1,16 +0,0 @@ -/* - * Copyright (C) 2018 Shanghai Eastsoft Microelectronics Co., Ltd. - * - * SPDX-License-Identifier: Apache-2.0 - * - * Change Logs: - * Date Author Notes - * 2019-10-23 yuzrain the first version - */ - -#ifndef DRV_HWTIMER_H__ -#define DRV_HWTIMER_H__ - -int rt_hw_hwtimer_init(void); - -#endif diff --git a/bsp/essemi/es32f0271/drivers/drv_i2c.c b/bsp/essemi/es32f0271/drivers/drv_i2c.c deleted file mode 100644 index fb4f79de09..0000000000 --- a/bsp/essemi/es32f0271/drivers/drv_i2c.c +++ /dev/null @@ -1,275 +0,0 @@ -/* - * Copyright (C) 2018 Shanghai Eastsoft Microelectronics Co., Ltd. - * - * SPDX-License-Identifier: Apache-2.0 - * - * Change Logs: - * Date Author Notes - * 2019-10-23 yuzrain the first version - */ - -#include -#include -#include -#include "board.h" -#include "drv_i2c.h" -#include "md_i2c.h" -#include "md_gpio.h" - -#ifdef RT_USING_I2C - -#define TIMEOUT 0xF -/* Define I2C hardware SCL timeout */ -#define I2C_TIMING_48MHZ_CLK100KHZ ((0xBU<<28)|(4<<20)|(2<<16)|(0xF<<8)|(0x13)) - -/** - * @brief: I2C receive. - * @param: i2cx, pointer to the I2Cx - * @param: addr, address - * @param: buf, send data buffer - * @param: len, the length of buf - * @param: timout, timeout - * @retval: rt_err_t - */ -static rt_err_t __i2c_master_recv(I2C_TypeDef *i2cx, rt_uint16_t addr, - rt_uint8_t *buf, rt_uint16_t len, rt_uint32_t timout) -{ - rt_uint32_t rt_timout; - - // - // Config I2C transfer mode - // - md_i2c_set_con2_add10(i2cx, MD_I2C_ADDRESSINGMODE_7BIT); - /* Config slaver address */ - md_i2c_set_con2_sadd(i2cx, addr); - /* Config data size */ - md_i2c_set_con2_nbytes(i2cx, len); - /* Reset TX FIFO */ - md_i2c_set_fcon_txfrst(i2cx, MD_I2C_TXFIFO_RESET); - /* Config mode */ - md_i2c_set_con2_rd_wrn(i2cx, MD_I2C_MASTER_READ); - /* Config auto-reload */ - md_i2c_set_con2_reload(i2cx, MD_I2C_NORELOAD_MODE); - /* When NBYTES is matched, the communication will be automatically stop */ - md_i2c_set_con2_autoend(i2cx, MD_I2C_AUTOEND_MODE); - /* Start the I2C communication */ - md_i2c_set_con2_start(i2cx, MD_I2C_START_GENERATION); - - while (len > 0) - { - /* Wait Rx FIFO non-empty */ - rt_timout = timout; - while (md_i2c_is_active_stat_rxe(i2cx) && (--rt_timout)); - if (rt_timout == 0) - return RT_ETIMEOUT; - - *buf++ = md_i2c_recv(i2cx); - len--; - } - - return RT_EOK; -} - -/** - * @brief: I2C send. - * @param: i2cx, pointer to the I2Cx - * @param: addr, address - * @param: buf, send data buffer - * @param: len, the length of buf - * @param: timout, timeout - * @retval: rt_err_t - */ -static rt_err_t __i2c_master_send(I2C_TypeDef *i2cx, rt_uint16_t addr, - rt_uint8_t *buf, rt_uint16_t len, rt_uint32_t timout) -{ - rt_uint32_t rt_timout; - rt_uint8_t index; - - // - // Config I2C transfer mode - // - md_i2c_set_con2_add10(i2cx, MD_I2C_ADDRESSINGMODE_7BIT); - /* Config slaver address */ - md_i2c_set_con2_sadd(i2cx, addr); - /* Config data size */ - md_i2c_set_con2_nbytes(i2cx, len); - /* Reset TX FIFO */ - md_i2c_set_fcon_txfrst(i2cx, MD_I2C_TXFIFO_RESET); - /* Config mode */ - md_i2c_set_con2_rd_wrn(i2cx, MD_I2C_MASTER_WRITE); - /* Enable auto-end */ - md_i2c_set_con2_autoend(i2cx, MD_I2C_AUTOEND_MODE); - - // - // Check if the bus is busy - // - /* Wait bus to be ready */ - rt_timout = timout; - while ((READ_BIT(i2cx->STAT, I2C_STAT_BUSY_MSK) == I2C_STAT_BUSY_MSK) && (--rt_timout)); - if (rt_timout == 0) - return RT_EBUSY; - - // - // Start to send - // - if (len <= 8) - { - for (index = 0; index < len; index++) - md_i2c_send(i2cx, *buf++); - - len = 0; - } - else - { - for (index = 0; index < 8; index++) - md_i2c_send(i2cx, *buf++); - - len -= 8; - } - - /* Start the I2C communication */ - md_i2c_set_con2_start(i2cx, MD_I2C_START_GENERATION); - - while (len > 0) - { - rt_timout = timout; - while (md_i2c_is_active_stat_txf(i2cx) && (--rt_timout)); - if (rt_timout == 0) - return RT_ETIMEOUT; - - md_i2c_send(i2cx, *buf++); - len--; - } - - return RT_EOK; -} - -static rt_size_t es32f0_master_xfer(struct rt_i2c_bus_device *bus, - struct rt_i2c_msg msgs[], - rt_uint32_t num) -{ - struct rt_i2c_msg *msg; - rt_uint32_t i; - rt_err_t ret = RT_ERROR; - - for (i = 0; i < num; i++) - { - msg = &msgs[i]; - if (msg->flags & RT_I2C_RD) - { - if (__i2c_master_recv(bus->priv, msg->addr << 1, msg->buf, msg->len, TIMEOUT) != 0) - { - LOG_E("i2c bus write failed,i2c bus stop!\n"); - goto out; - } - } - else - { - if (__i2c_master_send(bus->priv, msg->addr << 1, msg->buf, msg->len, TIMEOUT) != 0) - { - LOG_E("i2c bus write failed,i2c bus stop!\n"); - goto out; - } - } - } - - ret = i; - -out: - LOG_E("send stop condition\n"); - - return ret; -} - -const struct rt_i2c_bus_device_ops es32f0_i2c_ops = -{ - es32f0_master_xfer, - RT_NULL, - RT_NULL, -}; - -static void _i2c_init(void) -{ - md_i2c_inittypedef I2C_Init = - { - .Timing = CLK100kHz48M, - .Address1 = 0x55 << 1, - .AddrSize = MD_I2C_ADDRESSINGMODE_7BIT, - .DualAddressMode = MD_I2C_DUALADDRESS_DISABLE, - .Address2 = 0xAA, - .Address2Masks = MD_I2C_ADDR2_NOMASK - }; - -#ifdef BSP_USING_I2C1 - /* Open I2C clock */ - SET_BIT(RCU->APB1EN, RCU_APB1EN_I2C1EN_MSK); - - /* GPIO configuration */ - md_gpio_set_pull (GPIOC, MD_GPIO_PIN_12, MD_GPIO_PULL_UP); - md_gpio_set_pull (GPIOD, MD_GPIO_PIN_2, MD_GPIO_PULL_UP); - md_gpio_set_output_type (GPIOC, MD_GPIO_PIN_12, MD_GPIO_OUTPUT_OPENDRAIN); - md_gpio_set_output_type (GPIOD, MD_GPIO_PIN_2, MD_GPIO_OUTPUT_OPENDRAIN); - md_gpio_set_mode (GPIOC, MD_GPIO_PIN_12, MD_GPIO_MODE_FUNCTION); - md_gpio_set_mode (GPIOD, MD_GPIO_PIN_2, MD_GPIO_MODE_FUNCTION); - md_gpio_set_function8_15(GPIOC, MD_GPIO_PIN_12, MD_GPIO_AF1); - md_gpio_set_function0_7 (GPIOD, MD_GPIO_PIN_2, MD_GPIO_AF1); - - // - // Config I2C - // - md_i2c_init(I2C1, &I2C_Init); -#endif - -#ifdef BSP_USING_I2C2 - /* Open I2C clock */ - SET_BIT(RCU->APB1EN, RCU_APB1EN_I2C2EN_MSK); - - /* GPIO configuration */ - md_gpio_set_pull (GPIOB, MD_GPIO_PIN_10, MD_GPIO_PULL_UP); - md_gpio_set_pull (GPIOB, MD_GPIO_PIN_11, MD_GPIO_PULL_UP); - md_gpio_set_output_type (GPIOB, MD_GPIO_PIN_10, MD_GPIO_OUTPUT_OPENDRAIN); - md_gpio_set_output_type (GPIOB, MD_GPIO_PIN_11, MD_GPIO_OUTPUT_OPENDRAIN); - md_gpio_set_mode (GPIOB, MD_GPIO_PIN_10, MD_GPIO_MODE_FUNCTION); - md_gpio_set_mode (GPIOB, MD_GPIO_PIN_11, MD_GPIO_MODE_FUNCTION); - md_gpio_set_function8_15(GPIOB, MD_GPIO_PIN_10, MD_GPIO_AF1); - md_gpio_set_function8_15(GPIOB, MD_GPIO_PIN_11, MD_GPIO_AF1); - - // - // Config I2C - // - md_i2c_init(I2C2, &I2C_Init); -#endif -} - -#ifdef BSP_USING_I2C2 -static struct rt_i2c_bus_device i2c_device2; -#endif - -#ifdef BSP_USING_I2C1 -static struct rt_i2c_bus_device i2c_device1; -#endif -int rt_hw_i2c_init(void) -{ - _i2c_init(); - -#ifdef BSP_USING_I2C2 - /* define i2c Instance */ - rt_memset((void *)&i2c_device2, 0, sizeof(struct rt_i2c_bus_device)); - i2c_device2.ops = &es32f0_i2c_ops; - i2c_device2.priv = I2C2; - rt_i2c_bus_device_register(&i2c_device2, "i2c2"); -#endif - -#ifdef BSP_USING_I2C1 - /* define i2c Instance */ - rt_memset((void *)&i2c_device1, 0, sizeof(struct rt_i2c_bus_device)); - i2c_device1.ops = &es32f0_i2c_ops; - i2c_device1.priv = I2C1; - rt_i2c_bus_device_register(&i2c_device1, "i2c1"); -#endif - - return RT_EOK; -} -INIT_DEVICE_EXPORT(rt_hw_i2c_init); - -#endif diff --git a/bsp/essemi/es32f0271/drivers/drv_i2c.h b/bsp/essemi/es32f0271/drivers/drv_i2c.h deleted file mode 100644 index 7af06805f7..0000000000 --- a/bsp/essemi/es32f0271/drivers/drv_i2c.h +++ /dev/null @@ -1,16 +0,0 @@ -/* - * Copyright (C) 2018 Shanghai Eastsoft Microelectronics Co., Ltd. - * - * SPDX-License-Identifier: Apache-2.0 - * - * Change Logs: - * Date Author Notes - * 2019-10-23 yuzrain the first version - */ - -#ifndef DRV_I2C_H__ -#define DRV_I2C_H__ - -int rt_hw_i2c_init(void); - -#endif diff --git a/bsp/essemi/es32f0271/drivers/drv_pwm.c b/bsp/essemi/es32f0271/drivers/drv_pwm.c deleted file mode 100644 index 768fcd04cd..0000000000 --- a/bsp/essemi/es32f0271/drivers/drv_pwm.c +++ /dev/null @@ -1,208 +0,0 @@ -/* - * Copyright (C) 2018 Shanghai Eastsoft Microelectronics Co., Ltd. - * - * SPDX-License-Identifier: Apache-2.0 - * - * Change Logs: - * Date Author Notes - * 2019-10-23 yuzrain the first version - */ - -#include -#include -#include -#include -#include "md_gpio.h" - -/* PWM device control struct */ -struct pwm_dev_ctrl { - AD16C4T_TypeDef *timx; - rt_uint8_t chnm; /* Cannel number */ - struct rt_pwm_configuration *cfg; -}; - -#ifdef BSP_USING_PWM_GP16C2T1 - -/* Remember channel configuration */ -static struct rt_pwm_configuration pwm_ch_cfg_gp16c2t1[2] = { - [0] = { - .channel = 1, - .period = 0, - .pulse = 0 - }, - [1] = { - .channel = 2, - .period = 0, - .pulse = 0 - } -}; - -/* Define static device */ -static struct rt_device_pwm pwm_dev_gp16c2t1; -static struct pwm_dev_ctrl pwm_dev_gp16c2t1_ctrl; -#endif -#ifdef BSP_USING_PWM_GP16C2T4 - -/* Remember channel configuration */ -static struct rt_pwm_configuration pwm_ch_cfg_gp16c2t4[2] = { - [0] = { - .channel = 1, - .period = 0, - .pulse = 0 - }, - [1] = { - .channel = 2, - .period = 0, - .pulse = 0 - } -}; - -/* Define static device */ -static struct rt_device_pwm pwm_dev_gp16c2t4; -static struct pwm_dev_ctrl pwm_dev_gp16c2t4_ctrl; -#endif - -static void pwm_auto_config_freq(AD16C4T_TypeDef *timerx, uint32_t ns) -{ - uint32_t temp_ar; - uint32_t temp_pres = timerx->PRES & 0xFFFF; - uint32_t err_cnt = 0; - - /* Automatic setting frequency division ratio */ - while (err_cnt++ < 65536) - { - temp_ar = (uint64_t)SystemCoreClock * ns / 1000000000 / (temp_pres + 1); - if (temp_ar <= 0xFFFF) - break; - temp_pres++; - } - - /* Write back to PRES */ - timerx->PRES = (uint16_t)(temp_pres & 0xFFFF); - timerx->AR = temp_ar; -} - -static void pwm_set_duty(AD16C4T_TypeDef *timerx, uint8_t ch, uint32_t ns) -{ - uint32_t temp_pres = timerx->PRES & 0xFFFF; - uint64_t tmp = (uint64_t)SystemCoreClock * ns / 1000000000 / (temp_pres + 1); - - if (ch == 1) - WRITE_REG(timerx->CCVAL1, (uint32_t)tmp); - else if (ch == 2) - WRITE_REG(timerx->CCVAL2, (uint32_t)tmp); -} - -static rt_err_t es32f0_pwm_control(struct rt_device_pwm *device, int cmd, void *arg) -{ - rt_err_t ret = RT_EOK; - struct pwm_dev_ctrl *dev_ctrl - = (struct pwm_dev_ctrl *)device->parent.user_data; - struct rt_pwm_configuration *cfg = (struct rt_pwm_configuration *)arg; - AD16C4T_TypeDef *timerx = (AD16C4T_TypeDef *)dev_ctrl->timx; - - switch (cmd) - { - case PWM_CMD_ENABLE: - { - if (cfg->channel == 1) - SET_BIT(timerx->CCEP, AD16C4T_CCEP_CC1EN_MSK); - else if (cfg->channel == 2) - SET_BIT(timerx->CCEP, AD16C4T_CCEP_CC2EN_MSK); - break; - } - case PWM_CMD_DISABLE: - { - if (cfg->channel == 1) - CLEAR_BIT(timerx->CCEP, AD16C4T_CCEP_CC1EN_MSK); - else if (cfg->channel == 2) - CLEAR_BIT(timerx->CCEP, AD16C4T_CCEP_CC2EN_MSK); - break; - } - case PWM_CMD_SET: - { - /* count registers max 0xFFFF, auto adjust prescaler */ - pwm_auto_config_freq(timerx, cfg->period); - pwm_set_duty(timerx, cfg->channel, cfg->pulse); - /* Remember configuration */ - dev_ctrl->cfg[cfg->channel-1].period = cfg->period; - dev_ctrl->cfg[cfg->channel-1].pulse = cfg->pulse; - break; - } - case PWM_CMD_GET: - { - cfg->period = dev_ctrl->cfg[cfg->channel-1].period; - cfg->pulse = dev_ctrl->cfg[cfg->channel-1].pulse; - break; - } - - default: - break; - } - return ret; -} - -const static struct rt_pwm_ops es32f0_pwm_ops = -{ - es32f0_pwm_control -}; - -int rt_hw_pwm_init(void) -{ - rt_err_t ret = RT_EOK; - -#ifdef BSP_USING_PWM_GP16C2T1 /* 2 channels */ - /* Open clock */ - SET_BIT(RCU->APB2EN, RCU_APB2EN_GP16C2T1EN_MSK); - - /* GPIO configuration */ - md_gpio_set_mode (GPIOB, MD_GPIO_PIN_1, MD_GPIO_MODE_FUNCTION); - md_gpio_set_mode (GPIOB, MD_GPIO_PIN_2, MD_GPIO_MODE_FUNCTION); - md_gpio_set_function0_7 (GPIOB, MD_GPIO_PIN_1, MD_GPIO_AF5); - md_gpio_set_function0_7 (GPIOB, MD_GPIO_PIN_2, MD_GPIO_AF5); - - /* Timer configuration */ - MODIFY_REG(GP16C2T1->CHMR1, AD16C4T_CHMR1_OUTPUT_CH1MOD_MSK, - (6 << AD16C4T_CHMR1_OUTPUT_CH1MOD_POSS)); - MODIFY_REG(GP16C2T1->CHMR1, AD16C4T_CHMR1_OUTPUT_CH2MOD_MSK, - (6 << AD16C4T_CHMR1_OUTPUT_CH2MOD_POSS)); - SET_BIT(GP16C2T1->BDCFG, AD16C4T_BDCFG_GOEN_MSK); - SET_BIT(GP16C2T1->CON1, AD16C4T_CON1_CNTEN_MSK); - - pwm_dev_gp16c2t1_ctrl.chnm = 2; - pwm_dev_gp16c2t1_ctrl.timx = GP16C2T1; - pwm_dev_gp16c2t1_ctrl.cfg = pwm_ch_cfg_gp16c2t1; - /* Register PWM device */ - ret = rt_device_pwm_register(&pwm_dev_gp16c2t1, - "pwm1", &es32f0_pwm_ops, &pwm_dev_gp16c2t1_ctrl); -#endif - -#ifdef BSP_USING_PWM_GP16C2T4 /* 2 channels */ - /* Open clock */ - SET_BIT(RCU->APB2EN, RCU_APB2EN_GP16C2T4EN_MSK); - - /* GPIO configuration */ - md_gpio_set_mode (GPIOB, MD_GPIO_PIN_12, MD_GPIO_MODE_FUNCTION); - md_gpio_set_mode (GPIOB, MD_GPIO_PIN_14, MD_GPIO_MODE_FUNCTION); - md_gpio_set_function8_15(GPIOB, MD_GPIO_PIN_12, MD_GPIO_AF5); - md_gpio_set_function8_15(GPIOB, MD_GPIO_PIN_14, MD_GPIO_AF5); - - /* Timer configuration */ - MODIFY_REG(GP16C2T4->CHMR1, AD16C4T_CHMR1_OUTPUT_CH1MOD_MSK, - (6 << AD16C4T_CHMR1_OUTPUT_CH1MOD_POSS)); - MODIFY_REG(GP16C2T4->CHMR1, AD16C4T_CHMR1_OUTPUT_CH2MOD_MSK, - (6 << AD16C4T_CHMR1_OUTPUT_CH2MOD_POSS)); - SET_BIT(GP16C2T4->BDCFG, AD16C4T_BDCFG_GOEN_MSK); - SET_BIT(GP16C2T4->CON1, AD16C4T_CON1_CNTEN_MSK); - - pwm_dev_gp16c2t4_ctrl.chnm = 2; - pwm_dev_gp16c2t4_ctrl.timx = GP16C2T4; - pwm_dev_gp16c2t4_ctrl.cfg = pwm_ch_cfg_gp16c2t4; - /* Register PWM device */ - ret = rt_device_pwm_register(&pwm_dev_gp16c2t4, - "pwm2", &es32f0_pwm_ops, &pwm_dev_gp16c2t4_ctrl); -#endif - - return ret; -} -INIT_DEVICE_EXPORT(rt_hw_pwm_init); diff --git a/bsp/essemi/es32f0271/drivers/drv_pwm.h b/bsp/essemi/es32f0271/drivers/drv_pwm.h deleted file mode 100644 index 12c0364563..0000000000 --- a/bsp/essemi/es32f0271/drivers/drv_pwm.h +++ /dev/null @@ -1,16 +0,0 @@ -/* - * Copyright (C) 2018 Shanghai Eastsoft Microelectronics Co., Ltd. - * - * SPDX-License-Identifier: Apache-2.0 - * - * Change Logs: - * Date Author Notes - * 2019-10-23 yuzrain the first version - */ - -#ifndef DRV_PWM_H__ -#define DRV_PWM_H__ - -int rt_hw_pwm_init(void); - -#endif diff --git a/bsp/essemi/es32f0271/drivers/drv_rtc.c b/bsp/essemi/es32f0271/drivers/drv_rtc.c deleted file mode 100644 index 3e2cdd17a3..0000000000 --- a/bsp/essemi/es32f0271/drivers/drv_rtc.c +++ /dev/null @@ -1,253 +0,0 @@ -/* - * Copyright (C) 2018 Shanghai Eastsoft Microelectronics Co., Ltd. - * - * SPDX-License-Identifier: Apache-2.0 - * - * Change Logs: - * Date Author Notes - * 2019-10-23 yuzrain the first version - */ - -#include -#include -#include -#include -#include -#include "board.h" -#include "drv_rtc.h" - -#ifdef RT_USING_RTC - -/** - * @brief Time structure - */ -typedef struct -{ - uint8_t hour; /**< Hours */ - uint8_t minute; /**< Minutes */ - uint8_t second; /**< Seconds */ - uint16_t sub_sec; /**< Sub-seconds */ -} rtc_time_t; - -/** - * @brief Date structure - */ -typedef struct -{ - uint8_t week; /**< Weeks */ - uint8_t day; /**< days */ - uint8_t month; /**< months */ - uint8_t year; /**< years */ -} rtc_date_t; - -static rt_uint32_t bcd_to_dec(rt_uint32_t bcd) -{ - return ((bcd & 0xF) + ((bcd >> 4) & 0xF) * 10); -} - -static void rtc_get_time(rtc_time_t *time) -{ - rt_uint32_t tmp = RTC->TIME; - - time->second = bcd_to_dec(tmp & 0x7F); - time->minute = bcd_to_dec((tmp >> 8) & 0x7F); - time->hour = bcd_to_dec((tmp >> 16) & 0x7F); - - return; -} - -static void rtc_get_date(rtc_date_t *date) -{ - uint32_t tmp = RTC->CAL; - - date->day = bcd_to_dec(tmp & 0x3F); - date->month = bcd_to_dec((tmp >> 8) & 0x1F); - date->year = bcd_to_dec((tmp >> 16) & 0xFF); - date->week = bcd_to_dec((RTC->TIME >> 24) & 0x7); - - return; -} - -static rt_err_t es32f0_rtc_control(rt_device_t dev, int cmd, void *args) -{ - rt_err_t result = RT_EOK; - - struct tm time_temp; - struct tm *pNow; - rt_uint16_t timout = 0xFFF; - rtc_time_t *time = rt_malloc(sizeof(rtc_time_t)); - rtc_date_t *date = rt_malloc(sizeof(rtc_date_t)); - - switch (cmd) - { - case RT_DEVICE_CTRL_RTC_GET_TIME: - { - /* Wait RTC data ready then read */ - while ((--timout)&&((RTC->STAT & RTC_STAT_SYNDONE_MSK) != RTC_STAT_SYNDONE_MSK)); - if (timout == 0) - result = RT_ERROR; - /* Read */ - rtc_get_time(time); - rtc_get_date(date); - - time_temp.tm_sec = time->second; - time_temp.tm_min = time->minute; - time_temp.tm_hour = time->hour; - time_temp.tm_wday = date->week - 1; - time_temp.tm_mday = date->day; - time_temp.tm_mon = date->month - 1; - time_temp.tm_year = date->year - 1900 + 2000; - *((time_t *)args) = timegm(&time_temp); - break; - } - case RT_DEVICE_CTRL_RTC_SET_TIME: - { - rt_enter_critical(); - /* converts calendar time time into local time. */ - pNow = gmtime((const time_t *)args); - /* copy the statically located variable */ - memcpy(&time_temp, pNow, sizeof(struct tm)); - /* unlock scheduler. */ - rt_exit_critical(); - - time->hour = time_temp.tm_hour; - time->minute = time_temp.tm_min; - time->second = time_temp.tm_sec; - date->year = time_temp.tm_year + 1900 - 2000; - date->month = time_temp.tm_mon + 1; - date->day = time_temp.tm_mday; - /* Stop RTC */ - CLEAR_BIT(RTC->CON, RTC_CON_RTCEN_MSK); - WRITE_REG(RTC->TIME, ((time->hour/10)<hour%10)<minute/10)<minute%10)<second/10)<second%10)<CAL, ((date->year/10)<year%10)<month/10)<month%10)<day/10)<day%10)<CON, RTC_CON_RTCEN_MSK); - break; - } - case RT_DEVICE_CTRL_RTC_GET_ALARM: - break; - - case RT_DEVICE_CTRL_RTC_SET_ALARM: - break; - - default: - break; - } - - rt_free(time); - rt_free(date); - - return result; -} - -#ifdef RT_USING_DEVICE_OPS -const static struct rt_device_ops es32f0_rtc_ops = -{ - RT_NULL, - RT_NULL, - RT_NULL, - RT_NULL, - RT_NULL, - es32f0_rtc_control -}; -#endif - -static struct rt_device rtc_dev; -#define RTC_SOURCE_LOSC 0x1 -#define RTC_SOURCE_LRC 0x2 -int rt_hw_rtc_init(void) -{ - rt_err_t ret = RT_EOK; - rt_uint16_t timout = 0xFFFF; - rt_uint32_t rtc_clk = 32768-1; - rt_uint8_t rtc_src = RTC_SOURCE_LOSC; - - /* - * Config RTC clock - * We config the external 32.768K crystal as RTC clock source for the first - * choice. If external 32.768K crystal is not ready, we will choose LRC. - */ - /* Enable LOSC then wait it ready */ - if ((RCU->CON & RCU_CON_LOSCON_MSK) != RCU_CON_LOSCON_MSK) - SET_BIT(RCU->CON, RCU_CON_LOSCON_MSK); - - /* Wait external 32.768K crystal ready */ - while (((RCU->CON & RCU_CON_LOSCRDY_MSK) != RCU_CON_LOSCRDY_MSK)&&(--timout)); - if (timout == 0) - { - /* We use LRC if external 32.768K crystal is not ready */ - if ((RCU->CON & RCU_CON_LRCON_MSK) != RCU_CON_LRCON_MSK) - SET_BIT(RCU->CON, RCU_CON_LRCON_MSK); - /* Wait LRC ready */ - timout = 0xFF; - while (((RCU->CON & RCU_CON_LRCRDY_MSK) != RCU_CON_LRCRDY_MSK)&&(--timout)); - rtc_clk = 32000-1; - rtc_src = RTC_SOURCE_LRC; - } - - /* Open RTC clock */ - SET_BIT(RCU->AHBEN, RCU_AHBEN_RTCEN_MSK); - - /* Reset RTC */ - SET_BIT(RCU->AHBRST, RCU_AHBRST_RTCEN_MSK); - CLEAR_BIT(RCU->AHBRST, RCU_AHBRST_RTCEN_MSK); - CLEAR_BIT(RTC->CON, RTC_CON_RTCEN_MSK); - - /* Config RTC clock source */ - MODIFY_REG(RTC->CON, RTC_CON_CKSEL_MSK, rtc_src<CON, RTC_CON_PSCALE_MSK|RTC_CON_SCALE_MSK, - ((rtc_clk&0x7F)<>7)&0xFF)<TIME, (0x3<CAL, (0x1<CON, RTC_CON_RTCEN_MSK); - - rtc_dev.type = RT_Device_Class_RTC; - rtc_dev.rx_indicate = RT_NULL; - rtc_dev.tx_complete = RT_NULL; - -#ifdef RT_USING_DEVICE_OPS - rtc_dev.ops = &es32f0_rtc_ops; -#else - rtc_dev.init = RT_NULL; - rtc_dev.open = RT_NULL; - rtc_dev.close = RT_NULL; - rtc_dev.read = RT_NULL; - rtc_dev.write = RT_NULL; - rtc_dev.control = es32f0_rtc_control; -#endif - - rtc_dev.user_data = RTC; - - ret = rt_device_register(&rtc_dev, "rtc", RT_DEVICE_FLAG_RDWR); - - return ret; -} -INIT_DEVICE_EXPORT(rt_hw_rtc_init); - -#endif diff --git a/bsp/essemi/es32f0271/drivers/drv_rtc.h b/bsp/essemi/es32f0271/drivers/drv_rtc.h deleted file mode 100644 index 0fd0661026..0000000000 --- a/bsp/essemi/es32f0271/drivers/drv_rtc.h +++ /dev/null @@ -1,16 +0,0 @@ -/* - * Copyright (C) 2018 Shanghai Eastsoft Microelectronics Co., Ltd. - * - * SPDX-License-Identifier: Apache-2.0 - * - * Change Logs: - * Date Author Notes - * 2019-10-23 yuzrain the first version - */ - -#ifndef DRV_RTC_H__ -#define DRV_RTC_H__ - -int rt_hw_rtc_init(void); - -#endif diff --git a/bsp/essemi/es32f0271/drivers/drv_spi.c b/bsp/essemi/es32f0271/drivers/drv_spi.c deleted file mode 100644 index 9a7fc3ab70..0000000000 --- a/bsp/essemi/es32f0271/drivers/drv_spi.c +++ /dev/null @@ -1,439 +0,0 @@ -/* - * Copyright (C) 2018 Shanghai Eastsoft Microelectronics Co., Ltd. - * - * SPDX-License-Identifier: Apache-2.0 - * - * Change Logs: - * Date Author Notes - * 2019-10-23 yuzrain the first version - */ - -#include -#include -#include -#include -#include "board.h" -#include "drv_spi.h" -#include "md_spi.h" -#include "md_gpio.h" - -#ifdef RT_USING_SPI - -#define SPITIMEOUT 0x0FFF - -static rt_err_t __spi_send(struct rt_spi_device *device, rt_uint8_t *buf, - rt_int32_t len, rt_uint32_t tmout); -static rt_err_t __spi_recv(struct rt_spi_device *device, rt_uint8_t *buf, - rt_int32_t len, rt_uint32_t tmout); -static rt_err_t __spi_send_recv(struct rt_spi_device *device, rt_uint8_t *tbuf, - rt_uint8_t *rbuf, rt_int32_t len, rt_uint32_t tmout); - -/** - * @brief: SPI single line send. - * @param: device, pointer to the SPI device - * @param: buf, send data buffer - * @param: len, the length of buf - * @param: tmout, timeout - * @retval: rt_err_t - */ -static rt_err_t __spi_send(struct rt_spi_device *device, rt_uint8_t *buf, - rt_int32_t len, rt_uint32_t tmout) -{ - SPI_TypeDef *hspi; - rt_uint32_t rt_timout; - rt_uint8_t temp_data; - - /* Get the SPI port */ - hspi = (SPI_TypeDef *)device->bus->parent.user_data; - - /* Open SPI if it is disabled */ - if (READ_BIT(hspi->CON1, SPI_CON1_SPIEN_MSK) != SPI_CON1_SPIEN_MSK) - SET_BIT(hspi->CON1, SPI_CON1_SPIEN_MSK); - - while (len > 0) - { - /* Confirm that no data is being transmitted */ - rt_timout = tmout; - while (((hspi->STAT & SPI_STAT_TXE_MSK) == 0) && (--rt_timout)); - if (rt_timout == 0) - return RT_ETIMEOUT; - - /* Send data */ - if (device->config.data_width == 8) - { - hspi->DATA = *(rt_uint8_t *)buf; - buf++; - len--; - } - else if (device->config.data_width == 16) - { - hspi->DATA = *(rt_uint16_t *)buf; - buf += 2; - len -= 2; - } - else - return RT_EINVAL; - } - - /* At here, we have transmitted all the data. - * The next step is to clear the IT flag. - */ - for (rt_uint8_t i = 0; i < md_spi_get_stat_rxflv(hspi); i++) - temp_data = hspi->DATA; - UNUSED(temp_data); - hspi->ICR = hspi->RIF; - - return RT_EOK; -} - -/** - * @brief: SPI single line receive. - * @param: device, pointer to the SPI device - * @param: buf, receive data buffer - * @param: len, the length of buf - * @param: tmout, timeout - * @retval: rt_err_t - */ -static rt_err_t __spi_recv(struct rt_spi_device *device, rt_uint8_t *buf, - rt_int32_t len, rt_uint32_t tmout) -{ - SPI_TypeDef *hspi; - rt_uint32_t rt_timout; - - /* Get the SPI port */ - hspi = (SPI_TypeDef *)device->bus->parent.user_data; - - /* Open SPI if it is disabled */ - if (READ_BIT(hspi->CON1, SPI_CON1_SPIEN_MSK) != SPI_CON1_SPIEN_MSK) - SET_BIT(hspi->CON1, SPI_CON1_SPIEN_MSK); - - /* Handle data in __spi_send_recv() function */ - if (((device->config.mode & RT_SPI_SLAVE) == 0) - && ((device->config.mode & RT_SPI_3WIRE) == 0)) - __spi_send_recv(device, buf, buf, len, tmout); - - while (len > 0) - { - /* Waiting for data */ - rt_timout = tmout; - while (((hspi->STAT & SPI_STAT_RXTH_MSK) == 0) && (--rt_timout)); - if (rt_timout == 0) - return RT_ETIMEOUT; - - /* Send data */ - if (device->config.data_width == 8) - { - *(rt_uint8_t *)buf = hspi->DATA; - buf++; - len--; - } - else if (device->config.data_width == 16) - { - *(rt_uint16_t *)buf = hspi->DATA; - buf += 2; - len -= 2; - } - else - return RT_EINVAL; - } - - /* At here, we have transmitted all the data. - * The next step is to clear the IT flag. - */ - hspi->ICR = hspi->RIF; - - return RT_EOK; -} - -/** - * @brief: SPI two line transmission. - * @param: device, pointer to the SPI device - * @param: tbuf, send data buffer - * @param: rbuf, receive data buffer - * @param: len, the length of buf - * @param: tmout, timeout - * @retval: rt_err_t - */ -static rt_err_t __spi_send_recv(struct rt_spi_device *device, rt_uint8_t *tbuf, - rt_uint8_t *rbuf, rt_int32_t len, rt_uint32_t tmout) -{ - SPI_TypeDef *hspi; - rt_uint32_t rt_timout; - - /* Get the SPI port */ - hspi = (SPI_TypeDef *)device->bus->parent.user_data; - - /* Open SPI if it is disabled */ - if (READ_BIT(hspi->CON1, SPI_CON1_SPIEN_MSK) != SPI_CON1_SPIEN_MSK) - SET_BIT(hspi->CON1, SPI_CON1_SPIEN_MSK); - - /* return error if SPI is in 1-line mode */ - if ((device->config.mode & RT_SPI_3WIRE) == RT_SPI_3WIRE) - return RT_ERROR; - - while (len > 0) - { - /* Confirm that no data is being transmitted */ - rt_timout = tmout; - while (((hspi->STAT & SPI_STAT_TXE_MSK) == 0) && (--rt_timout)); - if (rt_timout == 0) - return RT_ETIMEOUT; - - /* Send data */ - if (device->config.data_width == 8) - { - hspi->DATA = *(rt_uint8_t *)tbuf; - tbuf++; - len--; - } - else if (device->config.data_width == 16) - { - hspi->DATA = *(rt_uint16_t *)tbuf; - tbuf += 2; - len -= 2; - } - else - return RT_EINVAL; - - /* Waiting for data */ - rt_timout = tmout; - while (((hspi->STAT & SPI_STAT_RXTH_MSK) == 0) && (--rt_timout)); - if (rt_timout == 0) - return RT_ETIMEOUT; - - /* Send data */ - if (device->config.data_width == 8) - { - *(rt_uint8_t *)rbuf = hspi->DATA; - rbuf++; - } - else if (device->config.data_width == 16) - { - *(rt_uint16_t *)rbuf = hspi->DATA; - rbuf += 2; - } - } - - /* At here, we have transmitted all the data. - * The next step is to clear the IT flag. - */ - hspi->ICR = hspi->RIF; - - return RT_EOK; -} - -rt_err_t spi_configure(struct rt_spi_device *device, - struct rt_spi_configuration *cfg) -{ - SPI_TypeDef *hspi; - hspi = (SPI_TypeDef *)device->bus->parent.user_data; - - /* Close SPI temporarily */ - md_spi_disable_con1_spien(hspi); - - /* config spi mode */ - if (cfg->mode & RT_SPI_SLAVE) - md_spi_set_con1_mstren(hspi, MD_SPI_MODE_SLAVE); - else - md_spi_set_con1_mstren(hspi, MD_SPI_MODE_MASTER); - - /* Config data mode */ - if (cfg->mode & RT_SPI_3WIRE) - md_spi_set_con1_bidimode(hspi, MD_SPI_HALF_DUPLEX); - else - md_spi_set_con1_bidimode(hspi, MD_SPI_FULL_DUPLEX); - - /* Config data width */ - if (cfg->data_width == 8) - md_spi_set_con1_flen(hspi, MD_SPI_FRAME_FORMAT_8BIT); - else if (cfg->data_width == 16) - md_spi_set_con1_flen(hspi, SPI_CON1_FLEN_MSK); - - /* Config phase */ - if (cfg->mode & RT_SPI_CPHA) - md_spi_set_con1_cpha(hspi, MD_SPI_PHASE_2EDGE); - else - md_spi_set_con1_cpha(hspi, MD_SPI_PHASE_1EDGE); - - /* Config polarity */ - if (cfg->mode & RT_SPI_CPOL) - md_spi_set_con1_cpol(hspi, MD_SPI_POLARITY_HIGH); - else - md_spi_set_con1_cpol(hspi, MD_SPI_POLARITY_LOW); - - /* Config if NSS pin is managed by software */ - md_spi_disable_con1_ssen(hspi); - - /* config spi clock */ - if (cfg->max_hz >= SystemCoreClock / 2) - { - /* pclk1 max speed 48MHz, spi master max speed 10MHz */ - if (SystemCoreClock / 2 <= 10000000) - md_spi_set_con1_baud(hspi, MD_SPI_BAUDRATEPRESCALER_DIV2); - else if (SystemCoreClock / 4 <= 10000000) - md_spi_set_con1_baud(hspi, MD_SPI_BAUDRATEPRESCALER_DIV4); - else - md_spi_set_con1_baud(hspi, MD_SPI_BAUDRATEPRESCALER_DIV8); - } - else if (cfg->max_hz >= SystemCoreClock / 4) - { - /* pclk1 max speed 48MHz, spi master max speed 10MHz */ - if (SystemCoreClock / 4 <= 10000000) - md_spi_set_con1_baud(hspi, MD_SPI_BAUDRATEPRESCALER_DIV4); - else - md_spi_set_con1_baud(hspi, MD_SPI_BAUDRATEPRESCALER_DIV8); - } - else if (cfg->max_hz >= SystemCoreClock / 8) - md_spi_set_con1_baud(hspi, MD_SPI_BAUDRATEPRESCALER_DIV8); - else if (cfg->max_hz >= SystemCoreClock / 16) - md_spi_set_con1_baud(hspi, MD_SPI_BAUDRATEPRESCALER_DIV16); - else if (cfg->max_hz >= SystemCoreClock / 32) - md_spi_set_con1_baud(hspi, MD_SPI_BAUDRATEPRESCALER_DIV32); - else if (cfg->max_hz >= SystemCoreClock / 64) - md_spi_set_con1_baud(hspi, MD_SPI_BAUDRATEPRESCALER_DIV64); - else if (cfg->max_hz >= SystemCoreClock / 128) - md_spi_set_con1_baud(hspi, MD_SPI_BAUDRATEPRESCALER_DIV128); - else - md_spi_set_con1_baud(hspi, MD_SPI_BAUDRATEPRESCALER_DIV256); - - /* Enable SPI */ - md_spi_enable_con1_spien(hspi); - - return RT_EOK; -} - -static rt_uint32_t spixfer(struct rt_spi_device *device, struct rt_spi_message *message) -{ - rt_err_t res; - rt_uint32_t *cs; - - RT_ASSERT(device != RT_NULL); - RT_ASSERT(device->bus != RT_NULL); - RT_ASSERT(device->bus->parent.user_data != RT_NULL); - RT_ASSERT(message->send_buf != RT_NULL || message->recv_buf != RT_NULL); - - cs = (rt_uint32_t *)device->parent.user_data; - - /* only send data */ - if (message->recv_buf == RT_NULL) - { - if (message->cs_take) - { - rt_pin_write(*cs, 0); - } - res = __spi_send(device, (rt_uint8_t *)message->send_buf, (rt_int32_t)message->length, SPITIMEOUT); - if (message->cs_release) - { - rt_pin_write(*cs, 1); - } - if (res != RT_EOK) - return RT_ERROR; - } - - /* only receive data */ - if (message->send_buf == RT_NULL) - { - if (message->cs_take) - { - rt_pin_write(*cs, 0); - } - res = __spi_recv(device, (rt_uint8_t *)message->recv_buf, (rt_int32_t)message->length, SPITIMEOUT); - if (message->cs_release) - { - rt_pin_write(*cs, 1); - } - if (res != RT_EOK) - return RT_ERROR; - } - - /* send & receive */ - else - { - if (message->cs_take) - { - rt_pin_write(*cs, 0); - } - res = __spi_send_recv(device, (rt_uint8_t *)message->send_buf, (rt_uint8_t *)message->recv_buf, - (rt_int32_t)message->length, SPITIMEOUT); - if (message->cs_release) - { - rt_pin_write(*cs, 1); - } - if (res != RT_EOK) - return RT_ERROR; - } - - return message->length; -} - -const struct rt_spi_ops es32f0_spi_ops = -{ - spi_configure, - spixfer, -}; - -static struct rt_spi_bus _spi_bus1, _spi_bus2; -int es32f0_spi_register_bus(SPI_TypeDef *SPIx, const char *name) -{ - struct rt_spi_bus *spi_bus; - - if (SPIx == SPI2) - { - /* Open GPIO and SPI clock */ - SET_BIT(RCU->APB1EN, RCU_APB1EN_SPI2EN_MSK); - SET_BIT(RCU->AHBEN, RCU_AHBEN_GPBEN_MSK); - - /* Config SPI2 GPIO */ - md_gpio_set_mode (GPIOB, MD_GPIO_PIN_13, MD_GPIO_MODE_FUNCTION); - md_gpio_set_mode (GPIOB, MD_GPIO_PIN_14, MD_GPIO_MODE_FUNCTION); - md_gpio_set_mode (GPIOB, MD_GPIO_PIN_15, MD_GPIO_MODE_FUNCTION); - md_gpio_set_function8_15 (GPIOB, MD_GPIO_PIN_13, MD_GPIO_AF0); - md_gpio_set_function8_15 (GPIOB, MD_GPIO_PIN_14, MD_GPIO_AF0); - md_gpio_set_function8_15 (GPIOB, MD_GPIO_PIN_15, MD_GPIO_AF0); - - /* Remember SPI bus2 */ - spi_bus = &_spi_bus2; - } - else if (SPIx == SPI1) - { - /* Open GPIO and SPI clock */ - SET_BIT(RCU->APB2EN, RCU_APB2EN_SPI1EN_MSK); - SET_BIT(RCU->AHBEN, RCU_AHBEN_GPBEN_MSK); - - /* Config SPI1 GPIO */ - md_gpio_set_mode (GPIOB, MD_GPIO_PIN_3, MD_GPIO_MODE_FUNCTION); - md_gpio_set_mode (GPIOB, MD_GPIO_PIN_4, MD_GPIO_MODE_FUNCTION); - md_gpio_set_mode (GPIOB, MD_GPIO_PIN_5, MD_GPIO_MODE_FUNCTION); - md_gpio_set_function0_7 (GPIOB, MD_GPIO_PIN_3, MD_GPIO_AF0); - md_gpio_set_function0_7 (GPIOB, MD_GPIO_PIN_4, MD_GPIO_AF0); - md_gpio_set_function0_7 (GPIOB, MD_GPIO_PIN_5, MD_GPIO_AF0); - - /* Remember SPI bus1 */ - spi_bus = &_spi_bus1; - } - else - { - return -1; - } - spi_bus->parent.user_data = SPIx; - - return rt_spi_bus_register(spi_bus, name, &es32f0_spi_ops); -} - -int rt_hw_spi_init(void) -{ - int result = 0; - -#ifdef BSP_USING_SPI2 - result = es32f0_spi_register_bus(SPI2, "spi2"); -#endif - -#ifdef BSP_USING_SPI1 - result = es32f0_spi_register_bus(SPI1, "spi1"); -#endif - - return result; -} -INIT_BOARD_EXPORT(rt_hw_spi_init); - -#endif diff --git a/bsp/essemi/es32f0271/drivers/drv_spi.h b/bsp/essemi/es32f0271/drivers/drv_spi.h deleted file mode 100644 index c7c8a13b4a..0000000000 --- a/bsp/essemi/es32f0271/drivers/drv_spi.h +++ /dev/null @@ -1,22 +0,0 @@ -/* - * Copyright (C) 2018 Shanghai Eastsoft Microelectronics Co., Ltd. - * - * SPDX-License-Identifier: Apache-2.0 - * - * Change Logs: - * Date Author Notes - * 2019-10-23 yuzrain the first version - */ - -#ifndef DRV_SPI_H__ -#define DRV_SPI_H__ - -#include -#include -#include - -///* cannot be used before completion init */ -//rt_err_t es32f0_spi_device_attach(rt_uint32_t pin, const char *bus_name, const char *device_name); -int rt_hw_spi_init(void); - -#endif diff --git a/bsp/essemi/es32f0271/drivers/drv_uart.c b/bsp/essemi/es32f0271/drivers/drv_uart.c deleted file mode 100644 index f860c2df91..0000000000 --- a/bsp/essemi/es32f0271/drivers/drv_uart.c +++ /dev/null @@ -1,296 +0,0 @@ -/* - * Copyright (C) 2018 Shanghai Eastsoft Microelectronics Co., Ltd. - * - * SPDX-License-Identifier: Apache-2.0 - * - * Change Logs: - * Date Author Notes - * 2019-10-23 yuzrain the first version - */ - -#include -#include -#include -#include "board.h" -#include "drv_uart.h" -#include "md_gpio.h" -#include "md_uart.h" - -#ifdef RT_USING_SERIAL - -/* es32 uart driver */ -struct es32_uart -{ - UART_TypeDef *huart; - IRQn_Type irq; -}; - -static rt_err_t es32f0x_configure(struct rt_serial_device *serial, struct serial_configure *cfg) -{ - struct es32_uart *uart; - RT_ASSERT(serial != RT_NULL); - RT_ASSERT(cfg != RT_NULL); - uart = (struct es32_uart *)serial->parent.user_data; - - /* Close TX/RX temporarily */ - md_uart_disable_lcon_txen(uart->huart); - md_uart_disable_lcon_rxen(uart->huart); - -#ifdef BSP_USING_UART1 - /* Open UART1 clock */ - SET_BIT(RCU->APB2EN, RCU_APB2EN_UART1EN_MSK); - - /* Config UART1 GPIO pin */ - md_gpio_set_pull (GPIOB, MD_GPIO_PIN_7, MD_GPIO_PULL_UP); - md_gpio_set_mode (GPIOB, MD_GPIO_PIN_6, MD_GPIO_MODE_FUNCTION); - md_gpio_set_mode (GPIOB, MD_GPIO_PIN_7, MD_GPIO_MODE_FUNCTION); - md_gpio_set_function0_7 (GPIOB, MD_GPIO_PIN_6, MD_GPIO_AF2); - md_gpio_set_function0_7 (GPIOB, MD_GPIO_PIN_7, MD_GPIO_AF2); -#endif /* uart2 gpio init */ - -#ifdef BSP_USING_UART2 - /* Open UART2 clock */ - SET_BIT(RCU->APB1EN, RCU_APB1EN_UART2EN_MSK); - - /* Config UART2 GPIO pin */ - md_gpio_set_pull (GPIOA, MD_GPIO_PIN_3, MD_GPIO_PULL_UP); - md_gpio_set_mode (GPIOA, MD_GPIO_PIN_2, MD_GPIO_MODE_FUNCTION); - md_gpio_set_mode (GPIOA, MD_GPIO_PIN_3, MD_GPIO_MODE_FUNCTION); - md_gpio_set_function0_7 (GPIOA, MD_GPIO_PIN_2, MD_GPIO_AF2); - md_gpio_set_function0_7 (GPIOA, MD_GPIO_PIN_3, MD_GPIO_AF2); -#endif /* uart1 gpio init */ - -#ifdef BSP_USING_UART3 - /* Open UART3 clock */ - SET_BIT(RCU->APB1EN, RCU_APB1EN_UART3EN_MSK); - - /* Config UART3 GPIO pin */ - md_gpio_set_pull (GPIOC, MD_GPIO_PIN_7, MD_GPIO_PULL_UP); - md_gpio_set_mode (GPIOC, MD_GPIO_PIN_6, MD_GPIO_MODE_FUNCTION); - md_gpio_set_mode (GPIOC, MD_GPIO_PIN_7, MD_GPIO_MODE_FUNCTION); - md_gpio_set_function0_7 (GPIOC, MD_GPIO_PIN_6, MD_GPIO_AF2); - md_gpio_set_function0_7 (GPIOC, MD_GPIO_PIN_7, MD_GPIO_AF2); -#endif /* uart3 gpio init */ - - if (cfg->bit_order == BIT_ORDER_MSB) - { - md_uart_set_lcon_msb(uart->huart, MD_UART_LCON_MSB_FIRST); - } - else - { - md_uart_set_lcon_msb(uart->huart, MD_UART_LCON_LSB_FIRST); - } - - if (cfg->invert == NRZ_INVERTED) - { - md_uart_enable_lcon_datainv(uart->huart); - } - else - { - md_uart_disable_lcon_datainv(uart->huart); - } - - /* Config buadrate */ - md_uart_set_brr(uart->huart, SystemCoreClock/cfg->baud_rate); - /* Config data width */ - md_uart_set_lcon_dls(uart->huart, 8-cfg->data_bits); - /* Config stop bits */ - md_uart_set_lcon_stop(uart->huart, cfg->stop_bits); - /* Config parity */ - if (cfg->parity > PARITY_NONE) - { - md_uart_set_lcon_ps(uart->huart, cfg->parity-1); - md_uart_enable_lcon_pe(uart->huart); - } - else - md_uart_disable_lcon_pe(uart->huart); - - /* enable rx int */ - md_uart_set_fcon_rxth(uart->huart, MD_UART_FCON_RXTH_1); - md_uart_enable_ier_rfth(uart->huart); - md_uart_enable_lcon_txen(uart->huart); - md_uart_enable_lcon_rxen(uart->huart); - - return RT_EOK; -} - -static rt_err_t es32f0x_control(struct rt_serial_device *serial, int cmd, void *arg) -{ - struct es32_uart *uart; - RT_ASSERT(serial != RT_NULL); - - uart = (struct es32_uart *)serial->parent.user_data; - switch (cmd) - { - case RT_DEVICE_CTRL_CLR_INT: - /* disable rx irq */ - NVIC_DisableIRQ(uart->irq); - /* disable interrupt */ - md_uart_disable_idr_rfth(uart->huart); - break; - - case RT_DEVICE_CTRL_SET_INT: - /* enable rx irq */ - NVIC_EnableIRQ(uart->irq); - /* enable interrupt */ - md_uart_enable_ier_rfth(uart->huart); - break; - } - - return RT_EOK; -} - -static int es32f0x_putc(struct rt_serial_device *serial, char c) -{ - struct es32_uart *uart; - RT_ASSERT(serial != RT_NULL); - uart = (struct es32_uart *)serial->parent.user_data; - - while (uart->huart->STAT & UART_STAT_TSBUSY_MSK); - WRITE_REG(uart->huart->TXBUF, c); - - return 1; -} - -static int es32f0x_getc(struct rt_serial_device *serial) -{ - int ch = -1; - struct es32_uart *uart; - - RT_ASSERT(serial != RT_NULL); - uart = (struct es32_uart *)serial->parent.user_data; - - if (uart->huart->STAT & UART_STAT_RFTH_MSK) - { - ch = (uint8_t)(uart->huart->RXBUF & 0xFF); - } - - return ch; -} - -static const struct rt_uart_ops es32f0x_uart_ops = -{ - es32f0x_configure, - es32f0x_control, - es32f0x_putc, - es32f0x_getc, -}; - -#ifdef BSP_USING_UART1 -/* UART1 device driver structure */ -struct es32_uart uart1 = -{ - UART1, - UART1_IRQn -}; - -struct rt_serial_device serial1; - -void UART1_IRQHandler(void) -{ - /* enter interrupt */ - rt_interrupt_enter(); - - if (md_uart_is_active_flag_rif_rfth(UART1) == 1) - { - rt_hw_serial_isr(&serial1, RT_SERIAL_EVENT_RX_IND); - md_uart_clear_flag_rfth(UART1); - } - /* leave interrupt */ - rt_interrupt_leave(); -} -#endif /* BSP_USING_UART1 */ - -#ifdef BSP_USING_UART2 -/* UART2 device driver structure */ -struct es32_uart uart2 = -{ - UART2, - UART2_IRQn -}; - -struct rt_serial_device serial2; - -void UART2_IRQHandler(void) -{ - /* enter interrupt */ - rt_interrupt_enter(); - - if (md_uart_is_active_flag_rif_rfth(UART2) == 1) - { - rt_hw_serial_isr(&serial2, RT_SERIAL_EVENT_RX_IND); - md_uart_clear_flag_rfth(UART2); - } - /* leave interrupt */ - rt_interrupt_leave(); -} -#endif /* BSP_USING_UART2 */ - -#ifdef BSP_USING_UART3 -/* UART3 device driver structure */ -struct es32_uart uart3 = -{ - UART3, - UART3_IRQn -}; - -struct rt_serial_device serial3; - -void UART3_AES_IRQHandler(void) -{ - /* enter interrupt */ - rt_interrupt_enter(); - - if (md_uart_is_active_flag_rif_rfth(UART3) == 1) - { - rt_hw_serial_isr(&serial3, RT_SERIAL_EVENT_RX_IND); - md_uart_clear_flag_rfth(UART3); - } - /* leave interrupt */ - rt_interrupt_leave(); -} -#endif /* BSP_USING_UART3 */ - -int rt_hw_uart_init(void) -{ - struct es32_uart *uart; - struct serial_configure config = RT_SERIAL_CONFIG_DEFAULT; - -#ifdef BSP_USING_UART1 - uart = &uart1; - serial1.ops = &es32f0x_uart_ops; - serial1.config = config; - - /* register UART1 device */ - rt_hw_serial_register(&serial1, "uart1", - RT_DEVICE_FLAG_RDWR | RT_DEVICE_FLAG_INT_RX, - uart); -#endif /* BSP_USING_UART1 */ - -#ifdef BSP_USING_UART2 - uart = &uart2; - serial2.ops = &es32f0x_uart_ops; - serial2.config = config; - - /* register UART2 device */ - rt_hw_serial_register(&serial2, "uart2", - RT_DEVICE_FLAG_RDWR | RT_DEVICE_FLAG_INT_RX, - uart); -#endif /* BSP_USING_UART2 */ - -#ifdef BSP_USING_UART3 - uart = &uart3; - serial3.ops = &es32f0x_uart_ops; - serial3.config = config; - - /* register UART3 device */ - rt_hw_serial_register(&serial3, "uart3", - RT_DEVICE_FLAG_RDWR | RT_DEVICE_FLAG_INT_RX, - uart); -#endif /* BSP_USING_UART3 */ - - return 0; -} -INIT_BOARD_EXPORT(rt_hw_uart_init); - -#endif diff --git a/bsp/essemi/es32f0271/drivers/drv_uart.h b/bsp/essemi/es32f0271/drivers/drv_uart.h deleted file mode 100644 index 7d3755d0a6..0000000000 --- a/bsp/essemi/es32f0271/drivers/drv_uart.h +++ /dev/null @@ -1,16 +0,0 @@ -/* - * Copyright (C) 2018 Shanghai Eastsoft Microelectronics Co., Ltd. - * - * SPDX-License-Identifier: Apache-2.0 - * - * Change Logs: - * Date Author Notes - * 2019-10-23 yuzrain the first version - */ - -#ifndef DRV_UART_H__ -#define DRV_UART_H__ - -int rt_hw_uart_init(void); - -#endif diff --git a/bsp/essemi/es32f0271/drivers/linker_scripts/link.sct b/bsp/essemi/es32f0271/drivers/linker_scripts/link.sct deleted file mode 100644 index 4ee8d1e3fc..0000000000 --- a/bsp/essemi/es32f0271/drivers/linker_scripts/link.sct +++ /dev/null @@ -1,14 +0,0 @@ -; ************************************************************* -; *** Scatter-Loading Description File generated by uVision *** -; ************************************************************* - -LR_IROM1 0x00000000 0x10000 { ; load region size_region - ER_IROM1 0x00000000 0x10000 { ; load address = execution address - *.o (RESET, +First) - *(InRoot$$Sections) - .ANY (+RO) - } - RW_IRAM1 0x20000000 0x2000{ ; RW data - .ANY (+RW +ZI) - } -} diff --git a/bsp/essemi/es32f0271/project.uvoptx b/bsp/essemi/es32f0271/project.uvoptx deleted file mode 100644 index bd379df962..0000000000 --- a/bsp/essemi/es32f0271/project.uvoptx +++ /dev/null @@ -1,797 +0,0 @@ - - - - 1.0 - -
### uVision Project, (C) Keil Software
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### uVision Project, (C) Keil Software
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- - - diff --git a/bsp/essemi/es32f0271/rtconfig.h b/bsp/essemi/es32f0271/rtconfig.h deleted file mode 100644 index 4a0cf3306a..0000000000 --- a/bsp/essemi/es32f0271/rtconfig.h +++ /dev/null @@ -1,183 +0,0 @@ -#ifndef RT_CONFIG_H__ -#define RT_CONFIG_H__ - -/* Automatically generated file; DO NOT EDIT. */ -/* RT-Thread Configuration */ - -/* RT-Thread Kernel */ - -#define RT_NAME_MAX 8 -#define RT_ALIGN_SIZE 4 -#define RT_THREAD_PRIORITY_32 -#define RT_THREAD_PRIORITY_MAX 32 -#define RT_TICK_PER_SECOND 100 -#define RT_USING_OVERFLOW_CHECK -#define RT_USING_HOOK -#define RT_USING_IDLE_HOOK -#define RT_IDLE_HOOK_LIST_SIZE 4 -#define IDLE_THREAD_STACK_SIZE 256 -#define RT_DEBUG -#define RT_DEBUG_COLOR - -/* Inter-Thread communication */ - -#define RT_USING_SEMAPHORE -#define RT_USING_MUTEX -#define RT_USING_EVENT -#define RT_USING_MAILBOX -#define RT_USING_MESSAGEQUEUE - -/* Memory Management */ - -#define RT_USING_MEMPOOL -#define RT_USING_SMALL_MEM -#define RT_USING_HEAP - -/* Kernel Device Object */ - -#define RT_USING_DEVICE -#define RT_USING_CONSOLE -#define RT_CONSOLEBUF_SIZE 128 -#define RT_CONSOLE_DEVICE_NAME "uart1" -#define RT_VER_NUM 0x40002 - -/* RT-Thread Components */ - -#define RT_USING_COMPONENTS_INIT -#define RT_USING_USER_MAIN -#define RT_MAIN_THREAD_STACK_SIZE 256 -#define RT_MAIN_THREAD_PRIORITY 10 - -/* C++ features */ - - -/* Command shell */ - -#define RT_USING_FINSH -#define FINSH_THREAD_NAME "tshell" -#define FINSH_USING_HISTORY -#define FINSH_HISTORY_LINES 5 -#define FINSH_USING_SYMTAB -#define FINSH_USING_DESCRIPTION -#define FINSH_THREAD_PRIORITY 20 -#define FINSH_THREAD_STACK_SIZE 2048 -#define FINSH_CMD_SIZE 80 -#define FINSH_USING_MSH -#define FINSH_USING_MSH_DEFAULT -#define FINSH_USING_MSH_ONLY -#define FINSH_ARG_MAX 10 - -/* Device virtual file system */ - - -/* Device Drivers */ - -#define RT_USING_DEVICE_IPC -#define RT_PIPE_BUFSZ 512 -#define RT_USING_SERIAL -#define RT_SERIAL_RB_BUFSZ 64 -#define RT_USING_PIN - -/* Using USB */ - - -/* POSIX layer and C standard library */ - - -/* Network */ - -/* Socket abstraction layer */ - - -/* Network interface device */ - - -/* light weight TCP/IP stack */ - - -/* AT commands */ - - -/* VBUS(Virtual Software BUS) */ - - -/* Utilities */ - - -/* RT-Thread online packages */ - -/* IoT - internet of things */ - - -/* Wi-Fi */ - -/* Marvell WiFi */ - - -/* Wiced WiFi */ - - -/* IoT Cloud */ - - -/* security packages */ - - -/* language packages */ - - -/* multimedia packages */ - - -/* tools packages */ - - -/* system packages */ - - -/* peripheral libraries and drivers */ - - -/* miscellaneous packages */ - - -/* samples: kernel and components samples */ - -#define SOC_ES32F0271LT - -/* Hardware Drivers Config */ - -/* On-chip Peripheral Drivers */ - -/* PIN Drivers */ - -#define BSP_USING_GPIO - -/* UART Drivers */ - -#define BSP_USING_UART1 - -/* SPI Drivers */ - - -/* I2C Drivers */ - - -/* HWtimer Drivers */ - - -/* PWM Drivers */ - - -/* RTC Drivers */ - - -/* ADC Drivers */ - - -/* Onboard Peripheral Drivers */ - -/* Offboard Peripheral Drivers */ - - -#endif diff --git a/bsp/essemi/es32f0271/rtconfig.py b/bsp/essemi/es32f0271/rtconfig.py deleted file mode 100644 index eb371bf3a7..0000000000 --- a/bsp/essemi/es32f0271/rtconfig.py +++ /dev/null @@ -1,135 +0,0 @@ -import os -import sys - -# toolchains options -CROSS_TOOL = 'keil' - -if os.getenv('RTT_CC'): - CROSS_TOOL = os.getenv('RTT_CC') - -# device options -ARCH = 'arm' -CPU = 'cortex-m0' - -# cross_tool provides the cross compiler -# EXEC_PATH is the compiler execute path, for example, CodeSourcery, Keil MDK, IAR -if CROSS_TOOL == 'gcc': # not support gcc yet - PLATFORM = 'gcc' - EXEC_PATH = 'C:/GCC' - -elif CROSS_TOOL == 'keil': - PLATFORM = 'armcc' - EXEC_PATH = 'C:/Keil' - -elif CROSS_TOOL == 'iar': # not support iar yet - PLATFORM = 'iar' - EXEC_PATH = 'C:/IAR' - -if os.getenv('RTT_EXEC_PATH'): - EXEC_PATH = os.getenv('RTT_EXEC_PATH') - -BUILD = 'debug' -#BUILD = 'release' - -if PLATFORM == 'gcc': - # toolchains - PREFIX = 'arm-none-eabi-' - CC = PREFIX + 'gcc' - CXX = PREFIX + 'g++' - AS = PREFIX + 'gcc' - AR = PREFIX + 'ar' - LINK = PREFIX + 'gcc' - TARGET_EXT = 'elf' - SIZE = PREFIX + 'size' - OBJDUMP = PREFIX + 'objdump' - OBJCPY = PREFIX + 'objcopy' - DEVICE = ' -mcpu=' + CPU + ' -mthumb -ffunction-sections -fdata-sections' - CFLAGS = DEVICE - AFLAGS = ' -c' + DEVICE + ' -x assembler-with-cpp -Wa,-mimplicit-it=thumb' - LFLAGS = DEVICE + ' -Wl,--gc-sections,-Map=rtthread.map,-cref,-u,Reset_Handler -T drivers/linker_scripts/link.lds' - - CPATH = '' - LPATH = '' - - if BUILD == 'debug': - CFLAGS += ' -O0 -gdwarf-2 -g' - AFLAGS += ' -gdwarf-2' - else: - CFLAGS += ' -O2' - - POST_ACTION = OBJCPY + ' -O binary $TARGET rtthread.bin\n' + OBJCPY + ' -O ihex $TARGET rtthread.hex\n' + SIZE + ' $TARGET \n' -elif PLATFORM == 'armcc': - # toolchains - CC = 'armcc' - AS = 'armasm' - AR = 'armar' - LINK = 'armlink' - TARGET_EXT = 'axf' - - DEVICE = ' --device DARMSTM' - CFLAGS = '-c ' + DEVICE + ' --apcs=interwork --c99' - AFLAGS = DEVICE + ' --apcs=interwork ' - LFLAGS = DEVICE + ' --scatter "drivers/linker_scripts/link.sct" --info sizes --info totals --info unused --info veneers --list rtthread.map --strict' - - CFLAGS += ' -I' + EXEC_PATH + '/ARM/ARMCC/include' - LFLAGS += ' --libpath ' + EXEC_PATH + '/ARM/ARMCC/lib' - - CFLAGS += ' -D__MICROLIB ' - AFLAGS += ' --pd "__MICROLIB SETA 1" ' - LFLAGS += ' --library_type=microlib ' - EXEC_PATH += '/ARM/ARMCC/bin' - - if BUILD == 'debug': - CFLAGS += ' -g -O0' - AFLAGS += ' -g' - else: - CFLAGS += ' -O2' - - POST_ACTION = 'fromelf --bin $TARGET --output rtthread.bin \nfromelf -z $TARGET' - -elif PLATFORM == 'iar': - # toolchains - CC = 'iccarm' - AS = 'iasmarm' - AR = 'iarchive' - LINK = 'ilinkarm' - TARGET_EXT = 'out' - - DEVICE = '-Dewarm' - - CFLAGS = DEVICE - CFLAGS += ' --diag_suppress Pa050' - CFLAGS += ' --no_cse' - CFLAGS += ' --no_unroll' - CFLAGS += ' --no_inline' - CFLAGS += ' --no_code_motion' - CFLAGS += ' --no_tbaa' - CFLAGS += ' --no_clustering' - CFLAGS += ' --no_scheduling' - CFLAGS += ' --endian=little' - CFLAGS += ' --cpu=Cortex-M0' - CFLAGS += ' -e' - CFLAGS += ' --fpu=None' - CFLAGS += ' --dlib_config "' + EXEC_PATH + '/arm/INC/c/DLib_Config_Normal.h"' - CFLAGS += ' --silent' - - AFLAGS = DEVICE - AFLAGS += ' -s+' - AFLAGS += ' -w+' - AFLAGS += ' -r' - AFLAGS += ' --cpu Cortex-M0' - AFLAGS += ' --fpu None' - AFLAGS += ' -S' - - LFLAGS = ' --config "drivers\linker_scripts\link.icf"' - LFLAGS += ' --redirect _Printf=_PrintfTiny' - LFLAGS += ' --redirect _Scanf=_ScanfSmall' - if BUILD == 'debug': - CFLAGS += ' --debug' - CFLAGS += ' -On' - else: - CFLAGS += ' -Oh' - - LFLAGS += ' --entry __iar_program_start' - EXEC_PATH = EXEC_PATH + '/arm/bin/' - POST_ACTION = '' diff --git a/bsp/essemi/es32f0271/template.uvoptx b/bsp/essemi/es32f0271/template.uvoptx deleted file mode 100644 index bb8cce6ff2..0000000000 --- a/bsp/essemi/es32f0271/template.uvoptx +++ /dev/null @@ -1,177 +0,0 @@ - - - - 1.0 - -
### uVision Project, (C) Keil Software
- - - *.c - *.s*; *.src; *.a* - *.obj; *.o - *.lib - *.txt; *.h; *.inc - *.plm - *.cpp - 0 - - - - 0 - 0 - - - - rt-thread - 0x4 - ARM-ADS - - 12000000 - - 1 - 1 - 0 - 1 - 0 - - - 1 - 65535 - 0 - 0 - 0 - - - 79 - 66 - 8 - .\build\keil\ - - - 1 - 1 - 1 - 0 - 1 - 1 - 0 - 1 - 0 - 0 - 0 - 0 - - - 1 - 1 - 1 - 1 - 1 - 1 - 1 - 0 - 0 - - - 0 - 0 - 1 - - 255 - - 0 - 1 - 1 - 1 - 1 - 1 - 1 - 1 - 1 - 1 - 0 - 1 - 1 - 1 - 0 - 1 - 1 - 1 - 1 - 0 - 0 - 1 - 0 - 0 - 3 - - - - - - - - - - - BIN\CMSIS_AGDI.dll - - - - 0 - UL2CM3 - UL2CM3(-S0 -C0 -P0 ) -FN1 -FC1000 -FD20000000 -FF0ES32F0271 -FL010000 -FS00 -FP0($$Device:ES32F0271LT$Flash\ES32F0271.FLM) - - - 0 - CMSIS_AGDI - -X"" -O206 -S0 -C0 -P00 -TO18 -TC10000000 -TP20 -TDS8007 -TDT0 -TDC1F -TIEFFFFFFFF -TIP8 -FO7 -FD20000000 -FC1000 -FN1 -FF0ES32F0271.FLM -FS00 -FL010000 -FP0($$Device:ES32F0271LT$Flash\ES32F0271.FLM) - - - - - 0 - - - 0 - 0 - 0 - 0 - 0 - 0 - 0 - 0 - 0 - 0 - 0 - 0 - 0 - 0 - 0 - 0 - 0 - 0 - 0 - 0 - 0 - 0 - 0 - 0 - - - - 0 - 0 - 0 - - - - - - - - - - - - diff --git a/bsp/essemi/es32f0271/template.uvprojx b/bsp/essemi/es32f0271/template.uvprojx deleted file mode 100644 index ce19e112f5..0000000000 --- a/bsp/essemi/es32f0271/template.uvprojx +++ /dev/null @@ -1,389 +0,0 @@ - - - - 2.1 - -
### uVision Project, (C) Keil Software
- - - - rt-thread - 0x4 - ARM-ADS - 0 - - - ES32F0271LT - Eastsoft - Eastsoft.ES32_DFP.1.0.4 - http://www.essemi.com - IRAM(0x20000000,0x00002000) IROM(0x00000000,0x00010000) CPUTYPE("Cortex-M0") CLOCK(12000000) ELITTLE - - - UL2CM3(-S0 -C0 -P0 -FD20000000 -FC1000 -FN1 -FF0ES32F0271 -FS00 -FL010000 -FP0($$Device:ES32F0271LT$Flash\ES32F0271.FLM)) - 0 - $$Device:ES32F0271LT$Device\Include\es32f027x.h - - - - - - - - - - $$Device:ES32F0271LT$SVD\es32f027x.svd - 0 - 0 - - - - - - - 0 - 0 - 0 - 0 - 1 - - .\build\keil\ - rtthread - 1 - 0 - 0 - 1 - 1 - .\build\keil\ - 1 - 0 - 0 - - 0 - 0 - - - 0 - 0 - 0 - 0 - - - 0 - 0 - - - 0 - 0 - 0 - 0 - - - 1 - 0 - fromelf --bin !L --output rtthread.bin - - 0 - 0 - 0 - 0 - - 0 - - - - 0 - 0 - 0 - 0 - 0 - 1 - 0 - 0 - 0 - 0 - 3 - - - 1 - - - SARMCM3.DLL - -MPU - DARMCM1.DLL - -pCM0 - SARMCM3.DLL - -MPU - TARMCM1.DLL - -pCM0 - - - - 1 - 0 - 0 - 0 - 16 - - - - - 1 - 0 - 0 - 1 - 1 - 4096 - - 1 - BIN\UL2CM3.DLL - "" () - - - - - 0 - - - - 0 - 1 - 1 - 1 - 1 - 1 - 1 - 1 - 0 - 1 - 1 - 0 - 1 - 1 - 0 - 0 - 1 - 1 - 1 - 1 - 1 - 1 - 1 - 1 - 1 - 0 - 0 - "Cortex-M0" - - 0 - 0 - 0 - 1 - 1 - 0 - 0 - 0 - 0 - 0 - 0 - 8 - 0 - 0 - 0 - 0 - 3 - 3 - 0 - 0 - 0 - 0 - 0 - 0 - 0 - 0 - 0 - 0 - 1 - 0 - 0 - 0 - 0 - 1 - 0 - - - 0 - 0x0 - 0x0 - - - 0 - 0x0 - 0x0 - - - 0 - 0x0 - 0x0 - - - 0 - 0x0 - 0x0 - - - 0 - 0x0 - 0x0 - - - 0 - 0x0 - 0x0 - - - 0 - 0x20000000 - 0x2000 - - - 1 - 0x0 - 0x10000 - - - 0 - 0x0 - 0x0 - - - 1 - 0x0 - 0x0 - - - 1 - 0x0 - 0x0 - - - 1 - 0x0 - 0x0 - - - 1 - 0x0 - 0x10000 - - - 1 - 0x0 - 0x0 - - - 0 - 0x0 - 0x0 - - - 0 - 0x0 - 0x0 - - - 0 - 0x0 - 0x0 - - - 0 - 0x20000000 - 0x2000 - - - 0 - 0x0 - 0x0 - - - - - - 1 - 3 - 0 - 0 - 1 - 0 - 0 - 0 - 0 - 0 - 0 - 0 - 0 - 1 - 0 - 0 - 1 - 1 - 1 - 1 - 0 - 0 - 0 - - - - - - - - - 1 - 0 - 0 - 0 - 0 - 0 - 0 - 0 - 0 - 0 - - - - - - - - - 1 - 0 - 0 - 0 - 1 - 0 - 0x08000000 - 0x20000000 - - - - - - - - - - - - - - - - - - - - -- cgit v1.3.1 From 7d5a97e3ea81e5e53e972eff4900cdd3dcb90dce Mon Sep 17 00:00:00 2001 From: liuhy Date: Fri, 10 Sep 2021 18:04:14 +0800 Subject: delete essemi bsp es32f0334 (libraries) --- .../Device/EastSoft/ES32F033x/Include/es32f033x.h | 5882 ---------------- .../ES32F033x/Startup/iar/startup_es32f033x.s | 266 - .../ES32F033x/Startup/keil/startup_es32f033x.s | 335 - .../EastSoft/ES32F033x/System/system_es32f033x.c | 28 - .../libraries/CMSIS/Include/arm_common_tables.h | 136 - .../libraries/CMSIS/Include/arm_const_structs.h | 79 - .../es32f0334/libraries/CMSIS/Include/arm_math.h | 7154 -------------------- .../libraries/CMSIS/Include/cmsis_armcc.h | 734 -- .../libraries/CMSIS/Include/cmsis_armcc_V6.h | 1800 ----- .../es32f0334/libraries/CMSIS/Include/cmsis_gcc.h | 1373 ---- .../es32f0334/libraries/CMSIS/Include/core_cm0.h | 798 --- .../libraries/CMSIS/Include/core_cm0plus.h | 914 --- .../libraries/CMSIS/Include/core_cmFunc.h | 87 - .../libraries/CMSIS/Include/core_cmInstr.h | 87 - .../libraries/CMSIS/Include/core_cmSimd.h | 96 - .../es32f0334/libraries/CMSIS/Include/core_sc000.h | 926 --- .../es32f0334/libraries/CMSIS/Include/core_sc300.h | 1745 ----- .../EASTSOFT_ES32F033x_ALD.chm | Bin 6539714 -> 0 bytes .../Include/ald_acmp.h | 338 - .../Include/ald_adc.h | 546 -- .../Include/ald_bkpc.h | 171 - .../Include/ald_calc.h | 57 - .../Include/ald_cmu.h | 651 -- .../Include/ald_conf.h | 55 - .../Include/ald_crc.h | 196 - .../Include/ald_crypt.h | 255 - .../Include/ald_dbgc.h | 156 - .../Include/ald_dma.h | 421 -- .../Include/ald_flash.h | 127 - .../Include/ald_gpio.h | 277 - .../Include/ald_i2c.h | 513 -- .../Include/ald_iap.h | 80 - .../Include/ald_lcd.h | 496 -- .../Include/ald_lptim.h | 370 - .../Include/ald_lpuart.h | 468 -- .../Include/ald_pis.h | 637 -- .../Include/ald_pmu.h | 251 - .../Include/ald_rmu.h | 288 - .../Include/ald_rtc.h | 669 -- .../Include/ald_smartcard.h | 274 - .../Include/ald_spi.h | 387 -- .../Include/ald_syscfg.h | 105 - .../Include/ald_timer.h | 1154 ---- .../Include/ald_trng.h | 203 - .../Include/ald_tsense.h | 199 - .../Include/ald_uart.h | 461 -- .../Include/ald_usart.h | 560 -- .../Include/ald_wdt.h | 116 - .../ES32F033x_ALD_StdPeriph_Driver/Include/type.h | 122 - .../ES32F033x_ALD_StdPeriph_Driver/Include/utils.h | 166 - .../Source/ald_acmp.c | 351 - .../Source/ald_adc.c | 1083 --- .../Source/ald_bkpc.c | 158 - .../Source/ald_calc.c | 121 - .../Source/ald_cmu.c | 1093 --- .../Source/ald_crc.c | 514 -- .../Source/ald_crypt.c | 996 --- .../Source/ald_dma.c | 999 --- .../Source/ald_flash.c | 208 - .../Source/ald_flash_ext.c | 330 - .../Source/ald_gpio.c | 623 -- .../Source/ald_i2c.c | 3109 --------- .../Source/ald_iap.c | 149 - .../Source/ald_lcd.c | 345 - .../Source/ald_lptim.c | 801 --- .../Source/ald_lpuart.c | 1192 ---- .../Source/ald_pis.c | 316 - .../Source/ald_pmu.c | 256 - .../Source/ald_rmu.c | 146 - .../Source/ald_rtc.c | 1192 ---- .../Source/ald_smartcard.c | 925 --- .../Source/ald_spi.c | 1789 ----- .../Source/ald_timer.c | 3675 ---------- .../Source/ald_trng.c | 309 - .../Source/ald_tsense.c | 253 - .../Source/ald_uart.c | 1178 ---- .../Source/ald_usart.c | 2326 ------- .../Source/ald_wdt.c | 214 - .../ES32F033x_ALD_StdPeriph_Driver/Source/utils.c | 440 -- bsp/essemi/es32f0334/libraries/SConscript | 27 - 80 files changed, 58327 deletions(-) delete mode 100644 bsp/essemi/es32f0334/libraries/CMSIS/Device/EastSoft/ES32F033x/Include/es32f033x.h delete mode 100644 bsp/essemi/es32f0334/libraries/CMSIS/Device/EastSoft/ES32F033x/Startup/iar/startup_es32f033x.s delete mode 100644 bsp/essemi/es32f0334/libraries/CMSIS/Device/EastSoft/ES32F033x/Startup/keil/startup_es32f033x.s delete mode 100644 bsp/essemi/es32f0334/libraries/CMSIS/Device/EastSoft/ES32F033x/System/system_es32f033x.c delete mode 100644 bsp/essemi/es32f0334/libraries/CMSIS/Include/arm_common_tables.h delete mode 100644 bsp/essemi/es32f0334/libraries/CMSIS/Include/arm_const_structs.h delete mode 100644 bsp/essemi/es32f0334/libraries/CMSIS/Include/arm_math.h delete mode 100644 bsp/essemi/es32f0334/libraries/CMSIS/Include/cmsis_armcc.h delete mode 100644 bsp/essemi/es32f0334/libraries/CMSIS/Include/cmsis_armcc_V6.h delete mode 100644 bsp/essemi/es32f0334/libraries/CMSIS/Include/cmsis_gcc.h delete mode 100644 bsp/essemi/es32f0334/libraries/CMSIS/Include/core_cm0.h delete mode 100644 bsp/essemi/es32f0334/libraries/CMSIS/Include/core_cm0plus.h delete mode 100644 bsp/essemi/es32f0334/libraries/CMSIS/Include/core_cmFunc.h delete mode 100644 bsp/essemi/es32f0334/libraries/CMSIS/Include/core_cmInstr.h delete mode 100644 bsp/essemi/es32f0334/libraries/CMSIS/Include/core_cmSimd.h delete mode 100644 bsp/essemi/es32f0334/libraries/CMSIS/Include/core_sc000.h delete mode 100644 bsp/essemi/es32f0334/libraries/CMSIS/Include/core_sc300.h delete mode 100644 bsp/essemi/es32f0334/libraries/ES32F033x_ALD_StdPeriph_Driver/EASTSOFT_ES32F033x_ALD.chm delete mode 100644 bsp/essemi/es32f0334/libraries/ES32F033x_ALD_StdPeriph_Driver/Include/ald_acmp.h delete mode 100644 bsp/essemi/es32f0334/libraries/ES32F033x_ALD_StdPeriph_Driver/Include/ald_adc.h delete mode 100644 bsp/essemi/es32f0334/libraries/ES32F033x_ALD_StdPeriph_Driver/Include/ald_bkpc.h delete mode 100644 bsp/essemi/es32f0334/libraries/ES32F033x_ALD_StdPeriph_Driver/Include/ald_calc.h delete mode 100644 bsp/essemi/es32f0334/libraries/ES32F033x_ALD_StdPeriph_Driver/Include/ald_cmu.h delete mode 100644 bsp/essemi/es32f0334/libraries/ES32F033x_ALD_StdPeriph_Driver/Include/ald_conf.h delete mode 100644 bsp/essemi/es32f0334/libraries/ES32F033x_ALD_StdPeriph_Driver/Include/ald_crc.h delete mode 100644 bsp/essemi/es32f0334/libraries/ES32F033x_ALD_StdPeriph_Driver/Include/ald_crypt.h delete mode 100644 bsp/essemi/es32f0334/libraries/ES32F033x_ALD_StdPeriph_Driver/Include/ald_dbgc.h delete mode 100644 bsp/essemi/es32f0334/libraries/ES32F033x_ALD_StdPeriph_Driver/Include/ald_dma.h delete mode 100644 bsp/essemi/es32f0334/libraries/ES32F033x_ALD_StdPeriph_Driver/Include/ald_flash.h delete mode 100644 bsp/essemi/es32f0334/libraries/ES32F033x_ALD_StdPeriph_Driver/Include/ald_gpio.h delete mode 100644 bsp/essemi/es32f0334/libraries/ES32F033x_ALD_StdPeriph_Driver/Include/ald_i2c.h delete mode 100644 bsp/essemi/es32f0334/libraries/ES32F033x_ALD_StdPeriph_Driver/Include/ald_iap.h delete mode 100644 bsp/essemi/es32f0334/libraries/ES32F033x_ALD_StdPeriph_Driver/Include/ald_lcd.h delete mode 100644 bsp/essemi/es32f0334/libraries/ES32F033x_ALD_StdPeriph_Driver/Include/ald_lptim.h delete mode 100644 bsp/essemi/es32f0334/libraries/ES32F033x_ALD_StdPeriph_Driver/Include/ald_lpuart.h delete mode 100644 bsp/essemi/es32f0334/libraries/ES32F033x_ALD_StdPeriph_Driver/Include/ald_pis.h delete mode 100644 bsp/essemi/es32f0334/libraries/ES32F033x_ALD_StdPeriph_Driver/Include/ald_pmu.h delete mode 100644 bsp/essemi/es32f0334/libraries/ES32F033x_ALD_StdPeriph_Driver/Include/ald_rmu.h delete mode 100644 bsp/essemi/es32f0334/libraries/ES32F033x_ALD_StdPeriph_Driver/Include/ald_rtc.h delete mode 100644 bsp/essemi/es32f0334/libraries/ES32F033x_ALD_StdPeriph_Driver/Include/ald_smartcard.h delete mode 100644 bsp/essemi/es32f0334/libraries/ES32F033x_ALD_StdPeriph_Driver/Include/ald_spi.h delete mode 100644 bsp/essemi/es32f0334/libraries/ES32F033x_ALD_StdPeriph_Driver/Include/ald_syscfg.h delete mode 100644 bsp/essemi/es32f0334/libraries/ES32F033x_ALD_StdPeriph_Driver/Include/ald_timer.h delete mode 100644 bsp/essemi/es32f0334/libraries/ES32F033x_ALD_StdPeriph_Driver/Include/ald_trng.h delete mode 100644 bsp/essemi/es32f0334/libraries/ES32F033x_ALD_StdPeriph_Driver/Include/ald_tsense.h delete mode 100644 bsp/essemi/es32f0334/libraries/ES32F033x_ALD_StdPeriph_Driver/Include/ald_uart.h delete mode 100644 bsp/essemi/es32f0334/libraries/ES32F033x_ALD_StdPeriph_Driver/Include/ald_usart.h delete mode 100644 bsp/essemi/es32f0334/libraries/ES32F033x_ALD_StdPeriph_Driver/Include/ald_wdt.h delete mode 100644 bsp/essemi/es32f0334/libraries/ES32F033x_ALD_StdPeriph_Driver/Include/type.h delete mode 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bsp/essemi/es32f0334/libraries/ES32F033x_ALD_StdPeriph_Driver/Source/ald_flash_ext.c delete mode 100644 bsp/essemi/es32f0334/libraries/ES32F033x_ALD_StdPeriph_Driver/Source/ald_gpio.c delete mode 100644 bsp/essemi/es32f0334/libraries/ES32F033x_ALD_StdPeriph_Driver/Source/ald_i2c.c delete mode 100644 bsp/essemi/es32f0334/libraries/ES32F033x_ALD_StdPeriph_Driver/Source/ald_iap.c delete mode 100644 bsp/essemi/es32f0334/libraries/ES32F033x_ALD_StdPeriph_Driver/Source/ald_lcd.c delete mode 100644 bsp/essemi/es32f0334/libraries/ES32F033x_ALD_StdPeriph_Driver/Source/ald_lptim.c delete mode 100644 bsp/essemi/es32f0334/libraries/ES32F033x_ALD_StdPeriph_Driver/Source/ald_lpuart.c delete mode 100644 bsp/essemi/es32f0334/libraries/ES32F033x_ALD_StdPeriph_Driver/Source/ald_pis.c delete mode 100644 bsp/essemi/es32f0334/libraries/ES32F033x_ALD_StdPeriph_Driver/Source/ald_pmu.c delete mode 100644 bsp/essemi/es32f0334/libraries/ES32F033x_ALD_StdPeriph_Driver/Source/ald_rmu.c delete mode 100644 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bsp/essemi/es32f0334/libraries/SConscript (limited to 'bsp') diff --git a/bsp/essemi/es32f0334/libraries/CMSIS/Device/EastSoft/ES32F033x/Include/es32f033x.h b/bsp/essemi/es32f0334/libraries/CMSIS/Device/EastSoft/ES32F033x/Include/es32f033x.h deleted file mode 100644 index e322ab9966..0000000000 --- a/bsp/essemi/es32f0334/libraries/CMSIS/Device/EastSoft/ES32F033x/Include/es32f033x.h +++ /dev/null @@ -1,5882 +0,0 @@ -/** - ********************************************************************************* - * - * @file es32f033x.h - * @brief ES32F033x Device Head File - * - * @version V1.0 - * @date 07 Nov 2017 - * @author AE Team - * @note - * - * Copyright (C) Shanghai Eastsoft Microelectronics Co. Ltd. All rights reserved. - * - ********************************************************************************* - */ - -#ifndef __ES32F0XX_H__ -#define __ES32F0XX_H__ - - -#define __I volatile const /* defines 'read only' permissions */ -#define __O volatile /* defines 'write only' permissions */ -#define __IO volatile /* defines 'read / write' permissions */ - -#define __CHECK_DEVICE_DEFINES -#define __NVIC_PRIO_BITS 2U -#define __CM0_REV 0x0000U -#define __Vendor_SysTickConfig 0U - -typedef enum IRQn { - /* Cortex-M0 processor cxceptions index */ - Reset_IRQn = -15, - NMI_IRQn = -14, - HardFault_IRQn = -13, - SVCall_IRQn = -5, - DebugMonitor_IRQn = -4, - PendSV_IRQn = -2, - SysTick_IRQn = -1, - - /* es32f0xx specific interrupt index */ - WWDG_IWDG_IRQn = 0, - LVD_IRQn = 1, - RTC_TSENSE_IRQn = 2, - CRYPT_TRNG_IRQn = 3, - CMU_IRQn = 4, - EXTI0_3_IRQn = 5, - EXTI4_7_IRQn = 6, - EXTI8_11_IRQn = 7, - EXTI12_15_IRQn = 8, - DMA_IRQn = 9, - CAN0_IRQn = 10, - LPTIM0_SPI2_IRQn = 11, - ADC_ACMP_IRQn = 12, - GP16C4T0_BRK_UP_TRIG_COM_IRQn = 13, - GP16C4T0_CC_IRQn = 14, - BS16T0_IRQn = 15, - GP16C2T0_IRQn = 17, - GP16C2T1_IRQn = 18, - BS16T1_UART2_IRQn = 19, - BS16T2_UART3_IRQn = 20, - GP16C4T1_LCD_IRQn = 21, - BS16T3_DAC0_IRQn = 22, - I2C0_IRQn = 23, - I2C1_IRQn = 24, - SPI0_IRQn = 25, - SPI1_IRQn = 26, - UART0_IRQn = 27, - UART1_IRQn = 28, - USART0_IRQn = 29, - USART1_IRQn = 30, - LPUART0_IRQn = 31, -} IRQn_Type; - - -#include -#include "core_cm0.h" - -#if defined (__CC_ARM) -#pragma anon_unions -#endif - -/* Peripheral register define */ - -/****************** Bit definition for SYSCFG_PROT register ************************/ - -#define SYSCFG_PROT_KEY_POSS 1U -#define SYSCFG_PROT_KEY_POSE 31U -#define SYSCFG_PROT_KEY_MSK BITS(SYSCFG_PROT_KEY_POSS,SYSCFG_PROT_KEY_POSE) - -#define SYSCFG_PROT_PROT_POS 0U -#define SYSCFG_PROT_PROT_MSK BIT(SYSCFG_PROT_PROT_POS) - -/****************** Bit definition for SYSCFG_MEMRMP register ************************/ - -#define SYSCFG_MEMRMP_VTOEN_POS 16U -#define SYSCFG_MEMRMP_VTOEN_MSK BIT(SYSCFG_MEMRMP_VTOEN_POS) - -#define SYSCFG_MEMRMP_BFRMPEN_POS 8U -#define SYSCFG_MEMRMP_BFRMPEN_MSK BIT(SYSCFG_MEMRMP_BFRMPEN_POS) - -#define SYSCFG_MEMRMP_BRRMPEN_POS 0U -#define SYSCFG_MEMRMP_BRRMPEN_MSK BIT(SYSCFG_MEMRMP_BRRMPEN_POS) - -/****************** Bit definition for SYSCFG_VTOR register ************************/ - -#define SYSCFG_VTOR_VTO_POSS 0U -#define SYSCFG_VTOR_VTO_POSE 29U -#define SYSCFG_VTOR_VTO_MSK BITS(SYSCFG_VTOR_VTO_POSS,SYSCFG_VTOR_VTO_POSE) - -typedef struct -{ - __IO uint32_t PROT; - __IO uint32_t MEMRMP; - __IO uint32_t VTOR; -} SYSCFG_TypeDef; - -/****************** Bit definition for MSC_FLASHKEY register ************************/ - -#define MSC_FLASHKEY_STATUS_POSS 0U -#define MSC_FLASHKEY_STATUS_POSE 1U -#define MSC_FLASHKEY_STATUS_MSK BITS(MSC_FLASHKEY_STATUS_POSS,MSC_FLASHKEY_STATUS_POSE) - -/****************** Bit definition for MSC_INFOKEY register ************************/ - -#define MSC_INFOKEY_STATUS_POSS 0U -#define MSC_INFOKEY_STATUS_POSE 1U -#define MSC_INFOKEY_STATUS_MSK BITS(MSC_INFOKEY_STATUS_POSS,MSC_INFOKEY_STATUS_POSE) - -/****************** Bit definition for MSC_FLASHADDR register ************************/ - -#define MSC_FLASHADDR_IFREN_POS 18U -#define MSC_FLASHADDR_IFREN_MSK BIT(MSC_FLASHADDR_IFREN_POS) - -#define MSC_FLASHADDR_ADDR_POSS 0U -#define MSC_FLASHADDR_ADDR_POSE 17U -#define MSC_FLASHADDR_ADDR_MSK BITS(MSC_FLASHADDR_ADDR_POSS,MSC_FLASHADDR_ADDR_POSE) - -/****************** Bit definition for MSC_FLASHFIFO register ************************/ - -#define MSC_FLASHFIFO_FIFO_POSS 0U -#define MSC_FLASHFIFO_FIFO_POSE 31U -#define MSC_FLASHFIFO_FIFO_MSK BITS(MSC_FLASHFIFO_FIFO_POSS,MSC_FLASHFIFO_FIFO_POSE) - -/****************** Bit definition for MSC_FLASHDL register ************************/ - -#define MSC_FLASHDL_DATAL_POSS 0U -#define MSC_FLASHDL_DATAL_POSE 31U -#define MSC_FLASHDL_DATAL_MSK BITS(MSC_FLASHDL_DATAL_POSS,MSC_FLASHDL_DATAL_POSE) - -/****************** Bit definition for MSC_FLASHDH register ************************/ - -#define MSC_FLASHDH_DATAH_POSS 0U -#define MSC_FLASHDH_DATAH_POSE 31U -#define MSC_FLASHDH_DATAH_MSK BITS(MSC_FLASHDH_DATAH_POSS,MSC_FLASHDH_DATAH_POSE) - -/****************** Bit definition for MSC_FLASHCMD register ************************/ - -#define MSC_FLASHCMD_CMD_POSS 0U -#define MSC_FLASHCMD_CMD_POSE 31U -#define MSC_FLASHCMD_CMD_MSK BITS(MSC_FLASHCMD_CMD_POSS,MSC_FLASHCMD_CMD_POSE) - -/****************** Bit definition for MSC_FLASHCR register ************************/ - -#define MSC_FLASHCR_FIFOEN_POS 5U -#define MSC_FLASHCR_FIFOEN_MSK BIT(MSC_FLASHCR_FIFOEN_POS) - -#define MSC_FLASHCR_FLASHREQ_POS 4U -#define MSC_FLASHCR_FLASHREQ_MSK BIT(MSC_FLASHCR_FLASHREQ_POS) - -#define MSC_FLASHCR_IAPRST_POS 1U -#define MSC_FLASHCR_IAPRST_MSK BIT(MSC_FLASHCR_IAPRST_POS) - -#define MSC_FLASHCR_IAPEN_POS 0U -#define MSC_FLASHCR_IAPEN_MSK BIT(MSC_FLASHCR_IAPEN_POS) - -/****************** Bit definition for MSC_FLASHSR register ************************/ - -#define MSC_FLASHSR_TIMEOUT_POS 7U -#define MSC_FLASHSR_TIMEOUT_MSK BIT(MSC_FLASHSR_TIMEOUT_POS) - -#define MSC_FLASHSR_PROG_POS 6U -#define MSC_FLASHSR_PROG_MSK BIT(MSC_FLASHSR_PROG_POS) - -#define MSC_FLASHSR_SERA_POS 5U -#define MSC_FLASHSR_SERA_MSK BIT(MSC_FLASHSR_SERA_POS) - -#define MSC_FLASHSR_MASE_POS 4U -#define MSC_FLASHSR_MASE_MSK BIT(MSC_FLASHSR_MASE_POS) - -#define MSC_FLASHSR_ADDR_OV_POS 3U -#define MSC_FLASHSR_ADDR_OV_MSK BIT(MSC_FLASHSR_ADDR_OV_POS) - -#define MSC_FLASHSR_WRP_FLAG_POS 2U -#define MSC_FLASHSR_WRP_FLAG_MSK BIT(MSC_FLASHSR_WRP_FLAG_POS) - -#define MSC_FLASHSR_BUSY_POS 1U -#define MSC_FLASHSR_BUSY_MSK BIT(MSC_FLASHSR_BUSY_POS) - -#define MSC_FLASHSR_FLASHACK_POS 0U -#define MSC_FLASHSR_FLASHACK_MSK BIT(MSC_FLASHSR_FLASHACK_POS) - -/****************** Bit definition for MSC_FLASHPL register ************************/ - -#define MSC_FLASHPL_PROG_LEN_POSS 0U -#define MSC_FLASHPL_PROG_LEN_POSE 15U -#define MSC_FLASHPL_PROG_LEN_MSK BITS(MSC_FLASHPL_PROG_LEN_POSS,MSC_FLASHPL_PROG_LEN_POSE) - -/****************** Bit definition for MSC_MEMWAIT register ************************/ - -#define MSC_MEMWAIT_SRAM_W_POSS 8U -#define MSC_MEMWAIT_SRAM_W_POSE 9U -#define MSC_MEMWAIT_SRAM_W_MSK BITS(MSC_MEMWAIT_SRAM_W_POSS,MSC_MEMWAIT_SRAM_W_POSE) - -#define MSC_MEMWAIT_FLASH_W_POSS 0U -#define MSC_MEMWAIT_FLASH_W_POSE 3U -#define MSC_MEMWAIT_FLASH_W_MSK BITS(MSC_MEMWAIT_FLASH_W_POSS,MSC_MEMWAIT_FLASH_W_POSE) - -typedef struct -{ - __IO uint32_t FLASHKEY; - __IO uint32_t INFOKEY; - __IO uint32_t FLASHADDR; - __O uint32_t FLASHFIFO; - __IO uint32_t FLASHDL; - __IO uint32_t FLASHDH; - __O uint32_t FLASHCMD; - __IO uint32_t FLASHCR; - __I uint32_t FLASHSR; - __IO uint32_t FLASHPL; - __IO uint32_t MEMWAIT; -} MSC_TypeDef; - -/****************** Bit definition for BKPC_PROT register ************************/ - -#define BKPC_PROT_KEY_POSS 1U -#define BKPC_PROT_KEY_POSE 31U -#define BKPC_PROT_KEY_MSK BITS(BKPC_PROT_KEY_POSS,BKPC_PROT_KEY_POSE) - -#define BKPC_PROT_PROT_POS 0U -#define BKPC_PROT_PROT_MSK BIT(BKPC_PROT_PROT_POS) - -/****************** Bit definition for BKPC_CR register ************************/ - -#define BKPC_CR_LDO_VSEL_POSS 24U -#define BKPC_CR_LDO_VSEL_POSE 26U -#define BKPC_CR_LDO_VSEL_MSK BITS(BKPC_CR_LDO_VSEL_POSS,BKPC_CR_LDO_VSEL_POSE) - -#define BKPC_CR_MT_STDB_POS 19U -#define BKPC_CR_MT_STDB_MSK BIT(BKPC_CR_MT_STDB_POS) - -#define BKPC_CR_VR1P5_VSEL_POSS 16U -#define BKPC_CR_VR1P5_VSEL_POSE 18U -#define BKPC_CR_VR1P5_VSEL_MSK BITS(BKPC_CR_VR1P5_VSEL_POSS,BKPC_CR_VR1P5_VSEL_POSE) - -#define BKPC_CR_TC_PWRDWN_POS 13U -#define BKPC_CR_TC_PWRDWN_MSK BIT(BKPC_CR_TC_PWRDWN_POS) - -#define BKPC_CR_WKPOL_POS 12U -#define BKPC_CR_WKPOL_MSK BIT(BKPC_CR_WKPOL_POS) - -#define BKPC_CR_WKPS_POSS 9U -#define BKPC_CR_WKPS_POSE 11U -#define BKPC_CR_WKPS_MSK BITS(BKPC_CR_WKPS_POSS,BKPC_CR_WKPS_POSE) - -#define BKPC_CR_WKPEN_POS 8U -#define BKPC_CR_WKPEN_MSK BIT(BKPC_CR_WKPEN_POS) - -#define BKPC_CR_LRCEN_POS 2U -#define BKPC_CR_LRCEN_MSK BIT(BKPC_CR_LRCEN_POS) - -#define BKPC_CR_LOSMEN_POS 1U -#define BKPC_CR_LOSMEN_MSK BIT(BKPC_CR_LOSMEN_POS) - -#define BKPC_CR_LOSCEN_POS 0U -#define BKPC_CR_LOSCEN_MSK BIT(BKPC_CR_LOSCEN_POS) - -/****************** Bit definition for BKPC_PCCR register ************************/ - -#define BKPC_PCCR_TSENSECS_POSS 4U -#define BKPC_PCCR_TSENSECS_POSE 5U -#define BKPC_PCCR_TSENSECS_MSK BITS(BKPC_PCCR_TSENSECS_POSS,BKPC_PCCR_TSENSECS_POSE) - -#define BKPC_PCCR_RTCCS_POSS 0U -#define BKPC_PCCR_RTCCS_POSE 1U -#define BKPC_PCCR_RTCCS_MSK BITS(BKPC_PCCR_RTCCS_POSS,BKPC_PCCR_RTCCS_POSE) - -typedef struct -{ - __IO uint32_t PROT; - __IO uint32_t CR; - __IO uint32_t PCCR; -} BKPC_TypeDef; - -/****************** Bit definition for PMU_CR register ************************/ - -#define PMU_CR_MTSTOP_POS 21U -#define PMU_CR_MTSTOP_MSK BIT(PMU_CR_MTSTOP_POS) - -#define PMU_CR_LPSTOP_POS 20U -#define PMU_CR_LPSTOP_MSK BIT(PMU_CR_LPSTOP_POS) - -#define PMU_CR_LPRUN_POS 19U -#define PMU_CR_LPRUN_MSK BIT(PMU_CR_LPRUN_POS) - -#define PMU_CR_LPVS_POSS 16U -#define PMU_CR_LPVS_POSE 18U -#define PMU_CR_LPVS_MSK BITS(PMU_CR_LPVS_POSS,PMU_CR_LPVS_POSE) - -#define PMU_CR_WKPS_POSS 9U -#define PMU_CR_WKPS_POSE 11U -#define PMU_CR_WKPS_MSK BITS(PMU_CR_WKPS_POSS,PMU_CR_WKPS_POSE) - -#define PMU_CR_WKPEN_POS 8U -#define PMU_CR_WKPEN_MSK BIT(PMU_CR_WKPEN_POS) - -#define PMU_CR_CSTANDBYF_POS 3U -#define PMU_CR_CSTANDBYF_MSK BIT(PMU_CR_CSTANDBYF_POS) - -#define PMU_CR_CWUF_POS 2U -#define PMU_CR_CWUF_MSK BIT(PMU_CR_CWUF_POS) - -#define PMU_CR_LPM_POSS 0U -#define PMU_CR_LPM_POSE 1U -#define PMU_CR_LPM_MSK BITS(PMU_CR_LPM_POSS,PMU_CR_LPM_POSE) - -/****************** Bit definition for PMU_SR register ************************/ - -#define PMU_SR_STANDBYF_POS 1U -#define PMU_SR_STANDBYF_MSK BIT(PMU_SR_STANDBYF_POS) - -#define PMU_SR_WUF_POS 0U -#define PMU_SR_WUF_MSK BIT(PMU_SR_WUF_POS) - -/****************** Bit definition for PMU_LVDCR register ************************/ - -#define PMU_LVDCR_LVDO_POS 15U -#define PMU_LVDCR_LVDO_MSK BIT(PMU_LVDCR_LVDO_POS) - -#define PMU_LVDCR_LVDFLT_POS 11U -#define PMU_LVDCR_LVDFLT_MSK BIT(PMU_LVDCR_LVDFLT_POS) - -#define PMU_LVDCR_LVIFS_POSS 8U -#define PMU_LVDCR_LVIFS_POSE 10U -#define PMU_LVDCR_LVIFS_MSK BITS(PMU_LVDCR_LVIFS_POSS,PMU_LVDCR_LVIFS_POSE) - -#define PMU_LVDCR_LVDS_POSS 4U -#define PMU_LVDCR_LVDS_POSE 7U -#define PMU_LVDCR_LVDS_MSK BITS(PMU_LVDCR_LVDS_POSS,PMU_LVDCR_LVDS_POSE) - -#define PMU_LVDCR_LVDCIF_POS 3U -#define PMU_LVDCR_LVDCIF_MSK BIT(PMU_LVDCR_LVDCIF_POS) - -#define PMU_LVDCR_LVDIF_POS 2U -#define PMU_LVDCR_LVDIF_MSK BIT(PMU_LVDCR_LVDIF_POS) - -#define PMU_LVDCR_LVDIE_POS 1U -#define PMU_LVDCR_LVDIE_MSK BIT(PMU_LVDCR_LVDIE_POS) - -#define PMU_LVDCR_LVDEN_POS 0U -#define PMU_LVDCR_LVDEN_MSK BIT(PMU_LVDCR_LVDEN_POS) - -/****************** Bit definition for PMU_PWRCR register ************************/ - -#define PMU_PWRCR_BXCAN_POS 4U -#define PMU_PWRCR_BXCAN_MSK BIT(PMU_PWRCR_BXCAN_POS) - -#define PMU_PWRCR_SRAM_POSS 0U -#define PMU_PWRCR_SRAM_POSE 1U -#define PMU_PWRCR_SRAM_MSK BITS(PMU_PWRCR_SRAM_POSS,PMU_PWRCR_SRAM_POSE) - -/****************** Bit definition for PMU_TWUR register ************************/ - -#define PMU_TWUR_TWU_POSS 0U -#define PMU_TWUR_TWU_POSE 11U -#define PMU_TWUR_TWU_MSK BITS(PMU_TWUR_TWU_POSS,PMU_TWUR_TWU_POSE) - -/****************** Bit definition for PMU_VREFCR register ************************/ - -#define PMU_VREFCR_FLTS_POSS 13U -#define PMU_VREFCR_FLTS_POSE 14U -#define PMU_VREFCR_FLTS_MSK BITS(PMU_VREFCR_FLTS_POSS,PMU_VREFCR_FLTS_POSE) - -#define PMU_VREFCR_CHOPCS_POSS 10U -#define PMU_VREFCR_CHOPCS_POSE 12U -#define PMU_VREFCR_CHOPCS_MSK BITS(PMU_VREFCR_CHOPCS_POSS,PMU_VREFCR_CHOPCS_POSE) - -#define PMU_VREFCR_CHOP1EN_POS 9U -#define PMU_VREFCR_CHOP1EN_MSK BIT(PMU_VREFCR_CHOP1EN_POS) - -#define PMU_VREFCR_CHOPEN_POS 8U -#define PMU_VREFCR_CHOPEN_MSK BIT(PMU_VREFCR_CHOPEN_POS) - -#define PMU_VREFCR_VREFEN_POS 0U -#define PMU_VREFCR_VREFEN_MSK BIT(PMU_VREFCR_VREFEN_POS) - -typedef struct -{ - __IO uint32_t CR; - __I uint32_t SR; - __IO uint32_t LVDCR; - __IO uint32_t PWRCR; - __IO uint32_t TWUR; - __IO uint32_t VREFCR; -} PMU_TypeDef; - -/****************** Bit definition for RMU_CR register ************************/ - -#define RMU_CR_BORVS_POSS 4U -#define RMU_CR_BORVS_POSE 7U -#define RMU_CR_BORVS_MSK BITS(RMU_CR_BORVS_POSS,RMU_CR_BORVS_POSE) - -#define RMU_CR_BORFLT_POSS 1U -#define RMU_CR_BORFLT_POSE 3U -#define RMU_CR_BORFLT_MSK BITS(RMU_CR_BORFLT_POSS,RMU_CR_BORFLT_POSE) - -#define RMU_CR_BOREN_POS 0U -#define RMU_CR_BOREN_MSK BIT(RMU_CR_BOREN_POS) - -/****************** Bit definition for RMU_RSTSR register ************************/ - -#define RMU_RSTSR_CFGERR_POS 16U -#define RMU_RSTSR_CFGERR_MSK BIT(RMU_RSTSR_CFGERR_POS) - -#define RMU_RSTSR_CFG_POS 10U -#define RMU_RSTSR_CFG_MSK BIT(RMU_RSTSR_CFG_POS) - -#define RMU_RSTSR_CPU_POS 9U -#define RMU_RSTSR_CPU_MSK BIT(RMU_RSTSR_CPU_POS) - -#define RMU_RSTSR_MCU_POS 8U -#define RMU_RSTSR_MCU_MSK BIT(RMU_RSTSR_MCU_POS) - -#define RMU_RSTSR_CHIP_POS 7U -#define RMU_RSTSR_CHIP_MSK BIT(RMU_RSTSR_CHIP_POS) - -#define RMU_RSTSR_LOCKUP_POS 6U -#define RMU_RSTSR_LOCKUP_MSK BIT(RMU_RSTSR_LOCKUP_POS) - -#define RMU_RSTSR_WWDT_POS 5U -#define RMU_RSTSR_WWDT_MSK BIT(RMU_RSTSR_WWDT_POS) - -#define RMU_RSTSR_IWDT_POS 4U -#define RMU_RSTSR_IWDT_MSK BIT(RMU_RSTSR_IWDT_POS) - -#define RMU_RSTSR_NMRST_POS 3U -#define RMU_RSTSR_NMRST_MSK BIT(RMU_RSTSR_NMRST_POS) - -#define RMU_RSTSR_BOR_POS 2U -#define RMU_RSTSR_BOR_MSK BIT(RMU_RSTSR_BOR_POS) - -#define RMU_RSTSR_WAKEUP_POS 1U -#define RMU_RSTSR_WAKEUP_MSK BIT(RMU_RSTSR_WAKEUP_POS) - -#define RMU_RSTSR_POR_POS 0U -#define RMU_RSTSR_POR_MSK BIT(RMU_RSTSR_POR_POS) - -/****************** Bit definition for RMU_CRSTSR register ************************/ - -#define RMU_CRSTSR_CFG_POS 10U -#define RMU_CRSTSR_CFG_MSK BIT(RMU_CRSTSR_CFG_POS) - -#define RMU_CRSTSR_CPU_POS 9U -#define RMU_CRSTSR_CPU_MSK BIT(RMU_CRSTSR_CPU_POS) - -#define RMU_CRSTSR_MCU_POS 8U -#define RMU_CRSTSR_MCU_MSK BIT(RMU_CRSTSR_MCU_POS) - -#define RMU_CRSTSR_CHIP_POS 7U -#define RMU_CRSTSR_CHIP_MSK BIT(RMU_CRSTSR_CHIP_POS) - -#define RMU_CRSTSR_LOCKUP_POS 6U -#define RMU_CRSTSR_LOCKUP_MSK BIT(RMU_CRSTSR_LOCKUP_POS) - -#define RMU_CRSTSR_WWDT_POS 5U -#define RMU_CRSTSR_WWDT_MSK BIT(RMU_CRSTSR_WWDT_POS) - -#define RMU_CRSTSR_IWDT_POS 4U -#define RMU_CRSTSR_IWDT_MSK BIT(RMU_CRSTSR_IWDT_POS) - -#define RMU_CRSTSR_NMRST_POS 3U -#define RMU_CRSTSR_NMRST_MSK BIT(RMU_CRSTSR_NMRST_POS) - -#define RMU_CRSTSR_BOR_POS 2U -#define RMU_CRSTSR_BOR_MSK BIT(RMU_CRSTSR_BOR_POS) - -#define RMU_CRSTSR_WAKEUP_POS 1U -#define RMU_CRSTSR_WAKEUP_MSK BIT(RMU_CRSTSR_WAKEUP_POS) - -#define RMU_CRSTSR_POR_POS 0U -#define RMU_CRSTSR_POR_MSK BIT(RMU_CRSTSR_POR_POS) - -/****************** Bit definition for RMU_AHB1RSTR register ************************/ - -#define RMU_AHB1RSTR_PISRST_POS 5U -#define RMU_AHB1RSTR_PISRST_MSK BIT(RMU_AHB1RSTR_PISRST_POS) - -#define RMU_AHB1RSTR_TRNGRST_POS 4U -#define RMU_AHB1RSTR_TRNGRST_MSK BIT(RMU_AHB1RSTR_TRNGRST_POS) - -#define RMU_AHB1RSTR_CRYPTRST_POS 3U -#define RMU_AHB1RSTR_CRYPTRST_MSK BIT(RMU_AHB1RSTR_CRYPTRST_POS) - -#define RMU_AHB1RSTR_CALCRST_POS 2U -#define RMU_AHB1RSTR_CALCRST_MSK BIT(RMU_AHB1RSTR_CALCRST_POS) - -#define RMU_AHB1RSTR_CRCRST_POS 1U -#define RMU_AHB1RSTR_CRCRST_MSK BIT(RMU_AHB1RSTR_CRCRST_POS) - -#define RMU_AHB1RSTR_GPIORST_POS 0U -#define RMU_AHB1RSTR_GPIORST_MSK BIT(RMU_AHB1RSTR_GPIORST_POS) - -/****************** Bit definition for RMU_AHB2RSTR register ************************/ - -#define RMU_AHB2RSTR_CPURST_POS 1U -#define RMU_AHB2RSTR_CPURST_MSK BIT(RMU_AHB2RSTR_CPURST_POS) - -#define RMU_AHB2RSTR_CHIPRST_POS 0U -#define RMU_AHB2RSTR_CHIPRST_MSK BIT(RMU_AHB2RSTR_CHIPRST_POS) - -/****************** Bit definition for RMU_APB1RSTR register ************************/ - -#define RMU_APB1RSTR_CAN0RST_POS 24U -#define RMU_APB1RSTR_CAN0RST_MSK BIT(RMU_APB1RSTR_CAN0RST_POS) - -#define RMU_APB1RSTR_I2C1RST_POS 21U -#define RMU_APB1RSTR_I2C1RST_MSK BIT(RMU_APB1RSTR_I2C1RST_POS) - -#define RMU_APB1RSTR_I2C0RST_POS 20U -#define RMU_APB1RSTR_I2C0RST_MSK BIT(RMU_APB1RSTR_I2C0RST_POS) - -#define RMU_APB1RSTR_SPI2RST_POS 18U -#define RMU_APB1RSTR_SPI2RST_MSK BIT(RMU_APB1RSTR_SPI2RST_POS) - -#define RMU_APB1RSTR_SPI1RST_POS 17U -#define RMU_APB1RSTR_SPI1RST_MSK BIT(RMU_APB1RSTR_SPI1RST_POS) - -#define RMU_APB1RSTR_SPI0RST_POS 16U -#define RMU_APB1RSTR_SPI0RST_MSK BIT(RMU_APB1RSTR_SPI0RST_POS) - -#define RMU_APB1RSTR_USART1RST_POS 13U -#define RMU_APB1RSTR_USART1RST_MSK BIT(RMU_APB1RSTR_USART1RST_POS) - -#define RMU_APB1RSTR_USART0RST_POS 12U -#define RMU_APB1RSTR_USART0RST_MSK BIT(RMU_APB1RSTR_USART0RST_POS) - -#define RMU_APB1RSTR_UART3RST_POS 11U -#define RMU_APB1RSTR_UART3RST_MSK BIT(RMU_APB1RSTR_UART3RST_POS) - -#define RMU_APB1RSTR_UART2RST_POS 10U -#define RMU_APB1RSTR_UART2RST_MSK BIT(RMU_APB1RSTR_UART2RST_POS) - -#define RMU_APB1RSTR_UART1RST_POS 9U -#define RMU_APB1RSTR_UART1RST_MSK BIT(RMU_APB1RSTR_UART1RST_POS) - -#define RMU_APB1RSTR_UART0RST_POS 8U -#define RMU_APB1RSTR_UART0RST_MSK BIT(RMU_APB1RSTR_UART0RST_POS) - -#define RMU_APB1RSTR_TIM7RST_POS 7U -#define RMU_APB1RSTR_TIM7RST_MSK BIT(RMU_APB1RSTR_TIM7RST_POS) - -#define RMU_APB1RSTR_TIM6RST_POS 6U -#define RMU_APB1RSTR_TIM6RST_MSK BIT(RMU_APB1RSTR_TIM6RST_POS) - -#define RMU_APB1RSTR_TIM5RST_POS 5U -#define RMU_APB1RSTR_TIM5RST_MSK BIT(RMU_APB1RSTR_TIM5RST_POS) - -#define RMU_APB1RSTR_TIM4RST_POS 4U -#define RMU_APB1RSTR_TIM4RST_MSK BIT(RMU_APB1RSTR_TIM4RST_POS) - -#define RMU_APB1RSTR_TIM3RST_POS 3U -#define RMU_APB1RSTR_TIM3RST_MSK BIT(RMU_APB1RSTR_TIM3RST_POS) - -#define RMU_APB1RSTR_TIM2RST_POS 2U -#define RMU_APB1RSTR_TIM2RST_MSK BIT(RMU_APB1RSTR_TIM2RST_POS) - -#define RMU_APB1RSTR_TIM1RST_POS 1U -#define RMU_APB1RSTR_TIM1RST_MSK BIT(RMU_APB1RSTR_TIM1RST_POS) - -#define RMU_APB1RSTR_TIM0RST_POS 0U -#define RMU_APB1RSTR_TIM0RST_MSK BIT(RMU_APB1RSTR_TIM0RST_POS) - -/****************** Bit definition for RMU_APB2RSTR register ************************/ - -#define RMU_APB2RSTR_BKPRAMRST_POS 18U -#define RMU_APB2RSTR_BKPRAMRST_MSK BIT(RMU_APB2RSTR_BKPRAMRST_POS) - -#define RMU_APB2RSTR_BKPCRST_POS 17U -#define RMU_APB2RSTR_BKPCRST_MSK BIT(RMU_APB2RSTR_BKPCRST_POS) - -#define RMU_APB2RSTR_TSENSERST_POS 16U -#define RMU_APB2RSTR_TSENSERST_MSK BIT(RMU_APB2RSTR_TSENSERST_POS) - -#define RMU_APB2RSTR_RTCRST_POS 15U -#define RMU_APB2RSTR_RTCRST_MSK BIT(RMU_APB2RSTR_RTCRST_POS) - -#define RMU_APB2RSTR_IWDTRST_POS 14U -#define RMU_APB2RSTR_IWDTRST_MSK BIT(RMU_APB2RSTR_IWDTRST_POS) - -#define RMU_APB2RSTR_LCDRST_POS 13U -#define RMU_APB2RSTR_LCDRST_MSK BIT(RMU_APB2RSTR_LCDRST_POS) - -#define RMU_APB2RSTR_WWDTRST_POS 12U -#define RMU_APB2RSTR_WWDTRST_MSK BIT(RMU_APB2RSTR_WWDTRST_POS) - -#define RMU_APB2RSTR_OPAMPRST_POS 8U -#define RMU_APB2RSTR_OPAMPRST_MSK BIT(RMU_APB2RSTR_OPAMPRST_POS) - -#define RMU_APB2RSTR_ACMP1RST_POS 7U -#define RMU_APB2RSTR_ACMP1RST_MSK BIT(RMU_APB2RSTR_ACMP1RST_POS) - -#define RMU_APB2RSTR_ACMP0RST_POS 6U -#define RMU_APB2RSTR_ACMP0RST_MSK BIT(RMU_APB2RSTR_ACMP0RST_POS) - -#define RMU_APB2RSTR_ADC0RST_POS 4U -#define RMU_APB2RSTR_ADC0RST_MSK BIT(RMU_APB2RSTR_ADC0RST_POS) - -#define RMU_APB2RSTR_LPUART0RST_POS 2U -#define RMU_APB2RSTR_LPUART0RST_MSK BIT(RMU_APB2RSTR_LPUART0RST_POS) - -#define RMU_APB2RSTR_LPTIM0RST_POS 0U -#define RMU_APB2RSTR_LPTIM0RST_MSK BIT(RMU_APB2RSTR_LPTIM0RST_POS) - -typedef struct -{ - __IO uint32_t CR; - uint32_t RESERVED0[3] ; - __I uint32_t RSTSR; - __O uint32_t CRSTSR; - uint32_t RESERVED1[2] ; - __O uint32_t AHB1RSTR; - __O uint32_t AHB2RSTR; - uint32_t RESERVED2[2] ; - __O uint32_t APB1RSTR; - __O uint32_t APB2RSTR; -} RMU_TypeDef; - -/****************** Bit definition for CMU_CSR register ************************/ - -#define CMU_CSR_CFT_RDYN_POS 25U -#define CMU_CSR_CFT_RDYN_MSK BIT(CMU_CSR_CFT_RDYN_POS) - -#define CMU_CSR_CFT_STU_POS 24U -#define CMU_CSR_CFT_STU_MSK BIT(CMU_CSR_CFT_STU_POS) - -#define CMU_CSR_CFT_CMD_POSS 16U -#define CMU_CSR_CFT_CMD_POSE 23U -#define CMU_CSR_CFT_CMD_MSK BITS(CMU_CSR_CFT_CMD_POSS,CMU_CSR_CFT_CMD_POSE) - -#define CMU_CSR_SYS_RDYN_POS 12U -#define CMU_CSR_SYS_RDYN_MSK BIT(CMU_CSR_SYS_RDYN_POS) - -#define CMU_CSR_SYS_STU_POSS 8U -#define CMU_CSR_SYS_STU_POSE 10U -#define CMU_CSR_SYS_STU_MSK BITS(CMU_CSR_SYS_STU_POSS,CMU_CSR_SYS_STU_POSE) - -#define CMU_CSR_SYS_CMD_POSS 0U -#define CMU_CSR_SYS_CMD_POSE 2U -#define CMU_CSR_SYS_CMD_MSK BITS(CMU_CSR_SYS_CMD_POSS,CMU_CSR_SYS_CMD_POSE) - -/****************** Bit definition for CMU_CFGR register ************************/ - -#define CMU_CFGR_HRCFST_POS 25U -#define CMU_CFGR_HRCFST_MSK BIT(CMU_CFGR_HRCFST_POS) - -#define CMU_CFGR_HRCFSW_POS 24U -#define CMU_CFGR_HRCFSW_MSK BIT(CMU_CFGR_HRCFSW_POS) - -#define CMU_CFGR_PCLK2DIV_POSS 20U -#define CMU_CFGR_PCLK2DIV_POSE 23U -#define CMU_CFGR_PCLK2DIV_MSK BITS(CMU_CFGR_PCLK2DIV_POSS,CMU_CFGR_PCLK2DIV_POSE) - -#define CMU_CFGR_PCLK1DIV_POSS 16U -#define CMU_CFGR_PCLK1DIV_POSE 19U -#define CMU_CFGR_PCLK1DIV_MSK BITS(CMU_CFGR_PCLK1DIV_POSS,CMU_CFGR_PCLK1DIV_POSE) - -#define CMU_CFGR_SYSDIV_POSS 12U -#define CMU_CFGR_SYSDIV_POSE 15U -#define CMU_CFGR_SYSDIV_MSK BITS(CMU_CFGR_SYSDIV_POSS,CMU_CFGR_SYSDIV_POSE) - -#define CMU_CFGR_HCLK1DIV_POSS 0U -#define CMU_CFGR_HCLK1DIV_POSE 3U -#define CMU_CFGR_HCLK1DIV_MSK BITS(CMU_CFGR_HCLK1DIV_POSS,CMU_CFGR_HCLK1DIV_POSE) - -/****************** Bit definition for CMU_CLKENR register ************************/ - -#define CMU_CLKENR_PLL2EN_POS 9U -#define CMU_CLKENR_PLL2EN_MSK BIT(CMU_CLKENR_PLL2EN_POS) - -#define CMU_CLKENR_PLL1EN_POS 8U -#define CMU_CLKENR_PLL1EN_MSK BIT(CMU_CLKENR_PLL1EN_POS) - -#define CMU_CLKENR_ULRCEN_POS 4U -#define CMU_CLKENR_ULRCEN_MSK BIT(CMU_CLKENR_ULRCEN_POS) - -#define CMU_CLKENR_LRCEN_POS 3U -#define CMU_CLKENR_LRCEN_MSK BIT(CMU_CLKENR_LRCEN_POS) - -#define CMU_CLKENR_HRCEN_POS 2U -#define CMU_CLKENR_HRCEN_MSK BIT(CMU_CLKENR_HRCEN_POS) - -#define CMU_CLKENR_LOSCEN_POS 1U -#define CMU_CLKENR_LOSCEN_MSK BIT(CMU_CLKENR_LOSCEN_POS) - -#define CMU_CLKENR_HOSCEN_POS 0U -#define CMU_CLKENR_HOSCEN_MSK BIT(CMU_CLKENR_HOSCEN_POS) - -/****************** Bit definition for CMU_CLKSR register ************************/ - -#define CMU_CLKSR_PLL2RDY_POS 25U -#define CMU_CLKSR_PLL2RDY_MSK BIT(CMU_CLKSR_PLL2RDY_POS) - -#define CMU_CLKSR_PLL1RDY_POS 24U -#define CMU_CLKSR_PLL1RDY_MSK BIT(CMU_CLKSR_PLL1RDY_POS) - -#define CMU_CLKSR_LRCRDY_POS 19U -#define CMU_CLKSR_LRCRDY_MSK BIT(CMU_CLKSR_LRCRDY_POS) - -#define CMU_CLKSR_HRCRDY_POS 18U -#define CMU_CLKSR_HRCRDY_MSK BIT(CMU_CLKSR_HRCRDY_POS) - -#define CMU_CLKSR_LOSCRDY_POS 17U -#define CMU_CLKSR_LOSCRDY_MSK BIT(CMU_CLKSR_LOSCRDY_POS) - -#define CMU_CLKSR_HOSCRDY_POS 16U -#define CMU_CLKSR_HOSCRDY_MSK BIT(CMU_CLKSR_HOSCRDY_POS) - -#define CMU_CLKSR_PLL2ACT_POS 9U -#define CMU_CLKSR_PLL2ACT_MSK BIT(CMU_CLKSR_PLL2ACT_POS) - -#define CMU_CLKSR_PLL1ACT_POS 8U -#define CMU_CLKSR_PLL1ACT_MSK BIT(CMU_CLKSR_PLL1ACT_POS) - -#define CMU_CLKSR_ULRCACT_POS 4U -#define CMU_CLKSR_ULRCACT_MSK BIT(CMU_CLKSR_ULRCACT_POS) - -#define CMU_CLKSR_LRCACT_POS 3U -#define CMU_CLKSR_LRCACT_MSK BIT(CMU_CLKSR_LRCACT_POS) - -#define CMU_CLKSR_HRCACT_POS 2U -#define CMU_CLKSR_HRCACT_MSK BIT(CMU_CLKSR_HRCACT_POS) - -#define CMU_CLKSR_LOSCACT_POS 1U -#define CMU_CLKSR_LOSCACT_MSK BIT(CMU_CLKSR_LOSCACT_POS) - -#define CMU_CLKSR_HOSCACT_POS 0U -#define CMU_CLKSR_HOSCACT_MSK BIT(CMU_CLKSR_HOSCACT_POS) - -/****************** Bit definition for CMU_PLLCFG register ************************/ - -#define CMU_PLLCFG_PLL2LCKN_POS 17U -#define CMU_PLLCFG_PLL2LCKN_MSK BIT(CMU_PLLCFG_PLL2LCKN_POS) - -#define CMU_PLLCFG_PLL1LCKN_POS 16U -#define CMU_PLLCFG_PLL1LCKN_MSK BIT(CMU_PLLCFG_PLL1LCKN_POS) - -#define CMU_PLLCFG_PLL2RFS_POSS 8U -#define CMU_PLLCFG_PLL2RFS_POSE 9U -#define CMU_PLLCFG_PLL2RFS_MSK BITS(CMU_PLLCFG_PLL2RFS_POSS,CMU_PLLCFG_PLL2RFS_POSE) - -#define CMU_PLLCFG_PLL1OS_POS 4U -#define CMU_PLLCFG_PLL1OS_MSK BIT(CMU_PLLCFG_PLL1OS_POS) - -#define CMU_PLLCFG_PLL1RFS_POSS 0U -#define CMU_PLLCFG_PLL1RFS_POSE 2U -#define CMU_PLLCFG_PLL1RFS_MSK BITS(CMU_PLLCFG_PLL1RFS_POSS,CMU_PLLCFG_PLL1RFS_POSE) - -/****************** Bit definition for CMU_HOSCCFG register ************************/ - -#define CMU_HOSCCFG_FREQ_POSS 0U -#define CMU_HOSCCFG_FREQ_POSE 4U -#define CMU_HOSCCFG_FREQ_MSK BITS(CMU_HOSCCFG_FREQ_POSS,CMU_HOSCCFG_FREQ_POSE) - -/****************** Bit definition for CMU_HOSMCR register ************************/ - -#define CMU_HOSMCR_NMIE_POS 20U -#define CMU_HOSMCR_NMIE_MSK BIT(CMU_HOSMCR_NMIE_POS) - -#define CMU_HOSMCR_STPIF_POS 19U -#define CMU_HOSMCR_STPIF_MSK BIT(CMU_HOSMCR_STPIF_POS) - -#define CMU_HOSMCR_STRIF_POS 18U -#define CMU_HOSMCR_STRIF_MSK BIT(CMU_HOSMCR_STRIF_POS) - -#define CMU_HOSMCR_STPIE_POS 17U -#define CMU_HOSMCR_STPIE_MSK BIT(CMU_HOSMCR_STPIE_POS) - -#define CMU_HOSMCR_STRIE_POS 16U -#define CMU_HOSMCR_STRIE_MSK BIT(CMU_HOSMCR_STRIE_POS) - -#define CMU_HOSMCR_FRQS_POSS 8U -#define CMU_HOSMCR_FRQS_POSE 10U -#define CMU_HOSMCR_FRQS_MSK BITS(CMU_HOSMCR_FRQS_POSS,CMU_HOSMCR_FRQS_POSE) - -#define CMU_HOSMCR_CLKS_POS 1U -#define CMU_HOSMCR_CLKS_MSK BIT(CMU_HOSMCR_CLKS_POS) - -#define CMU_HOSMCR_EN_POS 0U -#define CMU_HOSMCR_EN_MSK BIT(CMU_HOSMCR_EN_POS) - -/****************** Bit definition for CMU_LOSMCR register ************************/ - -#define CMU_LOSMCR_NMIE_POS 20U -#define CMU_LOSMCR_NMIE_MSK BIT(CMU_LOSMCR_NMIE_POS) - -#define CMU_LOSMCR_STPIF_POS 19U -#define CMU_LOSMCR_STPIF_MSK BIT(CMU_LOSMCR_STPIF_POS) - -#define CMU_LOSMCR_STRIF_POS 18U -#define CMU_LOSMCR_STRIF_MSK BIT(CMU_LOSMCR_STRIF_POS) - -#define CMU_LOSMCR_STPIE_POS 17U -#define CMU_LOSMCR_STPIE_MSK BIT(CMU_LOSMCR_STPIE_POS) - -#define CMU_LOSMCR_STRIE_POS 16U -#define CMU_LOSMCR_STRIE_MSK BIT(CMU_LOSMCR_STRIE_POS) - -#define CMU_LOSMCR_CLKS_POS 1U -#define CMU_LOSMCR_CLKS_MSK BIT(CMU_LOSMCR_CLKS_POS) - -#define CMU_LOSMCR_EN_POS 0U -#define CMU_LOSMCR_EN_MSK BIT(CMU_LOSMCR_EN_POS) - -/****************** Bit definition for CMU_PULMCR register ************************/ - -#define CMU_PULMCR_NMIE_POS 20U -#define CMU_PULMCR_NMIE_MSK BIT(CMU_PULMCR_NMIE_POS) - -#define CMU_PULMCR_ULKIF_POS 19U -#define CMU_PULMCR_ULKIF_MSK BIT(CMU_PULMCR_ULKIF_POS) - -#define CMU_PULMCR_LCKIF_POS 18U -#define CMU_PULMCR_LCKIF_MSK BIT(CMU_PULMCR_LCKIF_POS) - -#define CMU_PULMCR_ULKIE_POS 17U -#define CMU_PULMCR_ULKIE_MSK BIT(CMU_PULMCR_ULKIE_POS) - -#define CMU_PULMCR_LCKIE_POS 16U -#define CMU_PULMCR_LCKIE_MSK BIT(CMU_PULMCR_LCKIE_POS) - -#define CMU_PULMCR_MODE_POSS 8U -#define CMU_PULMCR_MODE_POSE 9U -#define CMU_PULMCR_MODE_MSK BITS(CMU_PULMCR_MODE_POSS,CMU_PULMCR_MODE_POSE) - -#define CMU_PULMCR_CLKS_POS 1U -#define CMU_PULMCR_CLKS_MSK BIT(CMU_PULMCR_CLKS_POS) - -#define CMU_PULMCR_EN_POS 0U -#define CMU_PULMCR_EN_MSK BIT(CMU_PULMCR_EN_POS) - -/****************** Bit definition for CMU_CLKOCR register ************************/ - -#define CMU_CLKOCR_LSCOS_POSS 24U -#define CMU_CLKOCR_LSCOS_POSE 26U -#define CMU_CLKOCR_LSCOS_MSK BITS(CMU_CLKOCR_LSCOS_POSS,CMU_CLKOCR_LSCOS_POSE) - -#define CMU_CLKOCR_LSCOEN_POS 16U -#define CMU_CLKOCR_LSCOEN_MSK BIT(CMU_CLKOCR_LSCOEN_POS) - -#define CMU_CLKOCR_HSCODIV_POSS 12U -#define CMU_CLKOCR_HSCODIV_POSE 14U -#define CMU_CLKOCR_HSCODIV_MSK BITS(CMU_CLKOCR_HSCODIV_POSS,CMU_CLKOCR_HSCODIV_POSE) - -#define CMU_CLKOCR_HSCOS_POSS 8U -#define CMU_CLKOCR_HSCOS_POSE 10U -#define CMU_CLKOCR_HSCOS_MSK BITS(CMU_CLKOCR_HSCOS_POSS,CMU_CLKOCR_HSCOS_POSE) - -#define CMU_CLKOCR_HSCOEN_POS 0U -#define CMU_CLKOCR_HSCOEN_MSK BIT(CMU_CLKOCR_HSCOEN_POS) - -/****************** Bit definition for CMU_BUZZCR register ************************/ - -#define CMU_BUZZCR_DAT_POSS 16U -#define CMU_BUZZCR_DAT_POSE 31U -#define CMU_BUZZCR_DAT_MSK BITS(CMU_BUZZCR_DAT_POSS,CMU_BUZZCR_DAT_POSE) - -#define CMU_BUZZCR_DIV_POSS 8U -#define CMU_BUZZCR_DIV_POSE 10U -#define CMU_BUZZCR_DIV_MSK BITS(CMU_BUZZCR_DIV_POSS,CMU_BUZZCR_DIV_POSE) - -#define CMU_BUZZCR_EN_POS 0U -#define CMU_BUZZCR_EN_MSK BIT(CMU_BUZZCR_EN_POS) - -/****************** Bit definition for CMU_AHB1ENR register ************************/ - -#define CMU_AHB1ENR_PISEN_POS 5U -#define CMU_AHB1ENR_PISEN_MSK BIT(CMU_AHB1ENR_PISEN_POS) - -#define CMU_AHB1ENR_TRNGEN_POS 4U -#define CMU_AHB1ENR_TRNGEN_MSK BIT(CMU_AHB1ENR_TRNGEN_POS) - -#define CMU_AHB1ENR_CRYPTEN_POS 3U -#define CMU_AHB1ENR_CRYPTEN_MSK BIT(CMU_AHB1ENR_CRYPTEN_POS) - -#define CMU_AHB1ENR_CALCEN_POS 2U -#define CMU_AHB1ENR_CALCEN_MSK BIT(CMU_AHB1ENR_CALCEN_POS) - -#define CMU_AHB1ENR_CRCEN_POS 1U -#define CMU_AHB1ENR_CRCEN_MSK BIT(CMU_AHB1ENR_CRCEN_POS) - -#define CMU_AHB1ENR_GPIOEN_POS 0U -#define CMU_AHB1ENR_GPIOEN_MSK BIT(CMU_AHB1ENR_GPIOEN_POS) - -/****************** Bit definition for CMU_APB1ENR register ************************/ - -#define CMU_APB1ENR_CAN0EN_POS 24U -#define CMU_APB1ENR_CAN0EN_MSK BIT(CMU_APB1ENR_CAN0EN_POS) - -#define CMU_APB1ENR_I2C1EN_POS 21U -#define CMU_APB1ENR_I2C1EN_MSK BIT(CMU_APB1ENR_I2C1EN_POS) - -#define CMU_APB1ENR_I2C0EN_POS 20U -#define CMU_APB1ENR_I2C0EN_MSK BIT(CMU_APB1ENR_I2C0EN_POS) - -#define CMU_APB1ENR_SPI2EN_POS 18U -#define CMU_APB1ENR_SPI2EN_MSK BIT(CMU_APB1ENR_SPI2EN_POS) - -#define CMU_APB1ENR_SPI1EN_POS 17U -#define CMU_APB1ENR_SPI1EN_MSK BIT(CMU_APB1ENR_SPI1EN_POS) - -#define CMU_APB1ENR_SPI0EN_POS 16U -#define CMU_APB1ENR_SPI0EN_MSK BIT(CMU_APB1ENR_SPI0EN_POS) - -#define CMU_APB1ENR_USART1EN_POS 13U -#define CMU_APB1ENR_USART1EN_MSK BIT(CMU_APB1ENR_USART1EN_POS) - -#define CMU_APB1ENR_USART0EN_POS 12U -#define CMU_APB1ENR_USART0EN_MSK BIT(CMU_APB1ENR_USART0EN_POS) - -#define CMU_APB1ENR_UART3EN_POS 11U -#define CMU_APB1ENR_UART3EN_MSK BIT(CMU_APB1ENR_UART3EN_POS) - -#define CMU_APB1ENR_UART2EN_POS 10U -#define CMU_APB1ENR_UART2EN_MSK BIT(CMU_APB1ENR_UART2EN_POS) - -#define CMU_APB1ENR_UART1EN_POS 9U -#define CMU_APB1ENR_UART1EN_MSK BIT(CMU_APB1ENR_UART1EN_POS) - -#define CMU_APB1ENR_UART0EN_POS 8U -#define CMU_APB1ENR_UART0EN_MSK BIT(CMU_APB1ENR_UART0EN_POS) - -#define CMU_APB1ENR_TIM7EN_POS 7U -#define CMU_APB1ENR_TIM7EN_MSK BIT(CMU_APB1ENR_TIM7EN_POS) - -#define CMU_APB1ENR_TIM6EN_POS 6U -#define CMU_APB1ENR_TIM6EN_MSK BIT(CMU_APB1ENR_TIM6EN_POS) - -#define CMU_APB1ENR_TIM5EN_POS 5U -#define CMU_APB1ENR_TIM5EN_MSK BIT(CMU_APB1ENR_TIM5EN_POS) - -#define CMU_APB1ENR_TIM4EN_POS 4U -#define CMU_APB1ENR_TIM4EN_MSK BIT(CMU_APB1ENR_TIM4EN_POS) - -#define CMU_APB1ENR_TIM3EN_POS 3U -#define CMU_APB1ENR_TIM3EN_MSK BIT(CMU_APB1ENR_TIM3EN_POS) - -#define CMU_APB1ENR_TIM2EN_POS 2U -#define CMU_APB1ENR_TIM2EN_MSK BIT(CMU_APB1ENR_TIM2EN_POS) - -#define CMU_APB1ENR_TIM1EN_POS 1U -#define CMU_APB1ENR_TIM1EN_MSK BIT(CMU_APB1ENR_TIM1EN_POS) - -#define CMU_APB1ENR_TIM0EN_POS 0U -#define CMU_APB1ENR_TIM0EN_MSK BIT(CMU_APB1ENR_TIM0EN_POS) - -/****************** Bit definition for CMU_APB2ENR register ************************/ - -#define CMU_APB2ENR_DBGCEN_POS 19U -#define CMU_APB2ENR_DBGCEN_MSK BIT(CMU_APB2ENR_DBGCEN_POS) - -#define CMU_APB2ENR_BKPCEN_POS 17U -#define CMU_APB2ENR_BKPCEN_MSK BIT(CMU_APB2ENR_BKPCEN_POS) - -#define CMU_APB2ENR_TSENSEEN_POS 16U -#define CMU_APB2ENR_TSENSEEN_MSK BIT(CMU_APB2ENR_TSENSEEN_POS) - -#define CMU_APB2ENR_RTCEN_POS 15U -#define CMU_APB2ENR_RTCEN_MSK BIT(CMU_APB2ENR_RTCEN_POS) - -#define CMU_APB2ENR_IWDTEN_POS 14U -#define CMU_APB2ENR_IWDTEN_MSK BIT(CMU_APB2ENR_IWDTEN_POS) - -#define CMU_APB2ENR_LCDEN_POS 13U -#define CMU_APB2ENR_LCDEN_MSK BIT(CMU_APB2ENR_LCDEN_POS) - -#define CMU_APB2ENR_WWDTEN_POS 12U -#define CMU_APB2ENR_WWDTEN_MSK BIT(CMU_APB2ENR_WWDTEN_POS) - -#define CMU_APB2ENR_OPAMPEN_POS 8U -#define CMU_APB2ENR_OPAMPEN_MSK BIT(CMU_APB2ENR_OPAMPEN_POS) - -#define CMU_APB2ENR_ACMP1EN_POS 7U -#define CMU_APB2ENR_ACMP1EN_MSK BIT(CMU_APB2ENR_ACMP1EN_POS) - -#define CMU_APB2ENR_ACMP0EN_POS 6U -#define CMU_APB2ENR_ACMP0EN_MSK BIT(CMU_APB2ENR_ACMP0EN_POS) - -#define CMU_APB2ENR_ADC0EN_POS 4U -#define CMU_APB2ENR_ADC0EN_MSK BIT(CMU_APB2ENR_ADC0EN_POS) - -#define CMU_APB2ENR_LPUART0EN_POS 2U -#define CMU_APB2ENR_LPUART0EN_MSK BIT(CMU_APB2ENR_LPUART0EN_POS) - -#define CMU_APB2ENR_LPTIM0EN_POS 0U -#define CMU_APB2ENR_LPTIM0EN_MSK BIT(CMU_APB2ENR_LPTIM0EN_POS) - -/****************** Bit definition for CMU_LPENR register ************************/ - -#define CMU_LPENR_HOSCEN_POS 3U -#define CMU_LPENR_HOSCEN_MSK BIT(CMU_LPENR_HOSCEN_POS) - -#define CMU_LPENR_HRCEN_POS 2U -#define CMU_LPENR_HRCEN_MSK BIT(CMU_LPENR_HRCEN_POS) - -#define CMU_LPENR_LOSCEN_POS 1U -#define CMU_LPENR_LOSCEN_MSK BIT(CMU_LPENR_LOSCEN_POS) - -#define CMU_LPENR_LRCEN_POS 0U -#define CMU_LPENR_LRCEN_MSK BIT(CMU_LPENR_LRCEN_POS) - -/****************** Bit definition for CMU_PERICR register ************************/ - -#define CMU_PERICR_LCD_POSS 16U -#define CMU_PERICR_LCD_POSE 18U -#define CMU_PERICR_LCD_MSK BITS(CMU_PERICR_LCD_POSS,CMU_PERICR_LCD_POSE) - -#define CMU_PERICR_LPUART0_POSS 8U -#define CMU_PERICR_LPUART0_POSE 11U -#define CMU_PERICR_LPUART0_MSK BITS(CMU_PERICR_LPUART0_POSS,CMU_PERICR_LPUART0_POSE) - -#define CMU_PERICR_LPTIM0_POSS 0U -#define CMU_PERICR_LPTIM0_POSE 3U -#define CMU_PERICR_LPTIM0_MSK BITS(CMU_PERICR_LPTIM0_POSS,CMU_PERICR_LPTIM0_POSE) - -/****************** Bit definition for CMU_HRCACR register ************************/ - -#define CMU_HRCACR_IB_POSS 28U -#define CMU_HRCACR_IB_POSE 29U -#define CMU_HRCACR_IB_MSK BITS(CMU_HRCACR_IB_POSS,CMU_HRCACR_IB_POSE) - -#define CMU_HRCACR_CAP_POSS 26U -#define CMU_HRCACR_CAP_POSE 27U -#define CMU_HRCACR_CAP_MSK BITS(CMU_HRCACR_CAP_POSS,CMU_HRCACR_CAP_POSE) - -#define CMU_HRCACR_CAL_POSS 16U -#define CMU_HRCACR_CAL_POSE 25U -#define CMU_HRCACR_CAL_MSK BITS(CMU_HRCACR_CAL_POSS,CMU_HRCACR_CAL_POSE) - -#define CMU_HRCACR_IBSET_POSS 14U -#define CMU_HRCACR_IBSET_POSE 15U -#define CMU_HRCACR_IBSET_MSK BITS(CMU_HRCACR_IBSET_POSS,CMU_HRCACR_IBSET_POSE) - -#define CMU_HRCACR_CAPSET_POSS 12U -#define CMU_HRCACR_CAPSET_POSE 13U -#define CMU_HRCACR_CAPSET_MSK BITS(CMU_HRCACR_CAPSET_POSS,CMU_HRCACR_CAPSET_POSE) - -#define CMU_HRCACR_STA_POSS 9U -#define CMU_HRCACR_STA_POSE 10U -#define CMU_HRCACR_STA_MSK BITS(CMU_HRCACR_STA_POSS,CMU_HRCACR_STA_POSE) - -#define CMU_HRCACR_BUSY_POS 8U -#define CMU_HRCACR_BUSY_MSK BIT(CMU_HRCACR_BUSY_POS) - -#define CMU_HRCACR_WRTRG_POS 7U -#define CMU_HRCACR_WRTRG_MSK BIT(CMU_HRCACR_WRTRG_POS) - -#define CMU_HRCACR_AC_POSS 4U -#define CMU_HRCACR_AC_POSE 6U -#define CMU_HRCACR_AC_MSK BITS(CMU_HRCACR_AC_POSS,CMU_HRCACR_AC_POSE) - -#define CMU_HRCACR_IBS_POS 3U -#define CMU_HRCACR_IBS_MSK BIT(CMU_HRCACR_IBS_POS) - -#define CMU_HRCACR_RFSEL_POS 2U -#define CMU_HRCACR_RFSEL_MSK BIT(CMU_HRCACR_RFSEL_POS) - -#define CMU_HRCACR_FREQ_POS 1U -#define CMU_HRCACR_FREQ_MSK BIT(CMU_HRCACR_FREQ_POS) - -#define CMU_HRCACR_EN_POS 0U -#define CMU_HRCACR_EN_MSK BIT(CMU_HRCACR_EN_POS) - -typedef struct -{ - __O uint32_t CSR; - __IO uint32_t CFGR; - uint32_t RESERVED0[2] ; - __IO uint32_t CLKENR; - __I uint32_t CLKSR; - __IO uint32_t PLLCFG; - __IO uint32_t HOSCCFG; - __IO uint32_t HOSMCR; - __IO uint32_t LOSMCR; - __IO uint32_t PULMCR; - uint32_t RESERVED1 ; - __IO uint32_t CLKOCR; - __IO uint32_t BUZZCR; - uint32_t RESERVED2[2] ; - __IO uint32_t AHB1ENR; - uint32_t RESERVED3[3] ; - __IO uint32_t APB1ENR; - __IO uint32_t APB2ENR; - uint32_t RESERVED4[2] ; - __IO uint32_t LPENR; - uint32_t RESERVED5[7] ; - __IO uint32_t PERICR; - uint32_t RESERVED6[3] ; - __IO uint32_t HRCACR; -} CMU_TypeDef; - -/****************** Bit definition for DMA_STATUS register ************************/ - -#define DMA_STATUS_STATUS_POSS 4U -#define DMA_STATUS_STATUS_POSE 7U -#define DMA_STATUS_STATUS_MSK BITS(DMA_STATUS_STATUS_POSS,DMA_STATUS_STATUS_POSE) - -#define DMA_STATUS_MASTER_ENABLE_POS 0U -#define DMA_STATUS_MASTER_ENABLE_MSK BIT(DMA_STATUS_MASTER_ENABLE_POS) - -/****************** Bit definition for DMA_CFG register ************************/ - -#define DMA_CFG_CHNL_PROT_CTRL_POSS 5U -#define DMA_CFG_CHNL_PROT_CTRL_POSE 7U -#define DMA_CFG_CHNL_PROT_CTRL_MSK BITS(DMA_CFG_CHNL_PROT_CTRL_POSS,DMA_CFG_CHNL_PROT_CTRL_POSE) - -#define DMA_CFG_MASTER_ENABLE_POS 0U -#define DMA_CFG_MASTER_ENABLE_MSK BIT(DMA_CFG_MASTER_ENABLE_POS) - -/****************** Bit definition for DMA_CTRLBASE register ************************/ - -#define DMA_CTRLBASE_CTRL_BASE_PTR_POSS 9U -#define DMA_CTRLBASE_CTRL_BASE_PTR_POSE 31U -#define DMA_CTRLBASE_CTRL_BASE_PTR_MSK BITS(DMA_CTRLBASE_CTRL_BASE_PTR_POSS,DMA_CTRLBASE_CTRL_BASE_PTR_POSE) - -/****************** Bit definition for DMA_ALTCTRLBASE register ************************/ - -#define DMA_ALTCTRLBASE_ALT_CTRL_BASE_PTR_POSS 0U -#define DMA_ALTCTRLBASE_ALT_CTRL_BASE_PTR_POSE 31U -#define DMA_ALTCTRLBASE_ALT_CTRL_BASE_PTR_MSK BITS(DMA_ALTCTRLBASE_ALT_CTRL_BASE_PTR_POSS,DMA_ALTCTRLBASE_ALT_CTRL_BASE_PTR_POSE) - -/****************** Bit definition for DMA_CHWAITSTATUS register ************************/ - -#define DMA_CHWAITSTATUS_DMA_WAITONREQ_STATUS_POSS 0U -#define DMA_CHWAITSTATUS_DMA_WAITONREQ_STATUS_POSE 31U -#define DMA_CHWAITSTATUS_DMA_WAITONREQ_STATUS_MSK BITS(DMA_CHWAITSTATUS_DMA_WAITONREQ_STATUS_POSS,DMA_CHWAITSTATUS_DMA_WAITONREQ_STATUS_POSE) - -/****************** Bit definition for DMA_CHSWREQ register ************************/ - -#define DMA_CHSWREQ_CHSWREQ_POSS 0U -#define DMA_CHSWREQ_CHSWREQ_POSE 31U -#define DMA_CHSWREQ_CHSWREQ_MSK BITS(DMA_CHSWREQ_CHSWREQ_POSS,DMA_CHSWREQ_CHSWREQ_POSE) - -/****************** Bit definition for DMA_CHUSEBURSTSET register ************************/ - -#define DMA_CHUSEBURSTSET_CHNL_USEBURST_SET_POSS 0U -#define DMA_CHUSEBURSTSET_CHNL_USEBURST_SET_POSE 31U -#define DMA_CHUSEBURSTSET_CHNL_USEBURST_SET_MSK BITS(DMA_CHUSEBURSTSET_CHNL_USEBURST_SET_POSS,DMA_CHUSEBURSTSET_CHNL_USEBURST_SET_POSE) - -/****************** Bit definition for DMA_CHUSEBURSTCLR register ************************/ - -#define DMA_CHUSEBURSTCLR_CHNL_USEBURST_CLR_POSS 0U -#define DMA_CHUSEBURSTCLR_CHNL_USEBURST_CLR_POSE 31U -#define DMA_CHUSEBURSTCLR_CHNL_USEBURST_CLR_MSK BITS(DMA_CHUSEBURSTCLR_CHNL_USEBURST_CLR_POSS,DMA_CHUSEBURSTCLR_CHNL_USEBURST_CLR_POSE) - -/****************** Bit definition for DMA_CHREQMASKSET register ************************/ - -#define DMA_CHREQMASKSET_CHNL_REQ_MASK_SET_POSS 0U -#define DMA_CHREQMASKSET_CHNL_REQ_MASK_SET_POSE 31U -#define DMA_CHREQMASKSET_CHNL_REQ_MASK_SET_MSK BITS(DMA_CHREQMASKSET_CHNL_REQ_MASK_SET_POSS,DMA_CHREQMASKSET_CHNL_REQ_MASK_SET_POSE) - -/****************** Bit definition for DMA_CHREQMASKCLR register ************************/ - -#define DMA_CHREQMASKCLR_CHNL_REQ_MASK_CLR_POSS 0U -#define DMA_CHREQMASKCLR_CHNL_REQ_MASK_CLR_POSE 31U -#define DMA_CHREQMASKCLR_CHNL_REQ_MASK_CLR_MSK BITS(DMA_CHREQMASKCLR_CHNL_REQ_MASK_CLR_POSS,DMA_CHREQMASKCLR_CHNL_REQ_MASK_CLR_POSE) - -/****************** Bit definition for DMA_CHENSET register ************************/ - -#define DMA_CHENSET_CHNL_ENABLE_SET_POSS 0U -#define DMA_CHENSET_CHNL_ENABLE_SET_POSE 31U -#define DMA_CHENSET_CHNL_ENABLE_SET_MSK BITS(DMA_CHENSET_CHNL_ENABLE_SET_POSS,DMA_CHENSET_CHNL_ENABLE_SET_POSE) - -/****************** Bit definition for DMA_CHENCLR register ************************/ - -#define DMA_CHENCLR_CHNL_ENABLE_CLR_POSS 0U -#define DMA_CHENCLR_CHNL_ENABLE_CLR_POSE 31U -#define DMA_CHENCLR_CHNL_ENABLE_CLR_MSK BITS(DMA_CHENCLR_CHNL_ENABLE_CLR_POSS,DMA_CHENCLR_CHNL_ENABLE_CLR_POSE) - -/****************** Bit definition for DMA_CHPRIALTSET register ************************/ - -#define DMA_CHPRIALTSET_CHNL_PRI_ALT_SET_POSS 0U -#define DMA_CHPRIALTSET_CHNL_PRI_ALT_SET_POSE 31U -#define DMA_CHPRIALTSET_CHNL_PRI_ALT_SET_MSK BITS(DMA_CHPRIALTSET_CHNL_PRI_ALT_SET_POSS,DMA_CHPRIALTSET_CHNL_PRI_ALT_SET_POSE) - -/****************** Bit definition for DMA_CHPRIALTCLR register ************************/ - -#define DMA_CHPRIALTCLR_CHNL_PRI_ALT_CLR_POSS 0U -#define DMA_CHPRIALTCLR_CHNL_PRI_ALT_CLR_POSE 31U -#define DMA_CHPRIALTCLR_CHNL_PRI_ALT_CLR_MSK BITS(DMA_CHPRIALTCLR_CHNL_PRI_ALT_CLR_POSS,DMA_CHPRIALTCLR_CHNL_PRI_ALT_CLR_POSE) - -/****************** Bit definition for DMA_CHPRSET register ************************/ - -#define DMA_CHPRSET_CHNL_PRIORITY_SET_POSS 0U -#define DMA_CHPRSET_CHNL_PRIORITY_SET_POSE 31U -#define DMA_CHPRSET_CHNL_PRIORITY_SET_MSK BITS(DMA_CHPRSET_CHNL_PRIORITY_SET_POSS,DMA_CHPRSET_CHNL_PRIORITY_SET_POSE) - -/****************** Bit definition for DMA_CHPRCLR register ************************/ - -#define DMA_CHPRCLR_CHNL_PRIORITY_CLR_POSS 0U -#define DMA_CHPRCLR_CHNL_PRIORITY_CLR_POSE 31U -#define DMA_CHPRCLR_CHNL_PRIORITY_CLR_MSK BITS(DMA_CHPRCLR_CHNL_PRIORITY_CLR_POSS,DMA_CHPRCLR_CHNL_PRIORITY_CLR_POSE) - -/****************** Bit definition for DMA_ERRCLR register ************************/ - -#define DMA_ERRCLR_ERR_CLR_POS 0U -#define DMA_ERRCLR_ERR_CLR_MSK BIT(DMA_ERRCLR_ERR_CLR_POS) - -/****************** Bit definition for DMA_IFLAG register ************************/ - -#define DMA_IFLAG_DMAERRIF_POS 31U -#define DMA_IFLAG_DMAERRIF_MSK BIT(DMA_IFLAG_DMAERRIF_POS) - -#define DMA_IFLAG_CH5DONEIF_POS 5U -#define DMA_IFLAG_CH5DONEIF_MSK BIT(DMA_IFLAG_CH5DONEIF_POS) - -#define DMA_IFLAG_CH4DONEIF_POS 4U -#define DMA_IFLAG_CH4DONEIF_MSK BIT(DMA_IFLAG_CH4DONEIF_POS) - -#define DMA_IFLAG_CH3DONEIF_POS 3U -#define DMA_IFLAG_CH3DONEIF_MSK BIT(DMA_IFLAG_CH3DONEIF_POS) - -#define DMA_IFLAG_CH2DONEIF_POS 2U -#define DMA_IFLAG_CH2DONEIF_MSK BIT(DMA_IFLAG_CH2DONEIF_POS) - -#define DMA_IFLAG_CH1DONEIF_POS 1U -#define DMA_IFLAG_CH1DONEIF_MSK BIT(DMA_IFLAG_CH1DONEIF_POS) - -#define DMA_IFLAG_CH0DONEIF_POS 0U -#define DMA_IFLAG_CH0DONEIF_MSK BIT(DMA_IFLAG_CH0DONEIF_POS) - -/****************** Bit definition for DMA_ICFR register ************************/ - -#define DMA_ICFR_DMAERRC_POS 31U -#define DMA_ICFR_DMAERRC_MSK BIT(DMA_ICFR_DMAERRC_POS) - -#define DMA_ICFR_CH5DONEC_POS 5U -#define DMA_ICFR_CH5DONEC_MSK BIT(DMA_ICFR_CH5DONEC_POS) - -#define DMA_ICFR_CH4DONEC_POS 4U -#define DMA_ICFR_CH4DONEC_MSK BIT(DMA_ICFR_CH4DONEC_POS) - -#define DMA_ICFR_CH3DONEC_POS 3U -#define DMA_ICFR_CH3DONEC_MSK BIT(DMA_ICFR_CH3DONEC_POS) - -#define DMA_ICFR_CH2DONEC_POS 2U -#define DMA_ICFR_CH2DONEC_MSK BIT(DMA_ICFR_CH2DONEC_POS) - -#define DMA_ICFR_CH1DONEC_POS 1U -#define DMA_ICFR_CH1DONEC_MSK BIT(DMA_ICFR_CH1DONEC_POS) - -#define DMA_ICFR_CH0DONEC_POS 0U -#define DMA_ICFR_CH0DONEC_MSK BIT(DMA_ICFR_CH0DONEC_POS) - -/****************** Bit definition for DMA_IER register ************************/ - -#define DMA_IER_DMAERRIE_POS 31U -#define DMA_IER_DMAERRIE_MSK BIT(DMA_IER_DMAERRIE_POS) - -#define DMA_IER_CH5DONEIE_POS 5U -#define DMA_IER_CH5DONEIE_MSK BIT(DMA_IER_CH5DONEIE_POS) - -#define DMA_IER_CH4DONEIE_POS 4U -#define DMA_IER_CH4DONEIE_MSK BIT(DMA_IER_CH4DONEIE_POS) - -#define DMA_IER_CH3DONEIE_POS 3U -#define DMA_IER_CH3DONEIE_MSK BIT(DMA_IER_CH3DONEIE_POS) - -#define DMA_IER_CH2DONEIE_POS 2U -#define DMA_IER_CH2DONEIE_MSK BIT(DMA_IER_CH2DONEIE_POS) - -#define DMA_IER_CH1DONEIE_POS 1U -#define DMA_IER_CH1DONEIE_MSK BIT(DMA_IER_CH1DONEIE_POS) - -#define DMA_IER_CH0DONEIE_POS 0U -#define DMA_IER_CH0DONEIE_MSK BIT(DMA_IER_CH0DONEIE_POS) - -/****************** Bit definition for DMA_CH0_SELCON register ************************/ - -#define DMA_CH0_SELCON_MSEL_POSS 8U -#define DMA_CH0_SELCON_MSEL_POSE 13U -#define DMA_CH0_SELCON_MSEL_MSK BITS(DMA_CH0_SELCON_MSEL_POSS,DMA_CH0_SELCON_MSEL_POSE) - -#define DMA_CH0_SELCON_MSIGSEL_POSS 0U -#define DMA_CH0_SELCON_MSIGSEL_POSE 3U -#define DMA_CH0_SELCON_MSIGSEL_MSK BITS(DMA_CH0_SELCON_MSIGSEL_POSS,DMA_CH0_SELCON_MSIGSEL_POSE) - -typedef struct -{ - __I uint32_t STATUS; - __IO uint32_t CFG; - __IO uint32_t CTRLBASE; - __I uint32_t ALTCTRLBASE; - __I uint32_t CHWAITSTATUS; - __IO uint32_t CHSWREQ; - __IO uint32_t CHUSEBURSTSET; - __O uint32_t CHUSEBURSTCLR; - __IO uint32_t CHREQMASKSET; - __O uint32_t CHREQMASKCLR; - __IO uint32_t CHENSET; - __O uint32_t CHENCLR; - __IO uint32_t CHPRIALTSET; - __O uint32_t CHPRIALTCLR; - __IO uint32_t CHPRSET; - __O uint32_t CHPRCLR; - uint32_t RESERVED0[3] ; - __IO uint32_t ERRCLR; - uint32_t RESERVED1[1004] ; - __I uint32_t IFLAG; - uint32_t RESERVED2 ; - __O uint32_t ICFR; - __IO uint32_t IER; - uint32_t RESERVED3[60] ; - __IO uint32_t CH_SELCON[6]; -} DMA_TypeDef; - -/****************** Bit definition for PIS_CH0_CON register ************************/ - -#define PIS_CH0_CON_SYNCSEL_POSS 24U -#define PIS_CH0_CON_SYNCSEL_POSE 26U -#define PIS_CH0_CON_SYNCSEL_MSK BITS(PIS_CH0_CON_SYNCSEL_POSS,PIS_CH0_CON_SYNCSEL_POSE) - -#define PIS_CH0_CON_PULCK_POSS 18U -#define PIS_CH0_CON_PULCK_POSE 19U -#define PIS_CH0_CON_PULCK_MSK BITS(PIS_CH0_CON_PULCK_POSS,PIS_CH0_CON_PULCK_POSE) - -#define PIS_CH0_CON_EDGS_POSS 16U -#define PIS_CH0_CON_EDGS_POSE 17U -#define PIS_CH0_CON_EDGS_MSK BITS(PIS_CH0_CON_EDGS_POSS,PIS_CH0_CON_EDGS_POSE) - -#define PIS_CH0_CON_SRCS_POSS 8U -#define PIS_CH0_CON_SRCS_POSE 13U -#define PIS_CH0_CON_SRCS_MSK BITS(PIS_CH0_CON_SRCS_POSS,PIS_CH0_CON_SRCS_POSE) - -#define PIS_CH0_CON_MSIGS_POSS 0U -#define PIS_CH0_CON_MSIGS_POSE 3U -#define PIS_CH0_CON_MSIGS_MSK BITS(PIS_CH0_CON_MSIGS_POSS,PIS_CH0_CON_MSIGS_POSE) - -/****************** Bit definition for PIS_CH_OER register ************************/ - -#define PIS_CH_OER_CH3OE_POS 3U -#define PIS_CH_OER_CH3OE_MSK BIT(PIS_CH_OER_CH3OE_POS) - -#define PIS_CH_OER_CH2OE_POS 2U -#define PIS_CH_OER_CH2OE_MSK BIT(PIS_CH_OER_CH2OE_POS) - -#define PIS_CH_OER_CH1OE_POS 1U -#define PIS_CH_OER_CH1OE_MSK BIT(PIS_CH_OER_CH1OE_POS) - -#define PIS_CH_OER_CH0OE_POS 0U -#define PIS_CH_OER_CH0OE_MSK BIT(PIS_CH_OER_CH0OE_POS) - -/****************** Bit definition for PIS_TAR_CON0 register ************************/ - -#define PIS_TAR_CON0_TIM3_CH2IN_SEL_POS 25U -#define PIS_TAR_CON0_TIM3_CH2IN_SEL_MSK BIT(PIS_TAR_CON0_TIM3_CH2IN_SEL_POS) - -#define PIS_TAR_CON0_TIM3_CH1IN_SEL_POS 24U -#define PIS_TAR_CON0_TIM3_CH1IN_SEL_MSK BIT(PIS_TAR_CON0_TIM3_CH1IN_SEL_POS) - -#define PIS_TAR_CON0_TIM2_CH2IN_SEL_POS 17U -#define PIS_TAR_CON0_TIM2_CH2IN_SEL_MSK BIT(PIS_TAR_CON0_TIM2_CH2IN_SEL_POS) - -#define PIS_TAR_CON0_TIM2_CH1IN_SEL_POS 16U -#define PIS_TAR_CON0_TIM2_CH1IN_SEL_MSK BIT(PIS_TAR_CON0_TIM2_CH1IN_SEL_POS) - -#define PIS_TAR_CON0_TIM0_BRKIN_SEL_POS 4U -#define PIS_TAR_CON0_TIM0_BRKIN_SEL_MSK BIT(PIS_TAR_CON0_TIM0_BRKIN_SEL_POS) - -#define PIS_TAR_CON0_TIM0_CH4IN_SEL_POS 3U -#define PIS_TAR_CON0_TIM0_CH4IN_SEL_MSK BIT(PIS_TAR_CON0_TIM0_CH4IN_SEL_POS) - -#define PIS_TAR_CON0_TIM0_CH3IN_SEL_POS 2U -#define PIS_TAR_CON0_TIM0_CH3IN_SEL_MSK BIT(PIS_TAR_CON0_TIM0_CH3IN_SEL_POS) - -#define PIS_TAR_CON0_TIM0_CH2IN_SEL_POS 1U -#define PIS_TAR_CON0_TIM0_CH2IN_SEL_MSK BIT(PIS_TAR_CON0_TIM0_CH2IN_SEL_POS) - -#define PIS_TAR_CON0_TIM0_CH1IN_SEL_POS 0U -#define PIS_TAR_CON0_TIM0_CH1IN_SEL_MSK BIT(PIS_TAR_CON0_TIM0_CH1IN_SEL_POS) - -/****************** Bit definition for PIS_TAR_CON1 register ************************/ - -#define PIS_TAR_CON1_SPI1_CLK_SEL_POS 15U -#define PIS_TAR_CON1_SPI1_CLK_SEL_MSK BIT(PIS_TAR_CON1_SPI1_CLK_SEL_POS) - -#define PIS_TAR_CON1_SPI1_RX_SEL_POS 14U -#define PIS_TAR_CON1_SPI1_RX_SEL_MSK BIT(PIS_TAR_CON1_SPI1_RX_SEL_POS) - -#define PIS_TAR_CON1_SPI0_CLK_SEL_POS 13U -#define PIS_TAR_CON1_SPI0_CLK_SEL_MSK BIT(PIS_TAR_CON1_SPI0_CLK_SEL_POS) - -#define PIS_TAR_CON1_SPI0_RX_SEL_POS 12U -#define PIS_TAR_CON1_SPI0_RX_SEL_MSK BIT(PIS_TAR_CON1_SPI0_RX_SEL_POS) - -#define PIS_TAR_CON1_LPUART0_RXD_SEL_POS 8U -#define PIS_TAR_CON1_LPUART0_RXD_SEL_MSK BIT(PIS_TAR_CON1_LPUART0_RXD_SEL_POS) - -#define PIS_TAR_CON1_USART1_RXD_SEL_POS 7U -#define PIS_TAR_CON1_USART1_RXD_SEL_MSK BIT(PIS_TAR_CON1_USART1_RXD_SEL_POS) - -#define PIS_TAR_CON1_USART0_RXD_SEL_POS 6U -#define PIS_TAR_CON1_USART0_RXD_SEL_MSK BIT(PIS_TAR_CON1_USART0_RXD_SEL_POS) - -#define PIS_TAR_CON1_UART3_RXD_SEL_POS 3U -#define PIS_TAR_CON1_UART3_RXD_SEL_MSK BIT(PIS_TAR_CON1_UART3_RXD_SEL_POS) - -#define PIS_TAR_CON1_UART2_RXD_SEL_POS 2U -#define PIS_TAR_CON1_UART2_RXD_SEL_MSK BIT(PIS_TAR_CON1_UART2_RXD_SEL_POS) - -#define PIS_TAR_CON1_UART1_RXD_SEL_POS 1U -#define PIS_TAR_CON1_UART1_RXD_SEL_MSK BIT(PIS_TAR_CON1_UART1_RXD_SEL_POS) - -#define PIS_TAR_CON1_UART0_RXD_SEL_POS 0U -#define PIS_TAR_CON1_UART0_RXD_SEL_MSK BIT(PIS_TAR_CON1_UART0_RXD_SEL_POS) - -/****************** Bit definition for PIS_TXMCR register ************************/ - -#define PIS_TXMCR_TXMLVLS_POS 8U -#define PIS_TXMCR_TXMLVLS_MSK BIT(PIS_TXMCR_TXMLVLS_POS) - -#define PIS_TXMCR_TXMSS_POSS 4U -#define PIS_TXMCR_TXMSS_POSE 7U -#define PIS_TXMCR_TXMSS_MSK BITS(PIS_TXMCR_TXMSS_POSS,PIS_TXMCR_TXMSS_POSE) - -#define PIS_TXMCR_TXSIGS_POSS 0U -#define PIS_TXMCR_TXSIGS_POSE 3U -#define PIS_TXMCR_TXSIGS_MSK BITS(PIS_TXMCR_TXSIGS_POSS,PIS_TXMCR_TXSIGS_POSE) - -typedef struct -{ - __IO uint32_t CH_CON[8]; - uint32_t RESERVED0[8] ; - __IO uint32_t CH_OER; - __IO uint32_t TAR_CON0; - __IO uint32_t TAR_CON1; - uint32_t RESERVED1[5] ; - __IO uint32_t UART0_TXMCR; - __IO uint32_t UART1_TXMCR; - __IO uint32_t UART2_TXMCR; - __IO uint32_t UART3_TXMCR; - __IO uint32_t LPUART0_TXMCR; -} PIS_TypeDef; - -/****************** Bit definition for GPIO_DIN register ************************/ - -#define GPIO_DIN_DIN_POSS 0U -#define GPIO_DIN_DIN_POSE 15U -#define GPIO_DIN_DIN_MSK BITS(GPIO_DIN_DIN_POSS,GPIO_DIN_DIN_POSE) - -/****************** Bit definition for GPIO_DOUT register ************************/ - -#define GPIO_DOUT_DOUT_POSS 0U -#define GPIO_DOUT_DOUT_POSE 15U -#define GPIO_DOUT_DOUT_MSK BITS(GPIO_DOUT_DOUT_POSS,GPIO_DOUT_DOUT_POSE) - -/****************** Bit definition for GPIO_BSRR register ************************/ - -#define GPIO_BSRR_BRR_POSS 16U -#define GPIO_BSRR_BRR_POSE 31U -#define GPIO_BSRR_BRR_MSK BITS(GPIO_BSRR_BRR_POSS,GPIO_BSRR_BRR_POSE) - -#define GPIO_BSRR_BSR_POSS 0U -#define GPIO_BSRR_BSR_POSE 15U -#define GPIO_BSRR_BSR_MSK BITS(GPIO_BSRR_BSR_POSS,GPIO_BSRR_BSR_POSE) - -/****************** Bit definition for GPIO_BIR register ************************/ - -#define GPIO_BIR_BIR_POSS 0U -#define GPIO_BIR_BIR_POSE 15U -#define GPIO_BIR_BIR_MSK BITS(GPIO_BIR_BIR_POSS,GPIO_BIR_BIR_POSE) - -/****************** Bit definition for GPIO_MODE register ************************/ - -#define GPIO_MODE_MODE_POSS 0U -#define GPIO_MODE_MODE_POSE 31U -#define GPIO_MODE_MODE_MSK BITS(GPIO_MODE_MODE_POSS,GPIO_MODE_MODE_POSE) - -/****************** Bit definition for GPIO_ODOS register ************************/ - -#define GPIO_ODOS_ODOS_POSS 0U -#define GPIO_ODOS_ODOS_POSE 31U -#define GPIO_ODOS_ODOS_MSK BITS(GPIO_ODOS_ODOS_POSS,GPIO_ODOS_ODOS_POSE) - -/****************** Bit definition for GPIO_PUPD register ************************/ - -#define GPIO_PUPD_PUPD_POSS 0U -#define GPIO_PUPD_PUPD_POSE 31U -#define GPIO_PUPD_PUPD_MSK BITS(GPIO_PUPD_PUPD_POSS,GPIO_PUPD_PUPD_POSE) - -/****************** Bit definition for GPIO_ODRV register ************************/ - -#define GPIO_ODRV_ODRV_POSS 0U -#define GPIO_ODRV_ODRV_POSE 31U -#define GPIO_ODRV_ODRV_MSK BITS(GPIO_ODRV_ODRV_POSS,GPIO_ODRV_ODRV_POSE) - -/****************** Bit definition for GPIO_FLT register ************************/ - -#define GPIO_FLT_FLT_POSS 0U -#define GPIO_FLT_FLT_POSE 15U -#define GPIO_FLT_FLT_MSK BITS(GPIO_FLT_FLT_POSS,GPIO_FLT_FLT_POSE) - -/****************** Bit definition for GPIO_TYPE register ************************/ - -#define GPIO_TYPE_TYPE_POSS 0U -#define GPIO_TYPE_TYPE_POSE 15U -#define GPIO_TYPE_TYPE_MSK BITS(GPIO_TYPE_TYPE_POSS,GPIO_TYPE_TYPE_POSE) - -/****************** Bit definition for GPIO_FUNC0 register ************************/ - -#define GPIO_FUNC0_FSEL_IO7_POSS 28U -#define GPIO_FUNC0_FSEL_IO7_POSE 31U -#define GPIO_FUNC0_FSEL_IO7_MSK BITS(GPIO_FUNC0_FSEL_IO7_POSS,GPIO_FUNC0_FSEL_IO7_POSE) - -#define GPIO_FUNC0_FSEL_IO6_POSS 24U -#define GPIO_FUNC0_FSEL_IO6_POSE 27U -#define GPIO_FUNC0_FSEL_IO6_MSK BITS(GPIO_FUNC0_FSEL_IO6_POSS,GPIO_FUNC0_FSEL_IO6_POSE) - -#define GPIO_FUNC0_FSEL_IO5_POSS 20U -#define GPIO_FUNC0_FSEL_IO5_POSE 23U -#define GPIO_FUNC0_FSEL_IO5_MSK BITS(GPIO_FUNC0_FSEL_IO5_POSS,GPIO_FUNC0_FSEL_IO5_POSE) - -#define GPIO_FUNC0_FSEL_IO4_POSS 16U -#define GPIO_FUNC0_FSEL_IO4_POSE 19U -#define GPIO_FUNC0_FSEL_IO4_MSK BITS(GPIO_FUNC0_FSEL_IO4_POSS,GPIO_FUNC0_FSEL_IO4_POSE) - -#define GPIO_FUNC0_FSEL_IO3_POSS 12U -#define GPIO_FUNC0_FSEL_IO3_POSE 15U -#define GPIO_FUNC0_FSEL_IO3_MSK BITS(GPIO_FUNC0_FSEL_IO3_POSS,GPIO_FUNC0_FSEL_IO3_POSE) - -#define GPIO_FUNC0_FSEL_IO2_POSS 8U -#define GPIO_FUNC0_FSEL_IO2_POSE 11U -#define GPIO_FUNC0_FSEL_IO2_MSK BITS(GPIO_FUNC0_FSEL_IO2_POSS,GPIO_FUNC0_FSEL_IO2_POSE) - -#define GPIO_FUNC0_FSEL_IO1_POSS 4U -#define GPIO_FUNC0_FSEL_IO1_POSE 7U -#define GPIO_FUNC0_FSEL_IO1_MSK BITS(GPIO_FUNC0_FSEL_IO1_POSS,GPIO_FUNC0_FSEL_IO1_POSE) - -#define GPIO_FUNC0_FSEL_IO0_POSS 0U -#define GPIO_FUNC0_FSEL_IO0_POSE 3U -#define GPIO_FUNC0_FSEL_IO0_MSK BITS(GPIO_FUNC0_FSEL_IO0_POSS,GPIO_FUNC0_FSEL_IO0_POSE) - -/****************** Bit definition for GPIO_FUNC1 register ************************/ - -#define GPIO_FUNC1_FSEL_IO15_POSS 28U -#define GPIO_FUNC1_FSEL_IO15_POSE 31U -#define GPIO_FUNC1_FSEL_IO15_MSK BITS(GPIO_FUNC1_FSEL_IO15_POSS,GPIO_FUNC1_FSEL_IO15_POSE) - -#define GPIO_FUNC1_FSEL_IO14_POSS 24U -#define GPIO_FUNC1_FSEL_IO14_POSE 27U -#define GPIO_FUNC1_FSEL_IO14_MSK BITS(GPIO_FUNC1_FSEL_IO14_POSS,GPIO_FUNC1_FSEL_IO14_POSE) - -#define GPIO_FUNC1_FSEL_IO13_POSS 20U -#define GPIO_FUNC1_FSEL_IO13_POSE 23U -#define GPIO_FUNC1_FSEL_IO13_MSK BITS(GPIO_FUNC1_FSEL_IO13_POSS,GPIO_FUNC1_FSEL_IO13_POSE) - -#define GPIO_FUNC1_FSEL_IO12_POSS 16U -#define GPIO_FUNC1_FSEL_IO12_POSE 19U -#define GPIO_FUNC1_FSEL_IO12_MSK BITS(GPIO_FUNC1_FSEL_IO12_POSS,GPIO_FUNC1_FSEL_IO12_POSE) - -#define GPIO_FUNC1_FSEL_IO11_POSS 12U -#define GPIO_FUNC1_FSEL_IO11_POSE 15U -#define GPIO_FUNC1_FSEL_IO11_MSK BITS(GPIO_FUNC1_FSEL_IO11_POSS,GPIO_FUNC1_FSEL_IO11_POSE) - -#define GPIO_FUNC1_FSEL_IO10_POSS 8U -#define GPIO_FUNC1_FSEL_IO10_POSE 11U -#define GPIO_FUNC1_FSEL_IO10_MSK BITS(GPIO_FUNC1_FSEL_IO10_POSS,GPIO_FUNC1_FSEL_IO10_POSE) - -#define GPIO_FUNC1_FSEL_IO9_POSS 4U -#define GPIO_FUNC1_FSEL_IO9_POSE 7U -#define GPIO_FUNC1_FSEL_IO9_MSK BITS(GPIO_FUNC1_FSEL_IO9_POSS,GPIO_FUNC1_FSEL_IO9_POSE) - -#define GPIO_FUNC1_FSEL_IO8_POSS 0U -#define GPIO_FUNC1_FSEL_IO8_POSE 3U -#define GPIO_FUNC1_FSEL_IO8_MSK BITS(GPIO_FUNC1_FSEL_IO8_POSS,GPIO_FUNC1_FSEL_IO8_POSE) - -/****************** Bit definition for GPIO_LOCK register ************************/ - -#define GPIO_LOCK_KEY_POSS 16U -#define GPIO_LOCK_KEY_POSE 31U -#define GPIO_LOCK_KEY_MSK BITS(GPIO_LOCK_KEY_POSS,GPIO_LOCK_KEY_POSE) - -#define GPIO_LOCK_LOCK_POSS 0U -#define GPIO_LOCK_LOCK_POSE 15U -#define GPIO_LOCK_LOCK_MSK BITS(GPIO_LOCK_LOCK_POSS,GPIO_LOCK_LOCK_POSE) - -typedef struct -{ - __I uint32_t DIN; - __IO uint32_t DOUT; - __O uint32_t BSRR; - __O uint32_t BIR; - __IO uint32_t MODE; - __IO uint32_t ODOS; - __IO uint32_t PUPD; - __IO uint32_t ODRV; - __IO uint32_t FLT; - __IO uint32_t TYPE; - __IO uint32_t FUNC0; - __IO uint32_t FUNC1; - __IO uint32_t LOCK; -} GPIO_TypeDef; - -/****************** Bit definition for GPIO_EXTIRER register ************************/ - -#define GPIO_EXTIRER_EXTIRER_POSS 0U -#define GPIO_EXTIRER_EXTIRER_POSE 15U -#define GPIO_EXTIRER_EXTIRER_MSK BITS(GPIO_EXTIRER_EXTIRER_POSS,GPIO_EXTIRER_EXTIRER_POSE) - -/****************** Bit definition for GPIO_EXTIFER register ************************/ - -#define GPIO_EXTIFER_EXTIFER_POSS 0U -#define GPIO_EXTIFER_EXTIFER_POSE 15U -#define GPIO_EXTIFER_EXTIFER_MSK BITS(GPIO_EXTIFER_EXTIFER_POSS,GPIO_EXTIFER_EXTIFER_POSE) - -/****************** Bit definition for GPIO_EXTIEN register ************************/ - -#define GPIO_EXTIEN_EXTIEN_POSS 0U -#define GPIO_EXTIEN_EXTIEN_POSE 15U -#define GPIO_EXTIEN_EXTIEN_MSK BITS(GPIO_EXTIEN_EXTIEN_POSS,GPIO_EXTIEN_EXTIEN_POSE) - -/****************** Bit definition for GPIO_EXTIFLAG register ************************/ - -#define GPIO_EXTIFLAG_EXTIFLAG_POSS 0U -#define GPIO_EXTIFLAG_EXTIFLAG_POSE 15U -#define GPIO_EXTIFLAG_EXTIFLAG_MSK BITS(GPIO_EXTIFLAG_EXTIFLAG_POSS,GPIO_EXTIFLAG_EXTIFLAG_POSE) - -/****************** Bit definition for GPIO_EXTISFR register ************************/ - -#define GPIO_EXTISFR_EXTISFR_POSS 0U -#define GPIO_EXTISFR_EXTISFR_POSE 15U -#define GPIO_EXTISFR_EXTISFR_MSK BITS(GPIO_EXTISFR_EXTISFR_POSS,GPIO_EXTISFR_EXTISFR_POSE) - -/****************** Bit definition for GPIO_EXTICFR register ************************/ - -#define GPIO_EXTICFR_EXTICFR_POSS 0U -#define GPIO_EXTICFR_EXTICFR_POSE 15U -#define GPIO_EXTICFR_EXTICFR_MSK BITS(GPIO_EXTICFR_EXTICFR_POSS,GPIO_EXTICFR_EXTICFR_POSE) - -/****************** Bit definition for GPIO_EXTIPSR0 register ************************/ - -#define GPIO_EXTIPSR0_EXTIS7_POSS 28U -#define GPIO_EXTIPSR0_EXTIS7_POSE 30U -#define GPIO_EXTIPSR0_EXTIS7_MSK BITS(GPIO_EXTIPSR0_EXTIS7_POSS,GPIO_EXTIPSR0_EXTIS7_POSE) - -#define GPIO_EXTIPSR0_EXTIS6_POSS 24U -#define GPIO_EXTIPSR0_EXTIS6_POSE 26U -#define GPIO_EXTIPSR0_EXTIS6_MSK BITS(GPIO_EXTIPSR0_EXTIS6_POSS,GPIO_EXTIPSR0_EXTIS6_POSE) - -#define GPIO_EXTIPSR0_EXTIS5_POSS 20U -#define GPIO_EXTIPSR0_EXTIS5_POSE 22U -#define GPIO_EXTIPSR0_EXTIS5_MSK BITS(GPIO_EXTIPSR0_EXTIS5_POSS,GPIO_EXTIPSR0_EXTIS5_POSE) - -#define GPIO_EXTIPSR0_EXTIS4_POSS 16U -#define GPIO_EXTIPSR0_EXTIS4_POSE 18U -#define GPIO_EXTIPSR0_EXTIS4_MSK BITS(GPIO_EXTIPSR0_EXTIS4_POSS,GPIO_EXTIPSR0_EXTIS4_POSE) - -#define GPIO_EXTIPSR0_EXTIS3_POSS 12U -#define GPIO_EXTIPSR0_EXTIS3_POSE 14U -#define GPIO_EXTIPSR0_EXTIS3_MSK BITS(GPIO_EXTIPSR0_EXTIS3_POSS,GPIO_EXTIPSR0_EXTIS3_POSE) - -#define GPIO_EXTIPSR0_EXTIS2_POSS 8U -#define GPIO_EXTIPSR0_EXTIS2_POSE 10U -#define GPIO_EXTIPSR0_EXTIS2_MSK BITS(GPIO_EXTIPSR0_EXTIS2_POSS,GPIO_EXTIPSR0_EXTIS2_POSE) - -#define GPIO_EXTIPSR0_EXTIS1_POSS 4U -#define GPIO_EXTIPSR0_EXTIS1_POSE 6U -#define GPIO_EXTIPSR0_EXTIS1_MSK BITS(GPIO_EXTIPSR0_EXTIS1_POSS,GPIO_EXTIPSR0_EXTIS1_POSE) - -#define GPIO_EXTIPSR0_EXTIS0_POSS 0U -#define GPIO_EXTIPSR0_EXTIS0_POSE 2U -#define GPIO_EXTIPSR0_EXTIS0_MSK BITS(GPIO_EXTIPSR0_EXTIS0_POSS,GPIO_EXTIPSR0_EXTIS0_POSE) - -/****************** Bit definition for GPIO_EXTIPSR1 register ************************/ - -#define GPIO_EXTIPSR1_EXTIS15_POSS 28U -#define GPIO_EXTIPSR1_EXTIS15_POSE 30U -#define GPIO_EXTIPSR1_EXTIS15_MSK BITS(GPIO_EXTIPSR1_EXTIS15_POSS,GPIO_EXTIPSR1_EXTIS15_POSE) - -#define GPIO_EXTIPSR1_EXTIS14_POSS 24U -#define GPIO_EXTIPSR1_EXTIS14_POSE 26U -#define GPIO_EXTIPSR1_EXTIS14_MSK BITS(GPIO_EXTIPSR1_EXTIS14_POSS,GPIO_EXTIPSR1_EXTIS14_POSE) - -#define GPIO_EXTIPSR1_EXTIS13_POSS 20U -#define GPIO_EXTIPSR1_EXTIS13_POSE 22U -#define GPIO_EXTIPSR1_EXTIS13_MSK BITS(GPIO_EXTIPSR1_EXTIS13_POSS,GPIO_EXTIPSR1_EXTIS13_POSE) - -#define GPIO_EXTIPSR1_EXTIS12_POSS 16U -#define GPIO_EXTIPSR1_EXTIS12_POSE 18U -#define GPIO_EXTIPSR1_EXTIS12_MSK BITS(GPIO_EXTIPSR1_EXTIS12_POSS,GPIO_EXTIPSR1_EXTIS12_POSE) - -#define GPIO_EXTIPSR1_EXTIS11_POSS 12U -#define GPIO_EXTIPSR1_EXTIS11_POSE 14U -#define GPIO_EXTIPSR1_EXTIS11_MSK BITS(GPIO_EXTIPSR1_EXTIS11_POSS,GPIO_EXTIPSR1_EXTIS11_POSE) - -#define GPIO_EXTIPSR1_EXTIS10_POSS 8U -#define GPIO_EXTIPSR1_EXTIS10_POSE 10U -#define GPIO_EXTIPSR1_EXTIS10_MSK BITS(GPIO_EXTIPSR1_EXTIS10_POSS,GPIO_EXTIPSR1_EXTIS10_POSE) - -#define GPIO_EXTIPSR1_EXTIS9_POSS 4U -#define GPIO_EXTIPSR1_EXTIS9_POSE 6U -#define GPIO_EXTIPSR1_EXTIS9_MSK BITS(GPIO_EXTIPSR1_EXTIS9_POSS,GPIO_EXTIPSR1_EXTIS9_POSE) - -#define GPIO_EXTIPSR1_EXTIS8_POSS 0U -#define GPIO_EXTIPSR1_EXTIS8_POSE 2U -#define GPIO_EXTIPSR1_EXTIS8_MSK BITS(GPIO_EXTIPSR1_EXTIS8_POSS,GPIO_EXTIPSR1_EXTIS8_POSE) - -/****************** Bit definition for GPIO_EXTIFLTCR register ************************/ - -#define GPIO_EXTIFLTCR_FLTCKS_POSS 24U -#define GPIO_EXTIFLTCR_FLTCKS_POSE 25U -#define GPIO_EXTIFLTCR_FLTCKS_MSK BITS(GPIO_EXTIFLTCR_FLTCKS_POSS,GPIO_EXTIFLTCR_FLTCKS_POSE) - -#define GPIO_EXTIFLTCR_FLTSEL_POSS 16U -#define GPIO_EXTIFLTCR_FLTSEL_POSE 23U -#define GPIO_EXTIFLTCR_FLTSEL_MSK BITS(GPIO_EXTIFLTCR_FLTSEL_POSS,GPIO_EXTIFLTCR_FLTSEL_POSE) - -#define GPIO_EXTIFLTCR_FLTEN_POSS 0U -#define GPIO_EXTIFLTCR_FLTEN_POSE 15U -#define GPIO_EXTIFLTCR_FLTEN_MSK BITS(GPIO_EXTIFLTCR_FLTEN_POSS,GPIO_EXTIFLTCR_FLTEN_POSE) - -typedef struct -{ - __IO uint32_t EXTIRER; - uint32_t RESERVED0 ; - __IO uint32_t EXTIFER; - uint32_t RESERVED1 ; - __IO uint32_t EXTIEN; - uint32_t RESERVED2 ; - __I uint32_t EXTIFLAG; - uint32_t RESERVED3 ; - __O uint32_t EXTISFR; - uint32_t RESERVED4 ; - __O uint32_t EXTICFR; - uint32_t RESERVED5 ; - __IO uint32_t EXTIPSR0; - __IO uint32_t EXTIPSR1; - uint32_t RESERVED6[2] ; - __IO uint32_t EXTIFLTCR; -} EXTI_TypeDef; - -/****************** Bit definition for RTC_WPR register ************************/ - -#define RTC_WPR_WP_POS 0U -#define RTC_WPR_WP_MSK BIT(RTC_WPR_WP_POS) - -/****************** Bit definition for RTC_CON register ************************/ - -#define RTC_CON_SSEC_POS 25U -#define RTC_CON_SSEC_MSK BIT(RTC_CON_SSEC_POS) - -#define RTC_CON_BUSY_POS 24U -#define RTC_CON_BUSY_MSK BIT(RTC_CON_BUSY_POS) - -#define RTC_CON_POL_POS 22U -#define RTC_CON_POL_MSK BIT(RTC_CON_POL_POS) - -#define RTC_CON_EOS_POSS 20U -#define RTC_CON_EOS_POSE 21U -#define RTC_CON_EOS_MSK BITS(RTC_CON_EOS_POSS,RTC_CON_EOS_POSE) - -#define RTC_CON_CKOS_POSS 17U -#define RTC_CON_CKOS_POSE 19U -#define RTC_CON_CKOS_MSK BITS(RTC_CON_CKOS_POSS,RTC_CON_CKOS_POSE) - -#define RTC_CON_CKOE_POS 16U -#define RTC_CON_CKOE_MSK BIT(RTC_CON_CKOE_POS) - -#define RTC_CON_WUCKS_POSS 13U -#define RTC_CON_WUCKS_POSE 15U -#define RTC_CON_WUCKS_MSK BITS(RTC_CON_WUCKS_POSS,RTC_CON_WUCKS_POSE) - -#define RTC_CON_WUTE_POS 12U -#define RTC_CON_WUTE_MSK BIT(RTC_CON_WUTE_POS) - -#define RTC_CON_DSTS_POS 10U -#define RTC_CON_DSTS_MSK BIT(RTC_CON_DSTS_POS) - -#define RTC_CON_SUB1H_POS 9U -#define RTC_CON_SUB1H_MSK BIT(RTC_CON_SUB1H_POS) - -#define RTC_CON_ADD1H_POS 8U -#define RTC_CON_ADD1H_MSK BIT(RTC_CON_ADD1H_POS) - -#define RTC_CON_TSPIN_POS 7U -#define RTC_CON_TSPIN_MSK BIT(RTC_CON_TSPIN_POS) - -#define RTC_CON_TSSEL_POS 6U -#define RTC_CON_TSSEL_MSK BIT(RTC_CON_TSSEL_POS) - -#define RTC_CON_TSEN_POS 5U -#define RTC_CON_TSEN_MSK BIT(RTC_CON_TSEN_POS) - -#define RTC_CON_SHDBP_POS 4U -#define RTC_CON_SHDBP_MSK BIT(RTC_CON_SHDBP_POS) - -#define RTC_CON_HFM_POS 3U -#define RTC_CON_HFM_MSK BIT(RTC_CON_HFM_POS) - -#define RTC_CON_ALMBEN_POS 2U -#define RTC_CON_ALMBEN_MSK BIT(RTC_CON_ALMBEN_POS) - -#define RTC_CON_ALMAEN_POS 1U -#define RTC_CON_ALMAEN_MSK BIT(RTC_CON_ALMAEN_POS) - -#define RTC_CON_GO_POS 0U -#define RTC_CON_GO_MSK BIT(RTC_CON_GO_POS) - -/****************** Bit definition for RTC_PSR register ************************/ - -#define RTC_PSR_APRS_POSS 16U -#define RTC_PSR_APRS_POSE 22U -#define RTC_PSR_APRS_MSK BITS(RTC_PSR_APRS_POSS,RTC_PSR_APRS_POSE) - -#define RTC_PSR_SPRS_POSS 0U -#define RTC_PSR_SPRS_POSE 14U -#define RTC_PSR_SPRS_MSK BITS(RTC_PSR_SPRS_POSS,RTC_PSR_SPRS_POSE) - -/****************** Bit definition for RTC_TAMPCON register ************************/ - -#define RTC_TAMPCON_TAMPFLT_POSS 20U -#define RTC_TAMPCON_TAMPFLT_POSE 21U -#define RTC_TAMPCON_TAMPFLT_MSK BITS(RTC_TAMPCON_TAMPFLT_POSS,RTC_TAMPCON_TAMPFLT_POSE) - -#define RTC_TAMPCON_TAMPCKS_POSS 17U -#define RTC_TAMPCON_TAMPCKS_POSE 19U -#define RTC_TAMPCON_TAMPCKS_MSK BITS(RTC_TAMPCON_TAMPCKS_POSS,RTC_TAMPCON_TAMPCKS_POSE) - -#define RTC_TAMPCON_TAMPTS_POS 16U -#define RTC_TAMPCON_TAMPTS_MSK BIT(RTC_TAMPCON_TAMPTS_POS) - -#define RTC_TAMPCON_TAMP1LV_POS 9U -#define RTC_TAMPCON_TAMP1LV_MSK BIT(RTC_TAMPCON_TAMP1LV_POS) - -#define RTC_TAMPCON_TAMP1EN_POS 8U -#define RTC_TAMPCON_TAMP1EN_MSK BIT(RTC_TAMPCON_TAMP1EN_POS) - -#define RTC_TAMPCON_TAMP0LV_POS 1U -#define RTC_TAMPCON_TAMP0LV_MSK BIT(RTC_TAMPCON_TAMP0LV_POS) - -#define RTC_TAMPCON_TAMP0EN_POS 0U -#define RTC_TAMPCON_TAMP0EN_MSK BIT(RTC_TAMPCON_TAMP0EN_POS) - -/****************** Bit definition for RTC_TIME register ************************/ - -#define RTC_TIME_PM_POS 22U -#define RTC_TIME_PM_MSK BIT(RTC_TIME_PM_POS) - -#define RTC_TIME_HRT_POSS 20U -#define RTC_TIME_HRT_POSE 21U -#define RTC_TIME_HRT_MSK BITS(RTC_TIME_HRT_POSS,RTC_TIME_HRT_POSE) - -#define RTC_TIME_HRU_POSS 16U -#define RTC_TIME_HRU_POSE 19U -#define RTC_TIME_HRU_MSK BITS(RTC_TIME_HRU_POSS,RTC_TIME_HRU_POSE) - -#define RTC_TIME_MINT_POSS 12U -#define RTC_TIME_MINT_POSE 14U -#define RTC_TIME_MINT_MSK BITS(RTC_TIME_MINT_POSS,RTC_TIME_MINT_POSE) - -#define RTC_TIME_MINU_POSS 8U -#define RTC_TIME_MINU_POSE 11U -#define RTC_TIME_MINU_MSK BITS(RTC_TIME_MINU_POSS,RTC_TIME_MINU_POSE) - -#define RTC_TIME_SECT_POSS 4U -#define RTC_TIME_SECT_POSE 6U -#define RTC_TIME_SECT_MSK BITS(RTC_TIME_SECT_POSS,RTC_TIME_SECT_POSE) - -#define RTC_TIME_SECU_POSS 0U -#define RTC_TIME_SECU_POSE 3U -#define RTC_TIME_SECU_MSK BITS(RTC_TIME_SECU_POSS,RTC_TIME_SECU_POSE) - -/****************** Bit definition for RTC_DATE register ************************/ - -#define RTC_DATE_WD_POSS 24U -#define RTC_DATE_WD_POSE 26U -#define RTC_DATE_WD_MSK BITS(RTC_DATE_WD_POSS,RTC_DATE_WD_POSE) - -#define RTC_DATE_YRT_POSS 20U -#define RTC_DATE_YRT_POSE 23U -#define RTC_DATE_YRT_MSK BITS(RTC_DATE_YRT_POSS,RTC_DATE_YRT_POSE) - -#define RTC_DATE_YRU_POSS 16U -#define RTC_DATE_YRU_POSE 19U -#define RTC_DATE_YRU_MSK BITS(RTC_DATE_YRU_POSS,RTC_DATE_YRU_POSE) - -#define RTC_DATE_MONT_POS 12U -#define RTC_DATE_MONT_MSK BIT(RTC_DATE_MONT_POS) - -#define RTC_DATE_MONU_POSS 8U -#define RTC_DATE_MONU_POSE 11U -#define RTC_DATE_MONU_MSK BITS(RTC_DATE_MONU_POSS,RTC_DATE_MONU_POSE) - -#define RTC_DATE_DAYT_POSS 4U -#define RTC_DATE_DAYT_POSE 5U -#define RTC_DATE_DAYT_MSK BITS(RTC_DATE_DAYT_POSS,RTC_DATE_DAYT_POSE) - -#define RTC_DATE_DAYU_POSS 0U -#define RTC_DATE_DAYU_POSE 3U -#define RTC_DATE_DAYU_MSK BITS(RTC_DATE_DAYU_POSS,RTC_DATE_DAYU_POSE) - -/****************** Bit definition for RTC_SSEC register ************************/ - -#define RTC_SSEC_VAL_POSS 0U -#define RTC_SSEC_VAL_POSE 15U -#define RTC_SSEC_VAL_MSK BITS(RTC_SSEC_VAL_POSS,RTC_SSEC_VAL_POSE) - -/****************** Bit definition for RTC_WUMAT register ************************/ - -#define RTC_WUMAT_VAL_POSS 0U -#define RTC_WUMAT_VAL_POSE 15U -#define RTC_WUMAT_VAL_MSK BITS(RTC_WUMAT_VAL_POSS,RTC_WUMAT_VAL_POSE) - -/****************** Bit definition for RTC_ALMA register ************************/ - -#define RTC_ALMA_WDS_POS 31U -#define RTC_ALMA_WDS_MSK BIT(RTC_ALMA_WDS_POS) - -#define RTC_ALMA_DAWD_POSS 24U -#define RTC_ALMA_DAWD_POSE 30U -#define RTC_ALMA_DAWD_MSK BITS(RTC_ALMA_DAWD_POSS,RTC_ALMA_DAWD_POSE) - -#define RTC_ALMA_DAYMSK_POS 30U -#define RTC_ALMA_DAYMSK_MSK BIT(RTC_ALMA_DAYMSK_POS) - -#define RTC_ALMA_DAWD_DAYT_POSS 28U -#define RTC_ALMA_DAWD_DAYT_POSE 29U -#define RTC_ALMA_DAWD_DAYT_MSK BITS(RTC_ALMA_DAWD_DAYT_POSS, RTC_ALMA_DAWD_DAYT_POSE) - -#define RTC_ALMA_DAWD_DAYU_POSS 24U -#define RTC_ALMA_DAWD_DAYU_POSE 27U -#define RTC_ALMA_DAWD_DAYU_MSK BITS(RTC_ALMA_DAWD_DAYU_POSS, RTC_ALMA_DAWD_DAYU_POSE) - -#define RTC_ALMA_HRMSK_POS 23U -#define RTC_ALMA_HRMSK_MSK BIT(RTC_ALMA_HRMSK_POS) - -#define RTC_ALMA_PM_POS 22U -#define RTC_ALMA_PM_MSK BIT(RTC_ALMA_PM_POS) - -#define RTC_ALMA_HRT_POSS 20U -#define RTC_ALMA_HRT_POSE 21U -#define RTC_ALMA_HRT_MSK BITS(RTC_ALMA_HRT_POSS,RTC_ALMA_HRT_POSE) - -#define RTC_ALMA_HRU_POSS 16U -#define RTC_ALMA_HRU_POSE 19U -#define RTC_ALMA_HRU_MSK BITS(RTC_ALMA_HRU_POSS,RTC_ALMA_HRU_POSE) - -#define RTC_ALMA_MINMSK_POS 15U -#define RTC_ALMA_MINMSK_MSK BIT(RTC_ALMA_MINMSK_POS) - -#define RTC_ALMA_MINT_POSS 12U -#define RTC_ALMA_MINT_POSE 14U -#define RTC_ALMA_MINT_MSK BITS(RTC_ALMA_MINT_POSS,RTC_ALMA_MINT_POSE) - -#define RTC_ALMA_MINU_POSS 8U -#define RTC_ALMA_MINU_POSE 11U -#define RTC_ALMA_MINU_MSK BITS(RTC_ALMA_MINU_POSS,RTC_ALMA_MINU_POSE) - -#define RTC_ALMA_SECMSK_POS 7U -#define RTC_ALMA_SECMSK_MSK BIT(RTC_ALMA_SECMSK_POS) - -#define RTC_ALMA_SECT_POSS 4U -#define RTC_ALMA_SECT_POSE 6U -#define RTC_ALMA_SECT_MSK BITS(RTC_ALMA_SECT_POSS,RTC_ALMA_SECT_POSE) - -#define RTC_ALMA_SECU_POSS 0U -#define RTC_ALMA_SECU_POSE 3U -#define RTC_ALMA_SECU_MSK BITS(RTC_ALMA_SECU_POSS,RTC_ALMA_SECU_POSE) - -/****************** Bit definition for RTC_ALMB register ************************/ - -#define RTC_ALMB_WDS_POS 31U -#define RTC_ALMB_WDS_MSK BIT(RTC_ALMB_WDS_POS) - -#define RTC_ALMB_DAWD_POSS 24U -#define RTC_ALMB_DAWD_POSE 30U -#define RTC_ALMB_DAWD_MSK BITS(RTC_ALMB_DAWD_POSS,RTC_ALMB_DAWD_POSE) - -#define RTC_ALMB_DAYMSK_POS 30U -#define RTC_ALMB_DAYMSK_MSK BIT(RTC_ALMB_DAYMSK_POS) - -#define RTC_ALMB_DAWD_DAYT_POSS 28U -#define RTC_ALMB_DAWD_DAYT_POSE 29U -#define RTC_ALMB_DAWD_DAYT_MSK BITS(RTC_ALMB_DAWD_DAYT_POSS, RTC_ALMB_DAWD_DAYT_POSE) - -#define RTC_ALMB_DAWD_DAYU_POSS 24U -#define RTC_ALMB_DAWD_DAYU_POSE 27U -#define RTC_ALMB_DAWD_DAYU_MSK BITS(RTC_ALMB_DAWD_DAYU_POSS, RTC_ALMB_DAWD_DAYU_POSE) - -#define RTC_ALMB_HRMSK_POS 23U -#define RTC_ALMB_HRMSK_MSK BIT(RTC_ALMB_HRMSK_POS) - -#define RTC_ALMB_PM_POS 22U -#define RTC_ALMB_PM_MSK BIT(RTC_ALMB_PM_POS) - -#define RTC_ALMB_HRT_POSS 20U -#define RTC_ALMB_HRT_POSE 21U -#define RTC_ALMB_HRT_MSK BITS(RTC_ALMB_HRT_POSS,RTC_ALMB_HRT_POSE) - -#define RTC_ALMB_HRU_POSS 16U -#define RTC_ALMB_HRU_POSE 19U -#define RTC_ALMB_HRU_MSK BITS(RTC_ALMB_HRU_POSS,RTC_ALMB_HRU_POSE) - -#define RTC_ALMB_MINMSK_POS 15U -#define RTC_ALMB_MINMSK_MSK BIT(RTC_ALMB_MINMSK_POS) - -#define RTC_ALMB_MINT_POSS 12U -#define RTC_ALMB_MINT_POSE 14U -#define RTC_ALMB_MINT_MSK BITS(RTC_ALMB_MINT_POSS,RTC_ALMB_MINT_POSE) - -#define RTC_ALMB_MINU_POSS 8U -#define RTC_ALMB_MINU_POSE 11U -#define RTC_ALMB_MINU_MSK BITS(RTC_ALMB_MINU_POSS,RTC_ALMB_MINU_POSE) - -#define RTC_ALMB_SECMSK_POS 7U -#define RTC_ALMB_SECMSK_MSK BIT(RTC_ALMB_SECMSK_POS) - -#define RTC_ALMB_SECT_POSS 4U -#define RTC_ALMB_SECT_POSE 6U -#define RTC_ALMB_SECT_MSK BITS(RTC_ALMB_SECT_POSS,RTC_ALMB_SECT_POSE) - -#define RTC_ALMB_SECU_POSS 0U -#define RTC_ALMB_SECU_POSE 3U -#define RTC_ALMB_SECU_MSK BITS(RTC_ALMB_SECU_POSS,RTC_ALMB_SECU_POSE) - -/****************** Bit definition for RTC_ALMASSEC register ************************/ - -#define RTC_ALMASSEC_SSECM_POSS 24U -#define RTC_ALMASSEC_SSECM_POSE 27U -#define RTC_ALMASSEC_SSECM_MSK BITS(RTC_ALMASSEC_SSECM_POSS,RTC_ALMASSEC_SSECM_POSE) - -#define RTC_ALMASSEC_SSEC_POSS 0U -#define RTC_ALMASSEC_SSEC_POSE 14U -#define RTC_ALMASSEC_SSEC_MSK BITS(RTC_ALMASSEC_SSEC_POSS,RTC_ALMASSEC_SSEC_POSE) - -/****************** Bit definition for RTC_ALMBSSEC register ************************/ - -#define RTC_ALMBSSEC_SSECM_POSS 24U -#define RTC_ALMBSSEC_SSECM_POSE 27U -#define RTC_ALMBSSEC_SSECM_MSK BITS(RTC_ALMBSSEC_SSECM_POSS,RTC_ALMBSSEC_SSECM_POSE) - -#define RTC_ALMBSSEC_SSEC_POSS 0U -#define RTC_ALMBSSEC_SSEC_POSE 14U -#define RTC_ALMBSSEC_SSEC_MSK BITS(RTC_ALMBSSEC_SSEC_POSS,RTC_ALMBSSEC_SSEC_POSE) - -/****************** Bit definition for RTC_TSTIME register ************************/ - -#define RTC_TSTIME_PM_POS 22U -#define RTC_TSTIME_PM_MSK BIT(RTC_TSTIME_PM_POS) - -#define RTC_TSTIME_HRT_POSS 20U -#define RTC_TSTIME_HRT_POSE 21U -#define RTC_TSTIME_HRT_MSK BITS(RTC_TSTIME_HRT_POSS,RTC_TSTIME_HRT_POSE) - -#define RTC_TSTIME_HRU_POSS 16U -#define RTC_TSTIME_HRU_POSE 19U -#define RTC_TSTIME_HRU_MSK BITS(RTC_TSTIME_HRU_POSS,RTC_TSTIME_HRU_POSE) - -#define RTC_TSTIME_MINT_POSS 12U -#define RTC_TSTIME_MINT_POSE 14U -#define RTC_TSTIME_MINT_MSK BITS(RTC_TSTIME_MINT_POSS,RTC_TSTIME_MINT_POSE) - -#define RTC_TSTIME_MINU_POSS 8U -#define RTC_TSTIME_MINU_POSE 11U -#define RTC_TSTIME_MINU_MSK BITS(RTC_TSTIME_MINU_POSS,RTC_TSTIME_MINU_POSE) - -#define RTC_TSTIME_SECT_POSS 4U -#define RTC_TSTIME_SECT_POSE 6U -#define RTC_TSTIME_SECT_MSK BITS(RTC_TSTIME_SECT_POSS,RTC_TSTIME_SECT_POSE) - -#define RTC_TSTIME_SECU_POSS 0U -#define RTC_TSTIME_SECU_POSE 3U -#define RTC_TSTIME_SECU_MSK BITS(RTC_TSTIME_SECU_POSS,RTC_TSTIME_SECU_POSE) - -/****************** Bit definition for RTC_TSDATE register ************************/ - -#define RTC_TSDATE_WD_POSS 24U -#define RTC_TSDATE_WD_POSE 26U -#define RTC_TSDATE_WD_MSK BITS(RTC_TSDATE_WD_POSS,RTC_TSDATE_WD_POSE) - -#define RTC_TSDATE_YRT_POSS 20U -#define RTC_TSDATE_YRT_POSE 23U -#define RTC_TSDATE_YRT_MSK BITS(RTC_TSDATE_YRT_POSS,RTC_TSDATE_YRT_POSE) - -#define RTC_TSDATE_YRU_POSS 16U -#define RTC_TSDATE_YRU_POSE 19U -#define RTC_TSDATE_YRU_MSK BITS(RTC_TSDATE_YRU_POSS,RTC_TSDATE_YRU_POSE) - -#define RTC_TSDATE_MONT_POS 12U -#define RTC_TSDATE_MONT_MSK BIT(RTC_TSDATE_MONT_POS) - -#define RTC_TSDATE_MONU_POSS 8U -#define RTC_TSDATE_MONU_POSE 11U -#define RTC_TSDATE_MONU_MSK BITS(RTC_TSDATE_MONU_POSS,RTC_TSDATE_MONU_POSE) - -#define RTC_TSDATE_DAYT_POSS 4U -#define RTC_TSDATE_DAYT_POSE 5U -#define RTC_TSDATE_DAYT_MSK BITS(RTC_TSDATE_DAYT_POSS,RTC_TSDATE_DAYT_POSE) - -#define RTC_TSDATE_DAYU_POSS 0U -#define RTC_TSDATE_DAYU_POSE 3U -#define RTC_TSDATE_DAYU_MSK BITS(RTC_TSDATE_DAYU_POSS,RTC_TSDATE_DAYU_POSE) - -/****************** Bit definition for RTC_TSSSEC register ************************/ - -#define RTC_TSSSEC_SSEC_POSS 0U -#define RTC_TSSSEC_SSEC_POSE 15U -#define RTC_TSSSEC_SSEC_MSK BITS(RTC_TSSSEC_SSEC_POSS,RTC_TSSSEC_SSEC_POSE) - -/****************** Bit definition for RTC_SSECTR register ************************/ - -#define RTC_SSECTR_INC_POS 31U -#define RTC_SSECTR_INC_MSK BIT(RTC_SSECTR_INC_POS) - -#define RTC_SSECTR_TRIM_POSS 0U -#define RTC_SSECTR_TRIM_POSE 14U -#define RTC_SSECTR_TRIM_MSK BITS(RTC_SSECTR_TRIM_POSS,RTC_SSECTR_TRIM_POSE) - -/****************** Bit definition for RTC_IER register ************************/ - -#define RTC_IER_TCE_POS 25U -#define RTC_IER_TCE_MSK BIT(RTC_IER_TCE_POS) - -#define RTC_IER_TCC_POS 24U -#define RTC_IER_TCC_MSK BIT(RTC_IER_TCC_POS) - -#define RTC_IER_WU_POS 18U -#define RTC_IER_WU_MSK BIT(RTC_IER_WU_POS) - -#define RTC_IER_SSTC_POS 17U -#define RTC_IER_SSTC_MSK BIT(RTC_IER_SSTC_POS) - -#define RTC_IER_RSC_POS 16U -#define RTC_IER_RSC_MSK BIT(RTC_IER_RSC_POS) - -#define RTC_IER_TAMP1_POS 13U -#define RTC_IER_TAMP1_MSK BIT(RTC_IER_TAMP1_POS) - -#define RTC_IER_TAMP0_POS 12U -#define RTC_IER_TAMP0_MSK BIT(RTC_IER_TAMP0_POS) - -#define RTC_IER_TSOV_POS 11U -#define RTC_IER_TSOV_MSK BIT(RTC_IER_TSOV_POS) - -#define RTC_IER_TS_POS 10U -#define RTC_IER_TS_MSK BIT(RTC_IER_TS_POS) - -#define RTC_IER_ALMB_POS 9U -#define RTC_IER_ALMB_MSK BIT(RTC_IER_ALMB_POS) - -#define RTC_IER_ALMA_POS 8U -#define RTC_IER_ALMA_MSK BIT(RTC_IER_ALMA_POS) - -#define RTC_IER_YR_POS 5U -#define RTC_IER_YR_MSK BIT(RTC_IER_YR_POS) - -#define RTC_IER_MON_POS 4U -#define RTC_IER_MON_MSK BIT(RTC_IER_MON_POS) - -#define RTC_IER_DAY_POS 3U -#define RTC_IER_DAY_MSK BIT(RTC_IER_DAY_POS) - -#define RTC_IER_HR_POS 2U -#define RTC_IER_HR_MSK BIT(RTC_IER_HR_POS) - -#define RTC_IER_MIN_POS 1U -#define RTC_IER_MIN_MSK BIT(RTC_IER_MIN_POS) - -#define RTC_IER_SEC_POS 0U -#define RTC_IER_SEC_MSK BIT(RTC_IER_SEC_POS) - -/****************** Bit definition for RTC_IFR register ************************/ - -#define RTC_IFR_TCEF_POS 25U -#define RTC_IFR_TCEF_MSK BIT(RTC_IFR_TCEF_POS) - -#define RTC_IFR_TCCF_POS 24U -#define RTC_IFR_TCCF_MSK BIT(RTC_IFR_TCCF_POS) - -#define RTC_IFR_WUF_POS 18U -#define RTC_IFR_WUF_MSK BIT(RTC_IFR_WUF_POS) - -#define RTC_IFR_SSTCF_POS 17U -#define RTC_IFR_SSTCF_MSK BIT(RTC_IFR_SSTCF_POS) - -#define RTC_IFR_RSCF_POS 16U -#define RTC_IFR_RSCF_MSK BIT(RTC_IFR_RSCF_POS) - -#define RTC_IFR_TAMP1F_POS 13U -#define RTC_IFR_TAMP1F_MSK BIT(RTC_IFR_TAMP1F_POS) - -#define RTC_IFR_TAMP0F_POS 12U -#define RTC_IFR_TAMP0F_MSK BIT(RTC_IFR_TAMP0F_POS) - -#define RTC_IFR_TSOVF_POS 11U -#define RTC_IFR_TSOVF_MSK BIT(RTC_IFR_TSOVF_POS) - -#define RTC_IFR_TSF_POS 10U -#define RTC_IFR_TSF_MSK BIT(RTC_IFR_TSF_POS) - -#define RTC_IFR_ALMBF_POS 9U -#define RTC_IFR_ALMBF_MSK BIT(RTC_IFR_ALMBF_POS) - -#define RTC_IFR_ALMAF_POS 8U -#define RTC_IFR_ALMAF_MSK BIT(RTC_IFR_ALMAF_POS) - -#define RTC_IFR_YRF_POS 5U -#define RTC_IFR_YRF_MSK BIT(RTC_IFR_YRF_POS) - -#define RTC_IFR_MONF_POS 4U -#define RTC_IFR_MONF_MSK BIT(RTC_IFR_MONF_POS) - -#define RTC_IFR_DAYF_POS 3U -#define RTC_IFR_DAYF_MSK BIT(RTC_IFR_DAYF_POS) - -#define RTC_IFR_HRF_POS 2U -#define RTC_IFR_HRF_MSK BIT(RTC_IFR_HRF_POS) - -#define RTC_IFR_MINF_POS 1U -#define RTC_IFR_MINF_MSK BIT(RTC_IFR_MINF_POS) - -#define RTC_IFR_SECF_POS 0U -#define RTC_IFR_SECF_MSK BIT(RTC_IFR_SECF_POS) - -/****************** Bit definition for RTC_IFCR register ************************/ - -#define RTC_IFCR_TCEFC_POS 25U -#define RTC_IFCR_TCEFC_MSK BIT(RTC_IFCR_TCEFC_POS) - -#define RTC_IFCR_TCCFC_POS 24U -#define RTC_IFCR_TCCFC_MSK BIT(RTC_IFCR_TCCFC_POS) - -#define RTC_IFCR_WUFC_POS 18U -#define RTC_IFCR_WUFC_MSK BIT(RTC_IFCR_WUFC_POS) - -#define RTC_IFCR_SSTCFC_POS 17U -#define RTC_IFCR_SSTCFC_MSK BIT(RTC_IFCR_SSTCFC_POS) - -#define RTC_IFCR_RSCFC_POS 16U -#define RTC_IFCR_RSCFC_MSK BIT(RTC_IFCR_RSCFC_POS) - -#define RTC_IFCR_TAMP1FC_POS 13U -#define RTC_IFCR_TAMP1FC_MSK BIT(RTC_IFCR_TAMP1FC_POS) - -#define RTC_IFCR_TAMP0FC_POS 12U -#define RTC_IFCR_TAMP0FC_MSK BIT(RTC_IFCR_TAMP0FC_POS) - -#define RTC_IFCR_TSOVFC_POS 11U -#define RTC_IFCR_TSOVFC_MSK BIT(RTC_IFCR_TSOVFC_POS) - -#define RTC_IFCR_TSFC_POS 10U -#define RTC_IFCR_TSFC_MSK BIT(RTC_IFCR_TSFC_POS) - -#define RTC_IFCR_ALMBFC_POS 9U -#define RTC_IFCR_ALMBFC_MSK BIT(RTC_IFCR_ALMBFC_POS) - -#define RTC_IFCR_ALMAFC_POS 8U -#define RTC_IFCR_ALMAFC_MSK BIT(RTC_IFCR_ALMAFC_POS) - -#define RTC_IFCR_YRFC_POS 5U -#define RTC_IFCR_YRFC_MSK BIT(RTC_IFCR_YRFC_POS) - -#define RTC_IFCR_MONFC_POS 4U -#define RTC_IFCR_MONFC_MSK BIT(RTC_IFCR_MONFC_POS) - -#define RTC_IFCR_DAYFC_POS 3U -#define RTC_IFCR_DAYFC_MSK BIT(RTC_IFCR_DAYFC_POS) - -#define RTC_IFCR_HRFC_POS 2U -#define RTC_IFCR_HRFC_MSK BIT(RTC_IFCR_HRFC_POS) - -#define RTC_IFCR_MINFC_POS 1U -#define RTC_IFCR_MINFC_MSK BIT(RTC_IFCR_MINFC_POS) - -#define RTC_IFCR_SECFC_POS 0U -#define RTC_IFCR_SECFC_MSK BIT(RTC_IFCR_SECFC_POS) - -/****************** Bit definition for RTC_ISR register ************************/ - -#define RTC_ISR_TCEF_POS 25U -#define RTC_ISR_TCEF_MSK BIT(RTC_ISR_TCEF_POS) - -#define RTC_ISR_TCCF_POS 24U -#define RTC_ISR_TCCF_MSK BIT(RTC_ISR_TCCF_POS) - -#define RTC_ISR_WUF_POS 18U -#define RTC_ISR_WUF_MSK BIT(RTC_ISR_WUF_POS) - -#define RTC_ISR_SSTCF_POS 17U -#define RTC_ISR_SSTCF_MSK BIT(RTC_ISR_SSTCF_POS) - -#define RTC_ISR_RSCF_POS 16U -#define RTC_ISR_RSCF_MSK BIT(RTC_ISR_RSCF_POS) - -#define RTC_ISR_TAMP1F_POS 13U -#define RTC_ISR_TAMP1F_MSK BIT(RTC_ISR_TAMP1F_POS) - -#define RTC_ISR_TAMP0F_POS 12U -#define RTC_ISR_TAMP0F_MSK BIT(RTC_ISR_TAMP0F_POS) - -#define RTC_ISR_TSOVF_POS 11U -#define RTC_ISR_TSOVF_MSK BIT(RTC_ISR_TSOVF_POS) - -#define RTC_ISR_TSF_POS 10U -#define RTC_ISR_TSF_MSK BIT(RTC_ISR_TSF_POS) - -#define RTC_ISR_ALMBF_POS 9U -#define RTC_ISR_ALMBF_MSK BIT(RTC_ISR_ALMBF_POS) - -#define RTC_ISR_ALMAF_POS 8U -#define RTC_ISR_ALMAF_MSK BIT(RTC_ISR_ALMAF_POS) - -#define RTC_ISR_YRF_POS 5U -#define RTC_ISR_YRF_MSK BIT(RTC_ISR_YRF_POS) - -#define RTC_ISR_MONF_POS 4U -#define RTC_ISR_MONF_MSK BIT(RTC_ISR_MONF_POS) - -#define RTC_ISR_DAYF_POS 3U -#define RTC_ISR_DAYF_MSK BIT(RTC_ISR_DAYF_POS) - -#define RTC_ISR_HRF_POS 2U -#define RTC_ISR_HRF_MSK BIT(RTC_ISR_HRF_POS) - -#define RTC_ISR_MINF_POS 1U -#define RTC_ISR_MINF_MSK BIT(RTC_ISR_MINF_POS) - -#define RTC_ISR_SECF_POS 0U -#define RTC_ISR_SECF_MSK BIT(RTC_ISR_SECF_POS) - -/****************** Bit definition for RTC_CALWPR register ************************/ - -#define RTC_CALWPR_WP_POS 0U -#define RTC_CALWPR_WP_MSK BIT(RTC_CALWPR_WP_POS) - -/****************** Bit definition for RTC_CALCON register ************************/ - -#define RTC_CALCON_DCMACC_POS 24U -#define RTC_CALCON_DCMACC_MSK BIT(RTC_CALCON_DCMACC_POS) - -#define RTC_CALCON_ALG_POS 23U -#define RTC_CALCON_ALG_MSK BIT(RTC_CALCON_ALG_POS) - -#define RTC_CALCON_TCP_POSS 20U -#define RTC_CALCON_TCP_POSE 22U -#define RTC_CALCON_TCP_MSK BITS(RTC_CALCON_TCP_POSS,RTC_CALCON_TCP_POSE) - -#define RTC_CALCON_ERR_POS 19U -#define RTC_CALCON_ERR_MSK BIT(RTC_CALCON_ERR_POS) - -#define RTC_CALCON_BUSY_POS 18U -#define RTC_CALCON_BUSY_MSK BIT(RTC_CALCON_BUSY_POS) - -#define RTC_CALCON_TCM_POSS 16U -#define RTC_CALCON_TCM_POSE 17U -#define RTC_CALCON_TCM_MSK BITS(RTC_CALCON_TCM_POSS,RTC_CALCON_TCM_POSE) - -#define RTC_CALCON_CALP_POSS 1U -#define RTC_CALCON_CALP_POSE 3U -#define RTC_CALCON_CALP_MSK BITS(RTC_CALCON_CALP_POSS,RTC_CALCON_CALP_POSE) - -#define RTC_CALCON_CALEN_POS 0U -#define RTC_CALCON_CALEN_MSK BIT(RTC_CALCON_CALEN_POS) - -/****************** Bit definition for RTC_CALDR register ************************/ - -#define RTC_CALDR_DATA_POSS 16U -#define RTC_CALDR_DATA_POSE 31U -#define RTC_CALDR_DATA_MSK BITS(RTC_CALDR_DATA_POSS,RTC_CALDR_DATA_POSE) - -#define RTC_CALDR_VAL_POSS 0U -#define RTC_CALDR_VAL_POSE 15U -#define RTC_CALDR_VAL_MSK BITS(RTC_CALDR_VAL_POSS,RTC_CALDR_VAL_POSE) - -/****************** Bit definition for RTC_TEMPR register ************************/ - -#define RTC_TEMPR_DATA_POSS 16U -#define RTC_TEMPR_DATA_POSE 31U -#define RTC_TEMPR_DATA_MSK BITS(RTC_TEMPR_DATA_POSS,RTC_TEMPR_DATA_POSE) - -#define RTC_TEMPR_VAL_POSS 0U -#define RTC_TEMPR_VAL_POSE 15U -#define RTC_TEMPR_VAL_MSK BITS(RTC_TEMPR_VAL_POSS,RTC_TEMPR_VAL_POSE) - -/****************** Bit definition for RTC_TEMPBDR register ************************/ - -#define RTC_TEMPBDR_VAL_POSS 0U -#define RTC_TEMPBDR_VAL_POSE 15U -#define RTC_TEMPBDR_VAL_MSK BITS(RTC_TEMPBDR_VAL_POSS,RTC_TEMPBDR_VAL_POSE) - -/****************** Bit definition for RTC_BKP register ************************/ - -#define RTC_BKP_BKP_POSS 0U -#define RTC_BKP_BKP_POSE 31U -#define RTC_BKP_BKP_MSK BITS(RTC_BKP_BKP_POSS,RTC_BKP_BKP_POSE) - -typedef struct -{ - __IO uint32_t WPR; - __IO uint32_t CON; - __IO uint32_t PSR; - __IO uint32_t TAMPCON; - __IO uint32_t TIME; - __IO uint32_t DATE; - __IO uint32_t SSEC; - __IO uint32_t WUMAT; - __IO uint32_t ALMA; - __IO uint32_t ALMB; - __IO uint32_t ALMASSEC; - __IO uint32_t ALMBSSEC; - __I uint32_t TSTIME; - __I uint32_t TSDATE; - __I uint32_t TSSSEC; - __O uint32_t SSECTR; - __IO uint32_t IER; - __I uint32_t IFR; - __O uint32_t IFCR; - __I uint32_t ISR; - __IO uint32_t CALWPR; - __IO uint32_t CALCON; - __IO uint32_t CALDR; - __IO uint32_t TEMPR; - __IO uint32_t LTCAR; - __IO uint32_t LTCBR; - __IO uint32_t LTCCR; - __IO uint32_t LTCDR; - __IO uint32_t LTCER; - __IO uint32_t HTCAR; - __IO uint32_t HTCBR; - __IO uint32_t HTCCR; - __IO uint32_t HTCDR; - __IO uint32_t HTCER; - __IO uint32_t TEMPBDR; - uint32_t RESERVED0[29] ; - __IO uint32_t BKPR[32]; -} RTC_TypeDef; - -/****************** Bit definition for TIMER_CON1 register ************************/ - -#define TIMER_CON1_DFCKSEL_POSS 8U -#define TIMER_CON1_DFCKSEL_POSE 9U -#define TIMER_CON1_DFCKSEL_MSK BITS(TIMER_CON1_DFCKSEL_POSS,TIMER_CON1_DFCKSEL_POSE) - -#define TIMER_CON1_ARPEN_POS 7U -#define TIMER_CON1_ARPEN_MSK BIT(TIMER_CON1_ARPEN_POS) - -#define TIMER_CON1_CMSEL_POSS 5U -#define TIMER_CON1_CMSEL_POSE 6U -#define TIMER_CON1_CMSEL_MSK BITS(TIMER_CON1_CMSEL_POSS,TIMER_CON1_CMSEL_POSE) - -#define TIMER_CON1_DIRSEL_POS 4U -#define TIMER_CON1_DIRSEL_MSK BIT(TIMER_CON1_DIRSEL_POS) - -#define TIMER_CON1_SPMEN_POS 3U -#define TIMER_CON1_SPMEN_MSK BIT(TIMER_CON1_SPMEN_POS) - -#define TIMER_CON1_UERSEL_POS 2U -#define TIMER_CON1_UERSEL_MSK BIT(TIMER_CON1_UERSEL_POS) - -#define TIMER_CON1_DISUE_POS 1U -#define TIMER_CON1_DISUE_MSK BIT(TIMER_CON1_DISUE_POS) - -#define TIMER_CON1_CNTEN_POS 0U -#define TIMER_CON1_CNTEN_MSK BIT(TIMER_CON1_CNTEN_POS) - -/****************** Bit definition for TIMER_CON2 register ************************/ - -#define TIMER_CON2_OISS4_POS 14U -#define TIMER_CON2_OISS4_MSK BIT(TIMER_CON2_OISS4_POS) - -#define TIMER_CON2_OISS3N_POS 13U -#define TIMER_CON2_OISS3N_MSK BIT(TIMER_CON2_OISS3N_POS) - -#define TIMER_CON2_OISS3_POS 12U -#define TIMER_CON2_OISS3_MSK BIT(TIMER_CON2_OISS3_POS) - -#define TIMER_CON2_OISS2N_POS 11U -#define TIMER_CON2_OISS2N_MSK BIT(TIMER_CON2_OISS2N_POS) - -#define TIMER_CON2_OISS2_POS 10U -#define TIMER_CON2_OISS2_MSK BIT(TIMER_CON2_OISS2_POS) - -#define TIMER_CON2_OISS1N_POS 9U -#define TIMER_CON2_OISS1N_MSK BIT(TIMER_CON2_OISS1N_POS) - -#define TIMER_CON2_OISS1_POS 8U -#define TIMER_CON2_OISS1_MSK BIT(TIMER_CON2_OISS1_POS) - -#define TIMER_CON2_I1FSEL_POS 7U -#define TIMER_CON2_I1FSEL_MSK BIT(TIMER_CON2_I1FSEL_POS) - -#define TIMER_CON2_TRGOSEL_POSS 4U -#define TIMER_CON2_TRGOSEL_POSE 6U -#define TIMER_CON2_TRGOSEL_MSK BITS(TIMER_CON2_TRGOSEL_POSS,TIMER_CON2_TRGOSEL_POSE) - -#define TIMER_CON2_CCDMASEL_POS 3U -#define TIMER_CON2_CCDMASEL_MSK BIT(TIMER_CON2_CCDMASEL_POS) - -#define TIMER_CON2_CCUSEL_POS 2U -#define TIMER_CON2_CCUSEL_MSK BIT(TIMER_CON2_CCUSEL_POS) - -#define TIMER_CON2_CCPCEN_POS 0U -#define TIMER_CON2_CCPCEN_MSK BIT(TIMER_CON2_CCPCEN_POS) - -/****************** Bit definition for TIMER_SMCON register ************************/ - -#define TIMER_SMCON_ETPOL_POS 15U -#define TIMER_SMCON_ETPOL_MSK BIT(TIMER_SMCON_ETPOL_POS) - -#define TIMER_SMCON_ECM2EN_POS 14U -#define TIMER_SMCON_ECM2EN_MSK BIT(TIMER_SMCON_ECM2EN_POS) - -#define TIMER_SMCON_ETPSEL_POSS 12U -#define TIMER_SMCON_ETPSEL_POSE 13U -#define TIMER_SMCON_ETPSEL_MSK BITS(TIMER_SMCON_ETPSEL_POSS,TIMER_SMCON_ETPSEL_POSE) - -#define TIMER_SMCON_ETFLT_POSS 8U -#define TIMER_SMCON_ETFLT_POSE 11U -#define TIMER_SMCON_ETFLT_MSK BITS(TIMER_SMCON_ETFLT_POSS,TIMER_SMCON_ETFLT_POSE) - -#define TIMER_SMCON_MSCFG_POS 7U -#define TIMER_SMCON_MSCFG_MSK BIT(TIMER_SMCON_MSCFG_POS) - -#define TIMER_SMCON_TSSEL_POSS 4U -#define TIMER_SMCON_TSSEL_POSE 6U -#define TIMER_SMCON_TSSEL_MSK BITS(TIMER_SMCON_TSSEL_POSS,TIMER_SMCON_TSSEL_POSE) - -#define TIMER_SMCON_SMODS_POSS 0U -#define TIMER_SMCON_SMODS_POSE 2U -#define TIMER_SMCON_SMODS_MSK BITS(TIMER_SMCON_SMODS_POSS,TIMER_SMCON_SMODS_POSE) - -/****************** Bit definition for TIMER_DIER register ************************/ - -#define TIMER_DIER_TRGDMA_POS 14U -#define TIMER_DIER_TRGDMA_MSK BIT(TIMER_DIER_TRGDMA_POS) - -#define TIMER_DIER_COMDMA_POS 13U -#define TIMER_DIER_COMDMA_MSK BIT(TIMER_DIER_COMDMA_POS) - -#define TIMER_DIER_CC4DMA_POS 12U -#define TIMER_DIER_CC4DMA_MSK BIT(TIMER_DIER_CC4DMA_POS) - -#define TIMER_DIER_CC3DMA_POS 11U -#define TIMER_DIER_CC3DMA_MSK BIT(TIMER_DIER_CC3DMA_POS) - -#define TIMER_DIER_CC2DMA_POS 10U -#define TIMER_DIER_CC2DMA_MSK BIT(TIMER_DIER_CC2DMA_POS) - -#define TIMER_DIER_CC1DMA_POS 9U -#define TIMER_DIER_CC1DMA_MSK BIT(TIMER_DIER_CC1DMA_POS) - -#define TIMER_DIER_UDMA_POS 8U -#define TIMER_DIER_UDMA_MSK BIT(TIMER_DIER_UDMA_POS) - -#define TIMER_DIER_BRKIT_POS 7U -#define TIMER_DIER_BRKIT_MSK BIT(TIMER_DIER_BRKIT_POS) - -#define TIMER_DIER_TRGIT_POS 6U -#define TIMER_DIER_TRGIT_MSK BIT(TIMER_DIER_TRGIT_POS) - -#define TIMER_DIER_COMIT_POS 5U -#define TIMER_DIER_COMIT_MSK BIT(TIMER_DIER_COMIT_POS) - -#define TIMER_DIER_CC4IT_POS 4U -#define TIMER_DIER_CC4IT_MSK BIT(TIMER_DIER_CC4IT_POS) - -#define TIMER_DIER_CC3IT_POS 3U -#define TIMER_DIER_CC3IT_MSK BIT(TIMER_DIER_CC3IT_POS) - -#define TIMER_DIER_CC2IT_POS 2U -#define TIMER_DIER_CC2IT_MSK BIT(TIMER_DIER_CC2IT_POS) - -#define TIMER_DIER_CC1IT_POS 1U -#define TIMER_DIER_CC1IT_MSK BIT(TIMER_DIER_CC1IT_POS) - -#define TIMER_DIER_UIT_POS 0U -#define TIMER_DIER_UIT_MSK BIT(TIMER_DIER_UIT_POS) - -/****************** Bit definition for TIMER_DIDR register ************************/ - -#define TIMER_DIDR_TRGDMA_POS 14U -#define TIMER_DIDR_TRGDMA_MSK BIT(TIMER_DIDR_TRGDMA_POS) - -#define TIMER_DIDR_COMD_POS 13U -#define TIMER_DIDR_COMD_MSK BIT(TIMER_DIDR_COMD_POS) - -#define TIMER_DIDR_CC4D_POS 12U -#define TIMER_DIDR_CC4D_MSK BIT(TIMER_DIDR_CC4D_POS) - -#define TIMER_DIDR_CC3D_POS 11U -#define TIMER_DIDR_CC3D_MSK BIT(TIMER_DIDR_CC3D_POS) - -#define TIMER_DIDR_CC2D_POS 10U -#define TIMER_DIDR_CC2D_MSK BIT(TIMER_DIDR_CC2D_POS) - -#define TIMER_DIDR_CC1D_POS 9U -#define TIMER_DIDR_CC1D_MSK BIT(TIMER_DIDR_CC1D_POS) - -#define TIMER_DIDR_UD_POS 8U -#define TIMER_DIDR_UD_MSK BIT(TIMER_DIDR_UD_POS) - -#define TIMER_DIDR_BRKI_POS 7U -#define TIMER_DIDR_BRKI_MSK BIT(TIMER_DIDR_BRKI_POS) - -#define TIMER_DIDR_TRGI_POS 6U -#define TIMER_DIDR_TRGI_MSK BIT(TIMER_DIDR_TRGI_POS) - -#define TIMER_DIDR_COMI_POS 5U -#define TIMER_DIDR_COMI_MSK BIT(TIMER_DIDR_COMI_POS) - -#define TIMER_DIDR_CC4I_POS 4U -#define TIMER_DIDR_CC4I_MSK BIT(TIMER_DIDR_CC4I_POS) - -#define TIMER_DIDR_CC3I_POS 3U -#define TIMER_DIDR_CC3I_MSK BIT(TIMER_DIDR_CC3I_POS) - -#define TIMER_DIDR_CC2I_POS 2U -#define TIMER_DIDR_CC2I_MSK BIT(TIMER_DIDR_CC2I_POS) - -#define TIMER_DIDR_CC1I_POS 1U -#define TIMER_DIDR_CC1I_MSK BIT(TIMER_DIDR_CC1I_POS) - -#define TIMER_DIDR_UI_POS 0U -#define TIMER_DIDR_UI_MSK BIT(TIMER_DIDR_UI_POS) - -/****************** Bit definition for TIMER_DIVS register ************************/ - -#define TIMER_DIVS_TRGDMA_POS 14U -#define TIMER_DIVS_TRGDMA_MSK BIT(TIMER_DIVS_TRGDMA_POS) - -#define TIMER_DIVS_COMDMA_POS 13U -#define TIMER_DIVS_COMDMA_MSK BIT(TIMER_DIVS_COMDMA_POS) - -#define TIMER_DIVS_CC4DMA_POS 12U -#define TIMER_DIVS_CC4DMA_MSK BIT(TIMER_DIVS_CC4DMA_POS) - -#define TIMER_DIVS_CC3DMA_POS 11U -#define TIMER_DIVS_CC3DMA_MSK BIT(TIMER_DIVS_CC3DMA_POS) - -#define TIMER_DIVS_CC2DMA_POS 10U -#define TIMER_DIVS_CC2DMA_MSK BIT(TIMER_DIVS_CC2DMA_POS) - -#define TIMER_DIVS_CC1DMA_POS 9U -#define TIMER_DIVS_CC1DMA_MSK BIT(TIMER_DIVS_CC1DMA_POS) - -#define TIMER_DIVS_UEDTR_POS 8U -#define TIMER_DIVS_UEDTR_MSK BIT(TIMER_DIVS_UEDTR_POS) - -#define TIMER_DIVS_BKI_POS 7U -#define TIMER_DIVS_BKI_MSK BIT(TIMER_DIVS_BKI_POS) - -#define TIMER_DIVS_TRGI_POS 6U -#define TIMER_DIVS_TRGI_MSK BIT(TIMER_DIVS_TRGI_POS) - -#define TIMER_DIVS_COMI_POS 5U -#define TIMER_DIVS_COMI_MSK BIT(TIMER_DIVS_COMI_POS) - -#define TIMER_DIVS_CC4I_POS 4U -#define TIMER_DIVS_CC4I_MSK BIT(TIMER_DIVS_CC4I_POS) - -#define TIMER_DIVS_CC3I_POS 3U -#define TIMER_DIVS_CC3I_MSK BIT(TIMER_DIVS_CC3I_POS) - -#define TIMER_DIVS_CC2I_POS 2U -#define TIMER_DIVS_CC2I_MSK BIT(TIMER_DIVS_CC2I_POS) - -#define TIMER_DIVS_CC1I_POS 1U -#define TIMER_DIVS_CC1I_MSK BIT(TIMER_DIVS_CC1I_POS) - -#define TIMER_DIVS_UEI_POS 0U -#define TIMER_DIVS_UEI_MSK BIT(TIMER_DIVS_UEI_POS) - -/****************** Bit definition for TIMER_RIF register ************************/ - -#define TIMER_RIF_CH4OVIF_POS 12U -#define TIMER_RIF_CH4OVIF_MSK BIT(TIMER_RIF_CH4OVIF_POS) - -#define TIMER_RIF_CH3OVIF_POS 11U -#define TIMER_RIF_CH3OVIF_MSK BIT(TIMER_RIF_CH3OVIF_POS) - -#define TIMER_RIF_CH2OVIF_POS 10U -#define TIMER_RIF_CH2OVIF_MSK BIT(TIMER_RIF_CH2OVIF_POS) - -#define TIMER_RIF_CH1OVIF_POS 9U -#define TIMER_RIF_CH1OVIF_MSK BIT(TIMER_RIF_CH1OVIF_POS) - -#define TIMER_RIF_BRKIF_POS 7U -#define TIMER_RIF_BRKIF_MSK BIT(TIMER_RIF_BRKIF_POS) - -#define TIMER_RIF_TRGIF_POS 6U -#define TIMER_RIF_TRGIF_MSK BIT(TIMER_RIF_TRGIF_POS) - -#define TIMER_RIF_COMIF_POS 5U -#define TIMER_RIF_COMIF_MSK BIT(TIMER_RIF_COMIF_POS) - -#define TIMER_RIF_CH4IF_POS 4U -#define TIMER_RIF_CH4IF_MSK BIT(TIMER_RIF_CH4IF_POS) - -#define TIMER_RIF_CH3IF_POS 3U -#define TIMER_RIF_CH3IF_MSK BIT(TIMER_RIF_CH3IF_POS) - -#define TIMER_RIF_CH2IF_POS 2U -#define TIMER_RIF_CH2IF_MSK BIT(TIMER_RIF_CH2IF_POS) - -#define TIMER_RIF_CH1IF_POS 1U -#define TIMER_RIF_CH1IF_MSK BIT(TIMER_RIF_CH1IF_POS) - -#define TIMER_RIF_UEVTIF_POS 0U -#define TIMER_RIF_UEVTIF_MSK BIT(TIMER_RIF_UEVTIF_POS) - -/****************** Bit definition for TIMER_IFM register ************************/ - -#define TIMER_IFM_BRKIM_POS 7U -#define TIMER_IFM_BRKIM_MSK BIT(TIMER_IFM_BRKIM_POS) - -#define TIMER_IFM_TRGI_POS 6U -#define TIMER_IFM_TRGI_MSK BIT(TIMER_IFM_TRGI_POS) - -#define TIMER_IFM_COMI_POS 5U -#define TIMER_IFM_COMI_MSK BIT(TIMER_IFM_COMI_POS) - -#define TIMER_IFM_CH4CCI_POS 4U -#define TIMER_IFM_CH4CCI_MSK BIT(TIMER_IFM_CH4CCI_POS) - -#define TIMER_IFM_CH3CCI_POS 3U -#define TIMER_IFM_CH3CCI_MSK BIT(TIMER_IFM_CH3CCI_POS) - -#define TIMER_IFM_CH2CCI_POS 2U -#define TIMER_IFM_CH2CCI_MSK BIT(TIMER_IFM_CH2CCI_POS) - -#define TIMER_IFM_CH1CCI_POS 1U -#define TIMER_IFM_CH1CCI_MSK BIT(TIMER_IFM_CH1CCI_POS) - -#define TIMER_IFM_UEI_POS 0U -#define TIMER_IFM_UEI_MSK BIT(TIMER_IFM_UEI_POS) - -/****************** Bit definition for TIMER_ICR register ************************/ - -#define TIMER_ICR_BRKIC_POS 7U -#define TIMER_ICR_BRKIC_MSK BIT(TIMER_ICR_BRKIC_POS) - -#define TIMER_ICR_TRGIC_POS 6U -#define TIMER_ICR_TRGIC_MSK BIT(TIMER_ICR_TRGIC_POS) - -#define TIMER_ICR_COMIC_POS 5U -#define TIMER_ICR_COMIC_MSK BIT(TIMER_ICR_COMIC_POS) - -#define TIMER_ICR_CH4CCIC_POS 4U -#define TIMER_ICR_CH4CCIC_MSK BIT(TIMER_ICR_CH4CCIC_POS) - -#define TIMER_ICR_CH3CCIC_POS 3U -#define TIMER_ICR_CH3CCIC_MSK BIT(TIMER_ICR_CH3CCIC_POS) - -#define TIMER_ICR_CH2CCIC_POS 2U -#define TIMER_ICR_CH2CCIC_MSK BIT(TIMER_ICR_CH2CCIC_POS) - -#define TIMER_ICR_CH1CCIC_POS 1U -#define TIMER_ICR_CH1CCIC_MSK BIT(TIMER_ICR_CH1CCIC_POS) - -#define TIMER_ICR_UEIC_POS 0U -#define TIMER_ICR_UEIC_MSK BIT(TIMER_ICR_UEIC_POS) - -/****************** Bit definition for TIMER_SGE register ************************/ - -#define TIMER_SGE_SGBRK_POS 7U -#define TIMER_SGE_SGBRK_MSK BIT(TIMER_SGE_SGBRK_POS) - -#define TIMER_SGE_SGTRG_POS 6U -#define TIMER_SGE_SGTRG_MSK BIT(TIMER_SGE_SGTRG_POS) - -#define TIMER_SGE_SGCOM_POS 5U -#define TIMER_SGE_SGCOM_MSK BIT(TIMER_SGE_SGCOM_POS) - -#define TIMER_SGE_SGCC4E_POS 4U -#define TIMER_SGE_SGCC4E_MSK BIT(TIMER_SGE_SGCC4E_POS) - -#define TIMER_SGE_SGCC3E_POS 3U -#define TIMER_SGE_SGCC3E_MSK BIT(TIMER_SGE_SGCC3E_POS) - -#define TIMER_SGE_SGCC2E_POS 2U -#define TIMER_SGE_SGCC2E_MSK BIT(TIMER_SGE_SGCC2E_POS) - -#define TIMER_SGE_SGCC1E_POS 1U -#define TIMER_SGE_SGCC1E_MSK BIT(TIMER_SGE_SGCC1E_POS) - -#define TIMER_SGE_SGU_POS 0U -#define TIMER_SGE_SGU_MSK BIT(TIMER_SGE_SGU_POS) - -/****************** Bit definition for TIMER_CHMR1 register ************************/ -/* Output */ -#define TIMER_CHMR1_CH2OCLREN_POS 15U -#define TIMER_CHMR1_CH2OCLREN_MSK BIT(TIMER_CHMR1_CH2OCLREN_POS) - -#define TIMER_CHMR1_CH2OMOD_POSS 12U -#define TIMER_CHMR1_CH2OMOD_POSE 14U -#define TIMER_CHMR1_CH2OMOD_MSK BITS(TIMER_CHMR1_CH2OMOD_POSS,TIMER_CHMR1_CH2OMOD_POSE) - -#define TIMER_CHMR1_CH2OPEN_POS 11U -#define TIMER_CHMR1_CH2OPEN_MSK BIT(TIMER_CHMR1_CH2OPEN_POS) - -#define TIMER_CHMR1_CH2OFEN_POS 10U -#define TIMER_CHMR1_CH2OFEN_MSK BIT(TIMER_CHMR1_CH2OFEN_POS) - -#define TIMER_CHMR1_CC2SSEL_POSS 8U -#define TIMER_CHMR1_CC2SSEL_POSE 9U -#define TIMER_CHMR1_CC2SSEL_MSK BITS(TIMER_CHMR1_CC2SSEL_POSS,TIMER_CHMR1_CC2SSEL_POSE) - -#define TIMER_CHMR1_CH1OCLREN_POS 7U -#define TIMER_CHMR1_CH1OCLREN_MSK BIT(TIMER_CHMR1_CH1OCLREN_POS) - -#define TIMER_CHMR1_CH1OMOD_POSS 4U -#define TIMER_CHMR1_CH1OMOD_POSE 6U -#define TIMER_CHMR1_CH1OMOD_MSK BITS(TIMER_CHMR1_CH1OMOD_POSS,TIMER_CHMR1_CH1OMOD_POSE) - -#define TIMER_CHMR1_CH1OPREN_POS 3U -#define TIMER_CHMR1_CH1OPREN_MSK BIT(TIMER_CHMR1_CH1OPREN_POS) - -#define TIMER_CHMR1_CH1OHSEN_POS 2U -#define TIMER_CHMR1_CH1OHSEN_MSK BIT(TIMER_CHMR1_CH1OHSEN_POS) - -#define TIMER_CHMR1_CC1SSEL_POSS 0U -#define TIMER_CHMR1_CC1SSEL_POSE 1U -#define TIMER_CHMR1_CC1SSEL_MSK BITS(TIMER_CHMR1_CC1SSEL_POSS,TIMER_CHMR1_CC1SSEL_POSE) - -/* Input */ -#define TIMER_CHMR1_I2FLT_POSS 12U -#define TIMER_CHMR1_I2FLT_POSE 15U -#define TIMER_CHMR1_I2FLT_MSK BITS(TIMER_CHMR1_I2FLT_POSS,TIMER_CHMR1_I2FLT_POSE) - -#define TIMER_CHMR1_IC2PRES_POSS 10U -#define TIMER_CHMR1_IC2PRES_POSE 11U -#define TIMER_CHMR1_IC2PRES_MSK BITS(TIMER_CHMR1_IC2PRES_POSS,TIMER_CHMR1_IC2PRES_POSE) - -#define TIMER_CHMR1_CC2SSEL_POSS 8U -#define TIMER_CHMR1_CC2SSEL_POSE 9U -#define TIMER_CHMR1_CC2SSEL_MSK BITS(TIMER_CHMR1_CC2SSEL_POSS,TIMER_CHMR1_CC2SSEL_POSE) - -#define TIMER_CHMR1_I1FLT_POSS 4U -#define TIMER_CHMR1_I1FLT_POSE 7U -#define TIMER_CHMR1_I1FLT_MSK BITS(TIMER_CHMR1_I1FLT_POSS,TIMER_CHMR1_I1FLT_POSE) - -#define TIMER_CHMR1_IC1PRES_POSS 2U -#define TIMER_CHMR1_IC1PRES_POSE 3U -#define TIMER_CHMR1_IC1PRES_MSK BITS(TIMER_CHMR1_IC1PRES_POSS,TIMER_CHMR1_IC1PRES_POSE) - -#define TIMER_CHMR1_CC1SSEL_POSS 0U -#define TIMER_CHMR1_CC1SSEL_POSE 1U -#define TIMER_CHMR1_CC1SSEL_MSK BITS(TIMER_CHMR1_CC1SSEL_POSS,TIMER_CHMR1_CC1SSEL_POSE) - -/****************** Bit definition for TIMER_CHMR2 register ************************/ -/* Output */ -#define TIMER_CHMR2_CH4OCLREN_POS 15U -#define TIMER_CHMR2_CH4OCLREN_MSK BIT(TIMER_CHMR2_CH4OCLREN_POS) - -#define TIMER_CHMR2_CH4OMOD_POSS 12U -#define TIMER_CHMR2_CH4OMOD_POSE 14U -#define TIMER_CHMR2_CH4OMOD_MSK BITS(TIMER_CHMR2_CH4OMOD_POSS,TIMER_CHMR2_CH4OMOD_POSE) - -#define TIMER_CHMR2_CH4OPEN_POS 11U -#define TIMER_CHMR2_CH4OPEN_MSK BIT(TIMER_CHMR2_CH4OPEN_POS) - -#define TIMER_CHMR2_CH4OHSEN_POS 10U -#define TIMER_CHMR2_CH4OHSEN_MSK BIT(TIMER_CHMR2_CH4OHSEN_POS) - -#define TIMER_CHMR2_CC4SSEL_POSS 8U -#define TIMER_CHMR2_CC4SSEL_POSE 9U -#define TIMER_CHMR2_CC4SSEL_MSK BITS(TIMER_CHMR2_CC4SSEL_POSS,TIMER_CHMR2_CC4SSEL_POSE) - -#define TIMER_CHMR2_CH3OCLREN_POS 7U -#define TIMER_CHMR2_CH3OCLREN_MSK BIT(TIMER_CHMR2_CH3OCLREN_POS) - -#define TIMER_CHMR2_CH3OMOD_POSS 4U -#define TIMER_CHMR2_CH3OMOD_POSE 6U -#define TIMER_CHMR2_CH3OMOD_MSK BITS(TIMER_CHMR2_CH3OMOD_POSS,TIMER_CHMR2_CH3OMOD_POSE) - -#define TIMER_CHMR2_CH3OPEN_POS 3U -#define TIMER_CHMR2_CH3OPEN_MSK BIT(TIMER_CHMR2_CH3OPEN_POS) - -#define TIMER_CHMR2_CH3OFEN_POS 2U -#define TIMER_CHMR2_CH3OFEN_MSK BIT(TIMER_CHMR2_CH3OFEN_POS) - -#define TIMER_CHMR2_CC3SSEL_POSS 0U -#define TIMER_CHMR2_CC3SSEL_POSE 1U -#define TIMER_CHMR2_CC3SSEL_MSK BITS(TIMER_CHMR2_CC3SSEL_POSS,TIMER_CHMR2_CC3SSEL_POSE) - -/* Input */ -#define TIMER_CHMR2_I4FLT_POSS 12U -#define TIMER_CHMR2_I4FLT_POSE 15U -#define TIMER_CHMR2_I4FLT_MSK BITS(TIMER_CHMR2_I4FLT_POSS,TIMER_CHMR2_I4FLT_POSE) - -#define TIMER_CHMR2_IC4PRES_POSS 10U -#define TIMER_CHMR2_IC4PRES_POSE 11U -#define TIMER_CHMR2_IC4PRES_MSK BITS(TIMER_CHMR2_IC4PRES_POSS,TIMER_CHMR2_IC4PRES_POSE) - -#define TIMER_CHMR2_CC4SSEL_POSS 8U -#define TIMER_CHMR2_CC4SSEL_POSE 9U -#define TIMER_CHMR2_CC4SSEL_MSK BITS(TIMER_CHMR2_CC4SSEL_POSS,TIMER_CHMR2_CC4SSEL_POSE) - -#define TIMER_CHMR2_I3FLT_POSS 4U -#define TIMER_CHMR2_I3FLT_POSE 7U -#define TIMER_CHMR2_I3FLT_MSK BITS(TIMER_CHMR2_I3FLT_POSS,TIMER_CHMR2_I3FLT_POSE) - -#define TIMER_CHMR2_IC3PRES_POSS 2U -#define TIMER_CHMR2_IC3PRES_POSE 3U -#define TIMER_CHMR2_IC3PRES_MSK BITS(TIMER_CHMR2_IC3PRES_POSS,TIMER_CHMR2_IC3PRES_POSE) - -#define TIMER_CHMR2_CC3SSEL_POSS 0U -#define TIMER_CHMR2_CC3SSEL_POSE 1U -#define TIMER_CHMR2_CC3SSEL_MSK BITS(TIMER_CHMR2_CC3SSEL_POSS,TIMER_CHMR2_CC3SSEL_POSE) - -/****************** Bit definition for TIMER_CCEP register ************************/ - -#define TIMER_CCEP_CC4POL_POS 13U -#define TIMER_CCEP_CC4POL_MSK BIT(TIMER_CCEP_CC4POL_POS) - -#define TIMER_CCEP_CC4EN_POS 12U -#define TIMER_CCEP_CC4EN_MSK BIT(TIMER_CCEP_CC4EN_POS) - -#define TIMER_CCEP_CC3NPOL_POS 11U -#define TIMER_CCEP_CC3NPOL_MSK BIT(TIMER_CCEP_CC3NPOL_POS) - -#define TIMER_CCEP_CC3NEN_POS 10U -#define TIMER_CCEP_CC3NEN_MSK BIT(TIMER_CCEP_CC3NEN_POS) - -#define TIMER_CCEP_CC3POL_POS 9U -#define TIMER_CCEP_CC3POL_MSK BIT(TIMER_CCEP_CC3POL_POS) - -#define TIMER_CCEP_CC3EN_POS 8U -#define TIMER_CCEP_CC3EN_MSK BIT(TIMER_CCEP_CC3EN_POS) - -#define TIMER_CCEP_CC2NPOL_POS 7U -#define TIMER_CCEP_CC2NPOL_MSK BIT(TIMER_CCEP_CC2NPOL_POS) - -#define TIMER_CCEP_CC2NEN_POS 6U -#define TIMER_CCEP_CC2NEN_MSK BIT(TIMER_CCEP_CC2NEN_POS) - -#define TIMER_CCEP_CC2POL_POS 5U -#define TIMER_CCEP_CC2POL_MSK BIT(TIMER_CCEP_CC2POL_POS) - -#define TIMER_CCEP_CC2EN_POS 4U -#define TIMER_CCEP_CC2EN_MSK BIT(TIMER_CCEP_CC2EN_POS) - -#define TIMER_CCEP_CC1NPOL_POS 3U -#define TIMER_CCEP_CC1NPOL_MSK BIT(TIMER_CCEP_CC1NPOL_POS) - -#define TIMER_CCEP_CC1NEN_POS 2U -#define TIMER_CCEP_CC1NEN_MSK BIT(TIMER_CCEP_CC1NEN_POS) - -#define TIMER_CCEP_CC1POL_POS 1U -#define TIMER_CCEP_CC1POL_MSK BIT(TIMER_CCEP_CC1POL_POS) - -#define TIMER_CCEP_CC1EN_POS 0U -#define TIMER_CCEP_CC1EN_MSK BIT(TIMER_CCEP_CC1EN_POS) - -/****************** Bit definition for TIMER_COUNT register ************************/ - -#define TIMER_COUNT_CNTV_POSS 0U -#define TIMER_COUNT_CNTV_POSE 15U -#define TIMER_COUNT_CNTV_MSK BITS(TIMER_COUNT_CNTV_POSS,TIMER_COUNT_CNTV_POSE) - -/****************** Bit definition for TIMER_PRES register ************************/ - -#define TIMER_PRES_PSCV_POSS 0U -#define TIMER_PRES_PSCV_POSE 15U -#define TIMER_PRES_PSCV_MSK BITS(TIMER_PRES_PSCV_POSS,TIMER_PRES_PSCV_POSE) - -/****************** Bit definition for TIMER_AR register ************************/ - -#define TIMER_AR_ARRV_POSS 0U -#define TIMER_AR_ARRV_POSE 15U -#define TIMER_AR_ARRV_MSK BITS(TIMER_AR_ARRV_POSS,TIMER_AR_ARRV_POSE) - -/****************** Bit definition for TIMER_REPAR register ************************/ - -#define TIMER_REPAR_REPV_POSS 0U -#define TIMER_REPAR_REPV_POSE 7U -#define TIMER_REPAR_REPV_MSK BITS(TIMER_REPAR_REPV_POSS,TIMER_REPAR_REPV_POSE) - -/****************** Bit definition for TIMER_CCVAL1 register ************************/ - -#define TIMER_CCVAL1_CCRV1_POSS 0U -#define TIMER_CCVAL1_CCRV1_POSE 15U -#define TIMER_CCVAL1_CCRV1_MSK BITS(TIMER_CCVAL1_CCRV1_POSS,TIMER_CCVAL1_CCRV1_POSE) - -/****************** Bit definition for TIMER_CCVAL2 register ************************/ - -#define TIMER_CCVAL2_CCRV2_POSS 0U -#define TIMER_CCVAL2_CCRV2_POSE 15U -#define TIMER_CCVAL2_CCRV2_MSK BITS(TIMER_CCVAL2_CCRV2_POSS,TIMER_CCVAL2_CCRV2_POSE) - -/****************** Bit definition for TIMER_CCVAL3 register ************************/ - -#define TIMER_CCVAL3_CCRV3_POSS 0U -#define TIMER_CCVAL3_CCRV3_POSE 15U -#define TIMER_CCVAL3_CCRV3_MSK BITS(TIMER_CCVAL3_CCRV3_POSS,TIMER_CCVAL3_CCRV3_POSE) - -/****************** Bit definition for TIMER_CCVAL4 register ************************/ - -#define TIMER_CCVAL4_CCRV4_POSS 0U -#define TIMER_CCVAL4_CCRV4_POSE 15U -#define TIMER_CCVAL4_CCRV4_MSK BITS(TIMER_CCVAL4_CCRV4_POSS,TIMER_CCVAL4_CCRV4_POSE) - -/****************** Bit definition for TIMER_BDCFG register ************************/ - -#define TIMER_BDCFG_GOEN_POS 15U -#define TIMER_BDCFG_GOEN_MSK BIT(TIMER_BDCFG_GOEN_POS) - -#define TIMER_BDCFG_AOEN_POS 14U -#define TIMER_BDCFG_AOEN_MSK BIT(TIMER_BDCFG_AOEN_POS) - -#define TIMER_BDCFG_BRKP_POS 13U -#define TIMER_BDCFG_BRKP_MSK BIT(TIMER_BDCFG_BRKP_POS) - -#define TIMER_BDCFG_BRKEN_POS 12U -#define TIMER_BDCFG_BRKEN_MSK BIT(TIMER_BDCFG_BRKEN_POS) - -#define TIMER_BDCFG_OFFSSR_POS 11U -#define TIMER_BDCFG_OFFSSR_MSK BIT(TIMER_BDCFG_OFFSSR_POS) - -#define TIMER_BDCFG_OFFSSI_POS 10U -#define TIMER_BDCFG_OFFSSI_MSK BIT(TIMER_BDCFG_OFFSSI_POS) - -#define TIMER_BDCFG_LOCKLVL_POSS 8U -#define TIMER_BDCFG_LOCKLVL_POSE 9U -#define TIMER_BDCFG_LOCKLVL_MSK BITS(TIMER_BDCFG_LOCKLVL_POSS,TIMER_BDCFG_LOCKLVL_POSE) - -#define TIMER_BDCFG_DT_POSS 0U -#define TIMER_BDCFG_DT_POSE 7U -#define TIMER_BDCFG_DT_MSK BITS(TIMER_BDCFG_DT_POSS,TIMER_BDCFG_DT_POSE) - -typedef struct -{ - __IO uint32_t CON1; - __IO uint32_t CON2; - __IO uint32_t SMCON; - __O uint32_t DIER; - __O uint32_t DIDR; - __I uint32_t DIVS; - __I uint32_t RIF; - __I uint32_t IFM; - __O uint32_t ICR; - __O uint32_t SGE; - __IO uint32_t CHMR1; - __IO uint32_t CHMR2; - __IO uint32_t CCEP; - __IO uint32_t COUNT; - __IO uint32_t PRES; - __IO uint32_t AR; - __IO uint32_t REPAR; - __IO uint32_t CCVAL1; - __IO uint32_t CCVAL2; - __IO uint32_t CCVAL3; - __IO uint32_t CCVAL4; - __IO uint32_t BDCFG; -} TIMER_TypeDef; - -/****************** Bit definition for USART_STAT register ************************/ - -#define USART_STAT_CTSIF_POS 9U -#define USART_STAT_CTSIF_MSK BIT(USART_STAT_CTSIF_POS) - -#define USART_STAT_TXEMPIF_POS 7U -#define USART_STAT_TXEMPIF_MSK BIT(USART_STAT_TXEMPIF_POS) - -#define USART_STAT_TXCIF_POS 6U -#define USART_STAT_TXCIF_MSK BIT(USART_STAT_TXCIF_POS) - -#define USART_STAT_RXNEIF_POS 5U -#define USART_STAT_RXNEIF_MSK BIT(USART_STAT_RXNEIF_POS) - -#define USART_STAT_IDLEIF_POS 4U -#define USART_STAT_IDLEIF_MSK BIT(USART_STAT_IDLEIF_POS) - -#define USART_STAT_OVRIF_POS 3U -#define USART_STAT_OVRIF_MSK BIT(USART_STAT_OVRIF_POS) - -#define USART_STAT_NDETIF_POS 2U -#define USART_STAT_NDETIF_MSK BIT(USART_STAT_NDETIF_POS) - -#define USART_STAT_FERRIF_POS 1U -#define USART_STAT_FERRIF_MSK BIT(USART_STAT_FERRIF_POS) - -#define USART_STAT_PERRIF_POS 0U -#define USART_STAT_PERRIF_MSK BIT(USART_STAT_PERRIF_POS) - -/****************** Bit definition for USART_DATA register ************************/ - -#define USART_DATA_VAL_POSS 0U -#define USART_DATA_VAL_POSE 8U -#define USART_DATA_VAL_MSK BITS(USART_DATA_VAL_POSS,USART_DATA_VAL_POSE) - -/****************** Bit definition for USART_BAUDCON register ************************/ - -#define USART_BAUDCON_DIV_M_POSS 4U -#define USART_BAUDCON_DIV_M_POSE 15U -#define USART_BAUDCON_DIV_M_MSK BITS(USART_BAUDCON_DIV_M_POSS,USART_BAUDCON_DIV_M_POSE) - -#define USART_BAUDCON_DIV_F_POSS 0U -#define USART_BAUDCON_DIV_F_POSE 3U -#define USART_BAUDCON_DIV_F_MSK BITS(USART_BAUDCON_DIV_F_POSS,USART_BAUDCON_DIV_F_POSE) - -/****************** Bit definition for USART_CON0 register ************************/ - -#define USART_CON0_EN_POS 13U -#define USART_CON0_EN_MSK BIT(USART_CON0_EN_POS) - -#define USART_CON0_DLEN_POS 12U -#define USART_CON0_DLEN_MSK BIT(USART_CON0_DLEN_POS) - -#define USART_CON0_WKMOD_POS 11U -#define USART_CON0_WKMOD_MSK BIT(USART_CON0_WKMOD_POS) - -#define USART_CON0_PEN_POS 10U -#define USART_CON0_PEN_MSK BIT(USART_CON0_PEN_POS) - -#define USART_CON0_PSEL_POS 9U -#define USART_CON0_PSEL_MSK BIT(USART_CON0_PSEL_POS) - -#define USART_CON0_PERRIE_POS 8U -#define USART_CON0_PERRIE_MSK BIT(USART_CON0_PERRIE_POS) - -#define USART_CON0_TXEMPIE_POS 7U -#define USART_CON0_TXEMPIE_MSK BIT(USART_CON0_TXEMPIE_POS) - -#define USART_CON0_TXCIE_POS 6U -#define USART_CON0_TXCIE_MSK BIT(USART_CON0_TXCIE_POS) - -#define USART_CON0_RXNEIE_POS 5U -#define USART_CON0_RXNEIE_MSK BIT(USART_CON0_RXNEIE_POS) - -#define USART_CON0_IDLEIE_POS 4U -#define USART_CON0_IDLEIE_MSK BIT(USART_CON0_IDLEIE_POS) - -#define USART_CON0_TXEN_POS 3U -#define USART_CON0_TXEN_MSK BIT(USART_CON0_TXEN_POS) - -#define USART_CON0_RXEN_POS 2U -#define USART_CON0_RXEN_MSK BIT(USART_CON0_RXEN_POS) - -#define USART_CON0_RXWK_POS 1U -#define USART_CON0_RXWK_MSK BIT(USART_CON0_RXWK_POS) - -/****************** Bit definition for USART_CON1 register ************************/ - -#define USART_CON1_STPLEN_POSS 12U -#define USART_CON1_STPLEN_POSE 13U -#define USART_CON1_STPLEN_MSK BITS(USART_CON1_STPLEN_POSS,USART_CON1_STPLEN_POSE) - -#define USART_CON1_SCKEN_POS 11U -#define USART_CON1_SCKEN_MSK BIT(USART_CON1_SCKEN_POS) - -#define USART_CON1_SCKPOL_POS 10U -#define USART_CON1_SCKPOL_MSK BIT(USART_CON1_SCKPOL_POS) - -#define USART_CON1_SCKPHA_POS 9U -#define USART_CON1_SCKPHA_MSK BIT(USART_CON1_SCKPHA_POS) - -#define USART_CON1_LBCP_POS 8U -#define USART_CON1_LBCP_MSK BIT(USART_CON1_LBCP_POS) - -#define USART_CON1_ADDR_POSS 0U -#define USART_CON1_ADDR_POSE 3U -#define USART_CON1_ADDR_MSK BITS(USART_CON1_ADDR_POSS,USART_CON1_ADDR_POSE) - -/****************** Bit definition for USART_CON2 register ************************/ - -#define USART_CON2_CTSIE_POS 10U -#define USART_CON2_CTSIE_MSK BIT(USART_CON2_CTSIE_POS) - -#define USART_CON2_CTSEN_POS 9U -#define USART_CON2_CTSEN_MSK BIT(USART_CON2_CTSEN_POS) - -#define USART_CON2_RTSEN_POS 8U -#define USART_CON2_RTSEN_MSK BIT(USART_CON2_RTSEN_POS) - -#define USART_CON2_TXDMAEN_POS 7U -#define USART_CON2_TXDMAEN_MSK BIT(USART_CON2_TXDMAEN_POS) - -#define USART_CON2_RXDMAEN_POS 6U -#define USART_CON2_RXDMAEN_MSK BIT(USART_CON2_RXDMAEN_POS) - -#define USART_CON2_SMARTEN_POS 5U -#define USART_CON2_SMARTEN_MSK BIT(USART_CON2_SMARTEN_POS) - -#define USART_CON2_NACK_POS 4U -#define USART_CON2_NACK_MSK BIT(USART_CON2_NACK_POS) - -#define USART_CON2_HDPSEL_POS 3U -#define USART_CON2_HDPSEL_MSK BIT(USART_CON2_HDPSEL_POS) - -#define USART_CON2_IREN_POS 1U -#define USART_CON2_IREN_MSK BIT(USART_CON2_IREN_POS) - -#define USART_CON2_ERRIE_POS 0U -#define USART_CON2_ERRIE_MSK BIT(USART_CON2_ERRIE_POS) - -/****************** Bit definition for USART_GP register ************************/ - -#define USART_GP_GTVAL_POSS 8U -#define USART_GP_GTVAL_POSE 15U -#define USART_GP_GTVAL_MSK BITS(USART_GP_GTVAL_POSS,USART_GP_GTVAL_POSE) - -#define USART_GP_PSC_POSS 0U -#define USART_GP_PSC_POSE 7U -#define USART_GP_PSC_MSK BITS(USART_GP_PSC_POSS,USART_GP_PSC_POSE) - -typedef struct -{ - __IO uint32_t STAT; - __IO uint32_t DATA; - __IO uint32_t BAUDCON; - __IO uint32_t CON0; - __IO uint32_t CON1; - __IO uint32_t CON2; - __IO uint32_t GP; -} USART_TypeDef; - -/****************** Bit definition for UART_RBR register ************************/ - -#define UART_RBR_RBR_POSS 0U -#define UART_RBR_RBR_POSE 8U -#define UART_RBR_RBR_MSK BITS(UART_RBR_RBR_POSS,UART_RBR_RBR_POSE) - -/****************** Bit definition for UART_TBR register ************************/ - -#define UART_TBR_TBR_POSS 0U -#define UART_TBR_TBR_POSE 8U -#define UART_TBR_TBR_MSK BITS(UART_TBR_TBR_POSS,UART_TBR_TBR_POSE) - -/****************** Bit definition for UART_BRR register ************************/ - -#define UART_BRR_BRR_POSS 0U -#define UART_BRR_BRR_POSE 15U -#define UART_BRR_BRR_MSK BITS(UART_BRR_BRR_POSS,UART_BRR_BRR_POSE) - -/****************** Bit definition for UART_LCR register ************************/ - -#define UART_LCR_SWAP_POS 13U -#define UART_LCR_SWAP_MSK BIT(UART_LCR_SWAP_POS) - -#define UART_LCR_TXINV_POS 12U -#define UART_LCR_TXINV_MSK BIT(UART_LCR_TXINV_POS) - -#define UART_LCR_RXINV_POS 11U -#define UART_LCR_RXINV_MSK BIT(UART_LCR_RXINV_POS) - -#define UART_LCR_DATAINV_POS 10U -#define UART_LCR_DATAINV_MSK BIT(UART_LCR_DATAINV_POS) - -#define UART_LCR_MSBFIRST_POS 9U -#define UART_LCR_MSBFIRST_MSK BIT(UART_LCR_MSBFIRST_POS) - -#define UART_LCR_RTOEN_POS 8U -#define UART_LCR_RTOEN_MSK BIT(UART_LCR_RTOEN_POS) - -#define UART_LCR_BRWEN_POS 7U -#define UART_LCR_BRWEN_MSK BIT(UART_LCR_BRWEN_POS) - -#define UART_LCR_BC_POS 6U -#define UART_LCR_BC_MSK BIT(UART_LCR_BC_POS) - -#define UART_LCR_RXEN_POS 5U -#define UART_LCR_RXEN_MSK BIT(UART_LCR_RXEN_POS) - -#define UART_LCR_PS_POS 4U -#define UART_LCR_PS_MSK BIT(UART_LCR_PS_POS) - -#define UART_LCR_PEN_POS 3U -#define UART_LCR_PEN_MSK BIT(UART_LCR_PEN_POS) - -#define UART_LCR_STOP_POS 2U -#define UART_LCR_STOP_MSK BIT(UART_LCR_STOP_POS) - -#define UART_LCR_DLS_POSS 0U -#define UART_LCR_DLS_POSE 1U -#define UART_LCR_DLS_MSK BITS(UART_LCR_DLS_POSS,UART_LCR_DLS_POSE) - -/****************** Bit definition for UART_MCR register ************************/ - -#define UART_MCR_HDSEL_POS 22U -#define UART_MCR_HDSEL_MSK BIT(UART_MCR_HDSEL_POS) - -#define UART_MCR_ABRRS_POS 15U -#define UART_MCR_ABRRS_MSK BIT(UART_MCR_ABRRS_POS) - -#define UART_MCR_ABRMOD_POSS 13U -#define UART_MCR_ABRMOD_POSE 14U -#define UART_MCR_ABRMOD_MSK BITS(UART_MCR_ABRMOD_POSS,UART_MCR_ABRMOD_POSE) - -#define UART_MCR_ABREN_POS 12U -#define UART_MCR_ABREN_MSK BIT(UART_MCR_ABREN_POS) - -#define UART_MCR_DMAEN_POS 11U -#define UART_MCR_DMAEN_MSK BIT(UART_MCR_DMAEN_POS) - -#define UART_MCR_LINBDL_POS 10U -#define UART_MCR_LINBDL_MSK BIT(UART_MCR_LINBDL_POS) - -#define UART_MCR_BKREQ_POS 9U -#define UART_MCR_BKREQ_MSK BIT(UART_MCR_BKREQ_POS) - -#define UART_MCR_LINEN_POS 8U -#define UART_MCR_LINEN_MSK BIT(UART_MCR_LINEN_POS) - -#define UART_MCR_AADINV_POS 7U -#define UART_MCR_AADINV_MSK BIT(UART_MCR_AADINV_POS) - -#define UART_MCR_AADDIR_POS 6U -#define UART_MCR_AADDIR_MSK BIT(UART_MCR_AADDIR_POS) - -#define UART_MCR_AADNOR_POS 5U -#define UART_MCR_AADNOR_MSK BIT(UART_MCR_AADNOR_POS) - -#define UART_MCR_AADEN_POS 4U -#define UART_MCR_AADEN_MSK BIT(UART_MCR_AADEN_POS) - -#define UART_MCR_RTSCTRL_POS 3U -#define UART_MCR_RTSCTRL_MSK BIT(UART_MCR_RTSCTRL_POS) - -#define UART_MCR_AFCEN_POS 2U -#define UART_MCR_AFCEN_MSK BIT(UART_MCR_AFCEN_POS) - -#define UART_MCR_LBEN_POS 1U -#define UART_MCR_LBEN_MSK BIT(UART_MCR_LBEN_POS) - -#define UART_MCR_IREN_POS 0U -#define UART_MCR_IREN_MSK BIT(UART_MCR_IREN_POS) - -/****************** Bit definition for UART_CR register ************************/ - -#define UART_CR_PSC_POSS 16U -#define UART_CR_PSC_POSE 23U -#define UART_CR_PSC_MSK BITS(UART_CR_PSC_POSS,UART_CR_PSC_POSE) - -#define UART_CR_DLY_POSS 8U -#define UART_CR_DLY_POSE 15U -#define UART_CR_DLY_MSK BITS(UART_CR_DLY_POSS,UART_CR_DLY_POSE) - -#define UART_CR_ADDR_POSS 0U -#define UART_CR_ADDR_POSE 7U -#define UART_CR_ADDR_MSK BITS(UART_CR_ADDR_POSS,UART_CR_ADDR_POSE) - -/****************** Bit definition for UART_RTOR register ************************/ - -#define UART_RTOR_BLEN_POSS 24U -#define UART_RTOR_BLEN_POSE 31U -#define UART_RTOR_BLEN_MSK BITS(UART_RTOR_BLEN_POSS,UART_RTOR_BLEN_POSE) - -#define UART_RTOR_RTO_POSS 0U -#define UART_RTOR_RTO_POSE 23U -#define UART_RTOR_RTO_MSK BITS(UART_RTOR_RTO_POSS,UART_RTOR_RTO_POSE) - -/****************** Bit definition for UART_FCR register ************************/ - -#define UART_FCR_TXFL_POSS 12U -#define UART_FCR_TXFL_POSE 15U -#define UART_FCR_TXFL_MSK BITS(UART_FCR_TXFL_POSS,UART_FCR_TXFL_POSE) - -#define UART_FCR_RXFL_POSS 8U -#define UART_FCR_RXFL_POSE 11U -#define UART_FCR_RXFL_MSK BITS(UART_FCR_RXFL_POSS,UART_FCR_RXFL_POSE) - -#define UART_FCR_TXTL_POSS 6U -#define UART_FCR_TXTL_POSE 7U -#define UART_FCR_TXTL_MSK BITS(UART_FCR_TXTL_POSS,UART_FCR_TXTL_POSE) - -#define UART_FCR_RXTL_POSS 4U -#define UART_FCR_RXTL_POSE 5U -#define UART_FCR_RXTL_MSK BITS(UART_FCR_RXTL_POSS,UART_FCR_RXTL_POSE) - -#define UART_FCR_TFRST_POS 2U -#define UART_FCR_TFRST_MSK BIT(UART_FCR_TFRST_POS) - -#define UART_FCR_RFRST_POS 1U -#define UART_FCR_RFRST_MSK BIT(UART_FCR_RFRST_POS) - -#define UART_FCR_FIFOEN_POS 0U -#define UART_FCR_FIFOEN_MSK BIT(UART_FCR_FIFOEN_POS) - -/****************** Bit definition for UART_SR register ************************/ - -#define UART_SR_CTS_POS 14U -#define UART_SR_CTS_MSK BIT(UART_SR_CTS_POS) - -#define UART_SR_DCTS_POS 13U -#define UART_SR_DCTS_MSK BIT(UART_SR_DCTS_POS) - -#define UART_SR_RFF_POS 12U -#define UART_SR_RFF_MSK BIT(UART_SR_RFF_POS) - -#define UART_SR_RFNE_POS 11U -#define UART_SR_RFNE_MSK BIT(UART_SR_RFNE_POS) - -#define UART_SR_TFEM_POS 10U -#define UART_SR_TFEM_MSK BIT(UART_SR_TFEM_POS) - -#define UART_SR_TFNF_POS 9U -#define UART_SR_TFNF_MSK BIT(UART_SR_TFNF_POS) - -#define UART_SR_BUSY_POS 8U -#define UART_SR_BUSY_MSK BIT(UART_SR_BUSY_POS) - -#define UART_SR_RFE_POS 7U -#define UART_SR_RFE_MSK BIT(UART_SR_RFE_POS) - -#define UART_SR_TEM_POS 6U -#define UART_SR_TEM_MSK BIT(UART_SR_TEM_POS) - -#define UART_SR_TBEM_POS 5U -#define UART_SR_TBEM_MSK BIT(UART_SR_TBEM_POS) - -#define UART_SR_BF_POS 4U -#define UART_SR_BF_MSK BIT(UART_SR_BF_POS) - -#define UART_SR_FE_POS 3U -#define UART_SR_FE_MSK BIT(UART_SR_FE_POS) - -#define UART_SR_PE_POS 2U -#define UART_SR_PE_MSK BIT(UART_SR_PE_POS) - -#define UART_SR_OE_POS 1U -#define UART_SR_OE_MSK BIT(UART_SR_OE_POS) - -#define UART_SR_DR_POS 0U -#define UART_SR_DR_MSK BIT(UART_SR_DR_POS) - -/****************** Bit definition for UART_IER register ************************/ - -#define UART_IER_CMIE_POS 11U -#define UART_IER_CMIE_MSK BIT(UART_IER_CMIE_POS) - -#define UART_IER_EOBIE_POS 10U -#define UART_IER_EOBIE_MSK BIT(UART_IER_EOBIE_POS) - -#define UART_IER_TCIE_POS 9U -#define UART_IER_TCIE_MSK BIT(UART_IER_TCIE_POS) - -#define UART_IER_LINBKIE_POS 8U -#define UART_IER_LINBKIE_MSK BIT(UART_IER_LINBKIE_POS) - -#define UART_IER_ABTOIE_POS 7U -#define UART_IER_ABTOIE_MSK BIT(UART_IER_ABTOIE_POS) - -#define UART_IER_ABEIE_POS 6U -#define UART_IER_ABEIE_MSK BIT(UART_IER_ABEIE_POS) - -#define UART_IER_BZIE_POS 5U -#define UART_IER_BZIE_MSK BIT(UART_IER_BZIE_POS) - -#define UART_IER_RTOIE_POS 4U -#define UART_IER_RTOIE_MSK BIT(UART_IER_RTOIE_POS) - -#define UART_IER_MDSIE_POS 3U -#define UART_IER_MDSIE_MSK BIT(UART_IER_MDSIE_POS) - -#define UART_IER_RXSIE_POS 2U -#define UART_IER_RXSIE_MSK BIT(UART_IER_RXSIE_POS) - -#define UART_IER_TXSIE_POS 1U -#define UART_IER_TXSIE_MSK BIT(UART_IER_TXSIE_POS) - -#define UART_IER_RXRDIE_POS 0U -#define UART_IER_RXRDIE_MSK BIT(UART_IER_RXRDIE_POS) - -/****************** Bit definition for UART_IDR register ************************/ - -#define UART_IDR_CMID_POS 11U -#define UART_IDR_CMID_MSK BIT(UART_IDR_CMID_POS) - -#define UART_IDR_EOBID_POS 10U -#define UART_IDR_EOBID_MSK BIT(UART_IDR_EOBID_POS) - -#define UART_IDR_TCID_POS 9U -#define UART_IDR_TCID_MSK BIT(UART_IDR_TCID_POS) - -#define UART_IDR_LINBKID_POS 8U -#define UART_IDR_LINBKID_MSK BIT(UART_IDR_LINBKID_POS) - -#define UART_IDR_ABTOID_POS 7U -#define UART_IDR_ABTOID_MSK BIT(UART_IDR_ABTOID_POS) - -#define UART_IDR_ABEID_POS 6U -#define UART_IDR_ABEID_MSK BIT(UART_IDR_ABEID_POS) - -#define UART_IDR_BZID_POS 5U -#define UART_IDR_BZID_MSK BIT(UART_IDR_BZID_POS) - -#define UART_IDR_RTOID_POS 4U -#define UART_IDR_RTOID_MSK BIT(UART_IDR_RTOID_POS) - -#define UART_IDR_MDSID_POS 3U -#define UART_IDR_MDSID_MSK BIT(UART_IDR_MDSID_POS) - -#define UART_IDR_RXSID_POS 2U -#define UART_IDR_RXSID_MSK BIT(UART_IDR_RXSID_POS) - -#define UART_IDR_TXSID_POS 1U -#define UART_IDR_TXSID_MSK BIT(UART_IDR_TXSID_POS) - -#define UART_IDR_RXRDID_POS 0U -#define UART_IDR_RXRDID_MSK BIT(UART_IDR_RXRDID_POS) - -/****************** Bit definition for UART_IVS register ************************/ - -#define UART_IVS_CMIS_POS 11U -#define UART_IVS_CMIS_MSK BIT(UART_IVS_CMIS_POS) - -#define UART_IVS_EOBIS_POS 10U -#define UART_IVS_EOBIS_MSK BIT(UART_IVS_EOBIS_POS) - -#define UART_IVS_TCIS_POS 9U -#define UART_IVS_TCIS_MSK BIT(UART_IVS_TCIS_POS) - -#define UART_IVS_LINBKIS_POS 8U -#define UART_IVS_LINBKIS_MSK BIT(UART_IVS_LINBKIS_POS) - -#define UART_IVS_ABTOIS_POS 7U -#define UART_IVS_ABTOIS_MSK BIT(UART_IVS_ABTOIS_POS) - -#define UART_IVS_ABEIS_POS 6U -#define UART_IVS_ABEIS_MSK BIT(UART_IVS_ABEIS_POS) - -#define UART_IVS_BZIS_POS 5U -#define UART_IVS_BZIS_MSK BIT(UART_IVS_BZIS_POS) - -#define UART_IVS_RTOIS_POS 4U -#define UART_IVS_RTOIS_MSK BIT(UART_IVS_RTOIS_POS) - -#define UART_IVS_MDSIS_POS 3U -#define UART_IVS_MDSIS_MSK BIT(UART_IVS_MDSIS_POS) - -#define UART_IVS_RXSIS_POS 2U -#define UART_IVS_RXSIS_MSK BIT(UART_IVS_RXSIS_POS) - -#define UART_IVS_TXSIS_POS 1U -#define UART_IVS_TXSIS_MSK BIT(UART_IVS_TXSIS_POS) - -#define UART_IVS_RXRDIS_POS 0U -#define UART_IVS_RXRDIS_MSK BIT(UART_IVS_RXRDIS_POS) - -/****************** Bit definition for UART_RIF register ************************/ - -#define UART_RIF_CMIF_POS 11U -#define UART_RIF_CMIF_MSK BIT(UART_RIF_CMIF_POS) - -#define UART_RIF_EOBIF_POS 10U -#define UART_RIF_EOBIF_MSK BIT(UART_RIF_EOBIF_POS) - -#define UART_RIF_TCIF_POS 9U -#define UART_RIF_TCIF_MSK BIT(UART_RIF_TCIF_POS) - -#define UART_RIF_LINBKIF_POS 8U -#define UART_RIF_LINBKIF_MSK BIT(UART_RIF_LINBKIF_POS) - -#define UART_RIF_ABTOIF_POS 7U -#define UART_RIF_ABTOIF_MSK BIT(UART_RIF_ABTOIF_POS) - -#define UART_RIF_ABEIF_POS 6U -#define UART_RIF_ABEIF_MSK BIT(UART_RIF_ABEIF_POS) - -#define UART_RIF_BZIF_POS 5U -#define UART_RIF_BZIF_MSK BIT(UART_RIF_BZIF_POS) - -#define UART_RIF_RTOIF_POS 4U -#define UART_RIF_RTOIF_MSK BIT(UART_RIF_RTOIF_POS) - -#define UART_RIF_MDSIF_POS 3U -#define UART_RIF_MDSIF_MSK BIT(UART_RIF_MDSIF_POS) - -#define UART_RIF_RXSIF_POS 2U -#define UART_RIF_RXSIF_MSK BIT(UART_RIF_RXSIF_POS) - -#define UART_RIF_TXSIF_POS 1U -#define UART_RIF_TXSIF_MSK BIT(UART_RIF_TXSIF_POS) - -#define UART_RIF_RXRDIF_POS 0U -#define UART_RIF_RXRDIF_MSK BIT(UART_RIF_RXRDIF_POS) - -/****************** Bit definition for UART_IFM register ************************/ - -#define UART_IFM_CMIM_POS 11U -#define UART_IFM_CMIM_MSK BIT(UART_IFM_CMIM_POS) - -#define UART_IFM_EOBIM_POS 10U -#define UART_IFM_EOBIM_MSK BIT(UART_IFM_EOBIM_POS) - -#define UART_IFM_TCIM_POS 9U -#define UART_IFM_TCIM_MSK BIT(UART_IFM_TCIM_POS) - -#define UART_IFM_LINBKIM_POS 8U -#define UART_IFM_LINBKIM_MSK BIT(UART_IFM_LINBKIM_POS) - -#define UART_IFM_ABTOIM_POS 7U -#define UART_IFM_ABTOIM_MSK BIT(UART_IFM_ABTOIM_POS) - -#define UART_IFM_ABEIM_POS 6U -#define UART_IFM_ABEIM_MSK BIT(UART_IFM_ABEIM_POS) - -#define UART_IFM_BZIM_POS 5U -#define UART_IFM_BZIM_MSK BIT(UART_IFM_BZIM_POS) - -#define UART_IFM_RTOIM_POS 4U -#define UART_IFM_RTOIM_MSK BIT(UART_IFM_RTOIM_POS) - -#define UART_IFM_MDSIM_POS 3U -#define UART_IFM_MDSIM_MSK BIT(UART_IFM_MDSIM_POS) - -#define UART_IFM_RXSIM_POS 2U -#define UART_IFM_RXSIM_MSK BIT(UART_IFM_RXSIM_POS) - -#define UART_IFM_TXSIM_POS 1U -#define UART_IFM_TXSIM_MSK BIT(UART_IFM_TXSIM_POS) - -#define UART_IFM_RXRDIM_POS 0U -#define UART_IFM_RXRDIM_MSK BIT(UART_IFM_RXRDIM_POS) - -/****************** Bit definition for UART_ICR register ************************/ - -#define UART_ICR_CMIC_POS 11U -#define UART_ICR_CMIC_MSK BIT(UART_ICR_CMIC_POS) - -#define UART_ICR_EOBIC_POS 10U -#define UART_ICR_EOBIC_MSK BIT(UART_ICR_EOBIC_POS) - -#define UART_ICR_TCIC_POS 9U -#define UART_ICR_TCIC_MSK BIT(UART_ICR_TCIC_POS) - -#define UART_ICR_LINBKIC_POS 8U -#define UART_ICR_LINBKIC_MSK BIT(UART_ICR_LINBKIC_POS) - -#define UART_ICR_ABTOIC_POS 7U -#define UART_ICR_ABTOIC_MSK BIT(UART_ICR_ABTOIC_POS) - -#define UART_ICR_ABEIC_POS 6U -#define UART_ICR_ABEIC_MSK BIT(UART_ICR_ABEIC_POS) - -#define UART_ICR_BZIC_POS 5U -#define UART_ICR_BZIC_MSK BIT(UART_ICR_BZIC_POS) - -#define UART_ICR_CHTOIC_POS 4U -#define UART_ICR_CHTOIC_MSK BIT(UART_ICR_CHTOIC_POS) - -#define UART_ICR_MDSIC_POS 3U -#define UART_ICR_MDSIC_MSK BIT(UART_ICR_MDSIC_POS) - -#define UART_ICR_RXSIC_POS 2U -#define UART_ICR_RXSIC_MSK BIT(UART_ICR_RXSIC_POS) - -#define UART_ICR_TXSIC_POS 1U -#define UART_ICR_TXSIC_MSK BIT(UART_ICR_TXSIC_POS) - -#define UART_ICR_RXRDIC_POS 0U -#define UART_ICR_RXRDIC_MSK BIT(UART_ICR_RXRDIC_POS) - -typedef struct -{ - __I uint32_t RBR; - __IO uint32_t TBR; - __IO uint32_t BRR; - __IO uint32_t LCR; - __IO uint32_t MCR; - __IO uint32_t CR; - __IO uint32_t RTOR; - __IO uint32_t FCR; - __I uint32_t SR; - __O uint32_t IER; - __O uint32_t IDR; - __I uint32_t IVS; - __I uint32_t RIF; - __I uint32_t IFM; - __O uint32_t ICR; -} UART_TypeDef; - -/****************** Bit definition for LPUART_CON0 register ************************/ - -#define LPUART_CON0_MODESEL_POSS 30U -#define LPUART_CON0_MODESEL_POSE 31U -#define LPUART_CON0_MODESEL_MSK BITS(LPUART_CON0_MODESEL_POSS,LPUART_CON0_MODESEL_POSE) - -#define LPUART_CON0_TXDMAE_POS 29U -#define LPUART_CON0_TXDMAE_MSK BIT(LPUART_CON0_TXDMAE_POS) - -#define LPUART_CON0_RXDMAE_POS 28U -#define LPUART_CON0_RXDMAE_MSK BIT(LPUART_CON0_RXDMAE_POS) - -#define LPUART_CON0_INTERVAL_POSS 16U -#define LPUART_CON0_INTERVAL_POSE 23U -#define LPUART_CON0_INTERVAL_MSK BITS(LPUART_CON0_INTERVAL_POSS,LPUART_CON0_INTERVAL_POSE) - -#define LPUART_CON0_SYNCBP_POS 15U -#define LPUART_CON0_SYNCBP_MSK BIT(LPUART_CON0_SYNCBP_POS) - -#define LPUART_CON0_CTSPOL_POS 13U -#define LPUART_CON0_CTSPOL_MSK BIT(LPUART_CON0_CTSPOL_POS) - -#define LPUART_CON0_RTSPOL_POS 12U -#define LPUART_CON0_RTSPOL_MSK BIT(LPUART_CON0_RTSPOL_POS) - -#define LPUART_CON0_ATCTSE_POS 11U -#define LPUART_CON0_ATCTSE_MSK BIT(LPUART_CON0_ATCTSE_POS) - -#define LPUART_CON0_ATRTSE_POS 10U -#define LPUART_CON0_ATRTSE_MSK BIT(LPUART_CON0_ATRTSE_POS) - -#define LPUART_CON0_BRKCE_POS 8U -#define LPUART_CON0_BRKCE_MSK BIT(LPUART_CON0_BRKCE_POS) - -#define LPUART_CON0_LPBMOD_POS 7U -#define LPUART_CON0_LPBMOD_MSK BIT(LPUART_CON0_LPBMOD_POS) - -#define LPUART_CON0_STICKPARSEL_POS 6U -#define LPUART_CON0_STICKPARSEL_MSK BIT(LPUART_CON0_STICKPARSEL_POS) - -#define LPUART_CON0_EVENPARSEL_POS 5U -#define LPUART_CON0_EVENPARSEL_MSK BIT(LPUART_CON0_EVENPARSEL_POS) - -#define LPUART_CON0_PARCHKE_POS 4U -#define LPUART_CON0_PARCHKE_MSK BIT(LPUART_CON0_PARCHKE_POS) - -#define LPUART_CON0_STPLENTH_POS 3U -#define LPUART_CON0_STPLENTH_MSK BIT(LPUART_CON0_STPLENTH_POS) - -#define LPUART_CON0_DATLENTH_POSS 0U -#define LPUART_CON0_DATLENTH_POSE 2U -#define LPUART_CON0_DATLENTH_MSK BITS(LPUART_CON0_DATLENTH_POSS,LPUART_CON0_DATLENTH_POSE) - -/****************** Bit definition for LPUART_CON1 register ************************/ - -#define LPUART_CON1_ADDCMP_POSS 24U -#define LPUART_CON1_ADDCMP_POSE 31U -#define LPUART_CON1_ADDCMP_MSK BITS(LPUART_CON1_ADDCMP_POSS,LPUART_CON1_ADDCMP_POSE) - -#define LPUART_CON1_ADETE_POS 23U -#define LPUART_CON1_ADETE_MSK BIT(LPUART_CON1_ADETE_POS) - -#define LPUART_CON1_ATDIRM_POS 22U -#define LPUART_CON1_ATDIRM_MSK BIT(LPUART_CON1_ATDIRM_POS) - -#define LPUART_CON1_ATADETE_POS 21U -#define LPUART_CON1_ATADETE_MSK BIT(LPUART_CON1_ATADETE_POS) - -#define LPUART_CON1_NMPMOD_POS 20U -#define LPUART_CON1_NMPMOD_MSK BIT(LPUART_CON1_NMPMOD_POS) - -#define LPUART_CON1_IRWIDTH_POS 16U -#define LPUART_CON1_IRWIDTH_MSK BIT(LPUART_CON1_IRWIDTH_POS) - -#define LPUART_CON1_TOICMP_POSS 8U -#define LPUART_CON1_TOICMP_POSE 15U -#define LPUART_CON1_TOICMP_MSK BITS(LPUART_CON1_TOICMP_POSS,LPUART_CON1_TOICMP_POSE) - -#define LPUART_CON1_TOCNTE_POS 7U -#define LPUART_CON1_TOCNTE_MSK BIT(LPUART_CON1_TOCNTE_POS) - -#define LPUART_CON1_IRTXINV_POS 3U -#define LPUART_CON1_IRTXINV_MSK BIT(LPUART_CON1_IRTXINV_POS) - -#define LPUART_CON1_IRRXINV_POS 2U -#define LPUART_CON1_IRRXINV_MSK BIT(LPUART_CON1_IRRXINV_POS) - -#define LPUART_CON1_IRTXE_POS 1U -#define LPUART_CON1_IRTXE_MSK BIT(LPUART_CON1_IRTXE_POS) - -#define LPUART_CON1_RTS_POS 0U -#define LPUART_CON1_RTS_MSK BIT(LPUART_CON1_RTS_POS) - -/****************** Bit definition for LPUART_CLKDIV register ************************/ - -#define LPUART_CLKDIV_CLKDIV_POSS 0U -#define LPUART_CLKDIV_CLKDIV_POSE 19U -#define LPUART_CLKDIV_CLKDIV_MSK BITS(LPUART_CLKDIV_CLKDIV_POSS,LPUART_CLKDIV_CLKDIV_POSE) - -/****************** Bit definition for LPUART_FIFOCON register ************************/ - -#define LPUART_FIFOCON_RTSTRGLVL_POSS 12U -#define LPUART_FIFOCON_RTSTRGLVL_POSE 15U -#define LPUART_FIFOCON_RTSTRGLVL_MSK BITS(LPUART_FIFOCON_RTSTRGLVL_POSS,LPUART_FIFOCON_RTSTRGLVL_POSE) - -#define LPUART_FIFOCON_RXTRGLVL_POSS 8U -#define LPUART_FIFOCON_RXTRGLVL_POSE 11U -#define LPUART_FIFOCON_RXTRGLVL_MSK BITS(LPUART_FIFOCON_RXTRGLVL_POSS,LPUART_FIFOCON_RXTRGLVL_POSE) - -#define LPUART_FIFOCON_NMPMRXDIS_POS 2U -#define LPUART_FIFOCON_NMPMRXDIS_MSK BIT(LPUART_FIFOCON_NMPMRXDIS_POS) - -#define LPUART_FIFOCON_TXRESET_POS 1U -#define LPUART_FIFOCON_TXRESET_MSK BIT(LPUART_FIFOCON_TXRESET_POS) - -#define LPUART_FIFOCON_RXRESET_POS 0U -#define LPUART_FIFOCON_RXRESET_MSK BIT(LPUART_FIFOCON_RXRESET_POS) - -/****************** Bit definition for LPUART_RXDR register ************************/ - -#define LPUART_RXDR_FERR_POS 15U -#define LPUART_RXDR_FERR_MSK BIT(LPUART_RXDR_FERR_POS) - -#define LPUART_RXDR_PERR_POS 14U -#define LPUART_RXDR_PERR_MSK BIT(LPUART_RXDR_PERR_POS) - -#define LPUART_RXDR_RXDR_POSS 0U -#define LPUART_RXDR_RXDR_POSE 8U -#define LPUART_RXDR_RXDR_MSK BITS(LPUART_RXDR_RXDR_POSS,LPUART_RXDR_RXDR_POSE) - -/****************** Bit definition for LPUART_TXDR register ************************/ - -#define LPUART_TXDR_TXDR_POSS 0U -#define LPUART_TXDR_TXDR_POSE 8U -#define LPUART_TXDR_TXDR_MSK BITS(LPUART_TXDR_TXDR_POSS,LPUART_TXDR_TXDR_POSE) - -/****************** Bit definition for LPUART_STAT register ************************/ - -#define LPUART_STAT_RTSSTAT_POS 18U -#define LPUART_STAT_RTSSTAT_MSK BIT(LPUART_STAT_RTSSTAT_POS) - -#define LPUART_STAT_CTSSTAT_POS 17U -#define LPUART_STAT_CTSSTAT_MSK BIT(LPUART_STAT_CTSSTAT_POS) - -#define LPUART_STAT_TXIDLE_POS 16U -#define LPUART_STAT_TXIDLE_MSK BIT(LPUART_STAT_TXIDLE_POS) - -#define LPUART_STAT_TXFULL_POS 15U -#define LPUART_STAT_TXFULL_MSK BIT(LPUART_STAT_TXFULL_POS) - -#define LPUART_STAT_TXEMP_POS 14U -#define LPUART_STAT_TXEMP_MSK BIT(LPUART_STAT_TXEMP_POS) - -#define LPUART_STAT_TXPTR_POSS 8U -#define LPUART_STAT_TXPTR_POSE 13U -#define LPUART_STAT_TXPTR_MSK BITS(LPUART_STAT_TXPTR_POSS,LPUART_STAT_TXPTR_POSE) - -#define LPUART_STAT_RXFULL_POS 7U -#define LPUART_STAT_RXFULL_MSK BIT(LPUART_STAT_RXFULL_POS) - -#define LPUART_STAT_RXEMP_POS 6U -#define LPUART_STAT_RXEMP_MSK BIT(LPUART_STAT_RXEMP_POS) - -#define LPUART_STAT_RXPTR_POSS 0U -#define LPUART_STAT_RXPTR_POSE 5U -#define LPUART_STAT_RXPTR_MSK BITS(LPUART_STAT_RXPTR_POSS,LPUART_STAT_RXPTR_POSE) - -/****************** Bit definition for LPUART_IER register ************************/ - -#define LPUART_IER_TCIE_POS 15U -#define LPUART_IER_TCIE_MSK BIT(LPUART_IER_TCIE_POS) - -#define LPUART_IER_ADETIE_POS 12U -#define LPUART_IER_ADETIE_MSK BIT(LPUART_IER_ADETIE_POS) - -#define LPUART_IER_BRKERRIE_POS 11U -#define LPUART_IER_BRKERRIE_MSK BIT(LPUART_IER_BRKERRIE_POS) - -#define LPUART_IER_FERRIE_POS 10U -#define LPUART_IER_FERRIE_MSK BIT(LPUART_IER_FERRIE_POS) - -#define LPUART_IER_PERRIE_POS 9U -#define LPUART_IER_PERRIE_MSK BIT(LPUART_IER_PERRIE_POS) - -#define LPUART_IER_DATWKIE_POS 8U -#define LPUART_IER_DATWKIE_MSK BIT(LPUART_IER_DATWKIE_POS) - -#define LPUART_IER_CTSWKIE_POS 7U -#define LPUART_IER_CTSWKIE_MSK BIT(LPUART_IER_CTSWKIE_POS) - -#define LPUART_IER_TXOVIE_POS 5U -#define LPUART_IER_TXOVIE_MSK BIT(LPUART_IER_TXOVIE_POS) - -#define LPUART_IER_RXOVIE_POS 4U -#define LPUART_IER_RXOVIE_MSK BIT(LPUART_IER_RXOVIE_POS) - -#define LPUART_IER_RXTOIE_POS 3U -#define LPUART_IER_RXTOIE_MSK BIT(LPUART_IER_RXTOIE_POS) - -#define LPUART_IER_CTSDETIE_POS 2U -#define LPUART_IER_CTSDETIE_MSK BIT(LPUART_IER_CTSDETIE_POS) - -#define LPUART_IER_TBEMPIE_POS 1U -#define LPUART_IER_TBEMPIE_MSK BIT(LPUART_IER_TBEMPIE_POS) - -#define LPUART_IER_RBRIE_POS 0U -#define LPUART_IER_RBRIE_MSK BIT(LPUART_IER_RBRIE_POS) - -/****************** Bit definition for LPUART_IFLAG register ************************/ - -#define LPUART_IFLAG_TCIF_POS 15U -#define LPUART_IFLAG_TCIF_MSK BIT(LPUART_IFLAG_TCIF_POS) - -#define LPUART_IFLAG_ADETIF_POS 12U -#define LPUART_IFLAG_ADETIF_MSK BIT(LPUART_IFLAG_ADETIF_POS) - -#define LPUART_IFLAG_BRKERRIF_POS 11U -#define LPUART_IFLAG_BRKERRIF_MSK BIT(LPUART_IFLAG_BRKERRIF_POS) - -#define LPUART_IFLAG_FERRIF_POS 10U -#define LPUART_IFLAG_FERRIF_MSK BIT(LPUART_IFLAG_FERRIF_POS) - -#define LPUART_IFLAG_PERRIF_POS 9U -#define LPUART_IFLAG_PERRIF_MSK BIT(LPUART_IFLAG_PERRIF_POS) - -#define LPUART_IFLAG_DATWKIF_POS 8U -#define LPUART_IFLAG_DATWKIF_MSK BIT(LPUART_IFLAG_DATWKIF_POS) - -#define LPUART_IFLAG_CTSWKIF_POS 7U -#define LPUART_IFLAG_CTSWKIF_MSK BIT(LPUART_IFLAG_CTSWKIF_POS) - -#define LPUART_IFLAG_TXOVIF_POS 5U -#define LPUART_IFLAG_TXOVIF_MSK BIT(LPUART_IFLAG_TXOVIF_POS) - -#define LPUART_IFLAG_RXOVIF_POS 4U -#define LPUART_IFLAG_RXOVIF_MSK BIT(LPUART_IFLAG_RXOVIF_POS) - -#define LPUART_IFLAG_RXTOIF_POS 3U -#define LPUART_IFLAG_RXTOIF_MSK BIT(LPUART_IFLAG_RXTOIF_POS) - -#define LPUART_IFLAG_CTSDETIF_POS 2U -#define LPUART_IFLAG_CTSDETIF_MSK BIT(LPUART_IFLAG_CTSDETIF_POS) - -#define LPUART_IFLAG_TBEMPIF_POS 1U -#define LPUART_IFLAG_TBEMPIF_MSK BIT(LPUART_IFLAG_TBEMPIF_POS) - -#define LPUART_IFLAG_RBRIF_POS 0U -#define LPUART_IFLAG_RBRIF_MSK BIT(LPUART_IFLAG_RBRIF_POS) - -/****************** Bit definition for LPUART_IFC register ************************/ - -#define LPUART_IFC_TCIFC_POS 15U -#define LPUART_IFC_TCIFC_MSK BIT(LPUART_IFC_TCIFC_POS) - -#define LPUART_IFC_ADETIFC_POS 12U -#define LPUART_IFC_ADETIFC_MSK BIT(LPUART_IFC_ADETIFC_POS) - -#define LPUART_IFC_BRKERRIFC_POS 11U -#define LPUART_IFC_BRKERRIFC_MSK BIT(LPUART_IFC_BRKERRIFC_POS) - -#define LPUART_IFC_FERRIFC_POS 10U -#define LPUART_IFC_FERRIFC_MSK BIT(LPUART_IFC_FERRIFC_POS) - -#define LPUART_IFC_PERRIFC_POS 9U -#define LPUART_IFC_PERRIFC_MSK BIT(LPUART_IFC_PERRIFC_POS) - -#define LPUART_IFC_DATWKIFC_POS 8U -#define LPUART_IFC_DATWKIFC_MSK BIT(LPUART_IFC_DATWKIFC_POS) - -#define LPUART_IFC_CTSWKIFC_POS 7U -#define LPUART_IFC_CTSWKIFC_MSK BIT(LPUART_IFC_CTSWKIFC_POS) - -#define LPUART_IFC_TXOVIFC_POS 5U -#define LPUART_IFC_TXOVIFC_MSK BIT(LPUART_IFC_TXOVIFC_POS) - -#define LPUART_IFC_RXOVIFC_POS 4U -#define LPUART_IFC_RXOVIFC_MSK BIT(LPUART_IFC_RXOVIFC_POS) - -#define LPUART_IFC_CTSDETIFC_POS 2U -#define LPUART_IFC_CTSDETIFC_MSK BIT(LPUART_IFC_CTSDETIFC_POS) - -#define LPUART_IFC_TBEMPIFC_POS 1U -#define LPUART_IFC_TBEMPIFC_MSK BIT(LPUART_IFC_TBEMPIFC_POS) - -#define LPUART_IFC_RBRIFC_POS 0U -#define LPUART_IFC_RBRIFC_MSK BIT(LPUART_IFC_RBRIFC_POS) - -/****************** Bit definition for LPUART_ISTAT register ************************/ - -#define LPUART_ISTAT_TCINT_POS 15U -#define LPUART_ISTAT_TCINT_MSK BIT(LPUART_ISTAT_TCINT_POS) - -#define LPUART_ISTAT_RXSTATINT_POS 9U -#define LPUART_ISTAT_RXSTATINT_MSK BIT(LPUART_ISTAT_RXSTATINT_POS) - -#define LPUART_ISTAT_DATWKINT_POS 8U -#define LPUART_ISTAT_DATWKINT_MSK BIT(LPUART_ISTAT_DATWKINT_POS) - -#define LPUART_ISTAT_CTSWKINT_POS 7U -#define LPUART_ISTAT_CTSWKINT_MSK BIT(LPUART_ISTAT_CTSWKINT_POS) - -#define LPUART_ISTAT_BUFERRINT_POS 4U -#define LPUART_ISTAT_BUFERRINT_MSK BIT(LPUART_ISTAT_BUFERRINT_POS) - -#define LPUART_ISTAT_RXTOINT_POS 3U -#define LPUART_ISTAT_RXTOINT_MSK BIT(LPUART_ISTAT_RXTOINT_POS) - -#define LPUART_ISTAT_CTSDETINT_POS 2U -#define LPUART_ISTAT_CTSDETINT_MSK BIT(LPUART_ISTAT_CTSDETINT_POS) - -#define LPUART_ISTAT_TBEMPINT_POS 1U -#define LPUART_ISTAT_TBEMPINT_MSK BIT(LPUART_ISTAT_TBEMPINT_POS) - -#define LPUART_ISTAT_RBRINT_POS 0U -#define LPUART_ISTAT_RBRINT_MSK BIT(LPUART_ISTAT_RBRINT_POS) - -/****************** Bit definition for LPUART_UPDATE register ************************/ - -#define LPUART_UPDATE_UDIS_POS 0U -#define LPUART_UPDATE_UDIS_MSK BIT(LPUART_UPDATE_UDIS_POS) - -/****************** Bit definition for LPUART_SYNCSTAT register ************************/ - -#define LPUART_SYNCSTAT_FIFOCONWBSY_POS 3U -#define LPUART_SYNCSTAT_FIFOCONWBSY_MSK BIT(LPUART_SYNCSTAT_FIFOCONWBSY_POS) - -#define LPUART_SYNCSTAT_CLKDIVWBSY_POS 2U -#define LPUART_SYNCSTAT_CLKDIVWBSY_MSK BIT(LPUART_SYNCSTAT_CLKDIVWBSY_POS) - -#define LPUART_SYNCSTAT_CON1WBSY_POS 1U -#define LPUART_SYNCSTAT_CON1WBSY_MSK BIT(LPUART_SYNCSTAT_CON1WBSY_POS) - -#define LPUART_SYNCSTAT_CON0WBSY_POS 0U -#define LPUART_SYNCSTAT_CON0WBSY_MSK BIT(LPUART_SYNCSTAT_CON0WBSY_POS) - -typedef struct -{ - __IO uint32_t CON0; - __IO uint32_t CON1; - __IO uint32_t CLKDIV; - __IO uint32_t FIFOCON; - uint32_t RESERVED0 ; - __I uint32_t RXDR; - __O uint32_t TXDR; - __I uint32_t STAT; - __IO uint32_t IER; - __I uint32_t IFLAG; - __O uint32_t IFC; - __I uint32_t ISTAT; - uint32_t RESERVED1[2] ; - __IO uint32_t UPDATE; - __I uint32_t SYNCSTAT; -} LPUART_TypeDef; - -/****************** Bit definition for SPI_CON1 register ************************/ - -#define SPI_CON1_BIDEN_POS 15U -#define SPI_CON1_BIDEN_MSK BIT(SPI_CON1_BIDEN_POS) - -#define SPI_CON1_BIDOEN_POS 14U -#define SPI_CON1_BIDOEN_MSK BIT(SPI_CON1_BIDOEN_POS) - -#define SPI_CON1_CRCEN_POS 13U -#define SPI_CON1_CRCEN_MSK BIT(SPI_CON1_CRCEN_POS) - -#define SPI_CON1_NXTCRC_POS 12U -#define SPI_CON1_NXTCRC_MSK BIT(SPI_CON1_NXTCRC_POS) - -#define SPI_CON1_FLEN_POS 11U -#define SPI_CON1_FLEN_MSK BIT(SPI_CON1_FLEN_POS) - -#define SPI_CON1_RXO_POS 10U -#define SPI_CON1_RXO_MSK BIT(SPI_CON1_RXO_POS) - -#define SPI_CON1_SSEN_POS 9U -#define SPI_CON1_SSEN_MSK BIT(SPI_CON1_SSEN_POS) - -#define SPI_CON1_SSOUT_POS 8U -#define SPI_CON1_SSOUT_MSK BIT(SPI_CON1_SSOUT_POS) - -#define SPI_CON1_LSBFST_POS 7U -#define SPI_CON1_LSBFST_MSK BIT(SPI_CON1_LSBFST_POS) - -#define SPI_CON1_SPIEN_POS 6U -#define SPI_CON1_SPIEN_MSK BIT(SPI_CON1_SPIEN_POS) - -#define SPI_CON1_BAUD_POSS 3U -#define SPI_CON1_BAUD_POSE 5U -#define SPI_CON1_BAUD_MSK BITS(SPI_CON1_BAUD_POSS,SPI_CON1_BAUD_POSE) - -#define SPI_CON1_MSTREN_POS 2U -#define SPI_CON1_MSTREN_MSK BIT(SPI_CON1_MSTREN_POS) - -#define SPI_CON1_CPOL_POS 1U -#define SPI_CON1_CPOL_MSK BIT(SPI_CON1_CPOL_POS) - -#define SPI_CON1_CPHA_POS 0U -#define SPI_CON1_CPHA_MSK BIT(SPI_CON1_CPHA_POS) - -/****************** Bit definition for SPI_CON2 register ************************/ - -#define SPI_CON2_TXBEIE_POS 7U -#define SPI_CON2_TXBEIE_MSK BIT(SPI_CON2_TXBEIE_POS) - -#define SPI_CON2_RXBNEIE_POS 6U -#define SPI_CON2_RXBNEIE_MSK BIT(SPI_CON2_RXBNEIE_POS) - -#define SPI_CON2_ERRIE_POS 5U -#define SPI_CON2_ERRIE_MSK BIT(SPI_CON2_ERRIE_POS) - -#define SPI_CON2_NSSOE_POS 2U -#define SPI_CON2_NSSOE_MSK BIT(SPI_CON2_NSSOE_POS) - -#define SPI_CON2_TXDMA_POS 1U -#define SPI_CON2_TXDMA_MSK BIT(SPI_CON2_TXDMA_POS) - -#define SPI_CON2_RXDMA_POS 0U -#define SPI_CON2_RXDMA_MSK BIT(SPI_CON2_RXDMA_POS) - -/****************** Bit definition for SPI_STAT register ************************/ - -#define SPI_STAT_BUSY_POS 7U -#define SPI_STAT_BUSY_MSK BIT(SPI_STAT_BUSY_POS) - -#define SPI_STAT_OVERR_POS 6U -#define SPI_STAT_OVERR_MSK BIT(SPI_STAT_OVERR_POS) - -#define SPI_STAT_MODERR_POS 5U -#define SPI_STAT_MODERR_MSK BIT(SPI_STAT_MODERR_POS) - -#define SPI_STAT_CRCERR_POS 4U -#define SPI_STAT_CRCERR_MSK BIT(SPI_STAT_CRCERR_POS) - -#define SPI_STAT_TXBE_POS 1U -#define SPI_STAT_TXBE_MSK BIT(SPI_STAT_TXBE_POS) - -#define SPI_STAT_RXBNE_POS 0U -#define SPI_STAT_RXBNE_MSK BIT(SPI_STAT_RXBNE_POS) - -/****************** Bit definition for SPI_DATA register ************************/ - -#define SPI_DATA_VALUE_POSS 0U -#define SPI_DATA_VALUE_POSE 15U -#define SPI_DATA_VALUE_MSK BITS(SPI_DATA_VALUE_POSS,SPI_DATA_VALUE_POSE) - -/****************** Bit definition for SPI_CRCPOLY register ************************/ - -#define SPI_CRCPOLY_VALUE_POSS 0U -#define SPI_CRCPOLY_VALUE_POSE 15U -#define SPI_CRCPOLY_VALUE_MSK BITS(SPI_CRCPOLY_VALUE_POSS,SPI_CRCPOLY_VALUE_POSE) - -/****************** Bit definition for SPI_RXCRC register ************************/ - -#define SPI_RXCRC_CRCVAL_POSS 0U -#define SPI_RXCRC_CRCVAL_POSE 15U -#define SPI_RXCRC_CRCVAL_MSK BITS(SPI_RXCRC_CRCVAL_POSS,SPI_RXCRC_CRCVAL_POSE) - -/****************** Bit definition for SPI_TXCRC register ************************/ - -#define SPI_TXCRC_CRCVAL_POSS 0U -#define SPI_TXCRC_CRCVAL_POSE 15U -#define SPI_TXCRC_CRCVAL_MSK BITS(SPI_TXCRC_CRCVAL_POSS,SPI_TXCRC_CRCVAL_POSE) - -typedef struct -{ - __IO uint32_t CON1; - __IO uint32_t CON2; - __IO uint32_t STAT; - __IO uint32_t DATA; - __IO uint32_t CRCPOLY; - __I uint32_t RXCRC; - __I uint32_t TXCRC; -} SPI_TypeDef; - -/****************** Bit definition for I2C_CON1 register ************************/ - -#define I2C_CON1_SRST_POS 15U -#define I2C_CON1_SRST_MSK BIT(I2C_CON1_SRST_POS) - -#define I2C_CON1_ALARM_POS 13U -#define I2C_CON1_ALARM_MSK BIT(I2C_CON1_ALARM_POS) - -#define I2C_CON1_TRPEC_POS 12U -#define I2C_CON1_TRPEC_MSK BIT(I2C_CON1_TRPEC_POS) - -#define I2C_CON1_POSAP_POS 11U -#define I2C_CON1_POSAP_MSK BIT(I2C_CON1_POSAP_POS) - -#define I2C_CON1_ACKEN_POS 10U -#define I2C_CON1_ACKEN_MSK BIT(I2C_CON1_ACKEN_POS) - -#define I2C_CON1_STOP_POS 9U -#define I2C_CON1_STOP_MSK BIT(I2C_CON1_STOP_POS) - -#define I2C_CON1_START_POS 8U -#define I2C_CON1_START_MSK BIT(I2C_CON1_START_POS) - -#define I2C_CON1_DISCS_POS 7U -#define I2C_CON1_DISCS_MSK BIT(I2C_CON1_DISCS_POS) - -#define I2C_CON1_GCEN_POS 6U -#define I2C_CON1_GCEN_MSK BIT(I2C_CON1_GCEN_POS) - -#define I2C_CON1_PECEN_POS 5U -#define I2C_CON1_PECEN_MSK BIT(I2C_CON1_PECEN_POS) - -#define I2C_CON1_ARPEN_POS 4U -#define I2C_CON1_ARPEN_MSK BIT(I2C_CON1_ARPEN_POS) - -#define I2C_CON1_SMBMOD_POS 3U -#define I2C_CON1_SMBMOD_MSK BIT(I2C_CON1_SMBMOD_POS) - -#define I2C_CON1_PMOD_POS 1U -#define I2C_CON1_PMOD_MSK BIT(I2C_CON1_PMOD_POS) - -#define I2C_CON1_PEN_POS 0U -#define I2C_CON1_PEN_MSK BIT(I2C_CON1_PEN_POS) - -/****************** Bit definition for I2C_CON2 register ************************/ - -#define I2C_CON2_LDMA_POS 12U -#define I2C_CON2_LDMA_MSK BIT(I2C_CON2_LDMA_POS) - -#define I2C_CON2_DMAEN_POS 11U -#define I2C_CON2_DMAEN_MSK BIT(I2C_CON2_DMAEN_POS) - -#define I2C_CON2_BUFIE_POS 10U -#define I2C_CON2_BUFIE_MSK BIT(I2C_CON2_BUFIE_POS) - -#define I2C_CON2_EVTIE_POS 9U -#define I2C_CON2_EVTIE_MSK BIT(I2C_CON2_EVTIE_POS) - -#define I2C_CON2_ERRIE_POS 8U -#define I2C_CON2_ERRIE_MSK BIT(I2C_CON2_ERRIE_POS) - -#define I2C_CON2_CLKF_POSS 0U -#define I2C_CON2_CLKF_POSE 5U -#define I2C_CON2_CLKF_MSK BITS(I2C_CON2_CLKF_POSS,I2C_CON2_CLKF_POSE) - -/****************** Bit definition for I2C_ADDR1 register ************************/ - -#define I2C_ADDR1_ADDTYPE_POS 15U -#define I2C_ADDR1_ADDTYPE_MSK BIT(I2C_ADDR1_ADDTYPE_POS) - -#define I2C_ADDR1_ADDH_POSS 8U -#define I2C_ADDR1_ADDH_POSE 9U -#define I2C_ADDR1_ADDH_MSK BITS(I2C_ADDR1_ADDH_POSS,I2C_ADDR1_ADDH_POSE) - -#define I2C_ADDR1_ADD_POSS 1U -#define I2C_ADDR1_ADD_POSE 7U -#define I2C_ADDR1_ADD_MSK BITS(I2C_ADDR1_ADD_POSS,I2C_ADDR1_ADD_POSE) - -#define I2C_ADDR1_ADDLSB_POS 0U -#define I2C_ADDR1_ADDLSB_MSK BIT(I2C_ADDR1_ADDLSB_POS) - -/****************** Bit definition for I2C_ADDR2 register ************************/ - -#define I2C_ADDR2_ADD_POSS 1U -#define I2C_ADDR2_ADD_POSE 7U -#define I2C_ADDR2_ADD_MSK BITS(I2C_ADDR2_ADD_POSS,I2C_ADDR2_ADD_POSE) - -#define I2C_ADDR2_DUALEN_POS 0U -#define I2C_ADDR2_DUALEN_MSK BIT(I2C_ADDR2_DUALEN_POS) - -/****************** Bit definition for I2C_DATA register ************************/ - -#define I2C_DATA_TRBUF_POSS 0U -#define I2C_DATA_TRBUF_POSE 7U -#define I2C_DATA_TRBUF_MSK BITS(I2C_DATA_TRBUF_POSS,I2C_DATA_TRBUF_POSE) - -/****************** Bit definition for I2C_STAT1 register ************************/ - -#define I2C_STAT1_SMBALARM_POS 15U -#define I2C_STAT1_SMBALARM_MSK BIT(I2C_STAT1_SMBALARM_POS) - -#define I2C_STAT1_SMBTO_POS 14U -#define I2C_STAT1_SMBTO_MSK BIT(I2C_STAT1_SMBTO_POS) - -#define I2C_STAT1_PECERR_POS 12U -#define I2C_STAT1_PECERR_MSK BIT(I2C_STAT1_PECERR_POS) - -#define I2C_STAT1_ROUERR_POS 11U -#define I2C_STAT1_ROUERR_MSK BIT(I2C_STAT1_ROUERR_POS) - -#define I2C_STAT1_ACKERR_POS 10U -#define I2C_STAT1_ACKERR_MSK BIT(I2C_STAT1_ACKERR_POS) - -#define I2C_STAT1_LARB_POS 9U -#define I2C_STAT1_LARB_MSK BIT(I2C_STAT1_LARB_POS) - -#define I2C_STAT1_BUSERR_POS 8U -#define I2C_STAT1_BUSERR_MSK BIT(I2C_STAT1_BUSERR_POS) - -#define I2C_STAT1_TXBE_POS 7U -#define I2C_STAT1_TXBE_MSK BIT(I2C_STAT1_TXBE_POS) - -#define I2C_STAT1_RXBNE_POS 6U -#define I2C_STAT1_RXBNE_MSK BIT(I2C_STAT1_RXBNE_POS) - -#define I2C_STAT1_DETSTP_POS 4U -#define I2C_STAT1_DETSTP_MSK BIT(I2C_STAT1_DETSTP_POS) - -#define I2C_STAT1_SENDADD10_POS 3U -#define I2C_STAT1_SENDADD10_MSK BIT(I2C_STAT1_SENDADD10_POS) - -#define I2C_STAT1_BTC_POS 2U -#define I2C_STAT1_BTC_MSK BIT(I2C_STAT1_BTC_POS) - -#define I2C_STAT1_ADDR_POS 1U -#define I2C_STAT1_ADDR_MSK BIT(I2C_STAT1_ADDR_POS) - -#define I2C_STAT1_SENDSTR_POS 0U -#define I2C_STAT1_SENDSTR_MSK BIT(I2C_STAT1_SENDSTR_POS) - -/****************** Bit definition for I2C_STAT2 register ************************/ - -#define I2C_STAT2_PECV_POSS 8U -#define I2C_STAT2_PECV_POSE 15U -#define I2C_STAT2_PECV_MSK BITS(I2C_STAT2_PECV_POSS,I2C_STAT2_PECV_POSE) - -#define I2C_STAT2_DMF_POS 7U -#define I2C_STAT2_DMF_MSK BIT(I2C_STAT2_DMF_POS) - -#define I2C_STAT2_SMBHH_POS 6U -#define I2C_STAT2_SMBHH_MSK BIT(I2C_STAT2_SMBHH_POS) - -#define I2C_STAT2_SMBDEF_POS 5U -#define I2C_STAT2_SMBDEF_MSK BIT(I2C_STAT2_SMBDEF_POS) - -#define I2C_STAT2_RXGCF_POS 4U -#define I2C_STAT2_RXGCF_MSK BIT(I2C_STAT2_RXGCF_POS) - -#define I2C_STAT2_TRF_POS 2U -#define I2C_STAT2_TRF_MSK BIT(I2C_STAT2_TRF_POS) - -#define I2C_STAT2_BSYF_POS 1U -#define I2C_STAT2_BSYF_MSK BIT(I2C_STAT2_BSYF_POS) - -#define I2C_STAT2_MASTER_POS 0U -#define I2C_STAT2_MASTER_MSK BIT(I2C_STAT2_MASTER_POS) - -/****************** Bit definition for I2C_CKCFG register ************************/ - -#define I2C_CKCFG_CLKMOD_POS 15U -#define I2C_CKCFG_CLKMOD_MSK BIT(I2C_CKCFG_CLKMOD_POS) - -#define I2C_CKCFG_DUTY_POS 14U -#define I2C_CKCFG_DUTY_MSK BIT(I2C_CKCFG_DUTY_POS) - -#define I2C_CKCFG_CLKSET_POSS 0U -#define I2C_CKCFG_CLKSET_POSE 11U -#define I2C_CKCFG_CLKSET_MSK BITS(I2C_CKCFG_CLKSET_POSS,I2C_CKCFG_CLKSET_POSE) - -/****************** Bit definition for I2C_RT register ************************/ - -#define I2C_RT_RISET_POSS 0U -#define I2C_RT_RISET_POSE 5U -#define I2C_RT_RISET_MSK BITS(I2C_RT_RISET_POSS,I2C_RT_RISET_POSE) - -typedef struct -{ - __IO uint32_t CON1; - __IO uint32_t CON2; - __IO uint32_t ADDR1; - __IO uint32_t ADDR2; - __IO uint32_t DATA; - __IO uint32_t STAT1; - __I uint32_t STAT2; - __IO uint32_t CKCFG; - __IO uint32_t RT; -} I2C_TypeDef; - -/****************** Bit definition for CRC_CR register ************************/ -#define CRC_CR_BYTORD_POS 24U -#define CRC_CR_BYTORD_MSK BIT(CRC_CR_BYTORD_POS) - -#define CRC_CR_DATLEN_POSS 22U -#define CRC_CR_DATLEN_POSE 23U -#define CRC_CR_DATLEN_MSK BITS(CRC_CR_DATLEN_POSS,CRC_CR_DATLEN_POSE) - -#define CRC_CR_MODE_POSS 20U -#define CRC_CR_MODE_POSE 21U -#define CRC_CR_MODE_MSK BITS(CRC_CR_MODE_POSS,CRC_CR_MODE_POSE) - -#define CRC_CR_CHSINV_POS 19U -#define CRC_CR_CHSINV_MSK BIT(CRC_CR_CHSINV_POS) - -#define CRC_CR_DATINV_POS 18U -#define CRC_CR_DATINV_MSK BIT(CRC_CR_DATINV_POS) - -#define CRC_CR_CHSREV_POS 17U -#define CRC_CR_CHSREV_MSK BIT(CRC_CR_CHSREV_POS) - -#define CRC_CR_DATREV_POS 16U -#define CRC_CR_DATREV_MSK BIT(CRC_CR_DATREV_POS) - -#define CRC_CR_DMAEN_POS 4U -#define CRC_CR_DMAEN_MSK BIT(CRC_CR_DMAEN_POS) - -#define CRC_CR_CWERR_POS 3U -#define CRC_CR_CWERR_MSK BIT(CRC_CR_CWERR_POS) - -#define CRC_CR_WERR_POS 2U -#define CRC_CR_WERR_MSK BIT(CRC_CR_WERR_POS) - -#define CRC_CR_RST_POS 1U -#define CRC_CR_RST_MSK BIT(CRC_CR_RST_POS) - -#define CRC_CR_EN_POS 0U -#define CRC_CR_EN_MSK BIT(CRC_CR_EN_POS) - -/****************** Bit definition for CRC_DATA register ************************/ - -#define CRC_DATA_DATA_POSS 0U -#define CRC_DATA_DATA_POSE 31U -#define CRC_DATA_DATA_MSK BITS(CRC_DATA_DATA_POSS,CRC_DATA_DATA_POSE) - -/****************** Bit definition for CRC_SEED register ************************/ - -#define CRC_SEED_SEED_POSS 0U -#define CRC_SEED_SEED_POSE 31U -#define CRC_SEED_SEED_MSK BITS(CRC_SEED_SEED_POSS,CRC_SEED_SEED_POSE) - -/****************** Bit definition for CRC_CHECKSUM register ************************/ - -#define CRC_CHECKSUM_CHECKSUM_POSS 0U -#define CRC_CHECKSUM_CHECKSUM_POSE 31U -#define CRC_CHECKSUM_CHECKSUM_MSK BITS(CRC_CHECKSUM_CHECKSUM_POSS,CRC_CHECKSUM_CHECKSUM_POSE) - -typedef struct -{ - __IO uint32_t CR; - __IO uint32_t DATA; - __IO uint32_t SEED; - __I uint32_t CHECKSUM; -} CRC_TypeDef; - -/****************** Bit definition for CRYPT_CON register ************************/ - -#define CRYPT_CON_CRYSEL_POS 31U -#define CRYPT_CON_CRYSEL_MSK BIT(CRYPT_CON_CRYSEL_POS) - -#define CRYPT_CON_RESCLR_POS 15U -#define CRYPT_CON_RESCLR_MSK BIT(CRYPT_CON_RESCLR_POS) - -#define CRYPT_CON_DMAEN_POS 14U -#define CRYPT_CON_DMAEN_MSK BIT(CRYPT_CON_DMAEN_POS) - -#define CRYPT_CON_FIFOODR_POS 13U -#define CRYPT_CON_FIFOODR_MSK BIT(CRYPT_CON_FIFOODR_POS) - -#define CRYPT_CON_FIFOEN_POS 12U -#define CRYPT_CON_FIFOEN_MSK BIT(CRYPT_CON_FIFOEN_POS) - -#define CRYPT_CON_DESKS_POS 11U -#define CRYPT_CON_DESKS_MSK BIT(CRYPT_CON_DESKS_POS) - -#define CRYPT_CON_TDES_POS 10U -#define CRYPT_CON_TDES_MSK BIT(CRYPT_CON_TDES_POS) - -#define CRYPT_CON_TYPE_POSS 8U -#define CRYPT_CON_TYPE_POSE 9U -#define CRYPT_CON_TYPE_MSK BITS(CRYPT_CON_TYPE_POSS,CRYPT_CON_TYPE_POSE) - -#define CRYPT_CON_IE_POS 7U -#define CRYPT_CON_IE_MSK BIT(CRYPT_CON_IE_POS) - -#define CRYPT_CON_IVEN_POS 6U -#define CRYPT_CON_IVEN_MSK BIT(CRYPT_CON_IVEN_POS) - -#define CRYPT_CON_MODE_POSS 4U -#define CRYPT_CON_MODE_POSE 5U -#define CRYPT_CON_MODE_MSK BITS(CRYPT_CON_MODE_POSS,CRYPT_CON_MODE_POSE) - -#define CRYPT_CON_AESKS_POSS 2U -#define CRYPT_CON_AESKS_POSE 3U -#define CRYPT_CON_AESKS_MSK BITS(CRYPT_CON_AESKS_POSS,CRYPT_CON_AESKS_POSE) - -#define CRYPT_CON_ENCS_POS 1U -#define CRYPT_CON_ENCS_MSK BIT(CRYPT_CON_ENCS_POS) - -#define CRYPT_CON_GO_POS 0U -#define CRYPT_CON_GO_MSK BIT(CRYPT_CON_GO_POS) - -/****************** Bit definition for CRYPT_IF register ************************/ - -#define CRYPT_IF_DONE_POS 8U -#define CRYPT_IF_DONE_MSK BIT(CRYPT_IF_DONE_POS) - -#define CRYPT_IF_MULTHIF_POS 2U -#define CRYPT_IF_MULTHIF_MSK BIT(CRYPT_IF_MULTHIF_POS) - -#define CRYPT_IF_DESIF_POS 1U -#define CRYPT_IF_DESIF_MSK BIT(CRYPT_IF_DESIF_POS) - -#define CRYPT_IF_AESIF_POS 0U -#define CRYPT_IF_AESIF_MSK BIT(CRYPT_IF_AESIF_POS) - -/****************** Bit definition for CRYPT_IFC register ************************/ - -#define CRYPT_IFC_MULTHIFC_POS 2U -#define CRYPT_IFC_MULTHIFC_MSK BIT(CRYPT_IFC_MULTHIFC_POS) - -#define CRYPT_IFC_DESIFC_POS 1U -#define CRYPT_IFC_DESIFC_MSK BIT(CRYPT_IFC_DESIFC_POS) - -#define CRYPT_IFC_AESIFC_POS 0U -#define CRYPT_IFC_AESIFC_MSK BIT(CRYPT_IFC_AESIFC_POS) - -/****************** Bit definition for CRYPT_FIFO register ************************/ - -#define CRYPT_FIFO_FIFO_POSS 0U -#define CRYPT_FIFO_FIFO_POSE 31U -#define CRYPT_FIFO_FIFO_MSK BITS(CRYPT_FIFO_FIFO_POSS,CRYPT_FIFO_FIFO_POSE) - -typedef struct -{ - __IO uint32_t DATA[4]; - __IO uint32_t KEY[8]; - __IO uint32_t IV[4]; - __I uint32_t RES[4]; - __IO uint32_t CON; - __I uint32_t IF; - __O uint32_t IFC; - __IO uint32_t FIFO; -} CRYPT_TypeDef; - -/****************** Bit definition for LCD_CR register ************************/ - -#define LCD_CR_VCHPS_POSS 24U -#define LCD_CR_VCHPS_POSE 25U -#define LCD_CR_VCHPS_MSK BITS(LCD_CR_VCHPS_POSS,LCD_CR_VCHPS_POSE) - -#define LCD_CR_DSLD_POSS 20U -#define LCD_CR_DSLD_POSE 23U -#define LCD_CR_DSLD_MSK BITS(LCD_CR_DSLD_POSS,LCD_CR_DSLD_POSE) - -#define LCD_CR_DSHD_POSS 16U -#define LCD_CR_DSHD_POSE 19U -#define LCD_CR_DSHD_MSK BITS(LCD_CR_DSHD_POSS,LCD_CR_DSHD_POSE) - -#define LCD_CR_VBUFLD_POS 15U -#define LCD_CR_VBUFLD_MSK BIT(LCD_CR_VBUFLD_POS) - -#define LCD_CR_VBUFHD_POS 14U -#define LCD_CR_VBUFHD_MSK BIT(LCD_CR_VBUFHD_POS) - -#define LCD_CR_RESLD_POSS 12U -#define LCD_CR_RESLD_POSE 13U -#define LCD_CR_RESLD_MSK BITS(LCD_CR_RESLD_POSS,LCD_CR_RESLD_POSE) - -#define LCD_CR_RESHD_POSS 10U -#define LCD_CR_RESHD_POSE 11U -#define LCD_CR_RESHD_MSK BITS(LCD_CR_RESHD_POSS,LCD_CR_RESHD_POSE) - -#define LCD_CR_BIAS_POSS 8U -#define LCD_CR_BIAS_POSE 9U -#define LCD_CR_BIAS_MSK BITS(LCD_CR_BIAS_POSS,LCD_CR_BIAS_POSE) - -#define LCD_CR_DUTY_POSS 4U -#define LCD_CR_DUTY_POSE 6U -#define LCD_CR_DUTY_MSK BITS(LCD_CR_DUTY_POSS,LCD_CR_DUTY_POSE) - -#define LCD_CR_OE_POS 3U -#define LCD_CR_OE_MSK BIT(LCD_CR_OE_POS) - -#define LCD_CR_VSEL_POSS 1U -#define LCD_CR_VSEL_POSE 2U -#define LCD_CR_VSEL_MSK BITS(LCD_CR_VSEL_POSS,LCD_CR_VSEL_POSE) - -#define LCD_CR_EN_POS 0U -#define LCD_CR_EN_MSK BIT(LCD_CR_EN_POS) - -/****************** Bit definition for LCD_FCR register ************************/ - -#define LCD_FCR_WFS_POS 31U -#define LCD_FCR_WFS_MSK BIT(LCD_FCR_WFS_POS) - -#define LCD_FCR_PRS_POSS 24U -#define LCD_FCR_PRS_POSE 27U -#define LCD_FCR_PRS_MSK BITS(LCD_FCR_PRS_POSS,LCD_FCR_PRS_POSE) - -#define LCD_FCR_DIV_POSS 20U -#define LCD_FCR_DIV_POSE 23U -#define LCD_FCR_DIV_MSK BITS(LCD_FCR_DIV_POSS,LCD_FCR_DIV_POSE) - -#define LCD_FCR_BLMOD_POSS 16U -#define LCD_FCR_BLMOD_POSE 17U -#define LCD_FCR_BLMOD_MSK BITS(LCD_FCR_BLMOD_POSS,LCD_FCR_BLMOD_POSE) - -#define LCD_FCR_BLFRQ_POSS 12U -#define LCD_FCR_BLFRQ_POSE 14U -#define LCD_FCR_BLFRQ_MSK BITS(LCD_FCR_BLFRQ_POSS,LCD_FCR_BLFRQ_POSE) - -#define LCD_FCR_DEAD_POSS 8U -#define LCD_FCR_DEAD_POSE 10U -#define LCD_FCR_DEAD_MSK BITS(LCD_FCR_DEAD_POSS,LCD_FCR_DEAD_POSE) - -#define LCD_FCR_HD_POS 7U -#define LCD_FCR_HD_MSK BIT(LCD_FCR_HD_POS) - -#define LCD_FCR_PON_POSS 4U -#define LCD_FCR_PON_POSE 6U -#define LCD_FCR_PON_MSK BITS(LCD_FCR_PON_POSS,LCD_FCR_PON_POSE) - -#define LCD_FCR_VGS_POSS 0U -#define LCD_FCR_VGS_POSE 3U -#define LCD_FCR_VGS_MSK BITS(LCD_FCR_VGS_POSS,LCD_FCR_VGS_POSE) - -/****************** Bit definition for LCD_SEGCR0 register ************************/ - -#define LCD_SEGCR0_SEG_OE_POSS 0U -#define LCD_SEGCR0_SEG_OE_POSE 31U -#define LCD_SEGCR0_SEG_OE_MSK BITS(LCD_SEGCR0_SEG_OE_POSS,LCD_SEGCR0_SEG_OE_POSE) - -/****************** Bit definition for LCD_SEGCR1 register ************************/ - -#define LCD_SEGCR1_SEG_OE_POSS 0U -#define LCD_SEGCR1_SEG_OE_POSE 11U -#define LCD_SEGCR1_SEG_OE_MSK BITS(LCD_SEGCR1_SEG_OE_POSS,LCD_SEGCR1_SEG_OE_POSE) - -/****************** Bit definition for LCD_IE register ************************/ - -#define LCD_IE_UDDIE_POS 1U -#define LCD_IE_UDDIE_MSK BIT(LCD_IE_UDDIE_POS) - -#define LCD_IE_SOFIE_POS 0U -#define LCD_IE_SOFIE_MSK BIT(LCD_IE_SOFIE_POS) - -/****************** Bit definition for LCD_IF register ************************/ - -#define LCD_IF_UDDIF_POS 1U -#define LCD_IF_UDDIF_MSK BIT(LCD_IF_UDDIF_POS) - -#define LCD_IF_SOFIF_POS 0U -#define LCD_IF_SOFIF_MSK BIT(LCD_IF_SOFIF_POS) - -/****************** Bit definition for LCD_IFCR register ************************/ - -#define LCD_IFCR_UDDIFC_POS 1U -#define LCD_IFCR_UDDIFC_MSK BIT(LCD_IFCR_UDDIFC_POS) - -#define LCD_IFCR_SOFIFC_POS 0U -#define LCD_IFCR_SOFIFC_MSK BIT(LCD_IFCR_SOFIFC_POS) - -/****************** Bit definition for LCD_SR register ************************/ - -#define LCD_SR_FCRSF_POS 3U -#define LCD_SR_FCRSF_MSK BIT(LCD_SR_FCRSF_POS) - -#define LCD_SR_UDR_POS 2U -#define LCD_SR_UDR_MSK BIT(LCD_SR_UDR_POS) - -#define LCD_SR_ENS_POS 1U -#define LCD_SR_ENS_MSK BIT(LCD_SR_ENS_POS) - -#define LCD_SR_RDY_POS 0U -#define LCD_SR_RDY_MSK BIT(LCD_SR_RDY_POS) - -/****************** Bit definition for LCD_BUF register ************************/ - -#define LCD_BUF_SEG_DATA_POSS 0U -#define LCD_BUF_SEG_DATA_POSE 31U -#define LCD_BUF_SEG_DATA_MSK BITS(LCD_BUF_SEG_DATA_POSS,LCD_BUF_SEG_DATA_POSE) - -typedef struct -{ - __IO uint32_t CR; - __IO uint32_t FCR; - __IO uint32_t SEGCR0; - __IO uint32_t SEGCR1; - __IO uint32_t IE; - __I uint32_t IF; - __O uint32_t IFCR; - __I uint32_t SR; - uint32_t RESERVED0[8] ; - __IO uint32_t BUF[16]; -} LCD_TypeDef; - -/****************** Bit definition for ADC_STAT register ************************/ - -#define ADC_STAT_ICHS_POS 9U -#define ADC_STAT_ICHS_MSK BIT(ADC_STAT_ICHS_POS) - -#define ADC_STAT_NCHS_POS 8U -#define ADC_STAT_NCHS_MSK BIT(ADC_STAT_NCHS_POS) - -#define ADC_STAT_OVR_POS 3U -#define ADC_STAT_OVR_MSK BIT(ADC_STAT_OVR_POS) - -#define ADC_STAT_ICHE_POS 2U -#define ADC_STAT_ICHE_MSK BIT(ADC_STAT_ICHE_POS) - -#define ADC_STAT_NCHE_POS 1U -#define ADC_STAT_NCHE_MSK BIT(ADC_STAT_NCHE_POS) - -#define ADC_STAT_AWDF_POS 0U -#define ADC_STAT_AWDF_MSK BIT(ADC_STAT_AWDF_POS) - -/****************** Bit definition for ADC_CLR register ************************/ - -#define ADC_CLR_ICHS_POS 9U -#define ADC_CLR_ICHS_MSK BIT(ADC_CLR_ICHS_POS) - -#define ADC_CLR_NCHS_POS 8U -#define ADC_CLR_NCHS_MSK BIT(ADC_CLR_NCHS_POS) - -#define ADC_CLR_OVR_POS 3U -#define ADC_CLR_OVR_MSK BIT(ADC_CLR_OVR_POS) - -#define ADC_CLR_ICHE_POS 2U -#define ADC_CLR_ICHE_MSK BIT(ADC_CLR_ICHE_POS) - -#define ADC_CLR_NCHE_POS 1U -#define ADC_CLR_NCHE_MSK BIT(ADC_CLR_NCHE_POS) - -#define ADC_CLR_AWDF_POS 0U -#define ADC_CLR_AWDF_MSK BIT(ADC_CLR_AWDF_POS) - -/****************** Bit definition for ADC_CON0 register ************************/ - -#define ADC_CON0_OVRIE_POS 26U -#define ADC_CON0_OVRIE_MSK BIT(ADC_CON0_OVRIE_POS) - -#define ADC_CON0_RSEL_POSS 24U -#define ADC_CON0_RSEL_POSE 25U -#define ADC_CON0_RSEL_MSK BITS(ADC_CON0_RSEL_POSS,ADC_CON0_RSEL_POSE) - -#define ADC_CON0_NCHWDEN_POS 23U -#define ADC_CON0_NCHWDEN_MSK BIT(ADC_CON0_NCHWDEN_POS) - -#define ADC_CON0_ICHWDTEN_POS 22U -#define ADC_CON0_ICHWDTEN_MSK BIT(ADC_CON0_ICHWDTEN_POS) - -#define ADC_CON0_ETRGN_POSS 13U -#define ADC_CON0_ETRGN_POSE 15U -#define ADC_CON0_ETRGN_MSK BITS(ADC_CON0_ETRGN_POSS,ADC_CON0_ETRGN_POSE) - -#define ADC_CON0_ICHDCEN_POS 12U -#define ADC_CON0_ICHDCEN_MSK BIT(ADC_CON0_ICHDCEN_POS) - -#define ADC_CON0_NCHDCEN_POS 11U -#define ADC_CON0_NCHDCEN_MSK BIT(ADC_CON0_NCHDCEN_POS) - -#define ADC_CON0_IAUTO_POS 10U -#define ADC_CON0_IAUTO_MSK BIT(ADC_CON0_IAUTO_POS) - -#define ADC_CON0_AWDSGL_POS 9U -#define ADC_CON0_AWDSGL_MSK BIT(ADC_CON0_AWDSGL_POS) - -#define ADC_CON0_SCANEN_POS 8U -#define ADC_CON0_SCANEN_MSK BIT(ADC_CON0_SCANEN_POS) - -#define ADC_CON0_ICHEIE_POS 7U -#define ADC_CON0_ICHEIE_MSK BIT(ADC_CON0_ICHEIE_POS) - -#define ADC_CON0_AWDIE_POS 6U -#define ADC_CON0_AWDIE_MSK BIT(ADC_CON0_AWDIE_POS) - -#define ADC_CON0_NCHEIE_POS 5U -#define ADC_CON0_NCHEIE_MSK BIT(ADC_CON0_NCHEIE_POS) - -#define ADC_CON0_AWDCH_POSS 0U -#define ADC_CON0_AWDCH_POSE 4U -#define ADC_CON0_AWDCH_MSK BITS(ADC_CON0_AWDCH_POSS,ADC_CON0_AWDCH_POSE) - -/****************** Bit definition for ADC_CON1 register ************************/ - -#define ADC_CON1_NCHTRG_POS 30U -#define ADC_CON1_NCHTRG_MSK BIT(ADC_CON1_NCHTRG_POS) - -#define ADC_CON1_ICHTRG_POS 22U -#define ADC_CON1_ICHTRG_MSK BIT(ADC_CON1_ICHTRG_POS) - -#define ADC_CON1_ALIGN_POS 11U -#define ADC_CON1_ALIGN_MSK BIT(ADC_CON1_ALIGN_POS) - -#define ADC_CON1_NCHESEL_POS 10U -#define ADC_CON1_NCHESEL_MSK BIT(ADC_CON1_NCHESEL_POS) - -#define ADC_CON1_OVRDIS_POS 8U -#define ADC_CON1_OVRDIS_MSK BIT(ADC_CON1_OVRDIS_POS) - -#define ADC_CON1_CM_POS 1U -#define ADC_CON1_CM_MSK BIT(ADC_CON1_CM_POS) - -#define ADC_CON1_ADCEN_POS 0U -#define ADC_CON1_ADCEN_MSK BIT(ADC_CON1_ADCEN_POS) - -/****************** Bit definition for ADC_SMPT1 register ************************/ - -#define ADC_SMPT1_CHT_POSS 0U -#define ADC_SMPT1_CHT_POSE 31U -#define ADC_SMPT1_CHT_MSK BITS(ADC_SMPT1_CHT_POSS,ADC_SMPT1_CHT_POSE) - -/****************** Bit definition for ADC_SMPT2 register ************************/ - -#define ADC_SMPT2_CHT_POSS 0U -#define ADC_SMPT2_CHT_POSE 7U -#define ADC_SMPT2_CHT_MSK BITS(ADC_SMPT2_CHT_POSS,ADC_SMPT2_CHT_POSE) - -/****************** Bit definition for ADC_ICHOFF1 register ************************/ - -#define ADC_ICHOFF1_IOFF_POSS 0U -#define ADC_ICHOFF1_IOFF_POSE 11U -#define ADC_ICHOFF1_IOFF_MSK BITS(ADC_ICHOFF1_IOFF_POSS,ADC_ICHOFF1_IOFF_POSE) - -/****************** Bit definition for ADC_ICHOFF2 register ************************/ - -#define ADC_ICHOFF2_IOFF_POSS 0U -#define ADC_ICHOFF2_IOFF_POSE 11U -#define ADC_ICHOFF2_IOFF_MSK BITS(ADC_ICHOFF2_IOFF_POSS,ADC_ICHOFF2_IOFF_POSE) - -/****************** Bit definition for ADC_ICHOFF3 register ************************/ - -#define ADC_ICHOFF3_IOFF_POSS 0U -#define ADC_ICHOFF3_IOFF_POSE 11U -#define ADC_ICHOFF3_IOFF_MSK BITS(ADC_ICHOFF3_IOFF_POSS,ADC_ICHOFF3_IOFF_POSE) - -/****************** Bit definition for ADC_ICHOFF4 register ************************/ - -#define ADC_ICHOFF4_IOFF_POSS 0U -#define ADC_ICHOFF4_IOFF_POSE 11U -#define ADC_ICHOFF4_IOFF_MSK BITS(ADC_ICHOFF4_IOFF_POSS,ADC_ICHOFF4_IOFF_POSE) - -/****************** Bit definition for ADC_WDTH register ************************/ - -#define ADC_WDTH_HT_POSS 0U -#define ADC_WDTH_HT_POSE 11U -#define ADC_WDTH_HT_MSK BITS(ADC_WDTH_HT_POSS,ADC_WDTH_HT_POSE) - -/****************** Bit definition for ADC_WDTL register ************************/ - -#define ADC_WDTL_LT_POSS 0U -#define ADC_WDTL_LT_POSE 11U -#define ADC_WDTL_LT_MSK BITS(ADC_WDTL_LT_POSS,ADC_WDTL_LT_POSE) - -/****************** Bit definition for ADC_NCHS1 register ************************/ - -#define ADC_NCHS1_NS4_POSS 24U -#define ADC_NCHS1_NS4_POSE 28U -#define ADC_NCHS1_NS4_MSK BITS(ADC_NCHS1_NS4_POSS,ADC_NCHS1_NS4_POSE) - -#define ADC_NCHS1_NS3_POSS 16U -#define ADC_NCHS1_NS3_POSE 20U -#define ADC_NCHS1_NS3_MSK BITS(ADC_NCHS1_NS3_POSS,ADC_NCHS1_NS3_POSE) - -#define ADC_NCHS1_NS2_POSS 8U -#define ADC_NCHS1_NS2_POSE 12U -#define ADC_NCHS1_NS2_MSK BITS(ADC_NCHS1_NS2_POSS,ADC_NCHS1_NS2_POSE) - -#define ADC_NCHS1_NS1_POSS 0U -#define ADC_NCHS1_NS1_POSE 4U -#define ADC_NCHS1_NS1_MSK BITS(ADC_NCHS1_NS1_POSS,ADC_NCHS1_NS1_POSE) - -/****************** Bit definition for ADC_NCHS2 register ************************/ - -#define ADC_NCHS2_NS8_POSS 24U -#define ADC_NCHS2_NS8_POSE 28U -#define ADC_NCHS2_NS8_MSK BITS(ADC_NCHS2_NS8_POSS,ADC_NCHS2_NS8_POSE) - -#define ADC_NCHS2_NS7_POSS 16U -#define ADC_NCHS2_NS7_POSE 20U -#define ADC_NCHS2_NS7_MSK BITS(ADC_NCHS2_NS7_POSS,ADC_NCHS2_NS7_POSE) - -#define ADC_NCHS2_NS6_POSS 8U -#define ADC_NCHS2_NS6_POSE 12U -#define ADC_NCHS2_NS6_MSK BITS(ADC_NCHS2_NS6_POSS,ADC_NCHS2_NS6_POSE) - -#define ADC_NCHS2_NS5_POSS 0U -#define ADC_NCHS2_NS5_POSE 4U -#define ADC_NCHS2_NS5_MSK BITS(ADC_NCHS2_NS5_POSS,ADC_NCHS2_NS5_POSE) - -/****************** Bit definition for ADC_NCHS3 register ************************/ - -#define ADC_NCHS3_NS12_POSS 24U -#define ADC_NCHS3_NS12_POSE 28U -#define ADC_NCHS3_NS12_MSK BITS(ADC_NCHS3_NS12_POSS,ADC_NCHS3_NS12_POSE) - -#define ADC_NCHS3_NS11_POSS 16U -#define ADC_NCHS3_NS11_POSE 20U -#define ADC_NCHS3_NS11_MSK BITS(ADC_NCHS3_NS11_POSS,ADC_NCHS3_NS11_POSE) - -#define ADC_NCHS3_NS10_POSS 8U -#define ADC_NCHS3_NS10_POSE 12U -#define ADC_NCHS3_NS10_MSK BITS(ADC_NCHS3_NS10_POSS,ADC_NCHS3_NS10_POSE) - -#define ADC_NCHS3_NS9_POSS 0U -#define ADC_NCHS3_NS9_POSE 4U -#define ADC_NCHS3_NS9_MSK BITS(ADC_NCHS3_NS9_POSS,ADC_NCHS3_NS9_POSE) - -/****************** Bit definition for ADC_NCHS4 register ************************/ - -#define ADC_NCHS4_NS16_POSS 24U -#define ADC_NCHS4_NS16_POSE 28U -#define ADC_NCHS4_NS16_MSK BITS(ADC_NCHS4_NS16_POSS,ADC_NCHS4_NS16_POSE) - -#define ADC_NCHS4_NS15_POSS 16U -#define ADC_NCHS4_NS15_POSE 20U -#define ADC_NCHS4_NS15_MSK BITS(ADC_NCHS4_NS15_POSS,ADC_NCHS4_NS15_POSE) - -#define ADC_NCHS4_NS14_POSS 8U -#define ADC_NCHS4_NS14_POSE 12U -#define ADC_NCHS4_NS14_MSK BITS(ADC_NCHS4_NS14_POSS,ADC_NCHS4_NS14_POSE) - -#define ADC_NCHS4_NS13_POSS 0U -#define ADC_NCHS4_NS13_POSE 4U -#define ADC_NCHS4_NS13_MSK BITS(ADC_NCHS4_NS13_POSS,ADC_NCHS4_NS13_POSE) - -/****************** Bit definition for ADC_ICHS register ************************/ - -#define ADC_ICHS_IS4_POSS 24U -#define ADC_ICHS_IS4_POSE 28U -#define ADC_ICHS_IS4_MSK BITS(ADC_ICHS_IS4_POSS,ADC_ICHS_IS4_POSE) - -#define ADC_ICHS_IS3_POSS 16U -#define ADC_ICHS_IS3_POSE 20U -#define ADC_ICHS_IS3_MSK BITS(ADC_ICHS_IS3_POSS,ADC_ICHS_IS3_POSE) - -#define ADC_ICHS_IS2_POSS 8U -#define ADC_ICHS_IS2_POSE 12U -#define ADC_ICHS_IS2_MSK BITS(ADC_ICHS_IS2_POSS,ADC_ICHS_IS2_POSE) - -#define ADC_ICHS_IS1_POSS 0U -#define ADC_ICHS_IS1_POSE 4U -#define ADC_ICHS_IS1_MSK BITS(ADC_ICHS_IS1_POSS,ADC_ICHS_IS1_POSE) - -/****************** Bit definition for ADC_CHSL register ************************/ - -#define ADC_CHSL_ISL_POSS 8U -#define ADC_CHSL_ISL_POSE 9U -#define ADC_CHSL_ISL_MSK BITS(ADC_CHSL_ISL_POSS,ADC_CHSL_ISL_POSE) - -#define ADC_CHSL_NSL_POSS 0U -#define ADC_CHSL_NSL_POSE 3U -#define ADC_CHSL_NSL_MSK BITS(ADC_CHSL_NSL_POSS,ADC_CHSL_NSL_POSE) - -/****************** Bit definition for ADC_ICHDR1 register ************************/ - -#define ADC_ICHDR1_VAL_POSS 0U -#define ADC_ICHDR1_VAL_POSE 15U -#define ADC_ICHDR1_VAL_MSK BITS(ADC_ICHDR1_VAL_POSS,ADC_ICHDR1_VAL_POSE) - -/****************** Bit definition for ADC_ICHDR2 register ************************/ - -#define ADC_ICHDR2_VAL_POSS 0U -#define ADC_ICHDR2_VAL_POSE 15U -#define ADC_ICHDR2_VAL_MSK BITS(ADC_ICHDR2_VAL_POSS,ADC_ICHDR2_VAL_POSE) - -/****************** Bit definition for ADC_ICHDR3 register ************************/ - -#define ADC_ICHDR3_VAL_POSS 0U -#define ADC_ICHDR3_VAL_POSE 15U -#define ADC_ICHDR3_VAL_MSK BITS(ADC_ICHDR3_VAL_POSS,ADC_ICHDR3_VAL_POSE) - -/****************** Bit definition for ADC_ICHDR4 register ************************/ - -#define ADC_ICHDR4_VAL_POSS 0U -#define ADC_ICHDR4_VAL_POSE 15U -#define ADC_ICHDR4_VAL_MSK BITS(ADC_ICHDR4_VAL_POSS,ADC_ICHDR4_VAL_POSE) - -/****************** Bit definition for ADC_NCHDR register ************************/ - -#define ADC_NCHDR_VAL_POSS 0U -#define ADC_NCHDR_VAL_POSE 15U -#define ADC_NCHDR_VAL_MSK BITS(ADC_NCHDR_VAL_POSS,ADC_NCHDR_VAL_POSE) - -/****************** Bit definition for ADC_CCR register ************************/ - -#define ADC_CCR_TRMEN_POS 28U -#define ADC_CCR_TRMEN_MSK BIT(ADC_CCR_TRMEN_POS) - -#define ADC_CCR_GAINCALEN_POS 25U -#define ADC_CCR_GAINCALEN_MSK BIT(ADC_CCR_GAINCALEN_POS) - -#define ADC_CCR_OFFCALEN_POS 24U -#define ADC_CCR_OFFCALEN_MSK BIT(ADC_CCR_OFFCALEN_POS) - -#define ADC_CCR_VREFOEN_POS 19U -#define ADC_CCR_VREFOEN_MSK BIT(ADC_CCR_VREFOEN_POS) - -#define ADC_CCR_VRNSEL_POS 18U -#define ADC_CCR_VRNSEL_MSK BIT(ADC_CCR_VRNSEL_POS) - -#define ADC_CCR_VRPSEL_POSS 16U -#define ADC_CCR_VRPSEL_POSE 17U -#define ADC_CCR_VRPSEL_MSK BITS(ADC_CCR_VRPSEL_POSS,ADC_CCR_VRPSEL_POSE) - -#define ADC_CCR_PWRMODSEL_POS 15U -#define ADC_CCR_PWRMODSEL_MSK BIT(ADC_CCR_PWRMODSEL_POS) - -#define ADC_CCR_DIFFEN_POS 12U -#define ADC_CCR_DIFFEN_MSK BIT(ADC_CCR_DIFFEN_POS) - -#define ADC_CCR_IREFEN_POS 11U -#define ADC_CCR_IREFEN_MSK BIT(ADC_CCR_IREFEN_POS) - -#define ADC_CCR_VRBUFEN_POS 10U -#define ADC_CCR_VRBUFEN_MSK BIT(ADC_CCR_VRBUFEN_POS) - -#define ADC_CCR_VCMBUFEN_POS 9U -#define ADC_CCR_VCMBUFEN_MSK BIT(ADC_CCR_VCMBUFEN_POS) - -#define ADC_CCR_VREFEN_POS 8U -#define ADC_CCR_VREFEN_MSK BIT(ADC_CCR_VREFEN_POS) - -#define ADC_CCR_CKDIV_POSS 0U -#define ADC_CCR_CKDIV_POSE 2U -#define ADC_CCR_CKDIV_MSK BITS(ADC_CCR_CKDIV_POSS,ADC_CCR_CKDIV_POSE) - -typedef struct -{ - __I uint32_t STAT; - __O uint32_t CLR; - __IO uint32_t CON0; - __IO uint32_t CON1; - __IO uint32_t SMPT1; - __IO uint32_t SMPT2; - __IO uint32_t ICHOFF[4]; - __IO uint32_t WDTH; - __IO uint32_t WDTL; - __IO uint32_t NCHS1; - __IO uint32_t NCHS2; - __IO uint32_t NCHS3; - __IO uint32_t NCHS4; - __IO uint32_t ICHS; - __IO uint32_t CHSL; - __I uint32_t ICHDR[4]; - __I uint32_t NCHDR; - __IO uint32_t CCR; -} ADC_TypeDef; - -/****************** Bit definition for ACMP_CON register ************************/ - -#define ACMP_CON_FALLEN_POS 17U -#define ACMP_CON_FALLEN_MSK BIT(ACMP_CON_FALLEN_POS) - -#define ACMP_CON_RISEEN_POS 16U -#define ACMP_CON_RISEEN_MSK BIT(ACMP_CON_RISEEN_POS) - -#define ACMP_CON_MODSEL_POSS 14U -#define ACMP_CON_MODSEL_POSE 15U -#define ACMP_CON_MODSEL_MSK BITS(ACMP_CON_MODSEL_POSS,ACMP_CON_MODSEL_POSE) - -#define ACMP_CON_WARMUPT_POSS 8U -#define ACMP_CON_WARMUPT_POSE 10U -#define ACMP_CON_WARMUPT_MSK BITS(ACMP_CON_WARMUPT_POSS,ACMP_CON_WARMUPT_POSE) - -#define ACMP_CON_HYSTSEL_POSS 4U -#define ACMP_CON_HYSTSEL_POSE 6U -#define ACMP_CON_HYSTSEL_MSK BITS(ACMP_CON_HYSTSEL_POSS,ACMP_CON_HYSTSEL_POSE) - -#define ACMP_CON_OUTINV_POS 3U -#define ACMP_CON_OUTINV_MSK BIT(ACMP_CON_OUTINV_POS) - -#define ACMP_CON_INACTV_POS 2U -#define ACMP_CON_INACTV_MSK BIT(ACMP_CON_INACTV_POS) - -#define ACMP_CON_EN_POS 0U -#define ACMP_CON_EN_MSK BIT(ACMP_CON_EN_POS) - -/****************** Bit definition for ACMP_INPUTSEL register ************************/ - -#define ACMP_INPUTSEL_VDDLVL_POSS 8U -#define ACMP_INPUTSEL_VDDLVL_POSE 13U -#define ACMP_INPUTSEL_VDDLVL_MSK BITS(ACMP_INPUTSEL_VDDLVL_POSS,ACMP_INPUTSEL_VDDLVL_POSE) - -#define ACMP_INPUTSEL_NSEL_POSS 4U -#define ACMP_INPUTSEL_NSEL_POSE 7U -#define ACMP_INPUTSEL_NSEL_MSK BITS(ACMP_INPUTSEL_NSEL_POSS,ACMP_INPUTSEL_NSEL_POSE) - -#define ACMP_INPUTSEL_PSEL_POSS 0U -#define ACMP_INPUTSEL_PSEL_POSE 2U -#define ACMP_INPUTSEL_PSEL_MSK BITS(ACMP_INPUTSEL_PSEL_POSS,ACMP_INPUTSEL_PSEL_POSE) - -/****************** Bit definition for ACMP_STAT register ************************/ - -#define ACMP_STAT_OUT_POS 1U -#define ACMP_STAT_OUT_MSK BIT(ACMP_STAT_OUT_POS) - -#define ACMP_STAT_ACT_POS 0U -#define ACMP_STAT_ACT_MSK BIT(ACMP_STAT_ACT_POS) - -/****************** Bit definition for ACMP_IES register ************************/ - -#define ACMP_IES_WARMUP_POS 1U -#define ACMP_IES_WARMUP_MSK BIT(ACMP_IES_WARMUP_POS) - -#define ACMP_IES_EDGE_POS 0U -#define ACMP_IES_EDGE_MSK BIT(ACMP_IES_EDGE_POS) - -/****************** Bit definition for ACMP_IEV register ************************/ - -#define ACMP_IEV_WARMUP_POS 1U -#define ACMP_IEV_WARMUP_MSK BIT(ACMP_IEV_WARMUP_POS) - -#define ACMP_IEV_EDGE_POS 0U -#define ACMP_IEV_EDGE_MSK BIT(ACMP_IEV_EDGE_POS) - -/****************** Bit definition for ACMP_IEC register ************************/ - -#define ACMP_IEC_WARMUP_POS 1U -#define ACMP_IEC_WARMUP_MSK BIT(ACMP_IEC_WARMUP_POS) - -#define ACMP_IEC_EDGE_POS 0U -#define ACMP_IEC_EDGE_MSK BIT(ACMP_IEC_EDGE_POS) - -/****************** Bit definition for ACMP_RIF register ************************/ - -#define ACMP_RIF_WARMUP_POS 1U -#define ACMP_RIF_WARMUP_MSK BIT(ACMP_RIF_WARMUP_POS) - -#define ACMP_RIF_EDGE_POS 0U -#define ACMP_RIF_EDGE_MSK BIT(ACMP_RIF_EDGE_POS) - -/****************** Bit definition for ACMP_IFM register ************************/ - -#define ACMP_IFM_WARMUP_POS 1U -#define ACMP_IFM_WARMUP_MSK BIT(ACMP_IFM_WARMUP_POS) - -#define ACMP_IFM_EDGE_POS 0U -#define ACMP_IFM_EDGE_MSK BIT(ACMP_IFM_EDGE_POS) - -/****************** Bit definition for ACMP_IFC register ************************/ - -#define ACMP_IFC_WARMUP_POS 1U -#define ACMP_IFC_WARMUP_MSK BIT(ACMP_IFC_WARMUP_POS) - -#define ACMP_IFC_EDGE_POS 0U -#define ACMP_IFC_EDGE_MSK BIT(ACMP_IFC_EDGE_POS) - -/****************** Bit definition for ACMP_PORT register ************************/ - -#define ACMP_PORT_PEN_POS 0U -#define ACMP_PORT_PEN_MSK BIT(ACMP_PORT_PEN_POS) - -typedef struct -{ - __IO uint32_t CON; - __IO uint32_t INPUTSEL; - __I uint32_t STAT; - __O uint32_t IES; - __I uint32_t IEV; - __O uint32_t IEC; - __I uint32_t RIF; - __O uint32_t IFM; - __O uint32_t IFC; - __IO uint32_t PORT; -} ACMP_TypeDef; - -/****************** Bit definition for CALC_SQRTSR register ************************/ - -#define CALC_SQRTSR_BUSY_POS 0U -#define CALC_SQRTSR_BUSY_MSK BIT(CALC_SQRTSR_BUSY_POS) - -/****************** Bit definition for CALC_RDCND register ************************/ - -#define CALC_RDCND_RADICAND_POSS 0U -#define CALC_RDCND_RADICAND_POSE 31U -#define CALC_RDCND_RADICAND_MSK BITS(CALC_RDCND_RADICAND_POSS,CALC_RDCND_RADICAND_POSE) - -/****************** Bit definition for CALC_SQRTRES register ************************/ - -#define CALC_SQRTRES_RESULT_POSS 0U -#define CALC_SQRTRES_RESULT_POSE 15U -#define CALC_SQRTRES_RESULT_MSK BITS(CALC_SQRTRES_RESULT_POSS,CALC_SQRTRES_RESULT_POSE) - -/****************** Bit definition for CALC_DIVDR register ************************/ - -#define CALC_DIVDR_DIVD_POSS 0U -#define CALC_DIVDR_DIVD_POSE 31U -#define CALC_DIVDR_DIVD_MSK BITS(CALC_DIVDR_DIVD_POSS,CALC_DIVDR_DIVD_POSE) - -/****************** Bit definition for CALC_DIVSR register ************************/ - -#define CALC_DIVSR_DIVS_POSS 0U -#define CALC_DIVSR_DIVS_POSE 31U -#define CALC_DIVSR_DIVS_MSK BITS(CALC_DIVSR_DIVS_POSS,CALC_DIVSR_DIVS_POSE) - -/****************** Bit definition for CALC_DIVQR register ************************/ - -#define CALC_DIVQR_DIVQ_POSS 0U -#define CALC_DIVQR_DIVQ_POSE 31U -#define CALC_DIVQR_DIVQ_MSK BITS(CALC_DIVQR_DIVQ_POSS,CALC_DIVQR_DIVQ_POSE) - -/****************** Bit definition for CALC_DIVRR register ************************/ - -#define CALC_DIVRR_DIVS_POSS 0U -#define CALC_DIVRR_DIVS_POSE 31U -#define CALC_DIVRR_DIVS_MSK BITS(CALC_DIVRR_DIVS_POSS,CALC_DIVRR_DIVS_POSE) - -/****************** Bit definition for CALC_DIVCSR register ************************/ - -#define CALC_DIVCSR_TRM_POS 9U -#define CALC_DIVCSR_TRM_MSK BIT(CALC_DIVCSR_TRM_POS) - -#define CALC_DIVCSR_SIGN_POS 8U -#define CALC_DIVCSR_SIGN_MSK BIT(CALC_DIVCSR_SIGN_POS) - -#define CALC_DIVCSR_DZ_POS 1U -#define CALC_DIVCSR_DZ_MSK BIT(CALC_DIVCSR_DZ_POS) - -#define CALC_DIVCSR_BUSY_POS 0U -#define CALC_DIVCSR_BUSY_MSK BIT(CALC_DIVCSR_BUSY_POS) - -typedef struct -{ - __I uint32_t SQRTSR; - __IO uint32_t RDCND; - __I uint32_t SQRTRES; - uint32_t RESERVED0[5] ; - __IO uint32_t DIVDR; - __IO uint32_t DIVSR; - __I uint32_t DIVQR; - __I uint32_t DIVRR; - __IO uint32_t DIVCSR; -} CALC_TypeDef; - -/****************** Bit definition for TRNG_CR register ************************/ - -#define TRNG_CR_ADJC_POSS 16U -#define TRNG_CR_ADJC_POSE 17U -#define TRNG_CR_ADJC_MSK BITS(TRNG_CR_ADJC_POSS,TRNG_CR_ADJC_POSE) - -#define TRNG_CR_SDSEL_POSS 10U -#define TRNG_CR_SDSEL_POSE 11U -#define TRNG_CR_SDSEL_MSK BITS(TRNG_CR_SDSEL_POSS,TRNG_CR_SDSEL_POSE) - -#define TRNG_CR_DSEL_POSS 8U -#define TRNG_CR_DSEL_POSE 9U -#define TRNG_CR_DSEL_MSK BITS(TRNG_CR_DSEL_POSS,TRNG_CR_DSEL_POSE) - -#define TRNG_CR_POSTEN_POS 3U -#define TRNG_CR_POSTEN_MSK BIT(TRNG_CR_POSTEN_POS) - -#define TRNG_CR_TRNGSEL_POS 2U -#define TRNG_CR_TRNGSEL_MSK BIT(TRNG_CR_TRNGSEL_POS) - -#define TRNG_CR_ADJM_POS 1U -#define TRNG_CR_ADJM_MSK BIT(TRNG_CR_ADJM_POS) - -#define TRNG_CR_TRNGEN_POS 0U -#define TRNG_CR_TRNGEN_MSK BIT(TRNG_CR_TRNGEN_POS) - -/****************** Bit definition for TRNG_SR register ************************/ - -#define TRNG_SR_OVER_POS 3U -#define TRNG_SR_OVER_MSK BIT(TRNG_SR_OVER_POS) - -#define TRNG_SR_SERR_POS 2U -#define TRNG_SR_SERR_MSK BIT(TRNG_SR_SERR_POS) - -#define TRNG_SR_DAVLD_POS 1U -#define TRNG_SR_DAVLD_MSK BIT(TRNG_SR_DAVLD_POS) - -#define TRNG_SR_START_POS 0U -#define TRNG_SR_START_MSK BIT(TRNG_SR_START_POS) - -/****************** Bit definition for TRNG_DR register ************************/ - -#define TRNG_DR_DATA_POSS 0U -#define TRNG_DR_DATA_POSE 31U -#define TRNG_DR_DATA_MSK BITS(TRNG_DR_DATA_POSS,TRNG_DR_DATA_POSE) - -/****************** Bit definition for TRNG_SEED register ************************/ - -#define TRNG_SEED_SEED_POSS 0U -#define TRNG_SEED_SEED_POSE 31U -#define TRNG_SEED_SEED_MSK BITS(TRNG_SEED_SEED_POSS,TRNG_SEED_SEED_POSE) - -/****************** Bit definition for TRNG_CFGR register ************************/ - -#define TRNG_CFGR_TOPLMT_POSS 16U -#define TRNG_CFGR_TOPLMT_POSE 24U -#define TRNG_CFGR_TOPLMT_MSK BITS(TRNG_CFGR_TOPLMT_POSS,TRNG_CFGR_TOPLMT_POSE) - -#define TRNG_CFGR_CKDIV_POSS 8U -#define TRNG_CFGR_CKDIV_POSE 11U -#define TRNG_CFGR_CKDIV_MSK BITS(TRNG_CFGR_CKDIV_POSS,TRNG_CFGR_CKDIV_POSE) - -#define TRNG_CFGR_TSTART_POSS 0U -#define TRNG_CFGR_TSTART_POSE 2U -#define TRNG_CFGR_TSTART_MSK BITS(TRNG_CFGR_TSTART_POSS,TRNG_CFGR_TSTART_POSE) - -/****************** Bit definition for TRNG_IER register ************************/ - -#define TRNG_IER_SERR_POS 2U -#define TRNG_IER_SERR_MSK BIT(TRNG_IER_SERR_POS) - -#define TRNG_IER_DAVLD_POS 1U -#define TRNG_IER_DAVLD_MSK BIT(TRNG_IER_DAVLD_POS) - -#define TRNG_IER_START_POS 0U -#define TRNG_IER_START_MSK BIT(TRNG_IER_START_POS) - -/****************** Bit definition for TRNG_IFR register ************************/ - -#define TRNG_IFR_SERR_POS 2U -#define TRNG_IFR_SERR_MSK BIT(TRNG_IFR_SERR_POS) - -#define TRNG_IFR_DAVLD_POS 1U -#define TRNG_IFR_DAVLD_MSK BIT(TRNG_IFR_DAVLD_POS) - -#define TRNG_IFR_START_POS 0U -#define TRNG_IFR_START_MSK BIT(TRNG_IFR_START_POS) - -/****************** Bit definition for TRNG_IFCR register ************************/ - -#define TRNG_IFCR_SERRC_POS 2U -#define TRNG_IFCR_SERRC_MSK BIT(TRNG_IFCR_SERRC_POS) - -#define TRNG_IFCR_DAVLDC_POS 1U -#define TRNG_IFCR_DAVLDC_MSK BIT(TRNG_IFCR_DAVLDC_POS) - -#define TRNG_IFCR_STARTC_POS 0U -#define TRNG_IFCR_STARTC_MSK BIT(TRNG_IFCR_STARTC_POS) - -/****************** Bit definition for TRNG_ISR register ************************/ - -#define TRNG_ISR_SERR_POS 2U -#define TRNG_ISR_SERR_MSK BIT(TRNG_ISR_SERR_POS) - -#define TRNG_ISR_DAVLD_POS 1U -#define TRNG_ISR_DAVLD_MSK BIT(TRNG_ISR_DAVLD_POS) - -#define TRNG_ISR_START_POS 0U -#define TRNG_ISR_START_MSK BIT(TRNG_ISR_START_POS) - -typedef struct -{ - __IO uint32_t CR; - __I uint32_t SR; - __I uint32_t DR; - __IO uint32_t SEED; - __IO uint32_t CFGR; - __IO uint32_t IER; - __I uint32_t IFR; - __O uint32_t IFCR; - __I uint32_t ISR; -} TRNG_TypeDef; - -/****************** Bit definition for TSENSE_WPR register ************************/ - -#define TSENSE_WPR_WP_POS 0U -#define TSENSE_WPR_WP_MSK BIT(TSENSE_WPR_WP_POS) - -/****************** Bit definition for TSENSE_CR register ************************/ - -#define TSENSE_CR_TSU_POSS 12U -#define TSENSE_CR_TSU_POSE 14U -#define TSENSE_CR_TSU_MSK BITS(TSENSE_CR_TSU_POSS,TSENSE_CR_TSU_POSE) - -#define TSENSE_CR_TOM_POSS 8U -#define TSENSE_CR_TOM_POSE 10U -#define TSENSE_CR_TOM_MSK BITS(TSENSE_CR_TOM_POSS,TSENSE_CR_TOM_POSE) - -#define TSENSE_CR_CTN_POS 4U -#define TSENSE_CR_CTN_MSK BIT(TSENSE_CR_CTN_POS) - -#define TSENSE_CR_RST_POS 3U -#define TSENSE_CR_RST_MSK BIT(TSENSE_CR_RST_POS) - -#define TSENSE_CR_ENS_POS 2U -#define TSENSE_CR_ENS_MSK BIT(TSENSE_CR_ENS_POS) - -#define TSENSE_CR_REQEN_POS 1U -#define TSENSE_CR_REQEN_MSK BIT(TSENSE_CR_REQEN_POS) - -#define TSENSE_CR_EN_POS 0U -#define TSENSE_CR_EN_MSK BIT(TSENSE_CR_EN_POS) - -/****************** Bit definition for TSENSE_DR register ************************/ - -#define TSENSE_DR_ERR_POS 31U -#define TSENSE_DR_ERR_MSK BIT(TSENSE_DR_ERR_POS) - -#define TSENSE_DR_DATA_POSS 0U -#define TSENSE_DR_DATA_POSE 15U -#define TSENSE_DR_DATA_MSK BITS(TSENSE_DR_DATA_POSS,TSENSE_DR_DATA_POSE) - -/****************** Bit definition for TSENSE_PSR register ************************/ - -#define TSENSE_PSR_PRS_POSS 0U -#define TSENSE_PSR_PRS_POSE 7U -#define TSENSE_PSR_PRS_MSK BITS(TSENSE_PSR_PRS_POSS,TSENSE_PSR_PRS_POSE) - -/****************** Bit definition for TSENSE_IE register ************************/ - -#define TSENSE_IE_TSENSE_POS 0U -#define TSENSE_IE_TSENSE_MSK BIT(TSENSE_IE_TSENSE_POS) - -/****************** Bit definition for TSENSE_IF register ************************/ - -#define TSENSE_IF_TSENSE_POS 0U -#define TSENSE_IF_TSENSE_MSK BIT(TSENSE_IF_TSENSE_POS) - -/****************** Bit definition for TSENSE_IFCR register ************************/ - -#define TSENSE_IFCR_TSENSE_POS 0U -#define TSENSE_IFCR_TSENSE_MSK BIT(TSENSE_IFCR_TSENSE_POS) - -/****************** Bit definition for TSENSE_LTGR register ************************/ - -#define TSENSE_LTGR_LTG_POSS 0U -#define TSENSE_LTGR_LTG_POSE 20U -#define TSENSE_LTGR_LTG_MSK BITS(TSENSE_LTGR_LTG_POSS,TSENSE_LTGR_LTG_POSE) - -/****************** Bit definition for TSENSE_HTGR register ************************/ - -#define TSENSE_HTGR_HTG_POSS 0U -#define TSENSE_HTGR_HTG_POSE 20U -#define TSENSE_HTGR_HTG_MSK BITS(TSENSE_HTGR_HTG_POSS,TSENSE_HTGR_HTG_POSE) - -/****************** Bit definition for TSENSE_TBDR register ************************/ - -#define TSENSE_TBDR_TBD_POSS 0U -#define TSENSE_TBDR_TBD_POSE 15U -#define TSENSE_TBDR_TBD_MSK BITS(TSENSE_TBDR_TBD_POSS,TSENSE_TBDR_TBD_POSE) - -/****************** Bit definition for TSENSE_TCALBDR register ************************/ - -#define TSENSE_TCALBDR_TCAL_POSS 0U -#define TSENSE_TCALBDR_TCAL_POSE 16U -#define TSENSE_TCALBDR_TCAL_MSK BITS(TSENSE_TCALBDR_TCAL_POSS,TSENSE_TCALBDR_TCAL_POSE) - -/****************** Bit definition for TSENSE_SR register ************************/ - -#define TSENSE_SR_TSOUT_POS 31U -#define TSENSE_SR_TSOUT_MSK BIT(TSENSE_SR_TSOUT_POS) - -#define TSENSE_SR_NVLD_POS 25U -#define TSENSE_SR_NVLD_MSK BIT(TSENSE_SR_NVLD_POS) - -#define TSENSE_SR_TCAL_POSS 0U -#define TSENSE_SR_TCAL_POSE 24U -#define TSENSE_SR_TCAL_MSK BITS(TSENSE_SR_TCAL_POSS,TSENSE_SR_TCAL_POSE) - -typedef struct -{ - __IO uint32_t WPR; - __IO uint32_t CR; - __I uint32_t DR; - __IO uint32_t PSR; - __IO uint32_t IE; - __I uint32_t IF; - __IO uint32_t IFCR; - __IO uint32_t LTGR; - __IO uint32_t HTGR; - __IO uint32_t TBDR; - __IO uint32_t TCALBDR; - __I uint32_t SR; -} TSENSE_TypeDef; - -/****************** Bit definition for IWDT_LOAD register ************************/ - -#define IWDT_LOAD_LOAD_POSS 0U -#define IWDT_LOAD_LOAD_POSE 31U -#define IWDT_LOAD_LOAD_MSK BITS(IWDT_LOAD_LOAD_POSS,IWDT_LOAD_LOAD_POSE) - -/****************** Bit definition for IWDT_VALUE register ************************/ - -#define IWDT_VALUE_VALUE_POSS 0U -#define IWDT_VALUE_VALUE_POSE 31U -#define IWDT_VALUE_VALUE_MSK BITS(IWDT_VALUE_VALUE_POSS,IWDT_VALUE_VALUE_POSE) - -/****************** Bit definition for IWDT_CON register ************************/ - -#define IWDT_CON_CLKS_POS 3U -#define IWDT_CON_CLKS_MSK BIT(IWDT_CON_CLKS_POS) - -#define IWDT_CON_RSTEN_POS 2U -#define IWDT_CON_RSTEN_MSK BIT(IWDT_CON_RSTEN_POS) - -#define IWDT_CON_IE_POS 1U -#define IWDT_CON_IE_MSK BIT(IWDT_CON_IE_POS) - -#define IWDT_CON_EN_POS 0U -#define IWDT_CON_EN_MSK BIT(IWDT_CON_EN_POS) - -/****************** Bit definition for IWDT_INTCLR register ************************/ - -#define IWDT_INTCLR_INTCLR_POSS 0U -#define IWDT_INTCLR_INTCLR_POSE 31U -#define IWDT_INTCLR_INTCLR_MSK BITS(IWDT_INTCLR_INTCLR_POSS,IWDT_INTCLR_INTCLR_POSE) - -/****************** Bit definition for IWDT_RIS register ************************/ - -#define IWDT_RIS_WDTIF_POS 0U -#define IWDT_RIS_WDTIF_MSK BIT(IWDT_RIS_WDTIF_POS) - -/****************** Bit definition for IWDT_LOCK register ************************/ - -#define IWDT_LOCK_LOCK_POS 0U -#define IWDT_LOCK_LOCK_MSK BIT(IWDT_LOCK_LOCK_POS) - -typedef struct -{ - __O uint32_t LOAD; - __I uint32_t VALUE; - __IO uint32_t CON; - __O uint32_t INTCLR; - __I uint32_t RIS; - uint32_t RESERVED0[59] ; - __IO uint32_t LOCK; -} IWDT_TypeDef; - -/****************** Bit definition for WWDT_LOAD register ************************/ - -#define WWDT_LOAD_LOAD_POSS 0U -#define WWDT_LOAD_LOAD_POSE 31U -#define WWDT_LOAD_LOAD_MSK BITS(WWDT_LOAD_LOAD_POSS,WWDT_LOAD_LOAD_POSE) - -/****************** Bit definition for WWDT_VALUE register ************************/ - -#define WWDT_VALUE_VALUE_POSS 0U -#define WWDT_VALUE_VALUE_POSE 31U -#define WWDT_VALUE_VALUE_MSK BITS(WWDT_VALUE_VALUE_POSS,WWDT_VALUE_VALUE_POSE) - -/****************** Bit definition for WWDT_CON register ************************/ - -#define WWDT_CON_WWDTWIN_POSS 4U -#define WWDT_CON_WWDTWIN_POSE 5U -#define WWDT_CON_WWDTWIN_MSK BITS(WWDT_CON_WWDTWIN_POSS,WWDT_CON_WWDTWIN_POSE) - -#define WWDT_CON_CLKS_POS 3U -#define WWDT_CON_CLKS_MSK BIT(WWDT_CON_CLKS_POS) - -#define WWDT_CON_RSTEN_POS 2U -#define WWDT_CON_RSTEN_MSK BIT(WWDT_CON_RSTEN_POS) - -#define WWDT_CON_IE_POS 1U -#define WWDT_CON_IE_MSK BIT(WWDT_CON_IE_POS) - -#define WWDT_CON_EN_POS 0U -#define WWDT_CON_EN_MSK BIT(WWDT_CON_EN_POS) - -/****************** Bit definition for WWDT_INTCLR register ************************/ - -#define WWDT_INTCLR_INTCLR_POSS 0U -#define WWDT_INTCLR_INTCLR_POSE 31U -#define WWDT_INTCLR_INTCLR_MSK BITS(WWDT_INTCLR_INTCLR_POSS,WWDT_INTCLR_INTCLR_POSE) - -/****************** Bit definition for WWDT_RIS register ************************/ - -#define WWDT_RIS_WWDTIF_POS 0U -#define WWDT_RIS_WWDTIF_MSK BIT(WWDT_RIS_WWDTIF_POS) - -/****************** Bit definition for WWDT_LOCK register ************************/ - -#define WWDT_LOCK_LOCK_POS 0U -#define WWDT_LOCK_LOCK_MSK BIT(WWDT_LOCK_LOCK_POS) - -typedef struct -{ - __O uint32_t LOAD; - __I uint32_t VALUE; - __IO uint32_t CON; - __O uint32_t INTCLR; - __I uint32_t RIS; - uint32_t RESERVED0[59]; - __IO uint32_t LOCK; -} WWDT_TypeDef; - -/****************** Bit definition for LP16T_CON0 register ************************/ - -#define LP16T_CON0_PRELOAD_POS 22U -#define LP16T_CON0_PRELOAD_MSK BIT(LP16T_CON0_PRELOAD_POS) - -#define LP16T_CON0_WAVEPOL_POS 21U -#define LP16T_CON0_WAVEPOL_MSK BIT(LP16T_CON0_WAVEPOL_POS) - -#define LP16T_CON0_WAVE_POSS 19U -#define LP16T_CON0_WAVE_POSE 20U -#define LP16T_CON0_WAVE_MSK BITS(LP16T_CON0_WAVE_POSS,LP16T_CON0_WAVE_POSE) - -#define LP16T_CON0_TRIGEN_POSS 17U -#define LP16T_CON0_TRIGEN_POSE 18U -#define LP16T_CON0_TRIGEN_MSK BITS(LP16T_CON0_TRIGEN_POSS,LP16T_CON0_TRIGEN_POSE) - -#define LP16T_CON0_TRIGSEL_POSS 13U -#define LP16T_CON0_TRIGSEL_POSE 15U -#define LP16T_CON0_TRIGSEL_MSK BITS(LP16T_CON0_TRIGSEL_POSS,LP16T_CON0_TRIGSEL_POSE) - -#define LP16T_CON0_PRESC_POSS 9U -#define LP16T_CON0_PRESC_POSE 11U -#define LP16T_CON0_PRESC_MSK BITS(LP16T_CON0_PRESC_POSS,LP16T_CON0_PRESC_POSE) - -#define LP16T_CON0_TRGFLT_POSS 6U -#define LP16T_CON0_TRGFLT_POSE 7U -#define LP16T_CON0_TRGFLT_MSK BITS(LP16T_CON0_TRGFLT_POSS,LP16T_CON0_TRGFLT_POSE) - -#define LP16T_CON0_CKFLT_POSS 3U -#define LP16T_CON0_CKFLT_POSE 4U -#define LP16T_CON0_CKFLT_MSK BITS(LP16T_CON0_CKFLT_POSS,LP16T_CON0_CKFLT_POSE) - -#define LP16T_CON0_CKPOL_POS 1U -#define LP16T_CON0_CKPOL_MSK BIT(LP16T_CON0_CKPOL_POS) - -#define LP16T_CON0_CKSEL_POS 0U -#define LP16T_CON0_CKSEL_MSK BIT(LP16T_CON0_CKSEL_POS) - -/****************** Bit definition for LP16T_CON1 register ************************/ - -#define LP16T_CON1_CNTSTRT_POS 2U -#define LP16T_CON1_CNTSTRT_MSK BIT(LP16T_CON1_CNTSTRT_POS) - -#define LP16T_CON1_SNGSTRT_POS 1U -#define LP16T_CON1_SNGSTRT_MSK BIT(LP16T_CON1_SNGSTRT_POS) - -#define LP16T_CON1_ENABLE_POS 0U -#define LP16T_CON1_ENABLE_MSK BIT(LP16T_CON1_ENABLE_POS) - -/****************** Bit definition for LP16T_ARR register ************************/ - -#define LP16T_ARR_ARR_POSS 0U -#define LP16T_ARR_ARR_POSE 15U -#define LP16T_ARR_ARR_MSK BITS(LP16T_ARR_ARR_POSS,LP16T_ARR_ARR_POSE) - -/****************** Bit definition for LP16T_CNT register ************************/ - -#define LP16T_CNT_CNT_POSS 0U -#define LP16T_CNT_CNT_POSE 15U -#define LP16T_CNT_CNT_MSK BITS(LP16T_CNT_CNT_POSS,LP16T_CNT_CNT_POSE) - -/****************** Bit definition for LP16T_CMP register ************************/ - -#define LP16T_CMP_CMP_POSS 0U -#define LP16T_CMP_CMP_POSE 15U -#define LP16T_CMP_CMP_MSK BITS(LP16T_CMP_CMP_POSS,LP16T_CMP_CMP_POSE) - -/****************** Bit definition for LP16T_IER register ************************/ - -#define LP16T_IER_EXTTRIGIE_POS 2U -#define LP16T_IER_EXTTRIGIE_MSK BIT(LP16T_IER_EXTTRIGIE_POS) - -#define LP16T_IER_ARRMIE_POS 1U -#define LP16T_IER_ARRMIE_MSK BIT(LP16T_IER_ARRMIE_POS) - -#define LP16T_IER_CMPMIE_POS 0U -#define LP16T_IER_CMPMIE_MSK BIT(LP16T_IER_CMPMIE_POS) - -/****************** Bit definition for LP16T_ISR register ************************/ - -#define LP16T_ISR_EXTTRIG_POS 2U -#define LP16T_ISR_EXTTRIG_MSK BIT(LP16T_ISR_EXTTRIG_POS) - -#define LP16T_ISR_ARRM_POS 1U -#define LP16T_ISR_ARRM_MSK BIT(LP16T_ISR_ARRM_POS) - -#define LP16T_ISR_CMPM_POS 0U -#define LP16T_ISR_CMPM_MSK BIT(LP16T_ISR_CMPM_POS) - -/****************** Bit definition for LP16T_IFC register ************************/ - -#define LP16T_IFC_EXTTRIG_POS 2U -#define LP16T_IFC_EXTTRIG_MSK BIT(LP16T_IFC_EXTTRIG_POS) - -#define LP16T_IFC_ARRM_POS 1U -#define LP16T_IFC_ARRM_MSK BIT(LP16T_IFC_ARRM_POS) - -#define LP16T_IFC_CMPM_POS 0U -#define LP16T_IFC_CMPM_MSK BIT(LP16T_IFC_CMPM_POS) - -/****************** Bit definition for LP16T_UPDATE register ************************/ - -#define LP16T_UPDATE_UDIS_POS 0U -#define LP16T_UPDATE_UDIS_MSK BIT(LP16T_UPDATE_UDIS_POS) - -/****************** Bit definition for LP16T_SYNCSTAT register ************************/ - -#define LP16T_SYNCSTAT_CMPWBSY_POS 3U -#define LP16T_SYNCSTAT_CMPWBSY_MSK BIT(LP16T_SYNCSTAT_CMPWBSY_POS) - -#define LP16T_SYNCSTAT_ARRWBSY_POS 2U -#define LP16T_SYNCSTAT_ARRWBSY_MSK BIT(LP16T_SYNCSTAT_ARRWBSY_POS) - -#define LP16T_SYNCSTAT_CON1WBSY_POS 1U -#define LP16T_SYNCSTAT_CON1WBSY_MSK BIT(LP16T_SYNCSTAT_CON1WBSY_POS) - -typedef struct -{ - __IO uint32_t CON0; - __IO uint32_t CON1; - __IO uint32_t ARR; - __I uint32_t CNT; - __IO uint32_t CMP; - uint32_t RESERVED0 ; - __IO uint32_t IER; - __I uint32_t ISR; - __O uint32_t IFC; - uint32_t RESERVED1[3] ; - __IO uint32_t UPDATE; - __I uint32_t SYNCSTAT; -} LPTIM_TypeDef; - -/****************** Bit definition for DBGC_IDCODE register ************************/ - -#define DBGC_IDCODE_REV_ID_POSS 16U -#define DBGC_IDCODE_REV_ID_POSE 31U -#define DBGC_IDCODE_REV_ID_MSK BITS(DBGC_IDCODE_REV_ID_POSS,DBGC_IDCODE_REV_ID_POSE) - -#define DBGC_IDCODE_CORE_ID_POSS 12U -#define DBGC_IDCODE_CORE_ID_POSE 15U -#define DBGC_IDCODE_CORE_ID_MSK BITS(DBGC_IDCODE_CORE_ID_POSS,DBGC_IDCODE_CORE_ID_POSE) - -#define DBGC_IDCODE_DEV_ID_POSS 0U -#define DBGC_IDCODE_DEV_ID_POSE 11U -#define DBGC_IDCODE_DEV_ID_MSK BITS(DBGC_IDCODE_DEV_ID_POSS,DBGC_IDCODE_DEV_ID_POSE) - -/****************** Bit definition for DBGC_CR register ************************/ - -#define DBGC_CR_DBG_STANDBY_POS 3U -#define DBGC_CR_DBG_STANDBY_MSK BIT(DBGC_CR_DBG_STANDBY_POS) - -#define DBGC_CR_DBG_STOP2_POS 2U -#define DBGC_CR_DBG_STOP2_MSK BIT(DBGC_CR_DBG_STOP2_POS) - -#define DBGC_CR_DBG_STOP1_POS 1U -#define DBGC_CR_DBG_STOP1_MSK BIT(DBGC_CR_DBG_STOP1_POS) - -#define DBGC_CR_DBG_SLEEP_POS 0U -#define DBGC_CR_DBG_SLEEP_MSK BIT(DBGC_CR_DBG_SLEEP_POS) - -/****************** Bit definition for DBGC_APB1FZ register ************************/ - -#define DBGC_APB1FZ_CAN_STOP_POS 12U -#define DBGC_APB1FZ_CAN_STOP_MSK BIT(DBGC_APB1FZ_CAN_STOP_POS) - -#define DBGC_APB1FZ_I2C1_SMBUS_TO_POS 9U -#define DBGC_APB1FZ_I2C1_SMBUS_TO_MSK BIT(DBGC_APB1FZ_I2C1_SMBUS_TO_POS) - -#define DBGC_APB1FZ_I2C0_SMBUS_TO_POS 8U -#define DBGC_APB1FZ_I2C0_SMBUS_TO_MSK BIT(DBGC_APB1FZ_I2C0_SMBUS_TO_POS) - -#define DBGC_APB1FZ_TIM7_STOP_POS 7U -#define DBGC_APB1FZ_TIM7_STOP_MSK BIT(DBGC_APB1FZ_TIM7_STOP_POS) - -#define DBGC_APB1FZ_TIM6_STOP_POS 6U -#define DBGC_APB1FZ_TIM6_STOP_MSK BIT(DBGC_APB1FZ_TIM6_STOP_POS) - -#define DBGC_APB1FZ_TIM5_STOP_POS 5U -#define DBGC_APB1FZ_TIM5_STOP_MSK BIT(DBGC_APB1FZ_TIM5_STOP_POS) - -#define DBGC_APB1FZ_TIM4_STOP_POS 4U -#define DBGC_APB1FZ_TIM4_STOP_MSK BIT(DBGC_APB1FZ_TIM4_STOP_POS) - -#define DBGC_APB1FZ_TIM3_STOP_POS 3U -#define DBGC_APB1FZ_TIM3_STOP_MSK BIT(DBGC_APB1FZ_TIM3_STOP_POS) - -#define DBGC_APB1FZ_TIM2_STOP_POS 2U -#define DBGC_APB1FZ_TIM2_STOP_MSK BIT(DBGC_APB1FZ_TIM2_STOP_POS) - -#define DBGC_APB1FZ_TIM1_STOP_POS 1U -#define DBGC_APB1FZ_TIM1_STOP_MSK BIT(DBGC_APB1FZ_TIM1_STOP_POS) - -#define DBGC_APB1FZ_TIM0_STOP_POS 0U -#define DBGC_APB1FZ_TIM0_STOP_MSK BIT(DBGC_APB1FZ_TIM0_STOP_POS) - -/****************** Bit definition for DBGC_APB2FZ register ************************/ - -#define DBGC_APB2FZ_RTC_STOP_POS 10U -#define DBGC_APB2FZ_RTC_STOP_MSK BIT(DBGC_APB2FZ_RTC_STOP_POS) - -#define DBGC_APB2FZ_WWDT_STOP_POS 9U -#define DBGC_APB2FZ_WWDT_STOP_MSK BIT(DBGC_APB2FZ_WWDT_STOP_POS) - -#define DBGC_APB2FZ_IWDT_STOP_POS 8U -#define DBGC_APB2FZ_IWDT_STOP_MSK BIT(DBGC_APB2FZ_IWDT_STOP_POS) - -#define DBGC_APB2FZ_LPTIM0_STOP_POS 0U -#define DBGC_APB2FZ_LPTIM0_STOP_MSK BIT(DBGC_APB2FZ_LPTIM0_STOP_POS) - -typedef struct -{ - __I uint32_t IDCODE; - __IO uint32_t CR; - __IO uint32_t APB1FZ; - __IO uint32_t APB2FZ; -} DBGC_TypeDef; - - -/* Base addresses */ -#define SRAM_BASE (0x20000000UL) -#define APB1_BASE (0x40000000UL) -#define APB2_BASE (0x40040000UL) -#define AHB_BASE (0x40080000UL) - -/* APB1 peripherals Base Address */ -#define GP16C4T0_BASE (APB1_BASE + 0x0000) -#define BS16T0_BASE (APB1_BASE + 0x0400) -#define GP16C2T0_BASE (APB1_BASE + 0x0800) -#define GP16C2T1_BASE (APB1_BASE + 0x0C00) -#define BS16T1_BASE (APB1_BASE + 0x1000) -#define BS16T2_BASE (APB1_BASE + 0x1400) -#define GP16C4T1_BASE (APB1_BASE + 0x1800) -#define BS16T3_BASE (APB1_BASE + 0x1C00) -#define UART0_BASE (APB1_BASE + 0x4000) -#define UART1_BASE (APB1_BASE + 0x4400) -#define UART2_BASE (APB1_BASE + 0x4800) -#define UART3_BASE (APB1_BASE + 0x4C00) -#define USART0_BASE (APB1_BASE + 0x5000) -#define USART1_BASE (APB1_BASE + 0x5400) -#define SPI0_BASE (APB1_BASE + 0x6000) -#define SPI1_BASE (APB1_BASE + 0x6400) -#define I2C0_BASE (APB1_BASE + 0x8000) -#define I2C1_BASE (APB1_BASE + 0x8400) -#define DMA0_BASE (APB1_BASE + 0xC000) - -/* APB2 peripherals Base Address */ -#define LPTIM0_BASE (APB2_BASE + 0x0000) -#define LPUART0_BASE (APB2_BASE + 0x1000) -#define ADC0_BASE (APB2_BASE + 0x2000) -#define ACMP0_BASE (APB2_BASE + 0x3000) -#define ACMP1_BASE (APB2_BASE + 0x3400) -#define DAC0_BASE (APB2_BASE + 0x5000) -#define WWDT_BASE (APB2_BASE + 0x6000) -#define IWDT_BASE (APB2_BASE + 0x6400) -#define LCD_BASE (APB2_BASE + 0x7000) -#define BKPC_BASE (APB2_BASE + 0x8000) -#define RTC_BASE (APB2_BASE + 0x8400) -#define TSENSE_BASE (APB2_BASE + 0x8800) -#define DBGC_BASE (APB2_BASE + 0xA000) - -/* AHB peripherals Base Address */ -#define SYSCFG_BASE (AHB_BASE + 0x0000) -#define CMU_BASE (AHB_BASE + 0x0400) -#define RMU_BASE (AHB_BASE + 0x0800) -#define PMU_BASE (AHB_BASE + 0x0C00) -#define MSC_BASE (AHB_BASE + 0x1000) -#define GPIOA_BASE (AHB_BASE + 0x4000) -#define GPIOB_BASE (AHB_BASE + 0x4040) -#define GPIOC_BASE (AHB_BASE + 0x4080) -#define GPIOD_BASE (AHB_BASE + 0x40C0) -#define GPIOE_BASE (AHB_BASE + 0x4100) -#define GPIOF_BASE (AHB_BASE + 0x4140) -#define GPIOG_BASE (AHB_BASE + 0x4180) -#define GPIOH_BASE (AHB_BASE + 0x41C0) -#define EXTI_BASE (AHB_BASE + 0x4300) -#define CRC_BASE (AHB_BASE + 0x5000) -#define CALC_BASE (AHB_BASE + 0x5400) -#define CRYPT_BASE (AHB_BASE + 0x5800) -#define TRNG_BASE (AHB_BASE + 0x5C00) -#define PIS_BASE (AHB_BASE + 0x6000) - -/* APB1 peripherals */ -#define GP16C4T0 ((TIMER_TypeDef *)GP16C4T0_BASE) -#define BS16T0 ((TIMER_TypeDef *)BS16T0_BASE) -#define GP16C2T0 ((TIMER_TypeDef *)GP16C2T0_BASE) -#define GP16C2T1 ((TIMER_TypeDef *)GP16C2T1_BASE) -#define BS16T1 ((TIMER_TypeDef *)BS16T1_BASE) -#define BS16T2 ((TIMER_TypeDef *)BS16T2_BASE) -#define GP16C4T1 ((TIMER_TypeDef *)GP16C4T1_BASE) -#define BS16T3 ((TIMER_TypeDef *)BS16T3_BASE) -#define UART0 ((UART_TypeDef *)UART0_BASE) -#define UART1 ((UART_TypeDef *)UART1_BASE) -#define UART2 ((UART_TypeDef *)UART2_BASE) -#define UART3 ((UART_TypeDef *)UART3_BASE) -#define USART0 ((USART_TypeDef *)USART0_BASE) -#define USART1 ((USART_TypeDef *)USART1_BASE) -#define SPI0 ((SPI_TypeDef *)SPI0_BASE) -#define SPI1 ((SPI_TypeDef *)SPI1_BASE) -#define I2C0 ((I2C_TypeDef *)I2C0_BASE) -#define I2C1 ((I2C_TypeDef *)I2C1_BASE) -#define DMA0 ((DMA_TypeDef *)DMA0_BASE) - -/* APB2 peripherals */ -#define LPTIM0 ((LPTIM_TypeDef *)LPTIM0_BASE) -#define LPUART0 ((LPUART_TypeDef *)LPUART0_BASE) -#define ADC0 ((ADC_TypeDef *)ADC0_BASE) -#define ACMP0 ((ACMP_TypeDef *)ACMP0_BASE) -#define ACMP1 ((ACMP_TypeDef *)ACMP1_BASE) -#define WWDT ((WWDT_TypeDef *)WWDT_BASE) -#define IWDT ((IWDT_TypeDef *)IWDT_BASE) -#define LCD ((LCD_TypeDef *)LCD_BASE) -#define BKPC ((BKPC_TypeDef *)BKPC_BASE) -#define RTC ((RTC_TypeDef *)RTC_BASE) -#define TSENSE ((TSENSE_TypeDef *)TSENSE_BASE) -#define DBGC ((DBGC_TypeDef *)DBGC_BASE) - -/* AHB peripherals */ -#define SYSCFG ((SYSCFG_TypeDef *)SYSCFG_BASE) -#define CMU ((CMU_TypeDef *)CMU_BASE) -#define RMU ((RMU_TypeDef *)RMU_BASE) -#define PMU ((PMU_TypeDef *)PMU_BASE) -#define MSC ((MSC_TypeDef *)MSC_BASE) -#define GPIOA ((GPIO_TypeDef *)GPIOA_BASE) -#define GPIOB ((GPIO_TypeDef *)GPIOB_BASE) -#define GPIOC ((GPIO_TypeDef *)GPIOC_BASE) -#define GPIOD ((GPIO_TypeDef *)GPIOD_BASE) -#define GPIOE ((GPIO_TypeDef *)GPIOE_BASE) -#define GPIOF ((GPIO_TypeDef *)GPIOF_BASE) -#define GPIOG ((GPIO_TypeDef *)GPIOG_BASE) -#define GPIOH ((GPIO_TypeDef *)GPIOH_BASE) -#define EXTI ((EXTI_TypeDef *)EXTI_BASE) -#define CRC ((CRC_TypeDef *)CRC_BASE) -#define CALC ((CALC_TypeDef *)CALC_BASE) -#define CRYPT ((CRYPT_TypeDef *)CRYPT_BASE) -#define TRNG ((TRNG_TypeDef *)TRNG_BASE) -#define PIS ((PIS_TypeDef *)PIS_BASE) - -#endif diff --git a/bsp/essemi/es32f0334/libraries/CMSIS/Device/EastSoft/ES32F033x/Startup/iar/startup_es32f033x.s b/bsp/essemi/es32f0334/libraries/CMSIS/Device/EastSoft/ES32F033x/Startup/iar/startup_es32f033x.s deleted file mode 100644 index f341d9e5ac..0000000000 --- a/bsp/essemi/es32f0334/libraries/CMSIS/Device/EastSoft/ES32F033x/Startup/iar/startup_es32f033x.s +++ /dev/null @@ -1,266 +0,0 @@ -;******************************************************************************* -; file : startup_es32f033x.s -; description: es32f033x Device Startup File -; author : AE Team -; data : 10 Dec 2018 -; Copyright (C) Shanghai Eastsoft Microelectronics Co. Ltd. All rights reserved. -;******************************************************************************* - - MODULE ?cstartup - - ;; Forward declaration of sections. - SECTION CSTACK:DATA:NOROOT(3) - SECTION .intvec:CODE:NOROOT(2) - - EXTERN __iar_program_start - PUBLIC __vector_table - - DATA -__vector_table - DCD sfe(CSTACK) ;0, load top of stack - DCD Reset_Handler ;1, reset handler - DCD NMI_Handler ;2, nmi handler - DCD HardFault_Handler ;3, hard fault handler - DCD 0 ;4, MPU Fault Handler - DCD 0 ;5, Bus Fault Handler - DCD 0 ;6, Usage Fault Handler - DCD 0 ;7, Reserved - DCD 0 ;8, Reserved - DCD 0 ;9, Reserved - DCD 0 ;10, Reserved - DCD SVC_Handler ;11, svcall handler - DCD DebugMon_Handler ;12, Debug Monitor Handler - DCD 0 ;13, Reserved - DCD PendSV_Handler ;14, pendsv handler - DCD SysTick_Handler ;15, systick handler - DCD WWDG_IWDG_Handler ;16, irq0 WWDG_IWDG handler - DCD LVD_Handler ;17, irq1 LVD handler - DCD RTC_TEMP_Handler ;18, irq2 RTC handler - DCD CRYPT_TRNG_Handler ;19, irq3 CRYPT handler - DCD CMU_Handler ;20, irq4 CMU handler - DCD EXTI0_3_Handler ;21, irq5 EXTI0_3 handler - DCD EXTI4_7_Handler ;22, irq6 EXTI4_7 handler - DCD EXTI8_11_Handler ;23, irq7 EXTI8_11 handler - DCD EXTI12_15_Handler ;24, irq8 EXTI12_15 handler - DCD DMA_Handler ;25, irq9 DMA handler - DCD CAN0_Handler ;26, irq10 CAN0_CRYPT_TRNG handler - DCD LPTIM0_SPI2_Handler ;27, irq11 LPTIM0_SPI2 handler - DCD ADC_ACMP_Handler ;28, irq12 ADC_ACMP handler - DCD AD16C4T0_BRK_UP_TRIG_COM_Handler ;29, irq13 AD16C4T0_BRK_UP_TRIG_COM handler - DCD AD16C4T0_CC_Handler ;30, irq14 AD16C4T0_CC handler - DCD BS16T0_Handler ;31, irq15 BS16T0 handler - DCD 0 ;32, irq16 Reserved - DCD GP16C2T0_Handler ;33, irq17 GP16C2T0 handler - DCD GP16C2T1_Handler ;34, irq18 GP16C2T1 handler - DCD BS16T1_UART2_Handler ;35, irq19 BS16T1_UART2 handler - DCD BS16T2_UART3_Handler ;36, irq20 BS16T2_UART3 handler - DCD GP16C4T0_LCD_Handler ;37, irq21 GP16C4T0_LCD handler - DCD BS16T3_DAC0_Handler ;38, irq22 BS16T3_DAC0 handler - DCD I2C0_Handler ;39, irq23 I2C0 handler - DCD I2C1_Handler ;40, irq24 I2C1 handler - DCD SPI0_Handler ;41, irq25 SPI0 handler - DCD SPI1_Handler ;42, irq26 SPI1 handler - DCD UART0_Handler ;43, irq27 UART0 handler - DCD UART1_Handler ;44, irq28 UART1 handler - DCD USART0_Handler ;45, irq29 USART0 handler - DCD USART1_Handler ;46, irq30 USART1 handler - DCD LPUART0_Handler ;47, irq31 LPUART0 handler - -;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; -;; -;; Default interrupt handlers. -;; - THUMB - - PUBWEAK Reset_Handler - SECTION .text:CODE:NOROOT:REORDER(2) -Reset_Handler - LDR R0, =__iar_program_start - BX R0 - - PUBWEAK NMI_Handler - SECTION .text:CODE:NOROOT:REORDER(1) -NMI_Handler - B NMI_Handler - - PUBWEAK HardFault_Handler - SECTION .text:CODE:NOROOT:REORDER(1) -HardFault_Handler - B HardFault_Handler - - PUBWEAK SVC_Handler - SECTION .text:CODE:NOROOT:REORDER(1) -SVC_Handler - B SVC_Handler - - PUBWEAK DebugMon_Handler - SECTION .text:CODE:NOROOT:REORDER(1) -DebugMon_Handler - B DebugMon_Handler - - PUBWEAK PendSV_Handler - SECTION .text:CODE:NOROOT:REORDER(1) -PendSV_Handler - B PendSV_Handler - - PUBWEAK SysTick_Handler - SECTION .text:CODE:NOROOT:REORDER(1) -SysTick_Handler - B SysTick_Handler - - PUBWEAK WWDG_IWDG_Handler - SECTION .text:CODE:NOROOT:REORDER(1) -WWDG_IWDG_Handler - B WWDG_IWDG_Handler - - PUBWEAK LVD_Handler - SECTION .text:CODE:NOROOT:REORDER(1) -LVD_Handler - B LVD_Handler - - PUBWEAK RTC_TEMP_Handler - SECTION .text:CODE:NOROOT:REORDER(1) -RTC_TEMP_Handler - B RTC_TEMP_Handler - - PUBWEAK CRYPT_TRNG_Handler - SECTION .text:CODE:NOROOT:REORDER(1) -CRYPT_TRNG_Handler - B CRYPT_TRNG_Handler - - PUBWEAK CMU_Handler - SECTION .text:CODE:NOROOT:REORDER(1) -CMU_Handler - B CMU_Handler - - PUBWEAK EXTI0_3_Handler - SECTION .text:CODE:NOROOT:REORDER(1) -EXTI0_3_Handler - B EXTI0_3_Handler - - PUBWEAK EXTI4_7_Handler - SECTION .text:CODE:NOROOT:REORDER(1) -EXTI4_7_Handler - B EXTI4_7_Handler - - PUBWEAK EXTI8_11_Handler - SECTION .text:CODE:NOROOT:REORDER(1) -EXTI8_11_Handler - B EXTI8_11_Handler - - PUBWEAK EXTI12_15_Handler - SECTION .text:CODE:NOROOT:REORDER(1) -EXTI12_15_Handler - B EXTI12_15_Handler - - PUBWEAK DMA_Handler - SECTION .text:CODE:NOROOT:REORDER(1) -DMA_Handler - B DMA_Handler - - PUBWEAK CAN0_Handler - SECTION .text:CODE:NOROOT:REORDER(1) -CAN0_Handler - B CAN0_Handler - - PUBWEAK LPTIM0_SPI2_Handler - SECTION .text:CODE:NOROOT:REORDER(1) -LPTIM0_SPI2_Handler - B LPTIM0_SPI2_Handler - - PUBWEAK ADC_ACMP_Handler - SECTION .text:CODE:NOROOT:REORDER(1) -ADC_ACMP_Handler - B ADC_ACMP_Handler - - PUBWEAK AD16C4T0_BRK_UP_TRIG_COM_Handler - SECTION .text:CODE:NOROOT:REORDER(1) -AD16C4T0_BRK_UP_TRIG_COM_Handler - B AD16C4T0_BRK_UP_TRIG_COM_Handler - - PUBWEAK AD16C4T0_CC_Handler - SECTION .text:CODE:NOROOT:REORDER(1) -AD16C4T0_CC_Handler - B AD16C4T0_CC_Handler - - PUBWEAK BS16T0_Handler - SECTION .text:CODE:NOROOT:REORDER(1) -BS16T0_Handler - B BS16T0_Handler - - PUBWEAK GP16C2T0_Handler - SECTION .text:CODE:NOROOT:REORDER(1) -GP16C2T0_Handler - B GP16C2T0_Handler - - PUBWEAK GP16C2T1_Handler - SECTION .text:CODE:NOROOT:REORDER(1) -GP16C2T1_Handler - B GP16C2T1_Handler - - PUBWEAK BS16T1_UART2_Handler - SECTION .text:CODE:NOROOT:REORDER(1) -BS16T1_UART2_Handler - B BS16T1_UART2_Handler - - PUBWEAK BS16T2_UART3_Handler - SECTION .text:CODE:NOROOT:REORDER(1) -BS16T2_UART3_Handler - B BS16T2_UART3_Handler - - PUBWEAK GP16C4T0_LCD_Handler - SECTION .text:CODE:NOROOT:REORDER(1) -GP16C4T0_LCD_Handler - B GP16C4T0_LCD_Handler - - PUBWEAK BS16T3_DAC0_Handler - SECTION .text:CODE:NOROOT:REORDER(1) -BS16T3_DAC0_Handler - B BS16T3_DAC0_Handler - - PUBWEAK I2C0_Handler - SECTION .text:CODE:NOROOT:REORDER(1) -I2C0_Handler - B I2C0_Handler - - PUBWEAK I2C1_Handler - SECTION .text:CODE:NOROOT:REORDER(1) -I2C1_Handler - B I2C1_Handler - - PUBWEAK SPI0_Handler - SECTION .text:CODE:NOROOT:REORDER(1) -SPI0_Handler - B SPI0_Handler - - PUBWEAK SPI1_Handler - SECTION .text:CODE:NOROOT:REORDER(1) -SPI1_Handler - B SPI1_Handler - - PUBWEAK UART0_Handler - SECTION .text:CODE:NOROOT:REORDER(1) -UART0_Handler - B UART0_Handler - - PUBWEAK UART1_Handler - SECTION .text:CODE:NOROOT:REORDER(1) -UART1_Handler - B UART1_Handler - - PUBWEAK USART0_Handler - SECTION .text:CODE:NOROOT:REORDER(1) -USART0_Handler - B USART0_Handler - - PUBWEAK USART1_Handler - SECTION .text:CODE:NOROOT:REORDER(1) -USART1_Handler - B USART1_Handler - - PUBWEAK LPUART0_Handler - SECTION .text:CODE:NOROOT:REORDER(1) -LPUART0_Handler - B LPUART0_Handler - - END diff --git a/bsp/essemi/es32f0334/libraries/CMSIS/Device/EastSoft/ES32F033x/Startup/keil/startup_es32f033x.s b/bsp/essemi/es32f0334/libraries/CMSIS/Device/EastSoft/ES32F033x/Startup/keil/startup_es32f033x.s deleted file mode 100644 index 11b29917a3..0000000000 --- a/bsp/essemi/es32f0334/libraries/CMSIS/Device/EastSoft/ES32F033x/Startup/keil/startup_es32f033x.s +++ /dev/null @@ -1,335 +0,0 @@ -;******************************************************************************* -; file : startup_es32f033x.s -; description: es32f033x Device Startup File -; author : AE Team -; data : 29 Aug 2017 -; Copyright (C) Shanghai Eastsoft Microelectronics Co. Ltd. All rights reserved. -;******************************************************************************* - -;Stack Configuration------------------------------------------------------------ -Stack_Size EQU 0x00000400 - AREA STACK, NOINIT, READWRITE, ALIGN=3 -Stack_Mem SPACE Stack_Size -__initial_sp -;------------------------------------------------------------------------------- - -;Heap Configuration------------------------------------------------------------- -Heap_Size EQU 0x00000000 - AREA HEAP, NOINIT, READWRITE, ALIGN=3 -__heap_base -Heap_Mem SPACE Heap_Size -__heap_limit -;------------------------------------------------------------------------------- - PRESERVE8 - THUMB - -; Vector Table Mapped to Address 0 at Reset------------------------------------- - AREA RESET, DATA, READONLY - EXPORT __Vectors - -__Vectors DCD __initial_sp ;0, load top of stack - DCD Reset_Handler ;1, reset handler - DCD NMI_Handler ;2, nmi handler - DCD HardFault_Handler ;3, hard fault handler - DCD 0 ;4, MPU Fault Handler - DCD 0 ;5, Bus Fault Handler - DCD 0 ;6, Usage Fault Handler - DCD 0 ;7, Reserved - DCD 0 ;8, Reserved - DCD 0 ;9, Reserved - DCD 0 ;10, Reserved - DCD SVC_Handler ;11, svcall handler - DCD DebugMon_Handler ;12, Debug Monitor Handler - DCD 0 ;13, Reserved - DCD PendSV_Handler ;14, pendsv handler - DCD SysTick_Handler ;15, systick handler - DCD WWDG_IWDG_Handler ;16, irq0 WWDG_IWDG handler - DCD LVD_Handler ;17, irq1 LVD handler - DCD RTC_TEMP_Handler ;18, irq2 RTC handler - DCD CRYPT_TRNG_Handler ;19, irq3 CRYPT handler - DCD CMU_Handler ;20, irq4 CMU handler - DCD EXTI0_3_Handler ;21, irq5 EXTI0_3 handler - DCD EXTI4_7_Handler ;22, irq6 EXTI4_7 handler - DCD EXTI8_11_Handler ;23, irq7 EXTI8_11 handler - DCD EXTI12_15_Handler ;24, irq8 EXTI12_15 handler - DCD DMA_Handler ;25, irq9 DMA handler - DCD CAN0_Handler ;26, irq10 CAN0_CRYPT_TRNG handler - DCD LPTIM0_SPI2_Handler ;27, irq11 LPTIM0_SPI2 handler - DCD ADC_ACMP_Handler ;28, irq12 ADC_ACMP handler - DCD AD16C4T0_BRK_UP_TRIG_COM_Handler ;29, irq13 AD16C4T0_BRK_UP_TRIG_COM handler - DCD AD16C4T0_CC_Handler ;30, irq14 AD16C4T0_CC handler - DCD BS16T0_Handler ;31, irq15 BS16T0 handler - DCD 0 ;32, irq16 Reserved - DCD GP16C2T0_Handler ;33, irq17 GP16C2T0 handler - DCD GP16C2T1_Handler ;34, irq18 GP16C2T1 handler - DCD BS16T1_UART2_Handler ;35, irq19 BS16T1_UART2 handler - DCD BS16T2_UART3_Handler ;36, irq20 BS16T2_UART3 handler - DCD GP16C4T0_LCD_Handler ;37, irq21 GP16C4T0_LCD handler - DCD BS16T3_DAC0_Handler ;38, irq22 BS16T3_DAC0 handler - DCD I2C0_Handler ;39, irq23 I2C0 handler - DCD I2C1_Handler ;40, irq24 I2C1 handler - DCD SPI0_Handler ;41, irq25 SPI0 handler - DCD SPI1_Handler ;42, irq26 SPI1 handler - DCD UART0_Handler ;43, irq27 UART0 handler - DCD UART1_Handler ;44, irq28 UART1 handler - DCD USART0_Handler ;45, irq29 USART0 handler - DCD USART1_Handler ;46, irq30 USART1 handler - DCD LPUART0_Handler ;47, irq31 LPUART0 handler - -;------------------------------------------------------------------------------- - AREA INT, CODE, READONLY ;code begin - -;Reset Handler---------------------------------------------- -Reset_Handler PROC - EXPORT Reset_Handler [WEAK] - IMPORT __main - LDR R0, =__main - BX R0 - NOP - ALIGN - ENDP - -;system int------------------------------------------------- -NMI_Handler PROC ;int 2 - EXPORT NMI_Handler [WEAK] - B . - ENDP - -HardFault_Handler \ - PROC ;int3 - EXPORT HardFault_Handler [WEAK] - B . - ENDP - -SVC_Handler \ - PROC ;int11 - EXPORT SVC_Handler [WEAK] - B . - ENDP - -DebugMon_Handler \ - PROC ;int12 - EXPORT DebugMon_Handler [WEAK] - B . - ENDP - -PendSV_Handler PROC ;int14 - EXPORT PendSV_Handler [WEAK] - B . - ENDP - -SysTick_Handler \ - PROC ;int15 - EXPORT SysTick_Handler [WEAK] - B . - ENDP - -;peripheral module int ----------------------------------------------- -WWDG_IWDG_Handler \ - PROC ;int16 - EXPORT WWDG_IWDG_Handler [WEAK] - B . - ENDP - -LVD_Handler \ - PROC ;int17 - EXPORT LVD_Handler [WEAK] - B . - ENDP - -RTC_TEMP_Handler \ - PROC ;int18 - EXPORT RTC_TEMP_Handler [WEAK] - B . - ENDP - -CRYPT_TRNG_Handler \ - PROC ;int19 - EXPORT CRYPT_TRNG_Handler [WEAK] - B . - ENDP - -CMU_Handler \ - PROC ;int20 - EXPORT CMU_Handler [WEAK] - B . - ENDP - -EXTI0_3_Handler \ - PROC ;int21 - EXPORT EXTI0_3_Handler [WEAK] - B . - ENDP - -EXTI4_7_Handler \ - PROC ;int22 - EXPORT EXTI4_7_Handler [WEAK] - B . - ENDP - -EXTI8_11_Handler \ - PROC ;int23 - EXPORT EXTI8_11_Handler [WEAK] - B . - ENDP - -EXTI12_15_Handler \ - PROC ;int24 - EXPORT EXTI12_15_Handler [WEAK] - B . - ENDP - -DMA_Handler \ - PROC ;int25 - EXPORT DMA_Handler [WEAK] - B . - ENDP - -CAN0_Handler \ - PROC ;int26 - EXPORT CAN0_Handler [WEAK] - B . - ENDP - -LPTIM0_SPI2_Handler \ - PROC ;int27 - EXPORT LPTIM0_SPI2_Handler [WEAK] - B . - ENDP - -ADC_ACMP_Handler \ - PROC ;int28 - EXPORT ADC_ACMP_Handler [WEAK] - B . - ENDP - -AD16C4T0_BRK_UP_TRIG_COM_Handler \ - PROC ;int29 - EXPORT AD16C4T0_BRK_UP_TRIG_COM_Handler [WEAK] - B . - ENDP - -AD16C4T0_CC_Handler \ - PROC ;int30 - EXPORT AD16C4T0_CC_Handler [WEAK] - B . - ENDP - -BS16T0_Handler \ - PROC ;int31 - EXPORT BS16T0_Handler [WEAK] - B . - ENDP - -GP16C2T0_Handler PROC ;int33 - EXPORT GP16C2T0_Handler [WEAK] - B . - ENDP - -GP16C2T1_Handler PROC ;int34 - EXPORT GP16C2T1_Handler [WEAK] - B . - ENDP - -BS16T1_UART2_Handler \ - PROC ;int35 - EXPORT BS16T1_UART2_Handler [WEAK] - B . - ENDP - -BS16T2_UART3_Handler \ - PROC ;int36 - EXPORT BS16T2_UART3_Handler [WEAK] - B . - ENDP - -GP16C4T0_LCD_Handler \ - PROC ;int37 - EXPORT GP16C4T0_LCD_Handler [WEAK] - B . - ENDP - -BS16T3_DAC0_Handler \ - PROC ;int38 - EXPORT BS16T3_DAC0_Handler [WEAK] - B . - ENDP - -I2C0_Handler \ - PROC ;int39 - EXPORT I2C0_Handler [WEAK] - B . - ENDP - -I2C1_Handler \ - PROC ;int40 - EXPORT I2C1_Handler [WEAK] - B . - ENDP - -SPI0_Handler \ - PROC ;int41 - EXPORT SPI0_Handler [WEAK] - B . - ENDP - -SPI1_Handler \ - PROC ;int42 - EXPORT SPI1_Handler [WEAK] - B . - ENDP - -UART0_Handler \ - PROC ;int43 - EXPORT UART0_Handler [WEAK] - B . - ENDP - -UART1_Handler \ - PROC ;int44 - EXPORT UART1_Handler [WEAK] - B . - ENDP - -USART0_Handler \ - PROC ;int45 - EXPORT USART0_Handler [WEAK] - B . - ENDP - -USART1_Handler \ - PROC ;int46 - EXPORT USART1_Handler [WEAK] - B . - ENDP - -LPUART0_Handler \ - PROC ;int47 - EXPORT LPUART0_Handler [WEAK] - B . - ENDP - -; User Initial Stack & Heap----------------------------------------------------- - ALIGN - IF :DEF:__MICROLIB - - EXPORT __initial_sp - EXPORT __heap_base - EXPORT __heap_limit - - ELSE - - IMPORT __use_two_region_memory - EXPORT __user_initial_stackheap -__user_initial_stackheap - LDR R0, = Heap_Mem - LDR R1, = (Stack_Mem + Stack_Size) - LDR R2, = (Heap_Mem + Heap_Size) - LDR R3, = Stack_Mem - BX LR - - ALIGN - - ENDIF - - END diff --git a/bsp/essemi/es32f0334/libraries/CMSIS/Device/EastSoft/ES32F033x/System/system_es32f033x.c b/bsp/essemi/es32f0334/libraries/CMSIS/Device/EastSoft/ES32F033x/System/system_es32f033x.c deleted file mode 100644 index 25df7e5a37..0000000000 --- a/bsp/essemi/es32f0334/libraries/CMSIS/Device/EastSoft/ES32F033x/System/system_es32f033x.c +++ /dev/null @@ -1,28 +0,0 @@ -/** - ********************************************************************************* - * - * @file system_es32f033x.c - * @brief CMSIS Cortex-M0 Device Peripheral Access Layer - * - * @version V1.0 - * @date 6 Dec 2018 - * @author AE Team - * @note - * - * Copyright (C) Shanghai Eastsoft Microelectronics Co. Ltd. All rights reserved. - * - ********************************************************************************* - */ - -#include "utils.h" - - -/** - * @brief Configuring system clock before startup. - * @note This function must be used after reset. - * @retval None - */ -void system_init (void) -{ - /* do nothing */ -} \ No newline at end of file diff --git a/bsp/essemi/es32f0334/libraries/CMSIS/Include/arm_common_tables.h b/bsp/essemi/es32f0334/libraries/CMSIS/Include/arm_common_tables.h deleted file mode 100644 index 8742a56991..0000000000 --- a/bsp/essemi/es32f0334/libraries/CMSIS/Include/arm_common_tables.h +++ /dev/null @@ -1,136 +0,0 @@ -/* ---------------------------------------------------------------------- -* Copyright (C) 2010-2014 ARM Limited. All rights reserved. -* -* $Date: 19. October 2015 -* $Revision: V.1.4.5 a -* -* Project: CMSIS DSP Library -* Title: arm_common_tables.h -* -* Description: This file has extern declaration for common tables like Bitreverse, reciprocal etc which are used across different functions -* -* Target Processor: Cortex-M4/Cortex-M3 -* -* Redistribution and use in source and binary forms, with or without -* modification, are permitted provided that the following conditions -* are met: -* - Redistributions of source code must retain the above copyright -* notice, this list of conditions and the following disclaimer. -* - Redistributions in binary form must reproduce the above copyright -* notice, this list of conditions and the following disclaimer in -* the documentation and/or other materials provided with the -* distribution. -* - Neither the name of ARM LIMITED nor the names of its contributors -* may be used to endorse or promote products derived from this -* software without specific prior written permission. -* -* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS -* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT -* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS -* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE -* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, -* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, -* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; -* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER -* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT -* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN -* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE -* POSSIBILITY OF SUCH DAMAGE. -* -------------------------------------------------------------------- */ - -#ifndef _ARM_COMMON_TABLES_H -#define _ARM_COMMON_TABLES_H - -#include "arm_math.h" - -extern const uint16_t armBitRevTable[1024]; -extern const q15_t armRecipTableQ15[64]; -extern const q31_t armRecipTableQ31[64]; -/* extern const q31_t realCoefAQ31[1024]; */ -/* extern const q31_t realCoefBQ31[1024]; */ -extern const float32_t twiddleCoef_16[32]; -extern const float32_t twiddleCoef_32[64]; -extern const float32_t twiddleCoef_64[128]; -extern const float32_t twiddleCoef_128[256]; -extern const float32_t twiddleCoef_256[512]; -extern const float32_t twiddleCoef_512[1024]; -extern const float32_t twiddleCoef_1024[2048]; -extern const float32_t twiddleCoef_2048[4096]; -extern const float32_t twiddleCoef_4096[8192]; -#define twiddleCoef twiddleCoef_4096 -extern const q31_t twiddleCoef_16_q31[24]; -extern const q31_t twiddleCoef_32_q31[48]; -extern const q31_t twiddleCoef_64_q31[96]; -extern const q31_t twiddleCoef_128_q31[192]; -extern const q31_t twiddleCoef_256_q31[384]; -extern const q31_t twiddleCoef_512_q31[768]; -extern const q31_t twiddleCoef_1024_q31[1536]; -extern const q31_t twiddleCoef_2048_q31[3072]; -extern const q31_t twiddleCoef_4096_q31[6144]; -extern const q15_t twiddleCoef_16_q15[24]; -extern const q15_t twiddleCoef_32_q15[48]; -extern const q15_t twiddleCoef_64_q15[96]; -extern const q15_t twiddleCoef_128_q15[192]; -extern const q15_t twiddleCoef_256_q15[384]; -extern const q15_t twiddleCoef_512_q15[768]; -extern const q15_t twiddleCoef_1024_q15[1536]; -extern const q15_t twiddleCoef_2048_q15[3072]; -extern const q15_t twiddleCoef_4096_q15[6144]; -extern const float32_t twiddleCoef_rfft_32[32]; -extern const float32_t twiddleCoef_rfft_64[64]; -extern const float32_t twiddleCoef_rfft_128[128]; -extern const float32_t twiddleCoef_rfft_256[256]; -extern const float32_t twiddleCoef_rfft_512[512]; -extern const float32_t twiddleCoef_rfft_1024[1024]; -extern const float32_t twiddleCoef_rfft_2048[2048]; -extern const float32_t twiddleCoef_rfft_4096[4096]; - - -/* floating-point bit reversal tables */ -#define ARMBITREVINDEXTABLE__16_TABLE_LENGTH ((uint16_t)20 ) -#define ARMBITREVINDEXTABLE__32_TABLE_LENGTH ((uint16_t)48 ) -#define ARMBITREVINDEXTABLE__64_TABLE_LENGTH ((uint16_t)56 ) -#define ARMBITREVINDEXTABLE_128_TABLE_LENGTH ((uint16_t)208 ) -#define ARMBITREVINDEXTABLE_256_TABLE_LENGTH ((uint16_t)440 ) -#define ARMBITREVINDEXTABLE_512_TABLE_LENGTH ((uint16_t)448 ) -#define ARMBITREVINDEXTABLE1024_TABLE_LENGTH ((uint16_t)1800) -#define ARMBITREVINDEXTABLE2048_TABLE_LENGTH ((uint16_t)3808) -#define ARMBITREVINDEXTABLE4096_TABLE_LENGTH ((uint16_t)4032) - -extern const uint16_t armBitRevIndexTable16[ARMBITREVINDEXTABLE__16_TABLE_LENGTH]; -extern const uint16_t armBitRevIndexTable32[ARMBITREVINDEXTABLE__32_TABLE_LENGTH]; -extern const uint16_t armBitRevIndexTable64[ARMBITREVINDEXTABLE__64_TABLE_LENGTH]; -extern const uint16_t armBitRevIndexTable128[ARMBITREVINDEXTABLE_128_TABLE_LENGTH]; -extern const uint16_t armBitRevIndexTable256[ARMBITREVINDEXTABLE_256_TABLE_LENGTH]; -extern const uint16_t armBitRevIndexTable512[ARMBITREVINDEXTABLE_512_TABLE_LENGTH]; -extern const uint16_t armBitRevIndexTable1024[ARMBITREVINDEXTABLE1024_TABLE_LENGTH]; -extern const uint16_t armBitRevIndexTable2048[ARMBITREVINDEXTABLE2048_TABLE_LENGTH]; -extern const uint16_t armBitRevIndexTable4096[ARMBITREVINDEXTABLE4096_TABLE_LENGTH]; - -/* fixed-point bit reversal tables */ -#define ARMBITREVINDEXTABLE_FIXED___16_TABLE_LENGTH ((uint16_t)12 ) -#define ARMBITREVINDEXTABLE_FIXED___32_TABLE_LENGTH ((uint16_t)24 ) -#define ARMBITREVINDEXTABLE_FIXED___64_TABLE_LENGTH ((uint16_t)56 ) -#define ARMBITREVINDEXTABLE_FIXED__128_TABLE_LENGTH ((uint16_t)112 ) -#define ARMBITREVINDEXTABLE_FIXED__256_TABLE_LENGTH ((uint16_t)240 ) -#define ARMBITREVINDEXTABLE_FIXED__512_TABLE_LENGTH ((uint16_t)480 ) -#define ARMBITREVINDEXTABLE_FIXED_1024_TABLE_LENGTH ((uint16_t)992 ) -#define ARMBITREVINDEXTABLE_FIXED_2048_TABLE_LENGTH ((uint16_t)1984) -#define ARMBITREVINDEXTABLE_FIXED_4096_TABLE_LENGTH ((uint16_t)4032) - -extern const uint16_t armBitRevIndexTable_fixed_16[ARMBITREVINDEXTABLE_FIXED___16_TABLE_LENGTH]; -extern const uint16_t armBitRevIndexTable_fixed_32[ARMBITREVINDEXTABLE_FIXED___32_TABLE_LENGTH]; -extern const uint16_t armBitRevIndexTable_fixed_64[ARMBITREVINDEXTABLE_FIXED___64_TABLE_LENGTH]; -extern const uint16_t armBitRevIndexTable_fixed_128[ARMBITREVINDEXTABLE_FIXED__128_TABLE_LENGTH]; -extern const uint16_t armBitRevIndexTable_fixed_256[ARMBITREVINDEXTABLE_FIXED__256_TABLE_LENGTH]; -extern const uint16_t armBitRevIndexTable_fixed_512[ARMBITREVINDEXTABLE_FIXED__512_TABLE_LENGTH]; -extern const uint16_t armBitRevIndexTable_fixed_1024[ARMBITREVINDEXTABLE_FIXED_1024_TABLE_LENGTH]; -extern const uint16_t armBitRevIndexTable_fixed_2048[ARMBITREVINDEXTABLE_FIXED_2048_TABLE_LENGTH]; -extern const uint16_t armBitRevIndexTable_fixed_4096[ARMBITREVINDEXTABLE_FIXED_4096_TABLE_LENGTH]; - -/* Tables for Fast Math Sine and Cosine */ -extern const float32_t sinTable_f32[FAST_MATH_TABLE_SIZE + 1]; -extern const q31_t sinTable_q31[FAST_MATH_TABLE_SIZE + 1]; -extern const q15_t sinTable_q15[FAST_MATH_TABLE_SIZE + 1]; - -#endif /* ARM_COMMON_TABLES_H */ diff --git a/bsp/essemi/es32f0334/libraries/CMSIS/Include/arm_const_structs.h b/bsp/essemi/es32f0334/libraries/CMSIS/Include/arm_const_structs.h deleted file mode 100644 index 726d06eb69..0000000000 --- a/bsp/essemi/es32f0334/libraries/CMSIS/Include/arm_const_structs.h +++ /dev/null @@ -1,79 +0,0 @@ -/* ---------------------------------------------------------------------- -* Copyright (C) 2010-2014 ARM Limited. All rights reserved. -* -* $Date: 19. March 2015 -* $Revision: V.1.4.5 -* -* Project: CMSIS DSP Library -* Title: arm_const_structs.h -* -* Description: This file has constant structs that are initialized for -* user convenience. For example, some can be given as -* arguments to the arm_cfft_f32() function. -* -* Target Processor: Cortex-M4/Cortex-M3 -* -* Redistribution and use in source and binary forms, with or without -* modification, are permitted provided that the following conditions -* are met: -* - Redistributions of source code must retain the above copyright -* notice, this list of conditions and the following disclaimer. -* - Redistributions in binary form must reproduce the above copyright -* notice, this list of conditions and the following disclaimer in -* the documentation and/or other materials provided with the -* distribution. -* - Neither the name of ARM LIMITED nor the names of its contributors -* may be used to endorse or promote products derived from this -* software without specific prior written permission. -* -* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS -* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT -* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS -* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE -* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, -* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, -* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; -* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER -* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT -* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN -* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE -* POSSIBILITY OF SUCH DAMAGE. -* -------------------------------------------------------------------- */ - -#ifndef _ARM_CONST_STRUCTS_H -#define _ARM_CONST_STRUCTS_H - -#include "arm_math.h" -#include "arm_common_tables.h" - - extern const arm_cfft_instance_f32 arm_cfft_sR_f32_len16; - extern const arm_cfft_instance_f32 arm_cfft_sR_f32_len32; - extern const arm_cfft_instance_f32 arm_cfft_sR_f32_len64; - extern const arm_cfft_instance_f32 arm_cfft_sR_f32_len128; - extern const arm_cfft_instance_f32 arm_cfft_sR_f32_len256; - extern const arm_cfft_instance_f32 arm_cfft_sR_f32_len512; - extern const arm_cfft_instance_f32 arm_cfft_sR_f32_len1024; - extern const arm_cfft_instance_f32 arm_cfft_sR_f32_len2048; - extern const arm_cfft_instance_f32 arm_cfft_sR_f32_len4096; - - extern const arm_cfft_instance_q31 arm_cfft_sR_q31_len16; - extern const arm_cfft_instance_q31 arm_cfft_sR_q31_len32; - extern const arm_cfft_instance_q31 arm_cfft_sR_q31_len64; - extern const arm_cfft_instance_q31 arm_cfft_sR_q31_len128; - extern const arm_cfft_instance_q31 arm_cfft_sR_q31_len256; - extern const arm_cfft_instance_q31 arm_cfft_sR_q31_len512; - extern const arm_cfft_instance_q31 arm_cfft_sR_q31_len1024; - extern const arm_cfft_instance_q31 arm_cfft_sR_q31_len2048; - extern const arm_cfft_instance_q31 arm_cfft_sR_q31_len4096; - - extern const arm_cfft_instance_q15 arm_cfft_sR_q15_len16; - extern const arm_cfft_instance_q15 arm_cfft_sR_q15_len32; - extern const arm_cfft_instance_q15 arm_cfft_sR_q15_len64; - extern const arm_cfft_instance_q15 arm_cfft_sR_q15_len128; - extern const arm_cfft_instance_q15 arm_cfft_sR_q15_len256; - extern const arm_cfft_instance_q15 arm_cfft_sR_q15_len512; - extern const arm_cfft_instance_q15 arm_cfft_sR_q15_len1024; - extern const arm_cfft_instance_q15 arm_cfft_sR_q15_len2048; - extern const arm_cfft_instance_q15 arm_cfft_sR_q15_len4096; - -#endif diff --git a/bsp/essemi/es32f0334/libraries/CMSIS/Include/arm_math.h b/bsp/essemi/es32f0334/libraries/CMSIS/Include/arm_math.h deleted file mode 100644 index d33f8a9b3b..0000000000 --- a/bsp/essemi/es32f0334/libraries/CMSIS/Include/arm_math.h +++ /dev/null @@ -1,7154 +0,0 @@ -/* ---------------------------------------------------------------------- -* Copyright (C) 2010-2015 ARM Limited. All rights reserved. -* -* $Date: 20. October 2015 -* $Revision: V1.4.5 b -* -* Project: CMSIS DSP Library -* Title: arm_math.h -* -* Description: Public header file for CMSIS DSP Library -* -* Target Processor: Cortex-M7/Cortex-M4/Cortex-M3/Cortex-M0 -* -* Redistribution and use in source and binary forms, with or without -* modification, are permitted provided that the following conditions -* are met: -* - Redistributions of source code must retain the above copyright -* notice, this list of conditions and the following disclaimer. -* - Redistributions in binary form must reproduce the above copyright -* notice, this list of conditions and the following disclaimer in -* the documentation and/or other materials provided with the -* distribution. -* - Neither the name of ARM LIMITED nor the names of its contributors -* may be used to endorse or promote products derived from this -* software without specific prior written permission. -* -* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS -* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT -* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS -* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE -* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, -* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, -* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; -* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER -* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT -* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN -* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE -* POSSIBILITY OF SUCH DAMAGE. - * -------------------------------------------------------------------- */ - -/** - \mainpage CMSIS DSP Software Library - * - * Introduction - * ------------ - * - * This user manual describes the CMSIS DSP software library, - * a suite of common signal processing functions for use on Cortex-M processor based devices. - * - * The library is divided into a number of functions each covering a specific category: - * - Basic math functions - * - Fast math functions - * - Complex math functions - * - Filters - * - Matrix functions - * - Transforms - * - Motor control functions - * - Statistical functions - * - Support functions - * - Interpolation functions - * - * The library has separate functions for operating on 8-bit integers, 16-bit integers, - * 32-bit integer and 32-bit floating-point values. - * - * Using the Library - * ------------ - * - * The library installer contains prebuilt versions of the libraries in the Lib folder. - * - arm_cortexM7lfdp_math.lib (Little endian and Double Precision Floating Point Unit on Cortex-M7) - * - arm_cortexM7bfdp_math.lib (Big endian and Double Precision Floating Point Unit on Cortex-M7) - * - arm_cortexM7lfsp_math.lib (Little endian and Single Precision Floating Point Unit on Cortex-M7) - * - arm_cortexM7bfsp_math.lib (Big endian and Single Precision Floating Point Unit on Cortex-M7) - * - arm_cortexM7l_math.lib (Little endian on Cortex-M7) - * - arm_cortexM7b_math.lib (Big endian on Cortex-M7) - * - arm_cortexM4lf_math.lib (Little endian and Floating Point Unit on Cortex-M4) - * - arm_cortexM4bf_math.lib (Big endian and Floating Point Unit on Cortex-M4) - * - arm_cortexM4l_math.lib (Little endian on Cortex-M4) - * - arm_cortexM4b_math.lib (Big endian on Cortex-M4) - * - arm_cortexM3l_math.lib (Little endian on Cortex-M3) - * - arm_cortexM3b_math.lib (Big endian on Cortex-M3) - * - arm_cortexM0l_math.lib (Little endian on Cortex-M0 / CortexM0+) - * - arm_cortexM0b_math.lib (Big endian on Cortex-M0 / CortexM0+) - * - * The library functions are declared in the public file arm_math.h which is placed in the Include folder. - * Simply include this file and link the appropriate library in the application and begin calling the library functions. The Library supports single - * public header file arm_math.h for Cortex-M7/M4/M3/M0/M0+ with little endian and big endian. Same header file will be used for floating point unit(FPU) variants. - * Define the appropriate pre processor MACRO ARM_MATH_CM7 or ARM_MATH_CM4 or ARM_MATH_CM3 or - * ARM_MATH_CM0 or ARM_MATH_CM0PLUS depending on the target processor in the application. - * - * Examples - * -------- - * - * The library ships with a number of examples which demonstrate how to use the library functions. - * - * Toolchain Support - * ------------ - * - * The library has been developed and tested with MDK-ARM version 5.14.0.0 - * The library is being tested in GCC and IAR toolchains and updates on this activity will be made available shortly. - * - * Building the Library - * ------------ - * - * The library installer contains a project file to re build libraries on MDK-ARM Tool chain in the CMSIS\\DSP_Lib\\Source\\ARM folder. - * - arm_cortexM_math.uvprojx - * - * - * The libraries can be built by opening the arm_cortexM_math.uvprojx project in MDK-ARM, selecting a specific target, and defining the optional pre processor MACROs detailed above. - * - * Pre-processor Macros - * ------------ - * - * Each library project have differant pre-processor macros. - * - * - UNALIGNED_SUPPORT_DISABLE: - * - * Define macro UNALIGNED_SUPPORT_DISABLE, If the silicon does not support unaligned memory access - * - * - ARM_MATH_BIG_ENDIAN: - * - * Define macro ARM_MATH_BIG_ENDIAN to build the library for big endian targets. By default library builds for little endian targets. - * - * - ARM_MATH_MATRIX_CHECK: - * - * Define macro ARM_MATH_MATRIX_CHECK for checking on the input and output sizes of matrices - * - * - ARM_MATH_ROUNDING: - * - * Define macro ARM_MATH_ROUNDING for rounding on support functions - * - * - ARM_MATH_CMx: - * - * Define macro ARM_MATH_CM4 for building the library on Cortex-M4 target, ARM_MATH_CM3 for building library on Cortex-M3 target - * and ARM_MATH_CM0 for building library on Cortex-M0 target, ARM_MATH_CM0PLUS for building library on Cortex-M0+ target, and - * ARM_MATH_CM7 for building the library on cortex-M7. - * - * - __FPU_PRESENT: - * - * Initialize macro __FPU_PRESENT = 1 when building on FPU supported Targets. Enable this macro for M4bf and M4lf libraries - * - *
- * CMSIS-DSP in ARM::CMSIS Pack - * ----------------------------- - * - * The following files relevant to CMSIS-DSP are present in the ARM::CMSIS Pack directories: - * |File/Folder |Content | - * |------------------------------|------------------------------------------------------------------------| - * |\b CMSIS\\Documentation\\DSP | This documentation | - * |\b CMSIS\\DSP_Lib | Software license agreement (license.txt) | - * |\b CMSIS\\DSP_Lib\\Examples | Example projects demonstrating the usage of the library functions | - * |\b CMSIS\\DSP_Lib\\Source | Source files for rebuilding the library | - * - *
- * Revision History of CMSIS-DSP - * ------------ - * Please refer to \ref ChangeLog_pg. - * - * Copyright Notice - * ------------ - * - * Copyright (C) 2010-2015 ARM Limited. All rights reserved. - */ - - -/** - * @defgroup groupMath Basic Math Functions - */ - -/** - * @defgroup groupFastMath Fast Math Functions - * This set of functions provides a fast approximation to sine, cosine, and square root. - * As compared to most of the other functions in the CMSIS math library, the fast math functions - * operate on individual values and not arrays. - * There are separate functions for Q15, Q31, and floating-point data. - * - */ - -/** - * @defgroup groupCmplxMath Complex Math Functions - * This set of functions operates on complex data vectors. - * The data in the complex arrays is stored in an interleaved fashion - * (real, imag, real, imag, ...). - * In the API functions, the number of samples in a complex array refers - * to the number of complex values; the array contains twice this number of - * real values. - */ - -/** - * @defgroup groupFilters Filtering Functions - */ - -/** - * @defgroup groupMatrix Matrix Functions - * - * This set of functions provides basic matrix math operations. - * The functions operate on matrix data structures. For example, - * the type - * definition for the floating-point matrix structure is shown - * below: - * 
- *     typedef struct
- *     {
- *       uint16_t numRows;     // number of rows of the matrix.
- *       uint16_t numCols;     // number of columns of the matrix.
- *       float32_t *pData;     // points to the data of the matrix.
- *     } arm_matrix_instance_f32;
- *
- * There are similar definitions for Q15 and Q31 data types. - * - * The structure specifies the size of the matrix and then points to - * an array of data. The array is of size numRows X numCols - * and the values are arranged in row order. That is, the - * matrix element (i, j) is stored at: - * 
- *     pData[i*numCols + j]
- *
- * - * \par Init Functions - * There is an associated initialization function for each type of matrix - * data structure. - * The initialization function sets the values of the internal structure fields. - * Refer to the function arm_mat_init_f32(), arm_mat_init_q31() - * and arm_mat_init_q15() for floating-point, Q31 and Q15 types, respectively. - * - * \par - * Use of the initialization function is optional. However, if initialization function is used - * then the instance structure cannot be placed into a const data section. - * To place the instance structure in a const data - * section, manually initialize the data structure. For example: - * 
- * arm_matrix_instance_f32 S = {nRows, nColumns, pData};
- * arm_matrix_instance_q31 S = {nRows, nColumns, pData};
- * arm_matrix_instance_q15 S = {nRows, nColumns, pData};
- *
- * where nRows specifies the number of rows, nColumns - * specifies the number of columns, and pData points to the - * data array. - * - * \par Size Checking - * By default all of the matrix functions perform size checking on the input and - * output matrices. For example, the matrix addition function verifies that the - * two input matrices and the output matrix all have the same number of rows and - * columns. If the size check fails the functions return: - * 
- *     ARM_MATH_SIZE_MISMATCH
- *
- * Otherwise the functions return - * 
- *     ARM_MATH_SUCCESS
- *
- * There is some overhead associated with this matrix size checking. - * The matrix size checking is enabled via the \#define - * 
- *     ARM_MATH_MATRIX_CHECK
- *
- * within the library project settings. By default this macro is defined - * and size checking is enabled. By changing the project settings and - * undefining this macro size checking is eliminated and the functions - * run a bit faster. With size checking disabled the functions always - * return ARM_MATH_SUCCESS. - */ - -/** - * @defgroup groupTransforms Transform Functions - */ - -/** - * @defgroup groupController Controller Functions - */ - -/** - * @defgroup groupStats Statistics Functions - */ -/** - * @defgroup groupSupport Support Functions - */ - -/** - * @defgroup groupInterpolation Interpolation Functions - * These functions perform 1- and 2-dimensional interpolation of data. - * Linear interpolation is used for 1-dimensional data and - * bilinear interpolation is used for 2-dimensional data. - */ - -/** - * @defgroup groupExamples Examples - */ -#ifndef _ARM_MATH_H -#define _ARM_MATH_H - -/* ignore some GCC warnings */ -#if defined ( __GNUC__ ) -#pragma GCC diagnostic push -#pragma GCC diagnostic ignored "-Wsign-conversion" -#pragma GCC diagnostic ignored "-Wconversion" -#pragma GCC diagnostic ignored "-Wunused-parameter" -#endif - -#define __CMSIS_GENERIC /* disable NVIC and Systick functions */ - -#if defined(ARM_MATH_CM7) - #include "core_cm7.h" -#elif defined (ARM_MATH_CM4) - #include "core_cm4.h" -#elif defined (ARM_MATH_CM3) - #include "core_cm3.h" -#elif defined (ARM_MATH_CM0) - #include "core_cm0.h" - #define ARM_MATH_CM0_FAMILY -#elif defined (ARM_MATH_CM0PLUS) - #include "core_cm0plus.h" - #define ARM_MATH_CM0_FAMILY -#else - #error "Define according the used Cortex core ARM_MATH_CM7, ARM_MATH_CM4, ARM_MATH_CM3, ARM_MATH_CM0PLUS or ARM_MATH_CM0" -#endif - -#undef __CMSIS_GENERIC /* enable NVIC and Systick functions */ -#include "string.h" -#include "math.h" -#ifdef __cplusplus -extern "C" -{ -#endif - - - /** - * @brief Macros required for reciprocal calculation in Normalized LMS - */ - -#define DELTA_Q31 (0x100) -#define DELTA_Q15 0x5 -#define INDEX_MASK 0x0000003F -#ifndef PI -#define PI 3.14159265358979f -#endif - - /** - * @brief Macros required for SINE and COSINE Fast math approximations - */ - -#define FAST_MATH_TABLE_SIZE 512 -#define FAST_MATH_Q31_SHIFT (32 - 10) -#define FAST_MATH_Q15_SHIFT (16 - 10) -#define CONTROLLER_Q31_SHIFT (32 - 9) -#define TABLE_SIZE 256 -#define TABLE_SPACING_Q31 0x400000 -#define TABLE_SPACING_Q15 0x80 - - /** - * @brief Macros required for SINE and COSINE Controller functions - */ - /* 1.31(q31) Fixed value of 2/360 */ - /* -1 to +1 is divided into 360 values so total spacing is (2/360) */ -#define INPUT_SPACING 0xB60B61 - - /** - * @brief Macro for Unaligned Support - */ -#ifndef UNALIGNED_SUPPORT_DISABLE - #define ALIGN4 -#else - #if defined (__GNUC__) - #define ALIGN4 __attribute__((aligned(4))) - #else - #define ALIGN4 __align(4) - #endif -#endif /* #ifndef UNALIGNED_SUPPORT_DISABLE */ - - /** - * @brief Error status returned by some functions in the library. - */ - - typedef enum - { - ARM_MATH_SUCCESS = 0, /**< No error */ - ARM_MATH_ARGUMENT_ERROR = -1, /**< One or more arguments are incorrect */ - ARM_MATH_LENGTH_ERROR = -2, /**< Length of data buffer is incorrect */ - ARM_MATH_SIZE_MISMATCH = -3, /**< Size of matrices is not compatible with the operation. */ - ARM_MATH_NANINF = -4, /**< Not-a-number (NaN) or infinity is generated */ - ARM_MATH_SINGULAR = -5, /**< Generated by matrix inversion if the input matrix is singular and cannot be inverted. */ - ARM_MATH_TEST_FAILURE = -6 /**< Test Failed */ - } arm_status; - - /** - * @brief 8-bit fractional data type in 1.7 format. - */ - typedef int8_t q7_t; - - /** - * @brief 16-bit fractional data type in 1.15 format. - */ - typedef int16_t q15_t; - - /** - * @brief 32-bit fractional data type in 1.31 format. - */ - typedef int32_t q31_t; - - /** - * @brief 64-bit fractional data type in 1.63 format. - */ - typedef int64_t q63_t; - - /** - * @brief 32-bit floating-point type definition. - */ - typedef float float32_t; - - /** - * @brief 64-bit floating-point type definition. - */ - typedef double float64_t; - - /** - * @brief definition to read/write two 16 bit values. - */ -#if defined __CC_ARM - #define __SIMD32_TYPE int32_t __packed - #define CMSIS_UNUSED __attribute__((unused)) - -#elif defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) - #define __SIMD32_TYPE int32_t - #define CMSIS_UNUSED __attribute__((unused)) - -#elif defined __GNUC__ - #define __SIMD32_TYPE int32_t - #define CMSIS_UNUSED __attribute__((unused)) - -#elif defined __ICCARM__ - #define __SIMD32_TYPE int32_t __packed - #define CMSIS_UNUSED - -#elif defined __CSMC__ - #define __SIMD32_TYPE int32_t - #define CMSIS_UNUSED - -#elif defined __TASKING__ - #define __SIMD32_TYPE __unaligned int32_t - #define CMSIS_UNUSED - -#else - #error Unknown compiler -#endif - -#define __SIMD32(addr) (*(__SIMD32_TYPE **) & (addr)) -#define __SIMD32_CONST(addr) ((__SIMD32_TYPE *)(addr)) -#define _SIMD32_OFFSET(addr) (*(__SIMD32_TYPE *) (addr)) -#define __SIMD64(addr) (*(int64_t **) & (addr)) - -#if defined (ARM_MATH_CM3) || defined (ARM_MATH_CM0_FAMILY) - /** - * @brief definition to pack two 16 bit values. - */ -#define __PKHBT(ARG1, ARG2, ARG3) ( (((int32_t)(ARG1) << 0) & (int32_t)0x0000FFFF) | \ - (((int32_t)(ARG2) << ARG3) & (int32_t)0xFFFF0000) ) -#define __PKHTB(ARG1, ARG2, ARG3) ( (((int32_t)(ARG1) << 0) & (int32_t)0xFFFF0000) | \ - (((int32_t)(ARG2) >> ARG3) & (int32_t)0x0000FFFF) ) - -#endif - - - /** - * @brief definition to pack four 8 bit values. - */ -#ifndef ARM_MATH_BIG_ENDIAN - -#define __PACKq7(v0,v1,v2,v3) ( (((int32_t)(v0) << 0) & (int32_t)0x000000FF) | \ - (((int32_t)(v1) << 8) & (int32_t)0x0000FF00) | \ - (((int32_t)(v2) << 16) & (int32_t)0x00FF0000) | \ - (((int32_t)(v3) << 24) & (int32_t)0xFF000000) ) -#else - -#define __PACKq7(v0,v1,v2,v3) ( (((int32_t)(v3) << 0) & (int32_t)0x000000FF) | \ - (((int32_t)(v2) << 8) & (int32_t)0x0000FF00) | \ - (((int32_t)(v1) << 16) & (int32_t)0x00FF0000) | \ - (((int32_t)(v0) << 24) & (int32_t)0xFF000000) ) - -#endif - - - /** - * @brief Clips Q63 to Q31 values. - */ - static __INLINE q31_t clip_q63_to_q31( - q63_t x) - { - return ((q31_t) (x >> 32) != ((q31_t) x >> 31)) ? - ((0x7FFFFFFF ^ ((q31_t) (x >> 63)))) : (q31_t) x; - } - - /** - * @brief Clips Q63 to Q15 values. - */ - static __INLINE q15_t clip_q63_to_q15( - q63_t x) - { - return ((q31_t) (x >> 32) != ((q31_t) x >> 31)) ? - ((0x7FFF ^ ((q15_t) (x >> 63)))) : (q15_t) (x >> 15); - } - - /** - * @brief Clips Q31 to Q7 values. - */ - static __INLINE q7_t clip_q31_to_q7( - q31_t x) - { - return ((q31_t) (x >> 24) != ((q31_t) x >> 23)) ? - ((0x7F ^ ((q7_t) (x >> 31)))) : (q7_t) x; - } - - /** - * @brief Clips Q31 to Q15 values. - */ - static __INLINE q15_t clip_q31_to_q15( - q31_t x) - { - return ((q31_t) (x >> 16) != ((q31_t) x >> 15)) ? - ((0x7FFF ^ ((q15_t) (x >> 31)))) : (q15_t) x; - } - - /** - * @brief Multiplies 32 X 64 and returns 32 bit result in 2.30 format. - */ - - static __INLINE q63_t mult32x64( - q63_t x, - q31_t y) - { - return ((((q63_t) (x & 0x00000000FFFFFFFF) * y) >> 32) + - (((q63_t) (x >> 32) * y))); - } - -/* - #if defined (ARM_MATH_CM0_FAMILY) && defined ( __CC_ARM ) - #define __CLZ __clz - #endif - */ -/* note: function can be removed when all toolchain support __CLZ for Cortex-M0 */ -#if defined (ARM_MATH_CM0_FAMILY) && ((defined (__ICCARM__)) ) - static __INLINE uint32_t __CLZ( - q31_t data); - - static __INLINE uint32_t __CLZ( - q31_t data) - { - uint32_t count = 0; - uint32_t mask = 0x80000000; - - while((data & mask) == 0) - { - count += 1u; - mask = mask >> 1u; - } - - return (count); - } -#endif - - /** - * @brief Function to Calculates 1/in (reciprocal) value of Q31 Data type. - */ - - static __INLINE uint32_t arm_recip_q31( - q31_t in, - q31_t * dst, - q31_t * pRecipTable) - { - q31_t out; - uint32_t tempVal; - uint32_t index, i; - uint32_t signBits; - - if(in > 0) - { - signBits = ((uint32_t) (__CLZ( in) - 1)); - } - else - { - signBits = ((uint32_t) (__CLZ(-in) - 1)); - } - - /* Convert input sample to 1.31 format */ - in = (in << signBits); - - /* calculation of index for initial approximated Val */ - index = (uint32_t)(in >> 24); - index = (index & INDEX_MASK); - - /* 1.31 with exp 1 */ - out = pRecipTable[index]; - - /* calculation of reciprocal value */ - /* running approximation for two iterations */ - for (i = 0u; i < 2u; i++) - { - tempVal = (uint32_t) (((q63_t) in * out) >> 31); - tempVal = 0x7FFFFFFFu - tempVal; - /* 1.31 with exp 1 */ - /* out = (q31_t) (((q63_t) out * tempVal) >> 30); */ - out = clip_q63_to_q31(((q63_t) out * tempVal) >> 30); - } - - /* write output */ - *dst = out; - - /* return num of signbits of out = 1/in value */ - return (signBits + 1u); - } - - - /** - * @brief Function to Calculates 1/in (reciprocal) value of Q15 Data type. - */ - static __INLINE uint32_t arm_recip_q15( - q15_t in, - q15_t * dst, - q15_t * pRecipTable) - { - q15_t out = 0; - uint32_t tempVal = 0; - uint32_t index = 0, i = 0; - uint32_t signBits = 0; - - if(in > 0) - { - signBits = ((uint32_t)(__CLZ( in) - 17)); - } - else - { - signBits = ((uint32_t)(__CLZ(-in) - 17)); - } - - /* Convert input sample to 1.15 format */ - in = (in << signBits); - - /* calculation of index for initial approximated Val */ - index = (uint32_t)(in >> 8); - index = (index & INDEX_MASK); - - /* 1.15 with exp 1 */ - out = pRecipTable[index]; - - /* calculation of reciprocal value */ - /* running approximation for two iterations */ - for (i = 0u; i < 2u; i++) - { - tempVal = (uint32_t) (((q31_t) in * out) >> 15); - tempVal = 0x7FFFu - tempVal; - /* 1.15 with exp 1 */ - out = (q15_t) (((q31_t) out * tempVal) >> 14); - /* out = clip_q31_to_q15(((q31_t) out * tempVal) >> 14); */ - } - - /* write output */ - *dst = out; - - /* return num of signbits of out = 1/in value */ - return (signBits + 1); - } - - - /* - * @brief C custom defined intrinisic function for only M0 processors - */ -#if defined(ARM_MATH_CM0_FAMILY) - static __INLINE q31_t __SSAT( - q31_t x, - uint32_t y) - { - int32_t posMax, negMin; - uint32_t i; - - posMax = 1; - for (i = 0; i < (y - 1); i++) - { - posMax = posMax * 2; - } - - if(x > 0) - { - posMax = (posMax - 1); - - if(x > posMax) - { - x = posMax; - } - } - else - { - negMin = -posMax; - - if(x < negMin) - { - x = negMin; - } - } - return (x); - } -#endif /* end of ARM_MATH_CM0_FAMILY */ - - - /* - * @brief C custom defined intrinsic function for M3 and M0 processors - */ -#if defined (ARM_MATH_CM3) || defined (ARM_MATH_CM0_FAMILY) - - /* - * @brief C custom defined QADD8 for M3 and M0 processors - */ - static __INLINE uint32_t __QADD8( - uint32_t x, - uint32_t y) - { - q31_t r, s, t, u; - - r = __SSAT(((((q31_t)x << 24) >> 24) + (((q31_t)y << 24) >> 24)), 8) & (int32_t)0x000000FF; - s = __SSAT(((((q31_t)x << 16) >> 24) + (((q31_t)y << 16) >> 24)), 8) & (int32_t)0x000000FF; - t = __SSAT(((((q31_t)x << 8) >> 24) + (((q31_t)y << 8) >> 24)), 8) & (int32_t)0x000000FF; - u = __SSAT(((((q31_t)x ) >> 24) + (((q31_t)y ) >> 24)), 8) & (int32_t)0x000000FF; - - return ((uint32_t)((u << 24) | (t << 16) | (s << 8) | (r ))); - } - - - /* - * @brief C custom defined QSUB8 for M3 and M0 processors - */ - static __INLINE uint32_t __QSUB8( - uint32_t x, - uint32_t y) - { - q31_t r, s, t, u; - - r = __SSAT(((((q31_t)x << 24) >> 24) - (((q31_t)y << 24) >> 24)), 8) & (int32_t)0x000000FF; - s = __SSAT(((((q31_t)x << 16) >> 24) - (((q31_t)y << 16) >> 24)), 8) & (int32_t)0x000000FF; - t = __SSAT(((((q31_t)x << 8) >> 24) - (((q31_t)y << 8) >> 24)), 8) & (int32_t)0x000000FF; - u = __SSAT(((((q31_t)x ) >> 24) - (((q31_t)y ) >> 24)), 8) & (int32_t)0x000000FF; - - return ((uint32_t)((u << 24) | (t << 16) | (s << 8) | (r ))); - } - - - /* - * @brief C custom defined QADD16 for M3 and M0 processors - */ - static __INLINE uint32_t __QADD16( - uint32_t x, - uint32_t y) - { -/* q31_t r, s; without initialisation 'arm_offset_q15 test' fails but 'intrinsic' tests pass! for armCC */ - q31_t r = 0, s = 0; - - r = __SSAT(((((q31_t)x << 16) >> 16) + (((q31_t)y << 16) >> 16)), 16) & (int32_t)0x0000FFFF; - s = __SSAT(((((q31_t)x ) >> 16) + (((q31_t)y ) >> 16)), 16) & (int32_t)0x0000FFFF; - - return ((uint32_t)((s << 16) | (r ))); - } - - - /* - * @brief C custom defined SHADD16 for M3 and M0 processors - */ - static __INLINE uint32_t __SHADD16( - uint32_t x, - uint32_t y) - { - q31_t r, s; - - r = (((((q31_t)x << 16) >> 16) + (((q31_t)y << 16) >> 16)) >> 1) & (int32_t)0x0000FFFF; - s = (((((q31_t)x ) >> 16) + (((q31_t)y ) >> 16)) >> 1) & (int32_t)0x0000FFFF; - - return ((uint32_t)((s << 16) | (r ))); - } - - - /* - * @brief C custom defined QSUB16 for M3 and M0 processors - */ - static __INLINE uint32_t __QSUB16( - uint32_t x, - uint32_t y) - { - q31_t r, s; - - r = __SSAT(((((q31_t)x << 16) >> 16) - (((q31_t)y << 16) >> 16)), 16) & (int32_t)0x0000FFFF; - s = __SSAT(((((q31_t)x ) >> 16) - (((q31_t)y ) >> 16)), 16) & (int32_t)0x0000FFFF; - - return ((uint32_t)((s << 16) | (r ))); - } - - - /* - * @brief C custom defined SHSUB16 for M3 and M0 processors - */ - static __INLINE uint32_t __SHSUB16( - uint32_t x, - uint32_t y) - { - q31_t r, s; - - r = (((((q31_t)x << 16) >> 16) - (((q31_t)y << 16) >> 16)) >> 1) & (int32_t)0x0000FFFF; - s = (((((q31_t)x ) >> 16) - (((q31_t)y ) >> 16)) >> 1) & (int32_t)0x0000FFFF; - - return ((uint32_t)((s << 16) | (r ))); - } - - - /* - * @brief C custom defined QASX for M3 and M0 processors - */ - static __INLINE uint32_t __QASX( - uint32_t x, - uint32_t y) - { - q31_t r, s; - - r = __SSAT(((((q31_t)x << 16) >> 16) - (((q31_t)y ) >> 16)), 16) & (int32_t)0x0000FFFF; - s = __SSAT(((((q31_t)x ) >> 16) + (((q31_t)y << 16) >> 16)), 16) & (int32_t)0x0000FFFF; - - return ((uint32_t)((s << 16) | (r ))); - } - - - /* - * @brief C custom defined SHASX for M3 and M0 processors - */ - static __INLINE uint32_t __SHASX( - uint32_t x, - uint32_t y) - { - q31_t r, s; - - r = (((((q31_t)x << 16) >> 16) - (((q31_t)y ) >> 16)) >> 1) & (int32_t)0x0000FFFF; - s = (((((q31_t)x ) >> 16) + (((q31_t)y << 16) >> 16)) >> 1) & (int32_t)0x0000FFFF; - - return ((uint32_t)((s << 16) | (r ))); - } - - - /* - * @brief C custom defined QSAX for M3 and M0 processors - */ - static __INLINE uint32_t __QSAX( - uint32_t x, - uint32_t y) - { - q31_t r, s; - - r = __SSAT(((((q31_t)x << 16) >> 16) + (((q31_t)y ) >> 16)), 16) & (int32_t)0x0000FFFF; - s = __SSAT(((((q31_t)x ) >> 16) - (((q31_t)y << 16) >> 16)), 16) & (int32_t)0x0000FFFF; - - return ((uint32_t)((s << 16) | (r ))); - } - - - /* - * @brief C custom defined SHSAX for M3 and M0 processors - */ - static __INLINE uint32_t __SHSAX( - uint32_t x, - uint32_t y) - { - q31_t r, s; - - r = (((((q31_t)x << 16) >> 16) + (((q31_t)y ) >> 16)) >> 1) & (int32_t)0x0000FFFF; - s = (((((q31_t)x ) >> 16) - (((q31_t)y << 16) >> 16)) >> 1) & (int32_t)0x0000FFFF; - - return ((uint32_t)((s << 16) | (r ))); - } - - - /* - * @brief C custom defined SMUSDX for M3 and M0 processors - */ - static __INLINE uint32_t __SMUSDX( - uint32_t x, - uint32_t y) - { - return ((uint32_t)(((((q31_t)x << 16) >> 16) * (((q31_t)y ) >> 16)) - - ((((q31_t)x ) >> 16) * (((q31_t)y << 16) >> 16)) )); - } - - /* - * @brief C custom defined SMUADX for M3 and M0 processors - */ - static __INLINE uint32_t __SMUADX( - uint32_t x, - uint32_t y) - { - return ((uint32_t)(((((q31_t)x << 16) >> 16) * (((q31_t)y ) >> 16)) + - ((((q31_t)x ) >> 16) * (((q31_t)y << 16) >> 16)) )); - } - - - /* - * @brief C custom defined QADD for M3 and M0 processors - */ - static __INLINE int32_t __QADD( - int32_t x, - int32_t y) - { - return ((int32_t)(clip_q63_to_q31((q63_t)x + (q31_t)y))); - } - - - /* - * @brief C custom defined QSUB for M3 and M0 processors - */ - static __INLINE int32_t __QSUB( - int32_t x, - int32_t y) - { - return ((int32_t)(clip_q63_to_q31((q63_t)x - (q31_t)y))); - } - - - /* - * @brief C custom defined SMLAD for M3 and M0 processors - */ - static __INLINE uint32_t __SMLAD( - uint32_t x, - uint32_t y, - uint32_t sum) - { - return ((uint32_t)(((((q31_t)x << 16) >> 16) * (((q31_t)y << 16) >> 16)) + - ((((q31_t)x ) >> 16) * (((q31_t)y ) >> 16)) + - ( ((q31_t)sum ) ) )); - } - - - /* - * @brief C custom defined SMLADX for M3 and M0 processors - */ - static __INLINE uint32_t __SMLADX( - uint32_t x, - uint32_t y, - uint32_t sum) - { - return ((uint32_t)(((((q31_t)x << 16) >> 16) * (((q31_t)y ) >> 16)) + - ((((q31_t)x ) >> 16) * (((q31_t)y << 16) >> 16)) + - ( ((q31_t)sum ) ) )); - } - - - /* - * @brief C custom defined SMLSDX for M3 and M0 processors - */ - static __INLINE uint32_t __SMLSDX( - uint32_t x, - uint32_t y, - uint32_t sum) - { - return ((uint32_t)(((((q31_t)x << 16) >> 16) * (((q31_t)y ) >> 16)) - - ((((q31_t)x ) >> 16) * (((q31_t)y << 16) >> 16)) + - ( ((q31_t)sum ) ) )); - } - - - /* - * @brief C custom defined SMLALD for M3 and M0 processors - */ - static __INLINE uint64_t __SMLALD( - uint32_t x, - uint32_t y, - uint64_t sum) - { -/* return (sum + ((q15_t) (x >> 16) * (q15_t) (y >> 16)) + ((q15_t) x * (q15_t) y)); */ - return ((uint64_t)(((((q31_t)x << 16) >> 16) * (((q31_t)y << 16) >> 16)) + - ((((q31_t)x ) >> 16) * (((q31_t)y ) >> 16)) + - ( ((q63_t)sum ) ) )); - } - - - /* - * @brief C custom defined SMLALDX for M3 and M0 processors - */ - static __INLINE uint64_t __SMLALDX( - uint32_t x, - uint32_t y, - uint64_t sum) - { -/* return (sum + ((q15_t) (x >> 16) * (q15_t) y)) + ((q15_t) x * (q15_t) (y >> 16)); */ - return ((uint64_t)(((((q31_t)x << 16) >> 16) * (((q31_t)y ) >> 16)) + - ((((q31_t)x ) >> 16) * (((q31_t)y << 16) >> 16)) + - ( ((q63_t)sum ) ) )); - } - - - /* - * @brief C custom defined SMUAD for M3 and M0 processors - */ - static __INLINE uint32_t __SMUAD( - uint32_t x, - uint32_t y) - { - return ((uint32_t)(((((q31_t)x << 16) >> 16) * (((q31_t)y << 16) >> 16)) + - ((((q31_t)x ) >> 16) * (((q31_t)y ) >> 16)) )); - } - - - /* - * @brief C custom defined SMUSD for M3 and M0 processors - */ - static __INLINE uint32_t __SMUSD( - uint32_t x, - uint32_t y) - { - return ((uint32_t)(((((q31_t)x << 16) >> 16) * (((q31_t)y << 16) >> 16)) - - ((((q31_t)x ) >> 16) * (((q31_t)y ) >> 16)) )); - } - - - /* - * @brief C custom defined SXTB16 for M3 and M0 processors - */ - static __INLINE uint32_t __SXTB16( - uint32_t x) - { - return ((uint32_t)(((((q31_t)x << 24) >> 24) & (q31_t)0x0000FFFF) | - ((((q31_t)x << 8) >> 8) & (q31_t)0xFFFF0000) )); - } - -#endif /* defined (ARM_MATH_CM3) || defined (ARM_MATH_CM0_FAMILY) */ - - - /** - * @brief Instance structure for the Q7 FIR filter. - */ - typedef struct - { - uint16_t numTaps; /**< number of filter coefficients in the filter. */ - q7_t *pState; /**< points to the state variable array. The array is of length numTaps+blockSize-1. */ - q7_t *pCoeffs; /**< points to the coefficient array. The array is of length numTaps.*/ - } arm_fir_instance_q7; - - /** - * @brief Instance structure for the Q15 FIR filter. - */ - typedef struct - { - uint16_t numTaps; /**< number of filter coefficients in the filter. */ - q15_t *pState; /**< points to the state variable array. The array is of length numTaps+blockSize-1. */ - q15_t *pCoeffs; /**< points to the coefficient array. The array is of length numTaps.*/ - } arm_fir_instance_q15; - - /** - * @brief Instance structure for the Q31 FIR filter. - */ - typedef struct - { - uint16_t numTaps; /**< number of filter coefficients in the filter. */ - q31_t *pState; /**< points to the state variable array. The array is of length numTaps+blockSize-1. */ - q31_t *pCoeffs; /**< points to the coefficient array. The array is of length numTaps. */ - } arm_fir_instance_q31; - - /** - * @brief Instance structure for the floating-point FIR filter. - */ - typedef struct - { - uint16_t numTaps; /**< number of filter coefficients in the filter. */ - float32_t *pState; /**< points to the state variable array. The array is of length numTaps+blockSize-1. */ - float32_t *pCoeffs; /**< points to the coefficient array. The array is of length numTaps. */ - } arm_fir_instance_f32; - - - /** - * @brief Processing function for the Q7 FIR filter. - * @param[in] S points to an instance of the Q7 FIR filter structure. - * @param[in] pSrc points to the block of input data. - * @param[out] pDst points to the block of output data. - * @param[in] blockSize number of samples to process. - */ - void arm_fir_q7( - const arm_fir_instance_q7 * S, - q7_t * pSrc, - q7_t * pDst, - uint32_t blockSize); - - - /** - * @brief Initialization function for the Q7 FIR filter. - * @param[in,out] S points to an instance of the Q7 FIR structure. - * @param[in] numTaps Number of filter coefficients in the filter. - * @param[in] pCoeffs points to the filter coefficients. - * @param[in] pState points to the state buffer. - * @param[in] blockSize number of samples that are processed. - */ - void arm_fir_init_q7( - arm_fir_instance_q7 * S, - uint16_t numTaps, - q7_t * pCoeffs, - q7_t * pState, - uint32_t blockSize); - - - /** - * @brief Processing function for the Q15 FIR filter. - * @param[in] S points to an instance of the Q15 FIR structure. - * @param[in] pSrc points to the block of input data. - * @param[out] pDst points to the block of output data. - * @param[in] blockSize number of samples to process. - */ - void arm_fir_q15( - const arm_fir_instance_q15 * S, - q15_t * pSrc, - q15_t * pDst, - uint32_t blockSize); - - - /** - * @brief Processing function for the fast Q15 FIR filter for Cortex-M3 and Cortex-M4. - * @param[in] S points to an instance of the Q15 FIR filter structure. - * @param[in] pSrc points to the block of input data. - * @param[out] pDst points to the block of output data. - * @param[in] blockSize number of samples to process. - */ - void arm_fir_fast_q15( - const arm_fir_instance_q15 * S, - q15_t * pSrc, - q15_t * pDst, - uint32_t blockSize); - - - /** - * @brief Initialization function for the Q15 FIR filter. - * @param[in,out] S points to an instance of the Q15 FIR filter structure. - * @param[in] numTaps Number of filter coefficients in the filter. Must be even and greater than or equal to 4. - * @param[in] pCoeffs points to the filter coefficients. - * @param[in] pState points to the state buffer. - * @param[in] blockSize number of samples that are processed at a time. - * @return The function returns ARM_MATH_SUCCESS if initialization was successful or ARM_MATH_ARGUMENT_ERROR if - * numTaps is not a supported value. - */ - arm_status arm_fir_init_q15( - arm_fir_instance_q15 * S, - uint16_t numTaps, - q15_t * pCoeffs, - q15_t * pState, - uint32_t blockSize); - - - /** - * @brief Processing function for the Q31 FIR filter. - * @param[in] S points to an instance of the Q31 FIR filter structure. - * @param[in] pSrc points to the block of input data. - * @param[out] pDst points to the block of output data. - * @param[in] blockSize number of samples to process. - */ - void arm_fir_q31( - const arm_fir_instance_q31 * S, - q31_t * pSrc, - q31_t * pDst, - uint32_t blockSize); - - - /** - * @brief Processing function for the fast Q31 FIR filter for Cortex-M3 and Cortex-M4. - * @param[in] S points to an instance of the Q31 FIR structure. - * @param[in] pSrc points to the block of input data. - * @param[out] pDst points to the block of output data. - * @param[in] blockSize number of samples to process. - */ - void arm_fir_fast_q31( - const arm_fir_instance_q31 * S, - q31_t * pSrc, - q31_t * pDst, - uint32_t blockSize); - - - /** - * @brief Initialization function for the Q31 FIR filter. - * @param[in,out] S points to an instance of the Q31 FIR structure. - * @param[in] numTaps Number of filter coefficients in the filter. - * @param[in] pCoeffs points to the filter coefficients. - * @param[in] pState points to the state buffer. - * @param[in] blockSize number of samples that are processed at a time. - */ - void arm_fir_init_q31( - arm_fir_instance_q31 * S, - uint16_t numTaps, - q31_t * pCoeffs, - q31_t * pState, - uint32_t blockSize); - - - /** - * @brief Processing function for the floating-point FIR filter. - * @param[in] S points to an instance of the floating-point FIR structure. - * @param[in] pSrc points to the block of input data. - * @param[out] pDst points to the block of output data. - * @param[in] blockSize number of samples to process. - */ - void arm_fir_f32( - const arm_fir_instance_f32 * S, - float32_t * pSrc, - float32_t * pDst, - uint32_t blockSize); - - - /** - * @brief Initialization function for the floating-point FIR filter. - * @param[in,out] S points to an instance of the floating-point FIR filter structure. - * @param[in] numTaps Number of filter coefficients in the filter. - * @param[in] pCoeffs points to the filter coefficients. - * @param[in] pState points to the state buffer. - * @param[in] blockSize number of samples that are processed at a time. - */ - void arm_fir_init_f32( - arm_fir_instance_f32 * S, - uint16_t numTaps, - float32_t * pCoeffs, - float32_t * pState, - uint32_t blockSize); - - - /** - * @brief Instance structure for the Q15 Biquad cascade filter. - */ - typedef struct - { - int8_t numStages; /**< number of 2nd order stages in the filter. Overall order is 2*numStages. */ - q15_t *pState; /**< Points to the array of state coefficients. The array is of length 4*numStages. */ - q15_t *pCoeffs; /**< Points to the array of coefficients. The array is of length 5*numStages. */ - int8_t postShift; /**< Additional shift, in bits, applied to each output sample. */ - } arm_biquad_casd_df1_inst_q15; - - /** - * @brief Instance structure for the Q31 Biquad cascade filter. - */ - typedef struct - { - uint32_t numStages; /**< number of 2nd order stages in the filter. Overall order is 2*numStages. */ - q31_t *pState; /**< Points to the array of state coefficients. The array is of length 4*numStages. */ - q31_t *pCoeffs; /**< Points to the array of coefficients. The array is of length 5*numStages. */ - uint8_t postShift; /**< Additional shift, in bits, applied to each output sample. */ - } arm_biquad_casd_df1_inst_q31; - - /** - * @brief Instance structure for the floating-point Biquad cascade filter. - */ - typedef struct - { - uint32_t numStages; /**< number of 2nd order stages in the filter. Overall order is 2*numStages. */ - float32_t *pState; /**< Points to the array of state coefficients. The array is of length 4*numStages. */ - float32_t *pCoeffs; /**< Points to the array of coefficients. The array is of length 5*numStages. */ - } arm_biquad_casd_df1_inst_f32; - - - /** - * @brief Processing function for the Q15 Biquad cascade filter. - * @param[in] S points to an instance of the Q15 Biquad cascade structure. - * @param[in] pSrc points to the block of input data. - * @param[out] pDst points to the block of output data. - * @param[in] blockSize number of samples to process. - */ - void arm_biquad_cascade_df1_q15( - const arm_biquad_casd_df1_inst_q15 * S, - q15_t * pSrc, - q15_t * pDst, - uint32_t blockSize); - - - /** - * @brief Initialization function for the Q15 Biquad cascade filter. - * @param[in,out] S points to an instance of the Q15 Biquad cascade structure. - * @param[in] numStages number of 2nd order stages in the filter. - * @param[in] pCoeffs points to the filter coefficients. - * @param[in] pState points to the state buffer. - * @param[in] postShift Shift to be applied to the output. Varies according to the coefficients format - */ - void arm_biquad_cascade_df1_init_q15( - arm_biquad_casd_df1_inst_q15 * S, - uint8_t numStages, - q15_t * pCoeffs, - q15_t * pState, - int8_t postShift); - - - /** - * @brief Fast but less precise processing function for the Q15 Biquad cascade filter for Cortex-M3 and Cortex-M4. - * @param[in] S points to an instance of the Q15 Biquad cascade structure. - * @param[in] pSrc points to the block of input data. - * @param[out] pDst points to the block of output data. - * @param[in] blockSize number of samples to process. - */ - void arm_biquad_cascade_df1_fast_q15( - const arm_biquad_casd_df1_inst_q15 * S, - q15_t * pSrc, - q15_t * pDst, - uint32_t blockSize); - - - /** - * @brief Processing function for the Q31 Biquad cascade filter - * @param[in] S points to an instance of the Q31 Biquad cascade structure. - * @param[in] pSrc points to the block of input data. - * @param[out] pDst points to the block of output data. - * @param[in] blockSize number of samples to process. - */ - void arm_biquad_cascade_df1_q31( - const arm_biquad_casd_df1_inst_q31 * S, - q31_t * pSrc, - q31_t * pDst, - uint32_t blockSize); - - - /** - * @brief Fast but less precise processing function for the Q31 Biquad cascade filter for Cortex-M3 and Cortex-M4. - * @param[in] S points to an instance of the Q31 Biquad cascade structure. - * @param[in] pSrc points to the block of input data. - * @param[out] pDst points to the block of output data. - * @param[in] blockSize number of samples to process. - */ - void arm_biquad_cascade_df1_fast_q31( - const arm_biquad_casd_df1_inst_q31 * S, - q31_t * pSrc, - q31_t * pDst, - uint32_t blockSize); - - - /** - * @brief Initialization function for the Q31 Biquad cascade filter. - * @param[in,out] S points to an instance of the Q31 Biquad cascade structure. - * @param[in] numStages number of 2nd order stages in the filter. - * @param[in] pCoeffs points to the filter coefficients. - * @param[in] pState points to the state buffer. - * @param[in] postShift Shift to be applied to the output. Varies according to the coefficients format - */ - void arm_biquad_cascade_df1_init_q31( - arm_biquad_casd_df1_inst_q31 * S, - uint8_t numStages, - q31_t * pCoeffs, - q31_t * pState, - int8_t postShift); - - - /** - * @brief Processing function for the floating-point Biquad cascade filter. - * @param[in] S points to an instance of the floating-point Biquad cascade structure. - * @param[in] pSrc points to the block of input data. - * @param[out] pDst points to the block of output data. - * @param[in] blockSize number of samples to process. - */ - void arm_biquad_cascade_df1_f32( - const arm_biquad_casd_df1_inst_f32 * S, - float32_t * pSrc, - float32_t * pDst, - uint32_t blockSize); - - - /** - * @brief Initialization function for the floating-point Biquad cascade filter. - * @param[in,out] S points to an instance of the floating-point Biquad cascade structure. - * @param[in] numStages number of 2nd order stages in the filter. - * @param[in] pCoeffs points to the filter coefficients. - * @param[in] pState points to the state buffer. - */ - void arm_biquad_cascade_df1_init_f32( - arm_biquad_casd_df1_inst_f32 * S, - uint8_t numStages, - float32_t * pCoeffs, - float32_t * pState); - - - /** - * @brief Instance structure for the floating-point matrix structure. - */ - typedef struct - { - uint16_t numRows; /**< number of rows of the matrix. */ - uint16_t numCols; /**< number of columns of the matrix. */ - float32_t *pData; /**< points to the data of the matrix. */ - } arm_matrix_instance_f32; - - - /** - * @brief Instance structure for the floating-point matrix structure. - */ - typedef struct - { - uint16_t numRows; /**< number of rows of the matrix. */ - uint16_t numCols; /**< number of columns of the matrix. */ - float64_t *pData; /**< points to the data of the matrix. */ - } arm_matrix_instance_f64; - - /** - * @brief Instance structure for the Q15 matrix structure. - */ - typedef struct - { - uint16_t numRows; /**< number of rows of the matrix. */ - uint16_t numCols; /**< number of columns of the matrix. */ - q15_t *pData; /**< points to the data of the matrix. */ - } arm_matrix_instance_q15; - - /** - * @brief Instance structure for the Q31 matrix structure. - */ - typedef struct - { - uint16_t numRows; /**< number of rows of the matrix. */ - uint16_t numCols; /**< number of columns of the matrix. */ - q31_t *pData; /**< points to the data of the matrix. */ - } arm_matrix_instance_q31; - - - /** - * @brief Floating-point matrix addition. - * @param[in] pSrcA points to the first input matrix structure - * @param[in] pSrcB points to the second input matrix structure - * @param[out] pDst points to output matrix structure - * @return The function returns either - * ARM_MATH_SIZE_MISMATCH or ARM_MATH_SUCCESS based on the outcome of size checking. - */ - arm_status arm_mat_add_f32( - const arm_matrix_instance_f32 * pSrcA, - const arm_matrix_instance_f32 * pSrcB, - arm_matrix_instance_f32 * pDst); - - - /** - * @brief Q15 matrix addition. - * @param[in] pSrcA points to the first input matrix structure - * @param[in] pSrcB points to the second input matrix structure - * @param[out] pDst points to output matrix structure - * @return The function returns either - * ARM_MATH_SIZE_MISMATCH or ARM_MATH_SUCCESS based on the outcome of size checking. - */ - arm_status arm_mat_add_q15( - const arm_matrix_instance_q15 * pSrcA, - const arm_matrix_instance_q15 * pSrcB, - arm_matrix_instance_q15 * pDst); - - - /** - * @brief Q31 matrix addition. - * @param[in] pSrcA points to the first input matrix structure - * @param[in] pSrcB points to the second input matrix structure - * @param[out] pDst points to output matrix structure - * @return The function returns either - * ARM_MATH_SIZE_MISMATCH or ARM_MATH_SUCCESS based on the outcome of size checking. - */ - arm_status arm_mat_add_q31( - const arm_matrix_instance_q31 * pSrcA, - const arm_matrix_instance_q31 * pSrcB, - arm_matrix_instance_q31 * pDst); - - - /** - * @brief Floating-point, complex, matrix multiplication. - * @param[in] pSrcA points to the first input matrix structure - * @param[in] pSrcB points to the second input matrix structure - * @param[out] pDst points to output matrix structure - * @return The function returns either - * ARM_MATH_SIZE_MISMATCH or ARM_MATH_SUCCESS based on the outcome of size checking. - */ - arm_status arm_mat_cmplx_mult_f32( - const arm_matrix_instance_f32 * pSrcA, - const arm_matrix_instance_f32 * pSrcB, - arm_matrix_instance_f32 * pDst); - - - /** - * @brief Q15, complex, matrix multiplication. - * @param[in] pSrcA points to the first input matrix structure - * @param[in] pSrcB points to the second input matrix structure - * @param[out] pDst points to output matrix structure - * @return The function returns either - * ARM_MATH_SIZE_MISMATCH or ARM_MATH_SUCCESS based on the outcome of size checking. - */ - arm_status arm_mat_cmplx_mult_q15( - const arm_matrix_instance_q15 * pSrcA, - const arm_matrix_instance_q15 * pSrcB, - arm_matrix_instance_q15 * pDst, - q15_t * pScratch); - - - /** - * @brief Q31, complex, matrix multiplication. - * @param[in] pSrcA points to the first input matrix structure - * @param[in] pSrcB points to the second input matrix structure - * @param[out] pDst points to output matrix structure - * @return The function returns either - * ARM_MATH_SIZE_MISMATCH or ARM_MATH_SUCCESS based on the outcome of size checking. - */ - arm_status arm_mat_cmplx_mult_q31( - const arm_matrix_instance_q31 * pSrcA, - const arm_matrix_instance_q31 * pSrcB, - arm_matrix_instance_q31 * pDst); - - - /** - * @brief Floating-point matrix transpose. - * @param[in] pSrc points to the input matrix - * @param[out] pDst points to the output matrix - * @return The function returns either ARM_MATH_SIZE_MISMATCH - * or ARM_MATH_SUCCESS based on the outcome of size checking. - */ - arm_status arm_mat_trans_f32( - const arm_matrix_instance_f32 * pSrc, - arm_matrix_instance_f32 * pDst); - - - /** - * @brief Q15 matrix transpose. - * @param[in] pSrc points to the input matrix - * @param[out] pDst points to the output matrix - * @return The function returns either ARM_MATH_SIZE_MISMATCH - * or ARM_MATH_SUCCESS based on the outcome of size checking. - */ - arm_status arm_mat_trans_q15( - const arm_matrix_instance_q15 * pSrc, - arm_matrix_instance_q15 * pDst); - - - /** - * @brief Q31 matrix transpose. - * @param[in] pSrc points to the input matrix - * @param[out] pDst points to the output matrix - * @return The function returns either ARM_MATH_SIZE_MISMATCH - * or ARM_MATH_SUCCESS based on the outcome of size checking. - */ - arm_status arm_mat_trans_q31( - const arm_matrix_instance_q31 * pSrc, - arm_matrix_instance_q31 * pDst); - - - /** - * @brief Floating-point matrix multiplication - * @param[in] pSrcA points to the first input matrix structure - * @param[in] pSrcB points to the second input matrix structure - * @param[out] pDst points to output matrix structure - * @return The function returns either - * ARM_MATH_SIZE_MISMATCH or ARM_MATH_SUCCESS based on the outcome of size checking. - */ - arm_status arm_mat_mult_f32( - const arm_matrix_instance_f32 * pSrcA, - const arm_matrix_instance_f32 * pSrcB, - arm_matrix_instance_f32 * pDst); - - - /** - * @brief Q15 matrix multiplication - * @param[in] pSrcA points to the first input matrix structure - * @param[in] pSrcB points to the second input matrix structure - * @param[out] pDst points to output matrix structure - * @param[in] pState points to the array for storing intermediate results - * @return The function returns either - * ARM_MATH_SIZE_MISMATCH or ARM_MATH_SUCCESS based on the outcome of size checking. - */ - arm_status arm_mat_mult_q15( - const arm_matrix_instance_q15 * pSrcA, - const arm_matrix_instance_q15 * pSrcB, - arm_matrix_instance_q15 * pDst, - q15_t * pState); - - - /** - * @brief Q15 matrix multiplication (fast variant) for Cortex-M3 and Cortex-M4 - * @param[in] pSrcA points to the first input matrix structure - * @param[in] pSrcB points to the second input matrix structure - * @param[out] pDst points to output matrix structure - * @param[in] pState points to the array for storing intermediate results - * @return The function returns either - * ARM_MATH_SIZE_MISMATCH or ARM_MATH_SUCCESS based on the outcome of size checking. - */ - arm_status arm_mat_mult_fast_q15( - const arm_matrix_instance_q15 * pSrcA, - const arm_matrix_instance_q15 * pSrcB, - arm_matrix_instance_q15 * pDst, - q15_t * pState); - - - /** - * @brief Q31 matrix multiplication - * @param[in] pSrcA points to the first input matrix structure - * @param[in] pSrcB points to the second input matrix structure - * @param[out] pDst points to output matrix structure - * @return The function returns either - * ARM_MATH_SIZE_MISMATCH or ARM_MATH_SUCCESS based on the outcome of size checking. - */ - arm_status arm_mat_mult_q31( - const arm_matrix_instance_q31 * pSrcA, - const arm_matrix_instance_q31 * pSrcB, - arm_matrix_instance_q31 * pDst); - - - /** - * @brief Q31 matrix multiplication (fast variant) for Cortex-M3 and Cortex-M4 - * @param[in] pSrcA points to the first input matrix structure - * @param[in] pSrcB points to the second input matrix structure - * @param[out] pDst points to output matrix structure - * @return The function returns either - * ARM_MATH_SIZE_MISMATCH or ARM_MATH_SUCCESS based on the outcome of size checking. - */ - arm_status arm_mat_mult_fast_q31( - const arm_matrix_instance_q31 * pSrcA, - const arm_matrix_instance_q31 * pSrcB, - arm_matrix_instance_q31 * pDst); - - - /** - * @brief Floating-point matrix subtraction - * @param[in] pSrcA points to the first input matrix structure - * @param[in] pSrcB points to the second input matrix structure - * @param[out] pDst points to output matrix structure - * @return The function returns either - * ARM_MATH_SIZE_MISMATCH or ARM_MATH_SUCCESS based on the outcome of size checking. - */ - arm_status arm_mat_sub_f32( - const arm_matrix_instance_f32 * pSrcA, - const arm_matrix_instance_f32 * pSrcB, - arm_matrix_instance_f32 * pDst); - - - /** - * @brief Q15 matrix subtraction - * @param[in] pSrcA points to the first input matrix structure - * @param[in] pSrcB points to the second input matrix structure - * @param[out] pDst points to output matrix structure - * @return The function returns either - * ARM_MATH_SIZE_MISMATCH or ARM_MATH_SUCCESS based on the outcome of size checking. - */ - arm_status arm_mat_sub_q15( - const arm_matrix_instance_q15 * pSrcA, - const arm_matrix_instance_q15 * pSrcB, - arm_matrix_instance_q15 * pDst); - - - /** - * @brief Q31 matrix subtraction - * @param[in] pSrcA points to the first input matrix structure - * @param[in] pSrcB points to the second input matrix structure - * @param[out] pDst points to output matrix structure - * @return The function returns either - * ARM_MATH_SIZE_MISMATCH or ARM_MATH_SUCCESS based on the outcome of size checking. - */ - arm_status arm_mat_sub_q31( - const arm_matrix_instance_q31 * pSrcA, - const arm_matrix_instance_q31 * pSrcB, - arm_matrix_instance_q31 * pDst); - - - /** - * @brief Floating-point matrix scaling. - * @param[in] pSrc points to the input matrix - * @param[in] scale scale factor - * @param[out] pDst points to the output matrix - * @return The function returns either - * ARM_MATH_SIZE_MISMATCH or ARM_MATH_SUCCESS based on the outcome of size checking. - */ - arm_status arm_mat_scale_f32( - const arm_matrix_instance_f32 * pSrc, - float32_t scale, - arm_matrix_instance_f32 * pDst); - - - /** - * @brief Q15 matrix scaling. - * @param[in] pSrc points to input matrix - * @param[in] scaleFract fractional portion of the scale factor - * @param[in] shift number of bits to shift the result by - * @param[out] pDst points to output matrix - * @return The function returns either - * ARM_MATH_SIZE_MISMATCH or ARM_MATH_SUCCESS based on the outcome of size checking. - */ - arm_status arm_mat_scale_q15( - const arm_matrix_instance_q15 * pSrc, - q15_t scaleFract, - int32_t shift, - arm_matrix_instance_q15 * pDst); - - - /** - * @brief Q31 matrix scaling. - * @param[in] pSrc points to input matrix - * @param[in] scaleFract fractional portion of the scale factor - * @param[in] shift number of bits to shift the result by - * @param[out] pDst points to output matrix structure - * @return The function returns either - * ARM_MATH_SIZE_MISMATCH or ARM_MATH_SUCCESS based on the outcome of size checking. - */ - arm_status arm_mat_scale_q31( - const arm_matrix_instance_q31 * pSrc, - q31_t scaleFract, - int32_t shift, - arm_matrix_instance_q31 * pDst); - - - /** - * @brief Q31 matrix initialization. - * @param[in,out] S points to an instance of the floating-point matrix structure. - * @param[in] nRows number of rows in the matrix. - * @param[in] nColumns number of columns in the matrix. - * @param[in] pData points to the matrix data array. - */ - void arm_mat_init_q31( - arm_matrix_instance_q31 * S, - uint16_t nRows, - uint16_t nColumns, - q31_t * pData); - - - /** - * @brief Q15 matrix initialization. - * @param[in,out] S points to an instance of the floating-point matrix structure. - * @param[in] nRows number of rows in the matrix. - * @param[in] nColumns number of columns in the matrix. - * @param[in] pData points to the matrix data array. - */ - void arm_mat_init_q15( - arm_matrix_instance_q15 * S, - uint16_t nRows, - uint16_t nColumns, - q15_t * pData); - - - /** - * @brief Floating-point matrix initialization. - * @param[in,out] S points to an instance of the floating-point matrix structure. - * @param[in] nRows number of rows in the matrix. - * @param[in] nColumns number of columns in the matrix. - * @param[in] pData points to the matrix data array. - */ - void arm_mat_init_f32( - arm_matrix_instance_f32 * S, - uint16_t nRows, - uint16_t nColumns, - float32_t * pData); - - - - /** - * @brief Instance structure for the Q15 PID Control. - */ - typedef struct - { - q15_t A0; /**< The derived gain, A0 = Kp + Ki + Kd . */ -#ifdef ARM_MATH_CM0_FAMILY - q15_t A1; - q15_t A2; -#else - q31_t A1; /**< The derived gain A1 = -Kp - 2Kd | Kd.*/ -#endif - q15_t state[3]; /**< The state array of length 3. */ - q15_t Kp; /**< The proportional gain. */ - q15_t Ki; /**< The integral gain. */ - q15_t Kd; /**< The derivative gain. */ - } arm_pid_instance_q15; - - /** - * @brief Instance structure for the Q31 PID Control. - */ - typedef struct - { - q31_t A0; /**< The derived gain, A0 = Kp + Ki + Kd . */ - q31_t A1; /**< The derived gain, A1 = -Kp - 2Kd. */ - q31_t A2; /**< The derived gain, A2 = Kd . */ - q31_t state[3]; /**< The state array of length 3. */ - q31_t Kp; /**< The proportional gain. */ - q31_t Ki; /**< The integral gain. */ - q31_t Kd; /**< The derivative gain. */ - } arm_pid_instance_q31; - - /** - * @brief Instance structure for the floating-point PID Control. - */ - typedef struct - { - float32_t A0; /**< The derived gain, A0 = Kp + Ki + Kd . */ - float32_t A1; /**< The derived gain, A1 = -Kp - 2Kd. */ - float32_t A2; /**< The derived gain, A2 = Kd . */ - float32_t state[3]; /**< The state array of length 3. */ - float32_t Kp; /**< The proportional gain. */ - float32_t Ki; /**< The integral gain. */ - float32_t Kd; /**< The derivative gain. */ - } arm_pid_instance_f32; - - - - /** - * @brief Initialization function for the floating-point PID Control. - * @param[in,out] S points to an instance of the PID structure. - * @param[in] resetStateFlag flag to reset the state. 0 = no change in state 1 = reset the state. - */ - void arm_pid_init_f32( - arm_pid_instance_f32 * S, - int32_t resetStateFlag); - - - /** - * @brief Reset function for the floating-point PID Control. - * @param[in,out] S is an instance of the floating-point PID Control structure - */ - void arm_pid_reset_f32( - arm_pid_instance_f32 * S); - - - /** - * @brief Initialization function for the Q31 PID Control. - * @param[in,out] S points to an instance of the Q15 PID structure. - * @param[in] resetStateFlag flag to reset the state. 0 = no change in state 1 = reset the state. - */ - void arm_pid_init_q31( - arm_pid_instance_q31 * S, - int32_t resetStateFlag); - - - /** - * @brief Reset function for the Q31 PID Control. - * @param[in,out] S points to an instance of the Q31 PID Control structure - */ - - void arm_pid_reset_q31( - arm_pid_instance_q31 * S); - - - /** - * @brief Initialization function for the Q15 PID Control. - * @param[in,out] S points to an instance of the Q15 PID structure. - * @param[in] resetStateFlag flag to reset the state. 0 = no change in state 1 = reset the state. - */ - void arm_pid_init_q15( - arm_pid_instance_q15 * S, - int32_t resetStateFlag); - - - /** - * @brief Reset function for the Q15 PID Control. - * @param[in,out] S points to an instance of the q15 PID Control structure - */ - void arm_pid_reset_q15( - arm_pid_instance_q15 * S); - - - /** - * @brief Instance structure for the floating-point Linear Interpolate function. - */ - typedef struct - { - uint32_t nValues; /**< nValues */ - float32_t x1; /**< x1 */ - float32_t xSpacing; /**< xSpacing */ - float32_t *pYData; /**< pointer to the table of Y values */ - } arm_linear_interp_instance_f32; - - /** - * @brief Instance structure for the floating-point bilinear interpolation function. - */ - typedef struct - { - uint16_t numRows; /**< number of rows in the data table. */ - uint16_t numCols; /**< number of columns in the data table. */ - float32_t *pData; /**< points to the data table. */ - } arm_bilinear_interp_instance_f32; - - /** - * @brief Instance structure for the Q31 bilinear interpolation function. - */ - typedef struct - { - uint16_t numRows; /**< number of rows in the data table. */ - uint16_t numCols; /**< number of columns in the data table. */ - q31_t *pData; /**< points to the data table. */ - } arm_bilinear_interp_instance_q31; - - /** - * @brief Instance structure for the Q15 bilinear interpolation function. - */ - typedef struct - { - uint16_t numRows; /**< number of rows in the data table. */ - uint16_t numCols; /**< number of columns in the data table. */ - q15_t *pData; /**< points to the data table. */ - } arm_bilinear_interp_instance_q15; - - /** - * @brief Instance structure for the Q15 bilinear interpolation function. - */ - typedef struct - { - uint16_t numRows; /**< number of rows in the data table. */ - uint16_t numCols; /**< number of columns in the data table. */ - q7_t *pData; /**< points to the data table. */ - } arm_bilinear_interp_instance_q7; - - - /** - * @brief Q7 vector multiplication. - * @param[in] pSrcA points to the first input vector - * @param[in] pSrcB points to the second input vector - * @param[out] pDst points to the output vector - * @param[in] blockSize number of samples in each vector - */ - void arm_mult_q7( - q7_t * pSrcA, - q7_t * pSrcB, - q7_t * pDst, - uint32_t blockSize); - - - /** - * @brief Q15 vector multiplication. - * @param[in] pSrcA points to the first input vector - * @param[in] pSrcB points to the second input vector - * @param[out] pDst points to the output vector - * @param[in] blockSize number of samples in each vector - */ - void arm_mult_q15( - q15_t * pSrcA, - q15_t * pSrcB, - q15_t * pDst, - uint32_t blockSize); - - - /** - * @brief Q31 vector multiplication. - * @param[in] pSrcA points to the first input vector - * @param[in] pSrcB points to the second input vector - * @param[out] pDst points to the output vector - * @param[in] blockSize number of samples in each vector - */ - void arm_mult_q31( - q31_t * pSrcA, - q31_t * pSrcB, - q31_t * pDst, - uint32_t blockSize); - - - /** - * @brief Floating-point vector multiplication. - * @param[in] pSrcA points to the first input vector - * @param[in] pSrcB points to the second input vector - * @param[out] pDst points to the output vector - * @param[in] blockSize number of samples in each vector - */ - void arm_mult_f32( - float32_t * pSrcA, - float32_t * pSrcB, - float32_t * pDst, - uint32_t blockSize); - - - /** - * @brief Instance structure for the Q15 CFFT/CIFFT function. - */ - typedef struct - { - uint16_t fftLen; /**< length of the FFT. */ - uint8_t ifftFlag; /**< flag that selects forward (ifftFlag=0) or inverse (ifftFlag=1) transform. */ - uint8_t bitReverseFlag; /**< flag that enables (bitReverseFlag=1) or disables (bitReverseFlag=0) bit reversal of output. */ - q15_t *pTwiddle; /**< points to the Sin twiddle factor table. */ - uint16_t *pBitRevTable; /**< points to the bit reversal table. */ - uint16_t twidCoefModifier; /**< twiddle coefficient modifier that supports different size FFTs with the same twiddle factor table. */ - uint16_t bitRevFactor; /**< bit reversal modifier that supports different size FFTs with the same bit reversal table. */ - } arm_cfft_radix2_instance_q15; - -/* Deprecated */ - arm_status arm_cfft_radix2_init_q15( - arm_cfft_radix2_instance_q15 * S, - uint16_t fftLen, - uint8_t ifftFlag, - uint8_t bitReverseFlag); - -/* Deprecated */ - void arm_cfft_radix2_q15( - const arm_cfft_radix2_instance_q15 * S, - q15_t * pSrc); - - - /** - * @brief Instance structure for the Q15 CFFT/CIFFT function. - */ - typedef struct - { - uint16_t fftLen; /**< length of the FFT. */ - uint8_t ifftFlag; /**< flag that selects forward (ifftFlag=0) or inverse (ifftFlag=1) transform. */ - uint8_t bitReverseFlag; /**< flag that enables (bitReverseFlag=1) or disables (bitReverseFlag=0) bit reversal of output. */ - q15_t *pTwiddle; /**< points to the twiddle factor table. */ - uint16_t *pBitRevTable; /**< points to the bit reversal table. */ - uint16_t twidCoefModifier; /**< twiddle coefficient modifier that supports different size FFTs with the same twiddle factor table. */ - uint16_t bitRevFactor; /**< bit reversal modifier that supports different size FFTs with the same bit reversal table. */ - } arm_cfft_radix4_instance_q15; - -/* Deprecated */ - arm_status arm_cfft_radix4_init_q15( - arm_cfft_radix4_instance_q15 * S, - uint16_t fftLen, - uint8_t ifftFlag, - uint8_t bitReverseFlag); - -/* Deprecated */ - void arm_cfft_radix4_q15( - const arm_cfft_radix4_instance_q15 * S, - q15_t * pSrc); - - /** - * @brief Instance structure for the Radix-2 Q31 CFFT/CIFFT function. - */ - typedef struct - { - uint16_t fftLen; /**< length of the FFT. */ - uint8_t ifftFlag; /**< flag that selects forward (ifftFlag=0) or inverse (ifftFlag=1) transform. */ - uint8_t bitReverseFlag; /**< flag that enables (bitReverseFlag=1) or disables (bitReverseFlag=0) bit reversal of output. */ - q31_t *pTwiddle; /**< points to the Twiddle factor table. */ - uint16_t *pBitRevTable; /**< points to the bit reversal table. */ - uint16_t twidCoefModifier; /**< twiddle coefficient modifier that supports different size FFTs with the same twiddle factor table. */ - uint16_t bitRevFactor; /**< bit reversal modifier that supports different size FFTs with the same bit reversal table. */ - } arm_cfft_radix2_instance_q31; - -/* Deprecated */ - arm_status arm_cfft_radix2_init_q31( - arm_cfft_radix2_instance_q31 * S, - uint16_t fftLen, - uint8_t ifftFlag, - uint8_t bitReverseFlag); - -/* Deprecated */ - void arm_cfft_radix2_q31( - const arm_cfft_radix2_instance_q31 * S, - q31_t * pSrc); - - /** - * @brief Instance structure for the Q31 CFFT/CIFFT function. - */ - typedef struct - { - uint16_t fftLen; /**< length of the FFT. */ - uint8_t ifftFlag; /**< flag that selects forward (ifftFlag=0) or inverse (ifftFlag=1) transform. */ - uint8_t bitReverseFlag; /**< flag that enables (bitReverseFlag=1) or disables (bitReverseFlag=0) bit reversal of output. */ - q31_t *pTwiddle; /**< points to the twiddle factor table. */ - uint16_t *pBitRevTable; /**< points to the bit reversal table. */ - uint16_t twidCoefModifier; /**< twiddle coefficient modifier that supports different size FFTs with the same twiddle factor table. */ - uint16_t bitRevFactor; /**< bit reversal modifier that supports different size FFTs with the same bit reversal table. */ - } arm_cfft_radix4_instance_q31; - -/* Deprecated */ - void arm_cfft_radix4_q31( - const arm_cfft_radix4_instance_q31 * S, - q31_t * pSrc); - -/* Deprecated */ - arm_status arm_cfft_radix4_init_q31( - arm_cfft_radix4_instance_q31 * S, - uint16_t fftLen, - uint8_t ifftFlag, - uint8_t bitReverseFlag); - - /** - * @brief Instance structure for the floating-point CFFT/CIFFT function. - */ - typedef struct - { - uint16_t fftLen; /**< length of the FFT. */ - uint8_t ifftFlag; /**< flag that selects forward (ifftFlag=0) or inverse (ifftFlag=1) transform. */ - uint8_t bitReverseFlag; /**< flag that enables (bitReverseFlag=1) or disables (bitReverseFlag=0) bit reversal of output. */ - float32_t *pTwiddle; /**< points to the Twiddle factor table. */ - uint16_t *pBitRevTable; /**< points to the bit reversal table. */ - uint16_t twidCoefModifier; /**< twiddle coefficient modifier that supports different size FFTs with the same twiddle factor table. */ - uint16_t bitRevFactor; /**< bit reversal modifier that supports different size FFTs with the same bit reversal table. */ - float32_t onebyfftLen; /**< value of 1/fftLen. */ - } arm_cfft_radix2_instance_f32; - -/* Deprecated */ - arm_status arm_cfft_radix2_init_f32( - arm_cfft_radix2_instance_f32 * S, - uint16_t fftLen, - uint8_t ifftFlag, - uint8_t bitReverseFlag); - -/* Deprecated */ - void arm_cfft_radix2_f32( - const arm_cfft_radix2_instance_f32 * S, - float32_t * pSrc); - - /** - * @brief Instance structure for the floating-point CFFT/CIFFT function. - */ - typedef struct - { - uint16_t fftLen; /**< length of the FFT. */ - uint8_t ifftFlag; /**< flag that selects forward (ifftFlag=0) or inverse (ifftFlag=1) transform. */ - uint8_t bitReverseFlag; /**< flag that enables (bitReverseFlag=1) or disables (bitReverseFlag=0) bit reversal of output. */ - float32_t *pTwiddle; /**< points to the Twiddle factor table. */ - uint16_t *pBitRevTable; /**< points to the bit reversal table. */ - uint16_t twidCoefModifier; /**< twiddle coefficient modifier that supports different size FFTs with the same twiddle factor table. */ - uint16_t bitRevFactor; /**< bit reversal modifier that supports different size FFTs with the same bit reversal table. */ - float32_t onebyfftLen; /**< value of 1/fftLen. */ - } arm_cfft_radix4_instance_f32; - -/* Deprecated */ - arm_status arm_cfft_radix4_init_f32( - arm_cfft_radix4_instance_f32 * S, - uint16_t fftLen, - uint8_t ifftFlag, - uint8_t bitReverseFlag); - -/* Deprecated */ - void arm_cfft_radix4_f32( - const arm_cfft_radix4_instance_f32 * S, - float32_t * pSrc); - - /** - * @brief Instance structure for the fixed-point CFFT/CIFFT function. - */ - typedef struct - { - uint16_t fftLen; /**< length of the FFT. */ - const q15_t *pTwiddle; /**< points to the Twiddle factor table. */ - const uint16_t *pBitRevTable; /**< points to the bit reversal table. */ - uint16_t bitRevLength; /**< bit reversal table length. */ - } arm_cfft_instance_q15; - -void arm_cfft_q15( - const arm_cfft_instance_q15 * S, - q15_t * p1, - uint8_t ifftFlag, - uint8_t bitReverseFlag); - - /** - * @brief Instance structure for the fixed-point CFFT/CIFFT function. - */ - typedef struct - { - uint16_t fftLen; /**< length of the FFT. */ - const q31_t *pTwiddle; /**< points to the Twiddle factor table. */ - const uint16_t *pBitRevTable; /**< points to the bit reversal table. */ - uint16_t bitRevLength; /**< bit reversal table length. */ - } arm_cfft_instance_q31; - -void arm_cfft_q31( - const arm_cfft_instance_q31 * S, - q31_t * p1, - uint8_t ifftFlag, - uint8_t bitReverseFlag); - - /** - * @brief Instance structure for the floating-point CFFT/CIFFT function. - */ - typedef struct - { - uint16_t fftLen; /**< length of the FFT. */ - const float32_t *pTwiddle; /**< points to the Twiddle factor table. */ - const uint16_t *pBitRevTable; /**< points to the bit reversal table. */ - uint16_t bitRevLength; /**< bit reversal table length. */ - } arm_cfft_instance_f32; - - void arm_cfft_f32( - const arm_cfft_instance_f32 * S, - float32_t * p1, - uint8_t ifftFlag, - uint8_t bitReverseFlag); - - /** - * @brief Instance structure for the Q15 RFFT/RIFFT function. - */ - typedef struct - { - uint32_t fftLenReal; /**< length of the real FFT. */ - uint8_t ifftFlagR; /**< flag that selects forward (ifftFlagR=0) or inverse (ifftFlagR=1) transform. */ - uint8_t bitReverseFlagR; /**< flag that enables (bitReverseFlagR=1) or disables (bitReverseFlagR=0) bit reversal of output. */ - uint32_t twidCoefRModifier; /**< twiddle coefficient modifier that supports different size FFTs with the same twiddle factor table. */ - q15_t *pTwiddleAReal; /**< points to the real twiddle factor table. */ - q15_t *pTwiddleBReal; /**< points to the imag twiddle factor table. */ - const arm_cfft_instance_q15 *pCfft; /**< points to the complex FFT instance. */ - } arm_rfft_instance_q15; - - arm_status arm_rfft_init_q15( - arm_rfft_instance_q15 * S, - uint32_t fftLenReal, - uint32_t ifftFlagR, - uint32_t bitReverseFlag); - - void arm_rfft_q15( - const arm_rfft_instance_q15 * S, - q15_t * pSrc, - q15_t * pDst); - - /** - * @brief Instance structure for the Q31 RFFT/RIFFT function. - */ - typedef struct - { - uint32_t fftLenReal; /**< length of the real FFT. */ - uint8_t ifftFlagR; /**< flag that selects forward (ifftFlagR=0) or inverse (ifftFlagR=1) transform. */ - uint8_t bitReverseFlagR; /**< flag that enables (bitReverseFlagR=1) or disables (bitReverseFlagR=0) bit reversal of output. */ - uint32_t twidCoefRModifier; /**< twiddle coefficient modifier that supports different size FFTs with the same twiddle factor table. */ - q31_t *pTwiddleAReal; /**< points to the real twiddle factor table. */ - q31_t *pTwiddleBReal; /**< points to the imag twiddle factor table. */ - const arm_cfft_instance_q31 *pCfft; /**< points to the complex FFT instance. */ - } arm_rfft_instance_q31; - - arm_status arm_rfft_init_q31( - arm_rfft_instance_q31 * S, - uint32_t fftLenReal, - uint32_t ifftFlagR, - uint32_t bitReverseFlag); - - void arm_rfft_q31( - const arm_rfft_instance_q31 * S, - q31_t * pSrc, - q31_t * pDst); - - /** - * @brief Instance structure for the floating-point RFFT/RIFFT function. - */ - typedef struct - { - uint32_t fftLenReal; /**< length of the real FFT. */ - uint16_t fftLenBy2; /**< length of the complex FFT. */ - uint8_t ifftFlagR; /**< flag that selects forward (ifftFlagR=0) or inverse (ifftFlagR=1) transform. */ - uint8_t bitReverseFlagR; /**< flag that enables (bitReverseFlagR=1) or disables (bitReverseFlagR=0) bit reversal of output. */ - uint32_t twidCoefRModifier; /**< twiddle coefficient modifier that supports different size FFTs with the same twiddle factor table. */ - float32_t *pTwiddleAReal; /**< points to the real twiddle factor table. */ - float32_t *pTwiddleBReal; /**< points to the imag twiddle factor table. */ - arm_cfft_radix4_instance_f32 *pCfft; /**< points to the complex FFT instance. */ - } arm_rfft_instance_f32; - - arm_status arm_rfft_init_f32( - arm_rfft_instance_f32 * S, - arm_cfft_radix4_instance_f32 * S_CFFT, - uint32_t fftLenReal, - uint32_t ifftFlagR, - uint32_t bitReverseFlag); - - void arm_rfft_f32( - const arm_rfft_instance_f32 * S, - float32_t * pSrc, - float32_t * pDst); - - /** - * @brief Instance structure for the floating-point RFFT/RIFFT function. - */ -typedef struct - { - arm_cfft_instance_f32 Sint; /**< Internal CFFT structure. */ - uint16_t fftLenRFFT; /**< length of the real sequence */ - float32_t * pTwiddleRFFT; /**< Twiddle factors real stage */ - } arm_rfft_fast_instance_f32 ; - -arm_status arm_rfft_fast_init_f32 ( - arm_rfft_fast_instance_f32 * S, - uint16_t fftLen); - -void arm_rfft_fast_f32( - arm_rfft_fast_instance_f32 * S, - float32_t * p, float32_t * pOut, - uint8_t ifftFlag); - - /** - * @brief Instance structure for the floating-point DCT4/IDCT4 function. - */ - typedef struct - { - uint16_t N; /**< length of the DCT4. */ - uint16_t Nby2; /**< half of the length of the DCT4. */ - float32_t normalize; /**< normalizing factor. */ - float32_t *pTwiddle; /**< points to the twiddle factor table. */ - float32_t *pCosFactor; /**< points to the cosFactor table. */ - arm_rfft_instance_f32 *pRfft; /**< points to the real FFT instance. */ - arm_cfft_radix4_instance_f32 *pCfft; /**< points to the complex FFT instance. */ - } arm_dct4_instance_f32; - - - /** - * @brief Initialization function for the floating-point DCT4/IDCT4. - * @param[in,out] S points to an instance of floating-point DCT4/IDCT4 structure. - * @param[in] S_RFFT points to an instance of floating-point RFFT/RIFFT structure. - * @param[in] S_CFFT points to an instance of floating-point CFFT/CIFFT structure. - * @param[in] N length of the DCT4. - * @param[in] Nby2 half of the length of the DCT4. - * @param[in] normalize normalizing factor. - * @return arm_status function returns ARM_MATH_SUCCESS if initialization is successful or ARM_MATH_ARGUMENT_ERROR if fftLenReal is not a supported transform length. - */ - arm_status arm_dct4_init_f32( - arm_dct4_instance_f32 * S, - arm_rfft_instance_f32 * S_RFFT, - arm_cfft_radix4_instance_f32 * S_CFFT, - uint16_t N, - uint16_t Nby2, - float32_t normalize); - - - /** - * @brief Processing function for the floating-point DCT4/IDCT4. - * @param[in] S points to an instance of the floating-point DCT4/IDCT4 structure. - * @param[in] pState points to state buffer. - * @param[in,out] pInlineBuffer points to the in-place input and output buffer. - */ - void arm_dct4_f32( - const arm_dct4_instance_f32 * S, - float32_t * pState, - float32_t * pInlineBuffer); - - - /** - * @brief Instance structure for the Q31 DCT4/IDCT4 function. - */ - typedef struct - { - uint16_t N; /**< length of the DCT4. */ - uint16_t Nby2; /**< half of the length of the DCT4. */ - q31_t normalize; /**< normalizing factor. */ - q31_t *pTwiddle; /**< points to the twiddle factor table. */ - q31_t *pCosFactor; /**< points to the cosFactor table. */ - arm_rfft_instance_q31 *pRfft; /**< points to the real FFT instance. */ - arm_cfft_radix4_instance_q31 *pCfft; /**< points to the complex FFT instance. */ - } arm_dct4_instance_q31; - - - /** - * @brief Initialization function for the Q31 DCT4/IDCT4. - * @param[in,out] S points to an instance of Q31 DCT4/IDCT4 structure. - * @param[in] S_RFFT points to an instance of Q31 RFFT/RIFFT structure - * @param[in] S_CFFT points to an instance of Q31 CFFT/CIFFT structure - * @param[in] N length of the DCT4. - * @param[in] Nby2 half of the length of the DCT4. - * @param[in] normalize normalizing factor. - * @return arm_status function returns ARM_MATH_SUCCESS if initialization is successful or ARM_MATH_ARGUMENT_ERROR if N is not a supported transform length. - */ - arm_status arm_dct4_init_q31( - arm_dct4_instance_q31 * S, - arm_rfft_instance_q31 * S_RFFT, - arm_cfft_radix4_instance_q31 * S_CFFT, - uint16_t N, - uint16_t Nby2, - q31_t normalize); - - - /** - * @brief Processing function for the Q31 DCT4/IDCT4. - * @param[in] S points to an instance of the Q31 DCT4 structure. - * @param[in] pState points to state buffer. - * @param[in,out] pInlineBuffer points to the in-place input and output buffer. - */ - void arm_dct4_q31( - const arm_dct4_instance_q31 * S, - q31_t * pState, - q31_t * pInlineBuffer); - - - /** - * @brief Instance structure for the Q15 DCT4/IDCT4 function. - */ - typedef struct - { - uint16_t N; /**< length of the DCT4. */ - uint16_t Nby2; /**< half of the length of the DCT4. */ - q15_t normalize; /**< normalizing factor. */ - q15_t *pTwiddle; /**< points to the twiddle factor table. */ - q15_t *pCosFactor; /**< points to the cosFactor table. */ - arm_rfft_instance_q15 *pRfft; /**< points to the real FFT instance. */ - arm_cfft_radix4_instance_q15 *pCfft; /**< points to the complex FFT instance. */ - } arm_dct4_instance_q15; - - - /** - * @brief Initialization function for the Q15 DCT4/IDCT4. - * @param[in,out] S points to an instance of Q15 DCT4/IDCT4 structure. - * @param[in] S_RFFT points to an instance of Q15 RFFT/RIFFT structure. - * @param[in] S_CFFT points to an instance of Q15 CFFT/CIFFT structure. - * @param[in] N length of the DCT4. - * @param[in] Nby2 half of the length of the DCT4. - * @param[in] normalize normalizing factor. - * @return arm_status function returns ARM_MATH_SUCCESS if initialization is successful or ARM_MATH_ARGUMENT_ERROR if N is not a supported transform length. - */ - arm_status arm_dct4_init_q15( - arm_dct4_instance_q15 * S, - arm_rfft_instance_q15 * S_RFFT, - arm_cfft_radix4_instance_q15 * S_CFFT, - uint16_t N, - uint16_t Nby2, - q15_t normalize); - - - /** - * @brief Processing function for the Q15 DCT4/IDCT4. - * @param[in] S points to an instance of the Q15 DCT4 structure. - * @param[in] pState points to state buffer. - * @param[in,out] pInlineBuffer points to the in-place input and output buffer. - */ - void arm_dct4_q15( - const arm_dct4_instance_q15 * S, - q15_t * pState, - q15_t * pInlineBuffer); - - - /** - * @brief Floating-point vector addition. - * @param[in] pSrcA points to the first input vector - * @param[in] pSrcB points to the second input vector - * @param[out] pDst points to the output vector - * @param[in] blockSize number of samples in each vector - */ - void arm_add_f32( - float32_t * pSrcA, - float32_t * pSrcB, - float32_t * pDst, - uint32_t blockSize); - - - /** - * @brief Q7 vector addition. - * @param[in] pSrcA points to the first input vector - * @param[in] pSrcB points to the second input vector - * @param[out] pDst points to the output vector - * @param[in] blockSize number of samples in each vector - */ - void arm_add_q7( - q7_t * pSrcA, - q7_t * pSrcB, - q7_t * pDst, - uint32_t blockSize); - - - /** - * @brief Q15 vector addition. - * @param[in] pSrcA points to the first input vector - * @param[in] pSrcB points to the second input vector - * @param[out] pDst points to the output vector - * @param[in] blockSize number of samples in each vector - */ - void arm_add_q15( - q15_t * pSrcA, - q15_t * pSrcB, - q15_t * pDst, - uint32_t blockSize); - - - /** - * @brief Q31 vector addition. - * @param[in] pSrcA points to the first input vector - * @param[in] pSrcB points to the second input vector - * @param[out] pDst points to the output vector - * @param[in] blockSize number of samples in each vector - */ - void arm_add_q31( - q31_t * pSrcA, - q31_t * pSrcB, - q31_t * pDst, - uint32_t blockSize); - - - /** - * @brief Floating-point vector subtraction. - * @param[in] pSrcA points to the first input vector - * @param[in] pSrcB points to the second input vector - * @param[out] pDst points to the output vector - * @param[in] blockSize number of samples in each vector - */ - void arm_sub_f32( - float32_t * pSrcA, - float32_t * pSrcB, - float32_t * pDst, - uint32_t blockSize); - - - /** - * @brief Q7 vector subtraction. - * @param[in] pSrcA points to the first input vector - * @param[in] pSrcB points to the second input vector - * @param[out] pDst points to the output vector - * @param[in] blockSize number of samples in each vector - */ - void arm_sub_q7( - q7_t * pSrcA, - q7_t * pSrcB, - q7_t * pDst, - uint32_t blockSize); - - - /** - * @brief Q15 vector subtraction. - * @param[in] pSrcA points to the first input vector - * @param[in] pSrcB points to the second input vector - * @param[out] pDst points to the output vector - * @param[in] blockSize number of samples in each vector - */ - void arm_sub_q15( - q15_t * pSrcA, - q15_t * pSrcB, - q15_t * pDst, - uint32_t blockSize); - - - /** - * @brief Q31 vector subtraction. - * @param[in] pSrcA points to the first input vector - * @param[in] pSrcB points to the second input vector - * @param[out] pDst points to the output vector - * @param[in] blockSize number of samples in each vector - */ - void arm_sub_q31( - q31_t * pSrcA, - q31_t * pSrcB, - q31_t * pDst, - uint32_t blockSize); - - - /** - * @brief Multiplies a floating-point vector by a scalar. - * @param[in] pSrc points to the input vector - * @param[in] scale scale factor to be applied - * @param[out] pDst points to the output vector - * @param[in] blockSize number of samples in the vector - */ - void arm_scale_f32( - float32_t * pSrc, - float32_t scale, - float32_t * pDst, - uint32_t blockSize); - - - /** - * @brief Multiplies a Q7 vector by a scalar. - * @param[in] pSrc points to the input vector - * @param[in] scaleFract fractional portion of the scale value - * @param[in] shift number of bits to shift the result by - * @param[out] pDst points to the output vector - * @param[in] blockSize number of samples in the vector - */ - void arm_scale_q7( - q7_t * pSrc, - q7_t scaleFract, - int8_t shift, - q7_t * pDst, - uint32_t blockSize); - - - /** - * @brief Multiplies a Q15 vector by a scalar. - * @param[in] pSrc points to the input vector - * @param[in] scaleFract fractional portion of the scale value - * @param[in] shift number of bits to shift the result by - * @param[out] pDst points to the output vector - * @param[in] blockSize number of samples in the vector - */ - void arm_scale_q15( - q15_t * pSrc, - q15_t scaleFract, - int8_t shift, - q15_t * pDst, - uint32_t blockSize); - - - /** - * @brief Multiplies a Q31 vector by a scalar. - * @param[in] pSrc points to the input vector - * @param[in] scaleFract fractional portion of the scale value - * @param[in] shift number of bits to shift the result by - * @param[out] pDst points to the output vector - * @param[in] blockSize number of samples in the vector - */ - void arm_scale_q31( - q31_t * pSrc, - q31_t scaleFract, - int8_t shift, - q31_t * pDst, - uint32_t blockSize); - - - /** - * @brief Q7 vector absolute value. - * @param[in] pSrc points to the input buffer - * @param[out] pDst points to the output buffer - * @param[in] blockSize number of samples in each vector - */ - void arm_abs_q7( - q7_t * pSrc, - q7_t * pDst, - uint32_t blockSize); - - - /** - * @brief Floating-point vector absolute value. - * @param[in] pSrc points to the input buffer - * @param[out] pDst points to the output buffer - * @param[in] blockSize number of samples in each vector - */ - void arm_abs_f32( - float32_t * pSrc, - float32_t * pDst, - uint32_t blockSize); - - - /** - * @brief Q15 vector absolute value. - * @param[in] pSrc points to the input buffer - * @param[out] pDst points to the output buffer - * @param[in] blockSize number of samples in each vector - */ - void arm_abs_q15( - q15_t * pSrc, - q15_t * pDst, - uint32_t blockSize); - - - /** - * @brief Q31 vector absolute value. - * @param[in] pSrc points to the input buffer - * @param[out] pDst points to the output buffer - * @param[in] blockSize number of samples in each vector - */ - void arm_abs_q31( - q31_t * pSrc, - q31_t * pDst, - uint32_t blockSize); - - - /** - * @brief Dot product of floating-point vectors. - * @param[in] pSrcA points to the first input vector - * @param[in] pSrcB points to the second input vector - * @param[in] blockSize number of samples in each vector - * @param[out] result output result returned here - */ - void arm_dot_prod_f32( - float32_t * pSrcA, - float32_t * pSrcB, - uint32_t blockSize, - float32_t * result); - - - /** - * @brief Dot product of Q7 vectors. - * @param[in] pSrcA points to the first input vector - * @param[in] pSrcB points to the second input vector - * @param[in] blockSize number of samples in each vector - * @param[out] result output result returned here - */ - void arm_dot_prod_q7( - q7_t * pSrcA, - q7_t * pSrcB, - uint32_t blockSize, - q31_t * result); - - - /** - * @brief Dot product of Q15 vectors. - * @param[in] pSrcA points to the first input vector - * @param[in] pSrcB points to the second input vector - * @param[in] blockSize number of samples in each vector - * @param[out] result output result returned here - */ - void arm_dot_prod_q15( - q15_t * pSrcA, - q15_t * pSrcB, - uint32_t blockSize, - q63_t * result); - - - /** - * @brief Dot product of Q31 vectors. - * @param[in] pSrcA points to the first input vector - * @param[in] pSrcB points to the second input vector - * @param[in] blockSize number of samples in each vector - * @param[out] result output result returned here - */ - void arm_dot_prod_q31( - q31_t * pSrcA, - q31_t * pSrcB, - uint32_t blockSize, - q63_t * result); - - - /** - * @brief Shifts the elements of a Q7 vector a specified number of bits. - * @param[in] pSrc points to the input vector - * @param[in] shiftBits number of bits to shift. A positive value shifts left; a negative value shifts right. - * @param[out] pDst points to the output vector - * @param[in] blockSize number of samples in the vector - */ - void arm_shift_q7( - q7_t * pSrc, - int8_t shiftBits, - q7_t * pDst, - uint32_t blockSize); - - - /** - * @brief Shifts the elements of a Q15 vector a specified number of bits. - * @param[in] pSrc points to the input vector - * @param[in] shiftBits number of bits to shift. A positive value shifts left; a negative value shifts right. - * @param[out] pDst points to the output vector - * @param[in] blockSize number of samples in the vector - */ - void arm_shift_q15( - q15_t * pSrc, - int8_t shiftBits, - q15_t * pDst, - uint32_t blockSize); - - - /** - * @brief Shifts the elements of a Q31 vector a specified number of bits. - * @param[in] pSrc points to the input vector - * @param[in] shiftBits number of bits to shift. A positive value shifts left; a negative value shifts right. - * @param[out] pDst points to the output vector - * @param[in] blockSize number of samples in the vector - */ - void arm_shift_q31( - q31_t * pSrc, - int8_t shiftBits, - q31_t * pDst, - uint32_t blockSize); - - - /** - * @brief Adds a constant offset to a floating-point vector. - * @param[in] pSrc points to the input vector - * @param[in] offset is the offset to be added - * @param[out] pDst points to the output vector - * @param[in] blockSize number of samples in the vector - */ - void arm_offset_f32( - float32_t * pSrc, - float32_t offset, - float32_t * pDst, - uint32_t blockSize); - - - /** - * @brief Adds a constant offset to a Q7 vector. - * @param[in] pSrc points to the input vector - * @param[in] offset is the offset to be added - * @param[out] pDst points to the output vector - * @param[in] blockSize number of samples in the vector - */ - void arm_offset_q7( - q7_t * pSrc, - q7_t offset, - q7_t * pDst, - uint32_t blockSize); - - - /** - * @brief Adds a constant offset to a Q15 vector. - * @param[in] pSrc points to the input vector - * @param[in] offset is the offset to be added - * @param[out] pDst points to the output vector - * @param[in] blockSize number of samples in the vector - */ - void arm_offset_q15( - q15_t * pSrc, - q15_t offset, - q15_t * pDst, - uint32_t blockSize); - - - /** - * @brief Adds a constant offset to a Q31 vector. - * @param[in] pSrc points to the input vector - * @param[in] offset is the offset to be added - * @param[out] pDst points to the output vector - * @param[in] blockSize number of samples in the vector - */ - void arm_offset_q31( - q31_t * pSrc, - q31_t offset, - q31_t * pDst, - uint32_t blockSize); - - - /** - * @brief Negates the elements of a floating-point vector. - * @param[in] pSrc points to the input vector - * @param[out] pDst points to the output vector - * @param[in] blockSize number of samples in the vector - */ - void arm_negate_f32( - float32_t * pSrc, - float32_t * pDst, - uint32_t blockSize); - - - /** - * @brief Negates the elements of a Q7 vector. - * @param[in] pSrc points to the input vector - * @param[out] pDst points to the output vector - * @param[in] blockSize number of samples in the vector - */ - void arm_negate_q7( - q7_t * pSrc, - q7_t * pDst, - uint32_t blockSize); - - - /** - * @brief Negates the elements of a Q15 vector. - * @param[in] pSrc points to the input vector - * @param[out] pDst points to the output vector - * @param[in] blockSize number of samples in the vector - */ - void arm_negate_q15( - q15_t * pSrc, - q15_t * pDst, - uint32_t blockSize); - - - /** - * @brief Negates the elements of a Q31 vector. - * @param[in] pSrc points to the input vector - * @param[out] pDst points to the output vector - * @param[in] blockSize number of samples in the vector - */ - void arm_negate_q31( - q31_t * pSrc, - q31_t * pDst, - uint32_t blockSize); - - - /** - * @brief Copies the elements of a floating-point vector. - * @param[in] pSrc input pointer - * @param[out] pDst output pointer - * @param[in] blockSize number of samples to process - */ - void arm_copy_f32( - float32_t * pSrc, - float32_t * pDst, - uint32_t blockSize); - - - /** - * @brief Copies the elements of a Q7 vector. - * @param[in] pSrc input pointer - * @param[out] pDst output pointer - * @param[in] blockSize number of samples to process - */ - void arm_copy_q7( - q7_t * pSrc, - q7_t * pDst, - uint32_t blockSize); - - - /** - * @brief Copies the elements of a Q15 vector. - * @param[in] pSrc input pointer - * @param[out] pDst output pointer - * @param[in] blockSize number of samples to process - */ - void arm_copy_q15( - q15_t * pSrc, - q15_t * pDst, - uint32_t blockSize); - - - /** - * @brief Copies the elements of a Q31 vector. - * @param[in] pSrc input pointer - * @param[out] pDst output pointer - * @param[in] blockSize number of samples to process - */ - void arm_copy_q31( - q31_t * pSrc, - q31_t * pDst, - uint32_t blockSize); - - - /** - * @brief Fills a constant value into a floating-point vector. - * @param[in] value input value to be filled - * @param[out] pDst output pointer - * @param[in] blockSize number of samples to process - */ - void arm_fill_f32( - float32_t value, - float32_t * pDst, - uint32_t blockSize); - - - /** - * @brief Fills a constant value into a Q7 vector. - * @param[in] value input value to be filled - * @param[out] pDst output pointer - * @param[in] blockSize number of samples to process - */ - void arm_fill_q7( - q7_t value, - q7_t * pDst, - uint32_t blockSize); - - - /** - * @brief Fills a constant value into a Q15 vector. - * @param[in] value input value to be filled - * @param[out] pDst output pointer - * @param[in] blockSize number of samples to process - */ - void arm_fill_q15( - q15_t value, - q15_t * pDst, - uint32_t blockSize); - - - /** - * @brief Fills a constant value into a Q31 vector. - * @param[in] value input value to be filled - * @param[out] pDst output pointer - * @param[in] blockSize number of samples to process - */ - void arm_fill_q31( - q31_t value, - q31_t * pDst, - uint32_t blockSize); - - -/** - * @brief Convolution of floating-point sequences. - * @param[in] pSrcA points to the first input sequence. - * @param[in] srcALen length of the first input sequence. - * @param[in] pSrcB points to the second input sequence. - * @param[in] srcBLen length of the second input sequence. - * @param[out] pDst points to the location where the output result is written. Length srcALen+srcBLen-1. - */ - void arm_conv_f32( - float32_t * pSrcA, - uint32_t srcALen, - float32_t * pSrcB, - uint32_t srcBLen, - float32_t * pDst); - - - /** - * @brief Convolution of Q15 sequences. - * @param[in] pSrcA points to the first input sequence. - * @param[in] srcALen length of the first input sequence. - * @param[in] pSrcB points to the second input sequence. - * @param[in] srcBLen length of the second input sequence. - * @param[out] pDst points to the block of output data Length srcALen+srcBLen-1. - * @param[in] pScratch1 points to scratch buffer of size max(srcALen, srcBLen) + 2*min(srcALen, srcBLen) - 2. - * @param[in] pScratch2 points to scratch buffer of size min(srcALen, srcBLen). - */ - void arm_conv_opt_q15( - q15_t * pSrcA, - uint32_t srcALen, - q15_t * pSrcB, - uint32_t srcBLen, - q15_t * pDst, - q15_t * pScratch1, - q15_t * pScratch2); - - -/** - * @brief Convolution of Q15 sequences. - * @param[in] pSrcA points to the first input sequence. - * @param[in] srcALen length of the first input sequence. - * @param[in] pSrcB points to the second input sequence. - * @param[in] srcBLen length of the second input sequence. - * @param[out] pDst points to the location where the output result is written. Length srcALen+srcBLen-1. - */ - void arm_conv_q15( - q15_t * pSrcA, - uint32_t srcALen, - q15_t * pSrcB, - uint32_t srcBLen, - q15_t * pDst); - - - /** - * @brief Convolution of Q15 sequences (fast version) for Cortex-M3 and Cortex-M4 - * @param[in] pSrcA points to the first input sequence. - * @param[in] srcALen length of the first input sequence. - * @param[in] pSrcB points to the second input sequence. - * @param[in] srcBLen length of the second input sequence. - * @param[out] pDst points to the block of output data Length srcALen+srcBLen-1. - */ - void arm_conv_fast_q15( - q15_t * pSrcA, - uint32_t srcALen, - q15_t * pSrcB, - uint32_t srcBLen, - q15_t * pDst); - - - /** - * @brief Convolution of Q15 sequences (fast version) for Cortex-M3 and Cortex-M4 - * @param[in] pSrcA points to the first input sequence. - * @param[in] srcALen length of the first input sequence. - * @param[in] pSrcB points to the second input sequence. - * @param[in] srcBLen length of the second input sequence. - * @param[out] pDst points to the block of output data Length srcALen+srcBLen-1. - * @param[in] pScratch1 points to scratch buffer of size max(srcALen, srcBLen) + 2*min(srcALen, srcBLen) - 2. - * @param[in] pScratch2 points to scratch buffer of size min(srcALen, srcBLen). - */ - void arm_conv_fast_opt_q15( - q15_t * pSrcA, - uint32_t srcALen, - q15_t * pSrcB, - uint32_t srcBLen, - q15_t * pDst, - q15_t * pScratch1, - q15_t * pScratch2); - - - /** - * @brief Convolution of Q31 sequences. - * @param[in] pSrcA points to the first input sequence. - * @param[in] srcALen length of the first input sequence. - * @param[in] pSrcB points to the second input sequence. - * @param[in] srcBLen length of the second input sequence. - * @param[out] pDst points to the block of output data Length srcALen+srcBLen-1. - */ - void arm_conv_q31( - q31_t * pSrcA, - uint32_t srcALen, - q31_t * pSrcB, - uint32_t srcBLen, - q31_t * pDst); - - - /** - * @brief Convolution of Q31 sequences (fast version) for Cortex-M3 and Cortex-M4 - * @param[in] pSrcA points to the first input sequence. - * @param[in] srcALen length of the first input sequence. - * @param[in] pSrcB points to the second input sequence. - * @param[in] srcBLen length of the second input sequence. - * @param[out] pDst points to the block of output data Length srcALen+srcBLen-1. - */ - void arm_conv_fast_q31( - q31_t * pSrcA, - uint32_t srcALen, - q31_t * pSrcB, - uint32_t srcBLen, - q31_t * pDst); - - - /** - * @brief Convolution of Q7 sequences. - * @param[in] pSrcA points to the first input sequence. - * @param[in] srcALen length of the first input sequence. - * @param[in] pSrcB points to the second input sequence. - * @param[in] srcBLen length of the second input sequence. - * @param[out] pDst points to the block of output data Length srcALen+srcBLen-1. - * @param[in] pScratch1 points to scratch buffer(of type q15_t) of size max(srcALen, srcBLen) + 2*min(srcALen, srcBLen) - 2. - * @param[in] pScratch2 points to scratch buffer (of type q15_t) of size min(srcALen, srcBLen). - */ - void arm_conv_opt_q7( - q7_t * pSrcA, - uint32_t srcALen, - q7_t * pSrcB, - uint32_t srcBLen, - q7_t * pDst, - q15_t * pScratch1, - q15_t * pScratch2); - - - /** - * @brief Convolution of Q7 sequences. - * @param[in] pSrcA points to the first input sequence. - * @param[in] srcALen length of the first input sequence. - * @param[in] pSrcB points to the second input sequence. - * @param[in] srcBLen length of the second input sequence. - * @param[out] pDst points to the block of output data Length srcALen+srcBLen-1. - */ - void arm_conv_q7( - q7_t * pSrcA, - uint32_t srcALen, - q7_t * pSrcB, - uint32_t srcBLen, - q7_t * pDst); - - - /** - * @brief Partial convolution of floating-point sequences. - * @param[in] pSrcA points to the first input sequence. - * @param[in] srcALen length of the first input sequence. - * @param[in] pSrcB points to the second input sequence. - * @param[in] srcBLen length of the second input sequence. - * @param[out] pDst points to the block of output data - * @param[in] firstIndex is the first output sample to start with. - * @param[in] numPoints is the number of output points to be computed. - * @return Returns either ARM_MATH_SUCCESS if the function completed correctly or ARM_MATH_ARGUMENT_ERROR if the requested subset is not in the range [0 srcALen+srcBLen-2]. - */ - arm_status arm_conv_partial_f32( - float32_t * pSrcA, - uint32_t srcALen, - float32_t * pSrcB, - uint32_t srcBLen, - float32_t * pDst, - uint32_t firstIndex, - uint32_t numPoints); - - - /** - * @brief Partial convolution of Q15 sequences. - * @param[in] pSrcA points to the first input sequence. - * @param[in] srcALen length of the first input sequence. - * @param[in] pSrcB points to the second input sequence. - * @param[in] srcBLen length of the second input sequence. - * @param[out] pDst points to the block of output data - * @param[in] firstIndex is the first output sample to start with. - * @param[in] numPoints is the number of output points to be computed. - * @param[in] pScratch1 points to scratch buffer of size max(srcALen, srcBLen) + 2*min(srcALen, srcBLen) - 2. - * @param[in] pScratch2 points to scratch buffer of size min(srcALen, srcBLen). - * @return Returns either ARM_MATH_SUCCESS if the function completed correctly or ARM_MATH_ARGUMENT_ERROR if the requested subset is not in the range [0 srcALen+srcBLen-2]. - */ - arm_status arm_conv_partial_opt_q15( - q15_t * pSrcA, - uint32_t srcALen, - q15_t * pSrcB, - uint32_t srcBLen, - q15_t * pDst, - uint32_t firstIndex, - uint32_t numPoints, - q15_t * pScratch1, - q15_t * pScratch2); - - - /** - * @brief Partial convolution of Q15 sequences. - * @param[in] pSrcA points to the first input sequence. - * @param[in] srcALen length of the first input sequence. - * @param[in] pSrcB points to the second input sequence. - * @param[in] srcBLen length of the second input sequence. - * @param[out] pDst points to the block of output data - * @param[in] firstIndex is the first output sample to start with. - * @param[in] numPoints is the number of output points to be computed. - * @return Returns either ARM_MATH_SUCCESS if the function completed correctly or ARM_MATH_ARGUMENT_ERROR if the requested subset is not in the range [0 srcALen+srcBLen-2]. - */ - arm_status arm_conv_partial_q15( - q15_t * pSrcA, - uint32_t srcALen, - q15_t * pSrcB, - uint32_t srcBLen, - q15_t * pDst, - uint32_t firstIndex, - uint32_t numPoints); - - - /** - * @brief Partial convolution of Q15 sequences (fast version) for Cortex-M3 and Cortex-M4 - * @param[in] pSrcA points to the first input sequence. - * @param[in] srcALen length of the first input sequence. - * @param[in] pSrcB points to the second input sequence. - * @param[in] srcBLen length of the second input sequence. - * @param[out] pDst points to the block of output data - * @param[in] firstIndex is the first output sample to start with. - * @param[in] numPoints is the number of output points to be computed. - * @return Returns either ARM_MATH_SUCCESS if the function completed correctly or ARM_MATH_ARGUMENT_ERROR if the requested subset is not in the range [0 srcALen+srcBLen-2]. - */ - arm_status arm_conv_partial_fast_q15( - q15_t * pSrcA, - uint32_t srcALen, - q15_t * pSrcB, - uint32_t srcBLen, - q15_t * pDst, - uint32_t firstIndex, - uint32_t numPoints); - - - /** - * @brief Partial convolution of Q15 sequences (fast version) for Cortex-M3 and Cortex-M4 - * @param[in] pSrcA points to the first input sequence. - * @param[in] srcALen length of the first input sequence. - * @param[in] pSrcB points to the second input sequence. - * @param[in] srcBLen length of the second input sequence. - * @param[out] pDst points to the block of output data - * @param[in] firstIndex is the first output sample to start with. - * @param[in] numPoints is the number of output points to be computed. - * @param[in] pScratch1 points to scratch buffer of size max(srcALen, srcBLen) + 2*min(srcALen, srcBLen) - 2. - * @param[in] pScratch2 points to scratch buffer of size min(srcALen, srcBLen). - * @return Returns either ARM_MATH_SUCCESS if the function completed correctly or ARM_MATH_ARGUMENT_ERROR if the requested subset is not in the range [0 srcALen+srcBLen-2]. - */ - arm_status arm_conv_partial_fast_opt_q15( - q15_t * pSrcA, - uint32_t srcALen, - q15_t * pSrcB, - uint32_t srcBLen, - q15_t * pDst, - uint32_t firstIndex, - uint32_t numPoints, - q15_t * pScratch1, - q15_t * pScratch2); - - - /** - * @brief Partial convolution of Q31 sequences. - * @param[in] pSrcA points to the first input sequence. - * @param[in] srcALen length of the first input sequence. - * @param[in] pSrcB points to the second input sequence. - * @param[in] srcBLen length of the second input sequence. - * @param[out] pDst points to the block of output data - * @param[in] firstIndex is the first output sample to start with. - * @param[in] numPoints is the number of output points to be computed. - * @return Returns either ARM_MATH_SUCCESS if the function completed correctly or ARM_MATH_ARGUMENT_ERROR if the requested subset is not in the range [0 srcALen+srcBLen-2]. - */ - arm_status arm_conv_partial_q31( - q31_t * pSrcA, - uint32_t srcALen, - q31_t * pSrcB, - uint32_t srcBLen, - q31_t * pDst, - uint32_t firstIndex, - uint32_t numPoints); - - - /** - * @brief Partial convolution of Q31 sequences (fast version) for Cortex-M3 and Cortex-M4 - * @param[in] pSrcA points to the first input sequence. - * @param[in] srcALen length of the first input sequence. - * @param[in] pSrcB points to the second input sequence. - * @param[in] srcBLen length of the second input sequence. - * @param[out] pDst points to the block of output data - * @param[in] firstIndex is the first output sample to start with. - * @param[in] numPoints is the number of output points to be computed. - * @return Returns either ARM_MATH_SUCCESS if the function completed correctly or ARM_MATH_ARGUMENT_ERROR if the requested subset is not in the range [0 srcALen+srcBLen-2]. - */ - arm_status arm_conv_partial_fast_q31( - q31_t * pSrcA, - uint32_t srcALen, - q31_t * pSrcB, - uint32_t srcBLen, - q31_t * pDst, - uint32_t firstIndex, - uint32_t numPoints); - - - /** - * @brief Partial convolution of Q7 sequences - * @param[in] pSrcA points to the first input sequence. - * @param[in] srcALen length of the first input sequence. - * @param[in] pSrcB points to the second input sequence. - * @param[in] srcBLen length of the second input sequence. - * @param[out] pDst points to the block of output data - * @param[in] firstIndex is the first output sample to start with. - * @param[in] numPoints is the number of output points to be computed. - * @param[in] pScratch1 points to scratch buffer(of type q15_t) of size max(srcALen, srcBLen) + 2*min(srcALen, srcBLen) - 2. - * @param[in] pScratch2 points to scratch buffer (of type q15_t) of size min(srcALen, srcBLen). - * @return Returns either ARM_MATH_SUCCESS if the function completed correctly or ARM_MATH_ARGUMENT_ERROR if the requested subset is not in the range [0 srcALen+srcBLen-2]. - */ - arm_status arm_conv_partial_opt_q7( - q7_t * pSrcA, - uint32_t srcALen, - q7_t * pSrcB, - uint32_t srcBLen, - q7_t * pDst, - uint32_t firstIndex, - uint32_t numPoints, - q15_t * pScratch1, - q15_t * pScratch2); - - -/** - * @brief Partial convolution of Q7 sequences. - * @param[in] pSrcA points to the first input sequence. - * @param[in] srcALen length of the first input sequence. - * @param[in] pSrcB points to the second input sequence. - * @param[in] srcBLen length of the second input sequence. - * @param[out] pDst points to the block of output data - * @param[in] firstIndex is the first output sample to start with. - * @param[in] numPoints is the number of output points to be computed. - * @return Returns either ARM_MATH_SUCCESS if the function completed correctly or ARM_MATH_ARGUMENT_ERROR if the requested subset is not in the range [0 srcALen+srcBLen-2]. - */ - arm_status arm_conv_partial_q7( - q7_t * pSrcA, - uint32_t srcALen, - q7_t * pSrcB, - uint32_t srcBLen, - q7_t * pDst, - uint32_t firstIndex, - uint32_t numPoints); - - - /** - * @brief Instance structure for the Q15 FIR decimator. - */ - typedef struct - { - uint8_t M; /**< decimation factor. */ - uint16_t numTaps; /**< number of coefficients in the filter. */ - q15_t *pCoeffs; /**< points to the coefficient array. The array is of length numTaps.*/ - q15_t *pState; /**< points to the state variable array. The array is of length numTaps+blockSize-1. */ - } arm_fir_decimate_instance_q15; - - /** - * @brief Instance structure for the Q31 FIR decimator. - */ - typedef struct - { - uint8_t M; /**< decimation factor. */ - uint16_t numTaps; /**< number of coefficients in the filter. */ - q31_t *pCoeffs; /**< points to the coefficient array. The array is of length numTaps.*/ - q31_t *pState; /**< points to the state variable array. The array is of length numTaps+blockSize-1. */ - } arm_fir_decimate_instance_q31; - - /** - * @brief Instance structure for the floating-point FIR decimator. - */ - typedef struct - { - uint8_t M; /**< decimation factor. */ - uint16_t numTaps; /**< number of coefficients in the filter. */ - float32_t *pCoeffs; /**< points to the coefficient array. The array is of length numTaps.*/ - float32_t *pState; /**< points to the state variable array. The array is of length numTaps+blockSize-1. */ - } arm_fir_decimate_instance_f32; - - - /** - * @brief Processing function for the floating-point FIR decimator. - * @param[in] S points to an instance of the floating-point FIR decimator structure. - * @param[in] pSrc points to the block of input data. - * @param[out] pDst points to the block of output data - * @param[in] blockSize number of input samples to process per call. - */ - void arm_fir_decimate_f32( - const arm_fir_decimate_instance_f32 * S, - float32_t * pSrc, - float32_t * pDst, - uint32_t blockSize); - - - /** - * @brief Initialization function for the floating-point FIR decimator. - * @param[in,out] S points to an instance of the floating-point FIR decimator structure. - * @param[in] numTaps number of coefficients in the filter. - * @param[in] M decimation factor. - * @param[in] pCoeffs points to the filter coefficients. - * @param[in] pState points to the state buffer. - * @param[in] blockSize number of input samples to process per call. - * @return The function returns ARM_MATH_SUCCESS if initialization is successful or ARM_MATH_LENGTH_ERROR if - * blockSize is not a multiple of M. - */ - arm_status arm_fir_decimate_init_f32( - arm_fir_decimate_instance_f32 * S, - uint16_t numTaps, - uint8_t M, - float32_t * pCoeffs, - float32_t * pState, - uint32_t blockSize); - - - /** - * @brief Processing function for the Q15 FIR decimator. - * @param[in] S points to an instance of the Q15 FIR decimator structure. - * @param[in] pSrc points to the block of input data. - * @param[out] pDst points to the block of output data - * @param[in] blockSize number of input samples to process per call. - */ - void arm_fir_decimate_q15( - const arm_fir_decimate_instance_q15 * S, - q15_t * pSrc, - q15_t * pDst, - uint32_t blockSize); - - - /** - * @brief Processing function for the Q15 FIR decimator (fast variant) for Cortex-M3 and Cortex-M4. - * @param[in] S points to an instance of the Q15 FIR decimator structure. - * @param[in] pSrc points to the block of input data. - * @param[out] pDst points to the block of output data - * @param[in] blockSize number of input samples to process per call. - */ - void arm_fir_decimate_fast_q15( - const arm_fir_decimate_instance_q15 * S, - q15_t * pSrc, - q15_t * pDst, - uint32_t blockSize); - - - /** - * @brief Initialization function for the Q15 FIR decimator. - * @param[in,out] S points to an instance of the Q15 FIR decimator structure. - * @param[in] numTaps number of coefficients in the filter. - * @param[in] M decimation factor. - * @param[in] pCoeffs points to the filter coefficients. - * @param[in] pState points to the state buffer. - * @param[in] blockSize number of input samples to process per call. - * @return The function returns ARM_MATH_SUCCESS if initialization is successful or ARM_MATH_LENGTH_ERROR if - * blockSize is not a multiple of M. - */ - arm_status arm_fir_decimate_init_q15( - arm_fir_decimate_instance_q15 * S, - uint16_t numTaps, - uint8_t M, - q15_t * pCoeffs, - q15_t * pState, - uint32_t blockSize); - - - /** - * @brief Processing function for the Q31 FIR decimator. - * @param[in] S points to an instance of the Q31 FIR decimator structure. - * @param[in] pSrc points to the block of input data. - * @param[out] pDst points to the block of output data - * @param[in] blockSize number of input samples to process per call. - */ - void arm_fir_decimate_q31( - const arm_fir_decimate_instance_q31 * S, - q31_t * pSrc, - q31_t * pDst, - uint32_t blockSize); - - /** - * @brief Processing function for the Q31 FIR decimator (fast variant) for Cortex-M3 and Cortex-M4. - * @param[in] S points to an instance of the Q31 FIR decimator structure. - * @param[in] pSrc points to the block of input data. - * @param[out] pDst points to the block of output data - * @param[in] blockSize number of input samples to process per call. - */ - void arm_fir_decimate_fast_q31( - arm_fir_decimate_instance_q31 * S, - q31_t * pSrc, - q31_t * pDst, - uint32_t blockSize); - - - /** - * @brief Initialization function for the Q31 FIR decimator. - * @param[in,out] S points to an instance of the Q31 FIR decimator structure. - * @param[in] numTaps number of coefficients in the filter. - * @param[in] M decimation factor. - * @param[in] pCoeffs points to the filter coefficients. - * @param[in] pState points to the state buffer. - * @param[in] blockSize number of input samples to process per call. - * @return The function returns ARM_MATH_SUCCESS if initialization is successful or ARM_MATH_LENGTH_ERROR if - * blockSize is not a multiple of M. - */ - arm_status arm_fir_decimate_init_q31( - arm_fir_decimate_instance_q31 * S, - uint16_t numTaps, - uint8_t M, - q31_t * pCoeffs, - q31_t * pState, - uint32_t blockSize); - - - /** - * @brief Instance structure for the Q15 FIR interpolator. - */ - typedef struct - { - uint8_t L; /**< upsample factor. */ - uint16_t phaseLength; /**< length of each polyphase filter component. */ - q15_t *pCoeffs; /**< points to the coefficient array. The array is of length L*phaseLength. */ - q15_t *pState; /**< points to the state variable array. The array is of length blockSize+phaseLength-1. */ - } arm_fir_interpolate_instance_q15; - - /** - * @brief Instance structure for the Q31 FIR interpolator. - */ - typedef struct - { - uint8_t L; /**< upsample factor. */ - uint16_t phaseLength; /**< length of each polyphase filter component. */ - q31_t *pCoeffs; /**< points to the coefficient array. The array is of length L*phaseLength. */ - q31_t *pState; /**< points to the state variable array. The array is of length blockSize+phaseLength-1. */ - } arm_fir_interpolate_instance_q31; - - /** - * @brief Instance structure for the floating-point FIR interpolator. - */ - typedef struct - { - uint8_t L; /**< upsample factor. */ - uint16_t phaseLength; /**< length of each polyphase filter component. */ - float32_t *pCoeffs; /**< points to the coefficient array. The array is of length L*phaseLength. */ - float32_t *pState; /**< points to the state variable array. The array is of length phaseLength+numTaps-1. */ - } arm_fir_interpolate_instance_f32; - - - /** - * @brief Processing function for the Q15 FIR interpolator. - * @param[in] S points to an instance of the Q15 FIR interpolator structure. - * @param[in] pSrc points to the block of input data. - * @param[out] pDst points to the block of output data. - * @param[in] blockSize number of input samples to process per call. - */ - void arm_fir_interpolate_q15( - const arm_fir_interpolate_instance_q15 * S, - q15_t * pSrc, - q15_t * pDst, - uint32_t blockSize); - - - /** - * @brief Initialization function for the Q15 FIR interpolator. - * @param[in,out] S points to an instance of the Q15 FIR interpolator structure. - * @param[in] L upsample factor. - * @param[in] numTaps number of filter coefficients in the filter. - * @param[in] pCoeffs points to the filter coefficient buffer. - * @param[in] pState points to the state buffer. - * @param[in] blockSize number of input samples to process per call. - * @return The function returns ARM_MATH_SUCCESS if initialization is successful or ARM_MATH_LENGTH_ERROR if - * the filter length numTaps is not a multiple of the interpolation factor L. - */ - arm_status arm_fir_interpolate_init_q15( - arm_fir_interpolate_instance_q15 * S, - uint8_t L, - uint16_t numTaps, - q15_t * pCoeffs, - q15_t * pState, - uint32_t blockSize); - - - /** - * @brief Processing function for the Q31 FIR interpolator. - * @param[in] S points to an instance of the Q15 FIR interpolator structure. - * @param[in] pSrc points to the block of input data. - * @param[out] pDst points to the block of output data. - * @param[in] blockSize number of input samples to process per call. - */ - void arm_fir_interpolate_q31( - const arm_fir_interpolate_instance_q31 * S, - q31_t * pSrc, - q31_t * pDst, - uint32_t blockSize); - - - /** - * @brief Initialization function for the Q31 FIR interpolator. - * @param[in,out] S points to an instance of the Q31 FIR interpolator structure. - * @param[in] L upsample factor. - * @param[in] numTaps number of filter coefficients in the filter. - * @param[in] pCoeffs points to the filter coefficient buffer. - * @param[in] pState points to the state buffer. - * @param[in] blockSize number of input samples to process per call. - * @return The function returns ARM_MATH_SUCCESS if initialization is successful or ARM_MATH_LENGTH_ERROR if - * the filter length numTaps is not a multiple of the interpolation factor L. - */ - arm_status arm_fir_interpolate_init_q31( - arm_fir_interpolate_instance_q31 * S, - uint8_t L, - uint16_t numTaps, - q31_t * pCoeffs, - q31_t * pState, - uint32_t blockSize); - - - /** - * @brief Processing function for the floating-point FIR interpolator. - * @param[in] S points to an instance of the floating-point FIR interpolator structure. - * @param[in] pSrc points to the block of input data. - * @param[out] pDst points to the block of output data. - * @param[in] blockSize number of input samples to process per call. - */ - void arm_fir_interpolate_f32( - const arm_fir_interpolate_instance_f32 * S, - float32_t * pSrc, - float32_t * pDst, - uint32_t blockSize); - - - /** - * @brief Initialization function for the floating-point FIR interpolator. - * @param[in,out] S points to an instance of the floating-point FIR interpolator structure. - * @param[in] L upsample factor. - * @param[in] numTaps number of filter coefficients in the filter. - * @param[in] pCoeffs points to the filter coefficient buffer. - * @param[in] pState points to the state buffer. - * @param[in] blockSize number of input samples to process per call. - * @return The function returns ARM_MATH_SUCCESS if initialization is successful or ARM_MATH_LENGTH_ERROR if - * the filter length numTaps is not a multiple of the interpolation factor L. - */ - arm_status arm_fir_interpolate_init_f32( - arm_fir_interpolate_instance_f32 * S, - uint8_t L, - uint16_t numTaps, - float32_t * pCoeffs, - float32_t * pState, - uint32_t blockSize); - - - /** - * @brief Instance structure for the high precision Q31 Biquad cascade filter. - */ - typedef struct - { - uint8_t numStages; /**< number of 2nd order stages in the filter. Overall order is 2*numStages. */ - q63_t *pState; /**< points to the array of state coefficients. The array is of length 4*numStages. */ - q31_t *pCoeffs; /**< points to the array of coefficients. The array is of length 5*numStages. */ - uint8_t postShift; /**< additional shift, in bits, applied to each output sample. */ - } arm_biquad_cas_df1_32x64_ins_q31; - - - /** - * @param[in] S points to an instance of the high precision Q31 Biquad cascade filter structure. - * @param[in] pSrc points to the block of input data. - * @param[out] pDst points to the block of output data - * @param[in] blockSize number of samples to process. - */ - void arm_biquad_cas_df1_32x64_q31( - const arm_biquad_cas_df1_32x64_ins_q31 * S, - q31_t * pSrc, - q31_t * pDst, - uint32_t blockSize); - - - /** - * @param[in,out] S points to an instance of the high precision Q31 Biquad cascade filter structure. - * @param[in] numStages number of 2nd order stages in the filter. - * @param[in] pCoeffs points to the filter coefficients. - * @param[in] pState points to the state buffer. - * @param[in] postShift shift to be applied to the output. Varies according to the coefficients format - */ - void arm_biquad_cas_df1_32x64_init_q31( - arm_biquad_cas_df1_32x64_ins_q31 * S, - uint8_t numStages, - q31_t * pCoeffs, - q63_t * pState, - uint8_t postShift); - - - /** - * @brief Instance structure for the floating-point transposed direct form II Biquad cascade filter. - */ - typedef struct - { - uint8_t numStages; /**< number of 2nd order stages in the filter. Overall order is 2*numStages. */ - float32_t *pState; /**< points to the array of state coefficients. The array is of length 2*numStages. */ - float32_t *pCoeffs; /**< points to the array of coefficients. The array is of length 5*numStages. */ - } arm_biquad_cascade_df2T_instance_f32; - - /** - * @brief Instance structure for the floating-point transposed direct form II Biquad cascade filter. - */ - typedef struct - { - uint8_t numStages; /**< number of 2nd order stages in the filter. Overall order is 2*numStages. */ - float32_t *pState; /**< points to the array of state coefficients. The array is of length 4*numStages. */ - float32_t *pCoeffs; /**< points to the array of coefficients. The array is of length 5*numStages. */ - } arm_biquad_cascade_stereo_df2T_instance_f32; - - /** - * @brief Instance structure for the floating-point transposed direct form II Biquad cascade filter. - */ - typedef struct - { - uint8_t numStages; /**< number of 2nd order stages in the filter. Overall order is 2*numStages. */ - float64_t *pState; /**< points to the array of state coefficients. The array is of length 2*numStages. */ - float64_t *pCoeffs; /**< points to the array of coefficients. The array is of length 5*numStages. */ - } arm_biquad_cascade_df2T_instance_f64; - - - /** - * @brief Processing function for the floating-point transposed direct form II Biquad cascade filter. - * @param[in] S points to an instance of the filter data structure. - * @param[in] pSrc points to the block of input data. - * @param[out] pDst points to the block of output data - * @param[in] blockSize number of samples to process. - */ - void arm_biquad_cascade_df2T_f32( - const arm_biquad_cascade_df2T_instance_f32 * S, - float32_t * pSrc, - float32_t * pDst, - uint32_t blockSize); - - - /** - * @brief Processing function for the floating-point transposed direct form II Biquad cascade filter. 2 channels - * @param[in] S points to an instance of the filter data structure. - * @param[in] pSrc points to the block of input data. - * @param[out] pDst points to the block of output data - * @param[in] blockSize number of samples to process. - */ - void arm_biquad_cascade_stereo_df2T_f32( - const arm_biquad_cascade_stereo_df2T_instance_f32 * S, - float32_t * pSrc, - float32_t * pDst, - uint32_t blockSize); - - - /** - * @brief Processing function for the floating-point transposed direct form II Biquad cascade filter. - * @param[in] S points to an instance of the filter data structure. - * @param[in] pSrc points to the block of input data. - * @param[out] pDst points to the block of output data - * @param[in] blockSize number of samples to process. - */ - void arm_biquad_cascade_df2T_f64( - const arm_biquad_cascade_df2T_instance_f64 * S, - float64_t * pSrc, - float64_t * pDst, - uint32_t blockSize); - - - /** - * @brief Initialization function for the floating-point transposed direct form II Biquad cascade filter. - * @param[in,out] S points to an instance of the filter data structure. - * @param[in] numStages number of 2nd order stages in the filter. - * @param[in] pCoeffs points to the filter coefficients. - * @param[in] pState points to the state buffer. - */ - void arm_biquad_cascade_df2T_init_f32( - arm_biquad_cascade_df2T_instance_f32 * S, - uint8_t numStages, - float32_t * pCoeffs, - float32_t * pState); - - - /** - * @brief Initialization function for the floating-point transposed direct form II Biquad cascade filter. - * @param[in,out] S points to an instance of the filter data structure. - * @param[in] numStages number of 2nd order stages in the filter. - * @param[in] pCoeffs points to the filter coefficients. - * @param[in] pState points to the state buffer. - */ - void arm_biquad_cascade_stereo_df2T_init_f32( - arm_biquad_cascade_stereo_df2T_instance_f32 * S, - uint8_t numStages, - float32_t * pCoeffs, - float32_t * pState); - - - /** - * @brief Initialization function for the floating-point transposed direct form II Biquad cascade filter. - * @param[in,out] S points to an instance of the filter data structure. - * @param[in] numStages number of 2nd order stages in the filter. - * @param[in] pCoeffs points to the filter coefficients. - * @param[in] pState points to the state buffer. - */ - void arm_biquad_cascade_df2T_init_f64( - arm_biquad_cascade_df2T_instance_f64 * S, - uint8_t numStages, - float64_t * pCoeffs, - float64_t * pState); - - - /** - * @brief Instance structure for the Q15 FIR lattice filter. - */ - typedef struct - { - uint16_t numStages; /**< number of filter stages. */ - q15_t *pState; /**< points to the state variable array. The array is of length numStages. */ - q15_t *pCoeffs; /**< points to the coefficient array. The array is of length numStages. */ - } arm_fir_lattice_instance_q15; - - /** - * @brief Instance structure for the Q31 FIR lattice filter. - */ - typedef struct - { - uint16_t numStages; /**< number of filter stages. */ - q31_t *pState; /**< points to the state variable array. The array is of length numStages. */ - q31_t *pCoeffs; /**< points to the coefficient array. The array is of length numStages. */ - } arm_fir_lattice_instance_q31; - - /** - * @brief Instance structure for the floating-point FIR lattice filter. - */ - typedef struct - { - uint16_t numStages; /**< number of filter stages. */ - float32_t *pState; /**< points to the state variable array. The array is of length numStages. */ - float32_t *pCoeffs; /**< points to the coefficient array. The array is of length numStages. */ - } arm_fir_lattice_instance_f32; - - - /** - * @brief Initialization function for the Q15 FIR lattice filter. - * @param[in] S points to an instance of the Q15 FIR lattice structure. - * @param[in] numStages number of filter stages. - * @param[in] pCoeffs points to the coefficient buffer. The array is of length numStages. - * @param[in] pState points to the state buffer. The array is of length numStages. - */ - void arm_fir_lattice_init_q15( - arm_fir_lattice_instance_q15 * S, - uint16_t numStages, - q15_t * pCoeffs, - q15_t * pState); - - - /** - * @brief Processing function for the Q15 FIR lattice filter. - * @param[in] S points to an instance of the Q15 FIR lattice structure. - * @param[in] pSrc points to the block of input data. - * @param[out] pDst points to the block of output data. - * @param[in] blockSize number of samples to process. - */ - void arm_fir_lattice_q15( - const arm_fir_lattice_instance_q15 * S, - q15_t * pSrc, - q15_t * pDst, - uint32_t blockSize); - - - /** - * @brief Initialization function for the Q31 FIR lattice filter. - * @param[in] S points to an instance of the Q31 FIR lattice structure. - * @param[in] numStages number of filter stages. - * @param[in] pCoeffs points to the coefficient buffer. The array is of length numStages. - * @param[in] pState points to the state buffer. The array is of length numStages. - */ - void arm_fir_lattice_init_q31( - arm_fir_lattice_instance_q31 * S, - uint16_t numStages, - q31_t * pCoeffs, - q31_t * pState); - - - /** - * @brief Processing function for the Q31 FIR lattice filter. - * @param[in] S points to an instance of the Q31 FIR lattice structure. - * @param[in] pSrc points to the block of input data. - * @param[out] pDst points to the block of output data - * @param[in] blockSize number of samples to process. - */ - void arm_fir_lattice_q31( - const arm_fir_lattice_instance_q31 * S, - q31_t * pSrc, - q31_t * pDst, - uint32_t blockSize); - - -/** - * @brief Initialization function for the floating-point FIR lattice filter. - * @param[in] S points to an instance of the floating-point FIR lattice structure. - * @param[in] numStages number of filter stages. - * @param[in] pCoeffs points to the coefficient buffer. The array is of length numStages. - * @param[in] pState points to the state buffer. The array is of length numStages. - */ - void arm_fir_lattice_init_f32( - arm_fir_lattice_instance_f32 * S, - uint16_t numStages, - float32_t * pCoeffs, - float32_t * pState); - - - /** - * @brief Processing function for the floating-point FIR lattice filter. - * @param[in] S points to an instance of the floating-point FIR lattice structure. - * @param[in] pSrc points to the block of input data. - * @param[out] pDst points to the block of output data - * @param[in] blockSize number of samples to process. - */ - void arm_fir_lattice_f32( - const arm_fir_lattice_instance_f32 * S, - float32_t * pSrc, - float32_t * pDst, - uint32_t blockSize); - - - /** - * @brief Instance structure for the Q15 IIR lattice filter. - */ - typedef struct - { - uint16_t numStages; /**< number of stages in the filter. */ - q15_t *pState; /**< points to the state variable array. The array is of length numStages+blockSize. */ - q15_t *pkCoeffs; /**< points to the reflection coefficient array. The array is of length numStages. */ - q15_t *pvCoeffs; /**< points to the ladder coefficient array. The array is of length numStages+1. */ - } arm_iir_lattice_instance_q15; - - /** - * @brief Instance structure for the Q31 IIR lattice filter. - */ - typedef struct - { - uint16_t numStages; /**< number of stages in the filter. */ - q31_t *pState; /**< points to the state variable array. The array is of length numStages+blockSize. */ - q31_t *pkCoeffs; /**< points to the reflection coefficient array. The array is of length numStages. */ - q31_t *pvCoeffs; /**< points to the ladder coefficient array. The array is of length numStages+1. */ - } arm_iir_lattice_instance_q31; - - /** - * @brief Instance structure for the floating-point IIR lattice filter. - */ - typedef struct - { - uint16_t numStages; /**< number of stages in the filter. */ - float32_t *pState; /**< points to the state variable array. The array is of length numStages+blockSize. */ - float32_t *pkCoeffs; /**< points to the reflection coefficient array. The array is of length numStages. */ - float32_t *pvCoeffs; /**< points to the ladder coefficient array. The array is of length numStages+1. */ - } arm_iir_lattice_instance_f32; - - - /** - * @brief Processing function for the floating-point IIR lattice filter. - * @param[in] S points to an instance of the floating-point IIR lattice structure. - * @param[in] pSrc points to the block of input data. - * @param[out] pDst points to the block of output data. - * @param[in] blockSize number of samples to process. - */ - void arm_iir_lattice_f32( - const arm_iir_lattice_instance_f32 * S, - float32_t * pSrc, - float32_t * pDst, - uint32_t blockSize); - - - /** - * @brief Initialization function for the floating-point IIR lattice filter. - * @param[in] S points to an instance of the floating-point IIR lattice structure. - * @param[in] numStages number of stages in the filter. - * @param[in] pkCoeffs points to the reflection coefficient buffer. The array is of length numStages. - * @param[in] pvCoeffs points to the ladder coefficient buffer. The array is of length numStages+1. - * @param[in] pState points to the state buffer. The array is of length numStages+blockSize-1. - * @param[in] blockSize number of samples to process. - */ - void arm_iir_lattice_init_f32( - arm_iir_lattice_instance_f32 * S, - uint16_t numStages, - float32_t * pkCoeffs, - float32_t * pvCoeffs, - float32_t * pState, - uint32_t blockSize); - - - /** - * @brief Processing function for the Q31 IIR lattice filter. - * @param[in] S points to an instance of the Q31 IIR lattice structure. - * @param[in] pSrc points to the block of input data. - * @param[out] pDst points to the block of output data. - * @param[in] blockSize number of samples to process. - */ - void arm_iir_lattice_q31( - const arm_iir_lattice_instance_q31 * S, - q31_t * pSrc, - q31_t * pDst, - uint32_t blockSize); - - - /** - * @brief Initialization function for the Q31 IIR lattice filter. - * @param[in] S points to an instance of the Q31 IIR lattice structure. - * @param[in] numStages number of stages in the filter. - * @param[in] pkCoeffs points to the reflection coefficient buffer. The array is of length numStages. - * @param[in] pvCoeffs points to the ladder coefficient buffer. The array is of length numStages+1. - * @param[in] pState points to the state buffer. The array is of length numStages+blockSize. - * @param[in] blockSize number of samples to process. - */ - void arm_iir_lattice_init_q31( - arm_iir_lattice_instance_q31 * S, - uint16_t numStages, - q31_t * pkCoeffs, - q31_t * pvCoeffs, - q31_t * pState, - uint32_t blockSize); - - - /** - * @brief Processing function for the Q15 IIR lattice filter. - * @param[in] S points to an instance of the Q15 IIR lattice structure. - * @param[in] pSrc points to the block of input data. - * @param[out] pDst points to the block of output data. - * @param[in] blockSize number of samples to process. - */ - void arm_iir_lattice_q15( - const arm_iir_lattice_instance_q15 * S, - q15_t * pSrc, - q15_t * pDst, - uint32_t blockSize); - - -/** - * @brief Initialization function for the Q15 IIR lattice filter. - * @param[in] S points to an instance of the fixed-point Q15 IIR lattice structure. - * @param[in] numStages number of stages in the filter. - * @param[in] pkCoeffs points to reflection coefficient buffer. The array is of length numStages. - * @param[in] pvCoeffs points to ladder coefficient buffer. The array is of length numStages+1. - * @param[in] pState points to state buffer. The array is of length numStages+blockSize. - * @param[in] blockSize number of samples to process per call. - */ - void arm_iir_lattice_init_q15( - arm_iir_lattice_instance_q15 * S, - uint16_t numStages, - q15_t * pkCoeffs, - q15_t * pvCoeffs, - q15_t * pState, - uint32_t blockSize); - - - /** - * @brief Instance structure for the floating-point LMS filter. - */ - typedef struct - { - uint16_t numTaps; /**< number of coefficients in the filter. */ - float32_t *pState; /**< points to the state variable array. The array is of length numTaps+blockSize-1. */ - float32_t *pCoeffs; /**< points to the coefficient array. The array is of length numTaps. */ - float32_t mu; /**< step size that controls filter coefficient updates. */ - } arm_lms_instance_f32; - - - /** - * @brief Processing function for floating-point LMS filter. - * @param[in] S points to an instance of the floating-point LMS filter structure. - * @param[in] pSrc points to the block of input data. - * @param[in] pRef points to the block of reference data. - * @param[out] pOut points to the block of output data. - * @param[out] pErr points to the block of error data. - * @param[in] blockSize number of samples to process. - */ - void arm_lms_f32( - const arm_lms_instance_f32 * S, - float32_t * pSrc, - float32_t * pRef, - float32_t * pOut, - float32_t * pErr, - uint32_t blockSize); - - - /** - * @brief Initialization function for floating-point LMS filter. - * @param[in] S points to an instance of the floating-point LMS filter structure. - * @param[in] numTaps number of filter coefficients. - * @param[in] pCoeffs points to the coefficient buffer. - * @param[in] pState points to state buffer. - * @param[in] mu step size that controls filter coefficient updates. - * @param[in] blockSize number of samples to process. - */ - void arm_lms_init_f32( - arm_lms_instance_f32 * S, - uint16_t numTaps, - float32_t * pCoeffs, - float32_t * pState, - float32_t mu, - uint32_t blockSize); - - - /** - * @brief Instance structure for the Q15 LMS filter. - */ - typedef struct - { - uint16_t numTaps; /**< number of coefficients in the filter. */ - q15_t *pState; /**< points to the state variable array. The array is of length numTaps+blockSize-1. */ - q15_t *pCoeffs; /**< points to the coefficient array. The array is of length numTaps. */ - q15_t mu; /**< step size that controls filter coefficient updates. */ - uint32_t postShift; /**< bit shift applied to coefficients. */ - } arm_lms_instance_q15; - - - /** - * @brief Initialization function for the Q15 LMS filter. - * @param[in] S points to an instance of the Q15 LMS filter structure. - * @param[in] numTaps number of filter coefficients. - * @param[in] pCoeffs points to the coefficient buffer. - * @param[in] pState points to the state buffer. - * @param[in] mu step size that controls filter coefficient updates. - * @param[in] blockSize number of samples to process. - * @param[in] postShift bit shift applied to coefficients. - */ - void arm_lms_init_q15( - arm_lms_instance_q15 * S, - uint16_t numTaps, - q15_t * pCoeffs, - q15_t * pState, - q15_t mu, - uint32_t blockSize, - uint32_t postShift); - - - /** - * @brief Processing function for Q15 LMS filter. - * @param[in] S points to an instance of the Q15 LMS filter structure. - * @param[in] pSrc points to the block of input data. - * @param[in] pRef points to the block of reference data. - * @param[out] pOut points to the block of output data. - * @param[out] pErr points to the block of error data. - * @param[in] blockSize number of samples to process. - */ - void arm_lms_q15( - const arm_lms_instance_q15 * S, - q15_t * pSrc, - q15_t * pRef, - q15_t * pOut, - q15_t * pErr, - uint32_t blockSize); - - - /** - * @brief Instance structure for the Q31 LMS filter. - */ - typedef struct - { - uint16_t numTaps; /**< number of coefficients in the filter. */ - q31_t *pState; /**< points to the state variable array. The array is of length numTaps+blockSize-1. */ - q31_t *pCoeffs; /**< points to the coefficient array. The array is of length numTaps. */ - q31_t mu; /**< step size that controls filter coefficient updates. */ - uint32_t postShift; /**< bit shift applied to coefficients. */ - } arm_lms_instance_q31; - - - /** - * @brief Processing function for Q31 LMS filter. - * @param[in] S points to an instance of the Q15 LMS filter structure. - * @param[in] pSrc points to the block of input data. - * @param[in] pRef points to the block of reference data. - * @param[out] pOut points to the block of output data. - * @param[out] pErr points to the block of error data. - * @param[in] blockSize number of samples to process. - */ - void arm_lms_q31( - const arm_lms_instance_q31 * S, - q31_t * pSrc, - q31_t * pRef, - q31_t * pOut, - q31_t * pErr, - uint32_t blockSize); - - - /** - * @brief Initialization function for Q31 LMS filter. - * @param[in] S points to an instance of the Q31 LMS filter structure. - * @param[in] numTaps number of filter coefficients. - * @param[in] pCoeffs points to coefficient buffer. - * @param[in] pState points to state buffer. - * @param[in] mu step size that controls filter coefficient updates. - * @param[in] blockSize number of samples to process. - * @param[in] postShift bit shift applied to coefficients. - */ - void arm_lms_init_q31( - arm_lms_instance_q31 * S, - uint16_t numTaps, - q31_t * pCoeffs, - q31_t * pState, - q31_t mu, - uint32_t blockSize, - uint32_t postShift); - - - /** - * @brief Instance structure for the floating-point normalized LMS filter. - */ - typedef struct - { - uint16_t numTaps; /**< number of coefficients in the filter. */ - float32_t *pState; /**< points to the state variable array. The array is of length numTaps+blockSize-1. */ - float32_t *pCoeffs; /**< points to the coefficient array. The array is of length numTaps. */ - float32_t mu; /**< step size that control filter coefficient updates. */ - float32_t energy; /**< saves previous frame energy. */ - float32_t x0; /**< saves previous input sample. */ - } arm_lms_norm_instance_f32; - - - /** - * @brief Processing function for floating-point normalized LMS filter. - * @param[in] S points to an instance of the floating-point normalized LMS filter structure. - * @param[in] pSrc points to the block of input data. - * @param[in] pRef points to the block of reference data. - * @param[out] pOut points to the block of output data. - * @param[out] pErr points to the block of error data. - * @param[in] blockSize number of samples to process. - */ - void arm_lms_norm_f32( - arm_lms_norm_instance_f32 * S, - float32_t * pSrc, - float32_t * pRef, - float32_t * pOut, - float32_t * pErr, - uint32_t blockSize); - - - /** - * @brief Initialization function for floating-point normalized LMS filter. - * @param[in] S points to an instance of the floating-point LMS filter structure. - * @param[in] numTaps number of filter coefficients. - * @param[in] pCoeffs points to coefficient buffer. - * @param[in] pState points to state buffer. - * @param[in] mu step size that controls filter coefficient updates. - * @param[in] blockSize number of samples to process. - */ - void arm_lms_norm_init_f32( - arm_lms_norm_instance_f32 * S, - uint16_t numTaps, - float32_t * pCoeffs, - float32_t * pState, - float32_t mu, - uint32_t blockSize); - - - /** - * @brief Instance structure for the Q31 normalized LMS filter. - */ - typedef struct - { - uint16_t numTaps; /**< number of coefficients in the filter. */ - q31_t *pState; /**< points to the state variable array. The array is of length numTaps+blockSize-1. */ - q31_t *pCoeffs; /**< points to the coefficient array. The array is of length numTaps. */ - q31_t mu; /**< step size that controls filter coefficient updates. */ - uint8_t postShift; /**< bit shift applied to coefficients. */ - q31_t *recipTable; /**< points to the reciprocal initial value table. */ - q31_t energy; /**< saves previous frame energy. */ - q31_t x0; /**< saves previous input sample. */ - } arm_lms_norm_instance_q31; - - - /** - * @brief Processing function for Q31 normalized LMS filter. - * @param[in] S points to an instance of the Q31 normalized LMS filter structure. - * @param[in] pSrc points to the block of input data. - * @param[in] pRef points to the block of reference data. - * @param[out] pOut points to the block of output data. - * @param[out] pErr points to the block of error data. - * @param[in] blockSize number of samples to process. - */ - void arm_lms_norm_q31( - arm_lms_norm_instance_q31 * S, - q31_t * pSrc, - q31_t * pRef, - q31_t * pOut, - q31_t * pErr, - uint32_t blockSize); - - - /** - * @brief Initialization function for Q31 normalized LMS filter. - * @param[in] S points to an instance of the Q31 normalized LMS filter structure. - * @param[in] numTaps number of filter coefficients. - * @param[in] pCoeffs points to coefficient buffer. - * @param[in] pState points to state buffer. - * @param[in] mu step size that controls filter coefficient updates. - * @param[in] blockSize number of samples to process. - * @param[in] postShift bit shift applied to coefficients. - */ - void arm_lms_norm_init_q31( - arm_lms_norm_instance_q31 * S, - uint16_t numTaps, - q31_t * pCoeffs, - q31_t * pState, - q31_t mu, - uint32_t blockSize, - uint8_t postShift); - - - /** - * @brief Instance structure for the Q15 normalized LMS filter. - */ - typedef struct - { - uint16_t numTaps; /**< Number of coefficients in the filter. */ - q15_t *pState; /**< points to the state variable array. The array is of length numTaps+blockSize-1. */ - q15_t *pCoeffs; /**< points to the coefficient array. The array is of length numTaps. */ - q15_t mu; /**< step size that controls filter coefficient updates. */ - uint8_t postShift; /**< bit shift applied to coefficients. */ - q15_t *recipTable; /**< Points to the reciprocal initial value table. */ - q15_t energy; /**< saves previous frame energy. */ - q15_t x0; /**< saves previous input sample. */ - } arm_lms_norm_instance_q15; - - - /** - * @brief Processing function for Q15 normalized LMS filter. - * @param[in] S points to an instance of the Q15 normalized LMS filter structure. - * @param[in] pSrc points to the block of input data. - * @param[in] pRef points to the block of reference data. - * @param[out] pOut points to the block of output data. - * @param[out] pErr points to the block of error data. - * @param[in] blockSize number of samples to process. - */ - void arm_lms_norm_q15( - arm_lms_norm_instance_q15 * S, - q15_t * pSrc, - q15_t * pRef, - q15_t * pOut, - q15_t * pErr, - uint32_t blockSize); - - - /** - * @brief Initialization function for Q15 normalized LMS filter. - * @param[in] S points to an instance of the Q15 normalized LMS filter structure. - * @param[in] numTaps number of filter coefficients. - * @param[in] pCoeffs points to coefficient buffer. - * @param[in] pState points to state buffer. - * @param[in] mu step size that controls filter coefficient updates. - * @param[in] blockSize number of samples to process. - * @param[in] postShift bit shift applied to coefficients. - */ - void arm_lms_norm_init_q15( - arm_lms_norm_instance_q15 * S, - uint16_t numTaps, - q15_t * pCoeffs, - q15_t * pState, - q15_t mu, - uint32_t blockSize, - uint8_t postShift); - - - /** - * @brief Correlation of floating-point sequences. - * @param[in] pSrcA points to the first input sequence. - * @param[in] srcALen length of the first input sequence. - * @param[in] pSrcB points to the second input sequence. - * @param[in] srcBLen length of the second input sequence. - * @param[out] pDst points to the block of output data Length 2 * max(srcALen, srcBLen) - 1. - */ - void arm_correlate_f32( - float32_t * pSrcA, - uint32_t srcALen, - float32_t * pSrcB, - uint32_t srcBLen, - float32_t * pDst); - - - /** - * @brief Correlation of Q15 sequences - * @param[in] pSrcA points to the first input sequence. - * @param[in] srcALen length of the first input sequence. - * @param[in] pSrcB points to the second input sequence. - * @param[in] srcBLen length of the second input sequence. - * @param[out] pDst points to the block of output data Length 2 * max(srcALen, srcBLen) - 1. - * @param[in] pScratch points to scratch buffer of size max(srcALen, srcBLen) + 2*min(srcALen, srcBLen) - 2. - */ - void arm_correlate_opt_q15( - q15_t * pSrcA, - uint32_t srcALen, - q15_t * pSrcB, - uint32_t srcBLen, - q15_t * pDst, - q15_t * pScratch); - - - /** - * @brief Correlation of Q15 sequences. - * @param[in] pSrcA points to the first input sequence. - * @param[in] srcALen length of the first input sequence. - * @param[in] pSrcB points to the second input sequence. - * @param[in] srcBLen length of the second input sequence. - * @param[out] pDst points to the block of output data Length 2 * max(srcALen, srcBLen) - 1. - */ - - void arm_correlate_q15( - q15_t * pSrcA, - uint32_t srcALen, - q15_t * pSrcB, - uint32_t srcBLen, - q15_t * pDst); - - - /** - * @brief Correlation of Q15 sequences (fast version) for Cortex-M3 and Cortex-M4. - * @param[in] pSrcA points to the first input sequence. - * @param[in] srcALen length of the first input sequence. - * @param[in] pSrcB points to the second input sequence. - * @param[in] srcBLen length of the second input sequence. - * @param[out] pDst points to the block of output data Length 2 * max(srcALen, srcBLen) - 1. - */ - - void arm_correlate_fast_q15( - q15_t * pSrcA, - uint32_t srcALen, - q15_t * pSrcB, - uint32_t srcBLen, - q15_t * pDst); - - - /** - * @brief Correlation of Q15 sequences (fast version) for Cortex-M3 and Cortex-M4. - * @param[in] pSrcA points to the first input sequence. - * @param[in] srcALen length of the first input sequence. - * @param[in] pSrcB points to the second input sequence. - * @param[in] srcBLen length of the second input sequence. - * @param[out] pDst points to the block of output data Length 2 * max(srcALen, srcBLen) - 1. - * @param[in] pScratch points to scratch buffer of size max(srcALen, srcBLen) + 2*min(srcALen, srcBLen) - 2. - */ - void arm_correlate_fast_opt_q15( - q15_t * pSrcA, - uint32_t srcALen, - q15_t * pSrcB, - uint32_t srcBLen, - q15_t * pDst, - q15_t * pScratch); - - - /** - * @brief Correlation of Q31 sequences. - * @param[in] pSrcA points to the first input sequence. - * @param[in] srcALen length of the first input sequence. - * @param[in] pSrcB points to the second input sequence. - * @param[in] srcBLen length of the second input sequence. - * @param[out] pDst points to the block of output data Length 2 * max(srcALen, srcBLen) - 1. - */ - void arm_correlate_q31( - q31_t * pSrcA, - uint32_t srcALen, - q31_t * pSrcB, - uint32_t srcBLen, - q31_t * pDst); - - - /** - * @brief Correlation of Q31 sequences (fast version) for Cortex-M3 and Cortex-M4 - * @param[in] pSrcA points to the first input sequence. - * @param[in] srcALen length of the first input sequence. - * @param[in] pSrcB points to the second input sequence. - * @param[in] srcBLen length of the second input sequence. - * @param[out] pDst points to the block of output data Length 2 * max(srcALen, srcBLen) - 1. - */ - void arm_correlate_fast_q31( - q31_t * pSrcA, - uint32_t srcALen, - q31_t * pSrcB, - uint32_t srcBLen, - q31_t * pDst); - - - /** - * @brief Correlation of Q7 sequences. - * @param[in] pSrcA points to the first input sequence. - * @param[in] srcALen length of the first input sequence. - * @param[in] pSrcB points to the second input sequence. - * @param[in] srcBLen length of the second input sequence. - * @param[out] pDst points to the block of output data Length 2 * max(srcALen, srcBLen) - 1. - * @param[in] pScratch1 points to scratch buffer(of type q15_t) of size max(srcALen, srcBLen) + 2*min(srcALen, srcBLen) - 2. - * @param[in] pScratch2 points to scratch buffer (of type q15_t) of size min(srcALen, srcBLen). - */ - void arm_correlate_opt_q7( - q7_t * pSrcA, - uint32_t srcALen, - q7_t * pSrcB, - uint32_t srcBLen, - q7_t * pDst, - q15_t * pScratch1, - q15_t * pScratch2); - - - /** - * @brief Correlation of Q7 sequences. - * @param[in] pSrcA points to the first input sequence. - * @param[in] srcALen length of the first input sequence. - * @param[in] pSrcB points to the second input sequence. - * @param[in] srcBLen length of the second input sequence. - * @param[out] pDst points to the block of output data Length 2 * max(srcALen, srcBLen) - 1. - */ - void arm_correlate_q7( - q7_t * pSrcA, - uint32_t srcALen, - q7_t * pSrcB, - uint32_t srcBLen, - q7_t * pDst); - - - /** - * @brief Instance structure for the floating-point sparse FIR filter. - */ - typedef struct - { - uint16_t numTaps; /**< number of coefficients in the filter. */ - uint16_t stateIndex; /**< state buffer index. Points to the oldest sample in the state buffer. */ - float32_t *pState; /**< points to the state buffer array. The array is of length maxDelay+blockSize-1. */ - float32_t *pCoeffs; /**< points to the coefficient array. The array is of length numTaps.*/ - uint16_t maxDelay; /**< maximum offset specified by the pTapDelay array. */ - int32_t *pTapDelay; /**< points to the array of delay values. The array is of length numTaps. */ - } arm_fir_sparse_instance_f32; - - /** - * @brief Instance structure for the Q31 sparse FIR filter. - */ - typedef struct - { - uint16_t numTaps; /**< number of coefficients in the filter. */ - uint16_t stateIndex; /**< state buffer index. Points to the oldest sample in the state buffer. */ - q31_t *pState; /**< points to the state buffer array. The array is of length maxDelay+blockSize-1. */ - q31_t *pCoeffs; /**< points to the coefficient array. The array is of length numTaps.*/ - uint16_t maxDelay; /**< maximum offset specified by the pTapDelay array. */ - int32_t *pTapDelay; /**< points to the array of delay values. The array is of length numTaps. */ - } arm_fir_sparse_instance_q31; - - /** - * @brief Instance structure for the Q15 sparse FIR filter. - */ - typedef struct - { - uint16_t numTaps; /**< number of coefficients in the filter. */ - uint16_t stateIndex; /**< state buffer index. Points to the oldest sample in the state buffer. */ - q15_t *pState; /**< points to the state buffer array. The array is of length maxDelay+blockSize-1. */ - q15_t *pCoeffs; /**< points to the coefficient array. The array is of length numTaps.*/ - uint16_t maxDelay; /**< maximum offset specified by the pTapDelay array. */ - int32_t *pTapDelay; /**< points to the array of delay values. The array is of length numTaps. */ - } arm_fir_sparse_instance_q15; - - /** - * @brief Instance structure for the Q7 sparse FIR filter. - */ - typedef struct - { - uint16_t numTaps; /**< number of coefficients in the filter. */ - uint16_t stateIndex; /**< state buffer index. Points to the oldest sample in the state buffer. */ - q7_t *pState; /**< points to the state buffer array. The array is of length maxDelay+blockSize-1. */ - q7_t *pCoeffs; /**< points to the coefficient array. The array is of length numTaps.*/ - uint16_t maxDelay; /**< maximum offset specified by the pTapDelay array. */ - int32_t *pTapDelay; /**< points to the array of delay values. The array is of length numTaps. */ - } arm_fir_sparse_instance_q7; - - - /** - * @brief Processing function for the floating-point sparse FIR filter. - * @param[in] S points to an instance of the floating-point sparse FIR structure. - * @param[in] pSrc points to the block of input data. - * @param[out] pDst points to the block of output data - * @param[in] pScratchIn points to a temporary buffer of size blockSize. - * @param[in] blockSize number of input samples to process per call. - */ - void arm_fir_sparse_f32( - arm_fir_sparse_instance_f32 * S, - float32_t * pSrc, - float32_t * pDst, - float32_t * pScratchIn, - uint32_t blockSize); - - - /** - * @brief Initialization function for the floating-point sparse FIR filter. - * @param[in,out] S points to an instance of the floating-point sparse FIR structure. - * @param[in] numTaps number of nonzero coefficients in the filter. - * @param[in] pCoeffs points to the array of filter coefficients. - * @param[in] pState points to the state buffer. - * @param[in] pTapDelay points to the array of offset times. - * @param[in] maxDelay maximum offset time supported. - * @param[in] blockSize number of samples that will be processed per block. - */ - void arm_fir_sparse_init_f32( - arm_fir_sparse_instance_f32 * S, - uint16_t numTaps, - float32_t * pCoeffs, - float32_t * pState, - int32_t * pTapDelay, - uint16_t maxDelay, - uint32_t blockSize); - - - /** - * @brief Processing function for the Q31 sparse FIR filter. - * @param[in] S points to an instance of the Q31 sparse FIR structure. - * @param[in] pSrc points to the block of input data. - * @param[out] pDst points to the block of output data - * @param[in] pScratchIn points to a temporary buffer of size blockSize. - * @param[in] blockSize number of input samples to process per call. - */ - void arm_fir_sparse_q31( - arm_fir_sparse_instance_q31 * S, - q31_t * pSrc, - q31_t * pDst, - q31_t * pScratchIn, - uint32_t blockSize); - - - /** - * @brief Initialization function for the Q31 sparse FIR filter. - * @param[in,out] S points to an instance of the Q31 sparse FIR structure. - * @param[in] numTaps number of nonzero coefficients in the filter. - * @param[in] pCoeffs points to the array of filter coefficients. - * @param[in] pState points to the state buffer. - * @param[in] pTapDelay points to the array of offset times. - * @param[in] maxDelay maximum offset time supported. - * @param[in] blockSize number of samples that will be processed per block. - */ - void arm_fir_sparse_init_q31( - arm_fir_sparse_instance_q31 * S, - uint16_t numTaps, - q31_t * pCoeffs, - q31_t * pState, - int32_t * pTapDelay, - uint16_t maxDelay, - uint32_t blockSize); - - - /** - * @brief Processing function for the Q15 sparse FIR filter. - * @param[in] S points to an instance of the Q15 sparse FIR structure. - * @param[in] pSrc points to the block of input data. - * @param[out] pDst points to the block of output data - * @param[in] pScratchIn points to a temporary buffer of size blockSize. - * @param[in] pScratchOut points to a temporary buffer of size blockSize. - * @param[in] blockSize number of input samples to process per call. - */ - void arm_fir_sparse_q15( - arm_fir_sparse_instance_q15 * S, - q15_t * pSrc, - q15_t * pDst, - q15_t * pScratchIn, - q31_t * pScratchOut, - uint32_t blockSize); - - - /** - * @brief Initialization function for the Q15 sparse FIR filter. - * @param[in,out] S points to an instance of the Q15 sparse FIR structure. - * @param[in] numTaps number of nonzero coefficients in the filter. - * @param[in] pCoeffs points to the array of filter coefficients. - * @param[in] pState points to the state buffer. - * @param[in] pTapDelay points to the array of offset times. - * @param[in] maxDelay maximum offset time supported. - * @param[in] blockSize number of samples that will be processed per block. - */ - void arm_fir_sparse_init_q15( - arm_fir_sparse_instance_q15 * S, - uint16_t numTaps, - q15_t * pCoeffs, - q15_t * pState, - int32_t * pTapDelay, - uint16_t maxDelay, - uint32_t blockSize); - - - /** - * @brief Processing function for the Q7 sparse FIR filter. - * @param[in] S points to an instance of the Q7 sparse FIR structure. - * @param[in] pSrc points to the block of input data. - * @param[out] pDst points to the block of output data - * @param[in] pScratchIn points to a temporary buffer of size blockSize. - * @param[in] pScratchOut points to a temporary buffer of size blockSize. - * @param[in] blockSize number of input samples to process per call. - */ - void arm_fir_sparse_q7( - arm_fir_sparse_instance_q7 * S, - q7_t * pSrc, - q7_t * pDst, - q7_t * pScratchIn, - q31_t * pScratchOut, - uint32_t blockSize); - - - /** - * @brief Initialization function for the Q7 sparse FIR filter. - * @param[in,out] S points to an instance of the Q7 sparse FIR structure. - * @param[in] numTaps number of nonzero coefficients in the filter. - * @param[in] pCoeffs points to the array of filter coefficients. - * @param[in] pState points to the state buffer. - * @param[in] pTapDelay points to the array of offset times. - * @param[in] maxDelay maximum offset time supported. - * @param[in] blockSize number of samples that will be processed per block. - */ - void arm_fir_sparse_init_q7( - arm_fir_sparse_instance_q7 * S, - uint16_t numTaps, - q7_t * pCoeffs, - q7_t * pState, - int32_t * pTapDelay, - uint16_t maxDelay, - uint32_t blockSize); - - - /** - * @brief Floating-point sin_cos function. - * @param[in] theta input value in degrees - * @param[out] pSinVal points to the processed sine output. - * @param[out] pCosVal points to the processed cos output. - */ - void arm_sin_cos_f32( - float32_t theta, - float32_t * pSinVal, - float32_t * pCosVal); - - - /** - * @brief Q31 sin_cos function. - * @param[in] theta scaled input value in degrees - * @param[out] pSinVal points to the processed sine output. - * @param[out] pCosVal points to the processed cosine output. - */ - void arm_sin_cos_q31( - q31_t theta, - q31_t * pSinVal, - q31_t * pCosVal); - - - /** - * @brief Floating-point complex conjugate. - * @param[in] pSrc points to the input vector - * @param[out] pDst points to the output vector - * @param[in] numSamples number of complex samples in each vector - */ - void arm_cmplx_conj_f32( - float32_t * pSrc, - float32_t * pDst, - uint32_t numSamples); - - /** - * @brief Q31 complex conjugate. - * @param[in] pSrc points to the input vector - * @param[out] pDst points to the output vector - * @param[in] numSamples number of complex samples in each vector - */ - void arm_cmplx_conj_q31( - q31_t * pSrc, - q31_t * pDst, - uint32_t numSamples); - - - /** - * @brief Q15 complex conjugate. - * @param[in] pSrc points to the input vector - * @param[out] pDst points to the output vector - * @param[in] numSamples number of complex samples in each vector - */ - void arm_cmplx_conj_q15( - q15_t * pSrc, - q15_t * pDst, - uint32_t numSamples); - - - /** - * @brief Floating-point complex magnitude squared - * @param[in] pSrc points to the complex input vector - * @param[out] pDst points to the real output vector - * @param[in] numSamples number of complex samples in the input vector - */ - void arm_cmplx_mag_squared_f32( - float32_t * pSrc, - float32_t * pDst, - uint32_t numSamples); - - - /** - * @brief Q31 complex magnitude squared - * @param[in] pSrc points to the complex input vector - * @param[out] pDst points to the real output vector - * @param[in] numSamples number of complex samples in the input vector - */ - void arm_cmplx_mag_squared_q31( - q31_t * pSrc, - q31_t * pDst, - uint32_t numSamples); - - - /** - * @brief Q15 complex magnitude squared - * @param[in] pSrc points to the complex input vector - * @param[out] pDst points to the real output vector - * @param[in] numSamples number of complex samples in the input vector - */ - void arm_cmplx_mag_squared_q15( - q15_t * pSrc, - q15_t * pDst, - uint32_t numSamples); - - - /** - * @ingroup groupController - */ - - /** - * @defgroup PID PID Motor Control - * - * A Proportional Integral Derivative (PID) controller is a generic feedback control - * loop mechanism widely used in industrial control systems. - * A PID controller is the most commonly used type of feedback controller. - * - * This set of functions implements (PID) controllers - * for Q15, Q31, and floating-point data types. The functions operate on a single sample - * of data and each call to the function returns a single processed value. - * S points to an instance of the PID control data structure. in - * is the input sample value. The functions return the output value. - * - * \par Algorithm: - * 
-   *    y[n] = y[n-1] + A0 * x[n] + A1 * x[n-1] + A2 * x[n-2]
-   *    A0 = Kp + Ki + Kd
-   *    A1 = (-Kp ) - (2 * Kd )
-   *    A2 = Kd
- * - * \par - * where \c Kp is proportional constant, \c Ki is Integral constant and \c Kd is Derivative constant - * - * \par - * \image html PID.gif "Proportional Integral Derivative Controller" - * - * \par - * The PID controller calculates an "error" value as the difference between - * the measured output and the reference input. - * The controller attempts to minimize the error by adjusting the process control inputs. - * The proportional value determines the reaction to the current error, - * the integral value determines the reaction based on the sum of recent errors, - * and the derivative value determines the reaction based on the rate at which the error has been changing. - * - * \par Instance Structure - * The Gains A0, A1, A2 and state variables for a PID controller are stored together in an instance data structure. - * A separate instance structure must be defined for each PID Controller. - * There are separate instance structure declarations for each of the 3 supported data types. - * - * \par Reset Functions - * There is also an associated reset function for each data type which clears the state array. - * - * \par Initialization Functions - * There is also an associated initialization function for each data type. - * The initialization function performs the following operations: - * - Initializes the Gains A0, A1, A2 from Kp,Ki, Kd gains. - * - Zeros out the values in the state buffer. - * - * \par - * Instance structure cannot be placed into a const data section and it is recommended to use the initialization function. - * - * \par Fixed-Point Behavior - * Care must be taken when using the fixed-point versions of the PID Controller functions. - * In particular, the overflow and saturation behavior of the accumulator used in each function must be considered. - * Refer to the function specific documentation below for usage guidelines. - */ - - /** - * @addtogroup PID - * @{ - */ - - /** - * @brief Process function for the floating-point PID Control. - * @param[in,out] S is an instance of the floating-point PID Control structure - * @param[in] in input sample to process - * @return out processed output sample. - */ - static __INLINE float32_t arm_pid_f32( - arm_pid_instance_f32 * S, - float32_t in) - { - float32_t out; - - /* y[n] = y[n-1] + A0 * x[n] + A1 * x[n-1] + A2 * x[n-2] */ - out = (S->A0 * in) + - (S->A1 * S->state[0]) + (S->A2 * S->state[1]) + (S->state[2]); - - /* Update state */ - S->state[1] = S->state[0]; - S->state[0] = in; - S->state[2] = out; - - /* return to application */ - return (out); - - } - - /** - * @brief Process function for the Q31 PID Control. - * @param[in,out] S points to an instance of the Q31 PID Control structure - * @param[in] in input sample to process - * @return out processed output sample. - * - * Scaling and Overflow Behavior: - * \par - * The function is implemented using an internal 64-bit accumulator. - * The accumulator has a 2.62 format and maintains full precision of the intermediate multiplication results but provides only a single guard bit. - * Thus, if the accumulator result overflows it wraps around rather than clip. - * In order to avoid overflows completely the input signal must be scaled down by 2 bits as there are four additions. - * After all multiply-accumulates are performed, the 2.62 accumulator is truncated to 1.32 format and then saturated to 1.31 format. - */ - static __INLINE q31_t arm_pid_q31( - arm_pid_instance_q31 * S, - q31_t in) - { - q63_t acc; - q31_t out; - - /* acc = A0 * x[n] */ - acc = (q63_t) S->A0 * in; - - /* acc += A1 * x[n-1] */ - acc += (q63_t) S->A1 * S->state[0]; - - /* acc += A2 * x[n-2] */ - acc += (q63_t) S->A2 * S->state[1]; - - /* convert output to 1.31 format to add y[n-1] */ - out = (q31_t) (acc >> 31u); - - /* out += y[n-1] */ - out += S->state[2]; - - /* Update state */ - S->state[1] = S->state[0]; - S->state[0] = in; - S->state[2] = out; - - /* return to application */ - return (out); - } - - - /** - * @brief Process function for the Q15 PID Control. - * @param[in,out] S points to an instance of the Q15 PID Control structure - * @param[in] in input sample to process - * @return out processed output sample. - * - * Scaling and Overflow Behavior: - * \par - * The function is implemented using a 64-bit internal accumulator. - * Both Gains and state variables are represented in 1.15 format and multiplications yield a 2.30 result. - * The 2.30 intermediate results are accumulated in a 64-bit accumulator in 34.30 format. - * There is no risk of internal overflow with this approach and the full precision of intermediate multiplications is preserved. - * After all additions have been performed, the accumulator is truncated to 34.15 format by discarding low 15 bits. - * Lastly, the accumulator is saturated to yield a result in 1.15 format. - */ - static __INLINE q15_t arm_pid_q15( - arm_pid_instance_q15 * S, - q15_t in) - { - q63_t acc; - q15_t out; - -#ifndef ARM_MATH_CM0_FAMILY - __SIMD32_TYPE *vstate; - - /* Implementation of PID controller */ - - /* acc = A0 * x[n] */ - acc = (q31_t) __SMUAD((uint32_t)S->A0, (uint32_t)in); - - /* acc += A1 * x[n-1] + A2 * x[n-2] */ - vstate = __SIMD32_CONST(S->state); - acc = (q63_t)__SMLALD((uint32_t)S->A1, (uint32_t)*vstate, (uint64_t)acc); -#else - /* acc = A0 * x[n] */ - acc = ((q31_t) S->A0) * in; - - /* acc += A1 * x[n-1] + A2 * x[n-2] */ - acc += (q31_t) S->A1 * S->state[0]; - acc += (q31_t) S->A2 * S->state[1]; -#endif - - /* acc += y[n-1] */ - acc += (q31_t) S->state[2] << 15; - - /* saturate the output */ - out = (q15_t) (__SSAT((acc >> 15), 16)); - - /* Update state */ - S->state[1] = S->state[0]; - S->state[0] = in; - S->state[2] = out; - - /* return to application */ - return (out); - } - - /** - * @} end of PID group - */ - - - /** - * @brief Floating-point matrix inverse. - * @param[in] src points to the instance of the input floating-point matrix structure. - * @param[out] dst points to the instance of the output floating-point matrix structure. - * @return The function returns ARM_MATH_SIZE_MISMATCH, if the dimensions do not match. - * If the input matrix is singular (does not have an inverse), then the algorithm terminates and returns error status ARM_MATH_SINGULAR. - */ - arm_status arm_mat_inverse_f32( - const arm_matrix_instance_f32 * src, - arm_matrix_instance_f32 * dst); - - - /** - * @brief Floating-point matrix inverse. - * @param[in] src points to the instance of the input floating-point matrix structure. - * @param[out] dst points to the instance of the output floating-point matrix structure. - * @return The function returns ARM_MATH_SIZE_MISMATCH, if the dimensions do not match. - * If the input matrix is singular (does not have an inverse), then the algorithm terminates and returns error status ARM_MATH_SINGULAR. - */ - arm_status arm_mat_inverse_f64( - const arm_matrix_instance_f64 * src, - arm_matrix_instance_f64 * dst); - - - - /** - * @ingroup groupController - */ - - /** - * @defgroup clarke Vector Clarke Transform - * Forward Clarke transform converts the instantaneous stator phases into a two-coordinate time invariant vector. - * Generally the Clarke transform uses three-phase currents Ia, Ib and Ic to calculate currents - * in the two-phase orthogonal stator axis Ialpha and Ibeta. - * When Ialpha is superposed with Ia as shown in the figure below - * \image html clarke.gif Stator current space vector and its components in (a,b). - * and Ia + Ib + Ic = 0, in this condition Ialpha and Ibeta - * can be calculated using only Ia and Ib. - * - * The function operates on a single sample of data and each call to the function returns the processed output. - * The library provides separate functions for Q31 and floating-point data types. - * \par Algorithm - * \image html clarkeFormula.gif - * where Ia and Ib are the instantaneous stator phases and - * pIalpha and pIbeta are the two coordinates of time invariant vector. - * \par Fixed-Point Behavior - * Care must be taken when using the Q31 version of the Clarke transform. - * In particular, the overflow and saturation behavior of the accumulator used must be considered. - * Refer to the function specific documentation below for usage guidelines. - */ - - /** - * @addtogroup clarke - * @{ - */ - - /** - * - * @brief Floating-point Clarke transform - * @param[in] Ia input three-phase coordinate a - * @param[in] Ib input three-phase coordinate b - * @param[out] pIalpha points to output two-phase orthogonal vector axis alpha - * @param[out] pIbeta points to output two-phase orthogonal vector axis beta - */ - static __INLINE void arm_clarke_f32( - float32_t Ia, - float32_t Ib, - float32_t * pIalpha, - float32_t * pIbeta) - { - /* Calculate pIalpha using the equation, pIalpha = Ia */ - *pIalpha = Ia; - - /* Calculate pIbeta using the equation, pIbeta = (1/sqrt(3)) * Ia + (2/sqrt(3)) * Ib */ - *pIbeta = ((float32_t) 0.57735026919 * Ia + (float32_t) 1.15470053838 * Ib); - } - - - /** - * @brief Clarke transform for Q31 version - * @param[in] Ia input three-phase coordinate a - * @param[in] Ib input three-phase coordinate b - * @param[out] pIalpha points to output two-phase orthogonal vector axis alpha - * @param[out] pIbeta points to output two-phase orthogonal vector axis beta - * - * Scaling and Overflow Behavior: - * \par - * The function is implemented using an internal 32-bit accumulator. - * The accumulator maintains 1.31 format by truncating lower 31 bits of the intermediate multiplication in 2.62 format. - * There is saturation on the addition, hence there is no risk of overflow. - */ - static __INLINE void arm_clarke_q31( - q31_t Ia, - q31_t Ib, - q31_t * pIalpha, - q31_t * pIbeta) - { - q31_t product1, product2; /* Temporary variables used to store intermediate results */ - - /* Calculating pIalpha from Ia by equation pIalpha = Ia */ - *pIalpha = Ia; - - /* Intermediate product is calculated by (1/(sqrt(3)) * Ia) */ - product1 = (q31_t) (((q63_t) Ia * 0x24F34E8B) >> 30); - - /* Intermediate product is calculated by (2/sqrt(3) * Ib) */ - product2 = (q31_t) (((q63_t) Ib * 0x49E69D16) >> 30); - - /* pIbeta is calculated by adding the intermediate products */ - *pIbeta = __QADD(product1, product2); - } - - /** - * @} end of clarke group - */ - - /** - * @brief Converts the elements of the Q7 vector to Q31 vector. - * @param[in] pSrc input pointer - * @param[out] pDst output pointer - * @param[in] blockSize number of samples to process - */ - void arm_q7_to_q31( - q7_t * pSrc, - q31_t * pDst, - uint32_t blockSize); - - - - /** - * @ingroup groupController - */ - - /** - * @defgroup inv_clarke Vector Inverse Clarke Transform - * Inverse Clarke transform converts the two-coordinate time invariant vector into instantaneous stator phases. - * - * The function operates on a single sample of data and each call to the function returns the processed output. - * The library provides separate functions for Q31 and floating-point data types. - * \par Algorithm - * \image html clarkeInvFormula.gif - * where pIa and pIb are the instantaneous stator phases and - * Ialpha and Ibeta are the two coordinates of time invariant vector. - * \par Fixed-Point Behavior - * Care must be taken when using the Q31 version of the Clarke transform. - * In particular, the overflow and saturation behavior of the accumulator used must be considered. - * Refer to the function specific documentation below for usage guidelines. - */ - - /** - * @addtogroup inv_clarke - * @{ - */ - - /** - * @brief Floating-point Inverse Clarke transform - * @param[in] Ialpha input two-phase orthogonal vector axis alpha - * @param[in] Ibeta input two-phase orthogonal vector axis beta - * @param[out] pIa points to output three-phase coordinate a - * @param[out] pIb points to output three-phase coordinate b - */ - static __INLINE void arm_inv_clarke_f32( - float32_t Ialpha, - float32_t Ibeta, - float32_t * pIa, - float32_t * pIb) - { - /* Calculating pIa from Ialpha by equation pIa = Ialpha */ - *pIa = Ialpha; - - /* Calculating pIb from Ialpha and Ibeta by equation pIb = -(1/2) * Ialpha + (sqrt(3)/2) * Ibeta */ - *pIb = -0.5f * Ialpha + 0.8660254039f * Ibeta; - } - - - /** - * @brief Inverse Clarke transform for Q31 version - * @param[in] Ialpha input two-phase orthogonal vector axis alpha - * @param[in] Ibeta input two-phase orthogonal vector axis beta - * @param[out] pIa points to output three-phase coordinate a - * @param[out] pIb points to output three-phase coordinate b - * - * Scaling and Overflow Behavior: - * \par - * The function is implemented using an internal 32-bit accumulator. - * The accumulator maintains 1.31 format by truncating lower 31 bits of the intermediate multiplication in 2.62 format. - * There is saturation on the subtraction, hence there is no risk of overflow. - */ - static __INLINE void arm_inv_clarke_q31( - q31_t Ialpha, - q31_t Ibeta, - q31_t * pIa, - q31_t * pIb) - { - q31_t product1, product2; /* Temporary variables used to store intermediate results */ - - /* Calculating pIa from Ialpha by equation pIa = Ialpha */ - *pIa = Ialpha; - - /* Intermediate product is calculated by (1/(2*sqrt(3)) * Ia) */ - product1 = (q31_t) (((q63_t) (Ialpha) * (0x40000000)) >> 31); - - /* Intermediate product is calculated by (1/sqrt(3) * pIb) */ - product2 = (q31_t) (((q63_t) (Ibeta) * (0x6ED9EBA1)) >> 31); - - /* pIb is calculated by subtracting the products */ - *pIb = __QSUB(product2, product1); - } - - /** - * @} end of inv_clarke group - */ - - /** - * @brief Converts the elements of the Q7 vector to Q15 vector. - * @param[in] pSrc input pointer - * @param[out] pDst output pointer - * @param[in] blockSize number of samples to process - */ - void arm_q7_to_q15( - q7_t * pSrc, - q15_t * pDst, - uint32_t blockSize); - - - - /** - * @ingroup groupController - */ - - /** - * @defgroup park Vector Park Transform - * - * Forward Park transform converts the input two-coordinate vector to flux and torque components. - * The Park transform can be used to realize the transformation of the Ialpha and the Ibeta currents - * from the stationary to the moving reference frame and control the spatial relationship between - * the stator vector current and rotor flux vector. - * If we consider the d axis aligned with the rotor flux, the diagram below shows the - * current vector and the relationship from the two reference frames: - * \image html park.gif "Stator current space vector and its component in (a,b) and in the d,q rotating reference frame" - * - * The function operates on a single sample of data and each call to the function returns the processed output. - * The library provides separate functions for Q31 and floating-point data types. - * \par Algorithm - * \image html parkFormula.gif - * where Ialpha and Ibeta are the stator vector components, - * pId and pIq are rotor vector components and cosVal and sinVal are the - * cosine and sine values of theta (rotor flux position). - * \par Fixed-Point Behavior - * Care must be taken when using the Q31 version of the Park transform. - * In particular, the overflow and saturation behavior of the accumulator used must be considered. - * Refer to the function specific documentation below for usage guidelines. - */ - - /** - * @addtogroup park - * @{ - */ - - /** - * @brief Floating-point Park transform - * @param[in] Ialpha input two-phase vector coordinate alpha - * @param[in] Ibeta input two-phase vector coordinate beta - * @param[out] pId points to output rotor reference frame d - * @param[out] pIq points to output rotor reference frame q - * @param[in] sinVal sine value of rotation angle theta - * @param[in] cosVal cosine value of rotation angle theta - * - * The function implements the forward Park transform. - * - */ - static __INLINE void arm_park_f32( - float32_t Ialpha, - float32_t Ibeta, - float32_t * pId, - float32_t * pIq, - float32_t sinVal, - float32_t cosVal) - { - /* Calculate pId using the equation, pId = Ialpha * cosVal + Ibeta * sinVal */ - *pId = Ialpha * cosVal + Ibeta * sinVal; - - /* Calculate pIq using the equation, pIq = - Ialpha * sinVal + Ibeta * cosVal */ - *pIq = -Ialpha * sinVal + Ibeta * cosVal; - } - - - /** - * @brief Park transform for Q31 version - * @param[in] Ialpha input two-phase vector coordinate alpha - * @param[in] Ibeta input two-phase vector coordinate beta - * @param[out] pId points to output rotor reference frame d - * @param[out] pIq points to output rotor reference frame q - * @param[in] sinVal sine value of rotation angle theta - * @param[in] cosVal cosine value of rotation angle theta - * - * Scaling and Overflow Behavior: - * \par - * The function is implemented using an internal 32-bit accumulator. - * The accumulator maintains 1.31 format by truncating lower 31 bits of the intermediate multiplication in 2.62 format. - * There is saturation on the addition and subtraction, hence there is no risk of overflow. - */ - static __INLINE void arm_park_q31( - q31_t Ialpha, - q31_t Ibeta, - q31_t * pId, - q31_t * pIq, - q31_t sinVal, - q31_t cosVal) - { - q31_t product1, product2; /* Temporary variables used to store intermediate results */ - q31_t product3, product4; /* Temporary variables used to store intermediate results */ - - /* Intermediate product is calculated by (Ialpha * cosVal) */ - product1 = (q31_t) (((q63_t) (Ialpha) * (cosVal)) >> 31); - - /* Intermediate product is calculated by (Ibeta * sinVal) */ - product2 = (q31_t) (((q63_t) (Ibeta) * (sinVal)) >> 31); - - - /* Intermediate product is calculated by (Ialpha * sinVal) */ - product3 = (q31_t) (((q63_t) (Ialpha) * (sinVal)) >> 31); - - /* Intermediate product is calculated by (Ibeta * cosVal) */ - product4 = (q31_t) (((q63_t) (Ibeta) * (cosVal)) >> 31); - - /* Calculate pId by adding the two intermediate products 1 and 2 */ - *pId = __QADD(product1, product2); - - /* Calculate pIq by subtracting the two intermediate products 3 from 4 */ - *pIq = __QSUB(product4, product3); - } - - /** - * @} end of park group - */ - - /** - * @brief Converts the elements of the Q7 vector to floating-point vector. - * @param[in] pSrc is input pointer - * @param[out] pDst is output pointer - * @param[in] blockSize is the number of samples to process - */ - void arm_q7_to_float( - q7_t * pSrc, - float32_t * pDst, - uint32_t blockSize); - - - /** - * @ingroup groupController - */ - - /** - * @defgroup inv_park Vector Inverse Park transform - * Inverse Park transform converts the input flux and torque components to two-coordinate vector. - * - * The function operates on a single sample of data and each call to the function returns the processed output. - * The library provides separate functions for Q31 and floating-point data types. - * \par Algorithm - * \image html parkInvFormula.gif - * where pIalpha and pIbeta are the stator vector components, - * Id and Iq are rotor vector components and cosVal and sinVal are the - * cosine and sine values of theta (rotor flux position). - * \par Fixed-Point Behavior - * Care must be taken when using the Q31 version of the Park transform. - * In particular, the overflow and saturation behavior of the accumulator used must be considered. - * Refer to the function specific documentation below for usage guidelines. - */ - - /** - * @addtogroup inv_park - * @{ - */ - - /** - * @brief Floating-point Inverse Park transform - * @param[in] Id input coordinate of rotor reference frame d - * @param[in] Iq input coordinate of rotor reference frame q - * @param[out] pIalpha points to output two-phase orthogonal vector axis alpha - * @param[out] pIbeta points to output two-phase orthogonal vector axis beta - * @param[in] sinVal sine value of rotation angle theta - * @param[in] cosVal cosine value of rotation angle theta - */ - static __INLINE void arm_inv_park_f32( - float32_t Id, - float32_t Iq, - float32_t * pIalpha, - float32_t * pIbeta, - float32_t sinVal, - float32_t cosVal) - { - /* Calculate pIalpha using the equation, pIalpha = Id * cosVal - Iq * sinVal */ - *pIalpha = Id * cosVal - Iq * sinVal; - - /* Calculate pIbeta using the equation, pIbeta = Id * sinVal + Iq * cosVal */ - *pIbeta = Id * sinVal + Iq * cosVal; - } - - - /** - * @brief Inverse Park transform for Q31 version - * @param[in] Id input coordinate of rotor reference frame d - * @param[in] Iq input coordinate of rotor reference frame q - * @param[out] pIalpha points to output two-phase orthogonal vector axis alpha - * @param[out] pIbeta points to output two-phase orthogonal vector axis beta - * @param[in] sinVal sine value of rotation angle theta - * @param[in] cosVal cosine value of rotation angle theta - * - * Scaling and Overflow Behavior: - * \par - * The function is implemented using an internal 32-bit accumulator. - * The accumulator maintains 1.31 format by truncating lower 31 bits of the intermediate multiplication in 2.62 format. - * There is saturation on the addition, hence there is no risk of overflow. - */ - static __INLINE void arm_inv_park_q31( - q31_t Id, - q31_t Iq, - q31_t * pIalpha, - q31_t * pIbeta, - q31_t sinVal, - q31_t cosVal) - { - q31_t product1, product2; /* Temporary variables used to store intermediate results */ - q31_t product3, product4; /* Temporary variables used to store intermediate results */ - - /* Intermediate product is calculated by (Id * cosVal) */ - product1 = (q31_t) (((q63_t) (Id) * (cosVal)) >> 31); - - /* Intermediate product is calculated by (Iq * sinVal) */ - product2 = (q31_t) (((q63_t) (Iq) * (sinVal)) >> 31); - - - /* Intermediate product is calculated by (Id * sinVal) */ - product3 = (q31_t) (((q63_t) (Id) * (sinVal)) >> 31); - - /* Intermediate product is calculated by (Iq * cosVal) */ - product4 = (q31_t) (((q63_t) (Iq) * (cosVal)) >> 31); - - /* Calculate pIalpha by using the two intermediate products 1 and 2 */ - *pIalpha = __QSUB(product1, product2); - - /* Calculate pIbeta by using the two intermediate products 3 and 4 */ - *pIbeta = __QADD(product4, product3); - } - - /** - * @} end of Inverse park group - */ - - - /** - * @brief Converts the elements of the Q31 vector to floating-point vector. - * @param[in] pSrc is input pointer - * @param[out] pDst is output pointer - * @param[in] blockSize is the number of samples to process - */ - void arm_q31_to_float( - q31_t * pSrc, - float32_t * pDst, - uint32_t blockSize); - - /** - * @ingroup groupInterpolation - */ - - /** - * @defgroup LinearInterpolate Linear Interpolation - * - * Linear interpolation is a method of curve fitting using linear polynomials. - * Linear interpolation works by effectively drawing a straight line between two neighboring samples and returning the appropriate point along that line - * - * \par - * \image html LinearInterp.gif "Linear interpolation" - * - * \par - * A Linear Interpolate function calculates an output value(y), for the input(x) - * using linear interpolation of the input values x0, x1( nearest input values) and the output values y0 and y1(nearest output values) - * - * \par Algorithm: - * 
-   *       y = y0 + (x - x0) * ((y1 - y0)/(x1-x0))
-   *       where x0, x1 are nearest values of input x
-   *             y0, y1 are nearest values to output y
-   *
- * - * \par - * This set of functions implements Linear interpolation process - * for Q7, Q15, Q31, and floating-point data types. The functions operate on a single - * sample of data and each call to the function returns a single processed value. - * S points to an instance of the Linear Interpolate function data structure. - * x is the input sample value. The functions returns the output value. - * - * \par - * if x is outside of the table boundary, Linear interpolation returns first value of the table - * if x is below input range and returns last value of table if x is above range. - */ - - /** - * @addtogroup LinearInterpolate - * @{ - */ - - /** - * @brief Process function for the floating-point Linear Interpolation Function. - * @param[in,out] S is an instance of the floating-point Linear Interpolation structure - * @param[in] x input sample to process - * @return y processed output sample. - * - */ - static __INLINE float32_t arm_linear_interp_f32( - arm_linear_interp_instance_f32 * S, - float32_t x) - { - float32_t y; - float32_t x0, x1; /* Nearest input values */ - float32_t y0, y1; /* Nearest output values */ - float32_t xSpacing = S->xSpacing; /* spacing between input values */ - int32_t i; /* Index variable */ - float32_t *pYData = S->pYData; /* pointer to output table */ - - /* Calculation of index */ - i = (int32_t) ((x - S->x1) / xSpacing); - - if(i < 0) - { - /* Iniatilize output for below specified range as least output value of table */ - y = pYData[0]; - } - else if((uint32_t)i >= S->nValues) - { - /* Iniatilize output for above specified range as last output value of table */ - y = pYData[S->nValues - 1]; - } - else - { - /* Calculation of nearest input values */ - x0 = S->x1 + i * xSpacing; - x1 = S->x1 + (i + 1) * xSpacing; - - /* Read of nearest output values */ - y0 = pYData[i]; - y1 = pYData[i + 1]; - - /* Calculation of output */ - y = y0 + (x - x0) * ((y1 - y0) / (x1 - x0)); - - } - - /* returns output value */ - return (y); - } - - - /** - * - * @brief Process function for the Q31 Linear Interpolation Function. - * @param[in] pYData pointer to Q31 Linear Interpolation table - * @param[in] x input sample to process - * @param[in] nValues number of table values - * @return y processed output sample. - * - * \par - * Input sample x is in 12.20 format which contains 12 bits for table index and 20 bits for fractional part. - * This function can support maximum of table size 2^12. - * - */ - static __INLINE q31_t arm_linear_interp_q31( - q31_t * pYData, - q31_t x, - uint32_t nValues) - { - q31_t y; /* output */ - q31_t y0, y1; /* Nearest output values */ - q31_t fract; /* fractional part */ - int32_t index; /* Index to read nearest output values */ - - /* Input is in 12.20 format */ - /* 12 bits for the table index */ - /* Index value calculation */ - index = ((x & (q31_t)0xFFF00000) >> 20); - - if(index >= (int32_t)(nValues - 1)) - { - return (pYData[nValues - 1]); - } - else if(index < 0) - { - return (pYData[0]); - } - else - { - /* 20 bits for the fractional part */ - /* shift left by 11 to keep fract in 1.31 format */ - fract = (x & 0x000FFFFF) << 11; - - /* Read two nearest output values from the index in 1.31(q31) format */ - y0 = pYData[index]; - y1 = pYData[index + 1]; - - /* Calculation of y0 * (1-fract) and y is in 2.30 format */ - y = ((q31_t) ((q63_t) y0 * (0x7FFFFFFF - fract) >> 32)); - - /* Calculation of y0 * (1-fract) + y1 *fract and y is in 2.30 format */ - y += ((q31_t) (((q63_t) y1 * fract) >> 32)); - - /* Convert y to 1.31 format */ - return (y << 1u); - } - } - - - /** - * - * @brief Process function for the Q15 Linear Interpolation Function. - * @param[in] pYData pointer to Q15 Linear Interpolation table - * @param[in] x input sample to process - * @param[in] nValues number of table values - * @return y processed output sample. - * - * \par - * Input sample x is in 12.20 format which contains 12 bits for table index and 20 bits for fractional part. - * This function can support maximum of table size 2^12. - * - */ - static __INLINE q15_t arm_linear_interp_q15( - q15_t * pYData, - q31_t x, - uint32_t nValues) - { - q63_t y; /* output */ - q15_t y0, y1; /* Nearest output values */ - q31_t fract; /* fractional part */ - int32_t index; /* Index to read nearest output values */ - - /* Input is in 12.20 format */ - /* 12 bits for the table index */ - /* Index value calculation */ - index = ((x & (int32_t)0xFFF00000) >> 20); - - if(index >= (int32_t)(nValues - 1)) - { - return (pYData[nValues - 1]); - } - else if(index < 0) - { - return (pYData[0]); - } - else - { - /* 20 bits for the fractional part */ - /* fract is in 12.20 format */ - fract = (x & 0x000FFFFF); - - /* Read two nearest output values from the index */ - y0 = pYData[index]; - y1 = pYData[index + 1]; - - /* Calculation of y0 * (1-fract) and y is in 13.35 format */ - y = ((q63_t) y0 * (0xFFFFF - fract)); - - /* Calculation of (y0 * (1-fract) + y1 * fract) and y is in 13.35 format */ - y += ((q63_t) y1 * (fract)); - - /* convert y to 1.15 format */ - return (q15_t) (y >> 20); - } - } - - - /** - * - * @brief Process function for the Q7 Linear Interpolation Function. - * @param[in] pYData pointer to Q7 Linear Interpolation table - * @param[in] x input sample to process - * @param[in] nValues number of table values - * @return y processed output sample. - * - * \par - * Input sample x is in 12.20 format which contains 12 bits for table index and 20 bits for fractional part. - * This function can support maximum of table size 2^12. - */ - static __INLINE q7_t arm_linear_interp_q7( - q7_t * pYData, - q31_t x, - uint32_t nValues) - { - q31_t y; /* output */ - q7_t y0, y1; /* Nearest output values */ - q31_t fract; /* fractional part */ - uint32_t index; /* Index to read nearest output values */ - - /* Input is in 12.20 format */ - /* 12 bits for the table index */ - /* Index value calculation */ - if (x < 0) - { - return (pYData[0]); - } - index = (x >> 20) & 0xfff; - - if(index >= (nValues - 1)) - { - return (pYData[nValues - 1]); - } - else - { - /* 20 bits for the fractional part */ - /* fract is in 12.20 format */ - fract = (x & 0x000FFFFF); - - /* Read two nearest output values from the index and are in 1.7(q7) format */ - y0 = pYData[index]; - y1 = pYData[index + 1]; - - /* Calculation of y0 * (1-fract ) and y is in 13.27(q27) format */ - y = ((y0 * (0xFFFFF - fract))); - - /* Calculation of y1 * fract + y0 * (1-fract) and y is in 13.27(q27) format */ - y += (y1 * fract); - - /* convert y to 1.7(q7) format */ - return (q7_t) (y >> 20); - } - } - - /** - * @} end of LinearInterpolate group - */ - - /** - * @brief Fast approximation to the trigonometric sine function for floating-point data. - * @param[in] x input value in radians. - * @return sin(x). - */ - float32_t arm_sin_f32( - float32_t x); - - - /** - * @brief Fast approximation to the trigonometric sine function for Q31 data. - * @param[in] x Scaled input value in radians. - * @return sin(x). - */ - q31_t arm_sin_q31( - q31_t x); - - - /** - * @brief Fast approximation to the trigonometric sine function for Q15 data. - * @param[in] x Scaled input value in radians. - * @return sin(x). - */ - q15_t arm_sin_q15( - q15_t x); - - - /** - * @brief Fast approximation to the trigonometric cosine function for floating-point data. - * @param[in] x input value in radians. - * @return cos(x). - */ - float32_t arm_cos_f32( - float32_t x); - - - /** - * @brief Fast approximation to the trigonometric cosine function for Q31 data. - * @param[in] x Scaled input value in radians. - * @return cos(x). - */ - q31_t arm_cos_q31( - q31_t x); - - - /** - * @brief Fast approximation to the trigonometric cosine function for Q15 data. - * @param[in] x Scaled input value in radians. - * @return cos(x). - */ - q15_t arm_cos_q15( - q15_t x); - - - /** - * @ingroup groupFastMath - */ - - - /** - * @defgroup SQRT Square Root - * - * Computes the square root of a number. - * There are separate functions for Q15, Q31, and floating-point data types. - * The square root function is computed using the Newton-Raphson algorithm. - * This is an iterative algorithm of the form: - * 
-   *      x1 = x0 - f(x0)/f'(x0)
-   *
- * where x1 is the current estimate, - * x0 is the previous estimate, and - * f'(x0) is the derivative of f() evaluated at x0. - * For the square root function, the algorithm reduces to: - * 
-   *     x0 = in/2                         [initial guess]
-   *     x1 = 1/2 * ( x0 + in / x0)        [each iteration]
-   *
- */ - - - /** - * @addtogroup SQRT - * @{ - */ - - /** - * @brief Floating-point square root function. - * @param[in] in input value. - * @param[out] pOut square root of input value. - * @return The function returns ARM_MATH_SUCCESS if input value is positive value or ARM_MATH_ARGUMENT_ERROR if - * in is negative value and returns zero output for negative values. - */ - static __INLINE arm_status arm_sqrt_f32( - float32_t in, - float32_t * pOut) - { - if(in >= 0.0f) - { - -#if (__FPU_USED == 1) && defined ( __CC_ARM ) - *pOut = __sqrtf(in); -#elif (__FPU_USED == 1) && (defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)) - *pOut = __builtin_sqrtf(in); -#elif (__FPU_USED == 1) && defined(__GNUC__) - *pOut = __builtin_sqrtf(in); -#elif (__FPU_USED == 1) && defined ( __ICCARM__ ) && (__VER__ >= 6040000) - __ASM("VSQRT.F32 %0,%1" : "=t"(*pOut) : "t"(in)); -#else - *pOut = sqrtf(in); -#endif - - return (ARM_MATH_SUCCESS); - } - else - { - *pOut = 0.0f; - return (ARM_MATH_ARGUMENT_ERROR); - } - } - - - /** - * @brief Q31 square root function. - * @param[in] in input value. The range of the input value is [0 +1) or 0x00000000 to 0x7FFFFFFF. - * @param[out] pOut square root of input value. - * @return The function returns ARM_MATH_SUCCESS if input value is positive value or ARM_MATH_ARGUMENT_ERROR if - * in is negative value and returns zero output for negative values. - */ - arm_status arm_sqrt_q31( - q31_t in, - q31_t * pOut); - - - /** - * @brief Q15 square root function. - * @param[in] in input value. The range of the input value is [0 +1) or 0x0000 to 0x7FFF. - * @param[out] pOut square root of input value. - * @return The function returns ARM_MATH_SUCCESS if input value is positive value or ARM_MATH_ARGUMENT_ERROR if - * in is negative value and returns zero output for negative values. - */ - arm_status arm_sqrt_q15( - q15_t in, - q15_t * pOut); - - /** - * @} end of SQRT group - */ - - - /** - * @brief floating-point Circular write function. - */ - static __INLINE void arm_circularWrite_f32( - int32_t * circBuffer, - int32_t L, - uint16_t * writeOffset, - int32_t bufferInc, - const int32_t * src, - int32_t srcInc, - uint32_t blockSize) - { - uint32_t i = 0u; - int32_t wOffset; - - /* Copy the value of Index pointer that points - * to the current location where the input samples to be copied */ - wOffset = *writeOffset; - - /* Loop over the blockSize */ - i = blockSize; - - while(i > 0u) - { - /* copy the input sample to the circular buffer */ - circBuffer[wOffset] = *src; - - /* Update the input pointer */ - src += srcInc; - - /* Circularly update wOffset. Watch out for positive and negative value */ - wOffset += bufferInc; - if(wOffset >= L) - wOffset -= L; - - /* Decrement the loop counter */ - i--; - } - - /* Update the index pointer */ - *writeOffset = (uint16_t)wOffset; - } - - - - /** - * @brief floating-point Circular Read function. - */ - static __INLINE void arm_circularRead_f32( - int32_t * circBuffer, - int32_t L, - int32_t * readOffset, - int32_t bufferInc, - int32_t * dst, - int32_t * dst_base, - int32_t dst_length, - int32_t dstInc, - uint32_t blockSize) - { - uint32_t i = 0u; - int32_t rOffset, dst_end; - - /* Copy the value of Index pointer that points - * to the current location from where the input samples to be read */ - rOffset = *readOffset; - dst_end = (int32_t) (dst_base + dst_length); - - /* Loop over the blockSize */ - i = blockSize; - - while(i > 0u) - { - /* copy the sample from the circular buffer to the destination buffer */ - *dst = circBuffer[rOffset]; - - /* Update the input pointer */ - dst += dstInc; - - if(dst == (int32_t *) dst_end) - { - dst = dst_base; - } - - /* Circularly update rOffset. Watch out for positive and negative value */ - rOffset += bufferInc; - - if(rOffset >= L) - { - rOffset -= L; - } - - /* Decrement the loop counter */ - i--; - } - - /* Update the index pointer */ - *readOffset = rOffset; - } - - - /** - * @brief Q15 Circular write function. - */ - static __INLINE void arm_circularWrite_q15( - q15_t * circBuffer, - int32_t L, - uint16_t * writeOffset, - int32_t bufferInc, - const q15_t * src, - int32_t srcInc, - uint32_t blockSize) - { - uint32_t i = 0u; - int32_t wOffset; - - /* Copy the value of Index pointer that points - * to the current location where the input samples to be copied */ - wOffset = *writeOffset; - - /* Loop over the blockSize */ - i = blockSize; - - while(i > 0u) - { - /* copy the input sample to the circular buffer */ - circBuffer[wOffset] = *src; - - /* Update the input pointer */ - src += srcInc; - - /* Circularly update wOffset. Watch out for positive and negative value */ - wOffset += bufferInc; - if(wOffset >= L) - wOffset -= L; - - /* Decrement the loop counter */ - i--; - } - - /* Update the index pointer */ - *writeOffset = (uint16_t)wOffset; - } - - - /** - * @brief Q15 Circular Read function. - */ - static __INLINE void arm_circularRead_q15( - q15_t * circBuffer, - int32_t L, - int32_t * readOffset, - int32_t bufferInc, - q15_t * dst, - q15_t * dst_base, - int32_t dst_length, - int32_t dstInc, - uint32_t blockSize) - { - uint32_t i = 0; - int32_t rOffset, dst_end; - - /* Copy the value of Index pointer that points - * to the current location from where the input samples to be read */ - rOffset = *readOffset; - - dst_end = (int32_t) (dst_base + dst_length); - - /* Loop over the blockSize */ - i = blockSize; - - while(i > 0u) - { - /* copy the sample from the circular buffer to the destination buffer */ - *dst = circBuffer[rOffset]; - - /* Update the input pointer */ - dst += dstInc; - - if(dst == (q15_t *) dst_end) - { - dst = dst_base; - } - - /* Circularly update wOffset. Watch out for positive and negative value */ - rOffset += bufferInc; - - if(rOffset >= L) - { - rOffset -= L; - } - - /* Decrement the loop counter */ - i--; - } - - /* Update the index pointer */ - *readOffset = rOffset; - } - - - /** - * @brief Q7 Circular write function. - */ - static __INLINE void arm_circularWrite_q7( - q7_t * circBuffer, - int32_t L, - uint16_t * writeOffset, - int32_t bufferInc, - const q7_t * src, - int32_t srcInc, - uint32_t blockSize) - { - uint32_t i = 0u; - int32_t wOffset; - - /* Copy the value of Index pointer that points - * to the current location where the input samples to be copied */ - wOffset = *writeOffset; - - /* Loop over the blockSize */ - i = blockSize; - - while(i > 0u) - { - /* copy the input sample to the circular buffer */ - circBuffer[wOffset] = *src; - - /* Update the input pointer */ - src += srcInc; - - /* Circularly update wOffset. Watch out for positive and negative value */ - wOffset += bufferInc; - if(wOffset >= L) - wOffset -= L; - - /* Decrement the loop counter */ - i--; - } - - /* Update the index pointer */ - *writeOffset = (uint16_t)wOffset; - } - - - /** - * @brief Q7 Circular Read function. - */ - static __INLINE void arm_circularRead_q7( - q7_t * circBuffer, - int32_t L, - int32_t * readOffset, - int32_t bufferInc, - q7_t * dst, - q7_t * dst_base, - int32_t dst_length, - int32_t dstInc, - uint32_t blockSize) - { - uint32_t i = 0; - int32_t rOffset, dst_end; - - /* Copy the value of Index pointer that points - * to the current location from where the input samples to be read */ - rOffset = *readOffset; - - dst_end = (int32_t) (dst_base + dst_length); - - /* Loop over the blockSize */ - i = blockSize; - - while(i > 0u) - { - /* copy the sample from the circular buffer to the destination buffer */ - *dst = circBuffer[rOffset]; - - /* Update the input pointer */ - dst += dstInc; - - if(dst == (q7_t *) dst_end) - { - dst = dst_base; - } - - /* Circularly update rOffset. Watch out for positive and negative value */ - rOffset += bufferInc; - - if(rOffset >= L) - { - rOffset -= L; - } - - /* Decrement the loop counter */ - i--; - } - - /* Update the index pointer */ - *readOffset = rOffset; - } - - - /** - * @brief Sum of the squares of the elements of a Q31 vector. - * @param[in] pSrc is input pointer - * @param[in] blockSize is the number of samples to process - * @param[out] pResult is output value. - */ - void arm_power_q31( - q31_t * pSrc, - uint32_t blockSize, - q63_t * pResult); - - - /** - * @brief Sum of the squares of the elements of a floating-point vector. - * @param[in] pSrc is input pointer - * @param[in] blockSize is the number of samples to process - * @param[out] pResult is output value. - */ - void arm_power_f32( - float32_t * pSrc, - uint32_t blockSize, - float32_t * pResult); - - - /** - * @brief Sum of the squares of the elements of a Q15 vector. - * @param[in] pSrc is input pointer - * @param[in] blockSize is the number of samples to process - * @param[out] pResult is output value. - */ - void arm_power_q15( - q15_t * pSrc, - uint32_t blockSize, - q63_t * pResult); - - - /** - * @brief Sum of the squares of the elements of a Q7 vector. - * @param[in] pSrc is input pointer - * @param[in] blockSize is the number of samples to process - * @param[out] pResult is output value. - */ - void arm_power_q7( - q7_t * pSrc, - uint32_t blockSize, - q31_t * pResult); - - - /** - * @brief Mean value of a Q7 vector. - * @param[in] pSrc is input pointer - * @param[in] blockSize is the number of samples to process - * @param[out] pResult is output value. - */ - void arm_mean_q7( - q7_t * pSrc, - uint32_t blockSize, - q7_t * pResult); - - - /** - * @brief Mean value of a Q15 vector. - * @param[in] pSrc is input pointer - * @param[in] blockSize is the number of samples to process - * @param[out] pResult is output value. - */ - void arm_mean_q15( - q15_t * pSrc, - uint32_t blockSize, - q15_t * pResult); - - - /** - * @brief Mean value of a Q31 vector. - * @param[in] pSrc is input pointer - * @param[in] blockSize is the number of samples to process - * @param[out] pResult is output value. - */ - void arm_mean_q31( - q31_t * pSrc, - uint32_t blockSize, - q31_t * pResult); - - - /** - * @brief Mean value of a floating-point vector. - * @param[in] pSrc is input pointer - * @param[in] blockSize is the number of samples to process - * @param[out] pResult is output value. - */ - void arm_mean_f32( - float32_t * pSrc, - uint32_t blockSize, - float32_t * pResult); - - - /** - * @brief Variance of the elements of a floating-point vector. - * @param[in] pSrc is input pointer - * @param[in] blockSize is the number of samples to process - * @param[out] pResult is output value. - */ - void arm_var_f32( - float32_t * pSrc, - uint32_t blockSize, - float32_t * pResult); - - - /** - * @brief Variance of the elements of a Q31 vector. - * @param[in] pSrc is input pointer - * @param[in] blockSize is the number of samples to process - * @param[out] pResult is output value. - */ - void arm_var_q31( - q31_t * pSrc, - uint32_t blockSize, - q31_t * pResult); - - - /** - * @brief Variance of the elements of a Q15 vector. - * @param[in] pSrc is input pointer - * @param[in] blockSize is the number of samples to process - * @param[out] pResult is output value. - */ - void arm_var_q15( - q15_t * pSrc, - uint32_t blockSize, - q15_t * pResult); - - - /** - * @brief Root Mean Square of the elements of a floating-point vector. - * @param[in] pSrc is input pointer - * @param[in] blockSize is the number of samples to process - * @param[out] pResult is output value. - */ - void arm_rms_f32( - float32_t * pSrc, - uint32_t blockSize, - float32_t * pResult); - - - /** - * @brief Root Mean Square of the elements of a Q31 vector. - * @param[in] pSrc is input pointer - * @param[in] blockSize is the number of samples to process - * @param[out] pResult is output value. - */ - void arm_rms_q31( - q31_t * pSrc, - uint32_t blockSize, - q31_t * pResult); - - - /** - * @brief Root Mean Square of the elements of a Q15 vector. - * @param[in] pSrc is input pointer - * @param[in] blockSize is the number of samples to process - * @param[out] pResult is output value. - */ - void arm_rms_q15( - q15_t * pSrc, - uint32_t blockSize, - q15_t * pResult); - - - /** - * @brief Standard deviation of the elements of a floating-point vector. - * @param[in] pSrc is input pointer - * @param[in] blockSize is the number of samples to process - * @param[out] pResult is output value. - */ - void arm_std_f32( - float32_t * pSrc, - uint32_t blockSize, - float32_t * pResult); - - - /** - * @brief Standard deviation of the elements of a Q31 vector. - * @param[in] pSrc is input pointer - * @param[in] blockSize is the number of samples to process - * @param[out] pResult is output value. - */ - void arm_std_q31( - q31_t * pSrc, - uint32_t blockSize, - q31_t * pResult); - - - /** - * @brief Standard deviation of the elements of a Q15 vector. - * @param[in] pSrc is input pointer - * @param[in] blockSize is the number of samples to process - * @param[out] pResult is output value. - */ - void arm_std_q15( - q15_t * pSrc, - uint32_t blockSize, - q15_t * pResult); - - - /** - * @brief Floating-point complex magnitude - * @param[in] pSrc points to the complex input vector - * @param[out] pDst points to the real output vector - * @param[in] numSamples number of complex samples in the input vector - */ - void arm_cmplx_mag_f32( - float32_t * pSrc, - float32_t * pDst, - uint32_t numSamples); - - - /** - * @brief Q31 complex magnitude - * @param[in] pSrc points to the complex input vector - * @param[out] pDst points to the real output vector - * @param[in] numSamples number of complex samples in the input vector - */ - void arm_cmplx_mag_q31( - q31_t * pSrc, - q31_t * pDst, - uint32_t numSamples); - - - /** - * @brief Q15 complex magnitude - * @param[in] pSrc points to the complex input vector - * @param[out] pDst points to the real output vector - * @param[in] numSamples number of complex samples in the input vector - */ - void arm_cmplx_mag_q15( - q15_t * pSrc, - q15_t * pDst, - uint32_t numSamples); - - - /** - * @brief Q15 complex dot product - * @param[in] pSrcA points to the first input vector - * @param[in] pSrcB points to the second input vector - * @param[in] numSamples number of complex samples in each vector - * @param[out] realResult real part of the result returned here - * @param[out] imagResult imaginary part of the result returned here - */ - void arm_cmplx_dot_prod_q15( - q15_t * pSrcA, - q15_t * pSrcB, - uint32_t numSamples, - q31_t * realResult, - q31_t * imagResult); - - - /** - * @brief Q31 complex dot product - * @param[in] pSrcA points to the first input vector - * @param[in] pSrcB points to the second input vector - * @param[in] numSamples number of complex samples in each vector - * @param[out] realResult real part of the result returned here - * @param[out] imagResult imaginary part of the result returned here - */ - void arm_cmplx_dot_prod_q31( - q31_t * pSrcA, - q31_t * pSrcB, - uint32_t numSamples, - q63_t * realResult, - q63_t * imagResult); - - - /** - * @brief Floating-point complex dot product - * @param[in] pSrcA points to the first input vector - * @param[in] pSrcB points to the second input vector - * @param[in] numSamples number of complex samples in each vector - * @param[out] realResult real part of the result returned here - * @param[out] imagResult imaginary part of the result returned here - */ - void arm_cmplx_dot_prod_f32( - float32_t * pSrcA, - float32_t * pSrcB, - uint32_t numSamples, - float32_t * realResult, - float32_t * imagResult); - - - /** - * @brief Q15 complex-by-real multiplication - * @param[in] pSrcCmplx points to the complex input vector - * @param[in] pSrcReal points to the real input vector - * @param[out] pCmplxDst points to the complex output vector - * @param[in] numSamples number of samples in each vector - */ - void arm_cmplx_mult_real_q15( - q15_t * pSrcCmplx, - q15_t * pSrcReal, - q15_t * pCmplxDst, - uint32_t numSamples); - - - /** - * @brief Q31 complex-by-real multiplication - * @param[in] pSrcCmplx points to the complex input vector - * @param[in] pSrcReal points to the real input vector - * @param[out] pCmplxDst points to the complex output vector - * @param[in] numSamples number of samples in each vector - */ - void arm_cmplx_mult_real_q31( - q31_t * pSrcCmplx, - q31_t * pSrcReal, - q31_t * pCmplxDst, - uint32_t numSamples); - - - /** - * @brief Floating-point complex-by-real multiplication - * @param[in] pSrcCmplx points to the complex input vector - * @param[in] pSrcReal points to the real input vector - * @param[out] pCmplxDst points to the complex output vector - * @param[in] numSamples number of samples in each vector - */ - void arm_cmplx_mult_real_f32( - float32_t * pSrcCmplx, - float32_t * pSrcReal, - float32_t * pCmplxDst, - uint32_t numSamples); - - - /** - * @brief Minimum value of a Q7 vector. - * @param[in] pSrc is input pointer - * @param[in] blockSize is the number of samples to process - * @param[out] result is output pointer - * @param[in] index is the array index of the minimum value in the input buffer. - */ - void arm_min_q7( - q7_t * pSrc, - uint32_t blockSize, - q7_t * result, - uint32_t * index); - - - /** - * @brief Minimum value of a Q15 vector. - * @param[in] pSrc is input pointer - * @param[in] blockSize is the number of samples to process - * @param[out] pResult is output pointer - * @param[in] pIndex is the array index of the minimum value in the input buffer. - */ - void arm_min_q15( - q15_t * pSrc, - uint32_t blockSize, - q15_t * pResult, - uint32_t * pIndex); - - - /** - * @brief Minimum value of a Q31 vector. - * @param[in] pSrc is input pointer - * @param[in] blockSize is the number of samples to process - * @param[out] pResult is output pointer - * @param[out] pIndex is the array index of the minimum value in the input buffer. - */ - void arm_min_q31( - q31_t * pSrc, - uint32_t blockSize, - q31_t * pResult, - uint32_t * pIndex); - - - /** - * @brief Minimum value of a floating-point vector. - * @param[in] pSrc is input pointer - * @param[in] blockSize is the number of samples to process - * @param[out] pResult is output pointer - * @param[out] pIndex is the array index of the minimum value in the input buffer. - */ - void arm_min_f32( - float32_t * pSrc, - uint32_t blockSize, - float32_t * pResult, - uint32_t * pIndex); - - -/** - * @brief Maximum value of a Q7 vector. - * @param[in] pSrc points to the input buffer - * @param[in] blockSize length of the input vector - * @param[out] pResult maximum value returned here - * @param[out] pIndex index of maximum value returned here - */ - void arm_max_q7( - q7_t * pSrc, - uint32_t blockSize, - q7_t * pResult, - uint32_t * pIndex); - - -/** - * @brief Maximum value of a Q15 vector. - * @param[in] pSrc points to the input buffer - * @param[in] blockSize length of the input vector - * @param[out] pResult maximum value returned here - * @param[out] pIndex index of maximum value returned here - */ - void arm_max_q15( - q15_t * pSrc, - uint32_t blockSize, - q15_t * pResult, - uint32_t * pIndex); - - -/** - * @brief Maximum value of a Q31 vector. - * @param[in] pSrc points to the input buffer - * @param[in] blockSize length of the input vector - * @param[out] pResult maximum value returned here - * @param[out] pIndex index of maximum value returned here - */ - void arm_max_q31( - q31_t * pSrc, - uint32_t blockSize, - q31_t * pResult, - uint32_t * pIndex); - - -/** - * @brief Maximum value of a floating-point vector. - * @param[in] pSrc points to the input buffer - * @param[in] blockSize length of the input vector - * @param[out] pResult maximum value returned here - * @param[out] pIndex index of maximum value returned here - */ - void arm_max_f32( - float32_t * pSrc, - uint32_t blockSize, - float32_t * pResult, - uint32_t * pIndex); - - - /** - * @brief Q15 complex-by-complex multiplication - * @param[in] pSrcA points to the first input vector - * @param[in] pSrcB points to the second input vector - * @param[out] pDst points to the output vector - * @param[in] numSamples number of complex samples in each vector - */ - void arm_cmplx_mult_cmplx_q15( - q15_t * pSrcA, - q15_t * pSrcB, - q15_t * pDst, - uint32_t numSamples); - - - /** - * @brief Q31 complex-by-complex multiplication - * @param[in] pSrcA points to the first input vector - * @param[in] pSrcB points to the second input vector - * @param[out] pDst points to the output vector - * @param[in] numSamples number of complex samples in each vector - */ - void arm_cmplx_mult_cmplx_q31( - q31_t * pSrcA, - q31_t * pSrcB, - q31_t * pDst, - uint32_t numSamples); - - - /** - * @brief Floating-point complex-by-complex multiplication - * @param[in] pSrcA points to the first input vector - * @param[in] pSrcB points to the second input vector - * @param[out] pDst points to the output vector - * @param[in] numSamples number of complex samples in each vector - */ - void arm_cmplx_mult_cmplx_f32( - float32_t * pSrcA, - float32_t * pSrcB, - float32_t * pDst, - uint32_t numSamples); - - - /** - * @brief Converts the elements of the floating-point vector to Q31 vector. - * @param[in] pSrc points to the floating-point input vector - * @param[out] pDst points to the Q31 output vector - * @param[in] blockSize length of the input vector - */ - void arm_float_to_q31( - float32_t * pSrc, - q31_t * pDst, - uint32_t blockSize); - - - /** - * @brief Converts the elements of the floating-point vector to Q15 vector. - * @param[in] pSrc points to the floating-point input vector - * @param[out] pDst points to the Q15 output vector - * @param[in] blockSize length of the input vector - */ - void arm_float_to_q15( - float32_t * pSrc, - q15_t * pDst, - uint32_t blockSize); - - - /** - * @brief Converts the elements of the floating-point vector to Q7 vector. - * @param[in] pSrc points to the floating-point input vector - * @param[out] pDst points to the Q7 output vector - * @param[in] blockSize length of the input vector - */ - void arm_float_to_q7( - float32_t * pSrc, - q7_t * pDst, - uint32_t blockSize); - - - /** - * @brief Converts the elements of the Q31 vector to Q15 vector. - * @param[in] pSrc is input pointer - * @param[out] pDst is output pointer - * @param[in] blockSize is the number of samples to process - */ - void arm_q31_to_q15( - q31_t * pSrc, - q15_t * pDst, - uint32_t blockSize); - - - /** - * @brief Converts the elements of the Q31 vector to Q7 vector. - * @param[in] pSrc is input pointer - * @param[out] pDst is output pointer - * @param[in] blockSize is the number of samples to process - */ - void arm_q31_to_q7( - q31_t * pSrc, - q7_t * pDst, - uint32_t blockSize); - - - /** - * @brief Converts the elements of the Q15 vector to floating-point vector. - * @param[in] pSrc is input pointer - * @param[out] pDst is output pointer - * @param[in] blockSize is the number of samples to process - */ - void arm_q15_to_float( - q15_t * pSrc, - float32_t * pDst, - uint32_t blockSize); - - - /** - * @brief Converts the elements of the Q15 vector to Q31 vector. - * @param[in] pSrc is input pointer - * @param[out] pDst is output pointer - * @param[in] blockSize is the number of samples to process - */ - void arm_q15_to_q31( - q15_t * pSrc, - q31_t * pDst, - uint32_t blockSize); - - - /** - * @brief Converts the elements of the Q15 vector to Q7 vector. - * @param[in] pSrc is input pointer - * @param[out] pDst is output pointer - * @param[in] blockSize is the number of samples to process - */ - void arm_q15_to_q7( - q15_t * pSrc, - q7_t * pDst, - uint32_t blockSize); - - - /** - * @ingroup groupInterpolation - */ - - /** - * @defgroup BilinearInterpolate Bilinear Interpolation - * - * Bilinear interpolation is an extension of linear interpolation applied to a two dimensional grid. - * The underlying function f(x, y) is sampled on a regular grid and the interpolation process - * determines values between the grid points. - * Bilinear interpolation is equivalent to two step linear interpolation, first in the x-dimension and then in the y-dimension. - * Bilinear interpolation is often used in image processing to rescale images. - * The CMSIS DSP library provides bilinear interpolation functions for Q7, Q15, Q31, and floating-point data types. - * - * Algorithm - * \par - * The instance structure used by the bilinear interpolation functions describes a two dimensional data table. - * For floating-point, the instance structure is defined as: - * 
-   *   typedef struct
-   *   {
-   *     uint16_t numRows;
-   *     uint16_t numCols;
-   *     float32_t *pData;
-   * } arm_bilinear_interp_instance_f32;
-   *
- * - * \par - * where numRows specifies the number of rows in the table; - * numCols specifies the number of columns in the table; - * and pData points to an array of size numRows*numCols values. - * The data table pTable is organized in row order and the supplied data values fall on integer indexes. - * That is, table element (x,y) is located at pTable[x + y*numCols] where x and y are integers. - * - * \par - * Let (x, y) specify the desired interpolation point. Then define: - * 
-   *     XF = floor(x)
-   *     YF = floor(y)
-   *
- * \par - * The interpolated output point is computed as: - * 
-   *  f(x, y) = f(XF, YF) * (1-(x-XF)) * (1-(y-YF))
-   *           + f(XF+1, YF) * (x-XF)*(1-(y-YF))
-   *           + f(XF, YF+1) * (1-(x-XF))*(y-YF)
-   *           + f(XF+1, YF+1) * (x-XF)*(y-YF)
-   *
- * Note that the coordinates (x, y) contain integer and fractional components. - * The integer components specify which portion of the table to use while the - * fractional components control the interpolation processor. - * - * \par - * if (x,y) are outside of the table boundary, Bilinear interpolation returns zero output. - */ - - /** - * @addtogroup BilinearInterpolate - * @{ - */ - - - /** - * - * @brief Floating-point bilinear interpolation. - * @param[in,out] S points to an instance of the interpolation structure. - * @param[in] X interpolation coordinate. - * @param[in] Y interpolation coordinate. - * @return out interpolated value. - */ - static __INLINE float32_t arm_bilinear_interp_f32( - const arm_bilinear_interp_instance_f32 * S, - float32_t X, - float32_t Y) - { - float32_t out; - float32_t f00, f01, f10, f11; - float32_t *pData = S->pData; - int32_t xIndex, yIndex, index; - float32_t xdiff, ydiff; - float32_t b1, b2, b3, b4; - - xIndex = (int32_t) X; - yIndex = (int32_t) Y; - - /* Care taken for table outside boundary */ - /* Returns zero output when values are outside table boundary */ - if(xIndex < 0 || xIndex > (S->numRows - 1) || yIndex < 0 || yIndex > (S->numCols - 1)) - { - return (0); - } - - /* Calculation of index for two nearest points in X-direction */ - index = (xIndex - 1) + (yIndex - 1) * S->numCols; - - - /* Read two nearest points in X-direction */ - f00 = pData[index]; - f01 = pData[index + 1]; - - /* Calculation of index for two nearest points in Y-direction */ - index = (xIndex - 1) + (yIndex) * S->numCols; - - - /* Read two nearest points in Y-direction */ - f10 = pData[index]; - f11 = pData[index + 1]; - - /* Calculation of intermediate values */ - b1 = f00; - b2 = f01 - f00; - b3 = f10 - f00; - b4 = f00 - f01 - f10 + f11; - - /* Calculation of fractional part in X */ - xdiff = X - xIndex; - - /* Calculation of fractional part in Y */ - ydiff = Y - yIndex; - - /* Calculation of bi-linear interpolated output */ - out = b1 + b2 * xdiff + b3 * ydiff + b4 * xdiff * ydiff; - - /* return to application */ - return (out); - } - - - /** - * - * @brief Q31 bilinear interpolation. - * @param[in,out] S points to an instance of the interpolation structure. - * @param[in] X interpolation coordinate in 12.20 format. - * @param[in] Y interpolation coordinate in 12.20 format. - * @return out interpolated value. - */ - static __INLINE q31_t arm_bilinear_interp_q31( - arm_bilinear_interp_instance_q31 * S, - q31_t X, - q31_t Y) - { - q31_t out; /* Temporary output */ - q31_t acc = 0; /* output */ - q31_t xfract, yfract; /* X, Y fractional parts */ - q31_t x1, x2, y1, y2; /* Nearest output values */ - int32_t rI, cI; /* Row and column indices */ - q31_t *pYData = S->pData; /* pointer to output table values */ - uint32_t nCols = S->numCols; /* num of rows */ - - /* Input is in 12.20 format */ - /* 12 bits for the table index */ - /* Index value calculation */ - rI = ((X & (q31_t)0xFFF00000) >> 20); - - /* Input is in 12.20 format */ - /* 12 bits for the table index */ - /* Index value calculation */ - cI = ((Y & (q31_t)0xFFF00000) >> 20); - - /* Care taken for table outside boundary */ - /* Returns zero output when values are outside table boundary */ - if(rI < 0 || rI > (S->numRows - 1) || cI < 0 || cI > (S->numCols - 1)) - { - return (0); - } - - /* 20 bits for the fractional part */ - /* shift left xfract by 11 to keep 1.31 format */ - xfract = (X & 0x000FFFFF) << 11u; - - /* Read two nearest output values from the index */ - x1 = pYData[(rI) + (int32_t)nCols * (cI) ]; - x2 = pYData[(rI) + (int32_t)nCols * (cI) + 1]; - - /* 20 bits for the fractional part */ - /* shift left yfract by 11 to keep 1.31 format */ - yfract = (Y & 0x000FFFFF) << 11u; - - /* Read two nearest output values from the index */ - y1 = pYData[(rI) + (int32_t)nCols * (cI + 1) ]; - y2 = pYData[(rI) + (int32_t)nCols * (cI + 1) + 1]; - - /* Calculation of x1 * (1-xfract ) * (1-yfract) and acc is in 3.29(q29) format */ - out = ((q31_t) (((q63_t) x1 * (0x7FFFFFFF - xfract)) >> 32)); - acc = ((q31_t) (((q63_t) out * (0x7FFFFFFF - yfract)) >> 32)); - - /* x2 * (xfract) * (1-yfract) in 3.29(q29) and adding to acc */ - out = ((q31_t) ((q63_t) x2 * (0x7FFFFFFF - yfract) >> 32)); - acc += ((q31_t) ((q63_t) out * (xfract) >> 32)); - - /* y1 * (1 - xfract) * (yfract) in 3.29(q29) and adding to acc */ - out = ((q31_t) ((q63_t) y1 * (0x7FFFFFFF - xfract) >> 32)); - acc += ((q31_t) ((q63_t) out * (yfract) >> 32)); - - /* y2 * (xfract) * (yfract) in 3.29(q29) and adding to acc */ - out = ((q31_t) ((q63_t) y2 * (xfract) >> 32)); - acc += ((q31_t) ((q63_t) out * (yfract) >> 32)); - - /* Convert acc to 1.31(q31) format */ - return ((q31_t)(acc << 2)); - } - - - /** - * @brief Q15 bilinear interpolation. - * @param[in,out] S points to an instance of the interpolation structure. - * @param[in] X interpolation coordinate in 12.20 format. - * @param[in] Y interpolation coordinate in 12.20 format. - * @return out interpolated value. - */ - static __INLINE q15_t arm_bilinear_interp_q15( - arm_bilinear_interp_instance_q15 * S, - q31_t X, - q31_t Y) - { - q63_t acc = 0; /* output */ - q31_t out; /* Temporary output */ - q15_t x1, x2, y1, y2; /* Nearest output values */ - q31_t xfract, yfract; /* X, Y fractional parts */ - int32_t rI, cI; /* Row and column indices */ - q15_t *pYData = S->pData; /* pointer to output table values */ - uint32_t nCols = S->numCols; /* num of rows */ - - /* Input is in 12.20 format */ - /* 12 bits for the table index */ - /* Index value calculation */ - rI = ((X & (q31_t)0xFFF00000) >> 20); - - /* Input is in 12.20 format */ - /* 12 bits for the table index */ - /* Index value calculation */ - cI = ((Y & (q31_t)0xFFF00000) >> 20); - - /* Care taken for table outside boundary */ - /* Returns zero output when values are outside table boundary */ - if(rI < 0 || rI > (S->numRows - 1) || cI < 0 || cI > (S->numCols - 1)) - { - return (0); - } - - /* 20 bits for the fractional part */ - /* xfract should be in 12.20 format */ - xfract = (X & 0x000FFFFF); - - /* Read two nearest output values from the index */ - x1 = pYData[((uint32_t)rI) + nCols * ((uint32_t)cI) ]; - x2 = pYData[((uint32_t)rI) + nCols * ((uint32_t)cI) + 1]; - - /* 20 bits for the fractional part */ - /* yfract should be in 12.20 format */ - yfract = (Y & 0x000FFFFF); - - /* Read two nearest output values from the index */ - y1 = pYData[((uint32_t)rI) + nCols * ((uint32_t)cI + 1) ]; - y2 = pYData[((uint32_t)rI) + nCols * ((uint32_t)cI + 1) + 1]; - - /* Calculation of x1 * (1-xfract ) * (1-yfract) and acc is in 13.51 format */ - - /* x1 is in 1.15(q15), xfract in 12.20 format and out is in 13.35 format */ - /* convert 13.35 to 13.31 by right shifting and out is in 1.31 */ - out = (q31_t) (((q63_t) x1 * (0xFFFFF - xfract)) >> 4u); - acc = ((q63_t) out * (0xFFFFF - yfract)); - - /* x2 * (xfract) * (1-yfract) in 1.51 and adding to acc */ - out = (q31_t) (((q63_t) x2 * (0xFFFFF - yfract)) >> 4u); - acc += ((q63_t) out * (xfract)); - - /* y1 * (1 - xfract) * (yfract) in 1.51 and adding to acc */ - out = (q31_t) (((q63_t) y1 * (0xFFFFF - xfract)) >> 4u); - acc += ((q63_t) out * (yfract)); - - /* y2 * (xfract) * (yfract) in 1.51 and adding to acc */ - out = (q31_t) (((q63_t) y2 * (xfract)) >> 4u); - acc += ((q63_t) out * (yfract)); - - /* acc is in 13.51 format and down shift acc by 36 times */ - /* Convert out to 1.15 format */ - return ((q15_t)(acc >> 36)); - } - - - /** - * @brief Q7 bilinear interpolation. - * @param[in,out] S points to an instance of the interpolation structure. - * @param[in] X interpolation coordinate in 12.20 format. - * @param[in] Y interpolation coordinate in 12.20 format. - * @return out interpolated value. - */ - static __INLINE q7_t arm_bilinear_interp_q7( - arm_bilinear_interp_instance_q7 * S, - q31_t X, - q31_t Y) - { - q63_t acc = 0; /* output */ - q31_t out; /* Temporary output */ - q31_t xfract, yfract; /* X, Y fractional parts */ - q7_t x1, x2, y1, y2; /* Nearest output values */ - int32_t rI, cI; /* Row and column indices */ - q7_t *pYData = S->pData; /* pointer to output table values */ - uint32_t nCols = S->numCols; /* num of rows */ - - /* Input is in 12.20 format */ - /* 12 bits for the table index */ - /* Index value calculation */ - rI = ((X & (q31_t)0xFFF00000) >> 20); - - /* Input is in 12.20 format */ - /* 12 bits for the table index */ - /* Index value calculation */ - cI = ((Y & (q31_t)0xFFF00000) >> 20); - - /* Care taken for table outside boundary */ - /* Returns zero output when values are outside table boundary */ - if(rI < 0 || rI > (S->numRows - 1) || cI < 0 || cI > (S->numCols - 1)) - { - return (0); - } - - /* 20 bits for the fractional part */ - /* xfract should be in 12.20 format */ - xfract = (X & (q31_t)0x000FFFFF); - - /* Read two nearest output values from the index */ - x1 = pYData[((uint32_t)rI) + nCols * ((uint32_t)cI) ]; - x2 = pYData[((uint32_t)rI) + nCols * ((uint32_t)cI) + 1]; - - /* 20 bits for the fractional part */ - /* yfract should be in 12.20 format */ - yfract = (Y & (q31_t)0x000FFFFF); - - /* Read two nearest output values from the index */ - y1 = pYData[((uint32_t)rI) + nCols * ((uint32_t)cI + 1) ]; - y2 = pYData[((uint32_t)rI) + nCols * ((uint32_t)cI + 1) + 1]; - - /* Calculation of x1 * (1-xfract ) * (1-yfract) and acc is in 16.47 format */ - out = ((x1 * (0xFFFFF - xfract))); - acc = (((q63_t) out * (0xFFFFF - yfract))); - - /* x2 * (xfract) * (1-yfract) in 2.22 and adding to acc */ - out = ((x2 * (0xFFFFF - yfract))); - acc += (((q63_t) out * (xfract))); - - /* y1 * (1 - xfract) * (yfract) in 2.22 and adding to acc */ - out = ((y1 * (0xFFFFF - xfract))); - acc += (((q63_t) out * (yfract))); - - /* y2 * (xfract) * (yfract) in 2.22 and adding to acc */ - out = ((y2 * (yfract))); - acc += (((q63_t) out * (xfract))); - - /* acc in 16.47 format and down shift by 40 to convert to 1.7 format */ - return ((q7_t)(acc >> 40)); - } - - /** - * @} end of BilinearInterpolate group - */ - - -/* SMMLAR */ -#define multAcc_32x32_keep32_R(a, x, y) \ - a = (q31_t) (((((q63_t) a) << 32) + ((q63_t) x * y) + 0x80000000LL ) >> 32) - -/* SMMLSR */ -#define multSub_32x32_keep32_R(a, x, y) \ - a = (q31_t) (((((q63_t) a) << 32) - ((q63_t) x * y) + 0x80000000LL ) >> 32) - -/* SMMULR */ -#define mult_32x32_keep32_R(a, x, y) \ - a = (q31_t) (((q63_t) x * y + 0x80000000LL ) >> 32) - -/* SMMLA */ -#define multAcc_32x32_keep32(a, x, y) \ - a += (q31_t) (((q63_t) x * y) >> 32) - -/* SMMLS */ -#define multSub_32x32_keep32(a, x, y) \ - a -= (q31_t) (((q63_t) x * y) >> 32) - -/* SMMUL */ -#define mult_32x32_keep32(a, x, y) \ - a = (q31_t) (((q63_t) x * y ) >> 32) - - -#if defined ( __CC_ARM ) - /* Enter low optimization region - place directly above function definition */ - #if defined( ARM_MATH_CM4 ) || defined( ARM_MATH_CM7) - #define LOW_OPTIMIZATION_ENTER \ - _Pragma ("push") \ - _Pragma ("O1") - #else - #define LOW_OPTIMIZATION_ENTER - #endif - - /* Exit low optimization region - place directly after end of function definition */ - #if defined( ARM_MATH_CM4 ) || defined( ARM_MATH_CM7) - #define LOW_OPTIMIZATION_EXIT \ - _Pragma ("pop") - #else - #define LOW_OPTIMIZATION_EXIT - #endif - - /* Enter low optimization region - place directly above function definition */ - #define IAR_ONLY_LOW_OPTIMIZATION_ENTER - - /* Exit low optimization region - place directly after end of function definition */ - #define IAR_ONLY_LOW_OPTIMIZATION_EXIT - -#elif defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) - #define LOW_OPTIMIZATION_ENTER - #define LOW_OPTIMIZATION_EXIT - #define IAR_ONLY_LOW_OPTIMIZATION_ENTER - #define IAR_ONLY_LOW_OPTIMIZATION_EXIT - -#elif defined(__GNUC__) - #define LOW_OPTIMIZATION_ENTER __attribute__(( optimize("-O1") )) - #define LOW_OPTIMIZATION_EXIT - #define IAR_ONLY_LOW_OPTIMIZATION_ENTER - #define IAR_ONLY_LOW_OPTIMIZATION_EXIT - -#elif defined(__ICCARM__) - /* Enter low optimization region - place directly above function definition */ - #if defined( ARM_MATH_CM4 ) || defined( ARM_MATH_CM7) - #define LOW_OPTIMIZATION_ENTER \ - _Pragma ("optimize=low") - #else - #define LOW_OPTIMIZATION_ENTER - #endif - - /* Exit low optimization region - place directly after end of function definition */ - #define LOW_OPTIMIZATION_EXIT - - /* Enter low optimization region - place directly above function definition */ - #if defined( ARM_MATH_CM4 ) || defined( ARM_MATH_CM7) - #define IAR_ONLY_LOW_OPTIMIZATION_ENTER \ - _Pragma ("optimize=low") - #else - #define IAR_ONLY_LOW_OPTIMIZATION_ENTER - #endif - - /* Exit low optimization region - place directly after end of function definition */ - #define IAR_ONLY_LOW_OPTIMIZATION_EXIT - -#elif defined(__CSMC__) - #define LOW_OPTIMIZATION_ENTER - #define LOW_OPTIMIZATION_EXIT - #define IAR_ONLY_LOW_OPTIMIZATION_ENTER - #define IAR_ONLY_LOW_OPTIMIZATION_EXIT - -#elif defined(__TASKING__) - #define LOW_OPTIMIZATION_ENTER - #define LOW_OPTIMIZATION_EXIT - #define IAR_ONLY_LOW_OPTIMIZATION_ENTER - #define IAR_ONLY_LOW_OPTIMIZATION_EXIT - -#endif - - -#ifdef __cplusplus -} -#endif - - -#if defined ( __GNUC__ ) -#pragma GCC diagnostic pop -#endif - -#endif /* _ARM_MATH_H */ - -/** - * - * End of file. - */ diff --git a/bsp/essemi/es32f0334/libraries/CMSIS/Include/cmsis_armcc.h b/bsp/essemi/es32f0334/libraries/CMSIS/Include/cmsis_armcc.h deleted file mode 100644 index 74c49c67de..0000000000 --- a/bsp/essemi/es32f0334/libraries/CMSIS/Include/cmsis_armcc.h +++ /dev/null @@ -1,734 +0,0 @@ -/**************************************************************************//** - * @file cmsis_armcc.h - * @brief CMSIS Cortex-M Core Function/Instruction Header File - * @version V4.30 - * @date 20. October 2015 - ******************************************************************************/ -/* Copyright (c) 2009 - 2015 ARM LIMITED - - All rights reserved. - Redistribution and use in source and binary forms, with or without - modification, are permitted provided that the following conditions are met: - - Redistributions of source code must retain the above copyright - notice, this list of conditions and the following disclaimer. - - Redistributions in binary form must reproduce the above copyright - notice, this list of conditions and the following disclaimer in the - documentation and/or other materials provided with the distribution. - - Neither the name of ARM nor the names of its contributors may be used - to endorse or promote products derived from this software without - specific prior written permission. - * - THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" - AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE - ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE - LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR - CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF - SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS - INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN - CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) - ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE - POSSIBILITY OF SUCH DAMAGE. - ---------------------------------------------------------------------------*/ - - -#ifndef __CMSIS_ARMCC_H -#define __CMSIS_ARMCC_H - - -#if defined(__ARMCC_VERSION) && (__ARMCC_VERSION < 400677) - #error "Please use ARM Compiler Toolchain V4.0.677 or later!" -#endif - -/* ########################### Core Function Access ########################### */ -/** \ingroup CMSIS_Core_FunctionInterface - \defgroup CMSIS_Core_RegAccFunctions CMSIS Core Register Access Functions - @{ - */ - -/* intrinsic void __enable_irq(); */ -/* intrinsic void __disable_irq(); */ - -/** - \brief Get Control Register - \details Returns the content of the Control Register. - \return Control Register value - */ -__STATIC_INLINE uint32_t __get_CONTROL(void) -{ - register uint32_t __regControl __ASM("control"); - return(__regControl); -} - - -/** - \brief Set Control Register - \details Writes the given value to the Control Register. - \param [in] control Control Register value to set - */ -__STATIC_INLINE void __set_CONTROL(uint32_t control) -{ - register uint32_t __regControl __ASM("control"); - __regControl = control; -} - - -/** - \brief Get IPSR Register - \details Returns the content of the IPSR Register. - \return IPSR Register value - */ -__STATIC_INLINE uint32_t __get_IPSR(void) -{ - register uint32_t __regIPSR __ASM("ipsr"); - return(__regIPSR); -} - - -/** - \brief Get APSR Register - \details Returns the content of the APSR Register. - \return APSR Register value - */ -__STATIC_INLINE uint32_t __get_APSR(void) -{ - register uint32_t __regAPSR __ASM("apsr"); - return(__regAPSR); -} - - -/** - \brief Get xPSR Register - \details Returns the content of the xPSR Register. - \return xPSR Register value - */ -__STATIC_INLINE uint32_t __get_xPSR(void) -{ - register uint32_t __regXPSR __ASM("xpsr"); - return(__regXPSR); -} - - -/** - \brief Get Process Stack Pointer - \details Returns the current value of the Process Stack Pointer (PSP). - \return PSP Register value - */ -__STATIC_INLINE uint32_t __get_PSP(void) -{ - register uint32_t __regProcessStackPointer __ASM("psp"); - return(__regProcessStackPointer); -} - - -/** - \brief Set Process Stack Pointer - \details Assigns the given value to the Process Stack Pointer (PSP). - \param [in] topOfProcStack Process Stack Pointer value to set - */ -__STATIC_INLINE void __set_PSP(uint32_t topOfProcStack) -{ - register uint32_t __regProcessStackPointer __ASM("psp"); - __regProcessStackPointer = topOfProcStack; -} - - -/** - \brief Get Main Stack Pointer - \details Returns the current value of the Main Stack Pointer (MSP). - \return MSP Register value - */ -__STATIC_INLINE uint32_t __get_MSP(void) -{ - register uint32_t __regMainStackPointer __ASM("msp"); - return(__regMainStackPointer); -} - - -/** - \brief Set Main Stack Pointer - \details Assigns the given value to the Main Stack Pointer (MSP). - \param [in] topOfMainStack Main Stack Pointer value to set - */ -__STATIC_INLINE void __set_MSP(uint32_t topOfMainStack) -{ - register uint32_t __regMainStackPointer __ASM("msp"); - __regMainStackPointer = topOfMainStack; -} - - -/** - \brief Get Priority Mask - \details Returns the current state of the priority mask bit from the Priority Mask Register. - \return Priority Mask value - */ -__STATIC_INLINE uint32_t __get_PRIMASK(void) -{ - register uint32_t __regPriMask __ASM("primask"); - return(__regPriMask); -} - - -/** - \brief Set Priority Mask - \details Assigns the given value to the Priority Mask Register. - \param [in] priMask Priority Mask - */ -__STATIC_INLINE void __set_PRIMASK(uint32_t priMask) -{ - register uint32_t __regPriMask __ASM("primask"); - __regPriMask = (priMask); -} - - -#if (__CORTEX_M >= 0x03U) || (__CORTEX_SC >= 300U) - -/** - \brief Enable FIQ - \details Enables FIQ interrupts by clearing the F-bit in the CPSR. - Can only be executed in Privileged modes. - */ -#define __enable_fault_irq __enable_fiq - - -/** - \brief Disable FIQ - \details Disables FIQ interrupts by setting the F-bit in the CPSR. - Can only be executed in Privileged modes. - */ -#define __disable_fault_irq __disable_fiq - - -/** - \brief Get Base Priority - \details Returns the current value of the Base Priority register. - \return Base Priority register value - */ -__STATIC_INLINE uint32_t __get_BASEPRI(void) -{ - register uint32_t __regBasePri __ASM("basepri"); - return(__regBasePri); -} - - -/** - \brief Set Base Priority - \details Assigns the given value to the Base Priority register. - \param [in] basePri Base Priority value to set - */ -__STATIC_INLINE void __set_BASEPRI(uint32_t basePri) -{ - register uint32_t __regBasePri __ASM("basepri"); - __regBasePri = (basePri & 0xFFU); -} - - -/** - \brief Set Base Priority with condition - \details Assigns the given value to the Base Priority register only if BASEPRI masking is disabled, - or the new value increases the BASEPRI priority level. - \param [in] basePri Base Priority value to set - */ -__STATIC_INLINE void __set_BASEPRI_MAX(uint32_t basePri) -{ - register uint32_t __regBasePriMax __ASM("basepri_max"); - __regBasePriMax = (basePri & 0xFFU); -} - - -/** - \brief Get Fault Mask - \details Returns the current value of the Fault Mask register. - \return Fault Mask register value - */ -__STATIC_INLINE uint32_t __get_FAULTMASK(void) -{ - register uint32_t __regFaultMask __ASM("faultmask"); - return(__regFaultMask); -} - - -/** - \brief Set Fault Mask - \details Assigns the given value to the Fault Mask register. - \param [in] faultMask Fault Mask value to set - */ -__STATIC_INLINE void __set_FAULTMASK(uint32_t faultMask) -{ - register uint32_t __regFaultMask __ASM("faultmask"); - __regFaultMask = (faultMask & (uint32_t)1); -} - -#endif /* (__CORTEX_M >= 0x03U) || (__CORTEX_SC >= 300U) */ - - -#if (__CORTEX_M == 0x04U) || (__CORTEX_M == 0x07U) - -/** - \brief Get FPSCR - \details Returns the current value of the Floating Point Status/Control register. - \return Floating Point Status/Control register value - */ -__STATIC_INLINE uint32_t __get_FPSCR(void) -{ -#if (__FPU_PRESENT == 1U) && (__FPU_USED == 1U) - register uint32_t __regfpscr __ASM("fpscr"); - return(__regfpscr); -#else - return(0U); -#endif -} - - -/** - \brief Set FPSCR - \details Assigns the given value to the Floating Point Status/Control register. - \param [in] fpscr Floating Point Status/Control value to set - */ -__STATIC_INLINE void __set_FPSCR(uint32_t fpscr) -{ -#if (__FPU_PRESENT == 1U) && (__FPU_USED == 1U) - register uint32_t __regfpscr __ASM("fpscr"); - __regfpscr = (fpscr); -#endif -} - -#endif /* (__CORTEX_M == 0x04U) || (__CORTEX_M == 0x07U) */ - - - -/*@} end of CMSIS_Core_RegAccFunctions */ - - -/* ########################## Core Instruction Access ######################### */ -/** \defgroup CMSIS_Core_InstructionInterface CMSIS Core Instruction Interface - Access to dedicated instructions - @{ -*/ - -/** - \brief No Operation - \details No Operation does nothing. This instruction can be used for code alignment purposes. - */ -#define __NOP __nop - - -/** - \brief Wait For Interrupt - \details Wait For Interrupt is a hint instruction that suspends execution until one of a number of events occurs. - */ -#define __WFI __wfi - - -/** - \brief Wait For Event - \details Wait For Event is a hint instruction that permits the processor to enter - a low-power state until one of a number of events occurs. - */ -#define __WFE __wfe - - -/** - \brief Send Event - \details Send Event is a hint instruction. It causes an event to be signaled to the CPU. - */ -#define __SEV __sev - - -/** - \brief Instruction Synchronization Barrier - \details Instruction Synchronization Barrier flushes the pipeline in the processor, - so that all instructions following the ISB are fetched from cache or memory, - after the instruction has been completed. - */ -#define __ISB() do {\ - __schedule_barrier();\ - __isb(0xF);\ - __schedule_barrier();\ - } while (0U) - -/** - \brief Data Synchronization Barrier - \details Acts as a special kind of Data Memory Barrier. - It completes when all explicit memory accesses before this instruction complete. - */ -#define __DSB() do {\ - __schedule_barrier();\ - __dsb(0xF);\ - __schedule_barrier();\ - } while (0U) - -/** - \brief Data Memory Barrier - \details Ensures the apparent order of the explicit memory operations before - and after the instruction, without ensuring their completion. - */ -#define __DMB() do {\ - __schedule_barrier();\ - __dmb(0xF);\ - __schedule_barrier();\ - } while (0U) - -/** - \brief Reverse byte order (32 bit) - \details Reverses the byte order in integer value. - \param [in] value Value to reverse - \return Reversed value - */ -#define __REV __rev - - -/** - \brief Reverse byte order (16 bit) - \details Reverses the byte order in two unsigned short values. - \param [in] value Value to reverse - \return Reversed value - */ -#ifndef __NO_EMBEDDED_ASM -__attribute__((section(".rev16_text"))) __STATIC_INLINE __ASM uint32_t __REV16(uint32_t value) -{ - rev16 r0, r0 - bx lr -} -#endif - -/** - \brief Reverse byte order in signed short value - \details Reverses the byte order in a signed short value with sign extension to integer. - \param [in] value Value to reverse - \return Reversed value - */ -#ifndef __NO_EMBEDDED_ASM -__attribute__((section(".revsh_text"))) __STATIC_INLINE __ASM int32_t __REVSH(int32_t value) -{ - revsh r0, r0 - bx lr -} -#endif - - -/** - \brief Rotate Right in unsigned value (32 bit) - \details Rotate Right (immediate) provides the value of the contents of a register rotated by a variable number of bits. - \param [in] value Value to rotate - \param [in] value Number of Bits to rotate - \return Rotated value - */ -#define __ROR __ror - - -/** - \brief Breakpoint - \details Causes the processor to enter Debug state. - Debug tools can use this to investigate system state when the instruction at a particular address is reached. - \param [in] value is ignored by the processor. - If required, a debugger can use it to store additional information about the breakpoint. - */ -#define __BKPT(value) __breakpoint(value) - - -/** - \brief Reverse bit order of value - \details Reverses the bit order of the given value. - \param [in] value Value to reverse - \return Reversed value - */ -#if (__CORTEX_M >= 0x03U) || (__CORTEX_SC >= 300U) - #define __RBIT __rbit -#else -__attribute__((always_inline)) __STATIC_INLINE uint32_t __RBIT(uint32_t value) -{ - uint32_t result; - int32_t s = 4 /*sizeof(v)*/ * 8 - 1; /* extra shift needed at end */ - - result = value; /* r will be reversed bits of v; first get LSB of v */ - for (value >>= 1U; value; value >>= 1U) - { - result <<= 1U; - result |= value & 1U; - s--; - } - result <<= s; /* shift when v's highest bits are zero */ - return(result); -} -#endif - - -/** - \brief Count leading zeros - \details Counts the number of leading zeros of a data value. - \param [in] value Value to count the leading zeros - \return number of leading zeros in value - */ -#define __CLZ __clz - - -#if (__CORTEX_M >= 0x03U) || (__CORTEX_SC >= 300U) - -/** - \brief LDR Exclusive (8 bit) - \details Executes a exclusive LDR instruction for 8 bit value. - \param [in] ptr Pointer to data - \return value of type uint8_t at (*ptr) - */ -#if defined(__ARMCC_VERSION) && (__ARMCC_VERSION < 5060020) - #define __LDREXB(ptr) ((uint8_t ) __ldrex(ptr)) -#else - #define __LDREXB(ptr) _Pragma("push") _Pragma("diag_suppress 3731") ((uint8_t ) __ldrex(ptr)) _Pragma("pop") -#endif - - -/** - \brief LDR Exclusive (16 bit) - \details Executes a exclusive LDR instruction for 16 bit values. - \param [in] ptr Pointer to data - \return value of type uint16_t at (*ptr) - */ -#if defined(__ARMCC_VERSION) && (__ARMCC_VERSION < 5060020) - #define __LDREXH(ptr) ((uint16_t) __ldrex(ptr)) -#else - #define __LDREXH(ptr) _Pragma("push") _Pragma("diag_suppress 3731") ((uint16_t) __ldrex(ptr)) _Pragma("pop") -#endif - - -/** - \brief LDR Exclusive (32 bit) - \details Executes a exclusive LDR instruction for 32 bit values. - \param [in] ptr Pointer to data - \return value of type uint32_t at (*ptr) - */ -#if defined(__ARMCC_VERSION) && (__ARMCC_VERSION < 5060020) - #define __LDREXW(ptr) ((uint32_t ) __ldrex(ptr)) -#else - #define __LDREXW(ptr) _Pragma("push") _Pragma("diag_suppress 3731") ((uint32_t ) __ldrex(ptr)) _Pragma("pop") -#endif - - -/** - \brief STR Exclusive (8 bit) - \details Executes a exclusive STR instruction for 8 bit values. - \param [in] value Value to store - \param [in] ptr Pointer to location - \return 0 Function succeeded - \return 1 Function failed - */ -#if defined(__ARMCC_VERSION) && (__ARMCC_VERSION < 5060020) - #define __STREXB(value, ptr) __strex(value, ptr) -#else - #define __STREXB(value, ptr) _Pragma("push") _Pragma("diag_suppress 3731") __strex(value, ptr) _Pragma("pop") -#endif - - -/** - \brief STR Exclusive (16 bit) - \details Executes a exclusive STR instruction for 16 bit values. - \param [in] value Value to store - \param [in] ptr Pointer to location - \return 0 Function succeeded - \return 1 Function failed - */ -#if defined(__ARMCC_VERSION) && (__ARMCC_VERSION < 5060020) - #define __STREXH(value, ptr) __strex(value, ptr) -#else - #define __STREXH(value, ptr) _Pragma("push") _Pragma("diag_suppress 3731") __strex(value, ptr) _Pragma("pop") -#endif - - -/** - \brief STR Exclusive (32 bit) - \details Executes a exclusive STR instruction for 32 bit values. - \param [in] value Value to store - \param [in] ptr Pointer to location - \return 0 Function succeeded - \return 1 Function failed - */ -#if defined(__ARMCC_VERSION) && (__ARMCC_VERSION < 5060020) - #define __STREXW(value, ptr) __strex(value, ptr) -#else - #define __STREXW(value, ptr) _Pragma("push") _Pragma("diag_suppress 3731") __strex(value, ptr) _Pragma("pop") -#endif - - -/** - \brief Remove the exclusive lock - \details Removes the exclusive lock which is created by LDREX. - */ -#define __CLREX __clrex - - -/** - \brief Signed Saturate - \details Saturates a signed value. - \param [in] value Value to be saturated - \param [in] sat Bit position to saturate to (1..32) - \return Saturated value - */ -#define __SSAT __ssat - - -/** - \brief Unsigned Saturate - \details Saturates an unsigned value. - \param [in] value Value to be saturated - \param [in] sat Bit position to saturate to (0..31) - \return Saturated value - */ -#define __USAT __usat - - -/** - \brief Rotate Right with Extend (32 bit) - \details Moves each bit of a bitstring right by one bit. - The carry input is shifted in at the left end of the bitstring. - \param [in] value Value to rotate - \return Rotated value - */ -#ifndef __NO_EMBEDDED_ASM -__attribute__((section(".rrx_text"))) __STATIC_INLINE __ASM uint32_t __RRX(uint32_t value) -{ - rrx r0, r0 - bx lr -} -#endif - - -/** - \brief LDRT Unprivileged (8 bit) - \details Executes a Unprivileged LDRT instruction for 8 bit value. - \param [in] ptr Pointer to data - \return value of type uint8_t at (*ptr) - */ -#define __LDRBT(ptr) ((uint8_t ) __ldrt(ptr)) - - -/** - \brief LDRT Unprivileged (16 bit) - \details Executes a Unprivileged LDRT instruction for 16 bit values. - \param [in] ptr Pointer to data - \return value of type uint16_t at (*ptr) - */ -#define __LDRHT(ptr) ((uint16_t) __ldrt(ptr)) - - -/** - \brief LDRT Unprivileged (32 bit) - \details Executes a Unprivileged LDRT instruction for 32 bit values. - \param [in] ptr Pointer to data - \return value of type uint32_t at (*ptr) - */ -#define __LDRT(ptr) ((uint32_t ) __ldrt(ptr)) - - -/** - \brief STRT Unprivileged (8 bit) - \details Executes a Unprivileged STRT instruction for 8 bit values. - \param [in] value Value to store - \param [in] ptr Pointer to location - */ -#define __STRBT(value, ptr) __strt(value, ptr) - - -/** - \brief STRT Unprivileged (16 bit) - \details Executes a Unprivileged STRT instruction for 16 bit values. - \param [in] value Value to store - \param [in] ptr Pointer to location - */ -#define __STRHT(value, ptr) __strt(value, ptr) - - -/** - \brief STRT Unprivileged (32 bit) - \details Executes a Unprivileged STRT instruction for 32 bit values. - \param [in] value Value to store - \param [in] ptr Pointer to location - */ -#define __STRT(value, ptr) __strt(value, ptr) - -#endif /* (__CORTEX_M >= 0x03U) || (__CORTEX_SC >= 300U) */ - -/*@}*/ /* end of group CMSIS_Core_InstructionInterface */ - - -/* ################### Compiler specific Intrinsics ########################### */ -/** \defgroup CMSIS_SIMD_intrinsics CMSIS SIMD Intrinsics - Access to dedicated SIMD instructions - @{ -*/ - -#if (__CORTEX_M >= 0x04U) /* only for Cortex-M4 and above */ - -#define __SADD8 __sadd8 -#define __QADD8 __qadd8 -#define __SHADD8 __shadd8 -#define __UADD8 __uadd8 -#define __UQADD8 __uqadd8 -#define __UHADD8 __uhadd8 -#define __SSUB8 __ssub8 -#define __QSUB8 __qsub8 -#define __SHSUB8 __shsub8 -#define __USUB8 __usub8 -#define __UQSUB8 __uqsub8 -#define __UHSUB8 __uhsub8 -#define __SADD16 __sadd16 -#define __QADD16 __qadd16 -#define __SHADD16 __shadd16 -#define __UADD16 __uadd16 -#define __UQADD16 __uqadd16 -#define __UHADD16 __uhadd16 -#define __SSUB16 __ssub16 -#define __QSUB16 __qsub16 -#define __SHSUB16 __shsub16 -#define __USUB16 __usub16 -#define __UQSUB16 __uqsub16 -#define __UHSUB16 __uhsub16 -#define __SASX __sasx -#define __QASX __qasx -#define __SHASX __shasx -#define __UASX __uasx -#define __UQASX __uqasx -#define __UHASX __uhasx -#define __SSAX __ssax -#define __QSAX __qsax -#define __SHSAX __shsax -#define __USAX __usax -#define __UQSAX __uqsax -#define __UHSAX __uhsax -#define __USAD8 __usad8 -#define __USADA8 __usada8 -#define __SSAT16 __ssat16 -#define __USAT16 __usat16 -#define __UXTB16 __uxtb16 -#define __UXTAB16 __uxtab16 -#define __SXTB16 __sxtb16 -#define __SXTAB16 __sxtab16 -#define __SMUAD __smuad -#define __SMUADX __smuadx -#define __SMLAD __smlad -#define __SMLADX __smladx -#define __SMLALD __smlald -#define __SMLALDX __smlaldx -#define __SMUSD __smusd -#define __SMUSDX __smusdx -#define __SMLSD __smlsd -#define __SMLSDX __smlsdx -#define __SMLSLD __smlsld -#define __SMLSLDX __smlsldx -#define __SEL __sel -#define __QADD __qadd -#define __QSUB __qsub - -#define __PKHBT(ARG1,ARG2,ARG3) ( ((((uint32_t)(ARG1)) ) & 0x0000FFFFUL) | \ - ((((uint32_t)(ARG2)) << (ARG3)) & 0xFFFF0000UL) ) - -#define __PKHTB(ARG1,ARG2,ARG3) ( ((((uint32_t)(ARG1)) ) & 0xFFFF0000UL) | \ - ((((uint32_t)(ARG2)) >> (ARG3)) & 0x0000FFFFUL) ) - -#define __SMMLA(ARG1,ARG2,ARG3) ( (int32_t)((((int64_t)(ARG1) * (ARG2)) + \ - ((int64_t)(ARG3) << 32U) ) >> 32U)) - -#endif /* (__CORTEX_M >= 0x04) */ -/*@} end of group CMSIS_SIMD_intrinsics */ - - -#endif /* __CMSIS_ARMCC_H */ diff --git a/bsp/essemi/es32f0334/libraries/CMSIS/Include/cmsis_armcc_V6.h b/bsp/essemi/es32f0334/libraries/CMSIS/Include/cmsis_armcc_V6.h deleted file mode 100644 index cd13240ce3..0000000000 --- a/bsp/essemi/es32f0334/libraries/CMSIS/Include/cmsis_armcc_V6.h +++ /dev/null @@ -1,1800 +0,0 @@ -/**************************************************************************//** - * @file cmsis_armcc_V6.h - * @brief CMSIS Cortex-M Core Function/Instruction Header File - * @version V4.30 - * @date 20. October 2015 - ******************************************************************************/ -/* Copyright (c) 2009 - 2015 ARM LIMITED - - All rights reserved. - Redistribution and use in source and binary forms, with or without - modification, are permitted provided that the following conditions are met: - - Redistributions of source code must retain the above copyright - notice, this list of conditions and the following disclaimer. - - Redistributions in binary form must reproduce the above copyright - notice, this list of conditions and the following disclaimer in the - documentation and/or other materials provided with the distribution. - - Neither the name of ARM nor the names of its contributors may be used - to endorse or promote products derived from this software without - specific prior written permission. - * - THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" - AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE - ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE - LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR - CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF - SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS - INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN - CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) - ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE - POSSIBILITY OF SUCH DAMAGE. - ---------------------------------------------------------------------------*/ - - -#ifndef __CMSIS_ARMCC_V6_H -#define __CMSIS_ARMCC_V6_H - - -/* ########################### Core Function Access ########################### */ -/** \ingroup CMSIS_Core_FunctionInterface - \defgroup CMSIS_Core_RegAccFunctions CMSIS Core Register Access Functions - @{ - */ - -/** - \brief Enable IRQ Interrupts - \details Enables IRQ interrupts by clearing the I-bit in the CPSR. - Can only be executed in Privileged modes. - */ -__attribute__((always_inline)) __STATIC_INLINE void __enable_irq(void) -{ - __ASM volatile ("cpsie i" : : : "memory"); -} - - -/** - \brief Disable IRQ Interrupts - \details Disables IRQ interrupts by setting the I-bit in the CPSR. - Can only be executed in Privileged modes. - */ -__attribute__((always_inline)) __STATIC_INLINE void __disable_irq(void) -{ - __ASM volatile ("cpsid i" : : : "memory"); -} - - -/** - \brief Get Control Register - \details Returns the content of the Control Register. - \return Control Register value - */ -__attribute__((always_inline)) __STATIC_INLINE uint32_t __get_CONTROL(void) -{ - uint32_t result; - - __ASM volatile ("MRS %0, control" : "=r" (result) ); - return(result); -} - - -#if (__ARM_FEATURE_CMSE == 3U) -/** - \brief Get Control Register (non-secure) - \details Returns the content of the non-secure Control Register when in secure mode. - \return non-secure Control Register value - */ -__attribute__((always_inline)) __STATIC_INLINE uint32_t __TZ_get_CONTROL_NS(void) -{ - uint32_t result; - - __ASM volatile ("MRS %0, control_ns" : "=r" (result) ); - return(result); -} -#endif - - -/** - \brief Set Control Register - \details Writes the given value to the Control Register. - \param [in] control Control Register value to set - */ -__attribute__((always_inline)) __STATIC_INLINE void __set_CONTROL(uint32_t control) -{ - __ASM volatile ("MSR control, %0" : : "r" (control) : "memory"); -} - - -#if (__ARM_FEATURE_CMSE == 3U) -/** - \brief Set Control Register (non-secure) - \details Writes the given value to the non-secure Control Register when in secure state. - \param [in] control Control Register value to set - */ -__attribute__((always_inline)) __STATIC_INLINE void __TZ_set_CONTROL_NS(uint32_t control) -{ - __ASM volatile ("MSR control_ns, %0" : : "r" (control) : "memory"); -} -#endif - - -/** - \brief Get IPSR Register - \details Returns the content of the IPSR Register. - \return IPSR Register value - */ -__attribute__((always_inline)) __STATIC_INLINE uint32_t __get_IPSR(void) -{ - uint32_t result; - - __ASM volatile ("MRS %0, ipsr" : "=r" (result) ); - return(result); -} - - -#if (__ARM_FEATURE_CMSE == 3U) -/** - \brief Get IPSR Register (non-secure) - \details Returns the content of the non-secure IPSR Register when in secure state. - \return IPSR Register value - */ -__attribute__((always_inline)) __STATIC_INLINE uint32_t __TZ_get_IPSR_NS(void) -{ - uint32_t result; - - __ASM volatile ("MRS %0, ipsr_ns" : "=r" (result) ); - return(result); -} -#endif - - -/** - \brief Get APSR Register - \details Returns the content of the APSR Register. - \return APSR Register value - */ -__attribute__((always_inline)) __STATIC_INLINE uint32_t __get_APSR(void) -{ - uint32_t result; - - __ASM volatile ("MRS %0, apsr" : "=r" (result) ); - return(result); -} - - -#if (__ARM_FEATURE_CMSE == 3U) -/** - \brief Get APSR Register (non-secure) - \details Returns the content of the non-secure APSR Register when in secure state. - \return APSR Register value - */ -__attribute__((always_inline)) __STATIC_INLINE uint32_t __TZ_get_APSR_NS(void) -{ - uint32_t result; - - __ASM volatile ("MRS %0, apsr_ns" : "=r" (result) ); - return(result); -} -#endif - - -/** - \brief Get xPSR Register - \details Returns the content of the xPSR Register. - \return xPSR Register value - */ -__attribute__((always_inline)) __STATIC_INLINE uint32_t __get_xPSR(void) -{ - uint32_t result; - - __ASM volatile ("MRS %0, xpsr" : "=r" (result) ); - return(result); -} - - -#if (__ARM_FEATURE_CMSE == 3U) -/** - \brief Get xPSR Register (non-secure) - \details Returns the content of the non-secure xPSR Register when in secure state. - \return xPSR Register value - */ -__attribute__((always_inline)) __STATIC_INLINE uint32_t __TZ_get_xPSR_NS(void) -{ - uint32_t result; - - __ASM volatile ("MRS %0, xpsr_ns" : "=r" (result) ); - return(result); -} -#endif - - -/** - \brief Get Process Stack Pointer - \details Returns the current value of the Process Stack Pointer (PSP). - \return PSP Register value - */ -__attribute__((always_inline)) __STATIC_INLINE uint32_t __get_PSP(void) -{ - register uint32_t result; - - __ASM volatile ("MRS %0, psp" : "=r" (result) ); - return(result); -} - - -#if (__ARM_FEATURE_CMSE == 3U) -/** - \brief Get Process Stack Pointer (non-secure) - \details Returns the current value of the non-secure Process Stack Pointer (PSP) when in secure state. - \return PSP Register value - */ -__attribute__((always_inline)) __STATIC_INLINE uint32_t __TZ_get_PSP_NS(void) -{ - register uint32_t result; - - __ASM volatile ("MRS %0, psp_ns" : "=r" (result) ); - return(result); -} -#endif - - -/** - \brief Set Process Stack Pointer - \details Assigns the given value to the Process Stack Pointer (PSP). - \param [in] topOfProcStack Process Stack Pointer value to set - */ -__attribute__((always_inline)) __STATIC_INLINE void __set_PSP(uint32_t topOfProcStack) -{ - __ASM volatile ("MSR psp, %0" : : "r" (topOfProcStack) : "sp"); -} - - -#if (__ARM_FEATURE_CMSE == 3U) -/** - \brief Set Process Stack Pointer (non-secure) - \details Assigns the given value to the non-secure Process Stack Pointer (PSP) when in secure state. - \param [in] topOfProcStack Process Stack Pointer value to set - */ -__attribute__((always_inline)) __STATIC_INLINE void __TZ_set_PSP_NS(uint32_t topOfProcStack) -{ - __ASM volatile ("MSR psp_ns, %0" : : "r" (topOfProcStack) : "sp"); -} -#endif - - -/** - \brief Get Main Stack Pointer - \details Returns the current value of the Main Stack Pointer (MSP). - \return MSP Register value - */ -__attribute__((always_inline)) __STATIC_INLINE uint32_t __get_MSP(void) -{ - register uint32_t result; - - __ASM volatile ("MRS %0, msp" : "=r" (result) ); - return(result); -} - - -#if (__ARM_FEATURE_CMSE == 3U) -/** - \brief Get Main Stack Pointer (non-secure) - \details Returns the current value of the non-secure Main Stack Pointer (MSP) when in secure state. - \return MSP Register value - */ -__attribute__((always_inline)) __STATIC_INLINE uint32_t __TZ_get_MSP_NS(void) -{ - register uint32_t result; - - __ASM volatile ("MRS %0, msp_ns" : "=r" (result) ); - return(result); -} -#endif - - -/** - \brief Set Main Stack Pointer - \details Assigns the given value to the Main Stack Pointer (MSP). - \param [in] topOfMainStack Main Stack Pointer value to set - */ -__attribute__((always_inline)) __STATIC_INLINE void __set_MSP(uint32_t topOfMainStack) -{ - __ASM volatile ("MSR msp, %0" : : "r" (topOfMainStack) : "sp"); -} - - -#if (__ARM_FEATURE_CMSE == 3U) -/** - \brief Set Main Stack Pointer (non-secure) - \details Assigns the given value to the non-secure Main Stack Pointer (MSP) when in secure state. - \param [in] topOfMainStack Main Stack Pointer value to set - */ -__attribute__((always_inline)) __STATIC_INLINE void __TZ_set_MSP_NS(uint32_t topOfMainStack) -{ - __ASM volatile ("MSR msp_ns, %0" : : "r" (topOfMainStack) : "sp"); -} -#endif - - -/** - \brief Get Priority Mask - \details Returns the current state of the priority mask bit from the Priority Mask Register. - \return Priority Mask value - */ -__attribute__((always_inline)) __STATIC_INLINE uint32_t __get_PRIMASK(void) -{ - uint32_t result; - - __ASM volatile ("MRS %0, primask" : "=r" (result) ); - return(result); -} - - -#if (__ARM_FEATURE_CMSE == 3U) -/** - \brief Get Priority Mask (non-secure) - \details Returns the current state of the non-secure priority mask bit from the Priority Mask Register when in secure state. - \return Priority Mask value - */ -__attribute__((always_inline)) __STATIC_INLINE uint32_t __TZ_get_PRIMASK_NS(void) -{ - uint32_t result; - - __ASM volatile ("MRS %0, primask_ns" : "=r" (result) ); - return(result); -} -#endif - - -/** - \brief Set Priority Mask - \details Assigns the given value to the Priority Mask Register. - \param [in] priMask Priority Mask - */ -__attribute__((always_inline)) __STATIC_INLINE void __set_PRIMASK(uint32_t priMask) -{ - __ASM volatile ("MSR primask, %0" : : "r" (priMask) : "memory"); -} - - -#if (__ARM_FEATURE_CMSE == 3U) -/** - \brief Set Priority Mask (non-secure) - \details Assigns the given value to the non-secure Priority Mask Register when in secure state. - \param [in] priMask Priority Mask - */ -__attribute__((always_inline)) __STATIC_INLINE void __TZ_set_PRIMASK_NS(uint32_t priMask) -{ - __ASM volatile ("MSR primask_ns, %0" : : "r" (priMask) : "memory"); -} -#endif - - -#if ((__ARM_ARCH_7M__ == 1U) || (__ARM_ARCH_7EM__ == 1U) || (__ARM_ARCH_8M__ == 1U)) /* ToDo: ARMCC_V6: check if this is ok for cortex >=3 */ - -/** - \brief Enable FIQ - \details Enables FIQ interrupts by clearing the F-bit in the CPSR. - Can only be executed in Privileged modes. - */ -__attribute__((always_inline)) __STATIC_INLINE void __enable_fault_irq(void) -{ - __ASM volatile ("cpsie f" : : : "memory"); -} - - -/** - \brief Disable FIQ - \details Disables FIQ interrupts by setting the F-bit in the CPSR. - Can only be executed in Privileged modes. - */ -__attribute__((always_inline)) __STATIC_INLINE void __disable_fault_irq(void) -{ - __ASM volatile ("cpsid f" : : : "memory"); -} - - -/** - \brief Get Base Priority - \details Returns the current value of the Base Priority register. - \return Base Priority register value - */ -__attribute__((always_inline)) __STATIC_INLINE uint32_t __get_BASEPRI(void) -{ - uint32_t result; - - __ASM volatile ("MRS %0, basepri" : "=r" (result) ); - return(result); -} - - -#if (__ARM_FEATURE_CMSE == 3U) -/** - \brief Get Base Priority (non-secure) - \details Returns the current value of the non-secure Base Priority register when in secure state. - \return Base Priority register value - */ -__attribute__((always_inline)) __STATIC_INLINE uint32_t __TZ_get_BASEPRI_NS(void) -{ - uint32_t result; - - __ASM volatile ("MRS %0, basepri_ns" : "=r" (result) ); - return(result); -} -#endif - - -/** - \brief Set Base Priority - \details Assigns the given value to the Base Priority register. - \param [in] basePri Base Priority value to set - */ -__attribute__((always_inline)) __STATIC_INLINE void __set_BASEPRI(uint32_t value) -{ - __ASM volatile ("MSR basepri, %0" : : "r" (value) : "memory"); -} - - -#if (__ARM_FEATURE_CMSE == 3U) -/** - \brief Set Base Priority (non-secure) - \details Assigns the given value to the non-secure Base Priority register when in secure state. - \param [in] basePri Base Priority value to set - */ -__attribute__((always_inline)) __STATIC_INLINE void __TZ_set_BASEPRI_NS(uint32_t value) -{ - __ASM volatile ("MSR basepri_ns, %0" : : "r" (value) : "memory"); -} -#endif - - -/** - \brief Set Base Priority with condition - \details Assigns the given value to the Base Priority register only if BASEPRI masking is disabled, - or the new value increases the BASEPRI priority level. - \param [in] basePri Base Priority value to set - */ -__attribute__((always_inline)) __STATIC_INLINE void __set_BASEPRI_MAX(uint32_t value) -{ - __ASM volatile ("MSR basepri_max, %0" : : "r" (value) : "memory"); -} - - -#if (__ARM_FEATURE_CMSE == 3U) -/** - \brief Set Base Priority with condition (non_secure) - \details Assigns the given value to the non-secure Base Priority register when in secure state only if BASEPRI masking is disabled, - or the new value increases the BASEPRI priority level. - \param [in] basePri Base Priority value to set - */ -__attribute__((always_inline)) __STATIC_INLINE void __TZ_set_BASEPRI_MAX_NS(uint32_t value) -{ - __ASM volatile ("MSR basepri_max_ns, %0" : : "r" (value) : "memory"); -} -#endif - - -/** - \brief Get Fault Mask - \details Returns the current value of the Fault Mask register. - \return Fault Mask register value - */ -__attribute__((always_inline)) __STATIC_INLINE uint32_t __get_FAULTMASK(void) -{ - uint32_t result; - - __ASM volatile ("MRS %0, faultmask" : "=r" (result) ); - return(result); -} - - -#if (__ARM_FEATURE_CMSE == 3U) -/** - \brief Get Fault Mask (non-secure) - \details Returns the current value of the non-secure Fault Mask register when in secure state. - \return Fault Mask register value - */ -__attribute__((always_inline)) __STATIC_INLINE uint32_t __TZ_get_FAULTMASK_NS(void) -{ - uint32_t result; - - __ASM volatile ("MRS %0, faultmask_ns" : "=r" (result) ); - return(result); -} -#endif - - -/** - \brief Set Fault Mask - \details Assigns the given value to the Fault Mask register. - \param [in] faultMask Fault Mask value to set - */ -__attribute__((always_inline)) __STATIC_INLINE void __set_FAULTMASK(uint32_t faultMask) -{ - __ASM volatile ("MSR faultmask, %0" : : "r" (faultMask) : "memory"); -} - - -#if (__ARM_FEATURE_CMSE == 3U) -/** - \brief Set Fault Mask (non-secure) - \details Assigns the given value to the non-secure Fault Mask register when in secure state. - \param [in] faultMask Fault Mask value to set - */ -__attribute__((always_inline)) __STATIC_INLINE void __TZ_set_FAULTMASK_NS(uint32_t faultMask) -{ - __ASM volatile ("MSR faultmask_ns, %0" : : "r" (faultMask) : "memory"); -} -#endif - - -#endif /* ((__ARM_ARCH_7M__ == 1U) || (__ARM_ARCH_8M__ == 1U)) */ - - -#if (__ARM_ARCH_8M__ == 1U) - -/** - \brief Get Process Stack Pointer Limit - \details Returns the current value of the Process Stack Pointer Limit (PSPLIM). - \return PSPLIM Register value - */ -__attribute__((always_inline)) __STATIC_INLINE uint32_t __get_PSPLIM(void) -{ - register uint32_t result; - - __ASM volatile ("MRS %0, psplim" : "=r" (result) ); - return(result); -} - - -#if (__ARM_FEATURE_CMSE == 3U) && (__ARM_ARCH_PROFILE == 'M') /* ToDo: ARMCC_V6: check predefined macro for mainline */ -/** - \brief Get Process Stack Pointer Limit (non-secure) - \details Returns the current value of the non-secure Process Stack Pointer Limit (PSPLIM) when in secure state. - \return PSPLIM Register value - */ -__attribute__((always_inline)) __STATIC_INLINE uint32_t __TZ_get_PSPLIM_NS(void) -{ - register uint32_t result; - - __ASM volatile ("MRS %0, psplim_ns" : "=r" (result) ); - return(result); -} -#endif - - -/** - \brief Set Process Stack Pointer Limit - \details Assigns the given value to the Process Stack Pointer Limit (PSPLIM). - \param [in] ProcStackPtrLimit Process Stack Pointer Limit value to set - */ -__attribute__((always_inline)) __STATIC_INLINE void __set_PSPLIM(uint32_t ProcStackPtrLimit) -{ - __ASM volatile ("MSR psplim, %0" : : "r" (ProcStackPtrLimit)); -} - - -#if (__ARM_FEATURE_CMSE == 3U) && (__ARM_ARCH_PROFILE == 'M') /* ToDo: ARMCC_V6: check predefined macro for mainline */ -/** - \brief Set Process Stack Pointer (non-secure) - \details Assigns the given value to the non-secure Process Stack Pointer Limit (PSPLIM) when in secure state. - \param [in] ProcStackPtrLimit Process Stack Pointer Limit value to set - */ -__attribute__((always_inline)) __STATIC_INLINE void __TZ_set_PSPLIM_NS(uint32_t ProcStackPtrLimit) -{ - __ASM volatile ("MSR psplim_ns, %0\n" : : "r" (ProcStackPtrLimit)); -} -#endif - - -/** - \brief Get Main Stack Pointer Limit - \details Returns the current value of the Main Stack Pointer Limit (MSPLIM). - \return MSPLIM Register value - */ -__attribute__((always_inline)) __STATIC_INLINE uint32_t __get_MSPLIM(void) -{ - register uint32_t result; - - __ASM volatile ("MRS %0, msplim" : "=r" (result) ); - - return(result); -} - - -#if (__ARM_FEATURE_CMSE == 3U) && (__ARM_ARCH_PROFILE == 'M') /* ToDo: ARMCC_V6: check predefined macro for mainline */ -/** - \brief Get Main Stack Pointer Limit (non-secure) - \details Returns the current value of the non-secure Main Stack Pointer Limit(MSPLIM) when in secure state. - \return MSPLIM Register value - */ -__attribute__((always_inline)) __STATIC_INLINE uint32_t __TZ_get_MSPLIM_NS(void) -{ - register uint32_t result; - - __ASM volatile ("MRS %0, msplim_ns" : "=r" (result) ); - return(result); -} -#endif - - -/** - \brief Set Main Stack Pointer Limit - \details Assigns the given value to the Main Stack Pointer Limit (MSPLIM). - \param [in] MainStackPtrLimit Main Stack Pointer Limit value to set - */ -__attribute__((always_inline)) __STATIC_INLINE void __set_MSPLIM(uint32_t MainStackPtrLimit) -{ - __ASM volatile ("MSR msplim, %0" : : "r" (MainStackPtrLimit)); -} - - -#if (__ARM_FEATURE_CMSE == 3U) && (__ARM_ARCH_PROFILE == 'M') /* ToDo: ARMCC_V6: check predefined macro for mainline */ -/** - \brief Set Main Stack Pointer Limit (non-secure) - \details Assigns the given value to the non-secure Main Stack Pointer Limit (MSPLIM) when in secure state. - \param [in] MainStackPtrLimit Main Stack Pointer value to set - */ -__attribute__((always_inline)) __STATIC_INLINE void __TZ_set_MSPLIM_NS(uint32_t MainStackPtrLimit) -{ - __ASM volatile ("MSR msplim_ns, %0" : : "r" (MainStackPtrLimit)); -} -#endif - -#endif /* (__ARM_ARCH_8M__ == 1U) */ - - -#if ((__ARM_ARCH_7EM__ == 1U) || (__ARM_ARCH_8M__ == 1U)) /* ToDo: ARMCC_V6: check if this is ok for cortex >=4 */ - -/** - \brief Get FPSCR - \details eturns the current value of the Floating Point Status/Control register. - \return Floating Point Status/Control register value - */ -#define __get_FPSCR __builtin_arm_get_fpscr -#if 0 -__attribute__((always_inline)) __STATIC_INLINE uint32_t __get_FPSCR(void) -{ -#if (__FPU_PRESENT == 1U) && (__FPU_USED == 1U) - uint32_t result; - - __ASM volatile (""); /* Empty asm statement works as a scheduling barrier */ - __ASM volatile ("VMRS %0, fpscr" : "=r" (result) ); - __ASM volatile (""); - return(result); -#else - return(0); -#endif -} -#endif - -#if (__ARM_FEATURE_CMSE == 3U) -/** - \brief Get FPSCR (non-secure) - \details Returns the current value of the non-secure Floating Point Status/Control register when in secure state. - \return Floating Point Status/Control register value - */ -__attribute__((always_inline)) __STATIC_INLINE uint32_t __TZ_get_FPSCR_NS(void) -{ -#if (__FPU_PRESENT == 1U) && (__FPU_USED == 1U) - uint32_t result; - - __ASM volatile (""); /* Empty asm statement works as a scheduling barrier */ - __ASM volatile ("VMRS %0, fpscr_ns" : "=r" (result) ); - __ASM volatile (""); - return(result); -#else - return(0); -#endif -} -#endif - - -/** - \brief Set FPSCR - \details Assigns the given value to the Floating Point Status/Control register. - \param [in] fpscr Floating Point Status/Control value to set - */ -#define __set_FPSCR __builtin_arm_set_fpscr -#if 0 -__attribute__((always_inline)) __STATIC_INLINE void __set_FPSCR(uint32_t fpscr) -{ -#if (__FPU_PRESENT == 1U) && (__FPU_USED == 1U) - __ASM volatile (""); /* Empty asm statement works as a scheduling barrier */ - __ASM volatile ("VMSR fpscr, %0" : : "r" (fpscr) : "vfpcc"); - __ASM volatile (""); -#endif -} -#endif - -#if (__ARM_FEATURE_CMSE == 3U) -/** - \brief Set FPSCR (non-secure) - \details Assigns the given value to the non-secure Floating Point Status/Control register when in secure state. - \param [in] fpscr Floating Point Status/Control value to set - */ -__attribute__((always_inline)) __STATIC_INLINE void __TZ_set_FPSCR_NS(uint32_t fpscr) -{ -#if (__FPU_PRESENT == 1U) && (__FPU_USED == 1U) - __ASM volatile (""); /* Empty asm statement works as a scheduling barrier */ - __ASM volatile ("VMSR fpscr_ns, %0" : : "r" (fpscr) : "vfpcc"); - __ASM volatile (""); -#endif -} -#endif - -#endif /* ((__ARM_ARCH_7EM__ == 1U) || (__ARM_ARCH_8M__ == 1U)) */ - - - -/*@} end of CMSIS_Core_RegAccFunctions */ - - -/* ########################## Core Instruction Access ######################### */ -/** \defgroup CMSIS_Core_InstructionInterface CMSIS Core Instruction Interface - Access to dedicated instructions - @{ -*/ - -/* Define macros for porting to both thumb1 and thumb2. - * For thumb1, use low register (r0-r7), specified by constraint "l" - * Otherwise, use general registers, specified by constraint "r" */ -#if defined (__thumb__) && !defined (__thumb2__) -#define __CMSIS_GCC_OUT_REG(r) "=l" (r) -#define __CMSIS_GCC_USE_REG(r) "l" (r) -#else -#define __CMSIS_GCC_OUT_REG(r) "=r" (r) -#define __CMSIS_GCC_USE_REG(r) "r" (r) -#endif - -/** - \brief No Operation - \details No Operation does nothing. This instruction can be used for code alignment purposes. - */ -#define __NOP __builtin_arm_nop - -/** - \brief Wait For Interrupt - \details Wait For Interrupt is a hint instruction that suspends execution until one of a number of events occurs. - */ -#define __WFI __builtin_arm_wfi - - -/** - \brief Wait For Event - \details Wait For Event is a hint instruction that permits the processor to enter - a low-power state until one of a number of events occurs. - */ -#define __WFE __builtin_arm_wfe - - -/** - \brief Send Event - \details Send Event is a hint instruction. It causes an event to be signaled to the CPU. - */ -#define __SEV __builtin_arm_sev - - -/** - \brief Instruction Synchronization Barrier - \details Instruction Synchronization Barrier flushes the pipeline in the processor, - so that all instructions following the ISB are fetched from cache or memory, - after the instruction has been completed. - */ -#define __ISB() __builtin_arm_isb(0xF); - -/** - \brief Data Synchronization Barrier - \details Acts as a special kind of Data Memory Barrier. - It completes when all explicit memory accesses before this instruction complete. - */ -#define __DSB() __builtin_arm_dsb(0xF); - - -/** - \brief Data Memory Barrier - \details Ensures the apparent order of the explicit memory operations before - and after the instruction, without ensuring their completion. - */ -#define __DMB() __builtin_arm_dmb(0xF); - - -/** - \brief Reverse byte order (32 bit) - \details Reverses the byte order in integer value. - \param [in] value Value to reverse - \return Reversed value - */ -#define __REV __builtin_bswap32 - - -/** - \brief Reverse byte order (16 bit) - \details Reverses the byte order in two unsigned short values. - \param [in] value Value to reverse - \return Reversed value - */ -#define __REV16 __builtin_bswap16 /* ToDo: ARMCC_V6: check if __builtin_bswap16 could be used */ -#if 0 -__attribute__((always_inline)) __STATIC_INLINE uint32_t __REV16(uint32_t value) -{ - uint32_t result; - - __ASM volatile ("rev16 %0, %1" : __CMSIS_GCC_OUT_REG (result) : __CMSIS_GCC_USE_REG (value) ); - return(result); -} -#endif - - -/** - \brief Reverse byte order in signed short value - \details Reverses the byte order in a signed short value with sign extension to integer. - \param [in] value Value to reverse - \return Reversed value - */ - /* ToDo: ARMCC_V6: check if __builtin_bswap16 could be used */ -__attribute__((always_inline)) __STATIC_INLINE int32_t __REVSH(int32_t value) -{ - int32_t result; - - __ASM volatile ("revsh %0, %1" : __CMSIS_GCC_OUT_REG (result) : __CMSIS_GCC_USE_REG (value) ); - return(result); -} - - -/** - \brief Rotate Right in unsigned value (32 bit) - \details Rotate Right (immediate) provides the value of the contents of a register rotated by a variable number of bits. - \param [in] op1 Value to rotate - \param [in] op2 Number of Bits to rotate - \return Rotated value - */ -__attribute__((always_inline)) __STATIC_INLINE uint32_t __ROR(uint32_t op1, uint32_t op2) -{ - return (op1 >> op2) | (op1 << (32U - op2)); -} - - -/** - \brief Breakpoint - \details Causes the processor to enter Debug state. - Debug tools can use this to investigate system state when the instruction at a particular address is reached. - \param [in] value is ignored by the processor. - If required, a debugger can use it to store additional information about the breakpoint. - */ -#define __BKPT(value) __ASM volatile ("bkpt "#value) - - -/** - \brief Reverse bit order of value - \details Reverses the bit order of the given value. - \param [in] value Value to reverse - \return Reversed value - */ - /* ToDo: ARMCC_V6: check if __builtin_arm_rbit is supported */ -__attribute__((always_inline)) __STATIC_INLINE uint32_t __RBIT(uint32_t value) -{ - uint32_t result; - -#if ((__ARM_ARCH_7M__ == 1U) || (__ARM_ARCH_7EM__ == 1U) || (__ARM_ARCH_8M__ == 1U)) /* ToDo: ARMCC_V6: check if this is ok for cortex >=3 */ - __ASM volatile ("rbit %0, %1" : "=r" (result) : "r" (value) ); -#else - int32_t s = 4 /*sizeof(v)*/ * 8 - 1; /* extra shift needed at end */ - - result = value; /* r will be reversed bits of v; first get LSB of v */ - for (value >>= 1U; value; value >>= 1U) - { - result <<= 1U; - result |= value & 1U; - s--; - } - result <<= s; /* shift when v's highest bits are zero */ -#endif - return(result); -} - - -/** - \brief Count leading zeros - \details Counts the number of leading zeros of a data value. - \param [in] value Value to count the leading zeros - \return number of leading zeros in value - */ -#define __CLZ __builtin_clz - - -#if ((__ARM_ARCH_7M__ == 1U) || (__ARM_ARCH_7EM__ == 1U) || (__ARM_ARCH_8M__ == 1U)) /* ToDo: ARMCC_V6: check if this is ok for cortex >=3 */ - -/** - \brief LDR Exclusive (8 bit) - \details Executes a exclusive LDR instruction for 8 bit value. - \param [in] ptr Pointer to data - \return value of type uint8_t at (*ptr) - */ -#define __LDREXB (uint8_t)__builtin_arm_ldrex - - -/** - \brief LDR Exclusive (16 bit) - \details Executes a exclusive LDR instruction for 16 bit values. - \param [in] ptr Pointer to data - \return value of type uint16_t at (*ptr) - */ -#define __LDREXH (uint16_t)__builtin_arm_ldrex - - -/** - \brief LDR Exclusive (32 bit) - \details Executes a exclusive LDR instruction for 32 bit values. - \param [in] ptr Pointer to data - \return value of type uint32_t at (*ptr) - */ -#define __LDREXW (uint32_t)__builtin_arm_ldrex - - -/** - \brief STR Exclusive (8 bit) - \details Executes a exclusive STR instruction for 8 bit values. - \param [in] value Value to store - \param [in] ptr Pointer to location - \return 0 Function succeeded - \return 1 Function failed - */ -#define __STREXB (uint32_t)__builtin_arm_strex - - -/** - \brief STR Exclusive (16 bit) - \details Executes a exclusive STR instruction for 16 bit values. - \param [in] value Value to store - \param [in] ptr Pointer to location - \return 0 Function succeeded - \return 1 Function failed - */ -#define __STREXH (uint32_t)__builtin_arm_strex - - -/** - \brief STR Exclusive (32 bit) - \details Executes a exclusive STR instruction for 32 bit values. - \param [in] value Value to store - \param [in] ptr Pointer to location - \return 0 Function succeeded - \return 1 Function failed - */ -#define __STREXW (uint32_t)__builtin_arm_strex - - -/** - \brief Remove the exclusive lock - \details Removes the exclusive lock which is created by LDREX. - */ -#define __CLREX __builtin_arm_clrex - - -/** - \brief Signed Saturate - \details Saturates a signed value. - \param [in] value Value to be saturated - \param [in] sat Bit position to saturate to (1..32) - \return Saturated value - */ -/*#define __SSAT __builtin_arm_ssat*/ -#define __SSAT(ARG1,ARG2) \ -({ \ - int32_t __RES, __ARG1 = (ARG1); \ - __ASM ("ssat %0, %1, %2" : "=r" (__RES) : "I" (ARG2), "r" (__ARG1) ); \ - __RES; \ - }) - - -/** - \brief Unsigned Saturate - \details Saturates an unsigned value. - \param [in] value Value to be saturated - \param [in] sat Bit position to saturate to (0..31) - \return Saturated value - */ -#define __USAT __builtin_arm_usat -#if 0 -#define __USAT(ARG1,ARG2) \ -({ \ - uint32_t __RES, __ARG1 = (ARG1); \ - __ASM ("usat %0, %1, %2" : "=r" (__RES) : "I" (ARG2), "r" (__ARG1) ); \ - __RES; \ - }) -#endif - - -/** - \brief Rotate Right with Extend (32 bit) - \details Moves each bit of a bitstring right by one bit. - The carry input is shifted in at the left end of the bitstring. - \param [in] value Value to rotate - \return Rotated value - */ -__attribute__((always_inline)) __STATIC_INLINE uint32_t __RRX(uint32_t value) -{ - uint32_t result; - - __ASM volatile ("rrx %0, %1" : __CMSIS_GCC_OUT_REG (result) : __CMSIS_GCC_USE_REG (value) ); - return(result); -} - - -/** - \brief LDRT Unprivileged (8 bit) - \details Executes a Unprivileged LDRT instruction for 8 bit value. - \param [in] ptr Pointer to data - \return value of type uint8_t at (*ptr) - */ -__attribute__((always_inline)) __STATIC_INLINE uint8_t __LDRBT(volatile uint8_t *ptr) -{ - uint32_t result; - - __ASM volatile ("ldrbt %0, %1" : "=r" (result) : "Q" (*ptr) ); - return ((uint8_t) result); /* Add explicit type cast here */ -} - - -/** - \brief LDRT Unprivileged (16 bit) - \details Executes a Unprivileged LDRT instruction for 16 bit values. - \param [in] ptr Pointer to data - \return value of type uint16_t at (*ptr) - */ -__attribute__((always_inline)) __STATIC_INLINE uint16_t __LDRHT(volatile uint16_t *ptr) -{ - uint32_t result; - - __ASM volatile ("ldrht %0, %1" : "=r" (result) : "Q" (*ptr) ); - return ((uint16_t) result); /* Add explicit type cast here */ -} - - -/** - \brief LDRT Unprivileged (32 bit) - \details Executes a Unprivileged LDRT instruction for 32 bit values. - \param [in] ptr Pointer to data - \return value of type uint32_t at (*ptr) - */ -__attribute__((always_inline)) __STATIC_INLINE uint32_t __LDRT(volatile uint32_t *ptr) -{ - uint32_t result; - - __ASM volatile ("ldrt %0, %1" : "=r" (result) : "Q" (*ptr) ); - return(result); -} - - -/** - \brief STRT Unprivileged (8 bit) - \details Executes a Unprivileged STRT instruction for 8 bit values. - \param [in] value Value to store - \param [in] ptr Pointer to location - */ -__attribute__((always_inline)) __STATIC_INLINE void __STRBT(uint8_t value, volatile uint8_t *ptr) -{ - __ASM volatile ("strbt %1, %0" : "=Q" (*ptr) : "r" ((uint32_t)value) ); -} - - -/** - \brief STRT Unprivileged (16 bit) - \details Executes a Unprivileged STRT instruction for 16 bit values. - \param [in] value Value to store - \param [in] ptr Pointer to location - */ -__attribute__((always_inline)) __STATIC_INLINE void __STRHT(uint16_t value, volatile uint16_t *ptr) -{ - __ASM volatile ("strht %1, %0" : "=Q" (*ptr) : "r" ((uint32_t)value) ); -} - - -/** - \brief STRT Unprivileged (32 bit) - \details Executes a Unprivileged STRT instruction for 32 bit values. - \param [in] value Value to store - \param [in] ptr Pointer to location - */ -__attribute__((always_inline)) __STATIC_INLINE void __STRT(uint32_t value, volatile uint32_t *ptr) -{ - __ASM volatile ("strt %1, %0" : "=Q" (*ptr) : "r" (value) ); -} - -#endif /* ((__ARM_ARCH_7M__ == 1U) || (__ARM_ARCH_7EM__ == 1U) || (__ARM_ARCH_8M__ == 1U)) */ - - -#if (__ARM_ARCH_8M__ == 1U) - -/** - \brief Load-Acquire (8 bit) - \details Executes a LDAB instruction for 8 bit value. - \param [in] ptr Pointer to data - \return value of type uint8_t at (*ptr) - */ -__attribute__((always_inline)) __STATIC_INLINE uint8_t __LDAB(volatile uint8_t *ptr) -{ - uint32_t result; - - __ASM volatile ("ldab %0, %1" : "=r" (result) : "Q" (*ptr) ); - return ((uint8_t) result); -} - - -/** - \brief Load-Acquire (16 bit) - \details Executes a LDAH instruction for 16 bit values. - \param [in] ptr Pointer to data - \return value of type uint16_t at (*ptr) - */ -__attribute__((always_inline)) __STATIC_INLINE uint16_t __LDAH(volatile uint16_t *ptr) -{ - uint32_t result; - - __ASM volatile ("ldah %0, %1" : "=r" (result) : "Q" (*ptr) ); - return ((uint16_t) result); -} - - -/** - \brief Load-Acquire (32 bit) - \details Executes a LDA instruction for 32 bit values. - \param [in] ptr Pointer to data - \return value of type uint32_t at (*ptr) - */ -__attribute__((always_inline)) __STATIC_INLINE uint32_t __LDA(volatile uint32_t *ptr) -{ - uint32_t result; - - __ASM volatile ("lda %0, %1" : "=r" (result) : "Q" (*ptr) ); - return(result); -} - - -/** - \brief Store-Release (8 bit) - \details Executes a STLB instruction for 8 bit values. - \param [in] value Value to store - \param [in] ptr Pointer to location - */ -__attribute__((always_inline)) __STATIC_INLINE void __STLB(uint8_t value, volatile uint8_t *ptr) -{ - __ASM volatile ("stlb %1, %0" : "=Q" (*ptr) : "r" ((uint32_t)value) ); -} - - -/** - \brief Store-Release (16 bit) - \details Executes a STLH instruction for 16 bit values. - \param [in] value Value to store - \param [in] ptr Pointer to location - */ -__attribute__((always_inline)) __STATIC_INLINE void __STLH(uint16_t value, volatile uint16_t *ptr) -{ - __ASM volatile ("stlh %1, %0" : "=Q" (*ptr) : "r" ((uint32_t)value) ); -} - - -/** - \brief Store-Release (32 bit) - \details Executes a STL instruction for 32 bit values. - \param [in] value Value to store - \param [in] ptr Pointer to location - */ -__attribute__((always_inline)) __STATIC_INLINE void __STL(uint32_t value, volatile uint32_t *ptr) -{ - __ASM volatile ("stl %1, %0" : "=Q" (*ptr) : "r" ((uint32_t)value) ); -} - - -/** - \brief Load-Acquire Exclusive (8 bit) - \details Executes a LDAB exclusive instruction for 8 bit value. - \param [in] ptr Pointer to data - \return value of type uint8_t at (*ptr) - */ -#define __LDAEXB (uint8_t)__builtin_arm_ldaex - - -/** - \brief Load-Acquire Exclusive (16 bit) - \details Executes a LDAH exclusive instruction for 16 bit values. - \param [in] ptr Pointer to data - \return value of type uint16_t at (*ptr) - */ -#define __LDAEXH (uint16_t)__builtin_arm_ldaex - - -/** - \brief Load-Acquire Exclusive (32 bit) - \details Executes a LDA exclusive instruction for 32 bit values. - \param [in] ptr Pointer to data - \return value of type uint32_t at (*ptr) - */ -#define __LDAEX (uint32_t)__builtin_arm_ldaex - - -/** - \brief Store-Release Exclusive (8 bit) - \details Executes a STLB exclusive instruction for 8 bit values. - \param [in] value Value to store - \param [in] ptr Pointer to location - \return 0 Function succeeded - \return 1 Function failed - */ -#define __STLEXB (uint32_t)__builtin_arm_stlex - - -/** - \brief Store-Release Exclusive (16 bit) - \details Executes a STLH exclusive instruction for 16 bit values. - \param [in] value Value to store - \param [in] ptr Pointer to location - \return 0 Function succeeded - \return 1 Function failed - */ -#define __STLEXH (uint32_t)__builtin_arm_stlex - - -/** - \brief Store-Release Exclusive (32 bit) - \details Executes a STL exclusive instruction for 32 bit values. - \param [in] value Value to store - \param [in] ptr Pointer to location - \return 0 Function succeeded - \return 1 Function failed - */ -#define __STLEX (uint32_t)__builtin_arm_stlex - -#endif /* (__ARM_ARCH_8M__ == 1U) */ - -/*@}*/ /* end of group CMSIS_Core_InstructionInterface */ - - -/* ################### Compiler specific Intrinsics ########################### */ -/** \defgroup CMSIS_SIMD_intrinsics CMSIS SIMD Intrinsics - Access to dedicated SIMD instructions - @{ -*/ - -#if (__ARM_FEATURE_DSP == 1U) /* ToDo: ARMCC_V6: This should be ARCH >= ARMv7-M + SIMD */ - -__attribute__((always_inline)) __STATIC_INLINE uint32_t __SADD8(uint32_t op1, uint32_t op2) -{ - uint32_t result; - - __ASM volatile ("sadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); - return(result); -} - -__attribute__((always_inline)) __STATIC_INLINE uint32_t __QADD8(uint32_t op1, uint32_t op2) -{ - uint32_t result; - - __ASM volatile ("qadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); - return(result); -} - -__attribute__((always_inline)) __STATIC_INLINE uint32_t __SHADD8(uint32_t op1, uint32_t op2) -{ - uint32_t result; - - __ASM volatile ("shadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); - return(result); -} - -__attribute__((always_inline)) __STATIC_INLINE uint32_t __UADD8(uint32_t op1, uint32_t op2) -{ - uint32_t result; - - __ASM volatile ("uadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); - return(result); -} - -__attribute__((always_inline)) __STATIC_INLINE uint32_t __UQADD8(uint32_t op1, uint32_t op2) -{ - uint32_t result; - - __ASM volatile ("uqadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); - return(result); -} - -__attribute__((always_inline)) __STATIC_INLINE uint32_t __UHADD8(uint32_t op1, uint32_t op2) -{ - uint32_t result; - - __ASM volatile ("uhadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); - return(result); -} - - -__attribute__((always_inline)) __STATIC_INLINE uint32_t __SSUB8(uint32_t op1, uint32_t op2) -{ - uint32_t result; - - __ASM volatile ("ssub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); - return(result); -} - -__attribute__((always_inline)) __STATIC_INLINE uint32_t __QSUB8(uint32_t op1, uint32_t op2) -{ - uint32_t result; - - __ASM volatile ("qsub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); - return(result); -} - -__attribute__((always_inline)) __STATIC_INLINE uint32_t __SHSUB8(uint32_t op1, uint32_t op2) -{ - uint32_t result; - - __ASM volatile ("shsub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); - return(result); -} - -__attribute__((always_inline)) __STATIC_INLINE uint32_t __USUB8(uint32_t op1, uint32_t op2) -{ - uint32_t result; - - __ASM volatile ("usub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); - return(result); -} - -__attribute__((always_inline)) __STATIC_INLINE uint32_t __UQSUB8(uint32_t op1, uint32_t op2) -{ - uint32_t result; - - __ASM volatile ("uqsub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); - return(result); -} - -__attribute__((always_inline)) __STATIC_INLINE uint32_t __UHSUB8(uint32_t op1, uint32_t op2) -{ - uint32_t result; - - __ASM volatile ("uhsub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); - return(result); -} - - -__attribute__((always_inline)) __STATIC_INLINE uint32_t __SADD16(uint32_t op1, uint32_t op2) -{ - uint32_t result; - - __ASM volatile ("sadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); - return(result); -} - -__attribute__((always_inline)) __STATIC_INLINE uint32_t __QADD16(uint32_t op1, uint32_t op2) -{ - uint32_t result; - - __ASM volatile ("qadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); - return(result); -} - -__attribute__((always_inline)) __STATIC_INLINE uint32_t __SHADD16(uint32_t op1, uint32_t op2) -{ - uint32_t result; - - __ASM volatile ("shadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); - return(result); -} - -__attribute__((always_inline)) __STATIC_INLINE uint32_t __UADD16(uint32_t op1, uint32_t op2) -{ - uint32_t result; - - __ASM volatile ("uadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); - return(result); -} - -__attribute__((always_inline)) __STATIC_INLINE uint32_t __UQADD16(uint32_t op1, uint32_t op2) -{ - uint32_t result; - - __ASM volatile ("uqadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); - return(result); -} - -__attribute__((always_inline)) __STATIC_INLINE uint32_t __UHADD16(uint32_t op1, uint32_t op2) -{ - uint32_t result; - - __ASM volatile ("uhadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); - return(result); -} - -__attribute__((always_inline)) __STATIC_INLINE uint32_t __SSUB16(uint32_t op1, uint32_t op2) -{ - uint32_t result; - - __ASM volatile ("ssub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); - return(result); -} - -__attribute__((always_inline)) __STATIC_INLINE uint32_t __QSUB16(uint32_t op1, uint32_t op2) -{ - uint32_t result; - - __ASM volatile ("qsub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); - return(result); -} - -__attribute__((always_inline)) __STATIC_INLINE uint32_t __SHSUB16(uint32_t op1, uint32_t op2) -{ - uint32_t result; - - __ASM volatile ("shsub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); - return(result); -} - -__attribute__((always_inline)) __STATIC_INLINE uint32_t __USUB16(uint32_t op1, uint32_t op2) -{ - uint32_t result; - - __ASM volatile ("usub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); - return(result); -} - -__attribute__((always_inline)) __STATIC_INLINE uint32_t __UQSUB16(uint32_t op1, uint32_t op2) -{ - uint32_t result; - - __ASM volatile ("uqsub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); - return(result); -} - -__attribute__((always_inline)) __STATIC_INLINE uint32_t __UHSUB16(uint32_t op1, uint32_t op2) -{ - uint32_t result; - - __ASM volatile ("uhsub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); - return(result); -} - -__attribute__((always_inline)) __STATIC_INLINE uint32_t __SASX(uint32_t op1, uint32_t op2) -{ - uint32_t result; - - __ASM volatile ("sasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); - return(result); -} - -__attribute__((always_inline)) __STATIC_INLINE uint32_t __QASX(uint32_t op1, uint32_t op2) -{ - uint32_t result; - - __ASM volatile ("qasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); - return(result); -} - -__attribute__((always_inline)) __STATIC_INLINE uint32_t __SHASX(uint32_t op1, uint32_t op2) -{ - uint32_t result; - - __ASM volatile ("shasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); - return(result); -} - -__attribute__((always_inline)) __STATIC_INLINE uint32_t __UASX(uint32_t op1, uint32_t op2) -{ - uint32_t result; - - __ASM volatile ("uasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); - return(result); -} - -__attribute__((always_inline)) __STATIC_INLINE uint32_t __UQASX(uint32_t op1, uint32_t op2) -{ - uint32_t result; - - __ASM volatile ("uqasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); - return(result); -} - -__attribute__((always_inline)) __STATIC_INLINE uint32_t __UHASX(uint32_t op1, uint32_t op2) -{ - uint32_t result; - - __ASM volatile ("uhasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); - return(result); -} - -__attribute__((always_inline)) __STATIC_INLINE uint32_t __SSAX(uint32_t op1, uint32_t op2) -{ - uint32_t result; - - __ASM volatile ("ssax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); - return(result); -} - -__attribute__((always_inline)) __STATIC_INLINE uint32_t __QSAX(uint32_t op1, uint32_t op2) -{ - uint32_t result; - - __ASM volatile ("qsax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); - return(result); -} - -__attribute__((always_inline)) __STATIC_INLINE uint32_t __SHSAX(uint32_t op1, uint32_t op2) -{ - uint32_t result; - - __ASM volatile ("shsax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); - return(result); -} - -__attribute__((always_inline)) __STATIC_INLINE uint32_t __USAX(uint32_t op1, uint32_t op2) -{ - uint32_t result; - - __ASM volatile ("usax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); - return(result); -} - -__attribute__((always_inline)) __STATIC_INLINE uint32_t __UQSAX(uint32_t op1, uint32_t op2) -{ - uint32_t result; - - __ASM volatile ("uqsax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); - return(result); -} - -__attribute__((always_inline)) __STATIC_INLINE uint32_t __UHSAX(uint32_t op1, uint32_t op2) -{ - uint32_t result; - - __ASM volatile ("uhsax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); - return(result); -} - -__attribute__((always_inline)) __STATIC_INLINE uint32_t __USAD8(uint32_t op1, uint32_t op2) -{ - uint32_t result; - - __ASM volatile ("usad8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); - return(result); -} - -__attribute__((always_inline)) __STATIC_INLINE uint32_t __USADA8(uint32_t op1, uint32_t op2, uint32_t op3) -{ - uint32_t result; - - __ASM volatile ("usada8 %0, %1, %2, %3" : "=r" (result) : "r" (op1), "r" (op2), "r" (op3) ); - return(result); -} - -#define __SSAT16(ARG1,ARG2) \ -({ \ - uint32_t __RES, __ARG1 = (ARG1); \ - __ASM ("ssat16 %0, %1, %2" : "=r" (__RES) : "I" (ARG2), "r" (__ARG1) ); \ - __RES; \ - }) - -#define __USAT16(ARG1,ARG2) \ -({ \ - uint32_t __RES, __ARG1 = (ARG1); \ - __ASM ("usat16 %0, %1, %2" : "=r" (__RES) : "I" (ARG2), "r" (__ARG1) ); \ - __RES; \ - }) - -__attribute__((always_inline)) __STATIC_INLINE uint32_t __UXTB16(uint32_t op1) -{ - uint32_t result; - - __ASM volatile ("uxtb16 %0, %1" : "=r" (result) : "r" (op1)); - return(result); -} - -__attribute__((always_inline)) __STATIC_INLINE uint32_t __UXTAB16(uint32_t op1, uint32_t op2) -{ - uint32_t result; - - __ASM volatile ("uxtab16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); - return(result); -} - -__attribute__((always_inline)) __STATIC_INLINE uint32_t __SXTB16(uint32_t op1) -{ - uint32_t result; - - __ASM volatile ("sxtb16 %0, %1" : "=r" (result) : "r" (op1)); - return(result); -} - -__attribute__((always_inline)) __STATIC_INLINE uint32_t __SXTAB16(uint32_t op1, uint32_t op2) -{ - uint32_t result; - - __ASM volatile ("sxtab16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); - return(result); -} - -__attribute__((always_inline)) __STATIC_INLINE uint32_t __SMUAD (uint32_t op1, uint32_t op2) -{ - uint32_t result; - - __ASM volatile ("smuad %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); - return(result); -} - -__attribute__((always_inline)) __STATIC_INLINE uint32_t __SMUADX (uint32_t op1, uint32_t op2) -{ - uint32_t result; - - __ASM volatile ("smuadx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); - return(result); -} - -__attribute__((always_inline)) __STATIC_INLINE uint32_t __SMLAD (uint32_t op1, uint32_t op2, uint32_t op3) -{ - uint32_t result; - - __ASM volatile ("smlad %0, %1, %2, %3" : "=r" (result) : "r" (op1), "r" (op2), "r" (op3) ); - return(result); -} - -__attribute__((always_inline)) __STATIC_INLINE uint32_t __SMLADX (uint32_t op1, uint32_t op2, uint32_t op3) -{ - uint32_t result; - - __ASM volatile ("smladx %0, %1, %2, %3" : "=r" (result) : "r" (op1), "r" (op2), "r" (op3) ); - return(result); -} - -__attribute__((always_inline)) __STATIC_INLINE uint64_t __SMLALD (uint32_t op1, uint32_t op2, uint64_t acc) -{ - union llreg_u{ - uint32_t w32[2]; - uint64_t w64; - } llr; - llr.w64 = acc; - -#ifndef __ARMEB__ /* Little endian */ - __ASM volatile ("smlald %0, %1, %2, %3" : "=r" (llr.w32[0]), "=r" (llr.w32[1]): "r" (op1), "r" (op2) , "0" (llr.w32[0]), "1" (llr.w32[1]) ); -#else /* Big endian */ - __ASM volatile ("smlald %0, %1, %2, %3" : "=r" (llr.w32[1]), "=r" (llr.w32[0]): "r" (op1), "r" (op2) , "0" (llr.w32[1]), "1" (llr.w32[0]) ); -#endif - - return(llr.w64); -} - -__attribute__((always_inline)) __STATIC_INLINE uint64_t __SMLALDX (uint32_t op1, uint32_t op2, uint64_t acc) -{ - union llreg_u{ - uint32_t w32[2]; - uint64_t w64; - } llr; - llr.w64 = acc; - -#ifndef __ARMEB__ /* Little endian */ - __ASM volatile ("smlaldx %0, %1, %2, %3" : "=r" (llr.w32[0]), "=r" (llr.w32[1]): "r" (op1), "r" (op2) , "0" (llr.w32[0]), "1" (llr.w32[1]) ); -#else /* Big endian */ - __ASM volatile ("smlaldx %0, %1, %2, %3" : "=r" (llr.w32[1]), "=r" (llr.w32[0]): "r" (op1), "r" (op2) , "0" (llr.w32[1]), "1" (llr.w32[0]) ); -#endif - - return(llr.w64); -} - -__attribute__((always_inline)) __STATIC_INLINE uint32_t __SMUSD (uint32_t op1, uint32_t op2) -{ - uint32_t result; - - __ASM volatile ("smusd %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); - return(result); -} - -__attribute__((always_inline)) __STATIC_INLINE uint32_t __SMUSDX (uint32_t op1, uint32_t op2) -{ - uint32_t result; - - __ASM volatile ("smusdx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); - return(result); -} - -__attribute__((always_inline)) __STATIC_INLINE uint32_t __SMLSD (uint32_t op1, uint32_t op2, uint32_t op3) -{ - uint32_t result; - - __ASM volatile ("smlsd %0, %1, %2, %3" : "=r" (result) : "r" (op1), "r" (op2), "r" (op3) ); - return(result); -} - -__attribute__((always_inline)) __STATIC_INLINE uint32_t __SMLSDX (uint32_t op1, uint32_t op2, uint32_t op3) -{ - uint32_t result; - - __ASM volatile ("smlsdx %0, %1, %2, %3" : "=r" (result) : "r" (op1), "r" (op2), "r" (op3) ); - return(result); -} - -__attribute__((always_inline)) __STATIC_INLINE uint64_t __SMLSLD (uint32_t op1, uint32_t op2, uint64_t acc) -{ - union llreg_u{ - uint32_t w32[2]; - uint64_t w64; - } llr; - llr.w64 = acc; - -#ifndef __ARMEB__ /* Little endian */ - __ASM volatile ("smlsld %0, %1, %2, %3" : "=r" (llr.w32[0]), "=r" (llr.w32[1]): "r" (op1), "r" (op2) , "0" (llr.w32[0]), "1" (llr.w32[1]) ); -#else /* Big endian */ - __ASM volatile ("smlsld %0, %1, %2, %3" : "=r" (llr.w32[1]), "=r" (llr.w32[0]): "r" (op1), "r" (op2) , "0" (llr.w32[1]), "1" (llr.w32[0]) ); -#endif - - return(llr.w64); -} - -__attribute__((always_inline)) __STATIC_INLINE uint64_t __SMLSLDX (uint32_t op1, uint32_t op2, uint64_t acc) -{ - union llreg_u{ - uint32_t w32[2]; - uint64_t w64; - } llr; - llr.w64 = acc; - -#ifndef __ARMEB__ /* Little endian */ - __ASM volatile ("smlsldx %0, %1, %2, %3" : "=r" (llr.w32[0]), "=r" (llr.w32[1]): "r" (op1), "r" (op2) , "0" (llr.w32[0]), "1" (llr.w32[1]) ); -#else /* Big endian */ - __ASM volatile ("smlsldx %0, %1, %2, %3" : "=r" (llr.w32[1]), "=r" (llr.w32[0]): "r" (op1), "r" (op2) , "0" (llr.w32[1]), "1" (llr.w32[0]) ); -#endif - - return(llr.w64); -} - -__attribute__((always_inline)) __STATIC_INLINE uint32_t __SEL (uint32_t op1, uint32_t op2) -{ - uint32_t result; - - __ASM volatile ("sel %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); - return(result); -} - -__attribute__((always_inline)) __STATIC_INLINE int32_t __QADD( int32_t op1, int32_t op2) -{ - int32_t result; - - __ASM volatile ("qadd %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); - return(result); -} - -__attribute__((always_inline)) __STATIC_INLINE int32_t __QSUB( int32_t op1, int32_t op2) -{ - int32_t result; - - __ASM volatile ("qsub %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); - return(result); -} - -#define __PKHBT(ARG1,ARG2,ARG3) \ -({ \ - uint32_t __RES, __ARG1 = (ARG1), __ARG2 = (ARG2); \ - __ASM ("pkhbt %0, %1, %2, lsl %3" : "=r" (__RES) : "r" (__ARG1), "r" (__ARG2), "I" (ARG3) ); \ - __RES; \ - }) - -#define __PKHTB(ARG1,ARG2,ARG3) \ -({ \ - uint32_t __RES, __ARG1 = (ARG1), __ARG2 = (ARG2); \ - if (ARG3 == 0) \ - __ASM ("pkhtb %0, %1, %2" : "=r" (__RES) : "r" (__ARG1), "r" (__ARG2) ); \ - else \ - __ASM ("pkhtb %0, %1, %2, asr %3" : "=r" (__RES) : "r" (__ARG1), "r" (__ARG2), "I" (ARG3) ); \ - __RES; \ - }) - -__attribute__((always_inline)) __STATIC_INLINE uint32_t __SMMLA (int32_t op1, int32_t op2, int32_t op3) -{ - int32_t result; - - __ASM volatile ("smmla %0, %1, %2, %3" : "=r" (result): "r" (op1), "r" (op2), "r" (op3) ); - return(result); -} - -#endif /* (__ARM_FEATURE_DSP == 1U) */ -/*@} end of group CMSIS_SIMD_intrinsics */ - - -#endif /* __CMSIS_ARMCC_V6_H */ diff --git a/bsp/essemi/es32f0334/libraries/CMSIS/Include/cmsis_gcc.h b/bsp/essemi/es32f0334/libraries/CMSIS/Include/cmsis_gcc.h deleted file mode 100644 index bb89fbba9e..0000000000 --- a/bsp/essemi/es32f0334/libraries/CMSIS/Include/cmsis_gcc.h +++ /dev/null @@ -1,1373 +0,0 @@ -/**************************************************************************//** - * @file cmsis_gcc.h - * @brief CMSIS Cortex-M Core Function/Instruction Header File - * @version V4.30 - * @date 20. October 2015 - ******************************************************************************/ -/* Copyright (c) 2009 - 2015 ARM LIMITED - - All rights reserved. - Redistribution and use in source and binary forms, with or without - modification, are permitted provided that the following conditions are met: - - Redistributions of source code must retain the above copyright - notice, this list of conditions and the following disclaimer. - - Redistributions in binary form must reproduce the above copyright - notice, this list of conditions and the following disclaimer in the - documentation and/or other materials provided with the distribution. - - Neither the name of ARM nor the names of its contributors may be used - to endorse or promote products derived from this software without - specific prior written permission. - * - THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" - AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE - ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE - LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR - CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF - SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS - INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN - CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) - ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE - POSSIBILITY OF SUCH DAMAGE. - ---------------------------------------------------------------------------*/ - - -#ifndef __CMSIS_GCC_H -#define __CMSIS_GCC_H - -/* ignore some GCC warnings */ -#if defined ( __GNUC__ ) -#pragma GCC diagnostic push -#pragma GCC diagnostic ignored "-Wsign-conversion" -#pragma GCC diagnostic ignored "-Wconversion" -#pragma GCC diagnostic ignored "-Wunused-parameter" -#endif - - -/* ########################### Core Function Access ########################### */ -/** \ingroup CMSIS_Core_FunctionInterface - \defgroup CMSIS_Core_RegAccFunctions CMSIS Core Register Access Functions - @{ - */ - -/** - \brief Enable IRQ Interrupts - \details Enables IRQ interrupts by clearing the I-bit in the CPSR. - Can only be executed in Privileged modes. - */ -__attribute__( ( always_inline ) ) __STATIC_INLINE void __enable_irq(void) -{ - __ASM volatile ("cpsie i" : : : "memory"); -} - - -/** - \brief Disable IRQ Interrupts - \details Disables IRQ interrupts by setting the I-bit in the CPSR. - Can only be executed in Privileged modes. - */ -__attribute__( ( always_inline ) ) __STATIC_INLINE void __disable_irq(void) -{ - __ASM volatile ("cpsid i" : : : "memory"); -} - - -/** - \brief Get Control Register - \details Returns the content of the Control Register. - \return Control Register value - */ -__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_CONTROL(void) -{ - uint32_t result; - - __ASM volatile ("MRS %0, control" : "=r" (result) ); - return(result); -} - - -/** - \brief Set Control Register - \details Writes the given value to the Control Register. - \param [in] control Control Register value to set - */ -__attribute__( ( always_inline ) ) __STATIC_INLINE void __set_CONTROL(uint32_t control) -{ - __ASM volatile ("MSR control, %0" : : "r" (control) : "memory"); -} - - -/** - \brief Get IPSR Register - \details Returns the content of the IPSR Register. - \return IPSR Register value - */ -__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_IPSR(void) -{ - uint32_t result; - - __ASM volatile ("MRS %0, ipsr" : "=r" (result) ); - return(result); -} - - -/** - \brief Get APSR Register - \details Returns the content of the APSR Register. - \return APSR Register value - */ -__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_APSR(void) -{ - uint32_t result; - - __ASM volatile ("MRS %0, apsr" : "=r" (result) ); - return(result); -} - - -/** - \brief Get xPSR Register - \details Returns the content of the xPSR Register. - - \return xPSR Register value - */ -__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_xPSR(void) -{ - uint32_t result; - - __ASM volatile ("MRS %0, xpsr" : "=r" (result) ); - return(result); -} - - -/** - \brief Get Process Stack Pointer - \details Returns the current value of the Process Stack Pointer (PSP). - \return PSP Register value - */ -__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_PSP(void) -{ - register uint32_t result; - - __ASM volatile ("MRS %0, psp\n" : "=r" (result) ); - return(result); -} - - -/** - \brief Set Process Stack Pointer - \details Assigns the given value to the Process Stack Pointer (PSP). - \param [in] topOfProcStack Process Stack Pointer value to set - */ -__attribute__( ( always_inline ) ) __STATIC_INLINE void __set_PSP(uint32_t topOfProcStack) -{ - __ASM volatile ("MSR psp, %0\n" : : "r" (topOfProcStack) : "sp"); -} - - -/** - \brief Get Main Stack Pointer - \details Returns the current value of the Main Stack Pointer (MSP). - \return MSP Register value - */ -__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_MSP(void) -{ - register uint32_t result; - - __ASM volatile ("MRS %0, msp\n" : "=r" (result) ); - return(result); -} - - -/** - \brief Set Main Stack Pointer - \details Assigns the given value to the Main Stack Pointer (MSP). - - \param [in] topOfMainStack Main Stack Pointer value to set - */ -__attribute__( ( always_inline ) ) __STATIC_INLINE void __set_MSP(uint32_t topOfMainStack) -{ - __ASM volatile ("MSR msp, %0\n" : : "r" (topOfMainStack) : "sp"); -} - - -/** - \brief Get Priority Mask - \details Returns the current state of the priority mask bit from the Priority Mask Register. - \return Priority Mask value - */ -__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_PRIMASK(void) -{ - uint32_t result; - - __ASM volatile ("MRS %0, primask" : "=r" (result) ); - return(result); -} - - -/** - \brief Set Priority Mask - \details Assigns the given value to the Priority Mask Register. - \param [in] priMask Priority Mask - */ -__attribute__( ( always_inline ) ) __STATIC_INLINE void __set_PRIMASK(uint32_t priMask) -{ - __ASM volatile ("MSR primask, %0" : : "r" (priMask) : "memory"); -} - - -#if (__CORTEX_M >= 0x03U) - -/** - \brief Enable FIQ - \details Enables FIQ interrupts by clearing the F-bit in the CPSR. - Can only be executed in Privileged modes. - */ -__attribute__( ( always_inline ) ) __STATIC_INLINE void __enable_fault_irq(void) -{ - __ASM volatile ("cpsie f" : : : "memory"); -} - - -/** - \brief Disable FIQ - \details Disables FIQ interrupts by setting the F-bit in the CPSR. - Can only be executed in Privileged modes. - */ -__attribute__( ( always_inline ) ) __STATIC_INLINE void __disable_fault_irq(void) -{ - __ASM volatile ("cpsid f" : : : "memory"); -} - - -/** - \brief Get Base Priority - \details Returns the current value of the Base Priority register. - \return Base Priority register value - */ -__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_BASEPRI(void) -{ - uint32_t result; - - __ASM volatile ("MRS %0, basepri" : "=r" (result) ); - return(result); -} - - -/** - \brief Set Base Priority - \details Assigns the given value to the Base Priority register. - \param [in] basePri Base Priority value to set - */ -__attribute__( ( always_inline ) ) __STATIC_INLINE void __set_BASEPRI(uint32_t value) -{ - __ASM volatile ("MSR basepri, %0" : : "r" (value) : "memory"); -} - - -/** - \brief Set Base Priority with condition - \details Assigns the given value to the Base Priority register only if BASEPRI masking is disabled, - or the new value increases the BASEPRI priority level. - \param [in] basePri Base Priority value to set - */ -__attribute__( ( always_inline ) ) __STATIC_INLINE void __set_BASEPRI_MAX(uint32_t value) -{ - __ASM volatile ("MSR basepri_max, %0" : : "r" (value) : "memory"); -} - - -/** - \brief Get Fault Mask - \details Returns the current value of the Fault Mask register. - \return Fault Mask register value - */ -__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_FAULTMASK(void) -{ - uint32_t result; - - __ASM volatile ("MRS %0, faultmask" : "=r" (result) ); - return(result); -} - - -/** - \brief Set Fault Mask - \details Assigns the given value to the Fault Mask register. - \param [in] faultMask Fault Mask value to set - */ -__attribute__( ( always_inline ) ) __STATIC_INLINE void __set_FAULTMASK(uint32_t faultMask) -{ - __ASM volatile ("MSR faultmask, %0" : : "r" (faultMask) : "memory"); -} - -#endif /* (__CORTEX_M >= 0x03U) */ - - -#if (__CORTEX_M == 0x04U) || (__CORTEX_M == 0x07U) - -/** - \brief Get FPSCR - \details Returns the current value of the Floating Point Status/Control register. - \return Floating Point Status/Control register value - */ -__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_FPSCR(void) -{ -#if (__FPU_PRESENT == 1U) && (__FPU_USED == 1U) - uint32_t result; - - /* Empty asm statement works as a scheduling barrier */ - __ASM volatile (""); - __ASM volatile ("VMRS %0, fpscr" : "=r" (result) ); - __ASM volatile (""); - return(result); -#else - return(0); -#endif -} - - -/** - \brief Set FPSCR - \details Assigns the given value to the Floating Point Status/Control register. - \param [in] fpscr Floating Point Status/Control value to set - */ -__attribute__( ( always_inline ) ) __STATIC_INLINE void __set_FPSCR(uint32_t fpscr) -{ -#if (__FPU_PRESENT == 1U) && (__FPU_USED == 1U) - /* Empty asm statement works as a scheduling barrier */ - __ASM volatile (""); - __ASM volatile ("VMSR fpscr, %0" : : "r" (fpscr) : "vfpcc"); - __ASM volatile (""); -#endif -} - -#endif /* (__CORTEX_M == 0x04U) || (__CORTEX_M == 0x07U) */ - - - -/*@} end of CMSIS_Core_RegAccFunctions */ - - -/* ########################## Core Instruction Access ######################### */ -/** \defgroup CMSIS_Core_InstructionInterface CMSIS Core Instruction Interface - Access to dedicated instructions - @{ -*/ - -/* Define macros for porting to both thumb1 and thumb2. - * For thumb1, use low register (r0-r7), specified by constraint "l" - * Otherwise, use general registers, specified by constraint "r" */ -#if defined (__thumb__) && !defined (__thumb2__) -#define __CMSIS_GCC_OUT_REG(r) "=l" (r) -#define __CMSIS_GCC_USE_REG(r) "l" (r) -#else -#define __CMSIS_GCC_OUT_REG(r) "=r" (r) -#define __CMSIS_GCC_USE_REG(r) "r" (r) -#endif - -/** - \brief No Operation - \details No Operation does nothing. This instruction can be used for code alignment purposes. - */ -__attribute__((always_inline)) __STATIC_INLINE void __NOP(void) -{ - __ASM volatile ("nop"); -} - - -/** - \brief Wait For Interrupt - \details Wait For Interrupt is a hint instruction that suspends execution until one of a number of events occurs. - */ -__attribute__((always_inline)) __STATIC_INLINE void __WFI(void) -{ - __ASM volatile ("wfi"); -} - - -/** - \brief Wait For Event - \details Wait For Event is a hint instruction that permits the processor to enter - a low-power state until one of a number of events occurs. - */ -__attribute__((always_inline)) __STATIC_INLINE void __WFE(void) -{ - __ASM volatile ("wfe"); -} - - -/** - \brief Send Event - \details Send Event is a hint instruction. It causes an event to be signaled to the CPU. - */ -__attribute__((always_inline)) __STATIC_INLINE void __SEV(void) -{ - __ASM volatile ("sev"); -} - - -/** - \brief Instruction Synchronization Barrier - \details Instruction Synchronization Barrier flushes the pipeline in the processor, - so that all instructions following the ISB are fetched from cache or memory, - after the instruction has been completed. - */ -__attribute__((always_inline)) __STATIC_INLINE void __ISB(void) -{ - __ASM volatile ("isb 0xF":::"memory"); -} - - -/** - \brief Data Synchronization Barrier - \details Acts as a special kind of Data Memory Barrier. - It completes when all explicit memory accesses before this instruction complete. - */ -__attribute__((always_inline)) __STATIC_INLINE void __DSB(void) -{ - __ASM volatile ("dsb 0xF":::"memory"); -} - - -/** - \brief Data Memory Barrier - \details Ensures the apparent order of the explicit memory operations before - and after the instruction, without ensuring their completion. - */ -__attribute__((always_inline)) __STATIC_INLINE void __DMB(void) -{ - __ASM volatile ("dmb 0xF":::"memory"); -} - - -/** - \brief Reverse byte order (32 bit) - \details Reverses the byte order in integer value. - \param [in] value Value to reverse - \return Reversed value - */ -__attribute__((always_inline)) __STATIC_INLINE uint32_t __REV(uint32_t value) -{ -#if (__GNUC__ > 4) || (__GNUC__ == 4 && __GNUC_MINOR__ >= 5) - return __builtin_bswap32(value); -#else - uint32_t result; - - __ASM volatile ("rev %0, %1" : __CMSIS_GCC_OUT_REG (result) : __CMSIS_GCC_USE_REG (value) ); - return(result); -#endif -} - - -/** - \brief Reverse byte order (16 bit) - \details Reverses the byte order in two unsigned short values. - \param [in] value Value to reverse - \return Reversed value - */ -__attribute__((always_inline)) __STATIC_INLINE uint32_t __REV16(uint32_t value) -{ - uint32_t result; - - __ASM volatile ("rev16 %0, %1" : __CMSIS_GCC_OUT_REG (result) : __CMSIS_GCC_USE_REG (value) ); - return(result); -} - - -/** - \brief Reverse byte order in signed short value - \details Reverses the byte order in a signed short value with sign extension to integer. - \param [in] value Value to reverse - \return Reversed value - */ -__attribute__((always_inline)) __STATIC_INLINE int32_t __REVSH(int32_t value) -{ -#if (__GNUC__ > 4) || (__GNUC__ == 4 && __GNUC_MINOR__ >= 8) - return (short)__builtin_bswap16(value); -#else - int32_t result; - - __ASM volatile ("revsh %0, %1" : __CMSIS_GCC_OUT_REG (result) : __CMSIS_GCC_USE_REG (value) ); - return(result); -#endif -} - - -/** - \brief Rotate Right in unsigned value (32 bit) - \details Rotate Right (immediate) provides the value of the contents of a register rotated by a variable number of bits. - \param [in] value Value to rotate - \param [in] value Number of Bits to rotate - \return Rotated value - */ -__attribute__((always_inline)) __STATIC_INLINE uint32_t __ROR(uint32_t op1, uint32_t op2) -{ - return (op1 >> op2) | (op1 << (32U - op2)); -} - - -/** - \brief Breakpoint - \details Causes the processor to enter Debug state. - Debug tools can use this to investigate system state when the instruction at a particular address is reached. - \param [in] value is ignored by the processor. - If required, a debugger can use it to store additional information about the breakpoint. - */ -#define __BKPT(value) __ASM volatile ("bkpt "#value) - - -/** - \brief Reverse bit order of value - \details Reverses the bit order of the given value. - \param [in] value Value to reverse - \return Reversed value - */ -__attribute__((always_inline)) __STATIC_INLINE uint32_t __RBIT(uint32_t value) -{ - uint32_t result; - -#if (__CORTEX_M >= 0x03U) || (__CORTEX_SC >= 300U) - __ASM volatile ("rbit %0, %1" : "=r" (result) : "r" (value) ); -#else - int32_t s = 4 /*sizeof(v)*/ * 8 - 1; /* extra shift needed at end */ - - result = value; /* r will be reversed bits of v; first get LSB of v */ - for (value >>= 1U; value; value >>= 1U) - { - result <<= 1U; - result |= value & 1U; - s--; - } - result <<= s; /* shift when v's highest bits are zero */ -#endif - return(result); -} - - -/** - \brief Count leading zeros - \details Counts the number of leading zeros of a data value. - \param [in] value Value to count the leading zeros - \return number of leading zeros in value - */ -#define __CLZ __builtin_clz - - -#if (__CORTEX_M >= 0x03U) || (__CORTEX_SC >= 300U) - -/** - \brief LDR Exclusive (8 bit) - \details Executes a exclusive LDR instruction for 8 bit value. - \param [in] ptr Pointer to data - \return value of type uint8_t at (*ptr) - */ -__attribute__((always_inline)) __STATIC_INLINE uint8_t __LDREXB(volatile uint8_t *addr) -{ - uint32_t result; - -#if (__GNUC__ > 4) || (__GNUC__ == 4 && __GNUC_MINOR__ >= 8) - __ASM volatile ("ldrexb %0, %1" : "=r" (result) : "Q" (*addr) ); -#else - /* Prior to GCC 4.8, "Q" will be expanded to [rx, #0] which is not - accepted by assembler. So has to use following less efficient pattern. - */ - __ASM volatile ("ldrexb %0, [%1]" : "=r" (result) : "r" (addr) : "memory" ); -#endif - return ((uint8_t) result); /* Add explicit type cast here */ -} - - -/** - \brief LDR Exclusive (16 bit) - \details Executes a exclusive LDR instruction for 16 bit values. - \param [in] ptr Pointer to data - \return value of type uint16_t at (*ptr) - */ -__attribute__((always_inline)) __STATIC_INLINE uint16_t __LDREXH(volatile uint16_t *addr) -{ - uint32_t result; - -#if (__GNUC__ > 4) || (__GNUC__ == 4 && __GNUC_MINOR__ >= 8) - __ASM volatile ("ldrexh %0, %1" : "=r" (result) : "Q" (*addr) ); -#else - /* Prior to GCC 4.8, "Q" will be expanded to [rx, #0] which is not - accepted by assembler. So has to use following less efficient pattern. - */ - __ASM volatile ("ldrexh %0, [%1]" : "=r" (result) : "r" (addr) : "memory" ); -#endif - return ((uint16_t) result); /* Add explicit type cast here */ -} - - -/** - \brief LDR Exclusive (32 bit) - \details Executes a exclusive LDR instruction for 32 bit values. - \param [in] ptr Pointer to data - \return value of type uint32_t at (*ptr) - */ -__attribute__((always_inline)) __STATIC_INLINE uint32_t __LDREXW(volatile uint32_t *addr) -{ - uint32_t result; - - __ASM volatile ("ldrex %0, %1" : "=r" (result) : "Q" (*addr) ); - return(result); -} - - -/** - \brief STR Exclusive (8 bit) - \details Executes a exclusive STR instruction for 8 bit values. - \param [in] value Value to store - \param [in] ptr Pointer to location - \return 0 Function succeeded - \return 1 Function failed - */ -__attribute__((always_inline)) __STATIC_INLINE uint32_t __STREXB(uint8_t value, volatile uint8_t *addr) -{ - uint32_t result; - - __ASM volatile ("strexb %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" ((uint32_t)value) ); - return(result); -} - - -/** - \brief STR Exclusive (16 bit) - \details Executes a exclusive STR instruction for 16 bit values. - \param [in] value Value to store - \param [in] ptr Pointer to location - \return 0 Function succeeded - \return 1 Function failed - */ -__attribute__((always_inline)) __STATIC_INLINE uint32_t __STREXH(uint16_t value, volatile uint16_t *addr) -{ - uint32_t result; - - __ASM volatile ("strexh %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" ((uint32_t)value) ); - return(result); -} - - -/** - \brief STR Exclusive (32 bit) - \details Executes a exclusive STR instruction for 32 bit values. - \param [in] value Value to store - \param [in] ptr Pointer to location - \return 0 Function succeeded - \return 1 Function failed - */ -__attribute__((always_inline)) __STATIC_INLINE uint32_t __STREXW(uint32_t value, volatile uint32_t *addr) -{ - uint32_t result; - - __ASM volatile ("strex %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" (value) ); - return(result); -} - - -/** - \brief Remove the exclusive lock - \details Removes the exclusive lock which is created by LDREX. - */ -__attribute__((always_inline)) __STATIC_INLINE void __CLREX(void) -{ - __ASM volatile ("clrex" ::: "memory"); -} - - -/** - \brief Signed Saturate - \details Saturates a signed value. - \param [in] value Value to be saturated - \param [in] sat Bit position to saturate to (1..32) - \return Saturated value - */ -#define __SSAT(ARG1,ARG2) \ -({ \ - uint32_t __RES, __ARG1 = (ARG1); \ - __ASM ("ssat %0, %1, %2" : "=r" (__RES) : "I" (ARG2), "r" (__ARG1) ); \ - __RES; \ - }) - - -/** - \brief Unsigned Saturate - \details Saturates an unsigned value. - \param [in] value Value to be saturated - \param [in] sat Bit position to saturate to (0..31) - \return Saturated value - */ -#define __USAT(ARG1,ARG2) \ -({ \ - uint32_t __RES, __ARG1 = (ARG1); \ - __ASM ("usat %0, %1, %2" : "=r" (__RES) : "I" (ARG2), "r" (__ARG1) ); \ - __RES; \ - }) - - -/** - \brief Rotate Right with Extend (32 bit) - \details Moves each bit of a bitstring right by one bit. - The carry input is shifted in at the left end of the bitstring. - \param [in] value Value to rotate - \return Rotated value - */ -__attribute__((always_inline)) __STATIC_INLINE uint32_t __RRX(uint32_t value) -{ - uint32_t result; - - __ASM volatile ("rrx %0, %1" : __CMSIS_GCC_OUT_REG (result) : __CMSIS_GCC_USE_REG (value) ); - return(result); -} - - -/** - \brief LDRT Unprivileged (8 bit) - \details Executes a Unprivileged LDRT instruction for 8 bit value. - \param [in] ptr Pointer to data - \return value of type uint8_t at (*ptr) - */ -__attribute__((always_inline)) __STATIC_INLINE uint8_t __LDRBT(volatile uint8_t *addr) -{ - uint32_t result; - -#if (__GNUC__ > 4) || (__GNUC__ == 4 && __GNUC_MINOR__ >= 8) - __ASM volatile ("ldrbt %0, %1" : "=r" (result) : "Q" (*addr) ); -#else - /* Prior to GCC 4.8, "Q" will be expanded to [rx, #0] which is not - accepted by assembler. So has to use following less efficient pattern. - */ - __ASM volatile ("ldrbt %0, [%1]" : "=r" (result) : "r" (addr) : "memory" ); -#endif - return ((uint8_t) result); /* Add explicit type cast here */ -} - - -/** - \brief LDRT Unprivileged (16 bit) - \details Executes a Unprivileged LDRT instruction for 16 bit values. - \param [in] ptr Pointer to data - \return value of type uint16_t at (*ptr) - */ -__attribute__((always_inline)) __STATIC_INLINE uint16_t __LDRHT(volatile uint16_t *addr) -{ - uint32_t result; - -#if (__GNUC__ > 4) || (__GNUC__ == 4 && __GNUC_MINOR__ >= 8) - __ASM volatile ("ldrht %0, %1" : "=r" (result) : "Q" (*addr) ); -#else - /* Prior to GCC 4.8, "Q" will be expanded to [rx, #0] which is not - accepted by assembler. So has to use following less efficient pattern. - */ - __ASM volatile ("ldrht %0, [%1]" : "=r" (result) : "r" (addr) : "memory" ); -#endif - return ((uint16_t) result); /* Add explicit type cast here */ -} - - -/** - \brief LDRT Unprivileged (32 bit) - \details Executes a Unprivileged LDRT instruction for 32 bit values. - \param [in] ptr Pointer to data - \return value of type uint32_t at (*ptr) - */ -__attribute__((always_inline)) __STATIC_INLINE uint32_t __LDRT(volatile uint32_t *addr) -{ - uint32_t result; - - __ASM volatile ("ldrt %0, %1" : "=r" (result) : "Q" (*addr) ); - return(result); -} - - -/** - \brief STRT Unprivileged (8 bit) - \details Executes a Unprivileged STRT instruction for 8 bit values. - \param [in] value Value to store - \param [in] ptr Pointer to location - */ -__attribute__((always_inline)) __STATIC_INLINE void __STRBT(uint8_t value, volatile uint8_t *addr) -{ - __ASM volatile ("strbt %1, %0" : "=Q" (*addr) : "r" ((uint32_t)value) ); -} - - -/** - \brief STRT Unprivileged (16 bit) - \details Executes a Unprivileged STRT instruction for 16 bit values. - \param [in] value Value to store - \param [in] ptr Pointer to location - */ -__attribute__((always_inline)) __STATIC_INLINE void __STRHT(uint16_t value, volatile uint16_t *addr) -{ - __ASM volatile ("strht %1, %0" : "=Q" (*addr) : "r" ((uint32_t)value) ); -} - - -/** - \brief STRT Unprivileged (32 bit) - \details Executes a Unprivileged STRT instruction for 32 bit values. - \param [in] value Value to store - \param [in] ptr Pointer to location - */ -__attribute__((always_inline)) __STATIC_INLINE void __STRT(uint32_t value, volatile uint32_t *addr) -{ - __ASM volatile ("strt %1, %0" : "=Q" (*addr) : "r" (value) ); -} - -#endif /* (__CORTEX_M >= 0x03U) || (__CORTEX_SC >= 300U) */ - -/*@}*/ /* end of group CMSIS_Core_InstructionInterface */ - - -/* ################### Compiler specific Intrinsics ########################### */ -/** \defgroup CMSIS_SIMD_intrinsics CMSIS SIMD Intrinsics - Access to dedicated SIMD instructions - @{ -*/ - -#if (__CORTEX_M >= 0x04U) /* only for Cortex-M4 and above */ - -__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SADD8(uint32_t op1, uint32_t op2) -{ - uint32_t result; - - __ASM volatile ("sadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); - return(result); -} - -__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __QADD8(uint32_t op1, uint32_t op2) -{ - uint32_t result; - - __ASM volatile ("qadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); - return(result); -} - -__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SHADD8(uint32_t op1, uint32_t op2) -{ - uint32_t result; - - __ASM volatile ("shadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); - return(result); -} - -__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UADD8(uint32_t op1, uint32_t op2) -{ - uint32_t result; - - __ASM volatile ("uadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); - return(result); -} - -__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UQADD8(uint32_t op1, uint32_t op2) -{ - uint32_t result; - - __ASM volatile ("uqadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); - return(result); -} - -__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UHADD8(uint32_t op1, uint32_t op2) -{ - uint32_t result; - - __ASM volatile ("uhadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); - return(result); -} - - -__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SSUB8(uint32_t op1, uint32_t op2) -{ - uint32_t result; - - __ASM volatile ("ssub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); - return(result); -} - -__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __QSUB8(uint32_t op1, uint32_t op2) -{ - uint32_t result; - - __ASM volatile ("qsub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); - return(result); -} - -__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SHSUB8(uint32_t op1, uint32_t op2) -{ - uint32_t result; - - __ASM volatile ("shsub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); - return(result); -} - -__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __USUB8(uint32_t op1, uint32_t op2) -{ - uint32_t result; - - __ASM volatile ("usub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); - return(result); -} - -__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UQSUB8(uint32_t op1, uint32_t op2) -{ - uint32_t result; - - __ASM volatile ("uqsub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); - return(result); -} - -__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UHSUB8(uint32_t op1, uint32_t op2) -{ - uint32_t result; - - __ASM volatile ("uhsub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); - return(result); -} - - -__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SADD16(uint32_t op1, uint32_t op2) -{ - uint32_t result; - - __ASM volatile ("sadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); - return(result); -} - -__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __QADD16(uint32_t op1, uint32_t op2) -{ - uint32_t result; - - __ASM volatile ("qadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); - return(result); -} - -__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SHADD16(uint32_t op1, uint32_t op2) -{ - uint32_t result; - - __ASM volatile ("shadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); - return(result); -} - -__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UADD16(uint32_t op1, uint32_t op2) -{ - uint32_t result; - - __ASM volatile ("uadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); - return(result); -} - -__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UQADD16(uint32_t op1, uint32_t op2) -{ - uint32_t result; - - __ASM volatile ("uqadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); - return(result); -} - -__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UHADD16(uint32_t op1, uint32_t op2) -{ - uint32_t result; - - __ASM volatile ("uhadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); - return(result); -} - -__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SSUB16(uint32_t op1, uint32_t op2) -{ - uint32_t result; - - __ASM volatile ("ssub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); - return(result); -} - -__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __QSUB16(uint32_t op1, uint32_t op2) -{ - uint32_t result; - - __ASM volatile ("qsub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); - return(result); -} - -__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SHSUB16(uint32_t op1, uint32_t op2) -{ - uint32_t result; - - __ASM volatile ("shsub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); - return(result); -} - -__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __USUB16(uint32_t op1, uint32_t op2) -{ - uint32_t result; - - __ASM volatile ("usub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); - return(result); -} - -__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UQSUB16(uint32_t op1, uint32_t op2) -{ - uint32_t result; - - __ASM volatile ("uqsub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); - return(result); -} - -__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UHSUB16(uint32_t op1, uint32_t op2) -{ - uint32_t result; - - __ASM volatile ("uhsub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); - return(result); -} - -__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SASX(uint32_t op1, uint32_t op2) -{ - uint32_t result; - - __ASM volatile ("sasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); - return(result); -} - -__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __QASX(uint32_t op1, uint32_t op2) -{ - uint32_t result; - - __ASM volatile ("qasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); - return(result); -} - -__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SHASX(uint32_t op1, uint32_t op2) -{ - uint32_t result; - - __ASM volatile ("shasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); - return(result); -} - -__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UASX(uint32_t op1, uint32_t op2) -{ - uint32_t result; - - __ASM volatile ("uasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); - return(result); -} - -__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UQASX(uint32_t op1, uint32_t op2) -{ - uint32_t result; - - __ASM volatile ("uqasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); - return(result); -} - -__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UHASX(uint32_t op1, uint32_t op2) -{ - uint32_t result; - - __ASM volatile ("uhasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); - return(result); -} - -__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SSAX(uint32_t op1, uint32_t op2) -{ - uint32_t result; - - __ASM volatile ("ssax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); - return(result); -} - -__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __QSAX(uint32_t op1, uint32_t op2) -{ - uint32_t result; - - __ASM volatile ("qsax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); - return(result); -} - -__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SHSAX(uint32_t op1, uint32_t op2) -{ - uint32_t result; - - __ASM volatile ("shsax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); - return(result); -} - -__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __USAX(uint32_t op1, uint32_t op2) -{ - uint32_t result; - - __ASM volatile ("usax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); - return(result); -} - -__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UQSAX(uint32_t op1, uint32_t op2) -{ - uint32_t result; - - __ASM volatile ("uqsax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); - return(result); -} - -__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UHSAX(uint32_t op1, uint32_t op2) -{ - uint32_t result; - - __ASM volatile ("uhsax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); - return(result); -} - -__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __USAD8(uint32_t op1, uint32_t op2) -{ - uint32_t result; - - __ASM volatile ("usad8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); - return(result); -} - -__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __USADA8(uint32_t op1, uint32_t op2, uint32_t op3) -{ - uint32_t result; - - __ASM volatile ("usada8 %0, %1, %2, %3" : "=r" (result) : "r" (op1), "r" (op2), "r" (op3) ); - return(result); -} - -#define __SSAT16(ARG1,ARG2) \ -({ \ - int32_t __RES, __ARG1 = (ARG1); \ - __ASM ("ssat16 %0, %1, %2" : "=r" (__RES) : "I" (ARG2), "r" (__ARG1) ); \ - __RES; \ - }) - -#define __USAT16(ARG1,ARG2) \ -({ \ - uint32_t __RES, __ARG1 = (ARG1); \ - __ASM ("usat16 %0, %1, %2" : "=r" (__RES) : "I" (ARG2), "r" (__ARG1) ); \ - __RES; \ - }) - -__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UXTB16(uint32_t op1) -{ - uint32_t result; - - __ASM volatile ("uxtb16 %0, %1" : "=r" (result) : "r" (op1)); - return(result); -} - -__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UXTAB16(uint32_t op1, uint32_t op2) -{ - uint32_t result; - - __ASM volatile ("uxtab16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); - return(result); -} - -__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SXTB16(uint32_t op1) -{ - uint32_t result; - - __ASM volatile ("sxtb16 %0, %1" : "=r" (result) : "r" (op1)); - return(result); -} - -__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SXTAB16(uint32_t op1, uint32_t op2) -{ - uint32_t result; - - __ASM volatile ("sxtab16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); - return(result); -} - -__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SMUAD (uint32_t op1, uint32_t op2) -{ - uint32_t result; - - __ASM volatile ("smuad %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); - return(result); -} - -__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SMUADX (uint32_t op1, uint32_t op2) -{ - uint32_t result; - - __ASM volatile ("smuadx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); - return(result); -} - -__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SMLAD (uint32_t op1, uint32_t op2, uint32_t op3) -{ - uint32_t result; - - __ASM volatile ("smlad %0, %1, %2, %3" : "=r" (result) : "r" (op1), "r" (op2), "r" (op3) ); - return(result); -} - -__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SMLADX (uint32_t op1, uint32_t op2, uint32_t op3) -{ - uint32_t result; - - __ASM volatile ("smladx %0, %1, %2, %3" : "=r" (result) : "r" (op1), "r" (op2), "r" (op3) ); - return(result); -} - -__attribute__( ( always_inline ) ) __STATIC_INLINE uint64_t __SMLALD (uint32_t op1, uint32_t op2, uint64_t acc) -{ - union llreg_u{ - uint32_t w32[2]; - uint64_t w64; - } llr; - llr.w64 = acc; - -#ifndef __ARMEB__ /* Little endian */ - __ASM volatile ("smlald %0, %1, %2, %3" : "=r" (llr.w32[0]), "=r" (llr.w32[1]): "r" (op1), "r" (op2) , "0" (llr.w32[0]), "1" (llr.w32[1]) ); -#else /* Big endian */ - __ASM volatile ("smlald %0, %1, %2, %3" : "=r" (llr.w32[1]), "=r" (llr.w32[0]): "r" (op1), "r" (op2) , "0" (llr.w32[1]), "1" (llr.w32[0]) ); -#endif - - return(llr.w64); -} - -__attribute__( ( always_inline ) ) __STATIC_INLINE uint64_t __SMLALDX (uint32_t op1, uint32_t op2, uint64_t acc) -{ - union llreg_u{ - uint32_t w32[2]; - uint64_t w64; - } llr; - llr.w64 = acc; - -#ifndef __ARMEB__ /* Little endian */ - __ASM volatile ("smlaldx %0, %1, %2, %3" : "=r" (llr.w32[0]), "=r" (llr.w32[1]): "r" (op1), "r" (op2) , "0" (llr.w32[0]), "1" (llr.w32[1]) ); -#else /* Big endian */ - __ASM volatile ("smlaldx %0, %1, %2, %3" : "=r" (llr.w32[1]), "=r" (llr.w32[0]): "r" (op1), "r" (op2) , "0" (llr.w32[1]), "1" (llr.w32[0]) ); -#endif - - return(llr.w64); -} - -__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SMUSD (uint32_t op1, uint32_t op2) -{ - uint32_t result; - - __ASM volatile ("smusd %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); - return(result); -} - -__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SMUSDX (uint32_t op1, uint32_t op2) -{ - uint32_t result; - - __ASM volatile ("smusdx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); - return(result); -} - -__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SMLSD (uint32_t op1, uint32_t op2, uint32_t op3) -{ - uint32_t result; - - __ASM volatile ("smlsd %0, %1, %2, %3" : "=r" (result) : "r" (op1), "r" (op2), "r" (op3) ); - return(result); -} - -__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SMLSDX (uint32_t op1, uint32_t op2, uint32_t op3) -{ - uint32_t result; - - __ASM volatile ("smlsdx %0, %1, %2, %3" : "=r" (result) : "r" (op1), "r" (op2), "r" (op3) ); - return(result); -} - -__attribute__( ( always_inline ) ) __STATIC_INLINE uint64_t __SMLSLD (uint32_t op1, uint32_t op2, uint64_t acc) -{ - union llreg_u{ - uint32_t w32[2]; - uint64_t w64; - } llr; - llr.w64 = acc; - -#ifndef __ARMEB__ /* Little endian */ - __ASM volatile ("smlsld %0, %1, %2, %3" : "=r" (llr.w32[0]), "=r" (llr.w32[1]): "r" (op1), "r" (op2) , "0" (llr.w32[0]), "1" (llr.w32[1]) ); -#else /* Big endian */ - __ASM volatile ("smlsld %0, %1, %2, %3" : "=r" (llr.w32[1]), "=r" (llr.w32[0]): "r" (op1), "r" (op2) , "0" (llr.w32[1]), "1" (llr.w32[0]) ); -#endif - - return(llr.w64); -} - -__attribute__( ( always_inline ) ) __STATIC_INLINE uint64_t __SMLSLDX (uint32_t op1, uint32_t op2, uint64_t acc) -{ - union llreg_u{ - uint32_t w32[2]; - uint64_t w64; - } llr; - llr.w64 = acc; - -#ifndef __ARMEB__ /* Little endian */ - __ASM volatile ("smlsldx %0, %1, %2, %3" : "=r" (llr.w32[0]), "=r" (llr.w32[1]): "r" (op1), "r" (op2) , "0" (llr.w32[0]), "1" (llr.w32[1]) ); -#else /* Big endian */ - __ASM volatile ("smlsldx %0, %1, %2, %3" : "=r" (llr.w32[1]), "=r" (llr.w32[0]): "r" (op1), "r" (op2) , "0" (llr.w32[1]), "1" (llr.w32[0]) ); -#endif - - return(llr.w64); -} - -__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SEL (uint32_t op1, uint32_t op2) -{ - uint32_t result; - - __ASM volatile ("sel %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); - return(result); -} - -__attribute__( ( always_inline ) ) __STATIC_INLINE int32_t __QADD( int32_t op1, int32_t op2) -{ - int32_t result; - - __ASM volatile ("qadd %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); - return(result); -} - -__attribute__( ( always_inline ) ) __STATIC_INLINE int32_t __QSUB( int32_t op1, int32_t op2) -{ - int32_t result; - - __ASM volatile ("qsub %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); - return(result); -} - -#define __PKHBT(ARG1,ARG2,ARG3) \ -({ \ - uint32_t __RES, __ARG1 = (ARG1), __ARG2 = (ARG2); \ - __ASM ("pkhbt %0, %1, %2, lsl %3" : "=r" (__RES) : "r" (__ARG1), "r" (__ARG2), "I" (ARG3) ); \ - __RES; \ - }) - -#define __PKHTB(ARG1,ARG2,ARG3) \ -({ \ - uint32_t __RES, __ARG1 = (ARG1), __ARG2 = (ARG2); \ - if (ARG3 == 0) \ - __ASM ("pkhtb %0, %1, %2" : "=r" (__RES) : "r" (__ARG1), "r" (__ARG2) ); \ - else \ - __ASM ("pkhtb %0, %1, %2, asr %3" : "=r" (__RES) : "r" (__ARG1), "r" (__ARG2), "I" (ARG3) ); \ - __RES; \ - }) - -__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SMMLA (int32_t op1, int32_t op2, int32_t op3) -{ - int32_t result; - - __ASM volatile ("smmla %0, %1, %2, %3" : "=r" (result): "r" (op1), "r" (op2), "r" (op3) ); - return(result); -} - -#endif /* (__CORTEX_M >= 0x04) */ -/*@} end of group CMSIS_SIMD_intrinsics */ - - -#if defined ( __GNUC__ ) -#pragma GCC diagnostic pop -#endif - -#endif /* __CMSIS_GCC_H */ diff --git a/bsp/essemi/es32f0334/libraries/CMSIS/Include/core_cm0.h b/bsp/essemi/es32f0334/libraries/CMSIS/Include/core_cm0.h deleted file mode 100644 index 711dad5517..0000000000 --- a/bsp/essemi/es32f0334/libraries/CMSIS/Include/core_cm0.h +++ /dev/null @@ -1,798 +0,0 @@ -/**************************************************************************//** - * @file core_cm0.h - * @brief CMSIS Cortex-M0 Core Peripheral Access Layer Header File - * @version V4.30 - * @date 20. October 2015 - ******************************************************************************/ -/* Copyright (c) 2009 - 2015 ARM LIMITED - - All rights reserved. - Redistribution and use in source and binary forms, with or without - modification, are permitted provided that the following conditions are met: - - Redistributions of source code must retain the above copyright - notice, this list of conditions and the following disclaimer. - - Redistributions in binary form must reproduce the above copyright - notice, this list of conditions and the following disclaimer in the - documentation and/or other materials provided with the distribution. - - Neither the name of ARM nor the names of its contributors may be used - to endorse or promote products derived from this software without - specific prior written permission. - * - THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" - AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE - ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE - LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR - CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF - SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS - INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN - CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) - ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE - POSSIBILITY OF SUCH DAMAGE. - ---------------------------------------------------------------------------*/ - - -#if defined ( __ICCARM__ ) - #pragma system_include /* treat file as system include file for MISRA check */ -#elif defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) - #pragma clang system_header /* treat file as system include file */ -#endif - -#ifndef __CORE_CM0_H_GENERIC -#define __CORE_CM0_H_GENERIC - -#include - -#ifdef __cplusplus - extern "C" { -#endif - -/** - \page CMSIS_MISRA_Exceptions MISRA-C:2004 Compliance Exceptions - CMSIS violates the following MISRA-C:2004 rules: - - \li Required Rule 8.5, object/function definition in header file.
- Function definitions in header files are used to allow 'inlining'. - - \li Required Rule 18.4, declaration of union type or object of union type: '{...}'.
- Unions are used for effective representation of core registers. - - \li Advisory Rule 19.7, Function-like macro defined.
- Function-like macros are used to allow more efficient code. - */ - - -/******************************************************************************* - * CMSIS definitions - ******************************************************************************/ -/** - \ingroup Cortex_M0 - @{ - */ - -/* CMSIS CM0 definitions */ -#define __CM0_CMSIS_VERSION_MAIN (0x04U) /*!< [31:16] CMSIS HAL main version */ -#define __CM0_CMSIS_VERSION_SUB (0x1EU) /*!< [15:0] CMSIS HAL sub version */ -#define __CM0_CMSIS_VERSION ((__CM0_CMSIS_VERSION_MAIN << 16U) | \ - __CM0_CMSIS_VERSION_SUB ) /*!< CMSIS HAL version number */ - -#define __CORTEX_M (0x00U) /*!< Cortex-M Core */ - - -#if defined ( __CC_ARM ) - #define __ASM __asm /*!< asm keyword for ARM Compiler */ - #define __INLINE __inline /*!< inline keyword for ARM Compiler */ - #define __STATIC_INLINE static __inline - -#elif defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) - #define __ASM __asm /*!< asm keyword for ARM Compiler */ - #define __INLINE __inline /*!< inline keyword for ARM Compiler */ - #define __STATIC_INLINE static __inline - -#elif defined ( __GNUC__ ) - #define __ASM __asm /*!< asm keyword for GNU Compiler */ - #define __INLINE inline /*!< inline keyword for GNU Compiler */ - #define __STATIC_INLINE static inline - -#elif defined ( __ICCARM__ ) - #define __ASM __asm /*!< asm keyword for IAR Compiler */ - #define __INLINE inline /*!< inline keyword for IAR Compiler. Only available in High optimization mode! */ - #define __STATIC_INLINE static inline - -#elif defined ( __TMS470__ ) - #define __ASM __asm /*!< asm keyword for TI CCS Compiler */ - #define __STATIC_INLINE static inline - -#elif defined ( __TASKING__ ) - #define __ASM __asm /*!< asm keyword for TASKING Compiler */ - #define __INLINE inline /*!< inline keyword for TASKING Compiler */ - #define __STATIC_INLINE static inline - -#elif defined ( __CSMC__ ) - #define __packed - #define __ASM _asm /*!< asm keyword for COSMIC Compiler */ - #define __INLINE inline /*!< inline keyword for COSMIC Compiler. Use -pc99 on compile line */ - #define __STATIC_INLINE static inline - -#else - #error Unknown compiler -#endif - -/** __FPU_USED indicates whether an FPU is used or not. - This core does not support an FPU at all -*/ -#define __FPU_USED 0U - -#if defined ( __CC_ARM ) - #if defined __TARGET_FPU_VFP - #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" - #endif - -#elif defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) - #if defined __ARM_PCS_VFP - #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" - #endif - -#elif defined ( __GNUC__ ) - #if defined (__VFP_FP__) && !defined(__SOFTFP__) - #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" - #endif - -#elif defined ( __ICCARM__ ) - #if defined __ARMVFP__ - #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" - #endif - -#elif defined ( __TMS470__ ) - #if defined __TI_VFP_SUPPORT__ - #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" - #endif - -#elif defined ( __TASKING__ ) - #if defined __FPU_VFP__ - #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" - #endif - -#elif defined ( __CSMC__ ) - #if ( __CSMC__ & 0x400U) - #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" - #endif - -#endif - -#include "core_cmInstr.h" /* Core Instruction Access */ -#include "core_cmFunc.h" /* Core Function Access */ - -#ifdef __cplusplus -} -#endif - -#endif /* __CORE_CM0_H_GENERIC */ - -#ifndef __CMSIS_GENERIC - -#ifndef __CORE_CM0_H_DEPENDANT -#define __CORE_CM0_H_DEPENDANT - -#ifdef __cplusplus - extern "C" { -#endif - -/* check device defines and use defaults */ -#if defined __CHECK_DEVICE_DEFINES - #ifndef __CM0_REV - #define __CM0_REV 0x0000U - #warning "__CM0_REV not defined in device header file; using default!" - #endif - - #ifndef __NVIC_PRIO_BITS - #define __NVIC_PRIO_BITS 2U - #warning "__NVIC_PRIO_BITS not defined in device header file; using default!" - #endif - - #ifndef __Vendor_SysTickConfig - #define __Vendor_SysTickConfig 0U - #warning "__Vendor_SysTickConfig not defined in device header file; using default!" - #endif -#endif - -/* IO definitions (access restrictions to peripheral registers) */ -/** - \defgroup CMSIS_glob_defs CMSIS Global Defines - - IO Type Qualifiers are used - \li to specify the access to peripheral variables. - \li for automatic generation of peripheral register debug information. -*/ -#ifdef __cplusplus - #define __I volatile /*!< Defines 'read only' permissions */ -#else - #define __I volatile const /*!< Defines 'read only' permissions */ -#endif -#define __O volatile /*!< Defines 'write only' permissions */ -#define __IO volatile /*!< Defines 'read / write' permissions */ - -/* following defines should be used for structure members */ -#define __IM volatile const /*! Defines 'read only' structure member permissions */ -#define __OM volatile /*! Defines 'write only' structure member permissions */ -#define __IOM volatile /*! Defines 'read / write' structure member permissions */ - -/*@} end of group Cortex_M0 */ - - - -/******************************************************************************* - * Register Abstraction - Core Register contain: - - Core Register - - Core NVIC Register - - Core SCB Register - - Core SysTick Register - ******************************************************************************/ -/** - \defgroup CMSIS_core_register Defines and Type Definitions - \brief Type definitions and defines for Cortex-M processor based devices. -*/ - -/** - \ingroup CMSIS_core_register - \defgroup CMSIS_CORE Status and Control Registers - \brief Core Register type definitions. - @{ - */ - -/** - \brief Union type to access the Application Program Status Register (APSR). - */ -typedef union -{ - struct - { - uint32_t _reserved0:28; /*!< bit: 0..27 Reserved */ - uint32_t V:1; /*!< bit: 28 Overflow condition code flag */ - uint32_t C:1; /*!< bit: 29 Carry condition code flag */ - uint32_t Z:1; /*!< bit: 30 Zero condition code flag */ - uint32_t N:1; /*!< bit: 31 Negative condition code flag */ - } b; /*!< Structure used for bit access */ - uint32_t w; /*!< Type used for word access */ -} APSR_Type; - -/* APSR Register Definitions */ -#define APSR_N_Pos 31U /*!< APSR: N Position */ -#define APSR_N_Msk (1UL << APSR_N_Pos) /*!< APSR: N Mask */ - -#define APSR_Z_Pos 30U /*!< APSR: Z Position */ -#define APSR_Z_Msk (1UL << APSR_Z_Pos) /*!< APSR: Z Mask */ - -#define APSR_C_Pos 29U /*!< APSR: C Position */ -#define APSR_C_Msk (1UL << APSR_C_Pos) /*!< APSR: C Mask */ - -#define APSR_V_Pos 28U /*!< APSR: V Position */ -#define APSR_V_Msk (1UL << APSR_V_Pos) /*!< APSR: V Mask */ - - -/** - \brief Union type to access the Interrupt Program Status Register (IPSR). - */ -typedef union -{ - struct - { - uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */ - uint32_t _reserved0:23; /*!< bit: 9..31 Reserved */ - } b; /*!< Structure used for bit access */ - uint32_t w; /*!< Type used for word access */ -} IPSR_Type; - -/* IPSR Register Definitions */ -#define IPSR_ISR_Pos 0U /*!< IPSR: ISR Position */ -#define IPSR_ISR_Msk (0x1FFUL /*<< IPSR_ISR_Pos*/) /*!< IPSR: ISR Mask */ - - -/** - \brief Union type to access the Special-Purpose Program Status Registers (xPSR). - */ -typedef union -{ - struct - { - uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */ - uint32_t _reserved0:15; /*!< bit: 9..23 Reserved */ - uint32_t T:1; /*!< bit: 24 Thumb bit (read 0) */ - uint32_t _reserved1:3; /*!< bit: 25..27 Reserved */ - uint32_t V:1; /*!< bit: 28 Overflow condition code flag */ - uint32_t C:1; /*!< bit: 29 Carry condition code flag */ - uint32_t Z:1; /*!< bit: 30 Zero condition code flag */ - uint32_t N:1; /*!< bit: 31 Negative condition code flag */ - } b; /*!< Structure used for bit access */ - uint32_t w; /*!< Type used for word access */ -} xPSR_Type; - -/* xPSR Register Definitions */ -#define xPSR_N_Pos 31U /*!< xPSR: N Position */ -#define xPSR_N_Msk (1UL << xPSR_N_Pos) /*!< xPSR: N Mask */ - -#define xPSR_Z_Pos 30U /*!< xPSR: Z Position */ -#define xPSR_Z_Msk (1UL << xPSR_Z_Pos) /*!< xPSR: Z Mask */ - -#define xPSR_C_Pos 29U /*!< xPSR: C Position */ -#define xPSR_C_Msk (1UL << xPSR_C_Pos) /*!< xPSR: C Mask */ - -#define xPSR_V_Pos 28U /*!< xPSR: V Position */ -#define xPSR_V_Msk (1UL << xPSR_V_Pos) /*!< xPSR: V Mask */ - -#define xPSR_T_Pos 24U /*!< xPSR: T Position */ -#define xPSR_T_Msk (1UL << xPSR_T_Pos) /*!< xPSR: T Mask */ - -#define xPSR_ISR_Pos 0U /*!< xPSR: ISR Position */ -#define xPSR_ISR_Msk (0x1FFUL /*<< xPSR_ISR_Pos*/) /*!< xPSR: ISR Mask */ - - -/** - \brief Union type to access the Control Registers (CONTROL). - */ -typedef union -{ - struct - { - uint32_t _reserved0:1; /*!< bit: 0 Reserved */ - uint32_t SPSEL:1; /*!< bit: 1 Stack to be used */ - uint32_t _reserved1:30; /*!< bit: 2..31 Reserved */ - } b; /*!< Structure used for bit access */ - uint32_t w; /*!< Type used for word access */ -} CONTROL_Type; - -/* CONTROL Register Definitions */ -#define CONTROL_SPSEL_Pos 1U /*!< CONTROL: SPSEL Position */ -#define CONTROL_SPSEL_Msk (1UL << CONTROL_SPSEL_Pos) /*!< CONTROL: SPSEL Mask */ - -/*@} end of group CMSIS_CORE */ - - -/** - \ingroup CMSIS_core_register - \defgroup CMSIS_NVIC Nested Vectored Interrupt Controller (NVIC) - \brief Type definitions for the NVIC Registers - @{ - */ - -/** - \brief Structure type to access the Nested Vectored Interrupt Controller (NVIC). - */ -typedef struct -{ - __IOM uint32_t ISER[1U]; /*!< Offset: 0x000 (R/W) Interrupt Set Enable Register */ - uint32_t RESERVED0[31U]; - __IOM uint32_t ICER[1U]; /*!< Offset: 0x080 (R/W) Interrupt Clear Enable Register */ - uint32_t RSERVED1[31U]; - __IOM uint32_t ISPR[1U]; /*!< Offset: 0x100 (R/W) Interrupt Set Pending Register */ - uint32_t RESERVED2[31U]; - __IOM uint32_t ICPR[1U]; /*!< Offset: 0x180 (R/W) Interrupt Clear Pending Register */ - uint32_t RESERVED3[31U]; - uint32_t RESERVED4[64U]; - __IOM uint32_t IP[8U]; /*!< Offset: 0x300 (R/W) Interrupt Priority Register */ -} NVIC_Type; - -/*@} end of group CMSIS_NVIC */ - - -/** - \ingroup CMSIS_core_register - \defgroup CMSIS_SCB System Control Block (SCB) - \brief Type definitions for the System Control Block Registers - @{ - */ - -/** - \brief Structure type to access the System Control Block (SCB). - */ -typedef struct -{ - __IM uint32_t CPUID; /*!< Offset: 0x000 (R/ ) CPUID Base Register */ - __IOM uint32_t ICSR; /*!< Offset: 0x004 (R/W) Interrupt Control and State Register */ - uint32_t RESERVED0; - __IOM uint32_t AIRCR; /*!< Offset: 0x00C (R/W) Application Interrupt and Reset Control Register */ - __IOM uint32_t SCR; /*!< Offset: 0x010 (R/W) System Control Register */ - __IOM uint32_t CCR; /*!< Offset: 0x014 (R/W) Configuration Control Register */ - uint32_t RESERVED1; - __IOM uint32_t SHP[2U]; /*!< Offset: 0x01C (R/W) System Handlers Priority Registers. [0] is RESERVED */ - __IOM uint32_t SHCSR; /*!< Offset: 0x024 (R/W) System Handler Control and State Register */ -} SCB_Type; - -/* SCB CPUID Register Definitions */ -#define SCB_CPUID_IMPLEMENTER_Pos 24U /*!< SCB CPUID: IMPLEMENTER Position */ -#define SCB_CPUID_IMPLEMENTER_Msk (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos) /*!< SCB CPUID: IMPLEMENTER Mask */ - -#define SCB_CPUID_VARIANT_Pos 20U /*!< SCB CPUID: VARIANT Position */ -#define SCB_CPUID_VARIANT_Msk (0xFUL << SCB_CPUID_VARIANT_Pos) /*!< SCB CPUID: VARIANT Mask */ - -#define SCB_CPUID_ARCHITECTURE_Pos 16U /*!< SCB CPUID: ARCHITECTURE Position */ -#define SCB_CPUID_ARCHITECTURE_Msk (0xFUL << SCB_CPUID_ARCHITECTURE_Pos) /*!< SCB CPUID: ARCHITECTURE Mask */ - -#define SCB_CPUID_PARTNO_Pos 4U /*!< SCB CPUID: PARTNO Position */ -#define SCB_CPUID_PARTNO_Msk (0xFFFUL << SCB_CPUID_PARTNO_Pos) /*!< SCB CPUID: PARTNO Mask */ - -#define SCB_CPUID_REVISION_Pos 0U /*!< SCB CPUID: REVISION Position */ -#define SCB_CPUID_REVISION_Msk (0xFUL /*<< SCB_CPUID_REVISION_Pos*/) /*!< SCB CPUID: REVISION Mask */ - -/* SCB Interrupt Control State Register Definitions */ -#define SCB_ICSR_NMIPENDSET_Pos 31U /*!< SCB ICSR: NMIPENDSET Position */ -#define SCB_ICSR_NMIPENDSET_Msk (1UL << SCB_ICSR_NMIPENDSET_Pos) /*!< SCB ICSR: NMIPENDSET Mask */ - -#define SCB_ICSR_PENDSVSET_Pos 28U /*!< SCB ICSR: PENDSVSET Position */ -#define SCB_ICSR_PENDSVSET_Msk (1UL << SCB_ICSR_PENDSVSET_Pos) /*!< SCB ICSR: PENDSVSET Mask */ - -#define SCB_ICSR_PENDSVCLR_Pos 27U /*!< SCB ICSR: PENDSVCLR Position */ -#define SCB_ICSR_PENDSVCLR_Msk (1UL << SCB_ICSR_PENDSVCLR_Pos) /*!< SCB ICSR: PENDSVCLR Mask */ - -#define SCB_ICSR_PENDSTSET_Pos 26U /*!< SCB ICSR: PENDSTSET Position */ -#define SCB_ICSR_PENDSTSET_Msk (1UL << SCB_ICSR_PENDSTSET_Pos) /*!< SCB ICSR: PENDSTSET Mask */ - -#define SCB_ICSR_PENDSTCLR_Pos 25U /*!< SCB ICSR: PENDSTCLR Position */ -#define SCB_ICSR_PENDSTCLR_Msk (1UL << SCB_ICSR_PENDSTCLR_Pos) /*!< SCB ICSR: PENDSTCLR Mask */ - -#define SCB_ICSR_ISRPREEMPT_Pos 23U /*!< SCB ICSR: ISRPREEMPT Position */ -#define SCB_ICSR_ISRPREEMPT_Msk (1UL << SCB_ICSR_ISRPREEMPT_Pos) /*!< SCB ICSR: ISRPREEMPT Mask */ - -#define SCB_ICSR_ISRPENDING_Pos 22U /*!< SCB ICSR: ISRPENDING Position */ -#define SCB_ICSR_ISRPENDING_Msk (1UL << SCB_ICSR_ISRPENDING_Pos) /*!< SCB ICSR: ISRPENDING Mask */ - -#define SCB_ICSR_VECTPENDING_Pos 12U /*!< SCB ICSR: VECTPENDING Position */ -#define SCB_ICSR_VECTPENDING_Msk (0x1FFUL << SCB_ICSR_VECTPENDING_Pos) /*!< SCB ICSR: VECTPENDING Mask */ - -#define SCB_ICSR_VECTACTIVE_Pos 0U /*!< SCB ICSR: VECTACTIVE Position */ -#define SCB_ICSR_VECTACTIVE_Msk (0x1FFUL /*<< SCB_ICSR_VECTACTIVE_Pos*/) /*!< SCB ICSR: VECTACTIVE Mask */ - -/* SCB Application Interrupt and Reset Control Register Definitions */ -#define SCB_AIRCR_VECTKEY_Pos 16U /*!< SCB AIRCR: VECTKEY Position */ -#define SCB_AIRCR_VECTKEY_Msk (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos) /*!< SCB AIRCR: VECTKEY Mask */ - -#define SCB_AIRCR_VECTKEYSTAT_Pos 16U /*!< SCB AIRCR: VECTKEYSTAT Position */ -#define SCB_AIRCR_VECTKEYSTAT_Msk (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos) /*!< SCB AIRCR: VECTKEYSTAT Mask */ - -#define SCB_AIRCR_ENDIANESS_Pos 15U /*!< SCB AIRCR: ENDIANESS Position */ -#define SCB_AIRCR_ENDIANESS_Msk (1UL << SCB_AIRCR_ENDIANESS_Pos) /*!< SCB AIRCR: ENDIANESS Mask */ - -#define SCB_AIRCR_SYSRESETREQ_Pos 2U /*!< SCB AIRCR: SYSRESETREQ Position */ -#define SCB_AIRCR_SYSRESETREQ_Msk (1UL << SCB_AIRCR_SYSRESETREQ_Pos) /*!< SCB AIRCR: SYSRESETREQ Mask */ - -#define SCB_AIRCR_VECTCLRACTIVE_Pos 1U /*!< SCB AIRCR: VECTCLRACTIVE Position */ -#define SCB_AIRCR_VECTCLRACTIVE_Msk (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos) /*!< SCB AIRCR: VECTCLRACTIVE Mask */ - -/* SCB System Control Register Definitions */ -#define SCB_SCR_SEVONPEND_Pos 4U /*!< SCB SCR: SEVONPEND Position */ -#define SCB_SCR_SEVONPEND_Msk (1UL << SCB_SCR_SEVONPEND_Pos) /*!< SCB SCR: SEVONPEND Mask */ - -#define SCB_SCR_SLEEPDEEP_Pos 2U /*!< SCB SCR: SLEEPDEEP Position */ -#define SCB_SCR_SLEEPDEEP_Msk (1UL << SCB_SCR_SLEEPDEEP_Pos) /*!< SCB SCR: SLEEPDEEP Mask */ - -#define SCB_SCR_SLEEPONEXIT_Pos 1U /*!< SCB SCR: SLEEPONEXIT Position */ -#define SCB_SCR_SLEEPONEXIT_Msk (1UL << SCB_SCR_SLEEPONEXIT_Pos) /*!< SCB SCR: SLEEPONEXIT Mask */ - -/* SCB Configuration Control Register Definitions */ -#define SCB_CCR_STKALIGN_Pos 9U /*!< SCB CCR: STKALIGN Position */ -#define SCB_CCR_STKALIGN_Msk (1UL << SCB_CCR_STKALIGN_Pos) /*!< SCB CCR: STKALIGN Mask */ - -#define SCB_CCR_UNALIGN_TRP_Pos 3U /*!< SCB CCR: UNALIGN_TRP Position */ -#define SCB_CCR_UNALIGN_TRP_Msk (1UL << SCB_CCR_UNALIGN_TRP_Pos) /*!< SCB CCR: UNALIGN_TRP Mask */ - -/* SCB System Handler Control and State Register Definitions */ -#define SCB_SHCSR_SVCALLPENDED_Pos 15U /*!< SCB SHCSR: SVCALLPENDED Position */ -#define SCB_SHCSR_SVCALLPENDED_Msk (1UL << SCB_SHCSR_SVCALLPENDED_Pos) /*!< SCB SHCSR: SVCALLPENDED Mask */ - -/*@} end of group CMSIS_SCB */ - - -/** - \ingroup CMSIS_core_register - \defgroup CMSIS_SysTick System Tick Timer (SysTick) - \brief Type definitions for the System Timer Registers. - @{ - */ - -/** - \brief Structure type to access the System Timer (SysTick). - */ -typedef struct -{ - __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) SysTick Control and Status Register */ - __IOM uint32_t LOAD; /*!< Offset: 0x004 (R/W) SysTick Reload Value Register */ - __IOM uint32_t VAL; /*!< Offset: 0x008 (R/W) SysTick Current Value Register */ - __IM uint32_t CALIB; /*!< Offset: 0x00C (R/ ) SysTick Calibration Register */ -} SysTick_Type; - -/* SysTick Control / Status Register Definitions */ -#define SysTick_CTRL_COUNTFLAG_Pos 16U /*!< SysTick CTRL: COUNTFLAG Position */ -#define SysTick_CTRL_COUNTFLAG_Msk (1UL << SysTick_CTRL_COUNTFLAG_Pos) /*!< SysTick CTRL: COUNTFLAG Mask */ - -#define SysTick_CTRL_CLKSOURCE_Pos 2U /*!< SysTick CTRL: CLKSOURCE Position */ -#define SysTick_CTRL_CLKSOURCE_Msk (1UL << SysTick_CTRL_CLKSOURCE_Pos) /*!< SysTick CTRL: CLKSOURCE Mask */ - -#define SysTick_CTRL_TICKINT_Pos 1U /*!< SysTick CTRL: TICKINT Position */ -#define SysTick_CTRL_TICKINT_Msk (1UL << SysTick_CTRL_TICKINT_Pos) /*!< SysTick CTRL: TICKINT Mask */ - -#define SysTick_CTRL_ENABLE_Pos 0U /*!< SysTick CTRL: ENABLE Position */ -#define SysTick_CTRL_ENABLE_Msk (1UL /*<< SysTick_CTRL_ENABLE_Pos*/) /*!< SysTick CTRL: ENABLE Mask */ - -/* SysTick Reload Register Definitions */ -#define SysTick_LOAD_RELOAD_Pos 0U /*!< SysTick LOAD: RELOAD Position */ -#define SysTick_LOAD_RELOAD_Msk (0xFFFFFFUL /*<< SysTick_LOAD_RELOAD_Pos*/) /*!< SysTick LOAD: RELOAD Mask */ - -/* SysTick Current Register Definitions */ -#define SysTick_VAL_CURRENT_Pos 0U /*!< SysTick VAL: CURRENT Position */ -#define SysTick_VAL_CURRENT_Msk (0xFFFFFFUL /*<< SysTick_VAL_CURRENT_Pos*/) /*!< SysTick VAL: CURRENT Mask */ - -/* SysTick Calibration Register Definitions */ -#define SysTick_CALIB_NOREF_Pos 31U /*!< SysTick CALIB: NOREF Position */ -#define SysTick_CALIB_NOREF_Msk (1UL << SysTick_CALIB_NOREF_Pos) /*!< SysTick CALIB: NOREF Mask */ - -#define SysTick_CALIB_SKEW_Pos 30U /*!< SysTick CALIB: SKEW Position */ -#define SysTick_CALIB_SKEW_Msk (1UL << SysTick_CALIB_SKEW_Pos) /*!< SysTick CALIB: SKEW Mask */ - -#define SysTick_CALIB_TENMS_Pos 0U /*!< SysTick CALIB: TENMS Position */ -#define SysTick_CALIB_TENMS_Msk (0xFFFFFFUL /*<< SysTick_CALIB_TENMS_Pos*/) /*!< SysTick CALIB: TENMS Mask */ - -/*@} end of group CMSIS_SysTick */ - - -/** - \ingroup CMSIS_core_register - \defgroup CMSIS_CoreDebug Core Debug Registers (CoreDebug) - \brief Cortex-M0 Core Debug Registers (DCB registers, SHCSR, and DFSR) are only accessible over DAP and not via processor. - Therefore they are not covered by the Cortex-M0 header file. - @{ - */ -/*@} end of group CMSIS_CoreDebug */ - - -/** - \ingroup CMSIS_core_register - \defgroup CMSIS_core_bitfield Core register bit field macros - \brief Macros for use with bit field definitions (xxx_Pos, xxx_Msk). - @{ - */ - -/** - \brief Mask and shift a bit field value for use in a register bit range. - \param[in] field Name of the register bit field. - \param[in] value Value of the bit field. - \return Masked and shifted value. -*/ -#define _VAL2FLD(field, value) ((value << field ## _Pos) & field ## _Msk) - -/** - \brief Mask and shift a register value to extract a bit filed value. - \param[in] field Name of the register bit field. - \param[in] value Value of register. - \return Masked and shifted bit field value. -*/ -#define _FLD2VAL(field, value) ((value & field ## _Msk) >> field ## _Pos) - -/*@} end of group CMSIS_core_bitfield */ - - -/** - \ingroup CMSIS_core_register - \defgroup CMSIS_core_base Core Definitions - \brief Definitions for base addresses, unions, and structures. - @{ - */ - -/* Memory mapping of Cortex-M0 Hardware */ -#define SCS_BASE (0xE000E000UL) /*!< System Control Space Base Address */ -#define SysTick_BASE (SCS_BASE + 0x0010UL) /*!< SysTick Base Address */ -#define NVIC_BASE (SCS_BASE + 0x0100UL) /*!< NVIC Base Address */ -#define SCB_BASE (SCS_BASE + 0x0D00UL) /*!< System Control Block Base Address */ - -#define SCB ((SCB_Type *) SCB_BASE ) /*!< SCB configuration struct */ -#define SysTick ((SysTick_Type *) SysTick_BASE ) /*!< SysTick configuration struct */ -#define NVIC ((NVIC_Type *) NVIC_BASE ) /*!< NVIC configuration struct */ - - -/*@} */ - - - -/******************************************************************************* - * Hardware Abstraction Layer - Core Function Interface contains: - - Core NVIC Functions - - Core SysTick Functions - - Core Register Access Functions - ******************************************************************************/ -/** - \defgroup CMSIS_Core_FunctionInterface Functions and Instructions Reference -*/ - - - -/* ########################## NVIC functions #################################### */ -/** - \ingroup CMSIS_Core_FunctionInterface - \defgroup CMSIS_Core_NVICFunctions NVIC Functions - \brief Functions that manage interrupts and exceptions via the NVIC. - @{ - */ - -/* Interrupt Priorities are WORD accessible only under ARMv6M */ -/* The following MACROS handle generation of the register offset and byte masks */ -#define _BIT_SHIFT(IRQn) ( ((((uint32_t)(int32_t)(IRQn)) ) & 0x03UL) * 8UL) -#define _SHP_IDX(IRQn) ( (((((uint32_t)(int32_t)(IRQn)) & 0x0FUL)-8UL) >> 2UL) ) -#define _IP_IDX(IRQn) ( (((uint32_t)(int32_t)(IRQn)) >> 2UL) ) - - -/** - \brief Enable External Interrupt - \details Enables a device-specific interrupt in the NVIC interrupt controller. - \param [in] IRQn External interrupt number. Value cannot be negative. - */ -__STATIC_INLINE void NVIC_EnableIRQ(IRQn_Type IRQn) -{ - NVIC->ISER[0U] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL)); -} - - -/** - \brief Disable External Interrupt - \details Disables a device-specific interrupt in the NVIC interrupt controller. - \param [in] IRQn External interrupt number. Value cannot be negative. - */ -__STATIC_INLINE void NVIC_DisableIRQ(IRQn_Type IRQn) -{ - NVIC->ICER[0U] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL)); -} - - -/** - \brief Get Pending Interrupt - \details Reads the pending register in the NVIC and returns the pending bit for the specified interrupt. - \param [in] IRQn Interrupt number. - \return 0 Interrupt status is not pending. - \return 1 Interrupt status is pending. - */ -__STATIC_INLINE uint32_t NVIC_GetPendingIRQ(IRQn_Type IRQn) -{ - return((uint32_t)(((NVIC->ISPR[0U] & (1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); -} - - -/** - \brief Set Pending Interrupt - \details Sets the pending bit of an external interrupt. - \param [in] IRQn Interrupt number. Value cannot be negative. - */ -__STATIC_INLINE void NVIC_SetPendingIRQ(IRQn_Type IRQn) -{ - NVIC->ISPR[0U] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL)); -} - - -/** - \brief Clear Pending Interrupt - \details Clears the pending bit of an external interrupt. - \param [in] IRQn External interrupt number. Value cannot be negative. - */ -__STATIC_INLINE void NVIC_ClearPendingIRQ(IRQn_Type IRQn) -{ - NVIC->ICPR[0U] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL)); -} - - -/** - \brief Set Interrupt Priority - \details Sets the priority of an interrupt. - \note The priority cannot be set for every core interrupt. - \param [in] IRQn Interrupt number. - \param [in] priority Priority to set. - */ -__STATIC_INLINE void NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority) -{ - if ((int32_t)(IRQn) < 0) - { - SCB->SHP[_SHP_IDX(IRQn)] = ((uint32_t)(SCB->SHP[_SHP_IDX(IRQn)] & ~(0xFFUL << _BIT_SHIFT(IRQn))) | - (((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL) << _BIT_SHIFT(IRQn))); - } - else - { - NVIC->IP[_IP_IDX(IRQn)] = ((uint32_t)(NVIC->IP[_IP_IDX(IRQn)] & ~(0xFFUL << _BIT_SHIFT(IRQn))) | - (((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL) << _BIT_SHIFT(IRQn))); - } -} - - -/** - \brief Get Interrupt Priority - \details Reads the priority of an interrupt. - The interrupt number can be positive to specify an external (device specific) interrupt, - or negative to specify an internal (core) interrupt. - \param [in] IRQn Interrupt number. - \return Interrupt Priority. - Value is aligned automatically to the implemented priority bits of the microcontroller. - */ -__STATIC_INLINE uint32_t NVIC_GetPriority(IRQn_Type IRQn) -{ - - if ((int32_t)(IRQn) < 0) - { - return((uint32_t)(((SCB->SHP[_SHP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) & (uint32_t)0xFFUL) >> (8U - __NVIC_PRIO_BITS))); - } - else - { - return((uint32_t)(((NVIC->IP[ _IP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) & (uint32_t)0xFFUL) >> (8U - __NVIC_PRIO_BITS))); - } -} - - -/** - \brief System Reset - \details Initiates a system reset request to reset the MCU. - */ -__STATIC_INLINE void NVIC_SystemReset(void) -{ - __DSB(); /* Ensure all outstanding memory accesses included - buffered write are completed before reset */ - SCB->AIRCR = ((0x5FAUL << SCB_AIRCR_VECTKEY_Pos) | - SCB_AIRCR_SYSRESETREQ_Msk); - __DSB(); /* Ensure completion of memory access */ - - for(;;) /* wait until reset */ - { - __NOP(); - } -} - -/*@} end of CMSIS_Core_NVICFunctions */ - - - -/* ################################## SysTick function ############################################ */ -/** - \ingroup CMSIS_Core_FunctionInterface - \defgroup CMSIS_Core_SysTickFunctions SysTick Functions - \brief Functions that configure the System. - @{ - */ - -#if (__Vendor_SysTickConfig == 0U) - -/** - \brief System Tick Configuration - \details Initializes the System Timer and its interrupt, and starts the System Tick Timer. - Counter is in free running mode to generate periodic interrupts. - \param [in] ticks Number of ticks between two interrupts. - \return 0 Function succeeded. - \return 1 Function failed. - \note When the variable __Vendor_SysTickConfig is set to 1, then the - function SysTick_Config is not included. In this case, the file device.h - must contain a vendor-specific implementation of this function. - */ -__STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks) -{ - if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk) - { - return (1UL); /* Reload value impossible */ - } - - SysTick->LOAD = (uint32_t)(ticks - 1UL); /* set reload register */ - NVIC_SetPriority (SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */ - SysTick->VAL = 0UL; /* Load the SysTick Counter Value */ - SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk | - SysTick_CTRL_TICKINT_Msk | - SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */ - return (0UL); /* Function successful */ -} - -#endif - -/*@} end of CMSIS_Core_SysTickFunctions */ - - - - -#ifdef __cplusplus -} -#endif - -#endif /* __CORE_CM0_H_DEPENDANT */ - -#endif /* __CMSIS_GENERIC */ diff --git a/bsp/essemi/es32f0334/libraries/CMSIS/Include/core_cm0plus.h b/bsp/essemi/es32f0334/libraries/CMSIS/Include/core_cm0plus.h deleted file mode 100644 index b04aa39053..0000000000 --- a/bsp/essemi/es32f0334/libraries/CMSIS/Include/core_cm0plus.h +++ /dev/null @@ -1,914 +0,0 @@ -/**************************************************************************//** - * @file core_cm0plus.h - * @brief CMSIS Cortex-M0+ Core Peripheral Access Layer Header File - * @version V4.30 - * @date 20. October 2015 - ******************************************************************************/ -/* Copyright (c) 2009 - 2015 ARM LIMITED - - All rights reserved. - Redistribution and use in source and binary forms, with or without - modification, are permitted provided that the following conditions are met: - - Redistributions of source code must retain the above copyright - notice, this list of conditions and the following disclaimer. - - Redistributions in binary form must reproduce the above copyright - notice, this list of conditions and the following disclaimer in the - documentation and/or other materials provided with the distribution. - - Neither the name of ARM nor the names of its contributors may be used - to endorse or promote products derived from this software without - specific prior written permission. - * - THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" - AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE - ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE - LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR - CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF - SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS - INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN - CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) - ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE - POSSIBILITY OF SUCH DAMAGE. - ---------------------------------------------------------------------------*/ - - -#if defined ( __ICCARM__ ) - #pragma system_include /* treat file as system include file for MISRA check */ -#elif defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) - #pragma clang system_header /* treat file as system include file */ -#endif - -#ifndef __CORE_CM0PLUS_H_GENERIC -#define __CORE_CM0PLUS_H_GENERIC - -#include - -#ifdef __cplusplus - extern "C" { -#endif - -/** - \page CMSIS_MISRA_Exceptions MISRA-C:2004 Compliance Exceptions - CMSIS violates the following MISRA-C:2004 rules: - - \li Required Rule 8.5, object/function definition in header file.
- Function definitions in header files are used to allow 'inlining'. - - \li Required Rule 18.4, declaration of union type or object of union type: '{...}'.
- Unions are used for effective representation of core registers. - - \li Advisory Rule 19.7, Function-like macro defined.
- Function-like macros are used to allow more efficient code. - */ - - -/******************************************************************************* - * CMSIS definitions - ******************************************************************************/ -/** - \ingroup Cortex-M0+ - @{ - */ - -/* CMSIS CM0+ definitions */ -#define __CM0PLUS_CMSIS_VERSION_MAIN (0x04U) /*!< [31:16] CMSIS HAL main version */ -#define __CM0PLUS_CMSIS_VERSION_SUB (0x1EU) /*!< [15:0] CMSIS HAL sub version */ -#define __CM0PLUS_CMSIS_VERSION ((__CM0PLUS_CMSIS_VERSION_MAIN << 16U) | \ - __CM0PLUS_CMSIS_VERSION_SUB ) /*!< CMSIS HAL version number */ - -#define __CORTEX_M (0x00U) /*!< Cortex-M Core */ - - -#if defined ( __CC_ARM ) - #define __ASM __asm /*!< asm keyword for ARM Compiler */ - #define __INLINE __inline /*!< inline keyword for ARM Compiler */ - #define __STATIC_INLINE static __inline - -#elif defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) - #define __ASM __asm /*!< asm keyword for ARM Compiler */ - #define __INLINE __inline /*!< inline keyword for ARM Compiler */ - #define __STATIC_INLINE static __inline - -#elif defined ( __GNUC__ ) - #define __ASM __asm /*!< asm keyword for GNU Compiler */ - #define __INLINE inline /*!< inline keyword for GNU Compiler */ - #define __STATIC_INLINE static inline - -#elif defined ( __ICCARM__ ) - #define __ASM __asm /*!< asm keyword for IAR Compiler */ - #define __INLINE inline /*!< inline keyword for IAR Compiler. Only available in High optimization mode! */ - #define __STATIC_INLINE static inline - -#elif defined ( __TMS470__ ) - #define __ASM __asm /*!< asm keyword for TI CCS Compiler */ - #define __STATIC_INLINE static inline - -#elif defined ( __TASKING__ ) - #define __ASM __asm /*!< asm keyword for TASKING Compiler */ - #define __INLINE inline /*!< inline keyword for TASKING Compiler */ - #define __STATIC_INLINE static inline - -#elif defined ( __CSMC__ ) - #define __packed - #define __ASM _asm /*!< asm keyword for COSMIC Compiler */ - #define __INLINE inline /*!< inline keyword for COSMIC Compiler. Use -pc99 on compile line */ - #define __STATIC_INLINE static inline - -#else - #error Unknown compiler -#endif - -/** __FPU_USED indicates whether an FPU is used or not. - This core does not support an FPU at all -*/ -#define __FPU_USED 0U - -#if defined ( __CC_ARM ) - #if defined __TARGET_FPU_VFP - #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" - #endif - -#elif defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) - #if defined __ARM_PCS_VFP - #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" - #endif - -#elif defined ( __GNUC__ ) - #if defined (__VFP_FP__) && !defined(__SOFTFP__) - #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" - #endif - -#elif defined ( __ICCARM__ ) - #if defined __ARMVFP__ - #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" - #endif - -#elif defined ( __TMS470__ ) - #if defined __TI_VFP_SUPPORT__ - #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" - #endif - -#elif defined ( __TASKING__ ) - #if defined __FPU_VFP__ - #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" - #endif - -#elif defined ( __CSMC__ ) - #if ( __CSMC__ & 0x400U) - #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" - #endif - -#endif - -#include "core_cmInstr.h" /* Core Instruction Access */ -#include "core_cmFunc.h" /* Core Function Access */ - -#ifdef __cplusplus -} -#endif - -#endif /* __CORE_CM0PLUS_H_GENERIC */ - -#ifndef __CMSIS_GENERIC - -#ifndef __CORE_CM0PLUS_H_DEPENDANT -#define __CORE_CM0PLUS_H_DEPENDANT - -#ifdef __cplusplus - extern "C" { -#endif - -/* check device defines and use defaults */ -#if defined __CHECK_DEVICE_DEFINES - #ifndef __CM0PLUS_REV - #define __CM0PLUS_REV 0x0000U - #warning "__CM0PLUS_REV not defined in device header file; using default!" - #endif - - #ifndef __MPU_PRESENT - #define __MPU_PRESENT 0U - #warning "__MPU_PRESENT not defined in device header file; using default!" - #endif - - #ifndef __VTOR_PRESENT - #define __VTOR_PRESENT 0U - #warning "__VTOR_PRESENT not defined in device header file; using default!" - #endif - - #ifndef __NVIC_PRIO_BITS - #define __NVIC_PRIO_BITS 2U - #warning "__NVIC_PRIO_BITS not defined in device header file; using default!" - #endif - - #ifndef __Vendor_SysTickConfig - #define __Vendor_SysTickConfig 0U - #warning "__Vendor_SysTickConfig not defined in device header file; using default!" - #endif -#endif - -/* IO definitions (access restrictions to peripheral registers) */ -/** - \defgroup CMSIS_glob_defs CMSIS Global Defines - - IO Type Qualifiers are used - \li to specify the access to peripheral variables. - \li for automatic generation of peripheral register debug information. -*/ -#ifdef __cplusplus - #define __I volatile /*!< Defines 'read only' permissions */ -#else - #define __I volatile const /*!< Defines 'read only' permissions */ -#endif -#define __O volatile /*!< Defines 'write only' permissions */ -#define __IO volatile /*!< Defines 'read / write' permissions */ - -/* following defines should be used for structure members */ -#define __IM volatile const /*! Defines 'read only' structure member permissions */ -#define __OM volatile /*! Defines 'write only' structure member permissions */ -#define __IOM volatile /*! Defines 'read / write' structure member permissions */ - -/*@} end of group Cortex-M0+ */ - - - -/******************************************************************************* - * Register Abstraction - Core Register contain: - - Core Register - - Core NVIC Register - - Core SCB Register - - Core SysTick Register - - Core MPU Register - ******************************************************************************/ -/** - \defgroup CMSIS_core_register Defines and Type Definitions - \brief Type definitions and defines for Cortex-M processor based devices. -*/ - -/** - \ingroup CMSIS_core_register - \defgroup CMSIS_CORE Status and Control Registers - \brief Core Register type definitions. - @{ - */ - -/** - \brief Union type to access the Application Program Status Register (APSR). - */ -typedef union -{ - struct - { - uint32_t _reserved0:28; /*!< bit: 0..27 Reserved */ - uint32_t V:1; /*!< bit: 28 Overflow condition code flag */ - uint32_t C:1; /*!< bit: 29 Carry condition code flag */ - uint32_t Z:1; /*!< bit: 30 Zero condition code flag */ - uint32_t N:1; /*!< bit: 31 Negative condition code flag */ - } b; /*!< Structure used for bit access */ - uint32_t w; /*!< Type used for word access */ -} APSR_Type; - -/* APSR Register Definitions */ -#define APSR_N_Pos 31U /*!< APSR: N Position */ -#define APSR_N_Msk (1UL << APSR_N_Pos) /*!< APSR: N Mask */ - -#define APSR_Z_Pos 30U /*!< APSR: Z Position */ -#define APSR_Z_Msk (1UL << APSR_Z_Pos) /*!< APSR: Z Mask */ - -#define APSR_C_Pos 29U /*!< APSR: C Position */ -#define APSR_C_Msk (1UL << APSR_C_Pos) /*!< APSR: C Mask */ - -#define APSR_V_Pos 28U /*!< APSR: V Position */ -#define APSR_V_Msk (1UL << APSR_V_Pos) /*!< APSR: V Mask */ - - -/** - \brief Union type to access the Interrupt Program Status Register (IPSR). - */ -typedef union -{ - struct - { - uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */ - uint32_t _reserved0:23; /*!< bit: 9..31 Reserved */ - } b; /*!< Structure used for bit access */ - uint32_t w; /*!< Type used for word access */ -} IPSR_Type; - -/* IPSR Register Definitions */ -#define IPSR_ISR_Pos 0U /*!< IPSR: ISR Position */ -#define IPSR_ISR_Msk (0x1FFUL /*<< IPSR_ISR_Pos*/) /*!< IPSR: ISR Mask */ - - -/** - \brief Union type to access the Special-Purpose Program Status Registers (xPSR). - */ -typedef union -{ - struct - { - uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */ - uint32_t _reserved0:15; /*!< bit: 9..23 Reserved */ - uint32_t T:1; /*!< bit: 24 Thumb bit (read 0) */ - uint32_t _reserved1:3; /*!< bit: 25..27 Reserved */ - uint32_t V:1; /*!< bit: 28 Overflow condition code flag */ - uint32_t C:1; /*!< bit: 29 Carry condition code flag */ - uint32_t Z:1; /*!< bit: 30 Zero condition code flag */ - uint32_t N:1; /*!< bit: 31 Negative condition code flag */ - } b; /*!< Structure used for bit access */ - uint32_t w; /*!< Type used for word access */ -} xPSR_Type; - -/* xPSR Register Definitions */ -#define xPSR_N_Pos 31U /*!< xPSR: N Position */ -#define xPSR_N_Msk (1UL << xPSR_N_Pos) /*!< xPSR: N Mask */ - -#define xPSR_Z_Pos 30U /*!< xPSR: Z Position */ -#define xPSR_Z_Msk (1UL << xPSR_Z_Pos) /*!< xPSR: Z Mask */ - -#define xPSR_C_Pos 29U /*!< xPSR: C Position */ -#define xPSR_C_Msk (1UL << xPSR_C_Pos) /*!< xPSR: C Mask */ - -#define xPSR_V_Pos 28U /*!< xPSR: V Position */ -#define xPSR_V_Msk (1UL << xPSR_V_Pos) /*!< xPSR: V Mask */ - -#define xPSR_T_Pos 24U /*!< xPSR: T Position */ -#define xPSR_T_Msk (1UL << xPSR_T_Pos) /*!< xPSR: T Mask */ - -#define xPSR_ISR_Pos 0U /*!< xPSR: ISR Position */ -#define xPSR_ISR_Msk (0x1FFUL /*<< xPSR_ISR_Pos*/) /*!< xPSR: ISR Mask */ - - -/** - \brief Union type to access the Control Registers (CONTROL). - */ -typedef union -{ - struct - { - uint32_t nPRIV:1; /*!< bit: 0 Execution privilege in Thread mode */ - uint32_t SPSEL:1; /*!< bit: 1 Stack to be used */ - uint32_t _reserved1:30; /*!< bit: 2..31 Reserved */ - } b; /*!< Structure used for bit access */ - uint32_t w; /*!< Type used for word access */ -} CONTROL_Type; - -/* CONTROL Register Definitions */ -#define CONTROL_SPSEL_Pos 1U /*!< CONTROL: SPSEL Position */ -#define CONTROL_SPSEL_Msk (1UL << CONTROL_SPSEL_Pos) /*!< CONTROL: SPSEL Mask */ - -#define CONTROL_nPRIV_Pos 0U /*!< CONTROL: nPRIV Position */ -#define CONTROL_nPRIV_Msk (1UL /*<< CONTROL_nPRIV_Pos*/) /*!< CONTROL: nPRIV Mask */ - -/*@} end of group CMSIS_CORE */ - - -/** - \ingroup CMSIS_core_register - \defgroup CMSIS_NVIC Nested Vectored Interrupt Controller (NVIC) - \brief Type definitions for the NVIC Registers - @{ - */ - -/** - \brief Structure type to access the Nested Vectored Interrupt Controller (NVIC). - */ -typedef struct -{ - __IOM uint32_t ISER[1U]; /*!< Offset: 0x000 (R/W) Interrupt Set Enable Register */ - uint32_t RESERVED0[31U]; - __IOM uint32_t ICER[1U]; /*!< Offset: 0x080 (R/W) Interrupt Clear Enable Register */ - uint32_t RSERVED1[31U]; - __IOM uint32_t ISPR[1U]; /*!< Offset: 0x100 (R/W) Interrupt Set Pending Register */ - uint32_t RESERVED2[31U]; - __IOM uint32_t ICPR[1U]; /*!< Offset: 0x180 (R/W) Interrupt Clear Pending Register */ - uint32_t RESERVED3[31U]; - uint32_t RESERVED4[64U]; - __IOM uint32_t IP[8U]; /*!< Offset: 0x300 (R/W) Interrupt Priority Register */ -} NVIC_Type; - -/*@} end of group CMSIS_NVIC */ - - -/** - \ingroup CMSIS_core_register - \defgroup CMSIS_SCB System Control Block (SCB) - \brief Type definitions for the System Control Block Registers - @{ - */ - -/** - \brief Structure type to access the System Control Block (SCB). - */ -typedef struct -{ - __IM uint32_t CPUID; /*!< Offset: 0x000 (R/ ) CPUID Base Register */ - __IOM uint32_t ICSR; /*!< Offset: 0x004 (R/W) Interrupt Control and State Register */ -#if (__VTOR_PRESENT == 1U) - __IOM uint32_t VTOR; /*!< Offset: 0x008 (R/W) Vector Table Offset Register */ -#else - uint32_t RESERVED0; -#endif - __IOM uint32_t AIRCR; /*!< Offset: 0x00C (R/W) Application Interrupt and Reset Control Register */ - __IOM uint32_t SCR; /*!< Offset: 0x010 (R/W) System Control Register */ - __IOM uint32_t CCR; /*!< Offset: 0x014 (R/W) Configuration Control Register */ - uint32_t RESERVED1; - __IOM uint32_t SHP[2U]; /*!< Offset: 0x01C (R/W) System Handlers Priority Registers. [0] is RESERVED */ - __IOM uint32_t SHCSR; /*!< Offset: 0x024 (R/W) System Handler Control and State Register */ -} SCB_Type; - -/* SCB CPUID Register Definitions */ -#define SCB_CPUID_IMPLEMENTER_Pos 24U /*!< SCB CPUID: IMPLEMENTER Position */ -#define SCB_CPUID_IMPLEMENTER_Msk (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos) /*!< SCB CPUID: IMPLEMENTER Mask */ - -#define SCB_CPUID_VARIANT_Pos 20U /*!< SCB CPUID: VARIANT Position */ -#define SCB_CPUID_VARIANT_Msk (0xFUL << SCB_CPUID_VARIANT_Pos) /*!< SCB CPUID: VARIANT Mask */ - -#define SCB_CPUID_ARCHITECTURE_Pos 16U /*!< SCB CPUID: ARCHITECTURE Position */ -#define SCB_CPUID_ARCHITECTURE_Msk (0xFUL << SCB_CPUID_ARCHITECTURE_Pos) /*!< SCB CPUID: ARCHITECTURE Mask */ - -#define SCB_CPUID_PARTNO_Pos 4U /*!< SCB CPUID: PARTNO Position */ -#define SCB_CPUID_PARTNO_Msk (0xFFFUL << SCB_CPUID_PARTNO_Pos) /*!< SCB CPUID: PARTNO Mask */ - -#define SCB_CPUID_REVISION_Pos 0U /*!< SCB CPUID: REVISION Position */ -#define SCB_CPUID_REVISION_Msk (0xFUL /*<< SCB_CPUID_REVISION_Pos*/) /*!< SCB CPUID: REVISION Mask */ - -/* SCB Interrupt Control State Register Definitions */ -#define SCB_ICSR_NMIPENDSET_Pos 31U /*!< SCB ICSR: NMIPENDSET Position */ -#define SCB_ICSR_NMIPENDSET_Msk (1UL << SCB_ICSR_NMIPENDSET_Pos) /*!< SCB ICSR: NMIPENDSET Mask */ - -#define SCB_ICSR_PENDSVSET_Pos 28U /*!< SCB ICSR: PENDSVSET Position */ -#define SCB_ICSR_PENDSVSET_Msk (1UL << SCB_ICSR_PENDSVSET_Pos) /*!< SCB ICSR: PENDSVSET Mask */ - -#define SCB_ICSR_PENDSVCLR_Pos 27U /*!< SCB ICSR: PENDSVCLR Position */ -#define SCB_ICSR_PENDSVCLR_Msk (1UL << SCB_ICSR_PENDSVCLR_Pos) /*!< SCB ICSR: PENDSVCLR Mask */ - -#define SCB_ICSR_PENDSTSET_Pos 26U /*!< SCB ICSR: PENDSTSET Position */ -#define SCB_ICSR_PENDSTSET_Msk (1UL << SCB_ICSR_PENDSTSET_Pos) /*!< SCB ICSR: PENDSTSET Mask */ - -#define SCB_ICSR_PENDSTCLR_Pos 25U /*!< SCB ICSR: PENDSTCLR Position */ -#define SCB_ICSR_PENDSTCLR_Msk (1UL << SCB_ICSR_PENDSTCLR_Pos) /*!< SCB ICSR: PENDSTCLR Mask */ - -#define SCB_ICSR_ISRPREEMPT_Pos 23U /*!< SCB ICSR: ISRPREEMPT Position */ -#define SCB_ICSR_ISRPREEMPT_Msk (1UL << SCB_ICSR_ISRPREEMPT_Pos) /*!< SCB ICSR: ISRPREEMPT Mask */ - -#define SCB_ICSR_ISRPENDING_Pos 22U /*!< SCB ICSR: ISRPENDING Position */ -#define SCB_ICSR_ISRPENDING_Msk (1UL << SCB_ICSR_ISRPENDING_Pos) /*!< SCB ICSR: ISRPENDING Mask */ - -#define SCB_ICSR_VECTPENDING_Pos 12U /*!< SCB ICSR: VECTPENDING Position */ -#define SCB_ICSR_VECTPENDING_Msk (0x1FFUL << SCB_ICSR_VECTPENDING_Pos) /*!< SCB ICSR: VECTPENDING Mask */ - -#define SCB_ICSR_VECTACTIVE_Pos 0U /*!< SCB ICSR: VECTACTIVE Position */ -#define SCB_ICSR_VECTACTIVE_Msk (0x1FFUL /*<< SCB_ICSR_VECTACTIVE_Pos*/) /*!< SCB ICSR: VECTACTIVE Mask */ - -#if (__VTOR_PRESENT == 1U) -/* SCB Interrupt Control State Register Definitions */ -#define SCB_VTOR_TBLOFF_Pos 8U /*!< SCB VTOR: TBLOFF Position */ -#define SCB_VTOR_TBLOFF_Msk (0xFFFFFFUL << SCB_VTOR_TBLOFF_Pos) /*!< SCB VTOR: TBLOFF Mask */ -#endif - -/* SCB Application Interrupt and Reset Control Register Definitions */ -#define SCB_AIRCR_VECTKEY_Pos 16U /*!< SCB AIRCR: VECTKEY Position */ -#define SCB_AIRCR_VECTKEY_Msk (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos) /*!< SCB AIRCR: VECTKEY Mask */ - -#define SCB_AIRCR_VECTKEYSTAT_Pos 16U /*!< SCB AIRCR: VECTKEYSTAT Position */ -#define SCB_AIRCR_VECTKEYSTAT_Msk (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos) /*!< SCB AIRCR: VECTKEYSTAT Mask */ - -#define SCB_AIRCR_ENDIANESS_Pos 15U /*!< SCB AIRCR: ENDIANESS Position */ -#define SCB_AIRCR_ENDIANESS_Msk (1UL << SCB_AIRCR_ENDIANESS_Pos) /*!< SCB AIRCR: ENDIANESS Mask */ - -#define SCB_AIRCR_SYSRESETREQ_Pos 2U /*!< SCB AIRCR: SYSRESETREQ Position */ -#define SCB_AIRCR_SYSRESETREQ_Msk (1UL << SCB_AIRCR_SYSRESETREQ_Pos) /*!< SCB AIRCR: SYSRESETREQ Mask */ - -#define SCB_AIRCR_VECTCLRACTIVE_Pos 1U /*!< SCB AIRCR: VECTCLRACTIVE Position */ -#define SCB_AIRCR_VECTCLRACTIVE_Msk (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos) /*!< SCB AIRCR: VECTCLRACTIVE Mask */ - -/* SCB System Control Register Definitions */ -#define SCB_SCR_SEVONPEND_Pos 4U /*!< SCB SCR: SEVONPEND Position */ -#define SCB_SCR_SEVONPEND_Msk (1UL << SCB_SCR_SEVONPEND_Pos) /*!< SCB SCR: SEVONPEND Mask */ - -#define SCB_SCR_SLEEPDEEP_Pos 2U /*!< SCB SCR: SLEEPDEEP Position */ -#define SCB_SCR_SLEEPDEEP_Msk (1UL << SCB_SCR_SLEEPDEEP_Pos) /*!< SCB SCR: SLEEPDEEP Mask */ - -#define SCB_SCR_SLEEPONEXIT_Pos 1U /*!< SCB SCR: SLEEPONEXIT Position */ -#define SCB_SCR_SLEEPONEXIT_Msk (1UL << SCB_SCR_SLEEPONEXIT_Pos) /*!< SCB SCR: SLEEPONEXIT Mask */ - -/* SCB Configuration Control Register Definitions */ -#define SCB_CCR_STKALIGN_Pos 9U /*!< SCB CCR: STKALIGN Position */ -#define SCB_CCR_STKALIGN_Msk (1UL << SCB_CCR_STKALIGN_Pos) /*!< SCB CCR: STKALIGN Mask */ - -#define SCB_CCR_UNALIGN_TRP_Pos 3U /*!< SCB CCR: UNALIGN_TRP Position */ -#define SCB_CCR_UNALIGN_TRP_Msk (1UL << SCB_CCR_UNALIGN_TRP_Pos) /*!< SCB CCR: UNALIGN_TRP Mask */ - -/* SCB System Handler Control and State Register Definitions */ -#define SCB_SHCSR_SVCALLPENDED_Pos 15U /*!< SCB SHCSR: SVCALLPENDED Position */ -#define SCB_SHCSR_SVCALLPENDED_Msk (1UL << SCB_SHCSR_SVCALLPENDED_Pos) /*!< SCB SHCSR: SVCALLPENDED Mask */ - -/*@} end of group CMSIS_SCB */ - - -/** - \ingroup CMSIS_core_register - \defgroup CMSIS_SysTick System Tick Timer (SysTick) - \brief Type definitions for the System Timer Registers. - @{ - */ - -/** - \brief Structure type to access the System Timer (SysTick). - */ -typedef struct -{ - __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) SysTick Control and Status Register */ - __IOM uint32_t LOAD; /*!< Offset: 0x004 (R/W) SysTick Reload Value Register */ - __IOM uint32_t VAL; /*!< Offset: 0x008 (R/W) SysTick Current Value Register */ - __IM uint32_t CALIB; /*!< Offset: 0x00C (R/ ) SysTick Calibration Register */ -} SysTick_Type; - -/* SysTick Control / Status Register Definitions */ -#define SysTick_CTRL_COUNTFLAG_Pos 16U /*!< SysTick CTRL: COUNTFLAG Position */ -#define SysTick_CTRL_COUNTFLAG_Msk (1UL << SysTick_CTRL_COUNTFLAG_Pos) /*!< SysTick CTRL: COUNTFLAG Mask */ - -#define SysTick_CTRL_CLKSOURCE_Pos 2U /*!< SysTick CTRL: CLKSOURCE Position */ -#define SysTick_CTRL_CLKSOURCE_Msk (1UL << SysTick_CTRL_CLKSOURCE_Pos) /*!< SysTick CTRL: CLKSOURCE Mask */ - -#define SysTick_CTRL_TICKINT_Pos 1U /*!< SysTick CTRL: TICKINT Position */ -#define SysTick_CTRL_TICKINT_Msk (1UL << SysTick_CTRL_TICKINT_Pos) /*!< SysTick CTRL: TICKINT Mask */ - -#define SysTick_CTRL_ENABLE_Pos 0U /*!< SysTick CTRL: ENABLE Position */ -#define SysTick_CTRL_ENABLE_Msk (1UL /*<< SysTick_CTRL_ENABLE_Pos*/) /*!< SysTick CTRL: ENABLE Mask */ - -/* SysTick Reload Register Definitions */ -#define SysTick_LOAD_RELOAD_Pos 0U /*!< SysTick LOAD: RELOAD Position */ -#define SysTick_LOAD_RELOAD_Msk (0xFFFFFFUL /*<< SysTick_LOAD_RELOAD_Pos*/) /*!< SysTick LOAD: RELOAD Mask */ - -/* SysTick Current Register Definitions */ -#define SysTick_VAL_CURRENT_Pos 0U /*!< SysTick VAL: CURRENT Position */ -#define SysTick_VAL_CURRENT_Msk (0xFFFFFFUL /*<< SysTick_VAL_CURRENT_Pos*/) /*!< SysTick VAL: CURRENT Mask */ - -/* SysTick Calibration Register Definitions */ -#define SysTick_CALIB_NOREF_Pos 31U /*!< SysTick CALIB: NOREF Position */ -#define SysTick_CALIB_NOREF_Msk (1UL << SysTick_CALIB_NOREF_Pos) /*!< SysTick CALIB: NOREF Mask */ - -#define SysTick_CALIB_SKEW_Pos 30U /*!< SysTick CALIB: SKEW Position */ -#define SysTick_CALIB_SKEW_Msk (1UL << SysTick_CALIB_SKEW_Pos) /*!< SysTick CALIB: SKEW Mask */ - -#define SysTick_CALIB_TENMS_Pos 0U /*!< SysTick CALIB: TENMS Position */ -#define SysTick_CALIB_TENMS_Msk (0xFFFFFFUL /*<< SysTick_CALIB_TENMS_Pos*/) /*!< SysTick CALIB: TENMS Mask */ - -/*@} end of group CMSIS_SysTick */ - -#if (__MPU_PRESENT == 1U) -/** - \ingroup CMSIS_core_register - \defgroup CMSIS_MPU Memory Protection Unit (MPU) - \brief Type definitions for the Memory Protection Unit (MPU) - @{ - */ - -/** - \brief Structure type to access the Memory Protection Unit (MPU). - */ -typedef struct -{ - __IM uint32_t TYPE; /*!< Offset: 0x000 (R/ ) MPU Type Register */ - __IOM uint32_t CTRL; /*!< Offset: 0x004 (R/W) MPU Control Register */ - __IOM uint32_t RNR; /*!< Offset: 0x008 (R/W) MPU Region RNRber Register */ - __IOM uint32_t RBAR; /*!< Offset: 0x00C (R/W) MPU Region Base Address Register */ - __IOM uint32_t RASR; /*!< Offset: 0x010 (R/W) MPU Region Attribute and Size Register */ -} MPU_Type; - -/* MPU Type Register Definitions */ -#define MPU_TYPE_IREGION_Pos 16U /*!< MPU TYPE: IREGION Position */ -#define MPU_TYPE_IREGION_Msk (0xFFUL << MPU_TYPE_IREGION_Pos) /*!< MPU TYPE: IREGION Mask */ - -#define MPU_TYPE_DREGION_Pos 8U /*!< MPU TYPE: DREGION Position */ -#define MPU_TYPE_DREGION_Msk (0xFFUL << MPU_TYPE_DREGION_Pos) /*!< MPU TYPE: DREGION Mask */ - -#define MPU_TYPE_SEPARATE_Pos 0U /*!< MPU TYPE: SEPARATE Position */ -#define MPU_TYPE_SEPARATE_Msk (1UL /*<< MPU_TYPE_SEPARATE_Pos*/) /*!< MPU TYPE: SEPARATE Mask */ - -/* MPU Control Register Definitions */ -#define MPU_CTRL_PRIVDEFENA_Pos 2U /*!< MPU CTRL: PRIVDEFENA Position */ -#define MPU_CTRL_PRIVDEFENA_Msk (1UL << MPU_CTRL_PRIVDEFENA_Pos) /*!< MPU CTRL: PRIVDEFENA Mask */ - -#define MPU_CTRL_HFNMIENA_Pos 1U /*!< MPU CTRL: HFNMIENA Position */ -#define MPU_CTRL_HFNMIENA_Msk (1UL << MPU_CTRL_HFNMIENA_Pos) /*!< MPU CTRL: HFNMIENA Mask */ - -#define MPU_CTRL_ENABLE_Pos 0U /*!< MPU CTRL: ENABLE Position */ -#define MPU_CTRL_ENABLE_Msk (1UL /*<< MPU_CTRL_ENABLE_Pos*/) /*!< MPU CTRL: ENABLE Mask */ - -/* MPU Region Number Register Definitions */ -#define MPU_RNR_REGION_Pos 0U /*!< MPU RNR: REGION Position */ -#define MPU_RNR_REGION_Msk (0xFFUL /*<< MPU_RNR_REGION_Pos*/) /*!< MPU RNR: REGION Mask */ - -/* MPU Region Base Address Register Definitions */ -#define MPU_RBAR_ADDR_Pos 8U /*!< MPU RBAR: ADDR Position */ -#define MPU_RBAR_ADDR_Msk (0xFFFFFFUL << MPU_RBAR_ADDR_Pos) /*!< MPU RBAR: ADDR Mask */ - -#define MPU_RBAR_VALID_Pos 4U /*!< MPU RBAR: VALID Position */ -#define MPU_RBAR_VALID_Msk (1UL << MPU_RBAR_VALID_Pos) /*!< MPU RBAR: VALID Mask */ - -#define MPU_RBAR_REGION_Pos 0U /*!< MPU RBAR: REGION Position */ -#define MPU_RBAR_REGION_Msk (0xFUL /*<< MPU_RBAR_REGION_Pos*/) /*!< MPU RBAR: REGION Mask */ - -/* MPU Region Attribute and Size Register Definitions */ -#define MPU_RASR_ATTRS_Pos 16U /*!< MPU RASR: MPU Region Attribute field Position */ -#define MPU_RASR_ATTRS_Msk (0xFFFFUL << MPU_RASR_ATTRS_Pos) /*!< MPU RASR: MPU Region Attribute field Mask */ - -#define MPU_RASR_XN_Pos 28U /*!< MPU RASR: ATTRS.XN Position */ -#define MPU_RASR_XN_Msk (1UL << MPU_RASR_XN_Pos) /*!< MPU RASR: ATTRS.XN Mask */ - -#define MPU_RASR_AP_Pos 24U /*!< MPU RASR: ATTRS.AP Position */ -#define MPU_RASR_AP_Msk (0x7UL << MPU_RASR_AP_Pos) /*!< MPU RASR: ATTRS.AP Mask */ - -#define MPU_RASR_TEX_Pos 19U /*!< MPU RASR: ATTRS.TEX Position */ -#define MPU_RASR_TEX_Msk (0x7UL << MPU_RASR_TEX_Pos) /*!< MPU RASR: ATTRS.TEX Mask */ - -#define MPU_RASR_S_Pos 18U /*!< MPU RASR: ATTRS.S Position */ -#define MPU_RASR_S_Msk (1UL << MPU_RASR_S_Pos) /*!< MPU RASR: ATTRS.S Mask */ - -#define MPU_RASR_C_Pos 17U /*!< MPU RASR: ATTRS.C Position */ -#define MPU_RASR_C_Msk (1UL << MPU_RASR_C_Pos) /*!< MPU RASR: ATTRS.C Mask */ - -#define MPU_RASR_B_Pos 16U /*!< MPU RASR: ATTRS.B Position */ -#define MPU_RASR_B_Msk (1UL << MPU_RASR_B_Pos) /*!< MPU RASR: ATTRS.B Mask */ - -#define MPU_RASR_SRD_Pos 8U /*!< MPU RASR: Sub-Region Disable Position */ -#define MPU_RASR_SRD_Msk (0xFFUL << MPU_RASR_SRD_Pos) /*!< MPU RASR: Sub-Region Disable Mask */ - -#define MPU_RASR_SIZE_Pos 1U /*!< MPU RASR: Region Size Field Position */ -#define MPU_RASR_SIZE_Msk (0x1FUL << MPU_RASR_SIZE_Pos) /*!< MPU RASR: Region Size Field Mask */ - -#define MPU_RASR_ENABLE_Pos 0U /*!< MPU RASR: Region enable bit Position */ -#define MPU_RASR_ENABLE_Msk (1UL /*<< MPU_RASR_ENABLE_Pos*/) /*!< MPU RASR: Region enable bit Disable Mask */ - -/*@} end of group CMSIS_MPU */ -#endif - - -/** - \ingroup CMSIS_core_register - \defgroup CMSIS_CoreDebug Core Debug Registers (CoreDebug) - \brief Cortex-M0+ Core Debug Registers (DCB registers, SHCSR, and DFSR) are only accessible over DAP and not via processor. - Therefore they are not covered by the Cortex-M0+ header file. - @{ - */ -/*@} end of group CMSIS_CoreDebug */ - - -/** - \ingroup CMSIS_core_register - \defgroup CMSIS_core_bitfield Core register bit field macros - \brief Macros for use with bit field definitions (xxx_Pos, xxx_Msk). - @{ - */ - -/** - \brief Mask and shift a bit field value for use in a register bit range. - \param[in] field Name of the register bit field. - \param[in] value Value of the bit field. - \return Masked and shifted value. -*/ -#define _VAL2FLD(field, value) ((value << field ## _Pos) & field ## _Msk) - -/** - \brief Mask and shift a register value to extract a bit filed value. - \param[in] field Name of the register bit field. - \param[in] value Value of register. - \return Masked and shifted bit field value. -*/ -#define _FLD2VAL(field, value) ((value & field ## _Msk) >> field ## _Pos) - -/*@} end of group CMSIS_core_bitfield */ - - -/** - \ingroup CMSIS_core_register - \defgroup CMSIS_core_base Core Definitions - \brief Definitions for base addresses, unions, and structures. - @{ - */ - -/* Memory mapping of Cortex-M0+ Hardware */ -#define SCS_BASE (0xE000E000UL) /*!< System Control Space Base Address */ -#define SysTick_BASE (SCS_BASE + 0x0010UL) /*!< SysTick Base Address */ -#define NVIC_BASE (SCS_BASE + 0x0100UL) /*!< NVIC Base Address */ -#define SCB_BASE (SCS_BASE + 0x0D00UL) /*!< System Control Block Base Address */ - -#define SCB ((SCB_Type *) SCB_BASE ) /*!< SCB configuration struct */ -#define SysTick ((SysTick_Type *) SysTick_BASE ) /*!< SysTick configuration struct */ -#define NVIC ((NVIC_Type *) NVIC_BASE ) /*!< NVIC configuration struct */ - -#if (__MPU_PRESENT == 1U) - #define MPU_BASE (SCS_BASE + 0x0D90UL) /*!< Memory Protection Unit */ - #define MPU ((MPU_Type *) MPU_BASE ) /*!< Memory Protection Unit */ -#endif - -/*@} */ - - - -/******************************************************************************* - * Hardware Abstraction Layer - Core Function Interface contains: - - Core NVIC Functions - - Core SysTick Functions - - Core Register Access Functions - ******************************************************************************/ -/** - \defgroup CMSIS_Core_FunctionInterface Functions and Instructions Reference -*/ - - - -/* ########################## NVIC functions #################################### */ -/** - \ingroup CMSIS_Core_FunctionInterface - \defgroup CMSIS_Core_NVICFunctions NVIC Functions - \brief Functions that manage interrupts and exceptions via the NVIC. - @{ - */ - -/* Interrupt Priorities are WORD accessible only under ARMv6M */ -/* The following MACROS handle generation of the register offset and byte masks */ -#define _BIT_SHIFT(IRQn) ( ((((uint32_t)(int32_t)(IRQn)) ) & 0x03UL) * 8UL) -#define _SHP_IDX(IRQn) ( (((((uint32_t)(int32_t)(IRQn)) & 0x0FUL)-8UL) >> 2UL) ) -#define _IP_IDX(IRQn) ( (((uint32_t)(int32_t)(IRQn)) >> 2UL) ) - - -/** - \brief Enable External Interrupt - \details Enables a device-specific interrupt in the NVIC interrupt controller. - \param [in] IRQn External interrupt number. Value cannot be negative. - */ -__STATIC_INLINE void NVIC_EnableIRQ(IRQn_Type IRQn) -{ - NVIC->ISER[0U] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL)); -} - - -/** - \brief Disable External Interrupt - \details Disables a device-specific interrupt in the NVIC interrupt controller. - \param [in] IRQn External interrupt number. Value cannot be negative. - */ -__STATIC_INLINE void NVIC_DisableIRQ(IRQn_Type IRQn) -{ - NVIC->ICER[0U] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL)); -} - - -/** - \brief Get Pending Interrupt - \details Reads the pending register in the NVIC and returns the pending bit for the specified interrupt. - \param [in] IRQn Interrupt number. - \return 0 Interrupt status is not pending. - \return 1 Interrupt status is pending. - */ -__STATIC_INLINE uint32_t NVIC_GetPendingIRQ(IRQn_Type IRQn) -{ - return((uint32_t)(((NVIC->ISPR[0U] & (1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); -} - - -/** - \brief Set Pending Interrupt - \details Sets the pending bit of an external interrupt. - \param [in] IRQn Interrupt number. Value cannot be negative. - */ -__STATIC_INLINE void NVIC_SetPendingIRQ(IRQn_Type IRQn) -{ - NVIC->ISPR[0U] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL)); -} - - -/** - \brief Clear Pending Interrupt - \details Clears the pending bit of an external interrupt. - \param [in] IRQn External interrupt number. Value cannot be negative. - */ -__STATIC_INLINE void NVIC_ClearPendingIRQ(IRQn_Type IRQn) -{ - NVIC->ICPR[0U] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL)); -} - - -/** - \brief Set Interrupt Priority - \details Sets the priority of an interrupt. - \note The priority cannot be set for every core interrupt. - \param [in] IRQn Interrupt number. - \param [in] priority Priority to set. - */ -__STATIC_INLINE void NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority) -{ - if ((int32_t)(IRQn) < 0) - { - SCB->SHP[_SHP_IDX(IRQn)] = ((uint32_t)(SCB->SHP[_SHP_IDX(IRQn)] & ~(0xFFUL << _BIT_SHIFT(IRQn))) | - (((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL) << _BIT_SHIFT(IRQn))); - } - else - { - NVIC->IP[_IP_IDX(IRQn)] = ((uint32_t)(NVIC->IP[_IP_IDX(IRQn)] & ~(0xFFUL << _BIT_SHIFT(IRQn))) | - (((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL) << _BIT_SHIFT(IRQn))); - } -} - - -/** - \brief Get Interrupt Priority - \details Reads the priority of an interrupt. - The interrupt number can be positive to specify an external (device specific) interrupt, - or negative to specify an internal (core) interrupt. - \param [in] IRQn Interrupt number. - \return Interrupt Priority. - Value is aligned automatically to the implemented priority bits of the microcontroller. - */ -__STATIC_INLINE uint32_t NVIC_GetPriority(IRQn_Type IRQn) -{ - - if ((int32_t)(IRQn) < 0) - { - return((uint32_t)(((SCB->SHP[_SHP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) & (uint32_t)0xFFUL) >> (8U - __NVIC_PRIO_BITS))); - } - else - { - return((uint32_t)(((NVIC->IP[ _IP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) & (uint32_t)0xFFUL) >> (8U - __NVIC_PRIO_BITS))); - } -} - - -/** - \brief System Reset - \details Initiates a system reset request to reset the MCU. - */ -__STATIC_INLINE void NVIC_SystemReset(void) -{ - __DSB(); /* Ensure all outstanding memory accesses included - buffered write are completed before reset */ - SCB->AIRCR = ((0x5FAUL << SCB_AIRCR_VECTKEY_Pos) | - SCB_AIRCR_SYSRESETREQ_Msk); - __DSB(); /* Ensure completion of memory access */ - - for(;;) /* wait until reset */ - { - __NOP(); - } -} - -/*@} end of CMSIS_Core_NVICFunctions */ - - - -/* ################################## SysTick function ############################################ */ -/** - \ingroup CMSIS_Core_FunctionInterface - \defgroup CMSIS_Core_SysTickFunctions SysTick Functions - \brief Functions that configure the System. - @{ - */ - -#if (__Vendor_SysTickConfig == 0U) - -/** - \brief System Tick Configuration - \details Initializes the System Timer and its interrupt, and starts the System Tick Timer. - Counter is in free running mode to generate periodic interrupts. - \param [in] ticks Number of ticks between two interrupts. - \return 0 Function succeeded. - \return 1 Function failed. - \note When the variable __Vendor_SysTickConfig is set to 1, then the - function SysTick_Config is not included. In this case, the file device.h - must contain a vendor-specific implementation of this function. - */ -__STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks) -{ - if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk) - { - return (1UL); /* Reload value impossible */ - } - - SysTick->LOAD = (uint32_t)(ticks - 1UL); /* set reload register */ - NVIC_SetPriority (SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */ - SysTick->VAL = 0UL; /* Load the SysTick Counter Value */ - SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk | - SysTick_CTRL_TICKINT_Msk | - SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */ - return (0UL); /* Function successful */ -} - -#endif - -/*@} end of CMSIS_Core_SysTickFunctions */ - - - - -#ifdef __cplusplus -} -#endif - -#endif /* __CORE_CM0PLUS_H_DEPENDANT */ - -#endif /* __CMSIS_GENERIC */ diff --git a/bsp/essemi/es32f0334/libraries/CMSIS/Include/core_cmFunc.h b/bsp/essemi/es32f0334/libraries/CMSIS/Include/core_cmFunc.h deleted file mode 100644 index 652a48af07..0000000000 --- a/bsp/essemi/es32f0334/libraries/CMSIS/Include/core_cmFunc.h +++ /dev/null @@ -1,87 +0,0 @@ -/**************************************************************************//** - * @file core_cmFunc.h - * @brief CMSIS Cortex-M Core Function Access Header File - * @version V4.30 - * @date 20. October 2015 - ******************************************************************************/ -/* Copyright (c) 2009 - 2015 ARM LIMITED - - All rights reserved. - Redistribution and use in source and binary forms, with or without - modification, are permitted provided that the following conditions are met: - - Redistributions of source code must retain the above copyright - notice, this list of conditions and the following disclaimer. - - Redistributions in binary form must reproduce the above copyright - notice, this list of conditions and the following disclaimer in the - documentation and/or other materials provided with the distribution. - - Neither the name of ARM nor the names of its contributors may be used - to endorse or promote products derived from this software without - specific prior written permission. - * - THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" - AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE - ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE - LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR - CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF - SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS - INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN - CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) - ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE - POSSIBILITY OF SUCH DAMAGE. - ---------------------------------------------------------------------------*/ - - -#if defined ( __ICCARM__ ) - #pragma system_include /* treat file as system include file for MISRA check */ -#elif defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) - #pragma clang system_header /* treat file as system include file */ -#endif - -#ifndef __CORE_CMFUNC_H -#define __CORE_CMFUNC_H - - -/* ########################### Core Function Access ########################### */ -/** \ingroup CMSIS_Core_FunctionInterface - \defgroup CMSIS_Core_RegAccFunctions CMSIS Core Register Access Functions - @{ -*/ - -/*------------------ RealView Compiler -----------------*/ -#if defined ( __CC_ARM ) - #include "cmsis_armcc.h" - -/*------------------ ARM Compiler V6 -------------------*/ -#elif defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) - #include "cmsis_armcc_V6.h" - -/*------------------ GNU Compiler ----------------------*/ -#elif defined ( __GNUC__ ) - #include "cmsis_gcc.h" - -/*------------------ ICC Compiler ----------------------*/ -#elif defined ( __ICCARM__ ) - #include - -/*------------------ TI CCS Compiler -------------------*/ -#elif defined ( __TMS470__ ) - #include - -/*------------------ TASKING Compiler ------------------*/ -#elif defined ( __TASKING__ ) - /* - * The CMSIS functions have been implemented as intrinsics in the compiler. - * Please use "carm -?i" to get an up to date list of all intrinsics, - * Including the CMSIS ones. - */ - -/*------------------ COSMIC Compiler -------------------*/ -#elif defined ( __CSMC__ ) - #include - -#endif - -/*@} end of CMSIS_Core_RegAccFunctions */ - -#endif /* __CORE_CMFUNC_H */ diff --git a/bsp/essemi/es32f0334/libraries/CMSIS/Include/core_cmInstr.h b/bsp/essemi/es32f0334/libraries/CMSIS/Include/core_cmInstr.h deleted file mode 100644 index f474b0e6f3..0000000000 --- a/bsp/essemi/es32f0334/libraries/CMSIS/Include/core_cmInstr.h +++ /dev/null @@ -1,87 +0,0 @@ -/**************************************************************************//** - * @file core_cmInstr.h - * @brief CMSIS Cortex-M Core Instruction Access Header File - * @version V4.30 - * @date 20. October 2015 - ******************************************************************************/ -/* Copyright (c) 2009 - 2015 ARM LIMITED - - All rights reserved. - Redistribution and use in source and binary forms, with or without - modification, are permitted provided that the following conditions are met: - - Redistributions of source code must retain the above copyright - notice, this list of conditions and the following disclaimer. - - Redistributions in binary form must reproduce the above copyright - notice, this list of conditions and the following disclaimer in the - documentation and/or other materials provided with the distribution. - - Neither the name of ARM nor the names of its contributors may be used - to endorse or promote products derived from this software without - specific prior written permission. - * - THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" - AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE - ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE - LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR - CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF - SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS - INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN - CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) - ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE - POSSIBILITY OF SUCH DAMAGE. - ---------------------------------------------------------------------------*/ - - -#if defined ( __ICCARM__ ) - #pragma system_include /* treat file as system include file for MISRA check */ -#elif defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) - #pragma clang system_header /* treat file as system include file */ -#endif - -#ifndef __CORE_CMINSTR_H -#define __CORE_CMINSTR_H - - -/* ########################## Core Instruction Access ######################### */ -/** \defgroup CMSIS_Core_InstructionInterface CMSIS Core Instruction Interface - Access to dedicated instructions - @{ -*/ - -/*------------------ RealView Compiler -----------------*/ -#if defined ( __CC_ARM ) - #include "cmsis_armcc.h" - -/*------------------ ARM Compiler V6 -------------------*/ -#elif defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) - #include "cmsis_armcc_V6.h" - -/*------------------ GNU Compiler ----------------------*/ -#elif defined ( __GNUC__ ) - #include "cmsis_gcc.h" - -/*------------------ ICC Compiler ----------------------*/ -#elif defined ( __ICCARM__ ) - #include - -/*------------------ TI CCS Compiler -------------------*/ -#elif defined ( __TMS470__ ) - #include - -/*------------------ TASKING Compiler ------------------*/ -#elif defined ( __TASKING__ ) - /* - * The CMSIS functions have been implemented as intrinsics in the compiler. - * Please use "carm -?i" to get an up to date list of all intrinsics, - * Including the CMSIS ones. - */ - -/*------------------ COSMIC Compiler -------------------*/ -#elif defined ( __CSMC__ ) - #include - -#endif - -/*@}*/ /* end of group CMSIS_Core_InstructionInterface */ - -#endif /* __CORE_CMINSTR_H */ diff --git a/bsp/essemi/es32f0334/libraries/CMSIS/Include/core_cmSimd.h b/bsp/essemi/es32f0334/libraries/CMSIS/Include/core_cmSimd.h deleted file mode 100644 index 66bf5c2a72..0000000000 --- a/bsp/essemi/es32f0334/libraries/CMSIS/Include/core_cmSimd.h +++ /dev/null @@ -1,96 +0,0 @@ -/**************************************************************************//** - * @file core_cmSimd.h - * @brief CMSIS Cortex-M SIMD Header File - * @version V4.30 - * @date 20. October 2015 - ******************************************************************************/ -/* Copyright (c) 2009 - 2015 ARM LIMITED - - All rights reserved. - Redistribution and use in source and binary forms, with or without - modification, are permitted provided that the following conditions are met: - - Redistributions of source code must retain the above copyright - notice, this list of conditions and the following disclaimer. - - Redistributions in binary form must reproduce the above copyright - notice, this list of conditions and the following disclaimer in the - documentation and/or other materials provided with the distribution. - - Neither the name of ARM nor the names of its contributors may be used - to endorse or promote products derived from this software without - specific prior written permission. - * - THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" - AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE - ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE - LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR - CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF - SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS - INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN - CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) - ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE - POSSIBILITY OF SUCH DAMAGE. - ---------------------------------------------------------------------------*/ - - -#if defined ( __ICCARM__ ) - #pragma system_include /* treat file as system include file for MISRA check */ -#elif defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) - #pragma clang system_header /* treat file as system include file */ -#endif - -#ifndef __CORE_CMSIMD_H -#define __CORE_CMSIMD_H - -#ifdef __cplusplus - extern "C" { -#endif - - -/* ################### Compiler specific Intrinsics ########################### */ -/** \defgroup CMSIS_SIMD_intrinsics CMSIS SIMD Intrinsics - Access to dedicated SIMD instructions - @{ -*/ - -/*------------------ RealView Compiler -----------------*/ -#if defined ( __CC_ARM ) - #include "cmsis_armcc.h" - -/*------------------ ARM Compiler V6 -------------------*/ -#elif defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) - #include "cmsis_armcc_V6.h" - -/*------------------ GNU Compiler ----------------------*/ -#elif defined ( __GNUC__ ) - #include "cmsis_gcc.h" - -/*------------------ ICC Compiler ----------------------*/ -#elif defined ( __ICCARM__ ) - #include - -/*------------------ TI CCS Compiler -------------------*/ -#elif defined ( __TMS470__ ) - #include - -/*------------------ TASKING Compiler ------------------*/ -#elif defined ( __TASKING__ ) - /* - * The CMSIS functions have been implemented as intrinsics in the compiler. - * Please use "carm -?i" to get an up to date list of all intrinsics, - * Including the CMSIS ones. - */ - -/*------------------ COSMIC Compiler -------------------*/ -#elif defined ( __CSMC__ ) - #include - -#endif - -/*@} end of group CMSIS_SIMD_intrinsics */ - - -#ifdef __cplusplus -} -#endif - -#endif /* __CORE_CMSIMD_H */ diff --git a/bsp/essemi/es32f0334/libraries/CMSIS/Include/core_sc000.h b/bsp/essemi/es32f0334/libraries/CMSIS/Include/core_sc000.h deleted file mode 100644 index 514dbd81b9..0000000000 --- a/bsp/essemi/es32f0334/libraries/CMSIS/Include/core_sc000.h +++ /dev/null @@ -1,926 +0,0 @@ -/**************************************************************************//** - * @file core_sc000.h - * @brief CMSIS SC000 Core Peripheral Access Layer Header File - * @version V4.30 - * @date 20. October 2015 - ******************************************************************************/ -/* Copyright (c) 2009 - 2015 ARM LIMITED - - All rights reserved. - Redistribution and use in source and binary forms, with or without - modification, are permitted provided that the following conditions are met: - - Redistributions of source code must retain the above copyright - notice, this list of conditions and the following disclaimer. - - Redistributions in binary form must reproduce the above copyright - notice, this list of conditions and the following disclaimer in the - documentation and/or other materials provided with the distribution. - - Neither the name of ARM nor the names of its contributors may be used - to endorse or promote products derived from this software without - specific prior written permission. - * - THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" - AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE - ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE - LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR - CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF - SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS - INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN - CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) - ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE - POSSIBILITY OF SUCH DAMAGE. - ---------------------------------------------------------------------------*/ - - -#if defined ( __ICCARM__ ) - #pragma system_include /* treat file as system include file for MISRA check */ -#elif defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) - #pragma clang system_header /* treat file as system include file */ -#endif - -#ifndef __CORE_SC000_H_GENERIC -#define __CORE_SC000_H_GENERIC - -#include - -#ifdef __cplusplus - extern "C" { -#endif - -/** - \page CMSIS_MISRA_Exceptions MISRA-C:2004 Compliance Exceptions - CMSIS violates the following MISRA-C:2004 rules: - - \li Required Rule 8.5, object/function definition in header file.
- Function definitions in header files are used to allow 'inlining'. - - \li Required Rule 18.4, declaration of union type or object of union type: '{...}'.
- Unions are used for effective representation of core registers. - - \li Advisory Rule 19.7, Function-like macro defined.
- Function-like macros are used to allow more efficient code. - */ - - -/******************************************************************************* - * CMSIS definitions - ******************************************************************************/ -/** - \ingroup SC000 - @{ - */ - -/* CMSIS SC000 definitions */ -#define __SC000_CMSIS_VERSION_MAIN (0x04U) /*!< [31:16] CMSIS HAL main version */ -#define __SC000_CMSIS_VERSION_SUB (0x1EU) /*!< [15:0] CMSIS HAL sub version */ -#define __SC000_CMSIS_VERSION ((__SC000_CMSIS_VERSION_MAIN << 16U) | \ - __SC000_CMSIS_VERSION_SUB ) /*!< CMSIS HAL version number */ - -#define __CORTEX_SC (000U) /*!< Cortex secure core */ - - -#if defined ( __CC_ARM ) - #define __ASM __asm /*!< asm keyword for ARM Compiler */ - #define __INLINE __inline /*!< inline keyword for ARM Compiler */ - #define __STATIC_INLINE static __inline - -#elif defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) - #define __ASM __asm /*!< asm keyword for ARM Compiler */ - #define __INLINE __inline /*!< inline keyword for ARM Compiler */ - #define __STATIC_INLINE static __inline - -#elif defined ( __GNUC__ ) - #define __ASM __asm /*!< asm keyword for GNU Compiler */ - #define __INLINE inline /*!< inline keyword for GNU Compiler */ - #define __STATIC_INLINE static inline - -#elif defined ( __ICCARM__ ) - #define __ASM __asm /*!< asm keyword for IAR Compiler */ - #define __INLINE inline /*!< inline keyword for IAR Compiler. Only available in High optimization mode! */ - #define __STATIC_INLINE static inline - -#elif defined ( __TMS470__ ) - #define __ASM __asm /*!< asm keyword for TI CCS Compiler */ - #define __STATIC_INLINE static inline - -#elif defined ( __TASKING__ ) - #define __ASM __asm /*!< asm keyword for TASKING Compiler */ - #define __INLINE inline /*!< inline keyword for TASKING Compiler */ - #define __STATIC_INLINE static inline - -#elif defined ( __CSMC__ ) - #define __packed - #define __ASM _asm /*!< asm keyword for COSMIC Compiler */ - #define __INLINE inline /*!< inline keyword for COSMIC Compiler. Use -pc99 on compile line */ - #define __STATIC_INLINE static inline - -#else - #error Unknown compiler -#endif - -/** __FPU_USED indicates whether an FPU is used or not. - This core does not support an FPU at all -*/ -#define __FPU_USED 0U - -#if defined ( __CC_ARM ) - #if defined __TARGET_FPU_VFP - #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" - #endif - -#elif defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) - #if defined __ARM_PCS_VFP - #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" - #endif - -#elif defined ( __GNUC__ ) - #if defined (__VFP_FP__) && !defined(__SOFTFP__) - #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" - #endif - -#elif defined ( __ICCARM__ ) - #if defined __ARMVFP__ - #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" - #endif - -#elif defined ( __TMS470__ ) - #if defined __TI_VFP_SUPPORT__ - #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" - #endif - -#elif defined ( __TASKING__ ) - #if defined __FPU_VFP__ - #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" - #endif - -#elif defined ( __CSMC__ ) - #if ( __CSMC__ & 0x400U) - #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" - #endif - -#endif - -#include "core_cmInstr.h" /* Core Instruction Access */ -#include "core_cmFunc.h" /* Core Function Access */ - -#ifdef __cplusplus -} -#endif - -#endif /* __CORE_SC000_H_GENERIC */ - -#ifndef __CMSIS_GENERIC - -#ifndef __CORE_SC000_H_DEPENDANT -#define __CORE_SC000_H_DEPENDANT - -#ifdef __cplusplus - extern "C" { -#endif - -/* check device defines and use defaults */ -#if defined __CHECK_DEVICE_DEFINES - #ifndef __SC000_REV - #define __SC000_REV 0x0000U - #warning "__SC000_REV not defined in device header file; using default!" - #endif - - #ifndef __MPU_PRESENT - #define __MPU_PRESENT 0U - #warning "__MPU_PRESENT not defined in device header file; using default!" - #endif - - #ifndef __NVIC_PRIO_BITS - #define __NVIC_PRIO_BITS 2U - #warning "__NVIC_PRIO_BITS not defined in device header file; using default!" - #endif - - #ifndef __Vendor_SysTickConfig - #define __Vendor_SysTickConfig 0U - #warning "__Vendor_SysTickConfig not defined in device header file; using default!" - #endif -#endif - -/* IO definitions (access restrictions to peripheral registers) */ -/** - \defgroup CMSIS_glob_defs CMSIS Global Defines - - IO Type Qualifiers are used - \li to specify the access to peripheral variables. - \li for automatic generation of peripheral register debug information. -*/ -#ifdef __cplusplus - #define __I volatile /*!< Defines 'read only' permissions */ -#else - #define __I volatile const /*!< Defines 'read only' permissions */ -#endif -#define __O volatile /*!< Defines 'write only' permissions */ -#define __IO volatile /*!< Defines 'read / write' permissions */ - -/* following defines should be used for structure members */ -#define __IM volatile const /*! Defines 'read only' structure member permissions */ -#define __OM volatile /*! Defines 'write only' structure member permissions */ -#define __IOM volatile /*! Defines 'read / write' structure member permissions */ - -/*@} end of group SC000 */ - - - -/******************************************************************************* - * Register Abstraction - Core Register contain: - - Core Register - - Core NVIC Register - - Core SCB Register - - Core SysTick Register - - Core MPU Register - ******************************************************************************/ -/** - \defgroup CMSIS_core_register Defines and Type Definitions - \brief Type definitions and defines for Cortex-M processor based devices. -*/ - -/** - \ingroup CMSIS_core_register - \defgroup CMSIS_CORE Status and Control Registers - \brief Core Register type definitions. - @{ - */ - -/** - \brief Union type to access the Application Program Status Register (APSR). - */ -typedef union -{ - struct - { - uint32_t _reserved0:28; /*!< bit: 0..27 Reserved */ - uint32_t V:1; /*!< bit: 28 Overflow condition code flag */ - uint32_t C:1; /*!< bit: 29 Carry condition code flag */ - uint32_t Z:1; /*!< bit: 30 Zero condition code flag */ - uint32_t N:1; /*!< bit: 31 Negative condition code flag */ - } b; /*!< Structure used for bit access */ - uint32_t w; /*!< Type used for word access */ -} APSR_Type; - -/* APSR Register Definitions */ -#define APSR_N_Pos 31U /*!< APSR: N Position */ -#define APSR_N_Msk (1UL << APSR_N_Pos) /*!< APSR: N Mask */ - -#define APSR_Z_Pos 30U /*!< APSR: Z Position */ -#define APSR_Z_Msk (1UL << APSR_Z_Pos) /*!< APSR: Z Mask */ - -#define APSR_C_Pos 29U /*!< APSR: C Position */ -#define APSR_C_Msk (1UL << APSR_C_Pos) /*!< APSR: C Mask */ - -#define APSR_V_Pos 28U /*!< APSR: V Position */ -#define APSR_V_Msk (1UL << APSR_V_Pos) /*!< APSR: V Mask */ - - -/** - \brief Union type to access the Interrupt Program Status Register (IPSR). - */ -typedef union -{ - struct - { - uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */ - uint32_t _reserved0:23; /*!< bit: 9..31 Reserved */ - } b; /*!< Structure used for bit access */ - uint32_t w; /*!< Type used for word access */ -} IPSR_Type; - -/* IPSR Register Definitions */ -#define IPSR_ISR_Pos 0U /*!< IPSR: ISR Position */ -#define IPSR_ISR_Msk (0x1FFUL /*<< IPSR_ISR_Pos*/) /*!< IPSR: ISR Mask */ - - -/** - \brief Union type to access the Special-Purpose Program Status Registers (xPSR). - */ -typedef union -{ - struct - { - uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */ - uint32_t _reserved0:15; /*!< bit: 9..23 Reserved */ - uint32_t T:1; /*!< bit: 24 Thumb bit (read 0) */ - uint32_t _reserved1:3; /*!< bit: 25..27 Reserved */ - uint32_t V:1; /*!< bit: 28 Overflow condition code flag */ - uint32_t C:1; /*!< bit: 29 Carry condition code flag */ - uint32_t Z:1; /*!< bit: 30 Zero condition code flag */ - uint32_t N:1; /*!< bit: 31 Negative condition code flag */ - } b; /*!< Structure used for bit access */ - uint32_t w; /*!< Type used for word access */ -} xPSR_Type; - -/* xPSR Register Definitions */ -#define xPSR_N_Pos 31U /*!< xPSR: N Position */ -#define xPSR_N_Msk (1UL << xPSR_N_Pos) /*!< xPSR: N Mask */ - -#define xPSR_Z_Pos 30U /*!< xPSR: Z Position */ -#define xPSR_Z_Msk (1UL << xPSR_Z_Pos) /*!< xPSR: Z Mask */ - -#define xPSR_C_Pos 29U /*!< xPSR: C Position */ -#define xPSR_C_Msk (1UL << xPSR_C_Pos) /*!< xPSR: C Mask */ - -#define xPSR_V_Pos 28U /*!< xPSR: V Position */ -#define xPSR_V_Msk (1UL << xPSR_V_Pos) /*!< xPSR: V Mask */ - -#define xPSR_T_Pos 24U /*!< xPSR: T Position */ -#define xPSR_T_Msk (1UL << xPSR_T_Pos) /*!< xPSR: T Mask */ - -#define xPSR_ISR_Pos 0U /*!< xPSR: ISR Position */ -#define xPSR_ISR_Msk (0x1FFUL /*<< xPSR_ISR_Pos*/) /*!< xPSR: ISR Mask */ - - -/** - \brief Union type to access the Control Registers (CONTROL). - */ -typedef union -{ - struct - { - uint32_t _reserved0:1; /*!< bit: 0 Reserved */ - uint32_t SPSEL:1; /*!< bit: 1 Stack to be used */ - uint32_t _reserved1:30; /*!< bit: 2..31 Reserved */ - } b; /*!< Structure used for bit access */ - uint32_t w; /*!< Type used for word access */ -} CONTROL_Type; - -/* CONTROL Register Definitions */ -#define CONTROL_SPSEL_Pos 1U /*!< CONTROL: SPSEL Position */ -#define CONTROL_SPSEL_Msk (1UL << CONTROL_SPSEL_Pos) /*!< CONTROL: SPSEL Mask */ - -/*@} end of group CMSIS_CORE */ - - -/** - \ingroup CMSIS_core_register - \defgroup CMSIS_NVIC Nested Vectored Interrupt Controller (NVIC) - \brief Type definitions for the NVIC Registers - @{ - */ - -/** - \brief Structure type to access the Nested Vectored Interrupt Controller (NVIC). - */ -typedef struct -{ - __IOM uint32_t ISER[1U]; /*!< Offset: 0x000 (R/W) Interrupt Set Enable Register */ - uint32_t RESERVED0[31U]; - __IOM uint32_t ICER[1U]; /*!< Offset: 0x080 (R/W) Interrupt Clear Enable Register */ - uint32_t RSERVED1[31U]; - __IOM uint32_t ISPR[1U]; /*!< Offset: 0x100 (R/W) Interrupt Set Pending Register */ - uint32_t RESERVED2[31U]; - __IOM uint32_t ICPR[1U]; /*!< Offset: 0x180 (R/W) Interrupt Clear Pending Register */ - uint32_t RESERVED3[31U]; - uint32_t RESERVED4[64U]; - __IOM uint32_t IP[8U]; /*!< Offset: 0x300 (R/W) Interrupt Priority Register */ -} NVIC_Type; - -/*@} end of group CMSIS_NVIC */ - - -/** - \ingroup CMSIS_core_register - \defgroup CMSIS_SCB System Control Block (SCB) - \brief Type definitions for the System Control Block Registers - @{ - */ - -/** - \brief Structure type to access the System Control Block (SCB). - */ -typedef struct -{ - __IM uint32_t CPUID; /*!< Offset: 0x000 (R/ ) CPUID Base Register */ - __IOM uint32_t ICSR; /*!< Offset: 0x004 (R/W) Interrupt Control and State Register */ - __IOM uint32_t VTOR; /*!< Offset: 0x008 (R/W) Vector Table Offset Register */ - __IOM uint32_t AIRCR; /*!< Offset: 0x00C (R/W) Application Interrupt and Reset Control Register */ - __IOM uint32_t SCR; /*!< Offset: 0x010 (R/W) System Control Register */ - __IOM uint32_t CCR; /*!< Offset: 0x014 (R/W) Configuration Control Register */ - uint32_t RESERVED0[1U]; - __IOM uint32_t SHP[2U]; /*!< Offset: 0x01C (R/W) System Handlers Priority Registers. [0] is RESERVED */ - __IOM uint32_t SHCSR; /*!< Offset: 0x024 (R/W) System Handler Control and State Register */ - uint32_t RESERVED1[154U]; - __IOM uint32_t SFCR; /*!< Offset: 0x290 (R/W) Security Features Control Register */ -} SCB_Type; - -/* SCB CPUID Register Definitions */ -#define SCB_CPUID_IMPLEMENTER_Pos 24U /*!< SCB CPUID: IMPLEMENTER Position */ -#define SCB_CPUID_IMPLEMENTER_Msk (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos) /*!< SCB CPUID: IMPLEMENTER Mask */ - -#define SCB_CPUID_VARIANT_Pos 20U /*!< SCB CPUID: VARIANT Position */ -#define SCB_CPUID_VARIANT_Msk (0xFUL << SCB_CPUID_VARIANT_Pos) /*!< SCB CPUID: VARIANT Mask */ - -#define SCB_CPUID_ARCHITECTURE_Pos 16U /*!< SCB CPUID: ARCHITECTURE Position */ -#define SCB_CPUID_ARCHITECTURE_Msk (0xFUL << SCB_CPUID_ARCHITECTURE_Pos) /*!< SCB CPUID: ARCHITECTURE Mask */ - -#define SCB_CPUID_PARTNO_Pos 4U /*!< SCB CPUID: PARTNO Position */ -#define SCB_CPUID_PARTNO_Msk (0xFFFUL << SCB_CPUID_PARTNO_Pos) /*!< SCB CPUID: PARTNO Mask */ - -#define SCB_CPUID_REVISION_Pos 0U /*!< SCB CPUID: REVISION Position */ -#define SCB_CPUID_REVISION_Msk (0xFUL /*<< SCB_CPUID_REVISION_Pos*/) /*!< SCB CPUID: REVISION Mask */ - -/* SCB Interrupt Control State Register Definitions */ -#define SCB_ICSR_NMIPENDSET_Pos 31U /*!< SCB ICSR: NMIPENDSET Position */ -#define SCB_ICSR_NMIPENDSET_Msk (1UL << SCB_ICSR_NMIPENDSET_Pos) /*!< SCB ICSR: NMIPENDSET Mask */ - -#define SCB_ICSR_PENDSVSET_Pos 28U /*!< SCB ICSR: PENDSVSET Position */ -#define SCB_ICSR_PENDSVSET_Msk (1UL << SCB_ICSR_PENDSVSET_Pos) /*!< SCB ICSR: PENDSVSET Mask */ - -#define SCB_ICSR_PENDSVCLR_Pos 27U /*!< SCB ICSR: PENDSVCLR Position */ -#define SCB_ICSR_PENDSVCLR_Msk (1UL << SCB_ICSR_PENDSVCLR_Pos) /*!< SCB ICSR: PENDSVCLR Mask */ - -#define SCB_ICSR_PENDSTSET_Pos 26U /*!< SCB ICSR: PENDSTSET Position */ -#define SCB_ICSR_PENDSTSET_Msk (1UL << SCB_ICSR_PENDSTSET_Pos) /*!< SCB ICSR: PENDSTSET Mask */ - -#define SCB_ICSR_PENDSTCLR_Pos 25U /*!< SCB ICSR: PENDSTCLR Position */ -#define SCB_ICSR_PENDSTCLR_Msk (1UL << SCB_ICSR_PENDSTCLR_Pos) /*!< SCB ICSR: PENDSTCLR Mask */ - -#define SCB_ICSR_ISRPREEMPT_Pos 23U /*!< SCB ICSR: ISRPREEMPT Position */ -#define SCB_ICSR_ISRPREEMPT_Msk (1UL << SCB_ICSR_ISRPREEMPT_Pos) /*!< SCB ICSR: ISRPREEMPT Mask */ - -#define SCB_ICSR_ISRPENDING_Pos 22U /*!< SCB ICSR: ISRPENDING Position */ -#define SCB_ICSR_ISRPENDING_Msk (1UL << SCB_ICSR_ISRPENDING_Pos) /*!< SCB ICSR: ISRPENDING Mask */ - -#define SCB_ICSR_VECTPENDING_Pos 12U /*!< SCB ICSR: VECTPENDING Position */ -#define SCB_ICSR_VECTPENDING_Msk (0x1FFUL << SCB_ICSR_VECTPENDING_Pos) /*!< SCB ICSR: VECTPENDING Mask */ - -#define SCB_ICSR_VECTACTIVE_Pos 0U /*!< SCB ICSR: VECTACTIVE Position */ -#define SCB_ICSR_VECTACTIVE_Msk (0x1FFUL /*<< SCB_ICSR_VECTACTIVE_Pos*/) /*!< SCB ICSR: VECTACTIVE Mask */ - -/* SCB Interrupt Control State Register Definitions */ -#define SCB_VTOR_TBLOFF_Pos 7U /*!< SCB VTOR: TBLOFF Position */ -#define SCB_VTOR_TBLOFF_Msk (0x1FFFFFFUL << SCB_VTOR_TBLOFF_Pos) /*!< SCB VTOR: TBLOFF Mask */ - -/* SCB Application Interrupt and Reset Control Register Definitions */ -#define SCB_AIRCR_VECTKEY_Pos 16U /*!< SCB AIRCR: VECTKEY Position */ -#define SCB_AIRCR_VECTKEY_Msk (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos) /*!< SCB AIRCR: VECTKEY Mask */ - -#define SCB_AIRCR_VECTKEYSTAT_Pos 16U /*!< SCB AIRCR: VECTKEYSTAT Position */ -#define SCB_AIRCR_VECTKEYSTAT_Msk (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos) /*!< SCB AIRCR: VECTKEYSTAT Mask */ - -#define SCB_AIRCR_ENDIANESS_Pos 15U /*!< SCB AIRCR: ENDIANESS Position */ -#define SCB_AIRCR_ENDIANESS_Msk (1UL << SCB_AIRCR_ENDIANESS_Pos) /*!< SCB AIRCR: ENDIANESS Mask */ - -#define SCB_AIRCR_SYSRESETREQ_Pos 2U /*!< SCB AIRCR: SYSRESETREQ Position */ -#define SCB_AIRCR_SYSRESETREQ_Msk (1UL << SCB_AIRCR_SYSRESETREQ_Pos) /*!< SCB AIRCR: SYSRESETREQ Mask */ - -#define SCB_AIRCR_VECTCLRACTIVE_Pos 1U /*!< SCB AIRCR: VECTCLRACTIVE Position */ -#define SCB_AIRCR_VECTCLRACTIVE_Msk (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos) /*!< SCB AIRCR: VECTCLRACTIVE Mask */ - -/* SCB System Control Register Definitions */ -#define SCB_SCR_SEVONPEND_Pos 4U /*!< SCB SCR: SEVONPEND Position */ -#define SCB_SCR_SEVONPEND_Msk (1UL << SCB_SCR_SEVONPEND_Pos) /*!< SCB SCR: SEVONPEND Mask */ - -#define SCB_SCR_SLEEPDEEP_Pos 2U /*!< SCB SCR: SLEEPDEEP Position */ -#define SCB_SCR_SLEEPDEEP_Msk (1UL << SCB_SCR_SLEEPDEEP_Pos) /*!< SCB SCR: SLEEPDEEP Mask */ - -#define SCB_SCR_SLEEPONEXIT_Pos 1U /*!< SCB SCR: SLEEPONEXIT Position */ -#define SCB_SCR_SLEEPONEXIT_Msk (1UL << SCB_SCR_SLEEPONEXIT_Pos) /*!< SCB SCR: SLEEPONEXIT Mask */ - -/* SCB Configuration Control Register Definitions */ -#define SCB_CCR_STKALIGN_Pos 9U /*!< SCB CCR: STKALIGN Position */ -#define SCB_CCR_STKALIGN_Msk (1UL << SCB_CCR_STKALIGN_Pos) /*!< SCB CCR: STKALIGN Mask */ - -#define SCB_CCR_UNALIGN_TRP_Pos 3U /*!< SCB CCR: UNALIGN_TRP Position */ -#define SCB_CCR_UNALIGN_TRP_Msk (1UL << SCB_CCR_UNALIGN_TRP_Pos) /*!< SCB CCR: UNALIGN_TRP Mask */ - -/* SCB System Handler Control and State Register Definitions */ -#define SCB_SHCSR_SVCALLPENDED_Pos 15U /*!< SCB SHCSR: SVCALLPENDED Position */ -#define SCB_SHCSR_SVCALLPENDED_Msk (1UL << SCB_SHCSR_SVCALLPENDED_Pos) /*!< SCB SHCSR: SVCALLPENDED Mask */ - -/*@} end of group CMSIS_SCB */ - - -/** - \ingroup CMSIS_core_register - \defgroup CMSIS_SCnSCB System Controls not in SCB (SCnSCB) - \brief Type definitions for the System Control and ID Register not in the SCB - @{ - */ - -/** - \brief Structure type to access the System Control and ID Register not in the SCB. - */ -typedef struct -{ - uint32_t RESERVED0[2U]; - __IOM uint32_t ACTLR; /*!< Offset: 0x008 (R/W) Auxiliary Control Register */ -} SCnSCB_Type; - -/* Auxiliary Control Register Definitions */ -#define SCnSCB_ACTLR_DISMCYCINT_Pos 0U /*!< ACTLR: DISMCYCINT Position */ -#define SCnSCB_ACTLR_DISMCYCINT_Msk (1UL /*<< SCnSCB_ACTLR_DISMCYCINT_Pos*/) /*!< ACTLR: DISMCYCINT Mask */ - -/*@} end of group CMSIS_SCnotSCB */ - - -/** - \ingroup CMSIS_core_register - \defgroup CMSIS_SysTick System Tick Timer (SysTick) - \brief Type definitions for the System Timer Registers. - @{ - */ - -/** - \brief Structure type to access the System Timer (SysTick). - */ -typedef struct -{ - __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) SysTick Control and Status Register */ - __IOM uint32_t LOAD; /*!< Offset: 0x004 (R/W) SysTick Reload Value Register */ - __IOM uint32_t VAL; /*!< Offset: 0x008 (R/W) SysTick Current Value Register */ - __IM uint32_t CALIB; /*!< Offset: 0x00C (R/ ) SysTick Calibration Register */ -} SysTick_Type; - -/* SysTick Control / Status Register Definitions */ -#define SysTick_CTRL_COUNTFLAG_Pos 16U /*!< SysTick CTRL: COUNTFLAG Position */ -#define SysTick_CTRL_COUNTFLAG_Msk (1UL << SysTick_CTRL_COUNTFLAG_Pos) /*!< SysTick CTRL: COUNTFLAG Mask */ - -#define SysTick_CTRL_CLKSOURCE_Pos 2U /*!< SysTick CTRL: CLKSOURCE Position */ -#define SysTick_CTRL_CLKSOURCE_Msk (1UL << SysTick_CTRL_CLKSOURCE_Pos) /*!< SysTick CTRL: CLKSOURCE Mask */ - -#define SysTick_CTRL_TICKINT_Pos 1U /*!< SysTick CTRL: TICKINT Position */ -#define SysTick_CTRL_TICKINT_Msk (1UL << SysTick_CTRL_TICKINT_Pos) /*!< SysTick CTRL: TICKINT Mask */ - -#define SysTick_CTRL_ENABLE_Pos 0U /*!< SysTick CTRL: ENABLE Position */ -#define SysTick_CTRL_ENABLE_Msk (1UL /*<< SysTick_CTRL_ENABLE_Pos*/) /*!< SysTick CTRL: ENABLE Mask */ - -/* SysTick Reload Register Definitions */ -#define SysTick_LOAD_RELOAD_Pos 0U /*!< SysTick LOAD: RELOAD Position */ -#define SysTick_LOAD_RELOAD_Msk (0xFFFFFFUL /*<< SysTick_LOAD_RELOAD_Pos*/) /*!< SysTick LOAD: RELOAD Mask */ - -/* SysTick Current Register Definitions */ -#define SysTick_VAL_CURRENT_Pos 0U /*!< SysTick VAL: CURRENT Position */ -#define SysTick_VAL_CURRENT_Msk (0xFFFFFFUL /*<< SysTick_VAL_CURRENT_Pos*/) /*!< SysTick VAL: CURRENT Mask */ - -/* SysTick Calibration Register Definitions */ -#define SysTick_CALIB_NOREF_Pos 31U /*!< SysTick CALIB: NOREF Position */ -#define SysTick_CALIB_NOREF_Msk (1UL << SysTick_CALIB_NOREF_Pos) /*!< SysTick CALIB: NOREF Mask */ - -#define SysTick_CALIB_SKEW_Pos 30U /*!< SysTick CALIB: SKEW Position */ -#define SysTick_CALIB_SKEW_Msk (1UL << SysTick_CALIB_SKEW_Pos) /*!< SysTick CALIB: SKEW Mask */ - -#define SysTick_CALIB_TENMS_Pos 0U /*!< SysTick CALIB: TENMS Position */ -#define SysTick_CALIB_TENMS_Msk (0xFFFFFFUL /*<< SysTick_CALIB_TENMS_Pos*/) /*!< SysTick CALIB: TENMS Mask */ - -/*@} end of group CMSIS_SysTick */ - -#if (__MPU_PRESENT == 1U) -/** - \ingroup CMSIS_core_register - \defgroup CMSIS_MPU Memory Protection Unit (MPU) - \brief Type definitions for the Memory Protection Unit (MPU) - @{ - */ - -/** - \brief Structure type to access the Memory Protection Unit (MPU). - */ -typedef struct -{ - __IM uint32_t TYPE; /*!< Offset: 0x000 (R/ ) MPU Type Register */ - __IOM uint32_t CTRL; /*!< Offset: 0x004 (R/W) MPU Control Register */ - __IOM uint32_t RNR; /*!< Offset: 0x008 (R/W) MPU Region RNRber Register */ - __IOM uint32_t RBAR; /*!< Offset: 0x00C (R/W) MPU Region Base Address Register */ - __IOM uint32_t RASR; /*!< Offset: 0x010 (R/W) MPU Region Attribute and Size Register */ -} MPU_Type; - -/* MPU Type Register Definitions */ -#define MPU_TYPE_IREGION_Pos 16U /*!< MPU TYPE: IREGION Position */ -#define MPU_TYPE_IREGION_Msk (0xFFUL << MPU_TYPE_IREGION_Pos) /*!< MPU TYPE: IREGION Mask */ - -#define MPU_TYPE_DREGION_Pos 8U /*!< MPU TYPE: DREGION Position */ -#define MPU_TYPE_DREGION_Msk (0xFFUL << MPU_TYPE_DREGION_Pos) /*!< MPU TYPE: DREGION Mask */ - -#define MPU_TYPE_SEPARATE_Pos 0U /*!< MPU TYPE: SEPARATE Position */ -#define MPU_TYPE_SEPARATE_Msk (1UL /*<< MPU_TYPE_SEPARATE_Pos*/) /*!< MPU TYPE: SEPARATE Mask */ - -/* MPU Control Register Definitions */ -#define MPU_CTRL_PRIVDEFENA_Pos 2U /*!< MPU CTRL: PRIVDEFENA Position */ -#define MPU_CTRL_PRIVDEFENA_Msk (1UL << MPU_CTRL_PRIVDEFENA_Pos) /*!< MPU CTRL: PRIVDEFENA Mask */ - -#define MPU_CTRL_HFNMIENA_Pos 1U /*!< MPU CTRL: HFNMIENA Position */ -#define MPU_CTRL_HFNMIENA_Msk (1UL << MPU_CTRL_HFNMIENA_Pos) /*!< MPU CTRL: HFNMIENA Mask */ - -#define MPU_CTRL_ENABLE_Pos 0U /*!< MPU CTRL: ENABLE Position */ -#define MPU_CTRL_ENABLE_Msk (1UL /*<< MPU_CTRL_ENABLE_Pos*/) /*!< MPU CTRL: ENABLE Mask */ - -/* MPU Region Number Register Definitions */ -#define MPU_RNR_REGION_Pos 0U /*!< MPU RNR: REGION Position */ -#define MPU_RNR_REGION_Msk (0xFFUL /*<< MPU_RNR_REGION_Pos*/) /*!< MPU RNR: REGION Mask */ - -/* MPU Region Base Address Register Definitions */ -#define MPU_RBAR_ADDR_Pos 8U /*!< MPU RBAR: ADDR Position */ -#define MPU_RBAR_ADDR_Msk (0xFFFFFFUL << MPU_RBAR_ADDR_Pos) /*!< MPU RBAR: ADDR Mask */ - -#define MPU_RBAR_VALID_Pos 4U /*!< MPU RBAR: VALID Position */ -#define MPU_RBAR_VALID_Msk (1UL << MPU_RBAR_VALID_Pos) /*!< MPU RBAR: VALID Mask */ - -#define MPU_RBAR_REGION_Pos 0U /*!< MPU RBAR: REGION Position */ -#define MPU_RBAR_REGION_Msk (0xFUL /*<< MPU_RBAR_REGION_Pos*/) /*!< MPU RBAR: REGION Mask */ - -/* MPU Region Attribute and Size Register Definitions */ -#define MPU_RASR_ATTRS_Pos 16U /*!< MPU RASR: MPU Region Attribute field Position */ -#define MPU_RASR_ATTRS_Msk (0xFFFFUL << MPU_RASR_ATTRS_Pos) /*!< MPU RASR: MPU Region Attribute field Mask */ - -#define MPU_RASR_XN_Pos 28U /*!< MPU RASR: ATTRS.XN Position */ -#define MPU_RASR_XN_Msk (1UL << MPU_RASR_XN_Pos) /*!< MPU RASR: ATTRS.XN Mask */ - -#define MPU_RASR_AP_Pos 24U /*!< MPU RASR: ATTRS.AP Position */ -#define MPU_RASR_AP_Msk (0x7UL << MPU_RASR_AP_Pos) /*!< MPU RASR: ATTRS.AP Mask */ - -#define MPU_RASR_TEX_Pos 19U /*!< MPU RASR: ATTRS.TEX Position */ -#define MPU_RASR_TEX_Msk (0x7UL << MPU_RASR_TEX_Pos) /*!< MPU RASR: ATTRS.TEX Mask */ - -#define MPU_RASR_S_Pos 18U /*!< MPU RASR: ATTRS.S Position */ -#define MPU_RASR_S_Msk (1UL << MPU_RASR_S_Pos) /*!< MPU RASR: ATTRS.S Mask */ - -#define MPU_RASR_C_Pos 17U /*!< MPU RASR: ATTRS.C Position */ -#define MPU_RASR_C_Msk (1UL << MPU_RASR_C_Pos) /*!< MPU RASR: ATTRS.C Mask */ - -#define MPU_RASR_B_Pos 16U /*!< MPU RASR: ATTRS.B Position */ -#define MPU_RASR_B_Msk (1UL << MPU_RASR_B_Pos) /*!< MPU RASR: ATTRS.B Mask */ - -#define MPU_RASR_SRD_Pos 8U /*!< MPU RASR: Sub-Region Disable Position */ -#define MPU_RASR_SRD_Msk (0xFFUL << MPU_RASR_SRD_Pos) /*!< MPU RASR: Sub-Region Disable Mask */ - -#define MPU_RASR_SIZE_Pos 1U /*!< MPU RASR: Region Size Field Position */ -#define MPU_RASR_SIZE_Msk (0x1FUL << MPU_RASR_SIZE_Pos) /*!< MPU RASR: Region Size Field Mask */ - -#define MPU_RASR_ENABLE_Pos 0U /*!< MPU RASR: Region enable bit Position */ -#define MPU_RASR_ENABLE_Msk (1UL /*<< MPU_RASR_ENABLE_Pos*/) /*!< MPU RASR: Region enable bit Disable Mask */ - -/*@} end of group CMSIS_MPU */ -#endif - - -/** - \ingroup CMSIS_core_register - \defgroup CMSIS_CoreDebug Core Debug Registers (CoreDebug) - \brief SC000 Core Debug Registers (DCB registers, SHCSR, and DFSR) are only accessible over DAP and not via processor. - Therefore they are not covered by the SC000 header file. - @{ - */ -/*@} end of group CMSIS_CoreDebug */ - - -/** - \ingroup CMSIS_core_register - \defgroup CMSIS_core_bitfield Core register bit field macros - \brief Macros for use with bit field definitions (xxx_Pos, xxx_Msk). - @{ - */ - -/** - \brief Mask and shift a bit field value for use in a register bit range. - \param[in] field Name of the register bit field. - \param[in] value Value of the bit field. - \return Masked and shifted value. -*/ -#define _VAL2FLD(field, value) ((value << field ## _Pos) & field ## _Msk) - -/** - \brief Mask and shift a register value to extract a bit filed value. - \param[in] field Name of the register bit field. - \param[in] value Value of register. - \return Masked and shifted bit field value. -*/ -#define _FLD2VAL(field, value) ((value & field ## _Msk) >> field ## _Pos) - -/*@} end of group CMSIS_core_bitfield */ - - -/** - \ingroup CMSIS_core_register - \defgroup CMSIS_core_base Core Definitions - \brief Definitions for base addresses, unions, and structures. - @{ - */ - -/* Memory mapping of SC000 Hardware */ -#define SCS_BASE (0xE000E000UL) /*!< System Control Space Base Address */ -#define SysTick_BASE (SCS_BASE + 0x0010UL) /*!< SysTick Base Address */ -#define NVIC_BASE (SCS_BASE + 0x0100UL) /*!< NVIC Base Address */ -#define SCB_BASE (SCS_BASE + 0x0D00UL) /*!< System Control Block Base Address */ - -#define SCnSCB ((SCnSCB_Type *) SCS_BASE ) /*!< System control Register not in SCB */ -#define SCB ((SCB_Type *) SCB_BASE ) /*!< SCB configuration struct */ -#define SysTick ((SysTick_Type *) SysTick_BASE ) /*!< SysTick configuration struct */ -#define NVIC ((NVIC_Type *) NVIC_BASE ) /*!< NVIC configuration struct */ - -#if (__MPU_PRESENT == 1U) - #define MPU_BASE (SCS_BASE + 0x0D90UL) /*!< Memory Protection Unit */ - #define MPU ((MPU_Type *) MPU_BASE ) /*!< Memory Protection Unit */ -#endif - -/*@} */ - - - -/******************************************************************************* - * Hardware Abstraction Layer - Core Function Interface contains: - - Core NVIC Functions - - Core SysTick Functions - - Core Register Access Functions - ******************************************************************************/ -/** - \defgroup CMSIS_Core_FunctionInterface Functions and Instructions Reference -*/ - - - -/* ########################## NVIC functions #################################### */ -/** - \ingroup CMSIS_Core_FunctionInterface - \defgroup CMSIS_Core_NVICFunctions NVIC Functions - \brief Functions that manage interrupts and exceptions via the NVIC. - @{ - */ - -/* Interrupt Priorities are WORD accessible only under ARMv6M */ -/* The following MACROS handle generation of the register offset and byte masks */ -#define _BIT_SHIFT(IRQn) ( ((((uint32_t)(int32_t)(IRQn)) ) & 0x03UL) * 8UL) -#define _SHP_IDX(IRQn) ( (((((uint32_t)(int32_t)(IRQn)) & 0x0FUL)-8UL) >> 2UL) ) -#define _IP_IDX(IRQn) ( (((uint32_t)(int32_t)(IRQn)) >> 2UL) ) - - -/** - \brief Enable External Interrupt - \details Enables a device-specific interrupt in the NVIC interrupt controller. - \param [in] IRQn External interrupt number. Value cannot be negative. - */ -__STATIC_INLINE void NVIC_EnableIRQ(IRQn_Type IRQn) -{ - NVIC->ISER[0U] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL)); -} - - -/** - \brief Disable External Interrupt - \details Disables a device-specific interrupt in the NVIC interrupt controller. - \param [in] IRQn External interrupt number. Value cannot be negative. - */ -__STATIC_INLINE void NVIC_DisableIRQ(IRQn_Type IRQn) -{ - NVIC->ICER[0U] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL)); -} - - -/** - \brief Get Pending Interrupt - \details Reads the pending register in the NVIC and returns the pending bit for the specified interrupt. - \param [in] IRQn Interrupt number. - \return 0 Interrupt status is not pending. - \return 1 Interrupt status is pending. - */ -__STATIC_INLINE uint32_t NVIC_GetPendingIRQ(IRQn_Type IRQn) -{ - return((uint32_t)(((NVIC->ISPR[0U] & (1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); -} - - -/** - \brief Set Pending Interrupt - \details Sets the pending bit of an external interrupt. - \param [in] IRQn Interrupt number. Value cannot be negative. - */ -__STATIC_INLINE void NVIC_SetPendingIRQ(IRQn_Type IRQn) -{ - NVIC->ISPR[0U] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL)); -} - - -/** - \brief Clear Pending Interrupt - \details Clears the pending bit of an external interrupt. - \param [in] IRQn External interrupt number. Value cannot be negative. - */ -__STATIC_INLINE void NVIC_ClearPendingIRQ(IRQn_Type IRQn) -{ - NVIC->ICPR[0U] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL)); -} - - -/** - \brief Set Interrupt Priority - \details Sets the priority of an interrupt. - \note The priority cannot be set for every core interrupt. - \param [in] IRQn Interrupt number. - \param [in] priority Priority to set. - */ -__STATIC_INLINE void NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority) -{ - if ((int32_t)(IRQn) < 0) - { - SCB->SHP[_SHP_IDX(IRQn)] = ((uint32_t)(SCB->SHP[_SHP_IDX(IRQn)] & ~(0xFFUL << _BIT_SHIFT(IRQn))) | - (((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL) << _BIT_SHIFT(IRQn))); - } - else - { - NVIC->IP[_IP_IDX(IRQn)] = ((uint32_t)(NVIC->IP[_IP_IDX(IRQn)] & ~(0xFFUL << _BIT_SHIFT(IRQn))) | - (((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL) << _BIT_SHIFT(IRQn))); - } -} - - -/** - \brief Get Interrupt Priority - \details Reads the priority of an interrupt. - The interrupt number can be positive to specify an external (device specific) interrupt, - or negative to specify an internal (core) interrupt. - \param [in] IRQn Interrupt number. - \return Interrupt Priority. - Value is aligned automatically to the implemented priority bits of the microcontroller. - */ -__STATIC_INLINE uint32_t NVIC_GetPriority(IRQn_Type IRQn) -{ - - if ((int32_t)(IRQn) < 0) - { - return((uint32_t)(((SCB->SHP[_SHP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) & (uint32_t)0xFFUL) >> (8U - __NVIC_PRIO_BITS))); - } - else - { - return((uint32_t)(((NVIC->IP[ _IP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) & (uint32_t)0xFFUL) >> (8U - __NVIC_PRIO_BITS))); - } -} - - -/** - \brief System Reset - \details Initiates a system reset request to reset the MCU. - */ -__STATIC_INLINE void NVIC_SystemReset(void) -{ - __DSB(); /* Ensure all outstanding memory accesses included - buffered write are completed before reset */ - SCB->AIRCR = ((0x5FAUL << SCB_AIRCR_VECTKEY_Pos) | - SCB_AIRCR_SYSRESETREQ_Msk); - __DSB(); /* Ensure completion of memory access */ - - for(;;) /* wait until reset */ - { - __NOP(); - } -} - -/*@} end of CMSIS_Core_NVICFunctions */ - - - -/* ################################## SysTick function ############################################ */ -/** - \ingroup CMSIS_Core_FunctionInterface - \defgroup CMSIS_Core_SysTickFunctions SysTick Functions - \brief Functions that configure the System. - @{ - */ - -#if (__Vendor_SysTickConfig == 0U) - -/** - \brief System Tick Configuration - \details Initializes the System Timer and its interrupt, and starts the System Tick Timer. - Counter is in free running mode to generate periodic interrupts. - \param [in] ticks Number of ticks between two interrupts. - \return 0 Function succeeded. - \return 1 Function failed. - \note When the variable __Vendor_SysTickConfig is set to 1, then the - function SysTick_Config is not included. In this case, the file device.h - must contain a vendor-specific implementation of this function. - */ -__STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks) -{ - if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk) - { - return (1UL); /* Reload value impossible */ - } - - SysTick->LOAD = (uint32_t)(ticks - 1UL); /* set reload register */ - NVIC_SetPriority (SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */ - SysTick->VAL = 0UL; /* Load the SysTick Counter Value */ - SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk | - SysTick_CTRL_TICKINT_Msk | - SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */ - return (0UL); /* Function successful */ -} - -#endif - -/*@} end of CMSIS_Core_SysTickFunctions */ - - - - -#ifdef __cplusplus -} -#endif - -#endif /* __CORE_SC000_H_DEPENDANT */ - -#endif /* __CMSIS_GENERIC */ diff --git a/bsp/essemi/es32f0334/libraries/CMSIS/Include/core_sc300.h b/bsp/essemi/es32f0334/libraries/CMSIS/Include/core_sc300.h deleted file mode 100644 index 8bd18aa318..0000000000 --- a/bsp/essemi/es32f0334/libraries/CMSIS/Include/core_sc300.h +++ /dev/null @@ -1,1745 +0,0 @@ -/**************************************************************************//** - * @file core_sc300.h - * @brief CMSIS SC300 Core Peripheral Access Layer Header File - * @version V4.30 - * @date 20. October 2015 - ******************************************************************************/ -/* Copyright (c) 2009 - 2015 ARM LIMITED - - All rights reserved. - Redistribution and use in source and binary forms, with or without - modification, are permitted provided that the following conditions are met: - - Redistributions of source code must retain the above copyright - notice, this list of conditions and the following disclaimer. - - Redistributions in binary form must reproduce the above copyright - notice, this list of conditions and the following disclaimer in the - documentation and/or other materials provided with the distribution. - - Neither the name of ARM nor the names of its contributors may be used - to endorse or promote products derived from this software without - specific prior written permission. - * - THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" - AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE - ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE - LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR - CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF - SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS - INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN - CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) - ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE - POSSIBILITY OF SUCH DAMAGE. - ---------------------------------------------------------------------------*/ - - -#if defined ( __ICCARM__ ) - #pragma system_include /* treat file as system include file for MISRA check */ -#elif defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) - #pragma clang system_header /* treat file as system include file */ -#endif - -#ifndef __CORE_SC300_H_GENERIC -#define __CORE_SC300_H_GENERIC - -#include - -#ifdef __cplusplus - extern "C" { -#endif - -/** - \page CMSIS_MISRA_Exceptions MISRA-C:2004 Compliance Exceptions - CMSIS violates the following MISRA-C:2004 rules: - - \li Required Rule 8.5, object/function definition in header file.
- Function definitions in header files are used to allow 'inlining'. - - \li Required Rule 18.4, declaration of union type or object of union type: '{...}'.
- Unions are used for effective representation of core registers. - - \li Advisory Rule 19.7, Function-like macro defined.
- Function-like macros are used to allow more efficient code. - */ - - -/******************************************************************************* - * CMSIS definitions - ******************************************************************************/ -/** - \ingroup SC3000 - @{ - */ - -/* CMSIS SC300 definitions */ -#define __SC300_CMSIS_VERSION_MAIN (0x04U) /*!< [31:16] CMSIS HAL main version */ -#define __SC300_CMSIS_VERSION_SUB (0x1EU) /*!< [15:0] CMSIS HAL sub version */ -#define __SC300_CMSIS_VERSION ((__SC300_CMSIS_VERSION_MAIN << 16U) | \ - __SC300_CMSIS_VERSION_SUB ) /*!< CMSIS HAL version number */ - -#define __CORTEX_SC (300U) /*!< Cortex secure core */ - - -#if defined ( __CC_ARM ) - #define __ASM __asm /*!< asm keyword for ARM Compiler */ - #define __INLINE __inline /*!< inline keyword for ARM Compiler */ - #define __STATIC_INLINE static __inline - -#elif defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) - #define __ASM __asm /*!< asm keyword for ARM Compiler */ - #define __INLINE __inline /*!< inline keyword for ARM Compiler */ - #define __STATIC_INLINE static __inline - -#elif defined ( __GNUC__ ) - #define __ASM __asm /*!< asm keyword for GNU Compiler */ - #define __INLINE inline /*!< inline keyword for GNU Compiler */ - #define __STATIC_INLINE static inline - -#elif defined ( __ICCARM__ ) - #define __ASM __asm /*!< asm keyword for IAR Compiler */ - #define __INLINE inline /*!< inline keyword for IAR Compiler. Only available in High optimization mode! */ - #define __STATIC_INLINE static inline - -#elif defined ( __TMS470__ ) - #define __ASM __asm /*!< asm keyword for TI CCS Compiler */ - #define __STATIC_INLINE static inline - -#elif defined ( __TASKING__ ) - #define __ASM __asm /*!< asm keyword for TASKING Compiler */ - #define __INLINE inline /*!< inline keyword for TASKING Compiler */ - #define __STATIC_INLINE static inline - -#elif defined ( __CSMC__ ) - #define __packed - #define __ASM _asm /*!< asm keyword for COSMIC Compiler */ - #define __INLINE inline /*!< inline keyword for COSMIC Compiler. Use -pc99 on compile line */ - #define __STATIC_INLINE static inline - -#else - #error Unknown compiler -#endif - -/** __FPU_USED indicates whether an FPU is used or not. - This core does not support an FPU at all -*/ -#define __FPU_USED 0U - -#if defined ( __CC_ARM ) - #if defined __TARGET_FPU_VFP - #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" - #endif - -#elif defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) - #if defined __ARM_PCS_VFP - #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" - #endif - -#elif defined ( __GNUC__ ) - #if defined (__VFP_FP__) && !defined(__SOFTFP__) - #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" - #endif - -#elif defined ( __ICCARM__ ) - #if defined __ARMVFP__ - #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" - #endif - -#elif defined ( __TMS470__ ) - #if defined __TI_VFP_SUPPORT__ - #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" - #endif - -#elif defined ( __TASKING__ ) - #if defined __FPU_VFP__ - #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" - #endif - -#elif defined ( __CSMC__ ) - #if ( __CSMC__ & 0x400U) - #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" - #endif - -#endif - -#include "core_cmInstr.h" /* Core Instruction Access */ -#include "core_cmFunc.h" /* Core Function Access */ - -#ifdef __cplusplus -} -#endif - -#endif /* __CORE_SC300_H_GENERIC */ - -#ifndef __CMSIS_GENERIC - -#ifndef __CORE_SC300_H_DEPENDANT -#define __CORE_SC300_H_DEPENDANT - -#ifdef __cplusplus - extern "C" { -#endif - -/* check device defines and use defaults */ -#if defined __CHECK_DEVICE_DEFINES - #ifndef __SC300_REV - #define __SC300_REV 0x0000U - #warning "__SC300_REV not defined in device header file; using default!" - #endif - - #ifndef __MPU_PRESENT - #define __MPU_PRESENT 0U - #warning "__MPU_PRESENT not defined in device header file; using default!" - #endif - - #ifndef __NVIC_PRIO_BITS - #define __NVIC_PRIO_BITS 4U - #warning "__NVIC_PRIO_BITS not defined in device header file; using default!" - #endif - - #ifndef __Vendor_SysTickConfig - #define __Vendor_SysTickConfig 0U - #warning "__Vendor_SysTickConfig not defined in device header file; using default!" - #endif -#endif - -/* IO definitions (access restrictions to peripheral registers) */ -/** - \defgroup CMSIS_glob_defs CMSIS Global Defines - - IO Type Qualifiers are used - \li to specify the access to peripheral variables. - \li for automatic generation of peripheral register debug information. -*/ -#ifdef __cplusplus - #define __I volatile /*!< Defines 'read only' permissions */ -#else - #define __I volatile const /*!< Defines 'read only' permissions */ -#endif -#define __O volatile /*!< Defines 'write only' permissions */ -#define __IO volatile /*!< Defines 'read / write' permissions */ - -/* following defines should be used for structure members */ -#define __IM volatile const /*! Defines 'read only' structure member permissions */ -#define __OM volatile /*! Defines 'write only' structure member permissions */ -#define __IOM volatile /*! Defines 'read / write' structure member permissions */ - -/*@} end of group SC300 */ - - - -/******************************************************************************* - * Register Abstraction - Core Register contain: - - Core Register - - Core NVIC Register - - Core SCB Register - - Core SysTick Register - - Core Debug Register - - Core MPU Register - ******************************************************************************/ -/** - \defgroup CMSIS_core_register Defines and Type Definitions - \brief Type definitions and defines for Cortex-M processor based devices. -*/ - -/** - \ingroup CMSIS_core_register - \defgroup CMSIS_CORE Status and Control Registers - \brief Core Register type definitions. - @{ - */ - -/** - \brief Union type to access the Application Program Status Register (APSR). - */ -typedef union -{ - struct - { - uint32_t _reserved0:27; /*!< bit: 0..26 Reserved */ - uint32_t Q:1; /*!< bit: 27 Saturation condition flag */ - uint32_t V:1; /*!< bit: 28 Overflow condition code flag */ - uint32_t C:1; /*!< bit: 29 Carry condition code flag */ - uint32_t Z:1; /*!< bit: 30 Zero condition code flag */ - uint32_t N:1; /*!< bit: 31 Negative condition code flag */ - } b; /*!< Structure used for bit access */ - uint32_t w; /*!< Type used for word access */ -} APSR_Type; - -/* APSR Register Definitions */ -#define APSR_N_Pos 31U /*!< APSR: N Position */ -#define APSR_N_Msk (1UL << APSR_N_Pos) /*!< APSR: N Mask */ - -#define APSR_Z_Pos 30U /*!< APSR: Z Position */ -#define APSR_Z_Msk (1UL << APSR_Z_Pos) /*!< APSR: Z Mask */ - -#define APSR_C_Pos 29U /*!< APSR: C Position */ -#define APSR_C_Msk (1UL << APSR_C_Pos) /*!< APSR: C Mask */ - -#define APSR_V_Pos 28U /*!< APSR: V Position */ -#define APSR_V_Msk (1UL << APSR_V_Pos) /*!< APSR: V Mask */ - -#define APSR_Q_Pos 27U /*!< APSR: Q Position */ -#define APSR_Q_Msk (1UL << APSR_Q_Pos) /*!< APSR: Q Mask */ - - -/** - \brief Union type to access the Interrupt Program Status Register (IPSR). - */ -typedef union -{ - struct - { - uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */ - uint32_t _reserved0:23; /*!< bit: 9..31 Reserved */ - } b; /*!< Structure used for bit access */ - uint32_t w; /*!< Type used for word access */ -} IPSR_Type; - -/* IPSR Register Definitions */ -#define IPSR_ISR_Pos 0U /*!< IPSR: ISR Position */ -#define IPSR_ISR_Msk (0x1FFUL /*<< IPSR_ISR_Pos*/) /*!< IPSR: ISR Mask */ - - -/** - \brief Union type to access the Special-Purpose Program Status Registers (xPSR). - */ -typedef union -{ - struct - { - uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */ - uint32_t _reserved0:15; /*!< bit: 9..23 Reserved */ - uint32_t T:1; /*!< bit: 24 Thumb bit (read 0) */ - uint32_t IT:2; /*!< bit: 25..26 saved IT state (read 0) */ - uint32_t Q:1; /*!< bit: 27 Saturation condition flag */ - uint32_t V:1; /*!< bit: 28 Overflow condition code flag */ - uint32_t C:1; /*!< bit: 29 Carry condition code flag */ - uint32_t Z:1; /*!< bit: 30 Zero condition code flag */ - uint32_t N:1; /*!< bit: 31 Negative condition code flag */ - } b; /*!< Structure used for bit access */ - uint32_t w; /*!< Type used for word access */ -} xPSR_Type; - -/* xPSR Register Definitions */ -#define xPSR_N_Pos 31U /*!< xPSR: N Position */ -#define xPSR_N_Msk (1UL << xPSR_N_Pos) /*!< xPSR: N Mask */ - -#define xPSR_Z_Pos 30U /*!< xPSR: Z Position */ -#define xPSR_Z_Msk (1UL << xPSR_Z_Pos) /*!< xPSR: Z Mask */ - -#define xPSR_C_Pos 29U /*!< xPSR: C Position */ -#define xPSR_C_Msk (1UL << xPSR_C_Pos) /*!< xPSR: C Mask */ - -#define xPSR_V_Pos 28U /*!< xPSR: V Position */ -#define xPSR_V_Msk (1UL << xPSR_V_Pos) /*!< xPSR: V Mask */ - -#define xPSR_Q_Pos 27U /*!< xPSR: Q Position */ -#define xPSR_Q_Msk (1UL << xPSR_Q_Pos) /*!< xPSR: Q Mask */ - -#define xPSR_IT_Pos 25U /*!< xPSR: IT Position */ -#define xPSR_IT_Msk (3UL << xPSR_IT_Pos) /*!< xPSR: IT Mask */ - -#define xPSR_T_Pos 24U /*!< xPSR: T Position */ -#define xPSR_T_Msk (1UL << xPSR_T_Pos) /*!< xPSR: T Mask */ - -#define xPSR_ISR_Pos 0U /*!< xPSR: ISR Position */ -#define xPSR_ISR_Msk (0x1FFUL /*<< xPSR_ISR_Pos*/) /*!< xPSR: ISR Mask */ - - -/** - \brief Union type to access the Control Registers (CONTROL). - */ -typedef union -{ - struct - { - uint32_t nPRIV:1; /*!< bit: 0 Execution privilege in Thread mode */ - uint32_t SPSEL:1; /*!< bit: 1 Stack to be used */ - uint32_t _reserved1:30; /*!< bit: 2..31 Reserved */ - } b; /*!< Structure used for bit access */ - uint32_t w; /*!< Type used for word access */ -} CONTROL_Type; - -/* CONTROL Register Definitions */ -#define CONTROL_SPSEL_Pos 1U /*!< CONTROL: SPSEL Position */ -#define CONTROL_SPSEL_Msk (1UL << CONTROL_SPSEL_Pos) /*!< CONTROL: SPSEL Mask */ - -#define CONTROL_nPRIV_Pos 0U /*!< CONTROL: nPRIV Position */ -#define CONTROL_nPRIV_Msk (1UL /*<< CONTROL_nPRIV_Pos*/) /*!< CONTROL: nPRIV Mask */ - -/*@} end of group CMSIS_CORE */ - - -/** - \ingroup CMSIS_core_register - \defgroup CMSIS_NVIC Nested Vectored Interrupt Controller (NVIC) - \brief Type definitions for the NVIC Registers - @{ - */ - -/** - \brief Structure type to access the Nested Vectored Interrupt Controller (NVIC). - */ -typedef struct -{ - __IOM uint32_t ISER[8U]; /*!< Offset: 0x000 (R/W) Interrupt Set Enable Register */ - uint32_t RESERVED0[24U]; - __IOM uint32_t ICER[8U]; /*!< Offset: 0x080 (R/W) Interrupt Clear Enable Register */ - uint32_t RSERVED1[24U]; - __IOM uint32_t ISPR[8U]; /*!< Offset: 0x100 (R/W) Interrupt Set Pending Register */ - uint32_t RESERVED2[24U]; - __IOM uint32_t ICPR[8U]; /*!< Offset: 0x180 (R/W) Interrupt Clear Pending Register */ - uint32_t RESERVED3[24U]; - __IOM uint32_t IABR[8U]; /*!< Offset: 0x200 (R/W) Interrupt Active bit Register */ - uint32_t RESERVED4[56U]; - __IOM uint8_t IP[240U]; /*!< Offset: 0x300 (R/W) Interrupt Priority Register (8Bit wide) */ - uint32_t RESERVED5[644U]; - __OM uint32_t STIR; /*!< Offset: 0xE00 ( /W) Software Trigger Interrupt Register */ -} NVIC_Type; - -/* Software Triggered Interrupt Register Definitions */ -#define NVIC_STIR_INTID_Pos 0U /*!< STIR: INTLINESNUM Position */ -#define NVIC_STIR_INTID_Msk (0x1FFUL /*<< NVIC_STIR_INTID_Pos*/) /*!< STIR: INTLINESNUM Mask */ - -/*@} end of group CMSIS_NVIC */ - - -/** - \ingroup CMSIS_core_register - \defgroup CMSIS_SCB System Control Block (SCB) - \brief Type definitions for the System Control Block Registers - @{ - */ - -/** - \brief Structure type to access the System Control Block (SCB). - */ -typedef struct -{ - __IM uint32_t CPUID; /*!< Offset: 0x000 (R/ ) CPUID Base Register */ - __IOM uint32_t ICSR; /*!< Offset: 0x004 (R/W) Interrupt Control and State Register */ - __IOM uint32_t VTOR; /*!< Offset: 0x008 (R/W) Vector Table Offset Register */ - __IOM uint32_t AIRCR; /*!< Offset: 0x00C (R/W) Application Interrupt and Reset Control Register */ - __IOM uint32_t SCR; /*!< Offset: 0x010 (R/W) System Control Register */ - __IOM uint32_t CCR; /*!< Offset: 0x014 (R/W) Configuration Control Register */ - __IOM uint8_t SHP[12U]; /*!< Offset: 0x018 (R/W) System Handlers Priority Registers (4-7, 8-11, 12-15) */ - __IOM uint32_t SHCSR; /*!< Offset: 0x024 (R/W) System Handler Control and State Register */ - __IOM uint32_t CFSR; /*!< Offset: 0x028 (R/W) Configurable Fault Status Register */ - __IOM uint32_t HFSR; /*!< Offset: 0x02C (R/W) HardFault Status Register */ - __IOM uint32_t DFSR; /*!< Offset: 0x030 (R/W) Debug Fault Status Register */ - __IOM uint32_t MMFAR; /*!< Offset: 0x034 (R/W) MemManage Fault Address Register */ - __IOM uint32_t BFAR; /*!< Offset: 0x038 (R/W) BusFault Address Register */ - __IOM uint32_t AFSR; /*!< Offset: 0x03C (R/W) Auxiliary Fault Status Register */ - __IM uint32_t PFR[2U]; /*!< Offset: 0x040 (R/ ) Processor Feature Register */ - __IM uint32_t DFR; /*!< Offset: 0x048 (R/ ) Debug Feature Register */ - __IM uint32_t ADR; /*!< Offset: 0x04C (R/ ) Auxiliary Feature Register */ - __IM uint32_t MMFR[4U]; /*!< Offset: 0x050 (R/ ) Memory Model Feature Register */ - __IM uint32_t ISAR[5U]; /*!< Offset: 0x060 (R/ ) Instruction Set Attributes Register */ - uint32_t RESERVED0[5U]; - __IOM uint32_t CPACR; /*!< Offset: 0x088 (R/W) Coprocessor Access Control Register */ - uint32_t RESERVED1[129U]; - __IOM uint32_t SFCR; /*!< Offset: 0x290 (R/W) Security Features Control Register */ -} SCB_Type; - -/* SCB CPUID Register Definitions */ -#define SCB_CPUID_IMPLEMENTER_Pos 24U /*!< SCB CPUID: IMPLEMENTER Position */ -#define SCB_CPUID_IMPLEMENTER_Msk (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos) /*!< SCB CPUID: IMPLEMENTER Mask */ - -#define SCB_CPUID_VARIANT_Pos 20U /*!< SCB CPUID: VARIANT Position */ -#define SCB_CPUID_VARIANT_Msk (0xFUL << SCB_CPUID_VARIANT_Pos) /*!< SCB CPUID: VARIANT Mask */ - -#define SCB_CPUID_ARCHITECTURE_Pos 16U /*!< SCB CPUID: ARCHITECTURE Position */ -#define SCB_CPUID_ARCHITECTURE_Msk (0xFUL << SCB_CPUID_ARCHITECTURE_Pos) /*!< SCB CPUID: ARCHITECTURE Mask */ - -#define SCB_CPUID_PARTNO_Pos 4U /*!< SCB CPUID: PARTNO Position */ -#define SCB_CPUID_PARTNO_Msk (0xFFFUL << SCB_CPUID_PARTNO_Pos) /*!< SCB CPUID: PARTNO Mask */ - -#define SCB_CPUID_REVISION_Pos 0U /*!< SCB CPUID: REVISION Position */ -#define SCB_CPUID_REVISION_Msk (0xFUL /*<< SCB_CPUID_REVISION_Pos*/) /*!< SCB CPUID: REVISION Mask */ - -/* SCB Interrupt Control State Register Definitions */ -#define SCB_ICSR_NMIPENDSET_Pos 31U /*!< SCB ICSR: NMIPENDSET Position */ -#define SCB_ICSR_NMIPENDSET_Msk (1UL << SCB_ICSR_NMIPENDSET_Pos) /*!< SCB ICSR: NMIPENDSET Mask */ - -#define SCB_ICSR_PENDSVSET_Pos 28U /*!< SCB ICSR: PENDSVSET Position */ -#define SCB_ICSR_PENDSVSET_Msk (1UL << SCB_ICSR_PENDSVSET_Pos) /*!< SCB ICSR: PENDSVSET Mask */ - -#define SCB_ICSR_PENDSVCLR_Pos 27U /*!< SCB ICSR: PENDSVCLR Position */ -#define SCB_ICSR_PENDSVCLR_Msk (1UL << SCB_ICSR_PENDSVCLR_Pos) /*!< SCB ICSR: PENDSVCLR Mask */ - -#define SCB_ICSR_PENDSTSET_Pos 26U /*!< SCB ICSR: PENDSTSET Position */ -#define SCB_ICSR_PENDSTSET_Msk (1UL << SCB_ICSR_PENDSTSET_Pos) /*!< SCB ICSR: PENDSTSET Mask */ - -#define SCB_ICSR_PENDSTCLR_Pos 25U /*!< SCB ICSR: PENDSTCLR Position */ -#define SCB_ICSR_PENDSTCLR_Msk (1UL << SCB_ICSR_PENDSTCLR_Pos) /*!< SCB ICSR: PENDSTCLR Mask */ - -#define SCB_ICSR_ISRPREEMPT_Pos 23U /*!< SCB ICSR: ISRPREEMPT Position */ -#define SCB_ICSR_ISRPREEMPT_Msk (1UL << SCB_ICSR_ISRPREEMPT_Pos) /*!< SCB ICSR: ISRPREEMPT Mask */ - -#define SCB_ICSR_ISRPENDING_Pos 22U /*!< SCB ICSR: ISRPENDING Position */ -#define SCB_ICSR_ISRPENDING_Msk (1UL << SCB_ICSR_ISRPENDING_Pos) /*!< SCB ICSR: ISRPENDING Mask */ - -#define SCB_ICSR_VECTPENDING_Pos 12U /*!< SCB ICSR: VECTPENDING Position */ -#define SCB_ICSR_VECTPENDING_Msk (0x1FFUL << SCB_ICSR_VECTPENDING_Pos) /*!< SCB ICSR: VECTPENDING Mask */ - -#define SCB_ICSR_RETTOBASE_Pos 11U /*!< SCB ICSR: RETTOBASE Position */ -#define SCB_ICSR_RETTOBASE_Msk (1UL << SCB_ICSR_RETTOBASE_Pos) /*!< SCB ICSR: RETTOBASE Mask */ - -#define SCB_ICSR_VECTACTIVE_Pos 0U /*!< SCB ICSR: VECTACTIVE Position */ -#define SCB_ICSR_VECTACTIVE_Msk (0x1FFUL /*<< SCB_ICSR_VECTACTIVE_Pos*/) /*!< SCB ICSR: VECTACTIVE Mask */ - -/* SCB Vector Table Offset Register Definitions */ -#define SCB_VTOR_TBLBASE_Pos 29U /*!< SCB VTOR: TBLBASE Position */ -#define SCB_VTOR_TBLBASE_Msk (1UL << SCB_VTOR_TBLBASE_Pos) /*!< SCB VTOR: TBLBASE Mask */ - -#define SCB_VTOR_TBLOFF_Pos 7U /*!< SCB VTOR: TBLOFF Position */ -#define SCB_VTOR_TBLOFF_Msk (0x3FFFFFUL << SCB_VTOR_TBLOFF_Pos) /*!< SCB VTOR: TBLOFF Mask */ - -/* SCB Application Interrupt and Reset Control Register Definitions */ -#define SCB_AIRCR_VECTKEY_Pos 16U /*!< SCB AIRCR: VECTKEY Position */ -#define SCB_AIRCR_VECTKEY_Msk (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos) /*!< SCB AIRCR: VECTKEY Mask */ - -#define SCB_AIRCR_VECTKEYSTAT_Pos 16U /*!< SCB AIRCR: VECTKEYSTAT Position */ -#define SCB_AIRCR_VECTKEYSTAT_Msk (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos) /*!< SCB AIRCR: VECTKEYSTAT Mask */ - -#define SCB_AIRCR_ENDIANESS_Pos 15U /*!< SCB AIRCR: ENDIANESS Position */ -#define SCB_AIRCR_ENDIANESS_Msk (1UL << SCB_AIRCR_ENDIANESS_Pos) /*!< SCB AIRCR: ENDIANESS Mask */ - -#define SCB_AIRCR_PRIGROUP_Pos 8U /*!< SCB AIRCR: PRIGROUP Position */ -#define SCB_AIRCR_PRIGROUP_Msk (7UL << SCB_AIRCR_PRIGROUP_Pos) /*!< SCB AIRCR: PRIGROUP Mask */ - -#define SCB_AIRCR_SYSRESETREQ_Pos 2U /*!< SCB AIRCR: SYSRESETREQ Position */ -#define SCB_AIRCR_SYSRESETREQ_Msk (1UL << SCB_AIRCR_SYSRESETREQ_Pos) /*!< SCB AIRCR: SYSRESETREQ Mask */ - -#define SCB_AIRCR_VECTCLRACTIVE_Pos 1U /*!< SCB AIRCR: VECTCLRACTIVE Position */ -#define SCB_AIRCR_VECTCLRACTIVE_Msk (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos) /*!< SCB AIRCR: VECTCLRACTIVE Mask */ - -#define SCB_AIRCR_VECTRESET_Pos 0U /*!< SCB AIRCR: VECTRESET Position */ -#define SCB_AIRCR_VECTRESET_Msk (1UL /*<< SCB_AIRCR_VECTRESET_Pos*/) /*!< SCB AIRCR: VECTRESET Mask */ - -/* SCB System Control Register Definitions */ -#define SCB_SCR_SEVONPEND_Pos 4U /*!< SCB SCR: SEVONPEND Position */ -#define SCB_SCR_SEVONPEND_Msk (1UL << SCB_SCR_SEVONPEND_Pos) /*!< SCB SCR: SEVONPEND Mask */ - -#define SCB_SCR_SLEEPDEEP_Pos 2U /*!< SCB SCR: SLEEPDEEP Position */ -#define SCB_SCR_SLEEPDEEP_Msk (1UL << SCB_SCR_SLEEPDEEP_Pos) /*!< SCB SCR: SLEEPDEEP Mask */ - -#define SCB_SCR_SLEEPONEXIT_Pos 1U /*!< SCB SCR: SLEEPONEXIT Position */ -#define SCB_SCR_SLEEPONEXIT_Msk (1UL << SCB_SCR_SLEEPONEXIT_Pos) /*!< SCB SCR: SLEEPONEXIT Mask */ - -/* SCB Configuration Control Register Definitions */ -#define SCB_CCR_STKALIGN_Pos 9U /*!< SCB CCR: STKALIGN Position */ -#define SCB_CCR_STKALIGN_Msk (1UL << SCB_CCR_STKALIGN_Pos) /*!< SCB CCR: STKALIGN Mask */ - -#define SCB_CCR_BFHFNMIGN_Pos 8U /*!< SCB CCR: BFHFNMIGN Position */ -#define SCB_CCR_BFHFNMIGN_Msk (1UL << SCB_CCR_BFHFNMIGN_Pos) /*!< SCB CCR: BFHFNMIGN Mask */ - -#define SCB_CCR_DIV_0_TRP_Pos 4U /*!< SCB CCR: DIV_0_TRP Position */ -#define SCB_CCR_DIV_0_TRP_Msk (1UL << SCB_CCR_DIV_0_TRP_Pos) /*!< SCB CCR: DIV_0_TRP Mask */ - -#define SCB_CCR_UNALIGN_TRP_Pos 3U /*!< SCB CCR: UNALIGN_TRP Position */ -#define SCB_CCR_UNALIGN_TRP_Msk (1UL << SCB_CCR_UNALIGN_TRP_Pos) /*!< SCB CCR: UNALIGN_TRP Mask */ - -#define SCB_CCR_USERSETMPEND_Pos 1U /*!< SCB CCR: USERSETMPEND Position */ -#define SCB_CCR_USERSETMPEND_Msk (1UL << SCB_CCR_USERSETMPEND_Pos) /*!< SCB CCR: USERSETMPEND Mask */ - -#define SCB_CCR_NONBASETHRDENA_Pos 0U /*!< SCB CCR: NONBASETHRDENA Position */ -#define SCB_CCR_NONBASETHRDENA_Msk (1UL /*<< SCB_CCR_NONBASETHRDENA_Pos*/) /*!< SCB CCR: NONBASETHRDENA Mask */ - -/* SCB System Handler Control and State Register Definitions */ -#define SCB_SHCSR_USGFAULTENA_Pos 18U /*!< SCB SHCSR: USGFAULTENA Position */ -#define SCB_SHCSR_USGFAULTENA_Msk (1UL << SCB_SHCSR_USGFAULTENA_Pos) /*!< SCB SHCSR: USGFAULTENA Mask */ - -#define SCB_SHCSR_BUSFAULTENA_Pos 17U /*!< SCB SHCSR: BUSFAULTENA Position */ -#define SCB_SHCSR_BUSFAULTENA_Msk (1UL << SCB_SHCSR_BUSFAULTENA_Pos) /*!< SCB SHCSR: BUSFAULTENA Mask */ - -#define SCB_SHCSR_MEMFAULTENA_Pos 16U /*!< SCB SHCSR: MEMFAULTENA Position */ -#define SCB_SHCSR_MEMFAULTENA_Msk (1UL << SCB_SHCSR_MEMFAULTENA_Pos) /*!< SCB SHCSR: MEMFAULTENA Mask */ - -#define SCB_SHCSR_SVCALLPENDED_Pos 15U /*!< SCB SHCSR: SVCALLPENDED Position */ -#define SCB_SHCSR_SVCALLPENDED_Msk (1UL << SCB_SHCSR_SVCALLPENDED_Pos) /*!< SCB SHCSR: SVCALLPENDED Mask */ - -#define SCB_SHCSR_BUSFAULTPENDED_Pos 14U /*!< SCB SHCSR: BUSFAULTPENDED Position */ -#define SCB_SHCSR_BUSFAULTPENDED_Msk (1UL << SCB_SHCSR_BUSFAULTPENDED_Pos) /*!< SCB SHCSR: BUSFAULTPENDED Mask */ - -#define SCB_SHCSR_MEMFAULTPENDED_Pos 13U /*!< SCB SHCSR: MEMFAULTPENDED Position */ -#define SCB_SHCSR_MEMFAULTPENDED_Msk (1UL << SCB_SHCSR_MEMFAULTPENDED_Pos) /*!< SCB SHCSR: MEMFAULTPENDED Mask */ - -#define SCB_SHCSR_USGFAULTPENDED_Pos 12U /*!< SCB SHCSR: USGFAULTPENDED Position */ -#define SCB_SHCSR_USGFAULTPENDED_Msk (1UL << SCB_SHCSR_USGFAULTPENDED_Pos) /*!< SCB SHCSR: USGFAULTPENDED Mask */ - -#define SCB_SHCSR_SYSTICKACT_Pos 11U /*!< SCB SHCSR: SYSTICKACT Position */ -#define SCB_SHCSR_SYSTICKACT_Msk (1UL << SCB_SHCSR_SYSTICKACT_Pos) /*!< SCB SHCSR: SYSTICKACT Mask */ - -#define SCB_SHCSR_PENDSVACT_Pos 10U /*!< SCB SHCSR: PENDSVACT Position */ -#define SCB_SHCSR_PENDSVACT_Msk (1UL << SCB_SHCSR_PENDSVACT_Pos) /*!< SCB SHCSR: PENDSVACT Mask */ - -#define SCB_SHCSR_MONITORACT_Pos 8U /*!< SCB SHCSR: MONITORACT Position */ -#define SCB_SHCSR_MONITORACT_Msk (1UL << SCB_SHCSR_MONITORACT_Pos) /*!< SCB SHCSR: MONITORACT Mask */ - -#define SCB_SHCSR_SVCALLACT_Pos 7U /*!< SCB SHCSR: SVCALLACT Position */ -#define SCB_SHCSR_SVCALLACT_Msk (1UL << SCB_SHCSR_SVCALLACT_Pos) /*!< SCB SHCSR: SVCALLACT Mask */ - -#define SCB_SHCSR_USGFAULTACT_Pos 3U /*!< SCB SHCSR: USGFAULTACT Position */ -#define SCB_SHCSR_USGFAULTACT_Msk (1UL << SCB_SHCSR_USGFAULTACT_Pos) /*!< SCB SHCSR: USGFAULTACT Mask */ - -#define SCB_SHCSR_BUSFAULTACT_Pos 1U /*!< SCB SHCSR: BUSFAULTACT Position */ -#define SCB_SHCSR_BUSFAULTACT_Msk (1UL << SCB_SHCSR_BUSFAULTACT_Pos) /*!< SCB SHCSR: BUSFAULTACT Mask */ - -#define SCB_SHCSR_MEMFAULTACT_Pos 0U /*!< SCB SHCSR: MEMFAULTACT Position */ -#define SCB_SHCSR_MEMFAULTACT_Msk (1UL /*<< SCB_SHCSR_MEMFAULTACT_Pos*/) /*!< SCB SHCSR: MEMFAULTACT Mask */ - -/* SCB Configurable Fault Status Register Definitions */ -#define SCB_CFSR_USGFAULTSR_Pos 16U /*!< SCB CFSR: Usage Fault Status Register Position */ -#define SCB_CFSR_USGFAULTSR_Msk (0xFFFFUL << SCB_CFSR_USGFAULTSR_Pos) /*!< SCB CFSR: Usage Fault Status Register Mask */ - -#define SCB_CFSR_BUSFAULTSR_Pos 8U /*!< SCB CFSR: Bus Fault Status Register Position */ -#define SCB_CFSR_BUSFAULTSR_Msk (0xFFUL << SCB_CFSR_BUSFAULTSR_Pos) /*!< SCB CFSR: Bus Fault Status Register Mask */ - -#define SCB_CFSR_MEMFAULTSR_Pos 0U /*!< SCB CFSR: Memory Manage Fault Status Register Position */ -#define SCB_CFSR_MEMFAULTSR_Msk (0xFFUL /*<< SCB_CFSR_MEMFAULTSR_Pos*/) /*!< SCB CFSR: Memory Manage Fault Status Register Mask */ - -/* SCB Hard Fault Status Register Definitions */ -#define SCB_HFSR_DEBUGEVT_Pos 31U /*!< SCB HFSR: DEBUGEVT Position */ -#define SCB_HFSR_DEBUGEVT_Msk (1UL << SCB_HFSR_DEBUGEVT_Pos) /*!< SCB HFSR: DEBUGEVT Mask */ - -#define SCB_HFSR_FORCED_Pos 30U /*!< SCB HFSR: FORCED Position */ -#define SCB_HFSR_FORCED_Msk (1UL << SCB_HFSR_FORCED_Pos) /*!< SCB HFSR: FORCED Mask */ - -#define SCB_HFSR_VECTTBL_Pos 1U /*!< SCB HFSR: VECTTBL Position */ -#define SCB_HFSR_VECTTBL_Msk (1UL << SCB_HFSR_VECTTBL_Pos) /*!< SCB HFSR: VECTTBL Mask */ - -/* SCB Debug Fault Status Register Definitions */ -#define SCB_DFSR_EXTERNAL_Pos 4U /*!< SCB DFSR: EXTERNAL Position */ -#define SCB_DFSR_EXTERNAL_Msk (1UL << SCB_DFSR_EXTERNAL_Pos) /*!< SCB DFSR: EXTERNAL Mask */ - -#define SCB_DFSR_VCATCH_Pos 3U /*!< SCB DFSR: VCATCH Position */ -#define SCB_DFSR_VCATCH_Msk (1UL << SCB_DFSR_VCATCH_Pos) /*!< SCB DFSR: VCATCH Mask */ - -#define SCB_DFSR_DWTTRAP_Pos 2U /*!< SCB DFSR: DWTTRAP Position */ -#define SCB_DFSR_DWTTRAP_Msk (1UL << SCB_DFSR_DWTTRAP_Pos) /*!< SCB DFSR: DWTTRAP Mask */ - -#define SCB_DFSR_BKPT_Pos 1U /*!< SCB DFSR: BKPT Position */ -#define SCB_DFSR_BKPT_Msk (1UL << SCB_DFSR_BKPT_Pos) /*!< SCB DFSR: BKPT Mask */ - -#define SCB_DFSR_HALTED_Pos 0U /*!< SCB DFSR: HALTED Position */ -#define SCB_DFSR_HALTED_Msk (1UL /*<< SCB_DFSR_HALTED_Pos*/) /*!< SCB DFSR: HALTED Mask */ - -/*@} end of group CMSIS_SCB */ - - -/** - \ingroup CMSIS_core_register - \defgroup CMSIS_SCnSCB System Controls not in SCB (SCnSCB) - \brief Type definitions for the System Control and ID Register not in the SCB - @{ - */ - -/** - \brief Structure type to access the System Control and ID Register not in the SCB. - */ -typedef struct -{ - uint32_t RESERVED0[1U]; - __IM uint32_t ICTR; /*!< Offset: 0x004 (R/ ) Interrupt Controller Type Register */ - uint32_t RESERVED1[1U]; -} SCnSCB_Type; - -/* Interrupt Controller Type Register Definitions */ -#define SCnSCB_ICTR_INTLINESNUM_Pos 0U /*!< ICTR: INTLINESNUM Position */ -#define SCnSCB_ICTR_INTLINESNUM_Msk (0xFUL /*<< SCnSCB_ICTR_INTLINESNUM_Pos*/) /*!< ICTR: INTLINESNUM Mask */ - -/*@} end of group CMSIS_SCnotSCB */ - - -/** - \ingroup CMSIS_core_register - \defgroup CMSIS_SysTick System Tick Timer (SysTick) - \brief Type definitions for the System Timer Registers. - @{ - */ - -/** - \brief Structure type to access the System Timer (SysTick). - */ -typedef struct -{ - __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) SysTick Control and Status Register */ - __IOM uint32_t LOAD; /*!< Offset: 0x004 (R/W) SysTick Reload Value Register */ - __IOM uint32_t VAL; /*!< Offset: 0x008 (R/W) SysTick Current Value Register */ - __IM uint32_t CALIB; /*!< Offset: 0x00C (R/ ) SysTick Calibration Register */ -} SysTick_Type; - -/* SysTick Control / Status Register Definitions */ -#define SysTick_CTRL_COUNTFLAG_Pos 16U /*!< SysTick CTRL: COUNTFLAG Position */ -#define SysTick_CTRL_COUNTFLAG_Msk (1UL << SysTick_CTRL_COUNTFLAG_Pos) /*!< SysTick CTRL: COUNTFLAG Mask */ - -#define SysTick_CTRL_CLKSOURCE_Pos 2U /*!< SysTick CTRL: CLKSOURCE Position */ -#define SysTick_CTRL_CLKSOURCE_Msk (1UL << SysTick_CTRL_CLKSOURCE_Pos) /*!< SysTick CTRL: CLKSOURCE Mask */ - -#define SysTick_CTRL_TICKINT_Pos 1U /*!< SysTick CTRL: TICKINT Position */ -#define SysTick_CTRL_TICKINT_Msk (1UL << SysTick_CTRL_TICKINT_Pos) /*!< SysTick CTRL: TICKINT Mask */ - -#define SysTick_CTRL_ENABLE_Pos 0U /*!< SysTick CTRL: ENABLE Position */ -#define SysTick_CTRL_ENABLE_Msk (1UL /*<< SysTick_CTRL_ENABLE_Pos*/) /*!< SysTick CTRL: ENABLE Mask */ - -/* SysTick Reload Register Definitions */ -#define SysTick_LOAD_RELOAD_Pos 0U /*!< SysTick LOAD: RELOAD Position */ -#define SysTick_LOAD_RELOAD_Msk (0xFFFFFFUL /*<< SysTick_LOAD_RELOAD_Pos*/) /*!< SysTick LOAD: RELOAD Mask */ - -/* SysTick Current Register Definitions */ -#define SysTick_VAL_CURRENT_Pos 0U /*!< SysTick VAL: CURRENT Position */ -#define SysTick_VAL_CURRENT_Msk (0xFFFFFFUL /*<< SysTick_VAL_CURRENT_Pos*/) /*!< SysTick VAL: CURRENT Mask */ - -/* SysTick Calibration Register Definitions */ -#define SysTick_CALIB_NOREF_Pos 31U /*!< SysTick CALIB: NOREF Position */ -#define SysTick_CALIB_NOREF_Msk (1UL << SysTick_CALIB_NOREF_Pos) /*!< SysTick CALIB: NOREF Mask */ - -#define SysTick_CALIB_SKEW_Pos 30U /*!< SysTick CALIB: SKEW Position */ -#define SysTick_CALIB_SKEW_Msk (1UL << SysTick_CALIB_SKEW_Pos) /*!< SysTick CALIB: SKEW Mask */ - -#define SysTick_CALIB_TENMS_Pos 0U /*!< SysTick CALIB: TENMS Position */ -#define SysTick_CALIB_TENMS_Msk (0xFFFFFFUL /*<< SysTick_CALIB_TENMS_Pos*/) /*!< SysTick CALIB: TENMS Mask */ - -/*@} end of group CMSIS_SysTick */ - - -/** - \ingroup CMSIS_core_register - \defgroup CMSIS_ITM Instrumentation Trace Macrocell (ITM) - \brief Type definitions for the Instrumentation Trace Macrocell (ITM) - @{ - */ - -/** - \brief Structure type to access the Instrumentation Trace Macrocell Register (ITM). - */ -typedef struct -{ - __OM union - { - __OM uint8_t u8; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 8-bit */ - __OM uint16_t u16; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 16-bit */ - __OM uint32_t u32; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 32-bit */ - } PORT [32U]; /*!< Offset: 0x000 ( /W) ITM Stimulus Port Registers */ - uint32_t RESERVED0[864U]; - __IOM uint32_t TER; /*!< Offset: 0xE00 (R/W) ITM Trace Enable Register */ - uint32_t RESERVED1[15U]; - __IOM uint32_t TPR; /*!< Offset: 0xE40 (R/W) ITM Trace Privilege Register */ - uint32_t RESERVED2[15U]; - __IOM uint32_t TCR; /*!< Offset: 0xE80 (R/W) ITM Trace Control Register */ - uint32_t RESERVED3[29U]; - __OM uint32_t IWR; /*!< Offset: 0xEF8 ( /W) ITM Integration Write Register */ - __IM uint32_t IRR; /*!< Offset: 0xEFC (R/ ) ITM Integration Read Register */ - __IOM uint32_t IMCR; /*!< Offset: 0xF00 (R/W) ITM Integration Mode Control Register */ - uint32_t RESERVED4[43U]; - __OM uint32_t LAR; /*!< Offset: 0xFB0 ( /W) ITM Lock Access Register */ - __IM uint32_t LSR; /*!< Offset: 0xFB4 (R/ ) ITM Lock Status Register */ - uint32_t RESERVED5[6U]; - __IM uint32_t PID4; /*!< Offset: 0xFD0 (R/ ) ITM Peripheral Identification Register #4 */ - __IM uint32_t PID5; /*!< Offset: 0xFD4 (R/ ) ITM Peripheral Identification Register #5 */ - __IM uint32_t PID6; /*!< Offset: 0xFD8 (R/ ) ITM Peripheral Identification Register #6 */ - __IM uint32_t PID7; /*!< Offset: 0xFDC (R/ ) ITM Peripheral Identification Register #7 */ - __IM uint32_t PID0; /*!< Offset: 0xFE0 (R/ ) ITM Peripheral Identification Register #0 */ - __IM uint32_t PID1; /*!< Offset: 0xFE4 (R/ ) ITM Peripheral Identification Register #1 */ - __IM uint32_t PID2; /*!< Offset: 0xFE8 (R/ ) ITM Peripheral Identification Register #2 */ - __IM uint32_t PID3; /*!< Offset: 0xFEC (R/ ) ITM Peripheral Identification Register #3 */ - __IM uint32_t CID0; /*!< Offset: 0xFF0 (R/ ) ITM Component Identification Register #0 */ - __IM uint32_t CID1; /*!< Offset: 0xFF4 (R/ ) ITM Component Identification Register #1 */ - __IM uint32_t CID2; /*!< Offset: 0xFF8 (R/ ) ITM Component Identification Register #2 */ - __IM uint32_t CID3; /*!< Offset: 0xFFC (R/ ) ITM Component Identification Register #3 */ -} ITM_Type; - -/* ITM Trace Privilege Register Definitions */ -#define ITM_TPR_PRIVMASK_Pos 0U /*!< ITM TPR: PRIVMASK Position */ -#define ITM_TPR_PRIVMASK_Msk (0xFUL /*<< ITM_TPR_PRIVMASK_Pos*/) /*!< ITM TPR: PRIVMASK Mask */ - -/* ITM Trace Control Register Definitions */ -#define ITM_TCR_BUSY_Pos 23U /*!< ITM TCR: BUSY Position */ -#define ITM_TCR_BUSY_Msk (1UL << ITM_TCR_BUSY_Pos) /*!< ITM TCR: BUSY Mask */ - -#define ITM_TCR_TraceBusID_Pos 16U /*!< ITM TCR: ATBID Position */ -#define ITM_TCR_TraceBusID_Msk (0x7FUL << ITM_TCR_TraceBusID_Pos) /*!< ITM TCR: ATBID Mask */ - -#define ITM_TCR_GTSFREQ_Pos 10U /*!< ITM TCR: Global timestamp frequency Position */ -#define ITM_TCR_GTSFREQ_Msk (3UL << ITM_TCR_GTSFREQ_Pos) /*!< ITM TCR: Global timestamp frequency Mask */ - -#define ITM_TCR_TSPrescale_Pos 8U /*!< ITM TCR: TSPrescale Position */ -#define ITM_TCR_TSPrescale_Msk (3UL << ITM_TCR_TSPrescale_Pos) /*!< ITM TCR: TSPrescale Mask */ - -#define ITM_TCR_SWOENA_Pos 4U /*!< ITM TCR: SWOENA Position */ -#define ITM_TCR_SWOENA_Msk (1UL << ITM_TCR_SWOENA_Pos) /*!< ITM TCR: SWOENA Mask */ - -#define ITM_TCR_DWTENA_Pos 3U /*!< ITM TCR: DWTENA Position */ -#define ITM_TCR_DWTENA_Msk (1UL << ITM_TCR_DWTENA_Pos) /*!< ITM TCR: DWTENA Mask */ - -#define ITM_TCR_SYNCENA_Pos 2U /*!< ITM TCR: SYNCENA Position */ -#define ITM_TCR_SYNCENA_Msk (1UL << ITM_TCR_SYNCENA_Pos) /*!< ITM TCR: SYNCENA Mask */ - -#define ITM_TCR_TSENA_Pos 1U /*!< ITM TCR: TSENA Position */ -#define ITM_TCR_TSENA_Msk (1UL << ITM_TCR_TSENA_Pos) /*!< ITM TCR: TSENA Mask */ - -#define ITM_TCR_ITMENA_Pos 0U /*!< ITM TCR: ITM Enable bit Position */ -#define ITM_TCR_ITMENA_Msk (1UL /*<< ITM_TCR_ITMENA_Pos*/) /*!< ITM TCR: ITM Enable bit Mask */ - -/* ITM Integration Write Register Definitions */ -#define ITM_IWR_ATVALIDM_Pos 0U /*!< ITM IWR: ATVALIDM Position */ -#define ITM_IWR_ATVALIDM_Msk (1UL /*<< ITM_IWR_ATVALIDM_Pos*/) /*!< ITM IWR: ATVALIDM Mask */ - -/* ITM Integration Read Register Definitions */ -#define ITM_IRR_ATREADYM_Pos 0U /*!< ITM IRR: ATREADYM Position */ -#define ITM_IRR_ATREADYM_Msk (1UL /*<< ITM_IRR_ATREADYM_Pos*/) /*!< ITM IRR: ATREADYM Mask */ - -/* ITM Integration Mode Control Register Definitions */ -#define ITM_IMCR_INTEGRATION_Pos 0U /*!< ITM IMCR: INTEGRATION Position */ -#define ITM_IMCR_INTEGRATION_Msk (1UL /*<< ITM_IMCR_INTEGRATION_Pos*/) /*!< ITM IMCR: INTEGRATION Mask */ - -/* ITM Lock Status Register Definitions */ -#define ITM_LSR_ByteAcc_Pos 2U /*!< ITM LSR: ByteAcc Position */ -#define ITM_LSR_ByteAcc_Msk (1UL << ITM_LSR_ByteAcc_Pos) /*!< ITM LSR: ByteAcc Mask */ - -#define ITM_LSR_Access_Pos 1U /*!< ITM LSR: Access Position */ -#define ITM_LSR_Access_Msk (1UL << ITM_LSR_Access_Pos) /*!< ITM LSR: Access Mask */ - -#define ITM_LSR_Present_Pos 0U /*!< ITM LSR: Present Position */ -#define ITM_LSR_Present_Msk (1UL /*<< ITM_LSR_Present_Pos*/) /*!< ITM LSR: Present Mask */ - -/*@}*/ /* end of group CMSIS_ITM */ - - -/** - \ingroup CMSIS_core_register - \defgroup CMSIS_DWT Data Watchpoint and Trace (DWT) - \brief Type definitions for the Data Watchpoint and Trace (DWT) - @{ - */ - -/** - \brief Structure type to access the Data Watchpoint and Trace Register (DWT). - */ -typedef struct -{ - __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) Control Register */ - __IOM uint32_t CYCCNT; /*!< Offset: 0x004 (R/W) Cycle Count Register */ - __IOM uint32_t CPICNT; /*!< Offset: 0x008 (R/W) CPI Count Register */ - __IOM uint32_t EXCCNT; /*!< Offset: 0x00C (R/W) Exception Overhead Count Register */ - __IOM uint32_t SLEEPCNT; /*!< Offset: 0x010 (R/W) Sleep Count Register */ - __IOM uint32_t LSUCNT; /*!< Offset: 0x014 (R/W) LSU Count Register */ - __IOM uint32_t FOLDCNT; /*!< Offset: 0x018 (R/W) Folded-instruction Count Register */ - __IM uint32_t PCSR; /*!< Offset: 0x01C (R/ ) Program Counter Sample Register */ - __IOM uint32_t COMP0; /*!< Offset: 0x020 (R/W) Comparator Register 0 */ - __IOM uint32_t MASK0; /*!< Offset: 0x024 (R/W) Mask Register 0 */ - __IOM uint32_t FUNCTION0; /*!< Offset: 0x028 (R/W) Function Register 0 */ - uint32_t RESERVED0[1U]; - __IOM uint32_t COMP1; /*!< Offset: 0x030 (R/W) Comparator Register 1 */ - __IOM uint32_t MASK1; /*!< Offset: 0x034 (R/W) Mask Register 1 */ - __IOM uint32_t FUNCTION1; /*!< Offset: 0x038 (R/W) Function Register 1 */ - uint32_t RESERVED1[1U]; - __IOM uint32_t COMP2; /*!< Offset: 0x040 (R/W) Comparator Register 2 */ - __IOM uint32_t MASK2; /*!< Offset: 0x044 (R/W) Mask Register 2 */ - __IOM uint32_t FUNCTION2; /*!< Offset: 0x048 (R/W) Function Register 2 */ - uint32_t RESERVED2[1U]; - __IOM uint32_t COMP3; /*!< Offset: 0x050 (R/W) Comparator Register 3 */ - __IOM uint32_t MASK3; /*!< Offset: 0x054 (R/W) Mask Register 3 */ - __IOM uint32_t FUNCTION3; /*!< Offset: 0x058 (R/W) Function Register 3 */ -} DWT_Type; - -/* DWT Control Register Definitions */ -#define DWT_CTRL_NUMCOMP_Pos 28U /*!< DWT CTRL: NUMCOMP Position */ -#define DWT_CTRL_NUMCOMP_Msk (0xFUL << DWT_CTRL_NUMCOMP_Pos) /*!< DWT CTRL: NUMCOMP Mask */ - -#define DWT_CTRL_NOTRCPKT_Pos 27U /*!< DWT CTRL: NOTRCPKT Position */ -#define DWT_CTRL_NOTRCPKT_Msk (0x1UL << DWT_CTRL_NOTRCPKT_Pos) /*!< DWT CTRL: NOTRCPKT Mask */ - -#define DWT_CTRL_NOEXTTRIG_Pos 26U /*!< DWT CTRL: NOEXTTRIG Position */ -#define DWT_CTRL_NOEXTTRIG_Msk (0x1UL << DWT_CTRL_NOEXTTRIG_Pos) /*!< DWT CTRL: NOEXTTRIG Mask */ - -#define DWT_CTRL_NOCYCCNT_Pos 25U /*!< DWT CTRL: NOCYCCNT Position */ -#define DWT_CTRL_NOCYCCNT_Msk (0x1UL << DWT_CTRL_NOCYCCNT_Pos) /*!< DWT CTRL: NOCYCCNT Mask */ - -#define DWT_CTRL_NOPRFCNT_Pos 24U /*!< DWT CTRL: NOPRFCNT Position */ -#define DWT_CTRL_NOPRFCNT_Msk (0x1UL << DWT_CTRL_NOPRFCNT_Pos) /*!< DWT CTRL: NOPRFCNT Mask */ - -#define DWT_CTRL_CYCEVTENA_Pos 22U /*!< DWT CTRL: CYCEVTENA Position */ -#define DWT_CTRL_CYCEVTENA_Msk (0x1UL << DWT_CTRL_CYCEVTENA_Pos) /*!< DWT CTRL: CYCEVTENA Mask */ - -#define DWT_CTRL_FOLDEVTENA_Pos 21U /*!< DWT CTRL: FOLDEVTENA Position */ -#define DWT_CTRL_FOLDEVTENA_Msk (0x1UL << DWT_CTRL_FOLDEVTENA_Pos) /*!< DWT CTRL: FOLDEVTENA Mask */ - -#define DWT_CTRL_LSUEVTENA_Pos 20U /*!< DWT CTRL: LSUEVTENA Position */ -#define DWT_CTRL_LSUEVTENA_Msk (0x1UL << DWT_CTRL_LSUEVTENA_Pos) /*!< DWT CTRL: LSUEVTENA Mask */ - -#define DWT_CTRL_SLEEPEVTENA_Pos 19U /*!< DWT CTRL: SLEEPEVTENA Position */ -#define DWT_CTRL_SLEEPEVTENA_Msk (0x1UL << DWT_CTRL_SLEEPEVTENA_Pos) /*!< DWT CTRL: SLEEPEVTENA Mask */ - -#define DWT_CTRL_EXCEVTENA_Pos 18U /*!< DWT CTRL: EXCEVTENA Position */ -#define DWT_CTRL_EXCEVTENA_Msk (0x1UL << DWT_CTRL_EXCEVTENA_Pos) /*!< DWT CTRL: EXCEVTENA Mask */ - -#define DWT_CTRL_CPIEVTENA_Pos 17U /*!< DWT CTRL: CPIEVTENA Position */ -#define DWT_CTRL_CPIEVTENA_Msk (0x1UL << DWT_CTRL_CPIEVTENA_Pos) /*!< DWT CTRL: CPIEVTENA Mask */ - -#define DWT_CTRL_EXCTRCENA_Pos 16U /*!< DWT CTRL: EXCTRCENA Position */ -#define DWT_CTRL_EXCTRCENA_Msk (0x1UL << DWT_CTRL_EXCTRCENA_Pos) /*!< DWT CTRL: EXCTRCENA Mask */ - -#define DWT_CTRL_PCSAMPLENA_Pos 12U /*!< DWT CTRL: PCSAMPLENA Position */ -#define DWT_CTRL_PCSAMPLENA_Msk (0x1UL << DWT_CTRL_PCSAMPLENA_Pos) /*!< DWT CTRL: PCSAMPLENA Mask */ - -#define DWT_CTRL_SYNCTAP_Pos 10U /*!< DWT CTRL: SYNCTAP Position */ -#define DWT_CTRL_SYNCTAP_Msk (0x3UL << DWT_CTRL_SYNCTAP_Pos) /*!< DWT CTRL: SYNCTAP Mask */ - -#define DWT_CTRL_CYCTAP_Pos 9U /*!< DWT CTRL: CYCTAP Position */ -#define DWT_CTRL_CYCTAP_Msk (0x1UL << DWT_CTRL_CYCTAP_Pos) /*!< DWT CTRL: CYCTAP Mask */ - -#define DWT_CTRL_POSTINIT_Pos 5U /*!< DWT CTRL: POSTINIT Position */ -#define DWT_CTRL_POSTINIT_Msk (0xFUL << DWT_CTRL_POSTINIT_Pos) /*!< DWT CTRL: POSTINIT Mask */ - -#define DWT_CTRL_POSTPRESET_Pos 1U /*!< DWT CTRL: POSTPRESET Position */ -#define DWT_CTRL_POSTPRESET_Msk (0xFUL << DWT_CTRL_POSTPRESET_Pos) /*!< DWT CTRL: POSTPRESET Mask */ - -#define DWT_CTRL_CYCCNTENA_Pos 0U /*!< DWT CTRL: CYCCNTENA Position */ -#define DWT_CTRL_CYCCNTENA_Msk (0x1UL /*<< DWT_CTRL_CYCCNTENA_Pos*/) /*!< DWT CTRL: CYCCNTENA Mask */ - -/* DWT CPI Count Register Definitions */ -#define DWT_CPICNT_CPICNT_Pos 0U /*!< DWT CPICNT: CPICNT Position */ -#define DWT_CPICNT_CPICNT_Msk (0xFFUL /*<< DWT_CPICNT_CPICNT_Pos*/) /*!< DWT CPICNT: CPICNT Mask */ - -/* DWT Exception Overhead Count Register Definitions */ -#define DWT_EXCCNT_EXCCNT_Pos 0U /*!< DWT EXCCNT: EXCCNT Position */ -#define DWT_EXCCNT_EXCCNT_Msk (0xFFUL /*<< DWT_EXCCNT_EXCCNT_Pos*/) /*!< DWT EXCCNT: EXCCNT Mask */ - -/* DWT Sleep Count Register Definitions */ -#define DWT_SLEEPCNT_SLEEPCNT_Pos 0U /*!< DWT SLEEPCNT: SLEEPCNT Position */ -#define DWT_SLEEPCNT_SLEEPCNT_Msk (0xFFUL /*<< DWT_SLEEPCNT_SLEEPCNT_Pos*/) /*!< DWT SLEEPCNT: SLEEPCNT Mask */ - -/* DWT LSU Count Register Definitions */ -#define DWT_LSUCNT_LSUCNT_Pos 0U /*!< DWT LSUCNT: LSUCNT Position */ -#define DWT_LSUCNT_LSUCNT_Msk (0xFFUL /*<< DWT_LSUCNT_LSUCNT_Pos*/) /*!< DWT LSUCNT: LSUCNT Mask */ - -/* DWT Folded-instruction Count Register Definitions */ -#define DWT_FOLDCNT_FOLDCNT_Pos 0U /*!< DWT FOLDCNT: FOLDCNT Position */ -#define DWT_FOLDCNT_FOLDCNT_Msk (0xFFUL /*<< DWT_FOLDCNT_FOLDCNT_Pos*/) /*!< DWT FOLDCNT: FOLDCNT Mask */ - -/* DWT Comparator Mask Register Definitions */ -#define DWT_MASK_MASK_Pos 0U /*!< DWT MASK: MASK Position */ -#define DWT_MASK_MASK_Msk (0x1FUL /*<< DWT_MASK_MASK_Pos*/) /*!< DWT MASK: MASK Mask */ - -/* DWT Comparator Function Register Definitions */ -#define DWT_FUNCTION_MATCHED_Pos 24U /*!< DWT FUNCTION: MATCHED Position */ -#define DWT_FUNCTION_MATCHED_Msk (0x1UL << DWT_FUNCTION_MATCHED_Pos) /*!< DWT FUNCTION: MATCHED Mask */ - -#define DWT_FUNCTION_DATAVADDR1_Pos 16U /*!< DWT FUNCTION: DATAVADDR1 Position */ -#define DWT_FUNCTION_DATAVADDR1_Msk (0xFUL << DWT_FUNCTION_DATAVADDR1_Pos) /*!< DWT FUNCTION: DATAVADDR1 Mask */ - -#define DWT_FUNCTION_DATAVADDR0_Pos 12U /*!< DWT FUNCTION: DATAVADDR0 Position */ -#define DWT_FUNCTION_DATAVADDR0_Msk (0xFUL << DWT_FUNCTION_DATAVADDR0_Pos) /*!< DWT FUNCTION: DATAVADDR0 Mask */ - -#define DWT_FUNCTION_DATAVSIZE_Pos 10U /*!< DWT FUNCTION: DATAVSIZE Position */ -#define DWT_FUNCTION_DATAVSIZE_Msk (0x3UL << DWT_FUNCTION_DATAVSIZE_Pos) /*!< DWT FUNCTION: DATAVSIZE Mask */ - -#define DWT_FUNCTION_LNK1ENA_Pos 9U /*!< DWT FUNCTION: LNK1ENA Position */ -#define DWT_FUNCTION_LNK1ENA_Msk (0x1UL << DWT_FUNCTION_LNK1ENA_Pos) /*!< DWT FUNCTION: LNK1ENA Mask */ - -#define DWT_FUNCTION_DATAVMATCH_Pos 8U /*!< DWT FUNCTION: DATAVMATCH Position */ -#define DWT_FUNCTION_DATAVMATCH_Msk (0x1UL << DWT_FUNCTION_DATAVMATCH_Pos) /*!< DWT FUNCTION: DATAVMATCH Mask */ - -#define DWT_FUNCTION_CYCMATCH_Pos 7U /*!< DWT FUNCTION: CYCMATCH Position */ -#define DWT_FUNCTION_CYCMATCH_Msk (0x1UL << DWT_FUNCTION_CYCMATCH_Pos) /*!< DWT FUNCTION: CYCMATCH Mask */ - -#define DWT_FUNCTION_EMITRANGE_Pos 5U /*!< DWT FUNCTION: EMITRANGE Position */ -#define DWT_FUNCTION_EMITRANGE_Msk (0x1UL << DWT_FUNCTION_EMITRANGE_Pos) /*!< DWT FUNCTION: EMITRANGE Mask */ - -#define DWT_FUNCTION_FUNCTION_Pos 0U /*!< DWT FUNCTION: FUNCTION Position */ -#define DWT_FUNCTION_FUNCTION_Msk (0xFUL /*<< DWT_FUNCTION_FUNCTION_Pos*/) /*!< DWT FUNCTION: FUNCTION Mask */ - -/*@}*/ /* end of group CMSIS_DWT */ - - -/** - \ingroup CMSIS_core_register - \defgroup CMSIS_TPI Trace Port Interface (TPI) - \brief Type definitions for the Trace Port Interface (TPI) - @{ - */ - -/** - \brief Structure type to access the Trace Port Interface Register (TPI). - */ -typedef struct -{ - __IOM uint32_t SSPSR; /*!< Offset: 0x000 (R/ ) Supported Parallel Port Size Register */ - __IOM uint32_t CSPSR; /*!< Offset: 0x004 (R/W) Current Parallel Port Size Register */ - uint32_t RESERVED0[2U]; - __IOM uint32_t ACPR; /*!< Offset: 0x010 (R/W) Asynchronous Clock Prescaler Register */ - uint32_t RESERVED1[55U]; - __IOM uint32_t SPPR; /*!< Offset: 0x0F0 (R/W) Selected Pin Protocol Register */ - uint32_t RESERVED2[131U]; - __IM uint32_t FFSR; /*!< Offset: 0x300 (R/ ) Formatter and Flush Status Register */ - __IOM uint32_t FFCR; /*!< Offset: 0x304 (R/W) Formatter and Flush Control Register */ - __IM uint32_t FSCR; /*!< Offset: 0x308 (R/ ) Formatter Synchronization Counter Register */ - uint32_t RESERVED3[759U]; - __IM uint32_t TRIGGER; /*!< Offset: 0xEE8 (R/ ) TRIGGER */ - __IM uint32_t FIFO0; /*!< Offset: 0xEEC (R/ ) Integration ETM Data */ - __IM uint32_t ITATBCTR2; /*!< Offset: 0xEF0 (R/ ) ITATBCTR2 */ - uint32_t RESERVED4[1U]; - __IM uint32_t ITATBCTR0; /*!< Offset: 0xEF8 (R/ ) ITATBCTR0 */ - __IM uint32_t FIFO1; /*!< Offset: 0xEFC (R/ ) Integration ITM Data */ - __IOM uint32_t ITCTRL; /*!< Offset: 0xF00 (R/W) Integration Mode Control */ - uint32_t RESERVED5[39U]; - __IOM uint32_t CLAIMSET; /*!< Offset: 0xFA0 (R/W) Claim tag set */ - __IOM uint32_t CLAIMCLR; /*!< Offset: 0xFA4 (R/W) Claim tag clear */ - uint32_t RESERVED7[8U]; - __IM uint32_t DEVID; /*!< Offset: 0xFC8 (R/ ) TPIU_DEVID */ - __IM uint32_t DEVTYPE; /*!< Offset: 0xFCC (R/ ) TPIU_DEVTYPE */ -} TPI_Type; - -/* TPI Asynchronous Clock Prescaler Register Definitions */ -#define TPI_ACPR_PRESCALER_Pos 0U /*!< TPI ACPR: PRESCALER Position */ -#define TPI_ACPR_PRESCALER_Msk (0x1FFFUL /*<< TPI_ACPR_PRESCALER_Pos*/) /*!< TPI ACPR: PRESCALER Mask */ - -/* TPI Selected Pin Protocol Register Definitions */ -#define TPI_SPPR_TXMODE_Pos 0U /*!< TPI SPPR: TXMODE Position */ -#define TPI_SPPR_TXMODE_Msk (0x3UL /*<< TPI_SPPR_TXMODE_Pos*/) /*!< TPI SPPR: TXMODE Mask */ - -/* TPI Formatter and Flush Status Register Definitions */ -#define TPI_FFSR_FtNonStop_Pos 3U /*!< TPI FFSR: FtNonStop Position */ -#define TPI_FFSR_FtNonStop_Msk (0x1UL << TPI_FFSR_FtNonStop_Pos) /*!< TPI FFSR: FtNonStop Mask */ - -#define TPI_FFSR_TCPresent_Pos 2U /*!< TPI FFSR: TCPresent Position */ -#define TPI_FFSR_TCPresent_Msk (0x1UL << TPI_FFSR_TCPresent_Pos) /*!< TPI FFSR: TCPresent Mask */ - -#define TPI_FFSR_FtStopped_Pos 1U /*!< TPI FFSR: FtStopped Position */ -#define TPI_FFSR_FtStopped_Msk (0x1UL << TPI_FFSR_FtStopped_Pos) /*!< TPI FFSR: FtStopped Mask */ - -#define TPI_FFSR_FlInProg_Pos 0U /*!< TPI FFSR: FlInProg Position */ -#define TPI_FFSR_FlInProg_Msk (0x1UL /*<< TPI_FFSR_FlInProg_Pos*/) /*!< TPI FFSR: FlInProg Mask */ - -/* TPI Formatter and Flush Control Register Definitions */ -#define TPI_FFCR_TrigIn_Pos 8U /*!< TPI FFCR: TrigIn Position */ -#define TPI_FFCR_TrigIn_Msk (0x1UL << TPI_FFCR_TrigIn_Pos) /*!< TPI FFCR: TrigIn Mask */ - -#define TPI_FFCR_EnFCont_Pos 1U /*!< TPI FFCR: EnFCont Position */ -#define TPI_FFCR_EnFCont_Msk (0x1UL << TPI_FFCR_EnFCont_Pos) /*!< TPI FFCR: EnFCont Mask */ - -/* TPI TRIGGER Register Definitions */ -#define TPI_TRIGGER_TRIGGER_Pos 0U /*!< TPI TRIGGER: TRIGGER Position */ -#define TPI_TRIGGER_TRIGGER_Msk (0x1UL /*<< TPI_TRIGGER_TRIGGER_Pos*/) /*!< TPI TRIGGER: TRIGGER Mask */ - -/* TPI Integration ETM Data Register Definitions (FIFO0) */ -#define TPI_FIFO0_ITM_ATVALID_Pos 29U /*!< TPI FIFO0: ITM_ATVALID Position */ -#define TPI_FIFO0_ITM_ATVALID_Msk (0x3UL << TPI_FIFO0_ITM_ATVALID_Pos) /*!< TPI FIFO0: ITM_ATVALID Mask */ - -#define TPI_FIFO0_ITM_bytecount_Pos 27U /*!< TPI FIFO0: ITM_bytecount Position */ -#define TPI_FIFO0_ITM_bytecount_Msk (0x3UL << TPI_FIFO0_ITM_bytecount_Pos) /*!< TPI FIFO0: ITM_bytecount Mask */ - -#define TPI_FIFO0_ETM_ATVALID_Pos 26U /*!< TPI FIFO0: ETM_ATVALID Position */ -#define TPI_FIFO0_ETM_ATVALID_Msk (0x3UL << TPI_FIFO0_ETM_ATVALID_Pos) /*!< TPI FIFO0: ETM_ATVALID Mask */ - -#define TPI_FIFO0_ETM_bytecount_Pos 24U /*!< TPI FIFO0: ETM_bytecount Position */ -#define TPI_FIFO0_ETM_bytecount_Msk (0x3UL << TPI_FIFO0_ETM_bytecount_Pos) /*!< TPI FIFO0: ETM_bytecount Mask */ - -#define TPI_FIFO0_ETM2_Pos 16U /*!< TPI FIFO0: ETM2 Position */ -#define TPI_FIFO0_ETM2_Msk (0xFFUL << TPI_FIFO0_ETM2_Pos) /*!< TPI FIFO0: ETM2 Mask */ - -#define TPI_FIFO0_ETM1_Pos 8U /*!< TPI FIFO0: ETM1 Position */ -#define TPI_FIFO0_ETM1_Msk (0xFFUL << TPI_FIFO0_ETM1_Pos) /*!< TPI FIFO0: ETM1 Mask */ - -#define TPI_FIFO0_ETM0_Pos 0U /*!< TPI FIFO0: ETM0 Position */ -#define TPI_FIFO0_ETM0_Msk (0xFFUL /*<< TPI_FIFO0_ETM0_Pos*/) /*!< TPI FIFO0: ETM0 Mask */ - -/* TPI ITATBCTR2 Register Definitions */ -#define TPI_ITATBCTR2_ATREADY_Pos 0U /*!< TPI ITATBCTR2: ATREADY Position */ -#define TPI_ITATBCTR2_ATREADY_Msk (0x1UL /*<< TPI_ITATBCTR2_ATREADY_Pos*/) /*!< TPI ITATBCTR2: ATREADY Mask */ - -/* TPI Integration ITM Data Register Definitions (FIFO1) */ -#define TPI_FIFO1_ITM_ATVALID_Pos 29U /*!< TPI FIFO1: ITM_ATVALID Position */ -#define TPI_FIFO1_ITM_ATVALID_Msk (0x3UL << TPI_FIFO1_ITM_ATVALID_Pos) /*!< TPI FIFO1: ITM_ATVALID Mask */ - -#define TPI_FIFO1_ITM_bytecount_Pos 27U /*!< TPI FIFO1: ITM_bytecount Position */ -#define TPI_FIFO1_ITM_bytecount_Msk (0x3UL << TPI_FIFO1_ITM_bytecount_Pos) /*!< TPI FIFO1: ITM_bytecount Mask */ - -#define TPI_FIFO1_ETM_ATVALID_Pos 26U /*!< TPI FIFO1: ETM_ATVALID Position */ -#define TPI_FIFO1_ETM_ATVALID_Msk (0x3UL << TPI_FIFO1_ETM_ATVALID_Pos) /*!< TPI FIFO1: ETM_ATVALID Mask */ - -#define TPI_FIFO1_ETM_bytecount_Pos 24U /*!< TPI FIFO1: ETM_bytecount Position */ -#define TPI_FIFO1_ETM_bytecount_Msk (0x3UL << TPI_FIFO1_ETM_bytecount_Pos) /*!< TPI FIFO1: ETM_bytecount Mask */ - -#define TPI_FIFO1_ITM2_Pos 16U /*!< TPI FIFO1: ITM2 Position */ -#define TPI_FIFO1_ITM2_Msk (0xFFUL << TPI_FIFO1_ITM2_Pos) /*!< TPI FIFO1: ITM2 Mask */ - -#define TPI_FIFO1_ITM1_Pos 8U /*!< TPI FIFO1: ITM1 Position */ -#define TPI_FIFO1_ITM1_Msk (0xFFUL << TPI_FIFO1_ITM1_Pos) /*!< TPI FIFO1: ITM1 Mask */ - -#define TPI_FIFO1_ITM0_Pos 0U /*!< TPI FIFO1: ITM0 Position */ -#define TPI_FIFO1_ITM0_Msk (0xFFUL /*<< TPI_FIFO1_ITM0_Pos*/) /*!< TPI FIFO1: ITM0 Mask */ - -/* TPI ITATBCTR0 Register Definitions */ -#define TPI_ITATBCTR0_ATREADY_Pos 0U /*!< TPI ITATBCTR0: ATREADY Position */ -#define TPI_ITATBCTR0_ATREADY_Msk (0x1UL /*<< TPI_ITATBCTR0_ATREADY_Pos*/) /*!< TPI ITATBCTR0: ATREADY Mask */ - -/* TPI Integration Mode Control Register Definitions */ -#define TPI_ITCTRL_Mode_Pos 0U /*!< TPI ITCTRL: Mode Position */ -#define TPI_ITCTRL_Mode_Msk (0x1UL /*<< TPI_ITCTRL_Mode_Pos*/) /*!< TPI ITCTRL: Mode Mask */ - -/* TPI DEVID Register Definitions */ -#define TPI_DEVID_NRZVALID_Pos 11U /*!< TPI DEVID: NRZVALID Position */ -#define TPI_DEVID_NRZVALID_Msk (0x1UL << TPI_DEVID_NRZVALID_Pos) /*!< TPI DEVID: NRZVALID Mask */ - -#define TPI_DEVID_MANCVALID_Pos 10U /*!< TPI DEVID: MANCVALID Position */ -#define TPI_DEVID_MANCVALID_Msk (0x1UL << TPI_DEVID_MANCVALID_Pos) /*!< TPI DEVID: MANCVALID Mask */ - -#define TPI_DEVID_PTINVALID_Pos 9U /*!< TPI DEVID: PTINVALID Position */ -#define TPI_DEVID_PTINVALID_Msk (0x1UL << TPI_DEVID_PTINVALID_Pos) /*!< TPI DEVID: PTINVALID Mask */ - -#define TPI_DEVID_MinBufSz_Pos 6U /*!< TPI DEVID: MinBufSz Position */ -#define TPI_DEVID_MinBufSz_Msk (0x7UL << TPI_DEVID_MinBufSz_Pos) /*!< TPI DEVID: MinBufSz Mask */ - -#define TPI_DEVID_AsynClkIn_Pos 5U /*!< TPI DEVID: AsynClkIn Position */ -#define TPI_DEVID_AsynClkIn_Msk (0x1UL << TPI_DEVID_AsynClkIn_Pos) /*!< TPI DEVID: AsynClkIn Mask */ - -#define TPI_DEVID_NrTraceInput_Pos 0U /*!< TPI DEVID: NrTraceInput Position */ -#define TPI_DEVID_NrTraceInput_Msk (0x1FUL /*<< TPI_DEVID_NrTraceInput_Pos*/) /*!< TPI DEVID: NrTraceInput Mask */ - -/* TPI DEVTYPE Register Definitions */ -#define TPI_DEVTYPE_MajorType_Pos 4U /*!< TPI DEVTYPE: MajorType Position */ -#define TPI_DEVTYPE_MajorType_Msk (0xFUL << TPI_DEVTYPE_MajorType_Pos) /*!< TPI DEVTYPE: MajorType Mask */ - -#define TPI_DEVTYPE_SubType_Pos 0U /*!< TPI DEVTYPE: SubType Position */ -#define TPI_DEVTYPE_SubType_Msk (0xFUL /*<< TPI_DEVTYPE_SubType_Pos*/) /*!< TPI DEVTYPE: SubType Mask */ - -/*@}*/ /* end of group CMSIS_TPI */ - - -#if (__MPU_PRESENT == 1U) -/** - \ingroup CMSIS_core_register - \defgroup CMSIS_MPU Memory Protection Unit (MPU) - \brief Type definitions for the Memory Protection Unit (MPU) - @{ - */ - -/** - \brief Structure type to access the Memory Protection Unit (MPU). - */ -typedef struct -{ - __IM uint32_t TYPE; /*!< Offset: 0x000 (R/ ) MPU Type Register */ - __IOM uint32_t CTRL; /*!< Offset: 0x004 (R/W) MPU Control Register */ - __IOM uint32_t RNR; /*!< Offset: 0x008 (R/W) MPU Region RNRber Register */ - __IOM uint32_t RBAR; /*!< Offset: 0x00C (R/W) MPU Region Base Address Register */ - __IOM uint32_t RASR; /*!< Offset: 0x010 (R/W) MPU Region Attribute and Size Register */ - __IOM uint32_t RBAR_A1; /*!< Offset: 0x014 (R/W) MPU Alias 1 Region Base Address Register */ - __IOM uint32_t RASR_A1; /*!< Offset: 0x018 (R/W) MPU Alias 1 Region Attribute and Size Register */ - __IOM uint32_t RBAR_A2; /*!< Offset: 0x01C (R/W) MPU Alias 2 Region Base Address Register */ - __IOM uint32_t RASR_A2; /*!< Offset: 0x020 (R/W) MPU Alias 2 Region Attribute and Size Register */ - __IOM uint32_t RBAR_A3; /*!< Offset: 0x024 (R/W) MPU Alias 3 Region Base Address Register */ - __IOM uint32_t RASR_A3; /*!< Offset: 0x028 (R/W) MPU Alias 3 Region Attribute and Size Register */ -} MPU_Type; - -/* MPU Type Register Definitions */ -#define MPU_TYPE_IREGION_Pos 16U /*!< MPU TYPE: IREGION Position */ -#define MPU_TYPE_IREGION_Msk (0xFFUL << MPU_TYPE_IREGION_Pos) /*!< MPU TYPE: IREGION Mask */ - -#define MPU_TYPE_DREGION_Pos 8U /*!< MPU TYPE: DREGION Position */ -#define MPU_TYPE_DREGION_Msk (0xFFUL << MPU_TYPE_DREGION_Pos) /*!< MPU TYPE: DREGION Mask */ - -#define MPU_TYPE_SEPARATE_Pos 0U /*!< MPU TYPE: SEPARATE Position */ -#define MPU_TYPE_SEPARATE_Msk (1UL /*<< MPU_TYPE_SEPARATE_Pos*/) /*!< MPU TYPE: SEPARATE Mask */ - -/* MPU Control Register Definitions */ -#define MPU_CTRL_PRIVDEFENA_Pos 2U /*!< MPU CTRL: PRIVDEFENA Position */ -#define MPU_CTRL_PRIVDEFENA_Msk (1UL << MPU_CTRL_PRIVDEFENA_Pos) /*!< MPU CTRL: PRIVDEFENA Mask */ - -#define MPU_CTRL_HFNMIENA_Pos 1U /*!< MPU CTRL: HFNMIENA Position */ -#define MPU_CTRL_HFNMIENA_Msk (1UL << MPU_CTRL_HFNMIENA_Pos) /*!< MPU CTRL: HFNMIENA Mask */ - -#define MPU_CTRL_ENABLE_Pos 0U /*!< MPU CTRL: ENABLE Position */ -#define MPU_CTRL_ENABLE_Msk (1UL /*<< MPU_CTRL_ENABLE_Pos*/) /*!< MPU CTRL: ENABLE Mask */ - -/* MPU Region Number Register Definitions */ -#define MPU_RNR_REGION_Pos 0U /*!< MPU RNR: REGION Position */ -#define MPU_RNR_REGION_Msk (0xFFUL /*<< MPU_RNR_REGION_Pos*/) /*!< MPU RNR: REGION Mask */ - -/* MPU Region Base Address Register Definitions */ -#define MPU_RBAR_ADDR_Pos 5U /*!< MPU RBAR: ADDR Position */ -#define MPU_RBAR_ADDR_Msk (0x7FFFFFFUL << MPU_RBAR_ADDR_Pos) /*!< MPU RBAR: ADDR Mask */ - -#define MPU_RBAR_VALID_Pos 4U /*!< MPU RBAR: VALID Position */ -#define MPU_RBAR_VALID_Msk (1UL << MPU_RBAR_VALID_Pos) /*!< MPU RBAR: VALID Mask */ - -#define MPU_RBAR_REGION_Pos 0U /*!< MPU RBAR: REGION Position */ -#define MPU_RBAR_REGION_Msk (0xFUL /*<< MPU_RBAR_REGION_Pos*/) /*!< MPU RBAR: REGION Mask */ - -/* MPU Region Attribute and Size Register Definitions */ -#define MPU_RASR_ATTRS_Pos 16U /*!< MPU RASR: MPU Region Attribute field Position */ -#define MPU_RASR_ATTRS_Msk (0xFFFFUL << MPU_RASR_ATTRS_Pos) /*!< MPU RASR: MPU Region Attribute field Mask */ - -#define MPU_RASR_XN_Pos 28U /*!< MPU RASR: ATTRS.XN Position */ -#define MPU_RASR_XN_Msk (1UL << MPU_RASR_XN_Pos) /*!< MPU RASR: ATTRS.XN Mask */ - -#define MPU_RASR_AP_Pos 24U /*!< MPU RASR: ATTRS.AP Position */ -#define MPU_RASR_AP_Msk (0x7UL << MPU_RASR_AP_Pos) /*!< MPU RASR: ATTRS.AP Mask */ - -#define MPU_RASR_TEX_Pos 19U /*!< MPU RASR: ATTRS.TEX Position */ -#define MPU_RASR_TEX_Msk (0x7UL << MPU_RASR_TEX_Pos) /*!< MPU RASR: ATTRS.TEX Mask */ - -#define MPU_RASR_S_Pos 18U /*!< MPU RASR: ATTRS.S Position */ -#define MPU_RASR_S_Msk (1UL << MPU_RASR_S_Pos) /*!< MPU RASR: ATTRS.S Mask */ - -#define MPU_RASR_C_Pos 17U /*!< MPU RASR: ATTRS.C Position */ -#define MPU_RASR_C_Msk (1UL << MPU_RASR_C_Pos) /*!< MPU RASR: ATTRS.C Mask */ - -#define MPU_RASR_B_Pos 16U /*!< MPU RASR: ATTRS.B Position */ -#define MPU_RASR_B_Msk (1UL << MPU_RASR_B_Pos) /*!< MPU RASR: ATTRS.B Mask */ - -#define MPU_RASR_SRD_Pos 8U /*!< MPU RASR: Sub-Region Disable Position */ -#define MPU_RASR_SRD_Msk (0xFFUL << MPU_RASR_SRD_Pos) /*!< MPU RASR: Sub-Region Disable Mask */ - -#define MPU_RASR_SIZE_Pos 1U /*!< MPU RASR: Region Size Field Position */ -#define MPU_RASR_SIZE_Msk (0x1FUL << MPU_RASR_SIZE_Pos) /*!< MPU RASR: Region Size Field Mask */ - -#define MPU_RASR_ENABLE_Pos 0U /*!< MPU RASR: Region enable bit Position */ -#define MPU_RASR_ENABLE_Msk (1UL /*<< MPU_RASR_ENABLE_Pos*/) /*!< MPU RASR: Region enable bit Disable Mask */ - -/*@} end of group CMSIS_MPU */ -#endif - - -/** - \ingroup CMSIS_core_register - \defgroup CMSIS_CoreDebug Core Debug Registers (CoreDebug) - \brief Type definitions for the Core Debug Registers - @{ - */ - -/** - \brief Structure type to access the Core Debug Register (CoreDebug). - */ -typedef struct -{ - __IOM uint32_t DHCSR; /*!< Offset: 0x000 (R/W) Debug Halting Control and Status Register */ - __OM uint32_t DCRSR; /*!< Offset: 0x004 ( /W) Debug Core Register Selector Register */ - __IOM uint32_t DCRDR; /*!< Offset: 0x008 (R/W) Debug Core Register Data Register */ - __IOM uint32_t DEMCR; /*!< Offset: 0x00C (R/W) Debug Exception and Monitor Control Register */ -} CoreDebug_Type; - -/* Debug Halting Control and Status Register Definitions */ -#define CoreDebug_DHCSR_DBGKEY_Pos 16U /*!< CoreDebug DHCSR: DBGKEY Position */ -#define CoreDebug_DHCSR_DBGKEY_Msk (0xFFFFUL << CoreDebug_DHCSR_DBGKEY_Pos) /*!< CoreDebug DHCSR: DBGKEY Mask */ - -#define CoreDebug_DHCSR_S_RESET_ST_Pos 25U /*!< CoreDebug DHCSR: S_RESET_ST Position */ -#define CoreDebug_DHCSR_S_RESET_ST_Msk (1UL << CoreDebug_DHCSR_S_RESET_ST_Pos) /*!< CoreDebug DHCSR: S_RESET_ST Mask */ - -#define CoreDebug_DHCSR_S_RETIRE_ST_Pos 24U /*!< CoreDebug DHCSR: S_RETIRE_ST Position */ -#define CoreDebug_DHCSR_S_RETIRE_ST_Msk (1UL << CoreDebug_DHCSR_S_RETIRE_ST_Pos) /*!< CoreDebug DHCSR: S_RETIRE_ST Mask */ - -#define CoreDebug_DHCSR_S_LOCKUP_Pos 19U /*!< CoreDebug DHCSR: S_LOCKUP Position */ -#define CoreDebug_DHCSR_S_LOCKUP_Msk (1UL << CoreDebug_DHCSR_S_LOCKUP_Pos) /*!< CoreDebug DHCSR: S_LOCKUP Mask */ - -#define CoreDebug_DHCSR_S_SLEEP_Pos 18U /*!< CoreDebug DHCSR: S_SLEEP Position */ -#define CoreDebug_DHCSR_S_SLEEP_Msk (1UL << CoreDebug_DHCSR_S_SLEEP_Pos) /*!< CoreDebug DHCSR: S_SLEEP Mask */ - -#define CoreDebug_DHCSR_S_HALT_Pos 17U /*!< CoreDebug DHCSR: S_HALT Position */ -#define CoreDebug_DHCSR_S_HALT_Msk (1UL << CoreDebug_DHCSR_S_HALT_Pos) /*!< CoreDebug DHCSR: S_HALT Mask */ - -#define CoreDebug_DHCSR_S_REGRDY_Pos 16U /*!< CoreDebug DHCSR: S_REGRDY Position */ -#define CoreDebug_DHCSR_S_REGRDY_Msk (1UL << CoreDebug_DHCSR_S_REGRDY_Pos) /*!< CoreDebug DHCSR: S_REGRDY Mask */ - -#define CoreDebug_DHCSR_C_SNAPSTALL_Pos 5U /*!< CoreDebug DHCSR: C_SNAPSTALL Position */ -#define CoreDebug_DHCSR_C_SNAPSTALL_Msk (1UL << CoreDebug_DHCSR_C_SNAPSTALL_Pos) /*!< CoreDebug DHCSR: C_SNAPSTALL Mask */ - -#define CoreDebug_DHCSR_C_MASKINTS_Pos 3U /*!< CoreDebug DHCSR: C_MASKINTS Position */ -#define CoreDebug_DHCSR_C_MASKINTS_Msk (1UL << CoreDebug_DHCSR_C_MASKINTS_Pos) /*!< CoreDebug DHCSR: C_MASKINTS Mask */ - -#define CoreDebug_DHCSR_C_STEP_Pos 2U /*!< CoreDebug DHCSR: C_STEP Position */ -#define CoreDebug_DHCSR_C_STEP_Msk (1UL << CoreDebug_DHCSR_C_STEP_Pos) /*!< CoreDebug DHCSR: C_STEP Mask */ - -#define CoreDebug_DHCSR_C_HALT_Pos 1U /*!< CoreDebug DHCSR: C_HALT Position */ -#define CoreDebug_DHCSR_C_HALT_Msk (1UL << CoreDebug_DHCSR_C_HALT_Pos) /*!< CoreDebug DHCSR: C_HALT Mask */ - -#define CoreDebug_DHCSR_C_DEBUGEN_Pos 0U /*!< CoreDebug DHCSR: C_DEBUGEN Position */ -#define CoreDebug_DHCSR_C_DEBUGEN_Msk (1UL /*<< CoreDebug_DHCSR_C_DEBUGEN_Pos*/) /*!< CoreDebug DHCSR: C_DEBUGEN Mask */ - -/* Debug Core Register Selector Register Definitions */ -#define CoreDebug_DCRSR_REGWnR_Pos 16U /*!< CoreDebug DCRSR: REGWnR Position */ -#define CoreDebug_DCRSR_REGWnR_Msk (1UL << CoreDebug_DCRSR_REGWnR_Pos) /*!< CoreDebug DCRSR: REGWnR Mask */ - -#define CoreDebug_DCRSR_REGSEL_Pos 0U /*!< CoreDebug DCRSR: REGSEL Position */ -#define CoreDebug_DCRSR_REGSEL_Msk (0x1FUL /*<< CoreDebug_DCRSR_REGSEL_Pos*/) /*!< CoreDebug DCRSR: REGSEL Mask */ - -/* Debug Exception and Monitor Control Register Definitions */ -#define CoreDebug_DEMCR_TRCENA_Pos 24U /*!< CoreDebug DEMCR: TRCENA Position */ -#define CoreDebug_DEMCR_TRCENA_Msk (1UL << CoreDebug_DEMCR_TRCENA_Pos) /*!< CoreDebug DEMCR: TRCENA Mask */ - -#define CoreDebug_DEMCR_MON_REQ_Pos 19U /*!< CoreDebug DEMCR: MON_REQ Position */ -#define CoreDebug_DEMCR_MON_REQ_Msk (1UL << CoreDebug_DEMCR_MON_REQ_Pos) /*!< CoreDebug DEMCR: MON_REQ Mask */ - -#define CoreDebug_DEMCR_MON_STEP_Pos 18U /*!< CoreDebug DEMCR: MON_STEP Position */ -#define CoreDebug_DEMCR_MON_STEP_Msk (1UL << CoreDebug_DEMCR_MON_STEP_Pos) /*!< CoreDebug DEMCR: MON_STEP Mask */ - -#define CoreDebug_DEMCR_MON_PEND_Pos 17U /*!< CoreDebug DEMCR: MON_PEND Position */ -#define CoreDebug_DEMCR_MON_PEND_Msk (1UL << CoreDebug_DEMCR_MON_PEND_Pos) /*!< CoreDebug DEMCR: MON_PEND Mask */ - -#define CoreDebug_DEMCR_MON_EN_Pos 16U /*!< CoreDebug DEMCR: MON_EN Position */ -#define CoreDebug_DEMCR_MON_EN_Msk (1UL << CoreDebug_DEMCR_MON_EN_Pos) /*!< CoreDebug DEMCR: MON_EN Mask */ - -#define CoreDebug_DEMCR_VC_HARDERR_Pos 10U /*!< CoreDebug DEMCR: VC_HARDERR Position */ -#define CoreDebug_DEMCR_VC_HARDERR_Msk (1UL << CoreDebug_DEMCR_VC_HARDERR_Pos) /*!< CoreDebug DEMCR: VC_HARDERR Mask */ - -#define CoreDebug_DEMCR_VC_INTERR_Pos 9U /*!< CoreDebug DEMCR: VC_INTERR Position */ -#define CoreDebug_DEMCR_VC_INTERR_Msk (1UL << CoreDebug_DEMCR_VC_INTERR_Pos) /*!< CoreDebug DEMCR: VC_INTERR Mask */ - -#define CoreDebug_DEMCR_VC_BUSERR_Pos 8U /*!< CoreDebug DEMCR: VC_BUSERR Position */ -#define CoreDebug_DEMCR_VC_BUSERR_Msk (1UL << CoreDebug_DEMCR_VC_BUSERR_Pos) /*!< CoreDebug DEMCR: VC_BUSERR Mask */ - -#define CoreDebug_DEMCR_VC_STATERR_Pos 7U /*!< CoreDebug DEMCR: VC_STATERR Position */ -#define CoreDebug_DEMCR_VC_STATERR_Msk (1UL << CoreDebug_DEMCR_VC_STATERR_Pos) /*!< CoreDebug DEMCR: VC_STATERR Mask */ - -#define CoreDebug_DEMCR_VC_CHKERR_Pos 6U /*!< CoreDebug DEMCR: VC_CHKERR Position */ -#define CoreDebug_DEMCR_VC_CHKERR_Msk (1UL << CoreDebug_DEMCR_VC_CHKERR_Pos) /*!< CoreDebug DEMCR: VC_CHKERR Mask */ - -#define CoreDebug_DEMCR_VC_NOCPERR_Pos 5U /*!< CoreDebug DEMCR: VC_NOCPERR Position */ -#define CoreDebug_DEMCR_VC_NOCPERR_Msk (1UL << CoreDebug_DEMCR_VC_NOCPERR_Pos) /*!< CoreDebug DEMCR: VC_NOCPERR Mask */ - -#define CoreDebug_DEMCR_VC_MMERR_Pos 4U /*!< CoreDebug DEMCR: VC_MMERR Position */ -#define CoreDebug_DEMCR_VC_MMERR_Msk (1UL << CoreDebug_DEMCR_VC_MMERR_Pos) /*!< CoreDebug DEMCR: VC_MMERR Mask */ - -#define CoreDebug_DEMCR_VC_CORERESET_Pos 0U /*!< CoreDebug DEMCR: VC_CORERESET Position */ -#define CoreDebug_DEMCR_VC_CORERESET_Msk (1UL /*<< CoreDebug_DEMCR_VC_CORERESET_Pos*/) /*!< CoreDebug DEMCR: VC_CORERESET Mask */ - -/*@} end of group CMSIS_CoreDebug */ - - -/** - \ingroup CMSIS_core_register - \defgroup CMSIS_core_bitfield Core register bit field macros - \brief Macros for use with bit field definitions (xxx_Pos, xxx_Msk). - @{ - */ - -/** - \brief Mask and shift a bit field value for use in a register bit range. - \param[in] field Name of the register bit field. - \param[in] value Value of the bit field. - \return Masked and shifted value. -*/ -#define _VAL2FLD(field, value) ((value << field ## _Pos) & field ## _Msk) - -/** - \brief Mask and shift a register value to extract a bit filed value. - \param[in] field Name of the register bit field. - \param[in] value Value of register. - \return Masked and shifted bit field value. -*/ -#define _FLD2VAL(field, value) ((value & field ## _Msk) >> field ## _Pos) - -/*@} end of group CMSIS_core_bitfield */ - - -/** - \ingroup CMSIS_core_register - \defgroup CMSIS_core_base Core Definitions - \brief Definitions for base addresses, unions, and structures. - @{ - */ - -/* Memory mapping of Cortex-M3 Hardware */ -#define SCS_BASE (0xE000E000UL) /*!< System Control Space Base Address */ -#define ITM_BASE (0xE0000000UL) /*!< ITM Base Address */ -#define DWT_BASE (0xE0001000UL) /*!< DWT Base Address */ -#define TPI_BASE (0xE0040000UL) /*!< TPI Base Address */ -#define CoreDebug_BASE (0xE000EDF0UL) /*!< Core Debug Base Address */ -#define SysTick_BASE (SCS_BASE + 0x0010UL) /*!< SysTick Base Address */ -#define NVIC_BASE (SCS_BASE + 0x0100UL) /*!< NVIC Base Address */ -#define SCB_BASE (SCS_BASE + 0x0D00UL) /*!< System Control Block Base Address */ - -#define SCnSCB ((SCnSCB_Type *) SCS_BASE ) /*!< System control Register not in SCB */ -#define SCB ((SCB_Type *) SCB_BASE ) /*!< SCB configuration struct */ -#define SysTick ((SysTick_Type *) SysTick_BASE ) /*!< SysTick configuration struct */ -#define NVIC ((NVIC_Type *) NVIC_BASE ) /*!< NVIC configuration struct */ -#define ITM ((ITM_Type *) ITM_BASE ) /*!< ITM configuration struct */ -#define DWT ((DWT_Type *) DWT_BASE ) /*!< DWT configuration struct */ -#define TPI ((TPI_Type *) TPI_BASE ) /*!< TPI configuration struct */ -#define CoreDebug ((CoreDebug_Type *) CoreDebug_BASE) /*!< Core Debug configuration struct */ - -#if (__MPU_PRESENT == 1U) - #define MPU_BASE (SCS_BASE + 0x0D90UL) /*!< Memory Protection Unit */ - #define MPU ((MPU_Type *) MPU_BASE ) /*!< Memory Protection Unit */ -#endif - -/*@} */ - - - -/******************************************************************************* - * Hardware Abstraction Layer - Core Function Interface contains: - - Core NVIC Functions - - Core SysTick Functions - - Core Debug Functions - - Core Register Access Functions - ******************************************************************************/ -/** - \defgroup CMSIS_Core_FunctionInterface Functions and Instructions Reference -*/ - - - -/* ########################## NVIC functions #################################### */ -/** - \ingroup CMSIS_Core_FunctionInterface - \defgroup CMSIS_Core_NVICFunctions NVIC Functions - \brief Functions that manage interrupts and exceptions via the NVIC. - @{ - */ - -/** - \brief Set Priority Grouping - \details Sets the priority grouping field using the required unlock sequence. - The parameter PriorityGroup is assigned to the field SCB->AIRCR [10:8] PRIGROUP field. - Only values from 0..7 are used. - In case of a conflict between priority grouping and available - priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set. - \param [in] PriorityGroup Priority grouping field. - */ -__STATIC_INLINE void NVIC_SetPriorityGrouping(uint32_t PriorityGroup) -{ - uint32_t reg_value; - uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ - - reg_value = SCB->AIRCR; /* read old register configuration */ - reg_value &= ~((uint32_t)(SCB_AIRCR_VECTKEY_Msk | SCB_AIRCR_PRIGROUP_Msk)); /* clear bits to change */ - reg_value = (reg_value | - ((uint32_t)0x5FAUL << SCB_AIRCR_VECTKEY_Pos) | - (PriorityGroupTmp << 8U) ); /* Insert write key and priorty group */ - SCB->AIRCR = reg_value; -} - - -/** - \brief Get Priority Grouping - \details Reads the priority grouping field from the NVIC Interrupt Controller. - \return Priority grouping field (SCB->AIRCR [10:8] PRIGROUP field). - */ -__STATIC_INLINE uint32_t NVIC_GetPriorityGrouping(void) -{ - return ((uint32_t)((SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) >> SCB_AIRCR_PRIGROUP_Pos)); -} - - -/** - \brief Enable External Interrupt - \details Enables a device-specific interrupt in the NVIC interrupt controller. - \param [in] IRQn External interrupt number. Value cannot be negative. - */ -__STATIC_INLINE void NVIC_EnableIRQ(IRQn_Type IRQn) -{ - NVIC->ISER[(((uint32_t)(int32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL)); -} - - -/** - \brief Disable External Interrupt - \details Disables a device-specific interrupt in the NVIC interrupt controller. - \param [in] IRQn External interrupt number. Value cannot be negative. - */ -__STATIC_INLINE void NVIC_DisableIRQ(IRQn_Type IRQn) -{ - NVIC->ICER[(((uint32_t)(int32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL)); -} - - -/** - \brief Get Pending Interrupt - \details Reads the pending register in the NVIC and returns the pending bit for the specified interrupt. - \param [in] IRQn Interrupt number. - \return 0 Interrupt status is not pending. - \return 1 Interrupt status is pending. - */ -__STATIC_INLINE uint32_t NVIC_GetPendingIRQ(IRQn_Type IRQn) -{ - return((uint32_t)(((NVIC->ISPR[(((uint32_t)(int32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); -} - - -/** - \brief Set Pending Interrupt - \details Sets the pending bit of an external interrupt. - \param [in] IRQn Interrupt number. Value cannot be negative. - */ -__STATIC_INLINE void NVIC_SetPendingIRQ(IRQn_Type IRQn) -{ - NVIC->ISPR[(((uint32_t)(int32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL)); -} - - -/** - \brief Clear Pending Interrupt - \details Clears the pending bit of an external interrupt. - \param [in] IRQn External interrupt number. Value cannot be negative. - */ -__STATIC_INLINE void NVIC_ClearPendingIRQ(IRQn_Type IRQn) -{ - NVIC->ICPR[(((uint32_t)(int32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL)); -} - - -/** - \brief Get Active Interrupt - \details Reads the active register in NVIC and returns the active bit. - \param [in] IRQn Interrupt number. - \return 0 Interrupt status is not active. - \return 1 Interrupt status is active. - */ -__STATIC_INLINE uint32_t NVIC_GetActive(IRQn_Type IRQn) -{ - return((uint32_t)(((NVIC->IABR[(((uint32_t)(int32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); -} - - -/** - \brief Set Interrupt Priority - \details Sets the priority of an interrupt. - \note The priority cannot be set for every core interrupt. - \param [in] IRQn Interrupt number. - \param [in] priority Priority to set. - */ -__STATIC_INLINE void NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority) -{ - if ((int32_t)(IRQn) < 0) - { - SCB->SHP[(((uint32_t)(int32_t)IRQn) & 0xFUL)-4UL] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL); - } - else - { - NVIC->IP[((uint32_t)(int32_t)IRQn)] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL); - } -} - - -/** - \brief Get Interrupt Priority - \details Reads the priority of an interrupt. - The interrupt number can be positive to specify an external (device specific) interrupt, - or negative to specify an internal (core) interrupt. - \param [in] IRQn Interrupt number. - \return Interrupt Priority. - Value is aligned automatically to the implemented priority bits of the microcontroller. - */ -__STATIC_INLINE uint32_t NVIC_GetPriority(IRQn_Type IRQn) -{ - - if ((int32_t)(IRQn) < 0) - { - return(((uint32_t)SCB->SHP[(((uint32_t)(int32_t)IRQn) & 0xFUL)-4UL] >> (8U - __NVIC_PRIO_BITS))); - } - else - { - return(((uint32_t)NVIC->IP[((uint32_t)(int32_t)IRQn)] >> (8U - __NVIC_PRIO_BITS))); - } -} - - -/** - \brief Encode Priority - \details Encodes the priority for an interrupt with the given priority group, - preemptive priority value, and subpriority value. - In case of a conflict between priority grouping and available - priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set. - \param [in] PriorityGroup Used priority group. - \param [in] PreemptPriority Preemptive priority value (starting from 0). - \param [in] SubPriority Subpriority value (starting from 0). - \return Encoded priority. Value can be used in the function \ref NVIC_SetPriority(). - */ -__STATIC_INLINE uint32_t NVIC_EncodePriority (uint32_t PriorityGroup, uint32_t PreemptPriority, uint32_t SubPriority) -{ - uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ - uint32_t PreemptPriorityBits; - uint32_t SubPriorityBits; - - PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp); - SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS)); - - return ( - ((PreemptPriority & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL)) << SubPriorityBits) | - ((SubPriority & (uint32_t)((1UL << (SubPriorityBits )) - 1UL))) - ); -} - - -/** - \brief Decode Priority - \details Decodes an interrupt priority value with a given priority group to - preemptive priority value and subpriority value. - In case of a conflict between priority grouping and available - priority bits (__NVIC_PRIO_BITS) the smallest possible priority group is set. - \param [in] Priority Priority value, which can be retrieved with the function \ref NVIC_GetPriority(). - \param [in] PriorityGroup Used priority group. - \param [out] pPreemptPriority Preemptive priority value (starting from 0). - \param [out] pSubPriority Subpriority value (starting from 0). - */ -__STATIC_INLINE void NVIC_DecodePriority (uint32_t Priority, uint32_t PriorityGroup, uint32_t* const pPreemptPriority, uint32_t* const pSubPriority) -{ - uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ - uint32_t PreemptPriorityBits; - uint32_t SubPriorityBits; - - PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp); - SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS)); - - *pPreemptPriority = (Priority >> SubPriorityBits) & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL); - *pSubPriority = (Priority ) & (uint32_t)((1UL << (SubPriorityBits )) - 1UL); -} - - -/** - \brief System Reset - \details Initiates a system reset request to reset the MCU. - */ -__STATIC_INLINE void NVIC_SystemReset(void) -{ - __DSB(); /* Ensure all outstanding memory accesses included - buffered write are completed before reset */ - SCB->AIRCR = (uint32_t)((0x5FAUL << SCB_AIRCR_VECTKEY_Pos) | - (SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) | - SCB_AIRCR_SYSRESETREQ_Msk ); /* Keep priority group unchanged */ - __DSB(); /* Ensure completion of memory access */ - - for(;;) /* wait until reset */ - { - __NOP(); - } -} - -/*@} end of CMSIS_Core_NVICFunctions */ - - - -/* ################################## SysTick function ############################################ */ -/** - \ingroup CMSIS_Core_FunctionInterface - \defgroup CMSIS_Core_SysTickFunctions SysTick Functions - \brief Functions that configure the System. - @{ - */ - -#if (__Vendor_SysTickConfig == 0U) - -/** - \brief System Tick Configuration - \details Initializes the System Timer and its interrupt, and starts the System Tick Timer. - Counter is in free running mode to generate periodic interrupts. - \param [in] ticks Number of ticks between two interrupts. - \return 0 Function succeeded. - \return 1 Function failed. - \note When the variable __Vendor_SysTickConfig is set to 1, then the - function SysTick_Config is not included. In this case, the file device.h - must contain a vendor-specific implementation of this function. - */ -__STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks) -{ - if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk) - { - return (1UL); /* Reload value impossible */ - } - - SysTick->LOAD = (uint32_t)(ticks - 1UL); /* set reload register */ - NVIC_SetPriority (SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */ - SysTick->VAL = 0UL; /* Load the SysTick Counter Value */ - SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk | - SysTick_CTRL_TICKINT_Msk | - SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */ - return (0UL); /* Function successful */ -} - -#endif - -/*@} end of CMSIS_Core_SysTickFunctions */ - - - -/* ##################################### Debug In/Output function ########################################### */ -/** - \ingroup CMSIS_Core_FunctionInterface - \defgroup CMSIS_core_DebugFunctions ITM Functions - \brief Functions that access the ITM debug interface. - @{ - */ - -extern volatile int32_t ITM_RxBuffer; /*!< External variable to receive characters. */ -#define ITM_RXBUFFER_EMPTY 0x5AA55AA5U /*!< Value identifying \ref ITM_RxBuffer is ready for next character. */ - - -/** - \brief ITM Send Character - \details Transmits a character via the ITM channel 0, and - \li Just returns when no debugger is connected that has booked the output. - \li Is blocking when a debugger is connected, but the previous character sent has not been transmitted. - \param [in] ch Character to transmit. - \returns Character to transmit. - */ -__STATIC_INLINE uint32_t ITM_SendChar (uint32_t ch) -{ - if (((ITM->TCR & ITM_TCR_ITMENA_Msk) != 0UL) && /* ITM enabled */ - ((ITM->TER & 1UL ) != 0UL) ) /* ITM Port #0 enabled */ - { - while (ITM->PORT[0U].u32 == 0UL) - { - __NOP(); - } - ITM->PORT[0U].u8 = (uint8_t)ch; - } - return (ch); -} - - -/** - \brief ITM Receive Character - \details Inputs a character via the external variable \ref ITM_RxBuffer. - \return Received character. - \return -1 No character pending. - */ -__STATIC_INLINE int32_t ITM_ReceiveChar (void) -{ - int32_t ch = -1; /* no character available */ - - if (ITM_RxBuffer != ITM_RXBUFFER_EMPTY) - { - ch = ITM_RxBuffer; - ITM_RxBuffer = ITM_RXBUFFER_EMPTY; /* ready for next character */ - } - - return (ch); -} - - -/** - \brief ITM Check Character - \details Checks whether a character is pending for reading in the variable \ref ITM_RxBuffer. - \return 0 No character available. - \return 1 Character available. - */ -__STATIC_INLINE int32_t ITM_CheckChar (void) -{ - - if (ITM_RxBuffer == ITM_RXBUFFER_EMPTY) - { - return (0); /* no character available */ - } - else - { - return (1); /* character available */ - } -} - -/*@} end of CMSIS_core_DebugFunctions */ - - - - -#ifdef __cplusplus -} -#endif - -#endif /* __CORE_SC300_H_DEPENDANT */ - -#endif /* __CMSIS_GENERIC */ diff --git a/bsp/essemi/es32f0334/libraries/ES32F033x_ALD_StdPeriph_Driver/EASTSOFT_ES32F033x_ALD.chm b/bsp/essemi/es32f0334/libraries/ES32F033x_ALD_StdPeriph_Driver/EASTSOFT_ES32F033x_ALD.chm deleted file mode 100644 index 9f5df67080..0000000000 Binary files a/bsp/essemi/es32f0334/libraries/ES32F033x_ALD_StdPeriph_Driver/EASTSOFT_ES32F033x_ALD.chm and /dev/null differ diff --git a/bsp/essemi/es32f0334/libraries/ES32F033x_ALD_StdPeriph_Driver/Include/ald_acmp.h b/bsp/essemi/es32f0334/libraries/ES32F033x_ALD_StdPeriph_Driver/Include/ald_acmp.h deleted file mode 100644 index 2bbe7437d0..0000000000 --- a/bsp/essemi/es32f0334/libraries/ES32F033x_ALD_StdPeriph_Driver/Include/ald_acmp.h +++ /dev/null @@ -1,338 +0,0 @@ -/** - ********************************************************************************* - * - * @file ald_acmp.h - * @brief Header file of ACMP module driver. - * - * @version V1.0 - * @date 13 Dec 2017 - * @author AE Team - * @note - * - * Copyright (C) Shanghai Eastsoft Microelectronics Co. Ltd. All rights reserved. - * - ********************************************************************************* - */ - -#ifndef __ALD_ACMP_H__ -#define __ALD_ACMP_H__ - -#ifdef __cplusplus - extern "C" { -#endif - -#include "utils.h" - -/** @addtogroup ES32FXXX_ALD - * @{ - */ - -/** @addtogroup ACMP - * @{ - */ - -/** @defgroup ACMP_Public_Types ACMP Public Types - * @{ - */ - -/** - * @brief Acmp interrupt - */ -typedef enum { - ACMP_IT_EDGE = (1U << 0), /**< Edge interrupt bit */ - ACMP_IT_WARMUP = (1U << 1), /**< Warm up interrupt bit */ -} acmp_it_t; - -/** - * @brief Acmp interrupt - */ -typedef enum { - ACMP_FLAG_EDGE = (1U << 0), /**< Edge interrupt flag */ - ACMP_FLAG_WARMUP = (1U << 1), /**< Warm up interrupt flag */ -} acmp_flag_t; - -/** - * @brief Acmp interrupt flag - */ -typedef enum { - ACMP_STATUS_EDGE = (1U << 0), /**< Edge interrupt flag */ - ACMP_STATUS_WARMUP = (1U << 1), /**< Warm up interrupt flag */ -} acmp_status_t; - -/** - * @brief Acmp positive input - */ -typedef enum { - ACMP_POS_CH0 = 0U, /**< Channel 0 as positive input */ - ACMP_POS_CH1 = 1U, /**< Channel 1 as positive input */ - ACMP_POS_CH2 = 2U, /**< Channel 2 as positive input */ - ACMP_POS_CH3 = 3U, /**< Channel 3 as positive input */ - ACMP_POS_CH4 = 4U, /**< Channel 4 as positive input */ - ACMP_POS_CH5 = 5U, /**< Channel 5 as positive input */ - ACMP_POS_CH6 = 6U, /**< Channel 6 as positive input */ - ACMP_POS_CH7 = 7U, /**< Channel 7 as positive input */ -} acmp_pos_input_t; - -/** - * @brief Acmp negative input - */ -typedef enum { - ACMP_NEG_CH0 = 0U, /**< Channel 0 as negative input */ - ACMP_NEG_CH1 = 1U, /**< Channel 1 as negative input */ - ACMP_NEG_CH2 = 2U, /**< Channel 2 as negative input */ - ACMP_NEG_CH3 = 3U, /**< Channel 3 as negative input */ - ACMP_NEG_CH4 = 4U, /**< Channel 4 as negative input */ - ACMP_NEG_CH5 = 5U, /**< Channel 5 as negative input */ - ACMP_NEG_CH6 = 6U, /**< Channel 6 as negative input */ - ACMP_NEG_CH7 = 7U, /**< Channel 7 as negative input */ - ACMP_NEG_1V25 = 8U, /**< 1.25v as negative input */ - ACMP_NEG_2V5 = 9U, /**< 2.5v as negative input */ - ACMP_NEG_VDD = 10U, /**< VDD as negative input */ -} acmp_neg_input_t; - -/** - * @brief Acmp mode - */ -typedef enum { - ACMP_ULTRA_LOW_POWER = 0U, /**< Ultra low power mode */ - ACMP_LOW_POWER = 1U, /**< Low power mode */ - ACMP_MIDDLE_POWER = 2U, /**< Middle power mode */ - ACMP_HIGH_POWER = 3U, /**< High power mode */ -} acmp_mode_t; - -/** - * @brief Acmp warm-up time - */ -typedef enum { - ACMP_4_PCLK = 0U, /**< 4 hfperclk cycles */ - ACMP_8_PCLK = 1U, /**< 4 hfperclk cycles */ - ACMP_16_PCLK = 2U, /**< 4 hfperclk cycles */ - ACMP_32_PCLK = 3U, /**< 4 hfperclk cycles */ - ACMP_64_PCLK = 4U, /**< 4 hfperclk cycles */ - ACMP_128_PCLK = 5U, /**< 4 hfperclk cycles */ - ACMP_256_PCLK = 6U, /**< 4 hfperclk cycles */ - ACMP_512_PCLK = 7U, /**< 4 hfperclk cycles */ -} acmp_warm_time_t; - -/** - * @brief Acmp hysteresis level - */ -typedef enum { - ACMP_HYST_0 = 0U, /**< No hysteresis */ - ACMP_HYST_15 = 1U, /**< 15mV hysteresis */ - ACMP_HYST_22 = 2U, /**< 22mV hysteresis */ - ACMP_HYST_29 = 3U, /**< 29mV hysteresis */ - ACMP_HYST_36 = 4U, /**< 36mV hysteresis */ - ACMP_HYST_43 = 5U, /**< 43mV hysteresis */ - ACMP_HYST_50 = 6U, /**< 50mV hysteresis */ - ACMP_HYST_57 = 7U, /**< 57mV hysteresis */ -} acmp_hystsel_t; - -/** - * @brief Acmp inactive state - */ -typedef enum { - ACMP_INACTVAL_LOW = 0U, /**< The inactive value is 0 */ - ACMP_INACTVAL_HIGH = 1U, /**< The inactive value is 1 */ -} acmp_inactval_t; - -/** - * @brief which edges set up interrupt - */ -typedef enum { - ACMP_EDGE_NONE = 0U, /**< Disable EDGE interrupt */ - ACMP_EDGE_FALL = 1U, /**< Falling edges set EDGE interrupt */ - ACMP_EDGE_RISE = 2U, /**< rise edges set EDGE interrupt */ - ACMP_EDGE_ALL = 3U, /**< Falling edges and rise edges set EDGE interrupt */ -} acmp_edge_t; - -/** - * @brief Acmp output function - */ -typedef enum { - ACMP_OUT_DISABLE = 0U, /**< Disable acmp output */ - ACMP_OUT_ENABLE = 1U, /**< Enable acmp output */ -} acmp_out_func_t; - -/** - * @brief Acmp warm-up interrupt function - */ -typedef enum { - ACMP_WARM_DISABLE = 0U, /**< Disable acmp warm-up interrupt */ - ACMP_WARM_ENABLE = 1U, /**< Enable acmp warm-up interrupt */ -} acmp_warm_it_func; - -/** - * @brief Acmp gpio output invert - */ -typedef enum { - ACMP_GPIO_NO_INV = 0U, /**< Acmp output to gpio is not inverted */ - ACMP_GPIO_INV = 1U, /**< Acmp output to gpio is inverted */ -} acmp_invert_t; - -/** - * @brief Acmp output config structure definition - */ -typedef struct { - acmp_out_func_t out_func; /**< Acmp output function */ - acmp_invert_t gpio_inv; /**< If invert gpio output */ -} acmp_output_config_t; - -/** - * @brief Acmp init structure definition - */ -typedef struct { - acmp_mode_t mode; /**< Acmp operation mode */ - acmp_warm_time_t warm_time; /**< Acmp warm up time */ - acmp_hystsel_t hystsel; /**< Acmp hysteresis level */ - acmp_warm_it_func warm_func; /**< Acmp warm-up interrupt enable/disable */ - acmp_pos_input_t pos_port; /**< Acmp positive port select */ - acmp_neg_input_t neg_port; /**< Acmp negative port select */ - acmp_inactval_t inactval; /**< Acmp inavtive output value */ - acmp_edge_t edge; /** Select edges to set interrupt flag */ - uint8_t vdd_level; /** Select scaling factor for CDD reference level, MAX is 63 */ -} acmp_init_t; - -/** - * @brief ACMP Handle Structure definition - */ -typedef struct acmp_handle_s { - ACMP_TypeDef *perh; /**< Register base address */ - acmp_init_t init; /**< ACMP required parameters */ - lock_state_t lock; /**< Locking object */ - - void (*acmp_warmup_cplt_cbk)(struct acmp_handle_s *arg); /**< Acmp warm-up complete callback */ - void (*acmp_edge_cplt_cbk)(struct acmp_handle_s *arg); /**< Acmp edge trigger callback */ -} acmp_handle_t; -/** - * @} - */ - -/** @defgroup ACMP_Public_Macros ACMP Public Macros - * @{ - */ -#define ACMP_ENABLE(handle) (SET_BIT((handle)->perh->CON, ACMP_CON_EN_MSK)) -#define ACMP_DISABLE(handle) (CLEAR_BIT((handle)->perh->CON, ACMP_CON_EN_MSK)) -/** - * @} - */ - -/** @defgroup ACMP_Private_Macros ACMP Private Macros - * @{ - */ -#define IS_ACMP_TYPE(x) (((x) == ACMP0) || \ - ((x) == ACMP1)) -#define IS_ACMP_MODE_TYPE(x) (((x) == ACMP_ULTRA_LOW_POWER) || \ - ((x) == ACMP_LOW_POWER) || \ - ((x) == ACMP_MIDDLE_POWER) || \ - ((x) == ACMP_HIGH_POWER)) -#define IS_ACMP_IT_TYPE(x) (((x) == ACMP_IT_EDGE) || \ - ((x) == ACMP_IT_WARMUP)) -#define IS_ACMP_FLAG_TYPE(x) (((x) == ACMP_FLAG_EDGE) || \ - ((x) == ACMP_FLAG_WARMUP)) -#define IS_ACMP_STATUS_TYPE(x) (((x) == ACMP_STATUS_EDGE) || \ - ((x) == ACMP_STATUS_WARMUP)) -#define IS_ACMP_POS_INPUT_TYPE(x) (((x) == ACMP_POS_CH0) || \ - ((x) == ACMP_POS_CH1) || \ - ((x) == ACMP_POS_CH2) || \ - ((x) == ACMP_POS_CH3) || \ - ((x) == ACMP_POS_CH4) || \ - ((x) == ACMP_POS_CH5) || \ - ((x) == ACMP_POS_CH6) || \ - ((x) == ACMP_POS_CH7)) -#define IS_ACMP_NEG_INPUT_TYPE(x) (((x) == ACMP_NEG_CH0) || \ - ((x) == ACMP_NEG_CH1) || \ - ((x) == ACMP_NEG_CH2) || \ - ((x) == ACMP_NEG_CH3) || \ - ((x) == ACMP_NEG_CH4) || \ - ((x) == ACMP_NEG_CH5) || \ - ((x) == ACMP_NEG_CH6) || \ - ((x) == ACMP_NEG_CH7) || \ - ((x) == ACMP_NEG_1V25) || \ - ((x) == ACMP_NEG_2V5) || \ - ((x) == ACMP_NEG_VDD)) -#define IS_ACMP_WARM_UP_TIME_TYPE(x) (((x) == ACMP_4_PCLK) || \ - ((x) == ACMP_8_PCLK) || \ - ((x) == ACMP_16_PCLK) || \ - ((x) == ACMP_32_PCLK) || \ - ((x) == ACMP_64_PCLK) || \ - ((x) == ACMP_128_PCLK) || \ - ((x) == ACMP_256_PCLK) || \ - ((x) == ACMP_512_PCLK)) -#define IS_ACMP_HYSTSEL_TYPE(x) (((x) == ACMP_HYST_0) || \ - ((x) == ACMP_HYST_15) || \ - ((x) == ACMP_HYST_22) || \ - ((x) == ACMP_HYST_29) || \ - ((x) == ACMP_HYST_36) || \ - ((x) == ACMP_HYST_43) || \ - ((x) == ACMP_HYST_50) || \ - ((x) == ACMP_HYST_57)) -#define IS_ACMP_INACTVAL_TYPE(x) (((x) == ACMP_INACTVAL_LOW) || \ - ((x) == ACMP_INACTVAL_HIGH)) -#define IS_ACMP_EDGE_TYPE(x) (((x) == ACMP_EDGE_NONE) || \ - ((x) == ACMP_EDGE_FALL) || \ - ((x) == ACMP_EDGE_RISE) || \ - ((x) == ACMP_EDGE_ALL)) -#define IS_ACMP_OUT_FUNC_TYPE(x) (((x) == ACMP_OUT_DISABLE) || \ - ((x) == ACMP_OUT_ENABLE)) -#define IS_ACMP_INVERT_TYPE(x) (((x) == ACMP_GPIO_NO_INV) || \ - ((x) == ACMP_GPIO_INV)) -#define IS_ACMP_WARM_FUNC_TYPE(x) (((x) == ACMP_WARM_DISABLE) || \ - ((x) == ACMP_WARM_ENABLE)) -/** - * @} - */ - -/** @addtogroup ACMP_Public_Functions - * @{ - */ - -/** @addtogroup ACMP_Public_Functions_Group1 - * @{ - */ -ald_status_t ald_acmp_init(acmp_handle_t *hperh); - -/** - * @} - */ - -/** @addtogroup ACMP_Public_Functions_Group2 - * @{ - */ -ald_status_t ald_acmp_interrupt_config(acmp_handle_t *hperh, acmp_it_t it, type_func_t state); -ald_status_t ald_acmp_set_interrupt_mask(acmp_handle_t *hperh, acmp_it_t it); -it_status_t ald_acmp_get_it_status(acmp_handle_t *hperh, acmp_it_t it); -it_status_t ald_acmp_get_flag_status(acmp_handle_t *hperh, acmp_flag_t it); -ald_status_t ald_acmp_clear_flag_status(acmp_handle_t *hperh, acmp_flag_t it); -flag_status_t ald_acmp_get_status(acmp_handle_t *hperh, acmp_status_t flag); - -/** - * @} - */ - -/** @addtogroup ACMP_Public_Functions_Group3 - * @{ - */ -void ald_acmp_irq_handler(acmp_handle_t *hperh); -ald_status_t ald_acmp_out_config(acmp_handle_t *hperh, acmp_output_config_t *config); -uint8_t ald_acmp_out_result(acmp_handle_t *hperh); -/** - * @} - */ - -/** - * @} - */ - -/** - * @} - */ - -/** - * @} - */ -#ifdef __cplusplus - extern "C" } -#endif - -#endif diff --git a/bsp/essemi/es32f0334/libraries/ES32F033x_ALD_StdPeriph_Driver/Include/ald_adc.h b/bsp/essemi/es32f0334/libraries/ES32F033x_ALD_StdPeriph_Driver/Include/ald_adc.h deleted file mode 100644 index b5f9532f8d..0000000000 --- a/bsp/essemi/es32f0334/libraries/ES32F033x_ALD_StdPeriph_Driver/Include/ald_adc.h +++ /dev/null @@ -1,546 +0,0 @@ -/** - ****************************************************************************** - * @file ald_adc.h - * @brief Header file of ADC Module library. - * - * @version V1.0 - * @date 15 Dec 2017 - * @author AE Team - * @note - * - * Copyright (C) Shanghai Eastsoft Microelectronics Co. Ltd. All rights reserved. - * - ****************************************************************************** - */ - -#ifndef __ALD_ADC_H__ -#define __ALD_ADC_H__ - -#ifdef __cplusplus - extern "C" { -#endif - -#include "utils.h" -#include "ald_dma.h" -#include "ald_pis.h" -#include "ald_timer.h" - -/** @addtogroup ES32FXXX_ALD - * @{ - */ - -/** @addtogroup ADC - * @{ - */ - -/** @defgroup ADC_Pubulic_Types ADC Pubulic Types - * @{ - */ - -/** - * @brief ADC State structures definition - */ -typedef enum { - ADC_STATE_RESET = 0x0U, /**< ADC not yet initialized or disabled */ - ADC_STATE_READY = 0x1U, /**< ADC peripheral ready for use */ - ADC_STATE_BUSY = 0x2U, /**< ADC is busy to internal process */ - ADC_STATE_TIMEOUT = 0x4U, /**< TimeOut occurrence */ - ADC_STATE_ERROR = 0x8U, /**< Internal error occurrence */ - ADC_STATE_BUSY_N = 0x10U, /**< Normal channel busy */ - ADC_STATE_BUSY_I = 0x20U, /**< Insert channel busy */ - ADC_STATE_BUSY_WDG = 0x40U, /**< Insert channel busy */ -} adc_state_t; - -/** - *@brief ADC Error Code - */ -typedef enum { - ADC_ERROR_NONE = 0x0U, /**< No error */ - ADC_ERROR_INTERNAL = 0x1U, /**< ADC IP internal error*/ - ADC_ERROR_OVR = 0x2U, /**< Overrun error */ - ADC_ERROR_DMA = 0x4U, /**< DMA transfer error */ -} adc_error_t; - -/** - *@brief ADC data alignment - */ -typedef enum { - ADC_DATAALIGN_RIGHT = 0x0U, /**< ADC data alignment right */ - ADC_DATAALIGN_LEFT = 0x1U, /**< ADC data alignment left */ -} adc_align_t; - -/** - *@brief ADC config hannal trigger the EOC IT mode - */ -typedef enum { - ADC_NCHESEL_MODE_ALL = 0x0U, /**< ADC set RCHE after convert sequence finish */ - ADC_NCHESEL_MODE_ONE = 0x1U, /**< ADC set RCHE after one convert finish */ -} adc_nchesel_t; - -/** - *@brief ADC channels - */ -typedef enum { - ADC_CHANNEL_0 = 0x0U, /**< ADC channel 0 */ - ADC_CHANNEL_1 = 0x1U, /**< ADC channel 1 */ - ADC_CHANNEL_2 = 0x2U, /**< ADC channel 2 */ - ADC_CHANNEL_3 = 0x3U, /**< ADC channel 3 */ - ADC_CHANNEL_4 = 0x4U, /**< ADC channel 4 */ - ADC_CHANNEL_5 = 0x5U, /**< ADC channel 5 */ - ADC_CHANNEL_6 = 0x6U, /**< ADC channel 6 */ - ADC_CHANNEL_7 = 0x7U, /**< ADC channel 7 */ - ADC_CHANNEL_8 = 0x8U, /**< ADC channel 8 */ - ADC_CHANNEL_9 = 0x9U, /**< ADC channel 9 */ - ADC_CHANNEL_10 = 0xAU, /**< ADC channel 10 */ - ADC_CHANNEL_11 = 0xBU, /**< ADC channel 11 */ - ADC_CHANNEL_12 = 0xCU, /**< ADC channel 12 */ - ADC_CHANNEL_13 = 0xDU, /**< ADC channel 13 */ - ADC_CHANNEL_14 = 0xEU, /**< ADC channel 14 */ - ADC_CHANNEL_15 = 0xFU, /**< ADC channel 15 */ - ADC_CHANNEL_16 = 0x10U, /**< ADC channel 16 */ - ADC_CHANNEL_17 = 0x11U, /**< ADC channel 17 */ - ADC_CHANNEL_18 = 0x12U, /**< ADC channel 18 */ - ADC_CHANNEL_19 = 0x13U, /**< ADC channel 19 */ -} adc_channel_t; - -/** - *@brief ADC sampling times - */ -typedef enum { - ADC_SAMPLETIME_1 = 0x0U, /**< ADC sampling times 1 clk */ - ADC_SAMPLETIME_2 = 0x1U, /**< ADC sampling times 2 clk */ - ADC_SAMPLETIME_4 = 0x2U, /**< ADC sampling times 4 clk */ - ADC_SAMPLETIME_15 = 0x3U, /**< ADC sampling times 15 clk */ -} adc_samp_t; - -/** - *@brief ADC index channel in normal group - */ -typedef enum { - ADC_NCH_IDX_1 = 0x1U, /**< ADC normal channel index 1 */ - ADC_NCH_IDX_2 = 0x2U, /**< ADC normal channel index 2 */ - ADC_NCH_IDX_3 = 0x3U, /**< ADC normal channel index 3 */ - ADC_NCH_IDX_4 = 0x4U, /**< ADC normal channel index 4 */ - ADC_NCH_IDX_5 = 0x5U, /**< ADC normal channel index 5 */ - ADC_NCH_IDX_6 = 0x6U, /**< ADC normal channel index 6 */ - ADC_NCH_IDX_7 = 0x7U, /**< ADC normal channel index 7 */ - ADC_NCH_IDX_8 = 0x8U, /**< ADC normal channel index 8 */ - ADC_NCH_IDX_9 = 0x9U, /**< ADC normal channel index 9 */ - ADC_NCH_IDX_10 = 0xAU, /**< ADC normal channel index 10 */ - ADC_NCH_IDX_11 = 0xBU, /**< ADC normal channel index 11 */ - ADC_NCH_IDX_12 = 0xCU, /**< ADC normal channel index 12 */ - ADC_NCH_IDX_13 = 0xDU, /**< ADC normal channel index 13 */ - ADC_NCH_IDX_14 = 0xEU, /**< ADC normal channel index 14 */ - ADC_NCH_IDX_15 = 0xFU, /**< ADC normal channel index 15 */ - ADC_NCH_IDX_16 = 0x10U, /**< ADC normal channel index 16 */ -} adc_nch_idx_t; - -/** - * @brief ADC index channel in insert group - */ -typedef enum { - ADC_ICH_IDX_1 = 0x1U, /**< ADC insert channel index 1 */ - ADC_ICH_IDX_2 = 0x2U, /**< ADC insert channel index 2 */ - ADC_ICH_IDX_3 = 0x3U, /**< ADC insert channel index 3 */ - ADC_ICH_IDX_4 = 0x4U, /**< ADC insert channel index 4 */ -} adc_ich_idx_t; - -/** - * @brief ADC analog watchdog mode - */ -typedef enum { - ADC_ANAWTD_NONE = 0x0U, /**< No watch dog */ - ADC_ANAWTD_SING_NM = 0x800200U, /**< One normal channel watch dog */ - ADC_ANAWTD_SING_IST = 0x400200U, /**< One insert channel watch dog */ - ADC_ANAWTD_SING_NMIST = 0xC00200U, /**< One normal and insert channel watch dog */ - ADC_ANAWTD_ALL_NM = 0x800000U, /**< All normal channel watch dog */ - ADC_ANAWTD_ALL_IST = 0x400000U, /**< All insert channel watch dog */ - ADC_ANAWTD_ALL_NMIST = 0xC00000U, /**< All normal and insert channel watch dog */ -} adc_ana_wdg_t; - -/** - * @brief ADC Event type - */ -typedef enum { - ADC_AWD_EVENT = (1U << 0), /**< ADC analog watch dog event */ -} adc_event_type_t; - -/** - * @brief ADC interrupts definition - */ -typedef enum { - ADC_IT_NCH = (1U << 5), /**< ADC it normal */ - ADC_IT_AWD = (1U << 6), /**< ADC it awd */ - ADC_IT_ICH = (1U << 7), /**< ADC it insert */ - ADC_IT_OVR = (1U << 26), /**< ADC it overring */ -} adc_it_t; - -/** - * @brief ADC flags definition - */ -typedef enum { - ADC_FLAG_AWD = (1U << 0), /**perh->CON1, ADC_CON1_ADCEN_MSK)) -#define ADC_DISABLE(handle) (CLEAR_BIT((handle)->perh->CON1, ADC_CON1_ADCEN_MSK)) -#define ADC_NH_TRIG_BY_SOFT(handle) (SET_BIT((handle)->perh->CON1, ADC_CON1_NCHTRG_MSK)) -#define ADC_IH_TRIG_BY_SOFT(handle) (SET_BIT((handle)->perh->CON1, ADC_CON1_ICHTRG_MSK)) -#define ADC_RESET_HANDLE_STATE(handle) ((handle)->state = ADC_STATE_RESET) -#define ADC_VREF_OUT_ENABLE(handle) (SET_BIT((handle)->perh->CCR, ADC_CCR_VREFOEN_MSK)) -#define ADC_VREF_OUT_DISABLE(handle) (CLEAR_BIT((handle)->perh->CCR, ADC_CCR_VREFOEN_MSK)) -#define ADC_SPEED_HIGH_ENABLE(handle) (SET_BIT((handle)->perh->CCR, ADC_CCR_PWRMODSEL_MSK)) -#define ADC_SPEED_HIGH_DISABLE(handle) (CLEAR_BIT((handle)->perh->CCR, ADC_CCR_PWRMODSEL_MSK)) -#define ADC_CALIBRATE_ENABLE(handle) (SET_BIT((handle)->perh->CCR, ADC_CCR_TRMEN_MSK)) -#define ADC_CALIBRATE_DISABLE(handle) (CLEAR_BIT((handle)->perh->CCR, ADC_CCR_TRMEN_MSK)) -/** - * @} - */ - -/** @defgroup ADC_Private_Macros ADC Private Macros - * @{ - */ -#define IS_ADC_ICH_IDX_TYPE(x) ((x) <= ADC_ICH_IDX_4) -#define IS_ADC_NCH_IDX_TYPE(x) ((x) <= ADC_NCH_IDX_16) -#define IS_ADC_SAMPLING_TIMES_TYPE(x) (((x) == ADC_SAMPLETIME_1) || \ - ((x) == ADC_SAMPLETIME_2) || \ - ((x) == ADC_SAMPLETIME_4) || \ - ((x) == ADC_SAMPLETIME_15)) -#define IS_ADC_CHANNELS_TYPE(x) ((x) <= ADC_CHANNEL_19) -#define IS_ADC_DATA_ALIGN_TYPE(x) (((x) == ADC_DATAALIGN_RIGHT) || \ - ((x) == ADC_DATAALIGN_LEFT)) -#define IS_ADC_ANALOG_WTD_MODE_TYPE(x) (((x) == ADC_ANAWTD_NONE) || \ - ((x) == ADC_ANAWTD_SING_NM) || \ - ((x) == ADC_ANAWTD_SING_IST) || \ - ((x) == ADC_ANAWTD_SING_NMIST) || \ - ((x) == ADC_ANAWTD_ALL_NM) || \ - ((x) == ADC_ANAWTD_ALL_IST) || \ - ((x) == ADC_ANAWTD_ALL_NMIST)) -#define IS_ADC_IT_TYPE(x) (((x) == ADC_IT_NCH) || \ - ((x) == ADC_IT_AWD) || \ - ((x) == ADC_IT_ICH) || \ - ((x) == ADC_IT_OVR )) -#define IS_ADC_FLAGS_TYPE(x) (((x) == ADC_FLAG_AWD) || \ - ((x) == ADC_FLAG_NCH) || \ - ((x) == ADC_FLAG_ICH) || \ - ((x) == ADC_FLAG_OVR) || \ - ((x) == ADC_FLAG_NCHS) || \ - ((x) == ADC_FLAG_ICHS)) -#define IS_ADC_CLK_DIV_TYPE(x) (((x) == ADC_CKDIV_1) || \ - ((x) == ADC_CKDIV_2) || \ - ((x) == ADC_CKDIV_4) || \ - ((x) == ADC_CKDIV_8) || \ - ((x) == ADC_CKDIV_16) || \ - ((x) == ADC_CKDIV_32) || \ - ((x) == ADC_CKDIV_64) || \ - ((x) == ADC_CKDIV_128)) -#define IS_ADC_NEG_REF_VOLTAGE_TYPE(x) (((x) == ADC_NEG_REF_VSS ) || \ - ((x) == ADC_NEG_REF_VREFN )) -#define IS_POS_REF_VOLTAGE_TYPE(x) (((x) == ADC_POS_REF_VDD) || \ - ((x) == ADC_POS_REF_VREEFP) || \ - ((x) == ADC_POS_REF_VREEFP_BUF)) -#define IS_ADC_NCH_NR_TYPE(x) ((x) <= ADC_NCH_NR_16) -#define IS_ADC_ICH_NR_TYPE(x) ((x) <= ADC_ICH_NR_4) -#define IS_ADC_DISC_MODE_TYPE(x) (((x) == ADC_ALL_DISABLE) || \ - ((x) == ADC_NCH_DISC_EN) || \ - ((x) == ADC_ICH_DISC_EN)) -#define IS_ADC_DISC_NR_TYPE(x) ((x) <= ADC_DISC_NR_8) -#define IS_ADC_CONV_BIT_TYPE(x) (((x) == ADC_CONV_BIT_12) || \ - ((x) == ADC_CONV_BIT_6) || \ - ((x) == ADC_CONV_BIT_8) || \ - ((x) == ADC_CONV_BIT_10)) -#define IS_ADC_TRIG_MODE_TYPE(x) (((x) == ADC_TRIG_SOFT) || \ - ((x) == ADC_TRIG_PIS) || \ - ((x) == ADC_TRIG_PIS_SOFT)) -#define IS_ADC_TYPE(x) (((x) == ADC0)) -#define IS_ADC_NCHESEL_MODE_TYPE(x) (((x) == ADC_NCHESEL_MODE_ALL) || \ - ((x) == ADC_NCHESEL_MODE_ONE)) -#define IS_ADC_EVENT_TYPE(x) ((x) == ADC_AWD_EVENT) -#define IS_ADC_IST_OFFSET_TYPE(x) ((x) <= 0xFFF) -#define IS_HTR_TYPE(x) ((x) <= 0xFFF) -#define IS_LTR_TYPE(x) ((x) <= 0xFFF) -/** - * @} - */ - -/** @addtogroup ADC_Public_Functions - * @{ - */ - -/** @addtogroup ADC_Public_Functions_Group1 - * @{ - */ -ald_status_t ald_adc_init(adc_handle_t *hperh); -ald_status_t ald_adc_reset(adc_handle_t *hperh); -/** - * @} - */ - -/** @addtogroup ADC_Public_Functions_Group2 - * @{ - */ -ald_status_t ald_adc_normal_start(adc_handle_t *hperh); -ald_status_t ald_adc_normal_stop(adc_handle_t *hperh); -ald_status_t ald_adc_normal_poll_for_conversion(adc_handle_t *hperh, uint32_t timeout); -ald_status_t ald_adc_poll_for_event(adc_handle_t *hperh, adc_event_type_t event_type, uint32_t timeout); -ald_status_t ald_adc_normal_start_by_it(adc_handle_t *hperh); -ald_status_t ald_adc_normal_stop_by_it(adc_handle_t *hperh); -#ifdef ALD_DMA -ald_status_t ald_adc_start_by_dma(adc_handle_t *hperh, uint16_t *buf, uint16_t size, uint8_t channel); -ald_status_t ald_adc_stop_by_dma(adc_handle_t *hperh, uint8_t channel); -ald_status_t ald_adc_timer_trigger_adc_by_dma(adc_timer_config_t *config); -#endif -uint32_t ald_adc_normal_get_value(adc_handle_t *hperh); -uint32_t ald_adc_get_vdd_value(adc_handle_t *hperh); -ald_status_t ald_adc_insert_start(adc_handle_t *hperh); -ald_status_t ald_adc_insert_stop(adc_handle_t *hperh); -ald_status_t ald_adc_insert_poll_for_conversion(adc_handle_t *hperh, uint32_t timeout); -ald_status_t ald_adc_insert_start_by_it(adc_handle_t *hperh); -ald_status_t ald_adc_insert_stop_by_it(adc_handle_t *hperh); -uint32_t ald_adc_insert_get_value(adc_handle_t *hperh, adc_ich_idx_t ih_rank); -void ald_adc_irq_handler(adc_handle_t *hperh); -/** - * @} - */ - -/** @addtogroup ADC_Public_Functions_Group3 - * @{ - */ -ald_status_t ald_adc_normal_channel_config(adc_handle_t *hperh, adc_nch_conf_t *config); -ald_status_t ald_adc_insert_channel_config(adc_handle_t *hperh, adc_ich_conf_t *config); -ald_status_t ald_adc_analog_wdg_config(adc_handle_t *hperh, adc_analog_wdg_conf_t *config); -void ald_adc_interrupt_config(adc_handle_t *hperh, adc_it_t it, type_func_t state); -it_status_t ald_adc_get_it_status(adc_handle_t *hperh, adc_it_t it); -flag_status_t ald_adc_get_flag_status(adc_handle_t *hperh, adc_flag_t flag); -void ald_adc_clear_flag_status(adc_handle_t *hperh, adc_flag_t flag); -/** - * @} - */ - -/** @addtogroup ADC_Public_Functions_Group4 - * @{ - */ -uint32_t ald_adc_get_state(adc_handle_t *hperh); -uint32_t ald_adc_get_error(adc_handle_t *hperh); -/** - * @} - */ - -/** - * @} - */ - -/** - * @} - */ - -/** - * @} - */ -#ifdef __cplusplus - extern "C" } -#endif - -#endif /* __ALD_ADC_H__ */ diff --git a/bsp/essemi/es32f0334/libraries/ES32F033x_ALD_StdPeriph_Driver/Include/ald_bkpc.h b/bsp/essemi/es32f0334/libraries/ES32F033x_ALD_StdPeriph_Driver/Include/ald_bkpc.h deleted file mode 100644 index cbaa1c88f8..0000000000 --- a/bsp/essemi/es32f0334/libraries/ES32F033x_ALD_StdPeriph_Driver/Include/ald_bkpc.h +++ /dev/null @@ -1,171 +0,0 @@ -/** - ********************************************************************************* - * - * @file ald_bkpc.h - * @brief Header file of BKPC module driver. - * - * @version V1.0 - * @date 15 Dec 2017 - * @author AE Team - * @note - * - * Copyright (C) Shanghai Eastsoft Microelectronics Co. Ltd. All rights reserved. - * - ******************************************************************************** - */ - -#ifndef __ALD_BKPC_H__ -#define __ALD_BKPC_H__ - -#ifdef __cplusplus -extern "C" { -#endif - -#include "utils.h" - - -/** @addtogroup ES32FXXX_ALD - * @{ - */ - -/** @addtogroup BKPC - * @{ - */ - -/** @defgroup BKPC_Public_Macros BKPC Public Macros - * @{ - */ -#define BKPC_LOCK() (WRITE_REG(BKPC->PROT, 0U)) -#define BKPC_UNLOCK() (WRITE_REG(BKPC->PROT, 0x9669AA55U)) -#define BKPC_LRC_ENABLE() \ -do { \ - BKPC_UNLOCK(); \ - SET_BIT(BKPC->CR, BKPC_CR_LRCEN_MSK); \ - BKPC_LOCK(); \ -} while (0) -#define BKPC_LRC_DISABLE() \ -do { \ - BKPC_UNLOCK(); \ - CLEAR_BIT(BKPC->CR, BKPC_CR_LRCEN_MSK); \ - BKPC_LOCK(); \ -} while (0) -#define BKPC_LOSM_ENABLE() \ -do { \ - BKPC_UNLOCK(); \ - SET_BIT(BKPC->CR, BKPC_CR_LOSMEN_MSK); \ - BKPC_LOCK(); \ -} while (0) -#define BKPC_LOSM_DISABLE() \ -do { \ - BKPC_UNLOCK(); \ - CLEAR_BIT(BKPC->CR, BKPC_CR_LOSMEN_MSK);\ - BKPC_LOCK(); \ -} while (0) -#define BKPC_LOSC_ENABLE() \ -do { \ - BKPC_UNLOCK(); \ - SET_BIT(BKPC->CR, BKPC_CR_LOSCEN_MSK); \ - BKPC_LOCK(); \ -} while (0) -#define BKPC_LOSC_DISABLE() \ -do { \ - BKPC_UNLOCK(); \ - CLEAR_BIT(BKPC->CR, BKPC_CR_LOSCEN_MSK);\ - BKPC_LOCK(); \ -} while (0) -/** - * @} - */ - -/** @defgroup BKPC_Public_Types BKPC Public Types - * @{ - */ -/** - * @brief BKPC ldo output select - */ -typedef enum { - BKPC_LDO_OUTPUT_1_6 = 0x0U, /**< 1.6V */ - BKPC_LDO_OUTPUT_1_3 = 0x1U, /**< 1.3V */ - BKPC_LDO_OUTPUT_1_4 = 0x2U, /**< 1.4V */ - BKPC_LDO_OUTPUT_1_5 = 0x4U, /**< 1.5V */ -} bkpc_ldo_output_t; - -/** - * @brief Standby wakeup port select - */ -typedef enum { - PMU_STANDBY_PORT_SEL_PA0 = 0x0U, /**< Wakeup by PA0 */ - PMU_STANDBY_PORT_SEL_PA1 = 0x1U, /**< Wakeup by PA1 */ - PMU_STANDBY_PORT_SEL_PA2 = 0x2U, /**< Wakeup by PA2 */ - PMU_STANDBY_PORT_SEL_PA3 = 0x3U, /**< Wakeup by PA3 */ - PMU_STANDBY_PORT_SEL_NONE = 0xFU, /**< Wakeup by other source */ -} bkpc_wakeup_port_t; - -/** - * @brief Standby wakeup level - */ -typedef enum { - PMU_STANDBY_LEVEL_HIGH = 0x0U, /**< High level */ - PMU_STANDBY_LEVEL_LOW = 0x1U, /**< Low level */ -} bkpc_wakeup_level_t; -/** - * @} - */ - -/** - * @defgroup BKPC_Private_Macros BKPC Private Macros - * @{ - */ -#define IS_BKPC_LDO_OUTPUT(x) (((x) == BKPC_LDO_OUTPUT_1_6) || \ - ((x) == BKPC_LDO_OUTPUT_1_3) || \ - ((x) == BKPC_LDO_OUTPUT_1_4) || \ - ((x) == BKPC_LDO_OUTPUT_1_5)) -#define IS_BKPC_WAKEUP_PORT(x) (((x) == PMU_STANDBY_PORT_SEL_PA0) || \ - ((x) == PMU_STANDBY_PORT_SEL_PA1) || \ - ((x) == PMU_STANDBY_PORT_SEL_PA2) || \ - ((x) == PMU_STANDBY_PORT_SEL_PA3) || \ - ((x) == PMU_STANDBY_PORT_SEL_NONE)) -#define IS_BKPC_WAKEUP_LEVEL(x) (((x) == PMU_STANDBY_LEVEL_HIGH) || \ - ((x) == PMU_STANDBY_LEVEL_LOW)) -#define IS_BKPC_RAM_IDX(x) ((x) < 32) -/** - * @} - */ - -/** @addtogroup BKPC_Public_Functions - * @{ - */ -/** @addtogroup BKPC_Public_Functions_Group1 - * @{ - */ -/* control functions */ -extern void ald_bkpc_standby_wakeup_config(bkpc_wakeup_port_t port, bkpc_wakeup_level_t level); -extern void ald_bkpc_ldo_config(bkpc_ldo_output_t output, type_func_t state); -/** - * @} - */ -/** @addtogroup BKPC_Public_Functions_Group2 - * @{ - */ -/* IO operation functions */ -extern void ald_bkpc_write_ram(uint8_t idx, uint32_t value); -extern uint32_t ald_bkpc_read_ram(uint8_t idx); -/** - * @} - */ -/** - * @} - */ - -/** - * @} - */ - -/** - * @} - */ -#ifdef __cplusplus -} -#endif - -#endif /* __ALD_BKPC_H__ */ diff --git a/bsp/essemi/es32f0334/libraries/ES32F033x_ALD_StdPeriph_Driver/Include/ald_calc.h b/bsp/essemi/es32f0334/libraries/ES32F033x_ALD_StdPeriph_Driver/Include/ald_calc.h deleted file mode 100644 index 283417d843..0000000000 --- a/bsp/essemi/es32f0334/libraries/ES32F033x_ALD_StdPeriph_Driver/Include/ald_calc.h +++ /dev/null @@ -1,57 +0,0 @@ -/** - ********************************************************************************* - * - * @file ald_calc.h - * @brief Header file of CALC module driver. - * - * @version V1.0 - * @date 04 Dec 2017 - * @author AE Team - * @note - * - * Copyright (C) Shanghai Eastsoft Microelectronics Co. Ltd. All rights reserved. - * - ******************************************************************************** - */ - -#ifndef __ALD_CALC_H__ -#define __ALD_CALC_H__ - -#ifdef __cplusplus -extern "C" { -#endif - -#include "utils.h" - - -/** @addtogroup ES32FXXX_ALD - * @{ - */ - -/** @addtogroup CALC - * @{ - */ - -/** @addtogroup CALC_Public_Functions - * @{ - */ -extern uint32_t ald_calc_sqrt(uint32_t data); -extern uint32_t ald_calc_div(uint32_t dividend, uint32_t divisor, uint32_t *remainder); -extern int32_t ald_calc_div_sign(int32_t dividend, int32_t divisor, int32_t *remainder); -extern flag_status_t ald_calc_get_dz_status(void); -/** - * @} - */ - -/** - * @} - */ - -/** - * @} - */ -#ifdef __cplusplus -} -#endif - -#endif /* __ALD_CALC_H__ */ diff --git a/bsp/essemi/es32f0334/libraries/ES32F033x_ALD_StdPeriph_Driver/Include/ald_cmu.h b/bsp/essemi/es32f0334/libraries/ES32F033x_ALD_StdPeriph_Driver/Include/ald_cmu.h deleted file mode 100644 index 648b3c2b50..0000000000 --- a/bsp/essemi/es32f0334/libraries/ES32F033x_ALD_StdPeriph_Driver/Include/ald_cmu.h +++ /dev/null @@ -1,651 +0,0 @@ -/** - ********************************************************************************* - * - * @file ald_cmu.h - * @brief Header file of CMU module driver. - * - * @version V1.0 - * @date 22 Nov 2017 - * @author AE Team - * @note - * - * Copyright (C) Shanghai Eastsoft Microelectronics Co. Ltd. All rights reserved. - * - ******************************************************************************** - */ - -#ifndef __ALD_CMU_H__ -#define __ALD_CMU_H__ - -#ifdef __cplusplus -extern "C" { -#endif - -#include "utils.h" -#include "ald_syscfg.h" - - -/** @addtogroup ES32FXXX_ALD - * @{ - */ - -/** @addtogroup CMU - * @{ - */ - -/** @defgroup CMU_Public_Macros CMU Public Macros - * @{ - */ -#define CMU_LOSC_ENABLE() \ -do { \ - SYSCFG_UNLOCK(); \ - SET_BIT(CMU->CLKENR, CMU_CLKENR_LOSCEN_MSK); \ - SYSCFG_LOCK(); \ -} while (0) -#define CMU_LOSC_DISABLE() \ -do { \ - SYSCFG_UNLOCK(); \ - CLEAR_BIT(CMU->CLKENR, CMU_CLKENR_LOSCEN_MSK); \ - SYSCFG_LOCK(); \ -} while (0) -#define CMU_LRC_ENABLE() \ -do { \ - SYSCFG_UNLOCK(); \ - SET_BIT(CMU->CLKENR, CMU_CLKENR_LRCEN_MSK); \ - SYSCFG_LOCK(); \ -} while (0) -#define CMU_LRC_DISABLE() \ -do { \ - SYSCFG_UNLOCK(); \ - CLEAR_BIT(CMU->CLKENR, CMU_CLKENR_LRCEN_MSK); \ - SYSCFG_LOCK(); \ -} while (0) -#define CMU_ULRC_ENABLE() \ -do { \ - SYSCFG_UNLOCK(); \ - SET_BIT(CMU->CLKENR, CMU_CLKENR_ULRCEN_MSK); \ - SYSCFG_LOCK(); \ -} while (0) -#define CMU_ULRC_DISABLE() \ -do { \ - SYSCFG_UNLOCK(); \ - CLEAR_BIT(CMU->CLKENR, CMU_CLKENR_ULRCEN_MSK); \ - SYSCFG_LOCK(); \ -} while (0) - -/* Low power mode control */ -#define CMU_LP_LRC_ENABLE() \ -do { \ - SYSCFG_UNLOCK(); \ - SET_BIT(CMU->LPENR, CMU_LPENR_LRCEN_MSK); \ - SYSCFG_LOCK(); \ -} while (0) -#define CMU_LP_LRC_DISABLE() \ -do { \ - SYSCFG_UNLOCK(); \ - CLEAR_BIT(CMU->LPENR, CMU_LPENR_LRCEN_MSK); \ - SYSCFG_LOCK(); \ -} while (0) -#define CMU_LP_LOSC_ENABLE() \ -do { \ - SYSCFG_UNLOCK(); \ - SET_BIT(CMU->LPENR, CMU_LPENR_LOSCEN_MSK); \ - SYSCFG_LOCK(); \ -} while (0) -#define CMU_LP_LOSC_DISABLE() \ -do { \ - SYSCFG_UNLOCK(); \ - CLEAR_BIT(CMU->LPENR, CMU_LPENR_LOSCEN_MSK); \ - SYSCFG_LOCK(); \ -} while (0) -#define CMU_LP_HRC_ENABLE() \ -do { \ - SYSCFG_UNLOCK(); \ - SET_BIT(CMU->LPENR, CMU_LPENR_HRCEN_MSK); \ - SYSCFG_LOCK(); \ -} while (0) -#define CMU_LP_HRC_DISABLE() \ -do { \ - SYSCFG_UNLOCK(); \ - CLEAR_BIT(CMU->LPENR, CMU_LPENR_HRCEN_MSK); \ - SYSCFG_LOCK(); \ -} while (0) -#define CMU_LP_HOSC_ENABLE() \ -do { \ - SYSCFG_UNLOCK(); \ - SET_BIT(CMU->LPENR, CMU_LPENR_HOSCEN_MSK); \ - SYSCFG_LOCK(); \ -} while (0) -#define CMU_LP_HOSC_DISABLE() \ -do { \ - SYSCFG_UNLOCK(); \ - CLEAR_BIT(CMU->LPENR, CMU_LPENR_HOSCEN_MSK); \ - SYSCFG_LOCK(); \ -} while (0) -/** - * @} - */ - - -/** @defgroup CMU_Public_Types CMU Public Types - * @{ - */ -/** - * @brief CMU state structure definition - */ -typedef enum { - CMU_CLOCK_HRC = 0x1U, /**< HRC */ - CMU_CLOCK_LRC = 0x2U, /**< LRC */ - CMU_CLOCK_LOSC = 0x3U, /**< LOSC */ - CMU_CLOCK_PLL1 = 0x4U, /**< PLL1 */ - CMU_CLOCK_HOSC = 0x5U, /**< HOSC */ -} cmu_clock_t; - -/** - * @brief PLL1 output clock - */ -typedef enum { - CMU_PLL1_OUTPUT_32M = 0x0U, /**< x8 (32MHz) */ - CMU_PLL1_OUTPUT_48M = 0x1U, /**< x12 (48MHz) */ -} cmu_pll1_output_t; - -/** - * @brief PLL1 referance clock - */ -typedef enum { - CMU_PLL1_INPUT_HRC_6 = 0x0U, /**< HRC / 6 */ - CMU_PLL1_INPUT_PLL2 = 0x1U, /**< PLL2 */ - CMU_PLL1_INPUT_HOSC = 0x2U, /**< HOSC / 1 */ - CMU_PLL1_INPUT_HOSC_2 = 0x3U, /**< HOSC / 2 */ - CMU_PLL1_INPUT_HOSC_3 = 0x4U, /**< HOSC / 3 */ - CMU_PLL1_INPUT_HOSC_4 = 0x5U, /**< HOSC / 4 */ - CMU_PLL1_INPUT_HOSC_5 = 0x6U, /**< HOSC / 5 */ - CMU_PLL1_INPUT_HOSC_6 = 0x7U, /**< HOSC / 6 */ -} cmu_pll1_input_t; - -/** - * @brief HOSC range - */ -typedef enum { - CMU_HOSC_2M = 0x0U, /**< 0~2MHz */ - CMU_HOSC_4M = 0x1U, /**< 2~4MHz */ - CMU_HOSC_8M = 0x2U, /**< 4~8MHz */ - CMU_HOSC_16M = 0x3U, /**< 8~16MHz */ - CMU_HOSC_24M = 0x4U, /**< 16~24MHz */ -} cmu_hosc_range_t; - -/** - * @brief Auto-calibrate input - */ -typedef enum { - CMU_AUTO_CALIB_INPUT_LOSE = 0x0U, /**< LOSC */ - CMU_AUTO_CALIB_INPUT_HOSE = 0x1U, /**< HOSC */ -} cmu_auto_calib_input_t; - -/** - * @brief Auto-calibrate output - */ -typedef enum { - CMU_AUTO_CALIB_OUTPUT_24M = 0x0U, /**< HOSC 24MHz */ - CMU_AUTO_CALIB_OUTPUT_2M = 0x1U, /**< HOSC 2MHz */ -} cmu_auto_calib_output_t; - -/** - * @brief Safe clock source type - */ -typedef enum { - CMU_SAFE_CLK_HOSC = 0x0U, /**< HOSC */ - CMU_SAFE_CLK_LOSC = 0x1U, /**< LOSC */ - CMU_SAFE_CLK_PLL = 0x2U, /**< PLL */ -} cmu_clock_safe_type_t; - -/** - * @brief Frequency division select bit - */ -typedef enum { - CMU_DIV_1 = 0x0U, /**< Division by 1 */ - CMU_DIV_2 = 0x1U, /**< Division by 2 */ - CMU_DIV_4 = 0x2U, /**< Division by 4 */ - CMU_DIV_8 = 0x3U, /**< Division by 8 */ - CMU_DIV_16 = 0x4U, /**< Division by 16 */ - CMU_DIV_32 = 0x5U, /**< Division by 32 */ - CMU_DIV_64 = 0x6U, /**< Division by 64 */ - CMU_DIV_128 = 0x7U, /**< Division by 128 */ - CMU_DIV_256 = 0x8U, /**< Division by 256 */ - CMU_DIV_512 = 0x9U, /**< Division by 512 */ - CMU_DIV_1024 = 0xAU, /**< Division by 1024 */ - CMU_DIV_2048 = 0xBU, /**< Division by 2048 */ - CMU_DIV_4096 = 0xCU, /**< Division by 4096 */ -} cmu_div_t; - -/** - * @brief Bus type - */ -typedef enum { - CMU_HCLK_1 = 0x0U, /**< AHB1 bus */ - CMU_SYS = 0x1U, /**< SYS bus */ - CMU_PCLK_1 = 0x2U, /**< APB1 bus */ - CMU_PCLK_2 = 0x3U, /**< APB2 bus */ -} cmu_bus_t; - -/** - * @brief Output high clock select - */ -typedef enum { - CMU_OUTPUT_HIGH_SEL_HOSC = 0x0U, /**< Select HOSC */ - CMU_OUTPUT_HIGH_SEL_LOSC = 0x1U, /**< Select LOSC */ - CMU_OUTPUT_HIGH_SEL_HRC = 0x2U, /**< Select HRC */ - CMU_OUTPUT_HIGH_SEL_LRC = 0x3U, /**< Select LRC */ - CMU_OUTPUT_HIGH_SEL_HOSM = 0x4U, /**< Select HOSM */ - CMU_OUTPUT_HIGH_SEL_PLL1 = 0x5U, /**< Select PLL1 */ - CMU_OUTPUT_HIGH_SEL_PLL2 = 0x6U, /**< Select PLL2 */ - CMU_OUTPUT_HIGH_SEL_SYSCLK = 0x7U, /**< Select SYSCLK */ -} cmu_output_high_sel_t; - -/** - * @brief Output frequency division - */ -typedef enum { - CMU_OUTPUT_DIV_1 = 0x0U, /**< Division by 1 */ - CMU_OUTPUT_DIV_2 = 0x1U, /**< Division by 2 */ - CMU_OUTPUT_DIV_4 = 0x2U, /**< Division by 4 */ - CMU_OUTPUT_DIV_8 = 0x3U, /**< Division by 8 */ - CMU_OUTPUT_DIV_16 = 0x4U, /**< Division by 16 */ - CMU_OUTPUT_DIV_32 = 0x5U, /**< Division by 32 */ - CMU_OUTPUT_DIV_64 = 0x6U, /**< Division by 64 */ - CMU_OUTPUT_DIV_128 = 0x7U, /**< Division by 128 */ -} cmu_output_high_div_t; - -/** - * @brief Output low clock select - */ -typedef enum { - CMU_OUTPUT_LOW_SEL_LOSC = 0x0U, /**< Select LOSC */ - CMU_OUTPUT_LOW_SEL_LRC = 0x1U, /**< Select LRC */ - CMU_OUTPUT_LOW_SEL_LOSM = 0x2U, /**< Select LOSM */ - CMU_OUTPUT_LOW_SEL_BUZZ = 0x3U, /**< Select BUZZ */ - CMU_OUTPUT_LOW_SEL_ULRC = 0x4U, /**< Select ULRC */ -} cmu_output_low_sel_t; - -/** - * @brief BUZZ frequency division - */ -typedef enum { - CMU_BUZZ_DIV_2 = 0x0U, /**< Division by 2 */ - CMU_BUZZ_DIV_4 = 0x1U, /**< Division by 4 */ - CMU_BUZZ_DIV_8 = 0x2U, /**< Division by 8 */ - CMU_BUZZ_DIV_16 = 0x3U, /**< Division by 16 */ - CMU_BUZZ_DIV_32 = 0x4U, /**< Division by 32 */ - CMU_BUZZ_DIV_64 = 0x5U, /**< Division by 64 */ - CMU_BUZZ_DIV_128 = 0x6U, /**< Division by 128 */ - CMU_BUZZ_DIV_256 = 0x7U, /**< Division by 256 */ -} cmu_buzz_div_t; - -/** - * @brief Low power peripheral clock select - */ -typedef enum { - CMU_LP_PERH_CLOCK_SEL_PCLK2 = 0x0U, /**< Select PCLK2 */ - CMU_LP_PERH_CLOCK_SEL_PLL1 = 0x1U, /**< Select PLL1 */ - CMU_LP_PERH_CLOCK_SEL_PLL2 = 0x2U, /**< Select PLL2 */ - CMU_LP_PERH_CLOCK_SEL_HRC = 0x3U, /**< Select HRC */ - CMU_LP_PERH_CLOCK_SEL_HOSC = 0x4U, /**< Select HOSC */ - CMU_LP_PERH_CLOCK_SEL_LRC = 0x5U, /**< Select LRC */ - CMU_LP_PERH_CLOCK_SEL_LOSC = 0x6U, /**< Select LOSC */ - CMU_LP_PERH_CLOCK_SEL_ULRC = 0x7U, /**< Select ULRC */ - CMU_LP_PERH_CLOCK_SEL_HRC_1M = 0x8U, /**< Select HRC down to 1MHz */ - CMU_LP_PERH_CLOCK_SEL_HOSC_1M = 0x9U, /**< Select HOSC down to 1MHz */ - CMU_LP_PERH_CLOCK_SEL_LOSM = 0xAU, /**< Select LOSM */ - CMU_LP_PERH_CLOCK_SEL_HOSM = 0xBU, /**< Select HOSM */ -} cmu_lp_perh_clock_sel_t; - -/** - * @brief LCD clock select - */ -typedef enum { - CMU_LCD_SEL_LOSM = 0x0U, /**< Select LOSM */ - CMU_LCD_SEL_LOSC = 0x1U, /**< Select LOSC */ - CMU_LCD_SEL_LRC = 0x2U, /**< Select LRC */ - CMU_LCD_SEL_ULRC = 0x3U, /**< Select ULRC */ - CMU_LCD_SEL_HRC_1M = 0x4U, /**< Select HRC down to 1MHz */ - CMU_LCD_SEL_HOSC_1M = 0x5U, /**< Select HOSC down to 1MHz */ -} cmu_lcd_clock_sel_t; - -/** - * @brief Peripheral clock enable/disable - * @verbatim - In this module, for the convenience of code maintenance, - TIMERx is used to indicate the sequence of the timer peripheral. - Different product series TIMERx represent different meanings: - 1. For ES32F065x series: - TIMER0 ----> AD16C4T0 - TIMER1 ----> BS16T0 - TIMER2 ----> GP16C2T0 - TIMER3 ----> GP16C2T1 - TIMER4 ----> BS16T1 - TIMER5 ----> BS16T2 - TIMER6 ----> GP16C4T0 - TIMER7 ----> BS16T3 - - 2. For ES32F033x/ES32F093x series: - TIMER0 ----> GP16C4T0 - TIMER1 ----> BS16T0 - TIMER2 ----> GP16C2T0 - TIMER3 ----> GP16C2T1 - TIMER4 ----> BS16T1 - TIMER5 ----> BS16T2 - TIMER6 ----> GP16C4T1 - TIMER7 ----> BS16T3 - @endverbatim - */ -typedef enum { - CMU_PERH_GPIO = (1U << 0), /**< GPIO */ - CMU_PERH_CRC = (1U << 1), /**< CRC */ - CMU_PERH_CALC = (1U << 2), /**< CALC */ - CMU_PERH_CRYPT = (1U << 3), /**< CRYPT */ - CMU_PERH_TRNG = (1U << 4), /**< TRNG */ - CMU_PERH_PIS = (1U << 5), /**< PIS */ - CMU_PERH_TIMER0 = (1U << 0) | (1U << 27), /**< TIMER0 */ - CMU_PERH_TIMER1 = (1U << 1) | (1U << 27), /**< TIMER1 */ - CMU_PERH_TIMER2 = (1U << 2) | (1U << 27), /**< TIMER2 */ - CMU_PERH_TIMER3 = (1U << 3) | (1U << 27), /**< TIMER3 */ - CMU_PERH_TIMER4 = (1U << 4) | (1U << 27), /**< TIMER4 */ - CMU_PERH_TIMER5 = (1U << 5) | (1U << 27), /**< TIMER5 */ - CMU_PERH_TIMER6 = (1U << 6) | (1U << 27), /**< TIMER6 */ - CMU_PERH_TIMER7 = (1U << 7) | (1U << 27), /**< TIMER7 */ - CMU_PERH_UART0 = (1U << 8) | (1U << 27), /**< UART0 */ - CMU_PERH_UART1 = (1U << 9) | (1U << 27), /**< UART1 */ - CMU_PERH_UART2 = (1U << 10) | (1U << 27), /**< UART2 */ - CMU_PERH_UART3 = (1U << 11) | (1U << 27), /**< UART3 */ - CMU_PERH_USART0 = (1U << 12) | (1U << 27), /**< USART0 */ - CMU_PERH_USART1 = (1U << 13) | (1U << 27), /**< USART1 */ - CMU_PERH_SPI0 = (1U << 16) | (1U << 27), /**< SPI0 */ - CMU_PERH_SPI1 = (1U << 17) | (1U << 27), /**< SPI1 */ - CMU_PERH_SPI2 = (1U << 18) | (1U << 27), /**< SPI2 */ - CMU_PERH_I2C0 = (1U << 20) | (1U << 27), /**< I2C0 */ - CMU_PERH_I2C1 = (1U << 21) | (1U << 27), /**< I2C1 */ - CMU_PERH_CAN = (1U << 24) | (1U << 27), /**< CAN */ - CMU_PERH_LPTIM0 = (1U << 0) | (1U << 28), /**< LPTIM0 */ - CMU_PERH_LPUART0 = (1U << 2) | (1U << 28), /**< LPUART0 */ - CMU_PERH_ADC0 = (1U << 4) | (1U << 28), /**< ADC0 */ - CMU_PERH_ADC1 = (1U << 5) | (1U << 28), /**< ADC1 */ - CMU_PERH_ACMP0 = (1U << 6) | (1U << 28), /**< ACMP0 */ - CMU_PERH_ACMP1 = (1U << 7) | (1U << 28), /**< ACMP1 */ - CMU_PERH_OPAMP = (1U << 8) | (1U << 28), /**< OPAMP */ - CMU_PERH_DAC0 = (1U << 9) | (1U << 28), /**< DAC0 */ - CMU_PERH_WWDT = (1U << 12) | (1U << 28), /**< WWDT */ - CMU_PERH_LCD = (1U << 13) | (1U << 28), /**< LCD */ - CMU_PERH_IWDT = (1U << 14) | (1U << 28), /**< IWDT */ - CMU_PERH_RTC = (1U << 15) | (1U << 28), /**< RTC */ - CMU_PERH_TSENSE = (1U << 16) | (1U << 28), /**< TSENSE */ - CMU_PERH_BKPC = (1U << 17) | (1U << 28), /**< BKPC */ - CMU_PERH_DBGC = (1U << 19) | (1U << 28), /**< DBGC */ - CMU_PERH_ALL = (0x7FFFFFFF), /**< ALL */ -} cmu_perh_t; - -/** - * @brief CMU interrupt type - */ -typedef enum { - CMU_LOSC_STOP = 0x0U, /**< LOSC STOP INTERRUPT */ - CMU_HOSC_STOP = 0x1U, /**< HOSC STOP INTERRUPT */ - CMU_PLL1_UNLOCK = 0x2U, /**< PLL1 UNLOCK INTERRUPT */ - CMU_LOSC_START = 0x3U, /**< LOSC START INTERRUPT */ - CMU_HOSC_START = 0x4U, /**< HOSC START INTERRUPT */ -} cmu_security_t; - -/** - * @brief CMU clock state type - */ -typedef enum { - CMU_CLOCK_STATE_HOSCACT = (1U << 0), /**< HOSC active */ - CMU_CLOCK_STATE_LOSCACT = (1U << 1), /**< LOSC active */ - CMU_CLOCK_STATE_HRCACT = (1U << 2), /**< HRC active */ - CMU_CLOCK_STATE_LRCACT = (1U << 3), /**< LRC active */ - CMU_CLOCK_STATE_ULRCACT = (1U << 4), /**< ULRC active */ - CMU_CLOCK_STATE_PLLACT = (1U << 8), /**< PLL active */ - CMU_CLOCK_STATE_HOSCRDY = (1U << 16), /**< HOSC ready */ - CMU_CLOCK_STATE_LOSCRDY = (1U << 17), /**< LOSC ready */ - CMU_CLOCK_STATE_HRCRDY = (1U << 18), /**< HRC ready */ - CMU_CLOCK_STATE_LRCRDY = (1U << 19), /**< LRC ready */ - CMU_CLOCK_STATE_PLLRDY = (1U << 24), /**< PLL ready */ -} cmu_clock_state_t; -/** - * @} - */ - -/** - * @defgroup CMU_Private_Macros CMU Private Macros - * @{ - */ -#define IS_CMU_CLOCK(x) (((x) == CMU_CLOCK_HRC) || \ - ((x) == CMU_CLOCK_LRC) || \ - ((x) == CMU_CLOCK_LOSC) || \ - ((x) == CMU_CLOCK_PLL1) || \ - ((x) == CMU_CLOCK_HOSC)) -#define IS_CMU_PLL1_OUTPUT(x) (((x) == CMU_PLL1_OUTPUT_32M) || \ - ((x) == CMU_PLL1_OUTPUT_48M)) -#define IS_CMU_PLL1_INPUT(x) (((x) == CMU_PLL1_INPUT_HRC_6) || \ - ((x) == CMU_PLL1_INPUT_PLL2) || \ - ((x) == CMU_PLL1_INPUT_HOSC) || \ - ((x) == CMU_PLL1_INPUT_HOSC_2) || \ - ((x) == CMU_PLL1_INPUT_HOSC_3) || \ - ((x) == CMU_PLL1_INPUT_HOSC_4) || \ - ((x) == CMU_PLL1_INPUT_HOSC_5) || \ - ((x) == CMU_PLL1_INPUT_HOSC_6)) -#define IS_CMU_HOSC_RANGE(x) (((x) == CMU_HOSC_2M) || \ - ((x) == CMU_HOSC_4M) || \ - ((x) == CMU_HOSC_8M) || \ - ((x) == CMU_HOSC_16M) || \ - ((x) == CMU_HOSC_24M)) -#define IS_CMU_DIV(x) (((x) == CMU_DIV_1) || \ - ((x) == CMU_DIV_2) || \ - ((x) == CMU_DIV_4) || \ - ((x) == CMU_DIV_8) || \ - ((x) == CMU_DIV_16) || \ - ((x) == CMU_DIV_32) || \ - ((x) == CMU_DIV_64) || \ - ((x) == CMU_DIV_128) || \ - ((x) == CMU_DIV_256) || \ - ((x) == CMU_DIV_512) || \ - ((x) == CMU_DIV_1024) || \ - ((x) == CMU_DIV_2048) || \ - ((x) == CMU_DIV_4096)) -#define IS_CMU_BUS(x) (((x) == CMU_HCLK_1) || \ - ((x) == CMU_SYS) || \ - ((x) == CMU_PCLK_1) || \ - ((x) == CMU_PCLK_2)) -#define IS_CMU_OUTPUT_HIGH_SEL(x) (((x) == CMU_OUTPUT_HIGH_SEL_HOSC) || \ - ((x) == CMU_OUTPUT_HIGH_SEL_LOSC) || \ - ((x) == CMU_OUTPUT_HIGH_SEL_HRC) || \ - ((x) == CMU_OUTPUT_HIGH_SEL_LRC) || \ - ((x) == CMU_OUTPUT_HIGH_SEL_HOSM) || \ - ((x) == CMU_OUTPUT_HIGH_SEL_PLL1) || \ - ((x) == CMU_OUTPUT_HIGH_SEL_PLL2) || \ - ((x) == CMU_OUTPUT_HIGH_SEL_SYSCLK)) -#define IS_CMU_OUTPUT_HIGH_DIV(x) (((x) == CMU_OUTPUT_DIV_1) || \ - ((x) == CMU_OUTPUT_DIV_2) || \ - ((x) == CMU_OUTPUT_DIV_4) || \ - ((x) == CMU_OUTPUT_DIV_8) || \ - ((x) == CMU_OUTPUT_DIV_16) || \ - ((x) == CMU_OUTPUT_DIV_32) || \ - ((x) == CMU_OUTPUT_DIV_64) || \ - ((x) == CMU_OUTPUT_DIV_128)) -#define IS_CMU_OUTPUT_LOW_SEL(x) (((x) == CMU_OUTPUT_LOW_SEL_LOSC) || \ - ((x) == CMU_OUTPUT_LOW_SEL_LRC ) || \ - ((x) == CMU_OUTPUT_LOW_SEL_LOSM) || \ - ((x) == CMU_OUTPUT_LOW_SEL_BUZZ) || \ - ((x) == CMU_OUTPUT_LOW_SEL_ULRC)) -#define IS_CMU_AUTO_CALIB_INPUT(x) (((x) == CMU_AUTO_CALIB_INPUT_LOSE) || \ - ((x) == CMU_AUTO_CALIB_INPUT_HOSE)) -#define IS_CMU_AUTO_CALIB_OUTPUT(x) (((x) == CMU_AUTO_CALIB_OUTPUT_24M) || \ - ((x) == CMU_AUTO_CALIB_OUTPUT_2M)) -#define IS_CMU_SAFE_CLOCK_TYPE(x) (((x) == CMU_SAFE_CLK_HOSC) || \ - ((x) == CMU_SAFE_CLK_LOSC) || \ - ((x) == CMU_SAFE_CLK_PLL)) -#define IS_CMU_BUZZ_DIV(x) (((x) == CMU_BUZZ_DIV_2) || \ - ((x) == CMU_BUZZ_DIV_4) || \ - ((x) == CMU_BUZZ_DIV_8) || \ - ((x) == CMU_BUZZ_DIV_16) || \ - ((x) == CMU_BUZZ_DIV_32) || \ - ((x) == CMU_BUZZ_DIV_64) || \ - ((x) == CMU_BUZZ_DIV_128) || \ - ((x) == CMU_BUZZ_DIV_256)) -#define IS_CMU_LP_PERH_CLOCK_SEL(x) (((x) == CMU_LP_PERH_CLOCK_SEL_PCLK2) || \ - ((x) == CMU_LP_PERH_CLOCK_SEL_PLL1) || \ - ((x) == CMU_LP_PERH_CLOCK_SEL_PLL2) || \ - ((x) == CMU_LP_PERH_CLOCK_SEL_HRC) || \ - ((x) == CMU_LP_PERH_CLOCK_SEL_HOSC) || \ - ((x) == CMU_LP_PERH_CLOCK_SEL_LRC) || \ - ((x) == CMU_LP_PERH_CLOCK_SEL_LOSC) || \ - ((x) == CMU_LP_PERH_CLOCK_SEL_ULRC) || \ - ((x) == CMU_LP_PERH_CLOCK_SEL_HRC_1M) || \ - ((x) == CMU_LP_PERH_CLOCK_SEL_HOSC_1M) || \ - ((x) == CMU_LP_PERH_CLOCK_SEL_LOSM) || \ - ((x) == CMU_LP_PERH_CLOCK_SEL_HOSM)) -#define IS_CMU_LCD_CLOCK_SEL(x) (((x) == CMU_LCD_SEL_LOSM) || \ - ((x) == CMU_LCD_SEL_LOSC) || \ - ((x) == CMU_LCD_SEL_LRC) || \ - ((x) == CMU_LCD_SEL_ULRC) || \ - ((x) == CMU_LCD_SEL_HRC_1M) || \ - ((x) == CMU_LCD_SEL_HOSC_1M)) -#define IS_CMU_PERH(x) (((x) == CMU_PERH_GPIO) || \ - ((x) == CMU_PERH_CRC) || \ - ((x) == CMU_PERH_CALC) || \ - ((x) == CMU_PERH_CRYPT) || \ - ((x) == CMU_PERH_TRNG) || \ - ((x) == CMU_PERH_PIS) || \ - ((x) == CMU_PERH_TIMER0) || \ - ((x) == CMU_PERH_TIMER1) || \ - ((x) == CMU_PERH_TIMER2) || \ - ((x) == CMU_PERH_TIMER3) || \ - ((x) == CMU_PERH_TIMER4) || \ - ((x) == CMU_PERH_TIMER5) || \ - ((x) == CMU_PERH_TIMER6) || \ - ((x) == CMU_PERH_TIMER7) || \ - ((x) == CMU_PERH_UART0) || \ - ((x) == CMU_PERH_UART1) || \ - ((x) == CMU_PERH_UART2) || \ - ((x) == CMU_PERH_UART3) || \ - ((x) == CMU_PERH_USART0) || \ - ((x) == CMU_PERH_USART1) || \ - ((x) == CMU_PERH_SPI0) || \ - ((x) == CMU_PERH_SPI1) || \ - ((x) == CMU_PERH_SPI2) || \ - ((x) == CMU_PERH_I2C0) || \ - ((x) == CMU_PERH_I2C1) || \ - ((x) == CMU_PERH_CAN) || \ - ((x) == CMU_PERH_LPTIM0) || \ - ((x) == CMU_PERH_LPUART0) || \ - ((x) == CMU_PERH_ADC0) || \ - ((x) == CMU_PERH_ADC1) || \ - ((x) == CMU_PERH_ACMP0) || \ - ((x) == CMU_PERH_ACMP1) || \ - ((x) == CMU_PERH_OPAMP) || \ - ((x) == CMU_PERH_DAC0) || \ - ((x) == CMU_PERH_WWDT) || \ - ((x) == CMU_PERH_LCD) || \ - ((x) == CMU_PERH_IWDT) || \ - ((x) == CMU_PERH_RTC) || \ - ((x) == CMU_PERH_TSENSE) || \ - ((x) == CMU_PERH_BKPC) || \ - ((x) == CMU_PERH_DBGC) || \ - ((x) == CMU_PERH_ALL)) -#define IS_CMU_CLOCK_STATE(x) (((x) == CMU_CLOCK_STATE_HOSCACT) || \ - ((x) == CMU_CLOCK_STATE_LOSCACT) || \ - ((x) == CMU_CLOCK_STATE_HRCACT) || \ - ((x) == CMU_CLOCK_STATE_LRCACT) || \ - ((x) == CMU_CLOCK_STATE_ULRCACT) || \ - ((x) == CMU_CLOCK_STATE_PLLACT) || \ - ((x) == CMU_CLOCK_STATE_HOSCRDY) || \ - ((x) == CMU_CLOCK_STATE_LOSCRDY) || \ - ((x) == CMU_CLOCK_STATE_HRCRDY) || \ - ((x) == CMU_CLOCK_STATE_LRCRDY) || \ - ((x) == CMU_CLOCK_STATE_PLLRDY)) -/** - * @} - */ - -/** @addtogroup CMU_Public_Functions - * @{ - */ -/** @addtogroup CMU_Public_Functions_Group1 - * @{ - */ -/* System clock configure */ -ald_status_t ald_cmu_clock_config_default(void); -ald_status_t ald_cmu_clock_config(cmu_clock_t clk, uint32_t clock); -void ald_cmu_pll1_config(cmu_pll1_input_t input, cmu_pll1_output_t output); -uint32_t ald_cmu_get_clock(void); -int32_t ald_cmu_auto_calib_clock(cmu_auto_calib_input_t input, cmu_auto_calib_output_t freq); -/** - * @} - */ - -/** @addtogroup CMU_Public_Functions_Group2 - * @{ - */ -/* BUS division control */ -void ald_cmu_div_config(cmu_bus_t bus, cmu_div_t div); -uint32_t ald_cmu_get_hclk1_clock(void); -uint32_t ald_cmu_get_sys_clock(void); -uint32_t ald_cmu_get_pclk1_clock(void); -uint32_t ald_cmu_get_pclk2_clock(void); -/** - * @} - */ - -/** @addtogroup CMU_Public_Functions_Group3 - * @{ - */ -/* Clock safe configure */ -void ald_cmu_hosc_safe_config(cmu_hosc_range_t clock, type_func_t status); -void ald_cmu_losc_safe_config(type_func_t status); -void ald_cmu_pll_safe_config(type_func_t status); -uint32_t ald_cmu_current_clock_source_get(cmu_clock_safe_type_t type); -flag_status_t ald_cmu_get_clock_state(cmu_clock_state_t sr); -void ald_cmu_irq_handler(void); -void ald_cmu_irq_cbk(cmu_security_t se); -/** - * @} - */ - -/** @addtogroup CMU_Public_Functions_Group4 - * @{ - */ -/* Clock output configure */ -void ald_cmu_output_high_clock_config(cmu_output_high_sel_t sel, - cmu_output_high_div_t div, type_func_t status); -void ald_cmu_output_low_clock_config(cmu_output_low_sel_t sel, type_func_t status); -/** - * @} - */ - -/** @addtogroup CMU_Public_Functions_Group5 - * @{ - */ -/* Peripheral Clock configure */ -void ald_cmu_buzz_config(cmu_buzz_div_t div, uint16_t dat, type_func_t status); -void ald_cmu_lptim0_clock_select(cmu_lp_perh_clock_sel_t clock); -void ald_cmu_lpuart0_clock_select(cmu_lp_perh_clock_sel_t clock); -void ald_cmu_lcd_clock_select(cmu_lcd_clock_sel_t clock); -void ald_cmu_perh_clock_config(cmu_perh_t perh, type_func_t status); -/** - * @} - */ -/** - * @} - */ - -/** - * @} - */ - -/** - * @} - */ -#ifdef __cplusplus -} -#endif - -#endif /* __ALD_CMU_H__ */ diff --git a/bsp/essemi/es32f0334/libraries/ES32F033x_ALD_StdPeriph_Driver/Include/ald_conf.h b/bsp/essemi/es32f0334/libraries/ES32F033x_ALD_StdPeriph_Driver/Include/ald_conf.h deleted file mode 100644 index 8d0931b38f..0000000000 --- a/bsp/essemi/es32f0334/libraries/ES32F033x_ALD_StdPeriph_Driver/Include/ald_conf.h +++ /dev/null @@ -1,55 +0,0 @@ -/** - ********************************************************************************* - * - * @file ald_conf.h - * @brief Enable/Disable the peripheral module. - * - * @version V1.0 - * @date 18 Apr 2017 - * @author AE Team - * @note - * - * Copyright (C) Shanghai Eastsoft Microelectronics Co. Ltd. All rights reserved. - * - ********************************************************************************* - */ - - -#ifndef __ALD_CONF_H__ -#define __ALD_CONF_H__ - - -#define ALD_DMA -#define ALD_GPIO -#define ALD_UART -#define ALD_LPUART -#define ALD_USART -#define ALD_SMARTCARD /* The ALD_SMARTCARD depend on ALD_USART */ -#define ALD_I2C -#define ALD_CMU -#define ALD_RMU -#define ALD_PMU -#define ALD_WDT -#define ALD_LCD -#define ALD_RTC -#define ALD_CAN -#define ALD_FLASH -#define ALD_ADC -#define ALD_CRC -#define ALD_CRYPT -#define ALD_TIMER -#define ALD_LPTIM -#define ALD_PIS -#define ALD_SPI -#define ALD_CALC -#define ALD_ACMP -#define ALD_OPAMP -#define ALD_TRNG -#define ALD_TEMP -#define ALD_BKPC -#define ALD_DAC -#define ALD_IAP - -#define TICK_INT_PRIORITY 3 - -#endif diff --git a/bsp/essemi/es32f0334/libraries/ES32F033x_ALD_StdPeriph_Driver/Include/ald_crc.h b/bsp/essemi/es32f0334/libraries/ES32F033x_ALD_StdPeriph_Driver/Include/ald_crc.h deleted file mode 100644 index 3ea24ea927..0000000000 --- a/bsp/essemi/es32f0334/libraries/ES32F033x_ALD_StdPeriph_Driver/Include/ald_crc.h +++ /dev/null @@ -1,196 +0,0 @@ -/** - ********************************************************************************* - * - * @file ald_crc.h - * @brief Header file of CRC module driver. - * - * @version V1.0 - * @date 6 Dec 2017 - * @author AE Team - * @note - * - * Copyright (C) Shanghai Eastsoft Microelectronics Co. Ltd. All rights reserved. - * - ********************************************************************************* - */ - -#ifndef __ALD_CRC_H__ -#define __ALD_CRC_H__ - -#ifdef __cplusplus - extern "C" { -#endif - -#include "utils.h" -#include "ald_dma.h" - -/** @addtogroup ES32FXXX_ALD - * @{ - */ - -/** @addtogroup CRC - * @{ - */ - -/** @defgroup CRC_Public_Types CRC Public Types - * @{ - */ - -/** - * @brief CRC mode - */ -typedef enum { - CRC_MODE_CCITT = 0U, /**< Ccitt */ - CRC_MODE_8 = 1U, /**< Crc8 */ - CRC_MODE_16 = 2U, /**< Crc16 */ - CRC_MODE_32 = 3U, /**< Crc32 */ -} crc_mode_t; - -/** - * @brief CRC input length - */ -typedef enum { - CRC_LEN_AUTO = 0U, /**< Auto */ - CRC_DATASIZE_8 = 1U, /**< Byte */ - CRC_DATASIZE_16 = 2U, /**< Half word */ - CRC_DATASIZE_32 = 3U, /**< Word */ -} crc_datasize_t; - -/** - * @brief CRC whether write error or no - */ -typedef enum { - CRC_WERR_NO = 0U, /**< No error */ - CRC_WERR_ERR = 1U, /**< Error */ -} crc_werr_t; - -/** - * @brief CRC state structures definition - */ -typedef enum { - CRC_STATE_RESET = 0x0U, /**< Peripheral is not initialized */ - CRC_STATE_READY = 0x1U, /**< Peripheral Initialized and ready for use */ - CRC_STATE_BUSY = 0x2U, /**< An internal process is ongoing */ - CRC_STATE_ERROR = 0x4U, /**< Error */ -} crc_state_t; - -/** - * @brief CRC init structure definition - */ -typedef struct { - crc_mode_t mode; /**< CRC mode */ - type_func_t data_rev; /**< CRC data reverse or no */ - type_func_t data_inv; /**< CRC data inverse or no */ - type_func_t chs_rev; /**< CRC check sum reverse or no */ - type_func_t chs_inv; /**< CRC check sum inverse or no */ - uint32_t seed; /**< CRC seed */ -} crc_init_t; - -/** - * @brief CRC Handle Structure definition - */ -typedef struct crc_handle_s { - CRC_TypeDef *perh; /**< Register base address */ - crc_init_t init; /**< CRC required parameters */ - uint8_t *cal_buf; /**< The pointer of preparing buffer */ - uint32_t *cal_res; /**< The pointer of result */ -#ifdef ALD_DMA - dma_handle_t hdma; /**< CRC DMA handle parameters */ -#endif - lock_state_t lock; /**< Locking object */ - crc_state_t state; /**< CRC operation state */ - - void (*cal_cplt_cbk)(struct crc_handle_s *arg); /**< Calculate completed callback */ - void (*err_cplt_cbk)(struct crc_handle_s *arg); /**< Calculate error callback */ -} crc_handle_t; -/** - * @} - */ - -/** @defgroup CRC_Public_Macros CRC Public Macros - * @{ - */ -#define CRC_ENABLE(handle) (SET_BIT((handle)->perh->CR, CRC_CR_EN_MSK)) -#define CRC_DISABLE(handle) (CLEAR_BIT((handle)->perh->CR, CRC_CR_EN_MSK)) -#define CRC_RESET(handle) (SET_BIT((handle)->perh->CR, CRC_CR_RST_MSK)) -#define CRC_DMA_ENABLE(handle) (SET_BIT((handle)->perh->CR, CRC_CR_DMAEN_MSK)) -#define CRC_DMA_DISABLE(handle) (CLEAR_BIT((handle)->perh->CR, CRC_CR_DMAEN_MSK)) -#define CRC_CLEAR_ERROR_FLAG(handle) (SET_BIT((handle)->perh->CR, CRC_CR_WERR_MSK)) -/** - * @} - */ - -/** @defgroup CRC_Private_Macros CRC Private Macros - * @{ - */ -#define IS_CRC(x) ((x) == CRC) -#define IS_CRC_MODE(x) (((x) == CRC_MODE_CCITT) || \ - ((x) == CRC_MODE_8) || \ - ((x) == CRC_MODE_16) || \ - ((x) == CRC_MODE_32)) -/** - * @} - */ - -/** @addtogroup CRC_Public_Functions - * @{ - */ - -/** @addtogroup CRC_Public_Functions_Group1 - * @{ - */ -ald_status_t ald_crc_init(crc_handle_t *hperh); -void ald_crc_reset(crc_handle_t *hperh); -/** - * @} - */ - -/** @addtogroup CRC_Public_Functions_Group2 - * @{ - */ -uint32_t ald_crc_calculate(crc_handle_t *hperh, uint8_t *buf, uint32_t size); -uint32_t ald_crc_calculate_halfword(crc_handle_t *hperh, uint16_t *buf, uint32_t size); -uint32_t ald_crc_calculate_word(crc_handle_t *hperh, uint32_t *buf, uint32_t size); -/** - * @} - */ - -#ifdef ALD_DMA -/** @addtogroup CRC_Public_Functions_Group3 - * @{ - */ -ald_status_t ald_crc_calculate_by_dma(crc_handle_t *hperh, uint8_t *buf, uint32_t *res, uint16_t size, uint8_t channel); -ald_status_t ald_crc_calculate_halfword_by_dma(crc_handle_t *hperh, uint16_t *buf, uint32_t *res, uint16_t size, uint8_t channel); -ald_status_t ald_crc_calculate_word_by_dma(crc_handle_t *hperh, uint32_t *buf, uint32_t *res, uint16_t size, uint8_t channel); -ald_status_t ald_crc_dma_pause(crc_handle_t *hperh); -ald_status_t ald_crc_dma_resume(crc_handle_t *hperh); -ald_status_t ald_crc_dma_stop(crc_handle_t *hperh); -/** - * @} - */ -#endif -/** @addtogroup CRC_Public_Functions_Group4 - * @{ - */ -crc_state_t ald_crc_get_state(crc_handle_t *hperh); -/** - * @} - */ - -/** - * @} - */ - -/** - * @} - */ - -/** - * @} - */ - -#ifdef __cplusplus -} -#endif - -#endif /* __ALD_CRC_H__ */ diff --git a/bsp/essemi/es32f0334/libraries/ES32F033x_ALD_StdPeriph_Driver/Include/ald_crypt.h b/bsp/essemi/es32f0334/libraries/ES32F033x_ALD_StdPeriph_Driver/Include/ald_crypt.h deleted file mode 100644 index 483c15a31e..0000000000 --- a/bsp/essemi/es32f0334/libraries/ES32F033x_ALD_StdPeriph_Driver/Include/ald_crypt.h +++ /dev/null @@ -1,255 +0,0 @@ -/** - ********************************************************************************* - * - * @file ald_crypt.h - * @brief Header file of CRYPT module driver. - * - * @version V1.0 - * @date 7 Dec 2017 - * @author AE Team - * @note - * - * Copyright (C) Shanghai Eastsoft Microelectronics Co. Ltd. All rights reserved. - * - ********************************************************************************* - */ - -#ifndef __ALD_CRYPT_H__ -#define __ALD_CRYPT_H__ - -#ifdef __cplusplus - extern "C" { -#endif - -#include "utils.h" -#include "ald_dma.h" - -/** @addtogroup ES32FXXX_ALD - * @{ - */ - -/** @addtogroup CRYPT - * @{ - */ - -/** @defgroup CRYPT_Public_Types CRYPT Public Types - * @{ - */ - -/** - * @brief CRYPT encrypt or decrypt select - */ -typedef enum { - CRYPT_DECRYPT = 0U, /**< Decrypt */ - CRYPT_ENCRYPT = 1U, /**< Encrypt */ -} crypt_encs_t; - -/** - * @brief CRYPT mode select - */ -typedef enum { - CRYPT_MODE_ECB = 0U, /**< ECB */ - CRYPT_MODE_CBC = 1U, /**< CBC */ - CRYPT_MODE_CTR = 2U, /**< CTR */ -} crypt_mode_t; - -/** - * @brief CRYPT data type - */ -typedef enum { - CRYPT_DATA_CHANGE_NO = 0U, /**< No exchange */ - CRYPT_DATA_CHANGE_16 = 1U, /**< 16bit exchange */ - CRYPT_DATA_CHANGE_8 = 2U, /**< 8bit exchange */ - CRYPT_DATA_CHANGE_1 = 3U, /**< 1bit exchange */ -} crypt_datatype_t; - -/** - * @brief CRYPT interrupt - */ -typedef enum { - CRYPT_IT_IT = 0x80U, /**< Interrupt */ -} crypt_it_t; - -/** - * @brief CRYPT interrupt flag - */ -typedef enum { - CRYPT_FLAG_AESIF = 0x1U, /**< Aes flag */ - CRYPT_FLAG_DONE = 0x100U, /**< Complete flag */ -} crypt_flag_t; - -/** - * @brief CRYPT state structures definition - */ -typedef enum { - CRYPT_STATE_RESET = 0x0U, /**< Peripheral is not initialized */ - CRYPT_STATE_READY = 0x1U, /**< Peripheral Initialized and ready for use */ - CRYPT_STATE_BUSY = 0x2U, /**< An internal process is ongoing */ - CRYPT_STATE_ERROR = 0x4U, /**< Error */ -} crypt_state_t; - -/** - * @brief CRYPT data type - */ -typedef enum { - DATA_32_BIT = 0U, /**< 32 bit data,don't swap */ - DATA_16_BIT = 1U, /**< 16 bit data,swap */ - DATA_8_BIT = 2U, /**< 8 bit data,swap */ - DATA_1_BIT = 3U, /**< 1 bit data, swap */ -} crypt_data_t; - -/** - * @brief CRYPT init structure definition - */ -typedef struct { - crypt_mode_t mode; /**< Crypt mode */ - crypt_data_t type; /**< Data type select */ -} crypt_init_t; - -/** - * @brief CRYPT Handle Structure definition - */ -typedef struct crypt_handle_s { - CRYPT_TypeDef *perh; /**< Register base address */ - crypt_init_t init; /**< CRYPT required parameters */ -#ifdef ALD_DMA - dma_handle_t hdma_m2p; /**< CRYPT DMA handle parameters memory to crypt module */ - dma_handle_t hdma_p2m; /**< CRYPT DMA handle parameters crypt module to memory */ -#endif - uint8_t *plain_text; /**< Pointer to plain text */ - uint8_t *cipher_text; /**< Pointer to cipher text */ - uint32_t size; /**< The size of crypt data buf */ - uint32_t count; /**< The count of crypt data buf */ - uint32_t step; /**< The step of once crypt 4(aes) */ - uint32_t dir; /**< ENCRYPT or DECRYPT */ - uint32_t iv[4]; /**< The iv of crypt */ - uint32_t key[4]; /**< The key of crypt */ - lock_state_t lock; /**< Locking object */ - crypt_state_t state; /**< CRYPT operation state */ - - void (*crypt_cplt_cbk)(struct crypt_handle_s *arg); /**< Crypt completed callback */ - void (*err_cplt_cbk)(struct crypt_handle_s *arg); /**< Crypt error callback */ -} crypt_handle_t; -/** - * @} - */ - -/** @defgroup CRYPT_Public_Macros CRYPT Public Macros - * @{ - */ -#define CRYPT_GO(handle) (SET_BIT((handle)->perh->CON, CRYPT_CON_GO_MSK)) -#define CRYPT_FIFOEN_ENABLE(handle) (SET_BIT((handle)->perh->CON, CRYPT_CON_FIFOEN_MSK)) -#define CRYPT_FIFOEN_DISABLE(handle) (CLEAR_BIT((handle)->perh->CON, CRYPT_CON_FIFOEN_MSK)) -#define CRYPT_IVEN_ENABLE(handle) (SET_BIT((handle)->perh->CON, CRYPT_CON_IVEN_MSK)) -#define CRYPT_IVEN_DISABLE(handle) (CLEAR_BIT((handle)->perh->CON, CRYPT_CON_IVEN_MSK)) -#define CRYPT_IE_ENABLE(handle) (SET_BIT((handle)->perh->CON, CRYPT_CON_IE_MSK)) -#define CRYPT_IE_DISABLE(handle) (CLEAR_BIT((handle)->perh->CON, CRYPT_CON_IE_MSK)) -#define CRYPT_DMA_ENABLE(handle) (SET_BIT((handle)->perh->CON, CRYPT_CON_DMAEN_MSK)) -#define CRYPT_DMA_DISABLE(handle) (CLEAR_BIT((handle)->perh->CON, CRYPT_CON_DMAEN_MSK)) -#define CRYPT_SETDIR(handle, dir) do {(handle)->perh->CON &= ~(0x1 << CRYPT_CON_ENCS_POS); \ - (handle)->perh->CON |= (dir << CRYPT_CON_ENCS_POS);} while (0) -#define CRYPT_WRITE_FIFO(handle, data) ((handle)->perh->FIFO = (data)) -#define CRYPT_READ_FIFO(handle) ((handle)->perh->FIFO) -/** - * @} - */ - -/** @defgroup CRYPT_Private_Macros CRYPT Private Macros - * @{ - */ -#define IS_CRYPT(x) ((x) == CRYPT) -#define IS_CRYPT_MODE(x) (((x) == CRYPT_MODE_ECB) || \ - ((x) == CRYPT_MODE_CBC) || \ - ((x) == CRYPT_MODE_CTR)) -#define IS_CRYPT_IT(x) ((x) == CRYPT_IT_IT) -#define IS_CRYPT_FLAG(x) (((x) == CRYPT_FLAG_AESIF) || \ - ((x) == CRYPT_FLAG_DONE)) -#define IS_CRYPT_IV_LEN(x) (((x) == IV_2_LEN) || \ - ((x) == IV_4_LEN)) -/** - * @} - */ - -/** @addtogroup CRYPT_Public_Functions - * @{ - */ - -/** @addtogroup CRYPT_Public_Functions_Group1 - * @{ - */ -ald_status_t ald_crypt_init(crypt_handle_t *hperh); -ald_status_t ald_crypt_write_key(crypt_handle_t *hperh, uint32_t *key); -ald_status_t ald_crypt_read_key(crypt_handle_t *hperh, uint32_t *key); -ald_status_t ald_crypt_write_ivr(crypt_handle_t *hperh, uint32_t *iv); -ald_status_t ald_crypt_read_ivr(crypt_handle_t *hperh, uint32_t *iv); -/** - * @} - */ - -/** @addtogroup CRYPT_Public_Functions_Group2 - * @{ - */ -ald_status_t ald_crypt_encrypt(crypt_handle_t *hperh, uint8_t *plain_text, uint8_t *cipher_text, uint32_t size); -ald_status_t ald_crypt_decrypt(crypt_handle_t *hperh, uint8_t *cipher_text, uint8_t *plain_text, uint32_t size); -ald_status_t ald_crypt_gcm_verify(crypt_handle_t *hperh, uint8_t *cipher_text, uint32_t size, uint8_t *aadata, uint32_t alen, uint8_t *tag); -ald_status_t ald_crypt_encrypt_by_it(crypt_handle_t *hperh, uint8_t *plain_text, uint8_t *cipher_text, uint32_t size); -ald_status_t ald_crypt_decrypt_by_it(crypt_handle_t *hperh, uint8_t *cipher_text, uint8_t *plain_text, uint32_t size); -#ifdef ALD_DMA -ald_status_t ald_crypt_encrypt_by_dma(crypt_handle_t *hperh, uint8_t *plain_text, - uint8_t *cipher_text, uint32_t size, uint8_t channel_m2p, uint8_t channel_p2m); -ald_status_t ald_crypt_decrypt_by_dma(crypt_handle_t *hperh, uint8_t *cipher_text, - uint8_t *plain_text, uint32_t size, uint8_t channel_m2p, uint8_t channel_p2m); -#endif -/** - * @} - */ - -/** @addtogroup CRYPT_Public_Functions_Group3 - * @{ - */ -#ifdef ALD_DMA -ald_status_t ald_crypt_dma_pause(crypt_handle_t *hperh); -ald_status_t ald_crypt_dma_resume(crypt_handle_t *hperh); -ald_status_t ald_crypt_dma_stop(crypt_handle_t *hperh); -#endif -void ald_crypt_irq_handler(crypt_handle_t *hperh); -/** - * @} - */ - -/** @addtogroup CRYPT_Public_Functions_Group4 - * @{ - */ -void ald_crypt_interrupt_config(crypt_handle_t *hperh, crypt_it_t it, type_func_t state); -flag_status_t ald_crypt_get_flag_status(crypt_handle_t *hperh, crypt_flag_t flag); -void ald_crypt_clear_flag_status(crypt_handle_t *hperh, crypt_flag_t flag); -it_status_t ald_crypt_get_it_status(crypt_handle_t *hperh, crypt_it_t it); -/** - * @} - */ - -/** @addtogroup CRYPT_Public_Functions_Group5 - * @{ - */ -crypt_state_t ald_crypt_get_state(crypt_handle_t *hperh); -/** - * @} - */ - -/** - * @} - */ - -/** - * @} - */ - -/** - * @} - */ - -#ifdef __cplusplus -} -#endif - -#endif diff --git a/bsp/essemi/es32f0334/libraries/ES32F033x_ALD_StdPeriph_Driver/Include/ald_dbgc.h b/bsp/essemi/es32f0334/libraries/ES32F033x_ALD_StdPeriph_Driver/Include/ald_dbgc.h deleted file mode 100644 index 3f695b7e8f..0000000000 --- a/bsp/essemi/es32f0334/libraries/ES32F033x_ALD_StdPeriph_Driver/Include/ald_dbgc.h +++ /dev/null @@ -1,156 +0,0 @@ -/** - ********************************************************************************* - * - * @file ald_dbgc.h - * @brief DEBUGCON module driver. - * - * @version V1.0 - * @date 04 Jun 2017 - * @author AE Team - * @note - * - * Copyright (C) Shanghai Eastsoft Microelectronics Co. Ltd. All rights reserved. - * - ********************************************************************************* - */ - -#ifndef __ALD_DBGC_H__ -#define __ALD_DBGC_H__ - -#ifdef __cplusplus - extern "C" { -#endif - -#include "utils.h" - - -/** @addtogroup ES32FXXX_ALD - * @{ - */ - -/** @defgroup DBGC DBGC - * @brief DBGC module driver - * @{ - */ - - - -/** @defgroup DBGC_Public_Types DBGC Public Types - * @{ - */ -/** - * @brief Debug mode select - */ -typedef enum { - DEBC_MODE_SLEEP = (1U << 0), /**< Sleep mode */ - DEBC_MODE_STOP1 = (1U << 1), /**< STOP1 mode */ - DEBC_MODE_STOP2 = (1U << 2), /**< STOP2 mode */ - DEBC_MODE_STANDBY = (1U << 3), /**< Standby mode */ -} dbgc_mode_t; - -/** - * @brief Debug peripheral select - */ -typedef enum { - DEBC_PERH_TIMER0 = (1U << 0), /**< AD16C4T0 */ - DEBC_PERH_TIMER1 = (1U << 1), /**< BS16T0 */ - DEBC_PERH_TIMER2 = (1U << 2), /**< GP16C2T0 */ - DEBC_PERH_TIMER3 = (1U << 3), /**< GP16C2T1 */ - DEBC_PERH_TIMER4 = (1U << 4), /**< BS16T1 */ - DEBC_PERH_TIMER5 = (1U << 5), /**< BS16T2 */ - DEBC_PERH_TIMER6 = (1U << 6), /**< GP16C4T0 */ - DEBC_PERH_TIMER7 = (1U << 7), /**< BS16T3 */ - DEBC_PERH_I2C0 = (1U << 8), /**< I2C0 SMBUS */ - DEBC_PERH_I2C1 = (1U << 9), /**< I2C1 SMBUS */ - DEBC_PERH_CAN = (1U << 12), /**< CAN */ - DEBC_PERH_LPTIM0 = (1U << 0) | (1U << 16), /**< LPTIM0 */ - DEBC_PERH_IWDT = (1U << 8) | (1U << 16), /**< IWDT */ - DEBC_PERH_WWDT = (1U << 9) | (1U << 16), /**< WWDT */ - DEBC_PERH_RTC = (1U << 10) | (1U << 16), /**< RTC */ -} dbgc_perh_t; -/** - * @} - */ - -/** @defgroup DBGC_Public_Functions DBGC Public Functions - * @{ - */ -/** - * @brief Gets version. - * @retval Version - */ -__INLINE uint32_t ald_dbgc_get_rev_id(void) -{ - return (DBGC->IDCODE >> 16); -} - -/** - * @brief Gets core id. - * @retval Core id - */ -__INLINE uint32_t ald_dbgc_get_core_id(void) -{ - return (DBGC->IDCODE >> 12) & 0xF; -} - -/** - * @brief Gets device id - * @retval device id - */ -__INLINE uint32_t ald_dbgc_get_device_id(void) -{ - return DBGC->IDCODE & 0xFFF; -} - -/** - * @brief Configures low power debug mode - * @param mode: The mode of low power. - * @param state: ENABLE/DISABLE - * @retval None - */ -__INLINE void ald_dbgc_mode_config(dbgc_mode_t mode, type_func_t state) -{ - if (state) - SET_BIT(DBGC->CR, mode); - else - CLEAR_BIT(DBGC->CR, mode); -} - -/** - * @brief Configures peripheral debug mode - * @param perh: The peripheral. - * @param state: ENABLE/DISABLE - * @retval None - */ -__INLINE void ald_dbgc_perh_config(dbgc_perh_t perh, type_func_t state) -{ - if ((perh >> 16) & 0x1) { - if (state) - SET_BIT(DBGC->APB2FZ, perh); - else - CLEAR_BIT(DBGC->APB2FZ, perh); - } - else { - if (state) - SET_BIT(DBGC->APB1FZ, perh); - else - CLEAR_BIT(DBGC->APB1FZ, perh); - } -} -/** - * @} - */ - -/** - * @} - */ - -/** - * @} - */ - -#ifdef __cplusplus -} -#endif - -#endif diff --git a/bsp/essemi/es32f0334/libraries/ES32F033x_ALD_StdPeriph_Driver/Include/ald_dma.h b/bsp/essemi/es32f0334/libraries/ES32F033x_ALD_StdPeriph_Driver/Include/ald_dma.h deleted file mode 100644 index 1fbebd56bf..0000000000 --- a/bsp/essemi/es32f0334/libraries/ES32F033x_ALD_StdPeriph_Driver/Include/ald_dma.h +++ /dev/null @@ -1,421 +0,0 @@ -/** - ********************************************************************************* - * - * @file ald_dma.h - * @brief DMA module Library. - * - * @version V1.0 - * @date 09 Nov 2017 - * @author AE Team - * @note - * - * Copyright (C) Shanghai Eastsoft Microelectronics Co. Ltd. All rights reserved. - * - ********************************************************************************* - */ - -#ifndef __ALD_DMA_H__ -#define __ALD_DMA_H__ - -#ifdef __cplusplus - extern "C" { -#endif - -#include "utils.h" - - -/** @addtogroup ES32FXXX_ALD - * @{ - */ - -/** @addtogroup DMA - * @{ - */ - -/** - * @defgroup DMA_Public_Macros DMA Public Macros - * @{ - */ -#define DMA_CH_COUNT 6U -#define DMA_ERR 31U -/** - * @} - */ - -/** - * @defgroup DMA_Public_Types DMA Public Types - * @{ - */ - -/** - * @brief Input source to DMA channel - * @verbatim - In this module, for the convenience of code maintenance, - TIMERx is used to indicate the sequence of the timer peripheral. - Different product series TIMERx represent different meanings: - 1. For ES32F065x series: - TIMER0 ----> AD16C4T0 - TIMER1 ----> BS16T0 - TIMER2 ----> GP16C2T0 - TIMER3 ----> GP16C2T1 - TIMER4 ----> BS16T1 - TIMER5 ----> BS16T2 - TIMER6 ----> GP16C4T0 - TIMER7 ----> BS16T3 - - 2. For ES32F033x/ES32F093x series: - TIMER0 ----> GP16C4T0 - TIMER1 ----> BS16T0 - TIMER2 ----> GP16C2T0 - TIMER3 ----> GP16C2T1 - TIMER4 ----> BS16T1 - TIMER5 ----> BS16T2 - TIMER6 ----> GP16C4T1 - TIMER7 ----> BS16T3 - @endverbatim - */ -typedef enum { - DMA_MSEL_NONE = 0x0U, /**< NONE */ - DMA_MSEL_GPIO = 0x1U, /**< GPIO */ - DMA_MSEL_CRYPT = 0x2U, /**< CRYPT */ - DMA_MSEL_ACMP = 0x3U, /**< ACMP */ - DMA_MSEL_DAC0 = 0x4U, /**< DAC0 */ - DMA_MSEL_ADC0 = 0x6U, /**< ADC0 */ - DMA_MSEL_CRC = 0x7U, /**< CRC */ - DMA_MSEL_UART0 = 0x8U, /**< UART0 */ - DMA_MSEL_UART1 = 0x9U, /**< UART1 */ - DMA_MSEL_UART2 = 0xAU, /**< UART2 */ - DMA_MSEL_UART3 = 0xBU, /**< UART3 */ - DMA_MSEL_USART0 = 0xCU, /**< USART0 */ - DMA_MSEL_USART1 = 0xDU, /**< USART1 */ - DMA_MSEL_SPI0 = 0xEU, /**< SPI0 */ - DMA_MSEL_SPI1 = 0xFU, /**< SPI1 */ - DMA_MSEL_I2C0 = 0x10U, /**< I2C0 */ - DMA_MSEL_I2C1 = 0x11U, /**< I2C1 */ - DMA_MSEL_TIMER0 = 0x12U, /**< TIMER0 */ - DMA_MSEL_TIMER1 = 0x13U, /**< TIMER1 */ - DMA_MSEL_TIMER2 = 0x14U, /**< TIMER2 */ - DMA_MSEL_TIMER3 = 0x15U, /**< TIMER3 */ - DMA_MSEL_RTC = 0x16U, /**< RTC */ - DMA_MSEL_LPTIM0 = 0x17U, /**< LPTIM0 */ - DMA_MSEL_LPUART0 = 0x18U, /**< LPUART0 */ - DMA_MSEL_DMA = 0x19U, /**< DMA */ - DMA_MSEL_SPI2 = 0x1AU, /**< SPI2 */ - DMA_MSEL_TIMER4 = 0x1BU, /**< TIMER4 */ - DMA_MSEL_TIMER5 = 0x1CU, /**< TIMER5 */ - DMA_MSEL_TIMER6 = 0x1DU, /**< TIMER6 */ - DMA_MSEL_TIMER7 = 0x1EU, /**< TIMER7 */ - DMA_MSEL_ADC1 = 0x1FU, /**< ADC1 */ - DMA_MSEL_PIS = 0x20U, /**< PIS */ - DMA_MSEL_TRNG = 0x21U, /**< TRNG */ -} dma_msel_t; - -/** - * @brief Input signal to DMA channel - */ -typedef enum { - DMA_MSIGSEL_NONE = 0x0U, /**< NONE */ - DMA_MSIGSEL_EXTI_0 = 0x0U, /**< External interrupt 0 */ - DMA_MSIGSEL_EXTI_1 = 0x1U, /**< External interrupt 1 */ - DMA_MSIGSEL_EXTI_2 = 0x2U, /**< External interrupt 2 */ - DMA_MSIGSEL_EXTI_3 = 0x3U, /**< External interrupt 3 */ - DMA_MSIGSEL_EXTI_4 = 0x4U, /**< External interrupt 4 */ - DMA_MSIGSEL_EXTI_5 = 0x5U, /**< External interrupt 5 */ - DMA_MSIGSEL_EXTI_6 = 0x6U, /**< External interrupt 6 */ - DMA_MSIGSEL_EXTI_7 = 0x7U, /**< External interrupt 7 */ - DMA_MSIGSEL_EXTI_8 = 0x8U, /**< External interrupt 8 */ - DMA_MSIGSEL_EXTI_9 = 0x9U, /**< External interrupt 9 */ - DMA_MSIGSEL_EXTI_10 = 0xAU, /**< External interrupt 10 */ - DMA_MSIGSEL_EXTI_11 = 0xBU, /**< External interrupt 11 */ - DMA_MSIGSEL_EXTI_12 = 0xCU, /**< External interrupt 12 */ - DMA_MSIGSEL_EXTI_13 = 0xDU, /**< External interrupt 13 */ - DMA_MSIGSEL_EXTI_14 = 0xEU, /**< External interrupt 14 */ - DMA_MSIGSEL_EXTI_15 = 0xFU, /**< External interrupt 15 */ - DMA_MSIGSEL_CRYPT_WRITE = 0x0U, /**< CRYPT write mode */ - DMA_MSIGSEL_CRYPT_READ = 0x1U, /**< CRYPT read mode */ - DMA_MSIGSEL_CALC_WRITE = 0x0U, /**< CALC write mode */ - DMA_MSIGSEL_CALC_READ = 0x1U, /**< CALC read mode */ - DMA_MSIGSEL_DAC0_CH0 = 0x0U, /**< DAC0 channel 0 complete */ - DMA_MSIGSEL_DAC0_CH1 = 0x1U, /**< DAC0 channel 1 complete */ - DMA_MSIGSEL_ADC = 0x0U, /**< ADC mode */ - DMA_MSIGSEL_UART_TXEMPTY = 0x0U, /**< UART transmit */ - DMA_MSIGSEL_UART_RNR = 0x1U, /**< UART receive */ - DMA_MSIGSEL_USART_RNR = 0x0U, /**< USART reveive */ - DMA_MSIGSEL_USART_TXEMPTY = 0x1U, /**< USART transmit */ - DMA_MSIGSEL_SPI_RNR = 0x0U, /**< SPI receive */ - DMA_MSIGSEL_SPI_TXEMPTY = 0x1U, /**< SPI transmit */ - DMA_MSIGSEL_I2C_RNR = 0x0U, /**< I2C receive */ - DMA_MSIGSEL_I2C_TXEMPTY = 0x1U, /**< I2C transmit */ - DMA_MSIGSEL_TIMER_CH1 = 0x0U, /**< TIM channal 1 */ - DMA_MSIGSEL_TIMER_CH2 = 0x1U, /**< TIM channal 2 */ - DMA_MSIGSEL_TIMER_CH3 = 0x2U, /**< TIM channal 3 */ - DMA_MSIGSEL_TIMER_CH4 = 0x3U, /**< TIM channal 4 */ - DMA_MSIGSEL_TIMER_TRI = 0x4U, /**< TIM trigger */ - DMA_MSIGSEL_TIMER_COMP = 0x5U, /**< TIM compare */ - DMA_MSIGSEL_TIMER_UPDATE = 0x6U, /**< TIM update */ - DMA_MSIGSEL_LPUART_RNR = 0x0U, /**< LPUART receive */ - DMA_MSIGSEL_LPUART_TXEMPTY = 0x1U, /**< LPUART transmit */ - DMA_MSIGSEL_PIS_CH0 = 0x0U, /**< PIS channal 0 */ - DMA_MSIGSEL_PIS_CH1 = 0x1U, /**< PIS channal 1 */ - DMA_MSIGSEL_PIS_CH2 = 0x2U, /**< PIS channal 2 */ - DMA_MSIGSEL_PIS_CH3 = 0x3U, /**< PIS channal 3 */ - DMA_MSIGSEL_PIS_CH4 = 0x4U, /**< PIS channal 4 */ - DMA_MSIGSEL_PIS_CH5 = 0x5U, /**< PIS channal 5 */ - DMA_MSIGSEL_PIS_CH6 = 0x6U, /**< PIS channal 6 */ - DMA_MSIGSEL_PIS_CH7 = 0x7U, /**< PIS channal 7 */ - DMA_MSIGSEL_PIS_CH8 = 0x8U, /**< PIS channal 8 */ - DMA_MSIGSEL_PIS_CH9 = 0x9U, /**< PIS channal 9 */ - DMA_MSIGSEL_PIS_CH10 = 0xAU, /**< PIS channal 10 */ - DMA_MSIGSEL_PIS_CH11 = 0xBU, /**< PIS channal 11 */ - DMA_MSIGSEL_PIS_CH12 = 0xCU, /**< PIS channal 12 */ - DMA_MSIGSEL_PIS_CH13 = 0xDU, /**< PIS channal 13 */ - DMA_MSIGSEL_PIS_CH14 = 0xEU, /**< PIS channal 14 */ - DMA_MSIGSEL_PIS_CH15 = 0xFU, /**< PIS channal 15 */ -} dma_msigsel_t; - -/** - * @brief DMA Descriptor control type - */ -typedef union { - struct { - uint32_t cycle_ctrl :3; /**< DMA operating mode @ref dma_cycle_ctrl_t */ - uint32_t next_useburst :1; /**< Uses the alternate data structure when complete a DMA cycle */ - uint32_t n_minus_1 :10; /**< Represent the total number of DMA transfers that DMA cycle contains. */ - uint32_t R_power :4; /**< Control how many DMA transfers can occur before re-arbitrates. @ref dma_arbiter_config_t */ - uint32_t src_prot_ctrl :3; /**< Control the state of HPROT when reads the source data. */ - uint32_t dst_prot_ctrl :3; /**< Control the state of HPROT when writes the destination data */ - uint32_t src_size :2; /**< Source data size @ref dma_data_size_t */ - uint32_t src_inc :2; /**< Control the source address increment. @ref dma_data_inc_t */ - uint32_t dst_size :2; /**< Destination data size. @ref dma_data_size_t */ - uint32_t dst_inc :2; /**< Destination address increment. @ref dma_data_inc_t */ - }; - uint32_t word; -} dma_ctrl_t; - -/** - * @brief Channel control data structure - */ -typedef struct { - void *src; /**< Source data end pointer */ - void *dst; /**< Destination data end pointer */ - dma_ctrl_t ctrl; /**< Control data configuration @ref dma_ctrl_t */ - uint32_t use; /**< Reserve for user */ -} dma_descriptor_t; - -/** - * @brief data increment - */ -typedef enum { - DMA_DATA_INC_BYTE = 0x0U, /**< Address increment by byte */ - DMA_DATA_INC_HALFWORD = 0x1U, /**< Address increment by halfword */ - DMA_DATA_INC_WORD = 0x2U, /**< Address increment by word */ - DMA_DATA_INC_NONE = 0x3U, /**< No increment */ -} dma_data_inc_t; - -/** - * @brief Data size - */ -typedef enum { - DMA_DATA_SIZE_BYTE = 0x0U, /**< Byte */ - DMA_DATA_SIZE_HALFWORD = 0x1U, /**< Halfword */ - DMA_DATA_SIZE_WORD = 0x2U, /**< Word */ -} dma_data_size_t; - -/** - * @brief The operating mode of the DMA cycle - */ -typedef enum { - DMA_CYCLE_CTRL_NONE = 0x0U, /**< Stop */ - DMA_CYCLE_CTRL_BASIC = 0x1U, /**< Basic */ - DMA_CYCLE_CTRL_AUTO = 0x2U, /**< Auto-request */ - DMA_CYCLE_CTRL_PINGPONG = 0x3U, /**< Ping-pong */ - DMA_CYCLE_CTRL_MEM_SG_PRIMARY = 0x4U, /**< Memory scatter-gather using the primary structure */ - DMA_CYCLE_CTRL_MEM_SG_ALTERNATE = 0x5U, /**< Memory scatter-gather using the alternate structure */ - DMA_CYCLE_CTRL_PER_SG_PRIMARY = 0x6U, /**< Peripheral scatter-gather using the primary structure */ - DMA_CYCLE_CTRL_PER_SG_ALTERNATE = 0x7U, /**< Peripheral scatter-gather using the alternate structure */ -} dma_cycle_ctrl_t; - -/** - * @brief Control how many DMA transfers can occur - * before the controller re-arbitrates - */ -typedef enum { - DMA_R_POWER_1 = 0x0U, /**< Arbitrates after each DMA transfer */ - DMA_R_POWER_2 = 0x1U, /**< Arbitrates after 2 DMA transfer */ - DMA_R_POWER_4 = 0x2U, /**< Arbitrates after 4 DMA transfer */ - DMA_R_POWER_8 = 0x3U, /**< Arbitrates after 8 DMA transfer */ - DMA_R_POWER_16 = 0x4U, /**< Arbitrates after 16 DMA transfer */ - DMA_R_POWER_32 = 0x5U, /**< Arbitrates after 32 DMA transfer */ - DMA_R_POWER_64 = 0x6U, /**< Arbitrates after 64 DMA transfer */ - DMA_R_POWER_128 = 0x7U, /**< Arbitrates after 128 DMA transfer */ - DMA_R_POWER_256 = 0x8U, /**< Arbitrates after 256 DMA transfer */ - DMA_R_POWER_512 = 0x9U, /**< Arbitrates after 512 DMA transfer */ - DMA_R_POWER_1024 = 0xAU, /**< Arbitrates after 1024 DMA transfer */ -} dma_arbiter_config_t; - -/** - * @brief Callback function pointer and param - */ -typedef struct { - void (*cplt_cbk)(void *arg); /**< DMA transfers complete callback */ - void (*err_cbk)(void* arg); /**< DMA occurs error callback */ - void *cplt_arg; /**< The parameter of cplt_cbk() */ - void *err_arg; /**< The parameter of err_cbk() */ -} dma_call_back_t; - -/** - * @brief DMA channal configure structure - */ -typedef struct { - void *src; /**< Source data begin pointer */ - void *dst; /**< Destination data begin pointer */ - uint16_t size; /**< The total number of DMA transfers that DMA cycle contains */ - dma_data_size_t data_width; /**< Data width, @ref dma_data_size_t */ - dma_data_inc_t src_inc; /**< Source increment type. @ref dma_data_inc_t */ - dma_data_inc_t dst_inc; /**< Destination increment type. @ref dma_data_inc_t */ - dma_arbiter_config_t R_power; /**< Control how many DMA transfers can occur before re-arbitrates. @ref dma_arbiter_config_t */ - type_func_t primary; /**< Use primary descriptor or alternate descriptor */ - type_func_t burst; /**< Enable/Disable the useburst setting for this channel */ - type_func_t high_prio; /**< High priority or default priority */ - type_func_t interrupt; /**< Enable/disable interrupt */ - dma_msel_t msel; /**< Input source to DMA channel @ref dma_msel_t */ - dma_msigsel_t msigsel; /**< Input signal to DMA channel @ref dma_msigsel_t */ - uint8_t channel; /**< Channel index */ -} dma_config_t; - -/** - * @brief DMA handle structure definition - */ -typedef struct { - DMA_TypeDef *perh; /**< DMA registers base address */ - dma_config_t config; /**< Channel configure structure. @ref dma_config_t */ - void (*cplt_cbk)(void *arg); /**< DMA transfers complete callback */ - void (*err_cbk)(void *arg); /**< DMA bus occurs error callback */ - void *cplt_arg; /**< The parameter of cplt_cbk() */ - void *err_arg; /**< The parameter of err_cbk() */ -} dma_handle_t; - -/** - * @brief Descriptor complete state - */ -typedef enum { - DMA_DESCP_CPLT_PRI = 0x0U, /**< Primary descriptor has been completed */ - DMA_DESCP_CPLT_ALT = 0x1U, /**< Alternate descriptor has been completed */ - DMA_DESCP_CPLT_ALL = 0x2U, /**< Both primary and alternate descriptors have been completed */ -} dma_descrp_cplt_t; -/** - * @} - */ - -/** - * @defgroup DMA_Private_Macros DMA Private Macros - * @{ - */ -#define IS_DMA_MSEL_TYPE(x) ((x) <= DMA_MSEL_TRNG) -#define IS_DMA_MSIGSEL_TYPE(x) ((x) <= 0xF) -#define IS_DMA_DATAINC_TYPE(x) (((x) == DMA_DATA_INC_BYTE) || \ - ((x) == DMA_DATA_INC_HALFWORD) || \ - ((x) == DMA_DATA_INC_WORD) || \ - ((x) == DMA_DATA_INC_NONE)) -#define IS_DMA_DATASIZE_TYPE(x) (((x) == DMA_DATA_SIZE_BYTE) || \ - ((x) == DMA_DATA_SIZE_HALFWORD) || \ - ((x) == DMA_DATA_SIZE_WORD)) -#define IS_CYCLECTRL_TYPE(x) (((x) == DMA_CYCLE_CTRL_NONE) || \ - ((x) == DMA_CYCLE_CTRL_BASIC) || \ - ((x) == DMA_CYCLE_CTRL_AUTO) || \ - ((x) == DMA_CYCLE_CTRL_PINGPONG) || \ - ((x) == DMA_CYCLE_CTRL_MEM_SG_PRIMARY) || \ - ((x) == DMA_CYCLE_CTRL_MEM_SG_ALTERNATE) || \ - ((x) == DMA_CYCLE_CTRL_PER_SG_PRIMARY) || \ - ((x) == DMA_CYCLE_CTRL_PER_SG_ALTERNATE)) -#define IS_DMA_ARBITERCONFIG_TYPE(x) (((x) == DMA_R_POWER_1) || \ - ((x) == DMA_R_POWER_2) || \ - ((x) == DMA_R_POWER_4) || \ - ((x) == DMA_R_POWER_8) || \ - ((x) == DMA_R_POWER_16) || \ - ((x) == DMA_R_POWER_32) || \ - ((x) == DMA_R_POWER_64) || \ - ((x) == DMA_R_POWER_128) || \ - ((x) == DMA_R_POWER_256) || \ - ((x) == DMA_R_POWER_512) || \ - ((x) == DMA_R_POWER_1024)) -#define IS_DMA(x) ((x) == DMA0) -#define IS_DMA_CHANNEL(x) ((x) <= 5) -#define IS_DMA_DATA_SIZE(x) ((x) <= 1024) -#define IS_DMA_IT_TYPE(x) (((x) <= 5) || ((x) == 31)) -/** - * @} - */ - -/** - * @addtogroup DMA_Public_Functions - * @{ - */ - -/** @addtogroup DMA_Public_Functions_Group1 - * @{ - */ -/* Initialization functions */ -extern void ald_dma_reset(DMA_TypeDef *DMAx); -extern void ald_dma_init(DMA_TypeDef *DMAx); -extern void ald_dma_config_struct(dma_config_t *p); -extern void ald_dma_config_sg_alt_desc(dma_descriptor_t *desc, dma_config_t *config, uint8_t memory); -/** - * @} - */ - - -/** @addtogroup DMA_Public_Functions_Group2 - * @{ - */ -/* Configure DMA channel functions */ -extern void ald_dma_config_auto(dma_handle_t *hperh); -extern void ald_dma_restart_auto(dma_handle_t *hperh, void *src, void *dst, uint16_t size); -extern void ald_dma_config_auto_easy(DMA_TypeDef *DMAx, void *src, void *dst, - uint16_t size, uint8_t channel, void (*cbk)(void *arg)); -extern void ald_dma_config_basic(dma_handle_t *hperh); -extern void ald_dma_restart_basic(dma_handle_t *hperh, void *src, void *dst, uint16_t size); -extern void ald_dma_config_basic_easy(DMA_TypeDef *DMAx, void *src, void *dst, uint16_t size, dma_msel_t msel, - dma_msigsel_t msigsel, uint8_t channel, void (*cbk)(void *arg)); -extern void ald_dma_config_ping_pong(DMA_TypeDef *DMAx, dma_config_t *config, - uint8_t first, void (*cbk)(void *arg)); -extern void ald_dma_config_sg_mem(DMA_TypeDef *DMAx, dma_descriptor_t *desc, - uint32_t nr, uint8_t channel, void (*cbk)(void *arg)); -extern void ald_dma_config_sg_per(DMA_TypeDef *DMAx, dma_descriptor_t *desc, uint32_t nr, uint8_t burst, - dma_msel_t msel, dma_msigsel_t msigsel, uint8_t channel, void (*cbk)(void *arg)); -/** - * @} - */ - -/** @addtogroup DMA_Public_Functions_Group3 - * @{ - */ -/* DMA control functions */ -extern void ald_dma_channel_config(DMA_TypeDef *DMAx, uint8_t channel, type_func_t state); -extern void ald_dma_interrupt_config(DMA_TypeDef *DMAx, uint8_t channel, type_func_t state); -extern it_status_t ald_dma_get_it_status(DMA_TypeDef *DMAx, uint8_t channel); -extern flag_status_t ald_dma_get_flag_status(DMA_TypeDef *DMAx, uint8_t channel); -extern void ald_dma_clear_flag_status(DMA_TypeDef *DMAx, uint8_t channel); -extern dma_descrp_cplt_t ald_dma_descriptor_cplt_get(DMA_TypeDef *DMAx, uint8_t channel); -extern void ald_dma_irq_handler(void); -/** - * @} - */ - -/** - * @} - */ - -/** - * @} - */ - -/** - * @} - */ - -#ifdef __cplusplus -} -#endif - -#endif /*__ALD_DMA_H__ */ diff --git a/bsp/essemi/es32f0334/libraries/ES32F033x_ALD_StdPeriph_Driver/Include/ald_flash.h b/bsp/essemi/es32f0334/libraries/ES32F033x_ALD_StdPeriph_Driver/Include/ald_flash.h deleted file mode 100644 index 8858b8b707..0000000000 --- a/bsp/essemi/es32f0334/libraries/ES32F033x_ALD_StdPeriph_Driver/Include/ald_flash.h +++ /dev/null @@ -1,127 +0,0 @@ -/** - ********************************************************************************* - * - * @file ald_flash.h - * @brief Header file of FLASH driver - * - * @version V1.0 - * @date 20 Nov 2017 - * @author AE Team - * @note - * - * Copyright (C) Shanghai Eastsoft Microelectronics Co. Ltd. All rights reserved. - * - ********************************************************************************* - */ - -#ifndef __ALD_FLASH_H__ -#define __ALD_FLASH_H__ - -#ifdef __cplusplus -extern "C" { -#endif - -#include "utils.h" - -/** @addtogroup ES32FXXX_ALD - * @{ - */ - -/** @addtogroup FLASH - * @{ - */ - -/** - * @defgroup FLASH_Private_Macros FLASH Private Macros - * @{ - */ -#define FLASH_REG_UNLOCK() \ -do { \ - if (op_cmd == OP_FLASH) { \ - WRITE_REG(MSC->FLASHKEY, 0x8ACE0246U); \ - WRITE_REG(MSC->FLASHKEY, 0x9BDF1357U); \ - } \ - else { \ - WRITE_REG(MSC->INFOKEY, 0x7153BFD9U); \ - WRITE_REG(MSC->INFOKEY, 0x0642CEA8U); \ - } \ -} while (0) -#define FLASH_REQ() (SET_BIT(MSC->FLASHCR, MSC_FLASHCR_FLASHREQ_MSK)) -#define FLASH_REQ_FIN() (CLEAR_BIT(MSC->FLASHCR, MSC_FLASHCR_FLASHREQ_MSK)) -#define FLASH_IAP_ENABLE() (SET_BIT(MSC->FLASHCR, MSC_FLASHCR_IAPEN_MSK)) -#define FLASH_IAP_DISABLE() (CLEAR_BIT(MSC->FLASHCR, MSC_FLASHCR_IAPEN_MSK)) -#define FLASH_BASE_ADDR 0x00000000U -#define FLASH_PAGE_SIZE 1024UL -#define FLASH_WORD_SIZE 8UL -#define FLASH_TOTAL_SIZE 256UL -#define FLASH_PAGE_MASK (FLASH_PAGE_SIZE - 1) -#define FLASH_WORD_MASK (FLASH_WORD_SIZE - 1) -#define IS_FLASH_ADDRESS(ADDR) ((ADDR) < (FLASH_BASE_ADDR + FLASH_PAGE_SIZE * FLASH_TOTAL_SIZE)) -#define IS_4BYTES_ALIGN(ADDR) (((uint32_t)(ADDR) & 0x3) == 0 ? 1 : 0) -#define FLASH_PAGE_ADDR(ADDR) ((ADDR) & (~FLASH_PAGE_MASK)) -#define FLASH_PAGEEND_ADDR(ADDR) ((ADDR) | FLASH_PAGE_MASK) -#define FLASH_WORD_ADDR(ADDR) ((ADDR) & (~FLASH_WORD_MASK)) -#define FLASH_WORDEND_ADDR(ADDR) ((ADDR) | FLASH_WORD_MASK) -#define INFO_PAGE_SIZE 1024UL -#define INFO_PAGE_MASK (INFO_PAGE_SIZE - 1) -#define INFO_PAGE_ADDR(ADDR) ((ADDR) & (~INFO_PAGE_MASK)) - -#ifdef USE_FLASH_FIFO - #define FLASH_FIFO 1 -#else - #define FLASH_FIFO 0 -#endif -/** - * @} - */ - -/** @defgroup FLASH_Private_Types FLASH Private Types - * @{ - */ -typedef enum { - FLASH_CMD_AE = 0x000051AEU, /**< Program area erase all */ - FLASH_CMD_PE = 0x00005EA1U, /**< Page erase */ - FLASH_CMD_WP = 0x00005DA2U, /**< Word program */ - FLASH_CMD_DATAPE = 0x00005BA4U, /**< Data flash page page erase */ - FLASH_CMD_DATAWP = 0x00005AA5U, /**< Data flash word program */ -} flash_cmd_type; - -typedef enum { - OP_FLASH = 0U, /**< Operate Pragram area */ - OP_INFO = 1U, /**< Operate info area */ -} op_cmd_type; - -/** - * @} - */ -/** @addtogroup Flash_Private_Functions - * @{ - */ -ald_status_t flash_page_erase(uint32_t addr); -ald_status_t flash_word_program(uint32_t addr, uint32_t *data, uint32_t len, uint32_t fifo); -/** - * @} - */ - -/** @addtogroup Flash_Public_Functions - * @{ - */ -ald_status_t ald_flash_read(uint32_t *ram_addr, uint32_t addr, uint16_t len); -ald_status_t ald_flash_write(uint32_t addr, uint8_t *buf, uint16_t len); -ald_status_t ald_flash_erase(uint32_t addr, uint16_t len); -/** - * @} - */ -/** - * @} - */ - -/** - * @} - */ - -#ifdef __cplusplus -} -#endif - -#endif /* __ALD_FLASH_H__ */ diff --git a/bsp/essemi/es32f0334/libraries/ES32F033x_ALD_StdPeriph_Driver/Include/ald_gpio.h b/bsp/essemi/es32f0334/libraries/ES32F033x_ALD_StdPeriph_Driver/Include/ald_gpio.h deleted file mode 100644 index 336c90f977..0000000000 --- a/bsp/essemi/es32f0334/libraries/ES32F033x_ALD_StdPeriph_Driver/Include/ald_gpio.h +++ /dev/null @@ -1,277 +0,0 @@ -/** - ********************************************************************************* - * - * @file ald_gpio.h - * @brief Header file of GPIO module driver - * - * @version V1.0 - * @date 07 Nov 2017 - * @author AE Team - * @note - * - * Copyright (C) Shanghai Eastsoft Microelectronics Co. Ltd. All rights reserved. - * - ********************************************************************************* - */ - -#ifndef __ALD_GPIO_H__ -#define __ALD_GPIO_H__ - -#ifdef __cplusplus - extern "C" { -#endif - -#include "utils.h" - - -/** @addtogroup ES32FXXX_ALD - * @{ - */ - -/** @addtogroup GPIO - * @{ - */ - -/** - * @defgroup GPIO_Public_Macros GPIO Public Macros - * @{ - */ -#define GPIO_PIN_0 (1U << 0) -#define GPIO_PIN_1 (1U << 1) -#define GPIO_PIN_2 (1U << 2) -#define GPIO_PIN_3 (1U << 3) -#define GPIO_PIN_4 (1U << 4) -#define GPIO_PIN_5 (1U << 5) -#define GPIO_PIN_6 (1U << 6) -#define GPIO_PIN_7 (1U << 7) -#define GPIO_PIN_8 (1U << 8) -#define GPIO_PIN_9 (1U << 9) -#define GPIO_PIN_10 (1U << 10) -#define GPIO_PIN_11 (1U << 11) -#define GPIO_PIN_12 (1U << 12) -#define GPIO_PIN_13 (1U << 13) -#define GPIO_PIN_14 (1U << 14) -#define GPIO_PIN_15 (1U << 15) -#define GPIO_PIN_ALL (0xFFFFU) -/** - * @} - */ - -/** - * @defgroup GPIO_Public_Types GPIO Public Types - * @{ - */ - -/** - * @brief GPIO mode - */ -typedef enum { - GPIO_MODE_CLOSE = 0x0U, /**< Digital close Analog open */ - GPIO_MODE_INPUT = 0x1U, /**< Input */ - GPIO_MODE_OUTPUT = 0x2U, /**< Output */ -} gpio_mode_t; - -/** - * @brief GPIO open-drain or push-pull - */ -typedef enum { - GPIO_PUSH_PULL = 0x0U, /**< Push-Pull */ - GPIO_OPEN_DRAIN = 0x2U, /**< Open-Drain. Can't output high level */ - GPIO_OPEN_SOURCE = 0x3U, /**< Open-Source. Can't output low level */ -} gpio_odos_t; - -/** - * @brief GPIO push-up or push-down - */ -typedef enum { - GPIO_FLOATING = 0x0U, /**< Floating */ - GPIO_PUSH_UP = 0x1U, /**< Push-Up */ - GPIO_PUSH_DOWN = 0x2U, /**< Push-Down */ - GPIO_PUSH_UP_DOWN = 0x3U, /**< Push-Up and Push-Down */ -} gpio_push_t; - -/** - * @brief GPIO output drive - */ -typedef enum { - GPIO_OUT_DRIVE_NORMAL = 0x0U, /**< Normal current flow */ - GPIO_OUT_DRIVE_STRONG = 0x1U, /**< Strong current flow */ -} gpio_out_drive_t; - -/** - * @brief GPIO filter - */ -typedef enum { - GPIO_FILTER_DISABLE = 0x0U, /**< Disable filter */ - GPIO_FILTER_ENABLE = 0x1U, /**< Enable filter */ -} gpio_filter_t; - -/** - * @brief GPIO type - */ -typedef enum { - GPIO_TYPE_CMOS = 0x0U, /**< CMOS Type */ - GPIO_TYPE_TTL = 0x1U, /**< TTL Type */ -} gpio_type_t; - -/** - * @brief GPIO functions - */ -typedef enum { - GPIO_FUNC_0 = 0U, /**< function #0 */ - GPIO_FUNC_1 = 1U, /**< function #1 */ - GPIO_FUNC_2 = 2U, /**< function #2 */ - GPIO_FUNC_3 = 3U, /**< function #3 */ - GPIO_FUNC_4 = 4U, /**< function #4 */ - GPIO_FUNC_5 = 5U, /**< function #5 */ - GPIO_FUNC_6 = 6U, /**< function #6 */ - GPIO_FUNC_7 = 7U, /**< function #7 */ -} gpio_func_t; - - -/** - * @brief GPIO Init Structure definition - */ -typedef struct { - gpio_mode_t mode; /**< Specifies the operating mode for the selected pins. - This parameter can be any value of @ref gpio_mode_t */ - gpio_odos_t odos; /**< Specifies the Open-Drain or Push-Pull for the selected pins. - This parameter can be a value of @ref gpio_odos_t */ - gpio_push_t pupd; /**< Specifies the Pull-up or Pull-Down for the selected pins. - This parameter can be a value of @ref gpio_push_t */ - gpio_out_drive_t odrv; /**< Specifies the output driver for the selected pins. - This parameter can be a value of @ref gpio_out_drive_t */ - gpio_filter_t flt; /**< Specifies the input filter for the selected pins. - This parameter can be a value of @ref gpio_filter_t */ - gpio_type_t type; /**< Specifies the type for the selected pins. - This parameter can be a value of @ref gpio_type_t */ - gpio_func_t func; /**< Specifies the function for the selected pins. - This parameter can be a value of @ref gpio_func_t */ -} gpio_init_t; - -/** - * @brief EXTI trigger style - */ -typedef enum { - EXTI_TRIGGER_RISING_EDGE = 0U, /**< Rising edge trigger */ - EXTI_TRIGGER_TRAILING_EDGE = 1U, /**< Trailing edge trigger */ - EXTI_TRIGGER_BOTH_EDGE = 2U, /**< Rising and trailing edge trigger */ -} exti_trigger_style_t; - -/** - * @brief EXTI filter clock select - */ -typedef enum { - EXTI_FILTER_CLOCK_10K = 0U, /**< cks = 10KHz */ - EXTI_FILTER_CLOCK_32K = 1U, /**< cks = 32KHz */ -} exti_filter_clock_t; - -/** - * @brief EXTI Init Structure definition - */ -typedef struct { - type_func_t filter; /**< Enable filter. */ - exti_filter_clock_t cks; /**< Filter clock select. */ - uint8_t filter_time; /**< Filter duration */ -} exti_init_t; -/** - * @} - */ - -/** - * @defgroup GPIO_Private_Macros GPIO Private Macros - * @{ - */ -#define PIN_MASK 0xFFFFU -#define UNLOCK_KEY 0x55AAU - -#define IS_GPIO_PIN(x) ((((x) & (uint16_t)0x00) == 0) && ((x) != (uint16_t)0x0)) -#define IS_GPIO_PORT(GPIOx) ((GPIOx == GPIOA) || \ - (GPIOx == GPIOB) || \ - (GPIOx == GPIOC) || \ - (GPIOx == GPIOD) || \ - (GPIOx == GPIOE) || \ - (GPIOx == GPIOF) || \ - (GPIOx == GPIOG) || \ - (GPIOx == GPIOH)) -#define IS_GPIO_MODE(x) (((x) == GPIO_MODE_CLOSE) || \ - ((x) == GPIO_MODE_INPUT) || \ - ((x) == GPIO_MODE_OUTPUT)) -#define IS_GPIO_ODOS(x) (((x) == GPIO_PUSH_PULL) || \ - ((x) == GPIO_OPEN_DRAIN) || \ - ((x) == GPIO_OPEN_SOURCE)) -#define IS_GPIO_PUPD(x) (((x) == GPIO_FLOATING) || \ - ((x) == GPIO_PUSH_UP) || \ - ((x) == GPIO_PUSH_DOWN) || \ - ((x) == GPIO_PUSH_UP_DOWN)) -#define IS_GPIO_ODRV(x) (((x) == GPIO_OUT_DRIVE_NORMAL) || \ - ((x) == GPIO_OUT_DRIVE_STRONG)) -#define IS_GPIO_FLT(x) (((x) == GPIO_FILTER_DISABLE) || \ - ((x) == GPIO_FILTER_ENABLE)) -#define IS_GPIO_TYPE(x) (((x) == GPIO_TYPE_TTL) || \ - ((x) == GPIO_TYPE_CMOS)) -#define IS_TRIGGER_STYLE(x) (((x) == EXTI_TRIGGER_RISING_EDGE) || \ - ((x) == EXTI_TRIGGER_TRAILING_EDGE) || \ - ((x) == EXTI_TRIGGER_BOTH_EDGE)) -#define IS_EXTI_FLTCKS_TYPE(x) (((x) == EXTI_FILTER_CLOCK_10K) || \ - ((x) == EXTI_FILTER_CLOCK_32K)) -#define IS_GPIO_FUNC(x) ((x) <= 7) -/** - * @} - */ - -/** @addtogroup GPIO_Public_Functions - * @{ - */ - -/** @addtogroup GPIO_Public_Functions_Group1 - * @{ - */ -void ald_gpio_init(GPIO_TypeDef *GPIOx, uint16_t pin, gpio_init_t *init); -void ald_gpio_init_default(GPIO_TypeDef *GPIOx, uint16_t pin); -void ald_gpio_func_default(GPIO_TypeDef *GPIOx); -void ald_gpio_exti_init(GPIO_TypeDef *GPIOx, uint16_t pin, exti_init_t *init); -/** - * @} - */ - -/** @addtogroup GPIO_Public_Functions_Group2 - * @{ - */ -uint8_t ald_gpio_read_pin(GPIO_TypeDef *GPIOx, uint16_t pin); -void ald_gpio_write_pin(GPIO_TypeDef *GPIOx, uint16_t pin, uint8_t val); -void ald_gpio_toggle_pin(GPIO_TypeDef *GPIOx, uint16_t pin); -void ald_gpio_toggle_dir(GPIO_TypeDef *GPIOx, uint16_t pin); -void ald_gpio_lock_pin(GPIO_TypeDef *GPIOx, uint16_t pin); -uint16_t ald_gpio_read_port(GPIO_TypeDef *GPIOx); -void ald_gpio_write_port(GPIO_TypeDef *GPIOx, uint16_t val); -/** - * @} - */ - -/** @addtogroup GPIO_Public_Functions_Group3 - * @{ - */ -void ald_gpio_exti_interrupt_config(uint16_t pin, exti_trigger_style_t style, type_func_t status); -flag_status_t ald_gpio_exti_get_flag_status(uint16_t pin); -void ald_gpio_exti_clear_flag_status(uint16_t pin); -/** - * @} - */ - -/** - * @} - */ - -/** - * @} - */ - -/** - * @} - */ -#ifdef __cplusplus -} -#endif - -#endif /* __ALD_GPIO_H__ */ diff --git a/bsp/essemi/es32f0334/libraries/ES32F033x_ALD_StdPeriph_Driver/Include/ald_i2c.h b/bsp/essemi/es32f0334/libraries/ES32F033x_ALD_StdPeriph_Driver/Include/ald_i2c.h deleted file mode 100644 index f421ff168e..0000000000 --- a/bsp/essemi/es32f0334/libraries/ES32F033x_ALD_StdPeriph_Driver/Include/ald_i2c.h +++ /dev/null @@ -1,513 +0,0 @@ -/** - ********************************************************************************* - * - * @file ald_i2c.h - * @brief Header file of I2C driver - * - * @version V1.0 - * @date 15 Nov 2017 - * @author AE Team - * @note - * - * Copyright (C) Shanghai Eastsoft Microelectronics Co. Ltd. All rights reserved. - * - ******************************************************************************** - */ - -#ifndef __ALD_I2C_H__ -#define __ALD_I2C_H__ - -#ifdef __cplusplus -extern "C" { -#endif - -#include "utils.h" -#include "ald_dma.h" -#include "ald_cmu.h" - -/** @addtogroup ES32FXXX_ALD - * @{ - */ - -/** @addtogroup I2C - * @{ - */ - -/** @defgroup I2C_Public_Types I2C Public Types - * @{ - */ -/** - * @brief I2C Error Code - */ -typedef enum { - I2C_ERROR_NONE = 0x0U, /**< No error */ - I2C_ERROR_BERR = 0x1U, /**< Berr error */ - I2C_ERROR_ARLO = 0x2U, /**< Arlo error */ - I2C_ERROR_AF = 0x4U, /**< Af error */ - I2C_ERROR_OVR = 0x8U, /**< Ovr error */ - I2C_ERROR_DMA = 0x10U, /**< Dma error */ - I2C_ERROR_TIMEOUT = 0x20U, /**< Timeout error */ -} i2c_error_t; - -/** - * @brief I2C state structure definition - */ -typedef enum { - I2C_STATE_RESET = 0x0U, /**< Peripheral is not yet Initialized */ - I2C_STATE_READY = 0x1U, /**< Peripheral Initialized and ready for use */ - I2C_STATE_BUSY = 0x2U, /**< An internal process is ongoing */ - I2C_STATE_BUSY_TX = 0x3U, /**< Data Transmission process is ongoing */ - I2C_STATE_BUSY_RX = 0x4U, /**< Data Reception process is ongoing */ - I2C_STATE_TIMEOUT = 0x5U, /**< timeout state */ - I2C_STATE_ERROR = 0x6U, /**< Error */ -} i2c_state_t; - -/** - * @brief I2C Duty Cycle - */ -typedef enum { - I2C_DUTYCYCLE_2 = 0x0U, /**< duty cycle is 2 */ - I2C_DUTYCYCLE_16_9 = 0x4000U, /**< duty cycle is 16/9 */ -} i2c_duty_t; - -/** - * @brief I2C Addressing Mode - */ -typedef enum { - I2C_ADDR_7BIT = 0x1U, /**< 7 bit address */ - I2C_ADDR_10BIT = 0x2U, /**< 10 bit address */ -} i2c_addr_t; - -/** - * @brief I2C Dual Addressing Mode - */ -typedef enum { - I2C_DUALADDR_DISABLE = 0x0U, /**< dual address is disable */ - I2C_DUALADDR_ENABLE = 0x1U, /**< dual address is enable */ -} i2c_dual_addr_t; - -/** - * @brief I2C General Call Addressing mode - */ -typedef enum { - I2C_GENERALCALL_DISABLE = 0x0U, /**< feneral call address is disable */ - I2C_GENERALCALL_ENABLE = 0x40U, /**< feneral call address is enable */ -} i2c_general_addr_t; - -/** - * @brief I2C Nostretch Mode - */ -typedef enum { - I2C_NOSTRETCH_DISABLE = 0x0U, /**< Nostretch disable */ - I2C_NOSTRETCH_ENABLE = 0x80U, /**< Nostretch enable */ -} i2c_nostretch_t; - -/** - * @brief I2C Memory Address Size - */ -typedef enum { - I2C_MEMADD_SIZE_8BIT = 0x1U, /**< 8 bit memory address size */ - I2C_MEMADD_SIZE_16BIT = 0x10U, /**< 10 bit memory address size */ -} i2c_addr_size_t; - -/** - * @brief I2C Flag Definition - */ -typedef enum { - I2C_FLAG_SB = (1U << 0), - I2C_FLAG_ADDR = (1U << 1), - I2C_FLAG_BTF = (1U << 2), - I2C_FLAG_ADD10 = (1U << 3), - I2C_FLAG_STOPF = (1U << 4), - I2C_FLAG_RXNE = (1U << 6), - I2C_FLAG_TXE = (1U << 7), - I2C_FLAG_BERR = (1U << 8), - I2C_FLAG_ARLO = (1U << 9), - I2C_FLAG_AF = (1U << 10), - I2C_FLAG_OVR = (1U << 11), - I2C_FLAG_PECERR = (1U << 12), - I2C_FLAG_TIMEOUT = (1U << 14), - I2C_FLAG_SMBALERT = (1U << 15), - I2C_FLAG_MSL = (1U << 16), - I2C_FLAG_BUSY = (1U << 17), - I2C_FLAG_TRA = (1U << 18), - I2C_FLAG_GENCALL = (1U << 20), - I2C_FLAG_SMBDEFAULT = (1U << 21), - I2C_FLAG_SMBHOST = (1U << 22), - I2C_FLAG_DUALF = (1U << 23), -} i2c_flag_t; - -/** - * @brief I2C mode structure definition - */ -typedef enum -{ - I2C_MODE_NONE = 0x0U, /**< No I2C communication on going */ - I2C_MODE_MASTER = 0x10U, /**< I2C communication is in Master mode */ - I2C_MODE_SLAVE = 0x20U, /**< I2C communication is in Slave mode */ - I2C_MODE_MEM = 0x40U, /**< I2C communication is in Memory mode */ -} i2c_mode_t; - -/** - * @brief I2C Clock - */ -typedef enum { - I2C_STANDARD_MODE_MAX_CLK = 100000U, /**< Standard mode clock */ - I2C_FAST_MODE_MAX_CLK = 400000U, /**< Fast mode clock */ -} i2c_clock_t; - -/** - * @brief Interrupt Configuration Definition - */ -typedef enum { - I2C_IT_BUF = (1U << 10), /**< Buffer interrupt */ - I2C_IT_EVT = (1U << 9), /**< Event interrupt */ - I2C_IT_ERR = (1U << 8), /**< Error interrupt */ -} i2c_interrupt_t; - -/** - * @brief I2C CON1 Register - */ -typedef enum { - I2C_CON1_PEN = (1U << 0), /**< PEN BIT */ - I2C_CON1_PMOD = (1U << 1), /**< PMOD BIT */ - I2C_CON1_SMBMOD = (1U << 3), /**< SMBMOD BIT */ - I2C_CON1_ARPEN = (1U << 4), /**< ARPEN BIT */ - I2C_CON1_PECEN = (1U << 5), /**< PECEN BIT */ - I2C_CON1_GCEN = (1U << 6), /**< GCEN BIT */ - I2C_CON1_DISCS = (1U << 7), /**< DISCS BIT */ - I2C_CON1_START = (1U << 8), /**< START BIT */ - I2C_CON1_STOP = (1U << 9), /**< STOP BIT */ - I2C_CON1_ACKEN = (1U << 10), /**< ACKEN BIT */ - I2C_CON1_POSAP = (1U << 11), /**< POSAP BIT */ - I2C_CON1_TRPEC = (1U << 12), /**< TRPEC BIT */ - I2C_CON1_ALARM = (1U << 13), /**< ALARM BIT */ - I2C_CON1_SRST = (1U << 15), /**< SRST BIT */ -} i2c_con1_t; - -/** - * @brief I2C CON2 Register - */ -typedef enum { - I2C_CON2_CLKF = 0x3FU, /**< CLKF BITS */ - I2C_CON2_CLKF_0 = (1U << 0), /**< CLKF_0 BIT */ - I2C_CON2_CLKF_1 = (1U << 1), /**< CLKF_1 BIT */ - I2C_CON2_CLKF_2 = (1U << 2), /**< CLKF_2 BIT */ - I2C_CON2_CLKF_3 = (1U << 3), /**< CLKF_3 BIT */ - I2C_CON2_CLKF_4 = (1U << 4), /**< CLKF_4 BIT */ - I2C_CON2_CLKF_5 = (1U << 5), /**< CLKF_5 BIT */ - I2C_CON2_ERRIE = (1U << 8), /**< ERRIE BIT */ - I2C_CON2_EVTIE = (1U << 9), /**< EVTIE BIT */ - I2C_CON2_BUFIE = (1U << 10), /**< BUFIE BIT */ - I2C_CON2_DMAEN = (1U << 11), /**< DMAEN BIT */ - I2C_CON2_LDMA = (1U << 12), /**< LDMA BIT */ -} i2c_con2_t; - -/** - * @brief I2C ADDR1 Register - */ -typedef enum { - I2C_ADDR1_ADDH0 = (1U << 0), /**< ADDH0 BIT */ - I2C_ADDR1_ADDH1 = (1U << 1), /**< ADDH1 BIT */ - I2C_ADDR1_ADDH2 = (1U << 2), /**< ADDH2 BIT */ - I2C_ADDR1_ADDH3 = (1U << 3), /**< ADDH3 BIT */ - I2C_ADDR1_ADDH4 = (1U << 4), /**< ADDH4 BIT */ - I2C_ADDR1_ADDH5 = (1U << 5), /**< ADDH5 BIT */ - I2C_ADDR1_ADDH6 = (1U << 6), /**< ADDH6 BIT */ - I2C_ADDR1_ADDH7 = (1U << 7), /**< ADDH7 BIT */ - I2C_ADDR1_ADDH8 = (1U << 8), /**< ADDH8 BIT */ - I2C_ADDR1_ADDH9 = (1U << 9), /**< ADDH9 BIT */ - I2C_ADDR1_ADDTYPE = (1U << 15), /**< ADDTYPE BIT */ -} i2c_addr1_t; - -/** - * @brief I2C ADDR2 Register - */ -typedef enum { - I2C_ADDR2_DUALEN = (1U << 0), /**< DUALEN BIT */ - I2C_ADDR2_ADD = (1U << 1), /**< ADD BIT */ -} i2c_addr2_t; - -/** - * @brief I2C STAT1 Register - */ -typedef enum { - I2C_STAT1_SB = (1U << 0), /**< SB BIT */ - I2C_STAT1_ADDR = (1U << 1), /**< ADDR BIT */ - I2C_STAT1_BTC = (1U << 2), /**< BTC BIT */ - I2C_STAT1_SENDADD10 = (1U << 3), /**< SENDADD10 BIT */ - I2C_STAT1_DETSTP = (1U << 4), /**< DETSTP BIT */ - I2C_STAT1_RXBNE = (1U << 6), /**< RXBNE BIT */ - I2C_STAT1_TXBE = (1U << 7), /**< TXBE BIT */ - I2C_STAT1_BUSERR = (1U << 8), /**< BUSERR BIT */ - I2C_STAT1_LARB = (1U << 9), /**< LARB BIT */ - I2C_STAT1_ACKERR = (1U << 10), /**< ACKERR BIT */ - I2C_STAT1_ROUERR = (1U << 11), /**< ROUERR BIT */ - I2C_STAT1_PECERR = (1U << 12), /**< PECERR BIT */ - I2C_STAT1_SMBTO = (1U << 14), /**< SMBTO BIT */ - I2C_STAT1_SMBALARM = (1U << 15), /**< SMBALARM BIT */ -} i2c_stat1_t; - -/** - * @brief I2C STAT2 Register - */ -typedef enum { - I2C_STAT2_MASTER = (1U << 0), /**< MASTER BIT */ - I2C_STAT2_BSYF = (1U << 1), /**< BSYF BIT */ - I2C_STAT2_TRF = (1U << 2), /**< TRF BIT */ - I2C_STAT2_RXGCF = (1U << 4), /**< RXGCF BIT */ - I2C_STAT2_SMBDEF = (1U << 5), /**< SMBDEF BIT */ - I2C_STAT2_SMBHH = (1U << 6), /**< SMBHH BIT */ - I2C_STAT2_DUALF = (1U << 7), /**< DMF BIT */ - I2C_STAT2_PECV = (1U << 8), /**< PECV BIT */ -} i2c_stat2_t; - -/** - * @brief I2C CKCFG Register - */ -typedef enum { - I2C_CKCFG_CLKSET = 0xFFFU, /**< CLKSET BITS */ - I2C_CKCFG_DUTY = (1U << 14), /**< DUTY BIT */ - I2C_CKCFG_CLKMOD = (1U << 15), /**< CLKMOD BIT */ -} i2c_ckcfg_t; - -/** - * @brief I2C RT Register - */ -typedef enum { - I2C_RT_RISET = 0x3FU, /**< RISET BITS */ -} i2c_trise_t; - -/** - * @brief I2C Configuration Structure definition - */ -typedef struct { - uint32_t clk_speed; /**< Specifies the clock frequency */ - i2c_duty_t duty; /**< Specifies the I2C fast mode duty cycle */ - uint32_t own_addr1; /**< Specifies the first device own address */ - i2c_addr_t addr_mode; /**< Specifies addressing mode */ - i2c_dual_addr_t dual_addr; /**< Specifies if dual addressing mode is selected */ - uint32_t own_addr2; /**< Specifies the second device own address */ - i2c_general_addr_t general_call; /**< Specifies if general call mode is selected */ - i2c_nostretch_t no_stretch; /**< Specifies if nostretch mode is selected */ -} i2c_init_t; - -/** - * @brief I2C handle Structure definition - */ -typedef struct i2c_handle_s { - I2C_TypeDef *perh; /**< I2C registers base address */ - i2c_init_t init; /**< I2C communication parameters */ - uint8_t *p_buff; /**< Pointer to I2C transfer buffer */ - uint16_t xfer_size; /**< I2C transfer size */ - __IO uint16_t xfer_count; /**< I2C transfer counter */ -#ifdef ALD_DMA - dma_handle_t hdmatx; /**< I2C Tx DMA handle parameters */ - dma_handle_t hdmarx; /**< I2C Rx DMA handle parameters */ -#endif - lock_state_t lock; /**< I2C locking object */ - __IO i2c_state_t state; /**< I2C communication state */ - __IO i2c_mode_t mode; /**< I2C communication mode */ - __IO uint32_t error_code; /**< I2C Error code */ - - void (*master_tx_cplt_cbk)(struct i2c_handle_s *arg); /**< Master Tx completed callback */ - void (*master_rx_cplt_cbk)(struct i2c_handle_s *arg); /**< Master Rx completed callback */ - void (*slave_tx_cplt_cbk)(struct i2c_handle_s *arg); /**< Slave Tx completed callback */ - void (*slave_rx_cplt_cbk)(struct i2c_handle_s *arg); /**< Slave Rx completed callback */ - void (*mem_tx_cplt_cbk)(struct i2c_handle_s *arg); /**< Tx to Memory completed callback */ - void (*mem_rx_cplt_cbk)(struct i2c_handle_s *arg); /**< Rx from Memory completed callback */ - void (*error_callback)(struct i2c_handle_s *arg); /**< Error callback */ -} i2c_handle_t; - -/** - * @} - */ - -/** @defgroup I2C_Public_Macro I2C Public Macros - * @{ - */ -#define I2C_RESET_HANDLE_STATE(x) ((x)->state = I2C_STATE_RESET) -#define I2C_CLEAR_ADDRFLAG(x) \ -do { \ - __IO uint32_t tmpreg; \ - tmpreg = (x)->perh->STAT1; \ - tmpreg = (x)->perh->STAT2; \ - UNUSED(tmpreg); \ -} while (0) -#define __I2C_CLEAR_STOPFLAG(x) \ -do { \ - __IO uint32_t tmpreg; \ - tmpreg = (x)->perh->STAT1; \ - tmpreg = SET_BIT((x)->perh->CON1, I2C_CON1_PEN); \ - UNUSED(tmpreg); \ -} while (0) -#define I2C_ENABLE(x) (SET_BIT((x)->perh->CON1, I2C_CON1_PEN_MSK)) -#define I2C_DISABLE(x) (CLEAR_BIT((x)->perh->CON1, I2C_CON1_PEN_MSK)) -/** - * @} - */ - -/** @defgroup I2C_Private_Macro I2C Private Macros - * @{ - */ -#define IS_I2C_TYPE(x) (((x) == I2C0) || \ - ((x) == I2C1)) -#define IS_I2C_ADDRESSING_MODE(x) (((x) == I2C_ADDR_7BIT) || \ - ((x) == I2C_ADDR_10BIT)) -#define IS_I2C_DUAL_ADDRESS(x) (((x) == I2C_DUALADDR_DISABLE) || \ - ((x) == I2C_DUALADDR_ENABLE)) -#define IS_I2C_GENERAL_CALL(x) (((x) == I2C_GENERALCALL_DISABLE) || \ - ((x) == I2C_GENERALCALL_ENABLE)) -#define IS_I2C_MEMADD_size(x) (((x) == I2C_MEMADD_SIZE_8BIT) || \ - ((x) == I2C_MEMADD_SIZE_16BIT)) -#define IS_I2C_NO_STRETCH(x) (((x) == I2C_NOSTRETCH_DISABLE) || \ - ((x) == I2C_NOSTRETCH_ENABLE)) -#define IS_I2C_OWN_ADDRESS1(x) (((x) & (uint32_t)(0xFFFFFC00)) == 0) -#define IS_I2C_OWN_ADDRESS2(x) (((x) & (uint32_t)(0xFFFFFF01)) == 0) -#define IS_I2C_CLOCK_SPEED(x) (((x) > 0) && ((x) <= I2C_FAST_MODE_MAX_CLK)) -#define IS_I2C_DUTY_CYCLE(x) (((x) == I2C_DUTYCYCLE_2) || \ - ((x) == I2C_DUTYCYCLE_16_9)) -#define IS_I2C_IT_TYPE(x) (((x) == I2C_IT_BUF) || \ - ((x) == I2C_IT_EVT) || \ - ((x) == I2C_IT_ERR)) -#define IS_I2C_FLAG(x) (((x) == I2C_FLAG_SB) || \ - ((x) == I2C_FLAG_ADDR) || \ - ((x) == I2C_FLAG_BTF) || \ - ((x) == I2C_FLAG_ADD10) || \ - ((x) == I2C_FLAG_STOPF) || \ - ((x) == I2C_FLAG_RXNE) || \ - ((x) == I2C_FLAG_TXE) || \ - ((x) == I2C_FLAG_BERR) || \ - ((x) == I2C_FLAG_ARLO) || \ - ((x) == I2C_FLAG_AF) || \ - ((x) == I2C_FLAG_OVR) || \ - ((x) == I2C_FLAG_PECERR) || \ - ((x) == I2C_FLAG_TIMEOUT) || \ - ((x) == I2C_FLAG_SMBALERT) || \ - ((x) == I2C_FLAG_MSL) || \ - ((x) == I2C_FLAG_BUSY) || \ - ((x) == I2C_FLAG_TRA) || \ - ((x) == I2C_FLAG_GENCALL) || \ - ((x) == I2C_FLAG_SMBDEFAULT) || \ - ((x) == I2C_FLAG_SMBHOST) || \ - ((x) == I2C_FLAG_DUALF)) - -#define I2C_FREQ_RANGE(x) ((x) / 1000000) -#define I2C_RISE_TIME(x, u) (((u) <= I2C_STANDARD_MODE_MAX_CLK) ? ((x) + 1) :\ - ((((x) * 300) / 1000) + 1)) -#define I2C_SPEED_STANDARD(x, y) (((((x) / ((y) << 1)) & I2C_CKCFG_CLKSET) < 4) ? 4:\ - ((x) / ((y) << 1))) -#define I2C_SPEED_FAST(x, y, z) (((z) == I2C_DUTYCYCLE_2) ? ((x) / ((y) * 3)) :\ - (((x) / ((y) * 25)) | I2C_DUTYCYCLE_16_9)) -#define I2C_SPEED(x, y, z) (((y) <= 100000) ? (I2C_SPEED_STANDARD((x), (y))) :\ - ((I2C_SPEED_FAST((x), (y), (z)) & I2C_CKCFG_CLKSET) == 0) ? 1 : \ - ((I2C_SPEED_FAST((x), (y), (z))) | I2C_CKCFG_CLKMOD)) -#define I2C_MEM_ADD_MSB(x) ((uint8_t)((uint16_t)(((uint16_t)((x) &\ - (uint16_t)(0xFF00))) >> 8))) -#define I2C_MEM_ADD_LSB(x) ((uint8_t)((uint16_t)((x) & (uint16_t)(0x00FF)))) -#define I2C_7BIT_ADD_WRITE(x) ((uint8_t)((x) & (~I2C_ADDR1_ADDH0))) -#define I2C_7BIT_ADD_READ(x) ((uint8_t)((x) | I2C_ADDR1_ADDH0)) -#define I2C_10BIT_ADDRESS(x) ((uint8_t)((uint16_t)((x) & (uint16_t)(0x00FF)))) -#define I2C_10BIT_HEADER_WRITE(x) ((uint8_t)((uint16_t)((uint16_t)(((uint16_t)((x) &\ - (uint16_t)(0x0300))) >> 7) | (uint16_t)(0xF0)))) -#define I2C_10BIT_HEADER_READ(x) ((uint8_t)((uint16_t)((uint16_t)(((uint16_t)((x) &\ - (uint16_t)(0x0300))) >> 7) | (uint16_t)(0xF1)))) -/** - * @} - */ - -/** @addtogroup I2C_Public_Functions - * @{ - */ - -/** @addtogroup I2C_Public_Functions_Group1 - * @{ - */ -ald_status_t ald_i2c_init(i2c_handle_t *hperh); -ald_status_t ald_i2c_reset(i2c_handle_t *hperh); - -/** - * @} - */ - -/** @addtogroup I2C_Public_Functions_Group2 - * @{ - */ - /** Blocking mode: Polling */ -ald_status_t ald_i2c_master_send(i2c_handle_t *hperh, uint16_t dev_addr, - uint8_t *buf, uint16_t size, uint32_t timeout); -ald_status_t ald_i2c_master_recv(i2c_handle_t *hperh, uint16_t dev_addr, - uint8_t *buf, uint16_t size, uint32_t timeout); -ald_status_t ald_i2c_slave_send(i2c_handle_t *hperh, uint8_t *buf, uint16_t size, uint32_t timeout); -ald_status_t ald_i2c_slave_recv(i2c_handle_t *hperh, uint8_t *buf, uint16_t size, uint32_t timeout); -ald_status_t ald_i2c_mem_write(i2c_handle_t *hperh, uint16_t dev_addr, uint16_t mem_addr, - i2c_addr_size_t add_size, uint8_t *buf, uint16_t size, uint32_t timeout); -ald_status_t ald_i2c_mem_read(i2c_handle_t *hperh, uint16_t dev_addr, uint16_t mem_addr, - i2c_addr_size_t add_size, uint8_t *buf, uint16_t size, uint32_t timeout); -ald_status_t ald_i2c_is_device_ready(i2c_handle_t *hperh, uint16_t dev_addr, uint32_t trials, uint32_t timeout); - - /** Non-Blocking mode: Interrupt */ -ald_status_t ald_i2c_master_send_by_it(i2c_handle_t *hperh, uint16_t dev_addr, uint8_t *buf, uint16_t size); -ald_status_t ald_i2c_master_recv_by_it(i2c_handle_t *hperh, uint16_t dev_addr, uint8_t *buf, uint16_t size); -ald_status_t ald_i2c_slave_send_by_it(i2c_handle_t *hperh, uint8_t *buf, uint16_t size); -ald_status_t ald_i2c_slave_recv_by_it(i2c_handle_t *hperh, uint8_t *buf, uint16_t size); -ald_status_t ald_i2c_mem_write_by_it(i2c_handle_t *hperh, uint16_t dev_addr, uint16_t mem_addr, - i2c_addr_size_t add_size, uint8_t *buf, uint16_t size); -ald_status_t ald_i2c_mem_read_by_it(i2c_handle_t *hperh, uint16_t dev_addr, uint16_t mem_addr, - i2c_addr_size_t add_size, uint8_t *buf, uint16_t size); - -#ifdef ALD_DMA - /** Non-Blocking mode: DMA */ -ald_status_t ald_i2c_master_send_by_dma(i2c_handle_t *hperh, uint16_t dev_addr, - uint8_t *buf, uint16_t size, uint8_t channel); -ald_status_t ald_i2c_master_recv_by_dma(i2c_handle_t *hperh, uint16_t dev_addr, - uint8_t *buf, uint16_t size, uint8_t channel); -ald_status_t ald_i2c_slave_send_by_dma(i2c_handle_t *hperh, uint8_t *buf, uint16_t size, uint8_t channel); -ald_status_t ald_i2c_slave_recv_by_dma(i2c_handle_t *hperh, uint8_t *buf, uint16_t size, uint8_t channel); -ald_status_t ald_i2c_mem_write_by_dma(i2c_handle_t *hperh, uint16_t dev_addr, uint16_t mem_addr, i2c_addr_size_t add_size, - uint8_t *buf, uint16_t size, uint8_t channel); -ald_status_t ald_i2c_mem_read_by_dma(i2c_handle_t *hperh, uint16_t dev_addr, uint16_t mem_addr, - i2c_addr_size_t add_size, uint8_t *buf, uint16_t size, uint8_t channel); -#endif -/** - * @} - */ - -/** @addtogroup I2C_Public_Functions_Group3 - * @{ - */ -i2c_state_t ald_i2c_get_state(i2c_handle_t *hperh); -uint32_t ald_i2c_get_error(i2c_handle_t *hperh); -flag_status_t ald_i2c_get_flag_status(i2c_handle_t *hperh, i2c_flag_t flag); -flag_status_t ald_i2c_get_it_status(i2c_handle_t *hperh, i2c_interrupt_t it); -void ald_i2c_clear_flag_status(i2c_handle_t *hperh, i2c_flag_t flag); -/** - * @} - */ - -/** @addtogroup I2C_Public_Functions_Group4 - * @{ - */ -void ald_i2c_interrupt_config(i2c_handle_t *hperh, i2c_interrupt_t it, type_func_t state); -void ald_i2c_ev_irq_handler(i2c_handle_t *hperh); -void ald_i2c_er_irq_handler(i2c_handle_t *hperh); -/** - * @} - */ - -/** - * @} - */ - -/** - * @} - */ - -/** - * @} - */ -#ifdef __cplusplus -} -#endif - -#endif /* __ALD_I2C_H__ */ diff --git a/bsp/essemi/es32f0334/libraries/ES32F033x_ALD_StdPeriph_Driver/Include/ald_iap.h b/bsp/essemi/es32f0334/libraries/ES32F033x_ALD_StdPeriph_Driver/Include/ald_iap.h deleted file mode 100644 index a777fca4a9..0000000000 --- a/bsp/essemi/es32f0334/libraries/ES32F033x_ALD_StdPeriph_Driver/Include/ald_iap.h +++ /dev/null @@ -1,80 +0,0 @@ -/** - ********************************************************************************* - * - * @file ald_iap.h - * @brief Header file of IAP module driver. - * - * @version V1.0 - * @date 04 Dec 2017 - * @author AE Team - * @note - * - * Copyright (C) Shanghai Eastsoft Microelectronics Co. Ltd. All rights reserved. - * - ******************************************************************************** - */ - -#ifndef __ALD_IAP_H__ -#define __ALD_IAP_H__ - -#ifdef __cplusplus -extern "C" { -#endif - -#include "utils.h" - - -/** @addtogroup ES32FXXX_ALD - * @{ - */ - -/** @addtogroup IAP - * @{ - */ - -/** - * @defgroup IAP_Private_Macros IAP Private Macros - * @{ - */ -#define IAP_WSP_ADDR 0x10000000U -#define IAP_PE_ADDR 0x10000004U -#define IAP_WP_ADDR 0x10000008U -#define IAP_DWP_ADDR 0x1000000cU -/** - * @} - */ - -/** @defgroup IAP_Private_Types IAP Private Types - * @{ - */ -typedef uint32_t (*IAP_PE)(uint32_t addr); -typedef uint32_t (*IAP_WP)(uint32_t addr, uint32_t data); -typedef uint32_t (*IAP_DWP)(uint32_t addr, uint32_t data_l, uint32_t data_h); -typedef uint32_t (*IAP_WSP)(uint32_t addr, uint8_t *data, uint32_t len, uint32_t erase); -/** - * @} - */ - -/** @addtogroup IAP_Public_Functions - * @{ - */ -uint32_t ald_iap_erase_page(uint32_t addr); -uint32_t ald_iap_program_word(uint32_t addr, uint32_t data); -uint32_t ald_iap_program_dword(uint32_t addr, uint32_t data_l, uint32_t data_h); -uint32_t ald_iap_program_words(uint32_t addr, uint8_t *data, uint32_t len, uint32_t erase); -/** - * @} - */ - -/** - * @} - */ - -/** - * @} - */ -#ifdef __cplusplus -} -#endif - -#endif /* __ALD_IAP_H__ */ diff --git a/bsp/essemi/es32f0334/libraries/ES32F033x_ALD_StdPeriph_Driver/Include/ald_lcd.h b/bsp/essemi/es32f0334/libraries/ES32F033x_ALD_StdPeriph_Driver/Include/ald_lcd.h deleted file mode 100644 index 9b14bdb67f..0000000000 --- a/bsp/essemi/es32f0334/libraries/ES32F033x_ALD_StdPeriph_Driver/Include/ald_lcd.h +++ /dev/null @@ -1,496 +0,0 @@ -/** - ********************************************************************************* - * - * @file ald_lcd.h - * @brief Header file of LCD module driver. - * - * @version V1.0 - * @date 29 Nov 2017 - * @author AE Team - * @note - * - * Copyright (C) Shanghai Eastsoft Microelectronics Co. Ltd. All rights reserved. - * - ******************************************************************************** - */ - -#ifndef __ALD_LCD_H__ -#define __ALD_LCD_H__ - -#ifdef __cplusplus -extern "C" { -#endif - -#include "utils.h" -#include "ald_cmu.h" - -/** @addtogroup ES32FXXX_ALD - * @{ - */ - -/** @addtogroup LCD - * @{ - */ - -/** @defgroup LCD_Public_Types LCD Public Types - * @{ - */ -/** - * @brief Lcd vlcd voltage type - */ -typedef enum { - LCD_VCHPS_3V2 = 0U, /**< 3.2V */ - LCD_VCHPS_3V8 = 1U, /**< 3.8V */ - LCD_VCHPS_4V8 = 2U, /**< 4.8V */ - LCD_VCHPS_5V4 = 3U, /**< 5.4V */ -} lcd_vchps_t; - -/** - * @brief Lcd function type - */ -typedef enum { - LCD_FUNC_DISABLE = 0U, /**< Lcd's function disable */ - LCD_FUNC_ENABLE = 1U, /**< Lcd's function enable */ -} lcd_func_t; - -/** - * @brief Lcd voltage type - */ -typedef enum { - LCD_VSEL_VDD = 0U, /**< VDD */ - LCD_VSEL_CP = 1U, /**< Charge pump output */ - LCD_VSEL_VLCD = 2U, /**< VLCD input */ -} lcd_vsel_t; - -/** - * @brief Lcd resistance select bit - */ -typedef enum { - LCD_RES_1MOHM = 0U, /**< 1M ohm */ - LCD_RES_2MOHM = 1U, /**< 2M ohm */ - LCD_RES_3MOHM = 2U, /**< 3M ohm */ -} lcd_res_t; - -/** - * @brief Lcd bias selector - */ -typedef enum { - LCD_BIAS_1_4 = 0U, /**< 1/4 bias */ - LCD_BIAS_1_2 = 2U, /**< 1/2 bias */ - LCD_BIAS_1_3 = 3U, /**< 1/3 bias */ -} lcd_bias_t; - -/** - * @brief Lcd duty - */ -typedef enum { - LCD_DUTY_STATIC = 0U, /**< Static duty (COM0) */ - LCD_DUTY_1_2 = 1U, /**< 1/2 duty (COM0~COM1) */ - LCD_DUTY_1_3 = 2U, /**< 1/3 duty (COM0~COM2) */ - LCD_DUTY_1_4 = 3U, /**< 1/4 duty (COM0~COM3) */ - LCD_DUTY_1_6 = 4U, /**< 1/6 duty (COM0~COM5) */ - LCD_DUTY_1_8 = 5U, /**< 1/8 duty (COM0~COM7) */ -} lcd_duty_t; - -/** - * @brief Lcd prescaler - */ -typedef enum { - LCD_PRS_1 = 0U, /**< CLKPRS = LCDCLK / 1 */ - LCD_PRS_2 = 1U, /**< CLKPRS = LCDCLK / 2 */ - LCD_PRS_4 = 2U, /**< CLKPRS = LCDCLK / 4 */ - LCD_PRS_8 = 3U, /**< CLKPRS = LCDCLK / 8 */ - LCD_PRS_16 = 4U, /**< CLKPRS = LCDCLK / 16 */ - LCD_PRS_32 = 5U, /**< CLKPRS = LCDCLK / 32 */ - LCD_PRS_64 = 6U, /**< CLKPRS = LCDCLK / 64 */ - LCD_PRS_128 = 7U, /**< CLKPRS = LCDCLK / 128 */ - LCD_PRS_256 = 8U, /**< CLKPRS = LCDCLK / 256 */ - LCD_PRS_512 = 9U, /**< CLKPRS = LCDCLK / 512 */ - LCD_PRS_1024 = 10U, /**< CLKPRS = LCDCLK / 1024 */ - LCD_PRS_2048 = 11U, /**< CLKPRS = LCDCLK / 2048 */ - LCD_PRS_4096 = 12U, /**< CLKPRS = LCDCLK / 4096 */ - LCD_PRS_8192 = 13U, /**< CLKPRS = LCDCLK / 8192 */ - LCD_PRS_16384 = 14U, /**< CLKPRS = LCDCLK / 16384 */ - LCD_PRS_32768 = 15U, /**< CLKPRS = LCDCLK / 32768 */ -} lcd_prs_t; - -/** - * @brief Lcd divider - */ -typedef enum { - LCD_DIV_16 = 0U, /**< DIVCLK = CLKPRS / 16 */ - LCD_DIV_17 = 1U, /**< DIVCLK = CLKPRS / 17 */ - LCD_DIV_18 = 2U, /**< DIVCLK = CLKPRS / 18 */ - LCD_DIV_19 = 3U, /**< DIVCLK = CLKPRS / 19 */ - LCD_DIV_20 = 4U, /**< DIVCLK = CLKPRS / 20 */ - LCD_DIV_21 = 5U, /**< DIVCLK = CLKPRS / 21 */ - LCD_DIV_22 = 6U, /**< DIVCLK = CLKPRS / 22 */ - LCD_DIV_23 = 7U, /**< DIVCLK = CLKPRS / 23 */ - LCD_DIV_24 = 8U, /**< DIVCLK = CLKPRS / 24 */ - LCD_DIV_25 = 9U, /**< DIVCLK = CLKPRS / 25 */ - LCD_DIV_26 = 10U, /**< DIVCLK = CLKPRS / 26 */ - LCD_DIV_27 = 11U, /**< DIVCLK = CLKPRS / 27 */ - LCD_DIV_28 = 12U, /**< DIVCLK = CLKPRS / 28 */ - LCD_DIV_29 = 13U, /**< DIVCLK = CLKPRS / 29 */ - LCD_DIV_30 = 14U, /**< DIVCLK = CLKPRS / 30 */ - LCD_DIV_31 = 15U, /**< DIVCLK = CLKPRS / 31 */ -} lcd_div_t; - -/** - * @brief Lcd blink mode - */ -typedef enum { - LCD_BLINK_OFF = 0U, /**< Blink disabled */ - LCD_BLINK_SEG0_COM0 = 1U, /**< Blink enabled on SEG0, COM0 */ - LCD_BLINK_SEG0_COMX2 = 2U, /**< Blink enabled on SEG0, COMx2 */ - LCD_BLINK_ALLSEG_ALLCOM = 3U, /**< Blink enabled on all SEG and all COM */ -} lcd_blink_t; - -/** - * @brief Lcd blink frequency - */ -typedef enum { - LCD_BLFRQ_8 = 0U, /**< DIVCLK / 8 */ - LCD_BLFRQ_16 = 1U, /**< DIVCLK / 16 */ - LCD_BLFRQ_32 = 2U, /**< DIVCLK / 32 */ - LCD_BLFRQ_64 = 3U, /**< DIVCLK / 64 */ - LCD_BLFRQ_128 = 4U, /**< DIVCLK / 128 */ - LCD_BLFRQ_256 = 5U, /**< DIVCLK / 256 */ - LCD_BLFRQ_512 = 6U, /**< DIVCLK / 512 */ - LCD_BLFRQ_1024 = 7U, /**< DIVCLK / 1024 */ -} lcd_blfrq_t; - -/** - * @brief Lcd dead time - */ -typedef enum { - LCD_DEAD_TIME_NONE = 0U, /**< No dead time */ - LCD_DEAD_TIME_1_DIVCLK = 1U, /**< Dead time is 1 divclk */ - LCD_DEAD_TIME_2_DIVCLK = 2U, /**< Dead time is 2 divclk */ - LCD_DEAD_TIME_3_DIVCLK = 3U, /**< Dead time is 3 divclk */ - LCD_DEAD_TIME_4_DIVCLK = 4U, /**< Dead time is 4 divclk */ - LCD_DEAD_TIME_5_DIVCLK = 5U, /**< Dead time is 5 divclk */ - LCD_DEAD_TIME_6_DIVCLK = 6U, /**< Dead time is 6 divclk */ - LCD_DEAD_TIME_7_DIVCLK = 7U, /**< Dead time is 7 divclk */ -} lcd_dead_t; - -/** - * @brief Lcd pulse keep time - */ -typedef enum { - LCD_PON_NONE = 0U, /**< No pulse keep time */ - LCD_PON_1_PRSCLK = 1U, /**< Pulse keep 1 prsclk */ - LCD_PON_2_PRSCLK = 2U, /**< Pulse keep 2 prsclk */ - LCD_PON_3_PRSCLK = 3U, /**< Pulse keep 3 prsclk */ - LCD_PON_4_PRSCLK = 4U, /**< Pulse keep 4 prsclk */ - LCD_PON_5_PRSCLK = 5U, /**< Pulse keep 5 prsclk */ - LCD_PON_6_PRSCLK = 6U, /**< Pulse keep 6 prsclk */ - LCD_PON_7_PRSCLK = 7U, /**< Pulse keep 7 prsclk */ -} lcd_pluse_on_t; - -/** - * @brief Lcd vgs select - */ -typedef enum { - LCD_VGS_0 = 0U, /**< Grey level display voltage is 30/45 vlcd */ - LCD_VGS_1 = 1U, /**< Grey level display voltage is 31/45 vlcd */ - LCD_VGS_2 = 2U, /**< Grey level display voltage is 32/45 vlcd */ - LCD_VGS_3 = 3U, /**< Grey level display voltage is 33/45 vlcd */ - LCD_VGS_4 = 4U, /**< Grey level display voltage is 34/45 vlcd */ - LCD_VGS_5 = 5U, /**< Grey level display voltage is 35/45 vlcd */ - LCD_VGS_6 = 6U, /**< Grey level display voltage is 36/45 vlcd */ - LCD_VGS_7 = 7U, /**< Grey level display voltage is 37/45 vlcd */ - LCD_VGS_8 = 8U, /**< Grey level display voltage is 38/45 vlcd */ - LCD_VGS_9 = 9U, /**< Grey level display voltage is 39/45 vlcd */ - LCD_VGS_10 = 10U, /**< Grey level display voltage is 40/45 vlcd */ - LCD_VGS_11 = 11U, /**< Grey level display voltage is 41/45 vlcd */ - LCD_VGS_12 = 12U, /**< Grey level display voltage is 42/45 vlcd */ - LCD_VGS_13 = 13U, /**< Grey level display voltage is 43/45 vlcd */ - LCD_VGS_14 = 14U, /**< Grey level display voltage is 44/45 vlcd */ - LCD_VGS_15 = 15U, /**< Grey level display voltage is equal to vlcd */ -} lcd_vgs_t; - -/** - * @brief Lcd wave choose - */ -typedef enum { - LCD_WAVE_A = 0U, /**< Wave type is A */ - LCD_WAVE_B = 1U, /**< Wave type is B */ -} lcd_wfs_t; - -/** - * @brief Lcd status select bit - */ -typedef enum { - LCD_STATUS_RDY = (1U << 0), /**< VLCD voltage state flag */ - LCD_STATUS_ENS = (1U << 1), /**< LCD Enable state flag*/ - LCD_STATUS_UDR = (1U << 2), /**< Update display request state flag */ - LCD_STATUS_FCRSF = (1U << 3), /**< LCD frame control sync flag */ - LCD_STATUS_ALL = 0xFFFFFFFU, /**< All flag */ -} lcd_status_t; - -/** - * @brief Lcd interrupt type - */ -typedef enum { - LCD_IT_SOF = (1U << 0), /**< Start of frame interrupt enable */ - LCD_IT_UDD = (1U << 1), /**< Update display done interrupt enable*/ -} lcd_it_t; - -/** - * @brief Lcd interrupt flag - */ -typedef enum { - LCD_FLAG_SOF = (1U << 0), /**< Start of frame interrupt enable flag*/ - LCD_FLAG_UDD = (1U << 1), /**< Update display done interrupt enable flag*/ -} lcd_flag_t; - -/** - * @brief Lcd interrupt type - */ -typedef enum { - SEG_0_TO_31 = 0U, /**< Segment 0 to 31 to be set */ - SEG_32_TO_59 = 1U, /**< Segment 32 to 59 to be set */ -} lcd_seg_t; - -/** - * @brief Lcd configure - */ -typedef struct -{ - lcd_vsel_t lcd_vsel; /**< Lcd power choose */ - lcd_vchps_t lcd_vchps; /**< Charge pump voltage choose */ - lcd_func_t lcd_vbufld; /**< Low drive mode function */ - lcd_func_t lcd_vbufhd; /**< High drive mode function */ - uint32_t lcd_dsld; /**< Low drive mode level */ - uint32_t lcd_dshd; /**< High drive mode level */ - lcd_res_t lcd_resld; /**< Low dirve mode resistance choose */ - lcd_res_t lcd_reshd; /**< High dirve mode resistance choose */ - lcd_bias_t lcd_bias; /**< LCD bias */ - lcd_duty_t lcd_duty; /**< LCD duty */ - lcd_wfs_t lcd_wfs; /**< Wave choose */ - lcd_prs_t lcd_prs; /**< Lcd clock prs */ - lcd_div_t lcd_div; /**< Lcd div */ - lcd_dead_t lcd_dead; /**< Lcd dead time */ - lcd_pluse_on_t lcd_pon; /**< Lcd pluse on time */ - lcd_vgs_t lcd_vgs; /**< Lcd gray level display voltage */ - cmu_lcd_clock_sel_t clock; /**< Lcd clock choose */ -} lcd_init_t; - -/** - * @brief Lcd handle Structure definition - */ -typedef struct lcd_handle_s { - LCD_TypeDef *perh; /**< LCD registers base address */ - lcd_init_t init; /**< LCD initialize parameters */ - lock_state_t lock; /**< Locking object */ - - void (*display_cplt_cbk)(struct lcd_handle_s *arg); /**< Display completed callback */ - void (*frame_start_cbk)(struct lcd_handle_s *arg); /**< Frame start callback */ -} lcd_handle_t; - -/** - * @} - */ - -/** @defgroup LCD_Public_Macro LCD Public Macros - * @{ - */ -#define LCD_HD_ENABLE(x) (SET_BIT((x)->perh->FCR, LCD_FCR_HD_MSK)) -#define LCD_HD_DISABLE(x) (CLEAR_BIT((x)->perh->FCR, LCD_FCR_HD_MSK)) -/** - * @} - */ - -/** - * @defgroup LCD_Private_Macros LCD Private Macros - * @{ - */ -#define IS_LCD_PERH_TYPE(x) ((x) == LCD) -#define IS_LCD_VCHPS_TYPE(x) (((x) == LCD_VCHPS_3V2) || \ - ((x) == LCD_VCHPS_3V8) || \ - ((x) == LCD_VCHPS_4V8) || \ - ((x) == LCD_VCHPS_5V4)) -#define IS_LCD_VSEL_TYPE(x) (((x) == LCD_VSEL_VDD) || \ - ((x) == LCD_VSEL_CP) || \ - ((x) == LCD_VSEL_VLCD)) -#define IS_LCD_FUNC_TYPE(x) (((x) == LCD_FUNC_DISABLE) || \ - ((x) == LCD_FUNC_ENABLE)) -#define IS_LCD_LEVEL_TYPE(x) (((x) > 0) | ((x) <= 0xF)) -#define IS_LCD_RES_TYPE(x) (((x) == LCD_RES_1MOHM) || \ - ((x) == LCD_RES_2MOHM) || \ - ((x) == LCD_RES_3MOHM)) -#define IS_LCD_BIAS_TYPE(x) (((x) == LCD_BIAS_1_4) || \ - ((x) == LCD_BIAS_1_2) || \ - ((x) == LCD_BIAS_1_3)) -#define IS_LCD_DUTY_TYPE(x) (((x) == LCD_DUTY_STATIC) || \ - ((x) == LCD_DUTY_1_2) || \ - ((x) == LCD_DUTY_1_3) || \ - ((x) == LCD_DUTY_1_4) || \ - ((x) == LCD_DUTY_1_6) || \ - ((x) == LCD_DUTY_1_8)) -#define IS_LCD_WFS_TYPE(x) (((x) == LCD_WAVE_A) || \ - ((x) == LCD_WAVE_B)) -#define IS_LCD_PRS_TYPE(x) (((x) == LCD_PRS_1) || \ - ((x) == LCD_PRS_2) || \ - ((x) == LCD_PRS_4) || \ - ((x) == LCD_PRS_8) || \ - ((x) == LCD_PRS_16) || \ - ((x) == LCD_PRS_32) || \ - ((x) == LCD_PRS_64) || \ - ((x) == LCD_PRS_128) || \ - ((x) == LCD_PRS_256) || \ - ((x) == LCD_PRS_512) || \ - ((x) == LCD_PRS_1024) || \ - ((x) == LCD_PRS_2048) || \ - ((x) == LCD_PRS_4096) || \ - ((x) == LCD_PRS_8192) || \ - ((x) == LCD_PRS_16384) || \ - ((x) == LCD_PRS_32768)) -#define IS_LCD_DIV_TYPE(x) (((x) == LCD_DIV_16) || \ - ((x) == LCD_DIV_17) || \ - ((x) == LCD_DIV_18) || \ - ((x) == LCD_DIV_19) || \ - ((x) == LCD_DIV_20) || \ - ((x) == LCD_DIV_21) || \ - ((x) == LCD_DIV_22) || \ - ((x) == LCD_DIV_23) || \ - ((x) == LCD_DIV_24) || \ - ((x) == LCD_DIV_25) || \ - ((x) == LCD_DIV_26) || \ - ((x) == LCD_DIV_27) || \ - ((x) == LCD_DIV_28) || \ - ((x) == LCD_DIV_29) || \ - ((x) == LCD_DIV_30) || \ - ((x) == LCD_DIV_31)) -#define IS_LCD_BLINK_MODE(x) (((x) == LCD_BLINK_OFF) || \ - ((x) == LCD_BLINK_SEG0_COM0) || \ - ((x) == LCD_BLINK_SEG0_COMX2) || \ - ((x) == LCD_BLINK_ALLSEG_ALLCOM)) -#define IS_LCD_BLFRQ_TYPE(x) (((x) == LCD_BLFRQ_8) || \ - ((x) == LCD_BLFRQ_16) || \ - ((x) == LCD_BLFRQ_32) || \ - ((x) == LCD_BLFRQ_64) || \ - ((x) == LCD_BLFRQ_128) || \ - ((x) == LCD_BLFRQ_256) || \ - ((x) == LCD_BLFRQ_512) || \ - ((x) == LCD_BLFRQ_1024)) -#define IS_LCD_STATUS_TYPE(x) (((x) == LCD_STATUS_RDY) || \ - ((x) == LCD_STATUS_ENS) || \ - ((x) == LCD_STATUS_UDR) || \ - ((x) == LCD_STATUS_FCRSF) || \ - ((x) == LCD_STATUS_ALL)) -#define IS_LCD_CLEARFLAG_TYPE(x)(((x) == LCD_FLAG_SOF) || \ - ((x) == LCD_FLAG_UDD) || \ - ((x) == LCD_STATUS_ALL)) -#define IS_LCD_IT_TYPE(x) (((x) == LCD_IT_SOF) || \ - ((x) == LCD_IT_UDD)) -#define IS_LCD_FLAG_TYPE(x) (((x) == LCD_FLAG_SOF) || \ - ((x) == LCD_FLAG_UDD)) -#define IS_LCD_SEG_TYPE(x) (((x) == SEG_0_TO_31) || \ - ((x) == SEG_32_TO_59)) -#define IS_LCD_DEAD_TYPE(x) (((x) == LCD_DEAD_TIME_NONE) || \ - ((x) == LCD_DEAD_TIME_1_DIVCLK) || \ - ((x) == LCD_DEAD_TIME_2_DIVCLK) || \ - ((x) == LCD_DEAD_TIME_3_DIVCLK) || \ - ((x) == LCD_DEAD_TIME_4_DIVCLK) || \ - ((x) == LCD_DEAD_TIME_5_DIVCLK) || \ - ((x) == LCD_DEAD_TIME_6_DIVCLK) || \ - ((x) == LCD_DEAD_TIME_7_DIVCLK)) -#define IS_LCD_PON_TYPE(x) (((x) == LCD_PON_NONE) || \ - ((x) == LCD_PON_1_PRSCLK) || \ - ((x) == LCD_PON_2_PRSCLK) || \ - ((x) == LCD_PON_3_PRSCLK) || \ - ((x) == LCD_PON_4_PRSCLK) || \ - ((x) == LCD_PON_5_PRSCLK) || \ - ((x) == LCD_PON_6_PRSCLK) || \ - ((x) == LCD_PON_7_PRSCLK)) -#define IS_LCD_VGS_TYPE(x) (((x) == LCD_VGS_0) || \ - ((x) == LCD_VGS_1) || \ - ((x) == LCD_VGS_2) || \ - ((x) == LCD_VGS_3) || \ - ((x) == LCD_VGS_4) || \ - ((x) == LCD_VGS_5) || \ - ((x) == LCD_VGS_6) || \ - ((x) == LCD_VGS_7) || \ - ((x) == LCD_VGS_8) || \ - ((x) == LCD_VGS_9) || \ - ((x) == LCD_VGS_10) || \ - ((x) == LCD_VGS_11) || \ - ((x) == LCD_VGS_12) || \ - ((x) == LCD_VGS_13) || \ - ((x) == LCD_VGS_14) || \ - ((x) == LCD_VGS_15)) -#define IS_LCD_BUFFER_TYPE(x) ((x) <= 15) - -/** - * @} - */ - -/** @addtogroup LCD_Public_Functions - * @{ - */ - -/** - * @addtogroup LCD_Public_Functions_Group1 - * @{ - */ -/* Initialization and enable functions */ -ald_status_t ald_lcd_init(lcd_handle_t *hperh); -ald_status_t ald_lcd_cmd(lcd_handle_t *hperh, type_func_t state); -/** - * @} - */ - -/** - * @addtogroup LCD_Public_Functions_Group2 - * @{ - */ -/* Config output and blink function */ -ald_status_t ald_lcd_blink_config(lcd_handle_t *hperh, lcd_blink_t blink_mode, lcd_blfrq_t blink_freq); -ald_status_t ald_lcd_write(lcd_handle_t *hperh, uint8_t buf, uint32_t buf_data); -ald_status_t ald_lcd_write_seg(lcd_handle_t *hperh, lcd_seg_t seg, uint32_t seg_data); -/** - * @} - */ - -/** - * @addtogroup LCD_Public_Functions_Group3 - * @{ - */ -/* Query lcd status function */ -uint32_t ald_lcd_get_status(lcd_handle_t *hperh, lcd_status_t lcd_flag); -/** - * @} - */ - -/** - * @addtogroup LCD_Public_Functions_Group4 - * @{ - */ -/* Interrupt function */ -ald_status_t ald_lcd_interrupt_config(lcd_handle_t *hperh, lcd_it_t it, type_func_t state); -flag_status_t ald_lcd_get_it_status(lcd_handle_t *hperh, lcd_it_t it); -it_status_t ald_lcd_get_flag_status(lcd_handle_t *hperh, lcd_flag_t flag); -ald_status_t ald_lcd_clear_flag_status(lcd_handle_t *hperh, lcd_flag_t flag); -void ald_lcd_irq_handler(lcd_handle_t *hperh); -/** - * @} - */ - -/** - * @} - */ - -/** - * @} - */ - -/** - * @} - */ -#ifdef __cplusplus -} -#endif - -#endif /* __ALD_LCD_H__ */ diff --git a/bsp/essemi/es32f0334/libraries/ES32F033x_ALD_StdPeriph_Driver/Include/ald_lptim.h b/bsp/essemi/es32f0334/libraries/ES32F033x_ALD_StdPeriph_Driver/Include/ald_lptim.h deleted file mode 100644 index dc570df1c5..0000000000 --- a/bsp/essemi/es32f0334/libraries/ES32F033x_ALD_StdPeriph_Driver/Include/ald_lptim.h +++ /dev/null @@ -1,370 +0,0 @@ -/** - ********************************************************************************* - * - * @file ald_lptim.c - * @brief LPTIM module driver. - * This is the common part of the LPTIM initialization - * - * @version V1.0 - * @date 09 Nov 2017 - * @author AE Team - * @note - * - * Copyright (C) Shanghai Eastsoft Microelectronics Co. Ltd. All rights reserved. - * - ********************************************************************************* - */ - -#ifndef __ALD_LPTIM_H__ -#define __ALD_LPTIM_H__ - -#ifdef __cplusplus - extern "C" { -#endif - -#include "utils.h" -#include "ald_cmu.h" - - -/** @addtogroup ES32FXXX_ALD - * @{ - */ - -/** @addtogroup LPTIM - * @{ - */ - -/** @defgroup LPTIM_Public_Types LPTIM Public Types - * @{ - */ - -/** - * @brief LPTIM clock select - */ -typedef enum { - LPTIM_CKSEL_INTERNAL = 0U, /**< Select internal clock */ - LPTIM_CKSEL_EXTERNAL = 1U, /**< Select external clock */ -} lptim_cksel_t; - -/** - * @brief LPTIM clock pol - */ -typedef enum { - LPTIM_CKPOL_RISING = 0U, /**< using rising edge */ - LPTIM_CKPOL_FALLING = 1U, /**< using falling edge */ -} lptim_ckpol_t; - -/** - * @brief LPTIM clock fliter - */ -typedef enum { - LPTIM_CKFLT_0 = 0U, /**< not clock filter */ - LPTIM_CKFLT_2 = 1U, /**< 2 cycle filter */ - LPTIM_CKFLT_4 = 2U, /**< 4 cycle filter */ - LPTIM_CKFLT_8 = 3U, /**< 8 cycle filter */ -} lptim_ckflt_t; - -/** - * @brief LPTIM trigger fliter - */ -typedef enum { - LPTIM_TRGFLT_0 = 0U, /**< not clock filter */ - LPTIM_TRGFLT_2 = 1U, /**< 2 cycle filter */ - LPTIM_TRGFLT_4 = 2U, /**< 4 cycle filter */ - LPTIM_TRGFLT_8 = 3U, /**< 8 cycle filter */ -} lptim_trgflt_t; - -/** - * @brief LPTIM prescaler - */ -typedef enum { - LPTIM_PRESC_1 = 0U, /**< No prescaler is used */ - LPTIM_PRESC_2 = 1U, /**< Clock is divided by 2 */ - LPTIM_PRESC_4 = 2U, /**< Clock is divided by 4 */ - LPTIM_PRESC_8 = 3U, /**< Clock is divided by 8 */ - LPTIM_PRESC_16 = 4U, /**< Clock is divided by 16 */ - LPTIM_PRESC_32 = 5U, /**< Clock is divided by 32 */ - LPTIM_PRESC_64 = 6U, /**< Clock is divided by 64 */ - LPTIM_PRESC_128 = 7U, /**< Clock is divided by 128 */ -} lptim_presc_t; - -/** - * @brief LPTIM trig select - */ -typedef enum { - LPTIM_TRIGSEL_EXT0 = 0U, /**< Trigger select external channel 0 */ - LPTIM_TRIGSEL_EXT1 = 1U, /**< Trigger select external channel 1 */ - LPTIM_TRIGSEL_EXT2 = 2U, /**< Trigger select external channel 2 */ - LPTIM_TRIGSEL_EXT3 = 3U, /**< Trigger select external channel 3 */ - LPTIM_TRIGSEL_EXT4 = 4U, /**< Trigger select external channel 4 */ - LPTIM_TRIGSEL_EXT5 = 5U, /**< Trigger select external channel 5 */ - LPTIM_TRIGSEL_EXT6 = 6U, /**< Trigger select external channel 6 */ - LPTIM_TRIGSEL_EXT7 = 7U, /**< Trigger select external channel 7 */ -} lptim_trigsel_t; - -/** - * @brief LPTIM start mode select - */ -typedef enum { - LPTIM_MODE_SINGLE = 0U, /**< Start single mode */ - LPTIM_MODE_CONTINUOUS = 1U, /**< Start continuous mode */ -} lptim_mode_t; - -/** - * @brief LPTIM trig en - */ -typedef enum { - LPTIM_TRIGEN_SW = 0U, /**< software trigger */ - LPTIM_TRIGEN_RISING = 1U, /**< rising edge trigger */ - LPTIM_TRIGEN_FALLING = 2U, /**< falling edge trigger */ - LPTIM_TRIGEN_BOTH = 3U, /**< rising and falling edge trigger */ -} lptim_trigen_t; - -/** - * @brief LPTIM wave - */ -typedef enum { - LPTIM_WAVE_NONE = 0U, /**< Output close */ - LPTIM_WAVE_TOGGLE = 1U, /**< Output toggle */ - LPTIM_WAVE_PULSE = 2U, /**< Output pulse */ - LPTIM_WAVE_PWM = 3U, /**< Output PWM */ -} lptim_wave_t; - -/** - * @brief LPTIM interrupt - */ -typedef enum { - LPTIM_IT_CMPMAT = 1U, /**< Compare interrupt bit */ - LPTIM_IT_ARRMAT = 2U, /**< Update interrupt bit */ - LPTIM_IT_EXTTRIG = 4U, /**< external trigger interrupt bit */ -} lptim_it_t; - -/** - * @brief LPTIM Interrupt flag - */ -typedef enum { - LPTIM_FLAG_CMPMAT = 1U, /**< Compare interrupt flag */ - LPTIM_FLAG_ARRMAT = 2U, /**< Update interrupt flag */ - LPTIM_FLAG_EXTTRIG = 4U, /**< Update interrupt flag */ -} lptim_flag_t; - -/** - * @brief LPTIM state structures definition - */ -typedef enum { - LPTIM_STATE_RESET = 0x00U, /**< Peripheral not yet initialized or disabled */ - LPTIM_STATE_READY = 0x01U, /**< Peripheral Initialized and ready for use */ - LPTIM_STATE_BUSY = 0x02U, /**< An internal process is ongoing */ - LPTIM_STATE_TIMEOUT = 0x03U, /**< Timeout state */ - LPTIM_STATE_ERROR = 0x04U, /**< Reception process is ongoing */ -} lptim_state_t; - -/** - * @brief LPTIM Init Structure definition - */ -typedef struct { - lptim_presc_t psc; /**< Specifies the prescaler value */ - uint16_t arr; /**< Specifies the update value */ - uint16_t cmp; /**< Specifies the compare value */ - cmu_lp_perh_clock_sel_t clock; /**< Specifies the clock choose */ - lptim_mode_t mode; /**< Specifies the start mode */ -} lptim_init_t; - -/** - * @brief LPTIM trigger Structure definition - */ -typedef struct { - lptim_trigen_t mode; /**< Specifies the trigger mode */ - lptim_trigsel_t sel; /**< Specifies the trigger source select */ -} lptim_trigger_init_t; - -/** - * @brief LPTIM trigger Structure definition - */ -typedef struct { - lptim_cksel_t sel; /**< Specifies the clock select */ - lptim_ckpol_t polarity; /**< Specifies the clock polarity */ -} lptim_clock_source_init_t; - -/** - * @brief LPTIM Handle Structure definition - */ -typedef struct lptim_handle_s { - LPTIM_TypeDef *perh; /**< Register base address */ - lptim_init_t init; /**< LPTIM Time required parameters */ - lock_state_t lock; /**< Locking object */ - lptim_state_t state; /**< LPTIM operation state */ - - void (*trig_cbk)(struct lptim_handle_s *arg); /**< Trigger callback */ - void (*update_cbk)(struct lptim_handle_s *arg); /**< Update callback */ - void (*cmp_cbk)(struct lptim_handle_s *arg); /**< Compare callback */ -} lptim_handle_t; -/** - * @} - */ - -/** @defgroup LPTIM_Public_Macros LPTIM Public Macros - * @{ - */ -#define LPTIM_ENABLE(x) (SET_BIT((x)->perh->CON1, LP16T_CON1_ENABLE_MSK)) -#define LPTIM_DISABLE(x) (CLEAR_BIT((x)->perh->CON1, LP16T_CON1_ENABLE_MSK)) -#define LPTIM_CNTSTART(x) (SET_BIT((x)->perh->CON1, LP16T_CON1_CNTSTRT_MSK)) -#define LPTIM_SNGSTART(x) (SET_BIT((x)->perh->CON1, LP16T_CON1_SNGSTRT_MSK)) -#define LPTIM_UPDATE_ENABLE(x) (SET_BIT((x)->perh->UPDATE, LP16T_UPDATE_UDIS_MSK)) -#define LPTIM_UPDATE_DISABLE(x) (CLEAR_BIT((x)->perh->UPDATE, LP16T_UPDATE_UDIS_MSK)) -#define LPTIM_PRELOAD_IMM(x) (SET_BIT((x)->perh->CR0, LP16T_CON0_PRELOAD_MSK)) -#define LPTIM_PRELOAD_WAIT(x) (CLEAR_BIT((x)->perh->CR0, LP16T_CON0_PRELOAD_MSK)) -#define LPTIM_WAVEPOL_NORMAL(x) (MODIFY_REG((x)->perh->CR0, LP16T_CON0_WAVE_MSK, 0 << LP16T_CON0_WAVE_POSS)) -#define LPTIM_WAVEPOL_INVERSE(x) (MODIFY_REG((x)->perh->CR0, LP16T_CON0_WAVE_MSK, 1 << LP16T_CON0_WAVE_POSS)) -/** - * @} - */ - -/** @defgroup LPTIM_Private_Macros LPTIM Private Macros - * @{ - */ -#define IS_LPTIM(x) ((x) == LPTIM0) -#define IS_LPTIM_CKSEL(x) (((x) == LPTIM_CKSEL_INTERNAL) || \ - ((x) == LPTIM_CKSEL_EXTERNAL)) -#define IS_LPTIM_CKPOL(x) (((x) == LPTIM_CKPOL_RISING) || \ - ((x) == LPTIM_CKPOL_FALLING)) -#define IS_LPTIM_MODE(x) (((x) == LPTIM_MODE_SINGLE) || \ - ((x) == LPTIM_MODE_CONTINUOUS)) -#define IS_LPTIM_CKFLT(x) (((x) == LPTIM_CKFLT_0) || \ - ((x) == LPTIM_CKFLT_2) || \ - ((x) == LPTIM_CKFLT_4) || \ - ((x) == LPTIM_CKFLT_8)) -#define IS_LPTIM_TRGFLT(x) (((x) == LPTIM_TRGFLT_0) || \ - ((x) == LPTIM_TRGFLT_2) || \ - ((x) == LPTIM_TRGFLT_4) || \ - ((x) == LPTIM_TRGFLT_8)) -#define IS_LPTIM_PRESC(x) (((x) == LPTIM_PRESC_1) || \ - ((x) == LPTIM_PRESC_2) || \ - ((x) == LPTIM_PRESC_4) || \ - ((x) == LPTIM_PRESC_8) || \ - ((x) == LPTIM_PRESC_16) || \ - ((x) == LPTIM_PRESC_32) || \ - ((x) == LPTIM_PRESC_64) || \ - ((x) == LPTIM_PRESC_128)) -#define IS_LPTIM_TRIGSEL(x) (((x) == LPTIM_TRIGSEL_EXT0) || \ - ((x) == LPTIM_TRIGSEL_EXT1) || \ - ((x) == LPTIM_TRIGSEL_EXT2) || \ - ((x) == LPTIM_TRIGSEL_EXT3) || \ - ((x) == LPTIM_TRIGSEL_EXT4) || \ - ((x) == LPTIM_TRIGSEL_EXT5) || \ - ((x) == LPTIM_TRIGSEL_EXT6) || \ - ((x) == LPTIM_TRIGSEL_EXT7)) -#define IS_LPTIM_TRIGEN(x) (((x) == LPTIM_TRIGEN_SW) || \ - ((x) == LPTIM_TRIGEN_RISING) || \ - ((x) == LPTIM_TRIGEN_FALLING) || \ - ((x) == LPTIM_TRIGEN_BOTH)) -#define IS_LPTIM_IT(x) (((x) == LPTIM_IT_CMPMAT) || \ - ((x) == LPTIM_IT_ARRMAT) || \ - ((x) == LPTIM_IT_EXTTRIG)) -#define IS_LPTIM_FLAG(x) (((x) == LPTIM_FLAG_CMPMAT) || \ - ((x) == LPTIM_FLAG_ARRMAT) || \ - ((x) == LPTIM_FLAG_EXTTRIG)) -/** - * @} - */ - -/** @addtogroup LPTIM_Public_Functions - * @{ - */ - -/** @addtogroup LPTIM_Public_Functions_Group1 - * @{ - */ -void ald_lptim_reset(lptim_handle_t *hperh); -void ald_lptim_trigger_config(lptim_handle_t *hperh, lptim_trigger_init_t *config); -void ald_lptim_clock_source_config(lptim_handle_t *hperh, lptim_clock_source_init_t *config); -void ald_lptim_trigger_filter_config(lptim_handle_t *hperh, lptim_trgflt_t flt); -void ald_lptim_clock_filter_config(lptim_handle_t *hperh, lptim_ckflt_t flt); -/** - * @} - */ - -/** @addtogroup LPTIM_Public_Functions_Group2 - * @{ - */ -ald_status_t ald_lptim_base_init(lptim_handle_t *hperh); -void ald_lptim_base_start(lptim_handle_t *hperh); -void ald_lptim_base_stop(lptim_handle_t *hperh); -void ald_lptim_base_start_by_it(lptim_handle_t *hperh); -void ald_lptim_base_stop_by_it(lptim_handle_t *hperh); -/** - * @} - */ - -/** @addtogroup LPTIM_Public_Functions_Group3 - * @{ - */ -ald_status_t ald_lptim_toggle_init(lptim_handle_t *hperh); -void ald_lptim_toggle_start(lptim_handle_t *hperh); -void ald_lptim_toggle_stop(lptim_handle_t *hperh); -void ald_lptim_toggle_start_by_it(lptim_handle_t *hperh); -void ald_lptim_toggle_stop_by_it(lptim_handle_t *hperh); -/** - * @} - */ - -/** @addtogroup LPTIM_Public_Functions_Group4 - * @{ - */ -ald_status_t ald_lptim_pulse_init(lptim_handle_t *hperh); -void ald_lptim_pulse_start(lptim_handle_t *hperh); -void ald_lptim_pulse_stop(lptim_handle_t *hperh); -void ald_lptim_pulse_start_by_it(lptim_handle_t *hperh); -void ald_lptim_pulse_stop_by_it(lptim_handle_t *hperh); -/** - * @} - */ - -/** @addtogroup LPTIM_Public_Functions_Group5 - * @{ - */ -ald_status_t ald_lptim_pwm_init(lptim_handle_t *hperh); -void ald_lptim_pwm_start(lptim_handle_t *hperh); -void ald_lptim_pwm_stop(lptim_handle_t *hperh); -void ald_lptim_pwm_start_by_it(lptim_handle_t *hperh); -void ald_lptim_pwm_stop_by_it(lptim_handle_t *hperh); -/** - * @} - */ - -/** @addtogroup LPTIM_Public_Functions_Group6 - * @{ - */ -void ald_lptim_irq_handler(lptim_handle_t *hperh); -void ald_lptim_interrupt_config(lptim_handle_t *hperh, lptim_it_t it, type_func_t state); -it_status_t ald_lptim_get_it_status(lptim_handle_t *hperh, lptim_it_t it); -flag_status_t ald_lptim_get_flag_status(lptim_handle_t *hperh, lptim_flag_t flag); -void ald_lptim_clear_flag_status(lptim_handle_t *hperh, lptim_flag_t flag); -/** - * @} - */ - -/** @addtogroup LPTIM_Public_Functions_Group7 - * @{ - */ -lptim_state_t ald_lptim_get_state(lptim_handle_t *hperh); -/** - * @} - */ - -/** - * @} - */ - -/** - * @} - */ - -/** - * @} - */ -#ifdef __cplusplus -} -#endif - -#endif /* __ALD_LPTIM_H__ */ diff --git a/bsp/essemi/es32f0334/libraries/ES32F033x_ALD_StdPeriph_Driver/Include/ald_lpuart.h b/bsp/essemi/es32f0334/libraries/ES32F033x_ALD_StdPeriph_Driver/Include/ald_lpuart.h deleted file mode 100644 index fe9d619159..0000000000 --- a/bsp/essemi/es32f0334/libraries/ES32F033x_ALD_StdPeriph_Driver/Include/ald_lpuart.h +++ /dev/null @@ -1,468 +0,0 @@ -/** - ********************************************************************************* - * - * @file ald_lpuart.h - * @brief Header file of Low Power UART module library. - * - * @version V1.0 - * @date 30 May 2017 - * @author AE Team - * @note - * - * Copyright (C) Shanghai Eastsoft Microelectronics Co. Ltd. All rights reserved. - * - ********************************************************************************* - */ - -#ifndef __ALD_LPUART_H__ -#define __ALD_LPUART_H__ - -#ifdef __cplusplus -extern "C" { -#endif - -#include "utils.h" -#include "ald_dma.h" -#include "ald_cmu.h" - - -/** @addtogroup ES32FXXX_ALD - * @{ - */ - -/** @addtogroup LPUART - * @{ - */ - -/** - * @defgroup LPUART_Public_Macros LPUART Public Macros - * @{ - */ - -/** - * @defgroup LPUART_Public_Macros1 LPUART FIFO Reset - * @{ - */ -#define LPUART_FIFO_TX_RESET(hperh) (SET_BIT((hperh)->perh->FIFOCON, LPUART_FIFOCON_TXRESET_MSK)) -#define LPUART_FIFO_RX_RESET(hperh) (SET_BIT((hperh)->perh->FIFOCON, LPUART_FIFOCON_RXRESET_MSK)) -/** - * @} - */ -/** - * @defgroup LPUART_Public_Macros2 LPUART RS485 RX Enable - * @{ - */ -#define LPUART_RS485_RX_DISABLE(hperh) (SET_BIT((hperh)->perh->FIFOCON, LPUART_FIFOCON_NMPMRXDIS_MSK)) -#define LPUART_RS485_RX_ENABLE(hperh) (CLEAR_BIT((hperh)->perh->FIFOCON, LPUART_FIFOCON_NMPMRXDIS_MSK)) -/** - * @} - */ -/** - * @defgroup LPUART_Public_Macros4 LPUART LoopMode Enable - * @{ - */ -#define LPUART_LPBMOD_ENABLE(hperh) (SET_BIT((hperh)->perh->CON0, LPUART_CON0_LPBMOD_MSK)) -#define LPUART_LPBMOD_DISABLE(hperh) (CLEAR_BIT((hperh)->perh->CON0, LPUART_CON0_LPBMOD_MSK)) -/** - * @} - */ -/** - * @defgroup LPUART_Public_Macros5 LPUART IrDA TX Enable - * @{ - */ -#define LPUART_IRTX_ENABLE(hperh) (SET_BIT((hperh)->perh->CON1, LPUART_CON1_IRTXE_MSK)) -#define LPUART_IRTX_DISABLE(hperh) (CLEAR_BIT((hperh)->perh->CON1, LPUART_CON1_IRTXE_MSK)) -/** - * @} - */ -/** - * @defgroup LPUART_Public_Macros6 LPUART IRWIDTH Enable - * @{ - */ -#define LPUART_IRWIDTH_DISABLE(hperh) (SET_BIT((hperh)->perh->CON1, LPUART_CON1_IRWIDTH_MSK)) -#define LPUART_IRWIDTH_ENABLE(hperh) (CLEAR_BIT((hperh)->perh->CON1, LPUART_CON1_IRWIDTH_MSK)) -/** - * @} - */ -/** - * @defgroup LPUART_Public_Macros7 LPUART CTS/RTS Enable - * @{ - */ -#define LPUART_CTS_ENABLE(hperh) (SET_BIT((hperh)->perh->CON0, LPUART_CON0_ATCTSE_MSK)) -#define LPUART_CTS_DISABLE(hperh) (CLEAR_BIT((hperh)->perh->CON0, LPUART_CON0_ATCTSE_MSK)) -#define LPUART_RTS_ENABLE(hperh) (SET_BIT((hperh)->perh->CON0, LPUART_CON0_ATRTSE_MSK)) -#define LPUART_RTS_DISABLE(hperh) (CLEAR_BIT((hperh)->perh->CON0, LPUART_CON0_ATRTSE_MSK)) -/** - * @} - */ -/** - * @defgroup LPUART_Public_Macros8 LPUART CTS/RTS Polarity - * @{ - */ -#define LPUART_CTS_POL_LOW(hperh) (SET_BIT((hperh)->perh->CON0, LPUART_CON0_CTSPOL_MSK)) -#define LPUART_CTS_POL_HIGH(hperh) (CLEAR_BIT((hperh)->perh->CON0, LPUART_CON0_CTSPOL_MSK)) -#define LPUART_RTS_POL_LOW(hperh) (SET_BIT((hperh)->perh->CON0, LPUART_CON0_RTSPOL_MSK)) -#define LPUART_RTS_POL_HIGH(hperh) (CLEAR_BIT((hperh)->perh->CON0, LPUART_CON0_RTSPOL_MSK)) -/** - * @} - */ -/** - * @defgroup LPUART_Public_Macros10 LPUART Update Enable - * @{ - */ -#define LPUART_UPDATE_ENABLE(hperh) (CLEAR_BIT((hperh)->perh->UPDATE, LPUART_UPDATE_UDIS_MSK)) -#define LPUART_UPDATE_DISABLE(hperh) (SET_BIT((hperh)->perh->UPDATE, LPUART_UPDATE_UDIS_MSK)) -/** - * @} - */ - -/** - * @} - */ - -/** @defgroup LPUART_Public_Types LPUART Public Types - * @{ - */ -/** - * @brief LPUART Word Length - */ -typedef enum { - LPUART_WORD_LENGTH_5B = 0x0U, /**< 5-bits */ - LPUART_WORD_LENGTH_6B = 0x1U, /**< 6-bits */ - LPUART_WORD_LENGTH_7B = 0x2U, /**< 7-bits */ - LPUART_WORD_LENGTH_8B = 0x3U, /**< 8-bits */ - LPUART_WORD_LENGTH_9B = 0x4U, /**< 9-bits */ -} lpuart_word_length_t; - -/** - * @brief LPUART Stop Bits - */ -typedef enum { - LPUART_STOP_BITS_1 = 0x0U, /**< 1-bits */ - LPUART_STOP_BITS_2 = 0x1U, /**< 2-bits */ -} lpuart_stop_bits_t; - -/** - * @brief LPUART Parity - */ -typedef enum { - LPUART_PARITY_NONE = 0x0U, /**< Not parity */ - LPUART_PARITY_ODD = 0x1U, /**< Odd parity */ - LPUART_PARITY_EVEN = 0x3U, /**< Even parity */ -} lpuart_parity_t; - -/** - * @brief LPUART Mode - */ -typedef enum { - LPUART_MODE_UART = 0x0U, /**< UART */ - LPUART_MODE_IrDA = 0x2U, /**< IrDA */ - LPUART_MODE_RS485 = 0x3U, /**< RS485 */ -} lpuart_mode_t; - -/** - * @brief LPUART Hardware Flow Control - */ -typedef enum { - LPUART_HW_FLOW_CTL_NONE = 0x0U, /**< None */ - LPUART_HW_FLOW_CTL_RTS = 0x1U, /**< RTS */ - LPUART_HW_FLOW_CTL_CTS = 0x2U, /**< CTS */ - LPUART_HW_FLOW_CTL_RTS_CTS = 0x3U, /**< RTS & CTS */ -} lpuart_hw_flow_ctl_t; - -/** - * @brief ALD LPUART State - */ -typedef enum { - LPUART_STATE_RESET = 0x00U, /**< Peripheral is not initialized */ - LPUART_STATE_READY = 0x01U, /**< Peripheral Initialized and ready for use */ - LPUART_STATE_BUSY = 0x02U, /**< an internal process is ongoing */ - LPUART_STATE_BUSY_TX = 0x11U, /**< Data Transmission process is ongoing */ - LPUART_STATE_BUSY_RX = 0x21U, /**< Data Reception process is ongoing */ - LPUART_STATE_BUSY_TX_RX = 0x31U, /**< Data Transmission Reception process is ongoing */ - LPUART_STATE_TIMEOUT = 0x03U, /**< Timeout state */ - LPUART_STATE_ERROR = 0x04U, /**< Error */ -} lpuart_state_t; - -/** - * @brief LPUART Error Codes - */ -typedef enum { - LPUART_ERROR_NONE = ((uint32_t)0x00U), /**< No error */ - LPUART_ERROR_PE = ((uint32_t)0x01U), /**< Parity error */ - LPUART_ERROR_NE = ((uint32_t)0x02U), /**< Noise error */ - LPUART_ERROR_FE = ((uint32_t)0x04U), /**< frame error */ - LPUART_ERROR_ORE = ((uint32_t)0x08U), /**< Overrun error */ - LPUART_ERROR_DMA = ((uint32_t)0x10U), /**< DMA transfer error */ -} lpuart_error_t; - -/** - * @brief LPUART Init structure definition - */ -typedef struct { - uint32_t baud; /**< Specifies the lpuart communication baud rate */ - lpuart_word_length_t word_length; /**< Specifies the number of data bits transmitted or received in a frame */ - lpuart_stop_bits_t stop_bits; /**< Specifies the number of stop bits transmitted */ - lpuart_parity_t parity; /**< Specifies the parity mode */ - lpuart_mode_t mode; /**< Specifies uart mode */ - lpuart_hw_flow_ctl_t fctl; /**< Specifies wether the hardware flow control mode is enabled or disabled */ - cmu_lp_perh_clock_sel_t clock; /**< Specifies clock, only support LOSC and LRC */ -} lpuart_init_t; - -/** - * @brief LPUART handle structure definition - */ -typedef struct lpuart_handle_s { - LPUART_TypeDef *perh; /**< LPUART registers base address */ - lpuart_init_t init; /**< LPUART communication parameters */ - uint8_t *tx_buf; /**< Pointer to LPUART Tx transfer Buffer */ - uint16_t tx_size; /**< LPUART Tx Transfer size */ - uint16_t tx_count; /**< LPUART Tx Transfer Counter */ - uint8_t *rx_buf; /**< Pointer to LPUART Rx transfer Buffer */ - uint16_t rx_size; /**< LPUART Rx Transfer size */ - uint16_t rx_count; /**< LPUART Rx Transfer Counter */ -#ifdef ALD_DMA - dma_handle_t hdmatx; /**< LPUART Tx DMA Handle parameters */ - dma_handle_t hdmarx; /**< LPUART Rx DMA Handle parameters */ -#endif - lock_state_t lock; /**< Locking object */ - lpuart_state_t state; /**< LPUART communication state */ - lpuart_error_t err_code; /**< LPUART Error code */ - - void (*tx_cplt_cbk)(struct lpuart_handle_s *arg); /**< Tx completed callback */ - void (*rx_cplt_cbk)(struct lpuart_handle_s *arg); /**< Rx completed callback */ - void (*error_cbk)(struct lpuart_handle_s *arg); /**< error callback */ -} lpuart_handle_t; - -/** - * @brief LPUART RS485 Configure Structure definition - */ -typedef struct { - type_func_t RS485_NMM; /**< Normal Point Mode */ - type_func_t RS485_AAD; /**< Auto-Address Detect */ - type_func_t RS485_AUD; /**< Auto-Direction Mode */ - type_func_t RS485_ADD_DET; /**< Eable/Disable Address Detect */ - uint8_t RS485_ADDCMP; /**< Address for compare */ -} lpuart_rs485_config_t; - -/** - * @brief LPUART DMA Requests - */ -typedef enum { - LPUART_DMA_REQ_TX = 0x0U, /**< TX dma */ - LPUART_DMA_REQ_RX = 0x1U, /**< RX dma */ -} lpuart_dma_req_t; - -/** - * @brief LPUART RXFIFO size - */ -typedef enum { - LPUART_RXFIFO_1BYTE = 0x0U, /**< 1-Byte */ - LPUART_RXFIFO_4BYTE = 0x1U, /**< 4-Bytes */ - LPUART_RXFIFO_8BYTE = 0x2U, /**< 8-Bytes */ - LPUART_RXFIFO_14BYTE = 0x3U, /**< 14-Bytes */ -} lpuart_rxfifo_t; - -/** - * @brief LPUART Interrupts Types - */ -typedef enum { - LPUART_IT_RBR = (1U << 0), /**< RBR */ - LPUART_IT_TBEMP = (1U << 1), /**< TBEMP */ - LPUART_IT_CTSDET = (1U << 2), /**< CTSDET */ - LPUART_IT_RXTO = (1U << 3), /**< RXTO */ - LPUART_IT_RXOV = (1U << 4), /**< RXOV */ - LPUART_IT_TXOV = (1U << 5), /**< TXOV */ - LPUART_IT_CTSWK = (1U << 7), /**< CTSWK */ - LPUART_IT_DATWK = (1U << 8), /**< DATWK */ - LPUART_IT_PERR = (1U << 9), /**< PERR */ - LPUART_IT_FERR = (1U << 10), /**< FERR */ - LPUART_IT_BRKERR = (1U << 11), /**< BRKERR */ - LPUART_IT_ADET = (1U << 12), /**< ADET */ - LPUART_IT_TC = (1U << 15), /**< TC */ -} lpuart_it_t; - -/** - * @brief LPUART Flags Types - */ -typedef enum { - LPUART_IF_RBR = (1U << 0), /**< RBR */ - LPUART_IF_TBEMP = (1U << 1), /**< TBEMP */ - LPUART_IF_CTSDET = (1U << 2), /**< CTSDET */ - LPUART_IF_RXTO = (1U << 3), /**< RXTO */ - LPUART_IF_RXOV = (1U << 4), /**< RXOV */ - LPUART_IF_TXOV = (1U << 5), /**< TXOV */ - LPUART_IF_CTSWK = (1U << 7), /**< CTSWK */ - LPUART_IF_DATWK = (1U << 8), /**< DATWK */ - LPUART_IF_PERR = (1U << 9), /**< PERR */ - LPUART_IF_FERR = (1U << 10), /**< FERR */ - LPUART_IF_BRKERR = (1U << 11), /**< BRKERR */ - LPUART_IF_ADET = (1U << 12), /**< ADET */ - LPUART_IF_TC = (1U << 15), /**< TC */ -} lpuart_flag_t; - -/** - * @brief LPUART Status Types - */ -typedef enum { - LPUART_STAT_RXEMP = (1U << 6), /**< RX FIFO empty */ - LPUART_STAT_RXFULL = (1U << 7), /**< RX FIFO full */ - LPUART_STAT_TXEMP = (1U << 14), /**< TX FIFO empty */ - LPUART_STAT_TXFULL = (1U << 15), /**< TX FIFO full */ - LPUART_STAT_TXIDLE = (1U << 16), /**< TX idle */ - LPUART_STAT_CTSSTAT = (1U << 17), /**< CTS status */ - LPUART_STAT_RTSSTAT = (1U << 18), /**< RTS status */ -} lpuart_status_t; -/** - * @} - */ - -/** @defgroup LPUART_Private_Macros LPUART Private Macros - * @{ - */ -#define IS_LPUART(x) ((x) == LPUART0) -#define IS_LPUART_DATA(x) ((x) <= 0x1FF) -#define IS_LPUART_BAUDRATE(x) (((x) > 0) && ((x) <= 115200)) -#define IS_LPUART_WORD_LENGTH(x) (((x) == LPUART_WORD_LENGTH_5B) || \ - ((x) == LPUART_WORD_LENGTH_6B) || \ - ((x) == LPUART_WORD_LENGTH_7B) || \ - ((x) == LPUART_WORD_LENGTH_8B) || \ - ((x) == LPUART_WORD_LENGTH_9B)) -#define IS_LPUART_STOPBITS(x) (((x) == LPUART_STOP_BITS_1) || \ - ((x) == LPUART_STOP_BITS_2)) -#define IS_LPUART_PARITY(x) (((x) == LPUART_PARITY_NONE) || \ - ((x) == LPUART_PARITY_ODD) || \ - ((x) == LPUART_PARITY_EVEN)) -#define IS_LPUART_MODE(x) (((x) == LPUART_MODE_UART) || \ - ((x) == LPUART_MODE_IrDA) || \ - ((x) == LPUART_MODE_RS485)) -#define IS_LPUART_HARDWARE_FLOW_CONTROL(x)\ - (((x) == LPUART_HW_FLOW_CTL_NONE) || \ - ((x) == LPUART_HW_FLOW_CTL_RTS) || \ - ((x) == LPUART_HW_FLOW_CTL_CTS) || \ - ((x) == LPUART_HW_FLOW_CTL_RTS_CTS)) -#define IS_LPUART_DMAREQ(x) (((x) == LPUART_DMA_REQ_TX) || ((x) == LPUART_DMA_REQ_RX)) -#define IS_LPUART_RXFIFO(x) (((x) == LPUART_RXFIFO_1BYTE) || \ - ((x) == LPUART_RXFIFO_4BYTE) || \ - ((x) == LPUART_RXFIFO_8BYTE) || \ - ((x) == LPUART_RXFIFO_14BYTE)) -#define IS_LPUART_IT(x) (((x) == LPUART_IT_RBR) || \ - ((x) == LPUART_IT_TBEMP) || \ - ((x) == LPUART_IT_CTSDET) || \ - ((x) == LPUART_IT_RXTO) || \ - ((x) == LPUART_IT_RXOV) || \ - ((x) == LPUART_IT_TXOV) || \ - ((x) == LPUART_IT_CTSWK) || \ - ((x) == LPUART_IT_DATWK) || \ - ((x) == LPUART_IT_PERR) || \ - ((x) == LPUART_IT_FERR) || \ - ((x) == LPUART_IT_BRKERR) || \ - ((x) == LPUART_IT_ADET) || \ - ((x) == LPUART_IT_TC)) -#define IS_LPUART_IF(x) (((x) == LPUART_IF_RBR) || \ - ((x) == LPUART_IF_TBEMP) || \ - ((x) == LPUART_IF_CTSDET) || \ - ((x) == LPUART_IF_RXTO) || \ - ((x) == LPUART_IF_RXOV) || \ - ((x) == LPUART_IF_TXOV) || \ - ((x) == LPUART_IF_CTSWK) || \ - ((x) == LPUART_IF_DATWK) || \ - ((x) == LPUART_IF_PERR) || \ - ((x) == LPUART_IF_FERR) || \ - ((x) == LPUART_IF_BRKERR) || \ - ((x) == LPUART_IF_ADET) || \ - ((x) == LPUART_IF_TC)) -#define IS_LPUART_STAT(x) (((x) == LPUART_STAT_RXEMP) || \ - ((x) == LPUART_STAT_RXFULL) || \ - ((x) == LPUART_STAT_TXEMP) || \ - ((x) == LPUART_STAT_TXFULL) || \ - ((x) == LPUART_STAT_TXIDLE) || \ - ((x) == LPUART_STAT_CTSSTAT) || \ - ((x) == LPUART_STAT_RTSSTAT)) - -#define LPUART_STATE_TX_MASK (1U << 4) -#define LPUART_STATE_RX_MASK (1U << 5) -/** - * @} - */ - -/** @addtogroup LPUART_Public_Functions - * @{ - */ - -/** @addtogroup LPUART_Public_Functions_Group1 - * @{ - */ -/* Initialization functions */ -void ald_lpuart_init(lpuart_handle_t *hperh); -void ald_lpuart_reset(lpuart_handle_t *hperh); -void ald_lpuart_rs485_config(lpuart_handle_t *hperh, lpuart_rs485_config_t *config); -/** - * @} - */ - -/** @addtogroup LPUART_Public_Functions_Group2 - * @{ - */ -/* IO operation functions */ -ald_status_t ald_lpuart_send(lpuart_handle_t *hperh, uint8_t *buf, uint16_t size, uint32_t timeout); -ald_status_t ald_lpuart_recv(lpuart_handle_t *hperh, uint8_t *buf, uint16_t size, uint32_t timeout); -ald_status_t ald_lpuart_send_by_it(lpuart_handle_t *hperh, uint8_t *buf, uint16_t size); -ald_status_t ald_lpuart_recv_by_it(lpuart_handle_t *hperh, uint8_t *buf, uint16_t size); -#ifdef ALD_DMA -ald_status_t ald_lpuart_send_by_dma(lpuart_handle_t *hperh, uint8_t *buf, uint16_t size, uint8_t channel); -ald_status_t ald_lpuart_recv_by_dma(lpuart_handle_t *hperh, uint8_t *buf, uint16_t size, uint8_t channel); -ald_status_t ald_lpuart_dma_pause(lpuart_handle_t *hperh); -ald_status_t ald_lpuart_dma_resume(lpuart_handle_t *hperh); -ald_status_t ald_lpuart_dma_stop(lpuart_handle_t *hperh); -#endif -void ald_lpuart_irq_handler(lpuart_handle_t *hperh); - -/** - * @} - */ - -/** @addtogroup LPUART_Public_Functions_Group3 - * @{ - */ -/* Peripheral Control functions */ -void ald_lpuart_interrupt_config(lpuart_handle_t *hperh, lpuart_it_t it, type_func_t status); -void ald_lpuart_tx_interval_config(lpuart_handle_t *hperh, uint8_t val); -void ald_lpuart_dma_req_config(lpuart_handle_t *hperh, lpuart_dma_req_t req, type_func_t status); -void ald_lpuart_rx_fifo_it_config(lpuart_handle_t *hperh, lpuart_rxfifo_t config); -void ald_lpuart_rx_fifo_rts_config(lpuart_handle_t *hperh, lpuart_rxfifo_t config); -ald_status_t ald_lpuart_rs485_send_addr(lpuart_handle_t *hperh, uint16_t addr, uint32_t timeout); -flag_status_t ald_lpuart_get_status(lpuart_handle_t *hperh, lpuart_status_t flag); -flag_status_t ald_lpuart_get_flag_status(lpuart_handle_t *hperh, lpuart_flag_t flag); -void ald_lpuart_clear_flag_status(lpuart_handle_t *hperh, lpuart_flag_t flag); -it_status_t ald_lpuart_get_it_status(lpuart_handle_t *hperh, lpuart_it_t it); -/** - * @} - */ - -/** @addtogroup LPUART_Public_Functions_Group4 - * @{ - */ -/* Peripheral State and Errors functions */ -lpuart_state_t ald_lpuart_get_state(lpuart_handle_t *hperh); -uint32_t ald_lpuart_get_error(lpuart_handle_t *hperh); -/** - * @} - */ - -/** - * @} - */ - -/** - * @} - */ - -/** - * @} - */ -#ifdef __cplusplus -} -#endif - -#endif /* __ALD_LPUART_H__ */ diff --git a/bsp/essemi/es32f0334/libraries/ES32F033x_ALD_StdPeriph_Driver/Include/ald_pis.h b/bsp/essemi/es32f0334/libraries/ES32F033x_ALD_StdPeriph_Driver/Include/ald_pis.h deleted file mode 100644 index c17b03cfd9..0000000000 --- a/bsp/essemi/es32f0334/libraries/ES32F033x_ALD_StdPeriph_Driver/Include/ald_pis.h +++ /dev/null @@ -1,637 +0,0 @@ -/** - ********************************************************************************* - * - * @file ald_pis.h - * @brief Header file of PIS driver. - * - * @version V1.0 - * @date 27 Nov 2017 - * @author AE Team - * @note - * - * Copyright (C) Shanghai Eastsoft Microelectronics Co. Ltd. All rights reserved. - * - ********************************************************************************* - */ - -#ifndef __ALD_PIS_H__ -#define __ALD_PIS_H__ - -#ifdef __cplusplus - extern "C" { -#endif - -#include "utils.h" - - -/** @addtogroup ES32FXXX_ALD - * @{ - */ - -/** @addtogroup PIS - * @{ - */ - -/** @defgroup PIS_Public_Types PIS Public Types - * @{ - */ -/** - * @brief Producer entry - * @verbatim - In this module, for the convenience of code maintenance, - TIMERx is used to indicate the sequence of the timer peripheral. - Different product series TIMERx represent different meanings: - 1. For ES32F065x series: - TIMER0 ----> AD16C4T0 - TIMER1 ----> BS16T0 - TIMER2 ----> GP16C2T0 - TIMER3 ----> GP16C2T1 - - 2. For ES32F033x/ES32F093x series: - TIMER0 ----> GP16C4T0 - TIMER1 ----> BS16T0 - TIMER2 ----> GP16C2T0 - TIMER3 ----> GP16C2T1 - @endverbatim - */ -typedef enum { - PIS_NON = 0x0U, /**< No async */ - PIS_GPIO_PIN0 = 0x10U, /**< Pin0, level,support async */ - PIS_GPIO_PIN1 = 0x11U, /**< Pin1, level,support async */ - PIS_GPIO_PIN2 = 0x12U, /**< Pin2, level,support async */ - PIS_GPIO_PIN3 = 0x13U, /**< Pin3, level,support async */ - PIS_GPIO_PIN4 = 0x14U, /**< Pin4, level,support async */ - PIS_GPIO_PIN5 = 0x15U, /**< Pin5, level,support async */ - PIS_GPIO_PIN6 = 0x16U, /**< Pin6, level,support async */ - PIS_GPIO_PIN7 = 0x17U, /**< Pin7, level,support async */ - PIS_GPIO_PIN8 = 0x18U, /**< Pin8, level,support async */ - PIS_GPIO_PIN9 = 0x19U, /**< Pin9, level,support async */ - PIS_GPIO_PIN10 = 0x1aU, /**< Pin10, level,support async */ - PIS_GPIO_PIN11 = 0x1bU, /**< Pin11, level,support async */ - PIS_GPIO_PIN12 = 0x1cU, /**< Pin12, level,support async */ - PIS_GPIO_PIN13 = 0x1dU, /**< Pin13, level,support async */ - PIS_GPIO_PIN14 = 0x1eU, /**< Pin14, level,support async */ - PIS_GPIO_PIN15 = 0x1fU, /**< Pin15, level,support async */ - PIS_ACMP_OUT0 = 0x30U, /**< Acmp0 output, level,support async */ - PIS_ACMP_OUT1 = 0x31U, /**< Acmp1 output, level,support async */ - PIS_DAC0_CH0 = 0x40U, /**< Dac0 channel 0, pclk2 pulse,support async */ - PIS_DAC0_CH1 = 0x41U, /**< Dac0 channel 1, pclk2 pulse,support async */ - PIS_ADC0_INJECT = 0x60U, /**< Adc0 inject, pclk2 pulse,support async */ - PIS_ADC0_REGULAT = 0x61U, /**< Adc0 regulat, pclk2 pulse,support async */ - PIS_ADC0_WINDOW = 0x62U, /**< Adc0 window, no have */ - PIS_LVD = 0x70U, /**< Lvd, level,support async */ - PIS_UART0_ASY_SEND = 0x80U, /**< Uart0 asy send, pulse,support async */ - PIS_UART0_ASY_RECV = 0x81U, /**< Uart0 asy recv, pulse,support async */ - PIS_UART0_IRDAOUT = 0x82U, /**< Uart0 irdaout, level,support async */ - PIS_UART0_RTSOUT = 0x83U, /**< Uart0 rtsout, level,support async */ - PIS_UART0_TXOUT = 0x84U, /**< Uart0 txout, level,support async */ - PIS_UART0_SYN_SEND = 0x85U, /**< Uart0 syn send, pulse,support async */ - PIS_UART0_SYN_RECV = 0x86U, /**< Uart0 syn recv, pulse,support async */ - PIS_UART1_ASY_SEND = 0x90U, /**< Uart1 asy send, pulse,support async */ - PIS_UART1_ASY_RECV = 0x91U, /**< Uart1 asy recv, pulse,support async */ - PIS_UART1_IRDA = 0x92U, /**< Uart1 irdaout, level,support async */ - PIS_UART1_RTS = 0x93U, /**< Uart1 rtsout, level,support async */ - PIS_UART1_TXOUT = 0x94U, /**< Uart1 txout, level,support async */ - PIS_UART1_SYN_SEND = 0x95U, /**< Uart1 syn send, pulse,support async */ - PIS_UART1_SYN_RECV = 0x96U, /**< Uart1 syn recv, pulse,support async */ - PIS_UART2_ASY_SEND = 0xa0U, /**< Uart2 asy send, pulse,support async */ - PIS_UART2_ASY_RECV = 0xa1U, /**< Uart2 asy recv, pulse,support async */ - PIS_UART2_IRDA = 0xa2U, /**< Uart2 irdaout, level,support async */ - PIS_UART2_RTS = 0xa3U, /**< Uart2 rtsout, level,support async */ - PIS_UART2_TXOUT = 0xa4U, /**< Uart2 txout, level,support async */ - PIS_UART2_SYN_SEND = 0xa5U, /**< Uart2 syn send, pulse,support async */ - PIS_UART2_SYN_RECV = 0xa6U, /**< Uart2 syn recv, pulse,support async */ - PIS_UART3_ASY_SEND = 0xb1U, /**< Uart3 asy send, pulse,support async */ - PIS_UART3_ASY_RECV = 0xb2U, /**< Uart3 asy recv, pulse,support async */ - PIS_UART3_IRDA = 0xb3U, /**< Uart3 irdaout, level,support async */ - PIS_UART3_RTS = 0xb4U, /**< Uart3 rtsout, level,support async */ - PIS_UART3_TXOUT = 0xb5U, /**< Uart3 txout, level,support async */ - PIS_UART3_SYN_SEND = 0xb6U, /**< Uart3 syn send, pulse,support async */ - PIS_UART3_SYN_RECV = 0xb7U, /**< Uart3 syn recv, pulse,support async */ - PIS_EUART0_RECV = 0xc0U, /**< Euart0 recv, plck1 pulse */ - PIS_EUART0_SEND = 0xc1U, /**< Euart0 send, plck1 pulse */ - PIS_EUART0_TXOUT = 0xc2U, /**< Euart0 txout, plck1 level */ - PIS_EUART1_RECV = 0xd0U, /**< Euart1 recv, plck1 pulse */ - PIS_EUART1_SEND = 0xd1U, /**< Euart1 send, plck1 pulse */ - PIS_EUART1_TXOUT = 0xd2U, /**< Euart1 txout, plck1 level */ - PIS_SPI0_RECV = 0xe0U, /**< Spi0 recv, plck1 pulse */ - PIS_SPI0_SEND = 0xe1U, /**< Spi0 send, plck1 pulse */ - PIS_SPI0_NE = 0xe2U, /**< Spi0 ne, plck1 level */ - PIS_SPI1_RECV = 0xf0U, /**< Spi1 recv, plck1 pulse */ - PIS_SPI1_SEND = 0xf1U, /**< Spi1 send, plck1 pulse */ - PIS_SPI1_NE = 0xf2U, /**< Spi1 ne, plck1 level */ - PIS_I2C0_RECV = 0x100U, /**< I2c0 recv, plck1 level */ - PIS_I2C0_SEND = 0x101U, /**< I2c0 send, plck1 level */ - PIS_I2C1_RECV = 0x110U, /**< I2c1 recv, plck1 level */ - PIS_I2C1_SEND = 0x111U, /**< I2c1 send, plck1 level */ - PIS_TIMER0_UPDATA = 0x120U, /**< Timer0 updata, plck1 pulse */ - PIS_TIMER0_TRIG = 0x121U, /**< Timer0 trig, plck1 pulse */ - PIS_TIMER0_INPUT = 0x122U, /**< Timer0 input, plck1 pulse */ - PIS_TIMER0_OUTPUT = 0x123U, /**< Timer0 output, plck1 pulse */ - PIS_TIMER1_UPDATA = 0x130U, /**< Timer1 updata, plck1 pulse */ - PIS_TIMER1_TRIG = 0x131U, /**< Timer1 trig, plck1 pulse */ - PIS_TIMER1_INPUT = 0x132U, /**< Timer1 input, plck1 pulse */ - PIS_TIMER1_OUTPUT = 0x133U, /**< Timer1 output, plck1 pulse */ - PIS_TIMER2_UPDATA = 0x140U, /**< Timer2 updata, plck1 pulse */ - PIS_TIMER2_TRIG = 0x141U, /**< Timer2 trig, plck1 pulse */ - PIS_TIMER2_INPUT = 0x142U, /**< Timer2 input, plck1 pulse */ - PIS_TIMER2_OUTPUT = 0x143U, /**< Timer2 output, plck1 pulse */ - PIS_TIMER3_UPDATA = 0x150U, /**< Timer0 updata, plck1 pulse */ - PIS_TIMER3_TRIG = 0x151U, /**< Timer0 trig, plck1 pulse */ - PIS_TIMER3_INPUT = 0x152U, /**< Timer0 input, plck1 pulse */ - PIS_TIMER3_OUTPUT = 0x153U, /**< Timer0 output, plck1 pulse */ - PIS_RTC_CLOCK = 0x160U, /**< Rtc clock, pulse,support async */ - PIS_RTC_ALARM = 0x161U, /**< Rtc alarm, pulse,support async */ - PIS_LPTIM0_SYN_UPDATA = 0x170U, /**< Lptimer0 syn updata, pulse,support async */ - PIS_LPTIM0_ASY_UPDATA = 0x171U, /**< Lptimer0 asy updata, pulse,support async */ - PIS_LPUART0_ASY_RECV = 0x180U, /**< Lpuart0 asy recv, pulse,support async */ - PIS_LPUART0_ASY_SEND = 0x181U, /**< Lpuart0 asy send, pulse,support async */ - PIS_LPUART0_SYN_RECV = 0x182U, /**< Lpuart0 syn recv, pulse,support async */ - PIS_LPUART0_SYN_SEND = 0x183U, /**< Lpuart0 syn recv, pulse,support async */ - PIS_DMA = 0x190U, /**< Dma, pulse,support async */ - PIS_ADC1_INJECT = 0x1a0U, /**< Adc1 inject, pclk2 pulse,support async */ - PIS_ADC1_REGULAT = 0x1a1U, /**< Adc1 regulat, pclk2 pulse,support async */ - PIS_ADC1_WINDOW = 0x1a2U, /**< Adc1 window, no have */ -} pis_src_t; - -/** - * @brief Consumer entry - */ -typedef enum { - PIS_CH0_TIMER0_BRKIN = 0x0400U, /**< Timer0 brkin */ - PIS_CH0_SPI1_CLK = 0x0F10U, /**< Spi1 clk */ - PIS_CH0_LPTIM0_EXT0 = 0x0030U, /**< Lptimer0 ext0 */ - PIS_CH0_ADC1_NORMAL = 0x0030U, /**< Adc1 normal */ - PIS_CH1_TIMER0_CH1IN = 0x0001U, /**< Timer0 ch1in */ - PIS_CH1_TIMER2_CH1IN = 0x1001U, /**< Timer2 ch1in */ - PIS_CH1_TIMER3_CH1IN = 0x1801U, /**< Timer3 ch1in */ - PIS_CH1_LPTIM0_EXT1 = 0x0031U, /**< Lptime0 ext1 */ - PIS_CH1_UART0_RX_IRDA = 0x0011U, /**< Uart0 rx irda */ - PIS_CH1_ADC1_INSERT = 0x0031U, /**< Adc1 insert */ - PIS_CH2_TIMER0_CH2IN = 0x0102U, /**< Timer0 ch2in */ - PIS_CH2_TIMER2_CH2IN = 0x1102U, /**< Timer2 ch2in */ - PIS_CH2_TIMER3_CH2IN = 0x1902U, /**< Timer3 ch2in */ - PIS_CH2_LPTIM0_EXT2 = 0x0032U, /**< Lptime0 ext2 */ - PIS_CH2_UART1_RX_IRDA = 0x0112U, /**< Uart1 rx irda */ - PIS_CH3_TIMER0_CH3IN = 0x0203U, /**< Timer0 ch3in */ - PIS_CH3_LPTIM0_EXT3 = 0x0033U, /**< Lptime0 ext3 */ - PIS_CH3_UART2_RX_IRDA = 0x0213U, /**< Uart2 rx irda */ - PIS_CH4_TIMER0_CH4IN = 0x0004U, /**< Timer0 ch4in */ - PIS_CH4_TIMER0_ITR0 = 0x0034U, /**< Timer0 itr0 */ - PIS_CH4_TIMER2_ITR0 = 0x0034U, /**< Timer2 itr0 */ - PIS_CH4_TIMER3_ITR0 = 0x0034U, /**< Timer3 itr0 */ - PIS_CH4_LPTIM0_EXT4 = 0x0434U, /**< Lptime0 ext4 */ - PIS_CH4_UART3_RX_IRDA = 0x0314U, /**< Uart3 rx irda */ - PIS_CH5_SPI0_RX = 0x0C15U, /**< Spi0 rx */ - PIS_CH5_LPTIM0_EXT5 = 0x0035U, /**< Lptime0 ext5 */ - PIS_CH5_EUART0_RX = 0x0615U, /**< Euart0 rx */ - PIS_CH5_TIMER0_ITR1 = 0x0035U, /**< Timer0 itr1 */ - PIS_CH5_TIMER2_ITR1 = 0x0035U, /**< Timer2 itr1 */ - PIS_CH5_TIMER3_ITR1 = 0x0035U, /**< Timer3 itr1 */ - PIS_CH6_SPI0_CLK = 0x0D16U, /**< Spi0 clk */ - PIS_CH6_ADC0_NORMAL = 0x0036U, /**< Adc0 normal */ - PIS_CH6_LPTIM0_EXT6 = 0x0036U, /**< Lptime0 ext6 */ - PIS_CH6_EUART1_RX = 0x0716U, /**< Euart1 rx */ - PIS_CH6_TIMER0_ITR2 = 0x0036U, /**< Timer0 itr2 */ - PIS_CH6_TIMER2_ITR2 = 0x0036U, /**< Timer2 itr2 */ - PIS_CH6_TIMER3_ITR2 = 0x0036U, /**< Timer3 itr2 */ - PIS_CH6_DAC_CH1 = 0x0036U, /**< Dac channel 1 */ - PIS_CH7_SPI1_RX = 0x0E17U, /**< Spi1 rx */ - PIS_CH7_ADC0_INSERT = 0x0037U, /**< Adc0 insert */ - PIS_CH7_LPTIM0_EXT7 = 0x0037U, /**< Lptime0 ext7 */ - PIS_CH7_DMA = 0x0037U, /**< Dma */ - PIS_CH7_TIMER0_ITR3 = 0x0037U, /**< Timer0 itr3 */ - PIS_CH7_TIMER2_ITR3 = 0x0037U, /**< Timer2 itr3 */ - PIS_CH7_TIMER3_ITR3 = 0x0037U, /**< Timer3 itr3 */ - PIS_CH7_LPUART_RX = 0x0817U, /**< Lpuart rx */ - PIS_CH7_DAC_CH0 = 0x0037U, /**< Dac channel 0 */ -} pis_trig_t; - -/** - * @brief Clock select - */ -typedef enum { - PIS_CLK_PCLK1 = 0U, /**< Pclock1 */ - PIS_CLK_PCLK2 = 1U, /**< Pclock2 */ - PIS_CLK_SYS = 2U, /**< Sys clock */ - PIS_CLK_LP = 3U, /**< Low power clock */ -} pis_clock_t; - -/** - * @brief Level select - */ -typedef enum { - PIS_EDGE_NONE = 0U, /**< None edge */ - PIS_EDGE_UP = 1U, /**< Up edge */ - PIS_EDGE_DOWN = 2U, /**< Down edge */ - PIS_EDGE_UP_DOWN = 3U, /**< Up and down edge */ -} pis_edge_t; - -/** - * @brief Output style - */ -typedef enum { - PIS_OUT_LEVEL = 0U, /**< Level */ - PIS_OUT_PULSE = 1U, /**< Pulse */ -} pis_output_t; -/** - * @brief Sync select - */ -typedef enum { - PIS_SYN_DIRECT = 0U, /**< Direct */ - PIS_SYN_ASY_PCLK1 = 1U, /**< Asy pclk1 */ - PIS_SYN_ASY_PCLK2 = 2U, /**< Asy pclk2 */ - PIS_SYN_ASY_PCLK = 3U, /**< Asy pclk */ - PIS_SYN_PCLK2_PCLK1 = 4U, /**< Pclk2 to pclk1 */ - PIS_SYN_PCLK1_PCLK2 = 5U, /**< Pclk1 to pclk2 */ - PIS_SYN_PCLK12_SYS = 6U, /**< Pclk1 or pclk2 to sysclk */ -} pis_syncsel_t; - -/** - * @brief Pis channel - */ -typedef enum { - PIS_CH_0 = 0U, /**< Channel 0 */ - PIS_CH_1 = 1U, /**< Channel 1 */ - PIS_CH_2 = 2U, /**< Channel 2 */ - PIS_CH_3 = 3U, /**< Channel 3 */ - PIS_CH_4 = 4U, /**< Channel 4 */ - PIS_CH_5 = 5U, /**< Channel 5 */ - PIS_CH_6 = 6U, /**< Channel 6 */ - PIS_CH_7 = 7U, /**< Channel 7 */ -} pis_ch_t; - -/** - * @brief Pis output channel - */ -typedef enum { - PIS_OUT_CH_0 = 0U, /**< Channel 0 */ - PIS_OUT_CH_1 = 1U, /**< Channel 1 */ - PIS_OUT_CH_2 = 2U, /**< Channel 2 */ - PIS_OUT_CH_3 = 3U, /**< Channel 3 */ -} pis_out_ch_t; - -/** - * @brief Indirect value,no care of it. - */ -typedef enum { - PIS_CON_0 = 0U, /**< Con 0 */ - PIS_CON_1 = 1U, /**< Con 1 */ - PIS_CON_NONE = 2U, /**< None */ -} pis_con_t; - -/** - * @brief PIS state structures definition - */ -typedef enum { - PIS_STATE_RESET = 0x00U, /**< Peripheral is not initialized */ - PIS_STATE_READY = 0x01U, /**< Peripheral Initialized and ready for use */ - PIS_STATE_BUSY = 0x02U, /**< An internal process is ongoing */ - PIS_STATE_TIMEOUT = 0x03U, /**< Timeout state */ - PIS_STATE_ERROR = 0x04U, /**< Error */ -} pis_state_t; - -/** - * @brief PIS modulate target - */ -typedef enum { - PIS_UART0_TX = 0U, /**< Modulate uart0 tx */ - PIS_UART1_TX = 1U, /**< Modulate uart1 tx */ - PIS_UART2_TX = 2U, /**< Modulate uart2 tx */ - PIS_UART3_TX = 3U, /**< Modulate uart3 tx */ - PIS_LPUART0_TX = 4U, /**< Modulate lpuart0 tx */ -} pis_modu_targ_t; - -/** - * @brief PIS modulate level - */ -typedef enum { - PIS_LOW_LEVEL = 0U, /**< Modulate low level */ - PIS_HIGH_LEVEL = 1U, /**< Modulate high level */ -} pis_modu_level_t; - -/** - * @brief PIS modulate source - * @note ES32F065x: - * AD16C4T0--TIMER0 - * GP16C4T0--TIMER6 - * GP16C2T0--TIMER2 - * GP16C2T1--TIMER3 - * BS16T0----TIMER1 - * BS16T1----TIMER4 - * BS16T2----TIMER5 - * BS16T3----TIMER7 - * - * ES32F033x: - * ES32F093x: - * GP16C4T0--TIMER0 - * GP16C4T1--TIMER6 - * GP16C2T0--TIMER2 - * GP16C2T1--TIMER3 - * BS16T0----TIMER1 - * BS16T1----TIMER4 - * BS16T2----TIMER5 - * BS16T3----TIMER7 - */ -typedef enum { - PIS_SRC_NONE = 0U, /**< Stop modulate */ - PIS_SRC_TIMER0 = 1U, /**< Modulate source is TIMER0 */ - PIS_SRC_TIMER1 = 2U, /**< Modulate source is TIMER1 */ - PIS_SRC_TIMER2 = 3U, /**< Modulate source is TIMER2 */ - PIS_SRC_TIMER3 = 4U, /**< Modulate source is TIMER3 */ - PIS_SRC_TIMER6 = 5U, /**< Modulate source is TIMER6 */ - PIS_SRC_TIMER7 = 6U, /**< Modulate source is TIMER7 */ - PIS_SRC_LPTIM0 = 7U, /**< Modulate source is LPTIM0 */ - PIS_SRC_BUZ = 8U, /**< Modulate source is buz */ -} pis_modu_src_t; - -/** - * @brief PIS modulate channel - */ -typedef enum { - PIS_TIMER_CH1 = 0U, /**< Src is TIMERx and choose channel 1 */ - PIS_TIMER_CH2 = 1U, /**< Src is TIMERx and choose channel 2 */ - PIS_TIMER_CH3 = 2U, /**< Src is TIMERx and choose channel 3 */ - PIS_TIMER_CH4 = 3U, /**< Src is TIMERx and choose channel 4 */ -} pis_modu_channel_t; - -/** - * @brief PIS init structure definition - */ -typedef struct { - pis_src_t producer_src; /**< Producer entry */ - pis_clock_t producer_clk; /**< Producer module clock */ - pis_edge_t producer_edge; /**< Producer module pin output edge */ - pis_trig_t consumer_trig; /**< Consumer entry */ - pis_clock_t consumer_clk; /**< Consumer clock */ -} pis_init_t; - -/** - * @brief PIS modulate config structure definition - */ -typedef struct { - pis_modu_targ_t target; /**< Modulate target */ - pis_modu_level_t level; /**< Modulate level */ - pis_modu_src_t src; /**< Modulate src */ - pis_modu_channel_t channel; /**< Modulate channel */ -} pis_modulate_config_t; - -/** - * @brief PIS Handle Structure definition - */ -typedef struct pis_handle_s { - PIS_TypeDef *perh; /**< Register base address */ - pis_init_t init; /**< PIS required parameters */ - pis_ch_t consumer_ch; /**< Indirect value, no care of it */ - pis_con_t consumer_con; /**< Indirect value, no care of it */ - uint8_t consumer_pos; /**< Indirect value, no care of it */ - uint32_t check_info; /**< When destroy a handle ,user need check whether is right that ready to destroy */ - lock_state_t lock; /**< Locking object */ - pis_state_t state; /**< PIS operation state */ -} pis_handle_t; -/** - * @} - */ - - -/** @defgroup PIS_Private_Macros PIS Private Macros - * @{ - */ -#define IS_PIS(x) (((x) == PIS)) -#define IS_PIS_SRC(x) (((x) == PIS_NON) || \ - ((x) == PIS_GPIO_PIN0) || \ - ((x) == PIS_GPIO_PIN1) || \ - ((x) == PIS_GPIO_PIN2) || \ - ((x) == PIS_GPIO_PIN3) || \ - ((x) == PIS_GPIO_PIN4) || \ - ((x) == PIS_GPIO_PIN5) || \ - ((x) == PIS_GPIO_PIN6) || \ - ((x) == PIS_GPIO_PIN7) || \ - ((x) == PIS_GPIO_PIN8) || \ - ((x) == PIS_GPIO_PIN9) || \ - ((x) == PIS_GPIO_PIN10) || \ - ((x) == PIS_GPIO_PIN11) || \ - ((x) == PIS_GPIO_PIN12) || \ - ((x) == PIS_GPIO_PIN13) || \ - ((x) == PIS_GPIO_PIN14) || \ - ((x) == PIS_GPIO_PIN15) || \ - ((x) == PIS_ACMP_OUT0) || \ - ((x) == PIS_ACMP_OUT1) || \ - ((x) == PIS_DAC0_CH1) || \ - ((x) == PIS_ACMP_OUT1) || \ - ((x) == PIS_ADC0_INJECT) || \ - ((x) == PIS_ADC0_REGULAT) || \ - ((x) == PIS_ADC0_WINDOW) || \ - ((x) == PIS_LVD) || \ - ((x) == PIS_UART0_ASY_SEND) || \ - ((x) == PIS_UART0_ASY_RECV) || \ - ((x) == PIS_UART0_IRDAOUT) || \ - ((x) == PIS_UART0_RTSOUT) || \ - ((x) == PIS_UART0_TXOUT) || \ - ((x) == PIS_UART0_SYN_SEND) || \ - ((x) == PIS_UART0_SYN_RECV) || \ - ((x) == PIS_UART1_ASY_SEND) || \ - ((x) == PIS_UART1_ASY_RECV) || \ - ((x) == PIS_UART1_IRDA) || \ - ((x) == PIS_UART1_RTS) || \ - ((x) == PIS_UART1_TXOUT) || \ - ((x) == PIS_UART1_SYN_SEND) || \ - ((x) == PIS_UART1_SYN_RECV) || \ - ((x) == PIS_UART2_ASY_SEND) || \ - ((x) == PIS_UART2_ASY_RECV) || \ - ((x) == PIS_UART2_IRDA) || \ - ((x) == PIS_UART2_RTS) || \ - ((x) == PIS_UART2_TXOUT) || \ - ((x) == PIS_UART2_SYN_SEND) || \ - ((x) == PIS_UART2_SYN_RECV) || \ - ((x) == PIS_UART3_ASY_SEND) || \ - ((x) == PIS_UART3_ASY_RECV) || \ - ((x) == PIS_UART3_IRDA) || \ - ((x) == PIS_UART3_RTS) || \ - ((x) == PIS_UART3_TXOUT) || \ - ((x) == PIS_UART3_SYN_SEND) || \ - ((x) == PIS_UART3_SYN_RECV) || \ - ((x) == PIS_EUART0_RECV) || \ - ((x) == PIS_EUART0_SEND) || \ - ((x) == PIS_EUART0_TXOUT) || \ - ((x) == PIS_EUART1_RECV) || \ - ((x) == PIS_EUART1_SEND) || \ - ((x) == PIS_EUART1_TXOUT) || \ - ((x) == PIS_SPI0_RECV) || \ - ((x) == PIS_SPI0_SEND) || \ - ((x) == PIS_SPI0_NE) || \ - ((x) == PIS_SPI1_RECV) || \ - ((x) == PIS_SPI1_SEND) || \ - ((x) == PIS_SPI1_NE) || \ - ((x) == PIS_I2C0_RECV) || \ - ((x) == PIS_I2C0_SEND) || \ - ((x) == PIS_I2C1_RECV) || \ - ((x) == PIS_I2C1_SEND) || \ - ((x) == PIS_TIMER0_UPDATA) || \ - ((x) == PIS_TIMER0_TRIG) || \ - ((x) == PIS_TIMER0_INPUT) || \ - ((x) == PIS_TIMER0_OUTPUT) || \ - ((x) == PIS_TIMER1_UPDATA) || \ - ((x) == PIS_TIMER1_TRIG) || \ - ((x) == PIS_TIMER1_INPUT) || \ - ((x) == PIS_TIMER1_OUTPUT) || \ - ((x) == PIS_TIMER2_UPDATA) || \ - ((x) == PIS_TIMER2_TRIG) || \ - ((x) == PIS_TIMER2_INPUT) || \ - ((x) == PIS_TIMER2_OUTPUT) || \ - ((x) == PIS_TIMER3_UPDATA) || \ - ((x) == PIS_TIMER3_TRIG) || \ - ((x) == PIS_TIMER3_INPUT) || \ - ((x) == PIS_TIMER3_OUTPUT) || \ - ((x) == PIS_RTC_CLOCK) || \ - ((x) == PIS_RTC_ALARM) || \ - ((x) == PIS_LPTIM0_SYN_UPDATA) || \ - ((x) == PIS_LPTIM0_ASY_UPDATA) || \ - ((x) == PIS_LPUART0_ASY_RECV) || \ - ((x) == PIS_LPUART0_ASY_SEND) || \ - ((x) == PIS_LPUART0_SYN_RECV) || \ - ((x) == PIS_LPUART0_SYN_SEND) || \ - ((x) == PIS_DMA) || \ - ((x) == PIS_ADC1_INJECT) || \ - ((x) == PIS_ADC1_REGULAT) || \ - ((x) == PIS_ADC1_WINDOW)) -#define IS_PIS_TRIG(x) (((x) == PIS_CH0_TIMER0_BRKIN) || \ - ((x) == PIS_CH0_SPI1_CLK) || \ - ((x) == PIS_CH0_LPTIM0_EXT0) || \ - ((x) == PIS_CH0_ADC1_NORMAL) || \ - ((x) == PIS_CH1_TIMER0_CH1IN) || \ - ((x) == PIS_CH1_TIMER2_CH1IN) || \ - ((x) == PIS_CH1_TIMER3_CH1IN) || \ - ((x) == PIS_CH1_UART0_RX_IRDA) || \ - ((x) == PIS_CH1_LPTIM0_EXT1) || \ - ((x) == PIS_CH1_ADC1_INSERT) || \ - ((x) == PIS_CH2_TIMER0_CH2IN) || \ - ((x) == PIS_CH2_TIMER2_CH2IN) || \ - ((x) == PIS_CH2_TIMER3_CH2IN) || \ - ((x) == PIS_CH2_LPTIM0_EXT2) || \ - ((x) == PIS_CH2_UART1_RX_IRDA) || \ - ((x) == PIS_CH3_TIMER0_CH3IN) || \ - ((x) == PIS_CH3_LPTIM0_EXT3) || \ - ((x) == PIS_CH3_UART2_RX_IRDA) || \ - ((x) == PIS_CH4_TIMER0_CH4IN) || \ - ((x) == PIS_CH4_TIMER0_ITR0) || \ - ((x) == PIS_CH4_TIMER2_ITR0) || \ - ((x) == PIS_CH4_TIMER3_ITR0) || \ - ((x) == PIS_CH4_LPTIM0_EXT4) || \ - ((x) == PIS_CH4_UART3_RX_IRDA) || \ - ((x) == PIS_CH5_SPI0_RX) || \ - ((x) == PIS_CH5_LPTIM0_EXT5) || \ - ((x) == PIS_CH5_EUART0_RX) || \ - ((x) == PIS_CH5_TIMER0_ITR1) || \ - ((x) == PIS_CH5_TIMER2_ITR1) || \ - ((x) == PIS_CH5_TIMER3_ITR1) || \ - ((x) == PIS_CH6_SPI0_CLK) || \ - ((x) == PIS_CH6_ADC0_NORMAL) || \ - ((x) == PIS_CH6_LPTIM0_EXT6) || \ - ((x) == PIS_CH6_EUART1_RX) || \ - ((x) == PIS_CH6_TIMER0_ITR2) || \ - ((x) == PIS_CH6_TIMER2_ITR2) || \ - ((x) == PIS_CH6_TIMER3_ITR2) || \ - ((x) == PIS_CH6_DAC_CH1) || \ - ((x) == PIS_CH7_SPI1_RX) || \ - ((x) == PIS_CH7_ADC0_INSERT) || \ - ((x) == PIS_CH7_LPTIM0_EXT7) || \ - ((x) == PIS_CH7_DMA) || \ - ((x) == PIS_CH7_TIMER0_ITR3) || \ - ((x) == PIS_CH7_TIMER2_ITR3) || \ - ((x) == PIS_CH7_TIMER3_ITR3) || \ - ((x) == PIS_CH7_DAC_CH0) || \ - ((x) == PIS_CH7_LPUART_RX)) -#define IS_PIS_CLOCK(x) (((x) == PIS_CLK_PCLK1) || \ - ((x) == PIS_CLK_PCLK2) || \ - ((x) == PIS_CLK_SYS) || \ - ((x) == PIS_CLK_LP)) -#define IS_PIS_EDGE(x) (((x) == PIS_EDGE_NONE) || \ - ((x) == PIS_EDGE_UP) || \ - ((x) == PIS_EDGE_DOWN) || \ - ((x) == PIS_EDGE_UP_DOWN)) -#define IS_PIS_OUTPUT(x) (((x) == PIS_OUT_LEVEL) || \ - ((x) == PIS_OUT_PULSE)) -#define IS_PIS_OUPUT_CH(x) (((x) == PIS_OUT_CH_0) || \ - ((x) == PIS_OUT_CH_1) || \ - ((x) == PIS_OUT_CH_2) || \ - ((x) == PIS_OUT_CH_3)) -#define IS_PIS_MODU_TARGET(x) (((x) == PIS_UART0_TX) || \ - ((x) == PIS_UART1_TX) || \ - ((x) == PIS_UART2_TX) || \ - ((x) == PIS_UART3_TX) || \ - ((x) == PIS_LPUART0_TX)) -#define IS_PIS_MODU_LEVEL(x) (((x) == PIS_LOW_LEVEL) || \ - ((x) == PIS_HIGH_LEVEL)) -#define IS_PIS_MODU_SRC(x) (((x) == PIS_SRC_NONE) || \ - ((x) == PIS_SRC_TIMER0) || \ - ((x) == PIS_SRC_TIMER1) || \ - ((x) == PIS_SRC_TIMER2) || \ - ((x) == PIS_SRC_TIMER3) || \ - ((x) == PIS_SRC_TIMER6) || \ - ((x) == PIS_SRC_TIMER7) || \ - ((x) == PIS_SRC_LPTIM0) || \ - ((x) == PIS_SRC_BUZ)) -#define IS_PIS_MODU_CHANNEL(x) (((x) == PIS_TIMER_CH1) || \ - ((x) == PIS_TIMER_CH2) || \ - ((x) == PIS_TIMER_CH3) || \ - ((x) == PIS_TIMER_CH4)) -/** - * @} - */ - -/** @addtogroup PIS_Public_Functions - * @{ - */ - -/** @addtogroup PIS_Public_Functions_Group1 - * @{ - */ -ald_status_t ald_pis_create(pis_handle_t *hperh); -ald_status_t ald_pis_destroy(pis_handle_t *hperh); -/** - * @} - */ - -/** @addtogroup PIS_Public_Functions_Group2 - * @{ - */ -ald_status_t ald_pis_output_start(pis_handle_t *hperh, pis_out_ch_t ch); -ald_status_t ald_pis_output_stop(pis_handle_t *hperh, pis_out_ch_t ch); -/** - * @} - */ - -/** @addtogroup PIS_Public_Functions_Group3 - * @{ - */ -pis_state_t ald_pis_get_state(pis_handle_t *hperh); -/** - * @} - */ - -/** @addtogroup PIS_Public_Functions_Group4 - * @{ - */ -ald_status_t ald_pis_modu_config(pis_handle_t *hperh, pis_modulate_config_t *config); -/** - * @} - */ - -/** - * @} - */ - -/** - * @} - */ - -/** - * @} - */ - -#ifdef __cplusplus -} -#endif - -#endif /* __ALD_PIS_H__ */ diff --git a/bsp/essemi/es32f0334/libraries/ES32F033x_ALD_StdPeriph_Driver/Include/ald_pmu.h b/bsp/essemi/es32f0334/libraries/ES32F033x_ALD_StdPeriph_Driver/Include/ald_pmu.h deleted file mode 100644 index 13f5977459..0000000000 --- a/bsp/essemi/es32f0334/libraries/ES32F033x_ALD_StdPeriph_Driver/Include/ald_pmu.h +++ /dev/null @@ -1,251 +0,0 @@ -/** - ********************************************************************************* - * - * @file ald_pmu.h - * @brief Header file of PMU module driver. - * - * @version V1.0 - * @date 04 Dec 2017 - * @author AE Team - * @note - * - * Copyright (C) Shanghai Eastsoft Microelectronics Co. Ltd. All rights reserved. - * - ******************************************************************************** - */ - -#ifndef __ALD_PMU_H__ -#define __ALD_PMU_H__ - -#ifdef __cplusplus -extern "C" { -#endif - -#include "utils.h" -#include "ald_syscfg.h" -#include "ald_bkpc.h" - - -/** @addtogroup ES32FXXX_ALD - * @{ - */ - -/** @addtogroup PMU - * @{ - */ - -/** @defgroup PMU_Public_Macros PMU Public Macros - * @{ - */ -#define PMU_SRAM0_ENABLE() \ -do { \ - SYSCFG_UNLOCK(); \ - SET_BIT(PMU->PWRCR, BIT(PMU_PWRCR_SRAM_POSS)); \ - SYSCFG_LOCK(); \ -} while (0) -#define PMU_SRAM0_DISABLE() \ -do { \ - SYSCFG_UNLOCK(); \ - CLEAR_BIT(PMU->PWRCR, BIT(PMU_PWRCR_SRAM_POSS));\ - SYSCFG_LOCK(); \ -} while (0) -#define PMU_SRAM1_ENABLE() \ -do { \ - SYSCFG_UNLOCK(); \ - SET_BIT(PMU->PWRCR, BIT(PMU_PWRCR_SRAM_POSE)); \ - SYSCFG_LOCK(); \ -} while (0) -#define PMU_SRAM1_DISABLE() \ -do { \ - SYSCFG_UNLOCK(); \ - CLEAR_BIT(PMU->PWRCR, BIT(PMU_PWRCR_SRAM_POSE));\ - SYSCFG_LOCK(); \ -} while (0) -#define PMU_BXCAN_ENABLE() \ -do { \ - SYSCFG_UNLOCK(); \ - SET_BIT(PMU->PWRCR, PMU_PWRCR_BXCAN_MSK); \ - SYSCFG_LOCK(); \ -} while (0) -#define PMU_BXCAN_DISABLE() \ -do { \ - SYSCFG_UNLOCK(); \ - CLEAR_BIT(PMU->PWRCR, PMU_PWRCR_BXCAN_MSK); \ - SYSCFG_LOCK(); \ -} while (0) - -#define PMU_LPSTOP_ENABLE() \ -do { \ - SYSCFG_UNLOCK(); \ - SET_BIT(PMU->CR, PMU_CR_LPSTOP_MSK); \ - SYSCFG_LOCK(); \ -} while (0) -#define PMU_LPSTOP_DISABLE() \ -do { \ - SYSCFG_UNLOCK(); \ - CLEAR_BIT(PMU->CR, PMU_CR_LPSTOP_MSK); \ - SYSCFG_LOCK(); \ -} while (0) -#define PMU_MTSTOP_ENABLE() \ -do { \ - SYSCFG_UNLOCK(); \ - SET_BIT(PMU->CR, PMU_CR_MTSTOP_MSK); \ - SYSCFG_LOCK(); \ -} while (0) -#define PMU_MTSTOP_DISABLE() \ -do { \ - SYSCFG_UNLOCK(); \ - CLEAR_BIT(PMU->CR, PMU_CR_MTSTOP_MSK); \ - SYSCFG_LOCK(); \ -} while (0) - -#define PMU_GET_LVD_STATUS() (READ_BITS(PMU->LVDCR, PMU_LVDCR_LVDO_MSK, PMU_LVDCR_LVDO_POS)) -/** - * @} - */ - - -/** @defgroup PMU_Public_Types PMU Public Types - * @{ - */ -/** - * @brief Low power mode - */ -typedef enum { - PMU_LP_STOP1 = 0x0U, /**< Stop1 */ - PMU_LP_STOP2 = 0x1U, /**< Stop2 */ - PMU_LP_STANDBY = 0x2U, /**< Standby */ -} pmu_lp_mode_t; - -typedef enum { - PMU_SR_WUF = (1U << 0), - PMU_SR_STANDBY = (1U << 1), -} pmu_status_t; - -/** - * @brief LVD voltage select - */ -typedef enum { - PMU_LVD_VOL_SEL_2_0 = 0x0U, /**< 2.0V ~ 2.05V */ - PMU_LVD_VOL_SEL_2_1 = 0x1U, /**< 2.1V ~ 2.15V */ - PMU_LVD_VOL_SEL_2_2 = 0x2U, /**< 2.2V ~ 2.25V */ - PMU_LVD_VOL_SEL_2_4 = 0x3U, /**< 2.4V ~ 2.45V */ - PMU_LVD_VOL_SEL_2_6 = 0x4U, /**< 2.6V ~ 2.65V */ - PMU_LVD_VOL_SEL_2_8 = 0x5U, /**< 2.8V ~ 2.85V */ - PMU_LVD_VOL_SEL_3_0 = 0x6U, /**< 3.0V ~ 3.05V */ - PMU_LVD_VOL_SEL_3_6 = 0x7U, /**< 3.6V ~ 3.65V */ - PMU_LVD_VOL_SEL_4_0 = 0x8U, /**< 4.0V ~ 4.05V */ - PMU_LVD_VOL_SEL_4_6 = 0x9U, /**< 4.6V ~ 4.65V */ - PMU_LVD_VOL_SEL_2_3 = 0xAU, /**< 2.3V ~ 2.35V */ - PMU_LVD_VOL_SEL_EXT = 0xFU, /**< Select external input. It must be 1.2V */ -} pmu_lvd_voltage_sel_t; - -/** - * @brief LVD trigger mode - */ -typedef enum { - PMU_LVD_TRIGGER_RISING_EDGE = 0x0U, /**< Rising edge */ - PMU_LVD_TRIGGER_FALLING_EDGE = 0x1U, /**< Falling edge */ - PMU_LVD_TRIGGER_HIGH_LEVEL = 0x2U, /**< High level */ - PMU_LVD_TRIGGER_LOW_LEVEL = 0x3U, /**< Low level */ - PMU_LVD_TRIGGER_RISING_FALLING = 0x4U, /**< Rising and falling edge */ -} pmu_lvd_trigger_mode_t; - -/** - * @brief LDO output voltage selest in low power mode - */ -typedef enum { - PMU_LDO_LPMODE_OUTPUT_1_5 = 0x0U, /**< 1.5V */ - PMU_LDO_LPMODE_OUTPUT_1_4 = 0x1U, /**< 1.4V */ - PMU_LDO_LPMODE_OUTPUT_1_3 = 0x2U, /**< 1.3V */ - PMU_LDO_LPMODE_OUTPUT_1_2 = 0x4U, /**< 1.2V */ -} pmu_ldo_lpmode_output_t; -/** - * @} - */ - -/** - * @defgroup PMU_Private_Macros PMU Private Macros - * @{ - */ -#define IS_PMU_LP_MODE(x) (((x) == PMU_LP_STOP1) || \ - ((x) == PMU_LP_STOP2) || \ - ((x) == PMU_LP_STANDBY)) -#define IS_PMU_STATUS(x) (((x) == PMU_SR_WUF) || ((x) == PMU_SR_STANDBY)) -#define IS_PMU_LVD_VOL_SEL(x) (((x) == PMU_LVD_VOL_SEL_2_0) || \ - ((x) == PMU_LVD_VOL_SEL_2_1) || \ - ((x) == PMU_LVD_VOL_SEL_2_2) || \ - ((x) == PMU_LVD_VOL_SEL_2_4) || \ - ((x) == PMU_LVD_VOL_SEL_2_6) || \ - ((x) == PMU_LVD_VOL_SEL_2_8) || \ - ((x) == PMU_LVD_VOL_SEL_3_0) || \ - ((x) == PMU_LVD_VOL_SEL_3_6) || \ - ((x) == PMU_LVD_VOL_SEL_4_0) || \ - ((x) == PMU_LVD_VOL_SEL_4_6) || \ - ((x) == PMU_LVD_VOL_SEL_2_3) || \ - ((x) == PMU_LVD_VOL_SEL_EXT)) -#define IS_PMU_LVD_TRIGGER_MODE(x) (((x) == PMU_LVD_TRIGGER_RISING_EDGE) || \ - ((x) == PMU_LVD_TRIGGER_FALLING_EDGE) || \ - ((x) == PMU_LVD_TRIGGER_HIGH_LEVEL) || \ - ((x) == PMU_LVD_TRIGGER_LOW_LEVEL) || \ - ((x) == PMU_LVD_TRIGGER_RISING_FALLING)) -#define IS_PMU_LDO_LPMODE_OUTPUT(x) (((x) == PMU_LDO_LPMODE_OUTPUT_1_5) || \ - ((x) == PMU_LDO_LPMODE_OUTPUT_1_4) || \ - ((x) == PMU_LDO_LPMODE_OUTPUT_1_3) || \ - ((x) == PMU_LDO_LPMODE_OUTPUT_1_2)) -/** - * @} - */ - -/** @addtogroup PMU_Public_Functions - * @{ - */ -/** @addtogroup PMU_Public_Functions_Group1 - * @{ - */ -/* Low power mode select */ -__STATIC_INLINE__ void ald_pmu_sleep() -{ - __WFI(); -} - -__STATIC_INLINE__ void ald_pmu_sleep_deep() -{ - SCB->SCR |= SCB_SCR_SLEEPDEEP_Msk; - __WFI(); -} - -void ald_pmu_stop1_enter(void); -void ald_pmu_stop2_enter(void); -void ald_pmu_standby_enter(bkpc_wakeup_port_t port, bkpc_wakeup_level_t level); -void ald_pmu_lprun_config(pmu_ldo_lpmode_output_t vol, type_func_t state); -flag_status_t ald_pmu_get_status(pmu_status_t sr); -void ald_pmu_clear_status(pmu_status_t sr); -/** - * @} - */ -/** @addtogroup PMU_Public_Functions_Group2 - * @{ - */ -/* LVD configure */ -void ald_pmu_lvd_config(pmu_lvd_voltage_sel_t sel, pmu_lvd_trigger_mode_t mode, type_func_t state); -void ald_lvd_irq_handler(void); -/** - * @} - */ -/** - * @} - */ - -/** - * @} - */ - -/** - * @} - */ -#ifdef __cplusplus -} -#endif - -#endif /* __ALD_PMU_H__ */ diff --git a/bsp/essemi/es32f0334/libraries/ES32F033x_ALD_StdPeriph_Driver/Include/ald_rmu.h b/bsp/essemi/es32f0334/libraries/ES32F033x_ALD_StdPeriph_Driver/Include/ald_rmu.h deleted file mode 100644 index 164ebb5e3f..0000000000 --- a/bsp/essemi/es32f0334/libraries/ES32F033x_ALD_StdPeriph_Driver/Include/ald_rmu.h +++ /dev/null @@ -1,288 +0,0 @@ -/** - ********************************************************************************* - * - * @file ald_rmu.h - * @brief Header file of RMU module driver. - * - * @version V1.0 - * @date 04 Dec 2017 - * @author AE Team - * @note - * - * Copyright (C) Shanghai Eastsoft Microelectronics Co. Ltd. All rights reserved. - * - ******************************************************************************** - */ - -#ifndef __ALD_RMU_H__ -#define __ALD_RMU_H__ - -#ifdef __cplusplus -extern "C" { -#endif - -#include "utils.h" - -/** @addtogroup ES32FXXX_ALD - * @{ - */ - -/** @addtogroup RMU - * @{ - */ - -/** @defgroup RMU_Public_Types RMU Public Types - * @{ - */ -/** - * @brief RMU BOR fliter - */ -typedef enum { - RMU_BORFLT_1 = 0x1U, /**< 1 cycle */ - RMU_BORFLT_2 = 0x2U, /**< 2 cycles */ - RMU_BORFLT_3 = 0x3U, /**< 3 cycles */ - RMU_BORFLT_4 = 0x4U, /**< 4 cycles */ - RMU_BORFLT_5 = 0x5U, /**< 5 cycles */ - RMU_BORFLT_6 = 0x6U, /**< 6 cycles */ - RMU_BORFLT_7 = 0x7U, /**< 7 cycles */ -} rmu_bor_filter_t; - -/** - * @brief RMU BOR voltage - */ -typedef enum { - RMU_VOL_1_8 = 0x0U, /**< 1.8V */ - RMU_VOL_2_0 = 0x1U, /**< 2.0V */ - RMU_VOL_2_2 = 0x2U, /**< 2.2V */ - RMU_VOL_2_4 = 0x3U, /**< 2.4V */ - RMU_VOL_2_6 = 0x4U, /**< 2.6V */ - RMU_VOL_2_8 = 0x5U, /**< 2.8V */ - RMU_VOL_3_0 = 0x6U, /**< 3.0V */ - RMU_VOL_3_2 = 0x7U, /**< 3.2V */ - RMU_VOL_3_4 = 0x8U, /**< 3.4V */ - RMU_VOL_3_6 = 0x9U, /**< 3.6V */ - RMU_VOL_3_8 = 0xAU, /**< 3.8V */ - RMU_VOL_4_0 = 0xBU, /**< 4.0V */ - RMU_VOL_4_2 = 0xCU, /**< 4.2V */ - RMU_VOL_4_4 = 0xDU, /**< 4.4V */ - RMU_VOL_4_6 = 0xEU, /**< 4.6V */ - RMU_VOL_4_8 = 0xFU, /**< 4.8V */ -} rmu_bor_vol_t; - -/** - * @brief RMU reset status - */ -typedef enum { - RMU_RST_POR = (1U << 0), /**< POR */ - RMU_RST_WAKEUP = (1U << 1), /**< WAKEUP */ - RMU_RST_BOR = (1U << 2), /**< BOR */ - RMU_RST_NMRST = (1U << 3), /**< NMRST */ - RMU_RST_IWDT = (1U << 4), /**< IWDT */ - RMU_RST_WWDT = (1U << 5), /**< WWDT */ - RMU_RST_LOCKUP = (1U << 6), /**< LOCKUP */ - RMU_RST_CHIP = (1U << 7), /**< CHIP */ - RMU_RST_MCU = (1U << 8), /**< MCU */ - RMU_RST_CPU = (1U << 9), /**< CPU */ - RMU_RST_CFG = (1U << 10), /**< CFG */ - RMU_RST_CFGERR = (1U << 16), /**< CFG Error */ - RMU_RST_ALL = (0xFFFFFU), /**< ALL */ -} rmu_state_t; - -/** - * @brief RMU periperal select bit - * @verbatim - In this module, for the convenience of code maintenance, - TIMERx is used to indicate the sequence of the timer peripheral. - Different product series TIMERx represent different meanings: - 1. For ES32F065x series: - TIMER0 ----> AD16C4T0 - TIMER1 ----> BS16T0 - TIMER2 ----> GP16C2T0 - TIMER3 ----> GP16C2T1 - TIMER4 ----> BS16T1 - TIMER5 ----> BS16T2 - TIMER6 ----> GP16C4T0 - TIMER7 ----> BS16T3 - - 2. For ES32F033x/ES32F093x series: - TIMER0 ----> GP16C4T0 - TIMER1 ----> BS16T0 - TIMER2 ----> GP16C2T0 - TIMER3 ----> GP16C2T1 - TIMER4 ----> BS16T1 - TIMER5 ----> BS16T2 - TIMER6 ----> GP16C4T1 - TIMER7 ----> BS16T3 - @endverbatim - */ -typedef enum { - RMU_PERH_GPIO = (1U << 0), /**< AHB1: GPIO */ - RMU_PERH_CRC = (1U << 1), /**< AHB1: CRC */ - RMU_PERH_CALC = (1U << 2), /**< AHB1: CALC */ - RMU_PERH_CRYPT = (1U << 3), /**< AHB1: CRYPT */ - RMU_PERH_TRNG = (1U << 4), /**< AHB1: TRNG */ - RMU_PERH_PIS = (1U << 5), /**< AHB1: PIS */ - RMU_PERH_CHIP = (1U << 0) | (1U << 27), /**< AHB2: CHIP */ - RMU_PERH_CPU = (1U << 1) | (1U << 27), /**< AHB2: CPU */ - RMU_PERH_TIMER0 = (1U << 0) | (1U << 28), /**< APB1: TIMER0 */ - RMU_PERH_TIMER1 = (1U << 1) | (1U << 28), /**< APB1: TIMER1 */ - RMU_PERH_TIMER2 = (1U << 2) | (1U << 28), /**< APB1: TIMER2 */ - RMU_PERH_TIMER3 = (1U << 3) | (1U << 28), /**< APB1: TIMER3 */ - RMU_PERH_TIMER4 = (1U << 4) | (1U << 28), /**< APB1: TIMER4 */ - RMU_PERH_TIMER5 = (1U << 5) | (1U << 28), /**< APB1: TIMER5 */ - RMU_PERH_TIMER6 = (1U << 6) | (1U << 28), /**< APB1: TIMER6 */ - RMU_PERH_TIMER7 = (1U << 7) | (1U << 28), /**< APB1: TIMER7 */ - RMU_PERH_UART0 = (1U << 8) | (1U << 28), /**< APB1: UART0 */ - RMU_PERH_UART1 = (1U << 9) | (1U << 28), /**< APB1: UART1 */ - RMU_PERH_UART2 = (1U << 10) | (1U << 28), /**< APB1: UART2 */ - RMU_PERH_UART3 = (1U << 11) | (1U << 28), /**< APB1: UART3 */ - RMU_PERH_USART0 = (1U << 12) | (1U << 28), /**< APB1: EUART0 */ - RMU_PERH_USART1 = (1U << 13) | (1U << 28), /**< APB1: EUART1 */ - RMU_PERH_SPI0 = (1U << 16) | (1U << 28), /**< APB1: SPI0 */ - RMU_PERH_SPI1 = (1U << 17) | (1U << 28), /**< APB1: SPI1 */ - RMU_PERH_SPI2 = (1U << 18) | (1U << 28), /**< APB1: SPI2 */ - RMU_PERH_I2C0 = (1U << 20) | (1U << 28), /**< APB1: I2C0 */ - RMU_PERH_I2C1 = (1U << 21) | (1U << 28), /**< APB1: I2C1 */ - RMU_PERH_CAN0 = (1U << 24) | (1U << 28), /**< APB1: CAN0 */ - RMU_PERH_LPTIM0 = (1U << 0) | (1U << 29), /**< APB2: LPTIM0 */ - RMU_PERH_LPUART0 = (1U << 2) | (1U << 29), /**< APB2: LPUART */ - RMU_PERH_ADC0 = (1U << 4) | (1U << 29), /**< APB2: ADC0 */ - RMU_PERH_ADC1 = (1U << 5) | (1U << 29), /**< APB2: ADC1 */ - RMU_PERH_ACMP0 = (1U << 6) | (1U << 29), /**< APB2: ACMP0 */ - RMU_PERH_ACMP1 = (1U << 7) | (1U << 29), /**< APB2: ACMP1 */ - RMU_PERH_OPAMP = (1U << 8) | (1U << 29), /**< APB2: OPAMP */ - RMU_PERH_DAC0 = (1U << 9) | (1U << 29), /**< APB2: DAC0 */ - RMU_PERH_WWDT = (1U << 12) | (1U << 29), /**< APB2: WWDT */ - RMU_PERH_LCD = (1U << 13) | (1U << 29), /**< APB2: LCD */ - RMU_PERH_IWDT = (1U << 14) | (1U << 29), /**< APB2: IWDT */ - RMU_PERH_RTC = (1U << 15) | (1U << 29), /**< APB2: RTC */ - RMU_PERH_TSENSE = (1U << 16) | (1U << 29), /**< APB2: TSENSE */ - RMU_PERH_BKPC = (1U << 17) | (1U << 29), /**< APB2: BKPC */ - RMU_PERH_BKPRAM = (1U << 18) | (1U << 29), /**< APB2: BKPRAM */ -} rmu_peripheral_t; -/** - * @} - */ - -/** - * @defgroup RMU_Private_Macros RMU Private Macros - * @{ - */ -#define IS_RMU_BORFLT(x) (((x) == RMU_BORFLT_1) || \ - ((x) == RMU_BORFLT_2) || \ - ((x) == RMU_BORFLT_3) || \ - ((x) == RMU_BORFLT_4) || \ - ((x) == RMU_BORFLT_5) || \ - ((x) == RMU_BORFLT_6) || \ - ((x) == RMU_BORFLT_7)) -#define IS_RMU_BORVOL(x) (((x) == RMU_VOL_1_8) || \ - ((x) == RMU_VOL_2_0) || \ - ((x) == RMU_VOL_2_2) || \ - ((x) == RMU_VOL_2_4) || \ - ((x) == RMU_VOL_2_6) || \ - ((x) == RMU_VOL_2_8) || \ - ((x) == RMU_VOL_3_0) || \ - ((x) == RMU_VOL_3_2) || \ - ((x) == RMU_VOL_3_4) || \ - ((x) == RMU_VOL_3_6) || \ - ((x) == RMU_VOL_3_8) || \ - ((x) == RMU_VOL_4_0) || \ - ((x) == RMU_VOL_4_2) || \ - ((x) == RMU_VOL_4_4) || \ - ((x) == RMU_VOL_4_6) || \ - ((x) == RMU_VOL_4_8)) -#define IS_RMU_STATE(x) (((x) == RMU_RST_POR) || \ - ((x) == RMU_RST_WAKEUP) || \ - ((x) == RMU_RST_BOR) || \ - ((x) == RMU_RST_NMRST) || \ - ((x) == RMU_RST_IWDT) || \ - ((x) == RMU_RST_WWDT) || \ - ((x) == RMU_RST_LOCKUP) || \ - ((x) == RMU_RST_CHIP) || \ - ((x) == RMU_RST_MCU) || \ - ((x) == RMU_RST_CPU) || \ - ((x) == RMU_RST_CFG) || \ - ((x) == RMU_RST_CFGERR) || \ - ((x) == RMU_RST_ALL)) -#define IS_RMU_STATE_CLEAR(x) (((x) == RMU_RST_POR) || \ - ((x) == RMU_RST_WAKEUP) || \ - ((x) == RMU_RST_BOR) || \ - ((x) == RMU_RST_NMRST) || \ - ((x) == RMU_RST_IWDT) || \ - ((x) == RMU_RST_WWDT) || \ - ((x) == RMU_RST_LOCKUP) || \ - ((x) == RMU_RST_CHIP) || \ - ((x) == RMU_RST_MCU) || \ - ((x) == RMU_RST_CPU) || \ - ((x) == RMU_RST_CFG) || \ - ((x) == RMU_RST_ALL)) -#define IS_RMU_PERH(x) (((x) == RMU_PERH_GPIO) || \ - ((x) == RMU_PERH_CRC) || \ - ((x) == RMU_PERH_CALC) || \ - ((x) == RMU_PERH_CRYPT) || \ - ((x) == RMU_PERH_TRNG) || \ - ((x) == RMU_PERH_PIS) || \ - ((x) == RMU_PERH_CHIP) || \ - ((x) == RMU_PERH_CPU) || \ - ((x) == RMU_PERH_TIMER0) || \ - ((x) == RMU_PERH_TIMER1) || \ - ((x) == RMU_PERH_TIMER2) || \ - ((x) == RMU_PERH_TIMER3) || \ - ((x) == RMU_PERH_TIMER4) || \ - ((x) == RMU_PERH_TIMER5) || \ - ((x) == RMU_PERH_TIMER6) || \ - ((x) == RMU_PERH_TIMER7) || \ - ((x) == RMU_PERH_UART0) || \ - ((x) == RMU_PERH_UART1) || \ - ((x) == RMU_PERH_UART2) || \ - ((x) == RMU_PERH_UART3) || \ - ((x) == RMU_PERH_USART0) || \ - ((x) == RMU_PERH_USART1) || \ - ((x) == RMU_PERH_SPI0) || \ - ((x) == RMU_PERH_SPI1) || \ - ((x) == RMU_PERH_SPI2) || \ - ((x) == RMU_PERH_I2C0) || \ - ((x) == RMU_PERH_I2C1) || \ - ((x) == RMU_PERH_CAN0) || \ - ((x) == RMU_PERH_LPTIM0) || \ - ((x) == RMU_PERH_LPUART0) || \ - ((x) == RMU_PERH_ADC0) || \ - ((x) == RMU_PERH_ADC1) || \ - ((x) == RMU_PERH_ACMP0) || \ - ((x) == RMU_PERH_ACMP1) || \ - ((x) == RMU_PERH_OPAMP) || \ - ((x) == RMU_PERH_DAC0) || \ - ((x) == RMU_PERH_WWDT) || \ - ((x) == RMU_PERH_LCD) || \ - ((x) == RMU_PERH_IWDT) || \ - ((x) == RMU_PERH_RTC) || \ - ((x) == RMU_PERH_TSENSE) || \ - ((x) == RMU_PERH_BKPC) || \ - ((x) == RMU_PERH_BKPRAM)) -/** - * @} - */ - -/** @addtogroup RMU_Public_Functions - * @{ - */ -void ald_rmu_bor_config(rmu_bor_filter_t flt, rmu_bor_vol_t vol, type_func_t state); -uint32_t ald_rmu_get_reset_status(rmu_state_t state); -void ald_rmu_clear_reset_status(rmu_state_t state); -void ald_rmu_reset_periperal(rmu_peripheral_t perh); -/** - * @} - */ - -/** - * @} - */ - -/** - * @} - */ -#ifdef __cplusplus -} -#endif - -#endif /* __ALD_RMU_H__ */ diff --git a/bsp/essemi/es32f0334/libraries/ES32F033x_ALD_StdPeriph_Driver/Include/ald_rtc.h b/bsp/essemi/es32f0334/libraries/ES32F033x_ALD_StdPeriph_Driver/Include/ald_rtc.h deleted file mode 100644 index dd5d8ad7ee..0000000000 --- a/bsp/essemi/es32f0334/libraries/ES32F033x_ALD_StdPeriph_Driver/Include/ald_rtc.h +++ /dev/null @@ -1,669 +0,0 @@ -/** - ****************************************************************************** - * @file ald_rtc.h - * @brief Header file of RTC Module driver. - * - * @version V1.0 - * @date 16 Nov 2017 - * @author AE Team - * @note - * - * Copyright (C) Shanghai Eastsoft Microelectronics Co. Ltd. All rights reserved. - * - ******************************************************************************* - */ - -#ifndef __ALD_RTC_H__ -#define __ALD_RTC_H__ - -#ifdef __cplusplus -extern "C" { -#endif - -#include "utils.h" - - -/** @addtogroup ES32FXXX_ALD - * @{ - */ - -/** @addtogroup RTC - * @{ - */ - -/** @defgroup RTC_Public_Types RTC Public Types - * @{ - */ - -/** - * @brief Hours format - */ -typedef enum { - RTC_HOUR_FORMAT_24 = 0x0U, /**< 24-hours format */ - RTC_HOUR_FORMAT_12 = 0x1U, /**< 12-hours format */ -} rtc_hour_format_t; - -/** - * @brief Output mode - */ -typedef enum { - RTC_OUTPUT_DISABLE = 0x0U, /**< Disable output */ - RTC_OUTPUT_ALARM_A = 0x1U, /**< Output alarm_a signal */ - RTC_OUTPUT_ALARM_B = 0x2U, /**< Output alarm_b signal */ - RTC_OUTPUT_WAKEUP = 0x3U, /**< Output wakeup signal */ -} rtc_output_select_t; - -/** - * @brief Output polarity - */ -typedef enum { - RTC_OUTPUT_POLARITY_HIGH = 0x0U, /**< Polarity is high */ - RTC_OUTPUT_POLARITY_LOW = 0x1U, /**< Polarity is low */ -} rtc_output_polarity_t; - -/** - * @brief Initialization structure - */ -typedef struct { - rtc_hour_format_t hour_format; /**< Hours format */ - uint32_t asynch_pre_div; /**< Asynchronous predivider value */ - uint32_t synch_pre_div; /**< Synchronous predivider value */ - rtc_output_select_t output; /**< Output signal type */ - rtc_output_polarity_t output_polarity; /**< Output polarity */ -} rtc_init_t; - -/** - * @brief Source select - */ -typedef enum { - RTC_SOURCE_LOSC = 0x0U, /**< LOSC */ - RTC_SOURCE_LRC = 0x1U, /**< LRC */ - RTC_SOURCE_HRC_DIV_1M = 0x2U, /**< HRC divide to 1MHz */ - RTC_SOURCE_HOSC_DIV_1M = 0x3U, /**< HOSC divide to 1MHz */ -} rtc_source_sel_t; - -/** - * @brief Time structure - */ -typedef struct { - uint8_t hour; /**< Hours */ - uint8_t minute; /**< Minutes */ - uint8_t second; /**< Seconds */ - uint16_t sub_sec; /**< Sub-seconds */ -} rtc_time_t; - -/** - * @brief Date structure - */ -typedef struct { - uint8_t week; /**< Weeks */ - uint8_t day; /**< days */ - uint8_t month; /**< months */ - uint8_t year; /**< years */ -} rtc_date_t; - -/** - * @brief Data format - */ -typedef enum { - RTC_FORMAT_DEC = 0U, /**< DEC format */ - RTC_FORMAT_BCD = 1U, /**< BCD format */ -} rtc_format_t; - -/** - * @brief Index of alarm - */ -typedef enum { - RTC_ALARM_A = 0x0U, /**< Alarm-A */ - RTC_ALARM_B = 0x1U, /**< Alarm-B */ -} rtc_alarm_idx_t; - -/** - * @brief Alarm mask - */ -typedef enum { - RTC_ALARM_MASK_NONE = 0x0U, /**< Mask is disable */ - RTC_ALARM_MASK_WEEK_DAY = (1U << 30), /**< Mask week or day */ - RTC_ALARM_MASK_HOUR = (1U << 23), /**< Mask hour */ - RTC_ALARM_MASK_MINUTE = (1U << 15), /**< Mask minute */ - RTC_ALARM_MASK_SECOND = (1U << 7), /**< Mask second */ - RTC_ALARM_MASK_ALL = 0x40808080U, /**< Mask all */ -} rtc_alarm_mask_t; - -/** - * @brief Alarm sub-second mask - */ -typedef enum { - RTC_ALARM_SS_MASK_NONE = 0xFU, /**< Mask is disable */ - RTC_ALARM_SS_MASK_14_1 = 0x1U, /**< Mask bit(1-14) */ - RTC_ALARM_SS_MASK_14_2 = 0x2U, /**< Mask bit(2-14) */ - RTC_ALARM_SS_MASK_14_3 = 0x3U, /**< Mask bit(3-14) */ - RTC_ALARM_SS_MASK_14_4 = 0x4U, /**< Mask bit(4-14) */ - RTC_ALARM_SS_MASK_14_5 = 0x5U, /**< Mask bit(5-14) */ - RTC_ALARM_SS_MASK_14_6 = 0x6U, /**< Mask bit(6-14) */ - RTC_ALARM_SS_MASK_14_7 = 0x7U, /**< Mask bit(7-14) */ - RTC_ALARM_SS_MASK_14_8 = 0x8U, /**< Mask bit(8-14) */ - RTC_ALARM_SS_MASK_14_9 = 0x9U, /**< Mask bit(9-14) */ - RTC_ALARM_SS_MASK_14_10 = 0xAU, /**< Mask bit(10-14) */ - RTC_ALARM_SS_MASK_14_11 = 0xBU, /**< Mask bit(11-14) */ - RTC_ALARM_SS_MASK_14_12 = 0xCU, /**< Mask bit(12-14) */ - RTC_ALARM_SS_MASK_14_13 = 0xDU, /**< Mask bit(13-14) */ - RTC_ALARM_SS_MASK_14 = 0xEU, /**< Mask bit14 */ - RTC_ALARM_SS_MASK_ALL = 0x0U, /**< Mask bit(0-14) */ -} rtc_sub_second_mask_t; - -/** - * @brief Alarm select week or day */ -typedef enum { - RTC_SELECT_DAY = 0x0U, /**< Alarm select day */ - RTC_SELECT_WEEK = 0x1U, /**< Alarm select week */ -} rtc_week_day_sel_t; - -/** - * @brief Alarm structure - */ -typedef struct { - rtc_alarm_idx_t idx; /**< Index of alarm */ - rtc_time_t time; /**< Time structure */ - uint32_t mask; /**< Alarm mask */ - rtc_sub_second_mask_t ss_mask; /**< Alarm sub-second mask */ - rtc_week_day_sel_t sel; /**< Select week or day */ - - union { - uint8_t week; /**< Alarm select week */ - uint8_t day; /**< Alarm select day */ - }; -} rtc_alarm_t; - -/** - * @brief Time stamp signel select - */ -typedef enum { - RTC_TS_SIGNAL_SEL_TAMPER0 = 0U, /**< Select tamper0 */ - RTC_TS_SIGNAL_SEL_TAMPER1 = 1U, /**< Select tamper1 */ -} rtc_ts_signal_sel_t; - -/** - * @brief Time stamp trigger style - */ -typedef enum { - RTC_TS_RISING_EDGE = 0U, /**< Rising edge */ - RTC_TS_FALLING_EDGE = 1U, /**< Falling edge */ -} rtc_ts_trigger_style_t; - -/** - * @brief Index of tamper - */ -typedef enum { - RTC_TAMPER_0 = 0U, /**< Tamper0 */ - RTC_TAMPER_1 = 1U, /**< Tamper1 */ -} rtc_tamper_idx_t; - -/** - * @brief Tamper trigger type - */ -typedef enum { - RTC_TAMPER_TRIGGER_LOW = 0U, /**< High trigger */ - RTC_TAMPER_TRIGGER_HIGH = 1U, /**< Low trigger */ -} rtc_tamper_trigger_t; - -/** - * @brief Tamper sampling frequency - */ -typedef enum { - RTC_TAMPER_SAMPLING_FREQ_32768 = 0U, /**< RTCCLK / 32768 */ - RTC_TAMPER_SAMPLING_FREQ_16384 = 1U, /**< RTCCLK / 16384 */ - RTC_TAMPER_SAMPLING_FREQ_8192 = 2U, /**< RTCCLK / 8192 */ - RTC_TAMPER_SAMPLING_FREQ_4096 = 3U, /**< RTCCLK / 4096 */ - RTC_TAMPER_SAMPLING_FREQ_2048 = 4U, /**< RTCCLK / 2048 */ - RTC_TAMPER_SAMPLING_FREQ_1024 = 5U, /**< RTCCLK / 1024 */ - RTC_TAMPER_SAMPLING_FREQ_512 = 6U, /**< RTCCLK / 512 */ - RTC_TAMPER_SAMPLING_FREQ_256 = 7U, /**< RTCCLK / 256 */ -} rtc_tamper_sampling_freq_t; - -/** - * @brief Tamper filter time - */ -typedef enum { - RTC_TAMPER_DURATION_1 = 0U, /**< Duration 1 sampling */ - RTC_TAMPER_DURATION_2 = 1U, /**< Duration 2 sampling */ - RTC_TAMPER_DURATION_4 = 2U, /**< Duration 4 sampling */ - RTC_TAMPER_DURATION_8 = 3U, /**< Duration 8 sampling */ -} rtc_tamper_duration_t; - -/** - * @brief Tamper structure - */ -typedef struct { - rtc_tamper_idx_t idx; /**< Index of tamper */ - rtc_tamper_trigger_t trig; /**< Trigger type */ - rtc_tamper_sampling_freq_t freq; /**< Sampling frequency */ - rtc_tamper_duration_t dur; /**< Filter time */ - type_func_t ts; /**< Enable/Disable trigger time stamp event */ -} rtc_tamper_t; - -/** - * @brief Wake-up clock - */ -typedef enum { - RTC_WAKEUP_CLOCK_DIV_16 = 0U, /**< RTCCLK / 16 */ - RTC_WAKEUP_CLOCK_DIV_8 = 1U, /**< RTCCLK / 8 */ - RTC_WAKEUP_CLOCK_DIV_4 = 2U, /**< RTCCLK / 4 */ - RTC_WAKEUP_CLOCK_DIV_2 = 3U, /**< RTCCLK / 2 */ - RTC_WAKEUP_CLOCK_1HZ = 4U, /**< 1Hz */ - RTC_WAKEUP_CLOCK_1HZ_PULS = 6U, /**< 1Hz and WUT + 65536 */ -} rtc_wakeup_clock_t; - -/** - * @brief RTC clock output type - */ -typedef enum { - RTC_CLOCK_OUTPUT_32768 = 0U, /**< 32768Hz */ - RTC_CLOCK_OUTPUT_1024 = 1U, /**< 1024Hz */ - RTC_CLOCK_OUTPUT_32 = 2U, /**< 32Hz */ - RTC_CLOCK_OUTPUT_1 = 3U, /**< 1Hz */ - RTC_CLOCK_OUTPUT_CAL_1 = 4U, /**< 1Hz after calibration */ - RTC_CLOCK_OUTPUT_EXA_1 = 5U, /**< Exact 1Hz */ -} rtc_clock_output_t; - -/** - * @ Calibration frequency - */ -typedef enum { - RTC_CALI_FREQ_10_SEC = 0U, /**< Calibrate every 10 seconds */ - RTC_CALI_FREQ_20_SEC = 1U, /**< Calibrate every 20 seconds */ - RTC_CALI_FREQ_1_MIN = 2U, /**< Calibrate every 1 minute */ - RTC_CALI_FREQ_2_MIN = 3U, /**< Calibrate every 2 minutes */ - RTC_CALI_FREQ_5_MIN = 4U, /**< Calibrate every 5 minutes */ - RTC_CALI_FREQ_10_MIN = 5U, /**< Calibrate every 10 minutes */ - RTC_CALI_FREQ_20_MIN = 6U, /**< Calibrate every 20 minutes */ - RTC_CALI_FREQ_1_SEC = 7U, /**< Calibrate every 1 second */ -} rtc_cali_freq_t; - -/** - * @brief Temperature compensate type - */ -typedef enum { - RTC_CALI_TC_NONE = 0U, /**< Temperature compensate disable */ - RTC_CALI_TC_AUTO_BY_HW = 1U, /**< Temperature compensate by hardware */ - RTC_CALI_TC_AUTO_BY_SF = 2U, /**< Temperature compensate by software */ - RTC_CALI_TC_AUTO_BY_HW_SF = 3U, /**< Temperature compensate by hardware, trigger by software */ -} rtc_cali_tc_t; - -/** - * @ Calculate frequency - */ -typedef enum { - RTC_CALI_CALC_FREQ_10_SEC = 0U, /**< Calculate every 10 seconds */ - RTC_CALI_CALC_FREQ_20_SEC = 1U, /**< Calculate every 20 seconds */ - RTC_CALI_CALC_FREQ_1_MIN = 2U, /**< Calculate every 1 minute */ - RTC_CALI_CALC_FREQ_2_MIN = 3U, /**< Calculate every 2 minutes */ - RTC_CALI_CALC_FREQ_5_MIN = 4U, /**< Calculate every 5 minutes */ - RTC_CALI_CALC_FREQ_10_MIN = 5U, /**< Calculate every 10 minutes */ - RTC_CALI_CALC_FREQ_20_MIN = 6U, /**< Calculate every 20 minutes */ - RTC_CALI_CALC_FREQ_1_HOUR = 7U, /**< Calculate every 1 hour */ -} rtc_cali_calc_freq_t; - -/** - * @brief Calibration algorithm - */ -typedef enum { - RTC_CALI_CALC_4 = 0U, /**< 4-polynomial */ - RTC_CALI_CALC_2 = 1U, /**< 2-parabola */ -} rtc_cali_calc_t; - -/** - * @brief Calibration structure - */ -typedef struct { - rtc_cali_freq_t cali_freq; /**< calibrate frequency */ - rtc_cali_tc_t tc; /**< Temperature compensate type */ - rtc_cali_calc_freq_t calc_freq; /**< Calculate frequency */ - rtc_cali_calc_t calc; /**< algorithm */ - type_func_t acc; /**< Enable/Disable decimal accumulate */ -} rtc_cali_t; - -/** - * @brief Interrupt type - */ -typedef enum { - RTC_IT_SEC = (1U << 0), /**< Second */ - RTC_IT_MIN = (1U << 1), /**< Minute */ - RTC_IT_HR = (1U << 2), /**< Hour */ - RTC_IT_DAY = (1U << 3), /**< Day */ - RTC_IT_MON = (1U << 4), /**< Month */ - RTC_IT_YR = (1U << 5), /**< Year */ - RTC_IT_ALMA = (1U << 8), /**< Alarm-A */ - RTC_IT_ALMB = (1U << 9), /**< Alarm-B */ - RTC_IT_TS = (1U << 10), /**< Time stamp */ - RTC_IT_TSOV = (1U << 11), /**< Time stamp overflow */ - RTC_IT_TP0 = (1U << 12), /**< Tamper-0 */ - RTC_IT_TP1 = (1U << 13), /**< Tamper-1 */ - RTC_IT_RSC = (1U << 16), /**< Synchronous complete */ - RTC_IT_SFC = (1U << 17), /**< Shift complete */ - RTC_IT_WU = (1U << 18), /**< Wake-up */ - RTC_IT_TCC = (1U << 24), /**< Temperature compensate complete */ - RTC_IT_TCE = (1U << 25), /**< Temperature compensate error */ -} rtc_it_t; - -/** - * @brief Interrupt flag - */ -typedef enum { - RTC_IF_SEC = (1U << 0), /**< Second */ - RTC_IF_MIN = (1U << 1), /**< Minute */ - RTC_IF_HR = (1U << 2), /**< Hour */ - RTC_IF_DAY = (1U << 3), /**< Day */ - RTC_IF_MON = (1U << 4), /**< Month */ - RTC_IF_YR = (1U << 5), /**< Year */ - RTC_IF_ALMA = (1U << 8), /**< Alarm-A */ - RTC_IF_ALMB = (1U << 9), /**< Alarm-B */ - RTC_IF_TS = (1U << 10), /**< Time stamp */ - RTC_IF_TSOV = (1U << 11), /**< Time stamp overflow */ - RTC_IF_TP0 = (1U << 12), /**< Tamper-0 */ - RTC_IF_TP1 = (1U << 13), /**< Tamper-1 */ - RTC_IF_RSC = (1U << 16), /**< Synchronous complete */ - RTC_IF_SFC = (1U << 17), /**< Shift complete */ - RTC_IF_WU = (1U << 18), /**< Wake-up */ - RTC_IF_TCC = (1U << 24), /**< Temperature compensate complete */ - RTC_IF_TCE = (1U << 25), /**< Temperature compensate error */ -} rtc_flag_t; -/** - * @} - */ - -/** @defgroup RTC_Public_Macro RTC Public Macros - * @{ - */ -#define RTC_UNLOCK() (WRITE_REG(RTC->WPR, 0x55AAAA55U)) -#define RTC_LOCK() (WRITE_REG(RTC->WPR, 0x0U)) -#define RTC_BY_PASS_ENABLE() \ -do { \ - RTC_UNLOCK(); \ - SET_BIT(RTC->CON, RTC_CON_SHDBP_MSK); \ - RTC_LOCK(); \ -} while (0) -#define RTC_BY_PASS_DISABLE() \ -do { \ - RTC_UNLOCK(); \ - CLEAR_BIT(RTC->CON, RTC_CON_SHDBP_MSK); \ - RTC_LOCK(); \ -} while (0) -#define RTC_SUMMER_TIME_ENABLE() \ -do { \ - RTC_UNLOCK(); \ - SET_BIT(RTC->CON, RTC_CON_ADD1H_MSK); \ - RTC_LOCK(); \ -} while (0) -#define RTC_SUMMER_TIME_DISABLE() \ -do { \ - RTC_UNLOCK(); \ - CLEAR_BIT(RTC->CON, RTC_CON_ADD1H_MSK); \ - RTC_LOCK(); \ -} while (0) -#define RTC_WINTER_TIME_ENABLE() \ -do { \ - RTC_UNLOCK(); \ - SET_BIT(RTC->CON, RTC_CON_SUB1H_MSK); \ - RTC_LOCK(); \ -} while (0) -#define RTC_WINTER_TIME_DISABLE() \ -do { \ - RTC_UNLOCK(); \ - CLEAR_BIT(RTC->CON, RTC_CON_SUB1H_MSK); \ - RTC_LOCK(); \ -} while (0) -/** - * @} - */ - -/** @defgroup CAN_Private_Macros CAN Private Macros - * @{ - */ -#define RTC_CALI_UNLOCK() (WRITE_REG(RTC->CALWPR, 0x699655AAU)) -#define RTC_CALI_LOCK() (WRITE_REG(RTC->CALWPR, 0x0U)) -#define ALARM_MASK_ALL 0x40808080U -#define RTC_TIMEOUT_VALUE 100U - -#define IS_SHIFT_SUB_SS(x) ((x) < (1U << 15)) -#define IS_RTC_HOUR_FORMAT(x) (((x) == RTC_HOUR_FORMAT_24) || \ - ((x) == RTC_HOUR_FORMAT_12)) -#define IS_RTC_OUTPUT_SEL(x) (((x) == RTC_OUTPUT_DISABLE) || \ - ((x) == RTC_OUTPUT_ALARM_A) || \ - ((x) == RTC_OUTPUT_ALARM_B) || \ - ((x) == RTC_OUTPUT_WAKEUP)) -#define IS_RTC_OUTPUT_POLARITY(x) (((x) == RTC_OUTPUT_POLARITY_HIGH) || \ - ((x) == RTC_OUTPUT_POLARITY_LOW)) -#define IS_RTC_SOURCE_SEL(x) (((x) == RTC_SOURCE_LOSC) || \ - ((x) == RTC_SOURCE_LRC) || \ - ((x) == RTC_SOURCE_HRC_DIV_1M ) || \ - ((x) == RTC_SOURCE_HOSC_DIV_1M)) -#define IS_RTC_ALARM(x) (((x) == RTC_ALARM_A) || \ - ((x) == RTC_ALARM_B)) -#define IS_RTC_ALARM_SEL(x) (((x) == RTC_SELECT_DAY) || \ - ((x) == RTC_SELECT_WEEK)) -#define IS_RTC_ALARM_MASK(x) (((x) == RTC_ALARM_MASK_NONE) || \ - ((x) == RTC_ALARM_MASK_WEEK_DAY) || \ - ((x) == RTC_ALARM_MASK_HOUR) || \ - ((x) == RTC_ALARM_MASK_MINUTE) || \ - ((x) == RTC_ALARM_MASK_SECOND) || \ - ((x) == RTC_ALARM_MASK_ALL)) -#define IS_RTC_ALARM_SS_MASK(x) (((x) == RTC_ALARM_SS_MASK_NONE) || \ - ((x) == RTC_ALARM_SS_MASK_14_1) || \ - ((x) == RTC_ALARM_SS_MASK_14_2) || \ - ((x) == RTC_ALARM_SS_MASK_14_3) || \ - ((x) == RTC_ALARM_SS_MASK_14_4) || \ - ((x) == RTC_ALARM_SS_MASK_14_5) || \ - ((x) == RTC_ALARM_SS_MASK_14_6) || \ - ((x) == RTC_ALARM_SS_MASK_14_7) || \ - ((x) == RTC_ALARM_SS_MASK_14_8) || \ - ((x) == RTC_ALARM_SS_MASK_14_9) || \ - ((x) == RTC_ALARM_SS_MASK_14_10) || \ - ((x) == RTC_ALARM_SS_MASK_14_11) || \ - ((x) == RTC_ALARM_SS_MASK_14_12) || \ - ((x) == RTC_ALARM_SS_MASK_14_13) || \ - ((x) == RTC_ALARM_SS_MASK_14) || \ - ((x) == RTC_ALARM_SS_MASK_ALL)) -#define IS_RTC_TS_SIGNAL(x) (((x) == RTC_TS_SIGNAL_SEL_TAMPER0) || \ - ((x) == RTC_TS_SIGNAL_SEL_TAMPER1)) -#define IS_RTC_TS_STYLE(x) (((x) == RTC_TS_RISING_EDGE) || \ - ((x) == RTC_TS_FALLING_EDGE)) -#define IS_RTC_FORMAT(x) (((x) == RTC_FORMAT_DEC) || \ - ((x) == RTC_FORMAT_BCD)) -#define IS_RTC_TAMPER(x) (((x) == RTC_TAMPER_0) || \ - ((x) == RTC_TAMPER_1)) -#define IS_RTC_TAMPER_TRIGGER(x) (((x) == RTC_TAMPER_TRIGGER_LOW) || \ - ((x) == RTC_TAMPER_TRIGGER_HIGH)) -#define IS_RTC_TAMPER_SAMPLING_FREQ(x) (((x) == RTC_TAMPER_SAMPLING_FREQ_32768) || \ - ((x) == RTC_TAMPER_SAMPLING_FREQ_16384) || \ - ((x) == RTC_TAMPER_SAMPLING_FREQ_8192) || \ - ((x) == RTC_TAMPER_SAMPLING_FREQ_4096) || \ - ((x) == RTC_TAMPER_SAMPLING_FREQ_2048) || \ - ((x) == RTC_TAMPER_SAMPLING_FREQ_1024) || \ - ((x) == RTC_TAMPER_SAMPLING_FREQ_512) || \ - ((x) == RTC_TAMPER_SAMPLING_FREQ_256)) -#define IS_RTC_TAMPER_DURATION(x) (((x) == RTC_TAMPER_DURATION_1) || \ - ((x) == RTC_TAMPER_DURATION_2) || \ - ((x) == RTC_TAMPER_DURATION_4) || \ - ((x) == RTC_TAMPER_DURATION_8)) -#define IS_RTC_WAKEUP_CLOCK(x) (((x) == RTC_WAKEUP_CLOCK_DIV_16) || \ - ((x) == RTC_WAKEUP_CLOCK_DIV_8) || \ - ((x) == RTC_WAKEUP_CLOCK_DIV_4) || \ - ((x) == RTC_WAKEUP_CLOCK_DIV_2) || \ - ((x) == RTC_WAKEUP_CLOCK_1HZ) || \ - ((x) == RTC_WAKEUP_CLOCK_1HZ_PULS)) -#define IS_RTC_CLOCK_OUTPUT(x) (((x) == RTC_CLOCK_OUTPUT_32768) || \ - ((x) == RTC_CLOCK_OUTPUT_1024) || \ - ((x) == RTC_CLOCK_OUTPUT_32) || \ - ((x) == RTC_CLOCK_OUTPUT_1) || \ - ((x) == RTC_CLOCK_OUTPUT_CAL_1) || \ - ((x) == RTC_CLOCK_OUTPUT_EXA_1)) -#define IS_RTC_CALI_FREQ(x) (((x) == RTC_CALI_FREQ_10_SEC) || \ - ((x) == RTC_CALI_FREQ_20_SEC) || \ - ((x) == RTC_CALI_FREQ_1_MIN) || \ - ((x) == RTC_CALI_FREQ_2_MIN) || \ - ((x) == RTC_CALI_FREQ_5_MIN) || \ - ((x) == RTC_CALI_FREQ_10_MIN) || \ - ((x) == RTC_CALI_FREQ_20_MIN) || \ - ((x) == RTC_CALI_FREQ_1_SEC)) -#define IS_RTC_CALI_TC(x) (((x) == RTC_CALI_TC_NONE) || \ - ((x) == RTC_CALI_TC_AUTO_BY_HW) || \ - ((x) == RTC_CALI_TC_AUTO_BY_SF) || \ - ((x) == RTC_CALI_TC_AUTO_BY_HW_SF)) -#define IS_RTC_CALC_FREQ(x) (((x) == RTC_CALI_CALC_FREQ_10_SEC) || \ - ((x) == RTC_CALI_CALC_FREQ_20_SEC) || \ - ((x) == RTC_CALI_CALC_FREQ_1_MIN) || \ - ((x) == RTC_CALI_CALC_FREQ_2_MIN) || \ - ((x) == RTC_CALI_CALC_FREQ_5_MIN) || \ - ((x) == RTC_CALI_CALC_FREQ_10_MIN) || \ - ((x) == RTC_CALI_CALC_FREQ_20_MIN) || \ - ((x) == RTC_CALI_CALC_FREQ_1_HOUR)) -#define IS_RTC_CALI_CALC(x) (((x) == RTC_CALI_CALC_4) || \ - ((x) == RTC_CALI_CALC_2)) -#define IS_RTC_IT(x) (((x) == RTC_IT_SEC) || \ - ((x) == RTC_IT_MIN) || \ - ((x) == RTC_IT_HR) || \ - ((x) == RTC_IT_DAY) || \ - ((x) == RTC_IT_MON) || \ - ((x) == RTC_IT_YR) || \ - ((x) == RTC_IT_ALMA) || \ - ((x) == RTC_IT_ALMB) || \ - ((x) == RTC_IT_TS) || \ - ((x) == RTC_IT_TSOV) || \ - ((x) == RTC_IT_TP0) || \ - ((x) == RTC_IT_TP1) || \ - ((x) == RTC_IT_RSC) || \ - ((x) == RTC_IT_SFC) || \ - ((x) == RTC_IT_WU) || \ - ((x) == RTC_IT_TCC) || \ - ((x) == RTC_IT_TCE)) -#define IS_RTC_IF(x) (((x) == RTC_IF_SEC) || \ - ((x) == RTC_IF_MIN) || \ - ((x) == RTC_IF_HR) || \ - ((x) == RTC_IF_DAY) || \ - ((x) == RTC_IF_MON) || \ - ((x) == RTC_IF_YR) || \ - ((x) == RTC_IF_ALMA) || \ - ((x) == RTC_IF_ALMB) || \ - ((x) == RTC_IF_TS) || \ - ((x) == RTC_IF_TSOV) || \ - ((x) == RTC_IF_TP0) || \ - ((x) == RTC_IF_TP1) || \ - ((x) == RTC_IF_RSC) || \ - ((x) == RTC_IF_SFC) || \ - ((x) == RTC_IF_WU) || \ - ((x) == RTC_IF_TCC) || \ - ((x) == RTC_IF_TCE)) -#define IS_RTC_SECOND(x) ((x) < 60) -#define IS_RTC_MINUTE(x) ((x) < 60) -#define IS_RTC_HOUR(x) ((x) < 24) -#define IS_RTC_DAY(x) (((x) > 0) && ((x) < 32)) -#define IS_RTC_MONTH(x) (((x) > 0) && ((x) < 13)) -#define IS_RTC_YEAR(x) ((x) < 100) -/** - * @} - */ - -/** @addtogroup RTC_Public_Functions - * @{ - */ - -/** @addtogroup RTC_Public_Functions_Group1 - * @{ - */ -/* Initialization functions */ -void ald_rtc_reset(void); -void ald_rtc_init(rtc_init_t *init); -void ald_rtc_source_select(rtc_source_sel_t sel); -/** - * @} - */ -/** @addtogroup RTC_Public_Functions_Group2 - * @{ - */ -/* Time and date operation functions */ -ald_status_t ald_rtc_set_time(rtc_time_t *time, rtc_format_t format); -ald_status_t ald_rtc_set_date(rtc_date_t *date, rtc_format_t format); -void ald_rtc_get_time(rtc_time_t *time, rtc_format_t format); -void ald_rtc_get_date(rtc_date_t *date, rtc_format_t format); -int32_t ald_rtc_get_date_time(rtc_date_t *date, rtc_time_t *time, rtc_format_t format); -/** - * @} - */ -/** @addtogroup RTC_Public_Functions_Group3 - * @{ - */ -/* Alarm functions */ -void ald_rtc_set_alarm(rtc_alarm_t *alarm, rtc_format_t format); -void ald_rtc_get_alarm(rtc_alarm_t *alarm, rtc_format_t format); -/** - * @} - */ -/** @addtogroup RTC_Public_Functions_Group4 - * @{ - */ -/* Time stamp functions */ -void ald_rtc_set_time_stamp(rtc_ts_signal_sel_t sel, rtc_ts_trigger_style_t style); -void ald_rtc_cancel_time_stamp(void); -void ald_rtc_get_time_stamp(rtc_time_t *ts_time, rtc_date_t *ts_date, rtc_format_t format); -/** - * @} - */ -/** @addtogroup RTC_Public_Functions_Group5 - * @{ - */ -/* Tamper functions */ -void ald_rtc_set_tamper(rtc_tamper_t *tamper); -void ald_rtc_cancel_tamper(rtc_tamper_idx_t idx); -/** - * @} - */ -/** @addtogroup RTC_Public_Functions_Group6 - * @{ - */ -/* Wakeup functions */ -void ald_rtc_set_wakeup(rtc_wakeup_clock_t clock, uint16_t value); -void ald_rtc_cancel_wakeup(void); -uint16_t ald_rtc_get_wakeup_timer_value(void); -/** - * @} - */ -/** @addtogroup RTC_Public_Functions_Group7 - * @{ - */ -/* Clock output functions */ -ald_status_t ald_rtc_set_clock_output(rtc_clock_output_t clock); -void ald_rtc_cancel_clock_output(void); -/** - * @} - */ -/** @addtogroup RTC_Public_Functions_Group8 - * @{ - */ -/* Control functions */ -void ald_rtc_interrupt_config(rtc_it_t it, type_func_t state); -void ald_rtc_alarm_cmd(rtc_alarm_idx_t idx, type_func_t state); -ald_status_t ald_rtc_set_shift(type_func_t add_1s, uint16_t sub_ss); -void ald_rtc_set_cali(rtc_cali_t *config); -void ald_rtc_cancel_cali(void); -ald_status_t ald_rtc_get_cali_status(void); -void ald_rtc_write_temp(uint16_t temp); -it_status_t ald_rtc_get_it_status(rtc_it_t it); -flag_status_t ald_rtc_get_flag_status(rtc_flag_t flag); -void ald_rtc_clear_flag_status(rtc_flag_t flag); -/** - * @} - */ -/** - * @} - */ -/** - * @} - */ -/** - * @} - */ -#ifdef __cplusplus -} -#endif -#endif diff --git a/bsp/essemi/es32f0334/libraries/ES32F033x_ALD_StdPeriph_Driver/Include/ald_smartcard.h b/bsp/essemi/es32f0334/libraries/ES32F033x_ALD_StdPeriph_Driver/Include/ald_smartcard.h deleted file mode 100644 index 74401fecc1..0000000000 --- a/bsp/essemi/es32f0334/libraries/ES32F033x_ALD_StdPeriph_Driver/Include/ald_smartcard.h +++ /dev/null @@ -1,274 +0,0 @@ -/** - ********************************************************************************* - * - * @file ald_usart.h - * @brief Header file of SMARTCARD driver module. - * - * @version V1.0 - * @date 25 Apr 2017 - * @author AE Team - * @note - * - * Copyright (C) Shanghai Eastsoft Microelectronics Co. Ltd. All rights reserved. - * - ********************************************************************************* - */ - -#ifndef __ALD_SMARTCARD_H__ -#define __ALD_SMARTCARD_H__ - -#ifdef __cplusplus - extern "C" { -#endif - -#include "utils.h" -#include "ald_dma.h" -#include "ald_usart.h" - - -/** @addtogroup ES32FXXX_ALD - * @{ - */ - -/** @addtogroup SMARTCARD - * @{ - */ - -/** @defgroup SMARTCARD_Public_Constants SMARTCARD Public constants - * @{ - */ - -/** - * @brief SMARTCARD error codes - */ -typedef enum { - SMARTCARD_ERROR_NONE = ((uint32_t)0x00U), /**< No error */ - SMARTCARD_ERROR_PE = ((uint32_t)0x01U), /**< Parity error */ - SMARTCARD_ERROR_NE = ((uint32_t)0x02U), /**< Noise error */ - SMARTCARD_ERROR_FE = ((uint32_t)0x04U), /**< frame error */ - SMARTCARD_ERROR_ORE = ((uint32_t)0x08U), /**< Overrun error */ - SMARTCARD_ERROR_DMA = ((uint32_t)0x10U), /**< DMA transfer error */ -} smartcard_error_t; - -/** - * @brief SMARTCARD Prescaler - */ -typedef enum { - SMARTCARD_PRESCALER_SYSCLK_DIV2 = ((uint32_t)0x1U), /**< SYSCLK divided by 2 */ - SMARTCARD_PRESCALER_SYSCLK_DIV4 = ((uint32_t)0x2U), /**< SYSCLK divided by 4 */ - SMARTCARD_PRESCALER_SYSCLK_DIV6 = ((uint32_t)0x3U), /**< SYSCLK divided by 6 */ - SMARTCARD_PRESCALER_SYSCLK_DIV8 = ((uint32_t)0x4U), /**< SYSCLK divided by 8 */ - SMARTCARD_PRESCALER_SYSCLK_DIV10 = ((uint32_t)0x5U), /**< SYSCLK divided by 10 */ - SMARTCARD_PRESCALER_SYSCLK_DIV12 = ((uint32_t)0x6U), /**< SYSCLK divided by 12 */ - SMARTCARD_PRESCALER_SYSCLK_DIV14 = ((uint32_t)0x7U), /**< SYSCLK divided by 14 */ - SMARTCARD_PRESCALER_SYSCLK_DIV16 = ((uint32_t)0x8U), /**< SYSCLK divided by 16 */ - SMARTCARD_PRESCALER_SYSCLK_DIV18 = ((uint32_t)0x9U), /**< SYSCLK divided by 18 */ - SMARTCARD_PRESCALER_SYSCLK_DIV20 = ((uint32_t)0xAU), /**< SYSCLK divided by 20 */ - SMARTCARD_PRESCALER_SYSCLK_DIV22 = ((uint32_t)0xBU), /**< SYSCLK divided by 22 */ - SMARTCARD_PRESCALER_SYSCLK_DIV24 = ((uint32_t)0xCU), /**< SYSCLK divided by 24 */ - SMARTCARD_PRESCALER_SYSCLK_DIV26 = ((uint32_t)0xDU), /**< SYSCLK divided by 26 */ - SMARTCARD_PRESCALER_SYSCLK_DIV28 = ((uint32_t)0xEU), /**< SYSCLK divided by 28 */ - SMARTCARD_PRESCALER_SYSCLK_DIV30 = ((uint32_t)0xFU), /**< SYSCLK divided by 30 */ - SMARTCARD_PRESCALER_SYSCLK_DIV32 = ((uint32_t)0x10U), /**< SYSCLK divided by 32 */ - SMARTCARD_PRESCALER_SYSCLK_DIV34 = ((uint32_t)0x11U), /**< SYSCLK divided by 34 */ - SMARTCARD_PRESCALER_SYSCLK_DIV36 = ((uint32_t)0x12U), /**< SYSCLK divided by 36 */ - SMARTCARD_PRESCALER_SYSCLK_DIV38 = ((uint32_t)0x13U), /**< SYSCLK divided by 38 */ - SMARTCARD_PRESCALER_SYSCLK_DIV40 = ((uint32_t)0x14U), /**< SYSCLK divided by 40 */ - SMARTCARD_PRESCALER_SYSCLK_DIV42 = ((uint32_t)0x15U), /**< SYSCLK divided by 42 */ - SMARTCARD_PRESCALER_SYSCLK_DIV44 = ((uint32_t)0x16U), /**< SYSCLK divided by 44 */ - SMARTCARD_PRESCALER_SYSCLK_DIV46 = ((uint32_t)0x17U), /**< SYSCLK divided by 46 */ - SMARTCARD_PRESCALER_SYSCLK_DIV48 = ((uint32_t)0x18U), /**< SYSCLK divided by 48 */ - SMARTCARD_PRESCALER_SYSCLK_DIV50 = ((uint32_t)0x19U), /**< SYSCLK divided by 50 */ - SMARTCARD_PRESCALER_SYSCLK_DIV52 = ((uint32_t)0x1AU), /**< SYSCLK divided by 52 */ - SMARTCARD_PRESCALER_SYSCLK_DIV54 = ((uint32_t)0x1BU), /**< SYSCLK divided by 54 */ - SMARTCARD_PRESCALER_SYSCLK_DIV56 = ((uint32_t)0x1CU), /**< SYSCLK divided by 56 */ - SMARTCARD_PRESCALER_SYSCLK_DIV58 = ((uint32_t)0x1DU), /**< SYSCLK divided by 58 */ - SMARTCARD_PRESCALER_SYSCLK_DIV60 = ((uint32_t)0x1EU), /**< SYSCLK divided by 60 */ - SMARTCARD_PRESCALER_SYSCLK_DIV62 = ((uint32_t)0x1FU), /**< SYSCLK divided by 62 */ -} smartcard_prescaler_t; - -/** - * @} - */ - -/** @defgroup SMARTCARD_Public_Types SMARTCARD Public Types - * @{ - */ - -/** - * @brief SMARTCARD Init Structure definition - */ -typedef struct { - uint32_t baud; /**< This member configures the SmartCard communication baud rate. */ - usart_word_length_t word_length;/**< Specifies the number of data bits transmitted or received in a frame. */ - usart_stop_bits_t stop_bits; /**< Specifies the number of stop bits transmitted. */ - usart_parity_t parity; /**< Specifies the parity mode. - @note When parity is enabled, the computed parity is inserted - at the MSB position of the transmitted data (9th bit when - the word length is set to 9 data bits; 8th bit when the - word length is set to 8 data bits).*/ - usart_mode_t mode; /**< Specifies whether the Receive or Transmit mode is enabled or disabled. */ - usart_cpol_t polarity; /**< Specifies the steady state of the serial clock. */ - usart_cpha_t phase; /**< Specifies the clock transition on which the bit capture is made.*/ - usart_last_bit_t last_bit; /**< Specifies whether the clock pulse corresponding to the last transmitted - data bit (MSB) has to be output on the SCLK pin in synchronous mode. - This parameter can be a value of @ref usart_last_bit_t */ - smartcard_prescaler_t prescaler;/**< Specifies the SmartCard Prescaler value used for dividing the system clock - to provide the smartcard clock. The value given in the register (5 significant bits) - is multiplied by 2 to give the division factor of the source clock frequency. */ - uint32_t guard_time; /**< Specifies the SmartCard Guard Time value in terms of number of baud clocks */ - type_func_t nack; /**< Specifies the SmartCard NACK Transmission state. */ -} smartcard_init_t; - -/** - * @brief ALD state structures definition - */ -typedef enum { - SMARTCARD_STATE_RESET = 0x00U, /**< Peripheral is not yet Initialized */ - SMARTCARD_STATE_READY = 0x01U, /**< Peripheral Initialized and ready for use */ - SMARTCARD_STATE_BUSY = 0x02U, /**< an internal process is ongoing */ - SMARTCARD_STATE_BUSY_TX = 0x11U, /**< Data Transmission process is ongoing */ - SMARTCARD_STATE_BUSY_RX = 0x21U, /**< Data Reception process is ongoing */ - SMARTCARD_STATE_BUSY_TX_RX = 0x31U, /**< Data Transmission and Reception process is ongoing */ - SMARTCARD_STATE_TIMEOUT = 0x03U, /**< Timeout state */ - SMARTCARD_STATE_ERROR = 0x04U, /**< Error */ -} smartcard_state_t; - - -/** - * @brief SMARTCARD handle structure definition - */ -typedef struct smartcard_handle_s { - USART_TypeDef *perh; /**< USART registers base address */ - smartcard_init_t init; /**< SmartCard communication parameters */ - uint8_t *tx_buf; /**< Pointer to SmartCard Tx transfer Buffer */ - uint16_t tx_size; /**< SmartCard Tx Transfer size */ - uint16_t tx_count; /**< SmartCard Tx Transfer Counter */ - uint8_t *rx_buf; /**< Pointer to SmartCard Rx transfer Buffer */ - uint16_t rx_size; /**< SmartCard Rx Transfer size */ - uint16_t rx_count; /**< SmartCard Rx Transfer Counter */ -#ifdef ALD_DMA - dma_handle_t hdmatx; /**< SmartCard Tx DMA Handle parameters */ - dma_handle_t hdmarx; /**< SmartCard Rx DMA Handle parameters */ -#endif - lock_state_t lock; /**< Locking object */ - smartcard_state_t state; /**< SmartCard communication state */ - uint32_t err_code; /**< SmartCard Error code */ - - void (*tx_cplt_cbk)(struct smartcard_handle_s *arg); /**< Tx completed callback */ - void (*rx_cplt_cbk)(struct smartcard_handle_s *arg); /**< Rx completed callback */ - void (*error_cbk)(struct smartcard_handle_s *arg); /**< error callback */ -} smartcard_handle_t; - -/** - * @} - */ - -/** @defgroup SMARTCARD_Public_Macros SMARTCARD Public Macros - * @{ - */ - -/** @defgroup SMARTCARD_Public_Macros_1 SMARTCARD handle reset - * @{ - */ -#define SMARTCARD_RESET_HANDLE_STATE(handle) ((handle)->state = SMARTCARD_STATE_RESET) -/** - * @} - */ - -/** @defgroup SMARTCARD_Public_Macros_2 SMARTCARD flush data - * @{ - */ -#define SMARTCARD_FLUSH_DRREGISTER(handle) ((handle)->perh->DATA) -/** - * @} - */ - -/** @defgroup SMARTCARD_Public_Macros_3 SMARTCARD enable - * @{ - */ -#define SMARTCARD_ENABLE(handle) (SET_BIT((handle)->perh->CON0, USART_CON0_EN_MSK)) -/** - * @} - */ - -/** @defgroup SMARTCARD_Public_Macros_4 SMARTCARD disable - * @{ - */ -#define SMARTCARD_DISABLE(handle) (CLEAR_BIT((handle)->perh->CON0, USART_CON0_EN_MSK)) -/** - * @} - */ - -/** - * @} - */ - -/** @defgroup SMARTCARD_Private_Macros SMARTCARD Private Macros - * @{ - */ - -#define IS_SMARTCARD_PRESCALER(x) (((x) >= SMARTCARD_PRESCALER_SYSCLK_DIV2) && \ - ((x) <= SMARTCARD_PRESCALER_SYSCLK_DIV62)) -/** - * @} - */ - -/** @addtogroup SMARTCARD_Public_Functions - * @{ - */ - -/** @addtogroup SMARTCARD_Public_Functions_Group1 - * @{ - */ -/* Initialization functions */ -ald_status_t ald_smartcard_init(smartcard_handle_t *hperh); -ald_status_t ald_smartcard_reset(smartcard_handle_t *hperh); -/** - * @} - */ - -/** @addtogroup SMARTCARD_Public_Functions_Group2 - * @{ - */ -/* IO operation functions */ -ald_status_t ald_smartcard_send(smartcard_handle_t *hperh, uint8_t *buf, uint16_t size, uint32_t timeout); -ald_status_t ald_smartcard_recv(smartcard_handle_t *hperh, uint8_t *buf, uint16_t size, uint32_t timeout); -ald_status_t ald_smartcard_send_by_it(smartcard_handle_t *hperh, uint8_t *buf, uint16_t size); -ald_status_t ald_smartcard_recv_by_it(smartcard_handle_t *hperh, uint8_t *buf, uint16_t size); -#ifdef ALD_DMA -ald_status_t ald_smartcard_send_by_dma(smartcard_handle_t *hperh, uint8_t *buf, uint16_t size, uint8_t channel); -ald_status_t ald_smartcard_recv_by_dma(smartcard_handle_t *hperh, uint8_t *buf, uint16_t size, uint8_t channel); -#endif -void ald_smartcard_irq_handler(smartcard_handle_t *hperh); -/** - * @} - */ - -/** @addtogroup SMARTCARD_Public_Functions_Group3 - * @{ - */ -/* Peripheral State and Errors functions functions */ -smartcard_state_t ald_smartcard_get_state(smartcard_handle_t *hperh); -uint32_t ald_smartcard_get_error(smartcard_handle_t *hperh); -/** - * @} - */ - -/** - * @} - */ - -/** - * @} - */ - -/** - * @} - */ - -#ifdef __cplusplus -} -#endif - -#endif /* __ALD_SMARTCARD_H__ */ diff --git a/bsp/essemi/es32f0334/libraries/ES32F033x_ALD_StdPeriph_Driver/Include/ald_spi.h b/bsp/essemi/es32f0334/libraries/ES32F033x_ALD_StdPeriph_Driver/Include/ald_spi.h deleted file mode 100644 index 1a7c7c7e5e..0000000000 --- a/bsp/essemi/es32f0334/libraries/ES32F033x_ALD_StdPeriph_Driver/Include/ald_spi.h +++ /dev/null @@ -1,387 +0,0 @@ -/** - ********************************************************************************* - * - * @file ald_spi.c - * @brief Header file of SPI module driver. - * - * @version V1.0 - * @date 13 Nov 2017 - * @author AE Team - * @note - * - * Copyright (C) Shanghai Eastsoft Microelectronics Co. Ltd. All rights reserved. - * - ********************************************************************************* - */ - -#ifndef __ALD_SPI_H__ -#define __ALD_SPI_H__ - -#ifdef __cplusplus - extern "C" { -#endif - -#include "utils.h" -#include "ald_dma.h" - -/** @addtogroup ES32FXXX_ALD - * @{ - */ - -/** @addtogroup SPI - * @{ - */ - -/** @defgroup SPI_Public_Types SPI Public Types - * @{ - */ - -/** - * @brief clock phase - */ -typedef enum { - SPI_CPHA_FIRST = 0U, /**< Transiting data in the first edge */ - SPI_CPHA_SECOND = 1U, /**< Transiting data in the seconde edge */ -} spi_cpha_t; - -/** - * @brief clock polarity - */ -typedef enum { - SPI_CPOL_LOW = 0U, /**< Polarity hold low when spi-bus is idle */ - SPI_CPOL_HIGH = 1U, /**< Polarity hold high when spi-bus is idle */ -} spi_cpol_t; - -/** - * @brief master selection - */ -typedef enum { - SPI_MODE_SLAVER = 0U, /**< Slave mode */ - SPI_MODE_MASTER = 1U, /**< Master mode */ -} spi_mode_t; - -/** - * @brief baud rate control - */ -typedef enum { - SPI_BAUD_2 = 0U, /**< fpclk/2 */ - SPI_BAUD_4 = 1U, /**< fpclk/4 */ - SPI_BAUD_8 = 2U, /**< fpclk/8 */ - SPI_BAUD_16 = 3U, /**< fpclk/16 */ - SPI_BAUD_32 = 4U, /**< fpclk/32 */ - SPI_BAUD_64 = 5U, /**< fpclk/64 */ - SPI_BAUD_128 = 6U, /**< fpclk/128 */ - SPI_BAUD_256 = 7U, /**< fpclk/256 */ -} spi_baud_t; - -/** - * @brief frame format - */ -typedef enum { - SPI_FIRSTBIT_MSB = 0U, /**< MSB transmitted first */ - SPI_FIRSTBIT_LSB = 1U, /**< LSB transmitted first */ -} spi_firstbit_t; - -/** - * @brief data frame format - */ -typedef enum { - SPI_DATA_SIZE_8 = 0U, /**< 8-bit data frame format is selected for transmission/reception */ - SPI_DATA_SIZE_16 = 1U, /**< 16-bit data frame format is selected for transmission/reception */ -} spi_datasize_t; - -/** - * @brief interrupt control - */ -typedef enum { - SPI_IT_ERR = (1U << 5), /**< error interrupt */ - SPI_IT_RXBNE = (1U << 6), /**< rx buffer not empty interrupt */ - SPI_IT_TXBE = (1U << 7), /**< tx buffer empty interrupt */ -} spi_it_t; - -/** - * @brief interrupt flag - */ -typedef enum { - SPI_IF_RXBNE = (1U << 0), /**< receive buffer not empty */ - SPI_IF_TXBE = (1U << 1), /**< transmit buffer empty */ - SPI_IF_CRCERR = (1U << 4), /**< crc error flag */ - SPI_IF_MODF = (1U << 5), /**< mode fault */ - SPI_IF_OVE = (1U << 6), /**< overrun flag */ - SPI_IF_BUSY = (1U << 7), /**< busy flag */ -} spi_flag_t; - -/** - * @brief SPI error status - */ -typedef enum { - SPI_ERROR_NONE = 0U, /**< none */ - SPI_ERROR_MODF = 1U, /**< mode fault */ - SPI_ERROR_CRC = 2U, /**< crc error */ - SPI_ERROR_OVE = 4U, /**< overrun error */ - SPI_ERROR_DMA = 8U, /**< dma error */ - SPI_ERROR_FLAG = 0x10U, /**< interrupt flag error */ -} spi_error_t; - - - -/** - * @brief SPI state structures definition - */ -typedef enum { - SPI_STATE_RESET = 0x00U, /**< Peripheral is not initialized */ - SPI_STATE_READY = 0x01U, /**< Peripheral Initialized and ready for use */ - SPI_STATE_BUSY = 0x02U, /**< an internal process is ongoing */ - SPI_STATE_BUSY_TX = 0x11U, /**< transmit is ongoing */ - SPI_STATE_BUSY_RX = 0x21U, /**< receive is ongoing */ - SPI_STATE_BUSY_TX_RX = 0x31U, /**< transmit and receive are ongoing */ - SPI_STATE_TIMEOUT = 0x03U, /**< Timeout state */ - SPI_STATE_ERROR = 0x04U, /**< Error */ -} spi_state_t; - -/** - * @brief SPI status definition - */ -typedef enum { - SPI_STATUS_RXBNE = (1U << 0), /**< Receive not empty status */ - SPI_STATUS_TXBE = (1U << 1), /**< Transmit empty status */ - SPI_STATUS_CRCERR = (1U << 4), /**< CRC error status */ - SPI_STATUS_MODEERR = (1U << 5), /**< Mode error status */ - SPI_STATUS_OVERR = (1U << 6), /**< Overflow status */ - SPI_STATUS_BUSY = (1U << 7), /**< Busy status */ - -} spi_status_t; - -/** - * @brief SPI direction definition - */ -typedef enum { - SPI_DIRECTION_2LINES = 0U, /**< 2 lines */ - SPI_DIRECTION_2LINES_RXONLY = 1U, /**< 2 lines only rx */ - SPI_DIRECTION_1LINE = 2U, /**< 1 line */ - SPI_DIRECTION_1LINE_RX = 3U, /**< 1 line only rx */ -} spi_direction_t; - -/** - * @brief SPI dma request definition - */ -typedef enum { - SPI_DMA_REQ_TX = 0U, /**< TX dma request */ - SPI_DMA_REQ_RX = 1U, /**< RX dma request */ -} spi_dma_req_t; - -/** - * @brief SPI TXE/RXNE status definition - */ -typedef enum { - SPI_SR_TXBE = 0U, /**< SR.TXE set */ - SPI_SR_RXBNE = 1U, /**< SR.RXNE set */ - SPI_SR_TXBE_RXBNE = 2U, /**< SR.TXE and SR.RXNE set */ -} spi_sr_status_t; - -/** - * @brief SPI init structure definition - */ -typedef struct { - spi_mode_t mode; /**< SPI mode */ - spi_direction_t dir; /**< SPI direction */ - spi_datasize_t data_size; /**< SPI data size */ - spi_baud_t baud; /**< SPI baudrate prescaler */ - spi_cpha_t phase; /**< SPI clock phase */ - spi_cpol_t polarity; /**< SPI clock polarity */ - spi_firstbit_t first_bit; /**< SPI first bit */ - type_func_t ss_en; /**< SPI ssm enable or disable */ - type_func_t crc_calc; /**< SPI crc calculation */ - uint16_t crc_poly; /**< SPI crc polynomial */ -} spi_init_t; - -/** - * @brief SPI handle structure definition - */ -typedef struct spi_handle_s { - SPI_TypeDef *perh; /**< SPI registers base address */ - spi_init_t init; /**< SPI communication parameters */ - uint8_t *tx_buf; /**< Pointer to SPI Tx transfer buffer */ - uint16_t tx_size; /**< SPI Tx transfer size */ - uint16_t tx_count; /**< SPI Tx transfer counter */ - uint8_t *rx_buf; /**< Pointer to SPI Rx transfer buffer */ - uint16_t rx_size; /**< SPI Rx Transfer size */ - uint16_t rx_count; /**< SPI Rx Transfer Counter */ -#ifdef ALD_DMA - dma_handle_t hdmatx; /**< SPI Tx DMA handle parameters */ - dma_handle_t hdmarx; /**< SPI Rx DMA handle parameters */ -#endif - lock_state_t lock; /**< Locking object */ - spi_state_t state; /**< SPI communication state */ - uint32_t err_code; /**< SPI error code */ - - void (*tx_cplt_cbk)(struct spi_handle_s *arg); /**< Tx completed callback */ - void (*rx_cplt_cbk)(struct spi_handle_s *arg); /**< Rx completed callback */ - void (*tx_rx_cplt_cbk)(struct spi_handle_s *arg); /**< Tx & Rx completed callback */ - void (*err_cbk)(struct spi_handle_s *arg); /**< error callback */ -} spi_handle_t; -/** - * @} - */ - -/** @defgroup SPI_Public_Macros SPI Public Macros - * @{ - */ -#define SPI_RESET_HANDLE_STATE(x) ((x)->state = SPI_STATE_RESET) -#define SPI_ENABLE(x) ((x)->perh->CON1 |= (1 << SPI_CON1_SPIEN_POS)) -#define SPI_DISABLE(x) ((x)->perh->CON1 &= ~(1 << SPI_CON1_SPIEN_POS)) -#define SPI_CRC_RESET(x) \ -do { \ - CLEAR_BIT((x)->perh->CON1, SPI_CON1_CRCEN_MSK); \ - SET_BIT((x)->perh->CON1, SPI_CON1_CRCEN_MSK); \ -} while (0) -#define SPI_CRCNEXT_ENABLE(x) (SET_BIT((x)->perh->CON1, SPI_CON1_NXTCRC_MSK)) -#define SPI_CRCNEXT_DISABLE(x) (CLEAR_BIT((x)->perh->CON1, SPI_CON1_NXTCRC_MSK)) -#define SPI_RXONLY_ENABLE(x) (SET_BIT((x)->perh->CON1, SPI_CON1_RXO_MSK)) -#define SPI_RXONLY_DISABLE(x) (CLEAR_BIT((x)->perh->CON1, SPI_CON1_RXO_MSK)) -#define SPI_1LINE_TX(x) (SET_BIT((x)->perh->CON1, SPI_CON1_BIDOEN_MSK)) -#define SPI_1LINE_RX(x) (CLEAR_BIT((x)->perh->CON1, SPI_CON1_BIDOEN_MSK)) -#define SPI_SSI_HIGH(x) (SET_BIT((x)->perh->CON1, SPI_CON1_SSOUT_MSK)) -#define SPI_SSI_LOW(x) (CLEAR_BIT((x)->perh->CON1, SPI_CON1_SSOUT_MSK)) -#define SPI_SSOE_ENABLE(x) (SET_BIT((x)->perh->CON2, SPI_CON2_NSSOE_MSK)) -#define SPI_SSOE_DISABLE(x) (CLEAR_BIT((x)->perh->CON2, SPI_CON2_NSSOE_MSK)) -/** - * @} - */ - -/** @defgroup SPI_Private_Macros SPI Private Macros - * @{ - */ -#if defined(ES32F065x) || defined(ES32F033x) -#define IS_SPI(x) (((x) == SPI0) || ((x) == SPI1)) -#endif -#if defined(ES32F093x) -#define IS_SPI(x) (((x) == SPI0) || ((x) == SPI1) || ((x) == SPI2)) -#endif -#define IS_SPI_CPHA(x) (((x) == SPI_CPHA_FIRST) || \ - ((x) == SPI_CPHA_SECOND)) -#define IS_SPI_CPOL(x) (((x) == SPI_CPOL_LOW) || \ - ((x) == SPI_CPOL_HIGH)) -#define IS_SPI_MODE(x) (((x) == SPI_MODE_SLAVER) || \ - ((x) == SPI_MODE_MASTER)) -#define IS_SPI_BAUD(x) (((x) == SPI_BAUD_2) || \ - ((x) == SPI_BAUD_4) || \ - ((x) == SPI_BAUD_8) || \ - ((x) == SPI_BAUD_16) || \ - ((x) == SPI_BAUD_32) || \ - ((x) == SPI_BAUD_64) || \ - ((x) == SPI_BAUD_128) || \ - ((x) == SPI_BAUD_256)) -#define IS_SPI_DATASIZE(x) (((x) == SPI_DATA_SIZE_8) || \ - ((x) == SPI_DATA_SIZE_16)) -#define IS_SPI_FIRSTBIT(x) (((x) == SPI_FIRSTBIT_MSB) || \ - ((x) == SPI_FIRSTBIT_LSB)) -#define IS_SPI_BIDOE(x) (((x) == SPI_BID_RX) || \ - ((x) == SPI_BID_TX)) -#define IS_SPI_BIDMODE(x) (((x) == SPI_BIDMODE_DUAL) || \ - ((x) == SPI_BIDMODE_SOLE)) -#define IS_SPI_DIRECTION(x) (((x) == SPI_DIRECTION_2LINES) || \ - ((x) == SPI_DIRECTION_2LINES_RXONLY) || \ - ((x) == SPI_DIRECTION_1LINE) || \ - ((x) == SPI_DIRECTION_1LINE_RX)) -#define IS_SPI_DMA_REQ(x) (((x) == SPI_DMA_REQ_TX) || \ - ((x) == SPI_DMA_REQ_RX)) -#define IS_SPI_SR_STATUS(x) (((x) == SPI_SR_TXBE) || \ - ((x) == SPI_SR_RXBNE) || \ - ((x) == SPI_SR_TXBE_RXBNE)) -#define IS_SPI_IT(x) (((x) == SPI_IT_ERR) || \ - ((x) == SPI_IT_RXBNE) || \ - ((x) == SPI_IT_TXBE)) -#define IS_SPI_IF(x) (((x) == SPI_IF_RXBNE) || \ - ((x) == SPI_IF_TXBE) || \ - ((x) == SPI_IF_CRCERR) || \ - ((x) == SPI_IF_MODF) || \ - ((x) == SPI_IF_OVE) || \ - ((x) == SPI_IF_BUSY)) -#define IS_SPI_STATUS(x) (((x) == SPI_STATUS_RXBNE) || \ - ((x) == SPI_STATUS_TXBE) || \ - ((x) == SPI_STATUS_CRCERR) || \ - ((x) == SPI_STATUS_MODEERR) || \ - ((x) == SPI_STATUS_OVERR) || \ - ((x) == SPI_STATUS_BUSY)) -/** - * @} - */ - -/** @addtogroup SPI_Public_Functions - * @{ - */ - -/** @addtogroup SPI_Public_Functions_Group1 - * @{ - */ - -ald_status_t ald_spi_init(spi_handle_t *hperh); -void ald_spi_reset(spi_handle_t *hperh); -/** - * @} - */ - -/** @addtogroup SPI_Public_Functions_Group2 - * @{ - */ -int32_t ald_spi_send_byte_fast(spi_handle_t *hperh, uint8_t data); -int32_t ald_spi_send_byte_fast_1line(spi_handle_t *hperh, uint8_t data); -uint8_t ald_spi_recv_byte_fast(spi_handle_t *hperh); -ald_status_t ald_spi_send(spi_handle_t *hperh, uint8_t *buf, uint16_t size, uint32_t timeout); -ald_status_t ald_spi_recv(spi_handle_t *hperh, uint8_t *buf, uint16_t size, uint32_t timeout); -ald_status_t ald_spi_send_recv(spi_handle_t *hperh, uint8_t *tx_buf, uint8_t *rx_buf, uint16_t size, uint32_t timeout); -ald_status_t ald_spi_send_by_it(spi_handle_t *hperh, uint8_t *buf, uint16_t size); -ald_status_t ald_spi_recv_by_it(spi_handle_t *hperh, uint8_t *buf, uint16_t size); -ald_status_t ald_spi_send_recv_by_it(spi_handle_t *hperh, uint8_t *tx_buf, uint8_t *rx_buf, uint16_t size); -#ifdef ALD_DMA -ald_status_t ald_spi_send_by_dma(spi_handle_t *hperh, uint8_t *buf, uint16_t size, uint8_t channel); -ald_status_t ald_spi_recv_by_dma(spi_handle_t *hperh, uint8_t *buf, uint16_t size, uint8_t channel); -ald_status_t ald_spi_send_recv_by_dma(spi_handle_t *hperh, uint8_t *tx_buf, uint8_t *rx_buf, uint16_t size, uint8_t tx_channel, uint8_t rx_channel); -ald_status_t ald_spi_dma_pause(spi_handle_t *hperh); -ald_status_t ald_spi_dma_resume(spi_handle_t *hperh); -ald_status_t ald_spi_dma_stop(spi_handle_t *hperh); -#endif -/** - * @} - */ - -/** @addtogroup SPI_Public_Functions_Group3 - * @{ - */ -void ald_spi_irq_handler(spi_handle_t *hperh); -void ald_spi_interrupt_config(spi_handle_t *hperh, spi_it_t it, type_func_t state); -void ald_spi_speed_config(spi_handle_t *hperh, spi_baud_t speed); -void ald_spi_dma_req_config(spi_handle_t *hperh, spi_dma_req_t req, type_func_t state); -it_status_t ald_spi_get_it_status(spi_handle_t *hperh, spi_it_t it); -flag_status_t spi_get_status(spi_handle_t *hperh, spi_status_t status); -flag_status_t ald_spi_get_flag_status(spi_handle_t *hperh, spi_flag_t flag); -void ald_spi_clear_flag_status(spi_handle_t *hperh, spi_flag_t flag); -/** - * @} - */ - -/** @addtogroup SPI_Public_Functions_Group4 - * @{ - */ -spi_state_t ald_spi_get_state(spi_handle_t *hperh); -uint32_t ald_spi_get_error(spi_handle_t *hperh); -/** - * @} - */ - -/** - * @} - */ - -/** - * @} - */ - -/** - * @} - */ -#ifdef __cplusplus -} -#endif -#endif diff --git a/bsp/essemi/es32f0334/libraries/ES32F033x_ALD_StdPeriph_Driver/Include/ald_syscfg.h b/bsp/essemi/es32f0334/libraries/ES32F033x_ALD_StdPeriph_Driver/Include/ald_syscfg.h deleted file mode 100644 index 35844c887e..0000000000 --- a/bsp/essemi/es32f0334/libraries/ES32F033x_ALD_StdPeriph_Driver/Include/ald_syscfg.h +++ /dev/null @@ -1,105 +0,0 @@ -/** - ********************************************************************************* - * - * @file ald_syscfg.h - * @brief SYSCFG module driver. - * - * @version V1.0 - * @date 04 Jun 2017 - * @author AE Team - * @note - * - * Copyright (C) Shanghai Eastsoft Microelectronics Co. Ltd. All rights reserved. - * - ********************************************************************************* - */ - -#ifndef __ALD_SYSCFG_H__ -#define __ALD_SYSCFG_H__ - -#ifdef __cplusplus - extern "C" { -#endif - -#include "utils.h" - - -/** @addtogroup ES32FXXX_ALD - * @{ - */ - -/** @defgroup SYSCFG SYSCFG - * @brief SYSCFG module driver - * @{ - */ - -/** @defgroup SYSCFG_Public_Macros SYSCFG Public Macros - * @{ - */ -#define SYSCFG_LOCK() WRITE_REG(SYSCFG->PROT, 0x0U) -#define SYSCFG_UNLOCK() WRITE_REG(SYSCFG->PROT, 0x55AA6996U) -#define GET_SYSCFG_LOCK() READ_BIT(SYSCFG->PROT, SYSCFG_PROT_PROT_MSK) - -#define BOOT_FROM_BOOT_ROM() \ -do { \ - SYSCFG_UNLOCK(); \ - SET_BIT(SYSCFG->MEMRMP, SYSCFG_MEMRMP_BRRMPEN_MSK); \ - CLEAR_BIT(SYSCFG->MEMRMP, SYSCFG_MEMRMP_BFRMPEN_MSK); \ - SYSCFG_LOCK(); \ -} while (0) - -#define BOOT_FROM_BOOT_FLASH() \ -do { \ - SYSCFG_UNLOCK(); \ - CLEAR_BIT(SYSCFG->MEMRMP, SYSCFG_MEMRMP_BRRMPEN_MSK); \ - SET_BIT(SYSCFG->MEMRMP, SYSCFG_MEMRMP_BFRMPEN_MSK); \ - SYSCFG_LOCK(); \ -} while (0) - -#define BOOT_FROM_FLASH() \ -do { \ - SYSCFG_UNLOCK(); \ - CLEAR_BIT(SYSCFG->MEMRMP, SYSCFG_MEMRMP_BRRMPEN_MSK); \ - CLEAR_BIT(SYSCFG->MEMRMP, SYSCFG_MEMRMP_BFRMPEN_MSK); \ - SYSCFG_LOCK(); \ -} while (0) -/** - * @} - */ - - -/** @defgroup SYSCFG_Public_Functions SYSCFG Public Functions - * @{ - */ -__STATIC_INLINE__ void ald_vtor_config(uint32_t offset, type_func_t status) -{ - SYSCFG_UNLOCK(); - - if (status) { - MODIFY_REG(SYSCFG->VTOR, SYSCFG_VTOR_VTO_MSK, (offset & ~0x3FU)); - SET_BIT(SYSCFG->MEMRMP, SYSCFG_MEMRMP_VTOEN_MSK); - } - else { - CLEAR_BIT(SYSCFG->MEMRMP, SYSCFG_MEMRMP_VTOEN_MSK); - } - - SYSCFG_LOCK(); - return; -} -/** - * @} - */ - -/** - * @} - */ - -/** - * @} - */ - -#ifdef __cplusplus -} -#endif - -#endif diff --git a/bsp/essemi/es32f0334/libraries/ES32F033x_ALD_StdPeriph_Driver/Include/ald_timer.h b/bsp/essemi/es32f0334/libraries/ES32F033x_ALD_StdPeriph_Driver/Include/ald_timer.h deleted file mode 100644 index 538fc0ca0b..0000000000 --- a/bsp/essemi/es32f0334/libraries/ES32F033x_ALD_StdPeriph_Driver/Include/ald_timer.h +++ /dev/null @@ -1,1154 +0,0 @@ -/** - ********************************************************************************* - * - * @file ald_timer.h - * @brief TIMER module driver. - * This is the common part of the TIMER initialization - * - * @version V1.0 - * @date 06 Nov 2017 - * @author AE Team - * @note - * - * Copyright (C) Shanghai Eastsoft Microelectronics Co. Ltd. All rights reserved. - * - ********************************************************************************* - */ - -#ifndef __ALD_TIMER_H__ -#define __ALD_TIMER_H__ - -#ifdef __cplusplus - extern "C" { -#endif - -#include "utils.h" -#include "ald_dma.h" - -/** @addtogroup ES32FXXX_ALD - * @{ - */ - -/** @addtogroup TIMER - * @{ - */ - -/** @defgroup TIMER_Public_Types TIMER Public Types - * @{ - */ - -/** - * @brief TIMER counter mode - */ -typedef enum { - TIMER_CNT_MODE_UP = 0U, /**< Counter mode up */ - TIMER_CNT_MODE_DOWN = 1U, /**< Counter mode down */ - TIMER_CNT_MODE_CENTER1 = 2U, /**< Counter mode center1 */ - TIMER_CNT_MODE_CENTER2 = 3U, /**< Counter mode center2 */ - TIMER_CNT_MODE_CENTER3 = 4U, /**< Counter mode center3 */ -} timer_cnt_mode_t; - -/** - * @brief TIMER clock division - */ -typedef enum { - TIMER_CLOCK_DIV1 = 0U, /**< No prescaler is used */ - TIMER_CLOCK_DIV2 = 1U, /** Clock is divided by 2 */ - TIMER_CLOCK_DIV4 = 2U, /** Clock is divided by 4 */ -} timer_clock_division_t; - -/** - * @brief TIMER output compare and PWM modes - */ -typedef enum { - TIMER_OC_MODE_TIMERING = 0U, /**< Output compare mode is timering */ - TIMER_OC_MODE_ACTIVE = 1U, /**< Output compare mode is active */ - TIMER_OC_MODE_INACTIVE = 2U, /**< Output compare mode is inactive */ - TIMER_OC_MODE_TOGGLE = 3U, /**< Output compare mode is toggle */ - TIMER_OC_MODE_FORCE_INACTIVE = 4U, /**< Output compare mode is force inactive */ - TIMER_OC_MODE_FORCE_ACTIVE = 5U, /**< Output compare mode is force active */ - TIMER_OC_MODE_PWM1 = 6U, /**< Output compare mode is pwm1 */ - TIMER_OC_MODE_PWM2 = 7U, /**< Output compare mode is pwm2 */ -} timer_oc_mode_t; - -/** - * @brief TIMER output compare polarity - */ -typedef enum { - TIMER_OC_POLARITY_HIGH = 0U, /**< Output compare polarity is high */ - TIMER_OC_POLARITY_LOW = 1U, /**< Output compare polarity is low */ -} timer_oc_polarity_t; - -/** - * @brief TIMER complementary output compare polarity - */ -typedef enum { - TIMER_OCN_POLARITY_HIGH = 0U, /**< Complementary output compare polarity is high */ - TIMER_OCN_POLARITY_LOW = 1U, /**< Complementary output compare polarity is low */ -} timer_ocn_polarity_t; - -/** - * @brief TIMER output compare idle state - */ -typedef enum { - TIMER_OC_IDLE_RESET = 0U, /**< Output compare idle state is reset */ - TIMER_OC_IDLE_SET = 1U, /**< Output compare idle state is set */ -} timer_oc_idle_t; - -/** - * @brief TIMER complementary output compare idle state - */ -typedef enum { - TIMER_OCN_IDLE_RESET = 0U, /**< Complementary output compare idle state is reset */ - TIMER_OCN_IDLE_SET = 1U, /**< Complementary output compare idle state is set */ -} timer_ocn_idle_t; - -/** - * @brief TIMER channel - */ -typedef enum { - TIMER_CHANNEL_1 = 0U, /**< Channel 1 */ - TIMER_CHANNEL_2 = 1U, /**< Channel 2 */ - TIMER_CHANNEL_3 = 2U, /**< Channel 3 */ - TIMER_CHANNEL_4 = 4U, /**< Channel 4 */ - TIMER_CHANNEL_ALL = 0xFU, /**< All channel */ -} timer_channel_t; - -/** - * @brief TIMER one pulse mode - */ -typedef enum { - TIMER_OP_MODE_REPEAT = 0U, /**< Repetitive */ - TIMER_OP_MODE_SINGLE = 1U, /**< single */ -} timer_op_mode_t; - -/** - * @brief TIMER one pulse output channel - */ -typedef enum { - TIMER_OP_OUTPUT_CHANNEL_1 = 0U, /**< One pulse output channal 1 */ - TIMER_OP_OUTPUT_CHANNEL_2 = 1U, /**< One pulse output channal 2 */ -} timer_op_output_channel_t; - -/** - * @brief TIMER time base configuration structure definition - */ -typedef struct { - uint32_t prescaler; /**< Specifies the prescaler value used to divide the TIMER clock. */ - timer_cnt_mode_t mode; /**< Specifies the counter mode. */ - uint32_t period; /**< Specifies the period value to be loaded into ARR at the next update event. */ - timer_clock_division_t clk_div; /**< Specifies the clock division.*/ - uint32_t re_cnt; /**< Specifies the repetition counter value. */ -} timer_base_init_t; - -/** - * @brief TIMER output compare configuration structure definition - */ -typedef struct { - timer_oc_mode_t oc_mode; /**< Specifies the TIMER mode. */ - uint32_t pulse; /**< Specifies the pulse value to be loaded into the Capture Compare Register. */ - timer_oc_polarity_t oc_polarity; /**< Specifies the output polarity. */ - timer_ocn_polarity_t ocn_polarity; /**< Specifies the complementary output polarity. */ - type_func_t oc_fast_en; /**< Specifies the Fast mode state. */ - timer_oc_idle_t oc_idle; /**< Specifies the TIMER Output Compare pin state during Idle state. */ - timer_ocn_idle_t ocn_idle; /**< Specifies the TIMER Output Compare pin state during Idle state. */ -} timer_oc_init_t; - -/** - * @brief State structures definition - */ -typedef enum { - TIMER_STATE_RESET = 0x00U, /**< Peripheral not yet initialized or disabled */ - TIMER_STATE_READY = 0x01U, /**< Peripheral Initialized and ready for use */ - TIMER_STATE_BUSY = 0x02U, /**< An internal process is ongoing */ - TIMER_STATE_TIMEREOUT = 0x03U, /**< Timeout state */ - TIMER_STATE_ERROR = 0x04U, /**< Reception process is ongoing */ -} timer_state_t; - -/** - * @brief Active channel structures definition - */ -typedef enum { - TIMER_ACTIVE_CHANNEL_1 = 0x01U, /**< The active channel is 1 */ - TIMER_ACTIVE_CHANNEL_2 = 0x02U, /**< The active channel is 2 */ - TIMER_ACTIVE_CHANNEL_3 = 0x04U, /**< The active channel is 3 */ - TIMER_ACTIVE_CHANNEL_4 = 0x08U, /**< The active channel is 4 */ - TIMER_ACTIVE_CHANNEL_CLEARED = 0x00U, /**< All active channels cleared */ -} timer_active_channel_t; - -/** - * @brief TIMER time base handle structure definition - */ -typedef struct timer_handle_s { - TIMER_TypeDef *perh; /**< Register base address */ - timer_base_init_t init; /**< TIMER Time Base required parameters */ - timer_active_channel_t ch; /**< Active channel */ - lock_state_t lock; /**< Locking object */ - timer_state_t state; /**< TIMER operation state */ - -#ifdef ALD_DMA - dma_handle_t hdma1; /**< Timer DMA handle parameters */ - dma_handle_t hdma2; -#endif - - void (*period_elapse_cbk)(struct timer_handle_s *arg); /**< Period elapse callback */ - void (*delay_elapse_cbk)(struct timer_handle_s *arg); /**< Delay_elapse callback */ - void (*capture_cbk)(struct timer_handle_s *arg); /**< Capture callback */ - void (*pwm_pulse_finish_cbk)(struct timer_handle_s *arg); /**< PWM_pulse_finish callback */ - void (*trigger_cbk)(struct timer_handle_s *arg); /**< Trigger callback */ - void (*break_cbk)(struct timer_handle_s *arg); /**< Break callback */ - void (*com_cbk)(struct timer_handle_s *arg); /**< commutation callback */ - void (*error_cbk)(struct timer_handle_s *arg); /**< Error callback */ -} timer_handle_t; - - -/** - * @brief TIMER encoder mode - */ -typedef enum { - TIMER_ENC_MODE_TI1 = 1U, /**< encoder mode 1 */ - TIMER_ENC_MODE_TI2 = 2U, /**< encoder mode 2 */ - TIMER_ENC_MODE_TI12 = 3U, /**< encoder mode 3 */ -} timer_encoder_mode_t; - -/** - * @brief TIMER input capture polarity - */ -typedef enum { - TIMER_IC_POLARITY_RISE = 0U, /**< Input capture polarity rising */ - TIMER_IC_POLARITY_FALL = 1U, /**< Input capture polarity falling */ -} timer_ic_polarity_t; - -/** - *@brief TIMER input capture selection - */ -typedef enum { - TIMER_IC_SEL_DIRECT = 1U, /**< IC1 -- TI1 */ - TIMER_IC_SEL_INDIRECT = 2U, /**< IC1 -- TI2 */ - TIMER_IC_SEL_TRC = 3U, /**< IC1 -- TRC */ -} timer_ic_select_t; - -/** - * @brief TIMER input capture prescaler - */ -typedef enum { - TIMER_IC_PSC_DIV1 = 0U, /**< Capture performed once every 1 events */ - TIMER_IC_PSC_DIV2 = 1U, /**< Capture performed once every 2 events */ - TIMER_IC_PSC_DIV4 = 2U, /**< Capture performed once every 4 events */ - TIMER_IC_PSC_DIV8 = 3U, /**< Capture performed once every 4 events */ -} timer_ic_prescaler_t; - -/** - * @brief TIMER encoder configuration structure definition - */ -typedef struct { - timer_encoder_mode_t mode; /**< Specifies the encoder mode */ - timer_ic_polarity_t ic1_polarity; /**< Specifies the active edge of the input signal */ - timer_ic_select_t ic1_sel; /**< Specifies the input */ - timer_ic_prescaler_t ic1_psc; /**< Specifies the Input Capture Prescaler */ - uint32_t ic1_filter; /**< Specifies the input capture filter */ - timer_ic_polarity_t ic2_polarity; /**< Specifies the active edge of the input signal */ - timer_ic_select_t ic2_sel; /**< Specifies the input */ - timer_ic_prescaler_t ic2_psc; /**< Specifies the Input Capture Prescaler */ - uint32_t ic2_filter; /**< Specifies the input capture filter */ -} timer_encoder_init_t; - -/** - * @brief TIMER input capture configuration structure definition - */ -typedef struct { - timer_ic_polarity_t polarity; /**< Specifies the active edge of the input signal */ - timer_ic_select_t sel; /**< Specifies the input */ - timer_ic_prescaler_t psc; /**< Specifies the Input Capture Prescaler */ - uint32_t filter; /**< Specifies the input capture filter */ -} timer_ic_init_t; - -/** - * @brief TIMER one pulse mode configuration structure definition - */ -typedef struct { - timer_oc_mode_t mode; /**< Specifies the TIMER mode */ - uint16_t pulse; /**< Specifies the pulse value */ - timer_oc_polarity_t oc_polarity; /**< Specifies the output polarity */ - timer_ocn_polarity_t ocn_polarity; /**< Specifies the complementary output polarity */ - timer_oc_idle_t oc_idle; /**< Specifies the TIMER Output Compare pin state during Idle state */ - timer_ocn_idle_t ocn_idle; /**< Specifies the TIMER Output Compare pin state during Idle state */ - timer_ic_polarity_t polarity; /**< Specifies the active edge of the input signal */ - timer_ic_select_t sel; /**< Specifies the input */ - uint32_t filter; /**< Specifies the input capture filter */ -} timer_one_pulse_init_t; - -/** @brief TIMER clear input source - */ -typedef enum { - TIMER_INPUT_NONE = 0U, /**< Clear input none */ - TIMER_INPUT_ETR = 1U, /**< Clear input etr */ -} timer_clear_input_source_t; - -/** @brief TIMER clear input polarity - */ -typedef enum { - TIMER_POLARITY_NO_INV = 0U, /**< Polarity for ETRx pin */ - TIMER_POLARITY_INV = 1U, /**< Polarity for ETRx pin */ -} timer_clear_input_polarity_t; - -/** @brief TIMER clear input polarity - */ -typedef enum { - TIMER_ETR_PSC_DIV1 = 0U, /**< No prescaler is used */ - TIMER_ETR_PSC_DIV2 = 1U, /**< ETR input source is divided by 2 */ - TIMER_ETR_PSC_DIV4 = 2U, /**< ETR input source is divided by 4 */ - TIMER_ETR_PSC_DIV8 = 3U, /**< ETR input source is divided by 8 */ -} timer_etr_psc_t; - -/** - * @brief TIMER clear input configuration handle structure definition - */ -typedef struct { - type_func_t state; /**< TIMER clear Input state */ - timer_clear_input_source_t source; /**< TIMER clear Input sources */ - timer_clear_input_polarity_t polarity; /**< TIMER Clear Input polarity */ - timer_etr_psc_t psc; /**< TIMER Clear Input prescaler */ - uint32_t filter; /**< TIMER Clear Input filter */ -} timer_clear_input_config_t; - -/** @brief TIMER clock source - */ -typedef enum { - TIMER_SRC_ETRMODE2 = 0U, /**< Clock source is etr mode2 */ - TIMER_SRC_INTER = 1U, /**< Clock source is etr internal */ - TIMER_SRC_ITR0 = 2U, /**< Clock source is etr itr0 */ - TIMER_SRC_ITR1 = 3U, /**< Clock source is etr itr1 */ - TIMER_SRC_ITR2 = 4U, /**< Clock source is etr itr2 */ - TIMER_SRC_ITR3 = 5U, /**< Clock source is etr itr3 */ - TIMER_SRC_TI1ED = 6U, /**< Clock source is etr ti1ed */ - TIMER_SRC_TI1 = 7U, /**< Clock source is etr ti1 */ - TIMER_SRC_TI2 = 8U, /**< Clock source is etr ti2 */ - TIMER_SRC_ETRMODE1 = 9U, /**< Clock source is etr mode1 */ -} timer_clock_source_t; - -/** @brief TIMER clock polarity - */ -typedef enum { - TIMER_CLK_POLARITY_INV = 1U, /**< Polarity for ETRx clock sources */ - TIMER_CLK_POLARITY_NO_INV = 0U, /**< Polarity for ETRx clock sources */ - TIMER_CLK_POLARITY_RISE = 0U, /**< Polarity for TIx clock sources */ - TIMER_CLK_POLARITY_FALL = 1U, /**< Polarity for TIx clock sources */ - TIMER_CLK_POLARITY_BOTH = 3U, /**< Polarity for TIx clock sources */ -} timer_clock_polarity_t; - -/** - * @brief TIMER clock config structure definition - */ -typedef struct { - timer_clock_source_t source; /**< TIMER clock sources */ - timer_clock_polarity_t polarity; /**< TIMER clock polarity */ - timer_etr_psc_t psc; /**< TIMER clock prescaler */ - uint32_t filter; /**< TIMER clock filter */ -} timer_clock_config_t; - -/** - * @brief TIMER slave mode - */ -typedef enum { - TIMER_MODE_DISABLE = 0U, /**< Slave mode is disable */ - TIMER_MODE_ENC1 = 1U, /**< Slave mode is encoder1 */ - TIMER_MODE_ENC2 = 2U, /**< Slave mode is encoder2 */ - TIMER_MODE_ENC3 = 3U, /**< Slave mode is encoder3 */ - TIMER_MODE_RESET = 4U, /**< Slave mode is reset */ - TIMER_MODE_GATED = 5U, /**< Slave mode is gated */ - TIMER_MODE_TRIG = 6U, /**< Slave mode is trigger */ - TIMER_MODE_EXTERNAL1 = 7U, /**< Slave mode is external1 */ -} timer_slave_mode_t; - -/** - * @brief TIMER ts definition - */ -typedef enum { - TIMER_TS_ITR0 = 0U, /**< ITR0 */ - TIMER_TS_ITR1 = 1U, /**< ITR1 */ - TIMER_TS_ITR2 = 2U, /**< ITR2 */ - TIMER_TS_ITR3 = 3U, /**< ITR3 */ - TIMER_TS_TI1F_ED = 4U, /**< TI1F_ED */ - TIMER_TS_TI1FP1 = 5U, /**< TI1FP1 */ - TIMER_TS_TI2FP2 = 6U, /**< TI2FP2 */ - TIMER_TS_ETRF = 7U, /**< ETRF */ -} timer_ts_t; - -/** - * @brief TIMER slave configuration structure definition - */ -typedef struct { - timer_slave_mode_t mode; /**< Slave mode selection */ - timer_ts_t input; /**< Input Trigger source */ - timer_clock_polarity_t polarity; /**< Input Trigger polarity */ - timer_etr_psc_t psc; /**< Input trigger prescaler */ - uint32_t filter; /**< Input trigger filter */ -} timer_slave_config_t; - -/** - * @brief TIMER hall sensor configuretion structure definition - */ -typedef struct { - timer_ic_polarity_t polarity; /**< Specifies the active edge of the input signal */ - timer_ic_prescaler_t psc; /**< Specifies the Input Capture Prescaler */ - uint32_t filter; /**< Specifies the input capture filter [0x0, 0xF] */ - uint32_t delay; /**< Specifies the pulse value to be loaded into the register [0x0, 0xFFFF] */ -} timer_hall_sensor_init_t; - -/** - * @brief TIMER lock level - */ -typedef enum { - TIMER_LOCK_LEVEL_OFF = 0U, /**< Lock off */ - TIMER_LOCK_LEVEL_1 = 1U, /**< Lock level 1 */ - TIMER_LOCK_LEVEL_2 = 2U, /**< Lock level 2 */ - TIMER_LOCK_LEVEL_3 = 3U, /**< Lock level 3 */ -} timer_lock_level_t; - -/** - * @brief TIMER break polarity - */ -typedef enum { - TIMER_BREAK_POLARITY_LOW = 0U, /**< LOW */ - TIMER_BREAK_POLARITY_HIGH = 1U, /**< HIGH */ -} timer_break_polarity_t; - -/** - * @brief TIMER break and dead time configuretion structure definition - */ -typedef struct { - type_func_t off_run; /**< Enalbe/Disable off state in run mode */ - type_func_t off_idle; /**< Enalbe/Disable off state in idle mode */ - timer_lock_level_t lock_level; /**< Lock level */ - uint32_t dead_time; /**< Dead time, [0x0, 0xFF] */ - type_func_t break_state; /**< Break state */ - timer_break_polarity_t polarity; /**< Break input polarity */ - type_func_t auto_out; /**< Enalbe/Disable automatic output */ -} timer_break_dead_time_t; - -/** - * @brief TIMER commutation event channel configuretion structure definition - */ -typedef struct { - type_func_t en; /**< Enalbe/Disable the channel */ - type_func_t n_en; /**< Enalbe/Disable the complementary channel */ - timer_oc_mode_t mode; /**< Mode of the channel */ -} timer_channel_config_t; - -/** - * @brief TIMER commutation event configuretion structure definition - */ -typedef struct { - timer_channel_config_t ch[3]; /**< Configure of channel */ -} timer_com_channel_config_t; - -/** - * @brief TIMER master mode selection - */ -typedef enum { - TIMER_TRGO_RESET = 0U, /**< RESET */ - TIMER_TRGO_ENABLE = 1U, /**< ENABLE */ - TIMER_TRGO_UPDATE = 2U, /**< UPDATE */ - TIMER_TRGO_OC1 = 3U, /**< OC1 */ - TIMER_TRGO_OC1REF = 4U, /**< OC1REF */ - TIMER_TRGO_OC2REF = 5U, /**< OC2REF */ - TIMER_TRGO_OC3REF = 6U, /**< OC3REF */ - TIMER_TRGO_OC4REF = 7U, /**< OC4REF */ -} timer_master_mode_sel_t; - -/** - * @brief TIMER master configuretion structure definition - */ -typedef struct { - timer_master_mode_sel_t sel; /**< Specifies the active edge of the input signal */ - type_func_t master_en; /**< Master/Slave mode selection */ -} timer_master_config_t; - -/** - * @brief Specifies the event source - */ -typedef enum { - TIMER_SRC_UPDATE = (1U << 0), /**< Event source is update */ - TIMER_SRC_CC1 = (1U << 1), /**< Event source is channel1 */ - TIMER_SRC_CC2 = (1U << 2), /**< Event source is channel2 */ - TIMER_SRC_CC3 = (1U << 3), /**< Event source is channel3 */ - TIMER_SRC_CC4 = (1U << 4), /**< Event source is channel4 */ - TIMER_SRC_COM = (1U << 5), /**< Event source is compare */ - TIMER_SRC_TRIG = (1U << 6), /**< Event source is trigger */ - TIMER_SRC_BREAK = (1U << 7), /**< Event source is break */ -} timer_event_source_t; - -/** - * @brief TIMER interrupt definition - */ -typedef enum { - TIMER_IT_UPDATE = (1U << 0), /**< Update interrupt bit */ - TIMER_IT_CC1 = (1U << 1), /**< Channel1 interrupt bit */ - TIMER_IT_CC2 = (1U << 2), /**< Channel2 interrupt bit */ - TIMER_IT_CC3 = (1U << 3), /**< Channel3 interrupt bit */ - TIMER_IT_CC4 = (1U << 4), /**< Channel4 interrupt bit */ - TIMER_IT_COM = (1U << 5), /**< compare interrupt bit */ - TIMER_IT_TRIGGER = (1U << 6), /**< Trigger interrupt bit */ - TIMER_IT_BREAK = (1U << 7), /**< Break interrupt bit */ -} timer_it_t; - -/** - * @brief TIMER DMA request - */ -typedef enum { - TIMER_DMA_UPDATE = (1U << 8), /**< DMA request from update */ - TIMER_DMA_CC1 = (1U << 9), /**< DMA request from channel1 */ - TIMER_DMA_CC2 = (1U << 10), /**< DMA request from channel2 */ - TIMER_DMA_CC3 = (1U << 11), /**< DMA request from channel3 */ - TIMER_DMA_CC4 = (1U << 12), /**< DMA request from channel4 */ - TIMER_DMA_COM = (1U << 13), /**< DMA request from compare */ - TIMER_DMA_TRIGGER = (1U << 14), /**< DMA request from trigger */ -} timer_dma_req_t; - -/** - * @brief TIMER flag definition - */ -typedef enum { - TIMER_FLAG_UPDATE = (1U << 0), /**< Update interrupt flag */ - TIMER_FLAG_CC1 = (1U << 1), /**< Channel1 interrupt flag */ - TIMER_FLAG_CC2 = (1U << 2), /**< Channel2 interrupt flag */ - TIMER_FLAG_CC3 = (1U << 3), /**< Channel3 interrupt flag */ - TIMER_FLAG_CC4 = (1U << 4), /**< Channel4 interrupt flag */ - TIMER_FLAG_COM = (1U << 5), /**< Compare interrupt flag */ - TIMER_FLAG_TRIGGER = (1U << 6), /**< Trigger interrupt flag */ - TIMER_FLAG_BREAK = (1U << 7), /**< Break interrupt flag */ - TIMER_FLAG_CC1OF = (1U << 9), /**< Channel1 override state flag */ - TIMER_FLAG_CC2OF = (1U << 10), /**< Channel2 override state flag */ - TIMER_FLAG_CC3OF = (1U << 11), /**< Channel3 override state flag */ - TIMER_FLAG_CC4OF = (1U << 12), /**< Channel4 override state flag */ -} timer_flag_t; -/** - * @} - */ - -/** @defgroup TIMER_Public_Macros TIMER Public Macros - * @{ - */ -#define CCER_CCxE_MASK ((1U << 0) | (1U << 4) | (1U << 8) | (1U << 12)) -#define CCER_CCxNE_MASK ((1U << 2) | (1U << 6) | (1U << 10)) - -/** - * @brief Reset TIMER handle state - */ -#define TIMER_RESET_HANDLE_STATE(hperh) ((hperh)->state = TIMER_STATE_RESET) - -/** - * @brief Enable the TIMER peripheral. - */ -#define TIMER_ENABLE(hperh) (SET_BIT((hperh)->perh->CON1, TIMER_CON1_CNTEN_MSK)) - -/** - * @brief Enable the TIMER main output. - */ -#define TIMER_MOE_ENABLE(hperh) (SET_BIT((hperh)->perh->BDCFG, TIMER_BDCFG_GOEN_MSK)) - -/** - * @brief Disable the TIMER peripheral. - */ -#define TIMER_DISABLE(hperh) \ -do { \ - if ((((hperh)->perh->CCEP & CCER_CCxE_MASK) == 0) \ - && (((hperh)->perh->CCEP & CCER_CCxNE_MASK) == 0)) \ - CLEAR_BIT((hperh)->perh->CON1, TIMER_CON1_CNTEN_MSK); \ -} while (0) - -/** - * @brief Disable the TIMER main output. - * @note The Main Output Enable of a timer instance is disabled only if - * all the CCx and CCxN channels have been disabled - */ -#define TIMER_MOE_DISABLE(hperh) \ -do { \ - if ((((hperh)->perh->CCEP & CCER_CCxE_MASK) == 0) \ - && (((hperh)->perh->CCEP & CCER_CCxNE_MASK) == 0)) \ - CLEAR_BIT((hperh)->perh->BDCFG, TIMER_BDCFG_GOEN_MSK); \ -} while (0) - -/** - * @brief Sets the TIMER autoreload register value on runtime without calling - * another time any Init function. - */ -#define TIMER_SET_AUTORELOAD(handle, AUTORELOAD) \ -do { \ - (handle)->perh->AR = (AUTORELOAD); \ - (handle)->init.period = (AUTORELOAD); \ -} while (0) - -/** - * @brief Gets the TIMER autoreload register value on runtime - */ -#define TIMER_GET_AUTORELOAD(handle) ((handle)->perh->AR) - -/** - * @brief Gets the TIMER count register value on runtime - */ -#define TIMER_GET_CNT(handle) ((handle)->perh->COUNT) - -/** - * @brief Gets the TIMER count direction value on runtime - */ -#define TIMER_GET_DIR(handle) (READ_BITS((handle)->perh->CON1, TIMER_CON1_DIRSEL_MSK, TIMER_CON1_DIRSEL_POS)) - -/** - * @brief CCx DMA request sent when CCx event occurs - */ -#define TIMER_CCx_DMA_REQ_CCx(handle) (CLEAR_BIT((handle)->perh->CON2, TIMER_CON2_CCDMASEL_MSK)) - -/** - * @brief CCx DMA request sent when update event occurs - */ -#define TIMER_CCx_DMA_REQ_UPDATE(handle) (SET_BIT((handle)->perh->CON2, TIMER_CON2_CCDMASEL_MSK)) - -/** - * @brief Enable channel - * @param handle: TIMER handle - * @param ch: Must be one of this: - * TIMER_CHANNEL_1 - * TIMER_CHANNEL_2 - * TIMER_CHANNEL_3 - * TIMER_CHANNEL_4 - */ -#define TIMER_CCx_ENABLE(handle, ch) (((ch) == TIMER_CHANNEL_4) ? \ -(SET_BIT((handle)->perh->CCEP, TIMER_CCEP_CC4POL_MSK)) : (WRITE_REG(((handle)->perh->CCEP), (((handle)->perh->CCEP) | (1 << ((ch) << 2)))))) - -/** - * @brief Disable channel - * @param handle: TIMER handle - * @param ch: Must be one of this: - * TIMER_CHANNEL_1 - * TIMER_CHANNEL_2 - * TIMER_CHANNEL_3 - * TIMER_CHANNEL_4 - */ -#define TIMER_CCx_DISABLE(handle, ch) (((ch) == TIMER_CHANNEL_4) ? \ -(CLEAR_BIT((handle)->perh->CCEP, TIMER_CCEP_CC4EN_MSK)) : ((handle)->perh->CCEP &= ~(1 << ((ch) << 2)))) - -/** - * @brief Enable complementary channel - * @param handle: TIMER handle - * @param ch: Must be one of this: - * TIMER_CHANNEL_1 - * TIMER_CHANNEL_2 - * TIMER_CHANNEL_3 - */ -#define TIMER_CCxN_ENABLE(handle, ch) ((handle)->perh->CCEP |= (1 << (((ch) << 2) + 2))) - -/** - * @brief Disable complementary channel - * @param handle: TIMER handle - * @param ch: Must be one of this: - * TIMER_CHANNEL_1 - * TIMER_CHANNEL_2 - * TIMER_CHANNEL_3 - */ -#define TIMER_CCxN_DISABLE(handle, ch) ((handle)->perh->CCEP &= ~(1 << (((ch) << 2) + 2))) -/** - * @} - */ - -/** @defgroup TIMER_Private_Macros TIMER Private Macros - * @{ - */ -#if defined (ES32F065x) -#define IS_TIMER_INSTANCE(x) (((x) == AD16C4T0) || \ - ((x) == GP16C4T0) || \ - ((x) == GP16C2T0) || \ - ((x) == GP16C2T1) || \ - ((x) == BS16T0) || \ - ((x) == BS16T1) || \ - ((x) == BS16T2) || \ - ((x) == BS16T3)) -#define IS_ADTIMER_INSTANCE(x) ((x) == AD16C4T0) -#define IS_TIMER_XOR_INSTANCE(x) (((x) == AD16C4T0) || ((x) == GP16C4T0)) -#define IS_TIMER_COM_EVENT_INSTANCE(x) (((x) == AD16C4T0) || \ - ((x) == GP16C2T0) || \ - ((x) == GP16C2T1)) -#define IS_TIMER_CC2_INSTANCE(x) (((x) == AD16C4T0) || \ - ((x) == GP16C4T0) || \ - ((x) == GP16C2T0) || \ - ((x) == GP16C2T1)) -#define IS_TIMER_CC4_INSTANCE(x) (((x) == AD16C4T0) || \ - ((x) == GP16C4T0)) -#define IS_TIMER_BREAK_INSTANCE(x) (((x) == AD16C4T0) || \ - ((x) == GP16C2T0) || \ - ((x) == GP16C2T1)) -#define IS_TIMER_PWM_INPUT_INSTANCE(x, y) ((((x) == AD16C4T0) && \ - (((y) == TIMER_CHANNEL_1) || \ - ((y) == TIMER_CHANNEL_2))) || \ - (((x) == GP16C2T0) && \ - (((y) == TIMER_CHANNEL_1) || \ - ((y) == TIMER_CHANNEL_2))) || \ - (((x) == GP16C2T1) && \ - (((y) == TIMER_CHANNEL_1) || \ - ((y) == TIMER_CHANNEL_2))) || \ - (((x) == AD16C4T0) && \ - (((y) == TIMER_CHANNEL_1) || \ - ((y) == TIMER_CHANNEL_2)))) -#define IS_TIMER_CCX_INSTANCE(x, y) ((((x) == AD16C4T0) && \ - (((y) == TIMER_CHANNEL_1) || \ - ((y) == TIMER_CHANNEL_2) || \ - ((y) == TIMER_CHANNEL_3) || \ - ((y) == TIMER_CHANNEL_4))) || \ - (((x) == GP16C2T0) && \ - (((y) == TIMER_CHANNEL_1) || \ - ((y) == TIMER_CHANNEL_2))) || \ - (((x) == GP16C2T1) && \ - (((y) == TIMER_CHANNEL_1) || \ - ((y) == TIMER_CHANNEL_2))) || \ - (((x) == GP16C4T0) && \ - (((y) == TIMER_CHANNEL_1) || \ - ((y) == TIMER_CHANNEL_2) || \ - ((y) == TIMER_CHANNEL_3) || \ - ((y) == TIMER_CHANNEL_4)))) -#define IS_TIMER_CCXN_INSTANCE(x, y) ((((x) == AD16C4T0) || \ - ((x) == GP16C2T0) || \ - ((x) == GP16C2T1)) && \ - (((y) == TIMER_CHANNEL_1) || \ - ((y) == TIMER_CHANNEL_2) || \ - ((y) == TIMER_CHANNEL_3) || \ - ((y) == TIMER_CHANNEL_4))) -#define IS_TIMER_REPETITION_COUNTER_INSTANCE(x) (((x) == AD16C4T0) || \ - ((x) == GP16C2T0) || \ - ((x) == GP16C2T1)) -#define IS_TIMER_CLOCK_DIVISION_INSTANCE(x) IS_TIMER_CC2_INSTANCE(x) - -#elif defined (ES32F033x) || defined (ES32F093x) - -#define IS_TIMER_INSTANCE(x) (((x) == GP16C4T0) || \ - ((x) == BS16T0) || \ - ((x) == GP16C2T0) || \ - ((x) == GP16C2T1) || \ - ((x) == BS16T1) || \ - ((x) == BS16T2) || \ - ((x) == GP16C4T1) || \ - ((x) == BS16T3)) -#define IS_ADTIMER_INSTANCE(x) ((x) == AD16C4T0) -#define IS_TIMER_XOR_INSTANCE(x) (((x) == GP16C4T0) || ((x) == GP16C4T1)) -#define IS_TIMER_COM_EVENT_INSTANCE(x) (((x) == GP16C4T0) || \ - ((x) == GP16C2T0) || \ - ((x) == GP16C2T1)) -#define IS_TIMER_CC2_INSTANCE(x) (((x) == GP16C4T0) || \ - ((x) == GP16C2T0) || \ - ((x) == GP16C2T1) || \ - ((x) == GP16C4T1)) -#define IS_TIMER_CC4_INSTANCE(x) (((x) == GP16C4T0) || \ - ((x) == GP16C4T1)) -#define IS_TIMER_BREAK_INSTANCE(x) (((x) == GP16C4T0)) -#define IS_TIMER_PWM_INPUT_INSTANCE(x, y) ((((x) == GP16C4T0) && \ - (((y) == TIMER_CHANNEL_1) || \ - ((y) == TIMER_CHANNEL_2))) || \ - (((x) == GP16C2T0) && \ - (((y) == TIMER_CHANNEL_1) || \ - ((y) == TIMER_CHANNEL_2))) || \ - (((x) == GP16C2T1) && \ - (((y) == TIMER_CHANNEL_1) || \ - ((y) == TIMER_CHANNEL_2))) || \ - (((x) == GP16C4T1) && \ - (((y) == TIMER_CHANNEL_1) || \ - ((y) == TIMER_CHANNEL_2)))) -#define IS_TIMER_CCX_INSTANCE(x, y) ((((x) == GP16C4T0) && \ - (((y) == TIMER_CHANNEL_1) || \ - ((y) == TIMER_CHANNEL_2) || \ - ((y) == TIMER_CHANNEL_3) || \ - ((y) == TIMER_CHANNEL_4))) || \ - (((x) == GP16C2T0) && \ - (((y) == TIMER_CHANNEL_1) || \ - ((y) == TIMER_CHANNEL_2))) || \ - (((x) == GP16C2T1) && \ - (((y) == TIMER_CHANNEL_1) || \ - ((y) == TIMER_CHANNEL_2))) || \ - (((x) == GP16C4T1) && \ - (((y) == TIMER_CHANNEL_1) || \ - ((y) == TIMER_CHANNEL_2) || \ - ((y) == TIMER_CHANNEL_3) || \ - ((y) == TIMER_CHANNEL_4)))) -#define IS_TIMER_CCXN_INSTANCE(x, y) ((((x) == GP16C4T0) || \ - ((x) == GP16C2T0) || \ - ((x) == GP16C2T1)) && \ - (((y) == TIMER_CHANNEL_1) || \ - ((y) == TIMER_CHANNEL_2) || \ - ((y) == TIMER_CHANNEL_3) || \ - ((y) == TIMER_CHANNEL_4))) -#define IS_TIMER_REPETITION_COUNTER_INSTANCE(x) (((x) == GP16C4T0) || \ - ((x) == GP16C2T0) || \ - ((x) == GP16C2T1)) -#define IS_TIMER_CLOCK_DIVISION_INSTANCE(x) IS_TIMER_CC2_INSTANCE(x) -#endif - -#define IS_TIMER_COUNTER_MODE(x) (((x) == TIMER_CNT_MODE_UP) || \ - ((x) == TIMER_CNT_MODE_DOWN) || \ - ((x) == TIMER_CNT_MODE_CENTER1) || \ - ((x) == TIMER_CNT_MODE_CENTER2) || \ - ((x) == TIMER_CNT_MODE_CENTER3)) -#define IS_TIMER_CLOCK_DIVISION(x) (((x) == TIMER_CLOCK_DIV1) || \ - ((x) == TIMER_CLOCK_DIV2) || \ - ((x) == TIMER_CLOCK_DIV4)) -#define IS_TIMER_PWM_MODE(x) (((x) == TIMER_OC_MODE_PWM1) || \ - ((x) == TIMER_OC_MODE_PWM2)) -#define IS_TIMER_OC_MODE(x) (((x) == TIMER_OC_MODE_TIMERING) || \ - ((x) == TIMER_OC_MODE_ACTIVE) || \ - ((x) == TIMER_OC_MODE_INACTIVE) || \ - ((x) == TIMER_OC_MODE_TOGGLE) || \ - ((x) == TIMER_OC_MODE_FORCE_ACTIVE) || \ - ((x) == TIMER_OC_MODE_FORCE_INACTIVE) || \ - ((x) == TIMER_OC_MODE_PWM1) || \ - ((x) == TIMER_OC_MODE_PWM2)) -#define IS_TIMER_OC_POLARITY(x) (((x) == TIMER_OC_POLARITY_HIGH) || \ - ((x) == TIMER_OC_POLARITY_LOW)) -#define IS_TIMER_OCN_POLARITY(x) (((x) == TIMER_OCN_POLARITY_HIGH) || \ - ((x) == TIMER_OCN_POLARITY_LOW)) -#define IS_TIMER_OCIDLE_STATE(x) (((x) == TIMER_OC_IDLE_RESET) || \ - ((x) == TIMER_OC_IDLE_SET)) -#define IS_TIMER_OCNIDLE_STATE(x) (((x) == TIMER_OCN_IDLE_RESET) || \ - ((x) == TIMER_OCN_IDLE_SET)) -#define IS_TIMER_CHANNELS(x) (((x) == TIMER_CHANNEL_1) || \ - ((x) == TIMER_CHANNEL_2) || \ - ((x) == TIMER_CHANNEL_3) || \ - ((x) == TIMER_CHANNEL_4) || \ - ((x) == TIMER_CHANNEL_ALL)) -#define IS_TIMER_OP_MODE(x) (((x) == TIMER_OP_MODE_REPEAT) || \ - ((x) == TIMER_OP_MODE_SINGLE)) -#define IS_TIMER_OP_OUTPUT_CH(x) (((x) == TIMER_OP_OUTPUT_CHANNEL_1) || \ - ((x) == TIMER_OP_OUTPUT_CHANNEL_2)) -#define IS_TIMER_ENCODER_MODE(x) (((x) == TIMER_ENC_MODE_TI1) || \ - ((x) == TIMER_ENC_MODE_TI2) || \ - ((x) == TIMER_ENC_MODE_TI12)) -#define IS_TIMER_IC_POLARITY(x) (((x) == TIMER_IC_POLARITY_RISE) || \ - ((x) == TIMER_IC_POLARITY_FALL)) -#define IS_TIMER_IC_SELECT(x) (((x) == TIMER_IC_SEL_DIRECT) || \ - ((x) == TIMER_IC_SEL_INDIRECT) || \ - ((x) == TIMER_IC_SEL_TRC)) -#define IS_TIMER_IC_PSC(x) (((x) == TIMER_IC_PSC_DIV1) || \ - ((x) == TIMER_IC_PSC_DIV2) || \ - ((x) == TIMER_IC_PSC_DIV4) || \ - ((x) == TIMER_IC_PSC_DIV8)) -#define IS_TIMER_IC_FILTER(x) ((x) <= 0xF) -#define IS_TIMER_DEAD_TIMERE(x) ((x) <= 0xFF) -#define IS_TIMER_CLEAR_INPUT_SOURCE(x) (((x) == TIMER_INPUT_NONE) || \ - ((x) == TIMER_INPUT_ETR)) -#define IS_TIMER_CLEAR_INPUT_POLARITY(x) (((x) == TIMER_POLARITY_NO_INV) || \ - ((x) == TIMER_POLARITY_INV)) -#define IS_TIMER_ETR_PSC(x) (((x) == TIMER_ETR_PSC_DIV1) || \ - ((x) == TIMER_ETR_PSC_DIV2) || \ - ((x) == TIMER_ETR_PSC_DIV4) || \ - ((x) == TIMER_ETR_PSC_DIV8)) -#define IS_TIMER_CLOCK_SOURCE(x) (((x) == TIMER_SRC_ETRMODE2) || \ - ((x) == TIMER_SRC_INTER) || \ - ((x) == TIMER_SRC_ITR0) || \ - ((x) == TIMER_SRC_ITR1) || \ - ((x) == TIMER_SRC_ITR2) || \ - ((x) == TIMER_SRC_ITR3) || \ - ((x) == TIMER_SRC_TI1ED) || \ - ((x) == TIMER_SRC_TI1) || \ - ((x) == TIMER_SRC_TI2) || \ - ((x) == TIMER_SRC_ETRMODE1)) -#define IS_TIMER_CLOCK_POLARITY(x) (((x) == TIMER_CLK_POLARITY_INV) || \ - ((x) == TIMER_CLK_POLARITY_NO_INV) || \ - ((x) == TIMER_CLK_POLARITY_RISE) || \ - ((x) == TIMER_CLK_POLARITY_FALL) || \ - ((x) == TIMER_CLK_POLARITY_BOTH)) -#define IS_TIMER_SLAVE_MODE(x) (((x) == TIMER_MODE_DISABLE) || \ - ((x) == TIMER_MODE_ENC1) || \ - ((x) == TIMER_MODE_ENC2) || \ - ((x) == TIMER_MODE_ENC3) || \ - ((x) == TIMER_MODE_RESET) || \ - ((x) == TIMER_MODE_GATED) || \ - ((x) == TIMER_MODE_TRIG) || \ - ((x) == TIMER_MODE_EXTERNAL1)) -#define IS_TIMER_EVENT_SOURCE(x) (((x) == TIMER_SRC_UPDATE) || \ - ((x) == TIMER_SRC_CC1) || \ - ((x) == TIMER_SRC_CC2) || \ - ((x) == TIMER_SRC_CC3) || \ - ((x) == TIMER_SRC_CC4) || \ - ((x) == TIMER_SRC_COM) || \ - ((x) == TIMER_SRC_TRIG) || \ - ((x) == TIMER_SRC_BREAK)) -#define IS_TIMER_TS(x) (((x) == TIMER_TS_ITR0) || \ - ((x) == TIMER_TS_ITR1) || \ - ((x) == TIMER_TS_ITR2) || \ - ((x) == TIMER_TS_ITR3) || \ - ((x) == TIMER_TS_TI1F_ED) || \ - ((x) == TIMER_TS_TI1FP1) || \ - ((x) == TIMER_TS_TI2FP2) || \ - ((x) == TIMER_TS_ETRF)) -#define IS_TIMER_CLOCK_LEVEL(x) (((x) == TIMER_LOCK_LEVEL_OFF) || \ - ((x) == TIMER_LOCK_LEVEL_1) || \ - ((x) == TIMER_LOCK_LEVEL_2) || \ - ((x) == TIMER_LOCK_LEVEL_3)) -#define IS_TIMER_BREAK_POLARITY(x) (((x) == TIMER_BREAK_POLARITY_LOW) || \ - ((x) == TIMER_BREAK_POLARITY_HIGH)) -#define IS_TIMER_MASTER_MODE_SEL(x) (((x) == TIMER_TRGO_RESET) || \ - ((x) == TIMER_TRGO_ENABLE) || \ - ((x) == TIMER_TRGO_UPDATE) || \ - ((x) == TIMER_TRGO_OC1) || \ - ((x) == TIMER_TRGO_OC1REF) || \ - ((x) == TIMER_TRGO_OC2REF) || \ - ((x) == TIMER_TRGO_OC3REF) || \ - ((x) == TIMER_TRGO_OC4REF)) -#define IS_TIMER_IT(x) (((x) == TIMER_IT_UPDATE) || \ - ((x) == TIMER_IT_CC1) || \ - ((x) == TIMER_IT_CC2) || \ - ((x) == TIMER_IT_CC3) || \ - ((x) == TIMER_IT_CC4) || \ - ((x) == TIMER_IT_COM) || \ - ((x) == TIMER_IT_TRIGGER) || \ - ((x) == TIMER_IT_BREAK)) -#define IS_TIMER_DMA_REQ(x) (((x) == TIMER_DMA_UPDATE) || \ - ((x) == TIMER_DMA_CC1) || \ - ((x) == TIMER_DMA_CC2) || \ - ((x) == TIMER_DMA_CC3) || \ - ((x) == TIMER_DMA_CC4) || \ - ((x) == TIMER_DMA_COM) || \ - ((x) == TIMER_DMA_TRIGGER)) -#define IS_TIMER_FLAG(x) (((x) == TIMER_FLAG_UPDATE) || \ - ((x) == TIMER_FLAG_CC1) || \ - ((x) == TIMER_FLAG_CC2) || \ - ((x) == TIMER_FLAG_CC3) || \ - ((x) == TIMER_FLAG_CC4) || \ - ((x) == TIMER_FLAG_COM) || \ - ((x) == TIMER_FLAG_TRIGGER) || \ - ((x) == TIMER_FLAG_BREAK) || \ - ((x) == TIMER_FLAG_CC1OF) || \ - ((x) == TIMER_FLAG_CC2OF) || \ - ((x) == TIMER_FLAG_CC3OF) || \ - ((x) == TIMER_FLAG_CC4OF)) -/** - * @} - */ - -/** @addtogroup TIMER_Public_Functions - * @{ - */ -/** @addtogroup TIMER_Public_Functions_Group1 - * @{ - */ -/* Time Base functions */ -ald_status_t ald_timer_base_init(timer_handle_t *hperh); -void ald_timer_base_reset(timer_handle_t *hperh); -void ald_timer_base_start(timer_handle_t *hperh); -void ald_timer_base_stop(timer_handle_t *hperh); -void ald_timer_base_start_by_it(timer_handle_t *hperh); -void ald_timer_base_stop_by_it(timer_handle_t *hperh); -#ifdef ALD_DMA -ald_status_t ald_timer_base_start_by_dma(timer_handle_t *hperh, - uint16_t *buf, uint32_t len, uint8_t dma_ch); -void ald_timer_base_stop_by_dma(timer_handle_t *hperh); -#endif -/** - * @} - */ - -/** @addtogroup TIMER_Public_Functions_Group2 - * @{ - */ -/* Timer Output Compare functions */ -ald_status_t ald_timer_oc_init(timer_handle_t *hperh); -void ald_timer_oc_start(timer_handle_t *hperh, timer_channel_t ch); -void ald_timer_oc_stop(timer_handle_t *hperh, timer_channel_t ch); -void ald_timer_oc_start_by_it(timer_handle_t *hperh, timer_channel_t ch); -void ald_timer_oc_stop_by_it(timer_handle_t *hperh, timer_channel_t ch); -#ifdef ALD_DMA -ald_status_t ald_timer_oc_start_by_dma(timer_handle_t *hperh, timer_channel_t ch, - uint16_t *buf, uint32_t len, uint8_t dma_ch); -void ald_timer_oc_stop_by_dma(timer_handle_t *hperh, timer_channel_t ch); -#endif -/** - * @} - */ - -/** @addtogroup TIMER_Public_Functions_Group3 - * @{ - */ -/* Timer PWM functions */ -ald_status_t ald_timer_pwm_init(timer_handle_t *hperh); -void ald_timer_pwm_start(timer_handle_t *hperh, timer_channel_t ch); -void ald_timer_pwm_stop(timer_handle_t *hperh, timer_channel_t ch); -void ald_timer_pwm_start_by_it(timer_handle_t *hperh, timer_channel_t ch); -void ald_timer_pwm_stop_by_it(timer_handle_t *hperh, timer_channel_t ch); -void ald_timer_pwm_set_freq(timer_handle_t *hperh, uint16_t freq); -void ald_timer_pwm_set_duty(timer_handle_t *hperh, timer_channel_t ch, uint16_t duty); -void ald_timer_pwm_set_input(timer_handle_t *hperh, timer_channel_t ch); -#ifdef ALD_DMA -ald_status_t ald_timer_pwm_start_by_dma(timer_handle_t *hperh, timer_channel_t ch, - uint16_t *buf, uint32_t len, uint8_t dma_ch); -void ald_timer_pwm_stop_by_dma(timer_handle_t *hperh, timer_channel_t ch); -#endif -/** - * @} - */ - -/** @addtogroup TIMER_Public_Functions_Group4 - * @{ - */ -/* Timer Input Capture functions */ -ald_status_t ald_timer_ic_init(timer_handle_t *hperh); -void ald_timer_ic_start(timer_handle_t *hperh, timer_channel_t ch); -void ald_timer_ic_stop(timer_handle_t *hperh, timer_channel_t ch); -void ald_timer_ic_start_by_it(timer_handle_t *hperh, timer_channel_t ch); -void ald_timer_ic_stop_by_it(timer_handle_t *hperh, timer_channel_t ch); -#ifdef ALD_DMA -ald_status_t ald_timer_ic_start_by_dma(timer_handle_t *hperh, timer_channel_t ch, - uint16_t *buf, uint32_t len, uint8_t dma_ch); -void ald_timer_ic_stop_by_dma(timer_handle_t *hperh, timer_channel_t ch); -#endif -/** - * @} - */ - -/** @addtogroup TIMER_Public_Functions_Group5 - * @{ - */ -/* Timer One Pulse functions */ -ald_status_t ald_timer_one_pulse_init(timer_handle_t *hperh, timer_op_mode_t mode); -void ald_timer_one_pulse_start(timer_handle_t *hperh, timer_op_output_channel_t ch); -void ald_timer_one_pulse_stop(timer_handle_t *hperh, timer_op_output_channel_t ch); -void ald_timer_one_pulse_start_by_it(timer_handle_t *hperh, timer_op_output_channel_t ch); -void ald_timer_one_pulse_stop_by_it(timer_handle_t *hperh, timer_op_output_channel_t ch); -/** - * @} - */ - -/** @addtogroup TIMER_Public_Functions_Group6 - * @{ - */ -/* Timer encoder functions */ -ald_status_t ald_timer_encoder_init(timer_handle_t *hperh, timer_encoder_init_t *config); -void ald_timer_encoder_start(timer_handle_t *hperh, timer_channel_t ch); -void ald_timer_encoder_stop(timer_handle_t *hperh, timer_channel_t ch); -void ald_timer_encoder_start_by_it(timer_handle_t *hperh, timer_channel_t ch); -void ald_timer_encoder_stop_by_it(timer_handle_t *hperh, timer_channel_t ch); -#ifdef ALD_DMA -ald_status_t ald_timer_encoder_start_by_dma(timer_handle_t *hperh, timer_channel_t ch, - uint16_t *buf1, uint16_t *buf2, uint32_t len, - uint8_t dma_ch1, uint8_t dma_ch2); -void ald_timer_encoder_stop_by_dma(timer_handle_t *hperh, timer_channel_t ch); -#endif -/** - * @} - */ - -/** @addtogroup TIMER_Public_Functions_Group7 - * @{ - */ -/* Timer hall sensor functions */ -ald_status_t ald_timer_hall_sensor_init(timer_handle_t *hperh, timer_hall_sensor_init_t *config); -void ald_timer_hall_sensor_start(timer_handle_t *hperh); -void ald_timer_hall_sensor_stop(timer_handle_t *hperh); -void ald_timer_hall_sensor_start_by_it(timer_handle_t *hperh); -void ald_timer_hall_sensor_stop_by_it(timer_handle_t *hperh); -#ifdef ALD_DMA -ald_status_t ald_timer_hall_sensor_start_by_dma(timer_handle_t *hperh, - uint16_t *buf, uint32_t len, uint8_t dma_ch); -void ald_timer_hall_sensor_stop_by_dma(timer_handle_t *hperh); -#endif -/** - * @} - */ - -/** @addtogroup TIMER_Public_Functions_Group8 - * @{ - */ -/* Timer complementary output compare functions */ -void ald_timer_ocn_start(timer_handle_t *hperh, timer_channel_t ch); -void ald_timer_ocn_stop(timer_handle_t *hperh, timer_channel_t ch); -void ald_timer_ocn_start_by_it(timer_handle_t *hperh, timer_channel_t ch); -void ald_timer_ocn_stop_by_it(timer_handle_t *hperh, timer_channel_t ch); -#ifdef ALD_DMA -ald_status_t ald_timer_ocn_start_by_dma(timer_handle_t *hperh, - timer_channel_t ch, uint16_t *buf, uint32_t len, uint8_t dma_ch); -void ald_timer_ocn_stop_by_dma(timer_handle_t *hperh, timer_channel_t ch); -#endif -/** - * @} - */ - -/** @addtogroup TIMER_Public_Functions_Group9 - * @{ - */ -/* Timer complementary PWM functions */ -void ald_timer_pwmn_start(timer_handle_t *hperh, timer_channel_t ch); -void ald_timer_pwmn_stop(timer_handle_t *hperh, timer_channel_t ch); -void ald_timer_pwmn_start_by_it(timer_handle_t *hperh, timer_channel_t ch); -void ald_timer_pwmn_stop_by_it(timer_handle_t *hperh, timer_channel_t ch); -#ifdef ALD_DMA -ald_status_t ald_timer_pwmn_start_by_dma(timer_handle_t *hperh, - timer_channel_t ch, uint16_t *buf, uint32_t len, uint8_t dma_ch); -void ald_timer_pwmn_stop_by_dma(timer_handle_t *hperh, timer_channel_t ch); -#endif -/** - * @} - */ - -/** @addtogroup TIMER_Public_Functions_Group10 - * @{ - */ -/* Timer complementary one pulse functions */ -void ald_timer_one_pulse_n_start(timer_handle_t *hperh, timer_channel_t ch); -void ald_timer_one_pulse_n_stop(timer_handle_t *hperh, timer_channel_t ch); -void ald_timer_one_pulse_n_start_by_it(timer_handle_t *hperh, timer_channel_t ch); -void ald_timer_one_pulse_n_stop_by_it(timer_handle_t *hperh, timer_channel_t ch); -/** - * @} - */ - -/** @addtogroup TIMER_Public_Functions_Group11 - * @{ - */ -/* Control functions */ -ald_status_t ald_timer_oc_config_channel(timer_handle_t *hperh, timer_oc_init_t* config, timer_channel_t ch); -ald_status_t ald_timer_ic_config_channel(timer_handle_t *hperh, timer_ic_init_t* config, timer_channel_t ch); -ald_status_t ald_timer_one_pulse_config_channel(timer_handle_t *hperh, timer_one_pulse_init_t *config, - timer_channel_t ch_out, timer_channel_t ch_in); -ald_status_t ald_timer_config_oc_ref_clear(timer_handle_t *hperh, timer_clear_input_config_t *config, timer_channel_t ch); -ald_status_t ald_timer_config_clock_source(timer_handle_t *hperh, timer_clock_config_t *config); -ald_status_t ald_timer_config_ti1_input(timer_handle_t *hperh, uint32_t ti1_select); -ald_status_t ald_timer_slave_config_sync(timer_handle_t *hperh, timer_slave_config_t *config); -ald_status_t ald_timer_slave_config_sync_by_it(timer_handle_t *hperh, timer_slave_config_t *config); -ald_status_t ald_timer_generate_event(timer_handle_t *hperh, timer_event_source_t event); -uint32_t ald_timer_read_capture_value(timer_handle_t *hperh, timer_channel_t ch); -void ald_timer_set_output_mode(timer_handle_t *hperh, timer_oc_mode_t mode, timer_channel_t ch); -void ald_timer_com_change_config(timer_handle_t *hperh, timer_com_channel_config_t *config); -void ald_timer_com_event_config(timer_handle_t *hperh, timer_ts_t ts, type_func_t trgi); -void ald_timer_com_event_config_it(timer_handle_t *hperh, timer_ts_t ts, type_func_t trgi); -void ald_timer_break_dead_time_config(timer_handle_t *hperh, timer_break_dead_time_t *config); -void ald_timer_master_sync_config(timer_handle_t *hperh, timer_master_config_t *config); -void ald_timer_irq_handler(timer_handle_t *hperh); -void ald_timer_dma_req_config(timer_handle_t *hperh, timer_dma_req_t req, type_func_t state); -void ald_timer_interrupt_config(timer_handle_t *hperh, timer_it_t it, type_func_t state); -it_status_t ald_timer_get_it_status(timer_handle_t *hperh, timer_it_t it); -flag_status_t ald_timer_get_flag_status(timer_handle_t *hperh, timer_flag_t flag); -void ald_timer_clear_flag_status(timer_handle_t *hperh, timer_flag_t flag); -/** - * @} - */ - -/** @addtogroup TIMER_Public_Functions_Group12 - * @{ - */ -/* State functions */ -timer_state_t ald_timer_get_state(timer_handle_t *hperh); -/** - * @} - */ -/** - * @} - */ - -/** - * @} - */ -/** - * @} - */ - -#ifdef __cplusplus -} -#endif - -#endif /* __ALD_TIMER_H__ */ diff --git a/bsp/essemi/es32f0334/libraries/ES32F033x_ALD_StdPeriph_Driver/Include/ald_trng.h b/bsp/essemi/es32f0334/libraries/ES32F033x_ALD_StdPeriph_Driver/Include/ald_trng.h deleted file mode 100644 index 635cb1a90a..0000000000 --- a/bsp/essemi/es32f0334/libraries/ES32F033x_ALD_StdPeriph_Driver/Include/ald_trng.h +++ /dev/null @@ -1,203 +0,0 @@ -/** - ********************************************************************************* - * - * @file ald_trng.h - * @brief Header file of TRNG module driver. - * - * @version V1.0 - * @date 04 Dec 2017 - * @author AE Team - * @note - * - * Copyright (C) Shanghai Eastsoft Microelectronics Co. Ltd. All rights reserved. - * - ******************************************************************************** - */ - -#ifndef __ALD_TRNG_H__ -#define __ALD_TRNG_H__ - -#ifdef __cplusplus -extern "C" { -#endif - -#include "utils.h" - - -/** @addtogroup ES32FXXX_ALD - * @{ - */ - -/** @addtogroup TRNG - * @{ - */ - -/** @defgroup TRNG_Public_Types TRNG Public Types - * @{ - */ -/** - * @brief Data width - */ -typedef enum { - TRNG_DSEL_1B = 0x0U, /**< 1-bit */ - TRNG_DSEL_8B = 0x1U, /**< 8-bit */ - TRNG_DSEL_16B = 0x2U, /**< 16-bit */ - TRNG_DSEL_32B = 0x3U, /**< 32-bit */ -} trng_data_width_t; - -/** - * @brief seed type - */ -typedef enum { - TRNG_SEED_TYPE_0 = 0x0U, /**< Using 0 as seed */ - TRNG_SEED_TYPE_1 = 0x1U, /**< Using 1 as seed */ - TRNG_SEED_TYPE_LAST = 0x2U, /**< Using last seed */ - TRNG_SEED_TYPE_SEED = 0x3U, /**< Using value of register */ -} trng_seed_type_t; - -/** - * @brief TRNG init structure definition - */ -typedef struct { - trng_data_width_t data_width; /**< The width of data */ - trng_seed_type_t seed_type; /**< The seed type */ - uint32_t seed; /**< The value of seed */ - uint16_t t_start; /**< T(start) = T(trng) * 2 ^ (t_start + 1), T(start) > 1ms */ - uint8_t adjc; /**< Adjust parameter */ - type_func_t posten; /**< Data back handle function */ -} trng_init_t; - -/** - * @brief TRNG state structures definition - */ -typedef enum { - TRNG_STATE_RESET = 0x0U, /**< Peripheral is not initialized */ - TRNG_STATE_READY = 0x1U, /**< Peripheral Initialized and ready for use */ - TRNG_STATE_BUSY = 0x2U, /**< An internal process is ongoing */ - TRNG_STATE_ERROR = 0x4U, /**< Error */ -} trng_state_t; - -/** - * @brief State type - */ -typedef enum { - TRNG_STATUS_START = (1U << 0), /**< Start state */ - TRNG_STATUS_DAVLD = (1U << 1), /**< Data valid state */ - TRNG_STATUS_SERR = (1U << 2), /**< Error state */ -} trng_status_t; - -/** - * @brief Interrupt type - */ -typedef enum { - TRNG_IT_START = (1U << 0), /**< Start */ - TRNG_IT_DAVLD = (1U << 1), /**< Data valid */ - TRNG_IT_SERR = (1U << 2), /**< Error */ -} trng_it_t; - -/** - * @brief Interrupt flag type - */ -typedef enum { - TRNG_IF_START = (1U << 0), /**< Start */ - TRNG_IF_DAVLD = (1U << 1), /**< Data valid */ - TRNG_IF_SERR = (1U << 2), /**< Error */ -} trng_flag_t; - -/** - * @brief TRNG Handle Structure definition - */ -typedef struct trng_handle_s { - TRNG_TypeDef *perh; /**< Register base address */ - trng_init_t init; /**< TRNG required parameters */ - uint32_t data; /**< result data */ - lock_state_t lock; /**< Locking object */ - trng_state_t state; /**< TRNG operation state */ - - void (*trng_cplt_cbk)(struct trng_handle_s *arg); /**< Trng completed callback */ - void (*err_cplt_cbk)(struct trng_handle_s *arg); /**< Trng error callback */ - void (*init_cplt_cbk)(struct trng_handle_s *arg); /**< Trng init completed callback */ -} trng_handle_t; -/** - * @} - */ - -/** @defgroup TRNG_Public_Macros TRNG Public Macros - * @{ - */ -#define TRNG_ENABLE() (SET_BIT(TRNG->CR, TRNG_CR_TRNGEN_MSK)) -#define TRNG_DISABLE() (CLEAR_BIT(TRNG->CR, TRNG_CR_TRNGEN_MSK)) -#define TRNG_ADJM_ENABLE() (SET_BIT(TRNG->CR, TRNG_CR_ADJM_MSK)) -#define TRNG_ADJM_DISABLE() (CLEAR_BIT(TRNG->CR, TRNG_CR_ADJM_MSK)) -/** - * @} - */ - -/** - * @defgroup TRNG_Private_Macros TRNG Private Macros - * @{ - */ -#define IS_TRNG_DATA_WIDTH(x) (((x) == TRNG_DSEL_1B) || \ - ((x) == TRNG_DSEL_8B) || \ - ((x) == TRNG_DSEL_16B) || \ - ((x) == TRNG_DSEL_32B)) -#define IS_TRNG_SEED_TYPE(x) (((x) == TRNG_SEED_TYPE_0) || \ - ((x) == TRNG_SEED_TYPE_1) || \ - ((x) == TRNG_SEED_TYPE_LAST) || \ - ((x) == TRNG_SEED_TYPE_SEED)) -#define IS_TRNG_STATUS(x) (((x) == TRNG_STATUS_START) || \ - ((x) == TRNG_STATUS_DAVLD) || \ - ((x) == TRNG_STATUS_SERR)) -#define IS_TRNG_IT(x) (((x) == TRNG_IT_START) || \ - ((x) == TRNG_IT_DAVLD) || \ - ((x) == TRNG_IT_SERR)) -#define IS_TRNG_FLAG(x) (((x) == TRNG_IF_START) || \ - ((x) == TRNG_IF_DAVLD) || \ - ((x) == TRNG_IF_SERR)) -#define IS_TRNG_ADJC(x) ((x) < 4) -#define IS_TRNG_T_START(x) ((x) < 8) -/** - * @} - */ - -/** @addtogroup TRNG_Public_Functions - * @{ - */ -/** @addtogroup TRNG_Public_Functions_Group1 - * @{ - */ -/* Initialization functions */ -extern ald_status_t ald_trng_init(trng_handle_t *hperh); -/** - * @} - */ -/** @addtogroup TRNG_Public_Functions_Group2 - * @{ - */ -/* Control functions */ -extern uint32_t ald_trng_get_result(trng_handle_t *hperh); -extern void ald_trng_interrupt_config(trng_handle_t *hperh, trng_it_t it, type_func_t state); -extern flag_status_t ald_trng_get_status(trng_handle_t *hperh, trng_status_t status); -extern it_status_t ald_trng_get_it_status(trng_handle_t *hperh, trng_it_t it); -extern flag_status_t ald_trng_get_flag_status(trng_handle_t *hperh, trng_flag_t flag); -extern void ald_trng_clear_flag_status(trng_handle_t *hperh, trng_flag_t flag); -extern void ald_trng_irq_handler(trng_handle_t *hperh); -/** - * @} - */ -/** - * @} - */ - -/** - * @} - */ - -/** - * @} - */ -#ifdef __cplusplus -} -#endif - -#endif /* __ALD_TRNG_H__ */ diff --git a/bsp/essemi/es32f0334/libraries/ES32F033x_ALD_StdPeriph_Driver/Include/ald_tsense.h b/bsp/essemi/es32f0334/libraries/ES32F033x_ALD_StdPeriph_Driver/Include/ald_tsense.h deleted file mode 100644 index 410dcb7ff6..0000000000 --- a/bsp/essemi/es32f0334/libraries/ES32F033x_ALD_StdPeriph_Driver/Include/ald_tsense.h +++ /dev/null @@ -1,199 +0,0 @@ -/** - ********************************************************************************* - * - * @file ald_tsense.h - * @brief Header file of TSENSE module driver. - * - * @version V1.0 - * @date 15 Dec 2017 - * @author AE Team - * @note - * - * Copyright (C) Shanghai Eastsoft Microelectronics Co. Ltd. All rights reserved. - * - ******************************************************************************** - */ - -#ifndef __ALD_TSENSE_H__ -#define __ALD_TSENSE_H__ - -#ifdef __cplusplus -extern "C" { -#endif - -#include "utils.h" - - -/** @addtogroup ES32FXXX_ALD - * @{ - */ - -/** @addtogroup TSENSE - * @{ - */ - -/** @defgroup TSENSE_Public_Macros TSENSE Public Macros - * @{ - */ -#define TSENSE_LOCK() (WRITE_REG(TSENSE->WPR, 0x0U)) -#define TSENSE_UNLOCK() (WRITE_REG(TSENSE->WPR, 0xA55A9669U)) -#define TSENSE_ENABLE() \ -do { \ - TSENSE_UNLOCK(); \ - SET_BIT(TSENSE->CR, TSENSE_CR_EN_MSK); \ - TSENSE_LOCK(); \ -} while (0) -#define TSENSE_DISABLE() \ -do { \ - TSENSE_UNLOCK(); \ - CLEAR_BIT(TSENSE->CR, TSENSE_CR_EN_MSK); \ - TSENSE_LOCK(); \ -} while (0) -#define TSENSE_REQ_ENABLE() \ -do { \ - TSENSE_UNLOCK(); \ - SET_BIT(TSENSE->CR, TSENSE_CR_REQEN_MSK); \ - TSENSE_LOCK(); \ -} while (0) -#define TSENSE_REQ_DISABLE() \ -do { \ - TSENSE_UNLOCK(); \ - CLEAR_BIT(TSENSE->CR, TSENSE_CR_REQEN_MSK); \ - TSENSE_LOCK(); \ -} while (0) -#define TSENSE_CTN_ENABLE() \ -do { \ - TSENSE_UNLOCK(); \ - SET_BIT(TSENSE->CR, TSENSE_CR_CTN_MSK); \ - TSENSE_LOCK(); \ -} while (0) -#define TSENSE_CTN_DISABLE() \ -do { \ - TSENSE_UNLOCK(); \ - CLEAR_BIT(TSENSE->CR, TSENSE_CR_CTN_MSK); \ - TSENSE_LOCK(); \ -} while (0) -#define TSENSE_RESET() \ -do { \ - TSENSE_UNLOCK(); \ - SET_BIT(TSENSE->CR, TSENSE_CR_RST_MSK); \ - TSENSE_LOCK(); \ -} while (0) -#define TSENSE_LTGR_WR(data) \ -do { \ - TSENSE_UNLOCK(); \ - WRITE_REG(TSENSE->LTGR, (data)); \ - TSENSE_LOCK(); \ -} while (0) -#define TSENSE_HTGR_WR(data) \ -do { \ - TSENSE_UNLOCK(); \ - WRITE_REG(TSENSE->HTGR, (data)); \ - TSENSE_LOCK(); \ -} while (0) -#define TSENSE_TBDR_WR(data) \ -do { \ - TSENSE_UNLOCK(); \ - WRITE_REG(TSENSE->TBDR, (data)); \ - TSENSE_LOCK(); \ -} while (0) -#define TSENSE_TCALBDR_WR(data) \ -do { \ - TSENSE_UNLOCK(); \ - WRITE_REG(TSENSE->TCALBDR, (data)); \ - TSENSE_LOCK(); \ -} while (0) -/** - * @} - */ - -/** @defgroup TSENSE_Public_Types TSENSE Public Types - * @{ - */ -/** - * @brief Temperature update time - */ -typedef enum { - TSENSE_UPDATE_CYCLE_3 = 0x3U, /**< 3 Cycles */ - TSENSE_UPDATE_CYCLE_4 = 0x4U, /**< 4 Cycles */ - TSENSE_UPDATE_CYCLE_5 = 0x5U, /**< 5 Cycles */ - TSENSE_UPDATE_CYCLE_6 = 0x6U, /**< 6 Cycles */ - TSENSE_UPDATE_CYCLE_7 = 0x7U, /**< 7 Cycles */ -} tsense_update_cycle_t; - -/** - * @brief Temperature output mode - */ -typedef enum { - TSENSE_OUTPUT_MODE_200 = 0x0U, /**< 200 cycles update one temperature */ - TSENSE_OUTPUT_MODE_400 = 0x1U, /**< 400 cycles update one temperature */ - TSENSE_OUTPUT_MODE_800 = 0x2U, /**< 800 cycles update one temperature */ - TSENSE_OUTPUT_MODE_1600 = 0x3U, /**< 1600 cycles update one temperature */ - TSENSE_OUTPUT_MODE_3200 = 0x4U, /**< 3200 cycles update one temperature */ -} tsense_output_mode_t; - -/** - * @brief Source select - */ -typedef enum { - TSENSE_SOURCE_LOSC = 0x0U, /**< LOSC */ - TSENSE_SOURCE_LRC = 0x1U, /**< LRC */ -} tsense_source_sel_t; - - -/** - * @brief Define callback function type - */ -typedef void (*tsense_cbk)(uint16_t value, ald_status_t status); -/** - * @} - */ - -/** - * @defgroup TSENSE_Private_Macros TSENSE Private Macros - * @{ - */ -#define IS_TSENSE_SOURCE_SEL(x) (((x) == TSENSE_SOURCE_LOSC) || \ - ((x) == TSENSE_SOURCE_LRC)) -/** - * @} - */ - -/** @addtogroup TSENSE_Public_Functions - * @{ - */ -/** @addtogroup TSENSE_Public_Functions_Group1 - * @{ - */ -/* Initialization functions */ -extern void ald_tsense_init(void); -extern void ald_tsense_source_select(tsense_source_sel_t sel); -/** - * @} - */ -/** @addtogroup TSENSE_Public_Functions_Group2 - * @{ - */ -/* Control functions */ -extern ald_status_t ald_tsense_get_value(uint16_t *tsense); -extern void ald_tsense_get_value_by_it(tsense_cbk cbk); -extern void ald_tsense_irq_handler(void); -/** - * @} - */ -/** - * @} - */ - -/** - * @} - */ - -/** - * @} - */ -#ifdef __cplusplus -} -#endif - -#endif /* __ALD_TSENSE_H__ */ diff --git a/bsp/essemi/es32f0334/libraries/ES32F033x_ALD_StdPeriph_Driver/Include/ald_uart.h b/bsp/essemi/es32f0334/libraries/ES32F033x_ALD_StdPeriph_Driver/Include/ald_uart.h deleted file mode 100644 index 10a351ca19..0000000000 --- a/bsp/essemi/es32f0334/libraries/ES32F033x_ALD_StdPeriph_Driver/Include/ald_uart.h +++ /dev/null @@ -1,461 +0,0 @@ -/** - ********************************************************************************* - * - * @file ald_uart.h - * @brief Header file of UART module library. - * - * @version V1.0 - * @date 21 Nov 2017 - * @author AE Team - * @note - * - * Copyright (C) Shanghai Eastsoft Microelectronics Co. Ltd. All rights reserved. - * - ********************************************************************************* - */ - -#ifndef __ALD_UART_H__ -#define __ALD_UART_H__ - -#ifdef __cplusplus -extern "C" { -#endif - -#include "utils.h" -#include "ald_dma.h" - - -/** @addtogroup ES32FXXX_ALD - * @{ - */ - -/** @addtogroup UART - * @{ - */ - -/** - * @defgroup UART_Public_Macros UART Public Macros - * @{ - */ -#define UART_RX_ENABLE(hperh) (SET_BIT((hperh)->perh->LCR, UART_LCR_RXEN_MSK)) -#define UART_RX_DISABLE(hperh) (CLEAR_BIT((hperh)->perh->LCR, UART_LCR_RXEN_MSK)) -#define UART_BRR_WRITE_ENABLE(hperh) (SET_BIT((hperh)->perh->LCR, UART_LCR_BRWEN_MSK)) -#define UART_BRR_WRITE_DISABLE(hperh) (CLEAR_BIT((hperh)->perh->LCR, UART_LCR_BRWEN_MSK)) -#define UART_RX_TIMEOUT_ENABLE(hperh) (SET_BIT((hperh)->perh->LCR, UART_LCR_RTOEN_MSK)) -#define UART_RX_TIMEOUT_DISABLE(hperh) (CLEAR_BIT((hperh)->perh->LCR, UART_LCR_RTOEN_MSK)) -#define UART_MSB_FIRST_ENABLE(hperh) (SET_BIT((hperh)->perh->LCR, UART_LCR_MSBFIRST_MSK)) -#define UART_MSB_FIRST_DISABLE(hperh) (CLEAR_BIT((hperh)->perh->LCR, UART_LCR_MSBFIRST_MSK)) -#define UART_DATA_INV_ENABLE(hperh) (SET_BIT((hperh)->perh->LCR, UART_LCR_DATAINV_MSK)) -#define UART_DATA_INV_DISABLE(hperh) (CLEAR_BIT((hperh)->perh->LCR, UART_LCR_DATAINV_MSK)) -#define UART_RX_INV_ENABLE(hperh) (SET_BIT((hperh)->perh->LCR, UART_LCR_RXINV_MSK)) -#define UART_RX_INV_DISABLE(hperh) (CLEAR_BIT((hperh)->perh->LCR, UART_LCR_RXINV_MSK)) -#define UART_TX_INV_ENABLE(hperh) (SET_BIT((hperh)->perh->LCR, UART_LCR_TXINV_MSK)) -#define UART_TX_INV_DISABLE(hperh) (CLEAR_BIT((hperh)->perh->LCR, UART_LCR_TXINV_MSK)) -#define UART_TX_RX_SWAP_ENABLE(hperh) (SET_BIT((hperh)->perh->LCR, UART_LCR_SWAP_MSK)) -#define UART_TX_RX_SWAP_DISABLE(hperh) (CLEAR_BIT((hperh)->perh->LCR, UART_LCR_SWAP_MSK)) -#define UART_HDSEL_ENABLE(hperh) (SET_BIT((hperh)->perh->MCR, UART_MCR_HDSEL_MSK)) -#define UART_HDSEL_DISABLE(hperh) (CLEAR_BIT((hperh)->perh->MCR, UART_MCR_HDSEL_MSK)) -#define UART_FIFO_TX_RESET(hperh) (SET_BIT((hperh)->perh->FCR, UART_FCR_TFRST_MSK)) -#define UART_FIFO_RX_RESET(hperh) (SET_BIT((hperh)->perh->FCR, UART_FCR_RFRST_MSK)) -#define UART_LPBMOD_ENABLE(hperh) (SET_BIT((hperh)->perh->MCR, UART_MCR_LBEN_MSK)) -#define UART_LPBMOD_DISABLE(hperh) (CLEAR_BIT((hperh)->perh->MCR, UART_MCR_LBEN_MSK)) -#define UART_AUTOBR_ENABLE(hperh) (SET_BIT((hperh)->perh->MCR, UART_MCR_ABREN_MSK)) -#define UART_AUTOBR_DISABLE(hperh) (CLEAR_BIT((hperh)->perh->MCR, UART_MCR_ABREN_MSK)) -#define UART_AUTOBR_RESTART(hperh) (SET_BIT((hperh)->perh->MCR, UART_MCR_ABRRS_MSK)) -#define UART_GET_BRR_VALUE(hperh) (READ_REG((hperh)->perh->BRR)) -#define UART_SET_TIMEOUT_VALUE(x, y) (MODIFY_REG((x)->perh->RTOR, UART_RTOR_RTO_MSK, (y) << UART_RTOR_RTO_POSS)) -/** - * @} - */ - -/** @defgroup UART_Public_Types UART Public Types - * @{ - */ -/** - * @brief UART word length - */ -typedef enum { - UART_WORD_LENGTH_5B = 0x0U, /**< 5-bits */ - UART_WORD_LENGTH_6B = 0x1U, /**< 6-bits */ - UART_WORD_LENGTH_7B = 0x2U, /**< 7-bits */ - UART_WORD_LENGTH_8B = 0x3U, /**< 8-bits */ -} uart_word_length_t; - -/** - * @brief UART stop bits - */ -typedef enum { - UART_STOP_BITS_1 = 0x0U, /**< 1-bits */ - UART_STOP_BITS_2 = 0x1U, /**< 2-bits */ - UART_STOP_BITS_0_5 = 0x0U, /**< 0.5-bits, using smartcard mode */ - UART_STOP_BITS_1_5 = 0x1U, /**< 1.5-bits, using smartcard mode */ -} uart_stop_bits_t; - -/** - * @brief UART parity - */ -typedef enum { - UART_PARITY_NONE = 0x0U, /**< Not parity */ - UART_PARITY_ODD = 0x1U, /**< Odd parity */ - UART_PARITY_EVEN = 0x3U, /**< Even parity */ -} uart_parity_t; - -/** - * @brief UART mode - */ -typedef enum { - UART_MODE_UART = 0x0U, /**< UART */ - UART_MODE_LIN = 0x1U, /**< LIN */ - UART_MODE_IrDA = 0x2U, /**< IrDA */ - UART_MODE_RS485 = 0x3U, /**< RS485 */ - UART_MODE_HDSEL = 0x4U, /**< Single-wire half-duplex */ -} uart_mode_t; - -/** - * @brief UART hardware flow control - */ -typedef enum { - UART_HW_FLOW_CTL_DISABLE = 0x0U, /**< Auto-flow-control disable */ - UART_HW_FLOW_CTL_ENABLE = 0x1U, /**< Auto-flow-control enable */ -} uart_hw_flow_ctl_t; - -/** - * @brief ALD UART state - */ -typedef enum { - UART_STATE_RESET = 0x00U, /**< Peripheral is not initialized */ - UART_STATE_READY = 0x01U, /**< Peripheral Initialized and ready for use */ - UART_STATE_BUSY = 0x02U, /**< an internal process is ongoing */ - UART_STATE_BUSY_TX = 0x11U, /**< Data Transmission process is ongoing */ - UART_STATE_BUSY_RX = 0x21U, /**< Data Reception process is ongoing */ - UART_STATE_BUSY_TX_RX = 0x31U, /**< Data Transmission Reception process is ongoing */ - UART_STATE_TIMEOUT = 0x03U, /**< Timeout state */ - UART_STATE_ERROR = 0x04U, /**< Error */ -} uart_state_t; - -/** - * @brief UART error codes - */ -typedef enum { - UART_ERROR_NONE = ((uint32_t)0x00U), /**< No error */ - UART_ERROR_PE = ((uint32_t)0x01U), /**< Parity error */ - UART_ERROR_NE = ((uint32_t)0x02U), /**< Noise error */ - UART_ERROR_FE = ((uint32_t)0x04U), /**< frame error */ - UART_ERROR_ORE = ((uint32_t)0x08U), /**< Overrun error */ - UART_ERROR_DMA = ((uint32_t)0x10U), /**< DMA transfer error */ -} uart_error_t; - -/** - * @brief UART init structure definition - */ -typedef struct { - uint32_t baud; /**< Specifies the uart communication baud rate */ - uart_word_length_t word_length; /**< Specifies the number of data bits transmitted or received in a frame */ - uart_stop_bits_t stop_bits; /**< Specifies the number of stop bits transmitted */ - uart_parity_t parity; /**< Specifies the parity mode */ - uart_mode_t mode; /**< Specifies uart mode */ - uart_hw_flow_ctl_t fctl; /**< Specifies wether the hardware flow control mode is enabled or disabled */ -} uart_init_t; - -/** - * @brief UART handle structure definition - */ -typedef struct uart_handle_s { - UART_TypeDef *perh; /**< UART registers base address */ - uart_init_t init; /**< UART communication parameters */ - uint8_t *tx_buf; /**< Pointer to UART Tx transfer Buffer */ - uint16_t tx_size; /**< UART Tx Transfer size */ - uint16_t tx_count; /**< UART Tx Transfer Counter */ - uint8_t *rx_buf; /**< Pointer to UART Rx transfer Buffer */ - uint16_t rx_size; /**< UART Rx Transfer size */ - uint16_t rx_count; /**< UART Rx Transfer Counter */ -#ifdef ALD_DMA - dma_handle_t hdmatx; /**< UART Tx DMA Handle parameters */ - dma_handle_t hdmarx; /**< UART Rx DMA Handle parameters */ -#endif - lock_state_t lock; /**< Locking object */ - uart_state_t state; /**< UART communication state */ - uart_error_t err_code; /**< UART Error code */ - - void (*tx_cplt_cbk)(struct uart_handle_s *arg); /**< Tx completed callback */ - void (*rx_cplt_cbk)(struct uart_handle_s *arg); /**< Rx completed callback */ - void (*error_cbk)(struct uart_handle_s *arg); /**< error callback */ -} uart_handle_t; - -/** - * @brief UART RS485 configure structure definition - */ -typedef struct { - type_func_t normal; /**< Normal mode */ - type_func_t dir; /**< Auto-direction mode */ - type_func_t invert; /**< Address detection invert */ - uint8_t addr; /**< Address for compare */ -} uart_rs485_config_t; - -/** - * @brief LIN detection break length - */ -typedef enum { - LIN_BREAK_LEN_10B = 0x0U, /**< 10-bit break */ - LIN_BREAK_LEN_11B = 0x1U, /**< 11-bit break */ -} uart_lin_break_len_t; - -/** - * @brief UART TXFIFO size - */ -typedef enum { - UART_TXFIFO_EMPTY = 0x0U, /**< Empty */ - UART_TXFIFO_2BYTE = 0x1U, /**< 2-Bytes */ - UART_TXFIFO_4BYTE = 0x2U, /**< 4-Bytes */ - UART_TXFIFO_8BYTE = 0x3U, /**< 8-Bytes */ -} uart_txfifo_t; - -/** - * @brief UART RXFIFO size - */ -typedef enum { - UART_RXFIFO_1BYTE = 0x0U, /**< 1-Byte */ - UART_RXFIFO_4BYTE = 0x1U, /**< 4-Bytes */ - UART_RXFIFO_8BYTE = 0x2U, /**< 8-Bytes */ - UART_RXFIFO_14BYTE = 0x3U, /**< 14-Bytes */ -} uart_rxfifo_t; - -/** - * @brief UART auto-baud mode - */ -typedef enum { - UART_ABRMOD_1_TO_0 = 0x0U, /**< Detect bit0:1, bit1:0 */ - UART_ABRMOD_1 = 0x1U, /**< Detect bit0:1 */ - UART_ABRMOD_0_TO_1 = 0x2U, /**< Detect bit0:0, bit1:1 */ -} uart_auto_baud_mode_t; - -/** - * @brief UART status types - */ -typedef enum { - UART_STATUS_DR = (1U << 0), /**< Data ready */ - UART_STATUS_OE = (1U << 1), /**< Overrun error */ - UART_STATUS_PE = (1U << 2), /**< Parity error */ - UART_STATUS_FE = (1U << 3), /**< Framing error */ - UART_STATUS_BI = (1U << 4), /**< Break interrupt */ - UART_STATUS_TBEM = (1U << 5), /**< Transmit buffer empty */ - UART_STATUS_TEM = (1U << 6), /**< Transmitter empty */ - UART_STATUS_RFE = (1U << 7), /**< Reveiver FIFO data error */ - UART_STATUS_BUSY = (1U << 8), /**< UART busy */ - UART_STATUS_TFNF = (1U << 9), /**< Transmit FIFO not full */ - UART_STATUS_TFEM = (1U << 10), /**< Transmit FIFO not empty */ - UART_STATUS_RFNE = (1U << 11), /**< Receive FIFO not empty */ - UART_STATUS_RFF = (1U << 12), /**< Receive FIFO full */ - UART_STATUS_DCTS = (1U << 14), /**< Delta clear to send */ - UART_STATUS_CTS = (1U << 15), /**< Clear to send */ -} uart_status_t; - -/** - * @brief UART interrupt types - */ -typedef enum { - UART_IT_RXRD = (1U << 0), /**< Receive data available */ - UART_IT_TXS = (1U << 1), /**< Tx empty status */ - UART_IT_RXS = (1U << 2), /**< Rx line status */ - UART_IT_MDS = (1U << 3), /**< Modem status */ - UART_IT_RTO = (1U << 4), /**< Receiver timeout */ - UART_IT_BZ = (1U << 5), /**< Busy status */ - UART_IT_ABE = (1U << 6), /**< Auto-baud rate detection end */ - UART_IT_ABTO = (1U << 7), /**< Auto-baud rate detection timeout */ - UART_IT_LINBK = (1U << 8), /**< Lin break detection */ - UART_IT_TC = (1U << 9), /**< Transmission complete */ - UART_IT_EOB = (1U << 10), /**< End of block */ - UART_IT_CM = (1U << 11), /**< Character match */ -} uart_it_t; - -/** - * @brief UART flags types - */ -typedef enum { - UART_IF_RXRD = (1U << 0), /**< Receive data available */ - UART_IF_TXS = (1U << 1), /**< Tx empty status */ - UART_IF_RXS = (1U << 2), /**< Rx line status */ - UART_IF_MDS = (1U << 3), /**< Modem status */ - UART_IF_RTO = (1U << 4), /**< Receiver timeout */ - UART_IF_BZ = (1U << 5), /**< Busy status */ - UART_IF_ABE = (1U << 6), /**< Auto-baud rate detection end */ - UART_IF_ABTO = (1U << 7), /**< Auto-baud rate detection timeout */ - UART_IF_LINBK = (1U << 8), /**< Lin break detection */ - UART_IF_TC = (1U << 9), /**< Transmission complete */ - UART_IF_EOB = (1U << 10), /**< End of block */ - UART_IF_CM = (1U << 11), /**< Character match */ -} uart_flag_t; -/** - * @} - */ - -/** @defgroup UART_Private_Macros UART Private Macros - * @{ - */ -#define IS_UART_ALL(x) (((x) == UART0) || \ - ((x) == UART1) || \ - ((x) == UART2) || \ - ((x) == UART3)) -#define IS_UART_WORD_LENGTH(x) (((x) == UART_WORD_LENGTH_5B) || \ - ((x) == UART_WORD_LENGTH_6B) || \ - ((x) == UART_WORD_LENGTH_7B) || \ - ((x) == UART_WORD_LENGTH_8B)) -#define IS_UART_STOPBITS(x) (((x) == UART_STOP_BITS_1) || \ - ((x) == UART_STOP_BITS_2) || \ - ((x) == UART_STOP_BITS_0_5) || \ - ((x) == UART_STOP_BITS_1_5)) -#define IS_UART_PARITY(x) (((x) == UART_PARITY_NONE) || \ - ((x) == UART_PARITY_ODD) || \ - ((x) == UART_PARITY_EVEN)) -#define IS_UART_MODE(x) (((x) == UART_MODE_UART) || \ - ((x) == UART_MODE_LIN) || \ - ((x) == UART_MODE_IrDA) || \ - ((x) == UART_MODE_RS485) || \ - ((x) == UART_MODE_HDSEL)) -#define IS_UART_HARDWARE_FLOW_CONTROL(x) \ - (((x) == UART_HW_FLOW_CTL_DISABLE) || \ - ((x) == UART_HW_FLOW_CTL_ENABLE)) -#define IS_UART_LIN_BREAK_LEN(x) (((x) == LIN_BREAK_LEN_10B) || \ - ((x) == LIN_BREAK_LEN_11B)) -#define IS_UART_TXFIFO_TYPE(x) (((x) == UART_TXFIFO_EMPTY) || \ - ((x) == UART_TXFIFO_2BYTE) || \ - ((x) == UART_TXFIFO_4BYTE) || \ - ((x) == UART_TXFIFO_8BYTE)) -#define IS_UART_RXFIFO_TYPE(x) (((x) == UART_RXFIFO_1BYTE) || \ - ((x) == UART_RXFIFO_4BYTE) || \ - ((x) == UART_RXFIFO_8BYTE) || \ - ((x) == UART_RXFIFO_14BYTE)) -#define IS_UART_AUTO_BAUD_MODE(x) (((x) == UART_ABRMOD_1_TO_0) || \ - ((x) == UART_ABRMOD_1) || \ - ((x) == UART_ABRMOD_0_TO_1)) -#define IS_UART_STATUS(x) (((x) == UART_STATUS_DR) || \ - ((x) == UART_STATUS_OE) || \ - ((x) == UART_STATUS_PE) || \ - ((x) == UART_STATUS_FE) || \ - ((x) == UART_STATUS_BI) || \ - ((x) == UART_STATUS_TBEM) || \ - ((x) == UART_STATUS_TEM) || \ - ((x) == UART_STATUS_RFE) || \ - ((x) == UART_STATUS_BUSY) || \ - ((x) == UART_STATUS_TFNF) || \ - ((x) == UART_STATUS_TFEM) || \ - ((x) == UART_STATUS_RFNE) || \ - ((x) == UART_STATUS_RFF) || \ - ((x) == UART_STATUS_DCTS) || \ - ((x) == UART_STATUS_CTS)) -#define IS_UART_IT(x) (((x) == UART_IT_RXRD) || \ - ((x) == UART_IT_TXS) || \ - ((x) == UART_IT_RXS) || \ - ((x) == UART_IT_MDS) || \ - ((x) == UART_IT_RTO) || \ - ((x) == UART_IT_BZ) || \ - ((x) == UART_IT_ABE) || \ - ((x) == UART_IT_ABTO) || \ - ((x) == UART_IT_LINBK) || \ - ((x) == UART_IT_TC) || \ - ((x) == UART_IT_EOB) || \ - ((x) == UART_IT_CM)) -#define IS_UART_IF(x) (((x) == UART_IF_RXRD) || \ - ((x) == UART_IF_TXS) || \ - ((x) == UART_IF_RXS) || \ - ((x) == UART_IF_MDS) || \ - ((x) == UART_IF_RTO) || \ - ((x) == UART_IF_BZ) || \ - ((x) == UART_IF_ABE) || \ - ((x) == UART_IF_ABTO) || \ - ((x) == UART_IF_LINBK) || \ - ((x) == UART_IF_TC) || \ - ((x) == UART_IF_EOB) || \ - ((x) == UART_IF_CM)) -#define IS_UART_BAUDRATE(x) (((x) > 0) && ((x) < 0x44AA21)) -#define IS_UART_DATA(x) ((x) <= 0x1FF) - -#define UART_STATE_TX_MASK (1U << 4) -#define UART_STATE_RX_MASK (1U << 5) -/** - * @} - */ - -/** @addtogroup UART_Public_Functions - * @{ - */ - -/** @addtogroup UART_Public_Functions_Group1 - * @{ - */ -/* Initialization functions */ -void ald_uart_init(uart_handle_t *hperh); -void ald_uart_reset(uart_handle_t *hperh); -void ald_uart_rs485_config(uart_handle_t *hperh, uart_rs485_config_t *config); -/** - * @} - */ - -/** @addtogroup UART_Public_Functions_Group2 - * @{ - */ -/* IO operation functions */ -ald_status_t ald_uart_send(uart_handle_t *hperh, uint8_t *buf, uint16_t size, uint32_t timeout); -ald_status_t ald_uart_recv(uart_handle_t *hperh, uint8_t *buf, uint16_t size, uint32_t timeout); -ald_status_t ald_uart_send_by_it(uart_handle_t *hperh, uint8_t *buf, uint16_t size); -ald_status_t ald_uart_recv_by_it(uart_handle_t *hperh, uint8_t *buf, uint16_t size); -#ifdef ALD_DMA -ald_status_t ald_uart_send_by_dma(uart_handle_t *hperh, uint8_t *buf, uint16_t size, uint8_t channel); -ald_status_t ald_uart_recv_by_dma(uart_handle_t *hperh, uint8_t *buf, uint16_t size, uint8_t channel); -ald_status_t ald_uart_dma_pause(uart_handle_t *hperh); -ald_status_t ald_uart_dma_resume(uart_handle_t *hperh); -ald_status_t ald_uart_dma_stop(uart_handle_t *hperh); -#endif -void ald_uart_irq_handler(uart_handle_t *hperh); -/** - * @} - */ - -/** @addtogroup UART_Public_Functions_Group3 - * @{ - */ -/* Peripheral Control functions */ -void ald_uart_interrupt_config(uart_handle_t *hperh, uart_it_t it, type_func_t state); -void ald_uart_dma_req_config(uart_handle_t *hperh, type_func_t state); -void ald_uart_tx_fifo_config(uart_handle_t *hperh, uart_txfifo_t config); -void ald_uart_rx_fifo_config(uart_handle_t *hperh, uart_rxfifo_t config); -void ald_uart_lin_send_break(uart_handle_t *hperh); -void ald_uart_lin_detect_break_len_config(uart_handle_t *hperh, uart_lin_break_len_t len); -void ald_uart_auto_baud_config(uart_handle_t *hperh, uart_auto_baud_mode_t mode); -ald_status_t ald_uart_rs485_send_addr(uart_handle_t *hperh, uint16_t addr, uint32_t timeout); -it_status_t ald_uart_get_it_status(uart_handle_t *hperh, uart_it_t it); -flag_status_t ald_uart_get_status(uart_handle_t *hperh, uart_status_t status); -flag_status_t ald_uart_get_flag_status(uart_handle_t *hperh, uart_flag_t flag); -flag_status_t ald_uart_get_mask_flag_status(uart_handle_t *hperh, uart_flag_t flag); -void ald_uart_clear_flag_status(uart_handle_t *hperh, uart_flag_t flag); -/** - * @} - */ - -/** @addtogroup UART_Public_Functions_Group4 - * @{ - */ -/* Peripheral State and Errors functions */ -uart_state_t ald_uart_get_state(uart_handle_t *hperh); -uint32_t ald_uart_get_error(uart_handle_t *hperh); -/** - * @} - */ - -/** - * @} - */ - -/** - * @} - */ - -/** - * @} - */ - -#ifdef __cplusplus -} -#endif - -#endif /* __ALD_UART_H__ */ diff --git a/bsp/essemi/es32f0334/libraries/ES32F033x_ALD_StdPeriph_Driver/Include/ald_usart.h b/bsp/essemi/es32f0334/libraries/ES32F033x_ALD_StdPeriph_Driver/Include/ald_usart.h deleted file mode 100644 index 4f30e2c2a4..0000000000 --- a/bsp/essemi/es32f0334/libraries/ES32F033x_ALD_StdPeriph_Driver/Include/ald_usart.h +++ /dev/null @@ -1,560 +0,0 @@ -/** - ********************************************************************************* - * - * @file ald_usart.h - * @brief Header file of USART module library. - * - * @version V1.0 - * @date 16 Apr 2017 - * @author AE Team - * @note - * - * Copyright (C) Shanghai Eastsoft Microelectronics Co. Ltd. All rights reserved. - * - ********************************************************************************* - */ - -#ifndef __ALD_USART_H__ -#define __ALD_USART_H__ - -#ifdef __cplusplus - extern "C" { -#endif - -#include "utils.h" -#include "ald_dma.h" - - -/** @addtogroup ES32FXXX_ALD - * @{ - */ - -/** @addtogroup USART - * @{ - */ - -/** @defgroup USART_Public_Types USART Public Types - * @{ - */ - -/** - * @brief usart_word_length - */ -typedef enum { - USART_WORD_LENGTH_8B = 0x0U, /**< Word length is 8-bits */ - USART_WORD_LENGTH_9B = 0x1U, /**< Word length is 9-bits */ -} usart_word_length_t; - -/** - * @brief usart_stop_bits - */ -typedef enum { - USART_STOP_BITS_1 = 0x0U, /**< Stop bits is 1-bits */ - USART_STOP_BITS_0_5 = 0x1U, /**< Stop bits is 0.5-bits */ - USART_STOP_BITS_2 = 0x2U, /**< Stop bits is 2-bits */ - USART_STOP_BITS_1_5 = 0x3U, /**< Stop bits is 1.5-bits */ -} usart_stop_bits_t; - -/** - * @brief usart_parity - */ -typedef enum { - USART_PARITY_NONE = 0x0U, /**< Not parity */ - USART_PARITY_EVEN = 0x2U, /**< Even parity */ - USART_PARITY_ODD = 0x3U, /**< Odd parity */ -} usart_parity_t; - -/** - * @brief usart_mode - */ -typedef enum { - USART_MODE_RX = 0x1U, /**< TX mode */ - USART_MODE_TX = 0x2U, /**< RX mode */ - USART_MODE_TX_RX = 0x3U, /**< TX & RX mode */ -} usart_mode_t; - -/** - * @brief usart_hardware_flow_control - */ -typedef enum { - USART_HW_FLOW_CTL_NONE = 0x0U, /**< Not flow control */ - USART_HW_FLOW_CTL_RTS = 0x1U, /**< RTS flow control */ - USART_HW_FLOW_CTL_CTS = 0x2U, /**< CTS flow control */ - USART_HW_FLOW_CTL_RTS_CTS = 0x3U, /**< RTS & CTS flow control */ -} usart_hw_flow_ctl_t; - -/** - * @brief usart_clock - */ -typedef enum { - USART_CLOCK_DISABLE = 0x0U, /**< Disable clock output */ - USART_CLOCK_ENABLE = 0x1U, /**< Enable clock output */ -} usart_clock_t; - -/** - * @brief usart_clock_polarity - */ -typedef enum { - USART_CPOL_LOW = 0x0U, /**< Clock polarity low */ - USART_CPOL_HIGH = 0x1U, /**< Clock polarity high */ -} usart_cpol_t; - -/** - * @brief usart_clock_phase - */ -typedef enum { - USART_CPHA_1EDGE = 0x0U, /**< Clock phase first edge */ - USART_CPHA_2EDGE = 0x1U, /**< Clock phase second edge */ -} usart_cpha_t; - -/** - * @brief usart_last_bit - */ -typedef enum { - USART_LAST_BIT_DISABLE = 0x0U, /**< Disable last bit clock output */ - USART_LAST_BIT_ENABLE = 0x1U, /**< Enable last bit clock output */ -} usart_last_bit_t; - -/** - * @brief usart state structures definition - */ -typedef enum { - USART_STATE_RESET = 0x00U, /**< Peripheral is not initialized */ - USART_STATE_READY = 0x01U, /**< Peripheral Initialized and ready for use */ - USART_STATE_BUSY = 0x02U, /**< an internal process is ongoing */ - USART_STATE_BUSY_TX = 0x11U, /**< Data Transmission process is ongoing */ - USART_STATE_BUSY_RX = 0x21U, /**< Data Reception process is ongoing */ - USART_STATE_BUSY_TX_RX = 0x31U, /**< Data Transmission Reception process is ongoing */ - USART_STATE_TIMEOUT = 0x03U, /**< Timeout state */ - USART_STATE_ERROR = 0x04U, /**< Error */ -} usart_state_t; - -/** - * @brief usart error codes - */ -typedef enum { - USART_ERROR_NONE = ((uint32_t)0x00U), /**< No error */ - USART_ERROR_PE = ((uint32_t)0x01U), /**< Parity error */ - USART_ERROR_NE = ((uint32_t)0x02U), /**< Noise error */ - USART_ERROR_FE = ((uint32_t)0x04U), /**< frame error */ - USART_ERROR_ORE = ((uint32_t)0x08U), /**< Overrun error */ - USART_ERROR_DMA = ((uint32_t)0x10U), /**< DMA transfer error */ -} usart_error_t; - - -/** - * @brief usart init structure definition - */ -typedef struct { - uint32_t baud; /**< This member configures the Usart communication baud rate. */ - usart_word_length_t word_length;/**< Specifies the number of data bits transmitted or received in a frame. */ - usart_stop_bits_t stop_bits; /**< Specifies the number of stop bits transmitted. */ - usart_parity_t parity; /**< Specifies the parity mode. - @note When parity is enabled, the computed parity is inserted - at the MSB position of the transmitted data (9th bit when - the word length is set to 9 data bits; 8th bit when the - word length is set to 8 data bits). */ - usart_mode_t mode; /**< Specifies wether the Receive or Transmit mode is enabled or disabled. */ - usart_hw_flow_ctl_t fctl; /**< Specifies wether the hardware flow control mode is enabled or disabled. */ -} usart_init_t; - -/** - * @brief USART handle structure definition - */ -typedef struct usart_handle_s { - USART_TypeDef *perh; /**< USART registers base address */ - usart_init_t init; /**< USART communication parameters */ - uint8_t *tx_buf; /**< Pointer to USART Tx transfer buffer */ - uint16_t tx_size; /**< USART Tx transfer size */ - uint16_t tx_count; /**< USART Tx transfer counter */ - uint8_t *rx_buf; /**< Pointer to USART Rx transfer buffer */ - uint16_t rx_size; /**< USART Rx Transfer size */ - uint16_t rx_count; /**< USART Rx Transfer Counter */ -#ifdef ALD_DMA - dma_handle_t hdmatx; /**< USART Tx DMA handle parameters */ - dma_handle_t hdmarx; /**< USART Rx DMA handle parameters */ -#endif - lock_state_t lock; /**< Locking object */ - usart_state_t state; /**< USART communication state */ - uint32_t err_code; /**< USART error code */ - - void (*tx_cplt_cbk)(struct usart_handle_s *arg); /**< Tx completed callback */ - void (*rx_cplt_cbk)(struct usart_handle_s *arg); /**< Rx completed callback */ - void (*tx_rx_cplt_cbk)(struct usart_handle_s *arg); /**< Tx & Rx completed callback */ - void (*error_cbk)(struct usart_handle_s *arg); /**< error callback */ -} usart_handle_t; - - -/** - * @brief USART clock init structure definition - */ -typedef struct { - usart_clock_t clk; /**< Pecifies whether the USART clock is enable or disable. */ - usart_cpol_t polarity; /**< Specifies the steady state of the serial clock. */ - usart_cpha_t phase; /**< Specifies the clock transition on which the bit capture is made. */ - usart_last_bit_t last_bit; /**< Specifies whether the clock pulse corresponding to the last transmitted - data bit (MSB) has to be output on the SCLK pin in synchronous mode. */ -} usart_clock_init_t; - - -/** - * @brief usart_dma_request - */ -typedef enum { - USART_DMA_REQ_TX = (1U << 7), /**< TX dma bit */ - USART_DMA_REQ_RX = (1U << 6), /**< RX dma bit */ -} usart_dma_req_t; - -/** - * @brief usart_wakeup_methods - */ -typedef enum { - USART_WAKEUP_IDLE = 0x0U, /**< Wake up the machine when bus-line is idle */ - USART_WAKEUP_ADDR = 0x1U, /**< Wake up the machine when match the address */ -} usart_wakeup_t; - -/** - * @brief usart_IrDA_low_power - */ -typedef enum { - USART_IrDA_MODE_NORMAL = 0x0U, /**< Normal IrDA mode */ - USART_IrDA_MODE_LOW_POWER = 0x1U, /**< Low-power IrDA mode */ -} usart_IrDA_mode_t; - -/** - * @brief USART interrupts definition - */ -typedef enum { - USART_IT_PE = ((1U << 8) | (1U << 16)), /**< Parity error */ - USART_IT_TXE = ((1U << 7) | (1U << 16)), /**< Tx empty */ - USART_IT_TC = ((1U << 6) | (1U << 16)), /**< Tx complete */ - USART_IT_RXNE = ((1U << 5) | (1U << 16)), /**< Rx not empty */ - USART_IT_IDLE = ((1U << 4) | (1U << 16)), /**< Idle */ - USART_IT_CTS = ((1U << 10)| (1U << 18)), /**< CTS */ - USART_IT_ERR = ((1U << 0) | (1U << 18)), /**< Error */ - USART_IT_ORE = (1U << 3), /**< Overrun error */ - USART_IT_NE = (1U << 2), /**< Noise error */ - USART_IT_FE = (1U << 0), /**< Frame error */ -} usart_it_t; - -/** - * @brief USART flags - */ -typedef enum { - USART_FLAG_CTS = (1U << 9), /**< CTS */ - USART_FLAG_TXE = (1U << 7), /**< Tx empty */ - USART_FLAG_TC = (1U << 6), /**< Tx complete */ - USART_FLAG_RXNE = (1U << 5), /**< Rx not empty */ - USART_FLAG_IDLE = (1U << 4), /**< Idle */ - USART_FLAG_ORE = (1U << 3), /**< Overrun error */ - USART_FLAG_NE = (1U << 2), /**< Noise error */ - USART_FLAG_FE = (1U << 1), /**< Frame error */ - USART_FLAG_PE = (1U << 0), /**< Parity error */ -} usart_flag_t; - -/** - * @} - */ - - -/** @defgroup USART_Public_Macros USART Public Macros - * @{ - */ - -/** @defgroup USART_Public_Macros_1 USART handle reset - * @{ - */ -#define USART_RESET_HANDLE_STATE(handle) ((handle)->state = USART_STATE_RESET) -/** - * @} - */ - -/** @defgroup USART_Public_Macros_2 USART clear PE flag - * @{ - */ -#define USART_CLEAR_PEFLAG(handle) \ -do { \ - __IO uint32_t tmpreg; \ - tmpreg = (handle)->perh->STAT; \ - tmpreg = (handle)->perh->DATA; \ - UNUSED(tmpreg); \ -} while (0) -/** - * @} - */ - -/** @defgroup USART_Public_Macros_3 USART clear FE flag - * @{ - */ -#define USART_CLEAR_FEFLAG(handle) USART_CLEAR_PEFLAG(handle) -/** - * @} - */ - -/** @defgroup USART_Public_Macros_4 USART clear NE flag - * @{ - */ -#define USART_CLEAR_NEFLAG(handle) USART_CLEAR_PEFLAG(handle) -/** - * @} - */ - -/** @defgroup USART_Public_Macros_5 USART clear ORE flag - * @{ - */ -#define USART_CLEAR_OREFLAG(handle) USART_CLEAR_PEFLAG(handle) -/** - * @} - */ - -/** @defgroup USART_Public_Macros_6 USART clear IDLE flag - * @{ - */ -#define USART_CLEAR_IDLEFLAG(handle) USART_CLEAR_PEFLAG(handle) -/** - * @} - */ - -/** @defgroup USART_Public_Macros_7 USART enable CTS flow control - * @{ - */ -#define USART_HWCONTROL_CTS_ENABLE(handle) \ - (SET_BIT((handle)->perh->CON2, USART_CON2_CTSEN_MSK)) -/** - * @} - */ - -/** @defgroup USART_Public_Macros_8 USART disable CTS flow control - * @{ - */ -#define USART_HWCONTROL_CTS_DISABLE(handle) \ - (CLEAR_BIT((handle)->perh->CON2, USART_CON2_CTSEN_MSK)) -/** - * @} - */ - -/** @defgroup USART_Public_Macros_9 USART enable RTS flow control - * @{ - */ -#define USART_HWCONTROL_RTS_ENABLE(handle) \ - (SET_BIT((handle)->perh->CON2, USART_CON2_RTSEN_MSK)) -/** - * @} - */ - -/** @defgroup USART_Public_Macros_10 USART disable RTS flow control - * @{ - */ -#define USART_HWCONTROL_RTS_DISABLE(handle) \ - (CLEAR_BIT((handle)->perh->CON2, USART_CON2_RTSEN_MSK)) -/** - * @} - */ - -/** @defgroup USART_Public_Macros_11 USART enable - * @{ - */ -#define USART_ENABLE(handle) (SET_BIT((handle)->perh->CON0, USART_CON0_EN_MSK)) -/** - * @} - */ - -/** @defgroup USART_Public_Macros_12 USART disable - * @{ - */ -#define USART_DISABLE(handle) (CLEAR_BIT((handle)->perh->CON0, USART_CON0_EN_MSK)) - /** - * @} - */ - -/** - * @} - */ - -/** @defgroup USART_Private_Macros USART Private Macros - * @{ - */ - -#define IS_USART(x) (((x) == USART0) || ((x) == USART1)) -#define IS_USART_WORD_LENGTH(x) (((x) == USART_WORD_LENGTH_8B) || \ - ((x) == USART_WORD_LENGTH_9B)) -#define IS_USART_STOPBITS(x) (((x) == USART_STOP_BITS_1) || \ - ((x) == USART_STOP_BITS_0_5) || \ - ((x) == USART_STOP_BITS_2) || \ - ((x) == USART_STOP_BITS_1_5)) -#define IS_USART_PARITY(x) (((x) == USART_PARITY_NONE) || \ - ((x) == USART_PARITY_EVEN) || \ - ((x) == USART_PARITY_ODD)) -#define IS_USART_MODE(x) (((x) == USART_MODE_RX) || \ - ((x) == USART_MODE_TX) || \ - ((x) == USART_MODE_TX_RX)) -#define IS_USART_HARDWARE_FLOW_CONTROL(x)\ - (((x) == USART_HW_FLOW_CTL_NONE) || \ - ((x) == USART_HW_FLOW_CTL_RTS) || \ - ((x) == USART_HW_FLOW_CTL_CTS) || \ - ((x) == USART_HW_FLOW_CTL_RTS_CTS)) -#define IS_USART_CLOCK(x) (((x) == USART_CLOCK_DISABLE) || \ - ((x) == USART_CLOCK_ENABLE)) -#define IS_USART_CPOL(x) (((x) == USART_CPOL_LOW) || ((x) == USART_CPOL_HIGH)) -#define IS_USART_CPHA(x) (((x) == USART_CPHA_1EDGE) || ((x) == USART_CPHA_2EDGE)) -#define IS_USART_LASTBIT(x) (((x) == USART_LAST_BIT_DISABLE) || \ - ((x) == USART_LAST_BIT_ENABLE)) -#define IS_USART_DMAREQ(x) (((x) == USART_DMA_REQ_TX) || \ - ((x) == USART_DMA_REQ_RX)) -#define IS_USART_WAKEUP(x) (((x) == USART_WAKEUP_IDLE) || \ - ((x) == USART_WAKEUP_ADDR)) -#define IS_USART_IRDA_MODE(x) (((x) == USART_IrDA_MODE_NORMAL) || \ - ((x) == USART_IrDA_MODE_LOW_POWER)) -#define IS_USART_CONFIG_IT(x) (((x) == USART_IT_PE) || ((x) == USART_IT_TXE) || \ - ((x) == USART_IT_TC) || ((x) == USART_IT_RXNE) || \ - ((x) == USART_IT_IDLE) || \ - ((x) == USART_IT_CTS) || ((x) == USART_IT_ERR)) -#define IS_USART_GET_IT(x) (((x) == USART_IT_PE) || ((x) == USART_IT_TXE) || \ - ((x) == USART_IT_TC) || ((x) == USART_IT_RXNE) || \ - ((x) == USART_IT_IDLE) || \ - ((x) == USART_IT_CTS) || ((x) == USART_IT_ORE) || \ - ((x) == USART_IT_NE) || ((x) == USART_IT_FE) || \ - ((x) == USART_IT_ERR)) -#define IS_USART_CLEAR_IT(x) (((x) == USART_IT_TC) || ((x) == USART_IT_RXNE) || \ - ((x) == USART_IT_CTS)) - -#define IS_USART_FLAG(x) (((x) == USART_FLAG_PE) || ((x) == USART_FLAG_TXE) || \ - ((x) == USART_FLAG_TC) || ((x) == USART_FLAG_RXNE) || \ - ((x) == USART_FLAG_IDLE) || \ - ((x) == USART_FLAG_CTS) || ((x) == USART_FLAG_ORE) || \ - ((x) == USART_FLAG_NE) || ((x) == USART_FLAG_FE)) -#define IS_USART_CLEAR_FLAG(x) (((x) == USART_FLAG_CTS) || \ - ((x) == USART_FLAG_TC) || \ - ((x) == USART_FLAG_RXNE)) -#define IS_USART_BAUDRATE(x) (((x) > 0) && ((x) < 0x0044AA21)) -#define IS_USART_ADDRESS(x) ((x) <= 0xF) -#define IS_USART_DATA(x) ((x) <= 0x1FF) -#define DUMMY_DATA 0xFFFF -#define USART_STATE_TX_MASK (1U << 4) -#define USART_STATE_RX_MASK (1U << 5) - -/** - * @} - */ - -/** @addtogroup USART_Public_Functions - * @{ - */ - -/** @addtogroup USART_Public_Functions_Group1 - * @{ - */ -/* Initialization functions */ -void ald_usart_reset(usart_handle_t *hperh); -ald_status_t ald_usart_init(usart_handle_t *hperh); -ald_status_t ald_usart_half_duplex_init(usart_handle_t *hperh); -ald_status_t ald_usart_multi_processor_init(usart_handle_t *hperh, uint8_t addr, usart_wakeup_t wakeup); -ald_status_t ald_usart_clock_init(usart_handle_t *hperh, usart_clock_init_t *init); -/** - * @} - */ - -/** @addtogroup USART_Public_Functions_Group2 - * @{ - */ - -/** @addtogroup USART_Public_Functions_Group2_1 - * @{ - */ -/* Asynchronization IO operation functions */ -ald_status_t ald_usart_send(usart_handle_t *hperh, uint8_t *buf, uint16_t size, uint32_t timeout); -ald_status_t ald_usart_recv(usart_handle_t *hperh, uint8_t *buf, uint16_t size, uint32_t timeout); -ald_status_t ald_usart_send_by_it(usart_handle_t *hperh, uint8_t *buf, uint16_t size); -ald_status_t ald_usart_recv_by_it(usart_handle_t *hperh, uint8_t *buf, uint16_t size); -ald_status_t ald_usart_recv_frame_by_it(usart_handle_t *hperh, uint8_t *buf, uint16_t size); -#ifdef ALD_DMA -ald_status_t ald_usart_send_by_dma(usart_handle_t *hperh, uint8_t *buf, uint16_t size, uint8_t channel); -ald_status_t ald_usart_recv_by_dma(usart_handle_t *hperh, uint8_t *buf, uint16_t size, uint8_t channel); -#endif -/** - * @} - */ - -/** @addtogroup USART_Public_Functions_Group2_2 - * @{ - */ -/* Synchronization IO operation functions */ -ald_status_t ald_usart_send_sync(usart_handle_t *hperh, uint8_t *buf, uint16_t size, uint32_t timeout); -ald_status_t ald_usart_recv_sync(usart_handle_t *hperh, uint8_t *buf, uint16_t size, uint32_t timeout); -ald_status_t ald_usart_send_recv_sync(usart_handle_t *hperh, uint8_t *tx_buf, uint8_t *rx_buf, uint16_t size, uint32_t timeout); -ald_status_t ald_usart_send_by_it_sync(usart_handle_t *hperh, uint8_t *buf, uint16_t size); -ald_status_t ald_usart_recv_by_it_sync(usart_handle_t *hperh, uint8_t *buf, uint16_t size); -ald_status_t ald_usart_send_recv_by_it_sync(usart_handle_t *hperh, uint8_t *tx_buf, uint8_t *rx_buf, uint16_t size); -#ifdef ALD_DMA -ald_status_t ald_usart_send_by_dma_sync(usart_handle_t *hperh, uint8_t *buf, uint16_t size, uint8_t channel); -ald_status_t ald_usart_recv_by_dma_sync(usart_handle_t *hperh, uint8_t *buf, uint16_t size, uint8_t tx_channel, uint8_t rx_channel); -ald_status_t ald_usart_send_recv_by_dma_sync(usart_handle_t *hperh, uint8_t *tx_buf, - uint8_t *rx_buf, uint16_t size, uint8_t tx_channel, uint8_t rx_channel); -#endif -/** - * @} - */ - -/** @addtogroup USART_Public_Functions_Group2_3 - * @{ - */ -/* Utilities functions */ -#ifdef ALD_DMA -ald_status_t ald_usart_dma_pause(usart_handle_t *hperh); -ald_status_t ald_usart_dma_resume(usart_handle_t *hperh); -ald_status_t ald_usart_dma_stop(usart_handle_t *hperh); -#endif -void ald_usart_irq_handler(usart_handle_t *hperh); -/** - * @} - */ - -/** - * @} - */ - -/** @addtogroup USART_Public_Functions_Group3 - * @{ - */ -/* Peripheral control functions */ -ald_status_t ald_usart_multi_processor_enter_mute_mode(usart_handle_t *hperh); -ald_status_t ald_usart_multi_processor_exit_mute_mode(usart_handle_t *hperh); -ald_status_t ald_usart_half_duplex_enable_send(usart_handle_t *hperh); -ald_status_t ald_usart_half_duplex_enable_recv(usart_handle_t *hperh); -void ald_usart_dma_req_config(usart_handle_t *hperh, usart_dma_req_t req, type_func_t state); -void ald_usart_interrupt_config(usart_handle_t *hperh, usart_it_t it, type_func_t state); -flag_status_t ald_usart_get_flag_status(usart_handle_t *hperh, usart_flag_t flag); -void ald_usart_clear_flag_status(usart_handle_t *hperh, usart_flag_t flag); -it_status_t ald_usart_get_it_status(usart_handle_t *hperh, usart_it_t it); -/** - * @} - */ - -/** @addtogroup USART_Public_Functions_Group4 - * @{ - */ - -/* Peripheral state and error functions */ -usart_state_t ald_usart_get_state(usart_handle_t *hperh); -uint32_t ald_usart_get_error(usart_handle_t *hperh); -/** - * @} - */ - -/** - * @} - */ - -/** - * @} - */ - -/** - * @} - */ - -#ifdef __cplusplus -} -#endif - -#endif /* __ALD_USART_H__ */ diff --git a/bsp/essemi/es32f0334/libraries/ES32F033x_ALD_StdPeriph_Driver/Include/ald_wdt.h b/bsp/essemi/es32f0334/libraries/ES32F033x_ALD_StdPeriph_Driver/Include/ald_wdt.h deleted file mode 100644 index 619f777324..0000000000 --- a/bsp/essemi/es32f0334/libraries/ES32F033x_ALD_StdPeriph_Driver/Include/ald_wdt.h +++ /dev/null @@ -1,116 +0,0 @@ -/** - ********************************************************************************* - * - * @file ald_wdt.h - * @brief Header file of WDT module driver. - * - * @version V1.0 - * @date 18 Dec 2017 - * @author AE Team - * @note - * - * Copyright (C) Shanghai Eastsoft Microelectronics Co. Ltd. All rights reserved. - * - ******************************************************************************** - */ - -#ifndef __ALD_WDT_H__ -#define __ALD_WDT_H__ - -#ifdef __cplusplus -extern "C" { -#endif - -#include "utils.h" - -/** @addtogroup ES32FXXX_ALD - * @{ - */ - -/** @addtogroup WDT - * @{ - */ - -/** @defgroup WDT_Public_Types WDT Public Types - * @{ - */ - -/** - * @brief Wwdt no dog window - */ -typedef enum { - WWDT_WIN_25 = 0x0U, /**< No dog window size: 25% */ - WWDT_WIN_50 = 0x1U, /**< No dog window size: 50% */ - WWDT_WIN_75 = 0x2U, /**< No dog window size: 75% */ - WWDT_WIN_00 = 0x3U, /**< No dog window size: 0% */ -} wwdt_win_t; - -/** - * @} - */ - -/** - * @defgroup WDT_Private_Macros WDT Private Macros - * @{ - */ -#define WWDT_UNLOCK() {WRITE_REG(WWDT->LOCK, 0x1ACCE551U);} -#define WWDT_LOCK() {WRITE_REG(WWDT->LOCK, 0xFFFFFFFFU);} -#define IWDT_UNLOCK() {WRITE_REG(IWDT->LOCK, 0x1ACCE551U);} -#define IWDT_LOCK() {WRITE_REG(IWDT->LOCK, 0xFFFFFFFFU);} - -/** - * @} - */ - -/** - * @addtogroup WDT_Private_Macros WDT Private Macros - * @{ - */ -#define IS_WWDT_WIN_TYPE(x) ((x == WWDT_WIN_25) || \ - (x == WWDT_WIN_50) || \ - (x == WWDT_WIN_75) || \ - (x == WWDT_WIN_00)) -#define IS_FUNC_STATE(x) (((x) == DISABLE) || \ - ((x) == ENABLE)) -/** - * @} - */ - -/** @addtogroup WWDT_Public_Functions - * @{ - */ -void ald_wwdt_init(uint32_t load, wwdt_win_t win, type_func_t interrupt); -void ald_wwdt_start(void); -uint32_t ald_wwdt_get_value(void); -it_status_t ald_wwdt_get_flag_status(void); -void ald_wwdt_clear_flag_status(void); -void ald_wwdt_feed_dog(void); -/** - * @} - */ - -/** @addtogroup IWDT_Public_Functions - * @{ - */ -void ald_iwdt_init(uint32_t load, type_func_t interrupt); -void ald_iwdt_start(void); -uint32_t ald_iwdt_get_value(void); -it_status_t ald_iwdt_get_flag_status(void); -void ald_iwdt_clear_flag_status(void); -void ald_iwdt_feed_dog(void); -/** - * @} - */ - -/** - * @} - */ - -/** - * @} - */ -#ifdef __cplusplus -} -#endif - -#endif /* __ALD_WDT_H__ */ diff --git a/bsp/essemi/es32f0334/libraries/ES32F033x_ALD_StdPeriph_Driver/Include/type.h b/bsp/essemi/es32f0334/libraries/ES32F033x_ALD_StdPeriph_Driver/Include/type.h deleted file mode 100644 index 54082f3f21..0000000000 --- a/bsp/essemi/es32f0334/libraries/ES32F033x_ALD_StdPeriph_Driver/Include/type.h +++ /dev/null @@ -1,122 +0,0 @@ -/** - ********************************************************************************* - * - * @file type.h - * @brief define type - * - * @version V1.0 - * @date 17 Apr 2017 - * @author AE Team - * @note - * - * Copyright (C) Shanghai Eastsoft Microelectronics Co. Ltd. All rights reserved. - * - ********************************************************************************* - */ - -#ifndef __TYPE_H__ -#define __TYPE_H__ - -#ifdef __cplusplus -extern "C" { -#endif - -#include - - -#if defined (__CC_ARM) -#define __INLINE__ __inline -#define __STATIC_INLINE__ static __inline -#else -#define __INLINE__ inline -#define __STATIC_INLINE__ static inline -#endif - -#define __isr__ - -typedef enum { - RESET = 0x0U, - SET = 0x1U, -} flag_status_t, it_status_t; - -typedef enum { - BIT_RESET = 0x0U, - BIT_SET = 0x1U, -} bit_status_t; - -typedef enum { - DISABLE = 0x0U, - ENABLE = 0x1U, -} type_func_t; -#define IS_FUNC_STATE(x) (((x) == DISABLE) || ((x) == ENABLE)) - -typedef enum { - FALSE = 0x0U, - TRUE = 0x1U, -} type_bool_t; - -typedef enum { - UNLOCK = 0x0U, - LOCK = 0x1U, -} lock_state_t; -#define IS_LOCK_STATE(x) (((x) == UNLOCK) || ((x) == LOCK)) - - -#define BIT(x) ((1U << (x))) -#define BITS(s, e) ((0xffffffffU << (s)) & (0xffffffffU >> (31 - (e)))) -#define SET_BIT(reg, bit) ((reg) |= (bit)) -#define CLEAR_BIT(reg, bit) ((reg) &= ~(bit)) -#define READ_BIT(reg, bit) ((reg) & (bit)) -#define READ_BITS(reg, msk, s) (((reg) & (msk)) >> (s)) -#define CLEAR_REG(reg) ((reg) = (0x0)) -#define WRITE_REG(reg, val) ((reg) = (val)) -#define READ_REG(reg) ((reg)) -#define MODIFY_REG(reg, clearmask, setmask) \ - WRITE_REG((reg), (((READ_REG(reg)) & (~(clearmask))) | (setmask))) -#define UNUSED(x) ((void)(x)) - -#ifdef USE_ASSERT -#define assert_param(x) \ -do { \ - if (!(x)) { \ - __disable_irq(); \ - while (1) \ - ; \ - } \ -} while (0) -#else -#define assert_param(x) -#endif - - -#define PER_MEM_BASE ((uint32_t) 0x40000000UL) /* PER base address */ -#define RAM_MEM_BASE ((uint32_t) 0x20000000UL) /* RAM base address */ -#define BITBAND_PER_BASE ((uint32_t) 0x42000000UL) /* Peripheral Address Space bit-band area */ -#define BITBAND_RAM_BASE ((uint32_t) 0x22000000UL) /* SRAM Address Space bit-band area */ - -__STATIC_INLINE__ void BITBAND_PER(volatile uint32_t *addr, uint32_t bit, uint32_t val) -{ - uint32_t tmp = BITBAND_PER_BASE + (((uint32_t)addr - PER_MEM_BASE) << 5) + (bit << 2); - *((volatile uint32_t *)tmp) = (uint32_t)val; -} - -__STATIC_INLINE__ void BITBAND_SRAM(uint32_t *addr, uint32_t bit, uint32_t val) -{ - uint32_t tmp = BITBAND_RAM_BASE + (((uint32_t)addr - RAM_MEM_BASE) << 5) + (bit << 2); - *((volatile uint32_t *)tmp) = (uint32_t)val; -} - -#if defined ( __GNUC__ ) - #ifndef __weak - #define __weak __attribute__((weak)) - #endif /* __weak */ - #ifndef __packed - #define __packed __attribute__((__packed__)) - #endif /* __packed */ -#endif /* __GNUC__ */ - -#ifdef __cplusplus -} -#endif /* __cplusplus */ - -#endif /* __TYPE_H__ */ diff --git a/bsp/essemi/es32f0334/libraries/ES32F033x_ALD_StdPeriph_Driver/Include/utils.h b/bsp/essemi/es32f0334/libraries/ES32F033x_ALD_StdPeriph_Driver/Include/utils.h deleted file mode 100644 index 619914c23a..0000000000 --- a/bsp/essemi/es32f0334/libraries/ES32F033x_ALD_StdPeriph_Driver/Include/utils.h +++ /dev/null @@ -1,166 +0,0 @@ -/** - ********************************************************************************* - * - * @file utils.h - * @brief This file contains the Utilities functions/types for the driver. - * - * @version V1.0 - * @date 07 Nov 2017 - * @author AE Team - * @note - * - * Copyright (C) Shanghai Eastsoft Microelectronics Co. Ltd. All rights reserved. - * - ********************************************************************************* - */ - -#ifndef __UTILS_H__ -#define __UTILS_H__ - -#ifdef __cplusplus - extern "C" { -#endif - -#include -#include "ald_conf.h" -#include "type.h" -#include "es32f033x.h" - - -/** @addtogroup ES32FXXX_ALD - * @{ - */ - -/** @addtogroup UTILS - * @{ - */ - -/** @defgroup ALD_Public_Types Public Types - * @{ - */ -/** - * @brief SysTick interval - */ -extern uint32_t __systick_interval; - -/** - * @brief ALD Status structures definition - */ -typedef enum { - OK = 0x0U, /**< Status: OK */ - ERROR = 0x1U, /**< Status: ERROR */ - BUSY = 0x2U, /**< Status: BUSY */ - TIMEOUT = 0x3U, /**< Status: TIMEOUT */ -} ald_status_t; - -/** - * @brief SysTick interval definition - */ -typedef enum { - SYSTICK_INTERVAL_1MS = 1000U, /**< Interval is 1ms */ - SYSTICK_INTERVAL_10MS = 100U, /**< Interval is 10ms */ - SYSTICK_INTERVAL_100MS = 10U, /**< Interval is 100ms */ - SYSTICK_INTERVAL_1000MS = 1U, /**< Interval is 1s */ -} systick_interval_t; -/** - * @} - */ - -/** @defgroup ALD_Public_Macros Public Macros - * @{ - */ -#define ALD_MAX_DELAY 0xFFFFFFFFU -#define IS_BIT_SET(reg, bit) (((reg) & (bit)) != RESET) -#define IS_BIT_CLR(reg, bit) (((reg) & (bit)) == RESET) -#define RESET_HANDLE_STATE(x) ((x)->state = 0) -#define __LOCK(x) \ - do { \ - if ((x)->lock == LOCK) { \ - return BUSY; \ - } \ - else { \ - (x)->lock = LOCK; \ - } \ - } while (0) - -#define __UNLOCK(x) \ - do { \ - (x)->lock = UNLOCK; \ - } while (0) - -/** - * @} - */ - -/** @defgroup ALD_Private_Macros Private Macros - * @{ - */ -#define MCU_UID0_ADDR 0x000403E0U -#define MCU_UID1_ADDR 0x000403E8U -#define MCU_UID2_ADDR 0x000403F0U -#define MCU_CHIPID_ADDR 0x000403F8U -#define IS_PRIO(x) ((x) < 4) -#define IS_SYSTICK_INTERVAL(x) (((x) == SYSTICK_INTERVAL_1MS) || \ - ((x) == SYSTICK_INTERVAL_10MS) || \ - ((x) == SYSTICK_INTERVAL_100MS) || \ - ((x) == SYSTICK_INTERVAL_1000MS)) -/** - * @} - */ - -/** @addtogroup ALD_Public_Functions - * @{ - */ - -/** @addtogroup ALD_Public_Functions_Group1 - * @{ - */ - -/* Initialization functions */ -void ald_cmu_init(void); -void ald_tick_init(uint32_t prio); -void ald_systick_interval_select(systick_interval_t value); - -/** - * @} - */ - -/** @addtogroup ALD_Public_Functions_Group2 - * @{ - */ -/* Peripheral Control functions */ -void ald_inc_tick_weak(void); -void ald_delay_ms(__IO uint32_t delay); -uint32_t ald_get_tick(void); -void ald_suspend_tick(void); -void ald_resume_tick(void); -void ald_systick_irq_cbk(void); -void ald_inc_tick(void); -uint32_t ald_get_ald_version(void); -ald_status_t ald_wait_flag(uint32_t *reg, uint32_t bit, flag_status_t status, uint32_t timeout); -void ald_mcu_irq_config(IRQn_Type irq, uint8_t prio, type_func_t status); -uint32_t ald_mcu_get_tick(void); -uint32_t ald_mcu_get_cpu_id(void); -void ald_mcu_get_uid(uint8_t *buf); -uint32_t ald_mcu_get_chipid(void); -/** - * @} - */ - -/** - * @} - */ - -/** - * @} - */ - -/** - * @} - */ - -#ifdef __cplusplus -} -#endif - -#endif /* __UTILS_H__ */ diff --git a/bsp/essemi/es32f0334/libraries/ES32F033x_ALD_StdPeriph_Driver/Source/ald_acmp.c b/bsp/essemi/es32f0334/libraries/ES32F033x_ALD_StdPeriph_Driver/Source/ald_acmp.c deleted file mode 100644 index e480de1697..0000000000 --- a/bsp/essemi/es32f0334/libraries/ES32F033x_ALD_StdPeriph_Driver/Source/ald_acmp.c +++ /dev/null @@ -1,351 +0,0 @@ -/** - ********************************************************************************* - * - * @file ald_acmp.c - * @brief ACMP module driver. - * - * @version V1.0 - * @date 13 Dec 2017 - * @author AE Team - * @note - * - * Copyright (C) Shanghai Eastsoft Microelectronics Co. Ltd. All rights reserved. - * - ********************************************************************************* - */ - -#include "ald_acmp.h" - -/** @addtogroup ES32FXXX_ALD - * @{ - */ - -/** @defgroup ACMP ACMP - * @brief ACMP module driver - * @{ - */ -#ifdef ALD_ACMP - -/** @defgroup ACMP_Public_Functions ACMP Public Functions - * @{ - */ - -/** @defgroup ACMP_Public_Functions_Group1 Initialization functions - * @brief Initialization and Configuration functions - * @{ - */ - -/** - * @brief Initializes the ACMP mode according to the specified parameters in - * the acmp_init_t and create the associated handle. - * @param hperh: Pointer to a acmp_handle_t structure that contains - * the configuration information for the specified ACMP module. - * @retval Status, see @ref ald_status_t. - */ -ald_status_t ald_acmp_init(acmp_handle_t *hperh) -{ - uint32_t tmp = 0; - - if (hperh == NULL) - return ERROR; - - if (hperh->init.vdd_level > 63) - return ERROR; - - assert_param(IS_ACMP_TYPE(hperh->perh)); - assert_param(IS_ACMP_MODE_TYPE(hperh->init.mode)); - assert_param(IS_ACMP_WARM_UP_TIME_TYPE(hperh->init.warm_time)); - assert_param(IS_ACMP_HYSTSEL_TYPE(hperh->init.hystsel)); - assert_param(IS_ACMP_WARM_FUNC_TYPE(hperh->init.warm_func)); - assert_param(IS_ACMP_POS_INPUT_TYPE(hperh->init.pos_port)); - assert_param(IS_ACMP_NEG_INPUT_TYPE(hperh->init.neg_port)); - assert_param(IS_ACMP_INACTVAL_TYPE(hperh->init.inactval)); - assert_param(IS_ACMP_EDGE_TYPE(hperh->init.edge)); - - __LOCK(hperh); - - tmp = hperh->perh->CON; - - tmp |= ((hperh->init.mode << ACMP_CON_MODSEL_POSS) | (hperh->init.warm_time << ACMP_CON_WARMUPT_POSS) | - (hperh->init.inactval << ACMP_CON_INACTV_POS) | (hperh->init.hystsel << ACMP_CON_HYSTSEL_POSS)); - - hperh->perh->CON = tmp; - - tmp = hperh->perh->INPUTSEL; - - tmp |= ((hperh->init.pos_port << ACMP_INPUTSEL_PSEL_POSS) | (hperh->init.neg_port << ACMP_INPUTSEL_NSEL_POSS) | - (hperh->init.vdd_level << ACMP_INPUTSEL_VDDLVL_POSS)); - - hperh->perh->INPUTSEL = tmp; - - if (hperh->init.warm_func == ACMP_WARM_DISABLE) - CLEAR_BIT(hperh->perh->IES, ACMP_IES_WARMUP_MSK); - else - SET_BIT(hperh->perh->IES, ACMP_IES_WARMUP_MSK); - - switch (hperh->init.edge) { - case ACMP_EDGE_NONE: - CLEAR_BIT(hperh->perh->CON, ACMP_CON_FALLEN_MSK); - CLEAR_BIT(hperh->perh->CON, ACMP_CON_RISEEN_MSK); - break; - - case ACMP_EDGE_FALL: - SET_BIT(hperh->perh->CON, ACMP_CON_FALLEN_MSK); - CLEAR_BIT(hperh->perh->CON, ACMP_CON_RISEEN_MSK); - break; - - case ACMP_EDGE_RISE: - CLEAR_BIT(hperh->perh->CON, ACMP_CON_FALLEN_MSK); - SET_BIT(hperh->perh->CON, ACMP_CON_RISEEN_MSK); - break; - - case ACMP_EDGE_ALL: - SET_BIT(hperh->perh->CON, ACMP_CON_FALLEN_MSK); - SET_BIT(hperh->perh->CON, ACMP_CON_RISEEN_MSK); - break; - - default: - break; - } - - SET_BIT(hperh->perh->CON, ACMP_CON_EN_MSK); - - tmp = 0; - while (READ_BIT(hperh->perh->STAT, ACMP_STAT_ACT_MSK) == 0) { - if (tmp++ >= 600000) { - __UNLOCK(hperh); - return ERROR; - } - } - - __UNLOCK(hperh); - return OK; -} -/** - * @} - */ - -/** @defgroup ACMP_Public_Functions_Group2 Interrupt operation functions - * @brief ACMP Interrupt operation functions - * @{ - */ - -/** - * @brief Enables or disables the specified ACMP interrupts. - * @param hperh: Pointer to a acmp_handle_t structure that contains - * the configuration information for the specified ACMP module. - * @param it: Specifies the ACMP interrupt sources to be enabled or disabled. - * This parameter can be one of the @ref acmp_it_t. - * @param state: New status - * - ENABLE - * - DISABLE - * @retval Status, see @ref ald_status_t. - */ -ald_status_t ald_acmp_interrupt_config(acmp_handle_t *hperh, acmp_it_t it, type_func_t state) -{ - assert_param(IS_ACMP_TYPE(hperh->perh)); - assert_param(IS_ACMP_IT_TYPE(it)); - assert_param(IS_FUNC_STATE(state)); - - __LOCK(hperh); - - if (state) - hperh->perh->IES |= it; - else - hperh->perh->IEC |= it; - - __UNLOCK(hperh); - - return OK; -} - -/** - * @brief Checks whether the specified ACMP interrupt has set or not. - * @param hperh: Pointer to a acmp_handle_t structure that contains - * the configuration information for the specified ACMP module. - * @param it: Specifies the ACMP interrupt sources to be enabled or disabled. - * This parameter can be one of the @ref acmp_it_t. - * @retval it_status_t - * - SET - * - RESET - */ -it_status_t ald_acmp_get_it_status(acmp_handle_t *hperh, acmp_it_t it) -{ - assert_param(IS_ACMP_TYPE(hperh->perh)); - assert_param(IS_ACMP_IT_TYPE(it)); - - if (hperh->perh->IEV & it) - return SET; - else - return RESET; -} - -/** - * @brief Checks whether the specified ACMP interrupt has occurred or not. - * @param hperh: Pointer to a acmp_handle_t structure that contains - * the configuration information for the specified ACMP module. - * @param flag: Specifies the ACMP interrupt source to check. - * This parameter can be one of the @ref acmp_it_t. - * @retval it_status_t - * - SET - * - RESET - */ -it_status_t ald_acmp_get_flag_status(acmp_handle_t *hperh, acmp_flag_t flag) -{ - assert_param(IS_ACMP_TYPE(hperh->perh)); - assert_param(IS_ACMP_FLAG_TYPE(flag)); - - if (hperh->perh->RIF & flag) { - __UNLOCK(hperh); - return SET; - } - - return RESET; -} - -/** @brief Clear the specified ACMP it flags. - * @param hperh: Pointer to a acmp_handle_t structure that contains - * the configuration information for the specified ACMP module. - * @param flag: specifies the it flag. - * This parameter can be one of the @ref acmp_it_t. - * @retval Status, see @ref ald_status_t. - */ -ald_status_t ald_acmp_clear_flag_status(acmp_handle_t *hperh, acmp_flag_t flag) -{ - assert_param(IS_ACMP_TYPE(hperh->perh)); - assert_param(IS_ACMP_FLAG_TYPE(flag)); - - __LOCK(hperh); - hperh->perh->IFC |= flag; - __UNLOCK(hperh); - - return OK; -} - -/** @brief Set the specified acmp it flags. - * @param hperh: Pointer to a acmp_handle_t structure that contains - * the configuration information for the specified acmp module. - * @param it: specifies the it flag. - * This parameter can be one of the @ref acmp_it_t. - * @retval Status, see @ref ald_status_t. - */ -ald_status_t acmp_set_it_mask(acmp_handle_t *hperh, acmp_it_t it) -{ - assert_param(IS_ACMP_TYPE(hperh->perh)); - assert_param(IS_ACMP_IT_TYPE(it)); - - __LOCK(hperh); - hperh->perh->IFM |= it; - __UNLOCK(hperh); - - return OK; -} - -/** @brief Check whether the specified ACMP flag is set or not. - * @param hperh: Pointer to a acmp_handle_t structure that contains - * the configuration information for the specified ACMP module. - * @param status: specifies the status to check. - * This parameter can be one of the @ref acmp_status_t. - * @retval flag_status_t - * - SET - * - RESET - */ -flag_status_t ald_acmp_get_status(acmp_handle_t *hperh, acmp_status_t status) -{ - assert_param(IS_ACMP_TYPE(hperh->perh)); - assert_param(IS_ACMP_STATUS_TYPE(status)); - - if (hperh->perh->STAT & status) { - __UNLOCK(hperh); - return SET; - } - - return RESET; -} -/** - * @} - */ - -/** @defgroup ACMP_Public_Functions_Group3 Output value functions - * @brief ACMP Output value functions - * @{ - */ - -/** - * @brief This function handles ACMP interrupt request. - * @param hperh: Pointer to a acmp_handle_t structure that contains - * the configuration information for the specified ACMP module. - * @retval None - */ -void ald_acmp_irq_handler(acmp_handle_t *hperh) -{ - if ((ald_acmp_get_flag_status(hperh, ACMP_FLAG_WARMUP) == SET) && (ald_acmp_get_it_status(hperh, ACMP_IT_WARMUP) == SET)) { - if (hperh->acmp_warmup_cplt_cbk) - hperh->acmp_warmup_cplt_cbk(hperh); - ald_acmp_clear_flag_status(hperh, ACMP_FLAG_WARMUP); - } - - if ((ald_acmp_get_flag_status(hperh, ACMP_FLAG_EDGE) == SET) && (ald_acmp_get_it_status(hperh, ACMP_IT_EDGE) == SET)) { - if (hperh->acmp_edge_cplt_cbk) - hperh->acmp_edge_cplt_cbk(hperh); - ald_acmp_clear_flag_status(hperh, ACMP_FLAG_EDGE); - } - - return; -} - -/** - * @brief This function config acmp output. - * @param hperh: Pointer to a acmp_handle_t structure that contains - * the configuration information for the specified ACMP module. - * @param config: Pointer to a acmp_output_config_t structure that contains - * the configutation information for acmp output. - * @retval Status, see @ref ald_status_t. - */ -ald_status_t ald_acmp_out_config(acmp_handle_t *hperh, acmp_output_config_t *config) -{ - if (hperh == NULL) - return ERROR; - - if (config == NULL) - return ERROR; - - assert_param(IS_ACMP_TYPE(hperh->perh)); - assert_param(IS_ACMP_INVERT_TYPE(config->gpio_inv)); - assert_param(IS_ACMP_OUT_FUNC_TYPE(config->out_func)); - - __LOCK(hperh); - hperh->perh->CON |= (config->gpio_inv << ACMP_CON_OUTINV_POS); - hperh->perh->PORT = config->out_func; - __UNLOCK(hperh); - - return OK; -} - -/** - * @brief This function output acmp result. - * @param hperh: Pointer to a acmp_handle_t structure that contains - * the configuration information for the specified ACMP module. - * @retval output value. - */ -uint8_t ald_acmp_out_result(acmp_handle_t *hperh) -{ - assert_param(IS_ACMP_TYPE(hperh->perh)); - - return (READ_BIT(hperh->perh->STAT, ACMP_STAT_OUT_MSK) >> ACMP_STAT_OUT_POS); -} -/** - * @} - */ - -/** - * @} - */ -#endif /* ALD_ACMP */ -/** - * @} - */ - -/** - * @} - */ diff --git a/bsp/essemi/es32f0334/libraries/ES32F033x_ALD_StdPeriph_Driver/Source/ald_adc.c b/bsp/essemi/es32f0334/libraries/ES32F033x_ALD_StdPeriph_Driver/Source/ald_adc.c deleted file mode 100644 index 7f1f522c7a..0000000000 --- a/bsp/essemi/es32f0334/libraries/ES32F033x_ALD_StdPeriph_Driver/Source/ald_adc.c +++ /dev/null @@ -1,1083 +0,0 @@ -/** - ****************************************************************************** - * @file ald_adc.c - * @brief This file provides firmware functions to manage the following - * functionalities of the Analog to Digital Convertor (ADC) - * peripheral: - * + Initialization functions - * ++ Initialization and Configuration of ADC - * + Operation functions - * ++ Start, stop, get result of conversions of normal - * group, using 3 possible modes: polling, interruption or DMA. - * + Control functions - * ++ Channels configuration on normal group - * ++ Channels configuration on insert group - * ++ Analog Watchdog configuration - * + State functions - * ++ ADC state machine management - * ++ Interrupts and flags management - * - * @version V1.0 - * @date 15 Dec 2017 - * @author AE Team. - * @note - * - * Copyright (C) Shanghai Eastsoft Microelectronics Co. Ltd. All rights reserved. - * - ********************************************************************************* - */ - - -#include "ald_cmu.h" -#include "ald_adc.h" - - -/** @addtogroup ES32FXXX_ALD - * @{ - */ - -/** @defgroup ADC ADC - * @brief ADC module driver - * @{ - */ - -#ifdef ALD_ADC - -/** @addtogroup ADC_Private_Functions - * @{ - */ -#ifdef ALD_DMA -static void adc_dma_normal_conv_cplt(void *arg); -static void adc_dma_error(void *arg); -#endif -/** - * @} - */ - - -/** @defgroup ADC_Public_Functions ADC Public Functions - * @{ - */ - -/** @defgroup ADC_Public_Functions_Group1 Initialization functions - * @brief Initialization and Configuration functions - * @{ - */ - -/** - * @brief Initializes the ADC peripheral and normal group according to - * parameters specified in structure "adc_handle_t". - * @param hperh: Pointer to a adc_handle_t structure that contains - * the configuration information for the specified ADC module. - * @retval Status, see @ref ald_status_t. - */ -ald_status_t ald_adc_init(adc_handle_t *hperh) -{ - if (hperh == NULL) - return ERROR; - - assert_param(IS_ADC_TYPE(hperh->perh)); - assert_param(IS_ADC_DATA_ALIGN_TYPE(hperh->init.align)); - assert_param(IS_FUNC_STATE(hperh->init.scan)); - assert_param(IS_ADC_NCH_NR_TYPE(hperh->init.nch_nr)); - assert_param(IS_ADC_DISC_MODE_TYPE(hperh->init.disc)); - assert_param(IS_ADC_DISC_NR_TYPE(hperh->init.disc_nr)); - assert_param(IS_ADC_CONV_BIT_TYPE(hperh->init.data_bit)); - assert_param(IS_ADC_CLK_DIV_TYPE(hperh->init.div)); - assert_param(IS_ADC_NCHESEL_MODE_TYPE(hperh->init.nche_sel)); - assert_param(IS_ADC_NEG_REF_VOLTAGE_TYPE(hperh->init.n_ref)); - assert_param(IS_POS_REF_VOLTAGE_TYPE(hperh->init.p_ref)); - - if (hperh->state == ADC_STATE_RESET ) { - hperh->error_code = ADC_ERROR_NONE; - hperh->lock = UNLOCK; - } - - if ((hperh->init.p_ref == ADC_POS_REF_VDD) && (hperh->init.n_ref == ADC_NEG_REF_VSS)) { - ADC_ENABLE(hperh); - - MODIFY_REG(hperh->perh->CCR, ADC_CCR_VRNSEL_MSK, hperh->init.n_ref << ADC_CCR_VRNSEL_POS); - MODIFY_REG(hperh->perh->CCR, ADC_CCR_VRPSEL_MSK, hperh->init.p_ref << ADC_CCR_VRPSEL_POSS); - MODIFY_REG(hperh->perh->CCR, ADC_CCR_VCMBUFEN_MSK, 1 << ADC_CCR_VCMBUFEN_POS); - MODIFY_REG(hperh->perh->CCR, ADC_CCR_IREFEN_MSK, 1 << ADC_CCR_IREFEN_POS); - MODIFY_REG(hperh->perh->CCR, ADC_CCR_VREFEN_MSK, 1 << ADC_CCR_VREFEN_POS); - MODIFY_REG(hperh->perh->CCR, ADC_CCR_CKDIV_MSK, 6 << ADC_CCR_CKDIV_POSS); - MODIFY_REG(hperh->perh->CON1, ADC_CON1_ALIGN_MSK, ADC_DATAALIGN_RIGHT << ADC_CON1_ALIGN_POS); - MODIFY_REG(hperh->perh->CON0, ADC_CON0_RSEL_MSK, ADC_CONV_BIT_12 << ADC_CON0_RSEL_POSS); - MODIFY_REG(hperh->perh->CON1, ADC_CON1_CM_MSK, DISABLE << ADC_CON1_CM_POS); - MODIFY_REG(hperh->perh->NCHS1, ADC_NCHS1_NS1_MSK, ADC_CHANNEL_18 << ADC_NCHS1_NS1_POSS); - hperh->perh->SMPT2 = 0x30; - - /* Start adc normal convert */ - SET_BIT(hperh->perh->CON1, ADC_CON1_NCHTRG_MSK); - /* Wait convert finish */ - while (!READ_BIT(hperh->perh->STAT, ADC_STAT_NCHE_MSK)); - hperh->vdd_value = (hperh->perh->NCHDR & 0xfff); - /* Get calibration VDD value */ - hperh->vdd_value = 2000 * 4096 / hperh->vdd_value; - } - - ADC_DISABLE(hperh); - ald_adc_reset(hperh); - hperh->state = ADC_STATE_BUSY; - MODIFY_REG(hperh->perh->CON1, ADC_CON1_ALIGN_MSK, hperh->init.align << ADC_CON1_ALIGN_POS); - MODIFY_REG(hperh->perh->CON0, ADC_CON0_RSEL_MSK, hperh->init.data_bit << ADC_CON0_RSEL_POSS); - - /* Enable discontinuous mode only if continuous mode is disable */ - if (hperh->init.disc == ADC_NCH_DISC_EN) { - hperh->init.scan = ENABLE; - SET_BIT(hperh->perh->CON0, ADC_CON0_NCHDCEN_MSK); - MODIFY_REG(hperh->perh->CON0, ADC_CON0_ETRGN_MSK, hperh->init.disc_nr << ADC_CON0_ETRGN_POSS); - } - else if (hperh->init.disc == ADC_ICH_DISC_EN) { - hperh->init.scan = ENABLE; - SET_BIT(hperh->perh->CON0, ADC_CON0_ICHDCEN_MSK); - MODIFY_REG(hperh->perh->CON0, ADC_CON0_ETRGN_MSK, hperh->init.disc_nr << ADC_CON0_ETRGN_POSS); - } - else { - CLEAR_BIT(hperh->perh->CON0, ADC_CON0_NCHDCEN_MSK); - CLEAR_BIT(hperh->perh->CON0, ADC_CON0_ICHDCEN_MSK); - } - - if ((hperh->init.scan == ENABLE) || (hperh->init.disc == ADC_NCH_DISC_EN)) - MODIFY_REG(hperh->perh->CHSL, ADC_CHSL_NSL_MSK, hperh->init.nch_nr << ADC_CHSL_NSL_POSS); - - MODIFY_REG(hperh->perh->CON1, ADC_CON1_CM_MSK, hperh->init.scan << ADC_CON1_CM_POS); - MODIFY_REG(hperh->perh->CCR, ADC_CCR_GAINCALEN_MSK, DISABLE << ADC_CCR_GAINCALEN_POS); - MODIFY_REG(hperh->perh->CCR, ADC_CCR_OFFCALEN_MSK, DISABLE << ADC_CCR_OFFCALEN_POS); - MODIFY_REG(hperh->perh->CCR, ADC_CCR_DIFFEN_MSK, DISABLE << ADC_CCR_DIFFEN_POS); - /* if the ADC clock less than 1MHz,PWRMOD should be disable*/ - MODIFY_REG(hperh->perh->CCR, ADC_CCR_PWRMODSEL_MSK, DISABLE << ADC_CCR_PWRMODSEL_POS); - MODIFY_REG(hperh->perh->CCR, ADC_CCR_VRBUFEN_MSK, ENABLE << ADC_CCR_VRBUFEN_POS); - MODIFY_REG(hperh->perh->CCR, ADC_CCR_VCMBUFEN_MSK, ENABLE << ADC_CCR_VCMBUFEN_POS); - MODIFY_REG(hperh->perh->CCR, ADC_CCR_VREFEN_MSK, ENABLE << ADC_CCR_VREFEN_POS); - MODIFY_REG(hperh->perh->CCR, ADC_CCR_IREFEN_MSK, ENABLE << ADC_CCR_IREFEN_POS); - MODIFY_REG(hperh->perh->CCR, ADC_CCR_CKDIV_MSK, hperh->init.div << ADC_CCR_CKDIV_POSS); - MODIFY_REG(hperh->perh->CCR, ADC_CCR_VRNSEL_MSK, hperh->init.n_ref << ADC_CCR_VRNSEL_POS); - MODIFY_REG(hperh->perh->CCR, ADC_CCR_VRPSEL_MSK, hperh->init.p_ref << ADC_CCR_VRPSEL_POSS); - MODIFY_REG(hperh->perh->CON1, ADC_CON1_NCHESEL_MSK, hperh->init.nche_sel << ADC_CON1_NCHESEL_POS); - ald_adc_interrupt_config(hperh, ADC_IT_OVR, ENABLE); - ADC_ENABLE(hperh); - - hperh->init.cont = DISABLE; - hperh->error_code = ADC_ERROR_NONE; - hperh->state = ADC_STATE_READY; - return OK; -} - -/** - * @brief Deinitialize the ADC peripheral registers to their default reset - * values. - * @param hperh: Pointer to a adc_handle_t structure that contains - * the configuration information for the specified ADC module. - * @retval Status, see @ref ald_status_t. - */ -ald_status_t ald_adc_reset(adc_handle_t *hperh) -{ - assert_param(IS_ADC_TYPE(hperh->perh)); - - ADC_DISABLE(hperh); - WRITE_REG(hperh->perh->CLR, 0x30F); - WRITE_REG(hperh->perh->CON0, 0x0); - WRITE_REG(hperh->perh->CON1, 0x0); - WRITE_REG(hperh->perh->CCR, 0x0); - WRITE_REG(hperh->perh->WDTH, 0xFFF); - WRITE_REG(hperh->perh->WDTL, 0x0); - WRITE_REG(hperh->perh->ICHOFF[0], 0x0); - WRITE_REG(hperh->perh->ICHOFF[1], 0x0); - WRITE_REG(hperh->perh->ICHOFF[2], 0x0); - WRITE_REG(hperh->perh->ICHOFF[3], 0x0); - WRITE_REG(hperh->perh->ICHS, 0x0); - WRITE_REG(hperh->perh->NCHS1, 0x0); - WRITE_REG(hperh->perh->NCHS2, 0x0); - WRITE_REG(hperh->perh->NCHS3, 0x0); - WRITE_REG(hperh->perh->NCHS4, 0x0); - WRITE_REG(hperh->perh->SMPT1, 0x0); - WRITE_REG(hperh->perh->SMPT2, 0x0); - WRITE_REG(hperh->perh->CHSL, 0x0); - - hperh->state = ADC_STATE_RESET; - hperh->error_code = ADC_ERROR_NONE; - return OK; -} -/** - * @} - */ - -/** @defgroup ADC_Public_Functions_Group2 IO operation functions - * @brief Input and Output operation functions - * @{ - */ - -/** - * @brief Enables ADC, starts conversion of normal group. - * @param hperh: Pointer to a adc_handle_t structure that contains - * the configuration information for the specified ADC module. - * @retval Status, see @ref ald_status_t. - */ -ald_status_t ald_adc_normal_start(adc_handle_t *hperh) -{ - assert_param(IS_ADC_TYPE(hperh->perh)); - - ADC_ENABLE(hperh); - WRITE_REG(hperh->perh->CLR, ADC_FLAG_NCH | ADC_FLAG_NCHS); - SET_BIT(hperh->perh->CON1, ADC_CON1_NCHTRG_MSK); - - return OK; -} - -/** - * @brief Stop ADC conversion of normal group (and insert channels in - * case of auto_injection mode), disable ADC peripheral. - * @note: ADC peripheral disable is forcing stop of potential - * conversion on insert group. If insert group is under use, it - * should be preliminarily stopped using ald_adc_insert_stop function. - * @param hperh: Pointer to a adc_handle_t structure that contains - * the configuration information for the specified ADC module. - * @retval Status, see @ref ald_status_t. - */ -ald_status_t ald_adc_normal_stop(adc_handle_t *hperh) -{ - assert_param(IS_ADC_TYPE(hperh->perh)); - - ADC_DISABLE(hperh); - hperh->state = ADC_STATE_READY; - return OK; -} - -/** - * @brief Wait for normal group conversion to be completed. - * @note This function cannot be used in a particular setup: ADC configured in DMA mode. - * In this case, DMA resets the flag EOC and polling cannot be performed on each conversion. - * @note When use this function,you should be pay attention to the hperh->init.reocs_mode, - * if it is ADC_REOCS_MODE_ALL, it means the function will wait all normal rank conversion finished. - * if it is ADC_REOCS_MODE_ONE, it means the funcion will wait every normal rank conversion finished. - * @param hperh: Pointer to a adc_handle_t structure that contains - * the configuration information for the specified ADC module. - * @param timeout: Timeout value in millisecond. - * @retval Status, see @ref ald_status_t. - */ -ald_status_t ald_adc_normal_poll_for_conversion(adc_handle_t *hperh, uint32_t timeout) -{ - uint32_t _tick; - - assert_param(IS_ADC_TYPE(hperh->perh)); - - _tick = ald_get_tick(); - while (!(READ_BIT(hperh->perh->STAT, ADC_STAT_NCHE_MSK))) { - if (timeout != ALD_MAX_DELAY ) { - if ((timeout == 0) || ((ald_get_tick() - _tick) > timeout)) { - hperh->state = ADC_STATE_TIMEOUT; - return TIMEOUT; - } - } - } - - WRITE_REG(hperh->perh->CLR, ADC_FLAG_NCHS | ADC_FLAG_NCH); - return OK; -} - -/** - * @brief Poll for conversion event. - * @param hperh: Pointer to a adc_handle_t structure that contains - * the configuration information for the specified ADC module. - * @param event_type: the ADC event type. - * This parameter can be one of the following values: - * ADC_awd_event: ADC Analog watchdog event. - * @param timeout: Timeout value in millisecond. - * @retval Status, see @ref ald_status_t. - */ -ald_status_t ald_adc_poll_for_event(adc_handle_t *hperh, adc_event_type_t event_type, uint32_t timeout) -{ - uint32_t _tick; - - assert_param(IS_ADC_TYPE(hperh->perh)); - assert_param(IS_ADC_EVENT_TYPE(event_type)); - - _tick = ald_get_tick(); - while (ald_adc_get_flag_status(hperh, (adc_flag_t)event_type) == RESET) { - if (timeout != ALD_MAX_DELAY ) { - if ((timeout == 0) || ((ald_get_tick() - _tick) > timeout)) { - hperh->state = ADC_STATE_TIMEOUT; - return TIMEOUT; - } - } - } - - - CLEAR_BIT(hperh->state, ADC_STATE_BUSY_WDG); - return OK; -} - -/** - * @brief Enables ADC, starts conversion of normal group with interruption. - * Interruptions enabled in this function: - * - REOC (end of conversion of normal group) - * Each of these interruptions has its dedicated callback function. - * @param hperh: Pointer to a adc_handle_t structure that contains - * the configuration information for the specified ADC module. - * @retval Status, see @ref ald_status_t. - */ -ald_status_t ald_adc_normal_start_by_it(adc_handle_t *hperh) -{ - assert_param(IS_ADC_TYPE(hperh->perh)); - - SET_BIT(hperh->state, ADC_STATE_BUSY_N); - ADC_ENABLE(hperh); - WRITE_REG(hperh->perh->CLR, ADC_FLAG_NCH); - ald_adc_interrupt_config(hperh, ADC_IT_NCH, ENABLE); - SET_BIT(hperh->perh->CON1, ADC_CON1_NCHTRG_MSK); - - return OK; -} - -/** - * @brief Stop ADC conversion of normal group (and insert group in - * case of auto_injection mode), disable interrution of - * end-of-conversion, disable ADC peripheral. - * @param hperh: Pointer to a adc_handle_t structure that contains - * the configuration information for the specified ADC module. - * @retval Status, see @ref ald_status_t. - */ -ald_status_t ald_adc_normal_stop_by_it(adc_handle_t *hperh) -{ - assert_param(IS_ADC_TYPE(hperh->perh)); - - ADC_DISABLE(hperh); - ald_adc_interrupt_config(hperh, ADC_IT_NCH, DISABLE); - CLEAR_BIT(hperh->state, ADC_STATE_BUSY_N); - - return OK; -} - -#ifdef ALD_DMA -/** - * @brief Enables ADC, starts conversion of normal group and transfers result - * through DMA. - * @param hperh: Pointer to a adc_handle_t structure that contains - * the configuration information for the specified ADC module. - * @param buf: The destination Buffer address. - * @param size: The length of data to be transferred from ADC peripheral to memory. - * @param channel: The DMA channel - * @retval Status, see @ref ald_status_t. - */ -ald_status_t ald_adc_start_by_dma(adc_handle_t *hperh, uint16_t *buf, uint16_t size, uint8_t channel) -{ - if ((buf == NULL) || (size == 0)) - return ERROR; - - assert_param(IS_ADC_TYPE(hperh->perh)); - - SET_BIT(hperh->state, ADC_STATE_BUSY_N); - - if (hperh->hdma.perh == NULL) - hperh->hdma.perh = DMA0; - - hperh->hdma.cplt_cbk = adc_dma_normal_conv_cplt; - hperh->hdma.cplt_arg = hperh; - hperh->hdma.err_cbk = adc_dma_error; - hperh->hdma.err_arg = hperh; - - ald_dma_config_struct(&hperh->hdma.config); - hperh->hdma.config.src = (void *)&hperh->perh->NCHDR; - hperh->hdma.config.dst = (void *)buf; - hperh->hdma.config.size = size; - hperh->hdma.config.data_width = DMA_DATA_SIZE_HALFWORD; - hperh->hdma.config.src_inc = DMA_DATA_INC_NONE; - hperh->hdma.config.dst_inc = DMA_DATA_INC_HALFWORD; - hperh->hdma.config.msel = DMA_MSEL_ADC0; - hperh->hdma.config.msigsel = DMA_MSIGSEL_ADC; - hperh->hdma.config.channel = channel; - ald_dma_config_basic(&hperh->hdma); - - ADC_ENABLE(hperh); - SET_BIT(hperh->perh->CON1, ADC_CON1_NCHTRG_MSK); - return OK; -} - -/** - * @brief Stop ADC conversion of normal group (and insert group in - * case of auto_insert mode), disable ADC DMA transfer, disable - * ADC peripheral. - * @param hperh: Pointer to a adc_handle_t structure that contains - * the configuration information for the specified ADC module. - * @param channel: The DMA channel. - * @retval Status, see @ref ald_status_t. - */ -ald_status_t ald_adc_stop_by_dma(adc_handle_t *hperh, uint8_t channel) -{ - assert_param(IS_ADC_TYPE(hperh->perh)); - - ADC_DISABLE(hperh); - ald_dma_channel_config(hperh->hdma.perh, channel, DISABLE); - CLEAR_BIT(hperh->state, ADC_STATE_BUSY_N); - return OK; -} - -/** - * @brief DMA transfer complete callback. - * @param arg: argument of the call back. - * @retval None - */ -static void adc_dma_timer_trigger_cplt(void *arg) -{ - adc_timer_config_t *hperh = (adc_timer_config_t *)arg; - - ald_timer_base_stop(&hperh->h_timer); - ADC_DISABLE(&hperh->h_adc); - ald_dma_channel_config(hperh->h_dma.perh, hperh->dma_ch, DISABLE); - CLEAR_BIT(hperh->h_adc.state, ADC_STATE_BUSY_N); - - if (hperh->h_adc.normal_cplt_cbk) - hperh->h_adc.normal_cplt_cbk(&hperh->h_adc); - - return; -} - -/** - * @brief Config Timer trigger adc function - * @param config: Pointer to a adc_timer_config_t structure that - * contains the configuration information for the specified function. - * @retval Status, see @ref ald_status_t. - */ -ald_status_t ald_adc_timer_trigger_adc_by_dma(adc_timer_config_t *config) -{ - SET_BIT(config->h_adc.state, ADC_STATE_BUSY_N); - - config->h_pis.perh = PIS; - config->h_pis.init.producer_clk = PIS_CLK_PCLK1; - config->h_pis.init.producer_edge = PIS_EDGE_NONE; - config->h_pis.init.consumer_clk = PIS_CLK_PCLK2; - - #if defined (ES32F065x) - if (config->p_timer == AD16C4T0) - config->h_pis.init.producer_src = PIS_TIMER0_UPDATA; - #elif defined(ES32F033x) || defined (ES32F093x) - if (config->p_timer == GP16C4T0) - config->h_pis.init.producer_src = PIS_TIMER0_UPDATA; - #endif - else if (config->p_timer == BS16T0) - config->h_pis.init.producer_src = PIS_TIMER1_UPDATA; - else if (config->p_timer == GP16C2T0) - config->h_pis.init.producer_src = PIS_TIMER2_UPDATA; - else if (config->p_timer == GP16C2T1) - config->h_pis.init.producer_src = PIS_TIMER3_UPDATA; - else - return ERROR; - - if (config->p_adc == ADC0) - config->h_pis.init.consumer_trig = PIS_CH6_ADC0_NORMAL; - else - return ERROR; - - ald_pis_create(&config->h_pis); - - /* Initialize TIMER0 */ - config->h_timer.perh = config->p_timer; - config->h_timer.init.prescaler = 0; - config->h_timer.init.mode = TIMER_CNT_MODE_UP; - config->h_timer.init.period = ((ald_cmu_get_pclk1_clock() / 1000000) * config->time); - config->h_timer.init.clk_div = TIMER_CLOCK_DIV1; - config->h_timer.init.re_cnt = 0; - ald_timer_base_init(&config->h_timer); - - config->h_adc.perh = config->p_adc; - config->h_adc.init.align = ADC_DATAALIGN_RIGHT; - config->h_adc.init.scan = DISABLE; - config->h_adc.init.cont = DISABLE; - config->h_adc.init.nch_nr = ADC_NCH_NR_1; - config->h_adc.init.disc = ADC_ALL_DISABLE; - config->h_adc.init.disc_nr = ADC_DISC_NR_1; - config->h_adc.init.data_bit = ADC_CONV_BIT_12; - config->h_adc.init.div = ADC_CKDIV_128; - config->h_adc.init.nche_sel = ADC_NCHESEL_MODE_ONE; - config->h_adc.init.n_ref = config->n_ref; - config->h_adc.init.p_ref = config->p_ref; - config->h_adc.normal_cplt_cbk = config->cplt_cbk; - config->h_adc.insert_cplt_cbk = NULL; - config->h_adc.wdg_cbk = NULL; - config->h_adc.error_cbk = NULL; - config->h_adc.ovr_cbk = NULL; - ald_adc_init(&config->h_adc); - ADC_ENABLE(&config->h_adc); - - config->config.ch = config->adc_ch; - config->config.idx = ADC_NCH_IDX_1; - config->config.samp = ADC_SAMPLETIME_4; - ald_adc_normal_channel_config(&config->h_adc, &config->config); - - config->h_dma.cplt_cbk = adc_dma_timer_trigger_cplt; - config->h_dma.cplt_arg = config; - config->h_dma.err_cbk = adc_dma_error; - config->h_dma.err_arg = &config->h_adc; - - ald_dma_config_struct(&config->h_dma.config); - config->h_dma.perh = DMA0; - config->h_dma.config.src = (void *)&config->h_adc.perh->NCHDR; - config->h_dma.config.dst = (void *)config->buf; - config->h_dma.config.size = config->size; - config->h_dma.config.data_width = DMA_DATA_SIZE_HALFWORD; - config->h_dma.config.src_inc = DMA_DATA_INC_NONE; - config->h_dma.config.dst_inc = DMA_DATA_INC_HALFWORD; - config->h_dma.config.msel = DMA_MSEL_ADC0; - config->h_dma.config.msigsel = DMA_MSIGSEL_ADC; - config->h_dma.config.channel = config->dma_ch; - ald_dma_config_basic(&config->h_dma); - ald_timer_base_start(&config->h_timer); - - return OK; -} -#endif - -/** - * @brief Get ADC normal group conversion result. - * @param hperh: Pointer to a adc_handle_t structure that contains - * the configuration information for the specified ADC module. - * @retval ADC group normal conversion data - */ -uint32_t ald_adc_normal_get_value(adc_handle_t *hperh) -{ - assert_param(IS_ADC_TYPE(hperh->perh)); - - return hperh->perh->NCHDR; -} - -/** - * @brief The pos reference is VDD and neg reference is VSS, - * get adc normal group result and convert voltage value. - * @param hperh: Pointer to a adc_handle_t structure that contains - * the configuration information for the specified ADC module. - * @retval ADC group normal voltage value,the unit is mV. - */ -uint32_t ald_adc_get_vdd_value(adc_handle_t *hperh) -{ - uint32_t value, _tmp[5]; - - if ((hperh->init.p_ref != ADC_POS_REF_VDD) || (hperh->init.n_ref != ADC_NEG_REF_VSS)) - return 0; - - _tmp[0] = hperh->perh->CCR; - _tmp[1] = hperh->perh->CON0; - _tmp[2] = hperh->perh->CON1; - _tmp[3] = hperh->perh->NCHS1; - _tmp[4] = hperh->perh->SMPT2; - - hperh->perh->CON0 = 0x0; - hperh->perh->CON1 = 0x0; - hperh->perh->NCHS1 = 0x0; - - ADC_ENABLE(hperh); - hperh->perh->CCR = 0x8B06; - MODIFY_REG(hperh->perh->CON0, ADC_CON1_ALIGN_MSK, ADC_DATAALIGN_RIGHT << ADC_CON1_ALIGN_POS); - MODIFY_REG(hperh->perh->CON0, ADC_CON0_RSEL_MSK, ADC_CONV_BIT_12 << ADC_CON0_RSEL_POSS); - MODIFY_REG(hperh->perh->CON1, ADC_CON1_CM_MSK, DISABLE << ADC_CON1_CM_POS); - MODIFY_REG(hperh->perh->NCHS1, ADC_NCHS1_NS1_MSK, ADC_CHANNEL_18 << ADC_NCHS1_NS1_POSS); - hperh->perh->SMPT2 = 0x30; - SET_BIT(hperh->perh->CON1, ADC_CON1_NCHTRG_MSK); - - while (!READ_BIT(hperh->perh->STAT, ADC_STAT_NCHE_MSK)); - WRITE_REG(hperh->perh->CLR, ADC_FLAG_NCH | ADC_FLAG_NCHS); - value = (hperh->perh->NCHDR & 0xfff); - value = value == 0 ? 1 : value; - value = (2000 << 12) / value; - hperh->vdd_value = value; - - hperh->perh->CCR = _tmp[0]; - hperh->perh->CON0 = _tmp[1]; - hperh->perh->CON1 = _tmp[2]; - hperh->perh->NCHS1 = _tmp[3]; - hperh->perh->SMPT2 = _tmp[4]; - ADC_DISABLE(hperh); - - return value; -} - -/** - * @brief Enables ADC, starts conversion of insert group. - * Interruptions enabled in this function: None. - * @param hperh: Pointer to a adc_handle_t structure that contains - * the configuration information for the specified ADC module. - * @retval Status, see @ref ald_status_t. - */ -ald_status_t ald_adc_insert_start(adc_handle_t *hperh) -{ - assert_param(IS_ADC_TYPE(hperh->perh)); - - ADC_ENABLE(hperh); - WRITE_REG(hperh->perh->CLR, ADC_FLAG_ICH); - - if (!(READ_BIT(hperh->perh->CON0, ADC_CON0_IAUTO_MSK))) - SET_BIT(hperh->perh->CON1, ADC_CON1_ICHTRG_MSK); - - return OK; -} - -/** - * @brief Stop conversion of insert channels. Disable ADC peripheral if - * no normal conversion is on going. - * @note If ADC must be disabled and if conversion is on going on - * normal group, function ald_adc_normal_stop must be used to stop both - * insert and normal groups, and disable the ADC. - * @note If insert group mode auto-injection is enabled, - * function ald_adc_normal_stop must be used. - * @param hperh: Pointer to a adc_handle_t structure that contains - * the configuration information for the specified ADC module. - * @retval Status, see @ref ald_status_t. - */ -ald_status_t ald_adc_insert_stop(adc_handle_t *hperh) -{ - assert_param(IS_ADC_TYPE(hperh->perh)); - - ADC_DISABLE(hperh); - hperh->state = ADC_STATE_READY; - return OK; -} - -/** - * @brief Wait for insert group conversion to be completed. - * @param hperh: Pointer to a adc_handle_t structure that contains - * the configuration information for the specified ADC module. - * @param timeout: Timeout value in millisecond. - * @retval Status, see @ref ald_status_t. - */ -ald_status_t ald_adc_insert_poll_for_conversion(adc_handle_t *hperh, uint32_t timeout) -{ - uint32_t _tick; - - assert_param(IS_ADC_TYPE(hperh->perh)); - - _tick = ald_get_tick(); - - while (!(READ_BIT(hperh->perh->STAT, ADC_STAT_ICHE_MSK))) { - if (timeout != ALD_MAX_DELAY) { - if ((timeout == 0) || ((ald_get_tick() - _tick) > timeout)) { - hperh->state = ADC_STATE_TIMEOUT; - return TIMEOUT; - } - } - } - - WRITE_REG(hperh->perh->CLR, ADC_FLAG_ICHS | ADC_FLAG_ICH); - return OK; -} - -/** - * @brief Enables ADC, starts conversion of insert group with interruption. - * - JEOC (end of conversion of insert group) - * Each of these interruptions has its dedicated callback function. - * @param hperh: Pointer to a adc_handle_t structure that contains - * the configuration information for the specified ADC module. - * @retval Status, see @ref ald_status_t.. - */ -ald_status_t ald_adc_insert_start_by_it(adc_handle_t *hperh) -{ - assert_param(IS_ADC_TYPE(hperh->perh)); - - SET_BIT(hperh->state, ADC_STATE_BUSY_I); - ADC_ENABLE(hperh); - WRITE_REG(hperh->perh->CLR, ADC_FLAG_ICHS | ADC_FLAG_ICH); - ald_adc_interrupt_config(hperh, ADC_IT_ICH, ENABLE); - - if (!(READ_BIT(hperh->perh->CON0, ADC_CON0_IAUTO_MSK))) - SET_BIT(hperh->perh->CON1, ADC_CON1_ICHTRG_MSK); - - return OK; -} - -/** - * @brief Stop conversion of insert channels, disable interruption of - * end-of-conversion. Disable ADC peripheral if no normal conversion - * is on going. - * @note If ADC must be disabled and if conversion is on going on - * normal group, function ald_adc_normal_stop must be used to stop both - * insert and normal groups, and disable the ADC. - * @note If insert group mode auto-injection is enabled, - * function ald_adc_normal_stop must be used. - * @param hperh: Pointer to a adc_handle_t structure that contains - * the configuration information for the specified ADC module. - * @retval None - */ -ald_status_t ald_adc_insert_stop_by_it(adc_handle_t *hperh) -{ - assert_param(IS_ADC_TYPE(hperh->perh)); - - CLEAR_BIT(hperh->state, ADC_STATE_BUSY_I); - ADC_DISABLE(hperh); - ald_adc_interrupt_config(hperh, ADC_IT_ICH, DISABLE); - return OK; -} - -/** - * @brief Get ADC insert group conversion result. - * @param hperh: Pointer to a adc_handle_t structure that contains - * the configuration information for the specified ADC module. - * @param idx: Index of the insert channel. - * @retval ADC group insert conversion data - */ -uint32_t ald_adc_insert_get_value(adc_handle_t *hperh, adc_ich_idx_t idx) -{ - assert_param(IS_ADC_TYPE(hperh->perh)); - assert_param(IS_ADC_ICH_IDX_TYPE(idx)); - - return hperh->perh->ICHDR[idx - 1]; -} - -/** - * @brief Handles ADC interrupt request - * @param hperh: Pointer to a adc_handle_t structure that contains - * the configuration information for the specified ADC module. - * @retval None - */ -void ald_adc_irq_handler(adc_handle_t *hperh) -{ - assert_param(IS_ADC_TYPE(hperh->perh)); - - if (ald_adc_get_it_status(hperh, ADC_IT_NCH) && ald_adc_get_flag_status(hperh, ADC_FLAG_NCH)) { - WRITE_REG(hperh->perh->CLR, ADC_FLAG_NCH | ADC_FLAG_NCHS); - CLEAR_BIT(hperh->state, ADC_STATE_BUSY_N); - - if (hperh->normal_cplt_cbk) - hperh->normal_cplt_cbk(hperh); - } - - if (ald_adc_get_it_status(hperh, ADC_IT_ICH) && ald_adc_get_flag_status(hperh, ADC_FLAG_ICH)) { - WRITE_REG(hperh->perh->CLR, ADC_FLAG_ICH | ADC_FLAG_ICHS); - CLEAR_BIT(hperh->state, ADC_STATE_BUSY_I); - - if (hperh->insert_cplt_cbk) - hperh->insert_cplt_cbk(hperh); - } - - if (ald_adc_get_it_status(hperh, ADC_IT_AWD) && ald_adc_get_flag_status(hperh, ADC_FLAG_AWD)) { - CLEAR_BIT(hperh->state, ADC_STATE_BUSY_WDG); - WRITE_REG(hperh->perh->CLR, ADC_FLAG_AWD); - - if (hperh->wdg_cbk) - hperh->wdg_cbk(hperh); - } - - if (ald_adc_get_it_status(hperh, ADC_IT_OVR) && ald_adc_get_flag_status(hperh, ADC_FLAG_OVR)) { - WRITE_REG(hperh->perh->CLR, ADC_FLAG_OVR); - hperh->error_code |= ADC_ERROR_OVR; - hperh->state |= ADC_STATE_ERROR; - - if (hperh->ovr_cbk) - hperh->ovr_cbk(hperh); - } -} - -/** - * @} - */ - -/** @defgroup ADC_Public_Functions_Group3 Peripheral Control functions - * @brief Peripheral Control functions - * @{ - */ - -/** - * @brief Configures the the selected channel to be linked to the normal - * group. - * @param hperh: Pointer to a adc_handle_t structure that contains - * the configuration information for the specified ADC module. - * @param config: Structure of ADC channel for normal group. - * @retval Status, see @ref ald_status_t. - */ -ald_status_t ald_adc_normal_channel_config(adc_handle_t *hperh, adc_nch_conf_t *config) -{ - assert_param(IS_ADC_TYPE(hperh->perh)); - assert_param(IS_ADC_CHANNELS_TYPE(config->ch)); - assert_param(IS_ADC_NCH_IDX_TYPE(config->idx)); - assert_param(IS_ADC_SAMPLING_TIMES_TYPE(config->samp)); - - if (config->idx <= ADC_NCH_IDX_4 ) { - hperh->perh->NCHS1 &= ~(0x1f << (uint32_t)((config->idx - 1) << 3)); - hperh->perh->NCHS1 |= (config->ch << (uint32_t)((config->idx - 1) << 3)); - } - else if (config->idx <= ADC_NCH_IDX_8) { - hperh->perh->NCHS2 &= ~(0x1f << (uint32_t)((config->idx - 5) << 3)); - hperh->perh->NCHS2 |= (config->ch << (uint32_t)((config->idx - 5) << 3)); - } - else if (config->idx <= ADC_NCH_IDX_12) { - hperh->perh->NCHS3 &= ~(0x1f << (uint32_t)((config->idx - 9) << 3)); - hperh->perh->NCHS3 |= (config->ch << (uint32_t)((config->idx - 9) << 3)); - } - else { - hperh->perh->NCHS4 &= ~(0x1f << (uint32_t)((config->idx - 13) << 3)); - hperh->perh->NCHS4 |= (config->ch << (uint32_t)((config->idx - 13) << 3)); - } - - if (config->ch <= 15) { - hperh->perh->SMPT1 &= ~(0x03 << (uint32_t)(config->ch << 1)); - hperh->perh->SMPT1 |= config->samp << (uint32_t)(config->ch << 1); - } - else { - hperh->perh->SMPT2 &= ~(0x03 << (uint32_t)((config->ch - 16) << 1)); - hperh->perh->SMPT2 |= config->samp << (uint32_t)((config->ch - 16) << 1); - } - - CLEAR_BIT(hperh->perh->CON0, ADC_CON0_SCANEN_MSK); - return OK; -} - -/** - * @brief Configures the the selected channel to be linked to the insert - * group. - * @param hperh: Pointer to a adc_handle_t structure that contains - * the configuration information for the specified ADC module. - * @param config: Structure of ADC channel for insert group. - * @retval Status, see @ref ald_status_t. - */ -ald_status_t ald_adc_insert_channel_config(adc_handle_t *hperh, adc_ich_conf_t *config) -{ - ald_status_t status = OK; - - assert_param(IS_ADC_TYPE(hperh->perh)); - assert_param(IS_ADC_CHANNELS_TYPE(config->ch)); - assert_param(IS_ADC_ICH_IDX_TYPE(config->idx)); - assert_param(IS_ADC_SAMPLING_TIMES_TYPE(config->samp)); - assert_param(IS_ADC_IST_OFFSET_TYPE(config->offset)); - assert_param(IS_ADC_ICH_NR_TYPE(config->nr)); - assert_param(IS_FUNC_STATE(config->auto_m)); - - MODIFY_REG(hperh->perh->CHSL, ADC_CHSL_ISL_MSK, config->nr << ADC_CHSL_ISL_POSS); - hperh->perh->ICHS &= ~(0x1f << (uint32_t)((config->idx - 1) << 3)); - hperh->perh->ICHS |= config->ch << (uint32_t)((config->idx - 1) << 3); - - if (config->nr > 0) - SET_BIT(hperh->perh->CON0, ADC_CON0_SCANEN_MSK); - else - CLEAR_BIT(hperh->perh->CON0, ADC_CON0_SCANEN_MSK); - - if (config->auto_m == ENABLE) - SET_BIT(hperh->perh->CON0, ADC_CON0_IAUTO_MSK); - else - CLEAR_BIT(hperh->perh->CON0, ADC_CON0_IAUTO_MSK); - - if (hperh->init.disc == ADC_ICH_DISC_EN) { - if (config->auto_m == DISABLE) { - SET_BIT(hperh->perh->CON0, ADC_CON0_ICHDCEN_MSK); - } - else { - hperh->state |= ADC_STATE_ERROR; - hperh->error_code |= ADC_ERROR_INTERNAL; - status = ERROR; - } - } - - if (config->ch <= 15) { - hperh->perh->SMPT1 &= ~(0x03U << ((uint32_t)config->ch << 1)); - hperh->perh->SMPT1 |= config->samp << ((uint32_t)config->ch << 1); - } - else { - hperh->perh->SMPT2 &= ~(0x03U << (((uint32_t)config->ch - 16) << 1)); - hperh->perh->SMPT2 |= config->samp << (((uint32_t)config->ch - 16) << 1); - } - - hperh->perh->ICHOFF[config->idx] = config->offset; - return status; -} - -/** - * @brief Configures the analog watchdog. - * @param hperh: Pointer to a adc_handle_t structure that contains - * the configuration information for the specified ADC module. - * @param config: Structure of ADC analog watchdog configuration - * @retval ALD status - */ -ald_status_t ald_adc_analog_wdg_config(adc_handle_t *hperh, adc_analog_wdg_conf_t *config) -{ - assert_param(IS_ADC_TYPE(hperh->perh)); - assert_param(IS_ADC_ANALOG_WTD_MODE_TYPE(config->mode)); - assert_param(IS_FUNC_STATE(config->interrupt)); - assert_param(IS_HTR_TYPE(config->high_thrd)); - assert_param(IS_LTR_TYPE(config->low_thrd)); - - if ((config->mode == ADC_ANAWTD_SING_NM) - || (config->mode == ADC_ANAWTD_SING_IST) - || (config->mode == ADC_ANAWTD_SING_NMIST)) - assert_param(IS_ADC_CHANNELS_TYPE(config->ch)); - - if (config->interrupt == DISABLE) - ald_adc_interrupt_config(hperh, ADC_IT_AWD, DISABLE); - else - ald_adc_interrupt_config(hperh, ADC_IT_AWD, ENABLE); - - CLEAR_BIT(hperh->perh->CON0, ADC_CON0_ICHWDTEN_MSK); - CLEAR_BIT(hperh->perh->CON0, ADC_CON0_NCHWDEN_MSK); - CLEAR_BIT(hperh->perh->CON0, ADC_CON0_AWDSGL_MSK); - hperh->perh->CON0 |= config->mode; - - if (READ_BIT(hperh->perh->CON0, ADC_CON0_AWDSGL_MSK)) - MODIFY_REG(hperh->perh->CON0, ADC_CON0_AWDCH_MSK, config->ch << ADC_CON0_AWDCH_POSS); - - WRITE_REG(hperh->perh->WDTL, config->low_thrd); - WRITE_REG(hperh->perh->WDTH, config->high_thrd); - SET_BIT(hperh->state, ADC_STATE_BUSY_WDG); - - return OK; -} - -/** - * @brief Enables or disables the specified ADC interrupts. - * @param hperh: Pointer to a adc_handle_t structure. - * @param it: Specifies the ADC interrupt sources to be enabled or disabled. - * This parameter can be one of the @ref adc_it_t. - * @param state: New status - * - ENABLE - * - DISABLE - * @retval None - */ -void ald_adc_interrupt_config(adc_handle_t *hperh, adc_it_t it, type_func_t state) -{ - assert_param(IS_ADC_TYPE(hperh->perh)); - assert_param(IS_ADC_IT_TYPE(it)); - assert_param(IS_FUNC_STATE(state)); - - if (state == ENABLE) - SET_BIT(hperh->perh->CON0, it); - else - CLEAR_BIT(hperh->perh->CON0, it); - - return; -} - -/** - * @brief Checks whether the specified ADC interrupt has occurred or not. - * @param hperh: Pointer to a adc_handle_t structure. - * @param it: Specifies the ADC interrupt source to check. - * This parameter can be one of the @ref adc_it_t. - * @retval Status - * - SET - * - RESET - */ -it_status_t ald_adc_get_it_status(adc_handle_t *hperh, adc_it_t it) -{ - assert_param(IS_ADC_TYPE(hperh->perh)); - assert_param(IS_ADC_IT_TYPE(it)); - - if (READ_BIT(hperh->perh->CON0, it)) - return SET; - - return RESET; -} - -/** @brief Check whether the specified ADC flag is set or not. - * @param hperh: Pointer to a adc_handle_t structure. - * @param flag: specifies the flag to check. - * This parameter can be one of the @ref adc_flag_t. - * @retval Status - * - SET - * - RESET - */ -flag_status_t ald_adc_get_flag_status(adc_handle_t *hperh, adc_flag_t flag) -{ - assert_param(IS_ADC_TYPE(hperh->perh)); - assert_param(IS_ADC_FLAGS_TYPE(flag)); - - if (READ_BIT(hperh->perh->STAT, flag)) - return SET; - - return RESET; -} - -/** @brief Clear the specified ADC pending flags. - * @param hperh: Pointer to a adc_handle_t structure. - * @param flag: specifies the flag to check. - * This parameter can be one of the @ref adc_flag_t. - * @retval None - */ -void ald_adc_clear_flag_status(adc_handle_t *hperh, adc_flag_t flag) -{ - assert_param(IS_ADC_TYPE(hperh->perh)); - assert_param(IS_ADC_FLAGS_TYPE(flag)); - - WRITE_REG(hperh->perh->CLR, flag); - return; -} -/** - * @} - */ - -/** @defgroup ADC_Public_Functions_Group4 Peripheral State functions - * @brief Peripheral State functions - * @{ - */ - -/** - * @brief return the ADC state - * @param hperh: Pointer to a adc_handle_t structure that contains - * the configuration information for the specified ADC module. - * @retval state - */ -uint32_t ald_adc_get_state(adc_handle_t *hperh) -{ - return hperh->state; -} - -/** - * @brief Return the ADC error code - * @param hperh: Pointer to a adc_handle_t structure that contains - * the configuration information for the specified ADC module. - * @retval ADC Error Code - */ -uint32_t ald_adc_get_error(adc_handle_t *hperh) -{ - return hperh->error_code; -} - -/** - *@} - */ - -/** - *@} - */ - -/** @defgroup ADC_Private_Functions ADC Private Functions - * @{ - */ - -#ifdef ALD_DMA -/** - * @brief DMA transfer complete callback. - * @param arg: argument of the call back. - * @retval None - */ -static void adc_dma_normal_conv_cplt(void *arg) -{ - adc_handle_t *hperh = (adc_handle_t *)arg; - - if (hperh->normal_cplt_cbk) - hperh->normal_cplt_cbk(hperh); - -} - -/** - * @brief DMA error callback - * @param arg: argument of the call back. - * @retval None - */ -static void adc_dma_error(void *arg) -{ - adc_handle_t *hperh = (adc_handle_t *)arg; - hperh->state |= ADC_STATE_ERROR; - hperh->error_code |= ADC_ERROR_DMA; - - if (hperh->error_cbk) - hperh->error_cbk(hperh); -} -#endif -/** - *@} - */ - -#endif /* ALD_ADC */ - -/** - *@} - */ - -/** - *@} - */ diff --git a/bsp/essemi/es32f0334/libraries/ES32F033x_ALD_StdPeriph_Driver/Source/ald_bkpc.c b/bsp/essemi/es32f0334/libraries/ES32F033x_ALD_StdPeriph_Driver/Source/ald_bkpc.c deleted file mode 100644 index a3852bdb22..0000000000 --- a/bsp/essemi/es32f0334/libraries/ES32F033x_ALD_StdPeriph_Driver/Source/ald_bkpc.c +++ /dev/null @@ -1,158 +0,0 @@ -/** - ********************************************************************************* - * - * @file ald_bkpc.c - * @brief BKPC module driver. - * - * @version V1.0 - * @date 15 Dec 2017 - * @author AE Team - * @note - * - * Copyright (C) Shanghai Eastsoft Microelectronics Co. Ltd. All rights reserved. - * - ********************************************************************************* - */ - -#include "ald_bkpc.h" -#include "ald_rtc.h" - - -/** @addtogroup ES32FXXX_ALD - * @{ - */ - -/** @defgroup BKPC BKPC - * @brief BKPC module driver - * @{ - */ -#ifdef ALD_BKPC - -/** @defgroup BKPC_Public_Functions BKPC Public Functions - * @{ - */ - -/** @addtogroup BKPC_Public_Functions_Group1 Peripheral Control functions - * @brief Peripheral Control functions - * - * @verbatim - ============================================================================== - ##### Peripheral Control functions ##### - ============================================================================== - [..] This section provides functions allowing to: - (+) ald_bkpc_ldo_config() API can configure LDO in backup field. - (+) ald_bkpc_standby_wakeup_config() API can configure STANDBY wakeup. - - @endverbatim - * @{ - */ - -/** - * @brief Configure ldo in backup field - * @param output: Output voltage select. - * @param state: DISABLE/ENABLE. - * @retval None - */ -void ald_bkpc_ldo_config(bkpc_ldo_output_t output, type_func_t state) -{ - assert_param(IS_BKPC_LDO_OUTPUT(output)); - assert_param(IS_FUNC_STATE(state)); - - BKPC_UNLOCK(); - MODIFY_REG(BKPC->CR, BKPC_CR_MT_STDB_MSK, state << BKPC_CR_MT_STDB_POS); - - if (state) - MODIFY_REG(BKPC->CR, BKPC_CR_LDO_VSEL_MSK, output << BKPC_CR_LDO_VSEL_POSS); - - BKPC_LOCK(); - return; -} - -/** - * @brief Configure standby wakeup in backup field - * @param port: Wakeup port - * @param level: HIGH/LOW. - * @retval None - */ -void ald_bkpc_standby_wakeup_config(bkpc_wakeup_port_t port, bkpc_wakeup_level_t level) -{ - assert_param(IS_BKPC_WAKEUP_PORT(port)); - assert_param(IS_BKPC_WAKEUP_LEVEL(level)); - - if (port == PMU_STANDBY_PORT_SEL_NONE) { - BKPC_UNLOCK(); - CLEAR_BIT(BKPC->CR, BKPC_CR_WKPEN_MSK); - BKPC_LOCK(); - return; - } - - BKPC_UNLOCK(); - SET_BIT(BKPC->CR, BKPC_CR_WKPEN_MSK); - MODIFY_REG(BKPC->CR, BKPC_CR_WKPS_MSK, port << BKPC_CR_WKPS_POSS); - MODIFY_REG(BKPC->CR, BKPC_CR_WKPOL_MSK, level << BKPC_CR_WKPOL_POS); - BKPC_LOCK(); - - return; -} -/** - * @} - */ - -/** @addtogroup BKPC_Public_Functions_Group2 IO operation functions - * @brief IO operation functions - * - * @verbatim - ============================================================================== - ##### IO operation functions ##### - ============================================================================== - [..] This section provides functions allowing to: - (+) ald_bkpc_write_ram() API can write data in backup ram. - (+) ald_bkpc_read_ram() API can read data from backup ram. - - @endverbatim - * @{ - */ - -/** - * @brief Write data into backup ram. - * @param idx: Index of backup word. - * @param value: Value which will be written to backup ram. - * @retval None - */ -void ald_bkpc_write_ram(uint8_t idx, uint32_t value) -{ - assert_param(IS_BKPC_RAM_IDX(idx)); - - RTC_UNLOCK(); - WRITE_REG(RTC->BKPR[idx], value); - RTC_LOCK(); - - return; -} - -/** - * @brief Read data from backup ram. - * @param idx: Index of backup word. - * @retval The data. - */ -uint32_t ald_bkpc_read_ram(uint8_t idx) -{ - assert_param(IS_BKPC_RAM_IDX(idx)); - - return READ_REG(RTC->BKPR[idx]); -} -/** - * @} - */ - -/** - * @} - */ -#endif /* ALD_BKPC */ -/** - * @} - */ - -/** - * @} - */ diff --git a/bsp/essemi/es32f0334/libraries/ES32F033x_ALD_StdPeriph_Driver/Source/ald_calc.c b/bsp/essemi/es32f0334/libraries/ES32F033x_ALD_StdPeriph_Driver/Source/ald_calc.c deleted file mode 100644 index ec2400453d..0000000000 --- a/bsp/essemi/es32f0334/libraries/ES32F033x_ALD_StdPeriph_Driver/Source/ald_calc.c +++ /dev/null @@ -1,121 +0,0 @@ -/** - ********************************************************************************* - * - * @file ald_calc.c - * @brief CALC module driver. - * - * @version V1.0 - * @date 04 Dec 2017 - * @author AE Team - * @note - * - * Copyright (C) Shanghai Eastsoft Microelectronics Co. Ltd. All rights reserved. - * - ********************************************************************************* - */ - -#include "ald_calc.h" - - -/** @addtogroup ES32FXXX_ALD - * @{ - */ - -/** @defgroup CALC CALC - * @brief CALC module driver - * @{ - */ -#ifdef ALD_CALC - -/** @defgroup CALC_Public_Functions CALC Public Functions - * @brief Accelerating calculate functions - * - * @verbatim - ============================================================================== - ##### Accelerating calculate functions ##### - ============================================================================== - [..] This section provides functions allowing to: - (+) Square root operation. - (+) Division. - (+) Get DZ flag. - - @endverbatim - * @{ - */ - -/** - * @brief Square root operation. - * @param data: The radicand - * @retval The value of square root. - */ -uint32_t ald_calc_sqrt(uint32_t data) -{ - WRITE_REG(CALC->RDCND, data); - while (READ_BIT(CALC->SQRTSR, CALC_SQRTSR_BUSY_MSK)); - - return READ_REG(CALC->SQRTRES); -} - -/** - * @brief Calculating division. - * @param dividend: The value of the dividend. - * @param divisor: The value of the divisor. - * @param remainder: The value of the remainder. - * @retval The result of division. - */ -uint32_t ald_calc_div(uint32_t dividend, uint32_t divisor, uint32_t *remainder) -{ - CLEAR_BIT(CALC->DIVCSR, CALC_DIVCSR_SIGN_MSK); - SET_BIT(CALC->DIVCSR, CALC_DIVCSR_TRM_MSK); - WRITE_REG(CALC->DIVDR, dividend); - WRITE_REG(CALC->DIVSR, divisor); - - while (READ_BIT(CALC->DIVCSR, CALC_DIVCSR_BUSY_MSK)); - - *remainder = READ_REG(CALC->DIVRR); - return READ_REG(CALC->DIVQR); -} - -/** - * @brief Calculating division. - * @param dividend: The value of the dividend. - * @param divisor: The value of the divisor. - * @param remainder: The value of the remainder. - * @retval The result of division. - */ -int32_t ald_calc_div_sign(int32_t dividend, int32_t divisor, int32_t *remainder) -{ - SET_BIT(CALC->DIVCSR, CALC_DIVCSR_SIGN_MSK); - SET_BIT(CALC->DIVCSR, CALC_DIVCSR_TRM_MSK); - WRITE_REG(CALC->DIVDR, dividend); - WRITE_REG(CALC->DIVSR, divisor); - - while (READ_BIT(CALC->DIVCSR, CALC_DIVCSR_BUSY_MSK)); - - *remainder = READ_REG(CALC->DIVRR); - return READ_REG(CALC->DIVQR); -} - -/** - * @brief Get the flag of divisor is zero. - * @retval The status, SET/RESET. - */ -flag_status_t ald_calc_get_dz_status(void) -{ - if (READ_BIT(CALC->DIVCSR, CALC_DIVCSR_DZ_MSK)) - return SET; - - return RESET; -} - -/** - * @} - */ -#endif /* ALD_CALC */ -/** - * @} - */ - -/** - * @} - */ diff --git a/bsp/essemi/es32f0334/libraries/ES32F033x_ALD_StdPeriph_Driver/Source/ald_cmu.c b/bsp/essemi/es32f0334/libraries/ES32F033x_ALD_StdPeriph_Driver/Source/ald_cmu.c deleted file mode 100644 index e43b12c7d1..0000000000 --- a/bsp/essemi/es32f0334/libraries/ES32F033x_ALD_StdPeriph_Driver/Source/ald_cmu.c +++ /dev/null @@ -1,1093 +0,0 @@ -/** - ********************************************************************************* - * - * @file ald_cmu.c - * @brief CMU module driver. - * - * @version V1.0 - * @date 22 Nov 2017 - * @author AE Team - * @note - * - * Copyright (C) Shanghai Eastsoft Microelectronics Co. Ltd. All rights reserved. - * - ********************************************************************************* - * @verbatim - ============================================================================== - ##### How to use this driver ##### - ============================================================================== - [..] - *** System clock configure *** - ================================= - [..] - (+) If you don't change system clock, you can using ald_cmu_clock_config_default() API. - It will select HRC as system clock. The system clock is 24MHz. - (+) If you want to change system clock, you can using ald_cmu_clock_config() API. - You can select one of the following as system clock: - @ref CMU_CLOCK_HRC 2MHz or 24MHz - @ref CMU_CLOCK_LRC 32768Hz - @ref CMU_CLOCK_LOSC 32768Hz - @ref CMU_CLOCK_PLL1 32MHz, 48MHz or (32768*1024)Hz - @ref CMU_CLOCK_HOSC 1MHz -- 24MHz - (+) If you select CMU_CLOCK_PLL1 as system clock, it must config the PLL1 - using ald_cmu_pll1_config() API. The input of clock must be 4MHz or PLL2. - (+) If you get system clock, you can using ald_cmu_get_sys_clock() API. - - *** BUS division control *** - =================================== - - MCLK sys_clk hclk1 - -------DIV_SYS-----------+------DIV_AHB1------------Peripheral(GPIO, CRC, ... etc.) - | - | pclk1 - +------DIV_APB1------------Peripheral(TIM, UART, ... etc.) - | - | pclk2 - +------DIV_APB2------------Peripheral(ADC, WWDT, ... etc.) - - [..] - (+) Configure the division using ald_cmu_div_config() API. - (+) Get sys_clk using ald_cmu_get_sys_clock() API. - (+) Get hclk1 using ald_cmu_get_hclk1_clock() API. - (+) Get pclk1 using ald_cmu_get_pclk1_clock() API. - (+) Get pclk2 using ald_cmu_get_pclk2_clock() API. - - *** Clock safe configure *** - =================================== - [..] - (+) If you select CMU_CLOCK_HOSC as system clock, you need enable - clock safe using ald_cmu_hosc_safe_config() API. It will change - CMU_CLOCK_HRC as system clock, when the outer crystal stoped. - (+) If you select CMU_CLOCK_LOSC as system clock, you need enable - clock safe using ald_cmu_losc_safe_config() API. It will change - CMU_CLOCK_LRC as system clock, when the outer crystal stoped. - (+) If you select CMU_CLOCK_PLL1 as system clock, you need enable - clock safe using ald_cmu_pll_safe_config() API. It will change - CMU_CLOCK_HRC as system clock, when the pll1 is lose. - (+) The ald_cmu_irq_cbk() will be invoked, when CMU interrupt has - been occurred. You can overwrite this function in application. - - *** Clock output configure *** - =================================== - [..] - (+) Output high-speed clock using ald_cmu_output_high_clock_config() API. - (+) Output low-speed clock using ald_cmu_output_low_clock_config() API. - - *** Peripheral clock configure *** - =================================== - [..] - (+) Configure buzz clock using ald_cmu_buzz_config() API. - (+) Selected lptim0 clock using ald_cmu_lptim0_clock_select() API. - (+) Selected lpuart clock using ald_cmu_lpuart0_clock_select() API. - (+) Selected lcd clock using ald_cmu_lcd_clock_select() API. - (+) Enable/Disable peripheral clock using ald_cmu_perh_clock_config() API. - - *** CMU ALD driver macros list *** - ============================================= - [..] - Below the list of most used macros in CMU driver. - - (+) CMU_LOSC_ENABLE(): Enable outer low crystal(32768Hz). - (+) CMU_LOSC_DISABLE(): Disable outer low crystal(32768Hz). - (+) CMU_LRC_ENABLE(): Enable LRC(32768Hz). - (+) CMU_LRC_DISABLE(): Disable LRC(32768Hz). - (+) CMU_ULRC_ENABLE(): Enable ULRC(10KHz). - (+) CMU_ULRC_DISABLE(): Disable ULRC(10KHz). - (+) CMU_LP_LRC_ENABLE(): Enable low power LRC(32768Hz). - (+) CMU_LP_LRC_DISABLE(): Disable low power LRC(32768Hz). - (+) CMU_LP_LOSC_ENABLE(): Enable low power LOSC(32768Hz). - (+) CMU_LP_LOSC_DISABLE(): Disable low power LOSC(32768Hz). - (+) CMU_LP_HRC_ENABLE(): Enable low power HRC(2MHz or 24MHz). - (+) CMU_LP_HRC_DISABLE(): Disable low power HRC(2MHz OR 24MHz). - (+) CMU_LP_HOSC_ENABLE(): Enable low power HOSC(1MHz -- 24MHz). - (+) CMU_LP_HOSC_DISABLE(): Disable low power HOSC(1MHz -- 24MHz). - - [..] - (@) You can refer to the CMU driver header file for used the macros - - @endverbatim - ****************************************************************************** - */ - -#include "ald_cmu.h" - - -/** @addtogroup ES32FXXX_ALD - * @{ - */ - -/** @defgroup CMU CMU - * @brief CMU module driver - * @{ - */ - -/** - * @defgroup CMU_Private_Variables CMU Private Variables - * @{ - */ -uint32_t __system_clock = 24000000U; -/** - * @} - */ - -/** @defgroup CMU_Private_Functions CMU Private Functions - * @{ - */ - -/** - * @brief Update the current system clock. This function - * will be invoked, when system clock has changed. - * @param clock: The new clock. - * @retval None - */ - -static void cmu_clock_update(uint32_t clock) -{ - __system_clock = clock; - - if (clock > 1000000) - ald_tick_init(TICK_INT_PRIORITY); - - return; -} - -/** - * @brief CMU module interrupt handler - * @retval None - */ -void ald_cmu_irq_handler(void) -{ - /* HOSC stop */ - if (READ_BIT(CMU->HOSMCR, CMU_HOSMCR_STPIF_MSK) && READ_BIT(CMU->HOSMCR, CMU_HOSMCR_STPIE_MSK)) { - SYSCFG_UNLOCK(); - SET_BIT(CMU->HOSMCR, CMU_HOSMCR_STPIF_MSK); - SYSCFG_LOCK(); - - if ((READ_BIT(CMU->HOSMCR, CMU_HOSMCR_CLKS_MSK)) - && ((READ_BITS(CMU->CSR, CMU_CSR_SYS_STU_MSK, CMU_CSR_SYS_STU_POSS) == 1) - || ((READ_BITS(CMU->CSR, CMU_CSR_SYS_STU_MSK, CMU_CSR_SYS_STU_POSS) == 5)))) - cmu_clock_update(READ_BIT(CMU->CFGR, CMU_CFGR_HRCFST_MSK) ? 2000000 : 24000000); - ald_cmu_irq_cbk(CMU_HOSC_STOP); - } - - /* HOSC start */ - if (READ_BIT(CMU->HOSMCR, CMU_HOSMCR_STRIF_MSK) && READ_BIT(CMU->HOSMCR, CMU_HOSMCR_STRIE_MSK)) { - SYSCFG_UNLOCK(); - SET_BIT(CMU->HOSMCR, CMU_HOSMCR_STRIF_MSK); - SYSCFG_LOCK(); - - if (!(READ_BIT(CMU->HOSMCR, CMU_HOSMCR_CLKS_MSK)) - && ((READ_BITS(CMU->CSR, CMU_CSR_SYS_STU_MSK, CMU_CSR_SYS_STU_POSS) == 5))) - cmu_clock_update((READ_BITS(CMU->HOSCCFG, CMU_HOSCCFG_FREQ_MSK, CMU_HOSCCFG_FREQ_POSS) + 1) * 1000000); - ald_cmu_irq_cbk(CMU_HOSC_START); - } - - /* LOSC stop */ - if (READ_BIT(CMU->LOSMCR, CMU_LOSMCR_STPIF_MSK) && READ_BIT(CMU->LOSMCR, CMU_LOSMCR_STPIE_MSK)) { - SYSCFG_UNLOCK(); - SET_BIT(CMU->LOSMCR, CMU_LOSMCR_STPIF_MSK); - SYSCFG_LOCK(); - ald_cmu_irq_cbk(CMU_LOSC_STOP); - } - - /* LOSC start */ - if (READ_BIT(CMU->LOSMCR, CMU_LOSMCR_STRIF_MSK) && READ_BIT(CMU->LOSMCR, CMU_LOSMCR_STRIE_MSK)) { - SYSCFG_UNLOCK(); - SET_BIT(CMU->LOSMCR, CMU_LOSMCR_STRIF_MSK); - SYSCFG_LOCK(); - ald_cmu_irq_cbk(CMU_LOSC_START); - } - - /* PLL1 lose */ - if (READ_BIT(CMU->PULMCR, CMU_PULMCR_ULKIF_MSK) && READ_BIT(CMU->PULMCR, CMU_PULMCR_ULKIE_MSK)) { - SYSCFG_UNLOCK(); - SET_BIT(CMU->PULMCR, CMU_PULMCR_ULKIF_MSK); - SYSCFG_LOCK(); - - if (READ_BIT(CMU->PULMCR, CMU_PULMCR_CLKS_MSK) - && ((READ_BITS(CMU->CSR, CMU_CSR_SYS_STU_MSK, CMU_CSR_SYS_STU_POSS) == 1) - || ((READ_BITS(CMU->CSR, CMU_CSR_SYS_STU_MSK, CMU_CSR_SYS_STU_POSS) == 5)))) - cmu_clock_update(READ_BIT(CMU->CFGR, CMU_CFGR_HRCFST_MSK) ? 2000000 : 24000000); - ald_cmu_irq_cbk(CMU_PLL1_UNLOCK); - } - - return; -} -/** - * @} - */ - -/** @defgroup CMU_Public_Functions CMU Public Functions - * @{ - */ - -/** @defgroup CMU_Public_Functions_Group1 System clock configuration - * @brief System clock configuration functions - * - * @verbatim - ============================================================================== - ##### System clock Configuration functions ##### - ============================================================================== - [..] This section provides functions allowing to: - (+) Configure system clock using default parameters. - (+) Configure system clock using specified parameters. - (+) Configure PLL1 using specified parameters. - (+) Get system clock. - - @endverbatim - * @{ - */ - -/** - * @brief Configure system clock using default. - * Select CMU_CLOCK_HRC(24MHz) as system clock and - * enable CMU_CLOCK_LRC(32768Hz). - * @retval The status of ALD. - */ -ald_status_t ald_cmu_clock_config_default(void) -{ - uint32_t cnt = 4000, tmp; - - SYSCFG_UNLOCK(); - - /* Select HRC */ - MODIFY_REG(CMU->CSR, CMU_CSR_SYS_CMD_MSK, CMU_CLOCK_HRC << CMU_CSR_SYS_CMD_POSS); - while (READ_BIT(CMU->CSR, CMU_CSR_SYS_RDYN_MSK) && (--cnt)); - - if (READ_BITS(CMU->CSR, CMU_CSR_SYS_STU_MSK, CMU_CSR_SYS_STU_POSS) != CMU_CLOCK_HRC) { - SYSCFG_LOCK(); - return ERROR; - } - - CLEAR_BIT(CMU->CFGR, CMU_CFGR_HRCFSW_MSK); /* Select 24Mhz */ - - tmp = READ_REG(CMU->CLKENR); - /* Enable HRC/LRC/LOSC */ - SET_BIT(tmp, CMU_CLKENR_HRCEN_MSK | CMU_CLKENR_LRCEN_MSK | CMU_CLKENR_LOSCEN_MSK); - WRITE_REG(CMU->CLKENR, tmp); - - SYSCFG_LOCK(); - return OK; -} - -/** - * @brief Configure system clock using specified parameters - * @param clk: The parameter can be one of the following: - * @arg @ref CMU_CLOCK_HRC 2MHz or 24MHz - * @arg @ref CMU_CLOCK_LRC 32768Hz - * @arg @ref CMU_CLOCK_LOSC 32768Hz - * @arg @ref CMU_CLOCK_PLL1 32MHz, 48MHz or (32768*1024)Hz - * @arg @ref CMU_CLOCK_HOSC 1MHz -- 24MHz - * @param clock: The clock which will be set. the value depends - * on the parameter of clk. - * @retval The status of ALD. - */ -ald_status_t ald_cmu_clock_config(cmu_clock_t clk, uint32_t clock) -{ - uint32_t cnt = 4000; - - assert_param(IS_CMU_CLOCK(clk)); - SYSCFG_UNLOCK(); - - switch (clk) { - case CMU_CLOCK_HRC: - assert_param(clock == 24000000 || clock == 2000000); - - MODIFY_REG(CMU->CSR, CMU_CSR_SYS_CMD_MSK, CMU_CLOCK_HRC << CMU_CSR_SYS_CMD_POSS); - while (READ_BIT(CMU->CSR, CMU_CSR_SYS_RDYN_MSK) && (--cnt)); - - if (READ_BITS(CMU->CSR, CMU_CSR_SYS_STU_MSK, CMU_CSR_SYS_STU_POSS) != CMU_CLOCK_HRC) { - SYSCFG_LOCK(); - return ERROR; - } - - if (clock == 24000000) - CLEAR_BIT(CMU->CFGR, CMU_CFGR_HRCFSW_MSK); - else - SET_BIT(CMU->CFGR, CMU_CFGR_HRCFSW_MSK); - - SET_BIT(CMU->CLKENR, CMU_CLKENR_HRCEN_MSK); - - for (cnt = 4000; cnt; --cnt); - cnt = 4000; - while ((!(READ_BIT(CMU->CLKSR, CMU_CLKSR_HRCACT_MSK))) && (--cnt)); - cnt = 4000; - while ((!(READ_BIT(CMU->CLKSR, CMU_CLKSR_HRCRDY_MSK))) && (--cnt)); - - cmu_clock_update(clock); - break; - - case CMU_CLOCK_LRC: - /* Close SysTick interrupt in lower clock */ - SysTick->CTRL &= ~SysTick_CTRL_ENABLE_Msk; - - MODIFY_REG(CMU->CSR, CMU_CSR_SYS_CMD_MSK, CMU_CLOCK_LRC << CMU_CSR_SYS_CMD_POSS); - while (READ_BIT(CMU->CSR, CMU_CSR_SYS_RDYN_MSK) && (--cnt)); - - if (READ_BITS(CMU->CSR, CMU_CSR_SYS_STU_MSK, CMU_CSR_SYS_STU_POSS) != CMU_CLOCK_LRC) { - SYSCFG_LOCK(); - return ERROR; - } - - SET_BIT(CMU->CLKENR, CMU_CLKENR_LRCEN_MSK); - - cnt = 4000; - while ((!(READ_BIT(CMU->CLKSR, CMU_CLKSR_LRCACT_MSK))) && (--cnt)); - cnt = 4000; - while ((!(READ_BIT(CMU->CLKSR, CMU_CLKSR_LRCRDY_MSK))) && (--cnt)); - - cmu_clock_update(32768); - break; - - case CMU_CLOCK_LOSC: - /* Close SysTick interrupt in lower clock */ - SysTick->CTRL &= ~SysTick_CTRL_ENABLE_Msk; - - MODIFY_REG(CMU->CSR, CMU_CSR_SYS_CMD_MSK, CMU_CLOCK_LOSC << CMU_CSR_SYS_CMD_POSS); - while (READ_BIT(CMU->CSR, CMU_CSR_SYS_RDYN_MSK) && (--cnt)); - - if (READ_BITS(CMU->CSR, CMU_CSR_SYS_STU_MSK, CMU_CSR_SYS_STU_POSS) != CMU_CLOCK_LOSC) { - SYSCFG_LOCK(); - return ERROR; - } - - SET_BIT(CMU->CLKENR, CMU_CLKENR_LOSCEN_MSK); - - cnt = 4000; - while ((!(READ_BIT(CMU->CLKSR, CMU_CLKSR_LOSCACT_MSK))) && (--cnt)); - cnt = 4000; - while ((!(READ_BIT(CMU->CLKSR, CMU_CLKSR_LOSCRDY_MSK))) && (--cnt)); - - cmu_clock_update(32768); - break; - - case CMU_CLOCK_PLL1: - MODIFY_REG(CMU->CSR, CMU_CSR_SYS_CMD_MSK, CMU_CLOCK_PLL1 << CMU_CSR_SYS_CMD_POSS); - while (READ_BIT(CMU->CSR, CMU_CSR_SYS_RDYN_MSK) && (--cnt)); - - if (READ_BITS(CMU->CSR, CMU_CSR_SYS_STU_MSK, CMU_CSR_SYS_STU_POSS) != CMU_CLOCK_PLL1) { - SYSCFG_LOCK(); - return ERROR; - } - - SET_BIT(CMU->CLKENR, CMU_CLKENR_PLL1EN_MSK); - - for (cnt = 4000; cnt; --cnt); - cnt = 4000; - while ((!(READ_BIT(CMU->CLKSR, CMU_CLKSR_PLL1ACT_MSK))) && (--cnt)); - cnt = 4000; - while ((!(READ_BIT(CMU->CLKSR, CMU_CLKSR_PLL1RDY_MSK))) && (--cnt)); - - cmu_clock_update(clock); - break; - - case CMU_CLOCK_HOSC: - assert_param(clock <= 24000000); - - MODIFY_REG(CMU->CSR, CMU_CSR_SYS_CMD_MSK, CMU_CLOCK_HOSC << CMU_CSR_SYS_CMD_POSS); - while (READ_BIT(CMU->CSR, CMU_CSR_SYS_RDYN_MSK) && (--cnt)); - - if (READ_BITS(CMU->CSR, CMU_CSR_SYS_STU_MSK, CMU_CSR_SYS_STU_POSS) != CMU_CLOCK_HOSC) { - SYSCFG_LOCK(); - return ERROR; - } - - SET_BIT(CMU->CLKENR, CMU_CLKENR_HOSCEN_MSK); - MODIFY_REG(CMU->HOSCCFG, CMU_HOSCCFG_FREQ_MSK, clock / 1000000 - 1); - - for (cnt = 4000; cnt; --cnt); - cnt = 4000; - while ((!(READ_BIT(CMU->CLKSR, CMU_CLKSR_HOSCACT_MSK))) && (--cnt)); - cnt = 4000; - while ((!(READ_BIT(CMU->CLKSR, CMU_CLKSR_HOSCRDY_MSK))) && (--cnt)); - - cmu_clock_update(clock); - break; - - default: - break; - } - - SYSCFG_LOCK(); - return OK; -} - - - -/** - * @brief Configure PLL1 using specified parameters. - * @param input: The input clock type. - * @param output: The output clock which can be 32MHz or 48MHz. - * When input = CMU_PLL1_INPUT_PLL2; then output must be - * CMU_PLL1_OUTPUT_32M, and then the real clock is (32768x1024)Hz. - * @retval None - */ -void ald_cmu_pll1_config(cmu_pll1_input_t input, cmu_pll1_output_t output) -{ - uint32_t cnt = 4000; - - assert_param(IS_CMU_PLL1_INPUT(input)); - assert_param(IS_CMU_PLL1_OUTPUT(output)); - - SYSCFG_UNLOCK(); - - if (input == CMU_PLL1_INPUT_HRC_6) { - SET_BIT(CMU->CLKENR, CMU_CLKENR_HRCEN_MSK); - } - else if (input == CMU_PLL1_INPUT_PLL2) { - SET_BIT(CMU->CLKENR, CMU_CLKENR_LOSCEN_MSK); - CLEAR_BIT(CMU->PLLCFG, CMU_PLLCFG_PLL2RFS_MSK); - SET_BIT(CMU->CLKENR, CMU_CLKENR_PLL2EN_MSK); - } - else { - SET_BIT(CMU->CLKENR, CMU_CLKENR_HOSCEN_MSK); - } - - MODIFY_REG(CMU->PLLCFG, CMU_PLLCFG_PLL1RFS_MSK, input << CMU_PLLCFG_PLL1RFS_POSS); - MODIFY_REG(CMU->PLLCFG, CMU_PLLCFG_PLL1OS_MSK, output << CMU_PLLCFG_PLL1OS_POS); - SET_BIT(CMU->CLKENR, CMU_CLKENR_PLL1EN_MSK); - - while ((READ_BIT(CMU->PLLCFG, CMU_PLLCFG_PLL1LCKN_MSK)) && (--cnt)); - cnt = 4000; - while ((!(READ_BIT(CMU->CLKSR, CMU_CLKSR_PLL1RDY_MSK))) && (--cnt)); - - SYSCFG_LOCK(); - return; -} - -/** - * @brief Gets MCLK clock. - * @retval The value of MCLK clock. - */ -uint32_t ald_cmu_get_clock(void) -{ - return __system_clock; -} - -/** - * @brief Automatic-calibrate internal clock. - * @param input: input type: HOSC or LOSC. - * @param freq: output frequency: 24MHz or 2MHz. - * @retval The result: - * - 0 Success - * - -1 Failed - */ -int32_t ald_cmu_auto_calib_clock(cmu_auto_calib_input_t input, cmu_auto_calib_output_t freq) -{ - uint32_t cnt = 5000, tmp; - - assert_param(IS_CMU_AUTO_CALIB_INPUT(input)); - assert_param(IS_CMU_AUTO_CALIB_OUTPUT(freq)); - - SYSCFG_UNLOCK(); - - tmp = READ_REG(CMU->HRCACR); - - MODIFY_REG(tmp, CMU_HRCACR_AC_MSK, 1 << CMU_HRCACR_AC_POSS); - MODIFY_REG(tmp, CMU_HRCACR_RFSEL_MSK, input << CMU_HRCACR_RFSEL_POS); - MODIFY_REG(tmp, CMU_HRCACR_FREQ_MSK, freq << CMU_HRCACR_FREQ_POS); - SET_BIT(tmp, CMU_HRCACR_EN_MSK); - WRITE_REG(CMU->HRCACR, tmp); - - while (cnt--); - cnt = 30000; - while ((READ_BIT(CMU->HRCACR, CMU_HRCACR_BUSY_MSK)) && (--cnt)); - - if (READ_BITS(CMU->HRCACR, CMU_HRCACR_STA_MSK, CMU_HRCACR_STA_POSS) != 1) { - CLEAR_BIT(CMU->HRCACR, CMU_HRCACR_EN_MSK); - SYSCFG_LOCK(); - return -1; - } - - SET_BIT(CMU->HRCACR, CMU_HRCACR_WRTRG_MSK); - CLEAR_BIT(CMU->HRCACR, CMU_HRCACR_EN_MSK); - SYSCFG_LOCK(); - - return 0; -} -/** - * @} - */ - -/** @defgroup CMU_Public_Functions_Group2 BUS division control - * @brief BUS division control functions - * - * @verbatim - ============================================================================== - ##### BUS division control functions ##### - ============================================================================== - [..] This section provides functions allowing to: - (+) Configure the bus division. - (+) Get AHB1 clock. - (+) Get system clock. - (+) Get APB1 clock. - (+) Get APB2 clock. - - @endverbatim - * @{ - */ - -/** - * @brief Configure the bus division. - * @param bus: The type of bus: - * @arg CMU_HCLK_1 - * @arg CMU_SYS - * @arg CMU_PCLK_1 - * @arg CMU_PCLK_2 - * @param div: The value of divider. - * @retval None - */ -void ald_cmu_div_config(cmu_bus_t bus, cmu_div_t div) -{ - assert_param(IS_CMU_BUS(bus)); - assert_param(IS_CMU_DIV(div)); - - SYSCFG_UNLOCK(); - - switch (bus) { - case CMU_HCLK_1: - MODIFY_REG(CMU->CFGR, CMU_CFGR_HCLK1DIV_MSK, div << CMU_CFGR_HCLK1DIV_POSS); - break; - - case CMU_SYS: - MODIFY_REG(CMU->CFGR, CMU_CFGR_SYSDIV_MSK, div << CMU_CFGR_SYSDIV_POSS); - - if ((__system_clock >> div) <= 1000000) { - /* Close SysTick interrupt in lower clock */ - SysTick->CTRL &= ~SysTick_CTRL_ENABLE_Msk; - } - else { - ald_tick_init(TICK_INT_PRIORITY); - } - - break; - - case CMU_PCLK_1: - MODIFY_REG(CMU->CFGR, CMU_CFGR_PCLK1DIV_MSK, div << CMU_CFGR_PCLK1DIV_POSS); - break; - - case CMU_PCLK_2: - MODIFY_REG(CMU->CFGR, CMU_CFGR_PCLK2DIV_MSK, div << CMU_CFGR_PCLK2DIV_POSS); - break; - - default: - break; - } - - SYSCFG_LOCK(); - return; -} - -/** - * @brief Get AHB1 clock. - * @retval The value of AHB1 clock. - */ -uint32_t ald_cmu_get_hclk1_clock(void) -{ - uint32_t sys_div = READ_BITS(CMU->CFGR, CMU_CFGR_SYSDIV_MSK, CMU_CFGR_SYSDIV_POSS); - uint32_t ahb_div = READ_BITS(CMU->CFGR, CMU_CFGR_HCLK1DIV_MSK, CMU_CFGR_HCLK1DIV_POSS); - - return (__system_clock >> sys_div) >> ahb_div; -} - -/** - * @brief Get system clock - * @retval The value of system clock - */ -uint32_t ald_cmu_get_sys_clock(void) -{ - uint32_t sys_div = READ_BITS(CMU->CFGR, CMU_CFGR_SYSDIV_MSK, CMU_CFGR_SYSDIV_POSS); - - return __system_clock >> sys_div; -} - -/** - * @brief Get APB1 clock. - * @retval The value of APB1 clock. - */ -uint32_t ald_cmu_get_pclk1_clock(void) -{ - uint32_t sys_div = READ_BITS(CMU->CFGR, CMU_CFGR_SYSDIV_MSK, CMU_CFGR_SYSDIV_POSS); - uint32_t apb1_div = READ_BITS(CMU->CFGR, CMU_CFGR_PCLK1DIV_MSK, CMU_CFGR_PCLK1DIV_POSS); - - return (__system_clock >> sys_div) >> apb1_div; -} - -/** - * @brief Get APB2 clock. - * @retval The value of APB2 clock. - */ -uint32_t ald_cmu_get_pclk2_clock(void) -{ - uint32_t sys_div = READ_BITS(CMU->CFGR, CMU_CFGR_SYSDIV_MSK, CMU_CFGR_SYSDIV_POSS); - uint32_t apb2_div = READ_BITS(CMU->CFGR, CMU_CFGR_PCLK2DIV_MSK, CMU_CFGR_PCLK2DIV_POSS); - - return (__system_clock >> sys_div) >> apb2_div; -} -/** - * @} - */ - -/** @defgroup CMU_Public_Functions_Group3 Clock safe configure - * @brief Clock safe configure functions - * - * @verbatim - ============================================================================== - ##### Clock safe configure functions ##### - ============================================================================== - [..] This section provides functions allowing to: - (+) Enable/Disable outer high crystal safe mode. - (+) Enable/Disable outer low crystal safe mode. - (+) Enable/Disable PLL1 safe mode. - (+) Interrupt callback function. - - @endverbatim - * @{ - */ - -/** - * @brief Enable/Disable outer high crystal safe mode. - * @param clock: the value of outer crystal frequency. - * @param status: The new status. - * @retval None - */ -void ald_cmu_hosc_safe_config(cmu_hosc_range_t clock, type_func_t status) -{ - assert_param(IS_CMU_HOSC_RANGE(clock)); - assert_param(IS_FUNC_STATE(status)); - - SYSCFG_UNLOCK(); - - if (status) { - SET_BIT(CMU->HOSMCR, CMU_HOSMCR_STPIF_MSK); - MODIFY_REG(CMU->HOSMCR, CMU_HOSMCR_FRQS_MSK, clock << CMU_HOSMCR_FRQS_POSS); - SET_BIT(CMU->HOSMCR, CMU_HOSMCR_EN_MSK); - SET_BIT(CMU->HOSMCR, CMU_HOSMCR_STPIE_MSK); - - ald_mcu_irq_config(CMU_IRQn, 3, ENABLE); - } - else { - CLEAR_BIT(CMU->HOSMCR, CMU_HOSMCR_EN_MSK); - CLEAR_BIT(CMU->HOSMCR, CMU_HOSMCR_STPIE_MSK); - - if (READ_BIT(CMU->LOSMCR, CMU_LOSMCR_EN_MSK) == 0 && READ_BIT(CMU->PULMCR, CMU_PULMCR_EN_MSK) == 0) - ald_mcu_irq_config(CMU_IRQn, 3, DISABLE); - } - - SYSCFG_LOCK(); - return; -} - -/** - * @brief Enable/Disable outer low crystal safe mode. - * @param status: The new status. - * @retval None - */ -void ald_cmu_losc_safe_config(type_func_t status) -{ - assert_param(IS_FUNC_STATE(status)); - SYSCFG_UNLOCK(); - - if (status) { - SET_BIT(CMU->LOSMCR, CMU_LOSMCR_STPIF_MSK); - SET_BIT(CMU->LOSMCR, CMU_LOSMCR_EN_MSK); - SET_BIT(CMU->LOSMCR, CMU_LOSMCR_STPIE_MSK); - - ald_mcu_irq_config(CMU_IRQn, 3, ENABLE); - } - else { - CLEAR_BIT(CMU->LOSMCR, CMU_LOSMCR_EN_MSK); - CLEAR_BIT(CMU->LOSMCR, CMU_LOSMCR_STPIE_MSK); - - if (READ_BIT(CMU->HOSMCR, CMU_HOSMCR_EN_MSK) == 0 && READ_BIT(CMU->PULMCR, CMU_PULMCR_EN_MSK) == 0) - ald_mcu_irq_config(CMU_IRQn, 3, DISABLE); - } - - SYSCFG_LOCK(); - return; -} - -/** - * @brief Enable/Disable PLL1 safe mode. - * @param status: The new status. - * @retval None - */ -void ald_cmu_pll_safe_config(type_func_t status) -{ - assert_param(IS_FUNC_STATE(status)); - SYSCFG_UNLOCK(); - - if (status) { - SET_BIT(CMU->PULMCR, CMU_PULMCR_ULKIF_MSK); - MODIFY_REG(CMU->PULMCR, CMU_PULMCR_MODE_MSK, 2 << CMU_PULMCR_MODE_POSS); - SET_BIT(CMU->PULMCR, CMU_PULMCR_EN_MSK); - SET_BIT(CMU->PULMCR, CMU_PULMCR_ULKIE_MSK); - - ald_mcu_irq_config(CMU_IRQn, 3, ENABLE); - } - else { - CLEAR_BIT(CMU->PULMCR, CMU_PULMCR_EN_MSK); - CLEAR_BIT(CMU->PULMCR, CMU_PULMCR_ULKIE_MSK); - - if (READ_BIT(CMU->HOSMCR, CMU_HOSMCR_EN_MSK) == 0 && READ_BIT(CMU->LOSMCR, CMU_LOSMCR_EN_MSK) == 0) - ald_mcu_irq_config(CMU_IRQn, 3, DISABLE); - } - - SYSCFG_LOCK(); - return; -} - -/** - * @brief Get current clock source. - * @param type: Type of source: HOSC/LOSC/PLL. - * @retval Status: - * - 0: Current clock is HOSC, LOSC or PLL - * - 1: Current clock is HRC, LRC or HRC - */ -uint32_t ald_cmu_current_clock_source_get(cmu_clock_safe_type_t type) -{ - assert_param(IS_CMU_SAFE_CLOCK_TYPE(type)); - - if (type == CMU_SAFE_CLK_HOSC) - return READ_BITS(CMU->HOSMCR, CMU_HOSMCR_CLKS_MSK, CMU_HOSMCR_CLKS_POS); - else if (type == CMU_SAFE_CLK_LOSC) - return READ_BITS(CMU->LOSMCR, CMU_LOSMCR_CLKS_MSK, CMU_LOSMCR_CLKS_POS); - else - return READ_BITS(CMU->PULMCR, CMU_PULMCR_CLKS_MSK, CMU_PULMCR_CLKS_POS); -} - -/** - * @brief Get clock state. - * @param sr: The state type, see @ref cmu_clock_state_t. - * @retval SET/RESET - */ -flag_status_t ald_cmu_get_clock_state(cmu_clock_state_t sr) -{ - assert_param(IS_CMU_CLOCK_STATE(sr)); - - if (READ_BIT(CMU->CLKSR, sr)) - return SET; - - return RESET; -} - -/** - * @brief Interrupt callback function. - * @note This function is declared as __weak to be overwritten in case of other - * implementations in user file. - * @retval None - */ -__weak void ald_cmu_irq_cbk(cmu_security_t se) -{ - return; -} -/** - * @} - */ - -/** @defgroup CMU_Public_Functions_Group4 Clock output configure - * @brief Clock output configure functions - * - * @verbatim - ============================================================================== - ##### Clock output configure functions ##### - ============================================================================== - [..] This section provides functions allowing to: - (+) Configure the high-speed clock output. - (+) Configure the low-speed clock output. - - @endverbatim - * @{ - */ - -/** - * @brief Configure the high-speed clock output. - * @param sel: Select the source: - * @arg CMU_OUTPUT_HIGH_SEL_HOSC - * @arg CMU_OUTPUT_HIGH_SEL_LOSC - * @arg CMU_OUTPUT_HIGH_SEL_HRC - * @arg CMU_OUTPUT_HIGH_SEL_LRC - * @arg CMU_OUTPUT_HIGH_SEL_HOSM - * @arg CMU_OUTPUT_HIGH_SEL_PLL1 - * @arg CMU_OUTPUT_HIGH_SEL_PLL2 - * @arg CMU_OUTPUT_HIGH_SEL_SYSCLK - * @param div: The value of divider: - * @arg CMU_OUTPUT_DIV_1 - * @arg CMU_OUTPUT_DIV_2 - * @arg CMU_OUTPUT_DIV_4 - * @arg CMU_OUTPUT_DIV_8 - * @arg CMU_OUTPUT_DIV_16 - * @arg CMU_OUTPUT_DIV_32 - * @arg CMU_OUTPUT_DIV_64 - * @arg CMU_OUTPUT_DIV_128 - * @param status: The new status. - * @retval None - */ -void ald_cmu_output_high_clock_config(cmu_output_high_sel_t sel, - cmu_output_high_div_t div, type_func_t status) -{ - assert_param(IS_CMU_OUTPUT_HIGH_SEL(sel)); - assert_param(IS_CMU_OUTPUT_HIGH_DIV(div)); - assert_param(IS_FUNC_STATE(status)); - - SYSCFG_UNLOCK(); - - if (status) { - MODIFY_REG(CMU->CLKOCR, CMU_CLKOCR_HSCOS_MSK, sel << CMU_CLKOCR_HSCOS_POSS); - MODIFY_REG(CMU->CLKOCR, CMU_CLKOCR_HSCODIV_MSK, div << CMU_CLKOCR_HSCODIV_POSS); - SET_BIT(CMU->CLKOCR, CMU_CLKOCR_HSCOEN_MSK); - } - else { - CLEAR_BIT(CMU->CLKOCR, CMU_CLKOCR_HSCOEN_MSK); - } - - SYSCFG_LOCK(); - return; -} - -/** - * @brief Configure the low-speed clock output. - * @param sel: Select the source: - * @arg CMU_OUTPUT_LOW_SEL_LOSC - * @arg CMU_OUTPUT_LOW_SEL_LRC - * @arg CMU_OUTPUT_LOW_SEL_LOSM - * @arg CMU_OUTPUT_LOW_SEL_BUZZ - * @arg CMU_OUTPUT_LOW_SEL_ULRC - * @param status: The new status. - * @retval None - */ -void ald_cmu_output_low_clock_config(cmu_output_low_sel_t sel, type_func_t status) -{ - assert_param(IS_CMU_OUTPUT_LOW_SEL(sel)); - assert_param(IS_FUNC_STATE(status)); - - SYSCFG_UNLOCK(); - - if (status) { - MODIFY_REG(CMU->CLKOCR, CMU_CLKOCR_LSCOS_MSK, sel << CMU_CLKOCR_LSCOS_POSS); - SET_BIT(CMU->CLKOCR, CMU_CLKOCR_LSCOEN_MSK); - } - else { - CLEAR_BIT(CMU->CLKOCR, CMU_CLKOCR_LSCOEN_MSK); - } - - SYSCFG_LOCK(); - return; -} -/** - * @} - */ - -/** @defgroup CMU_Public_Functions_Group5 Peripheral Clock configure - * @brief Peripheral clock configure functions - * - * @verbatim - ============================================================================== - ##### Peripheral clock configure functions ##### - ============================================================================== - [..] This section provides functions allowing to: - (+) Configure buzz clock. - (+) Select lptim0 clock source. - (+) Select lpuart0 clock source. - (+) Select lcd clock source. - (+) Enable/Disable peripheral clock. - - @endverbatim - * @{ - */ - -/** - * @brief Configure buzz clock. - * freq = sysclk / (2^(div + 1) * (dat + 1)) - * @param div: The value of divider. - * @param dat: The value of coefficient. - * @param status: The new status. - * @retval None - */ -void ald_cmu_buzz_config(cmu_buzz_div_t div, uint16_t dat, type_func_t status) -{ - assert_param(IS_CMU_BUZZ_DIV(div)); - assert_param(IS_FUNC_STATE(status)); - - SYSCFG_UNLOCK(); - - if (status) { - MODIFY_REG(CMU->BUZZCR, CMU_BUZZCR_DIV_MSK, div << CMU_BUZZCR_DIV_POSS); - MODIFY_REG(CMU->BUZZCR, CMU_BUZZCR_DAT_MSK, dat << CMU_BUZZCR_DAT_POSS); - SET_BIT(CMU->BUZZCR, CMU_BUZZCR_EN_MSK); - } - else { - CLEAR_BIT(CMU->BUZZCR, CMU_BUZZCR_EN_MSK); - } - - SYSCFG_LOCK(); - return; -} - -/** - * @brief Select lptim0 clock source. - * @param clock: The clock source: - * @arg CMU_LP_PERH_CLOCK_SEL_PCLK2 - * @arg CMU_LP_PERH_CLOCK_SEL_PLL1 - * @arg CMU_LP_PERH_CLOCK_SEL_PLL2 - * @arg CMU_LP_PERH_CLOCK_SEL_HRC - * @arg CMU_LP_PERH_CLOCK_SEL_HOSC - * @arg CMU_LP_PERH_CLOCK_SEL_LRC - * @arg CMU_LP_PERH_CLOCK_SEL_LOSC - * @arg CMU_LP_PERH_CLOCK_SEL_ULRC - * @arg CMU_LP_PERH_CLOCK_SEL_HRC_1M - * @arg CMU_LP_PERH_CLOCK_SEL_HOSC_1M - * @arg CMU_LP_PERH_CLOCK_SEL_LOSM - * @arg CMU_LP_PERH_CLOCK_SEL_HOSM - * @retval None - */ -void ald_cmu_lptim0_clock_select(cmu_lp_perh_clock_sel_t clock) -{ - assert_param(IS_CMU_LP_PERH_CLOCK_SEL(clock)); - - SYSCFG_UNLOCK(); - MODIFY_REG(CMU->PERICR, CMU_PERICR_LPTIM0_MSK, clock << CMU_PERICR_LPTIM0_POSS); - SYSCFG_LOCK(); - - return; -} - -/** - * @brief Select lpuart0 clock source. - * @param clock: The clock source: - * @arg CMU_LP_PERH_CLOCK_SEL_PCLK2 - * @arg CMU_LP_PERH_CLOCK_SEL_PLL1 - * @arg CMU_LP_PERH_CLOCK_SEL_PLL2 - * @arg CMU_LP_PERH_CLOCK_SEL_HRC - * @arg CMU_LP_PERH_CLOCK_SEL_HOSC - * @arg CMU_LP_PERH_CLOCK_SEL_LRC - * @arg CMU_LP_PERH_CLOCK_SEL_LOSC - * @arg CMU_LP_PERH_CLOCK_SEL_ULRC - * @arg CMU_LP_PERH_CLOCK_SEL_HRC_1M - * @arg CMU_LP_PERH_CLOCK_SEL_HOSC_1M - * @arg CMU_LP_PERH_CLOCK_SEL_LOSM - * @arg CMU_LP_PERH_CLOCK_SEL_HOSM - * @retval None - */ -void ald_cmu_lpuart0_clock_select(cmu_lp_perh_clock_sel_t clock) -{ - assert_param(IS_CMU_LP_PERH_CLOCK_SEL(clock)); - - SYSCFG_UNLOCK(); - MODIFY_REG(CMU->PERICR, CMU_PERICR_LPUART0_MSK, clock << CMU_PERICR_LPUART0_POSS); - SYSCFG_LOCK(); - - return; -} - -/** - * @brief Select lcd clock source. - * @param clock: The clock source: - * @arg CMU_LCD_SEL_LOSM - * @arg CMU_LCD_SEL_LOSC - * @arg CMU_LCD_SEL_LRC - * @arg CMU_LCD_SEL_ULRC - * @arg CMU_LCD_SEL_HRC_1M - * @arg CMU_LCD_SEL_HOSC_1M - * @retval None - */ -void ald_cmu_lcd_clock_select(cmu_lcd_clock_sel_t clock) -{ - assert_param(IS_CMU_LCD_CLOCK_SEL(clock)); - - SYSCFG_UNLOCK(); - MODIFY_REG(CMU->PERICR, CMU_PERICR_LCD_MSK, clock << CMU_PERICR_LCD_POSS); - SYSCFG_LOCK(); - - return; -} - -/** - * @brief Enable/Disable peripheral clock. - * @param perh: The type of peripheral, you can see @ref cmu_perh_t - * @param status: The new status. - * @retval None - */ -void ald_cmu_perh_clock_config(cmu_perh_t perh, type_func_t status) -{ - uint32_t idx, pos; - - assert_param(IS_CMU_PERH(perh)); - assert_param(IS_FUNC_STATE(status)); - - SYSCFG_UNLOCK(); - - if (perh == CMU_PERH_ALL) { - if (status) { - WRITE_REG(CMU->AHB1ENR, ~0); - WRITE_REG(CMU->APB1ENR, ~0); - WRITE_REG(CMU->APB2ENR, ~0); - } - else { - WRITE_REG(CMU->AHB1ENR, 0); - WRITE_REG(CMU->APB1ENR, 0); - WRITE_REG(CMU->APB2ENR, 0); - } - - SYSCFG_LOCK(); - return; - } - - idx = (perh >> 27) & 0x3; - pos = perh & ~(0x3 << 27); - - if (status) { - switch (idx) { - case 0: - SET_BIT(CMU->AHB1ENR, pos); - break; - - case 1: - SET_BIT(CMU->APB1ENR, pos); - break; - - case 2: - SET_BIT(CMU->APB2ENR, pos); - break; - - default: - break; - } - } - else { - switch (idx) { - case 0: - CLEAR_BIT(CMU->AHB1ENR, pos); - break; - - case 1: - CLEAR_BIT(CMU->APB1ENR, pos); - break; - - case 2: - CLEAR_BIT(CMU->APB2ENR, pos); - break; - - default: - break; - } - } - - SYSCFG_LOCK(); - return; -} - -/** - * @} - */ -/** - * @} - */ - -/** - * @} - */ - -/** - * @} - */ diff --git a/bsp/essemi/es32f0334/libraries/ES32F033x_ALD_StdPeriph_Driver/Source/ald_crc.c b/bsp/essemi/es32f0334/libraries/ES32F033x_ALD_StdPeriph_Driver/Source/ald_crc.c deleted file mode 100644 index bf6fde037c..0000000000 --- a/bsp/essemi/es32f0334/libraries/ES32F033x_ALD_StdPeriph_Driver/Source/ald_crc.c +++ /dev/null @@ -1,514 +0,0 @@ -/** - ********************************************************************************* - * - * @file ald_crc.c - * @brief CRC module driver. - * - * @version V1.0 - * @date 6 Dec 2017 - * @author AE Team - * @note - * - * Copyright (C) Shanghai Eastsoft Microelectronics Co. Ltd. All rights reserved. - * - ********************************************************************************* - */ - -#include "ald_crc.h" - -/** @addtogroup ES32FXXX_ALD - * @{ - */ - -/** @defgroup CRC CRC - * @brief CRC module driver - * @{ - */ -#ifdef ALD_CRC - -/** @addtogroup CRC_Private_Functions CRC Private Functions - * @{ - */ -void ald_crc_reset(crc_handle_t *hperh); -#ifdef ALD_DMA -static void crc_dma_calculate_cplt(void *arg); -static void crc_dma_error(void *arg); -#endif -/** - * @} - */ - - -/** @defgroup CRC_Public_Functions CRC Public Functions - * @{ - */ - -/** @defgroup CRC_Public_Functions_Group1 Initialization functions - * @brief Initialization and Configuration functions - * @{ - */ - -/** - * @brief Initializes the CRC mode according to the specified parameters in - * the crc_handle_t and create the associated handle. - * @param hperh: Pointer to a crc_handle_t structure that contains - * the configuration information for the specified CRC module. - * @retval Status, see @ref ald_status_t. - */ -ald_status_t ald_crc_init(crc_handle_t *hperh) -{ - uint32_t tmp = 0; - - if (hperh == NULL) - return ERROR; - - assert_param(IS_CRC(hperh->perh)); - assert_param(IS_CRC_MODE(hperh->init.mode)); - assert_param(IS_FUNC_STATE(hperh->init.chs_rev)); - assert_param(IS_FUNC_STATE(hperh->init.data_inv)); - assert_param(IS_FUNC_STATE(hperh->init.data_rev)); - assert_param(IS_FUNC_STATE(hperh->init.chs_inv)); - - ald_crc_reset(hperh); - __LOCK(hperh); - - CRC_ENABLE(hperh); - - tmp = hperh->perh->CR; - - tmp |= ((hperh->init.chs_rev << CRC_CR_CHSREV_POS) | (hperh->init.data_inv << CRC_CR_DATREV_POS) | - (hperh->init.chs_inv << CRC_CR_CHSINV_POS) | (hperh->init.mode << CRC_CR_MODE_POSS) | - (CRC_DATASIZE_8 << CRC_CR_DATLEN_POSS) | (hperh->init.data_rev << CRC_CR_DATREV_POS) | - (0 << CRC_CR_BYTORD_POS)); - - hperh->perh->CR = tmp; - hperh->perh->SEED = hperh->init.seed; - CRC_RESET(hperh); - - hperh->state = CRC_STATE_READY; - - __UNLOCK(hperh); - return OK; -} - -/** - * @} - */ - -/** @defgroup CRC_Public_Functions_Group2 Calculate functions - * @brief Calculate functions - * @{ - */ - -/** - * @brief Calculate the crc value of data by byte. - * @param hperh: Pointer to a crc_handle_t structure that contains - * the configuration information for the specified CRC module. - * @param buf: Pointer to data buffer - * @param size: The size of data to be calculate - * @retval result, the result of a amount data - */ -uint32_t ald_crc_calculate(crc_handle_t *hperh, uint8_t *buf, uint32_t size) -{ - uint32_t i; - uint32_t ret; - - assert_param(IS_CRC(hperh->perh)); - - if (buf == NULL || size == 0) - return 0; - - __LOCK(hperh); - MODIFY_REG(hperh->perh->CR, CRC_CR_DATLEN_MSK, CRC_DATASIZE_8 << CRC_CR_DATLEN_POSS); - hperh->state = CRC_STATE_BUSY; - - for (i = 0; i < size; i++) - *((volatile uint8_t *)&(hperh->perh->DATA)) = buf[i]; - - ret = CRC->CHECKSUM; - hperh->state = CRC_STATE_READY; - __UNLOCK(hperh); - - return ret; -} - -/** - * @brief Calculate the crc value of data by halfword. - * @param hperh: Pointer to a crc_handle_t structure that contains - * the configuration information for the specified CRC module. - * @param buf: Pointer to data buffer - * @param size: The size of data to be calculate,width is 2 bytes. - * @retval result, the result of a amount data - */ -uint32_t ald_crc_calculate_halfword(crc_handle_t *hperh, uint16_t *buf, uint32_t size) -{ - uint32_t i; - uint32_t ret; - - assert_param(IS_CRC(hperh->perh)); - - if (buf == NULL || size == 0) - return 0; - - __LOCK(hperh); - MODIFY_REG(hperh->perh->CR, CRC_CR_DATLEN_MSK, CRC_DATASIZE_16 << CRC_CR_DATLEN_POSS); - hperh->state = CRC_STATE_BUSY; - - for (i = 0; i < size; i++) - *((volatile uint16_t *)&(hperh->perh->DATA)) = buf[i]; - - ret = CRC->CHECKSUM; - hperh->state = CRC_STATE_READY; - __UNLOCK(hperh); - - return ret; -} - -/** - * @brief Calculate the crc value of data by word. - * @param hperh: Pointer to a crc_handle_t structure that contains - * the configuration information for the specified CRC module. - * @param buf: Pointer to data buffer - * @param size: The size of data to be calculate,width is 4 bytes - * @retval result, the result of a amount data - */ -uint32_t ald_crc_calculate_word(crc_handle_t *hperh, uint32_t *buf, uint32_t size) -{ - uint32_t i; - uint32_t ret; - - assert_param(IS_CRC(hperh->perh)); - - if (buf == NULL || size == 0) - return 0; - - __LOCK(hperh); - MODIFY_REG(hperh->perh->CR, CRC_CR_DATLEN_MSK, CRC_DATASIZE_32 << CRC_CR_DATLEN_POSS); - hperh->state = CRC_STATE_BUSY; - - for (i = 0; i < size; i++) - CRC->DATA = buf[i]; - - ret = CRC->CHECKSUM; - hperh->state = CRC_STATE_READY; - __UNLOCK(hperh); - - return ret; -} - -/** - * @} - */ - -#ifdef ALD_DMA -/** @defgroup CRC_Public_Functions_Group3 DMA operation functions - * @brief DMA operation functions - * @{ - */ - -/** - * @brief Calculate an amount of data used dma channel - * @param hperh: Pointer to a crc_handle_t structure that contains - * the configuration information for the specified CRC module. - * @param buf: Pointer to data buffer - * @param res: Pointer to result - * @param size: Amount of data to be Calculate - * @param channel: DMA channel as CRC transmit - * @retval Status, see @ref ald_status_t. - */ -ald_status_t ald_crc_calculate_by_dma(crc_handle_t *hperh, uint8_t *buf, uint32_t *res, uint16_t size, uint8_t channel) -{ - if (hperh->state != CRC_STATE_READY) - return BUSY; - - if (buf == NULL || size == 0) - return ERROR; - - __LOCK(hperh); - MODIFY_REG(hperh->perh->CR, CRC_CR_DATLEN_MSK, CRC_DATASIZE_8 << CRC_CR_DATLEN_POSS); - - hperh->state = CRC_STATE_BUSY; - - hperh->cal_buf = buf; - hperh->cal_res = res; - - if (hperh->hdma.perh == NULL) - hperh->hdma.perh = DMA0; - - hperh->hdma.cplt_arg = (void *)hperh; - hperh->hdma.cplt_cbk = &crc_dma_calculate_cplt; - hperh->hdma.err_arg = (void *)hperh; - hperh->hdma.err_cbk = &crc_dma_error; - - ald_dma_config_struct(&(hperh->hdma.config)); - hperh->hdma.config.data_width = DMA_DATA_SIZE_BYTE; - hperh->hdma.config.src = (void *)buf; - hperh->hdma.config.dst = (void *)&hperh->perh->DATA; - hperh->hdma.config.size = size; - hperh->hdma.config.src_inc = DMA_DATA_INC_BYTE; - hperh->hdma.config.dst_inc = DMA_DATA_INC_NONE; - hperh->hdma.config.msel = DMA_MSEL_CRC; - hperh->hdma.config.msigsel = DMA_MSIGSEL_NONE; - hperh->hdma.config.channel = channel; - ald_dma_config_basic(&(hperh->hdma)); - - __UNLOCK(hperh); - CRC_DMA_ENABLE(hperh); - - return OK; -} - -/** - * @brief Calculate an amount of data used dma channel,data width is half-word. - * @param hperh: Pointer to a crc_handle_t structure that contains - * the configuration information for the specified CRC module. - * @param buf: Pointer to half_word data buffer - * @param res: Pointer to result - * @param size: Amount of half_word data to be Calculate - * @param channel: DMA channel as CRC transmit - * @retval Status, see @ref ald_status_t. - */ -ald_status_t ald_crc_calculate_halfword_by_dma(crc_handle_t *hperh, uint16_t *buf, uint32_t *res, uint16_t size, uint8_t channel) -{ - if (hperh->state != CRC_STATE_READY) - return BUSY; - - if (buf == NULL || size == 0) - return ERROR; - - __LOCK(hperh); - MODIFY_REG(hperh->perh->CR, CRC_CR_DATLEN_MSK, CRC_DATASIZE_16 << CRC_CR_DATLEN_POSS); - - hperh->state = CRC_STATE_BUSY; - - hperh->cal_buf = (uint8_t *)buf; - hperh->cal_res = res; - - if (hperh->hdma.perh == NULL) - hperh->hdma.perh = DMA0; - - hperh->hdma.cplt_arg = (void *)hperh; - hperh->hdma.cplt_cbk = &crc_dma_calculate_cplt; - hperh->hdma.err_arg = (void *)hperh; - hperh->hdma.err_cbk = &crc_dma_error; - - ald_dma_config_struct(&(hperh->hdma.config)); - hperh->hdma.config.data_width = DMA_DATA_SIZE_HALFWORD; - hperh->hdma.config.src = (void *)buf; - hperh->hdma.config.dst = (void *)&hperh->perh->DATA; - hperh->hdma.config.size = size; - hperh->hdma.config.src_inc = DMA_DATA_INC_HALFWORD; - hperh->hdma.config.dst_inc = DMA_DATA_INC_NONE; - hperh->hdma.config.msel = DMA_MSEL_CRC; - hperh->hdma.config.msigsel = DMA_MSIGSEL_NONE; - hperh->hdma.config.channel = channel; - ald_dma_config_basic(&(hperh->hdma)); - - __UNLOCK(hperh); - CRC_DMA_ENABLE(hperh); - - return OK; -} - -/** - * @brief Calculate an amount of data used dma channel,data width is word. - * @param hperh: Pointer to a crc_handle_t structure that contains - * the configuration information for the specified CRC module. - * @param buf: Pointer to word data buffer - * @param res: Pointer to result - * @param size: Amount of word data to be Calculate - * @param channel: DMA channel as CRC transmit - * @retval Status, see @ref ald_status_t. - */ -ald_status_t ald_crc_calculate_word_by_dma(crc_handle_t *hperh, uint32_t *buf, uint32_t *res, uint16_t size, uint8_t channel) -{ - if (hperh->state != CRC_STATE_READY) - return BUSY; - - if (buf == NULL || size == 0) - return ERROR; - - __LOCK(hperh); - MODIFY_REG(hperh->perh->CR, CRC_CR_DATLEN_MSK, CRC_DATASIZE_32 << CRC_CR_DATLEN_POSS); - - hperh->state = CRC_STATE_BUSY; - - hperh->cal_buf = (uint8_t *)buf; - hperh->cal_res = res; - - if (hperh->hdma.perh == NULL) - hperh->hdma.perh = DMA0; - - hperh->hdma.cplt_arg = (void *)hperh; - hperh->hdma.cplt_cbk = &crc_dma_calculate_cplt; - hperh->hdma.err_arg = (void *)hperh; - hperh->hdma.err_cbk = &crc_dma_error; - - ald_dma_config_struct(&(hperh->hdma.config)); - hperh->hdma.config.data_width = DMA_DATA_SIZE_WORD; - hperh->hdma.config.src = (void *)buf; - hperh->hdma.config.dst = (void *)&hperh->perh->DATA; - hperh->hdma.config.size = size; - hperh->hdma.config.src_inc = DMA_DATA_INC_WORD; - hperh->hdma.config.dst_inc = DMA_DATA_INC_NONE; - hperh->hdma.config.msel = DMA_MSEL_CRC; - hperh->hdma.config.msigsel = DMA_MSIGSEL_NONE; - hperh->hdma.config.channel = channel; - ald_dma_config_basic(&(hperh->hdma)); - - __UNLOCK(hperh); - CRC_DMA_ENABLE(hperh); - - return OK; -} - - -/** - * @brief Pauses the DMA Transfer. - * @param hperh: Pointer to a crc_handle_t structure that contains - * the configuration information for the specified CRC module. - * @retval Status, see @ref ald_status_t. - */ -ald_status_t ald_crc_dma_pause(crc_handle_t *hperh) -{ - __LOCK(hperh); - CRC_DMA_DISABLE(hperh); - __UNLOCK(hperh); - - return OK; -} - -/** - * @brief Resumes the DMA Transfer. - * @param hperh: Pointer to a crc_handle_t structure that contains - * the configuration information for the specified CRC module. - * @retval Status, see @ref ald_status_t. - */ -ald_status_t ald_crc_dma_resume(crc_handle_t *hperh) -{ - __LOCK(hperh); - CRC_DMA_ENABLE(hperh); - __UNLOCK(hperh); - - return OK; -} - -/** - * @brief Stops the DMA Transfer. - * @param hperh: Pointer to a crc_handle_t structure that contains - * the configuration information for the specified CRC module. - * @retval Status, see @ref ald_status_t. - */ -ald_status_t ald_crc_dma_stop(crc_handle_t *hperh) -{ - __LOCK(hperh); - CRC_DMA_DISABLE(hperh); - __UNLOCK(hperh); - - hperh->state = CRC_STATE_READY; - return OK; -} - -/** - * @} - */ -#endif - -/** @defgroup CRC_Public_Functions_Group4 Peripheral State and Errors functions - * @brief CRC State and Errors functions - * @{ - */ - -/** - * @brief Returns the CRC state. - * @param hperh: Pointer to a crc_handle_t structure that contains - * the configuration information for the specified CRC module. - * @retval CRC state - */ -crc_state_t ald_crc_get_state(crc_handle_t *hperh) -{ - assert_param(IS_CRC(hperh->perh)); - - return hperh->state; -} -/** - * @} - */ - -/** - * @} - */ - -/** @defgroup CRC_Private_Functions CRC Private Functions - * @brief CRC Private functions - * @{ - */ - -/** - * @brief Reset the CRC peripheral. - * @param hperh: Pointer to a crc_handle_t structure that contains - * the configuration information for the specified CRC module. - * @retval None - */ -void ald_crc_reset(crc_handle_t *hperh) -{ - hperh->perh->DATA = 0x0; - hperh->perh->CR = 0x2; - hperh->perh->SEED = 0xFFFFFFFF; - - hperh->state = CRC_STATE_READY; - __UNLOCK(hperh); - return; -} - -#ifdef ALD_DMA -/** - * @brief DMA CRC calculate process complete callback. - * @param arg: Pointer to a crc_handle_t structure that contains - * the configuration information for the specified CRC module. - * @retval None - */ -static void crc_dma_calculate_cplt(void *arg) -{ - crc_handle_t *hperh = (crc_handle_t *)arg; - - *(hperh->cal_res) = CRC->CHECKSUM; - CRC_DMA_DISABLE(hperh); - - hperh->state = CRC_STATE_READY; - - if (hperh->cal_cplt_cbk) - hperh->cal_cplt_cbk(hperh); -} - -/** - * @brief DMA CRC communication error callback. - * @param arg: Pointer to a crc_handle_t structure that contains - * the configuration information for the specified CRC module. - * @retval None - */ -static void crc_dma_error(void *arg) -{ - crc_handle_t *hperh = (crc_handle_t *)arg; - - CRC_CLEAR_ERROR_FLAG(hperh); - CRC_DMA_DISABLE(hperh); - - hperh->state = CRC_STATE_READY; - - if (hperh->err_cplt_cbk) - hperh->err_cplt_cbk(hperh); -} -#endif -/** - * @} - */ -#endif /* ALD_CRC */ - -/** - * @} - */ - -/** - * @} - */ diff --git a/bsp/essemi/es32f0334/libraries/ES32F033x_ALD_StdPeriph_Driver/Source/ald_crypt.c b/bsp/essemi/es32f0334/libraries/ES32F033x_ALD_StdPeriph_Driver/Source/ald_crypt.c deleted file mode 100644 index ff8f92d9d5..0000000000 --- a/bsp/essemi/es32f0334/libraries/ES32F033x_ALD_StdPeriph_Driver/Source/ald_crypt.c +++ /dev/null @@ -1,996 +0,0 @@ -/** - ********************************************************************************* - * - * @file ald_crypt.c - * @brief CRYPT module driver. - * This is the common part of the CRYPT initialization - * - * @version V1.0 - * @date 7 Dec 2017 - * @author AE Team - * @note - * - * Copyright (C) Shanghai Eastsoft Microelectronics Co. Ltd. All rights reserved. - * - ********************************************************************************* - */ - - -#include "ald_crypt.h" - - -/** @addtogroup ES32FXXX_ALD - * @{ - */ - -/** @defgroup CRYPT CRYPT - * @brief CRYPT module driver - * @{ - */ -#ifdef ALD_CRYPT - -/** @addtogroup CRYPT_Private_Functions CRYPT Private Functions - * @{ - */ -void crypt_reset(crypt_handle_t *hperh); -#ifdef ALD_DMA -static void crypt_dma_crypt_cplt(void *arg); -static void crypt_dma_error(void *arg); -#endif -/** - * @} - */ - - -/** @defgroup CRYPT_Public_Functions CRYPT Public Functions - * @{ - */ - -/** @defgroup CRYPT_Public_Functions_Group1 Initialization functions - * @brief Initialization and Configuration functions - * @{ - */ - -/** - * @brief Initializes the CRYPT mode according to the specified parameters in - * the crypt_init_t and create the associated handle. - * @param hperh: Pointer to a crypt_handle_t structure that contains - * the configuration information for the specified CRYPT module. - * @retval Status, see @ref ald_status_t. - */ -ald_status_t ald_crypt_init(crypt_handle_t *hperh) -{ - uint32_t tmp = 0; - - if (hperh == NULL) - return ERROR; - - assert_param(IS_CRYPT(hperh->perh)); - assert_param(IS_CRYPT_MODE(hperh->init.mode)); - - __LOCK(hperh); - crypt_reset(hperh); - - if (hperh->state == CRYPT_STATE_RESET) - __UNLOCK(hperh); - - tmp = hperh->perh->CON; - hperh->step = 4; - tmp |= ((1 << CRYPT_CON_FIFOODR_POS) | (hperh->init.mode << CRYPT_CON_MODE_POSS) | \ - (hperh->init.type << CRYPT_CON_TYPE_POSS) | (1 << CRYPT_CON_FIFOEN_POS)); - WRITE_REG(hperh->perh->CON, tmp); - hperh->state = CRYPT_STATE_READY; - __UNLOCK(hperh); - - return OK; -} - -/** - * @brief Write the Content of KEY. - * @param hperh: Pointer to a crypt_handle_t structure that contains - * the configuration information for the specified CRYPT module. - * @param key: Pointer to key data buffer - * @retval Status, see @ref ald_status_t. - */ -ald_status_t ald_crypt_write_key(crypt_handle_t *hperh, uint32_t *key) -{ - uint32_t *temp = key; - uint32_t i; - - if ((hperh == NULL) || (key == NULL)) - return ERROR; - if (hperh->state == CRYPT_STATE_BUSY) - return BUSY; - - assert_param(IS_CRYPT(hperh->perh)); - - hperh->perh->KEY[3] = *temp++; - hperh->perh->KEY[2] = *temp++; - hperh->perh->KEY[1] = *temp++; - hperh->perh->KEY[0] = *temp; - - for (i = 0; i < 4; i++) - hperh->key[i] = *key++; - - return OK; -} - -/** - * @brief Read the Content of KEY. - * @param hperh: Pointer to a crypt_handle_t structure that contains - * the configuration information for the specified CRYPT module. - * @param key: The pointer to the key - * @retval Status, see @ref ald_status_t. - */ -ald_status_t ald_crypt_read_key(crypt_handle_t *hperh, uint32_t *key) -{ - uint32_t *temp = key; - - if ((hperh == NULL) || (key == NULL)) - return ERROR; - if (hperh->state == CRYPT_STATE_BUSY) - return BUSY; - - assert_param(IS_CRYPT(hperh->perh)); - - *temp++ = hperh->perh->KEY[3]; - *temp++ = hperh->perh->KEY[2]; - *temp++ = hperh->perh->KEY[1]; - *temp = hperh->perh->KEY[0]; - - return OK; -} - -/** - * @brief Write the Content of IV if you use CBC mode - * @param hperh: Pointer to a crypt_handle_t structure that contains - * the configuration information for the specified CRYPT module. - * @param iv: Pointer to iv data buffer - * @retval Status, see @ref ald_status_t. - */ -ald_status_t ald_crypt_write_ivr(crypt_handle_t *hperh, uint32_t *iv) -{ - uint32_t *temp = iv; - uint32_t i; - - if ((hperh == NULL) || (iv == NULL)) - return ERROR; - if (hperh->state == CRYPT_STATE_BUSY) - return BUSY; - - assert_param(IS_CRYPT(hperh->perh)); - - hperh->perh->IV[3] = *temp++; - hperh->perh->IV[2] = *temp++; - hperh->perh->IV[1] = *temp++; - hperh->perh->IV[0] = *temp; - - for (i = 0; i < 4; i++) - hperh->iv[i] = *iv++; - - CRYPT_IVEN_ENABLE(hperh); - return OK; -} - -/** - * @brief Read the Content of IV. - * @param hperh: Pointer to a crypt_handle_t structure that contains - * the configuration information for the specified CRYPT module. - * @param iv: Pointer to iv data buffer - * @retval Status, see @ref ald_status_t. - */ -ald_status_t ald_crypt_read_ivr(crypt_handle_t *hperh, uint32_t *iv) -{ - uint32_t *temp = iv; - - if ((hperh == NULL) || (iv == NULL)) - return ERROR; - if (hperh->state == CRYPT_STATE_BUSY) - return BUSY; - - assert_param(IS_CRYPT(hperh->perh)); - - *temp++ = hperh->perh->IV[3]; - *temp++ = hperh->perh->IV[2]; - *temp++ = hperh->perh->IV[1]; - *temp = hperh->perh->IV[0]; - - return OK; -} - -/** - * @} - */ - -/** @defgroup CRYPT_Public_Functions_Group2 Encrypt or Decrypt functions - * @brief Encrypt or Decrypt functions - * @{ - */ - -/** - * @brief Encrypt an amount of data in blocking mode. - * @param hperh: Pointer to a crypt_handle_t structure that contains - * the configuration information for the specified CRYPT module. - * @param plain_text: Pointer to plain data buffer - * @param cipher_text: Pointer to cipher data buffer - * @param size: Amount of plain data - * @retval Status, see @ref ald_status_t. - * @note the size is multiple of 16(ase) - */ -ald_status_t ald_crypt_encrypt(crypt_handle_t *hperh, uint8_t *plain_text, uint8_t *cipher_text, uint32_t size) -{ - uint32_t count = 0; - uint32_t i; - uint32_t *plain_buf = (uint32_t *)plain_text; - uint32_t *cipher_buf = (uint32_t *)cipher_text; - - if (hperh->state != CRYPT_STATE_READY) - return ERROR; - - if ((plain_buf == NULL) || (cipher_buf == NULL) || (size == 0)) - return ERROR; - - assert_param(IS_CRYPT(hperh->perh)); - - __LOCK(hperh); - hperh->state = CRYPT_STATE_BUSY; - CRYPT_SETDIR(hperh, CRYPT_ENCRYPT); - count = size / (4 * hperh->step); - - while (count--) { - for (i = 0; i < hperh->step; i++) { - CRYPT_WRITE_FIFO(hperh, *plain_buf); - plain_buf++; - } - - while (ald_crypt_get_flag_status(hperh, CRYPT_FLAG_DONE) == SET); - - for (i = 0; i < hperh->step; i++) { - *cipher_buf = CRYPT_READ_FIFO(hperh); - cipher_buf++; - } - } - - hperh->state = CRYPT_STATE_READY; - __UNLOCK(hperh); - - return OK; -} - -/** - * @brief Decrypt an amount of data in blocking mode. - * @param hperh: Pointer to a crypt_handle_t structure that contains - * the configuration information for the specified CRYPT module. - * @param cipher_text: Pointer to cipher data buffer - * @param plain_text: Pointer to plain data buffer - * @param size: Amount of cipher data - * @retval Status, see @ref ald_status_t. - * @note the size is multiple of 16(ase) - */ -ald_status_t ald_crypt_decrypt(crypt_handle_t *hperh, uint8_t *cipher_text, uint8_t *plain_text, uint32_t size) -{ - uint32_t count = 0; - uint32_t i; - uint32_t *plain_buf = (uint32_t*)plain_text; - uint32_t *cipher_buf = (uint32_t*)cipher_text; - - if (hperh->init.mode == CRYPT_MODE_CTR) { - return ald_crypt_encrypt(hperh, cipher_text, plain_text, size); - } - - if (hperh->state != CRYPT_STATE_READY) - return ERROR; - - if ((plain_buf == NULL) || (cipher_buf == NULL) || (size == 0)) - return ERROR; - - assert_param(IS_CRYPT(hperh->perh)); - - __LOCK(hperh); - hperh->state = CRYPT_STATE_BUSY; - CRYPT_SETDIR(hperh, CRYPT_DECRYPT); - count = size / (4 * hperh->step); - - while (count--) { - for (i = 0; i < hperh->step; i++) { - CRYPT_WRITE_FIFO(hperh, *cipher_buf); - cipher_buf++; - } - - while (ald_crypt_get_flag_status(hperh, CRYPT_FLAG_DONE) == SET); - - for (i = 0; i < hperh->step; i++) { - *plain_buf = CRYPT_READ_FIFO(hperh); - plain_buf++; - } - } - - hperh->state = CRYPT_STATE_READY; - __UNLOCK(hperh); - - return OK; -} - -void gcm_mul(uint32_t *res, uint32_t *data, uint32_t *iv) -{ - CRYPT->CON = 0; - CRYPT->DATA[0] = data[3]; - CRYPT->DATA[1] = data[2]; - CRYPT->DATA[2] = data[1]; - CRYPT->DATA[3] = data[0]; - CRYPT->IV[0] = iv[3]; - CRYPT->IV[1] = iv[2]; - CRYPT->IV[2] = iv[1]; - CRYPT->IV[3] = iv[0]; - CRYPT->CON |= ((1 << CRYPT_CON_RESCLR_POS) | (3 << CRYPT_CON_MODE_POSS) | \ - (1 << CRYPT_CON_GO_POS)); - - while (READ_BIT(CRYPT->IF, CRYPT_IF_MULTHIF_MSK) == 0); - - res[3] = CRYPT->RES[0]; - res[2] = CRYPT->RES[1]; - res[1] = CRYPT->RES[2]; - res[0] = CRYPT->RES[3]; - - WRITE_REG(CRYPT->IFC, CRYPT_IFC_MULTHIFC_MSK); - return; -} - -/** - * @brief verify an amount of data in gcm mode. - * @param hperh: Pointer to a crypt_handle_t structure that contains - * the configuration information for the specified CRYPT module. - * @param cipher_text: Pointer to cipher data buffer - * @param size: Amount of cipher data - * @param aadata: Pointer to additional authenticated data buffer - * @param alen: Amount of additional authenticated data - * @param tag: Pointer to authentication tag buffer - * @retval Status, see @ref ald_status_t. - */ -ald_status_t ald_crypt_gcm_verify(crypt_handle_t *hperh, uint8_t *cipher_text, uint32_t size, uint8_t *aadata, uint32_t alen, uint8_t *tag) -{ - uint8_t GCM_HASH_in[0x60] = {0}; - uint8_t ecb[16] = {0}; - uint32_t x_temp[4]; - uint64_t u, v; - uint32_t len = 0; - uint32_t j, i, k; - uint32_t *tag_temp, *cipher_text_temp; - - /* calculate u and v */ - u = 128 * ((size % 16) ? (size / 16 + 1) : size / 16) - size * 8; - v = 128 * ((alen % 16) ? (alen / 16 + 1): alen / 16) - alen * 8; - - /* get the input of GHASH algorithm,the input:A||0^v||C||0^u||[len(A)]_64||[len(C)]_64 */ - for (i = 0; i < alen; i++) { - GCM_HASH_in [i] = * (aadata + i); - } - len += alen; - for (i = 0; i < v / 8; i++) { - GCM_HASH_in[i + len] = 0; - } - len += v / 8; - for (i = 0; i < size; i++) { - GCM_HASH_in[i + len] = * (cipher_text + i); - } - len += size; - for (i = 0; i < u / 8; i++) { - GCM_HASH_in[i + len] = 0; - } - len += u / 8; - - for (i = 0; i < 4; i++) { - GCM_HASH_in[i + len] = 0; - } - len += 4; - - for (i = 0; i < 4; i++) { - GCM_HASH_in[i + len] = ((alen * 8) >> (8 * i)) & 0xFF; - } - len += 4; - - for (i = 0; i < 4; i++) { - GCM_HASH_in[i + len] = 0; - } - len += 4; - - for (i = 0; i < 4; i++) { - GCM_HASH_in[i + len] = ((size * 8) >> (8 * i)) & 0xFF; - } - len += 4; - - CRYPT->CON &= ~(3U << CRYPT_CON_MODE_POSS); - CRYPT->CON |= (CRYPT_MODE_ECB << CRYPT_CON_MODE_POSS); - - ald_crypt_encrypt(hperh, ecb, ecb, 16); - - k = len / 16; - for (i = 0; i < 16; i++) { - tag[i] = 0; - } - - cipher_text_temp = (uint32_t *)GCM_HASH_in; - tag_temp = (uint32_t *)tag; - for (i = 0; i < k; i++) { - for (j = 0; j < 4; j++) { - x_temp[j] = (*cipher_text_temp) ^ tag_temp[j]; - ++cipher_text_temp; - } - - gcm_mul((uint32_t *)tag_temp, x_temp, (uint32_t *)ecb); - } - - /* calculate the authentication tag T, - * T = CIPH_K(J0)^S,J0=IV||0^31||1,CIPH_K is the algorithm of AES in ECB mode - */ - tag_temp = (uint32_t *)tag; - ald_crypt_init(hperh); - CRYPT->CON &= ~(3U << CRYPT_CON_MODE_POSS); - CRYPT->CON |= (CRYPT_MODE_CTR << CRYPT_CON_MODE_POSS); - ald_crypt_write_key(hperh, hperh->key); - hperh->iv[3] = 1; - ald_crypt_write_ivr(hperh, hperh->iv); - ald_crypt_encrypt(hperh, tag, tag, 16); - - return OK; -} - -/** - * @brief Encrypt an amount of data in non-blocking mode. - * @param hperh: Pointer to a crypt_handle_t structure that contains - * the configuration information for the specified CRYPT module. - * @param plain_text: Pointer to plain data buffer - * @param cipher_text: Pointer to cipher data buffer - * @param size: Amount of plain data - * @retval Status, see @ref ald_status_t. - * @note the size is multiple of 16(ase) - */ -ald_status_t ald_crypt_encrypt_by_it(crypt_handle_t *hperh, uint8_t * plain_text, uint8_t *cipher_text, uint32_t size) -{ - uint32_t i; - uint32_t *plain_buf = (uint32_t *)plain_text; - - if (hperh->state != CRYPT_STATE_READY) - return ERROR; - - if ((plain_text == NULL) || (cipher_text == NULL) || (size == 0)) - return ERROR; - - assert_param(IS_CRYPT(hperh->perh)); - - __LOCK(hperh); - hperh->state = CRYPT_STATE_BUSY; - CRYPT_SETDIR(hperh, CRYPT_ENCRYPT); - hperh->count = hperh->step; - hperh->plain_text = plain_text; - hperh->cipher_text = cipher_text; - hperh->size = size; - ald_crypt_interrupt_config(hperh, CRYPT_IT_IT, ENABLE); - - for (i = 0; i < hperh->step; i++) { - CRYPT_WRITE_FIFO(hperh, *plain_buf); - ++plain_buf; - } - - __UNLOCK(hperh); - return OK; -} - -/** - * @brief Decrypt an amount of data in non-blocking mode. - * @param hperh: Pointer to a crypt_handle_t structure that contains - * the configuration information for the specified CRYPT module. - * @param plain_text: Pointer to plain data buffer - * @param cipher_text: Pointer to cipher data buffer - * @param size: Amount of cipher data - * @retval Status, see @ref ald_status_t. - * @note the size is multiple of 16(ase) - */ -ald_status_t ald_crypt_decrypt_by_it(crypt_handle_t *hperh, uint8_t *cipher_text, uint8_t *plain_text, uint32_t size) -{ - uint32_t i; - uint32_t *cipher_buf = (uint32_t*)cipher_text; - - if (hperh->init.mode == CRYPT_MODE_CTR) { - return ald_crypt_decrypt_by_it(hperh, cipher_text, plain_text, size); - } - - if (hperh->state != CRYPT_STATE_READY) - return ERROR; - - if ((plain_text == NULL) || (cipher_text == NULL) || (size == 0)) - return ERROR; - - assert_param(IS_CRYPT(hperh->perh)); - - __LOCK(hperh); - hperh->state = CRYPT_STATE_BUSY; - CRYPT_SETDIR(hperh, CRYPT_DECRYPT); - hperh->count = hperh->step; - hperh->plain_text = plain_text; - hperh->cipher_text = cipher_text; - hperh->size = size; - ald_crypt_interrupt_config(hperh, CRYPT_IT_IT, ENABLE); - - for (i = 0; i < hperh->step; i++) { - CRYPT_WRITE_FIFO(hperh, *cipher_buf); - cipher_buf++; - } - - __UNLOCK(hperh); - return OK; -} - -#ifdef ALD_DMA -/** - * @brief Encrypt an amount of data in non-blocking mode. - * @param hperh: Pointer to a crypt_handle_t structure that contains - * the configuration information for the specified CRYPT module. - * @param plain_text: Pointer to plain data buffer - * @param cipher_text: Pointer to cipher data buffer - * @param size: Amount of plain data - * @param channel_m2p: Memory to Crypt module DMA channel - * @param channel_p2m: Crypt module to Memory DMA channel - * @retval Status, see @ref ald_status_t. - * @note the size is multiple of 16(ase) - */ -ald_status_t ald_crypt_encrypt_by_dma(crypt_handle_t *hperh, uint8_t * plain_text, - uint8_t *cipher_text, uint32_t size, uint8_t channel_m2p, uint8_t channel_p2m) -{ - if (hperh->state != CRYPT_STATE_READY) - return ERROR; - - if (plain_text == NULL || cipher_text == NULL || size == 0) - return ERROR; - - assert_param(IS_CRYPT(hperh->perh)); - - __LOCK(hperh); - hperh->state = CRYPT_STATE_BUSY; - - hperh->plain_text = plain_text; - hperh->cipher_text = cipher_text; - hperh->size = size; - hperh->count = size; - - if (hperh->hdma_m2p.perh == NULL) - hperh->hdma_m2p.perh = DMA0; - if (hperh->hdma_p2m.perh == NULL) - hperh->hdma_p2m.perh = DMA0; - - hperh->hdma_m2p.cplt_arg = NULL; - hperh->hdma_m2p.cplt_cbk = NULL; - hperh->hdma_m2p.err_arg = NULL; - hperh->hdma_m2p.err_cbk = NULL; - - hperh->hdma_p2m.cplt_arg = (void *)hperh; - hperh->hdma_p2m.cplt_cbk = &crypt_dma_crypt_cplt; - hperh->hdma_p2m.err_arg = (void *)hperh; - hperh->hdma_p2m.err_cbk = &crypt_dma_error; - - CRYPT_SETDIR(hperh, CRYPT_ENCRYPT); - - ald_dma_config_struct(&hperh->hdma_m2p.config); - hperh->hdma_m2p.config.data_width = DMA_DATA_SIZE_WORD; - hperh->hdma_m2p.config.src = (void *)hperh->plain_text; - hperh->hdma_m2p.config.dst = (void *)&hperh->perh->FIFO; - hperh->hdma_m2p.config.size = size / 4; - hperh->hdma_m2p.config.src_inc = DMA_DATA_INC_WORD; - hperh->hdma_m2p.config.dst_inc = DMA_DATA_INC_NONE; - hperh->hdma_m2p.config.msel = DMA_MSEL_CRYPT; - hperh->hdma_m2p.config.msigsel = DMA_MSIGSEL_CRYPT_WRITE; - hperh->hdma_m2p.config.channel = channel_m2p; - ald_dma_config_basic(&(hperh->hdma_m2p)); - - ald_dma_config_struct(&hperh->hdma_p2m.config); - hperh->hdma_p2m.config.data_width = DMA_DATA_SIZE_WORD; - hperh->hdma_p2m.config.src = (void *)&hperh->perh->FIFO; - hperh->hdma_p2m.config.dst = (void *)hperh->cipher_text; - hperh->hdma_p2m.config.size = size / 4; - hperh->hdma_p2m.config.src_inc = DMA_DATA_INC_NONE; - hperh->hdma_p2m.config.dst_inc = DMA_DATA_INC_WORD; - hperh->hdma_p2m.config.msel = DMA_MSEL_CRYPT; - hperh->hdma_p2m.config.msigsel = DMA_MSIGSEL_CRYPT_READ; - hperh->hdma_p2m.config.channel = channel_p2m; - ald_dma_config_basic(&(hperh->hdma_p2m)); - - CRYPT_DMA_ENABLE(hperh); - __UNLOCK(hperh); - - return OK; -} - -/** - * @brief Decrypt an amount of data in non-blocking mode. - * @param hperh: Pointer to a crypt_handle_t structure that contains - * the configuration information for the specified CRYPT module. - * @param plain_text: Pointer to plain data buffer - * @param cipher_text: Pointer to cipher data buffer - * @param size: Amount of cipher data - * @param channel_m2p: Memory to Crypt module DMA channel - * @param channel_p2m: Crypt module to Memory DMA channel - * @retval Status, see @ref ald_status_t. - * @note the size is multiple of 16(ase) - */ -ald_status_t ald_crypt_decrypt_by_dma(crypt_handle_t *hperh, uint8_t * cipher_text, - uint8_t *plain_text, uint32_t size, uint8_t channel_m2p, uint8_t channel_p2m) -{ - if (hperh->init.mode == CRYPT_MODE_CTR) - return ald_crypt_decrypt_by_dma(hperh, cipher_text, plain_text, size, channel_m2p, channel_p2m); - - if (hperh->state != CRYPT_STATE_READY) - return ERROR; - if (plain_text == NULL || cipher_text == NULL || size == 0) - return ERROR; - - __LOCK(hperh); - hperh->state = CRYPT_STATE_BUSY; - - hperh->plain_text = plain_text; - hperh->cipher_text = cipher_text; - hperh->size = size; - hperh->count = size; - - if (hperh->hdma_m2p.perh == NULL) - hperh->hdma_m2p.perh = DMA0; - if (hperh->hdma_p2m.perh == NULL) - hperh->hdma_p2m.perh = DMA0; - - - hperh->hdma_m2p.cplt_arg = NULL; - hperh->hdma_m2p.cplt_cbk = NULL; - hperh->hdma_m2p.err_arg = NULL; - hperh->hdma_m2p.err_cbk = NULL; - - hperh->hdma_p2m.cplt_arg = (void *)hperh; - hperh->hdma_p2m.cplt_cbk = &crypt_dma_crypt_cplt; - hperh->hdma_p2m.err_arg = (void *)hperh; - hperh->hdma_p2m.err_cbk = &crypt_dma_error; - - CRYPT_SETDIR(hperh, CRYPT_DECRYPT); - - ald_dma_config_struct(&hperh->hdma_m2p.config); - hperh->hdma_m2p.config.data_width = DMA_DATA_SIZE_WORD; - hperh->hdma_m2p.config.src = (void *)hperh->cipher_text; - hperh->hdma_m2p.config.dst = (void *)&hperh->perh->FIFO; - hperh->hdma_m2p.config.size = size / 4; - hperh->hdma_m2p.config.src_inc = DMA_DATA_INC_WORD; - hperh->hdma_m2p.config.dst_inc = DMA_DATA_INC_NONE; - hperh->hdma_m2p.config.msel = DMA_MSEL_CRYPT; - hperh->hdma_m2p.config.msigsel = DMA_MSIGSEL_CRYPT_WRITE; - hperh->hdma_m2p.config.channel = channel_m2p; - ald_dma_config_basic(&(hperh->hdma_m2p)); - - ald_dma_config_struct(&hperh->hdma_p2m.config); - hperh->hdma_p2m.config.data_width = DMA_DATA_SIZE_WORD; - hperh->hdma_p2m.config.src = (void *)&hperh->perh->FIFO; - hperh->hdma_p2m.config.dst = (void *)hperh->plain_text; - hperh->hdma_p2m.config.size = size / 4; - hperh->hdma_p2m.config.src_inc = DMA_DATA_INC_NONE; - hperh->hdma_p2m.config.dst_inc = DMA_DATA_INC_WORD; - hperh->hdma_p2m.config.msel = DMA_MSEL_CRYPT; - hperh->hdma_p2m.config.msigsel = DMA_MSIGSEL_CRYPT_READ; - hperh->hdma_p2m.config.channel = channel_p2m; - ald_dma_config_basic(&(hperh->hdma_p2m)); - - CRYPT_DMA_ENABLE(hperh); - __UNLOCK(hperh); - - return OK; -} - -/** - * @} - */ - -/** @defgroup CRYPT_Public_Functions_Group3 DMA operation functions - * @brief DMA operation functions - * @{ - */ - -/** - * @brief Pauses the DMA Transfer. - * @param hperh: Pointer to a crypt_handle_t structure that contains - * the configuration information for the specified CRYPT module. - * @retval Status, see @ref ald_status_t. - */ -ald_status_t ald_crypt_dma_pause(crypt_handle_t *hperh) -{ - __LOCK(hperh); - CRYPT_DMA_DISABLE(hperh); - __UNLOCK(hperh); - - return OK; - -} - -/** - * @brief Resumes the DMA Transfer. - * @param hperh: Pointer to a crypt_handle_t structure that contains - * the configuration information for the specified CRYPT module. - * @retval Status, see @ref ald_status_t. - */ -ald_status_t ald_crypt_dma_resume(crypt_handle_t *hperh) -{ - __LOCK(hperh); - CRYPT_DMA_ENABLE(hperh); - __UNLOCK(hperh); - - return OK; -} - -/** - * @brief Stops the DMA Transfer. - * @param hperh: Pointer to a crypt_handle_t structure that contains - * the configuration information for the specified CRYPT module. - * @retval Status, see @ref ald_status_t. - */ -ald_status_t ald_crypt_dma_stop(crypt_handle_t *hperh) -{ - __LOCK(hperh); - CRYPT_DMA_DISABLE(hperh); - __UNLOCK(hperh); - - hperh->state = CRYPT_STATE_READY; - return OK; -} -#endif - -/** - * @brief This function handles CRYPT interrupt request. - * @param hperh: Pointer to a crypt_handle_t structure that contains - * the configuration information for the specified CRYPT module. - * @retval None - */ -void ald_crypt_irq_handler(crypt_handle_t *hperh) -{ - uint32_t i; - uint32_t *in_buf; - uint32_t *out_buf; - - if (READ_BIT(hperh->perh->CON, CRYPT_CON_ENCS_MSK)) { - in_buf = (uint32_t *)hperh->plain_text + hperh->count; - out_buf = (uint32_t *)hperh->cipher_text + hperh->count - hperh->step; - } - else { - in_buf = (uint32_t *)hperh->cipher_text + hperh->count; - out_buf = (uint32_t *)hperh->plain_text + hperh->count - hperh->step; - } - - if (ald_crypt_get_flag_status(hperh, CRYPT_FLAG_AESIF) == SET) { - ald_crypt_clear_flag_status(hperh, CRYPT_FLAG_AESIF); - } - - for (i = 0; i < hperh->step; i++) - *out_buf++ = CRYPT_READ_FIFO(hperh); - - hperh->count += hperh->step; - if (hperh->count > (hperh->size / 4)) { - hperh->count = 0; - hperh->state = CRYPT_STATE_READY; - - if (hperh->crypt_cplt_cbk) - hperh->crypt_cplt_cbk(hperh); - } - else { - for (i = 0; i < hperh->step; i++) { - CRYPT_WRITE_FIFO(hperh, *in_buf++); - } - } -} -/** - * @} - */ - -/** @defgroup CRYPT_Public_Functions_Group4 Peripheral Control functions - * @brief CRYPT control functions - * @{ - */ - -/** - * @brief Enables or disables the specified CRYPT interrupts. - * @param hperh: Pointer to a crypt_handle_t structure that contains - * the configuration information for the specified CRYPT module. - * @param it: Specifies the CRYPT interrupt sources to be enabled or disabled. - * This parameter can be one of the following values: - * @arg crypt_it_t: CRYPT interrupt - * @param state: New status - * - ENABLE - * - DISABLE - * @retval None - */ -void ald_crypt_interrupt_config(crypt_handle_t *hperh, crypt_it_t it, type_func_t state) -{ - assert_param(IS_CRYPT(hperh->perh)); - - if (it == CRYPT_IT_IT) { - CLEAR_BIT(CRYPT->CON, CRYPT_CON_IE_MSK); - CRYPT->CON |= (state << CRYPT_CON_IE_POS); - } - - return; -} - -/** @brief Check whether the specified CRYPT flag is set or not. - * @param hperh: Pointer to a crypt_handle_t structure that contains - * the configuration information for the specified CRYPT module. - * @param flag: specifies the flag to check. - * This parameter can be one of the @ref crypt_flag_t. - * @retval Status - * - SET - * - RESET - */ -flag_status_t ald_crypt_get_flag_status(crypt_handle_t *hperh, crypt_flag_t flag) -{ - assert_param(IS_CRYPT(hperh->perh)); - assert_param(IS_CRYPT_FLAG(flag)); - - if (CRYPT->IF & flag) - return SET; - - return RESET; -} - -/** @brief Clear the specified CRYPT pending flags. - * @param hperh: Pointer to a crypt_handle_t structure that contains - * the configuration information for the specified CRYPT module. - * @param flag: specifies the flag to check. - * This parameter can be any combination of the following values: - * @arg CRYPT_FLAG_AESIF: AES encrypt or decrypt Complete flag. - * @arg CRYPT_FLAG_DONE: encrypt or decrypt Complete flag. - * @retval None - */ -void ald_crypt_clear_flag_status(crypt_handle_t *hperh, crypt_flag_t flag) -{ - assert_param(IS_CRYPT(hperh->perh)); - assert_param(IS_CRYPT_FLAG(flag)); - - WRITE_REG(CRYPT->IFC, flag); - return; -} - -/** - * @brief Checks whether the specified CRYPT interrupt has occurred or not. - * @param hperh: Pointer to a crypt_handle_t structure that contains - * the configuration information for the specified CRYPT module. - * @param it: Specifies the CRYPT interrupt source to check. - * This parameter can be one of the following values: - * @arg crypt_it_t: CRYPT interrupt - * @retval Status - * - SET - * - RESET - */ -it_status_t ald_crypt_get_it_status(crypt_handle_t *hperh, crypt_it_t it) -{ - assert_param(IS_CRYPT_IT(it)); - - if (READ_BIT(CRYPT->CON, CRYPT_CON_IE_MSK)) - return SET; - - return RESET; -} - - -/** - * @} - */ - -/** @defgroup CRYPT_Public_Functions_Group5 Peripheral State and Errors functions - * @brief State and Errors functions - * @{ - */ - -/** - * @brief Returns the CRYPT state. - * @param hperh: Pointer to a crypt_handle_t structure that contains - * the configuration information for the specified CRYPT module. - * @retval CRYPT state - */ -crypt_state_t ald_crypt_get_state(crypt_handle_t *hperh) -{ - assert_param(IS_CRYPT(hperh->perh)); - - - return hperh->state; -} - -/** - * @} - */ - -/** - * @} - */ - -/** @defgroup CRYPT_Private_Functions CRYPT Private Functions - * @brief CRYPT Private functions - * @{ - */ - -/** - * @brief Reset the CRYPT peripheral. - * @param hperh: Pointer to a crypt_handle_t structure that contains - * the configuration information for the specified CRYPT module. - * @retval None - */ -void crypt_reset(crypt_handle_t *hperh) -{ - hperh->perh->DATA[0] = 0x0; - hperh->perh->DATA[1] = 0x0; - hperh->perh->DATA[2] = 0x0; - hperh->perh->DATA[3] = 0x0; - hperh->perh->KEY[0] = 0x0; - hperh->perh->KEY[1] = 0x0; - hperh->perh->KEY[2] = 0x0; - hperh->perh->KEY[3] = 0x0; - hperh->perh->KEY[4] = 0x0; - hperh->perh->KEY[5] = 0x0; - hperh->perh->KEY[6] = 0x0; - hperh->perh->KEY[7] = 0x0; - hperh->perh->IV[0] = 0x0; - hperh->perh->IV[1] = 0x0; - hperh->perh->IV[2] = 0x0; - hperh->perh->IV[3] = 0x0; - hperh->perh->CON = 0x0; - - hperh->state = CRYPT_STATE_READY; - __UNLOCK(hperh); -} - -#ifdef ALD_DMA -/** - * @brief DMA CRYPT encrypt or decrypt process complete callback. - * @param arg: Pointer to a crypt_handle_t structure that contains - * the configuration information for the specified CRYPT module. - * @retval None - */ -static void crypt_dma_crypt_cplt(void *arg) -{ - crypt_handle_t *hperh = (crypt_handle_t *)arg; - - CRYPT_DMA_DISABLE(hperh); - hperh->count = 0; - hperh->plain_text = NULL; - hperh->cipher_text = NULL; - hperh->size = 0; - - hperh->state = CRYPT_STATE_READY; - - if (hperh->crypt_cplt_cbk) - hperh->crypt_cplt_cbk(hperh); -} - -/** - * @brief DMA CRYPT communication error callback. - * @param arg: Pointer to a crypt_handle_t structure that contains - * the configuration information for the specified CRYPT module. - * @retval None - */ -static void crypt_dma_error(void *arg) -{ - crypt_handle_t *hperh = (crypt_handle_t *)arg; - CRYPT_DMA_DISABLE(hperh); - - hperh->count = 0; - hperh->plain_text = NULL; - hperh->cipher_text = NULL; - hperh->size = 0; - - hperh->state = CRYPT_STATE_READY; - - if (hperh->err_cplt_cbk) - hperh->err_cplt_cbk(hperh); -} -#endif -/** - * @} - */ - -/** - * @} - */ -#endif /* ALD_CRYPT */ - -/** - * @} - */ diff --git a/bsp/essemi/es32f0334/libraries/ES32F033x_ALD_StdPeriph_Driver/Source/ald_dma.c b/bsp/essemi/es32f0334/libraries/ES32F033x_ALD_StdPeriph_Driver/Source/ald_dma.c deleted file mode 100644 index f3c125578d..0000000000 --- a/bsp/essemi/es32f0334/libraries/ES32F033x_ALD_StdPeriph_Driver/Source/ald_dma.c +++ /dev/null @@ -1,999 +0,0 @@ -/** - ********************************************************************************* - * - * @file ald_dma.c - * @brief DMA module driver. - * - * @version V1.0 - * @date 09 Nov 2017 - * @author AE Team - * @note - * - * Copyright (C) Shanghai Eastsoft Microelectronics Co. Ltd. All rights reserved. - * - ********************************************************************************* - * @verbatim - ============================================================================== - ##### How to use this driver ##### - ============================================================================== - [..] - The DMA driver can be used as follows: - - (#) System initialization invokes ald_dma_init(), ald_cmu_init() --> ald_dma_init(). - - (#) Declare a dma_handle_t handle structure. - - (#) Configure the dma_handle_t structure, you can configure the - dma_config_t structure with the help of ald_dma_config_struct(). - - (#) Enable the DMA Configure: - (##) Memory -- memory: call ald_dma_config_auto(). - (##) Peripheral -- memory: call ald_dma_config_basic(). - (##) If you want use the dma easily, you can do this: - (+++) Memory -- memory: call ald_dma_config_auto_easy(). - (+++) Peripheral -- memory: call ald_dma_config_basic_easy(). - - (#) Enable the DMA request signal: - (##) Memory -- memory: the DMA request signal is request automatic. - (##) Peripheral -- memory: you need enable peripheral request signal. - - (#) If you enable DMA interrupt, the callback will be invoked: - (##) When DMA transfer is completed, the cplt_cbk() will be invoked. - (##) When DMA bus occurs error, the err_cbk() will be invoked. - - (#) If you don't enable the DMA interrupt, you need do this: - (##) Polling the ald_dma_get_flag_status(), this function's parameter is channel - or DMA_ERR. - (+++) When the function's Parameter is channel, if retval is SET, it means - the DMA transfer is completed. at this moment, you can do something, - and then, you need invoke ald_dma_clear_flag_status() to clear flag. - - (+++) When the function's Parameter is DMA_ERR, if retval is SET, it means - the DMA bus occurs error. at this moment, you can do something, - and then, you need invoke ald_dma_clear_flag_status() to clear flag. - - @endverbatim - */ - -#include -#include "ald_conf.h" -#include "ald_dma.h" - - -/** @addtogroup ES32FXXX_ALD - * @{ - */ - -/** @defgroup DMA DMA - * @brief DMA module driver - * @{ - */ - -#ifdef ALD_DMA -/** @defgroup DMA_Private_Variables DMA Private Variables - * @{ - */ -dma_descriptor_t dma0_ctrl_base[28] __attribute__ ((aligned(512))); -dma_call_back_t dma0_cbk[6]; -/** - * @} - */ - -/** @defgroup DMA_Private_Functions DMA Private Functions - * @{ - */ - -/** - * @brief Configure DMA channel using dma_config_t structure - * @param DMAx: Pointer to DMA peripheral - * @param mode: DMA transfer mode. see @ref dma_cycle_ctrl_t - * @param p: Pointer to dma_cycle_ctrl_t which contains - * DMA channel parameter. see @ref dma_config_t - * @retval None - */ -static void dma_config_base(DMA_TypeDef *DMAx, dma_cycle_ctrl_t mode, dma_config_t *p) -{ - dma_descriptor_t *descr; - - assert_param(IS_DMA(DMAx)); - assert_param(IS_CYCLECTRL_TYPE(mode)); - assert_param(p->src != NULL); - assert_param(p->dst != NULL); - assert_param(IS_DMA_DATA_SIZE(p->size)); - assert_param(IS_DMA_DATASIZE_TYPE(p->data_width)); - assert_param(IS_DMA_DATAINC_TYPE(p->src_inc)); - assert_param(IS_DMA_DATAINC_TYPE(p->dst_inc)); - assert_param(IS_DMA_ARBITERCONFIG_TYPE(p->R_power)); - assert_param(IS_FUNC_STATE(p->primary)); - assert_param(IS_FUNC_STATE(p->burst)); - assert_param(IS_FUNC_STATE(p->high_prio)); - assert_param(IS_FUNC_STATE(p->interrupt)); - assert_param(IS_DMA_MSEL_TYPE(p->msel)); - assert_param(IS_DMA_MSIGSEL_TYPE(p->msigsel)); - assert_param(IS_DMA_CHANNEL(p->channel)); - - if (p->primary) - descr = (dma_descriptor_t *)(DMAx->CTRLBASE) + p->channel; - else - descr = (dma_descriptor_t *)(DMAx->ALTCTRLBASE) + p->channel; - - if (p->src_inc == DMA_DATA_INC_NONE) - descr->src = p->src; - else - descr->src = (void *)((uint32_t)p->src + ((p->size - 1) << (uint32_t)p->src_inc)); - - if (p->dst_inc == DMA_DATA_INC_NONE) - descr->dst = p->dst; - else - descr->dst = (void *)((uint32_t)p->dst + ((p->size - 1) << (uint32_t)p->dst_inc)); - - descr->ctrl.cycle_ctrl = mode; - descr->ctrl.next_useburst = 0; - descr->ctrl.n_minus_1 = p->size - 1; - descr->ctrl.R_power = p->R_power; - descr->ctrl.src_prot_ctrl = 0, - descr->ctrl.dst_prot_ctrl = 0, - descr->ctrl.src_size = p->data_width; - descr->ctrl.src_inc = p->src_inc; - descr->ctrl.dst_size = p->data_width; - descr->ctrl.dst_inc = p->dst_inc; - - if (p->primary) - WRITE_REG(DMAx->CHPRIALTCLR, (1 << p->channel)); - else - WRITE_REG(DMAx->CHPRIALTSET, (1 << p->channel)); - - if (p->burst) - WRITE_REG(DMAx->CHUSEBURSTSET, (1 << p->channel)); - else - WRITE_REG(DMAx->CHUSEBURSTCLR, (1 << p->channel)); - - if (p->high_prio) - WRITE_REG(DMAx->CHPRSET, (1 << p->channel)); - else - WRITE_REG(DMAx->CHPRCLR, (1 << p->channel)); - - if (p->interrupt) - SET_BIT(DMAx->IER, (1 << p->channel)); - else - CLEAR_BIT(DMAx->IER, (1 << p->channel)); - - MODIFY_REG(DMAx->CH_SELCON[p->channel], DMA_CH0_SELCON_MSEL_MSK, p->msel << DMA_CH0_SELCON_MSEL_POSS); - MODIFY_REG(DMAx->CH_SELCON[p->channel], DMA_CH0_SELCON_MSIGSEL_MSK, p->msigsel << DMA_CH0_SELCON_MSIGSEL_POSS); - return; -} - -/** - * @brief Handle DMA interrupt - * @retval None - */ -void ald_dma_irq_handler(void) -{ - uint32_t i, reg = DMA0->IFLAG; - - for (i = 0; i < DMA_CH_COUNT; ++i) { - if (READ_BIT(reg, (1 << i))) { - if (dma0_cbk[i].cplt_cbk != NULL) - dma0_cbk[i].cplt_cbk(dma0_cbk[i].cplt_arg); - - ald_dma_clear_flag_status(DMA0, i); - } - } - - if (READ_BIT(reg, (1U << DMA_ERR))) { - ald_dma_clear_flag_status(DMA0, DMA_ERR); - - for (i = 0; i < DMA_CH_COUNT; ++i) { - if (((DMA0->CHENSET >> i) & 0x1) && (dma0_cbk[i].err_cbk != NULL)) - dma0_cbk[i].err_cbk(dma0_cbk[i].err_arg); - } - } - - return; -} -/** - * @} - */ - -/** @defgroup DMA_Public_Functions DMA Public Functions - * @{ - */ - -/** @defgroup DMA_Public_Functions_Group1 Initialization functions - * @brief Initialization functions - * - * @verbatim - =================================================================== - - #### Initialization functions #### - - =================================================================== - [..] - This subsection provides two functions to Initilizate DMA: - (+) ald_dma_reset(): Reset the DMA register. - - (+) ald_dma_init(): Initializate the DMA module. this function is - invoked by ald_cmu_init(). - this function do this: - (++) Initializte private variable dma_ctrl_base and dma_cbk. - (++) Reset DMA register. - (++) Set DMA interrupt priority: preempt_prio=1, sub_priority=1 - (++) Enable DMA interrupt. - (++) Enable DMA bus error interrupt. - (++) Configure CTRLBASE resigter. - (++) Enable DMA module. - - (+) ald_dma_config_struct(): Configure dma_config_t - structure using default parameter. - - (+) ald_dma_config_sg_alt_desc(): Configure dma_descriptor_t - structure using specified parameter. This function used - in scatter-gather mode(memory or peripheral). - @endverbatim - * @{ - */ - -/** - * @brief Reset the DMA register - * @param DMAx: Pointer to DMA peripheral - * @retval None - */ -void ald_dma_reset(DMA_TypeDef *DMAx) -{ - uint32_t i; - - assert_param(IS_DMA(DMAx)); - - WRITE_REG(DMAx->CFG, 0x0); - WRITE_REG(DMAx->CHUSEBURSTCLR, 0xFFF); - WRITE_REG(DMAx->CHREQMASKCLR, 0xFFF); - WRITE_REG(DMAx->CHENCLR, 0xFFF); - WRITE_REG(DMAx->CHPRIALTCLR, 0xFFF); - WRITE_REG(DMAx->CHPRCLR, 0xFFF); - WRITE_REG(DMAx->ERRCLR, 0x1); - WRITE_REG(DMAx->IER, 0x0); - WRITE_REG(DMAx->ICFR, 0x80000FFF); - - for (i = 0; i < DMA_CH_COUNT; ++i) - WRITE_REG(DMAx->CH_SELCON[i], 0x0); - - return; -} - -/** - * @brief DMA module initialization, this function - * is invoked by ald_cmu_init(). - * @param DMAx: Pointer to DMA peripheral - * @retval None - */ -void ald_dma_init(DMA_TypeDef *DMAx) -{ - assert_param(IS_DMA(DMAx)); - - memset(dma0_ctrl_base, 0x0, sizeof(dma0_ctrl_base)); - memset(dma0_cbk, 0x0, sizeof(dma0_cbk)); - - ald_dma_reset(DMAx); - NVIC_SetPriority(DMA_IRQn, 2); - NVIC_EnableIRQ(DMA_IRQn); - SET_BIT(DMAx->IER, DMA_IER_DMAERRIE_MSK); - - WRITE_REG(DMAx->CTRLBASE, (uint32_t)&dma0_ctrl_base); - SET_BIT(DMAx->CFG, DMA_CFG_MASTER_ENABLE_MSK); - - return; -} - -/** - * @brief Configure dma_config_t structure using default parameter. - * User can invoked this function, before configure dma_config_t - * @param p: Pointer to dma_config_t structure, see @ref dma_config_t - * @retval None - */ -void ald_dma_config_struct(dma_config_t *p) -{ - p->data_width = DMA_DATA_SIZE_BYTE; - p->src_inc = DMA_DATA_INC_BYTE; - p->dst_inc = DMA_DATA_INC_BYTE; - p->R_power = DMA_R_POWER_1; - p->primary = ENABLE; - p->burst = DISABLE; - p->high_prio = DISABLE; - p->interrupt = ENABLE; - - return; -} - -/** - * @brief Configure dma_descriptor_t structure using specified parameter. - * @note This function used in scatter-gather mode(memory or peripheral). - * @param desc: Address of the alternate descriptor. - * @param config: Pointer to the dma_config_t structure. - * @param memory: Memory or peripheral scatter-gather. - * @retval None - */ -void ald_dma_config_sg_alt_desc(dma_descriptor_t *desc, dma_config_t *config, uint8_t memory) -{ - if ((desc == NULL) || (config == NULL)) - return; - - if (config->src_inc == DMA_DATA_INC_NONE) - desc->src = config->src; - else - desc->src = (void *)((uint32_t)config->src + ((config->size - 1) << (uint32_t)config->data_width)); - - if (config->dst_inc == DMA_DATA_INC_NONE) - desc->dst = config->dst; - else - desc->dst = (void *)((uint32_t)config->dst + ((config->size - 1) << (uint32_t)config->data_width)); - - desc->ctrl.cycle_ctrl = memory ? DMA_CYCLE_CTRL_MEM_SG_ALTERNATE : DMA_CYCLE_CTRL_PER_SG_ALTERNATE; - desc->ctrl.next_useburst = memory ? 0 : 1; - desc->ctrl.n_minus_1 = config->size - 1; - desc->ctrl.R_power = config->R_power; - desc->ctrl.src_prot_ctrl = 0; - desc->ctrl.dst_prot_ctrl = 0; - desc->ctrl.src_size = config->data_width; - desc->ctrl.src_inc = config->src_inc; - desc->ctrl.dst_size = config->data_width; - desc->ctrl.dst_inc = config->dst_inc; - - return; -} - -/** - * @} - */ - -/** @defgroup DMA_Public_Functions_Group2 Configure DMA channel functions - * @brief Configure DMA channel functions - * - * @verbatim - =================================================================== - - #### Configure DMA channel functions #### - - =================================================================== - [..] - This subsection provides some functions allowing to configure - DMA channel. Include two type DMA transfer: - (+) Carry data from memory to memory, this mode APIs are: - (++) ald_dma_config_auto(): Configure DMA channel according to - the specified parameter in the dma_handle_t structure. - (++) ald_dma_restart_auto(): Restart DMA transmitted. - (++) ald_dma_config_auto_easy(): Configure DMA channel according - to the specified parameter. If you want use the dma easily, - you can invoke this function. - (++) ald_dma_config_sg_mem(): Carry data used scatter-gather mode. - (+) Carry data from peripheral to memory or from memory to peripheral, - this mode APIs are: - (++) ald_dma_config_basic(): Configure DMA channel according to - the specified parameter in the dma_handle_t structure. - (++) ald_dma_restart_basic(): Restart DMA transmitted. - (++) ald_dma_config_basic_easy(): Configure DMA channel according - to the specified parameter. If you want use the dma easily, - you can invoke this function. - (++) ald_dma_ping_pong(): Carry data used ping-pong mode. - (++) ald_dma_config_sg_per(): Carry data used scatter-gather mode. - - @endverbatim - * @{ - */ - -/** - * @brief Configure DMA channel according to the specified parameter - * in the dma_handle_t structure. The DMA mode is automatic. - * This mode is used to carry data from memory to memory. - * @param hperh: Pointer to DMA_handle_t structure that contains - * configuration information for specified DMA channel. - * @retval None - */ -void ald_dma_config_auto(dma_handle_t *hperh) -{ - dma0_cbk[hperh->config.channel].cplt_cbk = hperh->cplt_cbk; - dma0_cbk[hperh->config.channel].err_cbk = hperh->err_cbk; - dma0_cbk[hperh->config.channel].cplt_arg = hperh->cplt_arg; - dma0_cbk[hperh->config.channel].err_arg = hperh->err_arg; - dma_config_base(hperh->perh, DMA_CYCLE_CTRL_AUTO, &hperh->config); - - ald_dma_clear_flag_status(hperh->perh, hperh->config.channel); - WRITE_REG(hperh->perh->CHENSET, (1 << hperh->config.channel)); - SET_BIT(hperh->perh->CHSWREQ, (1 << hperh->config.channel)); - - return; -} - -/** - * @brief Restart DMA transmitted. The DMA mode is automatic. - * The other parameters have not changed except 'size' and 'addr'. - * @param hperh: Pointer to DMA_handle_t structure that contains - * configuration information for specified DMA channel. - * @param src: Source data begin pointer - * @param dst: Destination data begin pointer - * @param size: Size. - * @retval None - */ -void ald_dma_restart_auto(dma_handle_t *hperh, void *src, void *dst, uint16_t size) -{ - dma_descriptor_t *descr; - - if (hperh->config.primary) - descr = (dma_descriptor_t *)(hperh->perh->CTRLBASE) + hperh->config.channel; - else - descr = (dma_descriptor_t *)(hperh->perh->ALTCTRLBASE) + hperh->config.channel; - - if (src) { - if (hperh->config.src_inc == DMA_DATA_INC_NONE) - descr->src = src; - else - descr->src = (void *)((uint32_t)src + ((size - 1) << (uint32_t)hperh->config.data_width)); - } - - if (dst) { - if (hperh->config.dst_inc == DMA_DATA_INC_NONE) - descr->dst = dst; - else - descr->dst = (void *)((uint32_t)dst + ((size - 1) << (uint32_t)hperh->config.data_width)); - } - - ald_dma_clear_flag_status(hperh->perh, hperh->config.channel); - descr->ctrl.cycle_ctrl = DMA_CYCLE_CTRL_AUTO; - descr->ctrl.n_minus_1 = size - 1; - WRITE_REG(hperh->perh->CHENSET, (1 << hperh->config.channel)); - SET_BIT(hperh->perh->CHSWREQ, (1 << hperh->config.channel)); - return; -} - -/** - * @brief Configure DMA channel according to the specified parameter. - * The DMA mode is automatic. This mode is used to carry data - * from memory to memory. If User want use the dma easily, - * they can invoke this function. - * @param DMAx: Pointer to DMA peripheral - * @param src: Source data begin pointer - * @param dst: Destination data begin pointer - * @param size: The total number of DMA transfers that DMA cycle contains - * @param channel: Channel index which will be used. - * @param cbk: DMA complete callback function - * @retval None - */ -void ald_dma_config_auto_easy(DMA_TypeDef *DMAx, void *src, void *dst, - uint16_t size, uint8_t channel, void (*cbk)(void *arg)) -{ - dma_handle_t hperh; - - assert_param(IS_DMA(DMAx)); - - ald_dma_config_struct(&hperh.config); - hperh.config.src = src; - hperh.config.dst = dst; - hperh.config.size = size; - hperh.config.msel = DMA_MSEL_NONE; - hperh.config.msigsel = DMA_MSIGSEL_NONE; - hperh.config.channel = channel; - - hperh.perh = DMAx; - hperh.cplt_cbk = cbk; - hperh.cplt_arg = NULL; - hperh.err_cbk = NULL; - - ald_dma_clear_flag_status(DMAx, channel); - ald_dma_config_auto(&hperh); - - return; -} - -/** - * @brief Configure DMA channel according to the specified parameter - * in the dma_handle_t structure. The DMA mode is basic. - * This mode is used to carry data from peripheral to memory - * or from memory to peripheral. - * @param hperh: Pointer to dma_handle_t structure that contains - * configuration information for specified DMA channel. - * @retval None - */ -void ald_dma_config_basic(dma_handle_t *hperh) -{ - dma0_cbk[hperh->config.channel].cplt_cbk = hperh->cplt_cbk; - dma0_cbk[hperh->config.channel].err_cbk = hperh->err_cbk; - dma0_cbk[hperh->config.channel].cplt_arg = hperh->cplt_arg; - dma0_cbk[hperh->config.channel].err_arg = hperh->err_arg; - - ald_dma_clear_flag_status(hperh->perh, hperh->config.channel); - dma_config_base(hperh->perh, DMA_CYCLE_CTRL_BASIC, &hperh->config); - WRITE_REG(hperh->perh->CHENSET, (1 << hperh->config.channel)); - - return; -} - -/** - * @brief Restart DMA transmitted. The DMA mode is basic. - * The other parameters have not changed except 'size' and 'addr'. - * @param hperh: Pointer to DMA_handle_t structure that contains - * configuration information for specified DMA channel. - * @param src: Source data begin pointer - * @param dst: Destination data begin pointer - * @param size: Size. - * @retval None - */ -void ald_dma_restart_basic(dma_handle_t *hperh, void *src, void *dst, uint16_t size) -{ - dma_descriptor_t *descr; - - if (hperh->config.primary) - descr = (dma_descriptor_t *)(hperh->perh->CTRLBASE) + hperh->config.channel; - else - descr = (dma_descriptor_t *)(hperh->perh->ALTCTRLBASE) + hperh->config.channel; - - if (src) { - if (hperh->config.src_inc == DMA_DATA_INC_NONE) - descr->src = src; - else - descr->src = (void *)((uint32_t)src + ((size - 1) << (uint32_t)hperh->config.data_width)); - } - - if (dst) { - if (hperh->config.dst_inc == DMA_DATA_INC_NONE) - descr->dst = dst; - else - descr->dst = (void *)((uint32_t)dst + ((size - 1) << (uint32_t)hperh->config.data_width)); - } - - ald_dma_clear_flag_status(hperh->perh, hperh->config.channel); - descr->ctrl.cycle_ctrl = DMA_CYCLE_CTRL_BASIC; - descr->ctrl.n_minus_1 = size - 1; - WRITE_REG(hperh->perh->CHENSET, (1 << hperh->config.channel)); - - return; -} - -/** - * @brief Configure DMA channel according to the specified parameter. - * The DMA mode is basic. This mode is used to carry data - * from peripheral to memory or negative direction. If user want - * use the dma easily, they can invoke this function. - * @param DMAx: Pointer to DMA peripheral - * @param src: Source data begin pointer - * @param dst: Destination data begin pointer - * @param size: The total number of DMA transfers that DMA cycle contains - * @param msel: Input source to DMA channel @ref dma_msel_t - * @param msigsel: Input signal to DMA channel @ref dma_msigsel_t - * @param channel: Channel index which will be used - * @param cbk: DMA complete callback function - * @retval None - */ -void ald_dma_config_basic_easy(DMA_TypeDef *DMAx, void *src, void *dst, uint16_t size, dma_msel_t msel, - dma_msigsel_t msigsel, uint8_t channel, void (*cbk)(void *arg)) -{ - dma_handle_t hperh; - - assert_param(IS_DMA(DMAx)); - ald_dma_config_struct(&hperh.config); - - if (((uint32_t)src) >= 0x40000000) - hperh.config.src_inc = DMA_DATA_INC_NONE; - - if (((uint32_t)dst) >= 0x40000000) - hperh.config.dst_inc = DMA_DATA_INC_NONE; - - hperh.config.src = src; - hperh.config.dst = dst; - hperh.config.size = size; - hperh.config.msel = msel; - hperh.config.msigsel = msigsel; - hperh.config.channel = channel; - - hperh.perh = DMAx; - hperh.cplt_cbk = cbk; - hperh.cplt_arg = NULL; - hperh.err_cbk = NULL; - - ald_dma_clear_flag_status(DMAx, channel); - ald_dma_config_basic(&hperh); - - return; -} - -/** - * @brief Configure DMA channel according to the specified parameter. - * The DMA mode is ping-pong. - * @note The ping-pong mode does not support memory to memory. - * @param DMAx: Pointer to DMA peripheral. - * @param config: Pointer to the dma_config_t structure which contains - * the specified parameters. - * @param first: Whether it is the first transmission. 1-first, 0-not first. - * @param cbk: DMA complete callback function. - * @retval None - */ -void ald_dma_config_ping_pong(DMA_TypeDef *DMAx, dma_config_t *config, - uint8_t first, void (*cbk)(void *arg)) -{ - dma_descriptor_t *desc; - - assert_param(IS_DMA(DMAx)); - assert_param(config->src != NULL); - assert_param(config->dst != NULL); - assert_param(IS_DMA_DATA_SIZE(config->size)); - assert_param(IS_DMA_DATASIZE_TYPE(config->data_width)); - assert_param(IS_DMA_DATAINC_TYPE(config->src_inc)); - assert_param(IS_DMA_DATAINC_TYPE(config->dst_inc)); - assert_param(IS_DMA_ARBITERCONFIG_TYPE(config->R_power)); - assert_param(IS_FUNC_STATE(config->primary)); - assert_param(IS_FUNC_STATE(config->burst)); - assert_param(IS_FUNC_STATE(config->high_prio)); - assert_param(IS_FUNC_STATE(config->interrupt)); - assert_param(IS_DMA_MSEL_TYPE(config->msel)); - assert_param(IS_DMA_MSIGSEL_TYPE(config->msigsel)); - assert_param(IS_DMA_CHANNEL(config->channel)); - - dma0_cbk[config->channel].cplt_cbk = cbk; - dma0_cbk[config->channel].err_cbk = NULL; - dma0_cbk[config->channel].cplt_arg = NULL; - dma0_cbk[config->channel].err_arg = NULL; - - if (config->primary) - desc = (dma_descriptor_t *)(DMAx->CTRLBASE) + config->channel; - else - desc = (dma_descriptor_t *)(DMAx->ALTCTRLBASE) + config->channel; - - if (config->src_inc == DMA_DATA_INC_NONE) - desc->src = config->src; - else - desc->src = (void *)((uint32_t)config->src + ((config->size - 1) << (uint32_t)config->data_width)); - - if (config->dst_inc == DMA_DATA_INC_NONE) - desc->dst = config->dst; - else - desc->dst = (void *)((uint32_t)config->dst + ((config->size - 1) << (uint32_t)config->data_width)); - - desc->ctrl.cycle_ctrl = DMA_CYCLE_CTRL_PINGPONG; - desc->ctrl.next_useburst = 0; - desc->ctrl.n_minus_1 = config->size - 1; - desc->ctrl.R_power = config->R_power; - desc->ctrl.src_prot_ctrl = 0, - desc->ctrl.dst_prot_ctrl = 0, - desc->ctrl.src_size = config->data_width; - desc->ctrl.src_inc = config->src_inc; - desc->ctrl.dst_size = config->data_width; - desc->ctrl.dst_inc = config->dst_inc; - - if (!first) - return; - - if (config->primary) - WRITE_REG(DMAx->CHPRIALTCLR, (1 << config->channel)); - else - WRITE_REG(DMAx->CHPRIALTSET, (1 << config->channel)); - - if (config->burst) - WRITE_REG(DMAx->CHUSEBURSTSET, (1 << config->channel)); - else - WRITE_REG(DMAx->CHUSEBURSTCLR, (1 << config->channel)); - - if (config->high_prio) - WRITE_REG(DMAx->CHPRSET, (1 << config->channel)); - else - WRITE_REG(DMAx->CHPRCLR, (1 << config->channel)); - - if (config->interrupt) - SET_BIT(DMAx->IER, (1 << config->channel)); - else - CLEAR_BIT(DMAx->IER, (1 << config->channel)); - - MODIFY_REG(DMAx->CH_SELCON[config->channel], DMA_CH0_SELCON_MSEL_MSK, config->msel << DMA_CH0_SELCON_MSEL_POSS); - MODIFY_REG(DMAx->CH_SELCON[config->channel], DMA_CH0_SELCON_MSIGSEL_MSK, config->msigsel << DMA_CH0_SELCON_MSIGSEL_POSS); - - WRITE_REG(DMAx->ICFR, (1 << config->channel)); - WRITE_REG(DMAx->CHENSET, (1 << config->channel)); - - return; -} - -/** - * @brief Configure DMA channel according to the specified parameter. - * The DMA mode is memory scatter-gather. - * @param DMAx: Pointer to DMA peripheral. - * @param desc: Pointer to first alternate descriptor. - * @param nr: Number of the alternate descriptor. - * @param channel: Channel index which will be used. - * @param cbk: DMA complete callback function. - * @retval None - */ -void ald_dma_config_sg_mem(DMA_TypeDef *DMAx, dma_descriptor_t *desc, uint32_t nr, - uint8_t channel, void (*cbk)(void *arg)) -{ - dma_descriptor_t *tmp = (dma_descriptor_t *)(DMAx->CTRLBASE) + channel; - dma_descriptor_t *_tmp = (dma_descriptor_t *)(DMAx->ALTCTRLBASE) + channel; - - assert_param(IS_DMA(DMAx)); - assert_param(IS_DMA_CHANNEL(channel)); - - if ((desc == NULL) || (nr == 0)) - return; - - dma0_cbk[channel].cplt_cbk = cbk; - dma0_cbk[channel].err_cbk = NULL; - dma0_cbk[channel].cplt_arg = NULL; - dma0_cbk[channel].err_arg = NULL; - - tmp->src = (void *)((uint32_t)desc + (((nr << 2) - 1) << DMA_DATA_INC_WORD)); - tmp->dst = (void *)((uint32_t)_tmp + ((4 - 1) << DMA_DATA_INC_WORD)); - tmp->ctrl.cycle_ctrl = DMA_CYCLE_CTRL_MEM_SG_PRIMARY; - tmp->ctrl.next_useburst = 0; - tmp->ctrl.n_minus_1 = (nr << 2) - 1; - tmp->ctrl.R_power = DMA_R_POWER_4; - tmp->ctrl.src_prot_ctrl = 0, - tmp->ctrl.dst_prot_ctrl = 0, - tmp->ctrl.src_size = DMA_DATA_SIZE_WORD; - tmp->ctrl.src_inc = DMA_DATA_INC_WORD; - tmp->ctrl.dst_size = DMA_DATA_SIZE_WORD; - tmp->ctrl.dst_inc = DMA_DATA_INC_WORD; - - desc[nr - 1].ctrl.cycle_ctrl = DMA_CYCLE_CTRL_AUTO; - WRITE_REG(DMAx->CHPRIALTCLR, (1 << channel)); - WRITE_REG(DMAx->CHUSEBURSTCLR, (1 << channel)); - WRITE_REG(DMAx->CHPRCLR, (1 << channel)); - - WRITE_REG(DMAx->ICFR, (1 << channel)); - SET_BIT(DMAx->IER, (1 << channel)); - WRITE_REG(DMAx->CHENSET, (1 << channel)); - SET_BIT(DMAx->CHSWREQ, (1 << channel)); - - return; -} - -/** - * @brief Configure DMA channel according to the specified parameter. - * The DMA mode is peripheral scatter-gather. - * @note The size of the first transmission must be 5. - * @param DMAx: Pointer to DMA peripheral. - * @param desc: Pointer to first alternate descriptor. - * @param nr: Number of the alternate descriptor. - * @param burst: 1-Enable burst, 0-Disable burst. - * @param msel: Input source to DMA channel @ref dma_msel_t - * @param msigsel: Input signal to DMA channel @ref dma_msigsel_t - * @param channel: Channel index which will be used. - * @param cbk: DMA complete callback function. - * @retval None - */ -void ald_dma_config_sg_per(DMA_TypeDef *DMAx, dma_descriptor_t *desc, uint32_t nr, uint8_t burst, - dma_msel_t msel, dma_msigsel_t msigsel, uint8_t channel, void (*cbk)(void *arg)) -{ - dma_descriptor_t *tmp = (dma_descriptor_t *)(DMAx->CTRLBASE) + channel; - dma_descriptor_t *_tmp = (dma_descriptor_t *)(DMAx->ALTCTRLBASE) + channel; - - assert_param(IS_DMA(DMAx)); - assert_param(IS_DMA_MSEL_TYPE(msel)); - assert_param(IS_DMA_MSIGSEL_TYPE(msigsel)); - assert_param(IS_DMA_CHANNEL(channel)); - - if ((desc == NULL) || (nr == 0)) - return; - - dma0_cbk[channel].cplt_cbk = cbk; - dma0_cbk[channel].err_cbk = NULL; - dma0_cbk[channel].cplt_arg = NULL; - dma0_cbk[channel].err_arg = NULL; - - tmp->src = (void *)((uint32_t)desc + (((nr << 2) - 1) << DMA_DATA_INC_WORD)); - tmp->dst = (void *)((uint32_t)_tmp + ((4 - 1) << DMA_DATA_INC_WORD)); - tmp->ctrl.cycle_ctrl = DMA_CYCLE_CTRL_PER_SG_PRIMARY; - tmp->ctrl.next_useburst = 0; - tmp->ctrl.n_minus_1 = (nr << 2) - 1; - tmp->ctrl.R_power = DMA_R_POWER_4; - tmp->ctrl.src_prot_ctrl = 0, - tmp->ctrl.dst_prot_ctrl = 0, - tmp->ctrl.src_size = DMA_DATA_SIZE_WORD; - tmp->ctrl.src_inc = DMA_DATA_INC_WORD; - tmp->ctrl.dst_size = DMA_DATA_SIZE_WORD; - tmp->ctrl.dst_inc = DMA_DATA_INC_WORD; - - desc[nr - 1].ctrl.cycle_ctrl = DMA_CYCLE_CTRL_BASIC; - WRITE_REG(DMAx->CHPRIALTCLR, (1 << channel)); - burst ? (DMAx->CHUSEBURSTSET = (1 << channel)) : (DMAx->CHUSEBURSTCLR, (1 << channel)); - WRITE_REG(DMAx->CHPRCLR, (1 << channel)); - - MODIFY_REG(DMAx->CH_SELCON[channel], DMA_CH0_SELCON_MSEL_MSK, msel << DMA_CH0_SELCON_MSEL_POSS); - MODIFY_REG(DMAx->CH_SELCON[channel], DMA_CH0_SELCON_MSIGSEL_MSK, msigsel << DMA_CH0_SELCON_MSIGSEL_POSS); - - WRITE_REG(DMAx->ICFR, (1 << channel)); - SET_BIT(DMAx->IER, (1 << channel)); - WRITE_REG(DMAx->CHENSET, (1 << channel)); - - return; -} -/** - * @} - */ - -/** @defgroup DMA_Public_Functions_Group3 DMA Control functions - * @brief DMA control functions - * - * @verbatim - =================================================================== - - #### DMA control functions #### - - =================================================================== - [..] - This subsection provides some functions allowing to control DMA: - (+) ald_dma_channel_config(): Control DMA channel ENABLE/DISABLE. - (+) ald_dma_interrupt_config(): Control DMA channel interrupt ENABLE or - DISABLE. - (+) ald_dma_get_it_status(): Check whether the specified channel - interrupt is SET or RESET. - (+) ald_dma_get_flag_status(): Check whether the specified channel - flag is SET or RESET. - (+) ald_dma_clear_flag_status(): Clear the specified channel - pending flag - - @endverbatim - * @{ - */ - -/** - * @brief Configure channel enable or disable. It will unbind descriptor with - * channel, when channel has been disable. - * @param DMAx: Pointer to DMA peripheral - * @param channel: channel index - * @param state: status of channel: - * @arg ENABLE: Enable the channel - * @arg DISABLE: Disable the channel - * @retval None - */ -void ald_dma_channel_config(DMA_TypeDef *DMAx, uint8_t channel, type_func_t state) -{ - dma_descriptor_t *descr, *alt_descr; - - assert_param(IS_DMA(DMAx)); - assert_param(IS_DMA_CHANNEL(channel)); - assert_param(IS_FUNC_STATE(state)); - - descr = (dma_descriptor_t *)(DMAx->CTRLBASE) + channel; - alt_descr = (dma_descriptor_t *)(DMAx->ALTCTRLBASE) + channel; - - if (state) { - WRITE_REG(DMAx->CHENSET, (1 << channel)); - } - else { - memset(descr, 0x00, sizeof(dma_descriptor_t)); - memset(alt_descr, 0x00, sizeof(dma_descriptor_t)); - WRITE_REG(DMAx->CH_SELCON[channel], 0x0); - WRITE_REG(DMAx->CHENCLR, (1 << channel)); - } - - return; -} - -/** - * @brief Configure the interrupt enable or disable - * @param DMAx: Pointer to DMA peripheral - * @param channel: Channel index or DMA_ERR. - * @arg 0~5: Channel index - * @arg DMA_ERR: DMA bus error - * @param state: status of channel: - * @arg ENABLE: Enable the channel - * @arg DISABLE: Disable the channel - * - * @retval None - */ -void ald_dma_interrupt_config(DMA_TypeDef *DMAx, uint8_t channel, type_func_t state) -{ - assert_param(IS_DMA(DMAx)); - assert_param(IS_DMA_IT_TYPE(channel)); - assert_param(IS_FUNC_STATE(state)); - - if (state) - SET_BIT(DMAx->IER, (1 << channel)); - else - CLEAR_BIT(DMAx->IER, (1 << channel)); - - return; -} - -/** - * @brief Check whether the specified channel interrupt - * is set or reset - * @param DMAx: Pointer to DMA peripheral - * @param channel: Channel index or DMA_ERR - * @arg 0~5: Channel index - * @arg DMA_ERR: DMA bus error - * @retval Status: - * - SET: Channel interrupt is set - * - RESET: Channel interrupt is reset - */ -it_status_t ald_dma_get_it_status(DMA_TypeDef *DMAx, uint8_t channel) -{ - assert_param(IS_DMA(DMAx)); - assert_param(IS_DMA_IT_TYPE(channel)); - - if (READ_BIT(DMAx->IER, (1 << channel))) - return SET; - - return RESET; -} - -/** - * @brief Check whether the specified channel flag - * is set or reset - * @param DMAx: Pointer to DMA peripheral - * @param channel: Channel index or DMA_ERR - * @arg 0~5: Channel index - * @arg DMA_ERR: DMA bus error - * @retval Status: - * - SET: Channel flag is set - * - RESET: Channel flag is reset - */ -flag_status_t ald_dma_get_flag_status(DMA_TypeDef *DMAx, uint8_t channel) -{ - assert_param(IS_DMA(DMAx)); - assert_param(IS_DMA_IT_TYPE(channel)); - - if (READ_BIT(DMAx->IFLAG, (1 << channel))) - return SET; - - return RESET; -} - -/** - * @brief Clear the specified channel pending flag - * @param DMAx: Pointer to DMA peripheral - * @param channel: Channel index or DMA_ERR - * @arg 0~5: Channel index - * @arg DMA_ERR: DMA bus error - * @retval None - */ -void ald_dma_clear_flag_status(DMA_TypeDef *DMAx, uint8_t channel) -{ - assert_param(IS_DMA(DMAx)); - assert_param(IS_DMA_IT_TYPE(channel)); - - WRITE_REG(DMAx->ICFR, (1 << channel)); - return; -} - -/** - * @brief Get the completion status of the descriptor - * @param DMAx: Pointer to DMA peripheral - * @param channel: Channel index - * @retval Completion status: - * - DMA_DESCP_CPLT_PRI: Primary descriptor has been completed - * - DMA_DESCP_CPLT_ALT: Alternate descriptor has been completed - * - DMA_DESCP_CPLT_ALL: Both primary and alternate descriptors have been completed - */ -dma_descrp_cplt_t ald_dma_descriptor_cplt_get(DMA_TypeDef *DMAx, uint8_t channel) -{ - uint8_t pri, alt; - dma_descriptor_t *desc; - - assert_param(IS_DMA(DMAx)); - assert_param(IS_DMA_IT_TYPE(channel)); - - desc = (dma_descriptor_t *)(DMAx->CTRLBASE) + channel; - pri = desc->ctrl.cycle_ctrl; - desc = (dma_descriptor_t *)(DMAx->ALTCTRLBASE) + channel; - alt = desc->ctrl.cycle_ctrl; - - if ((pri == 0) && (alt == 0)) - return DMA_DESCP_CPLT_ALL; - - if (pri == 0) - return DMA_DESCP_CPLT_PRI; - else - return DMA_DESCP_CPLT_ALT; -} -/** - * @} - */ - -/** - * @} - */ -#endif /* ALD_DMA */ -/** - * @} - */ - -/** - * @} - */ diff --git a/bsp/essemi/es32f0334/libraries/ES32F033x_ALD_StdPeriph_Driver/Source/ald_flash.c b/bsp/essemi/es32f0334/libraries/ES32F033x_ALD_StdPeriph_Driver/Source/ald_flash.c deleted file mode 100644 index 44d25a7f76..0000000000 --- a/bsp/essemi/es32f0334/libraries/ES32F033x_ALD_StdPeriph_Driver/Source/ald_flash.c +++ /dev/null @@ -1,208 +0,0 @@ -/** - ********************************************************************************* - * - * @file ald_flash.c - * @brief FLASH module driver. - * - * @version V1.0 - * @date 20 Nov 2017 - * @author AE Team - * @note - * - * Copyright (C) Shanghai Eastsoft Microelectronics Co. Ltd. All rights reserved. - */ - -#include "ald_flash.h" - - -/** @addtogroup ES32FXXX_ALD - * @{ - */ - -/** @defgroup FLASH FLASH - * @brief FLASH module driver - * @{ - */ - -#ifdef ALD_FLASH - -#if defined ( __ICCARM__ ) -#define __RAMFUNC __ramfunc -#else -#define __RAMFUNC -#endif - -/** @defgroup Flash_Private_Variables Flash Private Variables - * @{ - */ -/* global variable*/ -static op_cmd_type OP_CMD = OP_FLASH; -/** - * @} - */ - -/** @defgroup Flash_Private_Functions Flash Private Functions - * @brief Flash Private functions - * @{ - */ -/** - * @brief Unlock the flash. - * @retval Status, see @ref ald_status_t. - */ -__RAMFUNC static ald_status_t flash_unlock(void) -{ - uint16_t i; - uint16_t op_cmd = OP_CMD; - - if (READ_BIT(MSC->FLASHSR, MSC_FLASHSR_BUSY_MSK)) - return ERROR; - - FLASH_REG_UNLOCK(); - FLASH_IAP_ENABLE(); - FLASH_REQ(); - - for (i = 0; i < 0xFFFF; i++) { - if (READ_BIT(MSC->FLASHSR, MSC_FLASHSR_FLASHACK_MSK)) - break; - } - - return i == 0xFFFF ? ERROR : OK; -} - -/** - * @brief Lock the flash. - * @retval Status, see @ref ald_status_t. - */ -__RAMFUNC static ald_status_t flash_lock(void) -{ - uint16_t i; - uint16_t op_cmd = OP_CMD; - - FLASH_REG_UNLOCK(); - WRITE_REG(MSC->FLASHCR, 0x0); - - for (i = 0; i < 0xFFFF; i++) { - if (!(READ_BIT(MSC->FLASHSR, MSC_FLASHSR_FLASHACK_MSK))) - break; - } - - return i == 0xFFFF ? ERROR : OK; -} - -/** - * @brief Erase one page. - * @param addr: The erased page's address - * @retval Status, see @ref ald_status_t. - */ -__RAMFUNC ald_status_t flash_page_erase(uint32_t addr) -{ - uint32_t i; - uint16_t op_cmd = OP_CMD; - - if (flash_unlock() != OK) - goto end; - - if (op_cmd == OP_FLASH) { - CLEAR_BIT(MSC->FLASHADDR, MSC_FLASHADDR_IFREN_MSK); - MODIFY_REG(MSC->FLASHADDR, MSC_FLASHADDR_ADDR_MSK, FLASH_PAGE_ADDR(addr) << MSC_FLASHADDR_ADDR_POSS); - } - else { - SET_BIT(MSC->FLASHADDR, MSC_FLASHADDR_IFREN_MSK); - MODIFY_REG(MSC->FLASHADDR, MSC_FLASHADDR_ADDR_MSK, INFO_PAGE_ADDR(addr) << MSC_FLASHADDR_ADDR_POSS); - } - - WRITE_REG(MSC->FLASHCMD, FLASH_CMD_PE); - - for (i = 0; i < 0xFFFF; i++) { - if (READ_BIT(MSC->FLASHSR, MSC_FLASHSR_BUSY_MSK)) - continue; - if (READ_BIT(MSC->FLASHSR, MSC_FLASHSR_ADDR_OV_MSK)) - goto end; - if (READ_BIT(MSC->FLASHSR, MSC_FLASHSR_WRP_FLAG_MSK)) - goto end; - if (READ_BIT(MSC->FLASHSR, MSC_FLASHSR_SERA_MSK)) - break; - } - - if (i == 0xFFFF) - goto end; - - if (flash_lock() == ERROR) - goto end; - - return OK; -end: - flash_lock(); - return ERROR; -} - -/** - * @brief Programme a word. - * @param addr: The word's address, it is must word align. - * @param data: The 8 bytes data be write. - * @param len: The number of data be write. - * @param fifo: Choose if use fifo. - * @retval Status, see @ref ald_status_t. - */ -__RAMFUNC ald_status_t flash_word_program(uint32_t addr, uint32_t *data, uint32_t len, uint32_t fifo) -{ - uint16_t i = 0; - uint16_t prog_len; - uint32_t *p_data = data; - uint16_t op_cmd = OP_CMD; - - if (flash_unlock() != OK) - goto end; - - if (op_cmd == OP_FLASH) - CLEAR_BIT(MSC->FLASHADDR, MSC_FLASHADDR_IFREN_MSK); - else - SET_BIT(MSC->FLASHADDR, MSC_FLASHADDR_IFREN_MSK); - - MODIFY_REG(MSC->FLASHADDR, MSC_FLASHADDR_ADDR_MSK, addr << MSC_FLASHADDR_ADDR_POSS); - MODIFY_REG(MSC->FLASHCR, MSC_FLASHCR_FIFOEN_MSK, fifo << MSC_FLASHCR_FIFOEN_POS); - - for (prog_len = 0; prog_len < len; prog_len++) { - if (fifo) { - WRITE_REG(MSC->FLASHFIFO, p_data[0]); - WRITE_REG(MSC->FLASHFIFO, p_data[1]); - } - else { - WRITE_REG(MSC->FLASHDL, p_data[0]); - WRITE_REG(MSC->FLASHDH, p_data[1]); - WRITE_REG(MSC->FLASHCMD, FLASH_CMD_WP); - } - - p_data += 2; - - for (i = 0; i < 0xFFFF; i++) { - if (READ_BIT(MSC->FLASHSR, MSC_FLASHSR_BUSY_MSK)) - continue; - if (READ_BIT(MSC->FLASHSR, MSC_FLASHSR_PROG_MSK)) - break; - } - } - if (i == 0xFFFF) - goto end; - - if (flash_lock() == ERROR) - goto end; - - return OK; -end: - flash_lock(); - return ERROR; -} -/** - * @} - */ - -#endif - -/** - * @} - */ - -/** - * @} - */ diff --git a/bsp/essemi/es32f0334/libraries/ES32F033x_ALD_StdPeriph_Driver/Source/ald_flash_ext.c b/bsp/essemi/es32f0334/libraries/ES32F033x_ALD_StdPeriph_Driver/Source/ald_flash_ext.c deleted file mode 100644 index 44e8fe7d9c..0000000000 --- a/bsp/essemi/es32f0334/libraries/ES32F033x_ALD_StdPeriph_Driver/Source/ald_flash_ext.c +++ /dev/null @@ -1,330 +0,0 @@ -/** - ********************************************************************************* - * - * @file ald_flash_ext.c - * @brief FLASH module driver. - * - * @version V1.0 - * @date 15 May 2019 - * @author AE Team - * @note - * - * Copyright (C) Shanghai Eastsoft Microelectronics Co. Ltd. All rights reserved. - * - ********************************************************************************* - * - ********************************************************************************* - * @verbatim - ============================================================================== - ##### FLASH Peripheral features ##### - ============================================================================== - [..] - Base address is 0x00000000 - - [..] - FLASH have just one programme mode , word programme. - word programme can programme 8 bytes once ; - - ============================================================================== - ##### How to use this driver ##### - ============================================================================== - [..] - (#) programme flash using ald_flash_write(uint32_t addr, uint8_t *buf, uint16_t len) - (++) call the function and supply all the three paraments is needs, addr means - the first address to write in this operation, buf is a pointer to the data which - need writing to flash. - - (#) erase flash using ald_flash_erase(uint32_t addr, uint16_t len) - (++) call the function and supply two paraments, addr is the first address to erase, - len is the length to erase - - (#) read flash using ald_flash_read(uint32_t *ram_addr, uint32_t addr, uint16_t len) - (++) read the flash and save to a buffer, ram_addr is the buffer's first address, - addr is the start reading address in flash, len is the length need read - - @endverbatim - */ - - -#include "ald_flash.h" - - -/** @addtogroup ES32FXXX_ALD - * @{ - */ - -/** @addtogroup FLASH - * @{ - */ - -#ifdef ALD_FLASH - -/** @addtogroup Flash_Private_Variables - * @{ - */ -/* opration buffer*/ -static uint8_t write_buf[FLASH_PAGE_SIZE]; -/** - * @} - */ - -/** @addtogroup Flash_Private_Functions - * @{ - */ - -/** - * @brief Check whether the flash between the given address section - * have been writen, if it have been writen, return TRUE, else - * return FALSE. - * @param begin_addr: The begin address. - * @param end_addr: The end address. - * @retval The check result - * - TRUE - * - FALSE - */ -static type_bool_t page_have_writen(uint32_t begin_addr, uint32_t end_addr) -{ - uint8_t* addr_to_read; - uint8_t value; - uint32_t index; - - /* Check the parameters */ - assert_param(IS_FLASH_ADDRESS(begin_addr)); - assert_param(IS_FLASH_ADDRESS(end_addr)); - - addr_to_read = (uint8_t *)begin_addr; - index = begin_addr; - value = 0xFF; - - if (begin_addr > end_addr) - return FALSE; - - while (index++ <= end_addr) { - value = *addr_to_read++; - - if (value != 0xFF) - break; - } - - return value == 0xFF ? FALSE : TRUE; -} -/** - * @} - */ - -/** @defgroup Flash_Public_Functions Flash Public Functions - * @verbatim - =============================================================================== - ##### Flash operation functions ##### - =============================================================================== - [..] - This section provides functions allowing to operate flash, such as read and write. - - @endverbatim - * @{ - */ - -/** - * @brief read the specified length bytes from flash, and store to the specified area. - * @param ram_addr: the specified area to store the reading bytes. - * @param addr: the start address. - * @param len: the length to read. - * @retval Status, see @ref ald_status_t. - */ -ald_status_t ald_flash_read(uint32_t *ram_addr, uint32_t addr, uint16_t len) -{ - uint32_t i; - uint32_t temp; - - assert_param(IS_4BYTES_ALIGN(ram_addr)); - assert_param(IS_FLASH_ADDRESS(addr)); - assert_param(IS_FLASH_ADDRESS(addr + len - 1)); - - temp = (uint32_t)ram_addr; - - if (((temp & 0x3) != 0) || (((addr) & 0x3) != 0)) - return ERROR; - - for (i = 0; i < len; i++) { - ram_addr[i] = ((uint32_t *)addr)[i]; - } - - return OK; -} - -/** - * @brief Write the give bytes to the given address section. - * @param addr: The start address to write. - * @param buf: The bytes' address. - * @param len: The length to write,and multiple of 2. - * @retval Status, see @ref ald_status_t. - */ - -ald_status_t ald_flash_write(uint32_t addr, uint8_t *buf, uint16_t len) -{ - uint32_t index = 0; - uint32_t para = 0; - uint32_t index2 = 0; - uint32_t start_write_addr; - uint32_t end_write_addr; - uint32_t start_word_addr; - uint32_t end_word_addr; - uint16_t len_to_write; - uint32_t len_index; - type_bool_t need_erase_page; - - assert_param(IS_FLASH_ADDRESS(addr)); - assert_param(IS_FLASH_ADDRESS(addr + len - 1)); - - len_to_write = len; - - __disable_irq(); - while (len_to_write > 0) { - need_erase_page = FALSE; - - for (index = 0; index < FLASH_PAGE_SIZE; index++) - write_buf[index] = 0xFF; - - start_write_addr = addr + (len - len_to_write); - end_write_addr = addr + len - 1; - end_write_addr = FLASH_PAGE_ADDR(start_write_addr) == FLASH_PAGE_ADDR(end_write_addr) - ? end_write_addr : FLASH_PAGEEND_ADDR(start_write_addr); - need_erase_page = page_have_writen(FLASH_WORD_ADDR(start_write_addr), - FLASH_WORDEND_ADDR(end_write_addr)); - - if (need_erase_page) { - if (ERROR == ald_flash_read((uint32_t *)write_buf, FLASH_PAGE_ADDR(start_write_addr), - FLASH_PAGE_SIZE >> 2)) { - __enable_irq(); - return ERROR; - } - - if (ERROR == flash_page_erase(FLASH_PAGE_ADDR(start_write_addr))) { - __enable_irq(); - return ERROR; - } - - para = end_write_addr & (FLASH_PAGE_SIZE - 1); - index = start_write_addr & (FLASH_PAGE_SIZE - 1); - index2 = len - len_to_write; - - while (index <= para) - write_buf[index++] = buf[index2++]; - - index2 = 0; - index = FLASH_PAGE_ADDR(start_write_addr); - len_index = FLASH_PAGE_SIZE; - } - else { - para = end_write_addr & (FLASH_PAGE_SIZE - 1); - index = start_write_addr & (FLASH_PAGE_SIZE - 1); - index2 = len - len_to_write; - - while (index <= para) - write_buf[index++] = buf[index2++]; - - start_word_addr = FLASH_WORD_ADDR(start_write_addr); - end_word_addr = FLASH_WORDEND_ADDR(end_write_addr); - index2 = (FLASH_WORD_ADDR(start_word_addr) - FLASH_PAGE_ADDR(start_word_addr)); - index = start_word_addr; - len_index = end_word_addr - start_word_addr + 1; - } - - if (ERROR == flash_word_program(index, (uint32_t *)(write_buf + index2), (len_index >> 3), FLASH_FIFO)) { - __enable_irq(); - return ERROR; - } - - len_to_write = len_to_write - (end_write_addr - start_write_addr + 1); - } - - __enable_irq(); - return OK; -} - -/** - * @brief erase The flash between the given address section. - * @param addr: The start address to erase. - * @param len: The length to erase. - * @retval Status, see @ref ald_status_t. - */ -ald_status_t ald_flash_erase(uint32_t addr, uint16_t len) -{ - uint32_t index; - int32_t para; - int32_t start_erase_addr; - int32_t end_erase_addr; - uint16_t len_not_erase; - uint32_t len_index; - type_bool_t page_need_save; - - assert_param(IS_FLASH_ADDRESS(addr)); - assert_param(IS_FLASH_ADDRESS(addr + len - 1)); - - len_not_erase = len; - - __disable_irq(); - while (len_not_erase > 0) { - page_need_save = FALSE; - - start_erase_addr = addr + len - len_not_erase; - end_erase_addr = addr + len - 1; - end_erase_addr = (FLASH_PAGE_ADDR(start_erase_addr) == FLASH_PAGE_ADDR(end_erase_addr)) - ? end_erase_addr : FLASH_PAGEEND_ADDR(start_erase_addr); - - if (start_erase_addr != FLASH_PAGE_ADDR(start_erase_addr)) { - if (page_have_writen(FLASH_PAGE_ADDR(start_erase_addr), (start_erase_addr - 1))) - page_need_save = TRUE; - } - if (end_erase_addr != FLASH_PAGEEND_ADDR(end_erase_addr)) { - if (page_have_writen((end_erase_addr + 1), FLASH_PAGEEND_ADDR(end_erase_addr))) - page_need_save = TRUE; - } - - if (page_need_save) { - if (ERROR == ald_flash_read((uint32_t *)write_buf, FLASH_PAGE_ADDR(start_erase_addr), - FLASH_PAGE_SIZE >> 2)) { - __enable_irq(); - return ERROR; - } - } - - if (ERROR == flash_page_erase(FLASH_PAGE_ADDR(start_erase_addr))) { - __enable_irq(); - return ERROR; - } - - if (page_need_save) { - para = end_erase_addr & (FLASH_PAGE_SIZE - 1); - index = start_erase_addr & (FLASH_PAGE_SIZE - 1); - - while (index <= para) - write_buf[index++] = 0xFF; - - index = FLASH_PAGE_ADDR(start_erase_addr); - len_index = FLASH_PAGE_SIZE; - if (ERROR == flash_word_program(index, (uint32_t *)write_buf, (len_index >> 3), FLASH_FIFO)) { - __enable_irq(); - return ERROR; - } - } - len_not_erase = len_not_erase - (end_erase_addr - start_erase_addr + 1); - } - - __enable_irq(); - return OK; -} -/** - * @} - */ - - -#endif - -/** - * @} - */ - -/** - * @} - */ diff --git a/bsp/essemi/es32f0334/libraries/ES32F033x_ALD_StdPeriph_Driver/Source/ald_gpio.c b/bsp/essemi/es32f0334/libraries/ES32F033x_ALD_StdPeriph_Driver/Source/ald_gpio.c deleted file mode 100644 index 08366e9350..0000000000 --- a/bsp/essemi/es32f0334/libraries/ES32F033x_ALD_StdPeriph_Driver/Source/ald_gpio.c +++ /dev/null @@ -1,623 +0,0 @@ -/** - ********************************************************************************* - * - * @file ald_gpio.c - * @brief GPIO module driver. - * This file provides firmware functions to manage the following - * functionalities of the General Purpose Input/Output (GPIO) peripheral: - * + Initialization functions - * + IO operation functions - * + Control functions - * - * @version V1.0 - * @date 07 Nov 2017 - * @author AE Team - * @note - * - * Copyright (C) Shanghai Eastsoft Microelectronics Co. Ltd. All rights reserved. - * - ********************************************************************************* - * @verbatim - ============================================================================== - ##### GPIO Peripheral features ##### - ============================================================================== - [..] - Subject to the specific hardware characteristics of each I/O port listed in the datasheet, each - port bit of the General Purpose IO (GPIO) Ports, can be individually configured by software - in several modes: - (+) Input mode - (+) Analog mode - (+) Output mode - (+) External interrupt/event lines - - [..] - During and just after reset, the external interrupt lines are not active and - the I/O ports are configured Analog mode. - - [..] - All GPIO pins have weak internal pull-up and pull-down resistors, which can be - activated or not. - - [..] - In Output mode, each IO can be configured on open-drain or push-pull - type and the Output driver can be selected depending on ODRV register. - - [..] - In Input mode, each IO can select filter function. - - [..] - Each IO can select TTL or SMIT type. - - [..] - Each IO have up to eight functions, user can configure the functions depend - on the user's environment. - - [..] - Each IO can be locked. Once locked, uesr can only change the output data. - Only when the CPU reset to unlock the GPIO port. - - [..] - All ports have external interrupt/event capability. To use external interrupt - lines, the port must be configured in input mode. All available GPIO pins are - connected to the 16 external interrupt/event lines from EXTI0 to EXTI15. - - [..] - Each input line can be independently configured to select the type (event or interrupt) and - the corresponding trigger event (rising or falling). Each line can also masked - independently. A pending register maintains the status line of the interrupt requests. - - ============================================================================== - ##### How to use this driver ##### - ============================================================================== - [..] - (#) Enable the GPIO clock. - - (#) Configure the GPIO pin(s) using ald_gpio_init(). - (++) Configure the IO mode using "mode" member from gpio_init_t structure - (++) Activate Pull-up, Pull-down resistor using "pupd" member from gpio_init_t - structure. - (++) In Output mode, configured on open-drain or push-pull using "odos" - member from gpio_init_t structure. - (++) In Output mode, configured output driver using "odrv" member - from gpio_init_t structure. - (++) In Input mode, configured filter function using "flt" member - from gpio_init_t structure. - (++) Configured type using "type" member from gpio_init_t structure. - (++) Configured functions using "func" member from gpio_init_t structure. - (++) Analog mode is required when a pin is to be used as ADC channel - or DAC output. - - (#) Configure the GPIO pin(s) using ald_gpio_init_default(). - (++) Configure GPIO pin using default param: - init.mode = GPIO_MODE_OUTPUT; - init.odos = GPIO_PUSH_PULL; - init.pupd = GPIO_PUSH_UP; - init.odrv = GPIO_OUT_DRIVE_NORMAL; - init.flt = GPIO_FILTER_DISABLE; - init.type = GPIO_TYPE_TTL; - init.func = GPIO_FUNC_1; - - (#) In case of external interrupt/event mode selection, user need invoke - ald_gpio_exti_init() to configure some param. And then invoke - ald_gpio_exti_interrupt_config() to enable/disable external interrupt/event. - - (#) In case of external interrupt/event mode selection, configure NVIC IRQ priority - mapped to the EXTI line using NVIC_SetPriority() and enable it using - NVIC_EnableIRQ(). - - (#) To get the level of a pin configured in input mode use GPIO_read_pin(). - - (#) To set/reset the level of a pin configured in output mode use - ald_gpio_write_pin()/ald_gpio_toggle_pin(). - - (#) To lock pin configuration until next reset use ald_gpio_lock_pin(). - - (#) Configure external interrupt mode and enable/disable using - ald_gpio_exti_interrupt_config(). - - (#) Get external interrupt flag status using ald_gpio_exti_get_flag_status(). - - (#) Clear pending external interrupt flag status using - ald_gpio_exti_clear_flag_status(). - - @endverbatim - */ - -#include "ald_conf.h" -#include "ald_gpio.h" - - -/** @addtogroup ES32FXXX_ALD - * @{ - */ - -/** @defgroup GPIO GPIO - * @brief GPIO module driver - * @{ - */ - -#ifdef ALD_GPIO - -/** @defgroup GPIO_Public_Functions GPIO Public Functions - * @{ - */ - -/** @defgroup GPIO_Public_Functions_Group1 Initialization functions - * @brief Initialization and Configuration functions - * - @verbatim - =============================================================================== - ##### Initialization functions ##### - =============================================================================== - [..] - This section provides functions allowing to initialize the GPIOs or external - interrupt to be ready for use. - - @endverbatim - * @{ - */ - -/** - * @brief Initialize the GPIOx peripheral according to the specified - * parameters in the gpio_init_t. - * @param GPIOx: Where x can be (A--H) to select the GPIO peripheral. - * @param pin: The pin which need to initialize. - * @param init: Pointer to a gpio_init_t structure that can contains - * the configuration information for the specified parameters. - * @retval None - */ -void ald_gpio_init(GPIO_TypeDef *GPIOx, uint16_t pin, gpio_init_t *init) -{ - uint32_t i, pos, mask, tmp; - - assert_param(IS_GPIO_PORT(GPIOx)); - assert_param(IS_GPIO_PIN(pin)); - assert_param(IS_GPIO_MODE(init->mode)); - assert_param(IS_GPIO_ODOS(init->odos)); - assert_param(IS_GPIO_PUPD(init->pupd)); - assert_param(IS_GPIO_ODRV(init->odrv)); - assert_param(IS_GPIO_FLT(init->flt)); - assert_param(IS_GPIO_TYPE(init->type)); - assert_param(IS_GPIO_FUNC(init->func)); - - for (i = 0; i < 16; ++i) { - if (((pin >> i) & 0x1) == 0) - continue; - - /* Get position and 2-bits mask */ - pos = i << 1; - mask = 0x3 << pos; - - /* Set PIN mode */ - tmp = READ_REG(GPIOx->MODE); - tmp &= ~mask; - tmp |= (init->mode << pos); - WRITE_REG(GPIOx->MODE, tmp); - - /* Set PIN open-drain or push-pull */ - tmp = READ_REG(GPIOx->ODOS); - tmp &= ~mask; - tmp |= (init->odos << pos); - WRITE_REG(GPIOx->ODOS, tmp); - - /* Set PIN push-up or/and push-down */ - tmp = READ_REG(GPIOx->PUPD); - tmp &= ~mask; - tmp |= (init->pupd << pos); - WRITE_REG(GPIOx->PUPD, tmp); - - /* Set PIN output driver */ - tmp = READ_REG(GPIOx->ODRV); - tmp &= ~mask; - tmp |= (init->odrv << pos); - WRITE_REG(GPIOx->ODRV, tmp); - - /* Get position and 1-bit mask */ - pos = i; - mask = 0x1 << pos; - - /* Set PIN filter enable or disable */ - tmp = READ_REG(GPIOx->FLT); - tmp &= ~mask; - tmp |= (init->flt << pos); - WRITE_REG(GPIOx->FLT, tmp); - - /* Set PIN type ttl or smit */ - tmp = READ_REG(GPIOx->TYPE); - tmp &= ~mask; - tmp |= (init->type << pos); - WRITE_REG(GPIOx->TYPE, tmp); - - /* Configure PIN function */ - pos = i < 8 ? (i << 2) : ((i - 8) << 2); - mask = 0xF << pos; - tmp = i < 8 ? READ_REG(GPIOx->FUNC0) : READ_REG(GPIOx->FUNC1); - tmp &= ~mask; - tmp |= (init->func << pos); - i < 8 ? WRITE_REG(GPIOx->FUNC0, tmp) : WRITE_REG(GPIOx->FUNC1, tmp); - } - - return; -} - -/** - * @brief Initialize the GPIOx peripheral using the default parameters. - * @param GPIOx: Where x can be (A--H) to select the GPIO peripheral. - * @param pin: The pin which need to initialize. - * @retval None - */ -void ald_gpio_init_default(GPIO_TypeDef *GPIOx, uint16_t pin) -{ - gpio_init_t init; - - /* Fill GPIO_init_t structure with default parameter */ - init.mode = GPIO_MODE_OUTPUT; - init.odos = GPIO_PUSH_PULL; - init.pupd = GPIO_PUSH_UP; - init.odrv = GPIO_OUT_DRIVE_NORMAL; - init.flt = GPIO_FILTER_DISABLE; - init.type = GPIO_TYPE_CMOS; - init.func = GPIO_FUNC_1; - - ald_gpio_init(GPIOx, pin, &init); - return; -} - -/** - * @brief Sets GPIO function to default(func0). - * @param GPIOx: Where x can be (A--H) to select the GPIO peripheral. - * @retval None - */ -void ald_gpio_func_default(GPIO_TypeDef *GPIOx) -{ - WRITE_REG(GPIOx->FUNC0, 0x00); - WRITE_REG(GPIOx->FUNC1, 0x00); - - return; -} - -/** - * @brief Initialize the external interrupt according to the specified - * parameters in the exti_init_t. - * @param GPIOx: Where x can be (A--H) to select the GPIO peripheral. - * @param pin: The pin which need to initialize. - * @param init: Pointer to a exti_init_t structure that can contains - * the configuration information for the specified parameters. - * @retval None - */ -void ald_gpio_exti_init(GPIO_TypeDef *GPIOx, uint16_t pin, exti_init_t *init) -{ - uint8_t i; - uint8_t port; - - assert_param(IS_GPIO_PORT(GPIOx)); - assert_param(IS_GPIO_PIN(pin)); - assert_param(IS_FUNC_STATE(init->filter)); - assert_param(IS_EXTI_FLTCKS_TYPE(init->cks)); - - /* Get GPIO port */ - if (GPIOx == GPIOA) - port = 0x0; - else if (GPIOx == GPIOB) - port = 0x1; - else if (GPIOx == GPIOC) - port = 2; - else if (GPIOx == GPIOD) - port = 3; - else if (GPIOx == GPIOE) - port = 4; - else if (GPIOx == GPIOF) - port = 5; - else if (GPIOx == GPIOG) - port = 6; - else if (GPIOx == GPIOH) - port = 7; - else - port = 0; - - /* Get Pin index */ - for (i = 0; i < 16; ++i) { - if (((pin >> i) & 0x1) == 0x1) - break; - } - - /* Select external interrupt line */ - if (i <= 7) { - EXTI->EXTIPSR0 &= ~(0x7U << (i * 4)); - EXTI->EXTIPSR0 |= (port << (i * 4)); - } - else { - i -= 8; - EXTI->EXTIPSR1 &= ~(0x7U << (i * 4)); - EXTI->EXTIPSR1 |= (port << (i * 4)); - } - - /* Configure filter parameter */ - if (init->filter == ENABLE) { - SET_BIT(EXTI->EXTIFLTCR, pin); - MODIFY_REG(EXTI->EXTIFLTCR, GPIO_EXTIFLTCR_FLTCKS_MSK, init->cks << GPIO_EXTIFLTCR_FLTCKS_POSS); - MODIFY_REG(EXTI->EXTIFLTCR, GPIO_EXTIFLTCR_FLTSEL_MSK, init->filter_time << GPIO_EXTIFLTCR_FLTSEL_POSS); - } - else { - CLEAR_BIT(EXTI->EXTIFLTCR, pin); - } - - return; -} -/** - * @} - */ - -/** @defgroup GPIO_Public_Functions_Group2 IO operation functions - * @brief GPIO Read and Write - * - @verbatim - =============================================================================== - ##### IO operation functions ##### - =============================================================================== - [..] - This subsection provides a set of functions allowing to manage the GPIOs. - - @endverbatim - * @{ - */ - -/** - * @brief Read the specified input port pin. - * @param GPIOx: Where x can be (A--H) to select the GPIO peripheral. - * @param pin: Specifies the pin to read. - * @retval The input pin value - */ -uint8_t ald_gpio_read_pin(GPIO_TypeDef *GPIOx, uint16_t pin) -{ - assert_param(IS_GPIO_PORT(GPIOx)); - assert_param(IS_GPIO_PIN(pin)); - - if (READ_BIT(GPIOx->DIN, pin)) - return 1; - else - return 0; -} - -/** - * @brief Set or clear the select Pin data. - * @param GPIOx: Where x can be (A--H) to select the GPIO peripheral. - * @param pin: The specified pin to be written. - * @param val: The specifies value to be written. - * @retval None - */ -void ald_gpio_write_pin(GPIO_TypeDef *GPIOx, uint16_t pin, uint8_t val) -{ - assert_param(IS_GPIO_PORT(GPIOx)); - assert_param(IS_GPIO_PIN(pin)); - - if ((val & (0x01)) == 0x00) - CLEAR_BIT(GPIOx->DOUT, pin); - else - SET_BIT(GPIOx->DOUT, pin); - - return; -} - -/** - * @brief Turn over the select data. - * @param GPIOx: Where x can be (A--H) to select the GPIO peripheral. - * @param pin: Specifies the pin to turn over. - * @retval None - */ -void ald_gpio_toggle_pin(GPIO_TypeDef *GPIOx, uint16_t pin) -{ - assert_param(IS_GPIO_PORT(GPIOx)); - assert_param(IS_GPIO_PIN(pin)); - - WRITE_REG(GPIOx->BIR, pin); - return; -} - -/** - * @brief Turn over the direction. - * @param GPIOx: Where x can be (A--H) to select the GPIO peripheral. - * @param pin: Specifies the pin to turn over. - * @retval None - */ -void ald_gpio_toggle_dir(GPIO_TypeDef *GPIOx, uint16_t pin) -{ - uint32_t i, pos, mask, tmp, value; - - assert_param(IS_GPIO_PORT(GPIOx)); - assert_param(IS_GPIO_PIN(pin)); - - for (i = 0; i < 16; ++i) { - if (((pin >> i) & 0x1) == 0) - continue; - - /* Get position and 2-bits mask */ - pos = i << 1; - mask = 0x3 << pos; - - /* Get the new direction */ - tmp = READ_REG(GPIOx->MODE); - value = (tmp >> pos) & 0x3; - - if ((value == 2) || (value == 3)) - value = 1; - else if (value == 1) { - value = 2; - } - else { - continue; /* do nothing */ - } - - /* Set PIN mode */ - tmp &= ~mask; - tmp |= (value << pos); - WRITE_REG(GPIOx->MODE, tmp); - } - - return; -} - -/** - * @brief Lock the GPIO prot. Once locked, can - * only change the output data. Only when the CPU - * reset to unlock the GPIO port. - * @param GPIOx: Where x can be (A--H) to select the GPIO peripheral. - * @param pin: The specified Pin to be written. - * @retval None - */ -void ald_gpio_lock_pin(GPIO_TypeDef *GPIOx, uint16_t pin) -{ - assert_param(IS_GPIO_PORT(GPIOx)); - assert_param(IS_GPIO_PIN(pin)); - - MODIFY_REG(GPIOx->LOCK, GPIO_LOCK_KEY_MSK, UNLOCK_KEY << GPIO_LOCK_KEY_POSS); - WRITE_REG(GPIOx->LOCK, pin); - - return; -} - -/** - * @brief Read the specified input port pin. - * @param GPIOx: Where x can be (A--H) to select the GPIO peripheral. - * @retval The value; - */ -uint16_t ald_gpio_read_port(GPIO_TypeDef *GPIOx) -{ - assert_param(IS_GPIO_PORT(GPIOx)); - - return READ_REG(GPIOx->DIN); -} - -/** - * @brief Set or clear the select Pin data. - * @param GPIOx: Where x can be (A--H) to select the GPIO peripheral. - * @param val: The specifies value to be written. - * @retval None - */ -void ald_gpio_write_port(GPIO_TypeDef *GPIOx, uint16_t val) -{ - assert_param(IS_GPIO_PORT(GPIOx)); - - WRITE_REG(GPIOx->DOUT, val); - return; -} - - -/** - * @} - */ - -/** @defgroup GPIO_Public_Functions_Group3 Control functions - * @brief EXTI Control functions - * - @verbatim - =============================================================================== - ##### Control functions ##### - =============================================================================== - [..] - This subsection provides a set of functions allowing to - control external interrupt. - - @endverbatim - * @{ - */ - -/** - * @brief Configure the interrupt according to the specified parameter. - * @param pin: The Pin which need to configure. - * @param style: External interrupt trigger style. - * @param status: - * @arg ENABLE - * @arg DISABLE - * @retval None - */ -void ald_gpio_exti_interrupt_config(uint16_t pin, exti_trigger_style_t style, type_func_t status) -{ - assert_param(IS_GPIO_PIN(pin)); - assert_param(IS_TRIGGER_STYLE(style)); - assert_param(IS_FUNC_STATE(status)); - - if (status == ENABLE) { - if (style == EXTI_TRIGGER_RISING_EDGE) { - SET_BIT(EXTI->EXTIRER, pin); - } - else if (style == EXTI_TRIGGER_TRAILING_EDGE) { - SET_BIT(EXTI->EXTIFER, pin); - } - else if (style == EXTI_TRIGGER_BOTH_EDGE) { - SET_BIT(EXTI->EXTIRER, pin); - SET_BIT(EXTI->EXTIFER, pin); - } - else { - ; /* do nothing */ - } - - WRITE_REG(EXTI->EXTICFR, 0xffff); - SET_BIT(EXTI->EXTIEN, pin); - } - else { - if (style == EXTI_TRIGGER_RISING_EDGE) { - CLEAR_BIT(EXTI->EXTIRER, pin); - } - else if (style == EXTI_TRIGGER_TRAILING_EDGE) { - CLEAR_BIT(EXTI->EXTIFER, pin); - } - else if (style == EXTI_TRIGGER_BOTH_EDGE) { - CLEAR_BIT(EXTI->EXTIRER, pin); - CLEAR_BIT(EXTI->EXTIFER, pin); - } - else { - ; /* do nothing */ - } - - CLEAR_BIT(EXTI->EXTIEN, pin); - } - - return; -} - -/** - * @brief Get the Flag about external interrupt. - * @param pin: The pin which belong to external interrupt. - * @retval Flag status - * - SET - * - RESET - */ -flag_status_t ald_gpio_exti_get_flag_status(uint16_t pin) -{ - assert_param(IS_GPIO_PIN(pin)); - - if (READ_BIT(EXTI->EXTIFLAG, pin)) - return SET; - - return RESET; -} - -/** - * @brief Clear the external interrupt flag. - * @param pin: The pin which belong to external interrupt. - * @retval None - */ -void ald_gpio_exti_clear_flag_status(uint16_t pin) -{ - assert_param(IS_GPIO_PIN(pin)); - - WRITE_REG(EXTI->EXTICFR, pin); - return; -} -/** - * @} - */ - -/** - * @} - */ - -#endif /* ALD_GPIO */ -/** - * @} - */ - -/** - * @} - */ diff --git a/bsp/essemi/es32f0334/libraries/ES32F033x_ALD_StdPeriph_Driver/Source/ald_i2c.c b/bsp/essemi/es32f0334/libraries/ES32F033x_ALD_StdPeriph_Driver/Source/ald_i2c.c deleted file mode 100644 index 82faa31502..0000000000 --- a/bsp/essemi/es32f0334/libraries/ES32F033x_ALD_StdPeriph_Driver/Source/ald_i2c.c +++ /dev/null @@ -1,3109 +0,0 @@ -/** - ********************************************************************************* - * - * @file ald_i2c.c - * @brief I2C module driver. - * - * @version V1.0 - * @date 15 Nov 2017 - * @author AE Team - * @note - * - * Copyright (C) Shanghai Eastsoft Microelectronics Co. Ltd. All rights reserved. - * - @verbatim - ============================================================================== - ##### How to use this driver ##### - ============================================================================== - [..] - The I2C driver can be used as follows: - - (#) Declare a i2c_handle_t handle structure, for example: - i2c_handle_t hperh; - - (#) Configure the Communication Speed, Duty cycle, Addressing mode, Own Address1, - Dual Addressing mode, Own Address2, General call and Nostretch mode in the hperh init structure. - - (#) Initialize the I2C registers by calling the ald_i2c_init(). - (#) To check if target device is ready for communication, use the function ald_i2c_is_device_ready() - - (#) For I2C IO and IO MEM operations, three operation modes are available within this driver : - - *** Polling mode IO operation *** - ================================= - [..] - (+) Transmit in master mode an amount of data in blocking mode using ald_i2c_master_send() - (+) Receive in master mode an amount of data in blocking mode using ald_i2c_master_recv() - (+) Transmit in slave mode an amount of data in blocking mode using ald_i2c_slave_send() - (+) Receive in slave mode an amount of data in blocking mode using ald_i2c_slave_recv() - - *** Polling mode IO MEM operation *** - ===================================== - [..] - (+) Write an amount of data in blocking mode to a specific memory address using ald_i2c_mem_write() - (+) Read an amount of data in blocking mode from a specific memory address using ald_i2c_mem_read() - - - *** Interrupt mode IO operation *** - =================================== - [..] - (+) The I2C interrupts should have the highest priority in the application in order - to make them uninterruptible. - (+) Transmit in master mode an amount of data in non-blocking mode using ald_i2c_master_send_by_it() - (+) At transmission end of transfer, hperh->master_tx_cplt_cbk() is executed and user can - add his own code by customization of function pointer hperh->master_tx_cplt_cbk() - (+) Receive in master mode an amount of data in non-blocking mode using ald_i2c_master_recv_by_it() - (+) At reception end of transfer, hperh->master_rx_cplt_cbk() is executed and user can - add his own code by customization of function pointer hperh->master_rx_cplt_cbk() - (+) Transmit in slave mode an amount of data in non-blocking mode using ald_i2c_slave_send_by_it() - (+) At transmission end of transfer, hperh->slave_tx_cplt_cbk() is executed and user can - add his own code by customization of function pointer hperh->slave_tx_cplt_cbk() - (+) Receive in slave mode an amount of data in non-blocking mode using ald_i2c_slave_recv_by_it() - (+) At reception end of transfer, hperh->slave_rx_cplt_cbk() is executed and user can - add his own code by customization of function pointer hperh->slave_rx_cplt_cbk() - (+) In case of transfer Error, hperh->error_callback() function is executed and user can - add his own code by customization of function pointer hperh->error_callback() - - *** Interrupt mode IO MEM operation *** - ======================================= - [..] - (+) The I2C interrupts should have the highest priority in the application in order - to make them uninterruptible. - (+) Write an amount of data in non-blocking mode with Interrupt to a specific memory address using - ald_i2c_mem_write_by_it() - (+) At Memory end of write transfer, hperh->mem_tx_cplt_cbk() is executed and user can - add his own code by customization of function pointer hperh->mem_tx_cplt_cbk() - (+) Read an amount of data in non-blocking mode with Interrupt from a specific memory address using - ald_i2c_mem_read_by_it() - (+) At Memory end of read transfer, hperh->mem_rx_cplt_cbk() is executed and user can - add his own code by customization of function pointer hperh->mem_rx_cplt_cbk() - (+) In case of transfer Error, hperh->error_callback() function is executed and user can - add his own code by customization of function pointer hperh->error_callback() - - *** DMA mode IO operation *** - ============================== - [..] - (+) Transmit in master mode an amount of data in non-blocking mode (DMA) using - ald_i2c_master_send_by_dma() - (+) At transmission end of transfer, hperh->master_tx_cplt_cbk() is executed and user can - add his own code by customization of function pointer hperh->master_tx_cplt_cbk() - (+) Receive in master mode an amount of data in non-blocking mode (DMA) using - ald_i2c_master_recv_by_dma() - (+) At reception end of transfer, hperh->master_rx_cplt_cbk() is executed and user can - add his own code by customization of function pointer hperh->master_rx_cplt_cbk() - (+) Transmit in slave mode an amount of data in non-blocking mode (DMA) using - ald_i2c_slave_send_by_dma() - (+) At transmission end of transfer, hperh->slave_tx_cplt_cbk() is executed and user can - add his own code by customization of function pointer hperh->slave_tx_cplt_cbk() - (+) Receive in slave mode an amount of data in non-blocking mode (DMA) using - ald_i2c_slave_recv_by_dma() - (+) At reception end of transfer, hperh->slave_rx_cplt_cbk() is executed and user can - add his own code by customization of function pointer hperh->slave_rx_cplt_cbk() - (+) In case of transfer Error, hperh->error_callback() function is executed and user can - add his own code by customization of function pointer hperh->error_callback() - - *** DMA mode IO MEM operation *** - ================================= - [..] - (+) Write an amount of data in non-blocking mode with DMA to a specific memory address using - ald_i2c_mem_write_by_dma() - (+) At Memory end of write transfer, hperh->mem_tx_cplt_cbk() is executed and user can - add his own code by customization of function pointer hperh->mem_tx_cplt_cbk() - (+) Read an amount of data in non-blocking mode with DMA from a specific memory address using - ald_i2c_mem_read_by_dma() - (+) At Memory end of read transfer, hperh->mem_rx_cplt_cbk() is executed and user can - add his own code by customization of function pointer hperh->mem_rx_cplt_cbk() - (+) In case of transfer Error, hperh->error_callback() function is executed and user can - add his own code by customization of function pointer hperh->error_callback() - - - *** I2C ald_status_t driver macros list *** - ================================== - [..] - Below the list of most used macros in I2C ald_status_t driver. - - (+) I2C_ENABLE: Enable the I2C peripheral - (+) I2C_DISABLE: Disable the I2C peripheral - (@) You can refer to the I2C ald_status_t driver header file for more useful macros - - - *** I2C Workarounds linked to Silicon Limitation *** - ==================================================== - [..] - Below the list of all silicon limitations implemented for library on our product. - (@) See ErrataSheet to know full silicon limitation list of your product. - - (#) Workarounds Implemented inside I2C library - (##) Wrong data read into data register (Polling and Interrupt mode) - (##) Start cannot be generated after a misplaced Stop - (##) Some software events must be managed before the current byte is being transferred: - Workaround: Use DMA in general, except when the Master is receiving a single byte. - For Interupt mode, I2C should have the highest priority in the application. - (##) Mismatch on the "Setup time for a repeated Start condition" timing parameter: - Workaround: Reduce the frequency down to 88 kHz or use the I2C Fast-mode if - supported by the slave. - (##) Data valid time (tVD;DAT) violated without the OVR flag being set: - Workaround: If the slave device allows it, use the clock stretching mechanism - by programming no_stretch = I2C_NOSTRETCH_DISABLE in ald_i2c_init. - - @endverbatim - ********************************************************************************* - */ - -#include "ald_i2c.h" - -/** @addtogroup ES32FXXX_ALD - * @{ - */ - -/** @defgroup I2C I2C - * @brief I2C module driver - * @{ - */ -#ifdef ALD_I2C - -/** @addtogroup I2C_Private_Constants I2C Private Constants - * @{ - */ -#define I2C_TIMEOUT_FLAG (__systick_interval / 20 + 1) -#define I2C_TIMEOUT_ADDR_SLAVE (__systick_interval * 10) -#define I2C_TIMEOUT_BUSY_FLAG (__systick_interval * 10) -#define I2C_MAX_DELAY 0xFFFFFFFF -/** - * @} - */ - -/** @addtogroup I2C_Private_Functions I2C Private Functions - * @{ - */ -#ifdef ALD_DMA -static void i2c_dma_master_send_cplt(void *argv); -static void i2c_dma_master_recv_cplt(void *argv); -static void i2c_dma_slave_send_cplt(void *argv); -static void i2c_dma_slave_recv_cplt(void *argv); -static void i2c_dma_mem_send_cplt(void *argv); -static void i2c_dma_mem_recv_cplt(void *argv); -static void i2c_dma_error(void *argv); -#endif -static ald_status_t i2c_master_req_write(i2c_handle_t *hperh, uint16_t dev_addr, uint32_t timeout); -static ald_status_t i2c_master_req_read(i2c_handle_t *hperh, uint16_t dev_addr, uint32_t timeout); -static ald_status_t i2c_req_mem_write(i2c_handle_t *hperh, uint16_t dev_addr, uint16_t mem_addr, - uint16_t add_size, uint32_t timeout); -static ald_status_t i2c_req_mem_read(i2c_handle_t *hperh, uint16_t dev_addr, uint16_t mem_addr, - uint16_t add_size, uint32_t timeout); -static ald_status_t i2c_wait_flag_to_timeout(i2c_handle_t *hperh, i2c_flag_t flag, - flag_status_t status, uint32_t timeout); -static ald_status_t i2c_wait_master_addr_to_timeout(i2c_handle_t *hperh, i2c_flag_t flag, uint32_t timeout); -static ald_status_t i2c_wait_txe_to_timeout(i2c_handle_t *hperh, uint32_t timeout); -static ald_status_t i2c_wait_btf_to_timeout(i2c_handle_t *hperh, uint32_t timeout); -static ald_status_t i2c_wait_rxne_to_timeout(i2c_handle_t *hperh, uint32_t timeout); -static ald_status_t i2c_wait_stop_to_timeout(i2c_handle_t *hperh, uint32_t timeout); -static ald_status_t i2c_is_ack_failed(i2c_handle_t *hperh); -static ald_status_t i2c_master_send_txe(i2c_handle_t *hperh); -static ald_status_t i2c_master_send_btf(i2c_handle_t *hperh); -static ald_status_t i2c_master_recv_rxne(i2c_handle_t *hperh); -static ald_status_t i2c_master_recv_btf(i2c_handle_t *hperh); -static ald_status_t i2c_slave_send_txe(i2c_handle_t *hperh); -static ald_status_t i2c_slave_send_btf(i2c_handle_t *hperh); -static ald_status_t i2c_slave_recv_rxne(i2c_handle_t *hperh); -static ald_status_t i2c_slave_recv_btf(i2c_handle_t *hperh); -static ald_status_t i2c_slave_addr(i2c_handle_t *hperh); -static ald_status_t i2c_slave_stopf(i2c_handle_t *hperh); -static ald_status_t i2c_slave_af(i2c_handle_t *hperh); -static uint32_t i2c_configure_speed(i2c_handle_t *hperh, uint32_t i2c_clk); -/** - * @} - */ - -/** @defgroup I2C_Public_Functions I2C Public functions - * @{ - */ - -/** @defgroup I2C_Public_Functions_Group1 Initialization functions - * @brief Initialization and Configuration functions - * -@verbatim - =============================================================================== - ##### Initialization and Configuration functions ##### - =============================================================================== - [..] This subsection provides a set of functions allowing to initialize and - de-initialiaze the I2Cx peripheral: - - (+) Call the function ald_i2c_init() to configure the selected device with - the selected configuration: - (++) Communication Speed - (++) Duty cycle - (++) Addressing mode - (++) Own Address 1 - (++) Dual Addressing mode - (++) Own Address 2 - (++) General call mode - (++) Nostretch mode - - (+) Call the function ald_i2c_reset() to restore the default configuration - of the selected I2Cx periperal. - -@endverbatim - * @{ - */ - -/** - * @brief Initializes the I2C according to the specified parameters - * in the i2c_init_t and initialize the associated handle. - * @param hperh: Pointer to a i2c_handle_t structure that contains - * the configuration information for the specified I2C. - * @retval Status, see @ref ald_status_t. - */ -ald_status_t ald_i2c_init(i2c_handle_t *hperh) -{ - uint32_t freqrange = 0; - uint32_t pclk1 = 0; - - if (hperh == NULL) - return ERROR; - - /* Check the parameters */ - assert_param(IS_I2C_TYPE(hperh->perh)); - assert_param(IS_I2C_CLOCK_SPEED(hperh->init.clk_speed)); - assert_param(IS_I2C_DUTY_CYCLE(hperh->init.duty)); - assert_param(IS_I2C_OWN_ADDRESS1(hperh->init.own_addr1)); - assert_param(IS_I2C_ADDRESSING_MODE(hperh->init.addr_mode)); - assert_param(IS_I2C_GENERAL_CALL(hperh->init.general_call)); - assert_param(IS_I2C_NO_STRETCH(hperh->init.no_stretch)); - - if (hperh->init.dual_addr == I2C_DUALADDR_ENABLE) - assert_param(IS_I2C_OWN_ADDRESS2(hperh->init.own_addr2)); - - if (hperh->state == I2C_STATE_RESET) - hperh->lock = UNLOCK; - - hperh->state = I2C_STATE_BUSY; - pclk1 = ald_cmu_get_pclk1_clock(); - I2C_DISABLE(hperh); - - freqrange = I2C_FREQ_RANGE(pclk1); - WRITE_REG(hperh->perh->CON2, freqrange); - WRITE_REG(hperh->perh->RT, I2C_RISE_TIME(freqrange, hperh->init.clk_speed)); - WRITE_REG(hperh->perh->CKCFG, i2c_configure_speed(hperh, pclk1)); - WRITE_REG(hperh->perh->CON1, hperh->init.general_call); - SET_BIT(hperh->perh->CON1, hperh->init.no_stretch); - - if (hperh->init.addr_mode == I2C_ADDR_7BIT) { - WRITE_REG(hperh->perh->ADDR1, (0x7FFF & hperh->init.own_addr1)); - } - else { - WRITE_REG(hperh->perh->ADDR1, (0x8000 | hperh->init.own_addr1)); - } - - WRITE_REG(hperh->perh->ADDR2, (hperh->init.dual_addr | hperh->init.own_addr2)); - - I2C_ENABLE(hperh); - - hperh->error_code = I2C_ERROR_NONE; - hperh->state = I2C_STATE_READY; - hperh->mode = I2C_MODE_NONE; - - return OK; -} - -/** - * @brief DeInitialize the I2C peripheral. - * @param hperh: Pointer to a i2c_handle_t structure that contains - * the configuration information for the specified I2C. - * @retval Status, see @ref ald_status_t. - */ -ald_status_t ald_i2c_reset(i2c_handle_t *hperh) -{ - if (hperh == NULL) - return ERROR; - - assert_param(IS_I2C_TYPE(hperh->perh)); - - hperh->state = I2C_STATE_BUSY; - I2C_DISABLE(hperh); - - hperh->error_code = I2C_ERROR_NONE; - hperh->state = I2C_STATE_RESET; - hperh->mode = I2C_MODE_NONE; - - __UNLOCK(hperh); - - return OK; -} -/** - * @} - */ - -/** @defgroup I2C_Public_Functions_Group2 Input and Output operation functions - * @brief Data transfers functions - * -@verbatim - =============================================================================== - ##### IO operation functions ##### - =============================================================================== - [..] - This subsection provides a set of functions allowing to manage the I2C data - transfers. - - (#) There are two modes of transfer: - (++) Blocking mode : The communication is performed in the polling mode. - The status of all data processing is returned by the same function - after finishing transfer. - (++) No-Blocking mode : The communication is performed using Interrupts - or DMA. These functions return the status of the transfer startup. - The end of the data processing will be indicated through the - dedicated I2C IRQ when using Interrupt mode or the DMA IRQ when - using DMA mode. - - (#) Blocking mode functions are : - (++) ald_i2c_master_send() - (++) ald_i2c_master_recv() - (++) ald_i2c_slave_send() - (++) ald_i2c_slave_recv() - (++) ald_i2c_mem_write() - (++) ald_i2c_mem_read() - (++) ald_i2c_is_device_ready() - - (#) No-Blocking mode functions with Interrupt are : - (++) ald_i2c_master_send_by_it() - (++) ald_i2c_master_recv_by_it() - (++) ald_i2c_slave_send_by_it() - (++) ald_i2c_slave_recv_by_it() - (++) ald_i2c_mem_write_by_it() - (++) ald_i2c_mem_read_by_it() - - (#) No-Blocking mode functions with DMA are : - (++) ald_i2c_master_send_by_dma() - (++) ald_i2c_master_recv_by_dma() - (++) ald_i2c_slave_send_by_dma() - (++) ald_i2c_slave_recv_by_dma() - (++) ald_i2c_mem_write_by_dma() - (++) ald_i2c_mem_read_by_dma() - - (#) A set of Transfer Complete Callbacks are provided in non Blocking mode: - (++) hperh->mem_tx_cplt_cbk() - (++) hperh->mem_rx_cplt_cbk() - (++) hperh->master_tx_cplt_cbk() - (++) hperh->master_rx_cplt_cbk() - (++) hperh->slave_tx_cplt_cbk() - (++) hperh->slave_rx_cplt_cbk() - (++) hperh->error_callback() - -@endverbatim - * @{ - */ - -/** - * @brief Transmits in master mode an amount of data in blocking mode. - * @param hperh: Pointer to a i2c_handle_t structure that contains - * the configuration information for the specified I2C. - * @param dev_addr: Target device address - * @param buf: Pointer to data buffer - * @param size: Amount of data to be sent - * @param timeout: Timeout duration - * @retval Status, see @ref ald_status_t. - */ -ald_status_t ald_i2c_master_send(i2c_handle_t *hperh, uint16_t dev_addr, uint8_t *buf, - uint16_t size, uint32_t timeout) -{ - if (hperh->state != I2C_STATE_READY) - return BUSY; - - if ((buf == NULL) || (size == 0)) - return ERROR; - - if (i2c_wait_flag_to_timeout(hperh, I2C_FLAG_BUSY, SET, I2C_TIMEOUT_BUSY_FLAG) != OK) - return BUSY; - - assert_param(IS_I2C_TYPE(hperh->perh)); - - __LOCK(hperh); - CLEAR_BIT(hperh->perh->CON1, I2C_CON1_POSAP); - - hperh->state = I2C_STATE_BUSY_TX; - hperh->mode = I2C_MODE_MASTER; - hperh->error_code = I2C_ERROR_NONE; - - if (i2c_master_req_write(hperh, dev_addr, timeout) != OK) { - if (hperh->error_code == I2C_ERROR_AF) { - __UNLOCK(hperh); - return ERROR; - } - else { - __UNLOCK(hperh); - return TIMEOUT; - } - } - - I2C_CLEAR_ADDRFLAG(hperh); - - while (size > 0) { - if (i2c_wait_txe_to_timeout(hperh, timeout) != OK) { - if (hperh->error_code == I2C_ERROR_AF) { - SET_BIT(hperh->perh->CON1, I2C_CON1_STOP); - __UNLOCK(hperh); - return ERROR; - } - else { - __UNLOCK(hperh); - return TIMEOUT; - } - } - - hperh->perh->DATA = (*buf++); - --size; - - if ((ald_i2c_get_flag_status(hperh, I2C_FLAG_BTF) == SET) && (size != 0)) { - hperh->perh->DATA = (*buf++); - --size; - } - } - - if (i2c_wait_btf_to_timeout(hperh, timeout) != OK) { - if (hperh->error_code == I2C_ERROR_AF) { - SET_BIT(hperh->perh->CON1, I2C_CON1_STOP); - __UNLOCK(hperh); - return ERROR; - } - else { - __UNLOCK(hperh); - return TIMEOUT; - } - } - - SET_BIT(hperh->perh->CON1, I2C_CON1_STOP); - hperh->state = I2C_STATE_READY; - __UNLOCK(hperh); - return OK; - -} - -/** - * @brief Receives in master mode an amount of data in blocking mode. - * @param hperh: Pointer to a i2c_handle_t structure that contains - * the configuration information for the specified I2C. - * @param dev_addr: Target device address - * @param buf: Pointer to data buffer - * @param size: Amount of data to be sent - * @param timeout: Timeout duration - * @retval Status, see @ref ald_status_t. - */ -ald_status_t ald_i2c_master_recv(i2c_handle_t *hperh, uint16_t dev_addr, uint8_t *buf, - uint16_t size, uint32_t timeout) -{ - if (hperh->state != I2C_STATE_READY) - return BUSY; - - if ((buf == NULL) || (size == 0)) - return ERROR; - - if (i2c_wait_flag_to_timeout(hperh, I2C_FLAG_BUSY, SET, I2C_TIMEOUT_BUSY_FLAG) != OK) - return BUSY; - - assert_param(IS_I2C_TYPE(hperh->perh)); - __LOCK(hperh); - - CLEAR_BIT(hperh->perh->CON1, I2C_CON1_POSAP); - - hperh->state = I2C_STATE_BUSY_RX; - hperh->mode = I2C_MODE_MASTER; - hperh->error_code = I2C_ERROR_NONE; - - if (i2c_master_req_read(hperh, dev_addr, timeout) != OK) { - if (hperh->error_code == I2C_ERROR_AF) { - __UNLOCK(hperh); - return ERROR; - } - else { - __UNLOCK(hperh); - return TIMEOUT; - } - } - - if (size == 1) { - CLEAR_BIT(hperh->perh->CON1, I2C_CON1_ACKEN); - __disable_irq(); - I2C_CLEAR_ADDRFLAG(hperh); - SET_BIT(hperh->perh->CON1, I2C_CON1_STOP); - __enable_irq(); - } - else if (size == 2) { - SET_BIT(hperh->perh->CON1, I2C_CON1_POSAP); - __disable_irq(); - I2C_CLEAR_ADDRFLAG(hperh); - CLEAR_BIT(hperh->perh->CON1, I2C_CON1_ACKEN); - __enable_irq(); - } - else { - SET_BIT(hperh->perh->CON1, I2C_CON1_ACKEN); - I2C_CLEAR_ADDRFLAG(hperh); - } - - while (size > 3) { - if (i2c_wait_rxne_to_timeout(hperh, timeout) != OK) { - if (hperh->error_code == I2C_ERROR_TIMEOUT) { - __UNLOCK(hperh); - return TIMEOUT; - } - else { - __UNLOCK(hperh); - return ERROR; - } - } - - (*buf++) = hperh->perh->DATA; - --size; - - if (ald_i2c_get_flag_status(hperh, I2C_FLAG_BTF) == SET) { - (*buf++) = hperh->perh->DATA; - --size; - } - } - - switch (size) { - case 1: - if (i2c_wait_rxne_to_timeout(hperh, timeout) != OK) { - if (hperh->error_code == I2C_ERROR_TIMEOUT) { - __UNLOCK(hperh); - return TIMEOUT; - } - else { - __UNLOCK(hperh); - return ERROR; - } - } - - (*buf++) = hperh->perh->DATA; - break; - - case 2: - if (i2c_wait_flag_to_timeout(hperh, I2C_FLAG_BTF, RESET, timeout) != OK) { - __UNLOCK(hperh); - return TIMEOUT; - } - - __disable_irq(); - SET_BIT(hperh->perh->CON1, I2C_CON1_STOP); - (*buf++) = hperh->perh->DATA; - __enable_irq(); - (*buf++) = hperh->perh->DATA; - break; - - case 3: - if (i2c_wait_flag_to_timeout(hperh, I2C_FLAG_BTF, RESET, timeout) != OK) { - __UNLOCK(hperh); - return TIMEOUT; - } - - CLEAR_BIT(hperh->perh->CON1, I2C_CON1_ACKEN); - __disable_irq(); - (*buf++) = hperh->perh->DATA; - - if (i2c_wait_flag_to_timeout(hperh, I2C_FLAG_BTF, RESET, timeout) != OK) { - __UNLOCK(hperh); - __enable_irq(); - return TIMEOUT; - } - - SET_BIT(hperh->perh->CON1, I2C_CON1_STOP); - (*buf++) = hperh->perh->DATA; - __enable_irq(); - (*buf++) = hperh->perh->DATA; - break; - - default : - break; - } - - hperh->state = I2C_STATE_READY; - hperh->mode = I2C_MODE_NONE; - __UNLOCK(hperh); - return OK; -} - -/** - * @brief Transmits in slave mode an amount of data in blocking mode. - * @param hperh: Pointer to a i2c_handle_t structure that contains - * the configuration information for the specified I2C. - * @param buf: Pointer to data buffer - * @param size: Amount of data to be sent - * @param timeout: Timeout duration - * @retval Status, see @ref ald_status_t. - */ -ald_status_t ald_i2c_slave_send(i2c_handle_t *hperh, uint8_t *buf, uint16_t size, uint32_t timeout) -{ - if (hperh->state != I2C_STATE_READY) - return BUSY; - - if ((buf == NULL) || (size == 0)) - return ERROR; - - if (i2c_wait_flag_to_timeout(hperh, I2C_FLAG_BUSY, SET, I2C_TIMEOUT_BUSY_FLAG) != OK) - return BUSY; - - assert_param(IS_I2C_TYPE(hperh->perh)); - - __LOCK(hperh); - CLEAR_BIT(hperh->perh->CON1, I2C_CON1_POSAP); - - hperh->state = I2C_STATE_BUSY_TX; - hperh->mode = I2C_MODE_SLAVE; - hperh->error_code = I2C_ERROR_NONE; - SET_BIT(hperh->perh->CON1, I2C_CON1_ACKEN); - - if (i2c_wait_flag_to_timeout(hperh, I2C_FLAG_ADDR, RESET, timeout) != OK) { - __UNLOCK(hperh); - return TIMEOUT; - } - - I2C_CLEAR_ADDRFLAG(hperh); - - if (hperh->init.addr_mode == I2C_ADDR_10BIT) { - if (i2c_wait_flag_to_timeout(hperh, I2C_FLAG_ADDR, RESET, timeout) != OK) { - __UNLOCK(hperh); - return TIMEOUT; - } - - I2C_CLEAR_ADDRFLAG(hperh); - } - - while (size > 0) { - if (i2c_wait_txe_to_timeout(hperh, timeout) != OK) { - CLEAR_BIT(hperh->perh->CON1, I2C_CON1_ACKEN); - - if (hperh->error_code == I2C_ERROR_AF) { - __UNLOCK(hperh); - return ERROR; - } - else { - __UNLOCK(hperh); - return TIMEOUT; - } - } - - hperh->perh->DATA = (*buf++); - --size; - - if ((ald_i2c_get_flag_status(hperh, I2C_FLAG_BTF) == SET) && (size != 0)) { - hperh->perh->DATA = (*buf++); - --size; - } - } - - if (i2c_wait_flag_to_timeout(hperh, I2C_FLAG_AF, RESET, timeout) != OK) { - __UNLOCK(hperh); - return TIMEOUT; - } - - ald_i2c_clear_flag_status(hperh, I2C_FLAG_AF); - - CLEAR_BIT(hperh->perh->CON1, I2C_CON1_ACKEN); - hperh->state = I2C_STATE_READY; - hperh->mode = I2C_MODE_NONE; - __UNLOCK(hperh); - return OK; -} - -/** - * @brief Receive in slave mode an amount of data in blocking mode - * @param hperh: Pointer to a i2c_handle_t structure that contains - * the configuration information for the specified I2C. - * @param buf: Pointer to data buffer - * @param size: Amount of data to be sent - * @param timeout: Timeout duration - * @retval Status, see @ref ald_status_t. - */ -ald_status_t ald_i2c_slave_recv(i2c_handle_t *hperh, uint8_t *buf, uint16_t size, uint32_t timeout) -{ - if (hperh->state != I2C_STATE_READY) - return BUSY; - - if ((buf == NULL) || (size == 0)) - return ERROR; - - if (i2c_wait_flag_to_timeout(hperh, I2C_FLAG_BUSY, SET, I2C_TIMEOUT_BUSY_FLAG) != OK) - return BUSY; - - assert_param(IS_I2C_TYPE(hperh->perh)); - - __LOCK(hperh); - CLEAR_BIT(hperh->perh->CON1, I2C_CON1_POSAP); - - hperh->state = I2C_STATE_BUSY_RX; - hperh->mode = I2C_MODE_SLAVE; - hperh->error_code = I2C_ERROR_NONE; - SET_BIT(hperh->perh->CON1, I2C_CON1_ACKEN); - - if (i2c_wait_flag_to_timeout(hperh, I2C_FLAG_ADDR, RESET, timeout) != OK) { - __UNLOCK(hperh); - return TIMEOUT; - } - - I2C_CLEAR_ADDRFLAG(hperh); - - while (size > 0) { - if (i2c_wait_rxne_to_timeout(hperh, timeout) != OK) { - hperh->perh->CON1 &= (uint32_t)(~I2C_CON1_ACKEN); - - if (hperh->error_code == I2C_ERROR_TIMEOUT) { - __UNLOCK(hperh); - return TIMEOUT; - } - else { - __UNLOCK(hperh); - return ERROR; - } - } - - (*buf++) = hperh->perh->DATA; - --size; - - if ((ald_i2c_get_flag_status(hperh, I2C_FLAG_BTF) == SET) && (size != 0)) { - (*buf++) = hperh->perh->DATA; - --size; - } - } - - if (i2c_wait_stop_to_timeout(hperh, I2C_TIMEOUT_FLAG) != OK) { - CLEAR_BIT(hperh->perh->CON1, I2C_CON1_ACKEN); - if (hperh->error_code == I2C_ERROR_AF) { - __UNLOCK(hperh); - return ERROR; - } - else { - __UNLOCK(hperh); - return TIMEOUT; - } - } - - __I2C_CLEAR_STOPFLAG(hperh); - CLEAR_BIT(hperh->perh->CON1, I2C_CON1_ACKEN); - hperh->state = I2C_STATE_READY; - hperh->mode = I2C_MODE_NONE; - __UNLOCK(hperh); - return OK; -} - -/** - * @brief Transmit in master mode an amount of data in non-blocking mode with Interrupt - * @param hperh: Pointer to a i2c_handle_t structure that contains - * the configuration information for the specified I2C. - * @param dev_addr: Target device address - * @param buf: Pointer to data buffer - * @param size: Amount of data to be sent - * @retval Status, see @ref ald_status_t. - */ -ald_status_t ald_i2c_master_send_by_it(i2c_handle_t *hperh, uint16_t dev_addr, uint8_t *buf, uint16_t size) -{ - if (hperh->state != I2C_STATE_READY) - return BUSY; - - if ((buf == NULL) || (size == 0)) - return ERROR; - - if (i2c_wait_flag_to_timeout(hperh, I2C_FLAG_BUSY, SET, I2C_TIMEOUT_BUSY_FLAG) != OK) - return BUSY; - - assert_param(IS_I2C_TYPE(hperh->perh)); - - __LOCK(hperh); - CLEAR_BIT(hperh->perh->CON1, I2C_CON1_POSAP); - - hperh->state = I2C_STATE_BUSY_TX; - hperh->mode = I2C_MODE_MASTER; - hperh->error_code = I2C_ERROR_NONE; - hperh->p_buff = buf; - hperh->xfer_size = size; - hperh->xfer_count = size; - - if (i2c_master_req_write(hperh, dev_addr, I2C_TIMEOUT_FLAG) != OK) { - if (hperh->error_code == I2C_ERROR_AF) { - __UNLOCK(hperh); - return ERROR; - } - else { - __UNLOCK(hperh); - return TIMEOUT; - } - } - - I2C_CLEAR_ADDRFLAG(hperh); - - __UNLOCK(hperh); - - /* Note : The I2C interrupts must be enabled after unlocking current process - * to avoid the risk of I2C interrupt handle execution before current - * process unlock */ - ald_i2c_interrupt_config(hperh, I2C_IT_EVT, ENABLE); - ald_i2c_interrupt_config(hperh, I2C_IT_BUF, ENABLE); - ald_i2c_interrupt_config(hperh, I2C_IT_ERR, ENABLE); - return OK; -} - -/** - * @brief Receive in master mode an amount of data in non-blocking mode with Interrupt - * @param hperh: Pointer to a i2c_handle_t structure that contains - * the configuration information for the specified I2C. - * @param dev_addr: Target device address - * @param buf: Pointer to data buffer - * @param size: Amount of data to be sent - * @retval Status, see @ref ald_status_t. - */ -ald_status_t ald_i2c_master_recv_by_it(i2c_handle_t *hperh, uint16_t dev_addr, uint8_t *buf, uint16_t size) -{ - if (hperh->state != I2C_STATE_READY) - return BUSY; - - if ((buf == NULL) || (size == 0)) - return ERROR; - - if (i2c_wait_flag_to_timeout(hperh, I2C_FLAG_BUSY, SET, I2C_TIMEOUT_BUSY_FLAG) != OK) - return BUSY; - - assert_param(IS_I2C_TYPE(hperh->perh)); - - __LOCK(hperh); - CLEAR_BIT(hperh->perh->CON1, I2C_CON1_POSAP); - - hperh->state = I2C_STATE_BUSY_RX; - hperh->mode = I2C_MODE_MASTER; - hperh->error_code = I2C_ERROR_NONE; - hperh->p_buff = buf; - hperh->xfer_size = size; - hperh->xfer_count = size; - - if (i2c_master_req_read(hperh, dev_addr, I2C_TIMEOUT_FLAG) != OK) { - if (hperh->error_code == I2C_ERROR_AF) { - __UNLOCK(hperh); - return ERROR; - } - else { - __UNLOCK(hperh); - return TIMEOUT; - } - } - - if (hperh->xfer_count == 1) { - CLEAR_BIT(hperh->perh->CON1, I2C_CON1_ACKEN); - I2C_CLEAR_ADDRFLAG(hperh); - SET_BIT(hperh->perh->CON1, I2C_CON1_STOP); - } - else if (hperh->xfer_count == 2) { - SET_BIT(hperh->perh->CON1, I2C_CON1_POSAP); - I2C_CLEAR_ADDRFLAG(hperh); - CLEAR_BIT(hperh->perh->CON1, I2C_CON1_ACKEN); - } - else { - SET_BIT(hperh->perh->CON1, I2C_CON1_ACKEN); - I2C_CLEAR_ADDRFLAG(hperh); - } - - __UNLOCK(hperh); - - /* Note : The I2C interrupts must be enabled after unlocking current process - * to avoid the risk of I2C interrupt handle execution before current - * process unlock */ - ald_i2c_interrupt_config(hperh, I2C_IT_EVT, ENABLE); - ald_i2c_interrupt_config(hperh, I2C_IT_BUF, ENABLE); - ald_i2c_interrupt_config(hperh, I2C_IT_ERR, ENABLE); - return OK; -} - -/** - * @brief Transmit in slave mode an amount of data in non-blocking mode with Interrupt - * @param hperh: Pointer to a i2c_handle_t structure that contains - * the configuration information for the specified I2C. - * @param buf: Pointer to data buffer - * @param size: Amount of data to be sent - * @retval Status, see @ref ald_status_t. - */ -ald_status_t ald_i2c_slave_send_by_it(i2c_handle_t *hperh, uint8_t *buf, uint16_t size) -{ - if (hperh->state != I2C_STATE_READY) - return BUSY; - - if ((buf == NULL) || (size == 0)) - return ERROR; - - if (i2c_wait_flag_to_timeout(hperh, I2C_FLAG_BUSY, SET, I2C_TIMEOUT_BUSY_FLAG) != OK) - return BUSY; - - assert_param(IS_I2C_TYPE(hperh->perh)); - - __LOCK(hperh); - CLEAR_BIT(hperh->perh->CON1, I2C_CON1_POSAP); - - hperh->state = I2C_STATE_BUSY_TX; - hperh->mode = I2C_MODE_SLAVE; - hperh->error_code = I2C_ERROR_NONE; - hperh->p_buff = buf; - hperh->xfer_size = size; - hperh->xfer_count = size; - SET_BIT(hperh->perh->CON1, I2C_CON1_ACKEN); - __UNLOCK(hperh); - - /* Note : The I2C interrupts must be enabled after unlocking current process - * to avoid the risk of I2C interrupt handle execution before current - * process unlock */ - ald_i2c_interrupt_config(hperh, I2C_IT_EVT, ENABLE); - ald_i2c_interrupt_config(hperh, I2C_IT_BUF, ENABLE); - ald_i2c_interrupt_config(hperh, I2C_IT_ERR, ENABLE); - - return OK; -} - -/** - * @brief Receive in slave mode an amount of data in non-blocking mode with Interrupt - * @param hperh: Pointer to a i2c_handle_t structure that contains - * the configuration information for the specified I2C. - * @param buf: Pointer to data buffer - * @param size: Amount of data to be sent - * @retval Status, see @ref ald_status_t. - */ -ald_status_t ald_i2c_slave_recv_by_it(i2c_handle_t *hperh, uint8_t *buf, uint16_t size) -{ - if (hperh->state != I2C_STATE_READY) - return BUSY; - - if ((buf == NULL) || (size == 0)) - return ERROR; - - if (i2c_wait_flag_to_timeout(hperh, I2C_FLAG_BUSY, SET, I2C_TIMEOUT_BUSY_FLAG) != OK) - return BUSY; - - assert_param(IS_I2C_TYPE(hperh->perh)); - - __LOCK(hperh); - CLEAR_BIT(hperh->perh->CON1, I2C_CON1_POSAP); - - hperh->state = I2C_STATE_BUSY_RX; - hperh->mode = I2C_MODE_SLAVE; - hperh->error_code = I2C_ERROR_NONE; - hperh->p_buff = buf; - hperh->xfer_size = size; - hperh->xfer_count = size; - SET_BIT(hperh->perh->CON1, I2C_CON1_ACKEN); - __UNLOCK(hperh); - - /* Note : The I2C interrupts must be enabled after unlocking current process - * to avoid the risk of I2C interrupt handle execution before current - * process unlock */ - ald_i2c_interrupt_config(hperh, I2C_IT_EVT, ENABLE); - ald_i2c_interrupt_config(hperh, I2C_IT_BUF, ENABLE); - ald_i2c_interrupt_config(hperh, I2C_IT_ERR, ENABLE); - - return OK; -} - -#ifdef ALD_DMA -/** - * @brief Transmit in master mode an amount of data in non-blocking mode with DMA - * @param hperh: Pointer to a i2c_handle_t structure that contains - * the configuration information for the specified I2C. - * @param dev_addr: Target device address - * @param buf: Pointer to data buffer - * @param size: Amount of data to be sent - * @param channel: DMA channel as I2C transmit - * @retval Status, see @ref ald_status_t. - */ -ald_status_t ald_i2c_master_send_by_dma(i2c_handle_t *hperh, uint16_t dev_addr, uint8_t *buf, - uint16_t size, uint8_t channel) -{ - if (hperh->state != I2C_STATE_READY) - return BUSY; - - if ((buf == NULL) || (size == 0)) - return ERROR; - - if (i2c_wait_flag_to_timeout(hperh, I2C_FLAG_BUSY, SET, I2C_TIMEOUT_BUSY_FLAG) != OK) - return BUSY; - - assert_param(IS_I2C_TYPE(hperh->perh)); - - __LOCK(hperh); - CLEAR_BIT(hperh->perh->CON1, I2C_CON1_POSAP); - - hperh->state = I2C_STATE_BUSY_TX; - hperh->mode = I2C_MODE_MASTER; - hperh->error_code = I2C_ERROR_NONE; - hperh->p_buff = buf; - hperh->xfer_size = size; - hperh->xfer_count = size; - - if (hperh->hdmatx.perh == NULL) - hperh->hdmatx.perh = DMA0; - - hperh->hdmatx.cplt_cbk = i2c_dma_master_send_cplt; - hperh->hdmatx.cplt_arg = hperh; - hperh->hdmatx.err_cbk = i2c_dma_error; - hperh->hdmatx.err_arg = hperh; - - ald_dma_config_struct(&hperh->hdmatx.config); - hperh->hdmatx.config.src = (void *)buf; - hperh->hdmatx.config.dst = (void *)&hperh->perh->DATA; - hperh->hdmatx.config.size = size; - hperh->hdmatx.config.data_width = DMA_DATA_SIZE_BYTE; - hperh->hdmatx.config.src_inc = DMA_DATA_INC_BYTE; - hperh->hdmatx.config.dst_inc = DMA_DATA_INC_NONE; - hperh->hdmatx.config.msel = hperh->perh == I2C0 ? DMA_MSEL_I2C0 : DMA_MSEL_I2C1; - hperh->hdmatx.config.msigsel = DMA_MSIGSEL_I2C_TXEMPTY; - hperh->hdmatx.config.channel = channel; - ald_dma_config_basic(&hperh->hdmatx); - - if (i2c_master_req_write(hperh, dev_addr, I2C_TIMEOUT_FLAG) != OK) { - if (hperh->error_code == I2C_ERROR_AF) { - __UNLOCK(hperh); - return ERROR; - } - else { - __UNLOCK(hperh); - return TIMEOUT; - } - } - - SET_BIT(hperh->perh->CON2, I2C_CON2_DMAEN); - I2C_CLEAR_ADDRFLAG(hperh); - __UNLOCK(hperh); - return OK; -} - -/** - * @brief Receive in master mode an amount of data in non-blocking mode with DMA - * @param hperh: Pointer to a i2c_handle_t structure that contains - * the configuration information for the specified I2C. - * @param dev_addr: Target device address - * @param buf: Pointer to data buffer - * @param size: Amount of data to be sent - * @param channel: DMA channel as I2C receive - * @retval Status, see @ref ald_status_t. - */ -ald_status_t ald_i2c_master_recv_by_dma(i2c_handle_t *hperh, uint16_t dev_addr, uint8_t *buf, - uint16_t size, uint8_t channel) -{ - if (hperh->state != I2C_STATE_READY) - return BUSY; - - if ((buf == NULL) || (size == 0)) - return ERROR; - - if (i2c_wait_flag_to_timeout(hperh, I2C_FLAG_BUSY, SET, I2C_TIMEOUT_BUSY_FLAG) != OK) - return BUSY; - - assert_param(IS_I2C_TYPE(hperh->perh)); - - __LOCK(hperh); - CLEAR_BIT(hperh->perh->CON1, I2C_CON1_POSAP); - - hperh->state = I2C_STATE_BUSY_RX; - hperh->mode = I2C_MODE_MASTER; - hperh->error_code = I2C_ERROR_NONE; - hperh->p_buff = buf; - hperh->xfer_size = size; - hperh->xfer_count = size; - - if (hperh->hdmarx.perh == NULL) - hperh->hdmarx.perh = DMA0; - - hperh->hdmarx.cplt_cbk = i2c_dma_master_recv_cplt; - hperh->hdmarx.cplt_arg = (void *)hperh; - hperh->hdmarx.err_cbk = i2c_dma_error; - hperh->hdmarx.err_arg = (void *)hperh; - - ald_dma_config_struct(&hperh->hdmarx.config); - hperh->hdmarx.config.src = (void *)&hperh->perh->DATA; - hperh->hdmarx.config.dst = (void *)buf; - hperh->hdmarx.config.size = size; - hperh->hdmarx.config.data_width = DMA_DATA_SIZE_BYTE; - hperh->hdmarx.config.src_inc = DMA_DATA_INC_NONE; - hperh->hdmarx.config.dst_inc = DMA_DATA_INC_BYTE; - hperh->hdmarx.config.msel = hperh->perh == I2C0 ? DMA_MSEL_I2C0 : DMA_MSEL_I2C1; - hperh->hdmarx.config.msigsel = DMA_MSIGSEL_I2C_RNR; - hperh->hdmarx.config.channel = channel; - ald_dma_config_basic(&hperh->hdmarx); - - if (i2c_master_req_read(hperh, dev_addr, I2C_TIMEOUT_FLAG) != OK) { - if (hperh->error_code == I2C_ERROR_AF) { - __UNLOCK(hperh); - return ERROR; - } - else { - __UNLOCK(hperh); - return TIMEOUT; - } - } - - if (size == 1) - CLEAR_BIT(hperh->perh->CON1, I2C_CON1_ACKEN); - else - SET_BIT(hperh->perh->CON2, I2C_CON2_LDMA); - - SET_BIT(hperh->perh->CON2, I2C_CON2_DMAEN); - I2C_CLEAR_ADDRFLAG(hperh); - __UNLOCK(hperh); - return OK; -} - -/** - * @brief Transmit in slave mode an amount of data in non-blocking mode with DMA - * @param hperh: Pointer to a i2c_handle_t structure that contains - * the configuration information for the specified I2C. - * @param buf: Pointer to data buffer - * @param size: Amount of data to be sent - * @param channel: DMA channel as I2C Transmit - * @retval Status, see @ref ald_status_t. - */ -ald_status_t ald_i2c_slave_send_by_dma(i2c_handle_t *hperh, uint8_t *buf, uint16_t size, uint8_t channel) -{ - if (hperh->state != I2C_STATE_READY) - return BUSY; - - if ((buf == NULL) || (size == 0)) - return ERROR; - - if (i2c_wait_flag_to_timeout(hperh, I2C_FLAG_BUSY, SET, I2C_TIMEOUT_BUSY_FLAG) != OK) - return BUSY; - - assert_param(IS_I2C_TYPE(hperh->perh)); - - __LOCK(hperh); - CLEAR_BIT(hperh->perh->CON1, I2C_CON1_POSAP); - - hperh->state = I2C_STATE_BUSY_TX; - hperh->mode = I2C_MODE_SLAVE; - hperh->error_code = I2C_ERROR_NONE; - hperh->p_buff = buf; - hperh->xfer_size = size; - hperh->xfer_count = size; - - if (hperh->hdmatx.perh == NULL) - hperh->hdmatx.perh = DMA0; - - hperh->hdmatx.cplt_cbk = i2c_dma_slave_send_cplt; - hperh->hdmatx.cplt_arg = hperh; - hperh->hdmatx.err_cbk = i2c_dma_error; - hperh->hdmatx.err_arg = hperh; - - ald_dma_config_struct(&hperh->hdmatx.config); - hperh->hdmatx.config.src = (void *)buf; - hperh->hdmatx.config.dst = (void *)&hperh->perh->DATA; - hperh->hdmatx.config.size = size; - hperh->hdmatx.config.data_width = DMA_DATA_SIZE_BYTE; - hperh->hdmatx.config.src_inc = DMA_DATA_INC_BYTE; - hperh->hdmatx.config.dst_inc = DMA_DATA_INC_NONE; - hperh->hdmatx.config.msel = hperh->perh == I2C0 ? DMA_MSEL_I2C0 : DMA_MSEL_I2C1; - hperh->hdmatx.config.msigsel = DMA_MSIGSEL_I2C_TXEMPTY; - hperh->hdmatx.config.channel = channel; - ald_dma_config_basic(&hperh->hdmatx); - - SET_BIT(hperh->perh->CON2, I2C_CON2_DMAEN); - SET_BIT(hperh->perh->CON1, I2C_CON1_ACKEN); - - if (i2c_wait_flag_to_timeout(hperh, I2C_FLAG_ADDR, RESET, I2C_TIMEOUT_ADDR_SLAVE) != OK) { - __UNLOCK(hperh); - return TIMEOUT; - } - - if (hperh->init.addr_mode == I2C_ADDR_7BIT) { - I2C_CLEAR_ADDRFLAG(hperh); - } - else { - I2C_CLEAR_ADDRFLAG(hperh); - - if (i2c_wait_flag_to_timeout(hperh, I2C_FLAG_ADDR, RESET, I2C_TIMEOUT_ADDR_SLAVE) != OK) { - __UNLOCK(hperh); - return TIMEOUT; - } - - I2C_CLEAR_ADDRFLAG(hperh); - } - - __UNLOCK(hperh); - - return OK; -} - -/** - * @brief Receive in slave mode an amount of data in non-blocking mode with DMA - * @param hperh: Pointer to a i2c_handle_t structure that contains - * the configuration information for the specified I2C. - * @param buf: Pointer to data buffer - * @param size: Amount of data to be sent - * @param channel: DMA channel as I2C receive - * @retval Status, see @ref ald_status_t. - */ -ald_status_t ald_i2c_slave_recv_by_dma(i2c_handle_t *hperh, uint8_t *buf, uint16_t size, uint8_t channel) -{ - if (hperh->state != I2C_STATE_READY) - return BUSY; - - if ((buf == NULL) || (size == 0)) - return ERROR; - - if (i2c_wait_flag_to_timeout(hperh, I2C_FLAG_BUSY, SET, I2C_TIMEOUT_BUSY_FLAG) != OK) - return BUSY; - - assert_param(IS_I2C_TYPE(hperh->perh)); - - __LOCK(hperh); - CLEAR_BIT(hperh->perh->CON1, I2C_CON1_POSAP); - - hperh->state = I2C_STATE_BUSY_RX; - hperh->mode = I2C_MODE_SLAVE; - hperh->error_code = I2C_ERROR_NONE; - hperh->p_buff = buf; - hperh->xfer_size = size; - hperh->xfer_count = size; - - if (hperh->hdmarx.perh == NULL) - hperh->hdmarx.perh = DMA0; - - hperh->hdmarx.cplt_cbk = i2c_dma_slave_recv_cplt; - hperh->hdmarx.cplt_arg = (void *)hperh; - hperh->hdmarx.err_cbk = i2c_dma_error; - hperh->hdmarx.err_arg = (void *)hperh; - - ald_dma_config_struct(&hperh->hdmarx.config); - hperh->hdmarx.config.src = (void *)&hperh->perh->DATA; - hperh->hdmarx.config.dst = (void *)buf; - hperh->hdmarx.config.size = size; - hperh->hdmarx.config.data_width = DMA_DATA_SIZE_BYTE; - hperh->hdmarx.config.src_inc = DMA_DATA_INC_NONE; - hperh->hdmarx.config.dst_inc = DMA_DATA_INC_BYTE; - hperh->hdmarx.config.msel = hperh->perh == I2C0 ? DMA_MSEL_I2C0 : DMA_MSEL_I2C1; - hperh->hdmarx.config.msigsel = DMA_MSIGSEL_I2C_RNR; - hperh->hdmarx.config.channel = channel; - ald_dma_config_basic(&hperh->hdmarx); - - SET_BIT(hperh->perh->CON2, I2C_CON2_DMAEN); - SET_BIT(hperh->perh->CON1, I2C_CON1_ACKEN); - - if (i2c_wait_flag_to_timeout(hperh, I2C_FLAG_ADDR, RESET, I2C_TIMEOUT_ADDR_SLAVE) != OK) { - __UNLOCK(hperh); - return TIMEOUT; - } - - I2C_CLEAR_ADDRFLAG(hperh); - __UNLOCK(hperh); - return OK; -} -#endif - -/** - * @brief Write an amount of data in blocking mode to a specific memory address - * @param hperh: Pointer to a i2c_handle_t structure that contains - * the configuration information for the specified I2C. - * @param dev_addr: Target device address - * @param mem_addr: Internal memory address - * @param add_size: size of internal memory address - * @param buf: Pointer to data buffer - * @param size: Amount of data to be sent - * @param timeout: Timeout duration - * @retval Status, see @ref ald_status_t. - */ -ald_status_t ald_i2c_mem_write(i2c_handle_t *hperh, uint16_t dev_addr, uint16_t mem_addr, - i2c_addr_size_t add_size, uint8_t *buf, uint16_t size, uint32_t timeout) -{ - if (hperh->state != I2C_STATE_READY) - return BUSY; - - if ((buf == NULL) || (size == 0)) - return ERROR; - - if (i2c_wait_flag_to_timeout(hperh, I2C_FLAG_BUSY, SET, I2C_TIMEOUT_BUSY_FLAG) != OK) - return BUSY; - - assert_param(IS_I2C_TYPE(hperh->perh)); - assert_param(IS_I2C_MEMADD_size(add_size)); - - __LOCK(hperh); - CLEAR_BIT(hperh->perh->CON1, I2C_CON1_POSAP); - - hperh->state = I2C_STATE_BUSY_TX; - hperh->mode = I2C_MODE_MEM; - hperh->error_code = I2C_ERROR_NONE; - - if (i2c_req_mem_write(hperh, dev_addr, mem_addr, add_size, timeout) != OK) { - if (hperh->error_code == I2C_ERROR_AF) { - __UNLOCK(hperh); - return ERROR; - } - else { - __UNLOCK(hperh); - return TIMEOUT; - } - } - - while (size > 0) { - if (i2c_wait_txe_to_timeout(hperh, timeout) != OK) { - if (hperh->error_code == I2C_ERROR_AF) { - SET_BIT(hperh->perh->CON1, I2C_CON1_STOP); - __UNLOCK(hperh); - return ERROR; - } - else { - __UNLOCK(hperh); - return TIMEOUT; - } - } - - hperh->perh->DATA = (*buf++); - --size; - - if ((ald_i2c_get_flag_status(hperh, I2C_FLAG_BTF) == SET) && (size != 0)) { - hperh->perh->DATA = (*buf++); - --size; - } - } - - if (i2c_wait_txe_to_timeout(hperh, timeout) != OK) { - if (hperh->error_code == I2C_ERROR_AF) { - SET_BIT(hperh->perh->CON1, I2C_CON1_STOP); - __UNLOCK(hperh); - return ERROR; - } - else { - __UNLOCK(hperh); - return TIMEOUT; - } - } - - SET_BIT(hperh->perh->CON1, I2C_CON1_STOP); - hperh->state = I2C_STATE_READY; - hperh->mode = I2C_MODE_NONE; - ald_delay_ms(10); - __UNLOCK(hperh); - return OK; -} - -/** - * @brief Read an amount of data in blocking mode from a specific memory address - * @param hperh: Pointer to a i2c_handle_t structure that contains - * the configuration information for the specified I2C. - * @param dev_addr: Target device address - * @param mem_addr: Internal memory address - * @param add_size: size of internal memory address - * @param buf: Pointer to data buffer - * @param size: Amount of data to be sent - * @param timeout: Timeout duration - * @retval Status, see @ref ald_status_t. - */ -ald_status_t ald_i2c_mem_read(i2c_handle_t *hperh, uint16_t dev_addr, uint16_t mem_addr, i2c_addr_size_t add_size, - uint8_t *buf, uint16_t size, uint32_t timeout) -{ - if (hperh->state != I2C_STATE_READY) - return BUSY; - - if ((buf == NULL) || (size == 0)) - return ERROR; - - if (i2c_wait_flag_to_timeout(hperh, I2C_FLAG_BUSY, SET, I2C_TIMEOUT_BUSY_FLAG) != OK) - return BUSY; - - assert_param(IS_I2C_TYPE(hperh->perh)); - assert_param(IS_I2C_MEMADD_size(add_size)); - - __LOCK(hperh); - CLEAR_BIT(hperh->perh->CON1, I2C_CON1_POSAP); - - hperh->state = I2C_STATE_BUSY_RX; - hperh->mode = I2C_MODE_MEM; - hperh->error_code = I2C_ERROR_NONE; - - if (i2c_req_mem_read(hperh, dev_addr, mem_addr, add_size, timeout) != OK) { - if (hperh->error_code == I2C_ERROR_AF) { - __UNLOCK(hperh); - return ERROR; - } - else { - __UNLOCK(hperh); - return TIMEOUT; - } - } - - if (size == 1) { - CLEAR_BIT(hperh->perh->CON1, I2C_CON1_ACKEN); - __disable_irq(); - I2C_CLEAR_ADDRFLAG(hperh); - SET_BIT(hperh->perh->CON1, I2C_CON1_STOP); - __enable_irq(); - } - else if (size == 2) { - SET_BIT(hperh->perh->CON1, I2C_CON1_POSAP); - __disable_irq(); - I2C_CLEAR_ADDRFLAG(hperh); - CLEAR_BIT(hperh->perh->CON1, I2C_CON1_ACKEN); - __enable_irq(); - } - else { - SET_BIT(hperh->perh->CON1, I2C_CON1_ACKEN); - I2C_CLEAR_ADDRFLAG(hperh); - } - - while (size > 3) { - if (i2c_wait_rxne_to_timeout(hperh, timeout) != OK) { - if (hperh->error_code == I2C_ERROR_TIMEOUT) { - __UNLOCK(hperh); - return TIMEOUT; - } - else { - __UNLOCK(hperh); - return ERROR; - } - } - - (*buf++) = hperh->perh->DATA; - --size; - - if (ald_i2c_get_flag_status(hperh, I2C_FLAG_BTF) == SET) { - (*buf++) = hperh->perh->DATA; - --size; - } - } - - switch (size) { - case 1: - if (i2c_wait_rxne_to_timeout(hperh, timeout) != OK) { - if (hperh->error_code == I2C_ERROR_TIMEOUT) { - __UNLOCK(hperh); - return TIMEOUT; - } - else { - __UNLOCK(hperh); - return ERROR; - } - } - - (*buf++) = hperh->perh->DATA; - break; - - case 2: - if (i2c_wait_flag_to_timeout(hperh, I2C_FLAG_BTF, RESET, timeout) != OK) { - __UNLOCK(hperh); - return TIMEOUT; - } - - __disable_irq(); - SET_BIT(hperh->perh->CON1, I2C_CON1_STOP); - (*buf++) = hperh->perh->DATA; - __enable_irq(); - (*buf++) = hperh->perh->DATA; - break; - - case 3: - if (i2c_wait_flag_to_timeout(hperh, I2C_FLAG_BTF, RESET, timeout) != OK) { - __UNLOCK(hperh); - return TIMEOUT; - } - - CLEAR_BIT(hperh->perh->CON1, I2C_CON1_ACKEN); - __disable_irq(); - (*buf++) = hperh->perh->DATA; - - if (i2c_wait_flag_to_timeout(hperh, I2C_FLAG_BTF, RESET, timeout) != OK) { - __UNLOCK(hperh); - __enable_irq(); - return TIMEOUT; - } - - SET_BIT(hperh->perh->CON1, I2C_CON1_STOP); - (*buf++) = hperh->perh->DATA; - __enable_irq(); - (*buf++) = hperh->perh->DATA; - break; - - default: - break; - } - - hperh->state = I2C_STATE_READY; - hperh->mode = I2C_MODE_NONE; - __UNLOCK(hperh); - return OK; -} - -/** - * @brief Write an amount of data in non-blocking mode with Interrupt to a specific memory address - * @param hperh: Pointer to a i2c_handle_t structure that contains - * the configuration information for the specified I2C. - * @param dev_addr: Target device address - * @param mem_addr: Internal memory address - * @param add_size: size of internal memory address - * @param buf: Pointer to data buffer - * @param size: Amount of data to be sent - * @retval Status, see @ref ald_status_t. - */ -ald_status_t ald_i2c_mem_write_by_it(i2c_handle_t *hperh, uint16_t dev_addr, uint16_t mem_addr, - i2c_addr_size_t add_size, uint8_t *buf, uint16_t size) -{ - if (hperh->state != I2C_STATE_READY) - return BUSY; - - if ((buf == NULL) || (size == 0)) - return ERROR; - - if (i2c_wait_flag_to_timeout(hperh, I2C_FLAG_BUSY, SET, I2C_TIMEOUT_BUSY_FLAG) != OK) - return BUSY; - - assert_param(IS_I2C_TYPE(hperh->perh)); - assert_param(IS_I2C_MEMADD_size(add_size)); - - __LOCK(hperh); - CLEAR_BIT(hperh->perh->CON1, I2C_CON1_POSAP); - - hperh->state = I2C_STATE_BUSY_TX; - hperh->mode = I2C_MODE_MEM; - hperh->error_code = I2C_ERROR_NONE; - hperh->p_buff = buf; - hperh->xfer_size = size; - hperh->xfer_count = size; - - if (i2c_req_mem_write(hperh, dev_addr, mem_addr, add_size, I2C_TIMEOUT_FLAG) != OK) { - if (hperh->error_code == I2C_ERROR_AF) { - __UNLOCK(hperh); - return ERROR; - } - else { - __UNLOCK(hperh); - return TIMEOUT; - } - } - - __UNLOCK(hperh); - - /* Note : The I2C interrupts must be enabled after unlocking current process - * to avoid the risk of I2C interrupt handle execution before current - * process unlock */ - ald_i2c_interrupt_config(hperh, I2C_IT_EVT, ENABLE); - ald_i2c_interrupt_config(hperh, I2C_IT_BUF, ENABLE); - ald_i2c_interrupt_config(hperh, I2C_IT_ERR, ENABLE); - - return OK; -} - -/** - * @brief Read an amount of data in non-blocking mode with Interrupt from a specific memory address - * @param hperh: Pointer to a i2c_handle_t structure that contains - * the configuration information for the specified I2C. - * @param dev_addr: Target device address - * @param mem_addr: Internal memory address - * @param add_size: size of internal memory address - * @param buf: Pointer to data buffer - * @param size: Amount of data to be sent - * @retval Status, see @ref ald_status_t. - */ -ald_status_t ald_i2c_mem_read_by_it(i2c_handle_t *hperh, uint16_t dev_addr, uint16_t mem_addr, - i2c_addr_size_t add_size, uint8_t *buf, uint16_t size) -{ - if (hperh->state != I2C_STATE_READY) - return BUSY; - - if ((buf == NULL) || (size == 0)) - return ERROR; - - if (i2c_wait_flag_to_timeout(hperh, I2C_FLAG_BUSY, SET, I2C_TIMEOUT_BUSY_FLAG) != OK) - return BUSY; - - assert_param(IS_I2C_TYPE(hperh->perh)); - assert_param(IS_I2C_MEMADD_size(add_size)); - - __LOCK(hperh); - CLEAR_BIT(hperh->perh->CON1, I2C_CON1_POSAP); - - hperh->state = I2C_STATE_BUSY_RX; - hperh->mode = I2C_MODE_MEM; - hperh->error_code = I2C_ERROR_NONE; - hperh->p_buff = buf; - hperh->xfer_size = size; - hperh->xfer_count = size; - - if (i2c_req_mem_read(hperh, dev_addr, mem_addr, add_size, I2C_TIMEOUT_FLAG) != OK) { - if (hperh->error_code == I2C_ERROR_AF) { - __UNLOCK(hperh); - return ERROR; - } - else { - __UNLOCK(hperh); - return TIMEOUT; - } - } - - if (hperh->xfer_count == 1) { - CLEAR_BIT(hperh->perh->CON1, I2C_CON1_ACKEN); - I2C_CLEAR_ADDRFLAG(hperh); - SET_BIT(hperh->perh->CON1, I2C_CON1_STOP); - } - else if (hperh->xfer_count == 2) { - SET_BIT(hperh->perh->CON1, I2C_CON1_POSAP); - I2C_CLEAR_ADDRFLAG(hperh); - CLEAR_BIT(hperh->perh->CON1, I2C_CON1_ACKEN); - } - else { - SET_BIT(hperh->perh->CON1, I2C_CON1_ACKEN); - I2C_CLEAR_ADDRFLAG(hperh); - } - - __UNLOCK(hperh); - - /* Note : The I2C interrupts must be enabled after unlocking current process - * to avoid the risk of I2C interrupt handle execution before current - * process unlock */ - ald_i2c_interrupt_config(hperh, I2C_IT_EVT, ENABLE); - ald_i2c_interrupt_config(hperh, I2C_IT_BUF, ENABLE); - ald_i2c_interrupt_config(hperh, I2C_IT_ERR, ENABLE); - - return OK; -} - -#ifdef ALD_DMA -/** - * @brief Write an amount of data in non-blocking mode with DMA to a specific memory address - * @param hperh: Pointer to a i2c_handle_t structure that contains - * the configuration information for the specified I2C. - * @param dev_addr: Target device address - * @param mem_addr: Internal memory address - * @param add_size: size of internal memory address - * @param buf: Pointer to data buffer - * @param size: Amount of data to be sent - * @param channel: DMA channel - * @retval Status, see @ref ald_status_t. - */ -ald_status_t ald_i2c_mem_write_by_dma(i2c_handle_t *hperh, uint16_t dev_addr, uint16_t mem_addr, i2c_addr_size_t add_size, - uint8_t *buf, uint16_t size, uint8_t channel) -{ - if (hperh->state != I2C_STATE_READY) - return BUSY; - - if ((buf == NULL) || (size == 0)) - return ERROR; - - if (i2c_wait_flag_to_timeout(hperh, I2C_FLAG_BUSY, SET, I2C_TIMEOUT_BUSY_FLAG) != OK) - return BUSY; - - assert_param(IS_I2C_TYPE(hperh->perh)); - assert_param(IS_I2C_MEMADD_size(add_size)); - - __LOCK(hperh); - CLEAR_BIT(hperh->perh->CON1, I2C_CON1_POSAP); - - hperh->state = I2C_STATE_BUSY_TX; - hperh->mode = I2C_MODE_MEM; - hperh->error_code = I2C_ERROR_NONE; - hperh->p_buff = buf; - hperh->xfer_size = size; - hperh->xfer_count = size; - - if (hperh->hdmatx.perh == NULL) - hperh->hdmatx.perh = DMA0; - - hperh->hdmatx.cplt_cbk = i2c_dma_mem_send_cplt; - hperh->hdmatx.cplt_arg = hperh; - hperh->hdmatx.err_cbk = i2c_dma_error; - hperh->hdmatx.err_arg = hperh; - ald_dma_config_struct(&hperh->hdmatx.config); - - hperh->hdmatx.config.src = (void *)buf; - hperh->hdmatx.config.dst = (void *)&hperh->perh->DATA; - hperh->hdmatx.config.data_width = DMA_DATA_SIZE_BYTE; - hperh->hdmatx.config.size = size; - hperh->hdmatx.config.src_inc = DMA_DATA_INC_BYTE; - hperh->hdmatx.config.dst_inc = DMA_DATA_INC_NONE; - hperh->hdmatx.config.msel = hperh->perh == I2C0 ? DMA_MSEL_I2C0 : DMA_MSEL_I2C1; - hperh->hdmatx.config.msigsel = DMA_MSIGSEL_I2C_TXEMPTY; - hperh->hdmatx.config.channel = channel; - ald_dma_config_basic(&hperh->hdmatx); - - if (i2c_req_mem_write(hperh, dev_addr, mem_addr, add_size, I2C_TIMEOUT_FLAG) != OK) { - if (hperh->error_code == I2C_ERROR_AF) { - __UNLOCK(hperh); - return ERROR; - } - else { - __UNLOCK(hperh); - return TIMEOUT; - } - } - - SET_BIT(hperh->perh->CON2, I2C_CON2_DMAEN); - __UNLOCK(hperh); - return OK; -} - -/** - * @brief Reads an amount of data in non-blocking mode with DMA from a specific memory address. - * @param hperh: Pointer to a i2c_handle_t structure that contains - * the configuration information for the specified I2C. - * @param dev_addr: Target device address - * @param mem_addr: Internal memory address - * @param add_size: size of internal memory address - * @param buf: Pointer to data buffer - * @param size: Amount of data to be read - * @param channel: DMA channel - * @retval Status, see @ref ald_status_t. - */ -ald_status_t ald_i2c_mem_read_by_dma(i2c_handle_t *hperh, uint16_t dev_addr, uint16_t mem_addr, i2c_addr_size_t add_size, - uint8_t *buf, uint16_t size, uint8_t channel) -{ - if (hperh->state != I2C_STATE_READY) - return BUSY; - - if ((buf == NULL) || (size == 0)) - return ERROR; - - if (i2c_wait_flag_to_timeout(hperh, I2C_FLAG_BUSY, SET, I2C_TIMEOUT_BUSY_FLAG) != OK) - return BUSY; - - assert_param(IS_I2C_TYPE(hperh->perh)); - assert_param(IS_I2C_MEMADD_size(add_size)); - - __LOCK(hperh); - CLEAR_BIT(hperh->perh->CON1, I2C_CON1_POSAP); - - hperh->state = I2C_STATE_BUSY_RX; - hperh->mode = I2C_MODE_MEM; - hperh->error_code = I2C_ERROR_NONE; - hperh->p_buff = buf; - hperh->xfer_size = size; - hperh->xfer_count = size; - - if (hperh->hdmarx.perh == NULL) - hperh->hdmarx.perh = DMA0; - - hperh->hdmarx.cplt_cbk = i2c_dma_mem_recv_cplt; - hperh->hdmarx.cplt_arg = (void *)hperh; - hperh->hdmarx.err_cbk = i2c_dma_error; - hperh->hdmarx.err_arg = (void *)hperh; - ald_dma_config_struct(&hperh->hdmarx.config); - - hperh->hdmarx.config.src = (void *)&hperh->perh->DATA; - hperh->hdmarx.config.dst = (void *)buf; - hperh->hdmarx.config.data_width = DMA_DATA_SIZE_BYTE; - hperh->hdmarx.config.size = size; - hperh->hdmarx.config.src_inc = DMA_DATA_INC_NONE; - hperh->hdmarx.config.dst_inc = DMA_DATA_INC_BYTE; - hperh->hdmarx.config.msel = hperh->perh == I2C0 ? DMA_MSEL_I2C0 : DMA_MSEL_I2C1; - hperh->hdmarx.config.msigsel = DMA_MSIGSEL_I2C_RNR; - hperh->hdmarx.config.channel = channel; - ald_dma_config_basic(&hperh->hdmarx); - - if (i2c_req_mem_read(hperh, dev_addr, mem_addr, add_size, I2C_TIMEOUT_FLAG) != OK) { - if (hperh->error_code == I2C_ERROR_AF) { - __UNLOCK(hperh); - return ERROR; - } - else { - __UNLOCK(hperh); - return TIMEOUT; - } - } - - if (size == 1) - CLEAR_BIT(hperh->perh->CON1, I2C_CON1_ACKEN); - else - SET_BIT(hperh->perh->CON2, I2C_CON2_LDMA); - - SET_BIT(hperh->perh->CON2, I2C_CON2_DMAEN); - I2C_CLEAR_ADDRFLAG(hperh); - __UNLOCK(hperh); - return OK; -} -#endif - -/** - * @brief Checks if target device is ready for communication. - * @note This function is used with Memory devices - * @param hperh: Pointer to a i2c_handle_t structure that contains - * the configuration information for the specified I2C. - * @param dev_addr: Target device address - * @param trials: Number of trials - * @param timeout: Timeout duration - * @retval Status, see @ref ald_status_t. - */ -ald_status_t ald_i2c_is_device_ready(i2c_handle_t *hperh, uint16_t dev_addr, uint32_t trials, uint32_t timeout) -{ - uint32_t tickstart = 0; - uint32_t tmp1 = 0; - uint32_t tmp2 = 0; - uint32_t tmp3 = 0; - uint32_t I2C_Trials = 1; - - if (hperh->state != I2C_STATE_READY) - return BUSY; - - if (i2c_wait_flag_to_timeout(hperh, I2C_FLAG_BUSY, SET, I2C_TIMEOUT_BUSY_FLAG) != OK) - return BUSY; - - assert_param(IS_I2C_TYPE(hperh->perh)); - - __LOCK(hperh); - CLEAR_BIT(hperh->perh->CON1, I2C_CON1_POSAP); - - hperh->state = I2C_STATE_BUSY; - hperh->error_code = I2C_ERROR_NONE; - - do { - SET_BIT(hperh->perh->CON1, I2C_CON1_START); - - if (i2c_wait_flag_to_timeout(hperh, I2C_FLAG_SB, RESET, timeout) != OK) { - __UNLOCK(hperh); - return TIMEOUT; - } - - hperh->perh->DATA = I2C_7BIT_ADD_WRITE(dev_addr); - tickstart = ald_get_tick(); - tmp1 = ald_i2c_get_flag_status(hperh, I2C_FLAG_ADDR); - tmp2 = ald_i2c_get_flag_status(hperh, I2C_FLAG_AF); - tmp3 = hperh->state; - - while ((tmp1 == RESET) && (tmp2 == RESET) && (tmp3 != I2C_STATE_TIMEOUT)) { - if ((timeout == 0) || ((ald_get_tick() - tickstart ) > timeout)) - hperh->state = I2C_STATE_TIMEOUT; - - tmp1 = ald_i2c_get_flag_status(hperh, I2C_FLAG_ADDR); - tmp2 = ald_i2c_get_flag_status(hperh, I2C_FLAG_AF); - tmp3 = hperh->state; - } - hperh->state = I2C_STATE_READY; - - if (ald_i2c_get_flag_status(hperh, I2C_FLAG_ADDR) == SET) { - SET_BIT(hperh->perh->CON1, I2C_CON1_STOP); - I2C_CLEAR_ADDRFLAG(hperh); - - if (i2c_wait_flag_to_timeout(hperh, I2C_FLAG_BUSY, SET, - I2C_TIMEOUT_BUSY_FLAG) != OK) { - __UNLOCK(hperh); - return TIMEOUT; - } - - hperh->state = I2C_STATE_READY; - __UNLOCK(hperh); - return OK; - } - else { - SET_BIT(hperh->perh->CON1, I2C_CON1_STOP); - ald_i2c_clear_flag_status(hperh, I2C_FLAG_AF); - - if (i2c_wait_flag_to_timeout(hperh, I2C_FLAG_BUSY, SET, - I2C_TIMEOUT_BUSY_FLAG) != OK) { - __UNLOCK(hperh); - return TIMEOUT; - } - } - } while (I2C_Trials++ < trials); - - hperh->state = I2C_STATE_READY; - __UNLOCK(hperh); - return OK; -} -/** - * @} - */ - -/** @defgroup I2C_Public_Functions_Group3 Peripheral Control functions - * @brief Peripheral state and Errors functions - * -@verbatim - =============================================================================== - ##### Peripheral Control functions ##### - =============================================================================== - [..] - This subsection permits to get in run-time the status of the peripheral - and the data flow. - -@endverbatim - * @{ - */ - -/** - * @brief Enable/disable the specified i2c interrupts. - * @param hperh: Pointer to a i2c_handle_t structure. - * @param it: Specifies the i2c interrupt sources to be enabled or disabled. - * This parameter can be one of the @ref i2c_interrupt_t. - * @param state: New state of the specified i2c interrupts. - * This parameter can be: - * @arg ENABLE - * @arg DISABLE - * @retval None - */ -void ald_i2c_interrupt_config(i2c_handle_t *hperh, i2c_interrupt_t it, type_func_t state) -{ - assert_param(IS_I2C_TYPE(hperh->perh)); - assert_param(IS_I2C_IT_TYPE(it)); - assert_param(IS_FUNC_STATE(state)); - - if (state == ENABLE) - SET_BIT((hperh)->perh->CON2, (it)); - else - CLEAR_BIT((hperh)->perh->CON2, (it)); - - return; -} - -/** - * @brief Get the status of I2C_SR register. - * @param hperh: Pointer to a i2c_handle_t structure. - * @param flag: Specifies the I2C status type. - * This parameter can be one of the @ref i2c_flag_t. - * @retval Status: - * - 0: RESET - * - 1: SET - */ -flag_status_t ald_i2c_get_flag_status(i2c_handle_t *hperh, i2c_flag_t flag) -{ - flag_status_t state = RESET; - - assert_param(IS_I2C_TYPE(hperh->perh)); - assert_param(IS_I2C_FLAG(flag)); - - if ((flag & 0xFF0000) == 0) { - if ((hperh->perh->STAT1 & flag) == flag) - state = SET; - } - else { - if ((hperh->perh->STAT2 & (flag >> 16)) == (flag >> 16)) - state = SET; - } - - return state; -} - -/** - * @brief Get the status of interrupt. - * @param hperh: Pointer to a i2c_handle_t structure. - * @param it: Specifies the i2c interrupt sources to be enabled or disabled. - * This parameter can be one of the @ref i2c_interrupt_t. - * @retval Status: - * - 0: RESET - * - 1: SET - */ -flag_status_t ald_i2c_get_it_status(i2c_handle_t *hperh, i2c_interrupt_t it) -{ - assert_param(IS_I2C_TYPE(hperh->perh)); - assert_param(IS_I2C_IT_TYPE(it)); - - if ((hperh->perh->CON2 & it) == it) - return SET; - else - return RESET; -} - -/** - * @brief Clear the UART interrupt flag. - * @param hperh: Pointer to a uart_handle_t structure. - * @param flag: Specifies the UART interrupt flag. - * This parameter can be one of the @ref uart_flag_t. - * @retval None - */ -void ald_i2c_clear_flag_status(i2c_handle_t *hperh, i2c_flag_t flag) -{ - assert_param(IS_I2C_TYPE(hperh->perh)); - assert_param(IS_I2C_FLAG(flag)); - - if (flag > 65535) - return; - - hperh->perh->STAT1 = (hperh->perh->STAT1 & (uint32_t)(~flag)); - - return; - -} - -/** - * @brief Return the I2C handle state. - * @param hperh: Pointer to a i2c_handle_t structure that contains - * the configuration information for the specified I2C. - * @retval ald_status_t state - */ -i2c_state_t ald_i2c_get_state(i2c_handle_t *hperh) -{ - return hperh->state; -} - -/** - * @brief Return the I2C error code. - * @param hperh: Pointer to a i2c_handle_t structure that contains - * the configuration information for the specified I2C. - * @retval I2C Error Code - */ -uint32_t ald_i2c_get_error(i2c_handle_t *hperh) -{ - return hperh->error_code; -} -/** - * @} - */ - -/** @defgroup I2C_Public_Functions_Group4 IRQ Handler and Callbacks - * @{ - */ - -/** - * @brief This function handles I2C event interrupt request. - * @param hperh: Pointer to a i2c_handle_t structure that contains - * the configuration information for the specified I2C. - * @retval None - */ -void ald_i2c_ev_irq_handler(i2c_handle_t *hperh) -{ - if (ald_i2c_get_flag_status(hperh, I2C_FLAG_ADDR) == SET) - i2c_slave_addr(hperh); - - if ((ald_i2c_get_it_status(hperh, I2C_IT_BUF) == SET) && (ald_i2c_get_flag_status(hperh, I2C_FLAG_TXE) == SET)) { - if ((hperh->mode == I2C_MODE_MASTER) || (hperh->mode == I2C_MODE_MEM)) - i2c_master_send_txe(hperh); - else - i2c_slave_send_txe(hperh); - } - - if ((ald_i2c_get_it_status(hperh, I2C_IT_BUF) == SET) && (ald_i2c_get_flag_status(hperh, I2C_FLAG_RXNE) == SET)) { - if ((hperh->mode == I2C_MODE_MASTER) || (hperh->mode == I2C_MODE_MEM)) - i2c_master_recv_rxne(hperh); - else - i2c_slave_recv_rxne(hperh); - } - - if (ald_i2c_get_flag_status(hperh, I2C_FLAG_BTF) == SET) { - if (ald_i2c_get_flag_status(hperh, I2C_FLAG_TRA) == SET) { - if ((hperh->mode == I2C_MODE_MASTER) || (hperh->mode == I2C_MODE_MEM)) - i2c_master_send_btf(hperh); - else - i2c_slave_send_btf(hperh); - } - else { - if ((hperh->mode == I2C_MODE_MASTER) || (hperh->mode == I2C_MODE_MEM)) - i2c_master_recv_btf(hperh); - else - i2c_slave_recv_btf(hperh); - } - } - - if ((hperh->mode == I2C_MODE_SLAVE) && (ald_i2c_get_flag_status(hperh, I2C_FLAG_STOPF) == SET)) - i2c_slave_stopf(hperh); -} - -/** - * @brief This function handles I2C error interrupt request. - * @param hperh: pointer to a i2c_handle_t structure that contains - * the configuration information for I2C module - * @retval NONE - */ -void ald_i2c_er_irq_handler(i2c_handle_t *hperh) -{ - uint32_t tmp1 = 0; - uint32_t tmp2 = 0; - uint32_t tmp3 = 0; - - tmp1 = ald_i2c_get_flag_status(hperh, I2C_FLAG_BERR); - tmp2 = ald_i2c_get_it_status(hperh, I2C_IT_ERR); - - /* I2C Bus error interrupt occurred */ - if ((tmp1 == SET) && (tmp2 == SET)) { - hperh->error_code |= I2C_ERROR_BERR; - ald_i2c_clear_flag_status(hperh, I2C_FLAG_BERR); - SET_BIT(hperh->perh->CON1, I2C_CON1_SRST); - } - - tmp1 = ald_i2c_get_flag_status(hperh, I2C_FLAG_ARLO); - tmp2 = ald_i2c_get_it_status(hperh, I2C_IT_ERR); - - /* I2C Arbitration Loss error interrupt occurred */ - if ((tmp1 == SET) && (tmp2 == SET)) { - hperh->error_code |= I2C_ERROR_ARLO; - ald_i2c_clear_flag_status(hperh, I2C_FLAG_ARLO); - } - - tmp1 = ald_i2c_get_flag_status(hperh, I2C_FLAG_AF); - tmp2 = ald_i2c_get_it_status(hperh, I2C_IT_ERR); - - /* I2C Acknowledge failure error interrupt occurred */ - if ((tmp1 == SET) && (tmp2 == SET)) { - tmp1 = hperh->mode; - tmp2 = hperh->xfer_count; - tmp3 = hperh->state; - if ((tmp1 == I2C_MODE_SLAVE) && (tmp2 == 0) && \ - (tmp3 == I2C_STATE_BUSY_TX)) { - i2c_slave_af(hperh); - } - else { - hperh->error_code |= I2C_ERROR_AF; - SET_BIT(hperh->perh->CON1, I2C_CON1_STOP); - ald_i2c_clear_flag_status(hperh, I2C_FLAG_AF); - } - } - - tmp1 = ald_i2c_get_flag_status(hperh, I2C_FLAG_OVR); - tmp2 = ald_i2c_get_it_status(hperh, I2C_IT_ERR); - - /* I2C Over-Run/Under-Run interrupt occurred */ - if ((tmp1 == SET) && (tmp2 == SET)) { - hperh->error_code |= I2C_ERROR_OVR; - ald_i2c_clear_flag_status(hperh, I2C_FLAG_OVR); - } - - if (hperh->error_code != I2C_ERROR_NONE) { - hperh->state = I2C_STATE_READY; - CLEAR_BIT(hperh->perh->CON1, I2C_CON1_POSAP); - if (hperh->error_callback) - hperh->error_callback(hperh); - } -} -/** - * @} - */ - -/** - * @} - */ - -/** @addtogroup I2C_Private_Functions - * @{ - */ - -/** - * @brief Handle TXE flag for Master Transmit mode - * @param hperh: Pointer to a i2c_handle_t structure that contains - * the configuration information for the specified I2C. - * @retval Status, see @ref ald_status_t. - */ -static ald_status_t i2c_master_send_txe(i2c_handle_t *hperh) -{ - if (hperh->xfer_count == 0) { - ald_i2c_interrupt_config(hperh, I2C_IT_BUF, DISABLE); - } - else { - hperh->perh->DATA = (*hperh->p_buff++); - hperh->xfer_count--; - } - - return OK; -} - -/** - * @brief Handle BTF flag for Master Transmit mode - * @param hperh: Pointer to a i2c_handle_t structure that contains - * the configuration information for the specified I2C. - * @retval Status, see @ref ald_status_t. - */ -static ald_status_t i2c_master_send_btf(i2c_handle_t *hperh) -{ - if (hperh->xfer_count != 0) { - hperh->perh->DATA = (*hperh->p_buff++); - hperh->xfer_count--; - } - else { - ald_i2c_interrupt_config(hperh, I2C_IT_EVT, DISABLE); - ald_i2c_interrupt_config(hperh, I2C_IT_BUF, DISABLE); - ald_i2c_interrupt_config(hperh, I2C_IT_ERR, DISABLE); - SET_BIT(hperh->perh->CON1, I2C_CON1_STOP); - if (hperh->mode == I2C_MODE_MEM) { - hperh->state = I2C_STATE_READY; - if (hperh->mem_tx_cplt_cbk) - hperh->mem_tx_cplt_cbk(hperh); - } - else { - hperh->state = I2C_STATE_READY; - if (hperh->master_tx_cplt_cbk) - hperh->master_tx_cplt_cbk(hperh); - } - } - return OK; -} - -/** - * @brief Handle RXNE flag for Master Receive mode - * @param hperh: Pointer to a i2c_handle_t structure that contains - * the configuration information for the specified I2C. - * @retval Status, see @ref ald_status_t. - */ -static ald_status_t i2c_master_recv_rxne(i2c_handle_t *hperh) -{ - uint32_t tmp = 0; - - tmp = hperh->xfer_count; - if (tmp > 3) { - (*hperh->p_buff++) = hperh->perh->DATA; - hperh->xfer_count--; - } - else if ((tmp == 2) || (tmp == 3)) { - ald_i2c_interrupt_config(hperh, I2C_IT_BUF, DISABLE); - } - else { - ald_i2c_interrupt_config(hperh, I2C_IT_EVT, DISABLE); - ald_i2c_interrupt_config(hperh, I2C_IT_BUF, DISABLE); - ald_i2c_interrupt_config(hperh, I2C_IT_ERR, DISABLE); - (*hperh->p_buff++) = hperh->perh->DATA; - hperh->xfer_count--; - - if (hperh->mode == I2C_MODE_MEM) { - hperh->state = I2C_STATE_READY; - if (hperh->mem_rx_cplt_cbk) - hperh->mem_rx_cplt_cbk(hperh); - } - else { - hperh->state = I2C_STATE_READY; - if (hperh->master_rx_cplt_cbk) - hperh->master_rx_cplt_cbk(hperh); - } - } - return OK; -} - -/** - * @brief Handle BTF flag for Master Receive mode - * @param hperh: Pointer to a i2c_handle_t structure that contains - * the configuration information for the specified I2C. - * @retval Status, see @ref ald_status_t. - */ -static ald_status_t i2c_master_recv_btf(i2c_handle_t *hperh) -{ - if (hperh->xfer_count == 3) { - CLEAR_BIT(hperh->perh->CON1, I2C_CON1_ACKEN); - (*hperh->p_buff++) = hperh->perh->DATA; - --hperh->xfer_count; - } - else if (hperh->xfer_count == 2) { - ald_i2c_interrupt_config(hperh, I2C_IT_EVT, DISABLE); - ald_i2c_interrupt_config(hperh, I2C_IT_ERR, DISABLE); - SET_BIT(hperh->perh->CON1, I2C_CON1_STOP); - (*hperh->p_buff++) = hperh->perh->DATA; - --hperh->xfer_count; - - (*hperh->p_buff++) = hperh->perh->DATA; - --hperh->xfer_count; - - if (hperh->mode == I2C_MODE_MEM) { - hperh->state = I2C_STATE_READY; - if (hperh->mem_rx_cplt_cbk) - hperh->mem_rx_cplt_cbk(hperh); - } - else { - hperh->state = I2C_STATE_READY; - if (hperh->master_rx_cplt_cbk) - hperh->master_rx_cplt_cbk(hperh); - } - } - else { - (*hperh->p_buff++) = hperh->perh->DATA; - --hperh->xfer_count; - } - return OK; -} - -/** - * @brief Handle TXE flag for Slave Transmit mode - * @param hperh: Pointer to a i2c_handle_t structure that contains - * the configuration information for the specified I2C. - * @retval Status, see @ref ald_status_t. - */ -static ald_status_t i2c_slave_send_txe(i2c_handle_t *hperh) -{ - if (hperh->xfer_count != 0) { - hperh->perh->DATA = (*hperh->p_buff++); - --hperh->xfer_count; - } - return OK; -} - -/** - * @brief Handle BTF flag for Slave Transmit mode - * @param hperh: Pointer to a i2c_handle_t structure that contains - * the configuration information for the specified I2C. - * @retval Status, see @ref ald_status_t. - */ -static ald_status_t i2c_slave_send_btf(i2c_handle_t *hperh) -{ - if (hperh->xfer_count != 0) { - hperh->perh->DATA = (*hperh->p_buff++); - --hperh->xfer_count; - } - return OK; -} - -/** - * @brief Handle RXNE flag for Slave Receive mode - * @param hperh: Pointer to a i2c_handle_t structure that contains - * the configuration information for the specified I2C. - * @retval Status, see @ref ald_status_t. - */ -static ald_status_t i2c_slave_recv_rxne(i2c_handle_t *hperh) -{ - if (hperh->xfer_count != 0) { - (*hperh->p_buff++) = hperh->perh->DATA; - --hperh->xfer_count; - } - return OK; -} - -/** - * @brief Handle BTF flag for Slave Receive mode - * @param hperh: Pointer to a i2c_handle_t structure that contains - * the configuration information for the specified I2C. - * @retval Status, see @ref ald_status_t. - */ -static ald_status_t i2c_slave_recv_btf(i2c_handle_t *hperh) -{ - if (hperh->xfer_count != 0) { - (*hperh->p_buff++) = hperh->perh->DATA; - --hperh->xfer_count; - } - return OK; -} - -/** - * @brief Handle ADD flag for Slave - * @param hperh: Pointer to a i2c_handle_t structure that contains - * the configuration information for the specified I2C. - * @retval Status, see @ref ald_status_t. - */ -static ald_status_t i2c_slave_addr(i2c_handle_t *hperh) -{ - I2C_CLEAR_ADDRFLAG(hperh); - - return OK; -} - -/** - * @brief Handle STOPF flag for Slave mode - * @param hperh: Pointer to a i2c_handle_t structure that contains - * the configuration information for the specified I2C. - * @retval Status, see @ref ald_status_t. - */ -static ald_status_t i2c_slave_stopf(i2c_handle_t *hperh) -{ - if (hperh->xfer_count != 0) { - (*hperh->p_buff++) = hperh->perh->DATA; - --hperh->xfer_count; - } - - ald_i2c_interrupt_config(hperh, I2C_IT_EVT, DISABLE); - ald_i2c_interrupt_config(hperh, I2C_IT_BUF, DISABLE); - ald_i2c_interrupt_config(hperh, I2C_IT_ERR, DISABLE); - __I2C_CLEAR_STOPFLAG(hperh); - - CLEAR_BIT(hperh->perh->CON1, I2C_CON1_ACKEN); - hperh->state = I2C_STATE_READY; - - if (hperh->slave_rx_cplt_cbk) - hperh->slave_rx_cplt_cbk(hperh); - - return OK; -} - -/** - * @brief Handle Acknowledge Failed for Slave mode - * @param hperh: Pointer to a i2c_handle_t structure that contains - * the configuration information for the specified I2C. - * @retval Status, see @ref ald_status_t. - */ -static ald_status_t i2c_slave_af(i2c_handle_t *hperh) -{ - ald_i2c_interrupt_config(hperh, I2C_IT_EVT, DISABLE); - ald_i2c_interrupt_config(hperh, I2C_IT_BUF, DISABLE); - ald_i2c_interrupt_config(hperh, I2C_IT_ERR, DISABLE); - ald_i2c_clear_flag_status(hperh, I2C_FLAG_AF); - - CLEAR_BIT(hperh->perh->CON1, I2C_CON1_ACKEN); - hperh->state = I2C_STATE_READY; - - if (hperh->slave_tx_cplt_cbk) - hperh->slave_tx_cplt_cbk(hperh); - - return OK; -} - -/** - * @brief Master sends target device address followed by internal memory address for write request. - * @param hperh: Pointer to a i2c_handle_t structure that contains - * the configuration information for the specified I2C. - * @param dev_addr: Target device address - * @param timeout: Timeout duration - * @retval Status, see @ref ald_status_t. - */ -static ald_status_t i2c_master_req_write(i2c_handle_t *hperh, uint16_t dev_addr, uint32_t timeout) -{ - SET_BIT(hperh->perh->CON1, I2C_CON1_START); - - if (i2c_wait_flag_to_timeout(hperh, I2C_FLAG_SB, RESET, timeout) != OK) - return TIMEOUT; - - if (hperh->init.addr_mode == I2C_ADDR_7BIT) { - hperh->perh->DATA = I2C_7BIT_ADD_WRITE(dev_addr); - } - else { - hperh->perh->DATA = I2C_10BIT_HEADER_WRITE(dev_addr); - - if (i2c_wait_master_addr_to_timeout(hperh, I2C_FLAG_ADD10, timeout) != OK) { - if (hperh->error_code == I2C_ERROR_AF) { - return ERROR; - } - else { - return TIMEOUT; - } - } - - hperh->perh->DATA = I2C_10BIT_ADDRESS(dev_addr); - } - - if (i2c_wait_master_addr_to_timeout(hperh, I2C_FLAG_ADDR, timeout) != OK) { - if (hperh->error_code == I2C_ERROR_AF) - return ERROR; - else - return TIMEOUT; - } - return OK; -} - -/** - * @brief Master sends target device address followed by internal memory address for read request. - * @param hperh: Pointer to a i2c_handle_t structure that contains - * the configuration information for the specified I2C. - * @param dev_addr: Target device address - * @param timeout: Timeout duration - * @retval Status, see @ref ald_status_t. - */ -static ald_status_t i2c_master_req_read(i2c_handle_t *hperh, uint16_t dev_addr, uint32_t timeout) -{ - SET_BIT(hperh->perh->CON1, I2C_CON1_ACKEN); - SET_BIT(hperh->perh->CON1, I2C_CON1_START); - - if (i2c_wait_flag_to_timeout(hperh, I2C_FLAG_SB, RESET, timeout) != OK) - return TIMEOUT; - - if (hperh->init.addr_mode == I2C_ADDR_7BIT) { - hperh->perh->DATA = I2C_7BIT_ADD_READ(dev_addr); - } - else { - hperh->perh->DATA = I2C_10BIT_HEADER_WRITE(dev_addr); - if (i2c_wait_master_addr_to_timeout(hperh, I2C_FLAG_ADD10, timeout) != OK) { - if (hperh->error_code == I2C_ERROR_AF) - return ERROR; - else - return TIMEOUT; - } - - hperh->perh->DATA = I2C_10BIT_ADDRESS(dev_addr); - - if (i2c_wait_master_addr_to_timeout(hperh, I2C_FLAG_ADDR, timeout) != OK) { - if (hperh->error_code == I2C_ERROR_AF) - return ERROR; - else - return TIMEOUT; - } - - I2C_CLEAR_ADDRFLAG(hperh); - SET_BIT(hperh->perh->CON1, I2C_CON1_START); - - if (i2c_wait_flag_to_timeout(hperh, I2C_FLAG_SB, RESET, timeout) != OK) - return TIMEOUT; - - hperh->perh->DATA = I2C_10BIT_HEADER_READ(dev_addr); - } - - if (i2c_wait_master_addr_to_timeout(hperh, I2C_FLAG_ADDR, timeout) != OK) { - if (hperh->error_code == I2C_ERROR_AF) - return ERROR; - else - return TIMEOUT; - } - - I2C_CLEAR_ADDRFLAG(hperh); - return OK; -} - -/** - * @brief Master sends target device address followed by internal memory address for write request. - * @param hperh: Pointer to a i2c_handle_t structure that contains - * the configuration information for the specified I2C. - * @param dev_addr: Target device address - * @param mem_addr: Internal memory address - * @param add_size: size of internal memory address - * @param timeout: Timeout duration - * @retval Status, see @ref ald_status_t. - */ -static ald_status_t i2c_req_mem_write(i2c_handle_t *hperh, uint16_t dev_addr, uint16_t mem_addr, uint16_t add_size, uint32_t timeout) -{ - SET_BIT(hperh->perh->CON1, I2C_CON1_START); - - if (i2c_wait_flag_to_timeout(hperh, I2C_FLAG_SB, RESET, timeout) != OK) { - return TIMEOUT; - } - - hperh->perh->DATA = I2C_7BIT_ADD_WRITE(dev_addr); - - if (i2c_wait_master_addr_to_timeout(hperh, I2C_FLAG_ADDR, timeout) != OK) { - if (hperh->error_code == I2C_ERROR_AF) - return ERROR; - else - return TIMEOUT; - } - - I2C_CLEAR_ADDRFLAG(hperh); - - if (i2c_wait_txe_to_timeout(hperh, timeout) != OK) { - if (hperh->error_code == I2C_ERROR_AF) { - SET_BIT(hperh->perh->CON1, I2C_CON1_STOP); - return ERROR; - } - else { - return TIMEOUT; - } - } - - if (add_size == I2C_MEMADD_SIZE_8BIT) { - hperh->perh->DATA = I2C_MEM_ADD_LSB(mem_addr); - } - else { - hperh->perh->DATA = I2C_MEM_ADD_MSB(mem_addr); - if (i2c_wait_txe_to_timeout(hperh, timeout) != OK) { - if (hperh->error_code == I2C_ERROR_AF) { - SET_BIT(hperh->perh->CON1, I2C_CON1_STOP); - return ERROR; - } - else { - return TIMEOUT; - } - } - hperh->perh->DATA = I2C_MEM_ADD_LSB(mem_addr); - } - - return OK; -} - -/** - * @brief Master sends target device address followed by internal memory address for read request. - * @param hperh: Pointer to a i2c_handle_t structure that contains - * the configuration information for the specified I2C. - * @param dev_addr: Target device address - * @param mem_addr: Internal memory address - * @param add_size: size of internal memory address - * @param timeout: Timeout duration - * @retval Status, see @ref ald_status_t. - */ -static ald_status_t i2c_req_mem_read(i2c_handle_t *hperh, uint16_t dev_addr, uint16_t mem_addr, uint16_t add_size, uint32_t timeout) -{ - SET_BIT(hperh->perh->CON1, I2C_CON1_ACKEN); - SET_BIT(hperh->perh->CON1, I2C_CON1_START); - - if (i2c_wait_flag_to_timeout(hperh, I2C_FLAG_SB, RESET, timeout) != OK) - return TIMEOUT; - - hperh->perh->DATA = I2C_7BIT_ADD_WRITE(dev_addr); - - if (i2c_wait_master_addr_to_timeout(hperh, I2C_FLAG_ADDR, timeout) != OK) { - if (hperh->error_code == I2C_ERROR_AF) - return ERROR; - else - return TIMEOUT; - } - - I2C_CLEAR_ADDRFLAG(hperh); - - if (i2c_wait_txe_to_timeout(hperh, timeout) != OK) { - if (hperh->error_code == I2C_ERROR_AF) { - SET_BIT(hperh->perh->CON1, I2C_CON1_STOP); - return ERROR; - } - else { - return TIMEOUT; - } - } - - if (add_size == I2C_MEMADD_SIZE_8BIT) { - hperh->perh->DATA = I2C_MEM_ADD_LSB(mem_addr); - } - else { - hperh->perh->DATA = I2C_MEM_ADD_MSB(mem_addr); - - if (i2c_wait_txe_to_timeout(hperh, timeout) != OK) { - if (hperh->error_code == I2C_ERROR_AF) { - SET_BIT(hperh->perh->CON1, I2C_CON1_STOP); - return ERROR; - } - else { - return TIMEOUT; - } - } - hperh->perh->DATA = I2C_MEM_ADD_LSB(mem_addr); - } - - if (i2c_wait_txe_to_timeout(hperh, timeout) != OK) { - if (hperh->error_code == I2C_ERROR_AF) { - SET_BIT(hperh->perh->CON1, I2C_CON1_STOP); - return ERROR; - } - else { - return TIMEOUT; - } - } - - SET_BIT(hperh->perh->CON1, I2C_CON1_START); - - if (i2c_wait_flag_to_timeout(hperh, I2C_FLAG_SB, RESET, timeout) != OK) - return TIMEOUT; - - hperh->perh->DATA = I2C_7BIT_ADD_READ(dev_addr); - - if (i2c_wait_master_addr_to_timeout(hperh, I2C_FLAG_ADDR, timeout) != OK) { - if (hperh->error_code == I2C_ERROR_AF) - return ERROR; - else - return TIMEOUT; - } - - return OK; -} - -#ifdef ALD_DMA -/** - * @brief DMA I2C master transmit process complete callback. - * @param argv: I2C handle - * @retval None - */ -static void i2c_dma_master_send_cplt(void *argv) -{ - i2c_handle_t* hperh = (i2c_handle_t*)argv; - - if (i2c_wait_flag_to_timeout(hperh, I2C_FLAG_BTF, RESET, I2C_TIMEOUT_FLAG) != OK) - hperh->error_code |= I2C_ERROR_TIMEOUT; - - SET_BIT(hperh->perh->CON1, I2C_CON1_STOP); - CLEAR_BIT(hperh->perh->CON2, I2C_CON2_DMAEN); - - hperh->xfer_count = 0; - hperh->state = I2C_STATE_READY; - hperh->mode = I2C_MODE_NONE; - - if (hperh->error_code != I2C_ERROR_NONE) { - if (hperh->error_callback) - hperh->error_callback(hperh); - } - else { - if (hperh->master_tx_cplt_cbk) - hperh->master_tx_cplt_cbk(hperh); - } -} - -/** - * @brief DMA I2C slave transmit process complete callback. - * @param argv: I2C handle - * @retval None - */ -static void i2c_dma_slave_send_cplt(void *argv) -{ - i2c_handle_t* hperh = (i2c_handle_t*)argv; - - if (i2c_wait_flag_to_timeout(hperh, I2C_FLAG_AF, RESET, I2C_TIMEOUT_FLAG) != OK) - hperh->error_code |= I2C_ERROR_TIMEOUT; - - ald_i2c_clear_flag_status(hperh, I2C_FLAG_AF); - - CLEAR_BIT(hperh->perh->CON1, I2C_CON1_ACKEN); - CLEAR_BIT(hperh->perh->CON2, I2C_CON2_DMAEN); - - hperh->xfer_count = 0; - hperh->state = I2C_STATE_READY; - hperh->mode = I2C_MODE_NONE; - - if (hperh->error_code != I2C_ERROR_NONE) { - if (hperh->error_callback) - hperh->error_callback(hperh); - } - else { - if (hperh->slave_tx_cplt_cbk) - hperh->slave_tx_cplt_cbk(hperh); - } -} - -/** - * @brief DMA I2C master receive process complete callback - * @param argv: I2C handle - * @retval None - */ -static void i2c_dma_master_recv_cplt(void *argv) -{ - i2c_handle_t* hperh = (i2c_handle_t*)argv; - - CLEAR_BIT(hperh->perh->CON1, I2C_CON1_ACKEN); - SET_BIT(hperh->perh->CON1, I2C_CON1_STOP); - CLEAR_BIT(hperh->perh->CON2, I2C_CON2_LDMA); - CLEAR_BIT(hperh->perh->CON2, I2C_CON2_DMAEN); - - hperh->xfer_count = 0; - hperh->state = I2C_STATE_READY; - hperh->mode = I2C_MODE_NONE; - - if (hperh->error_code != I2C_ERROR_NONE) { - if (hperh->error_callback) - hperh->error_callback(hperh); - } - else { - if (hperh->master_rx_cplt_cbk) - hperh->master_rx_cplt_cbk(hperh); - } -} - -/** - * @brief DMA I2C slave receive process complete callback. - * @param argv: I2C handle - * @retval None - */ -static void i2c_dma_slave_recv_cplt(void *argv) -{ - i2c_handle_t* hperh = (i2c_handle_t*)argv; - - if (i2c_wait_stop_to_timeout(hperh, I2C_TIMEOUT_FLAG) != OK) { - if (hperh->error_code == I2C_ERROR_AF) - hperh->error_code |= I2C_ERROR_AF; - else - hperh->error_code |= I2C_ERROR_TIMEOUT; - } - - __I2C_CLEAR_STOPFLAG(hperh); - - CLEAR_BIT(hperh->perh->CON1, I2C_CON1_ACKEN); - CLEAR_BIT(hperh->perh->CON2, I2C_CON2_DMAEN); - - hperh->xfer_count = 0; - hperh->state = I2C_STATE_READY; - hperh->mode = I2C_MODE_NONE; - - if (hperh->error_code != I2C_ERROR_NONE) { - if (hperh->error_callback) - hperh->error_callback(hperh); - } - else { - if (hperh->slave_rx_cplt_cbk) - hperh->slave_rx_cplt_cbk(hperh); - } -} - -/** - * @brief DMA I2C Memory Write process complete callback - * @param argv: I2C handle - * @retval None - */ -static void i2c_dma_mem_send_cplt(void *argv) -{ - i2c_handle_t* hperh = (i2c_handle_t*)argv; - - if (i2c_wait_flag_to_timeout(hperh, I2C_FLAG_BTF, RESET, I2C_TIMEOUT_FLAG) != OK) - hperh->error_code |= I2C_ERROR_TIMEOUT; - - SET_BIT(hperh->perh->CON1, I2C_CON1_STOP); - CLEAR_BIT(hperh->perh->CON2, I2C_CON2_DMAEN); - - hperh->xfer_count = 0; - hperh->state = I2C_STATE_READY; - hperh->mode = I2C_MODE_NONE; - - if (hperh->error_code != I2C_ERROR_NONE) { - if (hperh->error_callback) - hperh->error_callback(hperh); - } - else { - if (hperh->mem_tx_cplt_cbk) - hperh->mem_tx_cplt_cbk(hperh); - } -} - -/** - * @brief DMA I2C Memory Read process complete callback - * @param argv: I2C handle - * @retval None - */ -static void i2c_dma_mem_recv_cplt(void *argv) -{ - i2c_handle_t* hperh = (i2c_handle_t*)argv; - - CLEAR_BIT(hperh->perh->CON1, I2C_CON1_ACKEN); - SET_BIT(hperh->perh->CON1, I2C_CON1_STOP); - CLEAR_BIT(hperh->perh->CON2, I2C_CON2_LDMA); - CLEAR_BIT(hperh->perh->CON2, I2C_CON2_DMAEN); - - hperh->xfer_count = 0; - hperh->state = I2C_STATE_READY; - hperh->mode = I2C_MODE_NONE; - - if (hperh->error_code != I2C_ERROR_NONE) { - if (hperh->error_callback) - hperh->error_callback(hperh); - } - else { - if (hperh->mem_rx_cplt_cbk) - hperh->mem_rx_cplt_cbk(hperh); - } -} -#endif - -/** - * @brief I2C Configuration Speed function - * @param hperh: Pointer to a i2c_handle_t structure that contains - * the configuration information for the specified I2C. - * @param i2c_clk: PCLK frequency from RCC. - * @retval CCR Speed: Speed to set in I2C CCR Register - */ -static uint32_t i2c_configure_speed(i2c_handle_t *hperh, uint32_t i2c_clk) -{ - uint32_t tmp1 = 0; - - if (hperh->init.clk_speed <= I2C_STANDARD_MODE_MAX_CLK) { - tmp1 = (i2c_clk / (hperh->init.clk_speed << 1)); - if ((tmp1 & I2C_CKCFG_CLKSET) < 4 ) - return 4; - else - return tmp1; - } - else { - tmp1 = I2C_CKCFG_CLKMOD; - - if (hperh->init.duty == I2C_DUTYCYCLE_2) { - tmp1 |= (i2c_clk / (hperh->init.clk_speed * 3)) | I2C_DUTYCYCLE_2; - CLEAR_BIT(hperh->perh->CKCFG, I2C_CKCFG_CLKMOD_MSK); - } - else { - tmp1 |= (i2c_clk / (hperh->init.clk_speed * 25)) | I2C_DUTYCYCLE_16_9; - SET_BIT(hperh->perh->CKCFG, I2C_CKCFG_CLKMOD_MSK); - } - - if ((tmp1 & I2C_CKCFG_CLKSET) < 1 ) - return 1; - else - return tmp1; - } -} - -#ifdef ALD_DMA -/** - * @brief DMA I2C communication error callback. - * @param argv: I2C handle - * @retval None - */ -static void i2c_dma_error(void *argv) -{ - i2c_handle_t* hperh = (i2c_handle_t*)argv; - - CLEAR_BIT(hperh->perh->CON1, I2C_CON1_ACKEN); - - hperh->xfer_count = 0; - hperh->state = I2C_STATE_READY; - hperh->mode = I2C_MODE_NONE; - hperh->error_code |= I2C_ERROR_DMA; - - if (hperh->error_callback) - hperh->error_callback(hperh); -} -#endif - -/** - * @brief This function handles I2C Communication timeout. - * @param hperh: Pointer to a i2c_handle_t structure that contains - * the configuration information for the specified I2C. - * @param flag: specifies the I2C flag to check. - * @param status: The new flag status (SET or RESET). - * @param timeout: Timeout duration - * @retval Status, see @ref ald_status_t. - */ -static ald_status_t i2c_wait_flag_to_timeout(i2c_handle_t *hperh, i2c_flag_t flag, flag_status_t status, uint32_t timeout) -{ - uint32_t tickstart = 0; - - tickstart = ald_get_tick(); - - if (status == RESET) { - while (ald_i2c_get_flag_status(hperh, flag) == RESET) { - if ((timeout == 0) || ((ald_get_tick() - tickstart ) > timeout)) { - hperh->state = I2C_STATE_READY; - __UNLOCK(hperh); - return TIMEOUT; - } - } - } - else { - while (ald_i2c_get_flag_status(hperh, flag) != RESET) { - if ((timeout == 0) || ((ald_get_tick() - tickstart ) > timeout)) { - hperh->state = I2C_STATE_READY; - __UNLOCK(hperh); - return TIMEOUT; - } - } - } - return OK; -} - -/** - * @brief This function handles I2C Communication timeout for Master addressing phase. - * @param hperh: Pointer to a i2c_handle_t structure that contains - * the configuration information for the specified I2C. - * @param flag: specifies the I2C flag to check. - * @param timeout: Timeout duration - * @retval Status, see @ref ald_status_t. - */ -static ald_status_t i2c_wait_master_addr_to_timeout(i2c_handle_t *hperh, i2c_flag_t flag, uint32_t timeout) -{ - uint32_t tickstart = 0; - - tickstart = ald_get_tick(); - while (ald_i2c_get_flag_status(hperh, flag) == RESET) { - if (ald_i2c_get_flag_status(hperh, I2C_FLAG_AF) == SET) { - SET_BIT(hperh->perh->CON1, I2C_CON1_STOP); - ald_i2c_clear_flag_status(hperh, I2C_FLAG_AF); - - hperh->error_code = I2C_ERROR_AF; - hperh->state = I2C_STATE_READY; - __UNLOCK(hperh); - return ERROR; - } - - if (timeout != I2C_MAX_DELAY) { - if ((timeout == 0) || ((ald_get_tick() - tickstart ) > timeout)) { - hperh->state = I2C_STATE_READY; - __UNLOCK(hperh); - return TIMEOUT; - } - } - } - return OK; -} - -/** - * @brief This function handles I2C Communication timeout for specific usage of TXE flag. - * @param hperh: Pointer to a i2c_handle_t structure that contains - * the configuration information for the specified I2C. - * @param timeout: Timeout duration - * @retval Status, see @ref ald_status_t. - */ -static ald_status_t i2c_wait_txe_to_timeout(i2c_handle_t *hperh, uint32_t timeout) -{ - uint32_t tickstart = ald_get_tick(); - - while (ald_i2c_get_flag_status(hperh, I2C_FLAG_TXE) == RESET) { - if (i2c_is_ack_failed(hperh) != OK) - return ERROR; - - if (timeout != I2C_MAX_DELAY) { - if ((timeout == 0) || ((ald_get_tick() - tickstart) > timeout)) { - hperh->error_code |= I2C_ERROR_TIMEOUT; - hperh->state = I2C_STATE_READY; - __UNLOCK(hperh); - return TIMEOUT; - } - } - } - return OK; -} - -/** - * @brief This function handles I2C Communication timeout for specific usage of BTF flag. - * @param hperh: Pointer to a i2c_handle_t structure that contains - * the configuration information for the specified I2C. - * @param timeout: Timeout duration - * @retval Status, see @ref ald_status_t. - */ -static ald_status_t i2c_wait_btf_to_timeout(i2c_handle_t *hperh, uint32_t timeout) -{ - uint32_t tickstart = ald_get_tick(); - - while (ald_i2c_get_flag_status(hperh, I2C_FLAG_BTF) == RESET) { - if (i2c_is_ack_failed(hperh) != OK) { - return ERROR; - } - - if (timeout != I2C_MAX_DELAY) { - if ((timeout == 0) || ((ald_get_tick() - tickstart) > timeout)) { - hperh->error_code |= I2C_ERROR_TIMEOUT; - hperh->state = I2C_STATE_READY; - __UNLOCK(hperh); - return TIMEOUT; - } - } - } - return OK; -} - -/** - * @brief This function handles I2C Communication timeout for specific usage of STOP flag. - * @param hperh: Pointer to a i2c_handle_t structure that contains - * the configuration information for the specified I2C. - * @param timeout: Timeout duration - * @retval Status, see @ref ald_status_t. - */ -static ald_status_t i2c_wait_stop_to_timeout(i2c_handle_t *hperh, uint32_t timeout) -{ - uint32_t tickstart = 0x00; - tickstart = ald_get_tick(); - - while (ald_i2c_get_flag_status(hperh, I2C_FLAG_STOPF) == RESET) { - if (i2c_is_ack_failed(hperh) != OK) - return ERROR; - - if ((timeout == 0) || ((ald_get_tick() - tickstart) > timeout)) { - hperh->error_code |= I2C_ERROR_TIMEOUT; - hperh->state = I2C_STATE_READY; - __UNLOCK(hperh); - return TIMEOUT; - } - } - return OK; -} - -/** - * @brief This function handles I2C Communication timeout for specific usage of RXNE flag. - * @param hperh: Pointer to a i2c_handle_t structure that contains - * the configuration information for the specified I2C. - * @param timeout: Timeout duration - * @retval Status, see @ref ald_status_t. - */ -static ald_status_t i2c_wait_rxne_to_timeout(i2c_handle_t *hperh, uint32_t timeout) -{ - uint32_t tickstart = 0x00; - tickstart = ald_get_tick(); - - while (ald_i2c_get_flag_status(hperh, I2C_FLAG_RXNE) == RESET) { - if (ald_i2c_get_flag_status(hperh, I2C_FLAG_STOPF) == SET) { - ald_i2c_clear_flag_status(hperh, I2C_FLAG_STOPF); - hperh->error_code = I2C_ERROR_NONE; - hperh->state = I2C_STATE_READY; - __UNLOCK(hperh); - return ERROR; - } - - if ((timeout == 0) || ((ald_get_tick() - tickstart) > timeout)) { - hperh->error_code |= I2C_ERROR_TIMEOUT; - hperh->state = I2C_STATE_READY; - __UNLOCK(hperh); - return TIMEOUT; - } - } - return OK; -} - -/** - * @brief This function handles Acknowledge failed detection during an I2C Communication. - * @param hperh: Pointer to a i2c_handle_t structure that contains - * the configuration information for the specified I2C. - * @retval Status, see @ref ald_status_t. - */ -static ald_status_t i2c_is_ack_failed(i2c_handle_t *hperh) -{ - if (ald_i2c_get_flag_status(hperh, I2C_FLAG_AF) == SET) { - ald_i2c_clear_flag_status(hperh, I2C_FLAG_AF); - hperh->error_code = I2C_ERROR_AF; - hperh->state = I2C_STATE_READY; - __UNLOCK(hperh); - - return ERROR; - } - - return OK; -} -/** - * @} - */ - -#endif /* ALD_I2C */ -/** - * @} - */ - -/** - * @} - */ diff --git a/bsp/essemi/es32f0334/libraries/ES32F033x_ALD_StdPeriph_Driver/Source/ald_iap.c b/bsp/essemi/es32f0334/libraries/ES32F033x_ALD_StdPeriph_Driver/Source/ald_iap.c deleted file mode 100644 index ccb9b5170b..0000000000 --- a/bsp/essemi/es32f0334/libraries/ES32F033x_ALD_StdPeriph_Driver/Source/ald_iap.c +++ /dev/null @@ -1,149 +0,0 @@ -/** - ********************************************************************************* - * - * @file ald_iap.c - * @brief IAP module driver. - * - * @version V1.0 - * @date 04 Dec 2017 - * @author AE Team - * @note - * - * Copyright (C) Shanghai Eastsoft Microelectronics Co. Ltd. All rights reserved. - * - ********************************************************************************* - */ - -#include "ald_iap.h" - - -/** @addtogroup ES32FXXX_ALD - * @{ - */ - -/** @defgroup IAP IAP - * @brief IAP module driver - * @{ - */ -#ifdef ALD_IAP - - -/** @defgroup IAP_Public_Functions IAP Public Functions - * - * @verbatim - ============================================================================== - ##### Erase and Program flash functions ##### - ============================================================================== - [..] This section provides functions allowing to: - (+) Erase flash. - (+) Program flash. - - @endverbatim - * @{ - */ - -/** - * @brief Erases a specified page. - * @param addr: The beginning address of the page to be erased. - * @retval The result: - * - 0: SUCCESS - * - 1: ERROR - */ -uint32_t ald_iap_erase_page(uint32_t addr) -{ - uint32_t status; - IAP_PE iap_pe = (IAP_PE)(*(uint32_t *)IAP_PE_ADDR); - - __disable_irq(); - status = (*iap_pe)(addr); - __enable_irq(); - - return !status; -} - -/** - * @brief Programs a word at a specified address. - * @param addr: Specifies the address to be programmed. - * Bit0-1 must be zero. - * @param data: Specifies the data to be programmed. - * @retval The result: - * - 0: SUCCESS - * - 1: ERROR - */ -uint32_t ald_iap_program_word(uint32_t addr, uint32_t data) -{ - uint32_t status; - IAP_WP iap_wp = (IAP_WP)(*(uint32_t *)IAP_WP_ADDR); - - if (addr & 0x3) - return 1; - - __disable_irq(); - status = (*iap_wp)(addr, data); - __enable_irq(); - - return !status; -} - -/** - * @brief Programs double words at a specified address. - * @param addr: Specifies the address to be programmed. - * Bit0-1 must be zero. - * @param data_l: Specifies the LSB data to be programmed. - * @param data_h: Specifies the MSB data to be programmed. - * @retval The result: - * - 0: SUCCESS - * - 1: ERROR - */ -uint32_t ald_iap_program_dword(uint32_t addr, uint32_t data_l, uint32_t data_h) -{ - uint32_t status; - IAP_DWP iap_dwp = (IAP_DWP)(*(uint32_t *)IAP_DWP_ADDR); - - if (addr & 0x3) - return 1; - - __disable_irq(); - status = (*iap_dwp)(addr, data_l, data_h); - __enable_irq(); - - return !status; -} - -/** - * @brief Programs datas at a specified address. - * @param addr: Specifies the address to be programmed. - * Bit0-1 must be zero. - * @param data: Specifies the data to be programmed. - * @param len: Specifies the data length to be programmed. - * Bit0-1 must be zero. - * @param erase: Erase page flag before programming. - * @retval The result: - * - 0: SUCCESS - * - 1: ERROR - */ -uint32_t ald_iap_program_words(uint32_t addr, uint8_t *data, uint32_t len, uint32_t erase) -{ - uint32_t status; - IAP_WSP iap_wsp = (IAP_WSP)(*(uint32_t *)IAP_WSP_ADDR); - - if ((addr & 0x3) || (len & 0x3)) - return 1; - - __disable_irq(); - status = (*iap_wsp)(addr, data, len, erase); - __enable_irq(); - - return !status; -} -/** - * @} - */ -#endif /* ALD_IAP */ -/** - * @} - */ - -/** - * @} - */ diff --git a/bsp/essemi/es32f0334/libraries/ES32F033x_ALD_StdPeriph_Driver/Source/ald_lcd.c b/bsp/essemi/es32f0334/libraries/ES32F033x_ALD_StdPeriph_Driver/Source/ald_lcd.c deleted file mode 100644 index b4d955a98b..0000000000 --- a/bsp/essemi/es32f0334/libraries/ES32F033x_ALD_StdPeriph_Driver/Source/ald_lcd.c +++ /dev/null @@ -1,345 +0,0 @@ - /** - ********************************************************************************* - * - * @file ald_lcd.c - * @brief LCD module driver. - * - * @version V1.0 - * @date 29 Nov 2017 - * @author AE Team - * @note - * - * Copyright (C) Shanghai Eastsoft Microelectronics Co. Ltd. All rights reserved. - * - ********************************************************************************* - */ - -#include "ald_lcd.h" - -/** @addtogroup ES32FXXX_ALD - * @{ - */ - -/** @defgroup LCD LCD - * @brief LCD module library - * @{ - */ -#ifdef ALD_LCD - -/** @defgroup LCD_Public_Functions LCD Public Functions - * @{ - */ - -/** @defgroup LCD_Public_Functions_Group1 Initialize and Enable functions - * @brief Initialize and Enable Functions - * @{ - */ - -/** - * @brief Initializes the LCD Peripheral according to the specified parameters. - * @note This function can be used only when the LCD is disabled. - * @param hperh: Pointer to a lcd_handle_t structure that contains - * the configuration information for the specified LCD. - * @retval Status, see @ref ald_status_t. - */ -ald_status_t ald_lcd_init(lcd_handle_t *hperh) -{ - uint16_t delay = 0; - - assert_param(IS_LCD_PERH_TYPE(hperh->perh)); - assert_param(IS_LCD_VCHPS_TYPE(hperh->init.lcd_vchps)); - assert_param(IS_LCD_VSEL_TYPE(hperh->init.lcd_vsel)); - assert_param(IS_LCD_FUNC_TYPE(hperh->init.lcd_vbufld)); - assert_param(IS_LCD_FUNC_TYPE(hperh->init.lcd_vbufhd)); - assert_param(IS_LCD_LEVEL_TYPE(hperh->init.lcd_dsld)); - assert_param(IS_LCD_LEVEL_TYPE(hperh->init.lcd_dshd)); - assert_param(IS_LCD_RES_TYPE(hperh->init.lcd_resld)); - assert_param(IS_LCD_RES_TYPE(hperh->init.lcd_reshd)); - assert_param(IS_LCD_BIAS_TYPE(hperh->init.lcd_bias)); - assert_param(IS_LCD_DUTY_TYPE(hperh->init.lcd_duty)); - assert_param(IS_LCD_WFS_TYPE(hperh->init.lcd_wfs)); - assert_param(IS_LCD_PRS_TYPE(hperh->init.lcd_prs)); - assert_param(IS_LCD_DIV_TYPE(hperh->init.lcd_div)); - assert_param(IS_LCD_DEAD_TYPE(hperh->init.lcd_dead)); - assert_param(IS_LCD_PON_TYPE(hperh->init.lcd_pon)); - assert_param(IS_LCD_VGS_TYPE(hperh->init.lcd_vgs)); - - __LOCK(hperh); - - ald_cmu_lcd_clock_select(hperh->init.clock); - - MODIFY_REG(hperh->perh->FCR, LCD_FCR_WFS_MSK, hperh->init.lcd_wfs << LCD_FCR_WFS_POS); - MODIFY_REG(hperh->perh->FCR, LCD_FCR_PRS_MSK, hperh->init.lcd_prs << LCD_FCR_PRS_POSS); - for (delay = 0; delay < 3000; delay++); - MODIFY_REG(hperh->perh->FCR, LCD_FCR_DIV_MSK, hperh->init.lcd_div << LCD_FCR_DIV_POSS); - MODIFY_REG(hperh->perh->FCR, LCD_FCR_DEAD_MSK, hperh->init.lcd_dead << LCD_FCR_DEAD_POSS); - MODIFY_REG(hperh->perh->FCR, LCD_FCR_PON_MSK, hperh->init.lcd_pon << LCD_FCR_PON_POSS); - MODIFY_REG(hperh->perh->FCR, LCD_FCR_VGS_MSK, hperh->init.lcd_vgs << LCD_FCR_VGS_POSS); - - MODIFY_REG(hperh->perh->CR, LCD_CR_DUTY_MSK, hperh->init.lcd_duty << LCD_CR_DUTY_POSS); - MODIFY_REG(hperh->perh->CR, LCD_CR_BIAS_MSK, hperh->init.lcd_bias << LCD_CR_BIAS_POSS); - MODIFY_REG(hperh->perh->CR, LCD_CR_VBUFHD_MSK, hperh->init.lcd_vbufhd << LCD_CR_VBUFHD_POS); - MODIFY_REG(hperh->perh->CR, LCD_CR_VBUFLD_MSK, hperh->init.lcd_vbufld << LCD_CR_VBUFLD_POS); - MODIFY_REG(hperh->perh->CR, LCD_CR_DSHD_MSK, hperh->init.lcd_dshd << LCD_CR_DSHD_POSS); - MODIFY_REG(hperh->perh->CR, LCD_CR_DSLD_MSK, hperh->init.lcd_dsld << LCD_CR_DSLD_POSS); - MODIFY_REG(hperh->perh->CR, LCD_CR_RESHD_MSK, hperh->init.lcd_reshd << LCD_CR_RESHD_POSS); - MODIFY_REG(hperh->perh->CR, LCD_CR_RESLD_MSK, hperh->init.lcd_resld << LCD_CR_RESLD_POSS); - MODIFY_REG(hperh->perh->CR, LCD_CR_VSEL_MSK, hperh->init.lcd_vsel << LCD_CR_VSEL_POSS); - MODIFY_REG(hperh->perh->CR, LCD_CR_VCHPS_MSK, hperh->init.lcd_vchps << LCD_CR_VCHPS_POSS); - - __UNLOCK(hperh); - return OK; -} - -/** - * @brief Enables or disables the LCD controller. - * @param hperh: Pointer to a lcd_handle_t structure that contains - * the configuration information for the specified LCD. - * @param state: This parameter can be: ENABLE or DISABLE. - * @retval Status, see @ref ald_status_t. - */ -ald_status_t ald_lcd_cmd(lcd_handle_t *hperh, type_func_t state) -{ - assert_param(IS_LCD_PERH_TYPE(hperh->perh)); - assert_param(IS_FUNC_STATE(state)); - - __LOCK(hperh); - - MODIFY_REG(hperh->perh->CR, LCD_CR_OE_MSK, state << LCD_CR_OE_POS); - MODIFY_REG(hperh->perh->CR, LCD_CR_EN_MSK, state << LCD_CR_EN_POS); - - __UNLOCK(hperh); - return OK; -} -/** - * @} - */ - -/** @defgroup LCD_Public_Functions_Group2 Config output functions - * @brief Config output and blink functions - * @{ - */ - -/** - * @brief Configures the LCD blink mode and blink frequency. - * @param hperh: Pointer to a lcd_handle_t structure that contains - * the configuration information for the specified LCD. - * @param blink_mode: Specifies the LCD blink mode. - * @param blink_freq: Specifies the LCD blink frequency. - * @retval Status, see @ref ald_status_t. - */ -ald_status_t ald_lcd_blink_config(lcd_handle_t *hperh, lcd_blink_t blink_mode, lcd_blfrq_t blink_freq) -{ - uint16_t delay = 0; - assert_param(IS_LCD_PERH_TYPE(hperh->perh)); - assert_param(IS_LCD_BLINK_MODE(blink_mode)); - assert_param(IS_LCD_BLFRQ_TYPE(blink_freq)); - __LOCK(hperh); - - MODIFY_REG(hperh->perh->FCR, LCD_FCR_BLMOD_MSK, blink_mode << LCD_FCR_BLMOD_POSS); - for (delay = 0; delay < 3000; delay++); - MODIFY_REG(hperh->perh->FCR, LCD_FCR_BLFRQ_MSK, blink_freq << LCD_FCR_BLFRQ_POSS); - - __UNLOCK(hperh); - return OK; - } - -/** - * @brief Control segment port enable or disable - * @param hperh: Pointer to a lcd_handle_t structure that contains - * the configuration information for the specified LCD. - * @param seg: Specifies the LCD segment index - * @param seg_data: Specifies LCD segment data to be written to control segment output enable. - * @retval Status, see @ref ald_status_t. - */ -ald_status_t ald_lcd_write_seg(lcd_handle_t *hperh, lcd_seg_t seg, uint32_t seg_data) -{ - assert_param(IS_LCD_PERH_TYPE(hperh->perh)); - assert_param(IS_LCD_SEG_TYPE(seg)); - __LOCK(hperh); - - if (seg == SEG_0_TO_31) - WRITE_REG(hperh->perh->SEGCR0, seg_data); - else - WRITE_REG(hperh->perh->SEGCR1, seg_data); - - __UNLOCK(hperh); - return OK; -} - -/** - * @brief Writes a word in the specific LCD buffer to determine display. - * @param hperh: Pointer to a lcd_handle_t structure that contains - * the configuration information for the specified LCD. - * @param buf: Specifies the LCD buffer index. - * @param buf_data: Specifies LCD buffer data to be written to control display. - * @retval Status, see @ref ald_status_t. - */ -ald_status_t ald_lcd_write(lcd_handle_t *hperh, uint8_t buf, uint32_t buf_data) -{ - assert_param(IS_LCD_PERH_TYPE(hperh->perh)); - assert_param(IS_LCD_BUFFER_TYPE(buf)); - - __LOCK(hperh); - WRITE_REG(hperh->perh->BUF[buf], buf_data); - __UNLOCK(hperh); - - return OK; -} -/** - * @} - */ - -/** @defgroup LCD_Public_Functions_Group3 Peripheral State functions - * @brief LCD State functions - * @{ - */ - -/** - * @brief Checks whether the specified LCD flag is set or not. - * @param hperh: Pointer to a lcd_handle_t structure that contains - * the configuration information for the specified LCD. - * @param lcd_status: Specifies the flag to check. - * @retval The new state of LCD_STATUS - */ -uint32_t ald_lcd_get_status(lcd_handle_t *hperh, lcd_status_t lcd_status) -{ - assert_param(IS_LCD_PERH_TYPE(hperh->perh)); - assert_param(IS_LCD_STATUS_TYPE(lcd_status)); - - if (lcd_status == LCD_STATUS_ALL) - return hperh->perh->SR; - else - return hperh->perh->SR & lcd_status ? 1 : 0; -} -/** - * @} - */ - -/** @defgroup LCD_Public_Functions_Group4 Interrupt functions - * @brief LCD Interrupt functions - * @{ - */ - -/** - * @brief Enable or disable the specified interrupt - * @param hperh: Pointer to a lcd_handle_t structure that contains - * the configuration information for the specified LCD. - * @param it: Specifies the interrupt type to be enabled or disabled - * @arg @ref LCD_IT_SOF Start of frame interrupt enable - * @arg @ref LCD_IT_UDD Update display done interrupt - * @param state: New state of the specified interrupt. - * This parameter can be: ENABLE or DISABLE - * @retval Status, see @ref ald_status_t. - */ -ald_status_t ald_lcd_interrupt_config(lcd_handle_t *hperh, lcd_it_t it, type_func_t state) -{ - assert_param(IS_LCD_PERH_TYPE(hperh->perh)); - assert_param(IS_LCD_IT_TYPE(it)); - assert_param(IS_FUNC_STATE(state)); - __LOCK(hperh); - - if (state) - SET_BIT(hperh->perh->IE, it); - else - CLEAR_BIT(hperh->perh->IE, it); - - __UNLOCK(hperh); - return OK; -} - -/** - * @brief Checks whether the specified interrupt has set or not. - * @param hperh: Pointer to a lcd_handle_t structure that contains - * the configuration information for the specified LCD. - * @param it: Specifies the interrupt type to check - * This parameter can be one of the following values: - * @arg @ref LCD_IT_SOF Start of frame interrupt enable - * @arg @ref LCD_IT_UDD Update display done interrupt - * @retval The new state of the LCD_IT - */ -flag_status_t ald_lcd_get_it_status(lcd_handle_t *hperh, lcd_it_t it) -{ - assert_param(IS_LCD_PERH_TYPE(hperh->perh)); - assert_param(IS_LCD_IT_TYPE(it)); - - return hperh->perh->IE & it ? SET : RESET; -} - -/** - * @brief Checks whether the specified interrupt has occurred or not. - * @param hperh: Pointer to a lcd_handle_t structure that contains - * the configuration information for the specified LCD. - * @param flag: Specifies the interrupt type to check - * This parameter can be one of the following values: - * @arg @ref LCD_FLAG_SOF Start of frame interrupt enable - * @arg @ref LCD_FLAG_UDD Update display done interrupt - * @retval The new state of the LCD_IT - */ -it_status_t ald_lcd_get_flag_status(lcd_handle_t *hperh, lcd_flag_t flag) -{ - assert_param(IS_LCD_PERH_TYPE(hperh->perh)); - assert_param(IS_LCD_FLAG_TYPE(flag)); - - return hperh->perh->IF & flag ? SET : RESET; -} - -/** - * @brief Clear interrupt state flag - * @param hperh: Pointer to a lcd_handle_t structure that contains - * the configuration information for the specified LCD. - * @param flag: Specifies the interrupt type to clear - * This parameter can be one of the following values: - * @arg @ref LCD_FLAG_SOF Start of frame interrupt enable - * @arg @ref LCD_FLAG_UDD Update display done interrupt - * @retval Status, see @ref ald_status_t. - */ -ald_status_t ald_lcd_clear_flag_status(lcd_handle_t *hperh, lcd_flag_t flag) -{ - assert_param(IS_LCD_PERH_TYPE(hperh->perh)); - assert_param(IS_LCD_FLAG_TYPE(flag)); - - __LOCK(hperh); - WRITE_REG(hperh->perh->IFCR, flag); - __UNLOCK(hperh); - - return OK; -} - -/** - * @brief This function handles LCD event interrupt request. - * @param hperh: Pointer to a lcd_handle_t structure that contains - * the configuration information for the specified LCD. - * @retval None - */ -void ald_lcd_irq_handler(lcd_handle_t *hperh) -{ - if (ald_lcd_get_flag_status(hperh, LCD_FLAG_UDD)) { - ald_lcd_clear_flag_status(hperh, LCD_FLAG_UDD); - - if (hperh->display_cplt_cbk) - hperh->display_cplt_cbk(hperh); - } - - if (ald_lcd_get_flag_status(hperh, LCD_FLAG_SOF)) { - ald_lcd_clear_flag_status(hperh, LCD_FLAG_SOF); - - if (hperh->frame_start_cbk) - hperh->frame_start_cbk(hperh); - } - - return; -} -/** - * @} - */ -/** - * @} - */ -#endif /* ALD_LCD */ -/** - * @} - */ -/** - * @} - */ diff --git a/bsp/essemi/es32f0334/libraries/ES32F033x_ALD_StdPeriph_Driver/Source/ald_lptim.c b/bsp/essemi/es32f0334/libraries/ES32F033x_ALD_StdPeriph_Driver/Source/ald_lptim.c deleted file mode 100644 index 5b615f0b77..0000000000 --- a/bsp/essemi/es32f0334/libraries/ES32F033x_ALD_StdPeriph_Driver/Source/ald_lptim.c +++ /dev/null @@ -1,801 +0,0 @@ -/** - ********************************************************************************* - * - * @file ald_lptim.c - * @brief LPTIM module driver. - * This is the common part of the LPTIM initialization - * - * @version V1.0 - * @date 09 Nov 2017 - * @author AE Team - * @note - * - * Copyright (C) Shanghai Eastsoft Microelectronics Co. Ltd. All rights reserved. - * - ********************************************************************************* - */ - -#include "ald_lptim.h" - - -/** @addtogroup ES32FXXX_ALD - * @{ - */ - -/** @defgroup LPTIM LPTIM - * @brief LPTIM module driver - * @{ - */ -#ifdef ALD_LPTIM - -/** @defgroup LPTIM_Public_Functions LPTIM Public Functions - * @{ - */ - -/** @defgroup LPTIM_Public_Functions_Group1 Initialization functions - * @brief Initialization and Configuration functions - * - * @{ - */ -/** - * @brief Reset the LPTIM peripheral. - * @param hperh: Pointer to a lptim_handle_t. - * @retval None - */ -void ald_lptim_reset(lptim_handle_t *hperh) -{ - assert_param(IS_LPTIM(hperh->perh)); - - hperh->state = LPTIM_STATE_BUSY; - LPTIM_DISABLE(hperh); - hperh->state = LPTIM_STATE_RESET; - __UNLOCK(hperh); - - return; -} - -/** - * @brief Configure the LPTIM trigger mode according to the specified parameters in - * the lptim_trigger_init_t. - * @param hperh: Pointer to a lptim_handle_t. - * @param config: Pointer to a lptim_trigger_init_t. - * @retval None - */ -void ald_lptim_trigger_config(lptim_handle_t *hperh, lptim_trigger_init_t *config) -{ - assert_param(IS_LPTIM(hperh->perh)); - assert_param(IS_LPTIM_TRIGEN(config->mode)); - assert_param(IS_LPTIM_TRIGSEL(config->sel)); - - MODIFY_REG(hperh->perh->CON0, LP16T_CON0_TRIGEN_MSK, (config->mode) << LP16T_CON0_TRIGEN_POSS); - MODIFY_REG(hperh->perh->CON0, LP16T_CON0_TRIGSEL_MSK, (config->sel) << LP16T_CON0_TRIGSEL_POSS); - - return; -} - -/** - * @brief Configure the LPTIM clock source according to the specified parameters in - * the lptim_clock_source_init_t. - * @param hperh: Pointer to a lptim_handle_t. - * @param config: Pointer to a lptim_clock_source_init_t. - * @retval None - */ -void ald_lptim_clock_source_config(lptim_handle_t *hperh, lptim_clock_source_init_t *config) -{ - assert_param(IS_LPTIM(hperh->perh)); - assert_param(IS_LPTIM_CKSEL(config->sel)); - assert_param(IS_LPTIM_CKPOL(config->polarity)); - - MODIFY_REG(hperh->perh->CON0, LP16T_CON0_CKSEL_MSK, (config->sel) << LP16T_CON0_CKSEL_POS); - MODIFY_REG(hperh->perh->CON0, LP16T_CON0_CKPOL_MSK, (config->polarity) << LP16T_CON0_CKPOL_POS); - - return; -} - -/** - * @brief Configure the LPTIM trigger filter parameter according to - * the specified parameters in the lptim_trgflt_t. - * @param hperh: Pointer to a lptim_handle_t. - * @param flt: Pointer to a lptim_trgflt_t. - * @retval None - */ -void ald_lptim_trigger_filter_config(lptim_handle_t *hperh, lptim_trgflt_t flt) -{ - assert_param(IS_LPTIM(hperh->perh)); - assert_param(IS_LPTIM_TRGFLT(flt)); - - MODIFY_REG(hperh->perh->CON0, LP16T_CON0_TRGFLT_MSK, flt << LP16T_CON0_TRGFLT_POSS); - - return; -} - -/** - * @brief Configure the LPTIM clock filter parameter according to - * the specified parameters in the lptim_ckflt_t. - * @param hperh: Pointer to a lptim_handle_t. - * @param flt: Pointer to a lptim_ckflt_t. - * @retval None - */ -void ald_lptim_clock_filter_config(lptim_handle_t *hperh, lptim_ckflt_t flt) -{ - assert_param(IS_LPTIM(hperh->perh)); - assert_param(IS_LPTIM_CKFLT(flt)); - - MODIFY_REG(hperh->perh->CON0, LP16T_CON0_CKFLT_MSK, flt << LP16T_CON0_CKFLT_POSS); - - return; -} -/** - * @} - */ - -/** @defgroup LPTIM_Public_Functions_Group2 LPTIM base functions - * @brief LPTIM base functions - * - * @verbatim - ============================================================================== - ##### Low Pow Time Base functions ##### - ============================================================================== - [..] - This section provides functions allowing to: - (+) Initialize the LPTIM . - (+) Start the LPTIM. - (+) Stop the LPTIM. - (+) Start the LPTIM and enable interrupt. - (+) Stop the LPTIM and disable interrupt. - - @endverbatim - * @{ - */ -/** - * @brief Initializes the TIM according to the specified - * parameters in the tim_handle_t. - * @param hperh: LPTIM handle - * @retval Status, see @ref ald_status_t. - */ -ald_status_t ald_lptim_base_init(lptim_handle_t *hperh) -{ - assert_param(IS_LPTIM(hperh->perh)); - assert_param(IS_LPTIM_PRESC(hperh->init.psc)); - - __LOCK(hperh); - hperh->state = LPTIM_STATE_BUSY; - - ald_cmu_lptim0_clock_select(hperh->init.clock); - - WRITE_REG(hperh->perh->UPDATE, 1); - MODIFY_REG(hperh->perh->CON0, LP16T_CON0_WAVE_MSK, LPTIM_WAVE_NONE << LP16T_CON0_WAVE_POSS); - MODIFY_REG(hperh->perh->CON0, LP16T_CON0_PRESC_MSK, (hperh->init.psc) << LP16T_CON0_PRESC_POSS); - WRITE_REG(hperh->perh->ARR, hperh->init.arr); - WRITE_REG(hperh->perh->CMP, hperh->init.cmp); - WRITE_REG(hperh->perh->UPDATE, 0); - - while (READ_BIT(hperh->perh->SYNCSTAT, LP16T_SYNCSTAT_ARRWBSY_MSK)); - while (READ_BIT(hperh->perh->SYNCSTAT, LP16T_SYNCSTAT_CMPWBSY_MSK)); - - hperh->state = LPTIM_STATE_READY; - __UNLOCK(hperh); - return OK; -} - -/** - * @brief Starts the LPTIM. - * @param hperh: LPTIM handle - * @retval None - */ -void ald_lptim_base_start(lptim_handle_t *hperh) -{ - assert_param(IS_LPTIM(hperh->perh)); - assert_param(IS_LPTIM_MODE(hperh->init.mode)); - - LPTIM_ENABLE(hperh); - while (READ_BIT(hperh->perh->SYNCSTAT, LP16T_SYNCSTAT_CON1WBSY_MSK)); - - if (hperh->init.mode == LPTIM_MODE_CONTINUOUS) - LPTIM_CNTSTART(hperh); - else - LPTIM_SNGSTART(hperh); - - while (READ_BIT(hperh->perh->SYNCSTAT, LP16T_SYNCSTAT_CON1WBSY_MSK)); - return; -} - -/** - * @brief Stops the LPTIM. - * @param hperh: LPTIM handle - * @retval None - */ -void ald_lptim_base_stop(lptim_handle_t *hperh) -{ - assert_param(IS_LPTIM(hperh->perh)); - - LPTIM_DISABLE(hperh); - while (READ_BIT(hperh->perh->SYNCSTAT, LP16T_SYNCSTAT_CON1WBSY_MSK)); - return; -} - -/** - * @brief Starts the LPTIM in interrupt mode. - * @param hperh: LPTIM handle - * @retval None - */ -void ald_lptim_base_start_by_it(lptim_handle_t *hperh) -{ - assert_param(IS_LPTIM(hperh->perh)); - assert_param(IS_LPTIM_MODE(hperh->init.mode)); - - ald_lptim_interrupt_config(hperh, LPTIM_IT_ARRMAT, ENABLE); - LPTIM_ENABLE(hperh); - while (READ_BIT(hperh->perh->SYNCSTAT, LP16T_SYNCSTAT_CON1WBSY_MSK)); - - if (hperh->init.mode == LPTIM_MODE_CONTINUOUS) - LPTIM_CNTSTART(hperh); - else - LPTIM_SNGSTART(hperh); - - while (READ_BIT(hperh->perh->SYNCSTAT, LP16T_SYNCSTAT_CON1WBSY_MSK)); - return; -} - -/** - * @brief Stops the LPTIM Output toggle in interrupt mode. - * @param hperh: LPTIM handle - * @retval None - */ -void ald_lptim_base_stop_by_it(lptim_handle_t *hperh) -{ - assert_param(IS_LPTIM(hperh->perh)); - - ald_lptim_interrupt_config(hperh, LPTIM_IT_ARRMAT, DISABLE); - LPTIM_DISABLE(hperh); - while (READ_BIT(hperh->perh->SYNCSTAT, LP16T_SYNCSTAT_CON1WBSY_MSK)); - return; -} -/** - * @} - */ - -/** @defgroup LPTIM_Public_Functions_Group3 LPTIM output toggle functions - * @brief LPTIM output toggle functions - * - * @verbatim - ============================================================================== - ##### Time Output Compare functions ##### - ============================================================================== - [..] - This section provides functions allowing to: - (+) Initialize the LPTIM Output Toggle. - (+) Start the LPTIM Output Toggle. - (+) Stop the LPTIM Output Toggle. - (+) Start the LPTIM Output Toggle and enable interrupt. - (+) Stop the LPTIM Output Toggle and disable interrupt. - - @endverbatim - * @{ - */ -/** - * @brief Initializes the TIM Output toggle according to the specified - * parameters in the tim_handle_t. - * @param hperh: LPTIM handle - * @retval Status, see @ref ald_status_t. - */ -ald_status_t ald_lptim_toggle_init(lptim_handle_t *hperh) -{ - assert_param(IS_LPTIM(hperh->perh)); - assert_param(IS_LPTIM_PRESC(hperh->init.psc)); - - __LOCK(hperh); - hperh->state = LPTIM_STATE_BUSY; - - ald_cmu_lptim0_clock_select(hperh->init.clock); - - WRITE_REG(hperh->perh->UPDATE, 1); - MODIFY_REG(hperh->perh->CON0, LP16T_CON0_WAVE_MSK, LPTIM_WAVE_TOGGLE << LP16T_CON0_WAVE_POSS); - MODIFY_REG(hperh->perh->CON0, LP16T_CON0_PRESC_MSK, (hperh->init.psc) << LP16T_CON0_PRESC_POSS); - WRITE_REG(hperh->perh->ARR, hperh->init.arr); - WRITE_REG(hperh->perh->CMP, hperh->init.cmp); - WRITE_REG(hperh->perh->UPDATE, 0); - - while (READ_BIT(hperh->perh->SYNCSTAT, LP16T_SYNCSTAT_ARRWBSY_MSK)); - while (READ_BIT(hperh->perh->SYNCSTAT, LP16T_SYNCSTAT_CMPWBSY_MSK)); - - hperh->state = LPTIM_STATE_READY; - __UNLOCK(hperh); - return OK; -} - -/** - * @brief Starts the LPTIM Output toggle. - * @param hperh: LPTIM handle - * @retval None - */ -void ald_lptim_toggle_start(lptim_handle_t *hperh) -{ - assert_param(IS_LPTIM(hperh->perh)); - assert_param(IS_LPTIM_MODE(hperh->init.mode)); - - LPTIM_ENABLE(hperh); - while (READ_BIT(hperh->perh->SYNCSTAT, LP16T_SYNCSTAT_CON1WBSY_MSK)); - - if (hperh->init.mode == LPTIM_MODE_CONTINUOUS) - LPTIM_CNTSTART(hperh); - else - LPTIM_SNGSTART(hperh); - - while (READ_BIT(hperh->perh->SYNCSTAT, LP16T_SYNCSTAT_CON1WBSY_MSK)); - return; -} - -/** - * @brief Stops the LPTIM Output toggle. - * @param hperh: LPTIM handle - * @retval None - */ -void ald_lptim_toggle_stop(lptim_handle_t *hperh) -{ - assert_param(IS_LPTIM(hperh->perh)); - - LPTIM_DISABLE(hperh); - while (READ_BIT(hperh->perh->SYNCSTAT, LP16T_SYNCSTAT_CON1WBSY_MSK)); - return; -} - -/** - * @brief Starts the LPTIM Output toggle in interrupt mode. - * @param hperh: LPTIM handle - * @retval None - */ -void ald_lptim_toggle_start_by_it(lptim_handle_t *hperh) -{ - assert_param(IS_LPTIM(hperh->perh)); - assert_param(IS_LPTIM_MODE(hperh->init.mode)); - - ald_lptim_interrupt_config(hperh, LPTIM_IT_ARRMAT, ENABLE); - LPTIM_ENABLE(hperh); - while (READ_BIT(hperh->perh->SYNCSTAT, LP16T_SYNCSTAT_CON1WBSY_MSK)); - - if (hperh->init.mode == LPTIM_MODE_CONTINUOUS) - LPTIM_CNTSTART(hperh); - else - LPTIM_SNGSTART(hperh); - - while (READ_BIT(hperh->perh->SYNCSTAT, LP16T_SYNCSTAT_CON1WBSY_MSK)); - return; -} - -/** - * @brief Stops the LPTIM Output toggle in interrupt mode. - * @param hperh: LPTIM handle - * @retval None - */ -void ald_lptim_toggle_stop_by_it(lptim_handle_t *hperh) -{ - assert_param(IS_LPTIM(hperh->perh)); - - ald_lptim_interrupt_config(hperh, LPTIM_IT_ARRMAT, DISABLE); - LPTIM_DISABLE(hperh); - while (READ_BIT(hperh->perh->SYNCSTAT, LP16T_SYNCSTAT_CON1WBSY_MSK)); - return; -} -/** - * @} - */ - -/** @defgroup LPTIM_Public_Functions_Group4 LPTIM output pulse functions - * @brief LPTIM output pulse functions - * - * @verbatim - ============================================================================== - ##### Time Output Compare functions ##### - ============================================================================== - [..] - This section provides functions allowing to: - (+) Initialize the LPTIM Output pulse. - (+) Start the LPTIM Output pulse. - (+) Stop the LPTIM Output pulse. - (+) Start the LPTIM Output pulse and enable interrupt. - (+) Stop the LPTIM Output pulse and disable interrupt. - - @endverbatim - * @{ - */ -/** - * @brief Initializes the TIM Output pulse according to the specified - * parameters in the tim_handle_t. - * @param hperh: LPTIM handle - * @retval Status, see @ref ald_status_t. - */ -ald_status_t ald_lptim_pulse_init(lptim_handle_t *hperh) -{ - assert_param(IS_LPTIM(hperh->perh)); - assert_param(IS_LPTIM_PRESC(hperh->init.psc)); - - __LOCK(hperh); - hperh->state = LPTIM_STATE_BUSY; - ald_cmu_lptim0_clock_select(hperh->init.clock); - - WRITE_REG(hperh->perh->UPDATE, 1); - MODIFY_REG(hperh->perh->CON0, LP16T_CON0_WAVE_MSK, LPTIM_WAVE_PULSE << LP16T_CON0_WAVE_POSS); - MODIFY_REG(hperh->perh->CON0, LP16T_CON0_PRESC_MSK, (hperh->init.psc) << LP16T_CON0_PRESC_POSS); - WRITE_REG(hperh->perh->ARR, hperh->init.arr); - WRITE_REG(hperh->perh->CMP, hperh->init.cmp); - WRITE_REG(hperh->perh->UPDATE, 0); - - while (READ_BIT(hperh->perh->SYNCSTAT, LP16T_SYNCSTAT_ARRWBSY_MSK)); - while (READ_BIT(hperh->perh->SYNCSTAT, LP16T_SYNCSTAT_CMPWBSY_MSK)); - - hperh->state = LPTIM_STATE_READY; - __UNLOCK(hperh); - return OK; -} - -/** - * @brief Starts the LPTIM Output pulse. - * @param hperh: LPTIM handle - * @retval None - */ -void ald_lptim_pulse_start(lptim_handle_t *hperh) -{ - assert_param(IS_LPTIM(hperh->perh)); - assert_param(IS_LPTIM_MODE(hperh->init.mode)); - - LPTIM_ENABLE(hperh); - while (READ_BIT(hperh->perh->SYNCSTAT, LP16T_SYNCSTAT_CON1WBSY_MSK)); - - if (hperh->init.mode == LPTIM_MODE_CONTINUOUS) - LPTIM_CNTSTART(hperh); - else - LPTIM_SNGSTART(hperh); - - while (READ_BIT(hperh->perh->SYNCSTAT, LP16T_SYNCSTAT_CON1WBSY_MSK)); - return; -} - -/** - * @brief Stops the LPTIM Output pulse. - * @param hperh: LPTIM handle - * @retval None - */ -void ald_lptim_pulse_stop(lptim_handle_t *hperh) -{ - assert_param(IS_LPTIM(hperh->perh)); - - LPTIM_DISABLE(hperh); - while (READ_BIT(hperh->perh->SYNCSTAT, LP16T_SYNCSTAT_CON1WBSY_MSK)); - - return; -} - -/** - * @brief Starts the LPTIM Output pulse in interrupt mode. - * @param hperh: LPTIM handle - * @retval None - */ -void ald_lptim_pulse_start_by_it(lptim_handle_t *hperh) -{ - assert_param(IS_LPTIM(hperh->perh)); - assert_param(IS_LPTIM_MODE(hperh->init.mode)); - - ald_lptim_interrupt_config(hperh, LPTIM_IT_ARRMAT, ENABLE); - LPTIM_ENABLE(hperh); - while (READ_BIT(hperh->perh->SYNCSTAT, LP16T_SYNCSTAT_CON1WBSY_MSK)); - - if (hperh->init.mode == LPTIM_MODE_CONTINUOUS) - LPTIM_CNTSTART(hperh); - else - LPTIM_SNGSTART(hperh); - - while (READ_BIT(hperh->perh->SYNCSTAT, LP16T_SYNCSTAT_CON1WBSY_MSK)); - return; -} - -/** - * @brief Stops the LPTIM Output pulse in interrupt mode. - * @param hperh: LPTIM handle - * @retval None - */ -void ald_lptim_pulse_stop_by_it(lptim_handle_t *hperh) -{ - assert_param(IS_LPTIM(hperh->perh)); - - ald_lptim_interrupt_config(hperh, LPTIM_IT_ARRMAT, DISABLE); - LPTIM_DISABLE(hperh); - while (READ_BIT(hperh->perh->SYNCSTAT, LP16T_SYNCSTAT_CON1WBSY_MSK)); - - return; -} -/** - * @} - */ - -/** @defgroup LPTIM_Public_Functions_Group5 LPTIM output pwm functions - * @brief LPTIM output pwm functions - * - * @verbatim - ============================================================================== - ##### Time Output Compare functions ##### - ============================================================================== - [..] - This section provides functions allowing to: - (+) Initialize the LPTIM Output pwm. - (+) Start the LPTIM Output pwm. - (+) Stop the LPTIM Output pwm. - (+) Start the LPTIM Output pwm and enable interrupt. - (+) Stop the LPTIM Output pwm and disable interrupt. - - @endverbatim - * @{ - */ -/** - * @brief Initializes the TIM Output pwm according to the specified - * parameters in the tim_handle_t. - * @param hperh: LPTIM handle - * @retval Status, see @ref ald_status_t. - */ -ald_status_t ald_lptim_pwm_init(lptim_handle_t *hperh) -{ - assert_param(IS_LPTIM(hperh->perh)); - assert_param(IS_LPTIM_PRESC(hperh->init.psc)); - - __LOCK(hperh); - hperh->state = LPTIM_STATE_BUSY; - - WRITE_REG(hperh->perh->UPDATE, 1); - MODIFY_REG(hperh->perh->CON0, LP16T_CON0_WAVE_MSK, LPTIM_WAVE_PWM << LP16T_CON0_WAVE_POSS); - MODIFY_REG(hperh->perh->CON0, LP16T_CON0_PRESC_MSK, (hperh->init.psc) << LP16T_CON0_PRESC_POSS); - WRITE_REG(hperh->perh->ARR, hperh->init.arr); - WRITE_REG(hperh->perh->CMP, hperh->init.cmp); - WRITE_REG(hperh->perh->UPDATE, 0); - - while (READ_BIT(hperh->perh->SYNCSTAT, LP16T_SYNCSTAT_ARRWBSY_MSK)); - while (READ_BIT(hperh->perh->SYNCSTAT, LP16T_SYNCSTAT_CMPWBSY_MSK)); - - hperh->state = LPTIM_STATE_READY; - __UNLOCK(hperh); - return OK; -} - -/** - * @brief Starts the LPTIM Output pwm. - * @param hperh: LPTIM handle - * @retval None - */ -void ald_lptim_pwm_start(lptim_handle_t *hperh) -{ - assert_param(IS_LPTIM(hperh->perh)); - assert_param(IS_LPTIM_MODE(hperh->init.mode)); - - LPTIM_ENABLE(hperh); - while (READ_BIT(hperh->perh->SYNCSTAT, LP16T_SYNCSTAT_CON1WBSY_MSK)); - - if (hperh->init.mode == LPTIM_MODE_CONTINUOUS) - LPTIM_CNTSTART(hperh); - else - LPTIM_SNGSTART(hperh); - - while (READ_BIT(hperh->perh->SYNCSTAT, LP16T_SYNCSTAT_CON1WBSY_MSK)); - return; -} - -/** - * @brief Stops the LPTIM Output pwm. - * @param hperh: LPTIM handle - * @retval None - */ -void ald_lptim_pwm_stop(lptim_handle_t *hperh) -{ - assert_param(IS_LPTIM(hperh->perh)); - - LPTIM_DISABLE(hperh); - while (READ_BIT(hperh->perh->SYNCSTAT, LP16T_SYNCSTAT_CON1WBSY_MSK)); - - return; -} - -/** - * @brief Starts the LPTIM Output pwm in interrupt mode. - * @param hperh: LPTIM handle - * @retval None - */ -void ald_lptim_pwm_start_by_it(lptim_handle_t *hperh) -{ - assert_param(IS_LPTIM(hperh->perh)); - assert_param(IS_LPTIM_MODE(hperh->init.mode)); - - ald_lptim_interrupt_config(hperh, LPTIM_IT_CMPMAT, ENABLE); - LPTIM_ENABLE(hperh); - while (READ_BIT(hperh->perh->SYNCSTAT, LP16T_SYNCSTAT_CON1WBSY_MSK)); - - if (hperh->init.mode == LPTIM_MODE_CONTINUOUS) - LPTIM_CNTSTART(hperh); - else - LPTIM_SNGSTART(hperh); - - while (READ_BIT(hperh->perh->SYNCSTAT, LP16T_SYNCSTAT_CON1WBSY_MSK)); - return; -} - -/** - * @brief Stops the LPTIM Output pwm in interrupt mode. - * @param hperh: LPTIM handle - * @retval None - */ -void ald_lptim_pwm_stop_by_it(lptim_handle_t *hperh) -{ - assert_param(IS_LPTIM(hperh->perh)); - - ald_lptim_interrupt_config(hperh, LPTIM_IT_CMPMAT, DISABLE); - LPTIM_DISABLE(hperh); - while (READ_BIT(hperh->perh->SYNCSTAT, LP16T_SYNCSTAT_CON1WBSY_MSK)); - - return; -} -/** - * @} - */ - - -/** @defgroup LPTIM_Public_Functions_Group6 Control functions - * @brief LPTIM Control functions - * - * @{ - */ -/** - * @brief This function handles LPTIM interrupts requests. - * @param hperh: LPTIM handle - * @retval None - */ -void ald_lptim_irq_handler(lptim_handle_t *hperh) -{ - assert_param(IS_LPTIM(hperh->perh)); - - /* Output compare event */ - if (((ald_lptim_get_it_status(hperh, LPTIM_IT_CMPMAT)) != RESET) && - ((ald_lptim_get_flag_status(hperh, LPTIM_FLAG_CMPMAT)) != RESET)) { - ald_lptim_clear_flag_status(hperh, LPTIM_FLAG_CMPMAT); - - if (hperh->cmp_cbk) - hperh->cmp_cbk(hperh); - } - - /* Output update event */ - if (((ald_lptim_get_it_status(hperh, LPTIM_IT_ARRMAT)) != RESET) && - ((ald_lptim_get_flag_status(hperh, LPTIM_FLAG_ARRMAT)) != RESET)) { - ald_lptim_clear_flag_status(hperh, LPTIM_FLAG_ARRMAT); - - if (hperh->update_cbk) - hperh->update_cbk(hperh); - } - - /* Trigger event */ - if (((ald_lptim_get_it_status(hperh, LPTIM_IT_EXTTRIG)) != RESET) && - ((ald_lptim_get_flag_status(hperh, LPTIM_FLAG_EXTTRIG)) != RESET)) { - ald_lptim_clear_flag_status(hperh, LPTIM_FLAG_EXTTRIG); - - if (hperh->trig_cbk) - hperh->trig_cbk(hperh); - } - - return; -} - -/** - * @brief Enables or disables the specified LPTIM interrupts. - * @param hperh: Pointer to a lptim_handle_t structure that contains - * the configuration information for the specified LPTIM module. - * @param it: Specifies the SPI interrupt sources to be enabled or disabled. - * This parameter can be one of the @ref lptim_it_t. - * @param state: New status - * - ENABLE - * - DISABLE - * @retval None - */ -void ald_lptim_interrupt_config(lptim_handle_t *hperh, lptim_it_t it, type_func_t state) -{ - assert_param(IS_LPTIM(hperh->perh)); - assert_param(IS_LPTIM_IT(it)); - assert_param(IS_FUNC_STATE(state)); - - if (state == ENABLE) - SET_BIT(hperh->perh->IER, (uint32_t)it); - else - CLEAR_BIT(hperh->perh->IER, (uint32_t)it); - return; -} - -/** - * @brief Checks whether the specified LPTIM interrupt has occurred or not. - * @param hperh: Pointer to a lptim_handle_t structure that contains - * the configuration information for the specified LPTIM module. - * @param it: Specifies the LPTIM interrupt source to check. - * This parameter can be one of the @ref lptim_it_t. - * @retval Status - * - SET - * - RESET - */ -it_status_t ald_lptim_get_it_status(lptim_handle_t *hperh, lptim_it_t it) -{ - assert_param(IS_LPTIM(hperh->perh)); - assert_param(IS_LPTIM_IT(it)); - - if (READ_BIT(hperh->perh->IER, it)) - return SET; - - return RESET; -} - -/** @brief Check whether the specified LPTIM flag is set or not. - * @param hperh: Pointer to a lptim_handle_t structure that contains - * the configuration information for the specified LPTIM module. - * @param flag: specifies the flag to check. - * This parameter can be one of the @ref lptim_flag_t. - * @retval Status - * - SET - * - RESET - */ -flag_status_t ald_lptim_get_flag_status(lptim_handle_t *hperh, lptim_flag_t flag) -{ - assert_param(IS_LPTIM(hperh->perh)); - assert_param(IS_LPTIM_FLAG(flag)); - - if (READ_BIT(hperh->perh->ISR, flag)) - return SET; - - return RESET; -} - -/** @brief Clear the specified LPTIM pending flags. - * @param hperh: Pointer to a lptim_handle_t structure that contains - * the configuration information for the specified LPTIM module. - * @param flag: specifies the flag to check. - * This parameter can be one of the @ref lptim_flag_t. - * @retval None - */ -void ald_lptim_clear_flag_status(lptim_handle_t *hperh, lptim_flag_t flag) -{ - assert_param(IS_LPTIM(hperh->perh)); - assert_param(IS_LPTIM_FLAG(flag)); - - WRITE_REG(hperh->perh->IFC, (uint32_t)flag); - return; -} -/** - * @} - */ - -/** @defgroup LPTIM_Public_Functions_Group7 Peripheral State functions - * @brief Peripheral State functions - * - * @verbatim - ============================================================================== - ##### Peripheral State functions ##### - ============================================================================== - [..] - This subsection permit to get in run-time the status of the peripheral. - - @endverbatim - * @{ - */ - -/** - * @brief Return the LPTIM state - * @param hperh: LPTIM handle - * @retval LPTIM peripheral state - */ -lptim_state_t ald_lptim_get_state(lptim_handle_t *hperh) -{ - return hperh->state; -} -/** - * @} - */ -/** - * @} - */ -#endif /* ALD_LPTIM */ -/** - * @} - */ -/** - * @} - */ diff --git a/bsp/essemi/es32f0334/libraries/ES32F033x_ALD_StdPeriph_Driver/Source/ald_lpuart.c b/bsp/essemi/es32f0334/libraries/ES32F033x_ALD_StdPeriph_Driver/Source/ald_lpuart.c deleted file mode 100644 index 8a296925c1..0000000000 --- a/bsp/essemi/es32f0334/libraries/ES32F033x_ALD_StdPeriph_Driver/Source/ald_lpuart.c +++ /dev/null @@ -1,1192 +0,0 @@ -/** - ********************************************************************************* - * - * @file ald_lpuart.c - * @brief Low Power UART module driver. - * This file provides firmware functions to manage the following - * functionalities of the Low Power Universal Asynchronous Receiver - * Transmitter (LPUART) peripheral: - * + Initialization and Configuration functions - * + IO operation functions - * + Peripheral Control functions - * + Peripheral State and Errors functions - * - * @version V1.0 - * @date 30 May 2017 - * @author AE Team - * @note - * - * Copyright (C) Shanghai Eastsoft Microelectronics Co. Ltd. All rights reserved. - * - ********************************************************************************* - * @verbatim - ============================================================================== - ##### How to use this driver ##### - ============================================================================== - [..] - The LPUART driver can be used as follows: - - (#) Declare a lpuart_handle_t handle structure. - - (#) Initialize the LPUART resources: - (##) Enable the LPUART interface clock. - (##) LPUART pins configuration: - (+++) Enable the clock for the LPUART GPIOs. - (+++) Configure the LPUART pins (TX as alternate function pull-up, RX as alternate function Input). - (##) NVIC configuration if you need to use interrupt process (ald_lpuart_send_by_it() - and ald_lpuart_recv_by_it() APIs): - (+++) Configure the LPUART interrupt priority. - (+++) Enable the NVIC LPUART IRQ handle. - (##) DMA Configuration if you need to use DMA process (ald_lpuart_send_by_dma() - and ald_lpuart_recv_by_dma() APIs): - (+++) Declare a DMA handle structure for the Tx/Rx channel. - (+++) Enable the DMAx interface clock. - (+++) Configure the declared DMA handle structure with the required - Tx/Rx parameters. - (+++) Configure the DMA Tx/Rx channel. - (+++) Associate the initialized DMA handle to the LPUART DMA Tx/Rx handle. - - (#) Program the Baud Rate, Word Length, Stop Bit, Parity, Hardware - flow control and Mode(Receiver/Transmitter) in the hperh Init structure. - - (#) Initialize the LPUART registers by calling the ald_lpuart_init() API. - - [..] - Three operation modes are available within this driver: - - *** Polling mode IO operation *** - ================================= - [..] - (+) Send an amount of data in blocking mode using ald_lpuart_send() - (+) Receive an amount of data in blocking mode using ald_lpuart_recv() - - *** Interrupt mode IO operation *** - =================================== - [..] - (+) Send an amount of data in non blocking mode using ald_lpuart_send_by_it() - (+) At transmission end of transfer hperh->tx_cplt_cbk() is executed and user can - add his own code by customization of function pointer hperh->tx_cplt_cbk() - (+) Receive an amount of data in non blocking mode using ald_lpuart_recv_by_it() - (+) At reception end of transfer hperh->rx_cplt_cbk() is executed and user can - add his own code by customization of function pointer hperh->rx_cplt_cbk() - (+) In case of transfer Error, hperh->error_cbk() function is executed and user can - add his own code by customization of function pointer hperh->error_cbk() - - *** DMA mode IO operation *** - ============================== - [..] - (+) Send an amount of data in non blocking mode (DMA) using ald_lpuart_send_by_dma() - (+) At transmission end of transfer hperh->tx_cplt_cbk() is executed and user can - add his own code by customization of function pointer hperh->tx_cplt_cbk() - (+) Receive an amount of data in non blocking mode (DMA) using ald_lpuart_recv_by_dma() - (+) At reception end of transfer hperh->rx_cplt_cbk() is executed and user can - add his own code by customization of function pointer hperh->rx_cplt_cbk() - (+) In case of transfer Error, hperh->error_cbk() function is executed and user can - add his own code by customization of function pointer hperh->error_cbk() - (+) Pause the DMA Transfer using ald_lpuart_dma_pause() - (+) Resume the DMA Transfer using ald_lpuart_dma_resume() - (+) Stop the DMA Transfer using ald_lpuart_dma_stop() - - @endverbatim - ****************************************************************************** - */ - -#include "ald_lpuart.h" - - -/** @addtogroup ES32FXXX_ALD - * @{ - */ - -/** @defgroup LPUART LPUART - * @brief Low Power UART module driver - * @{ - */ -#ifdef ALD_LPUART - -/** @defgroup LPUART_Private_Functions LPUART Private Functions - * @brief LPUART Private functions - * @{ - */ - -#ifdef ALD_DMA -/** - * @brief DMA LPUART transmit process complete callback. - * @param arg: Pointer to a lpuart_handle_t structure that contains - * the configuration information for the specified LPUART module. - * @retval None - */ -static void lpuart_dma_send_cplt(void *arg) -{ - lpuart_handle_t *hperh = (lpuart_handle_t *)arg; - - hperh->tx_count = 0; - ald_lpuart_dma_req_config(hperh, LPUART_DMA_REQ_TX, DISABLE); - ald_lpuart_interrupt_config(hperh, LPUART_IT_TC, ENABLE); -} - -/** - * @brief DMA LPUART receive process complete callback. - * @param arg: Pointer to a lpuart_handle_t structure that contains - * the configuration information for the specified LPUART module. - * @retval None - */ -static void lpuart_dma_recv_cplt(void *arg) -{ - lpuart_handle_t *hperh = (lpuart_handle_t *)arg; - - hperh->rx_count = 0; - ald_lpuart_dma_req_config(hperh, LPUART_DMA_REQ_RX, DISABLE); - CLEAR_BIT(hperh->state, LPUART_STATE_RX_MASK); - - if (hperh->rx_cplt_cbk) - hperh->rx_cplt_cbk(hperh); -} - -/** - * @brief DMA LPUART communication error callback. - * @param arg: Pointer to a lpuart_handle_t structure that contains - * the configuration information for the specified LPUART module. - * @retval None - */ -static void lpuart_dma_error(void *arg) -{ - lpuart_handle_t *hperh = (lpuart_handle_t *)arg; - - hperh->rx_count = 0; - hperh->tx_count = 0; - hperh->state = LPUART_STATE_READY; - hperh->err_code |= LPUART_ERROR_DMA; - - if (hperh->error_cbk) - hperh->error_cbk(hperh); -} -#endif - -/** - * @brief This function handles uart Communication Timeout. - * @param hperh: Pointer to a lpuart_handle_t structure that contains - * the configuration information for the specified LPUART module. - * @param flag: specifies the uart flag to check. - * @param status: The new Flag status (SET or RESET). - * @param timeout: Timeout duration - * @retval Status, see @ref ald_status_t. - */ -static ald_status_t lpuart_wait_flag(lpuart_handle_t *hperh, lpuart_status_t flag, flag_status_t status, uint32_t timeout) -{ - uint32_t tick; - - if (timeout == 0) - return OK; - - tick = ald_get_tick(); - - /* Waiting for flag */ - while ((ald_lpuart_get_status(hperh, flag)) != status) { - if (((ald_get_tick()) - tick) > timeout) - return TIMEOUT; - } - - return OK; -} - -/** - * @brief Sends an amount of data in non blocking mode. - * @param hperh: Pointer to a lpuart_handle_t structure that contains - * the configuration information for the specified LPUART module. - * @retval Status, see @ref ald_status_t. - */ -static ald_status_t __lpuart_send_by_it(lpuart_handle_t *hperh) -{ - if ((hperh->state & LPUART_STATE_TX_MASK) == 0x0) - return BUSY; - - WRITE_REG(hperh->perh->TXDR, *hperh->tx_buf++); - - if (--hperh->tx_count == 0) { - ald_lpuart_interrupt_config(hperh, LPUART_IT_TBEMP, DISABLE); - ald_lpuart_interrupt_config(hperh, LPUART_IT_TC, ENABLE); - } - - return OK; -} - - -/** - * @brief Wraps up transmission in non blocking mode. - * @param hperh: Pointer to a lpuart_handle_t structure that contains - * the configuration information for the specified LPUART module. - * @retval Status, see @ref ald_status_t. - */ -static ald_status_t __lpuart_end_send_by_it(lpuart_handle_t *hperh) -{ - ald_lpuart_interrupt_config(hperh, LPUART_IT_TC, DISABLE); - CLEAR_BIT(hperh->state, LPUART_STATE_TX_MASK); - - if (hperh->tx_cplt_cbk) - hperh->tx_cplt_cbk(hperh); - - return OK; -} - -/** - * @brief Receives an amount of data in non blocking mode - * @param hperh: Pointer to a lpuart_handle_t structure that contains - * the configuration information for the specified LPUART module. - * @retval Status, see @ref ald_status_t. - */ -static ald_status_t __lpuart_recv_by_it(lpuart_handle_t *hperh) -{ - uint32_t tmp; - uint16_t i; - - if ((hperh->state & LPUART_STATE_RX_MASK) == 0x0) - return BUSY; - - do { - i = 10000; - tmp = hperh->perh->STAT & LPUART_STAT_RXPTR_MSK; - *hperh->rx_buf++ = (uint8_t)(hperh->perh->RXDR & 0xFF); - --hperh->rx_count; - - while (((hperh->perh->STAT & LPUART_STAT_RXPTR_MSK) != (uint32_t)(tmp - 1)) && (i--)); - } while (hperh->perh->STAT & LPUART_STAT_RXPTR_MSK); - - if (hperh->rx_count == 0) { - ald_lpuart_interrupt_config(hperh, LPUART_IT_RBR, DISABLE); - CLEAR_BIT(hperh->state, LPUART_STATE_RX_MASK); - - if (hperh->state == LPUART_STATE_READY) { - ald_lpuart_interrupt_config(hperh, LPUART_IT_PERR, DISABLE); - ald_lpuart_interrupt_config(hperh, LPUART_IT_FERR, DISABLE); - } - - if (hperh->rx_cplt_cbk) - hperh->rx_cplt_cbk(hperh); - } - - return OK; -} -/** - * @} - */ - -/** @defgroup LPUART_Public_Functions LPUART Public Functions - * @{ - */ - -/** @defgroup LPUART_Public_Functions_Group1 Initialization and Configuration functions - * @brief Initialization and Configuration functions - * -@verbatim -=============================================================================== - ##### Initialization and Configuration functions ##### - =============================================================================== - [..] - This subsection provides a set of functions allowing to initialize the LPUART - and configure LPUART param. - (+) For the LPUART only these parameters can be configured: - (++) Baud Rate - (++) Word Length - (++) Stop Bit - (++) Parity - (++) Hardware flow control - (+) For RS485 mode, user also need configure some parameters by - ald_lpuart_rs485_config(): - (++) Enable/disable normal point mode - (++) Enable/disable auto-address detect - (++) Enable/disable auto-direction - (++) Enable/disable address detect - (++) Enable/disable address for compare - - @endverbatim - * @{ - */ - -/** - * @brief Reset LPUART peripheral - * @param hperh: Pointer to a lpuart_handle_t structure that contains - * the configuration information for the specified LPUART module. - * @retval None - */ -void ald_lpuart_reset(lpuart_handle_t *hperh) -{ - WRITE_REG(hperh->perh->CON0, 0x3000); - WRITE_REG(hperh->perh->CON1, 0x4); - WRITE_REG(hperh->perh->CLKDIV, 0x0); - WRITE_REG(hperh->perh->FIFOCON, 0x0); - WRITE_REG(hperh->perh->IER, 0x0); - hperh->err_code = LPUART_ERROR_NONE; - hperh->state = LPUART_STATE_RESET; - - __UNLOCK(hperh); - return; -} - -/** - * @brief Initializes the LPUART according to the specified - * parameters in the lpuart_handle_t. - * @param hperh: Pointer to a lpuart_handle_t structure that contains - * the configuration information for the specified LPUART module. - * @retval None - */ -void ald_lpuart_init(lpuart_handle_t *hperh) -{ - uint32_t tmp; - - assert_param(IS_LPUART(hperh->perh)); - assert_param(IS_LPUART_BAUDRATE(hperh->init.baud)); - assert_param(IS_LPUART_WORD_LENGTH(hperh->init.word_length)); - assert_param(IS_LPUART_STOPBITS(hperh->init.stop_bits)); - assert_param(IS_LPUART_PARITY(hperh->init.parity)); - assert_param(IS_LPUART_MODE(hperh->init.mode)); - assert_param(IS_LPUART_HARDWARE_FLOW_CONTROL(hperh->init.fctl)); - - if ((hperh->init.clock != CMU_LP_PERH_CLOCK_SEL_LOSC) - && (hperh->init.clock != CMU_LP_PERH_CLOCK_SEL_LRC)) - hperh->init.clock = CMU_LP_PERH_CLOCK_SEL_LRC; - - ald_cmu_lpuart0_clock_select(hperh->init.clock); - ald_lpuart_reset(hperh); - LPUART_UPDATE_DISABLE(hperh); - - tmp = READ_REG(hperh->perh->CON0); - MODIFY_REG(tmp, LPUART_CON0_DATLENTH_MSK, hperh->init.word_length << LPUART_CON0_DATLENTH_POSS); - MODIFY_REG(tmp, LPUART_CON0_STPLENTH_MSK, hperh->init.stop_bits << LPUART_CON0_STPLENTH_POS); - - if (hperh->init.parity == LPUART_PARITY_NONE) - CLEAR_BIT(tmp, LPUART_CON0_PARCHKE_MSK); - else - SET_BIT(tmp, LPUART_CON0_PARCHKE_MSK); - - if (hperh->init.parity == LPUART_PARITY_EVEN) - SET_BIT(tmp, LPUART_CON0_EVENPARSEL_MSK); - else - CLEAR_BIT(tmp, LPUART_CON0_EVENPARSEL_MSK); - - MODIFY_REG(tmp, LPUART_CON0_ATRTSE_MSK, (hperh->init.fctl & 1) << LPUART_CON0_ATRTSE_POS); - MODIFY_REG(tmp, LPUART_CON0_ATCTSE_MSK, ((hperh->init.fctl >> 1) & 1) << LPUART_CON0_ATCTSE_POS); - WRITE_REG(hperh->perh->CON0, tmp); - WRITE_REG(hperh->perh->CLKDIV, (32768 << 8) / hperh->init.baud); - - if (hperh->init.mode == LPUART_MODE_IrDA) - CLEAR_BIT(hperh->perh->CON1, LPUART_CON1_IRRXINV_MSK); - - MODIFY_REG(hperh->perh->CON0, LPUART_CON0_MODESEL_MSK, hperh->init.mode << LPUART_CON0_MODESEL_POSS); - LPUART_UPDATE_ENABLE(hperh); - - while (hperh->perh->SYNCSTAT & 0xF) - ; - - hperh->state = LPUART_STATE_READY; - return; -} - -/** - * @brief Configure the RS485 mode according to the specified - * parameters in the lpuart_rs485_config_Typedef. - * @param hperh: Pointer to a lpuart_handle_t structure that contains - * the configuration information for the specified LPUART module. - * @param config: Specifies the RS485 parameters. - * @retval None - */ -void ald_lpuart_rs485_config(lpuart_handle_t *hperh, lpuart_rs485_config_t *config) -{ - uint32_t tmp; - - assert_param(IS_LPUART(hperh->perh)); - assert_param(IS_FUNC_STATE(config->RS485_NMM)); - assert_param(IS_FUNC_STATE(config->RS485_AAD)); - assert_param(IS_FUNC_STATE(config->RS485_AUD)); - assert_param(IS_FUNC_STATE(config->RS485_ADD_DET)); - - tmp = READ_REG(hperh->perh->CON1); - MODIFY_REG(tmp, LPUART_CON1_NMPMOD_MSK, config->RS485_NMM << LPUART_CON1_NMPMOD_POS); - MODIFY_REG(tmp, LPUART_CON1_ATADETE_MSK, config->RS485_AAD << LPUART_CON1_ATADETE_POS); - MODIFY_REG(tmp, LPUART_CON1_ATDIRM_MSK, config->RS485_AUD << LPUART_CON1_ATDIRM_POS); - MODIFY_REG(tmp, LPUART_CON1_ADETE_MSK, config->RS485_ADD_DET << LPUART_CON1_ADETE_POS); - MODIFY_REG(tmp, LPUART_CON1_ADDCMP_MSK, config->RS485_ADDCMP << LPUART_CON1_ADDCMP_POSS); - WRITE_REG(hperh->perh->CON1, tmp); - - return; -} - -/** - * @} - */ - -/** @defgroup LPUART_Public_Functions_Group2 IO operation functions - * @brief LPUART Transmit and Receive functions - * @verbatim - ============================================================================== - ##### IO operation functions ##### - ============================================================================== - [..] - This subsection provides a set of functions allowing to manage the LPUART data transfers. - - (#) There are two modes of transfer: - (++) Blocking mode: The communication is performed in polling mode. - The status of all data processing is returned by the same function - after finishing transfer. - (++) Non blocking mode: The communication is performed using Interrupts - or DMA, these APIs return the status. - The end of the data processing will be indicated through the - dedicated LPUART IRQ when using Interrupt mode or the DMA IRQ when - using DMA mode. - The hperh->tx_cplt_cbk(), hperh->rx_cplt_cbk() user callbacks - will be executed respectively at the end of the transmit or receive process. - The hperh->error_cbk() user callback will be executed when - a communication error is detected. - - (#) Blocking mode APIs are: - (++) ald_lpuart_send() - (++) ald_lpuart_recv() - - (#) Non Blocking mode APIs with Interrupt are: - (++) ald_lpuart_send_by_it() - (++) ald_lpuart_recv_by_it() - (++) ald_lpuart_irq_handler() - - (#) Non Blocking mode functions with DMA are: - (++) ald_lpuart_send_by_dma() - (++) ald_lpuart_recv_by_dma() - (++) ald_lpuart_dma_pause() - (++) ald_lpuart_dma_resume() - (++) ald_lpuart_dma_stop() - - (#) A set of Transfer Complete Callbacks are provided in non blocking mode: - (++) hperh->tx_cplt_cbk() - (++) hperh->rx_cplt_cbk() - (++) hperh->error_cbk() - - @endverbatim - * @{ - */ - -/** - * @brief Sends an amount of data in blocking mode. - * @param hperh: Pointer to a lpuart_handle_t structure that contains - * the configuration information for the specified LPUART module. - * @param buf: Pointer to data buffer - * @param size: Amount of data to be sent - * @param timeout: Timeout duration - * @retval Status, see @ref ald_status_t. - */ -ald_status_t ald_lpuart_send(lpuart_handle_t *hperh, uint8_t *buf, uint16_t size, uint32_t timeout) -{ - if ((hperh->state != LPUART_STATE_READY) && (hperh->state != LPUART_STATE_BUSY_RX)) - return BUSY; - - if ((buf == NULL) || (size == 0)) - return ERROR; - - __LOCK(hperh); - hperh->err_code = LPUART_ERROR_NONE; - SET_BIT(hperh->state, LPUART_STATE_TX_MASK); - - hperh->tx_size = size; - hperh->tx_count = size; - - while (hperh->tx_count-- > 0) { - if (lpuart_wait_flag(hperh, LPUART_STAT_TXEMP, SET, timeout) != OK) { - __UNLOCK(hperh); - hperh->state = LPUART_STATE_READY; - return TIMEOUT; - } - - WRITE_REG(hperh->perh->TXDR, *buf++); - - if (lpuart_wait_flag(hperh, LPUART_STAT_TXEMP, RESET, timeout) != OK) { - __UNLOCK(hperh); - hperh->state = LPUART_STATE_READY; - return TIMEOUT; - } - } - - if (lpuart_wait_flag(hperh, LPUART_STAT_TXIDLE, SET, timeout) != OK) { - __UNLOCK(hperh); - hperh->state = LPUART_STATE_READY; - return TIMEOUT; - } - - CLEAR_BIT(hperh->state, LPUART_STATE_TX_MASK); - __UNLOCK(hperh); - - return OK; -} - -/** - * @brief Receives an amount of data in blocking mode. - * @param hperh: Pointer to a lpuart_handle_t structure that contains - * the configuration information for the specified LPUART module. - * @param buf: Pointer to data buffer - * @param size: Amount of data to be received - * @param timeout: Timeout duration - * @retval Status, see @ref ald_status_t. - */ -ald_status_t ald_lpuart_recv(lpuart_handle_t *hperh, uint8_t *buf, uint16_t size, uint32_t timeout) -{ - if ((hperh->state != LPUART_STATE_READY) && (hperh->state != LPUART_STATE_BUSY_TX)) - return BUSY; - - if ((buf == NULL ) || (size == 0)) - return ERROR; - - __LOCK(hperh); - - hperh->err_code = LPUART_ERROR_NONE; - SET_BIT(hperh->state, LPUART_STATE_RX_MASK); - - hperh->rx_size = size; - hperh->rx_count = size; - - /* Check the remain data to be received */ - while (hperh->rx_count-- > 0) { - if (lpuart_wait_flag(hperh, LPUART_STAT_RXEMP, RESET, timeout) != OK) { - __UNLOCK(hperh); - hperh->state = LPUART_STATE_READY; - return TIMEOUT; - } - - *buf++ = (uint8_t)(hperh->perh->RXDR & 0xFF); - } - - CLEAR_BIT(hperh->state, LPUART_STATE_RX_MASK); - __UNLOCK(hperh); - - return OK; -} - -/** - * @brief Sends an amount of data in non blocking mode. - * @param hperh: Pointer to a lpuart_handle_t structure that contains - * the configuration information for the specified LPUART module. - * @param buf: Pointer to data buffer - * @param size: Amount of data to be sent - * @retval Status, see @ref ald_status_t. - */ -ald_status_t ald_lpuart_send_by_it(lpuart_handle_t *hperh, uint8_t *buf, uint16_t size) -{ - if ((hperh->state != LPUART_STATE_READY) && (hperh->state != LPUART_STATE_BUSY_RX)) - return BUSY; - - if ((buf == NULL ) || (size == 0)) - return ERROR; - - __LOCK(hperh); - - hperh->tx_buf = buf; - hperh->tx_size = size; - hperh->tx_count = size; - hperh->err_code = LPUART_ERROR_NONE; - SET_BIT(hperh->state, LPUART_STATE_TX_MASK); - - __UNLOCK(hperh); - ald_lpuart_interrupt_config(hperh, LPUART_IT_TBEMP, ENABLE); - - return OK; -} - -/** - * @brief Receives an amount of data in non blocking mode - * @param hperh: Pointer to a lpuart_handle_t structure that contains - * the configuration information for the specified LPUART module. - * @param buf: Pointer to data buffer - * @param size: Amount of data to be received - * @retval Status, see @ref ald_status_t. - */ -ald_status_t ald_lpuart_recv_by_it(lpuart_handle_t *hperh, uint8_t *buf, uint16_t size) -{ - if ((hperh->state != LPUART_STATE_READY) && (hperh->state != LPUART_STATE_BUSY_TX)) - return BUSY; - - if ((buf == NULL ) || (size == 0)) - return ERROR; - - __LOCK(hperh); - - hperh->rx_buf = buf; - hperh->rx_size = size; - hperh->rx_count = size; - hperh->err_code = LPUART_ERROR_NONE; - SET_BIT(hperh->state, LPUART_STATE_RX_MASK); - - __UNLOCK(hperh); - - ald_lpuart_interrupt_config(hperh, LPUART_IT_PERR, ENABLE); - ald_lpuart_interrupt_config(hperh, LPUART_IT_FERR, ENABLE); - ald_lpuart_interrupt_config(hperh, LPUART_IT_RBR, ENABLE); - - return OK; -} - -#ifdef ALD_DMA -/** - * @brief Sends an amount of data in non blocking mode. - * @param hperh: Pointer to a lpuart_handle_t structure that contains - * the configuration information for the specified LPUART module. - * @param buf: Pointer to data buffer - * @param size: Amount of data to be sent - * @param channel: DMA channel as LPUART transmit - * @retval Status, see @ref ald_status_t. - */ -ald_status_t ald_lpuart_send_by_dma(lpuart_handle_t *hperh, uint8_t *buf, uint16_t size, uint8_t channel) -{ - if ((hperh->state != LPUART_STATE_READY) && (hperh->state != LPUART_STATE_BUSY_RX)) - return BUSY; - - if ((buf == NULL ) || (size == 0)) - return ERROR; - - __LOCK(hperh); - - hperh->tx_buf = buf; - hperh->tx_size = size; - hperh->tx_count = size; - hperh->err_code = LPUART_ERROR_NONE; - SET_BIT(hperh->state, LPUART_STATE_TX_MASK); - - if (hperh->hdmatx.perh == NULL) - hperh->hdmatx.perh = DMA0; - - /* Set the dma parameters */ - hperh->hdmatx.cplt_cbk = lpuart_dma_send_cplt; - hperh->hdmatx.cplt_arg = (void *)hperh; - hperh->hdmatx.err_cbk = lpuart_dma_error; - hperh->hdmatx.err_arg = (void *)hperh; - - ald_dma_config_struct(&hperh->hdmatx.config); - hperh->hdmatx.config.src = (void *)buf; - hperh->hdmatx.config.dst = (void *)&hperh->perh->TXDR; - hperh->hdmatx.config.size = size; - hperh->hdmatx.config.src_inc = DMA_DATA_INC_BYTE; - hperh->hdmatx.config.dst_inc = DMA_DATA_INC_NONE; - hperh->hdmatx.config.msel = DMA_MSEL_LPUART0; - hperh->hdmatx.config.msigsel = DMA_MSIGSEL_LPUART_TXEMPTY; - hperh->hdmatx.config.channel = channel; - - if (hperh->init.mode == LPUART_MODE_RS485) { - hperh->hdmatx.config.src_inc = DMA_DATA_INC_HALFWORD; - hperh->hdmatx.config.data_width = DMA_DATA_SIZE_HALFWORD; - } - - ald_dma_config_basic(&hperh->hdmatx); - ald_lpuart_clear_flag_status(hperh, LPUART_IF_TC); - __UNLOCK(hperh); - ald_lpuart_dma_req_config(hperh, LPUART_DMA_REQ_TX, ENABLE); - - return OK; -} - -/** - * @brief Receives an amount of data in non blocking mode. - * @param hperh: Pointer to a lpuart_handle_t structure that contains - * the configuration information for the specified LPUART module. - * @param buf: Pointer to data buffer - * @param size: Amount of data to be received - * @param channel: DMA channel as LPUART receive - * @retval Status, see @ref ald_status_t. - */ -ald_status_t ald_lpuart_recv_by_dma(lpuart_handle_t *hperh, uint8_t *buf, uint16_t size, uint8_t channel) -{ - if ((hperh->state != LPUART_STATE_READY) && (hperh->state != LPUART_STATE_BUSY_TX)) - return BUSY; - - if ((buf == NULL ) || (size == 0)) - return ERROR; - - __LOCK(hperh); - - hperh->rx_buf = buf; - hperh->rx_size = size; - hperh->err_code = LPUART_ERROR_NONE; - SET_BIT(hperh->state, LPUART_STATE_RX_MASK); - - if (hperh->hdmarx.perh == NULL) - hperh->hdmarx.perh = DMA0; - - /* Set the dma parameters */ - hperh->hdmarx.cplt_cbk = lpuart_dma_recv_cplt; - hperh->hdmarx.cplt_arg = (void *)hperh; - hperh->hdmarx.err_cbk = lpuart_dma_error; - hperh->hdmarx.err_arg = (void *)hperh; - - ald_dma_config_struct(&hperh->hdmarx.config); - hperh->hdmarx.config.src = (void *)&hperh->perh->RXDR; - hperh->hdmarx.config.dst = (void *)buf; - hperh->hdmarx.config.size = size; - hperh->hdmarx.config.src_inc = DMA_DATA_INC_NONE; - hperh->hdmarx.config.dst_inc = DMA_DATA_INC_BYTE; - hperh->hdmarx.config.msel = DMA_MSEL_LPUART0; - hperh->hdmarx.config.msigsel = DMA_MSIGSEL_LPUART_RNR; - hperh->hdmarx.config.channel = channel; - - if (hperh->init.mode == LPUART_MODE_RS485) { - hperh->hdmarx.config.dst_inc = DMA_DATA_INC_HALFWORD; - hperh->hdmarx.config.data_width = DMA_DATA_SIZE_HALFWORD; - } - - ald_dma_config_basic(&hperh->hdmarx); - __UNLOCK(hperh); - ald_lpuart_dma_req_config(hperh, LPUART_DMA_REQ_RX, ENABLE); - - return OK; -} - -/** - * @brief Pauses the DMA Transfer. - * @param hperh: Pointer to a lpuart_handle_t structure that contains - * the configuration information for the specified LPUART module. - * @retval Status, see @ref ald_status_t. - */ -ald_status_t ald_lpuart_dma_pause(lpuart_handle_t *hperh) -{ - __LOCK(hperh); - - if (hperh->state == LPUART_STATE_BUSY_TX) { - ald_lpuart_dma_req_config(hperh, LPUART_DMA_REQ_TX, DISABLE); - } - else if (hperh->state == LPUART_STATE_BUSY_RX) { - ald_lpuart_dma_req_config(hperh, LPUART_DMA_REQ_RX, DISABLE); - } - else if (hperh->state == LPUART_STATE_BUSY_TX_RX) { - ald_lpuart_dma_req_config(hperh, LPUART_DMA_REQ_TX, DISABLE); - ald_lpuart_dma_req_config(hperh, LPUART_DMA_REQ_RX, DISABLE); - } - else { - __UNLOCK(hperh); - return ERROR; - } - - __UNLOCK(hperh); - return OK; -} - -/** - * @brief Resumes the DMA Transfer. - * @param hperh: Pointer to a lpuart_handle_t structure that contains - * the configuration information for the specified LPUART module. - * @retval Status, see @ref ald_status_t. - */ -ald_status_t ald_lpuart_dma_resume(lpuart_handle_t *hperh) -{ - __LOCK(hperh); - - if (hperh->state == LPUART_STATE_BUSY_TX) { - ald_lpuart_dma_req_config(hperh, LPUART_DMA_REQ_TX, ENABLE); - } - else if (hperh->state == LPUART_STATE_BUSY_RX) { - ald_lpuart_clear_flag_status(hperh, LPUART_IF_RXOV); - ald_lpuart_dma_req_config(hperh, LPUART_DMA_REQ_RX, ENABLE); - } - else if (hperh->state == LPUART_STATE_BUSY_TX_RX) { - ald_lpuart_clear_flag_status(hperh, LPUART_IF_RXOV); - ald_lpuart_dma_req_config(hperh, LPUART_DMA_REQ_TX, ENABLE); - ald_lpuart_dma_req_config(hperh, LPUART_DMA_REQ_RX, ENABLE); - } - else { - __UNLOCK(hperh); - return ERROR; - } - - __UNLOCK(hperh); - return OK; -} - -/** - * @brief Stops the DMA Transfer. - * @param hperh: Pointer to a lpuart_handle_t structure that contains - * the configuration information for the specified LPUART module. - * @retval Status, see @ref ald_status_t. - */ -ald_status_t ald_lpuart_dma_stop(lpuart_handle_t *hperh) -{ - ald_lpuart_dma_req_config(hperh, LPUART_DMA_REQ_TX, DISABLE); - ald_lpuart_dma_req_config(hperh, LPUART_DMA_REQ_RX, DISABLE); - - hperh->state = LPUART_STATE_READY; - return OK; -} -#endif - -/** - * @brief This function handles LPUART interrupt request. - * @param hperh: Pointer to a lpuart_handle_t structure that contains - * the configuration information for the specified LPUART module. - * @retval None - */ -void ald_lpuart_irq_handler(lpuart_handle_t *hperh) -{ - uint32_t flag; - uint32_t source; - - /* Handle CTS wakeup */ - flag = ald_lpuart_get_flag_status(hperh, LPUART_IF_CTSWK); - source = ald_lpuart_get_it_status(hperh, LPUART_IT_CTSWK); - if ((flag != RESET) && (source != RESET)) - ald_lpuart_clear_flag_status(hperh, LPUART_IF_CTSWK); - - /* Handle DATA wakeup */ - flag = ald_lpuart_get_flag_status(hperh, LPUART_IF_DATWK); - source = ald_lpuart_get_it_status(hperh, LPUART_IT_DATWK); - if ((flag != RESET) && (source != RESET)) - ald_lpuart_clear_flag_status(hperh, LPUART_IF_DATWK); - - /* Handle parity error */ - flag = ald_lpuart_get_flag_status(hperh, LPUART_IF_PERR); - source = ald_lpuart_get_it_status(hperh, LPUART_IT_PERR); - if ((flag != RESET) && (source != RESET)) - hperh->err_code |= LPUART_ERROR_PE; - - /* Handle frame error */ - flag = ald_lpuart_get_flag_status(hperh, LPUART_IF_FERR); - source = ald_lpuart_get_it_status(hperh, LPUART_IT_FERR); - if ((flag != RESET) && (source != RESET)) - hperh->err_code |= LPUART_ERROR_FE; - - /* Handle overflow error */ - flag = ald_lpuart_get_flag_status(hperh, LPUART_IF_RXOV); - source = ald_lpuart_get_it_status(hperh, LPUART_IT_RXOV); - if ((flag != RESET) && (source != RESET)) - hperh->err_code |= LPUART_ERROR_ORE; - - /* Receive */ - flag = ald_lpuart_get_flag_status(hperh, LPUART_IF_RBR); - source = ald_lpuart_get_it_status(hperh, LPUART_IT_RBR); - if ((flag != RESET) && (source != RESET)) - __lpuart_recv_by_it(hperh); - - /* Transmite */ - flag = ald_lpuart_get_flag_status(hperh, LPUART_IF_TBEMP); - source = ald_lpuart_get_it_status(hperh, LPUART_IT_TBEMP); - if ((flag != RESET) && (source != RESET)) - __lpuart_send_by_it(hperh); - - /* End Transmite */ - flag = ald_lpuart_get_flag_status(hperh, LPUART_IF_TC); - source = ald_lpuart_get_it_status(hperh, LPUART_IT_TC); - if ((flag != RESET) && (source != RESET)) - __lpuart_end_send_by_it(hperh); - - /* Handle error state */ - if (hperh->err_code != LPUART_ERROR_NONE) { - ald_lpuart_clear_flag_status(hperh, LPUART_IF_PERR); - ald_lpuart_clear_flag_status(hperh, LPUART_IF_FERR); - ald_lpuart_clear_flag_status(hperh, LPUART_IF_RXOV); - hperh->state = LPUART_STATE_READY; - - if (hperh->error_cbk) - hperh->error_cbk(hperh); - } -} -/** - * @} - */ - -/** @defgroup LPUART_Public_Functions_Group3 Peripheral Control functions - * @brief Low Power UART control functions - * - * @verbatim - ============================================================================== - ##### Peripheral Control functions ##### - ============================================================================== - [..] - This subsection provides a set of functions allowing to control the LPUART: - (+) ald_lpuart_interrupt_config() API can be helpful to configure LPUART interrupt source. - (+) ald_lpuart_tx_interval_config() API can be helpful to configure TX interval. - (+) ald_lpuart_dma_req_config() API can be helpful to configure LPUART DMA request. - (+) ald_lpuart_rx_fifo_it_config() API can be helpful to configure LPUART RX FIFO interrupt. - (+) ald_lpuart_rx_fifo_rts_config() API can be helpful to configure RTS threshold value. - (+) ald_lpuart_get_flag_status() API can get the status of LPUART flag. - (+) ald_lpuart_clear_flag_status() API can clear LPUART flag. - (+) ald_lpuart_get_it_status() API can get the status of interrupt source. - - @endverbatim - * @{ - */ - -/** - * @brief Enable/disable the specified LPUART interrupts. - * @param hperh: Pointer to a lpuart_handle_t structure that contains - * the configuration information for the specified LPUART module. - * @param it: Specifies the LPUART interrupt sources to be enabled or - * disabled. This parameter can be one of the @ref lpuart_it_t. - * @param status: New state of the specified LPUART interrupts. - * This parameter can be: - * @arg ENABLE - * @arg DISABLE - * @retval None - */ -void ald_lpuart_interrupt_config(lpuart_handle_t *hperh, lpuart_it_t it, type_func_t status) -{ - assert_param(IS_LPUART(hperh->perh)); - assert_param(IS_LPUART_IT(it)); - assert_param(IS_FUNC_STATE(status)); - - if (status == ENABLE) - SET_BIT(hperh->perh->IER, it); - else - CLEAR_BIT(hperh->perh->IER, it); - - return; -} - -/** - * @brief Configure transmite interval. - * @param hperh: Pointer to a lpuart_handle_t structure that contains - * the configuration information for the specified LPUART module. - * @param val: The value of interval. - * @retval None - */ -void ald_lpuart_tx_interval_config(lpuart_handle_t *hperh, uint8_t val) -{ - assert_param(IS_LPUART(hperh->perh)); - - MODIFY_REG(hperh->perh->CON0, LPUART_CON0_INTERVAL_MSK, val << LPUART_CON0_INTERVAL_POSS); - return; -} - -/** - * @brief Configure LPUART DMA request. - * @param hperh: Pointer to a lpuart_handle_t structure that contains - * the configuration information for the specified LPUART module. - * @param req: The DMA type: - * @arg LPUART_DMA_REQ_TX - * @arg LPUART_DMA_REQ_RX - * @param status: New state of the specified DMA request. - * This parameter can be: - * @arg ENABLE - * @arg DISABLE - * @retval None - */ -void ald_lpuart_dma_req_config(lpuart_handle_t *hperh, lpuart_dma_req_t req, type_func_t status) -{ - assert_param(IS_LPUART(hperh->perh)); - assert_param(IS_LPUART_DMAREQ(req)); - assert_param(IS_FUNC_STATE(status)); - - if (req == LPUART_DMA_REQ_TX) { - if (status == ENABLE) - SET_BIT(hperh->perh->CON0, LPUART_CON0_TXDMAE_MSK); - else - CLEAR_BIT(hperh->perh->CON0, LPUART_CON0_TXDMAE_MSK); - } - else { - if (status == ENABLE) - SET_BIT(hperh->perh->CON0, LPUART_CON0_RXDMAE_MSK); - else - CLEAR_BIT(hperh->perh->CON0, LPUART_CON0_RXDMAE_MSK); - } - - return; -} - -/** - * @brief Configure receive FIFO interrupt threshold value. - * @param hperh: Pointer to a lpuart_handle_t structure that contains - * the configuration information for the specified LPUART module. - * @param config: The value of RX FIFO interrupt threshold value. - * @retval None - */ -void ald_lpuart_rx_fifo_it_config(lpuart_handle_t *hperh, lpuart_rxfifo_t config) -{ - assert_param(IS_LPUART(hperh->perh)); - assert_param(IS_LPUART_RXFIFO(config)); - - MODIFY_REG(hperh->perh->FIFOCON, LPUART_FIFOCON_RXTRGLVL_MSK, config << LPUART_FIFOCON_RXTRGLVL_POSS); - return; -} - -/** - * @brief Configure receive FIFO RTS threshold value. - * @param hperh: Pointer to a lpuart_handle_t structure that contains - * the configuration information for the specified LPUART module. - * @param config: The value of RX FIFO RTS threshold value. - * @retval None - */ -void ald_lpuart_rx_fifo_rts_config(lpuart_handle_t *hperh, lpuart_rxfifo_t config) -{ - assert_param(IS_LPUART(hperh->perh)); - assert_param(IS_LPUART_RXFIFO(config)); - - MODIFY_REG(hperh->perh->FIFOCON, LPUART_FIFOCON_RTSTRGLVL_MSK, config << LPUART_FIFOCON_RTSTRGLVL_POSS); - return; -} - -/** - * @brief Send address in RS485 mode. - * @param hperh: Pointer to a lpuart_handle_t structure that contains - * the configuration information for the specified LPUART module. - * @param addr: the address of RS485 device. - * @param timeout: Timeout duration - * @retval The hal status. - */ -ald_status_t ald_lpuart_rs485_send_addr(lpuart_handle_t *hperh, uint16_t addr, uint32_t timeout) -{ - assert_param(IS_LPUART(hperh->perh)); - - if ((hperh->state != LPUART_STATE_READY) && (hperh->state != LPUART_STATE_BUSY_RX)) - return BUSY; - - SET_BIT(hperh->state, LPUART_STATE_TX_MASK); - - if (lpuart_wait_flag(hperh, LPUART_STAT_TXEMP, SET, timeout) != OK) { - hperh->state = LPUART_STATE_READY; - return TIMEOUT; - } - - WRITE_REG(hperh->perh->TXDR, addr | 0x100); - - if (lpuart_wait_flag(hperh, LPUART_STAT_TXEMP, RESET, timeout) != OK) { - hperh->state = LPUART_STATE_READY; - return TIMEOUT; - } - - if (lpuart_wait_flag(hperh, LPUART_STAT_TXIDLE, SET, timeout) != OK) { - hperh->state = LPUART_STATE_READY; - return TIMEOUT; - } - - CLEAR_BIT(hperh->state, LPUART_STATE_TX_MASK); - return OK; -} - -/** - * @brief Get the status of LPUART status. - * @param hperh: Pointer to a lpuart_handle_t structure that contains - * the configuration information for the specified LPUART module. - * @param flag: Specifies the LPUART status flag. - * This parameter can be one of the @ref lpuart_status_t. - * @retval Status: - * - RESET - * - SET - */ -flag_status_t ald_lpuart_get_status(lpuart_handle_t *hperh, lpuart_status_t flag) -{ - assert_param(IS_LPUART(hperh->perh)); - assert_param(IS_LPUART_STAT(flag)); - - if (READ_BIT(hperh->perh->STAT, flag)) - return SET; - - return RESET; -} - -/** - * @brief Get the status of LPUART interrupt flag. - * @param hperh: Pointer to a lpuart_handle_t structure that contains - * the configuration information for the specified LPUART module. - * @param flag: Specifies the LPUART interrupt flag. - * This parameter can be one of the @ref lpuart_flag_t. - * @retval Status: - * - RESET - * - SET - */ -flag_status_t ald_lpuart_get_flag_status(lpuart_handle_t *hperh, lpuart_flag_t flag) -{ - assert_param(IS_LPUART(hperh->perh)); - assert_param(IS_LPUART_IF(flag)); - - if (READ_BIT(hperh->perh->IFLAG, flag)) - return SET; - - return RESET; -} - -/** - * @brief Clear the LPUART interrupt flag. - * @param hperh: Pointer to a lpuart_handle_t structure that contains - * the configuration information for the specified LPUART module. - * @param flag: Specifies the LPUART interrupt flag. - * This parameter can be one of the @ref lpuart_flag_t. - * @retval None - */ -void ald_lpuart_clear_flag_status(lpuart_handle_t *hperh, lpuart_flag_t flag) -{ - assert_param(IS_LPUART(hperh->perh)); - assert_param(IS_LPUART_IF(flag)); - - WRITE_REG(hperh->perh->IFC, flag); - return; -} - -/** - * @brief Get the status of LPUART interrupt source. - * @param hperh: Pointer to a lpuart_handle_t structure that contains - * the configuration information for the specified LPUART module. - * @param it: Specifies the LPUART interrupt source. - * This parameter can be one of the @ref lpuart_it_t. - * @retval Status: - * - RESET - * - SET - */ -it_status_t ald_lpuart_get_it_status(lpuart_handle_t *hperh, lpuart_it_t it) -{ - assert_param(IS_LPUART(hperh->perh)); - assert_param(IS_LPUART_IT(it)); - - if (READ_BIT(hperh->perh->IER, it)) - return SET; - - return RESET; -} -/** - * @} - */ - -/** @defgroup LPUART_Public_Functions_Group4 Peripheral State and Errors functions - * @brief LPUART State and Errors functions - * -@verbatim - ============================================================================== - ##### Peripheral State and Errors functions ##### - ============================================================================== - [..] - This subsection provides a set of functions allowing to return the State of - LPUART communication process, return Peripheral Errors occurred during communication - process - (+) ald_lpuart_get_state() API can be helpful to check in run-time the state of the LPUART peripheral. - (+) ald_lpuart_get_error() check in run-time errors that could be occurred during communication. - -@endverbatim - * @{ - */ - -/** - * @brief Returns the LPUART state. - * @param hperh: Pointer to a lpuart_handle_t structure that contains - * the configuration information for the specified LPUART module. - * @retval HAL state - */ -lpuart_state_t ald_lpuart_get_state(lpuart_handle_t *hperh) -{ - return hperh->state; -} - -/** - * @brief Return the LPUART error code - * @param hperh: Pointer to a lpuart_handle_t structure that contains - * the configuration information for the specified LPUART. - * @retval LPUART Error Code - */ -uint32_t ald_lpuart_get_error(lpuart_handle_t *hperh) -{ - return hperh->err_code; -} - -/** - * @} - */ - -/** - * @} - */ -#endif /* ALD_LPUART */ - -/** - * @} - */ - -/** - * @} - */ diff --git a/bsp/essemi/es32f0334/libraries/ES32F033x_ALD_StdPeriph_Driver/Source/ald_pis.c b/bsp/essemi/es32f0334/libraries/ES32F033x_ALD_StdPeriph_Driver/Source/ald_pis.c deleted file mode 100644 index d9067499ea..0000000000 --- a/bsp/essemi/es32f0334/libraries/ES32F033x_ALD_StdPeriph_Driver/Source/ald_pis.c +++ /dev/null @@ -1,316 +0,0 @@ -/** - ********************************************************************************* - * - * @file ald_pis.c - * @brief PIS module driver. - * - * @version V1.0 - * @date 27 Nov 2017 - * @author AE Team - * @note - * - * Copyright (C) Shanghai Eastsoft Microelectronics Co. Ltd. All rights reserved. - * - ********************************************************************************* - */ - -#include "ald_pis.h" - -/** @addtogroup ES32FXXX_ALD - * @{ - */ - -/** @defgroup PIS PIS - * @brief PIS module driver - * @{ - */ -#ifdef ALD_PIS - -/** @defgroup PIS_Public_Functions PIS Public Functions - * @{ - */ - -/** @defgroup PIS_Public_Functions_Group1 Initialization functions - * @brief Initialization and Configuration functions - * @{ - */ - -/** - * @brief Create the PIS mode according to the specified parameters in - * the pis_handle_t and create the associated handle. - * @param hperh: Pointer to a pis_handle_t structure that contains - * the configuration information for the specified PIS module. - * @retval Status, see @ref ald_status_t. - */ -ald_status_t ald_pis_create(pis_handle_t *hperh) -{ - uint8_t clock_menu = 0; - - if (hperh == NULL) - return ERROR; - - assert_param(IS_PIS_SRC(hperh->init.producer_src)); - assert_param(IS_PIS_TRIG(hperh->init.consumer_trig)); - assert_param(IS_PIS_CLOCK(hperh->init.producer_clk)); - assert_param(IS_PIS_CLOCK(hperh->init.consumer_clk)); - assert_param(IS_PIS_EDGE(hperh->init.producer_edge)); - - __LOCK(hperh); - hperh->perh = PIS; - - /* get location of consumer in channel and position of con0/con1 - * accord to comsumer_trig information */ - hperh->consumer_ch = (pis_ch_t)(hperh->init.consumer_trig & 0x0F); - hperh->consumer_con = (pis_con_t)(((uint32_t)hperh->init.consumer_trig >> 4) & 0x0F); - hperh->consumer_pos = (1U << (uint32_t)(((uint32_t)hperh->init.consumer_trig >> 8) & 0xFF)); - - /* union producer clock and consumer clock */ - clock_menu = (hperh->init.producer_clk << 4) | (hperh->init.consumer_clk); - - if (hperh->perh->CH_CON[hperh->consumer_ch] != 0) { - __UNLOCK(hperh); - return BUSY; - } - - MODIFY_REG(hperh->perh->CH_CON[hperh->consumer_ch], PIS_CH0_CON_SRCS_MSK, ((hperh->init.producer_src) >> 4) << PIS_CH0_CON_SRCS_POSS); - MODIFY_REG(hperh->perh->CH_CON[hperh->consumer_ch], PIS_CH0_CON_MSIGS_MSK, ((hperh->init.producer_src) & 0xf) << PIS_CH0_CON_MSIGS_POSS); - - /* configure sync clock, judging by producer clock with consumer clock */ - switch (clock_menu) { - case 0x00: - case 0x11: - case 0x22: - case 0x33: - MODIFY_REG(hperh->perh->CH_CON[hperh->consumer_ch], PIS_CH0_CON_SYNCSEL_MSK, 0 << PIS_CH0_CON_SYNCSEL_POSS); - break; - case 0x01: - MODIFY_REG(hperh->perh->CH_CON[hperh->consumer_ch], PIS_CH0_CON_SYNCSEL_MSK, 5 << PIS_CH0_CON_SYNCSEL_POSS); - break; - case 0x02: - case 0x12: - MODIFY_REG(hperh->perh->CH_CON[hperh->consumer_ch], PIS_CH0_CON_SYNCSEL_MSK, 6 << PIS_CH0_CON_SYNCSEL_POSS); - break; - case 0x21: - MODIFY_REG(hperh->perh->CH_CON[hperh->consumer_ch], PIS_CH0_CON_SYNCSEL_MSK, 4 << PIS_CH0_CON_SYNCSEL_POSS); - break; - case 0x30: - MODIFY_REG(hperh->perh->CH_CON[hperh->consumer_ch], PIS_CH0_CON_SYNCSEL_MSK, 1 << PIS_CH0_CON_SYNCSEL_POSS); - break; - case 0x31: - MODIFY_REG(hperh->perh->CH_CON[hperh->consumer_ch], PIS_CH0_CON_SYNCSEL_MSK, 2 << PIS_CH0_CON_SYNCSEL_POSS); - break; - case 0x32: - MODIFY_REG(hperh->perh->CH_CON[hperh->consumer_ch], PIS_CH0_CON_SYNCSEL_MSK, 3 << PIS_CH0_CON_SYNCSEL_POSS); - break; - default: - break; - } - - MODIFY_REG(hperh->perh->CH_CON[hperh->consumer_ch], PIS_CH0_CON_PULCK_MSK, hperh->init.consumer_clk << PIS_CH0_CON_PULCK_POSS); - MODIFY_REG(hperh->perh->CH_CON[hperh->consumer_ch], PIS_CH0_CON_EDGS_MSK, hperh->init.producer_edge << PIS_CH0_CON_EDGS_POSS); - hperh->check_info = hperh->perh->CH_CON[hperh->consumer_ch]; - - /* enable consumer bit, switch pin of consumer */ - switch (hperh->consumer_con) { - case PIS_CON_0: - PIS->TAR_CON0 |= hperh->consumer_pos; - break; - case PIS_CON_1: - PIS->TAR_CON1 |= hperh->consumer_pos; - break; - default: - break; - } - - __UNLOCK(hperh); - return OK; -} - -/** - * @brief Destroy the PIS mode according to the specified parameters in - * the pis_init_t and create the associated handle. - * @param hperh: Pointer to a pis_handle_t structure that contains - * the configuration information for the specified PIS module. - * @retval Status, see @ref ald_status_t. - */ -ald_status_t ald_pis_destroy(pis_handle_t *hperh) -{ - assert_param(IS_PIS(hperh->perh)); - - if (hperh->check_info != hperh->perh->CH_CON[hperh->consumer_ch]) - return ERROR; - - __LOCK(hperh); - - CLEAR_BIT(PIS->CH_OER, (1U << (uint32_t)hperh->consumer_ch)); - WRITE_REG(hperh->perh->CH_CON[hperh->consumer_ch], 0x0); - - switch (hperh->consumer_con) { - case PIS_CON_0: - PIS->TAR_CON0 &= ~(hperh->consumer_pos); - break; - case PIS_CON_1: - PIS->TAR_CON1 &= ~(hperh->consumer_pos); - break; - default: - break; - } - - hperh->state = PIS_STATE_RESET; - __UNLOCK(hperh); - - return OK; -} -/** - * @} - */ - -/** @defgroup PIS_Public_Functions_Group2 Operation functions - * @brief PIS output enable or disable functions - * @{ - */ - -/** - * @brief Start the PIS output function. - * @param hperh: Pointer to a pis_handle_t structure that contains - * the configuration information for the specified PIS module. - * @param ch: The PIS channel enable output - * This parameter can be one of the following values: - * @arg PIS_OUT_CH_0 - * @arg PIS_OUT_CH_1 - * @arg PIS_OUT_CH_2 - * @arg PIS_OUT_CH_3 - * @retval Status, see @ref ald_status_t. - */ -ald_status_t ald_pis_output_start(pis_handle_t *hperh, pis_out_ch_t ch) -{ - assert_param(IS_PIS(hperh->perh)); - assert_param(IS_PIS_OUPUT_CH(ch)); - __LOCK(hperh); - SET_BIT(PIS->CH_OER, (1 << ch)); - __UNLOCK(hperh); - - return OK; -} - -/** - * @brief Stop the PIS output function. - * @param hperh: Pointer to a pis_handle_t structure that contains - * the configuration information for the specified PIS module. - * @param ch: The PIS channel disable output - * This parameter can be one of the following values: - * @arg PIS_OUT_CH_0 - * @arg PIS_OUT_CH_1 - * @arg PIS_OUT_CH_2 - * @arg PIS_OUT_CH_3 - * @retval Status, see @ref ald_status_t. - */ -ald_status_t ald_pis_output_stop(pis_handle_t *hperh, pis_out_ch_t ch) -{ - assert_param(IS_PIS(hperh->perh)); - assert_param(IS_PIS_OUPUT_CH(ch)); - __LOCK(hperh); - CLEAR_BIT(PIS->CH_OER, (1 << ch)); - __UNLOCK(hperh); - - return OK; -} -/** - * @} - */ - -/** @defgroup PIS_Public_Functions_Group3 Peripheral State and Errors functions - * @brief PIS State and Errors functions - * @{ - */ - -/** - * @brief Returns the PIS state. - * @param hperh: Pointer to a pis_handle_t structure that contains - * the configuration information for the specified PIS module. - * @retval ALD state - */ -pis_state_t ald_pis_get_state(pis_handle_t *hperh) -{ - assert_param(IS_PIS(hperh->perh)); - return hperh->state; -} - -/** - * @} - */ - -/** @defgroup PIS_Public_Functions_Group4 modulate output functions - * @brief PIS modulate output signal functions - * @{ - */ - -/** - * @brief Config the PIS modulate signal function - * @param hperh: Pointer to a pis_handle_t structure that contains - * the configuration information for the specified PIS module. - * @param config: Pointer to a pis_modulate_config_t structure that - * contains the selected target (UART0,UART1,UART2,UART3 or - * LPUART0) how to modulate the target output signal. - * @retval Status, see @ref ald_status_t. - */ -ald_status_t ald_pis_modu_config(pis_handle_t *hperh, pis_modulate_config_t *config) -{ - assert_param(IS_PIS(hperh->perh)); - assert_param(IS_PIS_MODU_TARGET(config->target)); - assert_param(IS_PIS_MODU_LEVEL(config->level)); - assert_param(IS_PIS_MODU_SRC(config->src)); - assert_param(IS_PIS_MODU_CHANNEL(config->channel)); - __LOCK(hperh); - - switch (config->target) { - case PIS_UART0_TX: - MODIFY_REG(hperh->perh->UART0_TXMCR, PIS_TXMCR_TXMLVLS_MSK, config->level << PIS_TXMCR_TXMLVLS_POS); - MODIFY_REG(hperh->perh->UART0_TXMCR, PIS_TXMCR_TXMSS_MSK, config->src << PIS_TXMCR_TXMSS_POSS); - MODIFY_REG(hperh->perh->UART0_TXMCR, PIS_TXMCR_TXSIGS_MSK, config->channel << PIS_TXMCR_TXSIGS_POSS); - break; - - case PIS_UART1_TX: - MODIFY_REG(hperh->perh->UART1_TXMCR, PIS_TXMCR_TXMLVLS_MSK, config->level << PIS_TXMCR_TXMLVLS_POS); - MODIFY_REG(hperh->perh->UART1_TXMCR, PIS_TXMCR_TXMSS_MSK, config->src << PIS_TXMCR_TXMSS_POSS); - MODIFY_REG(hperh->perh->UART1_TXMCR, PIS_TXMCR_TXSIGS_MSK, config->channel << PIS_TXMCR_TXSIGS_POSS); - break; - - case PIS_UART2_TX: - MODIFY_REG(hperh->perh->UART2_TXMCR, PIS_TXMCR_TXMLVLS_MSK, config->level << PIS_TXMCR_TXMLVLS_POS); - MODIFY_REG(hperh->perh->UART2_TXMCR, PIS_TXMCR_TXMSS_MSK, config->src << PIS_TXMCR_TXMSS_POSS); - MODIFY_REG(hperh->perh->UART2_TXMCR, PIS_TXMCR_TXSIGS_MSK, config->channel << PIS_TXMCR_TXSIGS_POSS); - break; - - case PIS_UART3_TX: - MODIFY_REG(hperh->perh->UART3_TXMCR, PIS_TXMCR_TXMLVLS_MSK, config->level << PIS_TXMCR_TXMLVLS_POS); - MODIFY_REG(hperh->perh->UART3_TXMCR, PIS_TXMCR_TXMSS_MSK, config->src << PIS_TXMCR_TXMSS_POSS); - MODIFY_REG(hperh->perh->UART3_TXMCR, PIS_TXMCR_TXSIGS_MSK, config->channel << PIS_TXMCR_TXSIGS_POSS); - break; - - case PIS_LPUART0_TX: - MODIFY_REG(hperh->perh->LPUART0_TXMCR, PIS_TXMCR_TXMLVLS_MSK, config->level << PIS_TXMCR_TXMLVLS_POS); - MODIFY_REG(hperh->perh->LPUART0_TXMCR, PIS_TXMCR_TXMSS_MSK, config->src << PIS_TXMCR_TXMSS_POSS); - MODIFY_REG(hperh->perh->LPUART0_TXMCR, PIS_TXMCR_TXSIGS_MSK, config->channel << PIS_TXMCR_TXSIGS_POSS); - break; - - default: - break; - } - - __UNLOCK(hperh); - return OK; -} -/** - * @} - */ -/** - * @} - */ -#endif /* ALD_PIS */ -/** - * @} - */ -/** - * @} - */ diff --git a/bsp/essemi/es32f0334/libraries/ES32F033x_ALD_StdPeriph_Driver/Source/ald_pmu.c b/bsp/essemi/es32f0334/libraries/ES32F033x_ALD_StdPeriph_Driver/Source/ald_pmu.c deleted file mode 100644 index 42094fc298..0000000000 --- a/bsp/essemi/es32f0334/libraries/ES32F033x_ALD_StdPeriph_Driver/Source/ald_pmu.c +++ /dev/null @@ -1,256 +0,0 @@ -/** - ********************************************************************************* - * - * @file ald_pmu.c - * @brief PMU module driver. - * - * @version V1.0 - * @date 04 Dec 2017 - * @author AE Team - * @note - * - * Copyright (C) Shanghai Eastsoft Microelectronics Co. Ltd. All rights reserved. - * - ********************************************************************************* - */ - -#include "ald_pmu.h" - - -/** @addtogroup ES32FXXX_ALD - * @{ - */ - -/** @defgroup PMU PMU - * @brief PMU module driver - * @{ - */ -#ifdef ALD_PMU - - -/** @defgroup PMU_Private_Functions PMU Private Functions - * @{ - */ - -/** - * @brief PMU module interrupt handler - * @retval None - */ -void ald_lvd_irq_handler(void) -{ - SYSCFG_UNLOCK(); - SET_BIT(PMU->LVDCR, PMU_LVDCR_LVDCIF_MSK); - SYSCFG_LOCK(); - - return; -} -/** - * @} - */ - -/** @defgroup PMU_Public_Functions PMU Public Functions - * @{ - */ - -/** @addtogroup PMU_Public_Functions_Group1 Low Power Mode - * @brief Low power mode select functions - * - * @verbatim - ============================================================================== - ##### Low power mode select functions ##### - ============================================================================== - [..] This section provides functions allowing to: - (+) Enter stop1 mode. - (+) Enter stop2 mode. - (+) Enter standby mode. - (+) Get wakeup status. - (+) Clear wakeup status. - - @endverbatim - * @{ - */ - -/** - * @brief Enter stop1 mode - * @retval None - */ -void ald_pmu_stop1_enter(void) -{ - SYSCFG_UNLOCK(); - SET_BIT(PMU->CR, PMU_CR_LPSTOP_MSK); - MODIFY_REG(PMU->CR, PMU_CR_LPM_MSK, PMU_LP_STOP1 << PMU_CR_LPM_POSS); - SYSCFG_LOCK(); - - SysTick->CTRL &= ~SysTick_CTRL_ENABLE_Msk; - SCB->SCR |= SCB_SCR_SLEEPDEEP_Msk; - __WFI(); - SysTick->CTRL |= SysTick_CTRL_ENABLE_Msk; - - return; -} - -/** - * @brief Enter stop2 mode - * @retval None - */ -void ald_pmu_stop2_enter(void) -{ - SYSCFG_UNLOCK(); - SET_BIT(PMU->CR, PMU_CR_LPSTOP_MSK); - MODIFY_REG(PMU->CR, PMU_CR_LPM_MSK, PMU_LP_STOP2 << PMU_CR_LPM_POSS); - SYSCFG_LOCK(); - - SysTick->CTRL &= ~SysTick_CTRL_ENABLE_Msk; - SCB->SCR |= SCB_SCR_SLEEPDEEP_Msk; - __WFI(); - SysTick->CTRL |= SysTick_CTRL_ENABLE_Msk; - - return; -} - -/** - * @brief Enter standby mode - * @param port: The port whick wake up the standby mode. - * @param level: Wakeup level. - * @retval None - */ -void ald_pmu_standby_enter(bkpc_wakeup_port_t port, bkpc_wakeup_level_t level) -{ - ald_bkpc_standby_wakeup_config(port, level); - - SYSCFG_UNLOCK(); - SET_BIT(PMU->CR, PMU_CR_LPSTOP_MSK); - MODIFY_REG(PMU->CR, PMU_CR_LPM_MSK, PMU_LP_STANDBY << PMU_CR_LPM_POSS); - SYSCFG_LOCK(); - - SysTick->CTRL &= ~SysTick_CTRL_ENABLE_Msk; - SCB->SCR |= SCB_SCR_SLEEPDEEP_Msk; - __WFI(); - SysTick->CTRL |= SysTick_CTRL_ENABLE_Msk; - - return; -} - -/** - * @brief Configures low power mode. The system clock must - * be less than 2MHz. Such as: LOSC or LRC. - * @param vol: LDO output voltage select in low power mode. - * @param state: New state, ENABLE/DISABLE; - * @retval None - */ -void ald_pmu_lprun_config(pmu_ldo_lpmode_output_t vol, type_func_t state) -{ - assert_param(IS_FUNC_STATE(state)); - SYSCFG_UNLOCK(); - - if (state) { - assert_param(IS_PMU_LDO_LPMODE_OUTPUT(vol)); - - MODIFY_REG(PMU->CR, PMU_CR_LPVS_MSK, vol << PMU_CR_LPVS_POSS); - SET_BIT(PMU->CR, PMU_CR_LPRUN_MSK); - } - else { - CLEAR_BIT(PMU->CR, PMU_CR_LPRUN_MSK); - } - - SYSCFG_LOCK(); - return; -} - -/** - * @brief Get wakup status. - * @param sr: Status bit. - * @retval Status. - */ -flag_status_t ald_pmu_get_status(pmu_status_t sr) -{ - assert_param(IS_PMU_STATUS(sr)); - - if (READ_BIT(PMU->SR, sr)) - return SET; - - return RESET; -} - -/** - * @brief Clear wakup status. - * @param sr: Status bit. - * @retval None - */ -void ald_pmu_clear_status(pmu_status_t sr) -{ - assert_param(IS_PMU_STATUS(sr)); - SYSCFG_UNLOCK(); - - if (sr == PMU_SR_WUF) - SET_BIT(PMU->CR, PMU_CR_CWUF_MSK); - else - SET_BIT(PMU->CR, PMU_CR_CSTANDBYF_MSK); - - SYSCFG_LOCK(); - return; -} -/** - * @} - */ - -/** @addtogroup PMU_Public_Functions_Group2 LVD Configure - * @brief LVD configure functions - * - * @verbatim - ============================================================================== - ##### LVD configure functions ##### - ============================================================================== - [..] This section provides functions allowing to: - (+) Configure lvd parameters. - (+) Interrupt callback function. - - @endverbatim - * @{ - */ - -/** - * @brief Configure lvd using specified parameters. - * @param sel: LVD threshold voltage. - * @param mode: LVD trigger mode. - * @param state: New state, ENABLE/DISABLE; - * @retval None - */ -void ald_pmu_lvd_config(pmu_lvd_voltage_sel_t sel, pmu_lvd_trigger_mode_t mode, type_func_t state) -{ - assert_param(IS_FUNC_STATE(state)); - SYSCFG_UNLOCK(); - - if (state) { - assert_param(IS_PMU_LVD_VOL_SEL(sel)); - assert_param(IS_PMU_LVD_TRIGGER_MODE(mode)); - - MODIFY_REG(PMU->LVDCR, PMU_LVDCR_LVDS_MSK, sel << PMU_LVDCR_LVDS_POSS); - MODIFY_REG(PMU->LVDCR, PMU_LVDCR_LVIFS_MSK, mode << PMU_LVDCR_LVIFS_POSS); - SET_BIT(PMU->LVDCR, PMU_LVDCR_LVDFLT_MSK); - SET_BIT(PMU->LVDCR, PMU_LVDCR_LVDCIF_MSK); - SET_BIT(PMU->LVDCR, PMU_LVDCR_LVDIE_MSK); - SET_BIT(PMU->LVDCR, PMU_LVDCR_LVDEN_MSK); - } - else { - SET_BIT(PMU->LVDCR, PMU_LVDCR_LVDCIF_MSK); - CLEAR_BIT(PMU->LVDCR, PMU_LVDCR_LVDIE_MSK); - CLEAR_BIT(PMU->LVDCR, PMU_LVDCR_LVDEN_MSK); - } - - SYSCFG_LOCK(); - return; -} -/** - * @} - */ -/** - * @} - */ -#endif /* ALD_PMU */ -/** - * @} - */ -/** - * @} - */ diff --git a/bsp/essemi/es32f0334/libraries/ES32F033x_ALD_StdPeriph_Driver/Source/ald_rmu.c b/bsp/essemi/es32f0334/libraries/ES32F033x_ALD_StdPeriph_Driver/Source/ald_rmu.c deleted file mode 100644 index 2b04f2719c..0000000000 --- a/bsp/essemi/es32f0334/libraries/ES32F033x_ALD_StdPeriph_Driver/Source/ald_rmu.c +++ /dev/null @@ -1,146 +0,0 @@ -/** - ********************************************************************************* - * - * @file ald_rmu.c - * @brief RMU module driver. - * - * @version V1.0 - * @date 04 Dec 2017 - * @author AE Team - * @note - * - * Copyright (C) Shanghai Eastsoft Microelectronics Co. Ltd. All rights reserved. - * - ********************************************************************************* - */ - -#include "ald_rmu.h" -#include "ald_syscfg.h" - -/** @addtogroup ES32FXXX_ALD - * @{ - */ - -/** @defgroup RMU RMU - * @brief RMU module driver - * @{ - */ -#ifdef ALD_RMU - -/** @defgroup RMU_Public_Functions RMU Public Functions - * @{ - */ - -/** - * @brief Configure BOR parameters. - * @param flt: filter time. - * @param vol: The voltage. - * @param state: The new status: ENABLE/DISABLE. - * @retval None - */ -void ald_rmu_bor_config(rmu_bor_filter_t flt, rmu_bor_vol_t vol, type_func_t state) -{ - assert_param(IS_FUNC_STATE(state)); - - SYSCFG_UNLOCK(); - - if (state) { - assert_param(IS_RMU_BORFLT(flt)); - assert_param(IS_RMU_BORVOL(vol)); - - MODIFY_REG(RMU->CR, RMU_CR_BORFLT_MSK, flt << RMU_CR_BORFLT_POSS); - MODIFY_REG(RMU->CR, RMU_CR_BORVS_MSK, vol << RMU_CR_BORVS_POSS); - SET_BIT(RMU->CR, RMU_CR_BOREN_MSK); - } - else { - CLEAR_BIT(RMU->CR, RMU_CR_BOREN_MSK); - } - - SYSCFG_LOCK(); - return; -} - -/** - * @brief Get specified reset status - * @param state: Speicifies the type of the reset, - * @retval The status. - */ -uint32_t ald_rmu_get_reset_status(rmu_state_t state) -{ - assert_param(IS_RMU_STATE(state)); - - if (state == RMU_RST_ALL) - return RMU->RSTSR; - - if (READ_BIT(RMU->RSTSR, state)) - return SET; - - return RESET; -} - -/** - * @brief Clear the specified reset status - * @param state: Specifies the type of the reset, - * @retval None - */ -void ald_rmu_clear_reset_status(rmu_state_t state) -{ - assert_param(IS_RMU_STATE_CLEAR(state)); - - SYSCFG_UNLOCK(); - WRITE_REG(RMU->CRSTSR, state); - SYSCFG_LOCK(); - - return; -} -/** - * @brief Reset peripheral device - * @param perh: The peripheral device, - * @retval None - */ -void ald_rmu_reset_periperal(rmu_peripheral_t perh) -{ - uint32_t idx, pos; - - assert_param(IS_RMU_PERH(perh)); - - idx = ((uint32_t)perh >> 27) & 0x7; - pos = perh & ~(0x7 << 27); - SYSCFG_UNLOCK(); - - switch (idx) { - case 0: - WRITE_REG(RMU->AHB1RSTR, pos); - break; - - case 1: - WRITE_REG(RMU->AHB2RSTR, pos); - break; - - case 2: - WRITE_REG(RMU->APB1RSTR, pos); - break; - - case 4: - WRITE_REG(RMU->APB2RSTR, pos); - break; - - default: - break; - } - - SYSCFG_LOCK(); - return; -} - -/** - * @} - */ -#endif /* ALD_RMU */ -/** - * @} - */ - -/** - * @} - */ diff --git a/bsp/essemi/es32f0334/libraries/ES32F033x_ALD_StdPeriph_Driver/Source/ald_rtc.c b/bsp/essemi/es32f0334/libraries/ES32F033x_ALD_StdPeriph_Driver/Source/ald_rtc.c deleted file mode 100644 index 7391045a62..0000000000 --- a/bsp/essemi/es32f0334/libraries/ES32F033x_ALD_StdPeriph_Driver/Source/ald_rtc.c +++ /dev/null @@ -1,1192 +0,0 @@ -/** - ****************************************************************************** - * @file ald_rtc.c - * @brief RTC module driver. - * This file provides firmware functions to manage the following - * functionalities of the RTC peripheral: - * + Initialization functions - * + Time and date functions - * + Alarm functions - * + Time stamp functions - * + Tamper functions - * + Wake-up functions - * + Clock output functions - * + Peripheral Control functions - * @version V1.0 - * @date 25 Apr 2017 - * @author AE Team - * - * Copyright (C) Shanghai Eastsoft Microelectronics Co. Ltd. All rights reserved. - * - ******************************************************************************** - * @verbatim - ============================================================================== - ##### How to use this driver ##### - ============================================================================== - [..] - (+) Enable the RTC controller interface clock. - (+) Select the RTC source clock(default LOSC). - (+) Configure the RTC asynchronous prescaler, synchronous prescaler and hour - format using the ald_rtc_init() function. - - *** Time and date operation *** - ================================= - [..] - (+) To configure the time use the ald_rtc_set_time() function. - (+) To configure the date use the ald_rtc_set_date() function. - (+) To read the time use the ald_rtc_get_time() function. - (+) To read the date use the ald_rtc_get_date() function. - - *** Alarm operation *** - =================================== - [..] - (+) To configure the alarm use ald_rtc_set_alarm() function - (+) To read the alarm use ald_rtc_get_alarm() function - (+) To cancel the alarm use ald_rtc_alarm_cmd() function - - *** Time stamp operation *** - =================================== - [..] - (+) To configure the time stamp use ald_rtc_set_time_stamp() function - (+) To read the time stamp use ald_rtc_get_time_stamp() function - (+) To cancel the time stamp use ald_rtc_cancel_time_stamp() function - - *** Tamper operation *** - =================================== - [..] - (+) To configure the tamper use ald_rtc_set_tamper() function - (+) To cancel the tamper use ald_rtc_alarm_cmd() function - - *** Wake-up operation *** - =================================== - [..] - (+) To configure the wake-up parameters use ald_rtc_set_wakeup() function - (+) To read the re-load register value use ald_rtc_get_wakeup_timer_value() function - (+) To cancel the wake-up use ald_rtc_cancel_wakeup() function - - *** Output clock operation *** - =================================== - [..] - (+) To configure the clock output type use ald_rtc_set_clock_output() function - (+) To cancel the clock output use ald_rtc_cancel_clock_output() function - - *** Control functions *** - =================================== - [..] - (+) Configure interrupt enable/disable. - (+) Enable/disable alarm. - (+) Configure rtc shift. - (+) Calibrate time. - (+) Get interrupt source status. - (+) Get interrupt flag status. - (+) Clear interrupt flag. - - ================================================================== - ##### RTC and low power modes ##### - ================================================================== - [..] The MCU can be woken up from a low power mode by an RTC alternate function. - [..] The RTC alternate functions are the RTC alarms (Alarm A and Alarm B), - RTC wake-up, RTC tamper event detection and RTC time stamp event detection. - These RTC alternate functions can wake up the system from the Stop and - Standby low power modes. - [..] The system can also wake up from low power modes without depending - on an external interrupt (Auto-wake-up mode), by using the RTC alarm - or the RTC wake-up events. - [..] The RTC provides a programmable time base for waking up from the Stop or - Standby mode at regular intervals. Wake-up from STOP and STANDBY modes - is possible only when the RTC clock source is LSE or LSI. - - *** RTC driver macros list *** - ============================================= - [..] - Below the list of most used macros in RTC driver. - - (+) RTC_UNLOCK() Disable the protect. - (+) RTC_LOCK() Enable the protect. - (+) RTC_BY_PASS_ENABLE() Enable the by-pass shadow register. - (+) RTC_BY_PASS_DISABLE() Disable the by-pass shadow register. - (+) RTC_SUMMER_TIME_ENABLE() Enable summer time. - (+) RTC_SUMMER_TIME_DISABLE() Disable summer time. - (+) RTC_WINTER_TIME_ENABLE() Enable winter time. - (+) RTC_WINTER_TIME_DISABLE() Disable winter time. - [..] - (@) You can refer to the RTC driver header file for used the macros - - @endverbatim - ****************************************************************************** - */ - -#include "ald_rtc.h" -#include "ald_bkpc.h" -#include "ald_tsense.h" -#include "ald_syscfg.h" - - -/** @addtogroup ES32FXXX_ALD - * @{ - */ - -/** @defgroup RTC RTC - * @brief RTC module driver - * @{ - */ -#ifdef ALD_RTC - -/** @addtogroup RTC_Private_Functions RTC Private Functions - * @{ - */ -/** - * @brief Converts form 2 digit BCD to Binary. - * @param bcd: BCD value to be converted. - * @retval Converted word. - */ -static uint32_t bcd_to_dec(uint32_t bcd) -{ - return ((bcd & 0xF) + ((bcd >> 4) & 0xF) * 10); -} - -/** - * @brief Converts a 2 digit decimal to BCD format. - * @param dec: Byte to be converted. - * @retval Converted byte. - */ -static uint32_t dec_to_bcd(uint32_t dec) -{ - return (((dec / 10) << 4) | (dec % 10)); -} - -/** - * @brief Time and Date consistency check. - * @param t_last: Last time. - * @param d_last: Last date. - * @param time: Current time. - * @param date: Current time. - * @retval status: - * 0 - Not consistency - * 1 - Consistency - */ -static int32_t rtc_consistency_check(rtc_time_t *t_last, - rtc_date_t *d_last, rtc_time_t *time, rtc_date_t *date) -{ - if (t_last->second != time->second) - return 0; - if (t_last->minute != time->minute) - return 0; - if (t_last->hour != time->hour) - return 0; - if (d_last->day != date->day) - return 0; - if (d_last->month != date->month) - return 0; - if (d_last->year != date->year) - return 0; - - return 1; -} -/** - * @} - */ - -/** @defgroup RTC_Public_Functions RTC Public Functions - * @{ - */ - -/** @defgroup RTC_Public_Functions_Group1 Initialization functions - * @brief Initialization functions - * - * @verbatim - =============================================================================== - ##### Initialization function ##### - =============================================================================== - [..] This section provides functions allowing to initialize and configure the - RTC Prescaler (Synchronous and Asynchronous), RTC Hour format, disable - RTC registers Write protection. - (#) The RTC Prescaler is programmed to generate the RTC 1Hz time base. - It is split into 2 programmable prescalers to minimize power consumption. - (++) A 7-bit asynchronous prescaler and a 13-bit synchronous prescaler. - (++) When both prescalers are used, it is recommended to configure the - asynchronous prescaler to a high value to minimize power consumption. - (#) All RTC registers are Write protected. Writing to the RTC registers - is enabled by writing a key into the Write Protection register. - - @endverbatim - * @{ - */ - -/** - * @brief Reset RTC register. - * @retval None - */ -void ald_rtc_reset(void) -{ - RTC_UNLOCK(); - - WRITE_REG(RTC->CON, 0x0); - WRITE_REG(RTC->TAMPCON, 0x0); - WRITE_REG(RTC->WUMAT, 0x0); - WRITE_REG(RTC->IER, 0x0); - WRITE_REG(RTC->IFCR, ~0x0); - - RTC_LOCK(); - return; -} - -/** - * @brief Initialize the RTC module. - * @param init: Pointer to rtc_init_t structure which contains - * the configuration parameters. - * @retval None - */ -void ald_rtc_init(rtc_init_t *init) -{ - assert_param(IS_RTC_HOUR_FORMAT(init->hour_format)); - assert_param(IS_RTC_OUTPUT_SEL(init->output)); - assert_param(IS_RTC_OUTPUT_POLARITY(init->output_polarity)); - - ald_rtc_reset(); - RTC_UNLOCK(); - - MODIFY_REG(RTC->CON, RTC_CON_HFM_MSK, init->hour_format << RTC_CON_HFM_POS); - MODIFY_REG(RTC->CON, RTC_CON_EOS_MSK, init->output << RTC_CON_EOS_POSS); - MODIFY_REG(RTC->CON, RTC_CON_POL_MSK, init->output_polarity << RTC_CON_POL_POS); - MODIFY_REG(RTC->PSR, RTC_PSR_SPRS_MSK, init->synch_pre_div << RTC_PSR_SPRS_POSS); - MODIFY_REG(RTC->PSR, RTC_PSR_APRS_MSK, init->asynch_pre_div << RTC_PSR_APRS_POSS); - SET_BIT(RTC->CON, RTC_CON_GO_MSK); - - RTC_LOCK(); - return; -} - -/** - * @brief Configure the RTC source. - * @param sel: RTC source type. - * @retval None - */ -void ald_rtc_source_select(rtc_source_sel_t sel) -{ - assert_param(IS_RTC_SOURCE_SEL(sel)); - - BKPC_UNLOCK(); - MODIFY_REG(BKPC->PCCR, BKPC_PCCR_RTCCS_MSK, sel << BKPC_PCCR_RTCCS_POSS); - - if (sel == RTC_SOURCE_LOSC) { - SET_BIT(BKPC->CR, BKPC_CR_LOSCEN_MSK); - } - else if (sel == RTC_SOURCE_LRC) { - SET_BIT(BKPC->CR, BKPC_CR_LRCEN_MSK); - } - else { - ; /* do nothing */ - } - - BKPC_LOCK(); - return; -} -/** - * @} - */ - -/** @defgroup RTC_Public_Functions_Group2 Time and Date functions - * @brief RTC Time and Date functions - * - * @verbatim - =============================================================================== - ##### Time and Date functions ##### - =============================================================================== - - [..] This section provides functions allowing: - [#] - (+) To configure the time use the ald_rtc_set_time() function. - (+) To configure the date use the ald_rtc_set_date() function. - (+) To read the time use the ald_rtc_get_time() function. - (+) To read the date use the ald_rtc_get_date() function. - - @endverbatim - * @{ - */ - -/** - * @brief Set specified time. - * @param time: pointer to a rtc_time_t structure. - * @param format: Data format. - * @retval ALD status. - */ -ald_status_t ald_rtc_set_time(rtc_time_t *time, rtc_format_t format) -{ - uint32_t tmp; - - assert_param(IS_RTC_FORMAT(format)); - - if (format == RTC_FORMAT_DEC) { - assert_param(IS_RTC_SECOND(time->second)); - assert_param(IS_RTC_MINUTE(time->minute)); - assert_param(IS_RTC_HOUR(time->hour)); - - tmp = (dec_to_bcd(time->second)) | - (dec_to_bcd(time->minute) << 8) | - (dec_to_bcd(time->hour) << 16); - } - else { - assert_param(IS_RTC_SECOND(bcd_to_dec(time->second))); - assert_param(IS_RTC_MINUTE(bcd_to_dec(time->minute))); - assert_param(IS_RTC_HOUR(bcd_to_dec(time->hour))); - - tmp = time->second | (time->minute << 8) | (time->hour << 16); - } - - RTC_UNLOCK(); - WRITE_REG(RTC->TIME, tmp); - RTC_LOCK(); - - tmp = ald_get_tick(); - - while (READ_BIT(RTC->CON, RTC_CON_BUSY_MSK)) { - if ((ald_get_tick() - tmp) > RTC_TIMEOUT_VALUE) - return TIMEOUT; - } - - return OK; -} - -/** - * @brief Set specified date. - * @param date: pointer to a rtc_date_t structure. - * @param format: Data format. - * @retval ALD status. - */ -ald_status_t ald_rtc_set_date(rtc_date_t *date, rtc_format_t format) -{ - uint32_t tmp; - - assert_param(IS_RTC_FORMAT(format)); - - if (format == RTC_FORMAT_DEC) { - assert_param(IS_RTC_DAY(date->day)); - assert_param(IS_RTC_MONTH(date->month)); - assert_param(IS_RTC_YEAR(date->year)); - - tmp = (dec_to_bcd(date->day)) | - (dec_to_bcd(date->month) << 8) | - (dec_to_bcd(date->year) << 16) | - (dec_to_bcd(date->week) << 24); - } - else { - assert_param(IS_RTC_DAY(bcd_to_dec(date->day))); - assert_param(IS_RTC_MONTH(bcd_to_dec(date->month))); - assert_param(IS_RTC_YEAR(bcd_to_dec(date->year))); - - tmp = date->day | (date->month << 8) | - (date->year << 16) | (date->week << 24); - } - - RTC_UNLOCK(); - WRITE_REG(RTC->DATE, tmp); - RTC_LOCK(); - - tmp = ald_get_tick(); - - while (READ_BIT(RTC->CON, RTC_CON_BUSY_MSK)) { - if ((ald_get_tick() - tmp) > RTC_TIMEOUT_VALUE) - return TIMEOUT; - } - - return OK; -} - -/** - * @brief Get current time. - * @param time: pointer to a rtc_time_t structure. - * @param format: Data format. - * @retval None - */ -void ald_rtc_get_time(rtc_time_t *time, rtc_format_t format) -{ - uint32_t tmp; - - assert_param(time != NULL); - assert_param(IS_RTC_FORMAT(format)); - - time->sub_sec = RTC->SSEC & 0xFFFF; - tmp = RTC->TIME; - - if (format == RTC_FORMAT_DEC) { - time->second = bcd_to_dec(tmp & 0x7F); - time->minute = bcd_to_dec((tmp >> 8) & 0x7F); - time->hour = bcd_to_dec((tmp >> 16) & 0x7F); - } - else { - time->second = tmp & 0x7F; - time->minute = (tmp >> 8) & 0x7F; - time->hour = (tmp >> 16) & 0x7F; - } - - return; -} - -/** - * @brief Get current date. - * @param date: pointer to a rtc_date_t structure. - * @param format: Data format. - * @retval None - */ -void ald_rtc_get_date(rtc_date_t *date, rtc_format_t format) -{ - uint32_t tmp = RTC->DATE; - - assert_param(date != NULL); - assert_param(IS_RTC_FORMAT(format)); - - if (format == RTC_FORMAT_DEC) { - date->day = bcd_to_dec(tmp & 0x3F); - date->month = bcd_to_dec((tmp >> 8) & 0x1F); - date->year = bcd_to_dec((tmp >> 16) & 0xFF); - date->week = bcd_to_dec((tmp >> 24) & 0x7); - } - else { - date->day = tmp & 0x3F; - date->month = (tmp >> 8) & 0x1F; - date->year = (tmp >> 16) & 0xFF; - date->week = (tmp >> 24) & 0x7; - } - - return; -} - -/** - * @brief Get time and date consistency. - * @param date: pointer to a rtc_date_t structure. - * @param time: pointer to a rtc_time_t structure. - * @param format: Data format. - * @retval Status: - * 0 - Consistency - * -1 - Not consistency - */ -int32_t ald_rtc_get_date_time(rtc_date_t *date, rtc_time_t *time, rtc_format_t format) -{ - int32_t nr = 3; - rtc_date_t d_last; - rtc_time_t t_last; - - while (nr--) { - ald_rtc_get_time(&t_last, format); - ald_rtc_get_date(&d_last, format); - ald_rtc_get_time(time, format); - ald_rtc_get_date(date, format); - - if (rtc_consistency_check(&t_last, &d_last, time, date)) - return 0; - } - - return -1; -} -/** - * @} - */ - -/** @defgroup RTC_Public_Functions_Group3 Alarm functions - * @brief RTC alarm functions - * - * @verbatim - =============================================================================== - ##### Alarm functions ##### - =============================================================================== - - [..] This section provides functions allowing: - [#] - (+) To configure the alarm use ald_rtc_set_alarm() function - (+) To read the alarm use ald_rtc_get_alarm() function - - @endverbatim - * @{ - */ - -/** - * @brief Set alarm. - * @param alarm: pointer to rtc_alarm_t struct. - * @param format: Data format. - * @retval None - */ -void ald_rtc_set_alarm(rtc_alarm_t *alarm, rtc_format_t format) -{ - unsigned int tmp, ss_tmp; - - assert_param(IS_RTC_ALARM(alarm->idx)); - assert_param(IS_RTC_ALARM_SEL(alarm->sel)); - assert_param(IS_RTC_ALARM_SS_MASK(alarm->ss_mask)); - assert_param(IS_RTC_FORMAT(format)); - - if (format == RTC_FORMAT_DEC) { - assert_param(IS_RTC_SECOND(alarm->time.second)); - assert_param(IS_RTC_MINUTE(alarm->time.minute)); - assert_param(IS_RTC_HOUR(alarm->time.hour)); - - tmp = (dec_to_bcd(alarm->time.second)) | - (dec_to_bcd(alarm->time.minute) << 8) | - (dec_to_bcd(alarm->time.hour) << 16) | - alarm->mask; - - if (alarm->sel == RTC_SELECT_DAY) { - assert_param(IS_RTC_DAY(alarm->day)); - - tmp |= (dec_to_bcd(alarm->day) << 24); - tmp &= 0x7FFFFFFF; /* Reset bit31 */ - } - else { - tmp |= (1 << (alarm->week + 24)); - tmp |= 0x80000000; /* Set bit31 */ - } - } - else { - assert_param(IS_RTC_SECOND(bcd_to_dec(alarm->time.second))); - assert_param(IS_RTC_MINUTE(bcd_to_dec(alarm->time.minute))); - assert_param(IS_RTC_HOUR(bcd_to_dec(alarm->time.hour))); - - tmp = alarm->time.second | - (alarm->time.minute << 8) | - (alarm->time.hour << 16) | - alarm->mask; - - if (alarm->sel == RTC_SELECT_DAY) { - assert_param(IS_RTC_DAY(bcd_to_dec(alarm->day))); - - tmp |= (alarm->day << 24); - tmp &= 0x7FFFFFFF; /* Reset bit31 */ - } - else { - tmp |= (1 << (alarm->week + 24)); - tmp |= 0x80000000; /* Set bit31 */ - } - } - - ss_tmp = (alarm->time.sub_sec & 0x7F) | - (alarm->ss_mask << 24); - - RTC_UNLOCK(); - - if (alarm->idx == RTC_ALARM_A) { - WRITE_REG(RTC->ALMA, tmp); - WRITE_REG(RTC->ALMASSEC, ss_tmp); - SET_BIT(RTC->CON, RTC_CON_ALMAEN_MSK); - } - else { - WRITE_REG(RTC->ALMB, tmp); - WRITE_REG(RTC->ALMBSSEC, ss_tmp); - SET_BIT(RTC->CON, RTC_CON_ALMBEN_MSK); - } - - RTC_LOCK(); - return; -} - -/** - * @brief Get alarm parameters. - * @param alarm: pointer to rtc_alarm_t struct. - * @param format: Data format. - * @retval None - */ -void ald_rtc_get_alarm(rtc_alarm_t *alarm, rtc_format_t format) -{ - uint8_t week; - uint32_t tmp, ss_tmp; - - assert_param(alarm != NULL); - assert_param(IS_RTC_FORMAT(format)); - - if (alarm->idx == RTC_ALARM_A) { - tmp = RTC->ALMA; - ss_tmp = RTC->ALMASSEC; - } - else { - tmp = RTC->ALMB; - ss_tmp = RTC->ALMBSSEC; - } - - if ((tmp >> 31) & 0x1) { - alarm->sel = RTC_SELECT_WEEK; - week = ((tmp >> 24) & 0x7F); - - switch (week) { - case 1: - alarm->week = 0; - break; - case 2: - alarm->week = 1; - break; - case 4: - alarm->week = 2; - break; - case 8: - alarm->week = 3; - break; - case 16: - alarm->week = 4; - break; - case 32: - alarm->week = 5; - break; - case 64: - alarm->week = 6; - break; - default: - break; - } - } - else { - alarm->sel = RTC_SELECT_DAY; - - if (format == RTC_FORMAT_DEC) - alarm->day = bcd_to_dec((tmp >> 24) & 0x3F); - else - alarm->day = (tmp >> 24) & 0x3F; - } - - if (format == RTC_FORMAT_DEC) { - alarm->time.second = bcd_to_dec(tmp & 0x7F); - alarm->time.minute = bcd_to_dec((tmp >> 8) & 0x7F); - alarm->time.hour = bcd_to_dec((tmp >> 16) & 0x3F); - } - else { - alarm->time.second = tmp & 0x7F; - alarm->time.minute = (tmp >> 8) & 0x7F; - alarm->time.hour = (tmp >> 16) & 0x3F; - } - - alarm->time.sub_sec = ss_tmp & 0x7FFF; - alarm->ss_mask = (rtc_sub_second_mask_t)((ss_tmp >> 24) & 0xF); - alarm->mask = tmp & ALARM_MASK_ALL; - - return; -} -/** - * @} - */ - -/** @defgroup RTC_Public_Functions_Group4 Time stamp functions - * @brief RTC time stamp functions - * - * @verbatim - =============================================================================== - ##### Time stamp functions ##### - =============================================================================== - - [..] This section provides functions allowing: - [#] - (+) To configure the time stamp use ald_rtc_set_time_stamp() function - (+) To read the time stamp use ald_rtc_get_time_stamp() function - (+) To cancel the time stamp use ald_rtc_cancel_time_stamp() function - - @endverbatim - * @{ - */ - -/** - * @brief Set time stamp. - * @param sel: time stamp signal select: - * @arg RTC_TS_SIGNAL_SEL_TAMPER0 - * @arg RTC_TS_SIGNAL_SEL_TAMPER1 - * @param style: time stamp trigger style: - * @arg RTC_TS_RISING_EDGE - * @arg RTC_TS_FALLING_EDGE - * @retval None - */ -void ald_rtc_set_time_stamp(rtc_ts_signal_sel_t sel, rtc_ts_trigger_style_t style) -{ - assert_param(IS_RTC_TS_SIGNAL(sel)); - assert_param(IS_RTC_TS_STYLE(style)); - - RTC_UNLOCK(); - - CLEAR_BIT(RTC->CON, RTC_CON_TSEN_MSK); - MODIFY_REG(RTC->CON, RTC_CON_TSSEL_MSK, style << RTC_CON_TSSEL_POS); - MODIFY_REG(RTC->CON, RTC_CON_TSPIN_MSK, sel << RTC_CON_TSPIN_POS); - SET_BIT(RTC->CON, RTC_CON_TSEN_MSK); - - RTC_LOCK(); - return; -} - -/** - * @brief Cancel time stamp. - * @retval None - */ -void ald_rtc_cancel_time_stamp(void) -{ - RTC_UNLOCK(); - CLEAR_BIT(RTC->CON, RTC_CON_TSEN_MSK); - RTC_LOCK(); - - return; -} - -/** - * @brief Get time stamp value. - * @param ts_time: pointer to rtc_time_t structure. - * @param ts_date: pointer to rtc_date_t structure. - * @param format: Data format. - * @retval None - */ -void ald_rtc_get_time_stamp(rtc_time_t *ts_time, rtc_date_t *ts_date, rtc_format_t format) -{ - uint32_t tmp0, tmp1; - - assert_param(ts_time != NULL); - assert_param(ts_date != NULL); - assert_param(IS_RTC_FORMAT(format)); - - ts_time->sub_sec = RTC->TSSSEC & 0xFFFF; - tmp0 = RTC->TSTIME; - tmp1 = RTC->TSDATE; - - if (format == RTC_FORMAT_DEC) { - ts_time->second = bcd_to_dec(tmp0 & 0x7F); - ts_time->minute = bcd_to_dec((tmp0 >> 8) & 0x7F); - ts_time->hour = bcd_to_dec((tmp0 >> 16) & 0x3F); - ts_date->day = bcd_to_dec(tmp1 & 0x3F); - ts_date->month = bcd_to_dec((tmp1 >> 8) & 0x1F); - ts_date->year = bcd_to_dec((tmp1 >> 16) & 0xFF); - ts_date->week = bcd_to_dec((tmp1 >> 24) & 0x7); - } - else { - ts_time->second = tmp0 & 0x7F; - ts_time->minute = (tmp0 >> 8) & 0x7F; - ts_time->hour = (tmp0 >> 16) & 0x3F; - ts_date->day = tmp1 & 0x3F; - ts_date->month = (tmp1 >> 8) & 0x1F; - ts_date->year = (tmp1 >> 16) & 0xFF; - ts_date->week = (tmp1 >> 24) & 0x7; - } - - return; -} -/** - * @} - */ - -/** @defgroup RTC_Public_Functions_Group5 Tamper functions - * @brief RTC tamper functions - * - * @verbatim - =============================================================================== - ##### Tamper functions ##### - =============================================================================== - - [..] This section provides functions allowing: - [#] - (+) To configure the tamper use ald_rtc_set_tamper() function - (+) To cancel the tamper use ald_rtc_alarm_cmd() function - - @endverbatim - * @{ - */ -/** - * @brief Set tamper parameters. - * @param tamper: pointer to rtc_tamper_t structure. - * @retval None - */ -void ald_rtc_set_tamper(rtc_tamper_t *tamper) -{ - assert_param(IS_RTC_TAMPER(tamper->idx)); - assert_param(IS_RTC_TAMPER_TRIGGER(tamper->trig)); - assert_param(IS_RTC_TAMPER_SAMPLING_FREQ(tamper->freq)); - assert_param(IS_RTC_TAMPER_DURATION(tamper->dur)); - assert_param(IS_FUNC_STATE(tamper->ts)); - - RTC_UNLOCK(); - MODIFY_REG(RTC->TAMPCON, RTC_TAMPCON_TAMPTS_MSK, tamper->ts << RTC_TAMPCON_TAMPTS_POS); - MODIFY_REG(RTC->TAMPCON, RTC_TAMPCON_TAMPCKS_MSK, tamper->freq << RTC_TAMPCON_TAMPCKS_POSS); - MODIFY_REG(RTC->TAMPCON, RTC_TAMPCON_TAMPFLT_MSK, tamper->dur << RTC_TAMPCON_TAMPFLT_POSS); - - if (tamper->idx == RTC_TAMPER_0) { - MODIFY_REG(RTC->TAMPCON, RTC_TAMPCON_TAMP0LV_MSK, tamper->trig << RTC_TAMPCON_TAMP0LV_POS); - SET_BIT(RTC->TAMPCON, RTC_TAMPCON_TAMP0EN_MSK); - } - else { - MODIFY_REG(RTC->TAMPCON, RTC_TAMPCON_TAMP1LV_MSK, tamper->trig << RTC_TAMPCON_TAMP1LV_POS); - SET_BIT(RTC->TAMPCON, RTC_TAMPCON_TAMP1EN_MSK); - } - - RTC_LOCK(); - return; -} - -/** - * @brief Cancel tamper. - * @param idx: index of tamper: - * @arg RTC_TAMPER_0 - * @arg RTC_TAMPER_1 - * @retval None - */ -void ald_rtc_cancel_tamper(rtc_tamper_idx_t idx) -{ - assert_param(IS_RTC_TAMPER(idx)); - - RTC_UNLOCK(); - - if (idx == RTC_TAMPER_0) - CLEAR_BIT(RTC->TAMPCON, RTC_TAMPCON_TAMP0EN_MSK); - else - CLEAR_BIT(RTC->TAMPCON, RTC_TAMPCON_TAMP1EN_MSK); - - RTC_LOCK(); - return; -} -/** - * @} - */ - -/** @defgroup RTC_Public_Functions_Group6 Wake-up functions - * @brief RTC wake-up functions - * - * @verbatim - =============================================================================== - ##### Wake-up functions ##### - =============================================================================== - - [..] This section provides functions allowing: - [#] - (+) To configure the wake-up parameters use ald_rtc_set_wakeup() function - (+) To read the re-load register value use ald_rtc_get_wakeup_timer_value() function - (+) To cancel the wake-up use ald_rtc_cancel_wakeup() function - - @endverbatim - * @{ - */ -/** - * @brief Set wake-up parameters. - * @param clock: pointer to rtc_wakeup_clock_t structure. - * @param value: re-load value. - * @retval None - */ -void ald_rtc_set_wakeup(rtc_wakeup_clock_t clock, uint16_t value) -{ - assert_param(IS_RTC_WAKEUP_CLOCK(clock)); - - RTC_UNLOCK(); - MODIFY_REG(RTC->CON, RTC_CON_WUCKS_MSK, clock << RTC_CON_WUCKS_POSS); - WRITE_REG(RTC->WUMAT, value & 0xFFFF); - SET_BIT(RTC->CON, RTC_CON_WUTE_MSK); - RTC_LOCK(); - - return; -} - -/** - * @brief Cancel wake-up. - * @retval None - */ -void ald_rtc_cancel_wakeup(void) -{ - RTC_UNLOCK(); - CLEAR_BIT(RTC->CON, RTC_CON_WUTE_MSK); - RTC_LOCK(); - - return; -} - -/** - * @brief Get wake-up re-load register value. - * @retval Value of re-load register. - */ -uint16_t ald_rtc_get_wakeup_timer_value(void) -{ - return RTC->WUMAT & 0xFFFF; -} -/** - * @} - */ - -/** @defgroup RTC_Public_Functions_Group7 Clock output functions - * @brief RTC clock output functions - * - * @verbatim - =============================================================================== - ##### Clock output functions ##### - =============================================================================== - - [..] This section provides functions allowing: - [#] - (+) To configure the clock output type use ald_rtc_set_clock_output() function - (+) To cancel the clock output use ald_rtc_cancel_clock_output() function - - @endverbatim - * @{ - */ -/** - * @brief Set clock output parameters. - * @param clock: pointer to rtc_clock_output_t structure. - * @retval ALD status. - */ -ald_status_t ald_rtc_set_clock_output(rtc_clock_output_t clock) -{ - uint32_t cnt = 4000; - assert_param(IS_RTC_CLOCK_OUTPUT(clock)); - - SYSCFG_UNLOCK(); - - if (clock == RTC_CLOCK_OUTPUT_EXA_1) { - SET_BIT(CMU->CLKENR, CMU_CLKENR_PLL2EN_MSK); - while ((READ_BIT(CMU->PLLCFG, CMU_PLLCFG_PLL2LCKN_MSK)) && (--cnt)); - cnt = 4000; - while ((!(READ_BIT(CMU->CLKSR, CMU_CLKSR_PLL2RDY_MSK))) && (--cnt)); - } - else { - CLEAR_BIT(CMU->CLKENR, CMU_CLKENR_PLL2EN_MSK); - } - - SYSCFG_LOCK(); - RTC_UNLOCK(); - MODIFY_REG(RTC->CON, RTC_CON_CKOS_MSK, clock << RTC_CON_CKOS_POSS); - SET_BIT(RTC->CON, RTC_CON_CKOE_MSK); - RTC_LOCK(); - - return OK; -} - -/** - * @brief Cancel clock output. - * @retval None - */ -void ald_rtc_cancel_clock_output(void) -{ - RTC_UNLOCK(); - CLEAR_BIT(RTC->CON, RTC_CON_CKOE_MSK); - RTC_LOCK(); - - return; -} -/** - * @} - */ - -/** @defgroup RTC_Public_Functions_Group8 Control functions - * @brief RTC control functions - * - * @verbatim - =============================================================================== - ##### Control functions ##### - =============================================================================== - - [..] This section provides functions allowing: - [#] - (+) Configure interrupt enable/disable. - (+) Enable/disable alarm. - (+) Configure rtc shift. - (+) Calibrate time. - (+) Get interrupt source status. - (+) Get interrupt flag status. - (+) Clear interrupt flag. - - @endverbatim - * @{ - */ -/** - * @brief Enable/disable the specified RTC interrupts. - * @param it: Specifies the RTC interrupt sources to be enabled or disabled. - * This parameter can be one of the @ref rtc_it_t. - * @param state: New state of the specified RTC interrupts. - * This parameter can be: - * @arg ENABLE - * @arg DISABLE - * @retval None - */ -void ald_rtc_interrupt_config(rtc_it_t it, type_func_t state) -{ - assert_param(IS_RTC_IT(it)); - assert_param(IS_FUNC_STATE(state)); - - RTC_UNLOCK(); - - if (state == ENABLE) - SET_BIT(RTC->IER, it); - else - CLEAR_BIT(RTC->IER, it); - - RTC_LOCK(); - return; -} - -/** - * @brief Enable/Disable alarm. - * @param idx: index of alarm: - * @arg RTC_ALARM_A - * @arg RTC_ALARM_B - * @param state: New status of the specified alarm: - * @arg ENABLE - * @arg DISABLE - * @retval None - */ -void ald_rtc_alarm_cmd(rtc_alarm_idx_t idx, type_func_t state) -{ - assert_param(IS_RTC_ALARM(idx)); - assert_param(IS_FUNC_STATE(state)); - - RTC_UNLOCK(); - - if (idx == RTC_ALARM_A) - MODIFY_REG(RTC->CON, RTC_CON_ALMAEN_MSK, state << RTC_CON_ALMAEN_POS); - else - MODIFY_REG(RTC->CON, RTC_CON_ALMBEN_MSK, state << RTC_CON_ALMBEN_POS); - - RTC_LOCK(); - return; -} - -/** - * @brief Set shift parameters. - * @param add_1s: Enable/Disable added 1 second. - * @param sub_ss: value of sub-sconde. - * @retval ALD status. - */ -ald_status_t ald_rtc_set_shift(type_func_t add_1s, uint16_t sub_ss) -{ - uint32_t tick; - - assert_param(IS_FUNC_STATE(add_1s)); - assert_param(IS_SHIFT_SUB_SS(sub_ss)); - - RTC_UNLOCK(); - MODIFY_REG(RTC->SSECTR, RTC_SSECTR_TRIM_MSK, sub_ss << RTC_SSECTR_TRIM_POSS); - MODIFY_REG(RTC->SSECTR, RTC_SSECTR_INC_MSK, add_1s << RTC_SSECTR_INC_POS); - RTC_LOCK(); - - tick = ald_get_tick(); - - while (READ_BIT(RTC->CON, RTC_CON_SSEC_MSK)) { - if ((ald_get_tick() - tick) > RTC_TIMEOUT_VALUE) - return TIMEOUT; - } - - return OK; -} - -/** - * @brief Set calibation - * @param config: pointer to rtc_cali_t structure. - * @retval None - */ -void ald_rtc_set_cali(rtc_cali_t *config) -{ - assert_param(IS_RTC_CALI_FREQ(config->cali_freq)); - assert_param(IS_RTC_CALI_TC(config->tc)); - assert_param(IS_RTC_CALC_FREQ(config->calc_freq)); - assert_param(IS_RTC_CALI_CALC(config->calc)); - assert_param(IS_FUNC_STATE(config->acc)); - - RTC_UNLOCK(); - RTC_CALI_UNLOCK(); - - MODIFY_REG(RTC->CALCON, RTC_CALCON_CALP_MSK, config->cali_freq << RTC_CALCON_CALP_POSS); - MODIFY_REG(RTC->CALCON, RTC_CALCON_TCM_MSK, config->tc << RTC_CALCON_TCM_POSS); - MODIFY_REG(RTC->CALCON, RTC_CALCON_TCP_MSK, config->calc_freq << RTC_CALCON_TCP_POSS); - MODIFY_REG(RTC->CALCON, RTC_CALCON_ALG_MSK, config->calc << RTC_CALCON_ALG_POS); - MODIFY_REG(RTC->CALCON, RTC_CALCON_DCMACC_MSK, config->acc << RTC_CALCON_DCMACC_POS); - SET_BIT(RTC->CALCON, RTC_CALCON_CALEN_MSK); - - RTC_CALI_LOCK(); - RTC_LOCK(); - - return; -} - -/** - * @brief Cancel calibration - * @retval None - */ -void ald_rtc_cancel_cali(void) -{ - RTC_CALI_UNLOCK(); - CLEAR_BIT(RTC->CALCON, RTC_CALCON_CALEN_MSK); - RTC_CALI_LOCK(); - - return; -} - -/** - * @brief Get calibration status. - * @retval ALD status. - */ -ald_status_t ald_rtc_get_cali_status(void) -{ - if (READ_BIT(RTC->CALCON, RTC_CALCON_ERR_MSK)) - return ERROR; - else - return OK; -} - -/** - * @brief Write temperature value. - * @param temp: the value of temperature. - * @retval None - */ -void ald_rtc_write_temp(uint16_t temp) -{ - RTC_CALI_UNLOCK(); - MODIFY_REG(RTC->TEMPR, RTC_TEMPR_VAL_MSK, temp << RTC_TEMPR_VAL_POSS); - RTC_CALI_LOCK(); - - return; -} - -/** - * @brief Get the status of RTC interrupt source. - * @param it: Specifies the RTC interrupt source. - * This parameter can be one of the @ref rtc_it_t. - * @retval Status: - * - 0: RESET - * - 1: SET - */ -it_status_t ald_rtc_get_it_status(rtc_it_t it) -{ - assert_param(IS_RTC_IT(it)); - - if (READ_BIT(RTC->IER, it)) - return SET; - - return RESET; -} - -/** - * @brief Get the status of RTC interrupt flag. - * @param flag: Specifies the RTC interrupt flag. - * This parameter can be one of the @ref rtc_flag_t. - * @retval Status: - * - 0: RESET - * - 1: SET - */ -flag_status_t ald_rtc_get_flag_status(rtc_flag_t flag) -{ - assert_param(IS_RTC_IF(flag)); - - if (READ_BIT(RTC->IFR, flag)) - return SET; - - return RESET; -} - -/** @brief Clear the specified RTC pending flag. - * @param flag: specifies the flag to check. - * @retval None. - */ -void ald_rtc_clear_flag_status(rtc_flag_t flag) -{ - assert_param(IS_RTC_IF(flag)); - - RTC_UNLOCK(); - WRITE_REG(RTC->IFCR, flag); - RTC_LOCK(); - - return; -} -/** - * @} - */ -/** - * @} - */ -#endif /* ALD_RTC */ -/** - * @} - */ -/** - * @} - */ diff --git a/bsp/essemi/es32f0334/libraries/ES32F033x_ALD_StdPeriph_Driver/Source/ald_smartcard.c b/bsp/essemi/es32f0334/libraries/ES32F033x_ALD_StdPeriph_Driver/Source/ald_smartcard.c deleted file mode 100644 index 2b3552ab77..0000000000 --- a/bsp/essemi/es32f0334/libraries/ES32F033x_ALD_StdPeriph_Driver/Source/ald_smartcard.c +++ /dev/null @@ -1,925 +0,0 @@ -/** - ********************************************************************************* - * - * @file ald_smartcard.c - * @brief SMARTCARD module driver. - * This file provides firmware functions to manage the following - * functionalities of the SMARTCARD peripheral: - * + Initialization functions - * + IO operation functions - * + Peripheral State and Errors functions - * - * @version V1.0 - * @date 25 Apr 2017 - * @author AE Team - * @note - * - * Copyright (C) Shanghai Eastsoft Microelectronics Co. Ltd. All rights reserved. - * - ********************************************************************************* - * @verbatim - ============================================================================== - ##### How to use this driver ##### - ============================================================================== - [..] - The SMARTCARD driver can be used as follows: - - (#) Declare a smartcard_handle_t handle structure. - (##) Enable the interface clock of the USARTx associated to the SMARTCARD. - (##) SMARTCARD pins configuration: - (+++) Enable the clock for the SMARTCARD GPIOs. - (+++) Configure the USART pins (TX as alternate function pull-up, RX as alternate function Input). - (##) NVIC configuration if you need to use interrupt process (ald_smartcard_send_by_it() - and ald_smartcard_recv_by_it() APIs): - (+++) Configure the USARTx interrupt priority. - (+++) Enable the NVIC USART IRQ handle. - (##) DMA Configuration if you need to use DMA process (ald_smartcard_send_by_dma() - and ald_smartcard_recv_by_dma() APIs): - (+++) Declare a DMA handle structure for the Tx/Rx channel. - (+++) Enable the DMAx interface clock. - (+++) Configure the declared DMA handle structure with the required Tx/Rx parameters. - (+++) Configure the DMA Tx/Rx channel. - (+++) Associate the initilalized DMA handle to the SMARTCARD DMA Tx/Rx handle. - (+++) Configure the priority and enable the NVIC for the transfer complete interrupt on the DMA Tx/Rx channel. - (+++) Configure the USARTx interrupt priority and enable the NVIC USART IRQ handle - (used for last byte sending completion detection in DMA non circular mode) - - (#) Program the Baud Rate, Word Length , Stop Bit, Parity, Hardware - flow control and Mode(Receiver/Transmitter) in the SMARTCARD Init structure. - - (#) Initialize the SMARTCARD registers by calling the ald_smartcard_init() API. - - (#) Three operation modes are available within this driver : - - *** Polling mode IO operation *** - ================================= - [..] - (+) Send an amount of data in blocking mode using ald_smartcard_send() - (+) Receive an amount of data in blocking mode using ald_smartcard_recv() - - *** Interrupt mode IO operation *** - =================================== - [..] - (+) Send an amount of data in non blocking mode using ald_smartcard_send_by_it() - (+) At transmission end of transfer hperh->tx_cplt_cbk() is executed and user can - add his own code by customization of function pointer hperh->tx_cplt_cbk() - (+) Receive an amount of data in non blocking mode using ald_smartcard_recv_by_it() - (+) At reception end of transfer hperh->rx_cplt_cbk() is executed and user can - add his own code by customization of function pointer hperh->rx_cplt_cbk() - (+) In case of transfer Error, hperh->error_cbk() function is executed and user can - add his own code by customization of function pointer hperh->error_cbk() - - *** DMA mode IO operation *** - ============================== - [..] - (+) Send an amount of data in non blocking mode (DMA) using ald_smartcard_send_by_dma() - (+) At transmission end of transfer hperh->tx_cplt_cbk() is executed and user can - add his own code by customization of function pointer hperh->tx_cplt_cbk() - (+) Receive an amount of data in non blocking mode (DMA) using ald_smartcard_recv_by_dma() - (+) At reception end of transfer hperh->rx_cplt_cbk() is executed and user can - add his own code by customization of function pointer hperh->rx_cplt_cbk() - (+) In case of transfer Error, hperh->error_cbk()() function is executed and user can - add his own code by customization of function pointer hperh->error_cbk() - - *** SMARTCARD ALD driver macros list *** - ======================================== - [..] - Below the list of most used macros in SMARTCARD ALD driver. - - (+) SMARTCARD_ENABLE: Enable the SmartCard peripheral. - (+) SMARTCARD_DISABLE: Disable the SmartCard peripheral. - (+) smartcard_reset_HANDLE_STATE : Reset SmartCard handle. - (+) SMARTCARD_FLUSH_DRREGISTER : Flush SmartCard data. - - [..] - (@) You can refer to the SMARTCARD library header file for more useful macros - - @endverbatim - ****************************************************************************** - */ - - -#include "ald_smartcard.h" -#include "ald_cmu.h" - - -/** @addtogroup ES32FXXX_ALD - * @{ - */ - -/** @defgroup SMARTCARD SMARTCARD - * @brief SMARTCARD module driver - * @{ - */ - -#ifdef ALD_SMARTCARD - -/** @addtogroup SMARTCARD_Private_Functions SMARTCARD Private Functions - * @{ - */ -static ald_status_t __smartcard_send_by_it(smartcard_handle_t *hperh); -static ald_status_t __smartcard_end_send_by_it(smartcard_handle_t *hsmartcard); -static ald_status_t __smartcard_recv_by_it(smartcard_handle_t *hperh); -static void smartcard_set_config(smartcard_handle_t *hperh); -#ifdef ALD_DMA -static void smartcard_dma_send_cplt(void *arg); -static void smartcard_dma_recv_cplt(void *arg); -static void smartcard_dma_error(void *arg); -#endif -static ald_status_t smartcard_wait_flag(smartcard_handle_t *hperh, usart_flag_t flag, flag_status_t status, uint32_t timeout); -/** - * @} - */ - -/** @defgroup SMARTCARD_Public_Functions SMARTCARD Public Functions - * @{ - */ - -/** @defgroup SMARTCARD_Public_Functions_Group1 Initialization functions - * @brief Initialization and Configuration functions - * - * @verbatim - - ============================================================================== - ##### Initialization and Configuration functions ##### - ============================================================================== - [..] - This subsection provides a set of functions allowing to initialize the USART - in Smartcard mode. - [..] - The Smartcard interface is designed to support asynchronous protocol Smartcards as - defined in the ISO 7816-3 standard. - [..] - The USART can provide a clock to the smartcard through the SCLK output. - In smartcard mode, SCLK is not associated to the communication but is simply derived - from the internal peripheral input clock through a 5-bit prescaler. - [..] - (+) For the Smartcard mode only these parameters can be configured: - (++) Baud Rate - (++) Word Length => Should be 9 bits (8 bits + parity) - (++) Stop Bit - (++) Parity: => Should be enabled - (++) USART polarity - (++) USART phase - (++) USART LastBit - (++) Receiver/transmitter modes - (++) Prescaler - (++) GuardTime - (++) NACKState: The Smartcard NACK state - - (+) Recommended SmartCard interface configuration to get the Answer to Reset from the Card: - (++) word Length = 9 Bits - (++) 1.5 Stop Bit - (++) Even parity - (++) BaudRate = 12096 baud - (++) Tx and Rx enabled - [..] - Please refer to the ISO 7816-3 specification for more details. - - (@) It is also possible to choose 0.5 stop bit for receiving but it is recommended - to use 1.5 stop bits for both transmitting and receiving to avoid switching - between the two configurations. - [..] - The ald_smartcard_init() function follows the USART SmartCard configuration procedure. - - @endverbatim - * @{ - */ - -/* - Additionnal remark on the smartcard frame: - +-------------------------------------------------------------+ - | M bit | PCE bit | SMARTCARD frame | - |---------------------|---------------------------------------| - | 1 | 1 | | SB | 8 bit data | PB | STB | | - +-------------------------------------------------------------+ -*/ - -/** - * @brief Initializes the SmartCard mode according to the specified - * parameters in the smartcard_handle_t and create the associated handle. - * @param hperh: Pointer to a smartcard_handle_t structure that contains - * the configuration information for the specified SMARTCARD module. - * @retval Status, see @ref ald_status_t. - */ -ald_status_t ald_smartcard_init(smartcard_handle_t *hperh) -{ - assert_param(IS_USART_WORD_LENGTH(hperh->init.word_length)); - assert_param(IS_USART_STOPBITS(hperh->init.stop_bits)); - assert_param(IS_USART_PARITY(hperh->init.parity)); - assert_param(IS_USART(hperh->perh)); - assert_param(IS_FUNC_STATE(hperh->init.nack)); - assert_param(IS_SMARTCARD_PRESCALER(hperh->init.prescaler)); - - if (hperh->state == SMARTCARD_STATE_RESET) - hperh->lock = UNLOCK; - - hperh->state = SMARTCARD_STATE_BUSY; - SMARTCARD_DISABLE(hperh); - - MODIFY_REG(hperh->perh->GP, USART_GP_PSC_MSK, hperh->init.prescaler << USART_GP_PSC_POSS); - MODIFY_REG(hperh->perh->GP, USART_GP_GTVAL_MSK, hperh->init.guard_time << USART_GP_GTVAL_POSS); - smartcard_set_config(hperh); - - CLEAR_BIT(hperh->perh->CON2, USART_CON2_IREN_MSK); - CLEAR_BIT(hperh->perh->CON2, USART_CON2_HDPSEL_MSK); - - SMARTCARD_ENABLE(hperh); - MODIFY_REG(hperh->perh->CON2, USART_CON2_NACK_MSK, hperh->init.nack << USART_CON2_NACK_POS); - SET_BIT(hperh->perh->CON2, USART_CON2_SMARTEN_MSK); - - hperh->err_code = SMARTCARD_ERROR_NONE; - hperh->state = SMARTCARD_STATE_READY; - return OK; -} - -/** - * @brief Reset SMARTCARD register. - * @param hperh: Pointer to a smartcard_handle_t structure that contains - * the configuration information for the specified SMARTCARD module. - * @retval Status, see @ref ald_status_t. - */ -ald_status_t ald_smartcard_reset(smartcard_handle_t *hperh) -{ - assert_param(IS_USART(hperh->perh)); - - hperh->state = SMARTCARD_STATE_BUSY; - SMARTCARD_DISABLE(hperh); - - WRITE_REG(hperh->perh->CON0, 0x0); - WRITE_REG(hperh->perh->CON1, 0x0); - WRITE_REG(hperh->perh->CON2, 0x0); - WRITE_REG(hperh->perh->BAUDCON, 0x0); - WRITE_REG(hperh->perh->GP, 0x0); - - hperh->err_code = SMARTCARD_ERROR_NONE; - hperh->state = SMARTCARD_STATE_RESET; - __UNLOCK(hperh); - - return OK; -} -/** - * @} - */ - -/** @defgroup SMARTCARD_Public_Functions_Group2 IO operation functions - * @brief SMARTCARD Transmit and Receive functions - * - * @verbatim - ============================================================================== - ##### IO operation functions ##### - ============================================================================== - [..] - This subsection provides a set of functions allowing to manage the SMARTCARD data transfers. - - [..] - (#) Smartcard is a single wire half duplex communication protocol. - The Smartcard interface is designed to support asynchronous protocol Smartcards as - defined in the ISO 7816-3 standard. - (#) The USART should be configured as: - (++) 8 bits plus parity: where M=1 and PCE=1 in the USART_CR1 register - (++) 1.5 stop bits when transmitting and receiving: where STOP=11 in the USART_CR2 register. - - (#) There are two modes of transfer: - (++) Blocking mode: The communication is performed in polling mode. - The library status of all data processing is returned by the same function - after finishing transfer. - (++) No-Blocking mode: The communication is performed using Interrupts - or DMA, the relevant API's return the library status. - The end of the data processing will be indicated through the - dedicated SMARTCARD IRQ when using Interrupt mode or the DMA IRQ when - using DMA mode. - The hperh->tx_cplt_cbk(), hperh->rx_cplt_cbk() user callbacks - will be executed respectively at the end of the Transmit or Receive process - The hperh->error_cbk() user callback will be executed when a communication - error is detected. - - (#) Blocking mode APIs are : - (++) ald_smartcard_send() - (++) ald_smartcard_recv() - - (#) Non Blocking mode APIs with Interrupt are : - (++) ald_smartcard_send_by_it() - (++) ald_smartcard_recv_by_it() - (++) ald_smartcard_irq_handler() - - (#) Non Blocking mode functions with DMA are : - (++) ald_smartcard_send_by_dma() - (++) ald_smartcard_recv_by_dma() - - * @endverbatim - * @{ - */ - -/** - * @brief Sends an amount of data in blocking mode. - * @param hperh: Pointer to a smartcard_handle_t structure that contains - * the configuration information for the specified SMARTCARD module. - * @param buf: Pointer to data buffer - * @param size: Amount of data to be sent - * @param timeout: Specify timeout value - * @retval Status, see @ref ald_status_t. - */ -ald_status_t ald_smartcard_send(smartcard_handle_t *hperh, uint8_t *buf, uint16_t size, uint32_t timeout) -{ - if ((hperh->state != SMARTCARD_STATE_READY) && (hperh->state != SMARTCARD_STATE_BUSY_RX)) - return BUSY; - if ((buf == NULL) || (size == 0)) - return ERROR; - - __LOCK(hperh); - hperh->err_code = SMARTCARD_ERROR_NONE; - SET_BIT(hperh->state, USART_STATE_TX_MASK); - - hperh->tx_size = size; - hperh->tx_count = size; - - while (hperh->tx_count-- > 0) { - if (smartcard_wait_flag(hperh, USART_FLAG_TXE, SET, timeout) != OK) { - hperh->state = SMARTCARD_STATE_READY; - __UNLOCK(hperh); - return TIMEOUT; - } - - WRITE_REG(hperh->perh->DATA, *buf++); - } - - if (smartcard_wait_flag(hperh, USART_FLAG_TC, SET, timeout) != OK) { - hperh->state = SMARTCARD_STATE_READY; - __UNLOCK(hperh); - return TIMEOUT; - } - - CLEAR_BIT(hperh->state, USART_STATE_TX_MASK); - __UNLOCK(hperh); - - return OK; -} - -/** - * @brief Receive an amount of data in blocking mode. - * @param hperh: Pointer to a smartcard_handle_t structure that contains - * the configuration information for the specified SMARTCARD module. - * @param buf: Pointer to data buffer - * @param size: Amount of data to be received - * @param timeout: Specify timeout value - * @retval Status, see @ref ald_status_t. - */ -ald_status_t ald_smartcard_recv(smartcard_handle_t *hperh, uint8_t *buf, uint16_t size, uint32_t timeout) -{ - if ((hperh->state != SMARTCARD_STATE_READY) && (hperh->state != SMARTCARD_STATE_BUSY_TX)) - return BUSY; - if ((buf == NULL) || (size == 0)) - return ERROR; - - __LOCK(hperh); - hperh->err_code = SMARTCARD_ERROR_NONE; - SET_BIT(hperh->state, USART_STATE_RX_MASK); - - hperh->rx_size = size; - hperh->rx_count = size; - - while (hperh->rx_count-- > 0) { - if (smartcard_wait_flag(hperh, USART_FLAG_RXNE, SET, timeout) != OK) { - hperh->state = SMARTCARD_STATE_READY; - __UNLOCK(hperh); - return TIMEOUT; - } - - *buf++ = (uint8_t)(hperh->perh->DATA & 0xFF); - } - - __UNLOCK(hperh); - CLEAR_BIT(hperh->state, USART_STATE_RX_MASK); - - return OK; -} - -/** - * @brief Sends an amount of data in non-blocking mode. - * @param hperh: Pointer to a smartcard_handle_t structure that contains - * the configuration information for the specified SMARTCARD module. - * @param buf: Pointer to data buffer - * @param size: Amount of data to be sent - * @retval Status, see @ref ald_status_t. - */ -ald_status_t ald_smartcard_send_by_it(smartcard_handle_t *hperh, uint8_t *buf, uint16_t size) -{ - if ((hperh->state != SMARTCARD_STATE_READY) && (hperh->state != SMARTCARD_STATE_BUSY_RX)) - return BUSY; - if ((buf == NULL) || (size == 0)) - return ERROR; - - __LOCK(hperh); - SET_BIT(hperh->state, USART_STATE_TX_MASK); - - hperh->tx_buf = buf; - hperh->tx_size = size; - hperh->tx_count = size; - hperh->err_code = SMARTCARD_ERROR_NONE; - - __UNLOCK(hperh); - ald_usart_interrupt_config((usart_handle_t *)hperh, USART_IT_ERR, ENABLE); - ald_usart_interrupt_config((usart_handle_t *)hperh, USART_IT_TXE, ENABLE); - - return OK; -} - -/** - * @brief Receives an amount of data in non-blocking mode. - * @param hperh: Pointer to a smartcard_handle_t structure that contains - * the configuration information for the specified SMARTCARD module. - * @param buf: Pointer to data buffer - * @param size: Amount of data to be received - * @retval Status, see @ref ald_status_t. - */ -ald_status_t ald_smartcard_recv_by_it(smartcard_handle_t *hperh, uint8_t *buf, uint16_t size) -{ - if ((hperh->state != SMARTCARD_STATE_READY) && (hperh->state != SMARTCARD_STATE_BUSY_TX)) - return BUSY; - if ((buf == NULL) || (size == 0)) - return ERROR; - - __LOCK(hperh); - SET_BIT(hperh->state, USART_STATE_RX_MASK); - - hperh->rx_buf = buf; - hperh->rx_size = size; - hperh->rx_count = size; - hperh->err_code = SMARTCARD_ERROR_NONE; - - __UNLOCK(hperh); - ald_usart_interrupt_config((usart_handle_t *)hperh, USART_IT_RXNE, ENABLE); - ald_usart_interrupt_config((usart_handle_t *)hperh, USART_IT_PE, ENABLE); - ald_usart_interrupt_config((usart_handle_t *)hperh, USART_IT_ERR, ENABLE); - - return OK; -} - -#ifdef ALD_DMA -/** - * @brief Sends an amount of data in non-blocking mode. - * @param hperh: Pointer to a smartcard_handle_t structure that contains - * the configuration information for the specified SMARTCARD module. - * @param buf: Pointer to data buffer - * @param size: Amount of data to be sent - * @param channel: DMA channel as USART transmit - * @retval Status, see @ref ald_status_t. - */ -ald_status_t ald_smartcard_send_by_dma(smartcard_handle_t *hperh, uint8_t *buf, uint16_t size, uint8_t channel) -{ - if ((hperh->state != SMARTCARD_STATE_READY) && (hperh->state != SMARTCARD_STATE_BUSY_RX)) - return BUSY; - if ((buf == NULL) || (size == 0)) - return ERROR; - - __LOCK(hperh); - SET_BIT(hperh->state, USART_STATE_TX_MASK); - - hperh->tx_buf = buf; - hperh->tx_size = size; - hperh->tx_count = size; - hperh->err_code = SMARTCARD_ERROR_NONE; - - if (hperh->hdmatx.perh == NULL) - hperh->hdmatx.perh = DMA0; - - hperh->hdmatx.cplt_cbk = smartcard_dma_send_cplt; - hperh->hdmatx.cplt_arg = (void *)hperh; - hperh->hdmatx.err_cbk = smartcard_dma_error; - hperh->hdmatx.err_arg = (void *)hperh; - - ald_dma_config_struct(&hperh->hdmatx.config); - hperh->hdmatx.config.src = (void *)buf; - hperh->hdmatx.config.dst = (void *)&hperh->perh->DATA; - hperh->hdmatx.config.size = size; - hperh->hdmatx.config.src_inc = DMA_DATA_INC_BYTE; - hperh->hdmatx.config.dst_inc = DMA_DATA_INC_NONE; - hperh->hdmatx.config.msel = hperh->perh == USART0 ? DMA_MSEL_USART0 : DMA_MSEL_USART1; - hperh->hdmatx.config.msigsel = DMA_MSIGSEL_USART_TXEMPTY; - hperh->hdmatx.config.channel = channel; - ald_dma_config_basic(&hperh->hdmatx); - - ald_usart_clear_flag_status((usart_handle_t *)hperh, USART_FLAG_TC); - __UNLOCK(hperh); - ald_usart_dma_req_config((usart_handle_t *)hperh, USART_DMA_REQ_TX, ENABLE); - - return OK; -} - -/** - * @brief Receive an amount of data in non-blocking mode. - * @param hperh: Pointer to a smartcard_handle_t structure that contains - * the configuration information for the specified SMARTCARD module. - * @param buf: Pointer to data buffer - * @param size: Amount of data to be received - * @param channel: DMA channel as USART transmit - * @note When the SMARTCARD parity is enabled (PCE = 1) the data received contain the parity bit. - * @retval Status, see @ref ald_status_t. - */ -ald_status_t ald_smartcard_recv_by_dma(smartcard_handle_t *hperh, uint8_t *buf, uint16_t size, uint8_t channel) -{ - if ((hperh->state != SMARTCARD_STATE_READY) && (hperh->state != SMARTCARD_STATE_BUSY_TX)) - return BUSY; - if ((buf == NULL) || (size == 0)) - return ERROR; - - __LOCK(hperh); - SET_BIT(hperh->state, USART_STATE_RX_MASK); - - hperh->rx_buf = buf; - hperh->rx_size = size; - hperh->rx_count = size; - hperh->err_code = SMARTCARD_ERROR_NONE; - - if (hperh->hdmarx.perh == NULL) - hperh->hdmarx.perh = DMA0; - - hperh->hdmarx.cplt_cbk = smartcard_dma_recv_cplt; - hperh->hdmarx.cplt_arg = (void *)hperh; - hperh->hdmarx.err_cbk = smartcard_dma_error; - hperh->hdmarx.err_arg = (void *)hperh; - - ald_dma_config_struct(&hperh->hdmarx.config); - hperh->hdmarx.config.src = (void *)&hperh->perh->DATA; - hperh->hdmarx.config.dst = (void *)buf; - hperh->hdmarx.config.size = size; - hperh->hdmarx.config.src_inc = DMA_DATA_INC_NONE; - hperh->hdmarx.config.dst_inc = DMA_DATA_INC_BYTE; - hperh->hdmarx.config.msel = hperh->perh == USART0 ? DMA_MSEL_USART0 : DMA_MSEL_USART1; - hperh->hdmarx.config.msigsel = DMA_MSIGSEL_USART_RNR; - hperh->hdmarx.config.channel = channel; - ald_dma_config_basic(&hperh->hdmarx); - - __UNLOCK(hperh); - ald_usart_dma_req_config((usart_handle_t *)hperh, USART_DMA_REQ_RX, ENABLE); - - return OK; -} -#endif - -/** - * @brief This function handles SMARTCARD interrupt request. - * @param hperh: Pointer to a smartcard_handle_t structure that contains - * the configuration information for the specified SMARTCARD module. - * @retval None - */ -void ald_smartcard_irq_handler(smartcard_handle_t *hperh) -{ - uint32_t flag; - uint32_t source; - - /* Handle parity error */ - flag = ald_usart_get_flag_status((usart_handle_t *)hperh, USART_FLAG_PE); - source = ald_usart_get_it_status((usart_handle_t *)hperh, USART_IT_PE); - if ((flag != RESET) && (source != RESET)) - hperh->err_code |= SMARTCARD_ERROR_PE; - - /* Handle frame error */ - flag = ald_usart_get_flag_status((usart_handle_t *)hperh, USART_FLAG_FE); - source = ald_usart_get_it_status((usart_handle_t *)hperh, USART_IT_ERR); - if ((flag != RESET) && (source != RESET)) - hperh->err_code |= SMARTCARD_ERROR_FE; - - /* Handle noise error */ - flag = ald_usart_get_flag_status((usart_handle_t *)hperh, USART_FLAG_NE); - if ((flag != RESET) && (source != RESET)) - hperh->err_code |= SMARTCARD_ERROR_NE; - - /* Handle overrun error */ - flag = ald_usart_get_flag_status((usart_handle_t *)hperh, USART_FLAG_ORE); - if ((flag != RESET) && (source != RESET)) - hperh->err_code |= SMARTCARD_ERROR_ORE; - - /* Handle receive */ - flag = ald_usart_get_flag_status((usart_handle_t *)hperh, USART_FLAG_RXNE); - source = ald_usart_get_it_status((usart_handle_t *)hperh, USART_IT_RXNE); - if ((flag != RESET) && (source != RESET)) - __smartcard_recv_by_it(hperh); - - /* Handle transmit */ - flag = ald_usart_get_flag_status((usart_handle_t *)hperh, USART_FLAG_TXE); - source = ald_usart_get_it_status((usart_handle_t *)hperh, USART_IT_TXE); - if ((flag != RESET) && (source != RESET)) - __smartcard_send_by_it(hperh); - - /* Handle transmit complete */ - flag = ald_usart_get_flag_status((usart_handle_t *)hperh, USART_FLAG_TC); - source = ald_usart_get_it_status((usart_handle_t *)hperh, USART_IT_TC); - if ((flag != RESET) && (source != RESET)) - __smartcard_end_send_by_it(hperh); - - /* Handle error */ - if (hperh->err_code != SMARTCARD_ERROR_NONE) { - USART_CLEAR_PEFLAG(hperh); - hperh->state = SMARTCARD_STATE_READY; - - if (hperh->error_cbk) - hperh->error_cbk(hperh); - } -} -/** - * @} - */ - -/** @defgroup SMARTCARD_Public_Functions_Group3 Peripheral State and Errors functions - * @brief SMARTCARD State and Errors functions - * -@verbatim - ============================================================================== - ##### Peripheral State and Errors functions ##### - ============================================================================== - [..] - This subsection provides a set of functions allowing to return the State of SmartCard - communication process and also return Peripheral Errors occurred during communication process - (+) ald_smartcard_get_state() API can be helpful to check in run-time the state - of the SMARTCARD peripheral. - (+) ald_smartcard_get_error() check in run-time errors that could be occurred during - communication. - -@endverbatim - * @{ - */ - -/** - * @brief Returns the SMARTCARD state. - * @param hperh: Pointer to a smartcard_handle_t structure that contains - * the configuration information for the specified SMARTCARD module. - * @retval ALD state - */ -smartcard_state_t ald_smartcard_get_state(smartcard_handle_t *hperh) -{ - return hperh->state; -} - -/** - * @brief Return the SMARTCARD error code - * @param hperh: Pointer to a smartcard_handle_t structure that contains - * the configuration information for the specified SMARTCARD module. - * @retval SMARTCARD Error Code - */ -uint32_t ald_smartcard_get_error(smartcard_handle_t *hperh) -{ - return hperh->err_code; -} - -/** - * @} - */ - -/** - * @} - */ - -/** @defgroup SMARTCARD_Private_Functions SMARTCARD Private Functions - * @brief SMARTCARD Private functions - * @{ - */ - -#ifdef ALD_DMA -/** - * @brief DMA SMARTCARD transmit process complete callback. - * @param arg: Pointer to a smartcard_handle_t structure that contains - * the configuration information for the specified DMA module. - * @retval None - */ -static void smartcard_dma_send_cplt(void *arg) -{ - smartcard_handle_t* hperh = ( smartcard_handle_t *)arg; - - hperh->tx_count = 0; - ald_usart_dma_req_config((usart_handle_t *)hperh, USART_DMA_REQ_TX, DISABLE); - ald_usart_interrupt_config((usart_handle_t *)hperh, USART_IT_TC, ENABLE); - - return; -} - -/** - * @brief DMA SMARTCARD receive process complete callback. - * @param arg: Pointer to a smartcard_handle_t structure that contains - * the configuration information for the specified DMA module. - * @retval None - */ -static void smartcard_dma_recv_cplt(void *arg) -{ - smartcard_handle_t* hperh = ( smartcard_handle_t* )arg; - - hperh->rx_count = 0; - ald_usart_dma_req_config((usart_handle_t *)hperh, USART_DMA_REQ_RX, DISABLE); - CLEAR_BIT(hperh->state, USART_STATE_RX_MASK); - - if (hperh->rx_cplt_cbk) - hperh->rx_cplt_cbk(hperh); - - return; -} - -/** - * @brief DMA SMARTCARD communication error callback. - * @param arg: Pointer to a smartcard_handle_t structure that contains - * the configuration information for the specified DMA module. - * @retval None - */ -static void smartcard_dma_error(void *arg) -{ - smartcard_handle_t* hperh = ( smartcard_handle_t* )arg; - - hperh->rx_count = 0; - hperh->tx_count = 0; - hperh->err_code = SMARTCARD_ERROR_DMA; - hperh->state = SMARTCARD_STATE_READY; - - ald_usart_dma_req_config((usart_handle_t *)hperh, USART_DMA_REQ_TX, DISABLE); - ald_usart_dma_req_config((usart_handle_t *)hperh, USART_DMA_REQ_RX, DISABLE); - - if (hperh->error_cbk) - hperh->error_cbk(hperh); - - return; -} -#endif - -/** - * @brief This function handles USART Communication Timeout. - * @param hperh: Pointer to a usart_handle_t structure that contains - * the configuration information for the specified USART module. - * @param flag: specifies the USART flag to check. - * @param status: The new Flag status (SET or RESET). - * @param timeout: Timeout duration - * @retval Status, see @ref ald_status_t. - */ -static ald_status_t smartcard_wait_flag(smartcard_handle_t *hperh, usart_flag_t flag, flag_status_t status, uint32_t timeout) -{ - uint32_t tick; - - if (timeout == 0) - return OK; - - tick = ald_get_tick(); - - while ((ald_usart_get_flag_status((usart_handle_t *)hperh, flag)) != status) { - if (((ald_get_tick()) - tick) > timeout) { - ald_usart_interrupt_config((usart_handle_t *)hperh, USART_IT_TXE, DISABLE); - ald_usart_interrupt_config((usart_handle_t *)hperh, USART_IT_RXNE, DISABLE); - ald_usart_interrupt_config((usart_handle_t *)hperh, USART_IT_PE, DISABLE); - ald_usart_interrupt_config((usart_handle_t *)hperh, USART_IT_ERR, DISABLE); - - return TIMEOUT; - } - } - - return OK; -} - -/** - * @brief Send an amount of data in non-blocking mode. - * @param hperh: Pointer to a smartcard_handle_t structure that contains - * the configuration information for the specified SMARTCARD module. - * Function called under interruption only, once - * interruptions have been enabled by ald_smartcard_send_by_it() - * @retval Status, see @ref ald_status_t. - */ -static ald_status_t __smartcard_send_by_it(smartcard_handle_t *hperh) -{ - if ((hperh->state != SMARTCARD_STATE_BUSY_TX) && (hperh->state != SMARTCARD_STATE_BUSY_TX_RX)) - return BUSY; - - WRITE_REG(hperh->perh->DATA, *hperh->tx_buf++); - - if (--hperh->tx_count == 0) { - ald_usart_interrupt_config((usart_handle_t *)hperh, USART_IT_TXE, DISABLE); - ald_usart_interrupt_config((usart_handle_t *)hperh, USART_IT_TC, ENABLE); - } - - return OK; -} - - -/** - * @brief Wraps up transmission in non blocking mode. - * @param hperh: pointer to a smartcard_handle_t structure that contains - * the configuration information for the specified SMARTCARD module. - * @retval Status, see @ref ald_status_t. - */ -static ald_status_t __smartcard_end_send_by_it(smartcard_handle_t *hperh) -{ - ald_usart_interrupt_config((usart_handle_t *)hperh, USART_IT_TC, DISABLE); - CLEAR_BIT(hperh->state, USART_STATE_TX_MASK); - - if (hperh->state == SMARTCARD_STATE_READY) - ald_usart_interrupt_config((usart_handle_t *)hperh, USART_IT_ERR, DISABLE); - - if (hperh->tx_cplt_cbk) - hperh->tx_cplt_cbk(hperh); - - return OK; -} - - -/** - * @brief Receive an amount of data in non-blocking mode. - * @param hperh: Pointer to a smartcard_handle_t structure that contains - * the configuration information for the specified SMARTCARD module. - * @retval Status, see @ref ald_status_t. - */ -static ald_status_t __smartcard_recv_by_it(smartcard_handle_t *hperh) -{ - if ((hperh->state != SMARTCARD_STATE_BUSY_RX) && (hperh->state != SMARTCARD_STATE_BUSY_TX_RX)) - return BUSY; - - *hperh->rx_buf++ = (uint8_t)(hperh->perh->DATA & 0xFF); - - if (--hperh->rx_count == 0) { - ald_usart_interrupt_config((usart_handle_t *)hperh, USART_IT_RXNE, DISABLE); - ald_usart_interrupt_config((usart_handle_t *)hperh, USART_IT_PE, DISABLE); - ald_usart_interrupt_config((usart_handle_t *)hperh, USART_IT_ERR, DISABLE); - CLEAR_BIT(hperh->state, USART_STATE_RX_MASK); - - if (hperh->rx_cplt_cbk) - hperh->rx_cplt_cbk(hperh); - } - - return OK; -} - -/** - * @brief Configures the SMARTCARD peripheral. - * @param hperh: Pointer to a smartcard_handle_t structure that contains - * the configuration information for the specified SMARTCARD module. - * @retval None - */ -static void smartcard_set_config(smartcard_handle_t *hperh) -{ - uint32_t tmp; - uint32_t integer; - uint32_t fractional; - - /* Check the parameters */ - assert_param(IS_USART(hperh->perh)); - assert_param(IS_USART_BAUDRATE(hperh->init.baud)); - assert_param(IS_USART_WORD_LENGTH(hperh->init.word_length)); - assert_param(IS_USART_STOPBITS(hperh->init.stop_bits)); - assert_param(IS_USART_PARITY(hperh->init.parity)); - assert_param(IS_USART_MODE(hperh->init.mode)); - - MODIFY_REG(hperh->perh->CON1, USART_CON1_STPLEN_MSK, hperh->init.stop_bits << USART_CON1_STPLEN_POSS); - tmp = READ_REG(hperh->perh->CON0); - MODIFY_REG(tmp, USART_CON0_DLEN_MSK, hperh->init.word_length << USART_CON0_DLEN_POS); - - if (hperh->init.parity == USART_PARITY_NONE) - CLEAR_BIT(tmp, USART_CON0_PEN_MSK); - else - SET_BIT(tmp, USART_CON0_PEN_MSK); - - if (hperh->init.parity == USART_PARITY_ODD) - SET_BIT(tmp, USART_CON0_PSEL_MSK); - else - CLEAR_BIT(tmp, USART_CON0_PSEL_MSK); - - WRITE_REG(hperh->perh->CON0, tmp); - CLEAR_BIT(hperh->perh->CON2, USART_CON2_RTSEN_MSK); - CLEAR_BIT(hperh->perh->CON2, USART_CON2_CTSEN_MSK); - MODIFY_REG(hperh->perh->CON0, USART_CON0_RXEN_MSK, (hperh->init.mode & 0x1) << USART_CON0_RXEN_POS); - MODIFY_REG(hperh->perh->CON0, USART_CON0_TXEN_MSK, ((hperh->init.mode >> 1) & 0x1) << USART_CON0_TXEN_POS); - tmp = READ_REG(hperh->perh->CON1); - SET_BIT(tmp, USART_CON1_SCKEN_MSK); - MODIFY_REG(tmp, USART_CON1_SCKPOL_MSK, hperh->init.polarity << USART_CON1_SCKPOL_POS); - MODIFY_REG(tmp, USART_CON1_SCKPHA_MSK, hperh->init.phase << USART_CON1_SCKPHA_POS); - MODIFY_REG(tmp, USART_CON1_LBCP_MSK, hperh->init.last_bit << USART_CON1_LBCP_POS); - - /* Determine the integer part */ - if (READ_BIT(hperh->perh->CON0, (1 << 15))) { - /* Integer part computing in case Oversampling mode is 8 Samples */ - integer = ((25 * ald_cmu_get_pclk1_clock()) / (2 * (hperh->init.baud))); - } - else { - /* Integer part computing in case Oversampling mode is 16 Samples */ - integer = ((25 * ald_cmu_get_pclk1_clock()) / (4 * (hperh->init.baud))); - } - tmp = (integer / 100) << 4; - - /* Determine the fractional part */ - fractional = integer - (100 * (tmp >> 4)); - - /* Implement the fractional part in the register */ - if (READ_BIT(hperh->perh->CON0, (1 << 15))) - tmp |= ((((fractional * 8) + 50) / 100)) & ((uint8_t)0x07); - else - tmp |= ((((fractional * 16) + 50) / 100)) & ((uint8_t)0x0F); - - WRITE_REG(hperh->perh->BAUDCON, (uint16_t)tmp); - return; -} - -/** - * @} - */ - -#endif /* ALD_SMARTCARD */ -/** - * @} - */ - -/** - * @} - */ diff --git a/bsp/essemi/es32f0334/libraries/ES32F033x_ALD_StdPeriph_Driver/Source/ald_spi.c b/bsp/essemi/es32f0334/libraries/ES32F033x_ALD_StdPeriph_Driver/Source/ald_spi.c deleted file mode 100644 index f756f6785d..0000000000 --- a/bsp/essemi/es32f0334/libraries/ES32F033x_ALD_StdPeriph_Driver/Source/ald_spi.c +++ /dev/null @@ -1,1789 +0,0 @@ -/** - ********************************************************************************* - * - * @file ald_spi.c - * @brief SPI module driver. - * This file provides firmware functions to manage the following - * functionalities of SPI peripheral: - * + Initialization functions - * + IO operation functions - * + Peripheral Control functions - * + Peripheral State functions - * - * @version V1.0 - * @date 13 Nov 2017 - * @author AE Team - * @note - * - * Copyright (C) Shanghai Eastsoft Microelectronics Co. Ltd. All rights reserved. - * - ********************************************************************************* - @verbatim - ============================================================================== - ##### How to use this driver ##### - ============================================================================== - [..] - The SPI driver can be used as follows: - - (#) Declare a spi_handle_t structure, for example: - spi_handle_t hperh; - - (#) Initialize the SPI low level resources: - (##) Enable the SPIx interface clock - (##) SPI pins configuration - (+++) Enable the clock for the SPI GPIOs - (+++) Configure these SPI pins as push-pull - (##) NVIC configuration if you need to use interrupt process - by implementing the ald_mcu_irq_config() API. - Invoked ald_spi_irq_handler() function in SPI-IRQ function - (##) DMA Configuration if you need to use DMA process - (+++) Define ALD_DMA in ald_conf.h - (+++) Enable the DMAx clock - - (#) Program the Mode, Direction , Data size, Baudrate Prescaler, NSS - management, Clock polarity and phase, FirstBit and CRC configuration in the hspi Init structure. - - (#) Initialize the SPI module by invoking the ald_spi_init() API. - - [..] - Circular mode restriction: - (#) The DMA circular mode cannot be used when the SPI is configured in these modes: - (##) Master 2Lines RxOnly - (##) Master 1Line Rx - (#) When the SPI DMA Pause/Stop features are used, we must use the following APIs - the ald_spi_dma_pause()/ ald_spi_dma_stop(). - - * @endverbatim - */ - -#include "ald_spi.h" - - -/** @addtogroup ES32FXXX_ALD - * @{ - */ - -/** @defgroup SPI SPI - * @brief SPI module driver - * @{ - */ -#ifdef ALD_SPI - -/** @addtogroup SPI_Private_Functions SPI Private Functions - * @{ - */ -static ald_status_t spi_wait_flag(spi_handle_t *hperh, spi_flag_t flag, flag_status_t status, uint32_t timeout); -static ald_status_t spi_wait_flag_irq(spi_handle_t *hperh, spi_flag_t flag, flag_status_t status, uint32_t timeout); -static void __spi_send_by_it(spi_handle_t *hperh); -static void __spi_recv_by_it(spi_handle_t *hperh); -static void __spi_send_recv_by_it(spi_handle_t *hperh, spi_sr_status_t status); -#ifdef ALD_DMA -static void spi_dma_send_cplt(void *arg); -static void spi_dma_recv_cplt(void *arg); -static void spi_dma_send_recv_cplt(void *arg); -static void spi_dma_error(void *arg); -#endif -/** - * @} - */ - -/** @defgroup SPI_Public_Functions SPI Public Functions - * @{ - */ - -/** @defgroup SPI_Public_Functions_Group1 Initialization functions - * @brief Initialization and Configuration functions - * - * @verbatim - =============================================================================== - ##### Initialization and de-initialization functions ##### - =============================================================================== - [..] This subsection provides a set of functions allowing to initialize and - reset the SPIx peripheral: - - (+) User must configure all related peripherals resources - (CLOCK, GPIO, DMA, NVIC). - - (+) Call the function ald_spi_init() to configure the selected device with - the selected configuration: - (++) Mode - (++) Direction - (++) Data Size - (++) Clock Polarity and Phase - (++) NSS Management - (++) BaudRate Prescaler - (++) FirstBit - (++) TIMode - (++) CRC Calculation - (++) CRC Polynomial if CRC enabled - - (+) Call the function ald_spi_reset() to reset the selected SPIx periperal. - - @endverbatim - * @{ - */ - -/** - * @brief Reset the SPI peripheral. - * @param hperh: Pointer to a spi_handle_t structure that contains - * the configuration information for the specified SPI module. - * @retval None - */ -void ald_spi_reset(spi_handle_t *hperh) -{ - hperh->perh->CON1 = 0x0; - hperh->perh->CON2 = 0x0; - hperh->perh->CRCPOLY = 0x00000007; - - SPI_RESET_HANDLE_STATE(hperh); - __UNLOCK(hperh); - - return; -} - -/** - * @brief Initializes the SPI mode according to the specified parameters in - * the SPI_init_t and create the associated handle. - * @param hperh: Pointer to a spi_handle_t structure that contains - * the configuration information for the specified SPI module. - * @retval Status, see @ref ald_status_t. - */ -ald_status_t ald_spi_init(spi_handle_t *hperh) -{ - uint32_t tmp = 0; - - if (hperh == NULL) - return ERROR; - - assert_param(IS_SPI(hperh->perh)); - assert_param(IS_SPI_MODE(hperh->init.mode)); - assert_param(IS_SPI_DIRECTION(hperh->init.dir)); - assert_param(IS_SPI_BAUD(hperh->init.baud)); - assert_param(IS_SPI_FIRSTBIT(hperh->init.first_bit)); - assert_param(IS_FUNC_STATE(hperh->init.ss_en)); - assert_param(IS_FUNC_STATE(hperh->init.crc_calc)); - assert_param(IS_SPI_DATASIZE(hperh->init.data_size)); - assert_param(IS_SPI_CPHA(hperh->init.phase)); - assert_param(IS_SPI_CPOL(hperh->init.polarity)); - - ald_spi_reset(hperh); - - tmp = hperh->perh->CON1; - - if (hperh->init.mode == SPI_MODE_MASTER) - tmp |= 1 << SPI_CON1_SSOUT_POS; - - tmp |= ((hperh->init.phase << SPI_CON1_CPHA_POS) | (hperh->init.polarity << SPI_CON1_CPOL_POS) | - (hperh->init.baud << SPI_CON1_BAUD_POSS) | (hperh->init.data_size << SPI_CON1_FLEN_POS) | - (hperh->init.mode << SPI_CON1_MSTREN_POS) | (hperh->init.ss_en << SPI_CON1_SSEN_POS) | - (hperh->init.first_bit << SPI_CON1_LSBFST_POS)); - - hperh->perh->CON1 = tmp; - - if (hperh->init.dir == SPI_DIRECTION_2LINES) { - CLEAR_BIT(hperh->perh->CON1, SPI_CON1_BIDEN_MSK); - CLEAR_BIT(hperh->perh->CON1, SPI_CON1_RXO_MSK); - } - else if (hperh->init.dir == SPI_DIRECTION_2LINES_RXONLY) { - CLEAR_BIT(hperh->perh->CON1, SPI_CON1_BIDEN_MSK); - SET_BIT(hperh->perh->CON1, SPI_CON1_RXO_MSK); - } - else { - SET_BIT(hperh->perh->CON1, SPI_CON1_BIDEN_MSK); - } - - /* configure CRC */ - hperh->perh->CON1 |= (hperh->init.crc_calc << SPI_CON1_CRCEN_POS); - hperh->perh->CRCPOLY = hperh->init.crc_poly; - - hperh->err_code = SPI_ERROR_NONE; - hperh->state = SPI_STATE_READY; - - if (hperh->init.dir == SPI_DIRECTION_2LINES) - SPI_ENABLE(hperh); - - return OK; -} -/** - * @} - */ - -/** @defgroup SPI_Public_Functions_Group2 IO operation functions - * @brief SPI Transmit and Receive functions - * - * @verbatim - ============================================================================== - ##### IO operation functions ##### - =============================================================================== - This subsection provides a set of functions allowing to manage the SPI - data transfers. - - [..] The SPI supports master or slave mode: - - (#) There are two modes of transfer: - (++) Blocking mode: The communication is performed in polling mode. - The ALD status of all data processing is returned by the same function - after finishing transfer. - (++) No-Blocking mode: The communication is performed using Interrupts - or DMA, These APIs return the ALD status. - The end of the data processing will be indicated through the - dedicated SPI IRQ when using Interrupt mode or the DMA IRQ when - using DMA mode. - The hperh->tx_cplt_cbk(), hperh->rx_cplt_cbk() and hperh->tx_rx_cplt_cbk() user callbacks - will be executed respectivelly at the end of the transmit or Receive process - The hperh->err_cbk() user callback will be executed when a communication error is detected - - (#) APIs provided for these 2 transfer modes (Blocking mode or Non blocking mode using either Interrupt or DMA) - exist for 1Line (simplex) and 2Lines (full duplex) modes. - - * @endverbatim - * @{ - */ - -/** - * @brief transmit one byte fast in blocking mode. - * @param hperh: Pointer to a spi_handle_t structure. - * @param data: Data to be sent - * @retval status: - * - 0 Success - * - -1 Failed - */ -int32_t ald_spi_send_byte_fast(spi_handle_t *hperh, uint8_t data) -{ - uint16_t cnt = 2000, temp; - - hperh->perh->DATA = data; - while (((hperh->perh->STAT & (1 << SPI_STAT_TXBE_POS)) == 0) && (--cnt)); - cnt = 2000; - while ((hperh->perh->STAT & (1 << SPI_STAT_RXBNE_POS)) == 0 && (--cnt)); - temp = hperh->perh->DATA; - UNUSED(temp); - - return cnt == 0 ? -1 : 0; -} - -/** - * @brief transmit one byte fast in blocking mode(1line). - * @param hperh: Pointer to a spi_handle_t structure. - * @param data: Data to be sent - * @retval status: - * - 0 Success - * - -1 Failed - */ -int32_t ald_spi_send_byte_fast_1line(spi_handle_t *hperh, uint8_t data) -{ - uint16_t cnt = 2000; - - hperh->perh->DATA = data; - while (((hperh->perh->STAT & (1 << SPI_STAT_TXBE_POS)) == 0) && (--cnt)); - - return cnt == 0 ? -1 : 0; -} - -/** - * @brief Receive one byte fast in blocking mode. - * @param hperh: Pointer to a spi_handle_t structure. - * @retval Data. - */ -uint8_t ald_spi_recv_byte_fast(spi_handle_t *hperh) -{ - uint16_t cnt = 2000; - - if (hperh->init.mode == SPI_MODE_MASTER) { - hperh->perh->DATA = 0xFF; - while (((hperh->perh->STAT & (1 << SPI_STAT_TXBE_POS)) == 0) && (--cnt)); - } - - cnt = 2000; - while (((hperh->perh->STAT & (1 << SPI_STAT_RXBNE_POS)) == 0) && (--cnt)); - return (uint8_t)hperh->perh->DATA; -} - -/** - * @brief transmit an amount of data in blocking mode. - * @param hperh: Pointer to a spi_handle_t structure. - * @param buf: Pointer to data buffer - * @param size: Amount of data to be sent - * @param timeout: Timeout duration - * @retval Status, see @ref ald_status_t. - */ -ald_status_t ald_spi_send(spi_handle_t *hperh, uint8_t *buf, uint16_t size, uint32_t timeout) -{ - assert_param(IS_SPI(hperh->perh)); - - if (hperh->state != SPI_STATE_READY) - return BUSY; - if (buf == NULL || size == 0) - return ERROR; - - __LOCK(hperh); - - hperh->state = SPI_STATE_BUSY_TX; - hperh->err_code = SPI_ERROR_NONE; - - hperh->tx_buf = buf; - hperh->tx_size = size; - hperh->tx_count = size; - hperh->rx_buf = NULL; - hperh->rx_size = 0; - hperh->rx_count = 0; - - if (hperh->init.crc_calc) - SPI_CRC_RESET(hperh); - if (hperh->init.dir == SPI_DIRECTION_1LINE) - SPI_1LINE_TX(hperh); - if (READ_BIT(hperh->perh->CON1, SPI_CON1_SPIEN_MSK) == 0) - SPI_ENABLE(hperh); - - if ((hperh->init.mode == SPI_MODE_SLAVER) || (hperh->tx_count == 1)) { - if (hperh->init.data_size == SPI_DATA_SIZE_8) { - hperh->perh->DATA = *hperh->tx_buf; - ++hperh->tx_buf; - --hperh->tx_count; - } - else { - hperh->perh->DATA = (*(uint16_t *)hperh->tx_buf); - hperh->tx_buf += 2; - --hperh->tx_count; - } - } - - while (hperh->tx_count > 0) { - if (spi_wait_flag(hperh, SPI_IF_TXBE, SET, timeout) != OK) { - if (hperh->init.crc_calc) - SPI_CRC_RESET(hperh); - - hperh->state = SPI_STATE_READY; - __UNLOCK(hperh); - return TIMEOUT; - } - - if (hperh->init.data_size == SPI_DATA_SIZE_8) { - hperh->perh->DATA = *hperh->tx_buf; - ++hperh->tx_buf; - --hperh->tx_count; - } - else { - hperh->perh->DATA = (*(uint16_t *)hperh->tx_buf); - hperh->tx_buf += 2; - --hperh->tx_count; - } - } - - if (hperh->init.crc_calc) - SPI_CRCNEXT_ENABLE(hperh); - - if ((spi_wait_flag(hperh, SPI_IF_TXBE, SET, timeout) != OK) - || (spi_wait_flag(hperh, SPI_IF_BUSY, RESET, timeout) != OK)) { - if (hperh->init.crc_calc) - SPI_CRC_RESET(hperh); - - hperh->state = SPI_STATE_READY; - __UNLOCK(hperh); - return TIMEOUT; - } - - if (hperh->init.dir == SPI_DIRECTION_2LINES) - ald_spi_clear_flag_status(hperh, SPI_IF_OVE); - - hperh->state = SPI_STATE_READY; - __UNLOCK(hperh); - - return OK; -} - -/** - * @brief Receive an amount of data in blocking mode. - * @param hperh: Pointer to a spi_handle_t structure. - * @param buf: Pointer to data buffer - * @param size: Amount of data to be received - * @param timeout: Timeout duration - * @retval Status, see @ref ald_status_t. - */ -ald_status_t ald_spi_recv(spi_handle_t *hperh, uint8_t *buf, uint16_t size, uint32_t timeout) -{ - uint16_t temp; - assert_param(IS_SPI(hperh->perh)); - - if (hperh->state != SPI_STATE_READY) - return BUSY; - if (buf == NULL || size == 0) - return ERROR; - - __LOCK(hperh); - hperh->state = SPI_STATE_BUSY_RX; - hperh->err_code = SPI_ERROR_NONE; - - hperh->rx_buf = buf; - hperh->rx_size = size; - hperh->rx_count = size; - hperh->tx_buf = NULL; - hperh->tx_size = 0; - hperh->tx_count = 0; - - if (hperh->init.crc_calc) - SPI_CRC_RESET(hperh); - if (hperh->init.dir == SPI_DIRECTION_1LINE_RX) - SPI_1LINE_RX(hperh); - - if ((hperh->init.mode == SPI_MODE_MASTER) && (hperh->init.dir == SPI_DIRECTION_2LINES)) { - __UNLOCK(hperh); - hperh->state = SPI_STATE_READY; - return ald_spi_send_recv(hperh, buf, buf, size, timeout); - } - - if ((hperh->init.dir == SPI_DIRECTION_2LINES_RXONLY) || (hperh->init.dir == SPI_DIRECTION_1LINE_RX)) - SPI_ENABLE(hperh); - - while (hperh->rx_count > 1) { - if (spi_wait_flag(hperh, SPI_IF_RXBNE, SET, timeout) != OK) { - if (hperh->init.crc_calc) - SPI_CRC_RESET(hperh); - - hperh->state = SPI_STATE_READY; - __UNLOCK(hperh); - return TIMEOUT; - } - - if (hperh->init.data_size == SPI_DATA_SIZE_8) { - *hperh->rx_buf = hperh->perh->DATA; - ++hperh->rx_buf; - --hperh->rx_count; - } - else { - *(uint16_t *)hperh->rx_buf = hperh->perh->DATA; - hperh->rx_buf += 2; - --hperh->rx_count; - } - } - - if (hperh->init.crc_calc) - SPI_CRCNEXT_ENABLE(hperh); - - if (spi_wait_flag(hperh, SPI_IF_RXBNE, SET, timeout) != OK) { - if (hperh->init.crc_calc) - SPI_CRC_RESET(hperh); - - hperh->state = SPI_STATE_READY; - __UNLOCK(hperh); - return TIMEOUT; - } - - if (hperh->init.data_size == SPI_DATA_SIZE_8) { - *hperh->rx_buf = hperh->perh->DATA; - ++hperh->rx_buf; - --hperh->rx_count; - } - else { - *(uint16_t *)hperh->rx_buf = hperh->perh->DATA; - hperh->rx_buf += 2; - --hperh->rx_count; - } - - if (hperh->init.crc_calc) { - if (spi_wait_flag(hperh, SPI_IF_RXBNE, SET, timeout) != OK) { - if (hperh->init.crc_calc) - SPI_CRC_RESET(hperh); - - hperh->state = SPI_STATE_READY; - __UNLOCK(hperh); - return TIMEOUT; - } - - temp = hperh->perh->DATA; - UNUSED(temp); - } - - if ((hperh->init.crc_calc) && (ald_spi_get_flag_status(hperh, SPI_IF_CRCERR) != RESET)) { - hperh->err_code |= SPI_ERROR_CRC; - SPI_CRC_RESET(hperh); - ald_spi_clear_flag_status(hperh, SPI_IF_CRCERR); - hperh->state = SPI_STATE_READY; - __UNLOCK(hperh); - return ERROR; - } - - hperh->state = SPI_STATE_READY; - __UNLOCK(hperh); - - return OK; -} - -/** - * @brief Full-Duplex Send receive an amount of data in full-duplex mode (blocking mode). - * @param hperh: Pointer to a spi_handle_t structure. - * @param tx_buf: Pointer to data transmitted buffer - * @param rx_buf: Pointer to data received buffer - * @param size: Amount of data to be sent - * @param timeout: Timeout duration - * @retval Status, see @ref ald_status_t. - */ -ald_status_t ald_spi_send_recv(spi_handle_t *hperh, uint8_t *tx_buf, uint8_t *rx_buf, uint16_t size, uint32_t timeout) -{ - uint16_t temp; - - assert_param(IS_SPI(hperh->perh)); - - if (hperh->state != SPI_STATE_READY) - return BUSY; - if (hperh->init.dir != SPI_DIRECTION_2LINES) - return ERROR; - if (tx_buf == NULL || rx_buf == NULL || size == 0) - return ERROR; - - __LOCK(hperh); - hperh->state = SPI_STATE_BUSY_TX_RX; - hperh->err_code = SPI_ERROR_NONE; - - hperh->tx_buf = tx_buf; - hperh->tx_size = size; - hperh->tx_count = size; - hperh->rx_buf = rx_buf; - hperh->rx_size = size; - hperh->rx_count = size; - - if (hperh->init.crc_calc) - SPI_CRC_RESET(hperh); - - if ((hperh->init.mode == SPI_MODE_SLAVER) || ((hperh->init.mode == SPI_MODE_SLAVER) && (hperh->tx_size == 1))) { - if (hperh->init.data_size == SPI_DATA_SIZE_8) { - hperh->perh->DATA = *hperh->tx_buf; - ++hperh->tx_buf; - --hperh->tx_count; - } - else { - hperh->perh->DATA = (*(uint16_t *)hperh->tx_buf); - hperh->tx_buf += 2; - --hperh->tx_count; - } - } - - if (hperh->tx_count == 0) { - if (hperh->init.crc_calc) - SPI_CRCNEXT_ENABLE(hperh); - - if (spi_wait_flag(hperh, SPI_IF_TXBE, SET, timeout) != OK) { - if (hperh->init.crc_calc) - SPI_CRC_RESET(hperh); - - hperh->state = SPI_STATE_READY; - __UNLOCK(hperh); - return TIMEOUT; - } - - if (hperh->init.data_size == SPI_DATA_SIZE_8) { - *hperh->rx_buf = hperh->perh->DATA; - ++hperh->rx_buf; - --hperh->rx_count; - } - else { - (*(uint16_t *)hperh->rx_buf) = hperh->perh->DATA; - hperh->rx_buf += 2; - --hperh->rx_count; - } - } - - while (hperh->tx_count > 0) { - if (spi_wait_flag(hperh, SPI_IF_TXBE, SET, timeout) != OK) { - if (hperh->init.crc_calc) - SPI_CRC_RESET(hperh); - - hperh->state = SPI_STATE_READY; - __UNLOCK(hperh); - return TIMEOUT; - } - - if (hperh->init.data_size == SPI_DATA_SIZE_8) { - hperh->perh->DATA = *hperh->tx_buf; - ++hperh->tx_buf; - --hperh->tx_count; - } - else { - hperh->perh->DATA = (*(uint16_t *)hperh->tx_buf); - hperh->tx_buf += 2; - --hperh->tx_count; - } - - if ((hperh->tx_count == 0) && (hperh->init.crc_calc)) - SPI_CRCNEXT_ENABLE(hperh); - - if (spi_wait_flag(hperh, SPI_IF_RXBNE, SET, timeout) != OK) { - if (hperh->init.crc_calc) - SPI_CRC_RESET(hperh); - - hperh->state = SPI_STATE_READY; - __UNLOCK(hperh); - return TIMEOUT; - } - - if (hperh->init.data_size == SPI_DATA_SIZE_8) { - *hperh->rx_buf = hperh->perh->DATA; - ++hperh->rx_buf; - --hperh->rx_count; - } - else { - (*(uint16_t *)hperh->rx_buf) = hperh->perh->DATA; - - hperh->rx_buf += 2; - --hperh->rx_count; - } - } - - if (hperh->init.mode == SPI_MODE_SLAVER) { - if (spi_wait_flag(hperh, SPI_IF_RXBNE, SET, timeout) != OK) { - if (hperh->init.crc_calc) - SPI_CRC_RESET(hperh); - - hperh->state = SPI_STATE_READY; - __UNLOCK(hperh); - return TIMEOUT; - } - - if (hperh->init.data_size == SPI_DATA_SIZE_8) { - *hperh->rx_buf = hperh->perh->DATA; - ++hperh->rx_buf; - --hperh->rx_count; - } - else { - (*(uint16_t *)hperh->rx_buf) = hperh->perh->DATA; - - hperh->rx_buf += 2; - --hperh->rx_count; - } - } - - if (hperh->init.crc_calc) { - if (spi_wait_flag(hperh, SPI_IF_RXBNE, SET, timeout) != OK) { - if (hperh->init.crc_calc) - SPI_CRC_RESET(hperh); - - hperh->state = SPI_STATE_READY; - __UNLOCK(hperh); - return TIMEOUT; - } - - temp = hperh->perh->DATA; - UNUSED(temp); - } - - if ((spi_wait_flag(hperh, SPI_IF_BUSY, RESET, timeout) != OK)) { - if (hperh->init.crc_calc) - SPI_CRC_RESET(hperh); - - hperh->state = SPI_STATE_READY; - __UNLOCK(hperh); - return TIMEOUT; - } - - if ((hperh->init.crc_calc) && (ald_spi_get_flag_status(hperh, SPI_IF_CRCERR) != RESET)) { - hperh->err_code |= SPI_ERROR_CRC; - SPI_CRC_RESET(hperh); - ald_spi_clear_flag_status(hperh, SPI_IF_CRCERR); - hperh->state = SPI_STATE_READY; - __UNLOCK(hperh); - - return ERROR; - } - - hperh->state = SPI_STATE_READY; - __UNLOCK(hperh); - - return OK; -} - -/** - * @brief Wraps up transmission in non blocking mode. - * @param hperh: pointer to a spi_handle_t structure. - * @param buf: Pointer to data transmitted buffer - * @param size: Amount of data to be sent - * @retval Status, see @ref ald_status_t. - */ -ald_status_t ald_spi_send_by_it(spi_handle_t *hperh, uint8_t *buf, uint16_t size) -{ - assert_param(IS_SPI(hperh->perh)); - - if (hperh->state != SPI_STATE_READY) - return BUSY; - if (buf == NULL || size == 0) - return ERROR; - - __LOCK(hperh); - hperh->state = SPI_STATE_BUSY_TX; - hperh->err_code = SPI_ERROR_NONE; - - hperh->tx_buf = buf; - hperh->tx_size = size; - hperh->tx_count = size; - hperh->rx_buf = NULL; - hperh->rx_size = 0; - hperh->rx_count = 0; - __UNLOCK(hperh); - - if (hperh->init.crc_calc) - SPI_CRC_RESET(hperh); - - if (hperh->init.dir == SPI_DIRECTION_1LINE) - SPI_1LINE_TX(hperh); - - if (hperh->init.dir == SPI_DIRECTION_2LINES) { - ald_spi_interrupt_config(hperh, SPI_IT_TXBE, ENABLE); - } - else { - ald_spi_interrupt_config(hperh, SPI_IT_TXBE, ENABLE); - ald_spi_interrupt_config(hperh, SPI_IT_ERR, ENABLE); - } - - if (READ_BIT(hperh->perh->CON1, SPI_CON1_SPIEN_MSK) == 0) - SPI_ENABLE(hperh); - - return OK; -} - -/** - * @brief Receives an amount of data in non blocking mode - * @param hperh: Pointer to a spi_handle_t structure. - * @param buf: Pointer to data received buffer - * @param size: Amount of data to be sent - * @retval Status, see @ref ald_status_t. - */ -ald_status_t ald_spi_recv_by_it(spi_handle_t *hperh, uint8_t *buf, uint16_t size) -{ - assert_param(IS_SPI(hperh->perh)); - - if (hperh->state != SPI_STATE_READY) - return BUSY; - if (buf == NULL || size == 0) - return ERROR; - if ((hperh->init.dir == SPI_DIRECTION_2LINES) && (hperh->init.mode == SPI_MODE_MASTER)) - return ERROR; /* Please call ald_spi_send_recv_by_it() */ - - __LOCK(hperh); - hperh->state = SPI_STATE_BUSY_RX; - hperh->err_code = SPI_ERROR_NONE; - - hperh->rx_buf = buf; - hperh->rx_size = size; - hperh->rx_count = size; - hperh->tx_buf = NULL; - hperh->tx_size = 0; - hperh->tx_count = 0; - __UNLOCK(hperh); - - if (hperh->init.dir == SPI_DIRECTION_1LINE_RX) - SPI_1LINE_RX(hperh); - - if (hperh->init.crc_calc == ENABLE) - SPI_CRC_RESET(hperh); - - ald_spi_interrupt_config(hperh, SPI_IT_RXBNE, ENABLE); - ald_spi_interrupt_config(hperh, SPI_IT_ERR, ENABLE); - - if ((hperh->init.dir == SPI_DIRECTION_2LINES_RXONLY) || (hperh->init.dir == SPI_DIRECTION_1LINE_RX)) - SPI_ENABLE(hperh); - - return OK; -} - -/** - * @brief Transmit and Receives an amount of data in non blocking mode - * @param hperh: Pointer to a spi_handle_t structure that contains - * the configuration information for the specified SPI module. - * @param tx_buf: Pointer to data transmitted buffer - * @param rx_buf: Pointer to data received buffer - * @param size: Amount of data to be sent - * @retval Status, see @ref ald_status_t. - */ -ald_status_t ald_spi_send_recv_by_it(spi_handle_t *hperh, uint8_t *tx_buf, uint8_t *rx_buf, uint16_t size) -{ - assert_param(IS_SPI(hperh->perh)); - - if (hperh->state != SPI_STATE_READY) - return BUSY; - if (tx_buf == NULL || rx_buf == NULL || size == 0) - return ERROR; - - __LOCK(hperh); - hperh->state = SPI_STATE_BUSY_TX_RX; - hperh->err_code = SPI_ERROR_NONE; - - hperh->tx_buf = tx_buf; - hperh->tx_size = size; - hperh->tx_count = size; - hperh->rx_buf = rx_buf; - hperh->rx_size = size; - hperh->rx_count = size; - __UNLOCK(hperh); - - if (hperh->init.crc_calc) - SPI_CRC_RESET(hperh); - - ald_spi_interrupt_config(hperh, SPI_IT_RXBNE, ENABLE); - ald_spi_interrupt_config(hperh, SPI_IT_TXBE, ENABLE); - ald_spi_interrupt_config(hperh, SPI_IT_ERR, ENABLE); - - return OK; -} - -#ifdef ALD_DMA -/** - * @brief Transmit an amount of data used dma channel - * @param hperh: Pointer to a spi_handle_t structure. - * @param buf: Pointer to data buffer - * @param size: Amount of data to be sent - * @param channel: DMA channel as SPI transmit - * @retval Status, see @ref ald_status_t. - */ -ald_status_t ald_spi_send_by_dma(spi_handle_t *hperh, uint8_t *buf, uint16_t size, uint8_t channel) -{ - assert_param(IS_SPI(hperh->perh)); - - if (hperh->state != SPI_STATE_READY) - return BUSY; - if (buf == NULL || size == 0) - return ERROR; - - __LOCK(hperh); - hperh->state = SPI_STATE_BUSY_TX; - hperh->err_code = SPI_ERROR_NONE; - - hperh->tx_buf = buf; - hperh->tx_size = size; - hperh->tx_count = size; - hperh->rx_buf = NULL; - hperh->rx_size = 0; - hperh->rx_count = 0; - - if (hperh->init.dir == SPI_DIRECTION_1LINE) - SPI_1LINE_TX(hperh); - if (hperh->init.crc_calc) - SPI_CRC_RESET(hperh); - - if (hperh->hdmatx.perh == NULL) - hperh->hdmatx.perh = DMA0; - - hperh->hdmatx.cplt_arg = (void *)hperh; - hperh->hdmatx.cplt_cbk = spi_dma_send_cplt; - hperh->hdmatx.err_arg = (void *)hperh; - hperh->hdmatx.err_cbk = spi_dma_error; - - /* Configure SPI DMA transmit */ - ald_dma_config_struct(&(hperh->hdmatx.config)); - hperh->hdmatx.config.data_width = hperh->init.data_size == SPI_DATA_SIZE_8 ? DMA_DATA_SIZE_BYTE : DMA_DATA_SIZE_HALFWORD; - hperh->hdmatx.config.src = (void *)buf; - hperh->hdmatx.config.dst = (void *)&hperh->perh->DATA; - hperh->hdmatx.config.size = size; - hperh->hdmatx.config.src_inc = hperh->init.data_size == SPI_DATA_SIZE_8 ? DMA_DATA_INC_BYTE : DMA_DATA_INC_HALFWORD; - hperh->hdmatx.config.dst_inc = DMA_DATA_INC_NONE; - hperh->hdmatx.config.msel = hperh->perh == SPI0 ? DMA_MSEL_SPI0 : (hperh->perh == SPI1 ? DMA_MSEL_SPI1 : DMA_MSEL_SPI2); - hperh->hdmatx.config.msigsel = DMA_MSIGSEL_SPI_TXEMPTY; - hperh->hdmatx.config.channel = channel; - ald_dma_config_basic(&(hperh->hdmatx)); - - __UNLOCK(hperh); - ald_spi_dma_req_config(hperh, SPI_DMA_REQ_TX, ENABLE); - - if (READ_BIT(hperh->perh->CON1, SPI_CON1_SPIEN_MSK) == 0) - SPI_ENABLE(hperh); - - return OK; -} - -/** - * @brief Receive an amount of data used dma channel - * @param hperh: Pointer to a spi_handle_t structure. - * @param buf: Pointer to data buffer - * @param size: Amount of data to be sent - * @param channel: DMA channel as SPI transmit - * @retval Status, see @ref ald_status_t. - */ -ald_status_t ald_spi_recv_by_dma(spi_handle_t *hperh, uint8_t *buf, uint16_t size, uint8_t channel) -{ - assert_param(IS_SPI(hperh->perh)); - - if (hperh->state != SPI_STATE_READY) - return BUSY; - if (buf == NULL || size == 0) - return ERROR; - - __LOCK(hperh); - hperh->state = SPI_STATE_BUSY_RX; - hperh->err_code = SPI_ERROR_NONE; - - hperh->rx_buf = buf; - hperh->rx_size = size; - hperh->rx_count = size; - hperh->tx_buf = NULL; - hperh->tx_size = 0; - hperh->tx_count = 0; - - if (hperh->init.dir == SPI_DIRECTION_1LINE_RX) - SPI_1LINE_RX(hperh); - if ((hperh->init.dir == SPI_DIRECTION_2LINES) && (hperh->init.mode == SPI_MODE_MASTER)) { - __UNLOCK(hperh); - return ERROR; /* Please use ald_spi_send_recv_by_dma() */ - } - if (hperh->init.crc_calc) - SPI_CRC_RESET(hperh); - - if (hperh->hdmarx.perh == NULL) - hperh->hdmarx.perh = DMA0; - - hperh->hdmarx.cplt_arg = (void *)hperh; - hperh->hdmarx.cplt_cbk = spi_dma_recv_cplt; - hperh->hdmarx.err_arg = (void *)hperh; - hperh->hdmarx.err_cbk = spi_dma_error; - - /* Configure DMA Receive */ - ald_dma_config_struct(&(hperh->hdmarx.config)); - hperh->hdmarx.config.data_width = hperh->init.data_size == SPI_DATA_SIZE_8 ? DMA_DATA_SIZE_BYTE : DMA_DATA_SIZE_HALFWORD; - hperh->hdmarx.config.src = (void *)&hperh->perh->DATA; - hperh->hdmarx.config.dst = (void *)buf; - hperh->hdmarx.config.size = size; - hperh->hdmarx.config.src_inc = DMA_DATA_INC_NONE; - hperh->hdmarx.config.dst_inc = hperh->init.data_size == SPI_DATA_SIZE_8 ? DMA_DATA_INC_BYTE : DMA_DATA_INC_HALFWORD;; - hperh->hdmarx.config.msel = hperh->perh == SPI0 ? DMA_MSEL_SPI0 : (hperh->perh == SPI1 ? DMA_MSEL_SPI1 : DMA_MSEL_SPI2); - hperh->hdmarx.config.msigsel = DMA_MSIGSEL_SPI_RNR; - hperh->hdmarx.config.channel = channel; - ald_dma_config_basic(&(hperh->hdmarx)); - - __UNLOCK(hperh); - ald_spi_dma_req_config(hperh, SPI_DMA_REQ_RX, ENABLE); - - if ((hperh->init.dir == SPI_DIRECTION_2LINES_RXONLY) || (hperh->init.dir == SPI_DIRECTION_1LINE_RX)) - SPI_ENABLE(hperh); - - return OK; -} - -/** - * @brief Transmit and Receive an amount of data used dma channel - * @param hperh: Pointer to a spi_handle_t structure. - * @param tx_buf: Pointer to data buffer - * @param rx_buf: Pointer to data buffer - * @param size: Amount of data to be sent - * @param tx_channel: DMA channel as SPI transmit - * @param rx_channel: DMA channel as SPI receive - * @retval Status, see @ref ald_status_t. - */ -ald_status_t ald_spi_send_recv_by_dma(spi_handle_t *hperh, uint8_t *tx_buf, uint8_t *rx_buf, uint16_t size, uint8_t tx_channel, uint8_t rx_channel) -{ - assert_param(IS_SPI(hperh->perh)); - - if (hperh->state != SPI_STATE_READY && hperh->state != SPI_STATE_BUSY_RX) - return BUSY; - if (tx_buf == NULL || rx_buf == NULL || size == 0) - return ERROR; - - __LOCK(hperh); - hperh->state = SPI_STATE_BUSY_RX; - hperh->err_code = SPI_ERROR_NONE; - - hperh->tx_buf = tx_buf; - hperh->tx_size = size; - hperh->tx_count = size; - hperh->rx_buf = rx_buf; - hperh->rx_size = size; - hperh->rx_count = size; - - if (hperh->hdmatx.perh == NULL) - hperh->hdmatx.perh = DMA0; - if (hperh->hdmarx.perh == NULL) - hperh->hdmarx.perh = DMA0; - - hperh->hdmatx.cplt_arg = NULL; - hperh->hdmatx.cplt_cbk = NULL; - hperh->hdmatx.err_arg = (void *)hperh; - hperh->hdmatx.err_cbk = spi_dma_error; - hperh->hdmarx.cplt_arg = (void *)hperh; - hperh->hdmarx.cplt_cbk = spi_dma_send_recv_cplt; - hperh->hdmarx.err_arg = (void *)hperh; - hperh->hdmarx.err_cbk = spi_dma_error; - - if (hperh->init.crc_calc) - SPI_CRC_RESET(hperh); - - /* Configure SPI DMA transmit */ - ald_dma_config_struct(&(hperh->hdmatx.config)); - hperh->hdmatx.config.data_width = hperh->init.data_size == SPI_DATA_SIZE_8 ? DMA_DATA_SIZE_BYTE : DMA_DATA_SIZE_HALFWORD; - hperh->hdmatx.config.src = (void *)tx_buf; - hperh->hdmatx.config.dst = (void *)&hperh->perh->DATA; - hperh->hdmatx.config.size = size; - hperh->hdmatx.config.src_inc = hperh->init.data_size == SPI_DATA_SIZE_8 ? DMA_DATA_INC_BYTE : DMA_DATA_INC_HALFWORD; - hperh->hdmatx.config.dst_inc = DMA_DATA_INC_NONE; - hperh->hdmatx.config.msel = hperh->perh == SPI0 ? DMA_MSEL_SPI0 : (hperh->perh == SPI1 ? DMA_MSEL_SPI1 : DMA_MSEL_SPI2); - hperh->hdmatx.config.msigsel = DMA_MSIGSEL_SPI_TXEMPTY; - hperh->hdmatx.config.channel = tx_channel; - ald_dma_config_basic(&(hperh->hdmatx)); - - /* Configure DMA Receive */ - ald_dma_config_struct(&(hperh->hdmarx.config)); - hperh->hdmarx.config.data_width = hperh->init.data_size == SPI_DATA_SIZE_8 ? DMA_DATA_SIZE_BYTE : DMA_DATA_SIZE_HALFWORD; - hperh->hdmarx.config.src = (void *)&hperh->perh->DATA; - hperh->hdmarx.config.dst = (void *)rx_buf; - hperh->hdmarx.config.size = size; - hperh->hdmarx.config.src_inc = DMA_DATA_INC_NONE; - hperh->hdmarx.config.dst_inc = hperh->init.data_size == SPI_DATA_SIZE_8 ? DMA_DATA_INC_BYTE : DMA_DATA_INC_HALFWORD;; - hperh->hdmarx.config.msel = hperh->perh == SPI0 ? DMA_MSEL_SPI0 : (hperh->perh == SPI1 ? DMA_MSEL_SPI1 : DMA_MSEL_SPI2); - hperh->hdmarx.config.msigsel = DMA_MSIGSEL_SPI_RNR; - hperh->hdmarx.config.channel = rx_channel; - ald_dma_config_basic(&(hperh->hdmarx)); - - __UNLOCK(hperh); - ald_spi_dma_req_config(hperh, SPI_DMA_REQ_TX, ENABLE); - ald_spi_dma_req_config(hperh, SPI_DMA_REQ_RX, ENABLE); - - return OK; -} - -/** - * @brief Pauses the DMA Transfer. - * @param hperh: Pointer to a spi_handle_t structure. - * @retval Status - */ -ald_status_t ald_spi_dma_pause(spi_handle_t *hperh) -{ - assert_param(IS_SPI(hperh->perh)); - - __LOCK(hperh); - ald_spi_dma_req_config(hperh, SPI_DMA_REQ_TX, DISABLE); - ald_spi_dma_req_config(hperh, SPI_DMA_REQ_RX, DISABLE); - __UNLOCK(hperh); - - return OK; -} - -/** - * @brief Resumes the DMA Transfer. - * @param hperh: Pointer to a spi_handle_t structure. - * @retval Status - */ -ald_status_t ald_spi_dma_resume(spi_handle_t *hperh) -{ - assert_param(IS_SPI(hperh->perh)); - - __LOCK(hperh); - ald_spi_dma_req_config(hperh, SPI_DMA_REQ_TX, ENABLE); - ald_spi_dma_req_config(hperh, SPI_DMA_REQ_RX, ENABLE); - __UNLOCK(hperh); - - return OK; -} - -/** - * @brief Stops the DMA Transfer. - * @param hperh: Pointer to a spi_handle_t structure. - * @retval Status - */ -ald_status_t ald_spi_dma_stop(spi_handle_t *hperh) -{ - assert_param(IS_SPI(hperh->perh)); - - __LOCK(hperh); - ald_spi_dma_req_config(hperh, SPI_DMA_REQ_TX, DISABLE); - ald_spi_dma_req_config(hperh, SPI_DMA_REQ_RX, DISABLE); - __UNLOCK(hperh); - - hperh->state = SPI_STATE_READY; - return OK; -} -#endif -/** - * @} - */ - -/** @defgroup SPI_Public_Functions_Group3 Control functions - * @brief SPI Control functions - * - * @verbatim - =============================================================================== - ##### Peripheral Control functions ##### - =============================================================================== - [..] - This subsection provides a set of functions allowing to control the SPI. - (+) Handle interrupt about SPI module. The ald_spi_irq_handler() function must - be invoked by SPI-IRQ function. - (+) Configure the interrupt DISABLE/ENABLE. - (+) Configure the DMA request. - (+) Get interrupt source status. - (+) Get interrupt flag status. - (+) Clear interrupt flag - - @endverbatim - * @{ - */ - -/** - * @brief This function handles SPI interrupt request. - * @param hperh: Pointer to a spi_handle_t structure. - * @retval None - */ -void ald_spi_irq_handler(spi_handle_t *hperh) -{ - if ((hperh->state == SPI_STATE_BUSY_RX) || (hperh->state == SPI_STATE_BUSY_TX)) { - if ((ald_spi_get_it_status(hperh, SPI_IT_RXBNE) != RESET) && (ald_spi_get_flag_status(hperh, SPI_IF_RXBNE) != RESET)) - __spi_recv_by_it(hperh); - - if ((ald_spi_get_it_status(hperh, SPI_IT_TXBE) != RESET) && (ald_spi_get_flag_status(hperh, SPI_IF_TXBE) != RESET)) - __spi_send_by_it(hperh); - } - - else if (hperh->state == SPI_STATE_BUSY_TX_RX) { - if (hperh->tx_size == hperh->tx_count) { - if ((ald_spi_get_it_status(hperh, SPI_IT_TXBE) != RESET) && (ald_spi_get_flag_status(hperh, SPI_IF_TXBE) != RESET)) - __spi_send_recv_by_it(hperh, SPI_SR_TXBE); - } - else { - if (hperh->init.mode == SPI_MODE_MASTER) { - if ((ald_spi_get_it_status(hperh, SPI_IT_TXBE) != RESET) && (ald_spi_get_flag_status(hperh, SPI_IF_TXBE) != RESET) - && (ald_spi_get_it_status(hperh, SPI_IT_RXBNE) != RESET) && (ald_spi_get_flag_status(hperh, SPI_IF_RXBNE) != RESET)) - __spi_send_recv_by_it(hperh, SPI_SR_TXBE_RXBNE); - } - else { - if ((ald_spi_get_it_status(hperh, SPI_IT_RXBNE) != RESET) && (ald_spi_get_flag_status(hperh, SPI_IF_RXBNE) != RESET)) - __spi_send_recv_by_it(hperh, SPI_SR_RXBNE); - - if ((ald_spi_get_it_status(hperh, SPI_IT_TXBE) != RESET) && (ald_spi_get_flag_status(hperh, SPI_IF_TXBE) != RESET)) - __spi_send_recv_by_it(hperh, SPI_SR_TXBE); - } - - - } - } - - if ((ald_spi_get_it_status(hperh, SPI_IT_ERR) != RESET)) { - if (ald_spi_get_flag_status(hperh, SPI_IF_CRCERR) != RESET) { - hperh->err_code |= SPI_ERROR_CRC; - ald_spi_clear_flag_status(hperh, SPI_IF_CRCERR); - } - if (ald_spi_get_flag_status(hperh, SPI_IF_MODF) != RESET) { - hperh->err_code |= SPI_ERROR_MODF; - ald_spi_clear_flag_status(hperh, SPI_IF_MODF); - } - if (ald_spi_get_flag_status(hperh, SPI_IF_OVE) != RESET) { - if ((hperh->state != SPI_STATE_BUSY_TX) && (hperh->state != SPI_STATE_READY)) { - hperh->err_code |= SPI_ERROR_OVE; - ald_spi_clear_flag_status(hperh, SPI_IF_OVE); - } - } - - if (hperh->err_code != SPI_ERROR_NONE) { - ald_spi_interrupt_config(hperh, SPI_IT_RXBNE, DISABLE); - ald_spi_interrupt_config(hperh, SPI_IT_TXBE, DISABLE); - ald_spi_interrupt_config(hperh, SPI_IT_ERR, DISABLE); - hperh->state = SPI_STATE_READY; - - if (hperh->err_cbk) - hperh->err_cbk(hperh); - } - } - - return; -} - -/** - * @brief Enables or disables the specified SPI interrupts. - * @param hperh: Pointer to a spi_handle_t structure. - * @param it: Specifies the SPI interrupt sources to be enabled or disabled. - * This parameter can be one of the @ref spi_it_t. - * @param state: New status - * - ENABLE - * - DISABLE - * @retval None - */ -void ald_spi_interrupt_config(spi_handle_t *hperh, spi_it_t it, type_func_t state) -{ - assert_param(IS_SPI(hperh->perh)); - assert_param(IS_SPI_IT(it)); - assert_param(IS_FUNC_STATE(state)); - - if (state == ENABLE) - hperh->perh->CON2 |= (uint32_t)it; - else - hperh->perh->CON2 &= ~((uint32_t)it); - - return; -} - -/** - * @brief Configure the specified SPI speed. - * @param hperh: Pointer to a spi_handle_t structure. - * @param speed: Specifies the SPI speed. - * This parameter can be one of the @ref spi_baud_t. - * @retval None - */ -void ald_spi_speed_config(spi_handle_t *hperh, spi_baud_t speed) -{ - uint32_t tmp = 0; - assert_param(IS_SPI(hperh->perh)); - assert_param(IS_SPI_BAUD(speed)); - - tmp = hperh->perh->CON1; - tmp &= ~(0x7U << SPI_CON1_BAUD_POSS); - tmp |= (speed << SPI_CON1_BAUD_POSS); - hperh->perh->CON1 = tmp; - return; -} - -/** - * @brief Enables or disables the dma request. - * @param hperh: Pointer to a spi_handle_t structure. - * @param req: Specifies the SPI dma request sources to be enabled or disabled. - * This parameter can be one of the @ref spi_dma_req_t. - * @param state: New status - * - ENABLE - * - DISABLE - * @retval None - */ -void ald_spi_dma_req_config(spi_handle_t *hperh, spi_dma_req_t req, type_func_t state) -{ - assert_param(IS_SPI(hperh->perh)); - assert_param(IS_SPI_DMA_REQ(req)); - assert_param(IS_FUNC_STATE(state)); - - if (state == ENABLE) { - if (req == SPI_DMA_REQ_TX) - SET_BIT(hperh->perh->CON2, SPI_CON2_TXDMA_MSK); - else - SET_BIT(hperh->perh->CON2, SPI_CON2_RXDMA_MSK); - } - else { - if (req == SPI_DMA_REQ_TX) - CLEAR_BIT(hperh->perh->CON2, SPI_CON2_TXDMA_MSK); - else - CLEAR_BIT(hperh->perh->CON2, SPI_CON2_RXDMA_MSK); - } - - return; -} - -/** @brief Check whether the specified SPI state flag is set or not. - * @param hperh: Pointer to a spi_handle_t structure. - * @param status: specifies the flag to check. - * This parameter can be one of the @ref spi_status_t. - * @retval Status - * - SET - * - RESET - */ -flag_status_t spi_get_status(spi_handle_t *hperh, spi_status_t status) -{ - assert_param(IS_SPI(hperh->perh)); - assert_param(IS_SPI_STATUS(status)); - - if (hperh->perh->STAT & status) - return SET; - - return RESET; -} - -/** - * @brief Checks whether the specified SPI interrupt has occurred or not. - * @param hperh: Pointer to a spi_handle_t structure. - * @param it: Specifies the SPI interrupt source to check. - * This parameter can be one of the @ref spi_it_t. - * @retval Status - * - SET - * - RESET - */ -it_status_t ald_spi_get_it_status(spi_handle_t *hperh, spi_it_t it) -{ - assert_param(IS_SPI(hperh->perh)); - assert_param(IS_SPI_IT(it)); - - if (hperh->perh->CON2 & it) - return SET; - - return RESET; -} - -/** @brief Check whether the specified SPI flag is set or not. - * @param hperh: Pointer to a spi_handle_t structure. - * @param flag: specifies the flag to check. - * This parameter can be one of the @ref spi_flag_t. - * @retval Status - * - SET - * - RESET - */ -flag_status_t ald_spi_get_flag_status(spi_handle_t *hperh, spi_flag_t flag) -{ - assert_param(IS_SPI(hperh->perh)); - assert_param(IS_SPI_IF(flag)); - - if (hperh->perh->STAT & flag) - return SET; - - return RESET; -} - -/** @brief Clear the specified SPI pending flags. - * @param hperh: Pointer to a spi_handle_t structure. - * @param flag: specifies the flag to check. - * This parameter can be one of the @ref spi_flag_t. - * @retval None - */ -void ald_spi_clear_flag_status(spi_handle_t *hperh, spi_flag_t flag) -{ - uint32_t temp; - - assert_param(IS_SPI(hperh->perh)); - assert_param(IS_SPI_IF(flag)); - - if (flag == SPI_IF_CRCERR) { - SET_BIT(hperh->perh->STAT, SPI_STAT_CRCERR_MSK); - return; - } - if (flag == SPI_IF_OVE) { - temp = hperh->perh->DATA; - temp = hperh->perh->STAT; - UNUSED(temp); - return; - } - if (flag == SPI_IF_MODF) { - temp = hperh->perh->STAT; - UNUSED(temp); - hperh->perh->CON1 = hperh->perh->CON1; - return; - } - - return; -} - -/** - * @brief This function handles SPI communication timeout. - * @param hperh: Pointer to a spi_handle_t structure. - * @param flag: specifies the SPI flag to check. - * @param status: The new Flag status (SET or RESET). - * @param timeout: Timeout duration - * @retval Status, see @ref ald_status_t. - */ -static ald_status_t spi_wait_flag(spi_handle_t *hperh, spi_flag_t flag, flag_status_t status, uint32_t timeout) -{ - uint32_t tick = ald_get_tick(); - - assert_param(timeout > 0); - - while ((ald_spi_get_flag_status(hperh, flag)) != status) { - if (((ald_get_tick()) - tick) > timeout) { - ald_spi_interrupt_config(hperh, SPI_IT_TXBE, DISABLE); - ald_spi_interrupt_config(hperh, SPI_IT_RXBNE, DISABLE); - ald_spi_interrupt_config(hperh, SPI_IT_ERR, DISABLE); - return TIMEOUT; - } - } - - return OK; -} - -/** - * @brief This function handles SPI communication timeout in interrupt function. - * @param hperh: Pointer to a spi_handle_t structure. - * @param flag: specifies the SPI flag to check. - * @param status: The new Flag status (SET or RESET). - * @param timeout: Timeout duration - * @retval Status, see @ref ald_status_t. - */ -static ald_status_t spi_wait_flag_irq(spi_handle_t *hperh, spi_flag_t flag, flag_status_t status, uint32_t timeout) -{ - assert_param(timeout > 0); - - while (((ald_spi_get_flag_status(hperh, flag)) != status) && (--timeout)); - - if (timeout) - return OK; - - ald_spi_interrupt_config(hperh, SPI_IT_TXBE, DISABLE); - ald_spi_interrupt_config(hperh, SPI_IT_RXBNE, DISABLE); - ald_spi_interrupt_config(hperh, SPI_IT_ERR, DISABLE); - - return TIMEOUT; -} - -/** - * @} - */ - -/** @defgroup SPI_Public_Functions_Group4 Peripheral State and Errors functions - * @brief SPI State and Errors functions - * - * @verbatim - =============================================================================== - ##### Peripheral State and Errors functions ##### - =============================================================================== - [..] - This subsection provides a set of functions allowing to control the SPI. - (+) ald_spi_get_state() API can check in run-time the state of the SPI peripheral - (+) ald_spi_get_error() check in run-time Errors occurring during communication - - @endverbatim - * @{ - */ - -/** - * @brief Returns the SPI state. - * @param hperh: Pointer to a spi_handle_t structure. - * @retval ALD state - */ -spi_state_t ald_spi_get_state(spi_handle_t *hperh) -{ - assert_param(IS_SPI(hperh->perh)); - return hperh->state; -} - -/** - * @brief Return the SPI error code - * @param hperh: Pointer to a spi_handle_t structure. - * @retval SPI Error Code - */ -uint32_t ald_spi_get_error(spi_handle_t *hperh) -{ - assert_param(IS_SPI(hperh->perh)); - return hperh->err_code; -} -/** - * @} - */ - -/** - * @} - */ - -/** @defgroup SPI_Private_Functions SPI Private Functions - * @brief SPI Private functions - * @{ - */ - -/** - * @brief handle program when an tx empty interrupt flag arrived in non block mode - * @param hperh: Pointer to a spi_handle_t structure. - * @retval Status, see @ref ald_status_t. - */ -static void __spi_send_by_it(spi_handle_t *hperh) -{ - if (hperh->tx_count == 0) { - ald_spi_interrupt_config(hperh, SPI_IT_TXBE, DISABLE); - ald_spi_interrupt_config(hperh, SPI_IT_ERR, DISABLE); - hperh->state = SPI_STATE_READY; - - if (hperh->init.dir == SPI_DIRECTION_2LINES) - ald_spi_clear_flag_status(hperh, SPI_IF_OVE); - - if ((spi_wait_flag_irq(hperh, SPI_IF_BUSY, RESET, 5000)) != OK) { - if (hperh->err_cbk) - hperh->err_cbk(hperh); - - return; - } - - if (hperh->tx_cplt_cbk) - hperh->tx_cplt_cbk(hperh); - - return; - } - - if (hperh->init.data_size == SPI_DATA_SIZE_8) { - hperh->perh->DATA = *hperh->tx_buf; - ++hperh->tx_buf; - } - else { - hperh->perh->DATA = *(uint16_t *)hperh->tx_buf; - hperh->tx_buf += 2; - } - --hperh->tx_count; - - if (hperh->tx_count == 0) { - if (hperh->init.crc_calc) - SPI_CRCNEXT_ENABLE(hperh); - } - - return; -} - -/** - * @brief handle program when an rx no empty interrupt flag arrived in non block mode - * @param hperh: Pointer to a spi_handle_t structure. - * @retval Status, see @ref ald_status_t. - */ -static void __spi_recv_by_it(spi_handle_t *hperh) -{ - uint16_t temp; - if (hperh->init.data_size == SPI_DATA_SIZE_8) { - *hperh->rx_buf = hperh->perh->DATA; - ++hperh->rx_buf; - } - else { - *(uint16_t *)hperh->rx_buf = hperh->perh->DATA; - hperh->rx_buf += 2; - } - --hperh->rx_count; - - if ((hperh->rx_count == 1) && (hperh->init.crc_calc)) - SPI_CRCNEXT_ENABLE(hperh); - - if (hperh->rx_count == 0) { - ald_spi_interrupt_config(hperh, SPI_IT_RXBNE, DISABLE); - ald_spi_interrupt_config(hperh, SPI_IT_ERR, DISABLE); - hperh->state = SPI_STATE_READY; - - if ((hperh->init.crc_calc) && (ald_spi_get_flag_status(hperh, SPI_IF_CRCERR) != RESET)) { - hperh->err_code |= SPI_ERROR_CRC; - ald_spi_clear_flag_status(hperh, SPI_IF_CRCERR); - - if (hperh->err_cbk) - hperh->err_cbk(hperh); - - return; - } - - if (hperh->init.crc_calc) { - temp = hperh->perh->DATA; - UNUSED(temp); - } - - if (hperh->rx_cplt_cbk) - hperh->rx_cplt_cbk(hperh); - } - - return; -} - -/** - * @brief handle program when an rx no empty interrupt flag arrived in non block mode(2 lines) - * @param hperh: Pointer to a spi_handle_t structure. - * @param status: SR.TXE or SR.RXNE set. - * @retval Status, see @ref ald_status_t. - */ -static void __spi_send_recv_by_it(spi_handle_t *hperh, spi_sr_status_t status) -{ - assert_param(IS_SPI_SR_STATUS(status)); - - if (hperh->rx_count != 0) { - if ((status == SPI_SR_RXBNE) || (status == SPI_SR_TXBE_RXBNE)) { - if (hperh->init.data_size == SPI_DATA_SIZE_8) { - *hperh->rx_buf = hperh->perh->DATA; - ++hperh->rx_buf; - } - else { - *(uint16_t *)hperh->rx_buf = hperh->perh->DATA; - hperh->rx_buf += 2; - } - - --hperh->rx_count; - } - } - - if (hperh->tx_count != 0) { - if ((status == SPI_SR_TXBE) || (status == SPI_SR_TXBE_RXBNE)) { - if (hperh->tx_count == 1) { - if (hperh->init.data_size == SPI_DATA_SIZE_8) { - hperh->perh->DATA = *hperh->tx_buf; - ++hperh->tx_buf; - } - else { - hperh->perh->DATA = *(uint16_t *)hperh->tx_buf; - hperh->tx_buf += 2; - } - - --hperh->tx_count; - - if (hperh->init.crc_calc) - SPI_CRCNEXT_ENABLE(hperh); - } - else { - if (hperh->init.data_size == SPI_DATA_SIZE_8) { - hperh->perh->DATA = *hperh->tx_buf; - ++hperh->tx_buf; - } - else { - hperh->perh->DATA = *(uint16_t *)hperh->tx_buf; - hperh->tx_buf += 2; - } - - if (--hperh->tx_count == 0) { - if (hperh->init.crc_calc) - SPI_CRCNEXT_ENABLE(hperh); - ald_spi_interrupt_config(hperh, SPI_IT_TXBE, DISABLE); - } - } - } - } - - if (hperh->rx_count == 0) { - ald_spi_interrupt_config(hperh, SPI_IT_TXBE, DISABLE); - ald_spi_interrupt_config(hperh, SPI_IT_RXBNE, DISABLE); - ald_spi_interrupt_config(hperh, SPI_IT_ERR, DISABLE); - hperh->state = SPI_STATE_READY; - - if ((hperh->init.crc_calc) && (ald_spi_get_flag_status(hperh, SPI_IF_CRCERR) != RESET)) { - hperh->err_code |= SPI_ERROR_CRC; - ald_spi_clear_flag_status(hperh, SPI_IF_CRCERR); - - if (hperh->err_cbk) - hperh->err_cbk(hperh); - - return; - } - - if (hperh->tx_rx_cplt_cbk) - hperh->tx_rx_cplt_cbk(hperh); - } - - return; -} - -#ifdef ALD_DMA -/** - * @brief DMA SPI transmit process complete callback. - * @param arg: Pointer to a spi_handle_t structure. - * @retval None - */ -static void spi_dma_send_cplt(void *arg) -{ - uint16_t delay; - spi_handle_t *hperh = (spi_handle_t *)arg; - - hperh->tx_count = 0; - ald_spi_dma_req_config(hperh, SPI_DMA_REQ_TX, DISABLE); - hperh->state = SPI_STATE_READY; - - if (hperh->init.dir == SPI_DIRECTION_2LINES) - ald_spi_clear_flag_status(hperh, SPI_IF_OVE); - - if ((spi_wait_flag_irq(hperh, SPI_IF_BUSY, RESET, 5000)) != OK) - hperh->err_code |= SPI_ERROR_FLAG; - - for (delay = 0; delay < 3000; delay++); - - if (hperh->err_code == SPI_ERROR_NONE) { - if (hperh->tx_cplt_cbk) - hperh->tx_cplt_cbk(hperh); - } - else { - if (hperh->err_cbk) - hperh->err_cbk(hperh); - } - - return; -} - -/** - * @brief DMA SPI receive process complete callback. - * @param arg: Pointer to a spi_handle_t structure. - * @retval None - */ -static void spi_dma_recv_cplt(void *arg) -{ - uint32_t tmp; - spi_handle_t *hperh = (spi_handle_t *)arg; - - hperh->rx_count = 0; - ald_spi_dma_req_config(hperh, SPI_DMA_REQ_TX, DISABLE); - ald_spi_dma_req_config(hperh, SPI_DMA_REQ_RX, DISABLE); - hperh->state = SPI_STATE_READY; - - if (hperh->init.crc_calc) { - if ((spi_wait_flag_irq(hperh, SPI_IF_RXBNE, SET, 5000)) != OK) - hperh->err_code |= SPI_ERROR_FLAG; - - tmp = hperh->perh->DATA; - UNUSED(tmp); - - if (ald_spi_get_flag_status(hperh, SPI_IF_CRCERR) == SET) { - SET_BIT(hperh->err_code, SPI_ERROR_CRC); - SPI_CRC_RESET(hperh); - ald_spi_clear_flag_status(hperh, SPI_IF_CRCERR); - } - } - - if (hperh->err_code == SPI_ERROR_NONE) { - if (hperh->rx_cplt_cbk) - hperh->rx_cplt_cbk(hperh); - } - else { - if (hperh->err_cbk) - hperh->err_cbk(hperh); - } - - return; -} - -/** - * @brief DMA SPI transmit and receive process complete callback. - * @param arg: Pointer to a SPI_handle_t structure. - * @retval None - */ -static void spi_dma_send_recv_cplt(void *arg) -{ - uint32_t tmp; - uint16_t delay; - spi_handle_t *hperh = (spi_handle_t *)arg; - - if (hperh->init.crc_calc) { - if ((spi_wait_flag_irq(hperh, SPI_IF_RXBNE, SET, 5000)) != OK) - hperh->err_code |= SPI_ERROR_FLAG; - - tmp = hperh->perh->DATA; - UNUSED(tmp); - - if (ald_spi_get_flag_status(hperh, SPI_IF_CRCERR) == SET) { - SET_BIT(hperh->err_code, SPI_ERROR_CRC); - ald_spi_clear_flag_status(hperh, SPI_IF_CRCERR); - } - } - - if ((spi_wait_flag_irq(hperh, SPI_IF_BUSY, RESET, 5000)) != OK) - hperh->err_code |= SPI_ERROR_FLAG; - - for (delay = 0; delay < 3000; delay++); - - ald_spi_dma_req_config(hperh, SPI_DMA_REQ_TX, DISABLE); - ald_spi_dma_req_config(hperh, SPI_DMA_REQ_RX, DISABLE); - hperh->tx_count = 0; - hperh->rx_count = 0; - hperh->state = SPI_STATE_READY; - - if (hperh->err_code == SPI_ERROR_NONE) { - if (hperh->tx_rx_cplt_cbk) - hperh->tx_rx_cplt_cbk(hperh); - } - else { - if (hperh->err_cbk) - hperh->err_cbk(hperh); - } - - return; -} - -/** - * @brief DMA SPI communication error callback. - * @param arg: Pointer to a spi_handle_t structure that contains - * the configuration information for the specified SPI module. - * @retval None - */ -static void spi_dma_error(void *arg) -{ - spi_handle_t *hperh = (spi_handle_t *)arg; - - ald_spi_dma_req_config(hperh, SPI_DMA_REQ_TX, DISABLE); - ald_spi_dma_req_config(hperh, SPI_DMA_REQ_RX, DISABLE); - SET_BIT(hperh->err_code, SPI_ERROR_DMA); - - hperh->tx_count = 0; - hperh->rx_count = 0; - hperh->state = SPI_STATE_READY; - - if (hperh->err_cbk) - hperh->err_cbk(hperh); - - return; -} -#endif /* ALD_DMA */ -/** - * @} - */ -#endif /* ALD_SPI */ -/** - * @} - */ - -/** - * @} - */ diff --git a/bsp/essemi/es32f0334/libraries/ES32F033x_ALD_StdPeriph_Driver/Source/ald_timer.c b/bsp/essemi/es32f0334/libraries/ES32F033x_ALD_StdPeriph_Driver/Source/ald_timer.c deleted file mode 100644 index dc0a285368..0000000000 --- a/bsp/essemi/es32f0334/libraries/ES32F033x_ALD_StdPeriph_Driver/Source/ald_timer.c +++ /dev/null @@ -1,3675 +0,0 @@ -/** - ********************************************************************************* - * - * @file ald_timer.c - * @brief TIMER module driver. - * This is the common part of the TIMER initialization - * - * @version V1.0 - * @date 06 Nov 2017 - * @author AE Team - * @note - * - * Copyright (C) Shanghai Eastsoft Microelectronics Co. Ltd. All rights reserved. - * - ********************************************************************************* - */ - -#include -#include "ald_timer.h" -#include "ald_cmu.h" - - -/** @addtogroup ES32FXXX_ALD - * @{ - */ - -/** @defgroup TIMER TIMER - * @brief TIMER module driver - * @{ - */ -#ifdef ALD_TIMER - -/** @defgroup TIMER_Private_Functions TIMER Private Functions - * @{ - */ -static void timer_base_set_config(TIMER_TypeDef *TIMERx, timer_base_init_t *init); -static void timer_oc1_set_config(TIMER_TypeDef *TIMERx, timer_oc_init_t *oc_config); -static void timer_oc2_set_config(TIMER_TypeDef *TIMERx, timer_oc_init_t *oc_config); -static void timer_oc3_set_config(TIMER_TypeDef *TIMERx, timer_oc_init_t *oc_config); -static void timer_oc4_set_config(TIMER_TypeDef *TIMERx, timer_oc_init_t *oc_config); -static void timer_ccx_channel_cmd(TIMER_TypeDef* TIMERx, timer_channel_t ch, type_func_t state); -static void timer_ccxn_channel_cmd(TIMER_TypeDef* TIMERx, timer_channel_t ch, type_func_t state); -static void timer_ti1_set_config(TIMER_TypeDef *TIMERx, timer_ic_polarity_t polarity, - timer_ic_select_t sel, uint32_t filter); -static void timer_ti1_set_config_stage(TIMER_TypeDef *TIMERx, timer_ic_polarity_t polarity, uint32_t filter); -static void timer_ti2_set_config(TIMER_TypeDef *TIMERx, timer_ic_polarity_t polarity, - timer_ic_select_t sel, uint32_t filter); -static void timer_ti2_set_config_stage(TIMER_TypeDef *TIMERx, timer_ic_polarity_t polarity, uint32_t filter); -static void timer_ti3_set_config(TIMER_TypeDef *TIMERx, timer_ic_polarity_t polarity, - timer_ic_select_t sel, uint32_t filter); -static void timer_ti4_set_config(TIMER_TypeDef *TIMERx, timer_ic_polarity_t polarity, - timer_ic_select_t sel, uint32_t filter); -static void timer_etr_set_config(TIMER_TypeDef* TIMERx, timer_etr_psc_t psc, timer_clock_polarity_t polarity, uint32_t filter); -static void timer_slave_set_config(timer_handle_t *hperh, timer_slave_config_t *config); -#ifdef ALD_DMA -static void timer_dma_oc_cplt(void *arg); -static void timer_dma_capture_cplt(void *arg); -static void timer_dma_period_elapse_cplt(void *arg); -static void timer_dma_error(void *arg); -static void timer_dma_msel(TIMER_TypeDef *hperh, dma_config_t *config); -#endif -/** - * @} - */ - -/** @defgroup TIMER_Public_Functions TIMER Public Functions - * @{ - */ - -/** @defgroup TIMER_Public_Functions_Group1 TIMER Base functions - * @brief Time Base functions - * - * @verbatim - ============================================================================== - ##### Timer Base functions ##### - ============================================================================== - [..] - This section provides functions allowing to: - (+) Initialize and configure the TIMER base. - (+) Reset the TIMER base. - (+) Start the Time Base. - (+) Stop the Time Base. - (+) Start the Time Base and enable interrupt. - (+) Stop the Time Base and disable interrupt. - (+) Start the Time Base and enable DMA transfer. - (+) Stop the Time Base and disable DMA transfer. - - @endverbatim - * @{ - */ -/** - * @brief Initializes the TIMER Time base Unit according to the specified - * parameters in the timer_handle_t and create the associated handle. - * @param hperh: TIMER base handle - * @retval Status, see @ref ald_status_t. - */ -ald_status_t ald_timer_base_init(timer_handle_t *hperh) -{ - if (hperh == NULL) - return ERROR; - - assert_param(IS_TIMER_INSTANCE(hperh->perh)); - assert_param(IS_TIMER_COUNTER_MODE(hperh->init.mode)); - assert_param(IS_TIMER_CLOCK_DIVISION(hperh->init.clk_div)); - - if (hperh->state == TIMER_STATE_RESET) - hperh->lock = UNLOCK; - - hperh->state = TIMER_STATE_BUSY; - timer_base_set_config(hperh->perh, &hperh->init); - hperh->state = TIMER_STATE_READY; - - return OK; -} - -/** - * @brief Reset the TIMER base peripheral - * @param hperh: TIMER base handle - * @retval Status, see @ref ald_status_t. - */ -void ald_timer_base_reset(timer_handle_t *hperh) -{ - assert_param(IS_TIMER_INSTANCE(hperh->perh)); - - hperh->state = TIMER_STATE_BUSY; - TIMER_DISABLE(hperh); - hperh->state = TIMER_STATE_RESET; - __UNLOCK(hperh); - - return; -} - -/** - * @brief Starts the TIMER Base generation. - * @param hperh: TIMER handle - * @retval None - */ -void ald_timer_base_start(timer_handle_t *hperh) -{ - assert_param(IS_TIMER_INSTANCE(hperh->perh)); - - hperh->state = TIMER_STATE_BUSY; - SET_BIT(hperh->perh->SGE, TIMER_SGE_SGU_MSK); - SET_BIT(hperh->perh->ICR, TIMER_ICR_UEIC_MSK); - TIMER_ENABLE(hperh); - hperh->state = TIMER_STATE_READY; - - return; -} - -/** - * @brief Stops the TIMER Base generation. - * @param hperh: TIMER handle - * @retval None - */ -void ald_timer_base_stop(timer_handle_t *hperh) -{ - assert_param(IS_TIMER_INSTANCE(hperh->perh)); - - hperh->state = TIMER_STATE_BUSY; - TIMER_DISABLE(hperh); - hperh->state = TIMER_STATE_READY; - - return; -} - -/** - * @brief Starts the TIMER Base generation in interrupt mode. - * @param hperh: TIMER handle - * @retval None - */ -void ald_timer_base_start_by_it(timer_handle_t *hperh) -{ - assert_param(IS_TIMER_INSTANCE(hperh->perh)); - - ald_timer_interrupt_config(hperh, TIMER_IT_UPDATE, ENABLE); - TIMER_ENABLE(hperh); - - return; -} - -/** - * @brief Stops the TIMER Base generation in interrupt mode. - * @param hperh: TIMER handle - * @retval None - */ -void ald_timer_base_stop_by_it(timer_handle_t *hperh) -{ - assert_param(IS_TIMER_INSTANCE(hperh->perh)); - - ald_timer_interrupt_config(hperh, TIMER_IT_UPDATE, DISABLE); - TIMER_DISABLE(hperh); - - return; -} - -#ifdef ALD_DMA -/** - * @brief Starts the TIMER Base generation in DMA mode. - * @param hperh: TIMER handle - * @param buf: The source Buffer address. - * @param len: The length of buffer to be transferred from memory to TIMER peripheral - * @param dma_ch: Channel of DMA. - * @retval Status, see @ref ald_status_t. -*/ -ald_status_t ald_timer_base_start_by_dma(timer_handle_t *hperh, - uint16_t *buf, uint32_t len, uint8_t dma_ch) -{ - assert_param(IS_TIMER_INSTANCE(hperh->perh)); - - if ((hperh->state == TIMER_STATE_BUSY)) - return BUSY; - if ((hperh->state == TIMER_STATE_READY)) { - if (((uint32_t)buf == 0 ) || (len == 0)) - return ERROR; - } - - hperh->state = TIMER_STATE_BUSY; - - if (hperh->hdma1.perh == NULL) - hperh->hdma1.perh = DMA0; - - hperh->hdma1.cplt_cbk = timer_dma_period_elapse_cplt; - hperh->hdma1.cplt_arg = (void *)hperh; - hperh->hdma1.err_cbk = timer_dma_error; - hperh->hdma1.err_arg = (void *)hperh; - - ald_dma_config_struct(&hperh->hdma1.config); - hperh->hdma1.config.src = (void *)buf; - hperh->hdma1.config.dst = (void *)&hperh->perh->AR; - hperh->hdma1.config.size = len; - hperh->hdma1.config.data_width = DMA_DATA_SIZE_HALFWORD; - hperh->hdma1.config.src_inc = DMA_DATA_INC_HALFWORD; - hperh->hdma1.config.dst_inc = DMA_DATA_INC_NONE; - hperh->hdma1.config.msigsel = DMA_MSIGSEL_TIMER_UPDATE; - hperh->hdma1.config.channel = dma_ch; - - timer_dma_msel(hperh->perh, &hperh->hdma1.config); - ald_dma_config_basic(&hperh->hdma1); - ald_timer_dma_req_config(hperh, TIMER_DMA_UPDATE, ENABLE); - TIMER_ENABLE(hperh); - - return OK; -} - -/** - * @brief Stops the TIMER Base generation in DMA mode. - * @param hperh: TIMER handle - * @retval None -*/ -void ald_timer_base_stop_by_dma(timer_handle_t *hperh) -{ - assert_param(IS_TIMER_INSTANCE(hperh->perh)); - - ald_timer_dma_req_config(hperh, TIMER_DMA_UPDATE, DISABLE); - TIMER_DISABLE(hperh); - hperh->state = TIMER_STATE_READY; - - return; -} -#endif -/** - * @} - */ - -/** @defgroup TIMER_Public_Functions_Group2 TIMER Output Compare functions - * @brief Time Output Compare functions - * - * @verbatim - ============================================================================== - ##### Time Output Compare functions ##### - ============================================================================== - [..] - This section provides functions allowing to: - (+) Initialize and configure the TIMER Output Compare. - (+) Start the Time Output Compare. - (+) Stop the Time Output Compare. - (+) Start the Time Output Compare and enable interrupt. - (+) Stop the Time Output Compare and disable interrupt. - (+) Start the Time Output Compare and enable DMA transfer. - (+) Stop the Time Output Compare and disable DMA transfer. - - @endverbatim - * @{ - */ -/** - * @brief Initializes the TIMER Output Compare according to the specified - * parameters in the timer_handle_t and create the associated handle. - * @param hperh: TIMER handle - * @retval Status, see @ref ald_status_t. - */ -ald_status_t ald_timer_oc_init(timer_handle_t *hperh) -{ - return ald_timer_base_init(hperh); -} - -/** - * @brief Starts the TIMER Output Compare signal generation. - * @param hperh: TIMER handle - * @param ch : TIMER Channel to be enabled - * This parameter can be one of the following values: - * @arg TIMER_CHANNEL_1: TIMER Channel 1 selected - * @arg TIMER_CHANNEL_2: TIMER Channel 2 selected - * @arg TIMER_CHANNEL_3: TIMER Channel 3 selected - * @arg TIMER_CHANNEL_4: TIMER Channel 4 selected - * @retval None - */ -void ald_timer_oc_start(timer_handle_t *hperh, timer_channel_t ch) -{ - assert_param(IS_TIMER_CCX_INSTANCE(hperh->perh, ch)); - - timer_ccx_channel_cmd(hperh->perh, ch, ENABLE); - - if (IS_TIMER_BREAK_INSTANCE(hperh->perh) != RESET) - TIMER_MOE_ENABLE(hperh); - - TIMER_ENABLE(hperh); - return; -} - -/** - * @brief Stops the TIMER Output Compare signal generation. - * @param hperh: TIMER handle - * @param ch: TIMER Channel to be disabled - * This parameter can be one of the following values: - * @arg TIMER_CHANNEL_1: TIMER Channel 1 selected - * @arg TIMER_CHANNEL_2: TIMER Channel 2 selected - * @arg TIMER_CHANNEL_3: TIMER Channel 3 selected - * @arg TIMER_CHANNEL_4: TIMER Channel 4 selected - * @retval None - */ -void ald_timer_oc_stop(timer_handle_t *hperh, timer_channel_t ch) -{ - assert_param(IS_TIMER_CCX_INSTANCE(hperh->perh, ch)); - - timer_ccx_channel_cmd(hperh->perh, ch, DISABLE); - - if (IS_TIMER_BREAK_INSTANCE(hperh->perh) != RESET) - TIMER_MOE_DISABLE(hperh); - - TIMER_DISABLE(hperh); - hperh->state = TIMER_STATE_READY; - return; -} - -/** - * @brief Starts the TIMER Output Compare signal generation in interrupt mode. - * @param hperh: TIMER handle - * @param ch: TIMER Channel to be enabled - * This parameter can be one of the following values: - * @arg TIMER_CHANNEL_1: TIMER Channel 1 selected - * @arg TIMER_CHANNEL_2: TIMER Channel 2 selected - * @arg TIMER_CHANNEL_3: TIMER Channel 3 selected - * @arg TIMER_CHANNEL_4: TIMER Channel 4 selected - * @retval None - */ -void ald_timer_oc_start_by_it(timer_handle_t *hperh, timer_channel_t ch) -{ - assert_param(IS_TIMER_CCX_INSTANCE(hperh->perh, ch)); - - switch (ch) { - case TIMER_CHANNEL_1: - ald_timer_interrupt_config(hperh, TIMER_IT_CC1, ENABLE); - break; - - case TIMER_CHANNEL_2: - ald_timer_interrupt_config(hperh, TIMER_IT_CC2, ENABLE); - break; - - case TIMER_CHANNEL_3: - ald_timer_interrupt_config(hperh, TIMER_IT_CC3, ENABLE); - break; - - case TIMER_CHANNEL_4: - ald_timer_interrupt_config(hperh, TIMER_IT_CC4, ENABLE); - break; - - default: - break; - } - - timer_ccx_channel_cmd(hperh->perh, ch, ENABLE); - - if (IS_TIMER_BREAK_INSTANCE(hperh->perh) != RESET) - TIMER_MOE_ENABLE(hperh); - - TIMER_ENABLE(hperh); - return; -} - -/** - * @brief Stops the TIMER Output Compare signal generation in interrupt mode. - * @param hperh: TIMER handle - * @param ch: TIMER Channel to be disabled - * This parameter can be one of the following values: - * @arg TIMER_CHANNEL_1: TIMER Channel 1 selected - * @arg TIMER_CHANNEL_2: TIMER Channel 2 selected - * @arg TIMER_CHANNEL_3: TIMER Channel 3 selected - * @arg TIMER_CHANNEL_4: TIMER Channel 4 selected - * @retval None - */ -void ald_timer_oc_stop_by_it(timer_handle_t *hperh, timer_channel_t ch) -{ - assert_param(IS_TIMER_CCX_INSTANCE(hperh->perh, ch)); - - switch (ch) { - case TIMER_CHANNEL_1: - ald_timer_interrupt_config(hperh, TIMER_IT_CC1, DISABLE); - break; - - case TIMER_CHANNEL_2: - ald_timer_interrupt_config(hperh, TIMER_IT_CC2, DISABLE); - break; - - case TIMER_CHANNEL_3: - ald_timer_interrupt_config(hperh, TIMER_IT_CC3, DISABLE); - break; - - case TIMER_CHANNEL_4: - ald_timer_interrupt_config(hperh, TIMER_IT_CC4, DISABLE); - break; - - default: - break; - } - - timer_ccx_channel_cmd(hperh->perh, ch, DISABLE); - - if (IS_TIMER_BREAK_INSTANCE(hperh->perh) != RESET) - TIMER_MOE_DISABLE(hperh); - - TIMER_DISABLE(hperh); - hperh->state = TIMER_STATE_READY; - return; -} - - - - - -#ifdef ALD_DMA -/** - * @brief Starts the TIMER Output Compare signal generation in DMA mode. - * @param hperh: TIMER handle - * @param ch: TIMER Channels to be enabled - * This parameter can be one of the following values: - * @arg TIMER_CHANNEL_1: TIMER Channel 1 selected - * @arg TIMER_CHANNEL_2: TIMER Channel 2 selected - * @arg TIMER_CHANNEL_3: TIMER Channel 3 selected - * @arg TIMER_CHANNEL_4: TIMER Channel 4 selected - * @param buf: The source Buffer address. - * @param len: The length of buffer to be transferred from memory to TIMER peripheral - * @param dma_ch: Channel of DMA. - * @retval Status, see @ref ald_status_t. - */ -ald_status_t ald_timer_oc_start_by_dma(timer_handle_t *hperh, timer_channel_t ch, - uint16_t *buf, uint32_t len, uint8_t dma_ch) -{ - assert_param(IS_TIMER_CCX_INSTANCE(hperh->perh, ch)); - - if ((hperh->state == TIMER_STATE_BUSY)) - return BUSY; - if ((hperh->state == TIMER_STATE_READY)) { - if (((uint32_t)buf == 0 ) || (len == 0)) - return ERROR; - } - - hperh->state = TIMER_STATE_BUSY; - - if (hperh->hdma1.perh == NULL) - hperh->hdma1.perh = DMA0; - - hperh->hdma1.cplt_cbk = timer_dma_oc_cplt; - hperh->hdma1.cplt_arg = (void *)hperh; - hperh->hdma1.err_cbk = timer_dma_error; - hperh->hdma1.err_arg = (void *)hperh; - - ald_dma_config_struct(&hperh->hdma1.config); - hperh->hdma1.config.src = (void *)buf; - hperh->hdma1.config.size = len; - hperh->hdma1.config.data_width = DMA_DATA_SIZE_HALFWORD; - hperh->hdma1.config.src_inc = DMA_DATA_INC_HALFWORD; - hperh->hdma1.config.dst_inc = DMA_DATA_INC_NONE; - hperh->hdma1.config.channel = dma_ch; - - - timer_dma_msel(hperh->perh, &hperh->hdma1.config); - - switch (ch) { - case TIMER_CHANNEL_1: - hperh->hdma1.config.dst = (void *)&hperh->perh->CCVAL1; - hperh->hdma1.config.msigsel = DMA_MSIGSEL_TIMER_CH1; - ald_dma_config_basic(&hperh->hdma1); - ald_timer_dma_req_config(hperh, TIMER_DMA_CC1, ENABLE); - hperh->ch = TIMER_ACTIVE_CHANNEL_1; - break; - - case TIMER_CHANNEL_2: - hperh->hdma1.config.dst = (void *)&hperh->perh->CCVAL2; - hperh->hdma1.config.msigsel = DMA_MSIGSEL_TIMER_CH2; - ald_dma_config_basic(&hperh->hdma1); - ald_timer_dma_req_config(hperh, TIMER_DMA_CC2, ENABLE); - hperh->ch = TIMER_ACTIVE_CHANNEL_2; - break; - - case TIMER_CHANNEL_3: - hperh->hdma1.config.dst = (void *)&hperh->perh->CCVAL3; - hperh->hdma1.config.msigsel = DMA_MSIGSEL_TIMER_CH3; - ald_dma_config_basic(&hperh->hdma1); - ald_timer_dma_req_config(hperh, TIMER_DMA_CC3, ENABLE); - hperh->ch = TIMER_ACTIVE_CHANNEL_3; - break; - - case TIMER_CHANNEL_4: - hperh->hdma1.config.dst = (void *)&hperh->perh->CCVAL4; - hperh->hdma1.config.msigsel = DMA_MSIGSEL_TIMER_CH4; - ald_dma_config_basic(&hperh->hdma1); - ald_timer_dma_req_config(hperh, TIMER_DMA_CC4, ENABLE); - hperh->ch = TIMER_ACTIVE_CHANNEL_4; - break; - - default: - break; - } - - timer_ccx_channel_cmd(hperh->perh, ch, ENABLE); - - if (IS_TIMER_BREAK_INSTANCE(hperh->perh) != RESET) - TIMER_MOE_ENABLE(hperh); - - TIMER_ENABLE(hperh); - return OK; -} - -/** - * @brief Stops the TIMER Output Compare signal generation in DMA mode. - * @param hperh: TIMER handle - * @param ch: TIMER Channels to be disabled - * This parameter can be one of the following values: - * @arg TIMER_CHANNEL_1: TIMER Channel 1 selected - * @arg TIMER_CHANNEL_2: TIMER Channel 2 selected - * @arg TIMER_CHANNEL_3: TIMER Channel 3 selected - * @arg TIMER_CHANNEL_4: TIMER Channel 4 selected - * @retval None -*/ -void ald_timer_oc_stop_by_dma(timer_handle_t *hperh, timer_channel_t ch) -{ - assert_param(IS_TIMER_CCX_INSTANCE(hperh->perh, ch)); - - switch (ch) { - case TIMER_CHANNEL_1: - ald_timer_dma_req_config(hperh, TIMER_DMA_CC1, DISABLE); - break; - - case TIMER_CHANNEL_2: - ald_timer_dma_req_config(hperh, TIMER_DMA_CC2, DISABLE); - break; - - case TIMER_CHANNEL_3: - ald_timer_dma_req_config(hperh, TIMER_DMA_CC3, DISABLE); - break; - - case TIMER_CHANNEL_4: - ald_timer_dma_req_config(hperh, TIMER_DMA_CC4, DISABLE); - break; - - default: - break; - } - - timer_ccx_channel_cmd(hperh->perh, ch, DISABLE); - - if (IS_TIMER_BREAK_INSTANCE(hperh->perh) != RESET) - TIMER_MOE_DISABLE(hperh); - - TIMER_DISABLE(hperh); - hperh->state = TIMER_STATE_READY; - return; -} -#endif -/** - * @} - */ - -/** @defgroup TIMER_Public_Functions_Group3 TIMER PWM functions - * @brief TIMER PWM functions - * - * @verbatim - ============================================================================== - ##### Time PWM functions ##### - ============================================================================== - [..] - This section provides functions allowing to: - (+) Initialize and configure the TIMER PWM. - (+) Start the Time PWM. - (+) Stop the Time PWM. - (+) Start the Time PWM and enable interrupt. - (+) Stop the Time PWM and disable interrupt. - (+) Start the Time PWM and enable DMA transfer. - (+) Stop the Time PWM and disable DMA transfer. - - @endverbatim - * @{ - */ -/** - * @brief Initializes the TIMER PWM Time Base according to the specified - * parameters in the timer_handle_t and create the associated handle. - * @param hperh: TIMER handle - * @retval Status, see @ref ald_status_t. - */ -ald_status_t ald_timer_pwm_init(timer_handle_t *hperh) -{ - return ald_timer_base_init(hperh); -} - -/** - * @brief Starts the PWM signal generation. - * @param hperh: TIMER handle - * @param ch: TIMER Channels to be enabled - * This parameter can be one of the following values: - * @arg TIMER_CHANNEL_1: TIMER Channel 1 selected - * @arg TIMER_CHANNEL_2: TIMER Channel 2 selected - * @arg TIMER_CHANNEL_3: TIMER Channel 3 selected - * @arg TIMER_CHANNEL_4: TIMER Channel 4 selected - * @retval None - */ -void ald_timer_pwm_start(timer_handle_t *hperh, timer_channel_t ch) -{ - ald_timer_oc_start(hperh, ch); - return; -} - -/** - * @brief Stops the PWM signal generation. - * @param hperh: TIMER handle - * @param ch: TIMER Channels to be disabled - * This parameter can be one of the following values: - * @arg TIMER_CHANNEL_1: TIMER Channel 1 selected - * @arg TIMER_CHANNEL_2: TIMER Channel 2 selected - * @arg TIMER_CHANNEL_3: TIMER Channel 3 selected - * @arg TIMER_CHANNEL_4: TIMER Channel 4 selected - * @retval None - */ -void ald_timer_pwm_stop(timer_handle_t *hperh, timer_channel_t ch) -{ - ald_timer_oc_stop(hperh, ch); - return; -} - -/** - * @brief Starts the PWM signal generation in interrupt mode. - * @param hperh: TIMER handle - * @param ch: TIMER Channel to be disabled - * This parameter can be one of the following values: - * @arg TIMER_CHANNEL_1: TIMER Channel 1 selected - * @arg TIMER_CHANNEL_2: TIMER Channel 2 selected - * @arg TIMER_CHANNEL_3: TIMER Channel 3 selected - * @arg TIMER_CHANNEL_4: TIMER Channel 4 selected - * @retval None - */ -void ald_timer_pwm_start_by_it(timer_handle_t *hperh, timer_channel_t ch) -{ - ald_timer_oc_start_by_it(hperh, ch); - return; -} - -/** - * @brief Stops the PWM signal generation in interrupt mode. - * @param hperh: TIMER handle - * @param ch: TIMER Channels to be disabled - * This parameter can be one of the following values: - * @arg TIMER_CHANNEL_1: TIMER Channel 1 selected - * @arg TIMER_CHANNEL_2: TIMER Channel 2 selected - * @arg TIMER_CHANNEL_3: TIMER Channel 3 selected - * @arg TIMER_CHANNEL_4: TIMER Channel 4 selected - * @retval None - */ -void ald_timer_pwm_stop_by_it(timer_handle_t *hperh, timer_channel_t ch) -{ - ald_timer_oc_stop_by_it(hperh, ch); - return; -} - -#ifdef ALD_DMA -/** - * @brief Starts the TIMER PWM signal generation in DMA mode. - * @param hperh: TIMER handle - * @param ch: TIMER Channels to be enabled - * This parameter can be one of the following values: - * @arg TIMER_CHANNEL_1: TIMER Channel 1 selected - * @arg TIMER_CHANNEL_2: TIMER Channel 2 selected - * @arg TIMER_CHANNEL_3: TIMER Channel 3 selected - * @arg TIMER_CHANNEL_4: TIMER Channel 4 selected - * @param buf: The source Buffer address. - * @param len: The length of buffer to be transferred from memory to TIMER peripheral - * @param dma_ch: Channel of DMA. - * @retval Status, see @ref ald_status_t. - */ -ald_status_t ald_timer_pwm_start_by_dma(timer_handle_t *hperh, timer_channel_t ch, - uint16_t *buf, uint32_t len, uint8_t dma_ch) -{ - return ald_timer_oc_start_by_dma(hperh, ch, buf, len, dma_ch); -} - -/** - * @brief Stops the TIMER PWM signal generation in DMA mode. - * @param hperh: TIMER handle - * @param ch: TIMER Channels to be disabled - * This parameter can be one of the following values: - * @arg TIMER_CHANNEL_1: TIMER Channel 1 selected - * @arg TIMER_CHANNEL_2: TIMER Channel 2 selected - * @arg TIMER_CHANNEL_3: TIMER Channel 3 selected - * @arg TIMER_CHANNEL_4: TIMER Channel 4 selected - * @retval None - */ -void ald_timer_pwm_stop_by_dma(timer_handle_t *hperh, timer_channel_t ch) -{ - ald_timer_oc_stop_by_dma(hperh, ch); - return; -} -#endif -/** - * @brief Set the PWM freq. - * @param hperh: TIMER handle - * @param freq: PWM freq to set - * @retval None - */ -void ald_timer_pwm_set_freq(timer_handle_t *hperh, uint16_t freq) -{ - uint32_t _arr; - - if (freq == 0) - return; - - _arr = ald_cmu_get_pclk1_clock() / (hperh->init.prescaler + 1) / freq - 1; - WRITE_REG(hperh->perh->AR, _arr); - hperh->init.period = _arr; -} - -/** - * @brief Set the PWM duty. - * @param hperh: TIMER handle - * @param ch: TIMER Channels to be enabled - * This parameter can be one of the following values: - * @arg TIMER_CHANNEL_1: TIMER Channel 1 selected - * @arg TIMER_CHANNEL_2: TIMER Channel 2 selected - * @arg TIMER_CHANNEL_3: TIMER Channel 3 selected - * @arg TIMER_CHANNEL_4: TIMER Channel 4 selected - * @param duty: PWM duty to set - * @retval None - */ -void ald_timer_pwm_set_duty(timer_handle_t *hperh, timer_channel_t ch, uint16_t duty) -{ - uint32_t tmp = (hperh->init.period + 1) * duty / 100 - 1; - - if (ch == TIMER_CHANNEL_1) - WRITE_REG(hperh->perh->CCVAL1, tmp); - else if (ch == TIMER_CHANNEL_2) - WRITE_REG(hperh->perh->CCVAL2, tmp); - else if (ch == TIMER_CHANNEL_3) - WRITE_REG(hperh->perh->CCVAL3, tmp); - else if (ch == TIMER_CHANNEL_4) - WRITE_REG(hperh->perh->CCVAL4, tmp); - else { - ;/* do nothing */ - } -} - -/** - * @brief Set capture the PWM. - * @param hperh: TIMER handle - * @param ch: TIMER Channels to be captured the PWM - * This parameter can be one of the following values: - * @arg TIMER_CHANNEL_1: TIMER Channel 1 selected - * @arg TIMER_CHANNEL_2: TIMER Channel 2 selected - * @retval None - */ -void ald_timer_pwm_set_input(timer_handle_t *hperh, timer_channel_t ch) -{ - assert_param(IS_TIMER_PWM_INPUT_INSTANCE(hperh->perh, ch)); - - CLEAR_BIT(hperh->perh->SMCON, TIMER_SMCON_SMODS_MSK); - switch (ch) { - case TIMER_CHANNEL_1: - MODIFY_REG(hperh->perh->CHMR1, TIMER_CHMR1_CC1SSEL_MSK, TIMER_IC_SEL_DIRECT << TIMER_CHMR1_CC1SSEL_POSS); - MODIFY_REG(hperh->perh->CHMR1, TIMER_CHMR1_CC2SSEL_MSK, TIMER_IC_SEL_INDIRECT << TIMER_CHMR1_CC2SSEL_POSS); - MODIFY_REG(hperh->perh->CCEP, TIMER_CCEP_CC1POL_MSK, TIMER_IC_POLARITY_RISE << TIMER_CCEP_CC1POL_POS); - MODIFY_REG(hperh->perh->CCEP, TIMER_CCEP_CC1NPOL_MSK, TIMER_IC_POLARITY_RISE << TIMER_CCEP_CC1NPOL_POS); - MODIFY_REG(hperh->perh->CCEP, TIMER_CCEP_CC2POL_MSK, TIMER_IC_POLARITY_FALL << TIMER_CCEP_CC2POL_POS); - MODIFY_REG(hperh->perh->CCEP, TIMER_CCEP_CC2NPOL_MSK, TIMER_IC_POLARITY_FALL << TIMER_CCEP_CC2NPOL_POS); - MODIFY_REG(hperh->perh->SMCON, TIMER_SMCON_TSSEL_MSK, TIMER_TS_TI1FP1 << TIMER_SMCON_TSSEL_POSS); - MODIFY_REG(hperh->perh->SMCON, TIMER_SMCON_SMODS_MSK, TIMER_MODE_RESET << TIMER_SMCON_SMODS_POSS); - break; - case TIMER_CHANNEL_2: - MODIFY_REG(hperh->perh->CHMR1, TIMER_CHMR1_CC1SSEL_MSK, TIMER_IC_SEL_INDIRECT << TIMER_CHMR1_CC1SSEL_POSS); - MODIFY_REG(hperh->perh->CHMR1, TIMER_CHMR1_CC2SSEL_MSK, TIMER_IC_SEL_DIRECT << TIMER_CHMR1_CC2SSEL_POSS); - MODIFY_REG(hperh->perh->CCEP, TIMER_CCEP_CC1POL_MSK, TIMER_IC_POLARITY_RISE << TIMER_CCEP_CC1POL_POS); - MODIFY_REG(hperh->perh->CCEP, TIMER_CCEP_CC1NPOL_MSK, TIMER_IC_POLARITY_FALL << TIMER_CCEP_CC1NPOL_POS); - MODIFY_REG(hperh->perh->CCEP, TIMER_CCEP_CC2POL_MSK, TIMER_IC_POLARITY_FALL << TIMER_CCEP_CC2POL_POS); - MODIFY_REG(hperh->perh->CCEP, TIMER_CCEP_CC2NPOL_MSK, TIMER_IC_POLARITY_RISE << TIMER_CCEP_CC2NPOL_POS); - MODIFY_REG(hperh->perh->SMCON, TIMER_SMCON_TSSEL_MSK, TIMER_TS_TI2FP2 << TIMER_SMCON_TSSEL_POSS); - MODIFY_REG(hperh->perh->SMCON, TIMER_SMCON_SMODS_MSK, TIMER_MODE_RESET << TIMER_SMCON_SMODS_POSS); - break; - default: - break; - } - - SET_BIT(hperh->perh->CCEP, TIMER_CCEP_CC1EN_MSK); - SET_BIT(hperh->perh->CCEP, TIMER_CCEP_CC2EN_MSK); - - return; -} -/** - * @} - */ - -/** @defgroup TIMER_Public_Functions_Group4 TIMER Input Capture functions - * @brief Time Input Capture functions - * - * @verbatim - ============================================================================== - ##### Time Input Capture functions ##### - ============================================================================== - [..] - This section provides functions allowing to: - (+) Initialize and configure the TIMER Input Capture. - (+) Start the Time Input Capture. - (+) Stop the Time Input Capture. - (+) Start the Time Input Capture and enable interrupt. - (+) Stop the Time Input Capture and disable interrupt. - (+) Start the Time Input Capture and enable DMA transfer. - (+) Stop the Time Input Capture and disable DMA transfer. - - * @endverbatim - * @{ - */ -/** - * @brief Initializes the TIMER Input Capture Time base according to the specified - * parameters in the timer_handle_t and create the associated handle. - * @param hperh: TIMER handle - * @retval Status, see @ref ald_status_t. - */ -ald_status_t ald_timer_ic_init(timer_handle_t *hperh) -{ - return ald_timer_base_init(hperh); -} - -/** - * @brief Starts the TIMER Input Capture measurement. - * @param hperh: TIMER handle - * @param ch: TIMER Channels to be enabled - * This parameter can be one of the following values: - * @arg TIMER_CHANNEL_1: TIMER Channel 1 selected - * @arg TIMER_CHANNEL_2: TIMER Channel 2 selected - * @arg TIMER_CHANNEL_3: TIMER Channel 3 selected - * @arg TIMER_CHANNEL_4: TIMER Channel 4 selected - * @retval None - */ -void ald_timer_ic_start(timer_handle_t *hperh, timer_channel_t ch) -{ - assert_param(IS_TIMER_CCX_INSTANCE(hperh->perh, ch)); - - timer_ccx_channel_cmd(hperh->perh, ch, ENABLE); - TIMER_ENABLE(hperh); - return; -} - -/** - * @brief Stops the TIMER Input Capture measurement. - * @param hperh: TIMER handle - * @param ch: TIMER Channels to be disabled - * This parameter can be one of the following values: - * @arg TIMER_CHANNEL_1: TIMER Channel 1 selected - * @arg TIMER_CHANNEL_2: TIMER Channel 2 selected - * @arg TIMER_CHANNEL_3: TIMER Channel 3 selected - * @arg TIMER_CHANNEL_4: TIMER Channel 4 selected - * @retval None - */ -void ald_timer_ic_stop(timer_handle_t *hperh, timer_channel_t ch) -{ - assert_param(IS_TIMER_CCX_INSTANCE(hperh->perh, ch)); - - timer_ccx_channel_cmd(hperh->perh, ch, DISABLE); - TIMER_DISABLE(hperh); - return; -} - -/** - * @brief Starts the TIMER Input Capture measurement in interrupt mode. - * @param hperh: TIMER handle - * @param ch: TIMER Channels to be enabled - * This parameter can be one of the following values: - * @arg TIMER_CHANNEL_1: TIMER Channel 1 selected - * @arg TIMER_CHANNEL_2: TIMER Channel 2 selected - * @arg TIMER_CHANNEL_3: TIMER Channel 3 selected - * @arg TIMER_CHANNEL_4: TIMER Channel 4 selected - * @retval None - */ -void ald_timer_ic_start_by_it(timer_handle_t *hperh, timer_channel_t ch) -{ - assert_param(IS_TIMER_CCX_INSTANCE(hperh->perh, ch)); - - switch (ch) { - case TIMER_CHANNEL_1: - ald_timer_interrupt_config(hperh, TIMER_IT_CC1, ENABLE); - break; - case TIMER_CHANNEL_2: - ald_timer_interrupt_config(hperh, TIMER_IT_CC2, ENABLE); - break; - case TIMER_CHANNEL_3: - ald_timer_interrupt_config(hperh, TIMER_IT_CC3, ENABLE); - break; - case TIMER_CHANNEL_4: - ald_timer_interrupt_config(hperh, TIMER_IT_CC4, ENABLE); - break; - default: - break; - } - - timer_ccx_channel_cmd(hperh->perh, ch, ENABLE); - TIMER_ENABLE(hperh); - return; -} - -/** - * @brief Stops the TIMER Input Capture measurement in interrupt mode. - * @param hperh: TIMER handle - * @param ch: TIMER Channels to be disabled - * This parameter can be one of the following values: - * @arg TIMER_CHANNEL_1: TIMER Channel 1 selected - * @arg TIMER_CHANNEL_2: TIMER Channel 2 selected - * @arg TIMER_CHANNEL_3: TIMER Channel 3 selected - * @arg TIMER_CHANNEL_4: TIMER Channel 4 selected - * @retval None - */ -void ald_timer_ic_stop_by_it(timer_handle_t *hperh, timer_channel_t ch) -{ - assert_param(IS_TIMER_CCX_INSTANCE(hperh->perh, ch)); - - switch (ch) { - case TIMER_CHANNEL_1: - ald_timer_interrupt_config(hperh, TIMER_IT_CC1, DISABLE); - break; - case TIMER_CHANNEL_2: - ald_timer_interrupt_config(hperh, TIMER_IT_CC2, DISABLE); - break; - case TIMER_CHANNEL_3: - ald_timer_interrupt_config(hperh, TIMER_IT_CC3, DISABLE); - break; - case TIMER_CHANNEL_4: - ald_timer_interrupt_config(hperh, TIMER_IT_CC4, DISABLE); - break; - default: - break; - } - - timer_ccx_channel_cmd(hperh->perh, ch, DISABLE); - TIMER_DISABLE(hperh); - return; -} - -#ifdef ALD_DMA -/** - * @brief Starts the TIMER Input Capture measurement in DMA mode. - * @param hperh: TIMER handle - * @param ch: TIMER Channels to be enabled - * This parameter can be one of the following values: - * @arg TIMER_CHANNEL_1: TIMER Channel 1 selected - * @arg TIMER_CHANNEL_2: TIMER Channel 2 selected - * @arg TIMER_CHANNEL_3: TIMER Channel 3 selected - * @arg TIMER_CHANNEL_4: TIMER Channel 4 selected - * @param buf: The destination Buffer address. - * @param len: The length of buffer to be transferred TIMER peripheral to memory - * @param dma_ch: Channel of DMA. - * @retval Status, see @ref ald_status_t. - */ -ald_status_t ald_timer_ic_start_by_dma(timer_handle_t *hperh, timer_channel_t ch, - uint16_t *buf, uint32_t len, uint8_t dma_ch) -{ - assert_param(IS_TIMER_CCX_INSTANCE(hperh->perh, ch)); - - if ((hperh->state == TIMER_STATE_BUSY)) - return BUSY; - if ((hperh->state == TIMER_STATE_READY)) { - if (((uint32_t)buf == 0 ) || (len == 0)) - return ERROR; - } - - hperh->state = TIMER_STATE_BUSY; - - if (hperh->hdma1.perh == NULL) - hperh->hdma1.perh = DMA0; - - hperh->hdma1.cplt_cbk = timer_dma_capture_cplt; - hperh->hdma1.cplt_arg = (void *)hperh; - hperh->hdma1.err_cbk = timer_dma_error; - hperh->hdma1.err_arg = (void *)hperh; - - ald_dma_config_struct(&hperh->hdma1.config); - hperh->hdma1.config.dst = (void *)buf; - hperh->hdma1.config.size = len; - hperh->hdma1.config.data_width = DMA_DATA_SIZE_HALFWORD; - hperh->hdma1.config.src_inc = DMA_DATA_INC_NONE; - hperh->hdma1.config.dst_inc = DMA_DATA_INC_HALFWORD; - hperh->hdma1.config.channel = dma_ch; - - timer_dma_msel(hperh->perh, &hperh->hdma1.config); - - switch (ch) { - case TIMER_CHANNEL_1: - hperh->hdma1.config.src = (void *)&hperh->perh->CCVAL1; - hperh->hdma1.config.msigsel = DMA_MSIGSEL_TIMER_CH1; - ald_dma_config_basic(&hperh->hdma1); - ald_timer_dma_req_config(hperh, TIMER_DMA_CC1, ENABLE); - hperh->ch = TIMER_ACTIVE_CHANNEL_1; - break; - - case TIMER_CHANNEL_2: - hperh->hdma1.config.src = (void *)&hperh->perh->CCVAL2; - hperh->hdma1.config.msigsel = DMA_MSIGSEL_TIMER_CH2; - ald_dma_config_basic(&hperh->hdma1); - ald_timer_dma_req_config(hperh, TIMER_DMA_CC2, ENABLE); - hperh->ch = TIMER_ACTIVE_CHANNEL_2; - break; - - case TIMER_CHANNEL_3: - hperh->hdma1.config.src = (void *)&hperh->perh->CCVAL3; - hperh->hdma1.config.msigsel = DMA_MSIGSEL_TIMER_CH3; - ald_dma_config_basic(&hperh->hdma1); - ald_timer_dma_req_config(hperh, TIMER_DMA_CC3, ENABLE); - hperh->ch = TIMER_ACTIVE_CHANNEL_3; - break; - - case TIMER_CHANNEL_4: - hperh->hdma1.config.src = (void *)&hperh->perh->CCVAL4; - hperh->hdma1.config.msigsel = DMA_MSIGSEL_TIMER_CH4; - ald_dma_config_basic(&hperh->hdma1); - ald_timer_dma_req_config(hperh, TIMER_DMA_CC4, ENABLE); - hperh->ch = TIMER_ACTIVE_CHANNEL_4; - break; - - default: - break; - } - - timer_ccx_channel_cmd(hperh->perh, ch, ENABLE); - TIMER_ENABLE(hperh); - return OK; -} - -/** - * @brief Stops the TIMER Input Capture measurement in DMA mode. - * @param hperh: TIMER handle - * @param ch: TIMER Channels to be disabled - * This parameter can be one of the following values: - * @arg TIMER_CHANNEL_1: TIMER Channel 1 selected - * @arg TIMER_CHANNEL_2: TIMER Channel 2 selected - * @arg TIMER_CHANNEL_3: TIMER Channel 3 selected - * @arg TIMER_CHANNEL_4: TIMER Channel 4 selected - * @retval None - */ -void ald_timer_ic_stop_by_dma(timer_handle_t *hperh, timer_channel_t ch) -{ - assert_param(IS_TIMER_CCX_INSTANCE(hperh->perh, ch)); - - switch (ch) { - case TIMER_CHANNEL_1: - ald_timer_dma_req_config(hperh, TIMER_DMA_CC1, DISABLE); - break; - case TIMER_CHANNEL_2: - ald_timer_dma_req_config(hperh, TIMER_DMA_CC2, DISABLE); - break; - case TIMER_CHANNEL_3: - ald_timer_dma_req_config(hperh, TIMER_DMA_CC3, DISABLE); - break; - case TIMER_CHANNEL_4: - ald_timer_dma_req_config(hperh, TIMER_DMA_CC4, DISABLE); - break; - default: - break; - } - - timer_ccx_channel_cmd(hperh->perh, ch, DISABLE); - TIMER_DISABLE(hperh); - hperh->state = TIMER_STATE_READY; - return; -} -#endif -/** - * @} - */ - -/** @defgroup TIMER_Public_Functions_Group5 TIMER One Pulse functions - * @brief Time One Pulse functions - * - * @verbatim - ============================================================================== - ##### Time One Pulse functions ##### - ============================================================================== - [..] - This section provides functions allowing to: - (+) Initialize and configure the TIMER One Pulse. - (+) Start the Time One Pulse. - (+) Stop the Time One Pulse. - (+) Start the Time One Pulse and enable interrupt. - (+) Stop the Time One Pulse and disable interrupt. - (+) Start the Time One Pulse and enable DMA transfer. - (+) Stop the Time One Pulse and disable DMA transfer. - - * @endverbatim - * @{ - */ -/** - * @brief Initializes the TIMER One Pulse Time Base according to the specified - * parameters in the timer_handle_t and create the associated handle. - * @param hperh: TIMER handle - * @param mode: Select the One pulse mode. - * This parameter can be one of the following values: - * @arg TIMER_OP_MODE_SINGLE: Only one pulse will be generated. - * @arg TIMER_OP_MODE_REPEAT: Repetitive pulses wil be generated. - * @retval Status, see @ref ald_status_t. - */ -ald_status_t ald_timer_one_pulse_init(timer_handle_t *hperh, timer_op_mode_t mode) -{ - if (hperh == NULL) - return ERROR; - - assert_param(IS_TIMER_INSTANCE(hperh->perh)); - assert_param(IS_TIMER_COUNTER_MODE(hperh->init.mode)); - assert_param(IS_TIMER_CLOCK_DIVISION(hperh->init.clk_div)); - assert_param(IS_TIMER_OP_MODE(mode)); - - if (hperh->state == TIMER_STATE_RESET) - hperh->lock = UNLOCK; - - hperh->state = TIMER_STATE_BUSY; - timer_base_set_config(hperh->perh, &hperh->init); - MODIFY_REG(hperh->perh->CON1, TIMER_CON1_SPMEN_MSK, mode << TIMER_CON1_SPMEN_POS); - hperh->state = TIMER_STATE_READY; - - return OK; -} - -/** - * @brief Starts the TIMER One Pulse signal generation. - * @param hperh: TIMER One Pulse handle - * @param ch: TIMER Channels to be enabled - * This parameter can be one of the following values: - * @arg TIMER_OP_OUTPUT_CHANNEL_1: TIMER Channel 1 selected - * @arg TIMER_OP_OUTPUT_CHANNEL_2: TIMER Channel 2 selected - * @retval None - */ -void ald_timer_one_pulse_start(timer_handle_t *hperh, timer_op_output_channel_t ch) -{ - /* Enable the Capture compare and the Input Capture channels - * (in the OPM Mode the two possible channels that can be used are TIMER_CHANNEL_1 and TIMER_CHANNEL_2) - * if TIMER_CHANNEL_1 is used as output, the TIMER_CHANNEL_2 will be used as input and - * if TIMER_CHANNEL_1 is used as input, the TIMER_CHANNEL_2 will be used as output - * in all combinations, the TIMER_CHANNEL_1 and TIMER_CHANNEL_2 should be enabled together - */ - timer_ccx_channel_cmd(hperh->perh, TIMER_CHANNEL_1, ENABLE); - timer_ccx_channel_cmd(hperh->perh, TIMER_CHANNEL_2, ENABLE); - - if (IS_TIMER_BREAK_INSTANCE(hperh->perh) != RESET) - TIMER_MOE_ENABLE(hperh); - - return; -} - -/** - * @brief Stops the TIMER One Pulse signal generation. - * @param hperh: TIMER handle - * @param ch: TIMER Channels to be enabled - * This parameter can be one of the following values: - * @arg TIMER_OP_OUTPUT_CHANNEL_1: TIMER Channel 1 selected - * @arg TIMER_OP_OUTPUT_CHANNEL_2: TIMER Channel 2 selected - * @retval None - */ -void ald_timer_one_pulse_stop(timer_handle_t *hperh, timer_op_output_channel_t ch) -{ - timer_ccx_channel_cmd(hperh->perh, TIMER_CHANNEL_1, DISABLE); - timer_ccx_channel_cmd(hperh->perh, TIMER_CHANNEL_2, DISABLE); - - if (IS_TIMER_BREAK_INSTANCE(hperh->perh) != RESET) - TIMER_MOE_DISABLE(hperh); - - TIMER_DISABLE(hperh); - return; -} - -/** - * @brief Starts the TIMER One Pulse signal generation in interrupt mode. - * @param hperh: TIMER handle - * @param ch: TIMER Channels to be enabled - * This parameter can be one of the following values: - * @arg TIMER_OP_OUTPUT_CHANNEL_1: TIMER Channel 1 selected - * @arg TIMER_OP_OUTPUT_CHANNEL_2: TIMER Channel 2 selected - * @retval None - */ -void ald_timer_one_pulse_start_by_it(timer_handle_t *hperh, timer_op_output_channel_t ch) -{ - /* Enable the Capture compare and the Input Capture channels - * (in the OPM Mode the two possible channels that can be used are TIMER_CHANNEL_1 and TIMER_CHANNEL_2) - * if TIMER_CHANNEL_1 is used as output, the TIMER_CHANNEL_2 will be used as input and - * if TIMER_CHANNEL_1 is used as input, the TIMER_CHANNEL_2 will be used as output - * in all combinations, the TIMER_CHANNEL_1 and TIMER_CHANNEL_2 should be enabled together - */ - ald_timer_interrupt_config(hperh, TIMER_IT_CC1, ENABLE); - ald_timer_interrupt_config(hperh, TIMER_IT_CC2, ENABLE); - timer_ccx_channel_cmd(hperh->perh, TIMER_CHANNEL_1, ENABLE); - timer_ccx_channel_cmd(hperh->perh, TIMER_CHANNEL_2, ENABLE); - - if (IS_TIMER_BREAK_INSTANCE(hperh->perh) != RESET) - TIMER_MOE_ENABLE(hperh); - - return; -} - -/** - * @brief Stops the TIMER One Pulse signal generation in interrupt mode. - * @param hperh : TIMER handle - * @param ch: TIMER Channels to be enabled - * This parameter can be one of the following values: - * @arg TIMER_OP_OUTPUT_CHANNEL_1: TIMER Channel 1 selected - * @arg TIMER_OP_OUTPUT_CHANNEL_2: TIMER Channel 2 selected - * @retval None - */ -void ald_timer_one_pulse_stop_by_it(timer_handle_t *hperh, timer_op_output_channel_t ch) -{ - ald_timer_interrupt_config(hperh, TIMER_IT_CC1, DISABLE); - ald_timer_interrupt_config(hperh, TIMER_IT_CC2, DISABLE); - timer_ccx_channel_cmd(hperh->perh, TIMER_CHANNEL_1, DISABLE); - timer_ccx_channel_cmd(hperh->perh, TIMER_CHANNEL_2, DISABLE); - - if (IS_TIMER_BREAK_INSTANCE(hperh->perh) != RESET) - TIMER_MOE_DISABLE(hperh); - - TIMER_DISABLE(hperh); - return; -} -/** - * @} - */ - -/** @defgroup TIMER_Public_Functions_Group6 TIMER Encoder functions - * @brief TIMER Encoder functions - * - * @verbatim - ============================================================================== - ##### Time Encoder functions ##### - ============================================================================== - [..] - This section provides functions allowing to: - (+) Initialize and configure the TIMER Encoder. - (+) Start the Time Encoder. - (+) Stop the Time Encoder. - (+) Start the Time Encoder and enable interrupt. - (+) Stop the Time Encoder and disable interrupt. - (+) Start the Time Encoder and enable DMA transfer. - (+) Stop the Time Encoder and disable DMA transfer. - - * @endverbatim - * @{ - */ -/** - * @brief Initializes the TIMER Encoder Interface and create the associated handle. - * @param hperh: TIMER handle - * @param config: TIMER Encoder Interface configuration structure - * @retval Status, see @ref ald_status_t. - */ -ald_status_t ald_timer_encoder_init(timer_handle_t *hperh, timer_encoder_init_t *config) -{ - if (hperh == NULL) - return ERROR; - - assert_param(IS_TIMER_CC2_INSTANCE(hperh->perh)); - assert_param(IS_TIMER_ENCODER_MODE(config->mode)); - assert_param(IS_TIMER_IC_POLARITY(config->ic1_polarity)); - assert_param(IS_TIMER_IC_POLARITY(config->ic2_polarity)); - assert_param(IS_TIMER_IC_SELECT(config->ic1_sel)); - assert_param(IS_TIMER_IC_SELECT(config->ic2_sel)); - assert_param(IS_TIMER_IC_PSC(config->ic1_psc)); - assert_param(IS_TIMER_IC_PSC(config->ic2_psc)); - assert_param(IS_TIMER_IC_FILTER(config->ic1_filter)); - assert_param(IS_TIMER_IC_FILTER(config->ic2_filter)); - - if (hperh->state == TIMER_STATE_RESET) - hperh->lock = UNLOCK; - - hperh->state = TIMER_STATE_BUSY; - CLEAR_BIT(hperh->perh->SMCON, TIMER_SMCON_SMODS_MSK); - timer_base_set_config(hperh->perh, &hperh->init); - - MODIFY_REG(hperh->perh->SMCON, TIMER_SMCON_SMODS_MSK, config->mode << TIMER_SMCON_SMODS_POSS); - MODIFY_REG(hperh->perh->CHMR1, TIMER_CHMR1_CC1SSEL_MSK, config->ic1_sel << TIMER_CHMR1_CC1SSEL_POSS); - MODIFY_REG(hperh->perh->CHMR1, TIMER_CHMR1_CC2SSEL_MSK, config->ic2_sel << TIMER_CHMR1_CC2SSEL_POSS); - MODIFY_REG(hperh->perh->CHMR1, TIMER_CHMR1_IC1PRES_MSK, config->ic1_psc << TIMER_CHMR1_IC1PRES_POSS); - MODIFY_REG(hperh->perh->CHMR1, TIMER_CHMR1_IC2PRES_MSK, config->ic2_psc << TIMER_CHMR1_IC2PRES_POSS); - MODIFY_REG(hperh->perh->CHMR1, TIMER_CHMR1_I1FLT_MSK, config->ic1_filter << TIMER_CHMR1_I1FLT_POSS); - MODIFY_REG(hperh->perh->CHMR1, TIMER_CHMR1_I2FLT_MSK, config->ic2_filter << TIMER_CHMR1_I2FLT_POSS); - MODIFY_REG(hperh->perh->CCEP, TIMER_CCEP_CC1POL_MSK, (config->ic1_polarity & 0x1) << TIMER_CCEP_CC1POL_POS); - MODIFY_REG(hperh->perh->CCEP, TIMER_CCEP_CC1NPOL_MSK, ((config->ic1_polarity >> 1) & 0x1) << TIMER_CCEP_CC1NPOL_POS); - MODIFY_REG(hperh->perh->CCEP, TIMER_CCEP_CC2POL_MSK, (config->ic2_polarity & 0x1) << TIMER_CCEP_CC2POL_POS); - MODIFY_REG(hperh->perh->CCEP, TIMER_CCEP_CC2NPOL_MSK, ((config->ic2_polarity >> 1) & 0x1) << TIMER_CCEP_CC2NPOL_POS); - - hperh->state = TIMER_STATE_READY; - return OK; -} - -/** - * @brief Starts the TIMER Encoder Interface. - * @param hperh: TIMER handle - * @param ch: TIMER Channels to be enabled - * This parameter can be one of the following values: - * @arg TIMER_CHANNEL_1: TIMER Channel 1 selected - * @arg TIMER_CHANNEL_2: TIMER Channel 2 selected - * @arg TIMER_CHANNEL_ALL: TIMER Channel 1 and TIMER Channel 2 are selected - * @retval None - */ -void ald_timer_encoder_start(timer_handle_t *hperh, timer_channel_t ch) -{ - assert_param(IS_TIMER_CC2_INSTANCE(hperh->perh)); - - switch (ch) { - case TIMER_CHANNEL_1: - timer_ccx_channel_cmd(hperh->perh, TIMER_CHANNEL_1, ENABLE); - break; - case TIMER_CHANNEL_2: - timer_ccx_channel_cmd(hperh->perh, TIMER_CHANNEL_2, ENABLE); - break; - default: - timer_ccx_channel_cmd(hperh->perh, TIMER_CHANNEL_1, ENABLE); - timer_ccx_channel_cmd(hperh->perh, TIMER_CHANNEL_2, ENABLE); - break; - } - - TIMER_ENABLE(hperh); - return; -} - -/** - * @brief Stops the TIMER Encoder Interface. - * @param hperh: TIMER handle - * @param ch: TIMER Channels to be enabled - * This parameter can be one of the following values: - * @arg TIMER_CHANNEL_1: TIMER Channel 1 selected - * @arg TIMER_CHANNEL_2: TIMER Channel 2 selected - * @arg TIMER_CHANNEL_ALL: TIMER Channel 1 and TIMER Channel 2 are selected - * @retval None - */ -void ald_timer_encoder_stop(timer_handle_t *hperh, timer_channel_t ch) -{ - assert_param(IS_TIMER_CC2_INSTANCE(hperh->perh)); - - switch (ch) { - case TIMER_CHANNEL_1: - timer_ccx_channel_cmd(hperh->perh, TIMER_CHANNEL_1, DISABLE); - break; - case TIMER_CHANNEL_2: - timer_ccx_channel_cmd(hperh->perh, TIMER_CHANNEL_2, DISABLE); - break; - default: - timer_ccx_channel_cmd(hperh->perh, TIMER_CHANNEL_1, DISABLE); - timer_ccx_channel_cmd(hperh->perh, TIMER_CHANNEL_2, DISABLE); - break; - } - - TIMER_DISABLE(hperh); - return; -} - -/** - * @brief Starts the TIMER Encoder Interface in interrupt mode. - * @param hperh: TIMER handle - * @param ch: TIMER Channels to be enabled - * This parameter can be one of the following values: - * @arg TIMER_CHANNEL_1: TIMER Channel 1 selected - * @arg TIMER_CHANNEL_2: TIMER Channel 2 selected - * @arg TIMER_CHANNEL_ALL: TIMER Channel 1 and TIMER Channel 2 are selected - * @retval None - */ -void ald_timer_encoder_start_by_it(timer_handle_t *hperh, timer_channel_t ch) -{ - assert_param(IS_TIMER_CC2_INSTANCE(hperh->perh)); - - switch (ch) { - case TIMER_CHANNEL_1: - timer_ccx_channel_cmd(hperh->perh, TIMER_CHANNEL_1, ENABLE); - ald_timer_interrupt_config(hperh, TIMER_IT_CC1, ENABLE); - break; - case TIMER_CHANNEL_2: - timer_ccx_channel_cmd(hperh->perh, TIMER_CHANNEL_2, ENABLE); - ald_timer_interrupt_config(hperh, TIMER_IT_CC2, ENABLE); - break; - default: - timer_ccx_channel_cmd(hperh->perh, TIMER_CHANNEL_1, ENABLE); - timer_ccx_channel_cmd(hperh->perh, TIMER_CHANNEL_2, ENABLE); - ald_timer_interrupt_config(hperh, TIMER_IT_CC1, ENABLE); - ald_timer_interrupt_config(hperh, TIMER_IT_CC2, ENABLE); - break; - } - - TIMER_ENABLE(hperh); - return; -} - -/** - * @brief Stops the TIMER Encoder Interface in interrupt mode. - * @param hperh: TIMER handle - * @param ch: TIMER Channels to be enabled - * This parameter can be one of the following values: - * @arg TIMER_CHANNEL_1: TIMER Channel 1 selected - * @arg TIMER_CHANNEL_2: TIMER Channel 2 selected - * @arg TIMER_CHANNEL_ALL: TIMER Channel 1 and TIMER Channel 2 are selected - * @retval None - */ -void ald_timer_encoder_stop_by_it(timer_handle_t *hperh, timer_channel_t ch) -{ - assert_param(IS_TIMER_CC2_INSTANCE(hperh->perh)); - - switch (ch) { - case TIMER_CHANNEL_1: - timer_ccx_channel_cmd(hperh->perh, TIMER_CHANNEL_1, DISABLE); - ald_timer_interrupt_config(hperh, TIMER_IT_CC1, DISABLE); - break; - case TIMER_CHANNEL_2: - timer_ccx_channel_cmd(hperh->perh, TIMER_CHANNEL_2, DISABLE); - ald_timer_interrupt_config(hperh, TIMER_IT_CC2, DISABLE); - break; - default: - timer_ccx_channel_cmd(hperh->perh, TIMER_CHANNEL_1, DISABLE); - timer_ccx_channel_cmd(hperh->perh, TIMER_CHANNEL_2, DISABLE); - ald_timer_interrupt_config(hperh, TIMER_IT_CC1, DISABLE); - ald_timer_interrupt_config(hperh, TIMER_IT_CC2, DISABLE); - break; - } - - TIMER_DISABLE(hperh); - hperh->state = TIMER_STATE_READY; - return; -} - -#ifdef ALD_DMA -/** - * @brief Starts the TIMER Encoder Interface in DMA mode. - * @param hperh: TIMER handle - * @param ch: TIMER Channels to be enabled - * This parameter can be one of the following values: - * @arg TIMER_CHANNEL_1: TIMER Channel 1 selected - * @arg TIMER_CHANNEL_2: TIMER Channel 2 selected - * @arg TIMER_CHANNEL_ALL: TIMER Channel 1 and TIMER Channel 2 are selected - * @param buf1: The destination Buffer address. Reading data from CCR1. - * @param buf2: The destination Buffer address. Reading data from CCR2. - * @param len: The length of buffer to be transferred TIMER peripheral to memory - * @param dma_ch1: Channel of DMA. - * @param dma_ch2: Channel of DMA. - * @retval Status, see @ref ald_status_t. - */ -ald_status_t ald_timer_encoder_start_by_dma(timer_handle_t *hperh, timer_channel_t ch, - uint16_t *buf1, uint16_t *buf2, uint32_t len, - uint8_t dma_ch1, uint8_t dma_ch2) -{ - assert_param(IS_TIMER_CC2_INSTANCE(hperh->perh)); - - if ((hperh->state == TIMER_STATE_BUSY)) - return BUSY; - if ((hperh->state == TIMER_STATE_READY)) { - if (((uint32_t)buf1 == 0) || ((uint32_t)buf2 == 0) || (len == 0)) - return ERROR; - } - - if (hperh->hdma1.perh == NULL) - hperh->hdma1.perh = DMA0; - if (hperh->hdma2.perh == NULL) - hperh->hdma2.perh = DMA0; - - hperh->state = TIMER_STATE_BUSY; - hperh->hdma1.cplt_cbk = timer_dma_capture_cplt; - hperh->hdma1.cplt_arg = (void *)hperh; - hperh->hdma1.err_cbk = timer_dma_error; - hperh->hdma1.err_arg = (void *)hperh; - - ald_dma_config_struct(&hperh->hdma1.config); - hperh->hdma1.config.size = len; - hperh->hdma1.config.data_width = DMA_DATA_SIZE_HALFWORD; - hperh->hdma1.config.src_inc = DMA_DATA_INC_NONE; - hperh->hdma1.config.dst_inc = DMA_DATA_INC_HALFWORD; - - timer_dma_msel(hperh->perh, &hperh->hdma1.config); - - switch (ch) { - case TIMER_CHANNEL_1: - hperh->hdma1.config.src = (void *)&hperh->perh->CCVAL1; - hperh->hdma1.config.dst = (void *)buf1; - hperh->hdma1.config.msigsel = DMA_MSIGSEL_TIMER_CH1; - hperh->hdma1.config.channel = dma_ch1; - ald_dma_config_basic(&hperh->hdma1); - ald_timer_dma_req_config(hperh, TIMER_DMA_CC1, ENABLE); - timer_ccx_channel_cmd(hperh->perh, TIMER_CHANNEL_1, ENABLE); - TIMER_ENABLE(hperh); - break; - - case TIMER_CHANNEL_2: - hperh->hdma1.config.src = (void *)&hperh->perh->CCVAL2; - hperh->hdma1.config.dst = (void *)buf2; - hperh->hdma1.config.msigsel = DMA_MSIGSEL_TIMER_CH2; - hperh->hdma1.config.channel = dma_ch2; - ald_dma_config_basic(&hperh->hdma1); - ald_timer_dma_req_config(hperh, TIMER_DMA_CC2, ENABLE); - timer_ccx_channel_cmd(hperh->perh, TIMER_CHANNEL_2, ENABLE); - TIMER_ENABLE(hperh); - break; - - default: - hperh->hdma2.cplt_cbk = timer_dma_capture_cplt; - hperh->hdma2.cplt_arg = (void *)hperh; - hperh->hdma2.err_cbk = timer_dma_error; - hperh->hdma2.err_arg = (void *)hperh; - memcpy(&hperh->hdma2.config, &hperh->hdma1.config, sizeof(dma_config_t)); - - hperh->hdma1.config.src = (void *)&hperh->perh->CCVAL1; - hperh->hdma1.config.dst = (void *)buf1; - hperh->hdma1.config.msigsel = DMA_MSIGSEL_TIMER_CH1; - hperh->hdma1.config.channel = dma_ch1; - ald_dma_config_basic(&hperh->hdma1); - ald_timer_dma_req_config(hperh, TIMER_DMA_CC1, ENABLE); - - hperh->hdma2.config.src = (void *)&hperh->perh->CCVAL2; - hperh->hdma2.config.dst = (void *)buf2; - hperh->hdma2.config.msigsel = DMA_MSIGSEL_TIMER_CH2; - hperh->hdma2.config.channel = dma_ch2; - ald_dma_config_basic(&hperh->hdma2); - ald_timer_dma_req_config(hperh, TIMER_DMA_CC2, ENABLE); - - timer_ccx_channel_cmd(hperh->perh, TIMER_CHANNEL_1, ENABLE); - timer_ccx_channel_cmd(hperh->perh, TIMER_CHANNEL_2, ENABLE); - TIMER_ENABLE(hperh); - break; - } - - return OK; -} - -/** - * @brief Stops the TIMER Encoder Interface in DMA mode. - * @param hperh: TIMER handle - * @param ch: TIMER Channels to be disabled - * This parameter can be one of the following values: - * @arg TIMER_CHANNEL_1: TIMER Channel 1 selected - * @arg TIMER_CHANNEL_2: TIMER Channel 2 selected - * @arg TIMER_CHANNEL_ALL: TIMER Channel 1 and TIMER Channel 2 are selected - * @retval None - */ -void ald_timer_encoder_stop_by_dma(timer_handle_t *hperh, timer_channel_t ch) -{ - assert_param(IS_TIMER_CC2_INSTANCE(hperh->perh)); - - switch (ch) { - case TIMER_CHANNEL_1: - timer_ccx_channel_cmd(hperh->perh, TIMER_CHANNEL_1, DISABLE); - ald_timer_dma_req_config(hperh, TIMER_DMA_CC1, DISABLE); - break; - case TIMER_CHANNEL_2: - timer_ccx_channel_cmd(hperh->perh, TIMER_CHANNEL_2, DISABLE); - ald_timer_dma_req_config(hperh, TIMER_DMA_CC2, DISABLE); - break; - default: - timer_ccx_channel_cmd(hperh->perh, TIMER_CHANNEL_1, DISABLE); - timer_ccx_channel_cmd(hperh->perh, TIMER_CHANNEL_2, DISABLE); - ald_timer_dma_req_config(hperh, TIMER_DMA_CC1, DISABLE); - ald_timer_dma_req_config(hperh, TIMER_DMA_CC2, DISABLE); - break; - } - - TIMER_DISABLE(hperh); - hperh->state = TIMER_STATE_READY; - return; -} -#endif -/** - * @} - */ - -/** @defgroup TIMER_Public_Functions_Group7 TIMER Hall Sensor functions - * @brief TIMER Hall Sensor functions - * - * @verbatim - ============================================================================== - ##### Time Hall Sensor functions ##### - ============================================================================== - [..] - This section provides functions allowing to: - (+) Initialize and configure the TIMER hall sensor. - (+) Start the hall sensor. - (+) Stop the hall sensor. - (+) Start the hall sensor and enable interrupt. - (+) Stop the hall sensor and disable interrupt. - (+) Start the hall sensor and enable DMA transfer. - (+) Stop the hal sensor and disable DMA transfer. - - * @endverbatim - * @{ - */ -/** - * @brief Initializes the TIMER Encoder Interface and create the associated handle. - * @param hperh: TIMER handle - * @param config: TIMER Encoder Interface configuration structure - * @retval Status, see @ref ald_status_t. - */ -ald_status_t ald_timer_hall_sensor_init(timer_handle_t *hperh, timer_hall_sensor_init_t *config) -{ - timer_oc_init_t oc; - - assert_param(IS_TIMER_XOR_INSTANCE(hperh->perh)); - assert_param(IS_TIMER_COUNTER_MODE(hperh->init.mode)); - assert_param(IS_TIMER_CLOCK_DIVISION(hperh->init.clk_div)); - assert_param(IS_TIMER_IC_POLARITY(config->polarity)); - assert_param(IS_TIMER_IC_PSC(config->psc)); - assert_param(IS_TIMER_IC_FILTER(config->filter)); - - if (hperh->state == TIMER_STATE_RESET) - hperh->lock = UNLOCK; - - hperh->state = TIMER_STATE_READY; - timer_base_set_config(hperh->perh, &hperh->init); - timer_ti1_set_config(hperh->perh, config->polarity, TIMER_IC_SEL_TRC, config->filter); - - MODIFY_REG(hperh->perh->CHMR1, TIMER_CHMR1_IC1PRES_MSK, config->psc << TIMER_CHMR1_IC1PRES_POSS); - SET_BIT(hperh->perh->CON2, TIMER_CON2_I1FSEL_MSK); - MODIFY_REG(hperh->perh->SMCON, TIMER_SMCON_TSSEL_MSK, TIMER_TS_TI1F_ED << TIMER_SMCON_TSSEL_POSS); - MODIFY_REG(hperh->perh->SMCON, TIMER_SMCON_SMODS_MSK, TIMER_MODE_RESET << TIMER_SMCON_SMODS_POSS); - - oc.oc_mode = TIMER_OC_MODE_PWM2; - oc.pulse = config->delay; - oc.oc_polarity = TIMER_OC_POLARITY_HIGH; - oc.ocn_polarity = TIMER_OCN_POLARITY_HIGH; - oc.oc_fast_en = DISABLE; - oc.oc_idle = TIMER_OC_IDLE_RESET; - oc.ocn_idle = TIMER_OCN_IDLE_RESET; - timer_oc2_set_config(hperh->perh, &oc); - - MODIFY_REG(hperh->perh->SMCON, TIMER_SMCON_SMODS_MSK, TIMER_TRGO_OC2REF << TIMER_SMCON_SMODS_POSS); - return OK; -} -/** - * @brief Starts the TIMER hall sensor interface. - * @param hperh: TIMER handle - * @retval None - */ -void ald_timer_hall_sensor_start(timer_handle_t *hperh) -{ - assert_param(IS_TIMER_XOR_INSTANCE(hperh->perh)); - - timer_ccx_channel_cmd(hperh->perh, TIMER_CHANNEL_1, ENABLE); - TIMER_ENABLE(hperh); - - return; -} - -/** - * @brief Stops the TIMER hall sensor interface. - * @param hperh: TIMER handle - * @retval None - */ -void ald_timer_hall_sensor_stop(timer_handle_t *hperh) -{ - assert_param(IS_TIMER_XOR_INSTANCE(hperh->perh)); - - timer_ccx_channel_cmd(hperh->perh, TIMER_CHANNEL_1, DISABLE); - TIMER_DISABLE(hperh); - - return; -} - -/** - * @brief Starts the TIMER hall sensor interface in interrupt mode. - * @param hperh: TIMER handle - * @retval None - */ -void ald_timer_hall_sensor_start_by_it(timer_handle_t *hperh) -{ - assert_param(IS_TIMER_XOR_INSTANCE(hperh->perh)); - - ald_timer_interrupt_config(hperh, TIMER_IT_CC1, ENABLE); - timer_ccx_channel_cmd(hperh->perh, TIMER_CHANNEL_1, ENABLE); - TIMER_ENABLE(hperh); - - return; -} - -/** - * @brief Stops the TIMER hall sensor interface in interrupt mode. - * @param hperh: TIMER handle - * @retval None - */ -void ald_timer_hall_sensor_stop_by_it(timer_handle_t *hperh) -{ - assert_param(IS_TIMER_XOR_INSTANCE(hperh->perh)); - - timer_ccx_channel_cmd(hperh->perh, TIMER_CHANNEL_1, DISABLE); - ald_timer_interrupt_config(hperh, TIMER_IT_CC1, DISABLE); - TIMER_DISABLE(hperh); - - return; -} - -#ifdef ALD_DMA -/** - * @brief Starts the TIMER hall sensor interface in DMA mode. - * @param hperh: TIMER handle - * @param buf: The destination Buffer address. Reading data from CCR1. - * @param len: The length of buffer to be transferred TIMER peripheral to memory - * @param dma_ch: Channel of DMA. - * @retval Status, see @ref ald_status_t. - */ -ald_status_t ald_timer_hall_sensor_start_by_dma(timer_handle_t *hperh, - uint16_t *buf, uint32_t len, uint8_t dma_ch) -{ - assert_param(IS_TIMER_XOR_INSTANCE(hperh->perh)); - - if ((hperh->state == TIMER_STATE_BUSY)) - return BUSY; - if ((hperh->state == TIMER_STATE_READY)) { - if (((uint32_t)buf == 0) || (len == 0)) - return ERROR; - } - - if (hperh->hdma1.perh == NULL) - hperh->hdma1.perh = DMA0; - - hperh->state = TIMER_STATE_BUSY; - hperh->hdma1.cplt_cbk = timer_dma_capture_cplt; - hperh->hdma1.cplt_arg = (void *)hperh; - hperh->hdma1.err_cbk = timer_dma_error; - hperh->hdma1.err_arg = (void *)hperh; - - ald_dma_config_struct(&hperh->hdma1.config); - hperh->hdma1.config.size = len; - hperh->hdma1.config.data_width = DMA_DATA_SIZE_HALFWORD; - hperh->hdma1.config.src_inc = DMA_DATA_INC_NONE; - hperh->hdma1.config.dst_inc = DMA_DATA_INC_HALFWORD; - - timer_dma_msel(hperh->perh, &hperh->hdma1.config); - - hperh->hdma1.config.src = (void *)&hperh->perh->CCVAL1; - hperh->hdma1.config.dst = (void *)buf; - hperh->hdma1.config.msigsel = DMA_MSIGSEL_TIMER_CH1; - hperh->hdma1.config.channel = dma_ch; - ald_dma_config_basic(&hperh->hdma1); - ald_timer_dma_req_config(hperh, TIMER_DMA_CC1, ENABLE); - timer_ccx_channel_cmd(hperh->perh, TIMER_CHANNEL_1, ENABLE); - TIMER_ENABLE(hperh); - - return OK; -} -/** - * @brief Stops the TIMER hall sensor interface in DMA mode. - * @param hperh: TIMER handle - * @retval None - */ -void ald_timer_hall_sensor_stop_by_dma(timer_handle_t *hperh) -{ - assert_param(IS_TIMER_XOR_INSTANCE(hperh->perh)); - - ald_timer_dma_req_config(hperh, TIMER_DMA_CC1, DISABLE); - timer_ccx_channel_cmd(hperh->perh, TIMER_CHANNEL_1, DISABLE); - TIMER_DISABLE(hperh); - - return; -} -#endif -/** - * @} - */ - -/** @defgroup TIMER_Public_Functions_Group8 TIMER complementary output compare functions - * @brief TIMER complementary output compare functions - * - * @verbatim - ============================================================================== - ##### Time complementary output compare functions ##### - ============================================================================== - [..] - This section provides functions allowing to: - (+) Start the Time complementary output compare. - (+) Stop the Time complementary output compare. - (+) Start the Time complementary output compare and enable interrupt. - (+) Stop the Time complementary output compare and disable interrupt. - (+) Start the Time complementary output compare and enable DMA transfer. - (+) Stop the Time complementary output compare and disable DMA transfer. - - * @endverbatim - * @{ - */ - -/** - * @brief Starts the TIMER output compare signal generation on the complementary output. - * @param hperh: TIMER handle - * @param ch: TIMER Channels to be enabled - * This parameter can be one of the following values: - * @arg TIMER_CHANNEL_1: TIMER Channel 1 selected - * @arg TIMER_CHANNEL_2: TIMER Channel 2 selected - * @arg TIMER_CHANNEL_3: TIMER Channel 3 selected - * @retval None - */ -void ald_timer_ocn_start(timer_handle_t *hperh, timer_channel_t ch) -{ - assert_param(IS_TIMER_CCXN_INSTANCE(hperh->perh, ch)); - - timer_ccxn_channel_cmd(hperh->perh, ch, ENABLE); - TIMER_MOE_ENABLE(hperh); - TIMER_ENABLE(hperh); - - return; -} - -/** - * @brief Stops the TIMER output compare signal generation on the complementary output. - * @param hperh: TIMER handle - * @param ch: TIMER Channels to be disabled - * This parameter can be one of the following values: - * @arg TIMER_CHANNEL_1: TIMER Channel 1 selected - * @arg TIMER_CHANNEL_2: TIMER Channel 2 selected - * @arg TIMER_CHANNEL_3: TIMER Channel 3 selected - * @retval None - */ -void ald_timer_ocn_stop(timer_handle_t *hperh, timer_channel_t ch) -{ - assert_param(IS_TIMER_CCXN_INSTANCE(hperh->perh, ch)); - - timer_ccxn_channel_cmd(hperh->perh, ch, DISABLE); - TIMER_MOE_DISABLE(hperh); - TIMER_DISABLE(hperh); - - return; -} - -/** - * @brief Starts the TIMER output compare signal generation on the complementary output. - * in interrupt mode - * @param hperh: TIMER handle - * @param ch: TIMER Channels to be enabled - * This parameter can be one of the following values: - * @arg TIMER_CHANNEL_1: TIMER Channel 1 selected - * @arg TIMER_CHANNEL_2: TIMER Channel 2 selected - * @arg TIMER_CHANNEL_3: TIMER Channel 3 selected - * @retval None - */ -void ald_timer_ocn_start_by_it(timer_handle_t *hperh, timer_channel_t ch) -{ - assert_param(IS_TIMER_CCXN_INSTANCE(hperh->perh, ch)); - - switch (ch) { - case TIMER_CHANNEL_1: - ald_timer_interrupt_config(hperh, TIMER_IT_CC1, ENABLE); - break; - - case TIMER_CHANNEL_2: - ald_timer_interrupt_config(hperh, TIMER_IT_CC2, ENABLE); - break; - - case TIMER_CHANNEL_3: - ald_timer_interrupt_config(hperh, TIMER_IT_CC3, ENABLE); - break; - default: - break; - } - - ald_timer_interrupt_config(hperh, TIMER_IT_BREAK, ENABLE); - timer_ccxn_channel_cmd(hperh->perh, ch, ENABLE); - TIMER_MOE_ENABLE(hperh); - TIMER_ENABLE(hperh); - - return; -} - -/** - * @brief Stops the TIMER output compare signal generation on the complementary output. - * in interrupt mode - * @param hperh: TIMER handle - * @param ch: TIMER Channels to be disabled - * This parameter can be one of the following values: - * @arg TIMER_CHANNEL_1: TIMER Channel 1 selected - * @arg TIMER_CHANNEL_2: TIMER Channel 2 selected - * @arg TIMER_CHANNEL_3: TIMER Channel 3 selected - * @retval None - */ -void ald_timer_ocn_stop_by_it(timer_handle_t *hperh, timer_channel_t ch) -{ - assert_param(IS_TIMER_CCXN_INSTANCE(hperh->perh, ch)); - - switch (ch) { - case TIMER_CHANNEL_1: - ald_timer_interrupt_config(hperh, TIMER_IT_CC1, DISABLE); - break; - - case TIMER_CHANNEL_2: - ald_timer_interrupt_config(hperh, TIMER_IT_CC2, DISABLE); - break; - - case TIMER_CHANNEL_3: - ald_timer_interrupt_config(hperh, TIMER_IT_CC3, DISABLE); - break; - default: - break; - } - - if ((!(READ_BIT(hperh->perh->CCEP, TIMER_CCEP_CC1NEN_MSK))) - && (!(READ_BIT(hperh->perh->CCEP, TIMER_CCEP_CC2NEN_MSK))) - && (!(READ_BIT(hperh->perh->CCEP, TIMER_CCEP_CC3NEN_MSK)))) { - ald_timer_interrupt_config(hperh, TIMER_IT_BREAK, DISABLE); - } - - timer_ccxn_channel_cmd(hperh->perh, ch, DISABLE); - TIMER_MOE_DISABLE(hperh); - TIMER_DISABLE(hperh); - - return; -} - -#ifdef ALD_DMA -/** - * @brief Starts the TIMER output compare signal generation on the complementary output. - * in DMA mode - * @param hperh: TIMER handle - * @param ch: TIMER Channels to be enabled - * This parameter can be one of the following values: - * @arg TIMER_CHANNEL_1: TIMER Channel 1 selected - * @arg TIMER_CHANNEL_2: TIMER Channel 2 selected - * @arg TIMER_CHANNEL_3: TIMER Channel 3 selected - * @param buf: The destination Buffer address. Reading data from CCRx. - * @param len: The length of buffer to be transferred TIMER peripheral to memory - * @param dma_ch: Channel of DMA. - * @retval None - */ -ald_status_t ald_timer_ocn_start_by_dma(timer_handle_t *hperh, - timer_channel_t ch, uint16_t *buf, uint32_t len, uint8_t dma_ch) -{ - assert_param(IS_TIMER_CCXN_INSTANCE(hperh->perh, ch)); - - if ((hperh->state == TIMER_STATE_BUSY)) - return BUSY; - if ((hperh->state == TIMER_STATE_READY)) { - if (((uint32_t)buf == 0 ) || (len == 0)) - return ERROR; - } - - hperh->state = TIMER_STATE_BUSY; - - if (hperh->hdma1.perh == NULL) - hperh->hdma1.perh = DMA0; - - hperh->hdma1.cplt_cbk = timer_dma_oc_cplt; - hperh->hdma1.cplt_arg = (void *)hperh; - hperh->hdma1.err_cbk = timer_dma_error; - hperh->hdma1.err_arg = (void *)hperh; - - ald_dma_config_struct(&hperh->hdma1.config); - hperh->hdma1.config.src = (void *)buf; - hperh->hdma1.config.size = len; - hperh->hdma1.config.data_width = DMA_DATA_SIZE_HALFWORD; - hperh->hdma1.config.src_inc = DMA_DATA_INC_HALFWORD; - hperh->hdma1.config.dst_inc = DMA_DATA_INC_NONE; - hperh->hdma1.config.channel = dma_ch; - hperh->hdma1.config.msel = DMA_MSEL_TIMER0; - - switch (ch) { - case TIMER_CHANNEL_1: - hperh->hdma1.config.dst = (void *)&hperh->perh->CCVAL1; - hperh->hdma1.config.msigsel = DMA_MSIGSEL_TIMER_CH1; - ald_dma_config_basic(&hperh->hdma1); - ald_timer_dma_req_config(hperh, TIMER_DMA_CC1, ENABLE); - hperh->ch = TIMER_ACTIVE_CHANNEL_1; - break; - - case TIMER_CHANNEL_2: - hperh->hdma1.config.dst = (void *)&hperh->perh->CCVAL2; - hperh->hdma1.config.msigsel = DMA_MSIGSEL_TIMER_CH2; - ald_dma_config_basic(&hperh->hdma1); - ald_timer_dma_req_config(hperh, TIMER_DMA_CC2, ENABLE); - hperh->ch = TIMER_ACTIVE_CHANNEL_2; - break; - - case TIMER_CHANNEL_3: - hperh->hdma1.config.dst = (void *)&hperh->perh->CCVAL3; - hperh->hdma1.config.msigsel = DMA_MSIGSEL_TIMER_CH3; - ald_dma_config_basic(&hperh->hdma1); - ald_timer_dma_req_config(hperh, TIMER_DMA_CC3, ENABLE); - hperh->ch = TIMER_ACTIVE_CHANNEL_3; - break; - - default: - break; - } - - timer_ccx_channel_cmd(hperh->perh, ch, ENABLE); - TIMER_MOE_ENABLE(hperh); - TIMER_ENABLE(hperh); - - return OK; -} - -/** - * @brief Starts the TIMER output compare signal generation on the complementary output. - * in DMA mode - * @param hperh: TIMER handle - * @param ch: TIMER Channels to be disabled - * This parameter can be one of the following values: - * @arg TIMER_CHANNEL_1: TIMER Channel 1 selected - * @arg TIMER_CHANNEL_2: TIMER Channel 2 selected - * @arg TIMER_CHANNEL_3: TIMER Channel 3 selected - * @retval None - */ -void ald_timer_ocn_stop_by_dma(timer_handle_t *hperh, timer_channel_t ch) -{ - assert_param(IS_TIMER_CCXN_INSTANCE(hperh->perh, ch)); - - switch (ch) { - case TIMER_CHANNEL_1: - ald_timer_dma_req_config(hperh, TIMER_DMA_CC1, DISABLE); - break; - - case TIMER_CHANNEL_2: - ald_timer_dma_req_config(hperh, TIMER_DMA_CC2, DISABLE); - break; - - case TIMER_CHANNEL_3: - ald_timer_dma_req_config(hperh, TIMER_DMA_CC3, DISABLE); - break; - default: - break; - } - - timer_ccxn_channel_cmd(hperh->perh, ch, DISABLE); - TIMER_MOE_DISABLE(hperh); - TIMER_DISABLE(hperh); - - return; -} -#endif -/** - * @} - */ - -/** @defgroup TIMER_Public_Functions_Group9 TIMER complementary PWM functions - * @brief TIMER complementary PWM functions - * - * @verbatim - ============================================================================== - ##### Time complementary PWM functions ##### - ============================================================================== - [..] - This section provides functions allowing to: - (+) Start the Time complementary PWM. - (+) Stop the Time complementary PWM. - (+) Start the Time complementary PWM and enable interrupt. - (+) Stop the Time complementary PWM and disable interrupt. - (+) Start the Time complementary PWM and enable DMA transfer. - (+) Stop the Time complementary PWM and disable DMA transfer. - - * @endverbatim - * @{ - */ - -/** - * @brief Starts the TIMER PWM signal generation on the complementary output. - * @param hperh: TIMER handle - * @param ch: TIMER Channels to be enabled - * This parameter can be one of the following values: - * @arg TIMER_CHANNEL_1: TIMER Channel 1 selected - * @arg TIMER_CHANNEL_2: TIMER Channel 2 selected - * @arg TIMER_CHANNEL_3: TIMER Channel 3 selected - * @retval None - */ -void ald_timer_pwmn_start(timer_handle_t *hperh, timer_channel_t ch) -{ - ald_timer_ocn_start(hperh, ch); -} - -/** - * @brief Stops the TIMER PWM signal generation on the complementary output. - * @param hperh: TIMER handle - * @param ch: TIMER Channels to be disabled - * This parameter can be one of the following values: - * @arg TIMER_CHANNEL_1: TIMER Channel 1 selected - * @arg TIMER_CHANNEL_2: TIMER Channel 2 selected - * @arg TIMER_CHANNEL_3: TIMER Channel 3 selected - * @retval None - */ -void ald_timer_pwmn_stop(timer_handle_t *hperh, timer_channel_t ch) -{ - ald_timer_ocn_stop(hperh, ch); -} - -/** - * @brief Starts the TIMER PWM signal generation on the complementary output. - * in interrupt mode - * @param hperh: TIMER handle - * @param ch: TIMER Channels to be enabled - * This parameter can be one of the following values: - * @arg TIMER_CHANNEL_1: TIMER Channel 1 selected - * @arg TIMER_CHANNEL_2: TIMER Channel 2 selected - * @arg TIMER_CHANNEL_3: TIMER Channel 3 selected - * @retval None - */ -void ald_timer_pwmn_start_by_it(timer_handle_t *hperh, timer_channel_t ch) -{ - ald_timer_ocn_start_by_it(hperh, ch); -} - -/** - * @brief Stops the TIMER PWM signal generation on the complementary output. - * in interrupt mode - * @param hperh: TIMER handle - * @param ch: TIMER Channels to be disabled - * This parameter can be one of the following values: - * @arg TIMER_CHANNEL_1: TIMER Channel 1 selected - * @arg TIMER_CHANNEL_2: TIMER Channel 2 selected - * @arg TIMER_CHANNEL_3: TIMER Channel 3 selected - * @retval None - */ -void ald_timer_pwmn_stop_by_it(timer_handle_t *hperh, timer_channel_t ch) -{ - ald_timer_ocn_stop_by_it(hperh, ch); -} - -#ifdef ALD_DMA -/** - * @brief Starts the TIMER PWM signal generation on the complementary output. - * in DMA mode - * @param hperh: TIMER handle - * @param ch: TIMER Channels to be enabled - * This parameter can be one of the following values: - * @arg TIMER_CHANNEL_1: TIMER Channel 1 selected - * @arg TIMER_CHANNEL_2: TIMER Channel 2 selected - * @arg TIMER_CHANNEL_3: TIMER Channel 3 selected - * @param buf: The destination Buffer address. Reading data from CCRx. - * @param len: The length of buffer to be transferred TIMER peripheral to memory - * @param dma_ch: Channel of DMA. - * @retval None - */ -ald_status_t ald_timer_pwmn_start_by_dma(timer_handle_t *hperh, - timer_channel_t ch, uint16_t *buf, uint32_t len, uint8_t dma_ch) -{ - return ald_timer_ocn_start_by_dma(hperh, ch, buf, len, dma_ch); -} - -/** - * @brief Starts the TIMER PWM signal generation on the complementary output. - * in DMA mode - * @param hperh: TIMER handle - * @param ch: TIMER Channels to be disabled - * This parameter can be one of the following values: - * @arg TIMER_CHANNEL_1: TIMER Channel 1 selected - * @arg TIMER_CHANNEL_2: TIMER Channel 2 selected - * @arg TIMER_CHANNEL_3: TIMER Channel 3 selected - * @retval None - */ -void ald_timer_pwmn_stop_by_dma(timer_handle_t *hperh, timer_channel_t ch) -{ - ald_timer_ocn_stop_by_dma(hperh, ch); -} -#endif -/** - * @} - */ - -/** @defgroup TIMER_Public_Functions_Group10 TIMER complementary one pulse functions - * @brief TIMER complementary one pulse functions - * - * @verbatim - ============================================================================== - ##### Time complementary one pulse functions ##### - ============================================================================== - [..] - This section provides functions allowing to: - (+) Start the Time complementary one pulse. - (+) Stop the Time complementary one pulse. - (+) Start the Time complementary one pulse and enable interrupt. - (+) Stop the Time complementary one pulse and disable interrupt. - - * @endverbatim - * @{ - */ - -/** - * @brief Starts the TIMER one pulse signal generation on the complementary output. - * @param hperh: TIMER handle - * @param ch: TIMER Channels to be enabled - * This parameter can be one of the following values: - * @arg TIMER_CHANNEL_1: TIMER Channel 1 selected - * @arg TIMER_CHANNEL_2: TIMER Channel 2 selected - * @retval None - */ -void ald_timer_one_pulse_n_start(timer_handle_t *hperh, timer_channel_t ch) -{ - ald_timer_ocn_start(hperh, ch); -} - -/** - * @brief Stops the TIMER one pulse signal generation on the complementary output. - * @param hperh: TIMER handle - * @param ch: TIMER Channels to be disabled - * This parameter can be one of the following values: - * @arg TIMER_CHANNEL_1: TIMER Channel 1 selected - * @arg TIMER_CHANNEL_2: TIMER Channel 2 selected - * @retval None - */ -void ald_timer_one_pulse_n_stop(timer_handle_t *hperh, timer_channel_t ch) -{ - ald_timer_ocn_stop(hperh, ch); -} - -/** - * @brief Starts the TIMER one pulse signal generation on the complementary output. - * in interrupt mode - * @param hperh: TIMER handle - * @param ch: TIMER Channels to be enabled - * This parameter can be one of the following values: - * @arg TIMER_CHANNEL_1: TIMER Channel 1 selected - * @arg TIMER_CHANNEL_2: TIMER Channel 2 selected - * @retval None - */ -void ald_timer_one_pulse_n_start_by_it(timer_handle_t *hperh, timer_channel_t ch) -{ - ald_timer_ocn_start_by_it(hperh, ch); -} - -/** - * @brief Stops the TIMER one pulse signal generation on the complementary output. - * in interrupt mode - * @param hperh: TIMER handle - * @param ch: TIMER Channels to be disabled - * This parameter can be one of the following values: - * @arg TIMER_CHANNEL_1: TIMER Channel 1 selected - * @arg TIMER_CHANNEL_2: TIMER Channel 2 selected - * @retval None - */ -void ald_timer_one_pulse_n_stop_by_it(timer_handle_t *hperh, timer_channel_t ch) -{ - ald_timer_ocn_stop_by_it(hperh, ch); -} -/** - * @} - */ - -/** @defgroup TIMER_Public_Functions_Group11 Peripheral Control functions - * @brief Peripheral Control functions - * - * @verbatim - ============================================================================== - ##### Peripheral Control functions ##### - ============================================================================== - [..] - This section provides functions allowing to: - (+) Configure The Input Output channels for OC, PWM, IC or One Pulse mode. - (+) Configure External Clock source. - (+) Configure Complementary channels, break features and dead timere. - (+) Configure Master and the Slave synchronization. - (+) Handle TIMER interrupt. - (+) Get TIMER compare register's vale. - (+) Configure TIMER interrupt ENABLE/DISABLE. - (+) Get TIMER interrupt source status. - (+) Get TIMER interrupt flag status. - (+) Clear TIMER interrupt flag. - - @endverbatim - * @{ - */ -/** - * @brief Initializes the TIMER Output Compare Channels according to the specified - * parameters in the timer_oc_init_t. - * @param hperh: TIMER handle - * @param config: TIMER Output Compare configuration structure - * @param ch: TIMER Channels to be enabled - * This parameter can be one of the following values: - * @arg TIMER_CHANNEL_1: TIMER Channel 1 selected - * @arg TIMER_CHANNEL_2: TIMER Channel 2 selected - * @arg TIMER_CHANNEL_3: TIMER Channel 3 selected - * @arg TIMER_CHANNEL_4: TIMER Channel 4 selected - * @retval Status, see @ref ald_status_t. - */ -ald_status_t ald_timer_oc_config_channel(timer_handle_t *hperh, timer_oc_init_t* config, timer_channel_t ch) -{ - assert_param(IS_TIMER_CCX_INSTANCE(hperh->perh, ch)); - assert_param(IS_TIMER_OC_MODE(config->oc_mode)); - assert_param(IS_TIMER_OC_POLARITY(config->oc_polarity)); - - __LOCK(hperh); - hperh->state = TIMER_STATE_BUSY; - - switch (ch) { - case TIMER_CHANNEL_1: - timer_oc1_set_config(hperh->perh, config); - break; - - case TIMER_CHANNEL_2: - timer_oc2_set_config(hperh->perh, config); - break; - - case TIMER_CHANNEL_3: - timer_oc3_set_config(hperh->perh, config); - break; - - case TIMER_CHANNEL_4: - timer_oc4_set_config(hperh->perh, config); - break; - - default: - break; - } - - hperh->state = TIMER_STATE_READY; - __UNLOCK(hperh); - return OK; -} - -/** - * @brief Initializes the TIMER Input Capture Channels according to the specified - * parameters in the timer_ic_init_t. - * @param hperh: TIMER handle - * @param config: TIMER Input Capture configuration structure - * @param ch: TIMER Channels to be enabled - * This parameter can be one of the following values: - * @arg TIMER_CHANNEL_1: TIMER Channel 1 selected - * @arg TIMER_CHANNEL_2: TIMER Channel 2 selected - * @arg TIMER_CHANNEL_3: TIMER Channel 3 selected - * @arg TIMER_CHANNEL_4: TIMER Channel 4 selected - * @retval Status, see @ref ald_status_t. - */ -ald_status_t ald_timer_ic_config_channel(timer_handle_t *hperh, timer_ic_init_t* config, timer_channel_t ch) -{ - assert_param(IS_TIMER_CC2_INSTANCE(hperh->perh)); - assert_param(IS_TIMER_IC_POLARITY(config->polarity)); - assert_param(IS_TIMER_IC_SELECT(config->sel)); - assert_param(IS_TIMER_IC_PSC(config->psc)); - assert_param(IS_TIMER_IC_FILTER(config->filter)); - - __LOCK(hperh); - hperh->state = TIMER_STATE_BUSY; - - switch (ch) { - case TIMER_CHANNEL_1: - timer_ti1_set_config(hperh->perh, config->polarity, config->sel, config->filter); - MODIFY_REG(hperh->perh->CHMR1, TIMER_CHMR1_IC1PRES_MSK, config->psc << TIMER_CHMR1_IC1PRES_POSS); - break; - - case TIMER_CHANNEL_2: - timer_ti2_set_config(hperh->perh, config->polarity, config->sel, config->filter); - MODIFY_REG(hperh->perh->CHMR1, TIMER_CHMR1_IC2PRES_MSK, config->psc << TIMER_CHMR1_IC2PRES_POSS); - break; - - case TIMER_CHANNEL_3: - timer_ti3_set_config(hperh->perh, config->polarity, config->sel, config->filter); - MODIFY_REG(hperh->perh->CHMR2, TIMER_CHMR2_IC3PRES_MSK, config->psc << TIMER_CHMR2_IC3PRES_POSS); - break; - - case TIMER_CHANNEL_4: - timer_ti4_set_config(hperh->perh, config->polarity, config->sel, config->filter); - MODIFY_REG(hperh->perh->CHMR2, TIMER_CHMR2_IC4PRES_MSK, config->psc << TIMER_CHMR2_IC4PRES_POSS); - break; - - default: - break; - } - - hperh->state = TIMER_STATE_READY; - __UNLOCK(hperh); - return OK; -} - -/** - * @brief Initializes the TIMER One Pulse Channels according to the specified - * parameters in the timer_one_pulse_init_t. - * @param hperh: TIMER handle - * @param config: TIMER One Pulse configuration structure - * @param ch_out: TIMER Channels to be enabled - * This parameter can be one of the following values: - * @arg TIMER_CHANNEL_1: TIMER Channel 1 selected - * @arg TIMER_CHANNEL_2: TIMER Channel 2 selected - * @param ch_in: TIMER Channels to be enabled - * This parameter can be one of the following values: - * @arg TIMER_CHANNEL_1: TIMER Channel 1 selected - * @arg TIMER_CHANNEL_2: TIMER Channel 2 selected - * @retval Status, see @ref ald_status_t. - */ -ald_status_t ald_timer_one_pulse_config_channel(timer_handle_t *hperh, timer_one_pulse_init_t *config, - timer_channel_t ch_out, timer_channel_t ch_in) -{ - timer_oc_init_t tmp; - - assert_param(IS_TIMER_CC2_INSTANCE(hperh->perh)); - assert_param(IS_TIMER_OC_MODE(config->mode)); - assert_param(IS_TIMER_OC_POLARITY(config->oc_polarity)); - assert_param(IS_TIMER_OCN_POLARITY(config->ocn_polarity)); - assert_param(IS_TIMER_OCIDLE_STATE(config->oc_idle)); - assert_param(IS_TIMER_OCNIDLE_STATE(config->ocn_idle)); - assert_param(IS_TIMER_IC_POLARITY(config->polarity)); - assert_param(IS_TIMER_IC_SELECT(config->sel)); - assert_param(IS_TIMER_IC_FILTER(config->filter)); - - if (ch_out == ch_in) - return ERROR; - - __LOCK(hperh); - hperh->state = TIMER_STATE_BUSY; - - tmp.oc_mode = config->mode; - tmp.pulse = config->pulse; - tmp.oc_polarity = config->oc_polarity; - tmp.ocn_polarity = config->ocn_polarity; - tmp.oc_idle = config->oc_idle; - tmp.ocn_idle = config->ocn_idle; - - switch (ch_out) { - case TIMER_CHANNEL_1: - timer_oc1_set_config(hperh->perh, &tmp); - break; - case TIMER_CHANNEL_2: - timer_oc2_set_config(hperh->perh, &tmp); - break; - default: - break; - } - - switch (ch_in) { - case TIMER_CHANNEL_1: - timer_ti1_set_config(hperh->perh, config->polarity, config->sel, config->filter); - CLEAR_BIT(hperh->perh->CHMR1, TIMER_CHMR1_IC1PRES_MSK); - MODIFY_REG(hperh->perh->SMCON, TIMER_SMCON_TSSEL_MSK, TIMER_TS_TI1FP1 << TIMER_SMCON_TSSEL_POSS); - MODIFY_REG(hperh->perh->SMCON, TIMER_SMCON_SMODS_MSK, TIMER_MODE_TRIG << TIMER_SMCON_SMODS_POSS); - break; - - case TIMER_CHANNEL_2: - timer_ti2_set_config(hperh->perh, config->polarity, config->sel, config->filter); - CLEAR_BIT(hperh->perh->CHMR1, TIMER_CHMR1_IC2PRES_MSK); - MODIFY_REG(hperh->perh->SMCON, TIMER_SMCON_TSSEL_MSK, TIMER_TS_TI2FP2 << TIMER_SMCON_TSSEL_POSS); - MODIFY_REG(hperh->perh->SMCON, TIMER_SMCON_SMODS_MSK, TIMER_MODE_TRIG << TIMER_SMCON_SMODS_POSS); - break; - default: - break; - } - - hperh->state = TIMER_STATE_READY; - __UNLOCK(hperh); - return OK; -} - -/** - * @brief Configures the OCRef clear feature - * @param hperh: TIMER handle - * @param config: pointer to a TIMER_ClearInputConfigTypeDef structure that - * contains the OCREF clear feature and parameters for the TIMER peripheral. - * @param ch: specifies the TIMER Channel - * This parameter can be one of the following values: - * @arg TIMER_CHANNEL_1: TIMER Channel 1 - * @arg TIMER_CHANNEL_2: TIMER Channel 2 - * @arg TIMER_CHANNEL_3: TIMER Channel 3 - * @arg TIMER_CHANNEL_4: TIMER Channel 4 - * @retval Status, see @ref ald_status_t. - */ -ald_status_t ald_timer_config_oc_ref_clear(timer_handle_t *hperh, timer_clear_input_config_t *config, timer_channel_t ch) -{ - assert_param(IS_TIMER_CC2_INSTANCE(hperh->perh)); - assert_param(IS_FUNC_STATE(config->state)); - assert_param(IS_TIMER_CLEAR_INPUT_SOURCE(config->source)); - assert_param(IS_TIMER_CLEAR_INPUT_POLARITY(config->polarity)); - assert_param(IS_TIMER_ETR_PSC(config->psc)); - assert_param(IS_TIMER_IC_FILTER(config->filter)); - - if (config->source == TIMER_INPUT_NONE) { - timer_etr_set_config(hperh->perh, TIMER_ETR_PSC_DIV1, TIMER_CLK_POLARITY_NO_INV, 0); - } - else { - timer_etr_set_config(hperh->perh, config->psc, - (timer_clock_polarity_t)config->polarity, config->filter); - } - - switch (ch) { - case TIMER_CHANNEL_1: - MODIFY_REG(hperh->perh->CHMR1, TIMER_CHMR1_CH1OCLREN_MSK, config->state << TIMER_CHMR1_CH1OCLREN_POS); - break; - - case TIMER_CHANNEL_2: - MODIFY_REG(hperh->perh->CHMR1, TIMER_CHMR1_CH2OCLREN_MSK, config->state << TIMER_CHMR1_CH2OCLREN_POS); - break; - - case TIMER_CHANNEL_3: - assert_param(IS_TIMER_CC4_INSTANCE(hperh->perh)); - MODIFY_REG(hperh->perh->CHMR2, TIMER_CHMR2_CH3OCLREN_MSK, config->state << TIMER_CHMR2_CH3OCLREN_POS); - break; - - case TIMER_CHANNEL_4: - assert_param(IS_TIMER_CC4_INSTANCE(hperh->perh)); - MODIFY_REG(hperh->perh->CHMR2, TIMER_CHMR2_CH4OCLREN_MSK, config->state << TIMER_CHMR2_CH4OCLREN_POS); - break; - - default: - break; - } - - return OK; -} - -/** - * @brief Configures the clock source to be used - * @param hperh: TIMER handle - * @param config: pointer to a timer_clock_config_t structure that - * contains the clock source information for the TIMER peripheral. - * @retval Status, see @ref ald_status_t. - */ -ald_status_t ald_timer_config_clock_source(timer_handle_t *hperh, timer_clock_config_t *config) -{ - assert_param(IS_TIMER_INSTANCE(hperh->perh)); - assert_param(IS_TIMER_CLOCK_SOURCE(config->source)); - assert_param(IS_TIMER_CLOCK_POLARITY(config->polarity)); - assert_param(IS_TIMER_ETR_PSC(config->psc)); - assert_param(IS_TIMER_IC_FILTER(config->filter)); - - __LOCK(hperh); - hperh->state = TIMER_STATE_BUSY; - WRITE_REG(hperh->perh->SMCON, 0x0); - - switch (config->source) { - case TIMER_SRC_INTER: - CLEAR_BIT(hperh->perh->SMCON, TIMER_SMCON_SMODS_MSK); - break; - - case TIMER_SRC_ETRMODE1: - timer_etr_set_config(hperh->perh, config->psc, config->polarity, config->filter); - MODIFY_REG(hperh->perh->SMCON, TIMER_SMCON_TSSEL_MSK, TIMER_TS_ETRF << TIMER_SMCON_TSSEL_POSS); - MODIFY_REG(hperh->perh->SMCON, TIMER_SMCON_SMODS_MSK, TIMER_MODE_EXTERNAL1 << TIMER_SMCON_SMODS_POSS); - break; - - case TIMER_SRC_ETRMODE2: - timer_etr_set_config(hperh->perh, config->psc, config->polarity, config->filter); - SET_BIT(hperh->perh->SMCON, TIMER_SMCON_ECM2EN_MSK); - break; - - case TIMER_SRC_TI1: - timer_ti1_set_config_stage(hperh->perh, (timer_ic_polarity_t)config->polarity, config->filter); - MODIFY_REG(hperh->perh->SMCON, TIMER_SMCON_TSSEL_MSK, TIMER_TS_TI1FP1 << TIMER_SMCON_TSSEL_POSS); - MODIFY_REG(hperh->perh->SMCON, TIMER_SMCON_SMODS_MSK, TIMER_MODE_EXTERNAL1 << TIMER_SMCON_SMODS_POSS); - break; - - case TIMER_SRC_TI2: - timer_ti2_set_config_stage(hperh->perh, (timer_ic_polarity_t)config->polarity, config->filter); - MODIFY_REG(hperh->perh->SMCON, TIMER_SMCON_TSSEL_MSK, TIMER_TS_TI2FP2 << TIMER_SMCON_TSSEL_POSS); - MODIFY_REG(hperh->perh->SMCON, TIMER_SMCON_SMODS_MSK, TIMER_MODE_EXTERNAL1 << TIMER_SMCON_SMODS_POSS); - break; - - case TIMER_SRC_TI1ED: - timer_ti1_set_config_stage(hperh->perh, (timer_ic_polarity_t)config->polarity, config->filter); - MODIFY_REG(hperh->perh->SMCON, TIMER_SMCON_TSSEL_MSK, TIMER_TS_TI1F_ED << TIMER_SMCON_TSSEL_POSS); - MODIFY_REG(hperh->perh->SMCON, TIMER_SMCON_SMODS_MSK, TIMER_MODE_EXTERNAL1 << TIMER_SMCON_SMODS_POSS); - break; - - case TIMER_SRC_ITR0: - MODIFY_REG(hperh->perh->SMCON, TIMER_SMCON_TSSEL_MSK, TIMER_TS_ITR0 << TIMER_SMCON_TSSEL_POSS); - MODIFY_REG(hperh->perh->SMCON, TIMER_SMCON_SMODS_MSK, TIMER_MODE_EXTERNAL1 << TIMER_SMCON_SMODS_POSS); - break; - - case TIMER_SRC_ITR1: - MODIFY_REG(hperh->perh->SMCON, TIMER_SMCON_TSSEL_MSK, TIMER_TS_ITR1 << TIMER_SMCON_TSSEL_POSS); - MODIFY_REG(hperh->perh->SMCON, TIMER_SMCON_SMODS_MSK, TIMER_MODE_EXTERNAL1 << TIMER_SMCON_SMODS_POSS); - break; - - case TIMER_SRC_ITR2: - MODIFY_REG(hperh->perh->SMCON, TIMER_SMCON_TSSEL_MSK, TIMER_TS_ITR2 << TIMER_SMCON_TSSEL_POSS); - MODIFY_REG(hperh->perh->SMCON, TIMER_SMCON_SMODS_MSK, TIMER_MODE_EXTERNAL1 << TIMER_SMCON_SMODS_POSS); - break; - - case TIMER_SRC_ITR3: - MODIFY_REG(hperh->perh->SMCON, TIMER_SMCON_TSSEL_MSK, TIMER_TS_ITR3 << TIMER_SMCON_TSSEL_POSS); - MODIFY_REG(hperh->perh->SMCON, TIMER_SMCON_SMODS_MSK, TIMER_MODE_EXTERNAL1 << TIMER_SMCON_SMODS_POSS); - break; - default: - break; - } - - hperh->state = TIMER_STATE_READY; - __UNLOCK(hperh); - return OK; -} - -/** - * @brief Selects the signal connected to the TI1 input: direct from CH1_input - * or a XOR combination between CH1_input, CH2_input & CH3_input - * @param hperh: TIMER handle. - * @param ti1_select: Indicate whether or not channel 1 is connected to the - * output of a XOR gate. - * This parameter can be one of the following values: - * @arg 0: The TIMERx_CH1 pin is connected to TI1 input - * @arg 1: The TIMERx_CH1, CH2 and CH3 - * pins are connected to the TI1 input (XOR combination) - * @retval Status, see @ref ald_status_t. - */ -ald_status_t ald_timer_config_ti1_input(timer_handle_t *hperh, uint32_t ti1_select) -{ - assert_param(IS_TIMER_INSTANCE(hperh->perh)); - - MODIFY_REG(hperh->perh->CON2, TIMER_CON2_I1FSEL_MSK, ti1_select << TIMER_CON2_I1FSEL_POS); - return OK; -} - -/** - * @brief Configures the TIMER in Slave mode - * @param hperh: TIMER handle. - * @param config: pointer to a timer_slave_config_t structure that - * contains the selected trigger (internal trigger input, filtered - * timerer input or external trigger input) and the Slave - * mode (Disable, Reset, Gated, Trigger, External clock mode 1). - * @retval Status, see @ref ald_status_t. - */ -ald_status_t ald_timer_slave_config_sync(timer_handle_t *hperh, timer_slave_config_t *config) -{ - assert_param(IS_TIMER_INSTANCE(hperh->perh)); - assert_param(IS_TIMER_SLAVE_MODE(config->mode)); - assert_param(IS_TIMER_TS(config->input)); - assert_param(IS_TIMER_CLOCK_POLARITY(config->polarity)); - assert_param(IS_TIMER_ETR_PSC(config->psc)); - assert_param(IS_TIMER_IC_FILTER(config->filter)); - - __LOCK(hperh); - hperh->state = TIMER_STATE_BUSY; - - timer_slave_set_config(hperh, config); - ald_timer_interrupt_config(hperh, TIMER_IT_TRIGGER, DISABLE); - ald_timer_dma_req_config(hperh, TIMER_DMA_TRIGGER, DISABLE); - - hperh->state = TIMER_STATE_READY; - __UNLOCK(hperh); - return OK; -} - -/** - * @brief Configures the TIMER in Slave mode in interrupt mode - * @param hperh: TIMER handle. - * @param config: pointer to a timer_slave_config_t structure that - * contains the selected trigger (internal trigger input, filtered - * timerer input or external trigger input) and the ) and the Slave - * mode (Disable, Reset, Gated, Trigger, External clock mode 1). - * @retval Status, see @ref ald_status_t. - */ -ald_status_t ald_timer_slave_config_sync_by_it(timer_handle_t *hperh, timer_slave_config_t *config) -{ - assert_param(IS_TIMER_INSTANCE(hperh->perh)); - assert_param(IS_TIMER_SLAVE_MODE(config->mode)); - assert_param(IS_TIMER_TS(config->input)); - assert_param(IS_TIMER_CLOCK_POLARITY(config->polarity)); - assert_param(IS_TIMER_ETR_PSC(config->psc)); - assert_param(IS_TIMER_IC_FILTER(config->filter)); - - __LOCK(hperh); - hperh->state = TIMER_STATE_BUSY; - - timer_slave_set_config(hperh, config); - ald_timer_interrupt_config(hperh, TIMER_IT_TRIGGER, ENABLE); - ald_timer_dma_req_config(hperh, TIMER_DMA_TRIGGER, DISABLE); - - hperh->state = TIMER_STATE_READY; - __UNLOCK(hperh); - return OK; -} - -/** - * @brief Generate a software event - * @param hperh: TIMER handle - * @param event: specifies the event source. - * @retval Status, see @ref ald_status_t. - */ -ald_status_t ald_timer_generate_event(timer_handle_t *hperh, timer_event_source_t event) -{ - assert_param(IS_TIMER_INSTANCE(hperh->perh)); - assert_param(IS_TIMER_EVENT_SOURCE(event)); - - __LOCK(hperh); - hperh->state = TIMER_STATE_BUSY; - WRITE_REG(hperh->perh->SGE, event); - hperh->state = TIMER_STATE_READY; - __UNLOCK(hperh); - - return OK; -} - -/** - * @brief Read the captured value from Capture Compare unit - * @param hperh: TIMER handle. - * @param ch: TIMER Channels to be enabled - * This parameter can be one of the following values: - * @arg TIMER_CHANNEL_1 : TIMER Channel 1 selected - * @arg TIMER_CHANNEL_2 : TIMER Channel 2 selected - * @arg TIMER_CHANNEL_3 : TIMER Channel 3 selected - * @arg TIMER_CHANNEL_4 : TIMER Channel 4 selected - * @retval Captured value - */ -uint32_t ald_timer_read_capture_value(timer_handle_t *hperh, timer_channel_t ch) -{ - uint32_t tmp; - - __LOCK(hperh); - hperh->state = TIMER_STATE_BUSY; - - switch (ch) { - case TIMER_CHANNEL_1: - tmp = hperh->perh->CCVAL1; - break; - case TIMER_CHANNEL_2: - tmp = hperh->perh->CCVAL2; - break; - case TIMER_CHANNEL_3: - tmp = hperh->perh->CCVAL3; - break; - case TIMER_CHANNEL_4: - tmp = hperh->perh->CCVAL4; - break; - default: - tmp = hperh->perh->CCVAL1; - break; - } - - hperh->state = TIMER_STATE_READY; - __UNLOCK(hperh); - return tmp; -} - -/** - * @brief Sets TIMER output mode. - * @param hperh: TIMER handle. - * @param mode: TIMER output mode. - * @param ch: TIMER Channels. - * This parameter can be one of the following values: - * @arg TIMER_CHANNEL_1 : TIMER Channel 1 selected - * @arg TIMER_CHANNEL_2 : TIMER Channel 2 selected - * @arg TIMER_CHANNEL_3 : TIMER Channel 3 selected - * @arg TIMER_CHANNEL_4 : TIMER Channel 4 selected - * @retval None - */ -void ald_timer_set_output_mode(timer_handle_t *hperh, timer_oc_mode_t mode, timer_channel_t ch) -{ - assert_param(IS_TIMER_CC2_INSTANCE(hperh->perh)); - assert_param(IS_TIMER_OC_MODE(mode)); - assert_param(IS_TIMER_CHANNELS(ch)); - - switch (ch) { - case TIMER_CHANNEL_1: - MODIFY_REG(hperh->perh->CHMR1, TIMER_CHMR1_CH1OMOD_MSK, mode << TIMER_CHMR1_CH1OMOD_POSS); - break; - case TIMER_CHANNEL_2: - MODIFY_REG(hperh->perh->CHMR1, TIMER_CHMR1_CH2OMOD_MSK, mode << TIMER_CHMR1_CH2OMOD_POSS); - break; - case TIMER_CHANNEL_3: - MODIFY_REG(hperh->perh->CHMR2, TIMER_CHMR2_CH3OMOD_MSK, mode << TIMER_CHMR2_CH3OMOD_POSS); - break; - case TIMER_CHANNEL_4: - MODIFY_REG(hperh->perh->CHMR2, TIMER_CHMR2_CH4OMOD_MSK, mode << TIMER_CHMR2_CH4OMOD_POSS); - break; - default: - break; - } - - return; -} - -/** - * @brief Configure the channel in commutation event. - * @param hperh: TIMER handel - * @param config: Parameters of the channel. - * @retval None - */ -void ald_timer_com_change_config(timer_handle_t *hperh, timer_com_channel_config_t *config) -{ - uint32_t cm1, cm2, cce; - - assert_param(IS_TIMER_COM_EVENT_INSTANCE(hperh->perh)); - assert_param(IS_FUNC_STATE(config->ch[0].en)); - assert_param(IS_FUNC_STATE(config->ch[0].n_en)); - assert_param(IS_TIMER_OC_MODE(config->ch[0].mode)); - assert_param(IS_FUNC_STATE(config->ch[1].en)); - assert_param(IS_FUNC_STATE(config->ch[1].n_en)); - assert_param(IS_TIMER_OC_MODE(config->ch[1].mode)); - assert_param(IS_FUNC_STATE(config->ch[2].en)); - assert_param(IS_FUNC_STATE(config->ch[2].n_en)); - assert_param(IS_TIMER_OC_MODE(config->ch[2].mode)); - - TIMER_MOE_DISABLE(hperh); - TIMER_DISABLE(hperh); - - cm1 = hperh->perh->CHMR1; - cm2 = hperh->perh->CHMR2; - cce = hperh->perh->CCEP; - - MODIFY_REG(cm1, (0x7 << 4), (config->ch[0].mode << 4)); - MODIFY_REG(cm1, (0x7 << 12), (config->ch[1].mode << 12)); - MODIFY_REG(cm2, (0x7 << 4), (config->ch[2].mode << 4)); - MODIFY_REG(cce, (0x1 << 0), (config->ch[0].en << 0)); - MODIFY_REG(cce, (0x1 << 2), (config->ch[0].n_en << 2)); - MODIFY_REG(cce, (0x1 << 4), (config->ch[1].en << 4)); - MODIFY_REG(cce, (0x1 << 6), (config->ch[1].n_en << 6)); - MODIFY_REG(cce, (0x1 << 8), (config->ch[2].en << 8)); - MODIFY_REG(cce, (0x1 << 10), (config->ch[2].n_en << 10)); - - WRITE_REG(hperh->perh->CHMR1, cm1); - WRITE_REG(hperh->perh->CHMR2, cm2); - WRITE_REG(hperh->perh->CCEP, cce); - - TIMER_MOE_ENABLE(hperh); - TIMER_ENABLE(hperh); - return; -} - -/** - * @brief Configure the TIMER commutation event sequence. - * @param hperh: TIMER handel - * @param ts: the internal trigger corresponding to the timerer interfacing - * with the hall sensor. - * This parameter can be one of the following values: - * @arg TIMER_TS_ITR0 - * @arg TIMER_TS_ITR1 - * @arg TIMER_TS_ITR2 - * @arg TIMER_TS_ITR3 - * @param trgi: the commutation event source. - * This parameter can be one of the following values: - * @arg ENABLE: Commutation event source is TRGI - * @arg DISABLE: Commutation event source is set by software using the COMG bit - * @retval None - */ -void ald_timer_com_event_config(timer_handle_t *hperh, timer_ts_t ts, type_func_t trgi) -{ - assert_param(IS_TIMER_COM_EVENT_INSTANCE(hperh->perh)); - assert_param(IS_TIMER_TS(ts)); - assert_param(IS_FUNC_STATE(trgi)); - - MODIFY_REG(hperh->perh->SMCON, TIMER_SMCON_TSSEL_MSK, ts << TIMER_SMCON_TSSEL_POSS); - SET_BIT(hperh->perh->CON2, TIMER_CON2_CCPCEN_MSK); - MODIFY_REG(hperh->perh->CON2, TIMER_CON2_CCUSEL_MSK, trgi << TIMER_CON2_CCUSEL_POS); - - return; -} - -/** - * @brief Configure the TIMER commutation event sequence with interrupt. - * @param hperh: TIMER handel - * @param ts: the internal trigger corresponding to the timerer interfacing - * with the hall sensor. - * This parameter can be one of the following values: - * @arg TIMER_TS_ITR0 - * @arg TIMER_TS_ITR1 - * @arg TIMER_TS_ITR2 - * @arg TIMER_TS_ITR3 - * @param trgi: the commutation event source. - * This parameter can be one of the following values: - * @arg ENABLE: Commutation event source is TRGI - * @arg DISABLE: Commutation event source is set by software using the COMG bit - * @retval None - */ -void ald_timer_com_event_config_it(timer_handle_t *hperh, timer_ts_t ts, type_func_t trgi) -{ - ald_timer_com_event_config(hperh, ts, trgi); - ald_timer_interrupt_config(hperh, TIMER_IT_COM, ENABLE); -} - -/** - * @brief Configure the break, dead timere, lock level state. - * @param hperh: TIMER handle - * @param config: Pointer to the timer_break_dead_timere_t structure. - * @retval None - */ -void ald_timer_break_dead_time_config(timer_handle_t *hperh, timer_break_dead_time_t *config) -{ - uint32_t tmp; - - assert_param(IS_TIMER_BREAK_INSTANCE(hperh->perh)); - assert_param(IS_FUNC_STATE(config->off_run)); - assert_param(IS_FUNC_STATE(config->off_idle)); - assert_param(IS_TIMER_CLOCK_LEVEL(config->lock_level)); - assert_param(IS_TIMER_DEAD_TIMERE(config->dead_time)); - assert_param(IS_FUNC_STATE(config->break_state)); - assert_param(IS_TIMER_BREAK_POLARITY(config->polarity)); - assert_param(IS_FUNC_STATE(config->auto_out)); - - tmp = READ_REG(hperh->perh->BDCFG); - MODIFY_REG(tmp, TIMER_BDCFG_OFFSSR_MSK, config->off_run << TIMER_BDCFG_OFFSSR_POS); - MODIFY_REG(tmp, TIMER_BDCFG_OFFSSI_MSK, config->off_idle << TIMER_BDCFG_OFFSSI_POS); - MODIFY_REG(tmp, TIMER_BDCFG_LOCKLVL_MSK, config->lock_level << TIMER_BDCFG_LOCKLVL_POSS); - MODIFY_REG(tmp, TIMER_BDCFG_DT_MSK, config->dead_time << TIMER_BDCFG_DT_POSS); - MODIFY_REG(tmp, TIMER_BDCFG_BRKEN_MSK, config->break_state << TIMER_BDCFG_BRKEN_POS); - MODIFY_REG(tmp, TIMER_BDCFG_BRKP_MSK, config->polarity << TIMER_BDCFG_BRKP_POS); - MODIFY_REG(tmp, TIMER_BDCFG_AOEN_MSK, config->auto_out << TIMER_BDCFG_AOEN_POS); - WRITE_REG(hperh->perh->BDCFG, tmp); - - hperh->state = TIMER_STATE_READY; - return; -} - -/** - * @brief Configure the master mode - * @param hperh: TIMER handle - * @param config: Pointer to the timer_master_config_t structure. - * @retval None - */ -void ald_timer_master_sync_config(timer_handle_t *hperh, timer_master_config_t *config) -{ - assert_param(IS_TIMER_INSTANCE(hperh->perh)); - assert_param(IS_TIMER_MASTER_MODE_SEL(config->sel)); - assert_param(IS_FUNC_STATE(config->master_en)); - - hperh->state = TIMER_STATE_BUSY; - MODIFY_REG(hperh->perh->CON2, TIMER_CON2_TRGOSEL_MSK, config->sel << TIMER_CON2_TRGOSEL_POSS); - MODIFY_REG(hperh->perh->SMCON, TIMER_SMCON_MSCFG_MSK, config->master_en << TIMER_SMCON_MSCFG_POS); - hperh->state = TIMER_STATE_READY; - - return; -} - -/** - * @brief This function handles TIMER interrupts requests. - * @param hperh: TIMER handle - * @retval None - */ -void ald_timer_irq_handler(timer_handle_t *hperh) -{ - uint32_t reg = hperh->perh->IFM; - - /* Capture or compare 1 event */ - if (READ_BIT(reg, TIMER_FLAG_CC1)) { - ald_timer_clear_flag_status(hperh, TIMER_FLAG_CC1); - hperh->ch = TIMER_ACTIVE_CHANNEL_1; - - /* Input capture event */ - if (READ_BIT(hperh->perh->CHMR1, TIMER_CHMR1_CC1SSEL_MSK)) { - if (hperh->capture_cbk) - hperh->capture_cbk(hperh); - } - else { /* Output compare event */ - if (hperh->delay_elapse_cbk) - hperh->delay_elapse_cbk(hperh); - if (hperh->pwm_pulse_finish_cbk) - hperh->pwm_pulse_finish_cbk(hperh); - } - - hperh->ch = TIMER_ACTIVE_CHANNEL_CLEARED; - } - /* Capture or compare 2 event */ - if (READ_BIT(reg, TIMER_FLAG_CC2)) { - ald_timer_clear_flag_status(hperh, TIMER_FLAG_CC2); - hperh->ch = TIMER_ACTIVE_CHANNEL_2; - - /* Input capture event */ - if (READ_BIT(hperh->perh->CHMR1, TIMER_CHMR1_CC2SSEL_MSK)) { - if (hperh->capture_cbk) - hperh->capture_cbk(hperh); - } - else { /* Output compare event */ - if (hperh->delay_elapse_cbk) - hperh->delay_elapse_cbk(hperh); - if (hperh->pwm_pulse_finish_cbk) - hperh->pwm_pulse_finish_cbk(hperh); - } - - hperh->ch = TIMER_ACTIVE_CHANNEL_CLEARED; - } - /* Capture or compare 3 event */ - if (READ_BIT(reg, TIMER_FLAG_CC3)) { - ald_timer_clear_flag_status(hperh, TIMER_FLAG_CC3); - hperh->ch = TIMER_ACTIVE_CHANNEL_3; - - /* Input capture event */ - if (READ_BIT(hperh->perh->CHMR2, TIMER_CHMR2_CC3SSEL_MSK)) { - if (hperh->capture_cbk) - hperh->capture_cbk(hperh); - } - else { /* Output compare event */ - if (hperh->delay_elapse_cbk) - hperh->delay_elapse_cbk(hperh); - if (hperh->pwm_pulse_finish_cbk) - hperh->pwm_pulse_finish_cbk(hperh); - } - - hperh->ch = TIMER_ACTIVE_CHANNEL_CLEARED; - } - /* Capture or compare 4 event */ - if (READ_BIT(reg, TIMER_FLAG_CC4)) { - ald_timer_clear_flag_status(hperh, TIMER_FLAG_CC4); - hperh->ch = TIMER_ACTIVE_CHANNEL_4; - - /* Input capture event */ - if (READ_BIT(hperh->perh->CHMR2, TIMER_CHMR2_CC4SSEL_MSK)) { - if (hperh->capture_cbk) - hperh->capture_cbk(hperh); - } - else { /* Output compare event */ - if (hperh->delay_elapse_cbk) - hperh->delay_elapse_cbk(hperh); - if (hperh->pwm_pulse_finish_cbk) - hperh->pwm_pulse_finish_cbk(hperh); - } - - hperh->ch = TIMER_ACTIVE_CHANNEL_CLEARED; - } - - /* TIMER Update event */ - if (READ_BIT(reg, TIMER_FLAG_UPDATE)) { - ald_timer_clear_flag_status(hperh, TIMER_FLAG_UPDATE); - - if (hperh->period_elapse_cbk) - hperh->period_elapse_cbk(hperh); - } - - /* TIMER Break input event */ - if (READ_BIT(reg, TIMER_FLAG_BREAK)) { - ald_timer_clear_flag_status(hperh, TIMER_FLAG_BREAK); - - if (hperh->break_cbk) - hperh->break_cbk(hperh); - } - - /* TIMER Trigger detection event */ - if (READ_BIT(reg, TIMER_FLAG_TRIGGER)) { - ald_timer_clear_flag_status(hperh, TIMER_FLAG_TRIGGER); - - if (hperh->trigger_cbk) - hperh->trigger_cbk(hperh); - } - - /* TIMER commutation event */ - if (READ_BIT(reg, TIMER_FLAG_COM)) { - ald_timer_clear_flag_status(hperh, TIMER_FLAG_COM); - - if (hperh->com_cbk) - hperh->com_cbk(hperh); - } - - return; -} - -/** - * @brief Configure DMA request source. - * @param hperh: TIMER handle - * @param req: DMA request source. - * @param state: New state of the specified DMA request. - * @retval None - */ -void ald_timer_dma_req_config(timer_handle_t *hperh, timer_dma_req_t req, type_func_t state) -{ - assert_param(IS_TIMER_INSTANCE(hperh->perh)); - assert_param(IS_TIMER_DMA_REQ(req)); - assert_param(IS_FUNC_STATE(state)); - - if (state == ENABLE) - SET_BIT(hperh->perh->DIER, req); - else - SET_BIT(hperh->perh->DIDR, req); - - return; -} - -/** - * @brief Enable/disable the specified TIMER interrupts. - * @param hperh: Pointer to a timer_handle_t structure. - * @param it: Specifies the timer interrupt sources to be enabled or disabled. - * This parameter can be one of the @ref timer_it_t. - * @param state: New state of the specified TIMER interrupts. - * This parameter can be: - * @arg ENABLE - * @arg DISABLE - * @retval None - */ -void ald_timer_interrupt_config(timer_handle_t *hperh, timer_it_t it, type_func_t state) -{ - assert_param(IS_TIMER_INSTANCE(hperh->perh)); - assert_param(IS_TIMER_IT(it)); - assert_param(IS_FUNC_STATE(state)); - - if (state == ENABLE) - SET_BIT(hperh->perh->DIER, it); - else - SET_BIT(hperh->perh->DIDR, it); - - return; -} - -/** - * @brief Get the status of TIMER interrupt source. - * @param hperh: Pointer to a timer_handle_t structure. - * @param it: Specifies the TIMER interrupt source. - * This parameter can be one of the @ref timer_it_t. - * @retval Status: - * - 0: RESET - * - 1: SET - */ -it_status_t ald_timer_get_it_status(timer_handle_t *hperh, timer_it_t it) -{ - assert_param(IS_TIMER_INSTANCE(hperh->perh)); - assert_param(IS_TIMER_IT(it)); - - if (hperh->perh->DIVS & it) - return SET; - - return RESET; -} - -/** - * @brief Get the status of TIMER interrupt flag. - * @param hperh: Pointer to a timer_handle_t structure. - * @param flag: Specifies the TIMER interrupt flag. - * This parameter can be one of the @ref timer_flag_t. - * @retval Status: - * - 0: RESET - * - 1: SET - */ -flag_status_t ald_timer_get_flag_status(timer_handle_t *hperh, timer_flag_t flag) -{ - assert_param(IS_TIMER_INSTANCE(hperh->perh)); - assert_param(IS_TIMER_FLAG(flag)); - - if (hperh->perh->RIF & flag) - return SET; - - return RESET; -} - -/** - * @brief Clear the TIMER interrupt flag. - * @param hperh: Pointer to a uart_handle_t structure. - * @param flag: Specifies the TIMER interrupt flag. - * This parameter can be one of the @ref timer_flag_t. - * @retval None - */ -void ald_timer_clear_flag_status(timer_handle_t *hperh, timer_flag_t flag) -{ - assert_param(IS_TIMER_INSTANCE(hperh->perh)); - assert_param(IS_TIMER_FLAG(flag)); - - hperh->perh->ICR = flag; - return; -} -/** - * @} - */ - -/** @defgroup TIMER_Public_Functions_Group12 Peripheral State functions - * @brief Peripheral State functions - * - * @verbatim - ============================================================================== - ##### Peripheral State functions ##### - ============================================================================== - [..] - This subsection permit to get in run-timere the status of the peripheral - and the data flow. - - @endverbatim - * @{ - */ - -/** - * @brief Return the TIMER Base state - * @param hperh: TIMER handle - * @retval TIMER peripheral state - */ -timer_state_t ald_timer_get_state(timer_handle_t *hperh) -{ - return hperh->state; -} -/** - * @} - */ -/** - * @} - */ - -/** @addtogroup TIMER_Private_Functions - * @{ - */ - -#ifdef ALD_DMA -/** - * @brief TIMER DMA out compare complete callback. - * @param arg: pointer to TIMER handle. - * @retval None - */ -void timer_dma_oc_cplt(void *arg) -{ - timer_handle_t *hperh = (timer_handle_t *)arg; - - if (hperh->delay_elapse_cbk) - hperh->delay_elapse_cbk(hperh); - - if (hperh->pwm_pulse_finish_cbk) - hperh->pwm_pulse_finish_cbk(hperh); - - hperh->ch = TIMER_ACTIVE_CHANNEL_CLEARED; - return; -} - -/** - * @brief TIMER DMA Capture complete callback. - * @param arg: pointer to TIMER handle. - * @retval None - */ -void timer_dma_capture_cplt(void *arg) -{ - timer_handle_t *hperh = (timer_handle_t *)arg; - - if (hperh->capture_cbk) - hperh->capture_cbk(hperh); - - hperh->ch = TIMER_ACTIVE_CHANNEL_CLEARED; - return; -} - -/** - * @brief TIMER DMA Period Elapse complete callback. - * @param arg: pointer to TIMER handle. - * @retval None - */ -void timer_dma_period_elapse_cplt(void *arg) -{ - timer_handle_t *hperh = (timer_handle_t *)arg; - - if (hperh->period_elapse_cbk) - hperh->period_elapse_cbk(hperh); - - hperh->state = TIMER_STATE_READY; - return; -} - -/** - * @brief TIMER DMA error callback - * @param arg: pointer to TIMER handle. - * @retval None - */ -void timer_dma_error(void *arg) -{ - timer_handle_t *hperh = (timer_handle_t *)arg; - - hperh->state = TIMER_STATE_READY; - if (hperh->error_cbk) - hperh->error_cbk(hperh); - - return; -} -#endif - -/** - * @brief Time Base configuration - * @param TIMERx: TIMER periheral - * @param init: TIMER Base configuration structure - * @retval None - */ -static void timer_base_set_config(TIMER_TypeDef *TIMERx, timer_base_init_t *init) -{ - assert_param(IS_TIMER_COUNTER_MODE(init->mode)); - assert_param(IS_TIMER_CLOCK_DIVISION(init->clk_div)); - - if (init->mode == TIMER_CNT_MODE_UP || init->mode == TIMER_CNT_MODE_DOWN) { - CLEAR_BIT(TIMERx->CON1, TIMER_CON1_CMSEL_MSK); - MODIFY_REG(TIMERx->CON1, TIMER_CON1_DIRSEL_MSK, init->mode << TIMER_CON1_DIRSEL_POS); - } - else { - MODIFY_REG(TIMERx->CON1, TIMER_CON1_CMSEL_MSK, (init->mode - 1) << TIMER_CON1_CMSEL_POSS); - } - - if (IS_TIMER_CLOCK_DIVISION_INSTANCE(TIMERx)) - MODIFY_REG(TIMERx->CON1, TIMER_CON1_DFCKSEL_MSK, init->clk_div << TIMER_CON1_DFCKSEL_POSS); - - WRITE_REG(TIMERx->AR, init->period); - WRITE_REG(TIMERx->PRES, init->prescaler); - - if (IS_TIMER_REPETITION_COUNTER_INSTANCE(TIMERx)) - WRITE_REG(TIMERx->REPAR, init->re_cnt); - - return; -} - -/** - * @brief Time Ouput Compare 1 configuration - * @param TIMERx: Select the TIMER peripheral - * @param oc_config: The ouput configuration structure - * @retval None - */ -static void timer_oc1_set_config(TIMER_TypeDef *TIMERx, timer_oc_init_t *oc_config) -{ - CLEAR_BIT(TIMERx->CCEP, TIMER_CCEP_CC1EN_MSK); - CLEAR_BIT(TIMERx->CHMR1, TIMER_CHMR1_CH1OMOD_MSK); - CLEAR_BIT(TIMERx->CHMR1, TIMER_CHMR1_CC1SSEL_MSK); - MODIFY_REG(TIMERx->CHMR1, TIMER_CHMR1_CH1OMOD_MSK, oc_config->oc_mode << TIMER_CHMR1_CH1OMOD_POSS); - MODIFY_REG(TIMERx->CCEP, TIMER_CCEP_CC1POL_MSK, oc_config->oc_polarity << TIMER_CCEP_CC1POL_POS); - - if (IS_TIMER_CCXN_INSTANCE(TIMERx, TIMER_CHANNEL_1)) { - assert_param(IS_TIMER_OCN_POLARITY(oc_config->ocn_polarity)); - MODIFY_REG(TIMERx->CCEP, TIMER_CCEP_CC1NPOL_MSK, oc_config->ocn_polarity << TIMER_CCEP_CC1NPOL_POS); - CLEAR_BIT(TIMERx->CCEP, TIMER_CCEP_CC1NEN_MSK); - } - - if (IS_TIMER_BREAK_INSTANCE(TIMERx)) { - assert_param(IS_TIMER_OCNIDLE_STATE(oc_config->ocn_idle)); - assert_param(IS_TIMER_OCIDLE_STATE(oc_config->oc_idle)); - - MODIFY_REG(TIMERx->CON2, TIMER_CON2_OISS1_MSK, oc_config->oc_idle << TIMER_CON2_OISS1_POS); - MODIFY_REG(TIMERx->CON2, TIMER_CON2_OISS1N_MSK, oc_config->ocn_idle << TIMER_CON2_OISS1N_POS); - } - - WRITE_REG(TIMERx->CCVAL1, oc_config->pulse); -} - -/** - * @brief Time Ouput Compare 2 configuration - * @param TIMERx: Select the TIMER peripheral - * @param oc_config: The ouput configuration structure - * @retval None - */ -static void timer_oc2_set_config(TIMER_TypeDef *TIMERx, timer_oc_init_t *oc_config) -{ - CLEAR_BIT(TIMERx->CCEP, TIMER_CCEP_CC2EN_MSK); - CLEAR_BIT(TIMERx->CHMR1, TIMER_CHMR1_CH2OMOD_MSK); - CLEAR_BIT(TIMERx->CHMR1, TIMER_CHMR1_CC2SSEL_MSK); - MODIFY_REG(TIMERx->CHMR1, TIMER_CHMR1_CH2OMOD_MSK, oc_config->oc_mode << TIMER_CHMR1_CH2OMOD_POSS); - MODIFY_REG(TIMERx->CCEP, TIMER_CCEP_CC2POL_MSK, oc_config->oc_polarity << TIMER_CCEP_CC2POL_POS); - - if (IS_TIMER_CCXN_INSTANCE(TIMERx, TIMER_CHANNEL_2)) { - assert_param(IS_TIMER_OCN_POLARITY(oc_config->ocn_polarity)); - MODIFY_REG(TIMERx->CCEP, TIMER_CCEP_CC2NPOL_MSK, oc_config->ocn_polarity << TIMER_CCEP_CC2NPOL_POS); - CLEAR_BIT(TIMERx->CCEP, TIMER_CCEP_CC2NEN_MSK); - } - - if (IS_TIMER_BREAK_INSTANCE(TIMERx)) { - assert_param(IS_TIMER_OCNIDLE_STATE(oc_config->ocn_idle)); - assert_param(IS_TIMER_OCIDLE_STATE(oc_config->oc_idle)); - - MODIFY_REG(TIMERx->CON2, TIMER_CON2_OISS2_MSK, oc_config->oc_idle << TIMER_CON2_OISS2_POS); - MODIFY_REG(TIMERx->CON2, TIMER_CON2_OISS2N_MSK, oc_config->ocn_idle << TIMER_CON2_OISS2N_POS); - } - - WRITE_REG(TIMERx->CCVAL2, oc_config->pulse); -} - -/** - * @brief Time Ouput Compare 3 configuration - * @param TIMERx: Select the TIMER peripheral - * @param oc_config: The ouput configuration structure - * @retval None - */ -static void timer_oc3_set_config(TIMER_TypeDef *TIMERx, timer_oc_init_t *oc_config) -{ - CLEAR_BIT(TIMERx->CCEP, TIMER_CCEP_CC3EN_MSK); - CLEAR_BIT(TIMERx->CHMR2, TIMER_CHMR2_CH3OMOD_MSK); - CLEAR_BIT(TIMERx->CHMR2, TIMER_CHMR2_CC3SSEL_MSK); - MODIFY_REG(TIMERx->CHMR2, TIMER_CHMR2_CH3OMOD_MSK, oc_config->oc_mode << TIMER_CHMR2_CH3OMOD_POSS); - MODIFY_REG(TIMERx->CCEP, TIMER_CCEP_CC3POL_MSK, oc_config->oc_polarity << TIMER_CCEP_CC3POL_POS); - - if (IS_TIMER_CCXN_INSTANCE(TIMERx, TIMER_CHANNEL_3)) { - assert_param(IS_TIMER_OCN_POLARITY(oc_config->ocn_polarity)); - MODIFY_REG(TIMERx->CCEP, TIMER_CCEP_CC3NPOL_MSK, oc_config->ocn_polarity << TIMER_CCEP_CC3NPOL_POS); - CLEAR_BIT(TIMERx->CCEP, TIMER_CCEP_CC3NEN_MSK); - } - - if (IS_TIMER_BREAK_INSTANCE(TIMERx)) { - assert_param(IS_TIMER_OCNIDLE_STATE(oc_config->ocn_idle)); - assert_param(IS_TIMER_OCIDLE_STATE(oc_config->oc_idle)); - - MODIFY_REG(TIMERx->CON2, TIMER_CON2_OISS3_MSK, oc_config->oc_idle << TIMER_CON2_OISS3_POS); - MODIFY_REG(TIMERx->CON2, TIMER_CON2_OISS3N_MSK, oc_config->ocn_idle << TIMER_CON2_OISS3N_POS); - } - - WRITE_REG(TIMERx->CCVAL3, oc_config->pulse); -} - -/** - * @brief Time Ouput Compare 4 configuration - * @param TIMERx: Select the TIMER peripheral - * @param oc_config: The ouput configuration structure - * @retval None - */ -static void timer_oc4_set_config(TIMER_TypeDef *TIMERx, timer_oc_init_t *oc_config) -{ - CLEAR_BIT(TIMERx->CCEP, TIMER_CCEP_CC4EN_MSK); - CLEAR_BIT(TIMERx->CHMR2, TIMER_CHMR2_CH4OMOD_MSK); - CLEAR_BIT(TIMERx->CHMR2, TIMER_CHMR2_CC4SSEL_MSK); - MODIFY_REG(TIMERx->CHMR2, TIMER_CHMR2_CH4OMOD_MSK, oc_config->oc_mode << TIMER_CHMR2_CH4OMOD_POSS); - MODIFY_REG(TIMERx->CCEP, TIMER_CCEP_CC4POL_MSK, oc_config->oc_polarity << TIMER_CCEP_CC4POL_POS); - - if (IS_TIMER_BREAK_INSTANCE(TIMERx)) { - assert_param(IS_TIMER_OCIDLE_STATE(oc_config->oc_idle)); - MODIFY_REG(TIMERx->CON2, TIMER_CON2_OISS4_MSK, oc_config->oc_idle << TIMER_CON2_OISS4_POS); - } - - WRITE_REG(TIMERx->CCVAL4, oc_config->pulse); -} - -/** - * @brief Enables or disables the TIMER Capture Compare Channel x. - * @param TIMERx: Select the TIMER peripheral - * @param ch: specifies the TIMER Channel - * This parameter can be one of the following values: - * @arg TIMER_CHANNEL_1: TIMER Channel 1 - * @arg TIMER_CHANNEL_2: TIMER Channel 2 - * @arg TIMER_CHANNEL_3: TIMER Channel 3 - * @arg TIMER_CHANNEL_4: TIMER Channel 4 - * @param state: specifies the TIMER Channel CCxE bit new state. - * @retval None - */ -static void timer_ccx_channel_cmd(TIMER_TypeDef* TIMERx, timer_channel_t ch, type_func_t state) -{ - assert_param(IS_TIMER_CC2_INSTANCE(TIMERx)); - assert_param(IS_TIMER_CHANNELS(ch)); - - switch (ch) { - case TIMER_CHANNEL_1: - MODIFY_REG(TIMERx->CCEP, TIMER_CCEP_CC1EN_MSK, state << TIMER_CCEP_CC1EN_POS); - break; - - case TIMER_CHANNEL_2: - MODIFY_REG(TIMERx->CCEP, TIMER_CCEP_CC2EN_MSK, state << TIMER_CCEP_CC2EN_POS); - break; - - case TIMER_CHANNEL_3: - MODIFY_REG(TIMERx->CCEP, TIMER_CCEP_CC3EN_MSK, state << TIMER_CCEP_CC3EN_POS); - break; - - case TIMER_CHANNEL_4: - MODIFY_REG(TIMERx->CCEP, TIMER_CCEP_CC4EN_MSK, state << TIMER_CCEP_CC4EN_POS); - break; - - default: - break; - } -} -/** - * @brief Enables or disables the TIMER Capture Compare Channel xN. - * @param TIMERx: Select the TIMER peripheral - * @param ch: specifies the TIMER Channel - * This parameter can be one of the following values: - * @arg TIMER_CHANNEL_1: TIMER Channel 1 - * @arg TIMER_CHANNEL_2: TIMER Channel 2 - * @arg TIMER_CHANNEL_3: TIMER Channel 3 - * @param state: specifies the TIMER Channel CCxNE bit new state. - * @retval None - */ -static void timer_ccxn_channel_cmd(TIMER_TypeDef* TIMERx, timer_channel_t ch, type_func_t state) -{ - switch (ch) { - case TIMER_CHANNEL_1: - MODIFY_REG(TIMERx->CCEP, TIMER_CCEP_CC1NEN_MSK, state << TIMER_CCEP_CC1NEN_POS); - break; - - case TIMER_CHANNEL_2: - MODIFY_REG(TIMERx->CCEP, TIMER_CCEP_CC2NEN_MSK, state << TIMER_CCEP_CC2NEN_POS); - break; - - case TIMER_CHANNEL_3: - MODIFY_REG(TIMERx->CCEP, TIMER_CCEP_CC3NEN_MSK, state << TIMER_CCEP_CC3NEN_POS); - break; - - default: - break; - } - -} - -/** - * @brief Configure the TI1 as Input. - * @param TIMERx: Select the TIMER peripheral. - * @param polarity: The Input Polarity. - * @param sel: specifies the input to be used. - * @param filter: Specifies the Input Capture Filter. - * This parameter must be a value between 0x00 and 0x0F. - * @retval None - */ -static void timer_ti1_set_config(TIMER_TypeDef *TIMERx, timer_ic_polarity_t polarity, - timer_ic_select_t sel, uint32_t filter) -{ - CLEAR_BIT(TIMERx->CCEP, TIMER_CCEP_CC1EN_MSK); - MODIFY_REG(TIMERx->CHMR1, TIMER_CHMR1_CC1SSEL_MSK, sel << TIMER_CHMR1_CC1SSEL_POSS); - MODIFY_REG(TIMERx->CHMR1, TIMER_CHMR1_I1FLT_MSK, filter << TIMER_CHMR1_I1FLT_POSS); - MODIFY_REG(TIMERx->CCEP, TIMER_CCEP_CC1POL_MSK, polarity << TIMER_CCEP_CC1POL_POS); - - return; -} - -/** - * @brief Configure the Polarity and Filter for TI1. - * @param TIMERx: Select the TIMER peripheral. - * @param polarity: The Input Polarity. - * @param filter: Specifies the Input Capture Filter. - * This parameter must be a value between 0x00 and 0x0F. - * @retval None - */ -static void timer_ti1_set_config_stage(TIMER_TypeDef *TIMERx, timer_ic_polarity_t polarity, uint32_t filter) -{ - MODIFY_REG(TIMERx->CHMR1, TIMER_CHMR1_I1FLT_MSK, filter << TIMER_CHMR1_I1FLT_POSS); - MODIFY_REG(TIMERx->CCEP, TIMER_CCEP_CC1POL_MSK, polarity << TIMER_CCEP_CC1POL_POS); - - - return; -} - -/** - * @brief Configure the TI2 as Input. - * @param TIMERx: Select the TIMER peripheral. - * @param polarity: The Input Polarity. - * @param sel: specifies the input to be used. - * @param filter: Specifies the Input Capture Filter. - * This parameter must be a value between 0x00 and 0x0F. - * @retval None - */ -static void timer_ti2_set_config(TIMER_TypeDef *TIMERx, timer_ic_polarity_t polarity, - timer_ic_select_t sel, uint32_t filter) -{ - CLEAR_BIT(TIMERx->CCEP, TIMER_CCEP_CC2EN_MSK); - MODIFY_REG(TIMERx->CHMR1, TIMER_CHMR1_CC2SSEL_MSK, sel << TIMER_CHMR1_CC2SSEL_POSS); - MODIFY_REG(TIMERx->CHMR1, TIMER_CHMR1_I2FLT_MSK, filter << TIMER_CHMR1_I2FLT_POSS); - MODIFY_REG(TIMERx->CCEP, TIMER_CCEP_CC2POL_MSK, polarity << TIMER_CCEP_CC2POL_POS); - - - return; -} - -/** - * @brief Configure the Polarity and Filter for TI2. - * @param TIMERx: Select the TIMER peripheral. - * @param polarity: The Input Polarity. - * @param filter: Specifies the Input Capture Filter. - * This parameter must be a value between 0x00 and 0x0F. - * @retval None - */ -static void timer_ti2_set_config_stage(TIMER_TypeDef *TIMERx, timer_ic_polarity_t polarity, uint32_t filter) -{ - MODIFY_REG(TIMERx->CHMR1, TIMER_CHMR1_I2FLT_MSK, filter << TIMER_CHMR1_I2FLT_POSS); - MODIFY_REG(TIMERx->CCEP, TIMER_CCEP_CC2POL_MSK, polarity << TIMER_CCEP_CC2POL_POS); - return; -} - -/** - * @brief Configure the TI3 as Input. - * @param TIMERx: Select the TIMER peripheral. - * @param polarity: The Input Polarity. - * @param sel: specifies the input to be used. - * @param filter: Specifies the Input Capture Filter. - * This parameter must be a value between 0x00 and 0x0F. - * @retval None - */ -static void timer_ti3_set_config(TIMER_TypeDef *TIMERx, timer_ic_polarity_t polarity, - timer_ic_select_t sel, uint32_t filter) -{ - CLEAR_BIT(TIMERx->CCEP, TIMER_CCEP_CC3EN_MSK); - MODIFY_REG(TIMERx->CHMR2, TIMER_CHMR2_CC3SSEL_MSK, sel << TIMER_CHMR2_CC3SSEL_POSS); - MODIFY_REG(TIMERx->CHMR2, TIMER_CHMR2_I3FLT_MSK, filter << TIMER_CHMR2_I3FLT_POSS); - MODIFY_REG(TIMERx->CCEP, TIMER_CCEP_CC3POL_MSK, polarity << TIMER_CCEP_CC3POL_POS); - - return; -} - -/** - * @brief Configure the TI4 as Input. - * @param TIMERx: Select the TIMER peripheral. - * @param polarity: The Input Polarity. - * @param sel: specifies the input to be used. - * @param filter: Specifies the Input Capture Filter. - * This parameter must be a value between 0x00 and 0x0F. - * @retval None - */ -static void timer_ti4_set_config(TIMER_TypeDef *TIMERx, timer_ic_polarity_t polarity, - timer_ic_select_t sel, uint32_t filter) -{ - CLEAR_BIT(TIMERx->CCEP, TIMER_CCEP_CC4EN_MSK); - MODIFY_REG(TIMERx->CHMR2, TIMER_CHMR2_CC4SSEL_MSK, sel << TIMER_CHMR2_CC4SSEL_POSS); - MODIFY_REG(TIMERx->CHMR2, TIMER_CHMR2_I4FLT_MSK, filter << TIMER_CHMR2_I4FLT_POSS); - MODIFY_REG(TIMERx->CCEP, TIMER_CCEP_CC4POL_MSK, polarity << TIMER_CCEP_CC4POL_POS); - return; -} - -/** - * @brief Configures the TIMERx External Trigger (ETR). - * @param TIMERx: Select the TIMER peripheral - * @param psc: The external Trigger Prescaler. - * @param polarity: The external Trigger Polarity. - * @param filter: External Trigger Filter. - * This parameter must be a value between 0x00 and 0x0F - * @retval None - */ -static void timer_etr_set_config(TIMER_TypeDef* TIMERx, timer_etr_psc_t psc, timer_clock_polarity_t polarity, uint32_t filter) -{ - MODIFY_REG(TIMERx->SMCON, TIMER_SMCON_ETFLT_MSK, filter << TIMER_SMCON_ETFLT_POSS); - MODIFY_REG(TIMERx->SMCON, TIMER_SMCON_ETPSEL_MSK, psc << TIMER_SMCON_ETPSEL_POSS); - CLEAR_BIT(TIMERx->SMCON, TIMER_SMCON_ECM2EN_MSK); - MODIFY_REG(TIMERx->SMCON, TIMER_SMCON_ETPOL_MSK, polarity << TIMER_SMCON_ETPOL_POS); - return; -} - -/** - * @brief Time Slave configuration - * @param hperh: pointer to a timer_handle_t structure that contains - * the configuration information for TIMER module. - * @param config: The slave configuration structure - * @retval None - */ -static void timer_slave_set_config(timer_handle_t *hperh, timer_slave_config_t *config) -{ - MODIFY_REG(hperh->perh->SMCON, TIMER_SMCON_TSSEL_MSK, config->input << TIMER_SMCON_TSSEL_POSS); - MODIFY_REG(hperh->perh->SMCON, TIMER_SMCON_SMODS_MSK, config->mode << TIMER_SMCON_SMODS_POSS); - - switch (config->input) { - case TIMER_TS_ETRF: - timer_etr_set_config(hperh->perh, config->psc, config->polarity, config->filter); - break; - - case TIMER_TS_TI1F_ED: - CLEAR_BIT(hperh->perh->CCEP, TIMER_CCEP_CC1EN_MSK); - MODIFY_REG(hperh->perh->CHMR1, TIMER_CHMR1_I1FLT_MSK, config->filter << TIMER_CHMR1_I1FLT_POSS); - break; - - case TIMER_TS_TI1FP1: - timer_ti1_set_config_stage(hperh->perh, (timer_ic_polarity_t)config->polarity, config->filter); - break; - - case TIMER_TS_TI2FP2: - timer_ti2_set_config_stage(hperh->perh, (timer_ic_polarity_t)config->polarity, config->filter); - break; - - default: - break; - } -} - -#ifdef ALD_DMA - -/** - * @brief Timer DMA msel signal configuration - * @param hperh: pointer to a timer_handle_t structure that contains - * the configuration information for TIMER module. - * @param config: DMA configuration structure - * @retval None - */ -static void timer_dma_msel(TIMER_TypeDef *hperh, dma_config_t *config) -{ - #if defined (ES32F065x) - if (hperh == AD16C4T0) - config->msel = DMA_MSEL_TIMER0; - if (hperh == GP16C4T0) - config->msel = DMA_MSEL_TIMER6; - #elif defined (ES32F033x) || defined (ES32F093x) - if (hperh == GP16C4T0) - config->msel = DMA_MSEL_TIMER0; - if (hperh == GP16C4T1) - config->msel = DMA_MSEL_TIMER6; - #endif - - if (hperh == GP16C2T0) - config->msel = DMA_MSEL_TIMER2; - if (hperh == GP16C2T1) - config->msel = DMA_MSEL_TIMER3; - if (hperh == BS16T0) - config->msel = DMA_MSEL_TIMER1; - if (hperh == BS16T1) - config->msel = DMA_MSEL_TIMER4; - if (hperh == BS16T2) - config->msel = DMA_MSEL_TIMER5; - if (hperh == BS16T3) - config->msel = DMA_MSEL_TIMER7; -} - -#endif - -/** - * @} - */ -#endif /* ALD_TIMER */ -/** - * @} - */ -/** - * @} - */ diff --git a/bsp/essemi/es32f0334/libraries/ES32F033x_ALD_StdPeriph_Driver/Source/ald_trng.c b/bsp/essemi/es32f0334/libraries/ES32F033x_ALD_StdPeriph_Driver/Source/ald_trng.c deleted file mode 100644 index 8e4d13a4d0..0000000000 --- a/bsp/essemi/es32f0334/libraries/ES32F033x_ALD_StdPeriph_Driver/Source/ald_trng.c +++ /dev/null @@ -1,309 +0,0 @@ -/** - ********************************************************************************* - * - * @file ald_trng.c - * @brief TRNG module driver. - * - * @version V1.0 - * @date 04 Dec 2017 - * @author AE Team - * @note - * - * Copyright (C) Shanghai Eastsoft Microelectronics Co. Ltd. All rights reserved. - * - ********************************************************************************* - */ - -#include "ald_trng.h" - - -/** @addtogroup ES32FXXX_ALD - * @{ - */ - -/** @defgroup TRNG TRNG - * @brief TRNG module driver - * @{ - */ -#ifdef ALD_TRNG - -/** @addtogroup CRYPT_Private_Functions CRYPT Private Functions - * @{ - */ -void trng_reset(trng_handle_t *hperh); -/** - * @} - */ - -/** @defgroup TRNG_Public_Functions TRNG Public Functions - * @{ - */ - -/** @addtogroup TRNG_Public_Functions_Group1 Initialization functions - * @brief Initialization functions - * - * @verbatim - ============================================================================== - ##### Initialization functions ##### - ============================================================================== - [..] This section provides functions allowing to initialize the TRNG: - (+) This parameters can be configured: - (++) Word Width - (++) Seed Type - (++) Seed - (++) Start Time - (++) Adjust parameter - - @endverbatim - * @{ - */ - - -/** - * @brief Initializes the TRNG according to the specified - * parameters in the trng_init_t. - * @param hperh: Pointer to a trng_handle_t structure that contains - * the configuration information for the specified TRNG module. - * @retval Status, see @ref ald_status_t. - */ -ald_status_t ald_trng_init(trng_handle_t *hperh) -{ - uint32_t tmp = 0; - - if (hperh == NULL) - return ERROR; - - assert_param(IS_TRNG_DATA_WIDTH(hperh->init.data_width)); - assert_param(IS_TRNG_SEED_TYPE(hperh->init.seed_type)); - assert_param(IS_TRNG_ADJC(hperh->init.adjc)); - assert_param(IS_FUNC_STATE(hperh->init.posten)); - assert_param(IS_TRNG_T_START(hperh->init.t_start)); - - __LOCK(hperh); - trng_reset(hperh); - - if (hperh->state == TRNG_STATE_RESET) - __UNLOCK(hperh); - - tmp = TRNG->CR; - - if (hperh->init.adjc == 0) - tmp = (0 << TRNG_CR_ADJM_POS); - else - tmp = (1 << TRNG_CR_ADJM_POS); - - tmp |= ((1 << TRNG_CR_TRNGSEL_POS) | (hperh->init.data_width << TRNG_CR_DSEL_POSS) | - (hperh->init.seed_type << TRNG_CR_SDSEL_POSS) | (hperh->init.adjc << TRNG_CR_ADJC_POSS) | - (hperh->init.posten << TRNG_CR_POSTEN_MSK)); - - TRNG->CR = tmp; - - WRITE_REG(TRNG->SEED, hperh->init.seed); - MODIFY_REG(TRNG->CFGR, TRNG_CFGR_TSTART_MSK, (hperh->init.t_start) << TRNG_CFGR_TSTART_POSS); - - hperh->state = TRNG_STATE_READY; - __UNLOCK(hperh); - return OK; -} -/** - * @} - */ - -/** @addtogroup TRNG_Public_Functions_Group2 Peripheral Control functions - * @brief Peripheral Control functions - * - * @verbatim - ============================================================================== - ##### Peripheral Control functions ##### - ============================================================================== - [..] This section provides functions allowing to: - (+) ald_trng_get_result() API can Get the result. - (+) ald_trng_interrupt_config() API can be helpful to configure TRNG interrupt source. - (+) ald_trng_get_it_status() API can get the status of interrupt source. - (+) ald_trng_get_status() API can get the status of SR register. - (+) ald_trng_get_flag_status() API can get the status of interrupt flag. - (+) ald_trng_clear_flag_status() API can clear interrupt flag. - - @endverbatim - * @{ - */ - -/** - * @brief Get the result. - * @param hperh: Pointer to a trng_handle_t structure that contains - * the configuration information for the specified TRNG module. - * @retval The resultl - */ -uint32_t ald_trng_get_result(trng_handle_t *hperh) -{ - hperh->state = TRNG_STATE_READY; - hperh->data = hperh->perh->DR; - return (uint32_t)hperh->perh->DR; -} - -/** - * @brief Enable/disable the specified interrupts. - * @param hperh: Pointer to a trng_handle_t structure that contains - * the configuration information for the specified TRNG module. - * @param it: Specifies the interrupt sources to be enabled or disabled. - * This parameter can be one of the @ref trng_it_t. - * @param state: New state of the specified interrupts. - * This parameter can be: - * @arg ENABLE - * @arg DISABLE - * @retval None - */ -void ald_trng_interrupt_config(trng_handle_t *hperh, trng_it_t it, type_func_t state) -{ - assert_param(IS_TRNG_IT(it)); - assert_param(IS_FUNC_STATE(state)); - - if (state) - SET_BIT(hperh->perh->IER, it); - else - CLEAR_BIT(hperh->perh->IER, it); - - return; -} - -/** - * @brief Get the status of SR register. - * @param hperh: Pointer to a trng_handle_t structure that contains - * the configuration information for the specified TRNG module. - * @param status: Specifies the TRNG status type. - * This parameter can be one of the @ref trng_status_t. - * @retval Status: - * - 0: RESET - * - 1: SET - */ -flag_status_t ald_trng_get_status(trng_handle_t *hperh, trng_status_t status) -{ - assert_param(IS_TRNG_STATUS(status)); - - if (READ_BIT(hperh->perh->SR, status)) - return SET; - - return RESET; -} - -/** - * @brief Get the status of interrupt source. - * @param hperh: Pointer to a trng_handle_t structure that contains - * the configuration information for the specified TRNG module. - * @param it: Specifies the interrupt source. - * This parameter can be one of the @ref trng_it_t. - * @retval Status: - * - 0: RESET - * - 1: SET - */ -it_status_t ald_trng_get_it_status(trng_handle_t *hperh, trng_it_t it) -{ - assert_param(IS_TRNG_IT(it)); - - if (READ_BIT(hperh->perh->IER, it)) - return SET; - - return RESET; -} - -/** - * @brief Get the status of interrupt flag. - * @param hperh: Pointer to a trng_handle_t structure that contains - * the configuration information for the specified TRNG module. - * @param flag: Specifies the interrupt flag. - * This parameter can be one of the @ref trng_flag_t. - * @retval Status: - * - 0: RESET - * - 1: SET - */ -flag_status_t ald_trng_get_flag_status(trng_handle_t *hperh, trng_flag_t flag) -{ - assert_param(IS_TRNG_FLAG(flag)); - - if (READ_BIT(hperh->perh->IFR, flag)) - return SET; - - return RESET; -} - -/** - * @brief Clear the interrupt flag. - * @param hperh: Pointer to a trng_handle_t structure that contains - * the configuration information for the specified TRNG module. - * @param flag: Specifies the interrupt flag. - * This parameter can be one of the @ref trng_flag_t. - * @retval None - */ -void ald_trng_clear_flag_status(trng_handle_t *hperh, trng_flag_t flag) -{ - assert_param(IS_TRNG_FLAG(flag)); - WRITE_REG(hperh->perh->IFCR, flag); - - return; -} - -/** - * @brief Reset the TRNG peripheral. - * @param hperh: Pointer to a trng_handle_t structure that contains - * the configuration information for the specified TRNG module. - * @retval None - */ -void trng_reset(trng_handle_t *hperh) -{ - TRNG->CR = 0; - TRNG->SEED = 0; - TRNG->CFGR = 0x1FF0707; - TRNG->IER = 0; - TRNG->IFCR = 0xFFFFFFFF; - - hperh->state = TRNG_STATE_READY; - __UNLOCK(hperh); - return; -} - -/** - * @brief This function handles TRNG interrupt request. - * @param hperh: Pointer to a trng_handle_t structure that contains - * the configuration information for the specified TRNG module. - * @retval None - */ -void ald_trng_irq_handler(trng_handle_t *hperh) -{ - if (ald_trng_get_flag_status(hperh, TRNG_IF_SERR) == SET) { - hperh->state = TRNG_STATE_ERROR; - ald_trng_clear_flag_status(hperh, TRNG_IF_SERR); - if (hperh->err_cplt_cbk) - hperh->err_cplt_cbk(hperh); - return; - } - - if (ald_trng_get_flag_status(hperh, TRNG_IF_DAVLD) == SET) { - hperh->data = hperh->perh->DR; - hperh->state = TRNG_STATE_READY; - ald_trng_clear_flag_status(hperh, TRNG_IF_DAVLD); - if (hperh->trng_cplt_cbk) - hperh->trng_cplt_cbk(hperh); - } - - if (ald_trng_get_flag_status(hperh, TRNG_IF_START) == SET) { - hperh->state = TRNG_STATE_BUSY; - ald_trng_clear_flag_status(hperh, TRNG_IF_START); - if (hperh->init_cplt_cbk) - hperh->init_cplt_cbk(hperh); - } -} - -/** - * @} - */ -/** - * @} - */ -#endif /* ALD_TRNG */ -/** - * @} - */ - -/** - * @} - */ diff --git a/bsp/essemi/es32f0334/libraries/ES32F033x_ALD_StdPeriph_Driver/Source/ald_tsense.c b/bsp/essemi/es32f0334/libraries/ES32F033x_ALD_StdPeriph_Driver/Source/ald_tsense.c deleted file mode 100644 index 5fcd8311f1..0000000000 --- a/bsp/essemi/es32f0334/libraries/ES32F033x_ALD_StdPeriph_Driver/Source/ald_tsense.c +++ /dev/null @@ -1,253 +0,0 @@ -/** - ********************************************************************************* - * - * @file ald_tsense.c - * @brief TSENSE module driver. - * - * @version V1.0 - * @date 15 Dec 2017 - * @author AE Team - * @note - * - * Copyright (C) Shanghai Eastsoft Microelectronics Co. Ltd. All rights reserved. - * - ********************************************************************************* - */ - -#include "ald_tsense.h" -#include "ald_bkpc.h" - - -/** @addtogroup ES32FXXX_ALD - * @{ - */ - -/** @defgroup TSENSE TSENSE - * @brief TSENSE module driver - * @{ - */ -#ifdef ALD_TSENSE - - -/** @defgroup TSENSE_Private_Variables TSENSE Private Variables - * @{ - */ -tsense_cbk __tsense_cbk; -/** - * @} - */ - -/** @defgroup TSENSE_Public_Functions TSENSE Public Functions - * @{ - */ - -/** @addtogroup TSENSE_Public_Functions_Group1 Initialization functions - * @brief Initialization functions - * - * @verbatim - ============================================================================== - ##### Initialization functions ##### - ============================================================================== - [..] This section provides functions allowing to initialize the TSENSE: - (+) This parameters can be configured: - (++) Update Cycle - (++) Output Mode - (++) Perscaler - (+) Select TSENSE source clock(default LOSC) - - @endverbatim - * @{ - */ - -/** - * @brief Initializes the TSENSE according to the specified - * @retval None - */ -void ald_tsense_init(void) -{ - uint16_t tempt, temptinv; - uint32_t tscic, tscicinv; - - TSENSE_UNLOCK(); - TSENSE->CR = 0; - - MODIFY_REG(TSENSE->CR, TSENSE_CR_CTN_MSK, 0x1 << TSENSE_CR_CTN_POS); - MODIFY_REG(TSENSE->CR, TSENSE_CR_TSU_MSK, 0x4 << TSENSE_CR_TSU_POSS); - MODIFY_REG(TSENSE->CR, TSENSE_CR_TOM_MSK, 0x3 << TSENSE_CR_TOM_POSS); - MODIFY_REG(TSENSE->PSR, TSENSE_PSR_PRS_MSK, 0x1 << TSENSE_PSR_PRS_POSS); - - TSENSE->HTGR = 0x88F18; - TSENSE->LTGR = 0x85C39; - tempt = *(volatile uint16_t *)0x40348; - temptinv = *(volatile uint16_t *)0x4034A; - tscic = *(volatile uint32_t *)0x40350; - tscicinv = *(volatile uint32_t *)0x40358; - - if ((tempt == (uint16_t)(~temptinv)) && (tscic == (~tscicinv))) { - TSENSE->TBDR = tempt; - TSENSE->TCALBDR = (tscic & 0x1FFFFFF) >> 6; - } - else { - TSENSE->TBDR = 0x1E00; - TSENSE->TCALBDR = 0x1FE70; - } - - TSENSE_LOCK(); - return; -} - -/** - * @brief Configure the TSENSE source. - * @param sel: TSENSE source type. - * @retval None - */ -void ald_tsense_source_select(tsense_source_sel_t sel) -{ - assert_param(IS_TSENSE_SOURCE_SEL(sel)); - - BKPC_UNLOCK(); - MODIFY_REG(BKPC->PCCR, BKPC_PCCR_TSENSECS_MSK, sel << BKPC_PCCR_TSENSECS_POSS); - - if (sel == TSENSE_SOURCE_LOSC) { - SET_BIT(BKPC->CR, BKPC_CR_LOSCEN_MSK); - } - else if (sel == TSENSE_SOURCE_LRC) { - SET_BIT(BKPC->CR, BKPC_CR_LRCEN_MSK); - } - else { - ; /* do nothing */ - } - - BKPC_LOCK(); - return; -} -/** - * @} - */ - -/** @addtogroup TSENSE_Public_Functions_Group2 Peripheral Control functions - * @brief Peripheral Control functions - * - * @verbatim - ============================================================================== - ##### Peripheral Control functions ##### - ============================================================================== - [..] This section provides functions allowing to: - (+) ald_tsense_get_value() API can get the current temperature. - (+) ald_tsense_get_value_by_it() API can get the current temperature by interrupt. - (+) ald_tsense_irq_handler() API can handle the interrupt request. - - @endverbatim - * @{ - */ - -/** - * @brief Get the current temperature - * @param tsense: The value of current temperature. - * @retval ALD status: - * @arg @ref OK The value is valid - * @arg @ref ERROR The value is invalid - */ -ald_status_t ald_tsense_get_value(uint16_t *tsense) -{ - uint32_t tmp = 0; - - TSENSE_UNLOCK(); - SET_BIT(TSENSE->IFCR, TSENSE_IFCR_TSENSE_MSK); - SET_BIT(TSENSE->CR, TSENSE_CR_EN_MSK); - TSENSE_LOCK(); - - while ((!(READ_BIT(TSENSE->IF, TSENSE_IF_TSENSE_MSK))) && (tmp++ < 1000000)); - - if (tmp >= 1000000) { - TSENSE_UNLOCK(); - CLEAR_BIT(TSENSE->CR, TSENSE_CR_EN_MSK); - TSENSE_LOCK(); - return TIMEOUT; - } - - TSENSE_UNLOCK(); - SET_BIT(TSENSE->IFCR, TSENSE_IFCR_TSENSE_MSK); - TSENSE_LOCK(); - - if (READ_BIT(TSENSE->DR, TSENSE_DR_ERR_MSK)) { - TSENSE_UNLOCK(); - CLEAR_BIT(TSENSE->CR, TSENSE_CR_EN_MSK); - TSENSE_LOCK(); - return ERROR; - } - - *tsense = READ_BITS(TSENSE->DR, TSENSE_DR_DATA_MSK, TSENSE_DR_DATA_POSS); - - TSENSE_UNLOCK(); - CLEAR_BIT(TSENSE->CR, TSENSE_CR_EN_MSK); - TSENSE_LOCK(); - - return OK; -} - -/** - * @brief Get the current temperature by interrupt - * @param cbk: The callback function - * @retval None - */ -void ald_tsense_get_value_by_it(tsense_cbk cbk) -{ - __tsense_cbk = cbk; - - TSENSE_UNLOCK(); - SET_BIT(TSENSE->IFCR, TSENSE_IFCR_TSENSE_MSK); - SET_BIT(TSENSE->IE, TSENSE_IE_TSENSE_MSK); - SET_BIT(TSENSE->CR, TSENSE_CR_EN_MSK); - TSENSE_LOCK(); - - return; -} - -/** - * @brief This function handles TSENSE interrupt request. - * @retval None - */ -void ald_tsense_irq_handler(void) -{ - TSENSE_UNLOCK(); - SET_BIT(TSENSE->IFCR, TSENSE_IFCR_TSENSE_MSK); - TSENSE_LOCK(); - - if (__tsense_cbk == NULL) { - TSENSE_UNLOCK(); - CLEAR_BIT(TSENSE->CR, TSENSE_CR_EN_MSK); - TSENSE_LOCK(); - return; - } - - if (READ_BIT(TSENSE->DR, TSENSE_DR_ERR_MSK)) { - TSENSE_UNLOCK(); - CLEAR_BIT(TSENSE->CR, TSENSE_CR_EN_MSK); - TSENSE_LOCK(); - __tsense_cbk(0, ERROR); - return; - } - - __tsense_cbk(READ_BITS(TSENSE->DR, TSENSE_DR_DATA_MSK, TSENSE_DR_DATA_POSS), OK); - - TSENSE_UNLOCK(); - SET_BIT(TSENSE->IFCR, TSENSE_IFCR_TSENSE_MSK); - CLEAR_BIT(TSENSE->CR, TSENSE_CR_EN_MSK); - TSENSE_LOCK(); - return; -} -/** - * @} - */ -/** - * @} - */ -#endif /* ALD_TSENSE */ -/** - * @} - */ - -/** - * @} - */ diff --git a/bsp/essemi/es32f0334/libraries/ES32F033x_ALD_StdPeriph_Driver/Source/ald_uart.c b/bsp/essemi/es32f0334/libraries/ES32F033x_ALD_StdPeriph_Driver/Source/ald_uart.c deleted file mode 100644 index ee4bd1bbd2..0000000000 --- a/bsp/essemi/es32f0334/libraries/ES32F033x_ALD_StdPeriph_Driver/Source/ald_uart.c +++ /dev/null @@ -1,1178 +0,0 @@ -/** - ********************************************************************************* - * - * @file ald_uart.c - * @brief UART module driver. - * This file provides firmware functions to manage the following - * functionalities of the Universal Asynchronous Receiver Transmitter (UART) peripheral: - * + Initialization and Configuration functions - * + IO operation functions - * + Peripheral Control functions - * + Peripheral State and Errors functions - * - * @version V1.0 - * @date 21 Nov 2017 - * @author AE Team - * @note - * - * Copyright (C) Shanghai Eastsoft Microelectronics Co. Ltd. All rights reserved. - * - ********************************************************************************* - * @verbatim - ============================================================================== - ##### How to use this driver ##### - ============================================================================== - [..] - The UART driver can be used as follows: - - (#) Declare a uart_handle_t handle structure. - - (#) Initialize the UART low level resources: - (##) Enable the UARTx interface clock. - (##) UART pins configuration: - (+++) Enable the clock for the UART GPIOs. - (+++) Configure the UART pins (TX as alternate function pull-up, RX as alternate function Input). - (##) NVIC configuration if you need to use interrupt process (ald_uart_send_by_it() - and ald_uart_recv_by_it() APIs): - (+++) Configure the uart interrupt priority. - (+++) Enable the NVIC UART IRQ handle. - (##) DMA Configuration if you need to use DMA process (ald_uart_send_by_dma() - and ald_uart_recv_by_dma() APIs): - (+++) Select the DMA Tx/Rx channel. - (+++) Associate the initialized DMA handle to the UART DMA Tx/Rx handle. - - (#) Program the Baud Rate, Word Length, Stop Bit, Parity, Hardware - flow control and Mode(Receiver/Transmitter) in the hperh Init structure. - - (#) Initialize the UART registers by calling the ald_uart_init() API. - - [..] - Three operation modes are available within this driver: - - *** Polling mode IO operation *** - ================================= - [..] - (+) Send an amount of data in blocking mode using ald_uart_send() - (+) Receive an amount of data in blocking mode using ald_uart_recv() - - *** Interrupt mode IO operation *** - =================================== - [..] - (+) Send an amount of data in non blocking mode using ald_uart_send_by_it() - (+) At transmission end of transfer hperh->tx_cplt_cbk() is executed and user can - add his own code by customization of function pointer hperh->tx_cplt_cbk() - (+) Receive an amount of data in non blocking mode using ald_uart_recv_by_it() - (+) At reception end of transfer hperh->rx_cplt_cbk() is executed and user can - add his own code by customization of function pointer hperh->rx_cplt_cbk() - (+) In case of transfer Error, hperh->error_cbk() function is executed and user can - add his own code by customization of function pointer hperh->error_cbk() - - *** DMA mode IO operation *** - ============================== - [..] - (+) Send an amount of data in non blocking mode (DMA) using ald_uart_send_by_dma() - (+) At transmission end of transfer hperh->tx_cplt_cbk() is executed and user can - add his own code by customization of function pointer hperh->tx_cplt_cbk() - (+) Receive an amount of data in non blocking mode (DMA) using ald_uart_recv_by_dma() - (+) At reception end of transfer hperh->rx_cplt_cbk() is executed and user can - add his own code by customization of function pointer hperh->rx_cplt_cbk() - (+) In case of transfer Error, hperh->error_cbk() function is executed and user can - add his own code by customization of function pointer hperh->error_cbk() - (+) Pause the DMA Transfer using ald_uart_dma_pause() - (+) Resume the DMA Transfer using ald_uart_dma_resume() - (+) Stop the DMA Transfer using ald_uart_dma_stop() - - @endverbatim - ****************************************************************************** - */ - -#include "ald_uart.h" -#include "ald_cmu.h" - - -/** @addtogroup ES32FXXX_ALD - * @{ - */ - -/** @defgroup UART UART - * @brief UART module driver - * @{ - */ -#ifdef ALD_UART - -/** @defgroup UART_Private_Functions UART Private Functions - * @brief UART Private functions - * @{ - */ -#ifdef ALD_DMA -/** - * @brief DMA uart transmit process complete callback. - * @param arg: Pointer to a uart_handle_t structure. - * @retval None - */ -static void uart_dma_send_cplt(void *arg) -{ - uart_handle_t *hperh = (uart_handle_t *)arg; - - if (hperh->state == UART_STATE_BUSY_TX) - ald_uart_dma_req_config(hperh, DISABLE); - - hperh->tx_count = 0; - ald_uart_interrupt_config(hperh, UART_IT_TC, ENABLE); - return; -} - -/** - * @brief DMA uart receive process complete callback. - * @param arg: Pointer to a uart_handle_t structure. - * @retval None - */ -static void uart_dma_recv_cplt(void *arg) -{ - uart_handle_t *hperh = (uart_handle_t *)arg; - - if (hperh->state == UART_STATE_BUSY_RX) - ald_uart_dma_req_config(hperh, DISABLE); - - hperh->rx_count = 0; - CLEAR_BIT(hperh->state, UART_STATE_RX_MASK); - - if (hperh->rx_cplt_cbk) - hperh->rx_cplt_cbk(hperh); - - return; -} - -/** - * @brief DMA uart communication error callback. - * @param arg: Pointer to a uart_handle_t structure. - * @retval None - */ -static void uart_dma_error(void *arg) -{ - uart_handle_t *hperh = (uart_handle_t *)arg; - - hperh->rx_count = 0; - hperh->tx_count = 0; - hperh->state = UART_STATE_READY; - hperh->err_code |= UART_ERROR_DMA; - ald_uart_dma_req_config(hperh, DISABLE); - - if (hperh->error_cbk) - hperh->error_cbk(hperh); - - return; -} -#endif - -/** - * @brief This function handles uart Communication Timeout. - * @param hperh: Pointer to a uart_handle_t structure. - * @param flag: specifies the uart flag to check. - * @param status: The new Flag status (SET or RESET). - * @param timeout: Timeout duration - * @retval Status, see @ref ald_status_t. - */ -static ald_status_t uart_wait_flag(uart_handle_t *hperh, uart_status_t flag, flag_status_t status, uint32_t timeout) -{ - uint32_t tick; - - if (timeout == 0) - return ERROR; - - tick = ald_get_tick(); - - /* Waiting for flag */ - while ((ald_uart_get_status(hperh, flag)) != status) { - if (((ald_get_tick()) - tick) > timeout) - return TIMEOUT; - } - - return OK; -} - -/** - * @brief Sends an amount of data in non blocking mode. - * @param hperh: Pointer to a uart_handle_t structure. - * @retval Status, see @ref ald_status_t. - */ -static ald_status_t __uart_send_by_it(uart_handle_t *hperh) -{ - if ((hperh->state & UART_STATE_TX_MASK) == 0x0) - return BUSY; - - WRITE_REG(hperh->perh->TBR, (uint8_t)(*hperh->tx_buf++ & 0x00FF)); - - if (--hperh->tx_count == 0) { - ald_uart_clear_flag_status(hperh, UART_IF_TC); - ald_uart_interrupt_config(hperh, UART_IT_TXS, DISABLE); - ald_uart_interrupt_config(hperh, UART_IT_TC, ENABLE); - } - - return OK; -} - -/** - * @brief Wraps up transmission in non blocking mode. - * @param hperh: pointer to a uart_handle_t structure. - * @retval Status, see @ref ald_status_t. - */ -static ald_status_t __uart_end_send_by_it(uart_handle_t *hperh) -{ - if (!(READ_BIT(hperh->perh->SR, UART_SR_TEM_MSK))) - return OK; - - ald_uart_interrupt_config(hperh, UART_IT_TC, DISABLE); - CLEAR_BIT(hperh->state, UART_STATE_TX_MASK); - if (hperh->tx_cplt_cbk) - hperh->tx_cplt_cbk(hperh); - - return OK; -} - -/** - * @brief Receives an amount of data in non blocking mode - * @param hperh: Pointer to a uart_handle_t structure. - * @retval Status, see @ref ald_status_t. - */ -static ald_status_t __uart_recv_by_it(uart_handle_t *hperh) -{ - if ((hperh->state & UART_STATE_RX_MASK) == 0x0) - return BUSY; - - *hperh->rx_buf++ = (uint8_t)(hperh->perh->RBR & 0xFF); - - if (--hperh->rx_count == 0) { - ald_uart_interrupt_config(hperh, UART_IT_RXRD, DISABLE); - CLEAR_BIT(hperh->state, UART_STATE_RX_MASK); - - if (hperh->rx_cplt_cbk) - hperh->rx_cplt_cbk(hperh); - } - - return OK; -} -/** - * @} - */ - -/** @defgroup UART_Public_Functions UART Public Functions - * @{ - */ - -/** @defgroup UART_Public_Functions_Group1 Initialization and Configuration functions - * @brief Initialization and Configuration functions - * - * @verbatim -=============================================================================== - ##### Initialization and Configuration functions ##### - =============================================================================== - [..] - This subsection provides a set of functions allowing to initialize the UARTx - and configure UARTx param. - (+) For the UARTx only these parameters can be configured: - (++) Baud Rate - (++) Word Length - (++) Stop Bit - (++) Parity - (++) Hardware flow control - (+) For RS485 mode, user also need configure some parameters by - ald_uart_rs485_config(): - (++) Enable/disable normal point mode - (++) Enable/disable auto-direction - (++) Enable/disable address detection invert - (++) Enable/disable address for compare - - @endverbatim - * @{ - */ - -/** - * @brief Reset UART peripheral - * @param hperh: Pointer to a uart_handle_t structure that contains - * the configuration information for the specified uart module. - * @retval None - */ -void ald_uart_reset(uart_handle_t *hperh) -{ - assert_param(IS_UART_ALL(hperh->perh)); - - WRITE_REG(hperh->perh->BRR, 0x0); - WRITE_REG(hperh->perh->LCR, 0x0); - WRITE_REG(hperh->perh->MCR, 0x0); - WRITE_REG(hperh->perh->CR, 0x0); - WRITE_REG(hperh->perh->RTOR, 0x0); - WRITE_REG(hperh->perh->FCR, 0x0); - WRITE_REG(hperh->perh->IDR, 0xFFF); - - hperh->err_code = UART_ERROR_NONE; - hperh->state = UART_STATE_RESET; - - __UNLOCK(hperh); - return; -} - -/** - * @brief Initializes the UARTx according to the specified - * parameters in the uart_handle_t. - * @param hperh: Pointer to a uart_handle_t structure that contains - * the configuration information for the specified UART module. - * @retval None - */ -void ald_uart_init(uart_handle_t *hperh) -{ - uint32_t tmp; - - assert_param(IS_UART_ALL(hperh->perh)); - assert_param(IS_UART_BAUDRATE(hperh->init.baud)); - assert_param(IS_UART_WORD_LENGTH(hperh->init.word_length)); - assert_param(IS_UART_STOPBITS(hperh->init.stop_bits)); - assert_param(IS_UART_PARITY(hperh->init.parity)); - assert_param(IS_UART_MODE(hperh->init.mode)); - assert_param(IS_UART_HARDWARE_FLOW_CONTROL(hperh->init.fctl)); - - ald_uart_reset(hperh); - - tmp = READ_REG(hperh->perh->LCR); - MODIFY_REG(tmp, UART_LCR_DLS_MSK, hperh->init.word_length << UART_LCR_DLS_POSS); - MODIFY_REG(tmp, UART_LCR_STOP_MSK, hperh->init.stop_bits << UART_LCR_STOP_POS); - MODIFY_REG(tmp, UART_LCR_PEN_MSK, (hperh->init.parity == UART_PARITY_NONE ? 0 : 1) << UART_LCR_PEN_POS); - MODIFY_REG(tmp, UART_LCR_PS_MSK, (hperh->init.parity == UART_PARITY_EVEN ? 1 : 0) << UART_LCR_PS_POS); - WRITE_REG(hperh->perh->LCR, tmp); - MODIFY_REG(hperh->perh->MCR, UART_MCR_AFCEN_MSK, hperh->init.fctl << UART_MCR_AFCEN_POS); - SET_BIT(hperh->perh->LCR, UART_LCR_BRWEN_MSK); - WRITE_REG(hperh->perh->BRR, ald_cmu_get_pclk1_clock() / hperh->init.baud); - CLEAR_BIT(hperh->perh->LCR, UART_LCR_BRWEN_MSK); - SET_BIT(hperh->perh->FCR, UART_FCR_FIFOEN_MSK); - SET_BIT(hperh->perh->FCR, UART_FCR_RFRST_MSK); - SET_BIT(hperh->perh->FCR, UART_FCR_TFRST_MSK); - MODIFY_REG(hperh->perh->FCR, UART_FCR_RXTL_MSK, 0 << UART_FCR_RXTL_POSS); - MODIFY_REG(hperh->perh->FCR, UART_FCR_TXTL_MSK, 0 << UART_FCR_TXTL_POSS); - SET_BIT(hperh->perh->LCR, UART_LCR_RXEN_MSK); - - if (hperh->init.mode == UART_MODE_LIN) - SET_BIT(hperh->perh->MCR, UART_MCR_LINEN_MSK); - else if (hperh->init.mode == UART_MODE_IrDA) - SET_BIT(hperh->perh->MCR, UART_MCR_IREN_MSK); - else if (hperh->init.mode == UART_MODE_RS485) - SET_BIT(hperh->perh->MCR, UART_MCR_AADEN_MSK); - else if (hperh->init.mode == UART_MODE_HDSEL) - SET_BIT(hperh->perh->MCR, UART_MCR_HDSEL_MSK); - else - ;/* do nothing */ - - if (hperh->init.fctl) - SET_BIT(hperh->perh->MCR, UART_MCR_RTSCTRL_MSK); - if (hperh->init.mode == UART_MODE_IrDA) - SET_BIT(hperh->perh->LCR, UART_LCR_RXINV_MSK); - - hperh->state = UART_STATE_READY; - hperh->err_code = UART_ERROR_NONE; - return; -} - -/** - * @brief Configure the RS485 mode according to the specified - * parameters in the uart_rs485_config_t. - * @param hperh: Pointer to a uart_handle_t structure that contains - * the configuration information for the specified UART module. - * @param config: Specifies the RS485 parameters. - * @retval None - */ -void ald_uart_rs485_config(uart_handle_t *hperh, uart_rs485_config_t *config) -{ - assert_param(IS_UART_ALL(hperh->perh)); - assert_param(IS_FUNC_STATE(config->normal)); - assert_param(IS_FUNC_STATE(config->dir)); - assert_param(IS_FUNC_STATE(config->invert)); - - MODIFY_REG(hperh->perh->MCR, UART_MCR_AADNOR_MSK, config->normal << UART_MCR_AADNOR_POS); - MODIFY_REG(hperh->perh->MCR, UART_MCR_AADDIR_MSK, config->dir << UART_MCR_AADDIR_POS); - MODIFY_REG(hperh->perh->MCR, UART_MCR_AADINV_MSK, config->invert << UART_MCR_AADINV_POS); - MODIFY_REG(hperh->perh->CR, UART_CR_ADDR_MSK, config->addr << UART_CR_ADDR_POSS); - - return; -} -/** - * @} - */ - -/** @defgroup UART_Public_Functions_Group2 IO operation functions - * @brief UART Transmit and Receive functions - * @verbatim - ============================================================================== - # IO operation functions # - ============================================================================== - [..] - This subsection provides a set of functions allowing to manage the UART data transfers. - - (#) There are two modes of transfer: - (++) Blocking mode: The communication is performed in polling mode. - The Status of all data processing is returned by the same function - after finishing transfer. - (++) Non blocking mode: The communication is performed using Interrupts - or DMA, these APIs return the Status. - The end of the data processing will be indicated through the - dedicated UART IRQ when using Interrupt mode or the DMA IRQ when - using DMA mode. - The hperh->tx_cplt_cbk(), hperh->rx_cplt_cbk() user callbacks - will be executed respectively at the end of the transmit or receive process. - The hperh->error_cbk() user callback will be executed when - a communication error is detected. - - (#) Blocking mode APIs are: - (++) ald_uart_send() - (++) ald_uart_recv() - - (#) Non Blocking mode APIs with Interrupt are: - (++) ald_uart_send_by_it() - (++) ald_uart_recv_by_it() - (++) ald_uart_irq_handler() - - (#) Non Blocking mode functions with DMA are: - (++) ald_uart_send_by_dma() - (++) ald_uart_recv_by_dma() - (++) ald_uart_dma_pause() - (++) ald_uart_dma_resume() - (++) ald_uart_dma_stop() - - (#) A set of transfer complete callbacks are provided in non blocking mode: - (++) hperh->tx_cplt_cbk() - (++) hperh->rx_cplt_cbk() - (++) hperh->error_cbk() - - @endverbatim - * @{ - */ - -/** - * @brief Sends an amount of data in blocking mode. - * @param hperh: Pointer to a uart_handle_t structure. - * @param buf: Pointer to data buffer - * @param size: Amount of data to be sent - * @param timeout: Timeout duration - * @retval Status, see @ref ald_status_t. - */ -ald_status_t ald_uart_send(uart_handle_t *hperh, uint8_t *buf, uint16_t size, uint32_t timeout) -{ - assert_param(IS_UART_ALL(hperh->perh)); - - if ((hperh->state != UART_STATE_READY) && (hperh->state != UART_STATE_BUSY_RX)) - return BUSY; - - if ((buf == NULL) || (size == 0)) - return ERROR; - - __LOCK(hperh); - hperh->err_code = UART_ERROR_NONE; - SET_BIT(hperh->state, UART_STATE_TX_MASK); - - hperh->tx_size = size; - hperh->tx_count = size; - - while (hperh->tx_count-- > 0) { - if (uart_wait_flag(hperh, UART_STATUS_TBEM, SET, timeout) != OK) { - __UNLOCK(hperh); - hperh->state = UART_STATE_READY; - return TIMEOUT; - } - - WRITE_REG(hperh->perh->TBR, (*buf++ & 0xFF)); - } - - if (uart_wait_flag(hperh, UART_STATUS_TEM, SET, timeout) != OK) { - __UNLOCK(hperh); - hperh->state = UART_STATE_READY; - return TIMEOUT; - } - - CLEAR_BIT(hperh->state, UART_STATE_TX_MASK); - __UNLOCK(hperh); - - return OK; -} - -/** - * @brief Receives an amount of data in blocking mode. - * @param hperh: Pointer to a uart_handle_t structure. - * @param buf: Pointer to data buffer - * @param size: Amount of data to be received - * @param timeout: Timeout duration - * @retval Status, see @ref ald_status_t. - */ -ald_status_t ald_uart_recv(uart_handle_t *hperh, uint8_t *buf, uint16_t size, uint32_t timeout) -{ - assert_param(IS_UART_ALL(hperh->perh)); - - if ((hperh->state != UART_STATE_READY) && (hperh->state != UART_STATE_BUSY_TX)) - return BUSY; - - if ((buf == NULL ) || (size == 0)) - return ERROR; - - __LOCK(hperh); - - hperh->err_code = UART_ERROR_NONE; - SET_BIT(hperh->state, UART_STATE_RX_MASK); - - hperh->rx_size = size; - hperh->rx_count = size; - - while (hperh->rx_count-- > 0) { - if (uart_wait_flag(hperh, UART_STATUS_DR, SET, timeout) != OK) { - __UNLOCK(hperh); - hperh->state = UART_STATE_READY; - return TIMEOUT; - } - - *buf++ = (uint8_t)(hperh->perh->RBR & 0xFF); - } - - CLEAR_BIT(hperh->state, UART_STATE_RX_MASK); - __UNLOCK(hperh); - - return OK; -} - -/** - * @brief Sends an amount of data in non blocking mode. - * @param hperh: Pointer to a uart_handle_t structure. - * @param buf: Pointer to data buffer - * @param size: Amount of data to be sent - * @retval Status, see @ref ald_status_t. - */ -ald_status_t ald_uart_send_by_it(uart_handle_t *hperh, uint8_t *buf, uint16_t size) -{ - assert_param(IS_UART_ALL(hperh->perh)); - - if ((hperh->state != UART_STATE_READY) && (hperh->state != UART_STATE_BUSY_RX)) - return BUSY; - - if ((buf == NULL ) || (size == 0)) - return ERROR; - - __LOCK(hperh); - - hperh->tx_buf = buf; - hperh->tx_size = size; - hperh->tx_count = size; - hperh->err_code = UART_ERROR_NONE; - SET_BIT(hperh->state, UART_STATE_TX_MASK); - __UNLOCK(hperh); - - if (((ald_uart_get_status(hperh, UART_STATUS_TBEM)) == SET) - && ((ald_uart_get_flag_status(hperh, UART_IF_TXS)) == RESET)) { - WRITE_REG(hperh->perh->TBR, (*hperh->tx_buf++ & 0xFF)); - --hperh->tx_count; - } - - if (hperh->tx_count == 0) { - ald_uart_interrupt_config(hperh, UART_IT_TC, ENABLE); - return OK; - } - - ald_uart_interrupt_config(hperh, UART_IT_TXS, ENABLE); - return OK; -} - -/** - * @brief Receives an amount of data in non blocking mode - * @param hperh: Pointer to a uart_handle_t structure. - * @param buf: Pointer to data buffer - * @param size: Amount of data to be received - * @retval Status, see @ref ald_status_t. - */ -ald_status_t ald_uart_recv_by_it(uart_handle_t *hperh, uint8_t *buf, uint16_t size) -{ - assert_param(IS_UART_ALL(hperh->perh)); - - if ((hperh->state != UART_STATE_READY) && (hperh->state != UART_STATE_BUSY_TX)) - return BUSY; - - if ((buf == NULL ) || (size == 0)) - return ERROR; - - __LOCK(hperh); - hperh->rx_buf = buf; - hperh->rx_size = size; - hperh->rx_count = size; - hperh->err_code = UART_ERROR_NONE; - SET_BIT(hperh->state, UART_STATE_RX_MASK); - __UNLOCK(hperh); - - ald_uart_interrupt_config(hperh, UART_IT_RXRD, ENABLE); - return OK; -} -#ifdef ALD_DMA -/** - * @brief Sends an amount of data in non blocking mode. - * @param hperh: Pointer to a uart_handle_t structure. - * @param buf: Pointer to data buffer - * @param size: Amount of data to be sent - * @param channel: DMA channel as UART transmit - * @retval Status, see @ref ald_status_t. - */ -ald_status_t ald_uart_send_by_dma(uart_handle_t *hperh, uint8_t *buf, uint16_t size, uint8_t channel) -{ - assert_param(IS_UART_ALL(hperh->perh)); - - if ((hperh->state != UART_STATE_READY) && (hperh->state != UART_STATE_BUSY_RX)) - return BUSY; - - if ((buf == NULL ) || (size == 0)) - return ERROR; - - __LOCK(hperh); - - hperh->tx_buf = buf; - hperh->tx_size = size; - hperh->tx_count = size; - hperh->err_code = UART_ERROR_NONE; - SET_BIT(hperh->state, UART_STATE_TX_MASK); - - if (hperh->hdmatx.perh == NULL) - hperh->hdmatx.perh = DMA0; - - hperh->hdmatx.cplt_cbk = uart_dma_send_cplt; - hperh->hdmatx.cplt_arg = (void *)hperh; - hperh->hdmatx.err_cbk = uart_dma_error; - hperh->hdmatx.err_arg = (void *)hperh; - - ald_dma_config_struct(&hperh->hdmatx.config); - hperh->hdmatx.config.src = (void *)buf; - hperh->hdmatx.config.dst = (void *)&hperh->perh->TBR; - hperh->hdmatx.config.size = size; - hperh->hdmatx.config.src_inc = DMA_DATA_INC_BYTE; - hperh->hdmatx.config.dst_inc = DMA_DATA_INC_NONE; - hperh->hdmatx.config.msigsel = DMA_MSIGSEL_UART_TXEMPTY; - hperh->hdmatx.config.burst = ENABLE; - hperh->hdmatx.config.channel = channel; - - if (hperh->init.mode == UART_MODE_RS485) { - hperh->hdmatx.config.src_inc = DMA_DATA_INC_HALFWORD; - hperh->hdmatx.config.data_width = DMA_DATA_SIZE_HALFWORD; - } - - if (hperh->perh == UART0) - hperh->hdmatx.config.msel = DMA_MSEL_UART0; - else if (hperh->perh == UART1) - hperh->hdmatx.config.msel = DMA_MSEL_UART1; - else if (hperh->perh == UART2) - hperh->hdmatx.config.msel = DMA_MSEL_UART2; - else if (hperh->perh == UART3) - hperh->hdmatx.config.msel = DMA_MSEL_UART3; - else - ; /* do nothing */ - - ald_dma_config_basic(&hperh->hdmatx); - - __UNLOCK(hperh); - ald_uart_clear_flag_status(hperh, UART_IF_TC); - ald_uart_dma_req_config(hperh, ENABLE); - - return OK; -} - -/** - * @brief Receives an amount of data in non blocking mode. - * @param hperh: Pointer to a uart_handle_t structure. - * @param buf: Pointer to data buffer - * @param size: Amount of data to be received - * @param channel: DMA channel as UART receive - * @retval Status, see @ref ald_status_t. - */ -ald_status_t ald_uart_recv_by_dma(uart_handle_t *hperh, uint8_t *buf, uint16_t size, uint8_t channel) -{ - assert_param(IS_UART_ALL(hperh->perh)); - - if ((hperh->state != UART_STATE_READY) && (hperh->state != UART_STATE_BUSY_TX)) - return BUSY; - - if ((buf == NULL) || (size == 0)) - return ERROR; - - __LOCK(hperh); - - hperh->rx_buf = buf; - hperh->rx_size = size; - hperh->err_code = UART_ERROR_NONE; - SET_BIT(hperh->state, UART_STATE_RX_MASK); - - if (hperh->hdmarx.perh == NULL) - hperh->hdmarx.perh = DMA0; - - hperh->hdmarx.cplt_cbk = uart_dma_recv_cplt; - hperh->hdmarx.cplt_arg = (void *)hperh; - hperh->hdmarx.err_cbk = uart_dma_error; - hperh->hdmarx.err_arg = (void *)hperh; - - ald_dma_config_struct(&hperh->hdmarx.config); - hperh->hdmarx.config.src = (void *)&hperh->perh->RBR; - hperh->hdmarx.config.dst = (void *)buf; - hperh->hdmarx.config.size = size; - hperh->hdmarx.config.src_inc = DMA_DATA_INC_NONE; - hperh->hdmarx.config.dst_inc = DMA_DATA_INC_BYTE; - hperh->hdmarx.config.msigsel = DMA_MSIGSEL_UART_RNR; - hperh->hdmarx.config.burst = ENABLE; - hperh->hdmarx.config.channel = channel; - - if (hperh->init.mode == UART_MODE_RS485) { - hperh->hdmarx.config.dst_inc = DMA_DATA_INC_HALFWORD; - hperh->hdmarx.config.data_width = DMA_DATA_SIZE_HALFWORD; - } - - if (hperh->perh == UART0) - hperh->hdmarx.config.msel = DMA_MSEL_UART0; - else if (hperh->perh == UART1) - hperh->hdmarx.config.msel = DMA_MSEL_UART1; - else if (hperh->perh == UART2) - hperh->hdmarx.config.msel = DMA_MSEL_UART2; - else if (hperh->perh == UART3) - hperh->hdmarx.config.msel = DMA_MSEL_UART3; - else - ; - - ald_dma_config_basic(&hperh->hdmarx); - __UNLOCK(hperh); - ald_uart_dma_req_config(hperh, ENABLE); - - return OK; -} - -/** - * @brief Pauses the DMA Transfer. - * @param hperh: Pointer to a uart_handle_t structure. - * @retval Status, see @ref ald_status_t. - */ -ald_status_t ald_uart_dma_pause(uart_handle_t *hperh) -{ - assert_param(IS_UART_ALL(hperh->perh)); - - ald_uart_dma_req_config(hperh, DISABLE); - return OK; -} - -/** - * @brief Resumes the DMA Transfer. - * @param hperh: Pointer to a uart_handle_t structure. - * @retval Status, see @ref ald_status_t. - */ -ald_status_t ald_uart_dma_resume(uart_handle_t *hperh) -{ - assert_param(IS_UART_ALL(hperh->perh)); - - ald_uart_dma_req_config(hperh, ENABLE); - return OK; -} - -/** - * @brief Stops the DMA Transfer. - * @param hperh: Pointer to a uart_handle_t structure. - * @retval Status, see @ref ald_status_t. - */ -ald_status_t ald_uart_dma_stop(uart_handle_t *hperh) -{ - assert_param(IS_UART_ALL(hperh->perh)); - - ald_uart_dma_req_config(hperh, DISABLE); - hperh->state = UART_STATE_READY; - return OK; -} -#endif - -/** - * @brief This function handles UART interrupt request. - * @param hperh: Pointer to a uart_handle_t structure. - * @retval None - */ -void ald_uart_irq_handler(uart_handle_t *hperh) -{ - assert_param(IS_UART_ALL(hperh->perh)); - - /* Handle parity error */ - if ((ald_uart_get_status(hperh, UART_STATUS_PE)) != RESET) - hperh->err_code |= UART_ERROR_PE; - - /* Handle frame error */ - if ((ald_uart_get_status(hperh, UART_STATUS_FE)) != RESET) - hperh->err_code |= UART_ERROR_FE; - - /* Handle overflow error */ - if ((ald_uart_get_status(hperh, UART_STATUS_OE)) != RESET) - hperh->err_code |= UART_ERROR_ORE; - - /* Receive */ - if ((ald_uart_get_mask_flag_status(hperh, UART_IF_RXRD)) != RESET) { - __uart_recv_by_it(hperh); - ald_uart_clear_flag_status(hperh, UART_IF_RXRD); - } - - /* Transmit */ - if ((ald_uart_get_mask_flag_status(hperh, UART_IF_TXS)) != RESET) { - __uart_send_by_it(hperh); - ald_uart_clear_flag_status(hperh, UART_IF_TXS); - } - - /* End Transmit */ - if ((ald_uart_get_mask_flag_status(hperh, UART_IF_TC)) != RESET) { - __uart_end_send_by_it(hperh); - ald_uart_clear_flag_status(hperh, UART_IF_TC); - } - - /* Handle error state */ - if (hperh->err_code != UART_ERROR_NONE) { - hperh->state = UART_STATE_READY; - - if (hperh->error_cbk) - hperh->error_cbk(hperh); - } -} -/** - * @} - */ - -/** @defgroup UART_Public_Functions_Group3 Peripheral Control functions - * @brief UART control functions - * - * @verbatim - ============================================================================== - ##### Peripheral Control functions ##### - ============================================================================== - [..] - This subsection provides a set of functions allowing to control the UART: - (+) ald_uart_interrupt_config() API can be helpful to configure UART interrupt source. - (+) ald_uart_dma_req_config() API can be helpful to configure UART DMA request. - (+) ald_uart_tx_fifo_config() API can be helpful to configure UART TX FIFO paramters. - (+) ald_uart_rx_fifo_config() API can be helpful to configure UART RX FIFO paramters. - (+) ald_uart_lin_send_break() API can send a frame of break in LIN mode. - (+) ald_uart_lin_detect_break_len_config() API can be helpful to configure the length of break frame. - (+) ald_uart_auto_baud_config() API can be helpful to configure detection data mode. - (+) ald_uart_get_it_status() API can get the status of interrupt source. - (+) ald_uart_get_status() API can get the status of UART_SR register. - (+) ald_uart_get_flag_status() API can get the status of UART flag. - (+) ald_uart_get_mask_flag_status() API can get status os flag and interrupt source. - (+) ald_uart_clear_flag_status() API can clear UART flag. - - @endverbatim - * @{ - */ - -/** - * @brief Enable/disable the specified UART interrupts. - * @param hperh: Pointer to a uart_handle_t structure. - * @param it: Specifies the UART interrupt sources to be enabled or disabled. - * This parameter can be one of the @ref uart_it_t. - * @param state: New state of the specified UART interrupts. - * This parameter can be: - * @arg ENABLE - * @arg DISABLE - * @retval None - */ -void ald_uart_interrupt_config(uart_handle_t *hperh, uart_it_t it, type_func_t state) -{ - assert_param(IS_UART_ALL(hperh->perh)); - assert_param(IS_UART_IT(it)); - assert_param(IS_FUNC_STATE(state)); - - if (state == ENABLE) - WRITE_REG(hperh->perh->IER, it); - else - WRITE_REG(hperh->perh->IDR, it); - - return; -} - -/** - * @brief Configure UART DMA request. - * @param hperh: Pointer to a uart_handle_t structure. - * @param state: New state of the specified DMA request. - * This parameter can be: - * @arg ENABLE - * @arg DISABLE - * @retval None - */ -void ald_uart_dma_req_config(uart_handle_t *hperh, type_func_t state) -{ - assert_param(IS_UART_ALL(hperh->perh)); - assert_param(IS_FUNC_STATE(state)); - - if (state == ENABLE) - SET_BIT(hperh->perh->MCR, UART_MCR_DMAEN_MSK); - else - CLEAR_BIT(hperh->perh->MCR, UART_MCR_DMAEN_MSK); - - return; -} - -/** - * @brief Configure transmit fifo parameters. - * @param hperh: Pointer to a uart_handle_t structure. - * @param config: Transmit fifo trigger level. - * @retval None - */ -void ald_uart_tx_fifo_config(uart_handle_t *hperh, uart_txfifo_t config) -{ - assert_param(IS_UART_ALL(hperh->perh)); - assert_param(IS_UART_TXFIFO_TYPE(config)); - - SET_BIT(hperh->perh->FCR, UART_FCR_TFRST_MSK); - MODIFY_REG(hperh->perh->FCR, UART_FCR_TXTL_MSK, config << UART_FCR_TXTL_POSS); - SET_BIT(hperh->perh->FCR, UART_FCR_FIFOEN_MSK); - - return; -} - -/** - * @brief Configure receive fifo parameters. - * @param hperh: Pointer to a uart_handle_t structure. - * @param config: Receive fifo trigger level. - * @retval None - */ -void ald_uart_rx_fifo_config(uart_handle_t *hperh, uart_rxfifo_t config) -{ - assert_param(IS_UART_ALL(hperh->perh)); - assert_param(IS_UART_RXFIFO_TYPE(config)); - - SET_BIT(hperh->perh->FCR, UART_FCR_RFRST_MSK); - MODIFY_REG(hperh->perh->FCR, UART_FCR_RXTL_MSK, config << UART_FCR_RXTL_POSS); - SET_BIT(hperh->perh->FCR, UART_FCR_FIFOEN_MSK); - - return; -} - -/** - * @brief request to send a frame of break. - * @param hperh: Pointer to a uart_handle_t structure. - * @retval None - */ -void ald_uart_lin_send_break(uart_handle_t *hperh) -{ - assert_param(IS_UART_ALL(hperh->perh)); - - SET_BIT(hperh->perh->MCR, UART_MCR_BKREQ_MSK); - return; -} - -/** - * @brief Configure the length of break frame to be detect. - * @param hperh: Pointer to a uart_handle_t structure. - * @param len: Length of break frame. - * @arg LIN_BREAK_LEN_10B - * @arg LIN_BREAK_LEN_11B - * @retval None - */ -void ald_uart_lin_detect_break_len_config(uart_handle_t *hperh, uart_lin_break_len_t len) -{ - assert_param(IS_UART_ALL(hperh->perh)); - assert_param(IS_UART_LIN_BREAK_LEN(len)); - - MODIFY_REG(hperh->perh->MCR, UART_MCR_LINBDL_MSK, len << UART_MCR_LINBDL_POS); - return; -} - -/** - * @brief Configure the mode of auto-baud-rate detect. - * @param hperh: Pointer to a uart_handle_t structure. - * @param mode: The mode of auto-baud-rate detect. - * @arg UART_ABRMOD_1_TO_0 - * @arg UART_ABRMOD_1 - * @arg UART_ABRMOD_0_TO_1 - * @retval None - */ -void ald_uart_auto_baud_config(uart_handle_t *hperh, uart_auto_baud_mode_t mode) -{ - assert_param(IS_UART_ALL(hperh->perh)); - assert_param(IS_UART_AUTO_BAUD_MODE(mode)); - - MODIFY_REG(hperh->perh->MCR, UART_MCR_ABRMOD_MSK, mode << UART_MCR_ABRMOD_POSS); - return; -} - -/** - * @brief Send address in RS485 mode. - * @param hperh: Pointer to a uart_handle_t structure that contains - * the configuration information for the specified UART module. - * @param addr: the address of RS485 device. - * @param timeout: Timeout duration - * @retval The ALD status. - */ -ald_status_t ald_uart_rs485_send_addr(uart_handle_t *hperh, uint16_t addr, uint32_t timeout) -{ - assert_param(IS_UART_ALL(hperh->perh)); - - if ((hperh->state != UART_STATE_READY) && (hperh->state != UART_STATE_BUSY_RX)) - return BUSY; - - SET_BIT(hperh->state, UART_STATE_TX_MASK); - - if (uart_wait_flag(hperh, UART_STATUS_TBEM, SET, timeout) != OK) { - hperh->state = UART_STATE_READY; - return TIMEOUT; - } - - WRITE_REG(hperh->perh->TBR, (addr | 0x100)); - - if (uart_wait_flag(hperh, UART_STATUS_TEM, SET, timeout) != OK) { - hperh->state = UART_STATE_READY; - return TIMEOUT; - } - - CLEAR_BIT(hperh->state, UART_STATE_TX_MASK); - - return OK; -} - -/** - * @brief Get the status of UART interrupt source. - * @param hperh: Pointer to a uart_handle_t structure. - * @param it: Specifies the UART interrupt source. - * This parameter can be one of the @ref uart_it_t. - * @retval Status: - * - 0: RESET - * - 1: SET - */ -it_status_t ald_uart_get_it_status(uart_handle_t *hperh, uart_it_t it) -{ - assert_param(IS_UART_ALL(hperh->perh)); - assert_param(IS_UART_IT(it)); - - if (READ_BIT(hperh->perh->IVS, it)) - return SET; - - return RESET; -} - -/** - * @brief Get the status of UART_SR register. - * @param hperh: Pointer to a uart_handle_t structure. - * @param status: Specifies the UART status type. - * This parameter can be one of the @ref uart_status_t. - * @retval Status: - * - 0: RESET - * - 1: SET - */ -flag_status_t ald_uart_get_status(uart_handle_t *hperh, uart_status_t status) -{ - assert_param(IS_UART_ALL(hperh->perh)); - assert_param(IS_UART_STATUS(status)); - - if (READ_BIT(hperh->perh->SR, status)) - return SET; - - return RESET; -} - - -/** - * @brief Get the status of UART interrupt flag. - * @param hperh: Pointer to a uart_handle_t structure. - * @param flag: Specifies the UART interrupt flag. - * This parameter can be one of the @ref uart_flag_t. - * @retval Status: - * - 0: RESET - * - 1: SET - */ -flag_status_t ald_uart_get_flag_status(uart_handle_t *hperh, uart_flag_t flag) -{ - assert_param(IS_UART_ALL(hperh->perh)); - assert_param(IS_UART_IF(flag)); - - if (READ_BIT(hperh->perh->RIF, flag)) - return SET; - - return RESET; -} - -/** - * @brief Get the status of interrupt flag and interupt source. - * @param hperh: Pointer to a uart_handle_t structure. - * @param flag: Specifies the UART interrupt flag. - * This parameter can be one of the @ref uart_flag_t. - * @retval Status: - * - 0: RESET - * - 1: SET - */ -flag_status_t ald_uart_get_mask_flag_status(uart_handle_t *hperh, uart_flag_t flag) -{ - assert_param(IS_UART_ALL(hperh->perh)); - assert_param(IS_UART_IF(flag)); - - if (READ_BIT(hperh->perh->IFM, flag)) - return SET; - - return RESET; -} - -/** - * @brief Clear the UART interrupt flag. - * @param hperh: Pointer to a uart_handle_t structure. - * @param flag: Specifies the UART interrupt flag. - * This parameter can be one of the @ref uart_flag_t. - * @retval None - */ -void ald_uart_clear_flag_status(uart_handle_t *hperh, uart_flag_t flag) -{ - assert_param(IS_UART_ALL(hperh->perh)); - assert_param(IS_UART_IF(flag)); - - WRITE_REG(hperh->perh->ICR, flag); - return; -} -/** - * @} - */ - -/** @defgroup UART_Public_Functions_Group4 Peripheral State and Errors functions - * @brief UART State and Errors functions - * -@verbatim - ============================================================================== - ##### Peripheral State and Errors functions ##### - ============================================================================== - [..] - This subsection provides a set of functions allowing to return the State of - UART communication process, return Peripheral Errors occurred during communication - process - (+) ald_uart_get_state() API can be helpful to check in run-time the state of the UART peripheral. - (+) ald_uart_get_error() check in run-time errors that could be occurred during communication. - -@endverbatim - * @{ - */ - -/** - * @brief Returns the UART state. - * @param hperh: Pointer to a uart_handle_t structure. - * @retval ALD state - */ -uart_state_t ald_uart_get_state(uart_handle_t *hperh) -{ - return hperh->state; -} - -/** - * @brief Return the UART error code - * @param hperh: Pointer to a uart_handle_t structure. - * @retval UART Error Code - */ -uint32_t ald_uart_get_error(uart_handle_t *hperh) -{ - return hperh->err_code; -} - -/** - * @} - */ - -/** - * @} - */ -#endif /* ALD_UART */ - -/** - * @} - */ - -/** - * @} - */ diff --git a/bsp/essemi/es32f0334/libraries/ES32F033x_ALD_StdPeriph_Driver/Source/ald_usart.c b/bsp/essemi/es32f0334/libraries/ES32F033x_ALD_StdPeriph_Driver/Source/ald_usart.c deleted file mode 100644 index 1e9ed5c501..0000000000 --- a/bsp/essemi/es32f0334/libraries/ES32F033x_ALD_StdPeriph_Driver/Source/ald_usart.c +++ /dev/null @@ -1,2326 +0,0 @@ -/** - ********************************************************************************* - * - * @file ald_usart.c - * @brief USART module driver. - * This file provides firmware functions to manage the following - * functionalities of the Universal Synchronous Asynchronous Receiver Transmitter (USART) peripheral: - * + Initialization functions - * + IO operation functions - * + Peripheral Control functions - * + Peripheral State and Errors functions - * - * @version V1.0 - * @date 25 Apr 2017 - * @author AE Team - * @note - * - * Copyright (C) Shanghai Eastsoft Microelectronics Co. Ltd. All rights reserved. - * - ********************************************************************************* - * @verbatim - ============================================================================== - ##### How to use this driver ##### - ============================================================================== - [..] - The USART ALD driver can be used as follows: - - (#) Declare a usart_handle_t handle structure. - - (#) Initialize the USART handle: - (##) Enable the USARTx interface clock. - (##) USART pins configuration: - (+++) Enable the clock for the USART GPIOs. - (+++) Configure the USART pins (TX as alternate function pull-up, RX as alternate function Input). - (##) NVIC configuration if you need to use interrupt process (ald_usart_send_by_it() - and ald_usart_recv_by_it() APIs): - (+++) Configure the USARTx interrupt priority. - (+++) Enable the NVIC USART IRQ handle. - (##) DMA Configuration if you need to use DMA process (ald_usart_send_by_dma() - and ald_usart_recv_by_dma() APIs): - (+++) Declare a DMA handle structure for the Tx/Rx channel. - (+++) Enable the DMAx interface clock. - (+++) Configure the declared DMA handle structure with the required - Tx/Rx parameters. - (+++) Configure the DMA Tx/Rx channel. - (+++) Associate the initialized DMA handle to the USART DMA Tx/Rx handle. - - (#) Program the baud rate, word length, stop bit, parity, hardware - flow control and mode(Receiver/Transmitter) in the hperh Init structure. - - (#) For the USART asynchronous mode, initialize the USART registers by calling - the ald_usart_init() API. - - (#) For the USART Half duplex mode, initialize the USART registers by calling - the ald_usart_half_duplex_init() API. - - (#) For the LIN mode, initialize the USART registers by calling the usart_lin_init() API. - - (#) For the Multi-Processor mode, initialize the USART registers by calling - the ald_usart_multi_processor_init() API. - - [..] - (@) The specific USART interrupts (Transmission complete interrupt, - RXNE interrupt and Error Interrupts) will be managed using the function - ald_usart_interrupt_config inside the transmit and receive process. - - [..] - Three operation modes are available within this driver : - - *** Polling mode IO operation *** - ================================= - [..] Asynchronous: - (+) Send an amount of data in blocking mode using ald_usart_send() - (+) Receive an amount of data in blocking mode using ald_usart_recv() - - [..] Synchronous: - (+) Send an amount of data in blocking mode using ald_usart_send_sync() - (+) Receive an amount of data in blocking mode using ald_usart_recv_sync() - - *** Interrupt mode IO operation *** - =================================== - [..] Asynchronous: - (+) Send an amount of data in non blocking mode using ald_usart_send_by_it() - (+) At transmission end of transfer hperh->tx_cplt_cbk() is executed and user can - add his own code by customization of function pointer hperh->tx_cplt_cbk() - (+) Receive an amount of data in non blocking mode using USART_recv_by_it() - (+) At reception end of transfer hperh->rx_cplt_cbk() is executed and user can - add his own code by customization of function pointer hperh->rx_cplt_cbk() - (+) In case of transfer Error, hperh->error_cbk() function is executed and user can - add his own code by customization of function pointer hperh->error_cbk() - [..] Synchronous: - (+) Send an amount of data in non blocking mode using ald_usart_send_by_it_sync() - (+) At transmission end of transfer hperh->tx_cplt_cbk() is executed and user can - add his own code by customization of function pointer hperh->tx_cplt_cbk() - (+) Receive an amount of data in non blocking mode using USART_recv_by_it_sync() - (+) At reception end of transfer hperh->rx_cplt_cbk() is executed and user can - add his own code by customization of function pointer hperh->rx_cplt_cbk() - (+) In case of transfer Error, hperh->error_cbk() function is executed and user can - add his own code by customization of function pointer hperh->error_cbk() - - *** DMA mode IO operation *** - ============================== - [..] Asynchronous: - (+) Send an amount of data in non blocking mode (DMA) using ald_usart_send_by_dma() - (+) At transmission end of transfer hperh->tx_cplt_cbk() is executed and user can - add his own code by customization of function pointer hperh->tx_cplt_cbk() - (+) Receive an amount of data in non blocking mode (DMA) using ald_usart_recv_by_dma() - (+) At reception end of transfer hperh->rx_cplt_cbk() is executed and user can - add his own code by customization of function pointer hperh->rx_cplt_cbk() - (+) In case of transfer Error, hperh->error_cbk()() function is executed and user can - add his own code by customization of function pointer hperh->error_cbk() - [..] Synchronous: - (+) Send an amount of data in non blocking mode (DMA) using ald_usart_send_by_dma_sync() - (+) At transmission end of transfer hperh->tx_cplt_cbk() is executed and user can - add his own code by customization of function pointer hperh->tx_cplt_cbk() - (+) Receive an amount of data in non blocking mode (DMA) using ald_usart_recv_by_dma_sync() - (+) At reception end of transfer hperh->rx_cplt_cbk() is executed and user can - add his own code by customization of function pointer hperh->rx_cplt_cbk() - (+) In case of transfer Error, hperh->error_cbk()() function is executed and user can - add his own code by customization of function pointer hperh->error_cbk() - [..] Utilities: - (+) Pause the DMA Transfer using ald_usart_dma_pause() - (+) Resume the DMA Transfer using ald_usart_dma_resume() - (+) Stop the DMA Transfer using ald_usart_dma_stop() - - *** USART ALD driver macros list *** - ============================================= - [..] - Below the list of most used macros in USART ALD driver. - - (+) USART_ENABLE: Enable the USART peripheral - (+) USART_DISABLE: Disable the USART peripheral - (+) USART_RESET_HANDLE_STATE : Reset USART handle - (+) USART_CLEAR_PEFLAG : Clear PE flag - (+) USART_CLEAR_FEFLAG: Clear FE flag - (+) USART_CLEAR_NEFLAG: Clear NE flag - (+) USART_CLEAR_OREFLAG: Clear voerrun flag - (+) USART_CLEAR_IDLEFLAG : Clear IDLE flag - (+) USART_HWCONTROL_CTS_ENABLE: Enable CTS flow control - (+) USART_HWCONTROL_CTS_DISABLE: Disable CTS flow control - (+) USART_HWCONTROL_RTS_ENABLE: Enable RTS flow control - (+) USART_HWCONTROL_RTS_DISABLE: Disable RTS flow control - - [..] - (@) You can refer to the USART Library header file for more useful macros - - @endverbatim - ****************************************************************************** - */ - -#include "ald_usart.h" -#include "ald_cmu.h" - - -/** @addtogroup ES32FXXX_ALD - * @{ - */ - -/** @defgroup USART USART - * @brief USART module driver - * @{ - */ -#ifdef ALD_USART - -/** @defgroup USART_Private_Variables USART Private Variables - * @{ - */ -uint8_t __frame_mode = 0; -/** - * @} - */ - -/** @addtogroup USART_Private_Functions USART Private Functions - * @{ - */ -static void usart_set_config (usart_handle_t *hperh); -static ald_status_t __usart_send_by_it(usart_handle_t *hperh); -static ald_status_t __usart_end_send_by_it(usart_handle_t *hperh); -static ald_status_t __usart_recv_by_it(usart_handle_t *hperh); -static ald_status_t __usart_recv_frame_cplt(usart_handle_t *hperh); -static ald_status_t __usart_recv_by_it_sync(usart_handle_t *hperh); -static ald_status_t __usart_send_recv_by_it_sync(usart_handle_t *hperh); -#ifdef ALD_DMA -static void usart_dma_send_cplt(void *arg); -static void usart_dma_recv_cplt(void *arg); -static void usart_dma_error(void *arg); -#endif -static ald_status_t usart_wait_flag(usart_handle_t *hperh, usart_flag_t flag, flag_status_t status, uint32_t timeout); -/** - * @} - */ - -/** @defgroup USART_Public_Functions USART Public Functions - * @{ - */ - -/** @defgroup USART_Public_Functions_Group1 Initialization functions - * @brief Initialization and Configuration functions - * - * @verbatim -=============================================================================== - ##### Initialization and Configuration functions ##### - =============================================================================== - [..] - This subsection provides a set of functions allowing to initialize the USARTx or the USARTy - in asynchronous or synchronous mode. - (+) For the asynchronous mode only these parameters can be configured: - (++) Baud rate - (++) Word length - (++) Stop bit - (++) Parity - (++) Hardware flow control - (++) Receiver/transmitter modes - [..] - The ald_usart_init(), ald_usart_half_duplex_init(), usart_lin_init(), ald_usart_multi_processor_init() - and ald_usart_clock_init() APIs follow respectively the USART asynchronous, USART Half duplex, - LIN, Multi-Processor and synchronous configuration procedures. - - @endverbatim - * @{ - */ - -/* - Additionnal remark: If the parity is enabled, then the MSB bit of the data written - in the data register is transmitted but is changed by the parity bit. - Depending on the frame length defined by the M bit (8-bits or 9-bits), - the possible USART frame formats are as listed in the following table: - +-------------------------------------------------------------+ - | M bit | PCE bit | USART frame | - |---------------------|---------------------------------------| - | 0 | 0 | | SB | 8 bit data | STB | | - |---------|-----------|---------------------------------------| - | 0 | 1 | | SB | 7 bit data | PB | STB | | - |---------|-----------|---------------------------------------| - | 1 | 0 | | SB | 9 bit data | STB | | - |---------|-----------|---------------------------------------| - | 1 | 1 | | SB | 8 bit data | PB | STB | | - +-------------------------------------------------------------+ -*/ - - -/** - * @brief Reset the USART peripheral. - * @param hperh: Pointer to a usart_handle_t structure that contains - * the configuration information for the specified USART module. - * @retval None - */ -void ald_usart_reset(usart_handle_t *hperh) -{ - assert_param(IS_USART(hperh->perh)); - - hperh->state = USART_STATE_BUSY; - USART_DISABLE(hperh); - - WRITE_REG(hperh->perh->CON0, 0x0); - WRITE_REG(hperh->perh->CON1, 0x0); - WRITE_REG(hperh->perh->CON2, 0x0); - - hperh->err_code = USART_ERROR_NONE; - hperh->state = USART_STATE_RESET; - - __UNLOCK(hperh); - return; -} - -/** - * @brief Initializes the USART mode according to the specified parameters in - * the usart_init_t and create the associated handle. - * @param hperh: Pointer to a usart_handle_t structure that contains - * the configuration information for the specified USART module. - * @retval Status, see @ref ald_status_t. - */ -ald_status_t ald_usart_init(usart_handle_t *hperh) -{ - assert_param(IS_USART(hperh->perh)); - assert_param(IS_USART_HARDWARE_FLOW_CONTROL(hperh->init.fctl)); - assert_param(IS_USART_WORD_LENGTH(hperh->init.word_length)); - - ald_usart_reset(hperh); - hperh->state = USART_STATE_BUSY; - USART_DISABLE(hperh); - usart_set_config(hperh); - - /* In asynchronous mode, the following bits must be kept cleared: - * - LINEN and CLKEN bits in the USART_CR2 register, - * - SCEN, HDSEL and IREN bits in the USART_CR3 register. - */ - CLEAR_BIT(hperh->perh->CON1, USART_CON1_SCKEN_MSK); - CLEAR_BIT(hperh->perh->CON2, USART_CON2_SMARTEN_MSK); - CLEAR_BIT(hperh->perh->CON2, USART_CON2_HDPSEL_MSK); - CLEAR_BIT(hperh->perh->CON2, USART_CON2_IREN_MSK); - - hperh->err_code = USART_ERROR_NONE; - hperh->state = USART_STATE_READY; - USART_ENABLE(hperh); - - return OK; -} - -/** - * @brief Initializes the half-duplex mode according to the specified - * parameters in the usart_init_t and create the associated handle. - * @param hperh: Pointer to a usart_handle_t structure that contains - * the configuration information for the specified USART module. - * @retval Status, see @ref ald_status_t. - */ -ald_status_t ald_usart_half_duplex_init(usart_handle_t *hperh) -{ - assert_param(IS_USART(hperh->perh)); - assert_param(IS_USART_WORD_LENGTH(hperh->init.word_length)); - - ald_usart_reset(hperh); - hperh->state = USART_STATE_BUSY; - USART_DISABLE(hperh); - usart_set_config(hperh); - - /* In half-duplex mode, the following bits must be kept cleared: - * - LINEN and CLKEN bits in the USART_CR2 register, - * - SCEN and IREN bits in the USART_CR3 register.*/ - CLEAR_BIT(hperh->perh->CON1, USART_CON1_SCKEN_MSK); - CLEAR_BIT(hperh->perh->CON2, USART_CON2_SMARTEN_MSK); - CLEAR_BIT(hperh->perh->CON2, USART_CON2_IREN_MSK); - SET_BIT(hperh->perh->CON2, USART_CON2_HDPSEL_MSK); - - hperh->err_code = USART_ERROR_NONE; - hperh->state = USART_STATE_READY; - USART_ENABLE(hperh); - - return OK; -} - -/** - * @brief Initializes the Multi-Processor mode according to the specified - * parameters in the usart_init_t and create the associated handle. - * @param hperh: Pointer to a usart_handle_t structure that contains - * the configuration information for the specified USART module. - * @param addr: USART node address - * @param wakeup: specifies the USART wakeup method. - * This parameter can be one of the following values: - * @arg USART_WAKEUP_IDLE: Wakeup by an idle line detection - * @arg USART_WAKEUP_ADDR: Wakeup by an address mark - * @retval Status, see @ref ald_status_t. - */ -ald_status_t ald_usart_multi_processor_init(usart_handle_t *hperh, uint8_t addr, usart_wakeup_t wakeup) -{ - assert_param(IS_USART(hperh->perh)); - assert_param(IS_USART_WAKEUP(wakeup)); - assert_param(IS_USART_ADDRESS(addr)); - assert_param(IS_USART_WORD_LENGTH(hperh->init.word_length)); - - ald_usart_reset(hperh); - hperh->state = USART_STATE_BUSY; - USART_DISABLE(hperh); - usart_set_config(hperh); - - /* In Multi-Processor mode, the following bits must be kept cleared: - * - LINEN and CLKEN bits in the USART_CR2 register, - * - SCEN, HDSEL and IREN bits in the USART_CR3 register */ - CLEAR_BIT(hperh->perh->CON1, USART_CON1_SCKEN_MSK); - CLEAR_BIT(hperh->perh->CON2, USART_CON2_SMARTEN_MSK); - CLEAR_BIT(hperh->perh->CON2, USART_CON2_HDPSEL_MSK); - CLEAR_BIT(hperh->perh->CON2, USART_CON2_IREN_MSK); - MODIFY_REG(hperh->perh->CON1, USART_CON1_ADDR_MSK, addr << USART_CON1_ADDR_POSS); - MODIFY_REG(hperh->perh->CON0, USART_CON0_WKMOD_MSK, wakeup << USART_CON0_WKMOD_POS); - - hperh->err_code = USART_ERROR_NONE; - hperh->state = USART_STATE_READY; - USART_ENABLE(hperh); - - return OK; -} - -/** - * @brief Initializes the synchronization mode according to the specified - * parameters in the usart_init_t and usart_clock_init_t. - * @param hperh: Pointer to a usart_handle_t structure that contains - * the configuration information for the specified USART module. - * @param init: USART Clock Init Structure. - * @retval Status, see @ref ald_status_t. - */ -ald_status_t ald_usart_clock_init(usart_handle_t *hperh, usart_clock_init_t *init) -{ - assert_param(IS_USART(hperh->perh)); - assert_param(IS_USART_WORD_LENGTH(hperh->init.word_length)); - - ald_usart_reset(hperh); - hperh->state = USART_STATE_BUSY; - USART_DISABLE(hperh); - usart_set_config(hperh); - - /* In Multi-Processor mode, the following bits must be kept cleared: - * - LINEN and CLKEN bits in the USART_CR2 register, - * - SCEN, HDSEL and IREN bits in the USART_CR3 register */ - CLEAR_BIT(hperh->perh->CON2, USART_CON2_SMARTEN_MSK); - CLEAR_BIT(hperh->perh->CON2, USART_CON2_HDPSEL_MSK); - CLEAR_BIT(hperh->perh->CON2, USART_CON2_IREN_MSK); - MODIFY_REG(hperh->perh->CON1, USART_CON1_SCKEN_MSK, init->clk << USART_CON1_SCKEN_POS); - MODIFY_REG(hperh->perh->CON1, USART_CON1_SCKPOL_MSK, init->polarity << USART_CON1_SCKPOL_POS); - MODIFY_REG(hperh->perh->CON1, USART_CON1_SCKPHA_MSK, init->phase << USART_CON1_SCKPHA_POS); - MODIFY_REG(hperh->perh->CON1, USART_CON1_LBCP_MSK, init->last_bit << USART_CON1_LBCP_POS); - - hperh->err_code = USART_ERROR_NONE; - hperh->state = USART_STATE_READY; - USART_ENABLE(hperh); - - return OK; -} - -/** - * @} - */ - -/** @defgroup USART_Public_Functions_Group2 IO operation functions - * @brief USART Transmit and Receive functions - * @{ - */ - -/** @defgroup USART_Public_Functions_Group2_1 Asynchronization IO operation functions - * @brief Asynchronization IO operation functions - * - * @verbatim - ============================================================================== - ##### IO operation functions ##### - ============================================================================== - [..] - This subsection provides a set of functions allowing to manage the USART asynchronous - and Half duplex data transfers. - - (#) There are two modes of transfer: - (++) Blocking mode: The communication is performed in polling mode. - The Status of all data processing is returned by the same function - after finishing transfer. - (++) Non blocking mode: The communication is performed using Interrupts - or DMA, these APIs return the Status. - The end of the data processing will be indicated through the - dedicated USART IRQ when using Interrupt mode or the DMA IRQ when - using DMA mode. - The hperh->tx_cplt_cbk(), hperh->rx_cplt_cbk() user callbacks - will be executed respectively at the end of the transmit or receive process. - The hperh->error_cbk() user callback will be executed when - a communication error is detected. - - (#) Blocking mode APIs are: - (++) ald_usart_send() - (++) ald_usart_recv() - - (#) Non Blocking mode APIs with Interrupt are: - (++) ald_usart_send_by_it() - (++) ald_usart_recv_by_it() - (++) urart_irq_handle() - - (#) Non Blocking mode functions with DMA are: - (++) ald_usart_send_by_dma() - (++) ald_usart_recv_by_dma() - (++) ald_usart_dma_pause() - (++) ald_usart_dma_resume() - (++) ald_usart_dma_stop() - - (#) A set of Transfer Complete Callbacks are provided in non blocking mode: - (++) hperh->tx_cplt_cbk() - (++) hperh->rx_cplt_cbk() - (++) hperh->error_cbk() - - [..] - (@) In the Half duplex communication, it is forbidden to run the transmit - and receive process in parallel, the USART state USART_STATE_BUSY_TX_RX - can't be useful. - - @endverbatim - * @{ - */ - -/** - * @brief Sends an amount of data in blocking mode. - * @param hperh: Pointer to a usart_handle_t structure that contains - * the configuration information for the specified USART module. - * @param buf: Pointer to data buffer - * @param size: Amount of data to be sent - * @param timeout: Timeout duration - * @retval Status, see @ref ald_status_t. - */ -ald_status_t ald_usart_send(usart_handle_t *hperh, uint8_t *buf, uint16_t size, uint32_t timeout) -{ - if ((hperh->state != USART_STATE_READY) && (hperh->state != USART_STATE_BUSY_RX)) - return BUSY; - - if ((buf == NULL) || (size == 0)) - return ERROR; - - __LOCK(hperh); - hperh->err_code = USART_ERROR_NONE; - SET_BIT(hperh->state, USART_STATE_TX_MASK); - - hperh->tx_size = size; - hperh->tx_count = size; - - while (hperh->tx_count-- > 0) { - if (usart_wait_flag(hperh, USART_FLAG_TXE, SET, timeout) != OK) { - __UNLOCK(hperh); - hperh->state = USART_STATE_READY; - return TIMEOUT; - } - - if (hperh->init.word_length == USART_WORD_LENGTH_9B) { - if (hperh->init.parity == USART_PARITY_NONE) { - WRITE_REG(hperh->perh->DATA, (*(uint16_t *)buf & (uint16_t)0x01FF)); - buf += 2; - } - else { - WRITE_REG(hperh->perh->DATA, *buf++); - } - } - else { - WRITE_REG(hperh->perh->DATA, *buf++); - } - } - - if (usart_wait_flag(hperh, USART_FLAG_TC, SET, timeout) != OK) { - __UNLOCK(hperh); - hperh->state = USART_STATE_READY; - return TIMEOUT; - } - - CLEAR_BIT(hperh->state, USART_STATE_TX_MASK); - __UNLOCK(hperh); - - return OK; -} - -/** - * @brief Receives an amount of data in blocking mode. - * @param hperh: Pointer to a usart_handle_t structure that contains - * the configuration information for the specified USART module. - * @param buf: Pointer to data buffer - * @param size: Amount of data to be received - * @param timeout: Timeout duration - * @retval Status, see @ref ald_status_t. - */ -ald_status_t ald_usart_recv(usart_handle_t *hperh, uint8_t *buf, uint16_t size, uint32_t timeout) -{ - if ((hperh->state != USART_STATE_READY) && (hperh->state != USART_STATE_BUSY_TX)) - return BUSY; - - if ((buf == NULL ) || (size == 0)) - return ERROR; - - __LOCK(hperh); - hperh->err_code = USART_ERROR_NONE; - SET_BIT(hperh->state, USART_STATE_RX_MASK); - - hperh->rx_size = size; - hperh->rx_count = size; - - while (hperh->rx_count-- > 0) { - if (usart_wait_flag(hperh, USART_FLAG_RXNE, SET, timeout) != OK) { - __UNLOCK(hperh); - hperh->state = USART_STATE_READY; - return TIMEOUT; - } - - if (hperh->init.word_length == USART_WORD_LENGTH_9B) { - if (hperh->init.parity == USART_PARITY_NONE) { - *(uint16_t *)buf = (uint16_t)(hperh->perh->DATA & 0x1FF); - buf += 2; - } - else { - *buf = (uint8_t)(hperh->perh->DATA & 0xFF); - buf += 1; - } - } - else { - if (hperh->init.parity == USART_PARITY_NONE) - *buf++ = (uint8_t)(hperh->perh->DATA & 0xFF); - else - *buf++ = (uint8_t)(hperh->perh->DATA & 0x7F); - } - } - - CLEAR_BIT(hperh->state, USART_STATE_RX_MASK); - __UNLOCK(hperh); - - return OK; -} - -/** - * @brief Sends an amount of data in non blocking mode. - * @param hperh: Pointer to a usart_handle_t structure that contains - * the configuration information for the specified USART module. - * @param buf: Pointer to data buffer - * @param size: Amount of data to be sent - * @retval Status, see @ref ald_status_t. - */ -ald_status_t ald_usart_send_by_it(usart_handle_t *hperh, uint8_t *buf, uint16_t size) -{ - if ((hperh->state != USART_STATE_READY) && (hperh->state != USART_STATE_BUSY_RX)) - return BUSY; - - if ((buf == NULL ) || (size == 0)) - return ERROR; - - __LOCK(hperh); - SET_BIT(hperh->state, USART_STATE_TX_MASK); - - hperh->tx_buf = buf; - hperh->tx_size = size; - hperh->tx_count = size; - hperh->err_code = USART_ERROR_NONE; - - __UNLOCK(hperh); - ald_usart_interrupt_config(hperh, USART_IT_TXE, ENABLE); - - return OK; -} - -/** - * @brief Receives an amount of data in non blocking mode - * @param hperh: Pointer to a usart_handle_t structure that contains - * the configuration information for the specified USART module. - * @param buf: Pointer to data buffer - * @param size: Amount of data to be received - * @retval Status, see @ref ald_status_t. - */ -ald_status_t ald_usart_recv_by_it(usart_handle_t *hperh, uint8_t *buf, uint16_t size) -{ - if ((hperh->state != USART_STATE_READY) && (hperh->state != USART_STATE_BUSY_TX)) - return BUSY; - - if ((buf == NULL ) || (size == 0)) - return ERROR; - - __LOCK(hperh); - SET_BIT(hperh->state, USART_STATE_RX_MASK); - - hperh->rx_buf = buf; - hperh->rx_size = size; - hperh->rx_count = size; - hperh->err_code = USART_ERROR_NONE; - - __UNLOCK(hperh); - ald_usart_interrupt_config(hperh, USART_IT_PE, ENABLE); - ald_usart_interrupt_config(hperh, USART_IT_ERR, ENABLE); - ald_usart_interrupt_config(hperh, USART_IT_RXNE, ENABLE); - - return OK; -} - -/** - * @brief Receives an frame in interrupt mode - * @param hperh: Pointer to a usart_handle_t structure that contains - * the configuration information for the specified USART module. - * @param buf: Pointer to data buffer - * @param size: Maximum amount of data to be received - * @retval Status, see @ref ald_status_t. - */ -ald_status_t ald_usart_recv_frame_by_it(usart_handle_t *hperh, uint8_t *buf, uint16_t size) -{ - if ((hperh->state != USART_STATE_READY) && (hperh->state != USART_STATE_BUSY_TX)) - return BUSY; - - if ((buf == NULL ) || (size == 0)) - return ERROR; - - __LOCK(hperh); - SET_BIT(hperh->state, USART_STATE_RX_MASK); - - hperh->rx_buf = buf; - hperh->rx_size = size; - hperh->rx_count = size; - hperh->err_code = USART_ERROR_NONE; - - __UNLOCK(hperh); - ald_usart_interrupt_config(hperh, USART_IT_PE, ENABLE); - ald_usart_interrupt_config(hperh, USART_IT_ERR, ENABLE); - ald_usart_interrupt_config(hperh, USART_IT_RXNE, ENABLE); - __frame_mode = 1; - - return OK; -} - -#ifdef ALD_DMA -/** - * @brief Sends an amount of data in non blocking mode. - * @param hperh: Pointer to a usart_handle_t structure that contains - * the configuration information for the specified USART module. - * @param buf: Pointer to data buffer - * @param size: Amount of data to be sent - * @param channel: DMA channel as USART transmit - * @retval Status, see @ref ald_status_t. - */ -ald_status_t ald_usart_send_by_dma(usart_handle_t *hperh, uint8_t *buf, uint16_t size, uint8_t channel) -{ - if ((hperh->state != USART_STATE_READY) && (hperh->state != USART_STATE_BUSY_RX)) - return BUSY; - - if ((buf == NULL ) || (size == 0)) - return ERROR; - - __LOCK(hperh); - SET_BIT(hperh->state, USART_STATE_TX_MASK); - - hperh->tx_buf = buf; - hperh->tx_size = size; - hperh->tx_count = size; - hperh->err_code = USART_ERROR_NONE; - - if (hperh->hdmatx.perh == NULL) - hperh->hdmatx.perh = DMA0; - - /* Configure callback function */ - hperh->hdmatx.cplt_cbk = usart_dma_send_cplt; - hperh->hdmatx.cplt_arg = (void *)hperh; - hperh->hdmatx.err_cbk = usart_dma_error; - hperh->hdmatx.err_arg = (void *)hperh; - - /* Configure USART DMA transmit */ - ald_dma_config_struct(&hperh->hdmatx.config); - hperh->hdmatx.config.src = (void *)buf; - hperh->hdmatx.config.dst = (void *)&hperh->perh->DATA; - hperh->hdmatx.config.size = size; - hperh->hdmatx.config.src_inc = DMA_DATA_INC_BYTE; - hperh->hdmatx.config.dst_inc = DMA_DATA_INC_NONE; - hperh->hdmatx.config.msel = hperh->perh == USART0 ? DMA_MSEL_USART0 : DMA_MSEL_USART1; - hperh->hdmatx.config.msigsel = DMA_MSIGSEL_USART_TXEMPTY; - hperh->hdmatx.config.channel = channel; - - if ((hperh->init.word_length == USART_WORD_LENGTH_9B) - && (hperh->init.parity == USART_PARITY_NONE)) { - hperh->hdmatx.config.src_inc = DMA_DATA_INC_HALFWORD; - hperh->hdmatx.config.data_width = DMA_DATA_SIZE_HALFWORD; - } - - ald_dma_config_basic(&hperh->hdmatx); - - __UNLOCK(hperh); - ald_usart_clear_flag_status(hperh, USART_FLAG_TC); - SET_BIT(hperh->perh->CON2, USART_CON2_TXDMAEN_MSK); - - return OK; -} - -/** - * @brief Receives an amount of data in non blocking mode. - * @param hperh: Pointer to a usart_handle_t structure that contains - * the configuration information for the specified USART module. - * @param buf: Pointer to data buffer - * @param size: Amount of data to be received - * @param channel: DMA channel as USART receive - * @note When the USART parity is enabled (PCE = 1), the received data contain - * the parity bit (MSB position) - * @retval Status, see @ref ald_status_t. - */ -ald_status_t ald_usart_recv_by_dma(usart_handle_t *hperh, uint8_t *buf, uint16_t size, uint8_t channel) -{ - if ((hperh->state != USART_STATE_READY) && (hperh->state != USART_STATE_BUSY_TX)) - return BUSY; - - if ((buf == NULL ) || (size == 0)) - return ERROR; - - __LOCK(hperh); - SET_BIT(hperh->state, USART_STATE_RX_MASK); - - hperh->rx_buf = buf; - hperh->rx_size = size; - hperh->err_code = USART_ERROR_NONE; - - if (hperh->hdmarx.perh == NULL) - hperh->hdmarx.perh = DMA0; - - /* Configure callback function */ - hperh->hdmarx.cplt_cbk = usart_dma_recv_cplt; - hperh->hdmarx.cplt_arg = (void *)hperh; - hperh->hdmarx.err_cbk = usart_dma_error; - hperh->hdmarx.err_arg = (void *)hperh; - - /* Configure DMA Receive */ - ald_dma_config_struct(&hperh->hdmarx.config); - hperh->hdmarx.config.src = (void *)&hperh->perh->DATA; - hperh->hdmarx.config.dst = (void *)buf; - hperh->hdmarx.config.size = size; - hperh->hdmarx.config.src_inc = DMA_DATA_INC_NONE; - hperh->hdmarx.config.dst_inc = DMA_DATA_INC_BYTE; - hperh->hdmarx.config.msel = hperh->perh == USART0 ? DMA_MSEL_USART0 : DMA_MSEL_USART1; - hperh->hdmarx.config.msigsel = DMA_MSIGSEL_USART_RNR; - hperh->hdmarx.config.channel = channel; - - if ((hperh->init.word_length == USART_WORD_LENGTH_9B) - && (hperh->init.parity == USART_PARITY_NONE)) { - hperh->hdmarx.config.dst_inc = DMA_DATA_INC_HALFWORD; - hperh->hdmarx.config.data_width = DMA_DATA_SIZE_HALFWORD; - } - - ald_dma_config_basic(&hperh->hdmarx); - - __UNLOCK(hperh); - SET_BIT(hperh->perh->CON2, USART_CON2_RXDMAEN_MSK); - - return OK; -} -#endif -/** - * @} - */ - -/** @defgroup USART_Public_Functions_Group2_2 Synchronization IO operation functions - * @brief Synchronization IO operation functions - * - * @verbatim - ============================================================================== - ##### IO operation functions ##### - ============================================================================== - [..] - This subsection provides a set of functions allowing to manage the USART synchronous - data transfers. - - [..] - The USART supports master mode only: it cannot receive or send data related to an input - clock (SCLK is always an output). - - (#) There are two modes of transfer: - (++) Blocking mode: The communication is performed in polling mode. - The Status of all data processing is returned by the same function - after finishing transfer. - (++) No-Blocking mode: The communication is performed using Interrupts - or DMA, These API's return the Status. - The end of the data processing will be indicated through the - dedicated USART IRQ when using Interrupt mode or the DMA IRQ when - using DMA mode. - The hperh->tx_cplt_cbk(), hperh->rx_cplt_cbk() and hperh->tx_rx_cplt_cbk() - user callbacks will be executed respectively at the end of the transmit - or Receive process. The hperh->error_cbk() user callback will be - executed when a communication error is detected - - (#) Blocking mode APIs are : - (++) ald_usart_send_sync() in simplex mode - (++) ald_usart_recv_sync() in full duplex receive only - (++) ald_usart_send_recv_sync() in full duplex mode - - (#) Non Blocking mode APIs with Interrupt are : - (++) ald_usart_send_by_it_sync()in simplex mode - (++) ald_usart_recv_by_it_sync() in full duplex receive only - (++) ald_usart_send_recv_by_it_sync() in full duplex mode - (++) ald_usart_irq_handler() - - (#) Non Blocking mode functions with DMA are : - (++) ald_usart_send_by_dma_sync()in simplex mode - (++) ald_usart_recv_by_dma_sync() in full duplex receive only - (++) usart_send_recv_by_dma_symc() in full duplex mode - (++) ald_usart_dma_pause() - (++) ald_usart_dma_resume() - (++) ald_usart_dma_stop() - - (#) A set of Transfer Complete Callbacks are provided in non Blocking mode: - (++) hperh->tx_cplt_cbk() - (++) hperh->rx_cplt_cbk() - (++) hperh->tx_rx_cplt_cbk() - (++) hperh->error_cbk() - - @endverbatim - * @{ - */ - -/** - * @brief Simplex Send an amount of data in blocking mode. - * @param hperh: Pointer to a usart_handle_t structure that contains - * the configuration information for the specified USART module. - * @param buf: Pointer to data buffer - * @param size: Amount of data to be sent - * @param timeout: Timeout duration - * @retval Status, see @ref ald_status_t. - */ -ald_status_t ald_usart_send_sync(usart_handle_t *hperh, uint8_t *buf, uint16_t size, uint32_t timeout) -{ - if (hperh->state != USART_STATE_READY) - return BUSY; - - if ((buf == NULL) || (size == 0)) - return ERROR; - - __LOCK(hperh); - - hperh->tx_size = size; - hperh->tx_count = size; - hperh->err_code = USART_ERROR_NONE; - hperh->state = USART_STATE_BUSY_TX; - - while (hperh->tx_count-- > 0) { - if (usart_wait_flag(hperh, USART_FLAG_TXE, SET, timeout) != OK) { - __UNLOCK(hperh); - hperh->state = USART_STATE_READY; - return TIMEOUT; - } - - if ((hperh->init.word_length == USART_WORD_LENGTH_9B) && (hperh->init.parity == USART_PARITY_NONE)) { - WRITE_REG(hperh->perh->DATA, (*(uint16_t *)buf & 0x1FF)); - buf += 2; - } - else { - WRITE_REG(hperh->perh->DATA, *buf++); - } - } - - if (usart_wait_flag(hperh, USART_FLAG_TC, SET, timeout) != OK) { - __UNLOCK(hperh); - hperh->state = USART_STATE_READY; - return TIMEOUT; - } - - hperh->state = USART_STATE_READY; - __UNLOCK(hperh); - - return OK; -} - -/** - * @brief Full-Duplex Receive an amount of data in blocking mode. - * @param hperh: Pointer to a usart_handle_t structure that contains - * the configuration information for the specified USART module. - * @param buf: Pointer to data buffer - * @param size: Amount of data to be received - * @param timeout: Timeout duration - * @retval Status, see @ref ald_status_t. - */ -ald_status_t ald_usart_recv_sync(usart_handle_t *hperh, uint8_t *buf, uint16_t size, uint32_t timeout) -{ - if (hperh->state != USART_STATE_READY) - return BUSY; - - if ((buf == NULL) || (size == 0)) - return ERROR; - - __LOCK(hperh); - - hperh->rx_size = size; - hperh->rx_count = size; - hperh->err_code = USART_ERROR_NONE; - hperh->state = USART_STATE_BUSY_RX; - - while (hperh->rx_count-- > 0) { - if (usart_wait_flag(hperh, USART_FLAG_TXE, SET, timeout) != OK) { - __UNLOCK(hperh); - hperh->state = USART_STATE_READY; - return TIMEOUT; - } - - if (hperh->init.word_length == USART_WORD_LENGTH_9B) { - WRITE_REG(hperh->perh->DATA, (DUMMY_DATA & 0x1FF)); - - if (usart_wait_flag(hperh, USART_FLAG_RXNE, SET, timeout) != OK) { - __UNLOCK(hperh); - hperh->state = USART_STATE_READY; - return TIMEOUT; - } - - if (hperh->init.parity == USART_PARITY_NONE) { - *(uint16_t *)buf = (uint16_t)(hperh->perh->DATA & 0x1FF); - buf += 2; - } - else { - *buf++ = (uint8_t)(hperh->perh->DATA & 0xFF); - } - } - else { - WRITE_REG(hperh->perh->DATA, (DUMMY_DATA & 0xFF)); - - if (usart_wait_flag(hperh, USART_FLAG_RXNE, SET, timeout) != OK) { - __UNLOCK(hperh); - hperh->state = USART_STATE_READY; - return TIMEOUT; - } - - if (hperh->init.parity == USART_PARITY_NONE) - *buf++ = (uint8_t)(hperh->perh->DATA & 0xFF); - else - *buf++ = (uint8_t)(hperh->perh->DATA & 0x7F); - } - } - - hperh->state = USART_STATE_READY; - __UNLOCK(hperh); - - return OK; -} - -/** - * @brief Full-Duplex Send receive an amount of data in full-duplex mode (blocking mode). - * @param hperh: Pointer to a usart_handle_t structure that contains - * the configuration information for the specified USART module. - * @param tx_buf: Pointer to data transmitted buffer - * @param rx_buf: Pointer to data received buffer - * @param size: Amount of data to be sent - * @param timeout: Timeout duration - * @retval Status, see @ref ald_status_t. - */ -ald_status_t ald_usart_send_recv_sync(usart_handle_t *hperh, uint8_t *tx_buf, uint8_t *rx_buf, uint16_t size, uint32_t timeout) -{ - if (hperh->state != USART_STATE_READY) - return BUSY; - - if ((tx_buf == NULL) || (rx_buf == NULL) || (size == 0)) - return ERROR; - - __LOCK(hperh); - - hperh->rx_size = size; - hperh->rx_count = size; - hperh->tx_size = size; - hperh->tx_count = size; - hperh->err_code = USART_ERROR_NONE; - hperh->state = USART_STATE_BUSY_RX; - - while (hperh->tx_count-- > 0) { - --hperh->rx_count; - - if (usart_wait_flag(hperh, USART_FLAG_TXE, SET, timeout) != OK) { - __UNLOCK(hperh); - hperh->state = USART_STATE_READY; - return TIMEOUT; - } - - if (hperh->init.word_length == USART_WORD_LENGTH_9B) { - if (hperh->init.parity == USART_PARITY_NONE) { - WRITE_REG(hperh->perh->DATA, (*(uint16_t *)tx_buf & 0x1FF)); - tx_buf += 2; - } - else { - WRITE_REG(hperh->perh->DATA, *tx_buf++); - } - - if (usart_wait_flag(hperh, USART_FLAG_RXNE, SET, timeout) != OK) { - __UNLOCK(hperh); - hperh->state = USART_STATE_READY; - return TIMEOUT; - } - - if (hperh->init.parity == USART_PARITY_NONE) { - *(uint16_t *)rx_buf = (uint16_t)(hperh->perh->DATA & 0x1FF); - rx_buf += 2; - } - else { - *rx_buf++ = (uint8_t)(hperh->perh->DATA & 0xFF); - } - } - else { - WRITE_REG(hperh->perh->DATA, *tx_buf++); - - if (usart_wait_flag(hperh, USART_FLAG_RXNE, SET, timeout) != OK) { - __UNLOCK(hperh); - hperh->state = USART_STATE_READY; - return TIMEOUT; - } - - if (hperh->init.parity == USART_PARITY_NONE) - *rx_buf++ = (uint8_t)(hperh->perh->DATA & 0xFF); - else - *rx_buf++ = (uint8_t)(hperh->perh->DATA & 0x7F); - } - } - - hperh->state = USART_STATE_READY; - __UNLOCK(hperh); - - return OK; -} - -/** - * @brief Simplex Send an amount of data in non-blocking mode. - * @param hperh: Pointer to a usart_handle_t structure that contains - * the configuration information for the specified USART module. - * @param buf: Pointer to data buffer - * @param size: Amount of data to be sent - * @retval Status, see @ref ald_status_t. - * @note The USART errors are not managed to avoid the overrun error. - */ -ald_status_t ald_usart_send_by_it_sync(usart_handle_t *hperh, uint8_t *buf, uint16_t size) -{ - if (hperh->state != USART_STATE_READY) - return BUSY; - - if ((buf == NULL) || (size == 0)) - return ERROR; - - __LOCK(hperh); - - hperh->tx_buf = buf; - hperh->tx_size = size; - hperh->tx_count = size; - hperh->err_code = USART_ERROR_NONE; - hperh->state = USART_STATE_BUSY_TX; - - /* The USART Error Interrupts: (Frame error, Noise error, Overrun error) - * are not managed by the USART transmit process to avoid the overrun interrupt - * when the USART mode is configured for transmit and receive "USART_MODE_TX_RX" - * to benefit for the frame error and noise interrupts the USART mode should be - * configured only for transmit "USART_MODE_TX" - * The __ALD_USART_ENABLE_IT(hperh, USART_IT_ERR) can be used to enable the Frame error, - * Noise error interrupt - */ - - __UNLOCK(hperh); - ald_usart_interrupt_config(hperh, USART_IT_TXE, ENABLE); - - return OK; -} - -/** - * @brief Simplex Receive an amount of data in non-blocking mode. - * @param hperh: Pointer to a usart_handle_t structure that contains - * the configuration information for the specified USART module. - * @param buf: Pointer to data buffer - * @param size: Amount of data to be received - * @retval Status, see @ref ald_status_t. - */ -ald_status_t ald_usart_recv_by_it_sync(usart_handle_t *hperh, uint8_t *buf, uint16_t size) -{ - if (hperh->state != USART_STATE_READY) - return BUSY; - - if ((buf == NULL) || (size == 0)) - return ERROR; - - __LOCK(hperh); - - hperh->rx_buf = buf; - hperh->rx_size = size; - hperh->rx_count = size; - hperh->err_code = USART_ERROR_NONE; - hperh->state = USART_STATE_BUSY_RX; - - __UNLOCK(hperh); - ald_usart_interrupt_config(hperh, USART_IT_RXNE, ENABLE); - ald_usart_interrupt_config(hperh, USART_IT_PE, ENABLE); - ald_usart_interrupt_config(hperh, USART_IT_ERR, ENABLE); - - WRITE_REG(hperh->perh->DATA, (DUMMY_DATA & (uint16_t)0x01FF)); - return OK; -} - -/** - * @brief Full-Duplex Send receive an amount of data in full-duplex mode (non-blocking). - * @param hperh: Pointer to a usart_handle_t structure that contains - * the configuration information for the specified USART module. - * @param tx_buf: Pointer to data transmitted buffer - * @param rx_buf: Pointer to data received buffer - * @param size: Amount of data to be received - * @retval Status, see @ref ald_status_t. - */ -ald_status_t ald_usart_send_recv_by_it_sync(usart_handle_t *hperh, uint8_t *tx_buf, uint8_t *rx_buf, uint16_t size) -{ - if (hperh->state != USART_STATE_READY) - return BUSY; - - if ((tx_buf == NULL) || (rx_buf == NULL) || (size == 0)) - return ERROR; - - __LOCK(hperh); - - hperh->rx_buf = rx_buf; - hperh->rx_size = size; - hperh->rx_count = size; - hperh->tx_buf = tx_buf; - hperh->tx_size = size; - hperh->tx_count = size; - hperh->err_code = USART_ERROR_NONE; - hperh->state = USART_STATE_BUSY_TX_RX; - - __UNLOCK(hperh); - ald_usart_interrupt_config(hperh, USART_IT_RXNE, ENABLE); - ald_usart_interrupt_config(hperh, USART_IT_PE, ENABLE); - ald_usart_interrupt_config(hperh, USART_IT_ERR, ENABLE); - ald_usart_interrupt_config(hperh, USART_IT_TXE, ENABLE); - - return OK; -} - -#ifdef ALD_DMA -/** - * @brief Simplex Send an amount of data in non-blocking mode. - * @param hperh: Pointer to a usart_handle_t structure that contains - * the configuration information for the specified USART module. - * @param buf: Pointer to data buffer - * @param size: Amount of data to be sent - * @param channel: DMA channel as USART transmit - * @retval Status, see @ref ald_status_t. - */ -ald_status_t ald_usart_send_by_dma_sync(usart_handle_t *hperh, uint8_t *buf, uint16_t size, uint8_t channel) -{ - if (hperh->state != USART_STATE_READY) - return BUSY; - - if ((buf == NULL) || (size == 0)) - return ERROR; - - __LOCK(hperh); - - hperh->tx_buf = buf; - hperh->tx_size = size; - hperh->tx_count = size; - hperh->err_code = USART_ERROR_NONE; - hperh->state = USART_STATE_BUSY_TX; - - if (hperh->hdmatx.perh == NULL) - hperh->hdmatx.perh = DMA0; - - /* Configure callback function */ - hperh->hdmatx.cplt_cbk = usart_dma_send_cplt; - hperh->hdmatx.cplt_arg = (void *)hperh; - hperh->hdmatx.err_cbk = usart_dma_error; - hperh->hdmatx.err_arg = (void *)hperh; - - /* Configure DMA transmit */ - ald_dma_config_struct(&hperh->hdmatx.config); - hperh->hdmatx.config.src = (void *)buf; - hperh->hdmatx.config.dst = (void *)&hperh->perh->DATA; - hperh->hdmatx.config.size = size; - hperh->hdmatx.config.src_inc = DMA_DATA_INC_BYTE; - hperh->hdmatx.config.dst_inc = DMA_DATA_INC_NONE; - hperh->hdmatx.config.msel = hperh->perh == USART0 ? DMA_MSEL_USART0 : DMA_MSEL_USART1; - hperh->hdmatx.config.msigsel = DMA_MSIGSEL_USART_TXEMPTY; - hperh->hdmatx.config.channel = channel; - - if ((hperh->init.word_length == USART_WORD_LENGTH_9B) - && (hperh->init.parity == USART_PARITY_NONE)) { - hperh->hdmatx.config.src_inc = DMA_DATA_INC_HALFWORD; - hperh->hdmatx.config.data_width = DMA_DATA_SIZE_HALFWORD; - } - - ald_dma_config_basic(&hperh->hdmatx); - - __UNLOCK(hperh); - ald_usart_clear_flag_status(hperh, USART_FLAG_TC); - SET_BIT(hperh->perh->CON2, USART_CON2_TXDMAEN_MSK); - - return OK; -} - -/** - * @brief Full-Duplex Receive an amount of data in non-blocking mode. - * @param hperh: Pointer to a usart_handle_t structure that contains - * the configuration information for the specified USART module. - * @param buf: Pointer to data buffer - * @param size: Amount of data to be received - * @param tx_channel: DMA channel as USART transmit - * @param rx_channel: DMA channel as USART receive - * @retval Status, see @ref ald_status_t. - * @note The USART DMA transmit channel must be configured in order to generate the clock for the slave. - * @note When the USART parity is enabled (PCE = 1) the data received contain the parity bit. - */ -ald_status_t ald_usart_recv_by_dma_sync(usart_handle_t *hperh, uint8_t *buf, uint16_t size, uint8_t tx_channel, uint8_t rx_channel) -{ - if (hperh->state != USART_STATE_READY) - return BUSY; - - if ((buf == NULL) || (size == 0)) - return ERROR; - - __LOCK(hperh); - - hperh->rx_buf = buf; - hperh->rx_size = size; - hperh->tx_buf = buf; - hperh->tx_size = size; - hperh->err_code = USART_ERROR_NONE; - hperh->state = USART_STATE_BUSY_RX; - - if (hperh->hdmatx.perh == NULL) - hperh->hdmatx.perh = DMA0; - if (hperh->hdmarx.perh == NULL) - hperh->hdmarx.perh = DMA0; - - /* Configure DMA callback function */ - hperh->hdmarx.cplt_cbk = usart_dma_recv_cplt; - hperh->hdmarx.cplt_arg = (void *)hperh; - hperh->hdmarx.err_cbk = usart_dma_error; - hperh->hdmarx.err_arg = (void *)hperh; - - /* Configure DMA receive*/ - ald_dma_config_struct(&hperh->hdmarx.config); - hperh->hdmarx.config.src = (void *)&hperh->perh->DATA; - hperh->hdmarx.config.dst = (void *)buf; - hperh->hdmarx.config.size = size; - hperh->hdmarx.config.src_inc = DMA_DATA_INC_NONE; - hperh->hdmarx.config.dst_inc = DMA_DATA_INC_BYTE; - hperh->hdmarx.config.msel = hperh->perh == USART0 ? DMA_MSEL_USART0 : DMA_MSEL_USART1; - hperh->hdmarx.config.msigsel = DMA_MSIGSEL_USART_RNR; - hperh->hdmarx.config.channel = rx_channel; - - if ((hperh->init.word_length == USART_WORD_LENGTH_9B) - && (hperh->init.parity == USART_PARITY_NONE)) { - hperh->hdmarx.config.dst_inc = DMA_DATA_INC_HALFWORD; - hperh->hdmarx.config.data_width = DMA_DATA_SIZE_HALFWORD; - } - - ald_dma_config_basic(&hperh->hdmarx); - - /* Enable the USART transmit DMA channel: the transmit channel is used in order - * to generate in the non-blocking mode the clock to the slave device, - * this mode isn't a simplex receive mode but a full-duplex receive one - */ - ald_dma_config_struct(&hperh->hdmatx.config); - hperh->hdmatx.config.src = (void *)buf; - hperh->hdmatx.config.dst = (void *)&hperh->perh->DATA; - hperh->hdmatx.config.size = size; - hperh->hdmatx.config.src_inc = DMA_DATA_INC_BYTE; - hperh->hdmatx.config.dst_inc = DMA_DATA_INC_NONE; - hperh->hdmatx.config.msel = hperh->perh == USART0 ? DMA_MSEL_USART0 : DMA_MSEL_USART1; - hperh->hdmatx.config.msigsel = DMA_MSIGSEL_USART_TXEMPTY; - hperh->hdmatx.config.channel = tx_channel; - - if ((hperh->init.word_length == USART_WORD_LENGTH_9B) - && (hperh->init.parity == USART_PARITY_NONE)) { - hperh->hdmatx.config.src_inc = DMA_DATA_INC_HALFWORD; - hperh->hdmatx.config.data_width = DMA_DATA_SIZE_HALFWORD; - } - - ald_dma_config_basic(&hperh->hdmatx); - - USART_CLEAR_OREFLAG(hperh); - __UNLOCK(hperh); - SET_BIT(hperh->perh->CON2, USART_CON2_RXDMAEN_MSK); - SET_BIT(hperh->perh->CON2, USART_CON2_TXDMAEN_MSK); - - return OK; -} - -/** - * @brief Full-Duplex Transmit Receive an amount of data in non-blocking mode. - * @param hperh: Pointer to a usart_handle_t structure that contains - * the configuration information for the specified USART module. - * @param tx_buf: Pointer to data transmitted buffer - * @param rx_buf: Pointer to data received buffer - * @param size: Amount of data to be received - * @param tx_channel: DMA channel as USART transmit - * @param rx_channel: DMA channel as USART receive - * @note When the USART parity is enabled (PCE = 1) the data received contain the parity bit. - * @retval Status, see @ref ald_status_t. - */ -ald_status_t ald_usart_send_recv_by_dma_sync(usart_handle_t *hperh, uint8_t *tx_buf, - uint8_t *rx_buf, uint16_t size, uint8_t tx_channel, uint8_t rx_channel) -{ - if (hperh->state != USART_STATE_READY) - return BUSY; - - if ((tx_buf == NULL) || (rx_buf == NULL) || (size == 0)) - return ERROR; - - __LOCK(hperh); - - hperh->rx_buf = rx_buf; - hperh->rx_size = size; - hperh->tx_buf = tx_buf; - hperh->tx_size = size; - hperh->err_code = USART_ERROR_NONE; - hperh->state = USART_STATE_BUSY_TX_RX; - - if (hperh->hdmatx.perh == NULL) - hperh->hdmatx.perh = DMA0; - if (hperh->hdmarx.perh == NULL) - hperh->hdmarx.perh = DMA0; - - /* Configure DMA callback function */ - hperh->hdmarx.cplt_cbk = usart_dma_recv_cplt; - hperh->hdmarx.cplt_arg = (void *)hperh; - hperh->hdmatx.cplt_cbk = usart_dma_send_cplt; - hperh->hdmatx.cplt_arg = (void *)hperh; - hperh->hdmatx.err_cbk = usart_dma_error; - hperh->hdmatx.err_arg = (void *)hperh; - hperh->hdmarx.err_cbk = usart_dma_error; - hperh->hdmarx.err_arg = (void *)hperh; - - /* Configure DMA receive */ - ald_dma_config_struct(&hperh->hdmarx.config); - hperh->hdmarx.config.src = (void *)&hperh->perh->DATA; - hperh->hdmarx.config.dst = (void *)rx_buf; - hperh->hdmarx.config.size = size; - hperh->hdmarx.config.src_inc = DMA_DATA_INC_NONE; - hperh->hdmarx.config.dst_inc = DMA_DATA_INC_BYTE; - hperh->hdmarx.config.msel = hperh->perh == USART0 ? DMA_MSEL_USART0 : DMA_MSEL_USART1; - hperh->hdmarx.config.msigsel = DMA_MSIGSEL_USART_RNR; - hperh->hdmarx.config.channel = rx_channel; - - if ((hperh->init.word_length == USART_WORD_LENGTH_9B) - && (hperh->init.parity == USART_PARITY_NONE)) { - hperh->hdmarx.config.dst_inc = DMA_DATA_INC_HALFWORD; - hperh->hdmarx.config.data_width = DMA_DATA_SIZE_HALFWORD; - } - - ald_dma_config_basic(&hperh->hdmarx); - - /* Configure DMA transmit*/ - ald_dma_config_struct(&hperh->hdmatx.config); - hperh->hdmatx.config.src = (void *)tx_buf; - hperh->hdmatx.config.dst = (void *)&hperh->perh->DATA; - hperh->hdmatx.config.size = size; - hperh->hdmatx.config.src_inc = DMA_DATA_INC_BYTE; - hperh->hdmatx.config.dst_inc = DMA_DATA_INC_NONE; - hperh->hdmatx.config.msel = hperh->perh == USART0 ? DMA_MSEL_USART0 : DMA_MSEL_USART1; - hperh->hdmatx.config.msigsel = DMA_MSIGSEL_USART_TXEMPTY; - hperh->hdmatx.config.channel = tx_channel; - - if ((hperh->init.word_length == USART_WORD_LENGTH_9B) - && (hperh->init.parity == USART_PARITY_NONE)) { - hperh->hdmatx.config.src_inc = DMA_DATA_INC_HALFWORD; - hperh->hdmatx.config.data_width = DMA_DATA_SIZE_HALFWORD; - } - - ald_dma_config_basic(&hperh->hdmatx); - - ald_usart_clear_flag_status(hperh, USART_FLAG_TC); - USART_CLEAR_OREFLAG(hperh); - __UNLOCK(hperh); - SET_BIT(hperh->perh->CON2, USART_CON2_RXDMAEN_MSK); - SET_BIT(hperh->perh->CON2, USART_CON2_TXDMAEN_MSK); - - return OK; -} -#endif -/** - * @} - */ - -/** @defgroup USART_Public_Functions_Group2_3 Utilities functions - * @brief Utilities functions - * @{ - */ -#ifdef ALD_DMA -/** - * @brief Pauses the DMA Transfer. - * @param hperh: Pointer to a usart_handle_t structure that contains - * the configuration information for the specified USART module. - * @retval Status, see @ref ald_status_t. - */ -ald_status_t ald_usart_dma_pause(usart_handle_t *hperh) -{ - __LOCK(hperh); - - if (hperh->state == USART_STATE_BUSY_TX) { - CLEAR_BIT(hperh->perh->CON2, USART_CON2_TXDMAEN_MSK); - } - else if (hperh->state == USART_STATE_BUSY_RX) { - CLEAR_BIT(hperh->perh->CON2, USART_CON2_RXDMAEN_MSK); - } - else if (hperh->state == USART_STATE_BUSY_TX_RX) { - CLEAR_BIT(hperh->perh->CON2, USART_CON2_TXDMAEN_MSK); - CLEAR_BIT(hperh->perh->CON2, USART_CON2_RXDMAEN_MSK); - } - else { - __UNLOCK(hperh); - return ERROR; - } - - __UNLOCK(hperh); - return OK; -} - -/** - * @brief Resumes the DMA Transfer. - * @param hperh: Pointer to a usart_handle_t structure that contains - * the configuration information for the specified USART module. - * @retval Status, see @ref ald_status_t. - */ -ald_status_t ald_usart_dma_resume(usart_handle_t *hperh) -{ - __LOCK(hperh); - - if (hperh->state == USART_STATE_BUSY_TX) { - SET_BIT(hperh->perh->CON2, USART_CON2_TXDMAEN_MSK); - } - else if (hperh->state == USART_STATE_BUSY_RX) { - USART_CLEAR_OREFLAG(hperh); - SET_BIT(hperh->perh->CON2, USART_CON2_RXDMAEN_MSK); - } - else if (hperh->state == USART_STATE_BUSY_TX_RX) { - USART_CLEAR_OREFLAG(hperh); - SET_BIT(hperh->perh->CON2, USART_CON2_TXDMAEN_MSK); - SET_BIT(hperh->perh->CON2, USART_CON2_RXDMAEN_MSK); - } - else { - __UNLOCK(hperh); - return ERROR; - } - - __UNLOCK(hperh); - return OK; -} - -/** - * @brief Stops the DMA Transfer. - * @param hperh: Pointer to a usart_handle_t structure that contains - * the configuration information for the specified USART module. - * @retval Status, see @ref ald_status_t. - */ -ald_status_t ald_usart_dma_stop(usart_handle_t *hperh) -{ - CLEAR_BIT(hperh->perh->CON2, USART_CON2_TXDMAEN_MSK); - CLEAR_BIT(hperh->perh->CON2, USART_CON2_RXDMAEN_MSK); - - hperh->state = USART_STATE_READY; - return OK; -} -#endif -/** - * @brief This function handles USART interrupt request. - * @param hperh: Pointer to a usart_handle_t structure that contains - * the configuration information for the specified USART module. - * @retval None - */ -void ald_usart_irq_handler(usart_handle_t *hperh) -{ - uint32_t flag; - uint32_t source; - - /* Handle parity error */ - flag = ald_usart_get_flag_status(hperh, USART_FLAG_PE); - source = ald_usart_get_it_status(hperh, USART_IT_PE); - if ((flag != RESET) && (source != RESET)) - hperh->err_code |= USART_ERROR_PE; - - /* Handle frame error */ - flag = ald_usart_get_flag_status(hperh, USART_FLAG_FE); - source = ald_usart_get_it_status(hperh, USART_IT_ERR); - if ((flag != RESET) && (source != RESET)) - hperh->err_code |= USART_ERROR_FE; - - /* Handle noise error */ - flag = ald_usart_get_flag_status(hperh, USART_FLAG_NE); - if ((flag != RESET) && (source != RESET)) - hperh->err_code |= USART_ERROR_NE; - - /* Handle overrun error */ - flag = ald_usart_get_flag_status(hperh, USART_FLAG_ORE); - if ((flag != RESET) && (source != RESET)) - hperh->err_code |= USART_ERROR_ORE; - - /* Handle idle error */ - flag = ald_usart_get_flag_status(hperh, USART_FLAG_IDLE); - source = ald_usart_get_it_status(hperh, USART_IT_IDLE); - if ((flag != RESET) && (source != RESET)) - __usart_recv_frame_cplt(hperh); - - /* Handle asynchronous */ - if (READ_BIT(hperh->perh->CON1, USART_CON1_SCKEN_MSK) == 0) { - /* Receiver */ - flag = ald_usart_get_flag_status(hperh, USART_FLAG_RXNE); - source = ald_usart_get_it_status(hperh, USART_IT_RXNE); - if ((flag != RESET) && (source != RESET)) - __usart_recv_by_it(hperh); - - /* Transmitter */ - flag = ald_usart_get_flag_status(hperh, USART_FLAG_TXE); - source = ald_usart_get_it_status(hperh, USART_IT_TXE); - if ((flag != RESET) && (source != RESET)) - __usart_send_by_it(hperh); - } - else { /* Handle synchronous */ - /* Receiver */ - flag = ald_usart_get_flag_status(hperh, USART_FLAG_RXNE); - source = ald_usart_get_it_status(hperh, USART_IT_RXNE); - if ((flag != RESET) && (source != RESET)) { - if (hperh->state == USART_STATE_BUSY_RX) - __usart_recv_by_it_sync(hperh); - else - __usart_send_recv_by_it_sync(hperh); - } - - /* Transmitter */ - flag = ald_usart_get_flag_status(hperh, USART_FLAG_TXE); - source = ald_usart_get_it_status(hperh, USART_IT_TXE); - if ((flag != RESET) && (source != RESET)) { - if (hperh->state == USART_STATE_BUSY_TX) - __usart_send_by_it(hperh); - else - __usart_send_recv_by_it_sync(hperh); - } - } - - /* Handle transmitter end */ - flag = ald_usart_get_flag_status(hperh, USART_FLAG_TC); - source = ald_usart_get_it_status(hperh, USART_IT_TC); - if ((flag != RESET) && (source != RESET)) - __usart_end_send_by_it(hperh); - - /* Handle error */ - if (hperh->err_code != USART_ERROR_NONE) { - USART_CLEAR_PEFLAG(hperh); - hperh->state = USART_STATE_READY; - - if (hperh->error_cbk != NULL) - hperh->error_cbk(hperh); - } -} - -/** - * @} - */ - -/** - * @} - */ - -/** @defgroup USART_Public_Functions_Group3 Peripheral Control functions - * @brief USART control functions - * - * @verbatim - ============================================================================== - ##### Peripheral Control functions ##### - ============================================================================== - [..] - This subsection provides a set of functions allowing to control the USART: - (+) usart_lin_send_break() API can be helpful to transmit the break character. - (+) ald_usart_multi_processor_enter_mute_mode() API can be helpful to enter the USART in mute mode. - (+) ald_usart_multi_processor_exit_mute_mode() API can be helpful to exit the USART mute mode by software. - (+) ald_usart_half_duplex_enable_send() API to enable the USART transmitter and disables the USART receiver in Half Duplex mode - (+) ald_usart_half_duplex_enable_recv() API to enable the USART receiver and disables the USART transmitter in Half Duplex mode - (+) ald_usart_interrupt_config() API to Enables/Disables the specified USART interrupts - (+) ald_usart_get_flag_status() API to get USART flag status - (+) ald_usart_clear_flag_status() API to clear USART flag status - (+) ald_usart_get_it_status() API to Checks whether the specified USART interrupt has occurred or not - - @endverbatim - * @{ - */ - -/** - * @brief Enters the USART in mute mode. - * @param hperh: Pointer to a usart_handle_t structure that contains - * the configuration information for the specified USART module. - * @retval Status, see @ref ald_status_t. - */ -ald_status_t ald_usart_multi_processor_enter_mute_mode(usart_handle_t *hperh) -{ - assert_param(IS_USART(hperh->perh)); - - __LOCK(hperh); - - hperh->state = USART_STATE_BUSY; - SET_BIT(hperh->perh->CON0, USART_CON0_RXWK_MSK); - hperh->state = USART_STATE_READY; - - __UNLOCK(hperh); - return OK; -} - -/** - * @brief Exits the USART mute mode: wake up software. - * @param hperh: Pointer to a usart_handle_t structure that contains - * the configuration information for the specified USART module. - * @retval Status, see @ref ald_status_t. - */ -ald_status_t ald_usart_multi_processor_exit_mute_mode(usart_handle_t *hperh) -{ - assert_param(IS_USART(hperh->perh)); - - __LOCK(hperh); - - hperh->state = USART_STATE_BUSY; - CLEAR_BIT(hperh->perh->CON0, USART_CON0_RXWK_MSK); - hperh->state = USART_STATE_READY; - - __UNLOCK(hperh); - return OK; -} - -/** - * @brief Enables the USART transmitter and disables the USART receiver. - * @param hperh: Pointer to a usart_handle_t structure that contains - * the configuration information for the specified USART module. - * @retval Status, see @ref ald_status_t. - */ -ald_status_t ald_usart_half_duplex_enable_send(usart_handle_t *hperh) -{ - __LOCK(hperh); - - hperh->state = USART_STATE_BUSY; - SET_BIT(hperh->perh->CON0, USART_CON0_RXEN_MSK); - SET_BIT(hperh->perh->CON0, USART_CON0_TXEN_MSK); - hperh->state = USART_STATE_READY; - - __UNLOCK(hperh); - return OK; -} - -/** - * @brief Enables the USART receiver and disables the USART transmitter. - * @param hperh: Pointer to a usart_handle_t structure that contains - * the configuration information for the specified USART module. - * @retval Status, see @ref ald_status_t. - */ -ald_status_t ald_usart_half_duplex_enable_recv(usart_handle_t *hperh) -{ - __LOCK(hperh); - - hperh->state = USART_STATE_BUSY; - SET_BIT(hperh->perh->CON0, USART_CON0_RXEN_MSK); - SET_BIT(hperh->perh->CON0, USART_CON0_TXEN_MSK); - hperh->state = USART_STATE_READY; - - __UNLOCK(hperh); - return OK; -} - -/** - * @brief Enables or disables the USART's DMA request. - * @param hperh: Pointer to a usart_handle_t structure that contains - * the configuration information for the specified USART module. - * @param req: specifies the DMA request. - * @arg USART_dma_req_tx: USART DMA transmit request - * @arg USART_dma_req_rx: USART DMA receive request - * @param state: New state of the DMA Request sources. - * @arg ENABLE - * @arg DISABLE - * @return: None - */ -void ald_usart_dma_req_config(usart_handle_t *hperh, usart_dma_req_t req, type_func_t state) -{ - assert_param(IS_USART(hperh->perh)); - assert_param(IS_USART_DMAREQ(req)); - assert_param(IS_FUNC_STATE(state)); - - if (state != DISABLE) - SET_BIT(hperh->perh->CON2, req); - else - CLEAR_BIT(hperh->perh->CON2, req); - - return; -} - -/** - * @brief Enables or disables the specified USART interrupts. - * @param hperh: Pointer to a usart_handle_t structure that contains - * the configuration information for the specified USART module. - * @param it: Specifies the USART interrupt sources to be enabled or disabled. - * This parameter can be one of the following values: - * @arg USART_IT_CTS: CTS change interrupt - * @arg USART_IT_LBD: LIN Break detection interrupt - * @arg USART_IT_TXE: Transmit Data Register empty interrupt - * @arg USART_IT_TC: Transmission complete interrupt - * @arg USART_IT_RXNE: Receive Data register not empty interrupt - * @arg USART_IT_IDLE: Idle line detection interrupt - * @arg USART_IT_PE: Parity Error interrupt - * @arg USART_IT_ERR: Error interrupt(Frame error, noise error, overrun error) - * @param state: New status - * - ENABLE - * - DISABLE - * @retval None - */ -void ald_usart_interrupt_config(usart_handle_t *hperh, usart_it_t it, type_func_t state) -{ - uint8_t idx; - - assert_param(IS_USART(hperh->perh)); - assert_param(IS_USART_CONFIG_IT(it)); - assert_param(IS_FUNC_STATE(state)); - - idx = (it >> 16) & 0x7; - it &= 0xFFFF; - - if (state) { - if (idx == 1) - SET_BIT(hperh->perh->CON0, it); - else if (idx == 2) - SET_BIT(hperh->perh->CON1, it); - else if (idx == 4) - SET_BIT(hperh->perh->CON2, it); - else - ; - } - else { - if (idx == 1) - CLEAR_BIT(hperh->perh->CON0, it); - else if (idx == 2) - CLEAR_BIT(hperh->perh->CON1, it); - else if (idx == 4) - CLEAR_BIT(hperh->perh->CON2, it); - else - ; - } - - return; -} - -/** @brief Check whether the specified USART flag is set or not. - * @param hperh: Pointer to a usart_handle_t structure that contains - * the configuration information for the specified USART module. - * @param flag: specifies the flag to check. - * This parameter can be one of the @ref usart_flag_t. - * @retval Status - * - SET - * - RESET - */ -flag_status_t ald_usart_get_flag_status(usart_handle_t *hperh, usart_flag_t flag) -{ - flag_status_t status = RESET; - - assert_param(IS_USART(hperh->perh)); - assert_param(IS_USART_FLAG(flag)); - - if (READ_BIT(hperh->perh->STAT, flag)) - status = SET; - - return status; -} - -/** @brief Clear the specified USART pending flags. - * @param hperh: Pointer to a usart_handle_t structure that contains - * the configuration information for the specified USART module. - * @param flag: specifies the flag to check. - * This parameter can be any combination of the following values: - * @arg USART_FLAG_TC: Transmission Complete flag. - * @arg USART_FLAG_RXNE: Receive data register not empty flag. - * @note PE (Parity error), FE (Framing error), NE (Noise error), ORE (OverRun - * error) and IDLE (Idle line detected) flags are cleared by software - * sequence: a read operation to USART_SR register followed by a read - * operation to USART_DR register. - * @note RXNE flag can be also cleared by a read to the USART_DR register. - * @note TC flag can be also cleared by software sequence: a read operation to - * USART_SR register followed by a write operation to USART_DR register. - * @note TXE flag is cleared only by a write to the USART_DR register. - * @retval None - */ -void ald_usart_clear_flag_status(usart_handle_t *hperh, usart_flag_t flag) -{ - assert_param(IS_USART(hperh->perh)); - assert_param(IS_USART_CLEAR_FLAG(flag)); - - CLEAR_BIT(hperh->perh->STAT, flag); -} - -/** - * @brief Checks whether the specified USART interrupt has occurred or not. - * @param hperh: Pointer to a usart_handle_t structure that contains - * the configuration information for the specified USART module. - * @param it: Specifies the USART interrupt source to check. - * This parameter can be one of the following values: - * @arg USART_IT_CTS: CTS change interrupt - * @arg USART_IT_LBD: LIN Break detection interrupt - * @arg USART_IT_TXE: Tansmit Data Register empty interrupt - * @arg USART_IT_TC: Transmission complete interrupt - * @arg USART_IT_RXNE: Receive Data register not empty interrupt - * @arg USART_IT_IDLE: Idle line detection interrupt - * @arg USART_IT_ORE: OverRun Error interrupt - * @arg USART_IT_NE: Noise Error interrupt - * @arg USART_IT_FE: Framing Error interrupt - * @arg USART_IT_PE: Parity Error interrupt - * @retval Status - * - SET - * - RESET - */ -it_status_t ald_usart_get_it_status(usart_handle_t *hperh, usart_it_t it) -{ - uint8_t idx; - it_status_t status = RESET; - - /* Check the parameters */ - assert_param(IS_USART(hperh->perh)); - assert_param(IS_USART_GET_IT(it)); - - idx = (it >> 16) & 0x7; - it &= 0xFFFF; - - if (idx == 0) { - if (READ_BIT(hperh->perh->STAT, it)) - status = SET; - } - else if (idx == 1) { - if (READ_BIT(hperh->perh->CON0, it)) - status = SET; - } - else if (idx == 2) { - if (READ_BIT(hperh->perh->CON1, it)) - status = SET; - } - else if (idx == 4) { - if (READ_BIT(hperh->perh->CON2, it)) - status = SET; - } - else { - /* do nothing */ - } - - return status; -} - -/** - * @} - */ - -/** @defgroup USART_Public_Functions_Group4 Peripheral State and Errors functions - * @brief USART State and Errors functions - * -@verbatim - ============================================================================== - ##### Peripheral State and Errors functions ##### - ============================================================================== - [..] - This subsection provides a set of functions allowing to return the State of - USART communication process, return Peripheral Errors occurred during communication - process - (+) ald_usart_get_state() API can be helpful to check in run-time the state of the USART peripheral. - (+) ald_usart_get_error() check in run-time errors that could be occurred during communication. - -@endverbatim - * @{ - */ - -/** - * @brief Returns the USART state. - * @param hperh: Pointer to a usart_handle_t structure that contains - * the configuration information for the specified USART module. - * @retval USART state - */ -usart_state_t ald_usart_get_state(usart_handle_t *hperh) -{ - return hperh->state; -} - -/** - * @brief Return the USART error code - * @param hperh: Pointer to a usart_handle_t structure that contains - * the configuration information for the specified USART. - * @retval USART Error Code - */ -uint32_t ald_usart_get_error(usart_handle_t *hperh) -{ - return hperh->err_code; -} - -/** - * @} - */ - -/** - * @} - */ - -/** @defgroup USART_Private_Functions USART Private Functions - * @brief USART Private functions - * @{ - */ -#ifdef ALD_DMA -/** - * @brief DMA USART transmit process complete callback. - * @param arg: Pointer to a usart_handle_t structure that contains - * the configuration information for the specified USART module. - * @retval None - */ -static void usart_dma_send_cplt(void *arg) -{ - usart_handle_t *hperh = (usart_handle_t *)arg; - - hperh->tx_count = 0; - CLEAR_BIT(hperh->perh->CON2, USART_CON2_TXDMAEN_MSK); - ald_usart_interrupt_config(hperh, USART_IT_TC, ENABLE); -} - -/** - * @brief DMA USART receive process complete callback. - * @param arg: Pointer to a usart_handle_t structure that contains - * the configuration information for the specified USART module. - * @retval None - */ -static void usart_dma_recv_cplt(void *arg) -{ - usart_handle_t *hperh = (usart_handle_t *)arg; - - hperh->rx_count = 0; - CLEAR_BIT(hperh->perh->CON2, USART_CON2_RXDMAEN_MSK); - CLEAR_BIT(hperh->state, USART_STATE_RX_MASK); - - if (hperh->rx_cplt_cbk != NULL) - hperh->rx_cplt_cbk(hperh); -} - -/** - * @brief DMA USART communication error callback. - * @param arg: Pointer to a usart_handle_t structure that contains - * the configuration information for the specified USART module. - * @retval None - */ -static void usart_dma_error(void *arg) -{ - usart_handle_t *hperh = (usart_handle_t *)arg; - - hperh->rx_count = 0; - hperh->tx_count = 0; - hperh->state = USART_STATE_READY; - hperh->err_code |= USART_ERROR_DMA; - - CLEAR_BIT(hperh->perh->CON2, USART_CON2_TXDMAEN_MSK); - CLEAR_BIT(hperh->perh->CON2, USART_CON2_RXDMAEN_MSK); - - if (hperh->error_cbk != NULL) - hperh->error_cbk(hperh); -} -#endif -/** - * @brief This function handles USART Communication Timeout. - * @param hperh: Pointer to a usart_handle_t structure that contains - * the configuration information for the specified USART module. - * @param flag: specifies the USART flag to check. - * @param status: The new Flag status (SET or RESET). - * @param timeout: Timeout duration - * @retval Status, see @ref ald_status_t. - */ -static ald_status_t usart_wait_flag(usart_handle_t *hperh, usart_flag_t flag, flag_status_t status, uint32_t timeout) -{ - uint32_t tick; - - if (timeout == 0) - return OK; - - tick = ald_get_tick(); - - while ((ald_usart_get_flag_status(hperh, flag)) != status) { - if (((ald_get_tick()) - tick) > timeout) { - ald_usart_interrupt_config(hperh, USART_IT_TXE, DISABLE); - ald_usart_interrupt_config(hperh, USART_IT_RXNE, DISABLE); - ald_usart_interrupt_config(hperh, USART_IT_PE, DISABLE); - ald_usart_interrupt_config(hperh, USART_IT_ERR, DISABLE); - - return TIMEOUT; - } - } - - return OK; -} - -/** - * @brief Sends an amount of data in non blocking mode. - * @param hperh: Pointer to a usart_handle_t structure that contains - * the configuration information for the specified USART module. - * @retval Status, see @ref ald_status_t. - */ -static ald_status_t __usart_send_by_it(usart_handle_t *hperh) -{ - if ((hperh->state != USART_STATE_BUSY_TX) && (hperh->state != USART_STATE_BUSY_TX_RX)) - return BUSY; - - if ((hperh->init.word_length == USART_WORD_LENGTH_9B) && (hperh->init.parity == USART_PARITY_NONE)) { - WRITE_REG(hperh->perh->DATA, (uint16_t)(*(uint16_t *)hperh->tx_buf & (uint16_t)0x01FF)); - hperh->tx_buf += 2; - } - else { - WRITE_REG(hperh->perh->DATA, *hperh->tx_buf++); - } - - if (--hperh->tx_count == 0) { - ald_usart_interrupt_config(hperh, USART_IT_TXE, DISABLE); - ald_usart_interrupt_config(hperh, USART_IT_TC, ENABLE); - } - - return OK; -} - - -/** - * @brief Wraps up transmission in non blocking mode. - * @param hperh: pointer to a usart_handle_t structure that contains - * the configuration information for the specified USART module. - * @retval Status, see @ref ald_status_t. - */ -static ald_status_t __usart_end_send_by_it(usart_handle_t *hperh) -{ - ald_usart_interrupt_config(hperh, USART_IT_TC, DISABLE); - CLEAR_BIT(hperh->state, USART_STATE_TX_MASK); - - if (hperh->tx_cplt_cbk != NULL) - hperh->tx_cplt_cbk(hperh); - - return OK; -} - -/** - * @brief Receives an amount of data in non blocking mode - * @param hperh: Pointer to a usart_handle_t structure that contains - * the configuration information for the specified USART module. - * @retval Status, see @ref ald_status_t. - */ -static ald_status_t __usart_recv_by_it(usart_handle_t *hperh) -{ - if ((hperh->state != USART_STATE_BUSY_RX) && (hperh->state != USART_STATE_BUSY_TX_RX)) - return BUSY; - - if (hperh->init.word_length == USART_WORD_LENGTH_9B) { - if (hperh->init.parity == USART_PARITY_NONE) { - *(uint16_t *)hperh->rx_buf = (uint16_t)(hperh->perh->DATA & (uint16_t)0x01FF); - hperh->rx_buf += 2; - } - else { - *hperh->rx_buf++ = (uint8_t)(hperh->perh->DATA & 0xFF); - } - } - else { - if (hperh->init.parity == USART_PARITY_NONE) - *hperh->rx_buf++ = (uint8_t)(hperh->perh->DATA & 0xFF); - else - *hperh->rx_buf++ = (uint8_t)(hperh->perh->DATA & 0x7F); - } - - if (__frame_mode && ((ald_usart_get_it_status(hperh, USART_IT_IDLE)) == RESET)) - ald_usart_interrupt_config(hperh, USART_IT_IDLE, ENABLE); - - if (--hperh->rx_count == 0) { - ald_usart_interrupt_config(hperh, USART_IT_RXNE, DISABLE); - CLEAR_BIT(hperh->state, USART_STATE_RX_MASK); - __frame_mode = 0; - - if (hperh->state == USART_STATE_READY) { - ald_usart_interrupt_config(hperh, USART_IT_PE, DISABLE); - ald_usart_interrupt_config(hperh, USART_IT_ERR, DISABLE); - } - - if (hperh->rx_cplt_cbk != NULL) - hperh->rx_cplt_cbk(hperh); - } - - return OK; -} - -/** - * @brief Receives an frame complete in non blocking mode - * @param hperh: Pointer to a usart_handle_t structure that contains - * the configuration information for the specified USART module. - * @retval Status, see @ref ald_status_t. - */ -static ald_status_t __usart_recv_frame_cplt(usart_handle_t *hperh) -{ - if ((hperh->state != USART_STATE_BUSY_RX) && (hperh->state != USART_STATE_BUSY_TX_RX)) - return BUSY; - - ald_usart_interrupt_config(hperh, USART_IT_IDLE, DISABLE); - ald_usart_interrupt_config(hperh, USART_IT_RXNE, DISABLE); - CLEAR_BIT(hperh->state, USART_STATE_RX_MASK); - - __frame_mode = 0; - hperh->rx_size -= hperh->rx_count; - - if (hperh->state == USART_STATE_READY) { - ald_usart_interrupt_config(hperh, USART_IT_PE, DISABLE); - ald_usart_interrupt_config(hperh, USART_IT_ERR, DISABLE); - } - - if (hperh->rx_cplt_cbk != NULL) - hperh->rx_cplt_cbk(hperh); - - return OK; -} - - - -/** - * @brief Simplex Receive an amount of data in non-blocking mode. - * @param hperh: Pointer to a usart_handle_t structure that contains - * the configuration information for the specified USART module. - * @retval Status, see @ref ald_status_t. - */ -static ald_status_t __usart_recv_by_it_sync(usart_handle_t *hperh) -{ - if (hperh->state != USART_STATE_BUSY_RX) - return BUSY; - - if (hperh->init.word_length == USART_WORD_LENGTH_9B) { - - if (hperh->init.parity == USART_PARITY_NONE) { - *(uint16_t *)hperh->rx_buf = (uint16_t)(hperh->perh->DATA & 0x1FF); - hperh->rx_buf += 2; - } - else { - *hperh->rx_buf++ = (uint8_t)(hperh->perh->DATA & 0xFF); - } - - if (--hperh->rx_count != 0x00) - WRITE_REG(hperh->perh->DATA, (DUMMY_DATA & 0x1FF)); - } - else { - if (hperh->init.parity == USART_PARITY_NONE) - *hperh->rx_buf++ = (uint8_t)(hperh->perh->DATA & 0xFF); - else - *hperh->rx_buf++ = (uint8_t)(hperh->perh->DATA & 0x7F); - - if (--hperh->rx_count != 0x00) - hperh->perh->DATA = (DUMMY_DATA & 0xFF); - } - - if (hperh->rx_count == 0) { - ald_usart_interrupt_config(hperh, USART_IT_RXNE, DISABLE); - ald_usart_interrupt_config(hperh, USART_IT_PE, DISABLE); - ald_usart_interrupt_config(hperh, USART_IT_ERR, DISABLE); - hperh->state = USART_STATE_READY; - - if (hperh->rx_cplt_cbk != NULL) - hperh->rx_cplt_cbk(hperh); - } - - return OK; -} - -/** - * @brief Full-Duplex Send receive an amount of data in full-duplex mode (non-blocking). - * @param hperh: Pointer to a usart_handle_t structure that contains - * the configuration information for the specified USART module. - * @retval Status, see @ref ald_status_t. - */ -static ald_status_t __usart_send_recv_by_it_sync(usart_handle_t *hperh) -{ - if (hperh->state != USART_STATE_BUSY_TX_RX) - return BUSY; - - if (hperh->tx_count != 0) { - if (ald_usart_get_flag_status(hperh, USART_FLAG_TXE) != RESET) { - if (hperh->init.word_length == USART_WORD_LENGTH_9B) { - if (hperh->init.parity == USART_PARITY_NONE) { - WRITE_REG(hperh->perh->DATA, (uint16_t)(*(uint16_t *)hperh->tx_buf & 0x1FF)); - hperh->tx_buf += 2; - } - else { - WRITE_REG(hperh->perh->DATA, *hperh->tx_buf++); - } - } - else { - WRITE_REG(hperh->perh->DATA, *hperh->tx_buf++); - } - - if (--hperh->tx_count == 0) - ald_usart_interrupt_config(hperh, USART_IT_TXE, DISABLE); - } - } - - if (hperh->rx_count != 0) { - if (ald_usart_get_flag_status(hperh, USART_FLAG_RXNE) != RESET) { - if (hperh->init.word_length == USART_WORD_LENGTH_9B) { - if (hperh->init.parity == USART_PARITY_NONE) { - *(uint16_t *)hperh->rx_buf = (uint16_t)(hperh->perh->DATA & 0x1FF); - hperh->rx_buf += 2; - } - else { - *hperh->rx_buf++ = (uint8_t)(hperh->perh->DATA & 0xFF); - } - } - else { - if (hperh->init.parity == USART_PARITY_NONE) - *hperh->rx_buf++ = (uint8_t)(hperh->perh->DATA & 0xFF); - else - *hperh->rx_buf++ = (uint8_t)(hperh->perh->DATA & 0x7F); - } - - --hperh->rx_count; - } - } - - if (hperh->rx_count == 0) { - ald_usart_interrupt_config(hperh, USART_IT_RXNE, DISABLE); - ald_usart_interrupt_config(hperh, USART_IT_PE, DISABLE); - ald_usart_interrupt_config(hperh, USART_IT_ERR, DISABLE); - - hperh->state = USART_STATE_READY; - - if (hperh->tx_rx_cplt_cbk != NULL) - hperh->tx_rx_cplt_cbk(hperh); - } - - return OK; -} - -/** - * @brief Configures the USART peripheral. - * @param hperh: Pointer to a usart_handle_t structure that contains - * the configuration information for the specified USART module. - * @retval None - */ -static void usart_set_config (usart_handle_t *hperh) -{ - uint32_t tmp; - uint32_t integer; - uint32_t fractional; - - /* Check the parameters */ - assert_param(IS_USART(hperh->perh)); - assert_param(IS_USART_BAUDRATE(hperh->init.baud)); - assert_param(IS_USART_WORD_LENGTH(hperh->init.word_length)); - assert_param(IS_USART_STOPBITS(hperh->init.stop_bits)); - assert_param(IS_USART_PARITY(hperh->init.parity)); - assert_param(IS_USART_MODE(hperh->init.mode)); - assert_param(IS_USART_HARDWARE_FLOW_CONTROL(hperh->init.fctl)); - - MODIFY_REG(hperh->perh->CON1, USART_CON1_STPLEN_MSK, hperh->init.stop_bits << USART_CON1_STPLEN_POSS); - tmp = READ_REG(hperh->perh->CON0); - MODIFY_REG(tmp, USART_CON0_DLEN_MSK, hperh->init.word_length << USART_CON0_DLEN_POS); - - if (hperh->init.parity == USART_PARITY_NONE) - CLEAR_BIT(tmp, USART_CON0_PEN_MSK); - else - SET_BIT(tmp, USART_CON0_PEN_MSK); - - if (hperh->init.parity == USART_PARITY_ODD) - SET_BIT(tmp, USART_CON0_PSEL_MSK); - else - CLEAR_BIT(tmp, USART_CON0_PSEL_MSK); - - WRITE_REG(hperh->perh->CON0, tmp); - MODIFY_REG(hperh->perh->CON2, USART_CON2_RTSEN_MSK, (hperh->init.fctl & 0x1) << USART_CON2_RTSEN_POS); - MODIFY_REG(hperh->perh->CON2, USART_CON2_CTSEN_MSK, ((hperh->init.fctl >> 1) & 0x1) << USART_CON2_CTSEN_POS); - MODIFY_REG(hperh->perh->CON0, USART_CON0_RXEN_MSK, (hperh->init.mode & 0x1) << USART_CON0_RXEN_POS); - MODIFY_REG(hperh->perh->CON0, USART_CON0_TXEN_MSK, ((hperh->init.mode >> 1) & 0x1) << USART_CON0_TXEN_POS); - - /* Determine the integer part */ - integer = ((25 * ald_cmu_get_pclk1_clock()) / (4 * (hperh->init.baud))); - tmp = (integer / 100) << 4; - - /* Determine the fractional part */ - fractional = integer - (100 * (tmp >> 4)); - tmp |= ((((fractional * 16) + 50) / 100) & ((uint8_t)0x0F)); - WRITE_REG(hperh->perh->BAUDCON, (uint16_t)tmp); - - return; -} -/** - * @} - */ -#endif /* ALD_USART */ -/** - * @} - */ -/** - * @} - */ diff --git a/bsp/essemi/es32f0334/libraries/ES32F033x_ALD_StdPeriph_Driver/Source/ald_wdt.c b/bsp/essemi/es32f0334/libraries/ES32F033x_ALD_StdPeriph_Driver/Source/ald_wdt.c deleted file mode 100644 index d19a0397ab..0000000000 --- a/bsp/essemi/es32f0334/libraries/ES32F033x_ALD_StdPeriph_Driver/Source/ald_wdt.c +++ /dev/null @@ -1,214 +0,0 @@ -/** - ********************************************************************************* - * - * @file ald_wdt.c - * @brief WDT module driver. - * - * @version V1.0 - * @date 18 Dec 2017 - * @author AE Team - * @note - * - * Copyright (C) Shanghai Eastsoft Microelectronics Co. Ltd. All rights reserved. - * - ********************************************************************************* - */ -#include "ald_conf.h" -#include "ald_wdt.h" - - -/** @addtogroup ES32FXXX_ALD - * @{ - */ - -/** @defgroup WDT WDT - * @brief WDT module driver - * @{ - */ -#ifdef ALD_WDT - - -/** @defgroup WWDT_Public_Functions WWDT Public Functions - * @brief Init and configure WWDT function - * @{ - */ -/** - * @brief Initializes the WWDT according to the specified parameters. - * @param load: Specifies the free-running downcounter value. - * @param win: specifics the no dog windows, - * the parameter can be one of the following values: - * @arg @ref WWDT_WIN_25 No dog window size: 25% - * @arg @ref WWDT_WIN_50 No dog window size: 50% - * @arg @ref WWDT_WIN_75 No dog window size: 75% - * @arg @ref WWDT_WIN_00 No dog window size: 0% - * @param interrupt: Enable or disable interrupt. - * @retval None - */ -void ald_wwdt_init(uint32_t load, wwdt_win_t win, type_func_t interrupt) -{ - assert_param(IS_WWDT_WIN_TYPE(win)); - assert_param(IS_FUNC_STATE(interrupt)); - - WWDT_UNLOCK(); - WRITE_REG(WWDT->LOAD, load); - MODIFY_REG(WWDT->CON, WWDT_CON_WWDTWIN_MSK, win << WWDT_CON_WWDTWIN_POSS); - SET_BIT(WWDT->CON, WWDT_CON_CLKS_MSK); - SET_BIT(WWDT->CON, WWDT_CON_RSTEN_MSK); - MODIFY_REG(WWDT->CON, WWDT_CON_IE_MSK, interrupt << WWDT_CON_IE_POS); - WWDT_LOCK(); - - return; -} - -/** - * @brief Start the WWDT - * @retval None - */ -void ald_wwdt_start(void) -{ - WWDT_UNLOCK(); - SET_BIT(WWDT->CON, WWDT_CON_EN_MSK); - WWDT_LOCK(); - - return; -} - -/** - * @brief Get the free-running downcounter value - * @retval Value - */ -uint32_t ald_wwdt_get_value(void) -{ - return WWDT->VALUE; -} - -/** - * @brief Get interrupt state - * @retval Value - */ -it_status_t ald_wwdt_get_flag_status(void) -{ - if (READ_BIT(WWDT->RIS, WWDT_RIS_WWDTIF_MSK)) - return SET; - - return RESET; -} - -/** - * @brief Clear interrupt state - * @retval None - */ -void ald_wwdt_clear_flag_status(void) -{ - WRITE_REG(WWDT->INTCLR, 1); - return; -} - -/** - * @brief Refreshes the WWDT - * @retval None - */ -void ald_wwdt_feed_dog(void) -{ - WWDT_UNLOCK(); - WRITE_REG(WWDT->INTCLR, 0x1); - WWDT_LOCK(); - - return; -} -/** - * @} - */ - -/** @defgroup IWDT_Public_Functions IWDT Public Functions - * @brief Init and configure IWDT function - * @{ - */ -/** - * @brief Initializes the IWDG according to the specified parameters. - * @param load: Specifies the free-running downcounter value. - * @param interrupt: Enable or disable interrupt. - * @retval None - */ -void ald_iwdt_init(uint32_t load, type_func_t interrupt) -{ - assert_param(IS_FUNC_STATE(interrupt)); - - IWDT_UNLOCK(); - WRITE_REG(IWDT->LOAD, load); - SET_BIT(IWDT->CON, IWDT_CON_CLKS_MSK); - SET_BIT(IWDT->CON, IWDT_CON_RSTEN_MSK); - MODIFY_REG(IWDT->CON, IWDT_CON_IE_MSK, interrupt << IWDT_CON_IE_POS); - IWDT_LOCK(); - - return; -} - -/** - * @brief Start the IWDT - * @retval None - */ -void ald_iwdt_start(void) -{ - IWDT_UNLOCK(); - SET_BIT(IWDT->CON, IWDT_CON_EN_MSK); - IWDT_LOCK(); - - return; -} - -/** - * @brief Get the free-running downcounter value - * @retval Value - */ -uint32_t ald_iwdt_get_value(void) -{ - return IWDT->VALUE; -} - -/** - * @brief Get interrupt state - * @retval Value - */ -it_status_t ald_iwdt_get_flag_status(void) -{ - if (READ_BIT(IWDT->RIS, IWDT_RIS_WDTIF_MSK)) - return SET; - - return RESET; -} - -/** - * @brief Clear interrupt state - * @retval None - */ -void ald_iwdt_clear_flag_status(void) -{ - WRITE_REG(IWDT->INTCLR, 1); - return; -} - -/** - * @brief Refreshes the WWDT - * @retval None - */ -void ald_iwdt_feed_dog(void) -{ - IWDT_UNLOCK(); - WRITE_REG(IWDT->INTCLR, 1); - IWDT_LOCK(); - - return; -} -/** - * @} - */ - -#endif /* ALD_WDT */ -/** - * @} - */ - -/** - * @} - */ diff --git a/bsp/essemi/es32f0334/libraries/ES32F033x_ALD_StdPeriph_Driver/Source/utils.c b/bsp/essemi/es32f0334/libraries/ES32F033x_ALD_StdPeriph_Driver/Source/utils.c deleted file mode 100644 index e406c53afc..0000000000 --- a/bsp/essemi/es32f0334/libraries/ES32F033x_ALD_StdPeriph_Driver/Source/utils.c +++ /dev/null @@ -1,440 +0,0 @@ -/** - ********************************************************************************* - * - * @file utils.c - * @brief This file contains the Utilities functions/types for the driver. - * - * @version V1.0 - * @date 07 Nov 2017 - * @author AE Team - * @note - * - * Copyright (C) Shanghai Eastsoft Microelectronics Co. Ltd. All rights reserved. - * - ********************************************************************************* - */ - -#include -#include "utils.h" -#include "ald_dma.h" -#include "ald_cmu.h" - - -/** @defgroup ES32FXXX_ALD EASTSOFT ES32F0xx ALD - * @brief Shanghai Eastsoft Microelectronics Cortex-M Chip Abstraction Layer Driver(ALD) - * @{ - */ - -/** @defgroup UTILS Utils - * @brief Utils module driver - * @{ - */ - -/** @defgroup ALD_Private_Constants Private Constants - * @brief ALD Private Constants - * @{ - */ - -/** - * @brief ALD version number - */ -#define __ALD_VERSION_MAIN (0x01) /**< [31:24] main version */ -#define __ALD_VERSION_SUB1 (0x00) /**< [23:16] sub1 version */ -#define __ALD_VERSION_SUB2 (0x00) /**< [15:8] sub2 version */ -#define __ALD_VERSION_RC (0x00) /**< [7:0] release candidate */ -#define __ALD_VERSION ((__ALD_VERSION_MAIN << 24) | \ - (__ALD_VERSION_SUB1 << 16) | \ - (__ALD_VERSION_SUB2 << 8 ) | \ - (__ALD_VERSION_RC)) -/** - * @} - */ - -/** @defgroup ALD_Private_Variables Private Variables - * @{ - */ -/** @brief lib_tick: Increase by one millisecond - */ -static __IO uint32_t lib_tick; -uint32_t __systick_interval = SYSTICK_INTERVAL_1MS; -/** - * @} - */ - - -/** @defgroup ALD_Public_Functions Public Functions - * @{ - */ - -/** @defgroup ALD_Public_Functions_Group1 Initialization Function - * @brief Initialization functions - * - * @verbatim - =============================================================================== - ##### Initialization functions ##### - =============================================================================== - [..] This section provides functions allowing to: - (+) Initializes interface, the NVIC allocation and initial clock - configuration. It initializes the source of time base also when timeout - is needed and the backup domain when enabled. - (+) Configure The time base source to have 1ms time base with a dedicated - Tick interrupt priority. - (++) Systick timer is used by default as source of time base, but user - can eventually implement his proper time base source (a general purpose - timer for example or other time source), keeping in mind that Time base - duration should be kept 1ms. - (++) Time base configuration function (ald_tick_init()) is called automatically - at the beginning of the program after reset by ald_cmu_init() or at - any time when clock is configured. - (++) Source of time base is configured to generate interrupts at regular - time intervals. Care must be taken if ald_delay_ms() is called from a - peripheral ISR process, the Tick interrupt line must have higher priority - (numerically lower) than the peripheral interrupt. Otherwise the caller - ISR process will be blocked. - (++) functions affecting time base configurations are declared as __weak - to make override possible in case of other implementations in user file. - (+) Configure the interval of Systick interrupt. - - @endverbatim - * @{ - */ - -/** - * @brief This function Configures time base source, NVIC and DMA. - * @note This function is called at the beginning of program after reset and before - * the clock configuration. - * @note The time base configuration is based on MSI clock when exiting from Reset. - * Once done, time base tick start incrementing. - * In the default implementation, Systick is used as source of time base. - * The tick variable is incremented each 1ms in its ISR. - * @retval None - */ -void ald_cmu_init(void) -{ - ald_cmu_clock_config_default(); - ald_tick_init(TICK_INT_PRIORITY); -#ifdef ALD_DMA - ald_dma_init(DMA0); -#endif - return; -} - -/** - * @brief This function configures the source of the time base. - * The time source is configured to have 1ms time base with a dedicated - * Tick interrupt priority. - * @note In the default implementation, SysTick timer is the source of time base. - * It is used to generate interrupts at regular time intervals. - * Care must be taken if ald_delay_ms() is called from a peripheral ISR process, - * The SysTick interrupt must have higher priority (numerically lower) - * than the peripheral interrupt. Otherwise the caller ISR process will be blocked. - * The function is declared as __weak to be overwritten in case of other - * implementation in user file. - * @param prio: Tick interrupt priority. - * @retval None - */ -__weak void ald_tick_init(uint32_t prio) -{ - /* Configure the SysTick IRQ */ - SysTick_Config(ald_cmu_get_sys_clock() / SYSTICK_INTERVAL_1MS); - - if (prio != 3) - NVIC_SetPriority(SysTick_IRQn, prio); - - return; -} - -/** - * @brief Selects the interval of systick interrupt. - * @param value: The value of interval: - * @arg @ref SYSTICK_INTERVAL_1MS 1 millisecond - * @arg @ref SYSTICK_INTERVAL_10MS 10 milliseconds - * @arg @ref SYSTICK_INTERVAL_100MS 100 milliseconds - * @arg @ref SYSTICK_INTERVAL_1000MS 1 second - * @retval None - */ -void ald_systick_interval_select(systick_interval_t value) -{ - assert_param(IS_SYSTICK_INTERVAL(value)); - - SysTick_Config(ald_cmu_get_sys_clock() / value); - __systick_interval = value; - - if (TICK_INT_PRIORITY != 3) - NVIC_SetPriority(SysTick_IRQn, TICK_INT_PRIORITY); - - return; -} -/** - * @} - */ - -/** @defgroup ALD_Public_Functions_Group2 Control functions - * @brief Control functions - * - * @verbatim - =============================================================================== - ##### Control functions ##### - =============================================================================== - [..] This section provides functions allowing to: - (+) Provide a tick value in millisecond - (+) Provide a blocking delay in millisecond - (+) Suspend the time base source interrupt - (+) Resume the time base source interrupt - (+) Get the ALD version - (+) Waiting for flag - (+) Configure the interrupt - (+) Provide system tick value - (+) Get CPU ID - (+) Get UID - (+) Get CHIPID - - @endverbatim - * @{ - */ - -/** - * @brief This function is called to increment a global variable "lib_tick" - * used as application time base. - * @note In the default implementation, this variable is incremented each 1ms - * in Systick ISR. - * @note This function is declared as __weak to be overwritten in case of other - * implementations in user file. - * @retval None - */ -__weak void ald_inc_tick_weak(void) -{ - ++lib_tick; -} - -/** - * @brief This function invoked by Systick ISR. - * @note This function is declared as __weak to be overwritten in case of - * other implementations in user file. - * @retval None - */ -__weak void ald_systick_irq_cbk(void) -{ - /* do nothing */ - return; -} - -/** - * @brief This function invoked by Systick ISR each 1ms. - * @retval None - */ -__isr__ void ald_inc_tick(void) -{ - ald_inc_tick_weak(); - ald_systick_irq_cbk(); - - return; -} - -/** - * @brief Provides a tick value in millisecond. - * @note This function is declared as __weak to be overwritten in case of other - * implementations in user file. - * @retval tick value - */ -__weak uint32_t ald_get_tick(void) -{ - return lib_tick; -} - -/** - * @brief This function provides accurate delay (in milliseconds) based - * on variable incremented. - * @note In the default implementation, SysTick timer is the source of time base. - * It is used to generate interrupts at regular time intervals where lib_tick - * is incremented. - * @note This function is declared as __weak to be overwritten in case of other - * implementations in user file. - * @param delay: specifies the delay time length, in milliseconds. - * @retval None - */ -__weak void ald_delay_ms(__IO uint32_t delay) -{ - uint32_t tick, __delay; - - switch (__systick_interval) { - case SYSTICK_INTERVAL_1MS: - __delay = delay; - break; - - case SYSTICK_INTERVAL_10MS: - __delay = delay / 10; - break; - - case SYSTICK_INTERVAL_100MS: - __delay = delay / 100; - break; - - case SYSTICK_INTERVAL_1000MS: - __delay = delay / 1000; - break; - - default: - __delay = delay; - break; - } - - tick = ald_get_tick(); - __delay = __delay == 0 ? 1 : __delay; - - while ((ald_get_tick() - tick) < __delay) - ; -} - -/** - * @brief Suspend Tick increment. - * @note In the default implementation, SysTick timer is the source of time base. - * It is used to generate interrupts at regular time intervals. - * Once ald_suspend_tick() is called, the the SysTick interrupt - * will be disabled and so Tick increment is suspended. - * @note This function is declared as __weak to be overwritten - * in case of other implementations in user file. - * @retval None - */ -__weak void ald_suspend_tick(void) -{ - CLEAR_BIT(SysTick->CTRL, SysTick_CTRL_TICKINT_Msk); -} - -/** - * @brief Resume Tick increment. - * @note In the default implementation, SysTick timer is the source of - * time base. It is used to generate interrupts at regular time - * intervals. Once ald_resume_tick() is called, the the SysTick - * interrupt will be enabled and so Tick increment is resumed. - * @note This function is declared as __weak to be overwritten - * in case of other implementations in user file. - * @retval None - */ -__weak void ald_resume_tick(void) -{ - SET_BIT(SysTick->CTRL, SysTick_CTRL_TICKINT_Msk); -} - -/** - * @brief This method returns the ALD revision - * @retval version: 0xXYZR (8bits for each decimal, R for RC) - */ -uint32_t ald_get_ald_version(void) -{ - return __ALD_VERSION; -} - -/** - * @brief Waiting the specified bit in the register change to SET/RESET. - * @param reg: The register address. - * @param bit: The specified bit. - * @param status: The status for waiting. - * @param timeout: Timeout duration. - * @retval Status, see @ref ald_status_t. - */ -ald_status_t ald_wait_flag(uint32_t *reg, uint32_t bit, flag_status_t status, uint32_t timeout) -{ - uint32_t tick = ald_get_tick(); - - assert_param(timeout > 0); - - if (status == SET) { - while (!(IS_BIT_SET(*reg, bit))) { - if (((ald_get_tick()) - tick) > timeout) - return TIMEOUT; - } - } - else { - while ((IS_BIT_SET(*reg, bit))) { - if (((ald_get_tick()) - tick) > timeout) - return TIMEOUT; - } - } - - return OK; -} - -/** - * @brief Configure interrupt. - * @param irq: Interrunpt type. - * @param prio: preempt priority(0-3). - * @param status: Status. - * @arg ENABLE - * @arg DISABLE - * @retval None - */ -void ald_mcu_irq_config(IRQn_Type irq, uint8_t prio, type_func_t status) -{ - assert_param(IS_FUNC_STATE(status)); - assert_param(IS_PRIO(prio)); - - if (status == ENABLE) { - NVIC_SetPriority(irq, prio); - NVIC_EnableIRQ(irq); - } - else { - NVIC_DisableIRQ(irq); - } - - return; -} - -/** - * @brief Get the system tick. - * @retval The value of current tick. - */ -uint32_t ald_mcu_get_tick(void) -{ - uint32_t load = SysTick->LOAD; - uint32_t val = SysTick->VAL; - - return (load - val); -} - -/** - * @brief Get the CPU ID. - * @retval CPU ID. - */ -uint32_t ald_mcu_get_cpu_id(void) -{ - return SCB->CPUID; -} - -/** - * @brief Get the UID. - * @param buf: Pointer to UID, len: 12Bytes(96-bits) - * @retval None - */ -void ald_mcu_get_uid(uint8_t *buf) -{ - memcpy(&buf[0], (void *)MCU_UID0_ADDR, 4); - memcpy(&buf[4], (void *)MCU_UID1_ADDR, 4); - memcpy(&buf[8], (void *)MCU_UID2_ADDR, 4); - - return; -} - -/** - * @brief Get the CHIPID - * @retval CHPID - */ -uint32_t ald_mcu_get_chipid(void) -{ - return (uint32_t)*(uint32_t *)MCU_CHIPID_ADDR; -} -/** - * @} - */ - -/** - * @} - */ - -/** - * @} - */ - -/** - * @} - */ diff --git a/bsp/essemi/es32f0334/libraries/SConscript b/bsp/essemi/es32f0334/libraries/SConscript deleted file mode 100644 index 7a04540b4e..0000000000 --- a/bsp/essemi/es32f0334/libraries/SConscript +++ /dev/null @@ -1,27 +0,0 @@ -import rtconfig -Import('RTT_ROOT') -from building import * - -# get current directory -cwd = GetCurrentDir() - -# The set of source files associated with this SConscript file. -src = [] - -src += Glob('ES32F033x_ALD_StdPeriph_Driver/Source/*.c') - -#add for startup script -if rtconfig.CROSS_TOOL == 'gcc': - src = src + ['CMSIS/Device/EastSoft/es32f033x/Startup/gcc/startup_es32f033x.s'] -elif rtconfig.CROSS_TOOL == 'keil': - src = src + ['CMSIS/Device/EastSoft/es32f033x/Startup/keil/startup_es32f033x.s'] -elif rtconfig.CROSS_TOOL == 'iar': - src = src + ['CMSIS/Device/EastSoft/es32f033x/Startup/iar/startup_es32f033x.s'] - -path = [cwd + '/CMSIS/Device/EastSoft/es32f033x/Include', - cwd + '/CMSIS/Include', - cwd + '/ES32F033x_ALD_StdPeriph_Driver/Include'] - -group = DefineGroup('Libraries', src, depend = [''], CPPPATH = path, CPPDEFINES = ['ES32F033x']) - -Return('group') -- cgit v1.3.1 From d77b9d823460e572c324ea459e5597d415519ba0 Mon Sep 17 00:00:00 2001 From: liuhy Date: Fri, 10 Sep 2021 18:05:17 +0800 Subject: delete essemi bsp es32f0334 (all) --- bsp/essemi/es32f0334/.config | 533 --------- bsp/essemi/es32f0334/Kconfig | 26 - bsp/essemi/es32f0334/README.md | 118 -- bsp/essemi/es32f0334/SConscript | 14 - bsp/essemi/es32f0334/SConstruct | 40 - bsp/essemi/es32f0334/applications/SConscript | 11 - bsp/essemi/es32f0334/applications/main.c | 30 - bsp/essemi/es32f0334/drivers/Kconfig | 176 --- bsp/essemi/es32f0334/drivers/SConscript | 94 -- bsp/essemi/es32f0334/drivers/board.c | 123 --- bsp/essemi/es32f0334/drivers/board.h | 36 - .../drivers/bsp_driver_example/.gitignore | 52 - .../es32f0334/drivers/bsp_driver_example/README.md | 47 - .../drivers/bsp_driver_example/adc_vol_sample.c | 57 - .../drivers/bsp_driver_example/can_sample.c | 144 --- .../drivers/bsp_driver_example/hwtimer_sample.c | 85 -- .../drivers/bsp_driver_example/i2c_sample.c | 97 -- .../drivers/bsp_driver_example/led_blink_sample.c | 83 -- .../drivers/bsp_driver_example/pin_beep_sample.c | 67 -- .../drivers/bsp_driver_example/pm_sample.c | 182 ---- .../drivers/bsp_driver_example/pwm_led_sample.c | 72 -- .../drivers/bsp_driver_example/rtc_sample.c | 51 - .../drivers/bsp_driver_example/spi_sample.c | 152 --- .../drivers/bsp_driver_example/uart_sample.c | 100 -- bsp/essemi/es32f0334/drivers/drv_adc.c | 193 ---- bsp/essemi/es32f0334/drivers/drv_adc.h | 16 - bsp/essemi/es32f0334/drivers/drv_gpio.c | 491 --------- bsp/essemi/es32f0334/drivers/drv_gpio.h | 16 - bsp/essemi/es32f0334/drivers/drv_hwtimer.c | 251 ----- bsp/essemi/es32f0334/drivers/drv_hwtimer.h | 16 - bsp/essemi/es32f0334/drivers/drv_i2c.c | 143 --- bsp/essemi/es32f0334/drivers/drv_i2c.h | 16 - bsp/essemi/es32f0334/drivers/drv_lptim.c | 124 --- bsp/essemi/es32f0334/drivers/drv_lptim.h | 23 - bsp/essemi/es32f0334/drivers/drv_pm.c | 260 ----- bsp/essemi/es32f0334/drivers/drv_pm.h | 16 - bsp/essemi/es32f0334/drivers/drv_pwm.c | 212 ---- bsp/essemi/es32f0334/drivers/drv_pwm.h | 16 - bsp/essemi/es32f0334/drivers/drv_rtc.c | 159 --- bsp/essemi/es32f0334/drivers/drv_rtc.h | 16 - bsp/essemi/es32f0334/drivers/drv_spi.c | 344 ------ bsp/essemi/es32f0334/drivers/drv_spi.h | 27 - bsp/essemi/es32f0334/drivers/drv_spiflash.c | 32 - bsp/essemi/es32f0334/drivers/drv_spiflash.h | 16 - bsp/essemi/es32f0334/drivers/drv_uart.c | 236 ---- bsp/essemi/es32f0334/drivers/drv_uart.h | 16 - .../es32f0334/drivers/linker_scripts/link.sct | 15 - .../es32f0334/figures/ES-PDS-ES32F0334-V1.1.jpg | Bin 3335280 -> 0 bytes bsp/essemi/es32f0334/figures/ESLinkII-mini.jpg | Bin 2698268 -> 0 bytes bsp/essemi/es32f0334/figures/drv_conf.jpg | Bin 153800 -> 0 bytes bsp/essemi/es32f0334/figures/drv_ex.jpg | Bin 176164 -> 0 bytes bsp/essemi/es32f0334/figures/k_conf.jpg | Bin 205576 -> 0 bytes bsp/essemi/es32f0334/figures/k_ex.jpg | Bin 214601 -> 0 bytes bsp/essemi/es32f0334/project.uvoptx | 1138 -------------------- bsp/essemi/es32f0334/project.uvprojx | 871 --------------- bsp/essemi/es32f0334/rtconfig.h | 195 ---- bsp/essemi/es32f0334/rtconfig.py | 135 --- bsp/essemi/es32f0334/template.uvoptx | 182 ---- bsp/essemi/es32f0334/template.uvprojx | 389 ------- 59 files changed, 7954 deletions(-) delete mode 100644 bsp/essemi/es32f0334/.config delete mode 100644 bsp/essemi/es32f0334/Kconfig delete mode 100644 bsp/essemi/es32f0334/README.md delete mode 100644 bsp/essemi/es32f0334/SConscript delete mode 100644 bsp/essemi/es32f0334/SConstruct delete mode 100644 bsp/essemi/es32f0334/applications/SConscript delete mode 100644 bsp/essemi/es32f0334/applications/main.c delete mode 100644 bsp/essemi/es32f0334/drivers/Kconfig delete mode 100644 bsp/essemi/es32f0334/drivers/SConscript delete mode 100644 bsp/essemi/es32f0334/drivers/board.c delete mode 100644 bsp/essemi/es32f0334/drivers/board.h delete mode 100644 bsp/essemi/es32f0334/drivers/bsp_driver_example/.gitignore delete mode 100644 bsp/essemi/es32f0334/drivers/bsp_driver_example/README.md delete mode 100644 bsp/essemi/es32f0334/drivers/bsp_driver_example/adc_vol_sample.c delete mode 100644 bsp/essemi/es32f0334/drivers/bsp_driver_example/can_sample.c delete mode 100644 bsp/essemi/es32f0334/drivers/bsp_driver_example/hwtimer_sample.c delete mode 100644 bsp/essemi/es32f0334/drivers/bsp_driver_example/i2c_sample.c delete mode 100644 bsp/essemi/es32f0334/drivers/bsp_driver_example/led_blink_sample.c delete mode 100644 bsp/essemi/es32f0334/drivers/bsp_driver_example/pin_beep_sample.c delete mode 100644 bsp/essemi/es32f0334/drivers/bsp_driver_example/pm_sample.c delete mode 100644 bsp/essemi/es32f0334/drivers/bsp_driver_example/pwm_led_sample.c delete mode 100644 bsp/essemi/es32f0334/drivers/bsp_driver_example/rtc_sample.c delete mode 100644 bsp/essemi/es32f0334/drivers/bsp_driver_example/spi_sample.c delete mode 100644 bsp/essemi/es32f0334/drivers/bsp_driver_example/uart_sample.c delete mode 100644 bsp/essemi/es32f0334/drivers/drv_adc.c delete mode 100644 bsp/essemi/es32f0334/drivers/drv_adc.h delete mode 100644 bsp/essemi/es32f0334/drivers/drv_gpio.c delete mode 100644 bsp/essemi/es32f0334/drivers/drv_gpio.h delete mode 100644 bsp/essemi/es32f0334/drivers/drv_hwtimer.c delete mode 100644 bsp/essemi/es32f0334/drivers/drv_hwtimer.h delete mode 100644 bsp/essemi/es32f0334/drivers/drv_i2c.c delete mode 100644 bsp/essemi/es32f0334/drivers/drv_i2c.h delete mode 100644 bsp/essemi/es32f0334/drivers/drv_lptim.c delete mode 100644 bsp/essemi/es32f0334/drivers/drv_lptim.h delete mode 100644 bsp/essemi/es32f0334/drivers/drv_pm.c delete mode 100644 bsp/essemi/es32f0334/drivers/drv_pm.h delete mode 100644 bsp/essemi/es32f0334/drivers/drv_pwm.c delete mode 100644 bsp/essemi/es32f0334/drivers/drv_pwm.h delete mode 100644 bsp/essemi/es32f0334/drivers/drv_rtc.c delete mode 100644 bsp/essemi/es32f0334/drivers/drv_rtc.h delete mode 100644 bsp/essemi/es32f0334/drivers/drv_spi.c delete mode 100644 bsp/essemi/es32f0334/drivers/drv_spi.h delete mode 100644 bsp/essemi/es32f0334/drivers/drv_spiflash.c delete mode 100644 bsp/essemi/es32f0334/drivers/drv_spiflash.h delete mode 100644 bsp/essemi/es32f0334/drivers/drv_uart.c delete mode 100644 bsp/essemi/es32f0334/drivers/drv_uart.h delete mode 100644 bsp/essemi/es32f0334/drivers/linker_scripts/link.sct delete mode 100644 bsp/essemi/es32f0334/figures/ES-PDS-ES32F0334-V1.1.jpg delete mode 100644 bsp/essemi/es32f0334/figures/ESLinkII-mini.jpg delete mode 100644 bsp/essemi/es32f0334/figures/drv_conf.jpg delete mode 100644 bsp/essemi/es32f0334/figures/drv_ex.jpg delete mode 100644 bsp/essemi/es32f0334/figures/k_conf.jpg delete mode 100644 bsp/essemi/es32f0334/figures/k_ex.jpg delete mode 100644 bsp/essemi/es32f0334/project.uvoptx delete mode 100644 bsp/essemi/es32f0334/project.uvprojx delete mode 100644 bsp/essemi/es32f0334/rtconfig.h delete mode 100644 bsp/essemi/es32f0334/rtconfig.py delete mode 100644 bsp/essemi/es32f0334/template.uvoptx delete mode 100644 bsp/essemi/es32f0334/template.uvprojx (limited to 'bsp') diff --git a/bsp/essemi/es32f0334/.config b/bsp/essemi/es32f0334/.config deleted file mode 100644 index aaa2042085..0000000000 --- a/bsp/essemi/es32f0334/.config +++ /dev/null @@ -1,533 +0,0 @@ -# -# Automatically generated file; DO NOT EDIT. -# RT-Thread Configuration -# - -# -# RT-Thread Kernel -# -CONFIG_RT_NAME_MAX=8 -# CONFIG_RT_USING_ARCH_DATA_TYPE is not set -# CONFIG_RT_USING_SMP is not set -CONFIG_RT_ALIGN_SIZE=4 -# CONFIG_RT_THREAD_PRIORITY_8 is not set -CONFIG_RT_THREAD_PRIORITY_32=y -# CONFIG_RT_THREAD_PRIORITY_256 is not set -CONFIG_RT_THREAD_PRIORITY_MAX=32 -CONFIG_RT_TICK_PER_SECOND=100 -CONFIG_RT_USING_OVERFLOW_CHECK=y -CONFIG_RT_USING_HOOK=y -CONFIG_RT_USING_IDLE_HOOK=y -CONFIG_RT_IDLE_HOOK_LIST_SIZE=4 -CONFIG_IDLE_THREAD_STACK_SIZE=256 -# CONFIG_RT_USING_TIMER_SOFT is not set -CONFIG_RT_DEBUG=y -CONFIG_RT_DEBUG_COLOR=y -# CONFIG_RT_DEBUG_INIT_CONFIG is not set -# CONFIG_RT_DEBUG_THREAD_CONFIG is not set -# CONFIG_RT_DEBUG_SCHEDULER_CONFIG is not set -# CONFIG_RT_DEBUG_IPC_CONFIG is not set -# CONFIG_RT_DEBUG_TIMER_CONFIG is not set -# CONFIG_RT_DEBUG_IRQ_CONFIG is not set -# CONFIG_RT_DEBUG_MEM_CONFIG is not set -# CONFIG_RT_DEBUG_SLAB_CONFIG is not set -# CONFIG_RT_DEBUG_MEMHEAP_CONFIG is not set -# CONFIG_RT_DEBUG_MODULE_CONFIG is not set - -# -# Inter-Thread communication -# -CONFIG_RT_USING_SEMAPHORE=y -CONFIG_RT_USING_MUTEX=y -CONFIG_RT_USING_EVENT=y -CONFIG_RT_USING_MAILBOX=y -CONFIG_RT_USING_MESSAGEQUEUE=y -# CONFIG_RT_USING_SIGNALS is not set - -# -# Memory Management -# -CONFIG_RT_USING_MEMPOOL=y -# CONFIG_RT_USING_MEMHEAP is not set -# CONFIG_RT_USING_NOHEAP is not set -CONFIG_RT_USING_SMALL_MEM=y -# CONFIG_RT_USING_SLAB is not set -# CONFIG_RT_USING_MEMTRACE is not set -CONFIG_RT_USING_HEAP=y - -# -# Kernel Device Object -# -CONFIG_RT_USING_DEVICE=y -# CONFIG_RT_USING_DEVICE_OPS is not set -# CONFIG_RT_USING_INTERRUPT_INFO is not set -CONFIG_RT_USING_CONSOLE=y -CONFIG_RT_CONSOLEBUF_SIZE=128 -CONFIG_RT_CONSOLE_DEVICE_NAME="uart1" -CONFIG_RT_VER_NUM=0x40003 -# CONFIG_RT_USING_CPU_FFS is not set -# CONFIG_ARCH_CPU_STACK_GROWS_UPWARD is not set - -# -# RT-Thread Components -# -CONFIG_RT_USING_COMPONENTS_INIT=y -CONFIG_RT_USING_USER_MAIN=y -CONFIG_RT_MAIN_THREAD_STACK_SIZE=2048 -CONFIG_RT_MAIN_THREAD_PRIORITY=10 - -# -# C++ features -# -# CONFIG_RT_USING_CPLUSPLUS is not set - -# -# Command shell -# -CONFIG_RT_USING_FINSH=y -CONFIG_FINSH_THREAD_NAME="tshell" -CONFIG_FINSH_USING_HISTORY=y -CONFIG_FINSH_HISTORY_LINES=5 -CONFIG_FINSH_USING_SYMTAB=y -CONFIG_FINSH_USING_DESCRIPTION=y -# CONFIG_FINSH_ECHO_DISABLE_DEFAULT is not set -CONFIG_FINSH_THREAD_PRIORITY=20 -CONFIG_FINSH_THREAD_STACK_SIZE=4096 -CONFIG_FINSH_CMD_SIZE=80 -# CONFIG_FINSH_USING_AUTH is not set -CONFIG_FINSH_USING_MSH=y -CONFIG_FINSH_USING_MSH_DEFAULT=y -CONFIG_FINSH_USING_MSH_ONLY=y -CONFIG_FINSH_ARG_MAX=10 - -# -# Device virtual file system -# -# CONFIG_RT_USING_DFS is not set - -# -# Device Drivers -# -CONFIG_RT_USING_DEVICE_IPC=y -CONFIG_RT_PIPE_BUFSZ=512 -# CONFIG_RT_USING_SYSTEM_WORKQUEUE is not set -CONFIG_RT_USING_SERIAL=y -# CONFIG_RT_SERIAL_USING_DMA is not set -CONFIG_RT_SERIAL_RB_BUFSZ=64 -# CONFIG_RT_USING_CAN is not set -CONFIG_RT_USING_HWTIMER=y -# CONFIG_RT_USING_CPUTIME is not set -CONFIG_RT_USING_I2C=y -# CONFIG_RT_I2C_DEBUG is not set -CONFIG_RT_USING_I2C_BITOPS=y -# CONFIG_RT_I2C_BITOPS_DEBUG is not set -CONFIG_RT_USING_PIN=y -CONFIG_RT_USING_ADC=y -# CONFIG_RT_USING_DAC is not set -CONFIG_RT_USING_PWM=y -# CONFIG_RT_USING_MTD_NOR is not set -# CONFIG_RT_USING_MTD_NAND is not set -CONFIG_RT_USING_PM=y -CONFIG_RT_USING_RTC=y -# CONFIG_RT_USING_ALARM is not set -# CONFIG_RT_USING_SOFT_RTC is not set -# CONFIG_RT_USING_SDIO is not set -CONFIG_RT_USING_SPI=y -# CONFIG_RT_USING_QSPI is not set -# CONFIG_RT_USING_SPI_MSD is not set -# CONFIG_RT_USING_SFUD is not set -# CONFIG_RT_USING_ENC28J60 is not set -# CONFIG_RT_USING_SPI_WIFI is not set -# CONFIG_RT_USING_WDT is not set -# CONFIG_RT_USING_AUDIO is not set -# CONFIG_RT_USING_SENSOR is not set -# CONFIG_RT_USING_TOUCH is not set -# CONFIG_RT_USING_HWCRYPTO is not set -# CONFIG_RT_USING_PULSE_ENCODER is not set -# CONFIG_RT_USING_INPUT_CAPTURE is not set -# CONFIG_RT_USING_WIFI is not set - -# -# Using USB -# -# CONFIG_RT_USING_USB_HOST is not set -# CONFIG_RT_USING_USB_DEVICE is not set - -# -# POSIX layer and C standard library -# -# CONFIG_RT_USING_LIBC is not set -# CONFIG_RT_USING_PTHREADS is not set -# CONFIG_RT_LIBC_USING_TIME is not set - -# -# Network -# - -# -# Socket abstraction layer -# -# CONFIG_RT_USING_SAL is not set - -# -# Network interface device -# -# CONFIG_RT_USING_NETDEV is not set - -# -# light weight TCP/IP stack -# -# CONFIG_RT_USING_LWIP is not set - -# -# AT commands -# -# CONFIG_RT_USING_AT is not set - -# -# VBUS(Virtual Software BUS) -# -# CONFIG_RT_USING_VBUS is not set - -# -# Utilities -# -# CONFIG_RT_USING_RYM is not set -# CONFIG_RT_USING_ULOG is not set -# CONFIG_RT_USING_UTEST is not set - -# -# RT-Thread online packages -# - -# -# IoT - internet of things -# -# CONFIG_PKG_USING_LORAWAN_DRIVER is not set -# CONFIG_PKG_USING_PAHOMQTT is not set -# CONFIG_PKG_USING_UMQTT is not set -# CONFIG_PKG_USING_WEBCLIENT is not set -# CONFIG_PKG_USING_WEBNET is not set -# CONFIG_PKG_USING_MONGOOSE is not set -# CONFIG_PKG_USING_MYMQTT is not set -# CONFIG_PKG_USING_KAWAII_MQTT is not set -# CONFIG_PKG_USING_BC28_MQTT is not set -# CONFIG_PKG_USING_WEBTERMINAL is not set -# CONFIG_PKG_USING_CJSON is not set -# CONFIG_PKG_USING_JSMN is not set -# CONFIG_PKG_USING_LIBMODBUS is not set -# CONFIG_PKG_USING_FREEMODBUS is not set -# CONFIG_PKG_USING_LJSON is not set -# CONFIG_PKG_USING_EZXML is not set -# CONFIG_PKG_USING_NANOPB is not set - -# -# Wi-Fi -# - -# -# Marvell WiFi -# -# CONFIG_PKG_USING_WLANMARVELL is not set - -# -# Wiced WiFi -# -# CONFIG_PKG_USING_WLAN_WICED is not set -# CONFIG_PKG_USING_RW007 is not set -# CONFIG_PKG_USING_COAP is not set -# CONFIG_PKG_USING_NOPOLL is not set -# CONFIG_PKG_USING_NETUTILS is not set -# CONFIG_PKG_USING_CMUX is not set -# CONFIG_PKG_USING_PPP_DEVICE is not set -# CONFIG_PKG_USING_AT_DEVICE is not set -# CONFIG_PKG_USING_ATSRV_SOCKET is not set -# CONFIG_PKG_USING_WIZNET is not set - -# -# IoT Cloud -# -# CONFIG_PKG_USING_ONENET is not set -# CONFIG_PKG_USING_GAGENT_CLOUD is not set -# CONFIG_PKG_USING_ALI_IOTKIT is not set -# CONFIG_PKG_USING_AZURE is not set -# CONFIG_PKG_USING_TENCENT_IOT_EXPLORER is not set -# CONFIG_PKG_USING_JIOT-C-SDK is not set -# CONFIG_PKG_USING_UCLOUD_IOT_SDK is not set -# CONFIG_PKG_USING_JOYLINK is not set -# CONFIG_PKG_USING_NIMBLE is not set -# CONFIG_PKG_USING_OTA_DOWNLOADER is not set -# CONFIG_PKG_USING_IPMSG is not set -# CONFIG_PKG_USING_LSSDP is not set -# CONFIG_PKG_USING_AIRKISS_OPEN is not set -# CONFIG_PKG_USING_LIBRWS is not set -# CONFIG_PKG_USING_TCPSERVER is not set -# CONFIG_PKG_USING_PROTOBUF_C is not set -# CONFIG_PKG_USING_ONNX_PARSER is not set -# CONFIG_PKG_USING_ONNX_BACKEND is not set -# CONFIG_PKG_USING_DLT645 is not set -# CONFIG_PKG_USING_QXWZ is not set -# CONFIG_PKG_USING_SMTP_CLIENT is not set -# CONFIG_PKG_USING_ABUP_FOTA is not set -# CONFIG_PKG_USING_LIBCURL2RTT is not set -# CONFIG_PKG_USING_CAPNP is not set -# CONFIG_PKG_USING_RT_CJSON_TOOLS is not set -# CONFIG_PKG_USING_AGILE_TELNET is not set -# CONFIG_PKG_USING_NMEALIB is not set -# CONFIG_PKG_USING_AGILE_JSMN is not set -# CONFIG_PKG_USING_PDULIB is not set -# CONFIG_PKG_USING_BTSTACK is not set -# CONFIG_PKG_USING_LORAWAN_ED_STACK is not set - -# -# security packages -# -# CONFIG_PKG_USING_MBEDTLS is not set -# CONFIG_PKG_USING_libsodium is not set -# CONFIG_PKG_USING_TINYCRYPT is not set -# CONFIG_PKG_USING_TFM is not set -# CONFIG_PKG_USING_YD_CRYPTO is not set - -# -# language packages -# -# CONFIG_PKG_USING_LUA is not set -# CONFIG_PKG_USING_JERRYSCRIPT is not set -# CONFIG_PKG_USING_MICROPYTHON is not set - -# -# multimedia packages -# -# CONFIG_PKG_USING_OPENMV is not set -# CONFIG_PKG_USING_MUPDF is not set -# CONFIG_PKG_USING_STEMWIN is not set -# CONFIG_PKG_USING_WAVPLAYER is not set -# CONFIG_PKG_USING_TJPGD is not set -# CONFIG_PKG_USING_HELIX is not set - -# -# tools packages -# -# CONFIG_PKG_USING_CMBACKTRACE is not set -# CONFIG_PKG_USING_EASYFLASH is not set -# CONFIG_PKG_USING_EASYLOGGER is not set -# CONFIG_PKG_USING_SYSTEMVIEW is not set -# CONFIG_PKG_USING_RDB is not set -# CONFIG_PKG_USING_QRCODE is not set -# CONFIG_PKG_USING_ULOG_EASYFLASH is not set -# CONFIG_PKG_USING_ADBD is not set -# CONFIG_PKG_USING_COREMARK is not set -# CONFIG_PKG_USING_DHRYSTONE is not set -# CONFIG_PKG_USING_NR_MICRO_SHELL is not set -# CONFIG_PKG_USING_CHINESE_FONT_LIBRARY is not set -# CONFIG_PKG_USING_LUNAR_CALENDAR is not set -# CONFIG_PKG_USING_BS8116A is not set -# CONFIG_PKG_USING_GPS_RMC is not set -# CONFIG_PKG_USING_URLENCODE is not set -# CONFIG_PKG_USING_UMCN is not set - -# -# system packages -# -# CONFIG_PKG_USING_GUIENGINE is not set -# CONFIG_PKG_USING_CAIRO is not set -# CONFIG_PKG_USING_PIXMAN is not set -# CONFIG_PKG_USING_LWEXT4 is not set -# CONFIG_PKG_USING_PARTITION is not set -# CONFIG_PKG_USING_FAL is not set -# CONFIG_PKG_USING_FLASHDB is not set -# CONFIG_PKG_USING_SQLITE is not set -# CONFIG_PKG_USING_RTI is not set -# CONFIG_PKG_USING_LITTLEVGL2RTT is not set -# CONFIG_PKG_USING_CMSIS is not set -# CONFIG_PKG_USING_DFS_YAFFS is not set -# CONFIG_PKG_USING_LITTLEFS is not set -# CONFIG_PKG_USING_THREAD_POOL is not set -# CONFIG_PKG_USING_ROBOTS is not set -# CONFIG_PKG_USING_EV is not set -# CONFIG_PKG_USING_SYSWATCH is not set -# CONFIG_PKG_USING_SYS_LOAD_MONITOR is not set -# CONFIG_PKG_USING_PLCCORE is not set -# CONFIG_PKG_USING_RAMDISK is not set -# CONFIG_PKG_USING_MININI is not set -# CONFIG_PKG_USING_QBOOT is not set -# CONFIG_PKG_USING_UCOSIII_WRAPPER is not set -# CONFIG_PKG_USING_PPOOL is not set - -# -# peripheral libraries and drivers -# -# CONFIG_PKG_USING_SENSORS_DRIVERS is not set -# CONFIG_PKG_USING_REALTEK_AMEBA is not set -# CONFIG_PKG_USING_SHT2X is not set -# CONFIG_PKG_USING_SHT3X is not set -# CONFIG_PKG_USING_STM32_SDIO is not set -# CONFIG_PKG_USING_ICM20608 is not set -# CONFIG_PKG_USING_U8G2 is not set -# CONFIG_PKG_USING_BUTTON is not set -# CONFIG_PKG_USING_PCF8574 is not set -# CONFIG_PKG_USING_SX12XX is not set -# CONFIG_PKG_USING_SIGNAL_LED is not set -# CONFIG_PKG_USING_LEDBLINK is not set -# CONFIG_PKG_USING_LITTLED is not set -# CONFIG_PKG_USING_LKDGUI is not set -# CONFIG_PKG_USING_NRF5X_SDK is not set -# CONFIG_PKG_USING_NRFX is not set -# CONFIG_PKG_USING_WM_LIBRARIES is not set -# CONFIG_PKG_USING_KENDRYTE_SDK is not set -# CONFIG_PKG_USING_INFRARED is not set -# CONFIG_PKG_USING_ROSSERIAL is not set -# CONFIG_PKG_USING_AGILE_BUTTON is not set -# CONFIG_PKG_USING_AGILE_LED is not set -# CONFIG_PKG_USING_AT24CXX is not set -# CONFIG_PKG_USING_MOTIONDRIVER2RTT is not set -# CONFIG_PKG_USING_AD7746 is not set -# CONFIG_PKG_USING_PCA9685 is not set -# CONFIG_PKG_USING_I2C_TOOLS is not set -# CONFIG_PKG_USING_NRF24L01 is not set -# CONFIG_PKG_USING_TOUCH_DRIVERS is not set -# CONFIG_PKG_USING_MAX17048 is not set -# CONFIG_PKG_USING_RPLIDAR is not set -# CONFIG_PKG_USING_AS608 is not set -# CONFIG_PKG_USING_RC522 is not set -# CONFIG_PKG_USING_WS2812B is not set -# CONFIG_PKG_USING_EMBARC_BSP is not set -# CONFIG_PKG_USING_EXTERN_RTC_DRIVERS is not set -# CONFIG_PKG_USING_MULTI_RTIMER is not set -# CONFIG_PKG_USING_MAX7219 is not set -# CONFIG_PKG_USING_BEEP is not set -# CONFIG_PKG_USING_EASYBLINK is not set -# CONFIG_PKG_USING_PMS_SERIES is not set -# CONFIG_PKG_USING_CAN_YMODEM is not set -# CONFIG_PKG_USING_LORA_RADIO_DRIVER is not set -# CONFIG_PKG_USING_QLED is not set -# CONFIG_PKG_USING_PAJ7620 is not set -# CONFIG_PKG_USING_AGILE_CONSOLE is not set -# CONFIG_PKG_USING_LD3320 is not set -# CONFIG_PKG_USING_WK2124 is not set -# CONFIG_PKG_USING_LY68L6400 is not set -# CONFIG_PKG_USING_DM9051 is not set - -# -# miscellaneous packages -# -# CONFIG_PKG_USING_LIBCSV is not set -# CONFIG_PKG_USING_OPTPARSE is not set -# CONFIG_PKG_USING_FASTLZ is not set -# CONFIG_PKG_USING_MINILZO is not set -# CONFIG_PKG_USING_QUICKLZ is not set -# CONFIG_PKG_USING_MULTIBUTTON is not set -# CONFIG_PKG_USING_FLEXIBLE_BUTTON is not set -# CONFIG_PKG_USING_CANFESTIVAL is not set -# CONFIG_PKG_USING_ZLIB is not set -# CONFIG_PKG_USING_DSTR is not set -# CONFIG_PKG_USING_TINYFRAME is not set -# CONFIG_PKG_USING_KENDRYTE_DEMO is not set -# CONFIG_PKG_USING_DIGITALCTRL is not set -# CONFIG_PKG_USING_UPACKER is not set -# CONFIG_PKG_USING_UPARAM is not set - -# -# samples: kernel and components samples -# -# CONFIG_PKG_USING_KERNEL_SAMPLES is not set -# CONFIG_PKG_USING_FILESYSTEM_SAMPLES is not set -# CONFIG_PKG_USING_NETWORK_SAMPLES is not set -# CONFIG_PKG_USING_PERIPHERAL_SAMPLES is not set -# CONFIG_PKG_USING_HELLO is not set -# CONFIG_PKG_USING_VI is not set -# CONFIG_PKG_USING_NNOM is not set -# CONFIG_PKG_USING_LIBANN is not set -# CONFIG_PKG_USING_ELAPACK is not set -# CONFIG_PKG_USING_ARMv7M_DWT is not set -# CONFIG_PKG_USING_VT100 is not set -# CONFIG_PKG_USING_TETRIS is not set -# CONFIG_PKG_USING_ULAPACK is not set -# CONFIG_PKG_USING_UKAL is not set -# CONFIG_PKG_USING_CRCLIB is not set -# CONFIG_PKG_USING_THREES is not set -# CONFIG_PKG_USING_2048 is not set -# CONFIG_PKG_USING_LWGPS is not set -# CONFIG_PKG_USING_TENSORFLOWLITEMICRO is not set - -# -# Hardware Drivers Config -# - -# -# On-chip Peripheral Drivers -# -CONFIG_BSP_USING_GPIO=y - -# -# UART Drivers -# -# CONFIG_BSP_USING_UART0 is not set -CONFIG_BSP_USING_UART1=y - -# -# SPI Drivers -# -# CONFIG_BSP_USING_SPI0 is not set -# CONFIG_BSP_USING_SPI1 is not set - -# -# I2C Drivers -# -# CONFIG_BSP_USING_I2C0 is not set -# CONFIG_BSP_USING_I2C1 is not set - -# -# PWM Drivers -# -# CONFIG_BSP_USING_PWM0 is not set -# CONFIG_BSP_USING_PWM1 is not set -# CONFIG_BSP_USING_PWM2 is not set -# CONFIG_BSP_USING_PWM3 is not set - -# -# HWtimer Drivers -# -# CONFIG_BSP_USING_HWTIMER0 is not set -# CONFIG_BSP_USING_HWTIMER1 is not set -# CONFIG_BSP_USING_HWTIMER2 is not set -# CONFIG_BSP_USING_HWTIMER3 is not set - -# -# RTC Drivers -# -# CONFIG_BSP_USING_RTC is not set - -# -# PM Drivers -# -# CONFIG_BSP_USING_PM is not set - -# -# ADC Drivers -# -# CONFIG_BSP_USING_ADC is not set - -# -# Onboard Peripheral Drivers -# -# CONFIG_BSP_USING_SPI_FLASH is not set - -# -# Offboard Peripheral Drivers -# - -# -# Peripheral Drivers test example -# -# CONFIG_BSP_USING_EXAMPLE_ADC_VOL is not set -# CONFIG_BSP_USING_EXAMPLE_HWTIMER is not set -# CONFIG_BSP_USING_EXAMPLE_I2C is not set -# CONFIG_BSP_USING_EXAMPLE_LED_BLINK is not set -# CONFIG_BSP_USING_EXAMPLE_PIN_BEEP is not set -# CONFIG_BSP_USING_EXAMPLE_PWM_LED is not set -# CONFIG_BSP_USING_EXAMPLE_RTC is not set -# CONFIG_BSP_USING_EXAMPLE_SPI is not set -# CONFIG_BSP_USING_EXAMPLE_UART is not set -# CONFIG_BSP_USING_EXAMPLE_PM is not set -CONFIG_SOC_ES32F0334LT=y diff --git a/bsp/essemi/es32f0334/Kconfig b/bsp/essemi/es32f0334/Kconfig deleted file mode 100644 index 87abf157f5..0000000000 --- a/bsp/essemi/es32f0334/Kconfig +++ /dev/null @@ -1,26 +0,0 @@ -mainmenu "RT-Thread Configuration" - -config BSP_DIR - string - option env="BSP_ROOT" - default "." - -config RTT_DIR - string - option env="RTT_ROOT" - default "../../.." - -config PKGS_DIR - string - option env="PKGS_ROOT" - default "packages" - -source "$RTT_DIR/Kconfig" -source "$PKGS_DIR/Kconfig" -source "drivers/Kconfig" - -config SOC_ES32F0334LT - bool - select RT_USING_COMPONENTS_INIT - select RT_USING_USER_MAIN - default y diff --git a/bsp/essemi/es32f0334/README.md b/bsp/essemi/es32f0334/README.md deleted file mode 100644 index ac98561868..0000000000 --- a/bsp/essemi/es32f0334/README.md +++ /dev/null @@ -1,118 +0,0 @@ -# ES-PDS-ES32F0334 开发板 BSP 说明 -标签： EastSoft、国产MCU、Cortex-M0、ES32F0334LT - -## 1. 简介 - -本文档为上海东软载波微电子开发团队为 ES-PDS-ES32F0334 开发板提供的 BSP (板级支持包) 说明。 -通过阅读本文档，开发者可以快速地上手该 BSP，将 RT-Thread 运行在开发板上。 - -### 1.1 开发板介绍 - -主要内容如下： -ES-PDS-ES32F0334 是东软载波微电子官方推出的一款基于 ARM Cortex-M0 内核的开发板，最高主频为 48MHz，可满足基础功能测试及高端功能扩展等开发需求。 - -开发板外观如下图所示： - -ES-PDS-ES32F0334-V1.1 - -![ES32F0334](figures/ES-PDS-ES32F0334-V1.1.jpg) - -该开发板常用 **板载资源** 如下： - -- MCU：ES32F0334LT，主频 48MHz，32KB SRAM，256KB FLASH，54 GPIOs -- 外部模块：SPI FLASH (MX25L64，8MB)、I2C EEPROM (M24C04，512B) -- 常用外设 - - LED：2个，(PA12/PC12) - - 液晶屏：1个 - - 可调电阻：1个 - - 按键：3个，K1(PF00)，K2（PF01)，RESET(MRST) -- 常用接口：GPIO、UART、SPI、I2C -- 调试接口，ESLinkⅡ(EastSoft 官方推出的开发工具，有标准版和mini版两种版本，均自带 CDC 串口功能) SWD 下载 - -外设支持: - -本 BSP 目前对外设的支持情况如下： - -| **板载外设** | **支持情况** | **备注** | -| :---------------- | :----------: | :------------------------------------| -| SPI FLASH | 支持 | SPI0 | -| **片上外设** | **支持情况** | **备注** | -| GPIO | 支持 | 54 GPIOs | -| UART | 支持 | UART0/1 | -| SPI | 支持 | SPI0/1 | -| I2C | 支持 | I2C0/1 | -| PWM | 支持 | PWM0/1/2/3 | -| TIMER | 支持 | TIMER0/1/2/3 | -| RTC | 支持 | RTC | -| PM | 支持 | Power Management | -| ADC | 支持 | ADC0 | - -更多详细信息请咨询[上海东软载波微电子技术支持](http://www.essemi.com/) - -## 2. 快速上手 - -本 BSP 为开发者提供 MDK5 工程。下面以 MDK5 开发环境为例，介绍如何将系统运行起来。 - -### 硬件连接 - -使用 ESLinkⅡ (自带 CDC 串口)或 Jlink 等调试工具连接开发板到 PC，拨动开关选择使用调试工具供电或使用外部电源供电。若使用 Jlink 等调试工具，还需要将 UART1_TX(PC10)、UART1_RX(PC11)、GND 接到串口工具上。 - -使用ESlinkⅡ(mini)连接开发板如下图所示： - -ESLinkⅡ(mini) + ES-PDS-ES32F0334-V1.1 - -![ESLinkII](figures/ESLinkII-mini.jpg) - -### 编译下载 - -双击 project.uvprojx 文件，打开 MDK5 工程，工程默认配置使用 JLink 下载程序，在通过 JLink 连接开发板的基础上，点击下载按钮即可下载程序到开发板，如果使用 ESLinkⅡ，则选择 "CMSIS-DAP Debugger"，连接正常后即可编译并下载程序到开发板。 - -### 运行结果 - -下载程序成功之后，系统会自动运行，观察串口输出的信息，同时开发板LED闪烁。 - -```bash - \ | / -- RT - Thread Operating System - / | \ 4.0.0 build Jan 28 2019 - 2006 - 2018 Copyright by rt-thread team -msh > -``` -## 3. 进阶使用 - -此 BSP 默认只开启了 GPIO 和 uart1 的功能，如果需使用 Flash 等更多高级功能，需要利用 ENV 工具对 BSP 进行配置，步骤如下： - -1. 在 bsp 下打开 env 工具。 - -2. 输入`menuconfig`命令配置工程，配置好之后保存退出。 - - a）如果需要使用内核用例，先配置rt-thread内核，如图： - - ![kernel_config](figures/k_conf.jpg) - - 然后配置内核用例，如图： - - ![kernel_samples](figures/k_ex.jpg) - - b）如果需要使用驱动用例：先使能驱动，如图： - - ![driver_config](figures/drv_conf.jpg) - - 然后配置驱动用例，如图： - - ![driver_sample](figures/drv_ex.jpg) - -3. 输入`pkgs --update`命令更新软件包。 - -4. 输入`scons --target=mdk5/iar` 命令重新生成工程。 - -更多 Env 工具的详细介绍请参考 [RT-Thread 文档中心](https://www.rt-thread.org/document/site/) - -## 4. 联系人信息 - -- [liuhongyan](https://gitee.com/liuhongyan98) - -## 5. 参考 - -- [ EastSoft 官网](http://www.essemi.com) - diff --git a/bsp/essemi/es32f0334/SConscript b/bsp/essemi/es32f0334/SConscript deleted file mode 100644 index 468297b6a9..0000000000 --- a/bsp/essemi/es32f0334/SConscript +++ /dev/null @@ -1,14 +0,0 @@ -# for module compiling -import os -Import('RTT_ROOT') - -objs = [] -cwd = str(Dir('#')) -list = os.listdir(cwd) - -for d in list: - path = os.path.join(cwd, d) - if os.path.isfile(os.path.join(path, 'SConscript')): - objs = objs + SConscript(os.path.join(d, 'SConscript')) - -Return('objs') diff --git a/bsp/essemi/es32f0334/SConstruct b/bsp/essemi/es32f0334/SConstruct deleted file mode 100644 index e75d75371b..0000000000 --- a/bsp/essemi/es32f0334/SConstruct +++ /dev/null @@ -1,40 +0,0 @@ -import os -import sys -import rtconfig - -if os.getenv('RTT_ROOT'): - RTT_ROOT = os.getenv('RTT_ROOT') -else: - RTT_ROOT = os.path.normpath(os.getcwd() + '/../../..') - -sys.path = sys.path + [os.path.join(RTT_ROOT, 'tools')] -try: - from building import * -except: - print('Cannot found RT-Thread root directory, please check RTT_ROOT') - print(RTT_ROOT) - exit(-1) - -TARGET = 'rtthread.' + rtconfig.TARGET_EXT - -DefaultEnvironment(tools=[]) -env = Environment(tools = ['mingw'], - AS = rtconfig.AS, ASFLAGS = rtconfig.AFLAGS, - CC = rtconfig.CC, CCFLAGS = rtconfig.CFLAGS, - AR = rtconfig.AR, ARFLAGS = '-rc', - LINK = rtconfig.LINK, LINKFLAGS = rtconfig.LFLAGS) -env.PrependENVPath('PATH', rtconfig.EXEC_PATH) - -if rtconfig.PLATFORM == 'iar': - env.Replace(CCCOM = ['$CC $CCFLAGS $CPPFLAGS $_CPPDEFFLAGS $_CPPINCFLAGS -o $TARGET $SOURCES']) - env.Replace(ARFLAGS = ['']) - env.Replace(LINKCOM = env["LINKCOM"] + ' --map project.map') - -Export('RTT_ROOT') -Export('rtconfig') - -# prepare building environment -objs = PrepareBuilding(env, RTT_ROOT, has_libcpu=False) - -# make a building -DoBuilding(TARGET, objs) diff --git a/bsp/essemi/es32f0334/applications/SConscript b/bsp/essemi/es32f0334/applications/SConscript deleted file mode 100644 index e0c84e8f14..0000000000 --- a/bsp/essemi/es32f0334/applications/SConscript +++ /dev/null @@ -1,11 +0,0 @@ -Import('RTT_ROOT') -Import('rtconfig') -from building import * - -cwd = os.path.join(str(Dir('#')), 'applications') -src = Glob('*.c') - -CPPPATH = [cwd, str(Dir('#'))] -group = DefineGroup('Applications', src, depend = [''], CPPPATH = CPPPATH) - -Return('group') diff --git a/bsp/essemi/es32f0334/applications/main.c b/bsp/essemi/es32f0334/applications/main.c deleted file mode 100644 index fbf34fb9af..0000000000 --- a/bsp/essemi/es32f0334/applications/main.c +++ /dev/null @@ -1,30 +0,0 @@ -/* - * Copyright (C) 2018 Shanghai Eastsoft Microelectronics Co., Ltd. - * - * SPDX-License-Identifier: Apache-2.0 - * - * Change Logs: - * Date Author Notes - * 2019-03-01 wangyq the first version - */ - -#include -#include - -#define LED_PIN 53 - -int main(void) -{ - int count = 1; - /* set PC12 pin mode to output */ - rt_pin_mode(LED_PIN, PIN_MODE_OUTPUT); - - while (count++) - { - rt_pin_write(LED_PIN, PIN_HIGH); - rt_thread_mdelay(500); - rt_pin_write(LED_PIN, PIN_LOW); - rt_thread_mdelay(500); - } - return RT_EOK; -} diff --git a/bsp/essemi/es32f0334/drivers/Kconfig b/bsp/essemi/es32f0334/drivers/Kconfig deleted file mode 100644 index 05c29ef313..0000000000 --- a/bsp/essemi/es32f0334/drivers/Kconfig +++ /dev/null @@ -1,176 +0,0 @@ -menu "Hardware Drivers Config" - - menu "On-chip Peripheral Drivers" - config BSP_USING_GPIO - bool "Enable GPIO" - select RT_USING_PIN - default y - - menu "UART Drivers" - config BSP_USING_UART0 - bool "Enable UART0 PB10/PB11(T/R)" - select RT_USING_SERIAL - default n - - config BSP_USING_UART1 - bool "Enable UART1 PC10/PC11(T/R)" - select RT_USING_SERIAL - default y - - endmenu - - menu "SPI Drivers" - config BSP_USING_SPI0 - bool "Enable SPI0 BUS PB03/PB04/PB05(CLK/MISO/MOSI)" - select RT_USING_SPI - select RT_USING_PIN - default n - - config BSP_USING_SPI1 - bool "Enable SPI1 BUS PB13/PB14/PB15(CLK/MISO/MOSI)" - select RT_USING_SPI - select RT_USING_PIN - default n - endmenu - - menu "I2C Drivers" - config BSP_USING_I2C0 - bool "Enable I2C0 BUS PB08/PB09(SCL/SDA)" - select RT_USING_I2C - default n - config BSP_USING_I2C1 - bool "Enable I2C1 BUS PB10/PB11(SCL/SDA)" - select RT_USING_I2C - default n - endmenu - - menu "PWM Drivers" - config BSP_USING_PWM0 - bool "Using PWM0 PA08/PA09/PA10/PA11" - select RT_USING_PWM - default n - - config BSP_USING_PWM1 - bool "Using PWM1 PB06/PB07/PB08" - select RT_USING_PWM - default n - - config BSP_USING_PWM2 - bool "Using PWM2 PA00/PA01" - select RT_USING_PWM - default n - - config BSP_USING_PWM3 - bool "Using PWM3 PC06/PC07" - select RT_USING_PWM - default n - endmenu - - menu "HWtimer Drivers" - config BSP_USING_HWTIMER0 - bool "Using timer0" - select RT_USING_HWTIMER - default n - - config BSP_USING_HWTIMER1 - bool "Using timer1" - select RT_USING_HWTIMER - default n - - config BSP_USING_HWTIMER2 - bool "Using timer2" - select RT_USING_HWTIMER - default n - - config BSP_USING_HWTIMER3 - bool "Using timer3" - select RT_USING_HWTIMER - default n - endmenu - - menu "RTC Drivers" - config BSP_USING_RTC - bool "Using RTC" - select RT_USING_RTC - default n - endmenu - - menu "PM Drivers" - config BSP_USING_PM - bool "Using PM" - select RT_USING_PM - default n - endmenu - - menu "ADC Drivers" - config BSP_USING_ADC - bool "Using ADC" - select RT_USING_ADC - default n - endmenu - - endmenu - - menu "Onboard Peripheral Drivers" - - config BSP_USING_SPI_FLASH - bool "Enable SPI FLASH (W25Q64 spi0)" - select BSP_USING_SPI - select BSP_USING_SPI0 - select RT_USING_SFUD - select RT_SFUD_USING_SFDP - default n - - endmenu - - menu "Offboard Peripheral Drivers" - - endmenu - - - menu "Peripheral Drivers test example" - - config BSP_USING_EXAMPLE_ADC_VOL - bool "BSP_USING_EXAMPLE_ADC_VOL" - default n - - config BSP_USING_EXAMPLE_HWTIMER - bool "BSP_USING_EXAMPLE_HWTIMER" - default n - - config BSP_USING_EXAMPLE_I2C - bool "BSP_USING_EXAMPLE_I2C" - default n - - config BSP_USING_EXAMPLE_LED_BLINK - bool "BSP_USING_EXAMPLE_LED_BLINK" - default y - - config BSP_USING_EXAMPLE_PIN_BEEP - bool "BSP_USING_EXAMPLE_PIN_BEEP" - default y - - config BSP_USING_EXAMPLE_PWM_LED - bool "BSP_USING_EXAMPLE_PWM_LED" - default n - - config BSP_USING_EXAMPLE_RTC - bool "BSP_USING_EXAMPLE_RTC" - default n - - config BSP_USING_EXAMPLE_SPI - bool "BSP_USING_EXAMPLE_SPI" - default n - - config BSP_USING_EXAMPLE_UART - bool "BSP_USING_EXAMPLE_UART" - default y - - config BSP_USING_EXAMPLE_PM - bool "BSP_USING_EXAMPLE_PM" - default n - - - endmenu - -endmenu diff --git a/bsp/essemi/es32f0334/drivers/SConscript b/bsp/essemi/es32f0334/drivers/SConscript deleted file mode 100644 index 78bd814312..0000000000 --- a/bsp/essemi/es32f0334/drivers/SConscript +++ /dev/null @@ -1,94 +0,0 @@ -from building import * - -cwd = GetCurrentDir() - -objs = [] - -# add the general drivers. -src = Split(''' -board.c -''') - -# add gpio code -if GetDepend('RT_USING_PIN'): - src += ['drv_gpio.c'] - -# add serial driver code -if GetDepend('BSP_USING_UART0') or GetDepend('BSP_USING_UART1'): - src += ['drv_uart.c'] - -# add spi driver code -if GetDepend('BSP_USING_SPI0') or GetDepend('BSP_USING_SPI1'): - src += ['drv_spi.c'] - -# add i2c driver code -if GetDepend('BSP_USING_I2C0') or GetDepend('BSP_USING_I2C1'): - src += ['drv_i2c.c'] - -# add spi flash driver code -if GetDepend('BSP_USING_SPI_FLASH'): - src += ['drv_spiflash.c'] - -# add pwm driver code -if GetDepend('BSP_USING_PWM0') or GetDepend('BSP_USING_PWM1') or GetDepend('BSP_USING_PWM2') or GetDepend('BSP_USING_PWM3'): - src += ['drv_pwm.c'] - -# add hwtimer driver code -if GetDepend('BSP_USING_HWTIMER0') or GetDepend('BSP_USING_HWTIMER1') or GetDepend('BSP_USING_HWTIMER2') or GetDepend('BSP_USING_HWTIMER3'): - src += ['drv_hwtimer.c'] - -# add rtc driver code -if GetDepend(['BSP_USING_RTC']): - src += ['drv_rtc.c'] - -# add pm driver code -if GetDepend(['BSP_USING_PM']): - src += ['drv_pm.c'] - src += ['drv_lptim.c'] - -# add adc driver code -if GetDepend(['BSP_USING_ADC']): - src += ['drv_adc.c'] - -CPPPATH = [cwd] -group = DefineGroup('Drivers', src, depend = [''], CPPPATH = CPPPATH) -objs = objs + group - -src = [] -cwd = GetCurrentDir() -include_path = [cwd] - -if GetDepend('BSP_USING_EXAMPLE_ADC_VOL'): - src += ['bsp_driver_example/adc_vol_sample.c'] - -if GetDepend('BSP_USING_EXAMPLE_HWTIMER'): - src += ['bsp_driver_example/hwtimer_sample.c'] - -if GetDepend('BSP_USING_EXAMPLE_I2C'): - src += ['bsp_driver_example/i2c_sample.c'] - -if GetDepend('BSP_USING_EXAMPLE_LED_BLINK'): - src += ['bsp_driver_example/led_blink_sample.c'] - -if GetDepend('BSP_USING_EXAMPLE_PIN_BEEP'): - src += ['bsp_driver_example/pin_beep_sample.c'] - -if GetDepend('BSP_USING_EXAMPLE_PWM_LED'): - src += ['bsp_driver_example/pwm_led_sample.c'] - -if GetDepend('BSP_USING_EXAMPLE_RTC'): - src += ['bsp_driver_example/rtc_sample.c'] - -if GetDepend('BSP_USING_EXAMPLE_UART'): - src += ['bsp_driver_example/uart_sample.c'] - -if GetDepend('BSP_USING_EXAMPLE_SPI'): - src += ['bsp_driver_example/spi_sample.c'] - -if GetDepend('BSP_USING_EXAMPLE_PM'): - src += ['bsp_driver_example/pm_sample.c'] - -group = DefineGroup('bsp-drivers-test-samples', src, depend = [''], CPPPATH = include_path) - -objs = objs + group -Return('objs') \ No newline at end of file diff --git a/bsp/essemi/es32f0334/drivers/board.c b/bsp/essemi/es32f0334/drivers/board.c deleted file mode 100644 index f41a66fbb2..0000000000 --- a/bsp/essemi/es32f0334/drivers/board.c +++ /dev/null @@ -1,123 +0,0 @@ -/* - * Copyright (C) 2018 Shanghai Eastsoft Microelectronics Co., Ltd. - * - * SPDX-License-Identifier: Apache-2.0 - * - * Change Logs: - * Date Author Notes - * 2019-03-01 wangyq the first version - */ - -#include -#include -#include "board.h" -#include "drv_uart.h" -#include "drv_gpio.h" -#include -#include - -/** - * @addtogroup es32f0 - */ - -/*@{*/ - -/******************************************************************************* -* Function Name : NVIC_Configuration -* Description : Configures Vector Table base location. -* Input : None -* Output : None -* Return : None -*******************************************************************************/ -void NVIC_Configuration(void) -{ -} - -/******************************************************************************* - * Function Name : SystemClock_Configuration - * Description : Configures the System Clock. - * Input : None - * Output : None - * Return : None - *******************************************************************************/ -void SystemClock_Config(void) -{ - /* hosc 12MHz, from hosc/3 pll to 48MHz */ - ald_cmu_pll1_config(CMU_PLL1_INPUT_HOSC_3, CMU_PLL1_OUTPUT_48M); - - /* MCLK 48MHz */ - ald_cmu_clock_config(CMU_CLOCK_PLL1, 48000000); -} - -/******************************************************************************* - * Function Name : SysTick_Configuration - * Description : Configures the SysTick for OS tick. - * Input : None - * Output : None - * Return : None - *******************************************************************************/ -void SysTick_Configuration(void) -{ - /* ticks = sysclk / RT_TICK_PER_SECOND */ - SysTick_Config(ald_cmu_get_sys_clock() / RT_TICK_PER_SECOND); -} - -/** - * This is the timer interrupt service routine. - * - */ -void SysTick_Handler(void) -{ - /* enter interrupt */ - rt_interrupt_enter(); - - rt_tick_increase(); - - /* leave interrupt */ - rt_interrupt_leave(); -} - -/*@}*/ -/** - * This function will initial ES32F0 board. - */ -void rt_hw_board_init(void) -{ - /* NVIC Configuration */ - NVIC_Configuration(); - - /*System Clock Configuration */ - SystemClock_Config(); - - /* Configure the SysTick */ - SysTick_Configuration(); - -#ifdef RT_USING_HEAP - rt_system_heap_init((void *)HEAP_BEGIN, (void *)HEAP_END); -#endif -#ifdef RT_USING_COMPONENTS_INIT - rt_components_board_init(); -#endif -#ifdef RT_USING_CONSOLE - rt_console_set_device(RT_CONSOLE_DEVICE_NAME); -#endif -} - -/** - * This function will delay for some us. - * - * @param us the delay time of us - */ -void rt_hw_us_delay(rt_uint32_t us) -{ - unsigned int start, now, delta, reload, us_tick; - start = SysTick->VAL; - reload = SysTick->LOAD; - us_tick = ald_cmu_get_sys_clock() / 1000000UL; - do - { - now = SysTick->VAL; - delta = start > now ? start - now : reload + start - now; - } - while (delta < us_tick * us); -} diff --git a/bsp/essemi/es32f0334/drivers/board.h b/bsp/essemi/es32f0334/drivers/board.h deleted file mode 100644 index 5df26393eb..0000000000 --- a/bsp/essemi/es32f0334/drivers/board.h +++ /dev/null @@ -1,36 +0,0 @@ -/* - * Copyright (C) 2018 Shanghai Eastsoft Microelectronics Co., Ltd. - * - * SPDX-License-Identifier: Apache-2.0 - * - * Change Logs: - * Date Author Notes - * 2019-03-01 wangyq the first version - */ - -// <<< Use Configuration Wizard in Context Menu >>> -#ifndef __BOARD_H__ -#define __BOARD_H__ - -#include -#include - -#define ES32F0_SRAM_SIZE 0x8000 -#define ES32F0_SRAM_END (0x20000000 + ES32F0_SRAM_SIZE) - -#if defined(__CC_ARM) || defined(__CLANG_ARM) - extern int Image$$RW_IRAM1$$ZI$$Limit; - #define HEAP_BEGIN ((void *)&Image$$RW_IRAM1$$ZI$$Limit) -#elif __ICCARM__ - #pragma section="HEAP" - #define HEAP_BEGIN (__segment_end("HEAP")) -#else - extern int __bss_end; - #define HEAP_BEGIN ((void *)&__bss_end) -#endif - -#define HEAP_END ES32F0_SRAM_END - -void rt_hw_board_init(void); - -#endif diff --git a/bsp/essemi/es32f0334/drivers/bsp_driver_example/.gitignore b/bsp/essemi/es32f0334/drivers/bsp_driver_example/.gitignore deleted file mode 100644 index c6127b38c1..0000000000 --- a/bsp/essemi/es32f0334/drivers/bsp_driver_example/.gitignore +++ /dev/null @@ -1,52 +0,0 @@ -# Prerequisites -*.d - -# Object files -*.o -*.ko -*.obj -*.elf - -# Linker output -*.ilk -*.map -*.exp - -# Precompiled Headers -*.gch -*.pch - -# Libraries -*.lib -*.a -*.la -*.lo - -# Shared objects (inc. Windows DLLs) -*.dll -*.so -*.so.* -*.dylib - -# Executables -*.exe -*.out -*.app -*.i*86 -*.x86_64 -*.hex - -# Debug files -*.dSYM/ -*.su -*.idb -*.pdb - -# Kernel Module Compile Results -*.mod* -*.cmd -.tmp_versions/ -modules.order -Module.symvers -Mkfile.old -dkms.conf diff --git a/bsp/essemi/es32f0334/drivers/bsp_driver_example/README.md b/bsp/essemi/es32f0334/drivers/bsp_driver_example/README.md deleted file mode 100644 index 80f12e1949..0000000000 --- a/bsp/essemi/es32f0334/drivers/bsp_driver_example/README.md +++ /dev/null @@ -1,47 +0,0 @@ -# 外设驱动测试用例 - -## 1、介绍 - -这个软件包包含一些外设设备操作的例程。 - -### 1.1 例程说明 - -| 文件 | 说明 | -| ---------------- | ------------------------------- | -| adc_vol_sample.c | 使用 ADC 设备转换电压数据 | -| can_sample.c | 通过 CAN 设备发送一帧，并创建一个线程接收数据然后打印输出。 | -| hwtimer_sample.c | 使用 硬件定时器定时 | -| i2c_sample.c | 使用 i2c 设备进行读写 | -| pm.c | 反复进入不同程度的睡眠。 | -| led_blink_sample.c | 使用 pin 设备控制 LED 闪烁 | -| pin_beep_sample.c | 使用 pin 设备控制蜂鸣器 | -| pwm_led_sample.c | 使用 pwm 设备控制 LED 的亮度 | -| rtc_sample.c | 使用 rtc 设备设置年月日时分秒信息 | -| spi_sample.c | 使用 spi 设备进行读写 | -| uart_sample.c | 使用 serial 设备中断接收及轮询发送模式收发数据 | - -### 1.2 依赖 - -依赖设备管理模块提供的设备驱动。 - -## 2、如何打开 外设驱动测试用例 - -使用 外设驱动测试用例 需要在 RT-Thread 的menuconfig中选择它，具体路径如下： - -``` -Hardware Driver Config ---> - Peripheral Driver test example---> -``` - -## 3、使用 外设驱动测试用例 - -在打开 Peripheral Driver test example 后，当进行 BSP 编译时，选择的软件包相关源代码会被加入到 BSP 工程中进行编译。 - -## 4、注意事项 - -暂无。 - -## 5、联系方式 & 感谢 - -* 维护：[misonyo](https://github.com/misonyo) -* 主页：https://github.com/RT-Thread-packages/peripheral-sample diff --git a/bsp/essemi/es32f0334/drivers/bsp_driver_example/adc_vol_sample.c b/bsp/essemi/es32f0334/drivers/bsp_driver_example/adc_vol_sample.c deleted file mode 100644 index 19eed3f35d..0000000000 --- a/bsp/essemi/es32f0334/drivers/bsp_driver_example/adc_vol_sample.c +++ /dev/null @@ -1,57 +0,0 @@ -/* - * Copyright (c) 2006-2018, RT-Thread Development Team - * - * SPDX-License-Identifier: Apache-2.0 - * - * Change Logs: - * Date Author Notes - * 2018-11-29 misonyo first implementation. - */ -/* - * 程序清单： ADC 设备使用例程 - * 例程导出了 adc_sample 命令到控制终端 - * 命令调用格式：adc_sample - * 程序功能：通过 ADC 设备采样电压值并转换为数值。 - * 示例代码参考电压为3.3V,转换位数为12位。 -*/ - -#include -#include - -#define ADC_DEV_NAME "adc0" /* ADC 设备名称 */ -#define ADC_DEV_CHANNEL 5 /* PA1 ADC 通道 */ -#define REFER_VOLTAGE 330 /* 参考电压 3.3V,数据精度乘以100保留2位小数*/ -#define CONVERT_BITS (1 << 12) /* 转换位数为12位 */ - -static int adc_vol_sample(int argc, char *argv[]) -{ - rt_adc_device_t adc_dev; - rt_uint32_t value, vol; - rt_err_t ret = RT_EOK; - - /* 查找设备 */ - adc_dev = (rt_adc_device_t)rt_device_find(ADC_DEV_NAME); - if (adc_dev == RT_NULL) - { - rt_kprintf("adc sample run failed! can't find %s device!\n", ADC_DEV_NAME); - return RT_ERROR; - } - - /* 使能设备 */ - ret = rt_adc_enable(adc_dev, ADC_DEV_CHANNEL); - - /* 读取采样值 */ - value = rt_adc_read(adc_dev, ADC_DEV_CHANNEL); - rt_kprintf("the value is :%d \n", value); - - /* 转换为对应电压值 */ - vol = value * REFER_VOLTAGE / CONVERT_BITS; - rt_kprintf("the voltage is :%d.%02d \n", vol / 100, vol % 100); - - /* 关闭通道 */ - ret = rt_adc_disable(adc_dev, ADC_DEV_CHANNEL); - - return ret; -} -/* 导出到 msh 命令列表中 */ -MSH_CMD_EXPORT(adc_vol_sample, adc voltage convert sample); diff --git a/bsp/essemi/es32f0334/drivers/bsp_driver_example/can_sample.c b/bsp/essemi/es32f0334/drivers/bsp_driver_example/can_sample.c deleted file mode 100644 index e63b11451d..0000000000 --- a/bsp/essemi/es32f0334/drivers/bsp_driver_example/can_sample.c +++ /dev/null @@ -1,144 +0,0 @@ -/* - * Copyright (c) 2006-2018, RT-Thread Development Team - * - * SPDX-License-Identifier: Apache-2.0 - * - * Change Logs: - * Date Author Notes - * 2019-06-25 misonyo first implementation. - */ -/* - * 程序清单：这是一个 CAN 设备使用例程 - * 例程导出了 can_sample 命令到控制终端 - * 命令调用格式：can_sample can2 - * 命令解释：命令第二个参数是要使用的 CAN 设备名称，为空则使用默认的 CAN 设备 - * 程序功能：通过 CAN 设备发送一帧，并创建一个线程接收数据然后打印输出。 -*/ - -#include -#include "rtdevice.h" - -#define CAN_DEV_NAME "can2" /* CAN 设备名称 */ - -static struct rt_semaphore rx_sem; /* 用于接收消息的信号量 */ -static rt_device_t can_dev; /* CAN 设备句柄 */ - -/* 接收数据回调函数 */ -static rt_err_t can_rx_call(rt_device_t dev, rt_size_t size) -{ - /* CAN 接收到数据后产生中断，调用此回调函数，然后发送接收信号量 */ - rt_sem_release(&rx_sem); - - return RT_EOK; -} - -static void can_rx_thread(void *parameter) -{ - int i; - struct rt_can_msg rxmsg = {0}; - - /* 设置接收回调函数 */ - rt_device_set_rx_indicate(can_dev, can_rx_call); - -#ifdef RT_CAN_USING_HDR - - rt_err_t res; - - struct rt_can_filter_item items[5] = - { - RT_CAN_FILTER_ITEM_INIT(0x100, 0, 0, 0, 0x700, RT_NULL, RT_NULL), /* std,match ID:0x100~0x1ff，hdr为-1，设置默认过滤表 */ - RT_CAN_FILTER_ITEM_INIT(0x300, 0, 0, 0, 0x700, RT_NULL, RT_NULL), /* std,match ID:0x300~0x3ff，hdr为-1 */ - RT_CAN_FILTER_ITEM_INIT(0x211, 0, 0, 0, 0x7ff, RT_NULL, RT_NULL), /* std,match ID:0x211，hdr为-1 */ - RT_CAN_FILTER_STD_INIT(0x486, RT_NULL, RT_NULL), /* std,match ID:0x486，hdr为-1 */ - {0x555, 0, 0, 0, 0x7ff, 7,} /* std,match ID:0x555，hdr为7，指定设置7号过滤表 */ - }; - struct rt_can_filter_config cfg = {5, 1, items}; /* 一共有5个过滤表 */ - /* 设置硬件过滤表 */ - res = rt_device_control(can_dev, RT_CAN_CMD_SET_FILTER, &cfg); - RT_ASSERT(res == RT_EOK); -#endif - - while (1) - { - /* hdr值为-1，表示直接从uselist链表读取数据 */ - rxmsg.hdr = -1; - /* 阻塞等待接收信号量 */ - rt_sem_take(&rx_sem, RT_WAITING_FOREVER); - /* 从CAN读取一帧数据 */ - rt_device_read(can_dev, 0, &rxmsg, sizeof(rxmsg)); - /* 打印数据ID及内容 */ - rt_kprintf("ID:%x ", rxmsg.id); - for (i = 0; i < 8; i++) - { - rt_kprintf("%2x ", rxmsg.data[i]); - } - - rt_kprintf("\n"); - } -} - -int can_sample(int argc, char *argv[]) -{ - struct rt_can_msg msg = {0}; - rt_err_t res; - rt_size_t size; - rt_thread_t thread; - char can_name[RT_NAME_MAX]; - - if (argc == 2) - { - rt_strncpy(can_name, argv[1], RT_NAME_MAX); - } - else - { - rt_strncpy(can_name, CAN_DEV_NAME, RT_NAME_MAX); - } - - can_dev = rt_device_find(can_name); - if (!can_dev) - { - rt_kprintf("find %s failed!\n", can_name); - return RT_ERROR; - } - - /* 初始化CAN接收信号量 */ - rt_sem_init(&rx_sem, "rx_sem", 0, RT_IPC_FLAG_FIFO); - - /* 以中断接收及发送方式打开CAN设备 */ - res = rt_device_open(can_dev, RT_DEVICE_FLAG_INT_TX | RT_DEVICE_FLAG_INT_RX); - RT_ASSERT(res == RT_EOK); - - thread = rt_thread_create("can_rx", can_rx_thread, RT_NULL, 1024, 25, 10); - if (thread != RT_NULL) - { - rt_thread_startup(thread); - } - else - { - rt_kprintf("create can_rx thread failed!\n"); - } - - msg.id = 0x78; /* ID为0x78 */ - msg.ide = RT_CAN_STDID; /* 标准格式 */ - msg.rtr = RT_CAN_DTR; /* 数据帧 */ - msg.len = 8; /* 数据长度为8 */ - /* 待发送的8字节数据 */ - msg.data[0] = 0x00; - msg.data[1] = 0x11; - msg.data[2] = 0x22; - msg.data[3] = 0x33; - msg.data[4] = 0x44; - msg.data[5] = 0x55; - msg.data[6] = 0x66; - msg.data[7] = 0x77; - /* 发送一帧CAN数据 */ - size = rt_device_write(can_dev, 0, &msg, sizeof(msg)); - if (size == 0) - { - rt_kprintf("can dev write data failed!\n"); - } - - return res; -} -/* 导出到 msh 命令列表中 */ -MSH_CMD_EXPORT(can_sample, can device sample); diff --git a/bsp/essemi/es32f0334/drivers/bsp_driver_example/hwtimer_sample.c b/bsp/essemi/es32f0334/drivers/bsp_driver_example/hwtimer_sample.c deleted file mode 100644 index e2e39664f3..0000000000 --- a/bsp/essemi/es32f0334/drivers/bsp_driver_example/hwtimer_sample.c +++ /dev/null @@ -1,85 +0,0 @@ -/* - * Copyright (c) 2006-2018, RT-Thread Development Team - * - * SPDX-License-Identifier: Apache-2.0 - * - * Change Logs: - * Date Author Notes - * 2018-11-30 misonyo first implementation. - */ -/* - * 程序清单：这是一个 hwtimer 设备使用例程 - * 例程导出了 hwtimer_sample 命令到控制终端 - * 命令调用格式：hwtimer_sample - * 程序功能：硬件定时器超时回调函数周期性的打印当前tick值，2次tick值之差换算为时间等同于定时时间值。 -*/ - -#include -#include - -#define HWTIMER_DEV_NAME "timer0" /* 定时器名称 */ - -/* 定时器超时回调函数 */ -static rt_err_t timeout_cb(rt_device_t dev, rt_size_t size) -{ - rt_kprintf("tick is :%d !\n", rt_tick_get()); - - return 0; -} - -static int hwtimer_sample(int argc, char *argv[]) -{ - rt_err_t ret = RT_EOK; - rt_hwtimerval_t timeout_s; /* 定时器超时值 */ - rt_device_t hw_dev = RT_NULL; /* 定时器设备句柄 */ - rt_hwtimer_mode_t mode; /* 定时器模式 */ - - /* 查找定时器设备 */ - hw_dev = rt_device_find(HWTIMER_DEV_NAME); - if (hw_dev == RT_NULL) - { - rt_kprintf("hwtimer sample run failed! can't find %s device!\n", HWTIMER_DEV_NAME); - return RT_ERROR; - } - - /* 以读写方式打开设备 */ - ret = rt_device_open(hw_dev, RT_DEVICE_OFLAG_RDWR); - if (ret != RT_EOK) - { - rt_kprintf("open %s device failed!\n", HWTIMER_DEV_NAME); - return ret; - } - - /* 设置超时回调函数 */ - rt_device_set_rx_indicate(hw_dev, timeout_cb); - - /* 设置模式为周期性定时器 */ - mode = HWTIMER_MODE_PERIOD; - ret = rt_device_control(hw_dev, HWTIMER_CTRL_MODE_SET, &mode); - if (ret != RT_EOK) - { - rt_kprintf("set mode failed! ret is :%d\n", ret); - return ret; - } - - /* 设置定时器超时值为5s并启动定时器 */ - timeout_s.sec = 5; /* 秒 */ - timeout_s.usec = 0; /* 微秒 */ - - if (rt_device_write(hw_dev, 0, &timeout_s, sizeof(timeout_s)) != sizeof(timeout_s)) - { - rt_kprintf("set timeout value failed\n"); - return RT_ERROR; - } - - /* 延时3500ms */ - rt_thread_mdelay(3500); - - /* 读取定时器当前值 */ - rt_device_read(hw_dev, 0, &timeout_s, sizeof(timeout_s)); - rt_kprintf("Read: Sec = %d, Usec = %d\n", timeout_s.sec, timeout_s.usec); - - return ret; -} -/* 导出到 msh 命令列表中 */ -MSH_CMD_EXPORT(hwtimer_sample, hwtimer sample); diff --git a/bsp/essemi/es32f0334/drivers/bsp_driver_example/i2c_sample.c b/bsp/essemi/es32f0334/drivers/bsp_driver_example/i2c_sample.c deleted file mode 100644 index 2d386433c6..0000000000 --- a/bsp/essemi/es32f0334/drivers/bsp_driver_example/i2c_sample.c +++ /dev/null @@ -1,97 +0,0 @@ -/* - * Copyright (C) 2018 Shanghai Eastsoft Microelectronics Co., Ltd. - * - * SPDX-License-Identifier: Apache-2.0 - * - * Change Logs: - * Date Author Notes - * 2020-12-15 liuhy first implementation. - */ -/* - * 程序清单：这是一个 I2C 设备使用例程 - * 例程导出了 i2c_io_sample 命令到控制终端 - * 命令调用格式：i2c_io_sample - * 命令解释：使用默认的I2C总线设备 - * 程序功能：通过 I2C 设备接收数据并打印，然后将接收的字符加1输出。 -*/ - -#include -#include - -#define I2C_BUS_NAME "i2c1" /* I2C总线设备名称 */ -#define SLAVE_ADDR 0x2D /* 从机地址 */ -#define STR_LEN 16 /* 接收发送的数据长度 */ - -static void i2c_io_sample(int argc, char *argv[]) -{ - - struct rt_i2c_bus_device *i2c_bus = RT_NULL; /* I2C总线设备句柄 */ - struct rt_i2c_msg temp_msg; /* I2C消息 */ - rt_uint8_t buffer[STR_LEN] = { 0U }; - rt_uint32_t i,num_msg; - rt_size_t s_stat; - - i2c_bus = (struct rt_i2c_bus_device *)rt_device_find(I2C_BUS_NAME); /* 通过名字获取I2C总线设备的句柄 */ - - if( i2c_bus == RT_NULL) - { - rt_kprintf("can't find i2c device :%s !\n",I2C_BUS_NAME); - - return; - } - - /*初始化消息*/ - temp_msg.addr = SLAVE_ADDR; /* 从机地址 */ - temp_msg.len = STR_LEN; /* 传输的数据长度 */ - temp_msg.buf = buffer; /* 读写缓存器 */ - - num_msg = 1; /* 传输一条消息 */ - - temp_msg.flags = RT_I2C_RD; /* I2C读 */ - s_stat = rt_i2c_transfer(i2c_bus,&temp_msg,num_msg); /* 传输消息 */ - - rt_thread_mdelay(400); - - if( s_stat == num_msg ) - { - rt_kprintf("receive successful. \n receive messege : %s \n:",buffer); - - for( i = 0 ; i < STR_LEN ; i++) - rt_kprintf(" %x",(unsigned int)buffer[i]); - - rt_kprintf("\n"); - } - else - { - rt_kprintf("device s% recieve fail \n buffer : s%\n",I2C_BUS_NAME,buffer); - return; - } - - for( i = 0 ; i < STR_LEN ; i++) - buffer[i]++; - - temp_msg.flags = RT_I2C_WR; /* I2C写 */ - s_stat = rt_i2c_transfer(i2c_bus,&temp_msg,num_msg); /* 传输一条 */ - - rt_thread_mdelay(400); - - if( s_stat == num_msg ) - { - rt_kprintf(" send successful \n messege : %s \n:",buffer); - - for( i = 0 ; i < STR_LEN ; i++) - rt_kprintf(" %x",(unsigned int)buffer[i]); - - rt_kprintf("\n"); - } - else - { - rt_kprintf("device s% send fail \n",I2C_BUS_NAME); - return; - } - - return; - -} -/* 导出到 msh 命令列表中 */ -MSH_CMD_EXPORT(i2c_io_sample, i2c io sample); diff --git a/bsp/essemi/es32f0334/drivers/bsp_driver_example/led_blink_sample.c b/bsp/essemi/es32f0334/drivers/bsp_driver_example/led_blink_sample.c deleted file mode 100644 index c073b5e5a7..0000000000 --- a/bsp/essemi/es32f0334/drivers/bsp_driver_example/led_blink_sample.c +++ /dev/null @@ -1,83 +0,0 @@ -/* - * Copyright (c) 2006-2018, RT-Thread Development Team - * - * SPDX-License-Identifier: Apache-2.0 - * - * Change Logs: - * Date Author Notes - * 2018-09-25 misonyo first edition. - */ -/* - * 程序清单：这是一个通过PIN脚控制LED亮灭的使用例程 - * 例程导出了 led_sample 命令到控制终端 - * 命令调用格式：led_sample - * 命令解释：命令第二个参数是要使用的PIN脚编号，为空则使用例程默认的引脚编号。 - * 程序功能：程序创建一个led线程，线程每隔1000ms改变PIN脚状态，达到控制led灯 - * 亮灭的效果。 -*/ - -#include -#include -#include - -/* PIN脚编号，查看驱动文件drv_gpio.c确定 */ -#define LED_PIN_NUM 45 /*PA12*/ -static int pin_num; - -static void led_entry(void *parameter) -{ - int count = 0; - /* 设置PIN脚模式为输出 */ - rt_pin_mode(pin_num, PIN_MODE_OUTPUT); - - while (1) - { - count++; - rt_kprintf("thread run count : %d\r\n", count); - /* 拉低PIN脚 */ - rt_pin_write(pin_num, PIN_LOW); - rt_kprintf("led on!\r\n"); - /* 延时1000ms */ - rt_thread_mdelay(1000); - - /* 拉高PIN脚 */ - rt_pin_write(pin_num, PIN_HIGH); - rt_kprintf("led off!\r\n"); - rt_thread_mdelay(1000); - } -} - -static int led_sample(int argc, char *argv[]) -{ - rt_thread_t tid; - rt_err_t ret = RT_EOK; - - /* 判断命令行参数是否给定了PIN脚编号 */ - if (argc == 2) - { - pin_num = atoi(argv[1]); - } - else - { - pin_num = LED_PIN_NUM; - } - - tid = rt_thread_create("led", - led_entry, - RT_NULL, - 512, - RT_THREAD_PRIORITY_MAX / 3, - 20); - if (tid != RT_NULL) - { - rt_thread_startup(tid); - } - else - { - ret = RT_ERROR; - } - - return ret; -} -/* 导出到 msh 命令列表中 */ -MSH_CMD_EXPORT(led_sample, led sample); diff --git a/bsp/essemi/es32f0334/drivers/bsp_driver_example/pin_beep_sample.c b/bsp/essemi/es32f0334/drivers/bsp_driver_example/pin_beep_sample.c deleted file mode 100644 index 911a0c800e..0000000000 --- a/bsp/essemi/es32f0334/drivers/bsp_driver_example/pin_beep_sample.c +++ /dev/null @@ -1,67 +0,0 @@ -/* - * Copyright (c) 2006-2018, RT-Thread Development Team - * - * SPDX-License-Identifier: Apache-2.0 - * - * Change Logs: - * Date Author Notes - * 2018-08-15 misonyo first implementation. - */ -/* - * 程序清单：这是一个 PIN 设备使用例程 - * 例程导出了 pin_beep_sample 命令到控制终端 - * 命令调用格式：pin_beep_sample - * 程序功能：通过按键控制蜂鸣器对应引脚的电平状态控制蜂鸣器 -*/ - -#include -#include - -/* 引脚编号，通过查看驱动文件drv_gpio.c确定 */ -#ifndef BEEP_PIN_NUM - #define BEEP_PIN_NUM 45 /* PA12 */ -#endif -#ifndef KEY0_PIN_NUM - #define KEY0_PIN_NUM 18 /* PF0 */ -#endif -#ifndef KEY1_PIN_NUM - #define KEY1_PIN_NUM 19 /* PF1 */ -#endif - -void beep_on(void *args) -{ - rt_kprintf("turn on beep!\n"); - - rt_pin_write(BEEP_PIN_NUM, PIN_HIGH); -} - -void beep_off(void *args) -{ - rt_kprintf("turn off beep!\n"); - - rt_pin_write(BEEP_PIN_NUM, PIN_LOW); -} - -static void pin_beep_sample(void) -{ - /* 蜂鸣器引脚为输出模式 */ - rt_pin_mode(BEEP_PIN_NUM, PIN_MODE_OUTPUT); - /* 默认低电平 */ - rt_pin_write(BEEP_PIN_NUM, PIN_LOW); - - /* 按键0引脚为输入模式 */ - rt_pin_mode(KEY0_PIN_NUM, PIN_MODE_INPUT_PULLUP); - /* 绑定中断，下降沿模式，回调函数名为beep_on */ - rt_pin_attach_irq(KEY0_PIN_NUM, PIN_IRQ_MODE_FALLING, beep_on, RT_NULL); - /* 使能中断 */ - rt_pin_irq_enable(KEY0_PIN_NUM, PIN_IRQ_ENABLE); - - /* 按键1引脚为输入模式 */ - rt_pin_mode(KEY1_PIN_NUM, PIN_MODE_INPUT_PULLUP); - /* 绑定中断，下降沿模式，回调函数名为beep_off */ - rt_pin_attach_irq(KEY1_PIN_NUM, PIN_IRQ_MODE_FALLING, beep_off, RT_NULL); - /* 使能中断 */ - rt_pin_irq_enable(KEY1_PIN_NUM, PIN_IRQ_ENABLE); -} -/* 导出到 msh 命令列表中 */ -MSH_CMD_EXPORT(pin_beep_sample, pin beep sample); diff --git a/bsp/essemi/es32f0334/drivers/bsp_driver_example/pm_sample.c b/bsp/essemi/es32f0334/drivers/bsp_driver_example/pm_sample.c deleted file mode 100644 index 08258b1650..0000000000 --- a/bsp/essemi/es32f0334/drivers/bsp_driver_example/pm_sample.c +++ /dev/null @@ -1,182 +0,0 @@ -/* - * Copyright (C) 2018 Shanghai Eastsoft Microelectronics Co., Ltd. - * - * SPDX-License-Identifier: Apache-2.0 - * - * Change Logs: - * Date Author Notes - * 2020-12-15 liuhy first implementation. - */ -/* - * 程序清单：这是一个 pm睡眠唤醒的使用例程 - * 例程导出了 pm_sample 命令到控制终端 - * 命令调用格式：pm_sample - * 命令解释：进入不同的睡眠模式，然后用按键唤醒 - * 程序功能：通过串口输出字符串，告知进入睡眠和唤醒睡眠的情况。 -*/ - -#include -#include - -#define PM_NAME "pm" /* 设备名称 */ -#define WAKE_UP_PIN 18 /* 唤醒源 */ -#define SLEEP_TIMES 12 /* 进入睡眠次数，轮流进入不同的睡眠模式，包括无睡眠模式 */ - -struct pm_callback_t -{ - volatile int in_fun_times; /*进入函数的次数*/ - volatile char flag; /*标志*/ - volatile int mode; /*需要打印的模式*/ -}; - -volatile struct pm_callback_t g_pm_data; - -/*进入睡眠前，睡眠唤醒后，都会进入。*/ -/*函数打印睡眠相关的信息*/ -void sleep_in_out_callback(rt_uint8_t event, rt_uint8_t mode, void *data) -{ - /*没有标志，不处理*/ - if(!(g_pm_data.flag)) - { - return; - } - - /*标志不正常，清空标志*/ - if((g_pm_data.flag) > 2) - { - (g_pm_data.flag) = 0; - return; - } - - /*模式不匹配*/ - if(g_pm_data.mode != mode ) - { - return; - } - - /*进入的事件*/ - switch(event) - { - /*进入睡眠前*/ - case RT_PM_ENTER_SLEEP: g_pm_data.flag = 1; - rt_kprintf("\n\r##%d : ENTER ",g_pm_data.in_fun_times); - g_pm_data.in_fun_times++; /*进入睡眠次数+1*/ - break; - /*睡眠唤醒后*/ - case RT_PM_EXIT_SLEEP: g_pm_data.flag = 0; /*睡眠唤醒后*/ - rt_kprintf("\n\rEXIT\n\r"); - rt_pm_release(mode); /*释放休眠模式*/ - return; - - default: break; - - }; - - /*当前的睡眠模式*/ - switch(mode) - { - case PM_SLEEP_MODE_NONE: rt_kprintf("PM_SLEEP_MODE_NONE\n\r"); - break; - case PM_SLEEP_MODE_IDLE: rt_kprintf("PM_SLEEP_MODE_IDLE\n\r"); - break; - case PM_SLEEP_MODE_LIGHT: rt_kprintf("PM_SLEEP_MODE_LIGHT\n\r"); - break; - case PM_SLEEP_MODE_DEEP: rt_kprintf("PM_SLEEP_MODE_DEEP\n\r"); - break; - case PM_SLEEP_MODE_STANDBY: rt_kprintf("PM_SLEEP_MODE_STANDBY\n\r"); - break; - case PM_SLEEP_MODE_SHUTDOWN: rt_kprintf("PM_SLEEP_MODE_SHUTDOWN\n\r"); - break; - case PM_SLEEP_MODE_MAX: rt_kprintf("PM_SLEEP_MODE_MAX\n\r"); - break; - default: break; - } - -} - -/* pm测试函数 */ -static void pm_test(void *parameter) -{ - int in_mode[7],i = 0; - - g_pm_data.in_fun_times = 0; - g_pm_data.flag = 0; - - in_mode[0] = PM_SLEEP_MODE_NONE; - in_mode[1] = PM_SLEEP_MODE_IDLE; - in_mode[2] = PM_SLEEP_MODE_LIGHT; - in_mode[3] = PM_SLEEP_MODE_DEEP; - in_mode[4] = PM_SLEEP_MODE_STANDBY; - in_mode[5] = PM_SLEEP_MODE_SHUTDOWN; - in_mode[6] = PM_SLEEP_MODE_MAX; - - /*设置回调函数和私有数据*/ - rt_pm_notify_set(sleep_in_out_callback,RT_NULL); - - while(i < SLEEP_TIMES) - { - - g_pm_data.mode = in_mode[i%6]; - - /*无休眠模式，不赋予标志*/ - if(g_pm_data.mode != PM_SLEEP_MODE_NONE) - { - g_pm_data.flag = 2; - - } - - /*请求选择的休眠模式*/ - rt_pm_request(in_mode[i%6]); - - rt_thread_mdelay(500); - - /*无休眠模式，不需要额外的等待*/ - while(( g_pm_data.flag != 0 )&&(g_pm_data.mode != PM_SLEEP_MODE_NONE)) - { - rt_thread_mdelay(500); - } - - /*释放选择的休眠模式*/ - rt_pm_release(in_mode[i%6]); - - i++; - - } - /*清除回调函数和私有数据*/ - rt_pm_notify_set(RT_NULL,RT_NULL); - rt_kprintf("thread pm_test close\n\r"); -} - -/*按键唤醒的回调函数*/ -void wake_by_pin(void *args) -{ - -} - -static int pm_sample(int argc, char *argv[]) -{ - rt_thread_t thread; - - /* 按键引脚为输入模式 */ - rt_pin_mode(WAKE_UP_PIN, PIN_MODE_INPUT_PULLUP); - - /* 绑定中断，下降沿模式，回调函数名为wake_by_pin */ - rt_pin_attach_irq(WAKE_UP_PIN, PIN_IRQ_MODE_RISING, wake_by_pin, RT_NULL); - /* 使能中断 */ - rt_pin_irq_enable(WAKE_UP_PIN, PIN_IRQ_ENABLE); - - thread = rt_thread_create("pm_test", pm_test, RT_NULL, 1024, 25, 10); - - if (thread != RT_NULL) - { - rt_thread_startup(thread); - } - else - { - rt_kprintf("create pm_test thread failed!\n\r"); - } - - return RT_EOK; -} -/* 导出到 msh 命令列表中 */ -MSH_CMD_EXPORT(pm_sample, pm sample); diff --git a/bsp/essemi/es32f0334/drivers/bsp_driver_example/pwm_led_sample.c b/bsp/essemi/es32f0334/drivers/bsp_driver_example/pwm_led_sample.c deleted file mode 100644 index 1ac2361445..0000000000 --- a/bsp/essemi/es32f0334/drivers/bsp_driver_example/pwm_led_sample.c +++ /dev/null @@ -1,72 +0,0 @@ -/* - * Copyright (c) 2006-2018, RT-Thread Development Team - * - * SPDX-License-Identifier: Apache-2.0 - * - * Change Logs: - * Date Author Notes - * 2018-11-25 misonyo first implementation. - */ -/* - * 程序清单：这是一个 PWM 设备使用例程 - * 例程导出了 pwm_led_sample 命令到控制终端 - * 命令调用格式：pwm_led_sample - * 程序功能：通过 PWM 设备控制 LED 灯的亮度，可以看到LED不停的由暗变到亮，然后又从亮变到暗。 -*/ - -#include -#include - -#define LED_PIN_NUM 45 /* PA12 LED PIN脚编号，查看驱动文件drv_gpio.c确定 */ -#define PWM_DEV_NAME "pwm0" /* PWM设备名称 */ -#define PWM_DEV_CHANNEL 2 /* PA9 PWM通道 */ - -struct rt_device_pwm *pwm_dev; /* PWM设备句柄 */ - -static int pwm_led_sample(int argc, char *argv[]) -{ - rt_uint32_t period, pulse, dir; - - period = 500000; /* 周期为0.5ms，单位为纳秒ns */ - dir = 1; /* PWM脉冲宽度值的增减方向 */ - pulse = 0; /* PWM脉冲宽度值，单位为纳秒ns */ - - /* 查找设备 */ - pwm_dev = (struct rt_device_pwm *)rt_device_find(PWM_DEV_NAME); - if (pwm_dev == RT_NULL) - { - rt_kprintf("pwm sample run failed! can't find %s device!\n", PWM_DEV_NAME); - return RT_ERROR; - } - - /* 设置PWM周期和脉冲宽度默认值 */ - rt_pwm_set(pwm_dev, PWM_DEV_CHANNEL, period, pulse); - /* 使能设备 */ - rt_pwm_enable(pwm_dev, PWM_DEV_CHANNEL); - - while (1) - { - rt_thread_mdelay(50); - if (dir) - { - pulse += 5000; /* 从0值开始每次增加5000ns */ - } - else - { - pulse -= 5000; /* 从最大值开始每次减少5000ns */ - } - if (pulse >= period) - { - dir = 0; - } - if (0 == pulse) - { - dir = 1; - } - - /* 设置PWM周期和脉冲宽度 */ - rt_pwm_set(pwm_dev, PWM_DEV_CHANNEL, period, pulse); - } -} -/* 导出到 msh 命令列表中 */ -MSH_CMD_EXPORT(pwm_led_sample, pwm sample); diff --git a/bsp/essemi/es32f0334/drivers/bsp_driver_example/rtc_sample.c b/bsp/essemi/es32f0334/drivers/bsp_driver_example/rtc_sample.c deleted file mode 100644 index 711a3a0ebb..0000000000 --- a/bsp/essemi/es32f0334/drivers/bsp_driver_example/rtc_sample.c +++ /dev/null @@ -1,51 +0,0 @@ -/* - * Copyright (c) 2006-2018, RT-Thread Development Team - * - * SPDX-License-Identifier: Apache-2.0 - * - * Change Logs: - * Date Author Notes - * 2018-11-30 misonyo first implementation. - */ -/* - * 程序清单：这是一个 RTC 设备使用例程 - * 例程导出了 rtc_sample 命令到控制终端 - * 命令调用格式：rtc_sample - * 程序功能：设置RTC设备的日期和时间，延时一段时间后获取当前时间并打印显示。 -*/ - -#include -#include - -static int rtc_sample(int argc, char *argv[]) -{ - rt_err_t ret = RT_EOK; - time_t now; - - /* 设置日期 */ - ret = set_date(2018, 12, 3); - if (ret != RT_EOK) - { - rt_kprintf("set RTC date failed\n"); - return ret; - } - - /* 设置时间 */ - ret = set_time(11, 15, 50); - if (ret != RT_EOK) - { - rt_kprintf("set RTC time failed\n"); - return ret; - } - - /* 延时3秒 */ - rt_thread_mdelay(3000); - - /* 获取时间 */ - now = time(RT_NULL); - rt_kprintf("%s\n", ctime(&now)); - - return ret; -} -/* 导出到 msh 命令列表中 */ -MSH_CMD_EXPORT(rtc_sample, rtc sample); diff --git a/bsp/essemi/es32f0334/drivers/bsp_driver_example/spi_sample.c b/bsp/essemi/es32f0334/drivers/bsp_driver_example/spi_sample.c deleted file mode 100644 index 994888cdb0..0000000000 --- a/bsp/essemi/es32f0334/drivers/bsp_driver_example/spi_sample.c +++ /dev/null @@ -1,152 +0,0 @@ -/* - * Copyright (C) 2018 Shanghai Eastsoft Microelectronics Co., Ltd. - * - * SPDX-License-Identifier: Apache-2.0 - * - * Change Logs: - * Date Author Notes - * 2020-12-15 liuhy first implementation. - */ -/* - * 程序清单：这是一个 SPI 设备使用例程 - * 例程导出了 spi_io_sample 命令到控制终端 - * 命令调用格式：spi_io_sample - * 程序功能：通过SPI设备先读取数据，然后每个字符加1后输出。 -*/ - -#include -#include - -#define SPI_DEVICE_NAME "spi00" -#define BUF_LEN 16 - -static void spi_io_sample(int argc, char *argv[]) -{ - struct rt_spi_device * spi_dev; /* spi设备的句柄 */ - struct rt_spi_configuration spi_config; - rt_uint8_t i,buffer[BUF_LEN] = { 0U }; - rt_err_t s_stat; - rt_err_t result; - - /* 查找 spi设备 获取spi设备句柄 */ - spi_dev = (struct rt_spi_device *)rt_device_find(SPI_DEVICE_NAME); - - if (spi_dev == RT_NULL) - { - rt_kprintf("spi sample run failed! can't find %s device!\n", SPI_DEVICE_NAME); - return; - } - - - /* 清空配置结构体 */ - rt_memset(&spi_config,0,sizeof(struct rt_spi_configuration)); - - spi_config.mode &= ~RT_SPI_SLAVE; /* 主机模式 */ - spi_config.mode &= ~RT_SPI_3WIRE; /* 4线，双向传输 */ - spi_config.mode |= RT_SPI_CPHA; /* 第二边沿采样 */ - spi_config.mode |= RT_SPI_CPOL; /* 空闲高电平 */ - spi_config.mode |= RT_SPI_NO_CS; /* 禁用软件从机选择管理 */ - spi_config.mode |= RT_SPI_MSB; /* 高位在前 */ - - spi_config.data_width = 8; /* 数据长度：8 */ - - spi_config.max_hz = 2000000; /* 最快时钟频率 */ - - /* 配置SPI设备 */ - s_stat = rt_spi_configure(spi_dev,&spi_config); - - if(s_stat != RT_EOK) - { - rt_kprintf(" spi config fail !\n "); - return; - } - - - /* 获取总线 ，防止总线被多个线程同时使用 */ - result = rt_spi_take_bus(spi_dev); - - if (result != RT_EOK) - { - rt_kprintf(" %s take spi bus failed! \n", SPI_DEVICE_NAME); - return; - } - - /* 选中片选 */ - result = rt_spi_take(spi_dev); - - if (result != RT_EOK) - { - rt_kprintf(" %s take spi cs failed! \n", SPI_DEVICE_NAME); - return; - } - - - /*接收一次数据*/ - result = rt_spi_recv(spi_dev,buffer,BUF_LEN); - - if(result != BUF_LEN) - { - rt_kprintf("receive fail. \n buffer is : %s \n:",buffer); - - for( i = 0 ; i < BUF_LEN ; i++) - rt_kprintf(" %x",(unsigned int)buffer[i]); - - rt_kprintf("\n"); - - return; - } - - rt_kprintf("receive successful. \n buffer is : %s \n:",buffer); - - for( i = 0 ; i < BUF_LEN ; i++) - rt_kprintf(" %x",(unsigned int)buffer[i]); - - rt_kprintf("\n"); - - /* 将接收到的数据加1 */ - for( i = 0 ; i < BUF_LEN ; i++) - buffer[i]++; - - /*发送数据*/ - result = rt_spi_send(spi_dev,buffer,BUF_LEN); - - if(result != BUF_LEN) - { - rt_kprintf("send fail. \n buffer is : %s \n:",buffer); - - for( i = 0 ; i < BUF_LEN ; i++) - rt_kprintf(" %x",(unsigned int)buffer[i]); - - rt_kprintf("\n"); - - return; - } - - rt_kprintf("send successful. \n buffer is : %s \n:",buffer); - - for( i = 0 ; i < BUF_LEN ; i++) - rt_kprintf(" %x",(unsigned int)buffer[i]); - - rt_kprintf("\n"); - - /* 释放片选 */ - result = rt_spi_release(spi_dev); - - if (result != RT_EOK) - { - rt_kprintf(" %s release spi cs failed! \n", SPI_DEVICE_NAME); - return; - } - - /* 释放总线 */ - result = rt_spi_release_bus(spi_dev); - - if (result != RT_EOK) - { - rt_kprintf(" %s release spi bus failed! \n", SPI_DEVICE_NAME); - return; - } - -} -/* 导出到 msh 命令列表中 */ -MSH_CMD_EXPORT(spi_io_sample, spi sample); diff --git a/bsp/essemi/es32f0334/drivers/bsp_driver_example/uart_sample.c b/bsp/essemi/es32f0334/drivers/bsp_driver_example/uart_sample.c deleted file mode 100644 index cbfd6bccef..0000000000 --- a/bsp/essemi/es32f0334/drivers/bsp_driver_example/uart_sample.c +++ /dev/null @@ -1,100 +0,0 @@ -/* - * Copyright (c) 2006-2018, RT-Thread Development Team - * - * SPDX-License-Identifier: Apache-2.0 - * - * Change Logs: - * Date Author Notes - * 2018-08-15 misonyo first implementation. - */ -/* - * 程序清单：这是一个 串口 设备使用例程 - * 例程导出了 uart_sample 命令到控制终端 - * 命令调用格式：uart_sample uart2 - * 命令解释：命令第二个参数是要使用的串口设备名称，为空则使用默认的串口设备 - * 程序功能：通过串口输出字符串"hello RT-Thread!"，然后错位输出输入的字符 -*/ - -#include - -#define SAMPLE_UART_NAME "uart1" /* 串口设备名称 */ - -/* 用于接收消息的信号量 */ -static struct rt_semaphore rx_sem; -static rt_device_t serial; - -/* 接收数据回调函数 */ -static rt_err_t uart_input(rt_device_t dev, rt_size_t size) -{ - /* 串口接收到数据后产生中断，调用此回调函数，然后发送接收信号量 */ - rt_sem_release(&rx_sem); - - return RT_EOK; -} - -static void serial_thread_entry(void *parameter) -{ - char ch; - - while (1) - { - /* 从串口读取一个字节的数据，没有读取到则等待接收信号量 */ - while (rt_device_read(serial, -1, &ch, 1) != 1) - { - /* 阻塞等待接收信号量，等到信号量后再次读取数据 */ - rt_sem_take(&rx_sem, RT_WAITING_FOREVER); - } - /* 读取到的数据通过串口错位输出 */ - ch = ch + 1; - rt_device_write(serial, 0, &ch, 1); - } -} - -static int uart_sample(int argc, char *argv[]) -{ - rt_err_t ret = RT_EOK; - char uart_name[RT_NAME_MAX]; - char str[] = "hello RT-Thread!\r\n"; - - if (argc == 2) - { - rt_strncpy(uart_name, argv[1], RT_NAME_MAX); - } - else - { - rt_strncpy(uart_name, SAMPLE_UART_NAME, RT_NAME_MAX); - } - - /* 查找串口设备 */ - serial = rt_device_find(uart_name); - if (!serial) - { - rt_kprintf("find %s failed!\n", uart_name); - return RT_ERROR; - } - - /* 初始化信号量 */ - rt_sem_init(&rx_sem, "rx_sem", 0, RT_IPC_FLAG_FIFO); - /* 以中断接收及轮询发送方式打开串口设备 */ - rt_device_open(serial, RT_DEVICE_FLAG_INT_RX); - /* 设置接收回调函数 */ - rt_device_set_rx_indicate(serial, uart_input); - /* 发送字符串 */ - rt_device_write(serial, 0, str, (sizeof(str) - 1)); - - /* 创建 serial 线程 */ - rt_thread_t thread = rt_thread_create("serial", serial_thread_entry, RT_NULL, 1024, 25, 10); - /* 创建成功则启动线程 */ - if (thread != RT_NULL) - { - rt_thread_startup(thread); - } - else - { - ret = RT_ERROR; - } - - return ret; -} -/* 导出到 msh 命令列表中 */ -MSH_CMD_EXPORT(uart_sample, uart device sample); diff --git a/bsp/essemi/es32f0334/drivers/drv_adc.c b/bsp/essemi/es32f0334/drivers/drv_adc.c deleted file mode 100644 index d9f1e5b899..0000000000 --- a/bsp/essemi/es32f0334/drivers/drv_adc.c +++ /dev/null @@ -1,193 +0,0 @@ -/* - * Copyright (C) 2018 Shanghai Eastsoft Microelectronics Co., Ltd. - * - * SPDX-License-Identifier: Apache-2.0 - * - * Change Logs: - * Date Author Notes - * 2019-04-08 wangyq the first version - * 2019-11-01 wangyq update libraries - */ - -#include -#include -#include -#include "board.h" -#include "drv_adc.h" -#include -#include - -#ifdef RT_USING_ADC - -/* define adc instance */ -static struct rt_adc_device _device_adc0; - -/* enable or disable adc */ -static rt_err_t es32f0_adc_enabled(struct rt_adc_device *device, rt_uint32_t channel, rt_bool_t enabled) -{ - adc_handle_t *_hadc = (adc_handle_t *)device->parent.user_data; - - RT_ASSERT(device != RT_NULL); - - if (enabled) - { - ADC_ENABLE(_hadc); - } - else - { - ADC_DISABLE(_hadc); - } - - return RT_EOK; -} - -static adc_channel_t es32f0_adc_get_channel(rt_uint32_t channel) -{ - adc_channel_t es32f0_channel; - gpio_init_t gpio_initstruct; - - /* Initialize ADC pin */ - gpio_initstruct.mode = GPIO_MODE_INPUT; - gpio_initstruct.pupd = GPIO_FLOATING; - gpio_initstruct.odrv = GPIO_OUT_DRIVE_NORMAL; - gpio_initstruct.flt = GPIO_FILTER_DISABLE; - gpio_initstruct.type = GPIO_TYPE_CMOS; - gpio_initstruct.func = GPIO_FUNC_0; - - /* select gpio pin as adc function */ - switch (channel) - { - case 0: - es32f0_channel = ADC_CHANNEL_0; - ald_gpio_init(GPIOC, GPIO_PIN_0, &gpio_initstruct); - break; - case 1: - es32f0_channel = ADC_CHANNEL_1; - ald_gpio_init(GPIOC, GPIO_PIN_1, &gpio_initstruct); - break; - case 2: - es32f0_channel = ADC_CHANNEL_2; - ald_gpio_init(GPIOC, GPIO_PIN_2, &gpio_initstruct); - break; - case 3: - es32f0_channel = ADC_CHANNEL_3; - ald_gpio_init(GPIOC, GPIO_PIN_3, &gpio_initstruct); - break; - case 4: - es32f0_channel = ADC_CHANNEL_4; - ald_gpio_init(GPIOA, GPIO_PIN_0, &gpio_initstruct); - break; - case 5: - es32f0_channel = ADC_CHANNEL_5; - ald_gpio_init(GPIOA, GPIO_PIN_1, &gpio_initstruct); - break; - case 6: - es32f0_channel = ADC_CHANNEL_6; - ald_gpio_init(GPIOA, GPIO_PIN_2, &gpio_initstruct); - break; - case 7: - es32f0_channel = ADC_CHANNEL_7; - ald_gpio_init(GPIOA, GPIO_PIN_3, &gpio_initstruct); - break; - case 8: - es32f0_channel = ADC_CHANNEL_8; - ald_gpio_init(GPIOA, GPIO_PIN_4, &gpio_initstruct); - break; - case 9: - es32f0_channel = ADC_CHANNEL_9; - ald_gpio_init(GPIOA, GPIO_PIN_5, &gpio_initstruct); - break; - case 10: - es32f0_channel = ADC_CHANNEL_10; - ald_gpio_init(GPIOA, GPIO_PIN_6, &gpio_initstruct); - break; - case 11: - es32f0_channel = ADC_CHANNEL_11; - ald_gpio_init(GPIOA, GPIO_PIN_7, &gpio_initstruct); - break; - case 12: - es32f0_channel = ADC_CHANNEL_12; - ald_gpio_init(GPIOC, GPIO_PIN_4, &gpio_initstruct); - break; - case 13: - es32f0_channel = ADC_CHANNEL_13; - ald_gpio_init(GPIOC, GPIO_PIN_5, &gpio_initstruct); - break; - case 14: - es32f0_channel = ADC_CHANNEL_14; - ald_gpio_init(GPIOB, GPIO_PIN_0, &gpio_initstruct); - break; - case 15: - es32f0_channel = ADC_CHANNEL_15; - ald_gpio_init(GPIOB, GPIO_PIN_1, &gpio_initstruct); - break; - case 16: - es32f0_channel = ADC_CHANNEL_16; - break; - case 17: - es32f0_channel = ADC_CHANNEL_17; - break; - case 18: - es32f0_channel = ADC_CHANNEL_18; - break; - default: - break; - } - - return es32f0_channel; -} - -static rt_err_t es32f0_get_adc_value(struct rt_adc_device *device, rt_uint32_t channel, rt_uint32_t *value) -{ - adc_handle_t *_hadc = (adc_handle_t *)device->parent.user_data; - adc_nch_conf_t nm_config; - - RT_ASSERT(device != RT_NULL); - RT_ASSERT(value != RT_NULL); - - /* config adc channel */ - nm_config.ch = es32f0_adc_get_channel(channel); - nm_config.idx = ADC_NCH_IDX_1; - nm_config.samp = ADC_SAMPLETIME_4; - ald_adc_normal_channel_config(_hadc, &nm_config); - - ald_adc_normal_start(_hadc); - - if (ald_adc_normal_poll_for_conversion(_hadc, 5000) == OK) - *value = ald_adc_normal_get_value(_hadc); - - return RT_EOK; -} - -static const struct rt_adc_ops es32f0_adc_ops = -{ - es32f0_adc_enabled, - es32f0_get_adc_value, -}; - -int rt_hw_adc_init(void) -{ - int result = RT_EOK; - static adc_handle_t _h_adc0; - - /* adc function initialization */ - _h_adc0.perh = ADC0; - _h_adc0.init.align = ADC_DATAALIGN_RIGHT; - _h_adc0.init.scan = DISABLE; - _h_adc0.init.cont = DISABLE; - _h_adc0.init.disc = ADC_ALL_DISABLE; - _h_adc0.init.disc_nr = ADC_DISC_NR_1; - _h_adc0.init.data_bit = ADC_CONV_BIT_12; - _h_adc0.init.div = ADC_CKDIV_128; - _h_adc0.init.nche_sel = ADC_NCHESEL_MODE_ALL; - _h_adc0.init.n_ref = ADC_NEG_REF_VSS; - _h_adc0.init.p_ref = ADC_POS_REF_VDD; - ald_adc_init(&_h_adc0); - - rt_hw_adc_register(&_device_adc0, "adc0", &es32f0_adc_ops, &_h_adc0); - - return result; -} -INIT_BOARD_EXPORT(rt_hw_adc_init); - -#endif diff --git a/bsp/essemi/es32f0334/drivers/drv_adc.h b/bsp/essemi/es32f0334/drivers/drv_adc.h deleted file mode 100644 index eaddd67407..0000000000 --- a/bsp/essemi/es32f0334/drivers/drv_adc.h +++ /dev/null @@ -1,16 +0,0 @@ -/* - * Copyright (C) 2018 Shanghai Eastsoft Microelectronics Co., Ltd. - * - * SPDX-License-Identifier: Apache-2.0 - * - * Change Logs: - * Date Author Notes - * 2019-04-03 wangyq the first version - */ - -#ifndef DRV_ADC_H__ -#define DRV_ADC_H__ - -int rt_hw_adc_init(void); - -#endif diff --git a/bsp/essemi/es32f0334/drivers/drv_gpio.c b/bsp/essemi/es32f0334/drivers/drv_gpio.c deleted file mode 100644 index d816af5fd3..0000000000 --- a/bsp/essemi/es32f0334/drivers/drv_gpio.c +++ /dev/null @@ -1,491 +0,0 @@ -/* - * Copyright (C) 2018 Shanghai Eastsoft Microelectronics Co., Ltd. - * - * SPDX-License-Identifier: Apache-2.0 - * - * Change Logs: - * Date Author Notes - * 2019-03-01 wangyq the first version - * 2019-11-01 wangyq update libraries - */ - -#include -#include -#include "board.h" -#include "drv_gpio.h" -#include -#include - -#ifdef RT_USING_PIN - -#define __ES32F0_PIN(index, gpio, gpio_index) {index, GPIO##gpio, GPIO_PIN_##gpio_index} -#define __ES32F0_PIN_DEFAULT {-1, 0, 0} - -/* ES32F0 GPIO driver */ -struct pin_index -{ - int index; - GPIO_TypeDef *gpio; - uint32_t pin; -}; - -static const struct pin_index pins[] = -{ - __ES32F0_PIN_DEFAULT, - __ES32F0_PIN_DEFAULT, - __ES32F0_PIN(2, C, 13), - __ES32F0_PIN(3, C, 14), - __ES32F0_PIN(4, C, 15), - __ES32F0_PIN(5, H, 0), - __ES32F0_PIN(6, H, 1), - __ES32F0_PIN_DEFAULT, - __ES32F0_PIN(8, C, 0), - __ES32F0_PIN(9, C, 1), - __ES32F0_PIN(10, C, 2), - __ES32F0_PIN(11, C, 3), - __ES32F0_PIN(12, H, 3), - __ES32F0_PIN(13, H, 4), - __ES32F0_PIN(14, A, 0), - __ES32F0_PIN(15, A, 1), - __ES32F0_PIN(16, A, 2), - __ES32F0_PIN(17, A, 3), - __ES32F0_PIN(18, F, 0), - __ES32F0_PIN(19, F, 1), - __ES32F0_PIN(20, A, 4), - __ES32F0_PIN(21, A, 5), - __ES32F0_PIN(22, A, 6), - __ES32F0_PIN(23, A, 7), - __ES32F0_PIN(24, C, 4), - __ES32F0_PIN(25, C, 5), - __ES32F0_PIN(26, B, 0), - __ES32F0_PIN(27, B, 1), - __ES32F0_PIN(28, B, 2), - __ES32F0_PIN(29, B, 10), - __ES32F0_PIN(30, B, 11), - __ES32F0_PIN_DEFAULT, - __ES32F0_PIN_DEFAULT, - __ES32F0_PIN(33, B, 12), - __ES32F0_PIN(34, B, 13), - __ES32F0_PIN(35, B, 14), - __ES32F0_PIN(36, B, 15), - __ES32F0_PIN(37, C, 6), - __ES32F0_PIN(38, C, 7), - __ES32F0_PIN(39, C, 8), - __ES32F0_PIN(40, C, 9), - __ES32F0_PIN(41, A, 8), - __ES32F0_PIN(42, A, 9), - __ES32F0_PIN(43, A, 10), - __ES32F0_PIN(44, A, 11), - __ES32F0_PIN(45, A, 12), - __ES32F0_PIN(46, A, 13), - __ES32F0_PIN_DEFAULT, - __ES32F0_PIN_DEFAULT, - __ES32F0_PIN(49, A, 14), - __ES32F0_PIN(50, A, 15), - __ES32F0_PIN(51, C, 10), - __ES32F0_PIN(52, C, 11), - __ES32F0_PIN(53, C, 12), - __ES32F0_PIN(54, D, 2), - __ES32F0_PIN(55, B, 3), - __ES32F0_PIN(56, B, 4), - __ES32F0_PIN(57, B, 5), - __ES32F0_PIN(58, B, 6), - __ES32F0_PIN(59, B, 7), - __ES32F0_PIN(60, H, 2), - __ES32F0_PIN(61, B, 8), - __ES32F0_PIN(62, E, 1), - __ES32F0_PIN_DEFAULT, - __ES32F0_PIN_DEFAULT, -}; - -struct pin_irq_map -{ - rt_uint16_t pinbit; - IRQn_Type irqno; -}; -static const struct pin_irq_map pin_irq_map[] = -{ - {GPIO_PIN_0, EXTI0_3_IRQn}, - {GPIO_PIN_1, EXTI0_3_IRQn}, - {GPIO_PIN_2, EXTI0_3_IRQn}, - {GPIO_PIN_3, EXTI0_3_IRQn}, - {GPIO_PIN_4, EXTI4_7_IRQn}, - {GPIO_PIN_5, EXTI4_7_IRQn}, - {GPIO_PIN_6, EXTI4_7_IRQn}, - {GPIO_PIN_7, EXTI4_7_IRQn}, - {GPIO_PIN_8, EXTI8_11_IRQn}, - {GPIO_PIN_9, EXTI8_11_IRQn}, - {GPIO_PIN_10, EXTI8_11_IRQn}, - {GPIO_PIN_11, EXTI8_11_IRQn}, - {GPIO_PIN_12, EXTI12_15_IRQn}, - {GPIO_PIN_13, EXTI12_15_IRQn}, - {GPIO_PIN_14, EXTI12_15_IRQn}, - {GPIO_PIN_15, EXTI12_15_IRQn}, -}; - -struct rt_pin_irq_hdr pin_irq_hdr_tab[] = -{ - { -1, 0, RT_NULL, RT_NULL}, - { -1, 0, RT_NULL, RT_NULL}, - { -1, 0, RT_NULL, RT_NULL}, - { -1, 0, RT_NULL, RT_NULL}, - { -1, 0, RT_NULL, RT_NULL}, - { -1, 0, RT_NULL, RT_NULL}, - { -1, 0, RT_NULL, RT_NULL}, - { -1, 0, RT_NULL, RT_NULL}, - { -1, 0, RT_NULL, RT_NULL}, - { -1, 0, RT_NULL, RT_NULL}, - { -1, 0, RT_NULL, RT_NULL}, - { -1, 0, RT_NULL, RT_NULL}, - { -1, 0, RT_NULL, RT_NULL}, - { -1, 0, RT_NULL, RT_NULL}, - { -1, 0, RT_NULL, RT_NULL}, - { -1, 0, RT_NULL, RT_NULL}, -}; - -#define ITEM_NUM(items) sizeof(items) / sizeof(items[0]) -const struct pin_index *get_pin(uint8_t pin) -{ - const struct pin_index *index; - if (pin < ITEM_NUM(pins)) - { - index = &pins[pin]; - if (index->index == -1) - index = RT_NULL; - } - else - { - index = RT_NULL; - } - return index; -}; - -void es32f0_pin_write(rt_device_t dev, rt_base_t pin, rt_base_t value) -{ - const struct pin_index *index; - index = get_pin(pin); - if (index == RT_NULL) - { - return; - } - ald_gpio_write_pin(index->gpio, index->pin, value); -} - -int es32f0_pin_read(rt_device_t dev, rt_base_t pin) -{ - int value; - const struct pin_index *index; - value = PIN_LOW; - index = get_pin(pin); - if (index == RT_NULL) - { - return value; - } - value = ald_gpio_read_pin(index->gpio, index->pin); - return value; -} - -void es32f0_pin_mode(rt_device_t dev, rt_base_t pin, rt_base_t mode) -{ - const struct pin_index *index; - gpio_init_t gpio_initstruct; - index = get_pin(pin); - if (index == RT_NULL) - { - return; - } - - /* Configure GPIO_InitStructure */ - gpio_initstruct.mode = GPIO_MODE_OUTPUT; - gpio_initstruct.func = GPIO_FUNC_1; - gpio_initstruct.odrv = GPIO_OUT_DRIVE_NORMAL; - gpio_initstruct.type = GPIO_TYPE_CMOS; - gpio_initstruct.pupd = GPIO_FLOATING; - gpio_initstruct.odos = GPIO_PUSH_PULL; - - if (mode == PIN_MODE_OUTPUT) - { - /* output setting */ - gpio_initstruct.mode = GPIO_MODE_OUTPUT; - gpio_initstruct.pupd = GPIO_FLOATING; - } - else if (mode == PIN_MODE_INPUT) - { - /* input setting: not pull. */ - gpio_initstruct.mode = GPIO_MODE_INPUT; - gpio_initstruct.pupd = GPIO_FLOATING; - } - else if (mode == PIN_MODE_INPUT_PULLUP) - { - /* input setting: pull up. */ - gpio_initstruct.mode = GPIO_MODE_INPUT; - gpio_initstruct.pupd = GPIO_PUSH_UP; - } - else if (mode == PIN_MODE_INPUT_PULLDOWN) - { - /* input setting: pull down. */ - gpio_initstruct.mode = GPIO_MODE_INPUT; - gpio_initstruct.pupd = GPIO_PUSH_DOWN; - } - else if (mode == PIN_MODE_OUTPUT_OD) - { - /* output setting: od. */ - gpio_initstruct.mode = GPIO_MODE_OUTPUT; - gpio_initstruct.pupd = GPIO_FLOATING; - gpio_initstruct.odos = GPIO_OPEN_DRAIN; - } - ald_gpio_init(index->gpio, index->pin, &gpio_initstruct); -} - -rt_inline const struct pin_irq_map *get_pin_irq_map(rt_uint16_t gpio_pin) -{ - rt_int32_t mapindex = gpio_pin & 0x00FF; - if (mapindex < 0 || mapindex >= ITEM_NUM(pin_irq_map)) - { - return RT_NULL; - } - return &pin_irq_map[mapindex]; -}; - -rt_err_t es32f0_pin_attach_irq(struct rt_device *device, rt_int32_t pin, - rt_uint32_t mode, void (*hdr)(void *args), void *args) -{ - const struct pin_index *index; - rt_base_t level; - rt_int32_t irqindex; - index = get_pin(pin); - if (index == RT_NULL) - { - return RT_ENOSYS; - } - /* pin no. convert to dec no. */ - for (irqindex = 0; irqindex < 16; irqindex++) - { - if ((0x01 << irqindex) == index->pin) - { - break; - } - } - if (irqindex < 0 || irqindex >= ITEM_NUM(pin_irq_map)) - { - return RT_ENOSYS; - } - level = rt_hw_interrupt_disable(); - if (pin_irq_hdr_tab[irqindex].pin == pin && - pin_irq_hdr_tab[irqindex].hdr == hdr && - pin_irq_hdr_tab[irqindex].mode == mode && - pin_irq_hdr_tab[irqindex].args == args) - { - rt_hw_interrupt_enable(level); - return RT_EOK; - } - if (pin_irq_hdr_tab[irqindex].pin != -1) - { - rt_hw_interrupt_enable(level); - return RT_EBUSY; - } - pin_irq_hdr_tab[irqindex].pin = pin; - pin_irq_hdr_tab[irqindex].hdr = hdr; - pin_irq_hdr_tab[irqindex].mode = mode; - pin_irq_hdr_tab[irqindex].args = args; - rt_hw_interrupt_enable(level); - return RT_EOK; -} - -rt_err_t es32f0_pin_detach_irq(struct rt_device *device, rt_int32_t pin) -{ - const struct pin_index *index; - rt_base_t level; - rt_int32_t irqindex = -1; - index = get_pin(pin); - if (index == RT_NULL) - { - return RT_ENOSYS; - } - irqindex = index->pin & 0x00FF; - if (irqindex < 0 || irqindex >= ITEM_NUM(pin_irq_map)) - { - return RT_ENOSYS; - } - level = rt_hw_interrupt_disable(); - if (pin_irq_hdr_tab[irqindex].pin == -1) - { - rt_hw_interrupt_enable(level); - return RT_EOK; - } - pin_irq_hdr_tab[irqindex].pin = -1; - pin_irq_hdr_tab[irqindex].hdr = RT_NULL; - pin_irq_hdr_tab[irqindex].mode = 0; - pin_irq_hdr_tab[irqindex].args = RT_NULL; - rt_hw_interrupt_enable(level); - return RT_EOK; -} - -rt_err_t es32f0_pin_irq_enable(struct rt_device *device, rt_base_t pin, - rt_uint32_t enabled) -{ - const struct pin_index *index; - const struct pin_irq_map *irqmap; - rt_base_t level; - rt_int32_t irqindex = -1; - /* Configure GPIO_InitStructure & EXTI_InitStructure */ - gpio_init_t gpio_initstruct; - exti_init_t exti_initstruct; - exti_initstruct.filter = DISABLE; - exti_initstruct.cks = EXTI_FILTER_CLOCK_10K; - exti_initstruct.filter_time = 0x0; - - index = get_pin(pin); - if (index == RT_NULL) - { - return RT_ENOSYS; - } - if (enabled == PIN_IRQ_ENABLE) - { - /* pin no. convert to dec no. */ - for (irqindex = 0; irqindex < 16; irqindex++) - { - if ((0x01 << irqindex) == index->pin) - { - break; - } - } - if (irqindex < 0 || irqindex >= ITEM_NUM(pin_irq_map)) - { - return RT_ENOSYS; - } - level = rt_hw_interrupt_disable(); - if (pin_irq_hdr_tab[irqindex].pin == -1) - { - rt_hw_interrupt_enable(level); - return RT_ENOSYS; - } - irqmap = &pin_irq_map[irqindex]; - ald_gpio_exti_init(index->gpio, index->pin, &exti_initstruct); - /* Configure GPIO_InitStructure */ - gpio_initstruct.mode = GPIO_MODE_INPUT; - gpio_initstruct.func = GPIO_FUNC_1; - switch (pin_irq_hdr_tab[irqindex].mode) - { - case PIN_IRQ_MODE_RISING: - gpio_initstruct.pupd = GPIO_PUSH_DOWN; - ald_gpio_exti_interrupt_config(index->pin, EXTI_TRIGGER_RISING_EDGE, ENABLE); - break; - case PIN_IRQ_MODE_FALLING: - gpio_initstruct.pupd = GPIO_PUSH_UP; - ald_gpio_exti_interrupt_config(index->pin, EXTI_TRIGGER_TRAILING_EDGE, ENABLE); - break; - case PIN_IRQ_MODE_RISING_FALLING: - gpio_initstruct.pupd = GPIO_FLOATING; - ald_gpio_exti_interrupt_config(index->pin, EXTI_TRIGGER_BOTH_EDGE, ENABLE); - break; - } - ald_gpio_init(index->gpio, index->pin, &gpio_initstruct); - NVIC_EnableIRQ(irqmap->irqno); - rt_hw_interrupt_enable(level); - } - else if (enabled == PIN_IRQ_DISABLE) - { - irqmap = get_pin_irq_map(index->pin); - if (irqmap == RT_NULL) - { - return RT_ENOSYS; - } - NVIC_DisableIRQ(irqmap->irqno); - } - else - { - return RT_ENOSYS; - } - return RT_EOK; -} - -const static struct rt_pin_ops _es32f0_pin_ops = -{ - es32f0_pin_mode, - es32f0_pin_write, - es32f0_pin_read, - es32f0_pin_attach_irq, - es32f0_pin_detach_irq, - es32f0_pin_irq_enable, - RT_NULL, -}; - -int rt_hw_pin_init(void) -{ - int result; - ald_cmu_perh_clock_config(CMU_PERH_GPIO, ENABLE); - result = rt_device_pin_register("pin", &_es32f0_pin_ops, RT_NULL); - return result; -} -INIT_BOARD_EXPORT(rt_hw_pin_init); - -rt_inline void pin_irq_hdr(uint16_t GPIO_Pin) -{ - uint16_t irqno; - /* pin no. convert to dec no. */ - for (irqno = 0; irqno < 16; irqno++) - { - if ((0x01 << irqno) == GPIO_Pin) - { - break; - } - } - if (irqno == 16) - return; - if (pin_irq_hdr_tab[irqno].hdr) - { - pin_irq_hdr_tab[irqno].hdr(pin_irq_hdr_tab[irqno].args); - } -} - -void GPIO_EXTI_Callback(uint16_t GPIO_Pin) -{ - if (ald_gpio_exti_get_flag_status(GPIO_Pin) != RESET) - { - ald_gpio_exti_clear_flag_status(GPIO_Pin); - pin_irq_hdr(GPIO_Pin); - } -} - -void EXTI0_3_Handler(void) -{ - rt_interrupt_enter(); - GPIO_EXTI_Callback(GPIO_PIN_0); - GPIO_EXTI_Callback(GPIO_PIN_1); - GPIO_EXTI_Callback(GPIO_PIN_2); - GPIO_EXTI_Callback(GPIO_PIN_3); - rt_interrupt_leave(); -} - -void EXTI4_7_Handler(void) -{ - rt_interrupt_enter(); - GPIO_EXTI_Callback(GPIO_PIN_4); - GPIO_EXTI_Callback(GPIO_PIN_5); - GPIO_EXTI_Callback(GPIO_PIN_6); - GPIO_EXTI_Callback(GPIO_PIN_7); - rt_interrupt_leave(); -} - -void EXTI8_11_Handler(void) -{ - rt_interrupt_enter(); - GPIO_EXTI_Callback(GPIO_PIN_8); - GPIO_EXTI_Callback(GPIO_PIN_9); - GPIO_EXTI_Callback(GPIO_PIN_10); - GPIO_EXTI_Callback(GPIO_PIN_11); - rt_interrupt_leave(); -} - -void EXTI12_15_Handler(void) -{ - rt_interrupt_enter(); - GPIO_EXTI_Callback(GPIO_PIN_12); - GPIO_EXTI_Callback(GPIO_PIN_13); - GPIO_EXTI_Callback(GPIO_PIN_14); - GPIO_EXTI_Callback(GPIO_PIN_15); - rt_interrupt_leave(); -} - -#endif diff --git a/bsp/essemi/es32f0334/drivers/drv_gpio.h b/bsp/essemi/es32f0334/drivers/drv_gpio.h deleted file mode 100644 index 506ab8cce6..0000000000 --- a/bsp/essemi/es32f0334/drivers/drv_gpio.h +++ /dev/null @@ -1,16 +0,0 @@ -/* - * Copyright (C) 2018 Shanghai Eastsoft Microelectronics Co., Ltd. - * - * SPDX-License-Identifier: Apache-2.0 - * - * Change Logs: - * Date Author Notes - * 2019-03-01 wangyq the first version - */ - -#ifndef DRV_GPIO_H__ -#define DRV_GPIO_H__ - -int rt_hw_pin_init(void); - -#endif diff --git a/bsp/essemi/es32f0334/drivers/drv_hwtimer.c b/bsp/essemi/es32f0334/drivers/drv_hwtimer.c deleted file mode 100644 index 499a7b429d..0000000000 --- a/bsp/essemi/es32f0334/drivers/drv_hwtimer.c +++ /dev/null @@ -1,251 +0,0 @@ -/* - * Copyright (C) 2018 Shanghai Eastsoft Microelectronics Co., Ltd. - * - * SPDX-License-Identifier: Apache-2.0 - * - * Change Logs: - * Date Author Notes - * 2019-3-19 wangyq the first version - * 2019-11-01 wangyq update libraries - */ - -#include -#include -#include -#include -#include -#include -#include - -#ifdef RT_USING_HWTIMER - -struct es32f0_hwtimer_dev -{ - rt_hwtimer_t parent; - timer_handle_t *hwtimer_periph; - IRQn_Type IRQn; -}; - -#ifdef BSP_USING_HWTIMER0 -static struct es32f0_hwtimer_dev hwtimer0; - -void BS16T0_Handler(void) -{ - ald_timer_clear_flag_status(hwtimer0.hwtimer_periph, TIMER_FLAG_UPDATE); - rt_device_hwtimer_isr(&hwtimer0.parent); - - if (HWTIMER_MODE_ONESHOT == hwtimer0.parent.mode) - { - ald_timer_base_stop(hwtimer0.hwtimer_periph); - } -} -#endif - -#ifdef BSP_USING_HWTIMER1 -static struct es32f0_hwtimer_dev hwtimer1; - -void BS16T1_UART2_Handler(void) -{ - if (ald_timer_get_it_status(hwtimer1.hwtimer_periph, TIMER_IT_UPDATE) && - ald_timer_get_flag_status(hwtimer1.hwtimer_periph, TIMER_FLAG_UPDATE)) - { - ald_timer_clear_flag_status(hwtimer1.hwtimer_periph, TIMER_FLAG_UPDATE); - rt_device_hwtimer_isr(&hwtimer1.parent); - - if (HWTIMER_MODE_ONESHOT == hwtimer1.parent.mode) - { - ald_timer_base_stop(hwtimer1.hwtimer_periph); - } - } -} -#endif - -#ifdef BSP_USING_HWTIMER2 -static struct es32f0_hwtimer_dev hwtimer2; - -void BS16T2_UART3_Handler(void) -{ - if (ald_timer_get_it_status(hwtimer2.hwtimer_periph, TIMER_IT_UPDATE) && - ald_timer_get_flag_status(hwtimer2.hwtimer_periph, TIMER_FLAG_UPDATE)) - { - ald_timer_clear_flag_status(hwtimer2.hwtimer_periph, TIMER_FLAG_UPDATE); - rt_device_hwtimer_isr(&hwtimer2.parent); - - if (HWTIMER_MODE_ONESHOT == hwtimer2.parent.mode) - { - ald_timer_base_stop(hwtimer2.hwtimer_periph); - } - } -} -#endif - -#ifdef BSP_USING_HWTIMER3 -static struct es32f0_hwtimer_dev hwtimer3; -/* can not use when DAC0 Handler is enabled */ -void BS16T3_DAC0_Handler(void) -{ - /* if BS16T3 it */ - if (ald_timer_get_it_status(hwtimer3.hwtimer_periph, TIMER_IT_UPDATE) && - ald_timer_get_flag_status(hwtimer3.hwtimer_periph, TIMER_FLAG_UPDATE)) - { - ald_timer_clear_flag_status(hwtimer3.hwtimer_periph, TIMER_FLAG_UPDATE); - rt_device_hwtimer_isr(&hwtimer3.parent); - - if (HWTIMER_MODE_ONESHOT == hwtimer3.parent.mode) - { - ald_timer_base_stop(hwtimer3.hwtimer_periph); - } - } -} -#endif - -static struct rt_hwtimer_info es32f0_hwtimer_info = -{ - 48000000, /* maximum count frequency */ - 1, /* minimum count frequency */ - 65535, /* counter maximum value */ - HWTIMER_CNTMODE_UP -}; - -static void es32f0_hwtimer_init(rt_hwtimer_t *timer, rt_uint32_t state) -{ - struct es32f0_hwtimer_dev *hwtimer = (struct es32f0_hwtimer_dev *)timer->parent.user_data; - - RT_ASSERT(hwtimer != RT_NULL); - - if (1 == state) - { - ald_timer_base_init(hwtimer->hwtimer_periph); - ald_timer_interrupt_config(hwtimer->hwtimer_periph, TIMER_IT_UPDATE, ENABLE); - NVIC_EnableIRQ(hwtimer->IRQn); - } - hwtimer->parent.freq = ald_cmu_get_pclk1_clock(); - es32f0_hwtimer_info.maxfreq = ald_cmu_get_pclk1_clock(); - es32f0_hwtimer_info.minfreq = ald_cmu_get_pclk1_clock(); -} - -static rt_err_t es32f0_hwtimer_start(rt_hwtimer_t *timer, - rt_uint32_t cnt, - rt_hwtimer_mode_t mode) -{ - struct es32f0_hwtimer_dev *hwtimer = (struct es32f0_hwtimer_dev *)timer->parent.user_data; - - RT_ASSERT(hwtimer != RT_NULL); - - WRITE_REG(hwtimer->hwtimer_periph->perh->AR, cnt); - ald_timer_base_start(hwtimer->hwtimer_periph); - - return RT_EOK; -} - -static void es32f0_hwtimer_stop(rt_hwtimer_t *timer) -{ - struct es32f0_hwtimer_dev *hwtimer = (struct es32f0_hwtimer_dev *)timer->parent.user_data; - - RT_ASSERT(hwtimer != RT_NULL); - - ald_timer_base_stop(hwtimer->hwtimer_periph); -} - -static rt_uint32_t es32f0_hwtimer_count_get(rt_hwtimer_t *timer) -{ - struct es32f0_hwtimer_dev *hwtimer = (struct es32f0_hwtimer_dev *)timer->parent.user_data; - uint32_t hwtimer_count = 0; - - RT_ASSERT(hwtimer != RT_NULL); - - hwtimer_count = READ_REG(hwtimer->hwtimer_periph->perh->COUNT); - - return hwtimer_count; -} - -static rt_err_t es32f0_hwtimer_control(rt_hwtimer_t *timer, - rt_uint32_t cmd, - void *args) -{ - rt_err_t ret = RT_EOK; - rt_uint32_t freq = 0; - struct es32f0_hwtimer_dev *hwtimer = (struct es32f0_hwtimer_dev *)timer->parent.user_data; - - RT_ASSERT(hwtimer != RT_NULL); - - switch (cmd) - { - case HWTIMER_CTRL_FREQ_SET: - freq = *(rt_uint32_t *)args; - if (freq != ald_cmu_get_pclk1_clock()) - { - ret = -RT_ERROR; - } - break; - - case HWTIMER_CTRL_STOP: - ald_timer_base_stop(hwtimer->hwtimer_periph); - break; - - default: - ret = RT_EINVAL; - break; - } - - return ret; -} - -static struct rt_hwtimer_ops es32f0_hwtimer_ops = -{ - es32f0_hwtimer_init, - es32f0_hwtimer_start, - es32f0_hwtimer_stop, - es32f0_hwtimer_count_get, - es32f0_hwtimer_control -}; - -int rt_hw_hwtimer_init(void) -{ - rt_err_t ret = RT_EOK; - -#ifdef BSP_USING_HWTIMER0 - static timer_handle_t _hwtimer_periph0; - _hwtimer_periph0.perh = BS16T0; - hwtimer0.IRQn = BS16T0_IRQn; - hwtimer0.hwtimer_periph = &_hwtimer_periph0; - hwtimer0.parent.info = &es32f0_hwtimer_info; - hwtimer0.parent.ops = &es32f0_hwtimer_ops; - ret = rt_device_hwtimer_register(&hwtimer0.parent, "timer0", &hwtimer0); -#endif - -#ifdef BSP_USING_HWTIMER1 - static timer_handle_t _hwtimer_periph1; - _hwtimer_periph1.perh = BS16T1; - hwtimer1.IRQn = BS16T1_UART2_IRQn; - hwtimer1.hwtimer_periph = &_hwtimer_periph1; - hwtimer1.parent.info = &es32f0_hwtimer_info; - hwtimer1.parent.ops = &es32f0_hwtimer_ops; - ret = rt_device_hwtimer_register(&hwtimer1.parent, "timer1", &hwtimer1); -#endif - -#ifdef BSP_USING_HWTIMER2 - static timer_handle_t _hwtimer_periph2; - _hwtimer_periph2.perh = BS16T2; - hwtimer2.IRQn = BS16T2_UART3_IRQn; - hwtimer2.hwtimer_periph = &_hwtimer_periph2; - hwtimer2.parent.info = &es32f0_hwtimer_info; - hwtimer2.parent.ops = &es32f0_hwtimer_ops; - ret = rt_device_hwtimer_register(&hwtimer2.parent, "timer2", &hwtimer2); -#endif - -#ifdef BSP_USING_HWTIMER3 - static timer_handle_t _hwtimer_periph3; - _hwtimer_periph3.perh = BS16T3; - hwtimer3.IRQn = BS16T3_DAC0_IRQn; - hwtimer3.hwtimer_periph = &_hwtimer_periph3; - hwtimer3.parent.info = &es32f0_hwtimer_info; - hwtimer3.parent.ops = &es32f0_hwtimer_ops; - ret = rt_device_hwtimer_register(&hwtimer3.parent, "timer3", &hwtimer3); -#endif - - return ret; -} -INIT_BOARD_EXPORT(rt_hw_hwtimer_init); - -#endif diff --git a/bsp/essemi/es32f0334/drivers/drv_hwtimer.h b/bsp/essemi/es32f0334/drivers/drv_hwtimer.h deleted file mode 100644 index e18d580fbd..0000000000 --- a/bsp/essemi/es32f0334/drivers/drv_hwtimer.h +++ /dev/null @@ -1,16 +0,0 @@ -/* - * Copyright (C) 2018 Shanghai Eastsoft Microelectronics Co., Ltd. - * - * SPDX-License-Identifier: Apache-2.0 - * - * Change Logs: - * Date Author Notes - * 2019-3-19 wangyq the first version - */ - -#ifndef DRV_HWTIMER_H__ -#define DRV_HWTIMER_H__ - -int rt_hw_hwtimer_init(void); - -#endif diff --git a/bsp/essemi/es32f0334/drivers/drv_i2c.c b/bsp/essemi/es32f0334/drivers/drv_i2c.c deleted file mode 100644 index 6824d654b5..0000000000 --- a/bsp/essemi/es32f0334/drivers/drv_i2c.c +++ /dev/null @@ -1,143 +0,0 @@ -/* - * Copyright (C) 2018 Shanghai Eastsoft Microelectronics Co., Ltd. - * - * SPDX-License-Identifier: Apache-2.0 - * - * Change Logs: - * Date Author Notes - * 2019-03-19 wangyq the first version - * 2019-11-01 wangyq update libraries - * 2020-12-15 liuhy update libraries - */ - -#include -#include -#include -#include "board.h" -#include "drv_i2c.h" -#include -#include - -#ifdef RT_USING_I2C - -#define TIMEOUT 0x0FFF -/* I2C struct definition */ -static i2c_handle_t _h_i2c0, _h_i2c1; - -static void _i2c_init(void) -{ - gpio_init_t gpio_instruct; - - /* Initialize I2C Pin */ - gpio_instruct.mode = GPIO_MODE_OUTPUT; - gpio_instruct.odos = GPIO_OPEN_DRAIN; - gpio_instruct.pupd = GPIO_PUSH_UP; - gpio_instruct.odrv = GPIO_OUT_DRIVE_NORMAL; - gpio_instruct.flt = GPIO_FILTER_DISABLE; - gpio_instruct.type = GPIO_TYPE_CMOS; - gpio_instruct.func = GPIO_FUNC_5; - -#ifdef BSP_USING_I2C0 - /* Initialize I2C Function */ - _h_i2c0.perh = I2C0; - _h_i2c0.init.clk_speed = 100000; - _h_i2c0.init.duty = I2C_DUTYCYCLE_2; - _h_i2c0.init.own_addr1 = 0x0A; - _h_i2c0.init.addr_mode = I2C_ADDR_7BIT; - _h_i2c0.init.general_call = I2C_GENERALCALL_DISABLE; - _h_i2c0.init.no_stretch = I2C_NOSTRETCH_ENABLE; - - ald_i2c_reset(&_h_i2c0); - ald_i2c_init(&_h_i2c0); - /* I2C0_SCL->PB8, I2C0_SDA->PB9 */ - ald_gpio_init(GPIOB, GPIO_PIN_8 | GPIO_PIN_9, &gpio_instruct); -#endif - -#ifdef BSP_USING_I2C1 - /* Initialize i2c function */ - _h_i2c1.perh = I2C1; - _h_i2c1.init.clk_speed = 100000; - _h_i2c1.init.duty = I2C_DUTYCYCLE_2; - _h_i2c1.init.own_addr1 = 0xA0; - _h_i2c1.init.addr_mode = I2C_ADDR_7BIT; - _h_i2c1.init.general_call = I2C_GENERALCALL_DISABLE; - _h_i2c1.init.no_stretch = I2C_NOSTRETCH_ENABLE; - - ald_i2c_reset(&_h_i2c1); - ald_i2c_init(&_h_i2c1); - /* I2C1_SCL->PB10, I2C1_SDA->PB11 */ - ald_gpio_init(GPIOB, GPIO_PIN_10 | GPIO_PIN_11, &gpio_instruct); -#endif -} - -static rt_size_t es32f0_master_xfer(struct rt_i2c_bus_device *bus, - struct rt_i2c_msg msgs[], - rt_uint32_t num) -{ - struct rt_i2c_msg *msg; - rt_uint32_t i; - rt_err_t ret = RT_ERROR; - - for (i = 0; i < num; i++) - { - msg = &msgs[i]; - if (msg->flags & RT_I2C_RD) - { - if (ald_i2c_master_recv(bus->priv, msg->addr << 1, msg->buf, msg->len, TIMEOUT) != 0) - { - LOG_E("i2c bus write failed,i2c bus stop!\n"); - goto out; - } - } - else - { - if (ald_i2c_master_send(bus->priv, msg->addr << 1, msg->buf, msg->len, TIMEOUT) != 0) - { - LOG_E("i2c bus write failed,i2c bus stop!\n"); - goto out; - } - } - } - - ret = i; - -out: - LOG_E("send stop condition\n"); - - return ret; -} - -const struct rt_i2c_bus_device_ops es32f0_i2c_ops = -{ - es32f0_master_xfer, - RT_NULL, - RT_NULL, -}; - -int rt_hw_i2c_init(void) -{ - _i2c_init(); - -#ifdef BSP_USING_I2C0 - /* define i2c Instance */ - static struct rt_i2c_bus_device _i2c_device0; - rt_memset((void *)&_i2c_device0, 0, sizeof(struct rt_i2c_bus_device)); - _i2c_device0.ops = &es32f0_i2c_ops; - _i2c_device0.priv = &_h_i2c0; - rt_i2c_bus_device_register(&_i2c_device0, "i2c0"); -#endif - -#ifdef BSP_USING_I2C1 - /* define i2c Instance */ - static struct rt_i2c_bus_device _i2c_device1; - rt_memset((void *)&_i2c_device1, 0, sizeof(struct rt_i2c_bus_device)); - _i2c_device1.ops = &es32f0_i2c_ops; - _i2c_device1.priv = &_h_i2c1; - rt_i2c_bus_device_register(&_i2c_device1, "i2c1"); -#endif - - return RT_EOK; -} -INIT_DEVICE_EXPORT(rt_hw_i2c_init); - -#endif diff --git a/bsp/essemi/es32f0334/drivers/drv_i2c.h b/bsp/essemi/es32f0334/drivers/drv_i2c.h deleted file mode 100644 index 2ba40feb69..0000000000 --- a/bsp/essemi/es32f0334/drivers/drv_i2c.h +++ /dev/null @@ -1,16 +0,0 @@ -/* - * Copyright (C) 2018 Shanghai Eastsoft Microelectronics Co., Ltd. - * - * SPDX-License-Identifier: Apache-2.0 - * - * Change Logs: - * Date Author Notes - * 2019-03-19 wangyq the first version - */ - -#ifndef DRV_I2C_H__ -#define DRV_I2C_H__ - -int rt_hw_i2c_init(void); - -#endif diff --git a/bsp/essemi/es32f0334/drivers/drv_lptim.c b/bsp/essemi/es32f0334/drivers/drv_lptim.c deleted file mode 100644 index 9bf0f8c0fe..0000000000 --- a/bsp/essemi/es32f0334/drivers/drv_lptim.c +++ /dev/null @@ -1,124 +0,0 @@ -/* - * Copyright (C) 2018 Shanghai Eastsoft Microelectronics Co., Ltd. - * - * SPDX-License-Identifier: Apache-2.0 - * - * Change Logs: - * Date Author Notes - * 2019-11-01 wangyq first version - */ - -#include -#include -#include - -static lptim_handle_t h_lptim; - -void LPTIM0_SPI2_Handler(void) -{ - /* LPTIM Intetrupt */ - if (ald_lptim_get_it_status(&h_lptim, LPTIM_IT_ARRMAT) && - ald_lptim_get_flag_status(&h_lptim, LPTIM_FLAG_ARRMAT)) - { - /* enter interrupt */ - rt_interrupt_enter(); - - ald_lptim_clear_flag_status(&h_lptim, LPTIM_FLAG_ARRMAT); - - /* leave interrupt */ - rt_interrupt_leave(); - } -} - -/** - * This function get current count value of LPTIM - * - * @return the count vlaue - */ -rt_uint32_t es32f0_lptim_get_current_tick(void) -{ - return READ_REG(h_lptim.perh->CNT); -} - -/** - * This function get the max value that LPTIM can count - * - * @return the max count - */ -rt_uint32_t es32f0_lptim_get_tick_max(void) -{ - return (0xFFFF); -} - -/** - * This function start LPTIM with reload value - * - * @param reload The value that LPTIM count down from - * - * @return RT_EOK - */ -rt_err_t es32f0_lptim_start(rt_uint32_t reload) -{ - h_lptim.init.arr = reload; - ald_lptim_toggle_start_by_it(&h_lptim); - - return (RT_EOK); -} - -/** - * This function stop LPTIM - */ -void es32f0_lptim_stop(void) -{ - ald_lptim_toggle_stop_by_it(&h_lptim); -} - -/** - * This function get the count clock of LPTIM - * - * @return the count clock frequency in Hz - */ -rt_uint32_t es32f0_lptim_get_countfreq(void) -{ - return 1000000; -} - -/** - * This function initialize the lptim - */ -int es32f0_hw_lptim_init(void) -{ - lptim_clock_source_init_t clock_config; - lptim_trigger_init_t trigger_config; - - /* Enable LPTIM clock */ - ald_cmu_perh_clock_config(CMU_PERH_LPTIM0, ENABLE); - - /* LPTIM Configuration */ - h_lptim.perh = LPTIM0; - h_lptim.init.psc = LPTIM_PRESC_1; // can not select other premeter - h_lptim.init.arr = 0x0FFF; - h_lptim.init.clock = CMU_LP_PERH_CLOCK_SEL_HRC_1M; - h_lptim.init.mode = LPTIM_MODE_SINGLE; - - ald_lptim_toggle_init(&h_lptim); - - /* Initialize clock source */ - clock_config.sel = LPTIM_CKSEL_INTERNAL; - clock_config.polarity = LPTIM_CKPOL_RISING; - ald_lptim_clock_source_config(&h_lptim, &clock_config); - - /* Initialize toggle */ - trigger_config.mode = LPTIM_TRIGEN_SW; - ald_lptim_trigger_config(&h_lptim, &trigger_config); - - ald_lptim_interrupt_config(&h_lptim, LPTIM_IT_ARRMAT, ENABLE); - - NVIC_ClearPendingIRQ(LPTIM0_SPI2_IRQn); - NVIC_SetPriority(LPTIM0_SPI2_IRQn, 0); - NVIC_EnableIRQ(LPTIM0_SPI2_IRQn); - - return 0; -} - -INIT_DEVICE_EXPORT(es32f0_hw_lptim_init); diff --git a/bsp/essemi/es32f0334/drivers/drv_lptim.h b/bsp/essemi/es32f0334/drivers/drv_lptim.h deleted file mode 100644 index 0e178ce848..0000000000 --- a/bsp/essemi/es32f0334/drivers/drv_lptim.h +++ /dev/null @@ -1,23 +0,0 @@ -/* - * Copyright (C) 2018 Shanghai Eastsoft Microelectronics Co., Ltd. - * - * SPDX-License-Identifier: Apache-2.0 - * - * Change Logs: - * Date Author Notes - * 2019-11-01 wangyq first version - */ - -#ifndef __DRV_PMTIMER_H__ -#define __DRV_PMTIMER_H__ - -#include - -rt_uint32_t es32f0_lptim_get_countfreq(void); -rt_uint32_t es32f0_lptim_get_tick_max(void); -rt_uint32_t es32f0_lptim_get_current_tick(void); - -rt_err_t es32f0_lptim_start(rt_uint32_t load); -void es32f0_lptim_stop(void); - -#endif /* __DRV_PMTIMER_H__ */ diff --git a/bsp/essemi/es32f0334/drivers/drv_pm.c b/bsp/essemi/es32f0334/drivers/drv_pm.c deleted file mode 100644 index d08c13f8d0..0000000000 --- a/bsp/essemi/es32f0334/drivers/drv_pm.c +++ /dev/null @@ -1,260 +0,0 @@ -/* - * Copyright (C) 2018 Shanghai Eastsoft Microelectronics Co., Ltd. - * - * SPDX-License-Identifier: Apache-2.0 - * - * Change Logs: - * Date Author Notes - * 2019-04-08 wangyq the first version - * 2019-11-01 wangyq adapt to the new power management interface - */ -#include -#include -#include -#include -#include -#include - -#ifdef RT_USING_PM - -static void uart_console_reconfig(void) -{ - struct serial_configure config = RT_SERIAL_CONFIG_DEFAULT; - - rt_device_control(rt_console_get_device(), RT_DEVICE_CTRL_CONFIG, &config); -} - -static void delay(void) -{ - long i; - rt_base_t level; - - level = rt_hw_interrupt_disable(); - i = 0; - do{ - i++; - } - while (i < 10000); - - rt_hw_interrupt_enable(level); -} - -/** - * This function will put ES32F033x into sleep mode. - * - * @param pm pointer to power manage structure - */ -static void sleep(struct rt_pm *pm, uint8_t mode) -{ - switch (mode) - { - case PM_SLEEP_MODE_NONE: - break; - - case PM_SLEEP_MODE_IDLE: - //__WFI(); - break; - - case PM_SLEEP_MODE_LIGHT: - if (pm->run_mode == PM_RUN_MODE_LOW_SPEED) - { - /* Enter LP SLEEP Mode, Enable low-power regulator */ - ald_pmu_lprun_config(PMU_LDO_LPMODE_OUTPUT_1_5, ENABLE); - } - else - { - /* Enter SLEEP Mode, Main regulator is ON */ - ald_pmu_stop1_enter(); - delay(); - } - break; - - case PM_SLEEP_MODE_DEEP: - /* Enter STOP 2 mode */ - ald_pmu_stop2_enter(); - delay(); - break; - - case PM_SLEEP_MODE_STANDBY: - /* Enter STANDBY mode */ - ald_pmu_stop2_enter(); - delay(); - break; - - case PM_SLEEP_MODE_SHUTDOWN: - /* Enter SHUTDOWNN mode */ - ald_pmu_stop2_enter(); - delay(); - break; - - default: - RT_ASSERT(0); - break; - } -} - -static uint8_t run_speed[PM_RUN_MODE_MAX][2] = -{ - {48, 0}, - {48, 1}, - {24, 2}, - {2, 3}, -}; - -static void run(struct rt_pm *pm, uint8_t mode) -{ - static uint8_t last_mode; - static char *run_str[] = PM_RUN_MODE_NAMES; - extern uint32_t __system_clock; - - if (mode == last_mode) - return; - last_mode = mode; - - ald_cmu_clock_config_default(); - __system_clock = 24000000; - switch (mode) - { - case PM_RUN_MODE_HIGH_SPEED: - case PM_RUN_MODE_NORMAL_SPEED: - /* hosc 12MHz, from hosc/3 pll to 48MHz */ - ald_cmu_pll1_config(CMU_PLL1_INPUT_HRC_6, CMU_PLL1_OUTPUT_48M); - /* MCLK 48MHz */ - ald_cmu_clock_config(CMU_CLOCK_PLL1, 48000000); - break; - case PM_RUN_MODE_MEDIUM_SPEED: - break; - case PM_RUN_MODE_LOW_SPEED: - ald_cmu_clock_config(CMU_CLOCK_HRC, 2000000); - break; - default: - break; - } - - /* 4. 更新外设时钟 */ - uart_console_reconfig(); - /* Re-Configure the Systick time */ - SysTick_Config(ald_cmu_get_sys_clock() / RT_TICK_PER_SECOND); - - rt_kprintf("switch to %s mode, frequency = %d MHz\n", run_str[mode], run_speed[mode][0]); -} - -/** - * This function caculate the PM tick from OS tick - * - * @param tick OS tick - * - * @return the PM tick - */ -static rt_tick_t es32f0_pm_tick_from_os_tick(rt_tick_t tick) -{ - rt_uint32_t freq = es32f0_lptim_get_countfreq(); - - return (freq * tick / RT_TICK_PER_SECOND); -} - -/** - * This function caculate the OS tick from PM tick - * - * @param tick PM tick - * - * @return the OS tick - */ -static rt_tick_t es32f0_os_tick_from_pm_tick(rt_uint32_t tick) -{ - static rt_uint32_t os_tick_remain = 0; - rt_uint32_t ret, freq; - - freq = es32f0_lptim_get_countfreq(); - ret = (tick * RT_TICK_PER_SECOND + os_tick_remain) / freq; - - os_tick_remain += (tick * RT_TICK_PER_SECOND); - os_tick_remain %= freq; - - return ret; -} - -/** - * This function start the timer of pm - * - * @param pm Pointer to power manage structure - * @param timeout How many OS Ticks that MCU can sleep - */ -static void pm_timer_start(struct rt_pm *pm, rt_uint32_t timeout) -{ - RT_ASSERT(pm != RT_NULL); - RT_ASSERT(timeout > 0); - - if (timeout != RT_TICK_MAX) - { - /* Convert OS Tick to pmtimer timeout value */ - timeout = es32f0_pm_tick_from_os_tick(timeout); - /* MAX 0xFFFF */ - if (timeout > es32f0_lptim_get_tick_max()) - { - timeout = es32f0_lptim_get_tick_max(); - } - - /* Enter PM_TIMER_MODE */ - es32f0_lptim_start(timeout); - } -} - -/** - * This function stop the timer of pm - * - * @param pm Pointer to power manage structure - */ -static void pm_timer_stop(struct rt_pm *pm) -{ - RT_ASSERT(pm != RT_NULL); - - /* Reset pmtimer status */ - es32f0_lptim_stop(); -} - -/** - * This function calculate how many OS Ticks that MCU have suspended - * - * @param pm Pointer to power manage structure - * - * @return OS Ticks - */ -static rt_tick_t pm_timer_get_tick(struct rt_pm *pm) -{ - rt_uint32_t timer_tick; - - RT_ASSERT(pm != RT_NULL); - - timer_tick = es32f0_lptim_get_current_tick(); - - return es32f0_os_tick_from_pm_tick(timer_tick); -} - -/** - * This function initialize the power manager - */ -int drv_pm_hw_init(void) -{ - static const struct rt_pm_ops _ops = - { - sleep, - run, - pm_timer_start, - pm_timer_stop, - pm_timer_get_tick - }; - - rt_uint8_t timer_mask = 0; - - /* initialize timer mask */ - timer_mask = 1UL << PM_SLEEP_MODE_DEEP; - - /* initialize system pm module */ - rt_system_pm_init(&_ops, timer_mask, RT_NULL); - - return 0; -} -INIT_BOARD_EXPORT(drv_pm_hw_init); - -#endif diff --git a/bsp/essemi/es32f0334/drivers/drv_pm.h b/bsp/essemi/es32f0334/drivers/drv_pm.h deleted file mode 100644 index a4f6cc84ee..0000000000 --- a/bsp/essemi/es32f0334/drivers/drv_pm.h +++ /dev/null @@ -1,16 +0,0 @@ -/* - * Copyright (C) 2018 Shanghai Eastsoft Microelectronics Co., Ltd. - * - * SPDX-License-Identifier: Apache-2.0 - * - * Change Logs: - * Date Author Notes - * 2019-04-01 wangyq the first version - */ - -#ifndef DRV_PM_H__ -#define DRV_PM_H__ - -int rt_hw_pm_init(void); - -#endif diff --git a/bsp/essemi/es32f0334/drivers/drv_pwm.c b/bsp/essemi/es32f0334/drivers/drv_pwm.c deleted file mode 100644 index 2a40b3d299..0000000000 --- a/bsp/essemi/es32f0334/drivers/drv_pwm.c +++ /dev/null @@ -1,212 +0,0 @@ -/* - * Copyright (C) 2018 Shanghai Eastsoft Microelectronics Co., Ltd. - * - * SPDX-License-Identifier: Apache-2.0 - * - * Change Logs: - * Date Author Notes - * 2019-03-19 wangyq the first version - * 2019-11-01 wangyq update libraries - */ - -#include -#include -#include -#include -#include -#include -#include - -static void pwm_set_freq(timer_handle_t *timer_initstruct, uint32_t ns) -{ - uint64_t _arr = (uint64_t)ald_cmu_get_pclk1_clock() * ns / 1000000000 / - (timer_initstruct->init.prescaler + 1); - - WRITE_REG(timer_initstruct->perh->AR, (uint32_t)_arr); - timer_initstruct->init.period = (uint32_t)_arr; -} - -static void pwm_set_duty(timer_handle_t *timer_initstruct, timer_channel_t ch, uint32_t ns) -{ - uint64_t tmp = (uint64_t)ald_cmu_get_pclk1_clock() * ns / 1000000000 / - (timer_initstruct->init.prescaler + 1); - - if (ch == TIMER_CHANNEL_1) - WRITE_REG(timer_initstruct->perh->CCVAL1, (uint32_t)tmp); - else if (ch == TIMER_CHANNEL_2) - WRITE_REG(timer_initstruct->perh->CCVAL2, (uint32_t)tmp); - else if (ch == TIMER_CHANNEL_3) - WRITE_REG(timer_initstruct->perh->CCVAL3, (uint32_t)tmp); - else if (ch == TIMER_CHANNEL_4) - WRITE_REG(timer_initstruct->perh->CCVAL4, (uint32_t)tmp); -} - -static rt_err_t es32f0_pwm_control(struct rt_device_pwm *device, int cmd, void *arg) -{ - rt_err_t ret = RT_EOK; - uint32_t _ccep; - timer_channel_t pwm_channel; - timer_oc_init_t tim_ocinit; - timer_handle_t *timer_initstruct = (timer_handle_t *)device->parent.user_data; - struct rt_pwm_configuration *cfg = (struct rt_pwm_configuration *)arg; - - RT_ASSERT(timer_initstruct != RT_NULL); - - tim_ocinit.oc_mode = TIMER_OC_MODE_PWM1; - tim_ocinit.oc_polarity = TIMER_OC_POLARITY_HIGH; - tim_ocinit.oc_fast_en = DISABLE; - tim_ocinit.ocn_polarity = TIMER_OCN_POLARITY_HIGH; - tim_ocinit.ocn_idle = TIMER_OCN_IDLE_RESET; - tim_ocinit.oc_idle = TIMER_OC_IDLE_RESET; - - /* select pwm output channel */ - if (1 == cfg->channel) - { - pwm_channel = TIMER_CHANNEL_1; - } - else if (2 == cfg->channel) - { - pwm_channel = TIMER_CHANNEL_2; - } - else if (3 == cfg->channel) - { - if (timer_initstruct->perh == GP16C2T0 || timer_initstruct->perh == GP16C2T1) - return RT_EINVAL; - pwm_channel = TIMER_CHANNEL_3; - } - else if (4 == cfg->channel) - { - if (timer_initstruct->perh == GP16C2T0 || timer_initstruct->perh == GP16C2T1 || - timer_initstruct->perh == GP16C4T0) - return RT_EINVAL; - pwm_channel = TIMER_CHANNEL_4; - } - else - { - return RT_EINVAL; - } - - switch (cmd) - { - case PWM_CMD_ENABLE: - ald_timer_pwm_start(timer_initstruct, pwm_channel); - break; - - case PWM_CMD_DISABLE: - ald_timer_pwm_stop(timer_initstruct, pwm_channel); - break; - - case PWM_CMD_SET: - _ccep = timer_initstruct->perh->CCEP; - /* count registers max 0xFFFF, auto adjust prescaler */ - do - { - pwm_set_freq(timer_initstruct, cfg->period); - timer_initstruct->init.prescaler ++; - } - while (timer_initstruct->init.period > 0xFFFF); - /* update prescaler */ - WRITE_REG(timer_initstruct->perh->PRES, --timer_initstruct->init.prescaler); - ald_timer_oc_config_channel(timer_initstruct, &tim_ocinit, pwm_channel); - pwm_set_duty(timer_initstruct, pwm_channel, cfg->pulse); - timer_initstruct->perh->CCEP = _ccep; - break; - - case PWM_CMD_GET: - cfg->pulse = ald_timer_read_capture_value(timer_initstruct, pwm_channel) * 100 / - READ_REG(timer_initstruct->perh->AR); - break; - - default: - break; - } - return ret; -} - -const static struct rt_pwm_ops es32f0_pwm_ops = -{ - es32f0_pwm_control -}; - -int rt_hw_pwm_init(void) -{ - rt_err_t ret = RT_EOK; - gpio_init_t gpio_initstructure; - - gpio_initstructure.mode = GPIO_MODE_OUTPUT; - gpio_initstructure.odos = GPIO_PUSH_PULL; - gpio_initstructure.pupd = GPIO_PUSH_UP; - gpio_initstructure.odrv = GPIO_OUT_DRIVE_NORMAL; - gpio_initstructure.flt = GPIO_FILTER_DISABLE; - gpio_initstructure.type = GPIO_TYPE_TTL; - -#ifdef BSP_USING_PWM0 /* 4 channels */ - static struct rt_device_pwm pwm_dev0; - static timer_handle_t timer_initstruct0; - - timer_initstruct0.perh = GP16C4T0; - ald_timer_pwm_init(&timer_initstruct0); - - /* gpio initialization */ - gpio_initstructure.func = GPIO_FUNC_2; - ald_gpio_init(GPIOA, GPIO_PIN_8, &gpio_initstructure); - ald_gpio_init(GPIOA, GPIO_PIN_9, &gpio_initstructure); - ald_gpio_init(GPIOA, GPIO_PIN_10, &gpio_initstructure); - ald_gpio_init(GPIOA, GPIO_PIN_11, &gpio_initstructure); - - ret = rt_device_pwm_register(&pwm_dev0, "pwm0", &es32f0_pwm_ops, - &timer_initstruct0); -#endif - -#ifdef BSP_USING_PWM1 /* 3 channels */ - static struct rt_device_pwm pwm_dev1; - static timer_handle_t timer_initstruct1; - - timer_initstruct1.perh = GP16C4T1; - ald_timer_pwm_init(&timer_initstruct1); - - /* gpio initialization */ - gpio_initstructure.func = GPIO_FUNC_2; - ald_gpio_init(GPIOB, GPIO_PIN_6, &gpio_initstructure); - ald_gpio_init(GPIOB, GPIO_PIN_7, &gpio_initstructure); - ald_gpio_init(GPIOB, GPIO_PIN_8, &gpio_initstructure); - - ret = rt_device_pwm_register(&pwm_dev1, "pwm1", &es32f0_pwm_ops, - &timer_initstruct1); -#endif - -#ifdef BSP_USING_PWM2 /* 2 channels */ - static struct rt_device_pwm pwm_dev2; - static timer_handle_t timer_initstruct2; - - timer_initstruct2.perh = GP16C2T0; - ald_timer_pwm_init(&timer_initstruct2); - - /* gpio initialization */ - gpio_initstructure.func = GPIO_FUNC_2; - ald_gpio_init(GPIOA, GPIO_PIN_0, &gpio_initstructure); - ald_gpio_init(GPIOA, GPIO_PIN_1, &gpio_initstructure); - - ret = rt_device_pwm_register(&pwm_dev2, "pwm2", &es32f0_pwm_ops, - &timer_initstruct2); -#endif - -#ifdef BSP_USING_PWM3 /* 2 channels */ - static struct rt_device_pwm pwm_dev3; - static timer_handle_t timer_initstruct3; - - timer_initstruct3.perh = GP16C2T1; - ald_timer_pwm_init(&timer_initstruct3); - - /* gpio initialization */ - gpio_initstructure.func = GPIO_FUNC_3; - ald_gpio_init(GPIOC, GPIO_PIN_6, &gpio_initstructure); - ald_gpio_init(GPIOC, GPIO_PIN_7, &gpio_initstructure); - - ret = rt_device_pwm_register(&pwm_dev3, "pwm3", &es32f0_pwm_ops, - &timer_initstruct3); -#endif - - return ret; -} -INIT_DEVICE_EXPORT(rt_hw_pwm_init); diff --git a/bsp/essemi/es32f0334/drivers/drv_pwm.h b/bsp/essemi/es32f0334/drivers/drv_pwm.h deleted file mode 100644 index 82505bb28c..0000000000 --- a/bsp/essemi/es32f0334/drivers/drv_pwm.h +++ /dev/null @@ -1,16 +0,0 @@ -/* - * Copyright (C) 2018 Shanghai Eastsoft Microelectronics Co., Ltd. - * - * SPDX-License-Identifier: Apache-2.0 - * - * Change Logs: - * Date Author Notes - * 2019-03-19 wangyq the first version - */ - -#ifndef DRV_PWM_H__ -#define DRV_PWM_H__ - -int rt_hw_pwm_init(void); - -#endif diff --git a/bsp/essemi/es32f0334/drivers/drv_rtc.c b/bsp/essemi/es32f0334/drivers/drv_rtc.c deleted file mode 100644 index 9471368454..0000000000 --- a/bsp/essemi/es32f0334/drivers/drv_rtc.c +++ /dev/null @@ -1,159 +0,0 @@ -/* - * Copyright (C) 2018 Shanghai Eastsoft Microelectronics Co., Ltd. - * - * SPDX-License-Identifier: Apache-2.0 - * - * Change Logs: - * Date Author Notes - * 2019-04-01 wangyq the first version - * 2019-11-01 wangyq update libraries - */ - -#include -#include -#include -#include -#include -#include "board.h" -#include "drv_rtc.h" -#include -#include - -#ifdef RT_USING_RTC - -static void __rtc_init(rtc_init_t *init) -{ - assert_param(IS_RTC_HOUR_FORMAT(init->hour_format)); - assert_param(IS_RTC_OUTPUT_SEL(init->output)); - assert_param(IS_RTC_OUTPUT_POLARITY(init->output_polarity)); - - ald_rtc_reset(); - RTC_UNLOCK(); - - MODIFY_REG(RTC->CON, RTC_CON_HFM_MSK, init->hour_format << RTC_CON_HFM_POS); - MODIFY_REG(RTC->CON, RTC_CON_EOS_MSK, init->output << RTC_CON_EOS_POSS); - MODIFY_REG(RTC->CON, RTC_CON_POL_MSK, init->output_polarity << RTC_CON_POL_POS); - MODIFY_REG(RTC->PSR, RTC_PSR_SPRS_MSK, init->synch_pre_div << RTC_PSR_SPRS_POSS); - MODIFY_REG(RTC->PSR, RTC_PSR_APRS_MSK, init->asynch_pre_div << RTC_PSR_APRS_POSS); - - RTC_LOCK(); - return; -} - -static rt_err_t es32f0_rtc_control(rt_device_t dev, int cmd, void *args) -{ - rt_err_t result = RT_EOK; - - struct tm time_temp; - struct tm *pNow; - rtc_date_t date; - rtc_time_t time; - - switch (cmd) - { - case RT_DEVICE_CTRL_RTC_GET_TIME: - - ald_rtc_get_date_time(&date, &time, RTC_FORMAT_DEC); - time_temp.tm_sec = time.second; - time_temp.tm_min = time.minute; - time_temp.tm_hour = time.hour; - time_temp.tm_mday = date.day; - time_temp.tm_mon = date.month - 1; - time_temp.tm_year = date.year - 1900 + 2000; - *((time_t *)args) = timegm(&time_temp); - break; - - case RT_DEVICE_CTRL_RTC_SET_TIME: - - rt_enter_critical(); - /* converts calendar time time into local time. */ - pNow = gmtime((const time_t *)args); - /* copy the statically located variable */ - memcpy(&time_temp, pNow, sizeof(struct tm)); - /* unlock scheduler. */ - rt_exit_critical(); - - time.hour = time_temp.tm_hour; - time.minute = time_temp.tm_min; - time.second = time_temp.tm_sec; - date.year = time_temp.tm_year + 1900 - 2000; - date.month = time_temp.tm_mon + 1; - date.day = time_temp.tm_mday; - ald_rtc_set_time(&time, RTC_FORMAT_DEC); - ald_rtc_set_date(&date, RTC_FORMAT_DEC); - /* start RTC */ - RTC_UNLOCK(); - SET_BIT(RTC->CON, RTC_CON_GO_MSK); - RTC_LOCK(); - break; - - case RT_DEVICE_CTRL_RTC_GET_ALARM: - break; - - case RT_DEVICE_CTRL_RTC_SET_ALARM: - break; - - default: - break; - } - - return result; -} - -#ifdef RT_USING_DEVICE_OPS -const static struct rt_device_ops es32f0_rtc_ops = -{ - RT_NULL, - RT_NULL, - RT_NULL, - RT_NULL, - RT_NULL, - es32f0_rtc_control -}; -#endif - -int rt_hw_rtc_init(void) -{ - rt_err_t ret = RT_EOK; - static struct rt_device rtc_dev; - rtc_init_t rtc_initstruct; - - /* enable external 32.768kHz */ - CMU_LOSC_ENABLE(); - ald_cmu_losc_safe_config(ENABLE); - /* set default time */ - RTC_UNLOCK(); - WRITE_REG(RTC->TIME, 0x134251); - WRITE_REG(RTC->DATE, 0x1190401); - RTC_LOCK(); - /* RTC function initialization */ - rtc_initstruct.hour_format = RTC_HOUR_FORMAT_24; - rtc_initstruct.asynch_pre_div = 0; - rtc_initstruct.synch_pre_div = 32767; - rtc_initstruct.output = RTC_OUTPUT_DISABLE; - __rtc_init(&rtc_initstruct); - - rtc_dev.type = RT_Device_Class_RTC; - rtc_dev.rx_indicate = RT_NULL; - rtc_dev.tx_complete = RT_NULL; - -#ifdef RT_USING_DEVICE_OPS - rtc_dev.ops = &es32f0_rtc_ops; -#else - rtc_dev.init = RT_NULL; - rtc_dev.open = RT_NULL; - rtc_dev.close = RT_NULL; - rtc_dev.read = RT_NULL; - rtc_dev.write = RT_NULL; - rtc_dev.control = es32f0_rtc_control; -#endif - - rtc_dev.user_data = RTC; - - ret = rt_device_register(&rtc_dev, "rtc", RT_DEVICE_FLAG_RDWR); - - return ret; -} -INIT_DEVICE_EXPORT(rt_hw_rtc_init); - -#endif diff --git a/bsp/essemi/es32f0334/drivers/drv_rtc.h b/bsp/essemi/es32f0334/drivers/drv_rtc.h deleted file mode 100644 index 68c2b8c891..0000000000 --- a/bsp/essemi/es32f0334/drivers/drv_rtc.h +++ /dev/null @@ -1,16 +0,0 @@ -/* - * Copyright (C) 2018 Shanghai Eastsoft Microelectronics Co., Ltd. - * - * SPDX-License-Identifier: Apache-2.0 - * - * Change Logs: - * Date Author Notes - * 2019-04-01 wangyq the first version - */ - -#ifndef DRV_RTC_H__ -#define DRV_RTC_H__ - -int rt_hw_rtc_init(void); - -#endif diff --git a/bsp/essemi/es32f0334/drivers/drv_spi.c b/bsp/essemi/es32f0334/drivers/drv_spi.c deleted file mode 100644 index dd37691125..0000000000 --- a/bsp/essemi/es32f0334/drivers/drv_spi.c +++ /dev/null @@ -1,344 +0,0 @@ -/* - * Copyright (C) 2018 Shanghai Eastsoft Microelectronics Co., Ltd. - * - * SPDX-License-Identifier: Apache-2.0 - * - * Change Logs: - * Date Author Notes - * 2019-01-24 wangyq the first version - * 2019-11-01 wangyq update libraries - * 2020-12-15 liuhy update libraries - */ - -#include -#include -#include -#include -#include "board.h" -#include "drv_spi.h" -#include -#include -#include - -#ifdef RT_USING_SPI - -#define SPITIMEOUT 0x0FFF - -rt_err_t spi_configure(struct rt_spi_device *device, - struct rt_spi_configuration *cfg) -{ - spi_handle_t *hspi; - hspi = (spi_handle_t *)device->bus->parent.user_data; - - /* config spi mode */ - if (cfg->mode & RT_SPI_SLAVE) - { - hspi->init.mode = SPI_MODE_SLAVER; - } - else - { - hspi->init.mode = SPI_MODE_MASTER; - } - if (cfg->mode & RT_SPI_3WIRE) - { - hspi->init.dir = SPI_DIRECTION_1LINE; - } - else - { - hspi->init.dir = SPI_DIRECTION_2LINES; - } - if (cfg->data_width == 8) - { - hspi->init.data_size = SPI_DATA_SIZE_8; - } - else if (cfg->data_width == 16) - { - hspi->init.data_size = SPI_DATA_SIZE_16; - } - - if (cfg->mode & RT_SPI_CPHA) - { - hspi->init.phase = SPI_CPHA_SECOND; - } - else - { - hspi->init.phase = SPI_CPHA_FIRST; - } - if (cfg->mode & RT_SPI_CPOL) - { - hspi->init.polarity = SPI_CPOL_HIGH; - } - else - { - hspi->init.polarity = SPI_CPOL_LOW; - } - if (cfg->mode & RT_SPI_NO_CS) - { - hspi->init.ss_en = DISABLE; - } - else - { - hspi->init.ss_en = ENABLE; - } - - /* config spi clock */ - if (cfg->max_hz >= ald_cmu_get_pclk1_clock() / 2) - { - /* pclk1 max speed 48MHz, spi master max speed 10MHz */ - if (ald_cmu_get_pclk1_clock() / 2 <= 10000000) - { - hspi->init.baud = SPI_BAUD_2; - } - else if (ald_cmu_get_pclk1_clock() / 4 <= 10000000) - { - hspi->init.baud = SPI_BAUD_4; - } - else - { - hspi->init.baud = SPI_BAUD_8; - } - } - else if (cfg->max_hz >= ald_cmu_get_pclk1_clock() / 4) - { - /* pclk1 max speed 48MHz, spi master max speed 10MHz */ - if (ald_cmu_get_pclk1_clock() / 4 <= 10000000) - { - hspi->init.baud = SPI_BAUD_4; - } - else - { - hspi->init.baud = SPI_BAUD_8; - } - } - else if (cfg->max_hz >= ald_cmu_get_pclk1_clock() / 8) - { - hspi->init.baud = SPI_BAUD_8; - } - else if (cfg->max_hz >= ald_cmu_get_pclk1_clock() / 16) - { - hspi->init.baud = SPI_BAUD_16; - } - else if (cfg->max_hz >= ald_cmu_get_pclk1_clock() / 32) - { - hspi->init.baud = SPI_BAUD_32; - } - else if (cfg->max_hz >= ald_cmu_get_pclk1_clock() / 64) - { - hspi->init.baud = SPI_BAUD_64; - } - else if (cfg->max_hz >= ald_cmu_get_pclk1_clock() / 128) - { - hspi->init.baud = SPI_BAUD_128; - } - else - { - hspi->init.baud = SPI_BAUD_256; - } - ald_spi_init(hspi); - return RT_EOK; -} - -static rt_uint32_t spixfer(struct rt_spi_device *device, struct rt_spi_message *message) -{ - rt_err_t res; - spi_handle_t *hspi; - struct es32f0_hw_spi_cs *cs; - - RT_ASSERT(device != RT_NULL); - RT_ASSERT(device->bus != RT_NULL); - RT_ASSERT(device->bus->parent.user_data != RT_NULL); - - hspi = (spi_handle_t *)device->bus->parent.user_data; - cs = device->parent.user_data; - - if(message->send_buf != RT_NULL || message->recv_buf != RT_NULL) - { - /* send & receive */ - if ((message->send_buf != RT_NULL) && (message->recv_buf != RT_NULL)) - { - if (message->cs_take) - { - rt_pin_write(cs->pin, 0); - } - res = ald_spi_send_recv(hspi, (rt_uint8_t *)message->send_buf, (rt_uint8_t *)message->recv_buf, - (rt_int32_t)message->length, SPITIMEOUT); - if (message->cs_release) - { - rt_pin_write(cs->pin, 1); - } - if (res != RT_EOK) - return RT_ERROR; - } - else - { - /* only send data */ - if (message->recv_buf == RT_NULL) - { - if (message->cs_take) - { - rt_pin_write(cs->pin, 0); - } - res = ald_spi_send(hspi, (rt_uint8_t *)message->send_buf, (rt_int32_t)message->length, SPITIMEOUT); - if (message->cs_release) - { - rt_pin_write(cs->pin, 1); - } - if (res != RT_EOK) - return RT_ERROR; - } - /* only receive data */ - if (message->send_buf == RT_NULL) - { - if (message->cs_take) - { - rt_pin_write(cs->pin, 0); - } - res = ald_spi_recv(hspi, (rt_uint8_t *)message->recv_buf, (rt_int32_t)message->length, SPITIMEOUT); - if (message->cs_release) - { - rt_pin_write(cs->pin, 1); - } - if (res != RT_EOK) - return RT_ERROR; - } - } - - } - else - { - if (message->cs_take) - { - rt_pin_write(cs->pin, 0); - } - - if (message->cs_release) - { - rt_pin_write(cs->pin, 1); - } - return RT_EOK; - } - return message->length; - -} - -const struct rt_spi_ops es32f0_spi_ops = -{ - spi_configure, - spixfer, -}; - - -rt_err_t es32f0_spi_device_attach(rt_uint32_t pin, const char *bus_name, const char *device_name) -{ - /* define spi Instance */ - struct rt_spi_device *spi_device = (struct rt_spi_device *)rt_malloc(sizeof(struct rt_spi_device)); - RT_ASSERT(spi_device != RT_NULL); - struct es32f0_hw_spi_cs *cs_pin = (struct es32f0_hw_spi_cs *)rt_malloc(sizeof(struct es32f0_hw_spi_cs)); - RT_ASSERT(cs_pin != RT_NULL); - cs_pin->pin = pin; - rt_pin_mode(pin, PIN_MODE_OUTPUT); - rt_pin_write(pin, 1); - return rt_spi_bus_attach_device(spi_device, device_name, bus_name, (void *)cs_pin); -} - -#ifdef BSP_USING_SPI0 - static struct rt_spi_bus _spi_bus0; - static spi_handle_t _spi0; -#endif - -#ifdef BSP_USING_SPI1 - static struct rt_spi_bus _spi_bus1; - static spi_handle_t _spi1; -#endif - -int rt_hw_spi_init(void) -{ - int result = RT_EOK; - - struct rt_spi_bus *spi_bus; - spi_handle_t *spi; - gpio_init_t gpio_instruct; - -#ifdef BSP_USING_SPI0 - _spi0.perh = SPI0; - spi_bus = &_spi_bus0; - spi = &_spi0; - rt_device_t spi_bus_dev0; - - /* SPI0 gpio init */ - gpio_instruct.mode = GPIO_MODE_OUTPUT; - gpio_instruct.odos = GPIO_PUSH_PULL; - gpio_instruct.func = GPIO_FUNC_4; - gpio_instruct.type = GPIO_TYPE_CMOS; - gpio_instruct.flt = GPIO_FILTER_DISABLE; - - /* PB3->SPI0_SCK, PB5->SPI0_MOSI */ - ald_gpio_init(GPIOB, GPIO_PIN_3 | GPIO_PIN_5, &gpio_instruct); - - /* PB4->SPI0_MISO */ - gpio_instruct.mode = GPIO_MODE_INPUT; - ald_gpio_init(GPIOB, GPIO_PIN_4, &gpio_instruct); - - spi_bus->parent.user_data = spi; - result = rt_spi_bus_register(spi_bus, "spi0", &es32f0_spi_ops); - if (result != RT_EOK) - { - return result; - } - - rt_device_register(spi_bus_dev0, "spi00", RT_DEVICE_FLAG_RDWR); - - /* SPI0_NSS = PA15 = PIN 50 */ - result = es32f0_spi_device_attach(50, "spi0", "spi00"); - - if (result != RT_EOK) - { - return result; - } - -#endif - -#ifdef BSP_USING_SPI1 - _spi1.perh = SPI1; - spi_bus = &_spi_bus1; - spi = &_spi1; - rt_device_t spi_bus_dev0; - - /* SPI1 gpio init */ - gpio_instruct.mode = GPIO_MODE_OUTPUT; - gpio_instruct.odos = GPIO_PUSH_PULL; - gpio_instruct.func = GPIO_FUNC_4; - gpio_instruct.type = GPIO_TYPE_CMOS; - gpio_instruct.flt = GPIO_FILTER_DISABLE; - - /* PB13->SPI1_SCK, PB15->SPI1_MOSI */ - ald_gpio_init(GPIOB, GPIO_PIN_13 | GPIO_PIN_15, &gpio_instruct); - - /* PB14->SPI1_MISO */ - gpio_instruct.mode = GPIO_MODE_INPUT; - ald_gpio_init(GPIOB, GPIO_PIN_14, &gpio_instruct); - - spi_bus->parent.user_data = spi; - result = rt_spi_bus_register(spi_bus, "spi1", &es32f0_spi_ops); - if (result != RT_EOK) - { - return result; - } - - rt_device_register(spi_bus_dev0, "spi10", RT_DEVICE_FLAG_RDWR); - - /* SPI1_NSS = PC00 = PIN 8 */ - result = es32f0_spi_device_attach(8, "spi1", "spi10"); - - if (result != RT_EOK) - { - return result; - } - -#endif - - return result; -} -INIT_BOARD_EXPORT(rt_hw_spi_init); - -#endif diff --git a/bsp/essemi/es32f0334/drivers/drv_spi.h b/bsp/essemi/es32f0334/drivers/drv_spi.h deleted file mode 100644 index 08e36431aa..0000000000 --- a/bsp/essemi/es32f0334/drivers/drv_spi.h +++ /dev/null @@ -1,27 +0,0 @@ -/* - * Copyright (C) 2018 Shanghai Eastsoft Microelectronics Co., Ltd. - * - * SPDX-License-Identifier: Apache-2.0 - * - * Change Logs: - * Date Author Notes - * 2019-03-19 wangyq the first version - */ - -#ifndef DRV_SPI_H__ -#define DRV_SPI_H__ - -#include -#include -#include - -struct es32f0_hw_spi_cs -{ - rt_uint32_t pin; -}; - -/* cannot be used before completion init */ -rt_err_t es32f0_spi_device_attach(rt_uint32_t pin, const char *bus_name, const char *device_name); -int rt_hw_spi_init(void); - -#endif diff --git a/bsp/essemi/es32f0334/drivers/drv_spiflash.c b/bsp/essemi/es32f0334/drivers/drv_spiflash.c deleted file mode 100644 index 9173e81ca3..0000000000 --- a/bsp/essemi/es32f0334/drivers/drv_spiflash.c +++ /dev/null @@ -1,32 +0,0 @@ -/* - * Copyright (C) 2018 Shanghai Eastsoft Microelectronics Co., Ltd. - * - * SPDX-License-Identifier: Apache-2.0 - * - * Change Logs: - * Date Author Notes - * 2019-03-19 wangyq the first version - * 2019-11-01 wangyq update libraries - */ - -#include -#include "spi_flash.h" -#include "drv_spiflash.h" -#include "spi_flash_sfud.h" -#include "drv_spi.h" - -#if defined(BSP_USING_SPI_FLASH) -int rt_hw_spi_flash_init(void) -{ - es32f0_spi_device_attach(50, "spi0", "spi00"); - - if (RT_NULL == rt_sfud_flash_probe("W25Q64", "spi00")) - { - return -RT_ERROR; - }; - - return RT_EOK; -} -INIT_COMPONENT_EXPORT(rt_hw_spi_flash_init); - -#endif diff --git a/bsp/essemi/es32f0334/drivers/drv_spiflash.h b/bsp/essemi/es32f0334/drivers/drv_spiflash.h deleted file mode 100644 index f578d2e48f..0000000000 --- a/bsp/essemi/es32f0334/drivers/drv_spiflash.h +++ /dev/null @@ -1,16 +0,0 @@ -/* - * Copyright (C) 2018 Shanghai Eastsoft Microelectronics Co., Ltd. - * - * SPDX-License-Identifier: Apache-2.0 - * - * Change Logs: - * Date Author Notes - * 2019-03-19 wangyq the first version - */ - -#ifndef DRV_NOR_FLASH_H__ -#define DRV_NOR_FLASH_H__ - -int rt_hw_spi_flash_init(void); - -#endif diff --git a/bsp/essemi/es32f0334/drivers/drv_uart.c b/bsp/essemi/es32f0334/drivers/drv_uart.c deleted file mode 100644 index a7fb0deee4..0000000000 --- a/bsp/essemi/es32f0334/drivers/drv_uart.c +++ /dev/null @@ -1,236 +0,0 @@ -/* - * Copyright (C) 2018 Shanghai Eastsoft Microelectronics Co., Ltd. - * - * SPDX-License-Identifier: Apache-2.0 - * - * Change Logs: - * Date Author Notes - * 2019-03-01 wangyq the first version - * 2019-11-01 wangyq update libraries - */ - -#include -#include -#include -#include "board.h" -#include "drv_uart.h" -#include -#include - -#ifdef RT_USING_SERIAL - -/* es32 uart driver */ -struct es32_uart -{ - uart_handle_t huart; - IRQn_Type irq; -}; - -static rt_err_t es32f0x_configure(struct rt_serial_device *serial, struct serial_configure *cfg) -{ - gpio_init_t gpio_init_initstructure; - struct es32_uart *uart; - RT_ASSERT(serial != RT_NULL); - RT_ASSERT(cfg != RT_NULL); - uart = (struct es32_uart *)serial->parent.user_data; - - /* Initialize tx pin */ - gpio_init_initstructure.mode = GPIO_MODE_OUTPUT; - gpio_init_initstructure.odos = GPIO_PUSH_PULL; - gpio_init_initstructure.pupd = GPIO_PUSH_UP; - gpio_init_initstructure.odrv = GPIO_OUT_DRIVE_NORMAL; - gpio_init_initstructure.flt = GPIO_FILTER_DISABLE; - gpio_init_initstructure.type = GPIO_TYPE_TTL; - -#ifdef BSP_USING_UART0 - gpio_init_initstructure.func = GPIO_FUNC_3; - ald_gpio_init(GPIOB, GPIO_PIN_10, &gpio_init_initstructure); - - /* Initialize rx pin ,the same as txpin except mode */ - gpio_init_initstructure.mode = GPIO_MODE_INPUT; - ald_gpio_init(GPIOB, GPIO_PIN_11, &gpio_init_initstructure); -#endif - -#ifdef BSP_USING_UART1 - /* Initialize tx pin */ - gpio_init_initstructure.func = GPIO_FUNC_3; - ald_gpio_init(GPIOC, GPIO_PIN_10, &gpio_init_initstructure); - - /* Initialize rx pin ,the same as txpin except mode*/ - gpio_init_initstructure.mode = GPIO_MODE_INPUT; - ald_gpio_init(GPIOC, GPIO_PIN_11, &gpio_init_initstructure); -#endif - - uart->huart.init.mode = UART_MODE_UART; - uart->huart.init.baud = cfg->baud_rate; - uart->huart.init.word_length = (uart_word_length_t)(cfg->data_bits - 5); - uart->huart.init.parity = (uart_parity_t)(cfg->parity == PARITY_EVEN ? UART_PARITY_EVEN : cfg->parity); - uart->huart.init.fctl = UART_HW_FLOW_CTL_DISABLE; - ald_uart_init(&uart->huart); - - if (cfg->bit_order == BIT_ORDER_MSB) - { - UART_MSB_FIRST_ENABLE(&uart->huart); - } - else - { - UART_MSB_FIRST_DISABLE(&uart->huart); - } - - if (cfg->invert == NRZ_INVERTED) - { - UART_DATA_INV_ENABLE(&uart->huart); - } - else - { - UART_DATA_INV_DISABLE(&uart->huart); - } - - /* enable rx int */ - ald_uart_interrupt_config(&uart->huart, UART_IT_RXRD, ENABLE); - - return RT_EOK; -} - -static rt_err_t es32f0x_control(struct rt_serial_device *serial, int cmd, void *arg) -{ - struct es32_uart *uart; - RT_ASSERT(serial != RT_NULL); - - uart = (struct es32_uart *)serial->parent.user_data; - switch (cmd) - { - case RT_DEVICE_CTRL_CLR_INT: - /* disable rx irq */ - NVIC_DisableIRQ(uart->irq); - /* disable interrupt */ - ald_uart_interrupt_config(&uart->huart, UART_IT_RXRD, DISABLE); - break; - - case RT_DEVICE_CTRL_SET_INT: - /* enable rx irq */ - NVIC_EnableIRQ(uart->irq); - /* enable interrupt */ - ald_uart_interrupt_config(&uart->huart, UART_IT_RXRD, ENABLE); - break; - } - - return RT_EOK; -} - -static int es32f0x_putc(struct rt_serial_device *serial, char c) -{ - struct es32_uart *uart; - RT_ASSERT(serial != RT_NULL); - uart = (struct es32_uart *)serial->parent.user_data; - - while (!(uart->huart.perh->SR & 0x40)) ; - WRITE_REG(uart->huart.perh->TBR, c); - - return 1; -} - -static int es32f0x_getc(struct rt_serial_device *serial) -{ - int ch = -1; - struct es32_uart *uart; - - RT_ASSERT(serial != RT_NULL); - uart = (struct es32_uart *)serial->parent.user_data; - - if (uart->huart.perh->SR & 0x01) - { - ch = (uint8_t)(uart->huart.perh->RBR & 0xFF); - } - - return ch; -} - -static const struct rt_uart_ops es32f0x_uart_ops = -{ - es32f0x_configure, - es32f0x_control, - es32f0x_putc, - es32f0x_getc, -}; - -#ifdef BSP_USING_UART0 -/* UART0 device driver structure */ -struct es32_uart uart0 = -{ - {UART0}, - UART0_IRQn -}; - -struct rt_serial_device serial0; - -void UART0_Handler(void) -{ - /* enter interrupt */ - rt_interrupt_enter(); - - if (UART0->RIF & 0x01) - { - rt_hw_serial_isr(&serial0, RT_SERIAL_EVENT_RX_IND); - } - /* leave interrupt */ - rt_interrupt_leave(); -} -#endif /* BSP_USING_UART0 */ - -#ifdef BSP_USING_UART1 -/* UART1 device driver structure */ -struct es32_uart uart1 = -{ - {UART1}, - UART1_IRQn -}; - -struct rt_serial_device serial1; - -void UART1_Handler(void) -{ - /* enter interrupt */ - rt_interrupt_enter(); - - if (UART1->RIF & 0x01) - { - rt_hw_serial_isr(&serial1, RT_SERIAL_EVENT_RX_IND); - } - /* leave interrupt */ - rt_interrupt_leave(); -} -#endif /* BSP_USING_UART1 */ - -int rt_hw_uart_init(void) -{ - struct es32_uart *uart; - struct serial_configure config = RT_SERIAL_CONFIG_DEFAULT; - -#ifdef BSP_USING_UART0 - uart = &uart0; - serial0.ops = &es32f0x_uart_ops; - serial0.config = config; - - /* register UART0 device */ - rt_hw_serial_register(&serial0, "uart0", - RT_DEVICE_FLAG_RDWR | RT_DEVICE_FLAG_INT_RX, - uart); -#endif /* BSP_USING_UART0 */ - -#ifdef BSP_USING_UART1 - uart = &uart1; - serial1.ops = &es32f0x_uart_ops; - serial1.config = config; - - /* register UART1 device */ - rt_hw_serial_register(&serial1, "uart1", - RT_DEVICE_FLAG_RDWR | RT_DEVICE_FLAG_INT_RX, - uart); -#endif /* BSP_USING_UART1 */ - - return 0; -} -INIT_BOARD_EXPORT(rt_hw_uart_init); - -#endif diff --git a/bsp/essemi/es32f0334/drivers/drv_uart.h b/bsp/essemi/es32f0334/drivers/drv_uart.h deleted file mode 100644 index 6007188c2b..0000000000 --- a/bsp/essemi/es32f0334/drivers/drv_uart.h +++ /dev/null @@ -1,16 +0,0 @@ -/* - * Copyright (C) 2018 Shanghai Eastsoft Microelectronics Co., Ltd. - * - * SPDX-License-Identifier: Apache-2.0 - * - * Change Logs: - * Date Author Notes - * 2019-03-01 wangyq the first version - */ - -#ifndef DRV_UART_H__ -#define DRV_UART_H__ - -int rt_hw_uart_init(void); - -#endif diff --git a/bsp/essemi/es32f0334/drivers/linker_scripts/link.sct b/bsp/essemi/es32f0334/drivers/linker_scripts/link.sct deleted file mode 100644 index 45489c5687..0000000000 --- a/bsp/essemi/es32f0334/drivers/linker_scripts/link.sct +++ /dev/null @@ -1,15 +0,0 @@ -; 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### uVision Project, (C) Keil Software
- - - - rt-thread - 0x4 - ARM-ADS - 5060750::V5.06 update 6 (build 750)::ARMCC - 0 - - - ES32F0334LT - Eastsoft - Eastsoft.ES32_DFP.7.2350 - http://www.essemi.com - IRAM(0x20000000,0x00008000) IROM(0x00000000,0x00040000) CPUTYPE("Cortex-M0") CLOCK(12000000) ELITTLE - - - UL2CM3(-S0 -C0 -P0 -FD20000000 -FC1000 -FN1 -FF0ES32F033x -FS00 -FL040000 -FP0($$Device:ES32F0334LT$Flash\ES32F033x.FLM)) - 0 - $$Device:ES32F0334LT$Device\Include\es32f033x.h - - - - - - - - - - $$Device:ES32F0334LT$SVD\es32f0xx.svd - 0 - 0 - - - - - - - 0 - 0 - 0 - 0 - 1 - - .\build\keil\ - rtthread - 1 - 0 - 0 - 1 - 1 - .\build\keil\ - 1 - 0 - 0 - - 0 - 0 - - - 0 - 0 - 0 - 0 - - - 0 - 0 - - - 0 - 0 - 0 - 0 - - - 1 - 0 - fromelf --bin !L --output rtthread.bin - - 0 - 0 - 0 - 0 - - 0 - - - - 0 - 0 - 0 - 0 - 0 - 1 - 0 - 0 - 0 - 0 - 3 - - - 1 - - - SARMCM3.DLL - -MPU - DARMCM1.DLL - -pCM0 - SARMCM3.DLL - -MPU - TARMCM1.DLL - -pCM0 - - - - 1 - 0 - 0 - 0 - 16 - - - - - 1 - 0 - 0 - 1 - 1 - 4096 - - 1 - BIN\UL2CM3.DLL - "" () - - - - - 0 - - - - 0 - 1 - 1 - 1 - 1 - 1 - 1 - 1 - 0 - 1 - 1 - 0 - 1 - 1 - 0 - 0 - 1 - 1 - 1 - 1 - 1 - 1 - 1 - 1 - 1 - 0 - 0 - "Cortex-M0" - - 0 - 0 - 0 - 1 - 1 - 0 - 0 - 0 - 0 - 0 - 0 - 8 - 0 - 0 - 0 - 0 - 3 - 3 - 0 - 0 - 0 - 0 - 0 - 0 - 0 - 0 - 0 - 0 - 1 - 0 - 0 - 0 - 0 - 1 - 0 - - - 0 - 0x0 - 0x0 - - - 0 - 0x0 - 0x0 - - - 0 - 0x0 - 0x0 - - - 0 - 0x0 - 0x0 - - - 0 - 0x0 - 0x0 - - - 0 - 0x0 - 0x0 - - - 0 - 0x20000000 - 0x8000 - - - 1 - 0x0 - 0x40000 - - - 0 - 0x0 - 0x0 - - - 1 - 0x0 - 0x0 - - - 1 - 0x0 - 0x0 - - - 1 - 0x0 - 0x0 - - - 1 - 0x0 - 0x40000 - - - 1 - 0x0 - 0x0 - - - 0 - 0x0 - 0x0 - - - 0 - 0x0 - 0x0 - - - 0 - 0x0 - 0x0 - - - 0 - 0x20000000 - 0x8000 - - - 0 - 0x0 - 0x0 - - - - - - 1 - 1 - 0 - 0 - 1 - 0 - 0 - 0 - 0 - 0 - 0 - 0 - 0 - 1 - 0 - 0 - 1 - 1 - 1 - 1 - 0 - 0 - 0 - - - ES32F033x - - applications;.;drivers;..\..\..\libcpu\arm\common;..\..\..\libcpu\arm\cortex-m0;..\..\..\components\drivers\include;..\..\..\components\drivers\include;..\..\..\components\drivers\include;..\..\..\components\drivers\include;..\..\..\components\drivers\include;..\..\..\components\drivers\include;..\..\..\components\drivers\spi;..\..\..\components\drivers\include;..\..\..\components\drivers\include;drivers;..\..\..\components\finsh;.;..\..\..\include;libraries\CMSIS\Device\EastSoft\es32f033x\Include;libraries\CMSIS\Include;libraries\ES32F033x_ALD_StdPeriph_Driver\Include - - - - 1 - 0 - 0 - 0 - 0 - 0 - 0 - 0 - 0 - 0 - - - - - - - - - 1 - 0 - 0 - 0 - 1 - 0 - 0x08000000 - 0x20000000 - - - - - - - - - - - - - Applications - - - main.c - 1 - applications\main.c - - - - - cpu - - - backtrace.c - 1 - ..\..\..\libcpu\arm\common\backtrace.c - - - div0.c - 1 - ..\..\..\libcpu\arm\common\div0.c - - - showmem.c - 1 - ..\..\..\libcpu\arm\common\showmem.c - - - cpuport.c - 1 - ..\..\..\libcpu\arm\cortex-m0\cpuport.c - - - context_rvds.S - 2 - ..\..\..\libcpu\arm\cortex-m0\context_rvds.S - - - - - DeviceDrivers - - - 0 - 0 - 0 - 0 - 0 - 1 - 0 - 0 - 0 - 0 - 3 - - - 0 - - - - 2 - 0 - 2 - 2 - 2 - 2 - 2 - 2 - 2 - 2 - 0 - 2 - 2 - 2 - 2 - 2 - 0 - 0 - 2 - 2 - 2 - 2 - 2 - - - - - - - - - 2 - 2 - 2 - 2 - 2 - 2 - 2 - 2 - 2 - 2 - - - - - - - - - - - - hwtimer.c - 1 - ..\..\..\components\drivers\hwtimer\hwtimer.c - - - i2c_core.c - 1 - ..\..\..\components\drivers\i2c\i2c_core.c - - - i2c_dev.c - 1 - ..\..\..\components\drivers\i2c\i2c_dev.c - - - i2c-bit-ops.c - 1 - ..\..\..\components\drivers\i2c\i2c-bit-ops.c - - - pin.c - 1 - ..\..\..\components\drivers\misc\pin.c - - - adc.c - 1 - ..\..\..\components\drivers\misc\adc.c - - - rt_drv_pwm.c - 1 - ..\..\..\components\drivers\misc\rt_drv_pwm.c - - - pm.c - 1 - ..\..\..\components\drivers\pm\pm.c - - - rtc.c - 1 - ..\..\..\components\drivers\rtc\rtc.c - - - serial.c - 1 - ..\..\..\components\drivers\serial\serial.c - - - spi_core.c - 1 - ..\..\..\components\drivers\spi\spi_core.c - - - spi_dev.c - 1 - ..\..\..\components\drivers\spi\spi_dev.c - - - completion.c - 1 - ..\..\..\components\drivers\src\completion.c - - - dataqueue.c - 1 - ..\..\..\components\drivers\src\dataqueue.c - - - pipe.c - 1 - ..\..\..\components\drivers\src\pipe.c - - - ringblk_buf.c - 1 - ..\..\..\components\drivers\src\ringblk_buf.c - - - ringbuffer.c - 1 - ..\..\..\components\drivers\src\ringbuffer.c - - - waitqueue.c - 1 - ..\..\..\components\drivers\src\waitqueue.c - - - workqueue.c - 1 - ..\..\..\components\drivers\src\workqueue.c - - - - - Drivers - - - board.c - 1 - drivers\board.c - - - drv_gpio.c - 1 - drivers\drv_gpio.c - - - drv_uart.c - 1 - drivers\drv_uart.c - - - - - finsh - - - shell.c - 1 - ..\..\..\components\finsh\shell.c - - - cmd.c - 1 - ..\..\..\components\finsh\cmd.c - - - msh.c - 1 - ..\..\..\components\finsh\msh.c - - - - - Kernel - - - clock.c - 1 - ..\..\..\src\clock.c - - - components.c - 1 - ..\..\..\src\components.c - - - device.c - 1 - ..\..\..\src\device.c - - - idle.c - 1 - ..\..\..\src\idle.c - - - ipc.c - 1 - ..\..\..\src\ipc.c - - - irq.c - 1 - ..\..\..\src\irq.c - - - kservice.c - 1 - ..\..\..\src\kservice.c - - - mem.c - 1 - ..\..\..\src\mem.c - - - mempool.c - 1 - ..\..\..\src\mempool.c - - - object.c - 1 - ..\..\..\src\object.c - - - scheduler.c - 1 - ..\..\..\src\scheduler.c - - - signal.c - 1 - ..\..\..\src\signal.c - - - thread.c - 1 - ..\..\..\src\thread.c - - - timer.c - 1 - ..\..\..\src\timer.c - - - - - Libraries - - - ald_acmp.c - 1 - libraries\ES32F033x_ALD_StdPeriph_Driver\Source\ald_acmp.c - - - ald_adc.c - 1 - libraries\ES32F033x_ALD_StdPeriph_Driver\Source\ald_adc.c - - - ald_bkpc.c - 1 - libraries\ES32F033x_ALD_StdPeriph_Driver\Source\ald_bkpc.c - - - ald_calc.c - 1 - libraries\ES32F033x_ALD_StdPeriph_Driver\Source\ald_calc.c - - - ald_cmu.c - 1 - libraries\ES32F033x_ALD_StdPeriph_Driver\Source\ald_cmu.c - - - ald_crc.c - 1 - libraries\ES32F033x_ALD_StdPeriph_Driver\Source\ald_crc.c - - - ald_crypt.c - 1 - libraries\ES32F033x_ALD_StdPeriph_Driver\Source\ald_crypt.c - - - ald_dma.c - 1 - libraries\ES32F033x_ALD_StdPeriph_Driver\Source\ald_dma.c - - - ald_flash.c - 1 - libraries\ES32F033x_ALD_StdPeriph_Driver\Source\ald_flash.c - - - ald_flash_ext.c - 1 - libraries\ES32F033x_ALD_StdPeriph_Driver\Source\ald_flash_ext.c - - - ald_gpio.c - 1 - libraries\ES32F033x_ALD_StdPeriph_Driver\Source\ald_gpio.c - - - ald_i2c.c - 1 - libraries\ES32F033x_ALD_StdPeriph_Driver\Source\ald_i2c.c - - - ald_iap.c - 1 - libraries\ES32F033x_ALD_StdPeriph_Driver\Source\ald_iap.c - - - ald_lcd.c - 1 - libraries\ES32F033x_ALD_StdPeriph_Driver\Source\ald_lcd.c - - - ald_lptim.c - 1 - libraries\ES32F033x_ALD_StdPeriph_Driver\Source\ald_lptim.c - - - ald_lpuart.c - 1 - libraries\ES32F033x_ALD_StdPeriph_Driver\Source\ald_lpuart.c - - - ald_pis.c - 1 - libraries\ES32F033x_ALD_StdPeriph_Driver\Source\ald_pis.c - - - ald_pmu.c - 1 - libraries\ES32F033x_ALD_StdPeriph_Driver\Source\ald_pmu.c - - - ald_rmu.c - 1 - libraries\ES32F033x_ALD_StdPeriph_Driver\Source\ald_rmu.c - - - ald_rtc.c - 1 - libraries\ES32F033x_ALD_StdPeriph_Driver\Source\ald_rtc.c - - - ald_smartcard.c - 1 - libraries\ES32F033x_ALD_StdPeriph_Driver\Source\ald_smartcard.c - - - ald_spi.c - 1 - libraries\ES32F033x_ALD_StdPeriph_Driver\Source\ald_spi.c - - - ald_timer.c - 1 - libraries\ES32F033x_ALD_StdPeriph_Driver\Source\ald_timer.c - - - ald_trng.c - 1 - libraries\ES32F033x_ALD_StdPeriph_Driver\Source\ald_trng.c - - - ald_tsense.c - 1 - libraries\ES32F033x_ALD_StdPeriph_Driver\Source\ald_tsense.c - - - ald_uart.c - 1 - libraries\ES32F033x_ALD_StdPeriph_Driver\Source\ald_uart.c - - - ald_usart.c - 1 - libraries\ES32F033x_ALD_StdPeriph_Driver\Source\ald_usart.c - - - ald_wdt.c - 1 - libraries\ES32F033x_ALD_StdPeriph_Driver\Source\ald_wdt.c - - - utils.c - 1 - libraries\ES32F033x_ALD_StdPeriph_Driver\Source\utils.c - - - startup_es32f033x.s - 2 - libraries\CMSIS\Device\EastSoft\es32f033x\Startup\keil\startup_es32f033x.s - - - - - - - - - - - - - - diff --git a/bsp/essemi/es32f0334/rtconfig.h b/bsp/essemi/es32f0334/rtconfig.h deleted file mode 100644 index 7354c8d7d8..0000000000 --- a/bsp/essemi/es32f0334/rtconfig.h +++ /dev/null @@ -1,195 +0,0 @@ -#ifndef RT_CONFIG_H__ -#define RT_CONFIG_H__ - -/* Automatically generated file; DO NOT EDIT. */ -/* RT-Thread Configuration */ - -/* RT-Thread Kernel */ - -#define RT_NAME_MAX 8 -#define RT_ALIGN_SIZE 4 -#define RT_THREAD_PRIORITY_32 -#define RT_THREAD_PRIORITY_MAX 32 -#define RT_TICK_PER_SECOND 100 -#define RT_USING_OVERFLOW_CHECK -#define RT_USING_HOOK -#define RT_USING_IDLE_HOOK -#define RT_IDLE_HOOK_LIST_SIZE 4 -#define IDLE_THREAD_STACK_SIZE 256 -#define RT_DEBUG -#define RT_DEBUG_COLOR - -/* Inter-Thread communication */ - -#define RT_USING_SEMAPHORE -#define RT_USING_MUTEX -#define RT_USING_EVENT -#define RT_USING_MAILBOX -#define RT_USING_MESSAGEQUEUE - -/* Memory Management */ - -#define RT_USING_MEMPOOL -#define RT_USING_SMALL_MEM -#define RT_USING_HEAP - -/* Kernel Device Object */ - -#define RT_USING_DEVICE -#define RT_USING_CONSOLE -#define RT_CONSOLEBUF_SIZE 128 -#define RT_CONSOLE_DEVICE_NAME "uart1" -#define RT_VER_NUM 0x40003 - -/* RT-Thread Components */ - -#define RT_USING_COMPONENTS_INIT -#define RT_USING_USER_MAIN -#define RT_MAIN_THREAD_STACK_SIZE 2048 -#define RT_MAIN_THREAD_PRIORITY 10 - -/* C++ features */ - - -/* Command shell */ - -#define RT_USING_FINSH -#define FINSH_THREAD_NAME "tshell" -#define FINSH_USING_HISTORY -#define FINSH_HISTORY_LINES 5 -#define FINSH_USING_SYMTAB -#define FINSH_USING_DESCRIPTION -#define FINSH_THREAD_PRIORITY 20 -#define FINSH_THREAD_STACK_SIZE 4096 -#define FINSH_CMD_SIZE 80 -#define FINSH_USING_MSH -#define FINSH_USING_MSH_DEFAULT -#define FINSH_USING_MSH_ONLY -#define FINSH_ARG_MAX 10 - -/* Device virtual file system */ - - -/* Device Drivers */ - -#define RT_USING_DEVICE_IPC -#define RT_PIPE_BUFSZ 512 -#define RT_USING_SERIAL -#define RT_SERIAL_RB_BUFSZ 64 -#define RT_USING_HWTIMER -#define RT_USING_I2C -#define RT_USING_I2C_BITOPS -#define RT_USING_PIN -#define RT_USING_ADC -#define RT_USING_PWM -#define RT_USING_PM -#define RT_USING_RTC -#define RT_USING_SPI - -/* Using USB */ - - -/* POSIX layer and C standard library */ - - -/* Network */ - -/* Socket abstraction layer */ - - -/* Network interface device */ - - -/* light weight TCP/IP stack */ - - -/* AT commands */ - - -/* VBUS(Virtual Software BUS) */ - - -/* Utilities */ - - -/* RT-Thread online packages */ - -/* IoT - internet of things */ - - -/* Wi-Fi */ - -/* Marvell WiFi */ - - -/* Wiced WiFi */ - - -/* IoT Cloud */ - - -/* security packages */ - - -/* language packages */ - - -/* multimedia packages */ - - -/* tools packages */ - - -/* system packages */ - - -/* peripheral libraries and drivers */ - - -/* miscellaneous packages */ - - -/* samples: kernel and components samples */ - - -/* Hardware Drivers Config */ - -/* On-chip Peripheral Drivers */ - -#define BSP_USING_GPIO - -/* UART Drivers */ - -#define BSP_USING_UART1 - -/* SPI Drivers */ - - -/* I2C Drivers */ - - -/* PWM Drivers */ - - -/* HWtimer Drivers */ - - -/* RTC Drivers */ - - -/* PM Drivers */ - - -/* ADC Drivers */ - - -/* Onboard Peripheral Drivers */ - - -/* Offboard Peripheral Drivers */ - -/* Peripheral Drivers test example */ - -#define SOC_ES32F0334LT - -#endif diff --git a/bsp/essemi/es32f0334/rtconfig.py b/bsp/essemi/es32f0334/rtconfig.py deleted file mode 100644 index eb371bf3a7..0000000000 --- a/bsp/essemi/es32f0334/rtconfig.py +++ /dev/null @@ -1,135 +0,0 @@ -import os -import sys - -# toolchains options -CROSS_TOOL = 'keil' - -if os.getenv('RTT_CC'): - CROSS_TOOL = os.getenv('RTT_CC') - -# device options -ARCH = 'arm' -CPU = 'cortex-m0' - -# cross_tool provides the cross compiler -# EXEC_PATH is the compiler execute path, for example, CodeSourcery, Keil MDK, IAR -if CROSS_TOOL == 'gcc': # not support gcc yet - PLATFORM = 'gcc' - EXEC_PATH = 'C:/GCC' - -elif CROSS_TOOL == 'keil': - PLATFORM = 'armcc' - EXEC_PATH = 'C:/Keil' - -elif CROSS_TOOL == 'iar': # not support iar yet - PLATFORM = 'iar' - EXEC_PATH = 'C:/IAR' - -if os.getenv('RTT_EXEC_PATH'): - EXEC_PATH = os.getenv('RTT_EXEC_PATH') - -BUILD = 'debug' -#BUILD = 'release' - -if PLATFORM == 'gcc': - # toolchains - PREFIX = 'arm-none-eabi-' - CC = PREFIX + 'gcc' - CXX = PREFIX + 'g++' - AS = PREFIX + 'gcc' - AR = PREFIX + 'ar' - LINK = PREFIX + 'gcc' - TARGET_EXT = 'elf' - SIZE = PREFIX + 'size' - OBJDUMP = PREFIX + 'objdump' - OBJCPY = PREFIX + 'objcopy' - DEVICE = ' -mcpu=' + CPU + ' -mthumb -ffunction-sections -fdata-sections' - CFLAGS = DEVICE - AFLAGS = ' -c' + DEVICE + ' -x assembler-with-cpp -Wa,-mimplicit-it=thumb' - LFLAGS = DEVICE + ' -Wl,--gc-sections,-Map=rtthread.map,-cref,-u,Reset_Handler -T drivers/linker_scripts/link.lds' - - CPATH = '' - LPATH = '' - - if BUILD == 'debug': - CFLAGS += ' -O0 -gdwarf-2 -g' - AFLAGS += ' -gdwarf-2' - else: - CFLAGS += ' -O2' - - POST_ACTION = OBJCPY + ' -O binary $TARGET rtthread.bin\n' + OBJCPY + ' -O ihex $TARGET rtthread.hex\n' + SIZE + ' $TARGET \n' -elif PLATFORM == 'armcc': - # toolchains - CC = 'armcc' - AS = 'armasm' - AR = 'armar' - LINK = 'armlink' - TARGET_EXT = 'axf' - - DEVICE = ' --device DARMSTM' - CFLAGS = '-c ' + DEVICE + ' --apcs=interwork --c99' - AFLAGS = DEVICE + ' --apcs=interwork ' - LFLAGS = DEVICE + ' --scatter "drivers/linker_scripts/link.sct" --info sizes --info totals --info unused --info veneers --list rtthread.map --strict' - - CFLAGS += ' -I' + EXEC_PATH + '/ARM/ARMCC/include' - LFLAGS += ' --libpath ' + EXEC_PATH + '/ARM/ARMCC/lib' - - CFLAGS += ' -D__MICROLIB ' - AFLAGS += ' --pd "__MICROLIB SETA 1" ' - LFLAGS += ' --library_type=microlib ' - EXEC_PATH += '/ARM/ARMCC/bin' - - if BUILD == 'debug': - CFLAGS += ' -g -O0' - AFLAGS += ' -g' - else: - CFLAGS += ' -O2' - - POST_ACTION = 'fromelf --bin $TARGET --output rtthread.bin \nfromelf -z $TARGET' - -elif PLATFORM == 'iar': - # toolchains - CC = 'iccarm' - AS = 'iasmarm' - AR = 'iarchive' - LINK = 'ilinkarm' - TARGET_EXT = 'out' - - DEVICE = '-Dewarm' - - CFLAGS = DEVICE - CFLAGS += ' --diag_suppress Pa050' - CFLAGS += ' --no_cse' - CFLAGS += ' --no_unroll' - CFLAGS += ' --no_inline' - CFLAGS += ' --no_code_motion' - CFLAGS += ' --no_tbaa' - CFLAGS += ' --no_clustering' - CFLAGS += ' --no_scheduling' - CFLAGS += ' --endian=little' - CFLAGS += ' --cpu=Cortex-M0' - CFLAGS += ' -e' - CFLAGS += ' --fpu=None' - CFLAGS += ' --dlib_config "' + EXEC_PATH + '/arm/INC/c/DLib_Config_Normal.h"' - CFLAGS += ' --silent' - - AFLAGS = DEVICE - AFLAGS += ' -s+' - AFLAGS += ' -w+' - AFLAGS += ' -r' - AFLAGS += ' --cpu Cortex-M0' - AFLAGS += ' --fpu None' - AFLAGS += ' -S' - - LFLAGS = ' --config "drivers\linker_scripts\link.icf"' - LFLAGS += ' --redirect _Printf=_PrintfTiny' - LFLAGS += ' --redirect _Scanf=_ScanfSmall' - if BUILD == 'debug': - CFLAGS += ' --debug' - CFLAGS += ' -On' - else: - CFLAGS += ' -Oh' - - LFLAGS += ' --entry __iar_program_start' - EXEC_PATH = EXEC_PATH + '/arm/bin/' - POST_ACTION = '' diff --git a/bsp/essemi/es32f0334/template.uvoptx b/bsp/essemi/es32f0334/template.uvoptx deleted file mode 100644 index 1b420d4999..0000000000 --- a/bsp/essemi/es32f0334/template.uvoptx +++ /dev/null @@ -1,182 +0,0 @@ - - - - 1.0 - -
### uVision Project, (C) Keil Software
- - - *.c - *.s*; *.src; *.a* - *.obj; *.o - *.lib - *.txt; *.h; *.inc - *.plm - *.cpp - 0 - - - - 0 - 0 - - - - rt-thread - 0x4 - ARM-ADS - - 12000000 - - 1 - 1 - 0 - 1 - 0 - - - 1 - 65535 - 0 - 0 - 0 - - - 79 - 66 - 8 - .\build\keil\ - - - 1 - 1 - 1 - 0 - 1 - 1 - 0 - 1 - 0 - 0 - 0 - 0 - - - 1 - 1 - 1 - 1 - 1 - 1 - 1 - 0 - 0 - - - 0 - 0 - 1 - - 255 - - 0 - 1 - 1 - 1 - 1 - 1 - 1 - 1 - 1 - 1 - 1 - 1 - 1 - 1 - 0 - 1 - 1 - 1 - 1 - 0 - 0 - 1 - 0 - 0 - 3 - - - - - - - - - - - BIN\CMSIS_AGDI.dll - - - - 0 - CMSIS_AGDI - -X"Any" -UAny -O206 -S0 -C0 -P00 -N00("ARM CoreSight SW-DP") -D00(0BB11477) -L00(0) -TO18 -TC10000000 -TP20 -TDS8007 -TDT0 -TDC1F -TIEFFFFFFFF -TIP8 -FO15 -FD20000000 -FC1000 -FN1 -FF0ES32F033x.FLM -FS00 -FL040000 -FP0($$Device:ES32F0334LT$Flash\ES32F033x.FLM) - - - 0 - JL2CM3 - -U12345678 -O78 -S4 -ZTIFSpeedSel2000 -A0 -C0 -JU1 -JI127.0.0.1 -JP0 -RST0 -TO18 -TC10000000 -TP21 -TDS8004 -TDT0 -TDC1F -TIEFFFFFFFF -TIP8 -TB1 -TFE0 -FO15 -FD20000000 -FC1000 -FN1 -FF0ES32F033x.FLM -FS00 -FL040000 -FP0($$Device:ES32F0334LT$Flash\ES32F033x.FLM) - - - 0 - UL2CM3 - UL2CM3(-S0 -C0 -P0 -FD20000000 -FC1000 -FN1 -FF0ES32F033x -FS00 -FL040000 -FP0($$Device:ES32F0334LT$Flash\ES32F033x.FLM)) - - - - - 0 - - - 0 - 0 - 0 - 0 - 0 - 0 - 0 - 0 - 0 - 0 - 0 - 0 - 0 - 0 - 0 - 0 - 0 - 0 - 0 - 0 - 0 - 0 - 0 - 0 - - - - 0 - 0 - 0 - - - - - - - - - - - - diff --git a/bsp/essemi/es32f0334/template.uvprojx b/bsp/essemi/es32f0334/template.uvprojx deleted file mode 100644 index 37ac22a68d..0000000000 --- a/bsp/essemi/es32f0334/template.uvprojx +++ /dev/null @@ -1,389 +0,0 @@ - - - - 2.1 - -
### uVision Project, (C) Keil Software
- - - - rt-thread - 0x4 - ARM-ADS - 0 - - - ES32F0334LT - Eastsoft - Eastsoft.ES32_DFP.7.2350 - http://www.essemi.com - IRAM(0x20000000,0x00008000) IROM(0x00000000,0x00040000) CPUTYPE("Cortex-M0") CLOCK(12000000) ELITTLE - - - UL2CM3(-S0 -C0 -P0 -FD20000000 -FC1000 -FN1 -FF0ES32F033x -FS00 -FL040000 -FP0($$Device:ES32F0334LT$Flash\ES32F033x.FLM)) - 0 - $$Device:ES32F0334LT$Device\Include\es32f033x.h - - - - - - - - - - $$Device:ES32F0334LT$SVD\es32f0xx.svd - 0 - 0 - - - - - - - 0 - 0 - 0 - 0 - 1 - - .\build\keil\ - rtthread - 1 - 0 - 0 - 1 - 1 - .\build\keil\ - 1 - 0 - 0 - - 0 - 0 - - - 0 - 0 - 0 - 0 - - - 0 - 0 - - - 0 - 0 - 0 - 0 - - - 1 - 0 - fromelf --bin !L --output rtthread.bin - - 0 - 0 - 0 - 0 - - 0 - - - - 0 - 0 - 0 - 0 - 0 - 1 - 0 - 0 - 0 - 0 - 3 - - - 1 - - - SARMCM3.DLL - -MPU - DARMCM1.DLL - -pCM0 - SARMCM3.DLL - -MPU - TARMCM1.DLL - -pCM0 - - - - 1 - 0 - 0 - 0 - 16 - - - - - 1 - 0 - 0 - 1 - 1 - 4096 - - 1 - BIN\UL2CM3.DLL - "" () - - - - - 0 - - - - 0 - 1 - 1 - 1 - 1 - 1 - 1 - 1 - 0 - 1 - 1 - 0 - 1 - 1 - 0 - 0 - 1 - 1 - 1 - 1 - 1 - 1 - 1 - 1 - 1 - 0 - 0 - "Cortex-M0" - - 0 - 0 - 0 - 1 - 1 - 0 - 0 - 0 - 0 - 0 - 0 - 8 - 0 - 0 - 0 - 0 - 3 - 3 - 0 - 0 - 0 - 0 - 0 - 0 - 0 - 0 - 0 - 0 - 1 - 0 - 0 - 0 - 0 - 1 - 0 - - - 0 - 0x0 - 0x0 - - - 0 - 0x0 - 0x0 - - - 0 - 0x0 - 0x0 - - - 0 - 0x0 - 0x0 - - - 0 - 0x0 - 0x0 - - - 0 - 0x0 - 0x0 - - - 0 - 0x20000000 - 0x8000 - - - 1 - 0x0 - 0x40000 - - - 0 - 0x0 - 0x0 - - - 1 - 0x0 - 0x0 - - - 1 - 0x0 - 0x0 - - - 1 - 0x0 - 0x0 - - - 1 - 0x0 - 0x40000 - - - 1 - 0x0 - 0x0 - - - 0 - 0x0 - 0x0 - - - 0 - 0x0 - 0x0 - - - 0 - 0x0 - 0x0 - - - 0 - 0x20000000 - 0x8000 - - - 0 - 0x0 - 0x0 - - - - - - 1 - 1 - 0 - 0 - 1 - 0 - 0 - 0 - 0 - 0 - 0 - 0 - 0 - 1 - 0 - 0 - 1 - 1 - 1 - 1 - 0 - 0 - 0 - - - - - - - - - 1 - 0 - 0 - 0 - 0 - 0 - 0 - 0 - 0 - 0 - - - - - - - - - 1 - 0 - 0 - 0 - 1 - 0 - 0x08000000 - 0x20000000 - - - - - - - - - - - - - - - - - - - - -- cgit v1.3.1 From ca77bbfb0a6bc7c6d95749fa07dfea2a60bd9960 Mon Sep 17 00:00:00 2001 From: liuhy Date: Fri, 10 Sep 2021 18:09:25 +0800 Subject: update es32f0654 , es32f369x libraries --- .../ES32F065x/Startup/gcc/startup_es32f065x.s | 299 +++++++++++++++++++++ .../ES32F065x/Startup/iar/startup_es32f065x.s | 29 +- .../ES32F065x/Startup/keil/startup_es32f065x.s | 21 +- .../ES32F36xx/Startup/gcc/startup_es32f36xx.S | 72 ++++- .../ES32F36xx/Startup/iar/startup_es32f36xx.s | 75 +++++- .../ES32F36xx/Startup/keil/startup_es32f36xx.s | 66 ++++- .../Include/ald_gpio.h | 74 +++-- .../Include/ald_i2c.h | 2 +- .../Include/ald_timer.h | 11 +- .../Include/ald_uart.h | 17 +- .../ES32F36xx_ALD_StdPeriph_Driver/Include/utils.h | 3 +- .../Source/ald_adc.c | 124 +++++---- .../Source/ald_can.c | 6 +- .../Source/ald_cmu.c | 7 +- .../Source/ald_dma.c | 11 +- .../Source/ald_gpio.c | 4 +- .../Source/ald_nand.c | 4 +- .../Source/ald_timer.c | 6 +- .../Source/ald_uart.c | 93 +++++-- .../ES32F36xx_ALD_StdPeriph_Driver/Source/utils.c | 239 +++++++++++++++- 20 files changed, 1011 insertions(+), 152 deletions(-) create mode 100644 bsp/essemi/es32f0654/libraries/CMSIS/Device/EastSoft/ES32F065x/Startup/gcc/startup_es32f065x.s (limited to 'bsp') diff --git a/bsp/essemi/es32f0654/libraries/CMSIS/Device/EastSoft/ES32F065x/Startup/gcc/startup_es32f065x.s b/bsp/essemi/es32f0654/libraries/CMSIS/Device/EastSoft/ES32F065x/Startup/gcc/startup_es32f065x.s new file mode 100644 index 0000000000..9f27a3d852 --- /dev/null +++ b/bsp/essemi/es32f0654/libraries/CMSIS/Device/EastSoft/ES32F065x/Startup/gcc/startup_es32f065x.s @@ -0,0 +1,299 @@ +/** + ****************************************************************************** + * @file startup_es32f065x.s + * @author AE Team + * @brief ES32F065x devices vector table for GCC toolchain. + * This module performs: + * - Set the initial SP + * - Set the initial PC == Reset_Handler, + * - Set the vector table entries with the exceptions ISR address + * - Branches to main in the C library (which eventually + * calls main()). + * After Reset the Cortex-M0 processor is in Thread mode, + * priority is Privileged, and the Stack is set to Main. + * @note + * Change Logs: + * Date Author Notes + * 10 Dec 2018 AE Team The first version + * + * Copyright (C) Shanghai Eastsoft Microelectronics Co. Ltd. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + ********************************************************************************** + */ + + .syntax unified + .arch armv6-m + .cpu cortex-m0 + .fpu softvfp + .thumb + +.global g_pfnVectors +.global Default_Handler + +/* start address for the initialization values of the .data section. +defined in linker script */ +.word _sidata +/* start address for the .data section. defined in linker script */ +.word _sdata +/* end address for the .data section. defined in linker script */ +.word _edata +/* start address for the .bss section. defined in linker script */ +.word _sbss +/* end address for the .bss section. defined in linker script */ +.word _ebss + + .section .text.Reset_Handler + .weak Reset_Handler + .type Reset_Handler, %function +Reset_Handler: + ldr r0, =_estack + mov sp, r0 /* set stack pointer */ + +/* Copy the data segment initializers from flash to SRAM */ + ldr r0, =_sdata + ldr r1, =_edata + ldr r2, =_sidata + movs r3, #0 + b LoopCopyDataInit + +CopyDataInit: + ldr r4, [r2, r3] + str r4, [r0, r3] + adds r3, r3, #4 + +LoopCopyDataInit: + adds r4, r0, r3 + cmp r4, r1 + bcc CopyDataInit + +/* Zero fill the bss segment. */ + ldr r2, =_sbss + ldr r4, =_ebss + movs r3, #0 + b LoopFillZerobss + +FillZerobss: + str r3, [r2] + adds r2, r2, #4 + +LoopFillZerobss: + cmp r2, r4 + bcc FillZerobss + + bl __libc_init_array + + bl main + +LoopForever: + b LoopForever + + +.size Reset_Handler, .-Reset_Handler + +/** + * @brief This is the code that gets called when the processor receives an + * unexpected interrupt. This simply enters an infinite loop, preserving + * the system state for examination by a debugger. + * + * @param None + * @retval : None +*/ + .section .text.Default_Handler,"ax",%progbits +Default_Handler: +Infinite_Loop: + b Infinite_Loop + .size Default_Handler, .-Default_Handler +/****************************************************************************** +* +* The minimal vector table for a Cortex M0. Note that the proper constructs +* must be placed on this to ensure that it ends up at physical address +* 0x0000.0000. +* +******************************************************************************/ + .section .isr_vector,"a",%progbits + .type g_pfnVectors, %object + .size g_pfnVectors, .-g_pfnVectors + + +g_pfnVectors: + .word _estack /* 0, load top of stack */ + .word Reset_Handler /* 1, reset handler */ + .word NMI_Handler /* 2, nmi handler */ + .word HardFault_Handler /* 3, hard fault handler */ + .word 0 /* 4, Reserved */ + .word 0 /* 5, Reserved */ + .word 0 /* 6, Reserved */ + .word 0 /* 7, Reserved */ + .word 0 /* 8, Reserved */ + .word 0 /* 9, Reserved */ + .word 0 /* 10, Reserved */ + .word SVC_Handler /* 11, svcall handler */ + .word DebugMon_Handler /* 12, Debug Monitor Handler */ + .word 0 /* 13, Reserved */ + .word PendSV_Handler /* 14, pendsv handler */ + .word SysTick_Handler /* 15, systick handler */ + .word WWDG_IWDG_Handler /* 16, irq0 WWDG_IWDG handler */ + .word LVD_Handler /* 17, irq1 LVD handler */ + .word RTC_TSENSE_Handler /* 18, irq2 RTC handler */ + .word CRYPT_TRNG_Handler /* 19, irq3 CRYPT handler */ + .word CMU_Handler /* 20, irq4 CMU handler */ + .word EXTI0_3_Handler /* 21, irq5 EXTI0_3 handler */ + .word EXTI4_7_Handler /* 22, irq6 EXTI4_7 handler */ + .word EXTI8_11_Handler /* 23, irq7 EXTI8_11 handler */ + .word EXTI12_15_Handler /* 24, irq8 EXTI12_15 handler */ + .word DMA_Handler /* 25, irq9 DMA handler */ + .word CAN0_Handler /* 26, irq10 CAN0_CRYPT_TRNG handler */ + .word LPTIM0_SPI2_Handler /* 27, irq11 LPTIM0_SPI2 handler */ + .word ADC_ACMP_Handler /* 28, irq12 ADC_ACMP handler */ + .word AD16C4T0_BRK_UP_TRIG_COM_Handler /* 29, irq13 AD16C4T0_BRK_UP_TRIG_COM handler */ + .word AD16C4T0_CC_Handler /* 30, irq14 AD16C4T0_CC handler */ + .word BS16T0_Handler /* 31, irq15 BS16T0 handler */ + .word 0 /* 32, irq16 Reserved */ + .word GP16C2T0_Handler /* 33, irq17 GP16C2T0 handler */ + .word GP16C2T1_Handler /* 34, irq18 GP16C2T1 handler */ + .word BS16T1_UART2_Handler /* 35, irq19 BS16T1_UART2 handler */ + .word BS16T2_UART3_Handler /* 36, irq20 BS16T2_UART3 handler */ + .word GP16C4T0_LCD_Handler /* 37, irq21 GP16C4T0_LCD handler */ + .word BS16T3_DAC0_Handler /* 38, irq22 BS16T3_DAC0 handler */ + .word I2C0_Handler /* 39, irq23 I2C0 handler */ + .word I2C1_Handler /* 40, irq24 I2C1 handler */ + .word SPI0_Handler /* 41, irq25 SPI0 handler */ + .word SPI1_Handler /* 42, irq26 SPI1 handler */ + .word UART0_Handler /* 43, irq27 UART0 handler */ + .word UART1_Handler /* 44, irq28 UART1 handler */ + .word USART0_Handler /* 45, irq29 USART0 handler */ + .word USART1_Handler /* 46 irq30 USART1 handler */ + .word LPUART0_Handler /* 47, irq31 LPUART0 handler */ + +/******************************************************************************* +* +* Provide weak aliases for each Exception handler to the Default_Handler. +* As they are weak aliases, any function with the same name will override +* this definition. +* +*******************************************************************************/ + + .weak NMI_Handler + .thumb_set NMI_Handler,Default_Handler + + .weak HardFault_Handler + .thumb_set HardFault_Handler,Default_Handler + + .weak SVC_Handler + .thumb_set SVC_Handler,Default_Handler + + .weak DebugMon_Handler + .thumb_set DebugMon_Handler,Default_Handler + + .weak PendSV_Handler + .thumb_set PendSV_Handler,Default_Handler + + .weak SysTick_Handler + .thumb_set SysTick_Handler,Default_Handler + + .weak WWDG_IWDG_Handler + .thumb_set WWDG_IWDG_Handler,Default_Handler + + .weak LVD_Handler + .thumb_set LVD_Handler,Default_Handler + + .weak RTC_TSENSE_Handler + .thumb_set RTC_TSENSE_Handler,Default_Handler + + .weak CRYPT_TRNG_Handler + .thumb_set CRYPT_TRNG_Handler,Default_Handler + + .weak CMU_Handler + .thumb_set CMU_Handler,Default_Handler + + .weak EXTI0_3_Handler + .thumb_set EXTI0_3_Handler,Default_Handler + + .weak EXTI4_7_Handler + .thumb_set EXTI4_7_Handler,Default_Handler + + .weak EXTI8_11_Handler + .thumb_set EXTI8_11_Handler,Default_Handler + + .weak EXTI12_15_Handler + .thumb_set EXTI12_15_Handler,Default_Handler + + .weak DMA_Handler + .thumb_set DMA_Handler,Default_Handler + + .weak CAN0_Handler + .thumb_set CAN0_Handler,Default_Handler + + .weak LPTIM0_SPI2_Handler + .thumb_set LPTIM0_SPI2_Handler,Default_Handler + + .weak ADC_ACMP_Handler + .thumb_set ADC_ACMP_Handler,Default_Handler + + .weak AD16C4T0_BRK_UP_TRIG_COM_Handler + .thumb_set AD16C4T0_BRK_UP_TRIG_COM_Handler,Default_Handler + + .weak AD16C4T0_CC_Handler + .thumb_set AD16C4T0_CC_Handler,Default_Handler + + .weak BS16T0_Handler + .thumb_set BS16T0_Handler,Default_Handler + + .weak GP16C2T0_Handler + .thumb_set GP16C2T0_Handler,Default_Handler + + .weak GP16C2T1_Handler + .thumb_set GP16C2T1_Handler,Default_Handler + + .weak BS16T1_UART2_Handler + .thumb_set BS16T1_UART2_Handler,Default_Handler + + .weak BS16T2_UART3_Handler + .thumb_set BS16T2_UART3_Handler,Default_Handler + + .weak GP16C4T0_LCD_Handler + .thumb_set GP16C4T0_LCD_Handler,Default_Handler + + .weak BS16T3_DAC0_Handler + .thumb_set BS16T3_DAC0_Handler,Default_Handler + + .weak I2C0_Handler + .thumb_set I2C0_Handler,Default_Handler + + .weak I2C1_Handler + .thumb_set I2C1_Handler,Default_Handler + + .weak SPI0_Handler + .thumb_set SPI0_Handler,Default_Handler + + .weak SPI1_Handler + .thumb_set SPI1_Handler,Default_Handler + + .weak UART0_Handler + .thumb_set UART0_Handler,Default_Handler + + .weak UART1_Handler + .thumb_set UART1_Handler,Default_Handler + + .weak USART0_Handler + .thumb_set USART0_Handler,Default_Handler + + .weak USART1_Handler + .thumb_set USART1_Handler,Default_Handler + + .weak LPUART0_Handler + .thumb_set LPUART0_Handler,Default_Handler + \ No newline at end of file diff --git a/bsp/essemi/es32f0654/libraries/CMSIS/Device/EastSoft/ES32F065x/Startup/iar/startup_es32f065x.s b/bsp/essemi/es32f0654/libraries/CMSIS/Device/EastSoft/ES32F065x/Startup/iar/startup_es32f065x.s index 265c345fb1..054b37dc64 100644 --- a/bsp/essemi/es32f0654/libraries/CMSIS/Device/EastSoft/ES32F065x/Startup/iar/startup_es32f065x.s +++ b/bsp/essemi/es32f0654/libraries/CMSIS/Device/EastSoft/ES32F065x/Startup/iar/startup_es32f065x.s @@ -3,8 +3,27 @@ ; description: es32f065x Device Startup File ; author : AE Team ; data : 10 Dec 2018 +; note +; Change Logs: +; Date Author Notes +; 10 Dec 2018 AE Team The first version +; ; Copyright (C) Shanghai Eastsoft Microelectronics Co. Ltd. All rights reserved. -;******************************************************************************* +; +; SPDX-License-Identifier: Apache-2.0 +; +; Licensed under the Apache License, Version 2.0 (the License); you may +; not use this file except in compliance with the License. +; You may obtain a copy of the License at +; +; www.apache.org/licenses/LICENSE-2.0 +; +; Unless required by applicable law or agreed to in writing, software +; distributed under the License is distributed on an AS IS BASIS, WITHOUT +; WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +; See the License for the specific language governing permissions and +; limitations under the License. +;********************************************************************************* MODULE ?cstartup @@ -35,7 +54,7 @@ __vector_table DCD SysTick_Handler ;15, systick handler DCD WWDG_IWDG_Handler ;16, irq0 WWDG_IWDG handler DCD LVD_Handler ;17, irq1 LVD handler - DCD RTC_TEMP_Handler ;18, irq2 RTC handler + DCD RTC_TSENSE_Handler ;18, irq2 RTC handler DCD CRYPT_TRNG_Handler ;19, irq3 CRYPT handler DCD CMU_Handler ;20, irq4 CMU handler DCD EXTI0_3_Handler ;21, irq5 EXTI0_3 handler @@ -118,10 +137,10 @@ WWDG_IWDG_Handler LVD_Handler B LVD_Handler - PUBWEAK RTC_TEMP_Handler + PUBWEAK RTC_TSENSE_Handler SECTION .text:CODE:NOROOT:REORDER(1) -RTC_TEMP_Handler - B RTC_TEMP_Handler +RTC_TSENSE_Handler + B RTC_TSENSE_Handler PUBWEAK CRYPT_TRNG_Handler SECTION .text:CODE:NOROOT:REORDER(1) diff --git a/bsp/essemi/es32f0654/libraries/CMSIS/Device/EastSoft/ES32F065x/Startup/keil/startup_es32f065x.s b/bsp/essemi/es32f0654/libraries/CMSIS/Device/EastSoft/ES32F065x/Startup/keil/startup_es32f065x.s index dab56328c5..233ad8aab6 100644 --- a/bsp/essemi/es32f0654/libraries/CMSIS/Device/EastSoft/ES32F065x/Startup/keil/startup_es32f065x.s +++ b/bsp/essemi/es32f0654/libraries/CMSIS/Device/EastSoft/ES32F065x/Startup/keil/startup_es32f065x.s @@ -3,8 +3,27 @@ ; description: es32f065x Device Startup File ; author : AE Team ; data : 29 Aug 2017 +; note +; Change Logs: +; Date Author Notes +; 29 Aug 2017 AE Team The first version +; ; Copyright (C) Shanghai Eastsoft Microelectronics Co. Ltd. All rights reserved. -;******************************************************************************* +; +; SPDX-License-Identifier: Apache-2.0 +; +; Licensed under the Apache License, Version 2.0 (the License); you may +; not use this file except in compliance with the License. +; You may obtain a copy of the License at +; +; www.apache.org/licenses/LICENSE-2.0 +; +; Unless required by applicable law or agreed to in writing, software +; distributed under the License is distributed on an AS IS BASIS, WITHOUT +; WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +; See the License for the specific language governing permissions and +; limitations under the License. +;********************************************************************************* ;Stack Configuration------------------------------------------------------------ Stack_Size EQU 0x00000400 diff --git a/bsp/essemi/es32f369x/libraries/CMSIS/Device/EastSoft/ES32F36xx/Startup/gcc/startup_es32f36xx.S b/bsp/essemi/es32f369x/libraries/CMSIS/Device/EastSoft/ES32F36xx/Startup/gcc/startup_es32f36xx.S index 4e34d42c1d..68d648f157 100644 --- a/bsp/essemi/es32f369x/libraries/CMSIS/Device/EastSoft/ES32F36xx/Startup/gcc/startup_es32f36xx.S +++ b/bsp/essemi/es32f369x/libraries/CMSIS/Device/EastSoft/ES32F36xx/Startup/gcc/startup_es32f36xx.S @@ -11,7 +11,27 @@ * calls main()). * After Reset the Cortex-M3 processor is in Thread mode, * priority is Privileged, and the Stack is set to Main. - ****************************************************************************** + * @note + * Change Logs: + * Date Author Notes + * 23 Jan 2019 AE Team The first version + * + * Copyright (C) Shanghai Eastsoft Microelectronics Co. Ltd. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + ********************************************************************************** */ .syntax unified @@ -41,6 +61,48 @@ defined in linker script */ Reset_Handler: ldr r0, =_estack mov sp, r0 /* set stack pointer */ + + ldr r0, =0x55AA6996 + ldr r1, =0x40080000 + str r0, [r1] + + ldr r0, =0x5A962814 + ldr r1, =0x40080100 + str r0, [r1] + ldr r0, =0xE7CB69A5 + str r0, [r1] + + ldr r0, =0x40083C00 + ldr r1, [r0] + ldr r2, =0xffff + and r1, r2 + ldr r2, =0x55AA0000 + orr r1, r2 + str r1, [r0] + str r1, [r0] + str r1, [r0] + str r1, [r0] + str r1, [r0] + str r1, [r0] + str r1, [r0] + str r1, [r0] + str r1, [r0] + str r1, [r0] + + mov r0, r0 + mov r0, r0 + + ldr r0, =0x123456 + ldr r1, =0x40080100 + str r0, [r1] + + ldr r0, =0x40080404 + ldr r1, =0x4000000 + str r1, [r0] + + ldr r0, =0x123456 + ldr r1, =0x40080000 + str r0, [r1] /* Copy the data segment initializers from flash to SRAM */ ldr r0, =_sdata @@ -72,11 +134,13 @@ FillZerobss: LoopFillZerobss: cmp r2, r4 bcc FillZerobss + + bl sys_config + bl adc_config -/*bl __libc_init_array + bl __libc_init_array - bl main */ - bl entry + bl main LoopForever: b LoopForever diff --git a/bsp/essemi/es32f369x/libraries/CMSIS/Device/EastSoft/ES32F36xx/Startup/iar/startup_es32f36xx.s b/bsp/essemi/es32f369x/libraries/CMSIS/Device/EastSoft/ES32F36xx/Startup/iar/startup_es32f36xx.s index 5e43634bd9..8cbaf6eb0e 100644 --- a/bsp/essemi/es32f369x/libraries/CMSIS/Device/EastSoft/ES32F36xx/Startup/iar/startup_es32f36xx.s +++ b/bsp/essemi/es32f369x/libraries/CMSIS/Device/EastSoft/ES32F36xx/Startup/iar/startup_es32f36xx.s @@ -3,8 +3,27 @@ ; description: es32f36xx Device Startup File ; author : AE Team ; data : 04 Jul 2019 +; note +; Change Logs: +; Date Author Notes +; 04 Jul 2019 AE Team The first version +; ; Copyright (C) Shanghai Eastsoft Microelectronics Co. Ltd. All rights reserved. -;******************************************************************************* +; +; SPDX-License-Identifier: Apache-2.0 +; +; Licensed under the Apache License, Version 2.0 (the License); you may +; not use this file except in compliance with the License. +; You may obtain a copy of the License at +; +; www.apache.org/licenses/LICENSE-2.0 +; +; Unless required by applicable law or agreed to in writing, software +; distributed under the License is distributed on an AS IS BASIS, WITHOUT +; WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +; See the License for the specific language governing permissions and +; limitations under the License. +;********************************************************************************* MODULE ?cstartup @@ -12,6 +31,8 @@ SECTION CSTACK:DATA:NOROOT(3) SECTION .intvec:CODE:NOROOT(2) + EXTERN sys_config + EXTERN adc_config EXTERN __iar_program_start PUBLIC __vector_table @@ -116,8 +137,56 @@ __vector_table PUBWEAK RESET_Handler SECTION .text:CODE:NOROOT:REORDER(2) RESET_Handler - LDR R0, =__iar_program_start - BX R0 + ldr r0, =0x55AA6996 + ldr r1, =0x40080000 + str r0, [r1] + + ldr r0, =0x5A962814 + ldr r1, =0x40080100 + str r0, [r1] + ldr r0, =0xE7CB69A5 + str r0, [r1] + + ldr r0, =0x40083C00 + ldr r1, [r0] + ldr r2, =0xffff + and r1, r2, r1 + ldr r2, =0x55AA0000 + orr r1, r2, r1 + str r1, [r0] + str r1, [r0] + str r1, [r0] + str r1, [r0] + str r1, [r0] + str r1, [r0] + str r1, [r0] + str r1, [r0] + str r1, [r0] + str r1, [r0] + + mov r0, r0 + mov r0, r0 + + ldr r0, =0x123456 + ldr r1, =0x40080100 + str r0, [r1] + + ldr r0, =0x40080404 + ldr r1, =0x4000000 + str r1, [r0] + + ldr r0, =0x123456 + ldr r1, =0x40080000 + str r0, [r1] + + LDR R0, =sys_config + BLX R0 + + LDR R0, =adc_config + BLX R0 + + LDR R0, =__iar_program_start + BX R0 PUBWEAK NMI_Handler SECTION .text:CODE:NOROOT:REORDER(1) diff --git a/bsp/essemi/es32f369x/libraries/CMSIS/Device/EastSoft/ES32F36xx/Startup/keil/startup_es32f36xx.s b/bsp/essemi/es32f369x/libraries/CMSIS/Device/EastSoft/ES32F36xx/Startup/keil/startup_es32f36xx.s index c8aaf3ed69..8e2c55e5e3 100644 --- a/bsp/essemi/es32f369x/libraries/CMSIS/Device/EastSoft/ES32F36xx/Startup/keil/startup_es32f36xx.s +++ b/bsp/essemi/es32f369x/libraries/CMSIS/Device/EastSoft/ES32F36xx/Startup/keil/startup_es32f36xx.s @@ -3,22 +3,27 @@ ; description: es32f36xx Device Startup File ; author : AE Team ; data : 23 Jan 2019 +; note +; Change Logs: +; Date Author Notes +; 23 Jan 2019 AE Team The first version +; ; Copyright (C) Shanghai Eastsoft Microelectronics Co. Ltd. All rights reserved. -; +; ; SPDX-License-Identifier: Apache-2.0 -; +; ; Licensed under the Apache License, Version 2.0 (the License); you may ; not use this file except in compliance with the License. ; You may obtain a copy of the License at -; +; ; www.apache.org/licenses/LICENSE-2.0 -; +; ; Unless required by applicable law or agreed to in writing, software ; distributed under the License is distributed on an AS IS BASIS, WITHOUT ; WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. ; See the License for the specific language governing permissions and ; limitations under the License. -;******************************************************************************* +;********************************************************************************* ;Stack Configuration------------------------------------------------------------ Stack_Size EQU 0x00000800 @@ -137,6 +142,57 @@ __Vectors DCD __initial_sp ;0, load top of stack ;Reset Handler---------------------------------------------- RESET_Handler PROC EXPORT RESET_Handler [WEAK] + + ldr r0, =0x55AA6996 + ldr r1, =0x40080000 + str r0, [r1] + + ldr r0, =0x5A962814 + ldr r1, =0x40080100 + str r0, [r1] + ldr r0, =0xE7CB69A5 + str r0, [r1] + + ldr r0, =0x40083C00 + ldr r1, [r0] + ldr r2, =0xffff + and r1, r2 + ldr r2, =0x55AA0000 + orr r1, r2 + str r1, [r0] + str r1, [r0] + str r1, [r0] + str r1, [r0] + str r1, [r0] + str r1, [r0] + str r1, [r0] + str r1, [r0] + str r1, [r0] + str r1, [r0] + + mov r0, r0 + mov r0, r0 + + ldr r0, =0x123456 + ldr r1, =0x40080100 + str r0, [r1] + + ldr r0, =0x40080404 + ldr r1, =0x4000000 + str r1, [r0] + + ldr r0, =0x123456 + ldr r1, =0x40080000 + str r0, [r1] + + IMPORT sys_config + LDR R0, =sys_config + BLX R0 + + IMPORT adc_config + LDR R0, =adc_config + BLX R0 + IMPORT __main LDR R0, =__main BX R0 diff --git a/bsp/essemi/es32f369x/libraries/ES32F36xx_ALD_StdPeriph_Driver/Include/ald_gpio.h b/bsp/essemi/es32f369x/libraries/ES32F36xx_ALD_StdPeriph_Driver/Include/ald_gpio.h index 517330ce32..07d98a1342 100644 --- a/bsp/essemi/es32f369x/libraries/ES32F36xx_ALD_StdPeriph_Driver/Include/ald_gpio.h +++ b/bsp/essemi/es32f369x/libraries/ES32F36xx_ALD_StdPeriph_Driver/Include/ald_gpio.h @@ -50,23 +50,63 @@ * @defgroup GPIO_Public_Macros GPIO Public Macros * @{ */ -#define GPIO_PIN_0 (1U << 0) -#define GPIO_PIN_1 (1U << 1) -#define GPIO_PIN_2 (1U << 2) -#define GPIO_PIN_3 (1U << 3) -#define GPIO_PIN_4 (1U << 4) -#define GPIO_PIN_5 (1U << 5) -#define GPIO_PIN_6 (1U << 6) -#define GPIO_PIN_7 (1U << 7) -#define GPIO_PIN_8 (1U << 8) -#define GPIO_PIN_9 (1U << 9) -#define GPIO_PIN_10 (1U << 10) -#define GPIO_PIN_11 (1U << 11) -#define GPIO_PIN_12 (1U << 12) -#define GPIO_PIN_13 (1U << 13) -#define GPIO_PIN_14 (1U << 14) -#define GPIO_PIN_15 (1U << 15) -#define GPIO_PIN_ALL (0xFFFF) +#define GPIO_PIN_0 (0x1U) +#define GPIO_PIN_1 (0x2U) +#define GPIO_PIN_2 (0x4U) +#define GPIO_PIN_3 (0x8U) +#define GPIO_PIN_4 (0x10U) +#define GPIO_PIN_5 (0x20U) +#define GPIO_PIN_6 (0x40U) +#define GPIO_PIN_7 (0x80U) +#define GPIO_PIN_8 (0x100U) +#define GPIO_PIN_9 (0x200U) +#define GPIO_PIN_10 (0x400U) +#define GPIO_PIN_11 (0x800U) +#define GPIO_PIN_12 (0x1000U) +#define GPIO_PIN_13 (0x2000U) +#define GPIO_PIN_14 (0x4000U) +#define GPIO_PIN_15 (0x8000U) +#define GPIO_PIN_ALL (0xFFFF) + +/* Toggle IO */ +#define ALD_GPIOA_TOGGLE_PIN(x) (GPIOA->BIR = (x)) +#define ALD_GPIOB_TOGGLE_PIN(x) (GPIOB->BIR = (x)) +#define ALD_GPIOC_TOGGLE_PIN(x) (GPIOC->BIR = (x)) +#define ALD_GPIOD_TOGGLE_PIN(x) (GPIOD->BIR = (x)) +#define ALD_GPIOE_TOGGLE_PIN(x) (GPIOE->BIR = (x)) +#define ALD_GPIOF_TOGGLE_PIN(x) (GPIOF->BIR = (x)) +#define ALD_GPIOG_TOGGLE_PIN(x) (GPIOG->BIR = (x)) +#define ALD_GPIOH_TOGGLE_PIN(x) (GPIOH->BIR = (x)) + +/* Read IO level */ +#define ALD_GPIOA_READ_PIN(x) ((GPIOA->DIN & (x)) ? 1 : 0) +#define ALD_GPIOB_READ_PIN(x) ((GPIOB->DIN & (x)) ? 1 : 0) +#define ALD_GPIOC_READ_PIN(x) ((GPIOC->DIN & (x)) ? 1 : 0) +#define ALD_GPIOD_READ_PIN(x) ((GPIOD->DIN & (x)) ? 1 : 0) +#define ALD_GPIOE_READ_PIN(x) ((GPIOE->DIN & (x)) ? 1 : 0) +#define ALD_GPIOF_READ_PIN(x) ((GPIOF->DIN & (x)) ? 1 : 0) +#define ALD_GPIOG_READ_PIN(x) ((GPIOG->DIN & (x)) ? 1 : 0) +#define ALD_GPIOH_READ_PIN(x) ((GPIOH->DIN & (x)) ? 1 : 0) + +/* Set IO as high */ +#define ALD_GPIOA_SET_PIN(x) (GPIOA->BSRR = (x)) +#define ALD_GPIOB_SET_PIN(x) (GPIOB->BSRR = (x)) +#define ALD_GPIOC_SET_PIN(x) (GPIOC->BSRR = (x)) +#define ALD_GPIOD_SET_PIN(x) (GPIOD->BSRR = (x)) +#define ALD_GPIOE_SET_PIN(x) (GPIOE->BSRR = (x)) +#define ALD_GPIOF_SET_PIN(x) (GPIOF->BSRR = (x)) +#define ALD_GPIOG_SET_PIN(x) (GPIOG->BSRR = (x)) +#define ALD_GPIOH_SET_PIN(x) (GPIOH->BSRR = (x)) + +/* Set IO as low */ +#define ALD_GPIOA_RESET_PIN(x) (GPIOA->BSRR = ((x) << 16)) +#define ALD_GPIOB_RESET_PIN(x) (GPIOB->BSRR = ((x) << 16)) +#define ALD_GPIOC_RESET_PIN(x) (GPIOC->BSRR = ((x) << 16)) +#define ALD_GPIOD_RESET_PIN(x) (GPIOD->BSRR = ((x) << 16)) +#define ALD_GPIOE_RESET_PIN(x) (GPIOE->BSRR = ((x) << 16)) +#define ALD_GPIOF_RESET_PIN(x) (GPIOF->BSRR = ((x) << 16)) +#define ALD_GPIOG_RESET_PIN(x) (GPIOG->BSRR = ((x) << 16)) +#define ALD_GPIOH_RESET_PIN(x) (GPIOH->BSRR = ((x) << 16)) /** * @} */ diff --git a/bsp/essemi/es32f369x/libraries/ES32F36xx_ALD_StdPeriph_Driver/Include/ald_i2c.h b/bsp/essemi/es32f369x/libraries/ES32F36xx_ALD_StdPeriph_Driver/Include/ald_i2c.h index c520c3d41a..fb81f4d70b 100644 --- a/bsp/essemi/es32f369x/libraries/ES32F36xx_ALD_StdPeriph_Driver/Include/ald_i2c.h +++ b/bsp/essemi/es32f369x/libraries/ES32F36xx_ALD_StdPeriph_Driver/Include/ald_i2c.h @@ -320,7 +320,7 @@ typedef struct i2c_handle_s { #define I2C_GET_IT_SOURCE(x, y) ((((x)->perh->IFM & (y)) == (y)) ? SET : RESET) #define I2C_GET_FLAG(x, y) ((((x)->perh->STAT) & ((y) & I2C_FLAG_MASK)) != RESET) #define I2C_MASTER_GET_DIR(x) (READ_BIT(((x)->perh->CON2), I2C_CON2_RD_WRN_MSK)) -#define I2C_SLAVE_GET_DIR(x) (READ_BIT(hperh->perh->STAT, I2C_STAT_DIR_MSK)) +#define I2C_SLAVE_GET_DIR(x) (READ_BIT(((x)->perh->STAT), I2C_STAT_DIR_MSK)) #define I2C_ENABLE(x) (SET_BIT((x)->perh->CON1, I2C_CON1_PE_MSK)) #define I2C_DISABLE(x) (CLEAR_BIT((x)->perh->CON1, I2C_CON1_PE_MSK)) /** diff --git a/bsp/essemi/es32f369x/libraries/ES32F36xx_ALD_StdPeriph_Driver/Include/ald_timer.h b/bsp/essemi/es32f369x/libraries/ES32F36xx_ALD_StdPeriph_Driver/Include/ald_timer.h index dcbc884368..ca3fe84d32 100644 --- a/bsp/essemi/es32f369x/libraries/ES32F36xx_ALD_StdPeriph_Driver/Include/ald_timer.h +++ b/bsp/essemi/es32f369x/libraries/ES32F36xx_ALD_StdPeriph_Driver/Include/ald_timer.h @@ -841,18 +841,15 @@ do { \ ((y) == TIMER_CHANNEL_3) || \ ((y) == TIMER_CHANNEL_4)))) -#define IS_TIMER_CCXN_INSTANCE(x, y) ((((x) == NULL) || \ - ((x) == NULL)) && \ +#define IS_TIMER_CCXN_INSTANCE(x, y) ((((x) == NULL)) && \ (((y) == TIMER_CHANNEL_1) || \ ((y) == TIMER_CHANNEL_2) || \ ((y) == TIMER_CHANNEL_3) || \ ((y) == TIMER_CHANNEL_4))) -#define IS_TIMER_REPETITION_COUNTER_INSTANCE(x) (((x) == NULL) || \ - ((x) == NULL)) +#define IS_TIMER_REPETITION_COUNTER_INSTANCE(x) (((x) == NULL)) -#define IS_TIMER_BREAK_INSTANCE(x) (((x) == NULL) || \ - ((x) == NULL)) +#define IS_TIMER_BREAK_INSTANCE(x) (((x) == NULL)) #define IS_TIMER_CLOCK_DIVISION_INSTANCE(x) IS_TIMER_CC2_INSTANCE(x) @@ -1050,7 +1047,7 @@ void ald_timer_pwm_start(timer_handle_t *hperh, timer_channel_t ch); void ald_timer_pwm_stop(timer_handle_t *hperh, timer_channel_t ch); void ald_timer_pwm_start_by_it(timer_handle_t *hperh, timer_channel_t ch); void ald_timer_pwm_stop_by_it(timer_handle_t *hperh, timer_channel_t ch); -void ald_timer_pwm_set_freq(timer_handle_t *hperh, uint16_t freq); +void ald_timer_pwm_set_freq(timer_handle_t *hperh, uint32_t freq); void ald_timer_pwm_set_duty(timer_handle_t *hperh, timer_channel_t ch, uint16_t duty); void ald_timer_pwm_set_input(timer_handle_t *hperh, timer_channel_t ch); #ifdef ALD_DMA diff --git a/bsp/essemi/es32f369x/libraries/ES32F36xx_ALD_StdPeriph_Driver/Include/ald_uart.h b/bsp/essemi/es32f369x/libraries/ES32F36xx_ALD_StdPeriph_Driver/Include/ald_uart.h index 56c1b5b94d..b5870ead77 100644 --- a/bsp/essemi/es32f369x/libraries/ES32F36xx_ALD_StdPeriph_Driver/Include/ald_uart.h +++ b/bsp/essemi/es32f369x/libraries/ES32F36xx_ALD_StdPeriph_Driver/Include/ald_uart.h @@ -213,16 +213,6 @@ typedef struct { uint8_t addr; /**< Address for compare */ } uart_rs485_config_t; -/** - * @brief Smart_card clock division - */ -typedef enum { - SCARD_CLOCK_DIV1 = 0x0U, /**< No prescaler is used */ - SCARD_CLOCK_DIV2 = 0x1U, /** Clock is divided by 2 */ - SCARD_CLOCK_DIV4 = 0x2U, /** Clock is divided by 4 */ - SCARD_CLOCK_DIV6 = 0x3U, /** Clock is divided by 6 */ -} scard_clk_div_t; - /** * @brief Smart_card Rx/Tx handle retry time */ @@ -244,7 +234,7 @@ typedef struct { uint8_t block_len; /**< Specifies the data block length.*/ uint8_t pt; /**< Specifies the protect time*/ scard_retry_t retry; /**< Specifies retry time.*/ - scard_clk_div_t clk_div; /**< Specifies the clock division.*/ + uint8_t clk_div; /**< Specifies the clock division.*/ type_func_t clk_out; /**< Specifies the clock out */ } uart_scard_config_t; @@ -458,10 +448,7 @@ typedef enum { ((x) == UART_IF_TFTH) || \ ((x) == UART_IF_TFEMPTY) || \ ((x) == UART_IF_TFOVER)) -#define IS_UART_SCARD_CLK(x) (((x) == SCARD_CLOCK_DIV1) || \ - ((x) == SCARD_CLOCK_DIV2) || \ - ((x) == SCARD_CLOCK_DIV4) || \ - ((x) == SCARD_CLOCK_DIV6)) +#define IS_UART_SCARD_CLK(x) (((x) <= 0x1F)) #define IS_UART_BAUDRATE(x) (((x) > 0) && ((x) < 0x44AA21)) #define IS_UART_DATA(x) ((x) <= 0x1FF) diff --git a/bsp/essemi/es32f369x/libraries/ES32F36xx_ALD_StdPeriph_Driver/Include/utils.h b/bsp/essemi/es32f369x/libraries/ES32F36xx_ALD_StdPeriph_Driver/Include/utils.h index b5589ce07a..e3b7242801 100644 --- a/bsp/essemi/es32f369x/libraries/ES32F36xx_ALD_StdPeriph_Driver/Include/utils.h +++ b/bsp/essemi/es32f369x/libraries/ES32F36xx_ALD_StdPeriph_Driver/Include/utils.h @@ -130,7 +130,7 @@ do { \ */ #define MCU_UID0_ADDR 0x000803E0U #define MCU_UID1_ADDR 0x000803E8U -#define MCU_UID2_ADDR 0x000803F0U +#define MCU_UID2_ADDR 0x000803ECU #define MCU_CHIPID_ADDR 0x000803F8U #define DWT_CR *(uint32_t *)0xE0001000U #define DWT_CYCCNT *(volatile uint32_t *)0xE0001004U @@ -170,6 +170,7 @@ void ald_systick_interval_select(systick_interval_t value); /* Peripheral Control functions */ void ald_inc_tick(void); void ald_systick_irq_cbk(void); +void ald_delay_us(__IO uint32_t delay); void ald_delay_ms(__IO uint32_t delay); uint32_t ald_get_tick(void); void ald_suspend_tick(void); diff --git a/bsp/essemi/es32f369x/libraries/ES32F36xx_ALD_StdPeriph_Driver/Source/ald_adc.c b/bsp/essemi/es32f369x/libraries/ES32F36xx_ALD_StdPeriph_Driver/Source/ald_adc.c index 6870742cc0..ebe1ff999e 100644 --- a/bsp/essemi/es32f369x/libraries/ES32F36xx_ALD_StdPeriph_Driver/Source/ald_adc.c +++ b/bsp/essemi/es32f369x/libraries/ES32F36xx_ALD_StdPeriph_Driver/Source/ald_adc.c @@ -133,19 +133,30 @@ ald_status_t ald_adc_init(adc_handle_t *hperh) MODIFY_REG(hperh->perh->CON1, ADC_CON1_CM_MSK, hperh->init.cont << ADC_CON1_CM_POS); MODIFY_REG(hperh->perh->CON0, ADC_CON0_SCANEN_MSK, hperh->init.scan << ADC_CON0_SCANEN_POS); - MODIFY_REG(hperh->perh->CCR, ADC_CCR_GAINCALEN_MSK, DISABLE << ADC_CCR_GAINCALEN_POS); - MODIFY_REG(hperh->perh->CCR, ADC_CCR_OFFCALEN_MSK, DISABLE << ADC_CCR_OFFCALEN_POS); - MODIFY_REG(hperh->perh->CCR, ADC_CCR_DIFFEN_MSK, DISABLE << ADC_CCR_DIFFEN_POS); + + ADC0->CCR = 0; + MODIFY_REG(ADC0->CCR, ADC_CCR_GAINCALEN_MSK, DISABLE << ADC_CCR_GAINCALEN_POS); + MODIFY_REG(ADC0->CCR, ADC_CCR_OFFCALEN_MSK, DISABLE << ADC_CCR_OFFCALEN_POS); /* if the ADC clock less than 1MHz,PWRMOD should be disable*/ - MODIFY_REG(hperh->perh->CCR, ADC_CCR_PWRMODSEL_MSK, DISABLE << ADC_CCR_PWRMODSEL_POS); - MODIFY_REG(hperh->perh->CCR, ADC_CCR_VRBUFEN_MSK, ENABLE << ADC_CCR_VRBUFEN_POS); - MODIFY_REG(hperh->perh->CCR, ADC_CCR_VCMBUFEN_MSK, ENABLE << ADC_CCR_VCMBUFEN_POS); - MODIFY_REG(hperh->perh->CCR, ADC_CCR_VREFEN_MSK, ENABLE << ADC_CCR_VREFEN_POS); - MODIFY_REG(hperh->perh->CCR, ADC_CCR_IREFEN_MSK, ENABLE << ADC_CCR_IREFEN_POS); + MODIFY_REG(ADC0->CCR, ADC_CCR_PWRMODSEL_MSK, DISABLE << ADC_CCR_PWRMODSEL_POS); + MODIFY_REG(ADC0->CCR, ADC_CCR_VRBUFEN_MSK, ENABLE << ADC_CCR_VRBUFEN_POS); + MODIFY_REG(ADC0->CCR, ADC_CCR_VCMBUFEN_MSK, ENABLE << ADC_CCR_VCMBUFEN_POS); + MODIFY_REG(ADC0->CCR, ADC_CCR_VREFEN_MSK, ENABLE << ADC_CCR_VREFEN_POS); + MODIFY_REG(ADC0->CCR, ADC_CCR_IREFEN_MSK, ENABLE << ADC_CCR_IREFEN_POS); + MODIFY_REG(ADC0->CCR, ADC_CCR_VRNSEL_MSK, hperh->init.n_ref << ADC_CCR_VRNSEL_POS); + MODIFY_REG(ADC0->CCR, ADC_CCR_VRPSEL_MSK, hperh->init.p_ref << ADC_CCR_VRPSEL_POSS); + + if (hperh->perh == ADC1) + ADC1->CCR = ADC0->CCR; + + MODIFY_REG(hperh->perh->CCR, ADC_CCR_DIFFEN_MSK, DISABLE << ADC_CCR_DIFFEN_POS); MODIFY_REG(hperh->perh->CCR, ADC_CCR_CKDIV_MSK, hperh->init.div << ADC_CCR_CKDIV_POSS); - MODIFY_REG(hperh->perh->CCR, ADC_CCR_VRNSEL_MSK, hperh->init.n_ref << ADC_CCR_VRNSEL_POS); - MODIFY_REG(hperh->perh->CCR, ADC_CCR_VRPSEL_MSK, hperh->init.p_ref << ADC_CCR_VRPSEL_POSS); - MODIFY_REG(hperh->perh->CON1, ADC_CON1_NCHESEL_MSK, hperh->init.nche_sel << ADC_CON1_NCHESEL_POS); + /* Enable adc calibration */ + SET_BIT(ADC0->CCR, ADC_CCR_TRMEN_MSK); + SET_BIT(ADC1->CCR, ADC_CCR_TRMEN_MSK); + + +MODIFY_REG(hperh->perh->CON1, ADC_CON1_NCHESEL_MSK, hperh->init.nche_sel << ADC_CON1_NCHESEL_POS); ald_adc_interrupt_config(hperh, ADC_IT_OVR, ENABLE); ADC_ENABLE(hperh); @@ -430,12 +441,12 @@ static void adc_dma_timer_trigger_cplt(void *arg) } /** - * @brief Config Timer trigger adc function + * @brief Config timer trigger adc insert channel conversion. * @param config: Pointer to a adc_timer_config_t structure that * contains the configuration information for the specified function. * @retval Status, see @ref ald_status_t. */ -ald_status_t ald_adc_timer_trigger_adc_by_dma(adc_timer_config_t *config) +ald_status_t ald_adc_timer_trigger_insert(adc_timer_config_t *config) { config->h_pis.perh = PIS; config->h_pis.init.producer_clk = PIS_CLK_PCLK1; @@ -467,13 +478,13 @@ ald_status_t ald_adc_timer_trigger_adc_by_dma(adc_timer_config_t *config) #endif if (config->p_adc == ADC0) - config->h_pis.init.consumer_trig = PIS_CH6_ADC0_NORMAL; + config->h_pis.init.consumer_trig = PIS_CH7_ADC0_INSERT; else return ERROR; ald_pis_create(&config->h_pis); - /* Initialize TIMER0 */ + /* Initialize TIMER */ config->h_timer.perh = config->p_timer; config->h_timer.init.prescaler = 0; config->h_timer.init.mode = TIMER_CNT_MODE_UP; @@ -486,7 +497,7 @@ ald_status_t ald_adc_timer_trigger_adc_by_dma(adc_timer_config_t *config) config->h_adc.init.align = ADC_DATAALIGN_RIGHT; config->h_adc.init.scan = DISABLE; config->h_adc.init.cont = DISABLE; - config->h_adc.init.nch_nr = ADC_NCH_NR_1; + config->h_adc.init.ich_nr = ADC_ICH_NR_1; config->h_adc.init.disc = ADC_ALL_DISABLE; config->h_adc.init.disc_nr = ADC_DISC_NR_1; config->h_adc.init.data_bit = ADC_CONV_BIT_12; @@ -500,49 +511,30 @@ ald_status_t ald_adc_timer_trigger_adc_by_dma(adc_timer_config_t *config) config->h_adc.error_cbk = NULL; config->h_adc.ovr_cbk = NULL; ald_adc_init(&config->h_adc); - - - - config->h_adc.perh->CON1 |= 0x10000000; - config->config.ch = config->adc_ch; - config->config.idx = ADC_NCH_IDX_1; - config->config.samp = ADC_SAMPLETIME_4; - ald_adc_normal_channel_config(&config->h_adc, &config->config); - - config->h_dma.cplt_cbk = adc_dma_timer_trigger_cplt; - config->h_dma.cplt_arg = config; - config->h_dma.err_cbk = adc_dma_error; - config->h_dma.err_arg = &config->h_adc; - - ald_dma_config_struct(&config->h_dma.config); - config->h_dma.perh = DMA0; - config->h_dma.config.src = (void *)&config->h_adc.perh->NCHDR; - config->h_dma.config.dst = (void *)config->buf; - config->h_dma.config.size = config->size; - config->h_dma.config.data_width = DMA_DATA_SIZE_HALFWORD; - config->h_dma.config.src_inc = DMA_DATA_INC_NONE; - config->h_dma.config.dst_inc = DMA_DATA_INC_HALFWORD; - config->h_dma.config.msel = config->p_adc == ADC0 ? DMA_MSEL_ADC0 : DMA_MSEL_ADC1; - config->h_dma.config.msigsel = DMA_MSIGSEL_ADC; - config->h_dma.config.burst = ENABLE; - config->h_dma.config.channel = config->dma_ch; - ald_dma_config_basic(&config->h_dma); - - SET_BIT(config->h_adc.perh->CON1, ADC_CON1_DMA_MSK); + + config->h_adc.perh->CON1 |= 0x00100000; /* rising edge trigger insert channel convert */ + config->i_config.ch = config->adc_ch; + config->i_config.idx = ADC_ICH_IDX_1; + config->i_config.samp = ADC_SAMPLETIME_4; + config->i_config.nr = ADC_ICH_NR_1; + config->i_config.auto_m = DISABLE; + ald_adc_insert_channel_config(&config->h_adc, &config->i_config); + ADC_ENABLE(&config->h_adc); ald_timer_base_start(&config->h_timer); - + return OK; } + /** - * @brief Config timer trigger adc insert channel conversion. + * @brief Config Timer trigger adc function * @param config: Pointer to a adc_timer_config_t structure that * contains the configuration information for the specified function. * @retval Status, see @ref ald_status_t. */ -ald_status_t ald_adc_timer_trigger_insert(adc_timer_config_t *config) +ald_status_t ald_adc_timer_trigger_adc_by_dma(adc_timer_config_t *config) { config->h_pis.perh = PIS; config->h_pis.init.producer_clk = PIS_CLK_PCLK1; @@ -574,7 +566,7 @@ ald_status_t ald_adc_timer_trigger_insert(adc_timer_config_t *config) #endif if (config->p_adc == ADC0) - config->h_pis.init.consumer_trig = PIS_CH7_ADC0_INSERT; + config->h_pis.init.consumer_trig = PIS_CH6_ADC0_NORMAL; else return ERROR; @@ -593,7 +585,7 @@ ald_status_t ald_adc_timer_trigger_insert(adc_timer_config_t *config) config->h_adc.init.align = ADC_DATAALIGN_RIGHT; config->h_adc.init.scan = DISABLE; config->h_adc.init.cont = DISABLE; - config->h_adc.init.ich_nr = ADC_ICH_NR_1; + config->h_adc.init.nch_nr = ADC_NCH_NR_1; config->h_adc.init.disc = ADC_ALL_DISABLE; config->h_adc.init.disc_nr = ADC_DISC_NR_1; config->h_adc.init.data_bit = ADC_CONV_BIT_12; @@ -608,12 +600,32 @@ ald_status_t ald_adc_timer_trigger_insert(adc_timer_config_t *config) config->h_adc.ovr_cbk = NULL; ald_adc_init(&config->h_adc); - config->h_adc.perh->CON1 |= 0x00100000; /* rising edge trigger insert channel convert */ - config->i_config.ch = config->adc_ch; - config->i_config.idx = ADC_ICH_IDX_1; - config->i_config.samp = ADC_SAMPLETIME_4; - config->i_config.auto_m = DISABLE; - ald_adc_insert_channel_config(&config->h_adc, &config->i_config); + config->h_adc.perh->CON1 |= 0x10000000; + config->config.ch = config->adc_ch; + config->config.idx = ADC_NCH_IDX_1; + config->config.samp = ADC_SAMPLETIME_4; + ald_adc_normal_channel_config(&config->h_adc, &config->config); + + config->h_dma.cplt_cbk = adc_dma_timer_trigger_cplt; + config->h_dma.cplt_arg = config; + config->h_dma.err_cbk = adc_dma_error; + config->h_dma.err_arg = &config->h_adc; + + ald_dma_config_struct(&config->h_dma.config); + config->h_dma.perh = DMA0; + config->h_dma.config.src = (void *)&config->h_adc.perh->NCHDR; + config->h_dma.config.dst = (void *)config->buf; + config->h_dma.config.size = config->size; + config->h_dma.config.data_width = DMA_DATA_SIZE_HALFWORD; + config->h_dma.config.src_inc = DMA_DATA_INC_NONE; + config->h_dma.config.dst_inc = DMA_DATA_INC_HALFWORD; + config->h_dma.config.msel = config->p_adc == ADC0 ? DMA_MSEL_ADC0 : DMA_MSEL_ADC1; + config->h_dma.config.msigsel = DMA_MSIGSEL_ADC; + config->h_dma.config.burst = ENABLE; + config->h_dma.config.channel = config->dma_ch; + ald_dma_config_basic(&config->h_dma); + + SET_BIT(config->h_adc.perh->CON1, ADC_CON1_DMA_MSK); ADC_ENABLE(&config->h_adc); ald_timer_base_start(&config->h_timer); diff --git a/bsp/essemi/es32f369x/libraries/ES32F36xx_ALD_StdPeriph_Driver/Source/ald_can.c b/bsp/essemi/es32f369x/libraries/ES32F36xx_ALD_StdPeriph_Driver/Source/ald_can.c index ec9ec28260..fb97024cd1 100644 --- a/bsp/essemi/es32f369x/libraries/ES32F36xx_ALD_StdPeriph_Driver/Source/ald_can.c +++ b/bsp/essemi/es32f369x/libraries/ES32F36xx_ALD_StdPeriph_Driver/Source/ald_can.c @@ -99,6 +99,7 @@ static void can_rx_fifo_release(can_handle_t *hperh, can_rx_fifo_t num); static ald_status_t __can_send_by_it(can_handle_t *hperh, uint8_t err); static ald_status_t __can_recv_by_it(can_handle_t *hperh, can_rx_fifo_t num); +static int __can_rx_check(can_handle_t *hperh, can_rx_fifo_t num); /** * @} */ @@ -138,7 +139,7 @@ ald_status_t ald_can_init(can_handle_t *hperh) assert_param(IS_FUNC_STATE(hperh->init.ttcm)); assert_param(IS_FUNC_STATE(hperh->init.abom)); assert_param(IS_FUNC_STATE(hperh->init.awk)); - assert_param(IS_FUNC_STATE(hperh->init.abom)); + assert_param(IS_FUNC_STATE(hperh->init.artx)); assert_param(IS_FUNC_STATE(hperh->init.rfom)); assert_param(IS_FUNC_STATE(hperh->init.txmp)); assert_param(IS_CAN_MODE(hperh->init.mode)); @@ -442,6 +443,9 @@ ald_status_t ald_can_recv(can_handle_t *hperh, can_rx_fifo_t num, can_rx_msg_t * } } + if (__can_rx_check(hperh, num)) + return ERROR; + stid = READ_BITS(hperh->perh->RxFIFO[num].RXFID, CAN_RXF0ID_STDID_MSK, CAN_RXF0ID_STDID_POSS); exid = READ_BITS(hperh->perh->RxFIFO[num].RXFID, CAN_RXF0ID_EXID_MSK, CAN_RXF0ID_EXID_POSS); msg->type = (can_id_type_t)READ_BITS(hperh->perh->RxFIFO[num].RXFID, CAN_RXF0ID_IDE_MSK, CAN_RXF0ID_IDE_POS); diff --git a/bsp/essemi/es32f369x/libraries/ES32F36xx_ALD_StdPeriph_Driver/Source/ald_cmu.c b/bsp/essemi/es32f369x/libraries/ES32F36xx_ALD_StdPeriph_Driver/Source/ald_cmu.c index 8beb08de5b..670546d515 100644 --- a/bsp/essemi/es32f369x/libraries/ES32F36xx_ALD_StdPeriph_Driver/Source/ald_cmu.c +++ b/bsp/essemi/es32f369x/libraries/ES32F36xx_ALD_StdPeriph_Driver/Source/ald_cmu.c @@ -290,12 +290,11 @@ ald_status_t ald_cmu_clock_config_default(void) return ERROR; } - WRITE_REG(CMU->CFGR, 0x0); - CLEAR_BIT(CMU->CFGR, CMU_CFGR_HRCFST_MSK); /* Select 24Mhz */ + WRITE_REG(CMU->CFGR, 0x4000000); /* Select 24MHz */ tmp = READ_REG(CMU->CLKENR); - /* Enable HRC/LRC/LOSC */ - SET_BIT(tmp, CMU_CLKENR_HRCEN_MSK | CMU_CLKENR_LRCEN_MSK | CMU_CLKENR_LOSCEN_MSK); + /* Enable HRC/LRC */ + SET_BIT(tmp, CMU_CLKENR_HRCEN_MSK | CMU_CLKENR_LRCEN_MSK); WRITE_REG(CMU->CLKENR, tmp); /* Reset LRC */ for (cnt = 0; cnt < 10000; ++cnt); diff --git a/bsp/essemi/es32f369x/libraries/ES32F36xx_ALD_StdPeriph_Driver/Source/ald_dma.c b/bsp/essemi/es32f369x/libraries/ES32F36xx_ALD_StdPeriph_Driver/Source/ald_dma.c index eae14f80c3..a12c72b371 100644 --- a/bsp/essemi/es32f369x/libraries/ES32F36xx_ALD_StdPeriph_Driver/Source/ald_dma.c +++ b/bsp/essemi/es32f369x/libraries/ES32F36xx_ALD_StdPeriph_Driver/Source/ald_dma.c @@ -186,19 +186,20 @@ void ald_dma_irq_handler(void) uint32_t i, reg = DMA0->IFLAG; for (i = 0; i < DMA_CH_COUNT; ++i) { - if (READ_BIT(reg, (1 << i))) { + if (READ_BIT(reg, (1U << i))) { + DMA0->ICFR = (1U << i); + DMA0->CHENCLR = (1U << i); + if (dma0_cbk[i].cplt_cbk != NULL) dma0_cbk[i].cplt_cbk(dma0_cbk[i].cplt_arg); - - ald_dma_clear_flag_status(DMA0, i); } } if (READ_BIT(reg, (1U << DMA_ERR))) { - ald_dma_clear_flag_status(DMA0, DMA_ERR); + DMA0->ICFR = (1U << DMA_ERR); for (i = 0; i < DMA_CH_COUNT; ++i) { - if (((DMA0->CHENSET >> i) & 0x1) && (dma0_cbk[i].err_cbk != NULL)) + if (dma0_cbk[i].err_cbk != NULL) dma0_cbk[i].err_cbk(dma0_cbk[i].err_arg); } } diff --git a/bsp/essemi/es32f369x/libraries/ES32F36xx_ALD_StdPeriph_Driver/Source/ald_gpio.c b/bsp/essemi/es32f369x/libraries/ES32F36xx_ALD_StdPeriph_Driver/Source/ald_gpio.c index 255c569463..8285401f26 100644 --- a/bsp/essemi/es32f369x/libraries/ES32F36xx_ALD_StdPeriph_Driver/Source/ald_gpio.c +++ b/bsp/essemi/es32f369x/libraries/ES32F36xx_ALD_StdPeriph_Driver/Source/ald_gpio.c @@ -415,9 +415,9 @@ void ald_gpio_write_pin(GPIO_TypeDef *GPIOx, uint16_t pin, uint8_t val) assert_param(IS_GPIO_PIN(pin)); if ((val & (0x01)) == 0x00) - CLEAR_BIT(GPIOx->DOUT, pin); + GPIOx->BSRR = pin << 16U; else - SET_BIT(GPIOx->DOUT, pin); + GPIOx->BSRR = pin; return; } diff --git a/bsp/essemi/es32f369x/libraries/ES32F36xx_ALD_StdPeriph_Driver/Source/ald_nand.c b/bsp/essemi/es32f369x/libraries/ES32F36xx_ALD_StdPeriph_Driver/Source/ald_nand.c index cc178feb7f..6008dcde08 100644 --- a/bsp/essemi/es32f369x/libraries/ES32F36xx_ALD_StdPeriph_Driver/Source/ald_nand.c +++ b/bsp/essemi/es32f369x/libraries/ES32F36xx_ALD_StdPeriph_Driver/Source/ald_nand.c @@ -305,7 +305,9 @@ ald_status_t ald_nand_read_page_8b(nand_handle_t *hperh, nand_address_t *addr, u *(__IO uint8_t *)((uint32_t)(deviceaddr | CMD_AREA)) = ((uint8_t)0x00); } - /* Get Data into Buffer */ + ald_delay_us(25); /*ʱ25us,nand flash ֲеֵ*/ + + /* Get Data into Buffer */ for (; index < size; index++) { *(uint8_t *)buf++ = *(uint8_t *)deviceaddr; } diff --git a/bsp/essemi/es32f369x/libraries/ES32F36xx_ALD_StdPeriph_Driver/Source/ald_timer.c b/bsp/essemi/es32f369x/libraries/ES32F36xx_ALD_StdPeriph_Driver/Source/ald_timer.c index 7860499237..49c6be5d1c 100644 --- a/bsp/essemi/es32f369x/libraries/ES32F36xx_ALD_StdPeriph_Driver/Source/ald_timer.c +++ b/bsp/essemi/es32f369x/libraries/ES32F36xx_ALD_StdPeriph_Driver/Source/ald_timer.c @@ -737,7 +737,7 @@ void ald_timer_pwm_stop_by_dma(timer_handle_t *hperh, timer_channel_t ch) * @param freq: PWM freq to set * @retval None */ -void ald_timer_pwm_set_freq(timer_handle_t *hperh, uint16_t freq) +void ald_timer_pwm_set_freq(timer_handle_t *hperh, uint32_t freq) { uint32_t _arr; @@ -758,12 +758,12 @@ void ald_timer_pwm_set_freq(timer_handle_t *hperh, uint16_t freq) * @arg TIMER_CHANNEL_2: TIMER Channel 2 selected * @arg TIMER_CHANNEL_3: TIMER Channel 3 selected * @arg TIMER_CHANNEL_4: TIMER Channel 4 selected - * @param duty: PWM duty to set + * @param duty: PWM duty to set [0, 100] * @retval None */ void ald_timer_pwm_set_duty(timer_handle_t *hperh, timer_channel_t ch, uint16_t duty) { - uint32_t tmp = (hperh->init.period + 1) * duty / 100 - 1; + uint32_t tmp = (hperh->init.period + 1) * duty / 100; if (ch == TIMER_CHANNEL_1) WRITE_REG(hperh->perh->CCVAL1, tmp); diff --git a/bsp/essemi/es32f369x/libraries/ES32F36xx_ALD_StdPeriph_Driver/Source/ald_uart.c b/bsp/essemi/es32f369x/libraries/ES32F36xx_ALD_StdPeriph_Driver/Source/ald_uart.c index 84c96348c6..44327be3f7 100644 --- a/bsp/essemi/es32f369x/libraries/ES32F36xx_ALD_StdPeriph_Driver/Source/ald_uart.c +++ b/bsp/essemi/es32f369x/libraries/ES32F36xx_ALD_StdPeriph_Driver/Source/ald_uart.c @@ -144,12 +144,29 @@ static void uart_dma_send_cplt(void *arg) */ static void uart_dma_recv_cplt(void *arg) { + uint32_t stat = 0; + uart_handle_t *hperh = (uart_handle_t *)arg; hperh->tx_count = hperh->tx_size; ald_uart_dma_req_config(hperh, UART_DMA_REQ_RX, DISABLE); hperh->rx_count = 0; CLEAR_BIT(hperh->state, UART_STATE_RX_MASK); + stat = hperh->perh->STAT; + + /* Handle parity error */ + if ((READ_BIT(stat, UART_STATUS_PERR)) != RESET) + hperh->err_code |= UART_ERROR_PE; + + /* Handle frame error */ + if ((READ_BIT(stat, UART_STATUS_FERR)) != RESET) + hperh->err_code |= UART_ERROR_FE; + + /* Handle rx overflow error */ + if ((READ_BIT(stat, UART_STATUS_RFOERR)) != RESET) { + hperh->err_code |= UART_ERROR_ORE; + UART_FIFO_RX_RESET(hperh); + } if (hperh->rx_cplt_cbk) hperh->rx_cplt_cbk(hperh); @@ -552,12 +569,16 @@ ald_status_t ald_uart_send(uart_handle_t *hperh, uint8_t *buf, uint16_t size, ui */ ald_status_t ald_uart_recv(uart_handle_t *hperh, uint8_t *buf, uint16_t size, uint32_t timeout) { + uint32_t stat = 0; + uint32_t err = 0; + uint32_t tick = 0; + assert_param(IS_UART_ALL(hperh->perh)); if ((hperh->state != UART_STATE_READY) && (hperh->state != UART_STATE_BUSY_TX)) return BUSY; - if ((buf == NULL) || (size == 0)) + if ((buf == NULL) || (size == 0) || (timeout == 0)) return ERROR; __LOCK(hperh); @@ -568,15 +589,47 @@ ald_status_t ald_uart_recv(uart_handle_t *hperh, uint8_t *buf, uint16_t size, ui hperh->rx_count = 0; SET_BIT(hperh->perh->FCON, UART_FCON_RFRST_MSK); + err = (UART_STATUS_PERR | UART_STATUS_FERR | UART_STATUS_RFOERR); + while (size-- > 0) { - if (uart_wait_flag(hperh, UART_STATUS_RFTH, SET, timeout) != OK) { - __UNLOCK(hperh); - hperh->state = UART_STATE_READY; - return TIMEOUT; + tick = ald_get_tick(); + + /* Waiting for flag */ + while (1) { + stat = hperh->perh->STAT; + if (READ_BIT(stat, UART_STATUS_RFTH) != RESET) + break; + + if (((ald_get_tick()) - tick) > timeout) { + __UNLOCK(hperh); + hperh->state = UART_STATE_READY; + return TIMEOUT; + } } + if ((stat & err) == RESET) { + *buf++ = (uint8_t)(hperh->perh->RXBUF & 0xFF); + hperh->rx_count++; + } + else { + /* Handle parity error */ + if ((READ_BIT(stat, UART_STATUS_PERR)) != RESET) + hperh->err_code |= UART_ERROR_PE; - *buf++ = (uint8_t)(hperh->perh->RXBUF & 0xFF); - hperh->rx_count++; + /* Handle frame error */ + if ((READ_BIT(stat, UART_STATUS_FERR)) != RESET) + hperh->err_code |= UART_ERROR_FE; + + /* Handle rx overflow error */ + if ((READ_BIT(stat, UART_STATUS_RFOERR)) != RESET) { + hperh->err_code |= UART_ERROR_ORE; + UART_FIFO_RX_RESET(hperh); + } + + CLEAR_BIT(hperh->state, UART_STATE_RX_MASK); + __UNLOCK(hperh); + + return ERROR; + } } CLEAR_BIT(hperh->state, UART_STATE_RX_MASK); @@ -898,7 +951,7 @@ ald_status_t ald_uart_recv_by_dma(uart_handle_t *hperh, uint8_t *buf, uint16_t s hperh->hdmarx.config.msigsel = DMA_MSIGSEL_UART_RNR; } - hperh->hdmatx.config.burst = ENABLE; + hperh->hdmarx.config.burst = ENABLE; hperh->hdmarx.config.channel = channel; if (hperh->init.mode == UART_MODE_RS485) { @@ -915,9 +968,9 @@ ald_status_t ald_uart_recv_by_dma(uart_handle_t *hperh, uint8_t *buf, uint16_t s else if (hperh->perh == UART3) hperh->hdmarx.config.msel = DMA_MSEL_UART3; else if (hperh->perh == UART4) - hperh->hdmatx.config.msel = DMA_MSEL_UART4; + hperh->hdmarx.config.msel = DMA_MSEL_UART4; else if (hperh->perh == UART5) - hperh->hdmatx.config.msel = DMA_MSEL_UART5; + hperh->hdmarx.config.msel = DMA_MSEL_UART5; else ; @@ -980,27 +1033,35 @@ ald_status_t ald_uart_dma_stop(uart_handle_t *hperh) */ void ald_uart_irq_handler(uart_handle_t *hperh) { + uint32_t stat = 0; + assert_param(IS_UART_ALL(hperh->perh)); + stat = hperh->perh->STAT; + /* Handle parity error */ - if (((ald_uart_get_status(hperh, UART_STATUS_PERR)) != RESET) && \ + if (((READ_BIT(stat, UART_STATUS_PERR)) != RESET) && \ (ald_uart_get_state(hperh)) == UART_STATE_RX_MASK) hperh->err_code |= UART_ERROR_PE; /* Handle frame error */ - if (((ald_uart_get_status(hperh, UART_STATUS_FERR)) != RESET) && \ + if (((READ_BIT(stat, UART_STATUS_FERR)) != RESET) && \ (ald_uart_get_state(hperh)) == UART_STATE_RX_MASK) hperh->err_code |= UART_ERROR_FE; /* Handle rx overflow error */ - if (((ald_uart_get_status(hperh, UART_STATUS_RFOERR)) != RESET) && \ - (ald_uart_get_state(hperh)) == UART_STATE_RX_MASK) + if (((READ_BIT(stat, UART_STATUS_RFOERR)) != RESET) && \ + (ald_uart_get_state(hperh)) == UART_STATE_RX_MASK) { hperh->err_code |= UART_ERROR_ORE; + UART_FIFO_RX_RESET(hperh); + } /* Handle tx overflow error */ - if (((ald_uart_get_status(hperh, UART_STATUS_TFOERR)) != RESET) && \ - (ald_uart_get_state(hperh)) == UART_STATE_TX_MASK) + if (((READ_BIT(stat, UART_STATUS_TFOERR)) != RESET) && \ + (ald_uart_get_state(hperh)) == UART_STATE_TX_MASK) { hperh->err_code |= UART_ERROR_ORE; + UART_FIFO_TX_RESET(hperh); + } /* Receive */ if ((ald_uart_get_mask_flag_status(hperh, UART_IF_RFTH)) != RESET) { diff --git a/bsp/essemi/es32f369x/libraries/ES32F36xx_ALD_StdPeriph_Driver/Source/utils.c b/bsp/essemi/es32f369x/libraries/ES32F36xx_ALD_StdPeriph_Driver/Source/utils.c index d2c5bfecb6..d57bc6e25b 100644 --- a/bsp/essemi/es32f369x/libraries/ES32F36xx_ALD_StdPeriph_Driver/Source/utils.c +++ b/bsp/essemi/es32f369x/libraries/ES32F36xx_ALD_StdPeriph_Driver/Source/utils.c @@ -4,10 +4,14 @@ * @file utils.c * @brief This file contains the Utilities functions/types for the driver. * - * @version V1.0 - * @date 07 Nov 2019 + * @version V1.1 + * @date 13 Apr 2021 * @author AE Team * @note + * Change Logs: + * Date Author Notes + * 07 Nov 2019 AE Team The first version + * 13 Apr 2021 AE Team Add API: sys_config() * * Copyright (C) Shanghai Eastsoft Microelectronics Co. Ltd. All rights reserved. * @@ -31,7 +35,8 @@ #include #include "utils.h" #include "ald_dma.h" -#include "ald_cmu.h" +#include "ald_cmu.h" +#include "ald_iap.h" /** @defgroup ES32FXXX_ALD EASTSOFT ES32F3xx ALD @@ -152,9 +157,9 @@ void ald_cmu_init(void) __weak void ald_tick_init(uint32_t prio) { /* Configure the SysTick IRQ */ - NVIC_SetPriority(SysTick_IRQn, prio); SysTick_Config(ald_cmu_get_sys_clock() / SYSTICK_INTERVAL_1MS); - + NVIC_SetPriority(SysTick_IRQn, prio); + return; } @@ -246,6 +251,31 @@ __weak uint32_t ald_get_tick(void) { return lib_tick; } + +/** + * @brief This function provides accurate delay (in milliseconds) based + * on variable incremented. + * @note In the default implementation, SysTick timer is the source of time base. + * It is used to generate interrupts at regular time intervals where lib_tick + * is incremented. + * @note This function is declared as __weak to be overwritten in case of other + * implementations in user file. + * @param delay: specifies the delay time length, in microseconds(us). + * @retval None + */ +__weak void ald_delay_us(__IO uint32_t delay) +{ + uint32_t start, now, delta, reload, us_tick; + start = SysTick->VAL; + reload = SysTick->LOAD; + us_tick = ald_cmu_get_sys_clock() / 1000000UL; + do + { + now = SysTick->VAL; + delta = (start > now) ? (start - now) : (reload + start - now); + } + while (delta < (us_tick * delay)); +} /** * @brief This function provides accurate delay (in milliseconds) based @@ -467,6 +497,205 @@ uint32_t ald_mcu_get_chipid(void) { return (uint32_t)*(uint32_t *)MCU_CHIPID_ADDR; } + +/** + * @brief Bypass bootroom and set VR1_Ref 0xA + * @retval None + */ +void sys_config(void) +{ + uint32_t i = 0, tmp = 0; + uint8_t err = 0, flag = 0; + uint32_t inf014 = 0, inf0154 = 0; + uint8_t cnt = 4; + + uint32_t *inf0_addr = (uint32_t *)0x20003C00; + /* read bootroom cfg register */ + inf014 = *((uint32_t *)(0x80000 + 56)); + /* read VR1_VREF register */ + inf0154 = *((uint32_t *)(0x80000 + 616)); + + if (inf0154 == 0xFFFFFFFF) + while(1); + + /* if bypass bootroom */ + if ((0xFFFFFFFF != inf014)) { + /* change cfg_boot value = 0xffff */ + inf014 = 0xFFFFFFFF; + flag = 0x1; + } + + /* change CFG_VR1_VREF value, FLASH ref 0xA */ + tmp = (inf0154 >> 8) & 0xF; + if (0xA != tmp) { + inf0154 &= ~(0xF << 8); + inf0154 |= (0xA << 8); + inf0154 = (inf0154 & (0x0000FFFF)) | ((~(inf0154 & 0xFFFF)) << 16); + flag = 0x1; + } + + /* if flag reset, return */ + if (0x0 == flag) + return; + + /* 0x80000, 256words,INFO0 value */ + for (i = 0; i < 256; i++) + inf0_addr[i] = *((uint32_t *)(0x80000 + i * 4)); + + /* refresh value */ + inf0_addr[14] = inf014; + inf0_addr[154] = inf0154; + + while(--cnt) { + err = 0; + /* unlock */ + *((volatile uint32_t *)(0x40080000)) = 0x55AA6996; + *((volatile uint32_t *)(0x40080100)) = 0x5A962814; + *((volatile uint32_t *)(0x40080100)) = 0xE7CB69A5; + + /* erase */ + if (ald_iap_erase_page(0x80000) == OK) { + /* program 256*4bytes, info0 */ + if (ald_iap_program_words(0x80000, (uint8_t *)inf0_addr, 1024, 0) == OK) { + /* check */ + for (i = 0; i < 256; i++) { + if (inf0_addr[i] != *((uint32_t *)(0x80000 + i * 4))) { + err = 1; + break;; + } + } + if (err == 0) { + /* lock */ + *((volatile uint32_t *)(0x40080100)) = 0x123456; + *((volatile uint32_t *)(0x40080100)) = 0x123456; + *((volatile uint32_t *)(0x40080000)) = 0x123456; + return; + } + } + else { + err = 1; + } + } + else { + err = 1; + } + } + + if (err) { + ald_iap_erase_page(0x80000); + /* lock */ + *((volatile uint32_t *)(0x40080100)) = 0x123456; + *((volatile uint32_t *)(0x40080100)) = 0x123456; + *((volatile uint32_t *)(0x40080000)) = 0x123456; + while(1); + } +} + +/** + * @brief ADC adjust parameter config + * @retval None + */ +void adc_config(void) +{ + uint32_t inf0176 = 0, inf0178 = 0; + uint32_t inf0250 = 0, inf0251 = 0; + uint32_t inf0242 = 0, i = 0; + uint8_t flag = 0, err = 0; + uint8_t cnt = 4; + /* ram store inf0 1k buffer, 15k ~ 16k */ + uint32_t *inf0_addr = (uint32_t *)0x20003C00; + + /* Read ADC_GE */ + inf0242 = *((uint32_t *)(0x80000 + 968)); + + if (0xF5230ADC == inf0242) return; + + /* read Lot ID */ + inf0250 = *((uint32_t *)(0x80000 + 1000)); + inf0251 = *((uint32_t *)(0x80000 + 1004)); + inf0251 = (inf0251 & 0xFFFF0000) >> 16; + + /* read CFG_ADC0DA/CFG_ADC1DA */ + inf0176 = *((uint32_t *)(0x80000 + 704)); + inf0178 = *((uint32_t *)(0x80000 + 712)); + + switch(inf0250) { + case 0x45465537: + if ((inf0251 == 0x3034) || (inf0251 == 0x3035)) + flag = 1; + break; + case 0x45503931: + if ((inf0251 == 0x3732) || (inf0251 == 0x3734)) + flag = 1; + break; + case 0x45503935: + if ((inf0251 == 0x3837) || (inf0251 == 0x3839)) + flag = 1; + break; + default: + break; + } + + if (!flag) return; + + inf0176 ^= (0x1 << 15); + inf0176 = (inf0176 & 0x0000FFFF) | ((~(inf0176 & 0xFFFF)) << 16); + + inf0178 ^= (0x1 << 15); + inf0178 = (inf0178 & 0x0000FFFF) | ((~(inf0178 & 0xFFFF)) << 16); + + /* 0x80000, 256words,INFO0 value */ + for (i = 0; i < 256; i++) + inf0_addr[i] = *((uint32_t *)(0x80000 + i * 4)); + + inf0_addr[176] = inf0176; + inf0_addr[178] = inf0178; + inf0_addr[242] = 0xF5230ADC; + + while(--cnt) { + err = 0; + /* unlock */ + *((volatile uint32_t *)(0x40080000)) = 0x55AA6996; + *((volatile uint32_t *)(0x40080100)) = 0x5A962814; + *((volatile uint32_t *)(0x40080100)) = 0xE7CB69A5; + + /* erase */ + if (ald_iap_erase_page(0x80000) == OK) { + /* program 256*4bytes, info0 */ + if (ald_iap_program_words(0x80000, (uint8_t *)inf0_addr, 1024, 0) == OK) { + /* check */ + for (i = 0; i < 256; i++) { + if (inf0_addr[i] != *((uint32_t *)(0x80000 + i * 4))) { + err = 1; + break;; + } + } + if (err == 0) { + /* lock */ + *((volatile uint32_t *)(0x40080100)) = 0x123456; + *((volatile uint32_t *)(0x40080100)) = 0x123456; + *((volatile uint32_t *)(0x40080000)) = 0x123456; + return; + } + } + else { + err = 1; + } + } + else { + err = 1; + } + } + + if (err) { + ald_iap_erase_page(0x80000); + /* lock */ + *((volatile uint32_t *)(0x40080100)) = 0x123456; + *((volatile uint32_t *)(0x40080100)) = 0x123456; + *((volatile uint32_t *)(0x40080000)) = 0x123456; + while(1); + } +} /** * @} */ -- cgit v1.3.1 From 0f6a75399218d732b968e07dd9216224c2cff1fd Mon Sep 17 00:00:00 2001 From: liuhy Date: Fri, 10 Sep 2021 18:13:18 +0800 Subject: update es32f0654 , es32f369x drivers. --- bsp/essemi/es32f0654/drivers/board.c | 2 + .../drivers/bsp_driver_example/i2c_sample.c | 4 -- .../drivers/bsp_driver_example/led_blink_sample.c | 3 +- .../drivers/bsp_driver_example/pin_beep_sample.c | 7 +-- .../drivers/bsp_driver_example/pm_sample.c | 3 +- .../drivers/bsp_driver_example/pwm_led_sample.c | 6 +-- .../drivers/bsp_driver_example/uart_sample.c | 57 ++++++++++++++++++++-- bsp/essemi/es32f0654/drivers/drv_can.c | 8 +-- bsp/essemi/es32f0654/drivers/drv_gpio.c | 12 +++-- bsp/essemi/es32f0654/drivers/drv_gpio.h | 2 + bsp/essemi/es32f0654/drivers/drv_i2c.c | 6 +-- bsp/essemi/es32f369x/drivers/board.c | 2 + .../drivers/bsp_driver_example/i2c_sample.c | 4 -- .../drivers/bsp_driver_example/led_blink_sample.c | 5 +- .../drivers/bsp_driver_example/pin_beep_sample.c | 9 ++-- .../drivers/bsp_driver_example/pm_sample.c | 11 ++--- .../drivers/bsp_driver_example/pwm_led_sample.c | 8 +-- .../drivers/bsp_driver_example/uart_sample.c | 57 ++++++++++++++++++++-- bsp/essemi/es32f369x/drivers/drv_adc.c | 4 +- bsp/essemi/es32f369x/drivers/drv_can.c | 8 +-- bsp/essemi/es32f369x/drivers/drv_gpio.c | 20 +++++--- bsp/essemi/es32f369x/drivers/drv_gpio.h | 2 + bsp/essemi/es32f369x/drivers/drv_i2c.c | 10 ++-- bsp/essemi/es32f369x/drivers/drv_spi.c | 4 +- bsp/essemi/es32f369x/drivers/drv_uart.c | 4 +- 25 files changed, 186 insertions(+), 72 deletions(-) (limited to 'bsp') diff --git a/bsp/essemi/es32f0654/drivers/board.c b/bsp/essemi/es32f0654/drivers/board.c index 7411168324..1719d06e20 100644 --- a/bsp/essemi/es32f0654/drivers/board.c +++ b/bsp/essemi/es32f0654/drivers/board.c @@ -127,6 +127,8 @@ void SysTick_Configuration(void) { /* ticks = sysclk / RT_TICK_PER_SECOND */ SysTick_Config(ald_cmu_get_sys_clock() / RT_TICK_PER_SECOND); + + __systick_interval = 1; } /** diff --git a/bsp/essemi/es32f0654/drivers/bsp_driver_example/i2c_sample.c b/bsp/essemi/es32f0654/drivers/bsp_driver_example/i2c_sample.c index c8a666609d..92a96b2e85 100644 --- a/bsp/essemi/es32f0654/drivers/bsp_driver_example/i2c_sample.c +++ b/bsp/essemi/es32f0654/drivers/bsp_driver_example/i2c_sample.c @@ -64,8 +64,6 @@ static void i2c_io_sample(int argc, char *argv[]) temp_msg.flags = RT_I2C_RD; /* I2C读 */ s_stat = rt_i2c_transfer(i2c_bus,&temp_msg,num_msg); /* 传输消息 */ - rt_thread_mdelay(400); - if( s_stat == num_msg ) { rt_kprintf("receive successful. \n receive messege : %s \n:",buffer); @@ -87,8 +85,6 @@ static void i2c_io_sample(int argc, char *argv[]) temp_msg.flags = RT_I2C_WR; /* I2C写 */ s_stat = rt_i2c_transfer(i2c_bus,&temp_msg,num_msg); /* 传输一条 */ - rt_thread_mdelay(400); - if( s_stat == num_msg ) { rt_kprintf(" send successful \n messege : %s \n:",buffer); diff --git a/bsp/essemi/es32f0654/drivers/bsp_driver_example/led_blink_sample.c b/bsp/essemi/es32f0654/drivers/bsp_driver_example/led_blink_sample.c index 42c956a060..fb5a98a279 100644 --- a/bsp/essemi/es32f0654/drivers/bsp_driver_example/led_blink_sample.c +++ b/bsp/essemi/es32f0654/drivers/bsp_driver_example/led_blink_sample.c @@ -19,9 +19,10 @@ #include #include #include +#include "drv_gpio.h" /* PIN脚编号，查看驱动文件drv_gpio.c确定 */ -#define LED_PIN_NUM 40 /*PB9*/ +#define LED_PIN_NUM GET_PIN(B,9) /*PB9*/ static int pin_num; static void led_entry(void *parameter) diff --git a/bsp/essemi/es32f0654/drivers/bsp_driver_example/pin_beep_sample.c b/bsp/essemi/es32f0654/drivers/bsp_driver_example/pin_beep_sample.c index 29dfbe1b2f..03e6b14ba1 100644 --- a/bsp/essemi/es32f0654/drivers/bsp_driver_example/pin_beep_sample.c +++ b/bsp/essemi/es32f0654/drivers/bsp_driver_example/pin_beep_sample.c @@ -16,16 +16,17 @@ #include #include +#include "drv_gpio.h" /* 引脚编号，通过查看驱动文件drv_gpio.c确定 */ #ifndef BEEP_PIN_NUM - #define BEEP_PIN_NUM 40 /* PB9 */ + #define BEEP_PIN_NUM GET_PIN(B,9) /* PB9 */ #endif #ifndef KEY0_PIN_NUM - #define KEY0_PIN_NUM 18 /* PF0 */ + #define KEY0_PIN_NUM GET_PIN(F,0) /* PF0 */ #endif #ifndef KEY1_PIN_NUM - #define KEY1_PIN_NUM 19 /* PF1 */ + #define KEY1_PIN_NUM GET_PIN(F,1) /* PF1 */ #endif void beep_on(void *args) diff --git a/bsp/essemi/es32f0654/drivers/bsp_driver_example/pm_sample.c b/bsp/essemi/es32f0654/drivers/bsp_driver_example/pm_sample.c index 78358e421c..d960bdd139 100644 --- a/bsp/essemi/es32f0654/drivers/bsp_driver_example/pm_sample.c +++ b/bsp/essemi/es32f0654/drivers/bsp_driver_example/pm_sample.c @@ -30,11 +30,12 @@ #include #include +#include "drv_gpio.h" #ifdef RT_USING_PM #define PM_NAME "pm" /* 设备名称 */ -#define WAKE_UP_PIN 19 /* 唤醒源 */ +#define WAKE_UP_PIN GET_PIN(F,0) /* 唤醒源 */ #define SLEEP_TIMES 12 /* 进入睡眠次数，轮流进入不同的睡眠模式，包括无睡眠模式 */ diff --git a/bsp/essemi/es32f0654/drivers/bsp_driver_example/pwm_led_sample.c b/bsp/essemi/es32f0654/drivers/bsp_driver_example/pwm_led_sample.c index 23ecfd227e..c2a0ed8fee 100644 --- a/bsp/essemi/es32f0654/drivers/bsp_driver_example/pwm_led_sample.c +++ b/bsp/essemi/es32f0654/drivers/bsp_driver_example/pwm_led_sample.c @@ -16,13 +16,13 @@ #include #include - +#include "drv_gpio.h" #ifdef RT_USING_PWM -#define LED_PIN_NUM 16 /* LED PIN脚编号，查看驱动文件drv_gpio.c确定 */ +#define LED_PIN_NUM GET_PIN(A,2) /* LED PIN脚编号，查看驱动文件drv_gpio.c确定 */ #define PWM_DEV_NAME "pwm1" /* PWM设备名称 */ -#define PWM_DEV_CHANNEL 1 /* PA8 PWM通道 */ +#define PWM_DEV_CHANNEL 1 /* PWM通道 */ struct rt_device_pwm *pwm_dev; /* PWM设备句柄 */ diff --git a/bsp/essemi/es32f0654/drivers/bsp_driver_example/uart_sample.c b/bsp/essemi/es32f0654/drivers/bsp_driver_example/uart_sample.c index cb750efe6e..efd893de21 100644 --- a/bsp/essemi/es32f0654/drivers/bsp_driver_example/uart_sample.c +++ b/bsp/essemi/es32f0654/drivers/bsp_driver_example/uart_sample.c @@ -12,16 +12,28 @@ * 例程导出了 uart_sample 命令到控制终端 * 命令调用格式：uart_sample uart2 * 命令解释：命令第二个参数是要使用的串口设备名称，为空则使用默认的串口设备 - * 程序功能：通过串口输出字符串"hello RT-Thread!"，然后错位输出输入的字符 + * 程序功能：通过串口输出字符串"hello RT-Thread!"，然后根据例子类型，处理输入数据，然后输出 */ #include -#define SAMPLE_UART_NAME "uart2" /* 串口设备名称 */ +/* UART_SAMPLE_TYPE = 1,错位输出 + = 2 接收到固定格式之后输出 +*/ +#define UART_SAMPLE_TYPE 1 + +#if (UART_SAMPLE_TYPE == 2) + +#define SAMPLE_UART_RXBUF_SIZE 256 /* 接收缓存大小 */ +#define SAMPLE_UART_END_SRTING "\r\n" /* 结尾固定格式 */ + +#endif + +#define SAMPLE_UART_NAME "uart0" /* 串口设备名称 */ /* 用于接收消息的信号量 */ static struct rt_semaphore rx_sem; -static rt_device_t serial; +static rt_device_t serial; /* 接收数据回调函数 */ static rt_err_t uart_input(rt_device_t dev, rt_size_t size) @@ -33,7 +45,8 @@ static rt_err_t uart_input(rt_device_t dev, rt_size_t size) } static void serial_thread_entry(void *parameter) -{ +{ +#if (UART_SAMPLE_TYPE == 1) char ch; while (1) @@ -48,6 +61,42 @@ static void serial_thread_entry(void *parameter) ch = ch + 1; rt_device_write(serial, 0, &ch, 1); } +#endif + +#if (UART_SAMPLE_TYPE == 2) + char rx_buf[SAMPLE_UART_RXBUF_SIZE],*end = SAMPLE_UART_END_SRTING; /*rx_buf[]:接收缓存，可修改大小 end[]:固定的结束格式（可修改，不可包含'\0'）*/ + uint32_t rx_index = 0; /*接收数据的索引 */ + uint32_t end_len = rt_strlen(end); /*固定的结束格式的长度*/ + + while(1) + { + + /* 从串口读取一个字节的数据，没有读取到则等待接收信号量 */ + while (rt_device_read(serial, -1, (rx_buf + rx_index), 1) != 1) + { + /* 阻塞等待接收信号量，等到信号量后再次读取数据 */ + rt_sem_take(&rx_sem, RT_WAITING_FOREVER); + } + + rx_index++; + if(rx_index >= SAMPLE_UART_RXBUF_SIZE) + { + rt_kprintf("rx_buf over!\r\n"); /*范围越界*/ + } + + /*判断是否固定的结尾格式*/ + if((rx_index >= end_len)&&\ + ((rt_strncmp(end,(rx_buf + rx_index - end_len),end_len)) == 0)) + { + rt_device_write(serial, 0, rx_buf, rx_index); + rx_index = 0; + } + + } + + +#endif + } static int uart_sample(int argc, char *argv[]) diff --git a/bsp/essemi/es32f0654/drivers/drv_can.c b/bsp/essemi/es32f0654/drivers/drv_can.c index 7c73acd0cf..cf2d9d66d1 100644 --- a/bsp/essemi/es32f0654/drivers/drv_can.c +++ b/bsp/essemi/es32f0654/drivers/drv_can.c @@ -418,14 +418,14 @@ static int _can_sendmsg(struct rt_can_device *can, const void *buf, rt_uint32_t } /* clear TIR */ h_can->perh->TxMailBox[box_num].TXID &= CAN_TXID0_TXMREQ_MSK; - /* Set up the Id */ + /* Set up the Id */ if (RT_CAN_STDID == pmsg->ide) - { - h_can->perh->TxMailBox[box_num].TXID |= (txheader.std << CAN_TXID0_STDID_POSS) | txheader.rtr; + { + h_can->perh->TxMailBox[box_num].TXID |= (txheader.std << CAN_TXID0_STDID_POSS) | (txheader.rtr << CAN_TXID0_RTR_POS); } else { - h_can->perh->TxMailBox[box_num].TXID |= (txheader.ext << CAN_TXID0_EXID_POSS) | txheader.type | txheader.rtr; + h_can->perh->TxMailBox[box_num].TXID |= (txheader.ext << CAN_TXID0_EXID_POSS) | (txheader.type << CAN_TXID0_IDE_POS) | (txheader.rtr << CAN_TXID0_RTR_POS); } /* Set up the DLC */ h_can->perh->TxMailBox[box_num].TXFCON = pmsg->len & 0x0FU; diff --git a/bsp/essemi/es32f0654/drivers/drv_gpio.c b/bsp/essemi/es32f0654/drivers/drv_gpio.c index 00050866e5..994b26ad94 100644 --- a/bsp/essemi/es32f0654/drivers/drv_gpio.c +++ b/bsp/essemi/es32f0654/drivers/drv_gpio.c @@ -314,12 +314,18 @@ void es32f0_pin_mode(rt_device_t dev, rt_base_t pin, rt_base_t mode) rt_inline const struct pin_irq_map *get_pin_irq_map(rt_uint16_t gpio_pin) { - rt_int32_t mapindex = gpio_pin & 0x00FF; - if (mapindex < 0 || mapindex >= ITEM_NUM(pin_irq_map)) + uint8_t map_index = 0U; + + while(gpio_pin >> (++map_index)) + { + } + map_index--; + + if (map_index >= ITEM_NUM(pin_irq_map)) { return RT_NULL; } - return &pin_irq_map[mapindex]; + return &pin_irq_map[map_index]; }; rt_err_t es32f0_pin_attach_irq(struct rt_device *device, rt_int32_t pin, diff --git a/bsp/essemi/es32f0654/drivers/drv_gpio.h b/bsp/essemi/es32f0654/drivers/drv_gpio.h index b0b68714d3..21f564f937 100644 --- a/bsp/essemi/es32f0654/drivers/drv_gpio.h +++ b/bsp/essemi/es32f0654/drivers/drv_gpio.h @@ -26,6 +26,8 @@ #include "es_conf_info_gpio.h" +#define GET_PIN(port,pin) (ES_PIN_GPIO_##port##_##pin) + int rt_hw_pin_init(void); #endif diff --git a/bsp/essemi/es32f0654/drivers/drv_i2c.c b/bsp/essemi/es32f0654/drivers/drv_i2c.c index 1109b7f641..911f316687 100644 --- a/bsp/essemi/es32f0654/drivers/drv_i2c.c +++ b/bsp/essemi/es32f0654/drivers/drv_i2c.c @@ -81,9 +81,9 @@ static void _i2c_init(void) #ifdef BSP_USING_I2C1 -#if defined(ES_I2C1_SDA_GPIO_FUNC)&&defined(ES_I2C1_SDA_GPIO_PORT)&&defined(ES_I2C1_SDA_GPIO_PIN) - gpio_instruct.func = ES_I2C1_SDA_GPIO_FUNC; - ald_gpio_init(ES_I2C1_SDA_GPIO_PORT, ES_I2C1_SDA_GPIO_PIN, &gpio_instruct); +#if defined(ES_I2C1_SCL_GPIO_FUNC)&&defined(ES_I2C1_SCL_GPIO_PORT)&&defined(ES_I2C1_SCL_GPIO_PIN) + gpio_instruct.func = ES_I2C1_SCL_GPIO_FUNC; + ald_gpio_init(ES_I2C1_SCL_GPIO_PORT, ES_I2C1_SCL_GPIO_PIN, &gpio_instruct); #endif #if defined(ES_I2C1_SDA_GPIO_FUNC)&&defined(ES_I2C1_SDA_GPIO_PORT)&&defined(ES_I2C1_SDA_GPIO_PIN) diff --git a/bsp/essemi/es32f369x/drivers/board.c b/bsp/essemi/es32f369x/drivers/board.c index ea42df63dc..ae52cbf5dc 100644 --- a/bsp/essemi/es32f369x/drivers/board.c +++ b/bsp/essemi/es32f369x/drivers/board.c @@ -129,6 +129,8 @@ void SysTick_Configuration(void) { /* ticks = sysclk / RT_TICK_PER_SECOND */ SysTick_Config(ald_cmu_get_sys_clock() / RT_TICK_PER_SECOND); + + __systick_interval = 1; } /** diff --git a/bsp/essemi/es32f369x/drivers/bsp_driver_example/i2c_sample.c b/bsp/essemi/es32f369x/drivers/bsp_driver_example/i2c_sample.c index c8a666609d..92a96b2e85 100644 --- a/bsp/essemi/es32f369x/drivers/bsp_driver_example/i2c_sample.c +++ b/bsp/essemi/es32f369x/drivers/bsp_driver_example/i2c_sample.c @@ -64,8 +64,6 @@ static void i2c_io_sample(int argc, char *argv[]) temp_msg.flags = RT_I2C_RD; /* I2C读 */ s_stat = rt_i2c_transfer(i2c_bus,&temp_msg,num_msg); /* 传输消息 */ - rt_thread_mdelay(400); - if( s_stat == num_msg ) { rt_kprintf("receive successful. \n receive messege : %s \n:",buffer); @@ -87,8 +85,6 @@ static void i2c_io_sample(int argc, char *argv[]) temp_msg.flags = RT_I2C_WR; /* I2C写 */ s_stat = rt_i2c_transfer(i2c_bus,&temp_msg,num_msg); /* 传输一条 */ - rt_thread_mdelay(400); - if( s_stat == num_msg ) { rt_kprintf(" send successful \n messege : %s \n:",buffer); diff --git a/bsp/essemi/es32f369x/drivers/bsp_driver_example/led_blink_sample.c b/bsp/essemi/es32f369x/drivers/bsp_driver_example/led_blink_sample.c index f1c9901ad0..6d75105695 100644 --- a/bsp/essemi/es32f369x/drivers/bsp_driver_example/led_blink_sample.c +++ b/bsp/essemi/es32f369x/drivers/bsp_driver_example/led_blink_sample.c @@ -18,10 +18,11 @@ #include #include -#include +#include +#include "drv_gpio.h" /* PIN脚编号，查看驱动文件drv_gpio.c确定 */ -#define LED_PIN_NUM 19 /*PF1*/ +#define LED_PIN_NUM GET_PIN( F , 1 ) static int pin_num; static void led_entry(void *parameter) diff --git a/bsp/essemi/es32f369x/drivers/bsp_driver_example/pin_beep_sample.c b/bsp/essemi/es32f369x/drivers/bsp_driver_example/pin_beep_sample.c index 58a7bf1891..9cf9ef81e8 100644 --- a/bsp/essemi/es32f369x/drivers/bsp_driver_example/pin_beep_sample.c +++ b/bsp/essemi/es32f369x/drivers/bsp_driver_example/pin_beep_sample.c @@ -15,17 +15,18 @@ */ #include -#include +#include +#include "drv_gpio.h" /* 引脚编号，通过查看驱动文件drv_gpio.c确定 */ #ifndef BEEP_PIN_NUM - #define BEEP_PIN_NUM 19 /* PF1 */ + #define BEEP_PIN_NUM GET_PIN( F , 1 ) #endif #ifndef KEY0_PIN_NUM - #define KEY0_PIN_NUM 52 /* PC11 */ + #define KEY0_PIN_NUM GET_PIN( C , 11 ) #endif #ifndef KEY1_PIN_NUM - #define KEY1_PIN_NUM 53 /* PC12 */ + #define KEY1_PIN_NUM GET_PIN( C , 12 ) #endif void beep_on(void *args) diff --git a/bsp/essemi/es32f369x/drivers/bsp_driver_example/pm_sample.c b/bsp/essemi/es32f369x/drivers/bsp_driver_example/pm_sample.c index 731dca4115..fb4b78d731 100644 --- a/bsp/essemi/es32f369x/drivers/bsp_driver_example/pm_sample.c +++ b/bsp/essemi/es32f369x/drivers/bsp_driver_example/pm_sample.c @@ -30,15 +30,14 @@ #include #include -#include "drv_pm.h" -#include "ald_gpio.h" - +#include "drv_pm.h" +#include "drv_gpio.h" #ifdef RT_USING_PM -#define PM_NAME "pm" /* 设备名称 */ -#define WAKE_UP_PIN 51 /* 唤醒源 */ -#define SLEEP_TIMES 12 /* 进入睡眠次数，轮流进入不同的睡眠模式，包括无睡眠模式 */ +#define PM_NAME "pm" /* 设备名称 */ +#define WAKE_UP_PIN GET_PIN( C , 10 ) /* 唤醒源 */ +#define SLEEP_TIMES 12 /* 进入睡眠次数，轮流进入不同的睡眠模式，包括无睡眠模式 */ /*部分芯片进入深度睡眠后，部分外设的部分寄存器可能会丢失*/ #define SAVE_REG UART0 diff --git a/bsp/essemi/es32f369x/drivers/bsp_driver_example/pwm_led_sample.c b/bsp/essemi/es32f369x/drivers/bsp_driver_example/pwm_led_sample.c index 8d12b74e15..51cedd49eb 100644 --- a/bsp/essemi/es32f369x/drivers/bsp_driver_example/pwm_led_sample.c +++ b/bsp/essemi/es32f369x/drivers/bsp_driver_example/pwm_led_sample.c @@ -16,13 +16,13 @@ #include #include - +#include "drv_gpio.h" #ifdef RT_USING_PWM -#define LED_PIN_NUM 37 /* PF1 LED PIN脚编号，查看驱动文件drv_gpio.c确定 */ -#define PWM_DEV_NAME "pwm1" /* PWM设备名称 */ -#define PWM_DEV_CHANNEL 1 /* PWM通道 */ +#define LED_PIN_NUM GET_PIN( C , 6 ) /* LED PIN脚编号，查看驱动文件drv_gpio.c确定 */ +#define PWM_DEV_NAME "pwm1" /* PWM设备名称 */ +#define PWM_DEV_CHANNEL 1 /* PWM通道 */ struct rt_device_pwm *pwm_dev; /* PWM设备句柄 */ diff --git a/bsp/essemi/es32f369x/drivers/bsp_driver_example/uart_sample.c b/bsp/essemi/es32f369x/drivers/bsp_driver_example/uart_sample.c index e059df32bb..2094a6576e 100644 --- a/bsp/essemi/es32f369x/drivers/bsp_driver_example/uart_sample.c +++ b/bsp/essemi/es32f369x/drivers/bsp_driver_example/uart_sample.c @@ -12,16 +12,28 @@ * 例程导出了 uart_sample 命令到控制终端 * 命令调用格式：uart_sample uart2 * 命令解释：命令第二个参数是要使用的串口设备名称，为空则使用默认的串口设备 - * 程序功能：通过串口输出字符串"hello RT-Thread!"，然后错位输出输入的字符 + * 程序功能：通过串口输出字符串"hello RT-Thread!"，然后根据例子类型，处理输入数据，然后输出 */ #include -#define SAMPLE_UART_NAME "uart0" /* 串口设备名称 */ +/* UART_SAMPLE_TYPE = 1,错位输出 + = 2 接收到固定格式之后输出 +*/ +#define UART_SAMPLE_TYPE 1 + +#if (UART_SAMPLE_TYPE == 2) + +#define SAMPLE_UART_RXBUF_SIZE 256 /* 接收缓存大小 */ +#define SAMPLE_UART_END_SRTING "\r\n" /* 结尾固定格式 */ + +#endif + +#define SAMPLE_UART_NAME "uart1" /* 串口设备名称 */ /* 用于接收消息的信号量 */ static struct rt_semaphore rx_sem; -static rt_device_t serial; +static rt_device_t serial; /* 接收数据回调函数 */ static rt_err_t uart_input(rt_device_t dev, rt_size_t size) @@ -33,7 +45,8 @@ static rt_err_t uart_input(rt_device_t dev, rt_size_t size) } static void serial_thread_entry(void *parameter) -{ +{ +#if (UART_SAMPLE_TYPE == 1) char ch; while (1) @@ -48,6 +61,42 @@ static void serial_thread_entry(void *parameter) ch = ch + 1; rt_device_write(serial, 0, &ch, 1); } +#endif + +#if (UART_SAMPLE_TYPE == 2) + char rx_buf[SAMPLE_UART_RXBUF_SIZE],*end = SAMPLE_UART_END_SRTING; /*rx_buf[]:接收缓存，可修改大小 end[]:固定的结束格式（可修改，不可包含'\0'）*/ + uint32_t rx_index = 0; /*接收数据的索引 */ + uint32_t end_len = rt_strlen(end); /*固定的结束格式的长度*/ + + while(1) + { + + /* 从串口读取一个字节的数据，没有读取到则等待接收信号量 */ + while (rt_device_read(serial, -1, (rx_buf + rx_index), 1) != 1) + { + /* 阻塞等待接收信号量，等到信号量后再次读取数据 */ + rt_sem_take(&rx_sem, RT_WAITING_FOREVER); + } + + rx_index++; + if(rx_index >= SAMPLE_UART_RXBUF_SIZE) + { + rt_kprintf("rx_buf over!\r\n"); /*范围越界*/ + } + + /*判断是否固定的结尾格式*/ + if((rx_index >= end_len)&&\ + ((rt_strncmp(end,(rx_buf + rx_index - end_len),end_len)) == 0)) + { + rt_device_write(serial, 0, rx_buf, rx_index); + rx_index = 0; + } + + } + + +#endif + } static int uart_sample(int argc, char *argv[]) diff --git a/bsp/essemi/es32f369x/drivers/drv_adc.c b/bsp/essemi/es32f369x/drivers/drv_adc.c index 716fddcfa4..91bf56ef38 100644 --- a/bsp/essemi/es32f369x/drivers/drv_adc.c +++ b/bsp/essemi/es32f369x/drivers/drv_adc.c @@ -68,8 +68,8 @@ static adc_channel_t es32f3_adc_get_channel(rt_uint32_t channel) gpio_initstruct.mode = GPIO_MODE_INPUT; gpio_initstruct.pupd = GPIO_FLOATING; gpio_initstruct.odos = GPIO_OPEN_DRAIN; - gpio_initstruct.podrv = GPIO_OUT_DRIVE_1; - gpio_initstruct.nodrv = GPIO_OUT_DRIVE_1; + gpio_initstruct.podrv = GPIO_OUT_DRIVE_6; + gpio_initstruct.nodrv = GPIO_OUT_DRIVE_6; gpio_initstruct.flt = GPIO_FILTER_DISABLE; gpio_initstruct.type = GPIO_TYPE_CMOS; gpio_initstruct.func = GPIO_FUNC_0; diff --git a/bsp/essemi/es32f369x/drivers/drv_can.c b/bsp/essemi/es32f369x/drivers/drv_can.c index 6e7456b9b6..48c462c5f1 100644 --- a/bsp/essemi/es32f369x/drivers/drv_can.c +++ b/bsp/essemi/es32f369x/drivers/drv_can.c @@ -413,14 +413,14 @@ static int _can_sendmsg(struct rt_can_device *can, const void *buf, rt_uint32_t /* clear TIR */ h_can->perh->TxMailBox[box_num].TXID &= CAN_TXID0_TXMREQ_MSK; - /* Set up the Id */ + /* Set up the Id */ if (RT_CAN_STDID == pmsg->ide) - { - h_can->perh->TxMailBox[box_num].TXID |= (txheader.std << CAN_TXID0_STDID_POSS) | txheader.rtr; + { + h_can->perh->TxMailBox[box_num].TXID |= (txheader.std << CAN_TXID0_STDID_POSS) | (txheader.rtr << CAN_TXID0_RTR_POS); } else { - h_can->perh->TxMailBox[box_num].TXID |= (txheader.ext << CAN_TXID0_EXID_POSS) | txheader.type | txheader.rtr; + h_can->perh->TxMailBox[box_num].TXID |= (txheader.ext << CAN_TXID0_EXID_POSS) | (txheader.type << CAN_TXID0_IDE_POS) | (txheader.rtr << CAN_TXID0_RTR_POS); } /* Set up the DLC */ h_can->perh->TxMailBox[box_num].TXFCON = pmsg->len & 0x0FU; diff --git a/bsp/essemi/es32f369x/drivers/drv_gpio.c b/bsp/essemi/es32f369x/drivers/drv_gpio.c index 8ce6ab7aa8..24621e117a 100644 --- a/bsp/essemi/es32f369x/drivers/drv_gpio.c +++ b/bsp/essemi/es32f369x/drivers/drv_gpio.c @@ -274,8 +274,8 @@ void es32f3_pin_mode(rt_device_t dev, rt_base_t pin, rt_base_t mode) /* Configure GPIO_InitStructure */ gpio_initstruct.mode = GPIO_MODE_OUTPUT; gpio_initstruct.func = GPIO_FUNC_1; - gpio_initstruct.podrv = GPIO_OUT_DRIVE_1; - gpio_initstruct.nodrv = GPIO_OUT_DRIVE_0_1; + gpio_initstruct.podrv = GPIO_OUT_DRIVE_6; + gpio_initstruct.nodrv = GPIO_OUT_DRIVE_6; gpio_initstruct.type = GPIO_TYPE_CMOS; gpio_initstruct.odos = GPIO_PUSH_PULL; gpio_initstruct.flt = GPIO_FILTER_DISABLE; @@ -316,12 +316,18 @@ void es32f3_pin_mode(rt_device_t dev, rt_base_t pin, rt_base_t mode) rt_inline const struct pin_irq_map *get_pin_irq_map(rt_uint16_t gpio_pin) { - rt_int32_t mapindex = gpio_pin & 0x00FF; - if (mapindex < 0 || mapindex >= ITEM_NUM(pin_irq_map)) + uint8_t map_index = 0U; + + while(gpio_pin >> (++map_index)) + { + } + map_index--; + + if (map_index >= ITEM_NUM(pin_irq_map)) { return RT_NULL; } - return &pin_irq_map[mapindex]; + return &pin_irq_map[map_index]; }; rt_err_t es32f3_pin_attach_irq(struct rt_device *device, rt_int32_t pin, @@ -442,8 +448,8 @@ rt_err_t es32f3_pin_irq_enable(struct rt_device *device, rt_base_t pin, /* Configure GPIO_InitStructure */ gpio_initstruct.mode = GPIO_MODE_INPUT; gpio_initstruct.odos = GPIO_PUSH_PULL; - gpio_initstruct.podrv = GPIO_OUT_DRIVE_1; - gpio_initstruct.nodrv = GPIO_OUT_DRIVE_1; + gpio_initstruct.podrv = GPIO_OUT_DRIVE_6; + gpio_initstruct.nodrv = GPIO_OUT_DRIVE_6; gpio_initstruct.func = GPIO_FUNC_1; gpio_initstruct.flt = GPIO_FILTER_DISABLE; switch (pin_irq_hdr_tab[irqindex].mode) diff --git a/bsp/essemi/es32f369x/drivers/drv_gpio.h b/bsp/essemi/es32f369x/drivers/drv_gpio.h index 8489e625d5..efb5f27f7e 100644 --- a/bsp/essemi/es32f369x/drivers/drv_gpio.h +++ b/bsp/essemi/es32f369x/drivers/drv_gpio.h @@ -25,6 +25,8 @@ #define DRV_GPIO_H__ #include "es_conf_info_gpio.h" + +#define GET_PIN(port,pin) (ES_PIN_GPIO_##port##_##pin) int rt_hw_pin_init(void); diff --git a/bsp/essemi/es32f369x/drivers/drv_i2c.c b/bsp/essemi/es32f369x/drivers/drv_i2c.c index c398d5ab45..01d4404606 100644 --- a/bsp/essemi/es32f369x/drivers/drv_i2c.c +++ b/bsp/essemi/es32f369x/drivers/drv_i2c.c @@ -49,8 +49,8 @@ static void _i2c_init(void) gpio_instruct.mode = GPIO_MODE_OUTPUT; gpio_instruct.odos = GPIO_OPEN_DRAIN; gpio_instruct.pupd = GPIO_PUSH_UP; - gpio_instruct.podrv = GPIO_OUT_DRIVE_1; - gpio_instruct.nodrv = GPIO_OUT_DRIVE_0_1; + gpio_instruct.podrv = GPIO_OUT_DRIVE_6; + gpio_instruct.nodrv = GPIO_OUT_DRIVE_6; gpio_instruct.flt = GPIO_FILTER_DISABLE; gpio_instruct.type = GPIO_TYPE_CMOS; @@ -83,9 +83,9 @@ static void _i2c_init(void) #ifdef BSP_USING_I2C1 -#if defined(ES_I2C1_SDA_GPIO_FUNC)&&defined(ES_I2C1_SDA_GPIO_PORT)&&defined(ES_I2C1_SDA_GPIO_PIN) - gpio_instruct.func = ES_I2C1_SDA_GPIO_FUNC; - ald_gpio_init(ES_I2C1_SDA_GPIO_PORT, ES_I2C1_SDA_GPIO_PIN, &gpio_instruct); +#if defined(ES_I2C1_SCL_GPIO_FUNC)&&defined(ES_I2C1_SCL_GPIO_PORT)&&defined(ES_I2C1_SCL_GPIO_PIN) + gpio_instruct.func = ES_I2C1_SCL_GPIO_FUNC; + ald_gpio_init(ES_I2C1_SCL_GPIO_PORT, ES_I2C1_SCL_GPIO_PIN, &gpio_instruct); #endif #if defined(ES_I2C1_SDA_GPIO_FUNC)&&defined(ES_I2C1_SDA_GPIO_PORT)&&defined(ES_I2C1_SDA_GPIO_PIN) diff --git a/bsp/essemi/es32f369x/drivers/drv_spi.c b/bsp/essemi/es32f369x/drivers/drv_spi.c index aae178f78e..f777645a56 100644 --- a/bsp/essemi/es32f369x/drivers/drv_spi.c +++ b/bsp/essemi/es32f369x/drivers/drv_spi.c @@ -283,8 +283,8 @@ int rt_hw_spi_init(void) gpio_instruct.pupd = GPIO_PUSH_UP_DOWN; gpio_instruct.odos = GPIO_PUSH_PULL; - gpio_instruct.podrv = GPIO_OUT_DRIVE_1; - gpio_instruct.nodrv = GPIO_OUT_DRIVE_1; + gpio_instruct.podrv = GPIO_OUT_DRIVE_6; + gpio_instruct.nodrv = GPIO_OUT_DRIVE_6; gpio_instruct.type = GPIO_TYPE_TTL; gpio_instruct.flt = GPIO_FILTER_DISABLE; diff --git a/bsp/essemi/es32f369x/drivers/drv_uart.c b/bsp/essemi/es32f369x/drivers/drv_uart.c index 5ca5085c54..f964f6f82d 100644 --- a/bsp/essemi/es32f369x/drivers/drv_uart.c +++ b/bsp/essemi/es32f369x/drivers/drv_uart.c @@ -198,8 +198,8 @@ static rt_err_t es32f3x_configure(struct rt_serial_device *serial, struct serial gpio_initstructure.mode = GPIO_MODE_OUTPUT; gpio_initstructure.odos = GPIO_PUSH_PULL; gpio_initstructure.pupd = GPIO_PUSH_UP; - gpio_initstructure.podrv = GPIO_OUT_DRIVE_1; - gpio_initstructure.nodrv = GPIO_OUT_DRIVE_1; + gpio_initstructure.podrv = GPIO_OUT_DRIVE_6; + gpio_initstructure.nodrv = GPIO_OUT_DRIVE_6; gpio_initstructure.flt = GPIO_FILTER_DISABLE; gpio_initstructure.type = GPIO_TYPE_TTL; -- cgit v1.3.1 From 870f82190a0c01c4bc1c8f256b355c465e4c99bb Mon Sep 17 00:00:00 2001 From: liuhy Date: Fri, 10 Sep 2021 18:15:33 +0800 Subject: update applications/main.c --- bsp/essemi/es32f0654/applications/main.c | 3 ++- bsp/essemi/es32f369x/applications/main.c | 5 +++-- 2 files changed, 5 insertions(+), 3 deletions(-) (limited to 'bsp') diff --git a/bsp/essemi/es32f0654/applications/main.c b/bsp/essemi/es32f0654/applications/main.c index fd331eb8d9..10d69b22b0 100644 --- a/bsp/essemi/es32f0654/applications/main.c +++ b/bsp/essemi/es32f0654/applications/main.c @@ -10,8 +10,9 @@ #include #include +#include "drv_gpio.h" -#define LED_PIN 39 +#define LED_PIN GET_PIN( C , 8 ) int main(void) { diff --git a/bsp/essemi/es32f369x/applications/main.c b/bsp/essemi/es32f369x/applications/main.c index c8068e94d6..ed064d6f0a 100644 --- a/bsp/essemi/es32f369x/applications/main.c +++ b/bsp/essemi/es32f369x/applications/main.c @@ -10,13 +10,14 @@ #include #include +#include "drv_gpio.h" -#define LED_PIN 18 +#define LED_PIN GET_PIN( F , 0 ) int main(void) { int count = 1; - /* set PF00 pin mode to output */ + /* set pin mode to output */ rt_pin_mode(LED_PIN, PIN_MODE_OUTPUT); while (count++) -- cgit v1.3.1 From 05bf7e61f69512b1ab4c1010a471bb4277ce77b5 Mon Sep 17 00:00:00 2001 From: WUSY1991 <1191297340@qq.com> Date: Fri, 10 Sep 2021 19:41:22 +0800 Subject: add yichip/yc3121-pos bsp --- bsp/yichip/yc3121-pos/.config | 582 + bsp/yichip/yc3121-pos/.gitignore | 44 + bsp/yichip/yc3121-pos/.ignore_format.yml | 25 + bsp/yichip/yc3121-pos/Kconfig | 27 + bsp/yichip/yc3121-pos/Libraries/SConscript | 17 + .../yc3121-pos/Libraries/core/board_config.h | 275 + bsp/yichip/yc3121-pos/Libraries/core/misc.c | 102 + bsp/yichip/yc3121-pos/Libraries/core/misc.h | 93 + bsp/yichip/yc3121-pos/Libraries/core/rom_api.h | 42 + bsp/yichip/yc3121-pos/Libraries/core/system.c | 254 + bsp/yichip/yc3121-pos/Libraries/core/system.h | 43 + bsp/yichip/yc3121-pos/Libraries/core/type.h | 67 + bsp/yichip/yc3121-pos/Libraries/core/yc3121.h | 666 + bsp/yichip/yc3121-pos/Libraries/sdk/yc_dma.c | 72 + bsp/yichip/yc3121-pos/Libraries/sdk/yc_dma.h | 91 + bsp/yichip/yc3121-pos/Libraries/sdk/yc_gpio.c | 211 + bsp/yichip/yc3121-pos/Libraries/sdk/yc_gpio.h | 299 + bsp/yichip/yc3121-pos/Libraries/sdk/yc_systick.c | 72 + bsp/yichip/yc3121-pos/Libraries/sdk/yc_systick.h | 64 + bsp/yichip/yc3121-pos/Libraries/sdk/yc_uart.c | 429 + bsp/yichip/yc3121-pos/Libraries/sdk/yc_uart.h | 304 + bsp/yichip/yc3121-pos/Libraries/sdk/yc_wdt.c | 54 + bsp/yichip/yc3121-pos/Libraries/sdk/yc_wdt.h | 74 + .../yc3121-pos/Libraries/startup/flash_start.s | 396 + .../yc3121-pos/Libraries/startup/flash_start_gcc.s | 318 + .../yc3121-pos/Libraries/startup/flash_start_iar.s | 311 + bsp/yichip/yc3121-pos/Libraries/startup/startup.s | 175 + bsp/yichip/yc3121-pos/README.md | 36 + bsp/yichip/yc3121-pos/SConscript | 11 + bsp/yichip/yc3121-pos/SConstruct | 40 + bsp/yichip/yc3121-pos/applications/SConscript | 9 + bsp/yichip/yc3121-pos/applications/main.c | 31 + bsp/yichip/yc3121-pos/drivers/Kconfig | 22 + bsp/yichip/yc3121-pos/drivers/SConscript | 25 + bsp/yichip/yc3121-pos/drivers/board.c | 57 + bsp/yichip/yc3121-pos/drivers/board.h | 44 + bsp/yichip/yc3121-pos/drivers/drv_gpio.c | 199 + bsp/yichip/yc3121-pos/drivers/drv_gpio.h | 16 + bsp/yichip/yc3121-pos/drivers/drv_uart.c | 194 + bsp/yichip/yc3121-pos/drivers/drv_uart.h | 16 + .../yc3121-pos/drivers/linker_scripts/link.icf | 32 + .../yc3121-pos/drivers/linker_scripts/link.lds | 161 + .../yc3121-pos/drivers/linker_scripts/link.sct | 32 + bsp/yichip/yc3121-pos/figures/YC3121-pos.jpg | Bin 0 -> 245850 bytes bsp/yichip/yc3121-pos/project.ewd | 2834 ++++ bsp/yichip/yc3121-pos/project.ewp | 2223 +++ bsp/yichip/yc3121-pos/project.eww | 10 + bsp/yichip/yc3121-pos/project.uvoptx | 793 + bsp/yichip/yc3121-pos/project.uvprojx | 661 + bsp/yichip/yc3121-pos/rtconfig.h | 178 + bsp/yichip/yc3121-pos/rtconfig.py | 152 + bsp/yichip/yc3121-pos/rtthread_asm.txt | 14979 +++++++++++++++++++ bsp/yichip/yc3121-pos/template.ewp | 2032 +++ bsp/yichip/yc3121-pos/template.eww | 10 + bsp/yichip/yc3121-pos/template.uvopt | 184 + bsp/yichip/yc3121-pos/template.uvoptx | 177 + bsp/yichip/yc3121-pos/template.uvprojx | 389 + 57 files changed, 30654 insertions(+) create mode 100644 bsp/yichip/yc3121-pos/.config create mode 100644 bsp/yichip/yc3121-pos/.gitignore create mode 100644 bsp/yichip/yc3121-pos/.ignore_format.yml create mode 100644 bsp/yichip/yc3121-pos/Kconfig create mode 100644 bsp/yichip/yc3121-pos/Libraries/SConscript create mode 100644 bsp/yichip/yc3121-pos/Libraries/core/board_config.h create mode 100644 bsp/yichip/yc3121-pos/Libraries/core/misc.c create mode 100644 bsp/yichip/yc3121-pos/Libraries/core/misc.h create mode 100644 bsp/yichip/yc3121-pos/Libraries/core/rom_api.h create mode 100644 bsp/yichip/yc3121-pos/Libraries/core/system.c create mode 100644 bsp/yichip/yc3121-pos/Libraries/core/system.h create mode 100644 bsp/yichip/yc3121-pos/Libraries/core/type.h create mode 100644 bsp/yichip/yc3121-pos/Libraries/core/yc3121.h create mode 100644 bsp/yichip/yc3121-pos/Libraries/sdk/yc_dma.c create mode 100644 bsp/yichip/yc3121-pos/Libraries/sdk/yc_dma.h create mode 100644 bsp/yichip/yc3121-pos/Libraries/sdk/yc_gpio.c create mode 100644 bsp/yichip/yc3121-pos/Libraries/sdk/yc_gpio.h create mode 100644 bsp/yichip/yc3121-pos/Libraries/sdk/yc_systick.c create mode 100644 bsp/yichip/yc3121-pos/Libraries/sdk/yc_systick.h create mode 100644 bsp/yichip/yc3121-pos/Libraries/sdk/yc_uart.c create mode 100644 bsp/yichip/yc3121-pos/Libraries/sdk/yc_uart.h create mode 100644 bsp/yichip/yc3121-pos/Libraries/sdk/yc_wdt.c create mode 100644 bsp/yichip/yc3121-pos/Libraries/sdk/yc_wdt.h create mode 100644 bsp/yichip/yc3121-pos/Libraries/startup/flash_start.s create mode 100644 bsp/yichip/yc3121-pos/Libraries/startup/flash_start_gcc.s create mode 100644 bsp/yichip/yc3121-pos/Libraries/startup/flash_start_iar.s create mode 100644 bsp/yichip/yc3121-pos/Libraries/startup/startup.s create mode 100644 bsp/yichip/yc3121-pos/README.md create mode 100644 bsp/yichip/yc3121-pos/SConscript create mode 100644 bsp/yichip/yc3121-pos/SConstruct create mode 100644 bsp/yichip/yc3121-pos/applications/SConscript create mode 100644 bsp/yichip/yc3121-pos/applications/main.c create mode 100644 bsp/yichip/yc3121-pos/drivers/Kconfig create mode 100644 bsp/yichip/yc3121-pos/drivers/SConscript create mode 100644 bsp/yichip/yc3121-pos/drivers/board.c create mode 100644 bsp/yichip/yc3121-pos/drivers/board.h create mode 100644 bsp/yichip/yc3121-pos/drivers/drv_gpio.c create mode 100644 bsp/yichip/yc3121-pos/drivers/drv_gpio.h create mode 100644 bsp/yichip/yc3121-pos/drivers/drv_uart.c create mode 100644 bsp/yichip/yc3121-pos/drivers/drv_uart.h create mode 100644 bsp/yichip/yc3121-pos/drivers/linker_scripts/link.icf create mode 100644 bsp/yichip/yc3121-pos/drivers/linker_scripts/link.lds create mode 100644 bsp/yichip/yc3121-pos/drivers/linker_scripts/link.sct create mode 100644 bsp/yichip/yc3121-pos/figures/YC3121-pos.jpg create mode 100644 bsp/yichip/yc3121-pos/project.ewd create mode 100644 bsp/yichip/yc3121-pos/project.ewp create mode 100644 bsp/yichip/yc3121-pos/project.eww create mode 100644 bsp/yichip/yc3121-pos/project.uvoptx create mode 100644 bsp/yichip/yc3121-pos/project.uvprojx create mode 100644 bsp/yichip/yc3121-pos/rtconfig.h create mode 100644 bsp/yichip/yc3121-pos/rtconfig.py create mode 100644 bsp/yichip/yc3121-pos/rtthread_asm.txt create mode 100644 bsp/yichip/yc3121-pos/template.ewp create mode 100644 bsp/yichip/yc3121-pos/template.eww create mode 100644 bsp/yichip/yc3121-pos/template.uvopt create mode 100644 bsp/yichip/yc3121-pos/template.uvoptx create mode 100644 bsp/yichip/yc3121-pos/template.uvprojx (limited to 'bsp') diff --git a/bsp/yichip/yc3121-pos/.config b/bsp/yichip/yc3121-pos/.config new file mode 100644 index 0000000000..eca18829fa --- /dev/null +++ b/bsp/yichip/yc3121-pos/.config @@ -0,0 +1,582 @@ +# +# Automatically generated file; DO NOT EDIT. +# RT-Thread Configuration +# + +# +# RT-Thread Kernel +# +CONFIG_RT_NAME_MAX=8 +# CONFIG_RT_USING_ARCH_DATA_TYPE is not set +# CONFIG_RT_USING_SMP is not set +CONFIG_RT_ALIGN_SIZE=4 +# CONFIG_RT_THREAD_PRIORITY_8 is not set +CONFIG_RT_THREAD_PRIORITY_32=y +# CONFIG_RT_THREAD_PRIORITY_256 is not set +CONFIG_RT_THREAD_PRIORITY_MAX=32 +CONFIG_RT_TICK_PER_SECOND=100 +CONFIG_RT_USING_OVERFLOW_CHECK=y +CONFIG_RT_USING_HOOK=y +CONFIG_RT_USING_IDLE_HOOK=y +CONFIG_RT_IDLE_HOOK_LIST_SIZE=4 +CONFIG_IDLE_THREAD_STACK_SIZE=256 +# CONFIG_RT_USING_TIMER_SOFT is not set + +# +# kservice optimization +# +# CONFIG_RT_KSERVICE_USING_STDLIB is not set +# CONFIG_RT_KSERVICE_USING_TINY_SIZE is not set +# CONFIG_RT_USING_ASM_MEMCPY is not set +CONFIG_RT_DEBUG=y +CONFIG_RT_DEBUG_COLOR=y +# CONFIG_RT_DEBUG_INIT_CONFIG is not set +# CONFIG_RT_DEBUG_THREAD_CONFIG is not set +# CONFIG_RT_DEBUG_SCHEDULER_CONFIG is not set +# CONFIG_RT_DEBUG_IPC_CONFIG is not set +# CONFIG_RT_DEBUG_TIMER_CONFIG is not set +# CONFIG_RT_DEBUG_IRQ_CONFIG is not set +# CONFIG_RT_DEBUG_MEM_CONFIG is not set +# CONFIG_RT_DEBUG_SLAB_CONFIG is not set +# CONFIG_RT_DEBUG_MEMHEAP_CONFIG is not set +# CONFIG_RT_DEBUG_MODULE_CONFIG is not set + +# +# Inter-Thread communication +# +CONFIG_RT_USING_SEMAPHORE=y +CONFIG_RT_USING_MUTEX=y +CONFIG_RT_USING_EVENT=y +CONFIG_RT_USING_MAILBOX=y +CONFIG_RT_USING_MESSAGEQUEUE=y +# CONFIG_RT_USING_SIGNALS is not set + +# +# Memory Management +# +CONFIG_RT_USING_MEMPOOL=y +CONFIG_RT_USING_MEMHEAP=y +# CONFIG_RT_USING_NOHEAP is not set +CONFIG_RT_USING_SMALL_MEM=y +# CONFIG_RT_USING_SLAB is not set +# CONFIG_RT_USING_MEMHEAP_AS_HEAP is not set +# CONFIG_RT_USING_USERHEAP is not set +# CONFIG_RT_USING_MEMTRACE is not set +CONFIG_RT_USING_HEAP=y + +# +# Kernel Device Object +# +CONFIG_RT_USING_DEVICE=y +# CONFIG_RT_USING_DEVICE_OPS is not set +# CONFIG_RT_USING_INTERRUPT_INFO is not set +CONFIG_RT_USING_CONSOLE=y +CONFIG_RT_CONSOLEBUF_SIZE=128 +CONFIG_RT_CONSOLE_DEVICE_NAME="uart0" +# CONFIG_RT_PRINTF_LONGLONG is not set +CONFIG_RT_VER_NUM=0x40004 +# CONFIG_RT_USING_CPU_FFS is not set +# CONFIG_ARCH_CPU_STACK_GROWS_UPWARD is not set + +# +# RT-Thread Components +# +CONFIG_RT_USING_COMPONENTS_INIT=y +CONFIG_RT_USING_USER_MAIN=y +CONFIG_RT_MAIN_THREAD_STACK_SIZE=2048 +CONFIG_RT_MAIN_THREAD_PRIORITY=10 + +# +# C++ features +# +# CONFIG_RT_USING_CPLUSPLUS is not set + +# +# Command shell +# +CONFIG_RT_USING_FINSH=y +CONFIG_RT_USING_MSH=y +CONFIG_FINSH_USING_MSH=y +CONFIG_FINSH_THREAD_NAME="tshell" +CONFIG_FINSH_THREAD_PRIORITY=20 +CONFIG_FINSH_THREAD_STACK_SIZE=4096 +CONFIG_FINSH_USING_HISTORY=y +CONFIG_FINSH_HISTORY_LINES=5 +CONFIG_FINSH_USING_SYMTAB=y +CONFIG_FINSH_CMD_SIZE=80 +CONFIG_MSH_USING_BUILT_IN_COMMANDS=y +CONFIG_FINSH_USING_DESCRIPTION=y +# CONFIG_FINSH_ECHO_DISABLE_DEFAULT is not set +# CONFIG_FINSH_USING_AUTH is not set +CONFIG_FINSH_ARG_MAX=10 + +# +# Device virtual file system +# +# CONFIG_RT_USING_DFS is not set + +# +# Device Drivers +# +CONFIG_RT_USING_DEVICE_IPC=y +CONFIG_RT_PIPE_BUFSZ=512 +# CONFIG_RT_USING_SYSTEM_WORKQUEUE is not set +CONFIG_RT_USING_SERIAL=y +CONFIG_RT_USING_SERIAL_V1=y +# CONFIG_RT_USING_SERIAL_V2 is not set +# CONFIG_RT_SERIAL_USING_DMA is not set +CONFIG_RT_SERIAL_RB_BUFSZ=64 +# CONFIG_RT_USING_CAN is not set +# CONFIG_RT_USING_HWTIMER is not set +# CONFIG_RT_USING_CPUTIME is not set +# CONFIG_RT_USING_I2C is not set +# CONFIG_RT_USING_PHY is not set +CONFIG_RT_USING_PIN=y +# CONFIG_RT_USING_ADC is not set +# CONFIG_RT_USING_DAC is not set +# CONFIG_RT_USING_PWM is not set +# CONFIG_RT_USING_MTD_NOR is not set +# CONFIG_RT_USING_MTD_NAND is not set +# CONFIG_RT_USING_PM is not set +# CONFIG_RT_USING_RTC is not set +# CONFIG_RT_USING_SDIO is not set +# CONFIG_RT_USING_SPI is not set +# CONFIG_RT_USING_WDT is not set +# CONFIG_RT_USING_AUDIO is not set +# CONFIG_RT_USING_SENSOR is not set +# CONFIG_RT_USING_TOUCH is not set +# CONFIG_RT_USING_HWCRYPTO is not set +# CONFIG_RT_USING_PULSE_ENCODER is not set +# CONFIG_RT_USING_INPUT_CAPTURE is not set +# CONFIG_RT_USING_WIFI is not set + +# +# Using USB +# +# CONFIG_RT_USING_USB_HOST is not set +# CONFIG_RT_USING_USB_DEVICE is not set + +# +# POSIX layer and C standard library +# +# CONFIG_RT_USING_LIBC is not set +# CONFIG_RT_USING_PTHREADS is not set +CONFIG_RT_LIBC_USING_TIME=y +CONFIG_RT_LIBC_DEFAULT_TIMEZONE=8 + +# +# Network +# + +# +# Socket abstraction layer +# +# CONFIG_RT_USING_SAL is not set + +# +# Network interface device +# +# CONFIG_RT_USING_NETDEV is not set + +# +# light weight TCP/IP stack +# +# CONFIG_RT_USING_LWIP is not set + +# +# AT commands +# +# CONFIG_RT_USING_AT is not set + +# +# VBUS(Virtual Software BUS) +# +# CONFIG_RT_USING_VBUS is not set + +# +# Utilities +# +# CONFIG_RT_USING_RYM is not set +# CONFIG_RT_USING_ULOG is not set +# CONFIG_RT_USING_UTEST is not set +# CONFIG_RT_USING_RT_LINK is not set + +# +# RT-Thread Utestcases +# +# CONFIG_RT_USING_UTESTCASES is not set + +# +# RT-Thread online packages +# + +# +# IoT - internet of things +# +# CONFIG_PKG_USING_LORAWAN_DRIVER is not set +# CONFIG_PKG_USING_PAHOMQTT is not set +# CONFIG_PKG_USING_UMQTT is not set +# CONFIG_PKG_USING_WEBCLIENT is not set +# CONFIG_PKG_USING_WEBNET is not set +# CONFIG_PKG_USING_MONGOOSE is not set +# CONFIG_PKG_USING_MYMQTT is not set +# CONFIG_PKG_USING_KAWAII_MQTT is not set +# CONFIG_PKG_USING_BC28_MQTT is not set +# CONFIG_PKG_USING_WEBTERMINAL is not set +# CONFIG_PKG_USING_CJSON is not set +# CONFIG_PKG_USING_JSMN is not set +# CONFIG_PKG_USING_LIBMODBUS is not set +# CONFIG_PKG_USING_FREEMODBUS is not set +# CONFIG_PKG_USING_LJSON is not set +# CONFIG_PKG_USING_EZXML is not set +# CONFIG_PKG_USING_NANOPB is not set + +# +# Wi-Fi +# + +# +# Marvell WiFi +# +# CONFIG_PKG_USING_WLANMARVELL is not set + +# +# Wiced WiFi +# +# CONFIG_PKG_USING_WLAN_WICED is not set +# CONFIG_PKG_USING_RW007 is not set +# CONFIG_PKG_USING_COAP is not set +# CONFIG_PKG_USING_NOPOLL is not set +# CONFIG_PKG_USING_NETUTILS is not set +# CONFIG_PKG_USING_CMUX is not set +# CONFIG_PKG_USING_PPP_DEVICE is not set +# CONFIG_PKG_USING_AT_DEVICE is not set +# CONFIG_PKG_USING_ATSRV_SOCKET is not set +# CONFIG_PKG_USING_WIZNET is not set +# CONFIG_PKG_USING_ZB_COORDINATOR is not set + +# +# IoT Cloud +# +# CONFIG_PKG_USING_ONENET is not set +# CONFIG_PKG_USING_GAGENT_CLOUD is not set +# CONFIG_PKG_USING_ALI_IOTKIT is not set +# CONFIG_PKG_USING_AZURE is not set +# CONFIG_PKG_USING_TENCENT_IOT_EXPLORER is not set +# CONFIG_PKG_USING_JIOT-C-SDK is not set +# CONFIG_PKG_USING_UCLOUD_IOT_SDK is not set +# CONFIG_PKG_USING_JOYLINK is not set +# CONFIG_PKG_USING_NIMBLE is not set +# CONFIG_PKG_USING_OTA_DOWNLOADER is not set +# CONFIG_PKG_USING_IPMSG is not set +# CONFIG_PKG_USING_LSSDP is not set +# CONFIG_PKG_USING_AIRKISS_OPEN is not set +# CONFIG_PKG_USING_LIBRWS is not set +# CONFIG_PKG_USING_TCPSERVER is not set +# CONFIG_PKG_USING_PROTOBUF_C is not set +# CONFIG_PKG_USING_DLT645 is not set +# CONFIG_PKG_USING_QXWZ is not set +# CONFIG_PKG_USING_SMTP_CLIENT is not set +# CONFIG_PKG_USING_ABUP_FOTA is not set +# CONFIG_PKG_USING_LIBCURL2RTT is not set +# CONFIG_PKG_USING_CAPNP is not set +# CONFIG_PKG_USING_RT_CJSON_TOOLS is not set +# CONFIG_PKG_USING_AGILE_TELNET is not set +# CONFIG_PKG_USING_NMEALIB is not set +# CONFIG_PKG_USING_AGILE_JSMN is not set +# CONFIG_PKG_USING_PDULIB is not set +# CONFIG_PKG_USING_BTSTACK is not set +# CONFIG_PKG_USING_LORAWAN_ED_STACK is not set +# CONFIG_PKG_USING_WAYZ_IOTKIT is not set +# CONFIG_PKG_USING_MAVLINK is not set +# CONFIG_PKG_USING_RAPIDJSON is not set +# CONFIG_PKG_USING_BSAL is not set +# CONFIG_PKG_USING_AGILE_MODBUS is not set +# CONFIG_PKG_USING_AGILE_FTP is not set +# CONFIG_PKG_USING_EMBEDDEDPROTO is not set +# CONFIG_PKG_USING_RT_LINK_HW is not set + +# +# security packages +# +# CONFIG_PKG_USING_MBEDTLS is not set +# CONFIG_PKG_USING_libsodium is not set +# CONFIG_PKG_USING_TINYCRYPT is not set +# CONFIG_PKG_USING_TFM is not set +# CONFIG_PKG_USING_YD_CRYPTO is not set + +# +# language packages +# +# CONFIG_PKG_USING_LUA is not set +# CONFIG_PKG_USING_JERRYSCRIPT is not set +# CONFIG_PKG_USING_MICROPYTHON is not set +# CONFIG_PKG_USING_PIKASCRIPT is not set + +# +# multimedia packages +# +# CONFIG_PKG_USING_OPENMV is not set +# CONFIG_PKG_USING_MUPDF is not set +# CONFIG_PKG_USING_STEMWIN is not set +# CONFIG_PKG_USING_WAVPLAYER is not set +# CONFIG_PKG_USING_TJPGD is not set +# CONFIG_PKG_USING_PDFGEN is not set +# CONFIG_PKG_USING_HELIX is not set +# CONFIG_PKG_USING_AZUREGUIX is not set +# CONFIG_PKG_USING_TOUCHGFX2RTT is not set +# CONFIG_PKG_USING_NUEMWIN is not set +# CONFIG_PKG_USING_MP3PLAYER is not set +# CONFIG_PKG_USING_TINYJPEG is not set + +# +# tools packages +# +# CONFIG_PKG_USING_CMBACKTRACE is not set +# CONFIG_PKG_USING_EASYFLASH is not set +# CONFIG_PKG_USING_EASYLOGGER is not set +# CONFIG_PKG_USING_SYSTEMVIEW is not set +# CONFIG_PKG_USING_SEGGER_RTT is not set +# CONFIG_PKG_USING_RDB is not set +# CONFIG_PKG_USING_QRCODE is not set +# CONFIG_PKG_USING_ULOG_EASYFLASH is not set +# CONFIG_PKG_USING_ULOG_FILE is not set +# CONFIG_PKG_USING_LOGMGR is not set +# CONFIG_PKG_USING_ADBD is not set +# CONFIG_PKG_USING_COREMARK is not set +# CONFIG_PKG_USING_DHRYSTONE is not set +# CONFIG_PKG_USING_MEMORYPERF is not set +# CONFIG_PKG_USING_NR_MICRO_SHELL is not set +# CONFIG_PKG_USING_CHINESE_FONT_LIBRARY is not set +# CONFIG_PKG_USING_LUNAR_CALENDAR is not set +# CONFIG_PKG_USING_BS8116A is not set +# CONFIG_PKG_USING_GPS_RMC is not set +# CONFIG_PKG_USING_URLENCODE is not set +# CONFIG_PKG_USING_UMCN is not set +# CONFIG_PKG_USING_LWRB2RTT is not set +# CONFIG_PKG_USING_CPU_USAGE is not set +# CONFIG_PKG_USING_GBK2UTF8 is not set +# CONFIG_PKG_USING_VCONSOLE is not set +# CONFIG_PKG_USING_KDB is not set +# CONFIG_PKG_USING_WAMR is not set +# CONFIG_PKG_USING_MICRO_XRCE_DDS_CLIENT is not set +# CONFIG_PKG_USING_LWLOG is not set +# CONFIG_PKG_USING_ANV_TRACE is not set +# CONFIG_PKG_USING_ANV_MEMLEAK is not set +# CONFIG_PKG_USING_ANV_TESTSUIT is not set +# CONFIG_PKG_USING_ANV_BENCH is not set +# CONFIG_PKG_USING_DEVMEM is not set +# CONFIG_PKG_USING_REGEX is not set +# CONFIG_PKG_USING_MEM_SANDBOX is not set +# CONFIG_PKG_USING_SOLAR_TERMS is not set +# CONFIG_PKG_USING_GAN_ZHI is not set + +# +# system packages +# + +# +# acceleration: Assembly language or algorithmic acceleration packages +# +# CONFIG_PKG_USING_RT_MEMCPY_CM is not set +# CONFIG_PKG_USING_QFPLIB_M0_FULL is not set +# CONFIG_PKG_USING_QFPLIB_M0_TINY is not set +# CONFIG_PKG_USING_QFPLIB_M3 is not set + +# +# Micrium: Micrium software products porting for RT-Thread +# +# CONFIG_PKG_USING_UCOSIII_WRAPPER is not set +# CONFIG_PKG_USING_UCOSII_WRAPPER is not set +# CONFIG_PKG_USING_UC_CRC is not set +# CONFIG_PKG_USING_UC_CLK is not set +# CONFIG_PKG_USING_UC_COMMON is not set +# CONFIG_PKG_USING_UC_MODBUS is not set +# CONFIG_PKG_USING_GUIENGINE is not set +# CONFIG_PKG_USING_CAIRO is not set +# CONFIG_PKG_USING_PIXMAN is not set +# CONFIG_PKG_USING_PARTITION is not set +# CONFIG_PKG_USING_FAL is not set +# CONFIG_PKG_USING_FLASHDB is not set +# CONFIG_PKG_USING_SQLITE is not set +# CONFIG_PKG_USING_RTI is not set +# CONFIG_PKG_USING_LITTLEVGL2RTT is not set +# CONFIG_PKG_USING_CMSIS is not set +# CONFIG_PKG_USING_DFS_YAFFS is not set +# CONFIG_PKG_USING_LITTLEFS is not set +# CONFIG_PKG_USING_DFS_JFFS2 is not set +# CONFIG_PKG_USING_DFS_UFFS is not set +# CONFIG_PKG_USING_LWEXT4 is not set +# CONFIG_PKG_USING_THREAD_POOL is not set +# CONFIG_PKG_USING_ROBOTS is not set +# CONFIG_PKG_USING_EV is not set +# CONFIG_PKG_USING_SYSWATCH is not set +# CONFIG_PKG_USING_SYS_LOAD_MONITOR is not set +# CONFIG_PKG_USING_PLCCORE is not set +# CONFIG_PKG_USING_RAMDISK is not set +# CONFIG_PKG_USING_MININI is not set +# CONFIG_PKG_USING_QBOOT is not set +# CONFIG_PKG_USING_PPOOL is not set +# CONFIG_PKG_USING_OPENAMP is not set +# CONFIG_PKG_USING_RT_KPRINTF_THREADSAFE is not set +# CONFIG_PKG_USING_LPM is not set +# CONFIG_PKG_USING_TLSF is not set +# CONFIG_PKG_USING_EVENT_RECORDER is not set +# CONFIG_PKG_USING_ARM_2D is not set +# CONFIG_PKG_USING_WCWIDTH is not set +# CONFIG_PKG_USING_MCUBOOT is not set + +# +# peripheral libraries and drivers +# +# CONFIG_PKG_USING_SENSORS_DRIVERS is not set +# CONFIG_PKG_USING_REALTEK_AMEBA is not set +# CONFIG_PKG_USING_SHT2X is not set +# CONFIG_PKG_USING_SHT3X is not set +# CONFIG_PKG_USING_AS7341 is not set +# CONFIG_PKG_USING_STM32_SDIO is not set +# CONFIG_PKG_USING_ICM20608 is not set +# CONFIG_PKG_USING_U8G2 is not set +# CONFIG_PKG_USING_BUTTON is not set +# CONFIG_PKG_USING_PCF8574 is not set +# CONFIG_PKG_USING_SX12XX is not set +# CONFIG_PKG_USING_SIGNAL_LED is not set +# CONFIG_PKG_USING_LEDBLINK is not set +# CONFIG_PKG_USING_LITTLED is not set +# CONFIG_PKG_USING_LKDGUI is not set +# CONFIG_PKG_USING_NRF5X_SDK is not set +# CONFIG_PKG_USING_NRFX is not set +# CONFIG_PKG_USING_WM_LIBRARIES is not set +# CONFIG_PKG_USING_KENDRYTE_SDK is not set +# CONFIG_PKG_USING_INFRARED is not set +# CONFIG_PKG_USING_AGILE_BUTTON is not set +# CONFIG_PKG_USING_AGILE_LED is not set +# CONFIG_PKG_USING_AT24CXX is not set +# CONFIG_PKG_USING_MOTIONDRIVER2RTT is not set +# CONFIG_PKG_USING_AD7746 is not set +# CONFIG_PKG_USING_PCA9685 is not set +# CONFIG_PKG_USING_I2C_TOOLS is not set +# CONFIG_PKG_USING_NRF24L01 is not set +# CONFIG_PKG_USING_TOUCH_DRIVERS is not set +# CONFIG_PKG_USING_MAX17048 is not set +# CONFIG_PKG_USING_RPLIDAR is not set +# CONFIG_PKG_USING_AS608 is not set +# CONFIG_PKG_USING_RC522 is not set +# CONFIG_PKG_USING_WS2812B is not set +# CONFIG_PKG_USING_EMBARC_BSP is not set +# CONFIG_PKG_USING_EXTERN_RTC_DRIVERS is not set +# CONFIG_PKG_USING_MULTI_RTIMER is not set +# CONFIG_PKG_USING_MAX7219 is not set +# CONFIG_PKG_USING_BEEP is not set +# CONFIG_PKG_USING_EASYBLINK is not set +# CONFIG_PKG_USING_PMS_SERIES is not set +# CONFIG_PKG_USING_CAN_YMODEM is not set +# CONFIG_PKG_USING_LORA_RADIO_DRIVER is not set +# CONFIG_PKG_USING_QLED is not set +# CONFIG_PKG_USING_PAJ7620 is not set +# CONFIG_PKG_USING_AGILE_CONSOLE is not set +# CONFIG_PKG_USING_LD3320 is not set +# CONFIG_PKG_USING_WK2124 is not set +# CONFIG_PKG_USING_LY68L6400 is not set +# CONFIG_PKG_USING_DM9051 is not set +# CONFIG_PKG_USING_SSD1306 is not set +# CONFIG_PKG_USING_QKEY is not set +# CONFIG_PKG_USING_RS485 is not set +# CONFIG_PKG_USING_NES is not set +# CONFIG_PKG_USING_VIRTUAL_SENSOR is not set +# CONFIG_PKG_USING_VDEVICE is not set +# CONFIG_PKG_USING_SGM706 is not set +# CONFIG_PKG_USING_STM32WB55_SDK is not set +# CONFIG_PKG_USING_RDA58XX is not set +# CONFIG_PKG_USING_LIBNFC is not set +# CONFIG_PKG_USING_MFOC is not set +# CONFIG_PKG_USING_TMC51XX is not set +# CONFIG_PKG_USING_TCA9534 is not set +# CONFIG_PKG_USING_KOBUKI is not set +# CONFIG_PKG_USING_ROSSERIAL is not set +# CONFIG_PKG_USING_MICRO_ROS is not set +# CONFIG_PKG_USING_MCP23008 is not set +# CONFIG_PKG_USING_BLUETRUM_SDK is not set + +# +# AI packages +# +# CONFIG_PKG_USING_LIBANN is not set +# CONFIG_PKG_USING_NNOM is not set +# CONFIG_PKG_USING_ONNX_BACKEND is not set +# CONFIG_PKG_USING_ONNX_PARSER is not set +# CONFIG_PKG_USING_TENSORFLOWLITEMICRO is not set +# CONFIG_PKG_USING_ELAPACK is not set +# CONFIG_PKG_USING_ULAPACK is not set +# CONFIG_PKG_USING_QUEST is not set +# CONFIG_PKG_USING_NAXOS is not set + +# +# miscellaneous packages +# + +# +# samples: kernel and components samples +# +# CONFIG_PKG_USING_KERNEL_SAMPLES is not set +# CONFIG_PKG_USING_FILESYSTEM_SAMPLES is not set +# CONFIG_PKG_USING_NETWORK_SAMPLES is not set +# CONFIG_PKG_USING_PERIPHERAL_SAMPLES is not set + +# +# entertainment: terminal games and other interesting software packages +# +# CONFIG_PKG_USING_CMATRIX is not set +# CONFIG_PKG_USING_SL is not set +# CONFIG_PKG_USING_CAL is not set +# CONFIG_PKG_USING_ACLOCK is not set +# CONFIG_PKG_USING_THREES is not set +# CONFIG_PKG_USING_2048 is not set +# CONFIG_PKG_USING_SNAKE is not set +# CONFIG_PKG_USING_TETRIS is not set +# CONFIG_PKG_USING_DONUT is not set +# CONFIG_PKG_USING_LIBCSV is not set +# CONFIG_PKG_USING_OPTPARSE is not set +# CONFIG_PKG_USING_FASTLZ is not set +# CONFIG_PKG_USING_MINILZO is not set +# CONFIG_PKG_USING_QUICKLZ is not set +# CONFIG_PKG_USING_LZMA is not set +# CONFIG_PKG_USING_MULTIBUTTON is not set +# CONFIG_PKG_USING_FLEXIBLE_BUTTON is not set +# CONFIG_PKG_USING_CANFESTIVAL is not set +# CONFIG_PKG_USING_ZLIB is not set +# CONFIG_PKG_USING_MINIZIP is not set +# CONFIG_PKG_USING_DSTR is not set +# CONFIG_PKG_USING_TINYFRAME is not set +# CONFIG_PKG_USING_KENDRYTE_DEMO is not set +# CONFIG_PKG_USING_DIGITALCTRL is not set +# CONFIG_PKG_USING_UPACKER is not set +# CONFIG_PKG_USING_UPARAM is not set +# CONFIG_PKG_USING_HELLO is not set +# CONFIG_PKG_USING_VI is not set +# CONFIG_PKG_USING_KI is not set +# CONFIG_PKG_USING_ARMv7M_DWT is not set +# CONFIG_PKG_USING_VT100 is not set +# CONFIG_PKG_USING_UKAL is not set +# CONFIG_PKG_USING_CRCLIB is not set +# CONFIG_PKG_USING_LWGPS is not set +# CONFIG_PKG_USING_STATE_MACHINE is not set +# CONFIG_PKG_USING_MCURSES is not set +# CONFIG_PKG_USING_COWSAY is not set +# CONFIG_PKG_USING_TERMBOX is not set +CONFIG_SOC_SWM320VET7=y + +# +# Hardware Drivers Config +# + +# +# On-chip Peripheral Drivers +# +CONFIG_BSP_USING_GPIO=y + +# +# UART Drivers +# +CONFIG_BSP_USING_UART0=y +# CONFIG_BSP_USING_UART1 is not set diff --git a/bsp/yichip/yc3121-pos/.gitignore b/bsp/yichip/yc3121-pos/.gitignore new file mode 100644 index 0000000000..4a42abf20f --- /dev/null +++ b/bsp/yichip/yc3121-pos/.gitignore @@ -0,0 +1,44 @@ +./.vscode/* +./build/* +*.pyc +*.map +*.dblite +*.elf +*.bin +*.hex +*.axf +*.exe +*.pdb +*.idb +*.ilk +*.old +build +Debug +documentation/html +packages/ +*~ +*.o +*.obj +*.out +*.bak +*.dep +*.lib +*.i +*.d +.DS_Stor* +.config 3 +.config 4 +.config 5 +Midea-X1 +*.uimg +GPATH +GRTAGS +GTAGS +.vscode +JLinkLog.txt +JLinkSettings.ini +DebugConfig/ +RTE/ +settings/ +*.uvguix* +cconfig.h diff --git a/bsp/yichip/yc3121-pos/.ignore_format.yml b/bsp/yichip/yc3121-pos/.ignore_format.yml new file mode 100644 index 0000000000..b7cc004bc7 --- /dev/null +++ b/bsp/yichip/yc3121-pos/.ignore_format.yml @@ -0,0 +1,25 @@ +# files format check exclude path, please follow the instructions below to modify; +# If you need to exclude an entire folder, add the folder path in dir_path; +# If you need to exclude a file, add the path to the file in file_path. + +file_path: +- Libraries/core/board_config.h +- Libraries/core/misc.c +- Libraries/core/misc.h +- Libraries/core/rom_api.h +- Libraries/core/system.c +- Libraries/core/system.h +- Libraries/core/type.h +- Libraries/core/yc3121.h +- Libraries/sdk/yc_dma.c +- Libraries/sdk/yc_dma.h +- Libraries/sdk/yc_gpio.c +- Libraries/sdk/yc_gpio.h +- Libraries/sdk/yc_systick.c +- Libraries/sdk/yc_uart.c +- Libraries/sdk/yc_uart.h + +dir_path: +- Libraries/core +- Libraries/sdk +- Libraries/startup diff --git a/bsp/yichip/yc3121-pos/Kconfig b/bsp/yichip/yc3121-pos/Kconfig new file mode 100644 index 0000000000..59dcef1b29 --- /dev/null +++ b/bsp/yichip/yc3121-pos/Kconfig @@ -0,0 +1,27 @@ +mainmenu "RT-Thread Configuration" + +config BSP_DIR + string + option env="BSP_ROOT" + default "." + +config RTT_DIR + string + option env="RTT_ROOT" + default "../.." + +config PKGS_DIR + string + option env="PKGS_ROOT" + default "packages" + +source "$RTT_DIR/Kconfig" +source "$PKGS_DIR/Kconfig" + +config SOC_SWM320VET7 + bool + select RT_USING_COMPONENTS_INIT + select RT_USING_USER_MAIN + default y + +source "drivers/Kconfig" diff --git a/bsp/yichip/yc3121-pos/Libraries/SConscript b/bsp/yichip/yc3121-pos/Libraries/SConscript new file mode 100644 index 0000000000..4e245383ba --- /dev/null +++ b/bsp/yichip/yc3121-pos/Libraries/SConscript @@ -0,0 +1,17 @@ +from building import * +import rtconfig +cwd = GetCurrentDir() +src = Glob('sdk/*.c') +CPPPATH = [cwd + '/sdk', cwd + '/core', cwd] + +src += Glob('core/*.c') + +if rtconfig.CROSS_TOOL == 'gcc': + src += ['startup/flash_start_gcc.s'] +elif rtconfig.CROSS_TOOL == 'keil': + src += ['startup/startup.s', 'startup/flash_start.s'] +elif rtconfig.CROSS_TOOL == 'iar': + src += ['startup/flash_start_iar.s'] +group = DefineGroup('Libraries', src, depend = [''], CPPPATH = CPPPATH) + +Return('group') diff --git a/bsp/yichip/yc3121-pos/Libraries/core/board_config.h b/bsp/yichip/yc3121-pos/Libraries/core/board_config.h new file mode 100644 index 0000000000..306d8891ba --- /dev/null +++ b/bsp/yichip/yc3121-pos/Libraries/core/board_config.h @@ -0,0 +1,275 @@ +/* +File Name : board_config.h +Author : Yichip +Version : V1.0 +Date : 2020/07/17 +Description : board I/O config file. +*/ + +#ifndef __BOARD_CONFIG_H__ +#define __BOARD_CONFIG_H__ + +#include "yc3121.h" +#include "yc_gpio.h" +#include "yc_exti.h" +#include "yc_spi.h" + +//开发板选择 +#define MPOS_BOARD_V2_1 0 +#define EPOS_BOARD_V1_0 1 +#define BOARD_VER EPOS_BOARD_V1_0 + +//ADC管脚配置 +#define ADC_IO_PORT GPIOC +#define ADC2_IO_PIN GPIO_Pin_7 +#define ADC3_IO_PIN GPIO_Pin_8 + +//外部中断管脚配置 +#define EXTI_PORT EXTI_Line0 +#define EXTI_PIN EXTI_PinSource14 + +#if (BOARD_VER == MPOS_BOARD_V2_1) +//DEBUG串口配置 +#define UARTBAUD 921600 +#define UART0_TX_PORT GPIOA +#define UART0_TX_PIN GPIO_Pin_1 +#define UART0_RX_PORT GPIOA +#define UART0_RX_PIN GPIO_Pin_0 + +//串口1配置 +#define UART1_TX_PORT GPIOA +#define UART1_TX_PIN GPIO_Pin_14 +#define UART1_RX_PORT GPIOA +#define UART1_RX_PIN GPIO_Pin_15 + +//BEEP驱动IO +#define BEEP_PWM 0 +#define BEEP_PORT GPIOA +#define BEEP_PIN GPIO_Pin_11 + +//IC卡在位检测IO +#define DET_PORT GPIOC +#define DET_PIN GPIO_Pin_12 + +//NFC IO +#define NFC_SPI SPI1 +#define NFC_12M_CLK_PORT GPIOA +#define NFC_12M_CLK_PIN GPIO_Pin_3 + +#define NFC_RST_PORT GPIOA +#define NFC_RST_PIN GPIO_Pin_4 + +#define NFC_SPI_MISO_PORT GPIOB +#define NFC_SPI_MISO_PIN GPIO_Pin_2 + +#define NFC_SPI_MOSI_PORT GPIOB +#define NFC_SPI_MOSI_PIN GPIO_Pin_1 + +#define NFC_SPI_SCL_PORT GPIOB +#define NFC_SPI_SCL_PIN GPIO_Pin_0 + +#define NFC_SPI_CS_PORT GPIOB +#define NFC_SPI_CS_PIN GPIO_Pin_6 + +//EEPROM写保护控制IO +#define IIC_WP2_PORT GPIOB +#define IIC_WP2_PIN GPIO_Pin_0 +#define IIC_WP128_PORT GPIOC +#define IIC_WP128_PIN GPIO_Pin_10 + +//IIC驱动IO +#define IIC_SDA_PORT GPIOB +#define IIC_SDA_PIN GPIO_Pin_2 +#define IIC_SCL_PORT GPIOA +#define IIC_SCL_PIN GPIO_Pin_11 + +//KEYBOARD配置 +#define GPIO_GROUP_Line_1 GPIOC +#define Line_1 GPIO_Pin_7 + +#define GPIO_GROUP_Line_2 GPIOC +#define Line_2 GPIO_Pin_9 + +#define GPIO_GROUP_Line_3 GPIOC +#define Line_3 GPIO_Pin_8 + +#define GPIO_GROUP_Line_4 GPIOC +#define Line_4 GPIO_Pin_10 + +#define GPIO_GROUP_Line_5 GPIOC +#define Line_5 GPIO_Pin_11 + +//LCD屏幕驱动配置 +#define LCD_SPI SPI0 +#define LCDSDA_PIN GPIO_Pin_1 +#define LCDSDA_PORT GPIOB +#define LCDSCL_PIN GPIO_Pin_0 +#define LCDSCL_PORT GPIOB +#define LCDCS_PIN GPIO_Pin_6 +#define LCDCS_PORT GPIOC +#define LCDRST_PIN GPIO_Pin_5 +#define LCDRST_PORT GPIOA +#define LCDA0_PIN GPIO_Pin_10 +#define LCDA0_PORT GPIOA +#define LCDBL_PIN GPIO_Pin_2 +#define LCDBL_PORT GPIOA + +#elif (BOARD_VER == EPOS_BOARD_V1_0) +//DEBUG串口配置 +#define UARTBAUD 921600 +#define UART0_TX_PORT GPIOA +#define UART0_TX_PIN GPIO_Pin_1 +#define UART0_RX_PORT GPIOA +#define UART0_RX_PIN GPIO_Pin_0 + +//串口1配置 +#define UART1_TX_PORT GPIOA +#define UART1_TX_PIN GPIO_Pin_14 +#define UART1_RX_PORT GPIOA +#define UART1_RX_PIN GPIO_Pin_15 + +//BEEP驱动IO +#define BEEP_PWM 0 +#define BEEP_PORT GPIOC +#define BEEP_PIN GPIO_Pin_1 + +//IC卡在位检测IO +#define DET_PORT GPIOA +#define DET_PIN GPIO_Pin_4 + +//NFC IO +#define NFC_SPI SPI1 +#define NFC_12M_CLK_PORT GPIOC +#define NFC_12M_CLK_PIN GPIO_Pin_10 + +#define NFC_RST_PORT GPIOC +#define NFC_RST_PIN GPIO_Pin_5 + +#define NFC_TVDD_PORT GPIOC +#define NFC_TVDD_PIN GPIO_Pin_4 + +#define NFC_SPI_MISO_PORT GPIOC +#define NFC_SPI_MISO_PIN GPIO_Pin_6 + +#define NFC_SPI_MOSI_PORT GPIOC +#define NFC_SPI_MOSI_PIN GPIO_Pin_7 + +#define NFC_SPI_SCL_PORT GPIOC +#define NFC_SPI_SCL_PIN GPIO_Pin_8 + +#define NFC_SPI_CS_PORT GPIOC +#define NFC_SPI_CS_PIN GPIO_Pin_9 + +//IIC驱动IO + +//KEYBOARD配置 +#define KEY_PORT_1 GPIOA +#define KEY_PIN_1 GPIO_Pin_9 + +#define KEY_PORT_2 GPIOA +#define KEY_PIN_2 GPIO_Pin_15 + +#define KEY_PORT_3 GPIOA +#define KEY_PIN_3 GPIO_Pin_14 + +#define KEY_PORT_4 GPIOA +#define KEY_PIN_4 GPIO_Pin_8 + +#define KEY_PORT_5 GPIOA +#define KEY_PIN_5 GPIO_Pin_7 + +#define KEY_PORT_6 GPIOA +#define KEY_PIN_6 GPIO_Pin_6 + +//TFT屏幕驱动配置 +#define ST7789VTFTSPI SPI1 +#define ST7789_TFT_SDA_PIN GPIO_Pin_7 +#define ST7789_TFT_SDA_PORT GPIOC + +#define ST7789_TFT_A0_PIN GPIO_Pin_10 +#define ST7789_TFT_A0_PORT GPIOA + +#define ST7789_TFT_SCL_PIN GPIO_Pin_8 +#define ST7789_TFT_SCL_PORT GPIOC + +#define ST7789_TFT_RST_PIN GPIO_Pin_11 +#define ST7789_TFT_RST_PORT GPIOA + +#define ST7789_TFT_CS_PIN GPIO_Pin_5 +#define ST7789_TFT_CS_PORT GPIOA + +#define ST7789_TFT_BL_PIN GPIO_Pin_12 +#define ST7789_TFT_BL_PORT GPIOA +#define ST7789_TFT_BL_HIGH_LIGHT 1 + +/*QRdecode tft */ +//tft camera io +#define QR_CAMERA_FREQ 24 +#define QR_CAMERA_SDA 28 +#define QR_CAMERA_SCL 29 +#define QR_CAMERA_RST 32 +#define QR_CAMERA_PD 31//power down +#define QR_CAMERA_MCLK 35 +#define QR_CAMERA_PCLK 34 +#define QR_CAMERA_DATA 30 +#define QR_CAMERA_CS 42 + +//tft io +#define QR_TFT_RST (11) /*rst pin*/ +#define QR_TFT_CS ( 5) /*cs pin*/ +#define QR_TFT_CLK (40) /*clk pin*/ +#define QR_TFT_MOSI (39) /*mosi pin*/ +#define QR_TFT_A0 (10) /*a0 pin*/ +#define QR_TFT_BL (12 | (1 << 7)) /*bl pin*/ +#define QR_TFT_START_COLUMN ( (320 - 236) / 2 ) /*display center*/ + +//key io +#define QR_KEY_T_MATRIX ( 0) /*key mode :0: T matrix key,1:matrix key*/ +#define QR_KEY_LINE_NUM ( 6) /*Value range 0~10*/ +#define QR_KEY_COL_NUM ( 0) /*Value range (T matrix key: 0)*/ +#define QR_KEY_CANCEL_POSTION ( (5 << 4) | 6 ) /*Exit key*/ +#define QR_KEY_LINE_1 ( 9) /*GPIO pin*/ +#define QR_KEY_LINE_2 (15) /*GPIO pin*/ +#define QR_KEY_LINE_3 (14) /*GPIO pin*/ +#define QR_KEY_LINE_4 ( 8) /*GPIO pin*/ +#define QR_KEY_LINE_5 ( 7) /*GPIO pin*/ +#define QR_KEY_LINE_6 ( 6) /*GPIO pin*/ + +/*QRdecode lcd */ +//lcd io +#define QR_LCD_RST (14) +#define QR_LCD_CS (15) +#define QR_LCD_CLK (10) +#define QR_LCD_MOSI ( 3) +#define QR_LCD_A0 (11) +#define QR_LCD_BL (39 | (1 << 7)) +#define QR_LCD_SPI_BOUDSPEED (0xFF) +#define QR_LCD_BLANK_LINE_NUM ( 0) /*Value range 0~7*/ +#define QR_LCD_COLUMN_NUM (64) /*Value range 0~7*/ +#define QR_LCD_START_COLUMN ((128 - 64)/2) + +//lcd camera io + +#define QR_LCD_CAMERA_FREQ (24) +#define QR_LCD_CAMERA_SDA (17) +#define QR_LCD_CAMERA_SCL (16) +#define QR_LCD_CAMERA_RST (41) +#define QR_LCD_CAMERA_PD ( 5)//power down +#define QR_LCD_CAMERA_MCLK (40) +#define QR_LCD_CAMERA_PCLK (38) +#define QR_LCD_CAMERA_DATA ( 2) +#define QR_LCD_CAMERA_CS (42) + +/*touch*/ +#define TP_Y_HIGH_PORT GPIOA +#define TP_Y_HIGH_IO_PIN GPIO_Pin_4 +#define TP_Y_LOW_PORT GPIOC +#define TP_Y_LOW_IO_PIN GPIO_Pin_12 +#define TP_X_HIGH_PORT GPIOA +#define TP_X_HIGH_IO_PIN GPIO_Pin_13 +#define TP_X_LOW_PORT GPIOC +#define TP_X_LOW_IO_PIN GPIO_Pin_11 + +#endif + +#endif diff --git a/bsp/yichip/yc3121-pos/Libraries/core/misc.c b/bsp/yichip/yc3121-pos/Libraries/core/misc.c new file mode 100644 index 0000000000..24837c1c3b --- /dev/null +++ b/bsp/yichip/yc3121-pos/Libraries/core/misc.c @@ -0,0 +1,102 @@ +/* +File Name : board_config.h +Author : Yichip +Version : V1.0 +Date : 2020/07/17 +Description : misc file. +*/ + +#include "misc.h" + +/* following defines should be used for structure members */ +#define __IM volatile const /*! Defines 'read only' structure member permissions */ +#define __OM volatile /*! Defines 'write only' structure member permissions */ +#define __IOM volatile /*! Defines 'read / write' structure member permissions */ + +/* Memory mapping of Cortex-M0 Hardware */ +#define SCS_BASE (0xE000E000UL) /*!< System Control Space Base Address */ +#define NVIC_BASE (SCS_BASE + 0x0100UL) /*!< NVIC Base Address */ +#define SCB_BASE (SCS_BASE + 0x0D00UL) /*!< System Control Block Base Address */ + +typedef struct +{ + __IM uint32_t CPUID; /*!< Offset: 0x000 (R/ ) CPUID Base Register */ + __IOM uint32_t ICSR; /*!< Offset: 0x004 (R/W) Interrupt Control and State Register */ + uint32_t RESERVED0; + __IOM uint32_t AIRCR; /*!< Offset: 0x00C (R/W) Application Interrupt and Reset Control Register */ + __IOM uint32_t SCR; /*!< Offset: 0x010 (R/W) System Control Register */ + __IOM uint32_t CCR; /*!< Offset: 0x014 (R/W) Configuration Control Register */ + uint32_t RESERVED1; + __IOM uint32_t SHP[2U]; /*!< Offset: 0x01C (R/W) System Handlers Priority Registers. [0] is RESERVED */ + __IOM uint32_t SHCSR; /*!< Offset: 0x024 (R/W) System Handler Control and State Register */ +} SCB_Type; + +/** + \brief Structure type to access the Nested Vectored Interrupt Controller (NVIC). + */ +typedef struct +{ + __IOM uint32_t ISER[1U]; /*!< Offset: 0x000 (R/W) Interrupt Set Enable Register */ + uint32_t RESERVED0[31U]; + __IOM uint32_t ICER[1U]; /*!< Offset: 0x080 (R/W) Interrupt Clear Enable Register */ + uint32_t RSERVED1[31U]; + __IOM uint32_t ISPR[1U]; /*!< Offset: 0x100 (R/W) Interrupt Set Pending Register */ + uint32_t RESERVED2[31U]; + __IOM uint32_t ICPR[1U]; /*!< Offset: 0x180 (R/W) Interrupt Clear Pending Register */ + uint32_t RESERVED3[31U]; + uint32_t RESERVED4[64U]; + __IOM uint32_t IP[8U]; /*!< Offset: 0x300 (R/W) Interrupt Priority Register */ +} NVIC_Type; + +#define SCB ((SCB_Type *)SCB_BASE) /*!< SCB configuration struct */ +#define NVIC ((NVIC_Type *)NVIC_BASE) /*!< NVIC configuration struct */ + +/* The following MACROS handle generation of the register offset and byte masks */ +#define _BIT_SHIFT(IRQn) (((((uint32_t)(int32_t)(IRQn))) & 0x03UL) * 8UL) +#define _SHP_IDX(IRQn) ((((((uint32_t)(int32_t)(IRQn)) & 0x0FUL) - 8UL) >> 2UL)) +#define _IP_IDX(IRQn) ((((uint32_t)(int32_t)(IRQn)) >> 2UL)) + +/* ----------------Configuration of the Cortex-M0 Processor and Core Peripherals---------------- */ +#define __CM0_REV 0x0000 /*!< Cortex-M0 Core Revision */ +#define __MPU_PRESENT 0 /*!< MPU present or not */ +#define __NVIC_PRIO_BITS 2 /*!< Number of Bits used for Priority Levels */ +#define __Vendor_SysTickConfig 0 /*!< Set to 1 if different SysTick Config is used */ +/* End of group Configuration_of_CMSIS */ + +uint32_t NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority) +{ + if ((int32_t)(IRQn) < 0) + { + SCB->SHP[_SHP_IDX(IRQn)] = ((uint32_t)(SCB->SHP[_SHP_IDX(IRQn)] & ~(0xFFUL << _BIT_SHIFT(IRQn))) | + (((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL) << _BIT_SHIFT(IRQn))); + } + else + { + NVIC->IP[_IP_IDX(IRQn)] = ((uint32_t)(NVIC->IP[_IP_IDX(IRQn)] & ~(0xFFUL << _BIT_SHIFT(IRQn))) | + (((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL) << _BIT_SHIFT(IRQn))); + } + return SUCCESS; +} + +#define SBC_ICSR_PENDSV_IRQ 28 +void trigger_PendSV(void) +{ + SCB->ICSR |= (1 << SBC_ICSR_PENDSV_IRQ); +} + +void NVIC_EnableIRQ(IRQn_Type IRQnx) +{ + enable_intr((int)IRQnx); +} + +void NVIC_DisableIRQ(IRQn_Type IRQnx) +{ + disable_intr((int)IRQnx); +} + +void soft_reset(void) +{ + SYSCTRL_RST_EN |= 0x01; + SYSCTRL_RESET = 0x55; + while (1); +} diff --git a/bsp/yichip/yc3121-pos/Libraries/core/misc.h b/bsp/yichip/yc3121-pos/Libraries/core/misc.h new file mode 100644 index 0000000000..519fc2c94b --- /dev/null +++ b/bsp/yichip/yc3121-pos/Libraries/core/misc.h @@ -0,0 +1,93 @@ +/* +File Name : board_config.h +Author : Yichip +Version : V1.0 +Date : 2020/07/17 +Description : misc file. +*/ + +#ifndef __MISC_H +#define __MISC_H +#include "yc3121.h" + +#ifdef __cplusplus +extern "C" { +#endif + +typedef enum +{ + SVCall_IRQn = -5, //SVC_IRQHandler + PendSV_IRQn = -2, //PENDSV_IRQHandler + SysTick_IRQn = -1, //SYSTICK_IRQHandler + USB_IRQn = 0, + IIC_IRQn = 1, + QSPI_IRQn = 2, + SPI0_IRQn = 3, + SPI1_IRQn = 4, + UART0_IRQn = 5, + UART1_IRQn = 6, + MEMCP_IRQn = 7,//DMA MEM_TO_MEM + RSA_IRQn = 8, + SCI0_IRQn = 9, + SCI1_IRQn = 10, + BT_IRQn = 11, + GPIO_IRQn = 12, + TIM0_IRQn = 13, + TIM1_IRQn = 14, + TIM2_IRQn = 15, + TIM3_IRQn = 16, + TIM4_IRQn = 17, + TIM5_IRQn = 18, + TIM6_IRQn = 19, + TIM7_IRQn = 20, + TIM8_IRQn = 21, + SM4_IRQn = 22, + SEC_IRQn = 23, + MSR_IRQn = 24, + TRNG_IRQn = 25, + WDT_IRQn = 26 +} IRQn_Type; + +/** + * @brief Enable External Interrupt + * @param IRQnx IRQn External interrupt number. Value cannot be negative. + * @retval none + */ +void NVIC_EnableIRQ(IRQn_Type IRQnx); + +/** + * @brief Disable External Interrupt + * @param IRQnx IRQn External interrupt number. Value cannot be negative. + * @retval none + */ +void NVIC_DisableIRQ(IRQn_Type IRQnx); + +/** + * @brief Set Interrupt Priority + * @param IRQn Interrupt number. + * @retval SUCCESS or ERROR + */ +uint32_t NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority); + + +/** + * @brief trigger PendSV Interrupt + * @param none + * @retval none + */ +void trigger_PendSV(void); + +/** + * @brief System Reset + * @param none + * @retval none + */ +void soft_reset(void); + + +#ifdef __cplusplus +} +#endif + +#endif /* __MISC_H */ + diff --git a/bsp/yichip/yc3121-pos/Libraries/core/rom_api.h b/bsp/yichip/yc3121-pos/Libraries/core/rom_api.h new file mode 100644 index 0000000000..bd57d6056d --- /dev/null +++ b/bsp/yichip/yc3121-pos/Libraries/core/rom_api.h @@ -0,0 +1,42 @@ +/* +File Name : rom_api.h +Author : Yichip +Version : V1.0 +Date : 2020/02/11 +Description : rom fun information. +*/ + +#ifndef __ROM_API_H__ +#define __ROM_API_H__ + +/* TIMER */ +#define FUNC_DELAY_US_ADDR (0x4238 + 1) +#define FUNC_DELAY_MS_ADDR (0x425c + 1) + +/* OTP */ +#define FUNC_INIT_OTP_ADDR (0x442c + 1) +#define FUNC_DEINIT_OTP_ADDR (0x4480 + 1) +#define FUNC_READ_OTP_ADDR (0x449c + 1) +#define FUNC_WRITE_OTP_ADDR (0x4594 + 1) +#define FUNC_READ_CHIPID_ADDR (0x45d8 + 1) +#define FUNC_READ_CHIPLF_ADDR (0x45e6 + 1) + +/* LPM */ +#define FUNC_LPM_READ_ADDR (0x4c80 + 1) +#define FUNC_LPM_WRITE_ADDR (0x4c9c + 1) +#define FUNC_LPM_BT_WRITE_ADDR (0x4cb0 + 1) +#define FUNC_LPM_BT_READ_ADDR (0x4d24 + 1) +#define FUNC_LPM_SLEEP_ADDR (0x4d68 + 1) +#define FUNC_SETLPMVAL_ADDR (0x4280 + 1) + +/* QSPI */ +#define FUNC_ENC_WRITE_FLASH_ADDR (0x51f0 + 1) +#define FUNC_QSPI_FLASH_SECTORERASE_ADDR (0x48b4 + 1) +#define FUNC_QSPI_FLASH_BLOCKERASE_ADDR (0x48c0 + 1) +#define FUNC_QSPI_FLASH_WRITE_ADDR (0x47f4 + 1) +#define FUNC_QSPI_FLASH_READ_ADDR (0x48f6 + 1) +#define FUNC_FLASH_BLANK_CHECK (0x513c + 1) +#define FUNC_PREFETCH (0x4404 + 1) +#define FUNC_READ_FLASH_ID (0x4960 + 1) + +#endif diff --git a/bsp/yichip/yc3121-pos/Libraries/core/system.c b/bsp/yichip/yc3121-pos/Libraries/core/system.c new file mode 100644 index 0000000000..99b3f8b928 --- /dev/null +++ b/bsp/yichip/yc3121-pos/Libraries/core/system.c @@ -0,0 +1,254 @@ +/* +File Name : system.c +Author : Yichip +Version : V1.0 +Date : 2019/12/4 +Description : none. +*/ + +#include +#include "system.h" + +//***************************************************************************** +// +//! A simple MyPrintf function supporting \%c, \%d, \%p, \%s, \%u,\%x, and \%X. +//! +//! \param format is the format string. +//! \param ... are the optional arguments, which depend on the contents of the +//! \return None. +// +//***************************************************************************** + +static const int8_t *const g_pcHex1 = "0123456789abcdef"; +static const int8_t *const g_pcHex2 = "0123456789ABCDEF"; + + +void printfsend(UART_TypeDef UARTx, uint8_t *buf, int len) +{ + uint8_t printbuf[256]; + for (int i = 0; i < len; i++) + { + printbuf[i] = buf[i]; + } + + UART_SendBuf(UARTx, printbuf, len); +} + +void MyPrintf(char *format, ...) +{ + uint32_t ulIdx, ulValue, ulPos, ulCount, ulBase, ulNeg; + int8_t *pcStr, pcBuf[16], cFill; + char HexFormat; + va_list vaArgP; + + va_start(vaArgP, format); + + while (*format) + { + // Find the first non-% character, or the end of the string. + for (ulIdx = 0; (format[ulIdx] != '%') && (format[ulIdx] != '\0'); ulIdx++) + { + } + + // Write this portion of the string. + if (ulIdx > 0) + { + printfsend(UART0, (uint8_t *)format, ulIdx); + } + + format += ulIdx; + + if (*format == '%') + { + format++; + + // Set the digit count to zero, and the fill character to space + // (i.e. to the defaults). + ulCount = 0; + cFill = ' '; + + again: + switch (*format++) + { + case '0': + case '1': + case '2': + case '3': + case '4': + case '5': + case '6': + case '7': + case '8': + case '9': + { + if ((format[-1] == '0') && (ulCount == 0)) + { + cFill = '0'; + } + + ulCount *= 10; + ulCount += format[-1] - '0'; + + goto again; + } + + case 'c': + { + ulValue = va_arg(vaArgP, unsigned long); + printfsend(UART0, (uint8_t *)&ulValue, 1); + break; + } + + case 'd': + { + ulValue = va_arg(vaArgP, unsigned long); + ulPos = 0; + + if ((long)ulValue < 0) + { + ulValue = -(long)ulValue; + ulNeg = 1; + } + else + { + ulNeg = 0; + } + + ulBase = 10; + goto convert; + } + + case 's': + { + pcStr = (int8_t *)va_arg(vaArgP, char *); + + for (ulIdx = 0; pcStr[ulIdx] != '\0'; ulIdx++) + { + } + + printfsend(UART0, (uint8_t *)pcStr, ulIdx); + + if (ulCount > ulIdx) + { + ulCount -= ulIdx; + while (ulCount--) + { + printfsend(UART0, (uint8_t *)" ", 1); + } + } + break; + } + + case 'u': + { + ulValue = va_arg(vaArgP, unsigned long); + ulPos = 0; + ulBase = 10; + ulNeg = 0; + goto convert; + } + + case 'X': + { + ulValue = va_arg(vaArgP, unsigned long); + ulPos = 0; + ulBase = 16; + ulNeg = 0; + HexFormat = 'X'; + goto convert; + } + + case 'x': + + case 'p': + { + ulValue = va_arg(vaArgP, unsigned long); + ulPos = 0; + ulBase = 16; + ulNeg = 0; + HexFormat = 'x'; + + convert: + for (ulIdx = 1; + (((ulIdx * ulBase) <= ulValue) && + (((ulIdx * ulBase) / ulBase) == ulIdx)); + ulIdx *= ulBase, ulCount--) + { + } + + if (ulNeg) + { + ulCount--; + } + + if (ulNeg && (cFill == '0')) + { + pcBuf[ulPos++] = '-'; + ulNeg = 0; + } + + if ((ulCount > 1) && (ulCount < 16)) + { + for (ulCount--; ulCount; ulCount--) + { + pcBuf[ulPos++] = cFill; + } + } + + if (ulNeg) + { + pcBuf[ulPos++] = '-'; + } + + for (; ulIdx; ulIdx /= ulBase) + { + if (HexFormat == 'x') + pcBuf[ulPos++] = g_pcHex1[(ulValue / ulIdx) % ulBase]; //x + else + pcBuf[ulPos++] = g_pcHex2[(ulValue / ulIdx) % ulBase]; //X + } + + printfsend(UART0, (uint8_t *)pcBuf, ulPos); + break; + } + + case '%': + { + printfsend(UART0, (uint8_t *)format - 1, 1); + break; + } + + default: + { + printfsend(UART0, (uint8_t *)"ERROR", 5); + break; + } + } //switch + } //if + } //while + va_end(vaArgP); +} + +void printv(uint8_t *buf, uint32_t len, uint8_t *s) +{ + uint32_t i = 0; + uint32_t n = 0; + MyPrintf("\r\n %s:", s); + for (i = 0; i < len; i++) + { + if (i % 16 == 0) + { + MyPrintf("\r\n%08x:", n); + n += 16; + } + MyPrintf("%02x ", buf[i]); + } +} + +void _assert_handler(const char *file, int line, const char *func) +{ +#if defined(SDK_DEBUG) + MyPrintf("Assert trigger at file: %s line:%d func: %s\n ", file, line, func); +#endif + while (1); +} diff --git a/bsp/yichip/yc3121-pos/Libraries/core/system.h b/bsp/yichip/yc3121-pos/Libraries/core/system.h new file mode 100644 index 0000000000..b7bd069a98 --- /dev/null +++ b/bsp/yichip/yc3121-pos/Libraries/core/system.h @@ -0,0 +1,43 @@ +/* +File Name : system.h +Author : Yichip +Version : V1.0 +Date : 2018/05/22 +Description : none. +*/ + +#ifndef __SYSTEM_H__ +#define __SYSTEM_H__ + + +#include +#include "yc_uart.h" + +//#define SDK_DEBUG //Debug switch + +#define BIT_SET(a,b) ((a) |= (1<<(b))) +#define BIT_CLEAR(a,b) ((a) &= ~(1<<(b))) +#define BIT_FLIP(a,b) ((a) ^= (1<<(b))) //bit Negation +#define BIT_GET(a,b) (((a) & (1<<(b)))>>(b)) + +/** + * @brief Print format string to serial port 0.You need to initialize the serial port 0 before you use MyPrintf. + * + * @param format : format string + * @param ...: format parameter + */ +void MyPrintf(char *format, ...); + +void _assert_handler(const char *file, int line, const char *func); + +void printv(uint8_t *buf, uint32_t len, uint8_t *s); + +#define _ASSERT(x) \ +if (!(x)) \ +{ \ + _assert_handler(__FILE__,__LINE__,__FUNCTION__);\ +} + + +#endif /*__SYSTEM_H__*/ + diff --git a/bsp/yichip/yc3121-pos/Libraries/core/type.h b/bsp/yichip/yc3121-pos/Libraries/core/type.h new file mode 100644 index 0000000000..112f0374e6 --- /dev/null +++ b/bsp/yichip/yc3121-pos/Libraries/core/type.h @@ -0,0 +1,67 @@ +/* +File Name : type.h +Author : Yichip +Version : V1.0 +Date : 2018/05/25 +Description : Data type definition. +*/ + +#ifndef __TYPE_H__ +#define __TYPE_H__ + +#if defined (__CC_ARM) || defined ( __ICCARM__ ) +typedef unsigned char uint8_t; +typedef unsigned short uint16_t; +typedef unsigned int uint32_t; +typedef unsigned long long uint64_t; +typedef unsigned char byte; +typedef unsigned short word; + +typedef signed char int8_t; +typedef signed short int16_t; +typedef signed int int32_t; +typedef signed long long int64_t; +#else +#include "stdio.h" +typedef unsigned char byte; +typedef unsigned short word; +#endif + +/** + * @brief __NOINLINE definition + */ +#if defined ( __CC_ARM ) || defined ( __GNUC__ ) +/* ARM & GNUCompiler + ---------------- +*/ +#define __NOINLINE noinline + +#elif defined ( __ICCARM__ ) +/* ICCARM Compiler + --------------- +*/ +#define __NOINLINE _Pragma("optimize = no_inline") + +#endif + +#ifndef Boolean +typedef enum {FALSE = 0, TRUE =1} Boolean; +#define IS_BOOLEAN(bool) ((bool == FALSE) || (bool == TRUE)) +#endif + +#ifndef FunctionalState +typedef enum {DISABLE = 0, ENABLE =1} FunctionalState; +#define IS_FUNCTIONAL_STATE(state) ((state== DISABLE) || (state == ENABLE)) +#endif + +#ifndef FunctionalState +typedef enum {ERROR = 0, SUCCESS = 1} ErrorStatus; +#define IS_ERROR_STATE(status) ((status== ERROR) || (status == SUCCESS)) +#endif + +#ifndef FlagStatus +typedef enum {RESET = 0, SET = !RESET} FlagStatus, ITStatus; +#endif + +#endif /*__TYPE_H__*/ + diff --git a/bsp/yichip/yc3121-pos/Libraries/core/yc3121.h b/bsp/yichip/yc3121-pos/Libraries/core/yc3121.h new file mode 100644 index 0000000000..0e06007591 --- /dev/null +++ b/bsp/yichip/yc3121-pos/Libraries/core/yc3121.h @@ -0,0 +1,666 @@ +/* +File Name : yc3121.h +Author : Yichip +Version : V1.0 +Date : 2018/03/27 +Description : Register and hardware information. +*/ + +#ifndef __YC3121_H__ +#define __YC3121_H__ + +#include "type.h" +#include "system.h" +#include +#include "rom_api.h" + +#define NO_BT 0 +#define EXIST_BT 1 +#define NO_XTAL 2 + +#define VERSIONS EXIST_BT + +#define M0_FPGA 1 +#define POS_FPGA 2 +#define POS_CHIP 3 + +#define HARDWAER POS_CHIP + +#if (HARDWAER == M0_FPGA) + #define CPU_MHZ (24*1000000) +#elif (HARDWAER == POS_CHIP) + #define CRYSTAL_CLK (192*1000000) + #define CPU_MHZ ((CRYSTAL_CLK)/((SYSCTRL_HCLK_CON&0x0f)+2)) +#endif + +#define noinline __attribute__((noinline)) + +#define IPC_HOLD_BT *(volatile byte*)0xC4FEF +#define IPC_RX_START_ADDR (volatile byte*)0xc4ff0 +#define IPC_RX_END_ADDR (volatile byte*)0xc4ff2 +#define IPC_RX_READ_PTR (volatile byte*)0xc4ff4 +#define IPC_RX_WRITE_PTR (volatile byte*)0xc4ff6 +#define IPC_TX_START_ADDR (volatile byte*)0xc4ff8 +#define IPC_TX_END_ADDR (volatile byte*)0xc4ffa +#define IPC_TX_READ_PTR (volatile byte*)0xc4ffc +#define IPC_TX_WRITE_PTR (volatile byte*)0xc4ffe + +#define BT_REV *(volatile byte*)0xc8000 +#define BT_STEP *(volatile byte*)0xc8001 +#define BT_PC *(volatile word*)0xc800e +#define BT_RESET *(volatile byte*)0xc8010 +#define BT_UCODE_HI *(volatile byte*)0xc8022 +#define BT_UCODE_CTRL *(volatile byte*)0xc8023 +#define BT_UCODE_LO *(volatile byte*)0xc8024 +#define BT_UCODE_DATA *(volatile byte*)0xc8025 +#define BT_RHALFSLOT_LOW *(volatile byte*)0xc8040 +#define BT_CONTRU *(volatile byte*)0xc812c +#define BT_CONTWU *(volatile byte*)0xc812e +#define BT_CONFIG *(volatile byte*)0xc8043 +#define BT_CLKPLL_EN *(volatile byte*)0xc8905 +#define BT_CHGPUMP_EN *(volatile byte*)0xc8973 +#define WAKEUP_BT *(volatile byte*)0xF853C + +#define BT_INIT_FLAG 7 +#define WAKEUP_BT_FLAG 2 + +//register base address + +#define WDT_BASEADDR 0xf0000 +#define SCI7816_BASEADDR 0xf0400 + +#define TIMER_BASEADDR 0xf0c00 +#define SM4_BASEADDR 0xf5200 +#define RSA_BASEADDR 0xf5800 +#define USB_BASEADDR 0xf6000 +#define DES_BASEADDR 0xf8000 +#define CRC_BASEADDR 0xf8200 +#define AES_BASEADDR 0xf8300 +#define LPM_BASEADDR 0xf8400 +#define SYSCTRL_BASEADDR 0xf8500 +#define SECURE_BASEADDR 0xf8540 +#define CLKGEN_BASEADDR 0xf8560 +#define MPU_BASEADDR 0xf8580 +#define SHA_BASEADDR 0xf8600 +#define GPIO_BASEADDR 0xf8700 +#define DMA_BASEADDR 0xf8800 +#define QSPI_BASEADDR DMA_BASEADDR +#define ISO7811_BASEADDR 0xf8f00 + +#define WD_CONFIG *(volatile int*)(WDT_BASEADDR + 0x00) +#define WD_STATUS *(volatile int*)(WDT_BASEADDR + 0x04) +#define WD_KICK *(volatile int*)(WDT_BASEADDR + 0x08) +#define WD_CLEAR *(volatile int*)(WDT_BASEADDR + 0x0c) + +#define SCI7816_MODE *(volatile int*)(SCI7816_BASEADDR + 0x00) +#define SCI7816_CTRL *(volatile int*)(SCI7816_BASEADDR + 0x08) +#define SCI7816_STAT *(volatile int*)(SCI7816_BASEADDR + 0x0c) +#define SCI7816_INT *(volatile int*)(SCI7816_BASEADDR + 0x10) +#define SCI7816_DATA *(volatile int*)(SCI7816_BASEADDR + 0x20) +#define SCI7816_ETU *(volatile int*)(SCI7816_BASEADDR + 0x28) +#define SCI7816_BGT *(volatile int*)(SCI7816_BASEADDR + 0x2c) +#define SCI7816_CWT *(volatile int*)(SCI7816_BASEADDR + 0x30) +#define SCI7816_EDC *(volatile int*)(SCI7816_BASEADDR + 0x34) + +#define PWM_TOTAL 9 + +#define TIM_PCNT(x) *(volatile int*)(TIMER_BASEADDR + x*8) +#define TIM_NCNT(x) *(volatile int*)(TIMER_BASEADDR + 4 + x*8) +#define TIM_CTRL *(volatile int*)(TIMER_BASEADDR + PWM_TOTAL*8) +#define TIM_CTRL1 *(volatile int*)(TIMER_BASEADDR + PWM_TOTAL*8 + 4) +#define TIM_CNT(x) *(volatile int*)(TIMER_BASEADDR + PWM_TOTAL*8 + (PWM_TOTAL*4 + 31)/32*4 + x*4) + +#define SHA_DATA(x) *(volatile int*)(SHA_BASEADDR + 0x00 + x*4) +#define SHA_BDATA(x) *(volatile uint8_t*)(SHA_BASEADDR + 0x00 + x) +#define SHA_RESULT(x) *(volatile int*)(SHA_BASEADDR + 0x80 + x*4) +#define SHA_CTRL *(volatile int*)(SHA_BASEADDR + 0xc0) + +#define SYSCTRL_PRIV_CTRL *(volatile int*)(SYSCTRL_BASEADDR + 0x0) +#define SYSCTRL_STATUS *(volatile int*)(SYSCTRL_BASEADDR + 0x4) +#define OTP_ADDR *(volatile short*)(SYSCTRL_BASEADDR + 0x8) +#define OTP_CTRL *(volatile short*)(SYSCTRL_BASEADDR + 0xa) +#define OTP_RDATA *(volatile byte*)(SYSCTRL_BASEADDR + 0xc) +#define OTP_STATUS *(volatile int*)(SYSCTRL_BASEADDR + 0xc) + +#define SYSCTRL_LPM_RDATA *(volatile int*)(SYSCTRL_BASEADDR + 0x10) +#define SYSCTRL_LPM_SCB *(volatile int*)(SYSCTRL_BASEADDR + 0x14) +#define SYSCTRL_HWCTRL(x) *(volatile uint8_t*)(SYSCTRL_BASEADDR + 0x18 + x) +#define SYSCTRL_RNG_CTRL *(volatile int*)(SYSCTRL_BASEADDR + 0x28) +#define SYSCTRL_RNG_DATAB(x) *(volatile uint8_t*)(SYSCTRL_BASEADDR + 0x2c+x) + +#define SYSCTRL_RNG_DATA(x) *(volatile int*)(SYSCTRL_BASEADDR + 0x2c+x*4) + +#define SYSCTRL_ROM_SWITCH *(volatile uint8_t*)(SYSCTRL_BASEADDR + 0x3c) +#define SYSCTRL_LPM_STATUS *(volatile byte *)(SYSCTRL_BASEADDR + 0x3d) +#define SYSCTRL_OTPN_ADDR *(volatile uint8_t*)(SYSCTRL_BASEADDR + 0x3e) +#define SYSCTRL_OTPU_ADDR *(volatile uint8_t*)(SYSCTRL_BASEADDR + 0x3f) + +#define SECURE_CTRL *(volatile int*)(SECURE_BASEADDR + 0x0) +#define SECURE_STATUS *(volatile int*)(SECURE_BASEADDR + 0x4) +#define SECURE_MEDCON *(volatile int*)(SECURE_BASEADDR + 0x8) +#define SECURE_RAMKEY *(volatile int*)(SECURE_BASEADDR + 0xc) + +#define SYSCTRL_HCLK_CON *(volatile int*)(CLKGEN_BASEADDR + 0x00) +#define SYSCTRL_RSACLK *(volatile int*)(CLKGEN_BASEADDR + 0x08) +#define SYSCTRL_CLK_CLS *(volatile int*)(CLKGEN_BASEADDR + 0x0c) +#define SYSCTRL_RST_EN *(volatile int*)(CLKGEN_BASEADDR + 0x14) +#define SYSCTRL_RST_TYPE *(volatile int*)(CLKGEN_BASEADDR + 0x18) +#define SYSCTRL_RESET *(volatile int*)(CLKGEN_BASEADDR + 0x1c) + +#define MPUCTRL_ID *(volatile int*)(MPU_BASEADDR + 0x00) +#define MPUCTRL_CTRL *(volatile int*)(MPU_BASEADDR + 0x04) +#define MPUCTRL_FSR *(volatile int*)(MPU_BASEADDR + 0x0c) +#define MPUCTRL_FAR *(volatile int*)(MPU_BASEADDR + 0x10) + +#define MPUCTRL_PROTECTION *(volatile int*)(MPU_BASEADDR + 0x14) +#define MPUCTRL_USER_START *(volatile int*)(MPU_BASEADDR + 0x18) +#define MPUCTRL_REGION_BASE(x) *(volatile int*)(MPU_BASEADDR + 0x40 + x*4) +#define MPUCTRL_REGION_LIMIT(x) *(volatile int*)(MPU_BASEADDR + 0x60 + x*4) + +#define LPM_CTRL (volatile int*)(LPM_BASEADDR + 0x00) +#define LPM_SENSOR (volatile int*)(LPM_BASEADDR + 0x04) +#define LPM_WKUP_TIMER (volatile int*)(LPM_BASEADDR + 0x08) +#define LPM_SECMAX (volatile int*)(LPM_BASEADDR+0x0c) +#define LPM_GPIO_WKUP (volatile int*)(LPM_BASEADDR + 0x10) +#define LPM_GPIO_WKHI (volatile int*)(LPM_BASEADDR + 0x14) +#define LPM_SLEEP (volatile int*)(LPM_BASEADDR + 0x20) +#define LPM_CLR_INTR (volatile int*)(LPM_BASEADDR + 0x24) +#define LPM_STATUS (volatile int*)(LPM_BASEADDR + 0x78) +#define LPM_RTC_CNT (volatile int*)(LPM_BASEADDR + 0x7c) +#define LPM_KEY(x) (volatile int*)(LPM_BASEADDR + 0x80 + x*4) + +#define GPIO_GROUP_NUM 3 +#define GPIO_PIN_NUM 16 + +#define GPIO_CONFIG(x) *((volatile uint8_t*)(GPIO_BASEADDR + x)) +#define GPIO_INTR_EN(groupx) *((volatile uint16_t*)(GPIO_BASEADDR+GPIO_GROUP_NUM*GPIO_PIN_NUM) + groupx) +#define GPIO_TRIG_MODE(groupx) *((volatile uint16_t*)(GPIO_BASEADDR+(GPIO_GROUP_NUM*GPIO_PIN_NUM) +GPIO_GROUP_NUM*2) +groupx) +#define GPIO_IN(groupx) *((volatile uint16_t*)(GPIO_BASEADDR+(GPIO_GROUP_NUM*GPIO_PIN_NUM) +GPIO_GROUP_NUM*4)+groupx) + +#define DMA_SRC_ADDR(x) *(volatile int*)(DMA_BASEADDR + 0x00 + x*0x100) +#define DMA_DEST_ADDR(x) *(volatile int*)(DMA_BASEADDR + 0x04 + x*0x100) +#define DMA_LEN(x) *(volatile int*)(DMA_BASEADDR + 0x08 + x*0x100) +#define DMA_CONFIG(x) *(volatile uint8_t*)(DMA_BASEADDR + 0x0c + x*0x100) +#define DMA_START(x) *(volatile uint8_t*)(DMA_BASEADDR + 0x0f + x*0x100) +#define DMA_STATUS(x) *(volatile int*)(DMA_BASEADDR + 0x10 + x*0x100) +#define DMA_RPTR(x) *(volatile int*)(DMA_BASEADDR + 0x14 + x*0x100) +#define DMA_WPTR(x) *(volatile int*)(DMA_BASEADDR + 0x18 + x*0x100) + +#define QSPI_CTRL *(volatile int*)(QSPI_BASEADDR + 0x1c) +#define QAES_ADDRKEY *(volatile int*)(QSPI_BASEADDR + 0x20) +#define QAES_CTRL *(volatile int*)(QSPI_BASEADDR + 0x24) +#define QAES_RAND(x) *(volatile int*)(QSPI_BASEADDR + 0x28 + x*4) +#define QAES_KEY(x) *(volatile int*)(QSPI_BASEADDR + 0x30 + x*4) +#define QAES_DATA(x) *(volatile int*)(QSPI_BASEADDR + 0x40 + x*4) +#define QAES_KEYB(x) *(volatile byte*)(QSPI_BASEADDR + 0x30 + x) +#define SPID0_CTRL *(volatile int*)0xf891c +#define SPID1_CTRL *(volatile int*)0xf8a1c +#define UART0_CTRL *(volatile int*)0xf8b1c +#define UART0_INTR *(volatile int*)0xf8b20 +#define UART0_RDATA *(volatile byte*)0xf8b24 +#define UART0_STATUS *(volatile int*)0xf8b28 +#define UART1_CTRL *(volatile int*)0xf8c1c +#define UART1_INTR *(volatile int*)0xf8c20 +#define UART1_RDATA *(volatile byte*)0xf8c24 +#define UART1_STATUS *(volatile int*)0xf8c28 +#define IICD_DELAY *(volatile int*)0xf8d1c +#define IICD_CTRL *(volatile int*)0xf8d20 + +#define USB_CONFIG *(volatile byte*)USB_BASEADDR +#define USB_INT_MASK(x) *(volatile byte*)(USB_BASEADDR + 1 + x) +#define USB_ADDR *(volatile byte*)(USB_BASEADDR + 4) +#define USB_TRG *(volatile byte*)(USB_BASEADDR + 0x10) +#define USB_STALL *(volatile byte*)(USB_BASEADDR + 0x11) +#define USB_CLEAR *(volatile byte*)(USB_BASEADDR + 0x12) +#define USB_EP(x) *(volatile byte*)(USB_BASEADDR + 0x18 + x) +#define USB_EP_LEN(x) *(volatile byte*)(USB_BASEADDR + 0x20 + x) +#define USB_STATUS *(volatile byte*)(USB_BASEADDR + 0x26) +#define USB_FIFO_EMPTY *(volatile byte*)(USB_BASEADDR + 0x27) +#define USB_FIFO_FULL *(volatile byte*)(USB_BASEADDR + 0x28) + + +#define AES_CNTRL_REG *((volatile uint32_t *)(AES_BASEADDR)) +#define AES_DATA_REG0 ((volatile uint32_t *)(AES_BASEADDR+0x10)) +#define AES_DATA_REG1 ((volatile uint32_t *)(AES_BASEADDR+0x14)) +#define AES_DATA_REG2 ((volatile uint32_t *)(AES_BASEADDR+0x18)) +#define AES_DATA_REG3 ((volatile uint32_t *)(AES_BASEADDR+0x1C)) +#define AES_KEY_REG0 ((volatile uint32_t *)(AES_BASEADDR+0x20)) +#define AES_KEY_REG1 ((volatile uint32_t *)(AES_BASEADDR+0x24)) +#define AES_KEY_REG2 ((volatile uint32_t *)(AES_BASEADDR+0x28)) +#define AES_KEY_REG3 ((volatile uint32_t *)(AES_BASEADDR+0x2C)) +#define AES_KEY_REG4 ((volatile uint32_t *)(AES_BASEADDR+0x30)) +#define AES_KEY_REG5 ((volatile uint32_t *)(AES_BASEADDR+0x34)) +#define AES_KEY_REG6 ((volatile uint32_t *)(AES_BASEADDR+0x38)) +#define AES_KEY_REG7 ((volatile uint32_t *)(AES_BASEADDR+0x3C)) +#define AES_RAND_REG0 ((volatile uint32_t *)(AES_BASEADDR+0x40)) +#define AES_RAND_REG1 ((volatile uint32_t *)(AES_BASEADDR+0x44)) +#define AES_FKEY_REG0 ((volatile uint32_t *)(AES_BASEADDR+0x50)) + +#define AES_DATAB(x) *(volatile byte*)(AES_BASEADDR + 0x10 + (x)) +#define AES_KEYB(x) *(volatile byte*)(AES_BASEADDR + 0x20 + (x)) + +#define DESCNTRL_REG *((volatile uint32_t *)(DES_BASEADDR+0x00)) +#define DESRAND_REG ((volatile uint32_t *)(DES_BASEADDR+0x0c)) +#define DESFAKE_KEY ((volatile uint32_t *)(DES_BASEADDR+0x10)) +#define DESIV_REG ((volatile uint32_t *)(DES_BASEADDR+0x18)) +#define DESDATA_REG ((volatile uint32_t *)(DES_BASEADDR+0x20)) +#define DESKEY1_REG ((volatile uint32_t *)(DES_BASEADDR+0x28)) +#define DESKEY2_REG ((volatile uint32_t *)(DES_BASEADDR+0x30)) +#define DESKEY3_REG ((volatile uint32_t *)(DES_BASEADDR+0x38)) +#define DES_KEYB(x) *(volatile byte *)(DES_BASEADDR+0x28 + x) +#define DES_DATAB(x) *(volatile byte *)(DES_BASEADDR+0x20 + x) + +#define SM4_REG0 (*(volatile uint32_t *)(SM4_BASEADDR + 0x0)) +#define SM4_REG1 (*(volatile uint32_t *)(SM4_BASEADDR + 0x4)) +#define SM4_IER (*(volatile uint32_t *)(SM4_BASEADDR + 0x8)) +#define SM4_MR (*(volatile uint32_t *)(SM4_BASEADDR + 0xc)) +#define SM4_KEY0 ((volatile uint32_t *)(SM4_BASEADDR + 0x10)) +#define SM4_KEY1 ((volatile uint32_t *)(SM4_BASEADDR + 0x14)) +#define SM4_KEY2 ((volatile uint32_t *)(SM4_BASEADDR + 0x18)) +#define SM4_KEY3 ((volatile uint32_t *)(SM4_BASEADDR + 0x1c)) +#define SM4_IV0 ((volatile uint32_t *)(SM4_BASEADDR + 0x20)) +#define SM4_IV1 ((volatile uint32_t *)(SM4_BASEADDR + 0x24)) +#define SM4_IV2 ((volatile uint32_t *)(SM4_BASEADDR + 0x28)) +#define SM4_IV3 ((volatile uint32_t *)(SM4_BASEADDR + 0x2c)) +#define SM4_DATA0 ((volatile uint32_t *)(SM4_BASEADDR + 0x30)) +#define SM4_DATA1 ((volatile uint32_t *)(SM4_BASEADDR + 0x34)) +#define SM4_DATA2 ((volatile uint32_t *)(SM4_BASEADDR + 0x38)) +#define SM4_DATA3 ((volatile uint32_t *)(SM4_BASEADDR + 0x3c)) + + +#define RECR (*((volatile uint32_t *)(RSA_BASEADDR+0x00))) +#define RESR (*((volatile uint32_t *)(RSA_BASEADDR+0x04))) +#define REFR (*((volatile uint32_t *)(RSA_BASEADDR+0x08))) +#define RESCR (*((volatile uint32_t *)(RSA_BASEADDR+0x0c))) +#define REDQR (*((volatile uint32_t *)(RSA_BASEADDR+0x10))) +#define REINT (*((volatile uint32_t *)(RSA_BASEADDR+0x14))) +#define RECFR (*((volatile uint32_t *)(RSA_BASEADDR+0x18))) +#define REBKR ((volatile uint32_t *)(RSA_BASEADDR+0x1c)) +#define REDRR (*((volatile uint32_t *)(RSA_BASEADDR+0x24))) +#define REDAR ((volatile uint32_t *)(RSA_BASEADDR+0x100)) +#define REDAR1 ((volatile uint32_t *)(RSA_BASEADDR+0x120)) +#define REDAR2 ((volatile uint32_t *)(RSA_BASEADDR+0x140)) +#define REDAR3 ((volatile uint32_t *)(RSA_BASEADDR+0x160)) +#define REDXR ((volatile uint32_t *)(RSA_BASEADDR+0x200)) +#define REDXR1 ((volatile uint32_t *)(RSA_BASEADDR+0x220)) +#define REDXR2 ((volatile uint32_t *)(RSA_BASEADDR+0x240)) +#define REDXR3 ((volatile uint32_t *)(RSA_BASEADDR+0x260)) +#define REDYR ((volatile uint32_t *)(RSA_BASEADDR+0x280)) +#define REDYR1 ((volatile uint32_t *)(RSA_BASEADDR+0x2a0)) +#define REDYR2 ((volatile uint32_t *)(RSA_BASEADDR+0x2c0)) +#define REDYR3 ((volatile uint32_t *)(RSA_BASEADDR+0x2e0)) +#define REDBR ((volatile uint32_t *)(RSA_BASEADDR+0x300)) +#define REDBR1 ((volatile uint32_t *)(RSA_BASEADDR+0x320)) +#define REDBR2 ((volatile uint32_t *)(RSA_BASEADDR+0x340)) +#define REDBR3 ((volatile uint32_t *)(RSA_BASEADDR+0x360)) +#define REDBRH ((volatile uint32_t *)(RSA_BASEADDR+0x380)) +#define REDCR ((volatile uint32_t *)(RSA_BASEADDR+0x500)) +#define REDCR1 ((volatile uint32_t *)(RSA_BASEADDR+0x520)) +#define REDCR2 ((volatile uint32_t *)(RSA_BASEADDR+0x540)) +#define REDCR3 ((volatile uint32_t *)(RSA_BASEADDR+0x560)) +#define REDCRH ((volatile uint32_t *)(RSA_BASEADDR+0x580)) +#define REDUR ((volatile uint32_t *)(RSA_BASEADDR+0x600)) +#define REDVR ((volatile uint32_t *)(RSA_BASEADDR+0x680)) +#define REDVR2 ((volatile uint32_t *)(RSA_BASEADDR+0x6c0)) +#define REDPR ((volatile uint32_t *)(RSA_BASEADDR+0x700)) +#define REDPR1 ((volatile uint32_t *)(RSA_BASEADDR+0x720)) +#define REDPR2 ((volatile uint32_t *)(RSA_BASEADDR+0x740)) +#define REDPR3 ((volatile uint32_t *)(RSA_BASEADDR+0x760)) +#define REDPRH ((volatile uint32_t *)(RSA_BASEADDR+0x780)) + +#define ISO7811_BASE_ADDR_T1 *((volatile uint32_t *)(ISO7811_BASEADDR+0x00)) +#define ISO7811_BASE_ADDR_T2 *((volatile uint32_t *)(ISO7811_BASEADDR+0x04)) +#define ISO7811_BASE_ADDR_T3 *((volatile uint32_t *)(ISO7811_BASEADDR+0x08)) +#define ISO7811_CTRL *((volatile uint32_t *)(ISO7811_BASEADDR+0x0C)) + +#define ISO7811_T1_PEAK_VALUE_CFG *((volatile uint32_t *)(ISO7811_BASEADDR+0x10)) +#define ISO7811_T1_PEAK_WIDTH_CFG *((volatile uint32_t *)(ISO7811_BASEADDR+0x14)) +#define ISO7811_T1_PULSE_WIDTH_CFG *((volatile uint32_t *)(ISO7811_BASEADDR+0x18)) +#define ISO7811_T1_AGC_CFG *((volatile uint32_t *)(ISO7811_BASEADDR+0x1c)) + +#define ISO7811_T2_PEAK_VALUE_CFG *((volatile uint32_t *)(ISO7811_BASEADDR+0x20)) +#define ISO7811_T2_PEAK_WIDTH_CFG *((volatile uint32_t *)(ISO7811_BASEADDR+0x24)) +#define ISO7811_T2_PULSE_WIDTH_CFG *((volatile uint32_t *)(ISO7811_BASEADDR+0x28)) +#define ISO7811_T2_AGC_CFG *((volatile uint32_t *)(ISO7811_BASEADDR+0x2c)) + +#define ISO7811_T3_PEAK_VALUE_CFG *((volatile uint32_t *)(ISO7811_BASEADDR+0x30)) +#define ISO7811_T3_PEAK_WIDTH_CFG *((volatile uint32_t *)(ISO7811_BASEADDR+0x34)) +#define ISO7811_T3_PULSE_WIDTH_CFG *((volatile uint32_t *)(ISO7811_BASEADDR+0x38)) +#define ISO7811_T3_AGC_CFG *((volatile uint32_t *)(ISO7811_BASEADDR+0x3c)) + +#define ISO7811_STATUS *((volatile uint32_t *)(ISO7811_BASEADDR+0x40)) +#define ISO7811_CHAR_NUM *((volatile uint32_t *)(ISO7811_BASEADDR+0x44)) +#define ISO7811_INTERFER_CHAR_NUM *((volatile uint32_t *)(ISO7811_BASEADDR+0x48)) +#define ISO7811_DC_EST *((volatile uint32_t *)(ISO7811_BASEADDR+0x4c)) +#define ISO7811_INTF_PEAK *((volatile uint32_t *)(ISO7811_BASEADDR+0x50)) +#define ISO7811_AGC_PEAK_VAL *((volatile uint32_t *)(ISO7811_BASEADDR +0x54)) + +#define SYST_CSR *(volatile int*)0xE000E010 +#define SYST_RVR *(volatile int*)0xE000E014 +#define SYST_CVR *(volatile int*)0xE000E018 + +#define TRACE_FIFO *(volatile int*)0xe0002020 +#define NVIC_ISER *(volatile int*)0xe000e100 +#define NVIC_ICER *(volatile int*)0xe000e180 +#define NVIC_ISPR *(volatile int*)0xe000e200 +#define NVIC_ICPR *(volatile int*)0xe000e280 + +#define CRC_RESULT_REG *(volatile uint32_t *)(CRC_BASEADDR+0X04) +#define CRC_MASK_REG *(volatile uint32_t *)(CRC_BASEADDR+0X08) +#define CRC_DATAB_REG *(volatile byte *)(CRC_BASEADDR+0X80) +#define CRC_DATAS_REG *(volatile short int *)(CRC_BASEADDR+0X80) +#define CRC_DATA_REG *(volatile int *)(CRC_BASEADDR+0X80) + +#define ADC_CTRL0 *(volatile uint8_t*)0xC8970 +#define ADC_CTRL1 *(volatile uint8_t*)0xC8971 +#define ADC_CTRL2 *(volatile uint8_t*)0xC8972 +#define ADC_CTRL3 *(volatile uint8_t*)0xC8973 +#define ADC_ENBLE *(volatile uint8_t*)0xC8906 +#define ADC_RDATA *(volatile uint16_t*)0xf850e + +/* SysTick registers */ +/* SysTick control & status */ +#define SYSTICK_CSR ((volatile unsigned int *)0xE000E010) +/* SysTick Reload value */ +#define SYSTICK_RVR ((volatile unsigned int *)0xE000E014) +/* SysTick Current value */ +#define SYSTICK_CVR ((volatile unsigned int *)0xE000E018) +/* SysTick CSR register bits */ +#define SYSTICK_CSR_COUNTFLAG 16 +#define SYSTICK_CSR_CLKSOURCE 2 +#define SYSTICK_CSR_TICKINT 1 +#define SYSTICK_CSR_ENABLE 0 + +//================ bit definitions ==================== +#define OTBIT_DIN 1<<0 +#define OTBIT_DLE 1<<1 +#define OTBIT_CEB 1<<2 +#define OTBIT_RSTB 1<<3 +#define OTBIT_CLE 1<<4 +#define OTBIT_PGMEN 1<<5 +#define OTBIT_PGMVFY 1<<6 +#define OTBIT_READEN 1<<7 +#define OTBIT_VPPEN 1<<8 +#define OTBIT_WEB 1<<9 + +#define AES_CNTRL_REG_START 0x1 + +#define AES_CNTRL_KEY_SEL_128 0X00 +#define AES_CNTRL_KEY_SEL_192 0X08 +#define AES_CNTRL_KEY_SEL_256 0X10 + +#define AES_CNTRL_ENC 0X00 +#define AES_CNTRL_DEC 0X02 + +#define AES_CNTRL_ENABLE_RAND 0X20 + +#define DMACH_QSPI 0 +#define DMACH_SPID0 1 +#define DMACH_SPID1 2 +#define DMACH_UART0 3 +#define DMACH_UART1 4 +#define DMACH_IICD 5 +#define DMACH_MEMCP 6 + +#define DMA_START_BIT 7 +#define DMA_CLR_INTR_BIT 6 +#define DMA_RESET_BIT 5 + +//==DES== +#define DESCNTRL_REG_START 0x1 +#define DESCNTRL_REG_ENCRYPT 0x2 +#define DESCNTRL_REG_KEY_SEL 0xc +#define DESCNTRL_REG_DES_MODE 0x10 +#define DESCNTRL_REG_OP_MODE 0x60 +#define DESCNTRL_REG_RAND_EN 0x80 + +#define DESCNTRL_REG_ENCRYPT_ENC 0X00 +#define DESCNTRL_REG_ENCRYPT_DEC 0X02 + +#define DESCNTRL_REG_KEY_SEL_DES1 0x00 +#define DESCNTRL_REG_KEY_SEL_DES2 0x04 +#define DESCNTRL_REG_KEY_SEL_DES3 0x08 + +#define DESCNTRL_REG_KEY_SEL_TDES2 0x00 +#define DESCNTRL_REG_KEY_SEL_TDES3 0x04 + +#define DESCNTRL_REG_DES_MODE_DES 0X00 +#define DESCNTRL_REG_DES_MODE_TDES 0X10 + +#define DESCNTRL_REG_OP_MODE_ECB 0x00 +#define DESCNTRL_REG_OP_MODE_CBC 0x20 +//==DES==END== + +//==RSA== +//sfr bit +// RECR register +#define RECR_start 0x01 +#define RECR_idle_run 0x02 +#define RECR_bus_crypt_en 0x04 +// RESR register +#define RESR_error_flag 0x01 +#define RESR_opdata_error 0x02 +//REINT register +#define REINT_rsa_int 0x01 +//==RSA==END== + +#define CLKCLS_INT 1 +#define CLKCLS_SHA 2 +#define CLKCLS_CRC 3 +#define CLKCLS_TIM 4 +#define CLKCLS_WDT 5 +#define CLKCLS_USB 6 +#define CLKCLS_SPI 7 +#define CLKCLS_DES 8 +#define CLKCLS_RSA 9 +#define CLKCLS_AES 10 +#define CLKCLS_GPIO 11 +#define CLKCLS_7816 12 +#define CLKCLS_BT 13 +#define CLKCLS_SM4 14 +#define CLKCLS_UART 15 +#define CLKCLS_7811 16 +#define CLKCLS_ADC7811 17 +#define CLKCLS_CP 18 + +#define INTR_USB 0 +#define INTR_IIC 1 +#define INTR_QSPI 2 +#define INTR_SPI0 3 +#define INTR_SPI1 4 +#define INTR_UART0 5 +#define INTR_UART1 6 +#define INTR_MEMCP 7 +#define INTR_RSA 8 +#define INTR_SCI0 9 +#define INTR_SCI1 10 +#define INTR_BT 11 +#define INTR_GPIO 12 +#define INTR_TMR0 13 +#define INTR_TMR1 14 +#define INTR_TMR2 15 +#define INTR_TMR3 16 +#define INTR_TMR4 17 +#define INTR_TMR5 18 +#define INTR_TMR6 19 +#define INTR_TMR7 20 +#define INTR_TMR8 21 +#define INTR_SM4 22 +#define INTR_SEC 23 +#define INTR_ISO7811 24 +#define INTR_TRNG 25 +#define INTR_WDT 26 + +#define SCICFG_TMODE 0 +#define SCICFG_BIT_ORDER 1 +#define SCICFG_PAD_TYPE 2 +#define SCICFG_ETU_SEL 3 +#define SCICFG_RETRY 5 +#define SCICFG_RETRY_EN 8 +#define SCICFG_IO_EN 9 +#define SCICFG_BGTEN 10 +#define SCICFG_CWTEN 11 +#define SCICFG_MCLK_SEL 12 +#define SCICFG_MASTER 15 +#define SCICFG_EDCEN 16 + +#define KCFG_COL 3 +#define KCFG_MDDBC 8 +#define KCFG_MUDBC 12 +#define KCFG_UDBC 16 +#define KCFG_CYLE 20 + +#define SM4_CNTRL_ECB 0X00 +#define SM4_CNTRL_CBC 0X02 +#define SM4_CNTRL_ENC 0X01 +#define SM4_CNTRL_DEC 0X00 + +/* =============== qspi flash command =================== */ +#define W25X_WRITE_ENABLE 0x06 +#define W25X_WRITE_DISABLE 0x04 +#define W25X_READ_STATUS1 0x05 +#define W25X_READ_STATUS2 0x35 +#define W25X_WRITE_STATUS 0x01 +#define W25X_READ_DATA 0x03 +#define W25X_FASTREAD_DATA 0x0B +#define W25X_FASTREAD_DUAL1 0x3B +#define W25X_FASTREAD_DUAL2 0xBB + +#define W25X_FASTREAD_QUAD1 0x6B +#define W25X_FASTREAD_QUAD2 0xEB +#define W25X_FASTREAD_QUAD3 0xE7 + +#define W25X_PAGE_PROGRAM 0x02 +#define W25X_SECTOR_ERASE 0x20 +#define W25X_BLOCK_ERASE32K 0x52 +#define W25X_BLOCK_ERASE64K 0xD8 +#define W25X_CHIP_ERASE 0xC7 +#define W25X_POWER_DOWN 0xB9 +#define W25X_RELEASE_POWERDOWN 0xAB +#define W25X_DEVICEID 0xAB +#define W25X_MANUFACT_DEVICEID 0x90 +#define W25X_JEDEC_DEVICEID 0x9F + +#define QSPICFG_XIPEN 1 << 12 +#define QSPICFG_DECEN 1 << 13 +#define QSPICFG_DUAL_MODE 1 << 0 +#define QSPICFG_QUAD_MODE 2 << 0 +#define QSPICFG_MBYTE 1 << 2 +#define QSPICFG_MBYTE_CONT 1 << 3 +#define QSPICFG_RETRY 3 << 24 + +#define QCSFT_DUMMY 8 +#define QCSFT_CMD 16 + +#define QSPICFG_MODE_3B QSPICFG_DUAL_MODE | W25X_FASTREAD_DUAL1 << QCSFT_CMD | 8 << QCSFT_DUMMY +#define QSPICFG_MODE_6B QSPICFG_QUAD_MODE | W25X_FASTREAD_QUAD1 << QCSFT_CMD | 8 << QCSFT_DUMMY +#define QSPICFG_MODE_BB QSPICFG_DUAL_MODE | QSPICFG_MBYTE | 0x60 | W25X_FASTREAD_DUAL2 << QCSFT_CMD +#define QSPICFG_MODE_EB QSPICFG_QUAD_MODE | QSPICFG_MBYTE | 0x60 | W25X_FASTREAD_QUAD2 << QCSFT_CMD | 4 << QCSFT_DUMMY +#define QSPICFG_MODE_E7 QSPICFG_QUAD_MODE | QSPICFG_MBYTE | 0x60 | W25X_FASTREAD_QUAD3 << QCSFT_CMD | 2 << QCSFT_DUMMY + +#define LPMCFG_BUCK_EN 1 << 25 +#define LPMCFG_TIMER_EN 1 << 28 +#define LPMCFG_KRST_EN 1 << 29 +#define LPMCFG_SENSOR_DUR 1 << 30 + +#define LPMSEN_SENSOR_DLY 5 +#define LPMSEN_SENSOR_LOCK 7 +#define LPMSEN_SHIELD_IO_EN 8 +#define LPMSEN_SHIELD_IO_TYPE 12 +#define LPMSEN_SHIELD_IO_PU 16 +#define LPMSEN_SHIELD_INTERVAL 24 +#define LPMSEN_SHIELD_ENABLE 27 +#define LPMSEN_SHIELD_PU_DLY 28 +#define LPMSEN_SHIELD_A_DLY 30 +#define LPMCFG_SENSOR_LOCK 31 + +//gpio ctrl bit define +#define GPCFG_INPUT 0 +#define GPCFG_QSPI_NCS 2 +#define GPCFG_QSPI_SCK 3 +#define GPCFG_QSPI_IO0 4 +#define GPCFG_QSPI_IO1 5 +#define GPCFG_QSPI_IO2 6 +#define GPCFG_QSPI_IO3 7 +#define GPCFG_UART0_TXD 8 +#define GPCFG_UART0_RXD 9 +#define GPCFG_UART0_RTS 10 +#define GPCFG_UART0_CTS 11 +#define GPCFG_UART1_TXD 12 +#define GPCFG_UART1_RXD 13 +#define GPCFG_UART1_RTS 14 +#define GPCFG_UART1_CTS 15 +#define GPCFG_PWM_OUT0 16 +#define GPCFG_PWM_OUT1 17 +#define GPCFG_PWM_OUT2 18 +#define GPCFG_PWM_OUT3 19 +#define GPCFG_PWM_OUT4 20 +#define GPCFG_PWM_OUT5 21 +#define GPCFG_PWM_OUT6 22 +#define GPCFG_PWM_OUT7 23 +#define GPCFG_SPID0_NCS 24 +#define GPCFG_SPID0_SCK 25 +#define GPCFG_SPID0_MOSI 26 +#define GPCFG_SPID0_SDIO 27 +#define GPCFG_SPID0_MISO 28 +#define GPCFG_SPID0_NCSIN 29 +#define GPCFG_SPID0_SCKIN 30 +#define GPCFG_PWM_OUT8 31 + +#define GPCFG_SPID1_NCS 48 +#define GPCFG_SPID1_SCK 49 +#define GPCFG_SPID1_MOSI 50 +#define GPCFG_SPID1_SDIO 51 +#define GPCFG_SPID1_MISO 52 +#define GPCFG_SPID1_NCSIN 53 +#define GPCFG_SPID1_SCKIN 54 +#define GPCFG_NFC_CLK_OUT 55 +#define GPCFG_SCI7816_IO 56 + +#define GPCFG_ICE 57 +#define GPCFG_IIC_SCL 58 +#define GPCFG_IIC_SDA 59 +#define GPCFG_JTAG_SWCLK 60 +#define GPCFG_JTAG_SWDAT 61 +#define GPCFG_OUTPUT_LOW 62 +#define GPCFG_OUTPUT_HIGH 63 +#define GPCFG_PU 64 +#define GPCFG_PD 128 +#define GPCFG_ANALOG 192 + +#define TIM_CTRL_ENABLE ((uint32_t)0) +#define TIM_CTRL_START_LEVEL ((uint32_t)1) +#define TIM_CTRL_MODE ((uint32_t)2) +#define TIM_CTRL_AUTO_RELOAD ((uint32_t)3) + +/* =============== macros =================== */ +#define PREFETCH_LINE(addr) *(volatile int*)addr = 0 +#define GETWORD(p) ((uint16_t)((*(volatile uint8_t *)((uint32_t)p)) |((((uint16_t)(*(volatile uint8_t *)((uint32_t)(p+1))))<<8) & 0xff00))) +static inline void enable_clock(int id) +{ + SYSCTRL_CLK_CLS &= ~(1 << id); +} +static inline void disable_clock(int id) +{ + SYSCTRL_CLK_CLS |= 1 << id; +} +static inline void enable_intr(int intid) +{ + NVIC_ISER |= 1 << intid; +} +static inline void disable_intr(int intid) +{ + NVIC_ICER = 1 << intid; +} + +extern void delay(int);//delay(x)=delay(x*110+450ns) +extern void invalidate_icache(int addr, int len); + +//#define SCY_FALSE seesim1() + +/*********************************************/ +#define SYSCTRL_PCLK_CON *(volatile int*)0xf7208 +#define SYSCTRL_POWERMODE *(volatile int*)0xf7218 + +//#define debug +#endif /* __YC3121_H__ */ diff --git a/bsp/yichip/yc3121-pos/Libraries/sdk/yc_dma.c b/bsp/yichip/yc3121-pos/Libraries/sdk/yc_dma.c new file mode 100644 index 0000000000..8b7f355076 --- /dev/null +++ b/bsp/yichip/yc3121-pos/Libraries/sdk/yc_dma.c @@ -0,0 +1,72 @@ +/* +File Name : yc_dma.c +Author : Yichip +Version : V1.0 +Date : 2018/03/27 +Description : DMA Mem_TO_Mem Mode encapsulation. + If enable DMA interrupt ,enter interrupt after sending data by default,and just one DMA IT Mode. +*/ + +#include "yc_dma.h" + +#define DMA_Channel DMACH_MEMCP +#define DMA_CLEAR_IT_BIT_Pos 6 +#define DMA_ENTERIT_BIT_Pos 1 +#define DMA_DATA_COMPLETE_BIT_Pos 0 + +void DMA_Init(DMA_InitTypeDef *DMA_InitStruct) +{ + DMA_SRC_ADDR(DMACH_MEMCP) = DMA_InitStruct->DMA_MemorySourceAddr; + DMA_DEST_ADDR(DMACH_MEMCP) = DMA_InitStruct->DMA_MemoryDestAddr; + DMA_LEN(DMACH_MEMCP) = (DMA_InitStruct->DMA_BlockSize << 16) | DMA_InitStruct->DMA_BlockSize; +} + +void DMA_ChannelCmd(FunctionalState NewState) +{ + if (NewState != DISABLE) + { + DMA_START(DMACH_MEMCP) |= (DMA_ENABLE); + } + else + { + DMA_START(DMACH_MEMCP) &= ~(DMA_ENABLE); + } +} + +void DMA_SetSRCAddress(uint32_t Address) +{ + DMA_SRC_ADDR(DMACH_MEMCP) = Address; +} + +void DMA_SetDSRAddress(uint32_t Address) +{ + DMA_DEST_ADDR(DMACH_MEMCP) = Address; +} + +FunctionalState DMA_IsChannelEnabled(void) +{ + if (1 == (DMA_START(DMACH_MEMCP) & DMA_ENABLE)) + { + return ENABLE; + } + else + { + return DISABLE; + } +} + +FlagStatus DMA_GetFlagStatus(void) +{ + return (FlagStatus)((DMA_STATUS(DMACH_MEMCP) & (1 << DMA_DATA_COMPLETE_BIT_Pos))); +} + +void DMA_ClearITPendingBit(void) +{ + DMA_START(DMACH_MEMCP) |= (1 << DMA_CLEAR_IT_BIT_Pos); +} + +void DMA_ITConfig(FunctionalState NewState) +{ + DMA_CONFIG(DMACH_MEMCP) &= ~(1 << DMA_ENTERIT_BIT_Pos); + DMA_CONFIG(DMACH_MEMCP) |= (NewState << DMA_ENTERIT_BIT_Pos); +} diff --git a/bsp/yichip/yc3121-pos/Libraries/sdk/yc_dma.h b/bsp/yichip/yc3121-pos/Libraries/sdk/yc_dma.h new file mode 100644 index 0000000000..deac52a157 --- /dev/null +++ b/bsp/yichip/yc3121-pos/Libraries/sdk/yc_dma.h @@ -0,0 +1,91 @@ +/* +File Name : yc_dma.h +Author : Yichip +Version : V1.0 +Date : 2018/03/27 +Description : DMA Mem_TO_Mem Mode encapsulation. + If enable DMA interrupt ,enter interrupt after sending data by default,and just one DMA IT Mode. +*/ + +#ifndef __YC_DMA_H_ +#define __YC_DMA_H_ + +#include "yc3121.h" +#define DMACH_QSPI 0 + +#define DMA_ENABLE_BIT_Pos 7 +#define DMA_ENABLE ((uint8_t)1 << DMA_ENABLE_BIT_Pos) + +#define DMA_IT_BIT_Pos 1 +#define DMA_IT_ENABLE ((uint32_t)1 << DMA_IT_BIT_Pos) +/*Peripheral DMA Channel*/ + +typedef struct +{ + uint32_t DMA_MemorySourceAddr; /*!< Specifies the memory Source address for Channel Mem_to_Mem. */ + + uint32_t DMA_MemoryDestAddr; /*!GPIO_Pin)); + _ASSERT(IS_GPIO_MODE(GPIO_InitStruct->GPIO_Mode)); + + int i; + + switch (GPIO_InitStruct->GPIO_Mode) + { + case GPIO_Mode_IN_FLOATING: + for (i = 0; i < GPIO_PIN_NUM; i++) + { + if (GPIO_InitStruct->GPIO_Pin & 1 << i) + GPIO_CONFIG(GPIOx * GPIO_PIN_NUM + i) = 0x00; + } + break; + + case GPIO_Mode_IPU: + for (i = 0; i < GPIO_PIN_NUM; i++) + { + if (GPIO_InitStruct->GPIO_Pin & 1 << i) + GPIO_CONFIG(GPIOx * GPIO_PIN_NUM + i) = 0x40; + } + break; + + case GPIO_Mode_IPD: + for (i = 0; i < GPIO_PIN_NUM; i++) + { + if (GPIO_InitStruct->GPIO_Pin & 1 << i) + GPIO_CONFIG(GPIOx * GPIO_PIN_NUM + i) = 0x80; + } + break; + + case GPIO_Mode_AIN: + for (i = 0; i < GPIO_PIN_NUM; i++) + { + if (GPIO_InitStruct->GPIO_Pin & 1 << i) + GPIO_CONFIG(GPIOx * GPIO_PIN_NUM + i) = 0xC0; + } + break; + + case GPIO_Mode_Out_PP: + for (i = 0; i < GPIO_PIN_NUM; i++) + { + if (GPIO_InitStruct->GPIO_Pin & 1 << i) + GPIO_CONFIG(GPIOx * GPIO_PIN_NUM + i) = 0x3E; + } + break; + + default: + break; + } +} + +void GPIO_PullUpCmd(GPIO_TypeDef GPIOx, uint16_t GPIO_Pin, FunctionalState NewState) +{ + _ASSERT(ISGPIOGROUP(GPIOx)); + _ASSERT(IS_GET_GPIO_PIN(GPIO_Pin)); + + int i; + + for (i = 0; i < GPIO_PIN_NUM; i++) + { + if (GPIO_Pin & 1 << i) + { + if (NewState == ENABLE) + { + GPIO_CONFIG(GPIOx * GPIO_PIN_NUM + i) |= 1 << 6; + } + else if (NewState == DISABLE) + { + GPIO_CONFIG(GPIOx * GPIO_PIN_NUM + i) &= ~(1 << 6); + } + } + } +} + +uint16_t GPIO_ReadInputData(GPIO_TypeDef GPIOx) +{ + _ASSERT(ISGPIOGROUP(GPIOx)); + + return GPIO_IN(GPIOx); +} + +uint8_t GPIO_ReadInputDataBit(GPIO_TypeDef GPIOx, uint16_t GPIO_Pin) +{ + _ASSERT(ISGPIOGROUP(GPIOx)); + _ASSERT(IS_GET_GPIO_PIN(GPIO_Pin)); + + if (GPIO_IN(GPIOx) & GPIO_Pin) + { + return (uint8_t)0x01; + } + else + { + return (uint8_t)0x00; + } +} + +uint16_t GPIO_ReadOutputData(GPIO_TypeDef GPIOx) +{ + _ASSERT(ISGPIOGROUP(GPIOx)); + + return GPIO_IN(GPIOx); +} + +uint8_t GPIO_ReadOutputDataBit(GPIO_TypeDef GPIOx, uint16_t GPIO_Pin) +{ + _ASSERT(ISGPIOGROUP(GPIOx)); + _ASSERT(IS_GET_GPIO_PIN(GPIO_Pin)); + + if (GPIO_IN(GPIOx) & GPIO_Pin) + { + return (uint8_t)0x01; + } + else + { + return (uint8_t)0x00; + } +} + +void GPIO_ResetBits(GPIO_TypeDef GPIOx, uint16_t GPIO_Pin) +{ + _ASSERT(ISGPIOGROUP(GPIOx)); + _ASSERT(IS_GET_GPIO_PIN(GPIO_Pin)); + + int i; + uint8_t Temp; + + for (i = 0; i < GPIO_PIN_NUM; i++) + { + if (GPIO_Pin & 1 << i) + { + Temp = GPIO_CONFIG(GPIOx * GPIO_PIN_NUM + i); + Temp |= 0x3F; //00111111 + Temp &= 0xFE; //11111110 + GPIO_CONFIG(GPIOx * GPIO_PIN_NUM + i) = Temp; + } + } +} + +void GPIO_SetBits(GPIO_TypeDef GPIOx, uint16_t GPIO_Pin) +{ + _ASSERT(ISGPIOGROUP(GPIOx)); + _ASSERT(IS_GET_GPIO_PIN(GPIO_Pin)); + + int i; + + for (i = 0; i < GPIO_PIN_NUM; i++) + { + if (GPIO_Pin & 1 << i) + GPIO_CONFIG(GPIOx * GPIO_PIN_NUM + i) |= 0x3F; //00111111 + } +} + +void GPIO_StructInit(GPIO_InitTypeDef *GPIO_InitStruct) +{ + GPIO_InitStruct->GPIO_Pin = GPIO_Pin_All; + GPIO_InitStruct->GPIO_Mode = GPIO_Mode_IN_FLOATING; +} + +void GPIO_Write(GPIO_TypeDef GPIOx, uint16_t value) +{ + _ASSERT(ISGPIOGROUP(GPIOx)); + + int i; + + for (i = 0; i < GPIO_PIN_NUM; i++) + { + if (BIT_GET(value, i)) + GPIO_SetBits(GPIOx, 1 << i); + else + GPIO_ResetBits(GPIOx, 1 << i); + } +} + +void GPIO_WriteBit(GPIO_TypeDef GPIOx, uint16_t GPIO_Pin, BitAction BitVal) +{ + _ASSERT(ISGPIOGROUP(GPIOx)); + _ASSERT(IS_GET_GPIO_PIN(GPIO_Pin)); + + if (BitVal == Bit_SET) + GPIO_SetBits(GPIOx, GPIO_Pin); + else if (BitVal == Bit_RESET) + GPIO_ResetBits(GPIOx, GPIO_Pin); +} diff --git a/bsp/yichip/yc3121-pos/Libraries/sdk/yc_gpio.h b/bsp/yichip/yc3121-pos/Libraries/sdk/yc_gpio.h new file mode 100644 index 0000000000..92f6ff9723 --- /dev/null +++ b/bsp/yichip/yc3121-pos/Libraries/sdk/yc_gpio.h @@ -0,0 +1,299 @@ +/* +File Name : yc_gpio.c +Author : Yichip +Version : V1.0 +Date : 2019/12/03 +Description : gpio encapsulation. +*/ + +#ifndef __YC_GPIO_H__ +#define __YC_GPIO_H__ + +#include "yc3121.h" + +/** + * @brief Configuration Mode enumeration + */ +typedef enum +{ + GPIO_Mode_IN_FLOATING = 0x01, + GPIO_Mode_IPU = 0x02, + GPIO_Mode_IPD = 0x03, + GPIO_Mode_AIN = 0x04, + GPIO_Mode_Out_PP = 0x05 /*!< analog signal mode */ +} GPIO_ModeTypeDef; + +#define IS_GPIO_MODE(mode) (((mode) == GPIO_Mode_IN_FLOATING) || \ + ((mode) == GPIO_Mode_IPU) || \ + ((mode) == GPIO_Mode_IPD) || \ + ((mode) == GPIO_Mode_Out_PP) || \ + ((mode) == GPIO_Mode_AIN)) + +/** + * @brief Bit_SET and Bit_RESET enumeration + */ +typedef enum +{ + Bit_RESET = 0, + Bit_SET +} BitAction; + +/** + * @brief gpio output enumeration + */ +typedef enum +{ + OutputLow = 0, + OutputHigh = 1 +} GPIO_OutputTypeDef; + +#define IS_GPIO_WAKE_MODE(MODE) (((MODE) == GPIO_WakeMode_Now) || \ + ((MODE) == GPIO_WakeMode_AfterGlitch)) + +/** + * @brief GPIO function enumeration + */ +typedef enum +{ + INPUT = GPCFG_INPUT, + QSPI_NCS = GPCFG_QSPI_NCS, + QSPI_SCK = GPCFG_QSPI_SCK, + QSPI_IO0 = GPCFG_QSPI_IO0, + QSPI_IO1 = GPCFG_QSPI_IO1, + QSPI_IO2 = GPCFG_QSPI_IO2, + QSPI_IO3 = GPCFG_QSPI_IO3, + UART0_TXD = GPCFG_UART0_TXD, + UART0_RXD = GPCFG_UART0_RXD, + UART0_RTS = GPCFG_UART0_RTS, + UART0_CTS = GPCFG_UART0_CTS, + UART1_TXD = GPCFG_UART1_TXD, + UART1_RXD = GPCFG_UART1_RXD, + UART1_RTS = GPCFG_UART1_RTS, + UART1_CTS = GPCFG_UART1_CTS, + PWM_OUT0 = GPCFG_PWM_OUT0, + PWM_OUT1 = GPCFG_PWM_OUT1, + PWM_OUT2 = GPCFG_PWM_OUT2, + PWM_OUT3 = GPCFG_PWM_OUT3, + PWM_OUT4 = GPCFG_PWM_OUT4, + PWM_OUT5 = GPCFG_PWM_OUT5, + PWM_OUT6 = GPCFG_PWM_OUT6, + PWM_OUT7 = GPCFG_PWM_OUT7, + PWM_OUT8 = GPCFG_PWM_OUT8, + SPID0_NCS = GPCFG_SPID0_NCS, + SPID0_SCK = GPCFG_SPID0_SCK, + SPID0_MOSI = GPCFG_SPID0_MOSI, + SPID0_SDIO = GPCFG_SPID0_SDIO, + SPID0_MISO = GPCFG_SPID0_MISO, + SPID0_NCSIN = GPCFG_SPID0_NCSIN, + SPID0_SCKIN = GPCFG_SPID0_SCKIN, + SPID1_NCS = GPCFG_SPID1_NCS, + SPID1_SCK = GPCFG_SPID1_SCK, + SPID1_MOSI = GPCFG_SPID1_MOSI, + SPID1_SDIO = GPCFG_SPID1_SDIO, + SPID1_MISO = GPCFG_SPID1_MISO, + SPID1_NCSIN = GPCFG_SPID1_NCSIN, + SPID1_SCKIN = GPCFG_SPID1_SCKIN, + NFC_CLK_OUT = GPCFG_NFC_CLK_OUT, + SCI7816_IO = GPCFG_SCI7816_IO, + IIC_SCL = GPCFG_IIC_SCL, + IIC_SDA = GPCFG_IIC_SDA, + JTAG_SWCLK = GPCFG_JTAG_SWCLK, + JTAG_SWDAT = GPCFG_JTAG_SWDAT, + OUTPUT_LOW = GPCFG_OUTPUT_LOW, + OUTPUT_HIGH = GPCFG_OUTPUT_HIGH, + PULL_UP = GPCFG_PU, + PULL_DOWN = GPCFG_PD, + ANALOG = GPCFG_ANALOG +} GPIO_FunTypeDef; + +#define GPIO_Pin_0 ((uint16_t)0x0001) /*!< Pin 0 selected */ +#define GPIO_Pin_1 ((uint16_t)0x0002) /*!< Pin 1 selected */ +#define GPIO_Pin_2 ((uint16_t)0x0004) /*!< Pin 2 selected */ +#define GPIO_Pin_3 ((uint16_t)0x0008) /*!< Pin 3 selected */ +#define GPIO_Pin_4 ((uint16_t)0x0010) /*!< Pin 4 selected */ +#define GPIO_Pin_5 ((uint16_t)0x0020) /*!< Pin 5 selected */ +#define GPIO_Pin_6 ((uint16_t)0x0040) /*!< Pin 6 selected */ +#define GPIO_Pin_7 ((uint16_t)0x0080) /*!< Pin 7 selected */ +#define GPIO_Pin_8 ((uint16_t)0x0100) /*!< Pin 8 selected */ +#define GPIO_Pin_9 ((uint16_t)0x0200) /*!< Pin 9 selected */ +#define GPIO_Pin_10 ((uint16_t)0x0400) /*!< Pin 10 selected */ +#define GPIO_Pin_11 ((uint16_t)0x0800) /*!< Pin 11 selected */ +#define GPIO_Pin_12 ((uint16_t)0x1000) /*!< Pin 12 selected */ +#define GPIO_Pin_13 ((uint16_t)0x2000) /*!< Pin 13 selected */ +#define GPIO_Pin_14 ((uint16_t)0x4000) /*!< Pin 14 selected */ +#define GPIO_Pin_15 ((uint16_t)0x8000) /*!< Pin 15 selected */ +#define GPIO_Pin_All ((uint16_t)0xffff) /*!< Pin All selected */ + +#define IS_GPIO_PIN(PIN) (((((PIN) & ~(uint16_t)0xFFFF)) == 0x00) && ((PIN) != (uint16_t)0x00)) + +#define IS_GET_GPIO_PIN(PIN) (((PIN) == GPIO_Pin_0) || \ + ((PIN) == GPIO_Pin_1) || \ + ((PIN) == GPIO_Pin_2) || \ + ((PIN) == GPIO_Pin_3) || \ + ((PIN) == GPIO_Pin_4) || \ + ((PIN) == GPIO_Pin_5) || \ + ((PIN) == GPIO_Pin_6) || \ + ((PIN) == GPIO_Pin_7) || \ + ((PIN) == GPIO_Pin_8) || \ + ((PIN) == GPIO_Pin_9) || \ + ((PIN) == GPIO_Pin_10) || \ + ((PIN) == GPIO_Pin_11) || \ + ((PIN) == GPIO_Pin_12) || \ + ((PIN) == GPIO_Pin_13) || \ + ((PIN) == GPIO_Pin_14) || \ + ((PIN) == GPIO_Pin_15)) + +/** + * @brief GPIO group enumeration + */ +typedef enum +{ + GPIOA = 0, + GPIOB, + GPIOC +} GPIO_TypeDef; + +#define ISGPIOGROUP(groupx) (groupx < GPIO_GROUP_NUM) + +/** + * @brief GPIO Init structure definition + */ +typedef struct +{ + uint16_t GPIO_Pin; + GPIO_ModeTypeDef GPIO_Mode; +} GPIO_InitTypeDef; + +/** + * @brief config gpio function(Only one can be configured at a time) + * + * @param GPIOx: where x can be (GPIOA...GPIOF) to select the GPIO group. + * + * @param GPIO_Pin: select the pin to read.(GPIO_Pin_0...GPIO_Pin_15)(Only one can be configured at a time) + * + * @param function:gpio function + * + * @retval none + */ +void GPIO_Config(GPIO_TypeDef GPIOx, uint16_t GPIO_Pin, GPIO_FunTypeDef function); + +/** + * @brief gpio mode Init + * + * @param GPIOx: where x can be (GPIOA...GPIOF) to select the GPIO group. + * + * @param GPIO_InitStruct:GPIO_InitStruct + * + * @retval none + */ +void GPIO_Init(GPIO_TypeDef GPIOx, GPIO_InitTypeDef *GPIO_InitStruct); + +/** + * @brief + * + * @param GPIOx: where x can be (GPIOA...GPIOF) to select the GPIO group. + * + * @param GPIO_Pin: select the pin to read.(GPIO_Pin_0...GPIO_Pin_7) + * + * @param NewState: new state of the port pin Pull Up.(ENABLE or DISABLE) + * + * @retval + */ +void GPIO_PullUpCmd(GPIO_TypeDef GPIOx, uint16_t GPIO_Pin, FunctionalState NewState); + +/** + * @brief Reads the GPIO input data(status) for byte. + * + * @param GPIOx: where x can be (GPIOA...GPIOF) to select the GPIO group. + * + * @retval GPIO input data(status). + */ +uint16_t GPIO_ReadInputData(GPIO_TypeDef GPIOx); + +/** + * @brief Reads the GPIO input data(status) for bit. + * + * @param GPIOx: where x can be (GPIOA...GPIOF) to select the GPIO group. + * + * @param GPIO_Pin: select the pin to read.(GPIO_Pin_0...GPIO_Pin_15) + * + * @retval The input status + */ +uint8_t GPIO_ReadInputDataBit(GPIO_TypeDef GPIOx, uint16_t GPIO_Pin); + +/** + * @brief Reads the GPIO output data(status) for byte. + * + * @param GPIOx: where x can be (GPIOA...GPIOF) to select the GPIO group. + * + * @retval GPIO output data(status). + */ +uint16_t GPIO_ReadOutputData(GPIO_TypeDef GPIOx); + +/** + * @brief Reads the GPIO output data(status) for bit. + * + * @param GPIOx: where x can be (GPIOA...GPIOF) to select the GPIO group. + * + * @param GPIO_Pin: select the pin to read.(GPIO_Pin_0...GPIO_Pin_15) + * + * @retval The output status + */ +uint8_t GPIO_ReadOutputDataBit(GPIO_TypeDef GPIOx, uint16_t GPIO_Pin); + +/** + * @brief Clears the selected pin(only output mode) + * + * @param GPIOx: where x can be (GPIOA...GPIOF) to select the GPIO group. + * + * @param GPIO_Pin: select the pin to read.(GPIO_Pin_0...GPIO_Pin_15) + * + * @retval None + */ +void GPIO_ResetBits(GPIO_TypeDef GPIOx, uint16_t GPIO_Pin); + +/** + * @brief sets the selected pin(only output mode) + * + * @param GPIOx: where x can be (GPIOA...GPIOF) to select the GPIO group. + * + * @param GPIO_Pin: select the pin to read.(GPIO_Pin_0...GPIO_Pin_15) + * + * @retval None + */ +void GPIO_SetBits(GPIO_TypeDef GPIOx, uint16_t GPIO_Pin); + +/** + * @brief init GPIO_InitStruct to default value. + * @param GPIO_InitStruct : pointer to a GPIO_InitTypeDef structure which will be initialized. + * @retval None + */ +void GPIO_StructInit(GPIO_InitTypeDef *GPIO_InitStruct); + +/** + * @brief Writes data to the GPIO group port(only output mode) + * + * @param GPIOx: where x can be (GPIOA...GPIOF) to select the GPIO group. + * + * @param value: specifies the value to be written to the port output data register. + * + * @retval None + */ +void GPIO_Write(GPIO_TypeDef GPIOx, uint16_t value); + +/** + * @brief Sets or clears the selected data port bit(only output mode) + * + * @param GPIOx: where x can be (GPIOA...GPIOF) to select the GPIO group. + * + * @param GPIO_Pin: select the pin to read.(GPIO_Pin_0...GPIO_Pin_7) + * + * @param BitVal: specifies the value to be written to the selected bit. + * This parameter can be one of the BitAction enum values: + * @arg Bit_RESET: to clear the port pin + * @arg Bit_SET: to set the port pin + * @retval None + */ +void GPIO_WriteBit(GPIO_TypeDef GPIOx, uint16_t GPIO_Pin, BitAction BitVal); + +#endif /* __YC_GPIO_H__ */ diff --git a/bsp/yichip/yc3121-pos/Libraries/sdk/yc_systick.c b/bsp/yichip/yc3121-pos/Libraries/sdk/yc_systick.c new file mode 100644 index 0000000000..17172b7432 --- /dev/null +++ b/bsp/yichip/yc3121-pos/Libraries/sdk/yc_systick.c @@ -0,0 +1,72 @@ +/* +File Name : yc_systick.c +Author : Yichip +Version : V1.0 +Date : 2018/03/27 +Description : systick encapsulation. +*/ + +#include "yc_systick.h" + +tick SystickCount; + +void Systick_Dealy_Ms(uint32_t MS) +{ + uint32_t ReloadValue; + + ReloadValue = MS * 9600; + + *SYSTICK_CSR &= ~(((uint32_t)1) << SYSTICK_CSR_ENABLE); + *SYSTICK_RVR = ReloadValue; //Set the reload value + *SYSTICK_CVR = 0; //clear the current value + *SYSTICK_CSR |= ((SYSTICK_SYSCLOCK << SYSTICK_CSR_CLKSOURCE) | (1 << SYSTICK_CSR_ENABLE)); + + while (!(*SYSTICK_CVR == 0)); + *SYSTICK_RVR = 0; +} + +uint32_t SysTick_Config(uint32_t ReloadValue) +{ + ReloadValue -= 1; + if (!IS_RELOAD_VALUE(ReloadValue)) + return 1; + + *SYSTICK_CSR &= ~(((uint32_t)1) << SYSTICK_CSR_ENABLE); + + *SYSTICK_RVR = ReloadValue; //Set the reload value + *SYSTICK_CVR = 0; //clear the current value + SystickCount = 0; // Reset the overflow counter + *SYSTICK_CSR |= + ((SYSTICK_SYSCLOCK << SYSTICK_CSR_CLKSOURCE) | + (1 << SYSTICK_CSR_ENABLE) | + (1 << SYSTICK_CSR_TICKINT)); + return 0; +} + +tick SysTick_GetTick() +{ + return SystickCount; +} + +Boolean SysTick_IsTimeOut(tick start_tick, int interval) +{ + start_tick = SysTick_GetTick() - start_tick; + if (start_tick < 0) + start_tick += TICK_MAX_VALUE; + if (((start_tick * (*SYSTICK_RVR)) / (CPU_MHZ / 1000)) >= interval) + { + return TRUE; + } + else + { + return FALSE; + } +} + +uint32_t SysTick_GetRelativeTime(tick start_tick) +{ + start_tick = SysTick_GetTick() - start_tick; + if (start_tick < 0) + start_tick += TICK_MAX_VALUE; + return ((start_tick * (*SYSTICK_RVR)) / (CPU_MHZ / 1000)); +} diff --git a/bsp/yichip/yc3121-pos/Libraries/sdk/yc_systick.h b/bsp/yichip/yc3121-pos/Libraries/sdk/yc_systick.h new file mode 100644 index 0000000000..874056c2e3 --- /dev/null +++ b/bsp/yichip/yc3121-pos/Libraries/sdk/yc_systick.h @@ -0,0 +1,64 @@ +/* +File Name : yc_systick.h +Author : Yichip +Version : V1.0 +Date : 2018/03/27 +Description : systick encapsulation. +*/ + +#ifndef __YC_SYSTICK_H__ +#define __YC_SYSTICK_H__ +#include "..\core\yc3121.h" + +#define SYSTICK_SYSCLOCK 1 +#define SYSTICK_HALF_SYSCLOCK 0 + +#define IS_RELOAD_VALUE(x) (x>0&&x<=0xffffff) + +typedef int32_t tick; +#define TICK_MAX_VALUE (int32_t)0x7FFFFFFF + + +void Systick_Dealy_Ms(uint32_t MS); + +/** + * @brief Initialize systick and start systick + * + * @param ReloadValue : the systick reload value + * + * @retval 0:succeed 1:error + */ +uint32_t SysTick_Config(uint32_t ReloadValue); + + +/** + * @brief get the current value of SystickCount(SystickCount plus one for every overflow interrupt) + * + * @param none + * + * @retval current value of SystickCount + */ +tick SysTick_GetTick(void); + +/** + * @brief Determine whether the timeout that millisecond. + * + * @param start_tick:start tick + * + * @param interval:time interval(ms) + * + * @retval TRUE is timeout ,FALSE is not timeout + */ +Boolean SysTick_IsTimeOut(tick start_tick,int interval); + + +/** + * @brief get relative time . + * + * @param start_tick:start tick(start time) + * + * @retval the relative time(millisecond) + */ +uint32_t SysTick_GetRelativeTime(tick start_tick); + +#endif /* __YC_SYSTICK_H__ */ diff --git a/bsp/yichip/yc3121-pos/Libraries/sdk/yc_uart.c b/bsp/yichip/yc3121-pos/Libraries/sdk/yc_uart.c new file mode 100644 index 0000000000..1c26605e9a --- /dev/null +++ b/bsp/yichip/yc3121-pos/Libraries/sdk/yc_uart.c @@ -0,0 +1,429 @@ +/* +File Name : yc_uart.c +Author : Yichip +Version : V1.0 +Date : 2019/12/4 +Description : UART encapsulation. +*/ +#include "yc_uart.h" + +#define uart_DMA_buf_len 1024 +uint8_t uart0_DMA_buf[uart_DMA_buf_len] = {0}; +uint8_t uart1_DMA_buf[uart_DMA_buf_len] = {0}; + +#define RX_ENABLE_BIT 0 +#define RX_ENABLE (1 << RX_ENABLE_BIT) + +#define UART_DMA_ENABLE_BIT 31 +#define UART_DMA_ENABLE (1 << UART_DMA_ENABLE_BIT) + +#define TX_INTR_ENABLE_BIT 31 +#define TX_INTR_ENABLE ((uint32_t)1 << TX_INTR_ENABLE_BIT) + +#define Set_RxITNum_Mask 0xff00 +#define Statu_RxNum_Mask (uint32_t)0xffff0000 + +void UART_AutoFlowCtrlCmd(UART_TypeDef UARTx, FunctionalState NewState) +{ + _ASSERT(IS_UART(UARTx)); + + if (NewState == ENABLE) + { + switch (UARTx) + { + case UART0: + UART0_CTRL |= FlowCtrl_Enable; + break; + case UART1: + UART1_CTRL |= FlowCtrl_Enable; + break; + } + } + else + { + switch (UARTx) + { + case UART0: + UART0_CTRL &= (~FlowCtrl_Enable); + break; + case UART1: + UART1_CTRL &= (~FlowCtrl_Enable); + break; + } + } + return; +} + +void UART_ClearIT(UART_TypeDef UARTx) +{ + uint8_t ITType = UART_GetITIdentity(UARTx); + UART_ITConfig(UARTx, ITType, DISABLE); +} + +void UART_DeInit(UART_TypeDef UARTx) +{ + _ASSERT(IS_UART(UARTx)); + + switch (UARTx) + { + case UART0: + UART0_CTRL = 0; + break; + case UART1: + UART1_CTRL = 0; + break; + } +} + +void UART_DMASendBuf(UART_TypeDef UARTx, uint8_t *buf, int len) +{ + _ASSERT(IS_UART(UARTx)); + _ASSERT(NULL != buf); + _ASSERT((len < 0xffff)); + + if (UARTx == UART0) + { + DMA_SRC_ADDR(DMACH_UART0) = (int)buf; + DMA_LEN(DMACH_UART0) = (DMA_LEN(DMACH_UART0) & 0xffff) | len << 16; + DMA_START(DMACH_UART0) = (1 << DMA_START_BIT); + } + else + { + DMA_SRC_ADDR(DMACH_UART1) = (int)buf; + DMA_LEN(DMACH_UART1) = (DMA_LEN(DMACH_UART1) & 0xffff) | len << 16; + DMA_START(DMACH_UART1) = (1 << DMA_START_BIT); + } +} + +uint8_t UART_GetITIdentity(UART_TypeDef UARTx) +{ + uint8_t IT_Mode = 0; + switch (UARTx) + { + case UART0: + { + if (((UART0_CTRL & Set_RxITNum_Mask) > 0) && ((UART0_STATUS >> 16) > 0)) + { + IT_Mode = UART_IT_RX; + } + else + { + if ((UART0_CTRL & (uint32_t)TX_INTR_ENABLE)) + { + IT_Mode = UART_IT_TX; + } + else + { + IT_Mode = FALSE; + } + } + } + break; + + case UART1: + { + if (((UART1_CTRL & Set_RxITNum_Mask) > 0) && ((UART1_STATUS >> 16) > 0)) + { + IT_Mode = UART_IT_RX; + } + else + { + if (UART1_CTRL & TX_INTR_ENABLE) + { + IT_Mode = UART_IT_TX; + } + else + { + IT_Mode = FALSE; + } + } + } + break; + } + return IT_Mode; +} + +void UART_Init(UART_TypeDef UARTx, UART_InitTypeDef *UART_InitStruct) +{ +#define RESET_BAUD (1 << 7) +#define AUTO_BAUD (0 << 7) + uint32_t reg_value = 0; + uint32_t temp_baudrate = 0; + + _ASSERT(IS_UART(UARTx)); + _ASSERT(IS_MODE(UART_InitStruct->Mode)); + _ASSERT(IS_BAUDRATE(UART_InitStruct->BaudRate)); + _ASSERT(IS_PARITY(UART_InitStruct->Parity)); + _ASSERT(IS_FlowCtrl(UART_InitStruct->FlowCtrl)); + _ASSERT(IS_USART_STOPBITS(UART_InitStruct->StopBits)); + + temp_baudrate = ((48000000 / UART_InitStruct->BaudRate) << 16); + + reg_value = RX_ENABLE | + UART_InitStruct->Parity | + UART_InitStruct->DataBits | + UART_InitStruct->StopBits | + UART_InitStruct->FlowCtrl | + UART_InitStruct->Mode | + RESET_BAUD | + temp_baudrate; + + if (UARTx == UART0) + { + UART0_CTRL = 0; + DMA_DEST_ADDR(DMACH_UART0) = (int)uart0_DMA_buf; + DMA_LEN(DMACH_UART0) = uart_DMA_buf_len; + DMA_CONFIG(DMACH_UART0) = 1; + DMA_START(DMACH_UART0) |= (1 << (DMA_RESET_BIT)); + DMA_START(DMACH_UART0) &= ~(1 << (DMA_RESET_BIT)); + UART0_CTRL = 0; + UART0_CTRL = reg_value; + } + else + { + UART1_CTRL = 0; + DMA_DEST_ADDR(DMACH_UART1) = (int)uart1_DMA_buf; + DMA_LEN(DMACH_UART1) = uart_DMA_buf_len; + DMA_CONFIG(DMACH_UART1) = 1; + DMA_START(DMACH_UART1) |= (1 << (DMA_RESET_BIT)); + DMA_START(DMACH_UART1) &= ~(1 << (DMA_RESET_BIT)); + UART1_CTRL = 0; + UART1_CTRL = reg_value; + } + return; +} + +Boolean UART_IsRXFIFOFull(UART_TypeDef UARTx) +{ +#define BITRXFULL 1 + _ASSERT(IS_UART(UARTx)); + + if (UART0 == UARTx) + { + return (Boolean)(UART0_STATUS & (1 << BITRXFULL)); + } + else + { + return (Boolean)(UART1_STATUS & (1 << BITRXFULL)); + } +} + +Boolean UART_IsRXFIFONotEmpty(UART_TypeDef UARTx) +{ +#define BITRXEMPTY 0 + _ASSERT(IS_UART(UARTx)); + + if (UART0 == UARTx) + { + return (Boolean)((UART0_STATUS >> 16) ? 1 : 0); + } + else + { + return (Boolean)((UART1_STATUS >> 16) ? 1 : 0); + } +} + +Boolean UART_IsUARTBusy(UART_TypeDef UARTx) +{ + _ASSERT(IS_UART(UARTx)); + + if (UART0 == UARTx) + { + return (Boolean)(!(DMA_STATUS(DMACH_UART0) & 1)); + } + else + { + return (Boolean)(!(DMA_STATUS(DMACH_UART1) & 1)); + } +} + +void UART_ITConfig(UART_TypeDef UARTx, uint32_t UART_IT, FunctionalState NewState) +{ + _ASSERT(IS_UART(UARTx)); + _ASSERT(IS_UART_IT(UART_IT)); + + switch (UARTx) + { + case UART0: + { + if (UART_IT == UART_IT_RX) + { + if (NewState) + { + UART0_CTRL |= ((ENABLE << 8)); + } + else + { + UART0_CTRL &= ~Set_RxITNum_Mask; + } + } + else if (UART_IT == UART_IT_TX) + { + UART0_CTRL &= (~TX_INTR_ENABLE); + UART0_CTRL |= (NewState << TX_INTR_ENABLE_BIT); + } + } + break; + + case UART1: + { + if (UART_IT == UART_IT_RX) + { + if (NewState) + { + UART1_CTRL |= ((ENABLE << 8)); + } + else + { + UART1_CTRL &= ~Set_RxITNum_Mask; + } + } + else if (UART_IT == UART_IT_TX) + { + UART1_CTRL &= (uint32_t)~TX_INTR_ENABLE; + UART1_CTRL |= (NewState << TX_INTR_ENABLE_BIT); + } + } + break; + } +} + +uint8_t UART_ReceiveData(UART_TypeDef UARTx) +{ + _ASSERT(IS_UART(UARTx)); + + if (UART0 == UARTx) + { + return UART0_RDATA; + } + else + { + return UART1_RDATA; + } +} + +int UART_RecvBuf(UART_TypeDef UARTx, uint8_t *buf, int len) +{ + uint32_t length = 0; + volatile int *pstatus = NULL; + volatile unsigned char *pdata = NULL; + _ASSERT(IS_UART(UARTx)); + _ASSERT(NULL != buf); + + if (UART0 == UARTx) + { + pstatus = &UART0_STATUS; + pdata = &UART0_RDATA; + } + else + { + pstatus = &UART1_STATUS; + pdata = &UART1_RDATA; + } + + while ((*pstatus >> 16) > 0) + { + if (length < len) + { + buf[length++] = *pdata; + } + else + { + break; + } + } + + return length; +} + +void UART_SendBuf(UART_TypeDef UARTx, uint8_t *buf, int len) +{ + _ASSERT(IS_UART(UARTx)); + _ASSERT(NULL != buf); + _ASSERT((len < 0xffff)); + + if (UARTx == UART0) + { + DMA_SRC_ADDR(DMACH_UART0) = (int)buf; + DMA_LEN(DMACH_UART0) = (DMA_LEN(DMACH_UART0) & 0xffff) | len << 16; + DMA_START(DMACH_UART0) = (1 << DMA_START_BIT); + while ((!(DMA_STATUS(DMACH_UART0) & 1))); + } + else + { + DMA_SRC_ADDR(DMACH_UART1) = (int)buf; + DMA_LEN(DMACH_UART1) = (DMA_LEN(DMACH_UART1) & 0xffff) | len << 16; + DMA_START(DMACH_UART1) = (1 << DMA_START_BIT); + while ((!(DMA_STATUS(DMACH_UART1) & 1))); + } +} + +void UART_SendData(UART_TypeDef UARTx, uint8_t Data) +{ + uint8_t buf[1] = {Data}; + + if (UARTx == UART0) + { + DMA_SRC_ADDR(DMACH_UART0) = (int)buf; + DMA_LEN(DMACH_UART0) = (DMA_LEN(DMACH_UART0) & 0xffff) | 1 << 16; + DMA_START(DMACH_UART0) = (1 << DMA_START_BIT); + while (!(DMA_STATUS(DMACH_UART0) & 1)); + } + else + { + DMA_SRC_ADDR(DMACH_UART1) = (int)buf; + DMA_LEN(DMACH_UART1) = (DMA_LEN(DMACH_UART1) & 0xffff) | 1 << 16; + DMA_START(DMACH_UART1) = (1 << DMA_START_BIT); + while (!(DMA_STATUS(DMACH_UART1) & 1)); + } +} + +void UART_SetITTimeout(UART_TypeDef UARTx, uint16_t timeout) +{ + if (UART0 == UARTx) + { + UART0_INTR = timeout; + } + else + { + UART1_INTR = timeout; + } +} + +void UART_SetRxITNum(UART_TypeDef UARTx, uint8_t Bcnt) +{ + _ASSERT(IS_UART(UARTx)); + + if (UART0 == UARTx) + { + UART0_CTRL = (UART0_CTRL & 0xffff00ff) | ((Bcnt & 0xff) << 8); + } + else + { + UART1_CTRL = (UART1_CTRL & 0xffff00ff) | ((Bcnt & 0xff) << 8); + } +} + +void UART_StructInit(UART_InitTypeDef *UART_InitStruct) +{ + UART_InitStruct->BaudRate = 9600; + UART_InitStruct->DataBits = Databits_8b; + UART_InitStruct->FlowCtrl = FlowCtrl_None; + UART_InitStruct->Mode = Mode_duplex; + UART_InitStruct->StopBits = StopBits_1; + UART_InitStruct->Parity = 0; +} + +uint16_t UART_ReceiveDataLen(UART_TypeDef UARTx) +{ + _ASSERT(IS_UART(UARTx)); + + if (UART0 == UARTx) + { + return (uint16_t)(UART0_STATUS >> 16); + } + else + { + return (uint16_t)(UART1_STATUS >> 16); + } +} diff --git a/bsp/yichip/yc3121-pos/Libraries/sdk/yc_uart.h b/bsp/yichip/yc3121-pos/Libraries/sdk/yc_uart.h new file mode 100644 index 0000000000..22cf4b9d34 --- /dev/null +++ b/bsp/yichip/yc3121-pos/Libraries/sdk/yc_uart.h @@ -0,0 +1,304 @@ +/* +File Name : yc_uart.h +Author : Yichip +Version : V1.0 +Date : 2019/12/4 +Description : UART encapsulation. +*/ +#ifndef __YC_UART_H__ +#define __YC_UART_H__ + +#include "yc3121.h" + +/** @def time of UART receive data time out intterrupt. real time = regvalue*48 + * @{ + */ +#define TIME_IT_TIMEOUT (uint16_t)0x01 + +/** @defgroup USART_Mode + * @{ + */ +#define Mode_Single_Line (1<<6) +#define Mode_duplex (0<<6) +#define IS_MODE(MODE) (((MODE) == Mode_Single_Line) ||\ + ((MODE) == Mode_duplex)) +/** + * @} + */ + +/** @ + * @defgroup USART_DataBits + */ +#define Databits_8b (0<<2) +#define Databits_9b (1<<2) + +#define IS_USART_WORD_LENGTH(LENGTH) (((LENGTH) == Databits_8b) || \ + ((LENGTH) == Databits_9b)) +/** + * @} + */ + +/** @defgroup USART_Stop_Bits + * @{ + */ +#define StopBits_1 (0<<3) +#define StopBits_2 (1<<3) +#define IS_USART_STOPBITS(STOPBITS) (((STOPBITS) == StopBits_1) || \ + ((STOPBITS) == StopBits_2) ) +/** + * @} + */ + +/** @defgroup USART_Hardware_Flow_Control + * @{ + */ +#define FlowCtrl_None (0<<4) +#define FlowCtrl_Enable (1<<4) + +#define IS_FlowCtrl(CONTROL) (((CONTROL) == FlowCtrl_None) || \ + ((CONTROL) == FlowCtrl_Enable)) +/** + * @} + */ + +/** @defgroup UART_Interrupt_Type_definition + * @{ + */ +#define UART_IT_TX 0x01 +#define UART_IT_RX 0x02 +#define IS_UART_IT(x) (x == UART_IT_TX)||(x == UART_IT_RX) +/** + * @} + */ + +/** @defgroup USART_Parity +* @{ +*/ +#define Parity_None (0<<1) +#define Parity_Even (0<<1) +#define Parity_Odd (1<<1) +#define IS_PARITY(PARITY) (((PARITY) == Parity_Even) ||\ + ((PARITY) == Parity_None) ||\ + ((PARITY) == Parity_Odd)) +/** + * @} + */ + +/** @defgroup USART_BaudRate +* @{ +*/ +#define IS_BAUDRATE(BAUDRATE) (((BAUDRATE) > 0x5B8) && ((BAUDRATE) < 0x0044AA21)) +/** + * @} + */ + +typedef struct +{ + uint8_t Mode; /*!< Specifies wether the Receive or Transmit mode is enabled or disabled. + This parameter can be a value of @ref USART_Mode */ + + uint32_t BaudRate; /*!< This member configures the USART communication baud rate. */ + + uint8_t DataBits; /*!< Specifies the number of data bits transmitted or received in a frame. + This parameter can be a value of @ref USART_DataBits */ + + uint8_t StopBits; /*!< Specifies the number of stop bits transmitted. + This parameter can be a value of @ref USART_Stop_Bits */ + + uint8_t Parity; /*!< Specifies the parity mode. + This parameter can be a value of @ref USART_Parity + @note When parity is enabled, the computed parity is inserted + at the MSB position of the transmitted data (9th bit when + the word length is set to 9 data bits; 8th bit when the + word length is set to 8 data bits). */ + + uint8_t FlowCtrl; /*!< Specifies wether the hardware flow control mode is enabled or disabled. + This parameter can be a value of @ref USART_Hardware_Flow_Control */ + + int RxBufLen; /*!< Specifies uart DMA Rx buff length */ + +} UART_InitTypeDef; + +/** @defgroup UART_TypeDef +* @{ +*/ +typedef enum +{ + UART0 = 0, + UART1, +} UART_TypeDef; + +#define IS_UART(UARTx) (UARTx == UART0 ||UARTx == UART1) +/** + * @} + */ + +/** + * @brief ENABLE or DISABLE UARTx auto flow control + * @param USARTx: Select the USART or the UART peripheral. + * This parameter can be one of the following values: + * UART0, UART1. + * @param NewState:ENABLE or DISABLE auto flow control + * @retval None + */ +void UART_AutoFlowCtrlCmd(UART_TypeDef UARTx, FunctionalState NewState); + +/** + * @brief Clear IT + * @param USARTx: Select the USART or the UART peripheral. + * This parameter can be one of the following values: + * UART0, UART1. + * @retval None + */ +void UART_ClearIT(UART_TypeDef UARTx); + +/** + * @brief DeInit UART + * @param UARTx: Select the UART peripheral. + * This parameter can be one of the following values: + * UART0, UART1. + * @retval None + */ +void UART_DeInit(UART_TypeDef UARTx); + +/** + * @brief Transmits datas via UART DMA . + * @param USARTx: Select the USART or the UART peripheral. + * This parameter can be one of the following values: + * UART0, UART1. + * @param buf: pointer to a buf that contains the data you want transmit. + * @param len: the buf length + * @retval None + */ +void UART_DMASendBuf(UART_TypeDef UARTx, uint8_t *buf, int len); + +/** + * @brief Get IT Identity + * @param UARTx: Select the UART peripheral. + * @retval IT Identity + */ +uint8_t UART_GetITIdentity(UART_TypeDef UARTx); + +/** + * @brief Initializes the USARTx peripheral according to the specified + * parameters in the USART_InitStruct . + * @param UARTx: Select the UART peripheral. + * This parameter can be one of the following values: + * UART0, UART1. + * @param USART_InitStruct: pointer to a USART_InitTypeDef structure + * that contains the configuration information for the specified USART + * peripheral. + * @retval None + */ +void UART_Init(UART_TypeDef UARTx, UART_InitTypeDef *UART_InitStruct); + +/** + * @brief Judge Rx fifo full is or not. + * @param UARTx: Select the UART peripheral. + * @retval TRUE:Rx fifo is full. + * FALSE:Rx fifo is not full + */ +Boolean UART_IsRXFIFOFull(UART_TypeDef UARTx); + +/** + * @brief Judge Rx fifo empty is or not. + * @param UARTx: Select the UART peripheral. + * @retval TRUE:Rx fifo is not empty. + * FALSE:Rx fifo is empty; + */ +Boolean UART_IsRXFIFONotEmpty(UART_TypeDef UARTx); + +/** + * @brief Judge UART is Busy or not + * @param UARTx: Select the UART peripheral. + * @retval None + */ +Boolean UART_IsUARTBusy(UART_TypeDef UARTx); + +/** + * @brief Config Interrupt trigger mode + * @param USARTx: Select the USART or the UART peripheral. + * This parameter can be one of the following values: + * UART0, UART1. + * @param UART_IT: Interrupt trigger mode ,this param will the following values, + * UART_IT_TX:interrupt trigger after send data completed. + * UART_IT_RX:interrupt trigger when received data. + * @param NewState: + * @retval None + */ +void UART_ITConfig(UART_TypeDef UARTx, uint32_t UART_IT, FunctionalState NewState); + +/** + * @brief Receive single data through the USARTx peripheral. + * @param USARTx: Select the USART or the UART peripheral. + * This parameter can be one of the following values: + * UART0, UART1. + * @retval None + */ +uint8_t UART_ReceiveData(UART_TypeDef UARTx); + +/** + * @brief Receives datas through the UART DMA. + * @param USARTx: Select the USART or the UART peripheral. + * This parameter can be one of the following values: + * UART0, UART1. + * @param buf: pointer to a buf that contains the data you want receive. + * @param len: the buf length + * @retval None + */ +int UART_RecvBuf(UART_TypeDef UARTx, uint8_t *buf, int len); + +/** + * @brief T ransmits datas via UART DMA,the function will return after datas is sent. + * @param USARTx: Select the USART or the UART peripheral. + * This parameter can be one of the following values: + * UART0, UART1. + * @param buf: pointer to a buf that contains the data you want transmit. + * @param len: the buf length + * @retval None + */ +void UART_SendBuf(UART_TypeDef UARTx, uint8_t *buf, int len); + +/** + * @brief UART Send One Data + * @param UARTx: Select the UART peripheral. + * @retval None + */ +void UART_SendData(UART_TypeDef UARTx, uint8_t Data); + +/** + * @brief UART_SetITTimeout + * @param USARTx: Select the USART or the UART peripheral. + * This parameter can be one of the following values: + * UART0, UART1. + * timeout: 0x0000~0xffff + * @retval None + */ +void UART_SetITTimeout(UART_TypeDef UARTx, uint16_t timeout); + +/** + * @brief Set the number of uart receive data intterupt trigger + * @param UARTx: Select the UART peripheral. + * This parameter can be one of the following values: + * UART0, UART1. + * @param Bcnt: if the number of receive datas greater than Bcnt,interrupt trigger + * @retval None + */ +void UART_SetRxITNum(UART_TypeDef UARTx, uint8_t Bcnt); + +/** + * @brief Fills each USART_InitStruct member with its default value. + * @param USART_InitStruct: pointer to a USART_InitTypeDef structure + * which will be initialized. + * @retval None + */ +void UART_StructInit(UART_InitTypeDef *UART_InitStruct); + +/** + * @brief UART_ReceiveDataLen + * @param UARTx: UART0 or UART1 + * @retval Data len + */ +uint16_t UART_ReceiveDataLen(UART_TypeDef UARTx); + +#endif /*__YC_UART_H__*/ diff --git a/bsp/yichip/yc3121-pos/Libraries/sdk/yc_wdt.c b/bsp/yichip/yc3121-pos/Libraries/sdk/yc_wdt.c new file mode 100644 index 0000000000..8b4948b798 --- /dev/null +++ b/bsp/yichip/yc3121-pos/Libraries/sdk/yc_wdt.c @@ -0,0 +1,54 @@ +#include "yc_wdt.h" + +#define WDT_ENABLE_BIT_Mask 6 +#define WDT_MODE_BIT_Mask 5 +#define SYSCTRL_WDT_EN_BIT_Mask 1 + +/**************the value of feed dog************/ +#define COUNTER_RELOAD_KEY 0x5937 + +void WDT_SetReload(uint32_t Reload) +{ + uint32_t wdt_config = 0; + + _ASSERT(ISWDTRELOAD(Reload)); + + wdt_config = WD_CONFIG; + wdt_config &= 0xE0; + wdt_config |= Reload; + WD_CONFIG = wdt_config; +} + +void WDT_ReloadCounter(void) +{ + WD_KICK = COUNTER_RELOAD_KEY; +} + +void WDT_Enable(void) +{ + WD_CONFIG |= (1 << WDT_ENABLE_BIT_Mask); +} + +void WDT_ModeConfig(WDT_ModeTypeDef WDT_Mode) +{ + WD_CONFIG &= ~(1 << WDT_MODE_BIT_Mask); + WD_CONFIG |= (WDT_Mode << WDT_MODE_BIT_Mask); + if (WDT_CPUReset == WDT_Mode) + { + SYSCTRL_RST_EN |= (1 << 1); + } + else + { + SYSCTRL_RST_EN &= ~(1 << 1); + } +} + +ITStatus WDT_GetITStatus(void) +{ + return (ITStatus)(WD_KICK & 1); +} + +void WDT_ClearITPendingBit(void) +{ + WD_CLEAR = 1; +} diff --git a/bsp/yichip/yc3121-pos/Libraries/sdk/yc_wdt.h b/bsp/yichip/yc3121-pos/Libraries/sdk/yc_wdt.h new file mode 100644 index 0000000000..e9594d035e --- /dev/null +++ b/bsp/yichip/yc3121-pos/Libraries/sdk/yc_wdt.h @@ -0,0 +1,74 @@ +/** + ****************************************************************************** + * @file yc_wdt.h + * @author Yichip + * @version V1.0 + * @date 7-Dec-2019 + * @brief watchdog encapsulation. + * + ****************************************************************************** + */ + +#ifndef __YC_WDT_H__ +#define __YC_WDT_H__ + +#include "yc3121.h" + +/** + * @brief timer number Structure definition + */ +typedef enum +{ + WDT_CPUReset = 0, + WDT_Interrupt, +} WDT_ModeTypeDef; + +#define ISWDTRELOAD(load) (load>0&&load<=0x1f) + +/** + * @brief Set reload counter + * @param Reload: Reload counter equal to 2^reload. + * @retval none + */ +void WDT_SetReload(uint32_t Reload); + +/** + * @brief Set WDT mode + * @param WDT_Mode : Select the following values : + * WDT_CPUReset + * WDT_Interrupt. + * @retval none + * @description If Select WDT_CPUReset Mode,the bit for WDT RESET will be set;if + * Select WDT_Interrupt the bit for WDT RESET will + */ +void WDT_ModeConfig(WDT_ModeTypeDef WDT_Mode); + +/** + * @brief Get interrupt Status + * @param none + * @retval SET:interrupt ocuured. + */ +ITStatus WDT_GetITStatus(void); + +/** + * @brief Clear interrupt + * @param none + * @retval none + */ +void WDT_ClearITPendingBit(void); + +/** + * @brief Enable WDT + * @param none + * @retval none + */ +void WDT_Enable(void); + +/** + * @brief Feed the watchdog function + * @param none + * @retval none + */ +void WDT_ReloadCounter(void); + +#endif /*__YC_WDT_H__*/ diff --git a/bsp/yichip/yc3121-pos/Libraries/startup/flash_start.s b/bsp/yichip/yc3121-pos/Libraries/startup/flash_start.s new file mode 100644 index 0000000000..6c354c6f39 --- /dev/null +++ b/bsp/yichip/yc3121-pos/Libraries/startup/flash_start.s @@ -0,0 +1,396 @@ + AREA |.flash_start|, CODE, READONLY ,ALIGN=4 + +Reset_Handler PROC + EXPORT Reset_Handler + IMPORT __main + LDR R0, =__main + BX R0 + ENDP + + +hard_fault_handler PROC + EXPORT hard_fault_handler + IMPORT HardFault_Handler + ldr r0,=HardFault_Handler + bx r0 + nop + ENDP + +svc_handler PROC + EXPORT svc_handler + ldr r0,=SVC_IRQHandler + bx r0 + nop + ENDP + +pendsv_handler PROC + EXPORT pendsv_handler + IMPORT PendSV_Handler + ldr r0,=PendSV_Handler + bx r0 + nop + ENDP + +systick PROC + EXPORT systick + IMPORT SysTick_Handler + ldr r0,=SysTick_Handler + bx r0 + nop + ENDP + +irq0 PROC + EXPORT irq0 + movs r0,#4*0 + b isr + ENDP + +irq1 PROC + EXPORT irq1 + movs r0,#4*1 + b isr + ENDP + +irq2 PROC + EXPORT irq2 + movs r0,#4*2 + b isr + ENDP + +irq3 PROC + EXPORT irq3 + movs r0,#4*3 + b isr + ENDP + +irq4 PROC + EXPORT irq4 + movs r0,#4*4 + b isr + ENDP + +irq5 PROC + EXPORT irq5 + movs r0,#4*5 + b isr + ENDP + +irq6 PROC + EXPORT irq6 + movs r0,#4*6 + b isr + ENDP + +irq7 PROC + EXPORT irq7 + movs r0,#4*7 + b isr + ENDP + +irq8 PROC + EXPORT irq8 + movs r0,#4*8 + b isr + ENDP + +irq9 PROC + EXPORT irq9 + movs r0,#4*9 + b isr + ENDP + +irq10 PROC + EXPORT irq10 + movs r0,#4*10 + b isr + ENDP + +irq11 PROC + EXPORT irq11 + movs r0,#4*11 + b isr + ENDP + +irq12 PROC + EXPORT irq12 + movs r0,#4*12 + b isr + ENDP + +irq13 PROC + EXPORT irq13 + movs r0,#4*13 + b isr + ENDP + +irq14 PROC + EXPORT irq14 + movs r0,#4*14 + b isr + ENDP + +irq15 PROC + EXPORT irq15 + movs r0,#4*15 + b isr + ENDP + +irq16 PROC + EXPORT irq16 + movs r0,#4*16 + b isr + ENDP + +irq17 PROC + EXPORT irq17 + movs r0,#4*17 + b isr + ENDP + +irq18 PROC + EXPORT irq18 + movs r0,#4*18 + b isr + ENDP + +irq19 PROC + EXPORT irq19 + movs r0,#4*19 + b isr + ENDP + +irq20 PROC + EXPORT irq20 + movs r0,#4*20 + b isr + ENDP + +irq21 PROC + EXPORT irq21 + movs r0,#4*21 + b isr + ENDP + +irq22 PROC + EXPORT irq22 + movs r0,#4*22 + b isr + ENDP + +irq23 PROC + EXPORT irq23 + movs r0,#4*23 + b isr + ENDP + +irq24 PROC + EXPORT irq24 + movs r0,#4*24 + b isr + ENDP + +irq25 PROC + EXPORT irq25 + movs r0,#4*25 + b isr + ENDP + +irq26 PROC + EXPORT irq26 + movs r0,#4*26 + b isr + ENDP + +irq27 PROC + EXPORT irq27 + movs r0,#4*27 + b isr + ENDP + +irq28 PROC + EXPORT irq28 + movs r0,#4*28 + b isr + ENDP + +irq29 PROC + EXPORT irq29 + movs r0,#4*29 + b isr + ENDP + +irq30 PROC + EXPORT irq30 + movs r0,#4*30 + b isr + ENDP + +irq31 PROC + EXPORT irq31 + movs r0,#4*31 + b isr + ENDP + + +isr PROC + ldr r1,=isr_table + ldr r0,[r0, r1] + bx r0 + ENDP + + ALIGN +NMI_IRQHandler PROC + EXPORT NMI_IRQHandler [WEAK] + B . + ENDP + +HARD_FAULT_IRQHandler PROC + EXPORT HARD_FAULT_IRQHandler [WEAK] + B . + ENDP + +SVC_IRQHandler PROC + EXPORT SVC_IRQHandler [WEAK] + B . + ENDP + +PENDSV_IRQHandler PROC + EXPORT PENDSV_IRQHandler [WEAK] + B . + ENDP + +SYSTICK_IRQHandler PROC + EXPORT SYSTICK_IRQHandler [WEAK] + B . + ENDP + +EXTI0_IRQHandler PROC + EXPORT EXTI0_IRQHandler [WEAK] + B . + ENDP + +EXTI1_IRQHandler PROC + EXPORT EXTI1_IRQHandler [WEAK] + B . + ENDP + +EXTI2_IRQHandler PROC + EXPORT EXTI2_IRQHandler [WEAK] + B . + ENDP + +EXTI3_IRQHandler PROC + EXPORT EXTI3_IRQHandler [WEAK] + B . + ENDP + +EXTI4_IRQHandler PROC + EXPORT EXTI4_IRQHandler [WEAK] + B . + ENDP + +EXTI5_IRQHandler PROC + EXPORT EXTI5_IRQHandler [WEAK] + B . + ENDP + +Default_Handler PROC +; ToDo: Add here the export definition for the device specific external interrupts handler + EXPORT USB_IRQHandler [WEAK] + EXPORT IIC_IRQHandler [WEAK] + EXPORT QSPI_IRQHandler [WEAK] + EXPORT SPI0_IRQHandler [WEAK] + EXPORT SPI1_IRQHandler [WEAK] + EXPORT UART0_IRQHandler [WEAK] + EXPORT UART1_IRQHandler [WEAK] + EXPORT MEMCP_IRQHandler [WEAK] + EXPORT RSA_IRQHandler [WEAK] + EXPORT SCI0_IRQHandler [WEAK] + EXPORT SCI1_IRQHandler [WEAK] + EXPORT BT_IRQHandler [WEAK] + EXPORT GPIO_IRQHandler [WEAK] + EXPORT TIMER0_IRQHandler [WEAK] + EXPORT TIMER1_IRQHandler [WEAK] + EXPORT TIMER2_IRQHandler [WEAK] + EXPORT TIMER3_IRQHandler [WEAK] + EXPORT TIMER4_IRQHandler [WEAK] + EXPORT TIMER5_IRQHandler [WEAK] + EXPORT TIMER6_IRQHandler [WEAK] + EXPORT TIMER7_IRQHandler [WEAK] + EXPORT TIMER8_IRQHandler [WEAK] + EXPORT SM4_IRQHandler [WEAK] + EXPORT SEC_IRQHandler [WEAK] + EXPORT MSR_IRQHandler [WEAK] + EXPORT TRNG_IRQHandler [WEAK] + EXPORT WDT_IRQHandler [WEAK] + +; ToDo: Add here the names for the device specific external interrupts handler +USB_IRQHandler +IIC_IRQHandler +QSPI_IRQHandler +SPI0_IRQHandler +SPI1_IRQHandler +UART0_IRQHandler +UART1_IRQHandler +MEMCP_IRQHandler +RSA_IRQHandler +SCI0_IRQHandler +SCI1_IRQHandler +BT_IRQHandler +GPIO_IRQHandler +TIMER0_IRQHandler +TIMER1_IRQHandler +TIMER2_IRQHandler +TIMER3_IRQHandler +TIMER4_IRQHandler +TIMER5_IRQHandler +TIMER6_IRQHandler +TIMER7_IRQHandler +TIMER8_IRQHandler +SM4_IRQHandler +SEC_IRQHandler +MSR_IRQHandler +TRNG_IRQHandler +WDT_IRQHandler + B . + ENDP + + + + EXPORT isr_table +isr_table DCD USB_IRQHandler + DCD IIC_IRQHandler + DCD QSPI_IRQHandler + DCD SPI0_IRQHandler + DCD SPI1_IRQHandler + DCD UART0_IRQHandler + DCD UART1_IRQHandler + DCD MEMCP_IRQHandler + DCD RSA_IRQHandler + DCD SCI0_IRQHandler + DCD SCI1_IRQHandler + DCD BT_IRQHandler + DCD GPIO_IRQHandler + DCD TIMER0_IRQHandler + DCD TIMER1_IRQHandler + DCD TIMER2_IRQHandler + DCD TIMER3_IRQHandler + DCD TIMER4_IRQHandler + DCD TIMER5_IRQHandler + DCD TIMER6_IRQHandler + DCD TIMER7_IRQHandler + DCD TIMER8_IRQHandler + DCD SM4_IRQHandler + DCD SEC_IRQHandler + DCD MSR_IRQHandler + DCD TRNG_IRQHandler + DCD WDT_IRQHandler + END + + + + + + + + diff --git a/bsp/yichip/yc3121-pos/Libraries/startup/flash_start_gcc.s b/bsp/yichip/yc3121-pos/Libraries/startup/flash_start_gcc.s new file mode 100644 index 0000000000..02302d303f --- /dev/null +++ b/bsp/yichip/yc3121-pos/Libraries/startup/flash_start_gcc.s @@ -0,0 +1,318 @@ + .org 0x200 + .global Reset_Handler,hard_fault_handler,svc_handler,pendsv_handler,systick,irq0,irq1,irq2,irq3,irq4,irq5,irq6,irq7,irq8,irq9,irq10,irq11,irq12,irq13,irq14,irq15,irq16,irq17,irq18,irq19,irq20,irq21,irq22,irq23,irq24,irq25,irq26,irq27,irq28,irq29,irq30,irq31 + + .long + + +Reset_Handler: + ldr r0,=hardware_init + bx r0 + .thumb_func + +hard_fault_handler: + ldr r0,=HARD_FAULT_IRQHandler + bx r0 + nop + .thumb_func + +svc_handler: + ldr r0,=SVC_IRQHandler + bx r0 + nop + .thumb_func + +pendsv_handler: + ldr r0,=PENDSV_IRQHandler + bx r0 + nop + .thumb_func +systick: + ldr r0,=SYSTICK_IRQHandler + bx r0 + nop + .thumb_func +irq0: + mov r0,#4*0 + b isr + .thumb_func +irq1: + mov r0,#4*1 + b isr + .thumb_func +irq2: + mov r0,#4*2 + b isr + .thumb_func +irq3: + mov r0,#4*3 + b isr + .thumb_func +irq4: + mov r0,#4*4 + b isr + .thumb_func +irq5: + mov r0,#4*5 + b isr + .thumb_func +irq6: + mov r0,#4*6 + b isr + .thumb_func +irq7: + mov r0,#4*7 + b isr + .thumb_func +irq8: + mov r0,#4*8 + b isr + .thumb_func +irq9: + mov r0,#4*9 + b isr + .thumb_func +irq10: + mov r0,#4*10 + b isr + .thumb_func +irq11: + mov r0,#4*11 + b isr + .thumb_func +irq12: + mov r0,#4*12 + b isr + .thumb_func +irq13: + mov r0,#4*13 + b isr + .thumb_func +irq14: + mov r0,#4*14 + b isr + .thumb_func +irq15: + mov r0,#4*15 + b isr + .thumb_func +irq16: + mov r0,#4*16 + b isr + .thumb_func +irq17: + mov r0,#4*17 + b isr + .thumb_func +irq18: + mov r0,#4*18 + b isr + .thumb_func +irq19: + mov r0,#4*19 + b isr + .thumb_func +irq20: + mov r0,#4*20 + b isr + .thumb_func +irq21: + mov r0,#4*21 + b isr + .thumb_func +irq22: mov r0,#4*22 + b isr + .thumb_func +irq23: + mov r0,#4*23 + b isr + .thumb_func +irq24: + mov r0,#4*24 + b isr + .thumb_func +irq25: mov r0,#4*25 + b isr + .thumb_func +irq26: + mov r0,#4*26 + b isr + .thumb_func +irq27: + mov r0,#4*27 + b isr + .thumb_func +irq28: + mov r0,#4*28 + b isr + .thumb_func +irq29: + mov r0,#4*29 + b isr + .thumb_func +irq30: + mov r0,#4*30 + b isr + .thumb_func +irq31: + mov r0,#4*31 + b isr + .thumb_func + + + +isr: + ldr r1,=isr_table + ldr r0,[r0, r1] + bx r0 + + + + + .align 4 +isr_table: + .long USB_IRQHandler + .long IIC_IRQHandler + .long QSPI_IRQHandler + .long SPI0_IRQHandler + .long SPI1_IRQHandler + .long UART0_IRQHandler + .long UART1_IRQHandler + .long MEMCP_IRQHandler + .long RSA_IRQHandler + .long SCI0_IRQHandler + .long SCI1_IRQHandler + .long BT_IRQHandler + .long GPIO_IRQHandler + .long TIMER0_IRQHandler + .long TIMER1_IRQHandler + .long TIMER2_IRQHandler + .long TIMER3_IRQHandler + .long TIMER4_IRQHandler + .long TIMER5_IRQHandler + .long TIMER6_IRQHandler + .long TIMER7_IRQHandler + .long TIMER8_IRQHandler + .long SM4_IRQHandler + .long SEC_IRQHandler + .long MSR_IRQHandler + .long TRNG_IRQHandler + .long WDT_IRQHandler + + .thumb + .thumb_func +hardware_init: + ldr r1, =__exidx_start + ldr r2, =__data_start__ + ldr r3, =__data_end__ + + sub r3, r2 + ble .L_loop1_done + + .L_loop1: + sub r3, #4 + ldr r0, [r1,r3] + str r0, [r2,r3] + bgt .L_loop1 + + .L_loop1_done: + + + + /* Single BSS section scheme. + * + * The BSS section is specified by following symbols + * _sbss: start of the BSS section. + * _ebss: end of the BSS section. + * + * Both addresses must be aligned to 4 bytes boundary. + */ + ldr r1, =__bss_start__ + ldr r2, =__bss_end__ + + mov r0, #0 + + sub r2, r1 + ble .L_loop3_done + + .L_loop3: + sub r2, #4 + str r0, [r1, r2] + bgt .L_loop3 + .L_loop3_done: + ldr r0,=0x12345 + ldr r3,=0x1111 + bl main + + + .globl delay + .syntax unified +delay: + subs r0,#1 + bne delay + nop + bx lr + + + + + + + +.align 1 +.thumb_func +.weak Default_Handler +.type Default_Handler, %function + +Default_Handler: + b . + .size Default_Handler, . - Default_Handler + +/* Macro to define default handlers. Default handler + * will be weak symbol and just dead loops. They can be + * overwritten by other handlers */ + + .macro def_irq_handler handler_name + .weak \handler_name + .set \handler_name, Default_Handler + .endm + + def_irq_handler HARD_FAULT_IRQHandler + def_irq_handler SVC_IRQHandler + def_irq_handler PENDSV_IRQHandler + def_irq_handler SYSTICK_IRQHandler + def_irq_handler USB_IRQHandler + def_irq_handler IIC_IRQHandler + def_irq_handler QSPI_IRQHandler + def_irq_handler SPI0_IRQHandler + def_irq_handler SPI1_IRQHandler + def_irq_handler UART0_IRQHandler + def_irq_handler UART1_IRQHandler + def_irq_handler MEMCP_IRQHandler + def_irq_handler RSA_IRQHandler + def_irq_handler SCI0_IRQHandler + def_irq_handler SCI1_IRQHandler + def_irq_handler BT_IRQHandler + def_irq_handler GPIO_IRQHandler + def_irq_handler EXTI0_IRQHandler + def_irq_handler EXTI1_IRQHandler + def_irq_handler EXTI2_IRQHandler + def_irq_handler TIMER0_IRQHandler + def_irq_handler TIMER1_IRQHandler + def_irq_handler TIMER2_IRQHandler + def_irq_handler TIMER3_IRQHandler + def_irq_handler TIMER4_IRQHandler + def_irq_handler TIMER5_IRQHandler + def_irq_handler TIMER6_IRQHandler + def_irq_handler TIMER7_IRQHandler + def_irq_handler TIMER8_IRQHandler + def_irq_handler SM4_IRQHandler + def_irq_handler SEC_IRQHandler + def_irq_handler MSR_IRQHandler + def_irq_handler TRNG_IRQHandler + def_irq_handler WDT_IRQHandler + + + + + + diff --git a/bsp/yichip/yc3121-pos/Libraries/startup/flash_start_iar.s b/bsp/yichip/yc3121-pos/Libraries/startup/flash_start_iar.s new file mode 100644 index 0000000000..a1307cd43d --- /dev/null +++ b/bsp/yichip/yc3121-pos/Libraries/startup/flash_start_iar.s @@ -0,0 +1,311 @@ + MODULE ?cstartup + + EXTERN __iar_program_start + + SECTION CSTACK:DATA:NOROOT(3) + + PUBLIC start_flash + SECTION .intvec:CODE:REORDER(2) +start_flash + LDR R0, =hardware_init + BX R0 + + PUBLIC hard_fault_handler +hard_fault_handler + BL HARD_FAULT_IRQHandler + + PUBLIC svc_handler +svc_handler + BL SVC_IRQHandler + + PUBLIC pendsv_handler +pendsv_handler + BL PENDSV_IRQHandler + + PUBLIC systick +systick + BL SYSTICK_IRQHandler + + PUBLIC irq0 +irq0 + movs r0,#0 + b isr + + PUBLIC irq1 +irq1 + movs r0,#1 + b isr + + PUBLIC irq2 +irq2 + movs r0,#2 + b isr + + PUBLIC irq3 +irq3 + movs r0,#3 + b isr + + PUBLIC irq4 +irq4 + movs r0,#4 + b isr + + PUBLIC irq5 +irq5 + movs r0,#5 + b isr + + PUBLIC irq6 +irq6 + movs r0,#6 + b isr + + PUBLIC irq7 +irq7 + movs r0,#7 + b isr + + PUBLIC irq8 +irq8 + movs r0,#8 + b isr + + PUBLIC irq9 +irq9 + movs r0,#9 + b isr + + PUBLIC irq10 +irq10 + movs r0,#10 + b isr + + PUBLIC irq11 +irq11 + movs r0,#11 + b isr + + PUBLIC irq12 +irq12 + movs r0,#12 + b isr + + PUBLIC irq13 +irq13 + movs r0,#13 + b isr + + PUBLIC irq14 +irq14 + movs r0,#14 + b isr + + PUBLIC irq15 +irq15 + movs r0,#15 + b isr + + PUBLIC irq16 +irq16 + movs r0,#16 + b isr + + PUBLIC irq17 +irq17 + movs r0,#17 + b isr + + PUBLIC irq18 +irq18 + movs r0,#18 + b isr + + PUBLIC irq19 +irq19 + movs r0,#19 + b isr + + PUBLIC irq20 +irq20 + movs r0,#20 + b isr + + PUBLIC irq21 +irq21 + movs r0,#21 + b isr + + PUBLIC irq22 +irq22 + movs r0,#22 + b isr + + PUBLIC irq23 +irq23 + movs r0,#23 + b isr + + PUBLIC irq24 +irq24 + movs r0,#24 + b isr + + PUBLIC irq25 +irq25 + movs r0,#25 + b isr + + PUBLIC irq26 +irq26 + movs r0,#26 + b isr + + PUBLIC irq27 +irq27 + movs r0,#27 + b isr + + PUBLIC irq28 +irq28 + movs r0,#28 + b isr + + PUBLIC irq29 +irq29 + movs r0,#29 + b isr + + PUBLIC irq30 +irq30 + movs r0,#30 + b isr + + PUBLIC irq31 +irq31 + movs r0,#31 + b isr + + PUBLIC isr +isr + ldr r1,=__vector_table + ldr r0,[r0, r1] + bx r0 + + + PUBWEAK HARD_FAULT_IRQHandler + PUBWEAK SVC_IRQHandler + PUBWEAK PENDSV_IRQHandler + PUBWEAK SYSTICK_IRQHandler + PUBWEAK USB_IRQHandler + PUBWEAK IIC_IRQHandler + PUBWEAK QSPI_IRQHandler + PUBWEAK SPI0_IRQHandler + PUBWEAK SPI1_IRQHandler + PUBWEAK UART0_IRQHandler + PUBWEAK UART1_IRQHandler + PUBWEAK MEMCP_IRQHandler + PUBWEAK RSA_IRQHandler + PUBWEAK SCI0_IRQHandler + PUBWEAK SCI1_IRQHandler + PUBWEAK BT_IRQHandler + PUBWEAK GPIO_IRQHandler + PUBWEAK TIMER0_IRQHandler + PUBWEAK TIMER1_IRQHandler + PUBWEAK TIMER2_IRQHandler + PUBWEAK TIMER3_IRQHandler + PUBWEAK TIMER4_IRQHandler + PUBWEAK TIMER5_IRQHandler + PUBWEAK TIMER6_IRQHandler + PUBWEAK TIMER7_IRQHandler + PUBWEAK TIMER8_IRQHandler + PUBWEAK SM4_IRQHandler + PUBWEAK SEC_IRQHandler + PUBWEAK MSR_IRQHandler + PUBWEAK TRNG_IRQHandler + PUBWEAK WDT_IRQHandler + + +HARD_FAULT_IRQHandler +SVC_IRQHandler +PENDSV_IRQHandler +SYSTICK_IRQHandler + +USB_IRQHandler +IIC_IRQHandler +QSPI_IRQHandler +SPI0_IRQHandler +SPI1_IRQHandler +UART0_IRQHandler +UART1_IRQHandler +MEMCP_IRQHandler +RSA_IRQHandler +SCI0_IRQHandler +SCI1_IRQHandler +BT_IRQHandler +GPIO_IRQHandler +TIMER0_IRQHandler +TIMER1_IRQHandler +TIMER2_IRQHandler +TIMER3_IRQHandler +TIMER4_IRQHandler +TIMER5_IRQHandler +TIMER6_IRQHandler +TIMER7_IRQHandler +TIMER8_IRQHandler +SM4_IRQHandler +SEC_IRQHandler +MSR_IRQHandler +TRNG_IRQHandler +WDT_IRQHandler + B . + + PUBLIC delay +delay + subs r0,#1 + bne delay + nop + bx lr + + PUBLIC __vector_table + ALIGNROM 2 + data +__vector_table + DCD USB_IRQHandler + DCD IIC_IRQHandler + DCD QSPI_IRQHandler + DCD SPI0_IRQHandler + DCD SPI1_IRQHandler + DCD UART0_IRQHandler + DCD UART1_IRQHandler + DCD MEMCP_IRQHandler + DCD RSA_IRQHandler + DCD SCI0_IRQHandler + DCD SCI1_IRQHandler + DCD BT_IRQHandler + DCD GPIO_IRQHandler + DCD TIMER0_IRQHandler + DCD TIMER1_IRQHandler + DCD TIMER2_IRQHandler + DCD TIMER3_IRQHandler + DCD TIMER4_IRQHandler + DCD TIMER5_IRQHandler + DCD TIMER6_IRQHandler + DCD TIMER7_IRQHandler + DCD TIMER8_IRQHandler + DCD SM4_IRQHandler + DCD SEC_IRQHandler + DCD MSR_IRQHandler + DCD TRNG_IRQHandler + DCD WDT_IRQHandler + + + PUBLIC hardware_init + SECTION .intvec:CODE:REORDER(2) + CODE +hardware_init + LDR R0, =sfe(CSTACK) + mov sp, R0 + LDR R0, =__iar_program_start + BX R0 + END \ No newline at end of file diff --git a/bsp/yichip/yc3121-pos/Libraries/startup/startup.s b/bsp/yichip/yc3121-pos/Libraries/startup/startup.s new file mode 100644 index 0000000000..23aecc12b2 --- /dev/null +++ b/bsp/yichip/yc3121-pos/Libraries/startup/startup.s @@ -0,0 +1,175 @@ +Stack_Size EQU 0x0000100 + + AREA STACK, NOINIT, READWRITE, ALIGN=4 +Stack_Mem SPACE Stack_Size +__initial_sp EQU 0x30000 + + +; Heap Configuration +; Heap Size (in Bytes) <0x0-0xFFFFFFFF:8> +; + +Heap_Size EQU 0x00000000 + AREA HEAP, NOINIT, READWRITE, ALIGN=4 +__heap_base +Heap_Mem SPACE Heap_Size +__heap_limit + + + PRESERVE8 + THUMB + + +; Vector Table Mapped to Address 0 at Reset + + AREA RESET, DATA, READONLY + IMPORT systick + IMPORT irq0 + IMPORT irq1 + IMPORT irq2 + IMPORT irq3 + IMPORT irq4 + IMPORT irq5 + IMPORT irq6 + IMPORT irq7 + IMPORT irq8 + IMPORT irq9 + IMPORT irq10 + IMPORT irq11 + IMPORT irq12 + IMPORT irq13 + IMPORT irq14 + IMPORT irq15 + IMPORT irq16 + IMPORT irq17 + IMPORT irq18 + IMPORT irq19 + IMPORT irq20 + IMPORT irq21 + IMPORT irq22 + IMPORT irq23 + IMPORT irq24 + IMPORT irq25 + IMPORT irq26 + IMPORT irq27 + IMPORT irq28 + IMPORT irq29 + IMPORT irq30 + IMPORT irq31 + IMPORT hard_fault_handler + + EXPORT __Vectors + EXPORT __Vectors_End + EXPORT __Vectors_Size +__Vectors DCD __initial_sp ; Top of Stack + DCD reset_handler ; Reset Handler + DCD nmi_handler ; NMI Handler + DCD hard_fault_handler ; Hard Fault Handler + DCD 0 ; + DCD 0 ; + DCD 0 ; + DCD 0 ; + DCD 0 ; + DCD 0 ; + DCD 0 ; + DCD 0 ; + DCD 0 ; + DCD 0 ; + DCD 0 ; + DCD systick ; + DCD irq0 ; + DCD irq1 ; + DCD irq2 ; + DCD irq3 ; + DCD irq4 ; + DCD irq5 ; + DCD irq6 ; + DCD irq7 ; + DCD irq8 ; + DCD irq9 ; + DCD irq10 ; + DCD irq11 ; + DCD irq12 ; + DCD irq13 ; + DCD irq14 ; + DCD irq15 ; + DCD irq16 ; + DCD irq17 ; + DCD irq18 ; + DCD irq19 ; + DCD irq20 ; + DCD irq21 ; + DCD irq22 ; + DCD irq23 ; + DCD irq24 ; + DCD irq25 ; + DCD irq26 ; + DCD irq27 ; + DCD irq28 ; + DCD irq29 ; + DCD irq30 ; + DCD irq31 ; +__Vectors_End + +__Vectors_Size EQU __Vectors_End - __Vectors + + AREA |.text|, CODE, READONLY ,ALIGN=4 + + + +; Reset Handler + +reset_handler PROC + EXPORT reset_handler [WEAK] + IMPORT Reset_Handler +; bl Reset_Handler +; movs r0,#0x3 + + LDR R0, =Reset_Handler + BX R0 + nop + ENDP + + + +delay PROC + EXPORT delay + subs r0,#1 + bne delay + nop + bx lr + ENDP + +nmi_handler PROC + EXPORT nmi_handler [WEAK] + b nmi_handler + ENDP + + ALIGN + + AREA |.INIT_STACK_HEAP|, CODE,READONLY,ALIGN=4 +; User Initial Stack & Heap + + IF :DEF:__MICROLIB + EXPORT __initial_sp + EXPORT __heap_base + EXPORT __heap_limit + + ELSE + + IMPORT __use_two_region_memory + EXPORT __user_initial_stackheap + +__user_initial_stackheap PROC + LDR R0, = Heap_Mem + LDR R1, = __initial_sp + LDR R2, = (Heap_Mem + Heap_Size) + LDR R3, = Stack_Mem + BX LR + ENDP + + ALIGN + + ENDIF + + END \ No newline at end of file diff --git a/bsp/yichip/yc3121-pos/README.md b/bsp/yichip/yc3121-pos/README.md new file mode 100644 index 0000000000..490faa69a6 --- /dev/null +++ b/bsp/yichip/yc3121-pos/README.md @@ -0,0 +1,36 @@ +# YC3121-pos 板级支持包 说明 + +标签： YICHIP、Cortex-M0、YC3121、国产MCU + +--- + +## 1. 简介 + +本文档为 YC3121-pos 的 BSP(板级支持包) 说明。 + +通过阅读本文档，开发者可以快速地上手该 BSP，将 RT-Thread 运行在开发板上。 + +### 1.1 开发板介绍 + +YC3121-pos 开发板由易兆微提供，可满足基础测试及高端开发需求。 + +开发板外观如下图所示： + +YC3121-pos + +![YC3121-pos](figures/YC3121-pos.jpg "YC3121-pos") + +YC3121-pos 开发板板载资源如下： + +- MCU：YC3121 ARM 32-bit Cortex-M0，主频 96MHz，512KB FLASH ，64KB SRAM +- 常用外设 + - LED：4 个 + - 梯形矩阵键盘 + - 蜂鸣器 + - USB + - UART + - SPI LCD + - SPI NFC + - 7816 + - 7811 +- 调试接口：SWD diff --git a/bsp/yichip/yc3121-pos/SConscript b/bsp/yichip/yc3121-pos/SConscript new file mode 100644 index 0000000000..1b1c7506a4 --- /dev/null +++ b/bsp/yichip/yc3121-pos/SConscript @@ -0,0 +1,11 @@ +from building import * + +cwd = GetCurrentDir() + +objs = [] +list = os.listdir(cwd) +for d in list: + path = os.path.join(cwd, d) + if os.path.isfile(os.path.join(path, 'SConscript')): + objs = objs + SConscript(os.path.join(d, 'SConscript')) +Return('objs') diff --git a/bsp/yichip/yc3121-pos/SConstruct b/bsp/yichip/yc3121-pos/SConstruct new file mode 100644 index 0000000000..8418d596c0 --- /dev/null +++ b/bsp/yichip/yc3121-pos/SConstruct @@ -0,0 +1,40 @@ +import os +import sys +import rtconfig + +if os.getenv('RTT_ROOT'): + RTT_ROOT = os.getenv('RTT_ROOT') +else: + RTT_ROOT = os.path.normpath(os.getcwd() + '/../..') + +sys.path = sys.path + [os.path.join(RTT_ROOT, 'tools')] +try: + from building import * +except: + print('Cannot found RT-Thread root directory, please check RTT_ROOT') + print(RTT_ROOT) + exit(-1) + +TARGET = 'rtthread.' + rtconfig.TARGET_EXT + +DefaultEnvironment(tools=[]) +env = Environment(tools = ['mingw'], + AS = rtconfig.AS, ASFLAGS = rtconfig.AFLAGS, + CC = rtconfig.CC, CCFLAGS = rtconfig.CFLAGS, + AR = rtconfig.AR, ARFLAGS = '-rc', + LINK = rtconfig.LINK, LINKFLAGS = rtconfig.LFLAGS) +env.PrependENVPath('PATH', rtconfig.EXEC_PATH) + +if rtconfig.PLATFORM == 'iar': + env.Replace(CCCOM = ['$CC $CCFLAGS $CPPFLAGS $_CPPDEFFLAGS $_CPPINCFLAGS -o $TARGET $SOURCES']) + env.Replace(ARFLAGS = ['']) + env.Replace(LINKCOM = env["LINKCOM"] + ' --map project.map') + +Export('RTT_ROOT') +Export('rtconfig') + +# prepare building environment +objs = PrepareBuilding(env, RTT_ROOT, has_libcpu=False) + +# make a building +DoBuilding(TARGET, objs) diff --git a/bsp/yichip/yc3121-pos/applications/SConscript b/bsp/yichip/yc3121-pos/applications/SConscript new file mode 100644 index 0000000000..6452d39145 --- /dev/null +++ b/bsp/yichip/yc3121-pos/applications/SConscript @@ -0,0 +1,9 @@ +from building import * + +cwd = GetCurrentDir() +CPPPATH = [cwd, str(Dir('#'))] +src = Glob('*.c') + +group = DefineGroup('Applications', src, depend = [''], CPPPATH = CPPPATH) + +Return('group') diff --git a/bsp/yichip/yc3121-pos/applications/main.c b/bsp/yichip/yc3121-pos/applications/main.c new file mode 100644 index 0000000000..2ee0856d85 --- /dev/null +++ b/bsp/yichip/yc3121-pos/applications/main.c @@ -0,0 +1,31 @@ +/* + * Copyright (c) 2006-2021, YICHIP Technology Co.,Ltd. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Change Logs: + * Date Author Notes + * 2021-09-09 WSY first version + */ + +#include +#include +/* defined the LED pin: PA12 */ +#define LED_PIN 2 + +int main(void) +{ + int count = 1; + /* set LED4 pin mode to output */ + rt_pin_mode(LED_PIN, PIN_MODE_OUTPUT); + + while (count++) + { + rt_pin_write(LED_PIN, PIN_HIGH); + rt_thread_mdelay(500); + rt_pin_write(LED_PIN, PIN_LOW); + rt_thread_mdelay(500); + } + + return RT_EOK; +} diff --git a/bsp/yichip/yc3121-pos/drivers/Kconfig b/bsp/yichip/yc3121-pos/drivers/Kconfig new file mode 100644 index 0000000000..e0c1ca9902 --- /dev/null +++ b/bsp/yichip/yc3121-pos/drivers/Kconfig @@ -0,0 +1,22 @@ +menu "Hardware Drivers Config" + + menu "On-chip Peripheral Drivers" + config BSP_USING_GPIO + bool "Enable GPIO" + select RT_USING_PIN + default y + + menu "UART Drivers" + config BSP_USING_UART0 + bool "Enable UART0 PA2/3(R/T)" + select RT_USING_SERIAL + default y + + config BSP_USING_UART1 + bool "Enable UART1 PC2/3(R/T)" + select RT_USING_SERIAL + default n + endmenu + endmenu + +endmenu diff --git a/bsp/yichip/yc3121-pos/drivers/SConscript b/bsp/yichip/yc3121-pos/drivers/SConscript new file mode 100644 index 0000000000..df6a78e8a8 --- /dev/null +++ b/bsp/yichip/yc3121-pos/drivers/SConscript @@ -0,0 +1,25 @@ +# RT-Thread building script for component + +from building import * + +cwd = GetCurrentDir() + +# add the general drivers. +src = Split(""" +board.c +""") + +# add gpio driver code +if GetDepend(['BSP_USING_GPIO']): + src += ['drv_gpio.c'] + +# add serial driver code +if GetDepend('BSP_USING_UART0') or GetDepend('BSP_USING_UART1') or GetDepend('BSP_USING_UART2') or GetDepend('BSP_USING_UART3'): + src += ['drv_uart.c'] + + +CPPPATH = [cwd] + +group = DefineGroup('Drivers', src, depend = [''], CPPPATH = CPPPATH) + +Return('group') diff --git a/bsp/yichip/yc3121-pos/drivers/board.c b/bsp/yichip/yc3121-pos/drivers/board.c new file mode 100644 index 0000000000..361be18882 --- /dev/null +++ b/bsp/yichip/yc3121-pos/drivers/board.c @@ -0,0 +1,57 @@ +/* + * Copyright (c) 2006-2021, YICHIP Technology Co.,Ltd. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Change Logs: + * Date Author Notes + * 2021-09-09 WSY first version + */ + +#include +#if defined(BSP_USING_EXT_SRAM) && defined(RT_USING_MEMHEAP_AS_HEAP) + static struct rt_memheap system_heap; +#endif +#define SystemCoreClock (48000000) + +static void bsp_clock_config(void) +{ + SysTick_Config(SystemCoreClock / RT_TICK_PER_SECOND); +} + +void SysTick_Handler(void) +{ + /* enter interrupt */ + rt_interrupt_enter(); + + rt_tick_increase(); + + /* leave interrupt */ + rt_interrupt_leave(); +} + +#ifdef RT_USING_SERIAL +extern int rt_hw_uart_init(void); +#endif + +void rt_hw_board_init() +{ + bsp_clock_config(); + +#if defined(RT_USING_HEAP) + rt_system_heap_init((void *)HEAP_BEGIN, (void *)HEAP_END); +#endif + + /* UART driver initialization is open by default */ +#ifdef RT_USING_SERIAL + rt_hw_uart_init(); +#endif + +#ifdef RT_USING_CONSOLE + rt_console_set_device(RT_CONSOLE_DEVICE_NAME); +#endif + +#ifdef RT_USING_COMPONENTS_INIT + rt_components_board_init(); +#endif +} diff --git a/bsp/yichip/yc3121-pos/drivers/board.h b/bsp/yichip/yc3121-pos/drivers/board.h new file mode 100644 index 0000000000..573c6454a9 --- /dev/null +++ b/bsp/yichip/yc3121-pos/drivers/board.h @@ -0,0 +1,44 @@ +/* + * Copyright (c) 2006-2021, YICHIP Technology Co.,Ltd. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Change Logs: + * Date Author Notes + * 2021-09-09 WSY first version + */ + +#ifndef BOARD_H__ +#define BOARD_H__ +#include +#include +#include "yc_gpio.h" +#include "yc_uart.h" +#include "yc_systick.h" +#include "misc.h" + +#define SRAM_BASE 0x20000 +#define SRAM_SIZE 0x10000 + +#ifdef BSP_USING_EXT_SRAM + #define EXT_SRAM_BASE SRAMM_BASE + #define EXT_SRAM_SIZE BSP_EXT_SRAM_SIZE + #define EXT_SRAM_BEGIN EXT_SRAM_BASE + #define EXT_SRAM_END (EXT_SRAM_BASE + EXT_SRAM_SIZE) +#endif + +#define SRAM_END (SRAM_BASE + SRAM_SIZE) +#if defined(__CC_ARM) || defined(__CLANG_ARM) + extern int Image$$RW_IRAM1$$ZI$$Limit; + #define HEAP_BEGIN ((void *)&Image$$RW_IRAM1$$ZI$$Limit) +#elif __ICCARM__ + #pragma section = "HEAP" + #define HEAP_BEGIN (__segment_end("HEAP")) +#else + extern int __bss_end; + #define HEAP_BEGIN ((void *)&__bss_end) +#endif +#define HEAP_END SRAM_END +#define HEAP_SIZE (HEAP_END - (rt_uint32_t)HEAP_BEGIN) +extern void rt_hw_board_init(void); +#endif diff --git a/bsp/yichip/yc3121-pos/drivers/drv_gpio.c b/bsp/yichip/yc3121-pos/drivers/drv_gpio.c new file mode 100644 index 0000000000..10ccaa548f --- /dev/null +++ b/bsp/yichip/yc3121-pos/drivers/drv_gpio.c @@ -0,0 +1,199 @@ +/* + * Copyright (c) 2006-2021, YICHIP Technology Co.,Ltd. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Change Logs: + * Date Author Notes + * 2021-09-09 WSY first version + */ + +#include +#include +#include +#include + +typedef void (*pin_callback_t)(void *args); +struct pin +{ + uint32_t package_index; + const char *name; + IRQn_Type irq; + rt_uint32_t irq_mode; + pin_callback_t callback; + void *callback_args; +}; +typedef struct pin pin_t; + +static void yc_pin_mode(rt_device_t dev, rt_base_t pin, rt_base_t mode) +{ + /* Configure GPIO_InitStructure */ + if (mode == PIN_MODE_OUTPUT) + { + /* output setting */ + GPIO_CONFIG(pin) = OUTPUT_LOW; + } + else if (mode == PIN_MODE_INPUT) + { + /* input setting: not pull. */ + GPIO_CONFIG(pin) = INPUT; + } + else if (mode == PIN_MODE_INPUT_PULLUP) + { + /* input setting: pull up. */ + GPIO_CONFIG(pin) = PULL_UP; + } + else if (mode == PIN_MODE_INPUT_PULLDOWN) + { + /* input setting: pull down. */ + GPIO_CONFIG(pin) = PULL_DOWN; + } + else if (mode == PIN_MODE_OUTPUT_OD) + { + /* output setting: od. */ + GPIO_CONFIG(pin) = PULL_UP; + } +} + +static void yc_pin_write(rt_device_t dev, rt_base_t pin, rt_base_t value) +{ + if (value) + { + GPIO_CONFIG(pin) = OUTPUT_HIGH; + } + else + { + GPIO_CONFIG(pin) = OUTPUT_LOW; + } +} + +static int yc_pin_read(rt_device_t dev, rt_base_t pin) +{ + return GPIO_IN(pin / 16) & (1 << (pin % 16)) ? 1 : 0; +} + +static rt_err_t yc_pin_attach_irq(struct rt_device *device, + rt_int32_t pin, + rt_uint32_t mode, + pin_callback_t cb, + void *args) +{ + pin_t *index; + rt_base_t level; + if (index == RT_NULL) + { + return RT_EINVAL; + } + level = rt_hw_interrupt_disable(); + index->callback = cb; + index->callback_args = args; + index->irq_mode = mode; + + rt_hw_interrupt_enable(level); + return RT_EOK; +} + +static rt_err_t yc_pin_detach_irq(struct rt_device *device, rt_int32_t pin) +{ + pin_t *index; + rt_base_t level; + if (index == RT_NULL) + { + return RT_EINVAL; + } + level = rt_hw_interrupt_disable(); + index->callback = 0; + index->callback_args = 0; + index->irq_mode = 0; + rt_hw_interrupt_enable(level); + return RT_EOK; +} + +static rt_err_t yc_pin_irq_enable(struct rt_device *device, + rt_base_t pin, + rt_uint32_t enabled) +{ + pin_t *index; + rt_base_t level = 0; + if (index == RT_NULL) + { + return RT_EINVAL; + } + if (enabled == PIN_IRQ_ENABLE) + { + switch (index->irq_mode) + { + case PIN_IRQ_MODE_RISING: + + break; + case PIN_IRQ_MODE_FALLING: + + break; + case PIN_IRQ_MODE_RISING_FALLING: + + break; + case PIN_IRQ_MODE_HIGH_LEVEL: + GPIO_CONFIG(pin) = PULL_DOWN; + GPIO_TRIG_MODE(pin/16) &= (1 << (pin % 16)); + break; + case PIN_IRQ_MODE_LOW_LEVEL: + GPIO_CONFIG(pin) = PULL_UP; + GPIO_TRIG_MODE(pin/16) |= (1 << (pin % 16)); + break; + default: + rt_hw_interrupt_enable(level); + return RT_EINVAL; + } + + level = rt_hw_interrupt_disable(); + NVIC_EnableIRQ(index->irq); + GPIO_INTR_EN(pin / 16) |= (1 << (pin % 16)); + rt_hw_interrupt_enable(level); + } + else if (enabled == PIN_IRQ_DISABLE) + { + NVIC_DisableIRQ(index->irq); + GPIO_INTR_EN(pin / 16) &= ~(1 << (pin % 16)); + } + else + { + return RT_ENOSYS; + } + return RT_EOK; +} + +const static struct rt_pin_ops yc3121_pin_ops = + { + yc_pin_mode, + yc_pin_write, + yc_pin_read, + yc_pin_attach_irq, + yc_pin_detach_irq, + yc_pin_irq_enable, + RT_NULL, +}; + +int rt_hw_pin_init(void) +{ + int result; + result = rt_device_pin_register("pin", &yc3121_pin_ops, RT_NULL); + return result; +} +INIT_BOARD_EXPORT(rt_hw_pin_init); + +void GPIOA_Handler(void) +{ + int i; + + /* enter interrupt */ + rt_interrupt_enter(); + + for (i = 0; i < 48; i++) + { + // if(GPIO_IN(pin / 16) & (1 << (pin % 16))) + + } + + /* leave interrupt */ + rt_interrupt_leave(); +} diff --git a/bsp/yichip/yc3121-pos/drivers/drv_gpio.h b/bsp/yichip/yc3121-pos/drivers/drv_gpio.h new file mode 100644 index 0000000000..2f0bd6ce66 --- /dev/null +++ b/bsp/yichip/yc3121-pos/drivers/drv_gpio.h @@ -0,0 +1,16 @@ +/* + * Copyright (c) 2006-2021, YICHIP Technology Co.,Ltd. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Change Logs: + * Date Author Notes + * 2021-09-09 WSY first version + */ + +#ifndef DRV_GPIO_H__ +#define DRV_GPIO_H__ + +int rt_hw_pin_init(void); + +#endif diff --git a/bsp/yichip/yc3121-pos/drivers/drv_uart.c b/bsp/yichip/yc3121-pos/drivers/drv_uart.c new file mode 100644 index 0000000000..195be621eb --- /dev/null +++ b/bsp/yichip/yc3121-pos/drivers/drv_uart.c @@ -0,0 +1,194 @@ +/* + * Copyright (c) 2006-2021, YICHIP Technology Co.,Ltd. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Change Logs: + * Date Author Notes + * 2021-09-09 WSY first version + */ + +#include +#include +#include + +struct yc3121_uart +{ + UART_TypeDef uart; + IRQn_Type irq; +}; + +static rt_err_t yc3121_uart_configure(struct rt_serial_device *serial, + struct serial_configure *cfg) +{ + struct yc3121_uart *uart; + UART_InitTypeDef UART_initStruct; + RT_ASSERT(serial != RT_NULL); + RT_ASSERT(cfg != RT_NULL); + uart = (struct yc3121_uart *)serial->parent.user_data; + NVIC_DisableIRQ(uart->irq); + UART_initStruct.BaudRate = cfg->baud_rate; + UART_initStruct.FlowCtrl = FlowCtrl_None ; + UART_initStruct.Mode = Mode_duplex; + + switch (cfg->data_bits) + { + case DATA_BITS_9: + UART_initStruct.DataBits = Databits_9b; + break; + default: + UART_initStruct.DataBits = Databits_8b; + break; + } + switch (cfg->stop_bits) + { + case STOP_BITS_2: + UART_initStruct.StopBits = StopBits_2; + break; + default: + UART_initStruct.StopBits = StopBits_1; + break; + } + switch (cfg->parity) + { + case PARITY_ODD: + UART_initStruct.Parity = Parity_Odd; + break; + case PARITY_EVEN: + UART_initStruct.Parity = Parity_Even; + break; + default: + UART_initStruct.Parity = Parity_None; + break; + } + UART_Init(uart->uart, &UART_initStruct); + return RT_EOK; +} + +static rt_err_t yc3121_uart_control(struct rt_serial_device *serial, + int cmd, void *arg) +{ + struct yc3121_uart *uart; + RT_ASSERT(serial != RT_NULL); + uart = (struct yc3121_uart *)serial->parent.user_data; + switch (cmd) + { + case RT_DEVICE_CTRL_CLR_INT: + /* disable rx irq */ + UART_SetRxITNum(uart->uart, 0); + NVIC_DisableIRQ(uart->irq); + break; + case RT_DEVICE_CTRL_SET_INT: + /* enable rx irq */ + UART_SetRxITNum(uart->uart, 1); + UART_ITConfig(uart->uart, UART_IT_RX, ENABLE); + NVIC_EnableIRQ(uart->irq); + break; + } + return RT_EOK; +} + +static int yc3121_uart_putc(struct rt_serial_device *serial, char c) +{ + struct yc3121_uart *uart; + RT_ASSERT(serial != RT_NULL); + uart = (struct yc3121_uart *)serial->parent.user_data; + while (UART_IsUARTBusy(uart->uart)); + UART_SendData(uart->uart, c); + return 1; +} + +static int yc3121_uart_getc(struct rt_serial_device *serial) +{ + int ch; + struct yc3121_uart *uart; + RT_ASSERT(serial != RT_NULL); + uart = (struct yc3121_uart *)serial->parent.user_data; + ch = -1; + if (UART_ReceiveDataLen(uart->uart) != 0) + { + ch = UART_ReceiveData(uart->uart); + } + return ch; +} + +static const struct rt_uart_ops yc3121_uart_ops = +{ + yc3121_uart_configure, + yc3121_uart_control, + yc3121_uart_putc, + yc3121_uart_getc, +}; + +#if defined(BSP_USING_UART0) +/* UART0 device driver structure */ +static struct yc3121_uart uart0; +static struct rt_serial_device serial0; +void UART0_IRQHandler(void) +{ + /* enter interrupt */ + rt_interrupt_enter(); + + /* UART in mode Receiver */ + if (UART_GetITIdentity(uart0.uart) == UART_IT_RX) + { + rt_hw_serial_isr(&serial0, RT_SERIAL_EVENT_RX_IND); + } + /* leave interrupt */ + rt_interrupt_leave(); +} +#endif /* BSP_USING_UART0 */ + +#if defined(BSP_USING_UART1) +/* UART1 device driver structure */ +static struct yc3121_uart uart1; +static struct rt_serial_device serial1; +void UART1_IRQHandler(void) +{ + /* enter interrupt */ + rt_interrupt_enter(); + + /* UART in mode Receiver */ + if (UART_GetITIdentity(uart1.uart) == UART_IT_RX) + { + rt_hw_serial_isr(&serial1, RT_SERIAL_EVENT_RX_IND); + } + /* leave interrupt */ + rt_interrupt_leave(); +} +#endif /* BSP_USING_UART1 */ + +int rt_hw_uart_init(void) +{ + struct yc3121_uart *uart; + struct serial_configure config = RT_SERIAL_CONFIG_DEFAULT; +#ifdef BSP_USING_UART0 + + GPIO_CONFIG(1) = UART0_TXD; + GPIO_CONFIG(0) = UART0_RXD; + uart = &uart0; + uart->uart = UART0; + uart->irq = UART0_IRQn; + serial0.ops = &yc3121_uart_ops; + serial0.config = config; + /* register UART0 device */ + rt_hw_serial_register(&serial0, RT_CONSOLE_DEVICE_NAME, + RT_DEVICE_FLAG_RDWR | RT_DEVICE_FLAG_INT_RX, + uart); +#endif /* BSP_USING_UART0 */ +#ifdef BSP_USING_UART1 + GPIO_CONFIG(1) = UART1_TXD; + GPIO_CONFIG(0) = UART1_RXD; + uart = &uart1; + uart->uart = UART1; + uart->irq = UART1_IRQn; + serial1.ops = &yc3121_uart_ops; + serial1.config = config; + /* register UART1 device */ + rt_hw_serial_register(&serial1, "uart1", + RT_DEVICE_FLAG_RDWR | RT_DEVICE_FLAG_INT_RX, + uart); +#endif /* BSP_USING_UART1 */ + return 0; +} +INIT_BOARD_EXPORT(rt_hw_uart_init); diff --git a/bsp/yichip/yc3121-pos/drivers/drv_uart.h b/bsp/yichip/yc3121-pos/drivers/drv_uart.h new file mode 100644 index 0000000000..b4f84a1d93 --- /dev/null +++ b/bsp/yichip/yc3121-pos/drivers/drv_uart.h @@ -0,0 +1,16 @@ +/* + * Copyright (c) 2006-2021, YICHIP Technology Co.,Ltd. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Change Logs: + * Date Author Notes + * 2021-09-09 WSY first version + */ + +#ifndef DRV_UART_H__ +#define DRV_UART_H__ + +int rt_hw_uart_init(void); + +#endif diff --git a/bsp/yichip/yc3121-pos/drivers/linker_scripts/link.icf b/bsp/yichip/yc3121-pos/drivers/linker_scripts/link.icf new file mode 100644 index 0000000000..f58af36588 --- /dev/null +++ b/bsp/yichip/yc3121-pos/drivers/linker_scripts/link.icf @@ -0,0 +1,32 @@ +/*###ICF### Section handled by ICF editor, don't touch! ****/ +/*-Editor annotation file-*/ +/* IcfEditorFile="$TOOLKIT_DIR$\config\ide\IcfEditor\cortex_v1_0.xml" */ +/*-Specials-*/ +define symbol __ICFEDIT_intvec_start__ = 0x1000200; +/*-Memory Regions-*/ +define symbol __ICFEDIT_region_ROM_start__ = 0x1000200; +define symbol __ICFEDIT_region_ROM_end__ = 0x1ffffff; +define symbol __ICFEDIT_region_RAM_start__ = 0x20000; +define symbol __ICFEDIT_region_RAM_end__ = 0x2FFFF; +/*-Sizes-*/ +define symbol __ICFEDIT_size_cstack__ = 0xF800; +define symbol __ICFEDIT_size_heap__ = 0x800; +/**** End of ICF editor section. ###ICF###*/ + + +define memory mem with size = 4G; +define region ROM_region = mem:[from __ICFEDIT_region_ROM_start__ to __ICFEDIT_region_ROM_end__]; +define region RAM_region = mem:[from __ICFEDIT_region_RAM_start__ to __ICFEDIT_region_RAM_end__]; + +define block CSTACK with alignment = 8, size = __ICFEDIT_size_cstack__ { }; +define block HEAP with alignment = 8, size = __ICFEDIT_size_heap__ { }; + +initialize by copy { readwrite }; +//initialize by copy with packing = none { section __DLIB_PERTHREAD }; // Required in a multi-threaded application +do not initialize { section .noinit }; + +place at address mem:__ICFEDIT_intvec_start__ { readonly section .intvec }; + +place in ROM_region { readonly }; +place in RAM_region { readwrite, + block CSTACK, block HEAP }; \ No newline at end of file diff --git a/bsp/yichip/yc3121-pos/drivers/linker_scripts/link.lds b/bsp/yichip/yc3121-pos/drivers/linker_scripts/link.lds new file mode 100644 index 0000000000..177040fbd0 --- /dev/null +++ b/bsp/yichip/yc3121-pos/drivers/linker_scripts/link.lds @@ -0,0 +1,161 @@ +/* Linker script to configure memory regions. + * Need modifying for a specific board. + * FLASH.ORIGIN: starting address of flash + * FLASH.LENGTH: length of flash + * RAM.ORIGIN: starting address of RAM bank 0 + * RAM.LENGTH: length of RAM bank 0 + */ +MEMORY +{ + FLASH (rx) : ORIGIN = 0x1000000, LENGTH = 0x80000 /* 512K */ + RAM (rwx) : ORIGIN = 0x20000, LENGTH = 0x10000 /* 64K */ +} + +/* Linker script to place sections and symbol values. Should be used together + * with other linker script that defines memory regions FLASH and RAM. + * It references following symbols, which must be defined in code: + * Reset_Handler : Entry of reset handler + * + * It defines following symbols, which code can use without definition: + * __exidx_start + * __exidx_end + * __copy_table_start__ + * __copy_table_end__ + * __zero_table_start__ + * __zero_table_end__ + * __etext + * __data_start__ + * __preinit_array_start + * __preinit_array_end + * __init_array_start + * __init_array_end + * __fini_array_start + * __fini_array_end + * __data_end__ + * __bss_start__ + * __bss_end__ + * __end__ + * end + * __HeapLimit + * __StackLimit + * __StackTop + * __stack + */ +ENTRY(Reset_Handler) + +SECTIONS +{ + .text : + { + *flash_start*.o + *(.text*) + + KEEP(*(.init)) + KEEP(*(.fini)) + + /* .ctors */ + *crtbegin.o(.ctors) + *crtbegin?.o(.ctors) + *(EXCLUDE_FILE(*crtend?.o *crtend.o) .ctors) + *(SORT(.ctors.*)) + *(.ctors) + + /* .dtors */ + *crtbegin.o(.dtors) + *crtbegin?.o(.dtors) + *(EXCLUDE_FILE(*crtend?.o *crtend.o) .dtors) + *(SORT(.dtors.*)) + *(.dtors) + + *(.rodata*) + + KEEP(*(.eh_frame*)) + } > FLASH + + + + .ARM.extab : + { + *(.ARM.extab* .gnu.linkonce.armextab.*) + } > FLASH + + + .ARM.exidx : + { + *(.ARM.exidx* .gnu.linkonce.armexidx.*) + } > FLASH + + . = ALIGN(4); + __exidx_start = .; + + __etext = .; + + .data : AT (__etext) + { + __data_start__ = .; + *(vtable) + *(.data*) + + . = ALIGN(4); + /* preinit data */ + PROVIDE_HIDDEN (__preinit_array_start = .); + KEEP(*(.preinit_array)) + PROVIDE_HIDDEN (__preinit_array_end = .); + + . = ALIGN(4); + /* init data */ + PROVIDE_HIDDEN (__init_array_start = .); + KEEP(*(SORT(.init_array.*))) + KEEP(*(.init_array)) + PROVIDE_HIDDEN (__init_array_end = .); + + + . = ALIGN(4); + /* finit data */ + PROVIDE_HIDDEN (__fini_array_start = .); + KEEP(*(SORT(.fini_array.*))) + KEEP(*(.fini_array)) + PROVIDE_HIDDEN (__fini_array_end = .); + + KEEP(*(.jcr*)) + . = ALIGN(4); + /* All data end */ + __data_end__ = .; + + } > RAM + + .bss : + { + . = ALIGN(4); + __bss_start__ = .; + *(.bss*) + *(COMMON) + . = ALIGN(4); + __bss_end__ = .; + } > RAM + + .heap (COPY): + { + __end__ = .; + PROVIDE(end = .); + *(.heap*) + __HeapLimit = .; + } > RAM + + /* .stack_dummy section doesn't contains any symbols. It is only + * used for linker to calculate size of stack sections, and assign + * values to stack symbols later */ + .stack_dummy (COPY): + { + *(.stack*) + } > RAM + + /* Set stack top to end of RAM, and stack limit move down by + * size of stack_dummy section */ + __StackTop = ORIGIN(RAM) + LENGTH(RAM); + __StackLimit = __StackTop - SIZEOF(.stack_dummy); + PROVIDE(__stack = __StackTop); + + /* Check if data + heap + stack exceeds RAM limit */ + ASSERT(__StackLimit >= __HeapLimit, "region RAM overflowed with stack") +} \ No newline at end of file diff --git a/bsp/yichip/yc3121-pos/drivers/linker_scripts/link.sct b/bsp/yichip/yc3121-pos/drivers/linker_scripts/link.sct new file mode 100644 index 0000000000..71ad394af9 --- /dev/null +++ b/bsp/yichip/yc3121-pos/drivers/linker_scripts/link.sct @@ -0,0 +1,32 @@ +; ************************************************************* +; *** Scatter-Loading Description File generated by uVision *** +; ************************************************************* + +LR_IROM1 0x00000000 0x0007fff { ; load region size_region + ER_IROM1 0x00000000 0x00007fff { ; load address = execution address + startup.o (RESET, +First) +; startup.o (.text,+RO) +; *(InRoot$$Sections) + } +} + +LR_IROM3 0x1000200 0x200{ + ER_IROM3 0x1000200 { + flash_start.o (|.flash_start|,+RO) + } + ER_IROM3_1 0x1000340 { + startup.o (|.INIT_STACK_HEAP|,+RO) + } +} + +LR_IROM4 0x1000400 0x1000000{ + ER_IROM4 0x1000400 { + *(InRoot$$Sections) + .ANY (+RO) + } + + RW_IRAM1 0x00020000 0x010000 { ; RW data + .ANY (+RW +ZI) + } +} + diff --git a/bsp/yichip/yc3121-pos/figures/YC3121-pos.jpg b/bsp/yichip/yc3121-pos/figures/YC3121-pos.jpg new file mode 100644 index 0000000000..fa30094ed6 Binary files /dev/null and b/bsp/yichip/yc3121-pos/figures/YC3121-pos.jpg differ diff --git a/bsp/yichip/yc3121-pos/project.ewd b/bsp/yichip/yc3121-pos/project.ewd new file mode 100644 index 0000000000..52cc221b07 --- /dev/null +++ b/bsp/yichip/yc3121-pos/project.ewd @@ -0,0 +1,2834 @@ + + + 3 + + rt-thread + + ARM + + 1 + + C-SPY + 2 + + 29 + 1 + 1 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + ARMSIM_ID + 2 + + 1 + 1 + 1 + + + + + + + + CADI_ID + 2 + + 0 + 1 + 1 + + + + + + + + + CMSISDAP_ID + 2 + + 4 + 1 + 1 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + GDBSERVER_ID + 2 + + 0 + 1 + 1 + + + + + + + + + + + IJET_ID + 2 + + 8 + 1 + 1 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + JLINK_ID + 2 + + 16 + 1 + 1 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + LMIFTDI_ID + 2 + + 2 + 1 + 1 + + + + + + + + + + PEMICRO_ID + 2 + + 3 + 1 + 1 + + + + + + + + STLINK_ID + 2 + + 4 + 1 + 1 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + THIRDPARTY_ID + 2 + + 0 + 1 + 1 + + + + + + + + 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$EW_DIR$\common\plugins\CodeCoverage\CodeCoverage.ENU.ewplugin + 1 + + + $EW_DIR$\common\plugins\Orti\Orti.ENU.ewplugin + 0 + + + $EW_DIR$\common\plugins\TargetAccessServer\TargetAccessServer.ENU.ewplugin + 0 + + + $EW_DIR$\common\plugins\uCProbe\uCProbePlugin.ENU.ewplugin + 0 + + + + + Release + + ARM + + 0 + + C-SPY + 2 + + 29 + 1 + 0 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + ARMSIM_ID + 2 + + 1 + 1 + 0 + + + + + + + + CADI_ID + 2 + + 0 + 1 + 0 + + + + + + + + + CMSISDAP_ID + 2 + + 4 + 1 + 0 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + GDBSERVER_ID + 2 + + 0 + 1 + 0 + + + + + + + + + + + IJET_ID + 2 + + 8 + 1 + 0 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + JLINK_ID + 2 + + 16 + 1 + 0 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + LMIFTDI_ID + 2 + + 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$TOOLKIT_DIR$\plugins\rtos\uCOS-II\uCOS-II-286-KA-CSpy.ewplugin + 0 + + + $TOOLKIT_DIR$\plugins\rtos\uCOS-II\uCOS-II-KA-CSpy.ewplugin + 0 + + + $TOOLKIT_DIR$\plugins\rtos\uCOS-III\uCOS-III-KA-CSpy.ewplugin + 0 + + + $EW_DIR$\common\plugins\CodeCoverage\CodeCoverage.ENU.ewplugin + 1 + + + $EW_DIR$\common\plugins\Orti\Orti.ENU.ewplugin + 0 + + + $EW_DIR$\common\plugins\TargetAccessServer\TargetAccessServer.ENU.ewplugin + 0 + + + $EW_DIR$\common\plugins\uCProbe\uCProbePlugin.ENU.ewplugin + 0 + + + + diff --git a/bsp/yichip/yc3121-pos/project.ewp b/bsp/yichip/yc3121-pos/project.ewp new file mode 100644 index 0000000000..2f7701c186 --- /dev/null +++ b/bsp/yichip/yc3121-pos/project.ewp @@ -0,0 +1,2223 @@ + + 3 + + rt-thread + + ARM + + 1 + + General + 3 + + 29 + 1 + 1 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + ICCARM + 2 + + 34 + 1 + 1 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + 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$PROJ_DIR$\..\..\..\components\drivers\src\workqueue.c + + + $PROJ_DIR$\..\..\..\components\drivers\src\dataqueue.c + + + $PROJ_DIR$\..\..\..\components\drivers\src\ringblk_buf.c + + + + Drivers + + $PROJ_DIR$\drivers\drv_gpio.c + + + $PROJ_DIR$\drivers\drv_uart.c + + + $PROJ_DIR$\drivers\board.c + + + + Finsh + + $PROJ_DIR$\..\..\..\components\finsh\shell.c + + + $PROJ_DIR$\..\..\..\components\finsh\msh.c + + + $PROJ_DIR$\..\..\..\components\finsh\cmd.c + + + + Kernel + + $PROJ_DIR$\..\..\..\src\kservice.c + + + $PROJ_DIR$\..\..\..\src\mempool.c + + + $PROJ_DIR$\..\..\..\src\idle.c + + + $PROJ_DIR$\..\..\..\src\memheap.c + + + $PROJ_DIR$\..\..\..\src\scheduler.c + + + $PROJ_DIR$\..\..\..\src\components.c + + + $PROJ_DIR$\..\..\..\src\device.c + + + $PROJ_DIR$\..\..\..\src\object.c + + + $PROJ_DIR$\..\..\..\src\ipc.c + + + $PROJ_DIR$\..\..\..\src\thread.c + + + $PROJ_DIR$\..\..\..\src\irq.c + + + $PROJ_DIR$\..\..\..\src\mem.c + + + $PROJ_DIR$\..\..\..\src\clock.c + + + $PROJ_DIR$\..\..\..\src\timer.c + + + + libc + + $PROJ_DIR$\..\..\..\components\libc\compilers\common\time.c + + + + Libraries + + $PROJ_DIR$\Libraries\sdk\yc_dma.c + + + $PROJ_DIR$\Libraries\core\system.c + + + $PROJ_DIR$\Libraries\sdk\yc_systick.c + + + $PROJ_DIR$\Libraries\startup\flash_start_iar.s + + + $PROJ_DIR$\Libraries\core\bt_code_boot.c + + + $PROJ_DIR$\Libraries\sdk\yc_wdt.c + + + $PROJ_DIR$\Libraries\sdk\yc_gpio.c + + + $PROJ_DIR$\Libraries\core\misc.c + + + $PROJ_DIR$\Libraries\sdk\yc_uart.c + + + + utestcases + + diff --git a/bsp/yichip/yc3121-pos/project.eww b/bsp/yichip/yc3121-pos/project.eww new file mode 100644 index 0000000000..c2cb02eb1e --- /dev/null +++ b/bsp/yichip/yc3121-pos/project.eww @@ -0,0 +1,10 @@ + + + + + $WS_DIR$\project.ewp + + + + + diff --git a/bsp/yichip/yc3121-pos/project.uvoptx b/bsp/yichip/yc3121-pos/project.uvoptx new file mode 100644 index 0000000000..3f3ca22b61 --- /dev/null +++ b/bsp/yichip/yc3121-pos/project.uvoptx @@ -0,0 +1,793 @@ + + + + 1.0 + +
### uVision Project, (C) Keil Software
+ + + *.c + *.s*; *.src; *.a* + *.obj; *.o + *.lib + *.txt; *.h; *.inc + *.plm + *.cpp + 0 + + + + 0 + 0 + + + + rt-thread + 0x4 + ARM-ADS + + 12000000 + + 1 + 1 + 0 + 1 + 0 + + + 1 + 65535 + 0 + 0 + 0 + + + 79 + 66 + 8 + .\build\ + + + 1 + 1 + 1 + 0 + 1 + 1 + 0 + 1 + 0 + 0 + 0 + 0 + + + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 0 + 0 + + + 1 + 0 + 1 + + 7 + + 0 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 0 + 1 + 1 + 1 + 1 + 0 + 0 + 1 + 0 + 0 + 4 + + + + + + + + + + + Segger\JL2CM3.dll + + + + 0 + UL2CM3 + UL2CM3(-S0 -C0 -P0 -FD20000000 -FC1000) + + + 0 + JL2CM3 + -U788594195 -O78 -S2 -ZTIFSpeedSel5000 -A0 -C0 -JU1 -JI127.0.0.1 -JP0 -RST0 -N00("ARM CoreSight SW-DP") -D00(0BB11477) -L00(0) -TO18 -TC10000000 -TP21 -TDS8004 -TDT0 -TDC1F -TIEFFFFFFFF -TIP8 -TB1 -TFE0 -FO31 -FD20000 -FCA000 -FN0 + + + + + 0 + + + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + + + + 0 + 0 + 0 + + + + + + + + + + + + + Applications + 1 + 0 + 0 + 0 + + 1 + 1 + 1 + 0 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+ 1 + 0 + 0 + 0 + ..\..\..\src\components.c + components.c + 0 + 0 + + + 6 + 23 + 1 + 0 + 0 + 0 + ..\..\..\src\scheduler.c + scheduler.c + 0 + 0 + + + 6 + 24 + 1 + 0 + 0 + 0 + ..\..\..\src\idle.c + idle.c + 0 + 0 + + + 6 + 25 + 1 + 0 + 0 + 0 + ..\..\..\src\clock.c + clock.c + 0 + 0 + + + 6 + 26 + 1 + 0 + 0 + 0 + ..\..\..\src\device.c + device.c + 0 + 0 + + + 6 + 27 + 1 + 0 + 0 + 0 + ..\..\..\src\mempool.c + mempool.c + 0 + 0 + + + 6 + 28 + 1 + 0 + 0 + 0 + ..\..\..\src\kservice.c + kservice.c + 0 + 0 + + + 6 + 29 + 1 + 0 + 0 + 0 + ..\..\..\src\ipc.c + ipc.c + 0 + 0 + + + 6 + 30 + 1 + 0 + 0 + 0 + ..\..\..\src\timer.c + timer.c + 0 + 0 + + + 6 + 31 + 1 + 0 + 0 + 0 + ..\..\..\src\object.c + object.c + 0 + 0 + + + 6 + 32 + 1 + 0 + 0 + 0 + ..\..\..\src\memheap.c + memheap.c + 0 + 0 + + + 6 + 33 + 1 + 0 + 0 + 0 + ..\..\..\src\irq.c + irq.c + 0 + 0 + + + 6 + 34 + 1 + 0 + 0 + 0 + ..\..\..\src\thread.c + thread.c + 0 + 0 + + + 6 + 35 + 1 + 0 + 0 + 0 + ..\..\..\src\mem.c + mem.c + 0 + 0 + + + + + libc + 0 + 0 + 0 + 0 + + 7 + 36 + 1 + 0 + 0 + 0 + ..\..\..\components\libc\compilers\common\time.c + time.c + 0 + 0 + + + + + Libraries + 1 + 0 + 0 + 0 + + 8 + 37 + 1 + 0 + 0 + 0 + Libraries\sdk\yc_wdt.c + yc_wdt.c + 0 + 0 + + + 8 + 38 + 1 + 0 + 0 + 0 + Libraries\sdk\yc_uart.c + yc_uart.c + 0 + 0 + + + 8 + 39 + 1 + 0 + 0 + 0 + Libraries\sdk\yc_dma.c + yc_dma.c + 0 + 0 + + + 8 + 40 + 2 + 0 + 0 + 0 + Libraries\startup\flash_start.s + flash_start.s + 0 + 0 + + + 8 + 41 + 1 + 0 + 0 + 0 + Libraries\core\system.c + system.c + 0 + 0 + + + 8 + 42 + 1 + 0 + 0 + 0 + Libraries\sdk\yc_gpio.c + yc_gpio.c + 0 + 0 + + + 8 + 43 + 1 + 0 + 0 + 0 + Libraries\core\misc.c + misc.c + 0 + 0 + + + 8 + 44 + 2 + 0 + 0 + 0 + Libraries\startup\startup.s + startup.s + 0 + 0 + + + 8 + 45 + 1 + 0 + 0 + 0 + Libraries\sdk\yc_systick.c + yc_systick.c + 0 + 0 + + + 8 + 46 + 1 + 0 + 0 + 0 + Libraries\core\bt_code_boot.c + bt_code_boot.c + 0 + 0 + + + + diff --git a/bsp/yichip/yc3121-pos/project.uvprojx b/bsp/yichip/yc3121-pos/project.uvprojx new file mode 100644 index 0000000000..81b455d47b --- /dev/null +++ b/bsp/yichip/yc3121-pos/project.uvprojx @@ -0,0 +1,661 @@ + + + + 2.1 + +
### uVision Project, (C) Keil Software
+ + + + rt-thread + 0x4 + ARM-ADS + 5060750::V5.06 update 6 (build 750)::ARMCC + 0 + + + ARMCM0 + ARM + ARM.CMSIS.5.3.0 + http://www.keil.com/pack/ + IRAM(0x20000000,0x00020000) IROM(0x00000000,0x00040000) CPUTYPE("Cortex-M0") CLOCK(12000000) ESEL ELITTLE + + + UL2CM3(-S0 -C0 -P0 -FD20000000 -FC1000) + 0 + $$Device:ARMCM0$Device\ARM\ARMCM0\Include\ARMCM0.h + + + + + + + + + + $$Device:ARMCM0$Device\ARM\SVD\ARMCM0.svd + 0 + 0 + + + + + + + 0 + 0 + 0 + 0 + 1 + + .\build\keil\Obj\ + rtthread + 1 + 0 + 1 + 1 + 1 + .\build\ + 1 + 0 + 0 + + 0 + 0 + + + 0 + 0 + 0 + 0 + + + 0 + 0 + + + 0 + 0 + 0 + 0 + + + 1 + 0 + fromelf.exe --text -a -c --output=@L_asm.txt "!L" + + 0 + 0 + 0 + 0 + + 0 + + + + 0 + 0 + 0 + 0 + 0 + 1 + 0 + 0 + 0 + 0 + 3 + + + 1 + + + SARMCM3.DLL + + DARMCM1.DLL + -pCM0 + SARMCM3.DLL + + TARMCM1.DLL + -pCM0 + + + + 1 + 0 + 0 + 0 + 16 + + + + + 1 + 0 + 0 + 1 + 1 + 4100 + + 0 + Segger\JL2CM3.dll + "" () + + + + + 0 + + + + 0 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 0 + 1 + 1 + 0 + 1 + 1 + 0 + 0 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 0 + 0 + "Cortex-M0" + + 0 + 0 + 0 + 1 + 1 + 0 + 0 + 0 + 0 + 0 + 8 + 0 + 1 + 0 + 0 + 3 + 3 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 1 + 0 + 0 + 0 + 0 + 1 + 0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x20000000 + 0x20000 + + + 1 + 0x0 + 0x40000 + + + 0 + 0x0 + 0x0 + + + 1 + 0x0 + 0x0 + + + 1 + 0x0 + 0x0 + + + 1 + 0x0 + 0x0 + + + 1 + 0x0 + 0x40000 + + + 1 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x20000000 + 0x20000 + + + 0 + 0x0 + 0x0 + + + + + + 1 + 1 + 0 + 0 + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + + + __RTTHREAD__, __CLK_TCK=RT_TICK_PER_SECOND + + applications;.;..\..\..\libcpu\arm\common;..\..\..\libcpu\arm\cortex-m0;..\..\..\components\drivers\include;..\..\..\components\drivers\include;..\..\..\components\drivers\include;drivers;..\..\..\components\finsh;.;..\..\..\include;..\..\..\components\libc\compilers\common;..\..\..\components\libc\compilers\common\none-gcc;Libraries\sdk;Libraries\core;Libraries;..\..\..\examples\utest\testcases\kernel + + + + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + + + + + + + + + 0 + 0 + 0 + 0 + 1 + 0 + 0x00000000 + 0x20000000 + + .\drivers\linker_scripts\link.sct + + + + + + + + + + + Applications + + + main.c + 1 + applications\main.c + + + + + CPU + + + showmem.c + 1 + ..\..\..\libcpu\arm\common\showmem.c + + + div0.c + 1 + ..\..\..\libcpu\arm\common\div0.c + + + backtrace.c + 1 + ..\..\..\libcpu\arm\common\backtrace.c + + + cpuport.c + 1 + ..\..\..\libcpu\arm\cortex-m0\cpuport.c + + + context_rvds.S + 2 + ..\..\..\libcpu\arm\cortex-m0\context_rvds.S + + + + + DeviceDrivers + + + pin.c + 1 + ..\..\..\components\drivers\misc\pin.c + + + serial.c + 1 + ..\..\..\components\drivers\serial\serial.c + + + ringblk_buf.c + 1 + ..\..\..\components\drivers\src\ringblk_buf.c + + + completion.c + 1 + ..\..\..\components\drivers\src\completion.c + + + workqueue.c + 1 + ..\..\..\components\drivers\src\workqueue.c + + + dataqueue.c + 1 + ..\..\..\components\drivers\src\dataqueue.c + + + ringbuffer.c + 1 + ..\..\..\components\drivers\src\ringbuffer.c + + + waitqueue.c + 1 + ..\..\..\components\drivers\src\waitqueue.c + + + pipe.c + 1 + ..\..\..\components\drivers\src\pipe.c + + + + + Drivers + + + drv_gpio.c + 1 + drivers\drv_gpio.c + + + drv_uart.c + 1 + drivers\drv_uart.c + + + board.c + 1 + drivers\board.c + + + + + Finsh + + + shell.c + 1 + ..\..\..\components\finsh\shell.c + + + msh.c + 1 + ..\..\..\components\finsh\msh.c + + + cmd.c + 1 + ..\..\..\components\finsh\cmd.c + + + + + Kernel + + + components.c + 1 + ..\..\..\src\components.c + + + scheduler.c + 1 + ..\..\..\src\scheduler.c + + + idle.c + 1 + ..\..\..\src\idle.c + + + clock.c + 1 + ..\..\..\src\clock.c + + + device.c + 1 + ..\..\..\src\device.c + + + mempool.c + 1 + ..\..\..\src\mempool.c + + + kservice.c + 1 + ..\..\..\src\kservice.c + + + ipc.c + 1 + ..\..\..\src\ipc.c + + + timer.c + 1 + ..\..\..\src\timer.c + + + object.c + 1 + ..\..\..\src\object.c + + + memheap.c + 1 + ..\..\..\src\memheap.c + + + irq.c + 1 + ..\..\..\src\irq.c + + + thread.c + 1 + ..\..\..\src\thread.c + + + mem.c + 1 + ..\..\..\src\mem.c + + + + + libc + + + time.c + 1 + ..\..\..\components\libc\compilers\common\time.c + + + + + Libraries + + + yc_wdt.c + 1 + Libraries\sdk\yc_wdt.c + + + yc_uart.c + 1 + Libraries\sdk\yc_uart.c + + + yc_dma.c + 1 + Libraries\sdk\yc_dma.c + + + flash_start.s + 2 + Libraries\startup\flash_start.s + + + system.c + 1 + Libraries\core\system.c + + + yc_gpio.c + 1 + Libraries\sdk\yc_gpio.c + + + misc.c + 1 + Libraries\core\misc.c + + + startup.s + 2 + Libraries\startup\startup.s + + + yc_systick.c + 1 + Libraries\sdk\yc_systick.c + + + bt_code_boot.c + 1 + Libraries\core\bt_code_boot.c + + + + + + + + + + + + + + diff --git a/bsp/yichip/yc3121-pos/rtconfig.h b/bsp/yichip/yc3121-pos/rtconfig.h new file mode 100644 index 0000000000..d163fef848 --- /dev/null +++ b/bsp/yichip/yc3121-pos/rtconfig.h @@ -0,0 +1,178 @@ +#ifndef RT_CONFIG_H__ +#define RT_CONFIG_H__ + +/* Automatically generated file; DO NOT EDIT. */ +/* RT-Thread Configuration */ + +/* RT-Thread Kernel */ + +#define RT_NAME_MAX 8 +#define RT_ALIGN_SIZE 4 +#define RT_THREAD_PRIORITY_32 +#define RT_THREAD_PRIORITY_MAX 32 +#define RT_TICK_PER_SECOND 100 +#define RT_USING_OVERFLOW_CHECK +#define RT_USING_HOOK +#define RT_USING_IDLE_HOOK +#define RT_IDLE_HOOK_LIST_SIZE 4 +#define IDLE_THREAD_STACK_SIZE 256 + +/* kservice optimization */ + +#define RT_DEBUG +#define RT_DEBUG_COLOR + +/* Inter-Thread communication */ + +#define RT_USING_SEMAPHORE +#define RT_USING_MUTEX +#define RT_USING_EVENT +#define RT_USING_MAILBOX +#define RT_USING_MESSAGEQUEUE + +/* Memory Management */ + +#define RT_USING_MEMPOOL +#define RT_USING_MEMHEAP +#define RT_USING_SMALL_MEM +#define RT_USING_HEAP + +/* Kernel Device Object */ + +#define RT_USING_DEVICE +#define RT_USING_CONSOLE +#define RT_CONSOLEBUF_SIZE 128 +#define RT_CONSOLE_DEVICE_NAME "uart0" +#define RT_VER_NUM 0x40004 + +/* RT-Thread Components */ + +#define RT_USING_COMPONENTS_INIT +#define RT_USING_USER_MAIN +#define RT_MAIN_THREAD_STACK_SIZE 2048 +#define RT_MAIN_THREAD_PRIORITY 10 + +/* C++ features */ + + +/* Command shell */ + +#define RT_USING_FINSH +#define RT_USING_MSH +#define FINSH_USING_MSH +#define FINSH_THREAD_NAME "tshell" +#define FINSH_THREAD_PRIORITY 20 +#define FINSH_THREAD_STACK_SIZE 4096 +#define FINSH_USING_HISTORY +#define FINSH_HISTORY_LINES 5 +#define FINSH_USING_SYMTAB +#define FINSH_CMD_SIZE 80 +#define MSH_USING_BUILT_IN_COMMANDS +#define FINSH_USING_DESCRIPTION +#define FINSH_ARG_MAX 10 + +/* Device virtual file system */ + + +/* Device Drivers */ + +#define RT_USING_DEVICE_IPC +#define RT_PIPE_BUFSZ 512 +#define RT_USING_SERIAL +#define RT_USING_SERIAL_V1 +#define RT_SERIAL_RB_BUFSZ 64 +#define RT_USING_PIN + +/* Using USB */ + + +/* POSIX layer and C standard library */ + +#define RT_LIBC_USING_TIME +#define RT_LIBC_DEFAULT_TIMEZONE 8 + +/* Network */ + +/* Socket abstraction layer */ + + +/* Network interface device */ + + +/* light weight TCP/IP stack */ + + +/* AT commands */ + + +/* VBUS(Virtual Software BUS) */ + + +/* Utilities */ + + +/* RT-Thread Utestcases */ + + +/* RT-Thread online packages */ + +/* IoT - internet of things */ + + +/* Wi-Fi */ + +/* Marvell WiFi */ + + +/* Wiced WiFi */ + + +/* IoT Cloud */ + + +/* security packages */ + + +/* language packages */ + + +/* multimedia packages */ + + +/* tools packages */ + + +/* system packages */ + +/* acceleration: Assembly language or algorithmic acceleration packages */ + + +/* Micrium: Micrium software products porting for RT-Thread */ + + +/* peripheral libraries and drivers */ + + +/* AI packages */ + + +/* miscellaneous packages */ + +/* samples: kernel and components samples */ + + +/* entertainment: terminal games and other interesting software packages */ + +#define SOC_SWM320VET7 + +/* Hardware Drivers Config */ + +/* On-chip Peripheral Drivers */ + +#define BSP_USING_GPIO + +/* UART Drivers */ + +#define BSP_USING_UART0 + +#endif diff --git a/bsp/yichip/yc3121-pos/rtconfig.py b/bsp/yichip/yc3121-pos/rtconfig.py new file mode 100644 index 0000000000..f07430c42e --- /dev/null +++ b/bsp/yichip/yc3121-pos/rtconfig.py @@ -0,0 +1,152 @@ +# BSP Note: For TI EK-TM4C1294XL Tiva C Series Connected LancuhPad (REV D) + +import os +import sys +# toolchains options +ARCH='arm' +CPU='cortex-m0' +CROSS_TOOL='gcc' + +# device options +BSP_LIBRARY_TYPE = None + +if os.getenv('RTT_CC'): + CROSS_TOOL = os.getenv('RTT_CC') +if os.getenv('RTT_ROOT'): + RTT_ROOT = os.getenv('RTT_ROOT') + + +# cross_tool provides the cross compiler +# EXEC_PATH is the compiler execute path, for example, CodeSourcery, Keil MDK, IAR +if CROSS_TOOL == 'gcc': + PLATFORM = 'gcc' + EXEC_PATH = 'C:\gcc-arm-none-eabi-7-2018-q2-update-win32' +elif CROSS_TOOL == 'keil': + PLATFORM = 'armcc' + EXEC_PATH = 'C:/Keil_v5' +elif CROSS_TOOL == 'iar': + PLATFORM = 'iar' + EXEC_PATH = 'C:/Program Files (x86)/IAR Systems/Embedded Workbench 7.2' + +if os.getenv('RTT_EXEC_PATH'): + EXEC_PATH = os.getenv('RTT_EXEC_PATH') + +BUILD = 'debug' + +if PLATFORM == 'gcc': + # toolchains + PREFIX = 'arm-none-eabi-' + CC = PREFIX + 'gcc' + CXX = PREFIX + 'g++' + AS = PREFIX + 'gcc' + AR = PREFIX + 'ar' + LINK = PREFIX + 'gcc' + TARGET_EXT = 'elf' + SIZE = PREFIX + 'size' + OBJDUMP = PREFIX + 'objdump' + OBJCPY = PREFIX + 'objcopy' + + DEVICE = ' -mcpu=cortex-m0 -mthumb -ffunction-sections -fdata-sections' + CFLAGS = DEVICE + ' -Dgcc' + AFLAGS = ' -c' + DEVICE + ' -x assembler-with-cpp -Wa,-mimplicit-it=thumb ' + LFLAGS = DEVICE + ' -Wl,--gc-sections,-Map=rt-thread.map,-cref,-u,Reset_Handler -T drivers/linker_scripts/link.lds' + + CPATH = '' + LPATH = '' + + if BUILD == 'debug': + CFLAGS += ' -O0 -gdwarf-2 -g' + AFLAGS += ' -gdwarf-2' + else: + CFLAGS += ' -O2' + + CXXFLAGS = CFLAGS + + POST_ACTION = OBJCPY + ' -O binary $TARGET rtthread.bin\n' + SIZE + ' $TARGET \n' + +elif PLATFORM == 'armcc': + # toolchains + CC = 'armcc' + AS = 'armasm' + AR = 'armar' + LINK = 'armlink' + TARGET_EXT = 'axf' + + DEVICE = ' --cpu Cortex-M0 ' + CFLAGS = '-c ' + DEVICE + ' --apcs=interwork --c99' + AFLAGS = DEVICE + ' --apcs=interwork ' + LFLAGS = DEVICE + ' --scatter "drivers\linker_scripts\link.sct" --info sizes --info totals --info unused --info veneers --list rt-thread.map --strict' + CFLAGS += ' -I' + EXEC_PATH + '/ARM/ARMCC/include' + LFLAGS += ' --libpath=' + EXEC_PATH + '/ARM/ARMCC/lib' + + CFLAGS += ' -D__MICROLIB ' + AFLAGS += ' --pd "__MICROLIB SETA 1" ' + LFLAGS += ' --library_type=microlib ' + EXEC_PATH += '/ARM/ARMCC/bin/' + + if BUILD == 'debug': + CFLAGS += ' -g -O0' + AFLAGS += ' -g' + else: + CFLAGS += ' -O2' + + CXXFLAGS = CFLAGS + CFLAGS += ' -std=c99' + + POST_ACTION = 'fromelf.exe --text -a -c --output=@L_asm.txt "!L" \nfromelf -z $TARGET' + +elif PLATFORM == 'iar': + # toolchains + CC = 'iccarm' + CXX = 'iccarm' + AS = 'iasmarm' + AR = 'iarchive' + LINK = 'ilinkarm' + TARGET_EXT = 'out' + + DEVICE = '-Dewarm' + + CFLAGS = DEVICE + CFLAGS += ' --diag_suppress Pa050' + CFLAGS += ' --no_cse' + CFLAGS += ' --no_unroll' + CFLAGS += ' --no_inline' + CFLAGS += ' --no_code_motion' + CFLAGS += ' --no_tbaa' + CFLAGS += ' --no_clustering' + CFLAGS += ' --no_scheduling' + CFLAGS += ' --endian=little' + CFLAGS += ' --cpu=Cortex-M0' + CFLAGS += ' -e' + CFLAGS += ' --fpu=None' + CFLAGS += ' --dlib_config "' + EXEC_PATH + '/arm/INC/c/DLib_Config_Normal.h"' + CFLAGS += ' --silent' + + AFLAGS = DEVICE + AFLAGS += ' -s+' + AFLAGS += ' -w+' + AFLAGS += ' -r' + AFLAGS += ' --cpu Cortex-M0' + AFLAGS += ' --fpu None' + AFLAGS += ' -S' + + if BUILD == 'debug': + CFLAGS += ' --debug' + CFLAGS += ' -On' + else: + CFLAGS += ' -Oh' + + LFLAGS = ' --config "drivers/linker_scripts/link.icf"' + LFLAGS += ' --entry __iar_program_start' + + CXXFLAGS = CFLAGS + + EXEC_PATH = EXEC_PATH + '/arm/bin/' + POST_ACTION = 'ielftool --bin $TARGET rtthread.bin' + +def dist_handle(BSP_ROOT, dist_dir): + import sys + cwd_path = os.getcwd() + sys.path.append(os.path.join(os.path.dirname(BSP_ROOT), 'tools')) + from sdk_dist import dist_do_building + dist_do_building(BSP_ROOT, dist_dir) diff --git a/bsp/yichip/yc3121-pos/rtthread_asm.txt b/bsp/yichip/yc3121-pos/rtthread_asm.txt new file mode 100644 index 0000000000..88b0881675 --- /dev/null +++ b/bsp/yichip/yc3121-pos/rtthread_asm.txt @@ -0,0 +1,14979 @@ + +======================================================================== + +** ELF Header Information + + File Name: .\build\keil\Obj\rtthread.axf + + Machine class: ELFCLASS32 (32-bit) + Data encoding: ELFDATA2LSB (Little endian) + Header version: EV_CURRENT (Current version) + Operating System ABI: none + ABI Version: 0 + File Type: ET_EXEC (Executable) (2) + Machine: EM_ARM (ARM) + + Image Entry point: 0x01000401 + Flags: EF_ARM_HASENTRY + EF_ARM_ABI_FLOAT_SOFT (0x05000202) + + ARM ELF revision: 5 (ABI version 2) + + Conforms to Soft float procedure-call standard + + Built with + Component: ARM Compiler 5.06 update 6 (build 750) Tool: armasm [4d35ec] + Component: ARM Compiler 5.06 update 6 (build 750) Tool: armlink [4d35ed] + + Header size: 52 bytes (0x34) + Program header entry size: 32 bytes (0x20) + Section header entry size: 40 bytes (0x28) + + Program header entries: 3 + Section header entries: 19 + + Program header offset: 384436 (0x0005ddb4) + Section header offset: 384532 (0x0005de14) + + Section header string table index: 18 + +======================================================================== + +** Program header #0 (PT_LOAD) [PF_R] + Size : 192 bytes + Virtual address: 0x00000000 (Alignment 4) + + +==================================== + +** Program header #1 (PT_LOAD) [PF_X + PF_R] + Size : 372 bytes + Virtual address: 0x01000200 (Alignment 16) + + +==================================== + +** Program header #2 (PT_LOAD) [PF_X + PF_W + PF_R + PF_ARM_ENTRY] + Size : 36628 bytes (32872 bytes in file) + Virtual address: 0x01000400 (Alignment 16) + + +======================================================================== + +** Section #1 'ER_IROM1' (SHT_PROGBITS) [SHF_ALLOC] + Size : 192 bytes (alignment 4) + Address: 0x00000000 + + +** Section #2 'ER_IROM3' (SHT_PROGBITS) [SHF_ALLOC + SHF_EXECINSTR] + Size : 320 bytes (alignment 16) + Address: 0x01000200 + + $t + .flash_start + Reset_Handler + 0x01000200: 4849 IH LDR r0,[pc,#292] ; [0x1000328] = 0x1000401 + 0x01000202: 4700 .G BX r0 + hard_fault_handler + 0x01000204: 4849 IH LDR r0,[pc,#292] ; [0x100032c] = 0x100056d + 0x01000206: 4700 .G BX r0 + 0x01000208: bf00 .. NOP + svc_handler + 0x0100020a: 4849 IH LDR r0,[pc,#292] ; [0x1000330] = 0x10002a9 + 0x0100020c: 4700 .G BX r0 + 0x0100020e: bf00 .. NOP + pendsv_handler + 0x01000210: 4848 HH LDR r0,[pc,#288] ; [0x1000334] = 0x10004eb + 0x01000212: 4700 .G BX r0 + 0x01000214: bf00 .. NOP + systick + 0x01000216: 4848 HH LDR r0,[pc,#288] ; [0x1000338] = 0x1000b09 + 0x01000218: 4700 .G BX r0 + 0x0100021a: bf00 .. NOP + irq0 + 0x0100021c: 2000 . MOVS r0,#0 + 0x0100021e: e03d =. B isr ; 0x100029c + irq1 + 0x01000220: 2004 . MOVS r0,#4 + 0x01000222: e03b ;. B isr ; 0x100029c + irq2 + 0x01000224: 2008 . MOVS r0,#8 + 0x01000226: e039 9. B isr ; 0x100029c + irq3 + 0x01000228: 200c . MOVS r0,#0xc + 0x0100022a: e037 7. B isr ; 0x100029c + irq4 + 0x0100022c: 2010 . MOVS r0,#0x10 + 0x0100022e: e035 5. B isr ; 0x100029c + irq5 + 0x01000230: 2014 . MOVS r0,#0x14 + 0x01000232: e033 3. B isr ; 0x100029c + irq6 + 0x01000234: 2018 . MOVS r0,#0x18 + 0x01000236: e031 1. B isr ; 0x100029c + irq7 + 0x01000238: 201c . MOVS r0,#0x1c + 0x0100023a: e02f /. B isr ; 0x100029c + irq8 + 0x0100023c: 2020 MOVS r0,#0x20 + 0x0100023e: e02d -. B isr ; 0x100029c + irq9 + 0x01000240: 2024 $ MOVS r0,#0x24 + 0x01000242: e02b +. B isr ; 0x100029c + irq10 + 0x01000244: 2028 ( MOVS r0,#0x28 + 0x01000246: e029 ). B isr ; 0x100029c + irq11 + 0x01000248: 202c , MOVS r0,#0x2c + 0x0100024a: e027 '. B isr ; 0x100029c + irq12 + 0x0100024c: 2030 0 MOVS r0,#0x30 + 0x0100024e: e025 %. B isr ; 0x100029c + irq13 + 0x01000250: 2034 4 MOVS r0,#0x34 + 0x01000252: e023 #. B isr ; 0x100029c + irq14 + 0x01000254: 2038 8 MOVS r0,#0x38 + 0x01000256: e021 !. B isr ; 0x100029c + irq15 + 0x01000258: 203c < MOVS r0,#0x3c + 0x0100025a: e01f .. B isr ; 0x100029c + irq16 + 0x0100025c: 2040 @ MOVS r0,#0x40 + 0x0100025e: e01d .. B isr ; 0x100029c + irq17 + 0x01000260: 2044 D MOVS r0,#0x44 + 0x01000262: e01b .. B isr ; 0x100029c + irq18 + 0x01000264: 2048 H MOVS r0,#0x48 + 0x01000266: e019 .. B isr ; 0x100029c + irq19 + 0x01000268: 204c L MOVS r0,#0x4c + 0x0100026a: e017 .. B isr ; 0x100029c + irq20 + 0x0100026c: 2050 P MOVS r0,#0x50 + 0x0100026e: e015 .. B isr ; 0x100029c + irq21 + 0x01000270: 2054 T MOVS r0,#0x54 + 0x01000272: e013 .. B isr ; 0x100029c + irq22 + 0x01000274: 2058 X MOVS r0,#0x58 + 0x01000276: e011 .. B isr ; 0x100029c + irq23 + 0x01000278: 205c \ MOVS r0,#0x5c + 0x0100027a: e00f .. B isr ; 0x100029c + irq24 + 0x0100027c: 2060 ` MOVS r0,#0x60 + 0x0100027e: e00d .. B isr ; 0x100029c + irq25 + 0x01000280: 2064 d MOVS r0,#0x64 + 0x01000282: e00b .. B isr ; 0x100029c + irq26 + 0x01000284: 2068 h MOVS r0,#0x68 + 0x01000286: e009 .. B isr ; 0x100029c + irq27 + 0x01000288: 206c l MOVS r0,#0x6c + 0x0100028a: e007 .. B isr ; 0x100029c + irq28 + 0x0100028c: 2070 p MOVS r0,#0x70 + 0x0100028e: e005 .. B isr ; 0x100029c + irq29 + 0x01000290: 2074 t MOVS r0,#0x74 + 0x01000292: e003 .. B isr ; 0x100029c + irq30 + 0x01000294: 2078 x MOVS r0,#0x78 + 0x01000296: e001 .. B isr ; 0x100029c + irq31 + 0x01000298: 207c | MOVS r0,#0x7c + 0x0100029a: 46c0 .F MOV r8,r8 + isr + 0x0100029c: 4927 'I LDR r1,[pc,#156] ; [0x100033c] = 0x10002bc + 0x0100029e: 5840 @X LDR r0,[r0,r1] + 0x010002a0: 4700 .G BX r0 + $d + 0x010002a2: 0000 .. DCW 0 + $t + NMI_IRQHandler + 0x010002a4: e7fe .. B NMI_IRQHandler ; 0x10002a4 + HARD_FAULT_IRQHandler + 0x010002a6: e7fe .. B HARD_FAULT_IRQHandler ; 0x10002a6 + SVC_IRQHandler + 0x010002a8: e7fe .. B SVC_IRQHandler ; 0x10002a8 + PENDSV_IRQHandler + 0x010002aa: e7fe .. B PENDSV_IRQHandler ; 0x10002aa + SYSTICK_IRQHandler + 0x010002ac: e7fe .. B SYSTICK_IRQHandler ; 0x10002ac + EXTI0_IRQHandler + 0x010002ae: e7fe .. B EXTI0_IRQHandler ; 0x10002ae + EXTI1_IRQHandler + 0x010002b0: e7fe .. B EXTI1_IRQHandler ; 0x10002b0 + EXTI2_IRQHandler + 0x010002b2: e7fe .. B EXTI2_IRQHandler ; 0x10002b2 + EXTI3_IRQHandler + 0x010002b4: e7fe .. B EXTI3_IRQHandler ; 0x10002b4 + EXTI4_IRQHandler + 0x010002b6: e7fe .. B EXTI4_IRQHandler ; 0x10002b6 + EXTI5_IRQHandler + 0x010002b8: e7fe .. B EXTI5_IRQHandler ; 0x10002b8 + BT_IRQHandler + GPIO_IRQHandler + IIC_IRQHandler + MEMCP_IRQHandler + MSR_IRQHandler + QSPI_IRQHandler + RSA_IRQHandler + SCI0_IRQHandler + SCI1_IRQHandler + SEC_IRQHandler + SM4_IRQHandler + SPI0_IRQHandler + SPI1_IRQHandler + TIMER0_IRQHandler + TIMER1_IRQHandler + TIMER2_IRQHandler + TIMER3_IRQHandler + TIMER4_IRQHandler + TIMER5_IRQHandler + TIMER6_IRQHandler + TIMER7_IRQHandler + TIMER8_IRQHandler + TRNG_IRQHandler + UART1_IRQHandler + USB_IRQHandler + WDT_IRQHandler + 0x010002ba: e7fe .. B BT_IRQHandler ; 0x10002ba + $d + isr_table + 0x010002bc: 010002bb .... DCD 16777915 + 0x010002c0: 010002bb .... DCD 16777915 + 0x010002c4: 010002bb .... DCD 16777915 + 0x010002c8: 010002bb .... DCD 16777915 + 0x010002cc: 010002bb .... DCD 16777915 + 0x010002d0: 01000b19 .... DCD 16780057 + 0x010002d4: 010002bb .... DCD 16777915 + 0x010002d8: 010002bb .... DCD 16777915 + 0x010002dc: 010002bb .... DCD 16777915 + 0x010002e0: 010002bb .... DCD 16777915 + 0x010002e4: 010002bb .... DCD 16777915 + 0x010002e8: 010002bb .... DCD 16777915 + 0x010002ec: 010002bb .... DCD 16777915 + 0x010002f0: 010002bb .... DCD 16777915 + 0x010002f4: 010002bb .... DCD 16777915 + 0x010002f8: 010002bb .... DCD 16777915 + 0x010002fc: 010002bb .... DCD 16777915 + 0x01000300: 010002bb .... DCD 16777915 + 0x01000304: 010002bb .... DCD 16777915 + 0x01000308: 010002bb .... DCD 16777915 + 0x0100030c: 010002bb .... DCD 16777915 + 0x01000310: 010002bb .... DCD 16777915 + 0x01000314: 010002bb .... DCD 16777915 + 0x01000318: 010002bb .... DCD 16777915 + 0x0100031c: 010002bb .... DCD 16777915 + 0x01000320: 010002bb .... DCD 16777915 + 0x01000324: 010002bb .... DCD 16777915 + 0x01000328: 01000401 .... DCD 16778241 + 0x0100032c: 0100056d m... DCD 16778605 + 0x01000330: 010002a9 .... DCD 16777897 + 0x01000334: 010004eb .... DCD 16778475 + 0x01000338: 01000b09 .... DCD 16780041 + 0x0100033c: 010002bc .... DCD 16777916 + +** Section #3 'ER_IROM3_1' (SHT_PROGBITS) [SHF_ALLOC + SHF_EXECINSTR] + Size : 52 bytes (alignment 16) + Address: 0x01000340 + + $t + .INIT_STACK_HEAP + __user_initial_stackheap + 0x01000340: 4802 .H LDR r0,[pc,#8] ; [0x100034c] = 0x20e10 + 0x01000342: 4903 .I LDR r1,[pc,#12] ; [0x1000350] = 0x30000 + 0x01000344: 4a01 .J LDR r2,[pc,#4] ; [0x100034c] = 0x20e10 + 0x01000346: 4b03 .K LDR r3,[pc,#12] ; [0x1000354] = 0x20e10 + 0x01000348: 4770 pG BX lr + $d + 0x0100034a: 0000 .. DCW 0 + 0x0100034c: 00020e10 .... DCD 134672 + 0x01000350: 00030000 .... DCD 196608 + 0x01000354: 00020e10 .... DCD 134672 + 0x01000358: 00000000 .... DCD 0 + 0x0100035c: 00000000 .... DCD 0 + $t + .text + reset_handler + 0x01000360: 4803 .H LDR r0,[pc,#12] ; [0x1000370] = 0x1000201 + 0x01000362: 4700 .G BX r0 + 0x01000364: bf00 .. NOP + delay + 0x01000366: 3801 .8 SUBS r0,#1 + 0x01000368: d1fd .. BNE delay ; 0x1000366 + 0x0100036a: bf00 .. NOP + 0x0100036c: 4770 pG BX lr + nmi_handler + 0x0100036e: e7fe .. B nmi_handler ; 0x100036e + $d + 0x01000370: 01000201 .... DCD 16777729 + +** Section #4 'ER_IROM4' (SHT_PROGBITS) [SHF_ALLOC + SHF_EXECINSTR] + Size : 32772 bytes (alignment 4) + Address: 0x01000400 + + $t + !!!main + __main + 0x01000400: f000f802 .... BL __scatterload ; 0x1000408 + 0x01000404: f000f830 ..0. BL __rt_entry ; 0x1000468 + !!!scatter + __scatterload + __scatterload_rt2 + __scatterload_rt2_thumb_only + 0x01000408: a00c .. ADR r0,{pc}+0x34 ; 0x100043c + 0x0100040a: c830 0. LDM r0!,{r4,r5} + 0x0100040c: 3808 .8 SUBS r0,r0,#8 + 0x0100040e: 1824 $. ADDS r4,r4,r0 + 0x01000410: 182d -. ADDS r5,r5,r0 + 0x01000412: 46a2 .F MOV r10,r4 + 0x01000414: 1e67 g. SUBS r7,r4,#1 + 0x01000416: 46ab .F MOV r11,r5 + __scatterload_null + 0x01000418: 4654 TF MOV r4,r10 + 0x0100041a: 465d ]F MOV r5,r11 + 0x0100041c: 42ac .B CMP r4,r5 + 0x0100041e: d101 .. BNE 0x1000424 ; __scatterload_null + 12 + 0x01000420: f000f822 ..". BL __rt_entry ; 0x1000468 + 0x01000424: 467e ~F MOV r6,pc + 0x01000426: 3e0f .> SUBS r6,r6,#0xf + 0x01000428: cc0f .. LDM r4!,{r0-r3} + 0x0100042a: 46b6 .F MOV lr,r6 + 0x0100042c: 2601 .& MOVS r6,#1 + 0x0100042e: 4233 3B TST r3,r6 + 0x01000430: d000 .. BEQ 0x1000434 ; __scatterload_null + 28 + 0x01000432: 1afb .. SUBS r3,r7,r3 + 0x01000434: 46a2 .F MOV r10,r4 + 0x01000436: 46ab .F MOV r11,r5 + 0x01000438: 4333 3C ORRS r3,r3,r6 + 0x0100043a: 4718 .G BX r3 + $d + 0x0100043c: 00007fa8 .... DCD 32680 + 0x01000440: 00007fc8 .... DCD 32712 + $t + !!handler_zi + __scatterload_zeroinit + 0x01000444: 2300 .# MOVS r3,#0 + 0x01000446: 2400 .$ MOVS r4,#0 + 0x01000448: 2500 .% MOVS r5,#0 + 0x0100044a: 2600 .& MOVS r6,#0 + 0x0100044c: 3a10 .: SUBS r2,r2,#0x10 + 0x0100044e: d301 .. BCC 0x1000454 ; __scatterload_zeroinit + 16 + 0x01000450: c178 x. STM r1!,{r3-r6} + 0x01000452: d8fb .. BHI 0x100044c ; __scatterload_zeroinit + 8 + 0x01000454: 0752 R. LSLS r2,r2,#29 + 0x01000456: d300 .. BCC 0x100045a ; __scatterload_zeroinit + 22 + 0x01000458: c130 0. STM r1!,{r4,r5} + 0x0100045a: d500 .. BPL 0x100045e ; __scatterload_zeroinit + 26 + 0x0100045c: 600b .` STR r3,[r1,#0] + 0x0100045e: 4770 pG BX lr + .ARM.Collect$$libinit$$00000000 + __rt_lib_init + 0x01000460: b51f .. PUSH {r0-r4,lr} + .ARM.Collect$$libinit$$00000002 + .ARM.Collect$$libinit$$00000004 + .ARM.Collect$$libinit$$0000000A + .ARM.Collect$$libinit$$0000000C + .ARM.Collect$$libinit$$0000000E + .ARM.Collect$$libinit$$00000011 + .ARM.Collect$$libinit$$00000013 + .ARM.Collect$$libinit$$00000015 + .ARM.Collect$$libinit$$00000017 + .ARM.Collect$$libinit$$00000019 + .ARM.Collect$$libinit$$0000001B + .ARM.Collect$$libinit$$0000001D + .ARM.Collect$$libinit$$0000001F + .ARM.Collect$$libinit$$00000021 + .ARM.Collect$$libinit$$00000023 + .ARM.Collect$$libinit$$00000025 + .ARM.Collect$$libinit$$0000002C + .ARM.Collect$$libinit$$0000002E + .ARM.Collect$$libinit$$00000030 + .ARM.Collect$$libinit$$00000032 + .ARM.Collect$$libinit$$00000033 + __rt_lib_init_alloca_1 + __rt_lib_init_argv_1 + __rt_lib_init_atexit_1 + __rt_lib_init_clock_1 + __rt_lib_init_cpp_1 + __rt_lib_init_exceptions_1 + __rt_lib_init_fp_1 + __rt_lib_init_fp_trap_1 + __rt_lib_init_getenv_1 + __rt_lib_init_heap_1 + __rt_lib_init_lc_collate_1 + __rt_lib_init_lc_ctype_1 + __rt_lib_init_lc_monetary_1 + __rt_lib_init_lc_numeric_1 + __rt_lib_init_lc_time_1 + __rt_lib_init_preinit_1 + __rt_lib_init_rand_1 + __rt_lib_init_return + __rt_lib_init_signal_1 + __rt_lib_init_stdio_1 + __rt_lib_init_user_alloc_1 + 0x01000462: bd1f .. POP {r0-r4,pc} + .ARM.Collect$$libshutdown$$00000000 + __rt_lib_shutdown + 0x01000464: b510 .. PUSH {r4,lr} + .ARM.Collect$$libshutdown$$00000002 + .ARM.Collect$$libshutdown$$00000004 + .ARM.Collect$$libshutdown$$00000007 + .ARM.Collect$$libshutdown$$0000000A + .ARM.Collect$$libshutdown$$0000000C + .ARM.Collect$$libshutdown$$0000000F + .ARM.Collect$$libshutdown$$00000010 + __rt_lib_shutdown_cpp_1 + __rt_lib_shutdown_fp_trap_1 + __rt_lib_shutdown_heap_1 + __rt_lib_shutdown_return + __rt_lib_shutdown_signal_1 + __rt_lib_shutdown_stdio_1 + __rt_lib_shutdown_user_alloc_1 + 0x01000466: bd10 .. POP {r4,pc} + .ARM.Collect$$rtentry$$00000000 + .ARM.Collect$$rtentry$$00000002 + .ARM.Collect$$rtentry$$00000004 + __rt_entry + __rt_entry_presh_1 + __rt_entry_sh + 0x01000468: f000fab0 .... BL __user_setup_stackheap ; 0x10009cc + 0x0100046c: 4611 .F MOV r1,r2 + .ARM.Collect$$rtentry$$00000009 + .ARM.Collect$$rtentry$$0000000A + __rt_entry_li + __rt_entry_postsh_1 + 0x0100046e: f7fffff7 .... BL __rt_lib_init ; 0x1000460 + .ARM.Collect$$rtentry$$0000000C + .ARM.Collect$$rtentry$$0000000D + __rt_entry_main + __rt_entry_postli_1 + 0x01000472: f000fb09 .... BL main ; 0x1000a88 + 0x01000476: f000fac8 .... BL exit ; 0x1000a0a + .ARM.Collect$$rtexit$$00000000 + __rt_exit + 0x0100047a: b403 .. PUSH {r0,r1} + .ARM.Collect$$rtexit$$00000002 + .ARM.Collect$$rtexit$$00000003 + __rt_exit_ls + __rt_exit_prels_1 + 0x0100047c: f7fffff2 .... BL __rt_lib_shutdown ; 0x1000464 + .ARM.Collect$$rtexit$$00000004 + __rt_exit_exit + 0x01000480: bc03 .. POP {r0,r1} + 0x01000482: f000facf .... BL _sys_exit ; 0x1000a24 + 0x01000486: 0000 .. MOVS r0,r0 + .emb_text + __aeabi_memcpy4 + __aeabi_memcpy8 + 0x01000488: b570 p. PUSH {r4-r6,lr} + 0x0100048a: 4605 .F MOV r5,r0 + 0x0100048c: 460c .F MOV r4,r1 + 0x0100048e: 4616 .F MOV r6,r2 + 0x01000490: e002 .. B 0x1000498 ; __aeabi_memcpy4 + 16 + 0x01000492: cc0f .. LDM r4!,{r0-r3} + 0x01000494: c50f .. STM r5!,{r0-r3} + 0x01000496: 3e10 .> SUBS r6,r6,#0x10 + 0x01000498: 2e10 .. CMP r6,#0x10 + 0x0100049a: d2fa .. BCS 0x1000492 ; __aeabi_memcpy4 + 10 + 0x0100049c: 2e08 .. CMP r6,#8 + 0x0100049e: d302 .. BCC 0x10004a6 ; __aeabi_memcpy4 + 30 + 0x010004a0: cc03 .. LDM r4!,{r0,r1} + 0x010004a2: c503 .. STM r5!,{r0,r1} + 0x010004a4: 3e08 .> SUBS r6,r6,#8 + 0x010004a6: 2e04 .. CMP r6,#4 + 0x010004a8: d307 .. BCC 0x10004ba ; __aeabi_memcpy4 + 50 + 0x010004aa: cc01 .. LDM r4!,{r0} + 0x010004ac: c501 .. STM r5!,{r0} + 0x010004ae: 1f36 6. SUBS r6,r6,#4 + 0x010004b0: e003 .. B 0x10004ba ; __aeabi_memcpy4 + 50 + 0x010004b2: 7821 !x LDRB r1,[r4,#0] + 0x010004b4: 7029 )p STRB r1,[r5,#0] + 0x010004b6: 1c64 d. ADDS r4,r4,#1 + 0x010004b8: 1c6d m. ADDS r5,r5,#1 + 0x010004ba: 1e76 v. SUBS r6,r6,#1 + 0x010004bc: d2f9 .. BCS 0x10004b2 ; __aeabi_memcpy4 + 42 + 0x010004be: bd70 p. POP {r4-r6,pc} + .text + rt_hw_interrupt_disable + 0x010004c0: f3ef8010 .... MRS r0,PRIMASK + 0x010004c4: b672 r. CPSID i + 0x010004c6: 4770 pG BX lr + rt_hw_interrupt_enable + 0x010004c8: f3808810 .... MSR PRIMASK,r0 + 0x010004cc: 4770 pG BX lr + rt_hw_context_switch + rt_hw_context_switch_interrupt + 0x010004ce: 4a2a *J LDR r2,[pc,#168] ; [0x1000578] = 0x20008 + 0x010004d0: 6813 .h LDR r3,[r2,#0] + 0x010004d2: 2b01 .+ CMP r3,#1 + 0x010004d4: d003 .. BEQ 0x10004de ; rt_hw_context_switch + 16 + 0x010004d6: 2301 .# MOVS r3,#1 + 0x010004d8: 6013 .` STR r3,[r2,#0] + 0x010004da: 4a28 (J LDR r2,[pc,#160] ; [0x100057c] = 0x20000 + 0x010004dc: 6010 .` STR r0,[r2,#0] + 0x010004de: 4a28 (J LDR r2,[pc,#160] ; [0x1000580] = 0x20004 + 0x010004e0: 6011 .` STR r1,[r2,#0] + 0x010004e2: 4828 (H LDR r0,[pc,#160] ; [0x1000584] = 0xe000ed04 + 0x010004e4: 4928 (I LDR r1,[pc,#160] ; [0x1000588] = 0x10000000 + 0x010004e6: 6001 .` STR r1,[r0,#0] + 0x010004e8: 4770 pG BX lr + PendSV_Handler + 0x010004ea: f3ef8210 .... MRS r2,PRIMASK + 0x010004ee: b672 r. CPSID i + 0x010004f0: 4821 !H LDR r0,[pc,#132] ; [0x1000578] = 0x20008 + 0x010004f2: 6801 .h LDR r1,[r0,#0] + 0x010004f4: 2900 .) CMP r1,#0 + 0x010004f6: d01d .. BEQ 0x1000534 ; PendSV_Handler + 74 + 0x010004f8: 2100 .! MOVS r1,#0 + 0x010004fa: 6001 .` STR r1,[r0,#0] + 0x010004fc: 481f .H LDR r0,[pc,#124] ; [0x100057c] = 0x20000 + 0x010004fe: 6801 .h LDR r1,[r0,#0] + 0x01000500: 2900 .) CMP r1,#0 + 0x01000502: d00a .. BEQ 0x100051a ; PendSV_Handler + 48 + 0x01000504: f3ef8109 .... MRS r1,PSP + 0x01000508: 3920 9 SUBS r1,r1,#0x20 + 0x0100050a: 6800 .h LDR r0,[r0,#0] + 0x0100050c: 6001 .` STR r1,[r0,#0] + 0x0100050e: c1f0 .. STM r1!,{r4-r7} + 0x01000510: 4644 DF MOV r4,r8 + 0x01000512: 464d MF MOV r5,r9 + 0x01000514: 4656 VF MOV r6,r10 + 0x01000516: 465f _F MOV r7,r11 + 0x01000518: c1f0 .. STM r1!,{r4-r7} + 0x0100051a: 4919 .I LDR r1,[pc,#100] ; [0x1000580] = 0x20004 + 0x0100051c: 6809 .h LDR r1,[r1,#0] + 0x0100051e: 6809 .h LDR r1,[r1,#0] + 0x01000520: c9f0 .. LDM r1!,{r4-r7} + 0x01000522: b4f0 .. PUSH {r4-r7} + 0x01000524: c9f0 .. LDM r1!,{r4-r7} + 0x01000526: 46a0 .F MOV r8,r4 + 0x01000528: 46a9 .F MOV r9,r5 + 0x0100052a: 46b2 .F MOV r10,r6 + 0x0100052c: 46bb .F MOV r11,r7 + 0x0100052e: bcf0 .. POP {r4-r7} + 0x01000530: f3818809 .... MSR PSP,r1 + 0x01000534: f3828810 .... MSR PRIMASK,r2 + 0x01000538: 2004 . MOVS r0,#4 + 0x0100053a: 4240 @B RSBS r0,r0,#0 + 0x0100053c: 4700 .G BX r0 + rt_hw_context_switch_to + 0x0100053e: 4910 .I LDR r1,[pc,#64] ; [0x1000580] = 0x20004 + 0x01000540: 6008 .` STR r0,[r1,#0] + 0x01000542: 490e .I LDR r1,[pc,#56] ; [0x100057c] = 0x20000 + 0x01000544: 2000 . MOVS r0,#0 + 0x01000546: 6008 .` STR r0,[r1,#0] + 0x01000548: 490b .I LDR r1,[pc,#44] ; [0x1000578] = 0x20008 + 0x0100054a: 2001 . MOVS r0,#1 + 0x0100054c: 6008 .` STR r0,[r1,#0] + 0x0100054e: 480f .H LDR r0,[pc,#60] ; [0x100058c] = 0xe000ed20 + 0x01000550: 490f .I LDR r1,[pc,#60] ; [0x1000590] = 0xffff0000 + 0x01000552: 6802 .h LDR r2,[r0,#0] + 0x01000554: 4311 .C ORRS r1,r1,r2 + 0x01000556: 6001 .` STR r1,[r0,#0] + 0x01000558: 480a .H LDR r0,[pc,#40] ; [0x1000584] = 0xe000ed04 + 0x0100055a: 490b .I LDR r1,[pc,#44] ; [0x1000588] = 0x10000000 + 0x0100055c: 6001 .` STR r1,[r0,#0] + 0x0100055e: 480d .H LDR r0,[pc,#52] ; [0x1000594] = 0xe000ed08 + 0x01000560: 6800 .h LDR r0,[r0,#0] + 0x01000562: 6800 .h LDR r0,[r0,#0] + 0x01000564: f3808808 .... MSR MSP,r0 + 0x01000568: b662 b. CPSIE i + rt_hw_interrupt_thread_switch + 0x0100056a: 4770 pG BX lr + HardFault_Handler + 0x0100056c: f3ef8009 .... MRS r0,PSP + 0x01000570: b500 .. PUSH {lr} + 0x01000572: f003fdd1 .... BL rt_hw_hard_fault_exception ; 0x1004118 + 0x01000576: bd00 .. POP {pc} + $d + 0x01000578: 00020008 .... DCD 131080 + 0x0100057c: 00020000 .... DCD 131072 + 0x01000580: 00020004 .... DCD 131076 + 0x01000584: e000ed04 .... DCD 3758157060 + 0x01000588: 10000000 .... DCD 268435456 + 0x0100058c: e000ed20 ... DCD 3758157088 + 0x01000590: ffff0000 .... DCD 4294901760 + 0x01000594: e000ed08 .... DCD 3758157064 + $t + .text + memcmp + 0x01000598: 4603 .F MOV r3,r0 + 0x0100059a: b510 .. PUSH {r4,lr} + 0x0100059c: 430b .C ORRS r3,r3,r1 + 0x0100059e: 079b .. LSLS r3,r3,#30 + 0x010005a0: d10f .. BNE 0x10005c2 ; memcmp + 42 + 0x010005a2: 2a04 .* CMP r2,#4 + 0x010005a4: d30d .. BCC 0x10005c2 ; memcmp + 42 + 0x010005a6: c808 .. LDM r0!,{r3} + 0x010005a8: c910 .. LDM r1!,{r4} + 0x010005aa: 1f12 .. SUBS r2,r2,#4 + 0x010005ac: 42a3 .B CMP r3,r4 + 0x010005ae: d0f8 .. BEQ 0x10005a2 ; memcmp + 10 + 0x010005b0: ba18 .. REV r0,r3 + 0x010005b2: ba21 !. REV r1,r4 + 0x010005b4: 4288 .B CMP r0,r1 + 0x010005b6: d901 .. BLS 0x10005bc ; memcmp + 36 + 0x010005b8: 2001 . MOVS r0,#1 + 0x010005ba: bd10 .. POP {r4,pc} + 0x010005bc: 2000 . MOVS r0,#0 + 0x010005be: 43c0 .C MVNS r0,r0 + 0x010005c0: bd10 .. POP {r4,pc} + 0x010005c2: 2a00 .* CMP r2,#0 + 0x010005c4: d003 .. BEQ 0x10005ce ; memcmp + 54 + 0x010005c6: 07d3 .. LSLS r3,r2,#31 + 0x010005c8: d003 .. BEQ 0x10005d2 ; memcmp + 58 + 0x010005ca: 1c52 R. ADDS r2,r2,#1 + 0x010005cc: e007 .. B 0x10005de ; memcmp + 70 + 0x010005ce: 2000 . MOVS r0,#0 + 0x010005d0: bd10 .. POP {r4,pc} + 0x010005d2: 7803 .x LDRB r3,[r0,#0] + 0x010005d4: 780c .x LDRB r4,[r1,#0] + 0x010005d6: 1c40 @. ADDS r0,r0,#1 + 0x010005d8: 1c49 I. ADDS r1,r1,#1 + 0x010005da: 1b1b .. SUBS r3,r3,r4 + 0x010005dc: d107 .. BNE 0x10005ee ; memcmp + 86 + 0x010005de: 7803 .x LDRB r3,[r0,#0] + 0x010005e0: 780c .x LDRB r4,[r1,#0] + 0x010005e2: 1c40 @. ADDS r0,r0,#1 + 0x010005e4: 1c49 I. ADDS r1,r1,#1 + 0x010005e6: 1b1b .. SUBS r3,r3,r4 + 0x010005e8: d101 .. BNE 0x10005ee ; memcmp + 86 + 0x010005ea: 1e92 .. SUBS r2,r2,#2 + 0x010005ec: d1f1 .. BNE 0x10005d2 ; memcmp + 58 + 0x010005ee: 4618 .F MOV r0,r3 + 0x010005f0: bd10 .. POP {r4,pc} + 0x010005f2: 0000 .. MOVS r0,r0 + .text + strcpy + 0x010005f4: 4603 .F MOV r3,r0 + 0x010005f6: b570 p. PUSH {r4-r6,lr} + 0x010005f8: 4602 .F MOV r2,r0 + 0x010005fa: 430b .C ORRS r3,r3,r1 + 0x010005fc: 079b .. LSLS r3,r3,#30 + 0x010005fe: d10f .. BNE 0x1000620 ; strcpy + 44 + 0x01000600: 4c0e .L LDR r4,[pc,#56] ; [0x100063c] = 0x1010101 + 0x01000602: 01e6 .. LSLS r6,r4,#7 + 0x01000604: e000 .. B 0x1000608 ; strcpy + 20 + 0x01000606: c208 .. STM r2!,{r3} + 0x01000608: c908 .. LDM r1!,{r3} + 0x0100060a: 1b1d .. SUBS r5,r3,r4 + 0x0100060c: 439d .C BICS r5,r5,r3 + 0x0100060e: 4235 5B TST r5,r6 + 0x01000610: d0f9 .. BEQ 0x1000606 ; strcpy + 18 + 0x01000612: b2d9 .. UXTB r1,r3 + 0x01000614: 7011 .p STRB r1,[r2,#0] + 0x01000616: 1c52 R. ADDS r2,r2,#1 + 0x01000618: 2900 .) CMP r1,#0 + 0x0100061a: d00d .. BEQ 0x1000638 ; strcpy + 68 + 0x0100061c: 0a1b .. LSRS r3,r3,#8 + 0x0100061e: e7f8 .. B 0x1000612 ; strcpy + 30 + 0x01000620: 780b .x LDRB r3,[r1,#0] + 0x01000622: 1c49 I. ADDS r1,r1,#1 + 0x01000624: 7013 .p STRB r3,[r2,#0] + 0x01000626: 1c52 R. ADDS r2,r2,#1 + 0x01000628: 2b00 .+ CMP r3,#0 + 0x0100062a: d005 .. BEQ 0x1000638 ; strcpy + 68 + 0x0100062c: 780b .x LDRB r3,[r1,#0] + 0x0100062e: 1c49 I. ADDS r1,r1,#1 + 0x01000630: 7013 .p STRB r3,[r2,#0] + 0x01000632: 1c52 R. ADDS r2,r2,#1 + 0x01000634: 2b00 .+ CMP r3,#0 + 0x01000636: d1f3 .. BNE 0x1000620 ; strcpy + 44 + 0x01000638: bd70 p. POP {r4-r6,pc} + $d + 0x0100063a: 0000 .. DCW 0 + 0x0100063c: 01010101 .... DCD 16843009 + $t + .text + strlen + 0x01000640: b530 0. PUSH {r4,r5,lr} + 0x01000642: 1c44 D. ADDS r4,r0,#1 + 0x01000644: e003 .. B 0x100064e ; strlen + 14 + 0x01000646: 7801 .x LDRB r1,[r0,#0] + 0x01000648: 1c40 @. ADDS r0,r0,#1 + 0x0100064a: 2900 .) CMP r1,#0 + 0x0100064c: d00d .. BEQ 0x100066a ; strlen + 42 + 0x0100064e: 0781 .. LSLS r1,r0,#30 + 0x01000650: d1f9 .. BNE 0x1000646 ; strlen + 6 + 0x01000652: 4b0b .K LDR r3,[pc,#44] ; [0x1000680] = 0x1010101 + 0x01000654: 01dd .. LSLS r5,r3,#7 + 0x01000656: c804 .. LDM r0!,{r2} + 0x01000658: 1ad1 .. SUBS r1,r2,r3 + 0x0100065a: 4391 .C BICS r1,r1,r2 + 0x0100065c: 4029 )@ ANDS r1,r1,r5 + 0x0100065e: d0fa .. BEQ 0x1000656 ; strlen + 22 + 0x01000660: 1b00 .. SUBS r0,r0,r4 + 0x01000662: 060a .. LSLS r2,r1,#24 + 0x01000664: d003 .. BEQ 0x100066e ; strlen + 46 + 0x01000666: 1ec0 .. SUBS r0,r0,#3 + 0x01000668: bd30 0. POP {r4,r5,pc} + 0x0100066a: 1b00 .. SUBS r0,r0,r4 + 0x0100066c: bd30 0. POP {r4,r5,pc} + 0x0100066e: 040a .. LSLS r2,r1,#16 + 0x01000670: d001 .. BEQ 0x1000676 ; strlen + 54 + 0x01000672: 1e80 .. SUBS r0,r0,#2 + 0x01000674: bd30 0. POP {r4,r5,pc} + 0x01000676: 0209 .. LSLS r1,r1,#8 + 0x01000678: d0fc .. BEQ 0x1000674 ; strlen + 52 + 0x0100067a: 1e40 @. SUBS r0,r0,#1 + 0x0100067c: bd30 0. POP {r4,r5,pc} + $d + 0x0100067e: 0000 .. DCW 0 + 0x01000680: 01010101 .... DCD 16843009 + $t + .text + strncmp + 0x01000684: 4603 .F MOV r3,r0 + 0x01000686: b5f0 .. PUSH {r4-r7,lr} + 0x01000688: 430b .C ORRS r3,r3,r1 + 0x0100068a: 079b .. LSLS r3,r3,#30 + 0x0100068c: d12d -. BNE 0x10006ea ; strncmp + 102 + 0x0100068e: 4d24 $M LDR r5,[pc,#144] ; [0x1000720] = 0x1010101 + 0x01000690: 01ef .. LSLS r7,r5,#7 + 0x01000692: 2a04 .* CMP r2,#4 + 0x01000694: d329 ). BCC 0x10006ea ; strncmp + 102 + 0x01000696: c808 .. LDM r0!,{r3} + 0x01000698: c910 .. LDM r1!,{r4} + 0x0100069a: 1b5e ^. SUBS r6,r3,r5 + 0x0100069c: 439e .C BICS r6,r6,r3 + 0x0100069e: 1f12 .. SUBS r2,r2,#4 + 0x010006a0: 403e >@ ANDS r6,r6,r7 + 0x010006a2: d017 .. BEQ 0x10006d4 ; strncmp + 80 + 0x010006a4: b2d8 .. UXTB r0,r3 + 0x010006a6: b2e1 .. UXTB r1,r4 + 0x010006a8: 1a40 @. SUBS r0,r0,r1 + 0x010006aa: 0631 1. LSLS r1,r6,#24 + 0x010006ac: 4301 .C ORRS r1,r1,r0 + 0x010006ae: d110 .. BNE 0x10006d2 ; strncmp + 78 + 0x010006b0: b298 .. UXTH r0,r3 + 0x010006b2: b2a1 .. UXTH r1,r4 + 0x010006b4: 1a40 @. SUBS r0,r0,r1 + 0x010006b6: 0431 1. LSLS r1,r6,#16 + 0x010006b8: 4301 .C ORRS r1,r1,r0 + 0x010006ba: d10a .. BNE 0x10006d2 ; strncmp + 78 + 0x010006bc: 0218 .. LSLS r0,r3,#8 + 0x010006be: 0221 !. LSLS r1,r4,#8 + 0x010006c0: 0a00 .. LSRS r0,r0,#8 + 0x010006c2: 0a09 .. LSRS r1,r1,#8 + 0x010006c4: 1a40 @. SUBS r0,r0,r1 + 0x010006c6: 0231 1. LSLS r1,r6,#8 + 0x010006c8: 4301 .C ORRS r1,r1,r0 + 0x010006ca: d102 .. BNE 0x10006d2 ; strncmp + 78 + 0x010006cc: 0e18 .. LSRS r0,r3,#24 + 0x010006ce: 0e21 !. LSRS r1,r4,#24 + 0x010006d0: 1a40 @. SUBS r0,r0,r1 + 0x010006d2: bdf0 .. POP {r4-r7,pc} + 0x010006d4: 42a3 .B CMP r3,r4 + 0x010006d6: d0dc .. BEQ 0x1000692 ; strncmp + 14 + 0x010006d8: ba18 .. REV r0,r3 + 0x010006da: ba21 !. REV r1,r4 + 0x010006dc: 4288 .B CMP r0,r1 + 0x010006de: d901 .. BLS 0x10006e4 ; strncmp + 96 + 0x010006e0: 2001 . MOVS r0,#1 + 0x010006e2: bdf0 .. POP {r4-r7,pc} + 0x010006e4: 2000 . MOVS r0,#0 + 0x010006e6: 43c0 .C MVNS r0,r0 + 0x010006e8: bdf0 .. POP {r4-r7,pc} + 0x010006ea: 2a00 .* CMP r2,#0 + 0x010006ec: d101 .. BNE 0x10006f2 ; strncmp + 110 + 0x010006ee: 2000 . MOVS r0,#0 + 0x010006f0: bdf0 .. POP {r4-r7,pc} + 0x010006f2: 7803 .x LDRB r3,[r0,#0] + 0x010006f4: 780c .x LDRB r4,[r1,#0] + 0x010006f6: 1c40 @. ADDS r0,r0,#1 + 0x010006f8: 1c49 I. ADDS r1,r1,#1 + 0x010006fa: 2b00 .+ CMP r3,#0 + 0x010006fc: d00d .. BEQ 0x100071a ; strncmp + 150 + 0x010006fe: 42a3 .B CMP r3,r4 + 0x01000700: d10b .. BNE 0x100071a ; strncmp + 150 + 0x01000702: 1e52 R. SUBS r2,r2,#1 + 0x01000704: d009 .. BEQ 0x100071a ; strncmp + 150 + 0x01000706: 7803 .x LDRB r3,[r0,#0] + 0x01000708: 780c .x LDRB r4,[r1,#0] + 0x0100070a: 1c40 @. ADDS r0,r0,#1 + 0x0100070c: 1c49 I. ADDS r1,r1,#1 + 0x0100070e: 2b00 .+ CMP r3,#0 + 0x01000710: d003 .. BEQ 0x100071a ; strncmp + 150 + 0x01000712: 42a3 .B CMP r3,r4 + 0x01000714: d101 .. BNE 0x100071a ; strncmp + 150 + 0x01000716: 1e52 R. SUBS r2,r2,#1 + 0x01000718: d1eb .. BNE 0x10006f2 ; strncmp + 110 + 0x0100071a: 1b18 .. SUBS r0,r3,r4 + 0x0100071c: bdf0 .. POP {r4-r7,pc} + $d + 0x0100071e: 0000 .. DCW 0 + 0x01000720: 01010101 .... DCD 16843009 + $t + .text + strcat + 0x01000724: 1e42 B. SUBS r2,r0,#1 + 0x01000726: 7853 Sx LDRB r3,[r2,#1] + 0x01000728: 1c52 R. ADDS r2,r2,#1 + 0x0100072a: 2b00 .+ CMP r3,#0 + 0x0100072c: d1fb .. BNE 0x1000726 ; strcat + 2 + 0x0100072e: 780b .x LDRB r3,[r1,#0] + 0x01000730: 1c49 I. ADDS r1,r1,#1 + 0x01000732: 7013 .p STRB r3,[r2,#0] + 0x01000734: 1c52 R. ADDS r2,r2,#1 + 0x01000736: 2b00 .+ CMP r3,#0 + 0x01000738: d1f9 .. BNE 0x100072e ; strcat + 10 + 0x0100073a: 4770 pG BX lr + .text + __aeabi_memcpy + __rt_memcpy + 0x0100073c: b5f8 .. PUSH {r3-r7,lr} + 0x0100073e: 2a04 .* CMP r2,#4 + 0x01000740: d32c ,. BCC 0x100079c ; __aeabi_memcpy + 96 + 0x01000742: 0783 .. LSLS r3,r0,#30 + 0x01000744: d012 .. BEQ 0x100076c ; __aeabi_memcpy + 48 + 0x01000746: 780b .x LDRB r3,[r1,#0] + 0x01000748: 1c49 I. ADDS r1,r1,#1 + 0x0100074a: 7003 .p STRB r3,[r0,#0] + 0x0100074c: 1c40 @. ADDS r0,r0,#1 + 0x0100074e: 1e52 R. SUBS r2,r2,#1 + 0x01000750: 0783 .. LSLS r3,r0,#30 + 0x01000752: d00b .. BEQ 0x100076c ; __aeabi_memcpy + 48 + 0x01000754: 780b .x LDRB r3,[r1,#0] + 0x01000756: 1c49 I. ADDS r1,r1,#1 + 0x01000758: 7003 .p STRB r3,[r0,#0] + 0x0100075a: 1c40 @. ADDS r0,r0,#1 + 0x0100075c: 1e52 R. SUBS r2,r2,#1 + 0x0100075e: 0783 .. LSLS r3,r0,#30 + 0x01000760: d004 .. BEQ 0x100076c ; __aeabi_memcpy + 48 + 0x01000762: 780b .x LDRB r3,[r1,#0] + 0x01000764: 1c49 I. ADDS r1,r1,#1 + 0x01000766: 7003 .p STRB r3,[r0,#0] + 0x01000768: 1c40 @. ADDS r0,r0,#1 + 0x0100076a: 1e52 R. SUBS r2,r2,#1 + 0x0100076c: 078b .. LSLS r3,r1,#30 + 0x0100076e: 0f9b .. LSRS r3,r3,#30 + 0x01000770: d005 .. BEQ 0x100077e ; __aeabi_memcpy + 66 + 0x01000772: 1ac9 .. SUBS r1,r1,r3 + 0x01000774: 00df .. LSLS r7,r3,#3 + 0x01000776: 2320 # MOVS r3,#0x20 + 0x01000778: 1bde .. SUBS r6,r3,r7 + 0x0100077a: c908 .. LDM r1!,{r3} + 0x0100077c: e00a .. B 0x1000794 ; __aeabi_memcpy + 88 + 0x0100077e: f7fffe83 .... BL __aeabi_memcpy4 ; 0x1000488 + 0x01000782: bdf8 .. POP {r3-r7,pc} + 0x01000784: 461d .F MOV r5,r3 + 0x01000786: c908 .. LDM r1!,{r3} + 0x01000788: 40fd .@ LSRS r5,r5,r7 + 0x0100078a: 461c .F MOV r4,r3 + 0x0100078c: 40b4 .@ LSLS r4,r4,r6 + 0x0100078e: 432c ,C ORRS r4,r4,r5 + 0x01000790: c010 .. STM r0!,{r4} + 0x01000792: 1f12 .. SUBS r2,r2,#4 + 0x01000794: 2a04 .* CMP r2,#4 + 0x01000796: d2f5 .. BCS 0x1000784 ; __aeabi_memcpy + 72 + 0x01000798: 08f3 .. LSRS r3,r6,#3 + 0x0100079a: 1ac9 .. SUBS r1,r1,r3 + 0x0100079c: 1e52 R. SUBS r2,r2,#1 + 0x0100079e: d4f0 .. BMI 0x1000782 ; __aeabi_memcpy + 70 + 0x010007a0: 780b .x LDRB r3,[r1,#0] + 0x010007a2: 1c49 I. ADDS r1,r1,#1 + 0x010007a4: 7003 .p STRB r3,[r0,#0] + 0x010007a6: 1c40 @. ADDS r0,r0,#1 + 0x010007a8: 1e52 R. SUBS r2,r2,#1 + 0x010007aa: d4ea .. BMI 0x1000782 ; __aeabi_memcpy + 70 + 0x010007ac: 780b .x LDRB r3,[r1,#0] + 0x010007ae: 1c49 I. ADDS r1,r1,#1 + 0x010007b0: 7003 .p STRB r3,[r0,#0] + 0x010007b2: 1c40 @. ADDS r0,r0,#1 + 0x010007b4: 2a01 .* CMP r2,#1 + 0x010007b6: d4e4 .. BMI 0x1000782 ; __aeabi_memcpy + 70 + 0x010007b8: 7809 .x LDRB r1,[r1,#0] + 0x010007ba: 7001 .p STRB r1,[r0,#0] + 0x010007bc: bdf8 .. POP {r3-r7,pc} + .text + _memset_w + 0x010007be: e001 .. B 0x10007c4 ; _memset_w + 6 + 0x010007c0: c004 .. STM r0!,{r2} + 0x010007c2: 1f09 .. SUBS r1,r1,#4 + 0x010007c4: 2904 .) CMP r1,#4 + 0x010007c6: d2fb .. BCS 0x10007c0 ; _memset_w + 2 + 0x010007c8: 078b .. LSLS r3,r1,#30 + 0x010007ca: d501 .. BPL 0x10007d0 ; _memset_w + 18 + 0x010007cc: 8002 .. STRH r2,[r0,#0] + 0x010007ce: 1c80 .. ADDS r0,r0,#2 + 0x010007d0: 07c9 .. LSLS r1,r1,#31 + 0x010007d2: d000 .. BEQ 0x10007d6 ; _memset_w + 24 + 0x010007d4: 7002 .p STRB r2,[r0,#0] + 0x010007d6: 4770 pG BX lr + _memset + 0x010007d8: 2900 .) CMP r1,#0 + 0x010007da: d00b .. BEQ 0x10007f4 ; _memset + 28 + 0x010007dc: 07c3 .. LSLS r3,r0,#31 + 0x010007de: d002 .. BEQ 0x10007e6 ; _memset + 14 + 0x010007e0: 7002 .p STRB r2,[r0,#0] + 0x010007e2: 1c40 @. ADDS r0,r0,#1 + 0x010007e4: 1e49 I. SUBS r1,r1,#1 + 0x010007e6: 2902 .) CMP r1,#2 + 0x010007e8: d304 .. BCC 0x10007f4 ; _memset + 28 + 0x010007ea: 0783 .. LSLS r3,r0,#30 + 0x010007ec: d502 .. BPL 0x10007f4 ; _memset + 28 + 0x010007ee: 8002 .. STRH r2,[r0,#0] + 0x010007f0: 1c80 .. ADDS r0,r0,#2 + 0x010007f2: 1e89 .. SUBS r1,r1,#2 + 0x010007f4: e7e3 .. B _memset_w ; 0x10007be + __aeabi_memclr + __rt_memclr + 0x010007f6: 2200 ." MOVS r2,#0 + 0x010007f8: e7ee .. B _memset ; 0x10007d8 + __aeabi_memclr4 + __aeabi_memclr8 + __rt_memclr_w + 0x010007fa: 2200 ." MOVS r2,#0 + 0x010007fc: e7df .. B _memset_w ; 0x10007be + 0x010007fe: 0000 .. MOVS r0,r0 + .text + strncpy + 0x01000800: b5f8 .. PUSH {r3-r7,lr} + 0x01000802: 4607 .F MOV r7,r0 + 0x01000804: 460b .F MOV r3,r1 + 0x01000806: 4639 9F MOV r1,r7 + 0x01000808: 4319 .C ORRS r1,r1,r3 + 0x0100080a: 0789 .. LSLS r1,r1,#30 + 0x0100080c: d113 .. BNE 0x1000836 ; strncpy + 54 + 0x0100080e: 4c16 .L LDR r4,[pc,#88] ; [0x1000868] = 0x1010101 + 0x01000810: 01e6 .. LSLS r6,r4,#7 + 0x01000812: 2a04 .* CMP r2,#4 + 0x01000814: d30f .. BCC 0x1000836 ; strncpy + 54 + 0x01000816: cb02 .. LDM r3!,{r1} + 0x01000818: 1b0d .. SUBS r5,r1,r4 + 0x0100081a: 438d .C BICS r5,r5,r1 + 0x0100081c: 4235 5B TST r5,r6 + 0x0100081e: d102 .. BNE 0x1000826 ; strncpy + 38 + 0x01000820: c002 .. STM r0!,{r1} + 0x01000822: 1f12 .. SUBS r2,r2,#4 + 0x01000824: e7f5 .. B 0x1000812 ; strncpy + 18 + 0x01000826: b2cb .. UXTB r3,r1 + 0x01000828: 7003 .p STRB r3,[r0,#0] + 0x0100082a: 1c40 @. ADDS r0,r0,#1 + 0x0100082c: 1e52 R. SUBS r2,r2,#1 + 0x0100082e: 2b00 .+ CMP r3,#0 + 0x01000830: d013 .. BEQ 0x100085a ; strncpy + 90 + 0x01000832: 0a09 .. LSRS r1,r1,#8 + 0x01000834: e7f7 .. B 0x1000826 ; strncpy + 38 + 0x01000836: 2a00 .* CMP r2,#0 + 0x01000838: d014 .. BEQ 0x1000864 ; strncpy + 100 + 0x0100083a: 7819 .x LDRB r1,[r3,#0] + 0x0100083c: 1e52 R. SUBS r2,r2,#1 + 0x0100083e: 1c5b [. ADDS r3,r3,#1 + 0x01000840: 7001 .p STRB r1,[r0,#0] + 0x01000842: 1c40 @. ADDS r0,r0,#1 + 0x01000844: 2900 .) CMP r1,#0 + 0x01000846: d008 .. BEQ 0x100085a ; strncpy + 90 + 0x01000848: 2a00 .* CMP r2,#0 + 0x0100084a: d00b .. BEQ 0x1000864 ; strncpy + 100 + 0x0100084c: 7819 .x LDRB r1,[r3,#0] + 0x0100084e: 1e52 R. SUBS r2,r2,#1 + 0x01000850: 1c5b [. ADDS r3,r3,#1 + 0x01000852: 7001 .p STRB r1,[r0,#0] + 0x01000854: 1c40 @. ADDS r0,r0,#1 + 0x01000856: 2900 .) CMP r1,#0 + 0x01000858: d1ed .. BNE 0x1000836 ; strncpy + 54 + 0x0100085a: 2a00 .* CMP r2,#0 + 0x0100085c: d002 .. BEQ 0x1000864 ; strncpy + 100 + 0x0100085e: 4611 .F MOV r1,r2 + 0x01000860: f7ffffc9 .... BL __aeabi_memclr ; 0x10007f6 + 0x01000864: 4638 8F MOV r0,r7 + 0x01000866: bdf8 .. POP {r3-r7,pc} + $d + 0x01000868: 01010101 .... DCD 16843009 + $t + .text + __aeabi_uidiv + __aeabi_uidivmod + 0x0100086c: 2200 ." MOVS r2,#0 + 0x0100086e: 0903 .. LSRS r3,r0,#4 + 0x01000870: 428b .B CMP r3,r1 + 0x01000872: d32c ,. BCC 0x10008ce ; __aeabi_idiv + 78 + 0x01000874: 0a03 .. LSRS r3,r0,#8 + 0x01000876: 428b .B CMP r3,r1 + 0x01000878: d311 .. BCC 0x100089e ; __aeabi_idiv + 30 + 0x0100087a: 2300 .# MOVS r3,#0 + 0x0100087c: 469c .F MOV r12,r3 + 0x0100087e: e04e N. B 0x100091e ; __aeabi_idiv + 158 + __aeabi_idiv + __aeabi_idivmod + 0x01000880: 4603 .F MOV r3,r0 + 0x01000882: 430b .C ORRS r3,r3,r1 + 0x01000884: d43c <. BMI 0x1000900 ; __aeabi_idiv + 128 + 0x01000886: 2200 ." MOVS r2,#0 + 0x01000888: 0843 C. LSRS r3,r0,#1 + 0x0100088a: 428b .B CMP r3,r1 + 0x0100088c: d331 1. BCC 0x10008f2 ; __aeabi_idiv + 114 + 0x0100088e: 0903 .. LSRS r3,r0,#4 + 0x01000890: 428b .B CMP r3,r1 + 0x01000892: d31c .. BCC 0x10008ce ; __aeabi_idiv + 78 + 0x01000894: 0a03 .. LSRS r3,r0,#8 + 0x01000896: 428b .B CMP r3,r1 + 0x01000898: d301 .. BCC 0x100089e ; __aeabi_idiv + 30 + 0x0100089a: 4694 .F MOV r12,r2 + 0x0100089c: e03f ?. B 0x100091e ; __aeabi_idiv + 158 + 0x0100089e: 09c3 .. LSRS r3,r0,#7 + 0x010008a0: 428b .B CMP r3,r1 + 0x010008a2: d301 .. BCC 0x10008a8 ; __aeabi_idiv + 40 + 0x010008a4: 01cb .. LSLS r3,r1,#7 + 0x010008a6: 1ac0 .. SUBS r0,r0,r3 + 0x010008a8: 4152 RA ADCS r2,r2,r2 + 0x010008aa: 0983 .. LSRS r3,r0,#6 + 0x010008ac: 428b .B CMP r3,r1 + 0x010008ae: d301 .. BCC 0x10008b4 ; __aeabi_idiv + 52 + 0x010008b0: 018b .. LSLS r3,r1,#6 + 0x010008b2: 1ac0 .. SUBS r0,r0,r3 + 0x010008b4: 4152 RA ADCS r2,r2,r2 + 0x010008b6: 0943 C. LSRS r3,r0,#5 + 0x010008b8: 428b .B CMP r3,r1 + 0x010008ba: d301 .. BCC 0x10008c0 ; __aeabi_idiv + 64 + 0x010008bc: 014b K. LSLS r3,r1,#5 + 0x010008be: 1ac0 .. SUBS r0,r0,r3 + 0x010008c0: 4152 RA ADCS r2,r2,r2 + 0x010008c2: 0903 .. LSRS r3,r0,#4 + 0x010008c4: 428b .B CMP r3,r1 + 0x010008c6: d301 .. BCC 0x10008cc ; __aeabi_idiv + 76 + 0x010008c8: 010b .. LSLS r3,r1,#4 + 0x010008ca: 1ac0 .. SUBS r0,r0,r3 + 0x010008cc: 4152 RA ADCS r2,r2,r2 + 0x010008ce: 08c3 .. LSRS r3,r0,#3 + 0x010008d0: 428b .B CMP r3,r1 + 0x010008d2: d301 .. BCC 0x10008d8 ; __aeabi_idiv + 88 + 0x010008d4: 00cb .. LSLS r3,r1,#3 + 0x010008d6: 1ac0 .. SUBS r0,r0,r3 + 0x010008d8: 4152 RA ADCS r2,r2,r2 + 0x010008da: 0883 .. LSRS r3,r0,#2 + 0x010008dc: 428b .B CMP r3,r1 + 0x010008de: d301 .. BCC 0x10008e4 ; __aeabi_idiv + 100 + 0x010008e0: 008b .. LSLS r3,r1,#2 + 0x010008e2: 1ac0 .. SUBS r0,r0,r3 + 0x010008e4: 4152 RA ADCS r2,r2,r2 + 0x010008e6: 0843 C. LSRS r3,r0,#1 + 0x010008e8: 428b .B CMP r3,r1 + 0x010008ea: d301 .. BCC 0x10008f0 ; __aeabi_idiv + 112 + 0x010008ec: 004b K. LSLS r3,r1,#1 + 0x010008ee: 1ac0 .. SUBS r0,r0,r3 + 0x010008f0: 4152 RA ADCS r2,r2,r2 + 0x010008f2: 1a41 A. SUBS r1,r0,r1 + 0x010008f4: d200 .. BCS 0x10008f8 ; __aeabi_idiv + 120 + 0x010008f6: 4601 .F MOV r1,r0 + 0x010008f8: 4152 RA ADCS r2,r2,r2 + 0x010008fa: 4610 .F MOV r0,r2 + 0x010008fc: 4770 pG BX lr + 0x010008fe: e05d ]. B 0x10009bc ; __aeabi_idiv + 316 + 0x01000900: 0fca .. LSRS r2,r1,#31 + 0x01000902: d000 .. BEQ 0x1000906 ; __aeabi_idiv + 134 + 0x01000904: 4249 IB RSBS r1,r1,#0 + 0x01000906: 1003 .. ASRS r3,r0,#32 + 0x01000908: d300 .. BCC 0x100090c ; __aeabi_idiv + 140 + 0x0100090a: 4240 @B RSBS r0,r0,#0 + 0x0100090c: 4053 S@ EORS r3,r3,r2 + 0x0100090e: 2200 ." MOVS r2,#0 + 0x01000910: 469c .F MOV r12,r3 + 0x01000912: 0903 .. LSRS r3,r0,#4 + 0x01000914: 428b .B CMP r3,r1 + 0x01000916: d32d -. BCC 0x1000974 ; __aeabi_idiv + 244 + 0x01000918: 0a03 .. LSRS r3,r0,#8 + 0x0100091a: 428b .B CMP r3,r1 + 0x0100091c: d312 .. BCC 0x1000944 ; __aeabi_idiv + 196 + 0x0100091e: 22fc ." MOVS r2,#0xfc + 0x01000920: 0189 .. LSLS r1,r1,#6 + 0x01000922: ba12 .. REV r2,r2 + 0x01000924: 0a03 .. LSRS r3,r0,#8 + 0x01000926: 428b .B CMP r3,r1 + 0x01000928: d30c .. BCC 0x1000944 ; __aeabi_idiv + 196 + 0x0100092a: 0189 .. LSLS r1,r1,#6 + 0x0100092c: 1192 .. ASRS r2,r2,#6 + 0x0100092e: 428b .B CMP r3,r1 + 0x01000930: d308 .. BCC 0x1000944 ; __aeabi_idiv + 196 + 0x01000932: 0189 .. LSLS r1,r1,#6 + 0x01000934: 1192 .. ASRS r2,r2,#6 + 0x01000936: 428b .B CMP r3,r1 + 0x01000938: d304 .. BCC 0x1000944 ; __aeabi_idiv + 196 + 0x0100093a: 0189 .. LSLS r1,r1,#6 + 0x0100093c: d03a :. BEQ 0x10009b4 ; __aeabi_idiv + 308 + 0x0100093e: 1192 .. ASRS r2,r2,#6 + 0x01000940: e000 .. B 0x1000944 ; __aeabi_idiv + 196 + 0x01000942: 0989 .. LSRS r1,r1,#6 + 0x01000944: 09c3 .. LSRS r3,r0,#7 + 0x01000946: 428b .B CMP r3,r1 + 0x01000948: d301 .. BCC 0x100094e ; __aeabi_idiv + 206 + 0x0100094a: 01cb .. LSLS r3,r1,#7 + 0x0100094c: 1ac0 .. SUBS r0,r0,r3 + 0x0100094e: 4152 RA ADCS r2,r2,r2 + 0x01000950: 0983 .. LSRS r3,r0,#6 + 0x01000952: 428b .B CMP r3,r1 + 0x01000954: d301 .. BCC 0x100095a ; __aeabi_idiv + 218 + 0x01000956: 018b .. LSLS r3,r1,#6 + 0x01000958: 1ac0 .. SUBS r0,r0,r3 + 0x0100095a: 4152 RA ADCS r2,r2,r2 + 0x0100095c: 0943 C. LSRS r3,r0,#5 + 0x0100095e: 428b .B CMP r3,r1 + 0x01000960: d301 .. BCC 0x1000966 ; __aeabi_idiv + 230 + 0x01000962: 014b K. LSLS r3,r1,#5 + 0x01000964: 1ac0 .. SUBS r0,r0,r3 + 0x01000966: 4152 RA ADCS r2,r2,r2 + 0x01000968: 0903 .. LSRS r3,r0,#4 + 0x0100096a: 428b .B CMP r3,r1 + 0x0100096c: d301 .. BCC 0x1000972 ; __aeabi_idiv + 242 + 0x0100096e: 010b .. LSLS r3,r1,#4 + 0x01000970: 1ac0 .. SUBS r0,r0,r3 + 0x01000972: 4152 RA ADCS r2,r2,r2 + 0x01000974: 08c3 .. LSRS r3,r0,#3 + 0x01000976: 428b .B CMP r3,r1 + 0x01000978: d301 .. BCC 0x100097e ; __aeabi_idiv + 254 + 0x0100097a: 00cb .. LSLS r3,r1,#3 + 0x0100097c: 1ac0 .. SUBS r0,r0,r3 + 0x0100097e: 4152 RA ADCS r2,r2,r2 + 0x01000980: 0883 .. LSRS r3,r0,#2 + 0x01000982: 428b .B CMP r3,r1 + 0x01000984: d301 .. BCC 0x100098a ; __aeabi_idiv + 266 + 0x01000986: 008b .. LSLS r3,r1,#2 + 0x01000988: 1ac0 .. SUBS r0,r0,r3 + 0x0100098a: 4152 RA ADCS r2,r2,r2 + 0x0100098c: d2d9 .. BCS 0x1000942 ; __aeabi_idiv + 194 + 0x0100098e: 0843 C. LSRS r3,r0,#1 + 0x01000990: 428b .B CMP r3,r1 + 0x01000992: d301 .. BCC 0x1000998 ; __aeabi_idiv + 280 + 0x01000994: 004b K. LSLS r3,r1,#1 + 0x01000996: 1ac0 .. SUBS r0,r0,r3 + 0x01000998: 4152 RA ADCS r2,r2,r2 + 0x0100099a: 1a41 A. SUBS r1,r0,r1 + 0x0100099c: d200 .. BCS 0x10009a0 ; __aeabi_idiv + 288 + 0x0100099e: 4601 .F MOV r1,r0 + 0x010009a0: 4663 cF MOV r3,r12 + 0x010009a2: 4152 RA ADCS r2,r2,r2 + 0x010009a4: 105b [. ASRS r3,r3,#1 + 0x010009a6: 4610 .F MOV r0,r2 + 0x010009a8: d301 .. BCC 0x10009ae ; __aeabi_idiv + 302 + 0x010009aa: 4240 @B RSBS r0,r0,#0 + 0x010009ac: 2b00 .+ CMP r3,#0 + 0x010009ae: d500 .. BPL 0x10009b2 ; __aeabi_idiv + 306 + 0x010009b0: 4249 IB RSBS r1,r1,#0 + 0x010009b2: 4770 pG BX lr + 0x010009b4: 4663 cF MOV r3,r12 + 0x010009b6: 105b [. ASRS r3,r3,#1 + 0x010009b8: d300 .. BCC 0x10009bc ; __aeabi_idiv + 316 + 0x010009ba: 4240 @B RSBS r0,r0,#0 + 0x010009bc: b501 .. PUSH {r0,lr} + 0x010009be: 2000 . MOVS r0,#0 + 0x010009c0: 46c0 .F MOV r8,r8 + 0x010009c2: 46c0 .F MOV r8,r8 + 0x010009c4: bd02 .. POP {r1,pc} + .text + __use_two_region_memory + 0x010009c6: 4770 pG BX lr + __rt_heap_escrow$2region + 0x010009c8: 4770 pG BX lr + __rt_heap_expand$2region + 0x010009ca: 4770 pG BX lr + .text + __user_setup_stackheap + 0x010009cc: 4675 uF MOV r5,lr + 0x010009ce: f000f825 ..%. BL __user_libspace ; 0x1000a1c + 0x010009d2: 46ae .F MOV lr,r5 + 0x010009d4: 0005 .. MOVS r5,r0 + 0x010009d6: 4669 iF MOV r1,sp + 0x010009d8: 4653 SF MOV r3,r10 + 0x010009da: 08c0 .. LSRS r0,r0,#3 + 0x010009dc: 00c0 .. LSLS r0,r0,#3 + 0x010009de: 4685 .F MOV sp,r0 + 0x010009e0: b018 .. ADD sp,sp,#0x60 + 0x010009e2: b520 . PUSH {r5,lr} + 0x010009e4: f7fffcac .... BL __user_initial_stackheap ; 0x1000340 + 0x010009e8: bc60 `. POP {r5,r6} + 0x010009ea: 2700 .' MOVS r7,#0 + 0x010009ec: 0849 I. LSRS r1,r1,#1 + 0x010009ee: 46b6 .F MOV lr,r6 + 0x010009f0: 2600 .& MOVS r6,#0 + 0x010009f2: c5c0 .. STM r5!,{r6,r7} + 0x010009f4: c5c0 .. STM r5!,{r6,r7} + 0x010009f6: c5c0 .. STM r5!,{r6,r7} + 0x010009f8: c5c0 .. STM r5!,{r6,r7} + 0x010009fa: c5c0 .. STM r5!,{r6,r7} + 0x010009fc: c5c0 .. STM r5!,{r6,r7} + 0x010009fe: c5c0 .. STM r5!,{r6,r7} + 0x01000a00: c5c0 .. STM r5!,{r6,r7} + 0x01000a02: 3d40 @= SUBS r5,r5,#0x40 + 0x01000a04: 0049 I. LSLS r1,r1,#1 + 0x01000a06: 468d .F MOV sp,r1 + 0x01000a08: 4770 pG BX lr + .text + exit + 0x01000a0a: b510 .. PUSH {r4,lr} + 0x01000a0c: 4604 .F MOV r4,r0 + 0x01000a0e: 46c0 .F MOV r8,r8 + 0x01000a10: 46c0 .F MOV r8,r8 + 0x01000a12: 4620 F MOV r0,r4 + 0x01000a14: f7fffd31 ..1. BL __rt_exit ; 0x100047a + 0x01000a18: bd10 .. POP {r4,pc} + 0x01000a1a: 0000 .. MOVS r0,r0 + .text + __user_libspace + __user_perproc_libspace + __user_perthread_libspace + 0x01000a1c: 4800 .H LDR r0,[pc,#0] ; [0x1000a20] = 0x20da4 + 0x01000a1e: 4770 pG BX lr + $d + 0x01000a20: 00020da4 .... DCD 134564 + $t + .text + _sys_exit + 0x01000a24: 4901 .I LDR r1,[pc,#4] ; [0x1000a2c] = 0x20026 + 0x01000a26: 2018 . MOVS r0,#0x18 + 0x01000a28: beab .. BKPT #0xab + 0x01000a2a: e7fe .. B 0x1000a2a ; _sys_exit + 6 + $d + 0x01000a2c: 00020026 &... DCD 131110 + $t + .text + __I$use$semihosting + __use_no_semihosting_swi + 0x01000a30: 4770 pG BX lr + .text + .text + __decompress + __decompress1 + __semihosting_library_function + 0x01000a32: b570 p. PUSH {r4-r6,lr} + 0x01000a34: 188c .. ADDS r4,r1,r2 + 0x01000a36: 7805 .x LDRB r5,[r0,#0] + 0x01000a38: 1c40 @. ADDS r0,r0,#1 + 0x01000a3a: 076b k. LSLS r3,r5,#29 + 0x01000a3c: 0f5b [. LSRS r3,r3,#29 + 0x01000a3e: d101 .. BNE 0x1000a44 ; __decompress + 18 + 0x01000a40: 7803 .x LDRB r3,[r0,#0] + 0x01000a42: 1c40 @. ADDS r0,r0,#1 + 0x01000a44: 112a *. ASRS r2,r5,#4 + 0x01000a46: d106 .. BNE 0x1000a56 ; __decompress + 36 + 0x01000a48: 7802 .x LDRB r2,[r0,#0] + 0x01000a4a: 1c40 @. ADDS r0,r0,#1 + 0x01000a4c: e003 .. B 0x1000a56 ; __decompress + 36 + 0x01000a4e: 7806 .x LDRB r6,[r0,#0] + 0x01000a50: 1c40 @. ADDS r0,r0,#1 + 0x01000a52: 700e .p STRB r6,[r1,#0] + 0x01000a54: 1c49 I. ADDS r1,r1,#1 + 0x01000a56: 1e5b [. SUBS r3,r3,#1 + 0x01000a58: d1f9 .. BNE 0x1000a4e ; __decompress + 28 + 0x01000a5a: 072b +. LSLS r3,r5,#28 + 0x01000a5c: d405 .. BMI 0x1000a6a ; __decompress + 56 + 0x01000a5e: 2300 .# MOVS r3,#0 + 0x01000a60: 1e52 R. SUBS r2,r2,#1 + 0x01000a62: d40d .. BMI 0x1000a80 ; __decompress + 78 + 0x01000a64: 700b .p STRB r3,[r1,#0] + 0x01000a66: 1c49 I. ADDS r1,r1,#1 + 0x01000a68: e7fa .. B 0x1000a60 ; __decompress + 46 + 0x01000a6a: 7803 .x LDRB r3,[r0,#0] + 0x01000a6c: 1c40 @. ADDS r0,r0,#1 + 0x01000a6e: 1acb .. SUBS r3,r1,r3 + 0x01000a70: 1c92 .. ADDS r2,r2,#2 + 0x01000a72: e003 .. B 0x1000a7c ; __decompress + 74 + 0x01000a74: 781d .x LDRB r5,[r3,#0] + 0x01000a76: 700d .p STRB r5,[r1,#0] + 0x01000a78: 1c49 I. ADDS r1,r1,#1 + 0x01000a7a: 1c5b [. ADDS r3,r3,#1 + 0x01000a7c: 1e52 R. SUBS r2,r2,#1 + 0x01000a7e: d5f9 .. BPL 0x1000a74 ; __decompress + 66 + 0x01000a80: 42a1 .B CMP r1,r4 + 0x01000a82: d3d8 .. BCC 0x1000a36 ; __decompress + 4 + 0x01000a84: 2000 . MOVS r0,#0 + 0x01000a86: bd70 p. POP {r4-r6,pc} + i.$Sub$$main + main + 0x01000a88: b510 .. PUSH {r4,lr} + 0x01000a8a: f006f8f0 .... BL rtthread_startup ; 0x1006c6e + 0x01000a8e: 2000 . MOVS r0,#0 + 0x01000a90: bd10 .. POP {r4,pc} + 0x01000a92: 0000 .. MOVS r0,r0 + i.NVIC_DisableIRQ + NVIC_DisableIRQ + 0x01000a94: bf00 .. NOP + 0x01000a96: 2101 .! MOVS r1,#1 + 0x01000a98: 4081 .@ LSLS r1,r1,r0 + 0x01000a9a: 4a02 .J LDR r2,[pc,#8] ; [0x1000aa4] = 0xe000e180 + 0x01000a9c: 6011 .` STR r1,[r2,#0] + 0x01000a9e: bf00 .. NOP + 0x01000aa0: 4770 pG BX lr + $d + 0x01000aa2: 0000 .. DCW 0 + 0x01000aa4: e000e180 .... DCD 3758154112 + $t + i.NVIC_EnableIRQ + NVIC_EnableIRQ + 0x01000aa8: bf00 .. NOP + 0x01000aaa: 4904 .I LDR r1,[pc,#16] ; [0x1000abc] = 0xe000e100 + 0x01000aac: 6809 .h LDR r1,[r1,#0] + 0x01000aae: 2201 ." MOVS r2,#1 + 0x01000ab0: 4082 .@ LSLS r2,r2,r0 + 0x01000ab2: 4311 .C ORRS r1,r1,r2 + 0x01000ab4: 4a01 .J LDR r2,[pc,#4] ; [0x1000abc] = 0xe000e100 + 0x01000ab6: 6011 .` STR r1,[r2,#0] + 0x01000ab8: bf00 .. NOP + 0x01000aba: 4770 pG BX lr + $d + 0x01000abc: e000e100 .... DCD 3758153984 + $t + i.SysTick_Config + SysTick_Config + 0x01000ac0: 4601 .F MOV r1,r0 + 0x01000ac2: 1e49 I. SUBS r1,r1,#1 + 0x01000ac4: 2900 .) CMP r1,#0 + 0x01000ac6: d002 .. BEQ 0x1000ace ; SysTick_Config + 14 + 0x01000ac8: 480c .H LDR r0,[pc,#48] ; [0x1000afc] = 0xffffff + 0x01000aca: 4281 .B CMP r1,r0 + 0x01000acc: d901 .. BLS 0x1000ad2 ; SysTick_Config + 18 + 0x01000ace: 2001 . MOVS r0,#1 + 0x01000ad0: 4770 pG BX lr + 0x01000ad2: 480b .H LDR r0,[pc,#44] ; [0x1000b00] = 0xe000e000 + 0x01000ad4: 6900 .i LDR r0,[r0,#0x10] + 0x01000ad6: 0840 @. LSRS r0,r0,#1 + 0x01000ad8: 0040 @. LSLS r0,r0,#1 + 0x01000ada: 4a09 .J LDR r2,[pc,#36] ; [0x1000b00] = 0xe000e000 + 0x01000adc: 6110 .a STR r0,[r2,#0x10] + 0x01000ade: 4610 .F MOV r0,r2 + 0x01000ae0: 6141 Aa STR r1,[r0,#0x14] + 0x01000ae2: 2000 . MOVS r0,#0 + 0x01000ae4: 6190 .a STR r0,[r2,#0x18] + 0x01000ae6: 4a07 .J LDR r2,[pc,#28] ; [0x1000b04] = 0x20154 + 0x01000ae8: 6010 .` STR r0,[r2,#0] + 0x01000aea: 4805 .H LDR r0,[pc,#20] ; [0x1000b00] = 0xe000e000 + 0x01000aec: 6900 .i LDR r0,[r0,#0x10] + 0x01000aee: 2207 ." MOVS r2,#7 + 0x01000af0: 4310 .C ORRS r0,r0,r2 + 0x01000af2: 4a03 .J LDR r2,[pc,#12] ; [0x1000b00] = 0xe000e000 + 0x01000af4: 6110 .a STR r0,[r2,#0x10] + 0x01000af6: 2000 . MOVS r0,#0 + 0x01000af8: e7ea .. B 0x1000ad0 ; SysTick_Config + 16 + $d + 0x01000afa: 0000 .. DCW 0 + 0x01000afc: 00ffffff .... DCD 16777215 + 0x01000b00: e000e000 .... DCD 3758153728 + 0x01000b04: 00020154 T... DCD 131412 + $t + i.SysTick_Handler + SysTick_Handler + 0x01000b08: b510 .. PUSH {r4,lr} + 0x01000b0a: f003fc9b .... BL rt_interrupt_enter ; 0x1004444 + 0x01000b0e: f005fbed .... BL rt_tick_increase ; 0x10062ec + 0x01000b12: f003fcc1 .... BL rt_interrupt_leave ; 0x1004498 + 0x01000b16: bd10 .. POP {r4,pc} + i.UART0_IRQHandler + UART0_IRQHandler + 0x01000b18: b510 .. PUSH {r4,lr} + 0x01000b1a: f003fc93 .... BL rt_interrupt_enter ; 0x1004444 + 0x01000b1e: 4906 .I LDR r1,[pc,#24] ; [0x1000b38] = 0x20010 + 0x01000b20: 7808 .x LDRB r0,[r1,#0] + 0x01000b22: f000f80d .... BL UART_GetITIdentity ; 0x1000b40 + 0x01000b26: 2802 .( CMP r0,#2 + 0x01000b28: d103 .. BNE 0x1000b32 ; UART0_IRQHandler + 26 + 0x01000b2a: 2101 .! MOVS r1,#1 + 0x01000b2c: 4803 .H LDR r0,[pc,#12] ; [0x1000b3c] = 0x2019c + 0x01000b2e: f003fb7b ..{. BL rt_hw_serial_isr ; 0x1004228 + 0x01000b32: f003fcb1 .... BL rt_interrupt_leave ; 0x1004498 + 0x01000b36: bd10 .. POP {r4,pc} + $d + 0x01000b38: 00020010 .... DCD 131088 + 0x01000b3c: 0002019c .... DCD 131484 + $t + i.UART_GetITIdentity + UART_GetITIdentity + 0x01000b40: 4601 .F MOV r1,r0 + 0x01000b42: 2000 . MOVS r0,#0 + 0x01000b44: 2900 .) CMP r1,#0 + 0x01000b46: d002 .. BEQ 0x1000b4e ; UART_GetITIdentity + 14 + 0x01000b48: 2901 .) CMP r1,#1 + 0x01000b4a: d130 0. BNE 0x1000bae ; UART_GetITIdentity + 110 + 0x01000b4c: e017 .. B 0x1000b7e ; UART_GetITIdentity + 62 + 0x01000b4e: 4a19 .J LDR r2,[pc,#100] ; [0x1000bb4] = 0xf8b00 + 0x01000b50: 69d2 .i LDR r2,[r2,#0x1c] + 0x01000b52: 23ff .# MOVS r3,#0xff + 0x01000b54: 021b .. LSLS r3,r3,#8 + 0x01000b56: 401a .@ ANDS r2,r2,r3 + 0x01000b58: 2a00 .* CMP r2,#0 + 0x01000b5a: dd06 .. BLE 0x1000b6a ; UART_GetITIdentity + 42 + 0x01000b5c: 4a15 .J LDR r2,[pc,#84] ; [0x1000bb4] = 0xf8b00 + 0x01000b5e: 6a92 .j LDR r2,[r2,#0x28] + 0x01000b60: 1412 .. ASRS r2,r2,#16 + 0x01000b62: 2a00 .* CMP r2,#0 + 0x01000b64: dd01 .. BLE 0x1000b6a ; UART_GetITIdentity + 42 + 0x01000b66: 2002 . MOVS r0,#2 + 0x01000b68: e008 .. B 0x1000b7c ; UART_GetITIdentity + 60 + 0x01000b6a: 4a12 .J LDR r2,[pc,#72] ; [0x1000bb4] = 0xf8b00 + 0x01000b6c: 69d2 .i LDR r2,[r2,#0x1c] + 0x01000b6e: 0fd2 .. LSRS r2,r2,#31 + 0x01000b70: 07d2 .. LSLS r2,r2,#31 + 0x01000b72: 2a00 .* CMP r2,#0 + 0x01000b74: d001 .. BEQ 0x1000b7a ; UART_GetITIdentity + 58 + 0x01000b76: 2001 . MOVS r0,#1 + 0x01000b78: e000 .. B 0x1000b7c ; UART_GetITIdentity + 60 + 0x01000b7a: 2000 . MOVS r0,#0 + 0x01000b7c: e017 .. B 0x1000bae ; UART_GetITIdentity + 110 + 0x01000b7e: 4a0e .J LDR r2,[pc,#56] ; [0x1000bb8] = 0xf8c00 + 0x01000b80: 69d2 .i LDR r2,[r2,#0x1c] + 0x01000b82: 23ff .# MOVS r3,#0xff + 0x01000b84: 021b .. LSLS r3,r3,#8 + 0x01000b86: 401a .@ ANDS r2,r2,r3 + 0x01000b88: 2a00 .* CMP r2,#0 + 0x01000b8a: dd06 .. BLE 0x1000b9a ; UART_GetITIdentity + 90 + 0x01000b8c: 4a0a .J LDR r2,[pc,#40] ; [0x1000bb8] = 0xf8c00 + 0x01000b8e: 6a92 .j LDR r2,[r2,#0x28] + 0x01000b90: 1412 .. ASRS r2,r2,#16 + 0x01000b92: 2a00 .* CMP r2,#0 + 0x01000b94: dd01 .. BLE 0x1000b9a ; UART_GetITIdentity + 90 + 0x01000b96: 2002 . MOVS r0,#2 + 0x01000b98: e008 .. B 0x1000bac ; UART_GetITIdentity + 108 + 0x01000b9a: 4a07 .J LDR r2,[pc,#28] ; [0x1000bb8] = 0xf8c00 + 0x01000b9c: 69d2 .i LDR r2,[r2,#0x1c] + 0x01000b9e: 0fd2 .. LSRS r2,r2,#31 + 0x01000ba0: 07d2 .. LSLS r2,r2,#31 + 0x01000ba2: 2a00 .* CMP r2,#0 + 0x01000ba4: d001 .. BEQ 0x1000baa ; UART_GetITIdentity + 106 + 0x01000ba6: 2001 . MOVS r0,#1 + 0x01000ba8: e000 .. B 0x1000bac ; UART_GetITIdentity + 108 + 0x01000baa: 2000 . MOVS r0,#0 + 0x01000bac: bf00 .. NOP + 0x01000bae: bf00 .. NOP + 0x01000bb0: 4770 pG BX lr + $d + 0x01000bb2: 0000 .. DCW 0 + 0x01000bb4: 000f8b00 .... DCD 1018624 + 0x01000bb8: 000f8c00 .... DCD 1018880 + $t + i.UART_ITConfig + UART_ITConfig + 0x01000bbc: b570 p. PUSH {r4-r6,lr} + 0x01000bbe: 4606 .F MOV r6,r0 + 0x01000bc0: 460c .F MOV r4,r1 + 0x01000bc2: 4615 .F MOV r5,r2 + 0x01000bc4: 2e00 .. CMP r6,#0 + 0x01000bc6: d006 .. BEQ 0x1000bd6 ; UART_ITConfig + 26 + 0x01000bc8: 2e01 .. CMP r6,#1 + 0x01000bca: d004 .. BEQ 0x1000bd6 ; UART_ITConfig + 26 + 0x01000bcc: 4a2c ,J LDR r2,[pc,#176] ; [0x1000c80] = 0x1007c9e + 0x01000bce: 21f3 .! MOVS r1,#0xf3 + 0x01000bd0: a02c ,. ADR r0,{pc}+0xb4 ; 0x1000c84 + 0x01000bd2: f000fa3b ..;. BL _assert_handler ; 0x100104c + 0x01000bd6: 2c01 ., CMP r4,#1 + 0x01000bd8: d006 .. BEQ 0x1000be8 ; UART_ITConfig + 44 + 0x01000bda: 2c02 ., CMP r4,#2 + 0x01000bdc: d004 .. BEQ 0x1000be8 ; UART_ITConfig + 44 + 0x01000bde: 4a28 (J LDR r2,[pc,#160] ; [0x1000c80] = 0x1007c9e + 0x01000be0: 21f4 .! MOVS r1,#0xf4 + 0x01000be2: a028 (. ADR r0,{pc}+0xa2 ; 0x1000c84 + 0x01000be4: f000fa32 ..2. BL _assert_handler ; 0x100104c + 0x01000be8: 2e00 .. CMP r6,#0 + 0x01000bea: d002 .. BEQ 0x1000bf2 ; UART_ITConfig + 54 + 0x01000bec: 2e01 .. CMP r6,#1 + 0x01000bee: d144 D. BNE 0x1000c7a ; UART_ITConfig + 190 + 0x01000bf0: e021 !. B 0x1000c36 ; UART_ITConfig + 122 + 0x01000bf2: 2c02 ., CMP r4,#2 + 0x01000bf4: d110 .. BNE 0x1000c18 ; UART_ITConfig + 92 + 0x01000bf6: 2d00 .- CMP r5,#0 + 0x01000bf8: d006 .. BEQ 0x1000c08 ; UART_ITConfig + 76 + 0x01000bfa: 4828 (H LDR r0,[pc,#160] ; [0x1000c9c] = 0xf8b00 + 0x01000bfc: 69c0 .i LDR r0,[r0,#0x1c] + 0x01000bfe: 01e1 .. LSLS r1,r4,#7 + 0x01000c00: 4308 .C ORRS r0,r0,r1 + 0x01000c02: 4926 &I LDR r1,[pc,#152] ; [0x1000c9c] = 0xf8b00 + 0x01000c04: 61c8 .a STR r0,[r1,#0x1c] + 0x01000c06: e015 .. B 0x1000c34 ; UART_ITConfig + 120 + 0x01000c08: 4824 $H LDR r0,[pc,#144] ; [0x1000c9c] = 0xf8b00 + 0x01000c0a: 69c0 .i LDR r0,[r0,#0x1c] + 0x01000c0c: 21ff .! MOVS r1,#0xff + 0x01000c0e: 0209 .. LSLS r1,r1,#8 + 0x01000c10: 4388 .C BICS r0,r0,r1 + 0x01000c12: 4922 "I LDR r1,[pc,#136] ; [0x1000c9c] = 0xf8b00 + 0x01000c14: 61c8 .a STR r0,[r1,#0x1c] + 0x01000c16: e00d .. B 0x1000c34 ; UART_ITConfig + 120 + 0x01000c18: 2c01 ., CMP r4,#1 + 0x01000c1a: d10b .. BNE 0x1000c34 ; UART_ITConfig + 120 + 0x01000c1c: 481f .H LDR r0,[pc,#124] ; [0x1000c9c] = 0xf8b00 + 0x01000c1e: 69c0 .i LDR r0,[r0,#0x1c] + 0x01000c20: 0040 @. LSLS r0,r0,#1 + 0x01000c22: 0840 @. LSRS r0,r0,#1 + 0x01000c24: 491d .I LDR r1,[pc,#116] ; [0x1000c9c] = 0xf8b00 + 0x01000c26: 61c8 .a STR r0,[r1,#0x1c] + 0x01000c28: 4608 .F MOV r0,r1 + 0x01000c2a: 69c0 .i LDR r0,[r0,#0x1c] + 0x01000c2c: 07e9 .. LSLS r1,r5,#31 + 0x01000c2e: 4308 .C ORRS r0,r0,r1 + 0x01000c30: 491a .I LDR r1,[pc,#104] ; [0x1000c9c] = 0xf8b00 + 0x01000c32: 61c8 .a STR r0,[r1,#0x1c] + 0x01000c34: e021 !. B 0x1000c7a ; UART_ITConfig + 190 + 0x01000c36: 2c02 ., CMP r4,#2 + 0x01000c38: d110 .. BNE 0x1000c5c ; UART_ITConfig + 160 + 0x01000c3a: 2d00 .- CMP r5,#0 + 0x01000c3c: d006 .. BEQ 0x1000c4c ; UART_ITConfig + 144 + 0x01000c3e: 4818 .H LDR r0,[pc,#96] ; [0x1000ca0] = 0xf8c00 + 0x01000c40: 69c0 .i LDR r0,[r0,#0x1c] + 0x01000c42: 01e1 .. LSLS r1,r4,#7 + 0x01000c44: 4308 .C ORRS r0,r0,r1 + 0x01000c46: 4916 .I LDR r1,[pc,#88] ; [0x1000ca0] = 0xf8c00 + 0x01000c48: 61c8 .a STR r0,[r1,#0x1c] + 0x01000c4a: e015 .. B 0x1000c78 ; UART_ITConfig + 188 + 0x01000c4c: 4814 .H LDR r0,[pc,#80] ; [0x1000ca0] = 0xf8c00 + 0x01000c4e: 69c0 .i LDR r0,[r0,#0x1c] + 0x01000c50: 21ff .! MOVS r1,#0xff + 0x01000c52: 0209 .. LSLS r1,r1,#8 + 0x01000c54: 4388 .C BICS r0,r0,r1 + 0x01000c56: 4912 .I LDR r1,[pc,#72] ; [0x1000ca0] = 0xf8c00 + 0x01000c58: 61c8 .a STR r0,[r1,#0x1c] + 0x01000c5a: e00d .. B 0x1000c78 ; UART_ITConfig + 188 + 0x01000c5c: 2c01 ., CMP r4,#1 + 0x01000c5e: d10b .. BNE 0x1000c78 ; UART_ITConfig + 188 + 0x01000c60: 480f .H LDR r0,[pc,#60] ; [0x1000ca0] = 0xf8c00 + 0x01000c62: 69c0 .i LDR r0,[r0,#0x1c] + 0x01000c64: 0040 @. LSLS r0,r0,#1 + 0x01000c66: 0840 @. LSRS r0,r0,#1 + 0x01000c68: 490d .I LDR r1,[pc,#52] ; [0x1000ca0] = 0xf8c00 + 0x01000c6a: 61c8 .a STR r0,[r1,#0x1c] + 0x01000c6c: 4608 .F MOV r0,r1 + 0x01000c6e: 69c0 .i LDR r0,[r0,#0x1c] + 0x01000c70: 07e9 .. LSLS r1,r5,#31 + 0x01000c72: 4308 .C ORRS r0,r0,r1 + 0x01000c74: 490a .I LDR r1,[pc,#40] ; [0x1000ca0] = 0xf8c00 + 0x01000c76: 61c8 .a STR r0,[r1,#0x1c] + 0x01000c78: bf00 .. NOP + 0x01000c7a: bf00 .. NOP + 0x01000c7c: bd70 p. POP {r4-r6,pc} + $d + 0x01000c7e: 0000 .. DCW 0 + 0x01000c80: 01007c9e .|.. DCD 16809118 + 0x01000c84: 7262694c Libr DCD 1919052108 + 0x01000c88: 65697261 arie DCD 1701409377 + 0x01000c8c: 64735c73 s\sd DCD 1685281907 + 0x01000c90: 63795c6b k\yc DCD 1668897899 + 0x01000c94: 7261755f _uar DCD 1918989663 + 0x01000c98: 00632e74 t.c. DCD 6499956 + 0x01000c9c: 000f8b00 .... DCD 1018624 + 0x01000ca0: 000f8c00 .... DCD 1018880 + $t + i.UART_Init + UART_Init + 0x01000ca4: b5f8 .. PUSH {r3-r7,lr} + 0x01000ca6: 4605 .F MOV r5,r0 + 0x01000ca8: 460c .F MOV r4,r1 + 0x01000caa: 2600 .& MOVS r6,#0 + 0x01000cac: 2700 .' MOVS r7,#0 + 0x01000cae: 2d00 .- CMP r5,#0 + 0x01000cb0: d006 .. BEQ 0x1000cc0 ; UART_Init + 28 + 0x01000cb2: 2d01 .- CMP r5,#1 + 0x01000cb4: d004 .. BEQ 0x1000cc0 ; UART_Init + 28 + 0x01000cb6: 4a47 GJ LDR r2,[pc,#284] ; [0x1000dd4] = 0x1007c5c + 0x01000cb8: 219a .! MOVS r1,#0x9a + 0x01000cba: a047 G. ADR r0,{pc}+0x11e ; 0x1000dd8 + 0x01000cbc: f000f9c6 .... BL _assert_handler ; 0x100104c + 0x01000cc0: 7820 x LDRB r0,[r4,#0] + 0x01000cc2: 2840 @( CMP r0,#0x40 + 0x01000cc4: d007 .. BEQ 0x1000cd6 ; UART_Init + 50 + 0x01000cc6: 7820 x LDRB r0,[r4,#0] + 0x01000cc8: 2800 .( CMP r0,#0 + 0x01000cca: d004 .. BEQ 0x1000cd6 ; UART_Init + 50 + 0x01000ccc: 4a41 AJ LDR r2,[pc,#260] ; [0x1000dd4] = 0x1007c5c + 0x01000cce: 219b .! MOVS r1,#0x9b + 0x01000cd0: a041 A. ADR r0,{pc}+0x108 ; 0x1000dd8 + 0x01000cd2: f000f9bb .... BL _assert_handler ; 0x100104c + 0x01000cd6: 21b7 .! MOVS r1,#0xb7 + 0x01000cd8: 00c9 .. LSLS r1,r1,#3 + 0x01000cda: 6860 `h LDR r0,[r4,#4] + 0x01000cdc: 4288 .B CMP r0,r1 + 0x01000cde: d903 .. BLS 0x1000ce8 ; UART_Init + 68 + 0x01000ce0: 4943 CI LDR r1,[pc,#268] ; [0x1000df0] = 0x44aa21 + 0x01000ce2: 6860 `h LDR r0,[r4,#4] + 0x01000ce4: 4288 .B CMP r0,r1 + 0x01000ce6: d304 .. BCC 0x1000cf2 ; UART_Init + 78 + 0x01000ce8: 4a3a :J LDR r2,[pc,#232] ; [0x1000dd4] = 0x1007c5c + 0x01000cea: 219c .! MOVS r1,#0x9c + 0x01000cec: a03a :. ADR r0,{pc}+0xec ; 0x1000dd8 + 0x01000cee: f000f9ad .... BL _assert_handler ; 0x100104c + 0x01000cf2: 7aa0 .z LDRB r0,[r4,#0xa] + 0x01000cf4: 2800 .( CMP r0,#0 + 0x01000cf6: d00a .. BEQ 0x1000d0e ; UART_Init + 106 + 0x01000cf8: 7aa0 .z LDRB r0,[r4,#0xa] + 0x01000cfa: 2800 .( CMP r0,#0 + 0x01000cfc: d007 .. BEQ 0x1000d0e ; UART_Init + 106 + 0x01000cfe: 7aa0 .z LDRB r0,[r4,#0xa] + 0x01000d00: 2802 .( CMP r0,#2 + 0x01000d02: d004 .. BEQ 0x1000d0e ; UART_Init + 106 + 0x01000d04: 4a33 3J LDR r2,[pc,#204] ; [0x1000dd4] = 0x1007c5c + 0x01000d06: 219d .! MOVS r1,#0x9d + 0x01000d08: a033 3. ADR r0,{pc}+0xd0 ; 0x1000dd8 + 0x01000d0a: f000f99f .... BL _assert_handler ; 0x100104c + 0x01000d0e: 7ae0 .z LDRB r0,[r4,#0xb] + 0x01000d10: 2800 .( CMP r0,#0 + 0x01000d12: d007 .. BEQ 0x1000d24 ; UART_Init + 128 + 0x01000d14: 7ae0 .z LDRB r0,[r4,#0xb] + 0x01000d16: 2810 .( CMP r0,#0x10 + 0x01000d18: d004 .. BEQ 0x1000d24 ; UART_Init + 128 + 0x01000d1a: 4a2e .J LDR r2,[pc,#184] ; [0x1000dd4] = 0x1007c5c + 0x01000d1c: 219e .! MOVS r1,#0x9e + 0x01000d1e: a02e .. ADR r0,{pc}+0xba ; 0x1000dd8 + 0x01000d20: f000f994 .... BL _assert_handler ; 0x100104c + 0x01000d24: 7a60 `z LDRB r0,[r4,#9] + 0x01000d26: 2800 .( CMP r0,#0 + 0x01000d28: d007 .. BEQ 0x1000d3a ; UART_Init + 150 + 0x01000d2a: 7a60 `z LDRB r0,[r4,#9] + 0x01000d2c: 2808 .( CMP r0,#8 + 0x01000d2e: d004 .. BEQ 0x1000d3a ; UART_Init + 150 + 0x01000d30: 4a28 (J LDR r2,[pc,#160] ; [0x1000dd4] = 0x1007c5c + 0x01000d32: 219f .! MOVS r1,#0x9f + 0x01000d34: a028 (. ADR r0,{pc}+0xa4 ; 0x1000dd8 + 0x01000d36: f000f989 .... BL _assert_handler ; 0x100104c + 0x01000d3a: 482e .H LDR r0,[pc,#184] ; [0x1000df4] = 0x2dc6c00 + 0x01000d3c: 6861 ah LDR r1,[r4,#4] + 0x01000d3e: f7fffd95 .... BL __aeabi_uidiv ; 0x100086c + 0x01000d42: 0407 .. LSLS r7,r0,#16 + 0x01000d44: 7aa0 .z LDRB r0,[r4,#0xa] + 0x01000d46: 2101 .! MOVS r1,#1 + 0x01000d48: 4308 .C ORRS r0,r0,r1 + 0x01000d4a: 7a21 !z LDRB r1,[r4,#8] + 0x01000d4c: 4308 .C ORRS r0,r0,r1 + 0x01000d4e: 7a61 az LDRB r1,[r4,#9] + 0x01000d50: 4308 .C ORRS r0,r0,r1 + 0x01000d52: 7ae1 .z LDRB r1,[r4,#0xb] + 0x01000d54: 4308 .C ORRS r0,r0,r1 + 0x01000d56: 7821 !x LDRB r1,[r4,#0] + 0x01000d58: 4308 .C ORRS r0,r0,r1 + 0x01000d5a: 2180 .! MOVS r1,#0x80 + 0x01000d5c: 4308 .C ORRS r0,r0,r1 + 0x01000d5e: 4338 8C ORRS r0,r0,r7 + 0x01000d60: 4606 .F MOV r6,r0 + 0x01000d62: 2d00 .- CMP r5,#0 + 0x01000d64: d11a .. BNE 0x1000d9c ; UART_Init + 248 + 0x01000d66: 2000 . MOVS r0,#0 + 0x01000d68: 4923 #I LDR r1,[pc,#140] ; [0x1000df8] = 0xf8b00 + 0x01000d6a: 61c8 .a STR r0,[r1,#0x1c] + 0x01000d6c: 4823 #H LDR r0,[pc,#140] ; [0x1000dfc] = 0x205a4 + 0x01000d6e: 6048 H` STR r0,[r1,#4] + 0x01000d70: 2001 . MOVS r0,#1 + 0x01000d72: 0280 .. LSLS r0,r0,#10 + 0x01000d74: 6088 .` STR r0,[r1,#8] + 0x01000d76: 2001 . MOVS r0,#1 + 0x01000d78: 7308 .s STRB r0,[r1,#0xc] + 0x01000d7a: 4608 .F MOV r0,r1 + 0x01000d7c: 7bc0 .{ LDRB r0,[r0,#0xf] + 0x01000d7e: 2120 ! MOVS r1,#0x20 + 0x01000d80: 4308 .C ORRS r0,r0,r1 + 0x01000d82: 491d .I LDR r1,[pc,#116] ; [0x1000df8] = 0xf8b00 + 0x01000d84: 73c8 .s STRB r0,[r1,#0xf] + 0x01000d86: 4608 .F MOV r0,r1 + 0x01000d88: 7bc0 .{ LDRB r0,[r0,#0xf] + 0x01000d8a: 2120 ! MOVS r1,#0x20 + 0x01000d8c: 4388 .C BICS r0,r0,r1 + 0x01000d8e: 491a .I LDR r1,[pc,#104] ; [0x1000df8] = 0xf8b00 + 0x01000d90: 73c8 .s STRB r0,[r1,#0xf] + 0x01000d92: 2000 . MOVS r0,#0 + 0x01000d94: 61c8 .a STR r0,[r1,#0x1c] + 0x01000d96: 4608 .F MOV r0,r1 + 0x01000d98: 61c6 .a STR r6,[r0,#0x1c] + 0x01000d9a: e019 .. B 0x1000dd0 ; UART_Init + 300 + 0x01000d9c: 2000 . MOVS r0,#0 + 0x01000d9e: 4918 .I LDR r1,[pc,#96] ; [0x1000e00] = 0xf8c00 + 0x01000da0: 61c8 .a STR r0,[r1,#0x1c] + 0x01000da2: 4818 .H LDR r0,[pc,#96] ; [0x1000e04] = 0x209a4 + 0x01000da4: 6048 H` STR r0,[r1,#4] + 0x01000da6: 2001 . MOVS r0,#1 + 0x01000da8: 0280 .. LSLS r0,r0,#10 + 0x01000daa: 6088 .` STR r0,[r1,#8] + 0x01000dac: 2001 . MOVS r0,#1 + 0x01000dae: 7308 .s STRB r0,[r1,#0xc] + 0x01000db0: 4608 .F MOV r0,r1 + 0x01000db2: 7bc0 .{ LDRB r0,[r0,#0xf] + 0x01000db4: 2120 ! MOVS r1,#0x20 + 0x01000db6: 4308 .C ORRS r0,r0,r1 + 0x01000db8: 4911 .I LDR r1,[pc,#68] ; [0x1000e00] = 0xf8c00 + 0x01000dba: 73c8 .s STRB r0,[r1,#0xf] + 0x01000dbc: 4608 .F MOV r0,r1 + 0x01000dbe: 7bc0 .{ LDRB r0,[r0,#0xf] + 0x01000dc0: 2120 ! MOVS r1,#0x20 + 0x01000dc2: 4388 .C BICS r0,r0,r1 + 0x01000dc4: 490e .I LDR r1,[pc,#56] ; [0x1000e00] = 0xf8c00 + 0x01000dc6: 73c8 .s STRB r0,[r1,#0xf] + 0x01000dc8: 2000 . MOVS r0,#0 + 0x01000dca: 61c8 .a STR r0,[r1,#0x1c] + 0x01000dcc: 4608 .F MOV r0,r1 + 0x01000dce: 61c6 .a STR r6,[r0,#0x1c] + 0x01000dd0: bdf8 .. POP {r3-r7,pc} + $d + 0x01000dd2: 0000 .. DCW 0 + 0x01000dd4: 01007c5c \|.. DCD 16809052 + 0x01000dd8: 7262694c Libr DCD 1919052108 + 0x01000ddc: 65697261 arie DCD 1701409377 + 0x01000de0: 64735c73 s\sd DCD 1685281907 + 0x01000de4: 63795c6b k\yc DCD 1668897899 + 0x01000de8: 7261755f _uar DCD 1918989663 + 0x01000dec: 00632e74 t.c. DCD 6499956 + 0x01000df0: 0044aa21 !.D. DCD 4500001 + 0x01000df4: 02dc6c00 .l.. DCD 48000000 + 0x01000df8: 000f8b00 .... DCD 1018624 + 0x01000dfc: 000205a4 .... DCD 132516 + 0x01000e00: 000f8c00 .... DCD 1018880 + 0x01000e04: 000209a4 .... DCD 133540 + $t + i.UART_IsUARTBusy + UART_IsUARTBusy + 0x01000e08: b510 .. PUSH {r4,lr} + 0x01000e0a: 4604 .F MOV r4,r0 + 0x01000e0c: 2c00 ., CMP r4,#0 + 0x01000e0e: d006 .. BEQ 0x1000e1e ; UART_IsUARTBusy + 22 + 0x01000e10: 2c01 ., CMP r4,#1 + 0x01000e12: d004 .. BEQ 0x1000e1e ; UART_IsUARTBusy + 22 + 0x01000e14: 4a0a .J LDR r2,[pc,#40] ; [0x1000e40] = 0x1007c8e + 0x01000e16: 21e5 .! MOVS r1,#0xe5 + 0x01000e18: a00a .. ADR r0,{pc}+0x2c ; 0x1000e44 + 0x01000e1a: f000f917 .... BL _assert_handler ; 0x100104c + 0x01000e1e: 2c00 ., CMP r4,#0 + 0x01000e20: d106 .. BNE 0x1000e30 ; UART_IsUARTBusy + 40 + 0x01000e22: 480e .H LDR r0,[pc,#56] ; [0x1000e5c] = 0xf8b00 + 0x01000e24: 6900 .i LDR r0,[r0,#0x10] + 0x01000e26: 07c0 .. LSLS r0,r0,#31 + 0x01000e28: 0fc0 .. LSRS r0,r0,#31 + 0x01000e2a: 2101 .! MOVS r1,#1 + 0x01000e2c: 4048 H@ EORS r0,r0,r1 + 0x01000e2e: bd10 .. POP {r4,pc} + 0x01000e30: 480b .H LDR r0,[pc,#44] ; [0x1000e60] = 0xf8c00 + 0x01000e32: 6900 .i LDR r0,[r0,#0x10] + 0x01000e34: 07c0 .. LSLS r0,r0,#31 + 0x01000e36: 0fc0 .. LSRS r0,r0,#31 + 0x01000e38: 2101 .! MOVS r1,#1 + 0x01000e3a: 4048 H@ EORS r0,r0,r1 + 0x01000e3c: e7f7 .. B 0x1000e2e ; UART_IsUARTBusy + 38 + $d + 0x01000e3e: 0000 .. DCW 0 + 0x01000e40: 01007c8e .|.. DCD 16809102 + 0x01000e44: 7262694c Libr DCD 1919052108 + 0x01000e48: 65697261 arie DCD 1701409377 + 0x01000e4c: 64735c73 s\sd DCD 1685281907 + 0x01000e50: 63795c6b k\yc DCD 1668897899 + 0x01000e54: 7261755f _uar DCD 1918989663 + 0x01000e58: 00632e74 t.c. DCD 6499956 + 0x01000e5c: 000f8b00 .... DCD 1018624 + 0x01000e60: 000f8c00 .... DCD 1018880 + $t + i.UART_ReceiveData + UART_ReceiveData + 0x01000e64: b510 .. PUSH {r4,lr} + 0x01000e66: 4604 .F MOV r4,r0 + 0x01000e68: 2c00 ., CMP r4,#0 + 0x01000e6a: d007 .. BEQ 0x1000e7c ; UART_ReceiveData + 24 + 0x01000e6c: 2c01 ., CMP r4,#1 + 0x01000e6e: d005 .. BEQ 0x1000e7c ; UART_ReceiveData + 24 + 0x01000e70: 4a06 .J LDR r2,[pc,#24] ; [0x1000e8c] = 0x1007cac + 0x01000e72: 21ff .! MOVS r1,#0xff + 0x01000e74: 3128 (1 ADDS r1,r1,#0x28 + 0x01000e76: a006 .. ADR r0,{pc}+0x1a ; 0x1000e90 + 0x01000e78: f000f8e8 .... BL _assert_handler ; 0x100104c + 0x01000e7c: 2c00 ., CMP r4,#0 + 0x01000e7e: d102 .. BNE 0x1000e86 ; UART_ReceiveData + 34 + 0x01000e80: 4809 .H LDR r0,[pc,#36] ; [0x1000ea8] = 0xf8b20 + 0x01000e82: 7900 .y LDRB r0,[r0,#4] + 0x01000e84: bd10 .. POP {r4,pc} + 0x01000e86: 4809 .H LDR r0,[pc,#36] ; [0x1000eac] = 0xf8c20 + 0x01000e88: 7900 .y LDRB r0,[r0,#4] + 0x01000e8a: e7fb .. B 0x1000e84 ; UART_ReceiveData + 32 + $d + 0x01000e8c: 01007cac .|.. DCD 16809132 + 0x01000e90: 7262694c Libr DCD 1919052108 + 0x01000e94: 65697261 arie DCD 1701409377 + 0x01000e98: 64735c73 s\sd DCD 1685281907 + 0x01000e9c: 63795c6b k\yc DCD 1668897899 + 0x01000ea0: 7261755f _uar DCD 1918989663 + 0x01000ea4: 00632e74 t.c. DCD 6499956 + 0x01000ea8: 000f8b20 ... DCD 1018656 + 0x01000eac: 000f8c20 ... DCD 1018912 + $t + i.UART_ReceiveDataLen + UART_ReceiveDataLen + 0x01000eb0: b510 .. PUSH {r4,lr} + 0x01000eb2: 4604 .F MOV r4,r0 + 0x01000eb4: 2c00 ., CMP r4,#0 + 0x01000eb6: d007 .. BEQ 0x1000ec8 ; UART_ReceiveDataLen + 24 + 0x01000eb8: 2c01 ., CMP r4,#1 + 0x01000eba: d005 .. BEQ 0x1000ec8 ; UART_ReceiveDataLen + 24 + 0x01000ebc: 4a07 .J LDR r2,[pc,#28] ; [0x1000edc] = 0x1007ce7 + 0x01000ebe: 21ff .! MOVS r1,#0xff + 0x01000ec0: 31a8 .1 ADDS r1,r1,#0xa8 + 0x01000ec2: a007 .. ADR r0,{pc}+0x1e ; 0x1000ee0 + 0x01000ec4: f000f8c2 .... BL _assert_handler ; 0x100104c + 0x01000ec8: 2c00 ., CMP r4,#0 + 0x01000eca: d103 .. BNE 0x1000ed4 ; UART_ReceiveDataLen + 36 + 0x01000ecc: 480a .H LDR r0,[pc,#40] ; [0x1000ef8] = 0xf8b00 + 0x01000ece: 6a80 .j LDR r0,[r0,#0x28] + 0x01000ed0: 0c00 .. LSRS r0,r0,#16 + 0x01000ed2: bd10 .. POP {r4,pc} + 0x01000ed4: 4809 .H LDR r0,[pc,#36] ; [0x1000efc] = 0xf8c00 + 0x01000ed6: 6a80 .j LDR r0,[r0,#0x28] + 0x01000ed8: 0c00 .. LSRS r0,r0,#16 + 0x01000eda: e7fa .. B 0x1000ed2 ; UART_ReceiveDataLen + 34 + $d + 0x01000edc: 01007ce7 .|.. DCD 16809191 + 0x01000ee0: 7262694c Libr DCD 1919052108 + 0x01000ee4: 65697261 arie DCD 1701409377 + 0x01000ee8: 64735c73 s\sd DCD 1685281907 + 0x01000eec: 63795c6b k\yc DCD 1668897899 + 0x01000ef0: 7261755f _uar DCD 1918989663 + 0x01000ef4: 00632e74 t.c. DCD 6499956 + 0x01000ef8: 000f8b00 .... DCD 1018624 + 0x01000efc: 000f8c00 .... DCD 1018880 + $t + i.UART_SendData + UART_SendData + 0x01000f00: b508 .. PUSH {r3,lr} + 0x01000f02: 9100 .. STR r1,[sp,#0] + 0x01000f04: 2800 .( CMP r0,#0 + 0x01000f06: d114 .. BNE 0x1000f32 ; UART_SendData + 50 + 0x01000f08: 466a jF MOV r2,sp + 0x01000f0a: 4b14 .K LDR r3,[pc,#80] ; [0x1000f5c] = 0xf8b00 + 0x01000f0c: 601a .` STR r2,[r3,#0] + 0x01000f0e: 461a .F MOV r2,r3 + 0x01000f10: 6892 .h LDR r2,[r2,#8] + 0x01000f12: b292 .. UXTH r2,r2 + 0x01000f14: 2301 .# MOVS r3,#1 + 0x01000f16: 041b .. LSLS r3,r3,#16 + 0x01000f18: 18d2 .. ADDS r2,r2,r3 + 0x01000f1a: 4b10 .K LDR r3,[pc,#64] ; [0x1000f5c] = 0xf8b00 + 0x01000f1c: 609a .` STR r2,[r3,#8] + 0x01000f1e: 2280 ." MOVS r2,#0x80 + 0x01000f20: 73da .s STRB r2,[r3,#0xf] + 0x01000f22: bf00 .. NOP + 0x01000f24: 4a0d .J LDR r2,[pc,#52] ; [0x1000f5c] = 0xf8b00 + 0x01000f26: 6912 .i LDR r2,[r2,#0x10] + 0x01000f28: 07d2 .. LSLS r2,r2,#31 + 0x01000f2a: 0fd2 .. LSRS r2,r2,#31 + 0x01000f2c: 2a00 .* CMP r2,#0 + 0x01000f2e: d0f9 .. BEQ 0x1000f24 ; UART_SendData + 36 + 0x01000f30: e013 .. B 0x1000f5a ; UART_SendData + 90 + 0x01000f32: 466a jF MOV r2,sp + 0x01000f34: 4b0a .K LDR r3,[pc,#40] ; [0x1000f60] = 0xf8c00 + 0x01000f36: 601a .` STR r2,[r3,#0] + 0x01000f38: 461a .F MOV r2,r3 + 0x01000f3a: 6892 .h LDR r2,[r2,#8] + 0x01000f3c: b292 .. UXTH r2,r2 + 0x01000f3e: 2301 .# MOVS r3,#1 + 0x01000f40: 041b .. LSLS r3,r3,#16 + 0x01000f42: 18d2 .. ADDS r2,r2,r3 + 0x01000f44: 4b06 .K LDR r3,[pc,#24] ; [0x1000f60] = 0xf8c00 + 0x01000f46: 609a .` STR r2,[r3,#8] + 0x01000f48: 2280 ." MOVS r2,#0x80 + 0x01000f4a: 73da .s STRB r2,[r3,#0xf] + 0x01000f4c: bf00 .. NOP + 0x01000f4e: 4a04 .J LDR r2,[pc,#16] ; [0x1000f60] = 0xf8c00 + 0x01000f50: 6912 .i LDR r2,[r2,#0x10] + 0x01000f52: 07d2 .. LSLS r2,r2,#31 + 0x01000f54: 0fd2 .. LSRS r2,r2,#31 + 0x01000f56: 2a00 .* CMP r2,#0 + 0x01000f58: d0f9 .. BEQ 0x1000f4e ; UART_SendData + 78 + 0x01000f5a: bd08 .. POP {r3,pc} + $d + 0x01000f5c: 000f8b00 .... DCD 1018624 + 0x01000f60: 000f8c00 .... DCD 1018880 + $t + i.UART_SetRxITNum + UART_SetRxITNum + 0x01000f64: b570 p. PUSH {r4-r6,lr} + 0x01000f66: 4604 .F MOV r4,r0 + 0x01000f68: 460d .F MOV r5,r1 + 0x01000f6a: 2c00 ., CMP r4,#0 + 0x01000f6c: d007 .. BEQ 0x1000f7e ; UART_SetRxITNum + 26 + 0x01000f6e: 2c01 ., CMP r4,#1 + 0x01000f70: d005 .. BEQ 0x1000f7e ; UART_SetRxITNum + 26 + 0x01000f72: 4a0f .J LDR r2,[pc,#60] ; [0x1000fb0] = 0x1007cd7 + 0x01000f74: 21ff .! MOVS r1,#0xff + 0x01000f76: 318f .1 ADDS r1,r1,#0x8f + 0x01000f78: a00e .. ADR r0,{pc}+0x3c ; 0x1000fb4 + 0x01000f7a: f000f867 ..g. BL _assert_handler ; 0x100104c + 0x01000f7e: 2c00 ., CMP r4,#0 + 0x01000f80: d10a .. BNE 0x1000f98 ; UART_SetRxITNum + 52 + 0x01000f82: 4812 .H LDR r0,[pc,#72] ; [0x1000fcc] = 0xf8b00 + 0x01000f84: 69c0 .i LDR r0,[r0,#0x1c] + 0x01000f86: 21ff .! MOVS r1,#0xff + 0x01000f88: 0209 .. LSLS r1,r1,#8 + 0x01000f8a: 4388 .C BICS r0,r0,r1 + 0x01000f8c: 0629 ). LSLS r1,r5,#24 + 0x01000f8e: 0c09 .. LSRS r1,r1,#16 + 0x01000f90: 4308 .C ORRS r0,r0,r1 + 0x01000f92: 490e .I LDR r1,[pc,#56] ; [0x1000fcc] = 0xf8b00 + 0x01000f94: 61c8 .a STR r0,[r1,#0x1c] + 0x01000f96: e009 .. B 0x1000fac ; UART_SetRxITNum + 72 + 0x01000f98: 480d .H LDR r0,[pc,#52] ; [0x1000fd0] = 0xf8c00 + 0x01000f9a: 69c0 .i LDR r0,[r0,#0x1c] + 0x01000f9c: 21ff .! MOVS r1,#0xff + 0x01000f9e: 0209 .. LSLS r1,r1,#8 + 0x01000fa0: 4388 .C BICS r0,r0,r1 + 0x01000fa2: 0629 ). LSLS r1,r5,#24 + 0x01000fa4: 0c09 .. LSRS r1,r1,#16 + 0x01000fa6: 4308 .C ORRS r0,r0,r1 + 0x01000fa8: 4909 .I LDR r1,[pc,#36] ; [0x1000fd0] = 0xf8c00 + 0x01000faa: 61c8 .a STR r0,[r1,#0x1c] + 0x01000fac: bd70 p. POP {r4-r6,pc} + $d + 0x01000fae: 0000 .. DCW 0 + 0x01000fb0: 01007cd7 .|.. DCD 16809175 + 0x01000fb4: 7262694c Libr DCD 1919052108 + 0x01000fb8: 65697261 arie DCD 1701409377 + 0x01000fbc: 64735c73 s\sd DCD 1685281907 + 0x01000fc0: 63795c6b k\yc DCD 1668897899 + 0x01000fc4: 7261755f _uar DCD 1918989663 + 0x01000fc8: 00632e74 t.c. DCD 6499956 + 0x01000fcc: 000f8b00 .... DCD 1018624 + 0x01000fd0: 000f8c00 .... DCD 1018880 + $t + i.__ARM_common_switch8 + __ARM_common_switch8 + 0x01000fd4: b430 0. PUSH {r4,r5} + 0x01000fd6: 4674 tF MOV r4,lr + 0x01000fd8: 1e64 d. SUBS r4,r4,#1 + 0x01000fda: 7825 %x LDRB r5,[r4,#0] + 0x01000fdc: 1c64 d. ADDS r4,r4,#1 + 0x01000fde: 42ab .B CMP r3,r5 + 0x01000fe0: d304 .. BCC 0x1000fec ; __ARM_common_switch8 + 24 + 0x01000fe2: 5d63 c] LDRB r3,[r4,r5] + 0x01000fe4: 005b [. LSLS r3,r3,#1 + 0x01000fe6: 18e3 .. ADDS r3,r4,r3 + 0x01000fe8: bc30 0. POP {r4,r5} + 0x01000fea: 4718 .G BX r3 + 0x01000fec: 461d .F MOV r5,r3 + 0x01000fee: e7f8 .. B 0x1000fe2 ; __ARM_common_switch8 + 14 + i.__rt_ffs + __rt_ffs + 0x01000ff0: 4601 .F MOV r1,r0 + 0x01000ff2: 2900 .) CMP r1,#0 + 0x01000ff4: d100 .. BNE 0x1000ff8 ; __rt_ffs + 8 + 0x01000ff6: 4770 pG BX lr + 0x01000ff8: b2c8 .. UXTB r0,r1 + 0x01000ffa: 2800 .( CMP r0,#0 + 0x01000ffc: d004 .. BEQ 0x1001008 ; __rt_ffs + 24 + 0x01000ffe: b2c8 .. UXTB r0,r1 + 0x01001000: 4a11 .J LDR r2,[pc,#68] ; [0x1001048] = 0x10076b3 + 0x01001002: 5c10 .\ LDRB r0,[r2,r0] + 0x01001004: 1c40 @. ADDS r0,r0,#1 + 0x01001006: e7f6 .. B 0x1000ff6 ; __rt_ffs + 6 + 0x01001008: 20ff . MOVS r0,#0xff + 0x0100100a: 0200 .. LSLS r0,r0,#8 + 0x0100100c: 4008 .@ ANDS r0,r0,r1 + 0x0100100e: 2800 .( CMP r0,#0 + 0x01001010: d007 .. BEQ 0x1001022 ; __rt_ffs + 50 + 0x01001012: 20ff . MOVS r0,#0xff + 0x01001014: 0200 .. LSLS r0,r0,#8 + 0x01001016: 4008 .@ ANDS r0,r0,r1 + 0x01001018: 1200 .. ASRS r0,r0,#8 + 0x0100101a: 4a0b .J LDR r2,[pc,#44] ; [0x1001048] = 0x10076b3 + 0x0100101c: 5c10 .\ LDRB r0,[r2,r0] + 0x0100101e: 3009 .0 ADDS r0,r0,#9 + 0x01001020: e7e9 .. B 0x1000ff6 ; __rt_ffs + 6 + 0x01001022: 20ff . MOVS r0,#0xff + 0x01001024: 0400 .. LSLS r0,r0,#16 + 0x01001026: 4008 .@ ANDS r0,r0,r1 + 0x01001028: 2800 .( CMP r0,#0 + 0x0100102a: d007 .. BEQ 0x100103c ; __rt_ffs + 76 + 0x0100102c: 20ff . MOVS r0,#0xff + 0x0100102e: 0400 .. LSLS r0,r0,#16 + 0x01001030: 4008 .@ ANDS r0,r0,r1 + 0x01001032: 1400 .. ASRS r0,r0,#16 + 0x01001034: 4a04 .J LDR r2,[pc,#16] ; [0x1001048] = 0x10076b3 + 0x01001036: 5c10 .\ LDRB r0,[r2,r0] + 0x01001038: 3011 .0 ADDS r0,r0,#0x11 + 0x0100103a: e7dc .. B 0x1000ff6 ; __rt_ffs + 6 + 0x0100103c: 0e08 .. LSRS r0,r1,#24 + 0x0100103e: 4a02 .J LDR r2,[pc,#8] ; [0x1001048] = 0x10076b3 + 0x01001040: 5c10 .\ LDRB r0,[r2,r0] + 0x01001042: 3019 .0 ADDS r0,r0,#0x19 + 0x01001044: e7d7 .. B 0x1000ff6 ; __rt_ffs + 6 + $d + 0x01001046: 0000 .. DCW 0 + 0x01001048: 010076b3 .v.. DCD 16807603 + $t + i._assert_handler + _assert_handler + 0x0100104c: bf00 .. NOP + 0x0100104e: e7fe .. B 0x100104e ; _assert_handler + 2 + i._ipc_list_resume + _ipc_list_resume + 0x01001050: b570 p. PUSH {r4-r6,lr} + 0x01001052: 4604 .F MOV r4,r0 + 0x01001054: 6820 h LDR r0,[r4,#0] + 0x01001056: 4605 .F MOV r5,r0 + 0x01001058: 3d14 .= SUBS r5,r5,#0x14 + 0x0100105a: bf00 .. NOP + 0x0100105c: bf00 .. NOP + 0x0100105e: 4628 (F MOV r0,r5 + 0x01001060: f004ff4e ..N. BL rt_thread_resume ; 0x1005f00 + 0x01001064: 2000 . MOVS r0,#0 + 0x01001066: bd70 p. POP {r4-r6,pc} + i._ipc_list_suspend + _ipc_list_suspend + 0x01001068: b5f7 .. PUSH {r0-r2,r4-r7,lr} + 0x0100106a: 4605 .F MOV r5,r0 + 0x0100106c: 460c .F MOV r4,r1 + 0x0100106e: 4620 F MOV r0,r4 + 0x01001070: f005f842 ..B. BL rt_thread_suspend ; 0x10060f8 + 0x01001074: 9802 .. LDR r0,[sp,#8] + 0x01001076: 2800 .( CMP r0,#0 + 0x01001078: d002 .. BEQ 0x1001080 ; _ipc_list_suspend + 24 + 0x0100107a: 2801 .( CMP r0,#1 + 0x0100107c: d122 ". BNE 0x10010c4 ; _ipc_list_suspend + 92 + 0x0100107e: e005 .. B 0x100108c ; _ipc_list_suspend + 36 + 0x01001080: 4621 !F MOV r1,r4 + 0x01001082: 3114 .1 ADDS r1,r1,#0x14 + 0x01001084: 4628 (F MOV r0,r5 + 0x01001086: f003fa5f .._. BL rt_list_insert_before ; 0x1004548 + 0x0100108a: e021 !. B 0x10010d0 ; _ipc_list_suspend + 104 + 0x0100108c: 682e .h LDR r6,[r5,#0] + 0x0100108e: e00e .. B 0x10010ae ; _ipc_list_suspend + 70 + 0x01001090: 4637 7F MOV r7,r6 + 0x01001092: 3f14 .? SUBS r7,r7,#0x14 + 0x01001094: 2035 5 MOVS r0,#0x35 + 0x01001096: 5d01 .] LDRB r1,[r0,r4] + 0x01001098: 5dc0 .] LDRB r0,[r0,r7] + 0x0100109a: 4281 .B CMP r1,r0 + 0x0100109c: da06 .. BGE 0x10010ac ; _ipc_list_suspend + 68 + 0x0100109e: 4621 !F MOV r1,r4 + 0x010010a0: 3114 .1 ADDS r1,r1,#0x14 + 0x010010a2: 4638 8F MOV r0,r7 + 0x010010a4: 3014 .0 ADDS r0,r0,#0x14 + 0x010010a6: f003fa4f ..O. BL rt_list_insert_before ; 0x1004548 + 0x010010aa: e002 .. B 0x10010b2 ; _ipc_list_suspend + 74 + 0x010010ac: 6836 6h LDR r6,[r6,#0] + 0x010010ae: 42ae .B CMP r6,r5 + 0x010010b0: d1ee .. BNE 0x1001090 ; _ipc_list_suspend + 40 + 0x010010b2: bf00 .. NOP + 0x010010b4: 42ae .B CMP r6,r5 + 0x010010b6: d104 .. BNE 0x10010c2 ; _ipc_list_suspend + 90 + 0x010010b8: 4621 !F MOV r1,r4 + 0x010010ba: 3114 .1 ADDS r1,r1,#0x14 + 0x010010bc: 4628 (F MOV r0,r5 + 0x010010be: f003fa43 ..C. BL rt_list_insert_before ; 0x1004548 + 0x010010c2: e005 .. B 0x10010d0 ; _ipc_list_suspend + 104 + 0x010010c4: 2297 ." MOVS r2,#0x97 + 0x010010c6: 4904 .I LDR r1,[pc,#16] ; [0x10010d8] = 0x10077d5 + 0x010010c8: a004 .. ADR r0,{pc}+0x14 ; 0x10010dc + 0x010010ca: f002fa99 .... BL rt_assert_handler ; 0x1003600 + 0x010010ce: bf00 .. NOP + 0x010010d0: bf00 .. NOP + 0x010010d2: 2000 . MOVS r0,#0 + 0x010010d4: bdfe .. POP {r1-r7,pc} + $d + 0x010010d6: 0000 .. DCW 0 + 0x010010d8: 010077d5 .w.. DCD 16807893 + 0x010010dc: 00000030 0... DCD 48 + $t + i._ipc_object_init + _ipc_object_init + 0x010010e0: b510 .. PUSH {r4,lr} + 0x010010e2: 4604 .F MOV r4,r0 + 0x010010e4: 4620 F MOV r0,r4 + 0x010010e6: 3014 .0 ADDS r0,r0,#0x14 + 0x010010e8: f003fa1a .... BL rt_list_init ; 0x1004520 + 0x010010ec: 2000 . MOVS r0,#0 + 0x010010ee: bd10 .. POP {r4,pc} + i._memheap_dump_tag + _memheap_dump_tag + 0x010010f0: b57c |. PUSH {r2-r6,lr} + 0x010010f2: 4604 .F MOV r4,r0 + 0x010010f4: 4625 %F MOV r5,r4 + 0x010010f6: 3510 .5 ADDS r5,r5,#0x10 + 0x010010f8: 2204 ." MOVS r2,#4 + 0x010010fa: 4629 )F MOV r1,r5 + 0x010010fc: 4668 hF MOV r0,sp + 0x010010fe: f003fbd1 .... BL rt_memcpy ; 0x10048a4 + 0x01001102: 4625 %F MOV r5,r4 + 0x01001104: 3514 .5 ADDS r5,r5,#0x14 + 0x01001106: 2204 ." MOVS r2,#4 + 0x01001108: 4629 )F MOV r1,r5 + 0x0100110a: a801 .. ADD r0,sp,#4 + 0x0100110c: f003fbca .... BL rt_memcpy ; 0x10048a4 + 0x01001110: 466a jF MOV r2,sp + 0x01001112: 2108 .! MOVS r1,#8 + 0x01001114: a001 .. ADR r0,{pc}+8 ; 0x100111c + 0x01001116: f003f9db .... BL rt_kprintf ; 0x10044d0 + 0x0100111a: bd7c |. POP {r2-r6,pc} + $d + 0x0100111c: 732a2e25 %.*s DCD 1932144165 + 0x01001120: 00000000 .... DCD 0 + $t + i._msh_exec_cmd + _msh_exec_cmd + 0x01001124: b5f7 .. PUSH {r0-r2,r4-r7,lr} + 0x01001126: b08c .. SUB sp,sp,#0x30 + 0x01001128: 4605 .F MOV r5,r0 + 0x0100112a: 4617 .F MOV r7,r2 + 0x0100112c: 2400 .$ MOVS r4,#0 + 0x0100112e: 2d00 .- CMP r5,#0 + 0x01001130: d105 .. BNE 0x100113e ; _msh_exec_cmd + 26 + 0x01001132: 22ff ." MOVS r2,#0xff + 0x01001134: 321d .2 ADDS r2,r2,#0x1d + 0x01001136: 491d .I LDR r1,[pc,#116] ; [0x10011ac] = 0x100750f + 0x01001138: a01d .. ADR r0,{pc}+0x78 ; 0x10011b0 + 0x0100113a: f002fa61 ..a. BL rt_assert_handler ; 0x1003600 + 0x0100113e: 2f00 ./ CMP r7,#0 + 0x01001140: d105 .. BNE 0x100114e ; _msh_exec_cmd + 42 + 0x01001142: 22ff ." MOVS r2,#0xff + 0x01001144: 321e .2 ADDS r2,r2,#0x1e + 0x01001146: 4919 .I LDR r1,[pc,#100] ; [0x10011ac] = 0x100750f + 0x01001148: a01a .. ADR r0,{pc}+0x6c ; 0x10011b4 + 0x0100114a: f002fa59 ..Y. BL rt_assert_handler ; 0x1003600 + 0x0100114e: e000 .. B 0x1001152 ; _msh_exec_cmd + 46 + 0x01001150: 1c64 d. ADDS r4,r4,#1 + 0x01001152: 5d28 (] LDRB r0,[r5,r4] + 0x01001154: 2820 ( CMP r0,#0x20 + 0x01001156: d005 .. BEQ 0x1001164 ; _msh_exec_cmd + 64 + 0x01001158: 5d28 (] LDRB r0,[r5,r4] + 0x0100115a: 2809 .( CMP r0,#9 + 0x0100115c: d002 .. BEQ 0x1001164 ; _msh_exec_cmd + 64 + 0x0100115e: 980d .. LDR r0,[sp,#0x34] + 0x01001160: 4284 .B CMP r4,r0 + 0x01001162: d3f5 .. BCC 0x1001150 ; _msh_exec_cmd + 44 + 0x01001164: 2c00 ., CMP r4,#0 + 0x01001166: d102 .. BNE 0x100116e ; _msh_exec_cmd + 74 + 0x01001168: 1e60 `. SUBS r0,r4,#1 + 0x0100116a: b00f .. ADD sp,sp,#0x3c + 0x0100116c: bdf0 .. POP {r4-r7,pc} + 0x0100116e: 4621 !F MOV r1,r4 + 0x01001170: 4628 (F MOV r0,r5 + 0x01001172: f001ffed .... BL msh_get_cmd ; 0x1003150 + 0x01001176: 4606 .F MOV r6,r0 + 0x01001178: 2e00 .. CMP r6,#0 + 0x0100117a: d101 .. BNE 0x1001180 ; _msh_exec_cmd + 92 + 0x0100117c: 1e40 @. SUBS r0,r0,#1 + 0x0100117e: e7f4 .. B 0x100116a ; _msh_exec_cmd + 70 + 0x01001180: 2128 (! MOVS r1,#0x28 + 0x01001182: a801 .. ADD r0,sp,#4 + 0x01001184: f7fffb39 ..9. BL __aeabi_memclr4 ; 0x10007fa + 0x01001188: aa01 .. ADD r2,sp,#4 + 0x0100118a: 4628 (F MOV r0,r5 + 0x0100118c: 990d .. LDR r1,[sp,#0x34] + 0x0100118e: f002f831 ..1. BL msh_split ; 0x10031f4 + 0x01001192: 900b .. STR r0,[sp,#0x2c] + 0x01001194: 980b .. LDR r0,[sp,#0x2c] + 0x01001196: 2800 .( CMP r0,#0 + 0x01001198: d101 .. BNE 0x100119e ; _msh_exec_cmd + 122 + 0x0100119a: 1e40 @. SUBS r0,r0,#1 + 0x0100119c: e7e5 .. B 0x100116a ; _msh_exec_cmd + 70 + 0x0100119e: a901 .. ADD r1,sp,#4 + 0x010011a0: 980b .. LDR r0,[sp,#0x2c] + 0x010011a2: 47b0 .G BLX r6 + 0x010011a4: 6038 8` STR r0,[r7,#0] + 0x010011a6: 2000 . MOVS r0,#0 + 0x010011a8: e7df .. B 0x100116a ; _msh_exec_cmd + 70 + $d + 0x010011aa: 0000 .. DCW 0 + 0x010011ac: 0100750f .u.. DCD 16807183 + 0x010011b0: 00646d63 cmd. DCD 6581603 + 0x010011b4: 70746572 retp DCD 1886676338 + 0x010011b8: 00000000 .... DCD 0 + $t + i._pin_control + _pin_control + 0x010011bc: b5f8 .. PUSH {r3-r7,lr} + 0x010011be: 4605 .F MOV r5,r0 + 0x010011c0: 4616 .F MOV r6,r2 + 0x010011c2: 462f /F MOV r7,r5 + 0x010011c4: 2f00 ./ CMP r7,#0 + 0x010011c6: d104 .. BNE 0x10011d2 ; _pin_control + 22 + 0x010011c8: 2238 8" MOVS r2,#0x38 + 0x010011ca: 4908 .I LDR r1,[pc,#32] ; [0x10011ec] = 0x1007291 + 0x010011cc: a008 .. ADR r0,{pc}+0x24 ; 0x10011f0 + 0x010011ce: f002fa17 .... BL rt_assert_handler ; 0x1003600 + 0x010011d2: 4634 4F MOV r4,r6 + 0x010011d4: 2c00 ., CMP r4,#0 + 0x010011d6: d101 .. BNE 0x10011dc ; _pin_control + 32 + 0x010011d8: 1e60 `. SUBS r0,r4,#1 + 0x010011da: bdf8 .. POP {r3-r7,pc} + 0x010011dc: 8862 b. LDRH r2,[r4,#2] + 0x010011de: 8821 !. LDRH r1,[r4,#0] + 0x010011e0: 6c38 8l LDR r0,[r7,#0x40] + 0x010011e2: 6803 .h LDR r3,[r0,#0] + 0x010011e4: 4628 (F MOV r0,r5 + 0x010011e6: 4798 .G BLX r3 + 0x010011e8: 2000 . MOVS r0,#0 + 0x010011ea: e7f6 .. B 0x10011da ; _pin_control + 30 + $d + 0x010011ec: 01007291 .r.. DCD 16806545 + 0x010011f0: 206e6970 pin DCD 544106864 + 0x010011f4: 52203d21 != R DCD 1377844513 + 0x010011f8: 554e5f54 T_NU DCD 1431199572 + 0x010011fc: 00004c4c LL.. DCD 19532 + $t + i._pin_read + _pin_read + 0x01001200: b5f8 .. PUSH {r3-r7,lr} + 0x01001202: 4605 .F MOV r5,r0 + 0x01001204: 4616 .F MOV r6,r2 + 0x01001206: 461f .F MOV r7,r3 + 0x01001208: 9500 .. STR r5,[sp,#0] + 0x0100120a: 9d00 .. LDR r5,[sp,#0] + 0x0100120c: 2d00 .- CMP r5,#0 + 0x0100120e: d104 .. BNE 0x100121a ; _pin_read + 26 + 0x01001210: 2219 ." MOVS r2,#0x19 + 0x01001212: 490a .I LDR r1,[pc,#40] ; [0x100123c] = 0x100727c + 0x01001214: a00a .. ADR r0,{pc}+0x2c ; 0x1001240 + 0x01001216: f002f9f3 .... BL rt_assert_handler ; 0x1003600 + 0x0100121a: 4634 4F MOV r4,r6 + 0x0100121c: 2c00 ., CMP r4,#0 + 0x0100121e: d001 .. BEQ 0x1001224 ; _pin_read + 36 + 0x01001220: 2f04 ./ CMP r7,#4 + 0x01001222: d001 .. BEQ 0x1001228 ; _pin_read + 40 + 0x01001224: 2000 . MOVS r0,#0 + 0x01001226: bdf8 .. POP {r3-r7,pc} + 0x01001228: 8821 !. LDRH r1,[r4,#0] + 0x0100122a: 9800 .. LDR r0,[sp,#0] + 0x0100122c: 6c00 .l LDR r0,[r0,#0x40] + 0x0100122e: 6882 .h LDR r2,[r0,#8] + 0x01001230: 4628 (F MOV r0,r5 + 0x01001232: 4790 .G BLX r2 + 0x01001234: 8060 `. STRH r0,[r4,#2] + 0x01001236: 4638 8F MOV r0,r7 + 0x01001238: e7f5 .. B 0x1001226 ; _pin_read + 38 + $d + 0x0100123a: 0000 .. DCW 0 + 0x0100123c: 0100727c |r.. DCD 16806524 + 0x01001240: 206e6970 pin DCD 544106864 + 0x01001244: 52203d21 != R DCD 1377844513 + 0x01001248: 554e5f54 T_NU DCD 1431199572 + 0x0100124c: 00004c4c LL.. DCD 19532 + $t + i._pin_write + _pin_write + 0x01001250: b5f8 .. PUSH {r3-r7,lr} + 0x01001252: 4605 .F MOV r5,r0 + 0x01001254: 4616 .F MOV r6,r2 + 0x01001256: 461f .F MOV r7,r3 + 0x01001258: 9500 .. STR r5,[sp,#0] + 0x0100125a: 9d00 .. LDR r5,[sp,#0] + 0x0100125c: 2d00 .- CMP r5,#0 + 0x0100125e: d104 .. BNE 0x100126a ; _pin_write + 26 + 0x01001260: 2228 (" MOVS r2,#0x28 + 0x01001262: 490a .I LDR r1,[pc,#40] ; [0x100128c] = 0x1007286 + 0x01001264: a00a .. ADR r0,{pc}+0x2c ; 0x1001290 + 0x01001266: f002f9cb .... BL rt_assert_handler ; 0x1003600 + 0x0100126a: 4634 4F MOV r4,r6 + 0x0100126c: 2c00 ., CMP r4,#0 + 0x0100126e: d001 .. BEQ 0x1001274 ; _pin_write + 36 + 0x01001270: 2f04 ./ CMP r7,#4 + 0x01001272: d001 .. BEQ 0x1001278 ; _pin_write + 40 + 0x01001274: 2000 . MOVS r0,#0 + 0x01001276: bdf8 .. POP {r3-r7,pc} + 0x01001278: 8862 b. LDRH r2,[r4,#2] + 0x0100127a: 8821 !. LDRH r1,[r4,#0] + 0x0100127c: 9800 .. LDR r0,[sp,#0] + 0x0100127e: 6c00 .l LDR r0,[r0,#0x40] + 0x01001280: 6843 Ch LDR r3,[r0,#4] + 0x01001282: 4628 (F MOV r0,r5 + 0x01001284: 4798 .G BLX r3 + 0x01001286: 4638 8F MOV r0,r7 + 0x01001288: e7f5 .. B 0x1001276 ; _pin_write + 38 + $d + 0x0100128a: 0000 .. DCW 0 + 0x0100128c: 01007286 .r.. DCD 16806534 + 0x01001290: 206e6970 pin DCD 544106864 + 0x01001294: 52203d21 != R DCD 1377844513 + 0x01001298: 554e5f54 T_NU DCD 1431199572 + 0x0100129c: 00004c4c LL.. DCD 19532 + $t + i._rt_scheduler_stack_check + _rt_scheduler_stack_check + 0x010012a0: b570 p. PUSH {r4-r6,lr} + 0x010012a2: 4604 .F MOV r4,r0 + 0x010012a4: 2c00 ., CMP r4,#0 + 0x010012a6: d104 .. BNE 0x10012b2 ; _rt_scheduler_stack_check + 18 + 0x010012a8: 2254 T" MOVS r2,#0x54 + 0x010012aa: 4913 .I LDR r1,[pc,#76] ; [0x10012f8] = 0x1007598 + 0x010012ac: a013 .. ADR r0,{pc}+0x50 ; 0x10012fc + 0x010012ae: f002f9a7 .... BL rt_assert_handler ; 0x1003600 + 0x010012b2: 6aa0 .j LDR r0,[r4,#0x28] + 0x010012b4: 7800 .x LDRB r0,[r0,#0] + 0x010012b6: 2823 #( CMP r0,#0x23 + 0x010012b8: d109 .. BNE 0x10012ce ; _rt_scheduler_stack_check + 46 + 0x010012ba: 6aa1 .j LDR r1,[r4,#0x28] + 0x010012bc: 69e0 .i LDR r0,[r4,#0x1c] + 0x010012be: 4288 .B CMP r0,r1 + 0x010012c0: d905 .. BLS 0x10012ce ; _rt_scheduler_stack_check + 46 + 0x010012c2: 6ae1 .j LDR r1,[r4,#0x2c] + 0x010012c4: 6aa0 .j LDR r0,[r4,#0x28] + 0x010012c6: 1840 @. ADDS r0,r0,r1 + 0x010012c8: 69e1 .i LDR r1,[r4,#0x1c] + 0x010012ca: 4288 .B CMP r0,r1 + 0x010012cc: d20a .. BCS 0x10012e4 ; _rt_scheduler_stack_check + 68 + 0x010012ce: 4621 !F MOV r1,r4 + 0x010012d0: a00f .. ADR r0,{pc}+0x40 ; 0x1001310 + 0x010012d2: f003f8fd .... BL rt_kprintf ; 0x10044d0 + 0x010012d6: f7fff8f3 .... BL rt_hw_interrupt_disable ; 0x10004c0 + 0x010012da: 4605 .F MOV r5,r0 + 0x010012dc: bf00 .. NOP + 0x010012de: 2d00 .- CMP r5,#0 + 0x010012e0: d1fd .. BNE 0x10012de ; _rt_scheduler_stack_check + 62 + 0x010012e2: e008 .. B 0x10012f6 ; _rt_scheduler_stack_check + 86 + 0x010012e4: 6aa0 .j LDR r0,[r4,#0x28] + 0x010012e6: 3020 0 ADDS r0,r0,#0x20 + 0x010012e8: 69e1 .i LDR r1,[r4,#0x1c] + 0x010012ea: 4281 .B CMP r1,r0 + 0x010012ec: d803 .. BHI 0x10012f6 ; _rt_scheduler_stack_check + 86 + 0x010012ee: 4621 !F MOV r1,r4 + 0x010012f0: a00e .. ADR r0,{pc}+0x3c ; 0x100132c + 0x010012f2: f003f8ed .... BL rt_kprintf ; 0x10044d0 + 0x010012f6: bd70 p. POP {r4-r6,pc} + $d + 0x010012f8: 01007598 .u.. DCD 16807320 + 0x010012fc: 65726874 thre DCD 1701996660 + 0x01001300: 21206461 ad ! DCD 555770977 + 0x01001304: 5452203d = RT DCD 1414668349 + 0x01001308: 4c554e5f _NUL DCD 1280659039 + 0x0100130c: 0000004c L... DCD 76 + 0x01001310: 65726874 thre DCD 1701996660 + 0x01001314: 253a6461 ad:% DCD 624583777 + 0x01001318: 74732073 s st DCD 1953702003 + 0x0100131c: 206b6361 ack DCD 543908705 + 0x01001320: 7265766f over DCD 1919252079 + 0x01001324: 776f6c66 flow DCD 2003790950 + 0x01001328: 0000000a .... DCD 10 + 0x0100132c: 6e726177 warn DCD 1852989815 + 0x01001330: 3a676e69 ing: DCD 979857001 + 0x01001334: 20732520 %s DCD 544417056 + 0x01001338: 63617473 stac DCD 1667331187 + 0x0100133c: 7369206b k is DCD 1936269419 + 0x01001340: 6f6c6320 clo DCD 1869374240 + 0x01001344: 74206573 se t DCD 1948280179 + 0x01001348: 6e65206f o en DCD 1852121199 + 0x0100134c: 666f2064 d of DCD 1718558820 + 0x01001350: 61747320 sta DCD 1635021600 + 0x01001354: 61206b63 ck a DCD 1629514595 + 0x01001358: 65726464 ddre DCD 1701995620 + 0x0100135c: 0a2e7373 ss.. DCD 170816371 + 0x01001360: 00000000 .... DCD 0 + $t + i._scheduler_get_highest_priority_thread + _scheduler_get_highest_priority_thread + 0x01001364: b570 p. PUSH {r4-r6,lr} + 0x01001366: 4604 .F MOV r4,r0 + 0x01001368: 4806 .H LDR r0,[pc,#24] ; [0x1001384] = 0x20024 + 0x0100136a: 6800 .h LDR r0,[r0,#0] + 0x0100136c: f7fffe40 ..@. BL __rt_ffs ; 0x1000ff0 + 0x01001370: 1e45 E. SUBS r5,r0,#1 + 0x01001372: 00e8 .. LSLS r0,r5,#3 + 0x01001374: 4904 .I LDR r1,[pc,#16] ; [0x1001388] = 0x20274 + 0x01001376: 5808 .X LDR r0,[r1,r0] + 0x01001378: 4606 .F MOV r6,r0 + 0x0100137a: 3e14 .> SUBS r6,r6,#0x14 + 0x0100137c: 6025 %` STR r5,[r4,#0] + 0x0100137e: 4630 0F MOV r0,r6 + 0x01001380: bd70 p. POP {r4-r6,pc} + $d + 0x01001382: 0000 .. DCW 0 + 0x01001384: 00020024 $... DCD 131108 + 0x01001388: 00020274 t... DCD 131700 + $t + i._serial_check_buffer_size + _serial_check_buffer_size + 0x0100138c: b510 .. PUSH {r4,lr} + 0x0100138e: 4809 .H LDR r0,[pc,#36] ; [0x10013b4] = 0x2000c + 0x01001390: 6800 .h LDR r0,[r0,#0] + 0x01001392: 2800 .( CMP r0,#0 + 0x01001394: d10d .. BNE 0x10013b2 ; _serial_check_buffer_size + 38 + 0x01001396: bf00 .. NOP + 0x01001398: a007 .. ADR r0,{pc}+0x20 ; 0x10013b8 + 0x0100139a: f003f899 .... BL rt_kprintf ; 0x10044d0 + 0x0100139e: 480a .H LDR r0,[pc,#40] ; [0x10013c8] = 0x1007cfc + 0x010013a0: f003f896 .... BL rt_kprintf ; 0x10044d0 + 0x010013a4: a009 .. ADR r0,{pc}+0x28 ; 0x10013cc + 0x010013a6: f003f893 .... BL rt_kprintf ; 0x10044d0 + 0x010013aa: bf00 .. NOP + 0x010013ac: 2001 . MOVS r0,#1 + 0x010013ae: 4901 .I LDR r1,[pc,#4] ; [0x10013b4] = 0x2000c + 0x010013b0: 6008 .` STR r0,[r1,#0] + 0x010013b2: bd10 .. POP {r4,pc} + $d + 0x010013b4: 0002000c .... DCD 131084 + 0x010013b8: 33335b1b .[33 DCD 859003675 + 0x010013bc: 2f575b6d m[W/ DCD 794254189 + 0x010013c0: 54524155 UART DCD 1414676821 + 0x010013c4: 0000205d ] .. DCD 8285 + 0x010013c8: 01007cfc .|.. DCD 16809212 + 0x010013cc: 6d305b1b .[0m DCD 1831885595 + 0x010013d0: 0000000a .... DCD 10 + $t + i._serial_int_rx + _serial_int_rx + 0x010013d4: b5fe .. PUSH {r1-r7,lr} + 0x010013d6: 4606 .F MOV r6,r0 + 0x010013d8: 460f .F MOV r7,r1 + 0x010013da: 4615 .F MOV r5,r2 + 0x010013dc: 2e00 .. CMP r6,#0 + 0x010013de: d105 .. BNE 0x10013ec ; _serial_int_rx + 24 + 0x010013e0: 22ff ." MOVS r2,#0xff + 0x010013e2: 320f .2 ADDS r2,r2,#0xf + 0x010013e4: 491f .I LDR r1,[pc,#124] ; [0x1001464] = 0x1007324 + 0x010013e6: a020 . ADR r0,{pc}+0x82 ; 0x1001468 + 0x010013e8: f002f90a .... BL rt_assert_handler ; 0x1003600 + 0x010013ec: 9502 .. STR r5,[sp,#8] + 0x010013ee: 6cf4 .l LDR r4,[r6,#0x4c] + 0x010013f0: 2c00 ., CMP r4,#0 + 0x010013f2: d105 .. BNE 0x1001400 ; _serial_int_rx + 44 + 0x010013f4: 22ff ." MOVS r2,#0xff + 0x010013f6: 3213 .2 ADDS r2,r2,#0x13 + 0x010013f8: 491a .I LDR r1,[pc,#104] ; [0x1001464] = 0x1007324 + 0x010013fa: a020 . ADR r0,{pc}+0x82 ; 0x100147c + 0x010013fc: f002f900 .... BL rt_assert_handler ; 0x1003600 + 0x01001400: e029 ). B 0x1001456 ; _serial_int_rx + 130 + 0x01001402: f7fff85d ..]. BL rt_hw_interrupt_disable ; 0x10004c0 + 0x01001406: 9000 .. STR r0,[sp,#0] + 0x01001408: 88e0 .. LDRH r0,[r4,#6] + 0x0100140a: 88a1 .. LDRH r1,[r4,#4] + 0x0100140c: 4288 .B CMP r0,r1 + 0x0100140e: d106 .. BNE 0x100141e ; _serial_int_rx + 74 + 0x01001410: 68a0 .h LDR r0,[r4,#8] + 0x01001412: 2800 .( CMP r0,#0 + 0x01001414: d103 .. BNE 0x100141e ; _serial_int_rx + 74 + 0x01001416: 9800 .. LDR r0,[sp,#0] + 0x01001418: f7fff856 ..V. BL rt_hw_interrupt_enable ; 0x10004c8 + 0x0100141c: e01d .. B 0x100145a ; _serial_int_rx + 134 + 0x0100141e: 88e1 .. LDRH r1,[r4,#6] + 0x01001420: 6820 h LDR r0,[r4,#0] + 0x01001422: 5c40 @\ LDRB r0,[r0,r1] + 0x01001424: 9001 .. STR r0,[sp,#4] + 0x01001426: 88e0 .. LDRH r0,[r4,#6] + 0x01001428: 1c40 @. ADDS r0,r0,#1 + 0x0100142a: 80e0 .. STRH r0,[r4,#6] + 0x0100142c: 88e1 .. LDRH r1,[r4,#6] + 0x0100142e: 6cb0 .l LDR r0,[r6,#0x48] + 0x01001430: 0180 .. LSLS r0,r0,#6 + 0x01001432: 0c00 .. LSRS r0,r0,#16 + 0x01001434: 4281 .B CMP r1,r0 + 0x01001436: db01 .. BLT 0x100143c ; _serial_int_rx + 104 + 0x01001438: 2000 . MOVS r0,#0 + 0x0100143a: 80e0 .. STRH r0,[r4,#6] + 0x0100143c: 68a0 .h LDR r0,[r4,#8] + 0x0100143e: 2801 .( CMP r0,#1 + 0x01001440: d101 .. BNE 0x1001446 ; _serial_int_rx + 114 + 0x01001442: 2000 . MOVS r0,#0 + 0x01001444: 60a0 .` STR r0,[r4,#8] + 0x01001446: 9800 .. LDR r0,[sp,#0] + 0x01001448: f7fff83e ..>. BL rt_hw_interrupt_enable ; 0x10004c8 + 0x0100144c: 9801 .. LDR r0,[sp,#4] + 0x0100144e: 7038 8p STRB r0,[r7,#0] + 0x01001450: 1c7f .. ADDS r7,r7,#1 + 0x01001452: 1e6d m. SUBS r5,r5,#1 + 0x01001454: bf00 .. NOP + 0x01001456: 2d00 .- CMP r5,#0 + 0x01001458: d1d3 .. BNE 0x1001402 ; _serial_int_rx + 46 + 0x0100145a: bf00 .. NOP + 0x0100145c: 9802 .. LDR r0,[sp,#8] + 0x0100145e: 1b40 @. SUBS r0,r0,r5 + 0x01001460: bdfe .. POP {r1-r7,pc} + $d + 0x01001462: 0000 .. DCW 0 + 0x01001464: 01007324 $s.. DCD 16806692 + 0x01001468: 69726573 seri DCD 1769104755 + 0x0100146c: 21206c61 al ! DCD 555773025 + 0x01001470: 5452203d = RT DCD 1414668349 + 0x01001474: 4c554e5f _NUL DCD 1280659039 + 0x01001478: 0000004c L... DCD 76 + 0x0100147c: 665f7872 rx_f DCD 1717532786 + 0x01001480: 206f6669 ifo DCD 544171625 + 0x01001484: 52203d21 != R DCD 1377844513 + 0x01001488: 554e5f54 T_NU DCD 1431199572 + 0x0100148c: 00004c4c LL.. DCD 19532 + $t + i._serial_int_tx + _serial_int_tx + 0x01001490: b5f8 .. PUSH {r3-r7,lr} + 0x01001492: 4604 .F MOV r4,r0 + 0x01001494: 460e .F MOV r6,r1 + 0x01001496: 4615 .F MOV r5,r2 + 0x01001498: 2c00 ., CMP r4,#0 + 0x0100149a: d105 .. BNE 0x10014a8 ; _serial_int_tx + 24 + 0x0100149c: 22ff ." MOVS r2,#0xff + 0x0100149e: 323f ?2 ADDS r2,r2,#0x3f + 0x010014a0: 491c .I LDR r1,[pc,#112] ; [0x1001514] = 0x1007333 + 0x010014a2: 481d .H LDR r0,[pc,#116] ; [0x1001518] = 0x1001580 + 0x010014a4: f002f8ac .... BL rt_assert_handler ; 0x1003600 + 0x010014a8: 9500 .. STR r5,[sp,#0] + 0x010014aa: 6d27 'm LDR r7,[r4,#0x50] + 0x010014ac: 2f00 ./ CMP r7,#0 + 0x010014ae: d105 .. BNE 0x10014bc ; _serial_int_tx + 44 + 0x010014b0: 22ff ." MOVS r2,#0xff + 0x010014b2: 3243 C2 ADDS r2,r2,#0x43 + 0x010014b4: 4917 .I LDR r1,[pc,#92] ; [0x1001514] = 0x1007333 + 0x010014b6: a019 .. ADR r0,{pc}+0x66 ; 0x100151c + 0x010014b8: f002f8a2 .... BL rt_assert_handler ; 0x1003600 + 0x010014bc: e024 $. B 0x1001508 ; _serial_int_tx + 120 + 0x010014be: 7830 0x LDRB r0,[r6,#0] + 0x010014c0: 280a .( CMP r0,#0xa + 0x010014c2: d111 .. BNE 0x10014e8 ; _serial_int_tx + 88 + 0x010014c4: 8b20 . LDRH r0,[r4,#0x18] + 0x010014c6: 2140 @! MOVS r1,#0x40 + 0x010014c8: 4008 .@ ANDS r0,r0,r1 + 0x010014ca: 2800 .( CMP r0,#0 + 0x010014cc: d00c .. BEQ 0x10014e8 ; _serial_int_tx + 88 + 0x010014ce: 6c20 l LDR r0,[r4,#0x40] + 0x010014d0: 210d .! MOVS r1,#0xd + 0x010014d2: 6882 .h LDR r2,[r0,#8] + 0x010014d4: 4620 F MOV r0,r4 + 0x010014d6: 4790 .G BLX r2 + 0x010014d8: 1c40 @. ADDS r0,r0,#1 + 0x010014da: 2800 .( CMP r0,#0 + 0x010014dc: d104 .. BNE 0x10014e8 ; _serial_int_tx + 88 + 0x010014de: 1e41 A. SUBS r1,r0,#1 + 0x010014e0: 4638 8F MOV r0,r7 + 0x010014e2: f002f937 ..7. BL rt_completion_wait ; 0x1003754 + 0x010014e6: e00f .. B 0x1001508 ; _serial_int_tx + 120 + 0x010014e8: 7831 1x LDRB r1,[r6,#0] + 0x010014ea: 6c20 l LDR r0,[r4,#0x40] + 0x010014ec: 6882 .h LDR r2,[r0,#8] + 0x010014ee: 4620 F MOV r0,r4 + 0x010014f0: 4790 .G BLX r2 + 0x010014f2: 1c40 @. ADDS r0,r0,#1 + 0x010014f4: 2800 .( CMP r0,#0 + 0x010014f6: d104 .. BNE 0x1001502 ; _serial_int_tx + 114 + 0x010014f8: 1e41 A. SUBS r1,r0,#1 + 0x010014fa: 4638 8F MOV r0,r7 + 0x010014fc: f002f92a ..*. BL rt_completion_wait ; 0x1003754 + 0x01001500: e002 .. B 0x1001508 ; _serial_int_tx + 120 + 0x01001502: 1c76 v. ADDS r6,r6,#1 + 0x01001504: 1e6d m. SUBS r5,r5,#1 + 0x01001506: bf00 .. NOP + 0x01001508: 2d00 .- CMP r5,#0 + 0x0100150a: d1d8 .. BNE 0x10014be ; _serial_int_tx + 46 + 0x0100150c: 9800 .. LDR r0,[sp,#0] + 0x0100150e: 1b40 @. SUBS r0,r0,r5 + 0x01001510: bdf8 .. POP {r3-r7,pc} + $d + 0x01001512: 0000 .. DCW 0 + 0x01001514: 01007333 3s.. DCD 16806707 + 0x01001518: 01001580 .... DCD 16782720 + 0x0100151c: 21207874 tx ! DCD 555776116 + 0x01001520: 5452203d = RT DCD 1414668349 + 0x01001524: 4c554e5f _NUL DCD 1280659039 + 0x01001528: 0000004c L... DCD 76 + $t + i._serial_poll_rx + _serial_poll_rx + 0x0100152c: b5f8 .. PUSH {r3-r7,lr} + 0x0100152e: 4606 .F MOV r6,r0 + 0x01001530: 460f .F MOV r7,r1 + 0x01001532: 4614 .F MOV r4,r2 + 0x01001534: 2e00 .. CMP r6,#0 + 0x01001536: d104 .. BNE 0x1001542 ; _serial_poll_rx + 22 + 0x01001538: 22d8 ." MOVS r2,#0xd8 + 0x0100153a: 4910 .I LDR r1,[pc,#64] ; [0x100157c] = 0x1007304 + 0x0100153c: a010 .. ADR r0,{pc}+0x44 ; 0x1001580 + 0x0100153e: f002f85f .._. BL rt_assert_handler ; 0x1003600 + 0x01001542: 9400 .. STR r4,[sp,#0] + 0x01001544: e013 .. B 0x100156e ; _serial_poll_rx + 66 + 0x01001546: 6c30 0l LDR r0,[r6,#0x40] + 0x01001548: 68c1 .h LDR r1,[r0,#0xc] + 0x0100154a: 4630 0F MOV r0,r6 + 0x0100154c: 4788 .G BLX r1 + 0x0100154e: 4605 .F MOV r5,r0 + 0x01001550: 1c68 h. ADDS r0,r5,#1 + 0x01001552: 2800 .( CMP r0,#0 + 0x01001554: d100 .. BNE 0x1001558 ; _serial_poll_rx + 44 + 0x01001556: e00c .. B 0x1001572 ; _serial_poll_rx + 70 + 0x01001558: 703d =p STRB r5,[r7,#0] + 0x0100155a: 1c7f .. ADDS r7,r7,#1 + 0x0100155c: 1e64 d. SUBS r4,r4,#1 + 0x0100155e: 8b30 0. LDRH r0,[r6,#0x18] + 0x01001560: 2140 @! MOVS r1,#0x40 + 0x01001562: 4008 .@ ANDS r0,r0,r1 + 0x01001564: 2800 .( CMP r0,#0 + 0x01001566: d002 .. BEQ 0x100156e ; _serial_poll_rx + 66 + 0x01001568: 2d0a .- CMP r5,#0xa + 0x0100156a: d100 .. BNE 0x100156e ; _serial_poll_rx + 66 + 0x0100156c: e001 .. B 0x1001572 ; _serial_poll_rx + 70 + 0x0100156e: 2c00 ., CMP r4,#0 + 0x01001570: d1e9 .. BNE 0x1001546 ; _serial_poll_rx + 26 + 0x01001572: bf00 .. NOP + 0x01001574: 9800 .. LDR r0,[sp,#0] + 0x01001576: 1b00 .. SUBS r0,r0,r4 + 0x01001578: bdf8 .. POP {r3-r7,pc} + $d + 0x0100157a: 0000 .. DCW 0 + 0x0100157c: 01007304 .s.. DCD 16806660 + 0x01001580: 69726573 seri DCD 1769104755 + 0x01001584: 21206c61 al ! DCD 555773025 + 0x01001588: 5452203d = RT DCD 1414668349 + 0x0100158c: 4c554e5f _NUL DCD 1280659039 + 0x01001590: 0000004c L... DCD 76 + $t + i._serial_poll_tx + _serial_poll_tx + 0x01001594: b5f8 .. PUSH {r3-r7,lr} + 0x01001596: 4604 .F MOV r4,r0 + 0x01001598: 460e .F MOV r6,r1 + 0x0100159a: 4615 .F MOV r5,r2 + 0x0100159c: 2c00 ., CMP r4,#0 + 0x0100159e: d104 .. BNE 0x10015aa ; _serial_poll_tx + 22 + 0x010015a0: 22ef ." MOVS r2,#0xef + 0x010015a2: 490f .I LDR r1,[pc,#60] ; [0x10015e0] = 0x1007314 + 0x010015a4: 480f .H LDR r0,[pc,#60] ; [0x10015e4] = 0x1001580 + 0x010015a6: f002f82b ..+. BL rt_assert_handler ; 0x1003600 + 0x010015aa: 462f /F MOV r7,r5 + 0x010015ac: e013 .. B 0x10015d6 ; _serial_poll_tx + 66 + 0x010015ae: 7830 0x LDRB r0,[r6,#0] + 0x010015b0: 280a .( CMP r0,#0xa + 0x010015b2: d109 .. BNE 0x10015c8 ; _serial_poll_tx + 52 + 0x010015b4: 8b20 . LDRH r0,[r4,#0x18] + 0x010015b6: 2140 @! MOVS r1,#0x40 + 0x010015b8: 4008 .@ ANDS r0,r0,r1 + 0x010015ba: 2800 .( CMP r0,#0 + 0x010015bc: d004 .. BEQ 0x10015c8 ; _serial_poll_tx + 52 + 0x010015be: 6c20 l LDR r0,[r4,#0x40] + 0x010015c0: 210d .! MOVS r1,#0xd + 0x010015c2: 6882 .h LDR r2,[r0,#8] + 0x010015c4: 4620 F MOV r0,r4 + 0x010015c6: 4790 .G BLX r2 + 0x010015c8: 7831 1x LDRB r1,[r6,#0] + 0x010015ca: 6c20 l LDR r0,[r4,#0x40] + 0x010015cc: 6882 .h LDR r2,[r0,#8] + 0x010015ce: 4620 F MOV r0,r4 + 0x010015d0: 4790 .G BLX r2 + 0x010015d2: 1c76 v. ADDS r6,r6,#1 + 0x010015d4: 1e6d m. SUBS r5,r5,#1 + 0x010015d6: 2d00 .- CMP r5,#0 + 0x010015d8: d1e9 .. BNE 0x10015ae ; _serial_poll_tx + 26 + 0x010015da: 1b78 x. SUBS r0,r7,r5 + 0x010015dc: bdf8 .. POP {r3-r7,pc} + $d + 0x010015de: 0000 .. DCW 0 + 0x010015e0: 01007314 .s.. DCD 16806676 + 0x010015e4: 01001580 .... DCD 16782720 + $t + i._thread_cleanup_execute + _thread_cleanup_execute + 0x010015e8: b570 p. PUSH {r4-r6,lr} + 0x010015ea: 4604 .F MOV r4,r0 + 0x010015ec: f7feff68 ..h. BL rt_hw_interrupt_disable ; 0x10004c0 + 0x010015f0: 4605 .F MOV r5,r0 + 0x010015f2: 6fa0 .o LDR r0,[r4,#0x78] + 0x010015f4: 2800 .( CMP r0,#0 + 0x010015f6: d002 .. BEQ 0x10015fe ; _thread_cleanup_execute + 22 + 0x010015f8: 4620 F MOV r0,r4 + 0x010015fa: 6fa1 .o LDR r1,[r4,#0x78] + 0x010015fc: 4788 .G BLX r1 + 0x010015fe: 4628 (F MOV r0,r5 + 0x01001600: f7feff62 ..b. BL rt_hw_interrupt_enable ; 0x10004c8 + 0x01001604: bd70 p. POP {r4-r6,pc} + i._thread_exit + _thread_exit + 0x01001606: b570 p. PUSH {r4-r6,lr} + 0x01001608: f004fcca .... BL rt_thread_self ; 0x1005fa0 + 0x0100160c: 4604 .F MOV r4,r0 + 0x0100160e: f7feff57 ..W. BL rt_hw_interrupt_disable ; 0x10004c0 + 0x01001612: 4605 .F MOV r5,r0 + 0x01001614: 4620 F MOV r0,r4 + 0x01001616: f7ffffe7 .... BL _thread_cleanup_execute ; 0x10015e8 + 0x0100161a: 4620 F MOV r0,r4 + 0x0100161c: f003fe0c .... BL rt_schedule_remove_thread ; 0x1005238 + 0x01001620: 2104 .! MOVS r1,#4 + 0x01001622: 2034 4 MOVS r0,#0x34 + 0x01001624: 5501 .U STRB r1,[r0,r4] + 0x01001626: 4620 F MOV r0,r4 + 0x01001628: 304c L0 ADDS r0,r0,#0x4c + 0x0100162a: f004ff6b ..k. BL rt_timer_detach ; 0x1006504 + 0x0100162e: 4620 F MOV r0,r4 + 0x01001630: f003fc98 .... BL rt_object_is_systemobject ; 0x1004f64 + 0x01001634: 2801 .( CMP r0,#1 + 0x01001636: d103 .. BNE 0x1001640 ; _thread_exit + 58 + 0x01001638: 4620 F MOV r0,r4 + 0x0100163a: f003fb33 ..3. BL rt_object_detach ; 0x1004ca4 + 0x0100163e: e002 .. B 0x1001646 ; _thread_exit + 64 + 0x01001640: 4620 F MOV r0,r4 + 0x01001642: f004fbc1 .... BL rt_thread_defunct_enqueue ; 0x1005dc8 + 0x01001646: f003fcf5 .... BL rt_schedule ; 0x1005034 + 0x0100164a: 4628 (F MOV r0,r5 + 0x0100164c: f7feff3c ..<. BL rt_hw_interrupt_enable ; 0x10004c8 + 0x01001650: bd70 p. POP {r4-r6,pc} + 0x01001652: 0000 .. MOVS r0,r0 + i._thread_init + _thread_init + 0x01001654: b5fe .. PUSH {r1-r7,lr} + 0x01001656: 4604 .F MOV r4,r0 + 0x01001658: 4616 .F MOV r6,r2 + 0x0100165a: 461f .F MOV r7,r3 + 0x0100165c: 9d0a .. LDR r5,[sp,#0x28] + 0x0100165e: 4620 F MOV r0,r4 + 0x01001660: 3014 .0 ADDS r0,r0,#0x14 + 0x01001662: 6040 @` STR r0,[r0,#4] + 0x01001664: 6000 .` STR r0,[r0,#0] + 0x01001666: bf00 .. NOP + 0x01001668: 6226 &b STR r6,[r4,#0x20] + 0x0100166a: 6267 gb STR r7,[r4,#0x24] + 0x0100166c: 9808 .. LDR r0,[sp,#0x20] + 0x0100166e: 62a0 .b STR r0,[r4,#0x28] + 0x01001670: 9809 .. LDR r0,[sp,#0x24] + 0x01001672: 62e0 .b STR r0,[r4,#0x2c] + 0x01001674: 2123 #! MOVS r1,#0x23 + 0x01001676: 6ae2 .j LDR r2,[r4,#0x2c] + 0x01001678: 6aa0 .j LDR r0,[r4,#0x28] + 0x0100167a: f003fa22 ..". BL rt_memset ; 0x1004ac2 + 0x0100167e: 6ae1 .j LDR r1,[r4,#0x2c] + 0x01001680: 6aa0 .j LDR r0,[r4,#0x28] + 0x01001682: 1840 @. ADDS r0,r0,r1 + 0x01001684: 1f02 .. SUBS r2,r0,#4 + 0x01001686: 6a60 `j LDR r0,[r4,#0x24] + 0x01001688: 9001 .. STR r0,[sp,#4] + 0x0100168a: 6a20 j LDR r0,[r4,#0x20] + 0x0100168c: 4b19 .K LDR r3,[pc,#100] ; [0x10016f4] = 0x1001607 + 0x0100168e: 9000 .. STR r0,[sp,#0] + 0x01001690: 9901 .. LDR r1,[sp,#4] + 0x01001692: f002fe89 .... BL rt_hw_stack_init ; 0x10043a8 + 0x01001696: 61e0 .a STR r0,[r4,#0x1c] + 0x01001698: 2d20 - CMP r5,#0x20 + 0x0100169a: db04 .. BLT 0x10016a6 ; _thread_init + 82 + 0x0100169c: 22ae ." MOVS r2,#0xae + 0x0100169e: 4916 .I LDR r1,[pc,#88] ; [0x10016f8] = 0x1007b32 + 0x010016a0: a016 .. ADR r0,{pc}+0x5c ; 0x10016fc + 0x010016a2: f001ffad .... BL rt_assert_handler ; 0x1003600 + 0x010016a6: 2036 6 MOVS r0,#0x36 + 0x010016a8: 5505 .U STRB r5,[r0,r4] + 0x010016aa: 2035 5 MOVS r0,#0x35 + 0x010016ac: 5505 .U STRB r5,[r0,r4] + 0x010016ae: 2000 . MOVS r0,#0 + 0x010016b0: 63a0 .c STR r0,[r4,#0x38] + 0x010016b2: 980b .. LDR r0,[sp,#0x2c] + 0x010016b4: 6460 `d STR r0,[r4,#0x44] + 0x010016b6: 980b .. LDR r0,[sp,#0x2c] + 0x010016b8: 64a0 .d STR r0,[r4,#0x48] + 0x010016ba: 2000 . MOVS r0,#0 + 0x010016bc: 6320 c STR r0,[r4,#0x30] + 0x010016be: 2100 .! MOVS r1,#0 + 0x010016c0: 2034 4 MOVS r0,#0x34 + 0x010016c2: 5501 .U STRB r1,[r0,r4] + 0x010016c4: 2000 . MOVS r0,#0 + 0x010016c6: 67a0 .g STR r0,[r4,#0x78] + 0x010016c8: 67e0 .g STR r0,[r4,#0x7c] + 0x010016ca: 9000 .. STR r0,[sp,#0] + 0x010016cc: 4623 #F MOV r3,r4 + 0x010016ce: 4a14 .J LDR r2,[pc,#80] ; [0x1001720] = 0x10061d9 + 0x010016d0: 4621 !F MOV r1,r4 + 0x010016d2: 9001 .. STR r0,[sp,#4] + 0x010016d4: 4620 F MOV r0,r4 + 0x010016d6: 304c L0 ADDS r0,r0,#0x4c + 0x010016d8: f004ff86 .... BL rt_timer_init ; 0x10065e8 + 0x010016dc: bf00 .. NOP + 0x010016de: 4811 .H LDR r0,[pc,#68] ; [0x1001724] = 0x20130 + 0x010016e0: 6800 .h LDR r0,[r0,#0] + 0x010016e2: 2800 .( CMP r0,#0 + 0x010016e4: d003 .. BEQ 0x10016ee ; _thread_init + 154 + 0x010016e6: 4620 F MOV r0,r4 + 0x010016e8: 490e .I LDR r1,[pc,#56] ; [0x1001724] = 0x20130 + 0x010016ea: 6809 .h LDR r1,[r1,#0] + 0x010016ec: 4788 .G BLX r1 + 0x010016ee: bf00 .. NOP + 0x010016f0: 2000 . MOVS r0,#0 + 0x010016f2: bdfe .. POP {r1-r7,pc} + $d + 0x010016f4: 01001607 .... DCD 16782855 + 0x010016f8: 01007b32 2{.. DCD 16808754 + 0x010016fc: 6f697270 prio DCD 1869181552 + 0x01001700: 79746972 rity DCD 2037672306 + 0x01001704: 52203c20 < R DCD 1377844256 + 0x01001708: 48545f54 T_TH DCD 1213488980 + 0x0100170c: 44414552 READ DCD 1145128274 + 0x01001710: 4952505f _PRI DCD 1230131295 + 0x01001714: 5449524f ORIT DCD 1414091343 + 0x01001718: 414d5f59 Y_MA DCD 1095589721 + 0x0100171c: 00000058 X... DCD 88 + 0x01001720: 010061d9 .a.. DCD 16802265 + 0x01001724: 00020130 0... DCD 131376 + $t + i._timer_init + _timer_init + 0x01001728: b5ff .. PUSH {r0-r7,lr} + 0x0100172a: b081 .. SUB sp,sp,#4 + 0x0100172c: 4604 .F MOV r4,r0 + 0x0100172e: 460e .F MOV r6,r1 + 0x01001730: 4617 .F MOV r7,r2 + 0x01001732: 980a .. LDR r0,[sp,#0x28] + 0x01001734: 7260 `r STRB r0,[r4,#9] + 0x01001736: 7a60 `z LDRB r0,[r4,#9] + 0x01001738: 0840 @. LSRS r0,r0,#1 + 0x0100173a: 0040 @. LSLS r0,r0,#1 + 0x0100173c: 7260 `r STRB r0,[r4,#9] + 0x0100173e: 61e6 .a STR r6,[r4,#0x1c] + 0x01001740: 6227 'b STR r7,[r4,#0x20] + 0x01001742: 2000 . MOVS r0,#0 + 0x01001744: 62a0 .b STR r0,[r4,#0x28] + 0x01001746: 9804 .. LDR r0,[sp,#0x10] + 0x01001748: 6260 `b STR r0,[r4,#0x24] + 0x0100174a: 2500 .% MOVS r5,#0 + 0x0100174c: e006 .. B 0x100175c ; _timer_init + 52 + 0x0100174e: 00ea .. LSLS r2,r5,#3 + 0x01001750: 4621 !F MOV r1,r4 + 0x01001752: 3114 .1 ADDS r1,r1,#0x14 + 0x01001754: 1850 P. ADDS r0,r2,r1 + 0x01001756: f002fee6 .... BL rt_list_init ; 0x1004526 + 0x0100175a: 1c6d m. ADDS r5,r5,#1 + 0x0100175c: 2d01 .- CMP r5,#1 + 0x0100175e: dbf6 .. BLT 0x100174e ; _timer_init + 38 + 0x01001760: b005 .. ADD sp,sp,#0x14 + 0x01001762: bdf0 .. POP {r4-r7,pc} + i._timer_remove + _timer_remove + 0x01001764: b570 p. PUSH {r4-r6,lr} + 0x01001766: 4605 .F MOV r5,r0 + 0x01001768: 2400 .$ MOVS r4,#0 + 0x0100176a: e006 .. B 0x100177a ; _timer_remove + 22 + 0x0100176c: 00e2 .. LSLS r2,r4,#3 + 0x0100176e: 4629 )F MOV r1,r5 + 0x01001770: 3114 .1 ADDS r1,r1,#0x14 + 0x01001772: 1850 P. ADDS r0,r2,r1 + 0x01001774: f002ff19 .... BL rt_list_remove ; 0x10045aa + 0x01001778: 1c64 d. ADDS r4,r4,#1 + 0x0100177a: 2c01 ., CMP r4,#1 + 0x0100177c: dbf6 .. BLT 0x100176c ; _timer_remove + 8 + 0x0100177e: bd70 p. POP {r4-r6,pc} + i.bsp_clock_config + bsp_clock_config + 0x01001780: b510 .. PUSH {r4,lr} + 0x01001782: 4802 .H LDR r0,[pc,#8] ; [0x100178c] = 0x75300 + 0x01001784: f7fff99c .... BL SysTick_Config ; 0x1000ac0 + 0x01001788: bd10 .. POP {r4,pc} + $d + 0x0100178a: 0000 .. DCW 0 + 0x0100178c: 00075300 .S.. DCD 480000 + $t + i.clear + clear + 0x01001790: b510 .. PUSH {r4,lr} + 0x01001792: a002 .. ADR r0,{pc}+0xa ; 0x100179c + 0x01001794: f002fe9c .... BL rt_kprintf ; 0x10044d0 + 0x01001798: 2000 . MOVS r0,#0 + 0x0100179a: bd10 .. POP {r4,pc} + $d + 0x0100179c: 4a325b1b .[2J DCD 1244814107 + 0x010017a0: 00485b1b .[H. DCD 4741915 + $t + i.cmd_free + cmd_free + 0x010017a4: b570 p. PUSH {r4-r6,lr} + 0x010017a6: 4604 .F MOV r4,r0 + 0x010017a8: 460d .F MOV r5,r1 + 0x010017aa: f000ff09 .... BL list_mem ; 0x10025c0 + 0x010017ae: 2000 . MOVS r0,#0 + 0x010017b0: bd70 p. POP {r4-r6,pc} + i.cmd_ps + cmd_ps + 0x010017b2: b570 p. PUSH {r4-r6,lr} + 0x010017b4: 4604 .F MOV r4,r0 + 0x010017b6: 460d .F MOV r5,r1 + 0x010017b8: f001fa4a ..J. BL list_thread ; 0x1002c50 + 0x010017bc: 2000 . MOVS r0,#0 + 0x010017be: bd70 p. POP {r4-r6,pc} + i.finsh_get_prompt + finsh_get_prompt + 0x010017c0: b510 .. PUSH {r4,lr} + 0x010017c2: 4811 .H LDR r0,[pc,#68] ; [0x1001808] = 0x2001c + 0x010017c4: 6800 .h LDR r0,[r0,#0] + 0x010017c6: 3020 0 ADDS r0,r0,#0x20 + 0x010017c8: 7840 @x LDRB r0,[r0,#1] + 0x010017ca: 0780 .. LSLS r0,r0,#30 + 0x010017cc: 0fc0 .. LSRS r0,r0,#31 + 0x010017ce: 2800 .( CMP r0,#0 + 0x010017d0: d103 .. BNE 0x10017da ; finsh_get_prompt + 26 + 0x010017d2: 490e .I LDR r1,[pc,#56] ; [0x100180c] = 0x201f0 + 0x010017d4: 7008 .p STRB r0,[r1,#0] + 0x010017d6: 4608 .F MOV r0,r1 + 0x010017d8: bd10 .. POP {r4,pc} + 0x010017da: 480d .H LDR r0,[pc,#52] ; [0x1001810] = 0x20020 + 0x010017dc: 6800 .h LDR r0,[r0,#0] + 0x010017de: 2800 .( CMP r0,#0 + 0x010017e0: d007 .. BEQ 0x10017f2 ; finsh_get_prompt + 50 + 0x010017e2: 2280 ." MOVS r2,#0x80 + 0x010017e4: 480a .H LDR r0,[pc,#40] ; [0x1001810] = 0x20020 + 0x010017e6: 6801 .h LDR r1,[r0,#0] + 0x010017e8: 4808 .H LDR r0,[pc,#32] ; [0x100180c] = 0x201f0 + 0x010017ea: f7fff809 .... BL strncpy ; 0x1000800 + 0x010017ee: 4807 .H LDR r0,[pc,#28] ; [0x100180c] = 0x201f0 + 0x010017f0: e7f2 .. B 0x10017d8 ; finsh_get_prompt + 24 + 0x010017f2: a108 .. ADR r1,{pc}+0x22 ; 0x1001814 + 0x010017f4: 4805 .H LDR r0,[pc,#20] ; [0x100180c] = 0x201f0 + 0x010017f6: f7fefefd .... BL strcpy ; 0x10005f4 + 0x010017fa: a108 .. ADR r1,{pc}+0x22 ; 0x100181c + 0x010017fc: 4803 .H LDR r0,[pc,#12] ; [0x100180c] = 0x201f0 + 0x010017fe: f7feff91 .... BL strcat ; 0x1000724 + 0x01001802: 4802 .H LDR r0,[pc,#8] ; [0x100180c] = 0x201f0 + 0x01001804: e7e8 .. B 0x10017d8 ; finsh_get_prompt + 24 + $d + 0x01001806: 0000 .. DCW 0 + 0x01001808: 0002001c .... DCD 131100 + 0x0100180c: 000201f0 .... DCD 131568 + 0x01001810: 00020020 ... DCD 131104 + 0x01001814: 2068736d msh DCD 543716205 + 0x01001818: 00000000 .... DCD 0 + 0x0100181c: 0000003e >... DCD 62 + $t + i.finsh_getchar + finsh_getchar + 0x01001820: b508 .. PUSH {r3,lr} + 0x01001822: 2000 . MOVS r0,#0 + 0x01001824: 9000 .. STR r0,[sp,#0] + 0x01001826: 4810 .H LDR r0,[pc,#64] ; [0x1001868] = 0x2001c + 0x01001828: 6800 .h LDR r0,[r0,#0] + 0x0100182a: 2800 .( CMP r0,#0 + 0x0100182c: d104 .. BNE 0x1001838 ; finsh_getchar + 24 + 0x0100182e: 2299 ." MOVS r2,#0x99 + 0x01001830: 490e .I LDR r1,[pc,#56] ; [0x100186c] = 0x10074b4 + 0x01001832: a00f .. ADR r0,{pc}+0x3e ; 0x1001870 + 0x01001834: f001fee4 .... BL rt_assert_handler ; 0x1003600 + 0x01001838: e005 .. B 0x1001846 ; finsh_getchar + 38 + 0x0100183a: 2100 .! MOVS r1,#0 + 0x0100183c: 43c9 .C MVNS r1,r1 + 0x0100183e: 480a .H LDR r0,[pc,#40] ; [0x1001868] = 0x2001c + 0x01001840: 6800 .h LDR r0,[r0,#0] + 0x01001842: f003fdcd .... BL rt_sem_take ; 0x10053e0 + 0x01001846: 4908 .I LDR r1,[pc,#32] ; [0x1001868] = 0x2001c + 0x01001848: 6809 .h LDR r1,[r1,#0] + 0x0100184a: 31ff .1 ADDS r1,r1,#0xff + 0x0100184c: 31ff .1 ADDS r1,r1,#0xff + 0x0100184e: 3102 .1 ADDS r1,#2 + 0x01001850: 2301 .# MOVS r3,#1 + 0x01001852: 466a jF MOV r2,sp + 0x01001854: 68c8 .h LDR r0,[r1,#0xc] + 0x01001856: 1e99 .. SUBS r1,r3,#2 + 0x01001858: f002f9f4 .... BL rt_device_read ; 0x1003c44 + 0x0100185c: 2801 .( CMP r0,#1 + 0x0100185e: d1ec .. BNE 0x100183a ; finsh_getchar + 26 + 0x01001860: 4668 hF MOV r0,sp + 0x01001862: 7800 .x LDRB r0,[r0,#0] + 0x01001864: bd08 .. POP {r3,pc} + $d + 0x01001866: 0000 .. DCW 0 + 0x01001868: 0002001c .... DCD 131100 + 0x0100186c: 010074b4 .t.. DCD 16807092 + 0x01001870: 6c656873 shel DCD 1818585203 + 0x01001874: 3d21206c l != DCD 1025581164 + 0x01001878: 5f545220 RT_ DCD 1599361568 + 0x0100187c: 4c4c554e NULL DCD 1280070990 + 0x01001880: 00000000 .... DCD 0 + $t + i.finsh_rx_ind + finsh_rx_ind + 0x01001884: b570 p. PUSH {r4-r6,lr} + 0x01001886: 4604 .F MOV r4,r0 + 0x01001888: 460d .F MOV r5,r1 + 0x0100188a: 4807 .H LDR r0,[pc,#28] ; [0x10018a8] = 0x2001c + 0x0100188c: 6800 .h LDR r0,[r0,#0] + 0x0100188e: 2800 .( CMP r0,#0 + 0x01001890: d104 .. BNE 0x100189c ; finsh_rx_ind + 24 + 0x01001892: 22a8 ." MOVS r2,#0xa8 + 0x01001894: 4905 .I LDR r1,[pc,#20] ; [0x10018ac] = 0x10074c2 + 0x01001896: a006 .. ADR r0,{pc}+0x1a ; 0x10018b0 + 0x01001898: f001feb2 .... BL rt_assert_handler ; 0x1003600 + 0x0100189c: 4802 .H LDR r0,[pc,#8] ; [0x10018a8] = 0x2001c + 0x0100189e: 6800 .h LDR r0,[r0,#0] + 0x010018a0: f003fd44 ..D. BL rt_sem_release ; 0x100532c + 0x010018a4: 2000 . MOVS r0,#0 + 0x010018a6: bd70 p. POP {r4-r6,pc} + $d + 0x010018a8: 0002001c .... DCD 131100 + 0x010018ac: 010074c2 .t.. DCD 16807106 + 0x010018b0: 6c656873 shel DCD 1818585203 + 0x010018b4: 3d21206c l != DCD 1025581164 + 0x010018b8: 5f545220 RT_ DCD 1599361568 + 0x010018bc: 4c4c554e NULL DCD 1280070990 + 0x010018c0: 00000000 .... DCD 0 + $t + i.finsh_set_device + finsh_set_device + 0x010018c4: b570 p. PUSH {r4-r6,lr} + 0x010018c6: 4605 .F MOV r5,r0 + 0x010018c8: 2400 .$ MOVS r4,#0 + 0x010018ca: 482e .H LDR r0,[pc,#184] ; [0x1001984] = 0x2001c + 0x010018cc: 6800 .h LDR r0,[r0,#0] + 0x010018ce: 2800 .( CMP r0,#0 + 0x010018d0: d104 .. BNE 0x10018dc ; finsh_set_device + 24 + 0x010018d2: 22bb ." MOVS r2,#0xbb + 0x010018d4: 492c ,I LDR r1,[pc,#176] ; [0x1001988] = 0x10074cf + 0x010018d6: a02d -. ADR r0,{pc}+0xb6 ; 0x100198c + 0x010018d8: f001fe92 .... BL rt_assert_handler ; 0x1003600 + 0x010018dc: 4628 (F MOV r0,r5 + 0x010018de: f002f8d9 .... BL rt_device_find ; 0x1003a94 + 0x010018e2: 4604 .F MOV r4,r0 + 0x010018e4: 2c00 ., CMP r4,#0 + 0x010018e6: d104 .. BNE 0x10018f2 ; finsh_set_device + 46 + 0x010018e8: 4629 )F MOV r1,r5 + 0x010018ea: a02d -. ADR r0,{pc}+0xb6 ; 0x10019a0 + 0x010018ec: f002fdf0 .... BL rt_kprintf ; 0x10044d0 + 0x010018f0: bd70 p. POP {r4-r6,pc} + 0x010018f2: 4824 $H LDR r0,[pc,#144] ; [0x1001984] = 0x2001c + 0x010018f4: 6800 .h LDR r0,[r0,#0] + 0x010018f6: 30ff .0 ADDS r0,r0,#0xff + 0x010018f8: 30ff .0 ADDS r0,r0,#0xff + 0x010018fa: 3002 .0 ADDS r0,#2 + 0x010018fc: 68c0 .h LDR r0,[r0,#0xc] + 0x010018fe: 42a0 .B CMP r0,r4 + 0x01001900: d100 .. BNE 0x1001904 ; finsh_set_device + 64 + 0x01001902: e7f5 .. B 0x10018f0 ; finsh_set_device + 44 + 0x01001904: 21ff .! MOVS r1,#0xff + 0x01001906: 3144 D1 ADDS r1,r1,#0x44 + 0x01001908: 4620 F MOV r0,r4 + 0x0100190a: f002f8cb .... BL rt_device_open ; 0x1003aa4 + 0x0100190e: 2800 .( CMP r0,#0 + 0x01001910: d136 6. BNE 0x1001980 ; finsh_set_device + 188 + 0x01001912: 481c .H LDR r0,[pc,#112] ; [0x1001984] = 0x2001c + 0x01001914: 6800 .h LDR r0,[r0,#0] + 0x01001916: 30ff .0 ADDS r0,r0,#0xff + 0x01001918: 30ff .0 ADDS r0,r0,#0xff + 0x0100191a: 3002 .0 ADDS r0,#2 + 0x0100191c: 68c0 .h LDR r0,[r0,#0xc] + 0x0100191e: 2800 .( CMP r0,#0 + 0x01001920: d010 .. BEQ 0x1001944 ; finsh_set_device + 128 + 0x01001922: 4918 .I LDR r1,[pc,#96] ; [0x1001984] = 0x2001c + 0x01001924: 6809 .h LDR r1,[r1,#0] + 0x01001926: 31ff .1 ADDS r1,r1,#0xff + 0x01001928: 31ff .1 ADDS r1,r1,#0xff + 0x0100192a: 3102 .1 ADDS r1,#2 + 0x0100192c: 68c8 .h LDR r0,[r1,#0xc] + 0x0100192e: f002f855 ..U. BL rt_device_close ; 0x10039dc + 0x01001932: 4914 .I LDR r1,[pc,#80] ; [0x1001984] = 0x2001c + 0x01001934: 6809 .h LDR r1,[r1,#0] + 0x01001936: 31ff .1 ADDS r1,r1,#0xff + 0x01001938: 31ff .1 ADDS r1,r1,#0xff + 0x0100193a: 3102 .1 ADDS r1,#2 + 0x0100193c: 68c8 .h LDR r0,[r1,#0xc] + 0x0100193e: 2100 .! MOVS r1,#0 + 0x01001940: f002f9f6 .... BL rt_device_set_rx_indicate ; 0x1003d30 + 0x01001944: 2151 Q! MOVS r1,#0x51 + 0x01001946: 480f .H LDR r0,[pc,#60] ; [0x1001984] = 0x2001c + 0x01001948: 6800 .h LDR r0,[r0,#0] + 0x0100194a: 30ff .0 ADDS r0,r0,#0xff + 0x0100194c: 30b7 .0 ADDS r0,r0,#0xb7 + 0x0100194e: f7feff52 ..R. BL __aeabi_memclr ; 0x10007f6 + 0x01001952: 2100 .! MOVS r1,#0 + 0x01001954: 480b .H LDR r0,[pc,#44] ; [0x1001984] = 0x2001c + 0x01001956: 6800 .h LDR r0,[r0,#0] + 0x01001958: 30ff .0 ADDS r0,r0,#0xff + 0x0100195a: 30ff .0 ADDS r0,r0,#0xff + 0x0100195c: 3002 .0 ADDS r0,#2 + 0x0100195e: 8101 .. STRH r1,[r0,#8] + 0x01001960: 4808 .H LDR r0,[pc,#32] ; [0x1001984] = 0x2001c + 0x01001962: 6800 .h LDR r0,[r0,#0] + 0x01001964: 30ff .0 ADDS r0,r0,#0xff + 0x01001966: 30ff .0 ADDS r0,r0,#0xff + 0x01001968: 3002 .0 ADDS r0,#2 + 0x0100196a: 8141 A. STRH r1,[r0,#0xa] + 0x0100196c: 4805 .H LDR r0,[pc,#20] ; [0x1001984] = 0x2001c + 0x0100196e: 6800 .h LDR r0,[r0,#0] + 0x01001970: 30ff .0 ADDS r0,r0,#0xff + 0x01001972: 30ff .0 ADDS r0,r0,#0xff + 0x01001974: 3002 .0 ADDS r0,#2 + 0x01001976: 60c4 .` STR r4,[r0,#0xc] + 0x01001978: 4911 .I LDR r1,[pc,#68] ; [0x10019c0] = 0x1001885 + 0x0100197a: 4620 F MOV r0,r4 + 0x0100197c: f002f9d8 .... BL rt_device_set_rx_indicate ; 0x1003d30 + 0x01001980: bf00 .. NOP + 0x01001982: e7b5 .. B 0x10018f0 ; finsh_set_device + 44 + $d + 0x01001984: 0002001c .... DCD 131100 + 0x01001988: 010074cf .t.. DCD 16807119 + 0x0100198c: 6c656873 shel DCD 1818585203 + 0x01001990: 3d21206c l != DCD 1025581164 + 0x01001994: 5f545220 RT_ DCD 1599361568 + 0x01001998: 4c4c554e NULL DCD 1280070990 + 0x0100199c: 00000000 .... DCD 0 + 0x010019a0: 736e6966 fins DCD 1936615782 + 0x010019a4: 63203a68 h: c DCD 1663056488 + 0x010019a8: 6e206e61 an n DCD 1847619169 + 0x010019ac: 6620746f ot f DCD 1713402991 + 0x010019b0: 20646e69 ind DCD 543452777 + 0x010019b4: 69766564 devi DCD 1769366884 + 0x010019b8: 203a6563 ce: DCD 540697955 + 0x010019bc: 000a7325 %s.. DCD 684837 + 0x010019c0: 01001885 .... DCD 16783493 + $t + i.finsh_set_prompt_mode + finsh_set_prompt_mode + 0x010019c4: b510 .. PUSH {r4,lr} + 0x010019c6: 4604 .F MOV r4,r0 + 0x010019c8: 480b .H LDR r0,[pc,#44] ; [0x10019f8] = 0x2001c + 0x010019ca: 6800 .h LDR r0,[r0,#0] + 0x010019cc: 2800 .( CMP r0,#0 + 0x010019ce: d104 .. BNE 0x10019da ; finsh_set_prompt_mode + 22 + 0x010019d0: 228d ." MOVS r2,#0x8d + 0x010019d2: 490a .I LDR r1,[pc,#40] ; [0x10019fc] = 0x100749e + 0x010019d4: a00a .. ADR r0,{pc}+0x2c ; 0x1001a00 + 0x010019d6: f001fe13 .... BL rt_assert_handler ; 0x1003600 + 0x010019da: 4807 .H LDR r0,[pc,#28] ; [0x10019f8] = 0x2001c + 0x010019dc: 6800 .h LDR r0,[r0,#0] + 0x010019de: 3020 0 ADDS r0,r0,#0x20 + 0x010019e0: 7840 @x LDRB r0,[r0,#1] + 0x010019e2: 2102 .! MOVS r1,#2 + 0x010019e4: 4388 .C BICS r0,r0,r1 + 0x010019e6: 0061 a. LSLS r1,r4,#1 + 0x010019e8: 2202 ." MOVS r2,#2 + 0x010019ea: 4011 .@ ANDS r1,r1,r2 + 0x010019ec: 4308 .C ORRS r0,r0,r1 + 0x010019ee: 4902 .I LDR r1,[pc,#8] ; [0x10019f8] = 0x2001c + 0x010019f0: 6809 .h LDR r1,[r1,#0] + 0x010019f2: 3120 1 ADDS r1,r1,#0x20 + 0x010019f4: 7048 Hp STRB r0,[r1,#1] + 0x010019f6: bd10 .. POP {r4,pc} + $d + 0x010019f8: 0002001c .... DCD 131100 + 0x010019fc: 0100749e .t.. DCD 16807070 + 0x01001a00: 6c656873 shel DCD 1818585203 + 0x01001a04: 3d21206c l != DCD 1025581164 + 0x01001a08: 5f545220 RT_ DCD 1599361568 + 0x01001a0c: 4c4c554e NULL DCD 1280070990 + 0x01001a10: 00000000 .... DCD 0 + $t + i.finsh_system_function_init + finsh_system_function_init + 0x01001a14: 4a02 .J LDR r2,[pc,#8] ; [0x1001a20] = 0x20014 + 0x01001a16: 6010 .` STR r0,[r2,#0] + 0x01001a18: 4a02 .J LDR r2,[pc,#8] ; [0x1001a24] = 0x20018 + 0x01001a1a: 6011 .` STR r1,[r2,#0] + 0x01001a1c: 4770 pG BX lr + $d + 0x01001a1e: 0000 .. DCW 0 + 0x01001a20: 00020014 .... DCD 131092 + 0x01001a24: 00020018 .... DCD 131096 + $t + i.finsh_system_init + finsh_system_init + 0x01001a28: b57c |. PUSH {r2-r6,lr} + 0x01001a2a: 2500 .% MOVS r5,#0 + 0x01001a2c: 4919 .I LDR r1,[pc,#100] ; [0x1001a94] = 0x10083e4 + 0x01001a2e: 481a .H LDR r0,[pc,#104] ; [0x1001a98] = 0x100830c + 0x01001a30: f7fffff0 .... BL finsh_system_function_init ; 0x1001a14 + 0x01001a34: 2121 !! MOVS r1,#0x21 + 0x01001a36: 0109 .. LSLS r1,r1,#4 + 0x01001a38: 2001 . MOVS r0,#1 + 0x01001a3a: f001fe1d .... BL rt_calloc ; 0x1003678 + 0x01001a3e: 4917 .I LDR r1,[pc,#92] ; [0x1001a9c] = 0x2001c + 0x01001a40: 6008 .` STR r0,[r1,#0] + 0x01001a42: 4608 .F MOV r0,r1 + 0x01001a44: 6800 .h LDR r0,[r0,#0] + 0x01001a46: 2800 .( CMP r0,#0 + 0x01001a48: d104 .. BNE 0x1001a54 ; finsh_system_init + 44 + 0x01001a4a: a015 .. ADR r0,{pc}+0x56 ; 0x1001aa0 + 0x01001a4c: f002fd40 ..@. BL rt_kprintf ; 0x10044d0 + 0x01001a50: 1e68 h. SUBS r0,r5,#1 + 0x01001a52: bd7c |. POP {r2-r6,pc} + 0x01001a54: 200a . MOVS r0,#0xa + 0x01001a56: 2114 .! MOVS r1,#0x14 + 0x01001a58: 2301 .# MOVS r3,#1 + 0x01001a5a: 031b .. LSLS r3,r3,#12 + 0x01001a5c: 2200 ." MOVS r2,#0 + 0x01001a5e: 9100 .. STR r1,[sp,#0] + 0x01001a60: 9001 .. STR r0,[sp,#4] + 0x01001a62: 4915 .I LDR r1,[pc,#84] ; [0x1001ab8] = 0x1001acd + 0x01001a64: a015 .. ADR r0,{pc}+0x58 ; 0x1001abc + 0x01001a66: f004f96c ..l. BL rt_thread_create ; 0x1005d42 + 0x01001a6a: 4604 .F MOV r4,r0 + 0x01001a6c: 2300 .# MOVS r3,#0 + 0x01001a6e: 461a .F MOV r2,r3 + 0x01001a70: a114 .. ADR r1,{pc}+0x54 ; 0x1001ac4 + 0x01001a72: 480a .H LDR r0,[pc,#40] ; [0x1001a9c] = 0x2001c + 0x01001a74: 6800 .h LDR r0,[r0,#0] + 0x01001a76: f003fc21 ..!. BL rt_sem_init ; 0x10052bc + 0x01001a7a: 2001 . MOVS r0,#1 + 0x01001a7c: f7ffffa2 .... BL finsh_set_prompt_mode ; 0x10019c4 + 0x01001a80: 2c00 ., CMP r4,#0 + 0x01001a82: d004 .. BEQ 0x1001a8e ; finsh_system_init + 102 + 0x01001a84: 2d00 .- CMP r5,#0 + 0x01001a86: d102 .. BNE 0x1001a8e ; finsh_system_init + 102 + 0x01001a88: 4620 F MOV r0,r4 + 0x01001a8a: f004fad1 .... BL rt_thread_startup ; 0x1006030 + 0x01001a8e: 2000 . MOVS r0,#0 + 0x01001a90: e7df .. B 0x1001a52 ; finsh_system_init + 42 + $d + 0x01001a92: 0000 .. DCW 0 + 0x01001a94: 010083e4 .... DCD 16810980 + 0x01001a98: 0100830c .... DCD 16810764 + 0x01001a9c: 0002001c .... DCD 131100 + 0x01001aa0: 6d206f6e no m DCD 1830842222 + 0x01001aa4: 726f6d65 emor DCD 1919905125 + 0x01001aa8: 6f662079 y fo DCD 1868963961 + 0x01001aac: 68732072 r sh DCD 1752375410 + 0x01001ab0: 0a6c6c65 ell. DCD 174877797 + 0x01001ab4: 00000000 .... DCD 0 + 0x01001ab8: 01001acd .... DCD 16784077 + 0x01001abc: 65687374 tshe DCD 1701344116 + 0x01001ac0: 00006c6c ll.. DCD 27756 + 0x01001ac4: 78726873 shrx DCD 2020763763 + 0x01001ac8: 00000000 .... DCD 0 + $t + i.finsh_thread_entry + finsh_thread_entry + 0x01001acc: 48fe .H LDR r0,[pc,#1016] ; [0x1001ec8] = 0x2001c + 0x01001ace: 6800 .h LDR r0,[r0,#0] + 0x01001ad0: 3020 0 ADDS r0,r0,#0x20 + 0x01001ad2: 7840 @x LDRB r0,[r0,#1] + 0x01001ad4: 0840 @. LSRS r0,r0,#1 + 0x01001ad6: 0040 @. LSLS r0,r0,#1 + 0x01001ad8: 1c40 @. ADDS r0,r0,#1 + 0x01001ada: 49fb .I LDR r1,[pc,#1004] ; [0x1001ec8] = 0x2001c + 0x01001adc: 6809 .h LDR r1,[r1,#0] + 0x01001ade: 3120 1 ADDS r1,r1,#0x20 + 0x01001ae0: 7048 Hp STRB r0,[r1,#1] + 0x01001ae2: 48f9 .H LDR r0,[pc,#996] ; [0x1001ec8] = 0x2001c + 0x01001ae4: 6800 .h LDR r0,[r0,#0] + 0x01001ae6: 30ff .0 ADDS r0,r0,#0xff + 0x01001ae8: 30ff .0 ADDS r0,r0,#0xff + 0x01001aea: 3002 .0 ADDS r0,#2 + 0x01001aec: 68c0 .h LDR r0,[r0,#0xc] + 0x01001aee: 2800 .( CMP r0,#0 + 0x01001af0: d108 .. BNE 0x1001b04 ; finsh_thread_entry + 56 + 0x01001af2: f001feed .... BL rt_console_get_device ; 0x10038d0 + 0x01001af6: 4605 .F MOV r5,r0 + 0x01001af8: 2d00 .- CMP r5,#0 + 0x01001afa: d002 .. BEQ 0x1001b02 ; finsh_thread_entry + 54 + 0x01001afc: 4628 (F MOV r0,r5 + 0x01001afe: f7fffee1 .... BL finsh_set_device ; 0x10018c4 + 0x01001b02: bf00 .. NOP + 0x01001b04: f7fffe5c ..\. BL finsh_get_prompt ; 0x10017c0 + 0x01001b08: 4605 .F MOV r5,r0 + 0x01001b0a: f002fce1 .... BL rt_kprintf ; 0x10044d0 + 0x01001b0e: e2cf .. B 0x10020b0 ; finsh_thread_entry + 1508 + 0x01001b10: f7fffe86 .... BL finsh_getchar ; 0x1001820 + 0x01001b14: 4604 .F MOV r4,r0 + 0x01001b16: 2c00 ., CMP r4,#0 + 0x01001b18: da00 .. BGE 0x1001b1c ; finsh_thread_entry + 80 + 0x01001b1a: e2c9 .. B 0x10020b0 ; finsh_thread_entry + 1508 + 0x01001b1c: 2c1b ., CMP r4,#0x1b + 0x01001b1e: d105 .. BNE 0x1001b2c ; finsh_thread_entry + 96 + 0x01001b20: 2101 .! MOVS r1,#1 + 0x01001b22: 48e9 .H LDR r0,[pc,#932] ; [0x1001ec8] = 0x2001c + 0x01001b24: 6800 .h LDR r0,[r0,#0] + 0x01001b26: 3020 0 ADDS r0,r0,#0x20 + 0x01001b28: 7001 .p STRB r1,[r0,#0] + 0x01001b2a: e2c1 .. B 0x10020b0 ; finsh_thread_entry + 1508 + 0x01001b2c: 48e6 .H LDR r0,[pc,#920] ; [0x1001ec8] = 0x2001c + 0x01001b2e: 6800 .h LDR r0,[r0,#0] + 0x01001b30: 3020 0 ADDS r0,r0,#0x20 + 0x01001b32: 7800 .x LDRB r0,[r0,#0] + 0x01001b34: 2801 .( CMP r0,#1 + 0x01001b36: d10d .. BNE 0x1001b54 ; finsh_thread_entry + 136 + 0x01001b38: 2c5b [, CMP r4,#0x5b + 0x01001b3a: d105 .. BNE 0x1001b48 ; finsh_thread_entry + 124 + 0x01001b3c: 2102 .! MOVS r1,#2 + 0x01001b3e: 48e2 .H LDR r0,[pc,#904] ; [0x1001ec8] = 0x2001c + 0x01001b40: 6800 .h LDR r0,[r0,#0] + 0x01001b42: 3020 0 ADDS r0,r0,#0x20 + 0x01001b44: 7001 .p STRB r1,[r0,#0] + 0x01001b46: e2b3 .. B 0x10020b0 ; finsh_thread_entry + 1508 + 0x01001b48: 2100 .! MOVS r1,#0 + 0x01001b4a: 48df .H LDR r0,[pc,#892] ; [0x1001ec8] = 0x2001c + 0x01001b4c: 6800 .h LDR r0,[r0,#0] + 0x01001b4e: 3020 0 ADDS r0,r0,#0x20 + 0x01001b50: 7001 .p STRB r1,[r0,#0] + 0x01001b52: e0d8 .. B 0x1001d06 ; finsh_thread_entry + 570 + 0x01001b54: 48dc .H LDR r0,[pc,#880] ; [0x1001ec8] = 0x2001c + 0x01001b56: 6800 .h LDR r0,[r0,#0] + 0x01001b58: 3020 0 ADDS r0,r0,#0x20 + 0x01001b5a: 7800 .x LDRB r0,[r0,#0] + 0x01001b5c: 2802 .( CMP r0,#2 + 0x01001b5e: d1f8 .. BNE 0x1001b52 ; finsh_thread_entry + 134 + 0x01001b60: 2100 .! MOVS r1,#0 + 0x01001b62: 48d9 .H LDR r0,[pc,#868] ; [0x1001ec8] = 0x2001c + 0x01001b64: 6800 .h LDR r0,[r0,#0] + 0x01001b66: 3020 0 ADDS r0,r0,#0x20 + 0x01001b68: 7001 .p STRB r1,[r0,#0] + 0x01001b6a: 2c41 A, CMP r4,#0x41 + 0x01001b6c: d139 9. BNE 0x1001be2 ; finsh_thread_entry + 278 + 0x01001b6e: 48d6 .H LDR r0,[pc,#856] ; [0x1001ec8] = 0x2001c + 0x01001b70: 6800 .h LDR r0,[r0,#0] + 0x01001b72: 8c40 @. LDRH r0,[r0,#0x22] + 0x01001b74: 2800 .( CMP r0,#0 + 0x01001b76: dd07 .. BLE 0x1001b88 ; finsh_thread_entry + 188 + 0x01001b78: 48d3 .H LDR r0,[pc,#844] ; [0x1001ec8] = 0x2001c + 0x01001b7a: 6800 .h LDR r0,[r0,#0] + 0x01001b7c: 8c40 @. LDRH r0,[r0,#0x22] + 0x01001b7e: 1e40 @. SUBS r0,r0,#1 + 0x01001b80: 49d1 .I LDR r1,[pc,#836] ; [0x1001ec8] = 0x2001c + 0x01001b82: 6809 .h LDR r1,[r1,#0] + 0x01001b84: 8448 H. STRH r0,[r1,#0x22] + 0x01001b86: e004 .. B 0x1001b92 ; finsh_thread_entry + 198 + 0x01001b88: 2000 . MOVS r0,#0 + 0x01001b8a: 49cf .I LDR r1,[pc,#828] ; [0x1001ec8] = 0x2001c + 0x01001b8c: 6809 .h LDR r1,[r1,#0] + 0x01001b8e: 8448 H. STRH r0,[r1,#0x22] + 0x01001b90: e28e .. B 0x10020b0 ; finsh_thread_entry + 1508 + 0x01001b92: 48cd .H LDR r0,[pc,#820] ; [0x1001ec8] = 0x2001c + 0x01001b94: 6800 .h LDR r0,[r0,#0] + 0x01001b96: 8c40 @. LDRH r0,[r0,#0x22] + 0x01001b98: 2250 P" MOVS r2,#0x50 + 0x01001b9a: 4350 PC MULS r0,r2,r0 + 0x01001b9c: 4aca .J LDR r2,[pc,#808] ; [0x1001ec8] = 0x2001c + 0x01001b9e: 6812 .h LDR r2,[r2,#0] + 0x01001ba0: 3226 &2 ADDS r2,r2,#0x26 + 0x01001ba2: 1881 .. ADDS r1,r0,r2 + 0x01001ba4: 2250 P" MOVS r2,#0x50 + 0x01001ba6: 48c8 .H LDR r0,[pc,#800] ; [0x1001ec8] = 0x2001c + 0x01001ba8: 6800 .h LDR r0,[r0,#0] + 0x01001baa: 30ff .0 ADDS r0,r0,#0xff + 0x01001bac: 30b7 .0 ADDS r0,r0,#0xb7 + 0x01001bae: f7fefdc5 .... BL __aeabi_memcpy ; 0x100073c + 0x01001bb2: 48c5 .H LDR r0,[pc,#788] ; [0x1001ec8] = 0x2001c + 0x01001bb4: 6800 .h LDR r0,[r0,#0] + 0x01001bb6: 30ff .0 ADDS r0,r0,#0xff + 0x01001bb8: 30b7 .0 ADDS r0,r0,#0xb7 + 0x01001bba: f7fefd41 ..A. BL strlen ; 0x1000640 + 0x01001bbe: b281 .. UXTH r1,r0 + 0x01001bc0: 48c1 .H LDR r0,[pc,#772] ; [0x1001ec8] = 0x2001c + 0x01001bc2: 6800 .h LDR r0,[r0,#0] + 0x01001bc4: 30ff .0 ADDS r0,r0,#0xff + 0x01001bc6: 30ff .0 ADDS r0,r0,#0xff + 0x01001bc8: 3002 .0 ADDS r0,#2 + 0x01001bca: 8101 .. STRH r1,[r0,#8] + 0x01001bcc: 48be .H LDR r0,[pc,#760] ; [0x1001ec8] = 0x2001c + 0x01001bce: 6800 .h LDR r0,[r0,#0] + 0x01001bd0: 30ff .0 ADDS r0,r0,#0xff + 0x01001bd2: 30ff .0 ADDS r0,r0,#0xff + 0x01001bd4: 3002 .0 ADDS r0,#2 + 0x01001bd6: 8141 A. STRH r1,[r0,#0xa] + 0x01001bd8: 48bb .H LDR r0,[pc,#748] ; [0x1001ec8] = 0x2001c + 0x01001bda: 6800 .h LDR r0,[r0,#0] + 0x01001bdc: f005f874 ..t. BL shell_handle_history ; 0x1006cc8 + 0x01001be0: e266 f. B 0x10020b0 ; finsh_thread_entry + 1508 + 0x01001be2: 2c42 B, CMP r4,#0x42 + 0x01001be4: d146 F. BNE 0x1001c74 ; finsh_thread_entry + 424 + 0x01001be6: 48b8 .H LDR r0,[pc,#736] ; [0x1001ec8] = 0x2001c + 0x01001be8: 6800 .h LDR r0,[r0,#0] + 0x01001bea: 8c41 A. LDRH r1,[r0,#0x22] + 0x01001bec: 48b6 .H LDR r0,[pc,#728] ; [0x1001ec8] = 0x2001c + 0x01001bee: 6800 .h LDR r0,[r0,#0] + 0x01001bf0: 8c80 .. LDRH r0,[r0,#0x24] + 0x01001bf2: 1e40 @. SUBS r0,r0,#1 + 0x01001bf4: 4281 .B CMP r1,r0 + 0x01001bf6: da07 .. BGE 0x1001c08 ; finsh_thread_entry + 316 + 0x01001bf8: 48b3 .H LDR r0,[pc,#716] ; [0x1001ec8] = 0x2001c + 0x01001bfa: 6800 .h LDR r0,[r0,#0] + 0x01001bfc: 8c40 @. LDRH r0,[r0,#0x22] + 0x01001bfe: 1c40 @. ADDS r0,r0,#1 + 0x01001c00: 49b1 .I LDR r1,[pc,#708] ; [0x1001ec8] = 0x2001c + 0x01001c02: 6809 .h LDR r1,[r1,#0] + 0x01001c04: 8448 H. STRH r0,[r1,#0x22] + 0x01001c06: e00d .. B 0x1001c24 ; finsh_thread_entry + 344 + 0x01001c08: 48af .H LDR r0,[pc,#700] ; [0x1001ec8] = 0x2001c + 0x01001c0a: 6800 .h LDR r0,[r0,#0] + 0x01001c0c: 8c80 .. LDRH r0,[r0,#0x24] + 0x01001c0e: 2800 .( CMP r0,#0 + 0x01001c10: d007 .. BEQ 0x1001c22 ; finsh_thread_entry + 342 + 0x01001c12: 48ad .H LDR r0,[pc,#692] ; [0x1001ec8] = 0x2001c + 0x01001c14: 6800 .h LDR r0,[r0,#0] + 0x01001c16: 8c80 .. LDRH r0,[r0,#0x24] + 0x01001c18: 1e40 @. SUBS r0,r0,#1 + 0x01001c1a: 49ab .I LDR r1,[pc,#684] ; [0x1001ec8] = 0x2001c + 0x01001c1c: 6809 .h LDR r1,[r1,#0] + 0x01001c1e: 8448 H. STRH r0,[r1,#0x22] + 0x01001c20: e000 .. B 0x1001c24 ; finsh_thread_entry + 344 + 0x01001c22: e245 E. B 0x10020b0 ; finsh_thread_entry + 1508 + 0x01001c24: 48a8 .H LDR r0,[pc,#672] ; [0x1001ec8] = 0x2001c + 0x01001c26: 6800 .h LDR r0,[r0,#0] + 0x01001c28: 8c40 @. LDRH r0,[r0,#0x22] + 0x01001c2a: 2250 P" MOVS r2,#0x50 + 0x01001c2c: 4350 PC MULS r0,r2,r0 + 0x01001c2e: 4aa6 .J LDR r2,[pc,#664] ; [0x1001ec8] = 0x2001c + 0x01001c30: 6812 .h LDR r2,[r2,#0] + 0x01001c32: 3226 &2 ADDS r2,r2,#0x26 + 0x01001c34: 1881 .. ADDS r1,r0,r2 + 0x01001c36: 2250 P" MOVS r2,#0x50 + 0x01001c38: 48a3 .H LDR r0,[pc,#652] ; [0x1001ec8] = 0x2001c + 0x01001c3a: 6800 .h LDR r0,[r0,#0] + 0x01001c3c: 30ff .0 ADDS r0,r0,#0xff + 0x01001c3e: 30b7 .0 ADDS r0,r0,#0xb7 + 0x01001c40: f7fefd7c ..|. BL __aeabi_memcpy ; 0x100073c + 0x01001c44: 48a0 .H LDR r0,[pc,#640] ; [0x1001ec8] = 0x2001c + 0x01001c46: 6800 .h LDR r0,[r0,#0] + 0x01001c48: 30ff .0 ADDS r0,r0,#0xff + 0x01001c4a: 30b7 .0 ADDS r0,r0,#0xb7 + 0x01001c4c: f7fefcf8 .... BL strlen ; 0x1000640 + 0x01001c50: b281 .. UXTH r1,r0 + 0x01001c52: 489d .H LDR r0,[pc,#628] ; [0x1001ec8] = 0x2001c + 0x01001c54: 6800 .h LDR r0,[r0,#0] + 0x01001c56: 30ff .0 ADDS r0,r0,#0xff + 0x01001c58: 30ff .0 ADDS r0,r0,#0xff + 0x01001c5a: 3002 .0 ADDS r0,#2 + 0x01001c5c: 8101 .. STRH r1,[r0,#8] + 0x01001c5e: 489a .H LDR r0,[pc,#616] ; [0x1001ec8] = 0x2001c + 0x01001c60: 6800 .h LDR r0,[r0,#0] + 0x01001c62: 30ff .0 ADDS r0,r0,#0xff + 0x01001c64: 30ff .0 ADDS r0,r0,#0xff + 0x01001c66: 3002 .0 ADDS r0,#2 + 0x01001c68: 8141 A. STRH r1,[r0,#0xa] + 0x01001c6a: 4897 .H LDR r0,[pc,#604] ; [0x1001ec8] = 0x2001c + 0x01001c6c: 6800 .h LDR r0,[r0,#0] + 0x01001c6e: f005f82b ..+. BL shell_handle_history ; 0x1006cc8 + 0x01001c72: e21d .. B 0x10020b0 ; finsh_thread_entry + 1508 + 0x01001c74: 2c44 D, CMP r4,#0x44 + 0x01001c76: d119 .. BNE 0x1001cac ; finsh_thread_entry + 480 + 0x01001c78: 4893 .H LDR r0,[pc,#588] ; [0x1001ec8] = 0x2001c + 0x01001c7a: 6800 .h LDR r0,[r0,#0] + 0x01001c7c: 30ff .0 ADDS r0,r0,#0xff + 0x01001c7e: 30ff .0 ADDS r0,r0,#0xff + 0x01001c80: 3002 .0 ADDS r0,#2 + 0x01001c82: 8940 @. LDRH r0,[r0,#0xa] + 0x01001c84: 2800 .( CMP r0,#0 + 0x01001c86: d010 .. BEQ 0x1001caa ; finsh_thread_entry + 478 + 0x01001c88: a090 .. ADR r0,{pc}+0x244 ; 0x1001ecc + 0x01001c8a: f002fc21 ..!. BL rt_kprintf ; 0x10044d0 + 0x01001c8e: 488e .H LDR r0,[pc,#568] ; [0x1001ec8] = 0x2001c + 0x01001c90: 6800 .h LDR r0,[r0,#0] + 0x01001c92: 30ff .0 ADDS r0,r0,#0xff + 0x01001c94: 30ff .0 ADDS r0,r0,#0xff + 0x01001c96: 3002 .0 ADDS r0,#2 + 0x01001c98: 8940 @. LDRH r0,[r0,#0xa] + 0x01001c9a: 1e40 @. SUBS r0,r0,#1 + 0x01001c9c: b281 .. UXTH r1,r0 + 0x01001c9e: 488a .H LDR r0,[pc,#552] ; [0x1001ec8] = 0x2001c + 0x01001ca0: 6800 .h LDR r0,[r0,#0] + 0x01001ca2: 30ff .0 ADDS r0,r0,#0xff + 0x01001ca4: 30ff .0 ADDS r0,r0,#0xff + 0x01001ca6: 3002 .0 ADDS r0,#2 + 0x01001ca8: 8141 A. STRH r1,[r0,#0xa] + 0x01001caa: e201 .. B 0x10020b0 ; finsh_thread_entry + 1508 + 0x01001cac: 2c43 C, CMP r4,#0x43 + 0x01001cae: d12a *. BNE 0x1001d06 ; finsh_thread_entry + 570 + 0x01001cb0: 4885 .H LDR r0,[pc,#532] ; [0x1001ec8] = 0x2001c + 0x01001cb2: 6800 .h LDR r0,[r0,#0] + 0x01001cb4: 30ff .0 ADDS r0,r0,#0xff + 0x01001cb6: 30ff .0 ADDS r0,r0,#0xff + 0x01001cb8: 3002 .0 ADDS r0,#2 + 0x01001cba: 8941 A. LDRH r1,[r0,#0xa] + 0x01001cbc: 4882 .H LDR r0,[pc,#520] ; [0x1001ec8] = 0x2001c + 0x01001cbe: 6800 .h LDR r0,[r0,#0] + 0x01001cc0: 30ff .0 ADDS r0,r0,#0xff + 0x01001cc2: 30ff .0 ADDS r0,r0,#0xff + 0x01001cc4: 3002 .0 ADDS r0,#2 + 0x01001cc6: 8900 .. LDRH r0,[r0,#8] + 0x01001cc8: 4281 .B CMP r1,r0 + 0x01001cca: da1b .. BGE 0x1001d04 ; finsh_thread_entry + 568 + 0x01001ccc: 487e ~H LDR r0,[pc,#504] ; [0x1001ec8] = 0x2001c + 0x01001cce: 6800 .h LDR r0,[r0,#0] + 0x01001cd0: 30ff .0 ADDS r0,r0,#0xff + 0x01001cd2: 30ff .0 ADDS r0,r0,#0xff + 0x01001cd4: 3002 .0 ADDS r0,#2 + 0x01001cd6: 8942 B. LDRH r2,[r0,#0xa] + 0x01001cd8: 487b {H LDR r0,[pc,#492] ; [0x1001ec8] = 0x2001c + 0x01001cda: 6800 .h LDR r0,[r0,#0] + 0x01001cdc: 30ff .0 ADDS r0,r0,#0xff + 0x01001cde: 30b7 .0 ADDS r0,r0,#0xb7 + 0x01001ce0: 5c81 .\ LDRB r1,[r0,r2] + 0x01001ce2: a07b {. ADR r0,{pc}+0x1ee ; 0x1001ed0 + 0x01001ce4: f002fbf4 .... BL rt_kprintf ; 0x10044d0 + 0x01001ce8: 4877 wH LDR r0,[pc,#476] ; [0x1001ec8] = 0x2001c + 0x01001cea: 6800 .h LDR r0,[r0,#0] + 0x01001cec: 30ff .0 ADDS r0,r0,#0xff + 0x01001cee: 30ff .0 ADDS r0,r0,#0xff + 0x01001cf0: 3002 .0 ADDS r0,#2 + 0x01001cf2: 8940 @. LDRH r0,[r0,#0xa] + 0x01001cf4: 1c40 @. ADDS r0,r0,#1 + 0x01001cf6: b281 .. UXTH r1,r0 + 0x01001cf8: 4873 sH LDR r0,[pc,#460] ; [0x1001ec8] = 0x2001c + 0x01001cfa: 6800 .h LDR r0,[r0,#0] + 0x01001cfc: 30ff .0 ADDS r0,r0,#0xff + 0x01001cfe: 30ff .0 ADDS r0,r0,#0xff + 0x01001d00: 3002 .0 ADDS r0,#2 + 0x01001d02: 8141 A. STRH r1,[r0,#0xa] + 0x01001d04: e1d4 .. B 0x10020b0 ; finsh_thread_entry + 1508 + 0x01001d06: 2c00 ., CMP r4,#0 + 0x01001d08: d001 .. BEQ 0x1001d0e ; finsh_thread_entry + 578 + 0x01001d0a: 2cff ., CMP r4,#0xff + 0x01001d0c: d100 .. BNE 0x1001d10 ; finsh_thread_entry + 580 + 0x01001d0e: e1cf .. B 0x10020b0 ; finsh_thread_entry + 1508 + 0x01001d10: 2c09 ., CMP r4,#9 + 0x01001d12: d127 '. BNE 0x1001d64 ; finsh_thread_entry + 664 + 0x01001d14: 2500 .% MOVS r5,#0 + 0x01001d16: e003 .. B 0x1001d20 ; finsh_thread_entry + 596 + 0x01001d18: a06c l. ADR r0,{pc}+0x1b4 ; 0x1001ecc + 0x01001d1a: f002fbd9 .... BL rt_kprintf ; 0x10044d0 + 0x01001d1e: 1c6d m. ADDS r5,r5,#1 + 0x01001d20: 4869 iH LDR r0,[pc,#420] ; [0x1001ec8] = 0x2001c + 0x01001d22: 6800 .h LDR r0,[r0,#0] + 0x01001d24: 30ff .0 ADDS r0,r0,#0xff + 0x01001d26: 30ff .0 ADDS r0,r0,#0xff + 0x01001d28: 3002 .0 ADDS r0,#2 + 0x01001d2a: 8940 @. LDRH r0,[r0,#0xa] + 0x01001d2c: 42a8 .B CMP r0,r5 + 0x01001d2e: dcf3 .. BGT 0x1001d18 ; finsh_thread_entry + 588 + 0x01001d30: 4865 eH LDR r0,[pc,#404] ; [0x1001ec8] = 0x2001c + 0x01001d32: 6800 .h LDR r0,[r0,#0] + 0x01001d34: 30ff .0 ADDS r0,r0,#0xff + 0x01001d36: 30b7 .0 ADDS r0,r0,#0xb7 + 0x01001d38: f004ffae .... BL shell_auto_complete ; 0x1006c98 + 0x01001d3c: 4862 bH LDR r0,[pc,#392] ; [0x1001ec8] = 0x2001c + 0x01001d3e: 6800 .h LDR r0,[r0,#0] + 0x01001d40: 30ff .0 ADDS r0,r0,#0xff + 0x01001d42: 30b7 .0 ADDS r0,r0,#0xb7 + 0x01001d44: f7fefc7c ..|. BL strlen ; 0x1000640 + 0x01001d48: b281 .. UXTH r1,r0 + 0x01001d4a: 485f _H LDR r0,[pc,#380] ; [0x1001ec8] = 0x2001c + 0x01001d4c: 6800 .h LDR r0,[r0,#0] + 0x01001d4e: 30ff .0 ADDS r0,r0,#0xff + 0x01001d50: 30ff .0 ADDS r0,r0,#0xff + 0x01001d52: 3002 .0 ADDS r0,#2 + 0x01001d54: 8101 .. STRH r1,[r0,#8] + 0x01001d56: 485c \H LDR r0,[pc,#368] ; [0x1001ec8] = 0x2001c + 0x01001d58: 6800 .h LDR r0,[r0,#0] + 0x01001d5a: 30ff .0 ADDS r0,r0,#0xff + 0x01001d5c: 30ff .0 ADDS r0,r0,#0xff + 0x01001d5e: 3002 .0 ADDS r0,#2 + 0x01001d60: 8141 A. STRH r1,[r0,#0xa] + 0x01001d62: e1a5 .. B 0x10020b0 ; finsh_thread_entry + 1508 + 0x01001d64: 2c7f ., CMP r4,#0x7f + 0x01001d66: d001 .. BEQ 0x1001d6c ; finsh_thread_entry + 672 + 0x01001d68: 2c08 ., CMP r4,#8 + 0x01001d6a: d179 y. BNE 0x1001e60 ; finsh_thread_entry + 916 + 0x01001d6c: 4856 VH LDR r0,[pc,#344] ; [0x1001ec8] = 0x2001c + 0x01001d6e: 6800 .h LDR r0,[r0,#0] + 0x01001d70: 30ff .0 ADDS r0,r0,#0xff + 0x01001d72: 30ff .0 ADDS r0,r0,#0xff + 0x01001d74: 3002 .0 ADDS r0,#2 + 0x01001d76: 8940 @. LDRH r0,[r0,#0xa] + 0x01001d78: 2800 .( CMP r0,#0 + 0x01001d7a: d100 .. BNE 0x1001d7e ; finsh_thread_entry + 690 + 0x01001d7c: e198 .. B 0x10020b0 ; finsh_thread_entry + 1508 + 0x01001d7e: 4852 RH LDR r0,[pc,#328] ; [0x1001ec8] = 0x2001c + 0x01001d80: 6800 .h LDR r0,[r0,#0] + 0x01001d82: 30ff .0 ADDS r0,r0,#0xff + 0x01001d84: 30ff .0 ADDS r0,r0,#0xff + 0x01001d86: 3002 .0 ADDS r0,#2 + 0x01001d88: 8900 .. LDRH r0,[r0,#8] + 0x01001d8a: 1e40 @. SUBS r0,r0,#1 + 0x01001d8c: b281 .. UXTH r1,r0 + 0x01001d8e: 484e NH LDR r0,[pc,#312] ; [0x1001ec8] = 0x2001c + 0x01001d90: 6800 .h LDR r0,[r0,#0] + 0x01001d92: 30ff .0 ADDS r0,r0,#0xff + 0x01001d94: 30ff .0 ADDS r0,r0,#0xff + 0x01001d96: 3002 .0 ADDS r0,#2 + 0x01001d98: 8101 .. STRH r1,[r0,#8] + 0x01001d9a: 484b KH LDR r0,[pc,#300] ; [0x1001ec8] = 0x2001c + 0x01001d9c: 6800 .h LDR r0,[r0,#0] + 0x01001d9e: 30ff .0 ADDS r0,r0,#0xff + 0x01001da0: 30ff .0 ADDS r0,r0,#0xff + 0x01001da2: 3002 .0 ADDS r0,#2 + 0x01001da4: 8940 @. LDRH r0,[r0,#0xa] + 0x01001da6: 1e40 @. SUBS r0,r0,#1 + 0x01001da8: b281 .. UXTH r1,r0 + 0x01001daa: 4847 GH LDR r0,[pc,#284] ; [0x1001ec8] = 0x2001c + 0x01001dac: 6800 .h LDR r0,[r0,#0] + 0x01001dae: 30ff .0 ADDS r0,r0,#0xff + 0x01001db0: 30ff .0 ADDS r0,r0,#0xff + 0x01001db2: 3002 .0 ADDS r0,#2 + 0x01001db4: 8141 A. STRH r1,[r0,#0xa] + 0x01001db6: 4844 DH LDR r0,[pc,#272] ; [0x1001ec8] = 0x2001c + 0x01001db8: 6800 .h LDR r0,[r0,#0] + 0x01001dba: 30ff .0 ADDS r0,r0,#0xff + 0x01001dbc: 30ff .0 ADDS r0,r0,#0xff + 0x01001dbe: 3002 .0 ADDS r0,#2 + 0x01001dc0: 8901 .. LDRH r1,[r0,#8] + 0x01001dc2: 4841 AH LDR r0,[pc,#260] ; [0x1001ec8] = 0x2001c + 0x01001dc4: 6800 .h LDR r0,[r0,#0] + 0x01001dc6: 30ff .0 ADDS r0,r0,#0xff + 0x01001dc8: 30ff .0 ADDS r0,r0,#0xff + 0x01001dca: 3002 .0 ADDS r0,#2 + 0x01001dcc: 8940 @. LDRH r0,[r0,#0xa] + 0x01001dce: 4281 .B CMP r1,r0 + 0x01001dd0: dd54 T. BLE 0x1001e7c ; finsh_thread_entry + 944 + 0x01001dd2: 4b3d =K LDR r3,[pc,#244] ; [0x1001ec8] = 0x2001c + 0x01001dd4: 681b .h LDR r3,[r3,#0] + 0x01001dd6: 33ff .3 ADDS r3,r3,#0xff + 0x01001dd8: 33ff .3 ADDS r3,r3,#0xff + 0x01001dda: 3302 .3 ADDS r3,#2 + 0x01001ddc: 891e .. LDRH r6,[r3,#8] + 0x01001dde: 4b3a :K LDR r3,[pc,#232] ; [0x1001ec8] = 0x2001c + 0x01001de0: 681b .h LDR r3,[r3,#0] + 0x01001de2: 33ff .3 ADDS r3,r3,#0xff + 0x01001de4: 33ff .3 ADDS r3,r3,#0xff + 0x01001de6: 3302 .3 ADDS r3,#2 + 0x01001de8: 895b [. LDRH r3,[r3,#0xa] + 0x01001dea: 1af2 .. SUBS r2,r6,r3 + 0x01001dec: 4b36 6K LDR r3,[pc,#216] ; [0x1001ec8] = 0x2001c + 0x01001dee: 681b .h LDR r3,[r3,#0] + 0x01001df0: 33ff .3 ADDS r3,r3,#0xff + 0x01001df2: 33ff .3 ADDS r3,r3,#0xff + 0x01001df4: 3302 .3 ADDS r3,#2 + 0x01001df6: 895b [. LDRH r3,[r3,#0xa] + 0x01001df8: 1c5b [. ADDS r3,r3,#1 + 0x01001dfa: 4e33 3N LDR r6,[pc,#204] ; [0x1001ec8] = 0x2001c + 0x01001dfc: 6836 6h LDR r6,[r6,#0] + 0x01001dfe: 36ff .6 ADDS r6,r6,#0xff + 0x01001e00: 36b7 .6 ADDS r6,r6,#0xb7 + 0x01001e02: 1999 .. ADDS r1,r3,r6 + 0x01001e04: 4b30 0K LDR r3,[pc,#192] ; [0x1001ec8] = 0x2001c + 0x01001e06: 681b .h LDR r3,[r3,#0] + 0x01001e08: 33ff .3 ADDS r3,r3,#0xff + 0x01001e0a: 33ff .3 ADDS r3,r3,#0xff + 0x01001e0c: 3302 .3 ADDS r3,#2 + 0x01001e0e: 895e ^. LDRH r6,[r3,#0xa] + 0x01001e10: 4b2d -K LDR r3,[pc,#180] ; [0x1001ec8] = 0x2001c + 0x01001e12: 681b .h LDR r3,[r3,#0] + 0x01001e14: 33ff .3 ADDS r3,r3,#0xff + 0x01001e16: 33b7 .3 ADDS r3,r3,#0xb7 + 0x01001e18: 18f0 .. ADDS r0,r6,r3 + 0x01001e1a: f002fe31 ..1. BL rt_memmove ; 0x1004a80 + 0x01001e1e: 2100 .! MOVS r1,#0 + 0x01001e20: 4829 )H LDR r0,[pc,#164] ; [0x1001ec8] = 0x2001c + 0x01001e22: 6800 .h LDR r0,[r0,#0] + 0x01001e24: 30ff .0 ADDS r0,r0,#0xff + 0x01001e26: 30ff .0 ADDS r0,r0,#0xff + 0x01001e28: 3002 .0 ADDS r0,#2 + 0x01001e2a: 8902 .. LDRH r2,[r0,#8] + 0x01001e2c: 4826 &H LDR r0,[pc,#152] ; [0x1001ec8] = 0x2001c + 0x01001e2e: 6800 .h LDR r0,[r0,#0] + 0x01001e30: 30ff .0 ADDS r0,r0,#0xff + 0x01001e32: 30b7 .0 ADDS r0,r0,#0xb7 + 0x01001e34: 5481 .T STRB r1,[r0,r2] + 0x01001e36: 4824 $H LDR r0,[pc,#144] ; [0x1001ec8] = 0x2001c + 0x01001e38: 6800 .h LDR r0,[r0,#0] + 0x01001e3a: 30ff .0 ADDS r0,r0,#0xff + 0x01001e3c: 30ff .0 ADDS r0,r0,#0xff + 0x01001e3e: 3002 .0 ADDS r0,#2 + 0x01001e40: 8942 B. LDRH r2,[r0,#0xa] + 0x01001e42: 4821 !H LDR r0,[pc,#132] ; [0x1001ec8] = 0x2001c + 0x01001e44: 6800 .h LDR r0,[r0,#0] + 0x01001e46: 30ff .0 ADDS r0,r0,#0xff + 0x01001e48: 30b7 .0 ADDS r0,r0,#0xb7 + 0x01001e4a: 1811 .. ADDS r1,r2,r0 + 0x01001e4c: a021 !. ADR r0,{pc}+0x88 ; 0x1001ed4 + 0x01001e4e: f002fb3f ..?. BL rt_kprintf ; 0x10044d0 + 0x01001e52: 481d .H LDR r0,[pc,#116] ; [0x1001ec8] = 0x2001c + 0x01001e54: 6800 .h LDR r0,[r0,#0] + 0x01001e56: 30ff .0 ADDS r0,r0,#0xff + 0x01001e58: 30ff .0 ADDS r0,r0,#0xff + 0x01001e5a: 3002 .0 ADDS r0,#2 + 0x01001e5c: 8945 E. LDRH r5,[r0,#0xa] + 0x01001e5e: e004 .. B 0x1001e6a ; finsh_thread_entry + 926 + 0x01001e60: e01c .. B 0x1001e9c ; finsh_thread_entry + 976 + 0x01001e62: a01a .. ADR r0,{pc}+0x6a ; 0x1001ecc + 0x01001e64: f002fb34 ..4. BL rt_kprintf ; 0x10044d0 + 0x01001e68: 1c6d m. ADDS r5,r5,#1 + 0x01001e6a: 4817 .H LDR r0,[pc,#92] ; [0x1001ec8] = 0x2001c + 0x01001e6c: 6800 .h LDR r0,[r0,#0] + 0x01001e6e: 30ff .0 ADDS r0,r0,#0xff + 0x01001e70: 30ff .0 ADDS r0,r0,#0xff + 0x01001e72: 3002 .0 ADDS r0,#2 + 0x01001e74: 8900 .. LDRH r0,[r0,#8] + 0x01001e76: 42a8 .B CMP r0,r5 + 0x01001e78: daf3 .. BGE 0x1001e62 ; finsh_thread_entry + 918 + 0x01001e7a: e00e .. B 0x1001e9a ; finsh_thread_entry + 974 + 0x01001e7c: a017 .. ADR r0,{pc}+0x60 ; 0x1001edc + 0x01001e7e: f002fb27 ..'. BL rt_kprintf ; 0x10044d0 + 0x01001e82: 2100 .! MOVS r1,#0 + 0x01001e84: 4810 .H LDR r0,[pc,#64] ; [0x1001ec8] = 0x2001c + 0x01001e86: 6800 .h LDR r0,[r0,#0] + 0x01001e88: 30ff .0 ADDS r0,r0,#0xff + 0x01001e8a: 30ff .0 ADDS r0,r0,#0xff + 0x01001e8c: 3002 .0 ADDS r0,#2 + 0x01001e8e: 8902 .. LDRH r2,[r0,#8] + 0x01001e90: 480d .H LDR r0,[pc,#52] ; [0x1001ec8] = 0x2001c + 0x01001e92: 6800 .h LDR r0,[r0,#0] + 0x01001e94: 30ff .0 ADDS r0,r0,#0xff + 0x01001e96: 30b7 .0 ADDS r0,r0,#0xb7 + 0x01001e98: 5481 .T STRB r1,[r0,r2] + 0x01001e9a: e109 .. B 0x10020b0 ; finsh_thread_entry + 1508 + 0x01001e9c: 2c0d ., CMP r4,#0xd + 0x01001e9e: d001 .. BEQ 0x1001ea4 ; finsh_thread_entry + 984 + 0x01001ea0: 2c0a ., CMP r4,#0xa + 0x01001ea2: d143 C. BNE 0x1001f2c ; finsh_thread_entry + 1120 + 0x01001ea4: 4808 .H LDR r0,[pc,#32] ; [0x1001ec8] = 0x2001c + 0x01001ea6: 6800 .h LDR r0,[r0,#0] + 0x01001ea8: f004ff28 ..(. BL shell_push_history ; 0x1006cfc + 0x01001eac: 4806 .H LDR r0,[pc,#24] ; [0x1001ec8] = 0x2001c + 0x01001eae: 6800 .h LDR r0,[r0,#0] + 0x01001eb0: 3020 0 ADDS r0,r0,#0x20 + 0x01001eb2: 7840 @x LDRB r0,[r0,#1] + 0x01001eb4: 07c0 .. LSLS r0,r0,#31 + 0x01001eb6: 0fc0 .. LSRS r0,r0,#31 + 0x01001eb8: 2800 .( CMP r0,#0 + 0x01001eba: d002 .. BEQ 0x1001ec2 ; finsh_thread_entry + 1014 + 0x01001ebc: a008 .. ADR r0,{pc}+0x24 ; 0x1001ee0 + 0x01001ebe: f002fb07 .... BL rt_kprintf ; 0x10044d0 + 0x01001ec2: 4801 .H LDR r0,[pc,#4] ; [0x1001ec8] = 0x2001c + 0x01001ec4: 6800 .h LDR r0,[r0,#0] + 0x01001ec6: e00d .. B 0x1001ee4 ; finsh_thread_entry + 1048 + $d + 0x01001ec8: 0002001c .... DCD 131100 + 0x01001ecc: 00000008 .... DCD 8 + 0x01001ed0: 00006325 %c.. DCD 25381 + 0x01001ed4: 20732508 .%s DCD 544417032 + 0x01001ed8: 00000820 ... DCD 2080 + 0x01001edc: 00082008 . .. DCD 532488 + 0x01001ee0: 0000000a .... DCD 10 + $t + 0x01001ee4: 30ff .0 ADDS r0,r0,#0xff + 0x01001ee6: 30ff .0 ADDS r0,r0,#0xff + 0x01001ee8: 3002 .0 ADDS r0,#2 + 0x01001eea: 8901 .. LDRH r1,[r0,#8] + 0x01001eec: 4871 qH LDR r0,[pc,#452] ; [0x10020b4] = 0x2001c + 0x01001eee: 6800 .h LDR r0,[r0,#0] + 0x01001ef0: 30ff .0 ADDS r0,r0,#0xff + 0x01001ef2: 30b7 .0 ADDS r0,r0,#0xb7 + 0x01001ef4: f001f8f2 .... BL msh_exec ; 0x10030dc + 0x01001ef8: f7fffc62 ..b. BL finsh_get_prompt ; 0x10017c0 + 0x01001efc: 4605 .F MOV r5,r0 + 0x01001efe: f002fae7 .... BL rt_kprintf ; 0x10044d0 + 0x01001f02: 2151 Q! MOVS r1,#0x51 + 0x01001f04: 486b kH LDR r0,[pc,#428] ; [0x10020b4] = 0x2001c + 0x01001f06: 6800 .h LDR r0,[r0,#0] + 0x01001f08: 30ff .0 ADDS r0,r0,#0xff + 0x01001f0a: 30b7 .0 ADDS r0,r0,#0xb7 + 0x01001f0c: f7fefc73 ..s. BL __aeabi_memclr ; 0x10007f6 + 0x01001f10: 2100 .! MOVS r1,#0 + 0x01001f12: 4868 hH LDR r0,[pc,#416] ; [0x10020b4] = 0x2001c + 0x01001f14: 6800 .h LDR r0,[r0,#0] + 0x01001f16: 30ff .0 ADDS r0,r0,#0xff + 0x01001f18: 30ff .0 ADDS r0,r0,#0xff + 0x01001f1a: 3002 .0 ADDS r0,#2 + 0x01001f1c: 8101 .. STRH r1,[r0,#8] + 0x01001f1e: 4865 eH LDR r0,[pc,#404] ; [0x10020b4] = 0x2001c + 0x01001f20: 6800 .h LDR r0,[r0,#0] + 0x01001f22: 30ff .0 ADDS r0,r0,#0xff + 0x01001f24: 30ff .0 ADDS r0,r0,#0xff + 0x01001f26: 3002 .0 ADDS r0,#2 + 0x01001f28: 8141 A. STRH r1,[r0,#0xa] + 0x01001f2a: e0c1 .. B 0x10020b0 ; finsh_thread_entry + 1508 + 0x01001f2c: 4861 aH LDR r0,[pc,#388] ; [0x10020b4] = 0x2001c + 0x01001f2e: 6800 .h LDR r0,[r0,#0] + 0x01001f30: 30ff .0 ADDS r0,r0,#0xff + 0x01001f32: 30ff .0 ADDS r0,r0,#0xff + 0x01001f34: 3002 .0 ADDS r0,#2 + 0x01001f36: 8900 .. LDRH r0,[r0,#8] + 0x01001f38: 2850 P( CMP r0,#0x50 + 0x01001f3a: db06 .. BLT 0x1001f4a ; finsh_thread_entry + 1150 + 0x01001f3c: 2100 .! MOVS r1,#0 + 0x01001f3e: 485d ]H LDR r0,[pc,#372] ; [0x10020b4] = 0x2001c + 0x01001f40: 6800 .h LDR r0,[r0,#0] + 0x01001f42: 30ff .0 ADDS r0,r0,#0xff + 0x01001f44: 30ff .0 ADDS r0,r0,#0xff + 0x01001f46: 3002 .0 ADDS r0,#2 + 0x01001f48: 8101 .. STRH r1,[r0,#8] + 0x01001f4a: 485a ZH LDR r0,[pc,#360] ; [0x10020b4] = 0x2001c + 0x01001f4c: 6800 .h LDR r0,[r0,#0] + 0x01001f4e: 30ff .0 ADDS r0,r0,#0xff + 0x01001f50: 30ff .0 ADDS r0,r0,#0xff + 0x01001f52: 3002 .0 ADDS r0,#2 + 0x01001f54: 8941 A. LDRH r1,[r0,#0xa] + 0x01001f56: 4857 WH LDR r0,[pc,#348] ; [0x10020b4] = 0x2001c + 0x01001f58: 6800 .h LDR r0,[r0,#0] + 0x01001f5a: 30ff .0 ADDS r0,r0,#0xff + 0x01001f5c: 30ff .0 ADDS r0,r0,#0xff + 0x01001f5e: 3002 .0 ADDS r0,#2 + 0x01001f60: 8900 .. LDRH r0,[r0,#8] + 0x01001f62: 4281 .B CMP r1,r0 + 0x01001f64: da5a Z. BGE 0x100201c ; finsh_thread_entry + 1360 + 0x01001f66: 4b53 SK LDR r3,[pc,#332] ; [0x10020b4] = 0x2001c + 0x01001f68: 681b .h LDR r3,[r3,#0] + 0x01001f6a: 33ff .3 ADDS r3,r3,#0xff + 0x01001f6c: 33ff .3 ADDS r3,r3,#0xff + 0x01001f6e: 3302 .3 ADDS r3,#2 + 0x01001f70: 891e .. LDRH r6,[r3,#8] + 0x01001f72: 4b50 PK LDR r3,[pc,#320] ; [0x10020b4] = 0x2001c + 0x01001f74: 681b .h LDR r3,[r3,#0] + 0x01001f76: 33ff .3 ADDS r3,r3,#0xff + 0x01001f78: 33ff .3 ADDS r3,r3,#0xff + 0x01001f7a: 3302 .3 ADDS r3,#2 + 0x01001f7c: 895b [. LDRH r3,[r3,#0xa] + 0x01001f7e: 1af2 .. SUBS r2,r6,r3 + 0x01001f80: 4b4c LK LDR r3,[pc,#304] ; [0x10020b4] = 0x2001c + 0x01001f82: 681b .h LDR r3,[r3,#0] + 0x01001f84: 33ff .3 ADDS r3,r3,#0xff + 0x01001f86: 33ff .3 ADDS r3,r3,#0xff + 0x01001f88: 3302 .3 ADDS r3,#2 + 0x01001f8a: 895e ^. LDRH r6,[r3,#0xa] + 0x01001f8c: 4b49 IK LDR r3,[pc,#292] ; [0x10020b4] = 0x2001c + 0x01001f8e: 681b .h LDR r3,[r3,#0] + 0x01001f90: 33ff .3 ADDS r3,r3,#0xff + 0x01001f92: 33b7 .3 ADDS r3,r3,#0xb7 + 0x01001f94: 18f1 .. ADDS r1,r6,r3 + 0x01001f96: 4b47 GK LDR r3,[pc,#284] ; [0x10020b4] = 0x2001c + 0x01001f98: 681b .h LDR r3,[r3,#0] + 0x01001f9a: 33ff .3 ADDS r3,r3,#0xff + 0x01001f9c: 33ff .3 ADDS r3,r3,#0xff + 0x01001f9e: 3302 .3 ADDS r3,#2 + 0x01001fa0: 895b [. LDRH r3,[r3,#0xa] + 0x01001fa2: 1c5b [. ADDS r3,r3,#1 + 0x01001fa4: 4e43 CN LDR r6,[pc,#268] ; [0x10020b4] = 0x2001c + 0x01001fa6: 6836 6h LDR r6,[r6,#0] + 0x01001fa8: 36ff .6 ADDS r6,r6,#0xff + 0x01001faa: 36b7 .6 ADDS r6,r6,#0xb7 + 0x01001fac: 1998 .. ADDS r0,r3,r6 + 0x01001fae: f002fd67 ..g. BL rt_memmove ; 0x1004a80 + 0x01001fb2: 4840 @H LDR r0,[pc,#256] ; [0x10020b4] = 0x2001c + 0x01001fb4: 6800 .h LDR r0,[r0,#0] + 0x01001fb6: 30ff .0 ADDS r0,r0,#0xff + 0x01001fb8: 30ff .0 ADDS r0,r0,#0xff + 0x01001fba: 3002 .0 ADDS r0,#2 + 0x01001fbc: 8942 B. LDRH r2,[r0,#0xa] + 0x01001fbe: 483d =H LDR r0,[pc,#244] ; [0x10020b4] = 0x2001c + 0x01001fc0: 6800 .h LDR r0,[r0,#0] + 0x01001fc2: 30ff .0 ADDS r0,r0,#0xff + 0x01001fc4: 30b7 .0 ADDS r0,r0,#0xb7 + 0x01001fc6: 5484 .T STRB r4,[r0,r2] + 0x01001fc8: 483a :H LDR r0,[pc,#232] ; [0x10020b4] = 0x2001c + 0x01001fca: 6800 .h LDR r0,[r0,#0] + 0x01001fcc: 3020 0 ADDS r0,r0,#0x20 + 0x01001fce: 7840 @x LDRB r0,[r0,#1] + 0x01001fd0: 07c0 .. LSLS r0,r0,#31 + 0x01001fd2: 0fc0 .. LSRS r0,r0,#31 + 0x01001fd4: 2800 .( CMP r0,#0 + 0x01001fd6: d00d .. BEQ 0x1001ff4 ; finsh_thread_entry + 1320 + 0x01001fd8: 4836 6H LDR r0,[pc,#216] ; [0x10020b4] = 0x2001c + 0x01001fda: 6800 .h LDR r0,[r0,#0] + 0x01001fdc: 30ff .0 ADDS r0,r0,#0xff + 0x01001fde: 30ff .0 ADDS r0,r0,#0xff + 0x01001fe0: 3002 .0 ADDS r0,#2 + 0x01001fe2: 8942 B. LDRH r2,[r0,#0xa] + 0x01001fe4: 4833 3H LDR r0,[pc,#204] ; [0x10020b4] = 0x2001c + 0x01001fe6: 6800 .h LDR r0,[r0,#0] + 0x01001fe8: 30ff .0 ADDS r0,r0,#0xff + 0x01001fea: 30b7 .0 ADDS r0,r0,#0xb7 + 0x01001fec: 1811 .. ADDS r1,r2,r0 + 0x01001fee: a032 2. ADR r0,{pc}+0xca ; 0x10020b8 + 0x01001ff0: f002fa6e ..n. BL rt_kprintf ; 0x10044d0 + 0x01001ff4: 482f /H LDR r0,[pc,#188] ; [0x10020b4] = 0x2001c + 0x01001ff6: 6800 .h LDR r0,[r0,#0] + 0x01001ff8: 30ff .0 ADDS r0,r0,#0xff + 0x01001ffa: 30ff .0 ADDS r0,r0,#0xff + 0x01001ffc: 3002 .0 ADDS r0,#2 + 0x01001ffe: 8945 E. LDRH r5,[r0,#0xa] + 0x01002000: e003 .. B 0x100200a ; finsh_thread_entry + 1342 + 0x01002002: a02e .. ADR r0,{pc}+0xba ; 0x10020bc + 0x01002004: f002fa64 ..d. BL rt_kprintf ; 0x10044d0 + 0x01002008: 1c6d m. ADDS r5,r5,#1 + 0x0100200a: 482a *H LDR r0,[pc,#168] ; [0x10020b4] = 0x2001c + 0x0100200c: 6800 .h LDR r0,[r0,#0] + 0x0100200e: 30ff .0 ADDS r0,r0,#0xff + 0x01002010: 30ff .0 ADDS r0,r0,#0xff + 0x01002012: 3002 .0 ADDS r0,#2 + 0x01002014: 8900 .. LDRH r0,[r0,#8] + 0x01002016: 42a8 .B CMP r0,r5 + 0x01002018: dcf3 .. BGT 0x1002002 ; finsh_thread_entry + 1334 + 0x0100201a: e016 .. B 0x100204a ; finsh_thread_entry + 1406 + 0x0100201c: 4825 %H LDR r0,[pc,#148] ; [0x10020b4] = 0x2001c + 0x0100201e: 6800 .h LDR r0,[r0,#0] + 0x01002020: 30ff .0 ADDS r0,r0,#0xff + 0x01002022: 30ff .0 ADDS r0,r0,#0xff + 0x01002024: 3002 .0 ADDS r0,#2 + 0x01002026: 8902 .. LDRH r2,[r0,#8] + 0x01002028: 4822 "H LDR r0,[pc,#136] ; [0x10020b4] = 0x2001c + 0x0100202a: 6800 .h LDR r0,[r0,#0] + 0x0100202c: 30ff .0 ADDS r0,r0,#0xff + 0x0100202e: 30b7 .0 ADDS r0,r0,#0xb7 + 0x01002030: 5484 .T STRB r4,[r0,r2] + 0x01002032: 4820 H LDR r0,[pc,#128] ; [0x10020b4] = 0x2001c + 0x01002034: 6800 .h LDR r0,[r0,#0] + 0x01002036: 3020 0 ADDS r0,r0,#0x20 + 0x01002038: 7840 @x LDRB r0,[r0,#1] + 0x0100203a: 07c0 .. LSLS r0,r0,#31 + 0x0100203c: 0fc0 .. LSRS r0,r0,#31 + 0x0100203e: 2800 .( CMP r0,#0 + 0x01002040: d003 .. BEQ 0x100204a ; finsh_thread_entry + 1406 + 0x01002042: 4621 !F MOV r1,r4 + 0x01002044: a01e .. ADR r0,{pc}+0x7c ; 0x10020c0 + 0x01002046: f002fa43 ..C. BL rt_kprintf ; 0x10044d0 + 0x0100204a: 2400 .$ MOVS r4,#0 + 0x0100204c: 4819 .H LDR r0,[pc,#100] ; [0x10020b4] = 0x2001c + 0x0100204e: 6800 .h LDR r0,[r0,#0] + 0x01002050: 30ff .0 ADDS r0,r0,#0xff + 0x01002052: 30ff .0 ADDS r0,r0,#0xff + 0x01002054: 3002 .0 ADDS r0,#2 + 0x01002056: 8900 .. LDRH r0,[r0,#8] + 0x01002058: 1c40 @. ADDS r0,r0,#1 + 0x0100205a: b281 .. UXTH r1,r0 + 0x0100205c: 4815 .H LDR r0,[pc,#84] ; [0x10020b4] = 0x2001c + 0x0100205e: 6800 .h LDR r0,[r0,#0] + 0x01002060: 30ff .0 ADDS r0,r0,#0xff + 0x01002062: 30ff .0 ADDS r0,r0,#0xff + 0x01002064: 3002 .0 ADDS r0,#2 + 0x01002066: 8101 .. STRH r1,[r0,#8] + 0x01002068: 4812 .H LDR r0,[pc,#72] ; [0x10020b4] = 0x2001c + 0x0100206a: 6800 .h LDR r0,[r0,#0] + 0x0100206c: 30ff .0 ADDS r0,r0,#0xff + 0x0100206e: 30ff .0 ADDS r0,r0,#0xff + 0x01002070: 3002 .0 ADDS r0,#2 + 0x01002072: 8940 @. LDRH r0,[r0,#0xa] + 0x01002074: 1c40 @. ADDS r0,r0,#1 + 0x01002076: b281 .. UXTH r1,r0 + 0x01002078: 480e .H LDR r0,[pc,#56] ; [0x10020b4] = 0x2001c + 0x0100207a: 6800 .h LDR r0,[r0,#0] + 0x0100207c: 30ff .0 ADDS r0,r0,#0xff + 0x0100207e: 30ff .0 ADDS r0,r0,#0xff + 0x01002080: 3002 .0 ADDS r0,#2 + 0x01002082: 8141 A. STRH r1,[r0,#0xa] + 0x01002084: 480b .H LDR r0,[pc,#44] ; [0x10020b4] = 0x2001c + 0x01002086: 6800 .h LDR r0,[r0,#0] + 0x01002088: 30ff .0 ADDS r0,r0,#0xff + 0x0100208a: 30ff .0 ADDS r0,r0,#0xff + 0x0100208c: 3002 .0 ADDS r0,#2 + 0x0100208e: 8900 .. LDRH r0,[r0,#8] + 0x01002090: 2850 P( CMP r0,#0x50 + 0x01002092: db0c .. BLT 0x10020ae ; finsh_thread_entry + 1506 + 0x01002094: 2100 .! MOVS r1,#0 + 0x01002096: 4807 .H LDR r0,[pc,#28] ; [0x10020b4] = 0x2001c + 0x01002098: 6800 .h LDR r0,[r0,#0] + 0x0100209a: 30ff .0 ADDS r0,r0,#0xff + 0x0100209c: 30ff .0 ADDS r0,r0,#0xff + 0x0100209e: 3002 .0 ADDS r0,#2 + 0x010020a0: 8101 .. STRH r1,[r0,#8] + 0x010020a2: 4804 .H LDR r0,[pc,#16] ; [0x10020b4] = 0x2001c + 0x010020a4: 6800 .h LDR r0,[r0,#0] + 0x010020a6: 30ff .0 ADDS r0,r0,#0xff + 0x010020a8: 30ff .0 ADDS r0,r0,#0xff + 0x010020aa: 3002 .0 ADDS r0,#2 + 0x010020ac: 8141 A. STRH r1,[r0,#0xa] + 0x010020ae: bf00 .. NOP + 0x010020b0: e52e .. B 0x1001b10 ; finsh_thread_entry + 68 + $d + 0x010020b2: 0000 .. DCW 0 + 0x010020b4: 0002001c .... DCD 131100 + 0x010020b8: 00007325 %s.. DCD 29477 + 0x010020bc: 00000008 .... DCD 8 + 0x010020c0: 00006325 %c.. DCD 25381 + $t + i.hello + hello + 0x010020c4: b510 .. PUSH {r4,lr} + 0x010020c6: a002 .. ADR r0,{pc}+0xa ; 0x10020d0 + 0x010020c8: f002fa02 .... BL rt_kprintf ; 0x10044d0 + 0x010020cc: 2000 . MOVS r0,#0 + 0x010020ce: bd10 .. POP {r4,pc} + $d + 0x010020d0: 6c6c6548 Hell DCD 1819043144 + 0x010020d4: 5452206f o RT DCD 1414668399 + 0x010020d8: 7268542d -Thr DCD 1919439917 + 0x010020dc: 21646165 ead! DCD 560226661 + 0x010020e0: 0000000a .... DCD 10 + $t + i.list + list + 0x010020e4: b510 .. PUSH {r4,lr} + 0x010020e6: a00d .. ADR r0,{pc}+0x36 ; 0x100211c + 0x010020e8: f002f9f2 .... BL rt_kprintf ; 0x10044d0 + 0x010020ec: 4810 .H LDR r0,[pc,#64] ; [0x1002130] = 0x20014 + 0x010020ee: 6804 .h LDR r4,[r0,#0] + 0x010020f0: e00e .. B 0x1002110 ; list + 44 + 0x010020f2: 2202 ." MOVS r2,#2 + 0x010020f4: a10f .. ADR r1,{pc}+0x40 ; 0x1002134 + 0x010020f6: 6820 h LDR r0,[r4,#0] + 0x010020f8: f7fefac4 .... BL strncmp ; 0x1000684 + 0x010020fc: 2800 .( CMP r0,#0 + 0x010020fe: d100 .. BNE 0x1002102 ; list + 30 + 0x01002100: e005 .. B 0x100210e ; list + 42 + 0x01002102: a00d .. ADR r0,{pc}+0x36 ; 0x1002138 + 0x01002104: 6862 bh LDR r2,[r4,#4] + 0x01002106: 6821 !h LDR r1,[r4,#0] + 0x01002108: f002f9e2 .... BL rt_kprintf ; 0x10044d0 + 0x0100210c: bf00 .. NOP + 0x0100210e: 340c .4 ADDS r4,r4,#0xc + 0x01002110: 480d .H LDR r0,[pc,#52] ; [0x1002148] = 0x20018 + 0x01002112: 6800 .h LDR r0,[r0,#0] + 0x01002114: 4284 .B CMP r4,r0 + 0x01002116: d3ec .. BCC 0x10020f2 ; list + 14 + 0x01002118: 2000 . MOVS r0,#0 + 0x0100211a: bd10 .. POP {r4,pc} + $d + 0x0100211c: 6f432d2d --Co DCD 1866673453 + 0x01002120: 6e616d6d mman DCD 1851878765 + 0x01002124: 4c207364 ds L DCD 1277195108 + 0x01002128: 3a747369 ist: DCD 980710249 + 0x0100212c: 0000000a .... DCD 10 + 0x01002130: 00020014 .... DCD 131092 + 0x01002134: 00005f5f __.. DCD 24415 + 0x01002138: 36312d25 %-16 DCD 909192485 + 0x0100213c: 2d2d2073 s -- DCD 757932147 + 0x01002140: 0a732520 %s. DCD 175318304 + 0x01002144: 00000000 .... DCD 0 + 0x01002148: 00020018 .... DCD 131096 + $t + i.list_device + list_device + 0x0100214c: b5f0 .. PUSH {r4-r7,lr} + 0x0100214e: b093 .. SUB sp,sp,#0x4c + 0x01002150: 2700 .' MOVS r7,#0 + 0x01002152: a028 (. ADR r0,{pc}+0xa2 ; 0x10021f4 + 0x01002154: 9003 .. STR r0,[sp,#0xc] + 0x01002156: 2308 .# MOVS r3,#8 + 0x01002158: aa05 .. ADD r2,sp,#0x14 + 0x0100215a: 2109 .! MOVS r1,#9 + 0x0100215c: a80d .. ADD r0,sp,#0x34 + 0x0100215e: f000f921 ..!. BL list_find_init ; 0x10023a4 + 0x01002162: 2008 . MOVS r0,#8 + 0x01002164: 9004 .. STR r0,[sp,#0x10] + 0x01002166: a025 %. ADR r0,{pc}+0x96 ; 0x10021fc + 0x01002168: 9a03 .. LDR r2,[sp,#0xc] + 0x0100216a: 9904 .. LDR r1,[sp,#0x10] + 0x0100216c: f002f9b0 .... BL rt_kprintf ; 0x10044d0 + 0x01002170: 9804 .. LDR r0,[sp,#0x10] + 0x01002172: f001f8bb .... BL object_split ; 0x10032ec + 0x01002176: a02b +. ADR r0,{pc}+0xae ; 0x1002224 + 0x01002178: f002f9aa .... BL rt_kprintf ; 0x10044d0 + 0x0100217c: bf00 .. NOP + 0x0100217e: a90d .. ADD r1,sp,#0x34 + 0x01002180: 4638 8F MOV r0,r7 + 0x01002182: f000f923 ..#. BL list_get_next ; 0x10023cc + 0x01002186: 4607 .F MOV r7,r0 + 0x01002188: 2600 .& MOVS r6,#0 + 0x0100218a: e02b +. B 0x10021e4 ; list_device + 152 + 0x0100218c: 00b0 .. LSLS r0,r6,#2 + 0x0100218e: a905 .. ADD r1,sp,#0x14 + 0x01002190: 5808 .X LDR r0,[r1,r0] + 0x01002192: 4605 .F MOV r5,r0 + 0x01002194: 3d0c .= SUBS r5,r5,#0xc + 0x01002196: f7fef993 .... BL rt_hw_interrupt_disable ; 0x10004c0 + 0x0100219a: 9012 .. STR r0,[sp,#0x48] + 0x0100219c: 7a28 (z LDRB r0,[r5,#8] + 0x0100219e: 2180 .! MOVS r1,#0x80 + 0x010021a0: 4388 .C BICS r0,r0,r1 + 0x010021a2: a908 .. ADD r1,sp,#0x20 + 0x010021a4: 7f09 .. LDRB r1,[r1,#0x1c] + 0x010021a6: 4288 .B CMP r0,r1 + 0x010021a8: d003 .. BEQ 0x10021b2 ; list_device + 102 + 0x010021aa: 9812 .. LDR r0,[sp,#0x48] + 0x010021ac: f7fef98c .... BL rt_hw_interrupt_enable ; 0x10004c8 + 0x010021b0: e017 .. B 0x10021e2 ; list_device + 150 + 0x010021b2: 9812 .. LDR r0,[sp,#0x48] + 0x010021b4: f7fef988 .... BL rt_hw_interrupt_enable ; 0x10004c8 + 0x010021b8: 462c ,F MOV r4,r5 + 0x010021ba: 7ea1 .~ LDRB r1,[r4,#0x1a] + 0x010021bc: 7d20 } LDRB r0,[r4,#0x14] + 0x010021be: 2818 .( CMP r0,#0x18 + 0x010021c0: dc04 .. BGT 0x10021cc ; list_device + 128 + 0x010021c2: 7d20 } LDRB r0,[r4,#0x14] + 0x010021c4: 0080 .. LSLS r0,r0,#2 + 0x010021c6: 4a20 J LDR r2,[pc,#128] ; [0x1002248] = 0x1007520 + 0x010021c8: 5810 .X LDR r0,[r2,r0] + 0x010021ca: e001 .. B 0x10021d0 ; list_device + 132 + 0x010021cc: 481e .H LDR r0,[pc,#120] ; [0x1002248] = 0x1007520 + 0x010021ce: 6e00 .n LDR r0,[r0,#0x60] + 0x010021d0: 4623 #F MOV r3,r4 + 0x010021d2: 2208 ." MOVS r2,#8 + 0x010021d4: 9101 .. STR r1,[sp,#4] + 0x010021d6: 9000 .. STR r0,[sp,#0] + 0x010021d8: a01c .. ADR r0,{pc}+0x74 ; 0x100224c + 0x010021da: 9904 .. LDR r1,[sp,#0x10] + 0x010021dc: f002f978 ..x. BL rt_kprintf ; 0x10044d0 + 0x010021e0: bf00 .. NOP + 0x010021e2: 1c76 v. ADDS r6,r6,#1 + 0x010021e4: 9811 .. LDR r0,[sp,#0x44] + 0x010021e6: 42b0 .B CMP r0,r6 + 0x010021e8: dcd0 .. BGT 0x100218c ; list_device + 64 + 0x010021ea: 2f00 ./ CMP r7,#0 + 0x010021ec: d1c7 .. BNE 0x100217e ; list_device + 50 + 0x010021ee: 2000 . MOVS r0,#0 + 0x010021f0: b013 .. ADD sp,sp,#0x4c + 0x010021f2: bdf0 .. POP {r4-r7,pc} + $d + 0x010021f4: 69766564 devi DCD 1769366884 + 0x010021f8: 00006563 ce.. DCD 25955 + 0x010021fc: 2e2a2d25 %-*. DCD 774516005 + 0x01002200: 20202073 s DCD 538976371 + 0x01002204: 20202020 DCD 538976288 + 0x01002208: 79742020 ty DCD 2037653536 + 0x0100220c: 20206570 pe DCD 538994032 + 0x01002210: 20202020 DCD 538976288 + 0x01002214: 72202020 r DCD 1914708000 + 0x01002218: 63206665 ef c DCD 1663067749 + 0x0100221c: 746e756f ount DCD 1953396079 + 0x01002220: 0000000a .... DCD 10 + 0x01002224: 2d2d2d20 --- DCD 757935392 + 0x01002228: 2d2d2d2d ---- DCD 757935405 + 0x0100222c: 2d2d2d2d ---- DCD 757935405 + 0x01002230: 2d2d2d2d ---- DCD 757935405 + 0x01002234: 2d2d2d2d ---- DCD 757935405 + 0x01002238: 2d2d202d - -- DCD 757932077 + 0x0100223c: 2d2d2d2d ---- DCD 757935405 + 0x01002240: 2d2d2d2d ---- DCD 757935405 + 0x01002244: 0000000a .... DCD 10 + 0x01002248: 01007520 u.. DCD 16807200 + 0x0100224c: 2e2a2d25 %-*. DCD 774516005 + 0x01002250: 2520732a *s % DCD 622883626 + 0x01002254: 7330322d -20s DCD 1932538413 + 0x01002258: 382d2520 %-8 DCD 942482720 + 0x0100225c: 00000a64 d... DCD 2660 + $t + i.list_event + list_event + 0x01002260: b5f0 .. PUSH {r4-r7,lr} + 0x01002262: b093 .. SUB sp,sp,#0x4c + 0x01002264: 2700 .' MOVS r7,#0 + 0x01002266: a031 1. ADR r0,{pc}+0xc6 ; 0x100232c + 0x01002268: 9003 .. STR r0,[sp,#0xc] + 0x0100226a: 2308 .# MOVS r3,#8 + 0x0100226c: aa05 .. ADD r2,sp,#0x14 + 0x0100226e: 2104 .! MOVS r1,#4 + 0x01002270: a80d .. ADD r0,sp,#0x34 + 0x01002272: f000f897 .... BL list_find_init ; 0x10023a4 + 0x01002276: 2008 . MOVS r0,#8 + 0x01002278: 9004 .. STR r0,[sp,#0x10] + 0x0100227a: a02e .. ADR r0,{pc}+0xba ; 0x1002334 + 0x0100227c: 9a03 .. LDR r2,[sp,#0xc] + 0x0100227e: 9904 .. LDR r1,[sp,#0x10] + 0x01002280: f002f926 ..&. BL rt_kprintf ; 0x10044d0 + 0x01002284: 9804 .. LDR r0,[sp,#0x10] + 0x01002286: f001f831 ..1. BL object_split ; 0x10032ec + 0x0100228a: a033 3. ADR r0,{pc}+0xce ; 0x1002358 + 0x0100228c: f002f920 .. . BL rt_kprintf ; 0x10044d0 + 0x01002290: bf00 .. NOP + 0x01002292: a90d .. ADD r1,sp,#0x34 + 0x01002294: 4638 8F MOV r0,r7 + 0x01002296: f000f899 .... BL list_get_next ; 0x10023cc + 0x0100229a: 4607 .F MOV r7,r0 + 0x0100229c: 2500 .% MOVS r5,#0 + 0x0100229e: e03c <. B 0x100231a ; list_event + 186 + 0x010022a0: 00a8 .. LSLS r0,r5,#2 + 0x010022a2: a905 .. ADD r1,sp,#0x14 + 0x010022a4: 5808 .X LDR r0,[r1,r0] + 0x010022a6: 4606 .F MOV r6,r0 + 0x010022a8: 3e0c .> SUBS r6,r6,#0xc + 0x010022aa: f7fef909 .... BL rt_hw_interrupt_disable ; 0x10004c0 + 0x010022ae: 9012 .. STR r0,[sp,#0x48] + 0x010022b0: 7a30 0z LDRB r0,[r6,#8] + 0x010022b2: 2180 .! MOVS r1,#0x80 + 0x010022b4: 4388 .C BICS r0,r0,r1 + 0x010022b6: a908 .. ADD r1,sp,#0x20 + 0x010022b8: 7f09 .. LDRB r1,[r1,#0x1c] + 0x010022ba: 4288 .B CMP r0,r1 + 0x010022bc: d003 .. BEQ 0x10022c6 ; list_event + 102 + 0x010022be: 9812 .. LDR r0,[sp,#0x48] + 0x010022c0: f7fef902 .... BL rt_hw_interrupt_enable ; 0x10004c8 + 0x010022c4: e028 (. B 0x1002318 ; list_event + 184 + 0x010022c6: 9812 .. LDR r0,[sp,#0x48] + 0x010022c8: f7fef8fe .... BL rt_hw_interrupt_enable ; 0x10004c8 + 0x010022cc: 4634 4F MOV r4,r6 + 0x010022ce: 4620 F MOV r0,r4 + 0x010022d0: 3014 .0 ADDS r0,r0,#0x14 + 0x010022d2: f002f948 ..H. BL rt_list_isempty ; 0x1004566 + 0x010022d6: 2800 .( CMP r0,#0 + 0x010022d8: d115 .. BNE 0x1002306 ; list_event + 166 + 0x010022da: 4620 F MOV r0,r4 + 0x010022dc: 3014 .0 ADDS r0,r0,#0x14 + 0x010022de: f002f95a ..Z. BL rt_list_len ; 0x1004596 + 0x010022e2: 9002 .. STR r0,[sp,#8] + 0x010022e4: 69e1 .i LDR r1,[r4,#0x1c] + 0x010022e6: 4623 #F MOV r3,r4 + 0x010022e8: 2208 ." MOVS r2,#8 + 0x010022ea: 9100 .. STR r1,[sp,#0] + 0x010022ec: 9001 .. STR r0,[sp,#4] + 0x010022ee: a022 ". ADR r0,{pc}+0x8a ; 0x1002378 + 0x010022f0: 9904 .. LDR r1,[sp,#0x10] + 0x010022f2: f002f8ed .... BL rt_kprintf ; 0x10044d0 + 0x010022f6: 4620 F MOV r0,r4 + 0x010022f8: 3014 .0 ADDS r0,r0,#0x14 + 0x010022fa: f004fd6d ..m. BL show_wait_queue ; 0x1006dd8 + 0x010022fe: a015 .. ADR r0,{pc}+0x56 ; 0x1002354 + 0x01002300: f002f8e6 .... BL rt_kprintf ; 0x10044d0 + 0x01002304: e007 .. B 0x1002316 ; list_event + 182 + 0x01002306: 69e0 .i LDR r0,[r4,#0x1c] + 0x01002308: 4623 #F MOV r3,r4 + 0x0100230a: 2208 ." MOVS r2,#8 + 0x0100230c: 9000 .. STR r0,[sp,#0] + 0x0100230e: a020 . ADR r0,{pc}+0x82 ; 0x1002390 + 0x01002310: 9904 .. LDR r1,[sp,#0x10] + 0x01002312: f002f8dd .... BL rt_kprintf ; 0x10044d0 + 0x01002316: bf00 .. NOP + 0x01002318: 1c6d m. ADDS r5,r5,#1 + 0x0100231a: 9811 .. LDR r0,[sp,#0x44] + 0x0100231c: 42a8 .B CMP r0,r5 + 0x0100231e: dcbf .. BGT 0x10022a0 ; list_event + 64 + 0x01002320: 2f00 ./ CMP r7,#0 + 0x01002322: d1b6 .. BNE 0x1002292 ; list_event + 50 + 0x01002324: 2000 . MOVS r0,#0 + 0x01002326: b013 .. ADD sp,sp,#0x4c + 0x01002328: bdf0 .. POP {r4-r7,pc} + $d + 0x0100232a: 0000 .. DCW 0 + 0x0100232c: 6e657665 even DCD 1852143205 + 0x01002330: 00000074 t... DCD 116 + 0x01002334: 2e2a2d25 %-*. DCD 774516005 + 0x01002338: 20202073 s DCD 538976371 + 0x0100233c: 73202020 s DCD 1931485216 + 0x01002340: 20207465 et DCD 538997861 + 0x01002344: 75732020 su DCD 1970479136 + 0x01002348: 6e657073 spen DCD 1852141683 + 0x0100234c: 68742064 d th DCD 1752440932 + 0x01002350: 64616572 read DCD 1684104562 + 0x01002354: 0000000a .... DCD 10 + 0x01002358: 2d2d2020 -- DCD 757932064 + 0x0100235c: 2d2d2d2d ---- DCD 757935405 + 0x01002360: 2d2d2d2d ---- DCD 757935405 + 0x01002364: 2d2d2d20 --- DCD 757935392 + 0x01002368: 2d2d2d2d ---- DCD 757935405 + 0x0100236c: 2d2d2d2d ---- DCD 757935405 + 0x01002370: 0a2d2d2d ---. DCD 170732845 + 0x01002374: 00000000 .... DCD 0 + 0x01002378: 2e2a2d25 %-*. DCD 774516005 + 0x0100237c: 2020732a *s DCD 538997546 + 0x01002380: 30257830 0x%0 DCD 807761968 + 0x01002384: 25207838 8x % DCD 622884920 + 0x01002388: 3a643330 03d: DCD 979645232 + 0x0100238c: 00000000 .... DCD 0 + 0x01002390: 2e2a2d25 %-*. DCD 774516005 + 0x01002394: 2020732a *s DCD 538997546 + 0x01002398: 30257830 0x%0 DCD 807761968 + 0x0100239c: 30207838 8x 0 DCD 807434296 + 0x010023a0: 0000000a .... DCD 10 + $t + i.list_find_init + list_find_init + 0x010023a4: b5fe .. PUSH {r1-r7,lr} + 0x010023a6: 4604 .F MOV r4,r0 + 0x010023a8: 460d .F MOV r5,r1 + 0x010023aa: 4616 .F MOV r6,r2 + 0x010023ac: 461f .F MOV r7,r3 + 0x010023ae: 4628 (F MOV r0,r5 + 0x010023b0: f002fd02 .... BL rt_object_get_information ; 0x1004db8 + 0x010023b4: 9001 .. STR r0,[sp,#4] + 0x010023b6: 9801 .. LDR r0,[sp,#4] + 0x010023b8: 1d00 .. ADDS r0,r0,#4 + 0x010023ba: 9000 .. STR r0,[sp,#0] + 0x010023bc: 9800 .. LDR r0,[sp,#0] + 0x010023be: 6020 ` STR r0,[r4,#0] + 0x010023c0: 7225 %r STRB r5,[r4,#8] + 0x010023c2: 6066 f` STR r6,[r4,#4] + 0x010023c4: 60e7 .` STR r7,[r4,#0xc] + 0x010023c6: 2000 . MOVS r0,#0 + 0x010023c8: 6120 a STR r0,[r4,#0x10] + 0x010023ca: bdfe .. POP {r1-r7,pc} + i.list_get_next + list_get_next + 0x010023cc: b5f0 .. PUSH {r4-r7,lr} + 0x010023ce: b085 .. SUB sp,sp,#0x14 + 0x010023d0: 4607 .F MOV r7,r0 + 0x010023d2: 460c .F MOV r4,r1 + 0x010023d4: 2000 . MOVS r0,#0 + 0x010023d6: 9004 .. STR r0,[sp,#0x10] + 0x010023d8: 6120 a STR r0,[r4,#0x10] + 0x010023da: 68e0 .h LDR r0,[r4,#0xc] + 0x010023dc: 2800 .( CMP r0,#0 + 0x010023de: d002 .. BEQ 0x10023e6 ; list_get_next + 26 + 0x010023e0: 7a20 z LDRB r0,[r4,#8] + 0x010023e2: 2800 .( CMP r0,#0 + 0x010023e4: d102 .. BNE 0x10023ec ; list_get_next + 32 + 0x010023e6: 2000 . MOVS r0,#0 + 0x010023e8: b005 .. ADD sp,sp,#0x14 + 0x010023ea: bdf0 .. POP {r4-r7,pc} + 0x010023ec: 6820 h LDR r0,[r4,#0] + 0x010023ee: 9002 .. STR r0,[sp,#8] + 0x010023f0: 2f00 ./ CMP r7,#0 + 0x010023f2: d103 .. BNE 0x10023fc ; list_get_next + 48 + 0x010023f4: 9d02 .. LDR r5,[sp,#8] + 0x010023f6: 2001 . MOVS r0,#1 + 0x010023f8: 9004 .. STR r0,[sp,#0x10] + 0x010023fa: e000 .. B 0x10023fe ; list_get_next + 50 + 0x010023fc: 463d =F MOV r5,r7 + 0x010023fe: f7fef85f .._. BL rt_hw_interrupt_disable ; 0x10004c0 + 0x01002402: 9003 .. STR r0,[sp,#0xc] + 0x01002404: 9804 .. LDR r0,[sp,#0x10] + 0x01002406: 2800 .( CMP r0,#0 + 0x01002408: d10f .. BNE 0x100242a ; list_get_next + 94 + 0x0100240a: 4628 (F MOV r0,r5 + 0x0100240c: 380c .8 SUBS r0,r0,#0xc + 0x0100240e: 9000 .. STR r0,[sp,#0] + 0x01002410: 9800 .. LDR r0,[sp,#0] + 0x01002412: 7a00 .z LDRB r0,[r0,#8] + 0x01002414: 2180 .! MOVS r1,#0x80 + 0x01002416: 4388 .C BICS r0,r0,r1 + 0x01002418: 7a21 !z LDRB r1,[r4,#8] + 0x0100241a: 4288 .B CMP r0,r1 + 0x0100241c: d004 .. BEQ 0x1002428 ; list_get_next + 92 + 0x0100241e: 9803 .. LDR r0,[sp,#0xc] + 0x01002420: f7fef852 ..R. BL rt_hw_interrupt_enable ; 0x10004c8 + 0x01002424: 2000 . MOVS r0,#0 + 0x01002426: e7df .. B 0x10023e8 ; list_get_next + 28 + 0x01002428: bf00 .. NOP + 0x0100242a: 2600 .& MOVS r6,#0 + 0x0100242c: 6860 `h LDR r0,[r4,#4] + 0x0100242e: 9001 .. STR r0,[sp,#4] + 0x01002430: e00f .. B 0x1002452 ; list_get_next + 134 + 0x01002432: 682d -h LDR r5,[r5,#0] + 0x01002434: 9802 .. LDR r0,[sp,#8] + 0x01002436: 4285 .B CMP r5,r0 + 0x01002438: d101 .. BNE 0x100243e ; list_get_next + 114 + 0x0100243a: 2500 .% MOVS r5,#0 + 0x0100243c: e00a .. B 0x1002454 ; list_get_next + 136 + 0x0100243e: 1c76 v. ADDS r6,r6,#1 + 0x01002440: 9801 .. LDR r0,[sp,#4] + 0x01002442: 6005 .` STR r5,[r0,#0] + 0x01002444: 9801 .. LDR r0,[sp,#4] + 0x01002446: 1d00 .. ADDS r0,r0,#4 + 0x01002448: 9001 .. STR r0,[sp,#4] + 0x0100244a: 68e0 .h LDR r0,[r4,#0xc] + 0x0100244c: 42b0 .B CMP r0,r6 + 0x0100244e: d100 .. BNE 0x1002452 ; list_get_next + 134 + 0x01002450: e000 .. B 0x1002454 ; list_get_next + 136 + 0x01002452: e7ee .. B 0x1002432 ; list_get_next + 102 + 0x01002454: bf00 .. NOP + 0x01002456: 9803 .. LDR r0,[sp,#0xc] + 0x01002458: f7fef836 ..6. BL rt_hw_interrupt_enable ; 0x10004c8 + 0x0100245c: 6126 &a STR r6,[r4,#0x10] + 0x0100245e: 4628 (F MOV r0,r5 + 0x01002460: e7c2 .. B 0x10023e8 ; list_get_next + 28 + 0x01002462: 0000 .. MOVS r0,r0 + i.list_mailbox + list_mailbox + 0x01002464: b5f0 .. PUSH {r4-r7,lr} + 0x01002466: b095 .. SUB sp,sp,#0x54 + 0x01002468: 2700 .' MOVS r7,#0 + 0x0100246a: a036 6. ADR r0,{pc}+0xda ; 0x1002544 + 0x0100246c: 9005 .. STR r0,[sp,#0x14] + 0x0100246e: 2308 .# MOVS r3,#8 + 0x01002470: aa07 .. ADD r2,sp,#0x1c + 0x01002472: 2105 .! MOVS r1,#5 + 0x01002474: a80f .. ADD r0,sp,#0x3c + 0x01002476: f7ffff95 .... BL list_find_init ; 0x10023a4 + 0x0100247a: 2008 . MOVS r0,#8 + 0x0100247c: 9006 .. STR r0,[sp,#0x18] + 0x0100247e: a033 3. ADR r0,{pc}+0xce ; 0x100254c + 0x01002480: 9a05 .. LDR r2,[sp,#0x14] + 0x01002482: 9906 .. LDR r1,[sp,#0x18] + 0x01002484: f002f824 ..$. BL rt_kprintf ; 0x10044d0 + 0x01002488: 9806 .. LDR r0,[sp,#0x18] + 0x0100248a: f000ff2f ../. BL object_split ; 0x10032ec + 0x0100248e: a038 8. ADR r0,{pc}+0xe2 ; 0x1002570 + 0x01002490: f002f81e .... BL rt_kprintf ; 0x10044d0 + 0x01002494: bf00 .. NOP + 0x01002496: a90f .. ADD r1,sp,#0x3c + 0x01002498: 4638 8F MOV r0,r7 + 0x0100249a: f7ffff97 .... BL list_get_next ; 0x10023cc + 0x0100249e: 4607 .F MOV r7,r0 + 0x010024a0: 2500 .% MOVS r5,#0 + 0x010024a2: e046 F. B 0x1002532 ; list_mailbox + 206 + 0x010024a4: 00a8 .. LSLS r0,r5,#2 + 0x010024a6: a907 .. ADD r1,sp,#0x1c + 0x010024a8: 5808 .X LDR r0,[r1,r0] + 0x010024aa: 4606 .F MOV r6,r0 + 0x010024ac: 3e0c .> SUBS r6,r6,#0xc + 0x010024ae: f7fef807 .... BL rt_hw_interrupt_disable ; 0x10004c0 + 0x010024b2: 9014 .. STR r0,[sp,#0x50] + 0x010024b4: 7a30 0z LDRB r0,[r6,#8] + 0x010024b6: 2180 .! MOVS r1,#0x80 + 0x010024b8: 4388 .C BICS r0,r0,r1 + 0x010024ba: a910 .. ADD r1,sp,#0x40 + 0x010024bc: 7909 .y LDRB r1,[r1,#4] + 0x010024be: 4288 .B CMP r0,r1 + 0x010024c0: d003 .. BEQ 0x10024ca ; list_mailbox + 102 + 0x010024c2: 9814 .. LDR r0,[sp,#0x50] + 0x010024c4: f7fef800 .... BL rt_hw_interrupt_enable ; 0x10004c8 + 0x010024c8: e032 2. B 0x1002530 ; list_mailbox + 204 + 0x010024ca: 9814 .. LDR r0,[sp,#0x50] + 0x010024cc: f7fdfffc .... BL rt_hw_interrupt_enable ; 0x10004c8 + 0x010024d0: 4634 4F MOV r4,r6 + 0x010024d2: 4620 F MOV r0,r4 + 0x010024d4: 3014 .0 ADDS r0,r0,#0x14 + 0x010024d6: f002f846 ..F. BL rt_list_isempty ; 0x1004566 + 0x010024da: 2800 .( CMP r0,#0 + 0x010024dc: d117 .. BNE 0x100250e ; list_mailbox + 170 + 0x010024de: 4620 F MOV r0,r4 + 0x010024e0: 3014 .0 ADDS r0,r0,#0x14 + 0x010024e2: f002f858 ..X. BL rt_list_len ; 0x1004596 + 0x010024e6: 9004 .. STR r0,[sp,#0x10] + 0x010024e8: 8c21 !. LDRH r1,[r4,#0x20] + 0x010024ea: 8c62 b. LDRH r2,[r4,#0x22] + 0x010024ec: 4623 #F MOV r3,r4 + 0x010024ee: 9200 .. STR r2,[sp,#0] + 0x010024f0: 9101 .. STR r1,[sp,#4] + 0x010024f2: 9002 .. STR r0,[sp,#8] + 0x010024f4: 2208 ." MOVS r2,#8 + 0x010024f6: a025 %. ADR r0,{pc}+0x96 ; 0x100258c + 0x010024f8: 9906 .. LDR r1,[sp,#0x18] + 0x010024fa: f001ffe9 .... BL rt_kprintf ; 0x10044d0 + 0x010024fe: 4620 F MOV r0,r4 + 0x01002500: 3014 .0 ADDS r0,r0,#0x14 + 0x01002502: f004fc69 ..i. BL show_wait_queue ; 0x1006dd8 + 0x01002506: a027 '. ADR r0,{pc}+0x9e ; 0x10025a4 + 0x01002508: f001ffe2 .... BL rt_kprintf ; 0x10044d0 + 0x0100250c: e00f .. B 0x100252e ; list_mailbox + 202 + 0x0100250e: 4620 F MOV r0,r4 + 0x01002510: 3014 .0 ADDS r0,r0,#0x14 + 0x01002512: f002f840 ..@. BL rt_list_len ; 0x1004596 + 0x01002516: 9004 .. STR r0,[sp,#0x10] + 0x01002518: 8c21 !. LDRH r1,[r4,#0x20] + 0x0100251a: 8c62 b. LDRH r2,[r4,#0x22] + 0x0100251c: 4623 #F MOV r3,r4 + 0x0100251e: 9200 .. STR r2,[sp,#0] + 0x01002520: 9101 .. STR r1,[sp,#4] + 0x01002522: 9002 .. STR r0,[sp,#8] + 0x01002524: 2208 ." MOVS r2,#8 + 0x01002526: a020 . ADR r0,{pc}+0x82 ; 0x10025a8 + 0x01002528: 9906 .. LDR r1,[sp,#0x18] + 0x0100252a: f001ffd1 .... BL rt_kprintf ; 0x10044d0 + 0x0100252e: bf00 .. NOP + 0x01002530: 1c6d m. ADDS r5,r5,#1 + 0x01002532: 9813 .. LDR r0,[sp,#0x4c] + 0x01002534: 42a8 .B CMP r0,r5 + 0x01002536: dcb5 .. BGT 0x10024a4 ; list_mailbox + 64 + 0x01002538: 2f00 ./ CMP r7,#0 + 0x0100253a: d1ac .. BNE 0x1002496 ; list_mailbox + 50 + 0x0100253c: 2000 . MOVS r0,#0 + 0x0100253e: b015 .. ADD sp,sp,#0x54 + 0x01002540: bdf0 .. POP {r4-r7,pc} + $d + 0x01002542: 0000 .. DCW 0 + 0x01002544: 6c69616d mail DCD 1818845549 + 0x01002548: 00786f62 box. DCD 7892834 + 0x0100254c: 2e2a2d25 %-*. DCD 774516005 + 0x01002550: 6e652073 s en DCD 1852121203 + 0x01002554: 20797274 try DCD 544830068 + 0x01002558: 657a6973 size DCD 1702521203 + 0x0100255c: 73757320 sus DCD 1937077024 + 0x01002560: 646e6570 pend DCD 1684956528 + 0x01002564: 72687420 thr DCD 1919448096 + 0x01002568: 0a646165 ead. DCD 174350693 + 0x0100256c: 00000000 .... DCD 0 + 0x01002570: 2d2d2d20 --- DCD 757935392 + 0x01002574: 2d20202d - - DCD 757080109 + 0x01002578: 202d2d2d --- DCD 539831597 + 0x0100257c: 2d2d2d2d ---- DCD 757935405 + 0x01002580: 2d2d2d2d ---- DCD 757935405 + 0x01002584: 2d2d2d2d ---- DCD 757935405 + 0x01002588: 000a2d2d --.. DCD 666925 + 0x0100258c: 2e2a2d25 %-*. DCD 774516005 + 0x01002590: 2520732a *s % DCD 622883626 + 0x01002594: 20643430 04d DCD 543437872 + 0x01002598: 34302520 %04 DCD 875570464 + 0x0100259c: 64252064 d %d DCD 1680154724 + 0x010025a0: 0000003a :... DCD 58 + 0x010025a4: 0000000a .... DCD 10 + 0x010025a8: 2e2a2d25 %-*. DCD 774516005 + 0x010025ac: 2520732a *s % DCD 622883626 + 0x010025b0: 20643430 04d DCD 543437872 + 0x010025b4: 34302520 %04 DCD 875570464 + 0x010025b8: 64252064 d %d DCD 1680154724 + 0x010025bc: 0000000a .... DCD 10 + $t + i.list_mem + list_mem + 0x010025c0: b510 .. PUSH {r4,lr} + 0x010025c2: 4808 .H LDR r0,[pc,#32] ; [0x10025e4] = 0x20148 + 0x010025c4: 6801 .h LDR r1,[r0,#0] + 0x010025c6: a008 .. ADR r0,{pc}+0x22 ; 0x10025e8 + 0x010025c8: f001ff82 .... BL rt_kprintf ; 0x10044d0 + 0x010025cc: 480b .H LDR r0,[pc,#44] ; [0x10025fc] = 0x2014c + 0x010025ce: 6801 .h LDR r1,[r0,#0] + 0x010025d0: a00b .. ADR r0,{pc}+0x30 ; 0x1002600 + 0x010025d2: f001ff7d ..}. BL rt_kprintf ; 0x10044d0 + 0x010025d6: 480f .H LDR r0,[pc,#60] ; [0x1002614] = 0x20150 + 0x010025d8: 6801 .h LDR r1,[r0,#0] + 0x010025da: a00f .. ADR r0,{pc}+0x3e ; 0x1002618 + 0x010025dc: f001ff78 ..x. BL rt_kprintf ; 0x10044d0 + 0x010025e0: bd10 .. POP {r4,pc} + $d + 0x010025e2: 0000 .. DCW 0 + 0x010025e4: 00020148 H... DCD 131400 + 0x010025e8: 61746f74 tota DCD 1635020660 + 0x010025ec: 656d206c l me DCD 1701650540 + 0x010025f0: 79726f6d mory DCD 2037542765 + 0x010025f4: 6425203a : %d DCD 1680154682 + 0x010025f8: 0000000a .... DCD 10 + 0x010025fc: 0002014c L... DCD 131404 + 0x01002600: 64657375 used DCD 1684370293 + 0x01002604: 6d656d20 mem DCD 1835363616 + 0x01002608: 2079726f ory DCD 544830063 + 0x0100260c: 6425203a : %d DCD 1680154682 + 0x01002610: 0000000a .... DCD 10 + 0x01002614: 00020150 P... DCD 131408 + 0x01002618: 6978616d maxi DCD 1769496941 + 0x0100261c: 206d756d mum DCD 544044397 + 0x01002620: 6f6c6c61 allo DCD 1869376609 + 0x01002624: 65746163 cate DCD 1702125923 + 0x01002628: 656d2064 d me DCD 1701650532 + 0x0100262c: 79726f6d mory DCD 2037542765 + 0x01002630: 6425203a : %d DCD 1680154682 + 0x01002634: 0000000a .... DCD 10 + $t + i.list_memheap + list_memheap + 0x01002638: b5f0 .. PUSH {r4-r7,lr} + 0x0100263a: b093 .. SUB sp,sp,#0x4c + 0x0100263c: 2700 .' MOVS r7,#0 + 0x0100263e: a025 %. ADR r0,{pc}+0x96 ; 0x10026d4 + 0x01002640: 9003 .. STR r0,[sp,#0xc] + 0x01002642: 2308 .# MOVS r3,#8 + 0x01002644: aa05 .. ADD r2,sp,#0x14 + 0x01002646: 2107 .! MOVS r1,#7 + 0x01002648: a80d .. ADD r0,sp,#0x34 + 0x0100264a: f7fffeab .... BL list_find_init ; 0x10023a4 + 0x0100264e: 2008 . MOVS r0,#8 + 0x01002650: 9004 .. STR r0,[sp,#0x10] + 0x01002652: a022 ". ADR r0,{pc}+0x8a ; 0x10026dc + 0x01002654: 9a03 .. LDR r2,[sp,#0xc] + 0x01002656: 9904 .. LDR r1,[sp,#0x10] + 0x01002658: f001ff3a ..:. BL rt_kprintf ; 0x10044d0 + 0x0100265c: 9804 .. LDR r0,[sp,#0x10] + 0x0100265e: f000fe45 ..E. BL object_split ; 0x10032ec + 0x01002662: a02a *. ADR r0,{pc}+0xaa ; 0x100270c + 0x01002664: f001ff34 ..4. BL rt_kprintf ; 0x10044d0 + 0x01002668: bf00 .. NOP + 0x0100266a: a90d .. ADD r1,sp,#0x34 + 0x0100266c: 4638 8F MOV r0,r7 + 0x0100266e: f7fffead .... BL list_get_next ; 0x10023cc + 0x01002672: 4607 .F MOV r7,r0 + 0x01002674: 2600 .& MOVS r6,#0 + 0x01002676: e024 $. B 0x10026c2 ; list_memheap + 138 + 0x01002678: 00b0 .. LSLS r0,r6,#2 + 0x0100267a: a905 .. ADD r1,sp,#0x14 + 0x0100267c: 5808 .X LDR r0,[r1,r0] + 0x0100267e: 4604 .F MOV r4,r0 + 0x01002680: 3c0c .< SUBS r4,r4,#0xc + 0x01002682: f7fdff1d .... BL rt_hw_interrupt_disable ; 0x10004c0 + 0x01002686: 9012 .. STR r0,[sp,#0x48] + 0x01002688: 7a20 z LDRB r0,[r4,#8] + 0x0100268a: 2180 .! MOVS r1,#0x80 + 0x0100268c: 4388 .C BICS r0,r0,r1 + 0x0100268e: a908 .. ADD r1,sp,#0x20 + 0x01002690: 7f09 .. LDRB r1,[r1,#0x1c] + 0x01002692: 4288 .B CMP r0,r1 + 0x01002694: d003 .. BEQ 0x100269e ; list_memheap + 102 + 0x01002696: 9812 .. LDR r0,[sp,#0x48] + 0x01002698: f7fdff16 .... BL rt_hw_interrupt_enable ; 0x10004c8 + 0x0100269c: e010 .. B 0x10026c0 ; list_memheap + 136 + 0x0100269e: 9812 .. LDR r0,[sp,#0x48] + 0x010026a0: f7fdff12 .... BL rt_hw_interrupt_enable ; 0x10004c8 + 0x010026a4: 4625 %F MOV r5,r4 + 0x010026a6: 6a2a *j LDR r2,[r5,#0x20] + 0x010026a8: 69a9 .i LDR r1,[r5,#0x18] + 0x010026aa: 69e8 .i LDR r0,[r5,#0x1c] + 0x010026ac: 462b +F MOV r3,r5 + 0x010026ae: 9201 .. STR r2,[sp,#4] + 0x010026b0: 9100 .. STR r1,[sp,#0] + 0x010026b2: 9002 .. STR r0,[sp,#8] + 0x010026b4: 2208 ." MOVS r2,#8 + 0x010026b6: a020 . ADR r0,{pc}+0x82 ; 0x1002738 + 0x010026b8: 9904 .. LDR r1,[sp,#0x10] + 0x010026ba: f001ff09 .... BL rt_kprintf ; 0x10044d0 + 0x010026be: bf00 .. NOP + 0x010026c0: 1c76 v. ADDS r6,r6,#1 + 0x010026c2: 9811 .. LDR r0,[sp,#0x44] + 0x010026c4: 42b0 .B CMP r0,r6 + 0x010026c6: dcd7 .. BGT 0x1002678 ; list_memheap + 64 + 0x010026c8: 2f00 ./ CMP r7,#0 + 0x010026ca: d1ce .. BNE 0x100266a ; list_memheap + 50 + 0x010026cc: 2000 . MOVS r0,#0 + 0x010026ce: b013 .. ADD sp,sp,#0x4c + 0x010026d0: bdf0 .. POP {r4-r7,pc} + $d + 0x010026d2: 0000 .. DCW 0 + 0x010026d4: 686d656d memh DCD 1751999853 + 0x010026d8: 00706165 eap. DCD 7364965 + 0x010026dc: 2e2a2d25 %-*. DCD 774516005 + 0x010026e0: 70202073 s p DCD 1881153651 + 0x010026e4: 206c6f6f ool DCD 543977327 + 0x010026e8: 657a6973 size DCD 1702521203 + 0x010026ec: 616d2020 ma DCD 1634541600 + 0x010026f0: 73752078 x us DCD 1937055864 + 0x010026f4: 73206465 ed s DCD 1931502693 + 0x010026f8: 20657a69 ize DCD 543521385 + 0x010026fc: 69617661 avai DCD 1767994977 + 0x01002700: 6c62616c labl DCD 1818386796 + 0x01002704: 69732065 e si DCD 1769152613 + 0x01002708: 000a657a ze.. DCD 681338 + 0x0100270c: 2d2d2d20 --- DCD 757935392 + 0x01002710: 2d2d2d2d ---- DCD 757935405 + 0x01002714: 202d2d2d --- DCD 539831597 + 0x01002718: 2d2d2d2d ---- DCD 757935405 + 0x0100271c: 2d2d2d2d ---- DCD 757935405 + 0x01002720: 2d2d2d2d ---- DCD 757935405 + 0x01002724: 2d2d202d - -- DCD 757932077 + 0x01002728: 2d2d2d2d ---- DCD 757935405 + 0x0100272c: 2d2d2d2d ---- DCD 757935405 + 0x01002730: 2d2d2d2d ---- DCD 757935405 + 0x01002734: 0000000a .... DCD 10 + 0x01002738: 2e2a2d25 %-*. DCD 774516005 + 0x0100273c: 2520732a *s % DCD 622883626 + 0x01002740: 3031302d -010 DCD 808529965 + 0x01002744: 2d252064 d %- DCD 757407844 + 0x01002748: 64333130 013d DCD 1681076528 + 0x0100274c: 302d2520 %-0 DCD 808264992 + 0x01002750: 000a6435 5d.. DCD 681013 + $t + i.list_mempool + list_mempool + 0x01002754: b5f0 .. PUSH {r4-r7,lr} + 0x01002756: b097 .. SUB sp,sp,#0x5c + 0x01002758: 2000 . MOVS r0,#0 + 0x0100275a: 9008 .. STR r0,[sp,#0x20] + 0x0100275c: a037 7. ADR r0,{pc}+0xe0 ; 0x100283c + 0x0100275e: 9006 .. STR r0,[sp,#0x18] + 0x01002760: 2308 .# MOVS r3,#8 + 0x01002762: aa09 .. ADD r2,sp,#0x24 + 0x01002764: 4619 .F MOV r1,r3 + 0x01002766: a811 .. ADD r0,sp,#0x44 + 0x01002768: f7fffe1c .... BL list_find_init ; 0x10023a4 + 0x0100276c: 2008 . MOVS r0,#8 + 0x0100276e: 9007 .. STR r0,[sp,#0x1c] + 0x01002770: a034 4. ADR r0,{pc}+0xd4 ; 0x1002844 + 0x01002772: 9a06 .. LDR r2,[sp,#0x18] + 0x01002774: 9907 .. LDR r1,[sp,#0x1c] + 0x01002776: f001feab .... BL rt_kprintf ; 0x10044d0 + 0x0100277a: 9807 .. LDR r0,[sp,#0x1c] + 0x0100277c: f000fdb6 .... BL object_split ; 0x10032ec + 0x01002780: a03a :. ADR r0,{pc}+0xec ; 0x100286c + 0x01002782: f001fea5 .... BL rt_kprintf ; 0x10044d0 + 0x01002786: bf00 .. NOP + 0x01002788: a911 .. ADD r1,sp,#0x44 + 0x0100278a: 9808 .. LDR r0,[sp,#0x20] + 0x0100278c: f7fffe1e .... BL list_get_next ; 0x10023cc + 0x01002790: 9008 .. STR r0,[sp,#0x20] + 0x01002792: 2600 .& MOVS r6,#0 + 0x01002794: e049 I. B 0x100282a ; list_mempool + 214 + 0x01002796: 00b0 .. LSLS r0,r6,#2 + 0x01002798: a909 .. ADD r1,sp,#0x24 + 0x0100279a: 5808 .X LDR r0,[r1,r0] + 0x0100279c: 4607 .F MOV r7,r0 + 0x0100279e: 3f0c .? SUBS r7,r7,#0xc + 0x010027a0: f7fdfe8e .... BL rt_hw_interrupt_disable ; 0x10004c0 + 0x010027a4: 9016 .. STR r0,[sp,#0x58] + 0x010027a6: 7a38 8z LDRB r0,[r7,#8] + 0x010027a8: 2180 .! MOVS r1,#0x80 + 0x010027aa: 4388 .C BICS r0,r0,r1 + 0x010027ac: a910 .. ADD r1,sp,#0x40 + 0x010027ae: 7b09 .{ LDRB r1,[r1,#0xc] + 0x010027b0: 4288 .B CMP r0,r1 + 0x010027b2: d003 .. BEQ 0x10027bc ; list_mempool + 104 + 0x010027b4: 9816 .. LDR r0,[sp,#0x58] + 0x010027b6: f7fdfe87 .... BL rt_hw_interrupt_enable ; 0x10004c8 + 0x010027ba: e035 5. B 0x1002828 ; list_mempool + 212 + 0x010027bc: 9816 .. LDR r0,[sp,#0x58] + 0x010027be: f7fdfe83 .... BL rt_hw_interrupt_enable ; 0x10004c8 + 0x010027c2: 463c SUBS r6,r6,#0xc + 0x01002912: f7fdfdd5 .... BL rt_hw_interrupt_disable ; 0x10004c0 + 0x01002916: 9012 .. STR r0,[sp,#0x48] + 0x01002918: 7a30 0z LDRB r0,[r6,#8] + 0x0100291a: 2180 .! MOVS r1,#0x80 + 0x0100291c: 4388 .C BICS r0,r0,r1 + 0x0100291e: a908 .. ADD r1,sp,#0x20 + 0x01002920: 7f09 .. LDRB r1,[r1,#0x1c] + 0x01002922: 4288 .B CMP r0,r1 + 0x01002924: d003 .. BEQ 0x100292e ; list_msgqueue + 102 + 0x01002926: 9812 .. LDR r0,[sp,#0x48] + 0x01002928: f7fdfdce .... BL rt_hw_interrupt_enable ; 0x10004c8 + 0x0100292c: e02e .. B 0x100298c ; list_msgqueue + 196 + 0x0100292e: 9812 .. LDR r0,[sp,#0x48] + 0x01002930: f7fdfdca .... BL rt_hw_interrupt_enable ; 0x10004c8 + 0x01002934: 4634 4F MOV r4,r6 + 0x01002936: 4620 F MOV r0,r4 + 0x01002938: 3014 .0 ADDS r0,r0,#0x14 + 0x0100293a: f001fe14 .... BL rt_list_isempty ; 0x1004566 + 0x0100293e: 2800 .( CMP r0,#0 + 0x01002940: d115 .. BNE 0x100296e ; list_msgqueue + 166 + 0x01002942: 4620 F MOV r0,r4 + 0x01002944: 3014 .0 ADDS r0,r0,#0x14 + 0x01002946: f001fe26 ..&. BL rt_list_len ; 0x1004596 + 0x0100294a: 9002 .. STR r0,[sp,#8] + 0x0100294c: 8ca1 .. LDRH r1,[r4,#0x24] + 0x0100294e: 4623 #F MOV r3,r4 + 0x01002950: 2208 ." MOVS r2,#8 + 0x01002952: 9100 .. STR r1,[sp,#0] + 0x01002954: 9001 .. STR r0,[sp,#4] + 0x01002956: a022 ". ADR r0,{pc}+0x8a ; 0x10029e0 + 0x01002958: 9904 .. LDR r1,[sp,#0x10] + 0x0100295a: f001fdb9 .... BL rt_kprintf ; 0x10044d0 + 0x0100295e: 4620 F MOV r0,r4 + 0x01002960: 3014 .0 ADDS r0,r0,#0x14 + 0x01002962: f004fa39 ..9. BL show_wait_queue ; 0x1006dd8 + 0x01002966: a023 #. ADR r0,{pc}+0x8e ; 0x10029f4 + 0x01002968: f001fdb2 .... BL rt_kprintf ; 0x10044d0 + 0x0100296c: e00d .. B 0x100298a ; list_msgqueue + 194 + 0x0100296e: 4620 F MOV r0,r4 + 0x01002970: 3014 .0 ADDS r0,r0,#0x14 + 0x01002972: f001fe10 .... BL rt_list_len ; 0x1004596 + 0x01002976: 9002 .. STR r0,[sp,#8] + 0x01002978: 8ca1 .. LDRH r1,[r4,#0x24] + 0x0100297a: 4623 #F MOV r3,r4 + 0x0100297c: 2208 ." MOVS r2,#8 + 0x0100297e: 9100 .. STR r1,[sp,#0] + 0x01002980: 9001 .. STR r0,[sp,#4] + 0x01002982: a01d .. ADR r0,{pc}+0x76 ; 0x10029f8 + 0x01002984: 9904 .. LDR r1,[sp,#0x10] + 0x01002986: f001fda3 .... BL rt_kprintf ; 0x10044d0 + 0x0100298a: bf00 .. NOP + 0x0100298c: 1c6d m. ADDS r5,r5,#1 + 0x0100298e: 9811 .. LDR r0,[sp,#0x44] + 0x01002990: 42a8 .B CMP r0,r5 + 0x01002992: dcb9 .. BGT 0x1002908 ; list_msgqueue + 64 + 0x01002994: 2f00 ./ CMP r7,#0 + 0x01002996: d1b0 .. BNE 0x10028fa ; list_msgqueue + 50 + 0x01002998: 2000 . MOVS r0,#0 + 0x0100299a: b013 .. ADD sp,sp,#0x4c + 0x0100299c: bdf0 .. POP {r4-r7,pc} + $d + 0x0100299e: 0000 .. DCW 0 + 0x010029a0: 7167736d msgq DCD 1902605165 + 0x010029a4: 65756575 ueue DCD 1702192501 + 0x010029a8: 00000000 .... DCD 0 + 0x010029ac: 2e2a2d25 %-*. DCD 774516005 + 0x010029b0: 6e652073 s en DCD 1852121203 + 0x010029b4: 20797274 try DCD 544830068 + 0x010029b8: 70737573 susp DCD 1886614899 + 0x010029bc: 20646e65 end DCD 543452773 + 0x010029c0: 65726874 thre DCD 1701996660 + 0x010029c4: 000a6461 ad.. DCD 681057 + 0x010029c8: 2d2d2d20 --- DCD 757935392 + 0x010029cc: 2d20202d - - DCD 757080109 + 0x010029d0: 2d2d2d2d ---- DCD 757935405 + 0x010029d4: 2d2d2d2d ---- DCD 757935405 + 0x010029d8: 2d2d2d2d ---- DCD 757935405 + 0x010029dc: 00000a2d -... DCD 2605 + 0x010029e0: 2e2a2d25 %-*. DCD 774516005 + 0x010029e4: 2520732a *s % DCD 622883626 + 0x010029e8: 20643430 04d DCD 543437872 + 0x010029ec: 3a642520 %d: DCD 979641632 + 0x010029f0: 00000000 .... DCD 0 + 0x010029f4: 0000000a .... DCD 10 + 0x010029f8: 2e2a2d25 %-*. DCD 774516005 + 0x010029fc: 2520732a *s % DCD 622883626 + 0x01002a00: 20643430 04d DCD 543437872 + 0x01002a04: 0a642520 %d. DCD 174335264 + 0x01002a08: 00000000 .... DCD 0 + $t + i.list_mutex + list_mutex + 0x01002a0c: b5f0 .. PUSH {r4-r7,lr} + 0x01002a0e: b095 .. SUB sp,sp,#0x54 + 0x01002a10: 2700 .' MOVS r7,#0 + 0x01002a12: a028 (. ADR r0,{pc}+0xa2 ; 0x1002ab4 + 0x01002a14: 9005 .. STR r0,[sp,#0x14] + 0x01002a16: 2308 .# MOVS r3,#8 + 0x01002a18: aa07 .. ADD r2,sp,#0x1c + 0x01002a1a: 2103 .! MOVS r1,#3 + 0x01002a1c: a80f .. ADD r0,sp,#0x3c + 0x01002a1e: f7fffcc1 .... BL list_find_init ; 0x10023a4 + 0x01002a22: 2008 . MOVS r0,#8 + 0x01002a24: 9006 .. STR r0,[sp,#0x18] + 0x01002a26: a025 %. ADR r0,{pc}+0x96 ; 0x1002abc + 0x01002a28: 9a05 .. LDR r2,[sp,#0x14] + 0x01002a2a: 9906 .. LDR r1,[sp,#0x18] + 0x01002a2c: f001fd50 ..P. BL rt_kprintf ; 0x10044d0 + 0x01002a30: 9806 .. LDR r0,[sp,#0x18] + 0x01002a32: f000fc5b ..[. BL object_split ; 0x10032ec + 0x01002a36: a02a *. ADR r0,{pc}+0xaa ; 0x1002ae0 + 0x01002a38: f001fd4a ..J. BL rt_kprintf ; 0x10044d0 + 0x01002a3c: bf00 .. NOP + 0x01002a3e: a90f .. ADD r1,sp,#0x3c + 0x01002a40: 4638 8F MOV r0,r7 + 0x01002a42: f7fffcc3 .... BL list_get_next ; 0x10023cc + 0x01002a46: 4607 .F MOV r7,r0 + 0x01002a48: 2600 .& MOVS r6,#0 + 0x01002a4a: e02a *. B 0x1002aa2 ; list_mutex + 150 + 0x01002a4c: 00b0 .. LSLS r0,r6,#2 + 0x01002a4e: a907 .. ADD r1,sp,#0x1c + 0x01002a50: 5808 .X LDR r0,[r1,r0] + 0x01002a52: 4604 .F MOV r4,r0 + 0x01002a54: 3c0c .< SUBS r4,r4,#0xc + 0x01002a56: f7fdfd33 ..3. BL rt_hw_interrupt_disable ; 0x10004c0 + 0x01002a5a: 9014 .. STR r0,[sp,#0x50] + 0x01002a5c: 7a20 z LDRB r0,[r4,#8] + 0x01002a5e: 2180 .! MOVS r1,#0x80 + 0x01002a60: 4388 .C BICS r0,r0,r1 + 0x01002a62: a910 .. ADD r1,sp,#0x40 + 0x01002a64: 7909 .y LDRB r1,[r1,#4] + 0x01002a66: 4288 .B CMP r0,r1 + 0x01002a68: d003 .. BEQ 0x1002a72 ; list_mutex + 102 + 0x01002a6a: 9814 .. LDR r0,[sp,#0x50] + 0x01002a6c: f7fdfd2c ..,. BL rt_hw_interrupt_enable ; 0x10004c8 + 0x01002a70: e016 .. B 0x1002aa0 ; list_mutex + 148 + 0x01002a72: 9814 .. LDR r0,[sp,#0x50] + 0x01002a74: f7fdfd28 ..(. BL rt_hw_interrupt_enable ; 0x10004c8 + 0x01002a78: 4625 %F MOV r5,r4 + 0x01002a7a: 4628 (F MOV r0,r5 + 0x01002a7c: 3014 .0 ADDS r0,r0,#0x14 + 0x01002a7e: f001fd8a .... BL rt_list_len ; 0x1004596 + 0x01002a82: 9004 .. STR r0,[sp,#0x10] + 0x01002a84: 7fe9 .. LDRB r1,[r5,#0x1f] + 0x01002a86: 2308 .# MOVS r3,#8 + 0x01002a88: 6a2a *j LDR r2,[r5,#0x20] + 0x01002a8a: 9300 .. STR r3,[sp,#0] + 0x01002a8c: 9201 .. STR r2,[sp,#4] + 0x01002a8e: 9102 .. STR r1,[sp,#8] + 0x01002a90: 9003 .. STR r0,[sp,#0xc] + 0x01002a92: 462b +F MOV r3,r5 + 0x01002a94: 2208 ." MOVS r2,#8 + 0x01002a96: a01a .. ADR r0,{pc}+0x6a ; 0x1002b00 + 0x01002a98: 9906 .. LDR r1,[sp,#0x18] + 0x01002a9a: f001fd19 .... BL rt_kprintf ; 0x10044d0 + 0x01002a9e: bf00 .. NOP + 0x01002aa0: 1c76 v. ADDS r6,r6,#1 + 0x01002aa2: 9813 .. LDR r0,[sp,#0x4c] + 0x01002aa4: 42b0 .B CMP r0,r6 + 0x01002aa6: dcd1 .. BGT 0x1002a4c ; list_mutex + 64 + 0x01002aa8: 2f00 ./ CMP r7,#0 + 0x01002aaa: d1c8 .. BNE 0x1002a3e ; list_mutex + 50 + 0x01002aac: 2000 . MOVS r0,#0 + 0x01002aae: b015 .. ADD sp,sp,#0x54 + 0x01002ab0: bdf0 .. POP {r4-r7,pc} + $d + 0x01002ab2: 0000 .. DCW 0 + 0x01002ab4: 6574756d mute DCD 1702131053 + 0x01002ab8: 00000078 x... DCD 120 + 0x01002abc: 2e2a2d25 %-*. DCD 774516005 + 0x01002ac0: 20202073 s DCD 538976371 + 0x01002ac4: 656e776f owne DCD 1701738351 + 0x01002ac8: 68202072 r h DCD 1746935922 + 0x01002acc: 20646c6f old DCD 543452271 + 0x01002ad0: 70737573 susp DCD 1886614899 + 0x01002ad4: 20646e65 end DCD 543452773 + 0x01002ad8: 65726874 thre DCD 1701996660 + 0x01002adc: 000a6461 ad.. DCD 681057 + 0x01002ae0: 2d2d2d20 --- DCD 757935392 + 0x01002ae4: 2d2d2d2d ---- DCD 757935405 + 0x01002ae8: 2d2d202d - -- DCD 757932077 + 0x01002aec: 2d202d2d -- - DCD 757083437 + 0x01002af0: 2d2d2d2d ---- DCD 757935405 + 0x01002af4: 2d2d2d2d ---- DCD 757935405 + 0x01002af8: 2d2d2d2d ---- DCD 757935405 + 0x01002afc: 00000a2d -... DCD 2605 + 0x01002b00: 2e2a2d25 %-*. DCD 774516005 + 0x01002b04: 2520732a *s % DCD 622883626 + 0x01002b08: 2a2e382d -8.* DCD 707672109 + 0x01002b0c: 30252073 s %0 DCD 807739507 + 0x01002b10: 25206434 4d % DCD 622879796 + 0x01002b14: 00000a64 d... DCD 2660 + $t + i.list_sem + list_sem + 0x01002b18: b5f0 .. PUSH {r4-r7,lr} + 0x01002b1a: b093 .. SUB sp,sp,#0x4c + 0x01002b1c: 2700 .' MOVS r7,#0 + 0x01002b1e: a034 4. ADR r0,{pc}+0xd2 ; 0x1002bf0 + 0x01002b20: 9003 .. STR r0,[sp,#0xc] + 0x01002b22: 2308 .# MOVS r3,#8 + 0x01002b24: aa05 .. ADD r2,sp,#0x14 + 0x01002b26: 2102 .! MOVS r1,#2 + 0x01002b28: a80d .. ADD r0,sp,#0x34 + 0x01002b2a: f7fffc3b ..;. BL list_find_init ; 0x10023a4 + 0x01002b2e: 2008 . MOVS r0,#8 + 0x01002b30: 9004 .. STR r0,[sp,#0x10] + 0x01002b32: a032 2. ADR r0,{pc}+0xca ; 0x1002bfc + 0x01002b34: 9a03 .. LDR r2,[sp,#0xc] + 0x01002b36: 9904 .. LDR r1,[sp,#0x10] + 0x01002b38: f001fcca .... BL rt_kprintf ; 0x10044d0 + 0x01002b3c: 9804 .. LDR r0,[sp,#0x10] + 0x01002b3e: f000fbd5 .... BL object_split ; 0x10032ec + 0x01002b42: a035 5. ADR r0,{pc}+0xd6 ; 0x1002c18 + 0x01002b44: f001fcc4 .... BL rt_kprintf ; 0x10044d0 + 0x01002b48: bf00 .. NOP + 0x01002b4a: a90d .. ADD r1,sp,#0x34 + 0x01002b4c: 4638 8F MOV r0,r7 + 0x01002b4e: f7fffc3d ..=. BL list_get_next ; 0x10023cc + 0x01002b52: 4607 .F MOV r7,r0 + 0x01002b54: 2500 .% MOVS r5,#0 + 0x01002b56: e042 B. B 0x1002bde ; list_sem + 198 + 0x01002b58: 00a8 .. LSLS r0,r5,#2 + 0x01002b5a: a905 .. ADD r1,sp,#0x14 + 0x01002b5c: 5808 .X LDR r0,[r1,r0] + 0x01002b5e: 4606 .F MOV r6,r0 + 0x01002b60: 3e0c .> SUBS r6,r6,#0xc + 0x01002b62: f7fdfcad .... BL rt_hw_interrupt_disable ; 0x10004c0 + 0x01002b66: 9012 .. STR r0,[sp,#0x48] + 0x01002b68: 7a30 0z LDRB r0,[r6,#8] + 0x01002b6a: 2180 .! MOVS r1,#0x80 + 0x01002b6c: 4388 .C BICS r0,r0,r1 + 0x01002b6e: a908 .. ADD r1,sp,#0x20 + 0x01002b70: 7f09 .. LDRB r1,[r1,#0x1c] + 0x01002b72: 4288 .B CMP r0,r1 + 0x01002b74: d003 .. BEQ 0x1002b7e ; list_sem + 102 + 0x01002b76: 9812 .. LDR r0,[sp,#0x48] + 0x01002b78: f7fdfca6 .... BL rt_hw_interrupt_enable ; 0x10004c8 + 0x01002b7c: e02e .. B 0x1002bdc ; list_sem + 196 + 0x01002b7e: 9812 .. LDR r0,[sp,#0x48] + 0x01002b80: f7fdfca2 .... BL rt_hw_interrupt_enable ; 0x10004c8 + 0x01002b84: 4634 4F MOV r4,r6 + 0x01002b86: 4620 F MOV r0,r4 + 0x01002b88: 3014 .0 ADDS r0,r0,#0x14 + 0x01002b8a: f001fcec .... BL rt_list_isempty ; 0x1004566 + 0x01002b8e: 2800 .( CMP r0,#0 + 0x01002b90: d115 .. BNE 0x1002bbe ; list_sem + 166 + 0x01002b92: 4620 F MOV r0,r4 + 0x01002b94: 3014 .0 ADDS r0,r0,#0x14 + 0x01002b96: f001fcfe .... BL rt_list_len ; 0x1004596 + 0x01002b9a: 9002 .. STR r0,[sp,#8] + 0x01002b9c: 8ba1 .. LDRH r1,[r4,#0x1c] + 0x01002b9e: 4623 #F MOV r3,r4 + 0x01002ba0: 2208 ." MOVS r2,#8 + 0x01002ba2: 9100 .. STR r1,[sp,#0] + 0x01002ba4: 9001 .. STR r0,[sp,#4] + 0x01002ba6: a022 ". ADR r0,{pc}+0x8a ; 0x1002c30 + 0x01002ba8: 9904 .. LDR r1,[sp,#0x10] + 0x01002baa: f001fc91 .... BL rt_kprintf ; 0x10044d0 + 0x01002bae: 4620 F MOV r0,r4 + 0x01002bb0: 3014 .0 ADDS r0,r0,#0x14 + 0x01002bb2: f004f911 .... BL show_wait_queue ; 0x1006dd8 + 0x01002bb6: a017 .. ADR r0,{pc}+0x5e ; 0x1002c14 + 0x01002bb8: f001fc8a .... BL rt_kprintf ; 0x10044d0 + 0x01002bbc: e00d .. B 0x1002bda ; list_sem + 194 + 0x01002bbe: 4620 F MOV r0,r4 + 0x01002bc0: 3014 .0 ADDS r0,r0,#0x14 + 0x01002bc2: f001fce8 .... BL rt_list_len ; 0x1004596 + 0x01002bc6: 9002 .. STR r0,[sp,#8] + 0x01002bc8: 8ba1 .. LDRH r1,[r4,#0x1c] + 0x01002bca: 4623 #F MOV r3,r4 + 0x01002bcc: 2208 ." MOVS r2,#8 + 0x01002bce: 9100 .. STR r1,[sp,#0] + 0x01002bd0: 9001 .. STR r0,[sp,#4] + 0x01002bd2: a01b .. ADR r0,{pc}+0x6e ; 0x1002c40 + 0x01002bd4: 9904 .. LDR r1,[sp,#0x10] + 0x01002bd6: f001fc7b ..{. BL rt_kprintf ; 0x10044d0 + 0x01002bda: bf00 .. NOP + 0x01002bdc: 1c6d m. ADDS r5,r5,#1 + 0x01002bde: 9811 .. LDR r0,[sp,#0x44] + 0x01002be0: 42a8 .B CMP r0,r5 + 0x01002be2: dcb9 .. BGT 0x1002b58 ; list_sem + 64 + 0x01002be4: 2f00 ./ CMP r7,#0 + 0x01002be6: d1b0 .. BNE 0x1002b4a ; list_sem + 50 + 0x01002be8: 2000 . MOVS r0,#0 + 0x01002bea: b013 .. ADD sp,sp,#0x4c + 0x01002bec: bdf0 .. POP {r4-r7,pc} + $d + 0x01002bee: 0000 .. DCW 0 + 0x01002bf0: 616d6573 sema DCD 1634559347 + 0x01002bf4: 726f6870 phor DCD 1919903856 + 0x01002bf8: 00000065 e... DCD 101 + 0x01002bfc: 2e2a2d25 %-*. DCD 774516005 + 0x01002c00: 20762073 s v DCD 544612467 + 0x01002c04: 75732020 su DCD 1970479136 + 0x01002c08: 6e657073 spen DCD 1852141683 + 0x01002c0c: 68742064 d th DCD 1752440932 + 0x01002c10: 64616572 read DCD 1684104562 + 0x01002c14: 0000000a .... DCD 10 + 0x01002c18: 2d2d2d20 --- DCD 757935392 + 0x01002c1c: 2d2d2d20 --- DCD 757935392 + 0x01002c20: 2d2d2d2d ---- DCD 757935405 + 0x01002c24: 2d2d2d2d ---- DCD 757935405 + 0x01002c28: 0a2d2d2d ---. DCD 170732845 + 0x01002c2c: 00000000 .... DCD 0 + 0x01002c30: 2e2a2d25 %-*. DCD 774516005 + 0x01002c34: 2520732a *s % DCD 622883626 + 0x01002c38: 20643330 03d DCD 543437616 + 0x01002c3c: 003a6425 %d:. DCD 3826725 + 0x01002c40: 2e2a2d25 %-*. DCD 774516005 + 0x01002c44: 2520732a *s % DCD 622883626 + 0x01002c48: 20643330 03d DCD 543437616 + 0x01002c4c: 000a6425 %d.. DCD 680997 + $t + i.list_thread + list_thread + 0x01002c50: b5f0 .. PUSH {r4-r7,lr} + 0x01002c52: b0b7 .. SUB sp,sp,#0xdc + 0x01002c54: 2000 . MOVS r0,#0 + 0x01002c56: 9028 (. STR r0,[sp,#0xa0] + 0x01002c58: a049 I. ADR r0,{pc}+0x128 ; 0x1002d80 + 0x01002c5a: 9027 '. STR r0,[sp,#0x9c] + 0x01002c5c: 2308 .# MOVS r3,#8 + 0x01002c5e: aa29 ). ADD r2,sp,#0xa4 + 0x01002c60: 2101 .! MOVS r1,#1 + 0x01002c62: a831 1. ADD r0,sp,#0xc4 + 0x01002c64: f7fffb9e .... BL list_find_init ; 0x10023a4 + 0x01002c68: 2008 . MOVS r0,#8 + 0x01002c6a: 9026 &. STR r0,[sp,#0x98] + 0x01002c6c: 4846 FH LDR r0,[pc,#280] ; [0x1002d88] = 0x1007d60 + 0x01002c6e: 9a27 '. LDR r2,[sp,#0x9c] + 0x01002c70: 9926 &. LDR r1,[sp,#0x98] + 0x01002c72: f001fc2d ..-. BL rt_kprintf ; 0x10044d0 + 0x01002c76: 9826 &. LDR r0,[sp,#0x98] + 0x01002c78: f000fb38 ..8. BL object_split ; 0x10032ec + 0x01002c7c: a043 C. ADR r0,{pc}+0x110 ; 0x1002d8c + 0x01002c7e: f001fc27 ..'. BL rt_kprintf ; 0x10044d0 + 0x01002c82: bf00 .. NOP + 0x01002c84: a931 1. ADD r1,sp,#0xc4 + 0x01002c86: 9828 (. LDR r0,[sp,#0xa0] + 0x01002c88: f7fffba0 .... BL list_get_next ; 0x10023cc + 0x01002c8c: 9028 (. STR r0,[sp,#0xa0] + 0x01002c8e: 2000 . MOVS r0,#0 + 0x01002c90: 9025 %. STR r0,[sp,#0x94] + 0x01002c92: e06b k. B 0x1002d6c ; list_thread + 284 + 0x01002c94: 9825 %. LDR r0,[sp,#0x94] + 0x01002c96: 0080 .. LSLS r0,r0,#2 + 0x01002c98: a929 ). ADD r1,sp,#0xa4 + 0x01002c9a: 5808 .X LDR r0,[r1,r0] + 0x01002c9c: 4605 .F MOV r5,r0 + 0x01002c9e: 3d0c .= SUBS r5,r5,#0xc + 0x01002ca0: f7fdfc0e .... BL rt_hw_interrupt_disable ; 0x10004c0 + 0x01002ca4: 9036 6. STR r0,[sp,#0xd8] + 0x01002ca6: 7a28 (z LDRB r0,[r5,#8] + 0x01002ca8: 2180 .! MOVS r1,#0x80 + 0x01002caa: 4388 .C BICS r0,r0,r1 + 0x01002cac: a930 0. ADD r1,sp,#0xc0 + 0x01002cae: 7b09 .{ LDRB r1,[r1,#0xc] + 0x01002cb0: 4288 .B CMP r0,r1 + 0x01002cb2: d003 .. BEQ 0x1002cbc ; list_thread + 108 + 0x01002cb4: 9836 6. LDR r0,[sp,#0xd8] + 0x01002cb6: f7fdfc07 .... BL rt_hw_interrupt_enable ; 0x10004c8 + 0x01002cba: e054 T. B 0x1002d66 ; list_thread + 278 + 0x01002cbc: 2280 ." MOVS r2,#0x80 + 0x01002cbe: 4629 )F MOV r1,r5 + 0x01002cc0: a805 .. ADD r0,sp,#0x14 + 0x01002cc2: f001fdef .... BL rt_memcpy ; 0x10048a4 + 0x01002cc6: 9836 6. LDR r0,[sp,#0xd8] + 0x01002cc8: f7fdfbfe .... BL rt_hw_interrupt_enable ; 0x10004c8 + 0x01002ccc: 462c ,F MOV r4,r5 + 0x01002cce: 2035 5 MOVS r0,#0x35 + 0x01002cd0: 5d00 .] LDRB r0,[r0,r4] + 0x01002cd2: 4623 #F MOV r3,r4 + 0x01002cd4: 2208 ." MOVS r2,#8 + 0x01002cd6: 9000 .. STR r0,[sp,#0] + 0x01002cd8: a03c <. ADR r0,{pc}+0xf4 ; 0x1002dcc + 0x01002cda: 9926 &. LDR r1,[sp,#0x98] + 0x01002cdc: f001fbf8 .... BL rt_kprintf ; 0x10044d0 + 0x01002ce0: 2034 4 MOVS r0,#0x34 + 0x01002ce2: 5d00 .] LDRB r0,[r0,r4] + 0x01002ce4: 0746 F. LSLS r6,r0,#29 + 0x01002ce6: 0f76 v. LSRS r6,r6,#29 + 0x01002ce8: 2e01 .. CMP r6,#1 + 0x01002cea: d103 .. BNE 0x1002cf4 ; list_thread + 164 + 0x01002cec: a03a :. ADR r0,{pc}+0xec ; 0x1002dd8 + 0x01002cee: f001fbef .... BL rt_kprintf ; 0x10044d0 + 0x01002cf2: e016 .. B 0x1002d22 ; list_thread + 210 + 0x01002cf4: 2e02 .. CMP r6,#2 + 0x01002cf6: d103 .. BNE 0x1002d00 ; list_thread + 176 + 0x01002cf8: a03a :. ADR r0,{pc}+0xec ; 0x1002de4 + 0x01002cfa: f001fbe9 .... BL rt_kprintf ; 0x10044d0 + 0x01002cfe: e010 .. B 0x1002d22 ; list_thread + 210 + 0x01002d00: 2e00 .. CMP r6,#0 + 0x01002d02: d103 .. BNE 0x1002d0c ; list_thread + 188 + 0x01002d04: a03a :. ADR r0,{pc}+0xec ; 0x1002df0 + 0x01002d06: f001fbe3 .... BL rt_kprintf ; 0x10044d0 + 0x01002d0a: e00a .. B 0x1002d22 ; list_thread + 210 + 0x01002d0c: 2e04 .. CMP r6,#4 + 0x01002d0e: d103 .. BNE 0x1002d18 ; list_thread + 200 + 0x01002d10: a03a :. ADR r0,{pc}+0xec ; 0x1002dfc + 0x01002d12: f001fbdd .... BL rt_kprintf ; 0x10044d0 + 0x01002d16: e004 .. B 0x1002d22 ; list_thread + 210 + 0x01002d18: 2e03 .. CMP r6,#3 + 0x01002d1a: d102 .. BNE 0x1002d22 ; list_thread + 210 + 0x01002d1c: a03a :. ADR r0,{pc}+0xec ; 0x1002e08 + 0x01002d1e: f001fbd7 .... BL rt_kprintf ; 0x10044d0 + 0x01002d22: 6aa7 .j LDR r7,[r4,#0x28] + 0x01002d24: e000 .. B 0x1002d28 ; list_thread + 216 + 0x01002d26: 1c7f .. ADDS r7,r7,#1 + 0x01002d28: 7838 8x LDRB r0,[r7,#0] + 0x01002d2a: 2823 #( CMP r0,#0x23 + 0x01002d2c: d0fb .. BEQ 0x1002d26 ; list_thread + 214 + 0x01002d2e: 6aa3 .j LDR r3,[r4,#0x28] + 0x01002d30: 1afb .. SUBS r3,r7,r3 + 0x01002d32: 6ae2 .j LDR r2,[r4,#0x2c] + 0x01002d34: 1ad2 .. SUBS r2,r2,r3 + 0x01002d36: 2364 d# MOVS r3,#0x64 + 0x01002d38: 435a ZC MULS r2,r3,r2 + 0x01002d3a: 4610 .F MOV r0,r2 + 0x01002d3c: 6ae1 .j LDR r1,[r4,#0x2c] + 0x01002d3e: f7fdfd95 .... BL __aeabi_uidiv ; 0x100086c + 0x01002d42: 9004 .. STR r0,[sp,#0x10] + 0x01002d44: 6b21 !k LDR r1,[r4,#0x30] + 0x01002d46: 6ca0 .l LDR r0,[r4,#0x48] + 0x01002d48: 9101 .. STR r1,[sp,#4] + 0x01002d4a: 9000 .. STR r0,[sp,#0] + 0x01002d4c: 69e1 .i LDR r1,[r4,#0x1c] + 0x01002d4e: 6aa0 .j LDR r0,[r4,#0x28] + 0x01002d50: 1a40 @. SUBS r0,r0,r1 + 0x01002d52: 6ae1 .j LDR r1,[r4,#0x2c] + 0x01002d54: 1840 @. ADDS r0,r0,r1 + 0x01002d56: 9003 .. STR r0,[sp,#0xc] + 0x01002d58: 6ae2 .j LDR r2,[r4,#0x2c] + 0x01002d5a: 4601 .F MOV r1,r0 + 0x01002d5c: a02d -. ADR r0,{pc}+0xb8 ; 0x1002e14 + 0x01002d5e: 9b04 .. LDR r3,[sp,#0x10] + 0x01002d60: f001fbb6 .... BL rt_kprintf ; 0x10044d0 + 0x01002d64: bf00 .. NOP + 0x01002d66: 9825 %. LDR r0,[sp,#0x94] + 0x01002d68: 1c40 @. ADDS r0,r0,#1 + 0x01002d6a: 9025 %. STR r0,[sp,#0x94] + 0x01002d6c: 9935 5. LDR r1,[sp,#0xd4] + 0x01002d6e: 9825 %. LDR r0,[sp,#0x94] + 0x01002d70: 4281 .B CMP r1,r0 + 0x01002d72: dc8f .. BGT 0x1002c94 ; list_thread + 68 + 0x01002d74: 9828 (. LDR r0,[sp,#0xa0] + 0x01002d76: 2800 .( CMP r0,#0 + 0x01002d78: d184 .. BNE 0x1002c84 ; list_thread + 52 + 0x01002d7a: b037 7. ADD sp,sp,#0xdc + 0x01002d7c: bdf0 .. POP {r4-r7,pc} + $d + 0x01002d7e: 0000 .. DCW 0 + 0x01002d80: 65726874 thre DCD 1701996660 + 0x01002d84: 00006461 ad.. DCD 25697 + 0x01002d88: 01007d60 `}.. DCD 16809312 + 0x01002d8c: 2d2d2d20 --- DCD 757935392 + 0x01002d90: 2d2d2020 -- DCD 757932064 + 0x01002d94: 2d2d2d2d ---- DCD 757935405 + 0x01002d98: 2d2d202d - -- DCD 757932077 + 0x01002d9c: 2d2d2d2d ---- DCD 757935405 + 0x01002da0: 2d2d2d2d ---- DCD 757935405 + 0x01002da4: 2d2d2d20 --- DCD 757935392 + 0x01002da8: 2d2d2d2d ---- DCD 757935405 + 0x01002dac: 202d2d2d --- DCD 539831597 + 0x01002db0: 2d2d2d20 --- DCD 757935392 + 0x01002db4: 202d2d2d --- DCD 539831597 + 0x01002db8: 2d2d2d20 --- DCD 757935392 + 0x01002dbc: 2d2d2d2d ---- DCD 757935405 + 0x01002dc0: 202d2d2d --- DCD 539831597 + 0x01002dc4: 0a2d2d2d ---. DCD 170732845 + 0x01002dc8: 00000000 .... DCD 0 + 0x01002dcc: 2e2a2d25 %-*. DCD 774516005 + 0x01002dd0: 2520732a *s % DCD 622883626 + 0x01002dd4: 00206433 3d . DCD 2122803 + 0x01002dd8: 61657220 rea DCD 1634038304 + 0x01002ddc: 20207964 dy DCD 538999140 + 0x01002de0: 00000000 .... DCD 0 + 0x01002de4: 73757320 sus DCD 1937077024 + 0x01002de8: 646e6570 pend DCD 1684956528 + 0x01002dec: 00000000 .... DCD 0 + 0x01002df0: 696e6920 ini DCD 1768843552 + 0x01002df4: 20202074 t DCD 538976372 + 0x01002df8: 00000000 .... DCD 0 + 0x01002dfc: 6f6c6320 clo DCD 1869374240 + 0x01002e00: 20206573 se DCD 538994035 + 0x01002e04: 00000000 .... DCD 0 + 0x01002e08: 6e757220 run DCD 1853190688 + 0x01002e0c: 676e696e ning DCD 1735289198 + 0x01002e10: 00000000 .... DCD 0 + 0x01002e14: 25783020 0x% DCD 628633632 + 0x01002e18: 20783830 08x DCD 544749616 + 0x01002e1c: 30257830 0x%0 DCD 807761968 + 0x01002e20: 20207838 8x DCD 538998840 + 0x01002e24: 30252020 %0 DCD 807739424 + 0x01002e28: 25256432 2d%% DCD 623207474 + 0x01002e2c: 30202020 0 DCD 807411744 + 0x01002e30: 38302578 x%08 DCD 942679416 + 0x01002e34: 30252078 x %0 DCD 807739512 + 0x01002e38: 000a6433 3d.. DCD 681011 + $t + i.list_timer + list_timer + 0x01002e3c: b5f0 .. PUSH {r4-r7,lr} + 0x01002e3e: b093 .. SUB sp,sp,#0x4c + 0x01002e40: 2700 .' MOVS r7,#0 + 0x01002e42: a02d -. ADR r0,{pc}+0xb6 ; 0x1002ef8 + 0x01002e44: 9003 .. STR r0,[sp,#0xc] + 0x01002e46: 2308 .# MOVS r3,#8 + 0x01002e48: aa05 .. ADD r2,sp,#0x14 + 0x01002e4a: 210a .! MOVS r1,#0xa + 0x01002e4c: a80d .. ADD r0,sp,#0x34 + 0x01002e4e: f7fffaa9 .... BL list_find_init ; 0x10023a4 + 0x01002e52: 2008 . MOVS r0,#8 + 0x01002e54: 9004 .. STR r0,[sp,#0x10] + 0x01002e56: a02a *. ADR r0,{pc}+0xaa ; 0x1002f00 + 0x01002e58: 9a03 .. LDR r2,[sp,#0xc] + 0x01002e5a: 9904 .. LDR r1,[sp,#0x10] + 0x01002e5c: f001fb38 ..8. BL rt_kprintf ; 0x10044d0 + 0x01002e60: 9804 .. LDR r0,[sp,#0x10] + 0x01002e62: f000fa43 ..C. BL object_split ; 0x10032ec + 0x01002e66: a030 0. ADR r0,{pc}+0xc2 ; 0x1002f28 + 0x01002e68: f001fb32 ..2. BL rt_kprintf ; 0x10044d0 + 0x01002e6c: bf00 .. NOP + 0x01002e6e: a90d .. ADD r1,sp,#0x34 + 0x01002e70: 4638 8F MOV r0,r7 + 0x01002e72: f7fffaab .... BL list_get_next ; 0x10023cc + 0x01002e76: 4607 .F MOV r7,r0 + 0x01002e78: 2600 .& MOVS r6,#0 + 0x01002e7a: e02e .. B 0x1002eda ; list_timer + 158 + 0x01002e7c: 00b0 .. LSLS r0,r6,#2 + 0x01002e7e: a905 .. ADD r1,sp,#0x14 + 0x01002e80: 5808 .X LDR r0,[r1,r0] + 0x01002e82: 4604 .F MOV r4,r0 + 0x01002e84: 3c0c .< SUBS r4,r4,#0xc + 0x01002e86: f7fdfb1b .... BL rt_hw_interrupt_disable ; 0x10004c0 + 0x01002e8a: 9012 .. STR r0,[sp,#0x48] + 0x01002e8c: 7a20 z LDRB r0,[r4,#8] + 0x01002e8e: 2180 .! MOVS r1,#0x80 + 0x01002e90: 4388 .C BICS r0,r0,r1 + 0x01002e92: a908 .. ADD r1,sp,#0x20 + 0x01002e94: 7f09 .. LDRB r1,[r1,#0x1c] + 0x01002e96: 4288 .B CMP r0,r1 + 0x01002e98: d003 .. BEQ 0x1002ea2 ; list_timer + 102 + 0x01002e9a: 9812 .. LDR r0,[sp,#0x48] + 0x01002e9c: f7fdfb14 .... BL rt_hw_interrupt_enable ; 0x10004c8 + 0x01002ea0: e01a .. B 0x1002ed8 ; list_timer + 156 + 0x01002ea2: 9812 .. LDR r0,[sp,#0x48] + 0x01002ea4: f7fdfb10 .... BL rt_hw_interrupt_enable ; 0x10004c8 + 0x01002ea8: 4625 %F MOV r5,r4 + 0x01002eaa: 6aa9 .j LDR r1,[r5,#0x28] + 0x01002eac: 6a68 hj LDR r0,[r5,#0x24] + 0x01002eae: 462b +F MOV r3,r5 + 0x01002eb0: 2208 ." MOVS r2,#8 + 0x01002eb2: 9101 .. STR r1,[sp,#4] + 0x01002eb4: 9000 .. STR r0,[sp,#0] + 0x01002eb6: a025 %. ADR r0,{pc}+0x96 ; 0x1002f4c + 0x01002eb8: 9904 .. LDR r1,[sp,#0x10] + 0x01002eba: f001fb09 .... BL rt_kprintf ; 0x10044d0 + 0x01002ebe: 7a68 hz LDRB r0,[r5,#9] + 0x01002ec0: 07c0 .. LSLS r0,r0,#31 + 0x01002ec2: 0fc0 .. LSRS r0,r0,#31 + 0x01002ec4: 2800 .( CMP r0,#0 + 0x01002ec6: d003 .. BEQ 0x1002ed0 ; list_timer + 148 + 0x01002ec8: a026 &. ADR r0,{pc}+0x9c ; 0x1002f64 + 0x01002eca: f001fb01 .... BL rt_kprintf ; 0x10044d0 + 0x01002ece: e002 .. B 0x1002ed6 ; list_timer + 154 + 0x01002ed0: a027 '. ADR r0,{pc}+0xa0 ; 0x1002f70 + 0x01002ed2: f001fafd .... BL rt_kprintf ; 0x10044d0 + 0x01002ed6: bf00 .. NOP + 0x01002ed8: 1c76 v. ADDS r6,r6,#1 + 0x01002eda: 9811 .. LDR r0,[sp,#0x44] + 0x01002edc: 42b0 .B CMP r0,r6 + 0x01002ede: dccd .. BGT 0x1002e7c ; list_timer + 64 + 0x01002ee0: 2f00 ./ CMP r7,#0 + 0x01002ee2: d1c4 .. BNE 0x1002e6e ; list_timer + 50 + 0x01002ee4: f003f9fc .... BL rt_tick_get ; 0x10062e0 + 0x01002ee8: 4604 .F MOV r4,r0 + 0x01002eea: 4621 !F MOV r1,r4 + 0x01002eec: a024 $. ADR r0,{pc}+0x94 ; 0x1002f80 + 0x01002eee: f001faef .... BL rt_kprintf ; 0x10044d0 + 0x01002ef2: 2000 . MOVS r0,#0 + 0x01002ef4: b013 .. ADD sp,sp,#0x4c + 0x01002ef6: bdf0 .. POP {r4-r7,pc} + $d + 0x01002ef8: 656d6974 time DCD 1701669236 + 0x01002efc: 00000072 r... DCD 114 + 0x01002f00: 2e2a2d25 %-*. DCD 774516005 + 0x01002f04: 70202073 s p DCD 1881153651 + 0x01002f08: 6f697265 erio DCD 1869181541 + 0x01002f0c: 20636964 dic DCD 543385956 + 0x01002f10: 69742020 ti DCD 1769218080 + 0x01002f14: 756f656d meou DCD 1970234733 + 0x01002f18: 20202074 t DCD 538976372 + 0x01002f1c: 20202020 DCD 538976288 + 0x01002f20: 67616c66 flag DCD 1734437990 + 0x01002f24: 0000000a .... DCD 10 + 0x01002f28: 2d2d2d20 --- DCD 757935392 + 0x01002f2c: 2d2d2d2d ---- DCD 757935405 + 0x01002f30: 202d2d2d --- DCD 539831597 + 0x01002f34: 2d2d2d2d ---- DCD 757935405 + 0x01002f38: 2d2d2d2d ---- DCD 757935405 + 0x01002f3c: 2d202d2d -- - DCD 757083437 + 0x01002f40: 2d2d2d2d ---- DCD 757935405 + 0x01002f44: 2d2d2d2d ---- DCD 757935405 + 0x01002f48: 000a2d2d --.. DCD 666925 + 0x01002f4c: 2e2a2d25 %-*. DCD 774516005 + 0x01002f50: 3020732a *s 0 DCD 807433002 + 0x01002f54: 38302578 x%08 DCD 942679416 + 0x01002f58: 78302078 x 0x DCD 2016419960 + 0x01002f5c: 78383025 %08x DCD 2016948261 + 0x01002f60: 00000020 ... DCD 32 + 0x01002f64: 69746361 acti DCD 1769235297 + 0x01002f68: 65746176 vate DCD 1702125942 + 0x01002f6c: 00000a64 d... DCD 2660 + 0x01002f70: 63616564 deac DCD 1667327332 + 0x01002f74: 61766974 tiva DCD 1635150196 + 0x01002f78: 0a646574 ted. DCD 174351732 + 0x01002f7c: 00000000 .... DCD 0 + 0x01002f80: 72727563 curr DCD 1920103779 + 0x01002f84: 20746e65 ent DCD 544501349 + 0x01002f88: 6b636974 tick DCD 1801677172 + 0x01002f8c: 2578303a :0x% DCD 628633658 + 0x01002f90: 0a783830 08x. DCD 175650864 + 0x01002f94: 00000000 .... DCD 0 + $t + i.main + $Super$$main + 0x01002f98: b510 .. PUSH {r4,lr} + 0x01002f9a: 2401 .$ MOVS r4,#1 + 0x01002f9c: 2100 .! MOVS r1,#0 + 0x01002f9e: 2002 . MOVS r0,#2 + 0x01002fa0: f002f800 .... BL rt_pin_mode ; 0x1004fa4 + 0x01002fa4: e00f .. B 0x1002fc6 ; $Super$$main + 46 + 0x01002fa6: 2101 .! MOVS r1,#1 + 0x01002fa8: 2002 . MOVS r0,#2 + 0x01002faa: f002f81f .... BL rt_pin_write ; 0x1004fec + 0x01002fae: 20ff . MOVS r0,#0xff + 0x01002fb0: 30f5 .0 ADDS r0,r0,#0xf5 + 0x01002fb2: f002ff9b .... BL rt_thread_mdelay ; 0x1005eec + 0x01002fb6: 2100 .! MOVS r1,#0 + 0x01002fb8: 2002 . MOVS r0,#2 + 0x01002fba: f002f817 .... BL rt_pin_write ; 0x1004fec + 0x01002fbe: 20ff . MOVS r0,#0xff + 0x01002fc0: 30f5 .0 ADDS r0,r0,#0xf5 + 0x01002fc2: f002ff93 .... BL rt_thread_mdelay ; 0x1005eec + 0x01002fc6: 4620 F MOV r0,r4 + 0x01002fc8: 1c64 d. ADDS r4,r4,#1 + 0x01002fca: 2800 .( CMP r0,#0 + 0x01002fcc: d1eb .. BNE 0x1002fa6 ; $Super$$main + 14 + 0x01002fce: bd10 .. POP {r4,pc} + i.main_thread_entry + main_thread_entry + 0x01002fd0: b510 .. PUSH {r4,lr} + 0x01002fd2: 4604 .F MOV r4,r0 + 0x01002fd4: f000fc6e ..n. BL rt_components_init ; 0x10038b4 + 0x01002fd8: f7ffffde .... BL $Super$$main ; 0x1002f98 + 0x01002fdc: bd10 .. POP {r4,pc} + 0x01002fde: 0000 .. MOVS r0,r0 + i.memheaptrace + memheaptrace + 0x01002fe0: b570 p. PUSH {r4-r6,lr} + 0x01002fe2: 2007 . MOVS r0,#7 + 0x01002fe4: f001fefa .... BL rt_object_get_length ; 0x1004ddc + 0x01002fe8: 4605 .F MOV r5,r0 + 0x01002fea: 2d00 .- CMP r5,#0 + 0x01002fec: dd1f .. BLE 0x100302e ; memheaptrace + 78 + 0x01002fee: 00a8 .. LSLS r0,r5,#2 + 0x01002ff0: f001faf6 .... BL rt_malloc ; 0x10045e0 + 0x01002ff4: 4604 .F MOV r4,r0 + 0x01002ff6: 2c00 ., CMP r4,#0 + 0x01002ff8: d100 .. BNE 0x1002ffc ; memheaptrace + 28 + 0x01002ffa: bd70 p. POP {r4-r6,pc} + 0x01002ffc: f7fffb1c .... BL list_memheap ; 0x1002638 + 0x01003000: 2118 .! MOVS r1,#0x18 + 0x01003002: a00c .. ADR r0,{pc}+0x32 ; 0x1003034 + 0x01003004: f001fa64 ..d. BL rt_kprintf ; 0x10044d0 + 0x01003008: 462a *F MOV r2,r5 + 0x0100300a: 4621 !F MOV r1,r4 + 0x0100300c: 2007 . MOVS r0,#7 + 0x0100300e: f001ff00 .... BL rt_object_get_pointers ; 0x1004e12 + 0x01003012: 4605 .F MOV r5,r0 + 0x01003014: 2600 .& MOVS r6,#0 + 0x01003016: e004 .. B 0x1003022 ; memheaptrace + 66 + 0x01003018: 00b1 .. LSLS r1,r6,#2 + 0x0100301a: 5860 `X LDR r0,[r4,r1] + 0x0100301c: f001fc72 ..r. BL rt_memheap_dump ; 0x1004904 + 0x01003020: 1c76 v. ADDS r6,r6,#1 + 0x01003022: 42ae .B CMP r6,r5 + 0x01003024: dbf8 .. BLT 0x1003018 ; memheaptrace + 56 + 0x01003026: 4620 F MOV r0,r4 + 0x01003028: f000ff52 ..R. BL rt_free ; 0x1003ed0 + 0x0100302c: bf00 .. NOP + 0x0100302e: 2000 . MOVS r0,#0 + 0x01003030: e7e3 .. B 0x1002ffa ; memheaptrace + 26 + $d + 0x01003032: 0000 .. DCW 0 + 0x01003034: 686d656d memh DCD 1751999853 + 0x01003038: 20706165 eap DCD 544235877 + 0x0100303c: 64616568 head DCD 1684104552 + 0x01003040: 73207265 er s DCD 1931506277 + 0x01003044: 3a657a69 ize: DCD 979729001 + 0x01003048: 0a642520 %d. DCD 174335264 + 0x0100304c: 00000000 .... DCD 0 + $t + i.msh_auto_complete + msh_auto_complete + 0x01003050: b5f1 .. PUSH {r0,r4-r7,lr} + 0x01003052: b082 .. SUB sp,sp,#8 + 0x01003054: 2600 .& MOVS r6,#0 + 0x01003056: 2000 . MOVS r0,#0 + 0x01003058: 9001 .. STR r0,[sp,#4] + 0x0100305a: 9802 .. LDR r0,[sp,#8] + 0x0100305c: 7800 .x LDRB r0,[r0,#0] + 0x0100305e: 2800 .( CMP r0,#0 + 0x01003060: d104 .. BNE 0x100306c ; msh_auto_complete + 28 + 0x01003062: 2100 .! MOVS r1,#0 + 0x01003064: 4608 .F MOV r0,r1 + 0x01003066: f000f893 .... BL msh_help ; 0x1003190 + 0x0100306a: bdfe .. POP {r1-r7,pc} + 0x0100306c: 4818 .H LDR r0,[pc,#96] ; [0x10030d0] = 0x20014 + 0x0100306e: 6805 .h LDR r5,[r0,#0] + 0x01003070: e01f .. B 0x10030b2 ; msh_auto_complete + 98 + 0x01003072: 682f /h LDR r7,[r5,#0] + 0x01003074: 9802 .. LDR r0,[sp,#8] + 0x01003076: f7fdfae3 .... BL strlen ; 0x1000640 + 0x0100307a: 4602 .F MOV r2,r0 + 0x0100307c: 4639 9F MOV r1,r7 + 0x0100307e: 9000 .. STR r0,[sp,#0] + 0x01003080: 9802 .. LDR r0,[sp,#8] + 0x01003082: f7fdfaff .... BL strncmp ; 0x1000684 + 0x01003086: 2800 .( CMP r0,#0 + 0x01003088: d112 .. BNE 0x10030b0 ; msh_auto_complete + 96 + 0x0100308a: 2e00 .. CMP r6,#0 + 0x0100308c: d104 .. BNE 0x1003098 ; msh_auto_complete + 72 + 0x0100308e: 9701 .. STR r7,[sp,#4] + 0x01003090: 9801 .. LDR r0,[sp,#4] + 0x01003092: f7fdfad5 .... BL strlen ; 0x1000640 + 0x01003096: 4606 .F MOV r6,r0 + 0x01003098: 4639 9F MOV r1,r7 + 0x0100309a: 9801 .. LDR r0,[sp,#4] + 0x0100309c: f003feca .... BL str_common ; 0x1006e34 + 0x010030a0: 4604 .F MOV r4,r0 + 0x010030a2: 42b4 .B CMP r4,r6 + 0x010030a4: da00 .. BGE 0x10030a8 ; msh_auto_complete + 88 + 0x010030a6: 4626 &F MOV r6,r4 + 0x010030a8: 4639 9F MOV r1,r7 + 0x010030aa: a00a .. ADR r0,{pc}+0x2a ; 0x10030d4 + 0x010030ac: f001fa10 .... BL rt_kprintf ; 0x10044d0 + 0x010030b0: 350c .5 ADDS r5,r5,#0xc + 0x010030b2: 4809 .H LDR r0,[pc,#36] ; [0x10030d8] = 0x20018 + 0x010030b4: 6800 .h LDR r0,[r0,#0] + 0x010030b6: 4285 .B CMP r5,r0 + 0x010030b8: d3db .. BCC 0x1003072 ; msh_auto_complete + 34 + 0x010030ba: 9801 .. LDR r0,[sp,#4] + 0x010030bc: 2800 .( CMP r0,#0 + 0x010030be: d004 .. BEQ 0x10030ca ; msh_auto_complete + 122 + 0x010030c0: 4632 2F MOV r2,r6 + 0x010030c2: 9901 .. LDR r1,[sp,#4] + 0x010030c4: 9802 .. LDR r0,[sp,#8] + 0x010030c6: f002fd38 ..8. BL rt_strncpy ; 0x1005b3a + 0x010030ca: bf00 .. NOP + 0x010030cc: e7cd .. B 0x100306a ; msh_auto_complete + 26 + $d + 0x010030ce: 0000 .. DCW 0 + 0x010030d0: 00020014 .... DCD 131092 + 0x010030d4: 000a7325 %s.. DCD 684837 + 0x010030d8: 00020018 .... DCD 131096 + $t + i.msh_exec + msh_exec + 0x010030dc: b538 8. PUSH {r3-r5,lr} + 0x010030de: 4604 .F MOV r4,r0 + 0x010030e0: 460d .F MOV r5,r1 + 0x010030e2: e001 .. B 0x10030e8 ; msh_exec + 12 + 0x010030e4: 1c64 d. ADDS r4,r4,#1 + 0x010030e6: 1e6d m. SUBS r5,r5,#1 + 0x010030e8: 2d00 .- CMP r5,#0 + 0x010030ea: d005 .. BEQ 0x10030f8 ; msh_exec + 28 + 0x010030ec: 7820 x LDRB r0,[r4,#0] + 0x010030ee: 2820 ( CMP r0,#0x20 + 0x010030f0: d0f8 .. BEQ 0x10030e4 ; msh_exec + 8 + 0x010030f2: 7820 x LDRB r0,[r4,#0] + 0x010030f4: 2809 .( CMP r0,#9 + 0x010030f6: d0f5 .. BEQ 0x10030e4 ; msh_exec + 8 + 0x010030f8: 2d00 .- CMP r5,#0 + 0x010030fa: d101 .. BNE 0x1003100 ; msh_exec + 36 + 0x010030fc: 2000 . MOVS r0,#0 + 0x010030fe: bd38 8. POP {r3-r5,pc} + 0x01003100: 466a jF MOV r2,sp + 0x01003102: 4629 )F MOV r1,r5 + 0x01003104: 4620 F MOV r0,r4 + 0x01003106: f7fef80d .... BL _msh_exec_cmd ; 0x1001124 + 0x0100310a: 2800 .( CMP r0,#0 + 0x0100310c: d101 .. BNE 0x1003112 ; msh_exec + 54 + 0x0100310e: 9800 .. LDR r0,[sp,#0] + 0x01003110: e7f5 .. B 0x10030fe ; msh_exec + 34 + 0x01003112: 4620 F MOV r0,r4 + 0x01003114: e000 .. B 0x1003118 ; msh_exec + 60 + 0x01003116: 1c40 @. ADDS r0,r0,#1 + 0x01003118: 7801 .x LDRB r1,[r0,#0] + 0x0100311a: 2920 ) CMP r1,#0x20 + 0x0100311c: d002 .. BEQ 0x1003124 ; msh_exec + 72 + 0x0100311e: 7801 .x LDRB r1,[r0,#0] + 0x01003120: 2900 .) CMP r1,#0 + 0x01003122: d1f8 .. BNE 0x1003116 ; msh_exec + 58 + 0x01003124: 2100 .! MOVS r1,#0 + 0x01003126: 7001 .p STRB r1,[r0,#0] + 0x01003128: 4621 !F MOV r1,r4 + 0x0100312a: a003 .. ADR r0,{pc}+0xe ; 0x1003138 + 0x0100312c: f001f9d0 .... BL rt_kprintf ; 0x10044d0 + 0x01003130: 2000 . MOVS r0,#0 + 0x01003132: 43c0 .C MVNS r0,r0 + 0x01003134: e7e3 .. B 0x10030fe ; msh_exec + 34 + $d + 0x01003136: 0000 .. DCW 0 + 0x01003138: 203a7325 %s: DCD 540701477 + 0x0100313c: 6d6d6f63 comm DCD 1835888483 + 0x01003140: 20646e61 and DCD 543452769 + 0x01003144: 20746f6e not DCD 544501614 + 0x01003148: 6e756f66 foun DCD 1853189990 + 0x0100314c: 000a2e64 d... DCD 667236 + $t + i.msh_get_cmd + msh_get_cmd + 0x01003150: b5f8 .. PUSH {r3-r7,lr} + 0x01003152: 4606 .F MOV r6,r0 + 0x01003154: 460d .F MOV r5,r1 + 0x01003156: 2700 .' MOVS r7,#0 + 0x01003158: 480b .H LDR r0,[pc,#44] ; [0x1003188] = 0x20014 + 0x0100315a: 6804 .h LDR r4,[r0,#0] + 0x0100315c: e00d .. B 0x100317a ; msh_get_cmd + 42 + 0x0100315e: 462a *F MOV r2,r5 + 0x01003160: 4631 1F MOV r1,r6 + 0x01003162: 6820 h LDR r0,[r4,#0] + 0x01003164: f7fdfa8e .... BL strncmp ; 0x1000684 + 0x01003168: 2800 .( CMP r0,#0 + 0x0100316a: d105 .. BNE 0x1003178 ; msh_get_cmd + 40 + 0x0100316c: 6820 h LDR r0,[r4,#0] + 0x0100316e: 5d40 @] LDRB r0,[r0,r5] + 0x01003170: 2800 .( CMP r0,#0 + 0x01003172: d101 .. BNE 0x1003178 ; msh_get_cmd + 40 + 0x01003174: 68a7 .h LDR r7,[r4,#8] + 0x01003176: e004 .. B 0x1003182 ; msh_get_cmd + 50 + 0x01003178: 340c .4 ADDS r4,r4,#0xc + 0x0100317a: 4804 .H LDR r0,[pc,#16] ; [0x100318c] = 0x20018 + 0x0100317c: 6800 .h LDR r0,[r0,#0] + 0x0100317e: 4284 .B CMP r4,r0 + 0x01003180: d3ed .. BCC 0x100315e ; msh_get_cmd + 14 + 0x01003182: bf00 .. NOP + 0x01003184: 4638 8F MOV r0,r7 + 0x01003186: bdf8 .. POP {r3-r7,pc} + $d + 0x01003188: 00020014 .... DCD 131092 + 0x0100318c: 00020018 .... DCD 131096 + $t + i.msh_help + msh_help + 0x01003190: b570 p. PUSH {r4-r6,lr} + 0x01003192: 4605 .F MOV r5,r0 + 0x01003194: 460e .F MOV r6,r1 + 0x01003196: a00a .. ADR r0,{pc}+0x2a ; 0x10031c0 + 0x01003198: f001f99a .... BL rt_kprintf ; 0x10044d0 + 0x0100319c: 480f .H LDR r0,[pc,#60] ; [0x10031dc] = 0x20014 + 0x0100319e: 6804 .h LDR r4,[r0,#0] + 0x010031a0: e005 .. B 0x10031ae ; msh_help + 30 + 0x010031a2: a00f .. ADR r0,{pc}+0x3e ; 0x10031e0 + 0x010031a4: 6862 bh LDR r2,[r4,#4] + 0x010031a6: 6821 !h LDR r1,[r4,#0] + 0x010031a8: f001f992 .... BL rt_kprintf ; 0x10044d0 + 0x010031ac: 340c .4 ADDS r4,r4,#0xc + 0x010031ae: 480f .H LDR r0,[pc,#60] ; [0x10031ec] = 0x20018 + 0x010031b0: 6800 .h LDR r0,[r0,#0] + 0x010031b2: 4284 .B CMP r4,r0 + 0x010031b4: d3f5 .. BCC 0x10031a2 ; msh_help + 18 + 0x010031b6: a00e .. ADR r0,{pc}+0x3a ; 0x10031f0 + 0x010031b8: f001f98a .... BL rt_kprintf ; 0x10044d0 + 0x010031bc: 2000 . MOVS r0,#0 + 0x010031be: bd70 p. POP {r4-r6,pc} + $d + 0x010031c0: 542d5452 RT-T DCD 1412256850 + 0x010031c4: 61657268 hrea DCD 1634038376 + 0x010031c8: 68732064 d sh DCD 1752375396 + 0x010031cc: 206c6c65 ell DCD 543976549 + 0x010031d0: 6d6d6f63 comm DCD 1835888483 + 0x010031d4: 73646e61 ands DCD 1935961697 + 0x010031d8: 00000a3a :... DCD 2618 + 0x010031dc: 00020014 .... DCD 131092 + 0x010031e0: 36312d25 %-16 DCD 909192485 + 0x010031e4: 202d2073 s - DCD 539828339 + 0x010031e8: 000a7325 %s.. DCD 684837 + 0x010031ec: 00020018 .... DCD 131096 + 0x010031f0: 0000000a .... DCD 10 + $t + i.msh_split + msh_split + 0x010031f4: b5f7 .. PUSH {r0-r2,r4-r7,lr} + 0x010031f6: b082 .. SUB sp,sp,#8 + 0x010031f8: 460e .F MOV r6,r1 + 0x010031fa: 9c02 .. LDR r4,[sp,#8] + 0x010031fc: 2500 .% MOVS r5,#0 + 0x010031fe: 2700 .' MOVS r7,#0 + 0x01003200: e05b [. B 0x10032ba ; msh_split + 198 + 0x01003202: e003 .. B 0x100320c ; msh_split + 24 + 0x01003204: 2000 . MOVS r0,#0 + 0x01003206: 7020 p STRB r0,[r4,#0] + 0x01003208: 1c64 d. ADDS r4,r4,#1 + 0x0100320a: 1c6d m. ADDS r5,r5,#1 + 0x0100320c: 7820 x LDRB r0,[r4,#0] + 0x0100320e: 2820 ( CMP r0,#0x20 + 0x01003210: d002 .. BEQ 0x1003218 ; msh_split + 36 + 0x01003212: 7820 x LDRB r0,[r4,#0] + 0x01003214: 2809 .( CMP r0,#9 + 0x01003216: d101 .. BNE 0x100321c ; msh_split + 40 + 0x01003218: 42b5 .B CMP r5,r6 + 0x0100321a: d3f3 .. BCC 0x1003204 ; msh_split + 16 + 0x0100321c: 2f0a ./ CMP r7,#0xa + 0x0100321e: d316 .. BCC 0x100324e ; msh_split + 90 + 0x01003220: a029 ). ADR r0,{pc}+0xa8 ; 0x10032c8 + 0x01003222: f001f955 ..U. BL rt_kprintf ; 0x10044d0 + 0x01003226: 2000 . MOVS r0,#0 + 0x01003228: 9001 .. STR r0,[sp,#4] + 0x0100322a: e009 .. B 0x1003240 ; msh_split + 76 + 0x0100322c: 9801 .. LDR r0,[sp,#4] + 0x0100322e: 0082 .. LSLS r2,r0,#2 + 0x01003230: 9804 .. LDR r0,[sp,#0x10] + 0x01003232: 5881 .X LDR r1,[r0,r2] + 0x01003234: a02c ,. ADR r0,{pc}+0xb4 ; 0x10032e8 + 0x01003236: f001f94b ..K. BL rt_kprintf ; 0x10044d0 + 0x0100323a: 9801 .. LDR r0,[sp,#4] + 0x0100323c: 1c40 @. ADDS r0,r0,#1 + 0x0100323e: 9001 .. STR r0,[sp,#4] + 0x01003240: 9801 .. LDR r0,[sp,#4] + 0x01003242: 42b8 .B CMP r0,r7 + 0x01003244: d3f2 .. BCC 0x100322c ; msh_split + 56 + 0x01003246: a027 '. ADR r0,{pc}+0x9e ; 0x10032e4 + 0x01003248: f001f942 ..B. BL rt_kprintf ; 0x10044d0 + 0x0100324c: e037 7. B 0x10032be ; msh_split + 202 + 0x0100324e: 42b5 .B CMP r5,r6 + 0x01003250: d300 .. BCC 0x1003254 ; msh_split + 96 + 0x01003252: e034 4. B 0x10032be ; msh_split + 202 + 0x01003254: 7820 x LDRB r0,[r4,#0] + 0x01003256: 2822 "( CMP r0,#0x22 + 0x01003258: d11d .. BNE 0x1003296 ; msh_split + 162 + 0x0100325a: 1c64 d. ADDS r4,r4,#1 + 0x0100325c: 1c6d m. ADDS r5,r5,#1 + 0x0100325e: 00b9 .. LSLS r1,r7,#2 + 0x01003260: 9804 .. LDR r0,[sp,#0x10] + 0x01003262: 5044 DP STR r4,[r0,r1] + 0x01003264: 1c7f .. ADDS r7,r7,#1 + 0x01003266: e009 .. B 0x100327c ; msh_split + 136 + 0x01003268: 7820 x LDRB r0,[r4,#0] + 0x0100326a: 285c \( CMP r0,#0x5c + 0x0100326c: d104 .. BNE 0x1003278 ; msh_split + 132 + 0x0100326e: 7860 `x LDRB r0,[r4,#1] + 0x01003270: 2822 "( CMP r0,#0x22 + 0x01003272: d101 .. BNE 0x1003278 ; msh_split + 132 + 0x01003274: 1c64 d. ADDS r4,r4,#1 + 0x01003276: 1c6d m. ADDS r5,r5,#1 + 0x01003278: 1c64 d. ADDS r4,r4,#1 + 0x0100327a: 1c6d m. ADDS r5,r5,#1 + 0x0100327c: 7820 x LDRB r0,[r4,#0] + 0x0100327e: 2822 "( CMP r0,#0x22 + 0x01003280: d001 .. BEQ 0x1003286 ; msh_split + 146 + 0x01003282: 42b5 .B CMP r5,r6 + 0x01003284: d3f0 .. BCC 0x1003268 ; msh_split + 116 + 0x01003286: 42b5 .B CMP r5,r6 + 0x01003288: d300 .. BCC 0x100328c ; msh_split + 152 + 0x0100328a: e018 .. B 0x10032be ; msh_split + 202 + 0x0100328c: 2000 . MOVS r0,#0 + 0x0100328e: 7020 p STRB r0,[r4,#0] + 0x01003290: 1c64 d. ADDS r4,r4,#1 + 0x01003292: 1c6d m. ADDS r5,r5,#1 + 0x01003294: e011 .. B 0x10032ba ; msh_split + 198 + 0x01003296: 00b9 .. LSLS r1,r7,#2 + 0x01003298: 9804 .. LDR r0,[sp,#0x10] + 0x0100329a: 5044 DP STR r4,[r0,r1] + 0x0100329c: 1c7f .. ADDS r7,r7,#1 + 0x0100329e: e001 .. B 0x10032a4 ; msh_split + 176 + 0x010032a0: 1c64 d. ADDS r4,r4,#1 + 0x010032a2: 1c6d m. ADDS r5,r5,#1 + 0x010032a4: 7820 x LDRB r0,[r4,#0] + 0x010032a6: 2820 ( CMP r0,#0x20 + 0x010032a8: d004 .. BEQ 0x10032b4 ; msh_split + 192 + 0x010032aa: 7820 x LDRB r0,[r4,#0] + 0x010032ac: 2809 .( CMP r0,#9 + 0x010032ae: d001 .. BEQ 0x10032b4 ; msh_split + 192 + 0x010032b0: 42b5 .B CMP r5,r6 + 0x010032b2: d3f5 .. BCC 0x10032a0 ; msh_split + 172 + 0x010032b4: 42b5 .B CMP r5,r6 + 0x010032b6: d300 .. BCC 0x10032ba ; msh_split + 198 + 0x010032b8: e001 .. B 0x10032be ; msh_split + 202 + 0x010032ba: 42b5 .B CMP r5,r6 + 0x010032bc: d3a1 .. BCC 0x1003202 ; msh_split + 14 + 0x010032be: bf00 .. NOP + 0x010032c0: 4638 8F MOV r0,r7 + 0x010032c2: b005 .. ADD sp,sp,#0x14 + 0x010032c4: bdf0 .. POP {r4-r7,pc} + $d + 0x010032c6: 0000 .. DCW 0 + 0x010032c8: 206f6f54 Too DCD 544173908 + 0x010032cc: 796e616d many DCD 2037277037 + 0x010032d0: 67726120 arg DCD 1735549216 + 0x010032d4: 20212073 s ! DCD 539041907 + 0x010032d8: 6f206557 We o DCD 1864394071 + 0x010032dc: 20796c6e nly DCD 544828526 + 0x010032e0: 3a657355 Use: DCD 979727189 + 0x010032e4: 0000000a .... DCD 10 + 0x010032e8: 00207325 %s . DCD 2126629 + $t + i.object_split + object_split + 0x010032ec: b510 .. PUSH {r4,lr} + 0x010032ee: 4604 .F MOV r4,r0 + 0x010032f0: e002 .. B 0x10032f8 ; object_split + 12 + 0x010032f2: a004 .. ADR r0,{pc}+0x12 ; 0x1003304 + 0x010032f4: f001f8ec .... BL rt_kprintf ; 0x10044d0 + 0x010032f8: 4620 F MOV r0,r4 + 0x010032fa: 1e64 d. SUBS r4,r4,#1 + 0x010032fc: 2800 .( CMP r0,#0 + 0x010032fe: d1f8 .. BNE 0x10032f2 ; object_split + 6 + 0x01003300: bd10 .. POP {r4,pc} + $d + 0x01003302: 0000 .. DCW 0 + 0x01003304: 0000002d -... DCD 45 + $t + i.plug_holes + plug_holes + 0x01003308: b570 p. PUSH {r4-r6,lr} + 0x0100330a: 4604 .F MOV r4,r0 + 0x0100330c: 4828 (H LDR r0,[pc,#160] ; [0x10033b0] = 0x2013c + 0x0100330e: 6800 .h LDR r0,[r0,#0] + 0x01003310: 4284 .B CMP r4,r0 + 0x01003312: d204 .. BCS 0x100331e ; plug_holes + 22 + 0x01003314: 22a1 ." MOVS r2,#0xa1 + 0x01003316: 4927 'I LDR r1,[pc,#156] ; [0x10033b4] = 0x1007bef + 0x01003318: a027 '. ADR r0,{pc}+0xa0 ; 0x10033b8 + 0x0100331a: f000f971 ..q. BL rt_assert_handler ; 0x1003600 + 0x0100331e: 482e .H LDR r0,[pc,#184] ; [0x10033d8] = 0x20140 + 0x01003320: 6800 .h LDR r0,[r0,#0] + 0x01003322: 4284 .B CMP r4,r0 + 0x01003324: d304 .. BCC 0x1003330 ; plug_holes + 40 + 0x01003326: 22a2 ." MOVS r2,#0xa2 + 0x01003328: 4922 "I LDR r1,[pc,#136] ; [0x10033b4] = 0x1007bef + 0x0100332a: a02c ,. ADR r0,{pc}+0xb2 ; 0x10033dc + 0x0100332c: f000f968 ..h. BL rt_assert_handler ; 0x1003600 + 0x01003330: 8860 `. LDRH r0,[r4,#2] + 0x01003332: 2800 .( CMP r0,#0 + 0x01003334: d004 .. BEQ 0x1003340 ; plug_holes + 56 + 0x01003336: 22a3 ." MOVS r2,#0xa3 + 0x01003338: 491e .I LDR r1,[pc,#120] ; [0x10033b4] = 0x1007bef + 0x0100333a: a033 3. ADR r0,{pc}+0xce ; 0x1003408 + 0x0100333c: f000f960 ..`. BL rt_assert_handler ; 0x1003600 + 0x01003340: 491b .I LDR r1,[pc,#108] ; [0x10033b0] = 0x2013c + 0x01003342: 6860 `h LDR r0,[r4,#4] + 0x01003344: 6809 .h LDR r1,[r1,#0] + 0x01003346: 1845 E. ADDS r5,r0,r1 + 0x01003348: 42ac .B CMP r4,r5 + 0x0100334a: d016 .. BEQ 0x100337a ; plug_holes + 114 + 0x0100334c: 8868 h. LDRH r0,[r5,#2] + 0x0100334e: 2800 .( CMP r0,#0 + 0x01003350: d113 .. BNE 0x100337a ; plug_holes + 114 + 0x01003352: 4821 !H LDR r0,[pc,#132] ; [0x10033d8] = 0x20140 + 0x01003354: 6800 .h LDR r0,[r0,#0] + 0x01003356: 4285 .B CMP r5,r0 + 0x01003358: d00f .. BEQ 0x100337a ; plug_holes + 114 + 0x0100335a: 482f /H LDR r0,[pc,#188] ; [0x1003418] = 0x20144 + 0x0100335c: 6800 .h LDR r0,[r0,#0] + 0x0100335e: 42a8 .B CMP r0,r5 + 0x01003360: d101 .. BNE 0x1003366 ; plug_holes + 94 + 0x01003362: 482d -H LDR r0,[pc,#180] ; [0x1003418] = 0x20144 + 0x01003364: 6004 .` STR r4,[r0,#0] + 0x01003366: 6868 hh LDR r0,[r5,#4] + 0x01003368: 6060 `` STR r0,[r4,#4] + 0x0100336a: 4811 .H LDR r0,[pc,#68] ; [0x10033b0] = 0x2013c + 0x0100336c: 6800 .h LDR r0,[r0,#0] + 0x0100336e: 1a20 . SUBS r0,r4,r0 + 0x01003370: 4a0f .J LDR r2,[pc,#60] ; [0x10033b0] = 0x2013c + 0x01003372: 6869 ih LDR r1,[r5,#4] + 0x01003374: 6812 .h LDR r2,[r2,#0] + 0x01003376: 1889 .. ADDS r1,r1,r2 + 0x01003378: 6088 .` STR r0,[r1,#8] + 0x0100337a: 490d .I LDR r1,[pc,#52] ; [0x10033b0] = 0x2013c + 0x0100337c: 68a0 .h LDR r0,[r4,#8] + 0x0100337e: 6809 .h LDR r1,[r1,#0] + 0x01003380: 1846 F. ADDS r6,r0,r1 + 0x01003382: 42a6 .B CMP r6,r4 + 0x01003384: d012 .. BEQ 0x10033ac ; plug_holes + 164 + 0x01003386: 8870 p. LDRH r0,[r6,#2] + 0x01003388: 2800 .( CMP r0,#0 + 0x0100338a: d10f .. BNE 0x10033ac ; plug_holes + 164 + 0x0100338c: 4822 "H LDR r0,[pc,#136] ; [0x1003418] = 0x20144 + 0x0100338e: 6800 .h LDR r0,[r0,#0] + 0x01003390: 42a0 .B CMP r0,r4 + 0x01003392: d101 .. BNE 0x1003398 ; plug_holes + 144 + 0x01003394: 4820 H LDR r0,[pc,#128] ; [0x1003418] = 0x20144 + 0x01003396: 6006 .` STR r6,[r0,#0] + 0x01003398: 6860 `h LDR r0,[r4,#4] + 0x0100339a: 6070 p` STR r0,[r6,#4] + 0x0100339c: 4804 .H LDR r0,[pc,#16] ; [0x10033b0] = 0x2013c + 0x0100339e: 6800 .h LDR r0,[r0,#0] + 0x010033a0: 1a31 1. SUBS r1,r6,r0 + 0x010033a2: 4a03 .J LDR r2,[pc,#12] ; [0x10033b0] = 0x2013c + 0x010033a4: 6860 `h LDR r0,[r4,#4] + 0x010033a6: 6812 .h LDR r2,[r2,#0] + 0x010033a8: 1880 .. ADDS r0,r0,r2 + 0x010033aa: 6081 .` STR r1,[r0,#8] + 0x010033ac: bd70 p. POP {r4-r6,pc} + $d + 0x010033ae: 0000 .. DCW 0 + 0x010033b0: 0002013c <... DCD 131388 + 0x010033b4: 01007bef .{.. DCD 16808943 + 0x010033b8: 5f747228 (rt_ DCD 1601466920 + 0x010033bc: 746e6975 uint DCD 1953393013 + 0x010033c0: 20745f38 8_t DCD 544497464 + 0x010033c4: 656d292a *)me DCD 1701652778 + 0x010033c8: 3d3e206d m >= DCD 1027481709 + 0x010033cc: 61656820 hea DCD 1634035744 + 0x010033d0: 74705f70 p_pt DCD 1953521520 + 0x010033d4: 00000072 r... DCD 114 + 0x010033d8: 00020140 @... DCD 131392 + 0x010033dc: 5f747228 (rt_ DCD 1601466920 + 0x010033e0: 746e6975 uint DCD 1953393013 + 0x010033e4: 20745f38 8_t DCD 544497464 + 0x010033e8: 656d292a *)me DCD 1701652778 + 0x010033ec: 203c206d m < DCD 540811373 + 0x010033f0: 5f747228 (rt_ DCD 1601466920 + 0x010033f4: 746e6975 uint DCD 1953393013 + 0x010033f8: 20745f38 8_t DCD 544497464 + 0x010033fc: 6568292a *)he DCD 1701325098 + 0x01003400: 655f7061 ap_e DCD 1700753505 + 0x01003404: 0000646e nd.. DCD 25710 + 0x01003408: 2d6d656d mem- DCD 762144109 + 0x0100340c: 6573753e >use DCD 1702065470 + 0x01003410: 3d3d2064 d == DCD 1027416164 + 0x01003414: 00003020 0.. DCD 12320 + 0x01003418: 00020144 D... DCD 131396 + $t + i.print_number + print_number + 0x0100341c: b5ff .. PUSH {r0-r7,lr} + 0x0100341e: b08b .. SUB sp,sp,#0x2c + 0x01003420: 4604 .F MOV r4,r0 + 0x01003422: 4615 .F MOV r5,r2 + 0x01003424: 9e16 .. LDR r6,[sp,#0x58] + 0x01003426: 9815 .. LDR r0,[sp,#0x54] + 0x01003428: 9004 .. STR r0,[sp,#0x10] + 0x0100342a: 9814 .. LDR r0,[sp,#0x50] + 0x0100342c: 9002 .. STR r0,[sp,#8] + 0x0100342e: 2040 @ MOVS r0,#0x40 + 0x01003430: 4030 0@ ANDS r0,r0,r6 + 0x01003432: 2800 .( CMP r0,#0 + 0x01003434: d001 .. BEQ 0x100343a ; print_number + 30 + 0x01003436: 485c \H LDR r0,[pc,#368] ; [0x10035a8] = 0x10077c4 + 0x01003438: e000 .. B 0x100343c ; print_number + 32 + 0x0100343a: 485c \H LDR r0,[pc,#368] ; [0x10035ac] = 0x10077b3 + 0x0100343c: 9003 .. STR r0,[sp,#0xc] + 0x0100343e: 2010 . MOVS r0,#0x10 + 0x01003440: 4030 0@ ANDS r0,r0,r6 + 0x01003442: 2800 .( CMP r0,#0 + 0x01003444: d001 .. BEQ 0x100344a ; print_number + 46 + 0x01003446: 0876 v. LSRS r6,r6,#1 + 0x01003448: 0076 v. LSLS r6,r6,#1 + 0x0100344a: 07f0 .. LSLS r0,r6,#31 + 0x0100344c: 0fc0 .. LSRS r0,r0,#31 + 0x0100344e: 2800 .( CMP r0,#0 + 0x01003450: d001 .. BEQ 0x1003456 ; print_number + 58 + 0x01003452: 2030 0 MOVS r0,#0x30 + 0x01003454: e000 .. B 0x1003458 ; print_number + 60 + 0x01003456: 2020 MOVS r0,#0x20 + 0x01003458: 900a .. STR r0,[sp,#0x28] + 0x0100345a: 2000 . MOVS r0,#0 + 0x0100345c: 9009 .. STR r0,[sp,#0x24] + 0x0100345e: 2002 . MOVS r0,#2 + 0x01003460: 4030 0@ ANDS r0,r0,r6 + 0x01003462: 2800 .( CMP r0,#0 + 0x01003464: d012 .. BEQ 0x100348c ; print_number + 112 + 0x01003466: 2d00 .- CMP r5,#0 + 0x01003468: da03 .. BGE 0x1003472 ; print_number + 86 + 0x0100346a: 202d - MOVS r0,#0x2d + 0x0100346c: 9009 .. STR r0,[sp,#0x24] + 0x0100346e: 426d mB RSBS r5,r5,#0 + 0x01003470: e00c .. B 0x100348c ; print_number + 112 + 0x01003472: 2004 . MOVS r0,#4 + 0x01003474: 4030 0@ ANDS r0,r0,r6 + 0x01003476: 2800 .( CMP r0,#0 + 0x01003478: d002 .. BEQ 0x1003480 ; print_number + 100 + 0x0100347a: 202b + MOVS r0,#0x2b + 0x0100347c: 9009 .. STR r0,[sp,#0x24] + 0x0100347e: e005 .. B 0x100348c ; print_number + 112 + 0x01003480: 2008 . MOVS r0,#8 + 0x01003482: 4030 0@ ANDS r0,r0,r6 + 0x01003484: 2800 .( CMP r0,#0 + 0x01003486: d001 .. BEQ 0x100348c ; print_number + 112 + 0x01003488: 2020 MOVS r0,#0x20 + 0x0100348a: 9009 .. STR r0,[sp,#0x24] + 0x0100348c: 2700 .' MOVS r7,#0 + 0x0100348e: 2d00 .- CMP r5,#0 + 0x01003490: d105 .. BNE 0x100349e ; print_number + 130 + 0x01003492: 2230 0" MOVS r2,#0x30 + 0x01003494: 4638 8F MOV r0,r7 + 0x01003496: 1c7f .. ADDS r7,r7,#1 + 0x01003498: a905 .. ADD r1,sp,#0x14 + 0x0100349a: 540a .T STRB r2,[r1,r0] + 0x0100349c: e01d .. B 0x10034da ; print_number + 190 + 0x0100349e: e01a .. B 0x10034d6 ; print_number + 186 + 0x010034a0: 980e .. LDR r0,[sp,#0x38] + 0x010034a2: 9001 .. STR r0,[sp,#4] + 0x010034a4: 9801 .. LDR r0,[sp,#4] + 0x010034a6: 280a .( CMP r0,#0xa + 0x010034a8: d10a .. BNE 0x10034c0 ; print_number + 164 + 0x010034aa: 4628 (F MOV r0,r5 + 0x010034ac: 210a .! MOVS r1,#0xa + 0x010034ae: f7fdf9dd .... BL __aeabi_uidiv ; 0x100086c + 0x010034b2: 9100 .. STR r1,[sp,#0] + 0x010034b4: 4628 (F MOV r0,r5 + 0x010034b6: 210a .! MOVS r1,#0xa + 0x010034b8: f7fdf9d8 .... BL __aeabi_uidiv ; 0x100086c + 0x010034bc: 4605 .F MOV r5,r0 + 0x010034be: e003 .. B 0x10034c8 ; print_number + 172 + 0x010034c0: 0728 (. LSLS r0,r5,#28 + 0x010034c2: 0f00 .. LSRS r0,r0,#28 + 0x010034c4: 9000 .. STR r0,[sp,#0] + 0x010034c6: 092d -. LSRS r5,r5,#4 + 0x010034c8: 9800 .. LDR r0,[sp,#0] + 0x010034ca: 9903 .. LDR r1,[sp,#0xc] + 0x010034cc: 5c0a .\ LDRB r2,[r1,r0] + 0x010034ce: 4638 8F MOV r0,r7 + 0x010034d0: 1c7f .. ADDS r7,r7,#1 + 0x010034d2: a905 .. ADD r1,sp,#0x14 + 0x010034d4: 540a .T STRB r2,[r1,r0] + 0x010034d6: 2d00 .- CMP r5,#0 + 0x010034d8: d1e2 .. BNE 0x10034a0 ; print_number + 132 + 0x010034da: 9815 .. LDR r0,[sp,#0x54] + 0x010034dc: 4287 .B CMP r7,r0 + 0x010034de: dd00 .. BLE 0x10034e2 ; print_number + 198 + 0x010034e0: 9715 .. STR r7,[sp,#0x54] + 0x010034e2: 9915 .. LDR r1,[sp,#0x54] + 0x010034e4: 9802 .. LDR r0,[sp,#8] + 0x010034e6: 1a40 @. SUBS r0,r0,r1 + 0x010034e8: 9002 .. STR r0,[sp,#8] + 0x010034ea: 2011 . MOVS r0,#0x11 + 0x010034ec: 4030 0@ ANDS r0,r0,r6 + 0x010034ee: 2800 .( CMP r0,#0 + 0x010034f0: d114 .. BNE 0x100351c ; print_number + 256 + 0x010034f2: 9809 .. LDR r0,[sp,#0x24] + 0x010034f4: 2800 .( CMP r0,#0 + 0x010034f6: d005 .. BEQ 0x1003504 ; print_number + 232 + 0x010034f8: 9802 .. LDR r0,[sp,#8] + 0x010034fa: 2800 .( CMP r0,#0 + 0x010034fc: dd02 .. BLE 0x1003504 ; print_number + 232 + 0x010034fe: 9802 .. LDR r0,[sp,#8] + 0x01003500: 1e40 @. SUBS r0,r0,#1 + 0x01003502: 9002 .. STR r0,[sp,#8] + 0x01003504: e005 .. B 0x1003512 ; print_number + 246 + 0x01003506: 980c .. LDR r0,[sp,#0x30] + 0x01003508: 4284 .B CMP r4,r0 + 0x0100350a: d201 .. BCS 0x1003510 ; print_number + 244 + 0x0100350c: 2020 MOVS r0,#0x20 + 0x0100350e: 7020 p STRB r0,[r4,#0] + 0x01003510: 1c64 d. ADDS r4,r4,#1 + 0x01003512: 9802 .. LDR r0,[sp,#8] + 0x01003514: 1e41 A. SUBS r1,r0,#1 + 0x01003516: 9102 .. STR r1,[sp,#8] + 0x01003518: 2800 .( CMP r0,#0 + 0x0100351a: dcf4 .. BGT 0x1003506 ; print_number + 234 + 0x0100351c: 9809 .. LDR r0,[sp,#0x24] + 0x0100351e: 2800 .( CMP r0,#0 + 0x01003520: d008 .. BEQ 0x1003534 ; print_number + 280 + 0x01003522: 980c .. LDR r0,[sp,#0x30] + 0x01003524: 4284 .B CMP r4,r0 + 0x01003526: d201 .. BCS 0x100352c ; print_number + 272 + 0x01003528: 9809 .. LDR r0,[sp,#0x24] + 0x0100352a: 7020 p STRB r0,[r4,#0] + 0x0100352c: 9802 .. LDR r0,[sp,#8] + 0x0100352e: 1e40 @. SUBS r0,r0,#1 + 0x01003530: 9002 .. STR r0,[sp,#8] + 0x01003532: 1c64 d. ADDS r4,r4,#1 + 0x01003534: 2010 . MOVS r0,#0x10 + 0x01003536: 4030 0@ ANDS r0,r0,r6 + 0x01003538: 2800 .( CMP r0,#0 + 0x0100353a: d10b .. BNE 0x1003554 ; print_number + 312 + 0x0100353c: e005 .. B 0x100354a ; print_number + 302 + 0x0100353e: 980c .. LDR r0,[sp,#0x30] + 0x01003540: 4284 .B CMP r4,r0 + 0x01003542: d201 .. BCS 0x1003548 ; print_number + 300 + 0x01003544: 980a .. LDR r0,[sp,#0x28] + 0x01003546: 7020 p STRB r0,[r4,#0] + 0x01003548: 1c64 d. ADDS r4,r4,#1 + 0x0100354a: 9802 .. LDR r0,[sp,#8] + 0x0100354c: 1e41 A. SUBS r1,r0,#1 + 0x0100354e: 9102 .. STR r1,[sp,#8] + 0x01003550: 2800 .( CMP r0,#0 + 0x01003552: dcf4 .. BGT 0x100353e ; print_number + 290 + 0x01003554: e005 .. B 0x1003562 ; print_number + 326 + 0x01003556: 980c .. LDR r0,[sp,#0x30] + 0x01003558: 4284 .B CMP r4,r0 + 0x0100355a: d201 .. BCS 0x1003560 ; print_number + 324 + 0x0100355c: 2030 0 MOVS r0,#0x30 + 0x0100355e: 7020 p STRB r0,[r4,#0] + 0x01003560: 1c64 d. ADDS r4,r4,#1 + 0x01003562: 9815 .. LDR r0,[sp,#0x54] + 0x01003564: 1e41 A. SUBS r1,r0,#1 + 0x01003566: 9115 .. STR r1,[sp,#0x54] + 0x01003568: 42b8 .B CMP r0,r7 + 0x0100356a: dcf4 .. BGT 0x1003556 ; print_number + 314 + 0x0100356c: e006 .. B 0x100357c ; print_number + 352 + 0x0100356e: 980c .. LDR r0,[sp,#0x30] + 0x01003570: 4284 .B CMP r4,r0 + 0x01003572: d202 .. BCS 0x100357a ; print_number + 350 + 0x01003574: a805 .. ADD r0,sp,#0x14 + 0x01003576: 5dc0 .] LDRB r0,[r0,r7] + 0x01003578: 7020 p STRB r0,[r4,#0] + 0x0100357a: 1c64 d. ADDS r4,r4,#1 + 0x0100357c: 4638 8F MOV r0,r7 + 0x0100357e: 1e7f .. SUBS r7,r7,#1 + 0x01003580: 2800 .( CMP r0,#0 + 0x01003582: dd02 .. BLE 0x100358a ; print_number + 366 + 0x01003584: 9804 .. LDR r0,[sp,#0x10] + 0x01003586: 2800 .( CMP r0,#0 + 0x01003588: d1f1 .. BNE 0x100356e ; print_number + 338 + 0x0100358a: e005 .. B 0x1003598 ; print_number + 380 + 0x0100358c: 980c .. LDR r0,[sp,#0x30] + 0x0100358e: 4284 .B CMP r4,r0 + 0x01003590: d201 .. BCS 0x1003596 ; print_number + 378 + 0x01003592: 2020 MOVS r0,#0x20 + 0x01003594: 7020 p STRB r0,[r4,#0] + 0x01003596: 1c64 d. ADDS r4,r4,#1 + 0x01003598: 9802 .. LDR r0,[sp,#8] + 0x0100359a: 1e41 A. SUBS r1,r0,#1 + 0x0100359c: 9102 .. STR r1,[sp,#8] + 0x0100359e: 2800 .( CMP r0,#0 + 0x010035a0: dcf4 .. BGT 0x100358c ; print_number + 368 + 0x010035a2: 4620 F MOV r0,r4 + 0x010035a4: b00f .. ADD sp,sp,#0x3c + 0x010035a6: bdf0 .. POP {r4-r7,pc} + $d + 0x010035a8: 010077c4 .w.. DCD 16807876 + 0x010035ac: 010077b3 .w.. DCD 16807859 + $t + i.rt_application_init + rt_application_init + 0x010035b0: b51c .. PUSH {r2-r4,lr} + 0x010035b2: 2014 . MOVS r0,#0x14 + 0x010035b4: 210a .! MOVS r1,#0xa + 0x010035b6: 2301 .# MOVS r3,#1 + 0x010035b8: 02db .. LSLS r3,r3,#11 + 0x010035ba: 2200 ." MOVS r2,#0 + 0x010035bc: 9100 .. STR r1,[sp,#0] + 0x010035be: 9001 .. STR r0,[sp,#4] + 0x010035c0: 4907 .I LDR r1,[pc,#28] ; [0x10035e0] = 0x1002fd1 + 0x010035c2: a008 .. ADR r0,{pc}+0x22 ; 0x10035e4 + 0x010035c4: f002fbbd .... BL rt_thread_create ; 0x1005d42 + 0x010035c8: 4604 .F MOV r4,r0 + 0x010035ca: 2c00 ., CMP r4,#0 + 0x010035cc: d104 .. BNE 0x10035d8 ; rt_application_init + 40 + 0x010035ce: 22cb ." MOVS r2,#0xcb + 0x010035d0: 4906 .I LDR r1,[pc,#24] ; [0x10035ec] = 0x1007584 + 0x010035d2: a007 .. ADR r0,{pc}+0x1e ; 0x10035f0 + 0x010035d4: f000f814 .... BL rt_assert_handler ; 0x1003600 + 0x010035d8: 4620 F MOV r0,r4 + 0x010035da: f002fd29 ..). BL rt_thread_startup ; 0x1006030 + 0x010035de: bd1c .. POP {r2-r4,pc} + $d + 0x010035e0: 01002fd1 ./.. DCD 16789457 + 0x010035e4: 6e69616d main DCD 1852399981 + 0x010035e8: 00000000 .... DCD 0 + 0x010035ec: 01007584 .u.. DCD 16807300 + 0x010035f0: 20646974 tid DCD 543451508 + 0x010035f4: 52203d21 != R DCD 1377844513 + 0x010035f8: 554e5f54 T_NU DCD 1431199572 + 0x010035fc: 00004c4c LL.. DCD 19532 + $t + i.rt_assert_handler + rt_assert_handler + 0x01003600: b5f8 .. PUSH {r3-r7,lr} + 0x01003602: 4604 .F MOV r4,r0 + 0x01003604: 460d .F MOV r5,r1 + 0x01003606: 4616 .F MOV r6,r2 + 0x01003608: 2000 . MOVS r0,#0 + 0x0100360a: 9000 .. STR r0,[sp,#0] + 0x0100360c: 480b .H LDR r0,[pc,#44] ; [0x100363c] = 0x20050 + 0x0100360e: 6800 .h LDR r0,[r0,#0] + 0x01003610: 2800 .( CMP r0,#0 + 0x01003612: d10b .. BNE 0x100362c ; rt_assert_handler + 44 + 0x01003614: 4633 3F MOV r3,r6 + 0x01003616: 462a *F MOV r2,r5 + 0x01003618: 4621 !F MOV r1,r4 + 0x0100361a: a009 .. ADR r0,{pc}+0x26 ; 0x1003640 + 0x0100361c: f000ff58 ..X. BL rt_kprintf ; 0x10044d0 + 0x01003620: bf00 .. NOP + 0x01003622: 4668 hF MOV r0,sp + 0x01003624: 7800 .x LDRB r0,[r0,#0] + 0x01003626: 2800 .( CMP r0,#0 + 0x01003628: d0fb .. BEQ 0x1003622 ; rt_assert_handler + 34 + 0x0100362a: e005 .. B 0x1003638 ; rt_assert_handler + 56 + 0x0100362c: 4632 2F MOV r2,r6 + 0x0100362e: 4629 )F MOV r1,r5 + 0x01003630: 4620 F MOV r0,r4 + 0x01003632: 4b02 .K LDR r3,[pc,#8] ; [0x100363c] = 0x20050 + 0x01003634: 681b .h LDR r3,[r3,#0] + 0x01003636: 4798 .G BLX r3 + 0x01003638: bdf8 .. POP {r3-r7,pc} + $d + 0x0100363a: 0000 .. DCW 0 + 0x0100363c: 00020050 P... DCD 131152 + 0x01003640: 29732528 (%s) DCD 695412008 + 0x01003644: 73736120 ass DCD 1936941344 + 0x01003648: 69747265 erti DCD 1769239141 + 0x0100364c: 66206e6f on f DCD 1713401455 + 0x01003650: 656c6961 aile DCD 1701603681 + 0x01003654: 74612064 d at DCD 1952522340 + 0x01003658: 6e756620 fun DCD 1853187616 + 0x0100365c: 6f697463 ctio DCD 1869182051 + 0x01003660: 73253a6e n:%s DCD 1931819630 + 0x01003664: 696c202c , li DCD 1768693804 + 0x01003668: 6e20656e ne n DCD 1847616878 + 0x0100366c: 65626d75 umbe DCD 1700949365 + 0x01003670: 64253a72 r:%d DCD 1680161394 + 0x01003674: 00000a20 ... DCD 2592 + $t + i.rt_calloc + rt_calloc + 0x01003678: b570 p. PUSH {r4-r6,lr} + 0x0100367a: 4604 .F MOV r4,r0 + 0x0100367c: 460d .F MOV r5,r1 + 0x0100367e: 4621 !F MOV r1,r4 + 0x01003680: 4369 iC MULS r1,r5,r1 + 0x01003682: 4608 .F MOV r0,r1 + 0x01003684: f000ffac .... BL rt_malloc ; 0x10045e0 + 0x01003688: 4606 .F MOV r6,r0 + 0x0100368a: 2e00 .. CMP r6,#0 + 0x0100368c: d006 .. BEQ 0x100369c ; rt_calloc + 36 + 0x0100368e: 4620 F MOV r0,r4 + 0x01003690: 4368 hC MULS r0,r5,r0 + 0x01003692: 4602 .F MOV r2,r0 + 0x01003694: 2100 .! MOVS r1,#0 + 0x01003696: 4630 0F MOV r0,r6 + 0x01003698: f001fa13 .... BL rt_memset ; 0x1004ac2 + 0x0100369c: 4630 0F MOV r0,r6 + 0x0100369e: bd70 p. POP {r4-r6,pc} + i.rt_completion_done + rt_completion_done + 0x010036a0: b570 p. PUSH {r4-r6,lr} + 0x010036a2: 4604 .F MOV r4,r0 + 0x010036a4: 2c00 ., CMP r4,#0 + 0x010036a6: d104 .. BNE 0x10036b2 ; rt_completion_done + 18 + 0x010036a8: 227f ." MOVS r2,#0x7f + 0x010036aa: 4911 .I LDR r1,[pc,#68] ; [0x10036f0] = 0x10073ee + 0x010036ac: a011 .. ADR r0,{pc}+0x48 ; 0x10036f4 + 0x010036ae: f7ffffa7 .... BL rt_assert_handler ; 0x1003600 + 0x010036b2: 6820 h LDR r0,[r4,#0] + 0x010036b4: 2801 .( CMP r0,#1 + 0x010036b6: d100 .. BNE 0x10036ba ; rt_completion_done + 26 + 0x010036b8: bd70 p. POP {r4-r6,pc} + 0x010036ba: f7fcff01 .... BL rt_hw_interrupt_disable ; 0x10004c0 + 0x010036be: 4606 .F MOV r6,r0 + 0x010036c0: 2001 . MOVS r0,#1 + 0x010036c2: 6020 ` STR r0,[r4,#0] + 0x010036c4: 1d20 . ADDS r0,r4,#4 + 0x010036c6: f000ff46 ..F. BL rt_list_isempty ; 0x1004556 + 0x010036ca: 2800 .( CMP r0,#0 + 0x010036cc: d10b .. BNE 0x10036e6 ; rt_completion_done + 70 + 0x010036ce: 6860 `h LDR r0,[r4,#4] + 0x010036d0: 4605 .F MOV r5,r0 + 0x010036d2: 3d14 .= SUBS r5,r5,#0x14 + 0x010036d4: 4628 (F MOV r0,r5 + 0x010036d6: f002fc13 .... BL rt_thread_resume ; 0x1005f00 + 0x010036da: 4630 0F MOV r0,r6 + 0x010036dc: f7fcfef4 .... BL rt_hw_interrupt_enable ; 0x10004c8 + 0x010036e0: f001fca8 .... BL rt_schedule ; 0x1005034 + 0x010036e4: e002 .. B 0x10036ec ; rt_completion_done + 76 + 0x010036e6: 4630 0F MOV r0,r6 + 0x010036e8: f7fcfeee .... BL rt_hw_interrupt_enable ; 0x10004c8 + 0x010036ec: bf00 .. NOP + 0x010036ee: e7e3 .. B 0x10036b8 ; rt_completion_done + 24 + $d + 0x010036f0: 010073ee .s.. DCD 16806894 + 0x010036f4: 706d6f63 comp DCD 1886220131 + 0x010036f8: 6974656c leti DCD 1769235820 + 0x010036fc: 21206e6f on ! DCD 555773551 + 0x01003700: 5452203d = RT DCD 1414668349 + 0x01003704: 4c554e5f _NUL DCD 1280659039 + 0x01003708: 0000004c L... DCD 76 + $t + i.rt_completion_init + rt_completion_init + 0x0100370c: b570 p. PUSH {r4-r6,lr} + 0x0100370e: 4604 .F MOV r4,r0 + 0x01003710: 2c00 ., CMP r4,#0 + 0x01003712: d104 .. BNE 0x100371e ; rt_completion_init + 18 + 0x01003714: 221b ." MOVS r2,#0x1b + 0x01003716: 4908 .I LDR r1,[pc,#32] ; [0x1003738] = 0x10073c8 + 0x01003718: a008 .. ADR r0,{pc}+0x24 ; 0x100373c + 0x0100371a: f7ffff71 ..q. BL rt_assert_handler ; 0x1003600 + 0x0100371e: f7fcfecf .... BL rt_hw_interrupt_disable ; 0x10004c0 + 0x01003722: 4605 .F MOV r5,r0 + 0x01003724: 2000 . MOVS r0,#0 + 0x01003726: 6020 ` STR r0,[r4,#0] + 0x01003728: 1d20 . ADDS r0,r4,#4 + 0x0100372a: 6040 @` STR r0,[r0,#4] + 0x0100372c: 6000 .` STR r0,[r0,#0] + 0x0100372e: bf00 .. NOP + 0x01003730: 4628 (F MOV r0,r5 + 0x01003732: f7fcfec9 .... BL rt_hw_interrupt_enable ; 0x10004c8 + 0x01003736: bd70 p. POP {r4-r6,pc} + $d + 0x01003738: 010073c8 .s.. DCD 16806856 + 0x0100373c: 706d6f63 comp DCD 1886220131 + 0x01003740: 6974656c leti DCD 1769235820 + 0x01003744: 21206e6f on ! DCD 555773551 + 0x01003748: 5452203d = RT DCD 1414668349 + 0x0100374c: 4c554e5f _NUL DCD 1280659039 + 0x01003750: 0000004c L... DCD 76 + $t + i.rt_completion_wait + rt_completion_wait + 0x01003754: b5f3 .. PUSH {r0,r1,r4-r7,lr} + 0x01003756: b081 .. SUB sp,sp,#4 + 0x01003758: 4605 .F MOV r5,r0 + 0x0100375a: 2d00 .- CMP r5,#0 + 0x0100375c: d104 .. BNE 0x1003768 ; rt_completion_wait + 20 + 0x0100375e: 223a :" MOVS r2,#0x3a + 0x01003760: 492f /I LDR r1,[pc,#188] ; [0x1003820] = 0x10073db + 0x01003762: a030 0. ADR r0,{pc}+0xc2 ; 0x1003824 + 0x01003764: f7ffff4c ..L. BL rt_assert_handler ; 0x1003600 + 0x01003768: 2600 .& MOVS r6,#0 + 0x0100376a: f002fc19 .... BL rt_thread_self ; 0x1005fa0 + 0x0100376e: 4604 .F MOV r4,r0 + 0x01003770: f7fcfea6 .... BL rt_hw_interrupt_disable ; 0x10004c0 + 0x01003774: 4607 .F MOV r7,r0 + 0x01003776: 6828 (h LDR r0,[r5,#0] + 0x01003778: 2801 .( CMP r0,#1 + 0x0100377a: d048 H. BEQ 0x100380e ; rt_completion_wait + 186 + 0x0100377c: 1d28 (. ADDS r0,r5,#4 + 0x0100377e: f000feea .... BL rt_list_isempty ; 0x1004556 + 0x01003782: 2800 .( CMP r0,#0 + 0x01003784: d104 .. BNE 0x1003790 ; rt_completion_wait + 60 + 0x01003786: 2243 C" MOVS r2,#0x43 + 0x01003788: 4925 %I LDR r1,[pc,#148] ; [0x1003820] = 0x10073db + 0x0100378a: a02c ,. ADR r0,{pc}+0xb2 ; 0x100383c + 0x0100378c: f7ffff38 ..8. BL rt_assert_handler ; 0x1003600 + 0x01003790: 9802 .. LDR r0,[sp,#8] + 0x01003792: 2800 .( CMP r0,#0 + 0x01003794: d101 .. BNE 0x100379a ; rt_completion_wait + 70 + 0x01003796: 1e86 .. SUBS r6,r0,#2 + 0x01003798: e03c <. B 0x1003814 ; rt_completion_wait + 192 + 0x0100379a: 2000 . MOVS r0,#0 + 0x0100379c: 6320 c STR r0,[r4,#0x30] + 0x0100379e: 4620 F MOV r0,r4 + 0x010037a0: f002fcaa .... BL rt_thread_suspend ; 0x10060f8 + 0x010037a4: 1d29 ). ADDS r1,r5,#4 + 0x010037a6: 4620 F MOV r0,r4 + 0x010037a8: 3014 .0 ADDS r0,r0,#0x14 + 0x010037aa: 684a Jh LDR r2,[r1,#4] + 0x010037ac: 6010 .` STR r0,[r2,#0] + 0x010037ae: 684a Jh LDR r2,[r1,#4] + 0x010037b0: 6042 B` STR r2,[r0,#4] + 0x010037b2: 6048 H` STR r0,[r1,#4] + 0x010037b4: 6001 .` STR r1,[r0,#0] + 0x010037b6: bf00 .. NOP + 0x010037b8: bf00 .. NOP + 0x010037ba: f7fcfe81 .... BL rt_hw_interrupt_disable ; 0x10004c0 + 0x010037be: 9000 .. STR r0,[sp,#0] + 0x010037c0: f000fe5c ..\. BL rt_interrupt_get_nest ; 0x100447c + 0x010037c4: 2800 .( CMP r0,#0 + 0x010037c6: d008 .. BEQ 0x10037da ; rt_completion_wait + 134 + 0x010037c8: 4915 .I LDR r1,[pc,#84] ; [0x1003820] = 0x10073db + 0x010037ca: a028 (. ADR r0,{pc}+0xa2 ; 0x100386c + 0x010037cc: f000fe80 .... BL rt_kprintf ; 0x10044d0 + 0x010037d0: 2256 V" MOVS r2,#0x56 + 0x010037d2: 4913 .I LDR r1,[pc,#76] ; [0x1003820] = 0x10073db + 0x010037d4: a02f /. ADR r0,{pc}+0xc0 ; 0x1003894 + 0x010037d6: f7ffff13 .... BL rt_assert_handler ; 0x1003600 + 0x010037da: 9800 .. LDR r0,[sp,#0] + 0x010037dc: f7fcfe74 ..t. BL rt_hw_interrupt_enable ; 0x10004c8 + 0x010037e0: bf00 .. NOP + 0x010037e2: 9802 .. LDR r0,[sp,#8] + 0x010037e4: 2800 .( CMP r0,#0 + 0x010037e6: dd09 .. BLE 0x10037fc ; rt_completion_wait + 168 + 0x010037e8: aa02 .. ADD r2,sp,#8 + 0x010037ea: 2100 .! MOVS r1,#0 + 0x010037ec: 4620 F MOV r0,r4 + 0x010037ee: 304c L0 ADDS r0,r0,#0x4c + 0x010037f0: f002fe1a .... BL rt_timer_control ; 0x1006428 + 0x010037f4: 4620 F MOV r0,r4 + 0x010037f6: 304c L0 ADDS r0,r0,#0x4c + 0x010037f8: f002ff1c .... BL rt_timer_start ; 0x1006634 + 0x010037fc: 4638 8F MOV r0,r7 + 0x010037fe: f7fcfe63 ..c. BL rt_hw_interrupt_enable ; 0x10004c8 + 0x01003802: f001fc17 .... BL rt_schedule ; 0x1005034 + 0x01003806: 6b26 &k LDR r6,[r4,#0x30] + 0x01003808: f7fcfe5a ..Z. BL rt_hw_interrupt_disable ; 0x10004c0 + 0x0100380c: 4607 .F MOV r7,r0 + 0x0100380e: 2000 . MOVS r0,#0 + 0x01003810: 6028 (` STR r0,[r5,#0] + 0x01003812: bf00 .. NOP + 0x01003814: 4638 8F MOV r0,r7 + 0x01003816: f7fcfe57 ..W. BL rt_hw_interrupt_enable ; 0x10004c8 + 0x0100381a: 4630 0F MOV r0,r6 + 0x0100381c: bdfe .. POP {r1-r7,pc} + $d + 0x0100381e: 0000 .. DCW 0 + 0x01003820: 010073db .s.. DCD 16806875 + 0x01003824: 706d6f63 comp DCD 1886220131 + 0x01003828: 6974656c leti DCD 1769235820 + 0x0100382c: 21206e6f on ! DCD 555773551 + 0x01003830: 5452203d = RT DCD 1414668349 + 0x01003834: 4c554e5f _NUL DCD 1280659039 + 0x01003838: 0000004c L... DCD 76 + 0x0100383c: 6c5f7472 rt_l DCD 1818195058 + 0x01003840: 5f747369 ist_ DCD 1601467241 + 0x01003844: 6d657369 isem DCD 1835365225 + 0x01003848: 28797470 pty( DCD 679048304 + 0x0100384c: 6f632826 &(co DCD 1868769318 + 0x01003850: 656c706d mple DCD 1701605485 + 0x01003854: 6e6f6974 tion DCD 1852795252 + 0x01003858: 75733e2d ->su DCD 1970486829 + 0x0100385c: 6e657073 spen DCD 1852141683 + 0x01003860: 5f646564 ded_ DCD 1600415076 + 0x01003864: 7473696c list DCD 1953720684 + 0x01003868: 00002929 )).. DCD 10537 + 0x0100386c: 636e7546 Func DCD 1668183366 + 0x01003870: 6e6f6974 tion DCD 1852795252 + 0x01003874: 5d73255b [%s] DCD 1567827291 + 0x01003878: 61687320 sha DCD 1634235168 + 0x0100387c: 6e206c6c ll n DCD 1847618668 + 0x01003880: 6220746f ot b DCD 1646294127 + 0x01003884: 73752065 e us DCD 1937055845 + 0x01003888: 69206465 ed i DCD 1763730533 + 0x0100388c: 5349206e n IS DCD 1397301358 + 0x01003890: 00000a52 R... DCD 2642 + 0x01003894: 00000030 0... DCD 48 + $t + i.rt_components_board_init + rt_components_board_init + 0x01003898: b510 .. PUSH {r4,lr} + 0x0100389a: 4c04 .L LDR r4,[pc,#16] ; [0x10038ac] = 0x10082f4 + 0x0100389c: e002 .. B 0x10038a4 ; rt_components_board_init + 12 + 0x0100389e: 6820 h LDR r0,[r4,#0] + 0x010038a0: 4780 .G BLX r0 + 0x010038a2: 1d24 $. ADDS r4,r4,#4 + 0x010038a4: 4802 .H LDR r0,[pc,#8] ; [0x10038b0] = 0x1008300 + 0x010038a6: 4284 .B CMP r4,r0 + 0x010038a8: d3f9 .. BCC 0x100389e ; rt_components_board_init + 6 + 0x010038aa: bd10 .. POP {r4,pc} + $d + 0x010038ac: 010082f4 .... DCD 16810740 + 0x010038b0: 01008300 .... DCD 16810752 + $t + i.rt_components_init + rt_components_init + 0x010038b4: b510 .. PUSH {r4,lr} + 0x010038b6: 4c04 .L LDR r4,[pc,#16] ; [0x10038c8] = 0x1008300 + 0x010038b8: e002 .. B 0x10038c0 ; rt_components_init + 12 + 0x010038ba: 6820 h LDR r0,[r4,#0] + 0x010038bc: 4780 .G BLX r0 + 0x010038be: 1d24 $. ADDS r4,r4,#4 + 0x010038c0: 4802 .H LDR r0,[pc,#8] ; [0x10038cc] = 0x1008308 + 0x010038c2: 4284 .B CMP r4,r0 + 0x010038c4: d3f9 .. BCC 0x10038ba ; rt_components_init + 6 + 0x010038c6: bd10 .. POP {r4,pc} + $d + 0x010038c8: 01008300 .... DCD 16810752 + 0x010038cc: 01008308 .... DCD 16810760 + $t + i.rt_console_get_device + rt_console_get_device + 0x010038d0: 4801 .H LDR r0,[pc,#4] ; [0x10038d8] = 0x2004c + 0x010038d2: 6800 .h LDR r0,[r0,#0] + 0x010038d4: 4770 pG BX lr + $d + 0x010038d6: 0000 .. DCW 0 + 0x010038d8: 0002004c L... DCD 131148 + $t + i.rt_console_set_device + rt_console_set_device + 0x010038dc: b570 p. PUSH {r4-r6,lr} + 0x010038de: 4606 .F MOV r6,r0 + 0x010038e0: 480d .H LDR r0,[pc,#52] ; [0x1003918] = 0x2004c + 0x010038e2: 6805 .h LDR r5,[r0,#0] + 0x010038e4: 4630 0F MOV r0,r6 + 0x010038e6: f000f8d5 .... BL rt_device_find ; 0x1003a94 + 0x010038ea: 4604 .F MOV r4,r0 + 0x010038ec: 42ac .B CMP r4,r5 + 0x010038ee: d101 .. BNE 0x10038f4 ; rt_console_set_device + 24 + 0x010038f0: 2000 . MOVS r0,#0 + 0x010038f2: bd70 p. POP {r4-r6,pc} + 0x010038f4: 2c00 ., CMP r4,#0 + 0x010038f6: d00d .. BEQ 0x1003914 ; rt_console_set_device + 56 + 0x010038f8: 4807 .H LDR r0,[pc,#28] ; [0x1003918] = 0x2004c + 0x010038fa: 6800 .h LDR r0,[r0,#0] + 0x010038fc: 2800 .( CMP r0,#0 + 0x010038fe: d003 .. BEQ 0x1003908 ; rt_console_set_device + 44 + 0x01003900: 4805 .H LDR r0,[pc,#20] ; [0x1003918] = 0x2004c + 0x01003902: 6800 .h LDR r0,[r0,#0] + 0x01003904: f000f86a ..j. BL rt_device_close ; 0x10039dc + 0x01003908: 2143 C! MOVS r1,#0x43 + 0x0100390a: 4620 F MOV r0,r4 + 0x0100390c: f000f8ca .... BL rt_device_open ; 0x1003aa4 + 0x01003910: 4801 .H LDR r0,[pc,#4] ; [0x1003918] = 0x2004c + 0x01003912: 6004 .` STR r4,[r0,#0] + 0x01003914: 4628 (F MOV r0,r5 + 0x01003916: e7ec .. B 0x10038f2 ; rt_console_set_device + 22 + $d + 0x01003918: 0002004c L... DCD 131148 + $t + i.rt_defunct_execute + rt_defunct_execute + 0x0100391c: b5f8 .. PUSH {r3-r7,lr} + 0x0100391e: e041 A. B 0x10039a4 ; rt_defunct_execute + 136 + 0x01003920: bf00 .. NOP + 0x01003922: f7fcfdcd .... BL rt_hw_interrupt_disable ; 0x10004c0 + 0x01003926: 4607 .F MOV r7,r0 + 0x01003928: f000fda8 .... BL rt_interrupt_get_nest ; 0x100447c + 0x0100392c: 2800 .( CMP r0,#0 + 0x0100392e: d008 .. BEQ 0x1003942 ; rt_defunct_execute + 38 + 0x01003930: 491e .I LDR r1,[pc,#120] ; [0x10039ac] = 0x10075e6 + 0x01003932: a01f .. ADR r0,{pc}+0x7e ; 0x10039b0 + 0x01003934: f000fdcc .... BL rt_kprintf ; 0x10044d0 + 0x01003938: 22cb ." MOVS r2,#0xcb + 0x0100393a: 491c .I LDR r1,[pc,#112] ; [0x10039ac] = 0x10075e6 + 0x0100393c: a026 &. ADR r0,{pc}+0x9c ; 0x10039d8 + 0x0100393e: f7fffe5f .._. BL rt_assert_handler ; 0x1003600 + 0x01003942: 4638 8F MOV r0,r7 + 0x01003944: f7fcfdc0 .... BL rt_hw_interrupt_enable ; 0x10004c8 + 0x01003948: bf00 .. NOP + 0x0100394a: f7fcfdb9 .... BL rt_hw_interrupt_disable ; 0x10004c0 + 0x0100394e: 4606 .F MOV r6,r0 + 0x01003950: f002fa20 .. . BL rt_thread_defunct_dequeue ; 0x1005d94 + 0x01003954: 4604 .F MOV r4,r0 + 0x01003956: 2c00 ., CMP r4,#0 + 0x01003958: d103 .. BNE 0x1003962 ; rt_defunct_execute + 70 + 0x0100395a: 4630 0F MOV r0,r6 + 0x0100395c: f7fcfdb4 .... BL rt_hw_interrupt_enable ; 0x10004c8 + 0x01003960: e021 !. B 0x10039a6 ; rt_defunct_execute + 138 + 0x01003962: 6fa5 .o LDR r5,[r4,#0x78] + 0x01003964: 2d00 .- CMP r5,#0 + 0x01003966: d007 .. BEQ 0x1003978 ; rt_defunct_execute + 92 + 0x01003968: 4630 0F MOV r0,r6 + 0x0100396a: f7fcfdad .... BL rt_hw_interrupt_enable ; 0x10004c8 + 0x0100396e: 4620 F MOV r0,r4 + 0x01003970: 47a8 .G BLX r5 + 0x01003972: f7fcfda5 .... BL rt_hw_interrupt_disable ; 0x10004c0 + 0x01003976: 4606 .F MOV r6,r0 + 0x01003978: 4620 F MOV r0,r4 + 0x0100397a: f001faf3 .... BL rt_object_is_systemobject ; 0x1004f64 + 0x0100397e: 2801 .( CMP r0,#1 + 0x01003980: d106 .. BNE 0x1003990 ; rt_defunct_execute + 116 + 0x01003982: 4620 F MOV r0,r4 + 0x01003984: f001f98e .... BL rt_object_detach ; 0x1004ca4 + 0x01003988: 4630 0F MOV r0,r6 + 0x0100398a: f7fcfd9d .... BL rt_hw_interrupt_enable ; 0x10004c8 + 0x0100398e: e008 .. B 0x10039a2 ; rt_defunct_execute + 134 + 0x01003990: 4630 0F MOV r0,r6 + 0x01003992: f7fcfd99 .... BL rt_hw_interrupt_enable ; 0x10004c8 + 0x01003996: 6aa0 .j LDR r0,[r4,#0x28] + 0x01003998: f000fa9a .... BL rt_free ; 0x1003ed0 + 0x0100399c: 4620 F MOV r0,r4 + 0x0100399e: f001f92d ..-. BL rt_object_delete ; 0x1004bfc + 0x010039a2: bf00 .. NOP + 0x010039a4: e7bc .. B 0x1003920 ; rt_defunct_execute + 4 + 0x010039a6: bf00 .. NOP + 0x010039a8: bdf8 .. POP {r3-r7,pc} + $d + 0x010039aa: 0000 .. DCW 0 + 0x010039ac: 010075e6 .u.. DCD 16807398 + 0x010039b0: 636e7546 Func DCD 1668183366 + 0x010039b4: 6e6f6974 tion DCD 1852795252 + 0x010039b8: 5d73255b [%s] DCD 1567827291 + 0x010039bc: 61687320 sha DCD 1634235168 + 0x010039c0: 6e206c6c ll n DCD 1847618668 + 0x010039c4: 6220746f ot b DCD 1646294127 + 0x010039c8: 73752065 e us DCD 1937055845 + 0x010039cc: 69206465 ed i DCD 1763730533 + 0x010039d0: 5349206e n IS DCD 1397301358 + 0x010039d4: 00000a52 R... DCD 2642 + 0x010039d8: 00000030 0... DCD 48 + $t + i.rt_device_close + rt_device_close + 0x010039dc: b570 p. PUSH {r4-r6,lr} + 0x010039de: 4604 .F MOV r4,r0 + 0x010039e0: 2500 .% MOVS r5,#0 + 0x010039e2: 2c00 ., CMP r4,#0 + 0x010039e4: d105 .. BNE 0x10039f2 ; rt_device_close + 22 + 0x010039e6: 22ff ." MOVS r2,#0xff + 0x010039e8: 320b .2 ADDS r2,r2,#0xb + 0x010039ea: 4916 .I LDR r1,[pc,#88] ; [0x1003a44] = 0x100763e + 0x010039ec: a016 .. ADR r0,{pc}+0x5c ; 0x1003a48 + 0x010039ee: f7fffe07 .... BL rt_assert_handler ; 0x1003600 + 0x010039f2: 4620 F MOV r0,r4 + 0x010039f4: f001fa3a ..:. BL rt_object_get_type ; 0x1004e6c + 0x010039f8: 2809 .( CMP r0,#9 + 0x010039fa: d005 .. BEQ 0x1003a08 ; rt_device_close + 44 + 0x010039fc: 22ff ." MOVS r2,#0xff + 0x010039fe: 320c .2 ADDS r2,r2,#0xc + 0x01003a00: 4910 .I LDR r1,[pc,#64] ; [0x1003a44] = 0x100763e + 0x01003a02: a015 .. ADR r0,{pc}+0x56 ; 0x1003a58 + 0x01003a04: f7fffdfc .... BL rt_assert_handler ; 0x1003600 + 0x01003a08: 7ea0 .~ LDRB r0,[r4,#0x1a] + 0x01003a0a: 2800 .( CMP r0,#0 + 0x01003a0c: d101 .. BNE 0x1003a12 ; rt_device_close + 54 + 0x01003a0e: 1e40 @. SUBS r0,r0,#1 + 0x01003a10: bd70 p. POP {r4-r6,pc} + 0x01003a12: 7ea0 .~ LDRB r0,[r4,#0x1a] + 0x01003a14: 1e40 @. SUBS r0,r0,#1 + 0x01003a16: 76a0 .v STRB r0,[r4,#0x1a] + 0x01003a18: 7ea0 .~ LDRB r0,[r4,#0x1a] + 0x01003a1a: 2800 .( CMP r0,#0 + 0x01003a1c: d001 .. BEQ 0x1003a22 ; rt_device_close + 70 + 0x01003a1e: 2000 . MOVS r0,#0 + 0x01003a20: e7f6 .. B 0x1003a10 ; rt_device_close + 52 + 0x01003a22: 6ae0 .j LDR r0,[r4,#0x2c] + 0x01003a24: 2800 .( CMP r0,#0 + 0x01003a26: d003 .. BEQ 0x1003a30 ; rt_device_close + 84 + 0x01003a28: 4620 F MOV r0,r4 + 0x01003a2a: 6ae1 .j LDR r1,[r4,#0x2c] + 0x01003a2c: 4788 .G BLX r1 + 0x01003a2e: 4605 .F MOV r5,r0 + 0x01003a30: 2d00 .- CMP r5,#0 + 0x01003a32: d002 .. BEQ 0x1003a3a ; rt_device_close + 94 + 0x01003a34: 1da8 .. ADDS r0,r5,#6 + 0x01003a36: 2800 .( CMP r0,#0 + 0x01003a38: d101 .. BNE 0x1003a3e ; rt_device_close + 98 + 0x01003a3a: 2000 . MOVS r0,#0 + 0x01003a3c: 8320 . STRH r0,[r4,#0x18] + 0x01003a3e: 4628 (F MOV r0,r5 + 0x01003a40: e7e6 .. B 0x1003a10 ; rt_device_close + 52 + $d + 0x01003a42: 0000 .. DCW 0 + 0x01003a44: 0100763e >v.. DCD 16807486 + 0x01003a48: 20766564 dev DCD 544630116 + 0x01003a4c: 52203d21 != R DCD 1377844513 + 0x01003a50: 554e5f54 T_NU DCD 1431199572 + 0x01003a54: 00004c4c LL.. DCD 19532 + 0x01003a58: 6f5f7472 rt_o DCD 1868526706 + 0x01003a5c: 63656a62 bjec DCD 1667590754 + 0x01003a60: 65675f74 t_ge DCD 1701273460 + 0x01003a64: 79745f74 t_ty DCD 2037669748 + 0x01003a68: 26286570 pe(& DCD 640181616 + 0x01003a6c: 2d766564 dev- DCD 762733924 + 0x01003a70: 7261703e >par DCD 1918988350 + 0x01003a74: 29746e65 ent) DCD 695496293 + 0x01003a78: 203d3d20 == DCD 540884256 + 0x01003a7c: 4f5f5452 RT_O DCD 1331647570 + 0x01003a80: 63656a62 bjec DCD 1667590754 + 0x01003a84: 6c435f74 t_Cl DCD 1816354676 + 0x01003a88: 5f737361 ass_ DCD 1601401697 + 0x01003a8c: 69766544 Devi DCD 1769366852 + 0x01003a90: 00006563 ce.. DCD 25955 + $t + i.rt_device_find + rt_device_find + 0x01003a94: b510 .. PUSH {r4,lr} + 0x01003a96: 4604 .F MOV r4,r0 + 0x01003a98: 2109 .! MOVS r1,#9 + 0x01003a9a: 4620 F MOV r0,r4 + 0x01003a9c: f001f932 ..2. BL rt_object_find ; 0x1004d04 + 0x01003aa0: bd10 .. POP {r4,pc} + 0x01003aa2: 0000 .. MOVS r0,r0 + i.rt_device_open + rt_device_open + 0x01003aa4: b570 p. PUSH {r4-r6,lr} + 0x01003aa6: 4604 .F MOV r4,r0 + 0x01003aa8: 460e .F MOV r6,r1 + 0x01003aaa: 2500 .% MOVS r5,#0 + 0x01003aac: 2c00 ., CMP r4,#0 + 0x01003aae: d104 .. BNE 0x1003aba ; rt_device_open + 22 + 0x01003ab0: 22c9 ." MOVS r2,#0xc9 + 0x01003ab2: 492a *I LDR r1,[pc,#168] ; [0x1003b5c] = 0x100762f + 0x01003ab4: a02a *. ADR r0,{pc}+0xac ; 0x1003b60 + 0x01003ab6: f7fffda3 .... BL rt_assert_handler ; 0x1003600 + 0x01003aba: 4620 F MOV r0,r4 + 0x01003abc: f001f9d6 .... BL rt_object_get_type ; 0x1004e6c + 0x01003ac0: 2809 .( CMP r0,#9 + 0x01003ac2: d004 .. BEQ 0x1003ace ; rt_device_open + 42 + 0x01003ac4: 22ca ." MOVS r2,#0xca + 0x01003ac6: 4925 %I LDR r1,[pc,#148] ; [0x1003b5c] = 0x100762f + 0x01003ac8: a029 ). ADR r0,{pc}+0xa8 ; 0x1003b70 + 0x01003aca: f7fffd99 .... BL rt_assert_handler ; 0x1003600 + 0x01003ace: 8ae0 .. LDRH r0,[r4,#0x16] + 0x01003ad0: 2110 .! MOVS r1,#0x10 + 0x01003ad2: 4008 .@ ANDS r0,r0,r1 + 0x01003ad4: 2800 .( CMP r0,#0 + 0x01003ad6: d113 .. BNE 0x1003b00 ; rt_device_open + 92 + 0x01003ad8: 6a60 `j LDR r0,[r4,#0x24] + 0x01003ada: 2800 .( CMP r0,#0 + 0x01003adc: d00c .. BEQ 0x1003af8 ; rt_device_open + 84 + 0x01003ade: 4620 F MOV r0,r4 + 0x01003ae0: 6a61 aj LDR r1,[r4,#0x24] + 0x01003ae2: 4788 .G BLX r1 + 0x01003ae4: 4605 .F MOV r5,r0 + 0x01003ae6: 2d00 .- CMP r5,#0 + 0x01003ae8: d006 .. BEQ 0x1003af8 ; rt_device_open + 84 + 0x01003aea: 462a *F MOV r2,r5 + 0x01003aec: 4621 !F MOV r1,r4 + 0x01003aee: a02f /. ADR r0,{pc}+0xbe ; 0x1003bac + 0x01003af0: f000fcee .... BL rt_kprintf ; 0x10044d0 + 0x01003af4: 4628 (F MOV r0,r5 + 0x01003af6: bd70 p. POP {r4-r6,pc} + 0x01003af8: 8ae0 .. LDRH r0,[r4,#0x16] + 0x01003afa: 2110 .! MOVS r1,#0x10 + 0x01003afc: 4308 .C ORRS r0,r0,r1 + 0x01003afe: 82e0 .. STRH r0,[r4,#0x16] + 0x01003b00: 8ae0 .. LDRH r0,[r4,#0x16] + 0x01003b02: 2108 .! MOVS r1,#8 + 0x01003b04: 4008 .@ ANDS r0,r0,r1 + 0x01003b06: 2800 .( CMP r0,#0 + 0x01003b08: d006 .. BEQ 0x1003b18 ; rt_device_open + 116 + 0x01003b0a: 8b20 . LDRH r0,[r4,#0x18] + 0x01003b0c: 4008 .@ ANDS r0,r0,r1 + 0x01003b0e: 2800 .( CMP r0,#0 + 0x01003b10: d002 .. BEQ 0x1003b18 ; rt_device_open + 116 + 0x01003b12: 2006 . MOVS r0,#6 + 0x01003b14: 43c0 .C MVNS r0,r0 + 0x01003b16: e7ee .. B 0x1003af6 ; rt_device_open + 82 + 0x01003b18: 6aa0 .j LDR r0,[r4,#0x28] + 0x01003b1a: 2800 .( CMP r0,#0 + 0x01003b1c: d005 .. BEQ 0x1003b2a ; rt_device_open + 134 + 0x01003b1e: 4631 1F MOV r1,r6 + 0x01003b20: 4620 F MOV r0,r4 + 0x01003b22: 6aa2 .j LDR r2,[r4,#0x28] + 0x01003b24: 4790 .G BLX r2 + 0x01003b26: 4605 .F MOV r5,r0 + 0x01003b28: e002 .. B 0x1003b30 ; rt_device_open + 140 + 0x01003b2a: 482e .H LDR r0,[pc,#184] ; [0x1003be4] = 0xf0f + 0x01003b2c: 4030 0@ ANDS r0,r0,r6 + 0x01003b2e: 8320 . STRH r0,[r4,#0x18] + 0x01003b30: 2d00 .- CMP r5,#0 + 0x01003b32: d002 .. BEQ 0x1003b3a ; rt_device_open + 150 + 0x01003b34: 1da8 .. ADDS r0,r5,#6 + 0x01003b36: 2800 .( CMP r0,#0 + 0x01003b38: d10e .. BNE 0x1003b58 ; rt_device_open + 180 + 0x01003b3a: 8b20 . LDRH r0,[r4,#0x18] + 0x01003b3c: 2108 .! MOVS r1,#8 + 0x01003b3e: 4308 .C ORRS r0,r0,r1 + 0x01003b40: 8320 . STRH r0,[r4,#0x18] + 0x01003b42: 7ea0 .~ LDRB r0,[r4,#0x1a] + 0x01003b44: 1c40 @. ADDS r0,r0,#1 + 0x01003b46: 76a0 .v STRB r0,[r4,#0x1a] + 0x01003b48: 7ea0 .~ LDRB r0,[r4,#0x1a] + 0x01003b4a: 2800 .( CMP r0,#0 + 0x01003b4c: d104 .. BNE 0x1003b58 ; rt_device_open + 180 + 0x01003b4e: 22f8 ." MOVS r2,#0xf8 + 0x01003b50: 4902 .I LDR r1,[pc,#8] ; [0x1003b5c] = 0x100762f + 0x01003b52: a025 %. ADR r0,{pc}+0x96 ; 0x1003be8 + 0x01003b54: f7fffd54 ..T. BL rt_assert_handler ; 0x1003600 + 0x01003b58: 4628 (F MOV r0,r5 + 0x01003b5a: e7cc .. B 0x1003af6 ; rt_device_open + 82 + $d + 0x01003b5c: 0100762f /v.. DCD 16807471 + 0x01003b60: 20766564 dev DCD 544630116 + 0x01003b64: 52203d21 != R DCD 1377844513 + 0x01003b68: 554e5f54 T_NU DCD 1431199572 + 0x01003b6c: 00004c4c LL.. DCD 19532 + 0x01003b70: 6f5f7472 rt_o DCD 1868526706 + 0x01003b74: 63656a62 bjec DCD 1667590754 + 0x01003b78: 65675f74 t_ge DCD 1701273460 + 0x01003b7c: 79745f74 t_ty DCD 2037669748 + 0x01003b80: 26286570 pe(& DCD 640181616 + 0x01003b84: 2d766564 dev- DCD 762733924 + 0x01003b88: 7261703e >par DCD 1918988350 + 0x01003b8c: 29746e65 ent) DCD 695496293 + 0x01003b90: 203d3d20 == DCD 540884256 + 0x01003b94: 4f5f5452 RT_O DCD 1331647570 + 0x01003b98: 63656a62 bjec DCD 1667590754 + 0x01003b9c: 6c435f74 t_Cl DCD 1816354676 + 0x01003ba0: 5f737361 ass_ DCD 1601401697 + 0x01003ba4: 69766544 Devi DCD 1769366852 + 0x01003ba8: 00006563 ce.. DCD 25955 + 0x01003bac: 69206f54 To i DCD 1763733332 + 0x01003bb0: 6974696e niti DCD 1769236846 + 0x01003bb4: 7a696c61 aliz DCD 2053729377 + 0x01003bb8: 65642065 e de DCD 1701060709 + 0x01003bbc: 65636976 vice DCD 1701013878 + 0x01003bc0: 2073253a :%s DCD 544417082 + 0x01003bc4: 6c696166 fail DCD 1818845542 + 0x01003bc8: 202e6465 ed. DCD 539911269 + 0x01003bcc: 20656854 The DCD 543516756 + 0x01003bd0: 6f727265 erro DCD 1869771365 + 0x01003bd4: 6f632072 r co DCD 1868767346 + 0x01003bd8: 69206564 de i DCD 1763730788 + 0x01003bdc: 64252073 s %d DCD 1680154739 + 0x01003be0: 0000000a .... DCD 10 + 0x01003be4: 00000f0f .... DCD 3855 + 0x01003be8: 2d766564 dev- DCD 762733924 + 0x01003bec: 6665723e >ref DCD 1717924414 + 0x01003bf0: 756f635f _cou DCD 1970234207 + 0x01003bf4: 2120746e nt ! DCD 555775086 + 0x01003bf8: 0030203d = 0. DCD 3153981 + $t + i.rt_device_pin_register + rt_device_pin_register + 0x01003bfc: b570 p. PUSH {r4-r6,lr} + 0x01003bfe: 4604 .F MOV r4,r0 + 0x01003c00: 460e .F MOV r6,r1 + 0x01003c02: 4615 .F MOV r5,r2 + 0x01003c04: 2013 . MOVS r0,#0x13 + 0x01003c06: 490b .I LDR r1,[pc,#44] ; [0x1003c34] = 0x20158 + 0x01003c08: 7508 .u STRB r0,[r1,#0x14] + 0x01003c0a: 2000 . MOVS r0,#0 + 0x01003c0c: 61c8 .a STR r0,[r1,#0x1c] + 0x01003c0e: 6208 .b STR r0,[r1,#0x20] + 0x01003c10: 6248 Hb STR r0,[r1,#0x24] + 0x01003c12: 6288 .b STR r0,[r1,#0x28] + 0x01003c14: 62c8 .b STR r0,[r1,#0x2c] + 0x01003c16: 4808 .H LDR r0,[pc,#32] ; [0x1003c38] = 0x1001201 + 0x01003c18: 6308 .c STR r0,[r1,#0x30] + 0x01003c1a: 4808 .H LDR r0,[pc,#32] ; [0x1003c3c] = 0x1001251 + 0x01003c1c: 6348 Hc STR r0,[r1,#0x34] + 0x01003c1e: 4808 .H LDR r0,[pc,#32] ; [0x1003c40] = 0x10011bd + 0x01003c20: 6388 .c STR r0,[r1,#0x38] + 0x01003c22: 4608 .F MOV r0,r1 + 0x01003c24: 6406 .d STR r6,[r0,#0x40] + 0x01003c26: 63c5 .c STR r5,[r0,#0x3c] + 0x01003c28: 2203 ." MOVS r2,#3 + 0x01003c2a: 4621 !F MOV r1,r4 + 0x01003c2c: f000f864 ..d. BL rt_device_register ; 0x1003cf8 + 0x01003c30: 2000 . MOVS r0,#0 + 0x01003c32: bd70 p. POP {r4-r6,pc} + $d + 0x01003c34: 00020158 X... DCD 131416 + 0x01003c38: 01001201 .... DCD 16781825 + 0x01003c3c: 01001251 Q... DCD 16781905 + 0x01003c40: 010011bd .... DCD 16781757 + $t + i.rt_device_read + rt_device_read + 0x01003c44: b5ff .. PUSH {r0-r7,lr} + 0x01003c46: b081 .. SUB sp,sp,#4 + 0x01003c48: 4604 .F MOV r4,r0 + 0x01003c4a: 460d .F MOV r5,r1 + 0x01003c4c: 4616 .F MOV r6,r2 + 0x01003c4e: 2c00 ., CMP r4,#0 + 0x01003c50: d105 .. BNE 0x1003c5e ; rt_device_read + 26 + 0x01003c52: 22ff ." MOVS r2,#0xff + 0x01003c54: 3235 52 ADDS r2,r2,#0x35 + 0x01003c56: 4914 .I LDR r1,[pc,#80] ; [0x1003ca8] = 0x100764e + 0x01003c58: a014 .. ADR r0,{pc}+0x54 ; 0x1003cac + 0x01003c5a: f7fffcd1 .... BL rt_assert_handler ; 0x1003600 + 0x01003c5e: 4620 F MOV r0,r4 + 0x01003c60: f001f904 .... BL rt_object_get_type ; 0x1004e6c + 0x01003c64: 2809 .( CMP r0,#9 + 0x01003c66: d005 .. BEQ 0x1003c74 ; rt_device_read + 48 + 0x01003c68: 22ff ." MOVS r2,#0xff + 0x01003c6a: 3236 62 ADDS r2,r2,#0x36 + 0x01003c6c: 490e .I LDR r1,[pc,#56] ; [0x1003ca8] = 0x100764e + 0x01003c6e: a013 .. ADR r0,{pc}+0x4e ; 0x1003cbc + 0x01003c70: f7fffcc6 .... BL rt_assert_handler ; 0x1003600 + 0x01003c74: 7ea0 .~ LDRB r0,[r4,#0x1a] + 0x01003c76: 2800 .( CMP r0,#0 + 0x01003c78: d105 .. BNE 0x1003c86 ; rt_device_read + 66 + 0x01003c7a: 1e40 @. SUBS r0,r0,#1 + 0x01003c7c: f001fec8 .... BL rt_set_errno ; 0x1005a10 + 0x01003c80: 2000 . MOVS r0,#0 + 0x01003c82: b005 .. ADD sp,sp,#0x14 + 0x01003c84: bdf0 .. POP {r4-r7,pc} + 0x01003c86: 6b20 k LDR r0,[r4,#0x30] + 0x01003c88: 2800 .( CMP r0,#0 + 0x01003c8a: d006 .. BEQ 0x1003c9a ; rt_device_read + 86 + 0x01003c8c: 6b27 'k LDR r7,[r4,#0x30] + 0x01003c8e: 4632 2F MOV r2,r6 + 0x01003c90: 4629 )F MOV r1,r5 + 0x01003c92: 4620 F MOV r0,r4 + 0x01003c94: 9b04 .. LDR r3,[sp,#0x10] + 0x01003c96: 47b8 .G BLX r7 + 0x01003c98: e7f3 .. B 0x1003c82 ; rt_device_read + 62 + 0x01003c9a: 2005 . MOVS r0,#5 + 0x01003c9c: 43c0 .C MVNS r0,r0 + 0x01003c9e: f001feb7 .... BL rt_set_errno ; 0x1005a10 + 0x01003ca2: 2000 . MOVS r0,#0 + 0x01003ca4: e7ed .. B 0x1003c82 ; rt_device_read + 62 + $d + 0x01003ca6: 0000 .. DCW 0 + 0x01003ca8: 0100764e Nv.. DCD 16807502 + 0x01003cac: 20766564 dev DCD 544630116 + 0x01003cb0: 52203d21 != R DCD 1377844513 + 0x01003cb4: 554e5f54 T_NU DCD 1431199572 + 0x01003cb8: 00004c4c LL.. DCD 19532 + 0x01003cbc: 6f5f7472 rt_o DCD 1868526706 + 0x01003cc0: 63656a62 bjec DCD 1667590754 + 0x01003cc4: 65675f74 t_ge DCD 1701273460 + 0x01003cc8: 79745f74 t_ty DCD 2037669748 + 0x01003ccc: 26286570 pe(& DCD 640181616 + 0x01003cd0: 2d766564 dev- DCD 762733924 + 0x01003cd4: 7261703e >par DCD 1918988350 + 0x01003cd8: 29746e65 ent) DCD 695496293 + 0x01003cdc: 203d3d20 == DCD 540884256 + 0x01003ce0: 4f5f5452 RT_O DCD 1331647570 + 0x01003ce4: 63656a62 bjec DCD 1667590754 + 0x01003ce8: 6c435f74 t_Cl DCD 1816354676 + 0x01003cec: 5f737361 ass_ DCD 1601401697 + 0x01003cf0: 69766544 Devi DCD 1769366852 + 0x01003cf4: 00006563 ce.. DCD 25955 + $t + i.rt_device_register + rt_device_register + 0x01003cf8: b570 p. PUSH {r4-r6,lr} + 0x01003cfa: 4604 .F MOV r4,r0 + 0x01003cfc: 460d .F MOV r5,r1 + 0x01003cfe: 4616 .F MOV r6,r2 + 0x01003d00: 2c00 ., CMP r4,#0 + 0x01003d02: d101 .. BNE 0x1003d08 ; rt_device_register + 16 + 0x01003d04: 1e40 @. SUBS r0,r0,#1 + 0x01003d06: bd70 p. POP {r4-r6,pc} + 0x01003d08: 4628 (F MOV r0,r5 + 0x01003d0a: f7fffec3 .... BL rt_device_find ; 0x1003a94 + 0x01003d0e: 2800 .( CMP r0,#0 + 0x01003d10: d002 .. BEQ 0x1003d18 ; rt_device_register + 32 + 0x01003d12: 2000 . MOVS r0,#0 + 0x01003d14: 43c0 .C MVNS r0,r0 + 0x01003d16: e7f6 .. B 0x1003d06 ; rt_device_register + 14 + 0x01003d18: 462a *F MOV r2,r5 + 0x01003d1a: 2109 .! MOVS r1,#9 + 0x01003d1c: 4620 F MOV r0,r4 + 0x01003d1e: f001f8bf .... BL rt_object_init ; 0x1004ea0 + 0x01003d22: 82e6 .. STRH r6,[r4,#0x16] + 0x01003d24: 2000 . MOVS r0,#0 + 0x01003d26: 76a0 .v STRB r0,[r4,#0x1a] + 0x01003d28: 8320 . STRH r0,[r4,#0x18] + 0x01003d2a: bf00 .. NOP + 0x01003d2c: e7eb .. B 0x1003d06 ; rt_device_register + 14 + 0x01003d2e: 0000 .. MOVS r0,r0 + i.rt_device_set_rx_indicate + rt_device_set_rx_indicate + 0x01003d30: b570 p. PUSH {r4-r6,lr} + 0x01003d32: 4604 .F MOV r4,r0 + 0x01003d34: 460d .F MOV r5,r1 + 0x01003d36: 2c00 ., CMP r4,#0 + 0x01003d38: d105 .. BNE 0x1003d46 ; rt_device_set_rx_indicate + 22 + 0x01003d3a: 22ff ." MOVS r2,#0xff + 0x01003d3c: 3297 .2 ADDS r2,r2,#0x97 + 0x01003d3e: 4909 .I LDR r1,[pc,#36] ; [0x1003d64] = 0x100767f + 0x01003d40: a009 .. ADR r0,{pc}+0x28 ; 0x1003d68 + 0x01003d42: f7fffc5d ..]. BL rt_assert_handler ; 0x1003600 + 0x01003d46: 4620 F MOV r0,r4 + 0x01003d48: f001f890 .... BL rt_object_get_type ; 0x1004e6c + 0x01003d4c: 2809 .( CMP r0,#9 + 0x01003d4e: d005 .. BEQ 0x1003d5c ; rt_device_set_rx_indicate + 44 + 0x01003d50: 22ff ." MOVS r2,#0xff + 0x01003d52: 3298 .2 ADDS r2,r2,#0x98 + 0x01003d54: 4903 .I LDR r1,[pc,#12] ; [0x1003d64] = 0x100767f + 0x01003d56: a008 .. ADR r0,{pc}+0x22 ; 0x1003d78 + 0x01003d58: f7fffc52 ..R. BL rt_assert_handler ; 0x1003600 + 0x01003d5c: 61e5 .a STR r5,[r4,#0x1c] + 0x01003d5e: 2000 . MOVS r0,#0 + 0x01003d60: bd70 p. POP {r4-r6,pc} + $d + 0x01003d62: 0000 .. DCW 0 + 0x01003d64: 0100767f .v.. DCD 16807551 + 0x01003d68: 20766564 dev DCD 544630116 + 0x01003d6c: 52203d21 != R DCD 1377844513 + 0x01003d70: 554e5f54 T_NU DCD 1431199572 + 0x01003d74: 00004c4c LL.. DCD 19532 + 0x01003d78: 6f5f7472 rt_o DCD 1868526706 + 0x01003d7c: 63656a62 bjec DCD 1667590754 + 0x01003d80: 65675f74 t_ge DCD 1701273460 + 0x01003d84: 79745f74 t_ty DCD 2037669748 + 0x01003d88: 26286570 pe(& DCD 640181616 + 0x01003d8c: 2d766564 dev- DCD 762733924 + 0x01003d90: 7261703e >par DCD 1918988350 + 0x01003d94: 29746e65 ent) DCD 695496293 + 0x01003d98: 203d3d20 == DCD 540884256 + 0x01003d9c: 4f5f5452 RT_O DCD 1331647570 + 0x01003da0: 63656a62 bjec DCD 1667590754 + 0x01003da4: 6c435f74 t_Cl DCD 1816354676 + 0x01003da8: 5f737361 ass_ DCD 1601401697 + 0x01003dac: 69766544 Devi DCD 1769366852 + 0x01003db0: 00006563 ce.. DCD 25955 + $t + i.rt_device_write + rt_device_write + 0x01003db4: b5ff .. PUSH {r0-r7,lr} + 0x01003db6: b081 .. SUB sp,sp,#4 + 0x01003db8: 4604 .F MOV r4,r0 + 0x01003dba: 460d .F MOV r5,r1 + 0x01003dbc: 4616 .F MOV r6,r2 + 0x01003dbe: 2c00 ., CMP r4,#0 + 0x01003dc0: d105 .. BNE 0x1003dce ; rt_device_write + 26 + 0x01003dc2: 22ff ." MOVS r2,#0xff + 0x01003dc4: 325c \2 ADDS r2,r2,#0x5c + 0x01003dc6: 4914 .I LDR r1,[pc,#80] ; [0x1003e18] = 0x100765d + 0x01003dc8: a014 .. ADR r0,{pc}+0x54 ; 0x1003e1c + 0x01003dca: f7fffc19 .... BL rt_assert_handler ; 0x1003600 + 0x01003dce: 4620 F MOV r0,r4 + 0x01003dd0: f001f84c ..L. BL rt_object_get_type ; 0x1004e6c + 0x01003dd4: 2809 .( CMP r0,#9 + 0x01003dd6: d005 .. BEQ 0x1003de4 ; rt_device_write + 48 + 0x01003dd8: 22ff ." MOVS r2,#0xff + 0x01003dda: 325d ]2 ADDS r2,r2,#0x5d + 0x01003ddc: 490e .I LDR r1,[pc,#56] ; [0x1003e18] = 0x100765d + 0x01003dde: a013 .. ADR r0,{pc}+0x4e ; 0x1003e2c + 0x01003de0: f7fffc0e .... BL rt_assert_handler ; 0x1003600 + 0x01003de4: 7ea0 .~ LDRB r0,[r4,#0x1a] + 0x01003de6: 2800 .( CMP r0,#0 + 0x01003de8: d105 .. BNE 0x1003df6 ; rt_device_write + 66 + 0x01003dea: 1e40 @. SUBS r0,r0,#1 + 0x01003dec: f001fe10 .... BL rt_set_errno ; 0x1005a10 + 0x01003df0: 2000 . MOVS r0,#0 + 0x01003df2: b005 .. ADD sp,sp,#0x14 + 0x01003df4: bdf0 .. POP {r4-r7,pc} + 0x01003df6: 6b60 `k LDR r0,[r4,#0x34] + 0x01003df8: 2800 .( CMP r0,#0 + 0x01003dfa: d006 .. BEQ 0x1003e0a ; rt_device_write + 86 + 0x01003dfc: 6b67 gk LDR r7,[r4,#0x34] + 0x01003dfe: 4632 2F MOV r2,r6 + 0x01003e00: 4629 )F MOV r1,r5 + 0x01003e02: 4620 F MOV r0,r4 + 0x01003e04: 9b04 .. LDR r3,[sp,#0x10] + 0x01003e06: 47b8 .G BLX r7 + 0x01003e08: e7f3 .. B 0x1003df2 ; rt_device_write + 62 + 0x01003e0a: 2005 . MOVS r0,#5 + 0x01003e0c: 43c0 .C MVNS r0,r0 + 0x01003e0e: f001fdff .... BL rt_set_errno ; 0x1005a10 + 0x01003e12: 2000 . MOVS r0,#0 + 0x01003e14: e7ed .. B 0x1003df2 ; rt_device_write + 62 + $d + 0x01003e16: 0000 .. DCW 0 + 0x01003e18: 0100765d ]v.. DCD 16807517 + 0x01003e1c: 20766564 dev DCD 544630116 + 0x01003e20: 52203d21 != R DCD 1377844513 + 0x01003e24: 554e5f54 T_NU DCD 1431199572 + 0x01003e28: 00004c4c LL.. DCD 19532 + 0x01003e2c: 6f5f7472 rt_o DCD 1868526706 + 0x01003e30: 63656a62 bjec DCD 1667590754 + 0x01003e34: 65675f74 t_ge DCD 1701273460 + 0x01003e38: 79745f74 t_ty DCD 2037669748 + 0x01003e3c: 26286570 pe(& DCD 640181616 + 0x01003e40: 2d766564 dev- DCD 762733924 + 0x01003e44: 7261703e >par DCD 1918988350 + 0x01003e48: 29746e65 ent) DCD 695496293 + 0x01003e4c: 203d3d20 == DCD 540884256 + 0x01003e50: 4f5f5452 RT_O DCD 1331647570 + 0x01003e54: 63656a62 bjec DCD 1667590754 + 0x01003e58: 6c435f74 t_Cl DCD 1816354676 + 0x01003e5c: 5f737361 ass_ DCD 1601401697 + 0x01003e60: 69766544 Devi DCD 1769366852 + 0x01003e64: 00006563 ce.. DCD 25955 + $t + i.rt_enter_critical + rt_enter_critical + 0x01003e68: b510 .. PUSH {r4,lr} + 0x01003e6a: f7fcfb29 ..). BL rt_hw_interrupt_disable ; 0x10004c0 + 0x01003e6e: 4604 .F MOV r4,r0 + 0x01003e70: 4804 .H LDR r0,[pc,#16] ; [0x1003e84] = 0x20028 + 0x01003e72: 8800 .. LDRH r0,[r0,#0] + 0x01003e74: 1c40 @. ADDS r0,r0,#1 + 0x01003e76: b200 .. SXTH r0,r0 + 0x01003e78: 4902 .I LDR r1,[pc,#8] ; [0x1003e84] = 0x20028 + 0x01003e7a: 8008 .. STRH r0,[r1,#0] + 0x01003e7c: 4620 F MOV r0,r4 + 0x01003e7e: f7fcfb23 ..#. BL rt_hw_interrupt_enable ; 0x10004c8 + 0x01003e82: bd10 .. POP {r4,pc} + $d + 0x01003e84: 00020028 (... DCD 131112 + $t + i.rt_exit_critical + rt_exit_critical + 0x01003e88: b510 .. PUSH {r4,lr} + 0x01003e8a: f7fcfb19 .... BL rt_hw_interrupt_disable ; 0x10004c0 + 0x01003e8e: 4604 .F MOV r4,r0 + 0x01003e90: 480d .H LDR r0,[pc,#52] ; [0x1003ec8] = 0x20028 + 0x01003e92: 8800 .. LDRH r0,[r0,#0] + 0x01003e94: 1e40 @. SUBS r0,r0,#1 + 0x01003e96: b200 .. SXTH r0,r0 + 0x01003e98: 490b .I LDR r1,[pc,#44] ; [0x1003ec8] = 0x20028 + 0x01003e9a: 8008 .. STRH r0,[r1,#0] + 0x01003e9c: 4608 .F MOV r0,r1 + 0x01003e9e: 2100 .! MOVS r1,#0 + 0x01003ea0: 5e41 A^ LDRSH r1,[r0,r1] + 0x01003ea2: 2900 .) CMP r1,#0 + 0x01003ea4: dc0c .. BGT 0x1003ec0 ; rt_exit_critical + 56 + 0x01003ea6: 2000 . MOVS r0,#0 + 0x01003ea8: 4907 .I LDR r1,[pc,#28] ; [0x1003ec8] = 0x20028 + 0x01003eaa: 8008 .. STRH r0,[r1,#0] + 0x01003eac: 4620 F MOV r0,r4 + 0x01003eae: f7fcfb0b .... BL rt_hw_interrupt_enable ; 0x10004c8 + 0x01003eb2: 4806 .H LDR r0,[pc,#24] ; [0x1003ecc] = 0x2002c + 0x01003eb4: 6800 .h LDR r0,[r0,#0] + 0x01003eb6: 2800 .( CMP r0,#0 + 0x01003eb8: d005 .. BEQ 0x1003ec6 ; rt_exit_critical + 62 + 0x01003eba: f001f8bb .... BL rt_schedule ; 0x1005034 + 0x01003ebe: e002 .. B 0x1003ec6 ; rt_exit_critical + 62 + 0x01003ec0: 4620 F MOV r0,r4 + 0x01003ec2: f7fcfb01 .... BL rt_hw_interrupt_enable ; 0x10004c8 + 0x01003ec6: bd10 .. POP {r4,pc} + $d + 0x01003ec8: 00020028 (... DCD 131112 + 0x01003ecc: 0002002c ,... DCD 131116 + $t + i.rt_free + rt_free + 0x01003ed0: b570 p. PUSH {r4-r6,lr} + 0x01003ed2: 4605 .F MOV r5,r0 + 0x01003ed4: 2d00 .- CMP r5,#0 + 0x01003ed6: d100 .. BNE 0x1003eda ; rt_free + 10 + 0x01003ed8: bd70 p. POP {r4-r6,pc} + 0x01003eda: bf00 .. NOP + 0x01003edc: f7fcfaf0 .... BL rt_hw_interrupt_disable ; 0x10004c0 + 0x01003ee0: 4606 .F MOV r6,r0 + 0x01003ee2: f000facb .... BL rt_interrupt_get_nest ; 0x100447c + 0x01003ee6: 2800 .( CMP r0,#0 + 0x01003ee8: d008 .. BEQ 0x1003efc ; rt_free + 44 + 0x01003eea: 4942 BI LDR r1,[pc,#264] ; [0x1003ff4] = 0x1007c23 + 0x01003eec: a042 B. ADR r0,{pc}+0x10c ; 0x1003ff8 + 0x01003eee: f000faef .... BL rt_kprintf ; 0x10044d0 + 0x01003ef2: 4a4b KJ LDR r2,[pc,#300] ; [0x1004020] = 0x22f + 0x01003ef4: 493f ?I LDR r1,[pc,#252] ; [0x1003ff4] = 0x1007c23 + 0x01003ef6: a04b K. ADR r0,{pc}+0x12e ; 0x1004024 + 0x01003ef8: f7fffb82 .... BL rt_assert_handler ; 0x1003600 + 0x01003efc: 4630 0F MOV r0,r6 + 0x01003efe: f7fcfae3 .... BL rt_hw_interrupt_enable ; 0x10004c8 + 0x01003f02: bf00 .. NOP + 0x01003f04: 07a8 .. LSLS r0,r5,#30 + 0x01003f06: 0f80 .. LSRS r0,r0,#30 + 0x01003f08: 2800 .( CMP r0,#0 + 0x01003f0a: d005 .. BEQ 0x1003f18 ; rt_free + 72 + 0x01003f0c: 4a44 DJ LDR r2,[pc,#272] ; [0x1004020] = 0x22f + 0x01003f0e: 1c92 .. ADDS r2,r2,#2 + 0x01003f10: 4938 8I LDR r1,[pc,#224] ; [0x1003ff4] = 0x1007c23 + 0x01003f12: a045 E. ADR r0,{pc}+0x116 ; 0x1004028 + 0x01003f14: f7fffb74 ..t. BL rt_assert_handler ; 0x1003600 + 0x01003f18: 484f OH LDR r0,[pc,#316] ; [0x1004058] = 0x2013c + 0x01003f1a: 6800 .h LDR r0,[r0,#0] + 0x01003f1c: 4285 .B CMP r5,r0 + 0x01003f1e: d303 .. BCC 0x1003f28 ; rt_free + 88 + 0x01003f20: 484e NH LDR r0,[pc,#312] ; [0x100405c] = 0x20140 + 0x01003f22: 6800 .h LDR r0,[r0,#0] + 0x01003f24: 4285 .B CMP r5,r0 + 0x01003f26: d305 .. BCC 0x1003f34 ; rt_free + 100 + 0x01003f28: 4a3d =J LDR r2,[pc,#244] ; [0x1004020] = 0x22f + 0x01003f2a: 1cd2 .. ADDS r2,r2,#3 + 0x01003f2c: 4931 1I LDR r1,[pc,#196] ; [0x1003ff4] = 0x1007c23 + 0x01003f2e: 484c LH LDR r0,[pc,#304] ; [0x1004060] = 0x1007fe0 + 0x01003f30: f7fffb66 ..f. BL rt_assert_handler ; 0x1003600 + 0x01003f34: bf00 .. NOP + 0x01003f36: 484b KH LDR r0,[pc,#300] ; [0x1004064] = 0x20138 + 0x01003f38: 6800 .h LDR r0,[r0,#0] + 0x01003f3a: 2800 .( CMP r0,#0 + 0x01003f3c: d003 .. BEQ 0x1003f46 ; rt_free + 118 + 0x01003f3e: 4628 (F MOV r0,r5 + 0x01003f40: 4948 HI LDR r1,[pc,#288] ; [0x1004064] = 0x20138 + 0x01003f42: 6809 .h LDR r1,[r1,#0] + 0x01003f44: 4788 .G BLX r1 + 0x01003f46: bf00 .. NOP + 0x01003f48: 4843 CH LDR r0,[pc,#268] ; [0x1004058] = 0x2013c + 0x01003f4a: 6800 .h LDR r0,[r0,#0] + 0x01003f4c: 4285 .B CMP r5,r0 + 0x01003f4e: d303 .. BCC 0x1003f58 ; rt_free + 136 + 0x01003f50: 4842 BH LDR r0,[pc,#264] ; [0x100405c] = 0x20140 + 0x01003f52: 6800 .h LDR r0,[r0,#0] + 0x01003f54: 4285 .B CMP r5,r0 + 0x01003f56: d302 .. BCC 0x1003f5e ; rt_free + 142 + 0x01003f58: bf00 .. NOP + 0x01003f5a: bf00 .. NOP + 0x01003f5c: e7bc .. B 0x1003ed8 ; rt_free + 8 + 0x01003f5e: 462c ,F MOV r4,r5 + 0x01003f60: 3c0c .< SUBS r4,r4,#0xc + 0x01003f62: bf00 .. NOP + 0x01003f64: bf00 .. NOP + 0x01003f66: 2100 .! MOVS r1,#0 + 0x01003f68: 43c9 .C MVNS r1,r1 + 0x01003f6a: 483f ?H LDR r0,[pc,#252] ; [0x1004068] = 0x20584 + 0x01003f6c: f001fa38 ..8. BL rt_sem_take ; 0x10053e0 + 0x01003f70: 8860 `. LDRH r0,[r4,#2] + 0x01003f72: 2800 .( CMP r0,#0 + 0x01003f74: d004 .. BEQ 0x1003f80 ; rt_free + 176 + 0x01003f76: 8820 . LDRH r0,[r4,#0] + 0x01003f78: 21f5 .! MOVS r1,#0xf5 + 0x01003f7a: 0149 I. LSLS r1,r1,#5 + 0x01003f7c: 4288 .B CMP r0,r1 + 0x01003f7e: d008 .. BEQ 0x1003f92 ; rt_free + 194 + 0x01003f80: a03a :. ADR r0,{pc}+0xec ; 0x100406c + 0x01003f82: f000faa5 .... BL rt_kprintf ; 0x10044d0 + 0x01003f86: 8823 #. LDRH r3,[r4,#0] + 0x01003f88: 8862 b. LDRH r2,[r4,#2] + 0x01003f8a: 4621 !F MOV r1,r4 + 0x01003f8c: a03e >. ADR r0,{pc}+0xfc ; 0x1004088 + 0x01003f8e: f000fa9f .... BL rt_kprintf ; 0x10044d0 + 0x01003f92: 8860 `. LDRH r0,[r4,#2] + 0x01003f94: 2800 .( CMP r0,#0 + 0x01003f96: d105 .. BNE 0x1003fa4 ; rt_free + 212 + 0x01003f98: 4a21 !J LDR r2,[pc,#132] ; [0x1004020] = 0x22f + 0x01003f9a: 3222 "2 ADDS r2,r2,#0x22 + 0x01003f9c: 4915 .I LDR r1,[pc,#84] ; [0x1003ff4] = 0x1007c23 + 0x01003f9e: a046 F. ADR r0,{pc}+0x11a ; 0x10040b8 + 0x01003fa0: f7fffb2e .... BL rt_assert_handler ; 0x1003600 + 0x01003fa4: 8820 . LDRH r0,[r4,#0] + 0x01003fa6: 21f5 .! MOVS r1,#0xf5 + 0x01003fa8: 0149 I. LSLS r1,r1,#5 + 0x01003faa: 4288 .B CMP r0,r1 + 0x01003fac: d005 .. BEQ 0x1003fba ; rt_free + 234 + 0x01003fae: 4a1c .J LDR r2,[pc,#112] ; [0x1004020] = 0x22f + 0x01003fb0: 3223 #2 ADDS r2,r2,#0x23 + 0x01003fb2: 4910 .I LDR r1,[pc,#64] ; [0x1003ff4] = 0x1007c23 + 0x01003fb4: a043 C. ADR r0,{pc}+0x110 ; 0x10040c4 + 0x01003fb6: f7fffb23 ..#. BL rt_assert_handler ; 0x1003600 + 0x01003fba: 2000 . MOVS r0,#0 + 0x01003fbc: 8060 `. STRH r0,[r4,#2] + 0x01003fbe: 20f5 . MOVS r0,#0xf5 + 0x01003fc0: 0140 @. LSLS r0,r0,#5 + 0x01003fc2: 8020 . STRH r0,[r4,#0] + 0x01003fc4: 4846 FH LDR r0,[pc,#280] ; [0x10040e0] = 0x20144 + 0x01003fc6: 6800 .h LDR r0,[r0,#0] + 0x01003fc8: 4284 .B CMP r4,r0 + 0x01003fca: d201 .. BCS 0x1003fd0 ; rt_free + 256 + 0x01003fcc: 4844 DH LDR r0,[pc,#272] ; [0x10040e0] = 0x20144 + 0x01003fce: 6004 .` STR r4,[r0,#0] + 0x01003fd0: 4921 !I LDR r1,[pc,#132] ; [0x1004058] = 0x2013c + 0x01003fd2: 6860 `h LDR r0,[r4,#4] + 0x01003fd4: 6809 .h LDR r1,[r1,#0] + 0x01003fd6: 1a61 a. SUBS r1,r4,r1 + 0x01003fd8: 1a40 @. SUBS r0,r0,r1 + 0x01003fda: 4942 BI LDR r1,[pc,#264] ; [0x10040e4] = 0x2014c + 0x01003fdc: 6809 .h LDR r1,[r1,#0] + 0x01003fde: 1a08 .. SUBS r0,r1,r0 + 0x01003fe0: 4940 @I LDR r1,[pc,#256] ; [0x10040e4] = 0x2014c + 0x01003fe2: 6008 .` STR r0,[r1,#0] + 0x01003fe4: 4620 F MOV r0,r4 + 0x01003fe6: f7fff98f .... BL plug_holes ; 0x1003308 + 0x01003fea: 481f .H LDR r0,[pc,#124] ; [0x1004068] = 0x20584 + 0x01003fec: f001f99e .... BL rt_sem_release ; 0x100532c + 0x01003ff0: bf00 .. NOP + 0x01003ff2: e771 q. B 0x1003ed8 ; rt_free + 8 + $d + 0x01003ff4: 01007c23 #|.. DCD 16808995 + 0x01003ff8: 636e7546 Func DCD 1668183366 + 0x01003ffc: 6e6f6974 tion DCD 1852795252 + 0x01004000: 5d73255b [%s] DCD 1567827291 + 0x01004004: 61687320 sha DCD 1634235168 + 0x01004008: 6e206c6c ll n DCD 1847618668 + 0x0100400c: 6220746f ot b DCD 1646294127 + 0x01004010: 73752065 e us DCD 1937055845 + 0x01004014: 69206465 ed i DCD 1763730533 + 0x01004018: 5349206e n IS DCD 1397301358 + 0x0100401c: 00000a52 R... DCD 2642 + 0x01004020: 0000022f /... DCD 559 + 0x01004024: 00000030 0... DCD 48 + 0x01004028: 72282828 (((r DCD 1915234344 + 0x0100402c: 62755f74 t_ub DCD 1651859316 + 0x01004030: 5f657361 ase_ DCD 1600484193 + 0x01004034: 6d722974 t)rm DCD 1836198260 + 0x01004038: 20296d65 em) DCD 539585893 + 0x0100403c: 52282026 & (R DCD 1378361382 + 0x01004040: 4c415f54 T_AL DCD 1279352660 + 0x01004044: 5f4e4749 IGN_ DCD 1598965577 + 0x01004048: 455a4953 SIZE DCD 1163544915 + 0x0100404c: 31202d20 - 1 DCD 824192288 + 0x01004050: 3d202929 )) = DCD 1025517865 + 0x01004054: 0030203d = 0. DCD 3153981 + 0x01004058: 0002013c <... DCD 131388 + 0x0100405c: 00020140 @... DCD 131392 + 0x01004060: 01007fe0 .... DCD 16809952 + 0x01004064: 00020138 8... DCD 131384 + 0x01004068: 00020584 .... DCD 132484 + 0x0100406c: 66206f74 to f DCD 1713401716 + 0x01004070: 20656572 ree DCD 543516018 + 0x01004074: 61622061 a ba DCD 1633820769 + 0x01004078: 61642064 d da DCD 1633951844 + 0x0100407c: 62206174 ta b DCD 1646289268 + 0x01004080: 6b636f6c lock DCD 1801678700 + 0x01004084: 00000a3a :... DCD 2618 + 0x01004088: 3a6d656d mem: DCD 980247917 + 0x0100408c: 25783020 0x% DCD 628633632 + 0x01004090: 2c783830 08x, DCD 746076208 + 0x01004094: 65737520 use DCD 1702065440 + 0x01004098: 6c662064 d fl DCD 1818632292 + 0x0100409c: 203a6761 ag: DCD 540698465 + 0x010040a0: 202c6425 %d, DCD 539780133 + 0x010040a4: 6967616d magi DCD 1768382829 + 0x010040a8: 6f632063 c co DCD 1868767331 + 0x010040ac: 203a6564 de: DCD 540697956 + 0x010040b0: 30257830 0x%0 DCD 807761968 + 0x010040b4: 000a7834 4x.. DCD 686132 + 0x010040b8: 2d6d656d mem- DCD 762144109 + 0x010040bc: 6573753e >use DCD 1702065470 + 0x010040c0: 00000064 d... DCD 100 + 0x010040c4: 2d6d656d mem- DCD 762144109 + 0x010040c8: 67616d3e >mag DCD 1734438206 + 0x010040cc: 3d206369 ic = DCD 1025532777 + 0x010040d0: 4548203d = HE DCD 1162354749 + 0x010040d4: 4d5f5041 AP_M DCD 1298092097 + 0x010040d8: 43494741 AGIC DCD 1128875841 + 0x010040dc: 00000000 .... DCD 0 + 0x010040e0: 00020144 D... DCD 131396 + 0x010040e4: 0002014c L... DCD 131404 + $t + i.rt_hw_board_init + rt_hw_board_init + 0x010040e8: b510 .. PUSH {r4,lr} + 0x010040ea: f7fdfb49 ..I. BL bsp_clock_config ; 0x1001780 + 0x010040ee: 2103 .! MOVS r1,#3 + 0x010040f0: 0409 .. LSLS r1,r1,#16 + 0x010040f2: 4805 .H LDR r0,[pc,#20] ; [0x1004108] = 0x20f10 + 0x010040f4: f001fd3e ..>. BL rt_system_heap_init ; 0x1005b74 + 0x010040f8: f000f976 ..v. BL rt_hw_uart_init ; 0x10043e8 + 0x010040fc: a003 .. ADR r0,{pc}+0x10 ; 0x100410c + 0x010040fe: f7fffbed .... BL rt_console_set_device ; 0x10038dc + 0x01004102: f7fffbc9 .... BL rt_components_board_init ; 0x1003898 + 0x01004106: bd10 .. POP {r4,pc} + $d + 0x01004108: 00020f10 .... DCD 134928 + 0x0100410c: 74726175 uart DCD 1953653109 + 0x01004110: 00000030 0... DCD 48 + $t + i.rt_hw_console_output + rt_hw_console_output + 0x01004114: 4770 pG BX lr + 0x01004116: 0000 .. MOVS r0,r0 + i.rt_hw_hard_fault_exception + rt_hw_hard_fault_exception + 0x01004118: 4604 .F MOV r4,r0 + 0x0100411a: a014 .. ADR r0,{pc}+0x52 ; 0x100416c + 0x0100411c: 69e1 .i LDR r1,[r4,#0x1c] + 0x0100411e: f000f9d7 .... BL rt_kprintf ; 0x10044d0 + 0x01004122: a016 .. ADR r0,{pc}+0x5a ; 0x100417c + 0x01004124: 69a1 .i LDR r1,[r4,#0x18] + 0x01004126: f000f9d3 .... BL rt_kprintf ; 0x10044d0 + 0x0100412a: a018 .. ADR r0,{pc}+0x62 ; 0x100418c + 0x0100412c: 6961 ai LDR r1,[r4,#0x14] + 0x0100412e: f000f9cf .... BL rt_kprintf ; 0x10044d0 + 0x01004132: a01a .. ADR r0,{pc}+0x6a ; 0x100419c + 0x01004134: 6921 !i LDR r1,[r4,#0x10] + 0x01004136: f000f9cb .... BL rt_kprintf ; 0x10044d0 + 0x0100413a: a01c .. ADR r0,{pc}+0x72 ; 0x10041ac + 0x0100413c: 68e1 .h LDR r1,[r4,#0xc] + 0x0100413e: f000f9c7 .... BL rt_kprintf ; 0x10044d0 + 0x01004142: a01e .. ADR r0,{pc}+0x7a ; 0x10041bc + 0x01004144: 68a1 .h LDR r1,[r4,#8] + 0x01004146: f000f9c3 .... BL rt_kprintf ; 0x10044d0 + 0x0100414a: a020 . ADR r0,{pc}+0x82 ; 0x10041cc + 0x0100414c: 6861 ah LDR r1,[r4,#4] + 0x0100414e: f000f9bf .... BL rt_kprintf ; 0x10044d0 + 0x01004152: a022 ". ADR r0,{pc}+0x8a ; 0x10041dc + 0x01004154: 6821 !h LDR r1,[r4,#0] + 0x01004156: f000f9bb .... BL rt_kprintf ; 0x10044d0 + 0x0100415a: 4824 $H LDR r0,[pc,#144] ; [0x10041ec] = 0x2002c + 0x0100415c: 6801 .h LDR r1,[r0,#0] + 0x0100415e: a024 $. ADR r0,{pc}+0x92 ; 0x10041f0 + 0x01004160: f000f9b6 .... BL rt_kprintf ; 0x10044d0 + 0x01004164: f7fefd74 ..t. BL list_thread ; 0x1002c50 + 0x01004168: bf00 .. NOP + 0x0100416a: e7fe .. B 0x100416a ; rt_hw_hard_fault_exception + 82 + $d + 0x0100416c: 3a727370 psr: DCD 980579184 + 0x01004170: 25783020 0x% DCD 628633632 + 0x01004174: 0a783830 08x. DCD 175650864 + 0x01004178: 00000000 .... DCD 0 + 0x0100417c: 3a637020 pc: DCD 979595296 + 0x01004180: 25783020 0x% DCD 628633632 + 0x01004184: 0a783830 08x. DCD 175650864 + 0x01004188: 00000000 .... DCD 0 + 0x0100418c: 3a726c20 lr: DCD 980577312 + 0x01004190: 25783020 0x% DCD 628633632 + 0x01004194: 0a783830 08x. DCD 175650864 + 0x01004198: 00000000 .... DCD 0 + 0x0100419c: 3a323172 r12: DCD 976367986 + 0x010041a0: 25783020 0x% DCD 628633632 + 0x010041a4: 0a783830 08x. DCD 175650864 + 0x010041a8: 00000000 .... DCD 0 + 0x010041ac: 3a333072 r03: DCD 976433266 + 0x010041b0: 25783020 0x% DCD 628633632 + 0x010041b4: 0a783830 08x. DCD 175650864 + 0x010041b8: 00000000 .... DCD 0 + 0x010041bc: 3a323072 r02: DCD 976367730 + 0x010041c0: 25783020 0x% DCD 628633632 + 0x010041c4: 0a783830 08x. DCD 175650864 + 0x010041c8: 00000000 .... DCD 0 + 0x010041cc: 3a313072 r01: DCD 976302194 + 0x010041d0: 25783020 0x% DCD 628633632 + 0x010041d4: 0a783830 08x. DCD 175650864 + 0x010041d8: 00000000 .... DCD 0 + 0x010041dc: 3a303072 r00: DCD 976236658 + 0x010041e0: 25783020 0x% DCD 628633632 + 0x010041e4: 0a783830 08x. DCD 175650864 + 0x010041e8: 00000000 .... DCD 0 + 0x010041ec: 0002002c ,... DCD 131116 + 0x010041f0: 64726168 hard DCD 1685217640 + 0x010041f4: 75616620 fau DCD 1969317408 + 0x010041f8: 6f20746c lt o DCD 1864397932 + 0x010041fc: 6874206e n th DCD 1752440942 + 0x01004200: 64616572 read DCD 1684104562 + 0x01004204: 7325203a : %s DCD 1931812922 + 0x01004208: 0000000a .... DCD 10 + $t + i.rt_hw_pin_init + rt_hw_pin_init + 0x0100420c: b510 .. PUSH {r4,lr} + 0x0100420e: 2200 ." MOVS r2,#0 + 0x01004210: 4903 .I LDR r1,[pc,#12] ; [0x1004220] = 0x1007404 + 0x01004212: a004 .. ADR r0,{pc}+0x12 ; 0x1004224 + 0x01004214: f7fffcf2 .... BL rt_device_pin_register ; 0x1003bfc + 0x01004218: 4604 .F MOV r4,r0 + 0x0100421a: 4620 F MOV r0,r4 + 0x0100421c: bd10 .. POP {r4,pc} + $d + 0x0100421e: 0000 .. DCW 0 + 0x01004220: 01007404 .t.. DCD 16806916 + 0x01004224: 006e6970 pin. DCD 7235952 + $t + i.rt_hw_serial_isr + rt_hw_serial_isr + 0x01004228: b5fe .. PUSH {r1-r7,lr} + 0x0100422a: 4605 .F MOV r5,r0 + 0x0100422c: 460e .F MOV r6,r1 + 0x0100422e: b2f0 .. UXTB r0,r6 + 0x01004230: 2801 .( CMP r0,#1 + 0x01004232: d002 .. BEQ 0x100423a ; rt_hw_serial_isr + 18 + 0x01004234: 2802 .( CMP r0,#2 + 0x01004236: d164 d. BNE 0x1004302 ; rt_hw_serial_isr + 218 + 0x01004238: e05e ^. B 0x10042f8 ; rt_hw_serial_isr + 208 + 0x0100423a: 2700 .' MOVS r7,#0 + 0x0100423c: 43ff .C MVNS r7,r7 + 0x0100423e: 6cec .l LDR r4,[r5,#0x4c] + 0x01004240: 2c00 ., CMP r4,#0 + 0x01004242: d104 .. BNE 0x100424e ; rt_hw_serial_isr + 38 + 0x01004244: 4a30 0J LDR r2,[pc,#192] ; [0x1004308] = 0x50e + 0x01004246: 4931 1I LDR r1,[pc,#196] ; [0x100430c] = 0x10073b7 + 0x01004248: a031 1. ADR r0,{pc}+0xc8 ; 0x1004310 + 0x0100424a: f7fff9d9 .... BL rt_assert_handler ; 0x1003600 + 0x0100424e: e02f /. B 0x10042b0 ; rt_hw_serial_isr + 136 + 0x01004250: 6c28 (l LDR r0,[r5,#0x40] + 0x01004252: 68c1 .h LDR r1,[r0,#0xc] + 0x01004254: 4628 (F MOV r0,r5 + 0x01004256: 4788 .G BLX r1 + 0x01004258: 4607 .F MOV r7,r0 + 0x0100425a: 1c78 x. ADDS r0,r7,#1 + 0x0100425c: 2800 .( CMP r0,#0 + 0x0100425e: d100 .. BNE 0x1004262 ; rt_hw_serial_isr + 58 + 0x01004260: e027 '. B 0x10042b2 ; rt_hw_serial_isr + 138 + 0x01004262: f7fcf92d ..-. BL rt_hw_interrupt_disable ; 0x10004c0 + 0x01004266: 9001 .. STR r0,[sp,#4] + 0x01004268: 88a2 .. LDRH r2,[r4,#4] + 0x0100426a: 6821 !h LDR r1,[r4,#0] + 0x0100426c: 548f .T STRB r7,[r1,r2] + 0x0100426e: 88a0 .. LDRH r0,[r4,#4] + 0x01004270: 1c40 @. ADDS r0,r0,#1 + 0x01004272: 80a0 .. STRH r0,[r4,#4] + 0x01004274: 88a1 .. LDRH r1,[r4,#4] + 0x01004276: 6ca8 .l LDR r0,[r5,#0x48] + 0x01004278: 0180 .. LSLS r0,r0,#6 + 0x0100427a: 0c00 .. LSRS r0,r0,#16 + 0x0100427c: 4281 .B CMP r1,r0 + 0x0100427e: db01 .. BLT 0x1004284 ; rt_hw_serial_isr + 92 + 0x01004280: 2000 . MOVS r0,#0 + 0x01004282: 80a0 .. STRH r0,[r4,#4] + 0x01004284: 88a0 .. LDRH r0,[r4,#4] + 0x01004286: 88e1 .. LDRH r1,[r4,#6] + 0x01004288: 4288 .B CMP r0,r1 + 0x0100428a: d10e .. BNE 0x10042aa ; rt_hw_serial_isr + 130 + 0x0100428c: 88e0 .. LDRH r0,[r4,#6] + 0x0100428e: 1c40 @. ADDS r0,r0,#1 + 0x01004290: 80e0 .. STRH r0,[r4,#6] + 0x01004292: 2001 . MOVS r0,#1 + 0x01004294: 60a0 .` STR r0,[r4,#8] + 0x01004296: 88e1 .. LDRH r1,[r4,#6] + 0x01004298: 6ca8 .l LDR r0,[r5,#0x48] + 0x0100429a: 0180 .. LSLS r0,r0,#6 + 0x0100429c: 0c00 .. LSRS r0,r0,#16 + 0x0100429e: 4281 .B CMP r1,r0 + 0x010042a0: db01 .. BLT 0x10042a6 ; rt_hw_serial_isr + 126 + 0x010042a2: 2000 . MOVS r0,#0 + 0x010042a4: 80e0 .. STRH r0,[r4,#6] + 0x010042a6: f7fdf871 ..q. BL _serial_check_buffer_size ; 0x100138c + 0x010042aa: 9801 .. LDR r0,[sp,#4] + 0x010042ac: f7fcf90c .... BL rt_hw_interrupt_enable ; 0x10004c8 + 0x010042b0: e7ce .. B 0x1004250 ; rt_hw_serial_isr + 40 + 0x010042b2: bf00 .. NOP + 0x010042b4: 69e8 .i LDR r0,[r5,#0x1c] + 0x010042b6: 2800 .( CMP r0,#0 + 0x010042b8: d01d .. BEQ 0x10042f6 ; rt_hw_serial_isr + 206 + 0x010042ba: f7fcf901 .... BL rt_hw_interrupt_disable ; 0x10004c0 + 0x010042be: 9001 .. STR r0,[sp,#4] + 0x010042c0: 88a0 .. LDRH r0,[r4,#4] + 0x010042c2: 88e1 .. LDRH r1,[r4,#6] + 0x010042c4: 4288 .B CMP r0,r1 + 0x010042c6: db03 .. BLT 0x10042d0 ; rt_hw_serial_isr + 168 + 0x010042c8: 88a0 .. LDRH r0,[r4,#4] + 0x010042ca: 88e1 .. LDRH r1,[r4,#6] + 0x010042cc: 1a40 @. SUBS r0,r0,r1 + 0x010042ce: e006 .. B 0x10042de ; rt_hw_serial_isr + 182 + 0x010042d0: 88e0 .. LDRH r0,[r4,#6] + 0x010042d2: 88a1 .. LDRH r1,[r4,#4] + 0x010042d4: 1a41 A. SUBS r1,r0,r1 + 0x010042d6: 6ca8 .l LDR r0,[r5,#0x48] + 0x010042d8: 0180 .. LSLS r0,r0,#6 + 0x010042da: 0c00 .. LSRS r0,r0,#16 + 0x010042dc: 1a40 @. SUBS r0,r0,r1 + 0x010042de: 9000 .. STR r0,[sp,#0] + 0x010042e0: 9801 .. LDR r0,[sp,#4] + 0x010042e2: f7fcf8f1 .... BL rt_hw_interrupt_enable ; 0x10004c8 + 0x010042e6: 9800 .. LDR r0,[sp,#0] + 0x010042e8: 2800 .( CMP r0,#0 + 0x010042ea: d003 .. BEQ 0x10042f4 ; rt_hw_serial_isr + 204 + 0x010042ec: 69ea .i LDR r2,[r5,#0x1c] + 0x010042ee: 4628 (F MOV r0,r5 + 0x010042f0: 9900 .. LDR r1,[sp,#0] + 0x010042f2: 4790 .G BLX r2 + 0x010042f4: bf00 .. NOP + 0x010042f6: e004 .. B 0x1004302 ; rt_hw_serial_isr + 218 + 0x010042f8: 6d2c ,m LDR r4,[r5,#0x50] + 0x010042fa: 4620 F MOV r0,r4 + 0x010042fc: f7fff9d0 .... BL rt_completion_done ; 0x10036a0 + 0x01004300: bf00 .. NOP + 0x01004302: bf00 .. NOP + 0x01004304: bdfe .. POP {r1-r7,pc} + $d + 0x01004306: 0000 .. DCW 0 + 0x01004308: 0000050e .... DCD 1294 + 0x0100430c: 010073b7 .s.. DCD 16806839 + 0x01004310: 665f7872 rx_f DCD 1717532786 + 0x01004314: 206f6669 ifo DCD 544171625 + 0x01004318: 52203d21 != R DCD 1377844513 + 0x0100431c: 554e5f54 T_NU DCD 1431199572 + 0x01004320: 00004c4c LL.. DCD 19532 + $t + i.rt_hw_serial_register + rt_hw_serial_register + 0x01004324: b5ff .. PUSH {r0-r7,lr} + 0x01004326: b081 .. SUB sp,sp,#4 + 0x01004328: 4604 .F MOV r4,r0 + 0x0100432a: 4616 .F MOV r6,r2 + 0x0100432c: 461f .F MOV r7,r3 + 0x0100432e: 2c00 ., CMP r4,#0 + 0x01004330: d104 .. BNE 0x100433c ; rt_hw_serial_register + 24 + 0x01004332: 4a10 .J LDR r2,[pc,#64] ; [0x1004374] = 0x4e2 + 0x01004334: 4910 .I LDR r1,[pc,#64] ; [0x1004378] = 0x10073a1 + 0x01004336: a011 .. ADR r0,{pc}+0x46 ; 0x100437c + 0x01004338: f7fff962 ..b. BL rt_assert_handler ; 0x1003600 + 0x0100433c: 4625 %F MOV r5,r4 + 0x0100433e: 2000 . MOVS r0,#0 + 0x01004340: 462c ,F MOV r4,r5 + 0x01004342: 7528 (u STRB r0,[r5,#0x14] + 0x01004344: 61e8 .a STR r0,[r5,#0x1c] + 0x01004346: 6228 (b STR r0,[r5,#0x20] + 0x01004348: 4811 .H LDR r0,[pc,#68] ; [0x1004390] = 0x1005735 + 0x0100434a: 6268 hb STR r0,[r5,#0x24] + 0x0100434c: 4811 .H LDR r0,[pc,#68] ; [0x1004394] = 0x1005785 + 0x0100434e: 62a8 .b STR r0,[r5,#0x28] + 0x01004350: 4811 .H LDR r0,[pc,#68] ; [0x1004398] = 0x1005591 + 0x01004352: 62e8 .b STR r0,[r5,#0x2c] + 0x01004354: 4811 .H LDR r0,[pc,#68] ; [0x100439c] = 0x1005959 + 0x01004356: 6328 (c STR r0,[r5,#0x30] + 0x01004358: 4811 .H LDR r0,[pc,#68] ; [0x10043a0] = 0x10059b5 + 0x0100435a: 6368 hc STR r0,[r5,#0x34] + 0x0100435c: 4811 .H LDR r0,[pc,#68] ; [0x10043a4] = 0x1005689 + 0x0100435e: 63a8 .c STR r0,[r5,#0x38] + 0x01004360: 63ef .c STR r7,[r5,#0x3c] + 0x01004362: b2b2 .. UXTH r2,r6 + 0x01004364: 4628 (F MOV r0,r5 + 0x01004366: 9902 .. LDR r1,[sp,#8] + 0x01004368: f7fffcc6 .... BL rt_device_register ; 0x1003cf8 + 0x0100436c: 9000 .. STR r0,[sp,#0] + 0x0100436e: 9800 .. LDR r0,[sp,#0] + 0x01004370: b005 .. ADD sp,sp,#0x14 + 0x01004372: bdf0 .. POP {r4-r7,pc} + $d + 0x01004374: 000004e2 .... DCD 1250 + 0x01004378: 010073a1 .s.. DCD 16806817 + 0x0100437c: 69726573 seri DCD 1769104755 + 0x01004380: 21206c61 al ! DCD 555773025 + 0x01004384: 5452203d = RT DCD 1414668349 + 0x01004388: 4c554e5f _NUL DCD 1280659039 + 0x0100438c: 0000004c L... DCD 76 + 0x01004390: 01005735 5W.. DCD 16799541 + 0x01004394: 01005785 .W.. DCD 16799621 + 0x01004398: 01005591 .U.. DCD 16799121 + 0x0100439c: 01005959 YY.. DCD 16800089 + 0x010043a0: 010059b5 .Y.. DCD 16800181 + 0x010043a4: 01005689 .V.. DCD 16799369 + $t + i.rt_hw_stack_init + rt_hw_stack_init + 0x010043a8: b5ff .. PUSH {r0-r7,lr} + 0x010043aa: 460c .F MOV r4,r1 + 0x010043ac: 1d10 .. ADDS r0,r2,#4 + 0x010043ae: 08c0 .. LSRS r0,r0,#3 + 0x010043b0: 00c0 .. LSLS r0,r0,#3 + 0x010043b2: 3840 @8 SUBS r0,r0,#0x40 + 0x010043b4: 4601 .F MOV r1,r0 + 0x010043b6: 2500 .% MOVS r5,#0 + 0x010043b8: e003 .. B 0x10043c2 ; rt_hw_stack_init + 26 + 0x010043ba: 4e0a .N LDR r6,[pc,#40] ; [0x10043e4] = 0xdeadbeef + 0x010043bc: 00af .. LSLS r7,r5,#2 + 0x010043be: 51ce .Q STR r6,[r1,r7] + 0x010043c0: 1c6d m. ADDS r5,r5,#1 + 0x010043c2: 2d10 .- CMP r5,#0x10 + 0x010043c4: d3f9 .. BCC 0x10043ba ; rt_hw_stack_init + 18 + 0x010043c6: 620c .b STR r4,[r1,#0x20] + 0x010043c8: 2600 .& MOVS r6,#0 + 0x010043ca: 624e Nb STR r6,[r1,#0x24] + 0x010043cc: 628e .b STR r6,[r1,#0x28] + 0x010043ce: 62ce .b STR r6,[r1,#0x2c] + 0x010043d0: 630e .c STR r6,[r1,#0x30] + 0x010043d2: 634b Kc STR r3,[r1,#0x34] + 0x010043d4: 9e00 .. LDR r6,[sp,#0] + 0x010043d6: 638e .c STR r6,[r1,#0x38] + 0x010043d8: 2601 .& MOVS r6,#1 + 0x010043da: 0636 6. LSLS r6,r6,#24 + 0x010043dc: 63ce .c STR r6,[r1,#0x3c] + 0x010043de: b004 .. ADD sp,sp,#0x10 + 0x010043e0: bdf0 .. POP {r4-r7,pc} + $d + 0x010043e2: 0000 .. DCW 0 + 0x010043e4: deadbeef .... DCD 3735928559 + $t + i.rt_hw_uart_init + rt_hw_uart_init + 0x010043e8: b51c .. PUSH {r2-r4,lr} + 0x010043ea: 490f .I LDR r1,[pc,#60] ; [0x1004428] = 0x1007480 + 0x010043ec: c903 .. LDM r1,{r0,r1} + 0x010043ee: 9101 .. STR r1,[sp,#4] + 0x010043f0: 9000 .. STR r0,[sp,#0] + 0x010043f2: 2008 . MOVS r0,#8 + 0x010043f4: 490d .I LDR r1,[pc,#52] ; [0x100442c] = 0xf8700 + 0x010043f6: 7048 Hp STRB r0,[r1,#1] + 0x010043f8: 2009 . MOVS r0,#9 + 0x010043fa: 7008 .p STRB r0,[r1,#0] + 0x010043fc: 4c0c .L LDR r4,[pc,#48] ; [0x1004430] = 0x20010 + 0x010043fe: 2000 . MOVS r0,#0 + 0x01004400: 7020 p STRB r0,[r4,#0] + 0x01004402: 2005 . MOVS r0,#5 + 0x01004404: 7060 `p STRB r0,[r4,#1] + 0x01004406: 480b .H LDR r0,[pc,#44] ; [0x1004434] = 0x1007420 + 0x01004408: 490b .I LDR r1,[pc,#44] ; [0x1004438] = 0x2019c + 0x0100440a: 6408 .d STR r0,[r1,#0x40] + 0x0100440c: 4608 .F MOV r0,r1 + 0x0100440e: 9a01 .. LDR r2,[sp,#4] + 0x01004410: 9900 .. LDR r1,[sp,#0] + 0x01004412: 6482 .d STR r2,[r0,#0x48] + 0x01004414: 6441 Ad STR r1,[r0,#0x44] + 0x01004416: 4623 #F MOV r3,r4 + 0x01004418: 22ff ." MOVS r2,#0xff + 0x0100441a: 3204 .2 ADDS r2,#4 + 0x0100441c: a107 .. ADR r1,{pc}+0x20 ; 0x100443c + 0x0100441e: f7ffff81 .... BL rt_hw_serial_register ; 0x1004324 + 0x01004422: 2000 . MOVS r0,#0 + 0x01004424: bd1c .. POP {r2-r4,pc} + $d + 0x01004426: 0000 .. DCW 0 + 0x01004428: 01007480 .t.. DCD 16807040 + 0x0100442c: 000f8700 .... DCD 1017600 + 0x01004430: 00020010 .... DCD 131088 + 0x01004434: 01007420 t.. DCD 16806944 + 0x01004438: 0002019c .... DCD 131484 + 0x0100443c: 74726175 uart DCD 1953653109 + 0x01004440: 00000030 0... DCD 48 + $t + i.rt_interrupt_enter + rt_interrupt_enter + 0x01004444: b510 .. PUSH {r4,lr} + 0x01004446: f7fcf83b ..;. BL rt_hw_interrupt_disable ; 0x10004c0 + 0x0100444a: 4604 .F MOV r4,r0 + 0x0100444c: 4809 .H LDR r0,[pc,#36] ; [0x1004474] = 0x20124 + 0x0100444e: 7800 .x LDRB r0,[r0,#0] + 0x01004450: 1c40 @. ADDS r0,r0,#1 + 0x01004452: 4908 .I LDR r1,[pc,#32] ; [0x1004474] = 0x20124 + 0x01004454: 7008 .p STRB r0,[r1,#0] + 0x01004456: bf00 .. NOP + 0x01004458: 4807 .H LDR r0,[pc,#28] ; [0x1004478] = 0x2011c + 0x0100445a: 6800 .h LDR r0,[r0,#0] + 0x0100445c: 2800 .( CMP r0,#0 + 0x0100445e: d002 .. BEQ 0x1004466 ; rt_interrupt_enter + 34 + 0x01004460: 4805 .H LDR r0,[pc,#20] ; [0x1004478] = 0x2011c + 0x01004462: 6800 .h LDR r0,[r0,#0] + 0x01004464: 4780 .G BLX r0 + 0x01004466: bf00 .. NOP + 0x01004468: 4620 F MOV r0,r4 + 0x0100446a: f7fcf82d ..-. BL rt_hw_interrupt_enable ; 0x10004c8 + 0x0100446e: bf00 .. NOP + 0x01004470: bf00 .. NOP + 0x01004472: bd10 .. POP {r4,pc} + $d + 0x01004474: 00020124 $... DCD 131364 + 0x01004478: 0002011c .... DCD 131356 + $t + i.rt_interrupt_get_nest + rt_interrupt_get_nest + 0x0100447c: b570 p. PUSH {r4-r6,lr} + 0x0100447e: f7fcf81f .... BL rt_hw_interrupt_disable ; 0x10004c0 + 0x01004482: 4605 .F MOV r5,r0 + 0x01004484: 4803 .H LDR r0,[pc,#12] ; [0x1004494] = 0x20124 + 0x01004486: 7804 .x LDRB r4,[r0,#0] + 0x01004488: 4628 (F MOV r0,r5 + 0x0100448a: f7fcf81d .... BL rt_hw_interrupt_enable ; 0x10004c8 + 0x0100448e: 4620 F MOV r0,r4 + 0x01004490: bd70 p. POP {r4-r6,pc} + $d + 0x01004492: 0000 .. DCW 0 + 0x01004494: 00020124 $... DCD 131364 + $t + i.rt_interrupt_leave + rt_interrupt_leave + 0x01004498: b510 .. PUSH {r4,lr} + 0x0100449a: bf00 .. NOP + 0x0100449c: bf00 .. NOP + 0x0100449e: f7fcf80f .... BL rt_hw_interrupt_disable ; 0x10004c0 + 0x010044a2: 4604 .F MOV r4,r0 + 0x010044a4: bf00 .. NOP + 0x010044a6: 4808 .H LDR r0,[pc,#32] ; [0x10044c8] = 0x20120 + 0x010044a8: 6800 .h LDR r0,[r0,#0] + 0x010044aa: 2800 .( CMP r0,#0 + 0x010044ac: d002 .. BEQ 0x10044b4 ; rt_interrupt_leave + 28 + 0x010044ae: 4806 .H LDR r0,[pc,#24] ; [0x10044c8] = 0x20120 + 0x010044b0: 6800 .h LDR r0,[r0,#0] + 0x010044b2: 4780 .G BLX r0 + 0x010044b4: bf00 .. NOP + 0x010044b6: 4805 .H LDR r0,[pc,#20] ; [0x10044cc] = 0x20124 + 0x010044b8: 7800 .x LDRB r0,[r0,#0] + 0x010044ba: 1e40 @. SUBS r0,r0,#1 + 0x010044bc: 4903 .I LDR r1,[pc,#12] ; [0x10044cc] = 0x20124 + 0x010044be: 7008 .p STRB r0,[r1,#0] + 0x010044c0: 4620 F MOV r0,r4 + 0x010044c2: f7fcf801 .... BL rt_hw_interrupt_enable ; 0x10004c8 + 0x010044c6: bd10 .. POP {r4,pc} + $d + 0x010044c8: 00020120 ... DCD 131360 + 0x010044cc: 00020124 $... DCD 131364 + $t + i.rt_kprintf + rt_kprintf + 0x010044d0: b40f .. PUSH {r0-r3} + 0x010044d2: b538 8. PUSH {r3-r5,lr} + 0x010044d4: a805 .. ADD r0,sp,#0x14 + 0x010044d6: 9000 .. STR r0,[sp,#0] + 0x010044d8: 217f .! MOVS r1,#0x7f + 0x010044da: 480f .H LDR r0,[pc,#60] ; [0x1004518] = 0x20504 + 0x010044dc: 9b00 .. LDR r3,[sp,#0] + 0x010044de: 9a04 .. LDR r2,[sp,#0x10] + 0x010044e0: f002f9f4 .... BL rt_vsnprintf ; 0x10068cc + 0x010044e4: 4604 .F MOV r4,r0 + 0x010044e6: 2c7f ., CMP r4,#0x7f + 0x010044e8: d900 .. BLS 0x10044ec ; rt_kprintf + 28 + 0x010044ea: 247f .$ MOVS r4,#0x7f + 0x010044ec: 480b .H LDR r0,[pc,#44] ; [0x100451c] = 0x2004c + 0x010044ee: 6800 .h LDR r0,[r0,#0] + 0x010044f0: 2800 .( CMP r0,#0 + 0x010044f2: d103 .. BNE 0x10044fc ; rt_kprintf + 44 + 0x010044f4: 4808 .H LDR r0,[pc,#32] ; [0x1004518] = 0x20504 + 0x010044f6: f7fffe0d .... BL rt_hw_console_output ; 0x1004114 + 0x010044fa: e006 .. B 0x100450a ; rt_kprintf + 58 + 0x010044fc: 4623 #F MOV r3,r4 + 0x010044fe: 4a06 .J LDR r2,[pc,#24] ; [0x1004518] = 0x20504 + 0x01004500: 2100 .! MOVS r1,#0 + 0x01004502: 4806 .H LDR r0,[pc,#24] ; [0x100451c] = 0x2004c + 0x01004504: 6800 .h LDR r0,[r0,#0] + 0x01004506: f7fffc55 ..U. BL rt_device_write ; 0x1003db4 + 0x0100450a: 2000 . MOVS r0,#0 + 0x0100450c: 9000 .. STR r0,[sp,#0] + 0x0100450e: bc38 8. POP {r3-r5} + 0x01004510: bc08 .. POP {r3} + 0x01004512: b004 .. ADD sp,sp,#0x10 + 0x01004514: 4718 .G BX r3 + $d + 0x01004516: 0000 .. DCW 0 + 0x01004518: 00020504 .... DCD 132356 + 0x0100451c: 0002004c L... DCD 131148 + $t + i.rt_list_init + rt_list_init + 0x01004520: 6040 @` STR r0,[r0,#4] + 0x01004522: 6000 .` STR r0,[r0,#0] + 0x01004524: 4770 pG BX lr + i.rt_list_init + rt_list_init + 0x01004526: 6040 @` STR r0,[r0,#4] + 0x01004528: 6000 .` STR r0,[r0,#0] + 0x0100452a: 4770 pG BX lr + i.rt_list_insert_after + rt_list_insert_after + 0x0100452c: 6802 .h LDR r2,[r0,#0] + 0x0100452e: 6051 Q` STR r1,[r2,#4] + 0x01004530: 6802 .h LDR r2,[r0,#0] + 0x01004532: 600a .` STR r2,[r1,#0] + 0x01004534: 6001 .` STR r1,[r0,#0] + 0x01004536: 6048 H` STR r0,[r1,#4] + 0x01004538: 4770 pG BX lr + i.rt_list_insert_after + rt_list_insert_after + 0x0100453a: 6802 .h LDR r2,[r0,#0] + 0x0100453c: 6051 Q` STR r1,[r2,#4] + 0x0100453e: 6802 .h LDR r2,[r0,#0] + 0x01004540: 600a .` STR r2,[r1,#0] + 0x01004542: 6001 .` STR r1,[r0,#0] + 0x01004544: 6048 H` STR r0,[r1,#4] + 0x01004546: 4770 pG BX lr + i.rt_list_insert_before + rt_list_insert_before + 0x01004548: 6842 Bh LDR r2,[r0,#4] + 0x0100454a: 6011 .` STR r1,[r2,#0] + 0x0100454c: 6842 Bh LDR r2,[r0,#4] + 0x0100454e: 604a J` STR r2,[r1,#4] + 0x01004550: 6041 A` STR r1,[r0,#4] + 0x01004552: 6008 .` STR r0,[r1,#0] + 0x01004554: 4770 pG BX lr + i.rt_list_isempty + rt_list_isempty + 0x01004556: 4601 .F MOV r1,r0 + 0x01004558: 6808 .h LDR r0,[r1,#0] + 0x0100455a: 4288 .B CMP r0,r1 + 0x0100455c: d101 .. BNE 0x1004562 ; rt_list_isempty + 12 + 0x0100455e: 2001 . MOVS r0,#1 + 0x01004560: 4770 pG BX lr + 0x01004562: 2000 . MOVS r0,#0 + 0x01004564: e7fc .. B 0x1004560 ; rt_list_isempty + 10 + i.rt_list_isempty + rt_list_isempty + 0x01004566: 4601 .F MOV r1,r0 + 0x01004568: 6808 .h LDR r0,[r1,#0] + 0x0100456a: 4288 .B CMP r0,r1 + 0x0100456c: d101 .. BNE 0x1004572 ; rt_list_isempty + 12 + 0x0100456e: 2001 . MOVS r0,#1 + 0x01004570: 4770 pG BX lr + 0x01004572: 2000 . MOVS r0,#0 + 0x01004574: e7fc .. B 0x1004570 ; rt_list_isempty + 10 + i.rt_list_isempty + rt_list_isempty + 0x01004576: 4601 .F MOV r1,r0 + 0x01004578: 6808 .h LDR r0,[r1,#0] + 0x0100457a: 4288 .B CMP r0,r1 + 0x0100457c: d101 .. BNE 0x1004582 ; rt_list_isempty + 12 + 0x0100457e: 2001 . MOVS r0,#1 + 0x01004580: 4770 pG BX lr + 0x01004582: 2000 . MOVS r0,#0 + 0x01004584: e7fc .. B 0x1004580 ; rt_list_isempty + 10 + i.rt_list_isempty + rt_list_isempty + 0x01004586: 4601 .F MOV r1,r0 + 0x01004588: 6808 .h LDR r0,[r1,#0] + 0x0100458a: 4288 .B CMP r0,r1 + 0x0100458c: d101 .. BNE 0x1004592 ; rt_list_isempty + 12 + 0x0100458e: 2001 . MOVS r0,#1 + 0x01004590: 4770 pG BX lr + 0x01004592: 2000 . MOVS r0,#0 + 0x01004594: e7fc .. B 0x1004590 ; rt_list_isempty + 10 + i.rt_list_len + rt_list_len + 0x01004596: 4601 .F MOV r1,r0 + 0x01004598: 2000 . MOVS r0,#0 + 0x0100459a: 460a .F MOV r2,r1 + 0x0100459c: e001 .. B 0x10045a2 ; rt_list_len + 12 + 0x0100459e: 6812 .h LDR r2,[r2,#0] + 0x010045a0: 1c40 @. ADDS r0,r0,#1 + 0x010045a2: 6813 .h LDR r3,[r2,#0] + 0x010045a4: 428b .B CMP r3,r1 + 0x010045a6: d1fa .. BNE 0x100459e ; rt_list_len + 8 + 0x010045a8: 4770 pG BX lr + i.rt_list_remove + rt_list_remove + 0x010045aa: 6802 .h LDR r2,[r0,#0] + 0x010045ac: 6841 Ah LDR r1,[r0,#4] + 0x010045ae: 6051 Q` STR r1,[r2,#4] + 0x010045b0: 6842 Bh LDR r2,[r0,#4] + 0x010045b2: 6801 .h LDR r1,[r0,#0] + 0x010045b4: 6011 .` STR r1,[r2,#0] + 0x010045b6: 6040 @` STR r0,[r0,#4] + 0x010045b8: 6000 .` STR r0,[r0,#0] + 0x010045ba: 4770 pG BX lr + i.rt_list_remove + rt_list_remove + 0x010045bc: 6802 .h LDR r2,[r0,#0] + 0x010045be: 6841 Ah LDR r1,[r0,#4] + 0x010045c0: 6051 Q` STR r1,[r2,#4] + 0x010045c2: 6842 Bh LDR r2,[r0,#4] + 0x010045c4: 6801 .h LDR r1,[r0,#0] + 0x010045c6: 6011 .` STR r1,[r2,#0] + 0x010045c8: 6040 @` STR r0,[r0,#4] + 0x010045ca: 6000 .` STR r0,[r0,#0] + 0x010045cc: 4770 pG BX lr + i.rt_list_remove + rt_list_remove + 0x010045ce: 6802 .h LDR r2,[r0,#0] + 0x010045d0: 6841 Ah LDR r1,[r0,#4] + 0x010045d2: 6051 Q` STR r1,[r2,#4] + 0x010045d4: 6842 Bh LDR r2,[r0,#4] + 0x010045d6: 6801 .h LDR r1,[r0,#0] + 0x010045d8: 6011 .` STR r1,[r2,#0] + 0x010045da: 6040 @` STR r0,[r0,#4] + 0x010045dc: 6000 .` STR r0,[r0,#0] + 0x010045de: 4770 pG BX lr + i.rt_malloc + rt_malloc + 0x010045e0: b5fe .. PUSH {r1-r7,lr} + 0x010045e2: 4605 .F MOV r5,r0 + 0x010045e4: 2d00 .- CMP r5,#0 + 0x010045e6: d100 .. BNE 0x10045ea ; rt_malloc + 10 + 0x010045e8: bdfe .. POP {r1-r7,pc} + 0x010045ea: bf00 .. NOP + 0x010045ec: f7fbff68 ..h. BL rt_hw_interrupt_disable ; 0x10004c0 + 0x010045f0: 9000 .. STR r0,[sp,#0] + 0x010045f2: f7ffff43 ..C. BL rt_interrupt_get_nest ; 0x100447c + 0x010045f6: 2800 .( CMP r0,#0 + 0x010045f8: d009 .. BEQ 0x100460e ; rt_malloc + 46 + 0x010045fa: 497e ~I LDR r1,[pc,#504] ; [0x10047f4] = 0x1007c0e + 0x010045fc: a07e ~. ADR r0,{pc}+0x1fc ; 0x10047f8 + 0x010045fe: f7ffff67 ..g. BL rt_kprintf ; 0x10044d0 + 0x01004602: 22ff ." MOVS r2,#0xff + 0x01004604: 3219 .2 ADDS r2,r2,#0x19 + 0x01004606: 497b {I LDR r1,[pc,#492] ; [0x10047f4] = 0x1007c0e + 0x01004608: a085 .. ADR r0,{pc}+0x218 ; 0x1004820 + 0x0100460a: f7fefff9 .... BL rt_assert_handler ; 0x1003600 + 0x0100460e: 9800 .. LDR r0,[sp,#0] + 0x01004610: f7fbff5a ..Z. BL rt_hw_interrupt_enable ; 0x10004c8 + 0x01004614: bf00 .. NOP + 0x01004616: 1ce8 .. ADDS r0,r5,#3 + 0x01004618: 0880 .. LSRS r0,r0,#2 + 0x0100461a: 0080 .. LSLS r0,r0,#2 + 0x0100461c: 42a8 .B CMP r0,r5 + 0x0100461e: d001 .. BEQ 0x1004624 ; rt_malloc + 68 + 0x01004620: bf00 .. NOP + 0x01004622: e001 .. B 0x1004628 ; rt_malloc + 72 + 0x01004624: bf00 .. NOP + 0x01004626: bf00 .. NOP + 0x01004628: 1ce8 .. ADDS r0,r5,#3 + 0x0100462a: 0885 .. LSRS r5,r0,#2 + 0x0100462c: 00ad .. LSLS r5,r5,#2 + 0x0100462e: 487d }H LDR r0,[pc,#500] ; [0x1004824] = 0x20148 + 0x01004630: 6800 .h LDR r0,[r0,#0] + 0x01004632: 4285 .B CMP r5,r0 + 0x01004634: d903 .. BLS 0x100463e ; rt_malloc + 94 + 0x01004636: bf00 .. NOP + 0x01004638: bf00 .. NOP + 0x0100463a: 2000 . MOVS r0,#0 + 0x0100463c: e7d4 .. B 0x10045e8 ; rt_malloc + 8 + 0x0100463e: 2d0c .- CMP r5,#0xc + 0x01004640: d200 .. BCS 0x1004644 ; rt_malloc + 100 + 0x01004642: 250c .% MOVS r5,#0xc + 0x01004644: 2100 .! MOVS r1,#0 + 0x01004646: 43c9 .C MVNS r1,r1 + 0x01004648: 4877 wH LDR r0,[pc,#476] ; [0x1004828] = 0x20584 + 0x0100464a: f000fec9 .... BL rt_sem_take ; 0x10053e0 + 0x0100464e: 4877 wH LDR r0,[pc,#476] ; [0x100482c] = 0x20144 + 0x01004650: 6800 .h LDR r0,[r0,#0] + 0x01004652: 4977 wI LDR r1,[pc,#476] ; [0x1004830] = 0x2013c + 0x01004654: 6809 .h LDR r1,[r1,#0] + 0x01004656: 1a46 F. SUBS r6,r0,r1 + 0x01004658: e0c0 .. B 0x10047dc ; rt_malloc + 508 + 0x0100465a: 4875 uH LDR r0,[pc,#468] ; [0x1004830] = 0x2013c + 0x0100465c: 6800 .h LDR r0,[r0,#0] + 0x0100465e: 1984 .. ADDS r4,r0,r6 + 0x01004660: 8860 `. LDRH r0,[r4,#2] + 0x01004662: 2800 .( CMP r0,#0 + 0x01004664: d17d }. BNE 0x1004762 ; rt_malloc + 386 + 0x01004666: 4630 0F MOV r0,r6 + 0x01004668: 300c .0 ADDS r0,r0,#0xc + 0x0100466a: 6861 ah LDR r1,[r4,#4] + 0x0100466c: 1a08 .. SUBS r0,r1,r0 + 0x0100466e: 42a8 .B CMP r0,r5 + 0x01004670: d377 w. BCC 0x1004762 ; rt_malloc + 386 + 0x01004672: 4630 0F MOV r0,r6 + 0x01004674: 300c .0 ADDS r0,r0,#0xc + 0x01004676: 6861 ah LDR r1,[r4,#4] + 0x01004678: 1a09 .. SUBS r1,r1,r0 + 0x0100467a: 4628 (F MOV r0,r5 + 0x0100467c: 3018 .0 ADDS r0,r0,#0x18 + 0x0100467e: 4281 .B CMP r1,r0 + 0x01004680: d330 0. BCC 0x10046e4 ; rt_malloc + 260 + 0x01004682: 4630 0F MOV r0,r6 + 0x01004684: 300c .0 ADDS r0,r0,#0xc + 0x01004686: 1940 @. ADDS r0,r0,r5 + 0x01004688: 9001 .. STR r0,[sp,#4] + 0x0100468a: 4869 iH LDR r0,[pc,#420] ; [0x1004830] = 0x2013c + 0x0100468c: 6801 .h LDR r1,[r0,#0] + 0x0100468e: 9801 .. LDR r0,[sp,#4] + 0x01004690: 180f .. ADDS r7,r1,r0 + 0x01004692: 20f5 . MOVS r0,#0xf5 + 0x01004694: 0140 @. LSLS r0,r0,#5 + 0x01004696: 8038 8. STRH r0,[r7,#0] + 0x01004698: 2000 . MOVS r0,#0 + 0x0100469a: 8078 x. STRH r0,[r7,#2] + 0x0100469c: 6860 `h LDR r0,[r4,#4] + 0x0100469e: 6078 x` STR r0,[r7,#4] + 0x010046a0: 60be .` STR r6,[r7,#8] + 0x010046a2: 9801 .. LDR r0,[sp,#4] + 0x010046a4: 6060 `` STR r0,[r4,#4] + 0x010046a6: 2001 . MOVS r0,#1 + 0x010046a8: 8060 `. STRH r0,[r4,#2] + 0x010046aa: 485e ^H LDR r0,[pc,#376] ; [0x1004824] = 0x20148 + 0x010046ac: 6879 yh LDR r1,[r7,#4] + 0x010046ae: 6800 .h LDR r0,[r0,#0] + 0x010046b0: 300c .0 ADDS r0,r0,#0xc + 0x010046b2: 4281 .B CMP r1,r0 + 0x010046b4: d005 .. BEQ 0x10046c2 ; rt_malloc + 226 + 0x010046b6: 9801 .. LDR r0,[sp,#4] + 0x010046b8: 4a5d ]J LDR r2,[pc,#372] ; [0x1004830] = 0x2013c + 0x010046ba: 6879 yh LDR r1,[r7,#4] + 0x010046bc: 6812 .h LDR r2,[r2,#0] + 0x010046be: 1889 .. ADDS r1,r1,r2 + 0x010046c0: 6088 .` STR r0,[r1,#8] + 0x010046c2: 485c \H LDR r0,[pc,#368] ; [0x1004834] = 0x2014c + 0x010046c4: 6801 .h LDR r1,[r0,#0] + 0x010046c6: 4628 (F MOV r0,r5 + 0x010046c8: 300c .0 ADDS r0,r0,#0xc + 0x010046ca: 1808 .. ADDS r0,r1,r0 + 0x010046cc: 4959 YI LDR r1,[pc,#356] ; [0x1004834] = 0x2014c + 0x010046ce: 6008 .` STR r0,[r1,#0] + 0x010046d0: 4859 YH LDR r0,[pc,#356] ; [0x1004838] = 0x20150 + 0x010046d2: 6800 .h LDR r0,[r0,#0] + 0x010046d4: 6809 .h LDR r1,[r1,#0] + 0x010046d6: 4288 .B CMP r0,r1 + 0x010046d8: d219 .. BCS 0x100470e ; rt_malloc + 302 + 0x010046da: 4856 VH LDR r0,[pc,#344] ; [0x1004834] = 0x2014c + 0x010046dc: 6800 .h LDR r0,[r0,#0] + 0x010046de: 4956 VI LDR r1,[pc,#344] ; [0x1004838] = 0x20150 + 0x010046e0: 6008 .` STR r0,[r1,#0] + 0x010046e2: e014 .. B 0x100470e ; rt_malloc + 302 + 0x010046e4: 2001 . MOVS r0,#1 + 0x010046e6: 8060 `. STRH r0,[r4,#2] + 0x010046e8: 4951 QI LDR r1,[pc,#324] ; [0x1004830] = 0x2013c + 0x010046ea: 6860 `h LDR r0,[r4,#4] + 0x010046ec: 6809 .h LDR r1,[r1,#0] + 0x010046ee: 1a61 a. SUBS r1,r4,r1 + 0x010046f0: 1a40 @. SUBS r0,r0,r1 + 0x010046f2: 4950 PI LDR r1,[pc,#320] ; [0x1004834] = 0x2014c + 0x010046f4: 6809 .h LDR r1,[r1,#0] + 0x010046f6: 1840 @. ADDS r0,r0,r1 + 0x010046f8: 494e NI LDR r1,[pc,#312] ; [0x1004834] = 0x2014c + 0x010046fa: 6008 .` STR r0,[r1,#0] + 0x010046fc: 484e NH LDR r0,[pc,#312] ; [0x1004838] = 0x20150 + 0x010046fe: 6800 .h LDR r0,[r0,#0] + 0x01004700: 6809 .h LDR r1,[r1,#0] + 0x01004702: 4288 .B CMP r0,r1 + 0x01004704: d203 .. BCS 0x100470e ; rt_malloc + 302 + 0x01004706: 484b KH LDR r0,[pc,#300] ; [0x1004834] = 0x2014c + 0x01004708: 6800 .h LDR r0,[r0,#0] + 0x0100470a: 494b KI LDR r1,[pc,#300] ; [0x1004838] = 0x20150 + 0x0100470c: 6008 .` STR r0,[r1,#0] + 0x0100470e: 20f5 . MOVS r0,#0xf5 + 0x01004710: 0140 @. LSLS r0,r0,#5 + 0x01004712: 8020 . STRH r0,[r4,#0] + 0x01004714: 4845 EH LDR r0,[pc,#276] ; [0x100482c] = 0x20144 + 0x01004716: 6800 .h LDR r0,[r0,#0] + 0x01004718: 4284 .B CMP r4,r0 + 0x0100471a: d126 &. BNE 0x100476a ; rt_malloc + 394 + 0x0100471c: e007 .. B 0x100472e ; rt_malloc + 334 + 0x0100471e: 4843 CH LDR r0,[pc,#268] ; [0x100482c] = 0x20144 + 0x01004720: 6800 .h LDR r0,[r0,#0] + 0x01004722: 6840 @h LDR r0,[r0,#4] + 0x01004724: 4942 BI LDR r1,[pc,#264] ; [0x1004830] = 0x2013c + 0x01004726: 6809 .h LDR r1,[r1,#0] + 0x01004728: 1840 @. ADDS r0,r0,r1 + 0x0100472a: 4940 @I LDR r1,[pc,#256] ; [0x100482c] = 0x20144 + 0x0100472c: 6008 .` STR r0,[r1,#0] + 0x0100472e: 483f ?H LDR r0,[pc,#252] ; [0x100482c] = 0x20144 + 0x01004730: 6800 .h LDR r0,[r0,#0] + 0x01004732: 8840 @. LDRH r0,[r0,#2] + 0x01004734: 2800 .( CMP r0,#0 + 0x01004736: d005 .. BEQ 0x1004744 ; rt_malloc + 356 + 0x01004738: 483c use DCD 1702065470 + 0x01004864: 00292964 d)). DCD 2697572 + 0x01004868: 0100803c <... DCD 16810044 + 0x0100486c: 01007f94 .... DCD 16809876 + 0x01004870: 72282828 (((r DCD 1915234344 + 0x01004874: 62755f74 t_ub DCD 1651859316 + 0x01004878: 5f657361 ase_ DCD 1600484193 + 0x0100487c: 656d2974 t)me DCD 1701652852 + 0x01004880: 2620296d m) & DCD 639641965 + 0x01004884: 54522820 (RT DCD 1414670368 + 0x01004888: 494c415f _ALI DCD 1229734239 + 0x0100488c: 535f4e47 GN_S DCD 1398754887 + 0x01004890: 20455a49 IZE DCD 541416009 + 0x01004894: 2931202d - 1) DCD 691085357 + 0x01004898: 3d3d2029 ) == DCD 1027416105 + 0x0100489c: 00003020 0.. DCD 12320 + 0x010048a0: 00020134 4... DCD 131380 + $t + i.rt_memcpy + rt_memcpy + 0x010048a4: b5f7 .. PUSH {r0-r2,r4-r7,lr} + 0x010048a6: 4616 .F MOV r6,r2 + 0x010048a8: 9c00 .. LDR r4,[sp,#0] + 0x010048aa: 9d01 .. LDR r5,[sp,#4] + 0x010048ac: 4633 3F MOV r3,r6 + 0x010048ae: 2b10 .+ CMP r3,#0x10 + 0x010048b0: d31c .. BCC 0x10048ec ; rt_memcpy + 72 + 0x010048b2: 07a8 .. LSLS r0,r5,#30 + 0x010048b4: 0f80 .. LSRS r0,r0,#30 + 0x010048b6: 07a7 .. LSLS r7,r4,#30 + 0x010048b8: 0fbf .. LSRS r7,r7,#30 + 0x010048ba: 4338 8C ORRS r0,r0,r7 + 0x010048bc: 2800 .( CMP r0,#0 + 0x010048be: d115 .. BNE 0x10048ec ; rt_memcpy + 72 + 0x010048c0: 4621 !F MOV r1,r4 + 0x010048c2: 462a *F MOV r2,r5 + 0x010048c4: e008 .. B 0x10048d8 ; rt_memcpy + 52 + 0x010048c6: ca01 .. LDM r2!,{r0} + 0x010048c8: c101 .. STM r1!,{r0} + 0x010048ca: ca01 .. LDM r2!,{r0} + 0x010048cc: c101 .. STM r1!,{r0} + 0x010048ce: ca01 .. LDM r2!,{r0} + 0x010048d0: c101 .. STM r1!,{r0} + 0x010048d2: ca01 .. LDM r2!,{r0} + 0x010048d4: c101 .. STM r1!,{r0} + 0x010048d6: 3b10 .; SUBS r3,r3,#0x10 + 0x010048d8: 2b10 .+ CMP r3,#0x10 + 0x010048da: d2f4 .. BCS 0x10048c6 ; rt_memcpy + 34 + 0x010048dc: e002 .. B 0x10048e4 ; rt_memcpy + 64 + 0x010048de: ca01 .. LDM r2!,{r0} + 0x010048e0: c101 .. STM r1!,{r0} + 0x010048e2: 1f1b .. SUBS r3,r3,#4 + 0x010048e4: 2b04 .+ CMP r3,#4 + 0x010048e6: d2fa .. BCS 0x10048de ; rt_memcpy + 58 + 0x010048e8: 460c .F MOV r4,r1 + 0x010048ea: 4615 .F MOV r5,r2 + 0x010048ec: e003 .. B 0x10048f6 ; rt_memcpy + 82 + 0x010048ee: 7828 (x LDRB r0,[r5,#0] + 0x010048f0: 7020 p STRB r0,[r4,#0] + 0x010048f2: 1c6d m. ADDS r5,r5,#1 + 0x010048f4: 1c64 d. ADDS r4,r4,#1 + 0x010048f6: 4618 .F MOV r0,r3 + 0x010048f8: 1e5b [. SUBS r3,r3,#1 + 0x010048fa: 2800 .( CMP r0,#0 + 0x010048fc: d1f7 .. BNE 0x10048ee ; rt_memcpy + 74 + 0x010048fe: 9800 .. LDR r0,[sp,#0] + 0x01004900: bdfe .. POP {r1-r7,pc} + 0x01004902: 0000 .. MOVS r0,r0 + i.rt_memheap_dump + rt_memheap_dump + 0x01004904: b5f8 .. PUSH {r3-r7,lr} + 0x01004906: 4605 .F MOV r5,r0 + 0x01004908: 2d00 .- CMP r5,#0 + 0x0100490a: d100 .. BNE 0x100490e ; rt_memheap_dump + 10 + 0x0100490c: bdf8 .. POP {r3-r7,pc} + 0x0100490e: 4628 (F MOV r0,r5 + 0x01004910: f000faac .... BL rt_object_get_type ; 0x1004e6c + 0x01004914: 2807 .( CMP r0,#7 + 0x01004916: d004 .. BEQ 0x1004922 ; rt_memheap_dump + 30 + 0x01004918: 4a2a *J LDR r2,[pc,#168] ; [0x10049c4] = 0x2b1 + 0x0100491a: 492b +I LDR r1,[pc,#172] ; [0x10049c8] = 0x1007b22 + 0x0100491c: a02b +. ADR r0,{pc}+0xb0 ; 0x10049cc + 0x0100491e: f7fefe6f ..o. BL rt_assert_handler ; 0x1003600 + 0x01004922: 69a9 .i LDR r1,[r5,#0x18] + 0x01004924: 6968 hi LDR r0,[r5,#0x14] + 0x01004926: 1840 @. ADDS r0,r0,r1 + 0x01004928: 9000 .. STR r0,[sp,#0] + 0x0100492a: 462a *F MOV r2,r5 + 0x0100492c: 2108 .! MOVS r1,#8 + 0x0100492e: a037 7. ADR r0,{pc}+0xde ; 0x1004a0c + 0x01004930: 696b ki LDR r3,[r5,#0x14] + 0x01004932: f7fffdcd .... BL rt_kprintf ; 0x10044d0 + 0x01004936: a03d =. ADR r0,{pc}+0xf6 ; 0x1004a2c + 0x01004938: f7fffdca .... BL rt_kprintf ; 0x10044d0 + 0x0100493c: 2100 .! MOVS r1,#0 + 0x0100493e: 43c9 .C MVNS r1,r1 + 0x01004940: 4628 (F MOV r0,r5 + 0x01004942: 3044 D0 ADDS r0,r0,#0x44 + 0x01004944: f000fd4c ..L. BL rt_sem_take ; 0x10053e0 + 0x01004948: 6a6c lj LDR r4,[r5,#0x24] + 0x0100494a: 69a9 .i LDR r1,[r5,#0x18] + 0x0100494c: 6968 hi LDR r0,[r5,#0x14] + 0x0100494e: 1840 @. ADDS r0,r0,r1 + 0x01004950: 4606 .F MOV r6,r0 + 0x01004952: 3e18 .> SUBS r6,r6,#0x18 + 0x01004954: e02e .. B 0x10049b4 ; rt_memheap_dump + 176 + 0x01004956: 7820 x LDRB r0,[r4,#0] + 0x01004958: 07c0 .. LSLS r0,r0,#31 + 0x0100495a: 0fc0 .. LSRS r0,r0,#31 + 0x0100495c: 2800 .( CMP r0,#0 + 0x0100495e: d00a .. BEQ 0x1004976 ; rt_memheap_dump + 114 + 0x01004960: 6820 h LDR r0,[r4,#0] + 0x01004962: 0840 @. LSRS r0,r0,#1 + 0x01004964: 0040 @. LSLS r0,r0,#1 + 0x01004966: 4939 9I LDR r1,[pc,#228] ; [0x1004a4c] = 0x1ea01ea0 + 0x01004968: 4288 .B CMP r0,r1 + 0x0100496a: d004 .. BEQ 0x1004976 ; rt_memheap_dump + 114 + 0x0100496c: 4621 !F MOV r1,r4 + 0x0100496e: 3118 .1 ADDS r1,r1,#0x18 + 0x01004970: a037 7. ADR r0,{pc}+0xe0 ; 0x1004a50 + 0x01004972: f7fffdad .... BL rt_kprintf ; 0x10044d0 + 0x01004976: 4935 5I LDR r1,[pc,#212] ; [0x1004a4c] = 0x1ea01ea0 + 0x01004978: 1c49 I. ADDS r1,r1,#1 + 0x0100497a: 6820 h LDR r0,[r4,#0] + 0x0100497c: 4288 .B CMP r0,r1 + 0x0100497e: d10f .. BNE 0x10049a0 ; rt_memheap_dump + 156 + 0x01004980: 68a0 .h LDR r0,[r4,#8] + 0x01004982: 1b00 .. SUBS r0,r0,r4 + 0x01004984: 4602 .F MOV r2,r0 + 0x01004986: 3a18 .: SUBS r2,r2,#0x18 + 0x01004988: 4621 !F MOV r1,r4 + 0x0100498a: 3118 .1 ADDS r1,r1,#0x18 + 0x0100498c: a032 2. ADR r0,{pc}+0xcc ; 0x1004a58 + 0x0100498e: f7fffd9f .... BL rt_kprintf ; 0x10044d0 + 0x01004992: 4620 F MOV r0,r4 + 0x01004994: f7fcfbac .... BL _memheap_dump_tag ; 0x10010f0 + 0x01004998: a033 3. ADR r0,{pc}+0xd0 ; 0x1004a68 + 0x0100499a: f7fffd99 .... BL rt_kprintf ; 0x10044d0 + 0x0100499e: e008 .. B 0x10049b2 ; rt_memheap_dump + 174 + 0x010049a0: 68a0 .h LDR r0,[r4,#8] + 0x010049a2: 1b00 .. SUBS r0,r0,r4 + 0x010049a4: 4602 .F MOV r2,r0 + 0x010049a6: 3a18 .: SUBS r2,r2,#0x18 + 0x010049a8: 4621 !F MOV r1,r4 + 0x010049aa: 3118 .1 ADDS r1,r1,#0x18 + 0x010049ac: a02f /. ADR r0,{pc}+0xc0 ; 0x1004a6c + 0x010049ae: f7fffd8f .... BL rt_kprintf ; 0x10044d0 + 0x010049b2: 68a4 .h LDR r4,[r4,#8] + 0x010049b4: 42b4 .B CMP r4,r6 + 0x010049b6: d3ce .. BCC 0x1004956 ; rt_memheap_dump + 82 + 0x010049b8: 4628 (F MOV r0,r5 + 0x010049ba: 3044 D0 ADDS r0,r0,#0x44 + 0x010049bc: f000fcb6 .... BL rt_sem_release ; 0x100532c + 0x010049c0: 2000 . MOVS r0,#0 + 0x010049c2: e7a3 .. B 0x100490c ; rt_memheap_dump + 8 + $d + 0x010049c4: 000002b1 .... DCD 689 + 0x010049c8: 01007b22 "{.. DCD 16808738 + 0x010049cc: 6f5f7472 rt_o DCD 1868526706 + 0x010049d0: 63656a62 bjec DCD 1667590754 + 0x010049d4: 65675f74 t_ge DCD 1701273460 + 0x010049d8: 79745f74 t_ty DCD 2037669748 + 0x010049dc: 26286570 pe(& DCD 640181616 + 0x010049e0: 70616568 heap DCD 1885431144 + 0x010049e4: 61703e2d ->pa DCD 1634745901 + 0x010049e8: 746e6572 rent DCD 1953391986 + 0x010049ec: 3d3d2029 ) == DCD 1027416105 + 0x010049f0: 5f545220 RT_ DCD 1599361568 + 0x010049f4: 656a624f Obje DCD 1701470799 + 0x010049f8: 435f7463 ct_C DCD 1130329187 + 0x010049fc: 7373616c lass DCD 1936941420 + 0x01004a00: 6d654d5f _Mem DCD 1835355487 + 0x01004a04: 70616548 Heap DCD 1885431112 + 0x01004a08: 00000000 .... DCD 0 + 0x01004a0c: 2e255b0a .[%. DCD 774200074 + 0x01004a10: 205d732a *s] DCD 542995242 + 0x01004a14: 2578305b [0x% DCD 628633691 + 0x01004a18: 20783830 08x DCD 544749616 + 0x01004a1c: 7830202d - 0x DCD 2016419885 + 0x01004a20: 78383025 %08x DCD 2016948261 + 0x01004a24: 0a3e2d5d ]->. DCD 171847005 + 0x01004a28: 00000000 .... DCD 0 + 0x01004a2c: 2d2d2d2d ---- DCD 757935405 + 0x01004a30: 2d2d2d2d ---- DCD 757935405 + 0x01004a34: 2d2d2d2d ---- DCD 757935405 + 0x01004a38: 2d2d2d2d ---- DCD 757935405 + 0x01004a3c: 2d2d2d2d ---- DCD 757935405 + 0x01004a40: 2d2d2d2d ---- DCD 757935405 + 0x01004a44: 2d2d2d2d ---- DCD 757935405 + 0x01004a48: 000a2d2d --.. DCD 666925 + 0x01004a4c: 1ea01ea0 .... DCD 513810080 + 0x01004a50: 30257830 0x%0 DCD 807761968 + 0x01004a54: 00007838 8x.. DCD 30776 + 0x01004a58: 30257830 0x%0 DCD 807761968 + 0x01004a5c: 203a7838 8x: DCD 540702776 + 0x01004a60: 64382d25 %-8d DCD 1681403173 + 0x01004a64: 00000020 ... DCD 32 + 0x01004a68: 0000000a .... DCD 10 + 0x01004a6c: 30257830 0x%0 DCD 807761968 + 0x01004a70: 203a7838 8x: DCD 540702776 + 0x01004a74: 64382d25 %-8d DCD 1681403173 + 0x01004a78: 3e463c20 DCD 1044790304 + 0x01004a7c: 0000000a .... DCD 10 + $t + i.rt_memmove + rt_memmove + 0x01004a80: b570 p. PUSH {r4-r6,lr} + 0x01004a82: 460c .F MOV r4,r1 + 0x01004a84: 4601 .F MOV r1,r0 + 0x01004a86: 4623 #F MOV r3,r4 + 0x01004a88: 428b .B CMP r3,r1 + 0x01004a8a: d210 .. BCS 0x1004aae ; rt_memmove + 46 + 0x01004a8c: 189d .. ADDS r5,r3,r2 + 0x01004a8e: 428d .B CMP r5,r1 + 0x01004a90: d90d .. BLS 0x1004aae ; rt_memmove + 46 + 0x01004a92: 1889 .. ADDS r1,r1,r2 + 0x01004a94: 189b .. ADDS r3,r3,r2 + 0x01004a96: e005 .. B 0x1004aa4 ; rt_memmove + 36 + 0x01004a98: 1e5d ]. SUBS r5,r3,#1 + 0x01004a9a: 462b +F MOV r3,r5 + 0x01004a9c: 782e .x LDRB r6,[r5,#0] + 0x01004a9e: 1e4d M. SUBS r5,r1,#1 + 0x01004aa0: 4629 )F MOV r1,r5 + 0x01004aa2: 702e .p STRB r6,[r5,#0] + 0x01004aa4: 4615 .F MOV r5,r2 + 0x01004aa6: 1e52 R. SUBS r2,r2,#1 + 0x01004aa8: 2d00 .- CMP r5,#0 + 0x01004aaa: d1f5 .. BNE 0x1004a98 ; rt_memmove + 24 + 0x01004aac: e008 .. B 0x1004ac0 ; rt_memmove + 64 + 0x01004aae: e003 .. B 0x1004ab8 ; rt_memmove + 56 + 0x01004ab0: 781d .x LDRB r5,[r3,#0] + 0x01004ab2: 700d .p STRB r5,[r1,#0] + 0x01004ab4: 1c5b [. ADDS r3,r3,#1 + 0x01004ab6: 1c49 I. ADDS r1,r1,#1 + 0x01004ab8: 4615 .F MOV r5,r2 + 0x01004aba: 1e52 R. SUBS r2,r2,#1 + 0x01004abc: 2d00 .- CMP r5,#0 + 0x01004abe: d1f7 .. BNE 0x1004ab0 ; rt_memmove + 48 + 0x01004ac0: bd70 p. POP {r4-r6,pc} + i.rt_memset + rt_memset + 0x01004ac2: b5f7 .. PUSH {r0-r2,r4-r7,lr} + 0x01004ac4: 4605 .F MOV r5,r0 + 0x01004ac6: 9e01 .. LDR r6,[sp,#4] + 0x01004ac8: b2f4 .. UXTB r4,r6 + 0x01004aca: 2a04 .* CMP r2,#4 + 0x01004acc: d317 .. BCC 0x1004afe ; rt_memset + 60 + 0x01004ace: 0786 .. LSLS r6,r0,#30 + 0x01004ad0: 0fb6 .. LSRS r6,r6,#30 + 0x01004ad2: 2e00 .. CMP r6,#0 + 0x01004ad4: d113 .. BNE 0x1004afe ; rt_memset + 60 + 0x01004ad6: 4601 .F MOV r1,r0 + 0x01004ad8: 0226 &. LSLS r6,r4,#8 + 0x01004ada: 4326 &C ORRS r6,r6,r4 + 0x01004adc: 4633 3F MOV r3,r6 + 0x01004ade: 041e .. LSLS r6,r3,#16 + 0x01004ae0: 4333 3C ORRS r3,r3,r6 + 0x01004ae2: e004 .. B 0x1004aee ; rt_memset + 44 + 0x01004ae4: c108 .. STM r1!,{r3} + 0x01004ae6: c108 .. STM r1!,{r3} + 0x01004ae8: c108 .. STM r1!,{r3} + 0x01004aea: c108 .. STM r1!,{r3} + 0x01004aec: 3a10 .: SUBS r2,r2,#0x10 + 0x01004aee: 2a10 .* CMP r2,#0x10 + 0x01004af0: d2f8 .. BCS 0x1004ae4 ; rt_memset + 34 + 0x01004af2: e001 .. B 0x1004af8 ; rt_memset + 54 + 0x01004af4: c108 .. STM r1!,{r3} + 0x01004af6: 1f12 .. SUBS r2,r2,#4 + 0x01004af8: 2a04 .* CMP r2,#4 + 0x01004afa: d2fb .. BCS 0x1004af4 ; rt_memset + 50 + 0x01004afc: 460d .F MOV r5,r1 + 0x01004afe: e001 .. B 0x1004b04 ; rt_memset + 66 + 0x01004b00: 702c ,p STRB r4,[r5,#0] + 0x01004b02: 1c6d m. ADDS r5,r5,#1 + 0x01004b04: 4616 .F MOV r6,r2 + 0x01004b06: 1e52 R. SUBS r2,r2,#1 + 0x01004b08: 2e00 .. CMP r6,#0 + 0x01004b0a: d1f9 .. BNE 0x1004b00 ; rt_memset + 62 + 0x01004b0c: bdfe .. POP {r1-r7,pc} + 0x01004b0e: 0000 .. MOVS r0,r0 + i.rt_object_allocate + rt_object_allocate + 0x01004b10: b5fe .. PUSH {r1-r7,lr} + 0x01004b12: 4606 .F MOV r6,r0 + 0x01004b14: 460f .F MOV r7,r1 + 0x01004b16: bf00 .. NOP + 0x01004b18: f7fbfcd2 .... BL rt_hw_interrupt_disable ; 0x10004c0 + 0x01004b1c: 9000 .. STR r0,[sp,#0] + 0x01004b1e: f7fffcad .... BL rt_interrupt_get_nest ; 0x100447c + 0x01004b22: 2800 .( CMP r0,#0 + 0x01004b24: d009 .. BEQ 0x1004b3a ; rt_object_allocate + 42 + 0x01004b26: 4922 "I LDR r1,[pc,#136] ; [0x1004bb0] = 0x1007a6c + 0x01004b28: a022 ". ADR r0,{pc}+0x8c ; 0x1004bb4 + 0x01004b2a: f7fffcd1 .... BL rt_kprintf ; 0x10044d0 + 0x01004b2e: 22ff ." MOVS r2,#0xff + 0x01004b30: 329a .2 ADDS r2,r2,#0x9a + 0x01004b32: 491f .I LDR r1,[pc,#124] ; [0x1004bb0] = 0x1007a6c + 0x01004b34: a029 ). ADR r0,{pc}+0xa8 ; 0x1004bdc + 0x01004b36: f7fefd63 ..c. BL rt_assert_handler ; 0x1003600 + 0x01004b3a: 9800 .. LDR r0,[sp,#0] + 0x01004b3c: f7fbfcc4 .... BL rt_hw_interrupt_enable ; 0x10004c8 + 0x01004b40: bf00 .. NOP + 0x01004b42: 4630 0F MOV r0,r6 + 0x01004b44: f000f938 ..8. BL rt_object_get_information ; 0x1004db8 + 0x01004b48: 4605 .F MOV r5,r0 + 0x01004b4a: 2d00 .- CMP r5,#0 + 0x01004b4c: d105 .. BNE 0x1004b5a ; rt_object_allocate + 74 + 0x01004b4e: 22ff ." MOVS r2,#0xff + 0x01004b50: 329e .2 ADDS r2,r2,#0x9e + 0x01004b52: 4917 .I LDR r1,[pc,#92] ; [0x1004bb0] = 0x1007a6c + 0x01004b54: a022 ". ADR r0,{pc}+0x8c ; 0x1004be0 + 0x01004b56: f7fefd53 ..S. BL rt_assert_handler ; 0x1003600 + 0x01004b5a: 68e8 .h LDR r0,[r5,#0xc] + 0x01004b5c: f7fffd40 ..@. BL rt_malloc ; 0x10045e0 + 0x01004b60: 4604 .F MOV r4,r0 + 0x01004b62: 2c00 ., CMP r4,#0 + 0x01004b64: d100 .. BNE 0x1004b68 ; rt_object_allocate + 88 + 0x01004b66: bdfe .. POP {r1-r7,pc} + 0x01004b68: 2100 .! MOVS r1,#0 + 0x01004b6a: 4620 F MOV r0,r4 + 0x01004b6c: 68ea .h LDR r2,[r5,#0xc] + 0x01004b6e: f7ffffa8 .... BL rt_memset ; 0x1004ac2 + 0x01004b72: 7226 &r STRB r6,[r4,#8] + 0x01004b74: 2000 . MOVS r0,#0 + 0x01004b76: 7260 `r STRB r0,[r4,#9] + 0x01004b78: 2208 ." MOVS r2,#8 + 0x01004b7a: 4639 9F MOV r1,r7 + 0x01004b7c: 4620 F MOV r0,r4 + 0x01004b7e: f000ffdc .... BL rt_strncpy ; 0x1005b3a + 0x01004b82: bf00 .. NOP + 0x01004b84: 481c .H LDR r0,[pc,#112] ; [0x1004bf8] = 0x20108 + 0x01004b86: 6800 .h LDR r0,[r0,#0] + 0x01004b88: 2800 .( CMP r0,#0 + 0x01004b8a: d003 .. BEQ 0x1004b94 ; rt_object_allocate + 132 + 0x01004b8c: 4620 F MOV r0,r4 + 0x01004b8e: 491a .I LDR r1,[pc,#104] ; [0x1004bf8] = 0x20108 + 0x01004b90: 6809 .h LDR r1,[r1,#0] + 0x01004b92: 4788 .G BLX r1 + 0x01004b94: bf00 .. NOP + 0x01004b96: f7fbfc93 .... BL rt_hw_interrupt_disable ; 0x10004c0 + 0x01004b9a: 9001 .. STR r0,[sp,#4] + 0x01004b9c: 4621 !F MOV r1,r4 + 0x01004b9e: 310c .1 ADDS r1,r1,#0xc + 0x01004ba0: 1d28 (. ADDS r0,r5,#4 + 0x01004ba2: f7fffcca .... BL rt_list_insert_after ; 0x100453a + 0x01004ba6: 9801 .. LDR r0,[sp,#4] + 0x01004ba8: f7fbfc8e .... BL rt_hw_interrupt_enable ; 0x10004c8 + 0x01004bac: 4620 F MOV r0,r4 + 0x01004bae: e7da .. B 0x1004b66 ; rt_object_allocate + 86 + $d + 0x01004bb0: 01007a6c lz.. DCD 16808556 + 0x01004bb4: 636e7546 Func DCD 1668183366 + 0x01004bb8: 6e6f6974 tion DCD 1852795252 + 0x01004bbc: 5d73255b [%s] DCD 1567827291 + 0x01004bc0: 61687320 sha DCD 1634235168 + 0x01004bc4: 6e206c6c ll n DCD 1847618668 + 0x01004bc8: 6220746f ot b DCD 1646294127 + 0x01004bcc: 73752065 e us DCD 1937055845 + 0x01004bd0: 69206465 ed i DCD 1763730533 + 0x01004bd4: 5349206e n IS DCD 1397301358 + 0x01004bd8: 00000a52 R... DCD 2642 + 0x01004bdc: 00000030 0... DCD 48 + 0x01004be0: 6f666e69 info DCD 1868983913 + 0x01004be4: 74616d72 rmat DCD 1952542066 + 0x01004be8: 206e6f69 ion DCD 544108393 + 0x01004bec: 52203d21 != R DCD 1377844513 + 0x01004bf0: 554e5f54 T_NU DCD 1431199572 + 0x01004bf4: 00004c4c LL.. DCD 19532 + 0x01004bf8: 00020108 .... DCD 131336 + $t + i.rt_object_delete + rt_object_delete + 0x01004bfc: b570 p. PUSH {r4-r6,lr} + 0x01004bfe: 4604 .F MOV r4,r0 + 0x01004c00: 2c00 ., CMP r4,#0 + 0x01004c02: d105 .. BNE 0x1004c10 ; rt_object_delete + 20 + 0x01004c04: 22ff ." MOVS r2,#0xff + 0x01004c06: 32d8 .2 ADDS r2,r2,#0xd8 + 0x01004c08: 4914 .I LDR r1,[pc,#80] ; [0x1004c5c] = 0x1007a7f + 0x01004c0a: a015 .. ADR r0,{pc}+0x56 ; 0x1004c60 + 0x01004c0c: f7fefcf8 .... BL rt_assert_handler ; 0x1003600 + 0x01004c10: 7a20 z LDRB r0,[r4,#8] + 0x01004c12: 2180 .! MOVS r1,#0x80 + 0x01004c14: 4008 .@ ANDS r0,r0,r1 + 0x01004c16: 2800 .( CMP r0,#0 + 0x01004c18: d005 .. BEQ 0x1004c26 ; rt_object_delete + 42 + 0x01004c1a: 22ff ." MOVS r2,#0xff + 0x01004c1c: 32d9 .2 ADDS r2,r2,#0xd9 + 0x01004c1e: 490f .I LDR r1,[pc,#60] ; [0x1004c5c] = 0x1007a7f + 0x01004c20: a014 .. ADR r0,{pc}+0x54 ; 0x1004c74 + 0x01004c22: f7fefced .... BL rt_assert_handler ; 0x1003600 + 0x01004c26: bf00 .. NOP + 0x01004c28: 481d .H LDR r0,[pc,#116] ; [0x1004ca0] = 0x2010c + 0x01004c2a: 6800 .h LDR r0,[r0,#0] + 0x01004c2c: 2800 .( CMP r0,#0 + 0x01004c2e: d003 .. BEQ 0x1004c38 ; rt_object_delete + 60 + 0x01004c30: 4620 F MOV r0,r4 + 0x01004c32: 491b .I LDR r1,[pc,#108] ; [0x1004ca0] = 0x2010c + 0x01004c34: 6809 .h LDR r1,[r1,#0] + 0x01004c36: 4788 .G BLX r1 + 0x01004c38: bf00 .. NOP + 0x01004c3a: 2000 . MOVS r0,#0 + 0x01004c3c: 7220 r STRB r0,[r4,#8] + 0x01004c3e: f7fbfc3f ..?. BL rt_hw_interrupt_disable ; 0x10004c0 + 0x01004c42: 4605 .F MOV r5,r0 + 0x01004c44: 4620 F MOV r0,r4 + 0x01004c46: 300c .0 ADDS r0,r0,#0xc + 0x01004c48: f7fffcb8 .... BL rt_list_remove ; 0x10045bc + 0x01004c4c: 4628 (F MOV r0,r5 + 0x01004c4e: f7fbfc3b ..;. BL rt_hw_interrupt_enable ; 0x10004c8 + 0x01004c52: 4620 F MOV r0,r4 + 0x01004c54: f7fff93c ..<. BL rt_free ; 0x1003ed0 + 0x01004c58: bd70 p. POP {r4-r6,pc} + $d + 0x01004c5a: 0000 .. DCW 0 + 0x01004c5c: 01007a7f .z.. DCD 16808575 + 0x01004c60: 656a626f obje DCD 1701470831 + 0x01004c64: 21207463 ct ! DCD 555775075 + 0x01004c68: 5452203d = RT DCD 1414668349 + 0x01004c6c: 4c554e5f _NUL DCD 1280659039 + 0x01004c70: 0000004c L... DCD 76 + 0x01004c74: 626f2821 !(ob DCD 1651451937 + 0x01004c78: 7463656a ject DCD 1952671082 + 0x01004c7c: 79743e2d ->ty DCD 2037661229 + 0x01004c80: 26206570 pe & DCD 639657328 + 0x01004c84: 5f545220 RT_ DCD 1599361568 + 0x01004c88: 656a624f Obje DCD 1701470799 + 0x01004c8c: 435f7463 ct_C DCD 1130329187 + 0x01004c90: 7373616c lass DCD 1936941420 + 0x01004c94: 6174535f _Sta DCD 1635013471 + 0x01004c98: 29636974 tic) DCD 694380916 + 0x01004c9c: 00000000 .... DCD 0 + 0x01004ca0: 0002010c .... DCD 131340 + $t + i.rt_object_detach + rt_object_detach + 0x01004ca4: b570 p. PUSH {r4-r6,lr} + 0x01004ca6: 4604 .F MOV r4,r0 + 0x01004ca8: 2c00 ., CMP r4,#0 + 0x01004caa: d105 .. BNE 0x1004cb8 ; rt_object_detach + 20 + 0x01004cac: 22ff ." MOVS r2,#0xff + 0x01004cae: 3277 w2 ADDS r2,r2,#0x77 + 0x01004cb0: 490d .I LDR r1,[pc,#52] ; [0x1004ce8] = 0x1007a5b + 0x01004cb2: a00e .. ADR r0,{pc}+0x3a ; 0x1004cec + 0x01004cb4: f7fefca4 .... BL rt_assert_handler ; 0x1003600 + 0x01004cb8: bf00 .. NOP + 0x01004cba: 4811 .H LDR r0,[pc,#68] ; [0x1004d00] = 0x2010c + 0x01004cbc: 6800 .h LDR r0,[r0,#0] + 0x01004cbe: 2800 .( CMP r0,#0 + 0x01004cc0: d003 .. BEQ 0x1004cca ; rt_object_detach + 38 + 0x01004cc2: 4620 F MOV r0,r4 + 0x01004cc4: 490e .I LDR r1,[pc,#56] ; [0x1004d00] = 0x2010c + 0x01004cc6: 6809 .h LDR r1,[r1,#0] + 0x01004cc8: 4788 .G BLX r1 + 0x01004cca: bf00 .. NOP + 0x01004ccc: 2000 . MOVS r0,#0 + 0x01004cce: 7220 r STRB r0,[r4,#8] + 0x01004cd0: f7fbfbf6 .... BL rt_hw_interrupt_disable ; 0x10004c0 + 0x01004cd4: 4605 .F MOV r5,r0 + 0x01004cd6: 4620 F MOV r0,r4 + 0x01004cd8: 300c .0 ADDS r0,r0,#0xc + 0x01004cda: f7fffc6f ..o. BL rt_list_remove ; 0x10045bc + 0x01004cde: 4628 (F MOV r0,r5 + 0x01004ce0: f7fbfbf2 .... BL rt_hw_interrupt_enable ; 0x10004c8 + 0x01004ce4: bd70 p. POP {r4-r6,pc} + $d + 0x01004ce6: 0000 .. DCW 0 + 0x01004ce8: 01007a5b [z.. DCD 16808539 + 0x01004cec: 656a626f obje DCD 1701470831 + 0x01004cf0: 21207463 ct ! DCD 555775075 + 0x01004cf4: 5452203d = RT DCD 1414668349 + 0x01004cf8: 4c554e5f _NUL DCD 1280659039 + 0x01004cfc: 0000004c L... DCD 76 + 0x01004d00: 0002010c .... DCD 131340 + $t + i.rt_object_find + rt_object_find + 0x01004d04: b5fe .. PUSH {r1-r7,lr} + 0x01004d06: 4604 .F MOV r4,r0 + 0x01004d08: 460f .F MOV r7,r1 + 0x01004d0a: 2000 . MOVS r0,#0 + 0x01004d0c: 9001 .. STR r0,[sp,#4] + 0x01004d0e: 2500 .% MOVS r5,#0 + 0x01004d10: 2600 .& MOVS r6,#0 + 0x01004d12: 4638 8F MOV r0,r7 + 0x01004d14: f000f850 ..P. BL rt_object_get_information ; 0x1004db8 + 0x01004d18: 4606 .F MOV r6,r0 + 0x01004d1a: 2c00 ., CMP r4,#0 + 0x01004d1c: d001 .. BEQ 0x1004d22 ; rt_object_find + 30 + 0x01004d1e: 2e00 .. CMP r6,#0 + 0x01004d20: d101 .. BNE 0x1004d26 ; rt_object_find + 34 + 0x01004d22: 2000 . MOVS r0,#0 + 0x01004d24: bdfe .. POP {r1-r7,pc} + 0x01004d26: bf00 .. NOP + 0x01004d28: f7fbfbca .... BL rt_hw_interrupt_disable ; 0x10004c0 + 0x01004d2c: 9000 .. STR r0,[sp,#0] + 0x01004d2e: f7fffba5 .... BL rt_interrupt_get_nest ; 0x100447c + 0x01004d32: 2800 .( CMP r0,#0 + 0x01004d34: d008 .. BEQ 0x1004d48 ; rt_object_find + 68 + 0x01004d36: 4913 .I LDR r1,[pc,#76] ; [0x1004d84] = 0x1007abd + 0x01004d38: a013 .. ADR r0,{pc}+0x50 ; 0x1004d88 + 0x01004d3a: f7fffbc9 .... BL rt_kprintf ; 0x10044d0 + 0x01004d3e: 4a1c .J LDR r2,[pc,#112] ; [0x1004db0] = 0x229 + 0x01004d40: 4910 .I LDR r1,[pc,#64] ; [0x1004d84] = 0x1007abd + 0x01004d42: a01c .. ADR r0,{pc}+0x72 ; 0x1004db4 + 0x01004d44: f7fefc5c ..\. BL rt_assert_handler ; 0x1003600 + 0x01004d48: 9800 .. LDR r0,[sp,#0] + 0x01004d4a: f7fbfbbd .... BL rt_hw_interrupt_enable ; 0x10004c8 + 0x01004d4e: bf00 .. NOP + 0x01004d50: f7fff88a .... BL rt_enter_critical ; 0x1003e68 + 0x01004d54: 6875 uh LDR r5,[r6,#4] + 0x01004d56: e00e .. B 0x1004d76 ; rt_object_find + 114 + 0x01004d58: 4628 (F MOV r0,r5 + 0x01004d5a: 380c .8 SUBS r0,r0,#0xc + 0x01004d5c: 9001 .. STR r0,[sp,#4] + 0x01004d5e: 2208 ." MOVS r2,#8 + 0x01004d60: 4621 !F MOV r1,r4 + 0x01004d62: 9801 .. LDR r0,[sp,#4] + 0x01004d64: f000fed4 .... BL rt_strncmp ; 0x1005b10 + 0x01004d68: 2800 .( CMP r0,#0 + 0x01004d6a: d103 .. BNE 0x1004d74 ; rt_object_find + 112 + 0x01004d6c: f7fff88c .... BL rt_exit_critical ; 0x1003e88 + 0x01004d70: 9801 .. LDR r0,[sp,#4] + 0x01004d72: e7d7 .. B 0x1004d24 ; rt_object_find + 32 + 0x01004d74: 682d -h LDR r5,[r5,#0] + 0x01004d76: 1d30 0. ADDS r0,r6,#4 + 0x01004d78: 4285 .B CMP r5,r0 + 0x01004d7a: d1ed .. BNE 0x1004d58 ; rt_object_find + 84 + 0x01004d7c: f7fff884 .... BL rt_exit_critical ; 0x1003e88 + 0x01004d80: 2000 . MOVS r0,#0 + 0x01004d82: e7cf .. B 0x1004d24 ; rt_object_find + 32 + $d + 0x01004d84: 01007abd .z.. DCD 16808637 + 0x01004d88: 636e7546 Func DCD 1668183366 + 0x01004d8c: 6e6f6974 tion DCD 1852795252 + 0x01004d90: 5d73255b [%s] DCD 1567827291 + 0x01004d94: 61687320 sha DCD 1634235168 + 0x01004d98: 6e206c6c ll n DCD 1847618668 + 0x01004d9c: 6220746f ot b DCD 1646294127 + 0x01004da0: 73752065 e us DCD 1937055845 + 0x01004da4: 69206465 ed i DCD 1763730533 + 0x01004da8: 5349206e n IS DCD 1397301358 + 0x01004dac: 00000a52 R... DCD 2642 + 0x01004db0: 00000229 )... DCD 553 + 0x01004db4: 00000030 0... DCD 48 + $t + i.rt_object_get_information + rt_object_get_information + 0x01004db8: 4602 .F MOV r2,r0 + 0x01004dba: 2100 .! MOVS r1,#0 + 0x01004dbc: e008 .. B 0x1004dd0 ; rt_object_get_information + 24 + 0x01004dbe: 0108 .. LSLS r0,r1,#4 + 0x01004dc0: 4b05 .K LDR r3,[pc,#20] ; [0x1004dd8] = 0x20068 + 0x01004dc2: 5c18 .\ LDRB r0,[r3,r0] + 0x01004dc4: 4290 .B CMP r0,r2 + 0x01004dc6: d102 .. BNE 0x1004dce ; rt_object_get_information + 22 + 0x01004dc8: 0108 .. LSLS r0,r1,#4 + 0x01004dca: 18c0 .. ADDS r0,r0,r3 + 0x01004dcc: 4770 pG BX lr + 0x01004dce: 1c49 I. ADDS r1,r1,#1 + 0x01004dd0: 290a .) CMP r1,#0xa + 0x01004dd2: dbf4 .. BLT 0x1004dbe ; rt_object_get_information + 6 + 0x01004dd4: 2000 . MOVS r0,#0 + 0x01004dd6: e7f9 .. B 0x1004dcc ; rt_object_get_information + 20 + $d + 0x01004dd8: 00020068 h... DCD 131176 + $t + i.rt_object_get_length + rt_object_get_length + 0x01004ddc: b5f8 .. PUSH {r3-r7,lr} + 0x01004dde: 4607 .F MOV r7,r0 + 0x01004de0: 2500 .% MOVS r5,#0 + 0x01004de2: 2600 .& MOVS r6,#0 + 0x01004de4: 2400 .$ MOVS r4,#0 + 0x01004de6: 4638 8F MOV r0,r7 + 0x01004de8: f7ffffe6 .... BL rt_object_get_information ; 0x1004db8 + 0x01004dec: 4604 .F MOV r4,r0 + 0x01004dee: 2c00 ., CMP r4,#0 + 0x01004df0: d100 .. BNE 0x1004df4 ; rt_object_get_length + 24 + 0x01004df2: bdf8 .. POP {r3-r7,pc} + 0x01004df4: f7fbfb64 ..d. BL rt_hw_interrupt_disable ; 0x10004c0 + 0x01004df8: 9000 .. STR r0,[sp,#0] + 0x01004dfa: 6866 fh LDR r6,[r4,#4] + 0x01004dfc: e001 .. B 0x1004e02 ; rt_object_get_length + 38 + 0x01004dfe: 1c6d m. ADDS r5,r5,#1 + 0x01004e00: 6836 6h LDR r6,[r6,#0] + 0x01004e02: 1d20 . ADDS r0,r4,#4 + 0x01004e04: 4286 .B CMP r6,r0 + 0x01004e06: d1fa .. BNE 0x1004dfe ; rt_object_get_length + 34 + 0x01004e08: 9800 .. LDR r0,[sp,#0] + 0x01004e0a: f7fbfb5d ..]. BL rt_hw_interrupt_enable ; 0x10004c8 + 0x01004e0e: 4628 (F MOV r0,r5 + 0x01004e10: e7ef .. B 0x1004df2 ; rt_object_get_length + 22 + i.rt_object_get_pointers + rt_object_get_pointers + 0x01004e12: b5f7 .. PUSH {r0-r2,r4-r7,lr} + 0x01004e14: b082 .. SUB sp,sp,#8 + 0x01004e16: 4615 .F MOV r5,r2 + 0x01004e18: 2400 .$ MOVS r4,#0 + 0x01004e1a: 2600 .& MOVS r6,#0 + 0x01004e1c: 2700 .' MOVS r7,#0 + 0x01004e1e: 2d00 .- CMP r5,#0 + 0x01004e20: dc02 .. BGT 0x1004e28 ; rt_object_get_pointers + 22 + 0x01004e22: 2000 . MOVS r0,#0 + 0x01004e24: b005 .. ADD sp,sp,#0x14 + 0x01004e26: bdf0 .. POP {r4-r7,pc} + 0x01004e28: 9802 .. LDR r0,[sp,#8] + 0x01004e2a: f7ffffc5 .... BL rt_object_get_information ; 0x1004db8 + 0x01004e2e: 4607 .F MOV r7,r0 + 0x01004e30: 2f00 ./ CMP r7,#0 + 0x01004e32: d100 .. BNE 0x1004e36 ; rt_object_get_pointers + 36 + 0x01004e34: e7f6 .. B 0x1004e24 ; rt_object_get_pointers + 18 + 0x01004e36: f7fbfb43 ..C. BL rt_hw_interrupt_disable ; 0x10004c0 + 0x01004e3a: 9001 .. STR r0,[sp,#4] + 0x01004e3c: 687e ~h LDR r6,[r7,#4] + 0x01004e3e: e00b .. B 0x1004e58 ; rt_object_get_pointers + 70 + 0x01004e40: 4630 0F MOV r0,r6 + 0x01004e42: 380c .8 SUBS r0,r0,#0xc + 0x01004e44: 9000 .. STR r0,[sp,#0] + 0x01004e46: 00a2 .. LSLS r2,r4,#2 + 0x01004e48: 9903 .. LDR r1,[sp,#0xc] + 0x01004e4a: 9800 .. LDR r0,[sp,#0] + 0x01004e4c: 5088 .P STR r0,[r1,r2] + 0x01004e4e: 1c64 d. ADDS r4,r4,#1 + 0x01004e50: 42ac .B CMP r4,r5 + 0x01004e52: db00 .. BLT 0x1004e56 ; rt_object_get_pointers + 68 + 0x01004e54: e003 .. B 0x1004e5e ; rt_object_get_pointers + 76 + 0x01004e56: 6836 6h LDR r6,[r6,#0] + 0x01004e58: 1d38 8. ADDS r0,r7,#4 + 0x01004e5a: 4286 .B CMP r6,r0 + 0x01004e5c: d1f0 .. BNE 0x1004e40 ; rt_object_get_pointers + 46 + 0x01004e5e: bf00 .. NOP + 0x01004e60: 9801 .. LDR r0,[sp,#4] + 0x01004e62: f7fbfb31 ..1. BL rt_hw_interrupt_enable ; 0x10004c8 + 0x01004e66: 4620 F MOV r0,r4 + 0x01004e68: e7dc .. B 0x1004e24 ; rt_object_get_pointers + 18 + 0x01004e6a: 0000 .. MOVS r0,r0 + i.rt_object_get_type + rt_object_get_type + 0x01004e6c: b510 .. PUSH {r4,lr} + 0x01004e6e: 4604 .F MOV r4,r0 + 0x01004e70: 2c00 ., CMP r4,#0 + 0x01004e72: d105 .. BNE 0x1004e80 ; rt_object_get_type + 20 + 0x01004e74: 2283 ." MOVS r2,#0x83 + 0x01004e76: 0092 .. LSLS r2,r2,#2 + 0x01004e78: 4903 .I LDR r1,[pc,#12] ; [0x1004e88] = 0x1007aaa + 0x01004e7a: a004 .. ADR r0,{pc}+0x12 ; 0x1004e8c + 0x01004e7c: f7fefbc0 .... BL rt_assert_handler ; 0x1003600 + 0x01004e80: 7a20 z LDRB r0,[r4,#8] + 0x01004e82: 2180 .! MOVS r1,#0x80 + 0x01004e84: 4388 .C BICS r0,r0,r1 + 0x01004e86: bd10 .. POP {r4,pc} + $d + 0x01004e88: 01007aaa .z.. DCD 16808618 + 0x01004e8c: 656a626f obje DCD 1701470831 + 0x01004e90: 21207463 ct ! DCD 555775075 + 0x01004e94: 5452203d = RT DCD 1414668349 + 0x01004e98: 4c554e5f _NUL DCD 1280659039 + 0x01004e9c: 0000004c L... DCD 76 + $t + i.rt_object_init + rt_object_init + 0x01004ea0: b5f7 .. PUSH {r0-r2,r4-r7,lr} + 0x01004ea2: b082 .. SUB sp,sp,#8 + 0x01004ea4: 4604 .F MOV r4,r0 + 0x01004ea6: 460e .F MOV r6,r1 + 0x01004ea8: 2700 .' MOVS r7,#0 + 0x01004eaa: 4630 0F MOV r0,r6 + 0x01004eac: f7ffff84 .... BL rt_object_get_information ; 0x1004db8 + 0x01004eb0: 4605 .F MOV r5,r0 + 0x01004eb2: 2d00 .- CMP r5,#0 + 0x01004eb4: d105 .. BNE 0x1004ec2 ; rt_object_init + 34 + 0x01004eb6: 22ff ." MOVS r2,#0xff + 0x01004eb8: 323a :2 ADDS r2,r2,#0x3a + 0x01004eba: 491e .I LDR r1,[pc,#120] ; [0x1004f34] = 0x1007a4c + 0x01004ebc: a01e .. ADR r0,{pc}+0x7c ; 0x1004f38 + 0x01004ebe: f7fefb9f .... BL rt_assert_handler ; 0x1003600 + 0x01004ec2: f7feffd1 .... BL rt_enter_critical ; 0x1003e68 + 0x01004ec6: 686f oh LDR r7,[r5,#4] + 0x01004ec8: e00f .. B 0x1004eea ; rt_object_init + 74 + 0x01004eca: 4638 8F MOV r0,r7 + 0x01004ecc: 380c .8 SUBS r0,r0,#0xc + 0x01004ece: 9000 .. STR r0,[sp,#0] + 0x01004ed0: 9800 .. LDR r0,[sp,#0] + 0x01004ed2: 2800 .( CMP r0,#0 + 0x01004ed4: d008 .. BEQ 0x1004ee8 ; rt_object_init + 72 + 0x01004ed6: 9800 .. LDR r0,[sp,#0] + 0x01004ed8: 42a0 .B CMP r0,r4 + 0x01004eda: d105 .. BNE 0x1004ee8 ; rt_object_init + 72 + 0x01004edc: 22ff ." MOVS r2,#0xff + 0x01004ede: 324a J2 ADDS r2,r2,#0x4a + 0x01004ee0: 4914 .I LDR r1,[pc,#80] ; [0x1004f34] = 0x1007a4c + 0x01004ee2: a01b .. ADR r0,{pc}+0x6e ; 0x1004f50 + 0x01004ee4: f7fefb8c .... BL rt_assert_handler ; 0x1003600 + 0x01004ee8: 683f ?h LDR r7,[r7,#0] + 0x01004eea: 1d28 (. ADDS r0,r5,#4 + 0x01004eec: 4287 .B CMP r7,r0 + 0x01004eee: d1ec .. BNE 0x1004eca ; rt_object_init + 42 + 0x01004ef0: f7feffca .... BL rt_exit_critical ; 0x1003e88 + 0x01004ef4: 2080 . MOVS r0,#0x80 + 0x01004ef6: 4330 0C ORRS r0,r0,r6 + 0x01004ef8: 7220 r STRB r0,[r4,#8] + 0x01004efa: 2208 ." MOVS r2,#8 + 0x01004efc: 4620 F MOV r0,r4 + 0x01004efe: 9904 .. LDR r1,[sp,#0x10] + 0x01004f00: f000fe1b .... BL rt_strncpy ; 0x1005b3a + 0x01004f04: bf00 .. NOP + 0x01004f06: 4816 .H LDR r0,[pc,#88] ; [0x1004f60] = 0x20108 + 0x01004f08: 6800 .h LDR r0,[r0,#0] + 0x01004f0a: 2800 .( CMP r0,#0 + 0x01004f0c: d003 .. BEQ 0x1004f16 ; rt_object_init + 118 + 0x01004f0e: 4620 F MOV r0,r4 + 0x01004f10: 4913 .I LDR r1,[pc,#76] ; [0x1004f60] = 0x20108 + 0x01004f12: 6809 .h LDR r1,[r1,#0] + 0x01004f14: 4788 .G BLX r1 + 0x01004f16: bf00 .. NOP + 0x01004f18: f7fbfad2 .... BL rt_hw_interrupt_disable ; 0x10004c0 + 0x01004f1c: 9001 .. STR r0,[sp,#4] + 0x01004f1e: 4621 !F MOV r1,r4 + 0x01004f20: 310c .1 ADDS r1,r1,#0xc + 0x01004f22: 1d28 (. ADDS r0,r5,#4 + 0x01004f24: f7fffb09 .... BL rt_list_insert_after ; 0x100453a + 0x01004f28: 9801 .. LDR r0,[sp,#4] + 0x01004f2a: f7fbfacd .... BL rt_hw_interrupt_enable ; 0x10004c8 + 0x01004f2e: b005 .. ADD sp,sp,#0x14 + 0x01004f30: bdf0 .. POP {r4-r7,pc} + $d + 0x01004f32: 0000 .. DCW 0 + 0x01004f34: 01007a4c Lz.. DCD 16808524 + 0x01004f38: 6f666e69 info DCD 1868983913 + 0x01004f3c: 74616d72 rmat DCD 1952542066 + 0x01004f40: 206e6f69 ion DCD 544108393 + 0x01004f44: 52203d21 != R DCD 1377844513 + 0x01004f48: 554e5f54 T_NU DCD 1431199572 + 0x01004f4c: 00004c4c LL.. DCD 19532 + 0x01004f50: 206a626f obj DCD 543842927 + 0x01004f54: 6f203d21 != o DCD 1864383777 + 0x01004f58: 63656a62 bjec DCD 1667590754 + 0x01004f5c: 00000074 t... DCD 116 + 0x01004f60: 00020108 .... DCD 131336 + $t + i.rt_object_is_systemobject + rt_object_is_systemobject + 0x01004f64: b510 .. PUSH {r4,lr} + 0x01004f66: 4604 .F MOV r4,r0 + 0x01004f68: 2c00 ., CMP r4,#0 + 0x01004f6a: d105 .. BNE 0x1004f78 ; rt_object_is_systemobject + 20 + 0x01004f6c: 22ff ." MOVS r2,#0xff + 0x01004f6e: 32fa .2 ADDS r2,r2,#0xfa + 0x01004f70: 4906 .I LDR r1,[pc,#24] ; [0x1004f8c] = 0x1007a90 + 0x01004f72: a007 .. ADR r0,{pc}+0x1e ; 0x1004f90 + 0x01004f74: f7fefb44 ..D. BL rt_assert_handler ; 0x1003600 + 0x01004f78: 7a20 z LDRB r0,[r4,#8] + 0x01004f7a: 2180 .! MOVS r1,#0x80 + 0x01004f7c: 4008 .@ ANDS r0,r0,r1 + 0x01004f7e: 2800 .( CMP r0,#0 + 0x01004f80: d001 .. BEQ 0x1004f86 ; rt_object_is_systemobject + 34 + 0x01004f82: 2001 . MOVS r0,#1 + 0x01004f84: bd10 .. POP {r4,pc} + 0x01004f86: 2000 . MOVS r0,#0 + 0x01004f88: e7fc .. B 0x1004f84 ; rt_object_is_systemobject + 32 + $d + 0x01004f8a: 0000 .. DCW 0 + 0x01004f8c: 01007a90 .z.. DCD 16808592 + 0x01004f90: 656a626f obje DCD 1701470831 + 0x01004f94: 21207463 ct ! DCD 555775075 + 0x01004f98: 5452203d = RT DCD 1414668349 + 0x01004f9c: 4c554e5f _NUL DCD 1280659039 + 0x01004fa0: 0000004c L... DCD 76 + $t + i.rt_pin_mode + rt_pin_mode + 0x01004fa4: b570 p. PUSH {r4-r6,lr} + 0x01004fa6: 4604 .F MOV r4,r0 + 0x01004fa8: 460d .F MOV r5,r1 + 0x01004faa: 4808 .H LDR r0,[pc,#32] ; [0x1004fcc] = 0x20158 + 0x01004fac: 6c00 .l LDR r0,[r0,#0x40] + 0x01004fae: 2800 .( CMP r0,#0 + 0x01004fb0: d104 .. BNE 0x1004fbc ; rt_pin_mode + 24 + 0x01004fb2: 228a ." MOVS r2,#0x8a + 0x01004fb4: 4906 .I LDR r1,[pc,#24] ; [0x1004fd0] = 0x10072d4 + 0x01004fb6: a007 .. ADR r0,{pc}+0x1e ; 0x1004fd4 + 0x01004fb8: f7fefb22 ..". BL rt_assert_handler ; 0x1003600 + 0x01004fbc: 4803 .H LDR r0,[pc,#12] ; [0x1004fcc] = 0x20158 + 0x01004fbe: 6c00 .l LDR r0,[r0,#0x40] + 0x01004fc0: 462a *F MOV r2,r5 + 0x01004fc2: 4621 !F MOV r1,r4 + 0x01004fc4: 6803 .h LDR r3,[r0,#0] + 0x01004fc6: 4801 .H LDR r0,[pc,#4] ; [0x1004fcc] = 0x20158 + 0x01004fc8: 4798 .G BLX r3 + 0x01004fca: bd70 p. POP {r4-r6,pc} + $d + 0x01004fcc: 00020158 X... DCD 131416 + 0x01004fd0: 010072d4 .r.. DCD 16806612 + 0x01004fd4: 5f77685f _hw_ DCD 1601661023 + 0x01004fd8: 2e6e6970 pin. DCD 778987888 + 0x01004fdc: 2073706f ops DCD 544436335 + 0x01004fe0: 52203d21 != R DCD 1377844513 + 0x01004fe4: 554e5f54 T_NU DCD 1431199572 + 0x01004fe8: 00004c4c LL.. DCD 19532 + $t + i.rt_pin_write + rt_pin_write + 0x01004fec: b570 p. PUSH {r4-r6,lr} + 0x01004fee: 4604 .F MOV r4,r0 + 0x01004ff0: 460d .F MOV r5,r1 + 0x01004ff2: 4808 .H LDR r0,[pc,#32] ; [0x1005014] = 0x20158 + 0x01004ff4: 6c00 .l LDR r0,[r0,#0x40] + 0x01004ff6: 2800 .( CMP r0,#0 + 0x01004ff8: d104 .. BNE 0x1005004 ; rt_pin_write + 24 + 0x01004ffa: 2291 ." MOVS r2,#0x91 + 0x01004ffc: 4906 .I LDR r1,[pc,#24] ; [0x1005018] = 0x10072e0 + 0x01004ffe: a007 .. ADR r0,{pc}+0x1e ; 0x100501c + 0x01005000: f7fefafe .... BL rt_assert_handler ; 0x1003600 + 0x01005004: 4803 .H LDR r0,[pc,#12] ; [0x1005014] = 0x20158 + 0x01005006: 6c00 .l LDR r0,[r0,#0x40] + 0x01005008: 462a *F MOV r2,r5 + 0x0100500a: 4621 !F MOV r1,r4 + 0x0100500c: 6843 Ch LDR r3,[r0,#4] + 0x0100500e: 4801 .H LDR r0,[pc,#4] ; [0x1005014] = 0x20158 + 0x01005010: 4798 .G BLX r3 + 0x01005012: bd70 p. POP {r4-r6,pc} + $d + 0x01005014: 00020158 X... DCD 131416 + 0x01005018: 010072e0 .r.. DCD 16806624 + 0x0100501c: 5f77685f _hw_ DCD 1601661023 + 0x01005020: 2e6e6970 pin. DCD 778987888 + 0x01005024: 2073706f ops DCD 544436335 + 0x01005028: 52203d21 != R DCD 1377844513 + 0x0100502c: 554e5f54 T_NU DCD 1431199572 + 0x01005030: 00004c4c LL.. DCD 19532 + $t + i.rt_schedule + rt_schedule + 0x01005034: b5f8 .. PUSH {r3-r7,lr} + 0x01005036: f7fbfa43 ..C. BL rt_hw_interrupt_disable ; 0x10004c0 + 0x0100503a: 4606 .F MOV r6,r0 + 0x0100503c: 484f OH LDR r0,[pc,#316] ; [0x100517c] = 0x20028 + 0x0100503e: 8800 .. LDRH r0,[r0,#0] + 0x01005040: 2800 .( CMP r0,#0 + 0x01005042: d179 y. BNE 0x1005138 ; rt_schedule + 260 + 0x01005044: 484e NH LDR r0,[pc,#312] ; [0x1005180] = 0x20024 + 0x01005046: 6800 .h LDR r0,[r0,#0] + 0x01005048: 2800 .( CMP r0,#0 + 0x0100504a: d076 v. BEQ 0x100513a ; rt_schedule + 262 + 0x0100504c: 2700 .' MOVS r7,#0 + 0x0100504e: 4668 hF MOV r0,sp + 0x01005050: f7fcf988 .... BL _scheduler_get_highest_priority_thread ; 0x1001364 + 0x01005054: 4604 .F MOV r4,r0 + 0x01005056: 484b KH LDR r0,[pc,#300] ; [0x1005184] = 0x2002c + 0x01005058: 6800 .h LDR r0,[r0,#0] + 0x0100505a: 3020 0 ADDS r0,r0,#0x20 + 0x0100505c: 7d00 .} LDRB r0,[r0,#0x14] + 0x0100505e: 0740 @. LSLS r0,r0,#29 + 0x01005060: 0f40 @. LSRS r0,r0,#29 + 0x01005062: 2803 .( CMP r0,#3 + 0x01005064: d126 &. BNE 0x10050b4 ; rt_schedule + 128 + 0x01005066: 4847 GH LDR r0,[pc,#284] ; [0x1005184] = 0x2002c + 0x01005068: 6800 .h LDR r0,[r0,#0] + 0x0100506a: 3020 0 ADDS r0,r0,#0x20 + 0x0100506c: 7d40 @} LDRB r0,[r0,#0x15] + 0x0100506e: 9900 .. LDR r1,[sp,#0] + 0x01005070: 4288 .B CMP r0,r1 + 0x01005072: d202 .. BCS 0x100507a ; rt_schedule + 70 + 0x01005074: 4843 CH LDR r0,[pc,#268] ; [0x1005184] = 0x2002c + 0x01005076: 6804 .h LDR r4,[r0,#0] + 0x01005078: e012 .. B 0x10050a0 ; rt_schedule + 108 + 0x0100507a: 4842 BH LDR r0,[pc,#264] ; [0x1005184] = 0x2002c + 0x0100507c: 6800 .h LDR r0,[r0,#0] + 0x0100507e: 3020 0 ADDS r0,r0,#0x20 + 0x01005080: 7d40 @} LDRB r0,[r0,#0x15] + 0x01005082: 9900 .. LDR r1,[sp,#0] + 0x01005084: 4288 .B CMP r0,r1 + 0x01005086: d10a .. BNE 0x100509e ; rt_schedule + 106 + 0x01005088: 483e >H LDR r0,[pc,#248] ; [0x1005184] = 0x2002c + 0x0100508a: 6800 .h LDR r0,[r0,#0] + 0x0100508c: 3020 0 ADDS r0,r0,#0x20 + 0x0100508e: 7d00 .} LDRB r0,[r0,#0x14] + 0x01005090: 2108 .! MOVS r1,#8 + 0x01005092: 4008 .@ ANDS r0,r0,r1 + 0x01005094: 2800 .( CMP r0,#0 + 0x01005096: d102 .. BNE 0x100509e ; rt_schedule + 106 + 0x01005098: 483a :H LDR r0,[pc,#232] ; [0x1005184] = 0x2002c + 0x0100509a: 6804 .h LDR r4,[r0,#0] + 0x0100509c: e000 .. B 0x10050a0 ; rt_schedule + 108 + 0x0100509e: 2701 .' MOVS r7,#1 + 0x010050a0: 4838 8H LDR r0,[pc,#224] ; [0x1005184] = 0x2002c + 0x010050a2: 6800 .h LDR r0,[r0,#0] + 0x010050a4: 3020 0 ADDS r0,r0,#0x20 + 0x010050a6: 7d00 .} LDRB r0,[r0,#0x14] + 0x010050a8: 2108 .! MOVS r1,#8 + 0x010050aa: 4388 .C BICS r0,r0,r1 + 0x010050ac: 4935 5I LDR r1,[pc,#212] ; [0x1005184] = 0x2002c + 0x010050ae: 6809 .h LDR r1,[r1,#0] + 0x010050b0: 3120 1 ADDS r1,r1,#0x20 + 0x010050b2: 7508 .u STRB r0,[r1,#0x14] + 0x010050b4: 4833 3H LDR r0,[pc,#204] ; [0x1005184] = 0x2002c + 0x010050b6: 6800 .h LDR r0,[r0,#0] + 0x010050b8: 4284 .B CMP r4,r0 + 0x010050ba: d048 H. BEQ 0x100514e ; rt_schedule + 282 + 0x010050bc: 4932 2I LDR r1,[pc,#200] ; [0x1005188] = 0x20030 + 0x010050be: 9800 .. LDR r0,[sp,#0] + 0x010050c0: 7008 .p STRB r0,[r1,#0] + 0x010050c2: 4830 0H LDR r0,[pc,#192] ; [0x1005184] = 0x2002c + 0x010050c4: 6805 .h LDR r5,[r0,#0] + 0x010050c6: 6004 .` STR r4,[r0,#0] + 0x010050c8: bf00 .. NOP + 0x010050ca: 4830 0H LDR r0,[pc,#192] ; [0x100518c] = 0x20034 + 0x010050cc: 6800 .h LDR r0,[r0,#0] + 0x010050ce: 2800 .( CMP r0,#0 + 0x010050d0: d004 .. BEQ 0x10050dc ; rt_schedule + 168 + 0x010050d2: 4621 !F MOV r1,r4 + 0x010050d4: 4628 (F MOV r0,r5 + 0x010050d6: 4a2d -J LDR r2,[pc,#180] ; [0x100518c] = 0x20034 + 0x010050d8: 6812 .h LDR r2,[r2,#0] + 0x010050da: 4790 .G BLX r2 + 0x010050dc: bf00 .. NOP + 0x010050de: 2f00 ./ CMP r7,#0 + 0x010050e0: d002 .. BEQ 0x10050e8 ; rt_schedule + 180 + 0x010050e2: 4628 (F MOV r0,r5 + 0x010050e4: f000f858 ..X. BL rt_schedule_insert_thread ; 0x1005198 + 0x010050e8: 4620 F MOV r0,r4 + 0x010050ea: f000f8a5 .... BL rt_schedule_remove_thread ; 0x1005238 + 0x010050ee: 2034 4 MOVS r0,#0x34 + 0x010050f0: 5d00 .] LDRB r0,[r0,r4] + 0x010050f2: 08c0 .. LSRS r0,r0,#3 + 0x010050f4: 00c0 .. LSLS r0,r0,#3 + 0x010050f6: 2103 .! MOVS r1,#3 + 0x010050f8: 4308 .C ORRS r0,r0,r1 + 0x010050fa: 2134 4! MOVS r1,#0x34 + 0x010050fc: 5508 .U STRB r0,[r1,r4] + 0x010050fe: bf00 .. NOP + 0x01005100: bf00 .. NOP + 0x01005102: 4620 F MOV r0,r4 + 0x01005104: f7fcf8cc .... BL _rt_scheduler_stack_check ; 0x10012a0 + 0x01005108: 4821 !H LDR r0,[pc,#132] ; [0x1005190] = 0x20124 + 0x0100510a: 7800 .x LDRB r0,[r0,#0] + 0x0100510c: 2800 .( CMP r0,#0 + 0x0100510e: d115 .. BNE 0x100513c ; rt_schedule + 264 + 0x01005110: bf00 .. NOP + 0x01005112: 4820 H LDR r0,[pc,#128] ; [0x1005194] = 0x20038 + 0x01005114: 6800 .h LDR r0,[r0,#0] + 0x01005116: 2800 .( CMP r0,#0 + 0x01005118: d003 .. BEQ 0x1005122 ; rt_schedule + 238 + 0x0100511a: 4628 (F MOV r0,r5 + 0x0100511c: 491d .I LDR r1,[pc,#116] ; [0x1005194] = 0x20038 + 0x0100511e: 6809 .h LDR r1,[r1,#0] + 0x01005120: 4788 .G BLX r1 + 0x01005122: bf00 .. NOP + 0x01005124: 4621 !F MOV r1,r4 + 0x01005126: 311c .1 ADDS r1,r1,#0x1c + 0x01005128: 4628 (F MOV r0,r5 + 0x0100512a: 301c .0 ADDS r0,r0,#0x1c + 0x0100512c: f7fbf9cf .... BL rt_hw_context_switch ; 0x10004ce + 0x01005130: 4630 0F MOV r0,r6 + 0x01005132: f7fbf9c9 .... BL rt_hw_interrupt_enable ; 0x10004c8 + 0x01005136: e020 . B 0x100517a ; rt_schedule + 326 + 0x01005138: e01b .. B 0x1005172 ; rt_schedule + 318 + 0x0100513a: e019 .. B 0x1005170 ; rt_schedule + 316 + 0x0100513c: bf00 .. NOP + 0x0100513e: bf00 .. NOP + 0x01005140: 4621 !F MOV r1,r4 + 0x01005142: 311c .1 ADDS r1,r1,#0x1c + 0x01005144: 4628 (F MOV r0,r5 + 0x01005146: 301c .0 ADDS r0,r0,#0x1c + 0x01005148: f7fbf9c1 .... BL rt_hw_context_switch ; 0x10004ce + 0x0100514c: e00f .. B 0x100516e ; rt_schedule + 314 + 0x0100514e: 480d .H LDR r0,[pc,#52] ; [0x1005184] = 0x2002c + 0x01005150: 6800 .h LDR r0,[r0,#0] + 0x01005152: f000f871 ..q. BL rt_schedule_remove_thread ; 0x1005238 + 0x01005156: 480b .H LDR r0,[pc,#44] ; [0x1005184] = 0x2002c + 0x01005158: 6800 .h LDR r0,[r0,#0] + 0x0100515a: 3020 0 ADDS r0,r0,#0x20 + 0x0100515c: 7d00 .} LDRB r0,[r0,#0x14] + 0x0100515e: 08c0 .. LSRS r0,r0,#3 + 0x01005160: 00c0 .. LSLS r0,r0,#3 + 0x01005162: 2103 .! MOVS r1,#3 + 0x01005164: 4308 .C ORRS r0,r0,r1 + 0x01005166: 4907 .I LDR r1,[pc,#28] ; [0x1005184] = 0x2002c + 0x01005168: 6809 .h LDR r1,[r1,#0] + 0x0100516a: 3120 1 ADDS r1,r1,#0x20 + 0x0100516c: 7508 .u STRB r0,[r1,#0x14] + 0x0100516e: bf00 .. NOP + 0x01005170: bf00 .. NOP + 0x01005172: 4630 0F MOV r0,r6 + 0x01005174: f7fbf9a8 .... BL rt_hw_interrupt_enable ; 0x10004c8 + 0x01005178: bf00 .. NOP + 0x0100517a: bdf8 .. POP {r3-r7,pc} + $d + 0x0100517c: 00020028 (... DCD 131112 + 0x01005180: 00020024 $... DCD 131108 + 0x01005184: 0002002c ,... DCD 131116 + 0x01005188: 00020030 0... DCD 131120 + 0x0100518c: 00020034 4... DCD 131124 + 0x01005190: 00020124 $... DCD 131364 + 0x01005194: 00020038 8... DCD 131128 + $t + i.rt_schedule_insert_thread + rt_schedule_insert_thread + 0x01005198: b570 p. PUSH {r4-r6,lr} + 0x0100519a: 4604 .F MOV r4,r0 + 0x0100519c: 2c00 ., CMP r4,#0 + 0x0100519e: d104 .. BNE 0x10051aa ; rt_schedule_insert_thread + 18 + 0x010051a0: 4a1b .J LDR r2,[pc,#108] ; [0x1005210] = 0x2c7 + 0x010051a2: 491c .I LDR r1,[pc,#112] ; [0x1005214] = 0x10075b2 + 0x010051a4: a01c .. ADR r0,{pc}+0x74 ; 0x1005218 + 0x010051a6: f7fefa2b ..+. BL rt_assert_handler ; 0x1003600 + 0x010051aa: f7fbf989 .... BL rt_hw_interrupt_disable ; 0x10004c0 + 0x010051ae: 4605 .F MOV r5,r0 + 0x010051b0: 481e .H LDR r0,[pc,#120] ; [0x100522c] = 0x2002c + 0x010051b2: 6800 .h LDR r0,[r0,#0] + 0x010051b4: 4284 .B CMP r4,r0 + 0x010051b6: d108 .. BNE 0x10051ca ; rt_schedule_insert_thread + 50 + 0x010051b8: 2034 4 MOVS r0,#0x34 + 0x010051ba: 5d00 .] LDRB r0,[r0,r4] + 0x010051bc: 08c0 .. LSRS r0,r0,#3 + 0x010051be: 00c0 .. LSLS r0,r0,#3 + 0x010051c0: 2103 .! MOVS r1,#3 + 0x010051c2: 4308 .C ORRS r0,r0,r1 + 0x010051c4: 2134 4! MOVS r1,#0x34 + 0x010051c6: 5508 .U STRB r0,[r1,r4] + 0x010051c8: e01e .. B 0x1005208 ; rt_schedule_insert_thread + 112 + 0x010051ca: 2034 4 MOVS r0,#0x34 + 0x010051cc: 5d00 .] LDRB r0,[r0,r4] + 0x010051ce: 08c0 .. LSRS r0,r0,#3 + 0x010051d0: 00c0 .. LSLS r0,r0,#3 + 0x010051d2: 2101 .! MOVS r1,#1 + 0x010051d4: 4308 .C ORRS r0,r0,r1 + 0x010051d6: 2134 4! MOVS r1,#0x34 + 0x010051d8: 5508 .U STRB r0,[r1,r4] + 0x010051da: 2235 5" MOVS r2,#0x35 + 0x010051dc: 5d12 .] LDRB r2,[r2,r4] + 0x010051de: 00d2 .. LSLS r2,r2,#3 + 0x010051e0: 4b13 .K LDR r3,[pc,#76] ; [0x1005230] = 0x20274 + 0x010051e2: 18d0 .. ADDS r0,r2,r3 + 0x010051e4: 4621 !F MOV r1,r4 + 0x010051e6: 3114 .1 ADDS r1,r1,#0x14 + 0x010051e8: 6842 Bh LDR r2,[r0,#4] + 0x010051ea: 6011 .` STR r1,[r2,#0] + 0x010051ec: 6842 Bh LDR r2,[r0,#4] + 0x010051ee: 604a J` STR r2,[r1,#4] + 0x010051f0: 6041 A` STR r1,[r0,#4] + 0x010051f2: 6008 .` STR r0,[r1,#0] + 0x010051f4: bf00 .. NOP + 0x010051f6: bf00 .. NOP + 0x010051f8: bf00 .. NOP + 0x010051fa: 490e .I LDR r1,[pc,#56] ; [0x1005234] = 0x20024 + 0x010051fc: 6ba0 .k LDR r0,[r4,#0x38] + 0x010051fe: 6809 .h LDR r1,[r1,#0] + 0x01005200: 4308 .C ORRS r0,r0,r1 + 0x01005202: 490c .I LDR r1,[pc,#48] ; [0x1005234] = 0x20024 + 0x01005204: 6008 .` STR r0,[r1,#0] + 0x01005206: bf00 .. NOP + 0x01005208: 4628 (F MOV r0,r5 + 0x0100520a: f7fbf95d ..]. BL rt_hw_interrupt_enable ; 0x10004c8 + 0x0100520e: bd70 p. POP {r4-r6,pc} + $d + 0x01005210: 000002c7 .... DCD 711 + 0x01005214: 010075b2 .u.. DCD 16807346 + 0x01005218: 65726874 thre DCD 1701996660 + 0x0100521c: 21206461 ad ! DCD 555770977 + 0x01005220: 5452203d = RT DCD 1414668349 + 0x01005224: 4c554e5f _NUL DCD 1280659039 + 0x01005228: 0000004c L... DCD 76 + 0x0100522c: 0002002c ,... DCD 131116 + 0x01005230: 00020274 t... DCD 131700 + 0x01005234: 00020024 $... DCD 131108 + $t + i.rt_schedule_remove_thread + rt_schedule_remove_thread + 0x01005238: b570 p. PUSH {r4-r6,lr} + 0x0100523a: 4604 .F MOV r4,r0 + 0x0100523c: 2c00 ., CMP r4,#0 + 0x0100523e: d105 .. BNE 0x100524c ; rt_schedule_remove_thread + 20 + 0x01005240: 2265 e" MOVS r2,#0x65 + 0x01005242: 00d2 .. LSLS r2,r2,#3 + 0x01005244: 4915 .I LDR r1,[pc,#84] ; [0x100529c] = 0x10075cc + 0x01005246: a016 .. ADR r0,{pc}+0x5a ; 0x10052a0 + 0x01005248: f7fef9da .... BL rt_assert_handler ; 0x1003600 + 0x0100524c: f7fbf938 ..8. BL rt_hw_interrupt_disable ; 0x10004c0 + 0x01005250: 4605 .F MOV r5,r0 + 0x01005252: bf00 .. NOP + 0x01005254: bf00 .. NOP + 0x01005256: 4620 F MOV r0,r4 + 0x01005258: 3014 .0 ADDS r0,r0,#0x14 + 0x0100525a: 6802 .h LDR r2,[r0,#0] + 0x0100525c: 6841 Ah LDR r1,[r0,#4] + 0x0100525e: 6051 Q` STR r1,[r2,#4] + 0x01005260: 6842 Bh LDR r2,[r0,#4] + 0x01005262: 6801 .h LDR r1,[r0,#0] + 0x01005264: 6011 .` STR r1,[r2,#0] + 0x01005266: 6040 @` STR r0,[r0,#4] + 0x01005268: 6000 .` STR r0,[r0,#0] + 0x0100526a: bf00 .. NOP + 0x0100526c: 2135 5! MOVS r1,#0x35 + 0x0100526e: 5d09 .] LDRB r1,[r1,r4] + 0x01005270: 00c9 .. LSLS r1,r1,#3 + 0x01005272: 4a10 .J LDR r2,[pc,#64] ; [0x10052b4] = 0x20274 + 0x01005274: 1888 .. ADDS r0,r1,r2 + 0x01005276: 6801 .h LDR r1,[r0,#0] + 0x01005278: 4281 .B CMP r1,r0 + 0x0100527a: d101 .. BNE 0x1005280 ; rt_schedule_remove_thread + 72 + 0x0100527c: 2101 .! MOVS r1,#1 + 0x0100527e: e000 .. B 0x1005282 ; rt_schedule_remove_thread + 74 + 0x01005280: 2100 .! MOVS r1,#0 + 0x01005282: 2900 .) CMP r1,#0 + 0x01005284: d005 .. BEQ 0x1005292 ; rt_schedule_remove_thread + 90 + 0x01005286: 480c .H LDR r0,[pc,#48] ; [0x10052b8] = 0x20024 + 0x01005288: 6ba1 .k LDR r1,[r4,#0x38] + 0x0100528a: 6800 .h LDR r0,[r0,#0] + 0x0100528c: 4388 .C BICS r0,r0,r1 + 0x0100528e: 490a .I LDR r1,[pc,#40] ; [0x10052b8] = 0x20024 + 0x01005290: 6008 .` STR r0,[r1,#0] + 0x01005292: 4628 (F MOV r0,r5 + 0x01005294: f7fbf918 .... BL rt_hw_interrupt_enable ; 0x10004c8 + 0x01005298: bd70 p. POP {r4-r6,pc} + $d + 0x0100529a: 0000 .. DCW 0 + 0x0100529c: 010075cc .u.. DCD 16807372 + 0x010052a0: 65726874 thre DCD 1701996660 + 0x010052a4: 21206461 ad ! DCD 555770977 + 0x010052a8: 5452203d = RT DCD 1414668349 + 0x010052ac: 4c554e5f _NUL DCD 1280659039 + 0x010052b0: 0000004c L... DCD 76 + 0x010052b4: 00020274 t... DCD 131700 + 0x010052b8: 00020024 $... DCD 131108 + $t + i.rt_sem_init + rt_sem_init + 0x010052bc: b5f8 .. PUSH {r3-r7,lr} + 0x010052be: 4604 .F MOV r4,r0 + 0x010052c0: 460e .F MOV r6,r1 + 0x010052c2: 4615 .F MOV r5,r2 + 0x010052c4: 461f .F MOV r7,r3 + 0x010052c6: 2c00 ., CMP r4,#0 + 0x010052c8: d105 .. BNE 0x10052d6 ; rt_sem_init + 26 + 0x010052ca: 22ff ." MOVS r2,#0xff + 0x010052cc: 3221 !2 ADDS r2,r2,#0x21 + 0x010052ce: 490d .I LDR r1,[pc,#52] ; [0x1005304] = 0x10077e7 + 0x010052d0: a00d .. ADR r0,{pc}+0x38 ; 0x1005308 + 0x010052d2: f7fef995 .... BL rt_assert_handler ; 0x1003600 + 0x010052d6: 2001 . MOVS r0,#1 + 0x010052d8: 0400 .. LSLS r0,r0,#16 + 0x010052da: 4285 .B CMP r5,r0 + 0x010052dc: d305 .. BCC 0x10052ea ; rt_sem_init + 46 + 0x010052de: 22ff ." MOVS r2,#0xff + 0x010052e0: 3222 "2 ADDS r2,r2,#0x22 + 0x010052e2: 4908 .I LDR r1,[pc,#32] ; [0x1005304] = 0x10077e7 + 0x010052e4: a00c .. ADR r0,{pc}+0x34 ; 0x1005318 + 0x010052e6: f7fef98b .... BL rt_assert_handler ; 0x1003600 + 0x010052ea: 4632 2F MOV r2,r6 + 0x010052ec: 2102 .! MOVS r1,#2 + 0x010052ee: 4620 F MOV r0,r4 + 0x010052f0: f7fffdd6 .... BL rt_object_init ; 0x1004ea0 + 0x010052f4: 4620 F MOV r0,r4 + 0x010052f6: f7fbfef3 .... BL _ipc_object_init ; 0x10010e0 + 0x010052fa: 83a5 .. STRH r5,[r4,#0x1c] + 0x010052fc: 7267 gr STRB r7,[r4,#9] + 0x010052fe: 2000 . MOVS r0,#0 + 0x01005300: bdf8 .. POP {r3-r7,pc} + $d + 0x01005302: 0000 .. DCW 0 + 0x01005304: 010077e7 .w.. DCD 16807911 + 0x01005308: 206d6573 sem DCD 544040307 + 0x0100530c: 52203d21 != R DCD 1377844513 + 0x01005310: 554e5f54 T_NU DCD 1431199572 + 0x01005314: 00004c4c LL.. DCD 19532 + 0x01005318: 756c6176 valu DCD 1970037110 + 0x0100531c: 203c2065 e < DCD 540811365 + 0x01005320: 30317830 0x10 DCD 808548400 + 0x01005324: 55303030 000U DCD 1429221424 + 0x01005328: 00000000 .... DCD 0 + $t + i.rt_sem_release + rt_sem_release + 0x0100532c: b570 p. PUSH {r4-r6,lr} + 0x0100532e: 4604 .F MOV r4,r0 + 0x01005330: 2c00 ., CMP r4,#0 + 0x01005332: d105 .. BNE 0x1005340 ; rt_sem_release + 20 + 0x01005334: 2225 %" MOVS r2,#0x25 + 0x01005336: 0112 .. LSLS r2,r2,#4 + 0x01005338: 4920 I LDR r1,[pc,#128] ; [0x10053bc] = 0x1007829 + 0x0100533a: a021 !. ADR r0,{pc}+0x86 ; 0x10053c0 + 0x0100533c: f7fef960 ..`. BL rt_assert_handler ; 0x1003600 + 0x01005340: 4620 F MOV r0,r4 + 0x01005342: f7fffd93 .... BL rt_object_get_type ; 0x1004e6c + 0x01005346: 2802 .( CMP r0,#2 + 0x01005348: d004 .. BEQ 0x1005354 ; rt_sem_release + 40 + 0x0100534a: 4a21 !J LDR r2,[pc,#132] ; [0x10053d0] = 0x251 + 0x0100534c: 491b .I LDR r1,[pc,#108] ; [0x10053bc] = 0x1007829 + 0x0100534e: 4821 !H LDR r0,[pc,#132] ; [0x10053d4] = 0x1007f08 + 0x01005350: f7fef956 ..V. BL rt_assert_handler ; 0x1003600 + 0x01005354: bf00 .. NOP + 0x01005356: 4820 H LDR r0,[pc,#128] ; [0x10053d8] = 0x20118 + 0x01005358: 6800 .h LDR r0,[r0,#0] + 0x0100535a: 2800 .( CMP r0,#0 + 0x0100535c: d003 .. BEQ 0x1005366 ; rt_sem_release + 58 + 0x0100535e: 4620 F MOV r0,r4 + 0x01005360: 491d .I LDR r1,[pc,#116] ; [0x10053d8] = 0x20118 + 0x01005362: 6809 .h LDR r1,[r1,#0] + 0x01005364: 4788 .G BLX r1 + 0x01005366: bf00 .. NOP + 0x01005368: 2500 .% MOVS r5,#0 + 0x0100536a: f7fbf8a9 .... BL rt_hw_interrupt_disable ; 0x10004c0 + 0x0100536e: 4606 .F MOV r6,r0 + 0x01005370: bf00 .. NOP + 0x01005372: bf00 .. NOP + 0x01005374: 4620 F MOV r0,r4 + 0x01005376: 3014 .0 ADDS r0,r0,#0x14 + 0x01005378: f7fff8fd .... BL rt_list_isempty ; 0x1004576 + 0x0100537c: 2800 .( CMP r0,#0 + 0x0100537e: d105 .. BNE 0x100538c ; rt_sem_release + 96 + 0x01005380: 4620 F MOV r0,r4 + 0x01005382: 3014 .0 ADDS r0,r0,#0x14 + 0x01005384: f7fbfe64 ..d. BL _ipc_list_resume ; 0x1001050 + 0x01005388: 2501 .% MOVS r5,#1 + 0x0100538a: e00d .. B 0x10053a8 ; rt_sem_release + 124 + 0x0100538c: 8ba0 .. LDRH r0,[r4,#0x1c] + 0x0100538e: 4913 .I LDR r1,[pc,#76] ; [0x10053dc] = 0xffff + 0x01005390: 4288 .B CMP r0,r1 + 0x01005392: da03 .. BGE 0x100539c ; rt_sem_release + 112 + 0x01005394: 8ba0 .. LDRH r0,[r4,#0x1c] + 0x01005396: 1c40 @. ADDS r0,r0,#1 + 0x01005398: 83a0 .. STRH r0,[r4,#0x1c] + 0x0100539a: e005 .. B 0x10053a8 ; rt_sem_release + 124 + 0x0100539c: 4630 0F MOV r0,r6 + 0x0100539e: f7fbf893 .... BL rt_hw_interrupt_enable ; 0x10004c8 + 0x010053a2: 2002 . MOVS r0,#2 + 0x010053a4: 43c0 .C MVNS r0,r0 + 0x010053a6: bd70 p. POP {r4-r6,pc} + 0x010053a8: 4630 0F MOV r0,r6 + 0x010053aa: f7fbf88d .... BL rt_hw_interrupt_enable ; 0x10004c8 + 0x010053ae: 2d01 .- CMP r5,#1 + 0x010053b0: d101 .. BNE 0x10053b6 ; rt_sem_release + 138 + 0x010053b2: f7fffe3f ..?. BL rt_schedule ; 0x1005034 + 0x010053b6: 2000 . MOVS r0,#0 + 0x010053b8: e7f5 .. B 0x10053a6 ; rt_sem_release + 122 + $d + 0x010053ba: 0000 .. DCW 0 + 0x010053bc: 01007829 )x.. DCD 16807977 + 0x010053c0: 206d6573 sem DCD 544040307 + 0x010053c4: 52203d21 != R DCD 1377844513 + 0x010053c8: 554e5f54 T_NU DCD 1431199572 + 0x010053cc: 00004c4c LL.. DCD 19532 + 0x010053d0: 00000251 Q... DCD 593 + 0x010053d4: 01007f08 .... DCD 16809736 + 0x010053d8: 00020118 .... DCD 131352 + 0x010053dc: 0000ffff .... DCD 65535 + $t + i.rt_sem_take + rt_sem_take + 0x010053e0: b5f3 .. PUSH {r0,r1,r4-r7,lr} + 0x010053e2: b081 .. SUB sp,sp,#4 + 0x010053e4: 4605 .F MOV r5,r0 + 0x010053e6: 2d00 .- CMP r5,#0 + 0x010053e8: d105 .. BNE 0x10053f6 ; rt_sem_take + 22 + 0x010053ea: 22ff ." MOVS r2,#0xff + 0x010053ec: 32d7 .2 ADDS r2,r2,#0xd7 + 0x010053ee: 4947 GI LDR r1,[pc,#284] ; [0x100550c] = 0x100781d + 0x010053f0: a047 G. ADR r0,{pc}+0x120 ; 0x1005510 + 0x010053f2: f7fef905 .... BL rt_assert_handler ; 0x1003600 + 0x010053f6: 4628 (F MOV r0,r5 + 0x010053f8: f7fffd38 ..8. BL rt_object_get_type ; 0x1004e6c + 0x010053fc: 2802 .( CMP r0,#2 + 0x010053fe: d005 .. BEQ 0x100540c ; rt_sem_take + 44 + 0x01005400: 22ff ." MOVS r2,#0xff + 0x01005402: 32d8 .2 ADDS r2,r2,#0xd8 + 0x01005404: 4941 AI LDR r1,[pc,#260] ; [0x100550c] = 0x100781d + 0x01005406: 4846 FH LDR r0,[pc,#280] ; [0x1005520] = 0x1007f08 + 0x01005408: f7fef8fa .... BL rt_assert_handler ; 0x1003600 + 0x0100540c: bf00 .. NOP + 0x0100540e: 4845 EH LDR r0,[pc,#276] ; [0x1005524] = 0x20110 + 0x01005410: 6800 .h LDR r0,[r0,#0] + 0x01005412: 2800 .( CMP r0,#0 + 0x01005414: d003 .. BEQ 0x100541e ; rt_sem_take + 62 + 0x01005416: 4628 (F MOV r0,r5 + 0x01005418: 4942 BI LDR r1,[pc,#264] ; [0x1005524] = 0x20110 + 0x0100541a: 6809 .h LDR r1,[r1,#0] + 0x0100541c: 4788 .G BLX r1 + 0x0100541e: bf00 .. NOP + 0x01005420: f7fbf84e ..N. BL rt_hw_interrupt_disable ; 0x10004c0 + 0x01005424: 4606 .F MOV r6,r0 + 0x01005426: bf00 .. NOP + 0x01005428: bf00 .. NOP + 0x0100542a: 8ba8 .. LDRH r0,[r5,#0x1c] + 0x0100542c: 2800 .( CMP r0,#0 + 0x0100542e: dd06 .. BLE 0x100543e ; rt_sem_take + 94 + 0x01005430: 8ba8 .. LDRH r0,[r5,#0x1c] + 0x01005432: 1e40 @. SUBS r0,r0,#1 + 0x01005434: 83a8 .. STRH r0,[r5,#0x1c] + 0x01005436: 4630 0F MOV r0,r6 + 0x01005438: f7fbf846 ..F. BL rt_hw_interrupt_enable ; 0x10004c8 + 0x0100543c: e05a Z. B 0x10054f4 ; rt_sem_take + 276 + 0x0100543e: 9802 .. LDR r0,[sp,#8] + 0x01005440: 2800 .( CMP r0,#0 + 0x01005442: d105 .. BNE 0x1005450 ; rt_sem_take + 112 + 0x01005444: 4630 0F MOV r0,r6 + 0x01005446: f7fbf83f ..?. BL rt_hw_interrupt_enable ; 0x10004c8 + 0x0100544a: 2001 . MOVS r0,#1 + 0x0100544c: 43c0 .C MVNS r0,r0 + 0x0100544e: bdfe .. POP {r1-r7,pc} + 0x01005450: bf00 .. NOP + 0x01005452: f7fbf835 ..5. BL rt_hw_interrupt_disable ; 0x10004c0 + 0x01005456: 9000 .. STR r0,[sp,#0] + 0x01005458: f000fda2 .... BL rt_thread_self ; 0x1005fa0 + 0x0100545c: 2800 .( CMP r0,#0 + 0x0100545e: d109 .. BNE 0x1005474 ; rt_sem_take + 148 + 0x01005460: 492a *I LDR r1,[pc,#168] ; [0x100550c] = 0x100781d + 0x01005462: a031 1. ADR r0,{pc}+0xc6 ; 0x1005528 + 0x01005464: f7fff834 ..4. BL rt_kprintf ; 0x10044d0 + 0x01005468: 22ff ." MOVS r2,#0xff + 0x0100546a: 32f8 .2 ADDS r2,r2,#0xf8 + 0x0100546c: 4927 'I LDR r1,[pc,#156] ; [0x100550c] = 0x100781d + 0x0100546e: a03c <. ADR r0,{pc}+0xf2 ; 0x1005560 + 0x01005470: f7fef8c6 .... BL rt_assert_handler ; 0x1003600 + 0x01005474: bf00 .. NOP + 0x01005476: f7fbf823 ..#. BL rt_hw_interrupt_disable ; 0x10004c0 + 0x0100547a: 4607 .F MOV r7,r0 + 0x0100547c: f7fefffe .... BL rt_interrupt_get_nest ; 0x100447c + 0x01005480: 2800 .( CMP r0,#0 + 0x01005482: d009 .. BEQ 0x1005498 ; rt_sem_take + 184 + 0x01005484: 4921 !I LDR r1,[pc,#132] ; [0x100550c] = 0x100781d + 0x01005486: a037 7. ADR r0,{pc}+0xde ; 0x1005564 + 0x01005488: f7fff822 ..". BL rt_kprintf ; 0x10044d0 + 0x0100548c: 22ff ." MOVS r2,#0xff + 0x0100548e: 32f8 .2 ADDS r2,r2,#0xf8 + 0x01005490: 491e .I LDR r1,[pc,#120] ; [0x100550c] = 0x100781d + 0x01005492: a033 3. ADR r0,{pc}+0xce ; 0x1005560 + 0x01005494: f7fef8b4 .... BL rt_assert_handler ; 0x1003600 + 0x01005498: 4638 8F MOV r0,r7 + 0x0100549a: f7fbf815 .... BL rt_hw_interrupt_enable ; 0x10004c8 + 0x0100549e: bf00 .. NOP + 0x010054a0: 9800 .. LDR r0,[sp,#0] + 0x010054a2: f7fbf811 .... BL rt_hw_interrupt_enable ; 0x10004c8 + 0x010054a6: bf00 .. NOP + 0x010054a8: f000fd7a ..z. BL rt_thread_self ; 0x1005fa0 + 0x010054ac: 4604 .F MOV r4,r0 + 0x010054ae: 2100 .! MOVS r1,#0 + 0x010054b0: 6321 !c STR r1,[r4,#0x30] + 0x010054b2: bf00 .. NOP + 0x010054b4: bf00 .. NOP + 0x010054b6: 7a6a jz LDRB r2,[r5,#9] + 0x010054b8: 4621 !F MOV r1,r4 + 0x010054ba: 4628 (F MOV r0,r5 + 0x010054bc: 3014 .0 ADDS r0,r0,#0x14 + 0x010054be: f7fbfdd3 .... BL _ipc_list_suspend ; 0x1001068 + 0x010054c2: 9802 .. LDR r0,[sp,#8] + 0x010054c4: 2800 .( CMP r0,#0 + 0x010054c6: dd0b .. BLE 0x10054e0 ; rt_sem_take + 256 + 0x010054c8: bf00 .. NOP + 0x010054ca: bf00 .. NOP + 0x010054cc: aa02 .. ADD r2,sp,#8 + 0x010054ce: 2100 .! MOVS r1,#0 + 0x010054d0: 4620 F MOV r0,r4 + 0x010054d2: 304c L0 ADDS r0,r0,#0x4c + 0x010054d4: f000ffa8 .... BL rt_timer_control ; 0x1006428 + 0x010054d8: 4620 F MOV r0,r4 + 0x010054da: 304c L0 ADDS r0,r0,#0x4c + 0x010054dc: f001f8aa .... BL rt_timer_start ; 0x1006634 + 0x010054e0: 4630 0F MOV r0,r6 + 0x010054e2: f7fafff1 .... BL rt_hw_interrupt_enable ; 0x10004c8 + 0x010054e6: f7fffda5 .... BL rt_schedule ; 0x1005034 + 0x010054ea: 6b20 k LDR r0,[r4,#0x30] + 0x010054ec: 2800 .( CMP r0,#0 + 0x010054ee: d001 .. BEQ 0x10054f4 ; rt_sem_take + 276 + 0x010054f0: 6b20 k LDR r0,[r4,#0x30] + 0x010054f2: e7ac .. B 0x100544e ; rt_sem_take + 110 + 0x010054f4: bf00 .. NOP + 0x010054f6: 4825 %H LDR r0,[pc,#148] ; [0x100558c] = 0x20114 + 0x010054f8: 6800 .h LDR r0,[r0,#0] + 0x010054fa: 2800 .( CMP r0,#0 + 0x010054fc: d003 .. BEQ 0x1005506 ; rt_sem_take + 294 + 0x010054fe: 4628 (F MOV r0,r5 + 0x01005500: 4922 "I LDR r1,[pc,#136] ; [0x100558c] = 0x20114 + 0x01005502: 6809 .h LDR r1,[r1,#0] + 0x01005504: 4788 .G BLX r1 + 0x01005506: bf00 .. NOP + 0x01005508: 2000 . MOVS r0,#0 + 0x0100550a: e7a0 .. B 0x100544e ; rt_sem_take + 110 + $d + 0x0100550c: 0100781d .x.. DCD 16807965 + 0x01005510: 206d6573 sem DCD 544040307 + 0x01005514: 52203d21 != R DCD 1377844513 + 0x01005518: 554e5f54 T_NU DCD 1431199572 + 0x0100551c: 00004c4c LL.. DCD 19532 + 0x01005520: 01007f08 .... DCD 16809736 + 0x01005524: 00020110 .... DCD 131344 + 0x01005528: 636e7546 Func DCD 1668183366 + 0x0100552c: 6e6f6974 tion DCD 1852795252 + 0x01005530: 5d73255b [%s] DCD 1567827291 + 0x01005534: 61687320 sha DCD 1634235168 + 0x01005538: 6e206c6c ll n DCD 1847618668 + 0x0100553c: 6220746f ot b DCD 1646294127 + 0x01005540: 73752065 e us DCD 1937055845 + 0x01005544: 62206465 ed b DCD 1646290021 + 0x01005548: 726f6665 efor DCD 1919903333 + 0x0100554c: 63732065 e sc DCD 1668489317 + 0x01005550: 75646568 hedu DCD 1969513832 + 0x01005554: 2072656c ler DCD 544367980 + 0x01005558: 72617473 star DCD 1918989427 + 0x0100555c: 00000a74 t... DCD 2676 + 0x01005560: 00000030 0... DCD 48 + 0x01005564: 636e7546 Func DCD 1668183366 + 0x01005568: 6e6f6974 tion DCD 1852795252 + 0x0100556c: 5d73255b [%s] DCD 1567827291 + 0x01005570: 61687320 sha DCD 1634235168 + 0x01005574: 6e206c6c ll n DCD 1847618668 + 0x01005578: 6220746f ot b DCD 1646294127 + 0x0100557c: 73752065 e us DCD 1937055845 + 0x01005580: 69206465 ed i DCD 1763730533 + 0x01005584: 5349206e n IS DCD 1397301358 + 0x01005588: 00000a52 R... DCD 2642 + 0x0100558c: 00020114 .... DCD 131348 + $t + i.rt_serial_close + rt_serial_close + 0x01005590: b570 p. PUSH {r4-r6,lr} + 0x01005592: 4604 .F MOV r4,r0 + 0x01005594: 2c00 ., CMP r4,#0 + 0x01005596: d104 .. BNE 0x10055a2 ; rt_serial_close + 18 + 0x01005598: 4a2b +J LDR r2,[pc,#172] ; [0x1005648] = 0x2e5 + 0x0100559a: 492c ,I LDR r1,[pc,#176] ; [0x100564c] = 0x1007360 + 0x0100559c: a02c ,. ADR r0,{pc}+0xb4 ; 0x1005650 + 0x0100559e: f7fef82f ../. BL rt_assert_handler ; 0x1003600 + 0x010055a2: 4625 %F MOV r5,r4 + 0x010055a4: 7ea0 .~ LDRB r0,[r4,#0x1a] + 0x010055a6: 2801 .( CMP r0,#1 + 0x010055a8: dd01 .. BLE 0x10055ae ; rt_serial_close + 30 + 0x010055aa: 2000 . MOVS r0,#0 + 0x010055ac: bd70 p. POP {r4-r6,pc} + 0x010055ae: 8b20 . LDRH r0,[r4,#0x18] + 0x010055b0: 21ff .! MOVS r1,#0xff + 0x010055b2: 3101 .1 ADDS r1,#1 + 0x010055b4: 4008 .@ ANDS r0,r0,r1 + 0x010055b6: 2800 .( CMP r0,#0 + 0x010055b8: d019 .. BEQ 0x10055ee ; rt_serial_close + 94 + 0x010055ba: 6c28 (l LDR r0,[r5,#0x40] + 0x010055bc: 460a .F MOV r2,r1 + 0x010055be: 2111 .! MOVS r1,#0x11 + 0x010055c0: 6843 Ch LDR r3,[r0,#4] + 0x010055c2: 4628 (F MOV r0,r5 + 0x010055c4: 4798 .G BLX r3 + 0x010055c6: 8b20 . LDRH r0,[r4,#0x18] + 0x010055c8: 21ff .! MOVS r1,#0xff + 0x010055ca: 3101 .1 ADDS r1,#1 + 0x010055cc: 4388 .C BICS r0,r0,r1 + 0x010055ce: 8320 . STRH r0,[r4,#0x18] + 0x010055d0: 6cee .l LDR r6,[r5,#0x4c] + 0x010055d2: 2e00 .. CMP r6,#0 + 0x010055d4: d105 .. BNE 0x10055e2 ; rt_serial_close + 82 + 0x010055d6: 22bd ." MOVS r2,#0xbd + 0x010055d8: 0092 .. LSLS r2,r2,#2 + 0x010055da: 491c .I LDR r1,[pc,#112] ; [0x100564c] = 0x1007360 + 0x010055dc: a020 . ADR r0,{pc}+0x84 ; 0x1005660 + 0x010055de: f7fef80f .... BL rt_assert_handler ; 0x1003600 + 0x010055e2: 4630 0F MOV r0,r6 + 0x010055e4: f7fefc74 ..t. BL rt_free ; 0x1003ed0 + 0x010055e8: 2000 . MOVS r0,#0 + 0x010055ea: 64e8 .d STR r0,[r5,#0x4c] + 0x010055ec: bf00 .. NOP + 0x010055ee: 8b20 . LDRH r0,[r4,#0x18] + 0x010055f0: 2101 .! MOVS r1,#1 + 0x010055f2: 0289 .. LSLS r1,r1,#10 + 0x010055f4: 4008 .@ ANDS r0,r0,r1 + 0x010055f6: 2800 .( CMP r0,#0 + 0x010055f8: d019 .. BEQ 0x100562e ; rt_serial_close + 158 + 0x010055fa: 6c28 (l LDR r0,[r5,#0x40] + 0x010055fc: 460a .F MOV r2,r1 + 0x010055fe: 2111 .! MOVS r1,#0x11 + 0x01005600: 6843 Ch LDR r3,[r0,#4] + 0x01005602: 4628 (F MOV r0,r5 + 0x01005604: 4798 .G BLX r3 + 0x01005606: 8b20 . LDRH r0,[r4,#0x18] + 0x01005608: 2101 .! MOVS r1,#1 + 0x0100560a: 0289 .. LSLS r1,r1,#10 + 0x0100560c: 4388 .C BICS r0,r0,r1 + 0x0100560e: 8320 . STRH r0,[r4,#0x18] + 0x01005610: 6d2e .m LDR r6,[r5,#0x50] + 0x01005612: 2e00 .. CMP r6,#0 + 0x01005614: d105 .. BNE 0x1005622 ; rt_serial_close + 146 + 0x01005616: 2219 ." MOVS r2,#0x19 + 0x01005618: 0152 R. LSLS r2,r2,#5 + 0x0100561a: 490c .I LDR r1,[pc,#48] ; [0x100564c] = 0x1007360 + 0x0100561c: a015 .. ADR r0,{pc}+0x58 ; 0x1005674 + 0x0100561e: f7fdffef .... BL rt_assert_handler ; 0x1003600 + 0x01005622: 4630 0F MOV r0,r6 + 0x01005624: f7fefc54 ..T. BL rt_free ; 0x1003ed0 + 0x01005628: 2000 . MOVS r0,#0 + 0x0100562a: 6528 (e STR r0,[r5,#0x50] + 0x0100562c: bf00 .. NOP + 0x0100562e: 6c28 (l LDR r0,[r5,#0x40] + 0x01005630: 2200 ." MOVS r2,#0 + 0x01005632: 2104 .! MOVS r1,#4 + 0x01005634: 6843 Ch LDR r3,[r0,#4] + 0x01005636: 4628 (F MOV r0,r5 + 0x01005638: 4798 .G BLX r3 + 0x0100563a: 8ae0 .. LDRH r0,[r4,#0x16] + 0x0100563c: 2110 .! MOVS r1,#0x10 + 0x0100563e: 4388 .C BICS r0,r0,r1 + 0x01005640: 82e0 .. STRH r0,[r4,#0x16] + 0x01005642: 2000 . MOVS r0,#0 + 0x01005644: e7b2 .. B 0x10055ac ; rt_serial_close + 28 + $d + 0x01005646: 0000 .. DCW 0 + 0x01005648: 000002e5 .... DCD 741 + 0x0100564c: 01007360 `s.. DCD 16806752 + 0x01005650: 20766564 dev DCD 544630116 + 0x01005654: 52203d21 != R DCD 1377844513 + 0x01005658: 554e5f54 T_NU DCD 1431199572 + 0x0100565c: 00004c4c LL.. DCD 19532 + 0x01005660: 665f7872 rx_f DCD 1717532786 + 0x01005664: 206f6669 ifo DCD 544171625 + 0x01005668: 52203d21 != R DCD 1377844513 + 0x0100566c: 554e5f54 T_NU DCD 1431199572 + 0x01005670: 00004c4c LL.. DCD 19532 + 0x01005674: 665f7874 tx_f DCD 1717532788 + 0x01005678: 206f6669 ifo DCD 544171625 + 0x0100567c: 52203d21 != R DCD 1377844513 + 0x01005680: 554e5f54 T_NU DCD 1431199572 + 0x01005684: 00004c4c LL.. DCD 19532 + $t + i.rt_serial_control + rt_serial_control + 0x01005688: b5f7 .. PUSH {r0-r2,r4-r7,lr} + 0x0100568a: b082 .. SUB sp,sp,#8 + 0x0100568c: 4605 .F MOV r5,r0 + 0x0100568e: 4616 .F MOV r6,r2 + 0x01005690: 2000 . MOVS r0,#0 + 0x01005692: 9001 .. STR r0,[sp,#4] + 0x01005694: 2d00 .- CMP r5,#0 + 0x01005696: d104 .. BNE 0x10056a2 ; rt_serial_control + 26 + 0x01005698: 4a20 J LDR r2,[pc,#128] ; [0x100571c] = 0x3dd + 0x0100569a: 4921 !I LDR r1,[pc,#132] ; [0x1005720] = 0x100738f + 0x0100569c: a021 !. ADR r0,{pc}+0x88 ; 0x1005724 + 0x0100569e: f7fdffaf .... BL rt_assert_handler ; 0x1003600 + 0x010056a2: 462c ,F MOV r4,r5 + 0x010056a4: 9803 .. LDR r0,[sp,#0xc] + 0x010056a6: 2801 .( CMP r0,#1 + 0x010056a8: d009 .. BEQ 0x10056be ; rt_serial_control + 54 + 0x010056aa: 2802 .( CMP r0,#2 + 0x010056ac: d002 .. BEQ 0x10056b4 ; rt_serial_control + 44 + 0x010056ae: 2803 .( CMP r0,#3 + 0x010056b0: d129 ). BNE 0x1005706 ; rt_serial_control + 126 + 0x010056b2: e009 .. B 0x10056c8 ; rt_serial_control + 64 + 0x010056b4: 8ae8 .. LDRH r0,[r5,#0x16] + 0x010056b6: 2120 ! MOVS r1,#0x20 + 0x010056b8: 4308 .C ORRS r0,r0,r1 + 0x010056ba: 82e8 .. STRH r0,[r5,#0x16] + 0x010056bc: e02b +. B 0x1005716 ; rt_serial_control + 142 + 0x010056be: 8ae8 .. LDRH r0,[r5,#0x16] + 0x010056c0: 2120 ! MOVS r1,#0x20 + 0x010056c2: 4388 .C BICS r0,r0,r1 + 0x010056c4: 82e8 .. STRH r0,[r5,#0x16] + 0x010056c6: e026 &. B 0x1005716 ; rt_serial_control + 142 + 0x010056c8: 2e00 .. CMP r6,#0 + 0x010056ca: d01b .. BEQ 0x1005704 ; rt_serial_control + 124 + 0x010056cc: 4637 7F MOV r7,r6 + 0x010056ce: 6878 xh LDR r0,[r7,#4] + 0x010056d0: 0180 .. LSLS r0,r0,#6 + 0x010056d2: 0c01 .. LSRS r1,r0,#16 + 0x010056d4: 6ca0 .l LDR r0,[r4,#0x48] + 0x010056d6: 0180 .. LSLS r0,r0,#6 + 0x010056d8: 0c00 .. LSRS r0,r0,#16 + 0x010056da: 4281 .B CMP r1,r0 + 0x010056dc: d005 .. BEQ 0x10056ea ; rt_serial_control + 98 + 0x010056de: 7ea0 .~ LDRB r0,[r4,#0x1a] + 0x010056e0: 2800 .( CMP r0,#0 + 0x010056e2: d002 .. BEQ 0x10056ea ; rt_serial_control + 98 + 0x010056e4: 2007 . MOVS r0,#7 + 0x010056e6: b005 .. ADD sp,sp,#0x14 + 0x010056e8: bdf0 .. POP {r4-r7,pc} + 0x010056ea: 687a zh LDR r2,[r7,#4] + 0x010056ec: 6839 9h LDR r1,[r7,#0] + 0x010056ee: 64a2 .d STR r2,[r4,#0x48] + 0x010056f0: 6461 ad STR r1,[r4,#0x44] + 0x010056f2: 7ea0 .~ LDRB r0,[r4,#0x1a] + 0x010056f4: 2800 .( CMP r0,#0 + 0x010056f6: d004 .. BEQ 0x1005702 ; rt_serial_control + 122 + 0x010056f8: 6c20 l LDR r0,[r4,#0x40] + 0x010056fa: 4631 1F MOV r1,r6 + 0x010056fc: 6802 .h LDR r2,[r0,#0] + 0x010056fe: 4620 F MOV r0,r4 + 0x01005700: 4790 .G BLX r2 + 0x01005702: bf00 .. NOP + 0x01005704: e007 .. B 0x1005716 ; rt_serial_control + 142 + 0x01005706: 6c20 l LDR r0,[r4,#0x40] + 0x01005708: 4632 2F MOV r2,r6 + 0x0100570a: 6843 Ch LDR r3,[r0,#4] + 0x0100570c: 4620 F MOV r0,r4 + 0x0100570e: 9903 .. LDR r1,[sp,#0xc] + 0x01005710: 4798 .G BLX r3 + 0x01005712: 9001 .. STR r0,[sp,#4] + 0x01005714: bf00 .. NOP + 0x01005716: bf00 .. NOP + 0x01005718: 9801 .. LDR r0,[sp,#4] + 0x0100571a: e7e4 .. B 0x10056e6 ; rt_serial_control + 94 + $d + 0x0100571c: 000003dd .... DCD 989 + 0x01005720: 0100738f .s.. DCD 16806799 + 0x01005724: 20766564 dev DCD 544630116 + 0x01005728: 52203d21 != R DCD 1377844513 + 0x0100572c: 554e5f54 T_NU DCD 1431199572 + 0x01005730: 00004c4c LL.. DCD 19532 + $t + i.rt_serial_init + rt_serial_init + 0x01005734: b570 p. PUSH {r4-r6,lr} + 0x01005736: 4605 .F MOV r5,r0 + 0x01005738: 2600 .& MOVS r6,#0 + 0x0100573a: 2d00 .- CMP r5,#0 + 0x0100573c: d104 .. BNE 0x1005748 ; rt_serial_init + 20 + 0x0100573e: 4a0b .J LDR r2,[pc,#44] ; [0x100576c] = 0x241 + 0x01005740: 490b .I LDR r1,[pc,#44] ; [0x1005770] = 0x1007342 + 0x01005742: a00c .. ADR r0,{pc}+0x32 ; 0x1005774 + 0x01005744: f7fdff5c ..\. BL rt_assert_handler ; 0x1003600 + 0x01005748: 462c ,F MOV r4,r5 + 0x0100574a: 2000 . MOVS r0,#0 + 0x0100574c: 64e0 .d STR r0,[r4,#0x4c] + 0x0100574e: 6520 e STR r0,[r4,#0x50] + 0x01005750: 6c20 l LDR r0,[r4,#0x40] + 0x01005752: 6800 .h LDR r0,[r0,#0] + 0x01005754: 2800 .( CMP r0,#0 + 0x01005756: d006 .. BEQ 0x1005766 ; rt_serial_init + 50 + 0x01005758: 6c20 l LDR r0,[r4,#0x40] + 0x0100575a: 4621 !F MOV r1,r4 + 0x0100575c: 3144 D1 ADDS r1,r1,#0x44 + 0x0100575e: 6802 .h LDR r2,[r0,#0] + 0x01005760: 4620 F MOV r0,r4 + 0x01005762: 4790 .G BLX r2 + 0x01005764: 4606 .F MOV r6,r0 + 0x01005766: 4630 0F MOV r0,r6 + 0x01005768: bd70 p. POP {r4-r6,pc} + $d + 0x0100576a: 0000 .. DCW 0 + 0x0100576c: 00000241 A... DCD 577 + 0x01005770: 01007342 Bs.. DCD 16806722 + 0x01005774: 20766564 dev DCD 544630116 + 0x01005778: 52203d21 != R DCD 1377844513 + 0x0100577c: 554e5f54 T_NU DCD 1431199572 + 0x01005780: 00004c4c LL.. DCD 19532 + $t + i.rt_serial_open + rt_serial_open + 0x01005784: b5f8 .. PUSH {r3-r7,lr} + 0x01005786: 4604 .F MOV r4,r0 + 0x01005788: 460e .F MOV r6,r1 + 0x0100578a: 2000 . MOVS r0,#0 + 0x0100578c: 9000 .. STR r0,[sp,#0] + 0x0100578e: 2c00 ., CMP r4,#0 + 0x01005790: d105 .. BNE 0x100579e ; rt_serial_open + 26 + 0x01005792: 2295 ." MOVS r2,#0x95 + 0x01005794: 0092 .. LSLS r2,r2,#2 + 0x01005796: 4960 `I LDR r1,[pc,#384] ; [0x1005918] = 0x1007351 + 0x01005798: a060 `. ADR r0,{pc}+0x184 ; 0x100591c + 0x0100579a: f7fdff31 ..1. BL rt_assert_handler ; 0x1003600 + 0x0100579e: 4625 %F MOV r5,r4 + 0x010057a0: 2001 . MOVS r0,#1 + 0x010057a2: 0240 @. LSLS r0,r0,#9 + 0x010057a4: 4030 0@ ANDS r0,r0,r6 + 0x010057a6: 2800 .( CMP r0,#0 + 0x010057a8: d008 .. BEQ 0x10057bc ; rt_serial_open + 56 + 0x010057aa: 8ae0 .. LDRH r0,[r4,#0x16] + 0x010057ac: 2101 .! MOVS r1,#1 + 0x010057ae: 0249 I. LSLS r1,r1,#9 + 0x010057b0: 4008 .@ ANDS r0,r0,r1 + 0x010057b2: 2800 .( CMP r0,#0 + 0x010057b4: d102 .. BNE 0x10057bc ; rt_serial_open + 56 + 0x010057b6: 2007 . MOVS r0,#7 + 0x010057b8: 43c0 .C MVNS r0,r0 + 0x010057ba: bdf8 .. POP {r3-r7,pc} + 0x010057bc: 2001 . MOVS r0,#1 + 0x010057be: 02c0 .. LSLS r0,r0,#11 + 0x010057c0: 4030 0@ ANDS r0,r0,r6 + 0x010057c2: 2800 .( CMP r0,#0 + 0x010057c4: d008 .. BEQ 0x10057d8 ; rt_serial_open + 84 + 0x010057c6: 8ae0 .. LDRH r0,[r4,#0x16] + 0x010057c8: 2101 .! MOVS r1,#1 + 0x010057ca: 02c9 .. LSLS r1,r1,#11 + 0x010057cc: 4008 .@ ANDS r0,r0,r1 + 0x010057ce: 2800 .( CMP r0,#0 + 0x010057d0: d102 .. BNE 0x10057d8 ; rt_serial_open + 84 + 0x010057d2: 2007 . MOVS r0,#7 + 0x010057d4: 43c0 .C MVNS r0,r0 + 0x010057d6: e7f0 .. B 0x10057ba ; rt_serial_open + 54 + 0x010057d8: 20ff . MOVS r0,#0xff + 0x010057da: 3001 .0 ADDS r0,#1 + 0x010057dc: 4030 0@ ANDS r0,r0,r6 + 0x010057de: 2800 .( CMP r0,#0 + 0x010057e0: d008 .. BEQ 0x10057f4 ; rt_serial_open + 112 + 0x010057e2: 8ae0 .. LDRH r0,[r4,#0x16] + 0x010057e4: 21ff .! MOVS r1,#0xff + 0x010057e6: 3101 .1 ADDS r1,#1 + 0x010057e8: 4008 .@ ANDS r0,r0,r1 + 0x010057ea: 2800 .( CMP r0,#0 + 0x010057ec: d102 .. BNE 0x10057f4 ; rt_serial_open + 112 + 0x010057ee: 2007 . MOVS r0,#7 + 0x010057f0: 43c0 .C MVNS r0,r0 + 0x010057f2: e7e2 .. B 0x10057ba ; rt_serial_open + 54 + 0x010057f4: 2001 . MOVS r0,#1 + 0x010057f6: 0280 .. LSLS r0,r0,#10 + 0x010057f8: 4030 0@ ANDS r0,r0,r6 + 0x010057fa: 2800 .( CMP r0,#0 + 0x010057fc: d008 .. BEQ 0x1005810 ; rt_serial_open + 140 + 0x010057fe: 8ae0 .. LDRH r0,[r4,#0x16] + 0x01005800: 2101 .! MOVS r1,#1 + 0x01005802: 0289 .. LSLS r1,r1,#10 + 0x01005804: 4008 .@ ANDS r0,r0,r1 + 0x01005806: 2800 .( CMP r0,#0 + 0x01005808: d102 .. BNE 0x1005810 ; rt_serial_open + 140 + 0x0100580a: 2007 . MOVS r0,#7 + 0x0100580c: 43c0 .C MVNS r0,r0 + 0x0100580e: e7d4 .. B 0x10057ba ; rt_serial_open + 54 + 0x01005810: 2040 @ MOVS r0,#0x40 + 0x01005812: 4030 0@ ANDS r0,r0,r6 + 0x01005814: 2800 .( CMP r0,#0 + 0x01005816: d104 .. BNE 0x1005822 ; rt_serial_open + 158 + 0x01005818: 8b20 . LDRH r0,[r4,#0x18] + 0x0100581a: 2140 @! MOVS r1,#0x40 + 0x0100581c: 4008 .@ ANDS r0,r0,r1 + 0x0100581e: 2800 .( CMP r0,#0 + 0x01005820: d001 .. BEQ 0x1005826 ; rt_serial_open + 162 + 0x01005822: 2040 @ MOVS r0,#0x40 + 0x01005824: 9000 .. STR r0,[sp,#0] + 0x01005826: b2f0 .. UXTB r0,r6 + 0x01005828: 8320 . STRH r0,[r4,#0x18] + 0x0100582a: 6ce8 .l LDR r0,[r5,#0x4c] + 0x0100582c: 2800 .( CMP r0,#0 + 0x0100582e: d131 1. BNE 0x1005894 ; rt_serial_open + 272 + 0x01005830: 20ff . MOVS r0,#0xff + 0x01005832: 3001 .0 ADDS r0,#1 + 0x01005834: 4030 0@ ANDS r0,r0,r6 + 0x01005836: 2800 .( CMP r0,#0 + 0x01005838: d029 ). BEQ 0x100588e ; rt_serial_open + 266 + 0x0100583a: 6ca9 .l LDR r1,[r5,#0x48] + 0x0100583c: 0189 .. LSLS r1,r1,#6 + 0x0100583e: 0c09 .. LSRS r1,r1,#16 + 0x01005840: 4608 .F MOV r0,r1 + 0x01005842: 300c .0 ADDS r0,r0,#0xc + 0x01005844: f7fefecc .... BL rt_malloc ; 0x10045e0 + 0x01005848: 4607 .F MOV r7,r0 + 0x0100584a: 2f00 ./ CMP r7,#0 + 0x0100584c: d104 .. BNE 0x1005858 ; rt_serial_open + 212 + 0x0100584e: 4a37 7J LDR r2,[pc,#220] ; [0x100592c] = 0x273 + 0x01005850: 4931 1I LDR r1,[pc,#196] ; [0x1005918] = 0x1007351 + 0x01005852: a037 7. ADR r0,{pc}+0xde ; 0x1005930 + 0x01005854: f7fdfed4 .... BL rt_assert_handler ; 0x1003600 + 0x01005858: 4638 8F MOV r0,r7 + 0x0100585a: 300c .0 ADDS r0,r0,#0xc + 0x0100585c: 6038 8` STR r0,[r7,#0] + 0x0100585e: 6ca9 .l LDR r1,[r5,#0x48] + 0x01005860: 0189 .. LSLS r1,r1,#6 + 0x01005862: 0c0a .. LSRS r2,r1,#16 + 0x01005864: 2100 .! MOVS r1,#0 + 0x01005866: 6838 8h LDR r0,[r7,#0] + 0x01005868: f7fff92b ..+. BL rt_memset ; 0x1004ac2 + 0x0100586c: 2000 . MOVS r0,#0 + 0x0100586e: 80b8 .. STRH r0,[r7,#4] + 0x01005870: 80f8 .. STRH r0,[r7,#6] + 0x01005872: 60b8 .` STR r0,[r7,#8] + 0x01005874: 64ef .d STR r7,[r5,#0x4c] + 0x01005876: 8b20 . LDRH r0,[r4,#0x18] + 0x01005878: 21ff .! MOVS r1,#0xff + 0x0100587a: 3101 .1 ADDS r1,#1 + 0x0100587c: 4308 .C ORRS r0,r0,r1 + 0x0100587e: 8320 . STRH r0,[r4,#0x18] + 0x01005880: 6c28 (l LDR r0,[r5,#0x40] + 0x01005882: 460a .F MOV r2,r1 + 0x01005884: 2110 .! MOVS r1,#0x10 + 0x01005886: 6843 Ch LDR r3,[r0,#4] + 0x01005888: 4628 (F MOV r0,r5 + 0x0100588a: 4798 .G BLX r3 + 0x0100588c: e00c .. B 0x10058a8 ; rt_serial_open + 292 + 0x0100588e: 2000 . MOVS r0,#0 + 0x01005890: 64e8 .d STR r0,[r5,#0x4c] + 0x01005892: e009 .. B 0x10058a8 ; rt_serial_open + 292 + 0x01005894: 20ff . MOVS r0,#0xff + 0x01005896: 3001 .0 ADDS r0,#1 + 0x01005898: 4030 0@ ANDS r0,r0,r6 + 0x0100589a: 2800 .( CMP r0,#0 + 0x0100589c: d004 .. BEQ 0x10058a8 ; rt_serial_open + 292 + 0x0100589e: 8b20 . LDRH r0,[r4,#0x18] + 0x010058a0: 21ff .! MOVS r1,#0xff + 0x010058a2: 3101 .1 ADDS r1,#1 + 0x010058a4: 4308 .C ORRS r0,r0,r1 + 0x010058a6: 8320 . STRH r0,[r4,#0x18] + 0x010058a8: 6d28 (m LDR r0,[r5,#0x50] + 0x010058aa: 2800 .( CMP r0,#0 + 0x010058ac: d123 #. BNE 0x10058f6 ; rt_serial_open + 370 + 0x010058ae: 2001 . MOVS r0,#1 + 0x010058b0: 0280 .. LSLS r0,r0,#10 + 0x010058b2: 4030 0@ ANDS r0,r0,r6 + 0x010058b4: 2800 .( CMP r0,#0 + 0x010058b6: d01b .. BEQ 0x10058f0 ; rt_serial_open + 364 + 0x010058b8: 200c . MOVS r0,#0xc + 0x010058ba: f7fefe91 .... BL rt_malloc ; 0x10045e0 + 0x010058be: 4607 .F MOV r7,r0 + 0x010058c0: 2f00 ./ CMP r7,#0 + 0x010058c2: d105 .. BNE 0x10058d0 ; rt_serial_open + 332 + 0x010058c4: 4a19 .J LDR r2,[pc,#100] ; [0x100592c] = 0x273 + 0x010058c6: 323f ?2 ADDS r2,r2,#0x3f + 0x010058c8: 4913 .I LDR r1,[pc,#76] ; [0x1005918] = 0x1007351 + 0x010058ca: a01e .. ADR r0,{pc}+0x7a ; 0x1005944 + 0x010058cc: f7fdfe98 .... BL rt_assert_handler ; 0x1003600 + 0x010058d0: 4638 8F MOV r0,r7 + 0x010058d2: f7fdff1b .... BL rt_completion_init ; 0x100370c + 0x010058d6: 652f /e STR r7,[r5,#0x50] + 0x010058d8: 8b20 . LDRH r0,[r4,#0x18] + 0x010058da: 2101 .! MOVS r1,#1 + 0x010058dc: 0289 .. LSLS r1,r1,#10 + 0x010058de: 4308 .C ORRS r0,r0,r1 + 0x010058e0: 8320 . STRH r0,[r4,#0x18] + 0x010058e2: 6c28 (l LDR r0,[r5,#0x40] + 0x010058e4: 460a .F MOV r2,r1 + 0x010058e6: 2110 .! MOVS r1,#0x10 + 0x010058e8: 6843 Ch LDR r3,[r0,#4] + 0x010058ea: 4628 (F MOV r0,r5 + 0x010058ec: 4798 .G BLX r3 + 0x010058ee: e00c .. B 0x100590a ; rt_serial_open + 390 + 0x010058f0: 2000 . MOVS r0,#0 + 0x010058f2: 6528 (e STR r0,[r5,#0x50] + 0x010058f4: e009 .. B 0x100590a ; rt_serial_open + 390 + 0x010058f6: 2001 . MOVS r0,#1 + 0x010058f8: 0280 .. LSLS r0,r0,#10 + 0x010058fa: 4030 0@ ANDS r0,r0,r6 + 0x010058fc: 2800 .( CMP r0,#0 + 0x010058fe: d004 .. BEQ 0x100590a ; rt_serial_open + 390 + 0x01005900: 8b20 . LDRH r0,[r4,#0x18] + 0x01005902: 2101 .! MOVS r1,#1 + 0x01005904: 0289 .. LSLS r1,r1,#10 + 0x01005906: 4308 .C ORRS r0,r0,r1 + 0x01005908: 8320 . STRH r0,[r4,#0x18] + 0x0100590a: 8b20 . LDRH r0,[r4,#0x18] + 0x0100590c: 9900 .. LDR r1,[sp,#0] + 0x0100590e: 4308 .C ORRS r0,r0,r1 + 0x01005910: 8320 . STRH r0,[r4,#0x18] + 0x01005912: 2000 . MOVS r0,#0 + 0x01005914: e751 Q. B 0x10057ba ; rt_serial_open + 54 + $d + 0x01005916: 0000 .. DCW 0 + 0x01005918: 01007351 Qs.. DCD 16806737 + 0x0100591c: 20766564 dev DCD 544630116 + 0x01005920: 52203d21 != R DCD 1377844513 + 0x01005924: 554e5f54 T_NU DCD 1431199572 + 0x01005928: 00004c4c LL.. DCD 19532 + 0x0100592c: 00000273 s... DCD 627 + 0x01005930: 665f7872 rx_f DCD 1717532786 + 0x01005934: 206f6669 ifo DCD 544171625 + 0x01005938: 52203d21 != R DCD 1377844513 + 0x0100593c: 554e5f54 T_NU DCD 1431199572 + 0x01005940: 00004c4c LL.. DCD 19532 + 0x01005944: 665f7874 tx_f DCD 1717532788 + 0x01005948: 206f6669 ifo DCD 544171625 + 0x0100594c: 52203d21 != R DCD 1377844513 + 0x01005950: 554e5f54 T_NU DCD 1431199572 + 0x01005954: 00004c4c LL.. DCD 19532 + $t + i.rt_serial_read + rt_serial_read + 0x01005958: b5f8 .. PUSH {r3-r7,lr} + 0x0100595a: 4604 .F MOV r4,r0 + 0x0100595c: 4617 .F MOV r7,r2 + 0x0100595e: 461d .F MOV r5,r3 + 0x01005960: 2c00 ., CMP r4,#0 + 0x01005962: d105 .. BNE 0x1005970 ; rt_serial_read + 24 + 0x01005964: 2269 i" MOVS r2,#0x69 + 0x01005966: 00d2 .. LSLS r2,r2,#3 + 0x01005968: 490d .I LDR r1,[pc,#52] ; [0x10059a0] = 0x1007370 + 0x0100596a: a00e .. ADR r0,{pc}+0x3a ; 0x10059a4 + 0x0100596c: f7fdfe48 ..H. BL rt_assert_handler ; 0x1003600 + 0x01005970: 2d00 .- CMP r5,#0 + 0x01005972: d101 .. BNE 0x1005978 ; rt_serial_read + 32 + 0x01005974: 2000 . MOVS r0,#0 + 0x01005976: bdf8 .. POP {r3-r7,pc} + 0x01005978: 4626 &F MOV r6,r4 + 0x0100597a: 8b20 . LDRH r0,[r4,#0x18] + 0x0100597c: 21ff .! MOVS r1,#0xff + 0x0100597e: 3101 .1 ADDS r1,#1 + 0x01005980: 4008 .@ ANDS r0,r0,r1 + 0x01005982: 2800 .( CMP r0,#0 + 0x01005984: d005 .. BEQ 0x1005992 ; rt_serial_read + 58 + 0x01005986: 462a *F MOV r2,r5 + 0x01005988: 4639 9F MOV r1,r7 + 0x0100598a: 4630 0F MOV r0,r6 + 0x0100598c: f7fbfd22 ..". BL _serial_int_rx ; 0x10013d4 + 0x01005990: e7f1 .. B 0x1005976 ; rt_serial_read + 30 + 0x01005992: 462a *F MOV r2,r5 + 0x01005994: 4639 9F MOV r1,r7 + 0x01005996: 4630 0F MOV r0,r6 + 0x01005998: f7fbfdc8 .... BL _serial_poll_rx ; 0x100152c + 0x0100599c: e7eb .. B 0x1005976 ; rt_serial_read + 30 + $d + 0x0100599e: 0000 .. DCW 0 + 0x010059a0: 01007370 ps.. DCD 16806768 + 0x010059a4: 20766564 dev DCD 544630116 + 0x010059a8: 52203d21 != R DCD 1377844513 + 0x010059ac: 554e5f54 T_NU DCD 1431199572 + 0x010059b0: 00004c4c LL.. DCD 19532 + $t + i.rt_serial_write + rt_serial_write + 0x010059b4: b5f8 .. PUSH {r3-r7,lr} + 0x010059b6: 4604 .F MOV r4,r0 + 0x010059b8: 4617 .F MOV r7,r2 + 0x010059ba: 461d .F MOV r5,r3 + 0x010059bc: 2c00 ., CMP r4,#0 + 0x010059be: d104 .. BNE 0x10059ca ; rt_serial_write + 22 + 0x010059c0: 4a0d .J LDR r2,[pc,#52] ; [0x10059f8] = 0x362 + 0x010059c2: 490e .I LDR r1,[pc,#56] ; [0x10059fc] = 0x100737f + 0x010059c4: a00e .. ADR r0,{pc}+0x3c ; 0x1005a00 + 0x010059c6: f7fdfe1b .... BL rt_assert_handler ; 0x1003600 + 0x010059ca: 2d00 .- CMP r5,#0 + 0x010059cc: d101 .. BNE 0x10059d2 ; rt_serial_write + 30 + 0x010059ce: 2000 . MOVS r0,#0 + 0x010059d0: bdf8 .. POP {r3-r7,pc} + 0x010059d2: 4626 &F MOV r6,r4 + 0x010059d4: 8b20 . LDRH r0,[r4,#0x18] + 0x010059d6: 2101 .! MOVS r1,#1 + 0x010059d8: 0289 .. LSLS r1,r1,#10 + 0x010059da: 4008 .@ ANDS r0,r0,r1 + 0x010059dc: 2800 .( CMP r0,#0 + 0x010059de: d005 .. BEQ 0x10059ec ; rt_serial_write + 56 + 0x010059e0: 462a *F MOV r2,r5 + 0x010059e2: 4639 9F MOV r1,r7 + 0x010059e4: 4630 0F MOV r0,r6 + 0x010059e6: f7fbfd53 ..S. BL _serial_int_tx ; 0x1001490 + 0x010059ea: e7f1 .. B 0x10059d0 ; rt_serial_write + 28 + 0x010059ec: 462a *F MOV r2,r5 + 0x010059ee: 4639 9F MOV r1,r7 + 0x010059f0: 4630 0F MOV r0,r6 + 0x010059f2: f7fbfdcf .... BL _serial_poll_tx ; 0x1001594 + 0x010059f6: e7eb .. B 0x10059d0 ; rt_serial_write + 28 + $d + 0x010059f8: 00000362 b... DCD 866 + 0x010059fc: 0100737f .s.. DCD 16806783 + 0x01005a00: 20766564 dev DCD 544630116 + 0x01005a04: 52203d21 != R DCD 1377844513 + 0x01005a08: 554e5f54 T_NU DCD 1431199572 + 0x01005a0c: 00004c4c LL.. DCD 19532 + $t + i.rt_set_errno + rt_set_errno + 0x01005a10: b570 p. PUSH {r4-r6,lr} + 0x01005a12: 4604 .F MOV r4,r0 + 0x01005a14: f7fefd32 ..2. BL rt_interrupt_get_nest ; 0x100447c + 0x01005a18: 2800 .( CMP r0,#0 + 0x01005a1a: d002 .. BEQ 0x1005a22 ; rt_set_errno + 18 + 0x01005a1c: 4806 .H LDR r0,[pc,#24] ; [0x1005a38] = 0x20048 + 0x01005a1e: 6004 .` STR r4,[r0,#0] + 0x01005a20: bd70 p. POP {r4-r6,pc} + 0x01005a22: f000fabd .... BL rt_thread_self ; 0x1005fa0 + 0x01005a26: 4605 .F MOV r5,r0 + 0x01005a28: 2d00 .- CMP r5,#0 + 0x01005a2a: d102 .. BNE 0x1005a32 ; rt_set_errno + 34 + 0x01005a2c: 4802 .H LDR r0,[pc,#8] ; [0x1005a38] = 0x20048 + 0x01005a2e: 6004 .` STR r4,[r0,#0] + 0x01005a30: e7f6 .. B 0x1005a20 ; rt_set_errno + 16 + 0x01005a32: 632c ,c STR r4,[r5,#0x30] + 0x01005a34: bf00 .. NOP + 0x01005a36: e7f3 .. B 0x1005a20 ; rt_set_errno + 16 + $d + 0x01005a38: 00020048 H... DCD 131144 + $t + i.rt_show_version + rt_show_version + 0x01005a3c: b508 .. PUSH {r3,lr} + 0x01005a3e: a009 .. ADR r0,{pc}+0x26 ; 0x1005a64 + 0x01005a40: f7fefd46 ..F. BL rt_kprintf ; 0x10044d0 + 0x01005a44: a00a .. ADR r0,{pc}+0x2c ; 0x1005a70 + 0x01005a46: f7fefd43 ..C. BL rt_kprintf ; 0x10044d0 + 0x01005a4a: a012 .. ADR r0,{pc}+0x4a ; 0x1005a94 + 0x01005a4c: 2304 .# MOVS r3,#4 + 0x01005a4e: 2200 ." MOVS r2,#0 + 0x01005a50: 4619 .F MOV r1,r3 + 0x01005a52: 9000 .. STR r0,[sp,#0] + 0x01005a54: a012 .. ADR r0,{pc}+0x4c ; 0x1005aa0 + 0x01005a56: f7fefd3b ..;. BL rt_kprintf ; 0x10044d0 + 0x01005a5a: a019 .. ADR r0,{pc}+0x66 ; 0x1005ac0 + 0x01005a5c: f7fefd38 ..8. BL rt_kprintf ; 0x10044d0 + 0x01005a60: bd08 .. POP {r3,pc} + $d + 0x01005a62: 0000 .. DCW 0 + 0x01005a64: 205c200a . \ DCD 542908426 + 0x01005a68: 0a2f207c | /. DCD 170860668 + 0x01005a6c: 00000000 .... DCD 0 + 0x01005a70: 5452202d - RT DCD 1414668333 + 0x01005a74: 20202d20 - DCD 538979616 + 0x01005a78: 54202020 T DCD 1411391520 + 0x01005a7c: 61657268 hrea DCD 1634038376 + 0x01005a80: 704f2064 d Op DCD 1884233828 + 0x01005a84: 74617265 erat DCD 1952543333 + 0x01005a88: 20676e69 ing DCD 543649385 + 0x01005a8c: 74737953 Syst DCD 1953724755 + 0x01005a90: 000a6d65 em.. DCD 683365 + 0x01005a94: 20706553 Sep DCD 544236883 + 0x01005a98: 32203920 9 2 DCD 840972576 + 0x01005a9c: 00313230 021. DCD 3224112 + 0x01005aa0: 7c202f20 / | DCD 2082484000 + 0x01005aa4: 20205c20 \ DCD 538991648 + 0x01005aa8: 25202020 % DCD 622862368 + 0x01005aac: 64252e64 d.%d DCD 1680158308 + 0x01005ab0: 2064252e .%d DCD 543434030 + 0x01005ab4: 6c697562 buil DCD 1818850658 + 0x01005ab8: 73252064 d %s DCD 1931812964 + 0x01005abc: 0000000a .... DCD 10 + 0x01005ac0: 30303220 200 DCD 808464928 + 0x01005ac4: 202d2036 6 - DCD 539828278 + 0x01005ac8: 31323032 2021 DCD 825372722 + 0x01005acc: 706f4320 Cop DCD 1886339872 + 0x01005ad0: 67697279 yrig DCD 1734963833 + 0x01005ad4: 62207468 ht b DCD 1646294120 + 0x01005ad8: 74722079 y rt DCD 1953636473 + 0x01005adc: 7268742d -thr DCD 1919448109 + 0x01005ae0: 20646165 ead DCD 543449445 + 0x01005ae4: 6d616574 team DCD 1835099508 + 0x01005ae8: 0000000a .... DCD 10 + $t + i.rt_sprintf + rt_sprintf + 0x01005aec: b40f .. PUSH {r0-r3} + 0x01005aee: b538 8. PUSH {r3-r5,lr} + 0x01005af0: 4604 .F MOV r4,r0 + 0x01005af2: a806 .. ADD r0,sp,#0x18 + 0x01005af4: 9000 .. STR r0,[sp,#0] + 0x01005af6: 4620 F MOV r0,r4 + 0x01005af8: 9a00 .. LDR r2,[sp,#0] + 0x01005afa: 9905 .. LDR r1,[sp,#0x14] + 0x01005afc: f001f8a4 .... BL rt_vsprintf ; 0x1006c48 + 0x01005b00: 4605 .F MOV r5,r0 + 0x01005b02: 2000 . MOVS r0,#0 + 0x01005b04: 9000 .. STR r0,[sp,#0] + 0x01005b06: 4628 (F MOV r0,r5 + 0x01005b08: bc38 8. POP {r3-r5} + 0x01005b0a: bc08 .. POP {r3} + 0x01005b0c: b004 .. ADD sp,sp,#0x10 + 0x01005b0e: 4718 .G BX r3 + i.rt_strncmp + rt_strncmp + 0x01005b10: b530 0. PUSH {r4,r5,lr} + 0x01005b12: 4603 .F MOV r3,r0 + 0x01005b14: 2000 . MOVS r0,#0 + 0x01005b16: e00c .. B 0x1005b32 ; rt_strncmp + 34 + 0x01005b18: 780d .x LDRB r5,[r1,#0] + 0x01005b1a: 1c49 I. ADDS r1,r1,#1 + 0x01005b1c: 781c .x LDRB r4,[r3,#0] + 0x01005b1e: 1b64 d. SUBS r4,r4,r5 + 0x01005b20: b264 d. SXTB r4,r4 + 0x01005b22: 1e20 . SUBS r0,r4,#0 + 0x01005b24: d103 .. BNE 0x1005b2e ; rt_strncmp + 30 + 0x01005b26: 781d .x LDRB r5,[r3,#0] + 0x01005b28: 1c5b [. ADDS r3,r3,#1 + 0x01005b2a: 2d00 .- CMP r5,#0 + 0x01005b2c: d100 .. BNE 0x1005b30 ; rt_strncmp + 32 + 0x01005b2e: e002 .. B 0x1005b36 ; rt_strncmp + 38 + 0x01005b30: 1e52 R. SUBS r2,r2,#1 + 0x01005b32: 2a00 .* CMP r2,#0 + 0x01005b34: d1f0 .. BNE 0x1005b18 ; rt_strncmp + 8 + 0x01005b36: bf00 .. NOP + 0x01005b38: bd30 0. POP {r4,r5,pc} + i.rt_strncpy + rt_strncpy + 0x01005b3a: b570 p. PUSH {r4-r6,lr} + 0x01005b3c: 4603 .F MOV r3,r0 + 0x01005b3e: 2a00 .* CMP r2,#0 + 0x01005b40: d015 .. BEQ 0x1005b6e ; rt_strncpy + 52 + 0x01005b42: 4618 .F MOV r0,r3 + 0x01005b44: 460c .F MOV r4,r1 + 0x01005b46: bf00 .. NOP + 0x01005b48: 7825 %x LDRB r5,[r4,#0] + 0x01005b4a: 7005 .p STRB r5,[r0,#0] + 0x01005b4c: 1c64 d. ADDS r4,r4,#1 + 0x01005b4e: 1c40 @. ADDS r0,r0,#1 + 0x01005b50: 2d00 .- CMP r5,#0 + 0x01005b52: d107 .. BNE 0x1005b64 ; rt_strncpy + 42 + 0x01005b54: e002 .. B 0x1005b5c ; rt_strncpy + 34 + 0x01005b56: 2500 .% MOVS r5,#0 + 0x01005b58: 7005 .p STRB r5,[r0,#0] + 0x01005b5a: 1c40 @. ADDS r0,r0,#1 + 0x01005b5c: 1e55 U. SUBS r5,r2,#1 + 0x01005b5e: 1e2a *. SUBS r2,r5,#0 + 0x01005b60: d1f9 .. BNE 0x1005b56 ; rt_strncpy + 28 + 0x01005b62: e002 .. B 0x1005b6a ; rt_strncpy + 48 + 0x01005b64: 1e55 U. SUBS r5,r2,#1 + 0x01005b66: 1e2a *. SUBS r2,r5,#0 + 0x01005b68: d1ee .. BNE 0x1005b48 ; rt_strncpy + 14 + 0x01005b6a: bf00 .. NOP + 0x01005b6c: bf00 .. NOP + 0x01005b6e: 4618 .F MOV r0,r3 + 0x01005b70: bd70 p. POP {r4-r6,pc} + 0x01005b72: 0000 .. MOVS r0,r0 + i.rt_system_heap_init + rt_system_heap_init + 0x01005b74: b5f3 .. PUSH {r0,r1,r4-r7,lr} + 0x01005b76: b081 .. SUB sp,sp,#4 + 0x01005b78: 4605 .F MOV r5,r0 + 0x01005b7a: 1ce8 .. ADDS r0,r5,#3 + 0x01005b7c: 0886 .. LSRS r6,r0,#2 + 0x01005b7e: 00b6 .. LSLS r6,r6,#2 + 0x01005b80: 9802 .. LDR r0,[sp,#8] + 0x01005b82: 0887 .. LSRS r7,r0,#2 + 0x01005b84: 00bf .. LSLS r7,r7,#2 + 0x01005b86: bf00 .. NOP + 0x01005b88: f7fafc9a .... BL rt_hw_interrupt_disable ; 0x10004c0 + 0x01005b8c: 9000 .. STR r0,[sp,#0] + 0x01005b8e: f7fefc75 ..u. BL rt_interrupt_get_nest ; 0x100447c + 0x01005b92: 2800 .( CMP r0,#0 + 0x01005b94: d008 .. BEQ 0x1005ba8 ; rt_system_heap_init + 52 + 0x01005b96: 4929 )I LDR r1,[pc,#164] ; [0x1005c3c] = 0x1007bfa + 0x01005b98: a029 ). ADR r0,{pc}+0xa8 ; 0x1005c40 + 0x01005b9a: f7fefc99 .... BL rt_kprintf ; 0x10044d0 + 0x01005b9e: 22d2 ." MOVS r2,#0xd2 + 0x01005ba0: 4926 &I LDR r1,[pc,#152] ; [0x1005c3c] = 0x1007bfa + 0x01005ba2: a031 1. ADR r0,{pc}+0xc6 ; 0x1005c68 + 0x01005ba4: f7fdfd2c ..,. BL rt_assert_handler ; 0x1003600 + 0x01005ba8: 9800 .. LDR r0,[sp,#0] + 0x01005baa: f7fafc8d .... BL rt_hw_interrupt_enable ; 0x10004c8 + 0x01005bae: bf00 .. NOP + 0x01005bb0: 2f18 ./ CMP r7,#0x18 + 0x01005bb2: d908 .. BLS 0x1005bc6 ; rt_system_heap_init + 82 + 0x01005bb4: 4638 8F MOV r0,r7 + 0x01005bb6: 3818 .8 SUBS r0,r0,#0x18 + 0x01005bb8: 42b0 .B CMP r0,r6 + 0x01005bba: d304 .. BCC 0x1005bc6 ; rt_system_heap_init + 82 + 0x01005bbc: 1bb8 .. SUBS r0,r7,r6 + 0x01005bbe: 3818 .8 SUBS r0,r0,#0x18 + 0x01005bc0: 492a *I LDR r1,[pc,#168] ; [0x1005c6c] = 0x20148 + 0x01005bc2: 6008 .` STR r0,[r1,#0] + 0x01005bc4: e005 .. B 0x1005bd2 ; rt_system_heap_init + 94 + 0x01005bc6: 4629 )F MOV r1,r5 + 0x01005bc8: a029 ). ADR r0,{pc}+0xa8 ; 0x1005c70 + 0x01005bca: 9a02 .. LDR r2,[sp,#8] + 0x01005bcc: f7fefc80 .... BL rt_kprintf ; 0x10044d0 + 0x01005bd0: bdfe .. POP {r1-r7,pc} + 0x01005bd2: 4836 6H LDR r0,[pc,#216] ; [0x1005cac] = 0x2013c + 0x01005bd4: 6006 .` STR r6,[r0,#0] + 0x01005bd6: bf00 .. NOP + 0x01005bd8: bf00 .. NOP + 0x01005bda: 6804 .h LDR r4,[r0,#0] + 0x01005bdc: 20f5 . MOVS r0,#0xf5 + 0x01005bde: 0140 @. LSLS r0,r0,#5 + 0x01005be0: 8020 . STRH r0,[r4,#0] + 0x01005be2: 4822 "H LDR r0,[pc,#136] ; [0x1005c6c] = 0x20148 + 0x01005be4: 6800 .h LDR r0,[r0,#0] + 0x01005be6: 300c .0 ADDS r0,r0,#0xc + 0x01005be8: 6060 `` STR r0,[r4,#4] + 0x01005bea: 2000 . MOVS r0,#0 + 0x01005bec: 60a0 .` STR r0,[r4,#8] + 0x01005bee: 8060 `. STRH r0,[r4,#2] + 0x01005bf0: 492e .I LDR r1,[pc,#184] ; [0x1005cac] = 0x2013c + 0x01005bf2: 6860 `h LDR r0,[r4,#4] + 0x01005bf4: 6809 .h LDR r1,[r1,#0] + 0x01005bf6: 1840 @. ADDS r0,r0,r1 + 0x01005bf8: 492d -I LDR r1,[pc,#180] ; [0x1005cb0] = 0x20140 + 0x01005bfa: 6008 .` STR r0,[r1,#0] + 0x01005bfc: 20f5 . MOVS r0,#0xf5 + 0x01005bfe: 0140 @. LSLS r0,r0,#5 + 0x01005c00: 6809 .h LDR r1,[r1,#0] + 0x01005c02: 8008 .. STRH r0,[r1,#0] + 0x01005c04: 2001 . MOVS r0,#1 + 0x01005c06: 492a *I LDR r1,[pc,#168] ; [0x1005cb0] = 0x20140 + 0x01005c08: 6809 .h LDR r1,[r1,#0] + 0x01005c0a: 8048 H. STRH r0,[r1,#2] + 0x01005c0c: 4817 .H LDR r0,[pc,#92] ; [0x1005c6c] = 0x20148 + 0x01005c0e: 6800 .h LDR r0,[r0,#0] + 0x01005c10: 300c .0 ADDS r0,r0,#0xc + 0x01005c12: 4927 'I LDR r1,[pc,#156] ; [0x1005cb0] = 0x20140 + 0x01005c14: 6809 .h LDR r1,[r1,#0] + 0x01005c16: 6048 H` STR r0,[r1,#4] + 0x01005c18: 4814 .H LDR r0,[pc,#80] ; [0x1005c6c] = 0x20148 + 0x01005c1a: 6800 .h LDR r0,[r0,#0] + 0x01005c1c: 300c .0 ADDS r0,r0,#0xc + 0x01005c1e: 4924 $I LDR r1,[pc,#144] ; [0x1005cb0] = 0x20140 + 0x01005c20: 6809 .h LDR r1,[r1,#0] + 0x01005c22: 6088 .` STR r0,[r1,#8] + 0x01005c24: 2301 .# MOVS r3,#1 + 0x01005c26: 461a .F MOV r2,r3 + 0x01005c28: a122 ". ADR r1,{pc}+0x8c ; 0x1005cb4 + 0x01005c2a: 4824 $H LDR r0,[pc,#144] ; [0x1005cbc] = 0x20584 + 0x01005c2c: f7fffb46 ..F. BL rt_sem_init ; 0x10052bc + 0x01005c30: 481e .H LDR r0,[pc,#120] ; [0x1005cac] = 0x2013c + 0x01005c32: 6800 .h LDR r0,[r0,#0] + 0x01005c34: 4922 "I LDR r1,[pc,#136] ; [0x1005cc0] = 0x20144 + 0x01005c36: 6008 .` STR r0,[r1,#0] + 0x01005c38: bf00 .. NOP + 0x01005c3a: e7c9 .. B 0x1005bd0 ; rt_system_heap_init + 92 + $d + 0x01005c3c: 01007bfa .{.. DCD 16808954 + 0x01005c40: 636e7546 Func DCD 1668183366 + 0x01005c44: 6e6f6974 tion DCD 1852795252 + 0x01005c48: 5d73255b [%s] DCD 1567827291 + 0x01005c4c: 61687320 sha DCD 1634235168 + 0x01005c50: 6e206c6c ll n DCD 1847618668 + 0x01005c54: 6220746f ot b DCD 1646294127 + 0x01005c58: 73752065 e us DCD 1937055845 + 0x01005c5c: 69206465 ed i DCD 1763730533 + 0x01005c60: 5349206e n IS DCD 1397301358 + 0x01005c64: 00000a52 R... DCD 2642 + 0x01005c68: 00000030 0... DCD 48 + 0x01005c6c: 00020148 H... DCD 131400 + 0x01005c70: 206d656d mem DCD 544040301 + 0x01005c74: 74696e69 init DCD 1953066601 + 0x01005c78: 7265202c , er DCD 1919229996 + 0x01005c7c: 20726f72 ror DCD 544370546 + 0x01005c80: 69676562 begi DCD 1768383842 + 0x01005c84: 6461206e n ad DCD 1684086894 + 0x01005c88: 73657264 dres DCD 1936028260 + 0x01005c8c: 78302073 s 0x DCD 2016419955 + 0x01005c90: 202c7825 %x, DCD 539785253 + 0x01005c94: 20646e61 and DCD 543452769 + 0x01005c98: 20646e65 end DCD 543452773 + 0x01005c9c: 72646461 addr DCD 1919181921 + 0x01005ca0: 20737365 ess DCD 544437093 + 0x01005ca4: 78257830 0x%x DCD 2015721520 + 0x01005ca8: 0000000a .... DCD 10 + 0x01005cac: 0002013c <... DCD 131388 + 0x01005cb0: 00020140 @... DCD 131392 + 0x01005cb4: 70616568 heap DCD 1885431144 + 0x01005cb8: 00000000 .... DCD 0 + 0x01005cbc: 00020584 .... DCD 132484 + 0x01005cc0: 00020144 D... DCD 131396 + $t + i.rt_system_scheduler_init + rt_system_scheduler_init + 0x01005cc4: 2100 .! MOVS r1,#0 + 0x01005cc6: 4a0a .J LDR r2,[pc,#40] ; [0x1005cf0] = 0x20028 + 0x01005cc8: 8011 .. STRH r1,[r2,#0] + 0x01005cca: bf00 .. NOP + 0x01005ccc: bf00 .. NOP + 0x01005cce: 2000 . MOVS r0,#0 + 0x01005cd0: e007 .. B 0x1005ce2 ; rt_system_scheduler_init + 30 + 0x01005cd2: 00c2 .. LSLS r2,r0,#3 + 0x01005cd4: 4b07 .K LDR r3,[pc,#28] ; [0x1005cf4] = 0x20274 + 0x01005cd6: 18d1 .. ADDS r1,r2,r3 + 0x01005cd8: 6049 I` STR r1,[r1,#4] + 0x01005cda: 6009 .` STR r1,[r1,#0] + 0x01005cdc: bf00 .. NOP + 0x01005cde: 1c41 A. ADDS r1,r0,#1 + 0x01005ce0: 4608 .F MOV r0,r1 + 0x01005ce2: 2820 ( CMP r0,#0x20 + 0x01005ce4: dbf5 .. BLT 0x1005cd2 ; rt_system_scheduler_init + 14 + 0x01005ce6: 2100 .! MOVS r1,#0 + 0x01005ce8: 4a03 .J LDR r2,[pc,#12] ; [0x1005cf8] = 0x20024 + 0x01005cea: 6011 .` STR r1,[r2,#0] + 0x01005cec: 4770 pG BX lr + $d + 0x01005cee: 0000 .. DCW 0 + 0x01005cf0: 00020028 (... DCD 131112 + 0x01005cf4: 00020274 t... DCD 131700 + 0x01005cf8: 00020024 $... DCD 131108 + $t + i.rt_system_scheduler_start + rt_system_scheduler_start + 0x01005cfc: b538 8. PUSH {r3-r5,lr} + 0x01005cfe: 4668 hF MOV r0,sp + 0x01005d00: f7fbfb30 ..0. BL _scheduler_get_highest_priority_thread ; 0x1001364 + 0x01005d04: 4604 .F MOV r4,r0 + 0x01005d06: 4806 .H LDR r0,[pc,#24] ; [0x1005d20] = 0x2002c + 0x01005d08: 6004 .` STR r4,[r0,#0] + 0x01005d0a: 4620 F MOV r0,r4 + 0x01005d0c: f7fffa94 .... BL rt_schedule_remove_thread ; 0x1005238 + 0x01005d10: 2103 .! MOVS r1,#3 + 0x01005d12: 2034 4 MOVS r0,#0x34 + 0x01005d14: 5501 .U STRB r1,[r0,r4] + 0x01005d16: 4620 F MOV r0,r4 + 0x01005d18: 301c .0 ADDS r0,r0,#0x1c + 0x01005d1a: f7fafc10 .... BL rt_hw_context_switch_to ; 0x100053e + 0x01005d1e: bd38 8. POP {r3-r5,pc} + $d + 0x01005d20: 0002002c ,... DCD 131116 + $t + i.rt_system_timer_init + rt_system_timer_init + 0x01005d24: b510 .. PUSH {r4,lr} + 0x01005d26: 2400 .$ MOVS r4,#0 + 0x01005d28: e005 .. B 0x1005d36 ; rt_system_timer_init + 18 + 0x01005d2a: 00e1 .. LSLS r1,r4,#3 + 0x01005d2c: 4a03 .J LDR r2,[pc,#12] ; [0x1005d3c] = 0x20054 + 0x01005d2e: 1888 .. ADDS r0,r1,r2 + 0x01005d30: f7fefbf9 .... BL rt_list_init ; 0x1004526 + 0x01005d34: 1c64 d. ADDS r4,r4,#1 + 0x01005d36: 2c00 ., CMP r4,#0 + 0x01005d38: d0f7 .. BEQ 0x1005d2a ; rt_system_timer_init + 6 + 0x01005d3a: bd10 .. POP {r4,pc} + $d + 0x01005d3c: 00020054 T... DCD 131156 + $t + i.rt_system_timer_thread_init + rt_system_timer_thread_init + 0x01005d40: 4770 pG BX lr + i.rt_thread_create + rt_thread_create + 0x01005d42: b5ff .. PUSH {r0-r7,lr} + 0x01005d44: b085 .. SUB sp,sp,#0x14 + 0x01005d46: 4606 .F MOV r6,r0 + 0x01005d48: 460f .F MOV r7,r1 + 0x01005d4a: 461d .F MOV r5,r3 + 0x01005d4c: 4631 1F MOV r1,r6 + 0x01005d4e: 2001 . MOVS r0,#1 + 0x01005d50: f7fefede .... BL rt_object_allocate ; 0x1004b10 + 0x01005d54: 9004 .. STR r0,[sp,#0x10] + 0x01005d56: 9804 .. LDR r0,[sp,#0x10] + 0x01005d58: 2800 .( CMP r0,#0 + 0x01005d5a: d101 .. BNE 0x1005d60 ; rt_thread_create + 30 + 0x01005d5c: b009 .. ADD sp,sp,#0x24 + 0x01005d5e: bdf0 .. POP {r4-r7,pc} + 0x01005d60: 4628 (F MOV r0,r5 + 0x01005d62: f7fefc3d ..=. BL rt_malloc ; 0x10045e0 + 0x01005d66: 4604 .F MOV r4,r0 + 0x01005d68: 2c00 ., CMP r4,#0 + 0x01005d6a: d104 .. BNE 0x1005d76 ; rt_thread_create + 52 + 0x01005d6c: 9804 .. LDR r0,[sp,#0x10] + 0x01005d6e: f7feff45 ..E. BL rt_object_delete ; 0x1004bfc + 0x01005d72: 2000 . MOVS r0,#0 + 0x01005d74: e7f2 .. B 0x1005d5c ; rt_thread_create + 26 + 0x01005d76: 990e .. LDR r1,[sp,#0x38] + 0x01005d78: 980f .. LDR r0,[sp,#0x3c] + 0x01005d7a: 9501 .. STR r5,[sp,#4] + 0x01005d7c: 9400 .. STR r4,[sp,#0] + 0x01005d7e: 9102 .. STR r1,[sp,#8] + 0x01005d80: 9003 .. STR r0,[sp,#0xc] + 0x01005d82: 463a :F MOV r2,r7 + 0x01005d84: 4631 1F MOV r1,r6 + 0x01005d86: 9b07 .. LDR r3,[sp,#0x1c] + 0x01005d88: 9804 .. LDR r0,[sp,#0x10] + 0x01005d8a: f7fbfc63 ..c. BL _thread_init ; 0x1001654 + 0x01005d8e: 9804 .. LDR r0,[sp,#0x10] + 0x01005d90: e7e4 .. B 0x1005d5c ; rt_thread_create + 26 + 0x01005d92: 0000 .. MOVS r0,r0 + i.rt_thread_defunct_dequeue + rt_thread_defunct_dequeue + 0x01005d94: b510 .. PUSH {r4,lr} + 0x01005d96: 2200 ." MOVS r2,#0 + 0x01005d98: 490a .I LDR r1,[pc,#40] ; [0x1005dc4] = 0x2003c + 0x01005d9a: 6808 .h LDR r0,[r1,#0] + 0x01005d9c: 4288 .B CMP r0,r1 + 0x01005d9e: d00e .. BEQ 0x1005dbe ; rt_thread_defunct_dequeue + 42 + 0x01005da0: 6808 .h LDR r0,[r1,#0] + 0x01005da2: 4602 .F MOV r2,r0 + 0x01005da4: 3a14 .: SUBS r2,r2,#0x14 + 0x01005da6: 4610 .F MOV r0,r2 + 0x01005da8: 3014 .0 ADDS r0,r0,#0x14 + 0x01005daa: 6804 .h LDR r4,[r0,#0] + 0x01005dac: 6843 Ch LDR r3,[r0,#4] + 0x01005dae: 6063 c` STR r3,[r4,#4] + 0x01005db0: 6844 Dh LDR r4,[r0,#4] + 0x01005db2: 6803 .h LDR r3,[r0,#0] + 0x01005db4: 6023 #` STR r3,[r4,#0] + 0x01005db6: 6040 @` STR r0,[r0,#4] + 0x01005db8: 6000 .` STR r0,[r0,#0] + 0x01005dba: bf00 .. NOP + 0x01005dbc: bf00 .. NOP + 0x01005dbe: 4610 .F MOV r0,r2 + 0x01005dc0: bd10 .. POP {r4,pc} + $d + 0x01005dc2: 0000 .. DCW 0 + 0x01005dc4: 0002003c <... DCD 131132 + $t + i.rt_thread_defunct_enqueue + rt_thread_defunct_enqueue + 0x01005dc8: 4602 .F MOV r2,r0 + 0x01005dca: 4805 .H LDR r0,[pc,#20] ; [0x1005de0] = 0x2003c + 0x01005dcc: 4611 .F MOV r1,r2 + 0x01005dce: 3114 .1 ADDS r1,r1,#0x14 + 0x01005dd0: 6803 .h LDR r3,[r0,#0] + 0x01005dd2: 6059 Y` STR r1,[r3,#4] + 0x01005dd4: 6803 .h LDR r3,[r0,#0] + 0x01005dd6: 600b .` STR r3,[r1,#0] + 0x01005dd8: 6001 .` STR r1,[r0,#0] + 0x01005dda: 6048 H` STR r0,[r1,#4] + 0x01005ddc: bf00 .. NOP + 0x01005dde: 4770 pG BX lr + $d + 0x01005de0: 0002003c <... DCD 131132 + $t + i.rt_thread_idle_entry + rt_thread_idle_entry + 0x01005de4: e00d .. B 0x1005e02 ; rt_thread_idle_entry + 30 + 0x01005de6: 2400 .$ MOVS r4,#0 + 0x01005de8: e006 .. B 0x1005df8 ; rt_thread_idle_entry + 20 + 0x01005dea: 00a0 .. LSLS r0,r4,#2 + 0x01005dec: 4905 .I LDR r1,[pc,#20] ; [0x1005e04] = 0x204f4 + 0x01005dee: 580d .X LDR r5,[r1,r0] + 0x01005df0: 2d00 .- CMP r5,#0 + 0x01005df2: d000 .. BEQ 0x1005df6 ; rt_thread_idle_entry + 18 + 0x01005df4: 47a8 .G BLX r5 + 0x01005df6: 1c64 d. ADDS r4,r4,#1 + 0x01005df8: 2c04 ., CMP r4,#4 + 0x01005dfa: d3f6 .. BCC 0x1005dea ; rt_thread_idle_entry + 6 + 0x01005dfc: f7fdfd8e .... BL rt_defunct_execute ; 0x100391c + 0x01005e00: bf00 .. NOP + 0x01005e02: e7f0 .. B 0x1005de6 ; rt_thread_idle_entry + 2 + $d + 0x01005e04: 000204f4 .... DCD 132340 + $t + i.rt_thread_idle_init + rt_thread_idle_init + 0x01005e08: b530 0. PUSH {r4,r5,lr} + 0x01005e0a: b087 .. SUB sp,sp,#0x1c + 0x01005e0c: 2400 .$ MOVS r4,#0 + 0x01005e0e: e01c .. B 0x1005e4a ; rt_thread_idle_init + 66 + 0x01005e10: 4622 "F MOV r2,r4 + 0x01005e12: a110 .. ADR r1,{pc}+0x42 ; 0x1005e54 + 0x01005e14: a805 .. ADD r0,sp,#0x14 + 0x01005e16: f7fffe69 ..i. BL rt_sprintf ; 0x1005aec + 0x01005e1a: 2120 ! MOVS r1,#0x20 + 0x01005e1c: 221f ." MOVS r2,#0x1f + 0x01005e1e: 00cb .. LSLS r3,r1,#3 + 0x01005e20: 0220 . LSLS r0,r4,#8 + 0x01005e22: 4d0e .M LDR r5,[pc,#56] ; [0x1005e5c] = 0x203f4 + 0x01005e24: 1940 @. ADDS r0,r0,r5 + 0x01005e26: 9301 .. STR r3,[sp,#4] + 0x01005e28: 9202 .. STR r2,[sp,#8] + 0x01005e2a: 9103 .. STR r1,[sp,#0xc] + 0x01005e2c: 9000 .. STR r0,[sp,#0] + 0x01005e2e: 01e1 .. LSLS r1,r4,#7 + 0x01005e30: 4a0b .J LDR r2,[pc,#44] ; [0x1005e60] = 0x20374 + 0x01005e32: 1888 .. ADDS r0,r1,r2 + 0x01005e34: 2300 .# MOVS r3,#0 + 0x01005e36: 4a0b .J LDR r2,[pc,#44] ; [0x1005e64] = 0x1005de5 + 0x01005e38: a905 .. ADD r1,sp,#0x14 + 0x01005e3a: f000f815 .... BL rt_thread_init ; 0x1005e68 + 0x01005e3e: 01e1 .. LSLS r1,r4,#7 + 0x01005e40: 4a07 .J LDR r2,[pc,#28] ; [0x1005e60] = 0x20374 + 0x01005e42: 1888 .. ADDS r0,r1,r2 + 0x01005e44: f000f8f4 .... BL rt_thread_startup ; 0x1006030 + 0x01005e48: 1c64 d. ADDS r4,r4,#1 + 0x01005e4a: 2c00 ., CMP r4,#0 + 0x01005e4c: d0e0 .. BEQ 0x1005e10 ; rt_thread_idle_init + 8 + 0x01005e4e: b007 .. ADD sp,sp,#0x1c + 0x01005e50: bd30 0. POP {r4,r5,pc} + $d + 0x01005e52: 0000 .. DCW 0 + 0x01005e54: 6c646974 tidl DCD 1818519924 + 0x01005e58: 00642565 e%d. DCD 6563173 + 0x01005e5c: 000203f4 .... DCD 132084 + 0x01005e60: 00020374 t... DCD 131956 + 0x01005e64: 01005de5 .].. DCD 16801253 + $t + i.rt_thread_init + rt_thread_init + 0x01005e68: b5ff .. PUSH {r0-r7,lr} + 0x01005e6a: b085 .. SUB sp,sp,#0x14 + 0x01005e6c: 4604 .F MOV r4,r0 + 0x01005e6e: 460d .F MOV r5,r1 + 0x01005e70: 9f0f .. LDR r7,[sp,#0x3c] + 0x01005e72: 9e0e .. LDR r6,[sp,#0x38] + 0x01005e74: 2c00 ., CMP r4,#0 + 0x01005e76: d105 .. BNE 0x1005e84 ; rt_thread_init + 28 + 0x01005e78: 22ff ." MOVS r2,#0xff + 0x01005e7a: 3210 .2 ADDS r2,r2,#0x10 + 0x01005e7c: 490f .I LDR r1,[pc,#60] ; [0x1005ebc] = 0x1007b3f + 0x01005e7e: a010 .. ADR r0,{pc}+0x42 ; 0x1005ec0 + 0x01005e80: f7fdfbbe .... BL rt_assert_handler ; 0x1003600 + 0x01005e84: 2e00 .. CMP r6,#0 + 0x01005e86: d105 .. BNE 0x1005e94 ; rt_thread_init + 44 + 0x01005e88: 22ff ." MOVS r2,#0xff + 0x01005e8a: 3211 .2 ADDS r2,r2,#0x11 + 0x01005e8c: 490b .I LDR r1,[pc,#44] ; [0x1005ebc] = 0x1007b3f + 0x01005e8e: a011 .. ADR r0,{pc}+0x46 ; 0x1005ed4 + 0x01005e90: f7fdfbb6 .... BL rt_assert_handler ; 0x1003600 + 0x01005e94: 462a *F MOV r2,r5 + 0x01005e96: 2101 .! MOVS r1,#1 + 0x01005e98: 4620 F MOV r0,r4 + 0x01005e9a: f7fff801 .... BL rt_object_init ; 0x1004ea0 + 0x01005e9e: 9910 .. LDR r1,[sp,#0x40] + 0x01005ea0: 9811 .. LDR r0,[sp,#0x44] + 0x01005ea2: 9701 .. STR r7,[sp,#4] + 0x01005ea4: 9600 .. STR r6,[sp,#0] + 0x01005ea6: 9102 .. STR r1,[sp,#8] + 0x01005ea8: 9003 .. STR r0,[sp,#0xc] + 0x01005eaa: 4629 )F MOV r1,r5 + 0x01005eac: 4620 F MOV r0,r4 + 0x01005eae: 9b08 .. LDR r3,[sp,#0x20] + 0x01005eb0: 9a07 .. LDR r2,[sp,#0x1c] + 0x01005eb2: f7fbfbcf .... BL _thread_init ; 0x1001654 + 0x01005eb6: b009 .. ADD sp,sp,#0x24 + 0x01005eb8: bdf0 .. POP {r4-r7,pc} + $d + 0x01005eba: 0000 .. DCW 0 + 0x01005ebc: 01007b3f ?{.. DCD 16808767 + 0x01005ec0: 65726874 thre DCD 1701996660 + 0x01005ec4: 21206461 ad ! DCD 555770977 + 0x01005ec8: 5452203d = RT DCD 1414668349 + 0x01005ecc: 4c554e5f _NUL DCD 1280659039 + 0x01005ed0: 0000004c L... DCD 76 + 0x01005ed4: 63617473 stac DCD 1667331187 + 0x01005ed8: 74735f6b k_st DCD 1953718123 + 0x01005edc: 20747261 art DCD 544502369 + 0x01005ee0: 52203d21 != R DCD 1377844513 + 0x01005ee4: 554e5f54 T_NU DCD 1431199572 + 0x01005ee8: 00004c4c LL.. DCD 19532 + $t + i.rt_thread_mdelay + rt_thread_mdelay + 0x01005eec: b570 p. PUSH {r4-r6,lr} + 0x01005eee: 4604 .F MOV r4,r0 + 0x01005ef0: 4620 F MOV r0,r4 + 0x01005ef2: f000f9d3 .... BL rt_tick_from_millisecond ; 0x100629c + 0x01005ef6: 4605 .F MOV r5,r0 + 0x01005ef8: 4628 (F MOV r0,r5 + 0x01005efa: f000f857 ..W. BL rt_thread_sleep ; 0x1005fac + 0x01005efe: bd70 p. POP {r4-r6,pc} + i.rt_thread_resume + rt_thread_resume + 0x01005f00: b570 p. PUSH {r4-r6,lr} + 0x01005f02: 4604 .F MOV r4,r0 + 0x01005f04: 2c00 ., CMP r4,#0 + 0x01005f06: d105 .. BNE 0x1005f14 ; rt_thread_resume + 20 + 0x01005f08: 22d1 ." MOVS r2,#0xd1 + 0x01005f0a: 0092 .. LSLS r2,r2,#2 + 0x01005f0c: 491b .I LDR r1,[pc,#108] ; [0x1005f7c] = 0x1007bcc + 0x01005f0e: a01c .. ADR r0,{pc}+0x72 ; 0x1005f80 + 0x01005f10: f7fdfb76 ..v. BL rt_assert_handler ; 0x1003600 + 0x01005f14: 4620 F MOV r0,r4 + 0x01005f16: f7feffa9 .... BL rt_object_get_type ; 0x1004e6c + 0x01005f1a: 2801 .( CMP r0,#1 + 0x01005f1c: d004 .. BEQ 0x1005f28 ; rt_thread_resume + 40 + 0x01005f1e: 4a1d .J LDR r2,[pc,#116] ; [0x1005f94] = 0x345 + 0x01005f20: 4916 .I LDR r1,[pc,#88] ; [0x1005f7c] = 0x1007bcc + 0x01005f22: 481d .H LDR r0,[pc,#116] ; [0x1005f98] = 0x1007f50 + 0x01005f24: f7fdfb6c ..l. BL rt_assert_handler ; 0x1003600 + 0x01005f28: bf00 .. NOP + 0x01005f2a: bf00 .. NOP + 0x01005f2c: 2034 4 MOVS r0,#0x34 + 0x01005f2e: 5d00 .] LDRB r0,[r0,r4] + 0x01005f30: 0740 @. LSLS r0,r0,#29 + 0x01005f32: 0f40 @. LSRS r0,r0,#29 + 0x01005f34: 2802 .( CMP r0,#2 + 0x01005f36: d004 .. BEQ 0x1005f42 ; rt_thread_resume + 66 + 0x01005f38: bf00 .. NOP + 0x01005f3a: bf00 .. NOP + 0x01005f3c: 2000 . MOVS r0,#0 + 0x01005f3e: 43c0 .C MVNS r0,r0 + 0x01005f40: bd70 p. POP {r4-r6,pc} + 0x01005f42: f7fafabd .... BL rt_hw_interrupt_disable ; 0x10004c0 + 0x01005f46: 4605 .F MOV r5,r0 + 0x01005f48: 4620 F MOV r0,r4 + 0x01005f4a: 3014 .0 ADDS r0,r0,#0x14 + 0x01005f4c: f7fefb3f ..?. BL rt_list_remove ; 0x10045ce + 0x01005f50: 4620 F MOV r0,r4 + 0x01005f52: 304c L0 ADDS r0,r0,#0x4c + 0x01005f54: f000fc58 ..X. BL rt_timer_stop ; 0x1006808 + 0x01005f58: 4620 F MOV r0,r4 + 0x01005f5a: f7fff91d .... BL rt_schedule_insert_thread ; 0x1005198 + 0x01005f5e: 4628 (F MOV r0,r5 + 0x01005f60: f7fafab2 .... BL rt_hw_interrupt_enable ; 0x10004c8 + 0x01005f64: bf00 .. NOP + 0x01005f66: 480d .H LDR r0,[pc,#52] ; [0x1005f9c] = 0x2012c + 0x01005f68: 6800 .h LDR r0,[r0,#0] + 0x01005f6a: 2800 .( CMP r0,#0 + 0x01005f6c: d003 .. BEQ 0x1005f76 ; rt_thread_resume + 118 + 0x01005f6e: 4620 F MOV r0,r4 + 0x01005f70: 490a .I LDR r1,[pc,#40] ; [0x1005f9c] = 0x2012c + 0x01005f72: 6809 .h LDR r1,[r1,#0] + 0x01005f74: 4788 .G BLX r1 + 0x01005f76: bf00 .. NOP + 0x01005f78: 2000 . MOVS r0,#0 + 0x01005f7a: e7e1 .. B 0x1005f40 ; rt_thread_resume + 64 + $d + 0x01005f7c: 01007bcc .{.. DCD 16808908 + 0x01005f80: 65726874 thre DCD 1701996660 + 0x01005f84: 21206461 ad ! DCD 555770977 + 0x01005f88: 5452203d = RT DCD 1414668349 + 0x01005f8c: 4c554e5f _NUL DCD 1280659039 + 0x01005f90: 0000004c L... DCD 76 + 0x01005f94: 00000345 E... DCD 837 + 0x01005f98: 01007f50 P... DCD 16809808 + 0x01005f9c: 0002012c ,... DCD 131372 + $t + i.rt_thread_self + rt_thread_self + 0x01005fa0: 4801 .H LDR r0,[pc,#4] ; [0x1005fa8] = 0x2002c + 0x01005fa2: 6800 .h LDR r0,[r0,#0] + 0x01005fa4: 4770 pG BX lr + $d + 0x01005fa6: 0000 .. DCW 0 + 0x01005fa8: 0002002c ,... DCD 131116 + $t + i.rt_thread_sleep + rt_thread_sleep + 0x01005fac: b531 1. PUSH {r0,r4,r5,lr} + 0x01005fae: f7fffff7 .... BL rt_thread_self ; 0x1005fa0 + 0x01005fb2: 4604 .F MOV r4,r0 + 0x01005fb4: 2c00 ., CMP r4,#0 + 0x01005fb6: d104 .. BNE 0x1005fc2 ; rt_thread_sleep + 22 + 0x01005fb8: 4a15 .J LDR r2,[pc,#84] ; [0x1006010] = 0x21d + 0x01005fba: 4916 .I LDR r1,[pc,#88] ; [0x1006014] = 0x1007b82 + 0x01005fbc: a016 .. ADR r0,{pc}+0x5c ; 0x1006018 + 0x01005fbe: f7fdfb1f .... BL rt_assert_handler ; 0x1003600 + 0x01005fc2: 4620 F MOV r0,r4 + 0x01005fc4: f7feff52 ..R. BL rt_object_get_type ; 0x1004e6c + 0x01005fc8: 2801 .( CMP r0,#1 + 0x01005fca: d005 .. BEQ 0x1005fd8 ; rt_thread_sleep + 44 + 0x01005fcc: 4a10 .J LDR r2,[pc,#64] ; [0x1006010] = 0x21d + 0x01005fce: 1c52 R. ADDS r2,r2,#1 + 0x01005fd0: 4910 .I LDR r1,[pc,#64] ; [0x1006014] = 0x1007b82 + 0x01005fd2: 4816 .H LDR r0,[pc,#88] ; [0x100602c] = 0x1007f50 + 0x01005fd4: f7fdfb14 .... BL rt_assert_handler ; 0x1003600 + 0x01005fd8: f7fafa72 ..r. BL rt_hw_interrupt_disable ; 0x10004c0 + 0x01005fdc: 4605 .F MOV r5,r0 + 0x01005fde: 4620 F MOV r0,r4 + 0x01005fe0: f000f88a .... BL rt_thread_suspend ; 0x10060f8 + 0x01005fe4: 466a jF MOV r2,sp + 0x01005fe6: 2100 .! MOVS r1,#0 + 0x01005fe8: 4620 F MOV r0,r4 + 0x01005fea: 304c L0 ADDS r0,r0,#0x4c + 0x01005fec: f000fa1c .... BL rt_timer_control ; 0x1006428 + 0x01005ff0: 4620 F MOV r0,r4 + 0x01005ff2: 304c L0 ADDS r0,r0,#0x4c + 0x01005ff4: f000fb1e .... BL rt_timer_start ; 0x1006634 + 0x01005ff8: 4628 (F MOV r0,r5 + 0x01005ffa: f7fafa65 ..e. BL rt_hw_interrupt_enable ; 0x10004c8 + 0x01005ffe: f7fff819 .... BL rt_schedule ; 0x1005034 + 0x01006002: 6b20 k LDR r0,[r4,#0x30] + 0x01006004: 1c80 .. ADDS r0,r0,#2 + 0x01006006: 2800 .( CMP r0,#0 + 0x01006008: d100 .. BNE 0x100600c ; rt_thread_sleep + 96 + 0x0100600a: 6320 c STR r0,[r4,#0x30] + 0x0100600c: 2000 . MOVS r0,#0 + 0x0100600e: bd38 8. POP {r3-r5,pc} + $d + 0x01006010: 0000021d .... DCD 541 + 0x01006014: 01007b82 .{.. DCD 16808834 + 0x01006018: 65726874 thre DCD 1701996660 + 0x0100601c: 21206461 ad ! DCD 555770977 + 0x01006020: 5452203d = RT DCD 1414668349 + 0x01006024: 4c554e5f _NUL DCD 1280659039 + 0x01006028: 0000004c L... DCD 76 + 0x0100602c: 01007f50 P... DCD 16809808 + $t + i.rt_thread_startup + rt_thread_startup + 0x01006030: b510 .. PUSH {r4,lr} + 0x01006032: 4604 .F MOV r4,r0 + 0x01006034: 2c00 ., CMP r4,#0 + 0x01006036: d105 .. BNE 0x1006044 ; rt_thread_startup + 20 + 0x01006038: 22ff ." MOVS r2,#0xff + 0x0100603a: 3242 B2 ADDS r2,r2,#0x42 + 0x0100603c: 4919 .I LDR r1,[pc,#100] ; [0x10060a4] = 0x1007b4e + 0x0100603e: a01a .. ADR r0,{pc}+0x6a ; 0x10060a8 + 0x01006040: f7fdfade .... BL rt_assert_handler ; 0x1003600 + 0x01006044: 2034 4 MOVS r0,#0x34 + 0x01006046: 5d00 .] LDRB r0,[r0,r4] + 0x01006048: 0740 @. LSLS r0,r0,#29 + 0x0100604a: 0f40 @. LSRS r0,r0,#29 + 0x0100604c: 2800 .( CMP r0,#0 + 0x0100604e: d005 .. BEQ 0x100605c ; rt_thread_startup + 44 + 0x01006050: 22ff ." MOVS r2,#0xff + 0x01006052: 3243 C2 ADDS r2,r2,#0x43 + 0x01006054: 4913 .I LDR r1,[pc,#76] ; [0x10060a4] = 0x1007b4e + 0x01006056: a019 .. ADR r0,{pc}+0x66 ; 0x10060bc + 0x01006058: f7fdfad2 .... BL rt_assert_handler ; 0x1003600 + 0x0100605c: 4620 F MOV r0,r4 + 0x0100605e: f7feff05 .... BL rt_object_get_type ; 0x1004e6c + 0x01006062: 2801 .( CMP r0,#1 + 0x01006064: d005 .. BEQ 0x1006072 ; rt_thread_startup + 66 + 0x01006066: 22ff ." MOVS r2,#0xff + 0x01006068: 3244 D2 ADDS r2,r2,#0x44 + 0x0100606a: 490e .I LDR r1,[pc,#56] ; [0x10060a4] = 0x1007b4e + 0x0100606c: 4821 !H LDR r0,[pc,#132] ; [0x10060f4] = 0x1007f50 + 0x0100606e: f7fdfac7 .... BL rt_assert_handler ; 0x1003600 + 0x01006072: 2036 6 MOVS r0,#0x36 + 0x01006074: 5d01 .] LDRB r1,[r0,r4] + 0x01006076: 2035 5 MOVS r0,#0x35 + 0x01006078: 5501 .U STRB r1,[r0,r4] + 0x0100607a: 5d01 .] LDRB r1,[r0,r4] + 0x0100607c: 2001 . MOVS r0,#1 + 0x0100607e: 4088 .@ LSLS r0,r0,r1 + 0x01006080: 63a0 .c STR r0,[r4,#0x38] + 0x01006082: bf00 .. NOP + 0x01006084: bf00 .. NOP + 0x01006086: 2102 .! MOVS r1,#2 + 0x01006088: 2034 4 MOVS r0,#0x34 + 0x0100608a: 5501 .U STRB r1,[r0,r4] + 0x0100608c: 4620 F MOV r0,r4 + 0x0100608e: f7ffff37 ..7. BL rt_thread_resume ; 0x1005f00 + 0x01006092: f7ffff85 .... BL rt_thread_self ; 0x1005fa0 + 0x01006096: 2800 .( CMP r0,#0 + 0x01006098: d001 .. BEQ 0x100609e ; rt_thread_startup + 110 + 0x0100609a: f7feffcb .... BL rt_schedule ; 0x1005034 + 0x0100609e: 2000 . MOVS r0,#0 + 0x010060a0: bd10 .. POP {r4,pc} + $d + 0x010060a2: 0000 .. DCW 0 + 0x010060a4: 01007b4e N{.. DCD 16808782 + 0x010060a8: 65726874 thre DCD 1701996660 + 0x010060ac: 21206461 ad ! DCD 555770977 + 0x010060b0: 5452203d = RT DCD 1414668349 + 0x010060b4: 4c554e5f _NUL DCD 1280659039 + 0x010060b8: 0000004c L... DCD 76 + 0x010060bc: 72687428 (thr DCD 1919448104 + 0x010060c0: 2d646165 ead- DCD 761553253 + 0x010060c4: 6174733e >sta DCD 1635021630 + 0x010060c8: 20262074 t & DCD 539369588 + 0x010060cc: 545f5452 RT_T DCD 1415533650 + 0x010060d0: 41455248 HREA DCD 1095062088 + 0x010060d4: 54535f44 D_ST DCD 1414750020 + 0x010060d8: 4d5f5441 AT_M DCD 1298093121 + 0x010060dc: 294b5341 ASK) DCD 692802369 + 0x010060e0: 203d3d20 == DCD 540884256 + 0x010060e4: 545f5452 RT_T DCD 1415533650 + 0x010060e8: 41455248 HREA DCD 1095062088 + 0x010060ec: 4e495f44 D_IN DCD 1313431364 + 0x010060f0: 00005449 IT.. DCD 21577 + 0x010060f4: 01007f50 P... DCD 16809808 + $t + i.rt_thread_suspend + rt_thread_suspend + 0x010060f8: b570 p. PUSH {r4-r6,lr} + 0x010060fa: 4604 .F MOV r4,r0 + 0x010060fc: 2c00 ., CMP r4,#0 + 0x010060fe: d105 .. BNE 0x100610c ; rt_thread_suspend + 20 + 0x01006100: 22c5 ." MOVS r2,#0xc5 + 0x01006102: 0092 .. LSLS r2,r2,#2 + 0x01006104: 4924 $I LDR r1,[pc,#144] ; [0x1006198] = 0x1007bba + 0x01006106: a025 %. ADR r0,{pc}+0x96 ; 0x100619c + 0x01006108: f7fdfa7a ..z. BL rt_assert_handler ; 0x1003600 + 0x0100610c: 4620 F MOV r0,r4 + 0x0100610e: f7fefead .... BL rt_object_get_type ; 0x1004e6c + 0x01006112: 2801 .( CMP r0,#1 + 0x01006114: d004 .. BEQ 0x1006120 ; rt_thread_suspend + 40 + 0x01006116: 4a26 &J LDR r2,[pc,#152] ; [0x10061b0] = 0x315 + 0x01006118: 491f .I LDR r1,[pc,#124] ; [0x1006198] = 0x1007bba + 0x0100611a: 4826 &H LDR r0,[pc,#152] ; [0x10061b4] = 0x1007f50 + 0x0100611c: f7fdfa70 ..p. BL rt_assert_handler ; 0x1003600 + 0x01006120: bf00 .. NOP + 0x01006122: bf00 .. NOP + 0x01006124: 2034 4 MOVS r0,#0x34 + 0x01006126: 5d00 .] LDRB r0,[r0,r4] + 0x01006128: 0745 E. LSLS r5,r0,#29 + 0x0100612a: 0f6d m. LSRS r5,r5,#29 + 0x0100612c: 2d01 .- CMP r5,#1 + 0x0100612e: d006 .. BEQ 0x100613e ; rt_thread_suspend + 70 + 0x01006130: 2d03 .- CMP r5,#3 + 0x01006132: d004 .. BEQ 0x100613e ; rt_thread_suspend + 70 + 0x01006134: bf00 .. NOP + 0x01006136: bf00 .. NOP + 0x01006138: 2000 . MOVS r0,#0 + 0x0100613a: 43c0 .C MVNS r0,r0 + 0x0100613c: bd70 p. POP {r4-r6,pc} + 0x0100613e: f7faf9bf .... BL rt_hw_interrupt_disable ; 0x10004c0 + 0x01006142: 4606 .F MOV r6,r0 + 0x01006144: 2d03 .- CMP r5,#3 + 0x01006146: d109 .. BNE 0x100615c ; rt_thread_suspend + 100 + 0x01006148: f7ffff2a ..*. BL rt_thread_self ; 0x1005fa0 + 0x0100614c: 42a0 .B CMP r0,r4 + 0x0100614e: d005 .. BEQ 0x100615c ; rt_thread_suspend + 100 + 0x01006150: 4a17 .J LDR r2,[pc,#92] ; [0x10061b0] = 0x315 + 0x01006152: 3211 .2 ADDS r2,r2,#0x11 + 0x01006154: 4910 .I LDR r1,[pc,#64] ; [0x1006198] = 0x1007bba + 0x01006156: a018 .. ADR r0,{pc}+0x62 ; 0x10061b8 + 0x01006158: f7fdfa52 ..R. BL rt_assert_handler ; 0x1003600 + 0x0100615c: 4620 F MOV r0,r4 + 0x0100615e: f7fff86b ..k. BL rt_schedule_remove_thread ; 0x1005238 + 0x01006162: 2034 4 MOVS r0,#0x34 + 0x01006164: 5d00 .] LDRB r0,[r0,r4] + 0x01006166: 08c0 .. LSRS r0,r0,#3 + 0x01006168: 00c0 .. LSLS r0,r0,#3 + 0x0100616a: 2102 .! MOVS r1,#2 + 0x0100616c: 4308 .C ORRS r0,r0,r1 + 0x0100616e: 2134 4! MOVS r1,#0x34 + 0x01006170: 5508 .U STRB r0,[r1,r4] + 0x01006172: 4620 F MOV r0,r4 + 0x01006174: 304c L0 ADDS r0,r0,#0x4c + 0x01006176: f000fb47 ..G. BL rt_timer_stop ; 0x1006808 + 0x0100617a: 4630 0F MOV r0,r6 + 0x0100617c: f7faf9a4 .... BL rt_hw_interrupt_enable ; 0x10004c8 + 0x01006180: bf00 .. NOP + 0x01006182: 4814 .H LDR r0,[pc,#80] ; [0x10061d4] = 0x20128 + 0x01006184: 6800 .h LDR r0,[r0,#0] + 0x01006186: 2800 .( CMP r0,#0 + 0x01006188: d003 .. BEQ 0x1006192 ; rt_thread_suspend + 154 + 0x0100618a: 4620 F MOV r0,r4 + 0x0100618c: 4911 .I LDR r1,[pc,#68] ; [0x10061d4] = 0x20128 + 0x0100618e: 6809 .h LDR r1,[r1,#0] + 0x01006190: 4788 .G BLX r1 + 0x01006192: bf00 .. NOP + 0x01006194: 2000 . MOVS r0,#0 + 0x01006196: e7d1 .. B 0x100613c ; rt_thread_suspend + 68 + $d + 0x01006198: 01007bba .{.. DCD 16808890 + 0x0100619c: 65726874 thre DCD 1701996660 + 0x010061a0: 21206461 ad ! DCD 555770977 + 0x010061a4: 5452203d = RT DCD 1414668349 + 0x010061a8: 4c554e5f _NUL DCD 1280659039 + 0x010061ac: 0000004c L... DCD 76 + 0x010061b0: 00000315 .... DCD 789 + 0x010061b4: 01007f50 P... DCD 16809808 + 0x010061b8: 65726874 thre DCD 1701996660 + 0x010061bc: 3d206461 ad = DCD 1025533025 + 0x010061c0: 7472203d = rt DCD 1953636413 + 0x010061c4: 7268745f _thr DCD 1919448159 + 0x010061c8: 5f646165 ead_ DCD 1600414053 + 0x010061cc: 666c6573 self DCD 1718379891 + 0x010061d0: 00002928 ().. DCD 10536 + 0x010061d4: 00020128 (... DCD 131368 + $t + i.rt_thread_timeout + rt_thread_timeout + 0x010061d8: b570 p. PUSH {r4-r6,lr} + 0x010061da: 4605 .F MOV r5,r0 + 0x010061dc: 462c ,F MOV r4,r5 + 0x010061de: 2c00 ., CMP r4,#0 + 0x010061e0: d104 .. BNE 0x10061ec ; rt_thread_timeout + 20 + 0x010061e2: 4a17 .J LDR r2,[pc,#92] ; [0x1006240] = 0x372 + 0x010061e4: 4917 .I LDR r1,[pc,#92] ; [0x1006244] = 0x1007bdd + 0x010061e6: a018 .. ADR r0,{pc}+0x62 ; 0x1006248 + 0x010061e8: f7fdfa0a .... BL rt_assert_handler ; 0x1003600 + 0x010061ec: 2034 4 MOVS r0,#0x34 + 0x010061ee: 5d00 .] LDRB r0,[r0,r4] + 0x010061f0: 0740 @. LSLS r0,r0,#29 + 0x010061f2: 0f40 @. LSRS r0,r0,#29 + 0x010061f4: 2802 .( CMP r0,#2 + 0x010061f6: d005 .. BEQ 0x1006204 ; rt_thread_timeout + 44 + 0x010061f8: 4a11 .J LDR r2,[pc,#68] ; [0x1006240] = 0x372 + 0x010061fa: 1c52 R. ADDS r2,r2,#1 + 0x010061fc: 4911 .I LDR r1,[pc,#68] ; [0x1006244] = 0x1007bdd + 0x010061fe: a017 .. ADR r0,{pc}+0x5e ; 0x100625c + 0x01006200: f7fdf9fe .... BL rt_assert_handler ; 0x1003600 + 0x01006204: 4620 F MOV r0,r4 + 0x01006206: f7fefe31 ..1. BL rt_object_get_type ; 0x1004e6c + 0x0100620a: 2801 .( CMP r0,#1 + 0x0100620c: d005 .. BEQ 0x100621a ; rt_thread_timeout + 66 + 0x0100620e: 22dd ." MOVS r2,#0xdd + 0x01006210: 0092 .. LSLS r2,r2,#2 + 0x01006212: 490c .I LDR r1,[pc,#48] ; [0x1006244] = 0x1007bdd + 0x01006214: 4820 H LDR r0,[pc,#128] ; [0x1006298] = 0x1007f50 + 0x01006216: f7fdf9f3 .... BL rt_assert_handler ; 0x1003600 + 0x0100621a: f7faf951 ..Q. BL rt_hw_interrupt_disable ; 0x10004c0 + 0x0100621e: 4606 .F MOV r6,r0 + 0x01006220: 2001 . MOVS r0,#1 + 0x01006222: 43c0 .C MVNS r0,r0 + 0x01006224: 6320 c STR r0,[r4,#0x30] + 0x01006226: 4620 F MOV r0,r4 + 0x01006228: 3014 .0 ADDS r0,r0,#0x14 + 0x0100622a: f7fef9d0 .... BL rt_list_remove ; 0x10045ce + 0x0100622e: 4620 F MOV r0,r4 + 0x01006230: f7feffb2 .... BL rt_schedule_insert_thread ; 0x1005198 + 0x01006234: 4630 0F MOV r0,r6 + 0x01006236: f7faf947 ..G. BL rt_hw_interrupt_enable ; 0x10004c8 + 0x0100623a: f7fefefb .... BL rt_schedule ; 0x1005034 + 0x0100623e: bd70 p. POP {r4-r6,pc} + $d + 0x01006240: 00000372 r... DCD 882 + 0x01006244: 01007bdd .{.. DCD 16808925 + 0x01006248: 65726874 thre DCD 1701996660 + 0x0100624c: 21206461 ad ! DCD 555770977 + 0x01006250: 5452203d = RT DCD 1414668349 + 0x01006254: 4c554e5f _NUL DCD 1280659039 + 0x01006258: 0000004c L... DCD 76 + 0x0100625c: 72687428 (thr DCD 1919448104 + 0x01006260: 2d646165 ead- DCD 761553253 + 0x01006264: 6174733e >sta DCD 1635021630 + 0x01006268: 20262074 t & DCD 539369588 + 0x0100626c: 545f5452 RT_T DCD 1415533650 + 0x01006270: 41455248 HREA DCD 1095062088 + 0x01006274: 54535f44 D_ST DCD 1414750020 + 0x01006278: 4d5f5441 AT_M DCD 1298093121 + 0x0100627c: 294b5341 ASK) DCD 692802369 + 0x01006280: 203d3d20 == DCD 540884256 + 0x01006284: 545f5452 RT_T DCD 1415533650 + 0x01006288: 41455248 HREA DCD 1095062088 + 0x0100628c: 55535f44 D_SU DCD 1431527236 + 0x01006290: 4e455053 SPEN DCD 1313165395 + 0x01006294: 00000044 D... DCD 68 + 0x01006298: 01007f50 P... DCD 16809808 + $t + i.rt_tick_from_millisecond + rt_tick_from_millisecond + 0x0100629c: b570 p. PUSH {r4-r6,lr} + 0x0100629e: 4605 .F MOV r5,r0 + 0x010062a0: 2d00 .- CMP r5,#0 + 0x010062a2: da02 .. BGE 0x10062aa ; rt_tick_from_millisecond + 14 + 0x010062a4: 2400 .$ MOVS r4,#0 + 0x010062a6: 43e4 .C MVNS r4,r4 + 0x010062a8: e015 .. B 0x10062d6 ; rt_tick_from_millisecond + 58 + 0x010062aa: 217d }! MOVS r1,#0x7d + 0x010062ac: 00c9 .. LSLS r1,r1,#3 + 0x010062ae: 4628 (F MOV r0,r5 + 0x010062b0: f7fafae6 .... BL __aeabi_idiv ; 0x1000880 + 0x010062b4: 2164 d! MOVS r1,#0x64 + 0x010062b6: 4348 HC MULS r0,r1,r0 + 0x010062b8: 4604 .F MOV r4,r0 + 0x010062ba: 217d }! MOVS r1,#0x7d + 0x010062bc: 00c9 .. LSLS r1,r1,#3 + 0x010062be: 4628 (F MOV r0,r5 + 0x010062c0: f7fafade .... BL __aeabi_idiv ; 0x1000880 + 0x010062c4: 2064 d MOVS r0,#0x64 + 0x010062c6: 4341 AC MULS r1,r0,r1 + 0x010062c8: 4804 .H LDR r0,[pc,#16] ; [0x10062dc] = 0x3e7 + 0x010062ca: 180e .. ADDS r6,r1,r0 + 0x010062cc: 1c41 A. ADDS r1,r0,#1 + 0x010062ce: 4630 0F MOV r0,r6 + 0x010062d0: f7fafad6 .... BL __aeabi_idiv ; 0x1000880 + 0x010062d4: 1904 .. ADDS r4,r0,r4 + 0x010062d6: 4620 F MOV r0,r4 + 0x010062d8: bd70 p. POP {r4-r6,pc} + $d + 0x010062da: 0000 .. DCW 0 + 0x010062dc: 000003e7 .... DCD 999 + $t + i.rt_tick_get + rt_tick_get + 0x010062e0: 4801 .H LDR r0,[pc,#4] ; [0x10062e8] = 0x20044 + 0x010062e2: 6800 .h LDR r0,[r0,#0] + 0x010062e4: 4770 pG BX lr + $d + 0x010062e6: 0000 .. DCW 0 + 0x010062e8: 00020044 D... DCD 131140 + $t + i.rt_tick_increase + rt_tick_increase + 0x010062ec: b570 p. PUSH {r4-r6,lr} + 0x010062ee: f7faf8e7 .... BL rt_hw_interrupt_disable ; 0x10004c0 + 0x010062f2: 4605 .F MOV r5,r0 + 0x010062f4: 4810 .H LDR r0,[pc,#64] ; [0x1006338] = 0x20044 + 0x010062f6: 6800 .h LDR r0,[r0,#0] + 0x010062f8: 1c40 @. ADDS r0,r0,#1 + 0x010062fa: 490f .I LDR r1,[pc,#60] ; [0x1006338] = 0x20044 + 0x010062fc: 6008 .` STR r0,[r1,#0] + 0x010062fe: f7fffe4f ..O. BL rt_thread_self ; 0x1005fa0 + 0x01006302: 4604 .F MOV r4,r0 + 0x01006304: 6ca0 .l LDR r0,[r4,#0x48] + 0x01006306: 1e40 @. SUBS r0,r0,#1 + 0x01006308: 64a0 .d STR r0,[r4,#0x48] + 0x0100630a: 6ca0 .l LDR r0,[r4,#0x48] + 0x0100630c: 2800 .( CMP r0,#0 + 0x0100630e: d10d .. BNE 0x100632c ; rt_tick_increase + 64 + 0x01006310: 6c60 `l LDR r0,[r4,#0x44] + 0x01006312: 64a0 .d STR r0,[r4,#0x48] + 0x01006314: 2034 4 MOVS r0,#0x34 + 0x01006316: 5d00 .] LDRB r0,[r0,r4] + 0x01006318: 2108 .! MOVS r1,#8 + 0x0100631a: 4308 .C ORRS r0,r0,r1 + 0x0100631c: 2134 4! MOVS r1,#0x34 + 0x0100631e: 5508 .U STRB r0,[r1,r4] + 0x01006320: 4628 (F MOV r0,r5 + 0x01006322: f7faf8d1 .... BL rt_hw_interrupt_enable ; 0x10004c8 + 0x01006326: f7fefe85 .... BL rt_schedule ; 0x1005034 + 0x0100632a: e002 .. B 0x1006332 ; rt_tick_increase + 70 + 0x0100632c: 4628 (F MOV r0,r5 + 0x0100632e: f7faf8cb .... BL rt_hw_interrupt_enable ; 0x10004c8 + 0x01006332: f000f803 .... BL rt_timer_check ; 0x100633c + 0x01006336: bd70 p. POP {r4-r6,pc} + $d + 0x01006338: 00020044 D... DCD 131140 + $t + i.rt_timer_check + rt_timer_check + 0x0100633c: b57c |. PUSH {r2-r6,lr} + 0x0100633e: 4668 hF MOV r0,sp + 0x01006340: f7fef8f1 .... BL rt_list_init ; 0x1004526 + 0x01006344: bf00 .. NOP + 0x01006346: bf00 .. NOP + 0x01006348: f7ffffca .... BL rt_tick_get ; 0x10062e0 + 0x0100634c: 4605 .F MOV r5,r0 + 0x0100634e: f7faf8b7 .... BL rt_hw_interrupt_disable ; 0x10004c0 + 0x01006352: 4606 .F MOV r6,r0 + 0x01006354: e053 S. B 0x10063fe ; rt_timer_check + 194 + 0x01006356: 4830 0H LDR r0,[pc,#192] ; [0x1006418] = 0x20054 + 0x01006358: 6800 .h LDR r0,[r0,#0] + 0x0100635a: 4604 .F MOV r4,r0 + 0x0100635c: 3c14 .< SUBS r4,r4,#0x14 + 0x0100635e: 6aa0 .j LDR r0,[r4,#0x28] + 0x01006360: 1a28 (. SUBS r0,r5,r0 + 0x01006362: 492e .I LDR r1,[pc,#184] ; [0x100641c] = 0x7fffffff + 0x01006364: 4288 .B CMP r0,r1 + 0x01006366: d248 H. BCS 0x10063fa ; rt_timer_check + 190 + 0x01006368: bf00 .. NOP + 0x0100636a: 482d -H LDR r0,[pc,#180] ; [0x1006420] = 0x2005c + 0x0100636c: 6800 .h LDR r0,[r0,#0] + 0x0100636e: 2800 .( CMP r0,#0 + 0x01006370: d003 .. BEQ 0x100637a ; rt_timer_check + 62 + 0x01006372: 4620 F MOV r0,r4 + 0x01006374: 492a *I LDR r1,[pc,#168] ; [0x1006420] = 0x2005c + 0x01006376: 6809 .h LDR r1,[r1,#0] + 0x01006378: 4788 .G BLX r1 + 0x0100637a: bf00 .. NOP + 0x0100637c: 4620 F MOV r0,r4 + 0x0100637e: f7fbf9f1 .... BL _timer_remove ; 0x1001764 + 0x01006382: 7a60 `z LDRB r0,[r4,#9] + 0x01006384: 2102 .! MOVS r1,#2 + 0x01006386: 4008 .@ ANDS r0,r0,r1 + 0x01006388: 2800 .( CMP r0,#0 + 0x0100638a: d103 .. BNE 0x1006394 ; rt_timer_check + 88 + 0x0100638c: 7a60 `z LDRB r0,[r4,#9] + 0x0100638e: 0840 @. LSRS r0,r0,#1 + 0x01006390: 0040 @. LSLS r0,r0,#1 + 0x01006392: 7260 `r STRB r0,[r4,#9] + 0x01006394: 4621 !F MOV r1,r4 + 0x01006396: 3114 .1 ADDS r1,r1,#0x14 + 0x01006398: 4668 hF MOV r0,sp + 0x0100639a: f7fef8c7 .... BL rt_list_insert_after ; 0x100452c + 0x0100639e: 69e1 .i LDR r1,[r4,#0x1c] + 0x010063a0: 6a20 j LDR r0,[r4,#0x20] + 0x010063a2: 4788 .G BLX r1 + 0x010063a4: f7ffff9c .... BL rt_tick_get ; 0x10062e0 + 0x010063a8: 4605 .F MOV r5,r0 + 0x010063aa: bf00 .. NOP + 0x010063ac: 481d .H LDR r0,[pc,#116] ; [0x1006424] = 0x20060 + 0x010063ae: 6800 .h LDR r0,[r0,#0] + 0x010063b0: 2800 .( CMP r0,#0 + 0x010063b2: d003 .. BEQ 0x10063bc ; rt_timer_check + 128 + 0x010063b4: 4620 F MOV r0,r4 + 0x010063b6: 491b .I LDR r1,[pc,#108] ; [0x1006424] = 0x20060 + 0x010063b8: 6809 .h LDR r1,[r1,#0] + 0x010063ba: 4788 .G BLX r1 + 0x010063bc: bf00 .. NOP + 0x010063be: bf00 .. NOP + 0x010063c0: bf00 .. NOP + 0x010063c2: 4668 hF MOV r0,sp + 0x010063c4: f7fef8df .... BL rt_list_isempty ; 0x1004586 + 0x010063c8: 2800 .( CMP r0,#0 + 0x010063ca: d000 .. BEQ 0x10063ce ; rt_timer_check + 146 + 0x010063cc: e017 .. B 0x10063fe ; rt_timer_check + 194 + 0x010063ce: 4620 F MOV r0,r4 + 0x010063d0: 3014 .0 ADDS r0,r0,#0x14 + 0x010063d2: f7fef8ea .... BL rt_list_remove ; 0x10045aa + 0x010063d6: 7a60 `z LDRB r0,[r4,#9] + 0x010063d8: 2102 .! MOVS r1,#2 + 0x010063da: 4008 .@ ANDS r0,r0,r1 + 0x010063dc: 2800 .( CMP r0,#0 + 0x010063de: d00d .. BEQ 0x10063fc ; rt_timer_check + 192 + 0x010063e0: 7a60 `z LDRB r0,[r4,#9] + 0x010063e2: 07c0 .. LSLS r0,r0,#31 + 0x010063e4: 0fc0 .. LSRS r0,r0,#31 + 0x010063e6: 2800 .( CMP r0,#0 + 0x010063e8: d008 .. BEQ 0x10063fc ; rt_timer_check + 192 + 0x010063ea: 7a60 `z LDRB r0,[r4,#9] + 0x010063ec: 0840 @. LSRS r0,r0,#1 + 0x010063ee: 0040 @. LSLS r0,r0,#1 + 0x010063f0: 7260 `r STRB r0,[r4,#9] + 0x010063f2: 4620 F MOV r0,r4 + 0x010063f4: f000f91e .... BL rt_timer_start ; 0x1006634 + 0x010063f8: e000 .. B 0x10063fc ; rt_timer_check + 192 + 0x010063fa: e005 .. B 0x1006408 ; rt_timer_check + 204 + 0x010063fc: bf00 .. NOP + 0x010063fe: 4806 .H LDR r0,[pc,#24] ; [0x1006418] = 0x20054 + 0x01006400: f7fef8c1 .... BL rt_list_isempty ; 0x1004586 + 0x01006404: 2800 .( CMP r0,#0 + 0x01006406: d0a6 .. BEQ 0x1006356 ; rt_timer_check + 26 + 0x01006408: bf00 .. NOP + 0x0100640a: 4630 0F MOV r0,r6 + 0x0100640c: f7faf85c ..\. BL rt_hw_interrupt_enable ; 0x10004c8 + 0x01006410: bf00 .. NOP + 0x01006412: bf00 .. NOP + 0x01006414: bd7c |. POP {r2-r6,pc} + $d + 0x01006416: 0000 .. DCW 0 + 0x01006418: 00020054 T... DCD 131156 + 0x0100641c: 7fffffff .... DCD 2147483647 + 0x01006420: 0002005c \... DCD 131164 + 0x01006424: 00020060 `... DCD 131168 + $t + i.rt_timer_control + rt_timer_control + 0x01006428: b5f8 .. PUSH {r3-r7,lr} + 0x0100642a: 4604 .F MOV r4,r0 + 0x0100642c: 460e .F MOV r6,r1 + 0x0100642e: 4615 .F MOV r5,r2 + 0x01006430: 2c00 ., CMP r4,#0 + 0x01006432: d104 .. BNE 0x100643e ; rt_timer_control + 22 + 0x01006434: 4a1d .J LDR r2,[pc,#116] ; [0x10064ac] = 0x219 + 0x01006436: 491e .I LDR r1,[pc,#120] ; [0x10064b0] = 0x1007a3b + 0x01006438: a01e .. ADR r0,{pc}+0x7c ; 0x10064b4 + 0x0100643a: f7fdf8e1 .... BL rt_assert_handler ; 0x1003600 + 0x0100643e: 4620 F MOV r0,r4 + 0x01006440: f7fefd14 .... BL rt_object_get_type ; 0x1004e6c + 0x01006444: 280a .( CMP r0,#0xa + 0x01006446: d005 .. BEQ 0x1006454 ; rt_timer_control + 44 + 0x01006448: 4a18 .J LDR r2,[pc,#96] ; [0x10064ac] = 0x219 + 0x0100644a: 1c52 R. ADDS r2,r2,#1 + 0x0100644c: 4918 .I LDR r1,[pc,#96] ; [0x10064b0] = 0x1007a3b + 0x0100644e: a01e .. ADR r0,{pc}+0x7a ; 0x10064c8 + 0x01006450: f7fdf8d6 .... BL rt_assert_handler ; 0x1003600 + 0x01006454: f7faf834 ..4. BL rt_hw_interrupt_disable ; 0x10004c0 + 0x01006458: 4607 .F MOV r7,r0 + 0x0100645a: 0033 3. MOVS r3,r6 + 0x0100645c: f7fafdba .... BL __ARM_common_switch8 ; 0x1000fd4 + $d + 0x01006460: 0a040705 .... DCD 168036101 + 0x01006464: 001f140f .... DCD 2036751 + $t + 0x01006468: 6a60 `j LDR r0,[r4,#0x24] + 0x0100646a: 6028 (` STR r0,[r5,#0] + 0x0100646c: e018 .. B 0x10064a0 ; rt_timer_control + 120 + 0x0100646e: 6828 (h LDR r0,[r5,#0] + 0x01006470: 6260 `b STR r0,[r4,#0x24] + 0x01006472: e015 .. B 0x10064a0 ; rt_timer_control + 120 + 0x01006474: 7a60 `z LDRB r0,[r4,#9] + 0x01006476: 2102 .! MOVS r1,#2 + 0x01006478: 4388 .C BICS r0,r0,r1 + 0x0100647a: 7260 `r STRB r0,[r4,#9] + 0x0100647c: e010 .. B 0x10064a0 ; rt_timer_control + 120 + 0x0100647e: 7a60 `z LDRB r0,[r4,#9] + 0x01006480: 2102 .! MOVS r1,#2 + 0x01006482: 4308 .C ORRS r0,r0,r1 + 0x01006484: 7260 `r STRB r0,[r4,#9] + 0x01006486: e00b .. B 0x10064a0 ; rt_timer_control + 120 + 0x01006488: 7a60 `z LDRB r0,[r4,#9] + 0x0100648a: 07c0 .. LSLS r0,r0,#31 + 0x0100648c: 0fc0 .. LSRS r0,r0,#31 + 0x0100648e: 2800 .( CMP r0,#0 + 0x01006490: d002 .. BEQ 0x1006498 ; rt_timer_control + 112 + 0x01006492: 2001 . MOVS r0,#1 + 0x01006494: 6028 (` STR r0,[r5,#0] + 0x01006496: e001 .. B 0x100649c ; rt_timer_control + 116 + 0x01006498: 2000 . MOVS r0,#0 + 0x0100649a: 6028 (` STR r0,[r5,#0] + 0x0100649c: e000 .. B 0x10064a0 ; rt_timer_control + 120 + 0x0100649e: bf00 .. NOP + 0x010064a0: bf00 .. NOP + 0x010064a2: 4638 8F MOV r0,r7 + 0x010064a4: f7faf810 .... BL rt_hw_interrupt_enable ; 0x10004c8 + 0x010064a8: 2000 . MOVS r0,#0 + 0x010064aa: bdf8 .. POP {r3-r7,pc} + $d + 0x010064ac: 00000219 .... DCD 537 + 0x010064b0: 01007a3b ;z.. DCD 16808507 + 0x010064b4: 656d6974 time DCD 1701669236 + 0x010064b8: 3d212072 r != DCD 1025581170 + 0x010064bc: 5f545220 RT_ DCD 1599361568 + 0x010064c0: 4c4c554e NULL DCD 1280070990 + 0x010064c4: 00000000 .... DCD 0 + 0x010064c8: 6f5f7472 rt_o DCD 1868526706 + 0x010064cc: 63656a62 bjec DCD 1667590754 + 0x010064d0: 65675f74 t_ge DCD 1701273460 + 0x010064d4: 79745f74 t_ty DCD 2037669748 + 0x010064d8: 26286570 pe(& DCD 640181616 + 0x010064dc: 656d6974 time DCD 1701669236 + 0x010064e0: 703e2d72 r->p DCD 1883123058 + 0x010064e4: 6e657261 aren DCD 1852142177 + 0x010064e8: 3d202974 t) = DCD 1025517940 + 0x010064ec: 5452203d = RT DCD 1414668349 + 0x010064f0: 6a624f5f _Obj DCD 1784827743 + 0x010064f4: 5f746365 ect_ DCD 1601463141 + 0x010064f8: 73616c43 Clas DCD 1935764547 + 0x010064fc: 69545f73 s_Ti DCD 1767137139 + 0x01006500: 0072656d mer. DCD 7497069 + $t + i.rt_timer_detach + rt_timer_detach + 0x01006504: b570 p. PUSH {r4-r6,lr} + 0x01006506: 4604 .F MOV r4,r0 + 0x01006508: 2c00 ., CMP r4,#0 + 0x0100650a: d105 .. BNE 0x1006518 ; rt_timer_detach + 20 + 0x0100650c: 22ff ." MOVS r2,#0xff + 0x0100650e: 320d .2 ADDS r2,r2,#0xd + 0x01006510: 4915 .I LDR r1,[pc,#84] ; [0x1006568] = 0x10079fe + 0x01006512: a016 .. ADR r0,{pc}+0x5a ; 0x100656c + 0x01006514: f7fdf874 ..t. BL rt_assert_handler ; 0x1003600 + 0x01006518: 4620 F MOV r0,r4 + 0x0100651a: f7fefca7 .... BL rt_object_get_type ; 0x1004e6c + 0x0100651e: 280a .( CMP r0,#0xa + 0x01006520: d005 .. BEQ 0x100652e ; rt_timer_detach + 42 + 0x01006522: 22ff ." MOVS r2,#0xff + 0x01006524: 320e .2 ADDS r2,r2,#0xe + 0x01006526: 4910 .I LDR r1,[pc,#64] ; [0x1006568] = 0x10079fe + 0x01006528: a015 .. ADR r0,{pc}+0x58 ; 0x1006580 + 0x0100652a: f7fdf869 ..i. BL rt_assert_handler ; 0x1003600 + 0x0100652e: 4620 F MOV r0,r4 + 0x01006530: f7fefd18 .... BL rt_object_is_systemobject ; 0x1004f64 + 0x01006534: 2800 .( CMP r0,#0 + 0x01006536: d105 .. BNE 0x1006544 ; rt_timer_detach + 64 + 0x01006538: 22ff ." MOVS r2,#0xff + 0x0100653a: 320f .2 ADDS r2,r2,#0xf + 0x0100653c: 490a .I LDR r1,[pc,#40] ; [0x1006568] = 0x10079fe + 0x0100653e: a01f .. ADR r0,{pc}+0x7e ; 0x10065bc + 0x01006540: f7fdf85e ..^. BL rt_assert_handler ; 0x1003600 + 0x01006544: f7f9ffbc .... BL rt_hw_interrupt_disable ; 0x10004c0 + 0x01006548: 4605 .F MOV r5,r0 + 0x0100654a: 4620 F MOV r0,r4 + 0x0100654c: f7fbf90a .... BL _timer_remove ; 0x1001764 + 0x01006550: 7a60 `z LDRB r0,[r4,#9] + 0x01006552: 0840 @. LSRS r0,r0,#1 + 0x01006554: 0040 @. LSLS r0,r0,#1 + 0x01006556: 7260 `r STRB r0,[r4,#9] + 0x01006558: 4628 (F MOV r0,r5 + 0x0100655a: f7f9ffb5 .... BL rt_hw_interrupt_enable ; 0x10004c8 + 0x0100655e: 4620 F MOV r0,r4 + 0x01006560: f7fefba0 .... BL rt_object_detach ; 0x1004ca4 + 0x01006564: 2000 . MOVS r0,#0 + 0x01006566: bd70 p. POP {r4-r6,pc} + $d + 0x01006568: 010079fe .y.. DCD 16808446 + 0x0100656c: 656d6974 time DCD 1701669236 + 0x01006570: 3d212072 r != DCD 1025581170 + 0x01006574: 5f545220 RT_ DCD 1599361568 + 0x01006578: 4c4c554e NULL DCD 1280070990 + 0x0100657c: 00000000 .... DCD 0 + 0x01006580: 6f5f7472 rt_o DCD 1868526706 + 0x01006584: 63656a62 bjec DCD 1667590754 + 0x01006588: 65675f74 t_ge DCD 1701273460 + 0x0100658c: 79745f74 t_ty DCD 2037669748 + 0x01006590: 26286570 pe(& DCD 640181616 + 0x01006594: 656d6974 time DCD 1701669236 + 0x01006598: 703e2d72 r->p DCD 1883123058 + 0x0100659c: 6e657261 aren DCD 1852142177 + 0x010065a0: 3d202974 t) = DCD 1025517940 + 0x010065a4: 5452203d = RT DCD 1414668349 + 0x010065a8: 6a624f5f _Obj DCD 1784827743 + 0x010065ac: 5f746365 ect_ DCD 1601463141 + 0x010065b0: 73616c43 Clas DCD 1935764547 + 0x010065b4: 69545f73 s_Ti DCD 1767137139 + 0x010065b8: 0072656d mer. DCD 7497069 + 0x010065bc: 6f5f7472 rt_o DCD 1868526706 + 0x010065c0: 63656a62 bjec DCD 1667590754 + 0x010065c4: 73695f74 t_is DCD 1936285556 + 0x010065c8: 7379735f _sys DCD 1937339231 + 0x010065cc: 6f6d6574 temo DCD 1869440372 + 0x010065d0: 63656a62 bjec DCD 1667590754 + 0x010065d4: 74262874 t(&t DCD 1948657780 + 0x010065d8: 72656d69 imer DCD 1919249769 + 0x010065dc: 61703e2d ->pa DCD 1634745901 + 0x010065e0: 746e6572 rent DCD 1953391986 + 0x010065e4: 00000029 )... DCD 41 + $t + i.rt_timer_init + rt_timer_init + 0x010065e8: b5f8 .. PUSH {r3-r7,lr} + 0x010065ea: 4604 .F MOV r4,r0 + 0x010065ec: 460d .F MOV r5,r1 + 0x010065ee: 4616 .F MOV r6,r2 + 0x010065f0: 461f .F MOV r7,r3 + 0x010065f2: 2c00 ., CMP r4,#0 + 0x010065f4: d104 .. BNE 0x1006600 ; rt_timer_init + 24 + 0x010065f6: 22f7 ." MOVS r2,#0xf7 + 0x010065f8: 4908 .I LDR r1,[pc,#32] ; [0x100661c] = 0x10079f0 + 0x010065fa: a009 .. ADR r0,{pc}+0x26 ; 0x1006620 + 0x010065fc: f7fdf800 .... BL rt_assert_handler ; 0x1003600 + 0x01006600: 462a *F MOV r2,r5 + 0x01006602: 210a .! MOVS r1,#0xa + 0x01006604: 4620 F MOV r0,r4 + 0x01006606: f7fefc4b ..K. BL rt_object_init ; 0x1004ea0 + 0x0100660a: 9807 .. LDR r0,[sp,#0x1c] + 0x0100660c: 9000 .. STR r0,[sp,#0] + 0x0100660e: 463a :F MOV r2,r7 + 0x01006610: 4631 1F MOV r1,r6 + 0x01006612: 4620 F MOV r0,r4 + 0x01006614: 9b06 .. LDR r3,[sp,#0x18] + 0x01006616: f7fbf887 .... BL _timer_init ; 0x1001728 + 0x0100661a: bdf8 .. POP {r3-r7,pc} + $d + 0x0100661c: 010079f0 .y.. DCD 16808432 + 0x01006620: 656d6974 time DCD 1701669236 + 0x01006624: 3d212072 r != DCD 1025581170 + 0x01006628: 5f545220 RT_ DCD 1599361568 + 0x0100662c: 4c4c554e NULL DCD 1280070990 + 0x01006630: 00000000 .... DCD 0 + $t + i.rt_timer_start + rt_timer_start + 0x01006634: b5fe .. PUSH {r1-r7,lr} + 0x01006636: 4605 .F MOV r5,r0 + 0x01006638: 2d00 .- CMP r5,#0 + 0x0100663a: d105 .. BNE 0x1006648 ; rt_timer_start + 20 + 0x0100663c: 22ff ." MOVS r2,#0xff + 0x0100663e: 3279 y2 ADDS r2,r2,#0x79 + 0x01006640: 494f OI LDR r1,[pc,#316] ; [0x1006780] = 0x1007a1e + 0x01006642: a050 P. ADR r0,{pc}+0x142 ; 0x1006784 + 0x01006644: f7fcffdc .... BL rt_assert_handler ; 0x1003600 + 0x01006648: 4628 (F MOV r0,r5 + 0x0100664a: f7fefc0f .... BL rt_object_get_type ; 0x1004e6c + 0x0100664e: 280a .( CMP r0,#0xa + 0x01006650: d005 .. BEQ 0x100665e ; rt_timer_start + 42 + 0x01006652: 22ff ." MOVS r2,#0xff + 0x01006654: 327a z2 ADDS r2,r2,#0x7a + 0x01006656: 494a JI LDR r1,[pc,#296] ; [0x1006780] = 0x1007a1e + 0x01006658: a04f O. ADR r0,{pc}+0x140 ; 0x1006798 + 0x0100665a: f7fcffd1 .... BL rt_assert_handler ; 0x1003600 + 0x0100665e: 2000 . MOVS r0,#0 + 0x01006660: 9001 .. STR r0,[sp,#4] + 0x01006662: f7f9ff2d ..-. BL rt_hw_interrupt_disable ; 0x10004c0 + 0x01006666: 9002 .. STR r0,[sp,#8] + 0x01006668: 4628 (F MOV r0,r5 + 0x0100666a: f7fbf87b ..{. BL _timer_remove ; 0x1001764 + 0x0100666e: 7a68 hz LDRB r0,[r5,#9] + 0x01006670: 0840 @. LSRS r0,r0,#1 + 0x01006672: 0040 @. LSLS r0,r0,#1 + 0x01006674: 7268 hr STRB r0,[r5,#9] + 0x01006676: bf00 .. NOP + 0x01006678: 4856 VH LDR r0,[pc,#344] ; [0x10067d4] = 0x20114 + 0x0100667a: 6800 .h LDR r0,[r0,#0] + 0x0100667c: 2800 .( CMP r0,#0 + 0x0100667e: d003 .. BEQ 0x1006688 ; rt_timer_start + 84 + 0x01006680: 4628 (F MOV r0,r5 + 0x01006682: 4954 TI LDR r1,[pc,#336] ; [0x10067d4] = 0x20114 + 0x01006684: 6809 .h LDR r1,[r1,#0] + 0x01006686: 4788 .G BLX r1 + 0x01006688: bf00 .. NOP + 0x0100668a: 4953 SI LDR r1,[pc,#332] ; [0x10067d8] = 0x7fffffff + 0x0100668c: 6a68 hj LDR r0,[r5,#0x24] + 0x0100668e: 4288 .B CMP r0,r1 + 0x01006690: d305 .. BCC 0x100669e ; rt_timer_start + 106 + 0x01006692: 22ff ." MOVS r2,#0xff + 0x01006694: 328b .2 ADDS r2,r2,#0x8b + 0x01006696: 493a :I LDR r1,[pc,#232] ; [0x1006780] = 0x1007a1e + 0x01006698: a050 P. ADR r0,{pc}+0x144 ; 0x10067dc + 0x0100669a: f7fcffb1 .... BL rt_assert_handler ; 0x1003600 + 0x0100669e: f7fffe1f .... BL rt_tick_get ; 0x10062e0 + 0x010066a2: 6a69 ij LDR r1,[r5,#0x24] + 0x010066a4: 1840 @. ADDS r0,r0,r1 + 0x010066a6: 62a8 .b STR r0,[r5,#0x28] + 0x010066a8: 4e55 UN LDR r6,[pc,#340] ; [0x1006800] = 0x20054 + 0x010066aa: 9600 .. STR r6,[sp,#0] + 0x010066ac: 2400 .$ MOVS r4,#0 + 0x010066ae: e030 0. B 0x1006712 ; rt_timer_start + 222 + 0x010066b0: e01b .. B 0x10066ea ; rt_timer_start + 182 + 0x010066b2: 00a2 .. LSLS r2,r4,#2 + 0x010066b4: 466b kF MOV r3,sp + 0x010066b6: 589a .X LDR r2,[r3,r2] + 0x010066b8: 6811 .h LDR r1,[r2,#0] + 0x010066ba: 2214 ." MOVS r2,#0x14 + 0x010066bc: 00e3 .. LSLS r3,r4,#3 + 0x010066be: 18d2 .. ADDS r2,r2,r3 + 0x010066c0: 1a88 .. SUBS r0,r1,r2 + 0x010066c2: 6a82 .j LDR r2,[r0,#0x28] + 0x010066c4: 6aab .j LDR r3,[r5,#0x28] + 0x010066c6: 1ad2 .. SUBS r2,r2,r3 + 0x010066c8: d100 .. BNE 0x10066cc ; rt_timer_start + 152 + 0x010066ca: e007 .. B 0x10066dc ; rt_timer_start + 168 + 0x010066cc: 6a82 .j LDR r2,[r0,#0x28] + 0x010066ce: 6aab .j LDR r3,[r5,#0x28] + 0x010066d0: 1ad2 .. SUBS r2,r2,r3 + 0x010066d2: 4b41 AK LDR r3,[pc,#260] ; [0x10067d8] = 0x7fffffff + 0x010066d4: 429a .B CMP r2,r3 + 0x010066d6: d200 .. BCS 0x10066da ; rt_timer_start + 166 + 0x010066d8: e00f .. B 0x10066fa ; rt_timer_start + 198 + 0x010066da: bf00 .. NOP + 0x010066dc: 00a0 .. LSLS r0,r4,#2 + 0x010066de: 4669 iF MOV r1,sp + 0x010066e0: 5808 .X LDR r0,[r1,r0] + 0x010066e2: 6800 .h LDR r0,[r0,#0] + 0x010066e4: 00a1 .. LSLS r1,r4,#2 + 0x010066e6: 466a jF MOV r2,sp + 0x010066e8: 5050 PP STR r0,[r2,r1] + 0x010066ea: 00a0 .. LSLS r0,r4,#2 + 0x010066ec: 4669 iF MOV r1,sp + 0x010066ee: 5808 .X LDR r0,[r1,r0] + 0x010066f0: 00e1 .. LSLS r1,r4,#3 + 0x010066f2: 1989 .. ADDS r1,r1,r6 + 0x010066f4: 6849 Ih LDR r1,[r1,#4] + 0x010066f6: 4288 .B CMP r0,r1 + 0x010066f8: d1db .. BNE 0x10066b2 ; rt_timer_start + 126 + 0x010066fa: bf00 .. NOP + 0x010066fc: 2c00 ., CMP r4,#0 + 0x010066fe: d007 .. BEQ 0x1006710 ; rt_timer_start + 220 + 0x01006700: 00a0 .. LSLS r0,r4,#2 + 0x01006702: 4669 iF MOV r1,sp + 0x01006704: 5808 .X LDR r0,[r1,r0] + 0x01006706: 3008 .0 ADDS r0,r0,#8 + 0x01006708: 1c61 a. ADDS r1,r4,#1 + 0x0100670a: 0089 .. LSLS r1,r1,#2 + 0x0100670c: 466a jF MOV r2,sp + 0x0100670e: 5050 PP STR r0,[r2,r1] + 0x01006710: 1c64 d. ADDS r4,r4,#1 + 0x01006712: 2c00 ., CMP r4,#0 + 0x01006714: d0cc .. BEQ 0x10066b0 ; rt_timer_start + 124 + 0x01006716: 483b ;H LDR r0,[pc,#236] ; [0x1006804] = 0x20064 + 0x01006718: 6800 .h LDR r0,[r0,#0] + 0x0100671a: 1c40 @. ADDS r0,r0,#1 + 0x0100671c: 4939 9I LDR r1,[pc,#228] ; [0x1006804] = 0x20064 + 0x0100671e: 6008 .` STR r0,[r1,#0] + 0x01006720: 4608 .F MOV r0,r1 + 0x01006722: 6807 .h LDR r7,[r0,#0] + 0x01006724: 4629 )F MOV r1,r5 + 0x01006726: 3114 .1 ADDS r1,r1,#0x14 + 0x01006728: 9800 .. LDR r0,[sp,#0] + 0x0100672a: f7fdfeff .... BL rt_list_insert_after ; 0x100452c + 0x0100672e: 2402 .$ MOVS r4,#2 + 0x01006730: e014 .. B 0x100675c ; rt_timer_start + 296 + 0x01006732: 07b8 .. LSLS r0,r7,#30 + 0x01006734: 0f80 .. LSRS r0,r0,#30 + 0x01006736: 2800 .( CMP r0,#0 + 0x01006738: d10d .. BNE 0x1006756 ; rt_timer_start + 290 + 0x0100673a: 2201 ." MOVS r2,#1 + 0x0100673c: 1b12 .. SUBS r2,r2,r4 + 0x0100673e: 00d2 .. LSLS r2,r2,#3 + 0x01006740: 462b +F MOV r3,r5 + 0x01006742: 3314 .3 ADDS r3,r3,#0x14 + 0x01006744: 18d1 .. ADDS r1,r2,r3 + 0x01006746: 2201 ." MOVS r2,#1 + 0x01006748: 1b12 .. SUBS r2,r2,r4 + 0x0100674a: 0092 .. LSLS r2,r2,#2 + 0x0100674c: 466b kF MOV r3,sp + 0x0100674e: 5898 .X LDR r0,[r3,r2] + 0x01006750: f7fdfeec .... BL rt_list_insert_after ; 0x100452c + 0x01006754: e000 .. B 0x1006758 ; rt_timer_start + 292 + 0x01006756: e003 .. B 0x1006760 ; rt_timer_start + 300 + 0x01006758: 08bf .. LSRS r7,r7,#2 + 0x0100675a: 1c64 d. ADDS r4,r4,#1 + 0x0100675c: 2c01 ., CMP r4,#1 + 0x0100675e: d9e8 .. BLS 0x1006732 ; rt_timer_start + 254 + 0x01006760: bf00 .. NOP + 0x01006762: 7a68 hz LDRB r0,[r5,#9] + 0x01006764: 2101 .! MOVS r1,#1 + 0x01006766: 4308 .C ORRS r0,r0,r1 + 0x01006768: 7268 hr STRB r0,[r5,#9] + 0x0100676a: 9802 .. LDR r0,[sp,#8] + 0x0100676c: f7f9feac .... BL rt_hw_interrupt_enable ; 0x10004c8 + 0x01006770: 9801 .. LDR r0,[sp,#4] + 0x01006772: 2800 .( CMP r0,#0 + 0x01006774: d001 .. BEQ 0x100677a ; rt_timer_start + 326 + 0x01006776: f7fefc5d ..]. BL rt_schedule ; 0x1005034 + 0x0100677a: 2000 . MOVS r0,#0 + 0x0100677c: bdfe .. POP {r1-r7,pc} + $d + 0x0100677e: 0000 .. DCW 0 + 0x01006780: 01007a1e .z.. DCD 16808478 + 0x01006784: 656d6974 time DCD 1701669236 + 0x01006788: 3d212072 r != DCD 1025581170 + 0x0100678c: 5f545220 RT_ DCD 1599361568 + 0x01006790: 4c4c554e NULL DCD 1280070990 + 0x01006794: 00000000 .... DCD 0 + 0x01006798: 6f5f7472 rt_o DCD 1868526706 + 0x0100679c: 63656a62 bjec DCD 1667590754 + 0x010067a0: 65675f74 t_ge DCD 1701273460 + 0x010067a4: 79745f74 t_ty DCD 2037669748 + 0x010067a8: 26286570 pe(& DCD 640181616 + 0x010067ac: 656d6974 time DCD 1701669236 + 0x010067b0: 703e2d72 r->p DCD 1883123058 + 0x010067b4: 6e657261 aren DCD 1852142177 + 0x010067b8: 3d202974 t) = DCD 1025517940 + 0x010067bc: 5452203d = RT DCD 1414668349 + 0x010067c0: 6a624f5f _Obj DCD 1784827743 + 0x010067c4: 5f746365 ect_ DCD 1601463141 + 0x010067c8: 73616c43 Clas DCD 1935764547 + 0x010067cc: 69545f73 s_Ti DCD 1767137139 + 0x010067d0: 0072656d mer. DCD 7497069 + 0x010067d4: 00020114 .... DCD 131348 + 0x010067d8: 7fffffff .... DCD 2147483647 + 0x010067dc: 656d6974 time DCD 1701669236 + 0x010067e0: 693e2d72 r->i DCD 1765682546 + 0x010067e4: 5f74696e nit_ DCD 1601464686 + 0x010067e8: 6b636974 tick DCD 1801677172 + 0x010067ec: 52203c20 < R DCD 1377844256 + 0x010067f0: 49545f54 T_TI DCD 1230266196 + 0x010067f4: 4d5f4b43 CK_M DCD 1298090819 + 0x010067f8: 2f205841 AX / DCD 790648897 + 0x010067fc: 00003220 2.. DCD 12832 + 0x01006800: 00020054 T... DCD 131156 + 0x01006804: 00020064 d... DCD 131172 + $t + i.rt_timer_stop + rt_timer_stop + 0x01006808: b570 p. PUSH {r4-r6,lr} + 0x0100680a: 4604 .F MOV r4,r0 + 0x0100680c: 2c00 ., CMP r4,#0 + 0x0100680e: d105 .. BNE 0x100681c ; rt_timer_stop + 20 + 0x01006810: 22ff ." MOVS r2,#0xff + 0x01006812: 32f6 .2 ADDS r2,r2,#0xf6 + 0x01006814: 4917 .I LDR r1,[pc,#92] ; [0x1006874] = 0x1007a2d + 0x01006816: a018 .. ADR r0,{pc}+0x62 ; 0x1006878 + 0x01006818: f7fcfef2 .... BL rt_assert_handler ; 0x1003600 + 0x0100681c: 4620 F MOV r0,r4 + 0x0100681e: f7fefb25 ..%. BL rt_object_get_type ; 0x1004e6c + 0x01006822: 280a .( CMP r0,#0xa + 0x01006824: d005 .. BEQ 0x1006832 ; rt_timer_stop + 42 + 0x01006826: 22ff ." MOVS r2,#0xff + 0x01006828: 32f7 .2 ADDS r2,r2,#0xf7 + 0x0100682a: 4912 .I LDR r1,[pc,#72] ; [0x1006874] = 0x1007a2d + 0x0100682c: a017 .. ADR r0,{pc}+0x60 ; 0x100688c + 0x0100682e: f7fcfee7 .... BL rt_assert_handler ; 0x1003600 + 0x01006832: 7a60 `z LDRB r0,[r4,#9] + 0x01006834: 07c0 .. LSLS r0,r0,#31 + 0x01006836: 0fc0 .. LSRS r0,r0,#31 + 0x01006838: 2800 .( CMP r0,#0 + 0x0100683a: d101 .. BNE 0x1006840 ; rt_timer_stop + 56 + 0x0100683c: 1e40 @. SUBS r0,r0,#1 + 0x0100683e: bd70 p. POP {r4-r6,pc} + 0x01006840: bf00 .. NOP + 0x01006842: 4821 !H LDR r0,[pc,#132] ; [0x10068c8] = 0x20118 + 0x01006844: 6800 .h LDR r0,[r0,#0] + 0x01006846: 2800 .( CMP r0,#0 + 0x01006848: d003 .. BEQ 0x1006852 ; rt_timer_stop + 74 + 0x0100684a: 4620 F MOV r0,r4 + 0x0100684c: 491e .I LDR r1,[pc,#120] ; [0x10068c8] = 0x20118 + 0x0100684e: 6809 .h LDR r1,[r1,#0] + 0x01006850: 4788 .G BLX r1 + 0x01006852: bf00 .. NOP + 0x01006854: f7f9fe34 ..4. BL rt_hw_interrupt_disable ; 0x10004c0 + 0x01006858: 4605 .F MOV r5,r0 + 0x0100685a: 4620 F MOV r0,r4 + 0x0100685c: f7faff82 .... BL _timer_remove ; 0x1001764 + 0x01006860: 7a60 `z LDRB r0,[r4,#9] + 0x01006862: 0840 @. LSRS r0,r0,#1 + 0x01006864: 0040 @. LSLS r0,r0,#1 + 0x01006866: 7260 `r STRB r0,[r4,#9] + 0x01006868: 4628 (F MOV r0,r5 + 0x0100686a: f7f9fe2d ..-. BL rt_hw_interrupt_enable ; 0x10004c8 + 0x0100686e: 2000 . MOVS r0,#0 + 0x01006870: e7e5 .. B 0x100683e ; rt_timer_stop + 54 + $d + 0x01006872: 0000 .. DCW 0 + 0x01006874: 01007a2d -z.. DCD 16808493 + 0x01006878: 656d6974 time DCD 1701669236 + 0x0100687c: 3d212072 r != DCD 1025581170 + 0x01006880: 5f545220 RT_ DCD 1599361568 + 0x01006884: 4c4c554e NULL DCD 1280070990 + 0x01006888: 00000000 .... DCD 0 + 0x0100688c: 6f5f7472 rt_o DCD 1868526706 + 0x01006890: 63656a62 bjec DCD 1667590754 + 0x01006894: 65675f74 t_ge DCD 1701273460 + 0x01006898: 79745f74 t_ty DCD 2037669748 + 0x0100689c: 26286570 pe(& DCD 640181616 + 0x010068a0: 656d6974 time DCD 1701669236 + 0x010068a4: 703e2d72 r->p DCD 1883123058 + 0x010068a8: 6e657261 aren DCD 1852142177 + 0x010068ac: 3d202974 t) = DCD 1025517940 + 0x010068b0: 5452203d = RT DCD 1414668349 + 0x010068b4: 6a624f5f _Obj DCD 1784827743 + 0x010068b8: 5f746365 ect_ DCD 1601463141 + 0x010068bc: 73616c43 Clas DCD 1935764547 + 0x010068c0: 69545f73 s_Ti DCD 1767137139 + 0x010068c4: 0072656d mer. DCD 7497069 + 0x010068c8: 00020118 .... DCD 131352 + $t + i.rt_vsnprintf + rt_vsnprintf + 0x010068cc: b5ff .. PUSH {r0-r7,lr} + 0x010068ce: b08b .. SUB sp,sp,#0x2c + 0x010068d0: 9c0b .. LDR r4,[sp,#0x2c] + 0x010068d2: 9c0b .. LDR r4,[sp,#0x2c] + 0x010068d4: 980c .. LDR r0,[sp,#0x30] + 0x010068d6: 1826 &. ADDS r6,r4,r0 + 0x010068d8: 9c0b .. LDR r4,[sp,#0x2c] + 0x010068da: 42a6 .B CMP r6,r4 + 0x010068dc: d204 .. BCS 0x10068e8 ; rt_vsnprintf + 28 + 0x010068de: 2600 .& MOVS r6,#0 + 0x010068e0: 43f6 .C MVNS r6,r6 + 0x010068e2: 980b .. LDR r0,[sp,#0x2c] + 0x010068e4: 1a30 0. SUBS r0,r6,r0 + 0x010068e6: 900c .. STR r0,[sp,#0x30] + 0x010068e8: e194 .. B 0x1006c14 ; rt_vsnprintf + 840 + 0x010068ea: 980d .. LDR r0,[sp,#0x34] + 0x010068ec: 7800 .x LDRB r0,[r0,#0] + 0x010068ee: 2825 %( CMP r0,#0x25 + 0x010068f0: d006 .. BEQ 0x1006900 ; rt_vsnprintf + 52 + 0x010068f2: 42b4 .B CMP r4,r6 + 0x010068f4: d202 .. BCS 0x10068fc ; rt_vsnprintf + 48 + 0x010068f6: 980d .. LDR r0,[sp,#0x34] + 0x010068f8: 7800 .x LDRB r0,[r0,#0] + 0x010068fa: 7020 p STRB r0,[r4,#0] + 0x010068fc: 1c64 d. ADDS r4,r4,#1 + 0x010068fe: e186 .. B 0x1006c0e ; rt_vsnprintf + 834 + 0x01006900: 2500 .% MOVS r5,#0 + 0x01006902: e026 &. B 0x1006952 ; rt_vsnprintf + 134 + 0x01006904: 980d .. LDR r0,[sp,#0x34] + 0x01006906: 1c40 @. ADDS r0,r0,#1 + 0x01006908: 900d .. STR r0,[sp,#0x34] + 0x0100690a: 980d .. LDR r0,[sp,#0x34] + 0x0100690c: 7800 .x LDRB r0,[r0,#0] + 0x0100690e: 282d -( CMP r0,#0x2d + 0x01006910: d102 .. BNE 0x1006918 ; rt_vsnprintf + 76 + 0x01006912: 2010 . MOVS r0,#0x10 + 0x01006914: 4305 .C ORRS r5,r5,r0 + 0x01006916: e01c .. B 0x1006952 ; rt_vsnprintf + 134 + 0x01006918: 980d .. LDR r0,[sp,#0x34] + 0x0100691a: 7800 .x LDRB r0,[r0,#0] + 0x0100691c: 282b +( CMP r0,#0x2b + 0x0100691e: d102 .. BNE 0x1006926 ; rt_vsnprintf + 90 + 0x01006920: 2004 . MOVS r0,#4 + 0x01006922: 4305 .C ORRS r5,r5,r0 + 0x01006924: e015 .. B 0x1006952 ; rt_vsnprintf + 134 + 0x01006926: 980d .. LDR r0,[sp,#0x34] + 0x01006928: 7800 .x LDRB r0,[r0,#0] + 0x0100692a: 2820 ( CMP r0,#0x20 + 0x0100692c: d102 .. BNE 0x1006934 ; rt_vsnprintf + 104 + 0x0100692e: 2008 . MOVS r0,#8 + 0x01006930: 4305 .C ORRS r5,r5,r0 + 0x01006932: e00e .. B 0x1006952 ; rt_vsnprintf + 134 + 0x01006934: 980d .. LDR r0,[sp,#0x34] + 0x01006936: 7800 .x LDRB r0,[r0,#0] + 0x01006938: 2823 #( CMP r0,#0x23 + 0x0100693a: d102 .. BNE 0x1006942 ; rt_vsnprintf + 118 + 0x0100693c: 2020 MOVS r0,#0x20 + 0x0100693e: 4305 .C ORRS r5,r5,r0 + 0x01006940: e007 .. B 0x1006952 ; rt_vsnprintf + 134 + 0x01006942: 980d .. LDR r0,[sp,#0x34] + 0x01006944: 7800 .x LDRB r0,[r0,#0] + 0x01006946: 2830 0( CMP r0,#0x30 + 0x01006948: d102 .. BNE 0x1006950 ; rt_vsnprintf + 132 + 0x0100694a: 2001 . MOVS r0,#1 + 0x0100694c: 4305 .C ORRS r5,r5,r0 + 0x0100694e: e000 .. B 0x1006952 ; rt_vsnprintf + 134 + 0x01006950: e000 .. B 0x1006954 ; rt_vsnprintf + 136 + 0x01006952: e7d7 .. B 0x1006904 ; rt_vsnprintf + 56 + 0x01006954: bf00 .. NOP + 0x01006956: 2700 .' MOVS r7,#0 + 0x01006958: 43ff .C MVNS r7,r7 + 0x0100695a: 980d .. LDR r0,[sp,#0x34] + 0x0100695c: 7800 .x LDRB r0,[r0,#0] + 0x0100695e: 3830 08 SUBS r0,r0,#0x30 + 0x01006960: 280a .( CMP r0,#0xa + 0x01006962: d204 .. BCS 0x100696e ; rt_vsnprintf + 162 + 0x01006964: a80d .. ADD r0,sp,#0x34 + 0x01006966: f000fa53 ..S. BL skip_atoi ; 0x1006e10 + 0x0100696a: 4607 .F MOV r7,r0 + 0x0100696c: e00e .. B 0x100698c ; rt_vsnprintf + 192 + 0x0100696e: 980d .. LDR r0,[sp,#0x34] + 0x01006970: 7800 .x LDRB r0,[r0,#0] + 0x01006972: 282a *( CMP r0,#0x2a + 0x01006974: d10a .. BNE 0x100698c ; rt_vsnprintf + 192 + 0x01006976: 980d .. LDR r0,[sp,#0x34] + 0x01006978: 1c40 @. ADDS r0,r0,#1 + 0x0100697a: 900d .. STR r0,[sp,#0x34] + 0x0100697c: 980e .. LDR r0,[sp,#0x38] + 0x0100697e: c880 .. LDM r0!,{r7} + 0x01006980: 900e .. STR r0,[sp,#0x38] + 0x01006982: 2f00 ./ CMP r7,#0 + 0x01006984: da02 .. BGE 0x100698c ; rt_vsnprintf + 192 + 0x01006986: 427f .B RSBS r7,r7,#0 + 0x01006988: 2010 . MOVS r0,#0x10 + 0x0100698a: 4305 .C ORRS r5,r5,r0 + 0x0100698c: 2000 . MOVS r0,#0 + 0x0100698e: 43c0 .C MVNS r0,r0 + 0x01006990: 9003 .. STR r0,[sp,#0xc] + 0x01006992: 980d .. LDR r0,[sp,#0x34] + 0x01006994: 7800 .x LDRB r0,[r0,#0] + 0x01006996: 282e .( CMP r0,#0x2e + 0x01006998: d11e .. BNE 0x10069d8 ; rt_vsnprintf + 268 + 0x0100699a: 980d .. LDR r0,[sp,#0x34] + 0x0100699c: 1c40 @. ADDS r0,r0,#1 + 0x0100699e: 900d .. STR r0,[sp,#0x34] + 0x010069a0: 980d .. LDR r0,[sp,#0x34] + 0x010069a2: 7800 .x LDRB r0,[r0,#0] + 0x010069a4: 3830 08 SUBS r0,r0,#0x30 + 0x010069a6: 280a .( CMP r0,#0xa + 0x010069a8: d204 .. BCS 0x10069b4 ; rt_vsnprintf + 232 + 0x010069aa: a80d .. ADD r0,sp,#0x34 + 0x010069ac: f000fa30 ..0. BL skip_atoi ; 0x1006e10 + 0x010069b0: 9003 .. STR r0,[sp,#0xc] + 0x010069b2: e00c .. B 0x10069ce ; rt_vsnprintf + 258 + 0x010069b4: 980d .. LDR r0,[sp,#0x34] + 0x010069b6: 7800 .x LDRB r0,[r0,#0] + 0x010069b8: 282a *( CMP r0,#0x2a + 0x010069ba: d108 .. BNE 0x10069ce ; rt_vsnprintf + 258 + 0x010069bc: 980d .. LDR r0,[sp,#0x34] + 0x010069be: 1c40 @. ADDS r0,r0,#1 + 0x010069c0: 900d .. STR r0,[sp,#0x34] + 0x010069c2: 980e .. LDR r0,[sp,#0x38] + 0x010069c4: 6800 .h LDR r0,[r0,#0] + 0x010069c6: 9003 .. STR r0,[sp,#0xc] + 0x010069c8: 980e .. LDR r0,[sp,#0x38] + 0x010069ca: 1d00 .. ADDS r0,r0,#4 + 0x010069cc: 900e .. STR r0,[sp,#0x38] + 0x010069ce: 9803 .. LDR r0,[sp,#0xc] + 0x010069d0: 2800 .( CMP r0,#0 + 0x010069d2: da01 .. BGE 0x10069d8 ; rt_vsnprintf + 268 + 0x010069d4: 2000 . MOVS r0,#0 + 0x010069d6: 9003 .. STR r0,[sp,#0xc] + 0x010069d8: 2000 . MOVS r0,#0 + 0x010069da: 9004 .. STR r0,[sp,#0x10] + 0x010069dc: 980d .. LDR r0,[sp,#0x34] + 0x010069de: 7800 .x LDRB r0,[r0,#0] + 0x010069e0: 2868 h( CMP r0,#0x68 + 0x010069e2: d003 .. BEQ 0x10069ec ; rt_vsnprintf + 288 + 0x010069e4: 980d .. LDR r0,[sp,#0x34] + 0x010069e6: 7800 .x LDRB r0,[r0,#0] + 0x010069e8: 286c l( CMP r0,#0x6c + 0x010069ea: d105 .. BNE 0x10069f8 ; rt_vsnprintf + 300 + 0x010069ec: 980d .. LDR r0,[sp,#0x34] + 0x010069ee: 7800 .x LDRB r0,[r0,#0] + 0x010069f0: 9004 .. STR r0,[sp,#0x10] + 0x010069f2: 980d .. LDR r0,[sp,#0x34] + 0x010069f4: 1c40 @. ADDS r0,r0,#1 + 0x010069f6: 900d .. STR r0,[sp,#0x34] + 0x010069f8: 200a . MOVS r0,#0xa + 0x010069fa: 9005 .. STR r0,[sp,#0x14] + 0x010069fc: 980d .. LDR r0,[sp,#0x34] + 0x010069fe: 7800 .x LDRB r0,[r0,#0] + 0x01006a00: 286f o( CMP r0,#0x6f + 0x01006a02: d07d }. BEQ 0x1006b00 ; rt_vsnprintf + 564 + 0x01006a04: dc0c .. BGT 0x1006a20 ; rt_vsnprintf + 340 + 0x01006a06: 2863 c( CMP r0,#0x63 + 0x01006a08: d013 .. BEQ 0x1006a32 ; rt_vsnprintf + 358 + 0x01006a0a: dc04 .. BGT 0x1006a16 ; rt_vsnprintf + 330 + 0x01006a0c: 2825 %( CMP r0,#0x25 + 0x01006a0e: d078 x. BEQ 0x1006b02 ; rt_vsnprintf + 566 + 0x01006a10: 2858 X( CMP r0,#0x58 + 0x01006a12: d177 w. BNE 0x1006b04 ; rt_vsnprintf + 568 + 0x01006a14: e0a2 .. B 0x1006b5c ; rt_vsnprintf + 656 + 0x01006a16: 2864 d( CMP r0,#0x64 + 0x01006a18: d075 u. BEQ 0x1006b06 ; rt_vsnprintf + 570 + 0x01006a1a: 2869 i( CMP r0,#0x69 + 0x01006a1c: d1f9 .. BNE 0x1006a12 ; rt_vsnprintf + 326 + 0x01006a1e: e0a4 .. B 0x1006b6a ; rt_vsnprintf + 670 + 0x01006a20: 2870 p( CMP r0,#0x70 + 0x01006a22: d07e ~. BEQ 0x1006b22 ; rt_vsnprintf + 598 + 0x01006a24: 2873 s( CMP r0,#0x73 + 0x01006a26: d026 &. BEQ 0x1006a76 ; rt_vsnprintf + 426 + 0x01006a28: 2875 u( CMP r0,#0x75 + 0x01006a2a: d06e n. BEQ 0x1006b0a ; rt_vsnprintf + 574 + 0x01006a2c: 2878 x( CMP r0,#0x78 + 0x01006a2e: d1f0 .. BNE 0x1006a12 ; rt_vsnprintf + 326 + 0x01006a30: e097 .. B 0x1006b62 ; rt_vsnprintf + 662 + 0x01006a32: 2010 . MOVS r0,#0x10 + 0x01006a34: 4028 (@ ANDS r0,r0,r5 + 0x01006a36: 2800 .( CMP r0,#0 + 0x01006a38: d108 .. BNE 0x1006a4c ; rt_vsnprintf + 384 + 0x01006a3a: e004 .. B 0x1006a46 ; rt_vsnprintf + 378 + 0x01006a3c: 42b4 .B CMP r4,r6 + 0x01006a3e: d201 .. BCS 0x1006a44 ; rt_vsnprintf + 376 + 0x01006a40: 2020 MOVS r0,#0x20 + 0x01006a42: 7020 p STRB r0,[r4,#0] + 0x01006a44: 1c64 d. ADDS r4,r4,#1 + 0x01006a46: 1e78 x. SUBS r0,r7,#1 + 0x01006a48: 1e07 .. SUBS r7,r0,#0 + 0x01006a4a: dcf7 .. BGT 0x1006a3c ; rt_vsnprintf + 368 + 0x01006a4c: 980e .. LDR r0,[sp,#0x38] + 0x01006a4e: 7801 .x LDRB r1,[r0,#0] + 0x01006a50: 1d00 .. ADDS r0,r0,#4 + 0x01006a52: 900e .. STR r0,[sp,#0x38] + 0x01006a54: b2c8 .. UXTB r0,r1 + 0x01006a56: 9007 .. STR r0,[sp,#0x1c] + 0x01006a58: 42b4 .B CMP r4,r6 + 0x01006a5a: d201 .. BCS 0x1006a60 ; rt_vsnprintf + 404 + 0x01006a5c: 9807 .. LDR r0,[sp,#0x1c] + 0x01006a5e: 7020 p STRB r0,[r4,#0] + 0x01006a60: 1c64 d. ADDS r4,r4,#1 + 0x01006a62: e004 .. B 0x1006a6e ; rt_vsnprintf + 418 + 0x01006a64: 42b4 .B CMP r4,r6 + 0x01006a66: d201 .. BCS 0x1006a6c ; rt_vsnprintf + 416 + 0x01006a68: 2020 MOVS r0,#0x20 + 0x01006a6a: 7020 p STRB r0,[r4,#0] + 0x01006a6c: 1c64 d. ADDS r4,r4,#1 + 0x01006a6e: 1e78 x. SUBS r0,r7,#1 + 0x01006a70: 1e07 .. SUBS r7,r0,#0 + 0x01006a72: dcf7 .. BGT 0x1006a64 ; rt_vsnprintf + 408 + 0x01006a74: e0cb .. B 0x1006c0e ; rt_vsnprintf + 834 + 0x01006a76: 980e .. LDR r0,[sp,#0x38] + 0x01006a78: 6800 .h LDR r0,[r0,#0] + 0x01006a7a: 9006 .. STR r0,[sp,#0x18] + 0x01006a7c: 980e .. LDR r0,[sp,#0x38] + 0x01006a7e: 1d00 .. ADDS r0,r0,#4 + 0x01006a80: 900e .. STR r0,[sp,#0x38] + 0x01006a82: 9806 .. LDR r0,[sp,#0x18] + 0x01006a84: 2800 .( CMP r0,#0 + 0x01006a86: d101 .. BNE 0x1006a8c ; rt_vsnprintf + 448 + 0x01006a88: a06d m. ADR r0,{pc}+0x1b8 ; 0x1006c40 + 0x01006a8a: 9006 .. STR r0,[sp,#0x18] + 0x01006a8c: 2000 . MOVS r0,#0 + 0x01006a8e: 9008 .. STR r0,[sp,#0x20] + 0x01006a90: e002 .. B 0x1006a98 ; rt_vsnprintf + 460 + 0x01006a92: 9808 .. LDR r0,[sp,#0x20] + 0x01006a94: 1c40 @. ADDS r0,r0,#1 + 0x01006a96: 9008 .. STR r0,[sp,#0x20] + 0x01006a98: 9808 .. LDR r0,[sp,#0x20] + 0x01006a9a: 42b8 .B CMP r0,r7 + 0x01006a9c: d004 .. BEQ 0x1006aa8 ; rt_vsnprintf + 476 + 0x01006a9e: 9908 .. LDR r1,[sp,#0x20] + 0x01006aa0: 9806 .. LDR r0,[sp,#0x18] + 0x01006aa2: 5c40 @\ LDRB r0,[r0,r1] + 0x01006aa4: 2800 .( CMP r0,#0 + 0x01006aa6: d1f4 .. BNE 0x1006a92 ; rt_vsnprintf + 454 + 0x01006aa8: 9803 .. LDR r0,[sp,#0xc] + 0x01006aaa: 2800 .( CMP r0,#0 + 0x01006aac: dd05 .. BLE 0x1006aba ; rt_vsnprintf + 494 + 0x01006aae: 9903 .. LDR r1,[sp,#0xc] + 0x01006ab0: 9808 .. LDR r0,[sp,#0x20] + 0x01006ab2: 4288 .B CMP r0,r1 + 0x01006ab4: dd01 .. BLE 0x1006aba ; rt_vsnprintf + 494 + 0x01006ab6: 9803 .. LDR r0,[sp,#0xc] + 0x01006ab8: 9008 .. STR r0,[sp,#0x20] + 0x01006aba: 2010 . MOVS r0,#0x10 + 0x01006abc: 4028 (@ ANDS r0,r0,r5 + 0x01006abe: 2800 .( CMP r0,#0 + 0x01006ac0: d10a .. BNE 0x1006ad8 ; rt_vsnprintf + 524 + 0x01006ac2: e004 .. B 0x1006ace ; rt_vsnprintf + 514 + 0x01006ac4: 42b4 .B CMP r4,r6 + 0x01006ac6: d201 .. BCS 0x1006acc ; rt_vsnprintf + 512 + 0x01006ac8: 2020 MOVS r0,#0x20 + 0x01006aca: 7020 p STRB r0,[r4,#0] + 0x01006acc: 1c64 d. ADDS r4,r4,#1 + 0x01006ace: 4638 8F MOV r0,r7 + 0x01006ad0: 1e7f .. SUBS r7,r7,#1 + 0x01006ad2: 9908 .. LDR r1,[sp,#0x20] + 0x01006ad4: 4288 .B CMP r0,r1 + 0x01006ad6: dcf5 .. BGT 0x1006ac4 ; rt_vsnprintf + 504 + 0x01006ad8: 2000 . MOVS r0,#0 + 0x01006ada: 9009 .. STR r0,[sp,#0x24] + 0x01006adc: e00b .. B 0x1006af6 ; rt_vsnprintf + 554 + 0x01006ade: 42b4 .B CMP r4,r6 + 0x01006ae0: d202 .. BCS 0x1006ae8 ; rt_vsnprintf + 540 + 0x01006ae2: 9806 .. LDR r0,[sp,#0x18] + 0x01006ae4: 7800 .x LDRB r0,[r0,#0] + 0x01006ae6: 7020 p STRB r0,[r4,#0] + 0x01006ae8: 1c64 d. ADDS r4,r4,#1 + 0x01006aea: 9806 .. LDR r0,[sp,#0x18] + 0x01006aec: 1c40 @. ADDS r0,r0,#1 + 0x01006aee: 9006 .. STR r0,[sp,#0x18] + 0x01006af0: 9809 .. LDR r0,[sp,#0x24] + 0x01006af2: 1c40 @. ADDS r0,r0,#1 + 0x01006af4: 9009 .. STR r0,[sp,#0x24] + 0x01006af6: 9908 .. LDR r1,[sp,#0x20] + 0x01006af8: 9809 .. LDR r0,[sp,#0x24] + 0x01006afa: 4288 .B CMP r0,r1 + 0x01006afc: dbef .. BLT 0x1006ade ; rt_vsnprintf + 530 + 0x01006afe: e00a .. B 0x1006b16 ; rt_vsnprintf + 586 + 0x01006b00: e029 ). B 0x1006b56 ; rt_vsnprintf + 650 + 0x01006b02: e022 ". B 0x1006b4a ; rt_vsnprintf + 638 + 0x01006b04: e035 5. B 0x1006b72 ; rt_vsnprintf + 678 + 0x01006b06: e02f /. B 0x1006b68 ; rt_vsnprintf + 668 + 0x01006b08: e00b .. B 0x1006b22 ; rt_vsnprintf + 598 + 0x01006b0a: e031 1. B 0x1006b70 ; rt_vsnprintf + 676 + 0x01006b0c: 42b4 .B CMP r4,r6 + 0x01006b0e: d201 .. BCS 0x1006b14 ; rt_vsnprintf + 584 + 0x01006b10: 2020 MOVS r0,#0x20 + 0x01006b12: 7020 p STRB r0,[r4,#0] + 0x01006b14: 1c64 d. ADDS r4,r4,#1 + 0x01006b16: 4638 8F MOV r0,r7 + 0x01006b18: 1e7f .. SUBS r7,r7,#1 + 0x01006b1a: 9908 .. LDR r1,[sp,#0x20] + 0x01006b1c: 4288 .B CMP r0,r1 + 0x01006b1e: dcf5 .. BGT 0x1006b0c ; rt_vsnprintf + 576 + 0x01006b20: e075 u. B 0x1006c0e ; rt_vsnprintf + 834 + 0x01006b22: 1c78 x. ADDS r0,r7,#1 + 0x01006b24: 2800 .( CMP r0,#0 + 0x01006b26: d102 .. BNE 0x1006b2e ; rt_vsnprintf + 610 + 0x01006b28: 2708 .' MOVS r7,#8 + 0x01006b2a: 2001 . MOVS r0,#1 + 0x01006b2c: 4305 .C ORRS r5,r5,r0 + 0x01006b2e: 9803 .. LDR r0,[sp,#0xc] + 0x01006b30: 9700 .. STR r7,[sp,#0] + 0x01006b32: 9502 .. STR r5,[sp,#8] + 0x01006b34: 9001 .. STR r0,[sp,#4] + 0x01006b36: 980e .. LDR r0,[sp,#0x38] + 0x01006b38: c804 .. LDM r0!,{r2} + 0x01006b3a: 2310 .# MOVS r3,#0x10 + 0x01006b3c: 4631 1F MOV r1,r6 + 0x01006b3e: 900e .. STR r0,[sp,#0x38] + 0x01006b40: 4620 F MOV r0,r4 + 0x01006b42: f7fcfc6b ..k. BL print_number ; 0x100341c + 0x01006b46: 4604 .F MOV r4,r0 + 0x01006b48: e061 a. B 0x1006c0e ; rt_vsnprintf + 834 + 0x01006b4a: 42b4 .B CMP r4,r6 + 0x01006b4c: d201 .. BCS 0x1006b52 ; rt_vsnprintf + 646 + 0x01006b4e: 2025 % MOVS r0,#0x25 + 0x01006b50: 7020 p STRB r0,[r4,#0] + 0x01006b52: 1c64 d. ADDS r4,r4,#1 + 0x01006b54: e05b [. B 0x1006c0e ; rt_vsnprintf + 834 + 0x01006b56: 2008 . MOVS r0,#8 + 0x01006b58: 9005 .. STR r0,[sp,#0x14] + 0x01006b5a: e01e .. B 0x1006b9a ; rt_vsnprintf + 718 + 0x01006b5c: 2040 @ MOVS r0,#0x40 + 0x01006b5e: 4305 .C ORRS r5,r5,r0 + 0x01006b60: bf00 .. NOP + 0x01006b62: 2010 . MOVS r0,#0x10 + 0x01006b64: 9005 .. STR r0,[sp,#0x14] + 0x01006b66: e018 .. B 0x1006b9a ; rt_vsnprintf + 718 + 0x01006b68: bf00 .. NOP + 0x01006b6a: 2002 . MOVS r0,#2 + 0x01006b6c: 4305 .C ORRS r5,r5,r0 + 0x01006b6e: bf00 .. NOP + 0x01006b70: e013 .. B 0x1006b9a ; rt_vsnprintf + 718 + 0x01006b72: 42b4 .B CMP r4,r6 + 0x01006b74: d201 .. BCS 0x1006b7a ; rt_vsnprintf + 686 + 0x01006b76: 2025 % MOVS r0,#0x25 + 0x01006b78: 7020 p STRB r0,[r4,#0] + 0x01006b7a: 1c64 d. ADDS r4,r4,#1 + 0x01006b7c: 980d .. LDR r0,[sp,#0x34] + 0x01006b7e: 7800 .x LDRB r0,[r0,#0] + 0x01006b80: 2800 .( CMP r0,#0 + 0x01006b82: d006 .. BEQ 0x1006b92 ; rt_vsnprintf + 710 + 0x01006b84: 42b4 .B CMP r4,r6 + 0x01006b86: d202 .. BCS 0x1006b8e ; rt_vsnprintf + 706 + 0x01006b88: 980d .. LDR r0,[sp,#0x34] + 0x01006b8a: 7800 .x LDRB r0,[r0,#0] + 0x01006b8c: 7020 p STRB r0,[r4,#0] + 0x01006b8e: 1c64 d. ADDS r4,r4,#1 + 0x01006b90: e002 .. B 0x1006b98 ; rt_vsnprintf + 716 + 0x01006b92: 980d .. LDR r0,[sp,#0x34] + 0x01006b94: 1e40 @. SUBS r0,r0,#1 + 0x01006b96: 900d .. STR r0,[sp,#0x34] + 0x01006b98: e039 9. B 0x1006c0e ; rt_vsnprintf + 834 + 0x01006b9a: bf00 .. NOP + 0x01006b9c: 9804 .. LDR r0,[sp,#0x10] + 0x01006b9e: 286c l( CMP r0,#0x6c + 0x01006ba0: d10c .. BNE 0x1006bbc ; rt_vsnprintf + 752 + 0x01006ba2: 980e .. LDR r0,[sp,#0x38] + 0x01006ba4: 6800 .h LDR r0,[r0,#0] + 0x01006ba6: 900a .. STR r0,[sp,#0x28] + 0x01006ba8: 980e .. LDR r0,[sp,#0x38] + 0x01006baa: 1d00 .. ADDS r0,r0,#4 + 0x01006bac: 900e .. STR r0,[sp,#0x38] + 0x01006bae: 2002 . MOVS r0,#2 + 0x01006bb0: 4028 (@ ANDS r0,r0,r5 + 0x01006bb2: 2800 .( CMP r0,#0 + 0x01006bb4: d01f .. BEQ 0x1006bf6 ; rt_vsnprintf + 810 + 0x01006bb6: 980a .. LDR r0,[sp,#0x28] + 0x01006bb8: 900a .. STR r0,[sp,#0x28] + 0x01006bba: e01c .. B 0x1006bf6 ; rt_vsnprintf + 810 + 0x01006bbc: 9804 .. LDR r0,[sp,#0x10] + 0x01006bbe: 2868 h( CMP r0,#0x68 + 0x01006bc0: d10d .. BNE 0x1006bde ; rt_vsnprintf + 786 + 0x01006bc2: 980e .. LDR r0,[sp,#0x38] + 0x01006bc4: 8801 .. LDRH r1,[r0,#0] + 0x01006bc6: 1d00 .. ADDS r0,r0,#4 + 0x01006bc8: 900e .. STR r0,[sp,#0x38] + 0x01006bca: b288 .. UXTH r0,r1 + 0x01006bcc: 900a .. STR r0,[sp,#0x28] + 0x01006bce: 2002 . MOVS r0,#2 + 0x01006bd0: 4028 (@ ANDS r0,r0,r5 + 0x01006bd2: 2800 .( CMP r0,#0 + 0x01006bd4: d00f .. BEQ 0x1006bf6 ; rt_vsnprintf + 810 + 0x01006bd6: 980a .. LDR r0,[sp,#0x28] + 0x01006bd8: b200 .. SXTH r0,r0 + 0x01006bda: 900a .. STR r0,[sp,#0x28] + 0x01006bdc: e00b .. B 0x1006bf6 ; rt_vsnprintf + 810 + 0x01006bde: 980e .. LDR r0,[sp,#0x38] + 0x01006be0: 6800 .h LDR r0,[r0,#0] + 0x01006be2: 900a .. STR r0,[sp,#0x28] + 0x01006be4: 980e .. LDR r0,[sp,#0x38] + 0x01006be6: 1d00 .. ADDS r0,r0,#4 + 0x01006be8: 900e .. STR r0,[sp,#0x38] + 0x01006bea: 2002 . MOVS r0,#2 + 0x01006bec: 4028 (@ ANDS r0,r0,r5 + 0x01006bee: 2800 .( CMP r0,#0 + 0x01006bf0: d001 .. BEQ 0x1006bf6 ; rt_vsnprintf + 810 + 0x01006bf2: 980a .. LDR r0,[sp,#0x28] + 0x01006bf4: 900a .. STR r0,[sp,#0x28] + 0x01006bf6: 9803 .. LDR r0,[sp,#0xc] + 0x01006bf8: 9700 .. STR r7,[sp,#0] + 0x01006bfa: 9502 .. STR r5,[sp,#8] + 0x01006bfc: 9001 .. STR r0,[sp,#4] + 0x01006bfe: 4631 1F MOV r1,r6 + 0x01006c00: 4620 F MOV r0,r4 + 0x01006c02: 9b05 .. LDR r3,[sp,#0x14] + 0x01006c04: 9a0a .. LDR r2,[sp,#0x28] + 0x01006c06: f7fcfc09 .... BL print_number ; 0x100341c + 0x01006c0a: 4604 .F MOV r4,r0 + 0x01006c0c: bf00 .. NOP + 0x01006c0e: 980d .. LDR r0,[sp,#0x34] + 0x01006c10: 1c40 @. ADDS r0,r0,#1 + 0x01006c12: 900d .. STR r0,[sp,#0x34] + 0x01006c14: 980d .. LDR r0,[sp,#0x34] + 0x01006c16: 7800 .x LDRB r0,[r0,#0] + 0x01006c18: 2800 .( CMP r0,#0 + 0x01006c1a: d000 .. BEQ 0x1006c1e ; rt_vsnprintf + 850 + 0x01006c1c: e665 e. B 0x10068ea ; rt_vsnprintf + 30 + 0x01006c1e: 980c .. LDR r0,[sp,#0x30] + 0x01006c20: 2800 .( CMP r0,#0 + 0x01006c22: d008 .. BEQ 0x1006c36 ; rt_vsnprintf + 874 + 0x01006c24: 42b4 .B CMP r4,r6 + 0x01006c26: d202 .. BCS 0x1006c2e ; rt_vsnprintf + 866 + 0x01006c28: 2000 . MOVS r0,#0 + 0x01006c2a: 7020 p STRB r0,[r4,#0] + 0x01006c2c: e003 .. B 0x1006c36 ; rt_vsnprintf + 874 + 0x01006c2e: 2100 .! MOVS r1,#0 + 0x01006c30: 4630 0F MOV r0,r6 + 0x01006c32: 3820 8 SUBS r0,r0,#0x20 + 0x01006c34: 77c1 .w STRB r1,[r0,#0x1f] + 0x01006c36: 980b .. LDR r0,[sp,#0x2c] + 0x01006c38: 1a20 . SUBS r0,r4,r0 + 0x01006c3a: b00f .. ADD sp,sp,#0x3c + 0x01006c3c: bdf0 .. POP {r4-r7,pc} + $d + 0x01006c3e: 0000 .. DCW 0 + 0x01006c40: 4c554e28 (NUL DCD 1280658984 + 0x01006c44: 0000294c L).. DCD 10572 + $t + i.rt_vsprintf + rt_vsprintf + 0x01006c48: b537 7. PUSH {r0-r2,r4,r5,lr} + 0x01006c4a: 4605 .F MOV r5,r0 + 0x01006c4c: 460c .F MOV r4,r1 + 0x01006c4e: 4622 "F MOV r2,r4 + 0x01006c50: 2100 .! MOVS r1,#0 + 0x01006c52: 43c9 .C MVNS r1,r1 + 0x01006c54: 4628 (F MOV r0,r5 + 0x01006c56: 9b02 .. LDR r3,[sp,#8] + 0x01006c58: f7fffe38 ..8. BL rt_vsnprintf ; 0x10068cc + 0x01006c5c: bd3e >. POP {r1-r5,pc} + i.rti_board_end + rti_board_end + 0x01006c5e: 2000 . MOVS r0,#0 + 0x01006c60: 4770 pG BX lr + i.rti_board_start + rti_board_start + 0x01006c62: 2000 . MOVS r0,#0 + 0x01006c64: 4770 pG BX lr + i.rti_end + rti_end + 0x01006c66: 2000 . MOVS r0,#0 + 0x01006c68: 4770 pG BX lr + i.rti_start + rti_start + 0x01006c6a: 2000 . MOVS r0,#0 + 0x01006c6c: 4770 pG BX lr + i.rtthread_startup + rtthread_startup + 0x01006c6e: b510 .. PUSH {r4,lr} + 0x01006c70: f7f9fc26 ..&. BL rt_hw_interrupt_disable ; 0x10004c0 + 0x01006c74: f7fdfa38 ..8. BL rt_hw_board_init ; 0x10040e8 + 0x01006c78: f7fefee0 .... BL rt_show_version ; 0x1005a3c + 0x01006c7c: f7fff852 ..R. BL rt_system_timer_init ; 0x1005d24 + 0x01006c80: f7fff820 .. . BL rt_system_scheduler_init ; 0x1005cc4 + 0x01006c84: f7fcfc94 .... BL rt_application_init ; 0x10035b0 + 0x01006c88: f7fff85a ..Z. BL rt_system_timer_thread_init ; 0x1005d40 + 0x01006c8c: f7fff8bc .... BL rt_thread_idle_init ; 0x1005e08 + 0x01006c90: f7fff834 ..4. BL rt_system_scheduler_start ; 0x1005cfc + 0x01006c94: 2000 . MOVS r0,#0 + 0x01006c96: bd10 .. POP {r4,pc} + i.shell_auto_complete + shell_auto_complete + 0x01006c98: b570 p. PUSH {r4-r6,lr} + 0x01006c9a: 4604 .F MOV r4,r0 + 0x01006c9c: a007 .. ADR r0,{pc}+0x20 ; 0x1006cbc + 0x01006c9e: f7fdfc17 .... BL rt_kprintf ; 0x10044d0 + 0x01006ca2: 4620 F MOV r0,r4 + 0x01006ca4: f7fcf9d4 .... BL msh_auto_complete ; 0x1003050 + 0x01006ca8: f7fafd8a .... BL finsh_get_prompt ; 0x10017c0 + 0x01006cac: 4605 .F MOV r5,r0 + 0x01006cae: 4622 "F MOV r2,r4 + 0x01006cb0: 4629 )F MOV r1,r5 + 0x01006cb2: a003 .. ADR r0,{pc}+0xe ; 0x1006cc0 + 0x01006cb4: f7fdfc0c .... BL rt_kprintf ; 0x10044d0 + 0x01006cb8: bd70 p. POP {r4-r6,pc} + $d + 0x01006cba: 0000 .. DCW 0 + 0x01006cbc: 0000000a .... DCD 10 + 0x01006cc0: 73257325 %s%s DCD 1931834149 + 0x01006cc4: 00000000 .... DCD 0 + $t + i.shell_handle_history + shell_handle_history + 0x01006cc8: b570 p. PUSH {r4-r6,lr} + 0x01006cca: 4604 .F MOV r4,r0 + 0x01006ccc: a007 .. ADR r0,{pc}+0x20 ; 0x1006cec + 0x01006cce: f7fdfbff .... BL rt_kprintf ; 0x10044d0 + 0x01006cd2: f7fafd75 ..u. BL finsh_get_prompt ; 0x10017c0 + 0x01006cd6: 4605 .F MOV r5,r0 + 0x01006cd8: 4622 "F MOV r2,r4 + 0x01006cda: 32ff .2 ADDS r2,r2,#0xff + 0x01006cdc: 32b7 .2 ADDS r2,r2,#0xb7 + 0x01006cde: 4629 )F MOV r1,r5 + 0x01006ce0: a004 .. ADR r0,{pc}+0x14 ; 0x1006cf4 + 0x01006ce2: f7fdfbf5 .... BL rt_kprintf ; 0x10044d0 + 0x01006ce6: 2000 . MOVS r0,#0 + 0x01006ce8: bd70 p. POP {r4-r6,pc} + $d + 0x01006cea: 0000 .. DCW 0 + 0x01006cec: 4b325b1b .[2K DCD 1261591323 + 0x01006cf0: 0000000d .... DCD 13 + 0x01006cf4: 73257325 %s%s DCD 1931834149 + 0x01006cf8: 00000000 .... DCD 0 + $t + i.shell_push_history + shell_push_history + 0x01006cfc: b570 p. PUSH {r4-r6,lr} + 0x01006cfe: 4604 .F MOV r4,r0 + 0x01006d00: 2041 A MOVS r0,#0x41 + 0x01006d02: 00c0 .. LSLS r0,r0,#3 + 0x01006d04: 5b00 .[ LDRH r0,[r0,r4] + 0x01006d06: 2800 .( CMP r0,#0 + 0x01006d08: d063 c. BEQ 0x1006dd2 ; shell_push_history + 214 + 0x01006d0a: 8ca0 .. LDRH r0,[r4,#0x24] + 0x01006d0c: 2805 .( CMP r0,#5 + 0x01006d0e: db32 2. BLT 0x1006d76 ; shell_push_history + 122 + 0x01006d10: 2250 P" MOVS r2,#0x50 + 0x01006d12: 4621 !F MOV r1,r4 + 0x01006d14: 31ff .1 ADDS r1,r1,#0xff + 0x01006d16: 31b7 .1 ADDS r1,r1,#0xb7 + 0x01006d18: 4608 .F MOV r0,r1 + 0x01006d1a: 3850 P8 SUBS r0,r0,#0x50 + 0x01006d1c: f7f9fc3c ..<. BL memcmp ; 0x1000598 + 0x01006d20: 2800 .( CMP r0,#0 + 0x01006d22: d056 V. BEQ 0x1006dd2 ; shell_push_history + 214 + 0x01006d24: 2500 .% MOVS r5,#0 + 0x01006d26: e00c .. B 0x1006d42 ; shell_push_history + 70 + 0x01006d28: 1c6a j. ADDS r2,r5,#1 + 0x01006d2a: 2350 P# MOVS r3,#0x50 + 0x01006d2c: 435a ZC MULS r2,r3,r2 + 0x01006d2e: 4623 #F MOV r3,r4 + 0x01006d30: 3326 &3 ADDS r3,r3,#0x26 + 0x01006d32: 18d1 .. ADDS r1,r2,r3 + 0x01006d34: 2250 P" MOVS r2,#0x50 + 0x01006d36: 436a jC MULS r2,r5,r2 + 0x01006d38: 18d0 .. ADDS r0,r2,r3 + 0x01006d3a: 2250 P" MOVS r2,#0x50 + 0x01006d3c: f7f9fcfe .... BL __aeabi_memcpy ; 0x100073c + 0x01006d40: 1c6d m. ADDS r5,r5,#1 + 0x01006d42: 2d04 .- CMP r5,#4 + 0x01006d44: dbf0 .. BLT 0x1006d28 ; shell_push_history + 44 + 0x01006d46: 2150 P! MOVS r1,#0x50 + 0x01006d48: 4369 iC MULS r1,r5,r1 + 0x01006d4a: 4622 "F MOV r2,r4 + 0x01006d4c: 3226 &2 ADDS r2,r2,#0x26 + 0x01006d4e: 1888 .. ADDS r0,r1,r2 + 0x01006d50: 2150 P! MOVS r1,#0x50 + 0x01006d52: f7f9fd50 ..P. BL __aeabi_memclr ; 0x10007f6 + 0x01006d56: 2141 A! MOVS r1,#0x41 + 0x01006d58: 00c9 .. LSLS r1,r1,#3 + 0x01006d5a: 5b0a .[ LDRH r2,[r1,r4] + 0x01006d5c: 2150 P! MOVS r1,#0x50 + 0x01006d5e: 4369 iC MULS r1,r5,r1 + 0x01006d60: 4623 #F MOV r3,r4 + 0x01006d62: 3326 &3 ADDS r3,r3,#0x26 + 0x01006d64: 18c8 .. ADDS r0,r1,r3 + 0x01006d66: 4621 !F MOV r1,r4 + 0x01006d68: 31ff .1 ADDS r1,r1,#0xff + 0x01006d6a: 31b7 .1 ADDS r1,r1,#0xb7 + 0x01006d6c: f7f9fce6 .... BL __aeabi_memcpy ; 0x100073c + 0x01006d70: 2005 . MOVS r0,#5 + 0x01006d72: 84a0 .. STRH r0,[r4,#0x24] + 0x01006d74: e02d -. B 0x1006dd2 ; shell_push_history + 214 + 0x01006d76: 8ca0 .. LDRH r0,[r4,#0x24] + 0x01006d78: 2800 .( CMP r0,#0 + 0x01006d7a: d00e .. BEQ 0x1006d9a ; shell_push_history + 158 + 0x01006d7c: 8ca1 .. LDRH r1,[r4,#0x24] + 0x01006d7e: 1e49 I. SUBS r1,r1,#1 + 0x01006d80: 2250 P" MOVS r2,#0x50 + 0x01006d82: 4351 QC MULS r1,r2,r1 + 0x01006d84: 4622 "F MOV r2,r4 + 0x01006d86: 3226 &2 ADDS r2,r2,#0x26 + 0x01006d88: 1888 .. ADDS r0,r1,r2 + 0x01006d8a: 2250 P" MOVS r2,#0x50 + 0x01006d8c: 4621 !F MOV r1,r4 + 0x01006d8e: 31ff .1 ADDS r1,r1,#0xff + 0x01006d90: 31b7 .1 ADDS r1,r1,#0xb7 + 0x01006d92: f7f9fc01 .... BL memcmp ; 0x1000598 + 0x01006d96: 2800 .( CMP r0,#0 + 0x01006d98: d01b .. BEQ 0x1006dd2 ; shell_push_history + 214 + 0x01006d9a: 8ca0 .. LDRH r0,[r4,#0x24] + 0x01006d9c: 8460 `. STRH r0,[r4,#0x22] + 0x01006d9e: 8ca1 .. LDRH r1,[r4,#0x24] + 0x01006da0: 2250 P" MOVS r2,#0x50 + 0x01006da2: 4351 QC MULS r1,r2,r1 + 0x01006da4: 4622 "F MOV r2,r4 + 0x01006da6: 3226 &2 ADDS r2,r2,#0x26 + 0x01006da8: 1888 .. ADDS r0,r1,r2 + 0x01006daa: 2150 P! MOVS r1,#0x50 + 0x01006dac: f7f9fd23 ..#. BL __aeabi_memclr ; 0x10007f6 + 0x01006db0: 2141 A! MOVS r1,#0x41 + 0x01006db2: 00c9 .. LSLS r1,r1,#3 + 0x01006db4: 5b0a .[ LDRH r2,[r1,r4] + 0x01006db6: 8ca1 .. LDRH r1,[r4,#0x24] + 0x01006db8: 2350 P# MOVS r3,#0x50 + 0x01006dba: 4359 YC MULS r1,r3,r1 + 0x01006dbc: 4623 #F MOV r3,r4 + 0x01006dbe: 3326 &3 ADDS r3,r3,#0x26 + 0x01006dc0: 18c8 .. ADDS r0,r1,r3 + 0x01006dc2: 4621 !F MOV r1,r4 + 0x01006dc4: 31ff .1 ADDS r1,r1,#0xff + 0x01006dc6: 31b7 .1 ADDS r1,r1,#0xb7 + 0x01006dc8: f7f9fcb8 .... BL __aeabi_memcpy ; 0x100073c + 0x01006dcc: 8ca0 .. LDRH r0,[r4,#0x24] + 0x01006dce: 1c40 @. ADDS r0,r0,#1 + 0x01006dd0: 84a0 .. STRH r0,[r4,#0x24] + 0x01006dd2: 8ca0 .. LDRH r0,[r4,#0x24] + 0x01006dd4: 8460 `. STRH r0,[r4,#0x22] + 0x01006dd6: bd70 p. POP {r4-r6,pc} + i.show_wait_queue + show_wait_queue + 0x01006dd8: b570 p. PUSH {r4-r6,lr} + 0x01006dda: 4604 .F MOV r4,r0 + 0x01006ddc: 6825 %h LDR r5,[r4,#0] + 0x01006dde: e00d .. B 0x1006dfc ; show_wait_queue + 36 + 0x01006de0: 462e .F MOV r6,r5 + 0x01006de2: 3e14 .> SUBS r6,r6,#0x14 + 0x01006de4: 4632 2F MOV r2,r6 + 0x01006de6: 2108 .! MOVS r1,#8 + 0x01006de8: a006 .. ADR r0,{pc}+0x1c ; 0x1006e04 + 0x01006dea: f7fdfb71 ..q. BL rt_kprintf ; 0x10044d0 + 0x01006dee: 6828 (h LDR r0,[r5,#0] + 0x01006df0: 42a0 .B CMP r0,r4 + 0x01006df2: d002 .. BEQ 0x1006dfa ; show_wait_queue + 34 + 0x01006df4: a005 .. ADR r0,{pc}+0x18 ; 0x1006e0c + 0x01006df6: f7fdfb6b ..k. BL rt_kprintf ; 0x10044d0 + 0x01006dfa: 682d -h LDR r5,[r5,#0] + 0x01006dfc: 42a5 .B CMP r5,r4 + 0x01006dfe: d1ef .. BNE 0x1006de0 ; show_wait_queue + 8 + 0x01006e00: bd70 p. POP {r4-r6,pc} + $d + 0x01006e02: 0000 .. DCW 0 + 0x01006e04: 732a2e25 %.*s DCD 1932144165 + 0x01006e08: 00000000 .... DCD 0 + 0x01006e0c: 0000002f /... DCD 47 + $t + i.skip_atoi + skip_atoi + 0x01006e10: 4601 .F MOV r1,r0 + 0x01006e12: 2000 . MOVS r0,#0 + 0x01006e14: e008 .. B 0x1006e28 ; skip_atoi + 24 + 0x01006e16: 680b .h LDR r3,[r1,#0] + 0x01006e18: 1c5a Z. ADDS r2,r3,#1 + 0x01006e1a: 600a .` STR r2,[r1,#0] + 0x01006e1c: 781b .x LDRB r3,[r3,#0] + 0x01006e1e: 220a ." MOVS r2,#0xa + 0x01006e20: 4342 BC MULS r2,r0,r2 + 0x01006e22: 189a .. ADDS r2,r3,r2 + 0x01006e24: 4610 .F MOV r0,r2 + 0x01006e26: 3830 08 SUBS r0,r0,#0x30 + 0x01006e28: 680a .h LDR r2,[r1,#0] + 0x01006e2a: 7812 .x LDRB r2,[r2,#0] + 0x01006e2c: 3a30 0: SUBS r2,r2,#0x30 + 0x01006e2e: 2a0a .* CMP r2,#0xa + 0x01006e30: d3f1 .. BCC 0x1006e16 ; skip_atoi + 6 + 0x01006e32: 4770 pG BX lr + i.str_common + str_common + 0x01006e34: b510 .. PUSH {r4,lr} + 0x01006e36: 4603 .F MOV r3,r0 + 0x01006e38: 461a .F MOV r2,r3 + 0x01006e3a: e001 .. B 0x1006e40 ; str_common + 12 + 0x01006e3c: 1c52 R. ADDS r2,r2,#1 + 0x01006e3e: 1c49 I. ADDS r1,r1,#1 + 0x01006e40: 7810 .x LDRB r0,[r2,#0] + 0x01006e42: 2800 .( CMP r0,#0 + 0x01006e44: d006 .. BEQ 0x1006e54 ; str_common + 32 + 0x01006e46: 7808 .x LDRB r0,[r1,#0] + 0x01006e48: 2800 .( CMP r0,#0 + 0x01006e4a: d003 .. BEQ 0x1006e54 ; str_common + 32 + 0x01006e4c: 7810 .x LDRB r0,[r2,#0] + 0x01006e4e: 780c .x LDRB r4,[r1,#0] + 0x01006e50: 42a0 .B CMP r0,r4 + 0x01006e52: d0f3 .. BEQ 0x1006e3c ; str_common + 8 + 0x01006e54: 1ad0 .. SUBS r0,r2,r3 + 0x01006e56: bd10 .. POP {r4,pc} + i.version + version + 0x01006e58: b510 .. PUSH {r4,lr} + 0x01006e5a: f7fefdef .... BL rt_show_version ; 0x1005a3c + 0x01006e5e: 2000 . MOVS r0,#0 + 0x01006e60: bd10 .. POP {r4,pc} + 0x01006e62: 0000 .. MOVS r0,r0 + i.yc3121_uart_configure + yc3121_uart_configure + 0x01006e64: b57f .. PUSH {r0-r6,lr} + 0x01006e66: 4605 .F MOV r5,r0 + 0x01006e68: 460c .F MOV r4,r1 + 0x01006e6a: 2d00 .- CMP r5,#0 + 0x01006e6c: d104 .. BNE 0x1006e78 ; yc3121_uart_configure + 20 + 0x01006e6e: 221a ." MOVS r2,#0x1a + 0x01006e70: 4926 &I LDR r1,[pc,#152] ; [0x1006f0c] = 0x1007434 + 0x01006e72: a027 '. ADR r0,{pc}+0x9e ; 0x1006f10 + 0x01006e74: f7fcfbc4 .... BL rt_assert_handler ; 0x1003600 + 0x01006e78: 2c00 ., CMP r4,#0 + 0x01006e7a: d104 .. BNE 0x1006e86 ; yc3121_uart_configure + 34 + 0x01006e7c: 221b ." MOVS r2,#0x1b + 0x01006e7e: 4923 #I LDR r1,[pc,#140] ; [0x1006f0c] = 0x1007434 + 0x01006e80: a028 (. ADR r0,{pc}+0xa4 ; 0x1006f24 + 0x01006e82: f7fcfbbd .... BL rt_assert_handler ; 0x1003600 + 0x01006e86: 6bee .k LDR r6,[r5,#0x3c] + 0x01006e88: 2001 . MOVS r0,#1 + 0x01006e8a: 5630 0V LDRSB r0,[r6,r0] + 0x01006e8c: f7f9fe02 .... BL NVIC_DisableIRQ ; 0x1000a94 + 0x01006e90: 6820 h LDR r0,[r4,#0] + 0x01006e92: 9001 .. STR r0,[sp,#4] + 0x01006e94: 2100 .! MOVS r1,#0 + 0x01006e96: 4668 hF MOV r0,sp + 0x01006e98: 72c1 .r STRB r1,[r0,#0xb] + 0x01006e9a: 7001 .p STRB r1,[r0,#0] + 0x01006e9c: 7920 y LDRB r0,[r4,#4] + 0x01006e9e: 0700 .. LSLS r0,r0,#28 + 0x01006ea0: 0f00 .. LSRS r0,r0,#28 + 0x01006ea2: 2809 .( CMP r0,#9 + 0x01006ea4: d103 .. BNE 0x1006eae ; yc3121_uart_configure + 74 + 0x01006ea6: 2004 . MOVS r0,#4 + 0x01006ea8: 4669 iF MOV r1,sp + 0x01006eaa: 7208 .r STRB r0,[r1,#8] + 0x01006eac: e003 .. B 0x1006eb6 ; yc3121_uart_configure + 82 + 0x01006eae: 2000 . MOVS r0,#0 + 0x01006eb0: 4669 iF MOV r1,sp + 0x01006eb2: 7208 .r STRB r0,[r1,#8] + 0x01006eb4: bf00 .. NOP + 0x01006eb6: bf00 .. NOP + 0x01006eb8: 7920 y LDRB r0,[r4,#4] + 0x01006eba: 0680 .. LSLS r0,r0,#26 + 0x01006ebc: 0f80 .. LSRS r0,r0,#30 + 0x01006ebe: 2801 .( CMP r0,#1 + 0x01006ec0: d103 .. BNE 0x1006eca ; yc3121_uart_configure + 102 + 0x01006ec2: 2008 . MOVS r0,#8 + 0x01006ec4: 4669 iF MOV r1,sp + 0x01006ec6: 7248 Hr STRB r0,[r1,#9] + 0x01006ec8: e003 .. B 0x1006ed2 ; yc3121_uart_configure + 110 + 0x01006eca: 2000 . MOVS r0,#0 + 0x01006ecc: 4669 iF MOV r1,sp + 0x01006ece: 7248 Hr STRB r0,[r1,#9] + 0x01006ed0: bf00 .. NOP + 0x01006ed2: bf00 .. NOP + 0x01006ed4: 7920 y LDRB r0,[r4,#4] + 0x01006ed6: 0600 .. LSLS r0,r0,#24 + 0x01006ed8: 0f80 .. LSRS r0,r0,#30 + 0x01006eda: 2801 .( CMP r0,#1 + 0x01006edc: d002 .. BEQ 0x1006ee4 ; yc3121_uart_configure + 128 + 0x01006ede: 2802 .( CMP r0,#2 + 0x01006ee0: d108 .. BNE 0x1006ef4 ; yc3121_uart_configure + 144 + 0x01006ee2: e003 .. B 0x1006eec ; yc3121_uart_configure + 136 + 0x01006ee4: 2002 . MOVS r0,#2 + 0x01006ee6: 4669 iF MOV r1,sp + 0x01006ee8: 7288 .r STRB r0,[r1,#0xa] + 0x01006eea: e007 .. B 0x1006efc ; yc3121_uart_configure + 152 + 0x01006eec: 2000 . MOVS r0,#0 + 0x01006eee: 4669 iF MOV r1,sp + 0x01006ef0: 7288 .r STRB r0,[r1,#0xa] + 0x01006ef2: e003 .. B 0x1006efc ; yc3121_uart_configure + 152 + 0x01006ef4: 2000 . MOVS r0,#0 + 0x01006ef6: 4669 iF MOV r1,sp + 0x01006ef8: 7288 .r STRB r0,[r1,#0xa] + 0x01006efa: bf00 .. NOP + 0x01006efc: bf00 .. NOP + 0x01006efe: 7830 0x LDRB r0,[r6,#0] + 0x01006f00: 4669 iF MOV r1,sp + 0x01006f02: f7f9fecf .... BL UART_Init ; 0x1000ca4 + 0x01006f06: 2000 . MOVS r0,#0 + 0x01006f08: b004 .. ADD sp,sp,#0x10 + 0x01006f0a: bd70 p. POP {r4-r6,pc} + $d + 0x01006f0c: 01007434 4t.. DCD 16806964 + 0x01006f10: 69726573 seri DCD 1769104755 + 0x01006f14: 21206c61 al ! DCD 555773025 + 0x01006f18: 5452203d = RT DCD 1414668349 + 0x01006f1c: 4c554e5f _NUL DCD 1280659039 + 0x01006f20: 0000004c L... DCD 76 + 0x01006f24: 20676663 cfg DCD 543647331 + 0x01006f28: 52203d21 != R DCD 1377844513 + 0x01006f2c: 554e5f54 T_NU DCD 1431199572 + 0x01006f30: 00004c4c LL.. DCD 19532 + $t + i.yc3121_uart_control + yc3121_uart_control + 0x01006f34: b5f8 .. PUSH {r3-r7,lr} + 0x01006f36: 4605 .F MOV r5,r0 + 0x01006f38: 460e .F MOV r6,r1 + 0x01006f3a: 4617 .F MOV r7,r2 + 0x01006f3c: 2d00 .- CMP r5,#0 + 0x01006f3e: d104 .. BNE 0x1006f4a ; yc3121_uart_control + 22 + 0x01006f40: 2248 H" MOVS r2,#0x48 + 0x01006f42: 4911 .I LDR r1,[pc,#68] ; [0x1006f88] = 0x100744a + 0x01006f44: a011 .. ADR r0,{pc}+0x48 ; 0x1006f8c + 0x01006f46: f7fcfb5b ..[. BL rt_assert_handler ; 0x1003600 + 0x01006f4a: 6bec .k LDR r4,[r5,#0x3c] + 0x01006f4c: 2e10 .. CMP r6,#0x10 + 0x01006f4e: d00a .. BEQ 0x1006f66 ; yc3121_uart_control + 50 + 0x01006f50: 2e11 .. CMP r6,#0x11 + 0x01006f52: d116 .. BNE 0x1006f82 ; yc3121_uart_control + 78 + 0x01006f54: 7820 x LDRB r0,[r4,#0] + 0x01006f56: 2100 .! MOVS r1,#0 + 0x01006f58: f7faf804 .... BL UART_SetRxITNum ; 0x1000f64 + 0x01006f5c: 2001 . MOVS r0,#1 + 0x01006f5e: 5620 V LDRSB r0,[r4,r0] + 0x01006f60: f7f9fd98 .... BL NVIC_DisableIRQ ; 0x1000a94 + 0x01006f64: e00d .. B 0x1006f82 ; yc3121_uart_control + 78 + 0x01006f66: 7820 x LDRB r0,[r4,#0] + 0x01006f68: 2101 .! MOVS r1,#1 + 0x01006f6a: f7f9fffb .... BL UART_SetRxITNum ; 0x1000f64 + 0x01006f6e: 7820 x LDRB r0,[r4,#0] + 0x01006f70: 2201 ." MOVS r2,#1 + 0x01006f72: 2102 .! MOVS r1,#2 + 0x01006f74: f7f9fe22 ..". BL UART_ITConfig ; 0x1000bbc + 0x01006f78: 2001 . MOVS r0,#1 + 0x01006f7a: 5620 V LDRSB r0,[r4,r0] + 0x01006f7c: f7f9fd94 .... BL NVIC_EnableIRQ ; 0x1000aa8 + 0x01006f80: bf00 .. NOP + 0x01006f82: bf00 .. NOP + 0x01006f84: 2000 . MOVS r0,#0 + 0x01006f86: bdf8 .. POP {r3-r7,pc} + $d + 0x01006f88: 0100744a Jt.. DCD 16806986 + 0x01006f8c: 69726573 seri DCD 1769104755 + 0x01006f90: 21206c61 al ! DCD 555773025 + 0x01006f94: 5452203d = RT DCD 1414668349 + 0x01006f98: 4c554e5f _NUL DCD 1280659039 + 0x01006f9c: 0000004c L... DCD 76 + $t + i.yc3121_uart_getc + yc3121_uart_getc + 0x01006fa0: b570 p. PUSH {r4-r6,lr} + 0x01006fa2: 4604 .F MOV r4,r0 + 0x01006fa4: 2c00 ., CMP r4,#0 + 0x01006fa6: d104 .. BNE 0x1006fb2 ; yc3121_uart_getc + 18 + 0x01006fa8: 2269 i" MOVS r2,#0x69 + 0x01006faa: 4909 .I LDR r1,[pc,#36] ; [0x1006fd0] = 0x100746f + 0x01006fac: a009 .. ADR r0,{pc}+0x28 ; 0x1006fd4 + 0x01006fae: f7fcfb27 ..'. BL rt_assert_handler ; 0x1003600 + 0x01006fb2: 6be5 .k LDR r5,[r4,#0x3c] + 0x01006fb4: 2600 .& MOVS r6,#0 + 0x01006fb6: 43f6 .C MVNS r6,r6 + 0x01006fb8: 7828 (x LDRB r0,[r5,#0] + 0x01006fba: f7f9ff79 ..y. BL UART_ReceiveDataLen ; 0x1000eb0 + 0x01006fbe: 2800 .( CMP r0,#0 + 0x01006fc0: d003 .. BEQ 0x1006fca ; yc3121_uart_getc + 42 + 0x01006fc2: 7828 (x LDRB r0,[r5,#0] + 0x01006fc4: f7f9ff4e ..N. BL UART_ReceiveData ; 0x1000e64 + 0x01006fc8: 4606 .F MOV r6,r0 + 0x01006fca: 4630 0F MOV r0,r6 + 0x01006fcc: bd70 p. POP {r4-r6,pc} + $d + 0x01006fce: 0000 .. DCW 0 + 0x01006fd0: 0100746f ot.. DCD 16807023 + 0x01006fd4: 69726573 seri DCD 1769104755 + 0x01006fd8: 21206c61 al ! DCD 555773025 + 0x01006fdc: 5452203d = RT DCD 1414668349 + 0x01006fe0: 4c554e5f _NUL DCD 1280659039 + 0x01006fe4: 0000004c L... DCD 76 + $t + i.yc3121_uart_putc + yc3121_uart_putc + 0x01006fe8: b570 p. PUSH {r4-r6,lr} + 0x01006fea: 4604 .F MOV r4,r0 + 0x01006fec: 460e .F MOV r6,r1 + 0x01006fee: 2c00 ., CMP r4,#0 + 0x01006ff0: d104 .. BNE 0x1006ffc ; yc3121_uart_putc + 20 + 0x01006ff2: 225e ^" MOVS r2,#0x5e + 0x01006ff4: 4908 .I LDR r1,[pc,#32] ; [0x1007018] = 0x100745e + 0x01006ff6: a009 .. ADR r0,{pc}+0x26 ; 0x100701c + 0x01006ff8: f7fcfb02 .... BL rt_assert_handler ; 0x1003600 + 0x01006ffc: 6be5 .k LDR r5,[r4,#0x3c] + 0x01006ffe: bf00 .. NOP + 0x01007000: 7828 (x LDRB r0,[r5,#0] + 0x01007002: f7f9ff01 .... BL UART_IsUARTBusy ; 0x1000e08 + 0x01007006: 2800 .( CMP r0,#0 + 0x01007008: d1fa .. BNE 0x1007000 ; yc3121_uart_putc + 24 + 0x0100700a: 7828 (x LDRB r0,[r5,#0] + 0x0100700c: 4631 1F MOV r1,r6 + 0x0100700e: f7f9ff77 ..w. BL UART_SendData ; 0x1000f00 + 0x01007012: 2001 . MOVS r0,#1 + 0x01007014: bd70 p. POP {r4-r6,pc} + $d + 0x01007016: 0000 .. DCW 0 + 0x01007018: 0100745e ^t.. DCD 16807006 + 0x0100701c: 69726573 seri DCD 1769104755 + 0x01007020: 21206c61 al ! DCD 555773025 + 0x01007024: 5452203d = RT DCD 1414668349 + 0x01007028: 4c554e5f _NUL DCD 1280659039 + 0x0100702c: 0000004c L... DCD 76 + $t + i.yc_pin_attach_irq + yc_pin_attach_irq + 0x01007030: b5f8 .. PUSH {r3-r7,lr} + 0x01007032: 4615 .F MOV r5,r2 + 0x01007034: 461e .F MOV r6,r3 + 0x01007036: 9f06 .. LDR r7,[sp,#0x18] + 0x01007038: 2c00 ., CMP r4,#0 + 0x0100703a: d101 .. BNE 0x1007040 ; yc_pin_attach_irq + 16 + 0x0100703c: 200a . MOVS r0,#0xa + 0x0100703e: bdf8 .. POP {r3-r7,pc} + 0x01007040: f7f9fa3e ..>. BL rt_hw_interrupt_disable ; 0x10004c0 + 0x01007044: 9000 .. STR r0,[sp,#0] + 0x01007046: 6126 &a STR r6,[r4,#0x10] + 0x01007048: 6167 ga STR r7,[r4,#0x14] + 0x0100704a: 60e5 .` STR r5,[r4,#0xc] + 0x0100704c: 9800 .. LDR r0,[sp,#0] + 0x0100704e: f7f9fa3b ..;. BL rt_hw_interrupt_enable ; 0x10004c8 + 0x01007052: 2000 . MOVS r0,#0 + 0x01007054: e7f3 .. B 0x100703e ; yc_pin_attach_irq + 14 + i.yc_pin_detach_irq + yc_pin_detach_irq + 0x01007056: b5e0 .. PUSH {r5-r7,lr} + 0x01007058: 4606 .F MOV r6,r0 + 0x0100705a: 460f .F MOV r7,r1 + 0x0100705c: 2c00 ., CMP r4,#0 + 0x0100705e: d101 .. BNE 0x1007064 ; yc_pin_detach_irq + 14 + 0x01007060: 200a . MOVS r0,#0xa + 0x01007062: bde0 .. POP {r5-r7,pc} + 0x01007064: f7f9fa2c ..,. BL rt_hw_interrupt_disable ; 0x10004c0 + 0x01007068: 4605 .F MOV r5,r0 + 0x0100706a: 2000 . MOVS r0,#0 + 0x0100706c: 6120 a STR r0,[r4,#0x10] + 0x0100706e: 6160 `a STR r0,[r4,#0x14] + 0x01007070: 60e0 .` STR r0,[r4,#0xc] + 0x01007072: 4628 (F MOV r0,r5 + 0x01007074: f7f9fa28 ..(. BL rt_hw_interrupt_enable ; 0x10004c8 + 0x01007078: 2000 . MOVS r0,#0 + 0x0100707a: e7f2 .. B 0x1007062 ; yc_pin_detach_irq + 12 + i.yc_pin_irq_enable + yc_pin_irq_enable + 0x0100707c: b5f8 .. PUSH {r3-r7,lr} + 0x0100707e: 460c .F MOV r4,r1 + 0x01007080: 4616 .F MOV r6,r2 + 0x01007082: 2000 . MOVS r0,#0 + 0x01007084: 9000 .. STR r0,[sp,#0] + 0x01007086: 2d00 .- CMP r5,#0 + 0x01007088: d101 .. BNE 0x100708e ; yc_pin_irq_enable + 18 + 0x0100708a: 200a . MOVS r0,#0xa + 0x0100708c: bdf8 .. POP {r3-r7,pc} + 0x0100708e: 2e01 .. CMP r6,#1 + 0x01007090: d177 w. BNE 0x1007182 ; yc_pin_irq_enable + 262 + 0x01007092: 68e8 .h LDR r0,[r5,#0xc] + 0x01007094: 0003 .. MOVS r3,r0 + 0x01007096: f7f9ff9d .... BL __ARM_common_switch8 ; 0x1000fd4 + $d + 0x0100709a: 0405 .. DCW 1029 + 0x0100709c: 27070605 ...' DCD 654771717 + 0x010070a0: 0047 G. DCW 71 + $t + 0x010070a2: e046 F. B 0x1007132 ; yc_pin_irq_enable + 182 + 0x010070a4: e045 E. B 0x1007132 ; yc_pin_irq_enable + 182 + 0x010070a6: e044 D. B 0x1007132 ; yc_pin_irq_enable + 182 + 0x010070a8: 2080 . MOVS r0,#0x80 + 0x010070aa: 4949 II LDR r1,[pc,#292] ; [0x10071d0] = 0xf8700 + 0x010070ac: 1861 a. ADDS r1,r4,r1 + 0x010070ae: 7008 .p STRB r0,[r1,#0] + 0x010070b0: 4620 F MOV r0,r4 + 0x010070b2: 17e2 .. ASRS r2,r4,#31 + 0x010070b4: 0f12 .. LSRS r2,r2,#28 + 0x010070b6: 1812 .. ADDS r2,r2,r0 + 0x010070b8: 1112 .. ASRS r2,r2,#4 + 0x010070ba: 0052 R. LSLS r2,r2,#1 + 0x010070bc: 4b44 DK LDR r3,[pc,#272] ; [0x10071d0] = 0xf8700 + 0x010070be: 18d2 .. ADDS r2,r2,r3 + 0x010070c0: 8ed2 .. LDRH r2,[r2,#0x36] + 0x010070c2: 4621 !F MOV r1,r4 + 0x010070c4: 17e3 .. ASRS r3,r4,#31 + 0x010070c6: 0f1b .. LSRS r3,r3,#28 + 0x010070c8: 185b [. ADDS r3,r3,r1 + 0x010070ca: 111b .. ASRS r3,r3,#4 + 0x010070cc: 011b .. LSLS r3,r3,#4 + 0x010070ce: 1ae7 .. SUBS r7,r4,r3 + 0x010070d0: 2301 .# MOVS r3,#1 + 0x010070d2: 40bb .@ LSLS r3,r3,r7 + 0x010070d4: 401a .@ ANDS r2,r2,r3 + 0x010070d6: 17e3 .. ASRS r3,r4,#31 + 0x010070d8: 0f1b .. LSRS r3,r3,#28 + 0x010070da: 181b .. ADDS r3,r3,r0 + 0x010070dc: 111b .. ASRS r3,r3,#4 + 0x010070de: 005b [. LSLS r3,r3,#1 + 0x010070e0: 4f3b ;O LDR r7,[pc,#236] ; [0x10071d0] = 0xf8700 + 0x010070e2: 19db .. ADDS r3,r3,r7 + 0x010070e4: 86da .. STRH r2,[r3,#0x36] + 0x010070e6: e024 $. B 0x1007132 ; yc_pin_irq_enable + 182 + 0x010070e8: 2040 @ MOVS r0,#0x40 + 0x010070ea: 4939 9I LDR r1,[pc,#228] ; [0x10071d0] = 0xf8700 + 0x010070ec: 1861 a. ADDS r1,r4,r1 + 0x010070ee: 7008 .p STRB r0,[r1,#0] + 0x010070f0: 4620 F MOV r0,r4 + 0x010070f2: 17e2 .. ASRS r2,r4,#31 + 0x010070f4: 0f12 .. LSRS r2,r2,#28 + 0x010070f6: 1812 .. ADDS r2,r2,r0 + 0x010070f8: 1112 .. ASRS r2,r2,#4 + 0x010070fa: 0052 R. LSLS r2,r2,#1 + 0x010070fc: 4b34 4K LDR r3,[pc,#208] ; [0x10071d0] = 0xf8700 + 0x010070fe: 18d2 .. ADDS r2,r2,r3 + 0x01007100: 8ed2 .. LDRH r2,[r2,#0x36] + 0x01007102: 4621 !F MOV r1,r4 + 0x01007104: 17e3 .. ASRS r3,r4,#31 + 0x01007106: 0f1b .. LSRS r3,r3,#28 + 0x01007108: 185b [. ADDS r3,r3,r1 + 0x0100710a: 111b .. ASRS r3,r3,#4 + 0x0100710c: 011b .. LSLS r3,r3,#4 + 0x0100710e: 1ae7 .. SUBS r7,r4,r3 + 0x01007110: 2301 .# MOVS r3,#1 + 0x01007112: 40bb .@ LSLS r3,r3,r7 + 0x01007114: 431a .C ORRS r2,r2,r3 + 0x01007116: 17e3 .. ASRS r3,r4,#31 + 0x01007118: 0f1b .. LSRS r3,r3,#28 + 0x0100711a: 181b .. ADDS r3,r3,r0 + 0x0100711c: 111b .. ASRS r3,r3,#4 + 0x0100711e: 005b [. LSLS r3,r3,#1 + 0x01007120: 4f2b +O LDR r7,[pc,#172] ; [0x10071d0] = 0xf8700 + 0x01007122: 19db .. ADDS r3,r3,r7 + 0x01007124: 86da .. STRH r2,[r3,#0x36] + 0x01007126: e004 .. B 0x1007132 ; yc_pin_irq_enable + 182 + 0x01007128: 9800 .. LDR r0,[sp,#0] + 0x0100712a: f7f9f9cd .... BL rt_hw_interrupt_enable ; 0x10004c8 + 0x0100712e: 200a . MOVS r0,#0xa + 0x01007130: e7ac .. B 0x100708c ; yc_pin_irq_enable + 16 + 0x01007132: bf00 .. NOP + 0x01007134: f7f9f9c4 .... BL rt_hw_interrupt_disable ; 0x10004c0 + 0x01007138: 9000 .. STR r0,[sp,#0] + 0x0100713a: 2008 . MOVS r0,#8 + 0x0100713c: 5628 (V LDRSB r0,[r5,r0] + 0x0100713e: f7f9fcb3 .... BL NVIC_EnableIRQ ; 0x1000aa8 + 0x01007142: 4620 F MOV r0,r4 + 0x01007144: 17e2 .. ASRS r2,r4,#31 + 0x01007146: 0f12 .. LSRS r2,r2,#28 + 0x01007148: 1812 .. ADDS r2,r2,r0 + 0x0100714a: 1112 .. ASRS r2,r2,#4 + 0x0100714c: 0052 R. LSLS r2,r2,#1 + 0x0100714e: 4b20 K LDR r3,[pc,#128] ; [0x10071d0] = 0xf8700 + 0x01007150: 18d2 .. ADDS r2,r2,r3 + 0x01007152: 8e12 .. LDRH r2,[r2,#0x30] + 0x01007154: 4621 !F MOV r1,r4 + 0x01007156: 17e3 .. ASRS r3,r4,#31 + 0x01007158: 0f1b .. LSRS r3,r3,#28 + 0x0100715a: 185b [. ADDS r3,r3,r1 + 0x0100715c: 111b .. ASRS r3,r3,#4 + 0x0100715e: 011b .. LSLS r3,r3,#4 + 0x01007160: 1ae7 .. SUBS r7,r4,r3 + 0x01007162: 2301 .# MOVS r3,#1 + 0x01007164: 40bb .@ LSLS r3,r3,r7 + 0x01007166: 431a .C ORRS r2,r2,r3 + 0x01007168: 17e3 .. ASRS r3,r4,#31 + 0x0100716a: 0f1b .. LSRS r3,r3,#28 + 0x0100716c: 181b .. ADDS r3,r3,r0 + 0x0100716e: 111b .. ASRS r3,r3,#4 + 0x01007170: 005b [. LSLS r3,r3,#1 + 0x01007172: 4f17 .O LDR r7,[pc,#92] ; [0x10071d0] = 0xf8700 + 0x01007174: 19db .. ADDS r3,r3,r7 + 0x01007176: 861a .. STRH r2,[r3,#0x30] + 0x01007178: 9800 .. LDR r0,[sp,#0] + 0x0100717a: f7f9f9a5 .... BL rt_hw_interrupt_enable ; 0x10004c8 + 0x0100717e: e024 $. B 0x10071ca ; yc_pin_irq_enable + 334 + 0x01007180: e7ff .. B 0x1007182 ; yc_pin_irq_enable + 262 + 0x01007182: 2e00 .. CMP r6,#0 + 0x01007184: d11f .. BNE 0x10071c6 ; yc_pin_irq_enable + 330 + 0x01007186: 2008 . MOVS r0,#8 + 0x01007188: 5628 (V LDRSB r0,[r5,r0] + 0x0100718a: f7f9fc83 .... BL NVIC_DisableIRQ ; 0x1000a94 + 0x0100718e: 4620 F MOV r0,r4 + 0x01007190: 17e2 .. ASRS r2,r4,#31 + 0x01007192: 0f12 .. LSRS r2,r2,#28 + 0x01007194: 1812 .. ADDS r2,r2,r0 + 0x01007196: 1112 .. ASRS r2,r2,#4 + 0x01007198: 0052 R. LSLS r2,r2,#1 + 0x0100719a: 4b0d .K LDR r3,[pc,#52] ; [0x10071d0] = 0xf8700 + 0x0100719c: 18d2 .. ADDS r2,r2,r3 + 0x0100719e: 8e12 .. LDRH r2,[r2,#0x30] + 0x010071a0: 4621 !F MOV r1,r4 + 0x010071a2: 17e3 .. ASRS r3,r4,#31 + 0x010071a4: 0f1b .. LSRS r3,r3,#28 + 0x010071a6: 185b [. ADDS r3,r3,r1 + 0x010071a8: 111b .. ASRS r3,r3,#4 + 0x010071aa: 011b .. LSLS r3,r3,#4 + 0x010071ac: 1ae7 .. SUBS r7,r4,r3 + 0x010071ae: 2301 .# MOVS r3,#1 + 0x010071b0: 40bb .@ LSLS r3,r3,r7 + 0x010071b2: 439a .C BICS r2,r2,r3 + 0x010071b4: 17e3 .. ASRS r3,r4,#31 + 0x010071b6: 0f1b .. LSRS r3,r3,#28 + 0x010071b8: 181b .. ADDS r3,r3,r0 + 0x010071ba: 111b .. ASRS r3,r3,#4 + 0x010071bc: 005b [. LSLS r3,r3,#1 + 0x010071be: 4f04 .O LDR r7,[pc,#16] ; [0x10071d0] = 0xf8700 + 0x010071c0: 19db .. ADDS r3,r3,r7 + 0x010071c2: 861a .. STRH r2,[r3,#0x30] + 0x010071c4: e001 .. B 0x10071ca ; yc_pin_irq_enable + 334 + 0x010071c6: 2006 . MOVS r0,#6 + 0x010071c8: e760 `. B 0x100708c ; yc_pin_irq_enable + 16 + 0x010071ca: 2000 . MOVS r0,#0 + 0x010071cc: e75e ^. B 0x100708c ; yc_pin_irq_enable + 16 + $d + 0x010071ce: 0000 .. DCW 0 + 0x010071d0: 000f8700 .... DCD 1017600 + $t + i.yc_pin_mode + yc_pin_mode + 0x010071d4: b510 .. PUSH {r4,lr} + 0x010071d6: 2a00 .* CMP r2,#0 + 0x010071d8: d104 .. BNE 0x10071e4 ; yc_pin_mode + 16 + 0x010071da: 233e ># MOVS r3,#0x3e + 0x010071dc: 4c0f .L LDR r4,[pc,#60] ; [0x100721c] = 0xf8700 + 0x010071de: 190c .. ADDS r4,r1,r4 + 0x010071e0: 7023 #p STRB r3,[r4,#0] + 0x010071e2: e01a .. B 0x100721a ; yc_pin_mode + 70 + 0x010071e4: 2a01 .* CMP r2,#1 + 0x010071e6: d104 .. BNE 0x10071f2 ; yc_pin_mode + 30 + 0x010071e8: 2300 .# MOVS r3,#0 + 0x010071ea: 4c0c .L LDR r4,[pc,#48] ; [0x100721c] = 0xf8700 + 0x010071ec: 190c .. ADDS r4,r1,r4 + 0x010071ee: 7023 #p STRB r3,[r4,#0] + 0x010071f0: e013 .. B 0x100721a ; yc_pin_mode + 70 + 0x010071f2: 2a02 .* CMP r2,#2 + 0x010071f4: d104 .. BNE 0x1007200 ; yc_pin_mode + 44 + 0x010071f6: 2340 @# MOVS r3,#0x40 + 0x010071f8: 4c08 .L LDR r4,[pc,#32] ; [0x100721c] = 0xf8700 + 0x010071fa: 190c .. ADDS r4,r1,r4 + 0x010071fc: 7023 #p STRB r3,[r4,#0] + 0x010071fe: e00c .. B 0x100721a ; yc_pin_mode + 70 + 0x01007200: 2a03 .* CMP r2,#3 + 0x01007202: d104 .. BNE 0x100720e ; yc_pin_mode + 58 + 0x01007204: 2380 .# MOVS r3,#0x80 + 0x01007206: 4c05 .L LDR r4,[pc,#20] ; [0x100721c] = 0xf8700 + 0x01007208: 190c .. ADDS r4,r1,r4 + 0x0100720a: 7023 #p STRB r3,[r4,#0] + 0x0100720c: e005 .. B 0x100721a ; yc_pin_mode + 70 + 0x0100720e: 2a04 .* CMP r2,#4 + 0x01007210: d103 .. BNE 0x100721a ; yc_pin_mode + 70 + 0x01007212: 2340 @# MOVS r3,#0x40 + 0x01007214: 4c01 .L LDR r4,[pc,#4] ; [0x100721c] = 0xf8700 + 0x01007216: 190c .. ADDS r4,r1,r4 + 0x01007218: 7023 #p STRB r3,[r4,#0] + 0x0100721a: bd10 .. POP {r4,pc} + $d + 0x0100721c: 000f8700 .... DCD 1017600 + $t + i.yc_pin_read + yc_pin_read + 0x01007220: b570 p. PUSH {r4-r6,lr} + 0x01007222: 4604 .F MOV r4,r0 + 0x01007224: 460a .F MOV r2,r1 + 0x01007226: 17c8 .. ASRS r0,r1,#31 + 0x01007228: 0f00 .. LSRS r0,r0,#28 + 0x0100722a: 1880 .. ADDS r0,r0,r2 + 0x0100722c: 1100 .. ASRS r0,r0,#4 + 0x0100722e: 0040 @. LSLS r0,r0,#1 + 0x01007230: 4d09 .M LDR r5,[pc,#36] ; [0x1007258] = 0xf8700 + 0x01007232: 1940 @. ADDS r0,r0,r5 + 0x01007234: 8f80 .. LDRH r0,[r0,#0x3c] + 0x01007236: 460b .F MOV r3,r1 + 0x01007238: 17cd .. ASRS r5,r1,#31 + 0x0100723a: 0f2d -. LSRS r5,r5,#28 + 0x0100723c: 18ed .. ADDS r5,r5,r3 + 0x0100723e: 112d -. ASRS r5,r5,#4 + 0x01007240: 012d -. LSLS r5,r5,#4 + 0x01007242: 1b4e N. SUBS r6,r1,r5 + 0x01007244: 2501 .% MOVS r5,#1 + 0x01007246: 40b5 .@ LSLS r5,r5,r6 + 0x01007248: 4028 (@ ANDS r0,r0,r5 + 0x0100724a: 2800 .( CMP r0,#0 + 0x0100724c: d001 .. BEQ 0x1007252 ; yc_pin_read + 50 + 0x0100724e: 2001 . MOVS r0,#1 + 0x01007250: bd70 p. POP {r4-r6,pc} + 0x01007252: 2000 . MOVS r0,#0 + 0x01007254: e7fc .. B 0x1007250 ; yc_pin_read + 48 + $d + 0x01007256: 0000 .. DCW 0 + 0x01007258: 000f8700 .... DCD 1017600 + $t + i.yc_pin_write + yc_pin_write + 0x0100725c: b510 .. PUSH {r4,lr} + 0x0100725e: 2a00 .* CMP r2,#0 + 0x01007260: d004 .. BEQ 0x100726c ; yc_pin_write + 16 + 0x01007262: 233f ?# MOVS r3,#0x3f + 0x01007264: 4c04 .L LDR r4,[pc,#16] ; [0x1007278] = 0xf8700 + 0x01007266: 190c .. ADDS r4,r1,r4 + 0x01007268: 7023 #p STRB r3,[r4,#0] + 0x0100726a: e003 .. B 0x1007274 ; yc_pin_write + 24 + 0x0100726c: 233e ># MOVS r3,#0x3e + 0x0100726e: 4c02 .L LDR r4,[pc,#8] ; [0x1007278] = 0xf8700 + 0x01007270: 190c .. ADDS r4,r1,r4 + 0x01007272: 7023 #p STRB r3,[r4,#0] + 0x01007274: bd10 .. POP {r4,pc} + $d + 0x01007276: 0000 .. DCW 0 + 0x01007278: 000f8700 .... DCD 1017600 + $d.realdata + .constdata + __FUNCTION__ + 0x0100727c: 6e69705f _pin DCD 1852403807 + 0x01007280: 6165725f _rea DCD 1634038367 + 0x01007284: 0064 d. DCW 100 + __FUNCTION__ + 0x01007286: 705f _p DCW 28767 + 0x01007288: 775f6e69 in_w DCD 2002742889 + 0x0100728c: 65746972 rite DCD 1702127986 + 0x01007290: 00 . DCB 0 + __FUNCTION__ + 0x01007291: 5f7069 _pi DCB 95,112,105 + 0x01007294: 6f635f6e n_co DCD 1868783470 + 0x01007298: 6f72746e ntro DCD 1869771886 + 0x0100729c: 006c l. DCW 108 + __FUNCTION__ + 0x0100729e: 7472 rt DCW 29810 + 0x010072a0: 6e69705f _pin DCD 1852403807 + 0x010072a4: 7474615f _att DCD 1953784159 + 0x010072a8: 5f686361 ach_ DCD 1600676705 + 0x010072ac: 00717269 irq. DCD 7434857 + __FUNCTION__ + 0x010072b0: 705f7472 rt_p DCD 1885303922 + 0x010072b4: 645f6e69 in_d DCD 1683975785 + 0x010072b8: 63617465 etac DCD 1667331173 + 0x010072bc: 72695f68 h_ir DCD 1919508328 + 0x010072c0: 0071 q. DCW 113 + __FUNCTION__ + 0x010072c2: 7472 rt DCW 29810 + 0x010072c4: 6e69705f _pin DCD 1852403807 + 0x010072c8: 7172695f _irq DCD 1903323487 + 0x010072cc: 616e655f _ena DCD 1634624863 + 0x010072d0: 00656c62 ble. DCD 6646882 + __FUNCTION__ + 0x010072d4: 705f7472 rt_p DCD 1885303922 + 0x010072d8: 6d5f6e69 in_m DCD 1834970729 + 0x010072dc: 0065646f ode. DCD 6644847 + __FUNCTION__ + 0x010072e0: 705f7472 rt_p DCD 1885303922 + 0x010072e4: 775f6e69 in_w DCD 2002742889 + 0x010072e8: 65746972 rite DCD 1702127986 + 0x010072ec: 00 . DCB 0 + __FUNCTION__ + 0x010072ed: 72745f rt_ DCB 114,116,95 + 0x010072f0: 5f6e6970 pin_ DCD 1601071472 + 0x010072f4: 64616572 read DCD 1684104562 + 0x010072f8: 00 . DCB 0 + __FUNCTION__ + 0x010072f9: 72745f rt_ DCB 114,116,95 + 0x010072fc: 5f6e6970 pin_ DCD 1601071472 + 0x01007300: 00746567 get. DCD 7628135 + .constdata + __FUNCTION__ + 0x01007304: 7265735f _ser DCD 1919251295 + 0x01007308: 5f6c6169 ial_ DCD 1600938345 + 0x0100730c: 6c6c6f70 poll DCD 1819045744 + 0x01007310: 0078725f _rx. DCD 7893599 + __FUNCTION__ + 0x01007314: 7265735f _ser DCD 1919251295 + 0x01007318: 5f6c6169 ial_ DCD 1600938345 + 0x0100731c: 6c6c6f70 poll DCD 1819045744 + 0x01007320: 0078745f _tx. DCD 7894111 + __FUNCTION__ + 0x01007324: 7265735f _ser DCD 1919251295 + 0x01007328: 5f6c6169 ial_ DCD 1600938345 + 0x0100732c: 5f746e69 int_ DCD 1601465961 + 0x01007330: 7872 rx DCW 30834 + 0x01007332: 00 . DCB 0 + __FUNCTION__ + 0x01007333: 5f _ DCB 95 + 0x01007334: 69726573 seri DCD 1769104755 + 0x01007338: 695f6c61 al_i DCD 1767861345 + 0x0100733c: 745f746e nt_t DCD 1952412782 + 0x01007340: 0078 x. DCW 120 + __FUNCTION__ + 0x01007342: 7472 rt DCW 29810 + 0x01007344: 7265735f _ser DCD 1919251295 + 0x01007348: 5f6c6169 ial_ DCD 1600938345 + 0x0100734c: 74696e69 init DCD 1953066601 + 0x01007350: 00 . DCB 0 + __FUNCTION__ + 0x01007351: 72745f rt_ DCB 114,116,95 + 0x01007354: 69726573 seri DCD 1769104755 + 0x01007358: 6f5f6c61 al_o DCD 1868524641 + 0x0100735c: 006e6570 pen. DCD 7234928 + __FUNCTION__ + 0x01007360: 735f7472 rt_s DCD 1935635570 + 0x01007364: 61697265 eria DCD 1634300517 + 0x01007368: 6c635f6c l_cl DCD 1818451820 + 0x0100736c: 0065736f ose. DCD 6648687 + __FUNCTION__ + 0x01007370: 735f7472 rt_s DCD 1935635570 + 0x01007374: 61697265 eria DCD 1634300517 + 0x01007378: 65725f6c l_re DCD 1701994348 + 0x0100737c: 6461 ad DCW 25697 + 0x0100737e: 00 . DCB 0 + __FUNCTION__ + 0x0100737f: 72 r DCB 114 + 0x01007380: 65735f74 t_se DCD 1702059892 + 0x01007384: 6c616972 rial DCD 1818323314 + 0x01007388: 6972775f _wri DCD 1769109343 + 0x0100738c: 6574 te DCW 25972 + 0x0100738e: 00 . DCB 0 + __FUNCTION__ + 0x0100738f: 72 r DCB 114 + 0x01007390: 65735f74 t_se DCD 1702059892 + 0x01007394: 6c616972 rial DCD 1818323314 + 0x01007398: 6e6f635f _con DCD 1852793695 + 0x0100739c: 6c6f7274 trol DCD 1819243124 + 0x010073a0: 00 . DCB 0 + __FUNCTION__ + 0x010073a1: 72745f rt_ DCB 114,116,95 + 0x010073a4: 735f7768 hw_s DCD 1935636328 + 0x010073a8: 61697265 eria DCD 1634300517 + 0x010073ac: 65725f6c l_re DCD 1701994348 + 0x010073b0: 74736967 gist DCD 1953720679 + 0x010073b4: 7265 er DCW 29285 + 0x010073b6: 00 . DCB 0 + __FUNCTION__ + 0x010073b7: 72 r DCB 114 + 0x010073b8: 77685f74 t_hw DCD 2003328884 + 0x010073bc: 7265735f _ser DCD 1919251295 + 0x010073c0: 5f6c6169 ial_ DCD 1600938345 + 0x010073c4: 00727369 isr. DCD 7500649 + .constdata + __FUNCTION__ + 0x010073c8: 635f7472 rt_c DCD 1667200114 + 0x010073cc: 6c706d6f ompl DCD 1819307375 + 0x010073d0: 6f697465 etio DCD 1869182053 + 0x010073d4: 6e695f6e n_in DCD 1852399470 + 0x010073d8: 7469 it DCW 29801 + 0x010073da: 00 . DCB 0 + __FUNCTION__ + 0x010073db: 72 r DCB 114 + 0x010073dc: 6f635f74 t_co DCD 1868783476 + 0x010073e0: 656c706d mple DCD 1701605485 + 0x010073e4: 6e6f6974 tion DCD 1852795252 + 0x010073e8: 6961775f _wai DCD 1767995231 + 0x010073ec: 0074 t. DCW 116 + __FUNCTION__ + 0x010073ee: 7472 rt DCW 29810 + 0x010073f0: 6d6f635f _com DCD 1836016479 + 0x010073f4: 74656c70 plet DCD 1952803952 + 0x010073f8: 5f6e6f69 ion_ DCD 1601073001 + 0x010073fc: 656e6f64 done DCD 1701736292 + 0x01007400: 00000000 .... DCD 0 + .constdata + yc3121_pin_ops + 0x01007404: 010071d5 .q.. DCD 16806357 + 0x01007408: 0100725d ]r.. DCD 16806493 + 0x0100740c: 01007221 !r.. DCD 16806433 + 0x01007410: 01007031 1p.. DCD 16805937 + 0x01007414: 01007057 Wp.. DCD 16805975 + 0x01007418: 0100707d }p.. DCD 16806013 + 0x0100741c: 00000000 .... DCD 0 + .constdata + yc3121_uart_ops + 0x01007420: 01006e65 en.. DCD 16805477 + 0x01007424: 01006f35 5o.. DCD 16805685 + 0x01007428: 01006fe9 .o.. DCD 16805865 + 0x0100742c: 01006fa1 .o.. DCD 16805793 + 0x01007430: 00000000 .... DCD 0 + __FUNCTION__ + 0x01007434: 31336379 yc31 DCD 825451385 + 0x01007438: 755f3132 21_u DCD 1969172786 + 0x0100743c: 5f747261 art_ DCD 1601466977 + 0x01007440: 666e6f63 conf DCD 1718513507 + 0x01007444: 72756769 igur DCD 1920296809 + 0x01007448: 0065 e. DCW 101 + __FUNCTION__ + 0x0100744a: 6379 yc DCW 25465 + 0x0100744c: 31323133 3121 DCD 825372979 + 0x01007450: 7261755f _uar DCD 1918989663 + 0x01007454: 6f635f74 t_co DCD 1868783476 + 0x01007458: 6f72746e ntro DCD 1869771886 + 0x0100745c: 006c l. DCW 108 + __FUNCTION__ + 0x0100745e: 6379 yc DCW 25465 + 0x01007460: 31323133 3121 DCD 825372979 + 0x01007464: 7261755f _uar DCD 1918989663 + 0x01007468: 75705f74 t_pu DCD 1970298740 + 0x0100746c: 6374 tc DCW 25460 + 0x0100746e: 00 . DCB 0 + __FUNCTION__ + 0x0100746f: 79 y DCB 121 + 0x01007470: 32313363 c312 DCD 842085219 + 0x01007474: 61755f31 1_ua DCD 1635082033 + 0x01007478: 675f7472 rt_g DCD 1734308978 + 0x0100747c: 00637465 etc. DCD 6517861 + 0x01007480: 0001c200 .... DCD 115200 + 0x01007484: 00010008 .... DCD 65544 + .constdata + __FUNCTION__ + 0x01007488: 736e6966 fins DCD 1936615782 + 0x0100748c: 65675f68 h_ge DCD 1701273448 + 0x01007490: 72705f74 t_pr DCD 1919967092 + 0x01007494: 74706d6f ompt DCD 1953525103 + 0x01007498: 646f6d5f _mod DCD 1685024095 + 0x0100749c: 0065 e. DCW 101 + __FUNCTION__ + 0x0100749e: 6966 fi DCW 26982 + 0x010074a0: 5f68736e nsh_ DCD 1600680814 + 0x010074a4: 5f746573 set_ DCD 1601463667 + 0x010074a8: 6d6f7270 prom DCD 1836020336 + 0x010074ac: 6d5f7470 pt_m DCD 1834972272 + 0x010074b0: 0065646f ode. DCD 6644847 + __FUNCTION__ + 0x010074b4: 736e6966 fins DCD 1936615782 + 0x010074b8: 65675f68 h_ge DCD 1701273448 + 0x010074bc: 61686374 tcha DCD 1634231156 + 0x010074c0: 0072 r. DCW 114 + __FUNCTION__ + 0x010074c2: 6966 fi DCW 26982 + 0x010074c4: 5f68736e nsh_ DCD 1600680814 + 0x010074c8: 695f7872 rx_i DCD 1767864434 + 0x010074cc: 646e nd DCW 25710 + 0x010074ce: 00 . DCB 0 + __FUNCTION__ + 0x010074cf: 66 f DCB 102 + 0x010074d0: 68736e69 insh DCD 1752395369 + 0x010074d4: 7465735f _set DCD 1952805727 + 0x010074d8: 7665645f _dev DCD 1986356319 + 0x010074dc: 00656369 ice. DCD 6644585 + __FUNCTION__ + 0x010074e0: 736e6966 fins DCD 1936615782 + 0x010074e4: 65675f68 h_ge DCD 1701273448 + 0x010074e8: 65645f74 t_de DCD 1701076852 + 0x010074ec: 65636976 vice DCD 1701013878 + 0x010074f0: 00 . DCB 0 + __FUNCTION__ + 0x010074f1: 66696e fin DCB 102,105,110 + 0x010074f4: 735f6873 sh_s DCD 1935632499 + 0x010074f8: 655f7465 et_e DCD 1700754533 + 0x010074fc: 006f6863 cho. DCD 7301219 + __FUNCTION__ + 0x01007500: 736e6966 fins DCD 1936615782 + 0x01007504: 65675f68 h_ge DCD 1701273448 + 0x01007508: 63655f74 t_ec DCD 1667587956 + 0x0100750c: 6f68 ho DCW 28520 + 0x0100750e: 00 . DCB 0 + .constdata + __FUNCTION__ + 0x0100750f: 5f _ DCB 95 + 0x01007510: 5f68736d msh_ DCD 1600680813 + 0x01007514: 63657865 exec DCD 1667594341 + 0x01007518: 646d635f _cmd DCD 1684890463 + 0x0100751c: 00000000 .... DCD 0 + .constdata + device_type_str + 0x01007520: 01007e68 h~.. DCD 16809576 + 0x01007524: 01007e24 $~.. DCD 16809508 + 0x01007528: 01007da8 .}.. DCD 16809384 + 0x0100752c: 01007dbc .}.. DCD 16809404 + 0x01007530: 01007dd4 .}.. DCD 16809428 + 0x01007534: 01007da4 .}.. DCD 16809380 + 0x01007538: 01007df0 .}.. DCD 16809456 + 0x0100753c: 01007de0 .}.. DCD 16809440 + 0x01007540: 01007ed0 .~.. DCD 16809680 + 0x01007544: 01007e00 .~.. DCD 16809472 + 0x01007548: 01007ef8 .~.. DCD 16809720 + 0x0100754c: 01007ed8 .~.. DCD 16809688 + 0x01007550: 01007ee4 .~.. DCD 16809700 + 0x01007554: 01007dc8 .}.. DCD 16809416 + 0x01007558: 01007eec .~.. DCD 16809708 + 0x0100755c: 01007e44 D~.. DCD 16809540 + 0x01007560: 01007ec0 .~.. DCD 16809664 + 0x01007564: 01007e34 4~.. DCD 16809524 + 0x01007568: 01007e58 X~.. DCD 16809560 + 0x0100756c: 01007e8c .~.. DCD 16809612 + 0x01007570: 01007e7c |~.. DCD 16809596 + 0x01007574: 01007e14 .~.. DCD 16809492 + 0x01007578: 01007ea4 .~.. DCD 16809636 + 0x0100757c: 01007eb0 .~.. DCD 16809648 + 0x01007580: 01007ec8 .~.. DCD 16809672 + .constdata + __FUNCTION__ + 0x01007584: 615f7472 rt_a DCD 1633645682 + 0x01007588: 696c7070 ppli DCD 1768714352 + 0x0100758c: 69746163 cati DCD 1769234787 + 0x01007590: 695f6e6f on_i DCD 1767861871 + 0x01007594: 0074696e nit. DCD 7629166 + .constdata + __FUNCTION__ + 0x01007598: 5f74725f _rt_ DCD 1601466975 + 0x0100759c: 65686373 sche DCD 1701340019 + 0x010075a0: 656c7564 dule DCD 1701606756 + 0x010075a4: 74735f72 r_st DCD 1953718130 + 0x010075a8: 5f6b6361 ack_ DCD 1600873313 + 0x010075ac: 63656863 chec DCD 1667590243 + 0x010075b0: 006b k. DCW 107 + __FUNCTION__ + 0x010075b2: 7472 rt DCW 29810 + 0x010075b4: 6863735f _sch DCD 1751348063 + 0x010075b8: 6c756465 edul DCD 1819632741 + 0x010075bc: 6e695f65 e_in DCD 1852399461 + 0x010075c0: 74726573 sert DCD 1953654131 + 0x010075c4: 7268745f _thr DCD 1919448159 + 0x010075c8: 00646165 ead. DCD 6578533 + __FUNCTION__ + 0x010075cc: 735f7472 rt_s DCD 1935635570 + 0x010075d0: 64656863 ched DCD 1684367459 + 0x010075d4: 5f656c75 ule_ DCD 1600482421 + 0x010075d8: 6f6d6572 remo DCD 1869440370 + 0x010075dc: 745f6576 ve_t DCD 1952408950 + 0x010075e0: 61657268 hrea DCD 1634038376 + 0x010075e4: 0064 d. DCW 100 + .constdata + __FUNCTION__ + 0x010075e6: 7472 rt DCW 29810 + 0x010075e8: 6665645f _def DCD 1717920863 + 0x010075ec: 74636e75 unct DCD 1952673397 + 0x010075f0: 6578655f _exe DCD 1702389087 + 0x010075f4: 65747563 cute DCD 1702131043 + 0x010075f8: 00 . DCB 0 + .constdata + __FUNCTION__ + 0x010075f9: 72745f rt_ DCB 114,116,95 + 0x010075fc: 69766564 devi DCD 1769366884 + 0x01007600: 755f6563 ce_u DCD 1969186147 + 0x01007604: 6765726e nreg DCD 1734701678 + 0x01007608: 65747369 iste DCD 1702130537 + 0x0100760c: 0072 r. DCW 114 + __FUNCTION__ + 0x0100760e: 7472 rt DCW 29810 + 0x01007610: 7665645f _dev DCD 1986356319 + 0x01007614: 5f656369 ice_ DCD 1600480105 + 0x01007618: 74736564 dest DCD 1953719652 + 0x0100761c: 00796f72 roy. DCD 7958386 + __FUNCTION__ + 0x01007620: 645f7472 rt_d DCD 1683977330 + 0x01007624: 63697665 evic DCD 1667855973 + 0x01007628: 6e695f65 e_in DCD 1852399461 + 0x0100762c: 7469 it DCW 29801 + 0x0100762e: 00 . DCB 0 + __FUNCTION__ + 0x0100762f: 72 r DCB 114 + 0x01007630: 65645f74 t_de DCD 1701076852 + 0x01007634: 65636976 vice DCD 1701013878 + 0x01007638: 65706f5f _ope DCD 1701867359 + 0x0100763c: 006e n. DCW 110 + __FUNCTION__ + 0x0100763e: 7472 rt DCW 29810 + 0x01007640: 7665645f _dev DCD 1986356319 + 0x01007644: 5f656369 ice_ DCD 1600480105 + 0x01007648: 736f6c63 clos DCD 1936682083 + 0x0100764c: 0065 e. DCW 101 + __FUNCTION__ + 0x0100764e: 7472 rt DCW 29810 + 0x01007650: 7665645f _dev DCD 1986356319 + 0x01007654: 5f656369 ice_ DCD 1600480105 + 0x01007658: 64616572 read DCD 1684104562 + 0x0100765c: 00 . DCB 0 + __FUNCTION__ + 0x0100765d: 72745f rt_ DCB 114,116,95 + 0x01007660: 69766564 devi DCD 1769366884 + 0x01007664: 775f6563 ce_w DCD 2002740579 + 0x01007668: 65746972 rite DCD 1702127986 + 0x0100766c: 00 . DCB 0 + __FUNCTION__ + 0x0100766d: 72745f rt_ DCB 114,116,95 + 0x01007670: 69766564 devi DCD 1769366884 + 0x01007674: 635f6563 ce_c DCD 1667196259 + 0x01007678: 72746e6f ontr DCD 1920233071 + 0x0100767c: 6c6f ol DCW 27759 + 0x0100767e: 00 . DCB 0 + __FUNCTION__ + 0x0100767f: 72 r DCB 114 + 0x01007680: 65645f74 t_de DCD 1701076852 + 0x01007684: 65636976 vice DCD 1701013878 + 0x01007688: 7465735f _set DCD 1952805727 + 0x0100768c: 5f78725f _rx_ DCD 1601729119 + 0x01007690: 69646e69 indi DCD 1768189545 + 0x01007694: 65746163 cate DCD 1702125923 + 0x01007698: 00 . DCB 0 + __FUNCTION__ + 0x01007699: 72745f rt_ DCB 114,116,95 + 0x0100769c: 69766564 devi DCD 1769366884 + 0x010076a0: 735f6563 ce_s DCD 1935631715 + 0x010076a4: 745f7465 et_t DCD 1952412773 + 0x010076a8: 6f635f78 x_co DCD 1868783480 + 0x010076ac: 656c706d mple DCD 1701605485 + 0x010076b0: 6574 te DCW 25972 + 0x010076b2: 00 . DCB 0 + .constdata + __lowest_bit_bitmap + 0x010076b3: 00 . DCB 0 + 0x010076b4: 02000100 .... DCD 33554688 + 0x010076b8: 03000100 .... DCD 50331904 + 0x010076bc: 02000100 .... DCD 33554688 + 0x010076c0: 04000100 .... DCD 67109120 + 0x010076c4: 02000100 .... DCD 33554688 + 0x010076c8: 03000100 .... DCD 50331904 + 0x010076cc: 02000100 .... DCD 33554688 + 0x010076d0: 05000100 .... DCD 83886336 + 0x010076d4: 02000100 .... DCD 33554688 + 0x010076d8: 03000100 .... DCD 50331904 + 0x010076dc: 02000100 .... DCD 33554688 + 0x010076e0: 04000100 .... DCD 67109120 + 0x010076e4: 02000100 .... DCD 33554688 + 0x010076e8: 03000100 .... DCD 50331904 + 0x010076ec: 02000100 .... DCD 33554688 + 0x010076f0: 06000100 .... DCD 100663552 + 0x010076f4: 02000100 .... DCD 33554688 + 0x010076f8: 03000100 .... DCD 50331904 + 0x010076fc: 02000100 .... DCD 33554688 + 0x01007700: 04000100 .... DCD 67109120 + 0x01007704: 02000100 .... DCD 33554688 + 0x01007708: 03000100 .... DCD 50331904 + 0x0100770c: 02000100 .... DCD 33554688 + 0x01007710: 05000100 .... DCD 83886336 + 0x01007714: 02000100 .... DCD 33554688 + 0x01007718: 03000100 .... DCD 50331904 + 0x0100771c: 02000100 .... DCD 33554688 + 0x01007720: 04000100 .... DCD 67109120 + 0x01007724: 02000100 .... DCD 33554688 + 0x01007728: 03000100 .... DCD 50331904 + 0x0100772c: 02000100 .... DCD 33554688 + 0x01007730: 07000100 .... DCD 117440768 + 0x01007734: 02000100 .... DCD 33554688 + 0x01007738: 03000100 .... DCD 50331904 + 0x0100773c: 02000100 .... DCD 33554688 + 0x01007740: 04000100 .... DCD 67109120 + 0x01007744: 02000100 .... DCD 33554688 + 0x01007748: 03000100 .... DCD 50331904 + 0x0100774c: 02000100 .... DCD 33554688 + 0x01007750: 05000100 .... DCD 83886336 + 0x01007754: 02000100 .... DCD 33554688 + 0x01007758: 03000100 .... DCD 50331904 + 0x0100775c: 02000100 .... DCD 33554688 + 0x01007760: 04000100 .... DCD 67109120 + 0x01007764: 02000100 .... DCD 33554688 + 0x01007768: 03000100 .... DCD 50331904 + 0x0100776c: 02000100 .... DCD 33554688 + 0x01007770: 06000100 .... DCD 100663552 + 0x01007774: 02000100 .... DCD 33554688 + 0x01007778: 03000100 .... DCD 50331904 + 0x0100777c: 02000100 .... DCD 33554688 + 0x01007780: 04000100 .... DCD 67109120 + 0x01007784: 02000100 .... DCD 33554688 + 0x01007788: 03000100 .... DCD 50331904 + 0x0100778c: 02000100 .... DCD 33554688 + 0x01007790: 05000100 .... DCD 83886336 + 0x01007794: 02000100 .... DCD 33554688 + 0x01007798: 03000100 .... DCD 50331904 + 0x0100779c: 02000100 .... DCD 33554688 + 0x010077a0: 04000100 .... DCD 67109120 + 0x010077a4: 02000100 .... DCD 33554688 + 0x010077a8: 03000100 .... DCD 50331904 + 0x010077ac: 02000100 .... DCD 33554688 + 0x010077b0: 0100 .. DCW 256 + 0x010077b2: 00 . DCB 0 + small_digits + 0x010077b3: 30 0 DCB 48 + 0x010077b4: 34333231 1234 DCD 875770417 + 0x010077b8: 38373635 5678 DCD 943142453 + 0x010077bc: 63626139 9abc DCD 1667391801 + 0x010077c0: 00666564 def. DCD 6710628 + large_digits + 0x010077c4: 33323130 0123 DCD 858927408 + 0x010077c8: 37363534 4567 DCD 926299444 + 0x010077cc: 42413938 89AB DCD 1111570744 + 0x010077d0: 46454443 CDEF DCD 1178944579 + 0x010077d4: 00 . DCB 0 + .constdata + __FUNCTION__ + 0x010077d5: 5f6970 _ip DCB 95,105,112 + 0x010077d8: 696c5f63 c_li DCD 1768709987 + 0x010077dc: 735f7473 st_s DCD 1935635571 + 0x010077e0: 65707375 uspe DCD 1701868405 + 0x010077e4: 646e nd DCW 25710 + 0x010077e6: 00 . DCB 0 + __FUNCTION__ + 0x010077e7: 72 r DCB 114 + 0x010077e8: 65735f74 t_se DCD 1702059892 + 0x010077ec: 6e695f6d m_in DCD 1852399469 + 0x010077f0: 7469 it DCW 29801 + 0x010077f2: 00 . DCB 0 + __FUNCTION__ + 0x010077f3: 72 r DCB 114 + 0x010077f4: 65735f74 t_se DCD 1702059892 + 0x010077f8: 65645f6d m_de DCD 1701076845 + 0x010077fc: 68636174 tach DCD 1751343476 + 0x01007800: 00 . DCB 0 + __FUNCTION__ + 0x01007801: 72745f rt_ DCB 114,116,95 + 0x01007804: 5f6d6573 sem_ DCD 1601004915 + 0x01007808: 61657263 crea DCD 1634038371 + 0x0100780c: 6574 te DCW 25972 + 0x0100780e: 00 . DCB 0 + __FUNCTION__ + 0x0100780f: 72 r DCB 114 + 0x01007810: 65735f74 t_se DCD 1702059892 + 0x01007814: 65645f6d m_de DCD 1701076845 + 0x01007818: 6574656c lete DCD 1702126956 + 0x0100781c: 00 . DCB 0 + __FUNCTION__ + 0x0100781d: 72745f rt_ DCB 114,116,95 + 0x01007820: 5f6d6573 sem_ DCD 1601004915 + 0x01007824: 656b6174 take DCD 1701536116 + 0x01007828: 00 . DCB 0 + __FUNCTION__ + 0x01007829: 72745f rt_ DCB 114,116,95 + 0x0100782c: 5f6d6573 sem_ DCD 1601004915 + 0x01007830: 656c6572 rele DCD 1701602674 + 0x01007834: 00657361 ase. DCD 6648673 + __FUNCTION__ + 0x01007838: 735f7472 rt_s DCD 1935635570 + 0x0100783c: 635f6d65 em_c DCD 1667198309 + 0x01007840: 72746e6f ontr DCD 1920233071 + 0x01007844: 6c6f ol DCW 27759 + 0x01007846: 00 . DCB 0 + __FUNCTION__ + 0x01007847: 72 r DCB 114 + 0x01007848: 756d5f74 t_mu DCD 1970102132 + 0x0100784c: 5f786574 tex_ DCD 1601725812 + 0x01007850: 74696e69 init DCD 1953066601 + 0x01007854: 00 . DCB 0 + __FUNCTION__ + 0x01007855: 72745f rt_ DCB 114,116,95 + 0x01007858: 6574756d mute DCD 1702131053 + 0x0100785c: 65645f78 x_de DCD 1701076856 + 0x01007860: 68636174 tach DCD 1751343476 + 0x01007864: 00 . DCB 0 + __FUNCTION__ + 0x01007865: 72745f rt_ DCB 114,116,95 + 0x01007868: 6574756d mute DCD 1702131053 + 0x0100786c: 72635f78 x_cr DCD 1919115128 + 0x01007870: 65746165 eate DCD 1702125925 + 0x01007874: 00 . DCB 0 + __FUNCTION__ + 0x01007875: 72745f rt_ DCB 114,116,95 + 0x01007878: 6574756d mute DCD 1702131053 + 0x0100787c: 65645f78 x_de DCD 1701076856 + 0x01007880: 6574656c lete DCD 1702126956 + 0x01007884: 00 . DCB 0 + __FUNCTION__ + 0x01007885: 72745f rt_ DCB 114,116,95 + 0x01007888: 6574756d mute DCD 1702131053 + 0x0100788c: 61745f78 x_ta DCD 1635016568 + 0x01007890: 656b ke DCW 25963 + 0x01007892: 00 . DCB 0 + __FUNCTION__ + 0x01007893: 72 r DCB 114 + 0x01007894: 756d5f74 t_mu DCD 1970102132 + 0x01007898: 5f786574 tex_ DCD 1601725812 + 0x0100789c: 656c6572 rele DCD 1701602674 + 0x010078a0: 00657361 ase. DCD 6648673 + __FUNCTION__ + 0x010078a4: 6d5f7472 rt_m DCD 1834972274 + 0x010078a8: 78657475 utex DCD 2019914869 + 0x010078ac: 6e6f635f _con DCD 1852793695 + 0x010078b0: 6c6f7274 trol DCD 1819243124 + 0x010078b4: 00 . DCB 0 + __FUNCTION__ + 0x010078b5: 72745f rt_ DCB 114,116,95 + 0x010078b8: 6e657665 even DCD 1852143205 + 0x010078bc: 6e695f74 t_in DCD 1852399476 + 0x010078c0: 7469 it DCW 29801 + 0x010078c2: 00 . DCB 0 + __FUNCTION__ + 0x010078c3: 72 r DCB 114 + 0x010078c4: 76655f74 t_ev DCD 1986355060 + 0x010078c8: 5f746e65 ent_ DCD 1601465957 + 0x010078cc: 61746564 deta DCD 1635018084 + 0x010078d0: 6863 ch DCW 26723 + 0x010078d2: 00 . DCB 0 + __FUNCTION__ + 0x010078d3: 72 r DCB 114 + 0x010078d4: 76655f74 t_ev DCD 1986355060 + 0x010078d8: 5f746e65 ent_ DCD 1601465957 + 0x010078dc: 61657263 crea DCD 1634038371 + 0x010078e0: 6574 te DCW 25972 + 0x010078e2: 00 . DCB 0 + __FUNCTION__ + 0x010078e3: 72 r DCB 114 + 0x010078e4: 76655f74 t_ev DCD 1986355060 + 0x010078e8: 5f746e65 ent_ DCD 1601465957 + 0x010078ec: 656c6564 dele DCD 1701602660 + 0x010078f0: 6574 te DCW 25972 + 0x010078f2: 00 . DCB 0 + __FUNCTION__ + 0x010078f3: 72 r DCB 114 + 0x010078f4: 76655f74 t_ev DCD 1986355060 + 0x010078f8: 5f746e65 ent_ DCD 1601465957 + 0x010078fc: 646e6573 send DCD 1684956531 + 0x01007900: 00 . DCB 0 + __FUNCTION__ + 0x01007901: 72745f rt_ DCB 114,116,95 + 0x01007904: 6e657665 even DCD 1852143205 + 0x01007908: 65725f74 t_re DCD 1701994356 + 0x0100790c: 7663 cv DCW 30307 + 0x0100790e: 00 . DCB 0 + __FUNCTION__ + 0x0100790f: 72 r DCB 114 + 0x01007910: 76655f74 t_ev DCD 1986355060 + 0x01007914: 5f746e65 ent_ DCD 1601465957 + 0x01007918: 746e6f63 cont DCD 1953394531 + 0x0100791c: 006c6f72 rol. DCD 7106418 + __FUNCTION__ + 0x01007920: 6d5f7472 rt_m DCD 1834972274 + 0x01007924: 6e695f62 b_in DCD 1852399458 + 0x01007928: 7469 it DCW 29801 + 0x0100792a: 00 . DCB 0 + __FUNCTION__ + 0x0100792b: 72 r DCB 114 + 0x0100792c: 626d5f74 t_mb DCD 1651335028 + 0x01007930: 7465645f _det DCD 1952801887 + 0x01007934: 00686361 ach. DCD 6841185 + __FUNCTION__ + 0x01007938: 6d5f7472 rt_m DCD 1834972274 + 0x0100793c: 72635f62 b_cr DCD 1919115106 + 0x01007940: 65746165 eate DCD 1702125925 + 0x01007944: 00 . DCB 0 + __FUNCTION__ + 0x01007945: 72745f rt_ DCB 114,116,95 + 0x01007948: 645f626d mb_d DCD 1683972717 + 0x0100794c: 74656c65 elet DCD 1952803941 + 0x01007950: 0065 e. DCW 101 + __FUNCTION__ + 0x01007952: 7472 rt DCW 29810 + 0x01007954: 5f626d5f _mb_ DCD 1600286047 + 0x01007958: 646e6573 send DCD 1684956531 + 0x0100795c: 6961775f _wai DCD 1767995231 + 0x01007960: 0074 t. DCW 116 + __FUNCTION__ + 0x01007962: 7472 rt DCW 29810 + 0x01007964: 5f626d5f _mb_ DCD 1600286047 + 0x01007968: 65677275 urge DCD 1701278325 + 0x0100796c: 746e nt DCW 29806 + 0x0100796e: 00 . DCB 0 + __FUNCTION__ + 0x0100796f: 72 r DCB 114 + 0x01007970: 626d5f74 t_mb DCD 1651335028 + 0x01007974: 6365725f _rec DCD 1667592799 + 0x01007978: 0076 v. DCW 118 + __FUNCTION__ + 0x0100797a: 7472 rt DCW 29810 + 0x0100797c: 5f626d5f _mb_ DCD 1600286047 + 0x01007980: 746e6f63 cont DCD 1953394531 + 0x01007984: 006c6f72 rol. DCD 7106418 + __FUNCTION__ + 0x01007988: 6d5f7472 rt_m DCD 1834972274 + 0x0100798c: 6e695f71 q_in DCD 1852399473 + 0x01007990: 7469 it DCW 29801 + 0x01007992: 00 . DCB 0 + __FUNCTION__ + 0x01007993: 72 r DCB 114 + 0x01007994: 716d5f74 t_mq DCD 1902993268 + 0x01007998: 7465645f _det DCD 1952801887 + 0x0100799c: 00686361 ach. DCD 6841185 + __FUNCTION__ + 0x010079a0: 6d5f7472 rt_m DCD 1834972274 + 0x010079a4: 72635f71 q_cr DCD 1919115121 + 0x010079a8: 65746165 eate DCD 1702125925 + 0x010079ac: 00 . DCB 0 + __FUNCTION__ + 0x010079ad: 72745f rt_ DCB 114,116,95 + 0x010079b0: 645f716d mq_d DCD 1683976557 + 0x010079b4: 74656c65 elet DCD 1952803941 + 0x010079b8: 0065 e. DCW 101 + __FUNCTION__ + 0x010079ba: 7472 rt DCW 29810 + 0x010079bc: 5f716d5f _mq_ DCD 1601269087 + 0x010079c0: 646e6573 send DCD 1684956531 + 0x010079c4: 6961775f _wai DCD 1767995231 + 0x010079c8: 0074 t. DCW 116 + __FUNCTION__ + 0x010079ca: 7472 rt DCW 29810 + 0x010079cc: 5f716d5f _mq_ DCD 1601269087 + 0x010079d0: 65677275 urge DCD 1701278325 + 0x010079d4: 746e nt DCW 29806 + 0x010079d6: 00 . DCB 0 + __FUNCTION__ + 0x010079d7: 72 r DCB 114 + 0x010079d8: 716d5f74 t_mq DCD 1902993268 + 0x010079dc: 6365725f _rec DCD 1667592799 + 0x010079e0: 0076 v. DCW 118 + __FUNCTION__ + 0x010079e2: 7472 rt DCW 29810 + 0x010079e4: 5f716d5f _mq_ DCD 1601269087 + 0x010079e8: 746e6f63 cont DCD 1953394531 + 0x010079ec: 006c6f72 rol. DCD 7106418 + .constdata + __FUNCTION__ + 0x010079f0: 745f7472 rt_t DCD 1952412786 + 0x010079f4: 72656d69 imer DCD 1919249769 + 0x010079f8: 696e695f _ini DCD 1768843615 + 0x010079fc: 0074 t. DCW 116 + __FUNCTION__ + 0x010079fe: 7472 rt DCW 29810 + 0x01007a00: 6d69745f _tim DCD 1835627615 + 0x01007a04: 645f7265 er_d DCD 1683976805 + 0x01007a08: 63617465 etac DCD 1667331173 + 0x01007a0c: 0068 h. DCW 104 + __FUNCTION__ + 0x01007a0e: 7472 rt DCW 29810 + 0x01007a10: 6d69745f _tim DCD 1835627615 + 0x01007a14: 645f7265 er_d DCD 1683976805 + 0x01007a18: 74656c65 elet DCD 1952803941 + 0x01007a1c: 0065 e. DCW 101 + __FUNCTION__ + 0x01007a1e: 7472 rt DCW 29810 + 0x01007a20: 6d69745f _tim DCD 1835627615 + 0x01007a24: 735f7265 er_s DCD 1935635045 + 0x01007a28: 74726174 tart DCD 1953653108 + 0x01007a2c: 00 . DCB 0 + __FUNCTION__ + 0x01007a2d: 72745f rt_ DCB 114,116,95 + 0x01007a30: 656d6974 time DCD 1701669236 + 0x01007a34: 74735f72 r_st DCD 1953718130 + 0x01007a38: 706f op DCW 28783 + 0x01007a3a: 00 . DCB 0 + __FUNCTION__ + 0x01007a3b: 72 r DCB 114 + 0x01007a3c: 69745f74 t_ti DCD 1769234292 + 0x01007a40: 5f72656d mer_ DCD 1601332589 + 0x01007a44: 746e6f63 cont DCD 1953394531 + 0x01007a48: 006c6f72 rol. DCD 7106418 + .constdata + __FUNCTION__ + 0x01007a4c: 6f5f7472 rt_o DCD 1868526706 + 0x01007a50: 63656a62 bjec DCD 1667590754 + 0x01007a54: 6e695f74 t_in DCD 1852399476 + 0x01007a58: 7469 it DCW 29801 + 0x01007a5a: 00 . DCB 0 + __FUNCTION__ + 0x01007a5b: 72 r DCB 114 + 0x01007a5c: 626f5f74 t_ob DCD 1651466100 + 0x01007a60: 7463656a ject DCD 1952671082 + 0x01007a64: 7465645f _det DCD 1952801887 + 0x01007a68: 00686361 ach. DCD 6841185 + __FUNCTION__ + 0x01007a6c: 6f5f7472 rt_o DCD 1868526706 + 0x01007a70: 63656a62 bjec DCD 1667590754 + 0x01007a74: 6c615f74 t_al DCD 1818320756 + 0x01007a78: 61636f6c loca DCD 1633906540 + 0x01007a7c: 6574 te DCW 25972 + 0x01007a7e: 00 . DCB 0 + __FUNCTION__ + 0x01007a7f: 72 r DCB 114 + 0x01007a80: 626f5f74 t_ob DCD 1651466100 + 0x01007a84: 7463656a ject DCD 1952671082 + 0x01007a88: 6c65645f _del DCD 1818584159 + 0x01007a8c: 00657465 ete. DCD 6648933 + __FUNCTION__ + 0x01007a90: 6f5f7472 rt_o DCD 1868526706 + 0x01007a94: 63656a62 bjec DCD 1667590754 + 0x01007a98: 73695f74 t_is DCD 1936285556 + 0x01007a9c: 7379735f _sys DCD 1937339231 + 0x01007aa0: 6f6d6574 temo DCD 1869440372 + 0x01007aa4: 63656a62 bjec DCD 1667590754 + 0x01007aa8: 0074 t. DCW 116 + __FUNCTION__ + 0x01007aaa: 7472 rt DCW 29810 + 0x01007aac: 6a626f5f _obj DCD 1784835935 + 0x01007ab0: 5f746365 ect_ DCD 1601463141 + 0x01007ab4: 5f746567 get_ DCD 1601463655 + 0x01007ab8: 65707974 type DCD 1701869940 + 0x01007abc: 00 . DCB 0 + __FUNCTION__ + 0x01007abd: 72745f rt_ DCB 114,116,95 + 0x01007ac0: 656a626f obje DCD 1701470831 + 0x01007ac4: 665f7463 ct_f DCD 1717531747 + 0x01007ac8: 00646e69 ind. DCD 6581865 + .constdata + __FUNCTION__ + 0x01007acc: 6d5f7472 rt_m DCD 1834972274 + 0x01007ad0: 65686d65 emhe DCD 1701342565 + 0x01007ad4: 695f7061 ap_i DCD 1767862369 + 0x01007ad8: 0074696e nit. DCD 7629166 + __FUNCTION__ + 0x01007adc: 6d5f7472 rt_m DCD 1834972274 + 0x01007ae0: 65686d65 emhe DCD 1701342565 + 0x01007ae4: 645f7061 ap_d DCD 1683976289 + 0x01007ae8: 63617465 etac DCD 1667331173 + 0x01007aec: 0068 h. DCW 104 + __FUNCTION__ + 0x01007aee: 7472 rt DCW 29810 + 0x01007af0: 6d656d5f _mem DCD 1835363679 + 0x01007af4: 70616568 heap DCD 1885431144 + 0x01007af8: 6c6c615f _all DCD 1819042143 + 0x01007afc: 636f oc DCW 25455 + 0x01007afe: 00 . DCB 0 + __FUNCTION__ + 0x01007aff: 72 r DCB 114 + 0x01007b00: 656d5f74 t_me DCD 1701666676 + 0x01007b04: 6165686d mhea DCD 1634035821 + 0x01007b08: 65725f70 p_re DCD 1701994352 + 0x01007b0c: 6f6c6c61 allo DCD 1869376609 + 0x01007b10: 0063 c. DCW 99 + __FUNCTION__ + 0x01007b12: 7472 rt DCW 29810 + 0x01007b14: 6d656d5f _mem DCD 1835363679 + 0x01007b18: 70616568 heap DCD 1885431144 + 0x01007b1c: 6572665f _fre DCD 1701996127 + 0x01007b20: 0065 e. DCW 101 + __FUNCTION__ + 0x01007b22: 7472 rt DCW 29810 + 0x01007b24: 6d656d5f _mem DCD 1835363679 + 0x01007b28: 70616568 heap DCD 1885431144 + 0x01007b2c: 6d75645f _dum DCD 1836409951 + 0x01007b30: 0070 p. DCW 112 + .constdata + __FUNCTION__ + 0x01007b32: 745f _t DCW 29791 + 0x01007b34: 61657268 hrea DCD 1634038376 + 0x01007b38: 6e695f64 d_in DCD 1852399460 + 0x01007b3c: 7469 it DCW 29801 + 0x01007b3e: 00 . DCB 0 + __FUNCTION__ + 0x01007b3f: 72 r DCB 114 + 0x01007b40: 68745f74 t_th DCD 1752457076 + 0x01007b44: 64616572 read DCD 1684104562 + 0x01007b48: 696e695f _ini DCD 1768843615 + 0x01007b4c: 0074 t. DCW 116 + __FUNCTION__ + 0x01007b4e: 7472 rt DCW 29810 + 0x01007b50: 7268745f _thr DCD 1919448159 + 0x01007b54: 5f646165 ead_ DCD 1600414053 + 0x01007b58: 72617473 star DCD 1918989427 + 0x01007b5c: 00707574 tup. DCD 7370100 + __FUNCTION__ + 0x01007b60: 745f7472 rt_t DCD 1952412786 + 0x01007b64: 61657268 hrea DCD 1634038376 + 0x01007b68: 65645f64 d_de DCD 1701076836 + 0x01007b6c: 68636174 tach DCD 1751343476 + 0x01007b70: 00 . DCB 0 + __FUNCTION__ + 0x01007b71: 72745f rt_ DCB 114,116,95 + 0x01007b74: 65726874 thre DCD 1701996660 + 0x01007b78: 645f6461 ad_d DCD 1683973217 + 0x01007b7c: 74656c65 elet DCD 1952803941 + 0x01007b80: 0065 e. DCW 101 + __FUNCTION__ + 0x01007b82: 7472 rt DCW 29810 + 0x01007b84: 7268745f _thr DCD 1919448159 + 0x01007b88: 5f646165 ead_ DCD 1600414053 + 0x01007b8c: 65656c73 slee DCD 1701145715 + 0x01007b90: 0070 p. DCW 112 + __FUNCTION__ + 0x01007b92: 7472 rt DCW 29810 + 0x01007b94: 7268745f _thr DCD 1919448159 + 0x01007b98: 5f646165 ead_ DCD 1600414053 + 0x01007b9c: 616c6564 dela DCD 1634493796 + 0x01007ba0: 6e755f79 y_un DCD 1853185913 + 0x01007ba4: 006c6974 til. DCD 7104884 + __FUNCTION__ + 0x01007ba8: 745f7472 rt_t DCD 1952412786 + 0x01007bac: 61657268 hrea DCD 1634038376 + 0x01007bb0: 6f635f64 d_co DCD 1868783460 + 0x01007bb4: 6f72746e ntro DCD 1869771886 + 0x01007bb8: 006c l. DCW 108 + __FUNCTION__ + 0x01007bba: 7472 rt DCW 29810 + 0x01007bbc: 7268745f _thr DCD 1919448159 + 0x01007bc0: 5f646165 ead_ DCD 1600414053 + 0x01007bc4: 70737573 susp DCD 1886614899 + 0x01007bc8: 00646e65 end. DCD 6581861 + __FUNCTION__ + 0x01007bcc: 745f7472 rt_t DCD 1952412786 + 0x01007bd0: 61657268 hrea DCD 1634038376 + 0x01007bd4: 65725f64 d_re DCD 1701994340 + 0x01007bd8: 656d7573 sume DCD 1701672307 + 0x01007bdc: 00 . DCB 0 + __FUNCTION__ + 0x01007bdd: 72745f rt_ DCB 114,116,95 + 0x01007be0: 65726874 thre DCD 1701996660 + 0x01007be4: 745f6461 ad_t DCD 1952408673 + 0x01007be8: 6f656d69 imeo DCD 1868918121 + 0x01007bec: 7475 ut DCW 29813 + 0x01007bee: 00 . DCB 0 + .constdata + __FUNCTION__ + 0x01007bef: 70 p DCB 112 + 0x01007bf0: 5f67756c lug_ DCD 1600615788 + 0x01007bf4: 656c6f68 hole DCD 1701605224 + 0x01007bf8: 0073 s. DCW 115 + __FUNCTION__ + 0x01007bfa: 7472 rt DCW 29810 + 0x01007bfc: 7379735f _sys DCD 1937339231 + 0x01007c00: 5f6d6574 tem_ DCD 1601004916 + 0x01007c04: 70616568 heap DCD 1885431144 + 0x01007c08: 696e695f _ini DCD 1768843615 + 0x01007c0c: 0074 t. DCW 116 + __FUNCTION__ + 0x01007c0e: 7472 rt DCW 29810 + 0x01007c10: 6c616d5f _mal DCD 1818324319 + 0x01007c14: 00636f6c loc. DCD 6516588 + __FUNCTION__ + 0x01007c18: 725f7472 rt_r DCD 1918858354 + 0x01007c1c: 6c6c6165 eall DCD 1819042149 + 0x01007c20: 636f oc DCW 25455 + 0x01007c22: 00 . DCB 0 + __FUNCTION__ + 0x01007c23: 72 r DCB 114 + 0x01007c24: 72665f74 t_fr DCD 1919311732 + 0x01007c28: 6565 ee DCW 25957 + 0x01007c2a: 00 . DCB 0 + .constdata + __FUNCTION__ + 0x01007c2b: 55 U DCB 85 + 0x01007c2c: 5f545241 ART_ DCD 1599361601 + 0x01007c30: 6f747541 Auto DCD 1869903169 + 0x01007c34: 776f6c46 Flow DCD 2003790918 + 0x01007c38: 6c727443 Ctrl DCD 1819440195 + 0x01007c3c: 00646d43 Cmd. DCD 6581571 + __FUNCTION__ + 0x01007c40: 54524155 UART DCD 1414676821 + 0x01007c44: 4965445f _DeI DCD 1231373407 + 0x01007c48: 0074696e nit. DCD 7629166 + __FUNCTION__ + 0x01007c4c: 54524155 UART DCD 1414676821 + 0x01007c50: 414d445f _DMA DCD 1095582815 + 0x01007c54: 646e6553 Send DCD 1684956499 + 0x01007c58: 00667542 Buf. DCD 6714690 + __FUNCTION__ + 0x01007c5c: 54524155 UART DCD 1414676821 + 0x01007c60: 696e495f _Ini DCD 1768835423 + 0x01007c64: 0074 t. DCW 116 + __FUNCTION__ + 0x01007c66: 4155 UA DCW 16725 + 0x01007c68: 495f5452 RT_I DCD 1230984274 + 0x01007c6c: 46585273 sRXF DCD 1180193395 + 0x01007c70: 464f4649 IFOF DCD 1179600457 + 0x01007c74: 006c6c75 ull. DCD 7105653 + __FUNCTION__ + 0x01007c78: 54524155 UART DCD 1414676821 + 0x01007c7c: 5273495f _IsR DCD 1383287135 + 0x01007c80: 46494658 XFIF DCD 1179207256 + 0x01007c84: 746f4e4f ONot DCD 1953451599 + 0x01007c88: 74706d45 Empt DCD 1953525061 + 0x01007c8c: 0079 y. DCW 121 + __FUNCTION__ + 0x01007c8e: 4155 UA DCW 16725 + 0x01007c90: 495f5452 RT_I DCD 1230984274 + 0x01007c94: 52415573 sUAR DCD 1380013427 + 0x01007c98: 73754254 TBus DCD 1937064532 + 0x01007c9c: 0079 y. DCW 121 + __FUNCTION__ + 0x01007c9e: 4155 UA DCW 16725 + 0x01007ca0: 495f5452 RT_I DCD 1230984274 + 0x01007ca4: 6e6f4354 TCon DCD 1852785492 + 0x01007ca8: 00676966 fig. DCD 6777190 + __FUNCTION__ + 0x01007cac: 54524155 UART DCD 1414676821 + 0x01007cb0: 6365525f _Rec DCD 1667584607 + 0x01007cb4: 65766965 eive DCD 1702259045 + 0x01007cb8: 61746144 Data DCD 1635017028 + 0x01007cbc: 00 . DCB 0 + __FUNCTION__ + 0x01007cbd: 554152 UAR DCB 85,65,82 + 0x01007cc0: 65525f54 T_Re DCD 1699897172 + 0x01007cc4: 75427663 cvBu DCD 1967289955 + 0x01007cc8: 0066 f. DCW 102 + __FUNCTION__ + 0x01007cca: 4155 UA DCW 16725 + 0x01007ccc: 535f5452 RT_S DCD 1398756434 + 0x01007cd0: 42646e65 endB DCD 1113878117 + 0x01007cd4: 6675 uf DCW 26229 + 0x01007cd6: 00 . DCB 0 + __FUNCTION__ + 0x01007cd7: 55 U DCB 85 + 0x01007cd8: 5f545241 ART_ DCD 1599361601 + 0x01007cdc: 52746553 SetR DCD 1383359827 + 0x01007ce0: 4e544978 xITN DCD 1314146680 + 0x01007ce4: 6d75 um DCW 28021 + 0x01007ce6: 00 . DCB 0 + __FUNCTION__ + 0x01007ce7: 55 U DCB 85 + 0x01007ce8: 5f545241 ART_ DCD 1599361601 + 0x01007cec: 65636552 Rece DCD 1701012818 + 0x01007cf0: 44657669 iveD DCD 1147500137 + 0x01007cf4: 4c617461 ataL DCD 1281455201 + 0x01007cf8: 00006e65 en.. DCD 28261 + .conststring + 0x01007cfc: 6e726157 Warn DCD 1852989783 + 0x01007d00: 3a676e69 ing: DCD 979857001 + 0x01007d04: 65685420 The DCD 1701336096 + 0x01007d08: 69206572 re i DCD 1763730802 + 0x01007d0c: 6f6e2073 s no DCD 1869488243 + 0x01007d10: 6f6e6520 eno DCD 1869505824 + 0x01007d14: 20686775 ugh DCD 543713141 + 0x01007d18: 66667562 buff DCD 1717990754 + 0x01007d1c: 66207265 er f DCD 1713402469 + 0x01007d20: 7320726f or s DCD 1931506287 + 0x01007d24: 6e697661 avin DCD 1852405345 + 0x01007d28: 61642067 g da DCD 1633951847 + 0x01007d2c: 202c6174 ta, DCD 539779444 + 0x01007d30: 61656c70 plea DCD 1634036848 + 0x01007d34: 69206573 se i DCD 1763730803 + 0x01007d38: 6572636e ncre DCD 1701995374 + 0x01007d3c: 20657361 ase DCD 543519585 + 0x01007d40: 20656874 the DCD 543516788 + 0x01007d44: 535f5452 RT_S DCD 1398756434 + 0x01007d48: 41495245 ERIA DCD 1095324229 + 0x01007d4c: 42525f4c L_RB DCD 1112694604 + 0x01007d50: 4655425f _BUF DCD 1179992671 + 0x01007d54: 6f205a53 SZ o DCD 1864391251 + 0x01007d58: 6f697470 ptio DCD 1869182064 + 0x01007d5c: 00002e6e n... DCD 11886 + .conststring + 0x01007d60: 2e2a2d25 %-*. DCD 774516005 + 0x01007d64: 72702073 s pr DCD 1919950963 + 0x01007d68: 73202069 i s DCD 1931485289 + 0x01007d6c: 75746174 tatu DCD 1970561396 + 0x01007d70: 20202073 s DCD 538976371 + 0x01007d74: 73202020 s DCD 1931485216 + 0x01007d78: 20202070 p DCD 538976368 + 0x01007d7c: 74732020 st DCD 1953701920 + 0x01007d80: 206b6361 ack DCD 543908705 + 0x01007d84: 657a6973 size DCD 1702521203 + 0x01007d88: 78616d20 max DCD 2019650848 + 0x01007d8c: 65737520 use DCD 1702065440 + 0x01007d90: 656c2064 d le DCD 1701584996 + 0x01007d94: 74207466 ft t DCD 1948284006 + 0x01007d98: 206b6369 ick DCD 543908713 + 0x01007d9c: 72726520 err DCD 1920099616 + 0x01007da0: 000a726f or.. DCD 684655 + 0x01007da4: 00435452 RTC. DCD 4412498 + 0x01007da8: 7774654e Netw DCD 2004116814 + 0x01007dac: 206b726f ork DCD 543912559 + 0x01007db0: 65746e49 Inte DCD 1702129225 + 0x01007db4: 63616672 rfac DCD 1667327602 + 0x01007db8: 00000065 e... DCD 101 + 0x01007dbc: 2044544d MTD DCD 541348941 + 0x01007dc0: 69766544 Devi DCD 1769366852 + 0x01007dc4: 00006563 ce.. DCD 25955 + 0x01007dc8: 20495053 SPI DCD 541675603 + 0x01007dcc: 69766544 Devi DCD 1769366852 + 0x01007dd0: 00006563 ce.. DCD 25955 + 0x01007dd4: 204e4143 CAN DCD 541999427 + 0x01007dd8: 69766544 Devi DCD 1769366852 + 0x01007ddc: 00006563 ce.. DCD 25955 + 0x01007de0: 70617247 Grap DCD 1885434439 + 0x01007de4: 20636968 hic DCD 543385960 + 0x01007de8: 69766544 Devi DCD 1769366852 + 0x01007dec: 00006563 ce.. DCD 25955 + 0x01007df0: 6e756f53 Soun DCD 1853189971 + 0x01007df4: 65442064 d De DCD 1698963556 + 0x01007df8: 65636976 vice DCD 1701013878 + 0x01007dfc: 00000000 .... DCD 0 + 0x01007e00: 20425355 USB DCD 541217621 + 0x01007e04: 76616c53 Slav DCD 1986096211 + 0x01007e08: 65442065 e De DCD 1698963557 + 0x01007e0c: 65636976 vice DCD 1701013878 + 0x01007e10: 00000000 .... DCD 0 + 0x01007e14: 63756f54 Touc DCD 1668640596 + 0x01007e18: 65442068 h De DCD 1698963560 + 0x01007e1c: 65636976 vice DCD 1701013878 + 0x01007e20: 00000000 .... DCD 0 + 0x01007e24: 636f6c42 Bloc DCD 1668246594 + 0x01007e28: 6544206b k De DCD 1698963563 + 0x01007e2c: 65636976 vice DCD 1701013878 + 0x01007e30: 00000000 .... DCD 0 + 0x01007e34: 74726f50 Port DCD 1953656656 + 0x01007e38: 44206c61 al D DCD 1142975585 + 0x01007e3c: 63697665 evic DCD 1667855973 + 0x01007e40: 00000065 e... DCD 101 + 0x01007e44: 50204d50 PM P DCD 1344294224 + 0x01007e48: 64756573 seud DCD 1685415283 + 0x01007e4c: 6544206f o De DCD 1698963567 + 0x01007e50: 65636976 vice DCD 1701013878 + 0x01007e54: 00000000 .... DCD 0 + 0x01007e58: 656d6954 Time DCD 1701669204 + 0x01007e5c: 65442072 r De DCD 1698963570 + 0x01007e60: 65636976 vice DCD 1701013878 + 0x01007e64: 00000000 .... DCD 0 + 0x01007e68: 72616843 Char DCD 1918986307 + 0x01007e6c: 65746361 acte DCD 1702126433 + 0x01007e70: 65442072 r De DCD 1698963570 + 0x01007e74: 65636976 vice DCD 1701013878 + 0x01007e78: 00000000 .... DCD 0 + 0x01007e7c: 736e6553 Sens DCD 1936614739 + 0x01007e80: 4420726f or D DCD 1142977135 + 0x01007e84: 63697665 evic DCD 1667855973 + 0x01007e88: 00000065 e... DCD 101 + 0x01007e8c: 6373694d Misc DCD 1668507981 + 0x01007e90: 616c6c65 ella DCD 1634495589 + 0x01007e94: 756f656e neou DCD 1970234734 + 0x01007e98: 65442073 s De DCD 1698963571 + 0x01007e9c: 65636976 vice DCD 1701013878 + 0x01007ea0: 00000000 .... DCD 0 + 0x01007ea4: 20796850 Phy DCD 544827472 + 0x01007ea8: 69766544 Devi DCD 1769366852 + 0x01007eac: 00006563 ce.. DCD 25955 + 0x01007eb0: 75636553 Secu DCD 1969448275 + 0x01007eb4: 79746972 rity DCD 2037672306 + 0x01007eb8: 76654420 Dev DCD 1986348064 + 0x01007ebc: 00656369 ice. DCD 6644585 + 0x01007ec0: 65706950 Pipe DCD 1701865808 + 0x01007ec4: 00000000 .... DCD 0 + 0x01007ec8: 6e6b6e55 Unkn DCD 1852534357 + 0x01007ecc: 006e776f own. DCD 7239535 + 0x01007ed0: 20433249 I2C DCD 541274697 + 0x01007ed4: 00737542 Bus. DCD 7566658 + 0x01007ed8: 20425355 USB DCD 541217621 + 0x01007edc: 2047544f OTG DCD 541545551 + 0x01007ee0: 00737542 Bus. DCD 7566658 + 0x01007ee4: 20495053 SPI DCD 541675603 + 0x01007ee8: 00737542 Bus. DCD 7566658 + 0x01007eec: 4f494453 SDIO DCD 1330201683 + 0x01007ef0: 73754220 Bus DCD 1937064480 + 0x01007ef4: 00000000 .... DCD 0 + 0x01007ef8: 20425355 USB DCD 541217621 + 0x01007efc: 74736f48 Host DCD 1953722184 + 0x01007f00: 73754220 Bus DCD 1937064480 + 0x01007f04: 00000000 .... DCD 0 + .conststring + 0x01007f08: 6f5f7472 rt_o DCD 1868526706 + 0x01007f0c: 63656a62 bjec DCD 1667590754 + 0x01007f10: 65675f74 t_ge DCD 1701273460 + 0x01007f14: 79745f74 t_ty DCD 2037669748 + 0x01007f18: 26286570 pe(& DCD 640181616 + 0x01007f1c: 2d6d6573 sem- DCD 762144115 + 0x01007f20: 7261703e >par DCD 1918988350 + 0x01007f24: 2e746e65 ent. DCD 779382373 + 0x01007f28: 65726170 pare DCD 1701994864 + 0x01007f2c: 2029746e nt) DCD 539587694 + 0x01007f30: 52203d3d == R DCD 1377844541 + 0x01007f34: 624f5f54 T_Ob DCD 1649368916 + 0x01007f38: 7463656a ject DCD 1952671082 + 0x01007f3c: 616c435f _Cla DCD 1634485087 + 0x01007f40: 535f7373 ss_S DCD 1398764403 + 0x01007f44: 70616d65 emap DCD 1885433189 + 0x01007f48: 65726f68 hore DCD 1701998440 + 0x01007f4c: 00000000 .... DCD 0 + .conststring + 0x01007f50: 6f5f7472 rt_o DCD 1868526706 + 0x01007f54: 63656a62 bjec DCD 1667590754 + 0x01007f58: 65675f74 t_ge DCD 1701273460 + 0x01007f5c: 79745f74 t_ty DCD 2037669748 + 0x01007f60: 28286570 pe(( DCD 673736048 + 0x01007f64: 6f5f7472 rt_o DCD 1868526706 + 0x01007f68: 63656a62 bjec DCD 1667590754 + 0x01007f6c: 29745f74 t_t) DCD 695492468 + 0x01007f70: 65726874 thre DCD 1701996660 + 0x01007f74: 20296461 ad) DCD 539583585 + 0x01007f78: 52203d3d == R DCD 1377844541 + 0x01007f7c: 624f5f54 T_Ob DCD 1649368916 + 0x01007f80: 7463656a ject DCD 1952671082 + 0x01007f84: 616c435f _Cla DCD 1634485087 + 0x01007f88: 545f7373 ss_T DCD 1415541619 + 0x01007f8c: 61657268 hrea DCD 1634038376 + 0x01007f90: 00000064 d... DCD 100 + .conststring + 0x01007f94: 5f747228 (rt_ DCD 1601466920 + 0x01007f98: 73616275 ubas DCD 1935762037 + 0x01007f9c: 29745f65 e_t) DCD 695492453 + 0x01007fa0: 74722828 ((rt DCD 1953638440 + 0x01007fa4: 6e69755f _uin DCD 1852405087 + 0x01007fa8: 745f3874 t8_t DCD 1952397428 + 0x01007fac: 6d292a20 *)m DCD 1831414304 + 0x01007fb0: 2b206d65 em + DCD 723545445 + 0x01007fb4: 5a495320 SIZ DCD 1514754848 + 0x01007fb8: 5f464f45 EOF_ DCD 1598443333 + 0x01007fbc: 55525453 STRU DCD 1431458899 + 0x01007fc0: 4d5f5443 CT_M DCD 1298093123 + 0x01007fc4: 20294d45 EM) DCD 539577669 + 0x01007fc8: 54522025 % RT DCD 1414668325 + 0x01007fcc: 494c415f _ALI DCD 1229734239 + 0x01007fd0: 535f4e47 GN_S DCD 1398754887 + 0x01007fd4: 20455a49 IZE DCD 541416009 + 0x01007fd8: 30203d3d == 0 DCD 807419197 + 0x01007fdc: 00000000 .... DCD 0 + 0x01007fe0: 5f747228 (rt_ DCD 1601466920 + 0x01007fe4: 746e6975 uint DCD 1953393013 + 0x01007fe8: 20745f38 8_t DCD 544497464 + 0x01007fec: 6d72292a *)rm DCD 1836198186 + 0x01007ff0: 3e206d65 em > DCD 1042312549 + 0x01007ff4: 7228203d = (r DCD 1915232317 + 0x01007ff8: 69755f74 t_ui DCD 1769299828 + 0x01007ffc: 5f38746e nt8_ DCD 1597535342 + 0x01008000: 292a2074 t *) DCD 690626676 + 0x01008004: 70616568 heap DCD 1885431144 + 0x01008008: 7274705f _ptr DCD 1920233567 + 0x0100800c: 20262620 && DCD 539371040 + 0x01008010: 5f747228 (rt_ DCD 1601466920 + 0x01008014: 746e6975 uint DCD 1953393013 + 0x01008018: 20745f38 8_t DCD 544497464 + 0x0100801c: 6d72292a *)rm DCD 1836198186 + 0x01008020: 3c206d65 em < DCD 1008758117 + 0x01008024: 74722820 (rt DCD 1953638432 + 0x01008028: 6e69755f _uin DCD 1852405087 + 0x0100802c: 745f3874 t8_t DCD 1952397428 + 0x01008030: 68292a20 *)h DCD 1747528224 + 0x01008034: 5f706165 eap_ DCD 1601200485 + 0x01008038: 00646e65 end. DCD 6581861 + 0x0100803c: 5f747228 (rt_ DCD 1601466920 + 0x01008040: 73616275 ubas DCD 1935762037 + 0x01008044: 29745f65 e_t) DCD 695492453 + 0x01008048: 206d656d mem DCD 544040301 + 0x0100804c: 4953202b + SI DCD 1230184491 + 0x01008050: 464f455a ZEOF DCD 1179600218 + 0x01008054: 5254535f _STR DCD 1381258079 + 0x01008058: 5f544355 UCT_ DCD 1599357781 + 0x0100805c: 204d454d MEM DCD 541934925 + 0x01008060: 6973202b + si DCD 1769152555 + 0x01008064: 3c20657a ze < DCD 1008756090 + 0x01008068: 7228203d = (r DCD 1915232317 + 0x0100806c: 62755f74 t_ub DCD 1651859316 + 0x01008070: 5f657361 ase_ DCD 1600484193 + 0x01008074: 65682974 t)he DCD 1701325172 + 0x01008078: 655f7061 ap_e DCD 1700753505 + 0x0100807c: 646e nd DCW 25710 + 0x0100807e: 00 . DCB 0 + .rodata.name + __fsym_help_name + 0x0100807f: 68 h DCB 104 + 0x01008080: 00706c65 elp. DCD 7367781 + __fsym_help_desc + 0x01008084: 2d205452 RT - DCD 757093458 + 0x01008088: 72685420 Thr DCD 1919439904 + 0x0100808c: 20646165 ead DCD 543449445 + 0x01008090: 6c656873 shel DCD 1818585203 + 0x01008094: 6568206c l he DCD 1701322860 + 0x01008098: 002e706c lp.. DCD 3043436 + __fsym_ps_name + 0x0100809c: 7370 ps DCW 29552 + 0x0100809e: 00 . DCB 0 + __fsym_ps_desc + 0x0100809f: 4c L DCB 76 + 0x010080a0: 20747369 ist DCD 544502633 + 0x010080a4: 65726874 thre DCD 1701996660 + 0x010080a8: 20736461 ads DCD 544433249 + 0x010080ac: 74206e69 in t DCD 1948282473 + 0x010080b0: 73206568 he s DCD 1931502952 + 0x010080b4: 65747379 yste DCD 1702130553 + 0x010080b8: 2e6d m. DCW 11885 + 0x010080ba: 00 . DCB 0 + __fsym_free_name + 0x010080bb: 66 f DCB 102 + 0x010080bc: 00656572 ree. DCD 6645106 + __fsym_free_desc + 0x010080c0: 776f6853 Show DCD 2003789907 + 0x010080c4: 65687420 the DCD 1701344288 + 0x010080c8: 6d656d20 mem DCD 1835363616 + 0x010080cc: 2079726f ory DCD 544830063 + 0x010080d0: 67617375 usag DCD 1734439797 + 0x010080d4: 6e692065 e in DCD 1852383333 + 0x010080d8: 65687420 the DCD 1701344288 + 0x010080dc: 73797320 sys DCD 1937339168 + 0x010080e0: 2e6d6574 tem. DCD 778921332 + 0x010080e4: 00 . DCB 0 + .rodata.name + __fsym_hello_name + 0x010080e5: 68656c hel DCB 104,101,108 + 0x010080e8: 6f6c lo DCW 28524 + 0x010080ea: 00 . DCB 0 + __fsym_hello_desc + 0x010080eb: 73 s DCB 115 + 0x010080ec: 68207961 ay h DCD 1746958689 + 0x010080f0: 6f6c6c65 ello DCD 1869376613 + 0x010080f4: 726f7720 wor DCD 1919907616 + 0x010080f8: 646c ld DCW 25708 + 0x010080fa: 00 . DCB 0 + __fsym_clear_name + 0x010080fb: 63 c DCB 99 + 0x010080fc: 7261656c lear DCD 1918985580 + 0x01008100: 00 . DCB 0 + __fsym_clear_desc + 0x01008101: 636c65 cle DCB 99,108,101 + 0x01008104: 74207261 ar t DCD 1948283489 + 0x01008108: 74206568 he t DCD 1948280168 + 0x0100810c: 696d7265 ermi DCD 1768780389 + 0x01008110: 206c616e nal DCD 543973742 + 0x01008114: 65726373 scre DCD 1701995379 + 0x01008118: 6e65 en DCW 28261 + 0x0100811a: 00 . DCB 0 + __fsym_version_name + 0x0100811b: 76 v DCB 118 + 0x0100811c: 69737265 ersi DCD 1769173605 + 0x01008120: 6e6f on DCW 28271 + 0x01008122: 00 . DCB 0 + __fsym_version_desc + 0x01008123: 73 s DCB 115 + 0x01008124: 20776f68 how DCD 544698216 + 0x01008128: 2d205452 RT - DCD 757093458 + 0x0100812c: 72685420 Thr DCD 1919439904 + 0x01008130: 20646165 ead DCD 543449445 + 0x01008134: 73726576 vers DCD 1936876918 + 0x01008138: 206e6f69 ion DCD 544108393 + 0x0100813c: 6f666e69 info DCD 1868983913 + 0x01008140: 74616d72 rmat DCD 1952542066 + 0x01008144: 006e6f69 ion. DCD 7237481 + __fsym_list_thread_name + 0x01008148: 7473696c list DCD 1953720684 + 0x0100814c: 7268745f _thr DCD 1919448159 + 0x01008150: 00646165 ead. DCD 6578533 + __fsym_list_thread_desc + 0x01008154: 7473696c list DCD 1953720684 + 0x01008158: 72687420 thr DCD 1919448096 + 0x0100815c: 00646165 ead. DCD 6578533 + __fsym_list_sem_name + 0x01008160: 7473696c list DCD 1953720684 + 0x01008164: 6d65735f _sem DCD 1835365215 + 0x01008168: 00 . DCB 0 + __fsym_list_sem_desc + 0x01008169: 6c6973 lis DCB 108,105,115 + 0x0100816c: 65732074 t se DCD 1702043764 + 0x01008170: 6870616d maph DCD 1752195437 + 0x01008174: 2065726f ore DCD 543519343 + 0x01008178: 73206e69 in s DCD 1931505257 + 0x0100817c: 65747379 yste DCD 1702130553 + 0x01008180: 006d m. DCW 109 + __fsym_list_event_name + 0x01008182: 696c li DCW 26988 + 0x01008184: 655f7473 st_e DCD 1700754547 + 0x01008188: 746e6576 vent DCD 1953391990 + 0x0100818c: 00 . DCB 0 + __fsym_list_event_desc + 0x0100818d: 6c6973 lis DCB 108,105,115 + 0x01008190: 76652074 t ev DCD 1986338932 + 0x01008194: 20746e65 ent DCD 544501349 + 0x01008198: 73206e69 in s DCD 1931505257 + 0x0100819c: 65747379 yste DCD 1702130553 + 0x010081a0: 006d m. DCW 109 + __fsym_list_mutex_name + 0x010081a2: 696c li DCW 26988 + 0x010081a4: 6d5f7473 st_m DCD 1834972275 + 0x010081a8: 78657475 utex DCD 2019914869 + 0x010081ac: 00 . DCB 0 + __fsym_list_mutex_desc + 0x010081ad: 6c6973 lis DCB 108,105,115 + 0x010081b0: 756d2074 t mu DCD 1970086004 + 0x010081b4: 20786574 tex DCD 544761204 + 0x010081b8: 73206e69 in s DCD 1931505257 + 0x010081bc: 65747379 yste DCD 1702130553 + 0x010081c0: 006d m. DCW 109 + __fsym_list_mailbox_name + 0x010081c2: 696c li DCW 26988 + 0x010081c4: 6d5f7473 st_m DCD 1834972275 + 0x010081c8: 626c6961 ailb DCD 1651272033 + 0x010081cc: 786f ox DCW 30831 + 0x010081ce: 00 . DCB 0 + __fsym_list_mailbox_desc + 0x010081cf: 6c l DCB 108 + 0x010081d0: 20747369 ist DCD 544502633 + 0x010081d4: 6c69616d mail DCD 1818845549 + 0x010081d8: 786f6220 box DCD 2020565536 + 0x010081dc: 206e6920 in DCD 544106784 + 0x010081e0: 74737973 syst DCD 1953724787 + 0x010081e4: 6d65 em DCW 28005 + 0x010081e6: 00 . DCB 0 + __fsym_list_msgqueue_name + 0x010081e7: 6c l DCB 108 + 0x010081e8: 5f747369 ist_ DCD 1601467241 + 0x010081ec: 7167736d msgq DCD 1902605165 + 0x010081f0: 65756575 ueue DCD 1702192501 + 0x010081f4: 00 . DCB 0 + __fsym_list_msgqueue_desc + 0x010081f5: 6c6973 lis DCB 108,105,115 + 0x010081f8: 656d2074 t me DCD 1701650548 + 0x010081fc: 67617373 ssag DCD 1734439795 + 0x01008200: 75712065 e qu DCD 1970348133 + 0x01008204: 20657565 eue DCD 543520101 + 0x01008208: 73206e69 in s DCD 1931505257 + 0x0100820c: 65747379 yste DCD 1702130553 + 0x01008210: 006d m. DCW 109 + __fsym_list_memheap_name + 0x01008212: 696c li DCW 26988 + 0x01008214: 6d5f7473 st_m DCD 1834972275 + 0x01008218: 65686d65 emhe DCD 1701342565 + 0x0100821c: 7061 ap DCW 28769 + 0x0100821e: 00 . DCB 0 + __fsym_list_memheap_desc + 0x0100821f: 6c l DCB 108 + 0x01008220: 20747369 ist DCD 544502633 + 0x01008224: 6f6d656d memo DCD 1869440365 + 0x01008228: 68207972 ry h DCD 1746958706 + 0x0100822c: 20706165 eap DCD 544235877 + 0x01008230: 73206e69 in s DCD 1931505257 + 0x01008234: 65747379 yste DCD 1702130553 + 0x01008238: 006d m. DCW 109 + __fsym_list_mempool_name + 0x0100823a: 696c li DCW 26988 + 0x0100823c: 6d5f7473 st_m DCD 1834972275 + 0x01008240: 6f706d65 empo DCD 1869639013 + 0x01008244: 6c6f ol DCW 27759 + 0x01008246: 00 . DCB 0 + __fsym_list_mempool_desc + 0x01008247: 6c l DCB 108 + 0x01008248: 20747369 ist DCD 544502633 + 0x0100824c: 6f6d656d memo DCD 1869440365 + 0x01008250: 70207972 ry p DCD 1881176434 + 0x01008254: 206c6f6f ool DCD 543977327 + 0x01008258: 73206e69 in s DCD 1931505257 + 0x0100825c: 65747379 yste DCD 1702130553 + 0x01008260: 006d m. DCW 109 + __fsym_list_timer_name + 0x01008262: 696c li DCW 26988 + 0x01008264: 745f7473 st_t DCD 1952412787 + 0x01008268: 72656d69 imer DCD 1919249769 + 0x0100826c: 00 . DCB 0 + __fsym_list_timer_desc + 0x0100826d: 6c6973 lis DCB 108,105,115 + 0x01008270: 69742074 t ti DCD 1769218164 + 0x01008274: 2072656d mer DCD 544367981 + 0x01008278: 73206e69 in s DCD 1931505257 + 0x0100827c: 65747379 yste DCD 1702130553 + 0x01008280: 006d m. DCW 109 + __fsym_list_device_name + 0x01008282: 696c li DCW 26988 + 0x01008284: 645f7473 st_d DCD 1683977331 + 0x01008288: 63697665 evic DCD 1667855973 + 0x0100828c: 0065 e. DCW 101 + __fsym_list_device_desc + 0x0100828e: 696c li DCW 26988 + 0x01008290: 64207473 st d DCD 1679848563 + 0x01008294: 63697665 evic DCD 1667855973 + 0x01008298: 6e692065 e in DCD 1852383333 + 0x0100829c: 73797320 sys DCD 1937339168 + 0x010082a0: 006d6574 tem. DCD 7169396 + __fsym_list_name + 0x010082a4: 7473696c list DCD 1953720684 + 0x010082a8: 00 . DCB 0 + __fsym_list_desc + 0x010082a9: 6c6973 lis DCB 108,105,115 + 0x010082ac: 6c612074 t al DCD 1818304628 + 0x010082b0: 6f63206c l co DCD 1868767340 + 0x010082b4: 6e616d6d mman DCD 1851878765 + 0x010082b8: 69207364 ds i DCD 1763734372 + 0x010082bc: 7973206e n sy DCD 2037588078 + 0x010082c0: 6d657473 stem DCD 1835365491 + 0x010082c4: 00 . DCB 0 + .rodata.name + __fsym_memheaptrace_name + 0x010082c5: 6d656d mem DCB 109,101,109 + 0x010082c8: 70616568 heap DCD 1885431144 + 0x010082cc: 63617274 trac DCD 1667330676 + 0x010082d0: 0065 e. DCW 101 + __fsym_memheaptrace_desc + 0x010082d2: 7564 du DCW 30052 + 0x010082d4: 6d20706d mp m DCD 1830842477 + 0x010082d8: 726f6d65 emor DCD 1919905125 + 0x010082dc: 72742079 y tr DCD 1920213113 + 0x010082e0: 20656361 ace DCD 543515489 + 0x010082e4: 6f666e69 info DCD 1868983913 + 0x010082e8: 74616d72 rmat DCD 1952542066 + 0x010082ec: 006e6f69 ion. DCD 7237481 + .rti_fn.0 + __tagsym$$used + __rt_init_rti_start + 0x010082f0: 01006c6b kl.. DCD 16804971 + .rti_fn.0.end + __tagsym$$used + __rt_init_rti_board_start + 0x010082f4: 01006c63 cl.. DCD 16804963 + .rti_fn.1 + __tagsym$$used + __rt_init_rt_hw_pin_init + 0x010082f8: 0100420d .B.. DCD 16794125 + .rti_fn.1 + __tagsym$$used + __rt_init_rt_hw_uart_init + 0x010082fc: 010043e9 .C.. DCD 16794601 + .rti_fn.1.end + __tagsym$$used + __rt_init_rti_board_end + 0x01008300: 01006c5f _l.. DCD 16804959 + .rti_fn.6 + __tagsym$$used + __rt_init_finsh_system_init + 0x01008304: 01001a29 )... DCD 16783913 + .rti_fn.6.end + __tagsym$$used + __rt_init_rti_end + 0x01008308: 01006c67 gl.. DCD 16804967 + FSymTab + __tagsym$$used + FSymTab$$Base + __fsym_help + 0x0100830c: 0100807f .... DCD 16810111 + 0x01008310: 01008084 .... DCD 16810116 + 0x01008314: 01003191 .1.. DCD 16789905 + __tagsym$$used + __fsym_ps + 0x01008318: 0100809c .... DCD 16810140 + 0x0100831c: 0100809f .... DCD 16810143 + 0x01008320: 010017b3 .... DCD 16783283 + __tagsym$$used + __fsym_free + 0x01008324: 010080bb .... DCD 16810171 + 0x01008328: 010080c0 .... DCD 16810176 + 0x0100832c: 010017a5 .... DCD 16783269 + FSymTab + __tagsym$$used + __fsym_hello + 0x01008330: 010080e5 .... DCD 16810213 + 0x01008334: 010080eb .... DCD 16810219 + 0x01008338: 010020c5 . .. DCD 16785605 + __tagsym$$used + __fsym_clear + 0x0100833c: 010080fb .... DCD 16810235 + 0x01008340: 01008101 .... DCD 16810241 + 0x01008344: 01001791 .... DCD 16783249 + __tagsym$$used + __fsym_version + 0x01008348: 0100811b .... DCD 16810267 + 0x0100834c: 01008123 #... DCD 16810275 + 0x01008350: 01006e59 Yn.. DCD 16805465 + __tagsym$$used + __fsym_list_thread + 0x01008354: 01008148 H... DCD 16810312 + 0x01008358: 01008154 T... DCD 16810324 + 0x0100835c: 01002c51 Q,.. DCD 16788561 + __tagsym$$used + __fsym_list_sem + 0x01008360: 01008160 `... DCD 16810336 + 0x01008364: 01008169 i... DCD 16810345 + 0x01008368: 01002b19 .+.. DCD 16788249 + __tagsym$$used + __fsym_list_event + 0x0100836c: 01008182 .... DCD 16810370 + 0x01008370: 0100818d .... DCD 16810381 + 0x01008374: 01002261 a".. DCD 16786017 + __tagsym$$used + __fsym_list_mutex + 0x01008378: 010081a2 .... DCD 16810402 + 0x0100837c: 010081ad .... DCD 16810413 + 0x01008380: 01002a0d .*.. DCD 16787981 + __tagsym$$used + __fsym_list_mailbox + 0x01008384: 010081c2 .... DCD 16810434 + 0x01008388: 010081cf .... DCD 16810447 + 0x0100838c: 01002465 e$.. DCD 16786533 + __tagsym$$used + __fsym_list_msgqueue + 0x01008390: 010081e7 .... DCD 16810471 + 0x01008394: 010081f5 .... DCD 16810485 + 0x01008398: 010028c9 .(.. DCD 16787657 + __tagsym$$used + __fsym_list_memheap + 0x0100839c: 01008212 .... DCD 16810514 + 0x010083a0: 0100821f .... DCD 16810527 + 0x010083a4: 01002639 9&.. DCD 16787001 + __tagsym$$used + __fsym_list_mempool + 0x010083a8: 0100823a :... DCD 16810554 + 0x010083ac: 01008247 G... DCD 16810567 + 0x010083b0: 01002755 U'.. DCD 16787285 + __tagsym$$used + __fsym_list_timer + 0x010083b4: 01008262 b... DCD 16810594 + 0x010083b8: 0100826d m... DCD 16810605 + 0x010083bc: 01002e3d =... DCD 16789053 + __tagsym$$used + __fsym_list_device + 0x010083c0: 01008282 .... DCD 16810626 + 0x010083c4: 0100828e .... DCD 16810638 + 0x010083c8: 0100214d M!.. DCD 16785741 + __tagsym$$used + __fsym_list + 0x010083cc: 010082a4 .... DCD 16810660 + 0x010083d0: 010082a9 .... DCD 16810665 + 0x010083d4: 010020e5 . .. DCD 16785637 + FSymTab + __tagsym$$used + __fsym_memheaptrace + 0x010083d8: 010082c5 .... DCD 16810693 + 0x010083dc: 010082d2 .... DCD 16810706 + 0x010083e0: 01002fe1 ./.. DCD 16789473 + FSymTab$$Limit + Region$$Table$$Base + 0x010083e4: 01008404 .... DCD 16811012 + 0x010083e8: 00020000 .... DCD 131072 + 0x010083ec: 00000158 X... DCD 344 + 0x010083f0: 01000a32 2... DCD 16779826 + 0x010083f4: 01008468 h... DCD 16811112 + 0x010083f8: 00020158 X... DCD 131416 + 0x010083fc: 00000db8 .... DCD 3512 + 0x01008400: 01000444 D... DCD 16778308 + Region$$Table$$Limit + +** Section #5 'RW_IRAM1' (SHT_PROGBITS) [SHF_ALLOC + SHF_WRITE] + Size : 100 bytes (alignment 4) + Address: 0x00020000 + + +** Section #6 'RW_IRAM1' (SHT_NOBITS) [SHF_ALLOC + SHF_WRITE] + Size : 3512 bytes (alignment 16) + Address: 0x00020158 + + +** Section #7 '.debug_abbrev' (SHT_PROGBITS) + Size : 1476 bytes + + +** Section #8 '.debug_frame' (SHT_PROGBITS) + Size : 7560 bytes + + +** Section #9 '.debug_info' (SHT_PROGBITS) + Size : 124416 bytes + + +** Section #10 '.debug_line' (SHT_PROGBITS) + Size : 47496 bytes + + +** Section #11 '.debug_loc' (SHT_PROGBITS) + Size : 29452 bytes + + +** Section #12 '.debug_macinfo' (SHT_PROGBITS) + Size : 48792 bytes + + +** Section #13 '.debug_pubnames' (SHT_PROGBITS) + Size : 10286 bytes + + +** Section #14 '.symtab' (SHT_SYMTAB) + Size : 23392 bytes (alignment 4) + String table #15 '.strtab' + Last local symbol no. 1064 + + +** Section #15 '.strtab' (SHT_STRTAB) + Size : 15520 bytes + + +** Section #16 '.note' (SHT_NOTE) + Size : 40 bytes (alignment 4) + + +** Section #17 '.comment' (SHT_PROGBITS) + Size : 42332 bytes + + +** Section #18 '.shstrtab' (SHT_STRTAB) + Size : 184 bytes + + +address size variable name type +0x00020154 0x4 SystickCount tick + +address size variable name type +0x000205a4 0x400 uart0_DMA_buf array[1024] of uint8_t + +address size variable name type +0x000209a4 0x400 uart1_DMA_buf array[1024] of uint8_t + +address size variable name type +0x00020140 0x4 heap_end pointer to heap_mem + +address size variable name type +0x0002013c 0x4 heap_ptr pointer to rt_uint8_t + +address size variable name type +0x00020584 0x20 heap_sem rt_semaphore +0x00020584 0x1c heap_sem.parent rt_ipc_object +0x00020584 0x14 heap_sem.parent.parent rt_object +0x00020584 0x8 heap_sem.parent.parent.name array[8] of char +0x0002058c 0x1 heap_sem.parent.parent.type rt_uint8_t +0x0002058d 0x1 * heap_sem.parent.parent.flag rt_uint8_t +0x00020590 0x8 heap_sem.parent.parent.list rt_list_t +0x00020590 0x4 heap_sem.parent.parent.list.next pointer to rt_list_node +0x00020594 0x4 heap_sem.parent.parent.list.prev pointer to rt_list_node +0x00020598 0x8 heap_sem.parent.suspend_thread rt_list_t +0x00020598 0x4 heap_sem.parent.suspend_thread.next pointer to rt_list_node +0x0002059c 0x4 heap_sem.parent.suspend_thread.prev pointer to rt_list_node +0x000205a0 0x2 heap_sem.value rt_uint16_t +0x000205a2 0x2 heap_sem.reserved rt_uint16_t + +address size variable name type +0x00020144 0x4 lfree pointer to heap_mem + +address size variable name type +0x00020150 0x4 max_mem rt_size_t + +address size variable name type +0x00020148 0x4 mem_size_aligned rt_size_t + +address size variable name type +0x00020138 0x4 rt_free_hook pointer to function + +address size variable name type +0x00020134 0x4 rt_malloc_hook pointer to function + +address size variable name type +0x0002014c 0x4 used_mem rt_size_t + +address size variable name type +0x00020130 0x4 rt_thread_inited_hook pointer to function + +address size variable name type +0x0002012c 0x4 rt_thread_resume_hook pointer to function + +address size variable name type +0x00020128 0x4 rt_thread_suspend_hook pointer to function + +address size variable name type +0x0002011c 0x4 rt_interrupt_enter_hook pointer to function + +address size variable name type +0x00020120 0x4 rt_interrupt_leave_hook pointer to function + +address size variable name type +0x00020124 0x1 rt_interrupt_nest volatile rt_uint8_t + +address size variable name type +0x010083d8 0xc __fsym_memheaptrace const finsh_syscall +0x010083d8 0x4 __fsym_memheaptrace.name pointer to const char +0x010083dc 0x4 __fsym_memheaptrace.desc pointer to const char +0x010083e0 0x4 __fsym_memheaptrace.func syscall_func + +address size variable name type +0x010082d2 0x1e __fsym_memheaptrace_desc array[30] of const char + +address size variable name type +0x010082c5 0xd __fsym_memheaptrace_name array[13] of const char + +address size variable name type +0x00020068 0xa0 _object_container array[10] of rt_object_information + +address size variable name type +0x00020108 0x4 rt_object_attach_hook pointer to function + +address size variable name type +0x0002010c 0x4 rt_object_detach_hook pointer to function + +address size variable name type +0x00020118 0x4 rt_object_put_hook pointer to function + +address size variable name type +0x00020114 0x4 rt_object_take_hook pointer to function + +address size variable name type +0x00020110 0x4 rt_object_trytake_hook pointer to function + +address size variable name type +0x00020054 0x8 _timer_list array[1] of rt_list_t + +address size variable name type +0x0002005c 0x4 rt_timer_enter_hook pointer to function + +address size variable name type +0x00020060 0x4 rt_timer_exit_hook pointer to function + +address size variable name type +0x010076b3 0x100 __lowest_bit_bitmap array[256] of const rt_uint8_t + +address size variable name type +0x00020048 0x4 __rt_errno volatile int + +address size variable name type +0x0002004c 0x4 _console_device rt_device_t + +address size variable name type +0x00020050 0x4 rt_assert_hook pointer to function + +address size variable name type +0x00020044 0x4 rt_tick volatile rt_tick_t + +address size variable name type +0x0002003c 0x8 _rt_thread_defunct rt_list_t +0x0002003c 0x4 _rt_thread_defunct.next pointer to rt_list_node +0x00020040 0x4 _rt_thread_defunct.prev pointer to rt_list_node + +address size variable name type +0x00020374 0x80 idle array[1] of rt_thread + +address size variable name type +0x000204f4 0x10 idle_hook_list array[4] of pointer to function + +address size variable name type +0x000203f4 0x100 rt_thread_stack array[1] of array[256] of rt_uint8_t + +address size variable name type +0x00020030 0x1 rt_current_priority rt_uint8_t + +address size variable name type +0x0002002c 0x4 rt_current_thread pointer to rt_thread + +address size variable name type +0x00020034 0x4 rt_scheduler_hook pointer to function + +address size variable name type +0x00020028 0x2 rt_scheduler_lock_nest rt_int16_t + +address size variable name type +0x00020038 0x4 rt_scheduler_switch_hook pointer to function + +address size variable name type +0x00020274 0x100 rt_thread_priority_table array[32] of rt_list_t + +address size variable name type +0x00020024 0x4 rt_thread_ready_priority_group rt_uint32_t + +address size variable name type +0x01008300 0x4 __rt_init_rti_board_end const init_fn_t + +address size variable name type +0x010082f4 0x4 __rt_init_rti_board_start const init_fn_t + +address size variable name type +0x01008308 0x4 __rt_init_rti_end const init_fn_t + +address size variable name type +0x010082f0 0x4 __rt_init_rti_start const init_fn_t + +address size variable name type +0x0100833c 0xc __fsym_clear const finsh_syscall +0x0100833c 0x4 __fsym_clear.name pointer to const char +0x01008340 0x4 __fsym_clear.desc pointer to const char +0x01008344 0x4 __fsym_clear.func syscall_func + +address size variable name type +0x01008101 0x1a __fsym_clear_desc array[26] of const char + +address size variable name type +0x010080fb 0x6 __fsym_clear_name array[6] of const char + +address size variable name type +0x01008330 0xc __fsym_hello const finsh_syscall +0x01008330 0x4 __fsym_hello.name pointer to const char +0x01008334 0x4 __fsym_hello.desc pointer to const char +0x01008338 0x4 __fsym_hello.func syscall_func + +address size variable name type +0x010080eb 0x10 __fsym_hello_desc array[16] of const char + +address size variable name type +0x010080e5 0x6 __fsym_hello_name array[6] of const char + +address size variable name type +0x010083cc 0xc __fsym_list const finsh_syscall +0x010083cc 0x4 __fsym_list.name pointer to const char +0x010083d0 0x4 __fsym_list.desc pointer to const char +0x010083d4 0x4 __fsym_list.func syscall_func + +address size variable name type +0x010082a9 0x1c __fsym_list_desc array[28] of const char + +address size variable name type +0x010083c0 0xc __fsym_list_device const finsh_syscall +0x010083c0 0x4 __fsym_list_device.name pointer to const char +0x010083c4 0x4 __fsym_list_device.desc pointer to const char +0x010083c8 0x4 __fsym_list_device.func syscall_func + +address size variable name type +0x0100828e 0x16 __fsym_list_device_desc array[22] of const char + +address size variable name type +0x01008282 0xc __fsym_list_device_name array[12] of const char + +address size variable name type +0x0100836c 0xc __fsym_list_event const finsh_syscall +0x0100836c 0x4 __fsym_list_event.name pointer to const char +0x01008370 0x4 __fsym_list_event.desc pointer to const char +0x01008374 0x4 __fsym_list_event.func syscall_func + +address size variable name type +0x0100818d 0x15 __fsym_list_event_desc array[21] of const char + +address size variable name type +0x01008182 0xb __fsym_list_event_name array[11] of const char + +address size variable name type +0x01008384 0xc __fsym_list_mailbox const finsh_syscall +0x01008384 0x4 __fsym_list_mailbox.name pointer to const char +0x01008388 0x4 __fsym_list_mailbox.desc pointer to const char +0x0100838c 0x4 __fsym_list_mailbox.func syscall_func + +address size variable name type +0x010081cf 0x18 __fsym_list_mailbox_desc array[24] of const char + +address size variable name type +0x010081c2 0xd __fsym_list_mailbox_name array[13] of const char + +address size variable name type +0x0100839c 0xc __fsym_list_memheap const finsh_syscall +0x0100839c 0x4 __fsym_list_memheap.name pointer to const char +0x010083a0 0x4 __fsym_list_memheap.desc pointer to const char +0x010083a4 0x4 __fsym_list_memheap.func syscall_func + +address size variable name type +0x0100821f 0x1b __fsym_list_memheap_desc array[27] of const char + +address size variable name type +0x01008212 0xd __fsym_list_memheap_name array[13] of const char + +address size variable name type +0x010083a8 0xc __fsym_list_mempool const finsh_syscall +0x010083a8 0x4 __fsym_list_mempool.name pointer to const char +0x010083ac 0x4 __fsym_list_mempool.desc pointer to const char +0x010083b0 0x4 __fsym_list_mempool.func syscall_func + +address size variable name type +0x01008247 0x1b __fsym_list_mempool_desc array[27] of const char + +address size variable name type +0x0100823a 0xd __fsym_list_mempool_name array[13] of const char + +address size variable name type +0x01008390 0xc __fsym_list_msgqueue const finsh_syscall +0x01008390 0x4 __fsym_list_msgqueue.name pointer to const char +0x01008394 0x4 __fsym_list_msgqueue.desc pointer to const char +0x01008398 0x4 __fsym_list_msgqueue.func syscall_func + +address size variable name type +0x010081f5 0x1d __fsym_list_msgqueue_desc array[29] of const char + +address size variable name type +0x010081e7 0xe __fsym_list_msgqueue_name array[14] of const char + +address size variable name type +0x01008378 0xc __fsym_list_mutex const finsh_syscall +0x01008378 0x4 __fsym_list_mutex.name pointer to const char +0x0100837c 0x4 __fsym_list_mutex.desc pointer to const char +0x01008380 0x4 __fsym_list_mutex.func syscall_func + +address size variable name type +0x010081ad 0x15 __fsym_list_mutex_desc array[21] of const char + +address size variable name type +0x010081a2 0xb __fsym_list_mutex_name array[11] of const char + +address size variable name type +0x010082a4 0x5 __fsym_list_name array[5] of const char + +address size variable name type +0x01008360 0xc __fsym_list_sem const finsh_syscall +0x01008360 0x4 __fsym_list_sem.name pointer to const char +0x01008364 0x4 __fsym_list_sem.desc pointer to const char +0x01008368 0x4 __fsym_list_sem.func syscall_func + +address size variable name type +0x01008169 0x19 __fsym_list_sem_desc array[25] of const char + +address size variable name type +0x01008160 0x9 __fsym_list_sem_name array[9] of const char + +address size variable name type +0x01008354 0xc __fsym_list_thread const finsh_syscall +0x01008354 0x4 __fsym_list_thread.name pointer to const char +0x01008358 0x4 __fsym_list_thread.desc pointer to const char +0x0100835c 0x4 __fsym_list_thread.func syscall_func + +address size variable name type +0x01008154 0xc __fsym_list_thread_desc array[12] of const char + +address size variable name type +0x01008148 0xc __fsym_list_thread_name array[12] of const char + +address size variable name type +0x010083b4 0xc __fsym_list_timer const finsh_syscall +0x010083b4 0x4 __fsym_list_timer.name pointer to const char +0x010083b8 0x4 __fsym_list_timer.desc pointer to const char +0x010083bc 0x4 __fsym_list_timer.func syscall_func + +address size variable name type +0x0100826d 0x15 __fsym_list_timer_desc array[21] of const char + +address size variable name type +0x01008262 0xb __fsym_list_timer_name array[11] of const char + +address size variable name type +0x01008348 0xc __fsym_version const finsh_syscall +0x01008348 0x4 __fsym_version.name pointer to const char +0x0100834c 0x4 __fsym_version.desc pointer to const char +0x01008350 0x4 __fsym_version.func syscall_func + +address size variable name type +0x01008123 0x25 __fsym_version_desc array[37] of const char + +address size variable name type +0x0100811b 0x8 __fsym_version_name array[8] of const char + +address size variable name type +0x01007520 0x64 device_type_str array[25] of const pointer to char + +address size variable name type +0x01008324 0xc __fsym_free const finsh_syscall +0x01008324 0x4 __fsym_free.name pointer to const char +0x01008328 0x4 __fsym_free.desc pointer to const char +0x0100832c 0x4 __fsym_free.func syscall_func + +address size variable name type +0x010080c0 0x25 __fsym_free_desc array[37] of const char + +address size variable name type +0x010080bb 0x5 __fsym_free_name array[5] of const char + +address size variable name type +0x0100830c 0xc __fsym_help const finsh_syscall +0x0100830c 0x4 __fsym_help.name pointer to const char +0x01008310 0x4 __fsym_help.desc pointer to const char +0x01008314 0x4 __fsym_help.func syscall_func + +address size variable name type +0x01008084 0x18 __fsym_help_desc array[24] of const char + +address size variable name type +0x0100807f 0x5 __fsym_help_name array[5] of const char + +address size variable name type +0x01008318 0xc __fsym_ps const finsh_syscall +0x01008318 0x4 __fsym_ps.name pointer to const char +0x0100831c 0x4 __fsym_ps.desc pointer to const char +0x01008320 0x4 __fsym_ps.func syscall_func + +address size variable name type +0x0100809f 0x1c __fsym_ps_desc array[28] of const char + +address size variable name type +0x0100809c 0x3 __fsym_ps_name array[3] of const char + +address size variable name type +0x01008304 0x4 __rt_init_finsh_system_init const init_fn_t + +address size variable name type +0x00020014 0x4 _syscall_table_begin pointer to finsh_syscall + +address size variable name type +0x00020018 0x4 _syscall_table_end pointer to finsh_syscall + +address size variable name type +0x00020020 0x4 finsh_prompt_custom pointer to char + +address size variable name type +0x0002001c 0x4 shell pointer to finsh_shell + +address size variable name type +0x010082fc 0x4 __rt_init_rt_hw_uart_init const init_fn_t + +address size variable name type +0x0002019c 0x54 serial0 rt_serial_device +0x0002019c 0x40 serial0.parent rt_device +0x0002019c 0x14 serial0.parent.parent rt_object +0x0002019c 0x8 serial0.parent.parent.name array[8] of char +0x000201a4 0x1 serial0.parent.parent.type rt_uint8_t +0x000201a5 0x1 * serial0.parent.parent.flag rt_uint8_t +0x000201a8 0x8 serial0.parent.parent.list rt_list_t +0x000201a8 0x4 serial0.parent.parent.list.next pointer to rt_list_node +0x000201ac 0x4 serial0.parent.parent.list.prev pointer to rt_list_node +0x000201b0 0x1 * serial0.parent.type rt_device_class_type +0x000201b2 0x2 serial0.parent.flag rt_uint16_t +0x000201b4 0x2 serial0.parent.open_flag rt_uint16_t +0x000201b6 0x1 serial0.parent.ref_count rt_uint8_t +0x000201b7 0x1 serial0.parent.device_id rt_uint8_t +0x000201b8 0x4 serial0.parent.rx_indicate pointer to function +0x000201bc 0x4 serial0.parent.tx_complete pointer to function +0x000201c0 0x4 serial0.parent.init pointer to function +0x000201c4 0x4 serial0.parent.open pointer to function +0x000201c8 0x4 serial0.parent.close pointer to function +0x000201cc 0x4 serial0.parent.read pointer to function +0x000201d0 0x4 serial0.parent.write pointer to function +0x000201d4 0x4 serial0.parent.control pointer to function +0x000201d8 0x4 serial0.parent.user_data pointer to unknown Type +0x000201dc 0x4 serial0.ops pointer to const rt_uart_ops +0x000201e0 0x8 serial0.config serial_configure +0x000201e0 0x4 serial0.config.baud_rate rt_uint32_t +0x000201e4 0x4(28:4) serial0.config.data_bits rt_uint32_t +0x000201e4 0x4(26:2) serial0.config.stop_bits rt_uint32_t +0x000201e4 0x4(24:2) serial0.config.parity rt_uint32_t +0x000201e4 0x4(23:1) serial0.config.bit_order rt_uint32_t +0x000201e4 0x4(22:1) serial0.config.invert rt_uint32_t +0x000201e4 0x4(6:16) serial0.config.bufsz rt_uint32_t +0x000201e4 0x4(0:6) serial0.config.reserved rt_uint32_t +0x000201e8 0x4 serial0.serial_rx pointer to unknown Type +0x000201ec 0x4 serial0.serial_tx pointer to unknown Type + +address size variable name type +0x00020010 0x2 uart0 yc3121_uart +0x00020010 0x1 uart0.uart UART_TypeDef +0x00020011 0x1 uart0.irq IRQn_Type + +address size variable name type +0x01007420 0x14 yc3121_uart_ops const rt_uart_ops +0x01007420 0x4 yc3121_uart_ops.configure pointer to function +0x01007424 0x4 yc3121_uart_ops.control pointer to function +0x01007428 0x4 yc3121_uart_ops.putc pointer to function +0x0100742c 0x4 yc3121_uart_ops.getc pointer to function +0x01007430 0x4 yc3121_uart_ops.dma_transmit pointer to function + +address size variable name type +0x010082f8 0x4 __rt_init_rt_hw_pin_init const init_fn_t + +address size variable name type +0x01007404 0x1c yc3121_pin_ops const rt_pin_ops +0x01007404 0x4 yc3121_pin_ops.pin_mode pointer to function +0x01007408 0x4 yc3121_pin_ops.pin_write pointer to function +0x0100740c 0x4 yc3121_pin_ops.pin_read pointer to function +0x01007410 0x4 yc3121_pin_ops.pin_attach_irq pointer to unknown Type +0x01007414 0x4 yc3121_pin_ops.pin_detach_irq pointer to function +0x01007418 0x4 yc3121_pin_ops.pin_irq_enable pointer to function +0x0100741c 0x4 yc3121_pin_ops.pin_get pointer to function + +address size variable name type +0x00020158 0x44 _hw_pin rt_device_pin +0x00020158 0x40 _hw_pin.parent rt_device +0x00020158 0x14 _hw_pin.parent.parent rt_object +0x00020158 0x8 _hw_pin.parent.parent.name array[8] of char +0x00020160 0x1 _hw_pin.parent.parent.type rt_uint8_t +0x00020161 0x1 * _hw_pin.parent.parent.flag rt_uint8_t +0x00020164 0x8 _hw_pin.parent.parent.list rt_list_t +0x00020164 0x4 _hw_pin.parent.parent.list.next pointer to rt_list_node +0x00020168 0x4 _hw_pin.parent.parent.list.prev pointer to rt_list_node +0x0002016c 0x1 * _hw_pin.parent.type rt_device_class_type +0x0002016e 0x2 _hw_pin.parent.flag rt_uint16_t +0x00020170 0x2 _hw_pin.parent.open_flag rt_uint16_t +0x00020172 0x1 _hw_pin.parent.ref_count rt_uint8_t +0x00020173 0x1 _hw_pin.parent.device_id rt_uint8_t +0x00020174 0x4 _hw_pin.parent.rx_indicate pointer to function +0x00020178 0x4 _hw_pin.parent.tx_complete pointer to function +0x0002017c 0x4 _hw_pin.parent.init pointer to function +0x00020180 0x4 _hw_pin.parent.open pointer to function +0x00020184 0x4 _hw_pin.parent.close pointer to function +0x00020188 0x4 _hw_pin.parent.read pointer to function +0x0002018c 0x4 _hw_pin.parent.write pointer to function +0x00020190 0x4 _hw_pin.parent.control pointer to function +0x00020194 0x4 _hw_pin.parent.user_data pointer to unknown Type +0x00020198 0x4 _hw_pin.ops pointer to const rt_pin_ops + +address size variable name type +0x00020000 0x4 rt_interrupt_from_thread rt_uint32_t + +address size variable name type +0x00020004 0x4 rt_interrupt_to_thread rt_uint32_t + +address size variable name type +0x00020008 0x4 rt_thread_switch_interrupt_flag rt_uint32_t + diff --git a/bsp/yichip/yc3121-pos/template.ewp b/bsp/yichip/yc3121-pos/template.ewp new file mode 100644 index 0000000000..2ff75d9abc --- /dev/null +++ b/bsp/yichip/yc3121-pos/template.ewp @@ -0,0 +1,2032 @@ + + + 3 + + rt-thread + + ARM + + 1 + + General + 3 + + 29 + 1 + 1 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + ICCARM + 2 + + 34 + 1 + 1 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + AARM + 2 + + 10 + 1 + 1 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + OBJCOPY + 0 + + 1 + 1 + 1 + + + + + + + + + CUSTOM + 3 + + + + 0 + + + + BICOMP + 0 + + + + BUILDACTION + 1 + + + + + + + ILINK + 0 + + 20 + 1 + 1 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + IARCHIVE + 0 + + 0 + 1 + 1 + + + + + + + BILINK + 0 + + + + + Release + + ARM + + 0 + + General + 3 + + 29 + 1 + 0 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + ICCARM + 2 + + 34 + 1 + 0 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + AARM + 2 + + 10 + 1 + 0 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + OBJCOPY + 0 + + 1 + 1 + 0 + + + + + + + + + CUSTOM + 3 + + + + 0 + + + + BICOMP + 0 + + + + BUILDACTION + 1 + + + + + + + ILINK + 0 + + 20 + 1 + 0 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + IARCHIVE + 0 + + 0 + 1 + 0 + + + + + + + BILINK + 0 + + + + diff --git a/bsp/yichip/yc3121-pos/template.eww b/bsp/yichip/yc3121-pos/template.eww new file mode 100644 index 0000000000..bd036bb4c9 --- /dev/null +++ b/bsp/yichip/yc3121-pos/template.eww @@ -0,0 +1,10 @@ + + + + + $WS_DIR$\template.ewp + + + + + diff --git a/bsp/yichip/yc3121-pos/template.uvopt b/bsp/yichip/yc3121-pos/template.uvopt new file mode 100644 index 0000000000..0e93bee143 --- /dev/null +++ b/bsp/yichip/yc3121-pos/template.uvopt @@ -0,0 +1,184 @@ + + + + 1.0 + +
### uVision Project, (C) Keil Software
+ + + *.c + *.s*; *.src; *.a* + *.obj + *.lib + *.txt; *.h; *.inc + *.plm + *.cpp + + + + 0 + 0 + + + + rt-thread + 0x4 + ARM-ADS + + 25000000 + + 1 + 1 + 1 + 0 + + + 1 + 65535 + 0 + 0 + 0 + + + 79 + 66 + 8 + .\build\keil\List\ + + + 1 + 1 + 1 + 0 + 1 + 1 + 0 + 1 + 0 + 0 + 0 + 0 + + + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 0 + 0 + + + 0 + 0 + 1 + + 255 + + + 0 + Datasheet + DATASHTS\ST\STM32F4xx\DM00053488.pdf + + + 1 + Reference Manual + DATASHTS\ST\STM32F4xx\DM00031020.pdf + + + 2 + Technical Reference Manual + datashts\arm\cortex_m4\r0p1\DDI0439C_CORTEX_M4_R0P1_TRM.PDF + + + 3 + Generic User Guide + datashts\arm\cortex_m4\r0p1\DUI0553A_CORTEX_M4_DGUG.PDF + + + + 0 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 0 + 1 + 0 + 1 + 1 + 0 + 0 + 0 + 6 + + + + + + + + + + + Segger\JL2CM3.dll + + + + 0 + JL2CM3 + -U20090928 -O207 -S0 -A0 -C0 -JU1 -JI127.0.0.1 -JP0 -RST0 -TO18 -TC10000000 -TP21 -TDS8001 -TDT0 -TDC1F -TIEFFFFFFFF -TIP8 -TB1 -TFE0 -FO15 -FD20000000 -FC800 -FN1 -FF0STM32F4xx_1024 -FS08000000 -FL0100000 + + + 0 + UL2CM3 + UL2CM3(-O207 -S0 -C0 -FO7 -FN1 -FC800 -FD20000000 -FF0STM32F4xx_1024 -FL0100000 -FS08000000 + + + + + 0 + + + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + + + + + + + diff --git a/bsp/yichip/yc3121-pos/template.uvoptx b/bsp/yichip/yc3121-pos/template.uvoptx new file mode 100644 index 0000000000..3534243b9f --- /dev/null +++ b/bsp/yichip/yc3121-pos/template.uvoptx @@ -0,0 +1,177 @@ + + + + 1.0 + +
### uVision Project, (C) Keil Software
+ + + *.c + *.s*; *.src; *.a* + *.obj; *.o + *.lib + *.txt; *.h; *.inc + *.plm + *.cpp + 0 + + + + 0 + 0 + + + + rt-thread + 0x4 + ARM-ADS + + 12000000 + + 1 + 1 + 0 + 1 + 0 + + + 1 + 65535 + 0 + 0 + 0 + + + 79 + 66 + 8 + .\build\ + + + 1 + 1 + 1 + 0 + 1 + 1 + 0 + 1 + 0 + 0 + 0 + 0 + + + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 0 + 0 + + + 0 + 0 + 1 + + 7 + + 0 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 0 + 1 + 1 + 1 + 1 + 0 + 0 + 1 + 0 + 0 + 4 + + + + + + + + + + + Segger\JL2CM3.dll + + + + 0 + UL2CM3 + UL2CM3(-S0 -C0 -P0 -FD20000000 -FC1000) + + + 0 + JL2CM3 + -U788594195 -O78 -S2 -ZTIFSpeedSel5000 -A0 -C0 -JU1 -JI127.0.0.1 -JP0 -RST0 -N00("ARM CoreSight SW-DP") -D00(0BB11477) -L00(0) -TO18 -TC10000000 -TP21 -TDS8004 -TDT0 -TDC1F -TIEFFFFFFFF -TIP8 -TB1 -TFE0 -FO31 -FD20000 -FCA000 -FN0 + + + + + 0 + + + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + + + + 0 + 0 + 0 + + + + + + + + + + + + diff --git a/bsp/yichip/yc3121-pos/template.uvprojx b/bsp/yichip/yc3121-pos/template.uvprojx new file mode 100644 index 0000000000..daa2a90403 --- /dev/null +++ b/bsp/yichip/yc3121-pos/template.uvprojx @@ -0,0 +1,389 @@ + + + + 2.1 + +
### uVision Project, (C) Keil Software
+ + + + rt-thread + 0x4 + ARM-ADS + 5060528::V5.06 update 5 (build 528)::ARMCC + 0 + + + ARMCM0 + ARM + ARM.CMSIS.5.3.0 + http://www.keil.com/pack/ + IRAM(0x20000000,0x00020000) IROM(0x00000000,0x00040000) CPUTYPE("Cortex-M0") CLOCK(12000000) ESEL ELITTLE + + + UL2CM3(-S0 -C0 -P0 -FD20000000 -FC1000) + 0 + $$Device:ARMCM0$Device\ARM\ARMCM0\Include\ARMCM0.h + + + + + + + + + + $$Device:ARMCM0$Device\ARM\SVD\ARMCM0.svd + 0 + 0 + + + + + + + 0 + 0 + 0 + 0 + 1 + + .\build\keil\Obj\ + rtthread + 1 + 0 + 1 + 1 + 1 + .\build\ + 1 + 0 + 0 + + 0 + 0 + + + 0 + 0 + 0 + 0 + + + 0 + 0 + + + 0 + 0 + 0 + 0 + + + 1 + 0 + fromelf.exe --text -a -c --output=@L_asm.txt "!L" + + 0 + 0 + 0 + 0 + + 0 + + + + 0 + 0 + 0 + 0 + 0 + 1 + 0 + 0 + 0 + 0 + 3 + + + 1 + + + SARMCM3.DLL + + DARMCM1.DLL + -pCM0 + SARMCM3.DLL + + TARMCM1.DLL + -pCM0 + + + + 1 + 0 + 0 + 0 + 16 + + + + + 1 + 0 + 0 + 1 + 1 + 4100 + + 0 + Segger\JL2CM3.dll + "" () + + + + + 0 + + + + 0 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 0 + 1 + 1 + 0 + 1 + 1 + 0 + 0 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + "Cortex-M0" + + 0 + 0 + 0 + 1 + 1 + 0 + 0 + 0 + 0 + 0 + 8 + 0 + 1 + 0 + 0 + 3 + 3 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 1 + 0 + 0 + 0 + 0 + 1 + 0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x20000000 + 0x20000 + + + 1 + 0x0 + 0x40000 + + + 0 + 0x0 + 0x0 + + + 1 + 0x0 + 0x0 + + + 1 + 0x0 + 0x0 + + + 1 + 0x0 + 0x0 + + + 1 + 0x0 + 0x40000 + + + 1 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x20000000 + 0x20000 + + + 0 + 0x0 + 0x0 + + + + + + 1 + 1 + 0 + 0 + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + + + + + + + + + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + + + + + + + + + 0 + 0 + 0 + 0 + 1 + 0 + 0x00000000 + 0x20000000 + + .\drivers\linker_scripts\link.sct + + + + + + + + + + + + + + + + + + -- cgit v1.3.1 From 79bed2c0fd2e9add3bb9001258ff4bb4c0af492f Mon Sep 17 00:00:00 2001 From: fzxhub Date: Fri, 17 Sep 2021 18:19:23 +0800 Subject: 使用lpc408x时，需要用到ADC，因此写了ADC的驱动 MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit --- bsp/lpc408x/README.md | 1 + bsp/lpc408x/drivers/Kconfig | 5 ++ bsp/lpc408x/drivers/SConscript | 3 ++ bsp/lpc408x/drivers/drv_adc.c | 117 +++++++++++++++++++++++++++++++++++++++++ bsp/lpc408x/drivers/drv_adc.h | 10 ++++ 5 files changed, 136 insertions(+) create mode 100644 bsp/lpc408x/drivers/drv_adc.c create mode 100644 bsp/lpc408x/drivers/drv_adc.h (limited to 'bsp') diff --git a/bsp/lpc408x/README.md b/bsp/lpc408x/README.md index 7561dcc8f8..085d445308 100644 --- a/bsp/lpc408x/README.md +++ b/bsp/lpc408x/README.md @@ -51,6 +51,7 @@ finsh /> | ETH | 支持 | | | LCD | 支持 | | | SDRAM | 支持 | | +| ADC | 支持 | | ### IO 在板级支持包中的映射情况 diff --git a/bsp/lpc408x/drivers/Kconfig b/bsp/lpc408x/drivers/Kconfig index bf14b67519..a62f12bc74 100644 --- a/bsp/lpc408x/drivers/Kconfig +++ b/bsp/lpc408x/drivers/Kconfig @@ -12,6 +12,11 @@ menu "Hardware Drivers Config" select RT_USING_HWTIMER default n + config BSP_USING_ADC + bool "Using ADC" + select RT_USING_ADC + default n + menu "UART Drivers" config BSP_USING_UART0 bool "Enable UART0 P0.2/P0.3(T/R)" diff --git a/bsp/lpc408x/drivers/SConscript b/bsp/lpc408x/drivers/SConscript index 8c7c4435b2..2cfe8e8271 100644 --- a/bsp/lpc408x/drivers/SConscript +++ b/bsp/lpc408x/drivers/SConscript @@ -23,6 +23,9 @@ if GetDepend(['BSP_USING_SDRAM']): if GetDepend('BSP_USING_UART0') or GetDepend('BSP_USING_UART2'): src += ['drv_uart.c'] +if GetDepend('BSP_USING_ADC'): + src += ['drv_adc.c'] + group = DefineGroup('Drivers', src, depend = [''], CPPPATH = CPPPATH) Return('group') diff --git a/bsp/lpc408x/drivers/drv_adc.c b/bsp/lpc408x/drivers/drv_adc.c new file mode 100644 index 0000000000..ff7825df55 --- /dev/null +++ b/bsp/lpc408x/drivers/drv_adc.c @@ -0,0 +1,117 @@ +/* + * Copyright (c) 2006-2021, fzxhub + */ + +#include +#include +#include "board.h" +#include "drv_adc.h" + +#ifdef RT_USING_ADC + +#ifdef BSP_USING_ADC + +struct lpc_adc +{ + LPC_ADC_TypeDef *ADC; +}; +/* +* channel:0-7 +*/ +static rt_err_t lpc_adc_enabled(struct rt_adc_device *device, rt_uint32_t channel, rt_bool_t enabled) +{ + struct lpc_adc *adc; + + RT_ASSERT(device != RT_NULL); + adc = (struct lpc_adc *)device->parent.user_data; + + //enabled ADC + if(enabled == RT_FALSE) adc->ADC->CR &= ~(1<<21); + else adc->ADC->CR |= (1<<21); + + //Select the channel + adc->ADC->CR |= (1<parent.user_data; + + adc->ADC->CR = (LPC_ADC->CR & 0x00FFFF00) | (1<ADC->GDR & 0x80000000) == 0); + adc->ADC->CR = adc->ADC->CR | (1 << 24); + while ((adc->ADC->GDR & 0x80000000) == 0); + + data = adc->ADC->GDR; + data = (data >> 4) & 0xFFF; + + *value = data; + + return RT_EOK; +} + +static const struct rt_adc_ops lpc_adc_ops = +{ + lpc_adc_enabled, + lpc_adc_convert, +}; + +struct lpc_adc lpc_adc0 = +{ + LPC_ADC, +}; + +struct rt_adc_device adc0; + +int rt_hw_adc_init(void) +{ + rt_err_t ret = RT_EOK; + struct lpc_adc *adc; + + adc = &lpc_adc0; + + adc0.ops = &lpc_adc_ops; + adc0.parent.user_data = adc; + + //ADC port + LPC_IOCON->P0_23 = 0x01; //ADC0[0] + LPC_IOCON->P0_24 = 0x01; //ADC0[1] + LPC_IOCON->P0_25 = 0x01; //ADC0[2] + LPC_IOCON->P0_26 = 0x01; //ADC0[3] + LPC_IOCON->P1_30 = 0x03; //ADC0[4] + LPC_IOCON->P1_31 = 0x03; //ADC0[5] + LPC_IOCON->P0_12 = 0x03; //ADC0[6] + LPC_IOCON->P0_13 = 0x03; //ADC0[7] + + + //clock + LPC_SC->PCONP |= (1U << 12); + //config + LPC_ADC->CR = 0; + LPC_ADC->CR = (1 << 0)| // SEL + ((PeripheralClock / 1000000 - 1) << 8) | // CLKDIV = Fpclk / 1000000 - 1 + (0 << 16)| // BURST + (0 << 17)| // CLKS + (1 << 21)| // PDN + (0 << 22)| // TEST1 + (1 << 24)| // START + (0 << 27); // EDGE + //waiting + while ((LPC_ADC->GDR & 0x80000000) == 0); + + ret = rt_hw_adc_register(&adc0,"adc0",&lpc_adc_ops,adc); + + return ret; +} + +INIT_BOARD_EXPORT(rt_hw_adc_init); +#endif /* BSP_USING_ADC */ + +#endif /* RT_USING_ADC */ diff --git a/bsp/lpc408x/drivers/drv_adc.h b/bsp/lpc408x/drivers/drv_adc.h new file mode 100644 index 0000000000..2ef13ad96c --- /dev/null +++ b/bsp/lpc408x/drivers/drv_adc.h @@ -0,0 +1,10 @@ +/* + * Copyright (c) 2006-2021, fzxhub + */ + +#ifndef DRV_ADC_H__ +#define DRV_ADC_H__ + +int rt_hw_adc_init(void); + +#endif -- cgit v1.3.1 From 1b87dd23cb546c83f4609947173e7e92732511b5 Mon Sep 17 00:00:00 2001 From: fzxhub Date: Sat, 18 Sep 2021 09:41:44 +0800 Subject: lpc408x的ADC驱动进行格式处理 MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit --- bsp/lpc408x/drivers/drv_adc.c | 88 +++++++++++++++++++++---------------------- 1 file changed, 44 insertions(+), 44 deletions(-) (limited to 'bsp') diff --git a/bsp/lpc408x/drivers/drv_adc.c b/bsp/lpc408x/drivers/drv_adc.c index ff7825df55..0d9501b505 100644 --- a/bsp/lpc408x/drivers/drv_adc.c +++ b/bsp/lpc408x/drivers/drv_adc.c @@ -20,47 +20,47 @@ struct lpc_adc */ static rt_err_t lpc_adc_enabled(struct rt_adc_device *device, rt_uint32_t channel, rt_bool_t enabled) { - struct lpc_adc *adc; + struct lpc_adc *adc; RT_ASSERT(device != RT_NULL); adc = (struct lpc_adc *)device->parent.user_data; - - //enabled ADC - if(enabled == RT_FALSE) adc->ADC->CR &= ~(1<<21); - else adc->ADC->CR |= (1<<21); - - //Select the channel - adc->ADC->CR |= (1<ADC->CR &= ~(1<<21); + else adc->ADC->CR |= (1<<21); + + //Select the channel + adc->ADC->CR |= (1<parent.user_data; - - adc->ADC->CR = (LPC_ADC->CR & 0x00FFFF00) | (1<ADC->GDR & 0x80000000) == 0); - adc->ADC->CR = adc->ADC->CR | (1 << 24); - while ((adc->ADC->GDR & 0x80000000) == 0); - - data = adc->ADC->GDR; - data = (data >> 4) & 0xFFF; - - *value = data; - - return RT_EOK; + + adc->ADC->CR = (LPC_ADC->CR & 0x00FFFF00) | (1<ADC->GDR & 0x80000000) == 0); + adc->ADC->CR = adc->ADC->CR | (1 << 24); + while ((adc->ADC->GDR & 0x80000000) == 0); + + data = adc->ADC->GDR; + data = (data >> 4) & 0xFFF; + + *value = data; + + return RT_EOK; } static const struct rt_adc_ops lpc_adc_ops = { - lpc_adc_enabled, - lpc_adc_convert, + lpc_adc_enabled, + lpc_adc_convert, }; struct lpc_adc lpc_adc0 = @@ -72,16 +72,16 @@ struct rt_adc_device adc0; int rt_hw_adc_init(void) { - rt_err_t ret = RT_EOK; - struct lpc_adc *adc; - - adc = &lpc_adc0; - - adc0.ops = &lpc_adc_ops; - adc0.parent.user_data = adc; - - //ADC port - LPC_IOCON->P0_23 = 0x01; //ADC0[0] + rt_err_t ret = RT_EOK; + struct lpc_adc *adc; + + adc = &lpc_adc0; + + adc0.ops = &lpc_adc_ops; + adc0.parent.user_data = adc; + + //ADC port + LPC_IOCON->P0_23 = 0x01; //ADC0[0] LPC_IOCON->P0_24 = 0x01; //ADC0[1] LPC_IOCON->P0_25 = 0x01; //ADC0[2] LPC_IOCON->P0_26 = 0x01; //ADC0[3] @@ -89,12 +89,12 @@ int rt_hw_adc_init(void) LPC_IOCON->P1_31 = 0x03; //ADC0[5] LPC_IOCON->P0_12 = 0x03; //ADC0[6] LPC_IOCON->P0_13 = 0x03; //ADC0[7] - - - //clock - LPC_SC->PCONP |= (1U << 12); - //config - LPC_ADC->CR = 0; + + + //clock + LPC_SC->PCONP |= (1U << 12); + //config + LPC_ADC->CR = 0; LPC_ADC->CR = (1 << 0)| // SEL ((PeripheralClock / 1000000 - 1) << 8) | // CLKDIV = Fpclk / 1000000 - 1 (0 << 16)| // BURST @@ -103,12 +103,12 @@ int rt_hw_adc_init(void) (0 << 22)| // TEST1 (1 << 24)| // START (0 << 27); // EDGE - //waiting + //waiting while ((LPC_ADC->GDR & 0x80000000) == 0); - ret = rt_hw_adc_register(&adc0,"adc0",&lpc_adc_ops,adc); - - return ret; + ret = rt_hw_adc_register(&adc0,"adc0",&lpc_adc_ops,adc); + + return ret; } INIT_BOARD_EXPORT(rt_hw_adc_init); -- cgit v1.3.1 From 2389b309f4de480137866fc6c3cbeca32d1ef192 Mon Sep 17 00:00:00 2001 From: WUSY1991 <1191297340@qq.com> Date: Mon, 20 Sep 2021 09:20:17 +0800 Subject: 修改反馈的格式问题 MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit --- bsp/yichip/yc3121-pos/.ignore_format.yml | 20 +- bsp/yichip/yc3121-pos/README.md | 12 +- bsp/yichip/yc3121-pos/drivers/drv_gpio.c | 140 +- bsp/yichip/yc3121-pos/drivers/drv_uart.c | 1 - .../yc3121-pos/drivers/linker_scripts/link.icf | 2 +- .../yc3121-pos/drivers/linker_scripts/link.lds | 2 +- bsp/yichip/yc3121-pos/project.uvoptx | 20 +- bsp/yichip/yc3121-pos/project.uvprojx | 5 - bsp/yichip/yc3121-pos/rtthread_asm.txt | 14979 ------------------- 9 files changed, 121 insertions(+), 15060 deletions(-) delete mode 100644 bsp/yichip/yc3121-pos/rtthread_asm.txt (limited to 'bsp') diff --git a/bsp/yichip/yc3121-pos/.ignore_format.yml b/bsp/yichip/yc3121-pos/.ignore_format.yml index b7cc004bc7..2a686aabbe 100644 --- a/bsp/yichip/yc3121-pos/.ignore_format.yml +++ b/bsp/yichip/yc3121-pos/.ignore_format.yml @@ -3,23 +3,7 @@ # If you need to exclude a file, add the path to the file in file_path. file_path: -- Libraries/core/board_config.h -- Libraries/core/misc.c -- Libraries/core/misc.h -- Libraries/core/rom_api.h -- Libraries/core/system.c -- Libraries/core/system.h -- Libraries/core/type.h -- Libraries/core/yc3121.h -- Libraries/sdk/yc_dma.c -- Libraries/sdk/yc_dma.h -- Libraries/sdk/yc_gpio.c -- Libraries/sdk/yc_gpio.h -- Libraries/sdk/yc_systick.c -- Libraries/sdk/yc_uart.c -- Libraries/sdk/yc_uart.h + dir_path: -- Libraries/core -- Libraries/sdk -- Libraries/startup +- Libraries diff --git a/bsp/yichip/yc3121-pos/README.md b/bsp/yichip/yc3121-pos/README.md index 490faa69a6..b800866155 100644 --- a/bsp/yichip/yc3121-pos/README.md +++ b/bsp/yichip/yc3121-pos/README.md @@ -31,6 +31,12 @@ YC3121-pos 开发板板载资源如下： - UART - SPI LCD - SPI NFC - - 7816 - - 7811 -- 调试接口：SWD + - 7816接口 （接触IC卡，支持3V , 1.8V） + - 7811接口 （三轨磁条卡解码模块，支持ISO/ABA AAMVA 及IBM等标准卡） + - TIMER：9个32bi位 （支持PWM） + - TRNG：（1个真随机数发生器） + - 安全加密算法 + - 对称算法：对称算法：DES、TDES、AES-128/192/256、国密IV（SM4） + - 非对称算法：RSA-1024/2048、国密II（SM2）、ECC + - HASH 校验算法：SHA-1/224/256/384/512、国密III（SM3） +- 调试接口：SWD / ICE diff --git a/bsp/yichip/yc3121-pos/drivers/drv_gpio.c b/bsp/yichip/yc3121-pos/drivers/drv_gpio.c index 10ccaa548f..fc695a0318 100644 --- a/bsp/yichip/yc3121-pos/drivers/drv_gpio.c +++ b/bsp/yichip/yc3121-pos/drivers/drv_gpio.c @@ -13,6 +13,8 @@ #include #include +#define PIN_MAX_NUM (48) + typedef void (*pin_callback_t)(void *args); struct pin { @@ -25,6 +27,59 @@ struct pin }; typedef struct pin pin_t; + +struct rt_pin_irq_hdr pin_irq_hdr_tab[] = +{ + {-1, 0, RT_NULL, RT_NULL}, + {-1, 0, RT_NULL, RT_NULL}, + {-1, 0, RT_NULL, RT_NULL}, + {-1, 0, RT_NULL, RT_NULL}, + {-1, 0, RT_NULL, RT_NULL}, + {-1, 0, RT_NULL, RT_NULL}, + {-1, 0, RT_NULL, RT_NULL}, + {-1, 0, RT_NULL, RT_NULL}, + {-1, 0, RT_NULL, RT_NULL}, + {-1, 0, RT_NULL, RT_NULL}, + {-1, 0, RT_NULL, RT_NULL}, + {-1, 0, RT_NULL, RT_NULL}, + {-1, 0, RT_NULL, RT_NULL}, + {-1, 0, RT_NULL, RT_NULL}, + {-1, 0, RT_NULL, RT_NULL}, + {-1, 0, RT_NULL, RT_NULL}, + {-1, 0, RT_NULL, RT_NULL}, + {-1, 0, RT_NULL, RT_NULL}, + {-1, 0, RT_NULL, RT_NULL}, + {-1, 0, RT_NULL, RT_NULL}, + {-1, 0, RT_NULL, RT_NULL}, + {-1, 0, RT_NULL, RT_NULL}, + {-1, 0, RT_NULL, RT_NULL}, + {-1, 0, RT_NULL, RT_NULL}, + {-1, 0, RT_NULL, RT_NULL}, + {-1, 0, RT_NULL, RT_NULL}, + {-1, 0, RT_NULL, RT_NULL}, + {-1, 0, RT_NULL, RT_NULL}, + {-1, 0, RT_NULL, RT_NULL}, + {-1, 0, RT_NULL, RT_NULL}, + {-1, 0, RT_NULL, RT_NULL}, + {-1, 0, RT_NULL, RT_NULL}, + {-1, 0, RT_NULL, RT_NULL}, + {-1, 0, RT_NULL, RT_NULL}, + {-1, 0, RT_NULL, RT_NULL}, + {-1, 0, RT_NULL, RT_NULL}, + {-1, 0, RT_NULL, RT_NULL}, + {-1, 0, RT_NULL, RT_NULL}, + {-1, 0, RT_NULL, RT_NULL}, + {-1, 0, RT_NULL, RT_NULL}, + {-1, 0, RT_NULL, RT_NULL}, + {-1, 0, RT_NULL, RT_NULL}, + {-1, 0, RT_NULL, RT_NULL}, + {-1, 0, RT_NULL, RT_NULL}, + {-1, 0, RT_NULL, RT_NULL}, + {-1, 0, RT_NULL, RT_NULL}, + {-1, 0, RT_NULL, RT_NULL}, + {-1, 0, RT_NULL, RT_NULL}, +}; + static void yc_pin_mode(rt_device_t dev, rt_base_t pin, rt_base_t mode) { /* Configure GPIO_InitStructure */ @@ -78,33 +133,42 @@ static rt_err_t yc_pin_attach_irq(struct rt_device *device, pin_callback_t cb, void *args) { - pin_t *index; + rt_int32_t index = -1; rt_base_t level; - if (index == RT_NULL) + if (pin >= PIN_MAX_NUM) { - return RT_EINVAL; + return -RT_EINVAL; } + + index = pin; level = rt_hw_interrupt_disable(); - index->callback = cb; - index->callback_args = args; - index->irq_mode = mode; + pin_irq_hdr_tab[index].pin = pin; + pin_irq_hdr_tab[index].hdr = cb; + pin_irq_hdr_tab[index].mode = mode; + pin_irq_hdr_tab[index].args = args; rt_hw_interrupt_enable(level); + return RT_EOK; } static rt_err_t yc_pin_detach_irq(struct rt_device *device, rt_int32_t pin) { - pin_t *index; + rt_int32_t index = -1; rt_base_t level; - if (index == RT_NULL) + if (pin >= PIN_MAX_NUM) { - return RT_EINVAL; + return -RT_EINVAL; } + + index = pin; level = rt_hw_interrupt_disable(); - index->callback = 0; - index->callback_args = 0; - index->irq_mode = 0; + + pin_irq_hdr_tab[index].pin = -1; + pin_irq_hdr_tab[index].hdr = RT_NULL; + pin_irq_hdr_tab[index].mode = 0; + pin_irq_hdr_tab[index].args = RT_NULL; + rt_hw_interrupt_enable(level); return RT_EOK; } @@ -113,15 +177,18 @@ static rt_err_t yc_pin_irq_enable(struct rt_device *device, rt_base_t pin, rt_uint32_t enabled) { - pin_t *index; + rt_int32_t index; rt_base_t level = 0; - if (index == RT_NULL) + if (pin >= PIN_MAX_NUM) { - return RT_EINVAL; + return -RT_EINVAL; } + + index = pin; + if (enabled == PIN_IRQ_ENABLE) { - switch (index->irq_mode) + switch (pin_irq_hdr_tab[index].mode) { case PIN_IRQ_MODE_RISING: @@ -134,11 +201,11 @@ static rt_err_t yc_pin_irq_enable(struct rt_device *device, break; case PIN_IRQ_MODE_HIGH_LEVEL: GPIO_CONFIG(pin) = PULL_DOWN; - GPIO_TRIG_MODE(pin/16) &= (1 << (pin % 16)); + GPIO_TRIG_MODE(pin / 16) &= (1 << (pin % 16)); break; case PIN_IRQ_MODE_LOW_LEVEL: GPIO_CONFIG(pin) = PULL_UP; - GPIO_TRIG_MODE(pin/16) |= (1 << (pin % 16)); + GPIO_TRIG_MODE(pin / 16) |= (1 << (pin % 16)); break; default: rt_hw_interrupt_enable(level); @@ -146,13 +213,13 @@ static rt_err_t yc_pin_irq_enable(struct rt_device *device, } level = rt_hw_interrupt_disable(); - NVIC_EnableIRQ(index->irq); + NVIC_EnableIRQ(GPIO_IRQn); GPIO_INTR_EN(pin / 16) |= (1 << (pin % 16)); rt_hw_interrupt_enable(level); } else if (enabled == PIN_IRQ_DISABLE) { - NVIC_DisableIRQ(index->irq); + NVIC_DisableIRQ(GPIO_IRQn); GPIO_INTR_EN(pin / 16) &= ~(1 << (pin % 16)); } else @@ -163,14 +230,14 @@ static rt_err_t yc_pin_irq_enable(struct rt_device *device, } const static struct rt_pin_ops yc3121_pin_ops = - { - yc_pin_mode, - yc_pin_write, - yc_pin_read, - yc_pin_attach_irq, - yc_pin_detach_irq, - yc_pin_irq_enable, - RT_NULL, +{ + yc_pin_mode, + yc_pin_write, + yc_pin_read, + yc_pin_attach_irq, + yc_pin_detach_irq, + yc_pin_irq_enable, + RT_NULL, }; int rt_hw_pin_init(void) @@ -181,19 +248,20 @@ int rt_hw_pin_init(void) } INIT_BOARD_EXPORT(rt_hw_pin_init); -void GPIOA_Handler(void) +void GPIO_IRQHandler(void) { int i; - /* enter interrupt */ rt_interrupt_enter(); - - for (i = 0; i < 48; i++) + for (i = 0; i < PIN_MAX_NUM; i++) { - // if(GPIO_IN(pin / 16) & (1 << (pin % 16))) - + if ((GPIO_TRIG_MODE(i / 16) & (1 << (i % 16))) == (GPIO_IN(i / 16) & (1 << (i % 16)))) + { + if (pin_irq_hdr_tab[i].hdr) + { + pin_irq_hdr_tab[i].hdr(pin_irq_hdr_tab[i].args); + } + } } - - /* leave interrupt */ rt_interrupt_leave(); } diff --git a/bsp/yichip/yc3121-pos/drivers/drv_uart.c b/bsp/yichip/yc3121-pos/drivers/drv_uart.c index 195be621eb..973951663e 100644 --- a/bsp/yichip/yc3121-pos/drivers/drv_uart.c +++ b/bsp/yichip/yc3121-pos/drivers/drv_uart.c @@ -191,4 +191,3 @@ int rt_hw_uart_init(void) #endif /* BSP_USING_UART1 */ return 0; } -INIT_BOARD_EXPORT(rt_hw_uart_init); diff --git a/bsp/yichip/yc3121-pos/drivers/linker_scripts/link.icf b/bsp/yichip/yc3121-pos/drivers/linker_scripts/link.icf index f58af36588..25b66c5fe9 100644 --- a/bsp/yichip/yc3121-pos/drivers/linker_scripts/link.icf +++ b/bsp/yichip/yc3121-pos/drivers/linker_scripts/link.icf @@ -29,4 +29,4 @@ place at address mem:__ICFEDIT_intvec_start__ { readonly section .intvec }; place in ROM_region { readonly }; place in RAM_region { readwrite, - block CSTACK, block HEAP }; \ No newline at end of file + block CSTACK, block HEAP }; diff --git a/bsp/yichip/yc3121-pos/drivers/linker_scripts/link.lds b/bsp/yichip/yc3121-pos/drivers/linker_scripts/link.lds index 177040fbd0..ab85fa4c13 100644 --- a/bsp/yichip/yc3121-pos/drivers/linker_scripts/link.lds +++ b/bsp/yichip/yc3121-pos/drivers/linker_scripts/link.lds @@ -158,4 +158,4 @@ SECTIONS /* Check if data + heap + stack exceeds RAM limit */ ASSERT(__StackLimit >= __HeapLimit, "region RAM overflowed with stack") -} \ No newline at end of file +} diff --git a/bsp/yichip/yc3121-pos/project.uvoptx b/bsp/yichip/yc3121-pos/project.uvoptx index 3f3ca22b61..3ff6686c3f 100644 --- a/bsp/yichip/yc3121-pos/project.uvoptx +++ b/bsp/yichip/yc3121-pos/project.uvoptx @@ -176,7 +176,7 @@ Applications - 1 + 0 0 0 0 @@ -380,7 +380,7 @@ Drivers - 1 + 0 0 0 0 @@ -424,7 +424,7 @@ Finsh - 1 + 0 0 0 0 @@ -664,7 +664,7 @@ Libraries - 1 + 0 0 0 0 @@ -776,18 +776,6 @@ 0 0 - - 8 - 46 - 1 - 0 - 0 - 0 - Libraries\core\bt_code_boot.c - bt_code_boot.c - 0 - 0 - diff --git a/bsp/yichip/yc3121-pos/project.uvprojx b/bsp/yichip/yc3121-pos/project.uvprojx index 81b455d47b..0ddc763de2 100644 --- a/bsp/yichip/yc3121-pos/project.uvprojx +++ b/bsp/yichip/yc3121-pos/project.uvprojx @@ -641,11 +641,6 @@ 1 Libraries\sdk\yc_systick.c - - bt_code_boot.c - 1 - Libraries\core\bt_code_boot.c - diff --git a/bsp/yichip/yc3121-pos/rtthread_asm.txt b/bsp/yichip/yc3121-pos/rtthread_asm.txt deleted file mode 100644 index 88b0881675..0000000000 --- a/bsp/yichip/yc3121-pos/rtthread_asm.txt +++ /dev/null @@ -1,14979 +0,0 @@ - -======================================================================== - -** ELF Header Information - - File Name: .\build\keil\Obj\rtthread.axf - - Machine class: ELFCLASS32 (32-bit) - Data encoding: ELFDATA2LSB (Little endian) - Header version: EV_CURRENT (Current version) - Operating System ABI: none - ABI Version: 0 - File Type: ET_EXEC (Executable) (2) - Machine: EM_ARM (ARM) - - Image Entry point: 0x01000401 - Flags: EF_ARM_HASENTRY + EF_ARM_ABI_FLOAT_SOFT (0x05000202) - - ARM ELF revision: 5 (ABI version 2) - - Conforms to Soft float procedure-call standard - - Built with - Component: ARM Compiler 5.06 update 6 (build 750) Tool: armasm [4d35ec] - Component: ARM Compiler 5.06 update 6 (build 750) Tool: armlink [4d35ed] - - Header size: 52 bytes (0x34) - Program header entry size: 32 bytes (0x20) - Section header entry size: 40 bytes (0x28) - - Program header entries: 3 - Section header entries: 19 - - Program header offset: 384436 (0x0005ddb4) - Section header offset: 384532 (0x0005de14) - - Section header string table index: 18 - -======================================================================== - -** Program header #0 (PT_LOAD) [PF_R] - Size : 192 bytes - Virtual address: 0x00000000 (Alignment 4) - - -==================================== - -** Program header #1 (PT_LOAD) [PF_X + PF_R] - Size : 372 bytes - Virtual address: 0x01000200 (Alignment 16) - - -==================================== - -** Program header #2 (PT_LOAD) [PF_X + PF_W + PF_R + PF_ARM_ENTRY] - Size : 36628 bytes (32872 bytes in file) - Virtual address: 0x01000400 (Alignment 16) - - -======================================================================== - -** Section #1 'ER_IROM1' (SHT_PROGBITS) [SHF_ALLOC] - Size : 192 bytes (alignment 4) - Address: 0x00000000 - - -** Section #2 'ER_IROM3' (SHT_PROGBITS) [SHF_ALLOC + SHF_EXECINSTR] - Size : 320 bytes (alignment 16) - Address: 0x01000200 - - $t - .flash_start - Reset_Handler - 0x01000200: 4849 IH LDR r0,[pc,#292] ; [0x1000328] = 0x1000401 - 0x01000202: 4700 .G BX r0 - hard_fault_handler - 0x01000204: 4849 IH LDR r0,[pc,#292] ; [0x100032c] = 0x100056d - 0x01000206: 4700 .G BX r0 - 0x01000208: bf00 .. NOP - svc_handler - 0x0100020a: 4849 IH LDR r0,[pc,#292] ; [0x1000330] = 0x10002a9 - 0x0100020c: 4700 .G BX r0 - 0x0100020e: bf00 .. NOP - pendsv_handler - 0x01000210: 4848 HH LDR r0,[pc,#288] ; [0x1000334] = 0x10004eb - 0x01000212: 4700 .G BX r0 - 0x01000214: bf00 .. NOP - systick - 0x01000216: 4848 HH LDR r0,[pc,#288] ; [0x1000338] = 0x1000b09 - 0x01000218: 4700 .G BX r0 - 0x0100021a: bf00 .. NOP - irq0 - 0x0100021c: 2000 . MOVS r0,#0 - 0x0100021e: e03d =. B isr ; 0x100029c - irq1 - 0x01000220: 2004 . MOVS r0,#4 - 0x01000222: e03b ;. B isr ; 0x100029c - irq2 - 0x01000224: 2008 . MOVS r0,#8 - 0x01000226: e039 9. B isr ; 0x100029c - irq3 - 0x01000228: 200c . MOVS r0,#0xc - 0x0100022a: e037 7. B isr ; 0x100029c - irq4 - 0x0100022c: 2010 . MOVS r0,#0x10 - 0x0100022e: e035 5. B isr ; 0x100029c - irq5 - 0x01000230: 2014 . MOVS r0,#0x14 - 0x01000232: e033 3. B isr ; 0x100029c - irq6 - 0x01000234: 2018 . MOVS r0,#0x18 - 0x01000236: e031 1. B isr ; 0x100029c - irq7 - 0x01000238: 201c . MOVS r0,#0x1c - 0x0100023a: e02f /. B isr ; 0x100029c - irq8 - 0x0100023c: 2020 MOVS r0,#0x20 - 0x0100023e: e02d -. B isr ; 0x100029c - irq9 - 0x01000240: 2024 $ MOVS r0,#0x24 - 0x01000242: e02b +. B isr ; 0x100029c - irq10 - 0x01000244: 2028 ( MOVS r0,#0x28 - 0x01000246: e029 ). B isr ; 0x100029c - irq11 - 0x01000248: 202c , MOVS r0,#0x2c - 0x0100024a: e027 '. B isr ; 0x100029c - irq12 - 0x0100024c: 2030 0 MOVS r0,#0x30 - 0x0100024e: e025 %. B isr ; 0x100029c - irq13 - 0x01000250: 2034 4 MOVS r0,#0x34 - 0x01000252: e023 #. B isr ; 0x100029c - irq14 - 0x01000254: 2038 8 MOVS r0,#0x38 - 0x01000256: e021 !. B isr ; 0x100029c - irq15 - 0x01000258: 203c < MOVS r0,#0x3c - 0x0100025a: e01f .. B isr ; 0x100029c - irq16 - 0x0100025c: 2040 @ MOVS r0,#0x40 - 0x0100025e: e01d .. B isr ; 0x100029c - irq17 - 0x01000260: 2044 D MOVS r0,#0x44 - 0x01000262: e01b .. B isr ; 0x100029c - irq18 - 0x01000264: 2048 H MOVS r0,#0x48 - 0x01000266: e019 .. B isr ; 0x100029c - irq19 - 0x01000268: 204c L MOVS r0,#0x4c - 0x0100026a: e017 .. B isr ; 0x100029c - irq20 - 0x0100026c: 2050 P MOVS r0,#0x50 - 0x0100026e: e015 .. B isr ; 0x100029c - irq21 - 0x01000270: 2054 T MOVS r0,#0x54 - 0x01000272: e013 .. B isr ; 0x100029c - irq22 - 0x01000274: 2058 X MOVS r0,#0x58 - 0x01000276: e011 .. B isr ; 0x100029c - irq23 - 0x01000278: 205c \ MOVS r0,#0x5c - 0x0100027a: e00f .. B isr ; 0x100029c - irq24 - 0x0100027c: 2060 ` MOVS r0,#0x60 - 0x0100027e: e00d .. B isr ; 0x100029c - irq25 - 0x01000280: 2064 d MOVS r0,#0x64 - 0x01000282: e00b .. B isr ; 0x100029c - irq26 - 0x01000284: 2068 h MOVS r0,#0x68 - 0x01000286: e009 .. B isr ; 0x100029c - irq27 - 0x01000288: 206c l MOVS r0,#0x6c - 0x0100028a: e007 .. B isr ; 0x100029c - irq28 - 0x0100028c: 2070 p MOVS r0,#0x70 - 0x0100028e: e005 .. B isr ; 0x100029c - irq29 - 0x01000290: 2074 t MOVS r0,#0x74 - 0x01000292: e003 .. B isr ; 0x100029c - irq30 - 0x01000294: 2078 x MOVS r0,#0x78 - 0x01000296: e001 .. B isr ; 0x100029c - irq31 - 0x01000298: 207c | MOVS r0,#0x7c - 0x0100029a: 46c0 .F MOV r8,r8 - isr - 0x0100029c: 4927 'I LDR r1,[pc,#156] ; [0x100033c] = 0x10002bc - 0x0100029e: 5840 @X LDR r0,[r0,r1] - 0x010002a0: 4700 .G BX r0 - $d - 0x010002a2: 0000 .. DCW 0 - $t - NMI_IRQHandler - 0x010002a4: e7fe .. B NMI_IRQHandler ; 0x10002a4 - HARD_FAULT_IRQHandler - 0x010002a6: e7fe .. B HARD_FAULT_IRQHandler ; 0x10002a6 - SVC_IRQHandler - 0x010002a8: e7fe .. B SVC_IRQHandler ; 0x10002a8 - PENDSV_IRQHandler - 0x010002aa: e7fe .. B PENDSV_IRQHandler ; 0x10002aa - SYSTICK_IRQHandler - 0x010002ac: e7fe .. B SYSTICK_IRQHandler ; 0x10002ac - EXTI0_IRQHandler - 0x010002ae: e7fe .. B EXTI0_IRQHandler ; 0x10002ae - EXTI1_IRQHandler - 0x010002b0: e7fe .. B EXTI1_IRQHandler ; 0x10002b0 - EXTI2_IRQHandler - 0x010002b2: e7fe .. B EXTI2_IRQHandler ; 0x10002b2 - EXTI3_IRQHandler - 0x010002b4: e7fe .. B EXTI3_IRQHandler ; 0x10002b4 - EXTI4_IRQHandler - 0x010002b6: e7fe .. B EXTI4_IRQHandler ; 0x10002b6 - EXTI5_IRQHandler - 0x010002b8: e7fe .. B EXTI5_IRQHandler ; 0x10002b8 - BT_IRQHandler - GPIO_IRQHandler - IIC_IRQHandler - MEMCP_IRQHandler - MSR_IRQHandler - QSPI_IRQHandler - RSA_IRQHandler - SCI0_IRQHandler - SCI1_IRQHandler - SEC_IRQHandler - SM4_IRQHandler - SPI0_IRQHandler - SPI1_IRQHandler - TIMER0_IRQHandler - TIMER1_IRQHandler - TIMER2_IRQHandler - TIMER3_IRQHandler - TIMER4_IRQHandler - TIMER5_IRQHandler - TIMER6_IRQHandler - TIMER7_IRQHandler - TIMER8_IRQHandler - TRNG_IRQHandler - UART1_IRQHandler - USB_IRQHandler - WDT_IRQHandler - 0x010002ba: e7fe .. B BT_IRQHandler ; 0x10002ba - $d - isr_table - 0x010002bc: 010002bb .... DCD 16777915 - 0x010002c0: 010002bb .... DCD 16777915 - 0x010002c4: 010002bb .... DCD 16777915 - 0x010002c8: 010002bb .... DCD 16777915 - 0x010002cc: 010002bb .... DCD 16777915 - 0x010002d0: 01000b19 .... DCD 16780057 - 0x010002d4: 010002bb .... DCD 16777915 - 0x010002d8: 010002bb .... DCD 16777915 - 0x010002dc: 010002bb .... DCD 16777915 - 0x010002e0: 010002bb .... DCD 16777915 - 0x010002e4: 010002bb .... DCD 16777915 - 0x010002e8: 010002bb .... DCD 16777915 - 0x010002ec: 010002bb .... DCD 16777915 - 0x010002f0: 010002bb .... DCD 16777915 - 0x010002f4: 010002bb .... DCD 16777915 - 0x010002f8: 010002bb .... DCD 16777915 - 0x010002fc: 010002bb .... DCD 16777915 - 0x01000300: 010002bb .... DCD 16777915 - 0x01000304: 010002bb .... DCD 16777915 - 0x01000308: 010002bb .... DCD 16777915 - 0x0100030c: 010002bb .... DCD 16777915 - 0x01000310: 010002bb .... DCD 16777915 - 0x01000314: 010002bb .... DCD 16777915 - 0x01000318: 010002bb .... DCD 16777915 - 0x0100031c: 010002bb .... DCD 16777915 - 0x01000320: 010002bb .... DCD 16777915 - 0x01000324: 010002bb .... DCD 16777915 - 0x01000328: 01000401 .... DCD 16778241 - 0x0100032c: 0100056d m... DCD 16778605 - 0x01000330: 010002a9 .... DCD 16777897 - 0x01000334: 010004eb .... DCD 16778475 - 0x01000338: 01000b09 .... DCD 16780041 - 0x0100033c: 010002bc .... DCD 16777916 - -** Section #3 'ER_IROM3_1' (SHT_PROGBITS) [SHF_ALLOC + SHF_EXECINSTR] - Size : 52 bytes (alignment 16) - Address: 0x01000340 - - $t - .INIT_STACK_HEAP - __user_initial_stackheap - 0x01000340: 4802 .H LDR r0,[pc,#8] ; [0x100034c] = 0x20e10 - 0x01000342: 4903 .I LDR r1,[pc,#12] ; [0x1000350] = 0x30000 - 0x01000344: 4a01 .J LDR r2,[pc,#4] ; [0x100034c] = 0x20e10 - 0x01000346: 4b03 .K LDR r3,[pc,#12] ; [0x1000354] = 0x20e10 - 0x01000348: 4770 pG BX lr - $d - 0x0100034a: 0000 .. DCW 0 - 0x0100034c: 00020e10 .... DCD 134672 - 0x01000350: 00030000 .... DCD 196608 - 0x01000354: 00020e10 .... DCD 134672 - 0x01000358: 00000000 .... DCD 0 - 0x0100035c: 00000000 .... DCD 0 - $t - .text - reset_handler - 0x01000360: 4803 .H LDR r0,[pc,#12] ; [0x1000370] = 0x1000201 - 0x01000362: 4700 .G BX r0 - 0x01000364: bf00 .. NOP - delay - 0x01000366: 3801 .8 SUBS r0,#1 - 0x01000368: d1fd .. BNE delay ; 0x1000366 - 0x0100036a: bf00 .. NOP - 0x0100036c: 4770 pG BX lr - nmi_handler - 0x0100036e: e7fe .. B nmi_handler ; 0x100036e - $d - 0x01000370: 01000201 .... DCD 16777729 - -** Section #4 'ER_IROM4' (SHT_PROGBITS) [SHF_ALLOC + SHF_EXECINSTR] - Size : 32772 bytes (alignment 4) - Address: 0x01000400 - - $t - !!!main - __main - 0x01000400: f000f802 .... BL __scatterload ; 0x1000408 - 0x01000404: f000f830 ..0. BL __rt_entry ; 0x1000468 - !!!scatter - __scatterload - __scatterload_rt2 - __scatterload_rt2_thumb_only - 0x01000408: a00c .. ADR r0,{pc}+0x34 ; 0x100043c - 0x0100040a: c830 0. LDM r0!,{r4,r5} - 0x0100040c: 3808 .8 SUBS r0,r0,#8 - 0x0100040e: 1824 $. ADDS r4,r4,r0 - 0x01000410: 182d -. ADDS r5,r5,r0 - 0x01000412: 46a2 .F MOV r10,r4 - 0x01000414: 1e67 g. SUBS r7,r4,#1 - 0x01000416: 46ab .F MOV r11,r5 - __scatterload_null - 0x01000418: 4654 TF MOV r4,r10 - 0x0100041a: 465d ]F MOV r5,r11 - 0x0100041c: 42ac .B CMP r4,r5 - 0x0100041e: d101 .. BNE 0x1000424 ; __scatterload_null + 12 - 0x01000420: f000f822 ..". BL __rt_entry ; 0x1000468 - 0x01000424: 467e ~F MOV r6,pc - 0x01000426: 3e0f .> SUBS r6,r6,#0xf - 0x01000428: cc0f .. LDM r4!,{r0-r3} - 0x0100042a: 46b6 .F MOV lr,r6 - 0x0100042c: 2601 .& MOVS r6,#1 - 0x0100042e: 4233 3B TST r3,r6 - 0x01000430: d000 .. BEQ 0x1000434 ; __scatterload_null + 28 - 0x01000432: 1afb .. SUBS r3,r7,r3 - 0x01000434: 46a2 .F MOV r10,r4 - 0x01000436: 46ab .F MOV r11,r5 - 0x01000438: 4333 3C ORRS r3,r3,r6 - 0x0100043a: 4718 .G BX r3 - $d - 0x0100043c: 00007fa8 .... DCD 32680 - 0x01000440: 00007fc8 .... DCD 32712 - $t - !!handler_zi - __scatterload_zeroinit - 0x01000444: 2300 .# MOVS r3,#0 - 0x01000446: 2400 .$ MOVS r4,#0 - 0x01000448: 2500 .% MOVS r5,#0 - 0x0100044a: 2600 .& MOVS r6,#0 - 0x0100044c: 3a10 .: SUBS r2,r2,#0x10 - 0x0100044e: d301 .. BCC 0x1000454 ; __scatterload_zeroinit + 16 - 0x01000450: c178 x. STM r1!,{r3-r6} - 0x01000452: d8fb .. BHI 0x100044c ; __scatterload_zeroinit + 8 - 0x01000454: 0752 R. LSLS r2,r2,#29 - 0x01000456: d300 .. BCC 0x100045a ; __scatterload_zeroinit + 22 - 0x01000458: c130 0. STM r1!,{r4,r5} - 0x0100045a: d500 .. BPL 0x100045e ; __scatterload_zeroinit + 26 - 0x0100045c: 600b .` STR r3,[r1,#0] - 0x0100045e: 4770 pG BX lr - .ARM.Collect$$libinit$$00000000 - __rt_lib_init - 0x01000460: b51f .. PUSH {r0-r4,lr} - .ARM.Collect$$libinit$$00000002 - .ARM.Collect$$libinit$$00000004 - .ARM.Collect$$libinit$$0000000A - .ARM.Collect$$libinit$$0000000C - .ARM.Collect$$libinit$$0000000E - .ARM.Collect$$libinit$$00000011 - .ARM.Collect$$libinit$$00000013 - .ARM.Collect$$libinit$$00000015 - .ARM.Collect$$libinit$$00000017 - .ARM.Collect$$libinit$$00000019 - .ARM.Collect$$libinit$$0000001B - .ARM.Collect$$libinit$$0000001D - .ARM.Collect$$libinit$$0000001F - .ARM.Collect$$libinit$$00000021 - .ARM.Collect$$libinit$$00000023 - .ARM.Collect$$libinit$$00000025 - .ARM.Collect$$libinit$$0000002C - .ARM.Collect$$libinit$$0000002E - .ARM.Collect$$libinit$$00000030 - .ARM.Collect$$libinit$$00000032 - .ARM.Collect$$libinit$$00000033 - __rt_lib_init_alloca_1 - __rt_lib_init_argv_1 - __rt_lib_init_atexit_1 - __rt_lib_init_clock_1 - __rt_lib_init_cpp_1 - __rt_lib_init_exceptions_1 - __rt_lib_init_fp_1 - __rt_lib_init_fp_trap_1 - __rt_lib_init_getenv_1 - __rt_lib_init_heap_1 - __rt_lib_init_lc_collate_1 - __rt_lib_init_lc_ctype_1 - __rt_lib_init_lc_monetary_1 - __rt_lib_init_lc_numeric_1 - __rt_lib_init_lc_time_1 - __rt_lib_init_preinit_1 - __rt_lib_init_rand_1 - __rt_lib_init_return - __rt_lib_init_signal_1 - __rt_lib_init_stdio_1 - __rt_lib_init_user_alloc_1 - 0x01000462: bd1f .. POP {r0-r4,pc} - .ARM.Collect$$libshutdown$$00000000 - __rt_lib_shutdown - 0x01000464: b510 .. PUSH {r4,lr} - .ARM.Collect$$libshutdown$$00000002 - .ARM.Collect$$libshutdown$$00000004 - .ARM.Collect$$libshutdown$$00000007 - .ARM.Collect$$libshutdown$$0000000A - .ARM.Collect$$libshutdown$$0000000C - .ARM.Collect$$libshutdown$$0000000F - .ARM.Collect$$libshutdown$$00000010 - __rt_lib_shutdown_cpp_1 - __rt_lib_shutdown_fp_trap_1 - __rt_lib_shutdown_heap_1 - __rt_lib_shutdown_return - __rt_lib_shutdown_signal_1 - __rt_lib_shutdown_stdio_1 - __rt_lib_shutdown_user_alloc_1 - 0x01000466: bd10 .. POP {r4,pc} - .ARM.Collect$$rtentry$$00000000 - .ARM.Collect$$rtentry$$00000002 - .ARM.Collect$$rtentry$$00000004 - __rt_entry - __rt_entry_presh_1 - __rt_entry_sh - 0x01000468: f000fab0 .... BL __user_setup_stackheap ; 0x10009cc - 0x0100046c: 4611 .F MOV r1,r2 - .ARM.Collect$$rtentry$$00000009 - .ARM.Collect$$rtentry$$0000000A - __rt_entry_li - __rt_entry_postsh_1 - 0x0100046e: f7fffff7 .... BL __rt_lib_init ; 0x1000460 - .ARM.Collect$$rtentry$$0000000C - .ARM.Collect$$rtentry$$0000000D - __rt_entry_main - __rt_entry_postli_1 - 0x01000472: f000fb09 .... BL main ; 0x1000a88 - 0x01000476: f000fac8 .... BL exit ; 0x1000a0a - .ARM.Collect$$rtexit$$00000000 - __rt_exit - 0x0100047a: b403 .. PUSH {r0,r1} - .ARM.Collect$$rtexit$$00000002 - .ARM.Collect$$rtexit$$00000003 - __rt_exit_ls - __rt_exit_prels_1 - 0x0100047c: f7fffff2 .... BL __rt_lib_shutdown ; 0x1000464 - .ARM.Collect$$rtexit$$00000004 - __rt_exit_exit - 0x01000480: bc03 .. POP {r0,r1} - 0x01000482: f000facf .... BL _sys_exit ; 0x1000a24 - 0x01000486: 0000 .. MOVS r0,r0 - .emb_text - __aeabi_memcpy4 - __aeabi_memcpy8 - 0x01000488: b570 p. PUSH {r4-r6,lr} - 0x0100048a: 4605 .F MOV r5,r0 - 0x0100048c: 460c .F MOV r4,r1 - 0x0100048e: 4616 .F MOV r6,r2 - 0x01000490: e002 .. B 0x1000498 ; __aeabi_memcpy4 + 16 - 0x01000492: cc0f .. LDM r4!,{r0-r3} - 0x01000494: c50f .. STM r5!,{r0-r3} - 0x01000496: 3e10 .> SUBS r6,r6,#0x10 - 0x01000498: 2e10 .. CMP r6,#0x10 - 0x0100049a: d2fa .. BCS 0x1000492 ; __aeabi_memcpy4 + 10 - 0x0100049c: 2e08 .. CMP r6,#8 - 0x0100049e: d302 .. BCC 0x10004a6 ; __aeabi_memcpy4 + 30 - 0x010004a0: cc03 .. LDM r4!,{r0,r1} - 0x010004a2: c503 .. STM r5!,{r0,r1} - 0x010004a4: 3e08 .> SUBS r6,r6,#8 - 0x010004a6: 2e04 .. CMP r6,#4 - 0x010004a8: d307 .. BCC 0x10004ba ; __aeabi_memcpy4 + 50 - 0x010004aa: cc01 .. LDM r4!,{r0} - 0x010004ac: c501 .. STM r5!,{r0} - 0x010004ae: 1f36 6. SUBS r6,r6,#4 - 0x010004b0: e003 .. B 0x10004ba ; __aeabi_memcpy4 + 50 - 0x010004b2: 7821 !x LDRB r1,[r4,#0] - 0x010004b4: 7029 )p STRB r1,[r5,#0] - 0x010004b6: 1c64 d. ADDS r4,r4,#1 - 0x010004b8: 1c6d m. ADDS r5,r5,#1 - 0x010004ba: 1e76 v. SUBS r6,r6,#1 - 0x010004bc: d2f9 .. BCS 0x10004b2 ; __aeabi_memcpy4 + 42 - 0x010004be: bd70 p. POP {r4-r6,pc} - .text - rt_hw_interrupt_disable - 0x010004c0: f3ef8010 .... MRS r0,PRIMASK - 0x010004c4: b672 r. CPSID i - 0x010004c6: 4770 pG BX lr - rt_hw_interrupt_enable - 0x010004c8: f3808810 .... MSR PRIMASK,r0 - 0x010004cc: 4770 pG BX lr - rt_hw_context_switch - rt_hw_context_switch_interrupt - 0x010004ce: 4a2a *J LDR r2,[pc,#168] ; [0x1000578] = 0x20008 - 0x010004d0: 6813 .h LDR r3,[r2,#0] - 0x010004d2: 2b01 .+ CMP r3,#1 - 0x010004d4: d003 .. BEQ 0x10004de ; rt_hw_context_switch + 16 - 0x010004d6: 2301 .# MOVS r3,#1 - 0x010004d8: 6013 .` STR r3,[r2,#0] - 0x010004da: 4a28 (J LDR r2,[pc,#160] ; [0x100057c] = 0x20000 - 0x010004dc: 6010 .` STR r0,[r2,#0] - 0x010004de: 4a28 (J LDR r2,[pc,#160] ; [0x1000580] = 0x20004 - 0x010004e0: 6011 .` STR r1,[r2,#0] - 0x010004e2: 4828 (H LDR r0,[pc,#160] ; [0x1000584] = 0xe000ed04 - 0x010004e4: 4928 (I LDR r1,[pc,#160] ; [0x1000588] = 0x10000000 - 0x010004e6: 6001 .` STR r1,[r0,#0] - 0x010004e8: 4770 pG BX lr - PendSV_Handler - 0x010004ea: f3ef8210 .... MRS r2,PRIMASK - 0x010004ee: b672 r. CPSID i - 0x010004f0: 4821 !H LDR r0,[pc,#132] ; [0x1000578] = 0x20008 - 0x010004f2: 6801 .h LDR r1,[r0,#0] - 0x010004f4: 2900 .) CMP r1,#0 - 0x010004f6: d01d .. BEQ 0x1000534 ; PendSV_Handler + 74 - 0x010004f8: 2100 .! MOVS r1,#0 - 0x010004fa: 6001 .` STR r1,[r0,#0] - 0x010004fc: 481f .H LDR r0,[pc,#124] ; [0x100057c] = 0x20000 - 0x010004fe: 6801 .h LDR r1,[r0,#0] - 0x01000500: 2900 .) CMP r1,#0 - 0x01000502: d00a .. BEQ 0x100051a ; PendSV_Handler + 48 - 0x01000504: f3ef8109 .... MRS r1,PSP - 0x01000508: 3920 9 SUBS r1,r1,#0x20 - 0x0100050a: 6800 .h LDR r0,[r0,#0] - 0x0100050c: 6001 .` STR r1,[r0,#0] - 0x0100050e: c1f0 .. STM r1!,{r4-r7} - 0x01000510: 4644 DF MOV r4,r8 - 0x01000512: 464d MF MOV r5,r9 - 0x01000514: 4656 VF MOV r6,r10 - 0x01000516: 465f _F MOV r7,r11 - 0x01000518: c1f0 .. STM r1!,{r4-r7} - 0x0100051a: 4919 .I LDR r1,[pc,#100] ; [0x1000580] = 0x20004 - 0x0100051c: 6809 .h LDR r1,[r1,#0] - 0x0100051e: 6809 .h LDR r1,[r1,#0] - 0x01000520: c9f0 .. LDM r1!,{r4-r7} - 0x01000522: b4f0 .. PUSH {r4-r7} - 0x01000524: c9f0 .. LDM r1!,{r4-r7} - 0x01000526: 46a0 .F MOV r8,r4 - 0x01000528: 46a9 .F MOV r9,r5 - 0x0100052a: 46b2 .F MOV r10,r6 - 0x0100052c: 46bb .F MOV r11,r7 - 0x0100052e: bcf0 .. POP {r4-r7} - 0x01000530: f3818809 .... MSR PSP,r1 - 0x01000534: f3828810 .... MSR PRIMASK,r2 - 0x01000538: 2004 . MOVS r0,#4 - 0x0100053a: 4240 @B RSBS r0,r0,#0 - 0x0100053c: 4700 .G BX r0 - rt_hw_context_switch_to - 0x0100053e: 4910 .I LDR r1,[pc,#64] ; [0x1000580] = 0x20004 - 0x01000540: 6008 .` STR r0,[r1,#0] - 0x01000542: 490e .I LDR r1,[pc,#56] ; [0x100057c] = 0x20000 - 0x01000544: 2000 . MOVS r0,#0 - 0x01000546: 6008 .` STR r0,[r1,#0] - 0x01000548: 490b .I LDR r1,[pc,#44] ; [0x1000578] = 0x20008 - 0x0100054a: 2001 . MOVS r0,#1 - 0x0100054c: 6008 .` STR r0,[r1,#0] - 0x0100054e: 480f .H LDR r0,[pc,#60] ; [0x100058c] = 0xe000ed20 - 0x01000550: 490f .I LDR r1,[pc,#60] ; [0x1000590] = 0xffff0000 - 0x01000552: 6802 .h LDR r2,[r0,#0] - 0x01000554: 4311 .C ORRS r1,r1,r2 - 0x01000556: 6001 .` STR r1,[r0,#0] - 0x01000558: 480a .H LDR r0,[pc,#40] ; [0x1000584] = 0xe000ed04 - 0x0100055a: 490b .I LDR r1,[pc,#44] ; [0x1000588] = 0x10000000 - 0x0100055c: 6001 .` STR r1,[r0,#0] - 0x0100055e: 480d .H LDR r0,[pc,#52] ; [0x1000594] = 0xe000ed08 - 0x01000560: 6800 .h LDR r0,[r0,#0] - 0x01000562: 6800 .h LDR r0,[r0,#0] - 0x01000564: f3808808 .... MSR MSP,r0 - 0x01000568: b662 b. CPSIE i - rt_hw_interrupt_thread_switch - 0x0100056a: 4770 pG BX lr - HardFault_Handler - 0x0100056c: f3ef8009 .... MRS r0,PSP - 0x01000570: b500 .. PUSH {lr} - 0x01000572: f003fdd1 .... BL rt_hw_hard_fault_exception ; 0x1004118 - 0x01000576: bd00 .. POP {pc} - $d - 0x01000578: 00020008 .... DCD 131080 - 0x0100057c: 00020000 .... DCD 131072 - 0x01000580: 00020004 .... DCD 131076 - 0x01000584: e000ed04 .... DCD 3758157060 - 0x01000588: 10000000 .... DCD 268435456 - 0x0100058c: e000ed20 ... DCD 3758157088 - 0x01000590: ffff0000 .... DCD 4294901760 - 0x01000594: e000ed08 .... DCD 3758157064 - $t - .text - memcmp - 0x01000598: 4603 .F MOV r3,r0 - 0x0100059a: b510 .. PUSH {r4,lr} - 0x0100059c: 430b .C ORRS r3,r3,r1 - 0x0100059e: 079b .. LSLS r3,r3,#30 - 0x010005a0: d10f .. BNE 0x10005c2 ; memcmp + 42 - 0x010005a2: 2a04 .* CMP r2,#4 - 0x010005a4: d30d .. BCC 0x10005c2 ; memcmp + 42 - 0x010005a6: c808 .. LDM r0!,{r3} - 0x010005a8: c910 .. LDM r1!,{r4} - 0x010005aa: 1f12 .. SUBS r2,r2,#4 - 0x010005ac: 42a3 .B CMP r3,r4 - 0x010005ae: d0f8 .. BEQ 0x10005a2 ; memcmp + 10 - 0x010005b0: ba18 .. REV r0,r3 - 0x010005b2: ba21 !. REV r1,r4 - 0x010005b4: 4288 .B CMP r0,r1 - 0x010005b6: d901 .. BLS 0x10005bc ; memcmp + 36 - 0x010005b8: 2001 . MOVS r0,#1 - 0x010005ba: bd10 .. POP {r4,pc} - 0x010005bc: 2000 . MOVS r0,#0 - 0x010005be: 43c0 .C MVNS r0,r0 - 0x010005c0: bd10 .. POP {r4,pc} - 0x010005c2: 2a00 .* CMP r2,#0 - 0x010005c4: d003 .. BEQ 0x10005ce ; memcmp + 54 - 0x010005c6: 07d3 .. LSLS r3,r2,#31 - 0x010005c8: d003 .. BEQ 0x10005d2 ; memcmp + 58 - 0x010005ca: 1c52 R. ADDS r2,r2,#1 - 0x010005cc: e007 .. B 0x10005de ; memcmp + 70 - 0x010005ce: 2000 . MOVS r0,#0 - 0x010005d0: bd10 .. POP {r4,pc} - 0x010005d2: 7803 .x LDRB r3,[r0,#0] - 0x010005d4: 780c .x LDRB r4,[r1,#0] - 0x010005d6: 1c40 @. ADDS r0,r0,#1 - 0x010005d8: 1c49 I. ADDS r1,r1,#1 - 0x010005da: 1b1b .. SUBS r3,r3,r4 - 0x010005dc: d107 .. BNE 0x10005ee ; memcmp + 86 - 0x010005de: 7803 .x LDRB r3,[r0,#0] - 0x010005e0: 780c .x LDRB r4,[r1,#0] - 0x010005e2: 1c40 @. ADDS r0,r0,#1 - 0x010005e4: 1c49 I. ADDS r1,r1,#1 - 0x010005e6: 1b1b .. SUBS r3,r3,r4 - 0x010005e8: d101 .. BNE 0x10005ee ; memcmp + 86 - 0x010005ea: 1e92 .. SUBS r2,r2,#2 - 0x010005ec: d1f1 .. BNE 0x10005d2 ; memcmp + 58 - 0x010005ee: 4618 .F MOV r0,r3 - 0x010005f0: bd10 .. POP {r4,pc} - 0x010005f2: 0000 .. MOVS r0,r0 - .text - strcpy - 0x010005f4: 4603 .F MOV r3,r0 - 0x010005f6: b570 p. PUSH {r4-r6,lr} - 0x010005f8: 4602 .F MOV r2,r0 - 0x010005fa: 430b .C ORRS r3,r3,r1 - 0x010005fc: 079b .. LSLS r3,r3,#30 - 0x010005fe: d10f .. BNE 0x1000620 ; strcpy + 44 - 0x01000600: 4c0e .L LDR r4,[pc,#56] ; [0x100063c] = 0x1010101 - 0x01000602: 01e6 .. LSLS r6,r4,#7 - 0x01000604: e000 .. B 0x1000608 ; strcpy + 20 - 0x01000606: c208 .. STM r2!,{r3} - 0x01000608: c908 .. LDM r1!,{r3} - 0x0100060a: 1b1d .. SUBS r5,r3,r4 - 0x0100060c: 439d .C BICS r5,r5,r3 - 0x0100060e: 4235 5B TST r5,r6 - 0x01000610: d0f9 .. BEQ 0x1000606 ; strcpy + 18 - 0x01000612: b2d9 .. UXTB r1,r3 - 0x01000614: 7011 .p STRB r1,[r2,#0] - 0x01000616: 1c52 R. ADDS r2,r2,#1 - 0x01000618: 2900 .) CMP r1,#0 - 0x0100061a: d00d .. BEQ 0x1000638 ; strcpy + 68 - 0x0100061c: 0a1b .. LSRS r3,r3,#8 - 0x0100061e: e7f8 .. B 0x1000612 ; strcpy + 30 - 0x01000620: 780b .x LDRB r3,[r1,#0] - 0x01000622: 1c49 I. ADDS r1,r1,#1 - 0x01000624: 7013 .p STRB r3,[r2,#0] - 0x01000626: 1c52 R. ADDS r2,r2,#1 - 0x01000628: 2b00 .+ CMP r3,#0 - 0x0100062a: d005 .. BEQ 0x1000638 ; strcpy + 68 - 0x0100062c: 780b .x LDRB r3,[r1,#0] - 0x0100062e: 1c49 I. ADDS r1,r1,#1 - 0x01000630: 7013 .p STRB r3,[r2,#0] - 0x01000632: 1c52 R. ADDS r2,r2,#1 - 0x01000634: 2b00 .+ CMP r3,#0 - 0x01000636: d1f3 .. BNE 0x1000620 ; strcpy + 44 - 0x01000638: bd70 p. POP {r4-r6,pc} - $d - 0x0100063a: 0000 .. DCW 0 - 0x0100063c: 01010101 .... DCD 16843009 - $t - .text - strlen - 0x01000640: b530 0. PUSH {r4,r5,lr} - 0x01000642: 1c44 D. ADDS r4,r0,#1 - 0x01000644: e003 .. B 0x100064e ; strlen + 14 - 0x01000646: 7801 .x LDRB r1,[r0,#0] - 0x01000648: 1c40 @. ADDS r0,r0,#1 - 0x0100064a: 2900 .) CMP r1,#0 - 0x0100064c: d00d .. BEQ 0x100066a ; strlen + 42 - 0x0100064e: 0781 .. LSLS r1,r0,#30 - 0x01000650: d1f9 .. BNE 0x1000646 ; strlen + 6 - 0x01000652: 4b0b .K LDR r3,[pc,#44] ; [0x1000680] = 0x1010101 - 0x01000654: 01dd .. LSLS r5,r3,#7 - 0x01000656: c804 .. LDM r0!,{r2} - 0x01000658: 1ad1 .. SUBS r1,r2,r3 - 0x0100065a: 4391 .C BICS r1,r1,r2 - 0x0100065c: 4029 )@ ANDS r1,r1,r5 - 0x0100065e: d0fa .. BEQ 0x1000656 ; strlen + 22 - 0x01000660: 1b00 .. SUBS r0,r0,r4 - 0x01000662: 060a .. LSLS r2,r1,#24 - 0x01000664: d003 .. BEQ 0x100066e ; strlen + 46 - 0x01000666: 1ec0 .. SUBS r0,r0,#3 - 0x01000668: bd30 0. POP {r4,r5,pc} - 0x0100066a: 1b00 .. SUBS r0,r0,r4 - 0x0100066c: bd30 0. POP {r4,r5,pc} - 0x0100066e: 040a .. LSLS r2,r1,#16 - 0x01000670: d001 .. BEQ 0x1000676 ; strlen + 54 - 0x01000672: 1e80 .. SUBS r0,r0,#2 - 0x01000674: bd30 0. POP {r4,r5,pc} - 0x01000676: 0209 .. LSLS r1,r1,#8 - 0x01000678: d0fc .. BEQ 0x1000674 ; strlen + 52 - 0x0100067a: 1e40 @. SUBS r0,r0,#1 - 0x0100067c: bd30 0. POP {r4,r5,pc} - $d - 0x0100067e: 0000 .. DCW 0 - 0x01000680: 01010101 .... DCD 16843009 - $t - .text - strncmp - 0x01000684: 4603 .F MOV r3,r0 - 0x01000686: b5f0 .. PUSH {r4-r7,lr} - 0x01000688: 430b .C ORRS r3,r3,r1 - 0x0100068a: 079b .. LSLS r3,r3,#30 - 0x0100068c: d12d -. BNE 0x10006ea ; strncmp + 102 - 0x0100068e: 4d24 $M LDR r5,[pc,#144] ; [0x1000720] = 0x1010101 - 0x01000690: 01ef .. LSLS r7,r5,#7 - 0x01000692: 2a04 .* CMP r2,#4 - 0x01000694: d329 ). BCC 0x10006ea ; strncmp + 102 - 0x01000696: c808 .. LDM r0!,{r3} - 0x01000698: c910 .. LDM r1!,{r4} - 0x0100069a: 1b5e ^. SUBS r6,r3,r5 - 0x0100069c: 439e .C BICS r6,r6,r3 - 0x0100069e: 1f12 .. SUBS r2,r2,#4 - 0x010006a0: 403e >@ ANDS r6,r6,r7 - 0x010006a2: d017 .. BEQ 0x10006d4 ; strncmp + 80 - 0x010006a4: b2d8 .. UXTB r0,r3 - 0x010006a6: b2e1 .. UXTB r1,r4 - 0x010006a8: 1a40 @. SUBS r0,r0,r1 - 0x010006aa: 0631 1. LSLS r1,r6,#24 - 0x010006ac: 4301 .C ORRS r1,r1,r0 - 0x010006ae: d110 .. BNE 0x10006d2 ; strncmp + 78 - 0x010006b0: b298 .. UXTH r0,r3 - 0x010006b2: b2a1 .. UXTH r1,r4 - 0x010006b4: 1a40 @. SUBS r0,r0,r1 - 0x010006b6: 0431 1. LSLS r1,r6,#16 - 0x010006b8: 4301 .C ORRS r1,r1,r0 - 0x010006ba: d10a .. BNE 0x10006d2 ; strncmp + 78 - 0x010006bc: 0218 .. LSLS r0,r3,#8 - 0x010006be: 0221 !. LSLS r1,r4,#8 - 0x010006c0: 0a00 .. LSRS r0,r0,#8 - 0x010006c2: 0a09 .. LSRS r1,r1,#8 - 0x010006c4: 1a40 @. SUBS r0,r0,r1 - 0x010006c6: 0231 1. LSLS r1,r6,#8 - 0x010006c8: 4301 .C ORRS r1,r1,r0 - 0x010006ca: d102 .. BNE 0x10006d2 ; strncmp + 78 - 0x010006cc: 0e18 .. LSRS r0,r3,#24 - 0x010006ce: 0e21 !. LSRS r1,r4,#24 - 0x010006d0: 1a40 @. SUBS r0,r0,r1 - 0x010006d2: bdf0 .. POP {r4-r7,pc} - 0x010006d4: 42a3 .B CMP r3,r4 - 0x010006d6: d0dc .. BEQ 0x1000692 ; strncmp + 14 - 0x010006d8: ba18 .. REV r0,r3 - 0x010006da: ba21 !. REV r1,r4 - 0x010006dc: 4288 .B CMP r0,r1 - 0x010006de: d901 .. BLS 0x10006e4 ; strncmp + 96 - 0x010006e0: 2001 . MOVS r0,#1 - 0x010006e2: bdf0 .. POP {r4-r7,pc} - 0x010006e4: 2000 . MOVS r0,#0 - 0x010006e6: 43c0 .C MVNS r0,r0 - 0x010006e8: bdf0 .. POP {r4-r7,pc} - 0x010006ea: 2a00 .* CMP r2,#0 - 0x010006ec: d101 .. BNE 0x10006f2 ; strncmp + 110 - 0x010006ee: 2000 . MOVS r0,#0 - 0x010006f0: bdf0 .. POP {r4-r7,pc} - 0x010006f2: 7803 .x LDRB r3,[r0,#0] - 0x010006f4: 780c .x LDRB r4,[r1,#0] - 0x010006f6: 1c40 @. ADDS r0,r0,#1 - 0x010006f8: 1c49 I. ADDS r1,r1,#1 - 0x010006fa: 2b00 .+ CMP r3,#0 - 0x010006fc: d00d .. BEQ 0x100071a ; strncmp + 150 - 0x010006fe: 42a3 .B CMP r3,r4 - 0x01000700: d10b .. BNE 0x100071a ; strncmp + 150 - 0x01000702: 1e52 R. SUBS r2,r2,#1 - 0x01000704: d009 .. BEQ 0x100071a ; strncmp + 150 - 0x01000706: 7803 .x LDRB r3,[r0,#0] - 0x01000708: 780c .x LDRB r4,[r1,#0] - 0x0100070a: 1c40 @. ADDS r0,r0,#1 - 0x0100070c: 1c49 I. ADDS r1,r1,#1 - 0x0100070e: 2b00 .+ CMP r3,#0 - 0x01000710: d003 .. BEQ 0x100071a ; strncmp + 150 - 0x01000712: 42a3 .B CMP r3,r4 - 0x01000714: d101 .. BNE 0x100071a ; strncmp + 150 - 0x01000716: 1e52 R. SUBS r2,r2,#1 - 0x01000718: d1eb .. BNE 0x10006f2 ; strncmp + 110 - 0x0100071a: 1b18 .. SUBS r0,r3,r4 - 0x0100071c: bdf0 .. POP {r4-r7,pc} - $d - 0x0100071e: 0000 .. DCW 0 - 0x01000720: 01010101 .... DCD 16843009 - $t - .text - strcat - 0x01000724: 1e42 B. SUBS r2,r0,#1 - 0x01000726: 7853 Sx LDRB r3,[r2,#1] - 0x01000728: 1c52 R. ADDS r2,r2,#1 - 0x0100072a: 2b00 .+ CMP r3,#0 - 0x0100072c: d1fb .. BNE 0x1000726 ; strcat + 2 - 0x0100072e: 780b .x LDRB r3,[r1,#0] - 0x01000730: 1c49 I. ADDS r1,r1,#1 - 0x01000732: 7013 .p STRB r3,[r2,#0] - 0x01000734: 1c52 R. ADDS r2,r2,#1 - 0x01000736: 2b00 .+ CMP r3,#0 - 0x01000738: d1f9 .. BNE 0x100072e ; strcat + 10 - 0x0100073a: 4770 pG BX lr - .text - __aeabi_memcpy - __rt_memcpy - 0x0100073c: b5f8 .. PUSH {r3-r7,lr} - 0x0100073e: 2a04 .* CMP r2,#4 - 0x01000740: d32c ,. BCC 0x100079c ; __aeabi_memcpy + 96 - 0x01000742: 0783 .. LSLS r3,r0,#30 - 0x01000744: d012 .. BEQ 0x100076c ; __aeabi_memcpy + 48 - 0x01000746: 780b .x LDRB r3,[r1,#0] - 0x01000748: 1c49 I. ADDS r1,r1,#1 - 0x0100074a: 7003 .p STRB r3,[r0,#0] - 0x0100074c: 1c40 @. ADDS r0,r0,#1 - 0x0100074e: 1e52 R. SUBS r2,r2,#1 - 0x01000750: 0783 .. LSLS r3,r0,#30 - 0x01000752: d00b .. BEQ 0x100076c ; __aeabi_memcpy + 48 - 0x01000754: 780b .x LDRB r3,[r1,#0] - 0x01000756: 1c49 I. ADDS r1,r1,#1 - 0x01000758: 7003 .p STRB r3,[r0,#0] - 0x0100075a: 1c40 @. ADDS r0,r0,#1 - 0x0100075c: 1e52 R. SUBS r2,r2,#1 - 0x0100075e: 0783 .. LSLS r3,r0,#30 - 0x01000760: d004 .. BEQ 0x100076c ; __aeabi_memcpy + 48 - 0x01000762: 780b .x LDRB r3,[r1,#0] - 0x01000764: 1c49 I. ADDS r1,r1,#1 - 0x01000766: 7003 .p STRB r3,[r0,#0] - 0x01000768: 1c40 @. ADDS r0,r0,#1 - 0x0100076a: 1e52 R. SUBS r2,r2,#1 - 0x0100076c: 078b .. LSLS r3,r1,#30 - 0x0100076e: 0f9b .. LSRS r3,r3,#30 - 0x01000770: d005 .. BEQ 0x100077e ; __aeabi_memcpy + 66 - 0x01000772: 1ac9 .. SUBS r1,r1,r3 - 0x01000774: 00df .. LSLS r7,r3,#3 - 0x01000776: 2320 # MOVS r3,#0x20 - 0x01000778: 1bde .. SUBS r6,r3,r7 - 0x0100077a: c908 .. LDM r1!,{r3} - 0x0100077c: e00a .. B 0x1000794 ; __aeabi_memcpy + 88 - 0x0100077e: f7fffe83 .... BL __aeabi_memcpy4 ; 0x1000488 - 0x01000782: bdf8 .. POP {r3-r7,pc} - 0x01000784: 461d .F MOV r5,r3 - 0x01000786: c908 .. LDM r1!,{r3} - 0x01000788: 40fd .@ LSRS r5,r5,r7 - 0x0100078a: 461c .F MOV r4,r3 - 0x0100078c: 40b4 .@ LSLS r4,r4,r6 - 0x0100078e: 432c ,C ORRS r4,r4,r5 - 0x01000790: c010 .. STM r0!,{r4} - 0x01000792: 1f12 .. SUBS r2,r2,#4 - 0x01000794: 2a04 .* CMP r2,#4 - 0x01000796: d2f5 .. BCS 0x1000784 ; __aeabi_memcpy + 72 - 0x01000798: 08f3 .. LSRS r3,r6,#3 - 0x0100079a: 1ac9 .. SUBS r1,r1,r3 - 0x0100079c: 1e52 R. SUBS r2,r2,#1 - 0x0100079e: d4f0 .. BMI 0x1000782 ; __aeabi_memcpy + 70 - 0x010007a0: 780b .x LDRB r3,[r1,#0] - 0x010007a2: 1c49 I. ADDS r1,r1,#1 - 0x010007a4: 7003 .p STRB r3,[r0,#0] - 0x010007a6: 1c40 @. ADDS r0,r0,#1 - 0x010007a8: 1e52 R. SUBS r2,r2,#1 - 0x010007aa: d4ea .. BMI 0x1000782 ; __aeabi_memcpy + 70 - 0x010007ac: 780b .x LDRB r3,[r1,#0] - 0x010007ae: 1c49 I. ADDS r1,r1,#1 - 0x010007b0: 7003 .p STRB r3,[r0,#0] - 0x010007b2: 1c40 @. ADDS r0,r0,#1 - 0x010007b4: 2a01 .* CMP r2,#1 - 0x010007b6: d4e4 .. BMI 0x1000782 ; __aeabi_memcpy + 70 - 0x010007b8: 7809 .x LDRB r1,[r1,#0] - 0x010007ba: 7001 .p STRB r1,[r0,#0] - 0x010007bc: bdf8 .. POP {r3-r7,pc} - .text - _memset_w - 0x010007be: e001 .. B 0x10007c4 ; _memset_w + 6 - 0x010007c0: c004 .. STM r0!,{r2} - 0x010007c2: 1f09 .. SUBS r1,r1,#4 - 0x010007c4: 2904 .) CMP r1,#4 - 0x010007c6: d2fb .. BCS 0x10007c0 ; _memset_w + 2 - 0x010007c8: 078b .. LSLS r3,r1,#30 - 0x010007ca: d501 .. BPL 0x10007d0 ; _memset_w + 18 - 0x010007cc: 8002 .. STRH r2,[r0,#0] - 0x010007ce: 1c80 .. ADDS r0,r0,#2 - 0x010007d0: 07c9 .. LSLS r1,r1,#31 - 0x010007d2: d000 .. BEQ 0x10007d6 ; _memset_w + 24 - 0x010007d4: 7002 .p STRB r2,[r0,#0] - 0x010007d6: 4770 pG BX lr - _memset - 0x010007d8: 2900 .) CMP r1,#0 - 0x010007da: d00b .. BEQ 0x10007f4 ; _memset + 28 - 0x010007dc: 07c3 .. LSLS r3,r0,#31 - 0x010007de: d002 .. BEQ 0x10007e6 ; _memset + 14 - 0x010007e0: 7002 .p STRB r2,[r0,#0] - 0x010007e2: 1c40 @. ADDS r0,r0,#1 - 0x010007e4: 1e49 I. SUBS r1,r1,#1 - 0x010007e6: 2902 .) CMP r1,#2 - 0x010007e8: d304 .. BCC 0x10007f4 ; _memset + 28 - 0x010007ea: 0783 .. LSLS r3,r0,#30 - 0x010007ec: d502 .. BPL 0x10007f4 ; _memset + 28 - 0x010007ee: 8002 .. STRH r2,[r0,#0] - 0x010007f0: 1c80 .. ADDS r0,r0,#2 - 0x010007f2: 1e89 .. SUBS r1,r1,#2 - 0x010007f4: e7e3 .. B _memset_w ; 0x10007be - __aeabi_memclr - __rt_memclr - 0x010007f6: 2200 ." MOVS r2,#0 - 0x010007f8: e7ee .. B _memset ; 0x10007d8 - __aeabi_memclr4 - __aeabi_memclr8 - __rt_memclr_w - 0x010007fa: 2200 ." MOVS r2,#0 - 0x010007fc: e7df .. B _memset_w ; 0x10007be - 0x010007fe: 0000 .. MOVS r0,r0 - .text - strncpy - 0x01000800: b5f8 .. PUSH {r3-r7,lr} - 0x01000802: 4607 .F MOV r7,r0 - 0x01000804: 460b .F MOV r3,r1 - 0x01000806: 4639 9F MOV r1,r7 - 0x01000808: 4319 .C ORRS r1,r1,r3 - 0x0100080a: 0789 .. LSLS r1,r1,#30 - 0x0100080c: d113 .. BNE 0x1000836 ; strncpy + 54 - 0x0100080e: 4c16 .L LDR r4,[pc,#88] ; [0x1000868] = 0x1010101 - 0x01000810: 01e6 .. LSLS r6,r4,#7 - 0x01000812: 2a04 .* CMP r2,#4 - 0x01000814: d30f .. BCC 0x1000836 ; strncpy + 54 - 0x01000816: cb02 .. LDM r3!,{r1} - 0x01000818: 1b0d .. SUBS r5,r1,r4 - 0x0100081a: 438d .C BICS r5,r5,r1 - 0x0100081c: 4235 5B TST r5,r6 - 0x0100081e: d102 .. BNE 0x1000826 ; strncpy + 38 - 0x01000820: c002 .. STM r0!,{r1} - 0x01000822: 1f12 .. SUBS r2,r2,#4 - 0x01000824: e7f5 .. B 0x1000812 ; strncpy + 18 - 0x01000826: b2cb .. UXTB r3,r1 - 0x01000828: 7003 .p STRB r3,[r0,#0] - 0x0100082a: 1c40 @. ADDS r0,r0,#1 - 0x0100082c: 1e52 R. SUBS r2,r2,#1 - 0x0100082e: 2b00 .+ CMP r3,#0 - 0x01000830: d013 .. BEQ 0x100085a ; strncpy + 90 - 0x01000832: 0a09 .. LSRS r1,r1,#8 - 0x01000834: e7f7 .. B 0x1000826 ; strncpy + 38 - 0x01000836: 2a00 .* CMP r2,#0 - 0x01000838: d014 .. BEQ 0x1000864 ; strncpy + 100 - 0x0100083a: 7819 .x LDRB r1,[r3,#0] - 0x0100083c: 1e52 R. SUBS r2,r2,#1 - 0x0100083e: 1c5b [. ADDS r3,r3,#1 - 0x01000840: 7001 .p STRB r1,[r0,#0] - 0x01000842: 1c40 @. ADDS r0,r0,#1 - 0x01000844: 2900 .) CMP r1,#0 - 0x01000846: d008 .. BEQ 0x100085a ; strncpy + 90 - 0x01000848: 2a00 .* CMP r2,#0 - 0x0100084a: d00b .. BEQ 0x1000864 ; strncpy + 100 - 0x0100084c: 7819 .x LDRB r1,[r3,#0] - 0x0100084e: 1e52 R. SUBS r2,r2,#1 - 0x01000850: 1c5b [. ADDS r3,r3,#1 - 0x01000852: 7001 .p STRB r1,[r0,#0] - 0x01000854: 1c40 @. ADDS r0,r0,#1 - 0x01000856: 2900 .) CMP r1,#0 - 0x01000858: d1ed .. BNE 0x1000836 ; strncpy + 54 - 0x0100085a: 2a00 .* CMP r2,#0 - 0x0100085c: d002 .. BEQ 0x1000864 ; strncpy + 100 - 0x0100085e: 4611 .F MOV r1,r2 - 0x01000860: f7ffffc9 .... BL __aeabi_memclr ; 0x10007f6 - 0x01000864: 4638 8F MOV r0,r7 - 0x01000866: bdf8 .. POP {r3-r7,pc} - $d - 0x01000868: 01010101 .... DCD 16843009 - $t - .text - __aeabi_uidiv - __aeabi_uidivmod - 0x0100086c: 2200 ." MOVS r2,#0 - 0x0100086e: 0903 .. LSRS r3,r0,#4 - 0x01000870: 428b .B CMP r3,r1 - 0x01000872: d32c ,. BCC 0x10008ce ; __aeabi_idiv + 78 - 0x01000874: 0a03 .. LSRS r3,r0,#8 - 0x01000876: 428b .B CMP r3,r1 - 0x01000878: d311 .. BCC 0x100089e ; __aeabi_idiv + 30 - 0x0100087a: 2300 .# MOVS r3,#0 - 0x0100087c: 469c .F MOV r12,r3 - 0x0100087e: e04e N. B 0x100091e ; __aeabi_idiv + 158 - __aeabi_idiv - __aeabi_idivmod - 0x01000880: 4603 .F MOV r3,r0 - 0x01000882: 430b .C ORRS r3,r3,r1 - 0x01000884: d43c <. BMI 0x1000900 ; __aeabi_idiv + 128 - 0x01000886: 2200 ." MOVS r2,#0 - 0x01000888: 0843 C. LSRS r3,r0,#1 - 0x0100088a: 428b .B CMP r3,r1 - 0x0100088c: d331 1. BCC 0x10008f2 ; __aeabi_idiv + 114 - 0x0100088e: 0903 .. LSRS r3,r0,#4 - 0x01000890: 428b .B CMP r3,r1 - 0x01000892: d31c .. BCC 0x10008ce ; __aeabi_idiv + 78 - 0x01000894: 0a03 .. LSRS r3,r0,#8 - 0x01000896: 428b .B CMP r3,r1 - 0x01000898: d301 .. BCC 0x100089e ; __aeabi_idiv + 30 - 0x0100089a: 4694 .F MOV r12,r2 - 0x0100089c: e03f ?. B 0x100091e ; __aeabi_idiv + 158 - 0x0100089e: 09c3 .. LSRS r3,r0,#7 - 0x010008a0: 428b .B CMP r3,r1 - 0x010008a2: d301 .. BCC 0x10008a8 ; __aeabi_idiv + 40 - 0x010008a4: 01cb .. LSLS r3,r1,#7 - 0x010008a6: 1ac0 .. SUBS r0,r0,r3 - 0x010008a8: 4152 RA ADCS r2,r2,r2 - 0x010008aa: 0983 .. LSRS r3,r0,#6 - 0x010008ac: 428b .B CMP r3,r1 - 0x010008ae: d301 .. BCC 0x10008b4 ; __aeabi_idiv + 52 - 0x010008b0: 018b .. LSLS r3,r1,#6 - 0x010008b2: 1ac0 .. SUBS r0,r0,r3 - 0x010008b4: 4152 RA ADCS r2,r2,r2 - 0x010008b6: 0943 C. LSRS r3,r0,#5 - 0x010008b8: 428b .B CMP r3,r1 - 0x010008ba: d301 .. BCC 0x10008c0 ; __aeabi_idiv + 64 - 0x010008bc: 014b K. LSLS r3,r1,#5 - 0x010008be: 1ac0 .. SUBS r0,r0,r3 - 0x010008c0: 4152 RA ADCS r2,r2,r2 - 0x010008c2: 0903 .. LSRS r3,r0,#4 - 0x010008c4: 428b .B CMP r3,r1 - 0x010008c6: d301 .. BCC 0x10008cc ; __aeabi_idiv + 76 - 0x010008c8: 010b .. LSLS r3,r1,#4 - 0x010008ca: 1ac0 .. SUBS r0,r0,r3 - 0x010008cc: 4152 RA ADCS r2,r2,r2 - 0x010008ce: 08c3 .. LSRS r3,r0,#3 - 0x010008d0: 428b .B CMP r3,r1 - 0x010008d2: d301 .. BCC 0x10008d8 ; __aeabi_idiv + 88 - 0x010008d4: 00cb .. LSLS r3,r1,#3 - 0x010008d6: 1ac0 .. SUBS r0,r0,r3 - 0x010008d8: 4152 RA ADCS r2,r2,r2 - 0x010008da: 0883 .. LSRS r3,r0,#2 - 0x010008dc: 428b .B CMP r3,r1 - 0x010008de: d301 .. BCC 0x10008e4 ; __aeabi_idiv + 100 - 0x010008e0: 008b .. LSLS r3,r1,#2 - 0x010008e2: 1ac0 .. SUBS r0,r0,r3 - 0x010008e4: 4152 RA ADCS r2,r2,r2 - 0x010008e6: 0843 C. LSRS r3,r0,#1 - 0x010008e8: 428b .B CMP r3,r1 - 0x010008ea: d301 .. BCC 0x10008f0 ; __aeabi_idiv + 112 - 0x010008ec: 004b K. LSLS r3,r1,#1 - 0x010008ee: 1ac0 .. SUBS r0,r0,r3 - 0x010008f0: 4152 RA ADCS r2,r2,r2 - 0x010008f2: 1a41 A. SUBS r1,r0,r1 - 0x010008f4: d200 .. BCS 0x10008f8 ; __aeabi_idiv + 120 - 0x010008f6: 4601 .F MOV r1,r0 - 0x010008f8: 4152 RA ADCS r2,r2,r2 - 0x010008fa: 4610 .F MOV r0,r2 - 0x010008fc: 4770 pG BX lr - 0x010008fe: e05d ]. B 0x10009bc ; __aeabi_idiv + 316 - 0x01000900: 0fca .. LSRS r2,r1,#31 - 0x01000902: d000 .. BEQ 0x1000906 ; __aeabi_idiv + 134 - 0x01000904: 4249 IB RSBS r1,r1,#0 - 0x01000906: 1003 .. ASRS r3,r0,#32 - 0x01000908: d300 .. BCC 0x100090c ; __aeabi_idiv + 140 - 0x0100090a: 4240 @B RSBS r0,r0,#0 - 0x0100090c: 4053 S@ EORS r3,r3,r2 - 0x0100090e: 2200 ." MOVS r2,#0 - 0x01000910: 469c .F MOV r12,r3 - 0x01000912: 0903 .. LSRS r3,r0,#4 - 0x01000914: 428b .B CMP r3,r1 - 0x01000916: d32d -. BCC 0x1000974 ; __aeabi_idiv + 244 - 0x01000918: 0a03 .. LSRS r3,r0,#8 - 0x0100091a: 428b .B CMP r3,r1 - 0x0100091c: d312 .. BCC 0x1000944 ; __aeabi_idiv + 196 - 0x0100091e: 22fc ." MOVS r2,#0xfc - 0x01000920: 0189 .. LSLS r1,r1,#6 - 0x01000922: ba12 .. REV r2,r2 - 0x01000924: 0a03 .. LSRS r3,r0,#8 - 0x01000926: 428b .B CMP r3,r1 - 0x01000928: d30c .. BCC 0x1000944 ; __aeabi_idiv + 196 - 0x0100092a: 0189 .. LSLS r1,r1,#6 - 0x0100092c: 1192 .. ASRS r2,r2,#6 - 0x0100092e: 428b .B CMP r3,r1 - 0x01000930: d308 .. BCC 0x1000944 ; __aeabi_idiv + 196 - 0x01000932: 0189 .. LSLS r1,r1,#6 - 0x01000934: 1192 .. ASRS r2,r2,#6 - 0x01000936: 428b .B CMP r3,r1 - 0x01000938: d304 .. BCC 0x1000944 ; __aeabi_idiv + 196 - 0x0100093a: 0189 .. LSLS r1,r1,#6 - 0x0100093c: d03a :. BEQ 0x10009b4 ; __aeabi_idiv + 308 - 0x0100093e: 1192 .. ASRS r2,r2,#6 - 0x01000940: e000 .. B 0x1000944 ; __aeabi_idiv + 196 - 0x01000942: 0989 .. LSRS r1,r1,#6 - 0x01000944: 09c3 .. LSRS r3,r0,#7 - 0x01000946: 428b .B CMP r3,r1 - 0x01000948: d301 .. BCC 0x100094e ; __aeabi_idiv + 206 - 0x0100094a: 01cb .. LSLS r3,r1,#7 - 0x0100094c: 1ac0 .. SUBS r0,r0,r3 - 0x0100094e: 4152 RA ADCS r2,r2,r2 - 0x01000950: 0983 .. LSRS r3,r0,#6 - 0x01000952: 428b .B CMP r3,r1 - 0x01000954: d301 .. BCC 0x100095a ; __aeabi_idiv + 218 - 0x01000956: 018b .. LSLS r3,r1,#6 - 0x01000958: 1ac0 .. SUBS r0,r0,r3 - 0x0100095a: 4152 RA ADCS r2,r2,r2 - 0x0100095c: 0943 C. LSRS r3,r0,#5 - 0x0100095e: 428b .B CMP r3,r1 - 0x01000960: d301 .. BCC 0x1000966 ; __aeabi_idiv + 230 - 0x01000962: 014b K. LSLS r3,r1,#5 - 0x01000964: 1ac0 .. SUBS r0,r0,r3 - 0x01000966: 4152 RA ADCS r2,r2,r2 - 0x01000968: 0903 .. LSRS r3,r0,#4 - 0x0100096a: 428b .B CMP r3,r1 - 0x0100096c: d301 .. BCC 0x1000972 ; __aeabi_idiv + 242 - 0x0100096e: 010b .. LSLS r3,r1,#4 - 0x01000970: 1ac0 .. SUBS r0,r0,r3 - 0x01000972: 4152 RA ADCS r2,r2,r2 - 0x01000974: 08c3 .. LSRS r3,r0,#3 - 0x01000976: 428b .B CMP r3,r1 - 0x01000978: d301 .. BCC 0x100097e ; __aeabi_idiv + 254 - 0x0100097a: 00cb .. LSLS r3,r1,#3 - 0x0100097c: 1ac0 .. SUBS r0,r0,r3 - 0x0100097e: 4152 RA ADCS r2,r2,r2 - 0x01000980: 0883 .. LSRS r3,r0,#2 - 0x01000982: 428b .B CMP r3,r1 - 0x01000984: d301 .. BCC 0x100098a ; __aeabi_idiv + 266 - 0x01000986: 008b .. LSLS r3,r1,#2 - 0x01000988: 1ac0 .. SUBS r0,r0,r3 - 0x0100098a: 4152 RA ADCS r2,r2,r2 - 0x0100098c: d2d9 .. BCS 0x1000942 ; __aeabi_idiv + 194 - 0x0100098e: 0843 C. LSRS r3,r0,#1 - 0x01000990: 428b .B CMP r3,r1 - 0x01000992: d301 .. BCC 0x1000998 ; __aeabi_idiv + 280 - 0x01000994: 004b K. LSLS r3,r1,#1 - 0x01000996: 1ac0 .. SUBS r0,r0,r3 - 0x01000998: 4152 RA ADCS r2,r2,r2 - 0x0100099a: 1a41 A. SUBS r1,r0,r1 - 0x0100099c: d200 .. BCS 0x10009a0 ; __aeabi_idiv + 288 - 0x0100099e: 4601 .F MOV r1,r0 - 0x010009a0: 4663 cF MOV r3,r12 - 0x010009a2: 4152 RA ADCS r2,r2,r2 - 0x010009a4: 105b [. ASRS r3,r3,#1 - 0x010009a6: 4610 .F MOV r0,r2 - 0x010009a8: d301 .. BCC 0x10009ae ; __aeabi_idiv + 302 - 0x010009aa: 4240 @B RSBS r0,r0,#0 - 0x010009ac: 2b00 .+ CMP r3,#0 - 0x010009ae: d500 .. BPL 0x10009b2 ; __aeabi_idiv + 306 - 0x010009b0: 4249 IB RSBS r1,r1,#0 - 0x010009b2: 4770 pG BX lr - 0x010009b4: 4663 cF MOV r3,r12 - 0x010009b6: 105b [. ASRS r3,r3,#1 - 0x010009b8: d300 .. BCC 0x10009bc ; __aeabi_idiv + 316 - 0x010009ba: 4240 @B RSBS r0,r0,#0 - 0x010009bc: b501 .. PUSH {r0,lr} - 0x010009be: 2000 . MOVS r0,#0 - 0x010009c0: 46c0 .F MOV r8,r8 - 0x010009c2: 46c0 .F MOV r8,r8 - 0x010009c4: bd02 .. POP {r1,pc} - .text - __use_two_region_memory - 0x010009c6: 4770 pG BX lr - __rt_heap_escrow$2region - 0x010009c8: 4770 pG BX lr - __rt_heap_expand$2region - 0x010009ca: 4770 pG BX lr - .text - __user_setup_stackheap - 0x010009cc: 4675 uF MOV r5,lr - 0x010009ce: f000f825 ..%. BL __user_libspace ; 0x1000a1c - 0x010009d2: 46ae .F MOV lr,r5 - 0x010009d4: 0005 .. MOVS r5,r0 - 0x010009d6: 4669 iF MOV r1,sp - 0x010009d8: 4653 SF MOV r3,r10 - 0x010009da: 08c0 .. LSRS r0,r0,#3 - 0x010009dc: 00c0 .. LSLS r0,r0,#3 - 0x010009de: 4685 .F MOV sp,r0 - 0x010009e0: b018 .. ADD sp,sp,#0x60 - 0x010009e2: b520 . PUSH {r5,lr} - 0x010009e4: f7fffcac .... BL __user_initial_stackheap ; 0x1000340 - 0x010009e8: bc60 `. POP {r5,r6} - 0x010009ea: 2700 .' MOVS r7,#0 - 0x010009ec: 0849 I. LSRS r1,r1,#1 - 0x010009ee: 46b6 .F MOV lr,r6 - 0x010009f0: 2600 .& MOVS r6,#0 - 0x010009f2: c5c0 .. STM r5!,{r6,r7} - 0x010009f4: c5c0 .. STM r5!,{r6,r7} - 0x010009f6: c5c0 .. STM r5!,{r6,r7} - 0x010009f8: c5c0 .. STM r5!,{r6,r7} - 0x010009fa: c5c0 .. STM r5!,{r6,r7} - 0x010009fc: c5c0 .. STM r5!,{r6,r7} - 0x010009fe: c5c0 .. STM r5!,{r6,r7} - 0x01000a00: c5c0 .. STM r5!,{r6,r7} - 0x01000a02: 3d40 @= SUBS r5,r5,#0x40 - 0x01000a04: 0049 I. LSLS r1,r1,#1 - 0x01000a06: 468d .F MOV sp,r1 - 0x01000a08: 4770 pG BX lr - .text - exit - 0x01000a0a: b510 .. PUSH {r4,lr} - 0x01000a0c: 4604 .F MOV r4,r0 - 0x01000a0e: 46c0 .F MOV r8,r8 - 0x01000a10: 46c0 .F MOV r8,r8 - 0x01000a12: 4620 F MOV r0,r4 - 0x01000a14: f7fffd31 ..1. BL __rt_exit ; 0x100047a - 0x01000a18: bd10 .. POP {r4,pc} - 0x01000a1a: 0000 .. MOVS r0,r0 - .text - __user_libspace - __user_perproc_libspace - __user_perthread_libspace - 0x01000a1c: 4800 .H LDR r0,[pc,#0] ; [0x1000a20] = 0x20da4 - 0x01000a1e: 4770 pG BX lr - $d - 0x01000a20: 00020da4 .... DCD 134564 - $t - .text - _sys_exit - 0x01000a24: 4901 .I LDR r1,[pc,#4] ; [0x1000a2c] = 0x20026 - 0x01000a26: 2018 . MOVS r0,#0x18 - 0x01000a28: beab .. BKPT #0xab - 0x01000a2a: e7fe .. B 0x1000a2a ; _sys_exit + 6 - $d - 0x01000a2c: 00020026 &... DCD 131110 - $t - .text - __I$use$semihosting - __use_no_semihosting_swi - 0x01000a30: 4770 pG BX lr - .text - .text - __decompress - __decompress1 - __semihosting_library_function - 0x01000a32: b570 p. PUSH {r4-r6,lr} - 0x01000a34: 188c .. ADDS r4,r1,r2 - 0x01000a36: 7805 .x LDRB r5,[r0,#0] - 0x01000a38: 1c40 @. ADDS r0,r0,#1 - 0x01000a3a: 076b k. LSLS r3,r5,#29 - 0x01000a3c: 0f5b [. LSRS r3,r3,#29 - 0x01000a3e: d101 .. BNE 0x1000a44 ; __decompress + 18 - 0x01000a40: 7803 .x LDRB r3,[r0,#0] - 0x01000a42: 1c40 @. ADDS r0,r0,#1 - 0x01000a44: 112a *. ASRS r2,r5,#4 - 0x01000a46: d106 .. BNE 0x1000a56 ; __decompress + 36 - 0x01000a48: 7802 .x LDRB r2,[r0,#0] - 0x01000a4a: 1c40 @. ADDS r0,r0,#1 - 0x01000a4c: e003 .. B 0x1000a56 ; __decompress + 36 - 0x01000a4e: 7806 .x LDRB r6,[r0,#0] - 0x01000a50: 1c40 @. ADDS r0,r0,#1 - 0x01000a52: 700e .p STRB r6,[r1,#0] - 0x01000a54: 1c49 I. ADDS r1,r1,#1 - 0x01000a56: 1e5b [. SUBS r3,r3,#1 - 0x01000a58: d1f9 .. BNE 0x1000a4e ; __decompress + 28 - 0x01000a5a: 072b +. LSLS r3,r5,#28 - 0x01000a5c: d405 .. BMI 0x1000a6a ; __decompress + 56 - 0x01000a5e: 2300 .# MOVS r3,#0 - 0x01000a60: 1e52 R. SUBS r2,r2,#1 - 0x01000a62: d40d .. BMI 0x1000a80 ; __decompress + 78 - 0x01000a64: 700b .p STRB r3,[r1,#0] - 0x01000a66: 1c49 I. ADDS r1,r1,#1 - 0x01000a68: e7fa .. B 0x1000a60 ; __decompress + 46 - 0x01000a6a: 7803 .x LDRB r3,[r0,#0] - 0x01000a6c: 1c40 @. ADDS r0,r0,#1 - 0x01000a6e: 1acb .. SUBS r3,r1,r3 - 0x01000a70: 1c92 .. ADDS r2,r2,#2 - 0x01000a72: e003 .. B 0x1000a7c ; __decompress + 74 - 0x01000a74: 781d .x LDRB r5,[r3,#0] - 0x01000a76: 700d .p STRB r5,[r1,#0] - 0x01000a78: 1c49 I. ADDS r1,r1,#1 - 0x01000a7a: 1c5b [. ADDS r3,r3,#1 - 0x01000a7c: 1e52 R. SUBS r2,r2,#1 - 0x01000a7e: d5f9 .. BPL 0x1000a74 ; __decompress + 66 - 0x01000a80: 42a1 .B CMP r1,r4 - 0x01000a82: d3d8 .. BCC 0x1000a36 ; __decompress + 4 - 0x01000a84: 2000 . MOVS r0,#0 - 0x01000a86: bd70 p. POP {r4-r6,pc} - i.$Sub$$main - main - 0x01000a88: b510 .. PUSH {r4,lr} - 0x01000a8a: f006f8f0 .... BL rtthread_startup ; 0x1006c6e - 0x01000a8e: 2000 . MOVS r0,#0 - 0x01000a90: bd10 .. POP {r4,pc} - 0x01000a92: 0000 .. MOVS r0,r0 - i.NVIC_DisableIRQ - NVIC_DisableIRQ - 0x01000a94: bf00 .. NOP - 0x01000a96: 2101 .! MOVS r1,#1 - 0x01000a98: 4081 .@ LSLS r1,r1,r0 - 0x01000a9a: 4a02 .J LDR r2,[pc,#8] ; [0x1000aa4] = 0xe000e180 - 0x01000a9c: 6011 .` STR r1,[r2,#0] - 0x01000a9e: bf00 .. NOP - 0x01000aa0: 4770 pG BX lr - $d - 0x01000aa2: 0000 .. DCW 0 - 0x01000aa4: e000e180 .... DCD 3758154112 - $t - i.NVIC_EnableIRQ - NVIC_EnableIRQ - 0x01000aa8: bf00 .. NOP - 0x01000aaa: 4904 .I LDR r1,[pc,#16] ; [0x1000abc] = 0xe000e100 - 0x01000aac: 6809 .h LDR r1,[r1,#0] - 0x01000aae: 2201 ." MOVS r2,#1 - 0x01000ab0: 4082 .@ LSLS r2,r2,r0 - 0x01000ab2: 4311 .C ORRS r1,r1,r2 - 0x01000ab4: 4a01 .J LDR r2,[pc,#4] ; [0x1000abc] = 0xe000e100 - 0x01000ab6: 6011 .` STR r1,[r2,#0] - 0x01000ab8: bf00 .. NOP - 0x01000aba: 4770 pG BX lr - $d - 0x01000abc: e000e100 .... DCD 3758153984 - $t - i.SysTick_Config - SysTick_Config - 0x01000ac0: 4601 .F MOV r1,r0 - 0x01000ac2: 1e49 I. SUBS r1,r1,#1 - 0x01000ac4: 2900 .) CMP r1,#0 - 0x01000ac6: d002 .. BEQ 0x1000ace ; SysTick_Config + 14 - 0x01000ac8: 480c .H LDR r0,[pc,#48] ; [0x1000afc] = 0xffffff - 0x01000aca: 4281 .B CMP r1,r0 - 0x01000acc: d901 .. BLS 0x1000ad2 ; SysTick_Config + 18 - 0x01000ace: 2001 . MOVS r0,#1 - 0x01000ad0: 4770 pG BX lr - 0x01000ad2: 480b .H LDR r0,[pc,#44] ; [0x1000b00] = 0xe000e000 - 0x01000ad4: 6900 .i LDR r0,[r0,#0x10] - 0x01000ad6: 0840 @. LSRS r0,r0,#1 - 0x01000ad8: 0040 @. LSLS r0,r0,#1 - 0x01000ada: 4a09 .J LDR r2,[pc,#36] ; [0x1000b00] = 0xe000e000 - 0x01000adc: 6110 .a STR r0,[r2,#0x10] - 0x01000ade: 4610 .F MOV r0,r2 - 0x01000ae0: 6141 Aa STR r1,[r0,#0x14] - 0x01000ae2: 2000 . MOVS r0,#0 - 0x01000ae4: 6190 .a STR r0,[r2,#0x18] - 0x01000ae6: 4a07 .J LDR r2,[pc,#28] ; [0x1000b04] = 0x20154 - 0x01000ae8: 6010 .` STR r0,[r2,#0] - 0x01000aea: 4805 .H LDR r0,[pc,#20] ; [0x1000b00] = 0xe000e000 - 0x01000aec: 6900 .i LDR r0,[r0,#0x10] - 0x01000aee: 2207 ." MOVS r2,#7 - 0x01000af0: 4310 .C ORRS r0,r0,r2 - 0x01000af2: 4a03 .J LDR r2,[pc,#12] ; [0x1000b00] = 0xe000e000 - 0x01000af4: 6110 .a STR r0,[r2,#0x10] - 0x01000af6: 2000 . MOVS r0,#0 - 0x01000af8: e7ea .. B 0x1000ad0 ; SysTick_Config + 16 - $d - 0x01000afa: 0000 .. DCW 0 - 0x01000afc: 00ffffff .... DCD 16777215 - 0x01000b00: e000e000 .... DCD 3758153728 - 0x01000b04: 00020154 T... DCD 131412 - $t - i.SysTick_Handler - SysTick_Handler - 0x01000b08: b510 .. PUSH {r4,lr} - 0x01000b0a: f003fc9b .... BL rt_interrupt_enter ; 0x1004444 - 0x01000b0e: f005fbed .... BL rt_tick_increase ; 0x10062ec - 0x01000b12: f003fcc1 .... BL rt_interrupt_leave ; 0x1004498 - 0x01000b16: bd10 .. POP {r4,pc} - i.UART0_IRQHandler - UART0_IRQHandler - 0x01000b18: b510 .. PUSH {r4,lr} - 0x01000b1a: f003fc93 .... BL rt_interrupt_enter ; 0x1004444 - 0x01000b1e: 4906 .I LDR r1,[pc,#24] ; [0x1000b38] = 0x20010 - 0x01000b20: 7808 .x LDRB r0,[r1,#0] - 0x01000b22: f000f80d .... BL UART_GetITIdentity ; 0x1000b40 - 0x01000b26: 2802 .( CMP r0,#2 - 0x01000b28: d103 .. BNE 0x1000b32 ; UART0_IRQHandler + 26 - 0x01000b2a: 2101 .! MOVS r1,#1 - 0x01000b2c: 4803 .H LDR r0,[pc,#12] ; [0x1000b3c] = 0x2019c - 0x01000b2e: f003fb7b ..{. BL rt_hw_serial_isr ; 0x1004228 - 0x01000b32: f003fcb1 .... BL rt_interrupt_leave ; 0x1004498 - 0x01000b36: bd10 .. POP {r4,pc} - $d - 0x01000b38: 00020010 .... DCD 131088 - 0x01000b3c: 0002019c .... DCD 131484 - $t - i.UART_GetITIdentity - UART_GetITIdentity - 0x01000b40: 4601 .F MOV r1,r0 - 0x01000b42: 2000 . MOVS r0,#0 - 0x01000b44: 2900 .) CMP r1,#0 - 0x01000b46: d002 .. BEQ 0x1000b4e ; UART_GetITIdentity + 14 - 0x01000b48: 2901 .) CMP r1,#1 - 0x01000b4a: d130 0. BNE 0x1000bae ; UART_GetITIdentity + 110 - 0x01000b4c: e017 .. B 0x1000b7e ; UART_GetITIdentity + 62 - 0x01000b4e: 4a19 .J LDR r2,[pc,#100] ; [0x1000bb4] = 0xf8b00 - 0x01000b50: 69d2 .i LDR r2,[r2,#0x1c] - 0x01000b52: 23ff .# MOVS r3,#0xff - 0x01000b54: 021b .. LSLS r3,r3,#8 - 0x01000b56: 401a .@ ANDS r2,r2,r3 - 0x01000b58: 2a00 .* CMP r2,#0 - 0x01000b5a: dd06 .. BLE 0x1000b6a ; UART_GetITIdentity + 42 - 0x01000b5c: 4a15 .J LDR r2,[pc,#84] ; [0x1000bb4] = 0xf8b00 - 0x01000b5e: 6a92 .j LDR r2,[r2,#0x28] - 0x01000b60: 1412 .. ASRS r2,r2,#16 - 0x01000b62: 2a00 .* CMP r2,#0 - 0x01000b64: dd01 .. BLE 0x1000b6a ; UART_GetITIdentity + 42 - 0x01000b66: 2002 . MOVS r0,#2 - 0x01000b68: e008 .. B 0x1000b7c ; UART_GetITIdentity + 60 - 0x01000b6a: 4a12 .J LDR r2,[pc,#72] ; [0x1000bb4] = 0xf8b00 - 0x01000b6c: 69d2 .i LDR r2,[r2,#0x1c] - 0x01000b6e: 0fd2 .. LSRS r2,r2,#31 - 0x01000b70: 07d2 .. LSLS r2,r2,#31 - 0x01000b72: 2a00 .* CMP r2,#0 - 0x01000b74: d001 .. BEQ 0x1000b7a ; UART_GetITIdentity + 58 - 0x01000b76: 2001 . MOVS r0,#1 - 0x01000b78: e000 .. B 0x1000b7c ; UART_GetITIdentity + 60 - 0x01000b7a: 2000 . MOVS r0,#0 - 0x01000b7c: e017 .. B 0x1000bae ; UART_GetITIdentity + 110 - 0x01000b7e: 4a0e .J LDR r2,[pc,#56] ; [0x1000bb8] = 0xf8c00 - 0x01000b80: 69d2 .i LDR r2,[r2,#0x1c] - 0x01000b82: 23ff .# MOVS r3,#0xff - 0x01000b84: 021b .. LSLS r3,r3,#8 - 0x01000b86: 401a .@ ANDS r2,r2,r3 - 0x01000b88: 2a00 .* CMP r2,#0 - 0x01000b8a: dd06 .. BLE 0x1000b9a ; UART_GetITIdentity + 90 - 0x01000b8c: 4a0a .J LDR r2,[pc,#40] ; [0x1000bb8] = 0xf8c00 - 0x01000b8e: 6a92 .j LDR r2,[r2,#0x28] - 0x01000b90: 1412 .. ASRS r2,r2,#16 - 0x01000b92: 2a00 .* CMP r2,#0 - 0x01000b94: dd01 .. BLE 0x1000b9a ; UART_GetITIdentity + 90 - 0x01000b96: 2002 . MOVS r0,#2 - 0x01000b98: e008 .. B 0x1000bac ; UART_GetITIdentity + 108 - 0x01000b9a: 4a07 .J LDR r2,[pc,#28] ; [0x1000bb8] = 0xf8c00 - 0x01000b9c: 69d2 .i LDR r2,[r2,#0x1c] - 0x01000b9e: 0fd2 .. LSRS r2,r2,#31 - 0x01000ba0: 07d2 .. LSLS r2,r2,#31 - 0x01000ba2: 2a00 .* CMP r2,#0 - 0x01000ba4: d001 .. BEQ 0x1000baa ; UART_GetITIdentity + 106 - 0x01000ba6: 2001 . MOVS r0,#1 - 0x01000ba8: e000 .. B 0x1000bac ; UART_GetITIdentity + 108 - 0x01000baa: 2000 . MOVS r0,#0 - 0x01000bac: bf00 .. NOP - 0x01000bae: bf00 .. NOP - 0x01000bb0: 4770 pG BX lr - $d - 0x01000bb2: 0000 .. DCW 0 - 0x01000bb4: 000f8b00 .... DCD 1018624 - 0x01000bb8: 000f8c00 .... DCD 1018880 - $t - i.UART_ITConfig - UART_ITConfig - 0x01000bbc: b570 p. PUSH {r4-r6,lr} - 0x01000bbe: 4606 .F MOV r6,r0 - 0x01000bc0: 460c .F MOV r4,r1 - 0x01000bc2: 4615 .F MOV r5,r2 - 0x01000bc4: 2e00 .. CMP r6,#0 - 0x01000bc6: d006 .. BEQ 0x1000bd6 ; UART_ITConfig + 26 - 0x01000bc8: 2e01 .. CMP r6,#1 - 0x01000bca: d004 .. BEQ 0x1000bd6 ; UART_ITConfig + 26 - 0x01000bcc: 4a2c ,J LDR r2,[pc,#176] ; [0x1000c80] = 0x1007c9e - 0x01000bce: 21f3 .! MOVS r1,#0xf3 - 0x01000bd0: a02c ,. ADR r0,{pc}+0xb4 ; 0x1000c84 - 0x01000bd2: f000fa3b ..;. BL _assert_handler ; 0x100104c - 0x01000bd6: 2c01 ., CMP r4,#1 - 0x01000bd8: d006 .. BEQ 0x1000be8 ; UART_ITConfig + 44 - 0x01000bda: 2c02 ., CMP r4,#2 - 0x01000bdc: d004 .. BEQ 0x1000be8 ; UART_ITConfig + 44 - 0x01000bde: 4a28 (J LDR r2,[pc,#160] ; [0x1000c80] = 0x1007c9e - 0x01000be0: 21f4 .! MOVS r1,#0xf4 - 0x01000be2: a028 (. ADR r0,{pc}+0xa2 ; 0x1000c84 - 0x01000be4: f000fa32 ..2. BL _assert_handler ; 0x100104c - 0x01000be8: 2e00 .. CMP r6,#0 - 0x01000bea: d002 .. BEQ 0x1000bf2 ; UART_ITConfig + 54 - 0x01000bec: 2e01 .. CMP r6,#1 - 0x01000bee: d144 D. BNE 0x1000c7a ; UART_ITConfig + 190 - 0x01000bf0: e021 !. B 0x1000c36 ; UART_ITConfig + 122 - 0x01000bf2: 2c02 ., CMP r4,#2 - 0x01000bf4: d110 .. BNE 0x1000c18 ; UART_ITConfig + 92 - 0x01000bf6: 2d00 .- CMP r5,#0 - 0x01000bf8: d006 .. BEQ 0x1000c08 ; UART_ITConfig + 76 - 0x01000bfa: 4828 (H LDR r0,[pc,#160] ; [0x1000c9c] = 0xf8b00 - 0x01000bfc: 69c0 .i LDR r0,[r0,#0x1c] - 0x01000bfe: 01e1 .. LSLS r1,r4,#7 - 0x01000c00: 4308 .C ORRS r0,r0,r1 - 0x01000c02: 4926 &I LDR r1,[pc,#152] ; [0x1000c9c] = 0xf8b00 - 0x01000c04: 61c8 .a STR r0,[r1,#0x1c] - 0x01000c06: e015 .. B 0x1000c34 ; UART_ITConfig + 120 - 0x01000c08: 4824 $H LDR r0,[pc,#144] ; [0x1000c9c] = 0xf8b00 - 0x01000c0a: 69c0 .i LDR r0,[r0,#0x1c] - 0x01000c0c: 21ff .! MOVS r1,#0xff - 0x01000c0e: 0209 .. LSLS r1,r1,#8 - 0x01000c10: 4388 .C BICS r0,r0,r1 - 0x01000c12: 4922 "I LDR r1,[pc,#136] ; [0x1000c9c] = 0xf8b00 - 0x01000c14: 61c8 .a STR r0,[r1,#0x1c] - 0x01000c16: e00d .. B 0x1000c34 ; UART_ITConfig + 120 - 0x01000c18: 2c01 ., CMP r4,#1 - 0x01000c1a: d10b .. BNE 0x1000c34 ; UART_ITConfig + 120 - 0x01000c1c: 481f .H LDR r0,[pc,#124] ; [0x1000c9c] = 0xf8b00 - 0x01000c1e: 69c0 .i LDR r0,[r0,#0x1c] - 0x01000c20: 0040 @. LSLS r0,r0,#1 - 0x01000c22: 0840 @. LSRS r0,r0,#1 - 0x01000c24: 491d .I LDR r1,[pc,#116] ; [0x1000c9c] = 0xf8b00 - 0x01000c26: 61c8 .a STR r0,[r1,#0x1c] - 0x01000c28: 4608 .F MOV r0,r1 - 0x01000c2a: 69c0 .i LDR r0,[r0,#0x1c] - 0x01000c2c: 07e9 .. LSLS r1,r5,#31 - 0x01000c2e: 4308 .C ORRS r0,r0,r1 - 0x01000c30: 491a .I LDR r1,[pc,#104] ; [0x1000c9c] = 0xf8b00 - 0x01000c32: 61c8 .a STR r0,[r1,#0x1c] - 0x01000c34: e021 !. B 0x1000c7a ; UART_ITConfig + 190 - 0x01000c36: 2c02 ., CMP r4,#2 - 0x01000c38: d110 .. BNE 0x1000c5c ; UART_ITConfig + 160 - 0x01000c3a: 2d00 .- CMP r5,#0 - 0x01000c3c: d006 .. BEQ 0x1000c4c ; UART_ITConfig + 144 - 0x01000c3e: 4818 .H LDR r0,[pc,#96] ; [0x1000ca0] = 0xf8c00 - 0x01000c40: 69c0 .i LDR r0,[r0,#0x1c] - 0x01000c42: 01e1 .. LSLS r1,r4,#7 - 0x01000c44: 4308 .C ORRS r0,r0,r1 - 0x01000c46: 4916 .I LDR r1,[pc,#88] ; [0x1000ca0] = 0xf8c00 - 0x01000c48: 61c8 .a STR r0,[r1,#0x1c] - 0x01000c4a: e015 .. B 0x1000c78 ; UART_ITConfig + 188 - 0x01000c4c: 4814 .H LDR r0,[pc,#80] ; [0x1000ca0] = 0xf8c00 - 0x01000c4e: 69c0 .i LDR r0,[r0,#0x1c] - 0x01000c50: 21ff .! MOVS r1,#0xff - 0x01000c52: 0209 .. LSLS r1,r1,#8 - 0x01000c54: 4388 .C BICS r0,r0,r1 - 0x01000c56: 4912 .I LDR r1,[pc,#72] ; [0x1000ca0] = 0xf8c00 - 0x01000c58: 61c8 .a STR r0,[r1,#0x1c] - 0x01000c5a: e00d .. B 0x1000c78 ; UART_ITConfig + 188 - 0x01000c5c: 2c01 ., CMP r4,#1 - 0x01000c5e: d10b .. BNE 0x1000c78 ; UART_ITConfig + 188 - 0x01000c60: 480f .H LDR r0,[pc,#60] ; [0x1000ca0] = 0xf8c00 - 0x01000c62: 69c0 .i LDR r0,[r0,#0x1c] - 0x01000c64: 0040 @. LSLS r0,r0,#1 - 0x01000c66: 0840 @. LSRS r0,r0,#1 - 0x01000c68: 490d .I LDR r1,[pc,#52] ; [0x1000ca0] = 0xf8c00 - 0x01000c6a: 61c8 .a STR r0,[r1,#0x1c] - 0x01000c6c: 4608 .F MOV r0,r1 - 0x01000c6e: 69c0 .i LDR r0,[r0,#0x1c] - 0x01000c70: 07e9 .. LSLS r1,r5,#31 - 0x01000c72: 4308 .C ORRS r0,r0,r1 - 0x01000c74: 490a .I LDR r1,[pc,#40] ; [0x1000ca0] = 0xf8c00 - 0x01000c76: 61c8 .a STR r0,[r1,#0x1c] - 0x01000c78: bf00 .. NOP - 0x01000c7a: bf00 .. NOP - 0x01000c7c: bd70 p. POP {r4-r6,pc} - $d - 0x01000c7e: 0000 .. DCW 0 - 0x01000c80: 01007c9e .|.. DCD 16809118 - 0x01000c84: 7262694c Libr DCD 1919052108 - 0x01000c88: 65697261 arie DCD 1701409377 - 0x01000c8c: 64735c73 s\sd DCD 1685281907 - 0x01000c90: 63795c6b k\yc DCD 1668897899 - 0x01000c94: 7261755f _uar DCD 1918989663 - 0x01000c98: 00632e74 t.c. DCD 6499956 - 0x01000c9c: 000f8b00 .... DCD 1018624 - 0x01000ca0: 000f8c00 .... DCD 1018880 - $t - i.UART_Init - UART_Init - 0x01000ca4: b5f8 .. PUSH {r3-r7,lr} - 0x01000ca6: 4605 .F MOV r5,r0 - 0x01000ca8: 460c .F MOV r4,r1 - 0x01000caa: 2600 .& MOVS r6,#0 - 0x01000cac: 2700 .' MOVS r7,#0 - 0x01000cae: 2d00 .- CMP r5,#0 - 0x01000cb0: d006 .. BEQ 0x1000cc0 ; UART_Init + 28 - 0x01000cb2: 2d01 .- CMP r5,#1 - 0x01000cb4: d004 .. BEQ 0x1000cc0 ; UART_Init + 28 - 0x01000cb6: 4a47 GJ LDR r2,[pc,#284] ; [0x1000dd4] = 0x1007c5c - 0x01000cb8: 219a .! MOVS r1,#0x9a - 0x01000cba: a047 G. ADR r0,{pc}+0x11e ; 0x1000dd8 - 0x01000cbc: f000f9c6 .... BL _assert_handler ; 0x100104c - 0x01000cc0: 7820 x LDRB r0,[r4,#0] - 0x01000cc2: 2840 @( CMP r0,#0x40 - 0x01000cc4: d007 .. BEQ 0x1000cd6 ; UART_Init + 50 - 0x01000cc6: 7820 x LDRB r0,[r4,#0] - 0x01000cc8: 2800 .( CMP r0,#0 - 0x01000cca: d004 .. BEQ 0x1000cd6 ; UART_Init + 50 - 0x01000ccc: 4a41 AJ LDR r2,[pc,#260] ; [0x1000dd4] = 0x1007c5c - 0x01000cce: 219b .! MOVS r1,#0x9b - 0x01000cd0: a041 A. ADR r0,{pc}+0x108 ; 0x1000dd8 - 0x01000cd2: f000f9bb .... BL _assert_handler ; 0x100104c - 0x01000cd6: 21b7 .! MOVS r1,#0xb7 - 0x01000cd8: 00c9 .. LSLS r1,r1,#3 - 0x01000cda: 6860 `h LDR r0,[r4,#4] - 0x01000cdc: 4288 .B CMP r0,r1 - 0x01000cde: d903 .. BLS 0x1000ce8 ; UART_Init + 68 - 0x01000ce0: 4943 CI LDR r1,[pc,#268] ; [0x1000df0] = 0x44aa21 - 0x01000ce2: 6860 `h LDR r0,[r4,#4] - 0x01000ce4: 4288 .B CMP r0,r1 - 0x01000ce6: d304 .. BCC 0x1000cf2 ; UART_Init + 78 - 0x01000ce8: 4a3a :J LDR r2,[pc,#232] ; [0x1000dd4] = 0x1007c5c - 0x01000cea: 219c .! MOVS r1,#0x9c - 0x01000cec: a03a :. ADR r0,{pc}+0xec ; 0x1000dd8 - 0x01000cee: f000f9ad .... BL _assert_handler ; 0x100104c - 0x01000cf2: 7aa0 .z LDRB r0,[r4,#0xa] - 0x01000cf4: 2800 .( CMP r0,#0 - 0x01000cf6: d00a .. BEQ 0x1000d0e ; UART_Init + 106 - 0x01000cf8: 7aa0 .z LDRB r0,[r4,#0xa] - 0x01000cfa: 2800 .( CMP r0,#0 - 0x01000cfc: d007 .. BEQ 0x1000d0e ; UART_Init + 106 - 0x01000cfe: 7aa0 .z LDRB r0,[r4,#0xa] - 0x01000d00: 2802 .( CMP r0,#2 - 0x01000d02: d004 .. BEQ 0x1000d0e ; UART_Init + 106 - 0x01000d04: 4a33 3J LDR r2,[pc,#204] ; [0x1000dd4] = 0x1007c5c - 0x01000d06: 219d .! MOVS r1,#0x9d - 0x01000d08: a033 3. ADR r0,{pc}+0xd0 ; 0x1000dd8 - 0x01000d0a: f000f99f .... BL _assert_handler ; 0x100104c - 0x01000d0e: 7ae0 .z LDRB r0,[r4,#0xb] - 0x01000d10: 2800 .( CMP r0,#0 - 0x01000d12: d007 .. BEQ 0x1000d24 ; UART_Init + 128 - 0x01000d14: 7ae0 .z LDRB r0,[r4,#0xb] - 0x01000d16: 2810 .( CMP r0,#0x10 - 0x01000d18: d004 .. BEQ 0x1000d24 ; UART_Init + 128 - 0x01000d1a: 4a2e .J LDR r2,[pc,#184] ; [0x1000dd4] = 0x1007c5c - 0x01000d1c: 219e .! MOVS r1,#0x9e - 0x01000d1e: a02e .. ADR r0,{pc}+0xba ; 0x1000dd8 - 0x01000d20: f000f994 .... BL _assert_handler ; 0x100104c - 0x01000d24: 7a60 `z LDRB r0,[r4,#9] - 0x01000d26: 2800 .( CMP r0,#0 - 0x01000d28: d007 .. BEQ 0x1000d3a ; UART_Init + 150 - 0x01000d2a: 7a60 `z LDRB r0,[r4,#9] - 0x01000d2c: 2808 .( CMP r0,#8 - 0x01000d2e: d004 .. BEQ 0x1000d3a ; UART_Init + 150 - 0x01000d30: 4a28 (J LDR r2,[pc,#160] ; [0x1000dd4] = 0x1007c5c - 0x01000d32: 219f .! MOVS r1,#0x9f - 0x01000d34: a028 (. ADR r0,{pc}+0xa4 ; 0x1000dd8 - 0x01000d36: f000f989 .... BL _assert_handler ; 0x100104c - 0x01000d3a: 482e .H LDR r0,[pc,#184] ; [0x1000df4] = 0x2dc6c00 - 0x01000d3c: 6861 ah LDR r1,[r4,#4] - 0x01000d3e: f7fffd95 .... BL __aeabi_uidiv ; 0x100086c - 0x01000d42: 0407 .. LSLS r7,r0,#16 - 0x01000d44: 7aa0 .z LDRB r0,[r4,#0xa] - 0x01000d46: 2101 .! MOVS r1,#1 - 0x01000d48: 4308 .C ORRS r0,r0,r1 - 0x01000d4a: 7a21 !z LDRB r1,[r4,#8] - 0x01000d4c: 4308 .C ORRS r0,r0,r1 - 0x01000d4e: 7a61 az LDRB r1,[r4,#9] - 0x01000d50: 4308 .C ORRS r0,r0,r1 - 0x01000d52: 7ae1 .z LDRB r1,[r4,#0xb] - 0x01000d54: 4308 .C ORRS r0,r0,r1 - 0x01000d56: 7821 !x LDRB r1,[r4,#0] - 0x01000d58: 4308 .C ORRS r0,r0,r1 - 0x01000d5a: 2180 .! MOVS r1,#0x80 - 0x01000d5c: 4308 .C ORRS r0,r0,r1 - 0x01000d5e: 4338 8C ORRS r0,r0,r7 - 0x01000d60: 4606 .F MOV r6,r0 - 0x01000d62: 2d00 .- CMP r5,#0 - 0x01000d64: d11a .. BNE 0x1000d9c ; UART_Init + 248 - 0x01000d66: 2000 . MOVS r0,#0 - 0x01000d68: 4923 #I LDR r1,[pc,#140] ; [0x1000df8] = 0xf8b00 - 0x01000d6a: 61c8 .a STR r0,[r1,#0x1c] - 0x01000d6c: 4823 #H LDR r0,[pc,#140] ; [0x1000dfc] = 0x205a4 - 0x01000d6e: 6048 H` STR r0,[r1,#4] - 0x01000d70: 2001 . MOVS r0,#1 - 0x01000d72: 0280 .. LSLS r0,r0,#10 - 0x01000d74: 6088 .` STR r0,[r1,#8] - 0x01000d76: 2001 . MOVS r0,#1 - 0x01000d78: 7308 .s STRB r0,[r1,#0xc] - 0x01000d7a: 4608 .F MOV r0,r1 - 0x01000d7c: 7bc0 .{ LDRB r0,[r0,#0xf] - 0x01000d7e: 2120 ! MOVS r1,#0x20 - 0x01000d80: 4308 .C ORRS r0,r0,r1 - 0x01000d82: 491d .I LDR r1,[pc,#116] ; [0x1000df8] = 0xf8b00 - 0x01000d84: 73c8 .s STRB r0,[r1,#0xf] - 0x01000d86: 4608 .F MOV r0,r1 - 0x01000d88: 7bc0 .{ LDRB r0,[r0,#0xf] - 0x01000d8a: 2120 ! MOVS r1,#0x20 - 0x01000d8c: 4388 .C BICS r0,r0,r1 - 0x01000d8e: 491a .I LDR r1,[pc,#104] ; [0x1000df8] = 0xf8b00 - 0x01000d90: 73c8 .s STRB r0,[r1,#0xf] - 0x01000d92: 2000 . MOVS r0,#0 - 0x01000d94: 61c8 .a STR r0,[r1,#0x1c] - 0x01000d96: 4608 .F MOV r0,r1 - 0x01000d98: 61c6 .a STR r6,[r0,#0x1c] - 0x01000d9a: e019 .. B 0x1000dd0 ; UART_Init + 300 - 0x01000d9c: 2000 . MOVS r0,#0 - 0x01000d9e: 4918 .I LDR r1,[pc,#96] ; [0x1000e00] = 0xf8c00 - 0x01000da0: 61c8 .a STR r0,[r1,#0x1c] - 0x01000da2: 4818 .H LDR r0,[pc,#96] ; [0x1000e04] = 0x209a4 - 0x01000da4: 6048 H` STR r0,[r1,#4] - 0x01000da6: 2001 . MOVS r0,#1 - 0x01000da8: 0280 .. LSLS r0,r0,#10 - 0x01000daa: 6088 .` STR r0,[r1,#8] - 0x01000dac: 2001 . MOVS r0,#1 - 0x01000dae: 7308 .s STRB r0,[r1,#0xc] - 0x01000db0: 4608 .F MOV r0,r1 - 0x01000db2: 7bc0 .{ LDRB r0,[r0,#0xf] - 0x01000db4: 2120 ! MOVS r1,#0x20 - 0x01000db6: 4308 .C ORRS r0,r0,r1 - 0x01000db8: 4911 .I LDR r1,[pc,#68] ; [0x1000e00] = 0xf8c00 - 0x01000dba: 73c8 .s STRB r0,[r1,#0xf] - 0x01000dbc: 4608 .F MOV r0,r1 - 0x01000dbe: 7bc0 .{ LDRB r0,[r0,#0xf] - 0x01000dc0: 2120 ! MOVS r1,#0x20 - 0x01000dc2: 4388 .C BICS r0,r0,r1 - 0x01000dc4: 490e .I LDR r1,[pc,#56] ; [0x1000e00] = 0xf8c00 - 0x01000dc6: 73c8 .s STRB r0,[r1,#0xf] - 0x01000dc8: 2000 . MOVS r0,#0 - 0x01000dca: 61c8 .a STR r0,[r1,#0x1c] - 0x01000dcc: 4608 .F MOV r0,r1 - 0x01000dce: 61c6 .a STR r6,[r0,#0x1c] - 0x01000dd0: bdf8 .. POP {r3-r7,pc} - $d - 0x01000dd2: 0000 .. DCW 0 - 0x01000dd4: 01007c5c \|.. DCD 16809052 - 0x01000dd8: 7262694c Libr DCD 1919052108 - 0x01000ddc: 65697261 arie DCD 1701409377 - 0x01000de0: 64735c73 s\sd DCD 1685281907 - 0x01000de4: 63795c6b k\yc DCD 1668897899 - 0x01000de8: 7261755f _uar DCD 1918989663 - 0x01000dec: 00632e74 t.c. DCD 6499956 - 0x01000df0: 0044aa21 !.D. DCD 4500001 - 0x01000df4: 02dc6c00 .l.. DCD 48000000 - 0x01000df8: 000f8b00 .... DCD 1018624 - 0x01000dfc: 000205a4 .... DCD 132516 - 0x01000e00: 000f8c00 .... DCD 1018880 - 0x01000e04: 000209a4 .... DCD 133540 - $t - i.UART_IsUARTBusy - UART_IsUARTBusy - 0x01000e08: b510 .. PUSH {r4,lr} - 0x01000e0a: 4604 .F MOV r4,r0 - 0x01000e0c: 2c00 ., CMP r4,#0 - 0x01000e0e: d006 .. BEQ 0x1000e1e ; UART_IsUARTBusy + 22 - 0x01000e10: 2c01 ., CMP r4,#1 - 0x01000e12: d004 .. BEQ 0x1000e1e ; UART_IsUARTBusy + 22 - 0x01000e14: 4a0a .J LDR r2,[pc,#40] ; [0x1000e40] = 0x1007c8e - 0x01000e16: 21e5 .! MOVS r1,#0xe5 - 0x01000e18: a00a .. ADR r0,{pc}+0x2c ; 0x1000e44 - 0x01000e1a: f000f917 .... BL _assert_handler ; 0x100104c - 0x01000e1e: 2c00 ., CMP r4,#0 - 0x01000e20: d106 .. BNE 0x1000e30 ; UART_IsUARTBusy + 40 - 0x01000e22: 480e .H LDR r0,[pc,#56] ; [0x1000e5c] = 0xf8b00 - 0x01000e24: 6900 .i LDR r0,[r0,#0x10] - 0x01000e26: 07c0 .. LSLS r0,r0,#31 - 0x01000e28: 0fc0 .. LSRS r0,r0,#31 - 0x01000e2a: 2101 .! MOVS r1,#1 - 0x01000e2c: 4048 H@ EORS r0,r0,r1 - 0x01000e2e: bd10 .. POP {r4,pc} - 0x01000e30: 480b .H LDR r0,[pc,#44] ; [0x1000e60] = 0xf8c00 - 0x01000e32: 6900 .i LDR r0,[r0,#0x10] - 0x01000e34: 07c0 .. LSLS r0,r0,#31 - 0x01000e36: 0fc0 .. LSRS r0,r0,#31 - 0x01000e38: 2101 .! MOVS r1,#1 - 0x01000e3a: 4048 H@ EORS r0,r0,r1 - 0x01000e3c: e7f7 .. B 0x1000e2e ; UART_IsUARTBusy + 38 - $d - 0x01000e3e: 0000 .. DCW 0 - 0x01000e40: 01007c8e .|.. DCD 16809102 - 0x01000e44: 7262694c Libr DCD 1919052108 - 0x01000e48: 65697261 arie DCD 1701409377 - 0x01000e4c: 64735c73 s\sd DCD 1685281907 - 0x01000e50: 63795c6b k\yc DCD 1668897899 - 0x01000e54: 7261755f _uar DCD 1918989663 - 0x01000e58: 00632e74 t.c. DCD 6499956 - 0x01000e5c: 000f8b00 .... DCD 1018624 - 0x01000e60: 000f8c00 .... DCD 1018880 - $t - i.UART_ReceiveData - UART_ReceiveData - 0x01000e64: b510 .. PUSH {r4,lr} - 0x01000e66: 4604 .F MOV r4,r0 - 0x01000e68: 2c00 ., CMP r4,#0 - 0x01000e6a: d007 .. BEQ 0x1000e7c ; UART_ReceiveData + 24 - 0x01000e6c: 2c01 ., CMP r4,#1 - 0x01000e6e: d005 .. BEQ 0x1000e7c ; UART_ReceiveData + 24 - 0x01000e70: 4a06 .J LDR r2,[pc,#24] ; [0x1000e8c] = 0x1007cac - 0x01000e72: 21ff .! MOVS r1,#0xff - 0x01000e74: 3128 (1 ADDS r1,r1,#0x28 - 0x01000e76: a006 .. ADR r0,{pc}+0x1a ; 0x1000e90 - 0x01000e78: f000f8e8 .... BL _assert_handler ; 0x100104c - 0x01000e7c: 2c00 ., CMP r4,#0 - 0x01000e7e: d102 .. BNE 0x1000e86 ; UART_ReceiveData + 34 - 0x01000e80: 4809 .H LDR r0,[pc,#36] ; [0x1000ea8] = 0xf8b20 - 0x01000e82: 7900 .y LDRB r0,[r0,#4] - 0x01000e84: bd10 .. POP {r4,pc} - 0x01000e86: 4809 .H LDR r0,[pc,#36] ; [0x1000eac] = 0xf8c20 - 0x01000e88: 7900 .y LDRB r0,[r0,#4] - 0x01000e8a: e7fb .. B 0x1000e84 ; UART_ReceiveData + 32 - $d - 0x01000e8c: 01007cac .|.. DCD 16809132 - 0x01000e90: 7262694c Libr DCD 1919052108 - 0x01000e94: 65697261 arie DCD 1701409377 - 0x01000e98: 64735c73 s\sd DCD 1685281907 - 0x01000e9c: 63795c6b k\yc DCD 1668897899 - 0x01000ea0: 7261755f _uar DCD 1918989663 - 0x01000ea4: 00632e74 t.c. DCD 6499956 - 0x01000ea8: 000f8b20 ... DCD 1018656 - 0x01000eac: 000f8c20 ... DCD 1018912 - $t - i.UART_ReceiveDataLen - UART_ReceiveDataLen - 0x01000eb0: b510 .. PUSH {r4,lr} - 0x01000eb2: 4604 .F MOV r4,r0 - 0x01000eb4: 2c00 ., CMP r4,#0 - 0x01000eb6: d007 .. BEQ 0x1000ec8 ; UART_ReceiveDataLen + 24 - 0x01000eb8: 2c01 ., CMP r4,#1 - 0x01000eba: d005 .. BEQ 0x1000ec8 ; UART_ReceiveDataLen + 24 - 0x01000ebc: 4a07 .J LDR r2,[pc,#28] ; [0x1000edc] = 0x1007ce7 - 0x01000ebe: 21ff .! MOVS r1,#0xff - 0x01000ec0: 31a8 .1 ADDS r1,r1,#0xa8 - 0x01000ec2: a007 .. ADR r0,{pc}+0x1e ; 0x1000ee0 - 0x01000ec4: f000f8c2 .... BL _assert_handler ; 0x100104c - 0x01000ec8: 2c00 ., CMP r4,#0 - 0x01000eca: d103 .. BNE 0x1000ed4 ; UART_ReceiveDataLen + 36 - 0x01000ecc: 480a .H LDR r0,[pc,#40] ; [0x1000ef8] = 0xf8b00 - 0x01000ece: 6a80 .j LDR r0,[r0,#0x28] - 0x01000ed0: 0c00 .. LSRS r0,r0,#16 - 0x01000ed2: bd10 .. POP {r4,pc} - 0x01000ed4: 4809 .H LDR r0,[pc,#36] ; [0x1000efc] = 0xf8c00 - 0x01000ed6: 6a80 .j LDR r0,[r0,#0x28] - 0x01000ed8: 0c00 .. LSRS r0,r0,#16 - 0x01000eda: e7fa .. B 0x1000ed2 ; UART_ReceiveDataLen + 34 - $d - 0x01000edc: 01007ce7 .|.. DCD 16809191 - 0x01000ee0: 7262694c Libr DCD 1919052108 - 0x01000ee4: 65697261 arie DCD 1701409377 - 0x01000ee8: 64735c73 s\sd DCD 1685281907 - 0x01000eec: 63795c6b k\yc DCD 1668897899 - 0x01000ef0: 7261755f _uar DCD 1918989663 - 0x01000ef4: 00632e74 t.c. DCD 6499956 - 0x01000ef8: 000f8b00 .... DCD 1018624 - 0x01000efc: 000f8c00 .... DCD 1018880 - $t - i.UART_SendData - UART_SendData - 0x01000f00: b508 .. PUSH {r3,lr} - 0x01000f02: 9100 .. STR r1,[sp,#0] - 0x01000f04: 2800 .( CMP r0,#0 - 0x01000f06: d114 .. BNE 0x1000f32 ; UART_SendData + 50 - 0x01000f08: 466a jF MOV r2,sp - 0x01000f0a: 4b14 .K LDR r3,[pc,#80] ; [0x1000f5c] = 0xf8b00 - 0x01000f0c: 601a .` STR r2,[r3,#0] - 0x01000f0e: 461a .F MOV r2,r3 - 0x01000f10: 6892 .h LDR r2,[r2,#8] - 0x01000f12: b292 .. UXTH r2,r2 - 0x01000f14: 2301 .# MOVS r3,#1 - 0x01000f16: 041b .. LSLS r3,r3,#16 - 0x01000f18: 18d2 .. ADDS r2,r2,r3 - 0x01000f1a: 4b10 .K LDR r3,[pc,#64] ; [0x1000f5c] = 0xf8b00 - 0x01000f1c: 609a .` STR r2,[r3,#8] - 0x01000f1e: 2280 ." MOVS r2,#0x80 - 0x01000f20: 73da .s STRB r2,[r3,#0xf] - 0x01000f22: bf00 .. NOP - 0x01000f24: 4a0d .J LDR r2,[pc,#52] ; [0x1000f5c] = 0xf8b00 - 0x01000f26: 6912 .i LDR r2,[r2,#0x10] - 0x01000f28: 07d2 .. LSLS r2,r2,#31 - 0x01000f2a: 0fd2 .. LSRS r2,r2,#31 - 0x01000f2c: 2a00 .* CMP r2,#0 - 0x01000f2e: d0f9 .. BEQ 0x1000f24 ; UART_SendData + 36 - 0x01000f30: e013 .. B 0x1000f5a ; UART_SendData + 90 - 0x01000f32: 466a jF MOV r2,sp - 0x01000f34: 4b0a .K LDR r3,[pc,#40] ; [0x1000f60] = 0xf8c00 - 0x01000f36: 601a .` STR r2,[r3,#0] - 0x01000f38: 461a .F MOV r2,r3 - 0x01000f3a: 6892 .h LDR r2,[r2,#8] - 0x01000f3c: b292 .. UXTH r2,r2 - 0x01000f3e: 2301 .# MOVS r3,#1 - 0x01000f40: 041b .. LSLS r3,r3,#16 - 0x01000f42: 18d2 .. ADDS r2,r2,r3 - 0x01000f44: 4b06 .K LDR r3,[pc,#24] ; [0x1000f60] = 0xf8c00 - 0x01000f46: 609a .` STR r2,[r3,#8] - 0x01000f48: 2280 ." MOVS r2,#0x80 - 0x01000f4a: 73da .s STRB r2,[r3,#0xf] - 0x01000f4c: bf00 .. NOP - 0x01000f4e: 4a04 .J LDR r2,[pc,#16] ; [0x1000f60] = 0xf8c00 - 0x01000f50: 6912 .i LDR r2,[r2,#0x10] - 0x01000f52: 07d2 .. LSLS r2,r2,#31 - 0x01000f54: 0fd2 .. LSRS r2,r2,#31 - 0x01000f56: 2a00 .* CMP r2,#0 - 0x01000f58: d0f9 .. BEQ 0x1000f4e ; UART_SendData + 78 - 0x01000f5a: bd08 .. POP {r3,pc} - $d - 0x01000f5c: 000f8b00 .... DCD 1018624 - 0x01000f60: 000f8c00 .... DCD 1018880 - $t - i.UART_SetRxITNum - UART_SetRxITNum - 0x01000f64: b570 p. PUSH {r4-r6,lr} - 0x01000f66: 4604 .F MOV r4,r0 - 0x01000f68: 460d .F MOV r5,r1 - 0x01000f6a: 2c00 ., CMP r4,#0 - 0x01000f6c: d007 .. BEQ 0x1000f7e ; UART_SetRxITNum + 26 - 0x01000f6e: 2c01 ., CMP r4,#1 - 0x01000f70: d005 .. BEQ 0x1000f7e ; UART_SetRxITNum + 26 - 0x01000f72: 4a0f .J LDR r2,[pc,#60] ; [0x1000fb0] = 0x1007cd7 - 0x01000f74: 21ff .! MOVS r1,#0xff - 0x01000f76: 318f .1 ADDS r1,r1,#0x8f - 0x01000f78: a00e .. ADR r0,{pc}+0x3c ; 0x1000fb4 - 0x01000f7a: f000f867 ..g. BL _assert_handler ; 0x100104c - 0x01000f7e: 2c00 ., CMP r4,#0 - 0x01000f80: d10a .. BNE 0x1000f98 ; UART_SetRxITNum + 52 - 0x01000f82: 4812 .H LDR r0,[pc,#72] ; [0x1000fcc] = 0xf8b00 - 0x01000f84: 69c0 .i LDR r0,[r0,#0x1c] - 0x01000f86: 21ff .! MOVS r1,#0xff - 0x01000f88: 0209 .. LSLS r1,r1,#8 - 0x01000f8a: 4388 .C BICS r0,r0,r1 - 0x01000f8c: 0629 ). LSLS r1,r5,#24 - 0x01000f8e: 0c09 .. LSRS r1,r1,#16 - 0x01000f90: 4308 .C ORRS r0,r0,r1 - 0x01000f92: 490e .I LDR r1,[pc,#56] ; [0x1000fcc] = 0xf8b00 - 0x01000f94: 61c8 .a STR r0,[r1,#0x1c] - 0x01000f96: e009 .. B 0x1000fac ; UART_SetRxITNum + 72 - 0x01000f98: 480d .H LDR r0,[pc,#52] ; [0x1000fd0] = 0xf8c00 - 0x01000f9a: 69c0 .i LDR r0,[r0,#0x1c] - 0x01000f9c: 21ff .! MOVS r1,#0xff - 0x01000f9e: 0209 .. LSLS r1,r1,#8 - 0x01000fa0: 4388 .C BICS r0,r0,r1 - 0x01000fa2: 0629 ). LSLS r1,r5,#24 - 0x01000fa4: 0c09 .. LSRS r1,r1,#16 - 0x01000fa6: 4308 .C ORRS r0,r0,r1 - 0x01000fa8: 4909 .I LDR r1,[pc,#36] ; [0x1000fd0] = 0xf8c00 - 0x01000faa: 61c8 .a STR r0,[r1,#0x1c] - 0x01000fac: bd70 p. POP {r4-r6,pc} - $d - 0x01000fae: 0000 .. DCW 0 - 0x01000fb0: 01007cd7 .|.. DCD 16809175 - 0x01000fb4: 7262694c Libr DCD 1919052108 - 0x01000fb8: 65697261 arie DCD 1701409377 - 0x01000fbc: 64735c73 s\sd DCD 1685281907 - 0x01000fc0: 63795c6b k\yc DCD 1668897899 - 0x01000fc4: 7261755f _uar DCD 1918989663 - 0x01000fc8: 00632e74 t.c. DCD 6499956 - 0x01000fcc: 000f8b00 .... DCD 1018624 - 0x01000fd0: 000f8c00 .... DCD 1018880 - $t - i.__ARM_common_switch8 - __ARM_common_switch8 - 0x01000fd4: b430 0. PUSH {r4,r5} - 0x01000fd6: 4674 tF MOV r4,lr - 0x01000fd8: 1e64 d. SUBS r4,r4,#1 - 0x01000fda: 7825 %x LDRB r5,[r4,#0] - 0x01000fdc: 1c64 d. ADDS r4,r4,#1 - 0x01000fde: 42ab .B CMP r3,r5 - 0x01000fe0: d304 .. BCC 0x1000fec ; __ARM_common_switch8 + 24 - 0x01000fe2: 5d63 c] LDRB r3,[r4,r5] - 0x01000fe4: 005b [. LSLS r3,r3,#1 - 0x01000fe6: 18e3 .. ADDS r3,r4,r3 - 0x01000fe8: bc30 0. POP {r4,r5} - 0x01000fea: 4718 .G BX r3 - 0x01000fec: 461d .F MOV r5,r3 - 0x01000fee: e7f8 .. B 0x1000fe2 ; __ARM_common_switch8 + 14 - i.__rt_ffs - __rt_ffs - 0x01000ff0: 4601 .F MOV r1,r0 - 0x01000ff2: 2900 .) CMP r1,#0 - 0x01000ff4: d100 .. BNE 0x1000ff8 ; __rt_ffs + 8 - 0x01000ff6: 4770 pG BX lr - 0x01000ff8: b2c8 .. UXTB r0,r1 - 0x01000ffa: 2800 .( CMP r0,#0 - 0x01000ffc: d004 .. BEQ 0x1001008 ; __rt_ffs + 24 - 0x01000ffe: b2c8 .. UXTB r0,r1 - 0x01001000: 4a11 .J LDR r2,[pc,#68] ; [0x1001048] = 0x10076b3 - 0x01001002: 5c10 .\ LDRB r0,[r2,r0] - 0x01001004: 1c40 @. ADDS r0,r0,#1 - 0x01001006: e7f6 .. B 0x1000ff6 ; __rt_ffs + 6 - 0x01001008: 20ff . MOVS r0,#0xff - 0x0100100a: 0200 .. LSLS r0,r0,#8 - 0x0100100c: 4008 .@ ANDS r0,r0,r1 - 0x0100100e: 2800 .( CMP r0,#0 - 0x01001010: d007 .. BEQ 0x1001022 ; __rt_ffs + 50 - 0x01001012: 20ff . MOVS r0,#0xff - 0x01001014: 0200 .. LSLS r0,r0,#8 - 0x01001016: 4008 .@ ANDS r0,r0,r1 - 0x01001018: 1200 .. ASRS r0,r0,#8 - 0x0100101a: 4a0b .J LDR r2,[pc,#44] ; [0x1001048] = 0x10076b3 - 0x0100101c: 5c10 .\ LDRB r0,[r2,r0] - 0x0100101e: 3009 .0 ADDS r0,r0,#9 - 0x01001020: e7e9 .. B 0x1000ff6 ; __rt_ffs + 6 - 0x01001022: 20ff . MOVS r0,#0xff - 0x01001024: 0400 .. LSLS r0,r0,#16 - 0x01001026: 4008 .@ ANDS r0,r0,r1 - 0x01001028: 2800 .( CMP r0,#0 - 0x0100102a: d007 .. BEQ 0x100103c ; __rt_ffs + 76 - 0x0100102c: 20ff . MOVS r0,#0xff - 0x0100102e: 0400 .. LSLS r0,r0,#16 - 0x01001030: 4008 .@ ANDS r0,r0,r1 - 0x01001032: 1400 .. ASRS r0,r0,#16 - 0x01001034: 4a04 .J LDR r2,[pc,#16] ; [0x1001048] = 0x10076b3 - 0x01001036: 5c10 .\ LDRB r0,[r2,r0] - 0x01001038: 3011 .0 ADDS r0,r0,#0x11 - 0x0100103a: e7dc .. B 0x1000ff6 ; __rt_ffs + 6 - 0x0100103c: 0e08 .. LSRS r0,r1,#24 - 0x0100103e: 4a02 .J LDR r2,[pc,#8] ; [0x1001048] = 0x10076b3 - 0x01001040: 5c10 .\ LDRB r0,[r2,r0] - 0x01001042: 3019 .0 ADDS r0,r0,#0x19 - 0x01001044: e7d7 .. B 0x1000ff6 ; __rt_ffs + 6 - $d - 0x01001046: 0000 .. DCW 0 - 0x01001048: 010076b3 .v.. DCD 16807603 - $t - i._assert_handler - _assert_handler - 0x0100104c: bf00 .. NOP - 0x0100104e: e7fe .. B 0x100104e ; _assert_handler + 2 - i._ipc_list_resume - _ipc_list_resume - 0x01001050: b570 p. PUSH {r4-r6,lr} - 0x01001052: 4604 .F MOV r4,r0 - 0x01001054: 6820 h LDR r0,[r4,#0] - 0x01001056: 4605 .F MOV r5,r0 - 0x01001058: 3d14 .= SUBS r5,r5,#0x14 - 0x0100105a: bf00 .. NOP - 0x0100105c: bf00 .. NOP - 0x0100105e: 4628 (F MOV r0,r5 - 0x01001060: f004ff4e ..N. BL rt_thread_resume ; 0x1005f00 - 0x01001064: 2000 . MOVS r0,#0 - 0x01001066: bd70 p. POP {r4-r6,pc} - i._ipc_list_suspend - _ipc_list_suspend - 0x01001068: b5f7 .. PUSH {r0-r2,r4-r7,lr} - 0x0100106a: 4605 .F MOV r5,r0 - 0x0100106c: 460c .F MOV r4,r1 - 0x0100106e: 4620 F MOV r0,r4 - 0x01001070: f005f842 ..B. BL rt_thread_suspend ; 0x10060f8 - 0x01001074: 9802 .. LDR r0,[sp,#8] - 0x01001076: 2800 .( CMP r0,#0 - 0x01001078: d002 .. BEQ 0x1001080 ; _ipc_list_suspend + 24 - 0x0100107a: 2801 .( CMP r0,#1 - 0x0100107c: d122 ". BNE 0x10010c4 ; _ipc_list_suspend + 92 - 0x0100107e: e005 .. B 0x100108c ; _ipc_list_suspend + 36 - 0x01001080: 4621 !F MOV r1,r4 - 0x01001082: 3114 .1 ADDS r1,r1,#0x14 - 0x01001084: 4628 (F MOV r0,r5 - 0x01001086: f003fa5f .._. BL rt_list_insert_before ; 0x1004548 - 0x0100108a: e021 !. B 0x10010d0 ; _ipc_list_suspend + 104 - 0x0100108c: 682e .h LDR r6,[r5,#0] - 0x0100108e: e00e .. B 0x10010ae ; _ipc_list_suspend + 70 - 0x01001090: 4637 7F MOV r7,r6 - 0x01001092: 3f14 .? SUBS r7,r7,#0x14 - 0x01001094: 2035 5 MOVS r0,#0x35 - 0x01001096: 5d01 .] LDRB r1,[r0,r4] - 0x01001098: 5dc0 .] LDRB r0,[r0,r7] - 0x0100109a: 4281 .B CMP r1,r0 - 0x0100109c: da06 .. BGE 0x10010ac ; _ipc_list_suspend + 68 - 0x0100109e: 4621 !F MOV r1,r4 - 0x010010a0: 3114 .1 ADDS r1,r1,#0x14 - 0x010010a2: 4638 8F MOV r0,r7 - 0x010010a4: 3014 .0 ADDS r0,r0,#0x14 - 0x010010a6: f003fa4f ..O. BL rt_list_insert_before ; 0x1004548 - 0x010010aa: e002 .. B 0x10010b2 ; _ipc_list_suspend + 74 - 0x010010ac: 6836 6h LDR r6,[r6,#0] - 0x010010ae: 42ae .B CMP r6,r5 - 0x010010b0: d1ee .. BNE 0x1001090 ; _ipc_list_suspend + 40 - 0x010010b2: bf00 .. NOP - 0x010010b4: 42ae .B CMP r6,r5 - 0x010010b6: d104 .. BNE 0x10010c2 ; _ipc_list_suspend + 90 - 0x010010b8: 4621 !F MOV r1,r4 - 0x010010ba: 3114 .1 ADDS r1,r1,#0x14 - 0x010010bc: 4628 (F MOV r0,r5 - 0x010010be: f003fa43 ..C. BL rt_list_insert_before ; 0x1004548 - 0x010010c2: e005 .. B 0x10010d0 ; _ipc_list_suspend + 104 - 0x010010c4: 2297 ." MOVS r2,#0x97 - 0x010010c6: 4904 .I LDR r1,[pc,#16] ; [0x10010d8] = 0x10077d5 - 0x010010c8: a004 .. ADR r0,{pc}+0x14 ; 0x10010dc - 0x010010ca: f002fa99 .... BL rt_assert_handler ; 0x1003600 - 0x010010ce: bf00 .. NOP - 0x010010d0: bf00 .. NOP - 0x010010d2: 2000 . MOVS r0,#0 - 0x010010d4: bdfe .. POP {r1-r7,pc} - $d - 0x010010d6: 0000 .. DCW 0 - 0x010010d8: 010077d5 .w.. DCD 16807893 - 0x010010dc: 00000030 0... DCD 48 - $t - i._ipc_object_init - _ipc_object_init - 0x010010e0: b510 .. PUSH {r4,lr} - 0x010010e2: 4604 .F MOV r4,r0 - 0x010010e4: 4620 F MOV r0,r4 - 0x010010e6: 3014 .0 ADDS r0,r0,#0x14 - 0x010010e8: f003fa1a .... BL rt_list_init ; 0x1004520 - 0x010010ec: 2000 . MOVS r0,#0 - 0x010010ee: bd10 .. POP {r4,pc} - i._memheap_dump_tag - _memheap_dump_tag - 0x010010f0: b57c |. PUSH {r2-r6,lr} - 0x010010f2: 4604 .F MOV r4,r0 - 0x010010f4: 4625 %F MOV r5,r4 - 0x010010f6: 3510 .5 ADDS r5,r5,#0x10 - 0x010010f8: 2204 ." MOVS r2,#4 - 0x010010fa: 4629 )F MOV r1,r5 - 0x010010fc: 4668 hF MOV r0,sp - 0x010010fe: f003fbd1 .... BL rt_memcpy ; 0x10048a4 - 0x01001102: 4625 %F MOV r5,r4 - 0x01001104: 3514 .5 ADDS r5,r5,#0x14 - 0x01001106: 2204 ." MOVS r2,#4 - 0x01001108: 4629 )F MOV r1,r5 - 0x0100110a: a801 .. ADD r0,sp,#4 - 0x0100110c: f003fbca .... BL rt_memcpy ; 0x10048a4 - 0x01001110: 466a jF MOV r2,sp - 0x01001112: 2108 .! MOVS r1,#8 - 0x01001114: a001 .. ADR r0,{pc}+8 ; 0x100111c - 0x01001116: f003f9db .... BL rt_kprintf ; 0x10044d0 - 0x0100111a: bd7c |. POP {r2-r6,pc} - $d - 0x0100111c: 732a2e25 %.*s DCD 1932144165 - 0x01001120: 00000000 .... DCD 0 - $t - i._msh_exec_cmd - _msh_exec_cmd - 0x01001124: b5f7 .. PUSH {r0-r2,r4-r7,lr} - 0x01001126: b08c .. SUB sp,sp,#0x30 - 0x01001128: 4605 .F MOV r5,r0 - 0x0100112a: 4617 .F MOV r7,r2 - 0x0100112c: 2400 .$ MOVS r4,#0 - 0x0100112e: 2d00 .- CMP r5,#0 - 0x01001130: d105 .. BNE 0x100113e ; _msh_exec_cmd + 26 - 0x01001132: 22ff ." MOVS r2,#0xff - 0x01001134: 321d .2 ADDS r2,r2,#0x1d - 0x01001136: 491d .I LDR r1,[pc,#116] ; [0x10011ac] = 0x100750f - 0x01001138: a01d .. ADR r0,{pc}+0x78 ; 0x10011b0 - 0x0100113a: f002fa61 ..a. BL rt_assert_handler ; 0x1003600 - 0x0100113e: 2f00 ./ CMP r7,#0 - 0x01001140: d105 .. BNE 0x100114e ; _msh_exec_cmd + 42 - 0x01001142: 22ff ." MOVS r2,#0xff - 0x01001144: 321e .2 ADDS r2,r2,#0x1e - 0x01001146: 4919 .I LDR r1,[pc,#100] ; [0x10011ac] = 0x100750f - 0x01001148: a01a .. ADR r0,{pc}+0x6c ; 0x10011b4 - 0x0100114a: f002fa59 ..Y. BL rt_assert_handler ; 0x1003600 - 0x0100114e: e000 .. B 0x1001152 ; _msh_exec_cmd + 46 - 0x01001150: 1c64 d. ADDS r4,r4,#1 - 0x01001152: 5d28 (] LDRB r0,[r5,r4] - 0x01001154: 2820 ( CMP r0,#0x20 - 0x01001156: d005 .. BEQ 0x1001164 ; _msh_exec_cmd + 64 - 0x01001158: 5d28 (] LDRB r0,[r5,r4] - 0x0100115a: 2809 .( CMP r0,#9 - 0x0100115c: d002 .. BEQ 0x1001164 ; _msh_exec_cmd + 64 - 0x0100115e: 980d .. LDR r0,[sp,#0x34] - 0x01001160: 4284 .B CMP r4,r0 - 0x01001162: d3f5 .. BCC 0x1001150 ; _msh_exec_cmd + 44 - 0x01001164: 2c00 ., CMP r4,#0 - 0x01001166: d102 .. BNE 0x100116e ; _msh_exec_cmd + 74 - 0x01001168: 1e60 `. SUBS r0,r4,#1 - 0x0100116a: b00f .. ADD sp,sp,#0x3c - 0x0100116c: bdf0 .. POP {r4-r7,pc} - 0x0100116e: 4621 !F MOV r1,r4 - 0x01001170: 4628 (F MOV r0,r5 - 0x01001172: f001ffed .... BL msh_get_cmd ; 0x1003150 - 0x01001176: 4606 .F MOV r6,r0 - 0x01001178: 2e00 .. CMP r6,#0 - 0x0100117a: d101 .. BNE 0x1001180 ; _msh_exec_cmd + 92 - 0x0100117c: 1e40 @. SUBS r0,r0,#1 - 0x0100117e: e7f4 .. B 0x100116a ; _msh_exec_cmd + 70 - 0x01001180: 2128 (! MOVS r1,#0x28 - 0x01001182: a801 .. ADD r0,sp,#4 - 0x01001184: f7fffb39 ..9. BL __aeabi_memclr4 ; 0x10007fa - 0x01001188: aa01 .. ADD r2,sp,#4 - 0x0100118a: 4628 (F MOV r0,r5 - 0x0100118c: 990d .. LDR r1,[sp,#0x34] - 0x0100118e: f002f831 ..1. BL msh_split ; 0x10031f4 - 0x01001192: 900b .. STR r0,[sp,#0x2c] - 0x01001194: 980b .. LDR r0,[sp,#0x2c] - 0x01001196: 2800 .( CMP r0,#0 - 0x01001198: d101 .. BNE 0x100119e ; _msh_exec_cmd + 122 - 0x0100119a: 1e40 @. SUBS r0,r0,#1 - 0x0100119c: e7e5 .. B 0x100116a ; _msh_exec_cmd + 70 - 0x0100119e: a901 .. ADD r1,sp,#4 - 0x010011a0: 980b .. LDR r0,[sp,#0x2c] - 0x010011a2: 47b0 .G BLX r6 - 0x010011a4: 6038 8` STR r0,[r7,#0] - 0x010011a6: 2000 . MOVS r0,#0 - 0x010011a8: e7df .. B 0x100116a ; _msh_exec_cmd + 70 - $d - 0x010011aa: 0000 .. DCW 0 - 0x010011ac: 0100750f .u.. DCD 16807183 - 0x010011b0: 00646d63 cmd. DCD 6581603 - 0x010011b4: 70746572 retp DCD 1886676338 - 0x010011b8: 00000000 .... DCD 0 - $t - i._pin_control - _pin_control - 0x010011bc: b5f8 .. PUSH {r3-r7,lr} - 0x010011be: 4605 .F MOV r5,r0 - 0x010011c0: 4616 .F MOV r6,r2 - 0x010011c2: 462f /F MOV r7,r5 - 0x010011c4: 2f00 ./ CMP r7,#0 - 0x010011c6: d104 .. BNE 0x10011d2 ; _pin_control + 22 - 0x010011c8: 2238 8" MOVS r2,#0x38 - 0x010011ca: 4908 .I LDR r1,[pc,#32] ; [0x10011ec] = 0x1007291 - 0x010011cc: a008 .. ADR r0,{pc}+0x24 ; 0x10011f0 - 0x010011ce: f002fa17 .... BL rt_assert_handler ; 0x1003600 - 0x010011d2: 4634 4F MOV r4,r6 - 0x010011d4: 2c00 ., CMP r4,#0 - 0x010011d6: d101 .. BNE 0x10011dc ; _pin_control + 32 - 0x010011d8: 1e60 `. SUBS r0,r4,#1 - 0x010011da: bdf8 .. POP {r3-r7,pc} - 0x010011dc: 8862 b. LDRH r2,[r4,#2] - 0x010011de: 8821 !. LDRH r1,[r4,#0] - 0x010011e0: 6c38 8l LDR r0,[r7,#0x40] - 0x010011e2: 6803 .h LDR r3,[r0,#0] - 0x010011e4: 4628 (F MOV r0,r5 - 0x010011e6: 4798 .G BLX r3 - 0x010011e8: 2000 . MOVS r0,#0 - 0x010011ea: e7f6 .. B 0x10011da ; _pin_control + 30 - $d - 0x010011ec: 01007291 .r.. DCD 16806545 - 0x010011f0: 206e6970 pin DCD 544106864 - 0x010011f4: 52203d21 != R DCD 1377844513 - 0x010011f8: 554e5f54 T_NU DCD 1431199572 - 0x010011fc: 00004c4c LL.. DCD 19532 - $t - i._pin_read - _pin_read - 0x01001200: b5f8 .. PUSH {r3-r7,lr} - 0x01001202: 4605 .F MOV r5,r0 - 0x01001204: 4616 .F MOV r6,r2 - 0x01001206: 461f .F MOV r7,r3 - 0x01001208: 9500 .. STR r5,[sp,#0] - 0x0100120a: 9d00 .. LDR r5,[sp,#0] - 0x0100120c: 2d00 .- CMP r5,#0 - 0x0100120e: d104 .. BNE 0x100121a ; _pin_read + 26 - 0x01001210: 2219 ." MOVS r2,#0x19 - 0x01001212: 490a .I LDR r1,[pc,#40] ; [0x100123c] = 0x100727c - 0x01001214: a00a .. ADR r0,{pc}+0x2c ; 0x1001240 - 0x01001216: f002f9f3 .... BL rt_assert_handler ; 0x1003600 - 0x0100121a: 4634 4F MOV r4,r6 - 0x0100121c: 2c00 ., CMP r4,#0 - 0x0100121e: d001 .. BEQ 0x1001224 ; _pin_read + 36 - 0x01001220: 2f04 ./ CMP r7,#4 - 0x01001222: d001 .. BEQ 0x1001228 ; _pin_read + 40 - 0x01001224: 2000 . MOVS r0,#0 - 0x01001226: bdf8 .. POP {r3-r7,pc} - 0x01001228: 8821 !. LDRH r1,[r4,#0] - 0x0100122a: 9800 .. LDR r0,[sp,#0] - 0x0100122c: 6c00 .l LDR r0,[r0,#0x40] - 0x0100122e: 6882 .h LDR r2,[r0,#8] - 0x01001230: 4628 (F MOV r0,r5 - 0x01001232: 4790 .G BLX r2 - 0x01001234: 8060 `. STRH r0,[r4,#2] - 0x01001236: 4638 8F MOV r0,r7 - 0x01001238: e7f5 .. B 0x1001226 ; _pin_read + 38 - $d - 0x0100123a: 0000 .. DCW 0 - 0x0100123c: 0100727c |r.. DCD 16806524 - 0x01001240: 206e6970 pin DCD 544106864 - 0x01001244: 52203d21 != R DCD 1377844513 - 0x01001248: 554e5f54 T_NU DCD 1431199572 - 0x0100124c: 00004c4c LL.. DCD 19532 - $t - i._pin_write - _pin_write - 0x01001250: b5f8 .. PUSH {r3-r7,lr} - 0x01001252: 4605 .F MOV r5,r0 - 0x01001254: 4616 .F MOV r6,r2 - 0x01001256: 461f .F MOV r7,r3 - 0x01001258: 9500 .. STR r5,[sp,#0] - 0x0100125a: 9d00 .. LDR r5,[sp,#0] - 0x0100125c: 2d00 .- CMP r5,#0 - 0x0100125e: d104 .. BNE 0x100126a ; _pin_write + 26 - 0x01001260: 2228 (" MOVS r2,#0x28 - 0x01001262: 490a .I LDR r1,[pc,#40] ; [0x100128c] = 0x1007286 - 0x01001264: a00a .. ADR r0,{pc}+0x2c ; 0x1001290 - 0x01001266: f002f9cb .... BL rt_assert_handler ; 0x1003600 - 0x0100126a: 4634 4F MOV r4,r6 - 0x0100126c: 2c00 ., CMP r4,#0 - 0x0100126e: d001 .. BEQ 0x1001274 ; _pin_write + 36 - 0x01001270: 2f04 ./ CMP r7,#4 - 0x01001272: d001 .. BEQ 0x1001278 ; _pin_write + 40 - 0x01001274: 2000 . MOVS r0,#0 - 0x01001276: bdf8 .. POP {r3-r7,pc} - 0x01001278: 8862 b. LDRH r2,[r4,#2] - 0x0100127a: 8821 !. LDRH r1,[r4,#0] - 0x0100127c: 9800 .. LDR r0,[sp,#0] - 0x0100127e: 6c00 .l LDR r0,[r0,#0x40] - 0x01001280: 6843 Ch LDR r3,[r0,#4] - 0x01001282: 4628 (F MOV r0,r5 - 0x01001284: 4798 .G BLX r3 - 0x01001286: 4638 8F MOV r0,r7 - 0x01001288: e7f5 .. B 0x1001276 ; _pin_write + 38 - $d - 0x0100128a: 0000 .. DCW 0 - 0x0100128c: 01007286 .r.. DCD 16806534 - 0x01001290: 206e6970 pin DCD 544106864 - 0x01001294: 52203d21 != R DCD 1377844513 - 0x01001298: 554e5f54 T_NU DCD 1431199572 - 0x0100129c: 00004c4c LL.. DCD 19532 - $t - i._rt_scheduler_stack_check - _rt_scheduler_stack_check - 0x010012a0: b570 p. PUSH {r4-r6,lr} - 0x010012a2: 4604 .F MOV r4,r0 - 0x010012a4: 2c00 ., CMP r4,#0 - 0x010012a6: d104 .. BNE 0x10012b2 ; _rt_scheduler_stack_check + 18 - 0x010012a8: 2254 T" MOVS r2,#0x54 - 0x010012aa: 4913 .I LDR r1,[pc,#76] ; [0x10012f8] = 0x1007598 - 0x010012ac: a013 .. ADR r0,{pc}+0x50 ; 0x10012fc - 0x010012ae: f002f9a7 .... BL rt_assert_handler ; 0x1003600 - 0x010012b2: 6aa0 .j LDR r0,[r4,#0x28] - 0x010012b4: 7800 .x LDRB r0,[r0,#0] - 0x010012b6: 2823 #( CMP r0,#0x23 - 0x010012b8: d109 .. BNE 0x10012ce ; _rt_scheduler_stack_check + 46 - 0x010012ba: 6aa1 .j LDR r1,[r4,#0x28] - 0x010012bc: 69e0 .i LDR r0,[r4,#0x1c] - 0x010012be: 4288 .B CMP r0,r1 - 0x010012c0: d905 .. BLS 0x10012ce ; _rt_scheduler_stack_check + 46 - 0x010012c2: 6ae1 .j LDR r1,[r4,#0x2c] - 0x010012c4: 6aa0 .j LDR r0,[r4,#0x28] - 0x010012c6: 1840 @. ADDS r0,r0,r1 - 0x010012c8: 69e1 .i LDR r1,[r4,#0x1c] - 0x010012ca: 4288 .B CMP r0,r1 - 0x010012cc: d20a .. BCS 0x10012e4 ; _rt_scheduler_stack_check + 68 - 0x010012ce: 4621 !F MOV r1,r4 - 0x010012d0: a00f .. ADR r0,{pc}+0x40 ; 0x1001310 - 0x010012d2: f003f8fd .... BL rt_kprintf ; 0x10044d0 - 0x010012d6: f7fff8f3 .... BL rt_hw_interrupt_disable ; 0x10004c0 - 0x010012da: 4605 .F MOV r5,r0 - 0x010012dc: bf00 .. NOP - 0x010012de: 2d00 .- CMP r5,#0 - 0x010012e0: d1fd .. BNE 0x10012de ; _rt_scheduler_stack_check + 62 - 0x010012e2: e008 .. B 0x10012f6 ; _rt_scheduler_stack_check + 86 - 0x010012e4: 6aa0 .j LDR r0,[r4,#0x28] - 0x010012e6: 3020 0 ADDS r0,r0,#0x20 - 0x010012e8: 69e1 .i LDR r1,[r4,#0x1c] - 0x010012ea: 4281 .B CMP r1,r0 - 0x010012ec: d803 .. BHI 0x10012f6 ; _rt_scheduler_stack_check + 86 - 0x010012ee: 4621 !F MOV r1,r4 - 0x010012f0: a00e .. ADR r0,{pc}+0x3c ; 0x100132c - 0x010012f2: f003f8ed .... BL rt_kprintf ; 0x10044d0 - 0x010012f6: bd70 p. POP {r4-r6,pc} - $d - 0x010012f8: 01007598 .u.. DCD 16807320 - 0x010012fc: 65726874 thre DCD 1701996660 - 0x01001300: 21206461 ad ! DCD 555770977 - 0x01001304: 5452203d = RT DCD 1414668349 - 0x01001308: 4c554e5f _NUL DCD 1280659039 - 0x0100130c: 0000004c L... DCD 76 - 0x01001310: 65726874 thre DCD 1701996660 - 0x01001314: 253a6461 ad:% DCD 624583777 - 0x01001318: 74732073 s st DCD 1953702003 - 0x0100131c: 206b6361 ack DCD 543908705 - 0x01001320: 7265766f over DCD 1919252079 - 0x01001324: 776f6c66 flow DCD 2003790950 - 0x01001328: 0000000a .... DCD 10 - 0x0100132c: 6e726177 warn DCD 1852989815 - 0x01001330: 3a676e69 ing: DCD 979857001 - 0x01001334: 20732520 %s DCD 544417056 - 0x01001338: 63617473 stac DCD 1667331187 - 0x0100133c: 7369206b k is DCD 1936269419 - 0x01001340: 6f6c6320 clo DCD 1869374240 - 0x01001344: 74206573 se t DCD 1948280179 - 0x01001348: 6e65206f o en DCD 1852121199 - 0x0100134c: 666f2064 d of DCD 1718558820 - 0x01001350: 61747320 sta DCD 1635021600 - 0x01001354: 61206b63 ck a DCD 1629514595 - 0x01001358: 65726464 ddre DCD 1701995620 - 0x0100135c: 0a2e7373 ss.. DCD 170816371 - 0x01001360: 00000000 .... DCD 0 - $t - i._scheduler_get_highest_priority_thread - _scheduler_get_highest_priority_thread - 0x01001364: b570 p. PUSH {r4-r6,lr} - 0x01001366: 4604 .F MOV r4,r0 - 0x01001368: 4806 .H LDR r0,[pc,#24] ; [0x1001384] = 0x20024 - 0x0100136a: 6800 .h LDR r0,[r0,#0] - 0x0100136c: f7fffe40 ..@. BL __rt_ffs ; 0x1000ff0 - 0x01001370: 1e45 E. SUBS r5,r0,#1 - 0x01001372: 00e8 .. LSLS r0,r5,#3 - 0x01001374: 4904 .I LDR r1,[pc,#16] ; [0x1001388] = 0x20274 - 0x01001376: 5808 .X LDR r0,[r1,r0] - 0x01001378: 4606 .F MOV r6,r0 - 0x0100137a: 3e14 .> SUBS r6,r6,#0x14 - 0x0100137c: 6025 %` STR r5,[r4,#0] - 0x0100137e: 4630 0F MOV r0,r6 - 0x01001380: bd70 p. POP {r4-r6,pc} - $d - 0x01001382: 0000 .. DCW 0 - 0x01001384: 00020024 $... DCD 131108 - 0x01001388: 00020274 t... DCD 131700 - $t - i._serial_check_buffer_size - _serial_check_buffer_size - 0x0100138c: b510 .. PUSH {r4,lr} - 0x0100138e: 4809 .H LDR r0,[pc,#36] ; [0x10013b4] = 0x2000c - 0x01001390: 6800 .h LDR r0,[r0,#0] - 0x01001392: 2800 .( CMP r0,#0 - 0x01001394: d10d .. BNE 0x10013b2 ; _serial_check_buffer_size + 38 - 0x01001396: bf00 .. NOP - 0x01001398: a007 .. ADR r0,{pc}+0x20 ; 0x10013b8 - 0x0100139a: f003f899 .... BL rt_kprintf ; 0x10044d0 - 0x0100139e: 480a .H LDR r0,[pc,#40] ; [0x10013c8] = 0x1007cfc - 0x010013a0: f003f896 .... BL rt_kprintf ; 0x10044d0 - 0x010013a4: a009 .. ADR r0,{pc}+0x28 ; 0x10013cc - 0x010013a6: f003f893 .... BL rt_kprintf ; 0x10044d0 - 0x010013aa: bf00 .. NOP - 0x010013ac: 2001 . MOVS r0,#1 - 0x010013ae: 4901 .I LDR r1,[pc,#4] ; [0x10013b4] = 0x2000c - 0x010013b0: 6008 .` STR r0,[r1,#0] - 0x010013b2: bd10 .. POP {r4,pc} - $d - 0x010013b4: 0002000c .... DCD 131084 - 0x010013b8: 33335b1b .[33 DCD 859003675 - 0x010013bc: 2f575b6d m[W/ DCD 794254189 - 0x010013c0: 54524155 UART DCD 1414676821 - 0x010013c4: 0000205d ] .. DCD 8285 - 0x010013c8: 01007cfc .|.. DCD 16809212 - 0x010013cc: 6d305b1b .[0m DCD 1831885595 - 0x010013d0: 0000000a .... DCD 10 - $t - i._serial_int_rx - _serial_int_rx - 0x010013d4: b5fe .. PUSH {r1-r7,lr} - 0x010013d6: 4606 .F MOV r6,r0 - 0x010013d8: 460f .F MOV r7,r1 - 0x010013da: 4615 .F MOV r5,r2 - 0x010013dc: 2e00 .. CMP r6,#0 - 0x010013de: d105 .. BNE 0x10013ec ; _serial_int_rx + 24 - 0x010013e0: 22ff ." MOVS r2,#0xff - 0x010013e2: 320f .2 ADDS r2,r2,#0xf - 0x010013e4: 491f .I LDR r1,[pc,#124] ; [0x1001464] = 0x1007324 - 0x010013e6: a020 . ADR r0,{pc}+0x82 ; 0x1001468 - 0x010013e8: f002f90a .... BL rt_assert_handler ; 0x1003600 - 0x010013ec: 9502 .. STR r5,[sp,#8] - 0x010013ee: 6cf4 .l LDR r4,[r6,#0x4c] - 0x010013f0: 2c00 ., CMP r4,#0 - 0x010013f2: d105 .. BNE 0x1001400 ; _serial_int_rx + 44 - 0x010013f4: 22ff ." MOVS r2,#0xff - 0x010013f6: 3213 .2 ADDS r2,r2,#0x13 - 0x010013f8: 491a .I LDR r1,[pc,#104] ; [0x1001464] = 0x1007324 - 0x010013fa: a020 . ADR r0,{pc}+0x82 ; 0x100147c - 0x010013fc: f002f900 .... BL rt_assert_handler ; 0x1003600 - 0x01001400: e029 ). B 0x1001456 ; _serial_int_rx + 130 - 0x01001402: f7fff85d ..]. BL rt_hw_interrupt_disable ; 0x10004c0 - 0x01001406: 9000 .. STR r0,[sp,#0] - 0x01001408: 88e0 .. LDRH r0,[r4,#6] - 0x0100140a: 88a1 .. LDRH r1,[r4,#4] - 0x0100140c: 4288 .B CMP r0,r1 - 0x0100140e: d106 .. BNE 0x100141e ; _serial_int_rx + 74 - 0x01001410: 68a0 .h LDR r0,[r4,#8] - 0x01001412: 2800 .( CMP r0,#0 - 0x01001414: d103 .. BNE 0x100141e ; _serial_int_rx + 74 - 0x01001416: 9800 .. LDR r0,[sp,#0] - 0x01001418: f7fff856 ..V. BL rt_hw_interrupt_enable ; 0x10004c8 - 0x0100141c: e01d .. B 0x100145a ; _serial_int_rx + 134 - 0x0100141e: 88e1 .. LDRH r1,[r4,#6] - 0x01001420: 6820 h LDR r0,[r4,#0] - 0x01001422: 5c40 @\ LDRB r0,[r0,r1] - 0x01001424: 9001 .. STR r0,[sp,#4] - 0x01001426: 88e0 .. LDRH r0,[r4,#6] - 0x01001428: 1c40 @. ADDS r0,r0,#1 - 0x0100142a: 80e0 .. STRH r0,[r4,#6] - 0x0100142c: 88e1 .. LDRH r1,[r4,#6] - 0x0100142e: 6cb0 .l LDR r0,[r6,#0x48] - 0x01001430: 0180 .. LSLS r0,r0,#6 - 0x01001432: 0c00 .. LSRS r0,r0,#16 - 0x01001434: 4281 .B CMP r1,r0 - 0x01001436: db01 .. BLT 0x100143c ; _serial_int_rx + 104 - 0x01001438: 2000 . MOVS r0,#0 - 0x0100143a: 80e0 .. STRH r0,[r4,#6] - 0x0100143c: 68a0 .h LDR r0,[r4,#8] - 0x0100143e: 2801 .( CMP r0,#1 - 0x01001440: d101 .. BNE 0x1001446 ; _serial_int_rx + 114 - 0x01001442: 2000 . MOVS r0,#0 - 0x01001444: 60a0 .` STR r0,[r4,#8] - 0x01001446: 9800 .. LDR r0,[sp,#0] - 0x01001448: f7fff83e ..>. BL rt_hw_interrupt_enable ; 0x10004c8 - 0x0100144c: 9801 .. LDR r0,[sp,#4] - 0x0100144e: 7038 8p STRB r0,[r7,#0] - 0x01001450: 1c7f .. ADDS r7,r7,#1 - 0x01001452: 1e6d m. SUBS r5,r5,#1 - 0x01001454: bf00 .. NOP - 0x01001456: 2d00 .- CMP r5,#0 - 0x01001458: d1d3 .. BNE 0x1001402 ; _serial_int_rx + 46 - 0x0100145a: bf00 .. NOP - 0x0100145c: 9802 .. LDR r0,[sp,#8] - 0x0100145e: 1b40 @. SUBS r0,r0,r5 - 0x01001460: bdfe .. POP {r1-r7,pc} - $d - 0x01001462: 0000 .. DCW 0 - 0x01001464: 01007324 $s.. DCD 16806692 - 0x01001468: 69726573 seri DCD 1769104755 - 0x0100146c: 21206c61 al ! DCD 555773025 - 0x01001470: 5452203d = RT DCD 1414668349 - 0x01001474: 4c554e5f _NUL DCD 1280659039 - 0x01001478: 0000004c L... DCD 76 - 0x0100147c: 665f7872 rx_f DCD 1717532786 - 0x01001480: 206f6669 ifo DCD 544171625 - 0x01001484: 52203d21 != R DCD 1377844513 - 0x01001488: 554e5f54 T_NU DCD 1431199572 - 0x0100148c: 00004c4c LL.. DCD 19532 - $t - i._serial_int_tx - _serial_int_tx - 0x01001490: b5f8 .. PUSH {r3-r7,lr} - 0x01001492: 4604 .F MOV r4,r0 - 0x01001494: 460e .F MOV r6,r1 - 0x01001496: 4615 .F MOV r5,r2 - 0x01001498: 2c00 ., CMP r4,#0 - 0x0100149a: d105 .. BNE 0x10014a8 ; _serial_int_tx + 24 - 0x0100149c: 22ff ." MOVS r2,#0xff - 0x0100149e: 323f ?2 ADDS r2,r2,#0x3f - 0x010014a0: 491c .I LDR r1,[pc,#112] ; [0x1001514] = 0x1007333 - 0x010014a2: 481d .H LDR r0,[pc,#116] ; [0x1001518] = 0x1001580 - 0x010014a4: f002f8ac .... BL rt_assert_handler ; 0x1003600 - 0x010014a8: 9500 .. STR r5,[sp,#0] - 0x010014aa: 6d27 'm LDR r7,[r4,#0x50] - 0x010014ac: 2f00 ./ CMP r7,#0 - 0x010014ae: d105 .. BNE 0x10014bc ; _serial_int_tx + 44 - 0x010014b0: 22ff ." MOVS r2,#0xff - 0x010014b2: 3243 C2 ADDS r2,r2,#0x43 - 0x010014b4: 4917 .I LDR r1,[pc,#92] ; [0x1001514] = 0x1007333 - 0x010014b6: a019 .. ADR r0,{pc}+0x66 ; 0x100151c - 0x010014b8: f002f8a2 .... BL rt_assert_handler ; 0x1003600 - 0x010014bc: e024 $. B 0x1001508 ; _serial_int_tx + 120 - 0x010014be: 7830 0x LDRB r0,[r6,#0] - 0x010014c0: 280a .( CMP r0,#0xa - 0x010014c2: d111 .. BNE 0x10014e8 ; _serial_int_tx + 88 - 0x010014c4: 8b20 . LDRH r0,[r4,#0x18] - 0x010014c6: 2140 @! MOVS r1,#0x40 - 0x010014c8: 4008 .@ ANDS r0,r0,r1 - 0x010014ca: 2800 .( CMP r0,#0 - 0x010014cc: d00c .. BEQ 0x10014e8 ; _serial_int_tx + 88 - 0x010014ce: 6c20 l LDR r0,[r4,#0x40] - 0x010014d0: 210d .! MOVS r1,#0xd - 0x010014d2: 6882 .h LDR r2,[r0,#8] - 0x010014d4: 4620 F MOV r0,r4 - 0x010014d6: 4790 .G BLX r2 - 0x010014d8: 1c40 @. ADDS r0,r0,#1 - 0x010014da: 2800 .( CMP r0,#0 - 0x010014dc: d104 .. BNE 0x10014e8 ; _serial_int_tx + 88 - 0x010014de: 1e41 A. SUBS r1,r0,#1 - 0x010014e0: 4638 8F MOV r0,r7 - 0x010014e2: f002f937 ..7. BL rt_completion_wait ; 0x1003754 - 0x010014e6: e00f .. B 0x1001508 ; _serial_int_tx + 120 - 0x010014e8: 7831 1x LDRB r1,[r6,#0] - 0x010014ea: 6c20 l LDR r0,[r4,#0x40] - 0x010014ec: 6882 .h LDR r2,[r0,#8] - 0x010014ee: 4620 F MOV r0,r4 - 0x010014f0: 4790 .G BLX r2 - 0x010014f2: 1c40 @. ADDS r0,r0,#1 - 0x010014f4: 2800 .( CMP r0,#0 - 0x010014f6: d104 .. BNE 0x1001502 ; _serial_int_tx + 114 - 0x010014f8: 1e41 A. SUBS r1,r0,#1 - 0x010014fa: 4638 8F MOV r0,r7 - 0x010014fc: f002f92a ..*. BL rt_completion_wait ; 0x1003754 - 0x01001500: e002 .. B 0x1001508 ; _serial_int_tx + 120 - 0x01001502: 1c76 v. ADDS r6,r6,#1 - 0x01001504: 1e6d m. SUBS r5,r5,#1 - 0x01001506: bf00 .. NOP - 0x01001508: 2d00 .- CMP r5,#0 - 0x0100150a: d1d8 .. BNE 0x10014be ; _serial_int_tx + 46 - 0x0100150c: 9800 .. LDR r0,[sp,#0] - 0x0100150e: 1b40 @. SUBS r0,r0,r5 - 0x01001510: bdf8 .. POP {r3-r7,pc} - $d - 0x01001512: 0000 .. DCW 0 - 0x01001514: 01007333 3s.. DCD 16806707 - 0x01001518: 01001580 .... DCD 16782720 - 0x0100151c: 21207874 tx ! DCD 555776116 - 0x01001520: 5452203d = RT DCD 1414668349 - 0x01001524: 4c554e5f _NUL DCD 1280659039 - 0x01001528: 0000004c L... DCD 76 - $t - i._serial_poll_rx - _serial_poll_rx - 0x0100152c: b5f8 .. PUSH {r3-r7,lr} - 0x0100152e: 4606 .F MOV r6,r0 - 0x01001530: 460f .F MOV r7,r1 - 0x01001532: 4614 .F MOV r4,r2 - 0x01001534: 2e00 .. CMP r6,#0 - 0x01001536: d104 .. BNE 0x1001542 ; _serial_poll_rx + 22 - 0x01001538: 22d8 ." MOVS r2,#0xd8 - 0x0100153a: 4910 .I LDR r1,[pc,#64] ; [0x100157c] = 0x1007304 - 0x0100153c: a010 .. ADR r0,{pc}+0x44 ; 0x1001580 - 0x0100153e: f002f85f .._. BL rt_assert_handler ; 0x1003600 - 0x01001542: 9400 .. STR r4,[sp,#0] - 0x01001544: e013 .. B 0x100156e ; _serial_poll_rx + 66 - 0x01001546: 6c30 0l LDR r0,[r6,#0x40] - 0x01001548: 68c1 .h LDR r1,[r0,#0xc] - 0x0100154a: 4630 0F MOV r0,r6 - 0x0100154c: 4788 .G BLX r1 - 0x0100154e: 4605 .F MOV r5,r0 - 0x01001550: 1c68 h. ADDS r0,r5,#1 - 0x01001552: 2800 .( CMP r0,#0 - 0x01001554: d100 .. BNE 0x1001558 ; _serial_poll_rx + 44 - 0x01001556: e00c .. B 0x1001572 ; _serial_poll_rx + 70 - 0x01001558: 703d =p STRB r5,[r7,#0] - 0x0100155a: 1c7f .. ADDS r7,r7,#1 - 0x0100155c: 1e64 d. SUBS r4,r4,#1 - 0x0100155e: 8b30 0. LDRH r0,[r6,#0x18] - 0x01001560: 2140 @! MOVS r1,#0x40 - 0x01001562: 4008 .@ ANDS r0,r0,r1 - 0x01001564: 2800 .( CMP r0,#0 - 0x01001566: d002 .. BEQ 0x100156e ; _serial_poll_rx + 66 - 0x01001568: 2d0a .- CMP r5,#0xa - 0x0100156a: d100 .. BNE 0x100156e ; _serial_poll_rx + 66 - 0x0100156c: e001 .. B 0x1001572 ; _serial_poll_rx + 70 - 0x0100156e: 2c00 ., CMP r4,#0 - 0x01001570: d1e9 .. BNE 0x1001546 ; _serial_poll_rx + 26 - 0x01001572: bf00 .. NOP - 0x01001574: 9800 .. LDR r0,[sp,#0] - 0x01001576: 1b00 .. SUBS r0,r0,r4 - 0x01001578: bdf8 .. POP {r3-r7,pc} - $d - 0x0100157a: 0000 .. DCW 0 - 0x0100157c: 01007304 .s.. DCD 16806660 - 0x01001580: 69726573 seri DCD 1769104755 - 0x01001584: 21206c61 al ! DCD 555773025 - 0x01001588: 5452203d = RT DCD 1414668349 - 0x0100158c: 4c554e5f _NUL DCD 1280659039 - 0x01001590: 0000004c L... DCD 76 - $t - i._serial_poll_tx - _serial_poll_tx - 0x01001594: b5f8 .. PUSH {r3-r7,lr} - 0x01001596: 4604 .F MOV r4,r0 - 0x01001598: 460e .F MOV r6,r1 - 0x0100159a: 4615 .F MOV r5,r2 - 0x0100159c: 2c00 ., CMP r4,#0 - 0x0100159e: d104 .. BNE 0x10015aa ; _serial_poll_tx + 22 - 0x010015a0: 22ef ." MOVS r2,#0xef - 0x010015a2: 490f .I LDR r1,[pc,#60] ; [0x10015e0] = 0x1007314 - 0x010015a4: 480f .H LDR r0,[pc,#60] ; [0x10015e4] = 0x1001580 - 0x010015a6: f002f82b ..+. BL rt_assert_handler ; 0x1003600 - 0x010015aa: 462f /F MOV r7,r5 - 0x010015ac: e013 .. B 0x10015d6 ; _serial_poll_tx + 66 - 0x010015ae: 7830 0x LDRB r0,[r6,#0] - 0x010015b0: 280a .( CMP r0,#0xa - 0x010015b2: d109 .. BNE 0x10015c8 ; _serial_poll_tx + 52 - 0x010015b4: 8b20 . LDRH r0,[r4,#0x18] - 0x010015b6: 2140 @! MOVS r1,#0x40 - 0x010015b8: 4008 .@ ANDS r0,r0,r1 - 0x010015ba: 2800 .( CMP r0,#0 - 0x010015bc: d004 .. BEQ 0x10015c8 ; _serial_poll_tx + 52 - 0x010015be: 6c20 l LDR r0,[r4,#0x40] - 0x010015c0: 210d .! MOVS r1,#0xd - 0x010015c2: 6882 .h LDR r2,[r0,#8] - 0x010015c4: 4620 F MOV r0,r4 - 0x010015c6: 4790 .G BLX r2 - 0x010015c8: 7831 1x LDRB r1,[r6,#0] - 0x010015ca: 6c20 l LDR r0,[r4,#0x40] - 0x010015cc: 6882 .h LDR r2,[r0,#8] - 0x010015ce: 4620 F MOV r0,r4 - 0x010015d0: 4790 .G BLX r2 - 0x010015d2: 1c76 v. ADDS r6,r6,#1 - 0x010015d4: 1e6d m. SUBS r5,r5,#1 - 0x010015d6: 2d00 .- CMP r5,#0 - 0x010015d8: d1e9 .. BNE 0x10015ae ; _serial_poll_tx + 26 - 0x010015da: 1b78 x. SUBS r0,r7,r5 - 0x010015dc: bdf8 .. POP {r3-r7,pc} - $d - 0x010015de: 0000 .. DCW 0 - 0x010015e0: 01007314 .s.. DCD 16806676 - 0x010015e4: 01001580 .... DCD 16782720 - $t - i._thread_cleanup_execute - _thread_cleanup_execute - 0x010015e8: b570 p. PUSH {r4-r6,lr} - 0x010015ea: 4604 .F MOV r4,r0 - 0x010015ec: f7feff68 ..h. BL rt_hw_interrupt_disable ; 0x10004c0 - 0x010015f0: 4605 .F MOV r5,r0 - 0x010015f2: 6fa0 .o LDR r0,[r4,#0x78] - 0x010015f4: 2800 .( CMP r0,#0 - 0x010015f6: d002 .. BEQ 0x10015fe ; _thread_cleanup_execute + 22 - 0x010015f8: 4620 F MOV r0,r4 - 0x010015fa: 6fa1 .o LDR r1,[r4,#0x78] - 0x010015fc: 4788 .G BLX r1 - 0x010015fe: 4628 (F MOV r0,r5 - 0x01001600: f7feff62 ..b. BL rt_hw_interrupt_enable ; 0x10004c8 - 0x01001604: bd70 p. POP {r4-r6,pc} - i._thread_exit - _thread_exit - 0x01001606: b570 p. PUSH {r4-r6,lr} - 0x01001608: f004fcca .... BL rt_thread_self ; 0x1005fa0 - 0x0100160c: 4604 .F MOV r4,r0 - 0x0100160e: f7feff57 ..W. BL rt_hw_interrupt_disable ; 0x10004c0 - 0x01001612: 4605 .F MOV r5,r0 - 0x01001614: 4620 F MOV r0,r4 - 0x01001616: f7ffffe7 .... BL _thread_cleanup_execute ; 0x10015e8 - 0x0100161a: 4620 F MOV r0,r4 - 0x0100161c: f003fe0c .... BL rt_schedule_remove_thread ; 0x1005238 - 0x01001620: 2104 .! MOVS r1,#4 - 0x01001622: 2034 4 MOVS r0,#0x34 - 0x01001624: 5501 .U STRB r1,[r0,r4] - 0x01001626: 4620 F MOV r0,r4 - 0x01001628: 304c L0 ADDS r0,r0,#0x4c - 0x0100162a: f004ff6b ..k. BL rt_timer_detach ; 0x1006504 - 0x0100162e: 4620 F MOV r0,r4 - 0x01001630: f003fc98 .... BL rt_object_is_systemobject ; 0x1004f64 - 0x01001634: 2801 .( CMP r0,#1 - 0x01001636: d103 .. BNE 0x1001640 ; _thread_exit + 58 - 0x01001638: 4620 F MOV r0,r4 - 0x0100163a: f003fb33 ..3. BL rt_object_detach ; 0x1004ca4 - 0x0100163e: e002 .. B 0x1001646 ; _thread_exit + 64 - 0x01001640: 4620 F MOV r0,r4 - 0x01001642: f004fbc1 .... BL rt_thread_defunct_enqueue ; 0x1005dc8 - 0x01001646: f003fcf5 .... BL rt_schedule ; 0x1005034 - 0x0100164a: 4628 (F MOV r0,r5 - 0x0100164c: f7feff3c ..<. BL rt_hw_interrupt_enable ; 0x10004c8 - 0x01001650: bd70 p. POP {r4-r6,pc} - 0x01001652: 0000 .. MOVS r0,r0 - i._thread_init - _thread_init - 0x01001654: b5fe .. PUSH {r1-r7,lr} - 0x01001656: 4604 .F MOV r4,r0 - 0x01001658: 4616 .F MOV r6,r2 - 0x0100165a: 461f .F MOV r7,r3 - 0x0100165c: 9d0a .. LDR r5,[sp,#0x28] - 0x0100165e: 4620 F MOV r0,r4 - 0x01001660: 3014 .0 ADDS r0,r0,#0x14 - 0x01001662: 6040 @` STR r0,[r0,#4] - 0x01001664: 6000 .` STR r0,[r0,#0] - 0x01001666: bf00 .. NOP - 0x01001668: 6226 &b STR r6,[r4,#0x20] - 0x0100166a: 6267 gb STR r7,[r4,#0x24] - 0x0100166c: 9808 .. LDR r0,[sp,#0x20] - 0x0100166e: 62a0 .b STR r0,[r4,#0x28] - 0x01001670: 9809 .. LDR r0,[sp,#0x24] - 0x01001672: 62e0 .b STR r0,[r4,#0x2c] - 0x01001674: 2123 #! MOVS r1,#0x23 - 0x01001676: 6ae2 .j LDR r2,[r4,#0x2c] - 0x01001678: 6aa0 .j LDR r0,[r4,#0x28] - 0x0100167a: f003fa22 ..". BL rt_memset ; 0x1004ac2 - 0x0100167e: 6ae1 .j LDR r1,[r4,#0x2c] - 0x01001680: 6aa0 .j LDR r0,[r4,#0x28] - 0x01001682: 1840 @. ADDS r0,r0,r1 - 0x01001684: 1f02 .. SUBS r2,r0,#4 - 0x01001686: 6a60 `j LDR r0,[r4,#0x24] - 0x01001688: 9001 .. STR r0,[sp,#4] - 0x0100168a: 6a20 j LDR r0,[r4,#0x20] - 0x0100168c: 4b19 .K LDR r3,[pc,#100] ; [0x10016f4] = 0x1001607 - 0x0100168e: 9000 .. STR r0,[sp,#0] - 0x01001690: 9901 .. LDR r1,[sp,#4] - 0x01001692: f002fe89 .... BL rt_hw_stack_init ; 0x10043a8 - 0x01001696: 61e0 .a STR r0,[r4,#0x1c] - 0x01001698: 2d20 - CMP r5,#0x20 - 0x0100169a: db04 .. BLT 0x10016a6 ; _thread_init + 82 - 0x0100169c: 22ae ." MOVS r2,#0xae - 0x0100169e: 4916 .I LDR r1,[pc,#88] ; [0x10016f8] = 0x1007b32 - 0x010016a0: a016 .. ADR r0,{pc}+0x5c ; 0x10016fc - 0x010016a2: f001ffad .... BL rt_assert_handler ; 0x1003600 - 0x010016a6: 2036 6 MOVS r0,#0x36 - 0x010016a8: 5505 .U STRB r5,[r0,r4] - 0x010016aa: 2035 5 MOVS r0,#0x35 - 0x010016ac: 5505 .U STRB r5,[r0,r4] - 0x010016ae: 2000 . MOVS r0,#0 - 0x010016b0: 63a0 .c STR r0,[r4,#0x38] - 0x010016b2: 980b .. LDR r0,[sp,#0x2c] - 0x010016b4: 6460 `d STR r0,[r4,#0x44] - 0x010016b6: 980b .. LDR r0,[sp,#0x2c] - 0x010016b8: 64a0 .d STR r0,[r4,#0x48] - 0x010016ba: 2000 . MOVS r0,#0 - 0x010016bc: 6320 c STR r0,[r4,#0x30] - 0x010016be: 2100 .! MOVS r1,#0 - 0x010016c0: 2034 4 MOVS r0,#0x34 - 0x010016c2: 5501 .U STRB r1,[r0,r4] - 0x010016c4: 2000 . MOVS r0,#0 - 0x010016c6: 67a0 .g STR r0,[r4,#0x78] - 0x010016c8: 67e0 .g STR r0,[r4,#0x7c] - 0x010016ca: 9000 .. STR r0,[sp,#0] - 0x010016cc: 4623 #F MOV r3,r4 - 0x010016ce: 4a14 .J LDR r2,[pc,#80] ; [0x1001720] = 0x10061d9 - 0x010016d0: 4621 !F MOV r1,r4 - 0x010016d2: 9001 .. STR r0,[sp,#4] - 0x010016d4: 4620 F MOV r0,r4 - 0x010016d6: 304c L0 ADDS r0,r0,#0x4c - 0x010016d8: f004ff86 .... BL rt_timer_init ; 0x10065e8 - 0x010016dc: bf00 .. NOP - 0x010016de: 4811 .H LDR r0,[pc,#68] ; [0x1001724] = 0x20130 - 0x010016e0: 6800 .h LDR r0,[r0,#0] - 0x010016e2: 2800 .( CMP r0,#0 - 0x010016e4: d003 .. BEQ 0x10016ee ; _thread_init + 154 - 0x010016e6: 4620 F MOV r0,r4 - 0x010016e8: 490e .I LDR r1,[pc,#56] ; [0x1001724] = 0x20130 - 0x010016ea: 6809 .h LDR r1,[r1,#0] - 0x010016ec: 4788 .G BLX r1 - 0x010016ee: bf00 .. NOP - 0x010016f0: 2000 . MOVS r0,#0 - 0x010016f2: bdfe .. POP {r1-r7,pc} - $d - 0x010016f4: 01001607 .... DCD 16782855 - 0x010016f8: 01007b32 2{.. DCD 16808754 - 0x010016fc: 6f697270 prio DCD 1869181552 - 0x01001700: 79746972 rity DCD 2037672306 - 0x01001704: 52203c20 < R DCD 1377844256 - 0x01001708: 48545f54 T_TH DCD 1213488980 - 0x0100170c: 44414552 READ DCD 1145128274 - 0x01001710: 4952505f _PRI DCD 1230131295 - 0x01001714: 5449524f ORIT DCD 1414091343 - 0x01001718: 414d5f59 Y_MA DCD 1095589721 - 0x0100171c: 00000058 X... DCD 88 - 0x01001720: 010061d9 .a.. DCD 16802265 - 0x01001724: 00020130 0... DCD 131376 - $t - i._timer_init - _timer_init - 0x01001728: b5ff .. PUSH {r0-r7,lr} - 0x0100172a: b081 .. SUB sp,sp,#4 - 0x0100172c: 4604 .F MOV r4,r0 - 0x0100172e: 460e .F MOV r6,r1 - 0x01001730: 4617 .F MOV r7,r2 - 0x01001732: 980a .. LDR r0,[sp,#0x28] - 0x01001734: 7260 `r STRB r0,[r4,#9] - 0x01001736: 7a60 `z LDRB r0,[r4,#9] - 0x01001738: 0840 @. LSRS r0,r0,#1 - 0x0100173a: 0040 @. LSLS r0,r0,#1 - 0x0100173c: 7260 `r STRB r0,[r4,#9] - 0x0100173e: 61e6 .a STR r6,[r4,#0x1c] - 0x01001740: 6227 'b STR r7,[r4,#0x20] - 0x01001742: 2000 . MOVS r0,#0 - 0x01001744: 62a0 .b STR r0,[r4,#0x28] - 0x01001746: 9804 .. LDR r0,[sp,#0x10] - 0x01001748: 6260 `b STR r0,[r4,#0x24] - 0x0100174a: 2500 .% MOVS r5,#0 - 0x0100174c: e006 .. B 0x100175c ; _timer_init + 52 - 0x0100174e: 00ea .. LSLS r2,r5,#3 - 0x01001750: 4621 !F MOV r1,r4 - 0x01001752: 3114 .1 ADDS r1,r1,#0x14 - 0x01001754: 1850 P. ADDS r0,r2,r1 - 0x01001756: f002fee6 .... BL rt_list_init ; 0x1004526 - 0x0100175a: 1c6d m. ADDS r5,r5,#1 - 0x0100175c: 2d01 .- CMP r5,#1 - 0x0100175e: dbf6 .. BLT 0x100174e ; _timer_init + 38 - 0x01001760: b005 .. ADD sp,sp,#0x14 - 0x01001762: bdf0 .. POP {r4-r7,pc} - i._timer_remove - _timer_remove - 0x01001764: b570 p. PUSH {r4-r6,lr} - 0x01001766: 4605 .F MOV r5,r0 - 0x01001768: 2400 .$ MOVS r4,#0 - 0x0100176a: e006 .. B 0x100177a ; _timer_remove + 22 - 0x0100176c: 00e2 .. LSLS r2,r4,#3 - 0x0100176e: 4629 )F MOV r1,r5 - 0x01001770: 3114 .1 ADDS r1,r1,#0x14 - 0x01001772: 1850 P. ADDS r0,r2,r1 - 0x01001774: f002ff19 .... BL rt_list_remove ; 0x10045aa - 0x01001778: 1c64 d. ADDS r4,r4,#1 - 0x0100177a: 2c01 ., CMP r4,#1 - 0x0100177c: dbf6 .. BLT 0x100176c ; _timer_remove + 8 - 0x0100177e: bd70 p. POP {r4-r6,pc} - i.bsp_clock_config - bsp_clock_config - 0x01001780: b510 .. PUSH {r4,lr} - 0x01001782: 4802 .H LDR r0,[pc,#8] ; [0x100178c] = 0x75300 - 0x01001784: f7fff99c .... BL SysTick_Config ; 0x1000ac0 - 0x01001788: bd10 .. POP {r4,pc} - $d - 0x0100178a: 0000 .. DCW 0 - 0x0100178c: 00075300 .S.. DCD 480000 - $t - i.clear - clear - 0x01001790: b510 .. PUSH {r4,lr} - 0x01001792: a002 .. ADR r0,{pc}+0xa ; 0x100179c - 0x01001794: f002fe9c .... BL rt_kprintf ; 0x10044d0 - 0x01001798: 2000 . MOVS r0,#0 - 0x0100179a: bd10 .. POP {r4,pc} - $d - 0x0100179c: 4a325b1b .[2J DCD 1244814107 - 0x010017a0: 00485b1b .[H. DCD 4741915 - $t - i.cmd_free - cmd_free - 0x010017a4: b570 p. PUSH {r4-r6,lr} - 0x010017a6: 4604 .F MOV r4,r0 - 0x010017a8: 460d .F MOV r5,r1 - 0x010017aa: f000ff09 .... BL list_mem ; 0x10025c0 - 0x010017ae: 2000 . MOVS r0,#0 - 0x010017b0: bd70 p. POP {r4-r6,pc} - i.cmd_ps - cmd_ps - 0x010017b2: b570 p. PUSH {r4-r6,lr} - 0x010017b4: 4604 .F MOV r4,r0 - 0x010017b6: 460d .F MOV r5,r1 - 0x010017b8: f001fa4a ..J. BL list_thread ; 0x1002c50 - 0x010017bc: 2000 . MOVS r0,#0 - 0x010017be: bd70 p. POP {r4-r6,pc} - i.finsh_get_prompt - finsh_get_prompt - 0x010017c0: b510 .. PUSH {r4,lr} - 0x010017c2: 4811 .H LDR r0,[pc,#68] ; [0x1001808] = 0x2001c - 0x010017c4: 6800 .h LDR r0,[r0,#0] - 0x010017c6: 3020 0 ADDS r0,r0,#0x20 - 0x010017c8: 7840 @x LDRB r0,[r0,#1] - 0x010017ca: 0780 .. LSLS r0,r0,#30 - 0x010017cc: 0fc0 .. LSRS r0,r0,#31 - 0x010017ce: 2800 .( CMP r0,#0 - 0x010017d0: d103 .. BNE 0x10017da ; finsh_get_prompt + 26 - 0x010017d2: 490e .I LDR r1,[pc,#56] ; [0x100180c] = 0x201f0 - 0x010017d4: 7008 .p STRB r0,[r1,#0] - 0x010017d6: 4608 .F MOV r0,r1 - 0x010017d8: bd10 .. POP {r4,pc} - 0x010017da: 480d .H LDR r0,[pc,#52] ; [0x1001810] = 0x20020 - 0x010017dc: 6800 .h LDR r0,[r0,#0] - 0x010017de: 2800 .( CMP r0,#0 - 0x010017e0: d007 .. BEQ 0x10017f2 ; finsh_get_prompt + 50 - 0x010017e2: 2280 ." MOVS r2,#0x80 - 0x010017e4: 480a .H LDR r0,[pc,#40] ; [0x1001810] = 0x20020 - 0x010017e6: 6801 .h LDR r1,[r0,#0] - 0x010017e8: 4808 .H LDR r0,[pc,#32] ; [0x100180c] = 0x201f0 - 0x010017ea: f7fff809 .... BL strncpy ; 0x1000800 - 0x010017ee: 4807 .H LDR r0,[pc,#28] ; [0x100180c] = 0x201f0 - 0x010017f0: e7f2 .. B 0x10017d8 ; finsh_get_prompt + 24 - 0x010017f2: a108 .. ADR r1,{pc}+0x22 ; 0x1001814 - 0x010017f4: 4805 .H LDR r0,[pc,#20] ; [0x100180c] = 0x201f0 - 0x010017f6: f7fefefd .... BL strcpy ; 0x10005f4 - 0x010017fa: a108 .. ADR r1,{pc}+0x22 ; 0x100181c - 0x010017fc: 4803 .H LDR r0,[pc,#12] ; [0x100180c] = 0x201f0 - 0x010017fe: f7feff91 .... BL strcat ; 0x1000724 - 0x01001802: 4802 .H LDR r0,[pc,#8] ; [0x100180c] = 0x201f0 - 0x01001804: e7e8 .. B 0x10017d8 ; finsh_get_prompt + 24 - $d - 0x01001806: 0000 .. DCW 0 - 0x01001808: 0002001c .... DCD 131100 - 0x0100180c: 000201f0 .... DCD 131568 - 0x01001810: 00020020 ... DCD 131104 - 0x01001814: 2068736d msh DCD 543716205 - 0x01001818: 00000000 .... DCD 0 - 0x0100181c: 0000003e >... DCD 62 - $t - i.finsh_getchar - finsh_getchar - 0x01001820: b508 .. PUSH {r3,lr} - 0x01001822: 2000 . MOVS r0,#0 - 0x01001824: 9000 .. STR r0,[sp,#0] - 0x01001826: 4810 .H LDR r0,[pc,#64] ; [0x1001868] = 0x2001c - 0x01001828: 6800 .h LDR r0,[r0,#0] - 0x0100182a: 2800 .( CMP r0,#0 - 0x0100182c: d104 .. BNE 0x1001838 ; finsh_getchar + 24 - 0x0100182e: 2299 ." MOVS r2,#0x99 - 0x01001830: 490e .I LDR r1,[pc,#56] ; [0x100186c] = 0x10074b4 - 0x01001832: a00f .. ADR r0,{pc}+0x3e ; 0x1001870 - 0x01001834: f001fee4 .... BL rt_assert_handler ; 0x1003600 - 0x01001838: e005 .. B 0x1001846 ; finsh_getchar + 38 - 0x0100183a: 2100 .! MOVS r1,#0 - 0x0100183c: 43c9 .C MVNS r1,r1 - 0x0100183e: 480a .H LDR r0,[pc,#40] ; [0x1001868] = 0x2001c - 0x01001840: 6800 .h LDR r0,[r0,#0] - 0x01001842: f003fdcd .... BL rt_sem_take ; 0x10053e0 - 0x01001846: 4908 .I LDR r1,[pc,#32] ; [0x1001868] = 0x2001c - 0x01001848: 6809 .h LDR r1,[r1,#0] - 0x0100184a: 31ff .1 ADDS r1,r1,#0xff - 0x0100184c: 31ff .1 ADDS r1,r1,#0xff - 0x0100184e: 3102 .1 ADDS r1,#2 - 0x01001850: 2301 .# MOVS r3,#1 - 0x01001852: 466a jF MOV r2,sp - 0x01001854: 68c8 .h LDR r0,[r1,#0xc] - 0x01001856: 1e99 .. SUBS r1,r3,#2 - 0x01001858: f002f9f4 .... BL rt_device_read ; 0x1003c44 - 0x0100185c: 2801 .( CMP r0,#1 - 0x0100185e: d1ec .. BNE 0x100183a ; finsh_getchar + 26 - 0x01001860: 4668 hF MOV r0,sp - 0x01001862: 7800 .x LDRB r0,[r0,#0] - 0x01001864: bd08 .. POP {r3,pc} - $d - 0x01001866: 0000 .. DCW 0 - 0x01001868: 0002001c .... DCD 131100 - 0x0100186c: 010074b4 .t.. DCD 16807092 - 0x01001870: 6c656873 shel DCD 1818585203 - 0x01001874: 3d21206c l != DCD 1025581164 - 0x01001878: 5f545220 RT_ DCD 1599361568 - 0x0100187c: 4c4c554e NULL DCD 1280070990 - 0x01001880: 00000000 .... DCD 0 - $t - i.finsh_rx_ind - finsh_rx_ind - 0x01001884: b570 p. PUSH {r4-r6,lr} - 0x01001886: 4604 .F MOV r4,r0 - 0x01001888: 460d .F MOV r5,r1 - 0x0100188a: 4807 .H LDR r0,[pc,#28] ; [0x10018a8] = 0x2001c - 0x0100188c: 6800 .h LDR r0,[r0,#0] - 0x0100188e: 2800 .( CMP r0,#0 - 0x01001890: d104 .. BNE 0x100189c ; finsh_rx_ind + 24 - 0x01001892: 22a8 ." MOVS r2,#0xa8 - 0x01001894: 4905 .I LDR r1,[pc,#20] ; [0x10018ac] = 0x10074c2 - 0x01001896: a006 .. ADR r0,{pc}+0x1a ; 0x10018b0 - 0x01001898: f001feb2 .... BL rt_assert_handler ; 0x1003600 - 0x0100189c: 4802 .H LDR r0,[pc,#8] ; [0x10018a8] = 0x2001c - 0x0100189e: 6800 .h LDR r0,[r0,#0] - 0x010018a0: f003fd44 ..D. BL rt_sem_release ; 0x100532c - 0x010018a4: 2000 . MOVS r0,#0 - 0x010018a6: bd70 p. POP {r4-r6,pc} - $d - 0x010018a8: 0002001c .... DCD 131100 - 0x010018ac: 010074c2 .t.. DCD 16807106 - 0x010018b0: 6c656873 shel DCD 1818585203 - 0x010018b4: 3d21206c l != DCD 1025581164 - 0x010018b8: 5f545220 RT_ DCD 1599361568 - 0x010018bc: 4c4c554e NULL DCD 1280070990 - 0x010018c0: 00000000 .... DCD 0 - $t - i.finsh_set_device - finsh_set_device - 0x010018c4: b570 p. PUSH {r4-r6,lr} - 0x010018c6: 4605 .F MOV r5,r0 - 0x010018c8: 2400 .$ MOVS r4,#0 - 0x010018ca: 482e .H LDR r0,[pc,#184] ; [0x1001984] = 0x2001c - 0x010018cc: 6800 .h LDR r0,[r0,#0] - 0x010018ce: 2800 .( CMP r0,#0 - 0x010018d0: d104 .. BNE 0x10018dc ; finsh_set_device + 24 - 0x010018d2: 22bb ." MOVS r2,#0xbb - 0x010018d4: 492c ,I LDR r1,[pc,#176] ; [0x1001988] = 0x10074cf - 0x010018d6: a02d -. ADR r0,{pc}+0xb6 ; 0x100198c - 0x010018d8: f001fe92 .... BL rt_assert_handler ; 0x1003600 - 0x010018dc: 4628 (F MOV r0,r5 - 0x010018de: f002f8d9 .... BL rt_device_find ; 0x1003a94 - 0x010018e2: 4604 .F MOV r4,r0 - 0x010018e4: 2c00 ., CMP r4,#0 - 0x010018e6: d104 .. BNE 0x10018f2 ; finsh_set_device + 46 - 0x010018e8: 4629 )F MOV r1,r5 - 0x010018ea: a02d -. ADR r0,{pc}+0xb6 ; 0x10019a0 - 0x010018ec: f002fdf0 .... BL rt_kprintf ; 0x10044d0 - 0x010018f0: bd70 p. POP {r4-r6,pc} - 0x010018f2: 4824 $H LDR r0,[pc,#144] ; [0x1001984] = 0x2001c - 0x010018f4: 6800 .h LDR r0,[r0,#0] - 0x010018f6: 30ff .0 ADDS r0,r0,#0xff - 0x010018f8: 30ff .0 ADDS r0,r0,#0xff - 0x010018fa: 3002 .0 ADDS r0,#2 - 0x010018fc: 68c0 .h LDR r0,[r0,#0xc] - 0x010018fe: 42a0 .B CMP r0,r4 - 0x01001900: d100 .. BNE 0x1001904 ; finsh_set_device + 64 - 0x01001902: e7f5 .. B 0x10018f0 ; finsh_set_device + 44 - 0x01001904: 21ff .! MOVS r1,#0xff - 0x01001906: 3144 D1 ADDS r1,r1,#0x44 - 0x01001908: 4620 F MOV r0,r4 - 0x0100190a: f002f8cb .... BL rt_device_open ; 0x1003aa4 - 0x0100190e: 2800 .( CMP r0,#0 - 0x01001910: d136 6. BNE 0x1001980 ; finsh_set_device + 188 - 0x01001912: 481c .H LDR r0,[pc,#112] ; [0x1001984] = 0x2001c - 0x01001914: 6800 .h LDR r0,[r0,#0] - 0x01001916: 30ff .0 ADDS r0,r0,#0xff - 0x01001918: 30ff .0 ADDS r0,r0,#0xff - 0x0100191a: 3002 .0 ADDS r0,#2 - 0x0100191c: 68c0 .h LDR r0,[r0,#0xc] - 0x0100191e: 2800 .( CMP r0,#0 - 0x01001920: d010 .. BEQ 0x1001944 ; finsh_set_device + 128 - 0x01001922: 4918 .I LDR r1,[pc,#96] ; [0x1001984] = 0x2001c - 0x01001924: 6809 .h LDR r1,[r1,#0] - 0x01001926: 31ff .1 ADDS r1,r1,#0xff - 0x01001928: 31ff .1 ADDS r1,r1,#0xff - 0x0100192a: 3102 .1 ADDS r1,#2 - 0x0100192c: 68c8 .h LDR r0,[r1,#0xc] - 0x0100192e: f002f855 ..U. BL rt_device_close ; 0x10039dc - 0x01001932: 4914 .I LDR r1,[pc,#80] ; [0x1001984] = 0x2001c - 0x01001934: 6809 .h LDR r1,[r1,#0] - 0x01001936: 31ff .1 ADDS r1,r1,#0xff - 0x01001938: 31ff .1 ADDS r1,r1,#0xff - 0x0100193a: 3102 .1 ADDS r1,#2 - 0x0100193c: 68c8 .h LDR r0,[r1,#0xc] - 0x0100193e: 2100 .! MOVS r1,#0 - 0x01001940: f002f9f6 .... BL rt_device_set_rx_indicate ; 0x1003d30 - 0x01001944: 2151 Q! MOVS r1,#0x51 - 0x01001946: 480f .H LDR r0,[pc,#60] ; [0x1001984] = 0x2001c - 0x01001948: 6800 .h LDR r0,[r0,#0] - 0x0100194a: 30ff .0 ADDS r0,r0,#0xff - 0x0100194c: 30b7 .0 ADDS r0,r0,#0xb7 - 0x0100194e: f7feff52 ..R. BL __aeabi_memclr ; 0x10007f6 - 0x01001952: 2100 .! MOVS r1,#0 - 0x01001954: 480b .H LDR r0,[pc,#44] ; [0x1001984] = 0x2001c - 0x01001956: 6800 .h LDR r0,[r0,#0] - 0x01001958: 30ff .0 ADDS r0,r0,#0xff - 0x0100195a: 30ff .0 ADDS r0,r0,#0xff - 0x0100195c: 3002 .0 ADDS r0,#2 - 0x0100195e: 8101 .. STRH r1,[r0,#8] - 0x01001960: 4808 .H LDR r0,[pc,#32] ; [0x1001984] = 0x2001c - 0x01001962: 6800 .h LDR r0,[r0,#0] - 0x01001964: 30ff .0 ADDS r0,r0,#0xff - 0x01001966: 30ff .0 ADDS r0,r0,#0xff - 0x01001968: 3002 .0 ADDS r0,#2 - 0x0100196a: 8141 A. STRH r1,[r0,#0xa] - 0x0100196c: 4805 .H LDR r0,[pc,#20] ; [0x1001984] = 0x2001c - 0x0100196e: 6800 .h LDR r0,[r0,#0] - 0x01001970: 30ff .0 ADDS r0,r0,#0xff - 0x01001972: 30ff .0 ADDS r0,r0,#0xff - 0x01001974: 3002 .0 ADDS r0,#2 - 0x01001976: 60c4 .` STR r4,[r0,#0xc] - 0x01001978: 4911 .I LDR r1,[pc,#68] ; [0x10019c0] = 0x1001885 - 0x0100197a: 4620 F MOV r0,r4 - 0x0100197c: f002f9d8 .... BL rt_device_set_rx_indicate ; 0x1003d30 - 0x01001980: bf00 .. NOP - 0x01001982: e7b5 .. B 0x10018f0 ; finsh_set_device + 44 - $d - 0x01001984: 0002001c .... DCD 131100 - 0x01001988: 010074cf .t.. DCD 16807119 - 0x0100198c: 6c656873 shel DCD 1818585203 - 0x01001990: 3d21206c l != DCD 1025581164 - 0x01001994: 5f545220 RT_ DCD 1599361568 - 0x01001998: 4c4c554e NULL DCD 1280070990 - 0x0100199c: 00000000 .... DCD 0 - 0x010019a0: 736e6966 fins DCD 1936615782 - 0x010019a4: 63203a68 h: c DCD 1663056488 - 0x010019a8: 6e206e61 an n DCD 1847619169 - 0x010019ac: 6620746f ot f DCD 1713402991 - 0x010019b0: 20646e69 ind DCD 543452777 - 0x010019b4: 69766564 devi DCD 1769366884 - 0x010019b8: 203a6563 ce: DCD 540697955 - 0x010019bc: 000a7325 %s.. DCD 684837 - 0x010019c0: 01001885 .... DCD 16783493 - $t - i.finsh_set_prompt_mode - finsh_set_prompt_mode - 0x010019c4: b510 .. PUSH {r4,lr} - 0x010019c6: 4604 .F MOV r4,r0 - 0x010019c8: 480b .H LDR r0,[pc,#44] ; [0x10019f8] = 0x2001c - 0x010019ca: 6800 .h LDR r0,[r0,#0] - 0x010019cc: 2800 .( CMP r0,#0 - 0x010019ce: d104 .. BNE 0x10019da ; finsh_set_prompt_mode + 22 - 0x010019d0: 228d ." MOVS r2,#0x8d - 0x010019d2: 490a .I LDR r1,[pc,#40] ; [0x10019fc] = 0x100749e - 0x010019d4: a00a .. ADR r0,{pc}+0x2c ; 0x1001a00 - 0x010019d6: f001fe13 .... BL rt_assert_handler ; 0x1003600 - 0x010019da: 4807 .H LDR r0,[pc,#28] ; [0x10019f8] = 0x2001c - 0x010019dc: 6800 .h LDR r0,[r0,#0] - 0x010019de: 3020 0 ADDS r0,r0,#0x20 - 0x010019e0: 7840 @x LDRB r0,[r0,#1] - 0x010019e2: 2102 .! MOVS r1,#2 - 0x010019e4: 4388 .C BICS r0,r0,r1 - 0x010019e6: 0061 a. LSLS r1,r4,#1 - 0x010019e8: 2202 ." MOVS r2,#2 - 0x010019ea: 4011 .@ ANDS r1,r1,r2 - 0x010019ec: 4308 .C ORRS r0,r0,r1 - 0x010019ee: 4902 .I LDR r1,[pc,#8] ; [0x10019f8] = 0x2001c - 0x010019f0: 6809 .h LDR r1,[r1,#0] - 0x010019f2: 3120 1 ADDS r1,r1,#0x20 - 0x010019f4: 7048 Hp STRB r0,[r1,#1] - 0x010019f6: bd10 .. POP {r4,pc} - $d - 0x010019f8: 0002001c .... DCD 131100 - 0x010019fc: 0100749e .t.. DCD 16807070 - 0x01001a00: 6c656873 shel DCD 1818585203 - 0x01001a04: 3d21206c l != DCD 1025581164 - 0x01001a08: 5f545220 RT_ DCD 1599361568 - 0x01001a0c: 4c4c554e NULL DCD 1280070990 - 0x01001a10: 00000000 .... DCD 0 - $t - i.finsh_system_function_init - finsh_system_function_init - 0x01001a14: 4a02 .J LDR r2,[pc,#8] ; [0x1001a20] = 0x20014 - 0x01001a16: 6010 .` STR r0,[r2,#0] - 0x01001a18: 4a02 .J LDR r2,[pc,#8] ; [0x1001a24] = 0x20018 - 0x01001a1a: 6011 .` STR r1,[r2,#0] - 0x01001a1c: 4770 pG BX lr - $d - 0x01001a1e: 0000 .. DCW 0 - 0x01001a20: 00020014 .... DCD 131092 - 0x01001a24: 00020018 .... DCD 131096 - $t - i.finsh_system_init - finsh_system_init - 0x01001a28: b57c |. PUSH {r2-r6,lr} - 0x01001a2a: 2500 .% MOVS r5,#0 - 0x01001a2c: 4919 .I LDR r1,[pc,#100] ; [0x1001a94] = 0x10083e4 - 0x01001a2e: 481a .H LDR r0,[pc,#104] ; [0x1001a98] = 0x100830c - 0x01001a30: f7fffff0 .... BL finsh_system_function_init ; 0x1001a14 - 0x01001a34: 2121 !! MOVS r1,#0x21 - 0x01001a36: 0109 .. LSLS r1,r1,#4 - 0x01001a38: 2001 . MOVS r0,#1 - 0x01001a3a: f001fe1d .... BL rt_calloc ; 0x1003678 - 0x01001a3e: 4917 .I LDR r1,[pc,#92] ; [0x1001a9c] = 0x2001c - 0x01001a40: 6008 .` STR r0,[r1,#0] - 0x01001a42: 4608 .F MOV r0,r1 - 0x01001a44: 6800 .h LDR r0,[r0,#0] - 0x01001a46: 2800 .( CMP r0,#0 - 0x01001a48: d104 .. BNE 0x1001a54 ; finsh_system_init + 44 - 0x01001a4a: a015 .. ADR r0,{pc}+0x56 ; 0x1001aa0 - 0x01001a4c: f002fd40 ..@. BL rt_kprintf ; 0x10044d0 - 0x01001a50: 1e68 h. SUBS r0,r5,#1 - 0x01001a52: bd7c |. POP {r2-r6,pc} - 0x01001a54: 200a . MOVS r0,#0xa - 0x01001a56: 2114 .! MOVS r1,#0x14 - 0x01001a58: 2301 .# MOVS r3,#1 - 0x01001a5a: 031b .. LSLS r3,r3,#12 - 0x01001a5c: 2200 ." MOVS r2,#0 - 0x01001a5e: 9100 .. STR r1,[sp,#0] - 0x01001a60: 9001 .. STR r0,[sp,#4] - 0x01001a62: 4915 .I LDR r1,[pc,#84] ; [0x1001ab8] = 0x1001acd - 0x01001a64: a015 .. ADR r0,{pc}+0x58 ; 0x1001abc - 0x01001a66: f004f96c ..l. BL rt_thread_create ; 0x1005d42 - 0x01001a6a: 4604 .F MOV r4,r0 - 0x01001a6c: 2300 .# MOVS r3,#0 - 0x01001a6e: 461a .F MOV r2,r3 - 0x01001a70: a114 .. ADR r1,{pc}+0x54 ; 0x1001ac4 - 0x01001a72: 480a .H LDR r0,[pc,#40] ; [0x1001a9c] = 0x2001c - 0x01001a74: 6800 .h LDR r0,[r0,#0] - 0x01001a76: f003fc21 ..!. BL rt_sem_init ; 0x10052bc - 0x01001a7a: 2001 . MOVS r0,#1 - 0x01001a7c: f7ffffa2 .... BL finsh_set_prompt_mode ; 0x10019c4 - 0x01001a80: 2c00 ., CMP r4,#0 - 0x01001a82: d004 .. BEQ 0x1001a8e ; finsh_system_init + 102 - 0x01001a84: 2d00 .- CMP r5,#0 - 0x01001a86: d102 .. BNE 0x1001a8e ; finsh_system_init + 102 - 0x01001a88: 4620 F MOV r0,r4 - 0x01001a8a: f004fad1 .... BL rt_thread_startup ; 0x1006030 - 0x01001a8e: 2000 . MOVS r0,#0 - 0x01001a90: e7df .. B 0x1001a52 ; finsh_system_init + 42 - $d - 0x01001a92: 0000 .. DCW 0 - 0x01001a94: 010083e4 .... DCD 16810980 - 0x01001a98: 0100830c .... DCD 16810764 - 0x01001a9c: 0002001c .... DCD 131100 - 0x01001aa0: 6d206f6e no m DCD 1830842222 - 0x01001aa4: 726f6d65 emor DCD 1919905125 - 0x01001aa8: 6f662079 y fo DCD 1868963961 - 0x01001aac: 68732072 r sh DCD 1752375410 - 0x01001ab0: 0a6c6c65 ell. DCD 174877797 - 0x01001ab4: 00000000 .... DCD 0 - 0x01001ab8: 01001acd .... DCD 16784077 - 0x01001abc: 65687374 tshe DCD 1701344116 - 0x01001ac0: 00006c6c ll.. DCD 27756 - 0x01001ac4: 78726873 shrx DCD 2020763763 - 0x01001ac8: 00000000 .... DCD 0 - $t - i.finsh_thread_entry - finsh_thread_entry - 0x01001acc: 48fe .H LDR r0,[pc,#1016] ; [0x1001ec8] = 0x2001c - 0x01001ace: 6800 .h LDR r0,[r0,#0] - 0x01001ad0: 3020 0 ADDS r0,r0,#0x20 - 0x01001ad2: 7840 @x LDRB r0,[r0,#1] - 0x01001ad4: 0840 @. LSRS r0,r0,#1 - 0x01001ad6: 0040 @. LSLS r0,r0,#1 - 0x01001ad8: 1c40 @. ADDS r0,r0,#1 - 0x01001ada: 49fb .I LDR r1,[pc,#1004] ; [0x1001ec8] = 0x2001c - 0x01001adc: 6809 .h LDR r1,[r1,#0] - 0x01001ade: 3120 1 ADDS r1,r1,#0x20 - 0x01001ae0: 7048 Hp STRB r0,[r1,#1] - 0x01001ae2: 48f9 .H LDR r0,[pc,#996] ; [0x1001ec8] = 0x2001c - 0x01001ae4: 6800 .h LDR r0,[r0,#0] - 0x01001ae6: 30ff .0 ADDS r0,r0,#0xff - 0x01001ae8: 30ff .0 ADDS r0,r0,#0xff - 0x01001aea: 3002 .0 ADDS r0,#2 - 0x01001aec: 68c0 .h LDR r0,[r0,#0xc] - 0x01001aee: 2800 .( CMP r0,#0 - 0x01001af0: d108 .. BNE 0x1001b04 ; finsh_thread_entry + 56 - 0x01001af2: f001feed .... BL rt_console_get_device ; 0x10038d0 - 0x01001af6: 4605 .F MOV r5,r0 - 0x01001af8: 2d00 .- CMP r5,#0 - 0x01001afa: d002 .. BEQ 0x1001b02 ; finsh_thread_entry + 54 - 0x01001afc: 4628 (F MOV r0,r5 - 0x01001afe: f7fffee1 .... BL finsh_set_device ; 0x10018c4 - 0x01001b02: bf00 .. NOP - 0x01001b04: f7fffe5c ..\. BL finsh_get_prompt ; 0x10017c0 - 0x01001b08: 4605 .F MOV r5,r0 - 0x01001b0a: f002fce1 .... BL rt_kprintf ; 0x10044d0 - 0x01001b0e: e2cf .. B 0x10020b0 ; finsh_thread_entry + 1508 - 0x01001b10: f7fffe86 .... BL finsh_getchar ; 0x1001820 - 0x01001b14: 4604 .F MOV r4,r0 - 0x01001b16: 2c00 ., CMP r4,#0 - 0x01001b18: da00 .. BGE 0x1001b1c ; finsh_thread_entry + 80 - 0x01001b1a: e2c9 .. B 0x10020b0 ; finsh_thread_entry + 1508 - 0x01001b1c: 2c1b ., CMP r4,#0x1b - 0x01001b1e: d105 .. BNE 0x1001b2c ; finsh_thread_entry + 96 - 0x01001b20: 2101 .! MOVS r1,#1 - 0x01001b22: 48e9 .H LDR r0,[pc,#932] ; [0x1001ec8] = 0x2001c - 0x01001b24: 6800 .h LDR r0,[r0,#0] - 0x01001b26: 3020 0 ADDS r0,r0,#0x20 - 0x01001b28: 7001 .p STRB r1,[r0,#0] - 0x01001b2a: e2c1 .. B 0x10020b0 ; finsh_thread_entry + 1508 - 0x01001b2c: 48e6 .H LDR r0,[pc,#920] ; [0x1001ec8] = 0x2001c - 0x01001b2e: 6800 .h LDR r0,[r0,#0] - 0x01001b30: 3020 0 ADDS r0,r0,#0x20 - 0x01001b32: 7800 .x LDRB r0,[r0,#0] - 0x01001b34: 2801 .( CMP r0,#1 - 0x01001b36: d10d .. BNE 0x1001b54 ; finsh_thread_entry + 136 - 0x01001b38: 2c5b [, CMP r4,#0x5b - 0x01001b3a: d105 .. BNE 0x1001b48 ; finsh_thread_entry + 124 - 0x01001b3c: 2102 .! MOVS r1,#2 - 0x01001b3e: 48e2 .H LDR r0,[pc,#904] ; [0x1001ec8] = 0x2001c - 0x01001b40: 6800 .h LDR r0,[r0,#0] - 0x01001b42: 3020 0 ADDS r0,r0,#0x20 - 0x01001b44: 7001 .p STRB r1,[r0,#0] - 0x01001b46: e2b3 .. B 0x10020b0 ; finsh_thread_entry + 1508 - 0x01001b48: 2100 .! MOVS r1,#0 - 0x01001b4a: 48df .H LDR r0,[pc,#892] ; [0x1001ec8] = 0x2001c - 0x01001b4c: 6800 .h LDR r0,[r0,#0] - 0x01001b4e: 3020 0 ADDS r0,r0,#0x20 - 0x01001b50: 7001 .p STRB r1,[r0,#0] - 0x01001b52: e0d8 .. B 0x1001d06 ; finsh_thread_entry + 570 - 0x01001b54: 48dc .H LDR r0,[pc,#880] ; [0x1001ec8] = 0x2001c - 0x01001b56: 6800 .h LDR r0,[r0,#0] - 0x01001b58: 3020 0 ADDS r0,r0,#0x20 - 0x01001b5a: 7800 .x LDRB r0,[r0,#0] - 0x01001b5c: 2802 .( CMP r0,#2 - 0x01001b5e: d1f8 .. BNE 0x1001b52 ; finsh_thread_entry + 134 - 0x01001b60: 2100 .! MOVS r1,#0 - 0x01001b62: 48d9 .H LDR r0,[pc,#868] ; [0x1001ec8] = 0x2001c - 0x01001b64: 6800 .h LDR r0,[r0,#0] - 0x01001b66: 3020 0 ADDS r0,r0,#0x20 - 0x01001b68: 7001 .p STRB r1,[r0,#0] - 0x01001b6a: 2c41 A, CMP r4,#0x41 - 0x01001b6c: d139 9. BNE 0x1001be2 ; finsh_thread_entry + 278 - 0x01001b6e: 48d6 .H LDR r0,[pc,#856] ; [0x1001ec8] = 0x2001c - 0x01001b70: 6800 .h LDR r0,[r0,#0] - 0x01001b72: 8c40 @. LDRH r0,[r0,#0x22] - 0x01001b74: 2800 .( CMP r0,#0 - 0x01001b76: dd07 .. BLE 0x1001b88 ; finsh_thread_entry + 188 - 0x01001b78: 48d3 .H LDR r0,[pc,#844] ; [0x1001ec8] = 0x2001c - 0x01001b7a: 6800 .h LDR r0,[r0,#0] - 0x01001b7c: 8c40 @. LDRH r0,[r0,#0x22] - 0x01001b7e: 1e40 @. SUBS r0,r0,#1 - 0x01001b80: 49d1 .I LDR r1,[pc,#836] ; [0x1001ec8] = 0x2001c - 0x01001b82: 6809 .h LDR r1,[r1,#0] - 0x01001b84: 8448 H. STRH r0,[r1,#0x22] - 0x01001b86: e004 .. B 0x1001b92 ; finsh_thread_entry + 198 - 0x01001b88: 2000 . MOVS r0,#0 - 0x01001b8a: 49cf .I LDR r1,[pc,#828] ; [0x1001ec8] = 0x2001c - 0x01001b8c: 6809 .h LDR r1,[r1,#0] - 0x01001b8e: 8448 H. STRH r0,[r1,#0x22] - 0x01001b90: e28e .. B 0x10020b0 ; finsh_thread_entry + 1508 - 0x01001b92: 48cd .H LDR r0,[pc,#820] ; [0x1001ec8] = 0x2001c - 0x01001b94: 6800 .h LDR r0,[r0,#0] - 0x01001b96: 8c40 @. LDRH r0,[r0,#0x22] - 0x01001b98: 2250 P" MOVS r2,#0x50 - 0x01001b9a: 4350 PC MULS r0,r2,r0 - 0x01001b9c: 4aca .J LDR r2,[pc,#808] ; [0x1001ec8] = 0x2001c - 0x01001b9e: 6812 .h LDR r2,[r2,#0] - 0x01001ba0: 3226 &2 ADDS r2,r2,#0x26 - 0x01001ba2: 1881 .. ADDS r1,r0,r2 - 0x01001ba4: 2250 P" MOVS r2,#0x50 - 0x01001ba6: 48c8 .H LDR r0,[pc,#800] ; [0x1001ec8] = 0x2001c - 0x01001ba8: 6800 .h LDR r0,[r0,#0] - 0x01001baa: 30ff .0 ADDS r0,r0,#0xff - 0x01001bac: 30b7 .0 ADDS r0,r0,#0xb7 - 0x01001bae: f7fefdc5 .... BL __aeabi_memcpy ; 0x100073c - 0x01001bb2: 48c5 .H LDR r0,[pc,#788] ; [0x1001ec8] = 0x2001c - 0x01001bb4: 6800 .h LDR r0,[r0,#0] - 0x01001bb6: 30ff .0 ADDS r0,r0,#0xff - 0x01001bb8: 30b7 .0 ADDS r0,r0,#0xb7 - 0x01001bba: f7fefd41 ..A. BL strlen ; 0x1000640 - 0x01001bbe: b281 .. UXTH r1,r0 - 0x01001bc0: 48c1 .H LDR r0,[pc,#772] ; [0x1001ec8] = 0x2001c - 0x01001bc2: 6800 .h LDR r0,[r0,#0] - 0x01001bc4: 30ff .0 ADDS r0,r0,#0xff - 0x01001bc6: 30ff .0 ADDS r0,r0,#0xff - 0x01001bc8: 3002 .0 ADDS r0,#2 - 0x01001bca: 8101 .. STRH r1,[r0,#8] - 0x01001bcc: 48be .H LDR r0,[pc,#760] ; [0x1001ec8] = 0x2001c - 0x01001bce: 6800 .h LDR r0,[r0,#0] - 0x01001bd0: 30ff .0 ADDS r0,r0,#0xff - 0x01001bd2: 30ff .0 ADDS r0,r0,#0xff - 0x01001bd4: 3002 .0 ADDS r0,#2 - 0x01001bd6: 8141 A. STRH r1,[r0,#0xa] - 0x01001bd8: 48bb .H LDR r0,[pc,#748] ; [0x1001ec8] = 0x2001c - 0x01001bda: 6800 .h LDR r0,[r0,#0] - 0x01001bdc: f005f874 ..t. BL shell_handle_history ; 0x1006cc8 - 0x01001be0: e266 f. B 0x10020b0 ; finsh_thread_entry + 1508 - 0x01001be2: 2c42 B, CMP r4,#0x42 - 0x01001be4: d146 F. BNE 0x1001c74 ; finsh_thread_entry + 424 - 0x01001be6: 48b8 .H LDR r0,[pc,#736] ; [0x1001ec8] = 0x2001c - 0x01001be8: 6800 .h LDR r0,[r0,#0] - 0x01001bea: 8c41 A. LDRH r1,[r0,#0x22] - 0x01001bec: 48b6 .H LDR r0,[pc,#728] ; [0x1001ec8] = 0x2001c - 0x01001bee: 6800 .h LDR r0,[r0,#0] - 0x01001bf0: 8c80 .. LDRH r0,[r0,#0x24] - 0x01001bf2: 1e40 @. SUBS r0,r0,#1 - 0x01001bf4: 4281 .B CMP r1,r0 - 0x01001bf6: da07 .. BGE 0x1001c08 ; finsh_thread_entry + 316 - 0x01001bf8: 48b3 .H LDR r0,[pc,#716] ; [0x1001ec8] = 0x2001c - 0x01001bfa: 6800 .h LDR r0,[r0,#0] - 0x01001bfc: 8c40 @. LDRH r0,[r0,#0x22] - 0x01001bfe: 1c40 @. ADDS r0,r0,#1 - 0x01001c00: 49b1 .I LDR r1,[pc,#708] ; [0x1001ec8] = 0x2001c - 0x01001c02: 6809 .h LDR r1,[r1,#0] - 0x01001c04: 8448 H. STRH r0,[r1,#0x22] - 0x01001c06: e00d .. B 0x1001c24 ; finsh_thread_entry + 344 - 0x01001c08: 48af .H LDR r0,[pc,#700] ; [0x1001ec8] = 0x2001c - 0x01001c0a: 6800 .h LDR r0,[r0,#0] - 0x01001c0c: 8c80 .. LDRH r0,[r0,#0x24] - 0x01001c0e: 2800 .( CMP r0,#0 - 0x01001c10: d007 .. BEQ 0x1001c22 ; finsh_thread_entry + 342 - 0x01001c12: 48ad .H LDR r0,[pc,#692] ; [0x1001ec8] = 0x2001c - 0x01001c14: 6800 .h LDR r0,[r0,#0] - 0x01001c16: 8c80 .. LDRH r0,[r0,#0x24] - 0x01001c18: 1e40 @. SUBS r0,r0,#1 - 0x01001c1a: 49ab .I LDR r1,[pc,#684] ; [0x1001ec8] = 0x2001c - 0x01001c1c: 6809 .h LDR r1,[r1,#0] - 0x01001c1e: 8448 H. STRH r0,[r1,#0x22] - 0x01001c20: e000 .. B 0x1001c24 ; finsh_thread_entry + 344 - 0x01001c22: e245 E. B 0x10020b0 ; finsh_thread_entry + 1508 - 0x01001c24: 48a8 .H LDR r0,[pc,#672] ; [0x1001ec8] = 0x2001c - 0x01001c26: 6800 .h LDR r0,[r0,#0] - 0x01001c28: 8c40 @. LDRH r0,[r0,#0x22] - 0x01001c2a: 2250 P" MOVS r2,#0x50 - 0x01001c2c: 4350 PC MULS r0,r2,r0 - 0x01001c2e: 4aa6 .J LDR r2,[pc,#664] ; [0x1001ec8] = 0x2001c - 0x01001c30: 6812 .h LDR r2,[r2,#0] - 0x01001c32: 3226 &2 ADDS r2,r2,#0x26 - 0x01001c34: 1881 .. ADDS r1,r0,r2 - 0x01001c36: 2250 P" MOVS r2,#0x50 - 0x01001c38: 48a3 .H LDR r0,[pc,#652] ; [0x1001ec8] = 0x2001c - 0x01001c3a: 6800 .h LDR r0,[r0,#0] - 0x01001c3c: 30ff .0 ADDS r0,r0,#0xff - 0x01001c3e: 30b7 .0 ADDS r0,r0,#0xb7 - 0x01001c40: f7fefd7c ..|. BL __aeabi_memcpy ; 0x100073c - 0x01001c44: 48a0 .H LDR r0,[pc,#640] ; [0x1001ec8] = 0x2001c - 0x01001c46: 6800 .h LDR r0,[r0,#0] - 0x01001c48: 30ff .0 ADDS r0,r0,#0xff - 0x01001c4a: 30b7 .0 ADDS r0,r0,#0xb7 - 0x01001c4c: f7fefcf8 .... BL strlen ; 0x1000640 - 0x01001c50: b281 .. UXTH r1,r0 - 0x01001c52: 489d .H LDR r0,[pc,#628] ; [0x1001ec8] = 0x2001c - 0x01001c54: 6800 .h LDR r0,[r0,#0] - 0x01001c56: 30ff .0 ADDS r0,r0,#0xff - 0x01001c58: 30ff .0 ADDS r0,r0,#0xff - 0x01001c5a: 3002 .0 ADDS r0,#2 - 0x01001c5c: 8101 .. STRH r1,[r0,#8] - 0x01001c5e: 489a .H LDR r0,[pc,#616] ; [0x1001ec8] = 0x2001c - 0x01001c60: 6800 .h LDR r0,[r0,#0] - 0x01001c62: 30ff .0 ADDS r0,r0,#0xff - 0x01001c64: 30ff .0 ADDS r0,r0,#0xff - 0x01001c66: 3002 .0 ADDS r0,#2 - 0x01001c68: 8141 A. STRH r1,[r0,#0xa] - 0x01001c6a: 4897 .H LDR r0,[pc,#604] ; [0x1001ec8] = 0x2001c - 0x01001c6c: 6800 .h LDR r0,[r0,#0] - 0x01001c6e: f005f82b ..+. BL shell_handle_history ; 0x1006cc8 - 0x01001c72: e21d .. B 0x10020b0 ; finsh_thread_entry + 1508 - 0x01001c74: 2c44 D, CMP r4,#0x44 - 0x01001c76: d119 .. BNE 0x1001cac ; finsh_thread_entry + 480 - 0x01001c78: 4893 .H LDR r0,[pc,#588] ; [0x1001ec8] = 0x2001c - 0x01001c7a: 6800 .h LDR r0,[r0,#0] - 0x01001c7c: 30ff .0 ADDS r0,r0,#0xff - 0x01001c7e: 30ff .0 ADDS r0,r0,#0xff - 0x01001c80: 3002 .0 ADDS r0,#2 - 0x01001c82: 8940 @. LDRH r0,[r0,#0xa] - 0x01001c84: 2800 .( CMP r0,#0 - 0x01001c86: d010 .. BEQ 0x1001caa ; finsh_thread_entry + 478 - 0x01001c88: a090 .. ADR r0,{pc}+0x244 ; 0x1001ecc - 0x01001c8a: f002fc21 ..!. BL rt_kprintf ; 0x10044d0 - 0x01001c8e: 488e .H LDR r0,[pc,#568] ; [0x1001ec8] = 0x2001c - 0x01001c90: 6800 .h LDR r0,[r0,#0] - 0x01001c92: 30ff .0 ADDS r0,r0,#0xff - 0x01001c94: 30ff .0 ADDS r0,r0,#0xff - 0x01001c96: 3002 .0 ADDS r0,#2 - 0x01001c98: 8940 @. LDRH r0,[r0,#0xa] - 0x01001c9a: 1e40 @. SUBS r0,r0,#1 - 0x01001c9c: b281 .. UXTH r1,r0 - 0x01001c9e: 488a .H LDR r0,[pc,#552] ; [0x1001ec8] = 0x2001c - 0x01001ca0: 6800 .h LDR r0,[r0,#0] - 0x01001ca2: 30ff .0 ADDS r0,r0,#0xff - 0x01001ca4: 30ff .0 ADDS r0,r0,#0xff - 0x01001ca6: 3002 .0 ADDS r0,#2 - 0x01001ca8: 8141 A. STRH r1,[r0,#0xa] - 0x01001caa: e201 .. B 0x10020b0 ; finsh_thread_entry + 1508 - 0x01001cac: 2c43 C, CMP r4,#0x43 - 0x01001cae: d12a *. BNE 0x1001d06 ; finsh_thread_entry + 570 - 0x01001cb0: 4885 .H LDR r0,[pc,#532] ; [0x1001ec8] = 0x2001c - 0x01001cb2: 6800 .h LDR r0,[r0,#0] - 0x01001cb4: 30ff .0 ADDS r0,r0,#0xff - 0x01001cb6: 30ff .0 ADDS r0,r0,#0xff - 0x01001cb8: 3002 .0 ADDS r0,#2 - 0x01001cba: 8941 A. LDRH r1,[r0,#0xa] - 0x01001cbc: 4882 .H LDR r0,[pc,#520] ; [0x1001ec8] = 0x2001c - 0x01001cbe: 6800 .h LDR r0,[r0,#0] - 0x01001cc0: 30ff .0 ADDS r0,r0,#0xff - 0x01001cc2: 30ff .0 ADDS r0,r0,#0xff - 0x01001cc4: 3002 .0 ADDS r0,#2 - 0x01001cc6: 8900 .. LDRH r0,[r0,#8] - 0x01001cc8: 4281 .B CMP r1,r0 - 0x01001cca: da1b .. BGE 0x1001d04 ; finsh_thread_entry + 568 - 0x01001ccc: 487e ~H LDR r0,[pc,#504] ; [0x1001ec8] = 0x2001c - 0x01001cce: 6800 .h LDR r0,[r0,#0] - 0x01001cd0: 30ff .0 ADDS r0,r0,#0xff - 0x01001cd2: 30ff .0 ADDS r0,r0,#0xff - 0x01001cd4: 3002 .0 ADDS r0,#2 - 0x01001cd6: 8942 B. LDRH r2,[r0,#0xa] - 0x01001cd8: 487b {H LDR r0,[pc,#492] ; [0x1001ec8] = 0x2001c - 0x01001cda: 6800 .h LDR r0,[r0,#0] - 0x01001cdc: 30ff .0 ADDS r0,r0,#0xff - 0x01001cde: 30b7 .0 ADDS r0,r0,#0xb7 - 0x01001ce0: 5c81 .\ LDRB r1,[r0,r2] - 0x01001ce2: a07b {. ADR r0,{pc}+0x1ee ; 0x1001ed0 - 0x01001ce4: f002fbf4 .... BL rt_kprintf ; 0x10044d0 - 0x01001ce8: 4877 wH LDR r0,[pc,#476] ; [0x1001ec8] = 0x2001c - 0x01001cea: 6800 .h LDR r0,[r0,#0] - 0x01001cec: 30ff .0 ADDS r0,r0,#0xff - 0x01001cee: 30ff .0 ADDS r0,r0,#0xff - 0x01001cf0: 3002 .0 ADDS r0,#2 - 0x01001cf2: 8940 @. LDRH r0,[r0,#0xa] - 0x01001cf4: 1c40 @. ADDS r0,r0,#1 - 0x01001cf6: b281 .. UXTH r1,r0 - 0x01001cf8: 4873 sH LDR r0,[pc,#460] ; [0x1001ec8] = 0x2001c - 0x01001cfa: 6800 .h LDR r0,[r0,#0] - 0x01001cfc: 30ff .0 ADDS r0,r0,#0xff - 0x01001cfe: 30ff .0 ADDS r0,r0,#0xff - 0x01001d00: 3002 .0 ADDS r0,#2 - 0x01001d02: 8141 A. STRH r1,[r0,#0xa] - 0x01001d04: e1d4 .. B 0x10020b0 ; finsh_thread_entry + 1508 - 0x01001d06: 2c00 ., CMP r4,#0 - 0x01001d08: d001 .. BEQ 0x1001d0e ; finsh_thread_entry + 578 - 0x01001d0a: 2cff ., CMP r4,#0xff - 0x01001d0c: d100 .. BNE 0x1001d10 ; finsh_thread_entry + 580 - 0x01001d0e: e1cf .. B 0x10020b0 ; finsh_thread_entry + 1508 - 0x01001d10: 2c09 ., CMP r4,#9 - 0x01001d12: d127 '. BNE 0x1001d64 ; finsh_thread_entry + 664 - 0x01001d14: 2500 .% MOVS r5,#0 - 0x01001d16: e003 .. B 0x1001d20 ; finsh_thread_entry + 596 - 0x01001d18: a06c l. ADR r0,{pc}+0x1b4 ; 0x1001ecc - 0x01001d1a: f002fbd9 .... BL rt_kprintf ; 0x10044d0 - 0x01001d1e: 1c6d m. ADDS r5,r5,#1 - 0x01001d20: 4869 iH LDR r0,[pc,#420] ; [0x1001ec8] = 0x2001c - 0x01001d22: 6800 .h LDR r0,[r0,#0] - 0x01001d24: 30ff .0 ADDS r0,r0,#0xff - 0x01001d26: 30ff .0 ADDS r0,r0,#0xff - 0x01001d28: 3002 .0 ADDS r0,#2 - 0x01001d2a: 8940 @. LDRH r0,[r0,#0xa] - 0x01001d2c: 42a8 .B CMP r0,r5 - 0x01001d2e: dcf3 .. BGT 0x1001d18 ; finsh_thread_entry + 588 - 0x01001d30: 4865 eH LDR r0,[pc,#404] ; [0x1001ec8] = 0x2001c - 0x01001d32: 6800 .h LDR r0,[r0,#0] - 0x01001d34: 30ff .0 ADDS r0,r0,#0xff - 0x01001d36: 30b7 .0 ADDS r0,r0,#0xb7 - 0x01001d38: f004ffae .... BL shell_auto_complete ; 0x1006c98 - 0x01001d3c: 4862 bH LDR r0,[pc,#392] ; [0x1001ec8] = 0x2001c - 0x01001d3e: 6800 .h LDR r0,[r0,#0] - 0x01001d40: 30ff .0 ADDS r0,r0,#0xff - 0x01001d42: 30b7 .0 ADDS r0,r0,#0xb7 - 0x01001d44: f7fefc7c ..|. BL strlen ; 0x1000640 - 0x01001d48: b281 .. UXTH r1,r0 - 0x01001d4a: 485f _H LDR r0,[pc,#380] ; [0x1001ec8] = 0x2001c - 0x01001d4c: 6800 .h LDR r0,[r0,#0] - 0x01001d4e: 30ff .0 ADDS r0,r0,#0xff - 0x01001d50: 30ff .0 ADDS r0,r0,#0xff - 0x01001d52: 3002 .0 ADDS r0,#2 - 0x01001d54: 8101 .. STRH r1,[r0,#8] - 0x01001d56: 485c \H LDR r0,[pc,#368] ; [0x1001ec8] = 0x2001c - 0x01001d58: 6800 .h LDR r0,[r0,#0] - 0x01001d5a: 30ff .0 ADDS r0,r0,#0xff - 0x01001d5c: 30ff .0 ADDS r0,r0,#0xff - 0x01001d5e: 3002 .0 ADDS r0,#2 - 0x01001d60: 8141 A. STRH r1,[r0,#0xa] - 0x01001d62: e1a5 .. B 0x10020b0 ; finsh_thread_entry + 1508 - 0x01001d64: 2c7f ., CMP r4,#0x7f - 0x01001d66: d001 .. BEQ 0x1001d6c ; finsh_thread_entry + 672 - 0x01001d68: 2c08 ., CMP r4,#8 - 0x01001d6a: d179 y. BNE 0x1001e60 ; finsh_thread_entry + 916 - 0x01001d6c: 4856 VH LDR r0,[pc,#344] ; [0x1001ec8] = 0x2001c - 0x01001d6e: 6800 .h LDR r0,[r0,#0] - 0x01001d70: 30ff .0 ADDS r0,r0,#0xff - 0x01001d72: 30ff .0 ADDS r0,r0,#0xff - 0x01001d74: 3002 .0 ADDS r0,#2 - 0x01001d76: 8940 @. LDRH r0,[r0,#0xa] - 0x01001d78: 2800 .( CMP r0,#0 - 0x01001d7a: d100 .. BNE 0x1001d7e ; finsh_thread_entry + 690 - 0x01001d7c: e198 .. B 0x10020b0 ; finsh_thread_entry + 1508 - 0x01001d7e: 4852 RH LDR r0,[pc,#328] ; [0x1001ec8] = 0x2001c - 0x01001d80: 6800 .h LDR r0,[r0,#0] - 0x01001d82: 30ff .0 ADDS r0,r0,#0xff - 0x01001d84: 30ff .0 ADDS r0,r0,#0xff - 0x01001d86: 3002 .0 ADDS r0,#2 - 0x01001d88: 8900 .. LDRH r0,[r0,#8] - 0x01001d8a: 1e40 @. SUBS r0,r0,#1 - 0x01001d8c: b281 .. UXTH r1,r0 - 0x01001d8e: 484e NH LDR r0,[pc,#312] ; [0x1001ec8] = 0x2001c - 0x01001d90: 6800 .h LDR r0,[r0,#0] - 0x01001d92: 30ff .0 ADDS r0,r0,#0xff - 0x01001d94: 30ff .0 ADDS r0,r0,#0xff - 0x01001d96: 3002 .0 ADDS r0,#2 - 0x01001d98: 8101 .. STRH r1,[r0,#8] - 0x01001d9a: 484b KH LDR r0,[pc,#300] ; [0x1001ec8] = 0x2001c - 0x01001d9c: 6800 .h LDR r0,[r0,#0] - 0x01001d9e: 30ff .0 ADDS r0,r0,#0xff - 0x01001da0: 30ff .0 ADDS r0,r0,#0xff - 0x01001da2: 3002 .0 ADDS r0,#2 - 0x01001da4: 8940 @. LDRH r0,[r0,#0xa] - 0x01001da6: 1e40 @. SUBS r0,r0,#1 - 0x01001da8: b281 .. UXTH r1,r0 - 0x01001daa: 4847 GH LDR r0,[pc,#284] ; [0x1001ec8] = 0x2001c - 0x01001dac: 6800 .h LDR r0,[r0,#0] - 0x01001dae: 30ff .0 ADDS r0,r0,#0xff - 0x01001db0: 30ff .0 ADDS r0,r0,#0xff - 0x01001db2: 3002 .0 ADDS r0,#2 - 0x01001db4: 8141 A. STRH r1,[r0,#0xa] - 0x01001db6: 4844 DH LDR r0,[pc,#272] ; [0x1001ec8] = 0x2001c - 0x01001db8: 6800 .h LDR r0,[r0,#0] - 0x01001dba: 30ff .0 ADDS r0,r0,#0xff - 0x01001dbc: 30ff .0 ADDS r0,r0,#0xff - 0x01001dbe: 3002 .0 ADDS r0,#2 - 0x01001dc0: 8901 .. LDRH r1,[r0,#8] - 0x01001dc2: 4841 AH LDR r0,[pc,#260] ; [0x1001ec8] = 0x2001c - 0x01001dc4: 6800 .h LDR r0,[r0,#0] - 0x01001dc6: 30ff .0 ADDS r0,r0,#0xff - 0x01001dc8: 30ff .0 ADDS r0,r0,#0xff - 0x01001dca: 3002 .0 ADDS r0,#2 - 0x01001dcc: 8940 @. LDRH r0,[r0,#0xa] - 0x01001dce: 4281 .B CMP r1,r0 - 0x01001dd0: dd54 T. BLE 0x1001e7c ; finsh_thread_entry + 944 - 0x01001dd2: 4b3d =K LDR r3,[pc,#244] ; [0x1001ec8] = 0x2001c - 0x01001dd4: 681b .h LDR r3,[r3,#0] - 0x01001dd6: 33ff .3 ADDS r3,r3,#0xff - 0x01001dd8: 33ff .3 ADDS r3,r3,#0xff - 0x01001dda: 3302 .3 ADDS r3,#2 - 0x01001ddc: 891e .. LDRH r6,[r3,#8] - 0x01001dde: 4b3a :K LDR r3,[pc,#232] ; [0x1001ec8] = 0x2001c - 0x01001de0: 681b .h LDR r3,[r3,#0] - 0x01001de2: 33ff .3 ADDS r3,r3,#0xff - 0x01001de4: 33ff .3 ADDS r3,r3,#0xff - 0x01001de6: 3302 .3 ADDS r3,#2 - 0x01001de8: 895b [. LDRH r3,[r3,#0xa] - 0x01001dea: 1af2 .. SUBS r2,r6,r3 - 0x01001dec: 4b36 6K LDR r3,[pc,#216] ; [0x1001ec8] = 0x2001c - 0x01001dee: 681b .h LDR r3,[r3,#0] - 0x01001df0: 33ff .3 ADDS r3,r3,#0xff - 0x01001df2: 33ff .3 ADDS r3,r3,#0xff - 0x01001df4: 3302 .3 ADDS r3,#2 - 0x01001df6: 895b [. LDRH r3,[r3,#0xa] - 0x01001df8: 1c5b [. ADDS r3,r3,#1 - 0x01001dfa: 4e33 3N LDR r6,[pc,#204] ; [0x1001ec8] = 0x2001c - 0x01001dfc: 6836 6h LDR r6,[r6,#0] - 0x01001dfe: 36ff .6 ADDS r6,r6,#0xff - 0x01001e00: 36b7 .6 ADDS r6,r6,#0xb7 - 0x01001e02: 1999 .. ADDS r1,r3,r6 - 0x01001e04: 4b30 0K LDR r3,[pc,#192] ; [0x1001ec8] = 0x2001c - 0x01001e06: 681b .h LDR r3,[r3,#0] - 0x01001e08: 33ff .3 ADDS r3,r3,#0xff - 0x01001e0a: 33ff .3 ADDS r3,r3,#0xff - 0x01001e0c: 3302 .3 ADDS r3,#2 - 0x01001e0e: 895e ^. LDRH r6,[r3,#0xa] - 0x01001e10: 4b2d -K LDR r3,[pc,#180] ; [0x1001ec8] = 0x2001c - 0x01001e12: 681b .h LDR r3,[r3,#0] - 0x01001e14: 33ff .3 ADDS r3,r3,#0xff - 0x01001e16: 33b7 .3 ADDS r3,r3,#0xb7 - 0x01001e18: 18f0 .. ADDS r0,r6,r3 - 0x01001e1a: f002fe31 ..1. BL rt_memmove ; 0x1004a80 - 0x01001e1e: 2100 .! MOVS r1,#0 - 0x01001e20: 4829 )H LDR r0,[pc,#164] ; [0x1001ec8] = 0x2001c - 0x01001e22: 6800 .h LDR r0,[r0,#0] - 0x01001e24: 30ff .0 ADDS r0,r0,#0xff - 0x01001e26: 30ff .0 ADDS r0,r0,#0xff - 0x01001e28: 3002 .0 ADDS r0,#2 - 0x01001e2a: 8902 .. LDRH r2,[r0,#8] - 0x01001e2c: 4826 &H LDR r0,[pc,#152] ; [0x1001ec8] = 0x2001c - 0x01001e2e: 6800 .h LDR r0,[r0,#0] - 0x01001e30: 30ff .0 ADDS r0,r0,#0xff - 0x01001e32: 30b7 .0 ADDS r0,r0,#0xb7 - 0x01001e34: 5481 .T STRB r1,[r0,r2] - 0x01001e36: 4824 $H LDR r0,[pc,#144] ; [0x1001ec8] = 0x2001c - 0x01001e38: 6800 .h LDR r0,[r0,#0] - 0x01001e3a: 30ff .0 ADDS r0,r0,#0xff - 0x01001e3c: 30ff .0 ADDS r0,r0,#0xff - 0x01001e3e: 3002 .0 ADDS r0,#2 - 0x01001e40: 8942 B. LDRH r2,[r0,#0xa] - 0x01001e42: 4821 !H LDR r0,[pc,#132] ; [0x1001ec8] = 0x2001c - 0x01001e44: 6800 .h LDR r0,[r0,#0] - 0x01001e46: 30ff .0 ADDS r0,r0,#0xff - 0x01001e48: 30b7 .0 ADDS r0,r0,#0xb7 - 0x01001e4a: 1811 .. ADDS r1,r2,r0 - 0x01001e4c: a021 !. ADR r0,{pc}+0x88 ; 0x1001ed4 - 0x01001e4e: f002fb3f ..?. BL rt_kprintf ; 0x10044d0 - 0x01001e52: 481d .H LDR r0,[pc,#116] ; [0x1001ec8] = 0x2001c - 0x01001e54: 6800 .h LDR r0,[r0,#0] - 0x01001e56: 30ff .0 ADDS r0,r0,#0xff - 0x01001e58: 30ff .0 ADDS r0,r0,#0xff - 0x01001e5a: 3002 .0 ADDS r0,#2 - 0x01001e5c: 8945 E. LDRH r5,[r0,#0xa] - 0x01001e5e: e004 .. B 0x1001e6a ; finsh_thread_entry + 926 - 0x01001e60: e01c .. B 0x1001e9c ; finsh_thread_entry + 976 - 0x01001e62: a01a .. ADR r0,{pc}+0x6a ; 0x1001ecc - 0x01001e64: f002fb34 ..4. BL rt_kprintf ; 0x10044d0 - 0x01001e68: 1c6d m. ADDS r5,r5,#1 - 0x01001e6a: 4817 .H LDR r0,[pc,#92] ; [0x1001ec8] = 0x2001c - 0x01001e6c: 6800 .h LDR r0,[r0,#0] - 0x01001e6e: 30ff .0 ADDS r0,r0,#0xff - 0x01001e70: 30ff .0 ADDS r0,r0,#0xff - 0x01001e72: 3002 .0 ADDS r0,#2 - 0x01001e74: 8900 .. LDRH r0,[r0,#8] - 0x01001e76: 42a8 .B CMP r0,r5 - 0x01001e78: daf3 .. BGE 0x1001e62 ; finsh_thread_entry + 918 - 0x01001e7a: e00e .. B 0x1001e9a ; finsh_thread_entry + 974 - 0x01001e7c: a017 .. ADR r0,{pc}+0x60 ; 0x1001edc - 0x01001e7e: f002fb27 ..'. BL rt_kprintf ; 0x10044d0 - 0x01001e82: 2100 .! MOVS r1,#0 - 0x01001e84: 4810 .H LDR r0,[pc,#64] ; [0x1001ec8] = 0x2001c - 0x01001e86: 6800 .h LDR r0,[r0,#0] - 0x01001e88: 30ff .0 ADDS r0,r0,#0xff - 0x01001e8a: 30ff .0 ADDS r0,r0,#0xff - 0x01001e8c: 3002 .0 ADDS r0,#2 - 0x01001e8e: 8902 .. LDRH r2,[r0,#8] - 0x01001e90: 480d .H LDR r0,[pc,#52] ; [0x1001ec8] = 0x2001c - 0x01001e92: 6800 .h LDR r0,[r0,#0] - 0x01001e94: 30ff .0 ADDS r0,r0,#0xff - 0x01001e96: 30b7 .0 ADDS r0,r0,#0xb7 - 0x01001e98: 5481 .T STRB r1,[r0,r2] - 0x01001e9a: e109 .. B 0x10020b0 ; finsh_thread_entry + 1508 - 0x01001e9c: 2c0d ., CMP r4,#0xd - 0x01001e9e: d001 .. BEQ 0x1001ea4 ; finsh_thread_entry + 984 - 0x01001ea0: 2c0a ., CMP r4,#0xa - 0x01001ea2: d143 C. BNE 0x1001f2c ; finsh_thread_entry + 1120 - 0x01001ea4: 4808 .H LDR r0,[pc,#32] ; [0x1001ec8] = 0x2001c - 0x01001ea6: 6800 .h LDR r0,[r0,#0] - 0x01001ea8: f004ff28 ..(. BL shell_push_history ; 0x1006cfc - 0x01001eac: 4806 .H LDR r0,[pc,#24] ; [0x1001ec8] = 0x2001c - 0x01001eae: 6800 .h LDR r0,[r0,#0] - 0x01001eb0: 3020 0 ADDS r0,r0,#0x20 - 0x01001eb2: 7840 @x LDRB r0,[r0,#1] - 0x01001eb4: 07c0 .. LSLS r0,r0,#31 - 0x01001eb6: 0fc0 .. LSRS r0,r0,#31 - 0x01001eb8: 2800 .( CMP r0,#0 - 0x01001eba: d002 .. BEQ 0x1001ec2 ; finsh_thread_entry + 1014 - 0x01001ebc: a008 .. ADR r0,{pc}+0x24 ; 0x1001ee0 - 0x01001ebe: f002fb07 .... BL rt_kprintf ; 0x10044d0 - 0x01001ec2: 4801 .H LDR r0,[pc,#4] ; [0x1001ec8] = 0x2001c - 0x01001ec4: 6800 .h LDR r0,[r0,#0] - 0x01001ec6: e00d .. B 0x1001ee4 ; finsh_thread_entry + 1048 - $d - 0x01001ec8: 0002001c .... DCD 131100 - 0x01001ecc: 00000008 .... DCD 8 - 0x01001ed0: 00006325 %c.. DCD 25381 - 0x01001ed4: 20732508 .%s DCD 544417032 - 0x01001ed8: 00000820 ... DCD 2080 - 0x01001edc: 00082008 . .. DCD 532488 - 0x01001ee0: 0000000a .... DCD 10 - $t - 0x01001ee4: 30ff .0 ADDS r0,r0,#0xff - 0x01001ee6: 30ff .0 ADDS r0,r0,#0xff - 0x01001ee8: 3002 .0 ADDS r0,#2 - 0x01001eea: 8901 .. LDRH r1,[r0,#8] - 0x01001eec: 4871 qH LDR r0,[pc,#452] ; [0x10020b4] = 0x2001c - 0x01001eee: 6800 .h LDR r0,[r0,#0] - 0x01001ef0: 30ff .0 ADDS r0,r0,#0xff - 0x01001ef2: 30b7 .0 ADDS r0,r0,#0xb7 - 0x01001ef4: f001f8f2 .... BL msh_exec ; 0x10030dc - 0x01001ef8: f7fffc62 ..b. BL finsh_get_prompt ; 0x10017c0 - 0x01001efc: 4605 .F MOV r5,r0 - 0x01001efe: f002fae7 .... BL rt_kprintf ; 0x10044d0 - 0x01001f02: 2151 Q! MOVS r1,#0x51 - 0x01001f04: 486b kH LDR r0,[pc,#428] ; [0x10020b4] = 0x2001c - 0x01001f06: 6800 .h LDR r0,[r0,#0] - 0x01001f08: 30ff .0 ADDS r0,r0,#0xff - 0x01001f0a: 30b7 .0 ADDS r0,r0,#0xb7 - 0x01001f0c: f7fefc73 ..s. BL __aeabi_memclr ; 0x10007f6 - 0x01001f10: 2100 .! MOVS r1,#0 - 0x01001f12: 4868 hH LDR r0,[pc,#416] ; [0x10020b4] = 0x2001c - 0x01001f14: 6800 .h LDR r0,[r0,#0] - 0x01001f16: 30ff .0 ADDS r0,r0,#0xff - 0x01001f18: 30ff .0 ADDS r0,r0,#0xff - 0x01001f1a: 3002 .0 ADDS r0,#2 - 0x01001f1c: 8101 .. STRH r1,[r0,#8] - 0x01001f1e: 4865 eH LDR r0,[pc,#404] ; [0x10020b4] = 0x2001c - 0x01001f20: 6800 .h LDR r0,[r0,#0] - 0x01001f22: 30ff .0 ADDS r0,r0,#0xff - 0x01001f24: 30ff .0 ADDS r0,r0,#0xff - 0x01001f26: 3002 .0 ADDS r0,#2 - 0x01001f28: 8141 A. STRH r1,[r0,#0xa] - 0x01001f2a: e0c1 .. B 0x10020b0 ; finsh_thread_entry + 1508 - 0x01001f2c: 4861 aH LDR r0,[pc,#388] ; [0x10020b4] = 0x2001c - 0x01001f2e: 6800 .h LDR r0,[r0,#0] - 0x01001f30: 30ff .0 ADDS r0,r0,#0xff - 0x01001f32: 30ff .0 ADDS r0,r0,#0xff - 0x01001f34: 3002 .0 ADDS r0,#2 - 0x01001f36: 8900 .. LDRH r0,[r0,#8] - 0x01001f38: 2850 P( CMP r0,#0x50 - 0x01001f3a: db06 .. BLT 0x1001f4a ; finsh_thread_entry + 1150 - 0x01001f3c: 2100 .! MOVS r1,#0 - 0x01001f3e: 485d ]H LDR r0,[pc,#372] ; [0x10020b4] = 0x2001c - 0x01001f40: 6800 .h LDR r0,[r0,#0] - 0x01001f42: 30ff .0 ADDS r0,r0,#0xff - 0x01001f44: 30ff .0 ADDS r0,r0,#0xff - 0x01001f46: 3002 .0 ADDS r0,#2 - 0x01001f48: 8101 .. STRH r1,[r0,#8] - 0x01001f4a: 485a ZH LDR r0,[pc,#360] ; [0x10020b4] = 0x2001c - 0x01001f4c: 6800 .h LDR r0,[r0,#0] - 0x01001f4e: 30ff .0 ADDS r0,r0,#0xff - 0x01001f50: 30ff .0 ADDS r0,r0,#0xff - 0x01001f52: 3002 .0 ADDS r0,#2 - 0x01001f54: 8941 A. LDRH r1,[r0,#0xa] - 0x01001f56: 4857 WH LDR r0,[pc,#348] ; [0x10020b4] = 0x2001c - 0x01001f58: 6800 .h LDR r0,[r0,#0] - 0x01001f5a: 30ff .0 ADDS r0,r0,#0xff - 0x01001f5c: 30ff .0 ADDS r0,r0,#0xff - 0x01001f5e: 3002 .0 ADDS r0,#2 - 0x01001f60: 8900 .. LDRH r0,[r0,#8] - 0x01001f62: 4281 .B CMP r1,r0 - 0x01001f64: da5a Z. BGE 0x100201c ; finsh_thread_entry + 1360 - 0x01001f66: 4b53 SK LDR r3,[pc,#332] ; [0x10020b4] = 0x2001c - 0x01001f68: 681b .h LDR r3,[r3,#0] - 0x01001f6a: 33ff .3 ADDS r3,r3,#0xff - 0x01001f6c: 33ff .3 ADDS r3,r3,#0xff - 0x01001f6e: 3302 .3 ADDS r3,#2 - 0x01001f70: 891e .. LDRH r6,[r3,#8] - 0x01001f72: 4b50 PK LDR r3,[pc,#320] ; [0x10020b4] = 0x2001c - 0x01001f74: 681b .h LDR r3,[r3,#0] - 0x01001f76: 33ff .3 ADDS r3,r3,#0xff - 0x01001f78: 33ff .3 ADDS r3,r3,#0xff - 0x01001f7a: 3302 .3 ADDS r3,#2 - 0x01001f7c: 895b [. LDRH r3,[r3,#0xa] - 0x01001f7e: 1af2 .. SUBS r2,r6,r3 - 0x01001f80: 4b4c LK LDR r3,[pc,#304] ; [0x10020b4] = 0x2001c - 0x01001f82: 681b .h LDR r3,[r3,#0] - 0x01001f84: 33ff .3 ADDS r3,r3,#0xff - 0x01001f86: 33ff .3 ADDS r3,r3,#0xff - 0x01001f88: 3302 .3 ADDS r3,#2 - 0x01001f8a: 895e ^. LDRH r6,[r3,#0xa] - 0x01001f8c: 4b49 IK LDR r3,[pc,#292] ; [0x10020b4] = 0x2001c - 0x01001f8e: 681b .h LDR r3,[r3,#0] - 0x01001f90: 33ff .3 ADDS r3,r3,#0xff - 0x01001f92: 33b7 .3 ADDS r3,r3,#0xb7 - 0x01001f94: 18f1 .. ADDS r1,r6,r3 - 0x01001f96: 4b47 GK LDR r3,[pc,#284] ; [0x10020b4] = 0x2001c - 0x01001f98: 681b .h LDR r3,[r3,#0] - 0x01001f9a: 33ff .3 ADDS r3,r3,#0xff - 0x01001f9c: 33ff .3 ADDS r3,r3,#0xff - 0x01001f9e: 3302 .3 ADDS r3,#2 - 0x01001fa0: 895b [. LDRH r3,[r3,#0xa] - 0x01001fa2: 1c5b [. ADDS r3,r3,#1 - 0x01001fa4: 4e43 CN LDR r6,[pc,#268] ; [0x10020b4] = 0x2001c - 0x01001fa6: 6836 6h LDR r6,[r6,#0] - 0x01001fa8: 36ff .6 ADDS r6,r6,#0xff - 0x01001faa: 36b7 .6 ADDS r6,r6,#0xb7 - 0x01001fac: 1998 .. ADDS r0,r3,r6 - 0x01001fae: f002fd67 ..g. BL rt_memmove ; 0x1004a80 - 0x01001fb2: 4840 @H LDR r0,[pc,#256] ; [0x10020b4] = 0x2001c - 0x01001fb4: 6800 .h LDR r0,[r0,#0] - 0x01001fb6: 30ff .0 ADDS r0,r0,#0xff - 0x01001fb8: 30ff .0 ADDS r0,r0,#0xff - 0x01001fba: 3002 .0 ADDS r0,#2 - 0x01001fbc: 8942 B. LDRH r2,[r0,#0xa] - 0x01001fbe: 483d =H LDR r0,[pc,#244] ; [0x10020b4] = 0x2001c - 0x01001fc0: 6800 .h LDR r0,[r0,#0] - 0x01001fc2: 30ff .0 ADDS r0,r0,#0xff - 0x01001fc4: 30b7 .0 ADDS r0,r0,#0xb7 - 0x01001fc6: 5484 .T STRB r4,[r0,r2] - 0x01001fc8: 483a :H LDR r0,[pc,#232] ; [0x10020b4] = 0x2001c - 0x01001fca: 6800 .h LDR r0,[r0,#0] - 0x01001fcc: 3020 0 ADDS r0,r0,#0x20 - 0x01001fce: 7840 @x LDRB r0,[r0,#1] - 0x01001fd0: 07c0 .. LSLS r0,r0,#31 - 0x01001fd2: 0fc0 .. LSRS r0,r0,#31 - 0x01001fd4: 2800 .( CMP r0,#0 - 0x01001fd6: d00d .. BEQ 0x1001ff4 ; finsh_thread_entry + 1320 - 0x01001fd8: 4836 6H LDR r0,[pc,#216] ; [0x10020b4] = 0x2001c - 0x01001fda: 6800 .h LDR r0,[r0,#0] - 0x01001fdc: 30ff .0 ADDS r0,r0,#0xff - 0x01001fde: 30ff .0 ADDS r0,r0,#0xff - 0x01001fe0: 3002 .0 ADDS r0,#2 - 0x01001fe2: 8942 B. LDRH r2,[r0,#0xa] - 0x01001fe4: 4833 3H LDR r0,[pc,#204] ; [0x10020b4] = 0x2001c - 0x01001fe6: 6800 .h LDR r0,[r0,#0] - 0x01001fe8: 30ff .0 ADDS r0,r0,#0xff - 0x01001fea: 30b7 .0 ADDS r0,r0,#0xb7 - 0x01001fec: 1811 .. ADDS r1,r2,r0 - 0x01001fee: a032 2. ADR r0,{pc}+0xca ; 0x10020b8 - 0x01001ff0: f002fa6e ..n. BL rt_kprintf ; 0x10044d0 - 0x01001ff4: 482f /H LDR r0,[pc,#188] ; [0x10020b4] = 0x2001c - 0x01001ff6: 6800 .h LDR r0,[r0,#0] - 0x01001ff8: 30ff .0 ADDS r0,r0,#0xff - 0x01001ffa: 30ff .0 ADDS r0,r0,#0xff - 0x01001ffc: 3002 .0 ADDS r0,#2 - 0x01001ffe: 8945 E. LDRH r5,[r0,#0xa] - 0x01002000: e003 .. B 0x100200a ; finsh_thread_entry + 1342 - 0x01002002: a02e .. ADR r0,{pc}+0xba ; 0x10020bc - 0x01002004: f002fa64 ..d. BL rt_kprintf ; 0x10044d0 - 0x01002008: 1c6d m. ADDS r5,r5,#1 - 0x0100200a: 482a *H LDR r0,[pc,#168] ; [0x10020b4] = 0x2001c - 0x0100200c: 6800 .h LDR r0,[r0,#0] - 0x0100200e: 30ff .0 ADDS r0,r0,#0xff - 0x01002010: 30ff .0 ADDS r0,r0,#0xff - 0x01002012: 3002 .0 ADDS r0,#2 - 0x01002014: 8900 .. LDRH r0,[r0,#8] - 0x01002016: 42a8 .B CMP r0,r5 - 0x01002018: dcf3 .. BGT 0x1002002 ; finsh_thread_entry + 1334 - 0x0100201a: e016 .. B 0x100204a ; finsh_thread_entry + 1406 - 0x0100201c: 4825 %H LDR r0,[pc,#148] ; [0x10020b4] = 0x2001c - 0x0100201e: 6800 .h LDR r0,[r0,#0] - 0x01002020: 30ff .0 ADDS r0,r0,#0xff - 0x01002022: 30ff .0 ADDS r0,r0,#0xff - 0x01002024: 3002 .0 ADDS r0,#2 - 0x01002026: 8902 .. LDRH r2,[r0,#8] - 0x01002028: 4822 "H LDR r0,[pc,#136] ; [0x10020b4] = 0x2001c - 0x0100202a: 6800 .h LDR r0,[r0,#0] - 0x0100202c: 30ff .0 ADDS r0,r0,#0xff - 0x0100202e: 30b7 .0 ADDS r0,r0,#0xb7 - 0x01002030: 5484 .T STRB r4,[r0,r2] - 0x01002032: 4820 H LDR r0,[pc,#128] ; [0x10020b4] = 0x2001c - 0x01002034: 6800 .h LDR r0,[r0,#0] - 0x01002036: 3020 0 ADDS r0,r0,#0x20 - 0x01002038: 7840 @x LDRB r0,[r0,#1] - 0x0100203a: 07c0 .. LSLS r0,r0,#31 - 0x0100203c: 0fc0 .. LSRS r0,r0,#31 - 0x0100203e: 2800 .( CMP r0,#0 - 0x01002040: d003 .. BEQ 0x100204a ; finsh_thread_entry + 1406 - 0x01002042: 4621 !F MOV r1,r4 - 0x01002044: a01e .. ADR r0,{pc}+0x7c ; 0x10020c0 - 0x01002046: f002fa43 ..C. BL rt_kprintf ; 0x10044d0 - 0x0100204a: 2400 .$ MOVS r4,#0 - 0x0100204c: 4819 .H LDR r0,[pc,#100] ; [0x10020b4] = 0x2001c - 0x0100204e: 6800 .h LDR r0,[r0,#0] - 0x01002050: 30ff .0 ADDS r0,r0,#0xff - 0x01002052: 30ff .0 ADDS r0,r0,#0xff - 0x01002054: 3002 .0 ADDS r0,#2 - 0x01002056: 8900 .. LDRH r0,[r0,#8] - 0x01002058: 1c40 @. ADDS r0,r0,#1 - 0x0100205a: b281 .. UXTH r1,r0 - 0x0100205c: 4815 .H LDR r0,[pc,#84] ; [0x10020b4] = 0x2001c - 0x0100205e: 6800 .h LDR r0,[r0,#0] - 0x01002060: 30ff .0 ADDS r0,r0,#0xff - 0x01002062: 30ff .0 ADDS r0,r0,#0xff - 0x01002064: 3002 .0 ADDS r0,#2 - 0x01002066: 8101 .. STRH r1,[r0,#8] - 0x01002068: 4812 .H LDR r0,[pc,#72] ; [0x10020b4] = 0x2001c - 0x0100206a: 6800 .h LDR r0,[r0,#0] - 0x0100206c: 30ff .0 ADDS r0,r0,#0xff - 0x0100206e: 30ff .0 ADDS r0,r0,#0xff - 0x01002070: 3002 .0 ADDS r0,#2 - 0x01002072: 8940 @. LDRH r0,[r0,#0xa] - 0x01002074: 1c40 @. ADDS r0,r0,#1 - 0x01002076: b281 .. UXTH r1,r0 - 0x01002078: 480e .H LDR r0,[pc,#56] ; [0x10020b4] = 0x2001c - 0x0100207a: 6800 .h LDR r0,[r0,#0] - 0x0100207c: 30ff .0 ADDS r0,r0,#0xff - 0x0100207e: 30ff .0 ADDS r0,r0,#0xff - 0x01002080: 3002 .0 ADDS r0,#2 - 0x01002082: 8141 A. STRH r1,[r0,#0xa] - 0x01002084: 480b .H LDR r0,[pc,#44] ; [0x10020b4] = 0x2001c - 0x01002086: 6800 .h LDR r0,[r0,#0] - 0x01002088: 30ff .0 ADDS r0,r0,#0xff - 0x0100208a: 30ff .0 ADDS r0,r0,#0xff - 0x0100208c: 3002 .0 ADDS r0,#2 - 0x0100208e: 8900 .. LDRH r0,[r0,#8] - 0x01002090: 2850 P( CMP r0,#0x50 - 0x01002092: db0c .. BLT 0x10020ae ; finsh_thread_entry + 1506 - 0x01002094: 2100 .! MOVS r1,#0 - 0x01002096: 4807 .H LDR r0,[pc,#28] ; [0x10020b4] = 0x2001c - 0x01002098: 6800 .h LDR r0,[r0,#0] - 0x0100209a: 30ff .0 ADDS r0,r0,#0xff - 0x0100209c: 30ff .0 ADDS r0,r0,#0xff - 0x0100209e: 3002 .0 ADDS r0,#2 - 0x010020a0: 8101 .. STRH r1,[r0,#8] - 0x010020a2: 4804 .H LDR r0,[pc,#16] ; [0x10020b4] = 0x2001c - 0x010020a4: 6800 .h LDR r0,[r0,#0] - 0x010020a6: 30ff .0 ADDS r0,r0,#0xff - 0x010020a8: 30ff .0 ADDS r0,r0,#0xff - 0x010020aa: 3002 .0 ADDS r0,#2 - 0x010020ac: 8141 A. STRH r1,[r0,#0xa] - 0x010020ae: bf00 .. NOP - 0x010020b0: e52e .. B 0x1001b10 ; finsh_thread_entry + 68 - $d - 0x010020b2: 0000 .. DCW 0 - 0x010020b4: 0002001c .... DCD 131100 - 0x010020b8: 00007325 %s.. DCD 29477 - 0x010020bc: 00000008 .... DCD 8 - 0x010020c0: 00006325 %c.. DCD 25381 - $t - i.hello - hello - 0x010020c4: b510 .. PUSH {r4,lr} - 0x010020c6: a002 .. ADR r0,{pc}+0xa ; 0x10020d0 - 0x010020c8: f002fa02 .... BL rt_kprintf ; 0x10044d0 - 0x010020cc: 2000 . MOVS r0,#0 - 0x010020ce: bd10 .. POP {r4,pc} - $d - 0x010020d0: 6c6c6548 Hell DCD 1819043144 - 0x010020d4: 5452206f o RT DCD 1414668399 - 0x010020d8: 7268542d -Thr DCD 1919439917 - 0x010020dc: 21646165 ead! DCD 560226661 - 0x010020e0: 0000000a .... DCD 10 - $t - i.list - list - 0x010020e4: b510 .. PUSH {r4,lr} - 0x010020e6: a00d .. ADR r0,{pc}+0x36 ; 0x100211c - 0x010020e8: f002f9f2 .... BL rt_kprintf ; 0x10044d0 - 0x010020ec: 4810 .H LDR r0,[pc,#64] ; [0x1002130] = 0x20014 - 0x010020ee: 6804 .h LDR r4,[r0,#0] - 0x010020f0: e00e .. B 0x1002110 ; list + 44 - 0x010020f2: 2202 ." MOVS r2,#2 - 0x010020f4: a10f .. ADR r1,{pc}+0x40 ; 0x1002134 - 0x010020f6: 6820 h LDR r0,[r4,#0] - 0x010020f8: f7fefac4 .... BL strncmp ; 0x1000684 - 0x010020fc: 2800 .( CMP r0,#0 - 0x010020fe: d100 .. BNE 0x1002102 ; list + 30 - 0x01002100: e005 .. B 0x100210e ; list + 42 - 0x01002102: a00d .. ADR r0,{pc}+0x36 ; 0x1002138 - 0x01002104: 6862 bh LDR r2,[r4,#4] - 0x01002106: 6821 !h LDR r1,[r4,#0] - 0x01002108: f002f9e2 .... BL rt_kprintf ; 0x10044d0 - 0x0100210c: bf00 .. NOP - 0x0100210e: 340c .4 ADDS r4,r4,#0xc - 0x01002110: 480d .H LDR r0,[pc,#52] ; [0x1002148] = 0x20018 - 0x01002112: 6800 .h LDR r0,[r0,#0] - 0x01002114: 4284 .B CMP r4,r0 - 0x01002116: d3ec .. BCC 0x10020f2 ; list + 14 - 0x01002118: 2000 . MOVS r0,#0 - 0x0100211a: bd10 .. POP {r4,pc} - $d - 0x0100211c: 6f432d2d --Co DCD 1866673453 - 0x01002120: 6e616d6d mman DCD 1851878765 - 0x01002124: 4c207364 ds L DCD 1277195108 - 0x01002128: 3a747369 ist: DCD 980710249 - 0x0100212c: 0000000a .... DCD 10 - 0x01002130: 00020014 .... DCD 131092 - 0x01002134: 00005f5f __.. DCD 24415 - 0x01002138: 36312d25 %-16 DCD 909192485 - 0x0100213c: 2d2d2073 s -- DCD 757932147 - 0x01002140: 0a732520 %s. DCD 175318304 - 0x01002144: 00000000 .... DCD 0 - 0x01002148: 00020018 .... DCD 131096 - $t - i.list_device - list_device - 0x0100214c: b5f0 .. PUSH {r4-r7,lr} - 0x0100214e: b093 .. SUB sp,sp,#0x4c - 0x01002150: 2700 .' MOVS r7,#0 - 0x01002152: a028 (. ADR r0,{pc}+0xa2 ; 0x10021f4 - 0x01002154: 9003 .. STR r0,[sp,#0xc] - 0x01002156: 2308 .# MOVS r3,#8 - 0x01002158: aa05 .. ADD r2,sp,#0x14 - 0x0100215a: 2109 .! MOVS r1,#9 - 0x0100215c: a80d .. ADD r0,sp,#0x34 - 0x0100215e: f000f921 ..!. BL list_find_init ; 0x10023a4 - 0x01002162: 2008 . MOVS r0,#8 - 0x01002164: 9004 .. STR r0,[sp,#0x10] - 0x01002166: a025 %. ADR r0,{pc}+0x96 ; 0x10021fc - 0x01002168: 9a03 .. LDR r2,[sp,#0xc] - 0x0100216a: 9904 .. LDR r1,[sp,#0x10] - 0x0100216c: f002f9b0 .... BL rt_kprintf ; 0x10044d0 - 0x01002170: 9804 .. LDR r0,[sp,#0x10] - 0x01002172: f001f8bb .... BL object_split ; 0x10032ec - 0x01002176: a02b +. ADR r0,{pc}+0xae ; 0x1002224 - 0x01002178: f002f9aa .... BL rt_kprintf ; 0x10044d0 - 0x0100217c: bf00 .. NOP - 0x0100217e: a90d .. ADD r1,sp,#0x34 - 0x01002180: 4638 8F MOV r0,r7 - 0x01002182: f000f923 ..#. BL list_get_next ; 0x10023cc - 0x01002186: 4607 .F MOV r7,r0 - 0x01002188: 2600 .& MOVS r6,#0 - 0x0100218a: e02b +. B 0x10021e4 ; list_device + 152 - 0x0100218c: 00b0 .. LSLS r0,r6,#2 - 0x0100218e: a905 .. ADD r1,sp,#0x14 - 0x01002190: 5808 .X LDR r0,[r1,r0] - 0x01002192: 4605 .F MOV r5,r0 - 0x01002194: 3d0c .= SUBS r5,r5,#0xc - 0x01002196: f7fef993 .... BL rt_hw_interrupt_disable ; 0x10004c0 - 0x0100219a: 9012 .. STR r0,[sp,#0x48] - 0x0100219c: 7a28 (z LDRB r0,[r5,#8] - 0x0100219e: 2180 .! MOVS r1,#0x80 - 0x010021a0: 4388 .C BICS r0,r0,r1 - 0x010021a2: a908 .. ADD r1,sp,#0x20 - 0x010021a4: 7f09 .. LDRB r1,[r1,#0x1c] - 0x010021a6: 4288 .B CMP r0,r1 - 0x010021a8: d003 .. BEQ 0x10021b2 ; list_device + 102 - 0x010021aa: 9812 .. LDR r0,[sp,#0x48] - 0x010021ac: f7fef98c .... BL rt_hw_interrupt_enable ; 0x10004c8 - 0x010021b0: e017 .. B 0x10021e2 ; list_device + 150 - 0x010021b2: 9812 .. LDR r0,[sp,#0x48] - 0x010021b4: f7fef988 .... BL rt_hw_interrupt_enable ; 0x10004c8 - 0x010021b8: 462c ,F MOV r4,r5 - 0x010021ba: 7ea1 .~ LDRB r1,[r4,#0x1a] - 0x010021bc: 7d20 } LDRB r0,[r4,#0x14] - 0x010021be: 2818 .( CMP r0,#0x18 - 0x010021c0: dc04 .. BGT 0x10021cc ; list_device + 128 - 0x010021c2: 7d20 } LDRB r0,[r4,#0x14] - 0x010021c4: 0080 .. LSLS r0,r0,#2 - 0x010021c6: 4a20 J LDR r2,[pc,#128] ; [0x1002248] = 0x1007520 - 0x010021c8: 5810 .X LDR r0,[r2,r0] - 0x010021ca: e001 .. B 0x10021d0 ; list_device + 132 - 0x010021cc: 481e .H LDR r0,[pc,#120] ; [0x1002248] = 0x1007520 - 0x010021ce: 6e00 .n LDR r0,[r0,#0x60] - 0x010021d0: 4623 #F MOV r3,r4 - 0x010021d2: 2208 ." MOVS r2,#8 - 0x010021d4: 9101 .. STR r1,[sp,#4] - 0x010021d6: 9000 .. STR r0,[sp,#0] - 0x010021d8: a01c .. ADR r0,{pc}+0x74 ; 0x100224c - 0x010021da: 9904 .. LDR r1,[sp,#0x10] - 0x010021dc: f002f978 ..x. BL rt_kprintf ; 0x10044d0 - 0x010021e0: bf00 .. NOP - 0x010021e2: 1c76 v. ADDS r6,r6,#1 - 0x010021e4: 9811 .. LDR r0,[sp,#0x44] - 0x010021e6: 42b0 .B CMP r0,r6 - 0x010021e8: dcd0 .. BGT 0x100218c ; list_device + 64 - 0x010021ea: 2f00 ./ CMP r7,#0 - 0x010021ec: d1c7 .. BNE 0x100217e ; list_device + 50 - 0x010021ee: 2000 . MOVS r0,#0 - 0x010021f0: b013 .. ADD sp,sp,#0x4c - 0x010021f2: bdf0 .. POP {r4-r7,pc} - $d - 0x010021f4: 69766564 devi DCD 1769366884 - 0x010021f8: 00006563 ce.. DCD 25955 - 0x010021fc: 2e2a2d25 %-*. DCD 774516005 - 0x01002200: 20202073 s DCD 538976371 - 0x01002204: 20202020 DCD 538976288 - 0x01002208: 79742020 ty DCD 2037653536 - 0x0100220c: 20206570 pe DCD 538994032 - 0x01002210: 20202020 DCD 538976288 - 0x01002214: 72202020 r DCD 1914708000 - 0x01002218: 63206665 ef c DCD 1663067749 - 0x0100221c: 746e756f ount DCD 1953396079 - 0x01002220: 0000000a .... DCD 10 - 0x01002224: 2d2d2d20 --- DCD 757935392 - 0x01002228: 2d2d2d2d ---- DCD 757935405 - 0x0100222c: 2d2d2d2d ---- DCD 757935405 - 0x01002230: 2d2d2d2d ---- DCD 757935405 - 0x01002234: 2d2d2d2d ---- DCD 757935405 - 0x01002238: 2d2d202d - -- DCD 757932077 - 0x0100223c: 2d2d2d2d ---- DCD 757935405 - 0x01002240: 2d2d2d2d ---- DCD 757935405 - 0x01002244: 0000000a .... DCD 10 - 0x01002248: 01007520 u.. DCD 16807200 - 0x0100224c: 2e2a2d25 %-*. DCD 774516005 - 0x01002250: 2520732a *s % DCD 622883626 - 0x01002254: 7330322d -20s DCD 1932538413 - 0x01002258: 382d2520 %-8 DCD 942482720 - 0x0100225c: 00000a64 d... DCD 2660 - $t - i.list_event - list_event - 0x01002260: b5f0 .. PUSH {r4-r7,lr} - 0x01002262: b093 .. SUB sp,sp,#0x4c - 0x01002264: 2700 .' MOVS r7,#0 - 0x01002266: a031 1. ADR r0,{pc}+0xc6 ; 0x100232c - 0x01002268: 9003 .. STR r0,[sp,#0xc] - 0x0100226a: 2308 .# MOVS r3,#8 - 0x0100226c: aa05 .. ADD r2,sp,#0x14 - 0x0100226e: 2104 .! MOVS r1,#4 - 0x01002270: a80d .. ADD r0,sp,#0x34 - 0x01002272: f000f897 .... BL list_find_init ; 0x10023a4 - 0x01002276: 2008 . MOVS r0,#8 - 0x01002278: 9004 .. STR r0,[sp,#0x10] - 0x0100227a: a02e .. ADR r0,{pc}+0xba ; 0x1002334 - 0x0100227c: 9a03 .. LDR r2,[sp,#0xc] - 0x0100227e: 9904 .. LDR r1,[sp,#0x10] - 0x01002280: f002f926 ..&. BL rt_kprintf ; 0x10044d0 - 0x01002284: 9804 .. LDR r0,[sp,#0x10] - 0x01002286: f001f831 ..1. BL object_split ; 0x10032ec - 0x0100228a: a033 3. ADR r0,{pc}+0xce ; 0x1002358 - 0x0100228c: f002f920 .. . BL rt_kprintf ; 0x10044d0 - 0x01002290: bf00 .. NOP - 0x01002292: a90d .. ADD r1,sp,#0x34 - 0x01002294: 4638 8F MOV r0,r7 - 0x01002296: f000f899 .... BL list_get_next ; 0x10023cc - 0x0100229a: 4607 .F MOV r7,r0 - 0x0100229c: 2500 .% MOVS r5,#0 - 0x0100229e: e03c <. B 0x100231a ; list_event + 186 - 0x010022a0: 00a8 .. LSLS r0,r5,#2 - 0x010022a2: a905 .. ADD r1,sp,#0x14 - 0x010022a4: 5808 .X LDR r0,[r1,r0] - 0x010022a6: 4606 .F MOV r6,r0 - 0x010022a8: 3e0c .> SUBS r6,r6,#0xc - 0x010022aa: f7fef909 .... BL rt_hw_interrupt_disable ; 0x10004c0 - 0x010022ae: 9012 .. STR r0,[sp,#0x48] - 0x010022b0: 7a30 0z LDRB r0,[r6,#8] - 0x010022b2: 2180 .! MOVS r1,#0x80 - 0x010022b4: 4388 .C BICS r0,r0,r1 - 0x010022b6: a908 .. ADD r1,sp,#0x20 - 0x010022b8: 7f09 .. LDRB r1,[r1,#0x1c] - 0x010022ba: 4288 .B CMP r0,r1 - 0x010022bc: d003 .. BEQ 0x10022c6 ; list_event + 102 - 0x010022be: 9812 .. LDR r0,[sp,#0x48] - 0x010022c0: f7fef902 .... BL rt_hw_interrupt_enable ; 0x10004c8 - 0x010022c4: e028 (. B 0x1002318 ; list_event + 184 - 0x010022c6: 9812 .. LDR r0,[sp,#0x48] - 0x010022c8: f7fef8fe .... BL rt_hw_interrupt_enable ; 0x10004c8 - 0x010022cc: 4634 4F MOV r4,r6 - 0x010022ce: 4620 F MOV r0,r4 - 0x010022d0: 3014 .0 ADDS r0,r0,#0x14 - 0x010022d2: f002f948 ..H. BL rt_list_isempty ; 0x1004566 - 0x010022d6: 2800 .( CMP r0,#0 - 0x010022d8: d115 .. BNE 0x1002306 ; list_event + 166 - 0x010022da: 4620 F MOV r0,r4 - 0x010022dc: 3014 .0 ADDS r0,r0,#0x14 - 0x010022de: f002f95a ..Z. BL rt_list_len ; 0x1004596 - 0x010022e2: 9002 .. STR r0,[sp,#8] - 0x010022e4: 69e1 .i LDR r1,[r4,#0x1c] - 0x010022e6: 4623 #F MOV r3,r4 - 0x010022e8: 2208 ." MOVS r2,#8 - 0x010022ea: 9100 .. STR r1,[sp,#0] - 0x010022ec: 9001 .. STR r0,[sp,#4] - 0x010022ee: a022 ". ADR r0,{pc}+0x8a ; 0x1002378 - 0x010022f0: 9904 .. LDR r1,[sp,#0x10] - 0x010022f2: f002f8ed .... BL rt_kprintf ; 0x10044d0 - 0x010022f6: 4620 F MOV r0,r4 - 0x010022f8: 3014 .0 ADDS r0,r0,#0x14 - 0x010022fa: f004fd6d ..m. BL show_wait_queue ; 0x1006dd8 - 0x010022fe: a015 .. ADR r0,{pc}+0x56 ; 0x1002354 - 0x01002300: f002f8e6 .... BL rt_kprintf ; 0x10044d0 - 0x01002304: e007 .. B 0x1002316 ; list_event + 182 - 0x01002306: 69e0 .i LDR r0,[r4,#0x1c] - 0x01002308: 4623 #F MOV r3,r4 - 0x0100230a: 2208 ." MOVS r2,#8 - 0x0100230c: 9000 .. STR r0,[sp,#0] - 0x0100230e: a020 . ADR r0,{pc}+0x82 ; 0x1002390 - 0x01002310: 9904 .. LDR r1,[sp,#0x10] - 0x01002312: f002f8dd .... BL rt_kprintf ; 0x10044d0 - 0x01002316: bf00 .. NOP - 0x01002318: 1c6d m. ADDS r5,r5,#1 - 0x0100231a: 9811 .. LDR r0,[sp,#0x44] - 0x0100231c: 42a8 .B CMP r0,r5 - 0x0100231e: dcbf .. BGT 0x10022a0 ; list_event + 64 - 0x01002320: 2f00 ./ CMP r7,#0 - 0x01002322: d1b6 .. BNE 0x1002292 ; list_event + 50 - 0x01002324: 2000 . MOVS r0,#0 - 0x01002326: b013 .. ADD sp,sp,#0x4c - 0x01002328: bdf0 .. POP {r4-r7,pc} - $d - 0x0100232a: 0000 .. DCW 0 - 0x0100232c: 6e657665 even DCD 1852143205 - 0x01002330: 00000074 t... DCD 116 - 0x01002334: 2e2a2d25 %-*. DCD 774516005 - 0x01002338: 20202073 s DCD 538976371 - 0x0100233c: 73202020 s DCD 1931485216 - 0x01002340: 20207465 et DCD 538997861 - 0x01002344: 75732020 su DCD 1970479136 - 0x01002348: 6e657073 spen DCD 1852141683 - 0x0100234c: 68742064 d th DCD 1752440932 - 0x01002350: 64616572 read DCD 1684104562 - 0x01002354: 0000000a .... DCD 10 - 0x01002358: 2d2d2020 -- DCD 757932064 - 0x0100235c: 2d2d2d2d ---- DCD 757935405 - 0x01002360: 2d2d2d2d ---- DCD 757935405 - 0x01002364: 2d2d2d20 --- DCD 757935392 - 0x01002368: 2d2d2d2d ---- DCD 757935405 - 0x0100236c: 2d2d2d2d ---- DCD 757935405 - 0x01002370: 0a2d2d2d ---. DCD 170732845 - 0x01002374: 00000000 .... DCD 0 - 0x01002378: 2e2a2d25 %-*. DCD 774516005 - 0x0100237c: 2020732a *s DCD 538997546 - 0x01002380: 30257830 0x%0 DCD 807761968 - 0x01002384: 25207838 8x % DCD 622884920 - 0x01002388: 3a643330 03d: DCD 979645232 - 0x0100238c: 00000000 .... DCD 0 - 0x01002390: 2e2a2d25 %-*. DCD 774516005 - 0x01002394: 2020732a *s DCD 538997546 - 0x01002398: 30257830 0x%0 DCD 807761968 - 0x0100239c: 30207838 8x 0 DCD 807434296 - 0x010023a0: 0000000a .... DCD 10 - $t - i.list_find_init - list_find_init - 0x010023a4: b5fe .. PUSH {r1-r7,lr} - 0x010023a6: 4604 .F MOV r4,r0 - 0x010023a8: 460d .F MOV r5,r1 - 0x010023aa: 4616 .F MOV r6,r2 - 0x010023ac: 461f .F MOV r7,r3 - 0x010023ae: 4628 (F MOV r0,r5 - 0x010023b0: f002fd02 .... BL rt_object_get_information ; 0x1004db8 - 0x010023b4: 9001 .. STR r0,[sp,#4] - 0x010023b6: 9801 .. LDR r0,[sp,#4] - 0x010023b8: 1d00 .. ADDS r0,r0,#4 - 0x010023ba: 9000 .. STR r0,[sp,#0] - 0x010023bc: 9800 .. LDR r0,[sp,#0] - 0x010023be: 6020 ` STR r0,[r4,#0] - 0x010023c0: 7225 %r STRB r5,[r4,#8] - 0x010023c2: 6066 f` STR r6,[r4,#4] - 0x010023c4: 60e7 .` STR r7,[r4,#0xc] - 0x010023c6: 2000 . MOVS r0,#0 - 0x010023c8: 6120 a STR r0,[r4,#0x10] - 0x010023ca: bdfe .. POP {r1-r7,pc} - i.list_get_next - list_get_next - 0x010023cc: b5f0 .. PUSH {r4-r7,lr} - 0x010023ce: b085 .. SUB sp,sp,#0x14 - 0x010023d0: 4607 .F MOV r7,r0 - 0x010023d2: 460c .F MOV r4,r1 - 0x010023d4: 2000 . MOVS r0,#0 - 0x010023d6: 9004 .. STR r0,[sp,#0x10] - 0x010023d8: 6120 a STR r0,[r4,#0x10] - 0x010023da: 68e0 .h LDR r0,[r4,#0xc] - 0x010023dc: 2800 .( CMP r0,#0 - 0x010023de: d002 .. BEQ 0x10023e6 ; list_get_next + 26 - 0x010023e0: 7a20 z LDRB r0,[r4,#8] - 0x010023e2: 2800 .( CMP r0,#0 - 0x010023e4: d102 .. BNE 0x10023ec ; list_get_next + 32 - 0x010023e6: 2000 . MOVS r0,#0 - 0x010023e8: b005 .. ADD sp,sp,#0x14 - 0x010023ea: bdf0 .. POP {r4-r7,pc} - 0x010023ec: 6820 h LDR r0,[r4,#0] - 0x010023ee: 9002 .. STR r0,[sp,#8] - 0x010023f0: 2f00 ./ CMP r7,#0 - 0x010023f2: d103 .. BNE 0x10023fc ; list_get_next + 48 - 0x010023f4: 9d02 .. LDR r5,[sp,#8] - 0x010023f6: 2001 . MOVS r0,#1 - 0x010023f8: 9004 .. STR r0,[sp,#0x10] - 0x010023fa: e000 .. B 0x10023fe ; list_get_next + 50 - 0x010023fc: 463d =F MOV r5,r7 - 0x010023fe: f7fef85f .._. BL rt_hw_interrupt_disable ; 0x10004c0 - 0x01002402: 9003 .. STR r0,[sp,#0xc] - 0x01002404: 9804 .. LDR r0,[sp,#0x10] - 0x01002406: 2800 .( CMP r0,#0 - 0x01002408: d10f .. BNE 0x100242a ; list_get_next + 94 - 0x0100240a: 4628 (F MOV r0,r5 - 0x0100240c: 380c .8 SUBS r0,r0,#0xc - 0x0100240e: 9000 .. STR r0,[sp,#0] - 0x01002410: 9800 .. LDR r0,[sp,#0] - 0x01002412: 7a00 .z LDRB r0,[r0,#8] - 0x01002414: 2180 .! MOVS r1,#0x80 - 0x01002416: 4388 .C BICS r0,r0,r1 - 0x01002418: 7a21 !z LDRB r1,[r4,#8] - 0x0100241a: 4288 .B CMP r0,r1 - 0x0100241c: d004 .. BEQ 0x1002428 ; list_get_next + 92 - 0x0100241e: 9803 .. LDR r0,[sp,#0xc] - 0x01002420: f7fef852 ..R. BL rt_hw_interrupt_enable ; 0x10004c8 - 0x01002424: 2000 . MOVS r0,#0 - 0x01002426: e7df .. B 0x10023e8 ; list_get_next + 28 - 0x01002428: bf00 .. NOP - 0x0100242a: 2600 .& MOVS r6,#0 - 0x0100242c: 6860 `h LDR r0,[r4,#4] - 0x0100242e: 9001 .. STR r0,[sp,#4] - 0x01002430: e00f .. B 0x1002452 ; list_get_next + 134 - 0x01002432: 682d -h LDR r5,[r5,#0] - 0x01002434: 9802 .. LDR r0,[sp,#8] - 0x01002436: 4285 .B CMP r5,r0 - 0x01002438: d101 .. BNE 0x100243e ; list_get_next + 114 - 0x0100243a: 2500 .% MOVS r5,#0 - 0x0100243c: e00a .. B 0x1002454 ; list_get_next + 136 - 0x0100243e: 1c76 v. ADDS r6,r6,#1 - 0x01002440: 9801 .. LDR r0,[sp,#4] - 0x01002442: 6005 .` STR r5,[r0,#0] - 0x01002444: 9801 .. LDR r0,[sp,#4] - 0x01002446: 1d00 .. ADDS r0,r0,#4 - 0x01002448: 9001 .. STR r0,[sp,#4] - 0x0100244a: 68e0 .h LDR r0,[r4,#0xc] - 0x0100244c: 42b0 .B CMP r0,r6 - 0x0100244e: d100 .. BNE 0x1002452 ; list_get_next + 134 - 0x01002450: e000 .. B 0x1002454 ; list_get_next + 136 - 0x01002452: e7ee .. B 0x1002432 ; list_get_next + 102 - 0x01002454: bf00 .. NOP - 0x01002456: 9803 .. LDR r0,[sp,#0xc] - 0x01002458: f7fef836 ..6. BL rt_hw_interrupt_enable ; 0x10004c8 - 0x0100245c: 6126 &a STR r6,[r4,#0x10] - 0x0100245e: 4628 (F MOV r0,r5 - 0x01002460: e7c2 .. B 0x10023e8 ; list_get_next + 28 - 0x01002462: 0000 .. MOVS r0,r0 - i.list_mailbox - list_mailbox - 0x01002464: b5f0 .. PUSH {r4-r7,lr} - 0x01002466: b095 .. SUB sp,sp,#0x54 - 0x01002468: 2700 .' MOVS r7,#0 - 0x0100246a: a036 6. ADR r0,{pc}+0xda ; 0x1002544 - 0x0100246c: 9005 .. STR r0,[sp,#0x14] - 0x0100246e: 2308 .# MOVS r3,#8 - 0x01002470: aa07 .. ADD r2,sp,#0x1c - 0x01002472: 2105 .! MOVS r1,#5 - 0x01002474: a80f .. ADD r0,sp,#0x3c - 0x01002476: f7ffff95 .... BL list_find_init ; 0x10023a4 - 0x0100247a: 2008 . MOVS r0,#8 - 0x0100247c: 9006 .. STR r0,[sp,#0x18] - 0x0100247e: a033 3. ADR r0,{pc}+0xce ; 0x100254c - 0x01002480: 9a05 .. LDR r2,[sp,#0x14] - 0x01002482: 9906 .. LDR r1,[sp,#0x18] - 0x01002484: f002f824 ..$. BL rt_kprintf ; 0x10044d0 - 0x01002488: 9806 .. LDR r0,[sp,#0x18] - 0x0100248a: f000ff2f ../. BL object_split ; 0x10032ec - 0x0100248e: a038 8. ADR r0,{pc}+0xe2 ; 0x1002570 - 0x01002490: f002f81e .... BL rt_kprintf ; 0x10044d0 - 0x01002494: bf00 .. NOP - 0x01002496: a90f .. ADD r1,sp,#0x3c - 0x01002498: 4638 8F MOV r0,r7 - 0x0100249a: f7ffff97 .... BL list_get_next ; 0x10023cc - 0x0100249e: 4607 .F MOV r7,r0 - 0x010024a0: 2500 .% MOVS r5,#0 - 0x010024a2: e046 F. B 0x1002532 ; list_mailbox + 206 - 0x010024a4: 00a8 .. LSLS r0,r5,#2 - 0x010024a6: a907 .. ADD r1,sp,#0x1c - 0x010024a8: 5808 .X LDR r0,[r1,r0] - 0x010024aa: 4606 .F MOV r6,r0 - 0x010024ac: 3e0c .> SUBS r6,r6,#0xc - 0x010024ae: f7fef807 .... BL rt_hw_interrupt_disable ; 0x10004c0 - 0x010024b2: 9014 .. STR r0,[sp,#0x50] - 0x010024b4: 7a30 0z LDRB r0,[r6,#8] - 0x010024b6: 2180 .! MOVS r1,#0x80 - 0x010024b8: 4388 .C BICS r0,r0,r1 - 0x010024ba: a910 .. ADD r1,sp,#0x40 - 0x010024bc: 7909 .y LDRB r1,[r1,#4] - 0x010024be: 4288 .B CMP r0,r1 - 0x010024c0: d003 .. BEQ 0x10024ca ; list_mailbox + 102 - 0x010024c2: 9814 .. LDR r0,[sp,#0x50] - 0x010024c4: f7fef800 .... BL rt_hw_interrupt_enable ; 0x10004c8 - 0x010024c8: e032 2. B 0x1002530 ; list_mailbox + 204 - 0x010024ca: 9814 .. LDR r0,[sp,#0x50] - 0x010024cc: f7fdfffc .... BL rt_hw_interrupt_enable ; 0x10004c8 - 0x010024d0: 4634 4F MOV r4,r6 - 0x010024d2: 4620 F MOV r0,r4 - 0x010024d4: 3014 .0 ADDS r0,r0,#0x14 - 0x010024d6: f002f846 ..F. BL rt_list_isempty ; 0x1004566 - 0x010024da: 2800 .( CMP r0,#0 - 0x010024dc: d117 .. BNE 0x100250e ; list_mailbox + 170 - 0x010024de: 4620 F MOV r0,r4 - 0x010024e0: 3014 .0 ADDS r0,r0,#0x14 - 0x010024e2: f002f858 ..X. BL rt_list_len ; 0x1004596 - 0x010024e6: 9004 .. STR r0,[sp,#0x10] - 0x010024e8: 8c21 !. LDRH r1,[r4,#0x20] - 0x010024ea: 8c62 b. LDRH r2,[r4,#0x22] - 0x010024ec: 4623 #F MOV r3,r4 - 0x010024ee: 9200 .. STR r2,[sp,#0] - 0x010024f0: 9101 .. STR r1,[sp,#4] - 0x010024f2: 9002 .. STR r0,[sp,#8] - 0x010024f4: 2208 ." MOVS r2,#8 - 0x010024f6: a025 %. ADR r0,{pc}+0x96 ; 0x100258c - 0x010024f8: 9906 .. LDR r1,[sp,#0x18] - 0x010024fa: f001ffe9 .... BL rt_kprintf ; 0x10044d0 - 0x010024fe: 4620 F MOV r0,r4 - 0x01002500: 3014 .0 ADDS r0,r0,#0x14 - 0x01002502: f004fc69 ..i. BL show_wait_queue ; 0x1006dd8 - 0x01002506: a027 '. ADR r0,{pc}+0x9e ; 0x10025a4 - 0x01002508: f001ffe2 .... BL rt_kprintf ; 0x10044d0 - 0x0100250c: e00f .. B 0x100252e ; list_mailbox + 202 - 0x0100250e: 4620 F MOV r0,r4 - 0x01002510: 3014 .0 ADDS r0,r0,#0x14 - 0x01002512: f002f840 ..@. BL rt_list_len ; 0x1004596 - 0x01002516: 9004 .. STR r0,[sp,#0x10] - 0x01002518: 8c21 !. LDRH r1,[r4,#0x20] - 0x0100251a: 8c62 b. LDRH r2,[r4,#0x22] - 0x0100251c: 4623 #F MOV r3,r4 - 0x0100251e: 9200 .. STR r2,[sp,#0] - 0x01002520: 9101 .. STR r1,[sp,#4] - 0x01002522: 9002 .. STR r0,[sp,#8] - 0x01002524: 2208 ." MOVS r2,#8 - 0x01002526: a020 . ADR r0,{pc}+0x82 ; 0x10025a8 - 0x01002528: 9906 .. LDR r1,[sp,#0x18] - 0x0100252a: f001ffd1 .... BL rt_kprintf ; 0x10044d0 - 0x0100252e: bf00 .. NOP - 0x01002530: 1c6d m. ADDS r5,r5,#1 - 0x01002532: 9813 .. LDR r0,[sp,#0x4c] - 0x01002534: 42a8 .B CMP r0,r5 - 0x01002536: dcb5 .. BGT 0x10024a4 ; list_mailbox + 64 - 0x01002538: 2f00 ./ CMP r7,#0 - 0x0100253a: d1ac .. BNE 0x1002496 ; list_mailbox + 50 - 0x0100253c: 2000 . MOVS r0,#0 - 0x0100253e: b015 .. ADD sp,sp,#0x54 - 0x01002540: bdf0 .. POP {r4-r7,pc} - $d - 0x01002542: 0000 .. DCW 0 - 0x01002544: 6c69616d mail DCD 1818845549 - 0x01002548: 00786f62 box. DCD 7892834 - 0x0100254c: 2e2a2d25 %-*. DCD 774516005 - 0x01002550: 6e652073 s en DCD 1852121203 - 0x01002554: 20797274 try DCD 544830068 - 0x01002558: 657a6973 size DCD 1702521203 - 0x0100255c: 73757320 sus DCD 1937077024 - 0x01002560: 646e6570 pend DCD 1684956528 - 0x01002564: 72687420 thr DCD 1919448096 - 0x01002568: 0a646165 ead. DCD 174350693 - 0x0100256c: 00000000 .... DCD 0 - 0x01002570: 2d2d2d20 --- DCD 757935392 - 0x01002574: 2d20202d - - DCD 757080109 - 0x01002578: 202d2d2d --- DCD 539831597 - 0x0100257c: 2d2d2d2d ---- DCD 757935405 - 0x01002580: 2d2d2d2d ---- DCD 757935405 - 0x01002584: 2d2d2d2d ---- DCD 757935405 - 0x01002588: 000a2d2d --.. DCD 666925 - 0x0100258c: 2e2a2d25 %-*. DCD 774516005 - 0x01002590: 2520732a *s % DCD 622883626 - 0x01002594: 20643430 04d DCD 543437872 - 0x01002598: 34302520 %04 DCD 875570464 - 0x0100259c: 64252064 d %d DCD 1680154724 - 0x010025a0: 0000003a :... DCD 58 - 0x010025a4: 0000000a .... DCD 10 - 0x010025a8: 2e2a2d25 %-*. DCD 774516005 - 0x010025ac: 2520732a *s % DCD 622883626 - 0x010025b0: 20643430 04d DCD 543437872 - 0x010025b4: 34302520 %04 DCD 875570464 - 0x010025b8: 64252064 d %d DCD 1680154724 - 0x010025bc: 0000000a .... DCD 10 - $t - i.list_mem - list_mem - 0x010025c0: b510 .. PUSH {r4,lr} - 0x010025c2: 4808 .H LDR r0,[pc,#32] ; [0x10025e4] = 0x20148 - 0x010025c4: 6801 .h LDR r1,[r0,#0] - 0x010025c6: a008 .. ADR r0,{pc}+0x22 ; 0x10025e8 - 0x010025c8: f001ff82 .... BL rt_kprintf ; 0x10044d0 - 0x010025cc: 480b .H LDR r0,[pc,#44] ; [0x10025fc] = 0x2014c - 0x010025ce: 6801 .h LDR r1,[r0,#0] - 0x010025d0: a00b .. ADR r0,{pc}+0x30 ; 0x1002600 - 0x010025d2: f001ff7d ..}. BL rt_kprintf ; 0x10044d0 - 0x010025d6: 480f .H LDR r0,[pc,#60] ; [0x1002614] = 0x20150 - 0x010025d8: 6801 .h LDR r1,[r0,#0] - 0x010025da: a00f .. ADR r0,{pc}+0x3e ; 0x1002618 - 0x010025dc: f001ff78 ..x. BL rt_kprintf ; 0x10044d0 - 0x010025e0: bd10 .. POP {r4,pc} - $d - 0x010025e2: 0000 .. DCW 0 - 0x010025e4: 00020148 H... DCD 131400 - 0x010025e8: 61746f74 tota DCD 1635020660 - 0x010025ec: 656d206c l me DCD 1701650540 - 0x010025f0: 79726f6d mory DCD 2037542765 - 0x010025f4: 6425203a : %d DCD 1680154682 - 0x010025f8: 0000000a .... DCD 10 - 0x010025fc: 0002014c L... DCD 131404 - 0x01002600: 64657375 used DCD 1684370293 - 0x01002604: 6d656d20 mem DCD 1835363616 - 0x01002608: 2079726f ory DCD 544830063 - 0x0100260c: 6425203a : %d DCD 1680154682 - 0x01002610: 0000000a .... DCD 10 - 0x01002614: 00020150 P... DCD 131408 - 0x01002618: 6978616d maxi DCD 1769496941 - 0x0100261c: 206d756d mum DCD 544044397 - 0x01002620: 6f6c6c61 allo DCD 1869376609 - 0x01002624: 65746163 cate DCD 1702125923 - 0x01002628: 656d2064 d me DCD 1701650532 - 0x0100262c: 79726f6d mory DCD 2037542765 - 0x01002630: 6425203a : %d DCD 1680154682 - 0x01002634: 0000000a .... DCD 10 - $t - i.list_memheap - list_memheap - 0x01002638: b5f0 .. PUSH {r4-r7,lr} - 0x0100263a: b093 .. SUB sp,sp,#0x4c - 0x0100263c: 2700 .' MOVS r7,#0 - 0x0100263e: a025 %. ADR r0,{pc}+0x96 ; 0x10026d4 - 0x01002640: 9003 .. STR r0,[sp,#0xc] - 0x01002642: 2308 .# MOVS r3,#8 - 0x01002644: aa05 .. ADD r2,sp,#0x14 - 0x01002646: 2107 .! MOVS r1,#7 - 0x01002648: a80d .. ADD r0,sp,#0x34 - 0x0100264a: f7fffeab .... BL list_find_init ; 0x10023a4 - 0x0100264e: 2008 . MOVS r0,#8 - 0x01002650: 9004 .. STR r0,[sp,#0x10] - 0x01002652: a022 ". ADR r0,{pc}+0x8a ; 0x10026dc - 0x01002654: 9a03 .. LDR r2,[sp,#0xc] - 0x01002656: 9904 .. LDR r1,[sp,#0x10] - 0x01002658: f001ff3a ..:. BL rt_kprintf ; 0x10044d0 - 0x0100265c: 9804 .. LDR r0,[sp,#0x10] - 0x0100265e: f000fe45 ..E. BL object_split ; 0x10032ec - 0x01002662: a02a *. ADR r0,{pc}+0xaa ; 0x100270c - 0x01002664: f001ff34 ..4. BL rt_kprintf ; 0x10044d0 - 0x01002668: bf00 .. NOP - 0x0100266a: a90d .. ADD r1,sp,#0x34 - 0x0100266c: 4638 8F MOV r0,r7 - 0x0100266e: f7fffead .... BL list_get_next ; 0x10023cc - 0x01002672: 4607 .F MOV r7,r0 - 0x01002674: 2600 .& MOVS r6,#0 - 0x01002676: e024 $. B 0x10026c2 ; list_memheap + 138 - 0x01002678: 00b0 .. LSLS r0,r6,#2 - 0x0100267a: a905 .. ADD r1,sp,#0x14 - 0x0100267c: 5808 .X LDR r0,[r1,r0] - 0x0100267e: 4604 .F MOV r4,r0 - 0x01002680: 3c0c .< SUBS r4,r4,#0xc - 0x01002682: f7fdff1d .... BL rt_hw_interrupt_disable ; 0x10004c0 - 0x01002686: 9012 .. STR r0,[sp,#0x48] - 0x01002688: 7a20 z LDRB r0,[r4,#8] - 0x0100268a: 2180 .! MOVS r1,#0x80 - 0x0100268c: 4388 .C BICS r0,r0,r1 - 0x0100268e: a908 .. ADD r1,sp,#0x20 - 0x01002690: 7f09 .. LDRB r1,[r1,#0x1c] - 0x01002692: 4288 .B CMP r0,r1 - 0x01002694: d003 .. BEQ 0x100269e ; list_memheap + 102 - 0x01002696: 9812 .. LDR r0,[sp,#0x48] - 0x01002698: f7fdff16 .... BL rt_hw_interrupt_enable ; 0x10004c8 - 0x0100269c: e010 .. B 0x10026c0 ; list_memheap + 136 - 0x0100269e: 9812 .. LDR r0,[sp,#0x48] - 0x010026a0: f7fdff12 .... BL rt_hw_interrupt_enable ; 0x10004c8 - 0x010026a4: 4625 %F MOV r5,r4 - 0x010026a6: 6a2a *j LDR r2,[r5,#0x20] - 0x010026a8: 69a9 .i LDR r1,[r5,#0x18] - 0x010026aa: 69e8 .i LDR r0,[r5,#0x1c] - 0x010026ac: 462b +F MOV r3,r5 - 0x010026ae: 9201 .. STR r2,[sp,#4] - 0x010026b0: 9100 .. STR r1,[sp,#0] - 0x010026b2: 9002 .. STR r0,[sp,#8] - 0x010026b4: 2208 ." MOVS r2,#8 - 0x010026b6: a020 . ADR r0,{pc}+0x82 ; 0x1002738 - 0x010026b8: 9904 .. LDR r1,[sp,#0x10] - 0x010026ba: f001ff09 .... BL rt_kprintf ; 0x10044d0 - 0x010026be: bf00 .. NOP - 0x010026c0: 1c76 v. ADDS r6,r6,#1 - 0x010026c2: 9811 .. LDR r0,[sp,#0x44] - 0x010026c4: 42b0 .B CMP r0,r6 - 0x010026c6: dcd7 .. BGT 0x1002678 ; list_memheap + 64 - 0x010026c8: 2f00 ./ CMP r7,#0 - 0x010026ca: d1ce .. BNE 0x100266a ; list_memheap + 50 - 0x010026cc: 2000 . MOVS r0,#0 - 0x010026ce: b013 .. ADD sp,sp,#0x4c - 0x010026d0: bdf0 .. POP {r4-r7,pc} - $d - 0x010026d2: 0000 .. DCW 0 - 0x010026d4: 686d656d memh DCD 1751999853 - 0x010026d8: 00706165 eap. DCD 7364965 - 0x010026dc: 2e2a2d25 %-*. DCD 774516005 - 0x010026e0: 70202073 s p DCD 1881153651 - 0x010026e4: 206c6f6f ool DCD 543977327 - 0x010026e8: 657a6973 size DCD 1702521203 - 0x010026ec: 616d2020 ma DCD 1634541600 - 0x010026f0: 73752078 x us DCD 1937055864 - 0x010026f4: 73206465 ed s DCD 1931502693 - 0x010026f8: 20657a69 ize DCD 543521385 - 0x010026fc: 69617661 avai DCD 1767994977 - 0x01002700: 6c62616c labl DCD 1818386796 - 0x01002704: 69732065 e si DCD 1769152613 - 0x01002708: 000a657a ze.. DCD 681338 - 0x0100270c: 2d2d2d20 --- DCD 757935392 - 0x01002710: 2d2d2d2d ---- DCD 757935405 - 0x01002714: 202d2d2d --- DCD 539831597 - 0x01002718: 2d2d2d2d ---- DCD 757935405 - 0x0100271c: 2d2d2d2d ---- DCD 757935405 - 0x01002720: 2d2d2d2d ---- DCD 757935405 - 0x01002724: 2d2d202d - -- DCD 757932077 - 0x01002728: 2d2d2d2d ---- DCD 757935405 - 0x0100272c: 2d2d2d2d ---- DCD 757935405 - 0x01002730: 2d2d2d2d ---- DCD 757935405 - 0x01002734: 0000000a .... DCD 10 - 0x01002738: 2e2a2d25 %-*. DCD 774516005 - 0x0100273c: 2520732a *s % DCD 622883626 - 0x01002740: 3031302d -010 DCD 808529965 - 0x01002744: 2d252064 d %- DCD 757407844 - 0x01002748: 64333130 013d DCD 1681076528 - 0x0100274c: 302d2520 %-0 DCD 808264992 - 0x01002750: 000a6435 5d.. DCD 681013 - $t - i.list_mempool - list_mempool - 0x01002754: b5f0 .. PUSH {r4-r7,lr} - 0x01002756: b097 .. SUB sp,sp,#0x5c - 0x01002758: 2000 . MOVS r0,#0 - 0x0100275a: 9008 .. STR r0,[sp,#0x20] - 0x0100275c: a037 7. ADR r0,{pc}+0xe0 ; 0x100283c - 0x0100275e: 9006 .. STR r0,[sp,#0x18] - 0x01002760: 2308 .# MOVS r3,#8 - 0x01002762: aa09 .. ADD r2,sp,#0x24 - 0x01002764: 4619 .F MOV r1,r3 - 0x01002766: a811 .. ADD r0,sp,#0x44 - 0x01002768: f7fffe1c .... BL list_find_init ; 0x10023a4 - 0x0100276c: 2008 . MOVS r0,#8 - 0x0100276e: 9007 .. STR r0,[sp,#0x1c] - 0x01002770: a034 4. ADR r0,{pc}+0xd4 ; 0x1002844 - 0x01002772: 9a06 .. LDR r2,[sp,#0x18] - 0x01002774: 9907 .. LDR r1,[sp,#0x1c] - 0x01002776: f001feab .... BL rt_kprintf ; 0x10044d0 - 0x0100277a: 9807 .. LDR r0,[sp,#0x1c] - 0x0100277c: f000fdb6 .... BL object_split ; 0x10032ec - 0x01002780: a03a :. ADR r0,{pc}+0xec ; 0x100286c - 0x01002782: f001fea5 .... BL rt_kprintf ; 0x10044d0 - 0x01002786: bf00 .. NOP - 0x01002788: a911 .. ADD r1,sp,#0x44 - 0x0100278a: 9808 .. LDR r0,[sp,#0x20] - 0x0100278c: f7fffe1e .... BL list_get_next ; 0x10023cc - 0x01002790: 9008 .. STR r0,[sp,#0x20] - 0x01002792: 2600 .& MOVS r6,#0 - 0x01002794: e049 I. B 0x100282a ; list_mempool + 214 - 0x01002796: 00b0 .. LSLS r0,r6,#2 - 0x01002798: a909 .. ADD r1,sp,#0x24 - 0x0100279a: 5808 .X LDR r0,[r1,r0] - 0x0100279c: 4607 .F MOV r7,r0 - 0x0100279e: 3f0c .? SUBS r7,r7,#0xc - 0x010027a0: f7fdfe8e .... BL rt_hw_interrupt_disable ; 0x10004c0 - 0x010027a4: 9016 .. STR r0,[sp,#0x58] - 0x010027a6: 7a38 8z LDRB r0,[r7,#8] - 0x010027a8: 2180 .! MOVS r1,#0x80 - 0x010027aa: 4388 .C BICS r0,r0,r1 - 0x010027ac: a910 .. ADD r1,sp,#0x40 - 0x010027ae: 7b09 .{ LDRB r1,[r1,#0xc] - 0x010027b0: 4288 .B CMP r0,r1 - 0x010027b2: d003 .. BEQ 0x10027bc ; list_mempool + 104 - 0x010027b4: 9816 .. LDR r0,[sp,#0x58] - 0x010027b6: f7fdfe87 .... BL rt_hw_interrupt_enable ; 0x10004c8 - 0x010027ba: e035 5. B 0x1002828 ; list_mempool + 212 - 0x010027bc: 9816 .. LDR r0,[sp,#0x58] - 0x010027be: f7fdfe83 .... BL rt_hw_interrupt_enable ; 0x10004c8 - 0x010027c2: 463c SUBS r6,r6,#0xc - 0x01002912: f7fdfdd5 .... BL rt_hw_interrupt_disable ; 0x10004c0 - 0x01002916: 9012 .. STR r0,[sp,#0x48] - 0x01002918: 7a30 0z LDRB r0,[r6,#8] - 0x0100291a: 2180 .! MOVS r1,#0x80 - 0x0100291c: 4388 .C BICS r0,r0,r1 - 0x0100291e: a908 .. ADD r1,sp,#0x20 - 0x01002920: 7f09 .. LDRB r1,[r1,#0x1c] - 0x01002922: 4288 .B CMP r0,r1 - 0x01002924: d003 .. BEQ 0x100292e ; list_msgqueue + 102 - 0x01002926: 9812 .. LDR r0,[sp,#0x48] - 0x01002928: f7fdfdce .... BL rt_hw_interrupt_enable ; 0x10004c8 - 0x0100292c: e02e .. B 0x100298c ; list_msgqueue + 196 - 0x0100292e: 9812 .. LDR r0,[sp,#0x48] - 0x01002930: f7fdfdca .... BL rt_hw_interrupt_enable ; 0x10004c8 - 0x01002934: 4634 4F MOV r4,r6 - 0x01002936: 4620 F MOV r0,r4 - 0x01002938: 3014 .0 ADDS r0,r0,#0x14 - 0x0100293a: f001fe14 .... BL rt_list_isempty ; 0x1004566 - 0x0100293e: 2800 .( CMP r0,#0 - 0x01002940: d115 .. BNE 0x100296e ; list_msgqueue + 166 - 0x01002942: 4620 F MOV r0,r4 - 0x01002944: 3014 .0 ADDS r0,r0,#0x14 - 0x01002946: f001fe26 ..&. BL rt_list_len ; 0x1004596 - 0x0100294a: 9002 .. STR r0,[sp,#8] - 0x0100294c: 8ca1 .. LDRH r1,[r4,#0x24] - 0x0100294e: 4623 #F MOV r3,r4 - 0x01002950: 2208 ." MOVS r2,#8 - 0x01002952: 9100 .. STR r1,[sp,#0] - 0x01002954: 9001 .. STR r0,[sp,#4] - 0x01002956: a022 ". ADR r0,{pc}+0x8a ; 0x10029e0 - 0x01002958: 9904 .. LDR r1,[sp,#0x10] - 0x0100295a: f001fdb9 .... BL rt_kprintf ; 0x10044d0 - 0x0100295e: 4620 F MOV r0,r4 - 0x01002960: 3014 .0 ADDS r0,r0,#0x14 - 0x01002962: f004fa39 ..9. BL show_wait_queue ; 0x1006dd8 - 0x01002966: a023 #. ADR r0,{pc}+0x8e ; 0x10029f4 - 0x01002968: f001fdb2 .... BL rt_kprintf ; 0x10044d0 - 0x0100296c: e00d .. B 0x100298a ; list_msgqueue + 194 - 0x0100296e: 4620 F MOV r0,r4 - 0x01002970: 3014 .0 ADDS r0,r0,#0x14 - 0x01002972: f001fe10 .... BL rt_list_len ; 0x1004596 - 0x01002976: 9002 .. STR r0,[sp,#8] - 0x01002978: 8ca1 .. LDRH r1,[r4,#0x24] - 0x0100297a: 4623 #F MOV r3,r4 - 0x0100297c: 2208 ." MOVS r2,#8 - 0x0100297e: 9100 .. STR r1,[sp,#0] - 0x01002980: 9001 .. STR r0,[sp,#4] - 0x01002982: a01d .. ADR r0,{pc}+0x76 ; 0x10029f8 - 0x01002984: 9904 .. LDR r1,[sp,#0x10] - 0x01002986: f001fda3 .... BL rt_kprintf ; 0x10044d0 - 0x0100298a: bf00 .. NOP - 0x0100298c: 1c6d m. ADDS r5,r5,#1 - 0x0100298e: 9811 .. LDR r0,[sp,#0x44] - 0x01002990: 42a8 .B CMP r0,r5 - 0x01002992: dcb9 .. BGT 0x1002908 ; list_msgqueue + 64 - 0x01002994: 2f00 ./ CMP r7,#0 - 0x01002996: d1b0 .. BNE 0x10028fa ; list_msgqueue + 50 - 0x01002998: 2000 . MOVS r0,#0 - 0x0100299a: b013 .. ADD sp,sp,#0x4c - 0x0100299c: bdf0 .. POP {r4-r7,pc} - $d - 0x0100299e: 0000 .. DCW 0 - 0x010029a0: 7167736d msgq DCD 1902605165 - 0x010029a4: 65756575 ueue DCD 1702192501 - 0x010029a8: 00000000 .... DCD 0 - 0x010029ac: 2e2a2d25 %-*. DCD 774516005 - 0x010029b0: 6e652073 s en DCD 1852121203 - 0x010029b4: 20797274 try DCD 544830068 - 0x010029b8: 70737573 susp DCD 1886614899 - 0x010029bc: 20646e65 end DCD 543452773 - 0x010029c0: 65726874 thre DCD 1701996660 - 0x010029c4: 000a6461 ad.. DCD 681057 - 0x010029c8: 2d2d2d20 --- DCD 757935392 - 0x010029cc: 2d20202d - - DCD 757080109 - 0x010029d0: 2d2d2d2d ---- DCD 757935405 - 0x010029d4: 2d2d2d2d ---- DCD 757935405 - 0x010029d8: 2d2d2d2d ---- DCD 757935405 - 0x010029dc: 00000a2d -... DCD 2605 - 0x010029e0: 2e2a2d25 %-*. DCD 774516005 - 0x010029e4: 2520732a *s % DCD 622883626 - 0x010029e8: 20643430 04d DCD 543437872 - 0x010029ec: 3a642520 %d: DCD 979641632 - 0x010029f0: 00000000 .... DCD 0 - 0x010029f4: 0000000a .... DCD 10 - 0x010029f8: 2e2a2d25 %-*. DCD 774516005 - 0x010029fc: 2520732a *s % DCD 622883626 - 0x01002a00: 20643430 04d DCD 543437872 - 0x01002a04: 0a642520 %d. DCD 174335264 - 0x01002a08: 00000000 .... DCD 0 - $t - i.list_mutex - list_mutex - 0x01002a0c: b5f0 .. PUSH {r4-r7,lr} - 0x01002a0e: b095 .. SUB sp,sp,#0x54 - 0x01002a10: 2700 .' MOVS r7,#0 - 0x01002a12: a028 (. ADR r0,{pc}+0xa2 ; 0x1002ab4 - 0x01002a14: 9005 .. STR r0,[sp,#0x14] - 0x01002a16: 2308 .# MOVS r3,#8 - 0x01002a18: aa07 .. ADD r2,sp,#0x1c - 0x01002a1a: 2103 .! MOVS r1,#3 - 0x01002a1c: a80f .. ADD r0,sp,#0x3c - 0x01002a1e: f7fffcc1 .... BL list_find_init ; 0x10023a4 - 0x01002a22: 2008 . MOVS r0,#8 - 0x01002a24: 9006 .. STR r0,[sp,#0x18] - 0x01002a26: a025 %. ADR r0,{pc}+0x96 ; 0x1002abc - 0x01002a28: 9a05 .. LDR r2,[sp,#0x14] - 0x01002a2a: 9906 .. LDR r1,[sp,#0x18] - 0x01002a2c: f001fd50 ..P. BL rt_kprintf ; 0x10044d0 - 0x01002a30: 9806 .. LDR r0,[sp,#0x18] - 0x01002a32: f000fc5b ..[. BL object_split ; 0x10032ec - 0x01002a36: a02a *. ADR r0,{pc}+0xaa ; 0x1002ae0 - 0x01002a38: f001fd4a ..J. BL rt_kprintf ; 0x10044d0 - 0x01002a3c: bf00 .. NOP - 0x01002a3e: a90f .. ADD r1,sp,#0x3c - 0x01002a40: 4638 8F MOV r0,r7 - 0x01002a42: f7fffcc3 .... BL list_get_next ; 0x10023cc - 0x01002a46: 4607 .F MOV r7,r0 - 0x01002a48: 2600 .& MOVS r6,#0 - 0x01002a4a: e02a *. B 0x1002aa2 ; list_mutex + 150 - 0x01002a4c: 00b0 .. LSLS r0,r6,#2 - 0x01002a4e: a907 .. ADD r1,sp,#0x1c - 0x01002a50: 5808 .X LDR r0,[r1,r0] - 0x01002a52: 4604 .F MOV r4,r0 - 0x01002a54: 3c0c .< SUBS r4,r4,#0xc - 0x01002a56: f7fdfd33 ..3. BL rt_hw_interrupt_disable ; 0x10004c0 - 0x01002a5a: 9014 .. STR r0,[sp,#0x50] - 0x01002a5c: 7a20 z LDRB r0,[r4,#8] - 0x01002a5e: 2180 .! MOVS r1,#0x80 - 0x01002a60: 4388 .C BICS r0,r0,r1 - 0x01002a62: a910 .. ADD r1,sp,#0x40 - 0x01002a64: 7909 .y LDRB r1,[r1,#4] - 0x01002a66: 4288 .B CMP r0,r1 - 0x01002a68: d003 .. BEQ 0x1002a72 ; list_mutex + 102 - 0x01002a6a: 9814 .. LDR r0,[sp,#0x50] - 0x01002a6c: f7fdfd2c ..,. BL rt_hw_interrupt_enable ; 0x10004c8 - 0x01002a70: e016 .. B 0x1002aa0 ; list_mutex + 148 - 0x01002a72: 9814 .. LDR r0,[sp,#0x50] - 0x01002a74: f7fdfd28 ..(. BL rt_hw_interrupt_enable ; 0x10004c8 - 0x01002a78: 4625 %F MOV r5,r4 - 0x01002a7a: 4628 (F MOV r0,r5 - 0x01002a7c: 3014 .0 ADDS r0,r0,#0x14 - 0x01002a7e: f001fd8a .... BL rt_list_len ; 0x1004596 - 0x01002a82: 9004 .. STR r0,[sp,#0x10] - 0x01002a84: 7fe9 .. LDRB r1,[r5,#0x1f] - 0x01002a86: 2308 .# MOVS r3,#8 - 0x01002a88: 6a2a *j LDR r2,[r5,#0x20] - 0x01002a8a: 9300 .. STR r3,[sp,#0] - 0x01002a8c: 9201 .. STR r2,[sp,#4] - 0x01002a8e: 9102 .. STR r1,[sp,#8] - 0x01002a90: 9003 .. STR r0,[sp,#0xc] - 0x01002a92: 462b +F MOV r3,r5 - 0x01002a94: 2208 ." MOVS r2,#8 - 0x01002a96: a01a .. ADR r0,{pc}+0x6a ; 0x1002b00 - 0x01002a98: 9906 .. LDR r1,[sp,#0x18] - 0x01002a9a: f001fd19 .... BL rt_kprintf ; 0x10044d0 - 0x01002a9e: bf00 .. NOP - 0x01002aa0: 1c76 v. ADDS r6,r6,#1 - 0x01002aa2: 9813 .. LDR r0,[sp,#0x4c] - 0x01002aa4: 42b0 .B CMP r0,r6 - 0x01002aa6: dcd1 .. BGT 0x1002a4c ; list_mutex + 64 - 0x01002aa8: 2f00 ./ CMP r7,#0 - 0x01002aaa: d1c8 .. BNE 0x1002a3e ; list_mutex + 50 - 0x01002aac: 2000 . MOVS r0,#0 - 0x01002aae: b015 .. ADD sp,sp,#0x54 - 0x01002ab0: bdf0 .. POP {r4-r7,pc} - $d - 0x01002ab2: 0000 .. DCW 0 - 0x01002ab4: 6574756d mute DCD 1702131053 - 0x01002ab8: 00000078 x... DCD 120 - 0x01002abc: 2e2a2d25 %-*. DCD 774516005 - 0x01002ac0: 20202073 s DCD 538976371 - 0x01002ac4: 656e776f owne DCD 1701738351 - 0x01002ac8: 68202072 r h DCD 1746935922 - 0x01002acc: 20646c6f old DCD 543452271 - 0x01002ad0: 70737573 susp DCD 1886614899 - 0x01002ad4: 20646e65 end DCD 543452773 - 0x01002ad8: 65726874 thre DCD 1701996660 - 0x01002adc: 000a6461 ad.. DCD 681057 - 0x01002ae0: 2d2d2d20 --- DCD 757935392 - 0x01002ae4: 2d2d2d2d ---- DCD 757935405 - 0x01002ae8: 2d2d202d - -- DCD 757932077 - 0x01002aec: 2d202d2d -- - DCD 757083437 - 0x01002af0: 2d2d2d2d ---- DCD 757935405 - 0x01002af4: 2d2d2d2d ---- DCD 757935405 - 0x01002af8: 2d2d2d2d ---- DCD 757935405 - 0x01002afc: 00000a2d -... DCD 2605 - 0x01002b00: 2e2a2d25 %-*. DCD 774516005 - 0x01002b04: 2520732a *s % DCD 622883626 - 0x01002b08: 2a2e382d -8.* DCD 707672109 - 0x01002b0c: 30252073 s %0 DCD 807739507 - 0x01002b10: 25206434 4d % DCD 622879796 - 0x01002b14: 00000a64 d... DCD 2660 - $t - i.list_sem - list_sem - 0x01002b18: b5f0 .. PUSH {r4-r7,lr} - 0x01002b1a: b093 .. SUB sp,sp,#0x4c - 0x01002b1c: 2700 .' MOVS r7,#0 - 0x01002b1e: a034 4. ADR r0,{pc}+0xd2 ; 0x1002bf0 - 0x01002b20: 9003 .. STR r0,[sp,#0xc] - 0x01002b22: 2308 .# MOVS r3,#8 - 0x01002b24: aa05 .. ADD r2,sp,#0x14 - 0x01002b26: 2102 .! MOVS r1,#2 - 0x01002b28: a80d .. ADD r0,sp,#0x34 - 0x01002b2a: f7fffc3b ..;. BL list_find_init ; 0x10023a4 - 0x01002b2e: 2008 . MOVS r0,#8 - 0x01002b30: 9004 .. STR r0,[sp,#0x10] - 0x01002b32: a032 2. ADR r0,{pc}+0xca ; 0x1002bfc - 0x01002b34: 9a03 .. LDR r2,[sp,#0xc] - 0x01002b36: 9904 .. LDR r1,[sp,#0x10] - 0x01002b38: f001fcca .... BL rt_kprintf ; 0x10044d0 - 0x01002b3c: 9804 .. LDR r0,[sp,#0x10] - 0x01002b3e: f000fbd5 .... BL object_split ; 0x10032ec - 0x01002b42: a035 5. ADR r0,{pc}+0xd6 ; 0x1002c18 - 0x01002b44: f001fcc4 .... BL rt_kprintf ; 0x10044d0 - 0x01002b48: bf00 .. NOP - 0x01002b4a: a90d .. ADD r1,sp,#0x34 - 0x01002b4c: 4638 8F MOV r0,r7 - 0x01002b4e: f7fffc3d ..=. BL list_get_next ; 0x10023cc - 0x01002b52: 4607 .F MOV r7,r0 - 0x01002b54: 2500 .% MOVS r5,#0 - 0x01002b56: e042 B. B 0x1002bde ; list_sem + 198 - 0x01002b58: 00a8 .. LSLS r0,r5,#2 - 0x01002b5a: a905 .. ADD r1,sp,#0x14 - 0x01002b5c: 5808 .X LDR r0,[r1,r0] - 0x01002b5e: 4606 .F MOV r6,r0 - 0x01002b60: 3e0c .> SUBS r6,r6,#0xc - 0x01002b62: f7fdfcad .... BL rt_hw_interrupt_disable ; 0x10004c0 - 0x01002b66: 9012 .. STR r0,[sp,#0x48] - 0x01002b68: 7a30 0z LDRB r0,[r6,#8] - 0x01002b6a: 2180 .! MOVS r1,#0x80 - 0x01002b6c: 4388 .C BICS r0,r0,r1 - 0x01002b6e: a908 .. ADD r1,sp,#0x20 - 0x01002b70: 7f09 .. LDRB r1,[r1,#0x1c] - 0x01002b72: 4288 .B CMP r0,r1 - 0x01002b74: d003 .. BEQ 0x1002b7e ; list_sem + 102 - 0x01002b76: 9812 .. LDR r0,[sp,#0x48] - 0x01002b78: f7fdfca6 .... BL rt_hw_interrupt_enable ; 0x10004c8 - 0x01002b7c: e02e .. B 0x1002bdc ; list_sem + 196 - 0x01002b7e: 9812 .. LDR r0,[sp,#0x48] - 0x01002b80: f7fdfca2 .... BL rt_hw_interrupt_enable ; 0x10004c8 - 0x01002b84: 4634 4F MOV r4,r6 - 0x01002b86: 4620 F MOV r0,r4 - 0x01002b88: 3014 .0 ADDS r0,r0,#0x14 - 0x01002b8a: f001fcec .... BL rt_list_isempty ; 0x1004566 - 0x01002b8e: 2800 .( CMP r0,#0 - 0x01002b90: d115 .. BNE 0x1002bbe ; list_sem + 166 - 0x01002b92: 4620 F MOV r0,r4 - 0x01002b94: 3014 .0 ADDS r0,r0,#0x14 - 0x01002b96: f001fcfe .... BL rt_list_len ; 0x1004596 - 0x01002b9a: 9002 .. STR r0,[sp,#8] - 0x01002b9c: 8ba1 .. LDRH r1,[r4,#0x1c] - 0x01002b9e: 4623 #F MOV r3,r4 - 0x01002ba0: 2208 ." MOVS r2,#8 - 0x01002ba2: 9100 .. STR r1,[sp,#0] - 0x01002ba4: 9001 .. STR r0,[sp,#4] - 0x01002ba6: a022 ". ADR r0,{pc}+0x8a ; 0x1002c30 - 0x01002ba8: 9904 .. LDR r1,[sp,#0x10] - 0x01002baa: f001fc91 .... BL rt_kprintf ; 0x10044d0 - 0x01002bae: 4620 F MOV r0,r4 - 0x01002bb0: 3014 .0 ADDS r0,r0,#0x14 - 0x01002bb2: f004f911 .... BL show_wait_queue ; 0x1006dd8 - 0x01002bb6: a017 .. ADR r0,{pc}+0x5e ; 0x1002c14 - 0x01002bb8: f001fc8a .... BL rt_kprintf ; 0x10044d0 - 0x01002bbc: e00d .. B 0x1002bda ; list_sem + 194 - 0x01002bbe: 4620 F MOV r0,r4 - 0x01002bc0: 3014 .0 ADDS r0,r0,#0x14 - 0x01002bc2: f001fce8 .... BL rt_list_len ; 0x1004596 - 0x01002bc6: 9002 .. STR r0,[sp,#8] - 0x01002bc8: 8ba1 .. LDRH r1,[r4,#0x1c] - 0x01002bca: 4623 #F MOV r3,r4 - 0x01002bcc: 2208 ." MOVS r2,#8 - 0x01002bce: 9100 .. STR r1,[sp,#0] - 0x01002bd0: 9001 .. STR r0,[sp,#4] - 0x01002bd2: a01b .. ADR r0,{pc}+0x6e ; 0x1002c40 - 0x01002bd4: 9904 .. LDR r1,[sp,#0x10] - 0x01002bd6: f001fc7b ..{. BL rt_kprintf ; 0x10044d0 - 0x01002bda: bf00 .. NOP - 0x01002bdc: 1c6d m. ADDS r5,r5,#1 - 0x01002bde: 9811 .. LDR r0,[sp,#0x44] - 0x01002be0: 42a8 .B CMP r0,r5 - 0x01002be2: dcb9 .. BGT 0x1002b58 ; list_sem + 64 - 0x01002be4: 2f00 ./ CMP r7,#0 - 0x01002be6: d1b0 .. BNE 0x1002b4a ; list_sem + 50 - 0x01002be8: 2000 . MOVS r0,#0 - 0x01002bea: b013 .. ADD sp,sp,#0x4c - 0x01002bec: bdf0 .. POP {r4-r7,pc} - $d - 0x01002bee: 0000 .. DCW 0 - 0x01002bf0: 616d6573 sema DCD 1634559347 - 0x01002bf4: 726f6870 phor DCD 1919903856 - 0x01002bf8: 00000065 e... DCD 101 - 0x01002bfc: 2e2a2d25 %-*. DCD 774516005 - 0x01002c00: 20762073 s v DCD 544612467 - 0x01002c04: 75732020 su DCD 1970479136 - 0x01002c08: 6e657073 spen DCD 1852141683 - 0x01002c0c: 68742064 d th DCD 1752440932 - 0x01002c10: 64616572 read DCD 1684104562 - 0x01002c14: 0000000a .... DCD 10 - 0x01002c18: 2d2d2d20 --- DCD 757935392 - 0x01002c1c: 2d2d2d20 --- DCD 757935392 - 0x01002c20: 2d2d2d2d ---- DCD 757935405 - 0x01002c24: 2d2d2d2d ---- DCD 757935405 - 0x01002c28: 0a2d2d2d ---. DCD 170732845 - 0x01002c2c: 00000000 .... DCD 0 - 0x01002c30: 2e2a2d25 %-*. DCD 774516005 - 0x01002c34: 2520732a *s % DCD 622883626 - 0x01002c38: 20643330 03d DCD 543437616 - 0x01002c3c: 003a6425 %d:. DCD 3826725 - 0x01002c40: 2e2a2d25 %-*. DCD 774516005 - 0x01002c44: 2520732a *s % DCD 622883626 - 0x01002c48: 20643330 03d DCD 543437616 - 0x01002c4c: 000a6425 %d.. DCD 680997 - $t - i.list_thread - list_thread - 0x01002c50: b5f0 .. PUSH {r4-r7,lr} - 0x01002c52: b0b7 .. SUB sp,sp,#0xdc - 0x01002c54: 2000 . MOVS r0,#0 - 0x01002c56: 9028 (. STR r0,[sp,#0xa0] - 0x01002c58: a049 I. ADR r0,{pc}+0x128 ; 0x1002d80 - 0x01002c5a: 9027 '. STR r0,[sp,#0x9c] - 0x01002c5c: 2308 .# MOVS r3,#8 - 0x01002c5e: aa29 ). ADD r2,sp,#0xa4 - 0x01002c60: 2101 .! MOVS r1,#1 - 0x01002c62: a831 1. ADD r0,sp,#0xc4 - 0x01002c64: f7fffb9e .... BL list_find_init ; 0x10023a4 - 0x01002c68: 2008 . MOVS r0,#8 - 0x01002c6a: 9026 &. STR r0,[sp,#0x98] - 0x01002c6c: 4846 FH LDR r0,[pc,#280] ; [0x1002d88] = 0x1007d60 - 0x01002c6e: 9a27 '. LDR r2,[sp,#0x9c] - 0x01002c70: 9926 &. LDR r1,[sp,#0x98] - 0x01002c72: f001fc2d ..-. BL rt_kprintf ; 0x10044d0 - 0x01002c76: 9826 &. LDR r0,[sp,#0x98] - 0x01002c78: f000fb38 ..8. BL object_split ; 0x10032ec - 0x01002c7c: a043 C. ADR r0,{pc}+0x110 ; 0x1002d8c - 0x01002c7e: f001fc27 ..'. BL rt_kprintf ; 0x10044d0 - 0x01002c82: bf00 .. NOP - 0x01002c84: a931 1. ADD r1,sp,#0xc4 - 0x01002c86: 9828 (. LDR r0,[sp,#0xa0] - 0x01002c88: f7fffba0 .... BL list_get_next ; 0x10023cc - 0x01002c8c: 9028 (. STR r0,[sp,#0xa0] - 0x01002c8e: 2000 . MOVS r0,#0 - 0x01002c90: 9025 %. STR r0,[sp,#0x94] - 0x01002c92: e06b k. B 0x1002d6c ; list_thread + 284 - 0x01002c94: 9825 %. LDR r0,[sp,#0x94] - 0x01002c96: 0080 .. LSLS r0,r0,#2 - 0x01002c98: a929 ). ADD r1,sp,#0xa4 - 0x01002c9a: 5808 .X LDR r0,[r1,r0] - 0x01002c9c: 4605 .F MOV r5,r0 - 0x01002c9e: 3d0c .= SUBS r5,r5,#0xc - 0x01002ca0: f7fdfc0e .... BL rt_hw_interrupt_disable ; 0x10004c0 - 0x01002ca4: 9036 6. STR r0,[sp,#0xd8] - 0x01002ca6: 7a28 (z LDRB r0,[r5,#8] - 0x01002ca8: 2180 .! MOVS r1,#0x80 - 0x01002caa: 4388 .C BICS r0,r0,r1 - 0x01002cac: a930 0. ADD r1,sp,#0xc0 - 0x01002cae: 7b09 .{ LDRB r1,[r1,#0xc] - 0x01002cb0: 4288 .B CMP r0,r1 - 0x01002cb2: d003 .. BEQ 0x1002cbc ; list_thread + 108 - 0x01002cb4: 9836 6. LDR r0,[sp,#0xd8] - 0x01002cb6: f7fdfc07 .... BL rt_hw_interrupt_enable ; 0x10004c8 - 0x01002cba: e054 T. B 0x1002d66 ; list_thread + 278 - 0x01002cbc: 2280 ." MOVS r2,#0x80 - 0x01002cbe: 4629 )F MOV r1,r5 - 0x01002cc0: a805 .. ADD r0,sp,#0x14 - 0x01002cc2: f001fdef .... BL rt_memcpy ; 0x10048a4 - 0x01002cc6: 9836 6. LDR r0,[sp,#0xd8] - 0x01002cc8: f7fdfbfe .... BL rt_hw_interrupt_enable ; 0x10004c8 - 0x01002ccc: 462c ,F MOV r4,r5 - 0x01002cce: 2035 5 MOVS r0,#0x35 - 0x01002cd0: 5d00 .] LDRB r0,[r0,r4] - 0x01002cd2: 4623 #F MOV r3,r4 - 0x01002cd4: 2208 ." MOVS r2,#8 - 0x01002cd6: 9000 .. STR r0,[sp,#0] - 0x01002cd8: a03c <. ADR r0,{pc}+0xf4 ; 0x1002dcc - 0x01002cda: 9926 &. LDR r1,[sp,#0x98] - 0x01002cdc: f001fbf8 .... BL rt_kprintf ; 0x10044d0 - 0x01002ce0: 2034 4 MOVS r0,#0x34 - 0x01002ce2: 5d00 .] LDRB r0,[r0,r4] - 0x01002ce4: 0746 F. LSLS r6,r0,#29 - 0x01002ce6: 0f76 v. LSRS r6,r6,#29 - 0x01002ce8: 2e01 .. CMP r6,#1 - 0x01002cea: d103 .. BNE 0x1002cf4 ; list_thread + 164 - 0x01002cec: a03a :. ADR r0,{pc}+0xec ; 0x1002dd8 - 0x01002cee: f001fbef .... BL rt_kprintf ; 0x10044d0 - 0x01002cf2: e016 .. B 0x1002d22 ; list_thread + 210 - 0x01002cf4: 2e02 .. CMP r6,#2 - 0x01002cf6: d103 .. BNE 0x1002d00 ; list_thread + 176 - 0x01002cf8: a03a :. ADR r0,{pc}+0xec ; 0x1002de4 - 0x01002cfa: f001fbe9 .... BL rt_kprintf ; 0x10044d0 - 0x01002cfe: e010 .. B 0x1002d22 ; list_thread + 210 - 0x01002d00: 2e00 .. CMP r6,#0 - 0x01002d02: d103 .. BNE 0x1002d0c ; list_thread + 188 - 0x01002d04: a03a :. ADR r0,{pc}+0xec ; 0x1002df0 - 0x01002d06: f001fbe3 .... BL rt_kprintf ; 0x10044d0 - 0x01002d0a: e00a .. B 0x1002d22 ; list_thread + 210 - 0x01002d0c: 2e04 .. CMP r6,#4 - 0x01002d0e: d103 .. BNE 0x1002d18 ; list_thread + 200 - 0x01002d10: a03a :. ADR r0,{pc}+0xec ; 0x1002dfc - 0x01002d12: f001fbdd .... BL rt_kprintf ; 0x10044d0 - 0x01002d16: e004 .. B 0x1002d22 ; list_thread + 210 - 0x01002d18: 2e03 .. CMP r6,#3 - 0x01002d1a: d102 .. BNE 0x1002d22 ; list_thread + 210 - 0x01002d1c: a03a :. ADR r0,{pc}+0xec ; 0x1002e08 - 0x01002d1e: f001fbd7 .... BL rt_kprintf ; 0x10044d0 - 0x01002d22: 6aa7 .j LDR r7,[r4,#0x28] - 0x01002d24: e000 .. B 0x1002d28 ; list_thread + 216 - 0x01002d26: 1c7f .. ADDS r7,r7,#1 - 0x01002d28: 7838 8x LDRB r0,[r7,#0] - 0x01002d2a: 2823 #( CMP r0,#0x23 - 0x01002d2c: d0fb .. BEQ 0x1002d26 ; list_thread + 214 - 0x01002d2e: 6aa3 .j LDR r3,[r4,#0x28] - 0x01002d30: 1afb .. SUBS r3,r7,r3 - 0x01002d32: 6ae2 .j LDR r2,[r4,#0x2c] - 0x01002d34: 1ad2 .. SUBS r2,r2,r3 - 0x01002d36: 2364 d# MOVS r3,#0x64 - 0x01002d38: 435a ZC MULS r2,r3,r2 - 0x01002d3a: 4610 .F MOV r0,r2 - 0x01002d3c: 6ae1 .j LDR r1,[r4,#0x2c] - 0x01002d3e: f7fdfd95 .... BL __aeabi_uidiv ; 0x100086c - 0x01002d42: 9004 .. STR r0,[sp,#0x10] - 0x01002d44: 6b21 !k LDR r1,[r4,#0x30] - 0x01002d46: 6ca0 .l LDR r0,[r4,#0x48] - 0x01002d48: 9101 .. STR r1,[sp,#4] - 0x01002d4a: 9000 .. STR r0,[sp,#0] - 0x01002d4c: 69e1 .i LDR r1,[r4,#0x1c] - 0x01002d4e: 6aa0 .j LDR r0,[r4,#0x28] - 0x01002d50: 1a40 @. SUBS r0,r0,r1 - 0x01002d52: 6ae1 .j LDR r1,[r4,#0x2c] - 0x01002d54: 1840 @. ADDS r0,r0,r1 - 0x01002d56: 9003 .. STR r0,[sp,#0xc] - 0x01002d58: 6ae2 .j LDR r2,[r4,#0x2c] - 0x01002d5a: 4601 .F MOV r1,r0 - 0x01002d5c: a02d -. ADR r0,{pc}+0xb8 ; 0x1002e14 - 0x01002d5e: 9b04 .. LDR r3,[sp,#0x10] - 0x01002d60: f001fbb6 .... BL rt_kprintf ; 0x10044d0 - 0x01002d64: bf00 .. NOP - 0x01002d66: 9825 %. LDR r0,[sp,#0x94] - 0x01002d68: 1c40 @. ADDS r0,r0,#1 - 0x01002d6a: 9025 %. STR r0,[sp,#0x94] - 0x01002d6c: 9935 5. LDR r1,[sp,#0xd4] - 0x01002d6e: 9825 %. LDR r0,[sp,#0x94] - 0x01002d70: 4281 .B CMP r1,r0 - 0x01002d72: dc8f .. BGT 0x1002c94 ; list_thread + 68 - 0x01002d74: 9828 (. LDR r0,[sp,#0xa0] - 0x01002d76: 2800 .( CMP r0,#0 - 0x01002d78: d184 .. BNE 0x1002c84 ; list_thread + 52 - 0x01002d7a: b037 7. ADD sp,sp,#0xdc - 0x01002d7c: bdf0 .. POP {r4-r7,pc} - $d - 0x01002d7e: 0000 .. DCW 0 - 0x01002d80: 65726874 thre DCD 1701996660 - 0x01002d84: 00006461 ad.. DCD 25697 - 0x01002d88: 01007d60 `}.. DCD 16809312 - 0x01002d8c: 2d2d2d20 --- DCD 757935392 - 0x01002d90: 2d2d2020 -- DCD 757932064 - 0x01002d94: 2d2d2d2d ---- DCD 757935405 - 0x01002d98: 2d2d202d - -- DCD 757932077 - 0x01002d9c: 2d2d2d2d ---- DCD 757935405 - 0x01002da0: 2d2d2d2d ---- DCD 757935405 - 0x01002da4: 2d2d2d20 --- DCD 757935392 - 0x01002da8: 2d2d2d2d ---- DCD 757935405 - 0x01002dac: 202d2d2d --- DCD 539831597 - 0x01002db0: 2d2d2d20 --- DCD 757935392 - 0x01002db4: 202d2d2d --- DCD 539831597 - 0x01002db8: 2d2d2d20 --- DCD 757935392 - 0x01002dbc: 2d2d2d2d ---- DCD 757935405 - 0x01002dc0: 202d2d2d --- DCD 539831597 - 0x01002dc4: 0a2d2d2d ---. DCD 170732845 - 0x01002dc8: 00000000 .... DCD 0 - 0x01002dcc: 2e2a2d25 %-*. DCD 774516005 - 0x01002dd0: 2520732a *s % DCD 622883626 - 0x01002dd4: 00206433 3d . DCD 2122803 - 0x01002dd8: 61657220 rea DCD 1634038304 - 0x01002ddc: 20207964 dy DCD 538999140 - 0x01002de0: 00000000 .... DCD 0 - 0x01002de4: 73757320 sus DCD 1937077024 - 0x01002de8: 646e6570 pend DCD 1684956528 - 0x01002dec: 00000000 .... DCD 0 - 0x01002df0: 696e6920 ini DCD 1768843552 - 0x01002df4: 20202074 t DCD 538976372 - 0x01002df8: 00000000 .... DCD 0 - 0x01002dfc: 6f6c6320 clo DCD 1869374240 - 0x01002e00: 20206573 se DCD 538994035 - 0x01002e04: 00000000 .... DCD 0 - 0x01002e08: 6e757220 run DCD 1853190688 - 0x01002e0c: 676e696e ning DCD 1735289198 - 0x01002e10: 00000000 .... DCD 0 - 0x01002e14: 25783020 0x% DCD 628633632 - 0x01002e18: 20783830 08x DCD 544749616 - 0x01002e1c: 30257830 0x%0 DCD 807761968 - 0x01002e20: 20207838 8x DCD 538998840 - 0x01002e24: 30252020 %0 DCD 807739424 - 0x01002e28: 25256432 2d%% DCD 623207474 - 0x01002e2c: 30202020 0 DCD 807411744 - 0x01002e30: 38302578 x%08 DCD 942679416 - 0x01002e34: 30252078 x %0 DCD 807739512 - 0x01002e38: 000a6433 3d.. DCD 681011 - $t - i.list_timer - list_timer - 0x01002e3c: b5f0 .. PUSH {r4-r7,lr} - 0x01002e3e: b093 .. SUB sp,sp,#0x4c - 0x01002e40: 2700 .' MOVS r7,#0 - 0x01002e42: a02d -. ADR r0,{pc}+0xb6 ; 0x1002ef8 - 0x01002e44: 9003 .. STR r0,[sp,#0xc] - 0x01002e46: 2308 .# MOVS r3,#8 - 0x01002e48: aa05 .. ADD r2,sp,#0x14 - 0x01002e4a: 210a .! MOVS r1,#0xa - 0x01002e4c: a80d .. ADD r0,sp,#0x34 - 0x01002e4e: f7fffaa9 .... BL list_find_init ; 0x10023a4 - 0x01002e52: 2008 . MOVS r0,#8 - 0x01002e54: 9004 .. STR r0,[sp,#0x10] - 0x01002e56: a02a *. ADR r0,{pc}+0xaa ; 0x1002f00 - 0x01002e58: 9a03 .. LDR r2,[sp,#0xc] - 0x01002e5a: 9904 .. LDR r1,[sp,#0x10] - 0x01002e5c: f001fb38 ..8. BL rt_kprintf ; 0x10044d0 - 0x01002e60: 9804 .. LDR r0,[sp,#0x10] - 0x01002e62: f000fa43 ..C. BL object_split ; 0x10032ec - 0x01002e66: a030 0. ADR r0,{pc}+0xc2 ; 0x1002f28 - 0x01002e68: f001fb32 ..2. BL rt_kprintf ; 0x10044d0 - 0x01002e6c: bf00 .. NOP - 0x01002e6e: a90d .. ADD r1,sp,#0x34 - 0x01002e70: 4638 8F MOV r0,r7 - 0x01002e72: f7fffaab .... BL list_get_next ; 0x10023cc - 0x01002e76: 4607 .F MOV r7,r0 - 0x01002e78: 2600 .& MOVS r6,#0 - 0x01002e7a: e02e .. B 0x1002eda ; list_timer + 158 - 0x01002e7c: 00b0 .. LSLS r0,r6,#2 - 0x01002e7e: a905 .. ADD r1,sp,#0x14 - 0x01002e80: 5808 .X LDR r0,[r1,r0] - 0x01002e82: 4604 .F MOV r4,r0 - 0x01002e84: 3c0c .< SUBS r4,r4,#0xc - 0x01002e86: f7fdfb1b .... BL rt_hw_interrupt_disable ; 0x10004c0 - 0x01002e8a: 9012 .. STR r0,[sp,#0x48] - 0x01002e8c: 7a20 z LDRB r0,[r4,#8] - 0x01002e8e: 2180 .! MOVS r1,#0x80 - 0x01002e90: 4388 .C BICS r0,r0,r1 - 0x01002e92: a908 .. ADD r1,sp,#0x20 - 0x01002e94: 7f09 .. LDRB r1,[r1,#0x1c] - 0x01002e96: 4288 .B CMP r0,r1 - 0x01002e98: d003 .. BEQ 0x1002ea2 ; list_timer + 102 - 0x01002e9a: 9812 .. LDR r0,[sp,#0x48] - 0x01002e9c: f7fdfb14 .... BL rt_hw_interrupt_enable ; 0x10004c8 - 0x01002ea0: e01a .. B 0x1002ed8 ; list_timer + 156 - 0x01002ea2: 9812 .. LDR r0,[sp,#0x48] - 0x01002ea4: f7fdfb10 .... BL rt_hw_interrupt_enable ; 0x10004c8 - 0x01002ea8: 4625 %F MOV r5,r4 - 0x01002eaa: 6aa9 .j LDR r1,[r5,#0x28] - 0x01002eac: 6a68 hj LDR r0,[r5,#0x24] - 0x01002eae: 462b +F MOV r3,r5 - 0x01002eb0: 2208 ." MOVS r2,#8 - 0x01002eb2: 9101 .. STR r1,[sp,#4] - 0x01002eb4: 9000 .. STR r0,[sp,#0] - 0x01002eb6: a025 %. ADR r0,{pc}+0x96 ; 0x1002f4c - 0x01002eb8: 9904 .. LDR r1,[sp,#0x10] - 0x01002eba: f001fb09 .... BL rt_kprintf ; 0x10044d0 - 0x01002ebe: 7a68 hz LDRB r0,[r5,#9] - 0x01002ec0: 07c0 .. LSLS r0,r0,#31 - 0x01002ec2: 0fc0 .. LSRS r0,r0,#31 - 0x01002ec4: 2800 .( CMP r0,#0 - 0x01002ec6: d003 .. BEQ 0x1002ed0 ; list_timer + 148 - 0x01002ec8: a026 &. ADR r0,{pc}+0x9c ; 0x1002f64 - 0x01002eca: f001fb01 .... BL rt_kprintf ; 0x10044d0 - 0x01002ece: e002 .. B 0x1002ed6 ; list_timer + 154 - 0x01002ed0: a027 '. ADR r0,{pc}+0xa0 ; 0x1002f70 - 0x01002ed2: f001fafd .... BL rt_kprintf ; 0x10044d0 - 0x01002ed6: bf00 .. NOP - 0x01002ed8: 1c76 v. ADDS r6,r6,#1 - 0x01002eda: 9811 .. LDR r0,[sp,#0x44] - 0x01002edc: 42b0 .B CMP r0,r6 - 0x01002ede: dccd .. BGT 0x1002e7c ; list_timer + 64 - 0x01002ee0: 2f00 ./ CMP r7,#0 - 0x01002ee2: d1c4 .. BNE 0x1002e6e ; list_timer + 50 - 0x01002ee4: f003f9fc .... BL rt_tick_get ; 0x10062e0 - 0x01002ee8: 4604 .F MOV r4,r0 - 0x01002eea: 4621 !F MOV r1,r4 - 0x01002eec: a024 $. ADR r0,{pc}+0x94 ; 0x1002f80 - 0x01002eee: f001faef .... BL rt_kprintf ; 0x10044d0 - 0x01002ef2: 2000 . MOVS r0,#0 - 0x01002ef4: b013 .. ADD sp,sp,#0x4c - 0x01002ef6: bdf0 .. POP {r4-r7,pc} - $d - 0x01002ef8: 656d6974 time DCD 1701669236 - 0x01002efc: 00000072 r... DCD 114 - 0x01002f00: 2e2a2d25 %-*. DCD 774516005 - 0x01002f04: 70202073 s p DCD 1881153651 - 0x01002f08: 6f697265 erio DCD 1869181541 - 0x01002f0c: 20636964 dic DCD 543385956 - 0x01002f10: 69742020 ti DCD 1769218080 - 0x01002f14: 756f656d meou DCD 1970234733 - 0x01002f18: 20202074 t DCD 538976372 - 0x01002f1c: 20202020 DCD 538976288 - 0x01002f20: 67616c66 flag DCD 1734437990 - 0x01002f24: 0000000a .... DCD 10 - 0x01002f28: 2d2d2d20 --- DCD 757935392 - 0x01002f2c: 2d2d2d2d ---- DCD 757935405 - 0x01002f30: 202d2d2d --- DCD 539831597 - 0x01002f34: 2d2d2d2d ---- DCD 757935405 - 0x01002f38: 2d2d2d2d ---- DCD 757935405 - 0x01002f3c: 2d202d2d -- - DCD 757083437 - 0x01002f40: 2d2d2d2d ---- DCD 757935405 - 0x01002f44: 2d2d2d2d ---- DCD 757935405 - 0x01002f48: 000a2d2d --.. DCD 666925 - 0x01002f4c: 2e2a2d25 %-*. DCD 774516005 - 0x01002f50: 3020732a *s 0 DCD 807433002 - 0x01002f54: 38302578 x%08 DCD 942679416 - 0x01002f58: 78302078 x 0x DCD 2016419960 - 0x01002f5c: 78383025 %08x DCD 2016948261 - 0x01002f60: 00000020 ... DCD 32 - 0x01002f64: 69746361 acti DCD 1769235297 - 0x01002f68: 65746176 vate DCD 1702125942 - 0x01002f6c: 00000a64 d... DCD 2660 - 0x01002f70: 63616564 deac DCD 1667327332 - 0x01002f74: 61766974 tiva DCD 1635150196 - 0x01002f78: 0a646574 ted. DCD 174351732 - 0x01002f7c: 00000000 .... DCD 0 - 0x01002f80: 72727563 curr DCD 1920103779 - 0x01002f84: 20746e65 ent DCD 544501349 - 0x01002f88: 6b636974 tick DCD 1801677172 - 0x01002f8c: 2578303a :0x% DCD 628633658 - 0x01002f90: 0a783830 08x. DCD 175650864 - 0x01002f94: 00000000 .... DCD 0 - $t - i.main - $Super$$main - 0x01002f98: b510 .. PUSH {r4,lr} - 0x01002f9a: 2401 .$ MOVS r4,#1 - 0x01002f9c: 2100 .! MOVS r1,#0 - 0x01002f9e: 2002 . MOVS r0,#2 - 0x01002fa0: f002f800 .... BL rt_pin_mode ; 0x1004fa4 - 0x01002fa4: e00f .. B 0x1002fc6 ; $Super$$main + 46 - 0x01002fa6: 2101 .! MOVS r1,#1 - 0x01002fa8: 2002 . MOVS r0,#2 - 0x01002faa: f002f81f .... BL rt_pin_write ; 0x1004fec - 0x01002fae: 20ff . MOVS r0,#0xff - 0x01002fb0: 30f5 .0 ADDS r0,r0,#0xf5 - 0x01002fb2: f002ff9b .... BL rt_thread_mdelay ; 0x1005eec - 0x01002fb6: 2100 .! MOVS r1,#0 - 0x01002fb8: 2002 . MOVS r0,#2 - 0x01002fba: f002f817 .... BL rt_pin_write ; 0x1004fec - 0x01002fbe: 20ff . MOVS r0,#0xff - 0x01002fc0: 30f5 .0 ADDS r0,r0,#0xf5 - 0x01002fc2: f002ff93 .... BL rt_thread_mdelay ; 0x1005eec - 0x01002fc6: 4620 F MOV r0,r4 - 0x01002fc8: 1c64 d. ADDS r4,r4,#1 - 0x01002fca: 2800 .( CMP r0,#0 - 0x01002fcc: d1eb .. BNE 0x1002fa6 ; $Super$$main + 14 - 0x01002fce: bd10 .. POP {r4,pc} - i.main_thread_entry - main_thread_entry - 0x01002fd0: b510 .. PUSH {r4,lr} - 0x01002fd2: 4604 .F MOV r4,r0 - 0x01002fd4: f000fc6e ..n. BL rt_components_init ; 0x10038b4 - 0x01002fd8: f7ffffde .... BL $Super$$main ; 0x1002f98 - 0x01002fdc: bd10 .. POP {r4,pc} - 0x01002fde: 0000 .. MOVS r0,r0 - i.memheaptrace - memheaptrace - 0x01002fe0: b570 p. PUSH {r4-r6,lr} - 0x01002fe2: 2007 . MOVS r0,#7 - 0x01002fe4: f001fefa .... BL rt_object_get_length ; 0x1004ddc - 0x01002fe8: 4605 .F MOV r5,r0 - 0x01002fea: 2d00 .- CMP r5,#0 - 0x01002fec: dd1f .. BLE 0x100302e ; memheaptrace + 78 - 0x01002fee: 00a8 .. LSLS r0,r5,#2 - 0x01002ff0: f001faf6 .... BL rt_malloc ; 0x10045e0 - 0x01002ff4: 4604 .F MOV r4,r0 - 0x01002ff6: 2c00 ., CMP r4,#0 - 0x01002ff8: d100 .. BNE 0x1002ffc ; memheaptrace + 28 - 0x01002ffa: bd70 p. POP {r4-r6,pc} - 0x01002ffc: f7fffb1c .... BL list_memheap ; 0x1002638 - 0x01003000: 2118 .! MOVS r1,#0x18 - 0x01003002: a00c .. ADR r0,{pc}+0x32 ; 0x1003034 - 0x01003004: f001fa64 ..d. BL rt_kprintf ; 0x10044d0 - 0x01003008: 462a *F MOV r2,r5 - 0x0100300a: 4621 !F MOV r1,r4 - 0x0100300c: 2007 . MOVS r0,#7 - 0x0100300e: f001ff00 .... BL rt_object_get_pointers ; 0x1004e12 - 0x01003012: 4605 .F MOV r5,r0 - 0x01003014: 2600 .& MOVS r6,#0 - 0x01003016: e004 .. B 0x1003022 ; memheaptrace + 66 - 0x01003018: 00b1 .. LSLS r1,r6,#2 - 0x0100301a: 5860 `X LDR r0,[r4,r1] - 0x0100301c: f001fc72 ..r. BL rt_memheap_dump ; 0x1004904 - 0x01003020: 1c76 v. ADDS r6,r6,#1 - 0x01003022: 42ae .B CMP r6,r5 - 0x01003024: dbf8 .. BLT 0x1003018 ; memheaptrace + 56 - 0x01003026: 4620 F MOV r0,r4 - 0x01003028: f000ff52 ..R. BL rt_free ; 0x1003ed0 - 0x0100302c: bf00 .. NOP - 0x0100302e: 2000 . MOVS r0,#0 - 0x01003030: e7e3 .. B 0x1002ffa ; memheaptrace + 26 - $d - 0x01003032: 0000 .. DCW 0 - 0x01003034: 686d656d memh DCD 1751999853 - 0x01003038: 20706165 eap DCD 544235877 - 0x0100303c: 64616568 head DCD 1684104552 - 0x01003040: 73207265 er s DCD 1931506277 - 0x01003044: 3a657a69 ize: DCD 979729001 - 0x01003048: 0a642520 %d. DCD 174335264 - 0x0100304c: 00000000 .... DCD 0 - $t - i.msh_auto_complete - msh_auto_complete - 0x01003050: b5f1 .. PUSH {r0,r4-r7,lr} - 0x01003052: b082 .. SUB sp,sp,#8 - 0x01003054: 2600 .& MOVS r6,#0 - 0x01003056: 2000 . MOVS r0,#0 - 0x01003058: 9001 .. STR r0,[sp,#4] - 0x0100305a: 9802 .. LDR r0,[sp,#8] - 0x0100305c: 7800 .x LDRB r0,[r0,#0] - 0x0100305e: 2800 .( CMP r0,#0 - 0x01003060: d104 .. BNE 0x100306c ; msh_auto_complete + 28 - 0x01003062: 2100 .! MOVS r1,#0 - 0x01003064: 4608 .F MOV r0,r1 - 0x01003066: f000f893 .... BL msh_help ; 0x1003190 - 0x0100306a: bdfe .. POP {r1-r7,pc} - 0x0100306c: 4818 .H LDR r0,[pc,#96] ; [0x10030d0] = 0x20014 - 0x0100306e: 6805 .h LDR r5,[r0,#0] - 0x01003070: e01f .. B 0x10030b2 ; msh_auto_complete + 98 - 0x01003072: 682f /h LDR r7,[r5,#0] - 0x01003074: 9802 .. LDR r0,[sp,#8] - 0x01003076: f7fdfae3 .... BL strlen ; 0x1000640 - 0x0100307a: 4602 .F MOV r2,r0 - 0x0100307c: 4639 9F MOV r1,r7 - 0x0100307e: 9000 .. STR r0,[sp,#0] - 0x01003080: 9802 .. LDR r0,[sp,#8] - 0x01003082: f7fdfaff .... BL strncmp ; 0x1000684 - 0x01003086: 2800 .( CMP r0,#0 - 0x01003088: d112 .. BNE 0x10030b0 ; msh_auto_complete + 96 - 0x0100308a: 2e00 .. CMP r6,#0 - 0x0100308c: d104 .. BNE 0x1003098 ; msh_auto_complete + 72 - 0x0100308e: 9701 .. STR r7,[sp,#4] - 0x01003090: 9801 .. LDR r0,[sp,#4] - 0x01003092: f7fdfad5 .... BL strlen ; 0x1000640 - 0x01003096: 4606 .F MOV r6,r0 - 0x01003098: 4639 9F MOV r1,r7 - 0x0100309a: 9801 .. LDR r0,[sp,#4] - 0x0100309c: f003feca .... BL str_common ; 0x1006e34 - 0x010030a0: 4604 .F MOV r4,r0 - 0x010030a2: 42b4 .B CMP r4,r6 - 0x010030a4: da00 .. BGE 0x10030a8 ; msh_auto_complete + 88 - 0x010030a6: 4626 &F MOV r6,r4 - 0x010030a8: 4639 9F MOV r1,r7 - 0x010030aa: a00a .. ADR r0,{pc}+0x2a ; 0x10030d4 - 0x010030ac: f001fa10 .... BL rt_kprintf ; 0x10044d0 - 0x010030b0: 350c .5 ADDS r5,r5,#0xc - 0x010030b2: 4809 .H LDR r0,[pc,#36] ; [0x10030d8] = 0x20018 - 0x010030b4: 6800 .h LDR r0,[r0,#0] - 0x010030b6: 4285 .B CMP r5,r0 - 0x010030b8: d3db .. BCC 0x1003072 ; msh_auto_complete + 34 - 0x010030ba: 9801 .. LDR r0,[sp,#4] - 0x010030bc: 2800 .( CMP r0,#0 - 0x010030be: d004 .. BEQ 0x10030ca ; msh_auto_complete + 122 - 0x010030c0: 4632 2F MOV r2,r6 - 0x010030c2: 9901 .. LDR r1,[sp,#4] - 0x010030c4: 9802 .. LDR r0,[sp,#8] - 0x010030c6: f002fd38 ..8. BL rt_strncpy ; 0x1005b3a - 0x010030ca: bf00 .. NOP - 0x010030cc: e7cd .. B 0x100306a ; msh_auto_complete + 26 - $d - 0x010030ce: 0000 .. DCW 0 - 0x010030d0: 00020014 .... DCD 131092 - 0x010030d4: 000a7325 %s.. DCD 684837 - 0x010030d8: 00020018 .... DCD 131096 - $t - i.msh_exec - msh_exec - 0x010030dc: b538 8. PUSH {r3-r5,lr} - 0x010030de: 4604 .F MOV r4,r0 - 0x010030e0: 460d .F MOV r5,r1 - 0x010030e2: e001 .. B 0x10030e8 ; msh_exec + 12 - 0x010030e4: 1c64 d. ADDS r4,r4,#1 - 0x010030e6: 1e6d m. SUBS r5,r5,#1 - 0x010030e8: 2d00 .- CMP r5,#0 - 0x010030ea: d005 .. BEQ 0x10030f8 ; msh_exec + 28 - 0x010030ec: 7820 x LDRB r0,[r4,#0] - 0x010030ee: 2820 ( CMP r0,#0x20 - 0x010030f0: d0f8 .. BEQ 0x10030e4 ; msh_exec + 8 - 0x010030f2: 7820 x LDRB r0,[r4,#0] - 0x010030f4: 2809 .( CMP r0,#9 - 0x010030f6: d0f5 .. BEQ 0x10030e4 ; msh_exec + 8 - 0x010030f8: 2d00 .- CMP r5,#0 - 0x010030fa: d101 .. BNE 0x1003100 ; msh_exec + 36 - 0x010030fc: 2000 . MOVS r0,#0 - 0x010030fe: bd38 8. POP {r3-r5,pc} - 0x01003100: 466a jF MOV r2,sp - 0x01003102: 4629 )F MOV r1,r5 - 0x01003104: 4620 F MOV r0,r4 - 0x01003106: f7fef80d .... BL _msh_exec_cmd ; 0x1001124 - 0x0100310a: 2800 .( CMP r0,#0 - 0x0100310c: d101 .. BNE 0x1003112 ; msh_exec + 54 - 0x0100310e: 9800 .. LDR r0,[sp,#0] - 0x01003110: e7f5 .. B 0x10030fe ; msh_exec + 34 - 0x01003112: 4620 F MOV r0,r4 - 0x01003114: e000 .. B 0x1003118 ; msh_exec + 60 - 0x01003116: 1c40 @. ADDS r0,r0,#1 - 0x01003118: 7801 .x LDRB r1,[r0,#0] - 0x0100311a: 2920 ) CMP r1,#0x20 - 0x0100311c: d002 .. BEQ 0x1003124 ; msh_exec + 72 - 0x0100311e: 7801 .x LDRB r1,[r0,#0] - 0x01003120: 2900 .) CMP r1,#0 - 0x01003122: d1f8 .. BNE 0x1003116 ; msh_exec + 58 - 0x01003124: 2100 .! MOVS r1,#0 - 0x01003126: 7001 .p STRB r1,[r0,#0] - 0x01003128: 4621 !F MOV r1,r4 - 0x0100312a: a003 .. ADR r0,{pc}+0xe ; 0x1003138 - 0x0100312c: f001f9d0 .... BL rt_kprintf ; 0x10044d0 - 0x01003130: 2000 . MOVS r0,#0 - 0x01003132: 43c0 .C MVNS r0,r0 - 0x01003134: e7e3 .. B 0x10030fe ; msh_exec + 34 - $d - 0x01003136: 0000 .. DCW 0 - 0x01003138: 203a7325 %s: DCD 540701477 - 0x0100313c: 6d6d6f63 comm DCD 1835888483 - 0x01003140: 20646e61 and DCD 543452769 - 0x01003144: 20746f6e not DCD 544501614 - 0x01003148: 6e756f66 foun DCD 1853189990 - 0x0100314c: 000a2e64 d... DCD 667236 - $t - i.msh_get_cmd - msh_get_cmd - 0x01003150: b5f8 .. PUSH {r3-r7,lr} - 0x01003152: 4606 .F MOV r6,r0 - 0x01003154: 460d .F MOV r5,r1 - 0x01003156: 2700 .' MOVS r7,#0 - 0x01003158: 480b .H LDR r0,[pc,#44] ; [0x1003188] = 0x20014 - 0x0100315a: 6804 .h LDR r4,[r0,#0] - 0x0100315c: e00d .. B 0x100317a ; msh_get_cmd + 42 - 0x0100315e: 462a *F MOV r2,r5 - 0x01003160: 4631 1F MOV r1,r6 - 0x01003162: 6820 h LDR r0,[r4,#0] - 0x01003164: f7fdfa8e .... BL strncmp ; 0x1000684 - 0x01003168: 2800 .( CMP r0,#0 - 0x0100316a: d105 .. BNE 0x1003178 ; msh_get_cmd + 40 - 0x0100316c: 6820 h LDR r0,[r4,#0] - 0x0100316e: 5d40 @] LDRB r0,[r0,r5] - 0x01003170: 2800 .( CMP r0,#0 - 0x01003172: d101 .. BNE 0x1003178 ; msh_get_cmd + 40 - 0x01003174: 68a7 .h LDR r7,[r4,#8] - 0x01003176: e004 .. B 0x1003182 ; msh_get_cmd + 50 - 0x01003178: 340c .4 ADDS r4,r4,#0xc - 0x0100317a: 4804 .H LDR r0,[pc,#16] ; [0x100318c] = 0x20018 - 0x0100317c: 6800 .h LDR r0,[r0,#0] - 0x0100317e: 4284 .B CMP r4,r0 - 0x01003180: d3ed .. BCC 0x100315e ; msh_get_cmd + 14 - 0x01003182: bf00 .. NOP - 0x01003184: 4638 8F MOV r0,r7 - 0x01003186: bdf8 .. POP {r3-r7,pc} - $d - 0x01003188: 00020014 .... DCD 131092 - 0x0100318c: 00020018 .... DCD 131096 - $t - i.msh_help - msh_help - 0x01003190: b570 p. PUSH {r4-r6,lr} - 0x01003192: 4605 .F MOV r5,r0 - 0x01003194: 460e .F MOV r6,r1 - 0x01003196: a00a .. ADR r0,{pc}+0x2a ; 0x10031c0 - 0x01003198: f001f99a .... BL rt_kprintf ; 0x10044d0 - 0x0100319c: 480f .H LDR r0,[pc,#60] ; [0x10031dc] = 0x20014 - 0x0100319e: 6804 .h LDR r4,[r0,#0] - 0x010031a0: e005 .. B 0x10031ae ; msh_help + 30 - 0x010031a2: a00f .. ADR r0,{pc}+0x3e ; 0x10031e0 - 0x010031a4: 6862 bh LDR r2,[r4,#4] - 0x010031a6: 6821 !h LDR r1,[r4,#0] - 0x010031a8: f001f992 .... BL rt_kprintf ; 0x10044d0 - 0x010031ac: 340c .4 ADDS r4,r4,#0xc - 0x010031ae: 480f .H LDR r0,[pc,#60] ; [0x10031ec] = 0x20018 - 0x010031b0: 6800 .h LDR r0,[r0,#0] - 0x010031b2: 4284 .B CMP r4,r0 - 0x010031b4: d3f5 .. BCC 0x10031a2 ; msh_help + 18 - 0x010031b6: a00e .. ADR r0,{pc}+0x3a ; 0x10031f0 - 0x010031b8: f001f98a .... BL rt_kprintf ; 0x10044d0 - 0x010031bc: 2000 . MOVS r0,#0 - 0x010031be: bd70 p. POP {r4-r6,pc} - $d - 0x010031c0: 542d5452 RT-T DCD 1412256850 - 0x010031c4: 61657268 hrea DCD 1634038376 - 0x010031c8: 68732064 d sh DCD 1752375396 - 0x010031cc: 206c6c65 ell DCD 543976549 - 0x010031d0: 6d6d6f63 comm DCD 1835888483 - 0x010031d4: 73646e61 ands DCD 1935961697 - 0x010031d8: 00000a3a :... DCD 2618 - 0x010031dc: 00020014 .... DCD 131092 - 0x010031e0: 36312d25 %-16 DCD 909192485 - 0x010031e4: 202d2073 s - DCD 539828339 - 0x010031e8: 000a7325 %s.. DCD 684837 - 0x010031ec: 00020018 .... DCD 131096 - 0x010031f0: 0000000a .... DCD 10 - $t - i.msh_split - msh_split - 0x010031f4: b5f7 .. PUSH {r0-r2,r4-r7,lr} - 0x010031f6: b082 .. SUB sp,sp,#8 - 0x010031f8: 460e .F MOV r6,r1 - 0x010031fa: 9c02 .. LDR r4,[sp,#8] - 0x010031fc: 2500 .% MOVS r5,#0 - 0x010031fe: 2700 .' MOVS r7,#0 - 0x01003200: e05b [. B 0x10032ba ; msh_split + 198 - 0x01003202: e003 .. B 0x100320c ; msh_split + 24 - 0x01003204: 2000 . MOVS r0,#0 - 0x01003206: 7020 p STRB r0,[r4,#0] - 0x01003208: 1c64 d. ADDS r4,r4,#1 - 0x0100320a: 1c6d m. ADDS r5,r5,#1 - 0x0100320c: 7820 x LDRB r0,[r4,#0] - 0x0100320e: 2820 ( CMP r0,#0x20 - 0x01003210: d002 .. BEQ 0x1003218 ; msh_split + 36 - 0x01003212: 7820 x LDRB r0,[r4,#0] - 0x01003214: 2809 .( CMP r0,#9 - 0x01003216: d101 .. BNE 0x100321c ; msh_split + 40 - 0x01003218: 42b5 .B CMP r5,r6 - 0x0100321a: d3f3 .. BCC 0x1003204 ; msh_split + 16 - 0x0100321c: 2f0a ./ CMP r7,#0xa - 0x0100321e: d316 .. BCC 0x100324e ; msh_split + 90 - 0x01003220: a029 ). ADR r0,{pc}+0xa8 ; 0x10032c8 - 0x01003222: f001f955 ..U. BL rt_kprintf ; 0x10044d0 - 0x01003226: 2000 . MOVS r0,#0 - 0x01003228: 9001 .. STR r0,[sp,#4] - 0x0100322a: e009 .. B 0x1003240 ; msh_split + 76 - 0x0100322c: 9801 .. LDR r0,[sp,#4] - 0x0100322e: 0082 .. LSLS r2,r0,#2 - 0x01003230: 9804 .. LDR r0,[sp,#0x10] - 0x01003232: 5881 .X LDR r1,[r0,r2] - 0x01003234: a02c ,. ADR r0,{pc}+0xb4 ; 0x10032e8 - 0x01003236: f001f94b ..K. BL rt_kprintf ; 0x10044d0 - 0x0100323a: 9801 .. LDR r0,[sp,#4] - 0x0100323c: 1c40 @. ADDS r0,r0,#1 - 0x0100323e: 9001 .. STR r0,[sp,#4] - 0x01003240: 9801 .. LDR r0,[sp,#4] - 0x01003242: 42b8 .B CMP r0,r7 - 0x01003244: d3f2 .. BCC 0x100322c ; msh_split + 56 - 0x01003246: a027 '. ADR r0,{pc}+0x9e ; 0x10032e4 - 0x01003248: f001f942 ..B. BL rt_kprintf ; 0x10044d0 - 0x0100324c: e037 7. B 0x10032be ; msh_split + 202 - 0x0100324e: 42b5 .B CMP r5,r6 - 0x01003250: d300 .. BCC 0x1003254 ; msh_split + 96 - 0x01003252: e034 4. B 0x10032be ; msh_split + 202 - 0x01003254: 7820 x LDRB r0,[r4,#0] - 0x01003256: 2822 "( CMP r0,#0x22 - 0x01003258: d11d .. BNE 0x1003296 ; msh_split + 162 - 0x0100325a: 1c64 d. ADDS r4,r4,#1 - 0x0100325c: 1c6d m. ADDS r5,r5,#1 - 0x0100325e: 00b9 .. LSLS r1,r7,#2 - 0x01003260: 9804 .. LDR r0,[sp,#0x10] - 0x01003262: 5044 DP STR r4,[r0,r1] - 0x01003264: 1c7f .. ADDS r7,r7,#1 - 0x01003266: e009 .. B 0x100327c ; msh_split + 136 - 0x01003268: 7820 x LDRB r0,[r4,#0] - 0x0100326a: 285c \( CMP r0,#0x5c - 0x0100326c: d104 .. BNE 0x1003278 ; msh_split + 132 - 0x0100326e: 7860 `x LDRB r0,[r4,#1] - 0x01003270: 2822 "( CMP r0,#0x22 - 0x01003272: d101 .. BNE 0x1003278 ; msh_split + 132 - 0x01003274: 1c64 d. ADDS r4,r4,#1 - 0x01003276: 1c6d m. ADDS r5,r5,#1 - 0x01003278: 1c64 d. ADDS r4,r4,#1 - 0x0100327a: 1c6d m. ADDS r5,r5,#1 - 0x0100327c: 7820 x LDRB r0,[r4,#0] - 0x0100327e: 2822 "( CMP r0,#0x22 - 0x01003280: d001 .. BEQ 0x1003286 ; msh_split + 146 - 0x01003282: 42b5 .B CMP r5,r6 - 0x01003284: d3f0 .. BCC 0x1003268 ; msh_split + 116 - 0x01003286: 42b5 .B CMP r5,r6 - 0x01003288: d300 .. BCC 0x100328c ; msh_split + 152 - 0x0100328a: e018 .. B 0x10032be ; msh_split + 202 - 0x0100328c: 2000 . MOVS r0,#0 - 0x0100328e: 7020 p STRB r0,[r4,#0] - 0x01003290: 1c64 d. ADDS r4,r4,#1 - 0x01003292: 1c6d m. ADDS r5,r5,#1 - 0x01003294: e011 .. B 0x10032ba ; msh_split + 198 - 0x01003296: 00b9 .. LSLS r1,r7,#2 - 0x01003298: 9804 .. LDR r0,[sp,#0x10] - 0x0100329a: 5044 DP STR r4,[r0,r1] - 0x0100329c: 1c7f .. ADDS r7,r7,#1 - 0x0100329e: e001 .. B 0x10032a4 ; msh_split + 176 - 0x010032a0: 1c64 d. ADDS r4,r4,#1 - 0x010032a2: 1c6d m. ADDS r5,r5,#1 - 0x010032a4: 7820 x LDRB r0,[r4,#0] - 0x010032a6: 2820 ( CMP r0,#0x20 - 0x010032a8: d004 .. BEQ 0x10032b4 ; msh_split + 192 - 0x010032aa: 7820 x LDRB r0,[r4,#0] - 0x010032ac: 2809 .( CMP r0,#9 - 0x010032ae: d001 .. BEQ 0x10032b4 ; msh_split + 192 - 0x010032b0: 42b5 .B CMP r5,r6 - 0x010032b2: d3f5 .. BCC 0x10032a0 ; msh_split + 172 - 0x010032b4: 42b5 .B CMP r5,r6 - 0x010032b6: d300 .. BCC 0x10032ba ; msh_split + 198 - 0x010032b8: e001 .. B 0x10032be ; msh_split + 202 - 0x010032ba: 42b5 .B CMP r5,r6 - 0x010032bc: d3a1 .. BCC 0x1003202 ; msh_split + 14 - 0x010032be: bf00 .. NOP - 0x010032c0: 4638 8F MOV r0,r7 - 0x010032c2: b005 .. ADD sp,sp,#0x14 - 0x010032c4: bdf0 .. POP {r4-r7,pc} - $d - 0x010032c6: 0000 .. DCW 0 - 0x010032c8: 206f6f54 Too DCD 544173908 - 0x010032cc: 796e616d many DCD 2037277037 - 0x010032d0: 67726120 arg DCD 1735549216 - 0x010032d4: 20212073 s ! DCD 539041907 - 0x010032d8: 6f206557 We o DCD 1864394071 - 0x010032dc: 20796c6e nly DCD 544828526 - 0x010032e0: 3a657355 Use: DCD 979727189 - 0x010032e4: 0000000a .... DCD 10 - 0x010032e8: 00207325 %s . DCD 2126629 - $t - i.object_split - object_split - 0x010032ec: b510 .. PUSH {r4,lr} - 0x010032ee: 4604 .F MOV r4,r0 - 0x010032f0: e002 .. B 0x10032f8 ; object_split + 12 - 0x010032f2: a004 .. ADR r0,{pc}+0x12 ; 0x1003304 - 0x010032f4: f001f8ec .... BL rt_kprintf ; 0x10044d0 - 0x010032f8: 4620 F MOV r0,r4 - 0x010032fa: 1e64 d. SUBS r4,r4,#1 - 0x010032fc: 2800 .( CMP r0,#0 - 0x010032fe: d1f8 .. BNE 0x10032f2 ; object_split + 6 - 0x01003300: bd10 .. POP {r4,pc} - $d - 0x01003302: 0000 .. DCW 0 - 0x01003304: 0000002d -... DCD 45 - $t - i.plug_holes - plug_holes - 0x01003308: b570 p. PUSH {r4-r6,lr} - 0x0100330a: 4604 .F MOV r4,r0 - 0x0100330c: 4828 (H LDR r0,[pc,#160] ; [0x10033b0] = 0x2013c - 0x0100330e: 6800 .h LDR r0,[r0,#0] - 0x01003310: 4284 .B CMP r4,r0 - 0x01003312: d204 .. BCS 0x100331e ; plug_holes + 22 - 0x01003314: 22a1 ." MOVS r2,#0xa1 - 0x01003316: 4927 'I LDR r1,[pc,#156] ; [0x10033b4] = 0x1007bef - 0x01003318: a027 '. ADR r0,{pc}+0xa0 ; 0x10033b8 - 0x0100331a: f000f971 ..q. BL rt_assert_handler ; 0x1003600 - 0x0100331e: 482e .H LDR r0,[pc,#184] ; [0x10033d8] = 0x20140 - 0x01003320: 6800 .h LDR r0,[r0,#0] - 0x01003322: 4284 .B CMP r4,r0 - 0x01003324: d304 .. BCC 0x1003330 ; plug_holes + 40 - 0x01003326: 22a2 ." MOVS r2,#0xa2 - 0x01003328: 4922 "I LDR r1,[pc,#136] ; [0x10033b4] = 0x1007bef - 0x0100332a: a02c ,. ADR r0,{pc}+0xb2 ; 0x10033dc - 0x0100332c: f000f968 ..h. BL rt_assert_handler ; 0x1003600 - 0x01003330: 8860 `. LDRH r0,[r4,#2] - 0x01003332: 2800 .( CMP r0,#0 - 0x01003334: d004 .. BEQ 0x1003340 ; plug_holes + 56 - 0x01003336: 22a3 ." MOVS r2,#0xa3 - 0x01003338: 491e .I LDR r1,[pc,#120] ; [0x10033b4] = 0x1007bef - 0x0100333a: a033 3. ADR r0,{pc}+0xce ; 0x1003408 - 0x0100333c: f000f960 ..`. BL rt_assert_handler ; 0x1003600 - 0x01003340: 491b .I LDR r1,[pc,#108] ; [0x10033b0] = 0x2013c - 0x01003342: 6860 `h LDR r0,[r4,#4] - 0x01003344: 6809 .h LDR r1,[r1,#0] - 0x01003346: 1845 E. ADDS r5,r0,r1 - 0x01003348: 42ac .B CMP r4,r5 - 0x0100334a: d016 .. BEQ 0x100337a ; plug_holes + 114 - 0x0100334c: 8868 h. LDRH r0,[r5,#2] - 0x0100334e: 2800 .( CMP r0,#0 - 0x01003350: d113 .. BNE 0x100337a ; plug_holes + 114 - 0x01003352: 4821 !H LDR r0,[pc,#132] ; [0x10033d8] = 0x20140 - 0x01003354: 6800 .h LDR r0,[r0,#0] - 0x01003356: 4285 .B CMP r5,r0 - 0x01003358: d00f .. BEQ 0x100337a ; plug_holes + 114 - 0x0100335a: 482f /H LDR r0,[pc,#188] ; [0x1003418] = 0x20144 - 0x0100335c: 6800 .h LDR r0,[r0,#0] - 0x0100335e: 42a8 .B CMP r0,r5 - 0x01003360: d101 .. BNE 0x1003366 ; plug_holes + 94 - 0x01003362: 482d -H LDR r0,[pc,#180] ; [0x1003418] = 0x20144 - 0x01003364: 6004 .` STR r4,[r0,#0] - 0x01003366: 6868 hh LDR r0,[r5,#4] - 0x01003368: 6060 `` STR r0,[r4,#4] - 0x0100336a: 4811 .H LDR r0,[pc,#68] ; [0x10033b0] = 0x2013c - 0x0100336c: 6800 .h LDR r0,[r0,#0] - 0x0100336e: 1a20 . SUBS r0,r4,r0 - 0x01003370: 4a0f .J LDR r2,[pc,#60] ; [0x10033b0] = 0x2013c - 0x01003372: 6869 ih LDR r1,[r5,#4] - 0x01003374: 6812 .h LDR r2,[r2,#0] - 0x01003376: 1889 .. ADDS r1,r1,r2 - 0x01003378: 6088 .` STR r0,[r1,#8] - 0x0100337a: 490d .I LDR r1,[pc,#52] ; [0x10033b0] = 0x2013c - 0x0100337c: 68a0 .h LDR r0,[r4,#8] - 0x0100337e: 6809 .h LDR r1,[r1,#0] - 0x01003380: 1846 F. ADDS r6,r0,r1 - 0x01003382: 42a6 .B CMP r6,r4 - 0x01003384: d012 .. BEQ 0x10033ac ; plug_holes + 164 - 0x01003386: 8870 p. LDRH r0,[r6,#2] - 0x01003388: 2800 .( CMP r0,#0 - 0x0100338a: d10f .. BNE 0x10033ac ; plug_holes + 164 - 0x0100338c: 4822 "H LDR r0,[pc,#136] ; [0x1003418] = 0x20144 - 0x0100338e: 6800 .h LDR r0,[r0,#0] - 0x01003390: 42a0 .B CMP r0,r4 - 0x01003392: d101 .. BNE 0x1003398 ; plug_holes + 144 - 0x01003394: 4820 H LDR r0,[pc,#128] ; [0x1003418] = 0x20144 - 0x01003396: 6006 .` STR r6,[r0,#0] - 0x01003398: 6860 `h LDR r0,[r4,#4] - 0x0100339a: 6070 p` STR r0,[r6,#4] - 0x0100339c: 4804 .H LDR r0,[pc,#16] ; [0x10033b0] = 0x2013c - 0x0100339e: 6800 .h LDR r0,[r0,#0] - 0x010033a0: 1a31 1. SUBS r1,r6,r0 - 0x010033a2: 4a03 .J LDR r2,[pc,#12] ; [0x10033b0] = 0x2013c - 0x010033a4: 6860 `h LDR r0,[r4,#4] - 0x010033a6: 6812 .h LDR r2,[r2,#0] - 0x010033a8: 1880 .. ADDS r0,r0,r2 - 0x010033aa: 6081 .` STR r1,[r0,#8] - 0x010033ac: bd70 p. POP {r4-r6,pc} - $d - 0x010033ae: 0000 .. DCW 0 - 0x010033b0: 0002013c <... DCD 131388 - 0x010033b4: 01007bef .{.. DCD 16808943 - 0x010033b8: 5f747228 (rt_ DCD 1601466920 - 0x010033bc: 746e6975 uint DCD 1953393013 - 0x010033c0: 20745f38 8_t DCD 544497464 - 0x010033c4: 656d292a *)me DCD 1701652778 - 0x010033c8: 3d3e206d m >= DCD 1027481709 - 0x010033cc: 61656820 hea DCD 1634035744 - 0x010033d0: 74705f70 p_pt DCD 1953521520 - 0x010033d4: 00000072 r... DCD 114 - 0x010033d8: 00020140 @... DCD 131392 - 0x010033dc: 5f747228 (rt_ DCD 1601466920 - 0x010033e0: 746e6975 uint DCD 1953393013 - 0x010033e4: 20745f38 8_t DCD 544497464 - 0x010033e8: 656d292a *)me DCD 1701652778 - 0x010033ec: 203c206d m < DCD 540811373 - 0x010033f0: 5f747228 (rt_ DCD 1601466920 - 0x010033f4: 746e6975 uint DCD 1953393013 - 0x010033f8: 20745f38 8_t DCD 544497464 - 0x010033fc: 6568292a *)he DCD 1701325098 - 0x01003400: 655f7061 ap_e DCD 1700753505 - 0x01003404: 0000646e nd.. DCD 25710 - 0x01003408: 2d6d656d mem- DCD 762144109 - 0x0100340c: 6573753e >use DCD 1702065470 - 0x01003410: 3d3d2064 d == DCD 1027416164 - 0x01003414: 00003020 0.. DCD 12320 - 0x01003418: 00020144 D... DCD 131396 - $t - i.print_number - print_number - 0x0100341c: b5ff .. PUSH {r0-r7,lr} - 0x0100341e: b08b .. SUB sp,sp,#0x2c - 0x01003420: 4604 .F MOV r4,r0 - 0x01003422: 4615 .F MOV r5,r2 - 0x01003424: 9e16 .. LDR r6,[sp,#0x58] - 0x01003426: 9815 .. LDR r0,[sp,#0x54] - 0x01003428: 9004 .. STR r0,[sp,#0x10] - 0x0100342a: 9814 .. LDR r0,[sp,#0x50] - 0x0100342c: 9002 .. STR r0,[sp,#8] - 0x0100342e: 2040 @ MOVS r0,#0x40 - 0x01003430: 4030 0@ ANDS r0,r0,r6 - 0x01003432: 2800 .( CMP r0,#0 - 0x01003434: d001 .. BEQ 0x100343a ; print_number + 30 - 0x01003436: 485c \H LDR r0,[pc,#368] ; [0x10035a8] = 0x10077c4 - 0x01003438: e000 .. B 0x100343c ; print_number + 32 - 0x0100343a: 485c \H LDR r0,[pc,#368] ; [0x10035ac] = 0x10077b3 - 0x0100343c: 9003 .. STR r0,[sp,#0xc] - 0x0100343e: 2010 . MOVS r0,#0x10 - 0x01003440: 4030 0@ ANDS r0,r0,r6 - 0x01003442: 2800 .( CMP r0,#0 - 0x01003444: d001 .. BEQ 0x100344a ; print_number + 46 - 0x01003446: 0876 v. LSRS r6,r6,#1 - 0x01003448: 0076 v. LSLS r6,r6,#1 - 0x0100344a: 07f0 .. LSLS r0,r6,#31 - 0x0100344c: 0fc0 .. LSRS r0,r0,#31 - 0x0100344e: 2800 .( CMP r0,#0 - 0x01003450: d001 .. BEQ 0x1003456 ; print_number + 58 - 0x01003452: 2030 0 MOVS r0,#0x30 - 0x01003454: e000 .. B 0x1003458 ; print_number + 60 - 0x01003456: 2020 MOVS r0,#0x20 - 0x01003458: 900a .. STR r0,[sp,#0x28] - 0x0100345a: 2000 . MOVS r0,#0 - 0x0100345c: 9009 .. STR r0,[sp,#0x24] - 0x0100345e: 2002 . MOVS r0,#2 - 0x01003460: 4030 0@ ANDS r0,r0,r6 - 0x01003462: 2800 .( CMP r0,#0 - 0x01003464: d012 .. BEQ 0x100348c ; print_number + 112 - 0x01003466: 2d00 .- CMP r5,#0 - 0x01003468: da03 .. BGE 0x1003472 ; print_number + 86 - 0x0100346a: 202d - MOVS r0,#0x2d - 0x0100346c: 9009 .. STR r0,[sp,#0x24] - 0x0100346e: 426d mB RSBS r5,r5,#0 - 0x01003470: e00c .. B 0x100348c ; print_number + 112 - 0x01003472: 2004 . MOVS r0,#4 - 0x01003474: 4030 0@ ANDS r0,r0,r6 - 0x01003476: 2800 .( CMP r0,#0 - 0x01003478: d002 .. BEQ 0x1003480 ; print_number + 100 - 0x0100347a: 202b + MOVS r0,#0x2b - 0x0100347c: 9009 .. STR r0,[sp,#0x24] - 0x0100347e: e005 .. B 0x100348c ; print_number + 112 - 0x01003480: 2008 . MOVS r0,#8 - 0x01003482: 4030 0@ ANDS r0,r0,r6 - 0x01003484: 2800 .( CMP r0,#0 - 0x01003486: d001 .. BEQ 0x100348c ; print_number + 112 - 0x01003488: 2020 MOVS r0,#0x20 - 0x0100348a: 9009 .. STR r0,[sp,#0x24] - 0x0100348c: 2700 .' MOVS r7,#0 - 0x0100348e: 2d00 .- CMP r5,#0 - 0x01003490: d105 .. BNE 0x100349e ; print_number + 130 - 0x01003492: 2230 0" MOVS r2,#0x30 - 0x01003494: 4638 8F MOV r0,r7 - 0x01003496: 1c7f .. ADDS r7,r7,#1 - 0x01003498: a905 .. ADD r1,sp,#0x14 - 0x0100349a: 540a .T STRB r2,[r1,r0] - 0x0100349c: e01d .. B 0x10034da ; print_number + 190 - 0x0100349e: e01a .. B 0x10034d6 ; print_number + 186 - 0x010034a0: 980e .. LDR r0,[sp,#0x38] - 0x010034a2: 9001 .. STR r0,[sp,#4] - 0x010034a4: 9801 .. LDR r0,[sp,#4] - 0x010034a6: 280a .( CMP r0,#0xa - 0x010034a8: d10a .. BNE 0x10034c0 ; print_number + 164 - 0x010034aa: 4628 (F MOV r0,r5 - 0x010034ac: 210a .! MOVS r1,#0xa - 0x010034ae: f7fdf9dd .... BL __aeabi_uidiv ; 0x100086c - 0x010034b2: 9100 .. STR r1,[sp,#0] - 0x010034b4: 4628 (F MOV r0,r5 - 0x010034b6: 210a .! MOVS r1,#0xa - 0x010034b8: f7fdf9d8 .... BL __aeabi_uidiv ; 0x100086c - 0x010034bc: 4605 .F MOV r5,r0 - 0x010034be: e003 .. B 0x10034c8 ; print_number + 172 - 0x010034c0: 0728 (. LSLS r0,r5,#28 - 0x010034c2: 0f00 .. LSRS r0,r0,#28 - 0x010034c4: 9000 .. STR r0,[sp,#0] - 0x010034c6: 092d -. LSRS r5,r5,#4 - 0x010034c8: 9800 .. LDR r0,[sp,#0] - 0x010034ca: 9903 .. LDR r1,[sp,#0xc] - 0x010034cc: 5c0a .\ LDRB r2,[r1,r0] - 0x010034ce: 4638 8F MOV r0,r7 - 0x010034d0: 1c7f .. ADDS r7,r7,#1 - 0x010034d2: a905 .. ADD r1,sp,#0x14 - 0x010034d4: 540a .T STRB r2,[r1,r0] - 0x010034d6: 2d00 .- CMP r5,#0 - 0x010034d8: d1e2 .. BNE 0x10034a0 ; print_number + 132 - 0x010034da: 9815 .. LDR r0,[sp,#0x54] - 0x010034dc: 4287 .B CMP r7,r0 - 0x010034de: dd00 .. BLE 0x10034e2 ; print_number + 198 - 0x010034e0: 9715 .. STR r7,[sp,#0x54] - 0x010034e2: 9915 .. LDR r1,[sp,#0x54] - 0x010034e4: 9802 .. LDR r0,[sp,#8] - 0x010034e6: 1a40 @. SUBS r0,r0,r1 - 0x010034e8: 9002 .. STR r0,[sp,#8] - 0x010034ea: 2011 . MOVS r0,#0x11 - 0x010034ec: 4030 0@ ANDS r0,r0,r6 - 0x010034ee: 2800 .( CMP r0,#0 - 0x010034f0: d114 .. BNE 0x100351c ; print_number + 256 - 0x010034f2: 9809 .. LDR r0,[sp,#0x24] - 0x010034f4: 2800 .( CMP r0,#0 - 0x010034f6: d005 .. BEQ 0x1003504 ; print_number + 232 - 0x010034f8: 9802 .. LDR r0,[sp,#8] - 0x010034fa: 2800 .( CMP r0,#0 - 0x010034fc: dd02 .. BLE 0x1003504 ; print_number + 232 - 0x010034fe: 9802 .. LDR r0,[sp,#8] - 0x01003500: 1e40 @. SUBS r0,r0,#1 - 0x01003502: 9002 .. STR r0,[sp,#8] - 0x01003504: e005 .. B 0x1003512 ; print_number + 246 - 0x01003506: 980c .. LDR r0,[sp,#0x30] - 0x01003508: 4284 .B CMP r4,r0 - 0x0100350a: d201 .. BCS 0x1003510 ; print_number + 244 - 0x0100350c: 2020 MOVS r0,#0x20 - 0x0100350e: 7020 p STRB r0,[r4,#0] - 0x01003510: 1c64 d. ADDS r4,r4,#1 - 0x01003512: 9802 .. LDR r0,[sp,#8] - 0x01003514: 1e41 A. SUBS r1,r0,#1 - 0x01003516: 9102 .. STR r1,[sp,#8] - 0x01003518: 2800 .( CMP r0,#0 - 0x0100351a: dcf4 .. BGT 0x1003506 ; print_number + 234 - 0x0100351c: 9809 .. LDR r0,[sp,#0x24] - 0x0100351e: 2800 .( CMP r0,#0 - 0x01003520: d008 .. BEQ 0x1003534 ; print_number + 280 - 0x01003522: 980c .. LDR r0,[sp,#0x30] - 0x01003524: 4284 .B CMP r4,r0 - 0x01003526: d201 .. BCS 0x100352c ; print_number + 272 - 0x01003528: 9809 .. LDR r0,[sp,#0x24] - 0x0100352a: 7020 p STRB r0,[r4,#0] - 0x0100352c: 9802 .. LDR r0,[sp,#8] - 0x0100352e: 1e40 @. SUBS r0,r0,#1 - 0x01003530: 9002 .. STR r0,[sp,#8] - 0x01003532: 1c64 d. ADDS r4,r4,#1 - 0x01003534: 2010 . MOVS r0,#0x10 - 0x01003536: 4030 0@ ANDS r0,r0,r6 - 0x01003538: 2800 .( CMP r0,#0 - 0x0100353a: d10b .. BNE 0x1003554 ; print_number + 312 - 0x0100353c: e005 .. B 0x100354a ; print_number + 302 - 0x0100353e: 980c .. LDR r0,[sp,#0x30] - 0x01003540: 4284 .B CMP r4,r0 - 0x01003542: d201 .. BCS 0x1003548 ; print_number + 300 - 0x01003544: 980a .. LDR r0,[sp,#0x28] - 0x01003546: 7020 p STRB r0,[r4,#0] - 0x01003548: 1c64 d. ADDS r4,r4,#1 - 0x0100354a: 9802 .. LDR r0,[sp,#8] - 0x0100354c: 1e41 A. SUBS r1,r0,#1 - 0x0100354e: 9102 .. STR r1,[sp,#8] - 0x01003550: 2800 .( CMP r0,#0 - 0x01003552: dcf4 .. BGT 0x100353e ; print_number + 290 - 0x01003554: e005 .. B 0x1003562 ; print_number + 326 - 0x01003556: 980c .. LDR r0,[sp,#0x30] - 0x01003558: 4284 .B CMP r4,r0 - 0x0100355a: d201 .. BCS 0x1003560 ; print_number + 324 - 0x0100355c: 2030 0 MOVS r0,#0x30 - 0x0100355e: 7020 p STRB r0,[r4,#0] - 0x01003560: 1c64 d. ADDS r4,r4,#1 - 0x01003562: 9815 .. LDR r0,[sp,#0x54] - 0x01003564: 1e41 A. SUBS r1,r0,#1 - 0x01003566: 9115 .. STR r1,[sp,#0x54] - 0x01003568: 42b8 .B CMP r0,r7 - 0x0100356a: dcf4 .. BGT 0x1003556 ; print_number + 314 - 0x0100356c: e006 .. B 0x100357c ; print_number + 352 - 0x0100356e: 980c .. LDR r0,[sp,#0x30] - 0x01003570: 4284 .B CMP r4,r0 - 0x01003572: d202 .. BCS 0x100357a ; print_number + 350 - 0x01003574: a805 .. ADD r0,sp,#0x14 - 0x01003576: 5dc0 .] LDRB r0,[r0,r7] - 0x01003578: 7020 p STRB r0,[r4,#0] - 0x0100357a: 1c64 d. ADDS r4,r4,#1 - 0x0100357c: 4638 8F MOV r0,r7 - 0x0100357e: 1e7f .. SUBS r7,r7,#1 - 0x01003580: 2800 .( CMP r0,#0 - 0x01003582: dd02 .. BLE 0x100358a ; print_number + 366 - 0x01003584: 9804 .. LDR r0,[sp,#0x10] - 0x01003586: 2800 .( CMP r0,#0 - 0x01003588: d1f1 .. BNE 0x100356e ; print_number + 338 - 0x0100358a: e005 .. B 0x1003598 ; print_number + 380 - 0x0100358c: 980c .. LDR r0,[sp,#0x30] - 0x0100358e: 4284 .B CMP r4,r0 - 0x01003590: d201 .. BCS 0x1003596 ; print_number + 378 - 0x01003592: 2020 MOVS r0,#0x20 - 0x01003594: 7020 p STRB r0,[r4,#0] - 0x01003596: 1c64 d. ADDS r4,r4,#1 - 0x01003598: 9802 .. LDR r0,[sp,#8] - 0x0100359a: 1e41 A. SUBS r1,r0,#1 - 0x0100359c: 9102 .. STR r1,[sp,#8] - 0x0100359e: 2800 .( CMP r0,#0 - 0x010035a0: dcf4 .. BGT 0x100358c ; print_number + 368 - 0x010035a2: 4620 F MOV r0,r4 - 0x010035a4: b00f .. ADD sp,sp,#0x3c - 0x010035a6: bdf0 .. POP {r4-r7,pc} - $d - 0x010035a8: 010077c4 .w.. DCD 16807876 - 0x010035ac: 010077b3 .w.. DCD 16807859 - $t - i.rt_application_init - rt_application_init - 0x010035b0: b51c .. PUSH {r2-r4,lr} - 0x010035b2: 2014 . MOVS r0,#0x14 - 0x010035b4: 210a .! MOVS r1,#0xa - 0x010035b6: 2301 .# MOVS r3,#1 - 0x010035b8: 02db .. LSLS r3,r3,#11 - 0x010035ba: 2200 ." MOVS r2,#0 - 0x010035bc: 9100 .. STR r1,[sp,#0] - 0x010035be: 9001 .. STR r0,[sp,#4] - 0x010035c0: 4907 .I LDR r1,[pc,#28] ; [0x10035e0] = 0x1002fd1 - 0x010035c2: a008 .. ADR r0,{pc}+0x22 ; 0x10035e4 - 0x010035c4: f002fbbd .... BL rt_thread_create ; 0x1005d42 - 0x010035c8: 4604 .F MOV r4,r0 - 0x010035ca: 2c00 ., CMP r4,#0 - 0x010035cc: d104 .. BNE 0x10035d8 ; rt_application_init + 40 - 0x010035ce: 22cb ." MOVS r2,#0xcb - 0x010035d0: 4906 .I LDR r1,[pc,#24] ; [0x10035ec] = 0x1007584 - 0x010035d2: a007 .. ADR r0,{pc}+0x1e ; 0x10035f0 - 0x010035d4: f000f814 .... BL rt_assert_handler ; 0x1003600 - 0x010035d8: 4620 F MOV r0,r4 - 0x010035da: f002fd29 ..). BL rt_thread_startup ; 0x1006030 - 0x010035de: bd1c .. POP {r2-r4,pc} - $d - 0x010035e0: 01002fd1 ./.. DCD 16789457 - 0x010035e4: 6e69616d main DCD 1852399981 - 0x010035e8: 00000000 .... DCD 0 - 0x010035ec: 01007584 .u.. DCD 16807300 - 0x010035f0: 20646974 tid DCD 543451508 - 0x010035f4: 52203d21 != R DCD 1377844513 - 0x010035f8: 554e5f54 T_NU DCD 1431199572 - 0x010035fc: 00004c4c LL.. DCD 19532 - $t - i.rt_assert_handler - rt_assert_handler - 0x01003600: b5f8 .. PUSH {r3-r7,lr} - 0x01003602: 4604 .F MOV r4,r0 - 0x01003604: 460d .F MOV r5,r1 - 0x01003606: 4616 .F MOV r6,r2 - 0x01003608: 2000 . MOVS r0,#0 - 0x0100360a: 9000 .. STR r0,[sp,#0] - 0x0100360c: 480b .H LDR r0,[pc,#44] ; [0x100363c] = 0x20050 - 0x0100360e: 6800 .h LDR r0,[r0,#0] - 0x01003610: 2800 .( CMP r0,#0 - 0x01003612: d10b .. BNE 0x100362c ; rt_assert_handler + 44 - 0x01003614: 4633 3F MOV r3,r6 - 0x01003616: 462a *F MOV r2,r5 - 0x01003618: 4621 !F MOV r1,r4 - 0x0100361a: a009 .. ADR r0,{pc}+0x26 ; 0x1003640 - 0x0100361c: f000ff58 ..X. BL rt_kprintf ; 0x10044d0 - 0x01003620: bf00 .. NOP - 0x01003622: 4668 hF MOV r0,sp - 0x01003624: 7800 .x LDRB r0,[r0,#0] - 0x01003626: 2800 .( CMP r0,#0 - 0x01003628: d0fb .. BEQ 0x1003622 ; rt_assert_handler + 34 - 0x0100362a: e005 .. B 0x1003638 ; rt_assert_handler + 56 - 0x0100362c: 4632 2F MOV r2,r6 - 0x0100362e: 4629 )F MOV r1,r5 - 0x01003630: 4620 F MOV r0,r4 - 0x01003632: 4b02 .K LDR r3,[pc,#8] ; [0x100363c] = 0x20050 - 0x01003634: 681b .h LDR r3,[r3,#0] - 0x01003636: 4798 .G BLX r3 - 0x01003638: bdf8 .. POP {r3-r7,pc} - $d - 0x0100363a: 0000 .. DCW 0 - 0x0100363c: 00020050 P... DCD 131152 - 0x01003640: 29732528 (%s) DCD 695412008 - 0x01003644: 73736120 ass DCD 1936941344 - 0x01003648: 69747265 erti DCD 1769239141 - 0x0100364c: 66206e6f on f DCD 1713401455 - 0x01003650: 656c6961 aile DCD 1701603681 - 0x01003654: 74612064 d at DCD 1952522340 - 0x01003658: 6e756620 fun DCD 1853187616 - 0x0100365c: 6f697463 ctio DCD 1869182051 - 0x01003660: 73253a6e n:%s DCD 1931819630 - 0x01003664: 696c202c , li DCD 1768693804 - 0x01003668: 6e20656e ne n DCD 1847616878 - 0x0100366c: 65626d75 umbe DCD 1700949365 - 0x01003670: 64253a72 r:%d DCD 1680161394 - 0x01003674: 00000a20 ... DCD 2592 - $t - i.rt_calloc - rt_calloc - 0x01003678: b570 p. PUSH {r4-r6,lr} - 0x0100367a: 4604 .F MOV r4,r0 - 0x0100367c: 460d .F MOV r5,r1 - 0x0100367e: 4621 !F MOV r1,r4 - 0x01003680: 4369 iC MULS r1,r5,r1 - 0x01003682: 4608 .F MOV r0,r1 - 0x01003684: f000ffac .... BL rt_malloc ; 0x10045e0 - 0x01003688: 4606 .F MOV r6,r0 - 0x0100368a: 2e00 .. CMP r6,#0 - 0x0100368c: d006 .. BEQ 0x100369c ; rt_calloc + 36 - 0x0100368e: 4620 F MOV r0,r4 - 0x01003690: 4368 hC MULS r0,r5,r0 - 0x01003692: 4602 .F MOV r2,r0 - 0x01003694: 2100 .! MOVS r1,#0 - 0x01003696: 4630 0F MOV r0,r6 - 0x01003698: f001fa13 .... BL rt_memset ; 0x1004ac2 - 0x0100369c: 4630 0F MOV r0,r6 - 0x0100369e: bd70 p. POP {r4-r6,pc} - i.rt_completion_done - rt_completion_done - 0x010036a0: b570 p. PUSH {r4-r6,lr} - 0x010036a2: 4604 .F MOV r4,r0 - 0x010036a4: 2c00 ., CMP r4,#0 - 0x010036a6: d104 .. BNE 0x10036b2 ; rt_completion_done + 18 - 0x010036a8: 227f ." MOVS r2,#0x7f - 0x010036aa: 4911 .I LDR r1,[pc,#68] ; [0x10036f0] = 0x10073ee - 0x010036ac: a011 .. ADR r0,{pc}+0x48 ; 0x10036f4 - 0x010036ae: f7ffffa7 .... BL rt_assert_handler ; 0x1003600 - 0x010036b2: 6820 h LDR r0,[r4,#0] - 0x010036b4: 2801 .( CMP r0,#1 - 0x010036b6: d100 .. BNE 0x10036ba ; rt_completion_done + 26 - 0x010036b8: bd70 p. POP {r4-r6,pc} - 0x010036ba: f7fcff01 .... BL rt_hw_interrupt_disable ; 0x10004c0 - 0x010036be: 4606 .F MOV r6,r0 - 0x010036c0: 2001 . MOVS r0,#1 - 0x010036c2: 6020 ` STR r0,[r4,#0] - 0x010036c4: 1d20 . ADDS r0,r4,#4 - 0x010036c6: f000ff46 ..F. BL rt_list_isempty ; 0x1004556 - 0x010036ca: 2800 .( CMP r0,#0 - 0x010036cc: d10b .. BNE 0x10036e6 ; rt_completion_done + 70 - 0x010036ce: 6860 `h LDR r0,[r4,#4] - 0x010036d0: 4605 .F MOV r5,r0 - 0x010036d2: 3d14 .= SUBS r5,r5,#0x14 - 0x010036d4: 4628 (F MOV r0,r5 - 0x010036d6: f002fc13 .... BL rt_thread_resume ; 0x1005f00 - 0x010036da: 4630 0F MOV r0,r6 - 0x010036dc: f7fcfef4 .... BL rt_hw_interrupt_enable ; 0x10004c8 - 0x010036e0: f001fca8 .... BL rt_schedule ; 0x1005034 - 0x010036e4: e002 .. B 0x10036ec ; rt_completion_done + 76 - 0x010036e6: 4630 0F MOV r0,r6 - 0x010036e8: f7fcfeee .... BL rt_hw_interrupt_enable ; 0x10004c8 - 0x010036ec: bf00 .. NOP - 0x010036ee: e7e3 .. B 0x10036b8 ; rt_completion_done + 24 - $d - 0x010036f0: 010073ee .s.. DCD 16806894 - 0x010036f4: 706d6f63 comp DCD 1886220131 - 0x010036f8: 6974656c leti DCD 1769235820 - 0x010036fc: 21206e6f on ! DCD 555773551 - 0x01003700: 5452203d = RT DCD 1414668349 - 0x01003704: 4c554e5f _NUL DCD 1280659039 - 0x01003708: 0000004c L... DCD 76 - $t - i.rt_completion_init - rt_completion_init - 0x0100370c: b570 p. PUSH {r4-r6,lr} - 0x0100370e: 4604 .F MOV r4,r0 - 0x01003710: 2c00 ., CMP r4,#0 - 0x01003712: d104 .. BNE 0x100371e ; rt_completion_init + 18 - 0x01003714: 221b ." MOVS r2,#0x1b - 0x01003716: 4908 .I LDR r1,[pc,#32] ; [0x1003738] = 0x10073c8 - 0x01003718: a008 .. ADR r0,{pc}+0x24 ; 0x100373c - 0x0100371a: f7ffff71 ..q. BL rt_assert_handler ; 0x1003600 - 0x0100371e: f7fcfecf .... BL rt_hw_interrupt_disable ; 0x10004c0 - 0x01003722: 4605 .F MOV r5,r0 - 0x01003724: 2000 . MOVS r0,#0 - 0x01003726: 6020 ` STR r0,[r4,#0] - 0x01003728: 1d20 . ADDS r0,r4,#4 - 0x0100372a: 6040 @` STR r0,[r0,#4] - 0x0100372c: 6000 .` STR r0,[r0,#0] - 0x0100372e: bf00 .. NOP - 0x01003730: 4628 (F MOV r0,r5 - 0x01003732: f7fcfec9 .... BL rt_hw_interrupt_enable ; 0x10004c8 - 0x01003736: bd70 p. POP {r4-r6,pc} - $d - 0x01003738: 010073c8 .s.. DCD 16806856 - 0x0100373c: 706d6f63 comp DCD 1886220131 - 0x01003740: 6974656c leti DCD 1769235820 - 0x01003744: 21206e6f on ! DCD 555773551 - 0x01003748: 5452203d = RT DCD 1414668349 - 0x0100374c: 4c554e5f _NUL DCD 1280659039 - 0x01003750: 0000004c L... DCD 76 - $t - i.rt_completion_wait - rt_completion_wait - 0x01003754: b5f3 .. PUSH {r0,r1,r4-r7,lr} - 0x01003756: b081 .. SUB sp,sp,#4 - 0x01003758: 4605 .F MOV r5,r0 - 0x0100375a: 2d00 .- CMP r5,#0 - 0x0100375c: d104 .. BNE 0x1003768 ; rt_completion_wait + 20 - 0x0100375e: 223a :" MOVS r2,#0x3a - 0x01003760: 492f /I LDR r1,[pc,#188] ; [0x1003820] = 0x10073db - 0x01003762: a030 0. ADR r0,{pc}+0xc2 ; 0x1003824 - 0x01003764: f7ffff4c ..L. BL rt_assert_handler ; 0x1003600 - 0x01003768: 2600 .& MOVS r6,#0 - 0x0100376a: f002fc19 .... BL rt_thread_self ; 0x1005fa0 - 0x0100376e: 4604 .F MOV r4,r0 - 0x01003770: f7fcfea6 .... BL rt_hw_interrupt_disable ; 0x10004c0 - 0x01003774: 4607 .F MOV r7,r0 - 0x01003776: 6828 (h LDR r0,[r5,#0] - 0x01003778: 2801 .( CMP r0,#1 - 0x0100377a: d048 H. BEQ 0x100380e ; rt_completion_wait + 186 - 0x0100377c: 1d28 (. ADDS r0,r5,#4 - 0x0100377e: f000feea .... BL rt_list_isempty ; 0x1004556 - 0x01003782: 2800 .( CMP r0,#0 - 0x01003784: d104 .. BNE 0x1003790 ; rt_completion_wait + 60 - 0x01003786: 2243 C" MOVS r2,#0x43 - 0x01003788: 4925 %I LDR r1,[pc,#148] ; [0x1003820] = 0x10073db - 0x0100378a: a02c ,. ADR r0,{pc}+0xb2 ; 0x100383c - 0x0100378c: f7ffff38 ..8. BL rt_assert_handler ; 0x1003600 - 0x01003790: 9802 .. LDR r0,[sp,#8] - 0x01003792: 2800 .( CMP r0,#0 - 0x01003794: d101 .. BNE 0x100379a ; rt_completion_wait + 70 - 0x01003796: 1e86 .. SUBS r6,r0,#2 - 0x01003798: e03c <. B 0x1003814 ; rt_completion_wait + 192 - 0x0100379a: 2000 . MOVS r0,#0 - 0x0100379c: 6320 c STR r0,[r4,#0x30] - 0x0100379e: 4620 F MOV r0,r4 - 0x010037a0: f002fcaa .... BL rt_thread_suspend ; 0x10060f8 - 0x010037a4: 1d29 ). ADDS r1,r5,#4 - 0x010037a6: 4620 F MOV r0,r4 - 0x010037a8: 3014 .0 ADDS r0,r0,#0x14 - 0x010037aa: 684a Jh LDR r2,[r1,#4] - 0x010037ac: 6010 .` STR r0,[r2,#0] - 0x010037ae: 684a Jh LDR r2,[r1,#4] - 0x010037b0: 6042 B` STR r2,[r0,#4] - 0x010037b2: 6048 H` STR r0,[r1,#4] - 0x010037b4: 6001 .` STR r1,[r0,#0] - 0x010037b6: bf00 .. NOP - 0x010037b8: bf00 .. NOP - 0x010037ba: f7fcfe81 .... BL rt_hw_interrupt_disable ; 0x10004c0 - 0x010037be: 9000 .. STR r0,[sp,#0] - 0x010037c0: f000fe5c ..\. BL rt_interrupt_get_nest ; 0x100447c - 0x010037c4: 2800 .( CMP r0,#0 - 0x010037c6: d008 .. BEQ 0x10037da ; rt_completion_wait + 134 - 0x010037c8: 4915 .I LDR r1,[pc,#84] ; [0x1003820] = 0x10073db - 0x010037ca: a028 (. ADR r0,{pc}+0xa2 ; 0x100386c - 0x010037cc: f000fe80 .... BL rt_kprintf ; 0x10044d0 - 0x010037d0: 2256 V" MOVS r2,#0x56 - 0x010037d2: 4913 .I LDR r1,[pc,#76] ; [0x1003820] = 0x10073db - 0x010037d4: a02f /. ADR r0,{pc}+0xc0 ; 0x1003894 - 0x010037d6: f7ffff13 .... BL rt_assert_handler ; 0x1003600 - 0x010037da: 9800 .. LDR r0,[sp,#0] - 0x010037dc: f7fcfe74 ..t. BL rt_hw_interrupt_enable ; 0x10004c8 - 0x010037e0: bf00 .. NOP - 0x010037e2: 9802 .. LDR r0,[sp,#8] - 0x010037e4: 2800 .( CMP r0,#0 - 0x010037e6: dd09 .. BLE 0x10037fc ; rt_completion_wait + 168 - 0x010037e8: aa02 .. ADD r2,sp,#8 - 0x010037ea: 2100 .! MOVS r1,#0 - 0x010037ec: 4620 F MOV r0,r4 - 0x010037ee: 304c L0 ADDS r0,r0,#0x4c - 0x010037f0: f002fe1a .... BL rt_timer_control ; 0x1006428 - 0x010037f4: 4620 F MOV r0,r4 - 0x010037f6: 304c L0 ADDS r0,r0,#0x4c - 0x010037f8: f002ff1c .... BL rt_timer_start ; 0x1006634 - 0x010037fc: 4638 8F MOV r0,r7 - 0x010037fe: f7fcfe63 ..c. BL rt_hw_interrupt_enable ; 0x10004c8 - 0x01003802: f001fc17 .... BL rt_schedule ; 0x1005034 - 0x01003806: 6b26 &k LDR r6,[r4,#0x30] - 0x01003808: f7fcfe5a ..Z. BL rt_hw_interrupt_disable ; 0x10004c0 - 0x0100380c: 4607 .F MOV r7,r0 - 0x0100380e: 2000 . MOVS r0,#0 - 0x01003810: 6028 (` STR r0,[r5,#0] - 0x01003812: bf00 .. NOP - 0x01003814: 4638 8F MOV r0,r7 - 0x01003816: f7fcfe57 ..W. BL rt_hw_interrupt_enable ; 0x10004c8 - 0x0100381a: 4630 0F MOV r0,r6 - 0x0100381c: bdfe .. POP {r1-r7,pc} - $d - 0x0100381e: 0000 .. DCW 0 - 0x01003820: 010073db .s.. DCD 16806875 - 0x01003824: 706d6f63 comp DCD 1886220131 - 0x01003828: 6974656c leti DCD 1769235820 - 0x0100382c: 21206e6f on ! DCD 555773551 - 0x01003830: 5452203d = RT DCD 1414668349 - 0x01003834: 4c554e5f _NUL DCD 1280659039 - 0x01003838: 0000004c L... DCD 76 - 0x0100383c: 6c5f7472 rt_l DCD 1818195058 - 0x01003840: 5f747369 ist_ DCD 1601467241 - 0x01003844: 6d657369 isem DCD 1835365225 - 0x01003848: 28797470 pty( DCD 679048304 - 0x0100384c: 6f632826 &(co DCD 1868769318 - 0x01003850: 656c706d mple DCD 1701605485 - 0x01003854: 6e6f6974 tion DCD 1852795252 - 0x01003858: 75733e2d ->su DCD 1970486829 - 0x0100385c: 6e657073 spen DCD 1852141683 - 0x01003860: 5f646564 ded_ DCD 1600415076 - 0x01003864: 7473696c list DCD 1953720684 - 0x01003868: 00002929 )).. DCD 10537 - 0x0100386c: 636e7546 Func DCD 1668183366 - 0x01003870: 6e6f6974 tion DCD 1852795252 - 0x01003874: 5d73255b [%s] DCD 1567827291 - 0x01003878: 61687320 sha DCD 1634235168 - 0x0100387c: 6e206c6c ll n DCD 1847618668 - 0x01003880: 6220746f ot b DCD 1646294127 - 0x01003884: 73752065 e us DCD 1937055845 - 0x01003888: 69206465 ed i DCD 1763730533 - 0x0100388c: 5349206e n IS DCD 1397301358 - 0x01003890: 00000a52 R... DCD 2642 - 0x01003894: 00000030 0... DCD 48 - $t - i.rt_components_board_init - rt_components_board_init - 0x01003898: b510 .. PUSH {r4,lr} - 0x0100389a: 4c04 .L LDR r4,[pc,#16] ; [0x10038ac] = 0x10082f4 - 0x0100389c: e002 .. B 0x10038a4 ; rt_components_board_init + 12 - 0x0100389e: 6820 h LDR r0,[r4,#0] - 0x010038a0: 4780 .G BLX r0 - 0x010038a2: 1d24 $. ADDS r4,r4,#4 - 0x010038a4: 4802 .H LDR r0,[pc,#8] ; [0x10038b0] = 0x1008300 - 0x010038a6: 4284 .B CMP r4,r0 - 0x010038a8: d3f9 .. BCC 0x100389e ; rt_components_board_init + 6 - 0x010038aa: bd10 .. POP {r4,pc} - $d - 0x010038ac: 010082f4 .... DCD 16810740 - 0x010038b0: 01008300 .... DCD 16810752 - $t - i.rt_components_init - rt_components_init - 0x010038b4: b510 .. PUSH {r4,lr} - 0x010038b6: 4c04 .L LDR r4,[pc,#16] ; [0x10038c8] = 0x1008300 - 0x010038b8: e002 .. B 0x10038c0 ; rt_components_init + 12 - 0x010038ba: 6820 h LDR r0,[r4,#0] - 0x010038bc: 4780 .G BLX r0 - 0x010038be: 1d24 $. ADDS r4,r4,#4 - 0x010038c0: 4802 .H LDR r0,[pc,#8] ; [0x10038cc] = 0x1008308 - 0x010038c2: 4284 .B CMP r4,r0 - 0x010038c4: d3f9 .. BCC 0x10038ba ; rt_components_init + 6 - 0x010038c6: bd10 .. POP {r4,pc} - $d - 0x010038c8: 01008300 .... DCD 16810752 - 0x010038cc: 01008308 .... DCD 16810760 - $t - i.rt_console_get_device - rt_console_get_device - 0x010038d0: 4801 .H LDR r0,[pc,#4] ; [0x10038d8] = 0x2004c - 0x010038d2: 6800 .h LDR r0,[r0,#0] - 0x010038d4: 4770 pG BX lr - $d - 0x010038d6: 0000 .. DCW 0 - 0x010038d8: 0002004c L... DCD 131148 - $t - i.rt_console_set_device - rt_console_set_device - 0x010038dc: b570 p. PUSH {r4-r6,lr} - 0x010038de: 4606 .F MOV r6,r0 - 0x010038e0: 480d .H LDR r0,[pc,#52] ; [0x1003918] = 0x2004c - 0x010038e2: 6805 .h LDR r5,[r0,#0] - 0x010038e4: 4630 0F MOV r0,r6 - 0x010038e6: f000f8d5 .... BL rt_device_find ; 0x1003a94 - 0x010038ea: 4604 .F MOV r4,r0 - 0x010038ec: 42ac .B CMP r4,r5 - 0x010038ee: d101 .. BNE 0x10038f4 ; rt_console_set_device + 24 - 0x010038f0: 2000 . MOVS r0,#0 - 0x010038f2: bd70 p. POP {r4-r6,pc} - 0x010038f4: 2c00 ., CMP r4,#0 - 0x010038f6: d00d .. BEQ 0x1003914 ; rt_console_set_device + 56 - 0x010038f8: 4807 .H LDR r0,[pc,#28] ; [0x1003918] = 0x2004c - 0x010038fa: 6800 .h LDR r0,[r0,#0] - 0x010038fc: 2800 .( CMP r0,#0 - 0x010038fe: d003 .. BEQ 0x1003908 ; rt_console_set_device + 44 - 0x01003900: 4805 .H LDR r0,[pc,#20] ; [0x1003918] = 0x2004c - 0x01003902: 6800 .h LDR r0,[r0,#0] - 0x01003904: f000f86a ..j. BL rt_device_close ; 0x10039dc - 0x01003908: 2143 C! MOVS r1,#0x43 - 0x0100390a: 4620 F MOV r0,r4 - 0x0100390c: f000f8ca .... BL rt_device_open ; 0x1003aa4 - 0x01003910: 4801 .H LDR r0,[pc,#4] ; [0x1003918] = 0x2004c - 0x01003912: 6004 .` STR r4,[r0,#0] - 0x01003914: 4628 (F MOV r0,r5 - 0x01003916: e7ec .. B 0x10038f2 ; rt_console_set_device + 22 - $d - 0x01003918: 0002004c L... DCD 131148 - $t - i.rt_defunct_execute - rt_defunct_execute - 0x0100391c: b5f8 .. PUSH {r3-r7,lr} - 0x0100391e: e041 A. B 0x10039a4 ; rt_defunct_execute + 136 - 0x01003920: bf00 .. NOP - 0x01003922: f7fcfdcd .... BL rt_hw_interrupt_disable ; 0x10004c0 - 0x01003926: 4607 .F MOV r7,r0 - 0x01003928: f000fda8 .... BL rt_interrupt_get_nest ; 0x100447c - 0x0100392c: 2800 .( CMP r0,#0 - 0x0100392e: d008 .. BEQ 0x1003942 ; rt_defunct_execute + 38 - 0x01003930: 491e .I LDR r1,[pc,#120] ; [0x10039ac] = 0x10075e6 - 0x01003932: a01f .. ADR r0,{pc}+0x7e ; 0x10039b0 - 0x01003934: f000fdcc .... BL rt_kprintf ; 0x10044d0 - 0x01003938: 22cb ." MOVS r2,#0xcb - 0x0100393a: 491c .I LDR r1,[pc,#112] ; [0x10039ac] = 0x10075e6 - 0x0100393c: a026 &. ADR r0,{pc}+0x9c ; 0x10039d8 - 0x0100393e: f7fffe5f .._. BL rt_assert_handler ; 0x1003600 - 0x01003942: 4638 8F MOV r0,r7 - 0x01003944: f7fcfdc0 .... BL rt_hw_interrupt_enable ; 0x10004c8 - 0x01003948: bf00 .. NOP - 0x0100394a: f7fcfdb9 .... BL rt_hw_interrupt_disable ; 0x10004c0 - 0x0100394e: 4606 .F MOV r6,r0 - 0x01003950: f002fa20 .. . BL rt_thread_defunct_dequeue ; 0x1005d94 - 0x01003954: 4604 .F MOV r4,r0 - 0x01003956: 2c00 ., CMP r4,#0 - 0x01003958: d103 .. BNE 0x1003962 ; rt_defunct_execute + 70 - 0x0100395a: 4630 0F MOV r0,r6 - 0x0100395c: f7fcfdb4 .... BL rt_hw_interrupt_enable ; 0x10004c8 - 0x01003960: e021 !. B 0x10039a6 ; rt_defunct_execute + 138 - 0x01003962: 6fa5 .o LDR r5,[r4,#0x78] - 0x01003964: 2d00 .- CMP r5,#0 - 0x01003966: d007 .. BEQ 0x1003978 ; rt_defunct_execute + 92 - 0x01003968: 4630 0F MOV r0,r6 - 0x0100396a: f7fcfdad .... BL rt_hw_interrupt_enable ; 0x10004c8 - 0x0100396e: 4620 F MOV r0,r4 - 0x01003970: 47a8 .G BLX r5 - 0x01003972: f7fcfda5 .... BL rt_hw_interrupt_disable ; 0x10004c0 - 0x01003976: 4606 .F MOV r6,r0 - 0x01003978: 4620 F MOV r0,r4 - 0x0100397a: f001faf3 .... BL rt_object_is_systemobject ; 0x1004f64 - 0x0100397e: 2801 .( CMP r0,#1 - 0x01003980: d106 .. BNE 0x1003990 ; rt_defunct_execute + 116 - 0x01003982: 4620 F MOV r0,r4 - 0x01003984: f001f98e .... BL rt_object_detach ; 0x1004ca4 - 0x01003988: 4630 0F MOV r0,r6 - 0x0100398a: f7fcfd9d .... BL rt_hw_interrupt_enable ; 0x10004c8 - 0x0100398e: e008 .. B 0x10039a2 ; rt_defunct_execute + 134 - 0x01003990: 4630 0F MOV r0,r6 - 0x01003992: f7fcfd99 .... BL rt_hw_interrupt_enable ; 0x10004c8 - 0x01003996: 6aa0 .j LDR r0,[r4,#0x28] - 0x01003998: f000fa9a .... BL rt_free ; 0x1003ed0 - 0x0100399c: 4620 F MOV r0,r4 - 0x0100399e: f001f92d ..-. BL rt_object_delete ; 0x1004bfc - 0x010039a2: bf00 .. NOP - 0x010039a4: e7bc .. B 0x1003920 ; rt_defunct_execute + 4 - 0x010039a6: bf00 .. NOP - 0x010039a8: bdf8 .. POP {r3-r7,pc} - $d - 0x010039aa: 0000 .. DCW 0 - 0x010039ac: 010075e6 .u.. DCD 16807398 - 0x010039b0: 636e7546 Func DCD 1668183366 - 0x010039b4: 6e6f6974 tion DCD 1852795252 - 0x010039b8: 5d73255b [%s] DCD 1567827291 - 0x010039bc: 61687320 sha DCD 1634235168 - 0x010039c0: 6e206c6c ll n DCD 1847618668 - 0x010039c4: 6220746f ot b DCD 1646294127 - 0x010039c8: 73752065 e us DCD 1937055845 - 0x010039cc: 69206465 ed i DCD 1763730533 - 0x010039d0: 5349206e n IS DCD 1397301358 - 0x010039d4: 00000a52 R... DCD 2642 - 0x010039d8: 00000030 0... DCD 48 - $t - i.rt_device_close - rt_device_close - 0x010039dc: b570 p. PUSH {r4-r6,lr} - 0x010039de: 4604 .F MOV r4,r0 - 0x010039e0: 2500 .% MOVS r5,#0 - 0x010039e2: 2c00 ., CMP r4,#0 - 0x010039e4: d105 .. BNE 0x10039f2 ; rt_device_close + 22 - 0x010039e6: 22ff ." MOVS r2,#0xff - 0x010039e8: 320b .2 ADDS r2,r2,#0xb - 0x010039ea: 4916 .I LDR r1,[pc,#88] ; [0x1003a44] = 0x100763e - 0x010039ec: a016 .. ADR r0,{pc}+0x5c ; 0x1003a48 - 0x010039ee: f7fffe07 .... BL rt_assert_handler ; 0x1003600 - 0x010039f2: 4620 F MOV r0,r4 - 0x010039f4: f001fa3a ..:. BL rt_object_get_type ; 0x1004e6c - 0x010039f8: 2809 .( CMP r0,#9 - 0x010039fa: d005 .. BEQ 0x1003a08 ; rt_device_close + 44 - 0x010039fc: 22ff ." MOVS r2,#0xff - 0x010039fe: 320c .2 ADDS r2,r2,#0xc - 0x01003a00: 4910 .I LDR r1,[pc,#64] ; [0x1003a44] = 0x100763e - 0x01003a02: a015 .. ADR r0,{pc}+0x56 ; 0x1003a58 - 0x01003a04: f7fffdfc .... BL rt_assert_handler ; 0x1003600 - 0x01003a08: 7ea0 .~ LDRB r0,[r4,#0x1a] - 0x01003a0a: 2800 .( CMP r0,#0 - 0x01003a0c: d101 .. BNE 0x1003a12 ; rt_device_close + 54 - 0x01003a0e: 1e40 @. SUBS r0,r0,#1 - 0x01003a10: bd70 p. POP {r4-r6,pc} - 0x01003a12: 7ea0 .~ LDRB r0,[r4,#0x1a] - 0x01003a14: 1e40 @. SUBS r0,r0,#1 - 0x01003a16: 76a0 .v STRB r0,[r4,#0x1a] - 0x01003a18: 7ea0 .~ LDRB r0,[r4,#0x1a] - 0x01003a1a: 2800 .( CMP r0,#0 - 0x01003a1c: d001 .. BEQ 0x1003a22 ; rt_device_close + 70 - 0x01003a1e: 2000 . MOVS r0,#0 - 0x01003a20: e7f6 .. B 0x1003a10 ; rt_device_close + 52 - 0x01003a22: 6ae0 .j LDR r0,[r4,#0x2c] - 0x01003a24: 2800 .( CMP r0,#0 - 0x01003a26: d003 .. BEQ 0x1003a30 ; rt_device_close + 84 - 0x01003a28: 4620 F MOV r0,r4 - 0x01003a2a: 6ae1 .j LDR r1,[r4,#0x2c] - 0x01003a2c: 4788 .G BLX r1 - 0x01003a2e: 4605 .F MOV r5,r0 - 0x01003a30: 2d00 .- CMP r5,#0 - 0x01003a32: d002 .. BEQ 0x1003a3a ; rt_device_close + 94 - 0x01003a34: 1da8 .. ADDS r0,r5,#6 - 0x01003a36: 2800 .( CMP r0,#0 - 0x01003a38: d101 .. BNE 0x1003a3e ; rt_device_close + 98 - 0x01003a3a: 2000 . MOVS r0,#0 - 0x01003a3c: 8320 . STRH r0,[r4,#0x18] - 0x01003a3e: 4628 (F MOV r0,r5 - 0x01003a40: e7e6 .. B 0x1003a10 ; rt_device_close + 52 - $d - 0x01003a42: 0000 .. DCW 0 - 0x01003a44: 0100763e >v.. DCD 16807486 - 0x01003a48: 20766564 dev DCD 544630116 - 0x01003a4c: 52203d21 != R DCD 1377844513 - 0x01003a50: 554e5f54 T_NU DCD 1431199572 - 0x01003a54: 00004c4c LL.. DCD 19532 - 0x01003a58: 6f5f7472 rt_o DCD 1868526706 - 0x01003a5c: 63656a62 bjec DCD 1667590754 - 0x01003a60: 65675f74 t_ge DCD 1701273460 - 0x01003a64: 79745f74 t_ty DCD 2037669748 - 0x01003a68: 26286570 pe(& DCD 640181616 - 0x01003a6c: 2d766564 dev- DCD 762733924 - 0x01003a70: 7261703e >par DCD 1918988350 - 0x01003a74: 29746e65 ent) DCD 695496293 - 0x01003a78: 203d3d20 == DCD 540884256 - 0x01003a7c: 4f5f5452 RT_O DCD 1331647570 - 0x01003a80: 63656a62 bjec DCD 1667590754 - 0x01003a84: 6c435f74 t_Cl DCD 1816354676 - 0x01003a88: 5f737361 ass_ DCD 1601401697 - 0x01003a8c: 69766544 Devi DCD 1769366852 - 0x01003a90: 00006563 ce.. DCD 25955 - $t - i.rt_device_find - rt_device_find - 0x01003a94: b510 .. PUSH {r4,lr} - 0x01003a96: 4604 .F MOV r4,r0 - 0x01003a98: 2109 .! MOVS r1,#9 - 0x01003a9a: 4620 F MOV r0,r4 - 0x01003a9c: f001f932 ..2. BL rt_object_find ; 0x1004d04 - 0x01003aa0: bd10 .. POP {r4,pc} - 0x01003aa2: 0000 .. MOVS r0,r0 - i.rt_device_open - rt_device_open - 0x01003aa4: b570 p. PUSH {r4-r6,lr} - 0x01003aa6: 4604 .F MOV r4,r0 - 0x01003aa8: 460e .F MOV r6,r1 - 0x01003aaa: 2500 .% MOVS r5,#0 - 0x01003aac: 2c00 ., CMP r4,#0 - 0x01003aae: d104 .. BNE 0x1003aba ; rt_device_open + 22 - 0x01003ab0: 22c9 ." MOVS r2,#0xc9 - 0x01003ab2: 492a *I LDR r1,[pc,#168] ; [0x1003b5c] = 0x100762f - 0x01003ab4: a02a *. ADR r0,{pc}+0xac ; 0x1003b60 - 0x01003ab6: f7fffda3 .... BL rt_assert_handler ; 0x1003600 - 0x01003aba: 4620 F MOV r0,r4 - 0x01003abc: f001f9d6 .... BL rt_object_get_type ; 0x1004e6c - 0x01003ac0: 2809 .( CMP r0,#9 - 0x01003ac2: d004 .. BEQ 0x1003ace ; rt_device_open + 42 - 0x01003ac4: 22ca ." MOVS r2,#0xca - 0x01003ac6: 4925 %I LDR r1,[pc,#148] ; [0x1003b5c] = 0x100762f - 0x01003ac8: a029 ). ADR r0,{pc}+0xa8 ; 0x1003b70 - 0x01003aca: f7fffd99 .... BL rt_assert_handler ; 0x1003600 - 0x01003ace: 8ae0 .. LDRH r0,[r4,#0x16] - 0x01003ad0: 2110 .! MOVS r1,#0x10 - 0x01003ad2: 4008 .@ ANDS r0,r0,r1 - 0x01003ad4: 2800 .( CMP r0,#0 - 0x01003ad6: d113 .. BNE 0x1003b00 ; rt_device_open + 92 - 0x01003ad8: 6a60 `j LDR r0,[r4,#0x24] - 0x01003ada: 2800 .( CMP r0,#0 - 0x01003adc: d00c .. BEQ 0x1003af8 ; rt_device_open + 84 - 0x01003ade: 4620 F MOV r0,r4 - 0x01003ae0: 6a61 aj LDR r1,[r4,#0x24] - 0x01003ae2: 4788 .G BLX r1 - 0x01003ae4: 4605 .F MOV r5,r0 - 0x01003ae6: 2d00 .- CMP r5,#0 - 0x01003ae8: d006 .. BEQ 0x1003af8 ; rt_device_open + 84 - 0x01003aea: 462a *F MOV r2,r5 - 0x01003aec: 4621 !F MOV r1,r4 - 0x01003aee: a02f /. ADR r0,{pc}+0xbe ; 0x1003bac - 0x01003af0: f000fcee .... BL rt_kprintf ; 0x10044d0 - 0x01003af4: 4628 (F MOV r0,r5 - 0x01003af6: bd70 p. POP {r4-r6,pc} - 0x01003af8: 8ae0 .. LDRH r0,[r4,#0x16] - 0x01003afa: 2110 .! MOVS r1,#0x10 - 0x01003afc: 4308 .C ORRS r0,r0,r1 - 0x01003afe: 82e0 .. STRH r0,[r4,#0x16] - 0x01003b00: 8ae0 .. LDRH r0,[r4,#0x16] - 0x01003b02: 2108 .! MOVS r1,#8 - 0x01003b04: 4008 .@ ANDS r0,r0,r1 - 0x01003b06: 2800 .( CMP r0,#0 - 0x01003b08: d006 .. BEQ 0x1003b18 ; rt_device_open + 116 - 0x01003b0a: 8b20 . LDRH r0,[r4,#0x18] - 0x01003b0c: 4008 .@ ANDS r0,r0,r1 - 0x01003b0e: 2800 .( CMP r0,#0 - 0x01003b10: d002 .. BEQ 0x1003b18 ; rt_device_open + 116 - 0x01003b12: 2006 . MOVS r0,#6 - 0x01003b14: 43c0 .C MVNS r0,r0 - 0x01003b16: e7ee .. B 0x1003af6 ; rt_device_open + 82 - 0x01003b18: 6aa0 .j LDR r0,[r4,#0x28] - 0x01003b1a: 2800 .( CMP r0,#0 - 0x01003b1c: d005 .. BEQ 0x1003b2a ; rt_device_open + 134 - 0x01003b1e: 4631 1F MOV r1,r6 - 0x01003b20: 4620 F MOV r0,r4 - 0x01003b22: 6aa2 .j LDR r2,[r4,#0x28] - 0x01003b24: 4790 .G BLX r2 - 0x01003b26: 4605 .F MOV r5,r0 - 0x01003b28: e002 .. B 0x1003b30 ; rt_device_open + 140 - 0x01003b2a: 482e .H LDR r0,[pc,#184] ; [0x1003be4] = 0xf0f - 0x01003b2c: 4030 0@ ANDS r0,r0,r6 - 0x01003b2e: 8320 . STRH r0,[r4,#0x18] - 0x01003b30: 2d00 .- CMP r5,#0 - 0x01003b32: d002 .. BEQ 0x1003b3a ; rt_device_open + 150 - 0x01003b34: 1da8 .. ADDS r0,r5,#6 - 0x01003b36: 2800 .( CMP r0,#0 - 0x01003b38: d10e .. BNE 0x1003b58 ; rt_device_open + 180 - 0x01003b3a: 8b20 . LDRH r0,[r4,#0x18] - 0x01003b3c: 2108 .! MOVS r1,#8 - 0x01003b3e: 4308 .C ORRS r0,r0,r1 - 0x01003b40: 8320 . STRH r0,[r4,#0x18] - 0x01003b42: 7ea0 .~ LDRB r0,[r4,#0x1a] - 0x01003b44: 1c40 @. ADDS r0,r0,#1 - 0x01003b46: 76a0 .v STRB r0,[r4,#0x1a] - 0x01003b48: 7ea0 .~ LDRB r0,[r4,#0x1a] - 0x01003b4a: 2800 .( CMP r0,#0 - 0x01003b4c: d104 .. BNE 0x1003b58 ; rt_device_open + 180 - 0x01003b4e: 22f8 ." MOVS r2,#0xf8 - 0x01003b50: 4902 .I LDR r1,[pc,#8] ; [0x1003b5c] = 0x100762f - 0x01003b52: a025 %. ADR r0,{pc}+0x96 ; 0x1003be8 - 0x01003b54: f7fffd54 ..T. BL rt_assert_handler ; 0x1003600 - 0x01003b58: 4628 (F MOV r0,r5 - 0x01003b5a: e7cc .. B 0x1003af6 ; rt_device_open + 82 - $d - 0x01003b5c: 0100762f /v.. DCD 16807471 - 0x01003b60: 20766564 dev DCD 544630116 - 0x01003b64: 52203d21 != R DCD 1377844513 - 0x01003b68: 554e5f54 T_NU DCD 1431199572 - 0x01003b6c: 00004c4c LL.. DCD 19532 - 0x01003b70: 6f5f7472 rt_o DCD 1868526706 - 0x01003b74: 63656a62 bjec DCD 1667590754 - 0x01003b78: 65675f74 t_ge DCD 1701273460 - 0x01003b7c: 79745f74 t_ty DCD 2037669748 - 0x01003b80: 26286570 pe(& DCD 640181616 - 0x01003b84: 2d766564 dev- DCD 762733924 - 0x01003b88: 7261703e >par DCD 1918988350 - 0x01003b8c: 29746e65 ent) DCD 695496293 - 0x01003b90: 203d3d20 == DCD 540884256 - 0x01003b94: 4f5f5452 RT_O DCD 1331647570 - 0x01003b98: 63656a62 bjec DCD 1667590754 - 0x01003b9c: 6c435f74 t_Cl DCD 1816354676 - 0x01003ba0: 5f737361 ass_ DCD 1601401697 - 0x01003ba4: 69766544 Devi DCD 1769366852 - 0x01003ba8: 00006563 ce.. DCD 25955 - 0x01003bac: 69206f54 To i DCD 1763733332 - 0x01003bb0: 6974696e niti DCD 1769236846 - 0x01003bb4: 7a696c61 aliz DCD 2053729377 - 0x01003bb8: 65642065 e de DCD 1701060709 - 0x01003bbc: 65636976 vice DCD 1701013878 - 0x01003bc0: 2073253a :%s DCD 544417082 - 0x01003bc4: 6c696166 fail DCD 1818845542 - 0x01003bc8: 202e6465 ed. DCD 539911269 - 0x01003bcc: 20656854 The DCD 543516756 - 0x01003bd0: 6f727265 erro DCD 1869771365 - 0x01003bd4: 6f632072 r co DCD 1868767346 - 0x01003bd8: 69206564 de i DCD 1763730788 - 0x01003bdc: 64252073 s %d DCD 1680154739 - 0x01003be0: 0000000a .... DCD 10 - 0x01003be4: 00000f0f .... DCD 3855 - 0x01003be8: 2d766564 dev- DCD 762733924 - 0x01003bec: 6665723e >ref DCD 1717924414 - 0x01003bf0: 756f635f _cou DCD 1970234207 - 0x01003bf4: 2120746e nt ! DCD 555775086 - 0x01003bf8: 0030203d = 0. DCD 3153981 - $t - i.rt_device_pin_register - rt_device_pin_register - 0x01003bfc: b570 p. PUSH {r4-r6,lr} - 0x01003bfe: 4604 .F MOV r4,r0 - 0x01003c00: 460e .F MOV r6,r1 - 0x01003c02: 4615 .F MOV r5,r2 - 0x01003c04: 2013 . MOVS r0,#0x13 - 0x01003c06: 490b .I LDR r1,[pc,#44] ; [0x1003c34] = 0x20158 - 0x01003c08: 7508 .u STRB r0,[r1,#0x14] - 0x01003c0a: 2000 . MOVS r0,#0 - 0x01003c0c: 61c8 .a STR r0,[r1,#0x1c] - 0x01003c0e: 6208 .b STR r0,[r1,#0x20] - 0x01003c10: 6248 Hb STR r0,[r1,#0x24] - 0x01003c12: 6288 .b STR r0,[r1,#0x28] - 0x01003c14: 62c8 .b STR r0,[r1,#0x2c] - 0x01003c16: 4808 .H LDR r0,[pc,#32] ; [0x1003c38] = 0x1001201 - 0x01003c18: 6308 .c STR r0,[r1,#0x30] - 0x01003c1a: 4808 .H LDR r0,[pc,#32] ; [0x1003c3c] = 0x1001251 - 0x01003c1c: 6348 Hc STR r0,[r1,#0x34] - 0x01003c1e: 4808 .H LDR r0,[pc,#32] ; [0x1003c40] = 0x10011bd - 0x01003c20: 6388 .c STR r0,[r1,#0x38] - 0x01003c22: 4608 .F MOV r0,r1 - 0x01003c24: 6406 .d STR r6,[r0,#0x40] - 0x01003c26: 63c5 .c STR r5,[r0,#0x3c] - 0x01003c28: 2203 ." MOVS r2,#3 - 0x01003c2a: 4621 !F MOV r1,r4 - 0x01003c2c: f000f864 ..d. BL rt_device_register ; 0x1003cf8 - 0x01003c30: 2000 . MOVS r0,#0 - 0x01003c32: bd70 p. POP {r4-r6,pc} - $d - 0x01003c34: 00020158 X... DCD 131416 - 0x01003c38: 01001201 .... DCD 16781825 - 0x01003c3c: 01001251 Q... DCD 16781905 - 0x01003c40: 010011bd .... DCD 16781757 - $t - i.rt_device_read - rt_device_read - 0x01003c44: b5ff .. PUSH {r0-r7,lr} - 0x01003c46: b081 .. SUB sp,sp,#4 - 0x01003c48: 4604 .F MOV r4,r0 - 0x01003c4a: 460d .F MOV r5,r1 - 0x01003c4c: 4616 .F MOV r6,r2 - 0x01003c4e: 2c00 ., CMP r4,#0 - 0x01003c50: d105 .. BNE 0x1003c5e ; rt_device_read + 26 - 0x01003c52: 22ff ." MOVS r2,#0xff - 0x01003c54: 3235 52 ADDS r2,r2,#0x35 - 0x01003c56: 4914 .I LDR r1,[pc,#80] ; [0x1003ca8] = 0x100764e - 0x01003c58: a014 .. ADR r0,{pc}+0x54 ; 0x1003cac - 0x01003c5a: f7fffcd1 .... BL rt_assert_handler ; 0x1003600 - 0x01003c5e: 4620 F MOV r0,r4 - 0x01003c60: f001f904 .... BL rt_object_get_type ; 0x1004e6c - 0x01003c64: 2809 .( CMP r0,#9 - 0x01003c66: d005 .. BEQ 0x1003c74 ; rt_device_read + 48 - 0x01003c68: 22ff ." MOVS r2,#0xff - 0x01003c6a: 3236 62 ADDS r2,r2,#0x36 - 0x01003c6c: 490e .I LDR r1,[pc,#56] ; [0x1003ca8] = 0x100764e - 0x01003c6e: a013 .. ADR r0,{pc}+0x4e ; 0x1003cbc - 0x01003c70: f7fffcc6 .... BL rt_assert_handler ; 0x1003600 - 0x01003c74: 7ea0 .~ LDRB r0,[r4,#0x1a] - 0x01003c76: 2800 .( CMP r0,#0 - 0x01003c78: d105 .. BNE 0x1003c86 ; rt_device_read + 66 - 0x01003c7a: 1e40 @. SUBS r0,r0,#1 - 0x01003c7c: f001fec8 .... BL rt_set_errno ; 0x1005a10 - 0x01003c80: 2000 . MOVS r0,#0 - 0x01003c82: b005 .. ADD sp,sp,#0x14 - 0x01003c84: bdf0 .. POP {r4-r7,pc} - 0x01003c86: 6b20 k LDR r0,[r4,#0x30] - 0x01003c88: 2800 .( CMP r0,#0 - 0x01003c8a: d006 .. BEQ 0x1003c9a ; rt_device_read + 86 - 0x01003c8c: 6b27 'k LDR r7,[r4,#0x30] - 0x01003c8e: 4632 2F MOV r2,r6 - 0x01003c90: 4629 )F MOV r1,r5 - 0x01003c92: 4620 F MOV r0,r4 - 0x01003c94: 9b04 .. LDR r3,[sp,#0x10] - 0x01003c96: 47b8 .G BLX r7 - 0x01003c98: e7f3 .. B 0x1003c82 ; rt_device_read + 62 - 0x01003c9a: 2005 . MOVS r0,#5 - 0x01003c9c: 43c0 .C MVNS r0,r0 - 0x01003c9e: f001feb7 .... BL rt_set_errno ; 0x1005a10 - 0x01003ca2: 2000 . MOVS r0,#0 - 0x01003ca4: e7ed .. B 0x1003c82 ; rt_device_read + 62 - $d - 0x01003ca6: 0000 .. DCW 0 - 0x01003ca8: 0100764e Nv.. DCD 16807502 - 0x01003cac: 20766564 dev DCD 544630116 - 0x01003cb0: 52203d21 != R DCD 1377844513 - 0x01003cb4: 554e5f54 T_NU DCD 1431199572 - 0x01003cb8: 00004c4c LL.. DCD 19532 - 0x01003cbc: 6f5f7472 rt_o DCD 1868526706 - 0x01003cc0: 63656a62 bjec DCD 1667590754 - 0x01003cc4: 65675f74 t_ge DCD 1701273460 - 0x01003cc8: 79745f74 t_ty DCD 2037669748 - 0x01003ccc: 26286570 pe(& DCD 640181616 - 0x01003cd0: 2d766564 dev- DCD 762733924 - 0x01003cd4: 7261703e >par DCD 1918988350 - 0x01003cd8: 29746e65 ent) DCD 695496293 - 0x01003cdc: 203d3d20 == DCD 540884256 - 0x01003ce0: 4f5f5452 RT_O DCD 1331647570 - 0x01003ce4: 63656a62 bjec DCD 1667590754 - 0x01003ce8: 6c435f74 t_Cl DCD 1816354676 - 0x01003cec: 5f737361 ass_ DCD 1601401697 - 0x01003cf0: 69766544 Devi DCD 1769366852 - 0x01003cf4: 00006563 ce.. DCD 25955 - $t - i.rt_device_register - rt_device_register - 0x01003cf8: b570 p. PUSH {r4-r6,lr} - 0x01003cfa: 4604 .F MOV r4,r0 - 0x01003cfc: 460d .F MOV r5,r1 - 0x01003cfe: 4616 .F MOV r6,r2 - 0x01003d00: 2c00 ., CMP r4,#0 - 0x01003d02: d101 .. BNE 0x1003d08 ; rt_device_register + 16 - 0x01003d04: 1e40 @. SUBS r0,r0,#1 - 0x01003d06: bd70 p. POP {r4-r6,pc} - 0x01003d08: 4628 (F MOV r0,r5 - 0x01003d0a: f7fffec3 .... BL rt_device_find ; 0x1003a94 - 0x01003d0e: 2800 .( CMP r0,#0 - 0x01003d10: d002 .. BEQ 0x1003d18 ; rt_device_register + 32 - 0x01003d12: 2000 . MOVS r0,#0 - 0x01003d14: 43c0 .C MVNS r0,r0 - 0x01003d16: e7f6 .. B 0x1003d06 ; rt_device_register + 14 - 0x01003d18: 462a *F MOV r2,r5 - 0x01003d1a: 2109 .! MOVS r1,#9 - 0x01003d1c: 4620 F MOV r0,r4 - 0x01003d1e: f001f8bf .... BL rt_object_init ; 0x1004ea0 - 0x01003d22: 82e6 .. STRH r6,[r4,#0x16] - 0x01003d24: 2000 . MOVS r0,#0 - 0x01003d26: 76a0 .v STRB r0,[r4,#0x1a] - 0x01003d28: 8320 . STRH r0,[r4,#0x18] - 0x01003d2a: bf00 .. NOP - 0x01003d2c: e7eb .. B 0x1003d06 ; rt_device_register + 14 - 0x01003d2e: 0000 .. MOVS r0,r0 - i.rt_device_set_rx_indicate - rt_device_set_rx_indicate - 0x01003d30: b570 p. PUSH {r4-r6,lr} - 0x01003d32: 4604 .F MOV r4,r0 - 0x01003d34: 460d .F MOV r5,r1 - 0x01003d36: 2c00 ., CMP r4,#0 - 0x01003d38: d105 .. BNE 0x1003d46 ; rt_device_set_rx_indicate + 22 - 0x01003d3a: 22ff ." MOVS r2,#0xff - 0x01003d3c: 3297 .2 ADDS r2,r2,#0x97 - 0x01003d3e: 4909 .I LDR r1,[pc,#36] ; [0x1003d64] = 0x100767f - 0x01003d40: a009 .. ADR r0,{pc}+0x28 ; 0x1003d68 - 0x01003d42: f7fffc5d ..]. BL rt_assert_handler ; 0x1003600 - 0x01003d46: 4620 F MOV r0,r4 - 0x01003d48: f001f890 .... BL rt_object_get_type ; 0x1004e6c - 0x01003d4c: 2809 .( CMP r0,#9 - 0x01003d4e: d005 .. BEQ 0x1003d5c ; rt_device_set_rx_indicate + 44 - 0x01003d50: 22ff ." MOVS r2,#0xff - 0x01003d52: 3298 .2 ADDS r2,r2,#0x98 - 0x01003d54: 4903 .I LDR r1,[pc,#12] ; [0x1003d64] = 0x100767f - 0x01003d56: a008 .. ADR r0,{pc}+0x22 ; 0x1003d78 - 0x01003d58: f7fffc52 ..R. BL rt_assert_handler ; 0x1003600 - 0x01003d5c: 61e5 .a STR r5,[r4,#0x1c] - 0x01003d5e: 2000 . MOVS r0,#0 - 0x01003d60: bd70 p. POP {r4-r6,pc} - $d - 0x01003d62: 0000 .. DCW 0 - 0x01003d64: 0100767f .v.. DCD 16807551 - 0x01003d68: 20766564 dev DCD 544630116 - 0x01003d6c: 52203d21 != R DCD 1377844513 - 0x01003d70: 554e5f54 T_NU DCD 1431199572 - 0x01003d74: 00004c4c LL.. DCD 19532 - 0x01003d78: 6f5f7472 rt_o DCD 1868526706 - 0x01003d7c: 63656a62 bjec DCD 1667590754 - 0x01003d80: 65675f74 t_ge DCD 1701273460 - 0x01003d84: 79745f74 t_ty DCD 2037669748 - 0x01003d88: 26286570 pe(& DCD 640181616 - 0x01003d8c: 2d766564 dev- DCD 762733924 - 0x01003d90: 7261703e >par DCD 1918988350 - 0x01003d94: 29746e65 ent) DCD 695496293 - 0x01003d98: 203d3d20 == DCD 540884256 - 0x01003d9c: 4f5f5452 RT_O DCD 1331647570 - 0x01003da0: 63656a62 bjec DCD 1667590754 - 0x01003da4: 6c435f74 t_Cl DCD 1816354676 - 0x01003da8: 5f737361 ass_ DCD 1601401697 - 0x01003dac: 69766544 Devi DCD 1769366852 - 0x01003db0: 00006563 ce.. DCD 25955 - $t - i.rt_device_write - rt_device_write - 0x01003db4: b5ff .. PUSH {r0-r7,lr} - 0x01003db6: b081 .. SUB sp,sp,#4 - 0x01003db8: 4604 .F MOV r4,r0 - 0x01003dba: 460d .F MOV r5,r1 - 0x01003dbc: 4616 .F MOV r6,r2 - 0x01003dbe: 2c00 ., CMP r4,#0 - 0x01003dc0: d105 .. BNE 0x1003dce ; rt_device_write + 26 - 0x01003dc2: 22ff ." MOVS r2,#0xff - 0x01003dc4: 325c \2 ADDS r2,r2,#0x5c - 0x01003dc6: 4914 .I LDR r1,[pc,#80] ; [0x1003e18] = 0x100765d - 0x01003dc8: a014 .. ADR r0,{pc}+0x54 ; 0x1003e1c - 0x01003dca: f7fffc19 .... BL rt_assert_handler ; 0x1003600 - 0x01003dce: 4620 F MOV r0,r4 - 0x01003dd0: f001f84c ..L. BL rt_object_get_type ; 0x1004e6c - 0x01003dd4: 2809 .( CMP r0,#9 - 0x01003dd6: d005 .. BEQ 0x1003de4 ; rt_device_write + 48 - 0x01003dd8: 22ff ." MOVS r2,#0xff - 0x01003dda: 325d ]2 ADDS r2,r2,#0x5d - 0x01003ddc: 490e .I LDR r1,[pc,#56] ; [0x1003e18] = 0x100765d - 0x01003dde: a013 .. ADR r0,{pc}+0x4e ; 0x1003e2c - 0x01003de0: f7fffc0e .... BL rt_assert_handler ; 0x1003600 - 0x01003de4: 7ea0 .~ LDRB r0,[r4,#0x1a] - 0x01003de6: 2800 .( CMP r0,#0 - 0x01003de8: d105 .. BNE 0x1003df6 ; rt_device_write + 66 - 0x01003dea: 1e40 @. SUBS r0,r0,#1 - 0x01003dec: f001fe10 .... BL rt_set_errno ; 0x1005a10 - 0x01003df0: 2000 . MOVS r0,#0 - 0x01003df2: b005 .. ADD sp,sp,#0x14 - 0x01003df4: bdf0 .. POP {r4-r7,pc} - 0x01003df6: 6b60 `k LDR r0,[r4,#0x34] - 0x01003df8: 2800 .( CMP r0,#0 - 0x01003dfa: d006 .. BEQ 0x1003e0a ; rt_device_write + 86 - 0x01003dfc: 6b67 gk LDR r7,[r4,#0x34] - 0x01003dfe: 4632 2F MOV r2,r6 - 0x01003e00: 4629 )F MOV r1,r5 - 0x01003e02: 4620 F MOV r0,r4 - 0x01003e04: 9b04 .. LDR r3,[sp,#0x10] - 0x01003e06: 47b8 .G BLX r7 - 0x01003e08: e7f3 .. B 0x1003df2 ; rt_device_write + 62 - 0x01003e0a: 2005 . MOVS r0,#5 - 0x01003e0c: 43c0 .C MVNS r0,r0 - 0x01003e0e: f001fdff .... BL rt_set_errno ; 0x1005a10 - 0x01003e12: 2000 . MOVS r0,#0 - 0x01003e14: e7ed .. B 0x1003df2 ; rt_device_write + 62 - $d - 0x01003e16: 0000 .. DCW 0 - 0x01003e18: 0100765d ]v.. DCD 16807517 - 0x01003e1c: 20766564 dev DCD 544630116 - 0x01003e20: 52203d21 != R DCD 1377844513 - 0x01003e24: 554e5f54 T_NU DCD 1431199572 - 0x01003e28: 00004c4c LL.. DCD 19532 - 0x01003e2c: 6f5f7472 rt_o DCD 1868526706 - 0x01003e30: 63656a62 bjec DCD 1667590754 - 0x01003e34: 65675f74 t_ge DCD 1701273460 - 0x01003e38: 79745f74 t_ty DCD 2037669748 - 0x01003e3c: 26286570 pe(& DCD 640181616 - 0x01003e40: 2d766564 dev- DCD 762733924 - 0x01003e44: 7261703e >par DCD 1918988350 - 0x01003e48: 29746e65 ent) DCD 695496293 - 0x01003e4c: 203d3d20 == DCD 540884256 - 0x01003e50: 4f5f5452 RT_O DCD 1331647570 - 0x01003e54: 63656a62 bjec DCD 1667590754 - 0x01003e58: 6c435f74 t_Cl DCD 1816354676 - 0x01003e5c: 5f737361 ass_ DCD 1601401697 - 0x01003e60: 69766544 Devi DCD 1769366852 - 0x01003e64: 00006563 ce.. DCD 25955 - $t - i.rt_enter_critical - rt_enter_critical - 0x01003e68: b510 .. PUSH {r4,lr} - 0x01003e6a: f7fcfb29 ..). BL rt_hw_interrupt_disable ; 0x10004c0 - 0x01003e6e: 4604 .F MOV r4,r0 - 0x01003e70: 4804 .H LDR r0,[pc,#16] ; [0x1003e84] = 0x20028 - 0x01003e72: 8800 .. LDRH r0,[r0,#0] - 0x01003e74: 1c40 @. ADDS r0,r0,#1 - 0x01003e76: b200 .. SXTH r0,r0 - 0x01003e78: 4902 .I LDR r1,[pc,#8] ; [0x1003e84] = 0x20028 - 0x01003e7a: 8008 .. STRH r0,[r1,#0] - 0x01003e7c: 4620 F MOV r0,r4 - 0x01003e7e: f7fcfb23 ..#. BL rt_hw_interrupt_enable ; 0x10004c8 - 0x01003e82: bd10 .. POP {r4,pc} - $d - 0x01003e84: 00020028 (... DCD 131112 - $t - i.rt_exit_critical - rt_exit_critical - 0x01003e88: b510 .. PUSH {r4,lr} - 0x01003e8a: f7fcfb19 .... BL rt_hw_interrupt_disable ; 0x10004c0 - 0x01003e8e: 4604 .F MOV r4,r0 - 0x01003e90: 480d .H LDR r0,[pc,#52] ; [0x1003ec8] = 0x20028 - 0x01003e92: 8800 .. LDRH r0,[r0,#0] - 0x01003e94: 1e40 @. SUBS r0,r0,#1 - 0x01003e96: b200 .. SXTH r0,r0 - 0x01003e98: 490b .I LDR r1,[pc,#44] ; [0x1003ec8] = 0x20028 - 0x01003e9a: 8008 .. STRH r0,[r1,#0] - 0x01003e9c: 4608 .F MOV r0,r1 - 0x01003e9e: 2100 .! MOVS r1,#0 - 0x01003ea0: 5e41 A^ LDRSH r1,[r0,r1] - 0x01003ea2: 2900 .) CMP r1,#0 - 0x01003ea4: dc0c .. BGT 0x1003ec0 ; rt_exit_critical + 56 - 0x01003ea6: 2000 . MOVS r0,#0 - 0x01003ea8: 4907 .I LDR r1,[pc,#28] ; [0x1003ec8] = 0x20028 - 0x01003eaa: 8008 .. STRH r0,[r1,#0] - 0x01003eac: 4620 F MOV r0,r4 - 0x01003eae: f7fcfb0b .... BL rt_hw_interrupt_enable ; 0x10004c8 - 0x01003eb2: 4806 .H LDR r0,[pc,#24] ; [0x1003ecc] = 0x2002c - 0x01003eb4: 6800 .h LDR r0,[r0,#0] - 0x01003eb6: 2800 .( CMP r0,#0 - 0x01003eb8: d005 .. BEQ 0x1003ec6 ; rt_exit_critical + 62 - 0x01003eba: f001f8bb .... BL rt_schedule ; 0x1005034 - 0x01003ebe: e002 .. B 0x1003ec6 ; rt_exit_critical + 62 - 0x01003ec0: 4620 F MOV r0,r4 - 0x01003ec2: f7fcfb01 .... BL rt_hw_interrupt_enable ; 0x10004c8 - 0x01003ec6: bd10 .. POP {r4,pc} - $d - 0x01003ec8: 00020028 (... DCD 131112 - 0x01003ecc: 0002002c ,... DCD 131116 - $t - i.rt_free - rt_free - 0x01003ed0: b570 p. PUSH {r4-r6,lr} - 0x01003ed2: 4605 .F MOV r5,r0 - 0x01003ed4: 2d00 .- CMP r5,#0 - 0x01003ed6: d100 .. BNE 0x1003eda ; rt_free + 10 - 0x01003ed8: bd70 p. POP {r4-r6,pc} - 0x01003eda: bf00 .. NOP - 0x01003edc: f7fcfaf0 .... BL rt_hw_interrupt_disable ; 0x10004c0 - 0x01003ee0: 4606 .F MOV r6,r0 - 0x01003ee2: f000facb .... BL rt_interrupt_get_nest ; 0x100447c - 0x01003ee6: 2800 .( CMP r0,#0 - 0x01003ee8: d008 .. BEQ 0x1003efc ; rt_free + 44 - 0x01003eea: 4942 BI LDR r1,[pc,#264] ; [0x1003ff4] = 0x1007c23 - 0x01003eec: a042 B. ADR r0,{pc}+0x10c ; 0x1003ff8 - 0x01003eee: f000faef .... BL rt_kprintf ; 0x10044d0 - 0x01003ef2: 4a4b KJ LDR r2,[pc,#300] ; [0x1004020] = 0x22f - 0x01003ef4: 493f ?I LDR r1,[pc,#252] ; [0x1003ff4] = 0x1007c23 - 0x01003ef6: a04b K. ADR r0,{pc}+0x12e ; 0x1004024 - 0x01003ef8: f7fffb82 .... BL rt_assert_handler ; 0x1003600 - 0x01003efc: 4630 0F MOV r0,r6 - 0x01003efe: f7fcfae3 .... BL rt_hw_interrupt_enable ; 0x10004c8 - 0x01003f02: bf00 .. NOP - 0x01003f04: 07a8 .. LSLS r0,r5,#30 - 0x01003f06: 0f80 .. LSRS r0,r0,#30 - 0x01003f08: 2800 .( CMP r0,#0 - 0x01003f0a: d005 .. BEQ 0x1003f18 ; rt_free + 72 - 0x01003f0c: 4a44 DJ LDR r2,[pc,#272] ; [0x1004020] = 0x22f - 0x01003f0e: 1c92 .. ADDS r2,r2,#2 - 0x01003f10: 4938 8I LDR r1,[pc,#224] ; [0x1003ff4] = 0x1007c23 - 0x01003f12: a045 E. ADR r0,{pc}+0x116 ; 0x1004028 - 0x01003f14: f7fffb74 ..t. BL rt_assert_handler ; 0x1003600 - 0x01003f18: 484f OH LDR r0,[pc,#316] ; [0x1004058] = 0x2013c - 0x01003f1a: 6800 .h LDR r0,[r0,#0] - 0x01003f1c: 4285 .B CMP r5,r0 - 0x01003f1e: d303 .. BCC 0x1003f28 ; rt_free + 88 - 0x01003f20: 484e NH LDR r0,[pc,#312] ; [0x100405c] = 0x20140 - 0x01003f22: 6800 .h LDR r0,[r0,#0] - 0x01003f24: 4285 .B CMP r5,r0 - 0x01003f26: d305 .. BCC 0x1003f34 ; rt_free + 100 - 0x01003f28: 4a3d =J LDR r2,[pc,#244] ; [0x1004020] = 0x22f - 0x01003f2a: 1cd2 .. ADDS r2,r2,#3 - 0x01003f2c: 4931 1I LDR r1,[pc,#196] ; [0x1003ff4] = 0x1007c23 - 0x01003f2e: 484c LH LDR r0,[pc,#304] ; [0x1004060] = 0x1007fe0 - 0x01003f30: f7fffb66 ..f. BL rt_assert_handler ; 0x1003600 - 0x01003f34: bf00 .. NOP - 0x01003f36: 484b KH LDR r0,[pc,#300] ; [0x1004064] = 0x20138 - 0x01003f38: 6800 .h LDR r0,[r0,#0] - 0x01003f3a: 2800 .( CMP r0,#0 - 0x01003f3c: d003 .. BEQ 0x1003f46 ; rt_free + 118 - 0x01003f3e: 4628 (F MOV r0,r5 - 0x01003f40: 4948 HI LDR r1,[pc,#288] ; [0x1004064] = 0x20138 - 0x01003f42: 6809 .h LDR r1,[r1,#0] - 0x01003f44: 4788 .G BLX r1 - 0x01003f46: bf00 .. NOP - 0x01003f48: 4843 CH LDR r0,[pc,#268] ; [0x1004058] = 0x2013c - 0x01003f4a: 6800 .h LDR r0,[r0,#0] - 0x01003f4c: 4285 .B CMP r5,r0 - 0x01003f4e: d303 .. BCC 0x1003f58 ; rt_free + 136 - 0x01003f50: 4842 BH LDR r0,[pc,#264] ; [0x100405c] = 0x20140 - 0x01003f52: 6800 .h LDR r0,[r0,#0] - 0x01003f54: 4285 .B CMP r5,r0 - 0x01003f56: d302 .. BCC 0x1003f5e ; rt_free + 142 - 0x01003f58: bf00 .. NOP - 0x01003f5a: bf00 .. NOP - 0x01003f5c: e7bc .. B 0x1003ed8 ; rt_free + 8 - 0x01003f5e: 462c ,F MOV r4,r5 - 0x01003f60: 3c0c .< SUBS r4,r4,#0xc - 0x01003f62: bf00 .. NOP - 0x01003f64: bf00 .. NOP - 0x01003f66: 2100 .! MOVS r1,#0 - 0x01003f68: 43c9 .C MVNS r1,r1 - 0x01003f6a: 483f ?H LDR r0,[pc,#252] ; [0x1004068] = 0x20584 - 0x01003f6c: f001fa38 ..8. BL rt_sem_take ; 0x10053e0 - 0x01003f70: 8860 `. LDRH r0,[r4,#2] - 0x01003f72: 2800 .( CMP r0,#0 - 0x01003f74: d004 .. BEQ 0x1003f80 ; rt_free + 176 - 0x01003f76: 8820 . LDRH r0,[r4,#0] - 0x01003f78: 21f5 .! MOVS r1,#0xf5 - 0x01003f7a: 0149 I. LSLS r1,r1,#5 - 0x01003f7c: 4288 .B CMP r0,r1 - 0x01003f7e: d008 .. BEQ 0x1003f92 ; rt_free + 194 - 0x01003f80: a03a :. ADR r0,{pc}+0xec ; 0x100406c - 0x01003f82: f000faa5 .... BL rt_kprintf ; 0x10044d0 - 0x01003f86: 8823 #. LDRH r3,[r4,#0] - 0x01003f88: 8862 b. LDRH r2,[r4,#2] - 0x01003f8a: 4621 !F MOV r1,r4 - 0x01003f8c: a03e >. ADR r0,{pc}+0xfc ; 0x1004088 - 0x01003f8e: f000fa9f .... BL rt_kprintf ; 0x10044d0 - 0x01003f92: 8860 `. LDRH r0,[r4,#2] - 0x01003f94: 2800 .( CMP r0,#0 - 0x01003f96: d105 .. BNE 0x1003fa4 ; rt_free + 212 - 0x01003f98: 4a21 !J LDR r2,[pc,#132] ; [0x1004020] = 0x22f - 0x01003f9a: 3222 "2 ADDS r2,r2,#0x22 - 0x01003f9c: 4915 .I LDR r1,[pc,#84] ; [0x1003ff4] = 0x1007c23 - 0x01003f9e: a046 F. ADR r0,{pc}+0x11a ; 0x10040b8 - 0x01003fa0: f7fffb2e .... BL rt_assert_handler ; 0x1003600 - 0x01003fa4: 8820 . LDRH r0,[r4,#0] - 0x01003fa6: 21f5 .! MOVS r1,#0xf5 - 0x01003fa8: 0149 I. LSLS r1,r1,#5 - 0x01003faa: 4288 .B CMP r0,r1 - 0x01003fac: d005 .. BEQ 0x1003fba ; rt_free + 234 - 0x01003fae: 4a1c .J LDR r2,[pc,#112] ; [0x1004020] = 0x22f - 0x01003fb0: 3223 #2 ADDS r2,r2,#0x23 - 0x01003fb2: 4910 .I LDR r1,[pc,#64] ; [0x1003ff4] = 0x1007c23 - 0x01003fb4: a043 C. ADR r0,{pc}+0x110 ; 0x10040c4 - 0x01003fb6: f7fffb23 ..#. BL rt_assert_handler ; 0x1003600 - 0x01003fba: 2000 . MOVS r0,#0 - 0x01003fbc: 8060 `. STRH r0,[r4,#2] - 0x01003fbe: 20f5 . MOVS r0,#0xf5 - 0x01003fc0: 0140 @. LSLS r0,r0,#5 - 0x01003fc2: 8020 . STRH r0,[r4,#0] - 0x01003fc4: 4846 FH LDR r0,[pc,#280] ; [0x10040e0] = 0x20144 - 0x01003fc6: 6800 .h LDR r0,[r0,#0] - 0x01003fc8: 4284 .B CMP r4,r0 - 0x01003fca: d201 .. BCS 0x1003fd0 ; rt_free + 256 - 0x01003fcc: 4844 DH LDR r0,[pc,#272] ; [0x10040e0] = 0x20144 - 0x01003fce: 6004 .` STR r4,[r0,#0] - 0x01003fd0: 4921 !I LDR r1,[pc,#132] ; [0x1004058] = 0x2013c - 0x01003fd2: 6860 `h LDR r0,[r4,#4] - 0x01003fd4: 6809 .h LDR r1,[r1,#0] - 0x01003fd6: 1a61 a. SUBS r1,r4,r1 - 0x01003fd8: 1a40 @. SUBS r0,r0,r1 - 0x01003fda: 4942 BI LDR r1,[pc,#264] ; [0x10040e4] = 0x2014c - 0x01003fdc: 6809 .h LDR r1,[r1,#0] - 0x01003fde: 1a08 .. SUBS r0,r1,r0 - 0x01003fe0: 4940 @I LDR r1,[pc,#256] ; [0x10040e4] = 0x2014c - 0x01003fe2: 6008 .` STR r0,[r1,#0] - 0x01003fe4: 4620 F MOV r0,r4 - 0x01003fe6: f7fff98f .... BL plug_holes ; 0x1003308 - 0x01003fea: 481f .H LDR r0,[pc,#124] ; [0x1004068] = 0x20584 - 0x01003fec: f001f99e .... BL rt_sem_release ; 0x100532c - 0x01003ff0: bf00 .. NOP - 0x01003ff2: e771 q. B 0x1003ed8 ; rt_free + 8 - $d - 0x01003ff4: 01007c23 #|.. DCD 16808995 - 0x01003ff8: 636e7546 Func DCD 1668183366 - 0x01003ffc: 6e6f6974 tion DCD 1852795252 - 0x01004000: 5d73255b [%s] DCD 1567827291 - 0x01004004: 61687320 sha DCD 1634235168 - 0x01004008: 6e206c6c ll n DCD 1847618668 - 0x0100400c: 6220746f ot b DCD 1646294127 - 0x01004010: 73752065 e us DCD 1937055845 - 0x01004014: 69206465 ed i DCD 1763730533 - 0x01004018: 5349206e n IS DCD 1397301358 - 0x0100401c: 00000a52 R... DCD 2642 - 0x01004020: 0000022f /... DCD 559 - 0x01004024: 00000030 0... DCD 48 - 0x01004028: 72282828 (((r DCD 1915234344 - 0x0100402c: 62755f74 t_ub DCD 1651859316 - 0x01004030: 5f657361 ase_ DCD 1600484193 - 0x01004034: 6d722974 t)rm DCD 1836198260 - 0x01004038: 20296d65 em) DCD 539585893 - 0x0100403c: 52282026 & (R DCD 1378361382 - 0x01004040: 4c415f54 T_AL DCD 1279352660 - 0x01004044: 5f4e4749 IGN_ DCD 1598965577 - 0x01004048: 455a4953 SIZE DCD 1163544915 - 0x0100404c: 31202d20 - 1 DCD 824192288 - 0x01004050: 3d202929 )) = DCD 1025517865 - 0x01004054: 0030203d = 0. DCD 3153981 - 0x01004058: 0002013c <... DCD 131388 - 0x0100405c: 00020140 @... DCD 131392 - 0x01004060: 01007fe0 .... DCD 16809952 - 0x01004064: 00020138 8... DCD 131384 - 0x01004068: 00020584 .... DCD 132484 - 0x0100406c: 66206f74 to f DCD 1713401716 - 0x01004070: 20656572 ree DCD 543516018 - 0x01004074: 61622061 a ba DCD 1633820769 - 0x01004078: 61642064 d da DCD 1633951844 - 0x0100407c: 62206174 ta b DCD 1646289268 - 0x01004080: 6b636f6c lock DCD 1801678700 - 0x01004084: 00000a3a :... DCD 2618 - 0x01004088: 3a6d656d mem: DCD 980247917 - 0x0100408c: 25783020 0x% DCD 628633632 - 0x01004090: 2c783830 08x, DCD 746076208 - 0x01004094: 65737520 use DCD 1702065440 - 0x01004098: 6c662064 d fl DCD 1818632292 - 0x0100409c: 203a6761 ag: DCD 540698465 - 0x010040a0: 202c6425 %d, DCD 539780133 - 0x010040a4: 6967616d magi DCD 1768382829 - 0x010040a8: 6f632063 c co DCD 1868767331 - 0x010040ac: 203a6564 de: DCD 540697956 - 0x010040b0: 30257830 0x%0 DCD 807761968 - 0x010040b4: 000a7834 4x.. DCD 686132 - 0x010040b8: 2d6d656d mem- DCD 762144109 - 0x010040bc: 6573753e >use DCD 1702065470 - 0x010040c0: 00000064 d... DCD 100 - 0x010040c4: 2d6d656d mem- DCD 762144109 - 0x010040c8: 67616d3e >mag DCD 1734438206 - 0x010040cc: 3d206369 ic = DCD 1025532777 - 0x010040d0: 4548203d = HE DCD 1162354749 - 0x010040d4: 4d5f5041 AP_M DCD 1298092097 - 0x010040d8: 43494741 AGIC DCD 1128875841 - 0x010040dc: 00000000 .... DCD 0 - 0x010040e0: 00020144 D... DCD 131396 - 0x010040e4: 0002014c L... DCD 131404 - $t - i.rt_hw_board_init - rt_hw_board_init - 0x010040e8: b510 .. PUSH {r4,lr} - 0x010040ea: f7fdfb49 ..I. BL bsp_clock_config ; 0x1001780 - 0x010040ee: 2103 .! MOVS r1,#3 - 0x010040f0: 0409 .. LSLS r1,r1,#16 - 0x010040f2: 4805 .H LDR r0,[pc,#20] ; [0x1004108] = 0x20f10 - 0x010040f4: f001fd3e ..>. BL rt_system_heap_init ; 0x1005b74 - 0x010040f8: f000f976 ..v. BL rt_hw_uart_init ; 0x10043e8 - 0x010040fc: a003 .. ADR r0,{pc}+0x10 ; 0x100410c - 0x010040fe: f7fffbed .... BL rt_console_set_device ; 0x10038dc - 0x01004102: f7fffbc9 .... BL rt_components_board_init ; 0x1003898 - 0x01004106: bd10 .. POP {r4,pc} - $d - 0x01004108: 00020f10 .... DCD 134928 - 0x0100410c: 74726175 uart DCD 1953653109 - 0x01004110: 00000030 0... DCD 48 - $t - i.rt_hw_console_output - rt_hw_console_output - 0x01004114: 4770 pG BX lr - 0x01004116: 0000 .. MOVS r0,r0 - i.rt_hw_hard_fault_exception - rt_hw_hard_fault_exception - 0x01004118: 4604 .F MOV r4,r0 - 0x0100411a: a014 .. ADR r0,{pc}+0x52 ; 0x100416c - 0x0100411c: 69e1 .i LDR r1,[r4,#0x1c] - 0x0100411e: f000f9d7 .... BL rt_kprintf ; 0x10044d0 - 0x01004122: a016 .. ADR r0,{pc}+0x5a ; 0x100417c - 0x01004124: 69a1 .i LDR r1,[r4,#0x18] - 0x01004126: f000f9d3 .... BL rt_kprintf ; 0x10044d0 - 0x0100412a: a018 .. ADR r0,{pc}+0x62 ; 0x100418c - 0x0100412c: 6961 ai LDR r1,[r4,#0x14] - 0x0100412e: f000f9cf .... BL rt_kprintf ; 0x10044d0 - 0x01004132: a01a .. ADR r0,{pc}+0x6a ; 0x100419c - 0x01004134: 6921 !i LDR r1,[r4,#0x10] - 0x01004136: f000f9cb .... BL rt_kprintf ; 0x10044d0 - 0x0100413a: a01c .. ADR r0,{pc}+0x72 ; 0x10041ac - 0x0100413c: 68e1 .h LDR r1,[r4,#0xc] - 0x0100413e: f000f9c7 .... BL rt_kprintf ; 0x10044d0 - 0x01004142: a01e .. ADR r0,{pc}+0x7a ; 0x10041bc - 0x01004144: 68a1 .h LDR r1,[r4,#8] - 0x01004146: f000f9c3 .... BL rt_kprintf ; 0x10044d0 - 0x0100414a: a020 . ADR r0,{pc}+0x82 ; 0x10041cc - 0x0100414c: 6861 ah LDR r1,[r4,#4] - 0x0100414e: f000f9bf .... BL rt_kprintf ; 0x10044d0 - 0x01004152: a022 ". ADR r0,{pc}+0x8a ; 0x10041dc - 0x01004154: 6821 !h LDR r1,[r4,#0] - 0x01004156: f000f9bb .... BL rt_kprintf ; 0x10044d0 - 0x0100415a: 4824 $H LDR r0,[pc,#144] ; [0x10041ec] = 0x2002c - 0x0100415c: 6801 .h LDR r1,[r0,#0] - 0x0100415e: a024 $. ADR r0,{pc}+0x92 ; 0x10041f0 - 0x01004160: f000f9b6 .... BL rt_kprintf ; 0x10044d0 - 0x01004164: f7fefd74 ..t. BL list_thread ; 0x1002c50 - 0x01004168: bf00 .. NOP - 0x0100416a: e7fe .. B 0x100416a ; rt_hw_hard_fault_exception + 82 - $d - 0x0100416c: 3a727370 psr: DCD 980579184 - 0x01004170: 25783020 0x% DCD 628633632 - 0x01004174: 0a783830 08x. DCD 175650864 - 0x01004178: 00000000 .... DCD 0 - 0x0100417c: 3a637020 pc: DCD 979595296 - 0x01004180: 25783020 0x% DCD 628633632 - 0x01004184: 0a783830 08x. DCD 175650864 - 0x01004188: 00000000 .... DCD 0 - 0x0100418c: 3a726c20 lr: DCD 980577312 - 0x01004190: 25783020 0x% DCD 628633632 - 0x01004194: 0a783830 08x. DCD 175650864 - 0x01004198: 00000000 .... DCD 0 - 0x0100419c: 3a323172 r12: DCD 976367986 - 0x010041a0: 25783020 0x% DCD 628633632 - 0x010041a4: 0a783830 08x. DCD 175650864 - 0x010041a8: 00000000 .... DCD 0 - 0x010041ac: 3a333072 r03: DCD 976433266 - 0x010041b0: 25783020 0x% DCD 628633632 - 0x010041b4: 0a783830 08x. DCD 175650864 - 0x010041b8: 00000000 .... DCD 0 - 0x010041bc: 3a323072 r02: DCD 976367730 - 0x010041c0: 25783020 0x% DCD 628633632 - 0x010041c4: 0a783830 08x. DCD 175650864 - 0x010041c8: 00000000 .... DCD 0 - 0x010041cc: 3a313072 r01: DCD 976302194 - 0x010041d0: 25783020 0x% DCD 628633632 - 0x010041d4: 0a783830 08x. DCD 175650864 - 0x010041d8: 00000000 .... DCD 0 - 0x010041dc: 3a303072 r00: DCD 976236658 - 0x010041e0: 25783020 0x% DCD 628633632 - 0x010041e4: 0a783830 08x. DCD 175650864 - 0x010041e8: 00000000 .... DCD 0 - 0x010041ec: 0002002c ,... DCD 131116 - 0x010041f0: 64726168 hard DCD 1685217640 - 0x010041f4: 75616620 fau DCD 1969317408 - 0x010041f8: 6f20746c lt o DCD 1864397932 - 0x010041fc: 6874206e n th DCD 1752440942 - 0x01004200: 64616572 read DCD 1684104562 - 0x01004204: 7325203a : %s DCD 1931812922 - 0x01004208: 0000000a .... DCD 10 - $t - i.rt_hw_pin_init - rt_hw_pin_init - 0x0100420c: b510 .. PUSH {r4,lr} - 0x0100420e: 2200 ." MOVS r2,#0 - 0x01004210: 4903 .I LDR r1,[pc,#12] ; [0x1004220] = 0x1007404 - 0x01004212: a004 .. ADR r0,{pc}+0x12 ; 0x1004224 - 0x01004214: f7fffcf2 .... BL rt_device_pin_register ; 0x1003bfc - 0x01004218: 4604 .F MOV r4,r0 - 0x0100421a: 4620 F MOV r0,r4 - 0x0100421c: bd10 .. POP {r4,pc} - $d - 0x0100421e: 0000 .. DCW 0 - 0x01004220: 01007404 .t.. DCD 16806916 - 0x01004224: 006e6970 pin. DCD 7235952 - $t - i.rt_hw_serial_isr - rt_hw_serial_isr - 0x01004228: b5fe .. PUSH {r1-r7,lr} - 0x0100422a: 4605 .F MOV r5,r0 - 0x0100422c: 460e .F MOV r6,r1 - 0x0100422e: b2f0 .. UXTB r0,r6 - 0x01004230: 2801 .( CMP r0,#1 - 0x01004232: d002 .. BEQ 0x100423a ; rt_hw_serial_isr + 18 - 0x01004234: 2802 .( CMP r0,#2 - 0x01004236: d164 d. BNE 0x1004302 ; rt_hw_serial_isr + 218 - 0x01004238: e05e ^. B 0x10042f8 ; rt_hw_serial_isr + 208 - 0x0100423a: 2700 .' MOVS r7,#0 - 0x0100423c: 43ff .C MVNS r7,r7 - 0x0100423e: 6cec .l LDR r4,[r5,#0x4c] - 0x01004240: 2c00 ., CMP r4,#0 - 0x01004242: d104 .. BNE 0x100424e ; rt_hw_serial_isr + 38 - 0x01004244: 4a30 0J LDR r2,[pc,#192] ; [0x1004308] = 0x50e - 0x01004246: 4931 1I LDR r1,[pc,#196] ; [0x100430c] = 0x10073b7 - 0x01004248: a031 1. ADR r0,{pc}+0xc8 ; 0x1004310 - 0x0100424a: f7fff9d9 .... BL rt_assert_handler ; 0x1003600 - 0x0100424e: e02f /. B 0x10042b0 ; rt_hw_serial_isr + 136 - 0x01004250: 6c28 (l LDR r0,[r5,#0x40] - 0x01004252: 68c1 .h LDR r1,[r0,#0xc] - 0x01004254: 4628 (F MOV r0,r5 - 0x01004256: 4788 .G BLX r1 - 0x01004258: 4607 .F MOV r7,r0 - 0x0100425a: 1c78 x. ADDS r0,r7,#1 - 0x0100425c: 2800 .( CMP r0,#0 - 0x0100425e: d100 .. BNE 0x1004262 ; rt_hw_serial_isr + 58 - 0x01004260: e027 '. B 0x10042b2 ; rt_hw_serial_isr + 138 - 0x01004262: f7fcf92d ..-. BL rt_hw_interrupt_disable ; 0x10004c0 - 0x01004266: 9001 .. STR r0,[sp,#4] - 0x01004268: 88a2 .. LDRH r2,[r4,#4] - 0x0100426a: 6821 !h LDR r1,[r4,#0] - 0x0100426c: 548f .T STRB r7,[r1,r2] - 0x0100426e: 88a0 .. LDRH r0,[r4,#4] - 0x01004270: 1c40 @. ADDS r0,r0,#1 - 0x01004272: 80a0 .. STRH r0,[r4,#4] - 0x01004274: 88a1 .. LDRH r1,[r4,#4] - 0x01004276: 6ca8 .l LDR r0,[r5,#0x48] - 0x01004278: 0180 .. LSLS r0,r0,#6 - 0x0100427a: 0c00 .. LSRS r0,r0,#16 - 0x0100427c: 4281 .B CMP r1,r0 - 0x0100427e: db01 .. BLT 0x1004284 ; rt_hw_serial_isr + 92 - 0x01004280: 2000 . MOVS r0,#0 - 0x01004282: 80a0 .. STRH r0,[r4,#4] - 0x01004284: 88a0 .. LDRH r0,[r4,#4] - 0x01004286: 88e1 .. LDRH r1,[r4,#6] - 0x01004288: 4288 .B CMP r0,r1 - 0x0100428a: d10e .. BNE 0x10042aa ; rt_hw_serial_isr + 130 - 0x0100428c: 88e0 .. LDRH r0,[r4,#6] - 0x0100428e: 1c40 @. ADDS r0,r0,#1 - 0x01004290: 80e0 .. STRH r0,[r4,#6] - 0x01004292: 2001 . MOVS r0,#1 - 0x01004294: 60a0 .` STR r0,[r4,#8] - 0x01004296: 88e1 .. LDRH r1,[r4,#6] - 0x01004298: 6ca8 .l LDR r0,[r5,#0x48] - 0x0100429a: 0180 .. LSLS r0,r0,#6 - 0x0100429c: 0c00 .. LSRS r0,r0,#16 - 0x0100429e: 4281 .B CMP r1,r0 - 0x010042a0: db01 .. BLT 0x10042a6 ; rt_hw_serial_isr + 126 - 0x010042a2: 2000 . MOVS r0,#0 - 0x010042a4: 80e0 .. STRH r0,[r4,#6] - 0x010042a6: f7fdf871 ..q. BL _serial_check_buffer_size ; 0x100138c - 0x010042aa: 9801 .. LDR r0,[sp,#4] - 0x010042ac: f7fcf90c .... BL rt_hw_interrupt_enable ; 0x10004c8 - 0x010042b0: e7ce .. B 0x1004250 ; rt_hw_serial_isr + 40 - 0x010042b2: bf00 .. NOP - 0x010042b4: 69e8 .i LDR r0,[r5,#0x1c] - 0x010042b6: 2800 .( CMP r0,#0 - 0x010042b8: d01d .. BEQ 0x10042f6 ; rt_hw_serial_isr + 206 - 0x010042ba: f7fcf901 .... BL rt_hw_interrupt_disable ; 0x10004c0 - 0x010042be: 9001 .. STR r0,[sp,#4] - 0x010042c0: 88a0 .. LDRH r0,[r4,#4] - 0x010042c2: 88e1 .. LDRH r1,[r4,#6] - 0x010042c4: 4288 .B CMP r0,r1 - 0x010042c6: db03 .. BLT 0x10042d0 ; rt_hw_serial_isr + 168 - 0x010042c8: 88a0 .. LDRH r0,[r4,#4] - 0x010042ca: 88e1 .. LDRH r1,[r4,#6] - 0x010042cc: 1a40 @. SUBS r0,r0,r1 - 0x010042ce: e006 .. B 0x10042de ; rt_hw_serial_isr + 182 - 0x010042d0: 88e0 .. LDRH r0,[r4,#6] - 0x010042d2: 88a1 .. LDRH r1,[r4,#4] - 0x010042d4: 1a41 A. SUBS r1,r0,r1 - 0x010042d6: 6ca8 .l LDR r0,[r5,#0x48] - 0x010042d8: 0180 .. LSLS r0,r0,#6 - 0x010042da: 0c00 .. LSRS r0,r0,#16 - 0x010042dc: 1a40 @. SUBS r0,r0,r1 - 0x010042de: 9000 .. STR r0,[sp,#0] - 0x010042e0: 9801 .. LDR r0,[sp,#4] - 0x010042e2: f7fcf8f1 .... BL rt_hw_interrupt_enable ; 0x10004c8 - 0x010042e6: 9800 .. LDR r0,[sp,#0] - 0x010042e8: 2800 .( CMP r0,#0 - 0x010042ea: d003 .. BEQ 0x10042f4 ; rt_hw_serial_isr + 204 - 0x010042ec: 69ea .i LDR r2,[r5,#0x1c] - 0x010042ee: 4628 (F MOV r0,r5 - 0x010042f0: 9900 .. LDR r1,[sp,#0] - 0x010042f2: 4790 .G BLX r2 - 0x010042f4: bf00 .. NOP - 0x010042f6: e004 .. B 0x1004302 ; rt_hw_serial_isr + 218 - 0x010042f8: 6d2c ,m LDR r4,[r5,#0x50] - 0x010042fa: 4620 F MOV r0,r4 - 0x010042fc: f7fff9d0 .... BL rt_completion_done ; 0x10036a0 - 0x01004300: bf00 .. NOP - 0x01004302: bf00 .. NOP - 0x01004304: bdfe .. POP {r1-r7,pc} - $d - 0x01004306: 0000 .. DCW 0 - 0x01004308: 0000050e .... DCD 1294 - 0x0100430c: 010073b7 .s.. DCD 16806839 - 0x01004310: 665f7872 rx_f DCD 1717532786 - 0x01004314: 206f6669 ifo DCD 544171625 - 0x01004318: 52203d21 != R DCD 1377844513 - 0x0100431c: 554e5f54 T_NU DCD 1431199572 - 0x01004320: 00004c4c LL.. DCD 19532 - $t - i.rt_hw_serial_register - rt_hw_serial_register - 0x01004324: b5ff .. PUSH {r0-r7,lr} - 0x01004326: b081 .. SUB sp,sp,#4 - 0x01004328: 4604 .F MOV r4,r0 - 0x0100432a: 4616 .F MOV r6,r2 - 0x0100432c: 461f .F MOV r7,r3 - 0x0100432e: 2c00 ., CMP r4,#0 - 0x01004330: d104 .. BNE 0x100433c ; rt_hw_serial_register + 24 - 0x01004332: 4a10 .J LDR r2,[pc,#64] ; [0x1004374] = 0x4e2 - 0x01004334: 4910 .I LDR r1,[pc,#64] ; [0x1004378] = 0x10073a1 - 0x01004336: a011 .. ADR r0,{pc}+0x46 ; 0x100437c - 0x01004338: f7fff962 ..b. BL rt_assert_handler ; 0x1003600 - 0x0100433c: 4625 %F MOV r5,r4 - 0x0100433e: 2000 . MOVS r0,#0 - 0x01004340: 462c ,F MOV r4,r5 - 0x01004342: 7528 (u STRB r0,[r5,#0x14] - 0x01004344: 61e8 .a STR r0,[r5,#0x1c] - 0x01004346: 6228 (b STR r0,[r5,#0x20] - 0x01004348: 4811 .H LDR r0,[pc,#68] ; [0x1004390] = 0x1005735 - 0x0100434a: 6268 hb STR r0,[r5,#0x24] - 0x0100434c: 4811 .H LDR r0,[pc,#68] ; [0x1004394] = 0x1005785 - 0x0100434e: 62a8 .b STR r0,[r5,#0x28] - 0x01004350: 4811 .H LDR r0,[pc,#68] ; [0x1004398] = 0x1005591 - 0x01004352: 62e8 .b STR r0,[r5,#0x2c] - 0x01004354: 4811 .H LDR r0,[pc,#68] ; [0x100439c] = 0x1005959 - 0x01004356: 6328 (c STR r0,[r5,#0x30] - 0x01004358: 4811 .H LDR r0,[pc,#68] ; [0x10043a0] = 0x10059b5 - 0x0100435a: 6368 hc STR r0,[r5,#0x34] - 0x0100435c: 4811 .H LDR r0,[pc,#68] ; [0x10043a4] = 0x1005689 - 0x0100435e: 63a8 .c STR r0,[r5,#0x38] - 0x01004360: 63ef .c STR r7,[r5,#0x3c] - 0x01004362: b2b2 .. UXTH r2,r6 - 0x01004364: 4628 (F MOV r0,r5 - 0x01004366: 9902 .. LDR r1,[sp,#8] - 0x01004368: f7fffcc6 .... BL rt_device_register ; 0x1003cf8 - 0x0100436c: 9000 .. STR r0,[sp,#0] - 0x0100436e: 9800 .. LDR r0,[sp,#0] - 0x01004370: b005 .. ADD sp,sp,#0x14 - 0x01004372: bdf0 .. POP {r4-r7,pc} - $d - 0x01004374: 000004e2 .... DCD 1250 - 0x01004378: 010073a1 .s.. DCD 16806817 - 0x0100437c: 69726573 seri DCD 1769104755 - 0x01004380: 21206c61 al ! DCD 555773025 - 0x01004384: 5452203d = RT DCD 1414668349 - 0x01004388: 4c554e5f _NUL DCD 1280659039 - 0x0100438c: 0000004c L... DCD 76 - 0x01004390: 01005735 5W.. DCD 16799541 - 0x01004394: 01005785 .W.. DCD 16799621 - 0x01004398: 01005591 .U.. DCD 16799121 - 0x0100439c: 01005959 YY.. DCD 16800089 - 0x010043a0: 010059b5 .Y.. DCD 16800181 - 0x010043a4: 01005689 .V.. DCD 16799369 - $t - i.rt_hw_stack_init - rt_hw_stack_init - 0x010043a8: b5ff .. PUSH {r0-r7,lr} - 0x010043aa: 460c .F MOV r4,r1 - 0x010043ac: 1d10 .. ADDS r0,r2,#4 - 0x010043ae: 08c0 .. LSRS r0,r0,#3 - 0x010043b0: 00c0 .. LSLS r0,r0,#3 - 0x010043b2: 3840 @8 SUBS r0,r0,#0x40 - 0x010043b4: 4601 .F MOV r1,r0 - 0x010043b6: 2500 .% MOVS r5,#0 - 0x010043b8: e003 .. B 0x10043c2 ; rt_hw_stack_init + 26 - 0x010043ba: 4e0a .N LDR r6,[pc,#40] ; [0x10043e4] = 0xdeadbeef - 0x010043bc: 00af .. LSLS r7,r5,#2 - 0x010043be: 51ce .Q STR r6,[r1,r7] - 0x010043c0: 1c6d m. ADDS r5,r5,#1 - 0x010043c2: 2d10 .- CMP r5,#0x10 - 0x010043c4: d3f9 .. BCC 0x10043ba ; rt_hw_stack_init + 18 - 0x010043c6: 620c .b STR r4,[r1,#0x20] - 0x010043c8: 2600 .& MOVS r6,#0 - 0x010043ca: 624e Nb STR r6,[r1,#0x24] - 0x010043cc: 628e .b STR r6,[r1,#0x28] - 0x010043ce: 62ce .b STR r6,[r1,#0x2c] - 0x010043d0: 630e .c STR r6,[r1,#0x30] - 0x010043d2: 634b Kc STR r3,[r1,#0x34] - 0x010043d4: 9e00 .. LDR r6,[sp,#0] - 0x010043d6: 638e .c STR r6,[r1,#0x38] - 0x010043d8: 2601 .& MOVS r6,#1 - 0x010043da: 0636 6. LSLS r6,r6,#24 - 0x010043dc: 63ce .c STR r6,[r1,#0x3c] - 0x010043de: b004 .. ADD sp,sp,#0x10 - 0x010043e0: bdf0 .. POP {r4-r7,pc} - $d - 0x010043e2: 0000 .. DCW 0 - 0x010043e4: deadbeef .... DCD 3735928559 - $t - i.rt_hw_uart_init - rt_hw_uart_init - 0x010043e8: b51c .. PUSH {r2-r4,lr} - 0x010043ea: 490f .I LDR r1,[pc,#60] ; [0x1004428] = 0x1007480 - 0x010043ec: c903 .. LDM r1,{r0,r1} - 0x010043ee: 9101 .. STR r1,[sp,#4] - 0x010043f0: 9000 .. STR r0,[sp,#0] - 0x010043f2: 2008 . MOVS r0,#8 - 0x010043f4: 490d .I LDR r1,[pc,#52] ; [0x100442c] = 0xf8700 - 0x010043f6: 7048 Hp STRB r0,[r1,#1] - 0x010043f8: 2009 . MOVS r0,#9 - 0x010043fa: 7008 .p STRB r0,[r1,#0] - 0x010043fc: 4c0c .L LDR r4,[pc,#48] ; [0x1004430] = 0x20010 - 0x010043fe: 2000 . MOVS r0,#0 - 0x01004400: 7020 p STRB r0,[r4,#0] - 0x01004402: 2005 . MOVS r0,#5 - 0x01004404: 7060 `p STRB r0,[r4,#1] - 0x01004406: 480b .H LDR r0,[pc,#44] ; [0x1004434] = 0x1007420 - 0x01004408: 490b .I LDR r1,[pc,#44] ; [0x1004438] = 0x2019c - 0x0100440a: 6408 .d STR r0,[r1,#0x40] - 0x0100440c: 4608 .F MOV r0,r1 - 0x0100440e: 9a01 .. LDR r2,[sp,#4] - 0x01004410: 9900 .. LDR r1,[sp,#0] - 0x01004412: 6482 .d STR r2,[r0,#0x48] - 0x01004414: 6441 Ad STR r1,[r0,#0x44] - 0x01004416: 4623 #F MOV r3,r4 - 0x01004418: 22ff ." MOVS r2,#0xff - 0x0100441a: 3204 .2 ADDS r2,#4 - 0x0100441c: a107 .. ADR r1,{pc}+0x20 ; 0x100443c - 0x0100441e: f7ffff81 .... BL rt_hw_serial_register ; 0x1004324 - 0x01004422: 2000 . MOVS r0,#0 - 0x01004424: bd1c .. POP {r2-r4,pc} - $d - 0x01004426: 0000 .. DCW 0 - 0x01004428: 01007480 .t.. DCD 16807040 - 0x0100442c: 000f8700 .... DCD 1017600 - 0x01004430: 00020010 .... DCD 131088 - 0x01004434: 01007420 t.. DCD 16806944 - 0x01004438: 0002019c .... DCD 131484 - 0x0100443c: 74726175 uart DCD 1953653109 - 0x01004440: 00000030 0... DCD 48 - $t - i.rt_interrupt_enter - rt_interrupt_enter - 0x01004444: b510 .. PUSH {r4,lr} - 0x01004446: f7fcf83b ..;. BL rt_hw_interrupt_disable ; 0x10004c0 - 0x0100444a: 4604 .F MOV r4,r0 - 0x0100444c: 4809 .H LDR r0,[pc,#36] ; [0x1004474] = 0x20124 - 0x0100444e: 7800 .x LDRB r0,[r0,#0] - 0x01004450: 1c40 @. ADDS r0,r0,#1 - 0x01004452: 4908 .I LDR r1,[pc,#32] ; [0x1004474] = 0x20124 - 0x01004454: 7008 .p STRB r0,[r1,#0] - 0x01004456: bf00 .. NOP - 0x01004458: 4807 .H LDR r0,[pc,#28] ; [0x1004478] = 0x2011c - 0x0100445a: 6800 .h LDR r0,[r0,#0] - 0x0100445c: 2800 .( CMP r0,#0 - 0x0100445e: d002 .. BEQ 0x1004466 ; rt_interrupt_enter + 34 - 0x01004460: 4805 .H LDR r0,[pc,#20] ; [0x1004478] = 0x2011c - 0x01004462: 6800 .h LDR r0,[r0,#0] - 0x01004464: 4780 .G BLX r0 - 0x01004466: bf00 .. NOP - 0x01004468: 4620 F MOV r0,r4 - 0x0100446a: f7fcf82d ..-. BL rt_hw_interrupt_enable ; 0x10004c8 - 0x0100446e: bf00 .. NOP - 0x01004470: bf00 .. NOP - 0x01004472: bd10 .. POP {r4,pc} - $d - 0x01004474: 00020124 $... DCD 131364 - 0x01004478: 0002011c .... DCD 131356 - $t - i.rt_interrupt_get_nest - rt_interrupt_get_nest - 0x0100447c: b570 p. PUSH {r4-r6,lr} - 0x0100447e: f7fcf81f .... BL rt_hw_interrupt_disable ; 0x10004c0 - 0x01004482: 4605 .F MOV r5,r0 - 0x01004484: 4803 .H LDR r0,[pc,#12] ; [0x1004494] = 0x20124 - 0x01004486: 7804 .x LDRB r4,[r0,#0] - 0x01004488: 4628 (F MOV r0,r5 - 0x0100448a: f7fcf81d .... BL rt_hw_interrupt_enable ; 0x10004c8 - 0x0100448e: 4620 F MOV r0,r4 - 0x01004490: bd70 p. POP {r4-r6,pc} - $d - 0x01004492: 0000 .. DCW 0 - 0x01004494: 00020124 $... DCD 131364 - $t - i.rt_interrupt_leave - rt_interrupt_leave - 0x01004498: b510 .. PUSH {r4,lr} - 0x0100449a: bf00 .. NOP - 0x0100449c: bf00 .. NOP - 0x0100449e: f7fcf80f .... BL rt_hw_interrupt_disable ; 0x10004c0 - 0x010044a2: 4604 .F MOV r4,r0 - 0x010044a4: bf00 .. NOP - 0x010044a6: 4808 .H LDR r0,[pc,#32] ; [0x10044c8] = 0x20120 - 0x010044a8: 6800 .h LDR r0,[r0,#0] - 0x010044aa: 2800 .( CMP r0,#0 - 0x010044ac: d002 .. BEQ 0x10044b4 ; rt_interrupt_leave + 28 - 0x010044ae: 4806 .H LDR r0,[pc,#24] ; [0x10044c8] = 0x20120 - 0x010044b0: 6800 .h LDR r0,[r0,#0] - 0x010044b2: 4780 .G BLX r0 - 0x010044b4: bf00 .. NOP - 0x010044b6: 4805 .H LDR r0,[pc,#20] ; [0x10044cc] = 0x20124 - 0x010044b8: 7800 .x LDRB r0,[r0,#0] - 0x010044ba: 1e40 @. SUBS r0,r0,#1 - 0x010044bc: 4903 .I LDR r1,[pc,#12] ; [0x10044cc] = 0x20124 - 0x010044be: 7008 .p STRB r0,[r1,#0] - 0x010044c0: 4620 F MOV r0,r4 - 0x010044c2: f7fcf801 .... BL rt_hw_interrupt_enable ; 0x10004c8 - 0x010044c6: bd10 .. POP {r4,pc} - $d - 0x010044c8: 00020120 ... DCD 131360 - 0x010044cc: 00020124 $... DCD 131364 - $t - i.rt_kprintf - rt_kprintf - 0x010044d0: b40f .. PUSH {r0-r3} - 0x010044d2: b538 8. PUSH {r3-r5,lr} - 0x010044d4: a805 .. ADD r0,sp,#0x14 - 0x010044d6: 9000 .. STR r0,[sp,#0] - 0x010044d8: 217f .! MOVS r1,#0x7f - 0x010044da: 480f .H LDR r0,[pc,#60] ; [0x1004518] = 0x20504 - 0x010044dc: 9b00 .. LDR r3,[sp,#0] - 0x010044de: 9a04 .. LDR r2,[sp,#0x10] - 0x010044e0: f002f9f4 .... BL rt_vsnprintf ; 0x10068cc - 0x010044e4: 4604 .F MOV r4,r0 - 0x010044e6: 2c7f ., CMP r4,#0x7f - 0x010044e8: d900 .. BLS 0x10044ec ; rt_kprintf + 28 - 0x010044ea: 247f .$ MOVS r4,#0x7f - 0x010044ec: 480b .H LDR r0,[pc,#44] ; [0x100451c] = 0x2004c - 0x010044ee: 6800 .h LDR r0,[r0,#0] - 0x010044f0: 2800 .( CMP r0,#0 - 0x010044f2: d103 .. BNE 0x10044fc ; rt_kprintf + 44 - 0x010044f4: 4808 .H LDR r0,[pc,#32] ; [0x1004518] = 0x20504 - 0x010044f6: f7fffe0d .... BL rt_hw_console_output ; 0x1004114 - 0x010044fa: e006 .. B 0x100450a ; rt_kprintf + 58 - 0x010044fc: 4623 #F MOV r3,r4 - 0x010044fe: 4a06 .J LDR r2,[pc,#24] ; [0x1004518] = 0x20504 - 0x01004500: 2100 .! MOVS r1,#0 - 0x01004502: 4806 .H LDR r0,[pc,#24] ; [0x100451c] = 0x2004c - 0x01004504: 6800 .h LDR r0,[r0,#0] - 0x01004506: f7fffc55 ..U. BL rt_device_write ; 0x1003db4 - 0x0100450a: 2000 . MOVS r0,#0 - 0x0100450c: 9000 .. STR r0,[sp,#0] - 0x0100450e: bc38 8. POP {r3-r5} - 0x01004510: bc08 .. POP {r3} - 0x01004512: b004 .. ADD sp,sp,#0x10 - 0x01004514: 4718 .G BX r3 - $d - 0x01004516: 0000 .. DCW 0 - 0x01004518: 00020504 .... DCD 132356 - 0x0100451c: 0002004c L... DCD 131148 - $t - i.rt_list_init - rt_list_init - 0x01004520: 6040 @` STR r0,[r0,#4] - 0x01004522: 6000 .` STR r0,[r0,#0] - 0x01004524: 4770 pG BX lr - i.rt_list_init - rt_list_init - 0x01004526: 6040 @` STR r0,[r0,#4] - 0x01004528: 6000 .` STR r0,[r0,#0] - 0x0100452a: 4770 pG BX lr - i.rt_list_insert_after - rt_list_insert_after - 0x0100452c: 6802 .h LDR r2,[r0,#0] - 0x0100452e: 6051 Q` STR r1,[r2,#4] - 0x01004530: 6802 .h LDR r2,[r0,#0] - 0x01004532: 600a .` STR r2,[r1,#0] - 0x01004534: 6001 .` STR r1,[r0,#0] - 0x01004536: 6048 H` STR r0,[r1,#4] - 0x01004538: 4770 pG BX lr - i.rt_list_insert_after - rt_list_insert_after - 0x0100453a: 6802 .h LDR r2,[r0,#0] - 0x0100453c: 6051 Q` STR r1,[r2,#4] - 0x0100453e: 6802 .h LDR r2,[r0,#0] - 0x01004540: 600a .` STR r2,[r1,#0] - 0x01004542: 6001 .` STR r1,[r0,#0] - 0x01004544: 6048 H` STR r0,[r1,#4] - 0x01004546: 4770 pG BX lr - i.rt_list_insert_before - rt_list_insert_before - 0x01004548: 6842 Bh LDR r2,[r0,#4] - 0x0100454a: 6011 .` STR r1,[r2,#0] - 0x0100454c: 6842 Bh LDR r2,[r0,#4] - 0x0100454e: 604a J` STR r2,[r1,#4] - 0x01004550: 6041 A` STR r1,[r0,#4] - 0x01004552: 6008 .` STR r0,[r1,#0] - 0x01004554: 4770 pG BX lr - i.rt_list_isempty - rt_list_isempty - 0x01004556: 4601 .F MOV r1,r0 - 0x01004558: 6808 .h LDR r0,[r1,#0] - 0x0100455a: 4288 .B CMP r0,r1 - 0x0100455c: d101 .. BNE 0x1004562 ; rt_list_isempty + 12 - 0x0100455e: 2001 . MOVS r0,#1 - 0x01004560: 4770 pG BX lr - 0x01004562: 2000 . MOVS r0,#0 - 0x01004564: e7fc .. B 0x1004560 ; rt_list_isempty + 10 - i.rt_list_isempty - rt_list_isempty - 0x01004566: 4601 .F MOV r1,r0 - 0x01004568: 6808 .h LDR r0,[r1,#0] - 0x0100456a: 4288 .B CMP r0,r1 - 0x0100456c: d101 .. BNE 0x1004572 ; rt_list_isempty + 12 - 0x0100456e: 2001 . MOVS r0,#1 - 0x01004570: 4770 pG BX lr - 0x01004572: 2000 . MOVS r0,#0 - 0x01004574: e7fc .. B 0x1004570 ; rt_list_isempty + 10 - i.rt_list_isempty - rt_list_isempty - 0x01004576: 4601 .F MOV r1,r0 - 0x01004578: 6808 .h LDR r0,[r1,#0] - 0x0100457a: 4288 .B CMP r0,r1 - 0x0100457c: d101 .. BNE 0x1004582 ; rt_list_isempty + 12 - 0x0100457e: 2001 . MOVS r0,#1 - 0x01004580: 4770 pG BX lr - 0x01004582: 2000 . MOVS r0,#0 - 0x01004584: e7fc .. B 0x1004580 ; rt_list_isempty + 10 - i.rt_list_isempty - rt_list_isempty - 0x01004586: 4601 .F MOV r1,r0 - 0x01004588: 6808 .h LDR r0,[r1,#0] - 0x0100458a: 4288 .B CMP r0,r1 - 0x0100458c: d101 .. BNE 0x1004592 ; rt_list_isempty + 12 - 0x0100458e: 2001 . MOVS r0,#1 - 0x01004590: 4770 pG BX lr - 0x01004592: 2000 . MOVS r0,#0 - 0x01004594: e7fc .. B 0x1004590 ; rt_list_isempty + 10 - i.rt_list_len - rt_list_len - 0x01004596: 4601 .F MOV r1,r0 - 0x01004598: 2000 . MOVS r0,#0 - 0x0100459a: 460a .F MOV r2,r1 - 0x0100459c: e001 .. B 0x10045a2 ; rt_list_len + 12 - 0x0100459e: 6812 .h LDR r2,[r2,#0] - 0x010045a0: 1c40 @. ADDS r0,r0,#1 - 0x010045a2: 6813 .h LDR r3,[r2,#0] - 0x010045a4: 428b .B CMP r3,r1 - 0x010045a6: d1fa .. BNE 0x100459e ; rt_list_len + 8 - 0x010045a8: 4770 pG BX lr - i.rt_list_remove - rt_list_remove - 0x010045aa: 6802 .h LDR r2,[r0,#0] - 0x010045ac: 6841 Ah LDR r1,[r0,#4] - 0x010045ae: 6051 Q` STR r1,[r2,#4] - 0x010045b0: 6842 Bh LDR r2,[r0,#4] - 0x010045b2: 6801 .h LDR r1,[r0,#0] - 0x010045b4: 6011 .` STR r1,[r2,#0] - 0x010045b6: 6040 @` STR r0,[r0,#4] - 0x010045b8: 6000 .` STR r0,[r0,#0] - 0x010045ba: 4770 pG BX lr - i.rt_list_remove - rt_list_remove - 0x010045bc: 6802 .h LDR r2,[r0,#0] - 0x010045be: 6841 Ah LDR r1,[r0,#4] - 0x010045c0: 6051 Q` STR r1,[r2,#4] - 0x010045c2: 6842 Bh LDR r2,[r0,#4] - 0x010045c4: 6801 .h LDR r1,[r0,#0] - 0x010045c6: 6011 .` STR r1,[r2,#0] - 0x010045c8: 6040 @` STR r0,[r0,#4] - 0x010045ca: 6000 .` STR r0,[r0,#0] - 0x010045cc: 4770 pG BX lr - i.rt_list_remove - rt_list_remove - 0x010045ce: 6802 .h LDR r2,[r0,#0] - 0x010045d0: 6841 Ah LDR r1,[r0,#4] - 0x010045d2: 6051 Q` STR r1,[r2,#4] - 0x010045d4: 6842 Bh LDR r2,[r0,#4] - 0x010045d6: 6801 .h LDR r1,[r0,#0] - 0x010045d8: 6011 .` STR r1,[r2,#0] - 0x010045da: 6040 @` STR r0,[r0,#4] - 0x010045dc: 6000 .` STR r0,[r0,#0] - 0x010045de: 4770 pG BX lr - i.rt_malloc - rt_malloc - 0x010045e0: b5fe .. PUSH {r1-r7,lr} - 0x010045e2: 4605 .F MOV r5,r0 - 0x010045e4: 2d00 .- CMP r5,#0 - 0x010045e6: d100 .. BNE 0x10045ea ; rt_malloc + 10 - 0x010045e8: bdfe .. POP {r1-r7,pc} - 0x010045ea: bf00 .. NOP - 0x010045ec: f7fbff68 ..h. BL rt_hw_interrupt_disable ; 0x10004c0 - 0x010045f0: 9000 .. STR r0,[sp,#0] - 0x010045f2: f7ffff43 ..C. BL rt_interrupt_get_nest ; 0x100447c - 0x010045f6: 2800 .( CMP r0,#0 - 0x010045f8: d009 .. BEQ 0x100460e ; rt_malloc + 46 - 0x010045fa: 497e ~I LDR r1,[pc,#504] ; [0x10047f4] = 0x1007c0e - 0x010045fc: a07e ~. ADR r0,{pc}+0x1fc ; 0x10047f8 - 0x010045fe: f7ffff67 ..g. BL rt_kprintf ; 0x10044d0 - 0x01004602: 22ff ." MOVS r2,#0xff - 0x01004604: 3219 .2 ADDS r2,r2,#0x19 - 0x01004606: 497b {I LDR r1,[pc,#492] ; [0x10047f4] = 0x1007c0e - 0x01004608: a085 .. ADR r0,{pc}+0x218 ; 0x1004820 - 0x0100460a: f7fefff9 .... BL rt_assert_handler ; 0x1003600 - 0x0100460e: 9800 .. LDR r0,[sp,#0] - 0x01004610: f7fbff5a ..Z. BL rt_hw_interrupt_enable ; 0x10004c8 - 0x01004614: bf00 .. NOP - 0x01004616: 1ce8 .. ADDS r0,r5,#3 - 0x01004618: 0880 .. LSRS r0,r0,#2 - 0x0100461a: 0080 .. LSLS r0,r0,#2 - 0x0100461c: 42a8 .B CMP r0,r5 - 0x0100461e: d001 .. BEQ 0x1004624 ; rt_malloc + 68 - 0x01004620: bf00 .. NOP - 0x01004622: e001 .. B 0x1004628 ; rt_malloc + 72 - 0x01004624: bf00 .. NOP - 0x01004626: bf00 .. NOP - 0x01004628: 1ce8 .. ADDS r0,r5,#3 - 0x0100462a: 0885 .. LSRS r5,r0,#2 - 0x0100462c: 00ad .. LSLS r5,r5,#2 - 0x0100462e: 487d }H LDR r0,[pc,#500] ; [0x1004824] = 0x20148 - 0x01004630: 6800 .h LDR r0,[r0,#0] - 0x01004632: 4285 .B CMP r5,r0 - 0x01004634: d903 .. BLS 0x100463e ; rt_malloc + 94 - 0x01004636: bf00 .. NOP - 0x01004638: bf00 .. NOP - 0x0100463a: 2000 . MOVS r0,#0 - 0x0100463c: e7d4 .. B 0x10045e8 ; rt_malloc + 8 - 0x0100463e: 2d0c .- CMP r5,#0xc - 0x01004640: d200 .. BCS 0x1004644 ; rt_malloc + 100 - 0x01004642: 250c .% MOVS r5,#0xc - 0x01004644: 2100 .! MOVS r1,#0 - 0x01004646: 43c9 .C MVNS r1,r1 - 0x01004648: 4877 wH LDR r0,[pc,#476] ; [0x1004828] = 0x20584 - 0x0100464a: f000fec9 .... BL rt_sem_take ; 0x10053e0 - 0x0100464e: 4877 wH LDR r0,[pc,#476] ; [0x100482c] = 0x20144 - 0x01004650: 6800 .h LDR r0,[r0,#0] - 0x01004652: 4977 wI LDR r1,[pc,#476] ; [0x1004830] = 0x2013c - 0x01004654: 6809 .h LDR r1,[r1,#0] - 0x01004656: 1a46 F. SUBS r6,r0,r1 - 0x01004658: e0c0 .. B 0x10047dc ; rt_malloc + 508 - 0x0100465a: 4875 uH LDR r0,[pc,#468] ; [0x1004830] = 0x2013c - 0x0100465c: 6800 .h LDR r0,[r0,#0] - 0x0100465e: 1984 .. ADDS r4,r0,r6 - 0x01004660: 8860 `. LDRH r0,[r4,#2] - 0x01004662: 2800 .( CMP r0,#0 - 0x01004664: d17d }. BNE 0x1004762 ; rt_malloc + 386 - 0x01004666: 4630 0F MOV r0,r6 - 0x01004668: 300c .0 ADDS r0,r0,#0xc - 0x0100466a: 6861 ah LDR r1,[r4,#4] - 0x0100466c: 1a08 .. SUBS r0,r1,r0 - 0x0100466e: 42a8 .B CMP r0,r5 - 0x01004670: d377 w. BCC 0x1004762 ; rt_malloc + 386 - 0x01004672: 4630 0F MOV r0,r6 - 0x01004674: 300c .0 ADDS r0,r0,#0xc - 0x01004676: 6861 ah LDR r1,[r4,#4] - 0x01004678: 1a09 .. SUBS r1,r1,r0 - 0x0100467a: 4628 (F MOV r0,r5 - 0x0100467c: 3018 .0 ADDS r0,r0,#0x18 - 0x0100467e: 4281 .B CMP r1,r0 - 0x01004680: d330 0. BCC 0x10046e4 ; rt_malloc + 260 - 0x01004682: 4630 0F MOV r0,r6 - 0x01004684: 300c .0 ADDS r0,r0,#0xc - 0x01004686: 1940 @. ADDS r0,r0,r5 - 0x01004688: 9001 .. STR r0,[sp,#4] - 0x0100468a: 4869 iH LDR r0,[pc,#420] ; [0x1004830] = 0x2013c - 0x0100468c: 6801 .h LDR r1,[r0,#0] - 0x0100468e: 9801 .. LDR r0,[sp,#4] - 0x01004690: 180f .. ADDS r7,r1,r0 - 0x01004692: 20f5 . MOVS r0,#0xf5 - 0x01004694: 0140 @. LSLS r0,r0,#5 - 0x01004696: 8038 8. STRH r0,[r7,#0] - 0x01004698: 2000 . MOVS r0,#0 - 0x0100469a: 8078 x. STRH r0,[r7,#2] - 0x0100469c: 6860 `h LDR r0,[r4,#4] - 0x0100469e: 6078 x` STR r0,[r7,#4] - 0x010046a0: 60be .` STR r6,[r7,#8] - 0x010046a2: 9801 .. LDR r0,[sp,#4] - 0x010046a4: 6060 `` STR r0,[r4,#4] - 0x010046a6: 2001 . MOVS r0,#1 - 0x010046a8: 8060 `. STRH r0,[r4,#2] - 0x010046aa: 485e ^H LDR r0,[pc,#376] ; [0x1004824] = 0x20148 - 0x010046ac: 6879 yh LDR r1,[r7,#4] - 0x010046ae: 6800 .h LDR r0,[r0,#0] - 0x010046b0: 300c .0 ADDS r0,r0,#0xc - 0x010046b2: 4281 .B CMP r1,r0 - 0x010046b4: d005 .. BEQ 0x10046c2 ; rt_malloc + 226 - 0x010046b6: 9801 .. LDR r0,[sp,#4] - 0x010046b8: 4a5d ]J LDR r2,[pc,#372] ; [0x1004830] = 0x2013c - 0x010046ba: 6879 yh LDR r1,[r7,#4] - 0x010046bc: 6812 .h LDR r2,[r2,#0] - 0x010046be: 1889 .. ADDS r1,r1,r2 - 0x010046c0: 6088 .` STR r0,[r1,#8] - 0x010046c2: 485c \H LDR r0,[pc,#368] ; [0x1004834] = 0x2014c - 0x010046c4: 6801 .h LDR r1,[r0,#0] - 0x010046c6: 4628 (F MOV r0,r5 - 0x010046c8: 300c .0 ADDS r0,r0,#0xc - 0x010046ca: 1808 .. ADDS r0,r1,r0 - 0x010046cc: 4959 YI LDR r1,[pc,#356] ; [0x1004834] = 0x2014c - 0x010046ce: 6008 .` STR r0,[r1,#0] - 0x010046d0: 4859 YH LDR r0,[pc,#356] ; [0x1004838] = 0x20150 - 0x010046d2: 6800 .h LDR r0,[r0,#0] - 0x010046d4: 6809 .h LDR r1,[r1,#0] - 0x010046d6: 4288 .B CMP r0,r1 - 0x010046d8: d219 .. BCS 0x100470e ; rt_malloc + 302 - 0x010046da: 4856 VH LDR r0,[pc,#344] ; [0x1004834] = 0x2014c - 0x010046dc: 6800 .h LDR r0,[r0,#0] - 0x010046de: 4956 VI LDR r1,[pc,#344] ; [0x1004838] = 0x20150 - 0x010046e0: 6008 .` STR r0,[r1,#0] - 0x010046e2: e014 .. B 0x100470e ; rt_malloc + 302 - 0x010046e4: 2001 . MOVS r0,#1 - 0x010046e6: 8060 `. STRH r0,[r4,#2] - 0x010046e8: 4951 QI LDR r1,[pc,#324] ; [0x1004830] = 0x2013c - 0x010046ea: 6860 `h LDR r0,[r4,#4] - 0x010046ec: 6809 .h LDR r1,[r1,#0] - 0x010046ee: 1a61 a. SUBS r1,r4,r1 - 0x010046f0: 1a40 @. SUBS r0,r0,r1 - 0x010046f2: 4950 PI LDR r1,[pc,#320] ; [0x1004834] = 0x2014c - 0x010046f4: 6809 .h LDR r1,[r1,#0] - 0x010046f6: 1840 @. ADDS r0,r0,r1 - 0x010046f8: 494e NI LDR r1,[pc,#312] ; [0x1004834] = 0x2014c - 0x010046fa: 6008 .` STR r0,[r1,#0] - 0x010046fc: 484e NH LDR r0,[pc,#312] ; [0x1004838] = 0x20150 - 0x010046fe: 6800 .h LDR r0,[r0,#0] - 0x01004700: 6809 .h LDR r1,[r1,#0] - 0x01004702: 4288 .B CMP r0,r1 - 0x01004704: d203 .. BCS 0x100470e ; rt_malloc + 302 - 0x01004706: 484b KH LDR r0,[pc,#300] ; [0x1004834] = 0x2014c - 0x01004708: 6800 .h LDR r0,[r0,#0] - 0x0100470a: 494b KI LDR r1,[pc,#300] ; [0x1004838] = 0x20150 - 0x0100470c: 6008 .` STR r0,[r1,#0] - 0x0100470e: 20f5 . MOVS r0,#0xf5 - 0x01004710: 0140 @. LSLS r0,r0,#5 - 0x01004712: 8020 . STRH r0,[r4,#0] - 0x01004714: 4845 EH LDR r0,[pc,#276] ; [0x100482c] = 0x20144 - 0x01004716: 6800 .h LDR r0,[r0,#0] - 0x01004718: 4284 .B CMP r4,r0 - 0x0100471a: d126 &. BNE 0x100476a ; rt_malloc + 394 - 0x0100471c: e007 .. B 0x100472e ; rt_malloc + 334 - 0x0100471e: 4843 CH LDR r0,[pc,#268] ; [0x100482c] = 0x20144 - 0x01004720: 6800 .h LDR r0,[r0,#0] - 0x01004722: 6840 @h LDR r0,[r0,#4] - 0x01004724: 4942 BI LDR r1,[pc,#264] ; [0x1004830] = 0x2013c - 0x01004726: 6809 .h LDR r1,[r1,#0] - 0x01004728: 1840 @. ADDS r0,r0,r1 - 0x0100472a: 4940 @I LDR r1,[pc,#256] ; [0x100482c] = 0x20144 - 0x0100472c: 6008 .` STR r0,[r1,#0] - 0x0100472e: 483f ?H LDR r0,[pc,#252] ; [0x100482c] = 0x20144 - 0x01004730: 6800 .h LDR r0,[r0,#0] - 0x01004732: 8840 @. LDRH r0,[r0,#2] - 0x01004734: 2800 .( CMP r0,#0 - 0x01004736: d005 .. BEQ 0x1004744 ; rt_malloc + 356 - 0x01004738: 483c use DCD 1702065470 - 0x01004864: 00292964 d)). DCD 2697572 - 0x01004868: 0100803c <... DCD 16810044 - 0x0100486c: 01007f94 .... DCD 16809876 - 0x01004870: 72282828 (((r DCD 1915234344 - 0x01004874: 62755f74 t_ub DCD 1651859316 - 0x01004878: 5f657361 ase_ DCD 1600484193 - 0x0100487c: 656d2974 t)me DCD 1701652852 - 0x01004880: 2620296d m) & DCD 639641965 - 0x01004884: 54522820 (RT DCD 1414670368 - 0x01004888: 494c415f _ALI DCD 1229734239 - 0x0100488c: 535f4e47 GN_S DCD 1398754887 - 0x01004890: 20455a49 IZE DCD 541416009 - 0x01004894: 2931202d - 1) DCD 691085357 - 0x01004898: 3d3d2029 ) == DCD 1027416105 - 0x0100489c: 00003020 0.. DCD 12320 - 0x010048a0: 00020134 4... DCD 131380 - $t - i.rt_memcpy - rt_memcpy - 0x010048a4: b5f7 .. PUSH {r0-r2,r4-r7,lr} - 0x010048a6: 4616 .F MOV r6,r2 - 0x010048a8: 9c00 .. LDR r4,[sp,#0] - 0x010048aa: 9d01 .. LDR r5,[sp,#4] - 0x010048ac: 4633 3F MOV r3,r6 - 0x010048ae: 2b10 .+ CMP r3,#0x10 - 0x010048b0: d31c .. BCC 0x10048ec ; rt_memcpy + 72 - 0x010048b2: 07a8 .. LSLS r0,r5,#30 - 0x010048b4: 0f80 .. LSRS r0,r0,#30 - 0x010048b6: 07a7 .. LSLS r7,r4,#30 - 0x010048b8: 0fbf .. LSRS r7,r7,#30 - 0x010048ba: 4338 8C ORRS r0,r0,r7 - 0x010048bc: 2800 .( CMP r0,#0 - 0x010048be: d115 .. BNE 0x10048ec ; rt_memcpy + 72 - 0x010048c0: 4621 !F MOV r1,r4 - 0x010048c2: 462a *F MOV r2,r5 - 0x010048c4: e008 .. B 0x10048d8 ; rt_memcpy + 52 - 0x010048c6: ca01 .. LDM r2!,{r0} - 0x010048c8: c101 .. STM r1!,{r0} - 0x010048ca: ca01 .. LDM r2!,{r0} - 0x010048cc: c101 .. STM r1!,{r0} - 0x010048ce: ca01 .. LDM r2!,{r0} - 0x010048d0: c101 .. STM r1!,{r0} - 0x010048d2: ca01 .. LDM r2!,{r0} - 0x010048d4: c101 .. STM r1!,{r0} - 0x010048d6: 3b10 .; SUBS r3,r3,#0x10 - 0x010048d8: 2b10 .+ CMP r3,#0x10 - 0x010048da: d2f4 .. BCS 0x10048c6 ; rt_memcpy + 34 - 0x010048dc: e002 .. B 0x10048e4 ; rt_memcpy + 64 - 0x010048de: ca01 .. LDM r2!,{r0} - 0x010048e0: c101 .. STM r1!,{r0} - 0x010048e2: 1f1b .. SUBS r3,r3,#4 - 0x010048e4: 2b04 .+ CMP r3,#4 - 0x010048e6: d2fa .. BCS 0x10048de ; rt_memcpy + 58 - 0x010048e8: 460c .F MOV r4,r1 - 0x010048ea: 4615 .F MOV r5,r2 - 0x010048ec: e003 .. B 0x10048f6 ; rt_memcpy + 82 - 0x010048ee: 7828 (x LDRB r0,[r5,#0] - 0x010048f0: 7020 p STRB r0,[r4,#0] - 0x010048f2: 1c6d m. ADDS r5,r5,#1 - 0x010048f4: 1c64 d. ADDS r4,r4,#1 - 0x010048f6: 4618 .F MOV r0,r3 - 0x010048f8: 1e5b [. SUBS r3,r3,#1 - 0x010048fa: 2800 .( CMP r0,#0 - 0x010048fc: d1f7 .. BNE 0x10048ee ; rt_memcpy + 74 - 0x010048fe: 9800 .. LDR r0,[sp,#0] - 0x01004900: bdfe .. POP {r1-r7,pc} - 0x01004902: 0000 .. MOVS r0,r0 - i.rt_memheap_dump - rt_memheap_dump - 0x01004904: b5f8 .. PUSH {r3-r7,lr} - 0x01004906: 4605 .F MOV r5,r0 - 0x01004908: 2d00 .- CMP r5,#0 - 0x0100490a: d100 .. BNE 0x100490e ; rt_memheap_dump + 10 - 0x0100490c: bdf8 .. POP {r3-r7,pc} - 0x0100490e: 4628 (F MOV r0,r5 - 0x01004910: f000faac .... BL rt_object_get_type ; 0x1004e6c - 0x01004914: 2807 .( CMP r0,#7 - 0x01004916: d004 .. BEQ 0x1004922 ; rt_memheap_dump + 30 - 0x01004918: 4a2a *J LDR r2,[pc,#168] ; [0x10049c4] = 0x2b1 - 0x0100491a: 492b +I LDR r1,[pc,#172] ; [0x10049c8] = 0x1007b22 - 0x0100491c: a02b +. ADR r0,{pc}+0xb0 ; 0x10049cc - 0x0100491e: f7fefe6f ..o. BL rt_assert_handler ; 0x1003600 - 0x01004922: 69a9 .i LDR r1,[r5,#0x18] - 0x01004924: 6968 hi LDR r0,[r5,#0x14] - 0x01004926: 1840 @. ADDS r0,r0,r1 - 0x01004928: 9000 .. STR r0,[sp,#0] - 0x0100492a: 462a *F MOV r2,r5 - 0x0100492c: 2108 .! MOVS r1,#8 - 0x0100492e: a037 7. ADR r0,{pc}+0xde ; 0x1004a0c - 0x01004930: 696b ki LDR r3,[r5,#0x14] - 0x01004932: f7fffdcd .... BL rt_kprintf ; 0x10044d0 - 0x01004936: a03d =. ADR r0,{pc}+0xf6 ; 0x1004a2c - 0x01004938: f7fffdca .... BL rt_kprintf ; 0x10044d0 - 0x0100493c: 2100 .! MOVS r1,#0 - 0x0100493e: 43c9 .C MVNS r1,r1 - 0x01004940: 4628 (F MOV r0,r5 - 0x01004942: 3044 D0 ADDS r0,r0,#0x44 - 0x01004944: f000fd4c ..L. BL rt_sem_take ; 0x10053e0 - 0x01004948: 6a6c lj LDR r4,[r5,#0x24] - 0x0100494a: 69a9 .i LDR r1,[r5,#0x18] - 0x0100494c: 6968 hi LDR r0,[r5,#0x14] - 0x0100494e: 1840 @. ADDS r0,r0,r1 - 0x01004950: 4606 .F MOV r6,r0 - 0x01004952: 3e18 .> SUBS r6,r6,#0x18 - 0x01004954: e02e .. B 0x10049b4 ; rt_memheap_dump + 176 - 0x01004956: 7820 x LDRB r0,[r4,#0] - 0x01004958: 07c0 .. LSLS r0,r0,#31 - 0x0100495a: 0fc0 .. LSRS r0,r0,#31 - 0x0100495c: 2800 .( CMP r0,#0 - 0x0100495e: d00a .. BEQ 0x1004976 ; rt_memheap_dump + 114 - 0x01004960: 6820 h LDR r0,[r4,#0] - 0x01004962: 0840 @. LSRS r0,r0,#1 - 0x01004964: 0040 @. LSLS r0,r0,#1 - 0x01004966: 4939 9I LDR r1,[pc,#228] ; [0x1004a4c] = 0x1ea01ea0 - 0x01004968: 4288 .B CMP r0,r1 - 0x0100496a: d004 .. BEQ 0x1004976 ; rt_memheap_dump + 114 - 0x0100496c: 4621 !F MOV r1,r4 - 0x0100496e: 3118 .1 ADDS r1,r1,#0x18 - 0x01004970: a037 7. ADR r0,{pc}+0xe0 ; 0x1004a50 - 0x01004972: f7fffdad .... BL rt_kprintf ; 0x10044d0 - 0x01004976: 4935 5I LDR r1,[pc,#212] ; [0x1004a4c] = 0x1ea01ea0 - 0x01004978: 1c49 I. ADDS r1,r1,#1 - 0x0100497a: 6820 h LDR r0,[r4,#0] - 0x0100497c: 4288 .B CMP r0,r1 - 0x0100497e: d10f .. BNE 0x10049a0 ; rt_memheap_dump + 156 - 0x01004980: 68a0 .h LDR r0,[r4,#8] - 0x01004982: 1b00 .. SUBS r0,r0,r4 - 0x01004984: 4602 .F MOV r2,r0 - 0x01004986: 3a18 .: SUBS r2,r2,#0x18 - 0x01004988: 4621 !F MOV r1,r4 - 0x0100498a: 3118 .1 ADDS r1,r1,#0x18 - 0x0100498c: a032 2. ADR r0,{pc}+0xcc ; 0x1004a58 - 0x0100498e: f7fffd9f .... BL rt_kprintf ; 0x10044d0 - 0x01004992: 4620 F MOV r0,r4 - 0x01004994: f7fcfbac .... BL _memheap_dump_tag ; 0x10010f0 - 0x01004998: a033 3. ADR r0,{pc}+0xd0 ; 0x1004a68 - 0x0100499a: f7fffd99 .... BL rt_kprintf ; 0x10044d0 - 0x0100499e: e008 .. B 0x10049b2 ; rt_memheap_dump + 174 - 0x010049a0: 68a0 .h LDR r0,[r4,#8] - 0x010049a2: 1b00 .. SUBS r0,r0,r4 - 0x010049a4: 4602 .F MOV r2,r0 - 0x010049a6: 3a18 .: SUBS r2,r2,#0x18 - 0x010049a8: 4621 !F MOV r1,r4 - 0x010049aa: 3118 .1 ADDS r1,r1,#0x18 - 0x010049ac: a02f /. ADR r0,{pc}+0xc0 ; 0x1004a6c - 0x010049ae: f7fffd8f .... BL rt_kprintf ; 0x10044d0 - 0x010049b2: 68a4 .h LDR r4,[r4,#8] - 0x010049b4: 42b4 .B CMP r4,r6 - 0x010049b6: d3ce .. BCC 0x1004956 ; rt_memheap_dump + 82 - 0x010049b8: 4628 (F MOV r0,r5 - 0x010049ba: 3044 D0 ADDS r0,r0,#0x44 - 0x010049bc: f000fcb6 .... BL rt_sem_release ; 0x100532c - 0x010049c0: 2000 . MOVS r0,#0 - 0x010049c2: e7a3 .. B 0x100490c ; rt_memheap_dump + 8 - $d - 0x010049c4: 000002b1 .... DCD 689 - 0x010049c8: 01007b22 "{.. DCD 16808738 - 0x010049cc: 6f5f7472 rt_o DCD 1868526706 - 0x010049d0: 63656a62 bjec DCD 1667590754 - 0x010049d4: 65675f74 t_ge DCD 1701273460 - 0x010049d8: 79745f74 t_ty DCD 2037669748 - 0x010049dc: 26286570 pe(& DCD 640181616 - 0x010049e0: 70616568 heap DCD 1885431144 - 0x010049e4: 61703e2d ->pa DCD 1634745901 - 0x010049e8: 746e6572 rent DCD 1953391986 - 0x010049ec: 3d3d2029 ) == DCD 1027416105 - 0x010049f0: 5f545220 RT_ DCD 1599361568 - 0x010049f4: 656a624f Obje DCD 1701470799 - 0x010049f8: 435f7463 ct_C DCD 1130329187 - 0x010049fc: 7373616c lass DCD 1936941420 - 0x01004a00: 6d654d5f _Mem DCD 1835355487 - 0x01004a04: 70616548 Heap DCD 1885431112 - 0x01004a08: 00000000 .... DCD 0 - 0x01004a0c: 2e255b0a .[%. DCD 774200074 - 0x01004a10: 205d732a *s] DCD 542995242 - 0x01004a14: 2578305b [0x% DCD 628633691 - 0x01004a18: 20783830 08x DCD 544749616 - 0x01004a1c: 7830202d - 0x DCD 2016419885 - 0x01004a20: 78383025 %08x DCD 2016948261 - 0x01004a24: 0a3e2d5d ]->. DCD 171847005 - 0x01004a28: 00000000 .... DCD 0 - 0x01004a2c: 2d2d2d2d ---- DCD 757935405 - 0x01004a30: 2d2d2d2d ---- DCD 757935405 - 0x01004a34: 2d2d2d2d ---- DCD 757935405 - 0x01004a38: 2d2d2d2d ---- DCD 757935405 - 0x01004a3c: 2d2d2d2d ---- DCD 757935405 - 0x01004a40: 2d2d2d2d ---- DCD 757935405 - 0x01004a44: 2d2d2d2d ---- DCD 757935405 - 0x01004a48: 000a2d2d --.. DCD 666925 - 0x01004a4c: 1ea01ea0 .... DCD 513810080 - 0x01004a50: 30257830 0x%0 DCD 807761968 - 0x01004a54: 00007838 8x.. DCD 30776 - 0x01004a58: 30257830 0x%0 DCD 807761968 - 0x01004a5c: 203a7838 8x: DCD 540702776 - 0x01004a60: 64382d25 %-8d DCD 1681403173 - 0x01004a64: 00000020 ... DCD 32 - 0x01004a68: 0000000a .... DCD 10 - 0x01004a6c: 30257830 0x%0 DCD 807761968 - 0x01004a70: 203a7838 8x: DCD 540702776 - 0x01004a74: 64382d25 %-8d DCD 1681403173 - 0x01004a78: 3e463c20 DCD 1044790304 - 0x01004a7c: 0000000a .... DCD 10 - $t - i.rt_memmove - rt_memmove - 0x01004a80: b570 p. PUSH {r4-r6,lr} - 0x01004a82: 460c .F MOV r4,r1 - 0x01004a84: 4601 .F MOV r1,r0 - 0x01004a86: 4623 #F MOV r3,r4 - 0x01004a88: 428b .B CMP r3,r1 - 0x01004a8a: d210 .. BCS 0x1004aae ; rt_memmove + 46 - 0x01004a8c: 189d .. ADDS r5,r3,r2 - 0x01004a8e: 428d .B CMP r5,r1 - 0x01004a90: d90d .. BLS 0x1004aae ; rt_memmove + 46 - 0x01004a92: 1889 .. ADDS r1,r1,r2 - 0x01004a94: 189b .. ADDS r3,r3,r2 - 0x01004a96: e005 .. B 0x1004aa4 ; rt_memmove + 36 - 0x01004a98: 1e5d ]. SUBS r5,r3,#1 - 0x01004a9a: 462b +F MOV r3,r5 - 0x01004a9c: 782e .x LDRB r6,[r5,#0] - 0x01004a9e: 1e4d M. SUBS r5,r1,#1 - 0x01004aa0: 4629 )F MOV r1,r5 - 0x01004aa2: 702e .p STRB r6,[r5,#0] - 0x01004aa4: 4615 .F MOV r5,r2 - 0x01004aa6: 1e52 R. SUBS r2,r2,#1 - 0x01004aa8: 2d00 .- CMP r5,#0 - 0x01004aaa: d1f5 .. BNE 0x1004a98 ; rt_memmove + 24 - 0x01004aac: e008 .. B 0x1004ac0 ; rt_memmove + 64 - 0x01004aae: e003 .. B 0x1004ab8 ; rt_memmove + 56 - 0x01004ab0: 781d .x LDRB r5,[r3,#0] - 0x01004ab2: 700d .p STRB r5,[r1,#0] - 0x01004ab4: 1c5b [. ADDS r3,r3,#1 - 0x01004ab6: 1c49 I. ADDS r1,r1,#1 - 0x01004ab8: 4615 .F MOV r5,r2 - 0x01004aba: 1e52 R. SUBS r2,r2,#1 - 0x01004abc: 2d00 .- CMP r5,#0 - 0x01004abe: d1f7 .. BNE 0x1004ab0 ; rt_memmove + 48 - 0x01004ac0: bd70 p. POP {r4-r6,pc} - i.rt_memset - rt_memset - 0x01004ac2: b5f7 .. PUSH {r0-r2,r4-r7,lr} - 0x01004ac4: 4605 .F MOV r5,r0 - 0x01004ac6: 9e01 .. LDR r6,[sp,#4] - 0x01004ac8: b2f4 .. UXTB r4,r6 - 0x01004aca: 2a04 .* CMP r2,#4 - 0x01004acc: d317 .. BCC 0x1004afe ; rt_memset + 60 - 0x01004ace: 0786 .. LSLS r6,r0,#30 - 0x01004ad0: 0fb6 .. LSRS r6,r6,#30 - 0x01004ad2: 2e00 .. CMP r6,#0 - 0x01004ad4: d113 .. BNE 0x1004afe ; rt_memset + 60 - 0x01004ad6: 4601 .F MOV r1,r0 - 0x01004ad8: 0226 &. LSLS r6,r4,#8 - 0x01004ada: 4326 &C ORRS r6,r6,r4 - 0x01004adc: 4633 3F MOV r3,r6 - 0x01004ade: 041e .. LSLS r6,r3,#16 - 0x01004ae0: 4333 3C ORRS r3,r3,r6 - 0x01004ae2: e004 .. B 0x1004aee ; rt_memset + 44 - 0x01004ae4: c108 .. STM r1!,{r3} - 0x01004ae6: c108 .. STM r1!,{r3} - 0x01004ae8: c108 .. STM r1!,{r3} - 0x01004aea: c108 .. STM r1!,{r3} - 0x01004aec: 3a10 .: SUBS r2,r2,#0x10 - 0x01004aee: 2a10 .* CMP r2,#0x10 - 0x01004af0: d2f8 .. BCS 0x1004ae4 ; rt_memset + 34 - 0x01004af2: e001 .. B 0x1004af8 ; rt_memset + 54 - 0x01004af4: c108 .. STM r1!,{r3} - 0x01004af6: 1f12 .. SUBS r2,r2,#4 - 0x01004af8: 2a04 .* CMP r2,#4 - 0x01004afa: d2fb .. BCS 0x1004af4 ; rt_memset + 50 - 0x01004afc: 460d .F MOV r5,r1 - 0x01004afe: e001 .. B 0x1004b04 ; rt_memset + 66 - 0x01004b00: 702c ,p STRB r4,[r5,#0] - 0x01004b02: 1c6d m. ADDS r5,r5,#1 - 0x01004b04: 4616 .F MOV r6,r2 - 0x01004b06: 1e52 R. SUBS r2,r2,#1 - 0x01004b08: 2e00 .. CMP r6,#0 - 0x01004b0a: d1f9 .. BNE 0x1004b00 ; rt_memset + 62 - 0x01004b0c: bdfe .. POP {r1-r7,pc} - 0x01004b0e: 0000 .. MOVS r0,r0 - i.rt_object_allocate - rt_object_allocate - 0x01004b10: b5fe .. PUSH {r1-r7,lr} - 0x01004b12: 4606 .F MOV r6,r0 - 0x01004b14: 460f .F MOV r7,r1 - 0x01004b16: bf00 .. NOP - 0x01004b18: f7fbfcd2 .... BL rt_hw_interrupt_disable ; 0x10004c0 - 0x01004b1c: 9000 .. STR r0,[sp,#0] - 0x01004b1e: f7fffcad .... BL rt_interrupt_get_nest ; 0x100447c - 0x01004b22: 2800 .( CMP r0,#0 - 0x01004b24: d009 .. BEQ 0x1004b3a ; rt_object_allocate + 42 - 0x01004b26: 4922 "I LDR r1,[pc,#136] ; [0x1004bb0] = 0x1007a6c - 0x01004b28: a022 ". ADR r0,{pc}+0x8c ; 0x1004bb4 - 0x01004b2a: f7fffcd1 .... BL rt_kprintf ; 0x10044d0 - 0x01004b2e: 22ff ." MOVS r2,#0xff - 0x01004b30: 329a .2 ADDS r2,r2,#0x9a - 0x01004b32: 491f .I LDR r1,[pc,#124] ; [0x1004bb0] = 0x1007a6c - 0x01004b34: a029 ). ADR r0,{pc}+0xa8 ; 0x1004bdc - 0x01004b36: f7fefd63 ..c. BL rt_assert_handler ; 0x1003600 - 0x01004b3a: 9800 .. LDR r0,[sp,#0] - 0x01004b3c: f7fbfcc4 .... BL rt_hw_interrupt_enable ; 0x10004c8 - 0x01004b40: bf00 .. NOP - 0x01004b42: 4630 0F MOV r0,r6 - 0x01004b44: f000f938 ..8. BL rt_object_get_information ; 0x1004db8 - 0x01004b48: 4605 .F MOV r5,r0 - 0x01004b4a: 2d00 .- CMP r5,#0 - 0x01004b4c: d105 .. BNE 0x1004b5a ; rt_object_allocate + 74 - 0x01004b4e: 22ff ." MOVS r2,#0xff - 0x01004b50: 329e .2 ADDS r2,r2,#0x9e - 0x01004b52: 4917 .I LDR r1,[pc,#92] ; [0x1004bb0] = 0x1007a6c - 0x01004b54: a022 ". ADR r0,{pc}+0x8c ; 0x1004be0 - 0x01004b56: f7fefd53 ..S. BL rt_assert_handler ; 0x1003600 - 0x01004b5a: 68e8 .h LDR r0,[r5,#0xc] - 0x01004b5c: f7fffd40 ..@. BL rt_malloc ; 0x10045e0 - 0x01004b60: 4604 .F MOV r4,r0 - 0x01004b62: 2c00 ., CMP r4,#0 - 0x01004b64: d100 .. BNE 0x1004b68 ; rt_object_allocate + 88 - 0x01004b66: bdfe .. POP {r1-r7,pc} - 0x01004b68: 2100 .! MOVS r1,#0 - 0x01004b6a: 4620 F MOV r0,r4 - 0x01004b6c: 68ea .h LDR r2,[r5,#0xc] - 0x01004b6e: f7ffffa8 .... BL rt_memset ; 0x1004ac2 - 0x01004b72: 7226 &r STRB r6,[r4,#8] - 0x01004b74: 2000 . MOVS r0,#0 - 0x01004b76: 7260 `r STRB r0,[r4,#9] - 0x01004b78: 2208 ." MOVS r2,#8 - 0x01004b7a: 4639 9F MOV r1,r7 - 0x01004b7c: 4620 F MOV r0,r4 - 0x01004b7e: f000ffdc .... BL rt_strncpy ; 0x1005b3a - 0x01004b82: bf00 .. NOP - 0x01004b84: 481c .H LDR r0,[pc,#112] ; [0x1004bf8] = 0x20108 - 0x01004b86: 6800 .h LDR r0,[r0,#0] - 0x01004b88: 2800 .( CMP r0,#0 - 0x01004b8a: d003 .. BEQ 0x1004b94 ; rt_object_allocate + 132 - 0x01004b8c: 4620 F MOV r0,r4 - 0x01004b8e: 491a .I LDR r1,[pc,#104] ; [0x1004bf8] = 0x20108 - 0x01004b90: 6809 .h LDR r1,[r1,#0] - 0x01004b92: 4788 .G BLX r1 - 0x01004b94: bf00 .. NOP - 0x01004b96: f7fbfc93 .... BL rt_hw_interrupt_disable ; 0x10004c0 - 0x01004b9a: 9001 .. STR r0,[sp,#4] - 0x01004b9c: 4621 !F MOV r1,r4 - 0x01004b9e: 310c .1 ADDS r1,r1,#0xc - 0x01004ba0: 1d28 (. ADDS r0,r5,#4 - 0x01004ba2: f7fffcca .... BL rt_list_insert_after ; 0x100453a - 0x01004ba6: 9801 .. LDR r0,[sp,#4] - 0x01004ba8: f7fbfc8e .... BL rt_hw_interrupt_enable ; 0x10004c8 - 0x01004bac: 4620 F MOV r0,r4 - 0x01004bae: e7da .. B 0x1004b66 ; rt_object_allocate + 86 - $d - 0x01004bb0: 01007a6c lz.. DCD 16808556 - 0x01004bb4: 636e7546 Func DCD 1668183366 - 0x01004bb8: 6e6f6974 tion DCD 1852795252 - 0x01004bbc: 5d73255b [%s] DCD 1567827291 - 0x01004bc0: 61687320 sha DCD 1634235168 - 0x01004bc4: 6e206c6c ll n DCD 1847618668 - 0x01004bc8: 6220746f ot b DCD 1646294127 - 0x01004bcc: 73752065 e us DCD 1937055845 - 0x01004bd0: 69206465 ed i DCD 1763730533 - 0x01004bd4: 5349206e n IS DCD 1397301358 - 0x01004bd8: 00000a52 R... DCD 2642 - 0x01004bdc: 00000030 0... DCD 48 - 0x01004be0: 6f666e69 info DCD 1868983913 - 0x01004be4: 74616d72 rmat DCD 1952542066 - 0x01004be8: 206e6f69 ion DCD 544108393 - 0x01004bec: 52203d21 != R DCD 1377844513 - 0x01004bf0: 554e5f54 T_NU DCD 1431199572 - 0x01004bf4: 00004c4c LL.. DCD 19532 - 0x01004bf8: 00020108 .... DCD 131336 - $t - i.rt_object_delete - rt_object_delete - 0x01004bfc: b570 p. PUSH {r4-r6,lr} - 0x01004bfe: 4604 .F MOV r4,r0 - 0x01004c00: 2c00 ., CMP r4,#0 - 0x01004c02: d105 .. BNE 0x1004c10 ; rt_object_delete + 20 - 0x01004c04: 22ff ." MOVS r2,#0xff - 0x01004c06: 32d8 .2 ADDS r2,r2,#0xd8 - 0x01004c08: 4914 .I LDR r1,[pc,#80] ; [0x1004c5c] = 0x1007a7f - 0x01004c0a: a015 .. ADR r0,{pc}+0x56 ; 0x1004c60 - 0x01004c0c: f7fefcf8 .... BL rt_assert_handler ; 0x1003600 - 0x01004c10: 7a20 z LDRB r0,[r4,#8] - 0x01004c12: 2180 .! MOVS r1,#0x80 - 0x01004c14: 4008 .@ ANDS r0,r0,r1 - 0x01004c16: 2800 .( CMP r0,#0 - 0x01004c18: d005 .. BEQ 0x1004c26 ; rt_object_delete + 42 - 0x01004c1a: 22ff ." MOVS r2,#0xff - 0x01004c1c: 32d9 .2 ADDS r2,r2,#0xd9 - 0x01004c1e: 490f .I LDR r1,[pc,#60] ; [0x1004c5c] = 0x1007a7f - 0x01004c20: a014 .. ADR r0,{pc}+0x54 ; 0x1004c74 - 0x01004c22: f7fefced .... BL rt_assert_handler ; 0x1003600 - 0x01004c26: bf00 .. NOP - 0x01004c28: 481d .H LDR r0,[pc,#116] ; [0x1004ca0] = 0x2010c - 0x01004c2a: 6800 .h LDR r0,[r0,#0] - 0x01004c2c: 2800 .( CMP r0,#0 - 0x01004c2e: d003 .. BEQ 0x1004c38 ; rt_object_delete + 60 - 0x01004c30: 4620 F MOV r0,r4 - 0x01004c32: 491b .I LDR r1,[pc,#108] ; [0x1004ca0] = 0x2010c - 0x01004c34: 6809 .h LDR r1,[r1,#0] - 0x01004c36: 4788 .G BLX r1 - 0x01004c38: bf00 .. NOP - 0x01004c3a: 2000 . MOVS r0,#0 - 0x01004c3c: 7220 r STRB r0,[r4,#8] - 0x01004c3e: f7fbfc3f ..?. BL rt_hw_interrupt_disable ; 0x10004c0 - 0x01004c42: 4605 .F MOV r5,r0 - 0x01004c44: 4620 F MOV r0,r4 - 0x01004c46: 300c .0 ADDS r0,r0,#0xc - 0x01004c48: f7fffcb8 .... BL rt_list_remove ; 0x10045bc - 0x01004c4c: 4628 (F MOV r0,r5 - 0x01004c4e: f7fbfc3b ..;. BL rt_hw_interrupt_enable ; 0x10004c8 - 0x01004c52: 4620 F MOV r0,r4 - 0x01004c54: f7fff93c ..<. BL rt_free ; 0x1003ed0 - 0x01004c58: bd70 p. POP {r4-r6,pc} - $d - 0x01004c5a: 0000 .. DCW 0 - 0x01004c5c: 01007a7f .z.. DCD 16808575 - 0x01004c60: 656a626f obje DCD 1701470831 - 0x01004c64: 21207463 ct ! DCD 555775075 - 0x01004c68: 5452203d = RT DCD 1414668349 - 0x01004c6c: 4c554e5f _NUL DCD 1280659039 - 0x01004c70: 0000004c L... DCD 76 - 0x01004c74: 626f2821 !(ob DCD 1651451937 - 0x01004c78: 7463656a ject DCD 1952671082 - 0x01004c7c: 79743e2d ->ty DCD 2037661229 - 0x01004c80: 26206570 pe & DCD 639657328 - 0x01004c84: 5f545220 RT_ DCD 1599361568 - 0x01004c88: 656a624f Obje DCD 1701470799 - 0x01004c8c: 435f7463 ct_C DCD 1130329187 - 0x01004c90: 7373616c lass DCD 1936941420 - 0x01004c94: 6174535f _Sta DCD 1635013471 - 0x01004c98: 29636974 tic) DCD 694380916 - 0x01004c9c: 00000000 .... DCD 0 - 0x01004ca0: 0002010c .... DCD 131340 - $t - i.rt_object_detach - rt_object_detach - 0x01004ca4: b570 p. PUSH {r4-r6,lr} - 0x01004ca6: 4604 .F MOV r4,r0 - 0x01004ca8: 2c00 ., CMP r4,#0 - 0x01004caa: d105 .. BNE 0x1004cb8 ; rt_object_detach + 20 - 0x01004cac: 22ff ." MOVS r2,#0xff - 0x01004cae: 3277 w2 ADDS r2,r2,#0x77 - 0x01004cb0: 490d .I LDR r1,[pc,#52] ; [0x1004ce8] = 0x1007a5b - 0x01004cb2: a00e .. ADR r0,{pc}+0x3a ; 0x1004cec - 0x01004cb4: f7fefca4 .... BL rt_assert_handler ; 0x1003600 - 0x01004cb8: bf00 .. NOP - 0x01004cba: 4811 .H LDR r0,[pc,#68] ; [0x1004d00] = 0x2010c - 0x01004cbc: 6800 .h LDR r0,[r0,#0] - 0x01004cbe: 2800 .( CMP r0,#0 - 0x01004cc0: d003 .. BEQ 0x1004cca ; rt_object_detach + 38 - 0x01004cc2: 4620 F MOV r0,r4 - 0x01004cc4: 490e .I LDR r1,[pc,#56] ; [0x1004d00] = 0x2010c - 0x01004cc6: 6809 .h LDR r1,[r1,#0] - 0x01004cc8: 4788 .G BLX r1 - 0x01004cca: bf00 .. NOP - 0x01004ccc: 2000 . MOVS r0,#0 - 0x01004cce: 7220 r STRB r0,[r4,#8] - 0x01004cd0: f7fbfbf6 .... BL rt_hw_interrupt_disable ; 0x10004c0 - 0x01004cd4: 4605 .F MOV r5,r0 - 0x01004cd6: 4620 F MOV r0,r4 - 0x01004cd8: 300c .0 ADDS r0,r0,#0xc - 0x01004cda: f7fffc6f ..o. BL rt_list_remove ; 0x10045bc - 0x01004cde: 4628 (F MOV r0,r5 - 0x01004ce0: f7fbfbf2 .... BL rt_hw_interrupt_enable ; 0x10004c8 - 0x01004ce4: bd70 p. POP {r4-r6,pc} - $d - 0x01004ce6: 0000 .. DCW 0 - 0x01004ce8: 01007a5b [z.. DCD 16808539 - 0x01004cec: 656a626f obje DCD 1701470831 - 0x01004cf0: 21207463 ct ! DCD 555775075 - 0x01004cf4: 5452203d = RT DCD 1414668349 - 0x01004cf8: 4c554e5f _NUL DCD 1280659039 - 0x01004cfc: 0000004c L... DCD 76 - 0x01004d00: 0002010c .... DCD 131340 - $t - i.rt_object_find - rt_object_find - 0x01004d04: b5fe .. PUSH {r1-r7,lr} - 0x01004d06: 4604 .F MOV r4,r0 - 0x01004d08: 460f .F MOV r7,r1 - 0x01004d0a: 2000 . MOVS r0,#0 - 0x01004d0c: 9001 .. STR r0,[sp,#4] - 0x01004d0e: 2500 .% MOVS r5,#0 - 0x01004d10: 2600 .& MOVS r6,#0 - 0x01004d12: 4638 8F MOV r0,r7 - 0x01004d14: f000f850 ..P. BL rt_object_get_information ; 0x1004db8 - 0x01004d18: 4606 .F MOV r6,r0 - 0x01004d1a: 2c00 ., CMP r4,#0 - 0x01004d1c: d001 .. BEQ 0x1004d22 ; rt_object_find + 30 - 0x01004d1e: 2e00 .. CMP r6,#0 - 0x01004d20: d101 .. BNE 0x1004d26 ; rt_object_find + 34 - 0x01004d22: 2000 . MOVS r0,#0 - 0x01004d24: bdfe .. POP {r1-r7,pc} - 0x01004d26: bf00 .. NOP - 0x01004d28: f7fbfbca .... BL rt_hw_interrupt_disable ; 0x10004c0 - 0x01004d2c: 9000 .. STR r0,[sp,#0] - 0x01004d2e: f7fffba5 .... BL rt_interrupt_get_nest ; 0x100447c - 0x01004d32: 2800 .( CMP r0,#0 - 0x01004d34: d008 .. BEQ 0x1004d48 ; rt_object_find + 68 - 0x01004d36: 4913 .I LDR r1,[pc,#76] ; [0x1004d84] = 0x1007abd - 0x01004d38: a013 .. ADR r0,{pc}+0x50 ; 0x1004d88 - 0x01004d3a: f7fffbc9 .... BL rt_kprintf ; 0x10044d0 - 0x01004d3e: 4a1c .J LDR r2,[pc,#112] ; [0x1004db0] = 0x229 - 0x01004d40: 4910 .I LDR r1,[pc,#64] ; [0x1004d84] = 0x1007abd - 0x01004d42: a01c .. ADR r0,{pc}+0x72 ; 0x1004db4 - 0x01004d44: f7fefc5c ..\. BL rt_assert_handler ; 0x1003600 - 0x01004d48: 9800 .. LDR r0,[sp,#0] - 0x01004d4a: f7fbfbbd .... BL rt_hw_interrupt_enable ; 0x10004c8 - 0x01004d4e: bf00 .. NOP - 0x01004d50: f7fff88a .... BL rt_enter_critical ; 0x1003e68 - 0x01004d54: 6875 uh LDR r5,[r6,#4] - 0x01004d56: e00e .. B 0x1004d76 ; rt_object_find + 114 - 0x01004d58: 4628 (F MOV r0,r5 - 0x01004d5a: 380c .8 SUBS r0,r0,#0xc - 0x01004d5c: 9001 .. STR r0,[sp,#4] - 0x01004d5e: 2208 ." MOVS r2,#8 - 0x01004d60: 4621 !F MOV r1,r4 - 0x01004d62: 9801 .. LDR r0,[sp,#4] - 0x01004d64: f000fed4 .... BL rt_strncmp ; 0x1005b10 - 0x01004d68: 2800 .( CMP r0,#0 - 0x01004d6a: d103 .. BNE 0x1004d74 ; rt_object_find + 112 - 0x01004d6c: f7fff88c .... BL rt_exit_critical ; 0x1003e88 - 0x01004d70: 9801 .. LDR r0,[sp,#4] - 0x01004d72: e7d7 .. B 0x1004d24 ; rt_object_find + 32 - 0x01004d74: 682d -h LDR r5,[r5,#0] - 0x01004d76: 1d30 0. ADDS r0,r6,#4 - 0x01004d78: 4285 .B CMP r5,r0 - 0x01004d7a: d1ed .. BNE 0x1004d58 ; rt_object_find + 84 - 0x01004d7c: f7fff884 .... BL rt_exit_critical ; 0x1003e88 - 0x01004d80: 2000 . MOVS r0,#0 - 0x01004d82: e7cf .. B 0x1004d24 ; rt_object_find + 32 - $d - 0x01004d84: 01007abd .z.. DCD 16808637 - 0x01004d88: 636e7546 Func DCD 1668183366 - 0x01004d8c: 6e6f6974 tion DCD 1852795252 - 0x01004d90: 5d73255b [%s] DCD 1567827291 - 0x01004d94: 61687320 sha DCD 1634235168 - 0x01004d98: 6e206c6c ll n DCD 1847618668 - 0x01004d9c: 6220746f ot b DCD 1646294127 - 0x01004da0: 73752065 e us DCD 1937055845 - 0x01004da4: 69206465 ed i DCD 1763730533 - 0x01004da8: 5349206e n IS DCD 1397301358 - 0x01004dac: 00000a52 R... DCD 2642 - 0x01004db0: 00000229 )... DCD 553 - 0x01004db4: 00000030 0... DCD 48 - $t - i.rt_object_get_information - rt_object_get_information - 0x01004db8: 4602 .F MOV r2,r0 - 0x01004dba: 2100 .! MOVS r1,#0 - 0x01004dbc: e008 .. B 0x1004dd0 ; rt_object_get_information + 24 - 0x01004dbe: 0108 .. LSLS r0,r1,#4 - 0x01004dc0: 4b05 .K LDR r3,[pc,#20] ; [0x1004dd8] = 0x20068 - 0x01004dc2: 5c18 .\ LDRB r0,[r3,r0] - 0x01004dc4: 4290 .B CMP r0,r2 - 0x01004dc6: d102 .. BNE 0x1004dce ; rt_object_get_information + 22 - 0x01004dc8: 0108 .. LSLS r0,r1,#4 - 0x01004dca: 18c0 .. ADDS r0,r0,r3 - 0x01004dcc: 4770 pG BX lr - 0x01004dce: 1c49 I. ADDS r1,r1,#1 - 0x01004dd0: 290a .) CMP r1,#0xa - 0x01004dd2: dbf4 .. BLT 0x1004dbe ; rt_object_get_information + 6 - 0x01004dd4: 2000 . MOVS r0,#0 - 0x01004dd6: e7f9 .. B 0x1004dcc ; rt_object_get_information + 20 - $d - 0x01004dd8: 00020068 h... DCD 131176 - $t - i.rt_object_get_length - rt_object_get_length - 0x01004ddc: b5f8 .. PUSH {r3-r7,lr} - 0x01004dde: 4607 .F MOV r7,r0 - 0x01004de0: 2500 .% MOVS r5,#0 - 0x01004de2: 2600 .& MOVS r6,#0 - 0x01004de4: 2400 .$ MOVS r4,#0 - 0x01004de6: 4638 8F MOV r0,r7 - 0x01004de8: f7ffffe6 .... BL rt_object_get_information ; 0x1004db8 - 0x01004dec: 4604 .F MOV r4,r0 - 0x01004dee: 2c00 ., CMP r4,#0 - 0x01004df0: d100 .. BNE 0x1004df4 ; rt_object_get_length + 24 - 0x01004df2: bdf8 .. POP {r3-r7,pc} - 0x01004df4: f7fbfb64 ..d. BL rt_hw_interrupt_disable ; 0x10004c0 - 0x01004df8: 9000 .. STR r0,[sp,#0] - 0x01004dfa: 6866 fh LDR r6,[r4,#4] - 0x01004dfc: e001 .. B 0x1004e02 ; rt_object_get_length + 38 - 0x01004dfe: 1c6d m. ADDS r5,r5,#1 - 0x01004e00: 6836 6h LDR r6,[r6,#0] - 0x01004e02: 1d20 . ADDS r0,r4,#4 - 0x01004e04: 4286 .B CMP r6,r0 - 0x01004e06: d1fa .. BNE 0x1004dfe ; rt_object_get_length + 34 - 0x01004e08: 9800 .. LDR r0,[sp,#0] - 0x01004e0a: f7fbfb5d ..]. BL rt_hw_interrupt_enable ; 0x10004c8 - 0x01004e0e: 4628 (F MOV r0,r5 - 0x01004e10: e7ef .. B 0x1004df2 ; rt_object_get_length + 22 - i.rt_object_get_pointers - rt_object_get_pointers - 0x01004e12: b5f7 .. PUSH {r0-r2,r4-r7,lr} - 0x01004e14: b082 .. SUB sp,sp,#8 - 0x01004e16: 4615 .F MOV r5,r2 - 0x01004e18: 2400 .$ MOVS r4,#0 - 0x01004e1a: 2600 .& MOVS r6,#0 - 0x01004e1c: 2700 .' MOVS r7,#0 - 0x01004e1e: 2d00 .- CMP r5,#0 - 0x01004e20: dc02 .. BGT 0x1004e28 ; rt_object_get_pointers + 22 - 0x01004e22: 2000 . MOVS r0,#0 - 0x01004e24: b005 .. ADD sp,sp,#0x14 - 0x01004e26: bdf0 .. POP {r4-r7,pc} - 0x01004e28: 9802 .. LDR r0,[sp,#8] - 0x01004e2a: f7ffffc5 .... BL rt_object_get_information ; 0x1004db8 - 0x01004e2e: 4607 .F MOV r7,r0 - 0x01004e30: 2f00 ./ CMP r7,#0 - 0x01004e32: d100 .. BNE 0x1004e36 ; rt_object_get_pointers + 36 - 0x01004e34: e7f6 .. B 0x1004e24 ; rt_object_get_pointers + 18 - 0x01004e36: f7fbfb43 ..C. BL rt_hw_interrupt_disable ; 0x10004c0 - 0x01004e3a: 9001 .. STR r0,[sp,#4] - 0x01004e3c: 687e ~h LDR r6,[r7,#4] - 0x01004e3e: e00b .. B 0x1004e58 ; rt_object_get_pointers + 70 - 0x01004e40: 4630 0F MOV r0,r6 - 0x01004e42: 380c .8 SUBS r0,r0,#0xc - 0x01004e44: 9000 .. STR r0,[sp,#0] - 0x01004e46: 00a2 .. LSLS r2,r4,#2 - 0x01004e48: 9903 .. LDR r1,[sp,#0xc] - 0x01004e4a: 9800 .. LDR r0,[sp,#0] - 0x01004e4c: 5088 .P STR r0,[r1,r2] - 0x01004e4e: 1c64 d. ADDS r4,r4,#1 - 0x01004e50: 42ac .B CMP r4,r5 - 0x01004e52: db00 .. BLT 0x1004e56 ; rt_object_get_pointers + 68 - 0x01004e54: e003 .. B 0x1004e5e ; rt_object_get_pointers + 76 - 0x01004e56: 6836 6h LDR r6,[r6,#0] - 0x01004e58: 1d38 8. ADDS r0,r7,#4 - 0x01004e5a: 4286 .B CMP r6,r0 - 0x01004e5c: d1f0 .. BNE 0x1004e40 ; rt_object_get_pointers + 46 - 0x01004e5e: bf00 .. NOP - 0x01004e60: 9801 .. LDR r0,[sp,#4] - 0x01004e62: f7fbfb31 ..1. BL rt_hw_interrupt_enable ; 0x10004c8 - 0x01004e66: 4620 F MOV r0,r4 - 0x01004e68: e7dc .. B 0x1004e24 ; rt_object_get_pointers + 18 - 0x01004e6a: 0000 .. MOVS r0,r0 - i.rt_object_get_type - rt_object_get_type - 0x01004e6c: b510 .. PUSH {r4,lr} - 0x01004e6e: 4604 .F MOV r4,r0 - 0x01004e70: 2c00 ., CMP r4,#0 - 0x01004e72: d105 .. BNE 0x1004e80 ; rt_object_get_type + 20 - 0x01004e74: 2283 ." MOVS r2,#0x83 - 0x01004e76: 0092 .. LSLS r2,r2,#2 - 0x01004e78: 4903 .I LDR r1,[pc,#12] ; [0x1004e88] = 0x1007aaa - 0x01004e7a: a004 .. ADR r0,{pc}+0x12 ; 0x1004e8c - 0x01004e7c: f7fefbc0 .... BL rt_assert_handler ; 0x1003600 - 0x01004e80: 7a20 z LDRB r0,[r4,#8] - 0x01004e82: 2180 .! MOVS r1,#0x80 - 0x01004e84: 4388 .C BICS r0,r0,r1 - 0x01004e86: bd10 .. POP {r4,pc} - $d - 0x01004e88: 01007aaa .z.. DCD 16808618 - 0x01004e8c: 656a626f obje DCD 1701470831 - 0x01004e90: 21207463 ct ! DCD 555775075 - 0x01004e94: 5452203d = RT DCD 1414668349 - 0x01004e98: 4c554e5f _NUL DCD 1280659039 - 0x01004e9c: 0000004c L... DCD 76 - $t - i.rt_object_init - rt_object_init - 0x01004ea0: b5f7 .. PUSH {r0-r2,r4-r7,lr} - 0x01004ea2: b082 .. SUB sp,sp,#8 - 0x01004ea4: 4604 .F MOV r4,r0 - 0x01004ea6: 460e .F MOV r6,r1 - 0x01004ea8: 2700 .' MOVS r7,#0 - 0x01004eaa: 4630 0F MOV r0,r6 - 0x01004eac: f7ffff84 .... BL rt_object_get_information ; 0x1004db8 - 0x01004eb0: 4605 .F MOV r5,r0 - 0x01004eb2: 2d00 .- CMP r5,#0 - 0x01004eb4: d105 .. BNE 0x1004ec2 ; rt_object_init + 34 - 0x01004eb6: 22ff ." MOVS r2,#0xff - 0x01004eb8: 323a :2 ADDS r2,r2,#0x3a - 0x01004eba: 491e .I LDR r1,[pc,#120] ; [0x1004f34] = 0x1007a4c - 0x01004ebc: a01e .. ADR r0,{pc}+0x7c ; 0x1004f38 - 0x01004ebe: f7fefb9f .... BL rt_assert_handler ; 0x1003600 - 0x01004ec2: f7feffd1 .... BL rt_enter_critical ; 0x1003e68 - 0x01004ec6: 686f oh LDR r7,[r5,#4] - 0x01004ec8: e00f .. B 0x1004eea ; rt_object_init + 74 - 0x01004eca: 4638 8F MOV r0,r7 - 0x01004ecc: 380c .8 SUBS r0,r0,#0xc - 0x01004ece: 9000 .. STR r0,[sp,#0] - 0x01004ed0: 9800 .. LDR r0,[sp,#0] - 0x01004ed2: 2800 .( CMP r0,#0 - 0x01004ed4: d008 .. BEQ 0x1004ee8 ; rt_object_init + 72 - 0x01004ed6: 9800 .. LDR r0,[sp,#0] - 0x01004ed8: 42a0 .B CMP r0,r4 - 0x01004eda: d105 .. BNE 0x1004ee8 ; rt_object_init + 72 - 0x01004edc: 22ff ." MOVS r2,#0xff - 0x01004ede: 324a J2 ADDS r2,r2,#0x4a - 0x01004ee0: 4914 .I LDR r1,[pc,#80] ; [0x1004f34] = 0x1007a4c - 0x01004ee2: a01b .. ADR r0,{pc}+0x6e ; 0x1004f50 - 0x01004ee4: f7fefb8c .... BL rt_assert_handler ; 0x1003600 - 0x01004ee8: 683f ?h LDR r7,[r7,#0] - 0x01004eea: 1d28 (. ADDS r0,r5,#4 - 0x01004eec: 4287 .B CMP r7,r0 - 0x01004eee: d1ec .. BNE 0x1004eca ; rt_object_init + 42 - 0x01004ef0: f7feffca .... BL rt_exit_critical ; 0x1003e88 - 0x01004ef4: 2080 . MOVS r0,#0x80 - 0x01004ef6: 4330 0C ORRS r0,r0,r6 - 0x01004ef8: 7220 r STRB r0,[r4,#8] - 0x01004efa: 2208 ." MOVS r2,#8 - 0x01004efc: 4620 F MOV r0,r4 - 0x01004efe: 9904 .. LDR r1,[sp,#0x10] - 0x01004f00: f000fe1b .... BL rt_strncpy ; 0x1005b3a - 0x01004f04: bf00 .. NOP - 0x01004f06: 4816 .H LDR r0,[pc,#88] ; [0x1004f60] = 0x20108 - 0x01004f08: 6800 .h LDR r0,[r0,#0] - 0x01004f0a: 2800 .( CMP r0,#0 - 0x01004f0c: d003 .. BEQ 0x1004f16 ; rt_object_init + 118 - 0x01004f0e: 4620 F MOV r0,r4 - 0x01004f10: 4913 .I LDR r1,[pc,#76] ; [0x1004f60] = 0x20108 - 0x01004f12: 6809 .h LDR r1,[r1,#0] - 0x01004f14: 4788 .G BLX r1 - 0x01004f16: bf00 .. NOP - 0x01004f18: f7fbfad2 .... BL rt_hw_interrupt_disable ; 0x10004c0 - 0x01004f1c: 9001 .. STR r0,[sp,#4] - 0x01004f1e: 4621 !F MOV r1,r4 - 0x01004f20: 310c .1 ADDS r1,r1,#0xc - 0x01004f22: 1d28 (. ADDS r0,r5,#4 - 0x01004f24: f7fffb09 .... BL rt_list_insert_after ; 0x100453a - 0x01004f28: 9801 .. LDR r0,[sp,#4] - 0x01004f2a: f7fbfacd .... BL rt_hw_interrupt_enable ; 0x10004c8 - 0x01004f2e: b005 .. ADD sp,sp,#0x14 - 0x01004f30: bdf0 .. POP {r4-r7,pc} - $d - 0x01004f32: 0000 .. DCW 0 - 0x01004f34: 01007a4c Lz.. DCD 16808524 - 0x01004f38: 6f666e69 info DCD 1868983913 - 0x01004f3c: 74616d72 rmat DCD 1952542066 - 0x01004f40: 206e6f69 ion DCD 544108393 - 0x01004f44: 52203d21 != R DCD 1377844513 - 0x01004f48: 554e5f54 T_NU DCD 1431199572 - 0x01004f4c: 00004c4c LL.. DCD 19532 - 0x01004f50: 206a626f obj DCD 543842927 - 0x01004f54: 6f203d21 != o DCD 1864383777 - 0x01004f58: 63656a62 bjec DCD 1667590754 - 0x01004f5c: 00000074 t... DCD 116 - 0x01004f60: 00020108 .... DCD 131336 - $t - i.rt_object_is_systemobject - rt_object_is_systemobject - 0x01004f64: b510 .. PUSH {r4,lr} - 0x01004f66: 4604 .F MOV r4,r0 - 0x01004f68: 2c00 ., CMP r4,#0 - 0x01004f6a: d105 .. BNE 0x1004f78 ; rt_object_is_systemobject + 20 - 0x01004f6c: 22ff ." MOVS r2,#0xff - 0x01004f6e: 32fa .2 ADDS r2,r2,#0xfa - 0x01004f70: 4906 .I LDR r1,[pc,#24] ; [0x1004f8c] = 0x1007a90 - 0x01004f72: a007 .. ADR r0,{pc}+0x1e ; 0x1004f90 - 0x01004f74: f7fefb44 ..D. BL rt_assert_handler ; 0x1003600 - 0x01004f78: 7a20 z LDRB r0,[r4,#8] - 0x01004f7a: 2180 .! MOVS r1,#0x80 - 0x01004f7c: 4008 .@ ANDS r0,r0,r1 - 0x01004f7e: 2800 .( CMP r0,#0 - 0x01004f80: d001 .. BEQ 0x1004f86 ; rt_object_is_systemobject + 34 - 0x01004f82: 2001 . MOVS r0,#1 - 0x01004f84: bd10 .. POP {r4,pc} - 0x01004f86: 2000 . MOVS r0,#0 - 0x01004f88: e7fc .. B 0x1004f84 ; rt_object_is_systemobject + 32 - $d - 0x01004f8a: 0000 .. DCW 0 - 0x01004f8c: 01007a90 .z.. DCD 16808592 - 0x01004f90: 656a626f obje DCD 1701470831 - 0x01004f94: 21207463 ct ! DCD 555775075 - 0x01004f98: 5452203d = RT DCD 1414668349 - 0x01004f9c: 4c554e5f _NUL DCD 1280659039 - 0x01004fa0: 0000004c L... DCD 76 - $t - i.rt_pin_mode - rt_pin_mode - 0x01004fa4: b570 p. PUSH {r4-r6,lr} - 0x01004fa6: 4604 .F MOV r4,r0 - 0x01004fa8: 460d .F MOV r5,r1 - 0x01004faa: 4808 .H LDR r0,[pc,#32] ; [0x1004fcc] = 0x20158 - 0x01004fac: 6c00 .l LDR r0,[r0,#0x40] - 0x01004fae: 2800 .( CMP r0,#0 - 0x01004fb0: d104 .. BNE 0x1004fbc ; rt_pin_mode + 24 - 0x01004fb2: 228a ." MOVS r2,#0x8a - 0x01004fb4: 4906 .I LDR r1,[pc,#24] ; [0x1004fd0] = 0x10072d4 - 0x01004fb6: a007 .. ADR r0,{pc}+0x1e ; 0x1004fd4 - 0x01004fb8: f7fefb22 ..". BL rt_assert_handler ; 0x1003600 - 0x01004fbc: 4803 .H LDR r0,[pc,#12] ; [0x1004fcc] = 0x20158 - 0x01004fbe: 6c00 .l LDR r0,[r0,#0x40] - 0x01004fc0: 462a *F MOV r2,r5 - 0x01004fc2: 4621 !F MOV r1,r4 - 0x01004fc4: 6803 .h LDR r3,[r0,#0] - 0x01004fc6: 4801 .H LDR r0,[pc,#4] ; [0x1004fcc] = 0x20158 - 0x01004fc8: 4798 .G BLX r3 - 0x01004fca: bd70 p. POP {r4-r6,pc} - $d - 0x01004fcc: 00020158 X... DCD 131416 - 0x01004fd0: 010072d4 .r.. DCD 16806612 - 0x01004fd4: 5f77685f _hw_ DCD 1601661023 - 0x01004fd8: 2e6e6970 pin. DCD 778987888 - 0x01004fdc: 2073706f ops DCD 544436335 - 0x01004fe0: 52203d21 != R DCD 1377844513 - 0x01004fe4: 554e5f54 T_NU DCD 1431199572 - 0x01004fe8: 00004c4c LL.. DCD 19532 - $t - i.rt_pin_write - rt_pin_write - 0x01004fec: b570 p. PUSH {r4-r6,lr} - 0x01004fee: 4604 .F MOV r4,r0 - 0x01004ff0: 460d .F MOV r5,r1 - 0x01004ff2: 4808 .H LDR r0,[pc,#32] ; [0x1005014] = 0x20158 - 0x01004ff4: 6c00 .l LDR r0,[r0,#0x40] - 0x01004ff6: 2800 .( CMP r0,#0 - 0x01004ff8: d104 .. BNE 0x1005004 ; rt_pin_write + 24 - 0x01004ffa: 2291 ." MOVS r2,#0x91 - 0x01004ffc: 4906 .I LDR r1,[pc,#24] ; [0x1005018] = 0x10072e0 - 0x01004ffe: a007 .. ADR r0,{pc}+0x1e ; 0x100501c - 0x01005000: f7fefafe .... BL rt_assert_handler ; 0x1003600 - 0x01005004: 4803 .H LDR r0,[pc,#12] ; [0x1005014] = 0x20158 - 0x01005006: 6c00 .l LDR r0,[r0,#0x40] - 0x01005008: 462a *F MOV r2,r5 - 0x0100500a: 4621 !F MOV r1,r4 - 0x0100500c: 6843 Ch LDR r3,[r0,#4] - 0x0100500e: 4801 .H LDR r0,[pc,#4] ; [0x1005014] = 0x20158 - 0x01005010: 4798 .G BLX r3 - 0x01005012: bd70 p. POP {r4-r6,pc} - $d - 0x01005014: 00020158 X... DCD 131416 - 0x01005018: 010072e0 .r.. DCD 16806624 - 0x0100501c: 5f77685f _hw_ DCD 1601661023 - 0x01005020: 2e6e6970 pin. DCD 778987888 - 0x01005024: 2073706f ops DCD 544436335 - 0x01005028: 52203d21 != R DCD 1377844513 - 0x0100502c: 554e5f54 T_NU DCD 1431199572 - 0x01005030: 00004c4c LL.. DCD 19532 - $t - i.rt_schedule - rt_schedule - 0x01005034: b5f8 .. PUSH {r3-r7,lr} - 0x01005036: f7fbfa43 ..C. BL rt_hw_interrupt_disable ; 0x10004c0 - 0x0100503a: 4606 .F MOV r6,r0 - 0x0100503c: 484f OH LDR r0,[pc,#316] ; [0x100517c] = 0x20028 - 0x0100503e: 8800 .. LDRH r0,[r0,#0] - 0x01005040: 2800 .( CMP r0,#0 - 0x01005042: d179 y. BNE 0x1005138 ; rt_schedule + 260 - 0x01005044: 484e NH LDR r0,[pc,#312] ; [0x1005180] = 0x20024 - 0x01005046: 6800 .h LDR r0,[r0,#0] - 0x01005048: 2800 .( CMP r0,#0 - 0x0100504a: d076 v. BEQ 0x100513a ; rt_schedule + 262 - 0x0100504c: 2700 .' MOVS r7,#0 - 0x0100504e: 4668 hF MOV r0,sp - 0x01005050: f7fcf988 .... BL _scheduler_get_highest_priority_thread ; 0x1001364 - 0x01005054: 4604 .F MOV r4,r0 - 0x01005056: 484b KH LDR r0,[pc,#300] ; [0x1005184] = 0x2002c - 0x01005058: 6800 .h LDR r0,[r0,#0] - 0x0100505a: 3020 0 ADDS r0,r0,#0x20 - 0x0100505c: 7d00 .} LDRB r0,[r0,#0x14] - 0x0100505e: 0740 @. LSLS r0,r0,#29 - 0x01005060: 0f40 @. LSRS r0,r0,#29 - 0x01005062: 2803 .( CMP r0,#3 - 0x01005064: d126 &. BNE 0x10050b4 ; rt_schedule + 128 - 0x01005066: 4847 GH LDR r0,[pc,#284] ; [0x1005184] = 0x2002c - 0x01005068: 6800 .h LDR r0,[r0,#0] - 0x0100506a: 3020 0 ADDS r0,r0,#0x20 - 0x0100506c: 7d40 @} LDRB r0,[r0,#0x15] - 0x0100506e: 9900 .. LDR r1,[sp,#0] - 0x01005070: 4288 .B CMP r0,r1 - 0x01005072: d202 .. BCS 0x100507a ; rt_schedule + 70 - 0x01005074: 4843 CH LDR r0,[pc,#268] ; [0x1005184] = 0x2002c - 0x01005076: 6804 .h LDR r4,[r0,#0] - 0x01005078: e012 .. B 0x10050a0 ; rt_schedule + 108 - 0x0100507a: 4842 BH LDR r0,[pc,#264] ; [0x1005184] = 0x2002c - 0x0100507c: 6800 .h LDR r0,[r0,#0] - 0x0100507e: 3020 0 ADDS r0,r0,#0x20 - 0x01005080: 7d40 @} LDRB r0,[r0,#0x15] - 0x01005082: 9900 .. LDR r1,[sp,#0] - 0x01005084: 4288 .B CMP r0,r1 - 0x01005086: d10a .. BNE 0x100509e ; rt_schedule + 106 - 0x01005088: 483e >H LDR r0,[pc,#248] ; [0x1005184] = 0x2002c - 0x0100508a: 6800 .h LDR r0,[r0,#0] - 0x0100508c: 3020 0 ADDS r0,r0,#0x20 - 0x0100508e: 7d00 .} LDRB r0,[r0,#0x14] - 0x01005090: 2108 .! MOVS r1,#8 - 0x01005092: 4008 .@ ANDS r0,r0,r1 - 0x01005094: 2800 .( CMP r0,#0 - 0x01005096: d102 .. BNE 0x100509e ; rt_schedule + 106 - 0x01005098: 483a :H LDR r0,[pc,#232] ; [0x1005184] = 0x2002c - 0x0100509a: 6804 .h LDR r4,[r0,#0] - 0x0100509c: e000 .. B 0x10050a0 ; rt_schedule + 108 - 0x0100509e: 2701 .' MOVS r7,#1 - 0x010050a0: 4838 8H LDR r0,[pc,#224] ; [0x1005184] = 0x2002c - 0x010050a2: 6800 .h LDR r0,[r0,#0] - 0x010050a4: 3020 0 ADDS r0,r0,#0x20 - 0x010050a6: 7d00 .} LDRB r0,[r0,#0x14] - 0x010050a8: 2108 .! MOVS r1,#8 - 0x010050aa: 4388 .C BICS r0,r0,r1 - 0x010050ac: 4935 5I LDR r1,[pc,#212] ; [0x1005184] = 0x2002c - 0x010050ae: 6809 .h LDR r1,[r1,#0] - 0x010050b0: 3120 1 ADDS r1,r1,#0x20 - 0x010050b2: 7508 .u STRB r0,[r1,#0x14] - 0x010050b4: 4833 3H LDR r0,[pc,#204] ; [0x1005184] = 0x2002c - 0x010050b6: 6800 .h LDR r0,[r0,#0] - 0x010050b8: 4284 .B CMP r4,r0 - 0x010050ba: d048 H. BEQ 0x100514e ; rt_schedule + 282 - 0x010050bc: 4932 2I LDR r1,[pc,#200] ; [0x1005188] = 0x20030 - 0x010050be: 9800 .. LDR r0,[sp,#0] - 0x010050c0: 7008 .p STRB r0,[r1,#0] - 0x010050c2: 4830 0H LDR r0,[pc,#192] ; [0x1005184] = 0x2002c - 0x010050c4: 6805 .h LDR r5,[r0,#0] - 0x010050c6: 6004 .` STR r4,[r0,#0] - 0x010050c8: bf00 .. NOP - 0x010050ca: 4830 0H LDR r0,[pc,#192] ; [0x100518c] = 0x20034 - 0x010050cc: 6800 .h LDR r0,[r0,#0] - 0x010050ce: 2800 .( CMP r0,#0 - 0x010050d0: d004 .. BEQ 0x10050dc ; rt_schedule + 168 - 0x010050d2: 4621 !F MOV r1,r4 - 0x010050d4: 4628 (F MOV r0,r5 - 0x010050d6: 4a2d -J LDR r2,[pc,#180] ; [0x100518c] = 0x20034 - 0x010050d8: 6812 .h LDR r2,[r2,#0] - 0x010050da: 4790 .G BLX r2 - 0x010050dc: bf00 .. NOP - 0x010050de: 2f00 ./ CMP r7,#0 - 0x010050e0: d002 .. BEQ 0x10050e8 ; rt_schedule + 180 - 0x010050e2: 4628 (F MOV r0,r5 - 0x010050e4: f000f858 ..X. BL rt_schedule_insert_thread ; 0x1005198 - 0x010050e8: 4620 F MOV r0,r4 - 0x010050ea: f000f8a5 .... BL rt_schedule_remove_thread ; 0x1005238 - 0x010050ee: 2034 4 MOVS r0,#0x34 - 0x010050f0: 5d00 .] LDRB r0,[r0,r4] - 0x010050f2: 08c0 .. LSRS r0,r0,#3 - 0x010050f4: 00c0 .. LSLS r0,r0,#3 - 0x010050f6: 2103 .! MOVS r1,#3 - 0x010050f8: 4308 .C ORRS r0,r0,r1 - 0x010050fa: 2134 4! MOVS r1,#0x34 - 0x010050fc: 5508 .U STRB r0,[r1,r4] - 0x010050fe: bf00 .. NOP - 0x01005100: bf00 .. NOP - 0x01005102: 4620 F MOV r0,r4 - 0x01005104: f7fcf8cc .... BL _rt_scheduler_stack_check ; 0x10012a0 - 0x01005108: 4821 !H LDR r0,[pc,#132] ; [0x1005190] = 0x20124 - 0x0100510a: 7800 .x LDRB r0,[r0,#0] - 0x0100510c: 2800 .( CMP r0,#0 - 0x0100510e: d115 .. BNE 0x100513c ; rt_schedule + 264 - 0x01005110: bf00 .. NOP - 0x01005112: 4820 H LDR r0,[pc,#128] ; [0x1005194] = 0x20038 - 0x01005114: 6800 .h LDR r0,[r0,#0] - 0x01005116: 2800 .( CMP r0,#0 - 0x01005118: d003 .. BEQ 0x1005122 ; rt_schedule + 238 - 0x0100511a: 4628 (F MOV r0,r5 - 0x0100511c: 491d .I LDR r1,[pc,#116] ; [0x1005194] = 0x20038 - 0x0100511e: 6809 .h LDR r1,[r1,#0] - 0x01005120: 4788 .G BLX r1 - 0x01005122: bf00 .. NOP - 0x01005124: 4621 !F MOV r1,r4 - 0x01005126: 311c .1 ADDS r1,r1,#0x1c - 0x01005128: 4628 (F MOV r0,r5 - 0x0100512a: 301c .0 ADDS r0,r0,#0x1c - 0x0100512c: f7fbf9cf .... BL rt_hw_context_switch ; 0x10004ce - 0x01005130: 4630 0F MOV r0,r6 - 0x01005132: f7fbf9c9 .... BL rt_hw_interrupt_enable ; 0x10004c8 - 0x01005136: e020 . B 0x100517a ; rt_schedule + 326 - 0x01005138: e01b .. B 0x1005172 ; rt_schedule + 318 - 0x0100513a: e019 .. B 0x1005170 ; rt_schedule + 316 - 0x0100513c: bf00 .. NOP - 0x0100513e: bf00 .. NOP - 0x01005140: 4621 !F MOV r1,r4 - 0x01005142: 311c .1 ADDS r1,r1,#0x1c - 0x01005144: 4628 (F MOV r0,r5 - 0x01005146: 301c .0 ADDS r0,r0,#0x1c - 0x01005148: f7fbf9c1 .... BL rt_hw_context_switch ; 0x10004ce - 0x0100514c: e00f .. B 0x100516e ; rt_schedule + 314 - 0x0100514e: 480d .H LDR r0,[pc,#52] ; [0x1005184] = 0x2002c - 0x01005150: 6800 .h LDR r0,[r0,#0] - 0x01005152: f000f871 ..q. BL rt_schedule_remove_thread ; 0x1005238 - 0x01005156: 480b .H LDR r0,[pc,#44] ; [0x1005184] = 0x2002c - 0x01005158: 6800 .h LDR r0,[r0,#0] - 0x0100515a: 3020 0 ADDS r0,r0,#0x20 - 0x0100515c: 7d00 .} LDRB r0,[r0,#0x14] - 0x0100515e: 08c0 .. LSRS r0,r0,#3 - 0x01005160: 00c0 .. LSLS r0,r0,#3 - 0x01005162: 2103 .! MOVS r1,#3 - 0x01005164: 4308 .C ORRS r0,r0,r1 - 0x01005166: 4907 .I LDR r1,[pc,#28] ; [0x1005184] = 0x2002c - 0x01005168: 6809 .h LDR r1,[r1,#0] - 0x0100516a: 3120 1 ADDS r1,r1,#0x20 - 0x0100516c: 7508 .u STRB r0,[r1,#0x14] - 0x0100516e: bf00 .. NOP - 0x01005170: bf00 .. NOP - 0x01005172: 4630 0F MOV r0,r6 - 0x01005174: f7fbf9a8 .... BL rt_hw_interrupt_enable ; 0x10004c8 - 0x01005178: bf00 .. NOP - 0x0100517a: bdf8 .. POP {r3-r7,pc} - $d - 0x0100517c: 00020028 (... DCD 131112 - 0x01005180: 00020024 $... DCD 131108 - 0x01005184: 0002002c ,... DCD 131116 - 0x01005188: 00020030 0... DCD 131120 - 0x0100518c: 00020034 4... DCD 131124 - 0x01005190: 00020124 $... DCD 131364 - 0x01005194: 00020038 8... DCD 131128 - $t - i.rt_schedule_insert_thread - rt_schedule_insert_thread - 0x01005198: b570 p. PUSH {r4-r6,lr} - 0x0100519a: 4604 .F MOV r4,r0 - 0x0100519c: 2c00 ., CMP r4,#0 - 0x0100519e: d104 .. BNE 0x10051aa ; rt_schedule_insert_thread + 18 - 0x010051a0: 4a1b .J LDR r2,[pc,#108] ; [0x1005210] = 0x2c7 - 0x010051a2: 491c .I LDR r1,[pc,#112] ; [0x1005214] = 0x10075b2 - 0x010051a4: a01c .. ADR r0,{pc}+0x74 ; 0x1005218 - 0x010051a6: f7fefa2b ..+. BL rt_assert_handler ; 0x1003600 - 0x010051aa: f7fbf989 .... BL rt_hw_interrupt_disable ; 0x10004c0 - 0x010051ae: 4605 .F MOV r5,r0 - 0x010051b0: 481e .H LDR r0,[pc,#120] ; [0x100522c] = 0x2002c - 0x010051b2: 6800 .h LDR r0,[r0,#0] - 0x010051b4: 4284 .B CMP r4,r0 - 0x010051b6: d108 .. BNE 0x10051ca ; rt_schedule_insert_thread + 50 - 0x010051b8: 2034 4 MOVS r0,#0x34 - 0x010051ba: 5d00 .] LDRB r0,[r0,r4] - 0x010051bc: 08c0 .. LSRS r0,r0,#3 - 0x010051be: 00c0 .. LSLS r0,r0,#3 - 0x010051c0: 2103 .! MOVS r1,#3 - 0x010051c2: 4308 .C ORRS r0,r0,r1 - 0x010051c4: 2134 4! MOVS r1,#0x34 - 0x010051c6: 5508 .U STRB r0,[r1,r4] - 0x010051c8: e01e .. B 0x1005208 ; rt_schedule_insert_thread + 112 - 0x010051ca: 2034 4 MOVS r0,#0x34 - 0x010051cc: 5d00 .] LDRB r0,[r0,r4] - 0x010051ce: 08c0 .. LSRS r0,r0,#3 - 0x010051d0: 00c0 .. LSLS r0,r0,#3 - 0x010051d2: 2101 .! MOVS r1,#1 - 0x010051d4: 4308 .C ORRS r0,r0,r1 - 0x010051d6: 2134 4! MOVS r1,#0x34 - 0x010051d8: 5508 .U STRB r0,[r1,r4] - 0x010051da: 2235 5" MOVS r2,#0x35 - 0x010051dc: 5d12 .] LDRB r2,[r2,r4] - 0x010051de: 00d2 .. LSLS r2,r2,#3 - 0x010051e0: 4b13 .K LDR r3,[pc,#76] ; [0x1005230] = 0x20274 - 0x010051e2: 18d0 .. ADDS r0,r2,r3 - 0x010051e4: 4621 !F MOV r1,r4 - 0x010051e6: 3114 .1 ADDS r1,r1,#0x14 - 0x010051e8: 6842 Bh LDR r2,[r0,#4] - 0x010051ea: 6011 .` STR r1,[r2,#0] - 0x010051ec: 6842 Bh LDR r2,[r0,#4] - 0x010051ee: 604a J` STR r2,[r1,#4] - 0x010051f0: 6041 A` STR r1,[r0,#4] - 0x010051f2: 6008 .` STR r0,[r1,#0] - 0x010051f4: bf00 .. NOP - 0x010051f6: bf00 .. NOP - 0x010051f8: bf00 .. NOP - 0x010051fa: 490e .I LDR r1,[pc,#56] ; [0x1005234] = 0x20024 - 0x010051fc: 6ba0 .k LDR r0,[r4,#0x38] - 0x010051fe: 6809 .h LDR r1,[r1,#0] - 0x01005200: 4308 .C ORRS r0,r0,r1 - 0x01005202: 490c .I LDR r1,[pc,#48] ; [0x1005234] = 0x20024 - 0x01005204: 6008 .` STR r0,[r1,#0] - 0x01005206: bf00 .. NOP - 0x01005208: 4628 (F MOV r0,r5 - 0x0100520a: f7fbf95d ..]. BL rt_hw_interrupt_enable ; 0x10004c8 - 0x0100520e: bd70 p. POP {r4-r6,pc} - $d - 0x01005210: 000002c7 .... DCD 711 - 0x01005214: 010075b2 .u.. DCD 16807346 - 0x01005218: 65726874 thre DCD 1701996660 - 0x0100521c: 21206461 ad ! DCD 555770977 - 0x01005220: 5452203d = RT DCD 1414668349 - 0x01005224: 4c554e5f _NUL DCD 1280659039 - 0x01005228: 0000004c L... DCD 76 - 0x0100522c: 0002002c ,... DCD 131116 - 0x01005230: 00020274 t... DCD 131700 - 0x01005234: 00020024 $... DCD 131108 - $t - i.rt_schedule_remove_thread - rt_schedule_remove_thread - 0x01005238: b570 p. PUSH {r4-r6,lr} - 0x0100523a: 4604 .F MOV r4,r0 - 0x0100523c: 2c00 ., CMP r4,#0 - 0x0100523e: d105 .. BNE 0x100524c ; rt_schedule_remove_thread + 20 - 0x01005240: 2265 e" MOVS r2,#0x65 - 0x01005242: 00d2 .. LSLS r2,r2,#3 - 0x01005244: 4915 .I LDR r1,[pc,#84] ; [0x100529c] = 0x10075cc - 0x01005246: a016 .. ADR r0,{pc}+0x5a ; 0x10052a0 - 0x01005248: f7fef9da .... BL rt_assert_handler ; 0x1003600 - 0x0100524c: f7fbf938 ..8. BL rt_hw_interrupt_disable ; 0x10004c0 - 0x01005250: 4605 .F MOV r5,r0 - 0x01005252: bf00 .. NOP - 0x01005254: bf00 .. NOP - 0x01005256: 4620 F MOV r0,r4 - 0x01005258: 3014 .0 ADDS r0,r0,#0x14 - 0x0100525a: 6802 .h LDR r2,[r0,#0] - 0x0100525c: 6841 Ah LDR r1,[r0,#4] - 0x0100525e: 6051 Q` STR r1,[r2,#4] - 0x01005260: 6842 Bh LDR r2,[r0,#4] - 0x01005262: 6801 .h LDR r1,[r0,#0] - 0x01005264: 6011 .` STR r1,[r2,#0] - 0x01005266: 6040 @` STR r0,[r0,#4] - 0x01005268: 6000 .` STR r0,[r0,#0] - 0x0100526a: bf00 .. NOP - 0x0100526c: 2135 5! MOVS r1,#0x35 - 0x0100526e: 5d09 .] LDRB r1,[r1,r4] - 0x01005270: 00c9 .. LSLS r1,r1,#3 - 0x01005272: 4a10 .J LDR r2,[pc,#64] ; [0x10052b4] = 0x20274 - 0x01005274: 1888 .. ADDS r0,r1,r2 - 0x01005276: 6801 .h LDR r1,[r0,#0] - 0x01005278: 4281 .B CMP r1,r0 - 0x0100527a: d101 .. BNE 0x1005280 ; rt_schedule_remove_thread + 72 - 0x0100527c: 2101 .! MOVS r1,#1 - 0x0100527e: e000 .. B 0x1005282 ; rt_schedule_remove_thread + 74 - 0x01005280: 2100 .! MOVS r1,#0 - 0x01005282: 2900 .) CMP r1,#0 - 0x01005284: d005 .. BEQ 0x1005292 ; rt_schedule_remove_thread + 90 - 0x01005286: 480c .H LDR r0,[pc,#48] ; [0x10052b8] = 0x20024 - 0x01005288: 6ba1 .k LDR r1,[r4,#0x38] - 0x0100528a: 6800 .h LDR r0,[r0,#0] - 0x0100528c: 4388 .C BICS r0,r0,r1 - 0x0100528e: 490a .I LDR r1,[pc,#40] ; [0x10052b8] = 0x20024 - 0x01005290: 6008 .` STR r0,[r1,#0] - 0x01005292: 4628 (F MOV r0,r5 - 0x01005294: f7fbf918 .... BL rt_hw_interrupt_enable ; 0x10004c8 - 0x01005298: bd70 p. POP {r4-r6,pc} - $d - 0x0100529a: 0000 .. DCW 0 - 0x0100529c: 010075cc .u.. DCD 16807372 - 0x010052a0: 65726874 thre DCD 1701996660 - 0x010052a4: 21206461 ad ! DCD 555770977 - 0x010052a8: 5452203d = RT DCD 1414668349 - 0x010052ac: 4c554e5f _NUL DCD 1280659039 - 0x010052b0: 0000004c L... DCD 76 - 0x010052b4: 00020274 t... DCD 131700 - 0x010052b8: 00020024 $... DCD 131108 - $t - i.rt_sem_init - rt_sem_init - 0x010052bc: b5f8 .. PUSH {r3-r7,lr} - 0x010052be: 4604 .F MOV r4,r0 - 0x010052c0: 460e .F MOV r6,r1 - 0x010052c2: 4615 .F MOV r5,r2 - 0x010052c4: 461f .F MOV r7,r3 - 0x010052c6: 2c00 ., CMP r4,#0 - 0x010052c8: d105 .. BNE 0x10052d6 ; rt_sem_init + 26 - 0x010052ca: 22ff ." MOVS r2,#0xff - 0x010052cc: 3221 !2 ADDS r2,r2,#0x21 - 0x010052ce: 490d .I LDR r1,[pc,#52] ; [0x1005304] = 0x10077e7 - 0x010052d0: a00d .. ADR r0,{pc}+0x38 ; 0x1005308 - 0x010052d2: f7fef995 .... BL rt_assert_handler ; 0x1003600 - 0x010052d6: 2001 . MOVS r0,#1 - 0x010052d8: 0400 .. LSLS r0,r0,#16 - 0x010052da: 4285 .B CMP r5,r0 - 0x010052dc: d305 .. BCC 0x10052ea ; rt_sem_init + 46 - 0x010052de: 22ff ." MOVS r2,#0xff - 0x010052e0: 3222 "2 ADDS r2,r2,#0x22 - 0x010052e2: 4908 .I LDR r1,[pc,#32] ; [0x1005304] = 0x10077e7 - 0x010052e4: a00c .. ADR r0,{pc}+0x34 ; 0x1005318 - 0x010052e6: f7fef98b .... BL rt_assert_handler ; 0x1003600 - 0x010052ea: 4632 2F MOV r2,r6 - 0x010052ec: 2102 .! MOVS r1,#2 - 0x010052ee: 4620 F MOV r0,r4 - 0x010052f0: f7fffdd6 .... BL rt_object_init ; 0x1004ea0 - 0x010052f4: 4620 F MOV r0,r4 - 0x010052f6: f7fbfef3 .... BL _ipc_object_init ; 0x10010e0 - 0x010052fa: 83a5 .. STRH r5,[r4,#0x1c] - 0x010052fc: 7267 gr STRB r7,[r4,#9] - 0x010052fe: 2000 . MOVS r0,#0 - 0x01005300: bdf8 .. POP {r3-r7,pc} - $d - 0x01005302: 0000 .. DCW 0 - 0x01005304: 010077e7 .w.. DCD 16807911 - 0x01005308: 206d6573 sem DCD 544040307 - 0x0100530c: 52203d21 != R DCD 1377844513 - 0x01005310: 554e5f54 T_NU DCD 1431199572 - 0x01005314: 00004c4c LL.. DCD 19532 - 0x01005318: 756c6176 valu DCD 1970037110 - 0x0100531c: 203c2065 e < DCD 540811365 - 0x01005320: 30317830 0x10 DCD 808548400 - 0x01005324: 55303030 000U DCD 1429221424 - 0x01005328: 00000000 .... DCD 0 - $t - i.rt_sem_release - rt_sem_release - 0x0100532c: b570 p. PUSH {r4-r6,lr} - 0x0100532e: 4604 .F MOV r4,r0 - 0x01005330: 2c00 ., CMP r4,#0 - 0x01005332: d105 .. BNE 0x1005340 ; rt_sem_release + 20 - 0x01005334: 2225 %" MOVS r2,#0x25 - 0x01005336: 0112 .. LSLS r2,r2,#4 - 0x01005338: 4920 I LDR r1,[pc,#128] ; [0x10053bc] = 0x1007829 - 0x0100533a: a021 !. ADR r0,{pc}+0x86 ; 0x10053c0 - 0x0100533c: f7fef960 ..`. BL rt_assert_handler ; 0x1003600 - 0x01005340: 4620 F MOV r0,r4 - 0x01005342: f7fffd93 .... BL rt_object_get_type ; 0x1004e6c - 0x01005346: 2802 .( CMP r0,#2 - 0x01005348: d004 .. BEQ 0x1005354 ; rt_sem_release + 40 - 0x0100534a: 4a21 !J LDR r2,[pc,#132] ; [0x10053d0] = 0x251 - 0x0100534c: 491b .I LDR r1,[pc,#108] ; [0x10053bc] = 0x1007829 - 0x0100534e: 4821 !H LDR r0,[pc,#132] ; [0x10053d4] = 0x1007f08 - 0x01005350: f7fef956 ..V. BL rt_assert_handler ; 0x1003600 - 0x01005354: bf00 .. NOP - 0x01005356: 4820 H LDR r0,[pc,#128] ; [0x10053d8] = 0x20118 - 0x01005358: 6800 .h LDR r0,[r0,#0] - 0x0100535a: 2800 .( CMP r0,#0 - 0x0100535c: d003 .. BEQ 0x1005366 ; rt_sem_release + 58 - 0x0100535e: 4620 F MOV r0,r4 - 0x01005360: 491d .I LDR r1,[pc,#116] ; [0x10053d8] = 0x20118 - 0x01005362: 6809 .h LDR r1,[r1,#0] - 0x01005364: 4788 .G BLX r1 - 0x01005366: bf00 .. NOP - 0x01005368: 2500 .% MOVS r5,#0 - 0x0100536a: f7fbf8a9 .... BL rt_hw_interrupt_disable ; 0x10004c0 - 0x0100536e: 4606 .F MOV r6,r0 - 0x01005370: bf00 .. NOP - 0x01005372: bf00 .. NOP - 0x01005374: 4620 F MOV r0,r4 - 0x01005376: 3014 .0 ADDS r0,r0,#0x14 - 0x01005378: f7fff8fd .... BL rt_list_isempty ; 0x1004576 - 0x0100537c: 2800 .( CMP r0,#0 - 0x0100537e: d105 .. BNE 0x100538c ; rt_sem_release + 96 - 0x01005380: 4620 F MOV r0,r4 - 0x01005382: 3014 .0 ADDS r0,r0,#0x14 - 0x01005384: f7fbfe64 ..d. BL _ipc_list_resume ; 0x1001050 - 0x01005388: 2501 .% MOVS r5,#1 - 0x0100538a: e00d .. B 0x10053a8 ; rt_sem_release + 124 - 0x0100538c: 8ba0 .. LDRH r0,[r4,#0x1c] - 0x0100538e: 4913 .I LDR r1,[pc,#76] ; [0x10053dc] = 0xffff - 0x01005390: 4288 .B CMP r0,r1 - 0x01005392: da03 .. BGE 0x100539c ; rt_sem_release + 112 - 0x01005394: 8ba0 .. LDRH r0,[r4,#0x1c] - 0x01005396: 1c40 @. ADDS r0,r0,#1 - 0x01005398: 83a0 .. STRH r0,[r4,#0x1c] - 0x0100539a: e005 .. B 0x10053a8 ; rt_sem_release + 124 - 0x0100539c: 4630 0F MOV r0,r6 - 0x0100539e: f7fbf893 .... BL rt_hw_interrupt_enable ; 0x10004c8 - 0x010053a2: 2002 . MOVS r0,#2 - 0x010053a4: 43c0 .C MVNS r0,r0 - 0x010053a6: bd70 p. POP {r4-r6,pc} - 0x010053a8: 4630 0F MOV r0,r6 - 0x010053aa: f7fbf88d .... BL rt_hw_interrupt_enable ; 0x10004c8 - 0x010053ae: 2d01 .- CMP r5,#1 - 0x010053b0: d101 .. BNE 0x10053b6 ; rt_sem_release + 138 - 0x010053b2: f7fffe3f ..?. BL rt_schedule ; 0x1005034 - 0x010053b6: 2000 . MOVS r0,#0 - 0x010053b8: e7f5 .. B 0x10053a6 ; rt_sem_release + 122 - $d - 0x010053ba: 0000 .. DCW 0 - 0x010053bc: 01007829 )x.. DCD 16807977 - 0x010053c0: 206d6573 sem DCD 544040307 - 0x010053c4: 52203d21 != R DCD 1377844513 - 0x010053c8: 554e5f54 T_NU DCD 1431199572 - 0x010053cc: 00004c4c LL.. DCD 19532 - 0x010053d0: 00000251 Q... DCD 593 - 0x010053d4: 01007f08 .... DCD 16809736 - 0x010053d8: 00020118 .... DCD 131352 - 0x010053dc: 0000ffff .... DCD 65535 - $t - i.rt_sem_take - rt_sem_take - 0x010053e0: b5f3 .. PUSH {r0,r1,r4-r7,lr} - 0x010053e2: b081 .. SUB sp,sp,#4 - 0x010053e4: 4605 .F MOV r5,r0 - 0x010053e6: 2d00 .- CMP r5,#0 - 0x010053e8: d105 .. BNE 0x10053f6 ; rt_sem_take + 22 - 0x010053ea: 22ff ." MOVS r2,#0xff - 0x010053ec: 32d7 .2 ADDS r2,r2,#0xd7 - 0x010053ee: 4947 GI LDR r1,[pc,#284] ; [0x100550c] = 0x100781d - 0x010053f0: a047 G. ADR r0,{pc}+0x120 ; 0x1005510 - 0x010053f2: f7fef905 .... BL rt_assert_handler ; 0x1003600 - 0x010053f6: 4628 (F MOV r0,r5 - 0x010053f8: f7fffd38 ..8. BL rt_object_get_type ; 0x1004e6c - 0x010053fc: 2802 .( CMP r0,#2 - 0x010053fe: d005 .. BEQ 0x100540c ; rt_sem_take + 44 - 0x01005400: 22ff ." MOVS r2,#0xff - 0x01005402: 32d8 .2 ADDS r2,r2,#0xd8 - 0x01005404: 4941 AI LDR r1,[pc,#260] ; [0x100550c] = 0x100781d - 0x01005406: 4846 FH LDR r0,[pc,#280] ; [0x1005520] = 0x1007f08 - 0x01005408: f7fef8fa .... BL rt_assert_handler ; 0x1003600 - 0x0100540c: bf00 .. NOP - 0x0100540e: 4845 EH LDR r0,[pc,#276] ; [0x1005524] = 0x20110 - 0x01005410: 6800 .h LDR r0,[r0,#0] - 0x01005412: 2800 .( CMP r0,#0 - 0x01005414: d003 .. BEQ 0x100541e ; rt_sem_take + 62 - 0x01005416: 4628 (F MOV r0,r5 - 0x01005418: 4942 BI LDR r1,[pc,#264] ; [0x1005524] = 0x20110 - 0x0100541a: 6809 .h LDR r1,[r1,#0] - 0x0100541c: 4788 .G BLX r1 - 0x0100541e: bf00 .. NOP - 0x01005420: f7fbf84e ..N. BL rt_hw_interrupt_disable ; 0x10004c0 - 0x01005424: 4606 .F MOV r6,r0 - 0x01005426: bf00 .. NOP - 0x01005428: bf00 .. NOP - 0x0100542a: 8ba8 .. LDRH r0,[r5,#0x1c] - 0x0100542c: 2800 .( CMP r0,#0 - 0x0100542e: dd06 .. BLE 0x100543e ; rt_sem_take + 94 - 0x01005430: 8ba8 .. LDRH r0,[r5,#0x1c] - 0x01005432: 1e40 @. SUBS r0,r0,#1 - 0x01005434: 83a8 .. STRH r0,[r5,#0x1c] - 0x01005436: 4630 0F MOV r0,r6 - 0x01005438: f7fbf846 ..F. BL rt_hw_interrupt_enable ; 0x10004c8 - 0x0100543c: e05a Z. B 0x10054f4 ; rt_sem_take + 276 - 0x0100543e: 9802 .. LDR r0,[sp,#8] - 0x01005440: 2800 .( CMP r0,#0 - 0x01005442: d105 .. BNE 0x1005450 ; rt_sem_take + 112 - 0x01005444: 4630 0F MOV r0,r6 - 0x01005446: f7fbf83f ..?. BL rt_hw_interrupt_enable ; 0x10004c8 - 0x0100544a: 2001 . MOVS r0,#1 - 0x0100544c: 43c0 .C MVNS r0,r0 - 0x0100544e: bdfe .. POP {r1-r7,pc} - 0x01005450: bf00 .. NOP - 0x01005452: f7fbf835 ..5. BL rt_hw_interrupt_disable ; 0x10004c0 - 0x01005456: 9000 .. STR r0,[sp,#0] - 0x01005458: f000fda2 .... BL rt_thread_self ; 0x1005fa0 - 0x0100545c: 2800 .( CMP r0,#0 - 0x0100545e: d109 .. BNE 0x1005474 ; rt_sem_take + 148 - 0x01005460: 492a *I LDR r1,[pc,#168] ; [0x100550c] = 0x100781d - 0x01005462: a031 1. ADR r0,{pc}+0xc6 ; 0x1005528 - 0x01005464: f7fff834 ..4. BL rt_kprintf ; 0x10044d0 - 0x01005468: 22ff ." MOVS r2,#0xff - 0x0100546a: 32f8 .2 ADDS r2,r2,#0xf8 - 0x0100546c: 4927 'I LDR r1,[pc,#156] ; [0x100550c] = 0x100781d - 0x0100546e: a03c <. ADR r0,{pc}+0xf2 ; 0x1005560 - 0x01005470: f7fef8c6 .... BL rt_assert_handler ; 0x1003600 - 0x01005474: bf00 .. NOP - 0x01005476: f7fbf823 ..#. BL rt_hw_interrupt_disable ; 0x10004c0 - 0x0100547a: 4607 .F MOV r7,r0 - 0x0100547c: f7fefffe .... BL rt_interrupt_get_nest ; 0x100447c - 0x01005480: 2800 .( CMP r0,#0 - 0x01005482: d009 .. BEQ 0x1005498 ; rt_sem_take + 184 - 0x01005484: 4921 !I LDR r1,[pc,#132] ; [0x100550c] = 0x100781d - 0x01005486: a037 7. ADR r0,{pc}+0xde ; 0x1005564 - 0x01005488: f7fff822 ..". BL rt_kprintf ; 0x10044d0 - 0x0100548c: 22ff ." MOVS r2,#0xff - 0x0100548e: 32f8 .2 ADDS r2,r2,#0xf8 - 0x01005490: 491e .I LDR r1,[pc,#120] ; [0x100550c] = 0x100781d - 0x01005492: a033 3. ADR r0,{pc}+0xce ; 0x1005560 - 0x01005494: f7fef8b4 .... BL rt_assert_handler ; 0x1003600 - 0x01005498: 4638 8F MOV r0,r7 - 0x0100549a: f7fbf815 .... BL rt_hw_interrupt_enable ; 0x10004c8 - 0x0100549e: bf00 .. NOP - 0x010054a0: 9800 .. LDR r0,[sp,#0] - 0x010054a2: f7fbf811 .... BL rt_hw_interrupt_enable ; 0x10004c8 - 0x010054a6: bf00 .. NOP - 0x010054a8: f000fd7a ..z. BL rt_thread_self ; 0x1005fa0 - 0x010054ac: 4604 .F MOV r4,r0 - 0x010054ae: 2100 .! MOVS r1,#0 - 0x010054b0: 6321 !c STR r1,[r4,#0x30] - 0x010054b2: bf00 .. NOP - 0x010054b4: bf00 .. NOP - 0x010054b6: 7a6a jz LDRB r2,[r5,#9] - 0x010054b8: 4621 !F MOV r1,r4 - 0x010054ba: 4628 (F MOV r0,r5 - 0x010054bc: 3014 .0 ADDS r0,r0,#0x14 - 0x010054be: f7fbfdd3 .... BL _ipc_list_suspend ; 0x1001068 - 0x010054c2: 9802 .. LDR r0,[sp,#8] - 0x010054c4: 2800 .( CMP r0,#0 - 0x010054c6: dd0b .. BLE 0x10054e0 ; rt_sem_take + 256 - 0x010054c8: bf00 .. NOP - 0x010054ca: bf00 .. NOP - 0x010054cc: aa02 .. ADD r2,sp,#8 - 0x010054ce: 2100 .! MOVS r1,#0 - 0x010054d0: 4620 F MOV r0,r4 - 0x010054d2: 304c L0 ADDS r0,r0,#0x4c - 0x010054d4: f000ffa8 .... BL rt_timer_control ; 0x1006428 - 0x010054d8: 4620 F MOV r0,r4 - 0x010054da: 304c L0 ADDS r0,r0,#0x4c - 0x010054dc: f001f8aa .... BL rt_timer_start ; 0x1006634 - 0x010054e0: 4630 0F MOV r0,r6 - 0x010054e2: f7fafff1 .... BL rt_hw_interrupt_enable ; 0x10004c8 - 0x010054e6: f7fffda5 .... BL rt_schedule ; 0x1005034 - 0x010054ea: 6b20 k LDR r0,[r4,#0x30] - 0x010054ec: 2800 .( CMP r0,#0 - 0x010054ee: d001 .. BEQ 0x10054f4 ; rt_sem_take + 276 - 0x010054f0: 6b20 k LDR r0,[r4,#0x30] - 0x010054f2: e7ac .. B 0x100544e ; rt_sem_take + 110 - 0x010054f4: bf00 .. NOP - 0x010054f6: 4825 %H LDR r0,[pc,#148] ; [0x100558c] = 0x20114 - 0x010054f8: 6800 .h LDR r0,[r0,#0] - 0x010054fa: 2800 .( CMP r0,#0 - 0x010054fc: d003 .. BEQ 0x1005506 ; rt_sem_take + 294 - 0x010054fe: 4628 (F MOV r0,r5 - 0x01005500: 4922 "I LDR r1,[pc,#136] ; [0x100558c] = 0x20114 - 0x01005502: 6809 .h LDR r1,[r1,#0] - 0x01005504: 4788 .G BLX r1 - 0x01005506: bf00 .. NOP - 0x01005508: 2000 . MOVS r0,#0 - 0x0100550a: e7a0 .. B 0x100544e ; rt_sem_take + 110 - $d - 0x0100550c: 0100781d .x.. DCD 16807965 - 0x01005510: 206d6573 sem DCD 544040307 - 0x01005514: 52203d21 != R DCD 1377844513 - 0x01005518: 554e5f54 T_NU DCD 1431199572 - 0x0100551c: 00004c4c LL.. DCD 19532 - 0x01005520: 01007f08 .... DCD 16809736 - 0x01005524: 00020110 .... DCD 131344 - 0x01005528: 636e7546 Func DCD 1668183366 - 0x0100552c: 6e6f6974 tion DCD 1852795252 - 0x01005530: 5d73255b [%s] DCD 1567827291 - 0x01005534: 61687320 sha DCD 1634235168 - 0x01005538: 6e206c6c ll n DCD 1847618668 - 0x0100553c: 6220746f ot b DCD 1646294127 - 0x01005540: 73752065 e us DCD 1937055845 - 0x01005544: 62206465 ed b DCD 1646290021 - 0x01005548: 726f6665 efor DCD 1919903333 - 0x0100554c: 63732065 e sc DCD 1668489317 - 0x01005550: 75646568 hedu DCD 1969513832 - 0x01005554: 2072656c ler DCD 544367980 - 0x01005558: 72617473 star DCD 1918989427 - 0x0100555c: 00000a74 t... DCD 2676 - 0x01005560: 00000030 0... DCD 48 - 0x01005564: 636e7546 Func DCD 1668183366 - 0x01005568: 6e6f6974 tion DCD 1852795252 - 0x0100556c: 5d73255b [%s] DCD 1567827291 - 0x01005570: 61687320 sha DCD 1634235168 - 0x01005574: 6e206c6c ll n DCD 1847618668 - 0x01005578: 6220746f ot b DCD 1646294127 - 0x0100557c: 73752065 e us DCD 1937055845 - 0x01005580: 69206465 ed i DCD 1763730533 - 0x01005584: 5349206e n IS DCD 1397301358 - 0x01005588: 00000a52 R... DCD 2642 - 0x0100558c: 00020114 .... DCD 131348 - $t - i.rt_serial_close - rt_serial_close - 0x01005590: b570 p. PUSH {r4-r6,lr} - 0x01005592: 4604 .F MOV r4,r0 - 0x01005594: 2c00 ., CMP r4,#0 - 0x01005596: d104 .. BNE 0x10055a2 ; rt_serial_close + 18 - 0x01005598: 4a2b +J LDR r2,[pc,#172] ; [0x1005648] = 0x2e5 - 0x0100559a: 492c ,I LDR r1,[pc,#176] ; [0x100564c] = 0x1007360 - 0x0100559c: a02c ,. ADR r0,{pc}+0xb4 ; 0x1005650 - 0x0100559e: f7fef82f ../. BL rt_assert_handler ; 0x1003600 - 0x010055a2: 4625 %F MOV r5,r4 - 0x010055a4: 7ea0 .~ LDRB r0,[r4,#0x1a] - 0x010055a6: 2801 .( CMP r0,#1 - 0x010055a8: dd01 .. BLE 0x10055ae ; rt_serial_close + 30 - 0x010055aa: 2000 . MOVS r0,#0 - 0x010055ac: bd70 p. POP {r4-r6,pc} - 0x010055ae: 8b20 . LDRH r0,[r4,#0x18] - 0x010055b0: 21ff .! MOVS r1,#0xff - 0x010055b2: 3101 .1 ADDS r1,#1 - 0x010055b4: 4008 .@ ANDS r0,r0,r1 - 0x010055b6: 2800 .( CMP r0,#0 - 0x010055b8: d019 .. BEQ 0x10055ee ; rt_serial_close + 94 - 0x010055ba: 6c28 (l LDR r0,[r5,#0x40] - 0x010055bc: 460a .F MOV r2,r1 - 0x010055be: 2111 .! MOVS r1,#0x11 - 0x010055c0: 6843 Ch LDR r3,[r0,#4] - 0x010055c2: 4628 (F MOV r0,r5 - 0x010055c4: 4798 .G BLX r3 - 0x010055c6: 8b20 . LDRH r0,[r4,#0x18] - 0x010055c8: 21ff .! MOVS r1,#0xff - 0x010055ca: 3101 .1 ADDS r1,#1 - 0x010055cc: 4388 .C BICS r0,r0,r1 - 0x010055ce: 8320 . STRH r0,[r4,#0x18] - 0x010055d0: 6cee .l LDR r6,[r5,#0x4c] - 0x010055d2: 2e00 .. CMP r6,#0 - 0x010055d4: d105 .. BNE 0x10055e2 ; rt_serial_close + 82 - 0x010055d6: 22bd ." MOVS r2,#0xbd - 0x010055d8: 0092 .. LSLS r2,r2,#2 - 0x010055da: 491c .I LDR r1,[pc,#112] ; [0x100564c] = 0x1007360 - 0x010055dc: a020 . ADR r0,{pc}+0x84 ; 0x1005660 - 0x010055de: f7fef80f .... BL rt_assert_handler ; 0x1003600 - 0x010055e2: 4630 0F MOV r0,r6 - 0x010055e4: f7fefc74 ..t. BL rt_free ; 0x1003ed0 - 0x010055e8: 2000 . MOVS r0,#0 - 0x010055ea: 64e8 .d STR r0,[r5,#0x4c] - 0x010055ec: bf00 .. NOP - 0x010055ee: 8b20 . LDRH r0,[r4,#0x18] - 0x010055f0: 2101 .! MOVS r1,#1 - 0x010055f2: 0289 .. LSLS r1,r1,#10 - 0x010055f4: 4008 .@ ANDS r0,r0,r1 - 0x010055f6: 2800 .( CMP r0,#0 - 0x010055f8: d019 .. BEQ 0x100562e ; rt_serial_close + 158 - 0x010055fa: 6c28 (l LDR r0,[r5,#0x40] - 0x010055fc: 460a .F MOV r2,r1 - 0x010055fe: 2111 .! MOVS r1,#0x11 - 0x01005600: 6843 Ch LDR r3,[r0,#4] - 0x01005602: 4628 (F MOV r0,r5 - 0x01005604: 4798 .G BLX r3 - 0x01005606: 8b20 . LDRH r0,[r4,#0x18] - 0x01005608: 2101 .! MOVS r1,#1 - 0x0100560a: 0289 .. LSLS r1,r1,#10 - 0x0100560c: 4388 .C BICS r0,r0,r1 - 0x0100560e: 8320 . STRH r0,[r4,#0x18] - 0x01005610: 6d2e .m LDR r6,[r5,#0x50] - 0x01005612: 2e00 .. CMP r6,#0 - 0x01005614: d105 .. BNE 0x1005622 ; rt_serial_close + 146 - 0x01005616: 2219 ." MOVS r2,#0x19 - 0x01005618: 0152 R. LSLS r2,r2,#5 - 0x0100561a: 490c .I LDR r1,[pc,#48] ; [0x100564c] = 0x1007360 - 0x0100561c: a015 .. ADR r0,{pc}+0x58 ; 0x1005674 - 0x0100561e: f7fdffef .... BL rt_assert_handler ; 0x1003600 - 0x01005622: 4630 0F MOV r0,r6 - 0x01005624: f7fefc54 ..T. BL rt_free ; 0x1003ed0 - 0x01005628: 2000 . MOVS r0,#0 - 0x0100562a: 6528 (e STR r0,[r5,#0x50] - 0x0100562c: bf00 .. NOP - 0x0100562e: 6c28 (l LDR r0,[r5,#0x40] - 0x01005630: 2200 ." MOVS r2,#0 - 0x01005632: 2104 .! MOVS r1,#4 - 0x01005634: 6843 Ch LDR r3,[r0,#4] - 0x01005636: 4628 (F MOV r0,r5 - 0x01005638: 4798 .G BLX r3 - 0x0100563a: 8ae0 .. LDRH r0,[r4,#0x16] - 0x0100563c: 2110 .! MOVS r1,#0x10 - 0x0100563e: 4388 .C BICS r0,r0,r1 - 0x01005640: 82e0 .. STRH r0,[r4,#0x16] - 0x01005642: 2000 . MOVS r0,#0 - 0x01005644: e7b2 .. B 0x10055ac ; rt_serial_close + 28 - $d - 0x01005646: 0000 .. DCW 0 - 0x01005648: 000002e5 .... DCD 741 - 0x0100564c: 01007360 `s.. DCD 16806752 - 0x01005650: 20766564 dev DCD 544630116 - 0x01005654: 52203d21 != R DCD 1377844513 - 0x01005658: 554e5f54 T_NU DCD 1431199572 - 0x0100565c: 00004c4c LL.. DCD 19532 - 0x01005660: 665f7872 rx_f DCD 1717532786 - 0x01005664: 206f6669 ifo DCD 544171625 - 0x01005668: 52203d21 != R DCD 1377844513 - 0x0100566c: 554e5f54 T_NU DCD 1431199572 - 0x01005670: 00004c4c LL.. DCD 19532 - 0x01005674: 665f7874 tx_f DCD 1717532788 - 0x01005678: 206f6669 ifo DCD 544171625 - 0x0100567c: 52203d21 != R DCD 1377844513 - 0x01005680: 554e5f54 T_NU DCD 1431199572 - 0x01005684: 00004c4c LL.. DCD 19532 - $t - i.rt_serial_control - rt_serial_control - 0x01005688: b5f7 .. PUSH {r0-r2,r4-r7,lr} - 0x0100568a: b082 .. SUB sp,sp,#8 - 0x0100568c: 4605 .F MOV r5,r0 - 0x0100568e: 4616 .F MOV r6,r2 - 0x01005690: 2000 . MOVS r0,#0 - 0x01005692: 9001 .. STR r0,[sp,#4] - 0x01005694: 2d00 .- CMP r5,#0 - 0x01005696: d104 .. BNE 0x10056a2 ; rt_serial_control + 26 - 0x01005698: 4a20 J LDR r2,[pc,#128] ; [0x100571c] = 0x3dd - 0x0100569a: 4921 !I LDR r1,[pc,#132] ; [0x1005720] = 0x100738f - 0x0100569c: a021 !. ADR r0,{pc}+0x88 ; 0x1005724 - 0x0100569e: f7fdffaf .... BL rt_assert_handler ; 0x1003600 - 0x010056a2: 462c ,F MOV r4,r5 - 0x010056a4: 9803 .. LDR r0,[sp,#0xc] - 0x010056a6: 2801 .( CMP r0,#1 - 0x010056a8: d009 .. BEQ 0x10056be ; rt_serial_control + 54 - 0x010056aa: 2802 .( CMP r0,#2 - 0x010056ac: d002 .. BEQ 0x10056b4 ; rt_serial_control + 44 - 0x010056ae: 2803 .( CMP r0,#3 - 0x010056b0: d129 ). BNE 0x1005706 ; rt_serial_control + 126 - 0x010056b2: e009 .. B 0x10056c8 ; rt_serial_control + 64 - 0x010056b4: 8ae8 .. LDRH r0,[r5,#0x16] - 0x010056b6: 2120 ! MOVS r1,#0x20 - 0x010056b8: 4308 .C ORRS r0,r0,r1 - 0x010056ba: 82e8 .. STRH r0,[r5,#0x16] - 0x010056bc: e02b +. B 0x1005716 ; rt_serial_control + 142 - 0x010056be: 8ae8 .. LDRH r0,[r5,#0x16] - 0x010056c0: 2120 ! MOVS r1,#0x20 - 0x010056c2: 4388 .C BICS r0,r0,r1 - 0x010056c4: 82e8 .. STRH r0,[r5,#0x16] - 0x010056c6: e026 &. B 0x1005716 ; rt_serial_control + 142 - 0x010056c8: 2e00 .. CMP r6,#0 - 0x010056ca: d01b .. BEQ 0x1005704 ; rt_serial_control + 124 - 0x010056cc: 4637 7F MOV r7,r6 - 0x010056ce: 6878 xh LDR r0,[r7,#4] - 0x010056d0: 0180 .. LSLS r0,r0,#6 - 0x010056d2: 0c01 .. LSRS r1,r0,#16 - 0x010056d4: 6ca0 .l LDR r0,[r4,#0x48] - 0x010056d6: 0180 .. LSLS r0,r0,#6 - 0x010056d8: 0c00 .. LSRS r0,r0,#16 - 0x010056da: 4281 .B CMP r1,r0 - 0x010056dc: d005 .. BEQ 0x10056ea ; rt_serial_control + 98 - 0x010056de: 7ea0 .~ LDRB r0,[r4,#0x1a] - 0x010056e0: 2800 .( CMP r0,#0 - 0x010056e2: d002 .. BEQ 0x10056ea ; rt_serial_control + 98 - 0x010056e4: 2007 . MOVS r0,#7 - 0x010056e6: b005 .. ADD sp,sp,#0x14 - 0x010056e8: bdf0 .. POP {r4-r7,pc} - 0x010056ea: 687a zh LDR r2,[r7,#4] - 0x010056ec: 6839 9h LDR r1,[r7,#0] - 0x010056ee: 64a2 .d STR r2,[r4,#0x48] - 0x010056f0: 6461 ad STR r1,[r4,#0x44] - 0x010056f2: 7ea0 .~ LDRB r0,[r4,#0x1a] - 0x010056f4: 2800 .( CMP r0,#0 - 0x010056f6: d004 .. BEQ 0x1005702 ; rt_serial_control + 122 - 0x010056f8: 6c20 l LDR r0,[r4,#0x40] - 0x010056fa: 4631 1F MOV r1,r6 - 0x010056fc: 6802 .h LDR r2,[r0,#0] - 0x010056fe: 4620 F MOV r0,r4 - 0x01005700: 4790 .G BLX r2 - 0x01005702: bf00 .. NOP - 0x01005704: e007 .. B 0x1005716 ; rt_serial_control + 142 - 0x01005706: 6c20 l LDR r0,[r4,#0x40] - 0x01005708: 4632 2F MOV r2,r6 - 0x0100570a: 6843 Ch LDR r3,[r0,#4] - 0x0100570c: 4620 F MOV r0,r4 - 0x0100570e: 9903 .. LDR r1,[sp,#0xc] - 0x01005710: 4798 .G BLX r3 - 0x01005712: 9001 .. STR r0,[sp,#4] - 0x01005714: bf00 .. NOP - 0x01005716: bf00 .. NOP - 0x01005718: 9801 .. LDR r0,[sp,#4] - 0x0100571a: e7e4 .. B 0x10056e6 ; rt_serial_control + 94 - $d - 0x0100571c: 000003dd .... DCD 989 - 0x01005720: 0100738f .s.. DCD 16806799 - 0x01005724: 20766564 dev DCD 544630116 - 0x01005728: 52203d21 != R DCD 1377844513 - 0x0100572c: 554e5f54 T_NU DCD 1431199572 - 0x01005730: 00004c4c LL.. DCD 19532 - $t - i.rt_serial_init - rt_serial_init - 0x01005734: b570 p. PUSH {r4-r6,lr} - 0x01005736: 4605 .F MOV r5,r0 - 0x01005738: 2600 .& MOVS r6,#0 - 0x0100573a: 2d00 .- CMP r5,#0 - 0x0100573c: d104 .. BNE 0x1005748 ; rt_serial_init + 20 - 0x0100573e: 4a0b .J LDR r2,[pc,#44] ; [0x100576c] = 0x241 - 0x01005740: 490b .I LDR r1,[pc,#44] ; [0x1005770] = 0x1007342 - 0x01005742: a00c .. ADR r0,{pc}+0x32 ; 0x1005774 - 0x01005744: f7fdff5c ..\. BL rt_assert_handler ; 0x1003600 - 0x01005748: 462c ,F MOV r4,r5 - 0x0100574a: 2000 . MOVS r0,#0 - 0x0100574c: 64e0 .d STR r0,[r4,#0x4c] - 0x0100574e: 6520 e STR r0,[r4,#0x50] - 0x01005750: 6c20 l LDR r0,[r4,#0x40] - 0x01005752: 6800 .h LDR r0,[r0,#0] - 0x01005754: 2800 .( CMP r0,#0 - 0x01005756: d006 .. BEQ 0x1005766 ; rt_serial_init + 50 - 0x01005758: 6c20 l LDR r0,[r4,#0x40] - 0x0100575a: 4621 !F MOV r1,r4 - 0x0100575c: 3144 D1 ADDS r1,r1,#0x44 - 0x0100575e: 6802 .h LDR r2,[r0,#0] - 0x01005760: 4620 F MOV r0,r4 - 0x01005762: 4790 .G BLX r2 - 0x01005764: 4606 .F MOV r6,r0 - 0x01005766: 4630 0F MOV r0,r6 - 0x01005768: bd70 p. POP {r4-r6,pc} - $d - 0x0100576a: 0000 .. DCW 0 - 0x0100576c: 00000241 A... DCD 577 - 0x01005770: 01007342 Bs.. DCD 16806722 - 0x01005774: 20766564 dev DCD 544630116 - 0x01005778: 52203d21 != R DCD 1377844513 - 0x0100577c: 554e5f54 T_NU DCD 1431199572 - 0x01005780: 00004c4c LL.. DCD 19532 - $t - i.rt_serial_open - rt_serial_open - 0x01005784: b5f8 .. PUSH {r3-r7,lr} - 0x01005786: 4604 .F MOV r4,r0 - 0x01005788: 460e .F MOV r6,r1 - 0x0100578a: 2000 . MOVS r0,#0 - 0x0100578c: 9000 .. STR r0,[sp,#0] - 0x0100578e: 2c00 ., CMP r4,#0 - 0x01005790: d105 .. BNE 0x100579e ; rt_serial_open + 26 - 0x01005792: 2295 ." MOVS r2,#0x95 - 0x01005794: 0092 .. LSLS r2,r2,#2 - 0x01005796: 4960 `I LDR r1,[pc,#384] ; [0x1005918] = 0x1007351 - 0x01005798: a060 `. ADR r0,{pc}+0x184 ; 0x100591c - 0x0100579a: f7fdff31 ..1. BL rt_assert_handler ; 0x1003600 - 0x0100579e: 4625 %F MOV r5,r4 - 0x010057a0: 2001 . MOVS r0,#1 - 0x010057a2: 0240 @. LSLS r0,r0,#9 - 0x010057a4: 4030 0@ ANDS r0,r0,r6 - 0x010057a6: 2800 .( CMP r0,#0 - 0x010057a8: d008 .. BEQ 0x10057bc ; rt_serial_open + 56 - 0x010057aa: 8ae0 .. LDRH r0,[r4,#0x16] - 0x010057ac: 2101 .! MOVS r1,#1 - 0x010057ae: 0249 I. LSLS r1,r1,#9 - 0x010057b0: 4008 .@ ANDS r0,r0,r1 - 0x010057b2: 2800 .( CMP r0,#0 - 0x010057b4: d102 .. BNE 0x10057bc ; rt_serial_open + 56 - 0x010057b6: 2007 . MOVS r0,#7 - 0x010057b8: 43c0 .C MVNS r0,r0 - 0x010057ba: bdf8 .. POP {r3-r7,pc} - 0x010057bc: 2001 . MOVS r0,#1 - 0x010057be: 02c0 .. LSLS r0,r0,#11 - 0x010057c0: 4030 0@ ANDS r0,r0,r6 - 0x010057c2: 2800 .( CMP r0,#0 - 0x010057c4: d008 .. BEQ 0x10057d8 ; rt_serial_open + 84 - 0x010057c6: 8ae0 .. LDRH r0,[r4,#0x16] - 0x010057c8: 2101 .! MOVS r1,#1 - 0x010057ca: 02c9 .. LSLS r1,r1,#11 - 0x010057cc: 4008 .@ ANDS r0,r0,r1 - 0x010057ce: 2800 .( CMP r0,#0 - 0x010057d0: d102 .. BNE 0x10057d8 ; rt_serial_open + 84 - 0x010057d2: 2007 . MOVS r0,#7 - 0x010057d4: 43c0 .C MVNS r0,r0 - 0x010057d6: e7f0 .. B 0x10057ba ; rt_serial_open + 54 - 0x010057d8: 20ff . MOVS r0,#0xff - 0x010057da: 3001 .0 ADDS r0,#1 - 0x010057dc: 4030 0@ ANDS r0,r0,r6 - 0x010057de: 2800 .( CMP r0,#0 - 0x010057e0: d008 .. BEQ 0x10057f4 ; rt_serial_open + 112 - 0x010057e2: 8ae0 .. LDRH r0,[r4,#0x16] - 0x010057e4: 21ff .! MOVS r1,#0xff - 0x010057e6: 3101 .1 ADDS r1,#1 - 0x010057e8: 4008 .@ ANDS r0,r0,r1 - 0x010057ea: 2800 .( CMP r0,#0 - 0x010057ec: d102 .. BNE 0x10057f4 ; rt_serial_open + 112 - 0x010057ee: 2007 . MOVS r0,#7 - 0x010057f0: 43c0 .C MVNS r0,r0 - 0x010057f2: e7e2 .. B 0x10057ba ; rt_serial_open + 54 - 0x010057f4: 2001 . MOVS r0,#1 - 0x010057f6: 0280 .. LSLS r0,r0,#10 - 0x010057f8: 4030 0@ ANDS r0,r0,r6 - 0x010057fa: 2800 .( CMP r0,#0 - 0x010057fc: d008 .. BEQ 0x1005810 ; rt_serial_open + 140 - 0x010057fe: 8ae0 .. LDRH r0,[r4,#0x16] - 0x01005800: 2101 .! MOVS r1,#1 - 0x01005802: 0289 .. LSLS r1,r1,#10 - 0x01005804: 4008 .@ ANDS r0,r0,r1 - 0x01005806: 2800 .( CMP r0,#0 - 0x01005808: d102 .. BNE 0x1005810 ; rt_serial_open + 140 - 0x0100580a: 2007 . MOVS r0,#7 - 0x0100580c: 43c0 .C MVNS r0,r0 - 0x0100580e: e7d4 .. B 0x10057ba ; rt_serial_open + 54 - 0x01005810: 2040 @ MOVS r0,#0x40 - 0x01005812: 4030 0@ ANDS r0,r0,r6 - 0x01005814: 2800 .( CMP r0,#0 - 0x01005816: d104 .. BNE 0x1005822 ; rt_serial_open + 158 - 0x01005818: 8b20 . LDRH r0,[r4,#0x18] - 0x0100581a: 2140 @! MOVS r1,#0x40 - 0x0100581c: 4008 .@ ANDS r0,r0,r1 - 0x0100581e: 2800 .( CMP r0,#0 - 0x01005820: d001 .. BEQ 0x1005826 ; rt_serial_open + 162 - 0x01005822: 2040 @ MOVS r0,#0x40 - 0x01005824: 9000 .. STR r0,[sp,#0] - 0x01005826: b2f0 .. UXTB r0,r6 - 0x01005828: 8320 . STRH r0,[r4,#0x18] - 0x0100582a: 6ce8 .l LDR r0,[r5,#0x4c] - 0x0100582c: 2800 .( CMP r0,#0 - 0x0100582e: d131 1. BNE 0x1005894 ; rt_serial_open + 272 - 0x01005830: 20ff . MOVS r0,#0xff - 0x01005832: 3001 .0 ADDS r0,#1 - 0x01005834: 4030 0@ ANDS r0,r0,r6 - 0x01005836: 2800 .( CMP r0,#0 - 0x01005838: d029 ). BEQ 0x100588e ; rt_serial_open + 266 - 0x0100583a: 6ca9 .l LDR r1,[r5,#0x48] - 0x0100583c: 0189 .. LSLS r1,r1,#6 - 0x0100583e: 0c09 .. LSRS r1,r1,#16 - 0x01005840: 4608 .F MOV r0,r1 - 0x01005842: 300c .0 ADDS r0,r0,#0xc - 0x01005844: f7fefecc .... BL rt_malloc ; 0x10045e0 - 0x01005848: 4607 .F MOV r7,r0 - 0x0100584a: 2f00 ./ CMP r7,#0 - 0x0100584c: d104 .. BNE 0x1005858 ; rt_serial_open + 212 - 0x0100584e: 4a37 7J LDR r2,[pc,#220] ; [0x100592c] = 0x273 - 0x01005850: 4931 1I LDR r1,[pc,#196] ; [0x1005918] = 0x1007351 - 0x01005852: a037 7. ADR r0,{pc}+0xde ; 0x1005930 - 0x01005854: f7fdfed4 .... BL rt_assert_handler ; 0x1003600 - 0x01005858: 4638 8F MOV r0,r7 - 0x0100585a: 300c .0 ADDS r0,r0,#0xc - 0x0100585c: 6038 8` STR r0,[r7,#0] - 0x0100585e: 6ca9 .l LDR r1,[r5,#0x48] - 0x01005860: 0189 .. LSLS r1,r1,#6 - 0x01005862: 0c0a .. LSRS r2,r1,#16 - 0x01005864: 2100 .! MOVS r1,#0 - 0x01005866: 6838 8h LDR r0,[r7,#0] - 0x01005868: f7fff92b ..+. BL rt_memset ; 0x1004ac2 - 0x0100586c: 2000 . MOVS r0,#0 - 0x0100586e: 80b8 .. STRH r0,[r7,#4] - 0x01005870: 80f8 .. STRH r0,[r7,#6] - 0x01005872: 60b8 .` STR r0,[r7,#8] - 0x01005874: 64ef .d STR r7,[r5,#0x4c] - 0x01005876: 8b20 . LDRH r0,[r4,#0x18] - 0x01005878: 21ff .! MOVS r1,#0xff - 0x0100587a: 3101 .1 ADDS r1,#1 - 0x0100587c: 4308 .C ORRS r0,r0,r1 - 0x0100587e: 8320 . STRH r0,[r4,#0x18] - 0x01005880: 6c28 (l LDR r0,[r5,#0x40] - 0x01005882: 460a .F MOV r2,r1 - 0x01005884: 2110 .! MOVS r1,#0x10 - 0x01005886: 6843 Ch LDR r3,[r0,#4] - 0x01005888: 4628 (F MOV r0,r5 - 0x0100588a: 4798 .G BLX r3 - 0x0100588c: e00c .. B 0x10058a8 ; rt_serial_open + 292 - 0x0100588e: 2000 . MOVS r0,#0 - 0x01005890: 64e8 .d STR r0,[r5,#0x4c] - 0x01005892: e009 .. B 0x10058a8 ; rt_serial_open + 292 - 0x01005894: 20ff . MOVS r0,#0xff - 0x01005896: 3001 .0 ADDS r0,#1 - 0x01005898: 4030 0@ ANDS r0,r0,r6 - 0x0100589a: 2800 .( CMP r0,#0 - 0x0100589c: d004 .. BEQ 0x10058a8 ; rt_serial_open + 292 - 0x0100589e: 8b20 . LDRH r0,[r4,#0x18] - 0x010058a0: 21ff .! MOVS r1,#0xff - 0x010058a2: 3101 .1 ADDS r1,#1 - 0x010058a4: 4308 .C ORRS r0,r0,r1 - 0x010058a6: 8320 . STRH r0,[r4,#0x18] - 0x010058a8: 6d28 (m LDR r0,[r5,#0x50] - 0x010058aa: 2800 .( CMP r0,#0 - 0x010058ac: d123 #. BNE 0x10058f6 ; rt_serial_open + 370 - 0x010058ae: 2001 . MOVS r0,#1 - 0x010058b0: 0280 .. LSLS r0,r0,#10 - 0x010058b2: 4030 0@ ANDS r0,r0,r6 - 0x010058b4: 2800 .( CMP r0,#0 - 0x010058b6: d01b .. BEQ 0x10058f0 ; rt_serial_open + 364 - 0x010058b8: 200c . MOVS r0,#0xc - 0x010058ba: f7fefe91 .... BL rt_malloc ; 0x10045e0 - 0x010058be: 4607 .F MOV r7,r0 - 0x010058c0: 2f00 ./ CMP r7,#0 - 0x010058c2: d105 .. BNE 0x10058d0 ; rt_serial_open + 332 - 0x010058c4: 4a19 .J LDR r2,[pc,#100] ; [0x100592c] = 0x273 - 0x010058c6: 323f ?2 ADDS r2,r2,#0x3f - 0x010058c8: 4913 .I LDR r1,[pc,#76] ; [0x1005918] = 0x1007351 - 0x010058ca: a01e .. ADR r0,{pc}+0x7a ; 0x1005944 - 0x010058cc: f7fdfe98 .... BL rt_assert_handler ; 0x1003600 - 0x010058d0: 4638 8F MOV r0,r7 - 0x010058d2: f7fdff1b .... BL rt_completion_init ; 0x100370c - 0x010058d6: 652f /e STR r7,[r5,#0x50] - 0x010058d8: 8b20 . LDRH r0,[r4,#0x18] - 0x010058da: 2101 .! MOVS r1,#1 - 0x010058dc: 0289 .. LSLS r1,r1,#10 - 0x010058de: 4308 .C ORRS r0,r0,r1 - 0x010058e0: 8320 . STRH r0,[r4,#0x18] - 0x010058e2: 6c28 (l LDR r0,[r5,#0x40] - 0x010058e4: 460a .F MOV r2,r1 - 0x010058e6: 2110 .! MOVS r1,#0x10 - 0x010058e8: 6843 Ch LDR r3,[r0,#4] - 0x010058ea: 4628 (F MOV r0,r5 - 0x010058ec: 4798 .G BLX r3 - 0x010058ee: e00c .. B 0x100590a ; rt_serial_open + 390 - 0x010058f0: 2000 . MOVS r0,#0 - 0x010058f2: 6528 (e STR r0,[r5,#0x50] - 0x010058f4: e009 .. B 0x100590a ; rt_serial_open + 390 - 0x010058f6: 2001 . MOVS r0,#1 - 0x010058f8: 0280 .. LSLS r0,r0,#10 - 0x010058fa: 4030 0@ ANDS r0,r0,r6 - 0x010058fc: 2800 .( CMP r0,#0 - 0x010058fe: d004 .. BEQ 0x100590a ; rt_serial_open + 390 - 0x01005900: 8b20 . LDRH r0,[r4,#0x18] - 0x01005902: 2101 .! MOVS r1,#1 - 0x01005904: 0289 .. LSLS r1,r1,#10 - 0x01005906: 4308 .C ORRS r0,r0,r1 - 0x01005908: 8320 . STRH r0,[r4,#0x18] - 0x0100590a: 8b20 . LDRH r0,[r4,#0x18] - 0x0100590c: 9900 .. LDR r1,[sp,#0] - 0x0100590e: 4308 .C ORRS r0,r0,r1 - 0x01005910: 8320 . STRH r0,[r4,#0x18] - 0x01005912: 2000 . MOVS r0,#0 - 0x01005914: e751 Q. B 0x10057ba ; rt_serial_open + 54 - $d - 0x01005916: 0000 .. DCW 0 - 0x01005918: 01007351 Qs.. DCD 16806737 - 0x0100591c: 20766564 dev DCD 544630116 - 0x01005920: 52203d21 != R DCD 1377844513 - 0x01005924: 554e5f54 T_NU DCD 1431199572 - 0x01005928: 00004c4c LL.. DCD 19532 - 0x0100592c: 00000273 s... DCD 627 - 0x01005930: 665f7872 rx_f DCD 1717532786 - 0x01005934: 206f6669 ifo DCD 544171625 - 0x01005938: 52203d21 != R DCD 1377844513 - 0x0100593c: 554e5f54 T_NU DCD 1431199572 - 0x01005940: 00004c4c LL.. DCD 19532 - 0x01005944: 665f7874 tx_f DCD 1717532788 - 0x01005948: 206f6669 ifo DCD 544171625 - 0x0100594c: 52203d21 != R DCD 1377844513 - 0x01005950: 554e5f54 T_NU DCD 1431199572 - 0x01005954: 00004c4c LL.. DCD 19532 - $t - i.rt_serial_read - rt_serial_read - 0x01005958: b5f8 .. PUSH {r3-r7,lr} - 0x0100595a: 4604 .F MOV r4,r0 - 0x0100595c: 4617 .F MOV r7,r2 - 0x0100595e: 461d .F MOV r5,r3 - 0x01005960: 2c00 ., CMP r4,#0 - 0x01005962: d105 .. BNE 0x1005970 ; rt_serial_read + 24 - 0x01005964: 2269 i" MOVS r2,#0x69 - 0x01005966: 00d2 .. LSLS r2,r2,#3 - 0x01005968: 490d .I LDR r1,[pc,#52] ; [0x10059a0] = 0x1007370 - 0x0100596a: a00e .. ADR r0,{pc}+0x3a ; 0x10059a4 - 0x0100596c: f7fdfe48 ..H. BL rt_assert_handler ; 0x1003600 - 0x01005970: 2d00 .- CMP r5,#0 - 0x01005972: d101 .. BNE 0x1005978 ; rt_serial_read + 32 - 0x01005974: 2000 . MOVS r0,#0 - 0x01005976: bdf8 .. POP {r3-r7,pc} - 0x01005978: 4626 &F MOV r6,r4 - 0x0100597a: 8b20 . LDRH r0,[r4,#0x18] - 0x0100597c: 21ff .! MOVS r1,#0xff - 0x0100597e: 3101 .1 ADDS r1,#1 - 0x01005980: 4008 .@ ANDS r0,r0,r1 - 0x01005982: 2800 .( CMP r0,#0 - 0x01005984: d005 .. BEQ 0x1005992 ; rt_serial_read + 58 - 0x01005986: 462a *F MOV r2,r5 - 0x01005988: 4639 9F MOV r1,r7 - 0x0100598a: 4630 0F MOV r0,r6 - 0x0100598c: f7fbfd22 ..". BL _serial_int_rx ; 0x10013d4 - 0x01005990: e7f1 .. B 0x1005976 ; rt_serial_read + 30 - 0x01005992: 462a *F MOV r2,r5 - 0x01005994: 4639 9F MOV r1,r7 - 0x01005996: 4630 0F MOV r0,r6 - 0x01005998: f7fbfdc8 .... BL _serial_poll_rx ; 0x100152c - 0x0100599c: e7eb .. B 0x1005976 ; rt_serial_read + 30 - $d - 0x0100599e: 0000 .. DCW 0 - 0x010059a0: 01007370 ps.. DCD 16806768 - 0x010059a4: 20766564 dev DCD 544630116 - 0x010059a8: 52203d21 != R DCD 1377844513 - 0x010059ac: 554e5f54 T_NU DCD 1431199572 - 0x010059b0: 00004c4c LL.. DCD 19532 - $t - i.rt_serial_write - rt_serial_write - 0x010059b4: b5f8 .. PUSH {r3-r7,lr} - 0x010059b6: 4604 .F MOV r4,r0 - 0x010059b8: 4617 .F MOV r7,r2 - 0x010059ba: 461d .F MOV r5,r3 - 0x010059bc: 2c00 ., CMP r4,#0 - 0x010059be: d104 .. BNE 0x10059ca ; rt_serial_write + 22 - 0x010059c0: 4a0d .J LDR r2,[pc,#52] ; [0x10059f8] = 0x362 - 0x010059c2: 490e .I LDR r1,[pc,#56] ; [0x10059fc] = 0x100737f - 0x010059c4: a00e .. ADR r0,{pc}+0x3c ; 0x1005a00 - 0x010059c6: f7fdfe1b .... BL rt_assert_handler ; 0x1003600 - 0x010059ca: 2d00 .- CMP r5,#0 - 0x010059cc: d101 .. BNE 0x10059d2 ; rt_serial_write + 30 - 0x010059ce: 2000 . MOVS r0,#0 - 0x010059d0: bdf8 .. POP {r3-r7,pc} - 0x010059d2: 4626 &F MOV r6,r4 - 0x010059d4: 8b20 . LDRH r0,[r4,#0x18] - 0x010059d6: 2101 .! MOVS r1,#1 - 0x010059d8: 0289 .. LSLS r1,r1,#10 - 0x010059da: 4008 .@ ANDS r0,r0,r1 - 0x010059dc: 2800 .( CMP r0,#0 - 0x010059de: d005 .. BEQ 0x10059ec ; rt_serial_write + 56 - 0x010059e0: 462a *F MOV r2,r5 - 0x010059e2: 4639 9F MOV r1,r7 - 0x010059e4: 4630 0F MOV r0,r6 - 0x010059e6: f7fbfd53 ..S. BL _serial_int_tx ; 0x1001490 - 0x010059ea: e7f1 .. B 0x10059d0 ; rt_serial_write + 28 - 0x010059ec: 462a *F MOV r2,r5 - 0x010059ee: 4639 9F MOV r1,r7 - 0x010059f0: 4630 0F MOV r0,r6 - 0x010059f2: f7fbfdcf .... BL _serial_poll_tx ; 0x1001594 - 0x010059f6: e7eb .. B 0x10059d0 ; rt_serial_write + 28 - $d - 0x010059f8: 00000362 b... DCD 866 - 0x010059fc: 0100737f .s.. DCD 16806783 - 0x01005a00: 20766564 dev DCD 544630116 - 0x01005a04: 52203d21 != R DCD 1377844513 - 0x01005a08: 554e5f54 T_NU DCD 1431199572 - 0x01005a0c: 00004c4c LL.. DCD 19532 - $t - i.rt_set_errno - rt_set_errno - 0x01005a10: b570 p. PUSH {r4-r6,lr} - 0x01005a12: 4604 .F MOV r4,r0 - 0x01005a14: f7fefd32 ..2. BL rt_interrupt_get_nest ; 0x100447c - 0x01005a18: 2800 .( CMP r0,#0 - 0x01005a1a: d002 .. BEQ 0x1005a22 ; rt_set_errno + 18 - 0x01005a1c: 4806 .H LDR r0,[pc,#24] ; [0x1005a38] = 0x20048 - 0x01005a1e: 6004 .` STR r4,[r0,#0] - 0x01005a20: bd70 p. POP {r4-r6,pc} - 0x01005a22: f000fabd .... BL rt_thread_self ; 0x1005fa0 - 0x01005a26: 4605 .F MOV r5,r0 - 0x01005a28: 2d00 .- CMP r5,#0 - 0x01005a2a: d102 .. BNE 0x1005a32 ; rt_set_errno + 34 - 0x01005a2c: 4802 .H LDR r0,[pc,#8] ; [0x1005a38] = 0x20048 - 0x01005a2e: 6004 .` STR r4,[r0,#0] - 0x01005a30: e7f6 .. B 0x1005a20 ; rt_set_errno + 16 - 0x01005a32: 632c ,c STR r4,[r5,#0x30] - 0x01005a34: bf00 .. NOP - 0x01005a36: e7f3 .. B 0x1005a20 ; rt_set_errno + 16 - $d - 0x01005a38: 00020048 H... DCD 131144 - $t - i.rt_show_version - rt_show_version - 0x01005a3c: b508 .. PUSH {r3,lr} - 0x01005a3e: a009 .. ADR r0,{pc}+0x26 ; 0x1005a64 - 0x01005a40: f7fefd46 ..F. BL rt_kprintf ; 0x10044d0 - 0x01005a44: a00a .. ADR r0,{pc}+0x2c ; 0x1005a70 - 0x01005a46: f7fefd43 ..C. BL rt_kprintf ; 0x10044d0 - 0x01005a4a: a012 .. ADR r0,{pc}+0x4a ; 0x1005a94 - 0x01005a4c: 2304 .# MOVS r3,#4 - 0x01005a4e: 2200 ." MOVS r2,#0 - 0x01005a50: 4619 .F MOV r1,r3 - 0x01005a52: 9000 .. STR r0,[sp,#0] - 0x01005a54: a012 .. ADR r0,{pc}+0x4c ; 0x1005aa0 - 0x01005a56: f7fefd3b ..;. BL rt_kprintf ; 0x10044d0 - 0x01005a5a: a019 .. ADR r0,{pc}+0x66 ; 0x1005ac0 - 0x01005a5c: f7fefd38 ..8. BL rt_kprintf ; 0x10044d0 - 0x01005a60: bd08 .. POP {r3,pc} - $d - 0x01005a62: 0000 .. DCW 0 - 0x01005a64: 205c200a . \ DCD 542908426 - 0x01005a68: 0a2f207c | /. DCD 170860668 - 0x01005a6c: 00000000 .... DCD 0 - 0x01005a70: 5452202d - RT DCD 1414668333 - 0x01005a74: 20202d20 - DCD 538979616 - 0x01005a78: 54202020 T DCD 1411391520 - 0x01005a7c: 61657268 hrea DCD 1634038376 - 0x01005a80: 704f2064 d Op DCD 1884233828 - 0x01005a84: 74617265 erat DCD 1952543333 - 0x01005a88: 20676e69 ing DCD 543649385 - 0x01005a8c: 74737953 Syst DCD 1953724755 - 0x01005a90: 000a6d65 em.. DCD 683365 - 0x01005a94: 20706553 Sep DCD 544236883 - 0x01005a98: 32203920 9 2 DCD 840972576 - 0x01005a9c: 00313230 021. DCD 3224112 - 0x01005aa0: 7c202f20 / | DCD 2082484000 - 0x01005aa4: 20205c20 \ DCD 538991648 - 0x01005aa8: 25202020 % DCD 622862368 - 0x01005aac: 64252e64 d.%d DCD 1680158308 - 0x01005ab0: 2064252e .%d DCD 543434030 - 0x01005ab4: 6c697562 buil DCD 1818850658 - 0x01005ab8: 73252064 d %s DCD 1931812964 - 0x01005abc: 0000000a .... DCD 10 - 0x01005ac0: 30303220 200 DCD 808464928 - 0x01005ac4: 202d2036 6 - DCD 539828278 - 0x01005ac8: 31323032 2021 DCD 825372722 - 0x01005acc: 706f4320 Cop DCD 1886339872 - 0x01005ad0: 67697279 yrig DCD 1734963833 - 0x01005ad4: 62207468 ht b DCD 1646294120 - 0x01005ad8: 74722079 y rt DCD 1953636473 - 0x01005adc: 7268742d -thr DCD 1919448109 - 0x01005ae0: 20646165 ead DCD 543449445 - 0x01005ae4: 6d616574 team DCD 1835099508 - 0x01005ae8: 0000000a .... DCD 10 - $t - i.rt_sprintf - rt_sprintf - 0x01005aec: b40f .. PUSH {r0-r3} - 0x01005aee: b538 8. PUSH {r3-r5,lr} - 0x01005af0: 4604 .F MOV r4,r0 - 0x01005af2: a806 .. ADD r0,sp,#0x18 - 0x01005af4: 9000 .. STR r0,[sp,#0] - 0x01005af6: 4620 F MOV r0,r4 - 0x01005af8: 9a00 .. LDR r2,[sp,#0] - 0x01005afa: 9905 .. LDR r1,[sp,#0x14] - 0x01005afc: f001f8a4 .... BL rt_vsprintf ; 0x1006c48 - 0x01005b00: 4605 .F MOV r5,r0 - 0x01005b02: 2000 . MOVS r0,#0 - 0x01005b04: 9000 .. STR r0,[sp,#0] - 0x01005b06: 4628 (F MOV r0,r5 - 0x01005b08: bc38 8. POP {r3-r5} - 0x01005b0a: bc08 .. POP {r3} - 0x01005b0c: b004 .. ADD sp,sp,#0x10 - 0x01005b0e: 4718 .G BX r3 - i.rt_strncmp - rt_strncmp - 0x01005b10: b530 0. PUSH {r4,r5,lr} - 0x01005b12: 4603 .F MOV r3,r0 - 0x01005b14: 2000 . MOVS r0,#0 - 0x01005b16: e00c .. B 0x1005b32 ; rt_strncmp + 34 - 0x01005b18: 780d .x LDRB r5,[r1,#0] - 0x01005b1a: 1c49 I. ADDS r1,r1,#1 - 0x01005b1c: 781c .x LDRB r4,[r3,#0] - 0x01005b1e: 1b64 d. SUBS r4,r4,r5 - 0x01005b20: b264 d. SXTB r4,r4 - 0x01005b22: 1e20 . SUBS r0,r4,#0 - 0x01005b24: d103 .. BNE 0x1005b2e ; rt_strncmp + 30 - 0x01005b26: 781d .x LDRB r5,[r3,#0] - 0x01005b28: 1c5b [. ADDS r3,r3,#1 - 0x01005b2a: 2d00 .- CMP r5,#0 - 0x01005b2c: d100 .. BNE 0x1005b30 ; rt_strncmp + 32 - 0x01005b2e: e002 .. B 0x1005b36 ; rt_strncmp + 38 - 0x01005b30: 1e52 R. SUBS r2,r2,#1 - 0x01005b32: 2a00 .* CMP r2,#0 - 0x01005b34: d1f0 .. BNE 0x1005b18 ; rt_strncmp + 8 - 0x01005b36: bf00 .. NOP - 0x01005b38: bd30 0. POP {r4,r5,pc} - i.rt_strncpy - rt_strncpy - 0x01005b3a: b570 p. PUSH {r4-r6,lr} - 0x01005b3c: 4603 .F MOV r3,r0 - 0x01005b3e: 2a00 .* CMP r2,#0 - 0x01005b40: d015 .. BEQ 0x1005b6e ; rt_strncpy + 52 - 0x01005b42: 4618 .F MOV r0,r3 - 0x01005b44: 460c .F MOV r4,r1 - 0x01005b46: bf00 .. NOP - 0x01005b48: 7825 %x LDRB r5,[r4,#0] - 0x01005b4a: 7005 .p STRB r5,[r0,#0] - 0x01005b4c: 1c64 d. ADDS r4,r4,#1 - 0x01005b4e: 1c40 @. ADDS r0,r0,#1 - 0x01005b50: 2d00 .- CMP r5,#0 - 0x01005b52: d107 .. BNE 0x1005b64 ; rt_strncpy + 42 - 0x01005b54: e002 .. B 0x1005b5c ; rt_strncpy + 34 - 0x01005b56: 2500 .% MOVS r5,#0 - 0x01005b58: 7005 .p STRB r5,[r0,#0] - 0x01005b5a: 1c40 @. ADDS r0,r0,#1 - 0x01005b5c: 1e55 U. SUBS r5,r2,#1 - 0x01005b5e: 1e2a *. SUBS r2,r5,#0 - 0x01005b60: d1f9 .. BNE 0x1005b56 ; rt_strncpy + 28 - 0x01005b62: e002 .. B 0x1005b6a ; rt_strncpy + 48 - 0x01005b64: 1e55 U. SUBS r5,r2,#1 - 0x01005b66: 1e2a *. SUBS r2,r5,#0 - 0x01005b68: d1ee .. BNE 0x1005b48 ; rt_strncpy + 14 - 0x01005b6a: bf00 .. NOP - 0x01005b6c: bf00 .. NOP - 0x01005b6e: 4618 .F MOV r0,r3 - 0x01005b70: bd70 p. POP {r4-r6,pc} - 0x01005b72: 0000 .. MOVS r0,r0 - i.rt_system_heap_init - rt_system_heap_init - 0x01005b74: b5f3 .. PUSH {r0,r1,r4-r7,lr} - 0x01005b76: b081 .. SUB sp,sp,#4 - 0x01005b78: 4605 .F MOV r5,r0 - 0x01005b7a: 1ce8 .. ADDS r0,r5,#3 - 0x01005b7c: 0886 .. LSRS r6,r0,#2 - 0x01005b7e: 00b6 .. LSLS r6,r6,#2 - 0x01005b80: 9802 .. LDR r0,[sp,#8] - 0x01005b82: 0887 .. LSRS r7,r0,#2 - 0x01005b84: 00bf .. LSLS r7,r7,#2 - 0x01005b86: bf00 .. NOP - 0x01005b88: f7fafc9a .... BL rt_hw_interrupt_disable ; 0x10004c0 - 0x01005b8c: 9000 .. STR r0,[sp,#0] - 0x01005b8e: f7fefc75 ..u. BL rt_interrupt_get_nest ; 0x100447c - 0x01005b92: 2800 .( CMP r0,#0 - 0x01005b94: d008 .. BEQ 0x1005ba8 ; rt_system_heap_init + 52 - 0x01005b96: 4929 )I LDR r1,[pc,#164] ; [0x1005c3c] = 0x1007bfa - 0x01005b98: a029 ). ADR r0,{pc}+0xa8 ; 0x1005c40 - 0x01005b9a: f7fefc99 .... BL rt_kprintf ; 0x10044d0 - 0x01005b9e: 22d2 ." MOVS r2,#0xd2 - 0x01005ba0: 4926 &I LDR r1,[pc,#152] ; [0x1005c3c] = 0x1007bfa - 0x01005ba2: a031 1. ADR r0,{pc}+0xc6 ; 0x1005c68 - 0x01005ba4: f7fdfd2c ..,. BL rt_assert_handler ; 0x1003600 - 0x01005ba8: 9800 .. LDR r0,[sp,#0] - 0x01005baa: f7fafc8d .... BL rt_hw_interrupt_enable ; 0x10004c8 - 0x01005bae: bf00 .. NOP - 0x01005bb0: 2f18 ./ CMP r7,#0x18 - 0x01005bb2: d908 .. BLS 0x1005bc6 ; rt_system_heap_init + 82 - 0x01005bb4: 4638 8F MOV r0,r7 - 0x01005bb6: 3818 .8 SUBS r0,r0,#0x18 - 0x01005bb8: 42b0 .B CMP r0,r6 - 0x01005bba: d304 .. BCC 0x1005bc6 ; rt_system_heap_init + 82 - 0x01005bbc: 1bb8 .. SUBS r0,r7,r6 - 0x01005bbe: 3818 .8 SUBS r0,r0,#0x18 - 0x01005bc0: 492a *I LDR r1,[pc,#168] ; [0x1005c6c] = 0x20148 - 0x01005bc2: 6008 .` STR r0,[r1,#0] - 0x01005bc4: e005 .. B 0x1005bd2 ; rt_system_heap_init + 94 - 0x01005bc6: 4629 )F MOV r1,r5 - 0x01005bc8: a029 ). ADR r0,{pc}+0xa8 ; 0x1005c70 - 0x01005bca: 9a02 .. LDR r2,[sp,#8] - 0x01005bcc: f7fefc80 .... BL rt_kprintf ; 0x10044d0 - 0x01005bd0: bdfe .. POP {r1-r7,pc} - 0x01005bd2: 4836 6H LDR r0,[pc,#216] ; [0x1005cac] = 0x2013c - 0x01005bd4: 6006 .` STR r6,[r0,#0] - 0x01005bd6: bf00 .. NOP - 0x01005bd8: bf00 .. NOP - 0x01005bda: 6804 .h LDR r4,[r0,#0] - 0x01005bdc: 20f5 . MOVS r0,#0xf5 - 0x01005bde: 0140 @. LSLS r0,r0,#5 - 0x01005be0: 8020 . STRH r0,[r4,#0] - 0x01005be2: 4822 "H LDR r0,[pc,#136] ; [0x1005c6c] = 0x20148 - 0x01005be4: 6800 .h LDR r0,[r0,#0] - 0x01005be6: 300c .0 ADDS r0,r0,#0xc - 0x01005be8: 6060 `` STR r0,[r4,#4] - 0x01005bea: 2000 . MOVS r0,#0 - 0x01005bec: 60a0 .` STR r0,[r4,#8] - 0x01005bee: 8060 `. STRH r0,[r4,#2] - 0x01005bf0: 492e .I LDR r1,[pc,#184] ; [0x1005cac] = 0x2013c - 0x01005bf2: 6860 `h LDR r0,[r4,#4] - 0x01005bf4: 6809 .h LDR r1,[r1,#0] - 0x01005bf6: 1840 @. ADDS r0,r0,r1 - 0x01005bf8: 492d -I LDR r1,[pc,#180] ; [0x1005cb0] = 0x20140 - 0x01005bfa: 6008 .` STR r0,[r1,#0] - 0x01005bfc: 20f5 . MOVS r0,#0xf5 - 0x01005bfe: 0140 @. LSLS r0,r0,#5 - 0x01005c00: 6809 .h LDR r1,[r1,#0] - 0x01005c02: 8008 .. STRH r0,[r1,#0] - 0x01005c04: 2001 . MOVS r0,#1 - 0x01005c06: 492a *I LDR r1,[pc,#168] ; [0x1005cb0] = 0x20140 - 0x01005c08: 6809 .h LDR r1,[r1,#0] - 0x01005c0a: 8048 H. STRH r0,[r1,#2] - 0x01005c0c: 4817 .H LDR r0,[pc,#92] ; [0x1005c6c] = 0x20148 - 0x01005c0e: 6800 .h LDR r0,[r0,#0] - 0x01005c10: 300c .0 ADDS r0,r0,#0xc - 0x01005c12: 4927 'I LDR r1,[pc,#156] ; [0x1005cb0] = 0x20140 - 0x01005c14: 6809 .h LDR r1,[r1,#0] - 0x01005c16: 6048 H` STR r0,[r1,#4] - 0x01005c18: 4814 .H LDR r0,[pc,#80] ; [0x1005c6c] = 0x20148 - 0x01005c1a: 6800 .h LDR r0,[r0,#0] - 0x01005c1c: 300c .0 ADDS r0,r0,#0xc - 0x01005c1e: 4924 $I LDR r1,[pc,#144] ; [0x1005cb0] = 0x20140 - 0x01005c20: 6809 .h LDR r1,[r1,#0] - 0x01005c22: 6088 .` STR r0,[r1,#8] - 0x01005c24: 2301 .# MOVS r3,#1 - 0x01005c26: 461a .F MOV r2,r3 - 0x01005c28: a122 ". ADR r1,{pc}+0x8c ; 0x1005cb4 - 0x01005c2a: 4824 $H LDR r0,[pc,#144] ; [0x1005cbc] = 0x20584 - 0x01005c2c: f7fffb46 ..F. BL rt_sem_init ; 0x10052bc - 0x01005c30: 481e .H LDR r0,[pc,#120] ; [0x1005cac] = 0x2013c - 0x01005c32: 6800 .h LDR r0,[r0,#0] - 0x01005c34: 4922 "I LDR r1,[pc,#136] ; [0x1005cc0] = 0x20144 - 0x01005c36: 6008 .` STR r0,[r1,#0] - 0x01005c38: bf00 .. NOP - 0x01005c3a: e7c9 .. B 0x1005bd0 ; rt_system_heap_init + 92 - $d - 0x01005c3c: 01007bfa .{.. DCD 16808954 - 0x01005c40: 636e7546 Func DCD 1668183366 - 0x01005c44: 6e6f6974 tion DCD 1852795252 - 0x01005c48: 5d73255b [%s] DCD 1567827291 - 0x01005c4c: 61687320 sha DCD 1634235168 - 0x01005c50: 6e206c6c ll n DCD 1847618668 - 0x01005c54: 6220746f ot b DCD 1646294127 - 0x01005c58: 73752065 e us DCD 1937055845 - 0x01005c5c: 69206465 ed i DCD 1763730533 - 0x01005c60: 5349206e n IS DCD 1397301358 - 0x01005c64: 00000a52 R... DCD 2642 - 0x01005c68: 00000030 0... DCD 48 - 0x01005c6c: 00020148 H... DCD 131400 - 0x01005c70: 206d656d mem DCD 544040301 - 0x01005c74: 74696e69 init DCD 1953066601 - 0x01005c78: 7265202c , er DCD 1919229996 - 0x01005c7c: 20726f72 ror DCD 544370546 - 0x01005c80: 69676562 begi DCD 1768383842 - 0x01005c84: 6461206e n ad DCD 1684086894 - 0x01005c88: 73657264 dres DCD 1936028260 - 0x01005c8c: 78302073 s 0x DCD 2016419955 - 0x01005c90: 202c7825 %x, DCD 539785253 - 0x01005c94: 20646e61 and DCD 543452769 - 0x01005c98: 20646e65 end DCD 543452773 - 0x01005c9c: 72646461 addr DCD 1919181921 - 0x01005ca0: 20737365 ess DCD 544437093 - 0x01005ca4: 78257830 0x%x DCD 2015721520 - 0x01005ca8: 0000000a .... DCD 10 - 0x01005cac: 0002013c <... DCD 131388 - 0x01005cb0: 00020140 @... DCD 131392 - 0x01005cb4: 70616568 heap DCD 1885431144 - 0x01005cb8: 00000000 .... DCD 0 - 0x01005cbc: 00020584 .... DCD 132484 - 0x01005cc0: 00020144 D... DCD 131396 - $t - i.rt_system_scheduler_init - rt_system_scheduler_init - 0x01005cc4: 2100 .! MOVS r1,#0 - 0x01005cc6: 4a0a .J LDR r2,[pc,#40] ; [0x1005cf0] = 0x20028 - 0x01005cc8: 8011 .. STRH r1,[r2,#0] - 0x01005cca: bf00 .. NOP - 0x01005ccc: bf00 .. NOP - 0x01005cce: 2000 . MOVS r0,#0 - 0x01005cd0: e007 .. B 0x1005ce2 ; rt_system_scheduler_init + 30 - 0x01005cd2: 00c2 .. LSLS r2,r0,#3 - 0x01005cd4: 4b07 .K LDR r3,[pc,#28] ; [0x1005cf4] = 0x20274 - 0x01005cd6: 18d1 .. ADDS r1,r2,r3 - 0x01005cd8: 6049 I` STR r1,[r1,#4] - 0x01005cda: 6009 .` STR r1,[r1,#0] - 0x01005cdc: bf00 .. NOP - 0x01005cde: 1c41 A. ADDS r1,r0,#1 - 0x01005ce0: 4608 .F MOV r0,r1 - 0x01005ce2: 2820 ( CMP r0,#0x20 - 0x01005ce4: dbf5 .. BLT 0x1005cd2 ; rt_system_scheduler_init + 14 - 0x01005ce6: 2100 .! MOVS r1,#0 - 0x01005ce8: 4a03 .J LDR r2,[pc,#12] ; [0x1005cf8] = 0x20024 - 0x01005cea: 6011 .` STR r1,[r2,#0] - 0x01005cec: 4770 pG BX lr - $d - 0x01005cee: 0000 .. DCW 0 - 0x01005cf0: 00020028 (... DCD 131112 - 0x01005cf4: 00020274 t... DCD 131700 - 0x01005cf8: 00020024 $... DCD 131108 - $t - i.rt_system_scheduler_start - rt_system_scheduler_start - 0x01005cfc: b538 8. PUSH {r3-r5,lr} - 0x01005cfe: 4668 hF MOV r0,sp - 0x01005d00: f7fbfb30 ..0. BL _scheduler_get_highest_priority_thread ; 0x1001364 - 0x01005d04: 4604 .F MOV r4,r0 - 0x01005d06: 4806 .H LDR r0,[pc,#24] ; [0x1005d20] = 0x2002c - 0x01005d08: 6004 .` STR r4,[r0,#0] - 0x01005d0a: 4620 F MOV r0,r4 - 0x01005d0c: f7fffa94 .... BL rt_schedule_remove_thread ; 0x1005238 - 0x01005d10: 2103 .! MOVS r1,#3 - 0x01005d12: 2034 4 MOVS r0,#0x34 - 0x01005d14: 5501 .U STRB r1,[r0,r4] - 0x01005d16: 4620 F MOV r0,r4 - 0x01005d18: 301c .0 ADDS r0,r0,#0x1c - 0x01005d1a: f7fafc10 .... BL rt_hw_context_switch_to ; 0x100053e - 0x01005d1e: bd38 8. POP {r3-r5,pc} - $d - 0x01005d20: 0002002c ,... DCD 131116 - $t - i.rt_system_timer_init - rt_system_timer_init - 0x01005d24: b510 .. PUSH {r4,lr} - 0x01005d26: 2400 .$ MOVS r4,#0 - 0x01005d28: e005 .. B 0x1005d36 ; rt_system_timer_init + 18 - 0x01005d2a: 00e1 .. LSLS r1,r4,#3 - 0x01005d2c: 4a03 .J LDR r2,[pc,#12] ; [0x1005d3c] = 0x20054 - 0x01005d2e: 1888 .. ADDS r0,r1,r2 - 0x01005d30: f7fefbf9 .... BL rt_list_init ; 0x1004526 - 0x01005d34: 1c64 d. ADDS r4,r4,#1 - 0x01005d36: 2c00 ., CMP r4,#0 - 0x01005d38: d0f7 .. BEQ 0x1005d2a ; rt_system_timer_init + 6 - 0x01005d3a: bd10 .. POP {r4,pc} - $d - 0x01005d3c: 00020054 T... DCD 131156 - $t - i.rt_system_timer_thread_init - rt_system_timer_thread_init - 0x01005d40: 4770 pG BX lr - i.rt_thread_create - rt_thread_create - 0x01005d42: b5ff .. PUSH {r0-r7,lr} - 0x01005d44: b085 .. SUB sp,sp,#0x14 - 0x01005d46: 4606 .F MOV r6,r0 - 0x01005d48: 460f .F MOV r7,r1 - 0x01005d4a: 461d .F MOV r5,r3 - 0x01005d4c: 4631 1F MOV r1,r6 - 0x01005d4e: 2001 . MOVS r0,#1 - 0x01005d50: f7fefede .... BL rt_object_allocate ; 0x1004b10 - 0x01005d54: 9004 .. STR r0,[sp,#0x10] - 0x01005d56: 9804 .. LDR r0,[sp,#0x10] - 0x01005d58: 2800 .( CMP r0,#0 - 0x01005d5a: d101 .. BNE 0x1005d60 ; rt_thread_create + 30 - 0x01005d5c: b009 .. ADD sp,sp,#0x24 - 0x01005d5e: bdf0 .. POP {r4-r7,pc} - 0x01005d60: 4628 (F MOV r0,r5 - 0x01005d62: f7fefc3d ..=. BL rt_malloc ; 0x10045e0 - 0x01005d66: 4604 .F MOV r4,r0 - 0x01005d68: 2c00 ., CMP r4,#0 - 0x01005d6a: d104 .. BNE 0x1005d76 ; rt_thread_create + 52 - 0x01005d6c: 9804 .. LDR r0,[sp,#0x10] - 0x01005d6e: f7feff45 ..E. BL rt_object_delete ; 0x1004bfc - 0x01005d72: 2000 . MOVS r0,#0 - 0x01005d74: e7f2 .. B 0x1005d5c ; rt_thread_create + 26 - 0x01005d76: 990e .. LDR r1,[sp,#0x38] - 0x01005d78: 980f .. LDR r0,[sp,#0x3c] - 0x01005d7a: 9501 .. STR r5,[sp,#4] - 0x01005d7c: 9400 .. STR r4,[sp,#0] - 0x01005d7e: 9102 .. STR r1,[sp,#8] - 0x01005d80: 9003 .. STR r0,[sp,#0xc] - 0x01005d82: 463a :F MOV r2,r7 - 0x01005d84: 4631 1F MOV r1,r6 - 0x01005d86: 9b07 .. LDR r3,[sp,#0x1c] - 0x01005d88: 9804 .. LDR r0,[sp,#0x10] - 0x01005d8a: f7fbfc63 ..c. BL _thread_init ; 0x1001654 - 0x01005d8e: 9804 .. LDR r0,[sp,#0x10] - 0x01005d90: e7e4 .. B 0x1005d5c ; rt_thread_create + 26 - 0x01005d92: 0000 .. MOVS r0,r0 - i.rt_thread_defunct_dequeue - rt_thread_defunct_dequeue - 0x01005d94: b510 .. PUSH {r4,lr} - 0x01005d96: 2200 ." MOVS r2,#0 - 0x01005d98: 490a .I LDR r1,[pc,#40] ; [0x1005dc4] = 0x2003c - 0x01005d9a: 6808 .h LDR r0,[r1,#0] - 0x01005d9c: 4288 .B CMP r0,r1 - 0x01005d9e: d00e .. BEQ 0x1005dbe ; rt_thread_defunct_dequeue + 42 - 0x01005da0: 6808 .h LDR r0,[r1,#0] - 0x01005da2: 4602 .F MOV r2,r0 - 0x01005da4: 3a14 .: SUBS r2,r2,#0x14 - 0x01005da6: 4610 .F MOV r0,r2 - 0x01005da8: 3014 .0 ADDS r0,r0,#0x14 - 0x01005daa: 6804 .h LDR r4,[r0,#0] - 0x01005dac: 6843 Ch LDR r3,[r0,#4] - 0x01005dae: 6063 c` STR r3,[r4,#4] - 0x01005db0: 6844 Dh LDR r4,[r0,#4] - 0x01005db2: 6803 .h LDR r3,[r0,#0] - 0x01005db4: 6023 #` STR r3,[r4,#0] - 0x01005db6: 6040 @` STR r0,[r0,#4] - 0x01005db8: 6000 .` STR r0,[r0,#0] - 0x01005dba: bf00 .. NOP - 0x01005dbc: bf00 .. NOP - 0x01005dbe: 4610 .F MOV r0,r2 - 0x01005dc0: bd10 .. POP {r4,pc} - $d - 0x01005dc2: 0000 .. DCW 0 - 0x01005dc4: 0002003c <... DCD 131132 - $t - i.rt_thread_defunct_enqueue - rt_thread_defunct_enqueue - 0x01005dc8: 4602 .F MOV r2,r0 - 0x01005dca: 4805 .H LDR r0,[pc,#20] ; [0x1005de0] = 0x2003c - 0x01005dcc: 4611 .F MOV r1,r2 - 0x01005dce: 3114 .1 ADDS r1,r1,#0x14 - 0x01005dd0: 6803 .h LDR r3,[r0,#0] - 0x01005dd2: 6059 Y` STR r1,[r3,#4] - 0x01005dd4: 6803 .h LDR r3,[r0,#0] - 0x01005dd6: 600b .` STR r3,[r1,#0] - 0x01005dd8: 6001 .` STR r1,[r0,#0] - 0x01005dda: 6048 H` STR r0,[r1,#4] - 0x01005ddc: bf00 .. NOP - 0x01005dde: 4770 pG BX lr - $d - 0x01005de0: 0002003c <... DCD 131132 - $t - i.rt_thread_idle_entry - rt_thread_idle_entry - 0x01005de4: e00d .. B 0x1005e02 ; rt_thread_idle_entry + 30 - 0x01005de6: 2400 .$ MOVS r4,#0 - 0x01005de8: e006 .. B 0x1005df8 ; rt_thread_idle_entry + 20 - 0x01005dea: 00a0 .. LSLS r0,r4,#2 - 0x01005dec: 4905 .I LDR r1,[pc,#20] ; [0x1005e04] = 0x204f4 - 0x01005dee: 580d .X LDR r5,[r1,r0] - 0x01005df0: 2d00 .- CMP r5,#0 - 0x01005df2: d000 .. BEQ 0x1005df6 ; rt_thread_idle_entry + 18 - 0x01005df4: 47a8 .G BLX r5 - 0x01005df6: 1c64 d. ADDS r4,r4,#1 - 0x01005df8: 2c04 ., CMP r4,#4 - 0x01005dfa: d3f6 .. BCC 0x1005dea ; rt_thread_idle_entry + 6 - 0x01005dfc: f7fdfd8e .... BL rt_defunct_execute ; 0x100391c - 0x01005e00: bf00 .. NOP - 0x01005e02: e7f0 .. B 0x1005de6 ; rt_thread_idle_entry + 2 - $d - 0x01005e04: 000204f4 .... DCD 132340 - $t - i.rt_thread_idle_init - rt_thread_idle_init - 0x01005e08: b530 0. PUSH {r4,r5,lr} - 0x01005e0a: b087 .. SUB sp,sp,#0x1c - 0x01005e0c: 2400 .$ MOVS r4,#0 - 0x01005e0e: e01c .. B 0x1005e4a ; rt_thread_idle_init + 66 - 0x01005e10: 4622 "F MOV r2,r4 - 0x01005e12: a110 .. ADR r1,{pc}+0x42 ; 0x1005e54 - 0x01005e14: a805 .. ADD r0,sp,#0x14 - 0x01005e16: f7fffe69 ..i. BL rt_sprintf ; 0x1005aec - 0x01005e1a: 2120 ! MOVS r1,#0x20 - 0x01005e1c: 221f ." MOVS r2,#0x1f - 0x01005e1e: 00cb .. LSLS r3,r1,#3 - 0x01005e20: 0220 . LSLS r0,r4,#8 - 0x01005e22: 4d0e .M LDR r5,[pc,#56] ; [0x1005e5c] = 0x203f4 - 0x01005e24: 1940 @. ADDS r0,r0,r5 - 0x01005e26: 9301 .. STR r3,[sp,#4] - 0x01005e28: 9202 .. STR r2,[sp,#8] - 0x01005e2a: 9103 .. STR r1,[sp,#0xc] - 0x01005e2c: 9000 .. STR r0,[sp,#0] - 0x01005e2e: 01e1 .. LSLS r1,r4,#7 - 0x01005e30: 4a0b .J LDR r2,[pc,#44] ; [0x1005e60] = 0x20374 - 0x01005e32: 1888 .. ADDS r0,r1,r2 - 0x01005e34: 2300 .# MOVS r3,#0 - 0x01005e36: 4a0b .J LDR r2,[pc,#44] ; [0x1005e64] = 0x1005de5 - 0x01005e38: a905 .. ADD r1,sp,#0x14 - 0x01005e3a: f000f815 .... BL rt_thread_init ; 0x1005e68 - 0x01005e3e: 01e1 .. LSLS r1,r4,#7 - 0x01005e40: 4a07 .J LDR r2,[pc,#28] ; [0x1005e60] = 0x20374 - 0x01005e42: 1888 .. ADDS r0,r1,r2 - 0x01005e44: f000f8f4 .... BL rt_thread_startup ; 0x1006030 - 0x01005e48: 1c64 d. ADDS r4,r4,#1 - 0x01005e4a: 2c00 ., CMP r4,#0 - 0x01005e4c: d0e0 .. BEQ 0x1005e10 ; rt_thread_idle_init + 8 - 0x01005e4e: b007 .. ADD sp,sp,#0x1c - 0x01005e50: bd30 0. POP {r4,r5,pc} - $d - 0x01005e52: 0000 .. DCW 0 - 0x01005e54: 6c646974 tidl DCD 1818519924 - 0x01005e58: 00642565 e%d. DCD 6563173 - 0x01005e5c: 000203f4 .... DCD 132084 - 0x01005e60: 00020374 t... DCD 131956 - 0x01005e64: 01005de5 .].. DCD 16801253 - $t - i.rt_thread_init - rt_thread_init - 0x01005e68: b5ff .. PUSH {r0-r7,lr} - 0x01005e6a: b085 .. SUB sp,sp,#0x14 - 0x01005e6c: 4604 .F MOV r4,r0 - 0x01005e6e: 460d .F MOV r5,r1 - 0x01005e70: 9f0f .. LDR r7,[sp,#0x3c] - 0x01005e72: 9e0e .. LDR r6,[sp,#0x38] - 0x01005e74: 2c00 ., CMP r4,#0 - 0x01005e76: d105 .. BNE 0x1005e84 ; rt_thread_init + 28 - 0x01005e78: 22ff ." MOVS r2,#0xff - 0x01005e7a: 3210 .2 ADDS r2,r2,#0x10 - 0x01005e7c: 490f .I LDR r1,[pc,#60] ; [0x1005ebc] = 0x1007b3f - 0x01005e7e: a010 .. ADR r0,{pc}+0x42 ; 0x1005ec0 - 0x01005e80: f7fdfbbe .... BL rt_assert_handler ; 0x1003600 - 0x01005e84: 2e00 .. CMP r6,#0 - 0x01005e86: d105 .. BNE 0x1005e94 ; rt_thread_init + 44 - 0x01005e88: 22ff ." MOVS r2,#0xff - 0x01005e8a: 3211 .2 ADDS r2,r2,#0x11 - 0x01005e8c: 490b .I LDR r1,[pc,#44] ; [0x1005ebc] = 0x1007b3f - 0x01005e8e: a011 .. ADR r0,{pc}+0x46 ; 0x1005ed4 - 0x01005e90: f7fdfbb6 .... BL rt_assert_handler ; 0x1003600 - 0x01005e94: 462a *F MOV r2,r5 - 0x01005e96: 2101 .! MOVS r1,#1 - 0x01005e98: 4620 F MOV r0,r4 - 0x01005e9a: f7fff801 .... BL rt_object_init ; 0x1004ea0 - 0x01005e9e: 9910 .. LDR r1,[sp,#0x40] - 0x01005ea0: 9811 .. LDR r0,[sp,#0x44] - 0x01005ea2: 9701 .. STR r7,[sp,#4] - 0x01005ea4: 9600 .. STR r6,[sp,#0] - 0x01005ea6: 9102 .. STR r1,[sp,#8] - 0x01005ea8: 9003 .. STR r0,[sp,#0xc] - 0x01005eaa: 4629 )F MOV r1,r5 - 0x01005eac: 4620 F MOV r0,r4 - 0x01005eae: 9b08 .. LDR r3,[sp,#0x20] - 0x01005eb0: 9a07 .. LDR r2,[sp,#0x1c] - 0x01005eb2: f7fbfbcf .... BL _thread_init ; 0x1001654 - 0x01005eb6: b009 .. ADD sp,sp,#0x24 - 0x01005eb8: bdf0 .. POP {r4-r7,pc} - $d - 0x01005eba: 0000 .. DCW 0 - 0x01005ebc: 01007b3f ?{.. DCD 16808767 - 0x01005ec0: 65726874 thre DCD 1701996660 - 0x01005ec4: 21206461 ad ! DCD 555770977 - 0x01005ec8: 5452203d = RT DCD 1414668349 - 0x01005ecc: 4c554e5f _NUL DCD 1280659039 - 0x01005ed0: 0000004c L... DCD 76 - 0x01005ed4: 63617473 stac DCD 1667331187 - 0x01005ed8: 74735f6b k_st DCD 1953718123 - 0x01005edc: 20747261 art DCD 544502369 - 0x01005ee0: 52203d21 != R DCD 1377844513 - 0x01005ee4: 554e5f54 T_NU DCD 1431199572 - 0x01005ee8: 00004c4c LL.. DCD 19532 - $t - i.rt_thread_mdelay - rt_thread_mdelay - 0x01005eec: b570 p. PUSH {r4-r6,lr} - 0x01005eee: 4604 .F MOV r4,r0 - 0x01005ef0: 4620 F MOV r0,r4 - 0x01005ef2: f000f9d3 .... BL rt_tick_from_millisecond ; 0x100629c - 0x01005ef6: 4605 .F MOV r5,r0 - 0x01005ef8: 4628 (F MOV r0,r5 - 0x01005efa: f000f857 ..W. BL rt_thread_sleep ; 0x1005fac - 0x01005efe: bd70 p. POP {r4-r6,pc} - i.rt_thread_resume - rt_thread_resume - 0x01005f00: b570 p. PUSH {r4-r6,lr} - 0x01005f02: 4604 .F MOV r4,r0 - 0x01005f04: 2c00 ., CMP r4,#0 - 0x01005f06: d105 .. BNE 0x1005f14 ; rt_thread_resume + 20 - 0x01005f08: 22d1 ." MOVS r2,#0xd1 - 0x01005f0a: 0092 .. LSLS r2,r2,#2 - 0x01005f0c: 491b .I LDR r1,[pc,#108] ; [0x1005f7c] = 0x1007bcc - 0x01005f0e: a01c .. ADR r0,{pc}+0x72 ; 0x1005f80 - 0x01005f10: f7fdfb76 ..v. BL rt_assert_handler ; 0x1003600 - 0x01005f14: 4620 F MOV r0,r4 - 0x01005f16: f7feffa9 .... BL rt_object_get_type ; 0x1004e6c - 0x01005f1a: 2801 .( CMP r0,#1 - 0x01005f1c: d004 .. BEQ 0x1005f28 ; rt_thread_resume + 40 - 0x01005f1e: 4a1d .J LDR r2,[pc,#116] ; [0x1005f94] = 0x345 - 0x01005f20: 4916 .I LDR r1,[pc,#88] ; [0x1005f7c] = 0x1007bcc - 0x01005f22: 481d .H LDR r0,[pc,#116] ; [0x1005f98] = 0x1007f50 - 0x01005f24: f7fdfb6c ..l. BL rt_assert_handler ; 0x1003600 - 0x01005f28: bf00 .. NOP - 0x01005f2a: bf00 .. NOP - 0x01005f2c: 2034 4 MOVS r0,#0x34 - 0x01005f2e: 5d00 .] LDRB r0,[r0,r4] - 0x01005f30: 0740 @. LSLS r0,r0,#29 - 0x01005f32: 0f40 @. LSRS r0,r0,#29 - 0x01005f34: 2802 .( CMP r0,#2 - 0x01005f36: d004 .. BEQ 0x1005f42 ; rt_thread_resume + 66 - 0x01005f38: bf00 .. NOP - 0x01005f3a: bf00 .. NOP - 0x01005f3c: 2000 . MOVS r0,#0 - 0x01005f3e: 43c0 .C MVNS r0,r0 - 0x01005f40: bd70 p. POP {r4-r6,pc} - 0x01005f42: f7fafabd .... BL rt_hw_interrupt_disable ; 0x10004c0 - 0x01005f46: 4605 .F MOV r5,r0 - 0x01005f48: 4620 F MOV r0,r4 - 0x01005f4a: 3014 .0 ADDS r0,r0,#0x14 - 0x01005f4c: f7fefb3f ..?. BL rt_list_remove ; 0x10045ce - 0x01005f50: 4620 F MOV r0,r4 - 0x01005f52: 304c L0 ADDS r0,r0,#0x4c - 0x01005f54: f000fc58 ..X. BL rt_timer_stop ; 0x1006808 - 0x01005f58: 4620 F MOV r0,r4 - 0x01005f5a: f7fff91d .... BL rt_schedule_insert_thread ; 0x1005198 - 0x01005f5e: 4628 (F MOV r0,r5 - 0x01005f60: f7fafab2 .... BL rt_hw_interrupt_enable ; 0x10004c8 - 0x01005f64: bf00 .. NOP - 0x01005f66: 480d .H LDR r0,[pc,#52] ; [0x1005f9c] = 0x2012c - 0x01005f68: 6800 .h LDR r0,[r0,#0] - 0x01005f6a: 2800 .( CMP r0,#0 - 0x01005f6c: d003 .. BEQ 0x1005f76 ; rt_thread_resume + 118 - 0x01005f6e: 4620 F MOV r0,r4 - 0x01005f70: 490a .I LDR r1,[pc,#40] ; [0x1005f9c] = 0x2012c - 0x01005f72: 6809 .h LDR r1,[r1,#0] - 0x01005f74: 4788 .G BLX r1 - 0x01005f76: bf00 .. NOP - 0x01005f78: 2000 . MOVS r0,#0 - 0x01005f7a: e7e1 .. B 0x1005f40 ; rt_thread_resume + 64 - $d - 0x01005f7c: 01007bcc .{.. DCD 16808908 - 0x01005f80: 65726874 thre DCD 1701996660 - 0x01005f84: 21206461 ad ! DCD 555770977 - 0x01005f88: 5452203d = RT DCD 1414668349 - 0x01005f8c: 4c554e5f _NUL DCD 1280659039 - 0x01005f90: 0000004c L... DCD 76 - 0x01005f94: 00000345 E... DCD 837 - 0x01005f98: 01007f50 P... DCD 16809808 - 0x01005f9c: 0002012c ,... DCD 131372 - $t - i.rt_thread_self - rt_thread_self - 0x01005fa0: 4801 .H LDR r0,[pc,#4] ; [0x1005fa8] = 0x2002c - 0x01005fa2: 6800 .h LDR r0,[r0,#0] - 0x01005fa4: 4770 pG BX lr - $d - 0x01005fa6: 0000 .. DCW 0 - 0x01005fa8: 0002002c ,... DCD 131116 - $t - i.rt_thread_sleep - rt_thread_sleep - 0x01005fac: b531 1. PUSH {r0,r4,r5,lr} - 0x01005fae: f7fffff7 .... BL rt_thread_self ; 0x1005fa0 - 0x01005fb2: 4604 .F MOV r4,r0 - 0x01005fb4: 2c00 ., CMP r4,#0 - 0x01005fb6: d104 .. BNE 0x1005fc2 ; rt_thread_sleep + 22 - 0x01005fb8: 4a15 .J LDR r2,[pc,#84] ; [0x1006010] = 0x21d - 0x01005fba: 4916 .I LDR r1,[pc,#88] ; [0x1006014] = 0x1007b82 - 0x01005fbc: a016 .. ADR r0,{pc}+0x5c ; 0x1006018 - 0x01005fbe: f7fdfb1f .... BL rt_assert_handler ; 0x1003600 - 0x01005fc2: 4620 F MOV r0,r4 - 0x01005fc4: f7feff52 ..R. BL rt_object_get_type ; 0x1004e6c - 0x01005fc8: 2801 .( CMP r0,#1 - 0x01005fca: d005 .. BEQ 0x1005fd8 ; rt_thread_sleep + 44 - 0x01005fcc: 4a10 .J LDR r2,[pc,#64] ; [0x1006010] = 0x21d - 0x01005fce: 1c52 R. ADDS r2,r2,#1 - 0x01005fd0: 4910 .I LDR r1,[pc,#64] ; [0x1006014] = 0x1007b82 - 0x01005fd2: 4816 .H LDR r0,[pc,#88] ; [0x100602c] = 0x1007f50 - 0x01005fd4: f7fdfb14 .... BL rt_assert_handler ; 0x1003600 - 0x01005fd8: f7fafa72 ..r. BL rt_hw_interrupt_disable ; 0x10004c0 - 0x01005fdc: 4605 .F MOV r5,r0 - 0x01005fde: 4620 F MOV r0,r4 - 0x01005fe0: f000f88a .... BL rt_thread_suspend ; 0x10060f8 - 0x01005fe4: 466a jF MOV r2,sp - 0x01005fe6: 2100 .! MOVS r1,#0 - 0x01005fe8: 4620 F MOV r0,r4 - 0x01005fea: 304c L0 ADDS r0,r0,#0x4c - 0x01005fec: f000fa1c .... BL rt_timer_control ; 0x1006428 - 0x01005ff0: 4620 F MOV r0,r4 - 0x01005ff2: 304c L0 ADDS r0,r0,#0x4c - 0x01005ff4: f000fb1e .... BL rt_timer_start ; 0x1006634 - 0x01005ff8: 4628 (F MOV r0,r5 - 0x01005ffa: f7fafa65 ..e. BL rt_hw_interrupt_enable ; 0x10004c8 - 0x01005ffe: f7fff819 .... BL rt_schedule ; 0x1005034 - 0x01006002: 6b20 k LDR r0,[r4,#0x30] - 0x01006004: 1c80 .. ADDS r0,r0,#2 - 0x01006006: 2800 .( CMP r0,#0 - 0x01006008: d100 .. BNE 0x100600c ; rt_thread_sleep + 96 - 0x0100600a: 6320 c STR r0,[r4,#0x30] - 0x0100600c: 2000 . MOVS r0,#0 - 0x0100600e: bd38 8. POP {r3-r5,pc} - $d - 0x01006010: 0000021d .... DCD 541 - 0x01006014: 01007b82 .{.. DCD 16808834 - 0x01006018: 65726874 thre DCD 1701996660 - 0x0100601c: 21206461 ad ! DCD 555770977 - 0x01006020: 5452203d = RT DCD 1414668349 - 0x01006024: 4c554e5f _NUL DCD 1280659039 - 0x01006028: 0000004c L... DCD 76 - 0x0100602c: 01007f50 P... DCD 16809808 - $t - i.rt_thread_startup - rt_thread_startup - 0x01006030: b510 .. PUSH {r4,lr} - 0x01006032: 4604 .F MOV r4,r0 - 0x01006034: 2c00 ., CMP r4,#0 - 0x01006036: d105 .. BNE 0x1006044 ; rt_thread_startup + 20 - 0x01006038: 22ff ." MOVS r2,#0xff - 0x0100603a: 3242 B2 ADDS r2,r2,#0x42 - 0x0100603c: 4919 .I LDR r1,[pc,#100] ; [0x10060a4] = 0x1007b4e - 0x0100603e: a01a .. ADR r0,{pc}+0x6a ; 0x10060a8 - 0x01006040: f7fdfade .... BL rt_assert_handler ; 0x1003600 - 0x01006044: 2034 4 MOVS r0,#0x34 - 0x01006046: 5d00 .] LDRB r0,[r0,r4] - 0x01006048: 0740 @. LSLS r0,r0,#29 - 0x0100604a: 0f40 @. LSRS r0,r0,#29 - 0x0100604c: 2800 .( CMP r0,#0 - 0x0100604e: d005 .. BEQ 0x100605c ; rt_thread_startup + 44 - 0x01006050: 22ff ." MOVS r2,#0xff - 0x01006052: 3243 C2 ADDS r2,r2,#0x43 - 0x01006054: 4913 .I LDR r1,[pc,#76] ; [0x10060a4] = 0x1007b4e - 0x01006056: a019 .. ADR r0,{pc}+0x66 ; 0x10060bc - 0x01006058: f7fdfad2 .... BL rt_assert_handler ; 0x1003600 - 0x0100605c: 4620 F MOV r0,r4 - 0x0100605e: f7feff05 .... BL rt_object_get_type ; 0x1004e6c - 0x01006062: 2801 .( CMP r0,#1 - 0x01006064: d005 .. BEQ 0x1006072 ; rt_thread_startup + 66 - 0x01006066: 22ff ." MOVS r2,#0xff - 0x01006068: 3244 D2 ADDS r2,r2,#0x44 - 0x0100606a: 490e .I LDR r1,[pc,#56] ; [0x10060a4] = 0x1007b4e - 0x0100606c: 4821 !H LDR r0,[pc,#132] ; [0x10060f4] = 0x1007f50 - 0x0100606e: f7fdfac7 .... BL rt_assert_handler ; 0x1003600 - 0x01006072: 2036 6 MOVS r0,#0x36 - 0x01006074: 5d01 .] LDRB r1,[r0,r4] - 0x01006076: 2035 5 MOVS r0,#0x35 - 0x01006078: 5501 .U STRB r1,[r0,r4] - 0x0100607a: 5d01 .] LDRB r1,[r0,r4] - 0x0100607c: 2001 . MOVS r0,#1 - 0x0100607e: 4088 .@ LSLS r0,r0,r1 - 0x01006080: 63a0 .c STR r0,[r4,#0x38] - 0x01006082: bf00 .. NOP - 0x01006084: bf00 .. NOP - 0x01006086: 2102 .! MOVS r1,#2 - 0x01006088: 2034 4 MOVS r0,#0x34 - 0x0100608a: 5501 .U STRB r1,[r0,r4] - 0x0100608c: 4620 F MOV r0,r4 - 0x0100608e: f7ffff37 ..7. BL rt_thread_resume ; 0x1005f00 - 0x01006092: f7ffff85 .... BL rt_thread_self ; 0x1005fa0 - 0x01006096: 2800 .( CMP r0,#0 - 0x01006098: d001 .. BEQ 0x100609e ; rt_thread_startup + 110 - 0x0100609a: f7feffcb .... BL rt_schedule ; 0x1005034 - 0x0100609e: 2000 . MOVS r0,#0 - 0x010060a0: bd10 .. POP {r4,pc} - $d - 0x010060a2: 0000 .. DCW 0 - 0x010060a4: 01007b4e N{.. DCD 16808782 - 0x010060a8: 65726874 thre DCD 1701996660 - 0x010060ac: 21206461 ad ! DCD 555770977 - 0x010060b0: 5452203d = RT DCD 1414668349 - 0x010060b4: 4c554e5f _NUL DCD 1280659039 - 0x010060b8: 0000004c L... DCD 76 - 0x010060bc: 72687428 (thr DCD 1919448104 - 0x010060c0: 2d646165 ead- DCD 761553253 - 0x010060c4: 6174733e >sta DCD 1635021630 - 0x010060c8: 20262074 t & DCD 539369588 - 0x010060cc: 545f5452 RT_T DCD 1415533650 - 0x010060d0: 41455248 HREA DCD 1095062088 - 0x010060d4: 54535f44 D_ST DCD 1414750020 - 0x010060d8: 4d5f5441 AT_M DCD 1298093121 - 0x010060dc: 294b5341 ASK) DCD 692802369 - 0x010060e0: 203d3d20 == DCD 540884256 - 0x010060e4: 545f5452 RT_T DCD 1415533650 - 0x010060e8: 41455248 HREA DCD 1095062088 - 0x010060ec: 4e495f44 D_IN DCD 1313431364 - 0x010060f0: 00005449 IT.. DCD 21577 - 0x010060f4: 01007f50 P... DCD 16809808 - $t - i.rt_thread_suspend - rt_thread_suspend - 0x010060f8: b570 p. PUSH {r4-r6,lr} - 0x010060fa: 4604 .F MOV r4,r0 - 0x010060fc: 2c00 ., CMP r4,#0 - 0x010060fe: d105 .. BNE 0x100610c ; rt_thread_suspend + 20 - 0x01006100: 22c5 ." MOVS r2,#0xc5 - 0x01006102: 0092 .. LSLS r2,r2,#2 - 0x01006104: 4924 $I LDR r1,[pc,#144] ; [0x1006198] = 0x1007bba - 0x01006106: a025 %. ADR r0,{pc}+0x96 ; 0x100619c - 0x01006108: f7fdfa7a ..z. BL rt_assert_handler ; 0x1003600 - 0x0100610c: 4620 F MOV r0,r4 - 0x0100610e: f7fefead .... BL rt_object_get_type ; 0x1004e6c - 0x01006112: 2801 .( CMP r0,#1 - 0x01006114: d004 .. BEQ 0x1006120 ; rt_thread_suspend + 40 - 0x01006116: 4a26 &J LDR r2,[pc,#152] ; [0x10061b0] = 0x315 - 0x01006118: 491f .I LDR r1,[pc,#124] ; [0x1006198] = 0x1007bba - 0x0100611a: 4826 &H LDR r0,[pc,#152] ; [0x10061b4] = 0x1007f50 - 0x0100611c: f7fdfa70 ..p. BL rt_assert_handler ; 0x1003600 - 0x01006120: bf00 .. NOP - 0x01006122: bf00 .. NOP - 0x01006124: 2034 4 MOVS r0,#0x34 - 0x01006126: 5d00 .] LDRB r0,[r0,r4] - 0x01006128: 0745 E. LSLS r5,r0,#29 - 0x0100612a: 0f6d m. LSRS r5,r5,#29 - 0x0100612c: 2d01 .- CMP r5,#1 - 0x0100612e: d006 .. BEQ 0x100613e ; rt_thread_suspend + 70 - 0x01006130: 2d03 .- CMP r5,#3 - 0x01006132: d004 .. BEQ 0x100613e ; rt_thread_suspend + 70 - 0x01006134: bf00 .. NOP - 0x01006136: bf00 .. NOP - 0x01006138: 2000 . MOVS r0,#0 - 0x0100613a: 43c0 .C MVNS r0,r0 - 0x0100613c: bd70 p. POP {r4-r6,pc} - 0x0100613e: f7faf9bf .... BL rt_hw_interrupt_disable ; 0x10004c0 - 0x01006142: 4606 .F MOV r6,r0 - 0x01006144: 2d03 .- CMP r5,#3 - 0x01006146: d109 .. BNE 0x100615c ; rt_thread_suspend + 100 - 0x01006148: f7ffff2a ..*. BL rt_thread_self ; 0x1005fa0 - 0x0100614c: 42a0 .B CMP r0,r4 - 0x0100614e: d005 .. BEQ 0x100615c ; rt_thread_suspend + 100 - 0x01006150: 4a17 .J LDR r2,[pc,#92] ; [0x10061b0] = 0x315 - 0x01006152: 3211 .2 ADDS r2,r2,#0x11 - 0x01006154: 4910 .I LDR r1,[pc,#64] ; [0x1006198] = 0x1007bba - 0x01006156: a018 .. ADR r0,{pc}+0x62 ; 0x10061b8 - 0x01006158: f7fdfa52 ..R. BL rt_assert_handler ; 0x1003600 - 0x0100615c: 4620 F MOV r0,r4 - 0x0100615e: f7fff86b ..k. BL rt_schedule_remove_thread ; 0x1005238 - 0x01006162: 2034 4 MOVS r0,#0x34 - 0x01006164: 5d00 .] LDRB r0,[r0,r4] - 0x01006166: 08c0 .. LSRS r0,r0,#3 - 0x01006168: 00c0 .. LSLS r0,r0,#3 - 0x0100616a: 2102 .! MOVS r1,#2 - 0x0100616c: 4308 .C ORRS r0,r0,r1 - 0x0100616e: 2134 4! MOVS r1,#0x34 - 0x01006170: 5508 .U STRB r0,[r1,r4] - 0x01006172: 4620 F MOV r0,r4 - 0x01006174: 304c L0 ADDS r0,r0,#0x4c - 0x01006176: f000fb47 ..G. BL rt_timer_stop ; 0x1006808 - 0x0100617a: 4630 0F MOV r0,r6 - 0x0100617c: f7faf9a4 .... BL rt_hw_interrupt_enable ; 0x10004c8 - 0x01006180: bf00 .. NOP - 0x01006182: 4814 .H LDR r0,[pc,#80] ; [0x10061d4] = 0x20128 - 0x01006184: 6800 .h LDR r0,[r0,#0] - 0x01006186: 2800 .( CMP r0,#0 - 0x01006188: d003 .. BEQ 0x1006192 ; rt_thread_suspend + 154 - 0x0100618a: 4620 F MOV r0,r4 - 0x0100618c: 4911 .I LDR r1,[pc,#68] ; [0x10061d4] = 0x20128 - 0x0100618e: 6809 .h LDR r1,[r1,#0] - 0x01006190: 4788 .G BLX r1 - 0x01006192: bf00 .. NOP - 0x01006194: 2000 . MOVS r0,#0 - 0x01006196: e7d1 .. B 0x100613c ; rt_thread_suspend + 68 - $d - 0x01006198: 01007bba .{.. DCD 16808890 - 0x0100619c: 65726874 thre DCD 1701996660 - 0x010061a0: 21206461 ad ! DCD 555770977 - 0x010061a4: 5452203d = RT DCD 1414668349 - 0x010061a8: 4c554e5f _NUL DCD 1280659039 - 0x010061ac: 0000004c L... DCD 76 - 0x010061b0: 00000315 .... DCD 789 - 0x010061b4: 01007f50 P... DCD 16809808 - 0x010061b8: 65726874 thre DCD 1701996660 - 0x010061bc: 3d206461 ad = DCD 1025533025 - 0x010061c0: 7472203d = rt DCD 1953636413 - 0x010061c4: 7268745f _thr DCD 1919448159 - 0x010061c8: 5f646165 ead_ DCD 1600414053 - 0x010061cc: 666c6573 self DCD 1718379891 - 0x010061d0: 00002928 ().. DCD 10536 - 0x010061d4: 00020128 (... DCD 131368 - $t - i.rt_thread_timeout - rt_thread_timeout - 0x010061d8: b570 p. PUSH {r4-r6,lr} - 0x010061da: 4605 .F MOV r5,r0 - 0x010061dc: 462c ,F MOV r4,r5 - 0x010061de: 2c00 ., CMP r4,#0 - 0x010061e0: d104 .. BNE 0x10061ec ; rt_thread_timeout + 20 - 0x010061e2: 4a17 .J LDR r2,[pc,#92] ; [0x1006240] = 0x372 - 0x010061e4: 4917 .I LDR r1,[pc,#92] ; [0x1006244] = 0x1007bdd - 0x010061e6: a018 .. ADR r0,{pc}+0x62 ; 0x1006248 - 0x010061e8: f7fdfa0a .... BL rt_assert_handler ; 0x1003600 - 0x010061ec: 2034 4 MOVS r0,#0x34 - 0x010061ee: 5d00 .] LDRB r0,[r0,r4] - 0x010061f0: 0740 @. LSLS r0,r0,#29 - 0x010061f2: 0f40 @. LSRS r0,r0,#29 - 0x010061f4: 2802 .( CMP r0,#2 - 0x010061f6: d005 .. BEQ 0x1006204 ; rt_thread_timeout + 44 - 0x010061f8: 4a11 .J LDR r2,[pc,#68] ; [0x1006240] = 0x372 - 0x010061fa: 1c52 R. ADDS r2,r2,#1 - 0x010061fc: 4911 .I LDR r1,[pc,#68] ; [0x1006244] = 0x1007bdd - 0x010061fe: a017 .. ADR r0,{pc}+0x5e ; 0x100625c - 0x01006200: f7fdf9fe .... BL rt_assert_handler ; 0x1003600 - 0x01006204: 4620 F MOV r0,r4 - 0x01006206: f7fefe31 ..1. BL rt_object_get_type ; 0x1004e6c - 0x0100620a: 2801 .( CMP r0,#1 - 0x0100620c: d005 .. BEQ 0x100621a ; rt_thread_timeout + 66 - 0x0100620e: 22dd ." MOVS r2,#0xdd - 0x01006210: 0092 .. LSLS r2,r2,#2 - 0x01006212: 490c .I LDR r1,[pc,#48] ; [0x1006244] = 0x1007bdd - 0x01006214: 4820 H LDR r0,[pc,#128] ; [0x1006298] = 0x1007f50 - 0x01006216: f7fdf9f3 .... BL rt_assert_handler ; 0x1003600 - 0x0100621a: f7faf951 ..Q. BL rt_hw_interrupt_disable ; 0x10004c0 - 0x0100621e: 4606 .F MOV r6,r0 - 0x01006220: 2001 . MOVS r0,#1 - 0x01006222: 43c0 .C MVNS r0,r0 - 0x01006224: 6320 c STR r0,[r4,#0x30] - 0x01006226: 4620 F MOV r0,r4 - 0x01006228: 3014 .0 ADDS r0,r0,#0x14 - 0x0100622a: f7fef9d0 .... BL rt_list_remove ; 0x10045ce - 0x0100622e: 4620 F MOV r0,r4 - 0x01006230: f7feffb2 .... BL rt_schedule_insert_thread ; 0x1005198 - 0x01006234: 4630 0F MOV r0,r6 - 0x01006236: f7faf947 ..G. BL rt_hw_interrupt_enable ; 0x10004c8 - 0x0100623a: f7fefefb .... BL rt_schedule ; 0x1005034 - 0x0100623e: bd70 p. POP {r4-r6,pc} - $d - 0x01006240: 00000372 r... DCD 882 - 0x01006244: 01007bdd .{.. DCD 16808925 - 0x01006248: 65726874 thre DCD 1701996660 - 0x0100624c: 21206461 ad ! DCD 555770977 - 0x01006250: 5452203d = RT DCD 1414668349 - 0x01006254: 4c554e5f _NUL DCD 1280659039 - 0x01006258: 0000004c L... DCD 76 - 0x0100625c: 72687428 (thr DCD 1919448104 - 0x01006260: 2d646165 ead- DCD 761553253 - 0x01006264: 6174733e >sta DCD 1635021630 - 0x01006268: 20262074 t & DCD 539369588 - 0x0100626c: 545f5452 RT_T DCD 1415533650 - 0x01006270: 41455248 HREA DCD 1095062088 - 0x01006274: 54535f44 D_ST DCD 1414750020 - 0x01006278: 4d5f5441 AT_M DCD 1298093121 - 0x0100627c: 294b5341 ASK) DCD 692802369 - 0x01006280: 203d3d20 == DCD 540884256 - 0x01006284: 545f5452 RT_T DCD 1415533650 - 0x01006288: 41455248 HREA DCD 1095062088 - 0x0100628c: 55535f44 D_SU DCD 1431527236 - 0x01006290: 4e455053 SPEN DCD 1313165395 - 0x01006294: 00000044 D... DCD 68 - 0x01006298: 01007f50 P... DCD 16809808 - $t - i.rt_tick_from_millisecond - rt_tick_from_millisecond - 0x0100629c: b570 p. PUSH {r4-r6,lr} - 0x0100629e: 4605 .F MOV r5,r0 - 0x010062a0: 2d00 .- CMP r5,#0 - 0x010062a2: da02 .. BGE 0x10062aa ; rt_tick_from_millisecond + 14 - 0x010062a4: 2400 .$ MOVS r4,#0 - 0x010062a6: 43e4 .C MVNS r4,r4 - 0x010062a8: e015 .. B 0x10062d6 ; rt_tick_from_millisecond + 58 - 0x010062aa: 217d }! MOVS r1,#0x7d - 0x010062ac: 00c9 .. LSLS r1,r1,#3 - 0x010062ae: 4628 (F MOV r0,r5 - 0x010062b0: f7fafae6 .... BL __aeabi_idiv ; 0x1000880 - 0x010062b4: 2164 d! MOVS r1,#0x64 - 0x010062b6: 4348 HC MULS r0,r1,r0 - 0x010062b8: 4604 .F MOV r4,r0 - 0x010062ba: 217d }! MOVS r1,#0x7d - 0x010062bc: 00c9 .. LSLS r1,r1,#3 - 0x010062be: 4628 (F MOV r0,r5 - 0x010062c0: f7fafade .... BL __aeabi_idiv ; 0x1000880 - 0x010062c4: 2064 d MOVS r0,#0x64 - 0x010062c6: 4341 AC MULS r1,r0,r1 - 0x010062c8: 4804 .H LDR r0,[pc,#16] ; [0x10062dc] = 0x3e7 - 0x010062ca: 180e .. ADDS r6,r1,r0 - 0x010062cc: 1c41 A. ADDS r1,r0,#1 - 0x010062ce: 4630 0F MOV r0,r6 - 0x010062d0: f7fafad6 .... BL __aeabi_idiv ; 0x1000880 - 0x010062d4: 1904 .. ADDS r4,r0,r4 - 0x010062d6: 4620 F MOV r0,r4 - 0x010062d8: bd70 p. POP {r4-r6,pc} - $d - 0x010062da: 0000 .. DCW 0 - 0x010062dc: 000003e7 .... DCD 999 - $t - i.rt_tick_get - rt_tick_get - 0x010062e0: 4801 .H LDR r0,[pc,#4] ; [0x10062e8] = 0x20044 - 0x010062e2: 6800 .h LDR r0,[r0,#0] - 0x010062e4: 4770 pG BX lr - $d - 0x010062e6: 0000 .. DCW 0 - 0x010062e8: 00020044 D... DCD 131140 - $t - i.rt_tick_increase - rt_tick_increase - 0x010062ec: b570 p. PUSH {r4-r6,lr} - 0x010062ee: f7faf8e7 .... BL rt_hw_interrupt_disable ; 0x10004c0 - 0x010062f2: 4605 .F MOV r5,r0 - 0x010062f4: 4810 .H LDR r0,[pc,#64] ; [0x1006338] = 0x20044 - 0x010062f6: 6800 .h LDR r0,[r0,#0] - 0x010062f8: 1c40 @. ADDS r0,r0,#1 - 0x010062fa: 490f .I LDR r1,[pc,#60] ; [0x1006338] = 0x20044 - 0x010062fc: 6008 .` STR r0,[r1,#0] - 0x010062fe: f7fffe4f ..O. BL rt_thread_self ; 0x1005fa0 - 0x01006302: 4604 .F MOV r4,r0 - 0x01006304: 6ca0 .l LDR r0,[r4,#0x48] - 0x01006306: 1e40 @. SUBS r0,r0,#1 - 0x01006308: 64a0 .d STR r0,[r4,#0x48] - 0x0100630a: 6ca0 .l LDR r0,[r4,#0x48] - 0x0100630c: 2800 .( CMP r0,#0 - 0x0100630e: d10d .. BNE 0x100632c ; rt_tick_increase + 64 - 0x01006310: 6c60 `l LDR r0,[r4,#0x44] - 0x01006312: 64a0 .d STR r0,[r4,#0x48] - 0x01006314: 2034 4 MOVS r0,#0x34 - 0x01006316: 5d00 .] LDRB r0,[r0,r4] - 0x01006318: 2108 .! MOVS r1,#8 - 0x0100631a: 4308 .C ORRS r0,r0,r1 - 0x0100631c: 2134 4! MOVS r1,#0x34 - 0x0100631e: 5508 .U STRB r0,[r1,r4] - 0x01006320: 4628 (F MOV r0,r5 - 0x01006322: f7faf8d1 .... BL rt_hw_interrupt_enable ; 0x10004c8 - 0x01006326: f7fefe85 .... BL rt_schedule ; 0x1005034 - 0x0100632a: e002 .. B 0x1006332 ; rt_tick_increase + 70 - 0x0100632c: 4628 (F MOV r0,r5 - 0x0100632e: f7faf8cb .... BL rt_hw_interrupt_enable ; 0x10004c8 - 0x01006332: f000f803 .... BL rt_timer_check ; 0x100633c - 0x01006336: bd70 p. POP {r4-r6,pc} - $d - 0x01006338: 00020044 D... DCD 131140 - $t - i.rt_timer_check - rt_timer_check - 0x0100633c: b57c |. PUSH {r2-r6,lr} - 0x0100633e: 4668 hF MOV r0,sp - 0x01006340: f7fef8f1 .... BL rt_list_init ; 0x1004526 - 0x01006344: bf00 .. NOP - 0x01006346: bf00 .. NOP - 0x01006348: f7ffffca .... BL rt_tick_get ; 0x10062e0 - 0x0100634c: 4605 .F MOV r5,r0 - 0x0100634e: f7faf8b7 .... BL rt_hw_interrupt_disable ; 0x10004c0 - 0x01006352: 4606 .F MOV r6,r0 - 0x01006354: e053 S. B 0x10063fe ; rt_timer_check + 194 - 0x01006356: 4830 0H LDR r0,[pc,#192] ; [0x1006418] = 0x20054 - 0x01006358: 6800 .h LDR r0,[r0,#0] - 0x0100635a: 4604 .F MOV r4,r0 - 0x0100635c: 3c14 .< SUBS r4,r4,#0x14 - 0x0100635e: 6aa0 .j LDR r0,[r4,#0x28] - 0x01006360: 1a28 (. SUBS r0,r5,r0 - 0x01006362: 492e .I LDR r1,[pc,#184] ; [0x100641c] = 0x7fffffff - 0x01006364: 4288 .B CMP r0,r1 - 0x01006366: d248 H. BCS 0x10063fa ; rt_timer_check + 190 - 0x01006368: bf00 .. NOP - 0x0100636a: 482d -H LDR r0,[pc,#180] ; [0x1006420] = 0x2005c - 0x0100636c: 6800 .h LDR r0,[r0,#0] - 0x0100636e: 2800 .( CMP r0,#0 - 0x01006370: d003 .. BEQ 0x100637a ; rt_timer_check + 62 - 0x01006372: 4620 F MOV r0,r4 - 0x01006374: 492a *I LDR r1,[pc,#168] ; [0x1006420] = 0x2005c - 0x01006376: 6809 .h LDR r1,[r1,#0] - 0x01006378: 4788 .G BLX r1 - 0x0100637a: bf00 .. NOP - 0x0100637c: 4620 F MOV r0,r4 - 0x0100637e: f7fbf9f1 .... BL _timer_remove ; 0x1001764 - 0x01006382: 7a60 `z LDRB r0,[r4,#9] - 0x01006384: 2102 .! MOVS r1,#2 - 0x01006386: 4008 .@ ANDS r0,r0,r1 - 0x01006388: 2800 .( CMP r0,#0 - 0x0100638a: d103 .. BNE 0x1006394 ; rt_timer_check + 88 - 0x0100638c: 7a60 `z LDRB r0,[r4,#9] - 0x0100638e: 0840 @. LSRS r0,r0,#1 - 0x01006390: 0040 @. LSLS r0,r0,#1 - 0x01006392: 7260 `r STRB r0,[r4,#9] - 0x01006394: 4621 !F MOV r1,r4 - 0x01006396: 3114 .1 ADDS r1,r1,#0x14 - 0x01006398: 4668 hF MOV r0,sp - 0x0100639a: f7fef8c7 .... BL rt_list_insert_after ; 0x100452c - 0x0100639e: 69e1 .i LDR r1,[r4,#0x1c] - 0x010063a0: 6a20 j LDR r0,[r4,#0x20] - 0x010063a2: 4788 .G BLX r1 - 0x010063a4: f7ffff9c .... BL rt_tick_get ; 0x10062e0 - 0x010063a8: 4605 .F MOV r5,r0 - 0x010063aa: bf00 .. NOP - 0x010063ac: 481d .H LDR r0,[pc,#116] ; [0x1006424] = 0x20060 - 0x010063ae: 6800 .h LDR r0,[r0,#0] - 0x010063b0: 2800 .( CMP r0,#0 - 0x010063b2: d003 .. BEQ 0x10063bc ; rt_timer_check + 128 - 0x010063b4: 4620 F MOV r0,r4 - 0x010063b6: 491b .I LDR r1,[pc,#108] ; [0x1006424] = 0x20060 - 0x010063b8: 6809 .h LDR r1,[r1,#0] - 0x010063ba: 4788 .G BLX r1 - 0x010063bc: bf00 .. NOP - 0x010063be: bf00 .. NOP - 0x010063c0: bf00 .. NOP - 0x010063c2: 4668 hF MOV r0,sp - 0x010063c4: f7fef8df .... BL rt_list_isempty ; 0x1004586 - 0x010063c8: 2800 .( CMP r0,#0 - 0x010063ca: d000 .. BEQ 0x10063ce ; rt_timer_check + 146 - 0x010063cc: e017 .. B 0x10063fe ; rt_timer_check + 194 - 0x010063ce: 4620 F MOV r0,r4 - 0x010063d0: 3014 .0 ADDS r0,r0,#0x14 - 0x010063d2: f7fef8ea .... BL rt_list_remove ; 0x10045aa - 0x010063d6: 7a60 `z LDRB r0,[r4,#9] - 0x010063d8: 2102 .! MOVS r1,#2 - 0x010063da: 4008 .@ ANDS r0,r0,r1 - 0x010063dc: 2800 .( CMP r0,#0 - 0x010063de: d00d .. BEQ 0x10063fc ; rt_timer_check + 192 - 0x010063e0: 7a60 `z LDRB r0,[r4,#9] - 0x010063e2: 07c0 .. LSLS r0,r0,#31 - 0x010063e4: 0fc0 .. LSRS r0,r0,#31 - 0x010063e6: 2800 .( CMP r0,#0 - 0x010063e8: d008 .. BEQ 0x10063fc ; rt_timer_check + 192 - 0x010063ea: 7a60 `z LDRB r0,[r4,#9] - 0x010063ec: 0840 @. LSRS r0,r0,#1 - 0x010063ee: 0040 @. LSLS r0,r0,#1 - 0x010063f0: 7260 `r STRB r0,[r4,#9] - 0x010063f2: 4620 F MOV r0,r4 - 0x010063f4: f000f91e .... BL rt_timer_start ; 0x1006634 - 0x010063f8: e000 .. B 0x10063fc ; rt_timer_check + 192 - 0x010063fa: e005 .. B 0x1006408 ; rt_timer_check + 204 - 0x010063fc: bf00 .. NOP - 0x010063fe: 4806 .H LDR r0,[pc,#24] ; [0x1006418] = 0x20054 - 0x01006400: f7fef8c1 .... BL rt_list_isempty ; 0x1004586 - 0x01006404: 2800 .( CMP r0,#0 - 0x01006406: d0a6 .. BEQ 0x1006356 ; rt_timer_check + 26 - 0x01006408: bf00 .. NOP - 0x0100640a: 4630 0F MOV r0,r6 - 0x0100640c: f7faf85c ..\. BL rt_hw_interrupt_enable ; 0x10004c8 - 0x01006410: bf00 .. NOP - 0x01006412: bf00 .. NOP - 0x01006414: bd7c |. POP {r2-r6,pc} - $d - 0x01006416: 0000 .. DCW 0 - 0x01006418: 00020054 T... DCD 131156 - 0x0100641c: 7fffffff .... DCD 2147483647 - 0x01006420: 0002005c \... DCD 131164 - 0x01006424: 00020060 `... DCD 131168 - $t - i.rt_timer_control - rt_timer_control - 0x01006428: b5f8 .. PUSH {r3-r7,lr} - 0x0100642a: 4604 .F MOV r4,r0 - 0x0100642c: 460e .F MOV r6,r1 - 0x0100642e: 4615 .F MOV r5,r2 - 0x01006430: 2c00 ., CMP r4,#0 - 0x01006432: d104 .. BNE 0x100643e ; rt_timer_control + 22 - 0x01006434: 4a1d .J LDR r2,[pc,#116] ; [0x10064ac] = 0x219 - 0x01006436: 491e .I LDR r1,[pc,#120] ; [0x10064b0] = 0x1007a3b - 0x01006438: a01e .. ADR r0,{pc}+0x7c ; 0x10064b4 - 0x0100643a: f7fdf8e1 .... BL rt_assert_handler ; 0x1003600 - 0x0100643e: 4620 F MOV r0,r4 - 0x01006440: f7fefd14 .... BL rt_object_get_type ; 0x1004e6c - 0x01006444: 280a .( CMP r0,#0xa - 0x01006446: d005 .. BEQ 0x1006454 ; rt_timer_control + 44 - 0x01006448: 4a18 .J LDR r2,[pc,#96] ; [0x10064ac] = 0x219 - 0x0100644a: 1c52 R. ADDS r2,r2,#1 - 0x0100644c: 4918 .I LDR r1,[pc,#96] ; [0x10064b0] = 0x1007a3b - 0x0100644e: a01e .. ADR r0,{pc}+0x7a ; 0x10064c8 - 0x01006450: f7fdf8d6 .... BL rt_assert_handler ; 0x1003600 - 0x01006454: f7faf834 ..4. BL rt_hw_interrupt_disable ; 0x10004c0 - 0x01006458: 4607 .F MOV r7,r0 - 0x0100645a: 0033 3. MOVS r3,r6 - 0x0100645c: f7fafdba .... BL __ARM_common_switch8 ; 0x1000fd4 - $d - 0x01006460: 0a040705 .... DCD 168036101 - 0x01006464: 001f140f .... DCD 2036751 - $t - 0x01006468: 6a60 `j LDR r0,[r4,#0x24] - 0x0100646a: 6028 (` STR r0,[r5,#0] - 0x0100646c: e018 .. B 0x10064a0 ; rt_timer_control + 120 - 0x0100646e: 6828 (h LDR r0,[r5,#0] - 0x01006470: 6260 `b STR r0,[r4,#0x24] - 0x01006472: e015 .. B 0x10064a0 ; rt_timer_control + 120 - 0x01006474: 7a60 `z LDRB r0,[r4,#9] - 0x01006476: 2102 .! MOVS r1,#2 - 0x01006478: 4388 .C BICS r0,r0,r1 - 0x0100647a: 7260 `r STRB r0,[r4,#9] - 0x0100647c: e010 .. B 0x10064a0 ; rt_timer_control + 120 - 0x0100647e: 7a60 `z LDRB r0,[r4,#9] - 0x01006480: 2102 .! MOVS r1,#2 - 0x01006482: 4308 .C ORRS r0,r0,r1 - 0x01006484: 7260 `r STRB r0,[r4,#9] - 0x01006486: e00b .. B 0x10064a0 ; rt_timer_control + 120 - 0x01006488: 7a60 `z LDRB r0,[r4,#9] - 0x0100648a: 07c0 .. LSLS r0,r0,#31 - 0x0100648c: 0fc0 .. LSRS r0,r0,#31 - 0x0100648e: 2800 .( CMP r0,#0 - 0x01006490: d002 .. BEQ 0x1006498 ; rt_timer_control + 112 - 0x01006492: 2001 . MOVS r0,#1 - 0x01006494: 6028 (` STR r0,[r5,#0] - 0x01006496: e001 .. B 0x100649c ; rt_timer_control + 116 - 0x01006498: 2000 . MOVS r0,#0 - 0x0100649a: 6028 (` STR r0,[r5,#0] - 0x0100649c: e000 .. B 0x10064a0 ; rt_timer_control + 120 - 0x0100649e: bf00 .. NOP - 0x010064a0: bf00 .. NOP - 0x010064a2: 4638 8F MOV r0,r7 - 0x010064a4: f7faf810 .... BL rt_hw_interrupt_enable ; 0x10004c8 - 0x010064a8: 2000 . MOVS r0,#0 - 0x010064aa: bdf8 .. POP {r3-r7,pc} - $d - 0x010064ac: 00000219 .... DCD 537 - 0x010064b0: 01007a3b ;z.. DCD 16808507 - 0x010064b4: 656d6974 time DCD 1701669236 - 0x010064b8: 3d212072 r != DCD 1025581170 - 0x010064bc: 5f545220 RT_ DCD 1599361568 - 0x010064c0: 4c4c554e NULL DCD 1280070990 - 0x010064c4: 00000000 .... DCD 0 - 0x010064c8: 6f5f7472 rt_o DCD 1868526706 - 0x010064cc: 63656a62 bjec DCD 1667590754 - 0x010064d0: 65675f74 t_ge DCD 1701273460 - 0x010064d4: 79745f74 t_ty DCD 2037669748 - 0x010064d8: 26286570 pe(& DCD 640181616 - 0x010064dc: 656d6974 time DCD 1701669236 - 0x010064e0: 703e2d72 r->p DCD 1883123058 - 0x010064e4: 6e657261 aren DCD 1852142177 - 0x010064e8: 3d202974 t) = DCD 1025517940 - 0x010064ec: 5452203d = RT DCD 1414668349 - 0x010064f0: 6a624f5f _Obj DCD 1784827743 - 0x010064f4: 5f746365 ect_ DCD 1601463141 - 0x010064f8: 73616c43 Clas DCD 1935764547 - 0x010064fc: 69545f73 s_Ti DCD 1767137139 - 0x01006500: 0072656d mer. DCD 7497069 - $t - i.rt_timer_detach - rt_timer_detach - 0x01006504: b570 p. PUSH {r4-r6,lr} - 0x01006506: 4604 .F MOV r4,r0 - 0x01006508: 2c00 ., CMP r4,#0 - 0x0100650a: d105 .. BNE 0x1006518 ; rt_timer_detach + 20 - 0x0100650c: 22ff ." MOVS r2,#0xff - 0x0100650e: 320d .2 ADDS r2,r2,#0xd - 0x01006510: 4915 .I LDR r1,[pc,#84] ; [0x1006568] = 0x10079fe - 0x01006512: a016 .. ADR r0,{pc}+0x5a ; 0x100656c - 0x01006514: f7fdf874 ..t. BL rt_assert_handler ; 0x1003600 - 0x01006518: 4620 F MOV r0,r4 - 0x0100651a: f7fefca7 .... BL rt_object_get_type ; 0x1004e6c - 0x0100651e: 280a .( CMP r0,#0xa - 0x01006520: d005 .. BEQ 0x100652e ; rt_timer_detach + 42 - 0x01006522: 22ff ." MOVS r2,#0xff - 0x01006524: 320e .2 ADDS r2,r2,#0xe - 0x01006526: 4910 .I LDR r1,[pc,#64] ; [0x1006568] = 0x10079fe - 0x01006528: a015 .. ADR r0,{pc}+0x58 ; 0x1006580 - 0x0100652a: f7fdf869 ..i. BL rt_assert_handler ; 0x1003600 - 0x0100652e: 4620 F MOV r0,r4 - 0x01006530: f7fefd18 .... BL rt_object_is_systemobject ; 0x1004f64 - 0x01006534: 2800 .( CMP r0,#0 - 0x01006536: d105 .. BNE 0x1006544 ; rt_timer_detach + 64 - 0x01006538: 22ff ." MOVS r2,#0xff - 0x0100653a: 320f .2 ADDS r2,r2,#0xf - 0x0100653c: 490a .I LDR r1,[pc,#40] ; [0x1006568] = 0x10079fe - 0x0100653e: a01f .. ADR r0,{pc}+0x7e ; 0x10065bc - 0x01006540: f7fdf85e ..^. BL rt_assert_handler ; 0x1003600 - 0x01006544: f7f9ffbc .... BL rt_hw_interrupt_disable ; 0x10004c0 - 0x01006548: 4605 .F MOV r5,r0 - 0x0100654a: 4620 F MOV r0,r4 - 0x0100654c: f7fbf90a .... BL _timer_remove ; 0x1001764 - 0x01006550: 7a60 `z LDRB r0,[r4,#9] - 0x01006552: 0840 @. LSRS r0,r0,#1 - 0x01006554: 0040 @. LSLS r0,r0,#1 - 0x01006556: 7260 `r STRB r0,[r4,#9] - 0x01006558: 4628 (F MOV r0,r5 - 0x0100655a: f7f9ffb5 .... BL rt_hw_interrupt_enable ; 0x10004c8 - 0x0100655e: 4620 F MOV r0,r4 - 0x01006560: f7fefba0 .... BL rt_object_detach ; 0x1004ca4 - 0x01006564: 2000 . MOVS r0,#0 - 0x01006566: bd70 p. POP {r4-r6,pc} - $d - 0x01006568: 010079fe .y.. DCD 16808446 - 0x0100656c: 656d6974 time DCD 1701669236 - 0x01006570: 3d212072 r != DCD 1025581170 - 0x01006574: 5f545220 RT_ DCD 1599361568 - 0x01006578: 4c4c554e NULL DCD 1280070990 - 0x0100657c: 00000000 .... DCD 0 - 0x01006580: 6f5f7472 rt_o DCD 1868526706 - 0x01006584: 63656a62 bjec DCD 1667590754 - 0x01006588: 65675f74 t_ge DCD 1701273460 - 0x0100658c: 79745f74 t_ty DCD 2037669748 - 0x01006590: 26286570 pe(& DCD 640181616 - 0x01006594: 656d6974 time DCD 1701669236 - 0x01006598: 703e2d72 r->p DCD 1883123058 - 0x0100659c: 6e657261 aren DCD 1852142177 - 0x010065a0: 3d202974 t) = DCD 1025517940 - 0x010065a4: 5452203d = RT DCD 1414668349 - 0x010065a8: 6a624f5f _Obj DCD 1784827743 - 0x010065ac: 5f746365 ect_ DCD 1601463141 - 0x010065b0: 73616c43 Clas DCD 1935764547 - 0x010065b4: 69545f73 s_Ti DCD 1767137139 - 0x010065b8: 0072656d mer. DCD 7497069 - 0x010065bc: 6f5f7472 rt_o DCD 1868526706 - 0x010065c0: 63656a62 bjec DCD 1667590754 - 0x010065c4: 73695f74 t_is DCD 1936285556 - 0x010065c8: 7379735f _sys DCD 1937339231 - 0x010065cc: 6f6d6574 temo DCD 1869440372 - 0x010065d0: 63656a62 bjec DCD 1667590754 - 0x010065d4: 74262874 t(&t DCD 1948657780 - 0x010065d8: 72656d69 imer DCD 1919249769 - 0x010065dc: 61703e2d ->pa DCD 1634745901 - 0x010065e0: 746e6572 rent DCD 1953391986 - 0x010065e4: 00000029 )... DCD 41 - $t - i.rt_timer_init - rt_timer_init - 0x010065e8: b5f8 .. PUSH {r3-r7,lr} - 0x010065ea: 4604 .F MOV r4,r0 - 0x010065ec: 460d .F MOV r5,r1 - 0x010065ee: 4616 .F MOV r6,r2 - 0x010065f0: 461f .F MOV r7,r3 - 0x010065f2: 2c00 ., CMP r4,#0 - 0x010065f4: d104 .. BNE 0x1006600 ; rt_timer_init + 24 - 0x010065f6: 22f7 ." MOVS r2,#0xf7 - 0x010065f8: 4908 .I LDR r1,[pc,#32] ; [0x100661c] = 0x10079f0 - 0x010065fa: a009 .. ADR r0,{pc}+0x26 ; 0x1006620 - 0x010065fc: f7fdf800 .... BL rt_assert_handler ; 0x1003600 - 0x01006600: 462a *F MOV r2,r5 - 0x01006602: 210a .! MOVS r1,#0xa - 0x01006604: 4620 F MOV r0,r4 - 0x01006606: f7fefc4b ..K. BL rt_object_init ; 0x1004ea0 - 0x0100660a: 9807 .. LDR r0,[sp,#0x1c] - 0x0100660c: 9000 .. STR r0,[sp,#0] - 0x0100660e: 463a :F MOV r2,r7 - 0x01006610: 4631 1F MOV r1,r6 - 0x01006612: 4620 F MOV r0,r4 - 0x01006614: 9b06 .. LDR r3,[sp,#0x18] - 0x01006616: f7fbf887 .... BL _timer_init ; 0x1001728 - 0x0100661a: bdf8 .. POP {r3-r7,pc} - $d - 0x0100661c: 010079f0 .y.. DCD 16808432 - 0x01006620: 656d6974 time DCD 1701669236 - 0x01006624: 3d212072 r != DCD 1025581170 - 0x01006628: 5f545220 RT_ DCD 1599361568 - 0x0100662c: 4c4c554e NULL DCD 1280070990 - 0x01006630: 00000000 .... DCD 0 - $t - i.rt_timer_start - rt_timer_start - 0x01006634: b5fe .. PUSH {r1-r7,lr} - 0x01006636: 4605 .F MOV r5,r0 - 0x01006638: 2d00 .- CMP r5,#0 - 0x0100663a: d105 .. BNE 0x1006648 ; rt_timer_start + 20 - 0x0100663c: 22ff ." MOVS r2,#0xff - 0x0100663e: 3279 y2 ADDS r2,r2,#0x79 - 0x01006640: 494f OI LDR r1,[pc,#316] ; [0x1006780] = 0x1007a1e - 0x01006642: a050 P. ADR r0,{pc}+0x142 ; 0x1006784 - 0x01006644: f7fcffdc .... BL rt_assert_handler ; 0x1003600 - 0x01006648: 4628 (F MOV r0,r5 - 0x0100664a: f7fefc0f .... BL rt_object_get_type ; 0x1004e6c - 0x0100664e: 280a .( CMP r0,#0xa - 0x01006650: d005 .. BEQ 0x100665e ; rt_timer_start + 42 - 0x01006652: 22ff ." MOVS r2,#0xff - 0x01006654: 327a z2 ADDS r2,r2,#0x7a - 0x01006656: 494a JI LDR r1,[pc,#296] ; [0x1006780] = 0x1007a1e - 0x01006658: a04f O. ADR r0,{pc}+0x140 ; 0x1006798 - 0x0100665a: f7fcffd1 .... BL rt_assert_handler ; 0x1003600 - 0x0100665e: 2000 . MOVS r0,#0 - 0x01006660: 9001 .. STR r0,[sp,#4] - 0x01006662: f7f9ff2d ..-. BL rt_hw_interrupt_disable ; 0x10004c0 - 0x01006666: 9002 .. STR r0,[sp,#8] - 0x01006668: 4628 (F MOV r0,r5 - 0x0100666a: f7fbf87b ..{. BL _timer_remove ; 0x1001764 - 0x0100666e: 7a68 hz LDRB r0,[r5,#9] - 0x01006670: 0840 @. LSRS r0,r0,#1 - 0x01006672: 0040 @. LSLS r0,r0,#1 - 0x01006674: 7268 hr STRB r0,[r5,#9] - 0x01006676: bf00 .. NOP - 0x01006678: 4856 VH LDR r0,[pc,#344] ; [0x10067d4] = 0x20114 - 0x0100667a: 6800 .h LDR r0,[r0,#0] - 0x0100667c: 2800 .( CMP r0,#0 - 0x0100667e: d003 .. BEQ 0x1006688 ; rt_timer_start + 84 - 0x01006680: 4628 (F MOV r0,r5 - 0x01006682: 4954 TI LDR r1,[pc,#336] ; [0x10067d4] = 0x20114 - 0x01006684: 6809 .h LDR r1,[r1,#0] - 0x01006686: 4788 .G BLX r1 - 0x01006688: bf00 .. NOP - 0x0100668a: 4953 SI LDR r1,[pc,#332] ; [0x10067d8] = 0x7fffffff - 0x0100668c: 6a68 hj LDR r0,[r5,#0x24] - 0x0100668e: 4288 .B CMP r0,r1 - 0x01006690: d305 .. BCC 0x100669e ; rt_timer_start + 106 - 0x01006692: 22ff ." MOVS r2,#0xff - 0x01006694: 328b .2 ADDS r2,r2,#0x8b - 0x01006696: 493a :I LDR r1,[pc,#232] ; [0x1006780] = 0x1007a1e - 0x01006698: a050 P. ADR r0,{pc}+0x144 ; 0x10067dc - 0x0100669a: f7fcffb1 .... BL rt_assert_handler ; 0x1003600 - 0x0100669e: f7fffe1f .... BL rt_tick_get ; 0x10062e0 - 0x010066a2: 6a69 ij LDR r1,[r5,#0x24] - 0x010066a4: 1840 @. ADDS r0,r0,r1 - 0x010066a6: 62a8 .b STR r0,[r5,#0x28] - 0x010066a8: 4e55 UN LDR r6,[pc,#340] ; [0x1006800] = 0x20054 - 0x010066aa: 9600 .. STR r6,[sp,#0] - 0x010066ac: 2400 .$ MOVS r4,#0 - 0x010066ae: e030 0. B 0x1006712 ; rt_timer_start + 222 - 0x010066b0: e01b .. B 0x10066ea ; rt_timer_start + 182 - 0x010066b2: 00a2 .. LSLS r2,r4,#2 - 0x010066b4: 466b kF MOV r3,sp - 0x010066b6: 589a .X LDR r2,[r3,r2] - 0x010066b8: 6811 .h LDR r1,[r2,#0] - 0x010066ba: 2214 ." MOVS r2,#0x14 - 0x010066bc: 00e3 .. LSLS r3,r4,#3 - 0x010066be: 18d2 .. ADDS r2,r2,r3 - 0x010066c0: 1a88 .. SUBS r0,r1,r2 - 0x010066c2: 6a82 .j LDR r2,[r0,#0x28] - 0x010066c4: 6aab .j LDR r3,[r5,#0x28] - 0x010066c6: 1ad2 .. SUBS r2,r2,r3 - 0x010066c8: d100 .. BNE 0x10066cc ; rt_timer_start + 152 - 0x010066ca: e007 .. B 0x10066dc ; rt_timer_start + 168 - 0x010066cc: 6a82 .j LDR r2,[r0,#0x28] - 0x010066ce: 6aab .j LDR r3,[r5,#0x28] - 0x010066d0: 1ad2 .. SUBS r2,r2,r3 - 0x010066d2: 4b41 AK LDR r3,[pc,#260] ; [0x10067d8] = 0x7fffffff - 0x010066d4: 429a .B CMP r2,r3 - 0x010066d6: d200 .. BCS 0x10066da ; rt_timer_start + 166 - 0x010066d8: e00f .. B 0x10066fa ; rt_timer_start + 198 - 0x010066da: bf00 .. NOP - 0x010066dc: 00a0 .. LSLS r0,r4,#2 - 0x010066de: 4669 iF MOV r1,sp - 0x010066e0: 5808 .X LDR r0,[r1,r0] - 0x010066e2: 6800 .h LDR r0,[r0,#0] - 0x010066e4: 00a1 .. LSLS r1,r4,#2 - 0x010066e6: 466a jF MOV r2,sp - 0x010066e8: 5050 PP STR r0,[r2,r1] - 0x010066ea: 00a0 .. LSLS r0,r4,#2 - 0x010066ec: 4669 iF MOV r1,sp - 0x010066ee: 5808 .X LDR r0,[r1,r0] - 0x010066f0: 00e1 .. LSLS r1,r4,#3 - 0x010066f2: 1989 .. ADDS r1,r1,r6 - 0x010066f4: 6849 Ih LDR r1,[r1,#4] - 0x010066f6: 4288 .B CMP r0,r1 - 0x010066f8: d1db .. BNE 0x10066b2 ; rt_timer_start + 126 - 0x010066fa: bf00 .. NOP - 0x010066fc: 2c00 ., CMP r4,#0 - 0x010066fe: d007 .. BEQ 0x1006710 ; rt_timer_start + 220 - 0x01006700: 00a0 .. LSLS r0,r4,#2 - 0x01006702: 4669 iF MOV r1,sp - 0x01006704: 5808 .X LDR r0,[r1,r0] - 0x01006706: 3008 .0 ADDS r0,r0,#8 - 0x01006708: 1c61 a. ADDS r1,r4,#1 - 0x0100670a: 0089 .. LSLS r1,r1,#2 - 0x0100670c: 466a jF MOV r2,sp - 0x0100670e: 5050 PP STR r0,[r2,r1] - 0x01006710: 1c64 d. ADDS r4,r4,#1 - 0x01006712: 2c00 ., CMP r4,#0 - 0x01006714: d0cc .. BEQ 0x10066b0 ; rt_timer_start + 124 - 0x01006716: 483b ;H LDR r0,[pc,#236] ; [0x1006804] = 0x20064 - 0x01006718: 6800 .h LDR r0,[r0,#0] - 0x0100671a: 1c40 @. ADDS r0,r0,#1 - 0x0100671c: 4939 9I LDR r1,[pc,#228] ; [0x1006804] = 0x20064 - 0x0100671e: 6008 .` STR r0,[r1,#0] - 0x01006720: 4608 .F MOV r0,r1 - 0x01006722: 6807 .h LDR r7,[r0,#0] - 0x01006724: 4629 )F MOV r1,r5 - 0x01006726: 3114 .1 ADDS r1,r1,#0x14 - 0x01006728: 9800 .. LDR r0,[sp,#0] - 0x0100672a: f7fdfeff .... BL rt_list_insert_after ; 0x100452c - 0x0100672e: 2402 .$ MOVS r4,#2 - 0x01006730: e014 .. B 0x100675c ; rt_timer_start + 296 - 0x01006732: 07b8 .. LSLS r0,r7,#30 - 0x01006734: 0f80 .. LSRS r0,r0,#30 - 0x01006736: 2800 .( CMP r0,#0 - 0x01006738: d10d .. BNE 0x1006756 ; rt_timer_start + 290 - 0x0100673a: 2201 ." MOVS r2,#1 - 0x0100673c: 1b12 .. SUBS r2,r2,r4 - 0x0100673e: 00d2 .. LSLS r2,r2,#3 - 0x01006740: 462b +F MOV r3,r5 - 0x01006742: 3314 .3 ADDS r3,r3,#0x14 - 0x01006744: 18d1 .. ADDS r1,r2,r3 - 0x01006746: 2201 ." MOVS r2,#1 - 0x01006748: 1b12 .. SUBS r2,r2,r4 - 0x0100674a: 0092 .. LSLS r2,r2,#2 - 0x0100674c: 466b kF MOV r3,sp - 0x0100674e: 5898 .X LDR r0,[r3,r2] - 0x01006750: f7fdfeec .... BL rt_list_insert_after ; 0x100452c - 0x01006754: e000 .. B 0x1006758 ; rt_timer_start + 292 - 0x01006756: e003 .. B 0x1006760 ; rt_timer_start + 300 - 0x01006758: 08bf .. LSRS r7,r7,#2 - 0x0100675a: 1c64 d. ADDS r4,r4,#1 - 0x0100675c: 2c01 ., CMP r4,#1 - 0x0100675e: d9e8 .. BLS 0x1006732 ; rt_timer_start + 254 - 0x01006760: bf00 .. NOP - 0x01006762: 7a68 hz LDRB r0,[r5,#9] - 0x01006764: 2101 .! MOVS r1,#1 - 0x01006766: 4308 .C ORRS r0,r0,r1 - 0x01006768: 7268 hr STRB r0,[r5,#9] - 0x0100676a: 9802 .. LDR r0,[sp,#8] - 0x0100676c: f7f9feac .... BL rt_hw_interrupt_enable ; 0x10004c8 - 0x01006770: 9801 .. LDR r0,[sp,#4] - 0x01006772: 2800 .( CMP r0,#0 - 0x01006774: d001 .. BEQ 0x100677a ; rt_timer_start + 326 - 0x01006776: f7fefc5d ..]. BL rt_schedule ; 0x1005034 - 0x0100677a: 2000 . MOVS r0,#0 - 0x0100677c: bdfe .. POP {r1-r7,pc} - $d - 0x0100677e: 0000 .. DCW 0 - 0x01006780: 01007a1e .z.. DCD 16808478 - 0x01006784: 656d6974 time DCD 1701669236 - 0x01006788: 3d212072 r != DCD 1025581170 - 0x0100678c: 5f545220 RT_ DCD 1599361568 - 0x01006790: 4c4c554e NULL DCD 1280070990 - 0x01006794: 00000000 .... DCD 0 - 0x01006798: 6f5f7472 rt_o DCD 1868526706 - 0x0100679c: 63656a62 bjec DCD 1667590754 - 0x010067a0: 65675f74 t_ge DCD 1701273460 - 0x010067a4: 79745f74 t_ty DCD 2037669748 - 0x010067a8: 26286570 pe(& DCD 640181616 - 0x010067ac: 656d6974 time DCD 1701669236 - 0x010067b0: 703e2d72 r->p DCD 1883123058 - 0x010067b4: 6e657261 aren DCD 1852142177 - 0x010067b8: 3d202974 t) = DCD 1025517940 - 0x010067bc: 5452203d = RT DCD 1414668349 - 0x010067c0: 6a624f5f _Obj DCD 1784827743 - 0x010067c4: 5f746365 ect_ DCD 1601463141 - 0x010067c8: 73616c43 Clas DCD 1935764547 - 0x010067cc: 69545f73 s_Ti DCD 1767137139 - 0x010067d0: 0072656d mer. DCD 7497069 - 0x010067d4: 00020114 .... DCD 131348 - 0x010067d8: 7fffffff .... DCD 2147483647 - 0x010067dc: 656d6974 time DCD 1701669236 - 0x010067e0: 693e2d72 r->i DCD 1765682546 - 0x010067e4: 5f74696e nit_ DCD 1601464686 - 0x010067e8: 6b636974 tick DCD 1801677172 - 0x010067ec: 52203c20 < R DCD 1377844256 - 0x010067f0: 49545f54 T_TI DCD 1230266196 - 0x010067f4: 4d5f4b43 CK_M DCD 1298090819 - 0x010067f8: 2f205841 AX / DCD 790648897 - 0x010067fc: 00003220 2.. DCD 12832 - 0x01006800: 00020054 T... DCD 131156 - 0x01006804: 00020064 d... DCD 131172 - $t - i.rt_timer_stop - rt_timer_stop - 0x01006808: b570 p. PUSH {r4-r6,lr} - 0x0100680a: 4604 .F MOV r4,r0 - 0x0100680c: 2c00 ., CMP r4,#0 - 0x0100680e: d105 .. BNE 0x100681c ; rt_timer_stop + 20 - 0x01006810: 22ff ." MOVS r2,#0xff - 0x01006812: 32f6 .2 ADDS r2,r2,#0xf6 - 0x01006814: 4917 .I LDR r1,[pc,#92] ; [0x1006874] = 0x1007a2d - 0x01006816: a018 .. ADR r0,{pc}+0x62 ; 0x1006878 - 0x01006818: f7fcfef2 .... BL rt_assert_handler ; 0x1003600 - 0x0100681c: 4620 F MOV r0,r4 - 0x0100681e: f7fefb25 ..%. BL rt_object_get_type ; 0x1004e6c - 0x01006822: 280a .( CMP r0,#0xa - 0x01006824: d005 .. BEQ 0x1006832 ; rt_timer_stop + 42 - 0x01006826: 22ff ." MOVS r2,#0xff - 0x01006828: 32f7 .2 ADDS r2,r2,#0xf7 - 0x0100682a: 4912 .I LDR r1,[pc,#72] ; [0x1006874] = 0x1007a2d - 0x0100682c: a017 .. ADR r0,{pc}+0x60 ; 0x100688c - 0x0100682e: f7fcfee7 .... BL rt_assert_handler ; 0x1003600 - 0x01006832: 7a60 `z LDRB r0,[r4,#9] - 0x01006834: 07c0 .. LSLS r0,r0,#31 - 0x01006836: 0fc0 .. LSRS r0,r0,#31 - 0x01006838: 2800 .( CMP r0,#0 - 0x0100683a: d101 .. BNE 0x1006840 ; rt_timer_stop + 56 - 0x0100683c: 1e40 @. SUBS r0,r0,#1 - 0x0100683e: bd70 p. POP {r4-r6,pc} - 0x01006840: bf00 .. NOP - 0x01006842: 4821 !H LDR r0,[pc,#132] ; [0x10068c8] = 0x20118 - 0x01006844: 6800 .h LDR r0,[r0,#0] - 0x01006846: 2800 .( CMP r0,#0 - 0x01006848: d003 .. BEQ 0x1006852 ; rt_timer_stop + 74 - 0x0100684a: 4620 F MOV r0,r4 - 0x0100684c: 491e .I LDR r1,[pc,#120] ; [0x10068c8] = 0x20118 - 0x0100684e: 6809 .h LDR r1,[r1,#0] - 0x01006850: 4788 .G BLX r1 - 0x01006852: bf00 .. NOP - 0x01006854: f7f9fe34 ..4. BL rt_hw_interrupt_disable ; 0x10004c0 - 0x01006858: 4605 .F MOV r5,r0 - 0x0100685a: 4620 F MOV r0,r4 - 0x0100685c: f7faff82 .... BL _timer_remove ; 0x1001764 - 0x01006860: 7a60 `z LDRB r0,[r4,#9] - 0x01006862: 0840 @. LSRS r0,r0,#1 - 0x01006864: 0040 @. LSLS r0,r0,#1 - 0x01006866: 7260 `r STRB r0,[r4,#9] - 0x01006868: 4628 (F MOV r0,r5 - 0x0100686a: f7f9fe2d ..-. BL rt_hw_interrupt_enable ; 0x10004c8 - 0x0100686e: 2000 . MOVS r0,#0 - 0x01006870: e7e5 .. B 0x100683e ; rt_timer_stop + 54 - $d - 0x01006872: 0000 .. DCW 0 - 0x01006874: 01007a2d -z.. DCD 16808493 - 0x01006878: 656d6974 time DCD 1701669236 - 0x0100687c: 3d212072 r != DCD 1025581170 - 0x01006880: 5f545220 RT_ DCD 1599361568 - 0x01006884: 4c4c554e NULL DCD 1280070990 - 0x01006888: 00000000 .... DCD 0 - 0x0100688c: 6f5f7472 rt_o DCD 1868526706 - 0x01006890: 63656a62 bjec DCD 1667590754 - 0x01006894: 65675f74 t_ge DCD 1701273460 - 0x01006898: 79745f74 t_ty DCD 2037669748 - 0x0100689c: 26286570 pe(& DCD 640181616 - 0x010068a0: 656d6974 time DCD 1701669236 - 0x010068a4: 703e2d72 r->p DCD 1883123058 - 0x010068a8: 6e657261 aren DCD 1852142177 - 0x010068ac: 3d202974 t) = DCD 1025517940 - 0x010068b0: 5452203d = RT DCD 1414668349 - 0x010068b4: 6a624f5f _Obj DCD 1784827743 - 0x010068b8: 5f746365 ect_ DCD 1601463141 - 0x010068bc: 73616c43 Clas DCD 1935764547 - 0x010068c0: 69545f73 s_Ti DCD 1767137139 - 0x010068c4: 0072656d mer. DCD 7497069 - 0x010068c8: 00020118 .... DCD 131352 - $t - i.rt_vsnprintf - rt_vsnprintf - 0x010068cc: b5ff .. PUSH {r0-r7,lr} - 0x010068ce: b08b .. SUB sp,sp,#0x2c - 0x010068d0: 9c0b .. LDR r4,[sp,#0x2c] - 0x010068d2: 9c0b .. LDR r4,[sp,#0x2c] - 0x010068d4: 980c .. LDR r0,[sp,#0x30] - 0x010068d6: 1826 &. ADDS r6,r4,r0 - 0x010068d8: 9c0b .. LDR r4,[sp,#0x2c] - 0x010068da: 42a6 .B CMP r6,r4 - 0x010068dc: d204 .. BCS 0x10068e8 ; rt_vsnprintf + 28 - 0x010068de: 2600 .& MOVS r6,#0 - 0x010068e0: 43f6 .C MVNS r6,r6 - 0x010068e2: 980b .. LDR r0,[sp,#0x2c] - 0x010068e4: 1a30 0. SUBS r0,r6,r0 - 0x010068e6: 900c .. STR r0,[sp,#0x30] - 0x010068e8: e194 .. B 0x1006c14 ; rt_vsnprintf + 840 - 0x010068ea: 980d .. LDR r0,[sp,#0x34] - 0x010068ec: 7800 .x LDRB r0,[r0,#0] - 0x010068ee: 2825 %( CMP r0,#0x25 - 0x010068f0: d006 .. BEQ 0x1006900 ; rt_vsnprintf + 52 - 0x010068f2: 42b4 .B CMP r4,r6 - 0x010068f4: d202 .. BCS 0x10068fc ; rt_vsnprintf + 48 - 0x010068f6: 980d .. LDR r0,[sp,#0x34] - 0x010068f8: 7800 .x LDRB r0,[r0,#0] - 0x010068fa: 7020 p STRB r0,[r4,#0] - 0x010068fc: 1c64 d. ADDS r4,r4,#1 - 0x010068fe: e186 .. B 0x1006c0e ; rt_vsnprintf + 834 - 0x01006900: 2500 .% MOVS r5,#0 - 0x01006902: e026 &. B 0x1006952 ; rt_vsnprintf + 134 - 0x01006904: 980d .. LDR r0,[sp,#0x34] - 0x01006906: 1c40 @. ADDS r0,r0,#1 - 0x01006908: 900d .. STR r0,[sp,#0x34] - 0x0100690a: 980d .. LDR r0,[sp,#0x34] - 0x0100690c: 7800 .x LDRB r0,[r0,#0] - 0x0100690e: 282d -( CMP r0,#0x2d - 0x01006910: d102 .. BNE 0x1006918 ; rt_vsnprintf + 76 - 0x01006912: 2010 . MOVS r0,#0x10 - 0x01006914: 4305 .C ORRS r5,r5,r0 - 0x01006916: e01c .. B 0x1006952 ; rt_vsnprintf + 134 - 0x01006918: 980d .. LDR r0,[sp,#0x34] - 0x0100691a: 7800 .x LDRB r0,[r0,#0] - 0x0100691c: 282b +( CMP r0,#0x2b - 0x0100691e: d102 .. BNE 0x1006926 ; rt_vsnprintf + 90 - 0x01006920: 2004 . MOVS r0,#4 - 0x01006922: 4305 .C ORRS r5,r5,r0 - 0x01006924: e015 .. B 0x1006952 ; rt_vsnprintf + 134 - 0x01006926: 980d .. LDR r0,[sp,#0x34] - 0x01006928: 7800 .x LDRB r0,[r0,#0] - 0x0100692a: 2820 ( CMP r0,#0x20 - 0x0100692c: d102 .. BNE 0x1006934 ; rt_vsnprintf + 104 - 0x0100692e: 2008 . MOVS r0,#8 - 0x01006930: 4305 .C ORRS r5,r5,r0 - 0x01006932: e00e .. B 0x1006952 ; rt_vsnprintf + 134 - 0x01006934: 980d .. LDR r0,[sp,#0x34] - 0x01006936: 7800 .x LDRB r0,[r0,#0] - 0x01006938: 2823 #( CMP r0,#0x23 - 0x0100693a: d102 .. BNE 0x1006942 ; rt_vsnprintf + 118 - 0x0100693c: 2020 MOVS r0,#0x20 - 0x0100693e: 4305 .C ORRS r5,r5,r0 - 0x01006940: e007 .. B 0x1006952 ; rt_vsnprintf + 134 - 0x01006942: 980d .. LDR r0,[sp,#0x34] - 0x01006944: 7800 .x LDRB r0,[r0,#0] - 0x01006946: 2830 0( CMP r0,#0x30 - 0x01006948: d102 .. BNE 0x1006950 ; rt_vsnprintf + 132 - 0x0100694a: 2001 . MOVS r0,#1 - 0x0100694c: 4305 .C ORRS r5,r5,r0 - 0x0100694e: e000 .. B 0x1006952 ; rt_vsnprintf + 134 - 0x01006950: e000 .. B 0x1006954 ; rt_vsnprintf + 136 - 0x01006952: e7d7 .. B 0x1006904 ; rt_vsnprintf + 56 - 0x01006954: bf00 .. NOP - 0x01006956: 2700 .' MOVS r7,#0 - 0x01006958: 43ff .C MVNS r7,r7 - 0x0100695a: 980d .. LDR r0,[sp,#0x34] - 0x0100695c: 7800 .x LDRB r0,[r0,#0] - 0x0100695e: 3830 08 SUBS r0,r0,#0x30 - 0x01006960: 280a .( CMP r0,#0xa - 0x01006962: d204 .. BCS 0x100696e ; rt_vsnprintf + 162 - 0x01006964: a80d .. ADD r0,sp,#0x34 - 0x01006966: f000fa53 ..S. BL skip_atoi ; 0x1006e10 - 0x0100696a: 4607 .F MOV r7,r0 - 0x0100696c: e00e .. B 0x100698c ; rt_vsnprintf + 192 - 0x0100696e: 980d .. LDR r0,[sp,#0x34] - 0x01006970: 7800 .x LDRB r0,[r0,#0] - 0x01006972: 282a *( CMP r0,#0x2a - 0x01006974: d10a .. BNE 0x100698c ; rt_vsnprintf + 192 - 0x01006976: 980d .. LDR r0,[sp,#0x34] - 0x01006978: 1c40 @. ADDS r0,r0,#1 - 0x0100697a: 900d .. STR r0,[sp,#0x34] - 0x0100697c: 980e .. LDR r0,[sp,#0x38] - 0x0100697e: c880 .. LDM r0!,{r7} - 0x01006980: 900e .. STR r0,[sp,#0x38] - 0x01006982: 2f00 ./ CMP r7,#0 - 0x01006984: da02 .. BGE 0x100698c ; rt_vsnprintf + 192 - 0x01006986: 427f .B RSBS r7,r7,#0 - 0x01006988: 2010 . MOVS r0,#0x10 - 0x0100698a: 4305 .C ORRS r5,r5,r0 - 0x0100698c: 2000 . MOVS r0,#0 - 0x0100698e: 43c0 .C MVNS r0,r0 - 0x01006990: 9003 .. STR r0,[sp,#0xc] - 0x01006992: 980d .. LDR r0,[sp,#0x34] - 0x01006994: 7800 .x LDRB r0,[r0,#0] - 0x01006996: 282e .( CMP r0,#0x2e - 0x01006998: d11e .. BNE 0x10069d8 ; rt_vsnprintf + 268 - 0x0100699a: 980d .. LDR r0,[sp,#0x34] - 0x0100699c: 1c40 @. ADDS r0,r0,#1 - 0x0100699e: 900d .. STR r0,[sp,#0x34] - 0x010069a0: 980d .. LDR r0,[sp,#0x34] - 0x010069a2: 7800 .x LDRB r0,[r0,#0] - 0x010069a4: 3830 08 SUBS r0,r0,#0x30 - 0x010069a6: 280a .( CMP r0,#0xa - 0x010069a8: d204 .. BCS 0x10069b4 ; rt_vsnprintf + 232 - 0x010069aa: a80d .. ADD r0,sp,#0x34 - 0x010069ac: f000fa30 ..0. BL skip_atoi ; 0x1006e10 - 0x010069b0: 9003 .. STR r0,[sp,#0xc] - 0x010069b2: e00c .. B 0x10069ce ; rt_vsnprintf + 258 - 0x010069b4: 980d .. LDR r0,[sp,#0x34] - 0x010069b6: 7800 .x LDRB r0,[r0,#0] - 0x010069b8: 282a *( CMP r0,#0x2a - 0x010069ba: d108 .. BNE 0x10069ce ; rt_vsnprintf + 258 - 0x010069bc: 980d .. LDR r0,[sp,#0x34] - 0x010069be: 1c40 @. ADDS r0,r0,#1 - 0x010069c0: 900d .. STR r0,[sp,#0x34] - 0x010069c2: 980e .. LDR r0,[sp,#0x38] - 0x010069c4: 6800 .h LDR r0,[r0,#0] - 0x010069c6: 9003 .. STR r0,[sp,#0xc] - 0x010069c8: 980e .. LDR r0,[sp,#0x38] - 0x010069ca: 1d00 .. ADDS r0,r0,#4 - 0x010069cc: 900e .. STR r0,[sp,#0x38] - 0x010069ce: 9803 .. LDR r0,[sp,#0xc] - 0x010069d0: 2800 .( CMP r0,#0 - 0x010069d2: da01 .. BGE 0x10069d8 ; rt_vsnprintf + 268 - 0x010069d4: 2000 . MOVS r0,#0 - 0x010069d6: 9003 .. STR r0,[sp,#0xc] - 0x010069d8: 2000 . MOVS r0,#0 - 0x010069da: 9004 .. STR r0,[sp,#0x10] - 0x010069dc: 980d .. LDR r0,[sp,#0x34] - 0x010069de: 7800 .x LDRB r0,[r0,#0] - 0x010069e0: 2868 h( CMP r0,#0x68 - 0x010069e2: d003 .. BEQ 0x10069ec ; rt_vsnprintf + 288 - 0x010069e4: 980d .. LDR r0,[sp,#0x34] - 0x010069e6: 7800 .x LDRB r0,[r0,#0] - 0x010069e8: 286c l( CMP r0,#0x6c - 0x010069ea: d105 .. BNE 0x10069f8 ; rt_vsnprintf + 300 - 0x010069ec: 980d .. LDR r0,[sp,#0x34] - 0x010069ee: 7800 .x LDRB r0,[r0,#0] - 0x010069f0: 9004 .. STR r0,[sp,#0x10] - 0x010069f2: 980d .. LDR r0,[sp,#0x34] - 0x010069f4: 1c40 @. ADDS r0,r0,#1 - 0x010069f6: 900d .. STR r0,[sp,#0x34] - 0x010069f8: 200a . MOVS r0,#0xa - 0x010069fa: 9005 .. STR r0,[sp,#0x14] - 0x010069fc: 980d .. LDR r0,[sp,#0x34] - 0x010069fe: 7800 .x LDRB r0,[r0,#0] - 0x01006a00: 286f o( CMP r0,#0x6f - 0x01006a02: d07d }. BEQ 0x1006b00 ; rt_vsnprintf + 564 - 0x01006a04: dc0c .. BGT 0x1006a20 ; rt_vsnprintf + 340 - 0x01006a06: 2863 c( CMP r0,#0x63 - 0x01006a08: d013 .. BEQ 0x1006a32 ; rt_vsnprintf + 358 - 0x01006a0a: dc04 .. BGT 0x1006a16 ; rt_vsnprintf + 330 - 0x01006a0c: 2825 %( CMP r0,#0x25 - 0x01006a0e: d078 x. BEQ 0x1006b02 ; rt_vsnprintf + 566 - 0x01006a10: 2858 X( CMP r0,#0x58 - 0x01006a12: d177 w. BNE 0x1006b04 ; rt_vsnprintf + 568 - 0x01006a14: e0a2 .. B 0x1006b5c ; rt_vsnprintf + 656 - 0x01006a16: 2864 d( CMP r0,#0x64 - 0x01006a18: d075 u. BEQ 0x1006b06 ; rt_vsnprintf + 570 - 0x01006a1a: 2869 i( CMP r0,#0x69 - 0x01006a1c: d1f9 .. BNE 0x1006a12 ; rt_vsnprintf + 326 - 0x01006a1e: e0a4 .. B 0x1006b6a ; rt_vsnprintf + 670 - 0x01006a20: 2870 p( CMP r0,#0x70 - 0x01006a22: d07e ~. BEQ 0x1006b22 ; rt_vsnprintf + 598 - 0x01006a24: 2873 s( CMP r0,#0x73 - 0x01006a26: d026 &. BEQ 0x1006a76 ; rt_vsnprintf + 426 - 0x01006a28: 2875 u( CMP r0,#0x75 - 0x01006a2a: d06e n. BEQ 0x1006b0a ; rt_vsnprintf + 574 - 0x01006a2c: 2878 x( CMP r0,#0x78 - 0x01006a2e: d1f0 .. BNE 0x1006a12 ; rt_vsnprintf + 326 - 0x01006a30: e097 .. B 0x1006b62 ; rt_vsnprintf + 662 - 0x01006a32: 2010 . MOVS r0,#0x10 - 0x01006a34: 4028 (@ ANDS r0,r0,r5 - 0x01006a36: 2800 .( CMP r0,#0 - 0x01006a38: d108 .. BNE 0x1006a4c ; rt_vsnprintf + 384 - 0x01006a3a: e004 .. B 0x1006a46 ; rt_vsnprintf + 378 - 0x01006a3c: 42b4 .B CMP r4,r6 - 0x01006a3e: d201 .. BCS 0x1006a44 ; rt_vsnprintf + 376 - 0x01006a40: 2020 MOVS r0,#0x20 - 0x01006a42: 7020 p STRB r0,[r4,#0] - 0x01006a44: 1c64 d. ADDS r4,r4,#1 - 0x01006a46: 1e78 x. SUBS r0,r7,#1 - 0x01006a48: 1e07 .. SUBS r7,r0,#0 - 0x01006a4a: dcf7 .. BGT 0x1006a3c ; rt_vsnprintf + 368 - 0x01006a4c: 980e .. LDR r0,[sp,#0x38] - 0x01006a4e: 7801 .x LDRB r1,[r0,#0] - 0x01006a50: 1d00 .. ADDS r0,r0,#4 - 0x01006a52: 900e .. STR r0,[sp,#0x38] - 0x01006a54: b2c8 .. UXTB r0,r1 - 0x01006a56: 9007 .. STR r0,[sp,#0x1c] - 0x01006a58: 42b4 .B CMP r4,r6 - 0x01006a5a: d201 .. BCS 0x1006a60 ; rt_vsnprintf + 404 - 0x01006a5c: 9807 .. LDR r0,[sp,#0x1c] - 0x01006a5e: 7020 p STRB r0,[r4,#0] - 0x01006a60: 1c64 d. ADDS r4,r4,#1 - 0x01006a62: e004 .. B 0x1006a6e ; rt_vsnprintf + 418 - 0x01006a64: 42b4 .B CMP r4,r6 - 0x01006a66: d201 .. BCS 0x1006a6c ; rt_vsnprintf + 416 - 0x01006a68: 2020 MOVS r0,#0x20 - 0x01006a6a: 7020 p STRB r0,[r4,#0] - 0x01006a6c: 1c64 d. ADDS r4,r4,#1 - 0x01006a6e: 1e78 x. SUBS r0,r7,#1 - 0x01006a70: 1e07 .. SUBS r7,r0,#0 - 0x01006a72: dcf7 .. BGT 0x1006a64 ; rt_vsnprintf + 408 - 0x01006a74: e0cb .. B 0x1006c0e ; rt_vsnprintf + 834 - 0x01006a76: 980e .. LDR r0,[sp,#0x38] - 0x01006a78: 6800 .h LDR r0,[r0,#0] - 0x01006a7a: 9006 .. STR r0,[sp,#0x18] - 0x01006a7c: 980e .. LDR r0,[sp,#0x38] - 0x01006a7e: 1d00 .. ADDS r0,r0,#4 - 0x01006a80: 900e .. STR r0,[sp,#0x38] - 0x01006a82: 9806 .. LDR r0,[sp,#0x18] - 0x01006a84: 2800 .( CMP r0,#0 - 0x01006a86: d101 .. BNE 0x1006a8c ; rt_vsnprintf + 448 - 0x01006a88: a06d m. ADR r0,{pc}+0x1b8 ; 0x1006c40 - 0x01006a8a: 9006 .. STR r0,[sp,#0x18] - 0x01006a8c: 2000 . MOVS r0,#0 - 0x01006a8e: 9008 .. STR r0,[sp,#0x20] - 0x01006a90: e002 .. B 0x1006a98 ; rt_vsnprintf + 460 - 0x01006a92: 9808 .. LDR r0,[sp,#0x20] - 0x01006a94: 1c40 @. ADDS r0,r0,#1 - 0x01006a96: 9008 .. STR r0,[sp,#0x20] - 0x01006a98: 9808 .. LDR r0,[sp,#0x20] - 0x01006a9a: 42b8 .B CMP r0,r7 - 0x01006a9c: d004 .. BEQ 0x1006aa8 ; rt_vsnprintf + 476 - 0x01006a9e: 9908 .. LDR r1,[sp,#0x20] - 0x01006aa0: 9806 .. LDR r0,[sp,#0x18] - 0x01006aa2: 5c40 @\ LDRB r0,[r0,r1] - 0x01006aa4: 2800 .( CMP r0,#0 - 0x01006aa6: d1f4 .. BNE 0x1006a92 ; rt_vsnprintf + 454 - 0x01006aa8: 9803 .. LDR r0,[sp,#0xc] - 0x01006aaa: 2800 .( CMP r0,#0 - 0x01006aac: dd05 .. BLE 0x1006aba ; rt_vsnprintf + 494 - 0x01006aae: 9903 .. LDR r1,[sp,#0xc] - 0x01006ab0: 9808 .. LDR r0,[sp,#0x20] - 0x01006ab2: 4288 .B CMP r0,r1 - 0x01006ab4: dd01 .. BLE 0x1006aba ; rt_vsnprintf + 494 - 0x01006ab6: 9803 .. LDR r0,[sp,#0xc] - 0x01006ab8: 9008 .. STR r0,[sp,#0x20] - 0x01006aba: 2010 . MOVS r0,#0x10 - 0x01006abc: 4028 (@ ANDS r0,r0,r5 - 0x01006abe: 2800 .( CMP r0,#0 - 0x01006ac0: d10a .. BNE 0x1006ad8 ; rt_vsnprintf + 524 - 0x01006ac2: e004 .. B 0x1006ace ; rt_vsnprintf + 514 - 0x01006ac4: 42b4 .B CMP r4,r6 - 0x01006ac6: d201 .. BCS 0x1006acc ; rt_vsnprintf + 512 - 0x01006ac8: 2020 MOVS r0,#0x20 - 0x01006aca: 7020 p STRB r0,[r4,#0] - 0x01006acc: 1c64 d. ADDS r4,r4,#1 - 0x01006ace: 4638 8F MOV r0,r7 - 0x01006ad0: 1e7f .. SUBS r7,r7,#1 - 0x01006ad2: 9908 .. LDR r1,[sp,#0x20] - 0x01006ad4: 4288 .B CMP r0,r1 - 0x01006ad6: dcf5 .. BGT 0x1006ac4 ; rt_vsnprintf + 504 - 0x01006ad8: 2000 . MOVS r0,#0 - 0x01006ada: 9009 .. STR r0,[sp,#0x24] - 0x01006adc: e00b .. B 0x1006af6 ; rt_vsnprintf + 554 - 0x01006ade: 42b4 .B CMP r4,r6 - 0x01006ae0: d202 .. BCS 0x1006ae8 ; rt_vsnprintf + 540 - 0x01006ae2: 9806 .. LDR r0,[sp,#0x18] - 0x01006ae4: 7800 .x LDRB r0,[r0,#0] - 0x01006ae6: 7020 p STRB r0,[r4,#0] - 0x01006ae8: 1c64 d. ADDS r4,r4,#1 - 0x01006aea: 9806 .. LDR r0,[sp,#0x18] - 0x01006aec: 1c40 @. ADDS r0,r0,#1 - 0x01006aee: 9006 .. STR r0,[sp,#0x18] - 0x01006af0: 9809 .. LDR r0,[sp,#0x24] - 0x01006af2: 1c40 @. ADDS r0,r0,#1 - 0x01006af4: 9009 .. STR r0,[sp,#0x24] - 0x01006af6: 9908 .. LDR r1,[sp,#0x20] - 0x01006af8: 9809 .. LDR r0,[sp,#0x24] - 0x01006afa: 4288 .B CMP r0,r1 - 0x01006afc: dbef .. BLT 0x1006ade ; rt_vsnprintf + 530 - 0x01006afe: e00a .. B 0x1006b16 ; rt_vsnprintf + 586 - 0x01006b00: e029 ). B 0x1006b56 ; rt_vsnprintf + 650 - 0x01006b02: e022 ". B 0x1006b4a ; rt_vsnprintf + 638 - 0x01006b04: e035 5. B 0x1006b72 ; rt_vsnprintf + 678 - 0x01006b06: e02f /. B 0x1006b68 ; rt_vsnprintf + 668 - 0x01006b08: e00b .. B 0x1006b22 ; rt_vsnprintf + 598 - 0x01006b0a: e031 1. B 0x1006b70 ; rt_vsnprintf + 676 - 0x01006b0c: 42b4 .B CMP r4,r6 - 0x01006b0e: d201 .. BCS 0x1006b14 ; rt_vsnprintf + 584 - 0x01006b10: 2020 MOVS r0,#0x20 - 0x01006b12: 7020 p STRB r0,[r4,#0] - 0x01006b14: 1c64 d. ADDS r4,r4,#1 - 0x01006b16: 4638 8F MOV r0,r7 - 0x01006b18: 1e7f .. SUBS r7,r7,#1 - 0x01006b1a: 9908 .. LDR r1,[sp,#0x20] - 0x01006b1c: 4288 .B CMP r0,r1 - 0x01006b1e: dcf5 .. BGT 0x1006b0c ; rt_vsnprintf + 576 - 0x01006b20: e075 u. B 0x1006c0e ; rt_vsnprintf + 834 - 0x01006b22: 1c78 x. ADDS r0,r7,#1 - 0x01006b24: 2800 .( CMP r0,#0 - 0x01006b26: d102 .. BNE 0x1006b2e ; rt_vsnprintf + 610 - 0x01006b28: 2708 .' MOVS r7,#8 - 0x01006b2a: 2001 . MOVS r0,#1 - 0x01006b2c: 4305 .C ORRS r5,r5,r0 - 0x01006b2e: 9803 .. LDR r0,[sp,#0xc] - 0x01006b30: 9700 .. STR r7,[sp,#0] - 0x01006b32: 9502 .. STR r5,[sp,#8] - 0x01006b34: 9001 .. STR r0,[sp,#4] - 0x01006b36: 980e .. LDR r0,[sp,#0x38] - 0x01006b38: c804 .. LDM r0!,{r2} - 0x01006b3a: 2310 .# MOVS r3,#0x10 - 0x01006b3c: 4631 1F MOV r1,r6 - 0x01006b3e: 900e .. STR r0,[sp,#0x38] - 0x01006b40: 4620 F MOV r0,r4 - 0x01006b42: f7fcfc6b ..k. BL print_number ; 0x100341c - 0x01006b46: 4604 .F MOV r4,r0 - 0x01006b48: e061 a. B 0x1006c0e ; rt_vsnprintf + 834 - 0x01006b4a: 42b4 .B CMP r4,r6 - 0x01006b4c: d201 .. BCS 0x1006b52 ; rt_vsnprintf + 646 - 0x01006b4e: 2025 % MOVS r0,#0x25 - 0x01006b50: 7020 p STRB r0,[r4,#0] - 0x01006b52: 1c64 d. ADDS r4,r4,#1 - 0x01006b54: e05b [. B 0x1006c0e ; rt_vsnprintf + 834 - 0x01006b56: 2008 . MOVS r0,#8 - 0x01006b58: 9005 .. STR r0,[sp,#0x14] - 0x01006b5a: e01e .. B 0x1006b9a ; rt_vsnprintf + 718 - 0x01006b5c: 2040 @ MOVS r0,#0x40 - 0x01006b5e: 4305 .C ORRS r5,r5,r0 - 0x01006b60: bf00 .. NOP - 0x01006b62: 2010 . MOVS r0,#0x10 - 0x01006b64: 9005 .. STR r0,[sp,#0x14] - 0x01006b66: e018 .. B 0x1006b9a ; rt_vsnprintf + 718 - 0x01006b68: bf00 .. NOP - 0x01006b6a: 2002 . MOVS r0,#2 - 0x01006b6c: 4305 .C ORRS r5,r5,r0 - 0x01006b6e: bf00 .. NOP - 0x01006b70: e013 .. B 0x1006b9a ; rt_vsnprintf + 718 - 0x01006b72: 42b4 .B CMP r4,r6 - 0x01006b74: d201 .. BCS 0x1006b7a ; rt_vsnprintf + 686 - 0x01006b76: 2025 % MOVS r0,#0x25 - 0x01006b78: 7020 p STRB r0,[r4,#0] - 0x01006b7a: 1c64 d. ADDS r4,r4,#1 - 0x01006b7c: 980d .. LDR r0,[sp,#0x34] - 0x01006b7e: 7800 .x LDRB r0,[r0,#0] - 0x01006b80: 2800 .( CMP r0,#0 - 0x01006b82: d006 .. BEQ 0x1006b92 ; rt_vsnprintf + 710 - 0x01006b84: 42b4 .B CMP r4,r6 - 0x01006b86: d202 .. BCS 0x1006b8e ; rt_vsnprintf + 706 - 0x01006b88: 980d .. LDR r0,[sp,#0x34] - 0x01006b8a: 7800 .x LDRB r0,[r0,#0] - 0x01006b8c: 7020 p STRB r0,[r4,#0] - 0x01006b8e: 1c64 d. ADDS r4,r4,#1 - 0x01006b90: e002 .. B 0x1006b98 ; rt_vsnprintf + 716 - 0x01006b92: 980d .. LDR r0,[sp,#0x34] - 0x01006b94: 1e40 @. SUBS r0,r0,#1 - 0x01006b96: 900d .. STR r0,[sp,#0x34] - 0x01006b98: e039 9. B 0x1006c0e ; rt_vsnprintf + 834 - 0x01006b9a: bf00 .. NOP - 0x01006b9c: 9804 .. LDR r0,[sp,#0x10] - 0x01006b9e: 286c l( CMP r0,#0x6c - 0x01006ba0: d10c .. BNE 0x1006bbc ; rt_vsnprintf + 752 - 0x01006ba2: 980e .. LDR r0,[sp,#0x38] - 0x01006ba4: 6800 .h LDR r0,[r0,#0] - 0x01006ba6: 900a .. STR r0,[sp,#0x28] - 0x01006ba8: 980e .. LDR r0,[sp,#0x38] - 0x01006baa: 1d00 .. ADDS r0,r0,#4 - 0x01006bac: 900e .. STR r0,[sp,#0x38] - 0x01006bae: 2002 . MOVS r0,#2 - 0x01006bb0: 4028 (@ ANDS r0,r0,r5 - 0x01006bb2: 2800 .( CMP r0,#0 - 0x01006bb4: d01f .. BEQ 0x1006bf6 ; rt_vsnprintf + 810 - 0x01006bb6: 980a .. LDR r0,[sp,#0x28] - 0x01006bb8: 900a .. STR r0,[sp,#0x28] - 0x01006bba: e01c .. B 0x1006bf6 ; rt_vsnprintf + 810 - 0x01006bbc: 9804 .. LDR r0,[sp,#0x10] - 0x01006bbe: 2868 h( CMP r0,#0x68 - 0x01006bc0: d10d .. BNE 0x1006bde ; rt_vsnprintf + 786 - 0x01006bc2: 980e .. LDR r0,[sp,#0x38] - 0x01006bc4: 8801 .. LDRH r1,[r0,#0] - 0x01006bc6: 1d00 .. ADDS r0,r0,#4 - 0x01006bc8: 900e .. STR r0,[sp,#0x38] - 0x01006bca: b288 .. UXTH r0,r1 - 0x01006bcc: 900a .. STR r0,[sp,#0x28] - 0x01006bce: 2002 . MOVS r0,#2 - 0x01006bd0: 4028 (@ ANDS r0,r0,r5 - 0x01006bd2: 2800 .( CMP r0,#0 - 0x01006bd4: d00f .. BEQ 0x1006bf6 ; rt_vsnprintf + 810 - 0x01006bd6: 980a .. LDR r0,[sp,#0x28] - 0x01006bd8: b200 .. SXTH r0,r0 - 0x01006bda: 900a .. STR r0,[sp,#0x28] - 0x01006bdc: e00b .. B 0x1006bf6 ; rt_vsnprintf + 810 - 0x01006bde: 980e .. LDR r0,[sp,#0x38] - 0x01006be0: 6800 .h LDR r0,[r0,#0] - 0x01006be2: 900a .. STR r0,[sp,#0x28] - 0x01006be4: 980e .. LDR r0,[sp,#0x38] - 0x01006be6: 1d00 .. ADDS r0,r0,#4 - 0x01006be8: 900e .. STR r0,[sp,#0x38] - 0x01006bea: 2002 . MOVS r0,#2 - 0x01006bec: 4028 (@ ANDS r0,r0,r5 - 0x01006bee: 2800 .( CMP r0,#0 - 0x01006bf0: d001 .. BEQ 0x1006bf6 ; rt_vsnprintf + 810 - 0x01006bf2: 980a .. LDR r0,[sp,#0x28] - 0x01006bf4: 900a .. STR r0,[sp,#0x28] - 0x01006bf6: 9803 .. LDR r0,[sp,#0xc] - 0x01006bf8: 9700 .. STR r7,[sp,#0] - 0x01006bfa: 9502 .. STR r5,[sp,#8] - 0x01006bfc: 9001 .. STR r0,[sp,#4] - 0x01006bfe: 4631 1F MOV r1,r6 - 0x01006c00: 4620 F MOV r0,r4 - 0x01006c02: 9b05 .. LDR r3,[sp,#0x14] - 0x01006c04: 9a0a .. LDR r2,[sp,#0x28] - 0x01006c06: f7fcfc09 .... BL print_number ; 0x100341c - 0x01006c0a: 4604 .F MOV r4,r0 - 0x01006c0c: bf00 .. NOP - 0x01006c0e: 980d .. LDR r0,[sp,#0x34] - 0x01006c10: 1c40 @. ADDS r0,r0,#1 - 0x01006c12: 900d .. STR r0,[sp,#0x34] - 0x01006c14: 980d .. LDR r0,[sp,#0x34] - 0x01006c16: 7800 .x LDRB r0,[r0,#0] - 0x01006c18: 2800 .( CMP r0,#0 - 0x01006c1a: d000 .. BEQ 0x1006c1e ; rt_vsnprintf + 850 - 0x01006c1c: e665 e. B 0x10068ea ; rt_vsnprintf + 30 - 0x01006c1e: 980c .. LDR r0,[sp,#0x30] - 0x01006c20: 2800 .( CMP r0,#0 - 0x01006c22: d008 .. BEQ 0x1006c36 ; rt_vsnprintf + 874 - 0x01006c24: 42b4 .B CMP r4,r6 - 0x01006c26: d202 .. BCS 0x1006c2e ; rt_vsnprintf + 866 - 0x01006c28: 2000 . MOVS r0,#0 - 0x01006c2a: 7020 p STRB r0,[r4,#0] - 0x01006c2c: e003 .. B 0x1006c36 ; rt_vsnprintf + 874 - 0x01006c2e: 2100 .! MOVS r1,#0 - 0x01006c30: 4630 0F MOV r0,r6 - 0x01006c32: 3820 8 SUBS r0,r0,#0x20 - 0x01006c34: 77c1 .w STRB r1,[r0,#0x1f] - 0x01006c36: 980b .. LDR r0,[sp,#0x2c] - 0x01006c38: 1a20 . SUBS r0,r4,r0 - 0x01006c3a: b00f .. ADD sp,sp,#0x3c - 0x01006c3c: bdf0 .. POP {r4-r7,pc} - $d - 0x01006c3e: 0000 .. DCW 0 - 0x01006c40: 4c554e28 (NUL DCD 1280658984 - 0x01006c44: 0000294c L).. DCD 10572 - $t - i.rt_vsprintf - rt_vsprintf - 0x01006c48: b537 7. PUSH {r0-r2,r4,r5,lr} - 0x01006c4a: 4605 .F MOV r5,r0 - 0x01006c4c: 460c .F MOV r4,r1 - 0x01006c4e: 4622 "F MOV r2,r4 - 0x01006c50: 2100 .! MOVS r1,#0 - 0x01006c52: 43c9 .C MVNS r1,r1 - 0x01006c54: 4628 (F MOV r0,r5 - 0x01006c56: 9b02 .. LDR r3,[sp,#8] - 0x01006c58: f7fffe38 ..8. BL rt_vsnprintf ; 0x10068cc - 0x01006c5c: bd3e >. POP {r1-r5,pc} - i.rti_board_end - rti_board_end - 0x01006c5e: 2000 . MOVS r0,#0 - 0x01006c60: 4770 pG BX lr - i.rti_board_start - rti_board_start - 0x01006c62: 2000 . MOVS r0,#0 - 0x01006c64: 4770 pG BX lr - i.rti_end - rti_end - 0x01006c66: 2000 . MOVS r0,#0 - 0x01006c68: 4770 pG BX lr - i.rti_start - rti_start - 0x01006c6a: 2000 . MOVS r0,#0 - 0x01006c6c: 4770 pG BX lr - i.rtthread_startup - rtthread_startup - 0x01006c6e: b510 .. PUSH {r4,lr} - 0x01006c70: f7f9fc26 ..&. BL rt_hw_interrupt_disable ; 0x10004c0 - 0x01006c74: f7fdfa38 ..8. BL rt_hw_board_init ; 0x10040e8 - 0x01006c78: f7fefee0 .... BL rt_show_version ; 0x1005a3c - 0x01006c7c: f7fff852 ..R. BL rt_system_timer_init ; 0x1005d24 - 0x01006c80: f7fff820 .. . BL rt_system_scheduler_init ; 0x1005cc4 - 0x01006c84: f7fcfc94 .... BL rt_application_init ; 0x10035b0 - 0x01006c88: f7fff85a ..Z. BL rt_system_timer_thread_init ; 0x1005d40 - 0x01006c8c: f7fff8bc .... BL rt_thread_idle_init ; 0x1005e08 - 0x01006c90: f7fff834 ..4. BL rt_system_scheduler_start ; 0x1005cfc - 0x01006c94: 2000 . MOVS r0,#0 - 0x01006c96: bd10 .. POP {r4,pc} - i.shell_auto_complete - shell_auto_complete - 0x01006c98: b570 p. PUSH {r4-r6,lr} - 0x01006c9a: 4604 .F MOV r4,r0 - 0x01006c9c: a007 .. ADR r0,{pc}+0x20 ; 0x1006cbc - 0x01006c9e: f7fdfc17 .... BL rt_kprintf ; 0x10044d0 - 0x01006ca2: 4620 F MOV r0,r4 - 0x01006ca4: f7fcf9d4 .... BL msh_auto_complete ; 0x1003050 - 0x01006ca8: f7fafd8a .... BL finsh_get_prompt ; 0x10017c0 - 0x01006cac: 4605 .F MOV r5,r0 - 0x01006cae: 4622 "F MOV r2,r4 - 0x01006cb0: 4629 )F MOV r1,r5 - 0x01006cb2: a003 .. ADR r0,{pc}+0xe ; 0x1006cc0 - 0x01006cb4: f7fdfc0c .... BL rt_kprintf ; 0x10044d0 - 0x01006cb8: bd70 p. POP {r4-r6,pc} - $d - 0x01006cba: 0000 .. DCW 0 - 0x01006cbc: 0000000a .... DCD 10 - 0x01006cc0: 73257325 %s%s DCD 1931834149 - 0x01006cc4: 00000000 .... DCD 0 - $t - i.shell_handle_history - shell_handle_history - 0x01006cc8: b570 p. PUSH {r4-r6,lr} - 0x01006cca: 4604 .F MOV r4,r0 - 0x01006ccc: a007 .. ADR r0,{pc}+0x20 ; 0x1006cec - 0x01006cce: f7fdfbff .... BL rt_kprintf ; 0x10044d0 - 0x01006cd2: f7fafd75 ..u. BL finsh_get_prompt ; 0x10017c0 - 0x01006cd6: 4605 .F MOV r5,r0 - 0x01006cd8: 4622 "F MOV r2,r4 - 0x01006cda: 32ff .2 ADDS r2,r2,#0xff - 0x01006cdc: 32b7 .2 ADDS r2,r2,#0xb7 - 0x01006cde: 4629 )F MOV r1,r5 - 0x01006ce0: a004 .. ADR r0,{pc}+0x14 ; 0x1006cf4 - 0x01006ce2: f7fdfbf5 .... BL rt_kprintf ; 0x10044d0 - 0x01006ce6: 2000 . MOVS r0,#0 - 0x01006ce8: bd70 p. POP {r4-r6,pc} - $d - 0x01006cea: 0000 .. DCW 0 - 0x01006cec: 4b325b1b .[2K DCD 1261591323 - 0x01006cf0: 0000000d .... DCD 13 - 0x01006cf4: 73257325 %s%s DCD 1931834149 - 0x01006cf8: 00000000 .... DCD 0 - $t - i.shell_push_history - shell_push_history - 0x01006cfc: b570 p. PUSH {r4-r6,lr} - 0x01006cfe: 4604 .F MOV r4,r0 - 0x01006d00: 2041 A MOVS r0,#0x41 - 0x01006d02: 00c0 .. LSLS r0,r0,#3 - 0x01006d04: 5b00 .[ LDRH r0,[r0,r4] - 0x01006d06: 2800 .( CMP r0,#0 - 0x01006d08: d063 c. BEQ 0x1006dd2 ; shell_push_history + 214 - 0x01006d0a: 8ca0 .. LDRH r0,[r4,#0x24] - 0x01006d0c: 2805 .( CMP r0,#5 - 0x01006d0e: db32 2. BLT 0x1006d76 ; shell_push_history + 122 - 0x01006d10: 2250 P" MOVS r2,#0x50 - 0x01006d12: 4621 !F MOV r1,r4 - 0x01006d14: 31ff .1 ADDS r1,r1,#0xff - 0x01006d16: 31b7 .1 ADDS r1,r1,#0xb7 - 0x01006d18: 4608 .F MOV r0,r1 - 0x01006d1a: 3850 P8 SUBS r0,r0,#0x50 - 0x01006d1c: f7f9fc3c ..<. BL memcmp ; 0x1000598 - 0x01006d20: 2800 .( CMP r0,#0 - 0x01006d22: d056 V. BEQ 0x1006dd2 ; shell_push_history + 214 - 0x01006d24: 2500 .% MOVS r5,#0 - 0x01006d26: e00c .. B 0x1006d42 ; shell_push_history + 70 - 0x01006d28: 1c6a j. ADDS r2,r5,#1 - 0x01006d2a: 2350 P# MOVS r3,#0x50 - 0x01006d2c: 435a ZC MULS r2,r3,r2 - 0x01006d2e: 4623 #F MOV r3,r4 - 0x01006d30: 3326 &3 ADDS r3,r3,#0x26 - 0x01006d32: 18d1 .. ADDS r1,r2,r3 - 0x01006d34: 2250 P" MOVS r2,#0x50 - 0x01006d36: 436a jC MULS r2,r5,r2 - 0x01006d38: 18d0 .. ADDS r0,r2,r3 - 0x01006d3a: 2250 P" MOVS r2,#0x50 - 0x01006d3c: f7f9fcfe .... BL __aeabi_memcpy ; 0x100073c - 0x01006d40: 1c6d m. ADDS r5,r5,#1 - 0x01006d42: 2d04 .- CMP r5,#4 - 0x01006d44: dbf0 .. BLT 0x1006d28 ; shell_push_history + 44 - 0x01006d46: 2150 P! MOVS r1,#0x50 - 0x01006d48: 4369 iC MULS r1,r5,r1 - 0x01006d4a: 4622 "F MOV r2,r4 - 0x01006d4c: 3226 &2 ADDS r2,r2,#0x26 - 0x01006d4e: 1888 .. ADDS r0,r1,r2 - 0x01006d50: 2150 P! MOVS r1,#0x50 - 0x01006d52: f7f9fd50 ..P. BL __aeabi_memclr ; 0x10007f6 - 0x01006d56: 2141 A! MOVS r1,#0x41 - 0x01006d58: 00c9 .. LSLS r1,r1,#3 - 0x01006d5a: 5b0a .[ LDRH r2,[r1,r4] - 0x01006d5c: 2150 P! MOVS r1,#0x50 - 0x01006d5e: 4369 iC MULS r1,r5,r1 - 0x01006d60: 4623 #F MOV r3,r4 - 0x01006d62: 3326 &3 ADDS r3,r3,#0x26 - 0x01006d64: 18c8 .. ADDS r0,r1,r3 - 0x01006d66: 4621 !F MOV r1,r4 - 0x01006d68: 31ff .1 ADDS r1,r1,#0xff - 0x01006d6a: 31b7 .1 ADDS r1,r1,#0xb7 - 0x01006d6c: f7f9fce6 .... BL __aeabi_memcpy ; 0x100073c - 0x01006d70: 2005 . MOVS r0,#5 - 0x01006d72: 84a0 .. STRH r0,[r4,#0x24] - 0x01006d74: e02d -. B 0x1006dd2 ; shell_push_history + 214 - 0x01006d76: 8ca0 .. LDRH r0,[r4,#0x24] - 0x01006d78: 2800 .( CMP r0,#0 - 0x01006d7a: d00e .. BEQ 0x1006d9a ; shell_push_history + 158 - 0x01006d7c: 8ca1 .. LDRH r1,[r4,#0x24] - 0x01006d7e: 1e49 I. SUBS r1,r1,#1 - 0x01006d80: 2250 P" MOVS r2,#0x50 - 0x01006d82: 4351 QC MULS r1,r2,r1 - 0x01006d84: 4622 "F MOV r2,r4 - 0x01006d86: 3226 &2 ADDS r2,r2,#0x26 - 0x01006d88: 1888 .. ADDS r0,r1,r2 - 0x01006d8a: 2250 P" MOVS r2,#0x50 - 0x01006d8c: 4621 !F MOV r1,r4 - 0x01006d8e: 31ff .1 ADDS r1,r1,#0xff - 0x01006d90: 31b7 .1 ADDS r1,r1,#0xb7 - 0x01006d92: f7f9fc01 .... BL memcmp ; 0x1000598 - 0x01006d96: 2800 .( CMP r0,#0 - 0x01006d98: d01b .. BEQ 0x1006dd2 ; shell_push_history + 214 - 0x01006d9a: 8ca0 .. LDRH r0,[r4,#0x24] - 0x01006d9c: 8460 `. STRH r0,[r4,#0x22] - 0x01006d9e: 8ca1 .. LDRH r1,[r4,#0x24] - 0x01006da0: 2250 P" MOVS r2,#0x50 - 0x01006da2: 4351 QC MULS r1,r2,r1 - 0x01006da4: 4622 "F MOV r2,r4 - 0x01006da6: 3226 &2 ADDS r2,r2,#0x26 - 0x01006da8: 1888 .. ADDS r0,r1,r2 - 0x01006daa: 2150 P! MOVS r1,#0x50 - 0x01006dac: f7f9fd23 ..#. BL __aeabi_memclr ; 0x10007f6 - 0x01006db0: 2141 A! MOVS r1,#0x41 - 0x01006db2: 00c9 .. LSLS r1,r1,#3 - 0x01006db4: 5b0a .[ LDRH r2,[r1,r4] - 0x01006db6: 8ca1 .. LDRH r1,[r4,#0x24] - 0x01006db8: 2350 P# MOVS r3,#0x50 - 0x01006dba: 4359 YC MULS r1,r3,r1 - 0x01006dbc: 4623 #F MOV r3,r4 - 0x01006dbe: 3326 &3 ADDS r3,r3,#0x26 - 0x01006dc0: 18c8 .. ADDS r0,r1,r3 - 0x01006dc2: 4621 !F MOV r1,r4 - 0x01006dc4: 31ff .1 ADDS r1,r1,#0xff - 0x01006dc6: 31b7 .1 ADDS r1,r1,#0xb7 - 0x01006dc8: f7f9fcb8 .... BL __aeabi_memcpy ; 0x100073c - 0x01006dcc: 8ca0 .. LDRH r0,[r4,#0x24] - 0x01006dce: 1c40 @. ADDS r0,r0,#1 - 0x01006dd0: 84a0 .. STRH r0,[r4,#0x24] - 0x01006dd2: 8ca0 .. LDRH r0,[r4,#0x24] - 0x01006dd4: 8460 `. STRH r0,[r4,#0x22] - 0x01006dd6: bd70 p. POP {r4-r6,pc} - i.show_wait_queue - show_wait_queue - 0x01006dd8: b570 p. PUSH {r4-r6,lr} - 0x01006dda: 4604 .F MOV r4,r0 - 0x01006ddc: 6825 %h LDR r5,[r4,#0] - 0x01006dde: e00d .. B 0x1006dfc ; show_wait_queue + 36 - 0x01006de0: 462e .F MOV r6,r5 - 0x01006de2: 3e14 .> SUBS r6,r6,#0x14 - 0x01006de4: 4632 2F MOV r2,r6 - 0x01006de6: 2108 .! MOVS r1,#8 - 0x01006de8: a006 .. ADR r0,{pc}+0x1c ; 0x1006e04 - 0x01006dea: f7fdfb71 ..q. BL rt_kprintf ; 0x10044d0 - 0x01006dee: 6828 (h LDR r0,[r5,#0] - 0x01006df0: 42a0 .B CMP r0,r4 - 0x01006df2: d002 .. BEQ 0x1006dfa ; show_wait_queue + 34 - 0x01006df4: a005 .. ADR r0,{pc}+0x18 ; 0x1006e0c - 0x01006df6: f7fdfb6b ..k. BL rt_kprintf ; 0x10044d0 - 0x01006dfa: 682d -h LDR r5,[r5,#0] - 0x01006dfc: 42a5 .B CMP r5,r4 - 0x01006dfe: d1ef .. BNE 0x1006de0 ; show_wait_queue + 8 - 0x01006e00: bd70 p. POP {r4-r6,pc} - $d - 0x01006e02: 0000 .. DCW 0 - 0x01006e04: 732a2e25 %.*s DCD 1932144165 - 0x01006e08: 00000000 .... DCD 0 - 0x01006e0c: 0000002f /... DCD 47 - $t - i.skip_atoi - skip_atoi - 0x01006e10: 4601 .F MOV r1,r0 - 0x01006e12: 2000 . MOVS r0,#0 - 0x01006e14: e008 .. B 0x1006e28 ; skip_atoi + 24 - 0x01006e16: 680b .h LDR r3,[r1,#0] - 0x01006e18: 1c5a Z. ADDS r2,r3,#1 - 0x01006e1a: 600a .` STR r2,[r1,#0] - 0x01006e1c: 781b .x LDRB r3,[r3,#0] - 0x01006e1e: 220a ." MOVS r2,#0xa - 0x01006e20: 4342 BC MULS r2,r0,r2 - 0x01006e22: 189a .. ADDS r2,r3,r2 - 0x01006e24: 4610 .F MOV r0,r2 - 0x01006e26: 3830 08 SUBS r0,r0,#0x30 - 0x01006e28: 680a .h LDR r2,[r1,#0] - 0x01006e2a: 7812 .x LDRB r2,[r2,#0] - 0x01006e2c: 3a30 0: SUBS r2,r2,#0x30 - 0x01006e2e: 2a0a .* CMP r2,#0xa - 0x01006e30: d3f1 .. BCC 0x1006e16 ; skip_atoi + 6 - 0x01006e32: 4770 pG BX lr - i.str_common - str_common - 0x01006e34: b510 .. PUSH {r4,lr} - 0x01006e36: 4603 .F MOV r3,r0 - 0x01006e38: 461a .F MOV r2,r3 - 0x01006e3a: e001 .. B 0x1006e40 ; str_common + 12 - 0x01006e3c: 1c52 R. ADDS r2,r2,#1 - 0x01006e3e: 1c49 I. ADDS r1,r1,#1 - 0x01006e40: 7810 .x LDRB r0,[r2,#0] - 0x01006e42: 2800 .( CMP r0,#0 - 0x01006e44: d006 .. BEQ 0x1006e54 ; str_common + 32 - 0x01006e46: 7808 .x LDRB r0,[r1,#0] - 0x01006e48: 2800 .( CMP r0,#0 - 0x01006e4a: d003 .. BEQ 0x1006e54 ; str_common + 32 - 0x01006e4c: 7810 .x LDRB r0,[r2,#0] - 0x01006e4e: 780c .x LDRB r4,[r1,#0] - 0x01006e50: 42a0 .B CMP r0,r4 - 0x01006e52: d0f3 .. BEQ 0x1006e3c ; str_common + 8 - 0x01006e54: 1ad0 .. SUBS r0,r2,r3 - 0x01006e56: bd10 .. POP {r4,pc} - i.version - version - 0x01006e58: b510 .. PUSH {r4,lr} - 0x01006e5a: f7fefdef .... BL rt_show_version ; 0x1005a3c - 0x01006e5e: 2000 . MOVS r0,#0 - 0x01006e60: bd10 .. POP {r4,pc} - 0x01006e62: 0000 .. MOVS r0,r0 - i.yc3121_uart_configure - yc3121_uart_configure - 0x01006e64: b57f .. PUSH {r0-r6,lr} - 0x01006e66: 4605 .F MOV r5,r0 - 0x01006e68: 460c .F MOV r4,r1 - 0x01006e6a: 2d00 .- CMP r5,#0 - 0x01006e6c: d104 .. BNE 0x1006e78 ; yc3121_uart_configure + 20 - 0x01006e6e: 221a ." MOVS r2,#0x1a - 0x01006e70: 4926 &I LDR r1,[pc,#152] ; [0x1006f0c] = 0x1007434 - 0x01006e72: a027 '. ADR r0,{pc}+0x9e ; 0x1006f10 - 0x01006e74: f7fcfbc4 .... BL rt_assert_handler ; 0x1003600 - 0x01006e78: 2c00 ., CMP r4,#0 - 0x01006e7a: d104 .. BNE 0x1006e86 ; yc3121_uart_configure + 34 - 0x01006e7c: 221b ." MOVS r2,#0x1b - 0x01006e7e: 4923 #I LDR r1,[pc,#140] ; [0x1006f0c] = 0x1007434 - 0x01006e80: a028 (. ADR r0,{pc}+0xa4 ; 0x1006f24 - 0x01006e82: f7fcfbbd .... BL rt_assert_handler ; 0x1003600 - 0x01006e86: 6bee .k LDR r6,[r5,#0x3c] - 0x01006e88: 2001 . MOVS r0,#1 - 0x01006e8a: 5630 0V LDRSB r0,[r6,r0] - 0x01006e8c: f7f9fe02 .... BL NVIC_DisableIRQ ; 0x1000a94 - 0x01006e90: 6820 h LDR r0,[r4,#0] - 0x01006e92: 9001 .. STR r0,[sp,#4] - 0x01006e94: 2100 .! MOVS r1,#0 - 0x01006e96: 4668 hF MOV r0,sp - 0x01006e98: 72c1 .r STRB r1,[r0,#0xb] - 0x01006e9a: 7001 .p STRB r1,[r0,#0] - 0x01006e9c: 7920 y LDRB r0,[r4,#4] - 0x01006e9e: 0700 .. LSLS r0,r0,#28 - 0x01006ea0: 0f00 .. LSRS r0,r0,#28 - 0x01006ea2: 2809 .( CMP r0,#9 - 0x01006ea4: d103 .. BNE 0x1006eae ; yc3121_uart_configure + 74 - 0x01006ea6: 2004 . MOVS r0,#4 - 0x01006ea8: 4669 iF MOV r1,sp - 0x01006eaa: 7208 .r STRB r0,[r1,#8] - 0x01006eac: e003 .. B 0x1006eb6 ; yc3121_uart_configure + 82 - 0x01006eae: 2000 . MOVS r0,#0 - 0x01006eb0: 4669 iF MOV r1,sp - 0x01006eb2: 7208 .r STRB r0,[r1,#8] - 0x01006eb4: bf00 .. NOP - 0x01006eb6: bf00 .. NOP - 0x01006eb8: 7920 y LDRB r0,[r4,#4] - 0x01006eba: 0680 .. LSLS r0,r0,#26 - 0x01006ebc: 0f80 .. LSRS r0,r0,#30 - 0x01006ebe: 2801 .( CMP r0,#1 - 0x01006ec0: d103 .. BNE 0x1006eca ; yc3121_uart_configure + 102 - 0x01006ec2: 2008 . MOVS r0,#8 - 0x01006ec4: 4669 iF MOV r1,sp - 0x01006ec6: 7248 Hr STRB r0,[r1,#9] - 0x01006ec8: e003 .. B 0x1006ed2 ; yc3121_uart_configure + 110 - 0x01006eca: 2000 . MOVS r0,#0 - 0x01006ecc: 4669 iF MOV r1,sp - 0x01006ece: 7248 Hr STRB r0,[r1,#9] - 0x01006ed0: bf00 .. NOP - 0x01006ed2: bf00 .. NOP - 0x01006ed4: 7920 y LDRB r0,[r4,#4] - 0x01006ed6: 0600 .. LSLS r0,r0,#24 - 0x01006ed8: 0f80 .. LSRS r0,r0,#30 - 0x01006eda: 2801 .( CMP r0,#1 - 0x01006edc: d002 .. BEQ 0x1006ee4 ; yc3121_uart_configure + 128 - 0x01006ede: 2802 .( CMP r0,#2 - 0x01006ee0: d108 .. BNE 0x1006ef4 ; yc3121_uart_configure + 144 - 0x01006ee2: e003 .. B 0x1006eec ; yc3121_uart_configure + 136 - 0x01006ee4: 2002 . MOVS r0,#2 - 0x01006ee6: 4669 iF MOV r1,sp - 0x01006ee8: 7288 .r STRB r0,[r1,#0xa] - 0x01006eea: e007 .. B 0x1006efc ; yc3121_uart_configure + 152 - 0x01006eec: 2000 . MOVS r0,#0 - 0x01006eee: 4669 iF MOV r1,sp - 0x01006ef0: 7288 .r STRB r0,[r1,#0xa] - 0x01006ef2: e003 .. B 0x1006efc ; yc3121_uart_configure + 152 - 0x01006ef4: 2000 . MOVS r0,#0 - 0x01006ef6: 4669 iF MOV r1,sp - 0x01006ef8: 7288 .r STRB r0,[r1,#0xa] - 0x01006efa: bf00 .. NOP - 0x01006efc: bf00 .. NOP - 0x01006efe: 7830 0x LDRB r0,[r6,#0] - 0x01006f00: 4669 iF MOV r1,sp - 0x01006f02: f7f9fecf .... BL UART_Init ; 0x1000ca4 - 0x01006f06: 2000 . MOVS r0,#0 - 0x01006f08: b004 .. ADD sp,sp,#0x10 - 0x01006f0a: bd70 p. POP {r4-r6,pc} - $d - 0x01006f0c: 01007434 4t.. DCD 16806964 - 0x01006f10: 69726573 seri DCD 1769104755 - 0x01006f14: 21206c61 al ! DCD 555773025 - 0x01006f18: 5452203d = RT DCD 1414668349 - 0x01006f1c: 4c554e5f _NUL DCD 1280659039 - 0x01006f20: 0000004c L... DCD 76 - 0x01006f24: 20676663 cfg DCD 543647331 - 0x01006f28: 52203d21 != R DCD 1377844513 - 0x01006f2c: 554e5f54 T_NU DCD 1431199572 - 0x01006f30: 00004c4c LL.. DCD 19532 - $t - i.yc3121_uart_control - yc3121_uart_control - 0x01006f34: b5f8 .. PUSH {r3-r7,lr} - 0x01006f36: 4605 .F MOV r5,r0 - 0x01006f38: 460e .F MOV r6,r1 - 0x01006f3a: 4617 .F MOV r7,r2 - 0x01006f3c: 2d00 .- CMP r5,#0 - 0x01006f3e: d104 .. BNE 0x1006f4a ; yc3121_uart_control + 22 - 0x01006f40: 2248 H" MOVS r2,#0x48 - 0x01006f42: 4911 .I LDR r1,[pc,#68] ; [0x1006f88] = 0x100744a - 0x01006f44: a011 .. ADR r0,{pc}+0x48 ; 0x1006f8c - 0x01006f46: f7fcfb5b ..[. BL rt_assert_handler ; 0x1003600 - 0x01006f4a: 6bec .k LDR r4,[r5,#0x3c] - 0x01006f4c: 2e10 .. CMP r6,#0x10 - 0x01006f4e: d00a .. BEQ 0x1006f66 ; yc3121_uart_control + 50 - 0x01006f50: 2e11 .. CMP r6,#0x11 - 0x01006f52: d116 .. BNE 0x1006f82 ; yc3121_uart_control + 78 - 0x01006f54: 7820 x LDRB r0,[r4,#0] - 0x01006f56: 2100 .! MOVS r1,#0 - 0x01006f58: f7faf804 .... BL UART_SetRxITNum ; 0x1000f64 - 0x01006f5c: 2001 . MOVS r0,#1 - 0x01006f5e: 5620 V LDRSB r0,[r4,r0] - 0x01006f60: f7f9fd98 .... BL NVIC_DisableIRQ ; 0x1000a94 - 0x01006f64: e00d .. B 0x1006f82 ; yc3121_uart_control + 78 - 0x01006f66: 7820 x LDRB r0,[r4,#0] - 0x01006f68: 2101 .! MOVS r1,#1 - 0x01006f6a: f7f9fffb .... BL UART_SetRxITNum ; 0x1000f64 - 0x01006f6e: 7820 x LDRB r0,[r4,#0] - 0x01006f70: 2201 ." MOVS r2,#1 - 0x01006f72: 2102 .! MOVS r1,#2 - 0x01006f74: f7f9fe22 ..". BL UART_ITConfig ; 0x1000bbc - 0x01006f78: 2001 . MOVS r0,#1 - 0x01006f7a: 5620 V LDRSB r0,[r4,r0] - 0x01006f7c: f7f9fd94 .... BL NVIC_EnableIRQ ; 0x1000aa8 - 0x01006f80: bf00 .. NOP - 0x01006f82: bf00 .. NOP - 0x01006f84: 2000 . MOVS r0,#0 - 0x01006f86: bdf8 .. POP {r3-r7,pc} - $d - 0x01006f88: 0100744a Jt.. DCD 16806986 - 0x01006f8c: 69726573 seri DCD 1769104755 - 0x01006f90: 21206c61 al ! DCD 555773025 - 0x01006f94: 5452203d = RT DCD 1414668349 - 0x01006f98: 4c554e5f _NUL DCD 1280659039 - 0x01006f9c: 0000004c L... DCD 76 - $t - i.yc3121_uart_getc - yc3121_uart_getc - 0x01006fa0: b570 p. PUSH {r4-r6,lr} - 0x01006fa2: 4604 .F MOV r4,r0 - 0x01006fa4: 2c00 ., CMP r4,#0 - 0x01006fa6: d104 .. BNE 0x1006fb2 ; yc3121_uart_getc + 18 - 0x01006fa8: 2269 i" MOVS r2,#0x69 - 0x01006faa: 4909 .I LDR r1,[pc,#36] ; [0x1006fd0] = 0x100746f - 0x01006fac: a009 .. ADR r0,{pc}+0x28 ; 0x1006fd4 - 0x01006fae: f7fcfb27 ..'. BL rt_assert_handler ; 0x1003600 - 0x01006fb2: 6be5 .k LDR r5,[r4,#0x3c] - 0x01006fb4: 2600 .& MOVS r6,#0 - 0x01006fb6: 43f6 .C MVNS r6,r6 - 0x01006fb8: 7828 (x LDRB r0,[r5,#0] - 0x01006fba: f7f9ff79 ..y. BL UART_ReceiveDataLen ; 0x1000eb0 - 0x01006fbe: 2800 .( CMP r0,#0 - 0x01006fc0: d003 .. BEQ 0x1006fca ; yc3121_uart_getc + 42 - 0x01006fc2: 7828 (x LDRB r0,[r5,#0] - 0x01006fc4: f7f9ff4e ..N. BL UART_ReceiveData ; 0x1000e64 - 0x01006fc8: 4606 .F MOV r6,r0 - 0x01006fca: 4630 0F MOV r0,r6 - 0x01006fcc: bd70 p. POP {r4-r6,pc} - $d - 0x01006fce: 0000 .. DCW 0 - 0x01006fd0: 0100746f ot.. DCD 16807023 - 0x01006fd4: 69726573 seri DCD 1769104755 - 0x01006fd8: 21206c61 al ! DCD 555773025 - 0x01006fdc: 5452203d = RT DCD 1414668349 - 0x01006fe0: 4c554e5f _NUL DCD 1280659039 - 0x01006fe4: 0000004c L... DCD 76 - $t - i.yc3121_uart_putc - yc3121_uart_putc - 0x01006fe8: b570 p. PUSH {r4-r6,lr} - 0x01006fea: 4604 .F MOV r4,r0 - 0x01006fec: 460e .F MOV r6,r1 - 0x01006fee: 2c00 ., CMP r4,#0 - 0x01006ff0: d104 .. BNE 0x1006ffc ; yc3121_uart_putc + 20 - 0x01006ff2: 225e ^" MOVS r2,#0x5e - 0x01006ff4: 4908 .I LDR r1,[pc,#32] ; [0x1007018] = 0x100745e - 0x01006ff6: a009 .. ADR r0,{pc}+0x26 ; 0x100701c - 0x01006ff8: f7fcfb02 .... BL rt_assert_handler ; 0x1003600 - 0x01006ffc: 6be5 .k LDR r5,[r4,#0x3c] - 0x01006ffe: bf00 .. NOP - 0x01007000: 7828 (x LDRB r0,[r5,#0] - 0x01007002: f7f9ff01 .... BL UART_IsUARTBusy ; 0x1000e08 - 0x01007006: 2800 .( CMP r0,#0 - 0x01007008: d1fa .. BNE 0x1007000 ; yc3121_uart_putc + 24 - 0x0100700a: 7828 (x LDRB r0,[r5,#0] - 0x0100700c: 4631 1F MOV r1,r6 - 0x0100700e: f7f9ff77 ..w. BL UART_SendData ; 0x1000f00 - 0x01007012: 2001 . MOVS r0,#1 - 0x01007014: bd70 p. POP {r4-r6,pc} - $d - 0x01007016: 0000 .. DCW 0 - 0x01007018: 0100745e ^t.. DCD 16807006 - 0x0100701c: 69726573 seri DCD 1769104755 - 0x01007020: 21206c61 al ! DCD 555773025 - 0x01007024: 5452203d = RT DCD 1414668349 - 0x01007028: 4c554e5f _NUL DCD 1280659039 - 0x0100702c: 0000004c L... DCD 76 - $t - i.yc_pin_attach_irq - yc_pin_attach_irq - 0x01007030: b5f8 .. PUSH {r3-r7,lr} - 0x01007032: 4615 .F MOV r5,r2 - 0x01007034: 461e .F MOV r6,r3 - 0x01007036: 9f06 .. LDR r7,[sp,#0x18] - 0x01007038: 2c00 ., CMP r4,#0 - 0x0100703a: d101 .. BNE 0x1007040 ; yc_pin_attach_irq + 16 - 0x0100703c: 200a . MOVS r0,#0xa - 0x0100703e: bdf8 .. POP {r3-r7,pc} - 0x01007040: f7f9fa3e ..>. BL rt_hw_interrupt_disable ; 0x10004c0 - 0x01007044: 9000 .. STR r0,[sp,#0] - 0x01007046: 6126 &a STR r6,[r4,#0x10] - 0x01007048: 6167 ga STR r7,[r4,#0x14] - 0x0100704a: 60e5 .` STR r5,[r4,#0xc] - 0x0100704c: 9800 .. LDR r0,[sp,#0] - 0x0100704e: f7f9fa3b ..;. BL rt_hw_interrupt_enable ; 0x10004c8 - 0x01007052: 2000 . MOVS r0,#0 - 0x01007054: e7f3 .. B 0x100703e ; yc_pin_attach_irq + 14 - i.yc_pin_detach_irq - yc_pin_detach_irq - 0x01007056: b5e0 .. PUSH {r5-r7,lr} - 0x01007058: 4606 .F MOV r6,r0 - 0x0100705a: 460f .F MOV r7,r1 - 0x0100705c: 2c00 ., CMP r4,#0 - 0x0100705e: d101 .. BNE 0x1007064 ; yc_pin_detach_irq + 14 - 0x01007060: 200a . MOVS r0,#0xa - 0x01007062: bde0 .. POP {r5-r7,pc} - 0x01007064: f7f9fa2c ..,. BL rt_hw_interrupt_disable ; 0x10004c0 - 0x01007068: 4605 .F MOV r5,r0 - 0x0100706a: 2000 . MOVS r0,#0 - 0x0100706c: 6120 a STR r0,[r4,#0x10] - 0x0100706e: 6160 `a STR r0,[r4,#0x14] - 0x01007070: 60e0 .` STR r0,[r4,#0xc] - 0x01007072: 4628 (F MOV r0,r5 - 0x01007074: f7f9fa28 ..(. BL rt_hw_interrupt_enable ; 0x10004c8 - 0x01007078: 2000 . MOVS r0,#0 - 0x0100707a: e7f2 .. B 0x1007062 ; yc_pin_detach_irq + 12 - i.yc_pin_irq_enable - yc_pin_irq_enable - 0x0100707c: b5f8 .. PUSH {r3-r7,lr} - 0x0100707e: 460c .F MOV r4,r1 - 0x01007080: 4616 .F MOV r6,r2 - 0x01007082: 2000 . MOVS r0,#0 - 0x01007084: 9000 .. STR r0,[sp,#0] - 0x01007086: 2d00 .- CMP r5,#0 - 0x01007088: d101 .. BNE 0x100708e ; yc_pin_irq_enable + 18 - 0x0100708a: 200a . MOVS r0,#0xa - 0x0100708c: bdf8 .. POP {r3-r7,pc} - 0x0100708e: 2e01 .. CMP r6,#1 - 0x01007090: d177 w. BNE 0x1007182 ; yc_pin_irq_enable + 262 - 0x01007092: 68e8 .h LDR r0,[r5,#0xc] - 0x01007094: 0003 .. MOVS r3,r0 - 0x01007096: f7f9ff9d .... BL __ARM_common_switch8 ; 0x1000fd4 - $d - 0x0100709a: 0405 .. DCW 1029 - 0x0100709c: 27070605 ...' DCD 654771717 - 0x010070a0: 0047 G. DCW 71 - $t - 0x010070a2: e046 F. B 0x1007132 ; yc_pin_irq_enable + 182 - 0x010070a4: e045 E. B 0x1007132 ; yc_pin_irq_enable + 182 - 0x010070a6: e044 D. B 0x1007132 ; yc_pin_irq_enable + 182 - 0x010070a8: 2080 . MOVS r0,#0x80 - 0x010070aa: 4949 II LDR r1,[pc,#292] ; [0x10071d0] = 0xf8700 - 0x010070ac: 1861 a. ADDS r1,r4,r1 - 0x010070ae: 7008 .p STRB r0,[r1,#0] - 0x010070b0: 4620 F MOV r0,r4 - 0x010070b2: 17e2 .. ASRS r2,r4,#31 - 0x010070b4: 0f12 .. LSRS r2,r2,#28 - 0x010070b6: 1812 .. ADDS r2,r2,r0 - 0x010070b8: 1112 .. ASRS r2,r2,#4 - 0x010070ba: 0052 R. LSLS r2,r2,#1 - 0x010070bc: 4b44 DK LDR r3,[pc,#272] ; [0x10071d0] = 0xf8700 - 0x010070be: 18d2 .. ADDS r2,r2,r3 - 0x010070c0: 8ed2 .. LDRH r2,[r2,#0x36] - 0x010070c2: 4621 !F MOV r1,r4 - 0x010070c4: 17e3 .. ASRS r3,r4,#31 - 0x010070c6: 0f1b .. LSRS r3,r3,#28 - 0x010070c8: 185b [. ADDS r3,r3,r1 - 0x010070ca: 111b .. ASRS r3,r3,#4 - 0x010070cc: 011b .. LSLS r3,r3,#4 - 0x010070ce: 1ae7 .. SUBS r7,r4,r3 - 0x010070d0: 2301 .# MOVS r3,#1 - 0x010070d2: 40bb .@ LSLS r3,r3,r7 - 0x010070d4: 401a .@ ANDS r2,r2,r3 - 0x010070d6: 17e3 .. ASRS r3,r4,#31 - 0x010070d8: 0f1b .. LSRS r3,r3,#28 - 0x010070da: 181b .. ADDS r3,r3,r0 - 0x010070dc: 111b .. ASRS r3,r3,#4 - 0x010070de: 005b [. LSLS r3,r3,#1 - 0x010070e0: 4f3b ;O LDR r7,[pc,#236] ; [0x10071d0] = 0xf8700 - 0x010070e2: 19db .. ADDS r3,r3,r7 - 0x010070e4: 86da .. STRH r2,[r3,#0x36] - 0x010070e6: e024 $. B 0x1007132 ; yc_pin_irq_enable + 182 - 0x010070e8: 2040 @ MOVS r0,#0x40 - 0x010070ea: 4939 9I LDR r1,[pc,#228] ; [0x10071d0] = 0xf8700 - 0x010070ec: 1861 a. ADDS r1,r4,r1 - 0x010070ee: 7008 .p STRB r0,[r1,#0] - 0x010070f0: 4620 F MOV r0,r4 - 0x010070f2: 17e2 .. ASRS r2,r4,#31 - 0x010070f4: 0f12 .. LSRS r2,r2,#28 - 0x010070f6: 1812 .. ADDS r2,r2,r0 - 0x010070f8: 1112 .. ASRS r2,r2,#4 - 0x010070fa: 0052 R. LSLS r2,r2,#1 - 0x010070fc: 4b34 4K LDR r3,[pc,#208] ; [0x10071d0] = 0xf8700 - 0x010070fe: 18d2 .. ADDS r2,r2,r3 - 0x01007100: 8ed2 .. LDRH r2,[r2,#0x36] - 0x01007102: 4621 !F MOV r1,r4 - 0x01007104: 17e3 .. ASRS r3,r4,#31 - 0x01007106: 0f1b .. LSRS r3,r3,#28 - 0x01007108: 185b [. ADDS r3,r3,r1 - 0x0100710a: 111b .. ASRS r3,r3,#4 - 0x0100710c: 011b .. LSLS r3,r3,#4 - 0x0100710e: 1ae7 .. SUBS r7,r4,r3 - 0x01007110: 2301 .# MOVS r3,#1 - 0x01007112: 40bb .@ LSLS r3,r3,r7 - 0x01007114: 431a .C ORRS r2,r2,r3 - 0x01007116: 17e3 .. ASRS r3,r4,#31 - 0x01007118: 0f1b .. LSRS r3,r3,#28 - 0x0100711a: 181b .. ADDS r3,r3,r0 - 0x0100711c: 111b .. ASRS r3,r3,#4 - 0x0100711e: 005b [. LSLS r3,r3,#1 - 0x01007120: 4f2b +O LDR r7,[pc,#172] ; [0x10071d0] = 0xf8700 - 0x01007122: 19db .. ADDS r3,r3,r7 - 0x01007124: 86da .. STRH r2,[r3,#0x36] - 0x01007126: e004 .. B 0x1007132 ; yc_pin_irq_enable + 182 - 0x01007128: 9800 .. LDR r0,[sp,#0] - 0x0100712a: f7f9f9cd .... BL rt_hw_interrupt_enable ; 0x10004c8 - 0x0100712e: 200a . MOVS r0,#0xa - 0x01007130: e7ac .. B 0x100708c ; yc_pin_irq_enable + 16 - 0x01007132: bf00 .. NOP - 0x01007134: f7f9f9c4 .... BL rt_hw_interrupt_disable ; 0x10004c0 - 0x01007138: 9000 .. STR r0,[sp,#0] - 0x0100713a: 2008 . MOVS r0,#8 - 0x0100713c: 5628 (V LDRSB r0,[r5,r0] - 0x0100713e: f7f9fcb3 .... BL NVIC_EnableIRQ ; 0x1000aa8 - 0x01007142: 4620 F MOV r0,r4 - 0x01007144: 17e2 .. ASRS r2,r4,#31 - 0x01007146: 0f12 .. LSRS r2,r2,#28 - 0x01007148: 1812 .. ADDS r2,r2,r0 - 0x0100714a: 1112 .. ASRS r2,r2,#4 - 0x0100714c: 0052 R. LSLS r2,r2,#1 - 0x0100714e: 4b20 K LDR r3,[pc,#128] ; [0x10071d0] = 0xf8700 - 0x01007150: 18d2 .. ADDS r2,r2,r3 - 0x01007152: 8e12 .. LDRH r2,[r2,#0x30] - 0x01007154: 4621 !F MOV r1,r4 - 0x01007156: 17e3 .. ASRS r3,r4,#31 - 0x01007158: 0f1b .. LSRS r3,r3,#28 - 0x0100715a: 185b [. ADDS r3,r3,r1 - 0x0100715c: 111b .. ASRS r3,r3,#4 - 0x0100715e: 011b .. LSLS r3,r3,#4 - 0x01007160: 1ae7 .. SUBS r7,r4,r3 - 0x01007162: 2301 .# MOVS r3,#1 - 0x01007164: 40bb .@ LSLS r3,r3,r7 - 0x01007166: 431a .C ORRS r2,r2,r3 - 0x01007168: 17e3 .. ASRS r3,r4,#31 - 0x0100716a: 0f1b .. LSRS r3,r3,#28 - 0x0100716c: 181b .. ADDS r3,r3,r0 - 0x0100716e: 111b .. ASRS r3,r3,#4 - 0x01007170: 005b [. LSLS r3,r3,#1 - 0x01007172: 4f17 .O LDR r7,[pc,#92] ; [0x10071d0] = 0xf8700 - 0x01007174: 19db .. ADDS r3,r3,r7 - 0x01007176: 861a .. STRH r2,[r3,#0x30] - 0x01007178: 9800 .. LDR r0,[sp,#0] - 0x0100717a: f7f9f9a5 .... BL rt_hw_interrupt_enable ; 0x10004c8 - 0x0100717e: e024 $. B 0x10071ca ; yc_pin_irq_enable + 334 - 0x01007180: e7ff .. B 0x1007182 ; yc_pin_irq_enable + 262 - 0x01007182: 2e00 .. CMP r6,#0 - 0x01007184: d11f .. BNE 0x10071c6 ; yc_pin_irq_enable + 330 - 0x01007186: 2008 . MOVS r0,#8 - 0x01007188: 5628 (V LDRSB r0,[r5,r0] - 0x0100718a: f7f9fc83 .... BL NVIC_DisableIRQ ; 0x1000a94 - 0x0100718e: 4620 F MOV r0,r4 - 0x01007190: 17e2 .. ASRS r2,r4,#31 - 0x01007192: 0f12 .. LSRS r2,r2,#28 - 0x01007194: 1812 .. ADDS r2,r2,r0 - 0x01007196: 1112 .. ASRS r2,r2,#4 - 0x01007198: 0052 R. LSLS r2,r2,#1 - 0x0100719a: 4b0d .K LDR r3,[pc,#52] ; [0x10071d0] = 0xf8700 - 0x0100719c: 18d2 .. ADDS r2,r2,r3 - 0x0100719e: 8e12 .. LDRH r2,[r2,#0x30] - 0x010071a0: 4621 !F MOV r1,r4 - 0x010071a2: 17e3 .. ASRS r3,r4,#31 - 0x010071a4: 0f1b .. LSRS r3,r3,#28 - 0x010071a6: 185b [. ADDS r3,r3,r1 - 0x010071a8: 111b .. ASRS r3,r3,#4 - 0x010071aa: 011b .. LSLS r3,r3,#4 - 0x010071ac: 1ae7 .. SUBS r7,r4,r3 - 0x010071ae: 2301 .# MOVS r3,#1 - 0x010071b0: 40bb .@ LSLS r3,r3,r7 - 0x010071b2: 439a .C BICS r2,r2,r3 - 0x010071b4: 17e3 .. ASRS r3,r4,#31 - 0x010071b6: 0f1b .. LSRS r3,r3,#28 - 0x010071b8: 181b .. ADDS r3,r3,r0 - 0x010071ba: 111b .. ASRS r3,r3,#4 - 0x010071bc: 005b [. LSLS r3,r3,#1 - 0x010071be: 4f04 .O LDR r7,[pc,#16] ; [0x10071d0] = 0xf8700 - 0x010071c0: 19db .. ADDS r3,r3,r7 - 0x010071c2: 861a .. STRH r2,[r3,#0x30] - 0x010071c4: e001 .. B 0x10071ca ; yc_pin_irq_enable + 334 - 0x010071c6: 2006 . MOVS r0,#6 - 0x010071c8: e760 `. B 0x100708c ; yc_pin_irq_enable + 16 - 0x010071ca: 2000 . MOVS r0,#0 - 0x010071cc: e75e ^. B 0x100708c ; yc_pin_irq_enable + 16 - $d - 0x010071ce: 0000 .. DCW 0 - 0x010071d0: 000f8700 .... DCD 1017600 - $t - i.yc_pin_mode - yc_pin_mode - 0x010071d4: b510 .. PUSH {r4,lr} - 0x010071d6: 2a00 .* CMP r2,#0 - 0x010071d8: d104 .. BNE 0x10071e4 ; yc_pin_mode + 16 - 0x010071da: 233e ># MOVS r3,#0x3e - 0x010071dc: 4c0f .L LDR r4,[pc,#60] ; [0x100721c] = 0xf8700 - 0x010071de: 190c .. ADDS r4,r1,r4 - 0x010071e0: 7023 #p STRB r3,[r4,#0] - 0x010071e2: e01a .. B 0x100721a ; yc_pin_mode + 70 - 0x010071e4: 2a01 .* CMP r2,#1 - 0x010071e6: d104 .. BNE 0x10071f2 ; yc_pin_mode + 30 - 0x010071e8: 2300 .# MOVS r3,#0 - 0x010071ea: 4c0c .L LDR r4,[pc,#48] ; [0x100721c] = 0xf8700 - 0x010071ec: 190c .. ADDS r4,r1,r4 - 0x010071ee: 7023 #p STRB r3,[r4,#0] - 0x010071f0: e013 .. B 0x100721a ; yc_pin_mode + 70 - 0x010071f2: 2a02 .* CMP r2,#2 - 0x010071f4: d104 .. BNE 0x1007200 ; yc_pin_mode + 44 - 0x010071f6: 2340 @# MOVS r3,#0x40 - 0x010071f8: 4c08 .L LDR r4,[pc,#32] ; [0x100721c] = 0xf8700 - 0x010071fa: 190c .. ADDS r4,r1,r4 - 0x010071fc: 7023 #p STRB r3,[r4,#0] - 0x010071fe: e00c .. B 0x100721a ; yc_pin_mode + 70 - 0x01007200: 2a03 .* CMP r2,#3 - 0x01007202: d104 .. BNE 0x100720e ; yc_pin_mode + 58 - 0x01007204: 2380 .# MOVS r3,#0x80 - 0x01007206: 4c05 .L LDR r4,[pc,#20] ; [0x100721c] = 0xf8700 - 0x01007208: 190c .. ADDS r4,r1,r4 - 0x0100720a: 7023 #p STRB r3,[r4,#0] - 0x0100720c: e005 .. B 0x100721a ; yc_pin_mode + 70 - 0x0100720e: 2a04 .* CMP r2,#4 - 0x01007210: d103 .. BNE 0x100721a ; yc_pin_mode + 70 - 0x01007212: 2340 @# MOVS r3,#0x40 - 0x01007214: 4c01 .L LDR r4,[pc,#4] ; [0x100721c] = 0xf8700 - 0x01007216: 190c .. ADDS r4,r1,r4 - 0x01007218: 7023 #p STRB r3,[r4,#0] - 0x0100721a: bd10 .. POP {r4,pc} - $d - 0x0100721c: 000f8700 .... DCD 1017600 - $t - i.yc_pin_read - yc_pin_read - 0x01007220: b570 p. PUSH {r4-r6,lr} - 0x01007222: 4604 .F MOV r4,r0 - 0x01007224: 460a .F MOV r2,r1 - 0x01007226: 17c8 .. ASRS r0,r1,#31 - 0x01007228: 0f00 .. LSRS r0,r0,#28 - 0x0100722a: 1880 .. ADDS r0,r0,r2 - 0x0100722c: 1100 .. ASRS r0,r0,#4 - 0x0100722e: 0040 @. LSLS r0,r0,#1 - 0x01007230: 4d09 .M LDR r5,[pc,#36] ; [0x1007258] = 0xf8700 - 0x01007232: 1940 @. ADDS r0,r0,r5 - 0x01007234: 8f80 .. LDRH r0,[r0,#0x3c] - 0x01007236: 460b .F MOV r3,r1 - 0x01007238: 17cd .. ASRS r5,r1,#31 - 0x0100723a: 0f2d -. LSRS r5,r5,#28 - 0x0100723c: 18ed .. ADDS r5,r5,r3 - 0x0100723e: 112d -. ASRS r5,r5,#4 - 0x01007240: 012d -. LSLS r5,r5,#4 - 0x01007242: 1b4e N. SUBS r6,r1,r5 - 0x01007244: 2501 .% MOVS r5,#1 - 0x01007246: 40b5 .@ LSLS r5,r5,r6 - 0x01007248: 4028 (@ ANDS r0,r0,r5 - 0x0100724a: 2800 .( CMP r0,#0 - 0x0100724c: d001 .. BEQ 0x1007252 ; yc_pin_read + 50 - 0x0100724e: 2001 . MOVS r0,#1 - 0x01007250: bd70 p. POP {r4-r6,pc} - 0x01007252: 2000 . MOVS r0,#0 - 0x01007254: e7fc .. B 0x1007250 ; yc_pin_read + 48 - $d - 0x01007256: 0000 .. DCW 0 - 0x01007258: 000f8700 .... DCD 1017600 - $t - i.yc_pin_write - yc_pin_write - 0x0100725c: b510 .. PUSH {r4,lr} - 0x0100725e: 2a00 .* CMP r2,#0 - 0x01007260: d004 .. BEQ 0x100726c ; yc_pin_write + 16 - 0x01007262: 233f ?# MOVS r3,#0x3f - 0x01007264: 4c04 .L LDR r4,[pc,#16] ; [0x1007278] = 0xf8700 - 0x01007266: 190c .. ADDS r4,r1,r4 - 0x01007268: 7023 #p STRB r3,[r4,#0] - 0x0100726a: e003 .. B 0x1007274 ; yc_pin_write + 24 - 0x0100726c: 233e ># MOVS r3,#0x3e - 0x0100726e: 4c02 .L LDR r4,[pc,#8] ; [0x1007278] = 0xf8700 - 0x01007270: 190c .. ADDS r4,r1,r4 - 0x01007272: 7023 #p STRB r3,[r4,#0] - 0x01007274: bd10 .. POP {r4,pc} - $d - 0x01007276: 0000 .. DCW 0 - 0x01007278: 000f8700 .... DCD 1017600 - $d.realdata - .constdata - __FUNCTION__ - 0x0100727c: 6e69705f _pin DCD 1852403807 - 0x01007280: 6165725f _rea DCD 1634038367 - 0x01007284: 0064 d. DCW 100 - __FUNCTION__ - 0x01007286: 705f _p DCW 28767 - 0x01007288: 775f6e69 in_w DCD 2002742889 - 0x0100728c: 65746972 rite DCD 1702127986 - 0x01007290: 00 . DCB 0 - __FUNCTION__ - 0x01007291: 5f7069 _pi DCB 95,112,105 - 0x01007294: 6f635f6e n_co DCD 1868783470 - 0x01007298: 6f72746e ntro DCD 1869771886 - 0x0100729c: 006c l. DCW 108 - __FUNCTION__ - 0x0100729e: 7472 rt DCW 29810 - 0x010072a0: 6e69705f _pin DCD 1852403807 - 0x010072a4: 7474615f _att DCD 1953784159 - 0x010072a8: 5f686361 ach_ DCD 1600676705 - 0x010072ac: 00717269 irq. DCD 7434857 - __FUNCTION__ - 0x010072b0: 705f7472 rt_p DCD 1885303922 - 0x010072b4: 645f6e69 in_d DCD 1683975785 - 0x010072b8: 63617465 etac DCD 1667331173 - 0x010072bc: 72695f68 h_ir DCD 1919508328 - 0x010072c0: 0071 q. DCW 113 - __FUNCTION__ - 0x010072c2: 7472 rt DCW 29810 - 0x010072c4: 6e69705f _pin DCD 1852403807 - 0x010072c8: 7172695f _irq DCD 1903323487 - 0x010072cc: 616e655f _ena DCD 1634624863 - 0x010072d0: 00656c62 ble. DCD 6646882 - __FUNCTION__ - 0x010072d4: 705f7472 rt_p DCD 1885303922 - 0x010072d8: 6d5f6e69 in_m DCD 1834970729 - 0x010072dc: 0065646f ode. DCD 6644847 - __FUNCTION__ - 0x010072e0: 705f7472 rt_p DCD 1885303922 - 0x010072e4: 775f6e69 in_w DCD 2002742889 - 0x010072e8: 65746972 rite DCD 1702127986 - 0x010072ec: 00 . DCB 0 - __FUNCTION__ - 0x010072ed: 72745f rt_ DCB 114,116,95 - 0x010072f0: 5f6e6970 pin_ DCD 1601071472 - 0x010072f4: 64616572 read DCD 1684104562 - 0x010072f8: 00 . DCB 0 - __FUNCTION__ - 0x010072f9: 72745f rt_ DCB 114,116,95 - 0x010072fc: 5f6e6970 pin_ DCD 1601071472 - 0x01007300: 00746567 get. DCD 7628135 - .constdata - __FUNCTION__ - 0x01007304: 7265735f _ser DCD 1919251295 - 0x01007308: 5f6c6169 ial_ DCD 1600938345 - 0x0100730c: 6c6c6f70 poll DCD 1819045744 - 0x01007310: 0078725f _rx. DCD 7893599 - __FUNCTION__ - 0x01007314: 7265735f _ser DCD 1919251295 - 0x01007318: 5f6c6169 ial_ DCD 1600938345 - 0x0100731c: 6c6c6f70 poll DCD 1819045744 - 0x01007320: 0078745f _tx. DCD 7894111 - __FUNCTION__ - 0x01007324: 7265735f _ser DCD 1919251295 - 0x01007328: 5f6c6169 ial_ DCD 1600938345 - 0x0100732c: 5f746e69 int_ DCD 1601465961 - 0x01007330: 7872 rx DCW 30834 - 0x01007332: 00 . DCB 0 - __FUNCTION__ - 0x01007333: 5f _ DCB 95 - 0x01007334: 69726573 seri DCD 1769104755 - 0x01007338: 695f6c61 al_i DCD 1767861345 - 0x0100733c: 745f746e nt_t DCD 1952412782 - 0x01007340: 0078 x. DCW 120 - __FUNCTION__ - 0x01007342: 7472 rt DCW 29810 - 0x01007344: 7265735f _ser DCD 1919251295 - 0x01007348: 5f6c6169 ial_ DCD 1600938345 - 0x0100734c: 74696e69 init DCD 1953066601 - 0x01007350: 00 . DCB 0 - __FUNCTION__ - 0x01007351: 72745f rt_ DCB 114,116,95 - 0x01007354: 69726573 seri DCD 1769104755 - 0x01007358: 6f5f6c61 al_o DCD 1868524641 - 0x0100735c: 006e6570 pen. DCD 7234928 - __FUNCTION__ - 0x01007360: 735f7472 rt_s DCD 1935635570 - 0x01007364: 61697265 eria DCD 1634300517 - 0x01007368: 6c635f6c l_cl DCD 1818451820 - 0x0100736c: 0065736f ose. DCD 6648687 - __FUNCTION__ - 0x01007370: 735f7472 rt_s DCD 1935635570 - 0x01007374: 61697265 eria DCD 1634300517 - 0x01007378: 65725f6c l_re DCD 1701994348 - 0x0100737c: 6461 ad DCW 25697 - 0x0100737e: 00 . DCB 0 - __FUNCTION__ - 0x0100737f: 72 r DCB 114 - 0x01007380: 65735f74 t_se DCD 1702059892 - 0x01007384: 6c616972 rial DCD 1818323314 - 0x01007388: 6972775f _wri DCD 1769109343 - 0x0100738c: 6574 te DCW 25972 - 0x0100738e: 00 . DCB 0 - __FUNCTION__ - 0x0100738f: 72 r DCB 114 - 0x01007390: 65735f74 t_se DCD 1702059892 - 0x01007394: 6c616972 rial DCD 1818323314 - 0x01007398: 6e6f635f _con DCD 1852793695 - 0x0100739c: 6c6f7274 trol DCD 1819243124 - 0x010073a0: 00 . DCB 0 - __FUNCTION__ - 0x010073a1: 72745f rt_ DCB 114,116,95 - 0x010073a4: 735f7768 hw_s DCD 1935636328 - 0x010073a8: 61697265 eria DCD 1634300517 - 0x010073ac: 65725f6c l_re DCD 1701994348 - 0x010073b0: 74736967 gist DCD 1953720679 - 0x010073b4: 7265 er DCW 29285 - 0x010073b6: 00 . DCB 0 - __FUNCTION__ - 0x010073b7: 72 r DCB 114 - 0x010073b8: 77685f74 t_hw DCD 2003328884 - 0x010073bc: 7265735f _ser DCD 1919251295 - 0x010073c0: 5f6c6169 ial_ DCD 1600938345 - 0x010073c4: 00727369 isr. DCD 7500649 - .constdata - __FUNCTION__ - 0x010073c8: 635f7472 rt_c DCD 1667200114 - 0x010073cc: 6c706d6f ompl DCD 1819307375 - 0x010073d0: 6f697465 etio DCD 1869182053 - 0x010073d4: 6e695f6e n_in DCD 1852399470 - 0x010073d8: 7469 it DCW 29801 - 0x010073da: 00 . DCB 0 - __FUNCTION__ - 0x010073db: 72 r DCB 114 - 0x010073dc: 6f635f74 t_co DCD 1868783476 - 0x010073e0: 656c706d mple DCD 1701605485 - 0x010073e4: 6e6f6974 tion DCD 1852795252 - 0x010073e8: 6961775f _wai DCD 1767995231 - 0x010073ec: 0074 t. DCW 116 - __FUNCTION__ - 0x010073ee: 7472 rt DCW 29810 - 0x010073f0: 6d6f635f _com DCD 1836016479 - 0x010073f4: 74656c70 plet DCD 1952803952 - 0x010073f8: 5f6e6f69 ion_ DCD 1601073001 - 0x010073fc: 656e6f64 done DCD 1701736292 - 0x01007400: 00000000 .... DCD 0 - .constdata - yc3121_pin_ops - 0x01007404: 010071d5 .q.. DCD 16806357 - 0x01007408: 0100725d ]r.. DCD 16806493 - 0x0100740c: 01007221 !r.. DCD 16806433 - 0x01007410: 01007031 1p.. DCD 16805937 - 0x01007414: 01007057 Wp.. DCD 16805975 - 0x01007418: 0100707d }p.. DCD 16806013 - 0x0100741c: 00000000 .... DCD 0 - .constdata - yc3121_uart_ops - 0x01007420: 01006e65 en.. DCD 16805477 - 0x01007424: 01006f35 5o.. DCD 16805685 - 0x01007428: 01006fe9 .o.. DCD 16805865 - 0x0100742c: 01006fa1 .o.. DCD 16805793 - 0x01007430: 00000000 .... DCD 0 - __FUNCTION__ - 0x01007434: 31336379 yc31 DCD 825451385 - 0x01007438: 755f3132 21_u DCD 1969172786 - 0x0100743c: 5f747261 art_ DCD 1601466977 - 0x01007440: 666e6f63 conf DCD 1718513507 - 0x01007444: 72756769 igur DCD 1920296809 - 0x01007448: 0065 e. DCW 101 - __FUNCTION__ - 0x0100744a: 6379 yc DCW 25465 - 0x0100744c: 31323133 3121 DCD 825372979 - 0x01007450: 7261755f _uar DCD 1918989663 - 0x01007454: 6f635f74 t_co DCD 1868783476 - 0x01007458: 6f72746e ntro DCD 1869771886 - 0x0100745c: 006c l. DCW 108 - __FUNCTION__ - 0x0100745e: 6379 yc DCW 25465 - 0x01007460: 31323133 3121 DCD 825372979 - 0x01007464: 7261755f _uar DCD 1918989663 - 0x01007468: 75705f74 t_pu DCD 1970298740 - 0x0100746c: 6374 tc DCW 25460 - 0x0100746e: 00 . DCB 0 - __FUNCTION__ - 0x0100746f: 79 y DCB 121 - 0x01007470: 32313363 c312 DCD 842085219 - 0x01007474: 61755f31 1_ua DCD 1635082033 - 0x01007478: 675f7472 rt_g DCD 1734308978 - 0x0100747c: 00637465 etc. DCD 6517861 - 0x01007480: 0001c200 .... DCD 115200 - 0x01007484: 00010008 .... DCD 65544 - .constdata - __FUNCTION__ - 0x01007488: 736e6966 fins DCD 1936615782 - 0x0100748c: 65675f68 h_ge DCD 1701273448 - 0x01007490: 72705f74 t_pr DCD 1919967092 - 0x01007494: 74706d6f ompt DCD 1953525103 - 0x01007498: 646f6d5f _mod DCD 1685024095 - 0x0100749c: 0065 e. DCW 101 - __FUNCTION__ - 0x0100749e: 6966 fi DCW 26982 - 0x010074a0: 5f68736e nsh_ DCD 1600680814 - 0x010074a4: 5f746573 set_ DCD 1601463667 - 0x010074a8: 6d6f7270 prom DCD 1836020336 - 0x010074ac: 6d5f7470 pt_m DCD 1834972272 - 0x010074b0: 0065646f ode. DCD 6644847 - __FUNCTION__ - 0x010074b4: 736e6966 fins DCD 1936615782 - 0x010074b8: 65675f68 h_ge DCD 1701273448 - 0x010074bc: 61686374 tcha DCD 1634231156 - 0x010074c0: 0072 r. DCW 114 - __FUNCTION__ - 0x010074c2: 6966 fi DCW 26982 - 0x010074c4: 5f68736e nsh_ DCD 1600680814 - 0x010074c8: 695f7872 rx_i DCD 1767864434 - 0x010074cc: 646e nd DCW 25710 - 0x010074ce: 00 . DCB 0 - __FUNCTION__ - 0x010074cf: 66 f DCB 102 - 0x010074d0: 68736e69 insh DCD 1752395369 - 0x010074d4: 7465735f _set DCD 1952805727 - 0x010074d8: 7665645f _dev DCD 1986356319 - 0x010074dc: 00656369 ice. DCD 6644585 - __FUNCTION__ - 0x010074e0: 736e6966 fins DCD 1936615782 - 0x010074e4: 65675f68 h_ge DCD 1701273448 - 0x010074e8: 65645f74 t_de DCD 1701076852 - 0x010074ec: 65636976 vice DCD 1701013878 - 0x010074f0: 00 . DCB 0 - __FUNCTION__ - 0x010074f1: 66696e fin DCB 102,105,110 - 0x010074f4: 735f6873 sh_s DCD 1935632499 - 0x010074f8: 655f7465 et_e DCD 1700754533 - 0x010074fc: 006f6863 cho. DCD 7301219 - __FUNCTION__ - 0x01007500: 736e6966 fins DCD 1936615782 - 0x01007504: 65675f68 h_ge DCD 1701273448 - 0x01007508: 63655f74 t_ec DCD 1667587956 - 0x0100750c: 6f68 ho DCW 28520 - 0x0100750e: 00 . DCB 0 - .constdata - __FUNCTION__ - 0x0100750f: 5f _ DCB 95 - 0x01007510: 5f68736d msh_ DCD 1600680813 - 0x01007514: 63657865 exec DCD 1667594341 - 0x01007518: 646d635f _cmd DCD 1684890463 - 0x0100751c: 00000000 .... DCD 0 - .constdata - device_type_str - 0x01007520: 01007e68 h~.. DCD 16809576 - 0x01007524: 01007e24 $~.. DCD 16809508 - 0x01007528: 01007da8 .}.. DCD 16809384 - 0x0100752c: 01007dbc .}.. DCD 16809404 - 0x01007530: 01007dd4 .}.. DCD 16809428 - 0x01007534: 01007da4 .}.. DCD 16809380 - 0x01007538: 01007df0 .}.. DCD 16809456 - 0x0100753c: 01007de0 .}.. DCD 16809440 - 0x01007540: 01007ed0 .~.. DCD 16809680 - 0x01007544: 01007e00 .~.. DCD 16809472 - 0x01007548: 01007ef8 .~.. DCD 16809720 - 0x0100754c: 01007ed8 .~.. DCD 16809688 - 0x01007550: 01007ee4 .~.. DCD 16809700 - 0x01007554: 01007dc8 .}.. DCD 16809416 - 0x01007558: 01007eec .~.. DCD 16809708 - 0x0100755c: 01007e44 D~.. DCD 16809540 - 0x01007560: 01007ec0 .~.. DCD 16809664 - 0x01007564: 01007e34 4~.. DCD 16809524 - 0x01007568: 01007e58 X~.. DCD 16809560 - 0x0100756c: 01007e8c .~.. DCD 16809612 - 0x01007570: 01007e7c |~.. DCD 16809596 - 0x01007574: 01007e14 .~.. DCD 16809492 - 0x01007578: 01007ea4 .~.. DCD 16809636 - 0x0100757c: 01007eb0 .~.. DCD 16809648 - 0x01007580: 01007ec8 .~.. DCD 16809672 - .constdata - __FUNCTION__ - 0x01007584: 615f7472 rt_a DCD 1633645682 - 0x01007588: 696c7070 ppli DCD 1768714352 - 0x0100758c: 69746163 cati DCD 1769234787 - 0x01007590: 695f6e6f on_i DCD 1767861871 - 0x01007594: 0074696e nit. DCD 7629166 - .constdata - __FUNCTION__ - 0x01007598: 5f74725f _rt_ DCD 1601466975 - 0x0100759c: 65686373 sche DCD 1701340019 - 0x010075a0: 656c7564 dule DCD 1701606756 - 0x010075a4: 74735f72 r_st DCD 1953718130 - 0x010075a8: 5f6b6361 ack_ DCD 1600873313 - 0x010075ac: 63656863 chec DCD 1667590243 - 0x010075b0: 006b k. DCW 107 - __FUNCTION__ - 0x010075b2: 7472 rt DCW 29810 - 0x010075b4: 6863735f _sch DCD 1751348063 - 0x010075b8: 6c756465 edul DCD 1819632741 - 0x010075bc: 6e695f65 e_in DCD 1852399461 - 0x010075c0: 74726573 sert DCD 1953654131 - 0x010075c4: 7268745f _thr DCD 1919448159 - 0x010075c8: 00646165 ead. DCD 6578533 - __FUNCTION__ - 0x010075cc: 735f7472 rt_s DCD 1935635570 - 0x010075d0: 64656863 ched DCD 1684367459 - 0x010075d4: 5f656c75 ule_ DCD 1600482421 - 0x010075d8: 6f6d6572 remo DCD 1869440370 - 0x010075dc: 745f6576 ve_t DCD 1952408950 - 0x010075e0: 61657268 hrea DCD 1634038376 - 0x010075e4: 0064 d. DCW 100 - .constdata - __FUNCTION__ - 0x010075e6: 7472 rt DCW 29810 - 0x010075e8: 6665645f _def DCD 1717920863 - 0x010075ec: 74636e75 unct DCD 1952673397 - 0x010075f0: 6578655f _exe DCD 1702389087 - 0x010075f4: 65747563 cute DCD 1702131043 - 0x010075f8: 00 . DCB 0 - .constdata - __FUNCTION__ - 0x010075f9: 72745f rt_ DCB 114,116,95 - 0x010075fc: 69766564 devi DCD 1769366884 - 0x01007600: 755f6563 ce_u DCD 1969186147 - 0x01007604: 6765726e nreg DCD 1734701678 - 0x01007608: 65747369 iste DCD 1702130537 - 0x0100760c: 0072 r. DCW 114 - __FUNCTION__ - 0x0100760e: 7472 rt DCW 29810 - 0x01007610: 7665645f _dev DCD 1986356319 - 0x01007614: 5f656369 ice_ DCD 1600480105 - 0x01007618: 74736564 dest DCD 1953719652 - 0x0100761c: 00796f72 roy. DCD 7958386 - __FUNCTION__ - 0x01007620: 645f7472 rt_d DCD 1683977330 - 0x01007624: 63697665 evic DCD 1667855973 - 0x01007628: 6e695f65 e_in DCD 1852399461 - 0x0100762c: 7469 it DCW 29801 - 0x0100762e: 00 . DCB 0 - __FUNCTION__ - 0x0100762f: 72 r DCB 114 - 0x01007630: 65645f74 t_de DCD 1701076852 - 0x01007634: 65636976 vice DCD 1701013878 - 0x01007638: 65706f5f _ope DCD 1701867359 - 0x0100763c: 006e n. DCW 110 - __FUNCTION__ - 0x0100763e: 7472 rt DCW 29810 - 0x01007640: 7665645f _dev DCD 1986356319 - 0x01007644: 5f656369 ice_ DCD 1600480105 - 0x01007648: 736f6c63 clos DCD 1936682083 - 0x0100764c: 0065 e. DCW 101 - __FUNCTION__ - 0x0100764e: 7472 rt DCW 29810 - 0x01007650: 7665645f _dev DCD 1986356319 - 0x01007654: 5f656369 ice_ DCD 1600480105 - 0x01007658: 64616572 read DCD 1684104562 - 0x0100765c: 00 . DCB 0 - __FUNCTION__ - 0x0100765d: 72745f rt_ DCB 114,116,95 - 0x01007660: 69766564 devi DCD 1769366884 - 0x01007664: 775f6563 ce_w DCD 2002740579 - 0x01007668: 65746972 rite DCD 1702127986 - 0x0100766c: 00 . DCB 0 - __FUNCTION__ - 0x0100766d: 72745f rt_ DCB 114,116,95 - 0x01007670: 69766564 devi DCD 1769366884 - 0x01007674: 635f6563 ce_c DCD 1667196259 - 0x01007678: 72746e6f ontr DCD 1920233071 - 0x0100767c: 6c6f ol DCW 27759 - 0x0100767e: 00 . DCB 0 - __FUNCTION__ - 0x0100767f: 72 r DCB 114 - 0x01007680: 65645f74 t_de DCD 1701076852 - 0x01007684: 65636976 vice DCD 1701013878 - 0x01007688: 7465735f _set DCD 1952805727 - 0x0100768c: 5f78725f _rx_ DCD 1601729119 - 0x01007690: 69646e69 indi DCD 1768189545 - 0x01007694: 65746163 cate DCD 1702125923 - 0x01007698: 00 . DCB 0 - __FUNCTION__ - 0x01007699: 72745f rt_ DCB 114,116,95 - 0x0100769c: 69766564 devi DCD 1769366884 - 0x010076a0: 735f6563 ce_s DCD 1935631715 - 0x010076a4: 745f7465 et_t DCD 1952412773 - 0x010076a8: 6f635f78 x_co DCD 1868783480 - 0x010076ac: 656c706d mple DCD 1701605485 - 0x010076b0: 6574 te DCW 25972 - 0x010076b2: 00 . DCB 0 - .constdata - __lowest_bit_bitmap - 0x010076b3: 00 . DCB 0 - 0x010076b4: 02000100 .... DCD 33554688 - 0x010076b8: 03000100 .... DCD 50331904 - 0x010076bc: 02000100 .... DCD 33554688 - 0x010076c0: 04000100 .... DCD 67109120 - 0x010076c4: 02000100 .... DCD 33554688 - 0x010076c8: 03000100 .... DCD 50331904 - 0x010076cc: 02000100 .... DCD 33554688 - 0x010076d0: 05000100 .... DCD 83886336 - 0x010076d4: 02000100 .... DCD 33554688 - 0x010076d8: 03000100 .... DCD 50331904 - 0x010076dc: 02000100 .... DCD 33554688 - 0x010076e0: 04000100 .... DCD 67109120 - 0x010076e4: 02000100 .... DCD 33554688 - 0x010076e8: 03000100 .... DCD 50331904 - 0x010076ec: 02000100 .... DCD 33554688 - 0x010076f0: 06000100 .... DCD 100663552 - 0x010076f4: 02000100 .... DCD 33554688 - 0x010076f8: 03000100 .... DCD 50331904 - 0x010076fc: 02000100 .... DCD 33554688 - 0x01007700: 04000100 .... DCD 67109120 - 0x01007704: 02000100 .... DCD 33554688 - 0x01007708: 03000100 .... DCD 50331904 - 0x0100770c: 02000100 .... DCD 33554688 - 0x01007710: 05000100 .... DCD 83886336 - 0x01007714: 02000100 .... DCD 33554688 - 0x01007718: 03000100 .... DCD 50331904 - 0x0100771c: 02000100 .... DCD 33554688 - 0x01007720: 04000100 .... DCD 67109120 - 0x01007724: 02000100 .... DCD 33554688 - 0x01007728: 03000100 .... DCD 50331904 - 0x0100772c: 02000100 .... DCD 33554688 - 0x01007730: 07000100 .... DCD 117440768 - 0x01007734: 02000100 .... DCD 33554688 - 0x01007738: 03000100 .... DCD 50331904 - 0x0100773c: 02000100 .... DCD 33554688 - 0x01007740: 04000100 .... DCD 67109120 - 0x01007744: 02000100 .... DCD 33554688 - 0x01007748: 03000100 .... DCD 50331904 - 0x0100774c: 02000100 .... DCD 33554688 - 0x01007750: 05000100 .... DCD 83886336 - 0x01007754: 02000100 .... DCD 33554688 - 0x01007758: 03000100 .... DCD 50331904 - 0x0100775c: 02000100 .... DCD 33554688 - 0x01007760: 04000100 .... DCD 67109120 - 0x01007764: 02000100 .... DCD 33554688 - 0x01007768: 03000100 .... DCD 50331904 - 0x0100776c: 02000100 .... DCD 33554688 - 0x01007770: 06000100 .... DCD 100663552 - 0x01007774: 02000100 .... DCD 33554688 - 0x01007778: 03000100 .... DCD 50331904 - 0x0100777c: 02000100 .... DCD 33554688 - 0x01007780: 04000100 .... DCD 67109120 - 0x01007784: 02000100 .... DCD 33554688 - 0x01007788: 03000100 .... DCD 50331904 - 0x0100778c: 02000100 .... DCD 33554688 - 0x01007790: 05000100 .... DCD 83886336 - 0x01007794: 02000100 .... DCD 33554688 - 0x01007798: 03000100 .... DCD 50331904 - 0x0100779c: 02000100 .... DCD 33554688 - 0x010077a0: 04000100 .... DCD 67109120 - 0x010077a4: 02000100 .... DCD 33554688 - 0x010077a8: 03000100 .... DCD 50331904 - 0x010077ac: 02000100 .... DCD 33554688 - 0x010077b0: 0100 .. DCW 256 - 0x010077b2: 00 . DCB 0 - small_digits - 0x010077b3: 30 0 DCB 48 - 0x010077b4: 34333231 1234 DCD 875770417 - 0x010077b8: 38373635 5678 DCD 943142453 - 0x010077bc: 63626139 9abc DCD 1667391801 - 0x010077c0: 00666564 def. DCD 6710628 - large_digits - 0x010077c4: 33323130 0123 DCD 858927408 - 0x010077c8: 37363534 4567 DCD 926299444 - 0x010077cc: 42413938 89AB DCD 1111570744 - 0x010077d0: 46454443 CDEF DCD 1178944579 - 0x010077d4: 00 . DCB 0 - .constdata - __FUNCTION__ - 0x010077d5: 5f6970 _ip DCB 95,105,112 - 0x010077d8: 696c5f63 c_li DCD 1768709987 - 0x010077dc: 735f7473 st_s DCD 1935635571 - 0x010077e0: 65707375 uspe DCD 1701868405 - 0x010077e4: 646e nd DCW 25710 - 0x010077e6: 00 . DCB 0 - __FUNCTION__ - 0x010077e7: 72 r DCB 114 - 0x010077e8: 65735f74 t_se DCD 1702059892 - 0x010077ec: 6e695f6d m_in DCD 1852399469 - 0x010077f0: 7469 it DCW 29801 - 0x010077f2: 00 . DCB 0 - __FUNCTION__ - 0x010077f3: 72 r DCB 114 - 0x010077f4: 65735f74 t_se DCD 1702059892 - 0x010077f8: 65645f6d m_de DCD 1701076845 - 0x010077fc: 68636174 tach DCD 1751343476 - 0x01007800: 00 . DCB 0 - __FUNCTION__ - 0x01007801: 72745f rt_ DCB 114,116,95 - 0x01007804: 5f6d6573 sem_ DCD 1601004915 - 0x01007808: 61657263 crea DCD 1634038371 - 0x0100780c: 6574 te DCW 25972 - 0x0100780e: 00 . DCB 0 - __FUNCTION__ - 0x0100780f: 72 r DCB 114 - 0x01007810: 65735f74 t_se DCD 1702059892 - 0x01007814: 65645f6d m_de DCD 1701076845 - 0x01007818: 6574656c lete DCD 1702126956 - 0x0100781c: 00 . DCB 0 - __FUNCTION__ - 0x0100781d: 72745f rt_ DCB 114,116,95 - 0x01007820: 5f6d6573 sem_ DCD 1601004915 - 0x01007824: 656b6174 take DCD 1701536116 - 0x01007828: 00 . DCB 0 - __FUNCTION__ - 0x01007829: 72745f rt_ DCB 114,116,95 - 0x0100782c: 5f6d6573 sem_ DCD 1601004915 - 0x01007830: 656c6572 rele DCD 1701602674 - 0x01007834: 00657361 ase. DCD 6648673 - __FUNCTION__ - 0x01007838: 735f7472 rt_s DCD 1935635570 - 0x0100783c: 635f6d65 em_c DCD 1667198309 - 0x01007840: 72746e6f ontr DCD 1920233071 - 0x01007844: 6c6f ol DCW 27759 - 0x01007846: 00 . DCB 0 - __FUNCTION__ - 0x01007847: 72 r DCB 114 - 0x01007848: 756d5f74 t_mu DCD 1970102132 - 0x0100784c: 5f786574 tex_ DCD 1601725812 - 0x01007850: 74696e69 init DCD 1953066601 - 0x01007854: 00 . DCB 0 - __FUNCTION__ - 0x01007855: 72745f rt_ DCB 114,116,95 - 0x01007858: 6574756d mute DCD 1702131053 - 0x0100785c: 65645f78 x_de DCD 1701076856 - 0x01007860: 68636174 tach DCD 1751343476 - 0x01007864: 00 . DCB 0 - __FUNCTION__ - 0x01007865: 72745f rt_ DCB 114,116,95 - 0x01007868: 6574756d mute DCD 1702131053 - 0x0100786c: 72635f78 x_cr DCD 1919115128 - 0x01007870: 65746165 eate DCD 1702125925 - 0x01007874: 00 . DCB 0 - __FUNCTION__ - 0x01007875: 72745f rt_ DCB 114,116,95 - 0x01007878: 6574756d mute DCD 1702131053 - 0x0100787c: 65645f78 x_de DCD 1701076856 - 0x01007880: 6574656c lete DCD 1702126956 - 0x01007884: 00 . DCB 0 - __FUNCTION__ - 0x01007885: 72745f rt_ DCB 114,116,95 - 0x01007888: 6574756d mute DCD 1702131053 - 0x0100788c: 61745f78 x_ta DCD 1635016568 - 0x01007890: 656b ke DCW 25963 - 0x01007892: 00 . DCB 0 - __FUNCTION__ - 0x01007893: 72 r DCB 114 - 0x01007894: 756d5f74 t_mu DCD 1970102132 - 0x01007898: 5f786574 tex_ DCD 1601725812 - 0x0100789c: 656c6572 rele DCD 1701602674 - 0x010078a0: 00657361 ase. DCD 6648673 - __FUNCTION__ - 0x010078a4: 6d5f7472 rt_m DCD 1834972274 - 0x010078a8: 78657475 utex DCD 2019914869 - 0x010078ac: 6e6f635f _con DCD 1852793695 - 0x010078b0: 6c6f7274 trol DCD 1819243124 - 0x010078b4: 00 . DCB 0 - __FUNCTION__ - 0x010078b5: 72745f rt_ DCB 114,116,95 - 0x010078b8: 6e657665 even DCD 1852143205 - 0x010078bc: 6e695f74 t_in DCD 1852399476 - 0x010078c0: 7469 it DCW 29801 - 0x010078c2: 00 . DCB 0 - __FUNCTION__ - 0x010078c3: 72 r DCB 114 - 0x010078c4: 76655f74 t_ev DCD 1986355060 - 0x010078c8: 5f746e65 ent_ DCD 1601465957 - 0x010078cc: 61746564 deta DCD 1635018084 - 0x010078d0: 6863 ch DCW 26723 - 0x010078d2: 00 . DCB 0 - __FUNCTION__ - 0x010078d3: 72 r DCB 114 - 0x010078d4: 76655f74 t_ev DCD 1986355060 - 0x010078d8: 5f746e65 ent_ DCD 1601465957 - 0x010078dc: 61657263 crea DCD 1634038371 - 0x010078e0: 6574 te DCW 25972 - 0x010078e2: 00 . DCB 0 - __FUNCTION__ - 0x010078e3: 72 r DCB 114 - 0x010078e4: 76655f74 t_ev DCD 1986355060 - 0x010078e8: 5f746e65 ent_ DCD 1601465957 - 0x010078ec: 656c6564 dele DCD 1701602660 - 0x010078f0: 6574 te DCW 25972 - 0x010078f2: 00 . DCB 0 - __FUNCTION__ - 0x010078f3: 72 r DCB 114 - 0x010078f4: 76655f74 t_ev DCD 1986355060 - 0x010078f8: 5f746e65 ent_ DCD 1601465957 - 0x010078fc: 646e6573 send DCD 1684956531 - 0x01007900: 00 . DCB 0 - __FUNCTION__ - 0x01007901: 72745f rt_ DCB 114,116,95 - 0x01007904: 6e657665 even DCD 1852143205 - 0x01007908: 65725f74 t_re DCD 1701994356 - 0x0100790c: 7663 cv DCW 30307 - 0x0100790e: 00 . DCB 0 - __FUNCTION__ - 0x0100790f: 72 r DCB 114 - 0x01007910: 76655f74 t_ev DCD 1986355060 - 0x01007914: 5f746e65 ent_ DCD 1601465957 - 0x01007918: 746e6f63 cont DCD 1953394531 - 0x0100791c: 006c6f72 rol. DCD 7106418 - __FUNCTION__ - 0x01007920: 6d5f7472 rt_m DCD 1834972274 - 0x01007924: 6e695f62 b_in DCD 1852399458 - 0x01007928: 7469 it DCW 29801 - 0x0100792a: 00 . DCB 0 - __FUNCTION__ - 0x0100792b: 72 r DCB 114 - 0x0100792c: 626d5f74 t_mb DCD 1651335028 - 0x01007930: 7465645f _det DCD 1952801887 - 0x01007934: 00686361 ach. DCD 6841185 - __FUNCTION__ - 0x01007938: 6d5f7472 rt_m DCD 1834972274 - 0x0100793c: 72635f62 b_cr DCD 1919115106 - 0x01007940: 65746165 eate DCD 1702125925 - 0x01007944: 00 . DCB 0 - __FUNCTION__ - 0x01007945: 72745f rt_ DCB 114,116,95 - 0x01007948: 645f626d mb_d DCD 1683972717 - 0x0100794c: 74656c65 elet DCD 1952803941 - 0x01007950: 0065 e. DCW 101 - __FUNCTION__ - 0x01007952: 7472 rt DCW 29810 - 0x01007954: 5f626d5f _mb_ DCD 1600286047 - 0x01007958: 646e6573 send DCD 1684956531 - 0x0100795c: 6961775f _wai DCD 1767995231 - 0x01007960: 0074 t. DCW 116 - __FUNCTION__ - 0x01007962: 7472 rt DCW 29810 - 0x01007964: 5f626d5f _mb_ DCD 1600286047 - 0x01007968: 65677275 urge DCD 1701278325 - 0x0100796c: 746e nt DCW 29806 - 0x0100796e: 00 . DCB 0 - __FUNCTION__ - 0x0100796f: 72 r DCB 114 - 0x01007970: 626d5f74 t_mb DCD 1651335028 - 0x01007974: 6365725f _rec DCD 1667592799 - 0x01007978: 0076 v. DCW 118 - __FUNCTION__ - 0x0100797a: 7472 rt DCW 29810 - 0x0100797c: 5f626d5f _mb_ DCD 1600286047 - 0x01007980: 746e6f63 cont DCD 1953394531 - 0x01007984: 006c6f72 rol. DCD 7106418 - __FUNCTION__ - 0x01007988: 6d5f7472 rt_m DCD 1834972274 - 0x0100798c: 6e695f71 q_in DCD 1852399473 - 0x01007990: 7469 it DCW 29801 - 0x01007992: 00 . DCB 0 - __FUNCTION__ - 0x01007993: 72 r DCB 114 - 0x01007994: 716d5f74 t_mq DCD 1902993268 - 0x01007998: 7465645f _det DCD 1952801887 - 0x0100799c: 00686361 ach. DCD 6841185 - __FUNCTION__ - 0x010079a0: 6d5f7472 rt_m DCD 1834972274 - 0x010079a4: 72635f71 q_cr DCD 1919115121 - 0x010079a8: 65746165 eate DCD 1702125925 - 0x010079ac: 00 . DCB 0 - __FUNCTION__ - 0x010079ad: 72745f rt_ DCB 114,116,95 - 0x010079b0: 645f716d mq_d DCD 1683976557 - 0x010079b4: 74656c65 elet DCD 1952803941 - 0x010079b8: 0065 e. DCW 101 - __FUNCTION__ - 0x010079ba: 7472 rt DCW 29810 - 0x010079bc: 5f716d5f _mq_ DCD 1601269087 - 0x010079c0: 646e6573 send DCD 1684956531 - 0x010079c4: 6961775f _wai DCD 1767995231 - 0x010079c8: 0074 t. DCW 116 - __FUNCTION__ - 0x010079ca: 7472 rt DCW 29810 - 0x010079cc: 5f716d5f _mq_ DCD 1601269087 - 0x010079d0: 65677275 urge DCD 1701278325 - 0x010079d4: 746e nt DCW 29806 - 0x010079d6: 00 . DCB 0 - __FUNCTION__ - 0x010079d7: 72 r DCB 114 - 0x010079d8: 716d5f74 t_mq DCD 1902993268 - 0x010079dc: 6365725f _rec DCD 1667592799 - 0x010079e0: 0076 v. DCW 118 - __FUNCTION__ - 0x010079e2: 7472 rt DCW 29810 - 0x010079e4: 5f716d5f _mq_ DCD 1601269087 - 0x010079e8: 746e6f63 cont DCD 1953394531 - 0x010079ec: 006c6f72 rol. DCD 7106418 - .constdata - __FUNCTION__ - 0x010079f0: 745f7472 rt_t DCD 1952412786 - 0x010079f4: 72656d69 imer DCD 1919249769 - 0x010079f8: 696e695f _ini DCD 1768843615 - 0x010079fc: 0074 t. DCW 116 - __FUNCTION__ - 0x010079fe: 7472 rt DCW 29810 - 0x01007a00: 6d69745f _tim DCD 1835627615 - 0x01007a04: 645f7265 er_d DCD 1683976805 - 0x01007a08: 63617465 etac DCD 1667331173 - 0x01007a0c: 0068 h. DCW 104 - __FUNCTION__ - 0x01007a0e: 7472 rt DCW 29810 - 0x01007a10: 6d69745f _tim DCD 1835627615 - 0x01007a14: 645f7265 er_d DCD 1683976805 - 0x01007a18: 74656c65 elet DCD 1952803941 - 0x01007a1c: 0065 e. DCW 101 - __FUNCTION__ - 0x01007a1e: 7472 rt DCW 29810 - 0x01007a20: 6d69745f _tim DCD 1835627615 - 0x01007a24: 735f7265 er_s DCD 1935635045 - 0x01007a28: 74726174 tart DCD 1953653108 - 0x01007a2c: 00 . DCB 0 - __FUNCTION__ - 0x01007a2d: 72745f rt_ DCB 114,116,95 - 0x01007a30: 656d6974 time DCD 1701669236 - 0x01007a34: 74735f72 r_st DCD 1953718130 - 0x01007a38: 706f op DCW 28783 - 0x01007a3a: 00 . DCB 0 - __FUNCTION__ - 0x01007a3b: 72 r DCB 114 - 0x01007a3c: 69745f74 t_ti DCD 1769234292 - 0x01007a40: 5f72656d mer_ DCD 1601332589 - 0x01007a44: 746e6f63 cont DCD 1953394531 - 0x01007a48: 006c6f72 rol. DCD 7106418 - .constdata - __FUNCTION__ - 0x01007a4c: 6f5f7472 rt_o DCD 1868526706 - 0x01007a50: 63656a62 bjec DCD 1667590754 - 0x01007a54: 6e695f74 t_in DCD 1852399476 - 0x01007a58: 7469 it DCW 29801 - 0x01007a5a: 00 . DCB 0 - __FUNCTION__ - 0x01007a5b: 72 r DCB 114 - 0x01007a5c: 626f5f74 t_ob DCD 1651466100 - 0x01007a60: 7463656a ject DCD 1952671082 - 0x01007a64: 7465645f _det DCD 1952801887 - 0x01007a68: 00686361 ach. DCD 6841185 - __FUNCTION__ - 0x01007a6c: 6f5f7472 rt_o DCD 1868526706 - 0x01007a70: 63656a62 bjec DCD 1667590754 - 0x01007a74: 6c615f74 t_al DCD 1818320756 - 0x01007a78: 61636f6c loca DCD 1633906540 - 0x01007a7c: 6574 te DCW 25972 - 0x01007a7e: 00 . DCB 0 - __FUNCTION__ - 0x01007a7f: 72 r DCB 114 - 0x01007a80: 626f5f74 t_ob DCD 1651466100 - 0x01007a84: 7463656a ject DCD 1952671082 - 0x01007a88: 6c65645f _del DCD 1818584159 - 0x01007a8c: 00657465 ete. DCD 6648933 - __FUNCTION__ - 0x01007a90: 6f5f7472 rt_o DCD 1868526706 - 0x01007a94: 63656a62 bjec DCD 1667590754 - 0x01007a98: 73695f74 t_is DCD 1936285556 - 0x01007a9c: 7379735f _sys DCD 1937339231 - 0x01007aa0: 6f6d6574 temo DCD 1869440372 - 0x01007aa4: 63656a62 bjec DCD 1667590754 - 0x01007aa8: 0074 t. DCW 116 - __FUNCTION__ - 0x01007aaa: 7472 rt DCW 29810 - 0x01007aac: 6a626f5f _obj DCD 1784835935 - 0x01007ab0: 5f746365 ect_ DCD 1601463141 - 0x01007ab4: 5f746567 get_ DCD 1601463655 - 0x01007ab8: 65707974 type DCD 1701869940 - 0x01007abc: 00 . DCB 0 - __FUNCTION__ - 0x01007abd: 72745f rt_ DCB 114,116,95 - 0x01007ac0: 656a626f obje DCD 1701470831 - 0x01007ac4: 665f7463 ct_f DCD 1717531747 - 0x01007ac8: 00646e69 ind. DCD 6581865 - .constdata - __FUNCTION__ - 0x01007acc: 6d5f7472 rt_m DCD 1834972274 - 0x01007ad0: 65686d65 emhe DCD 1701342565 - 0x01007ad4: 695f7061 ap_i DCD 1767862369 - 0x01007ad8: 0074696e nit. DCD 7629166 - __FUNCTION__ - 0x01007adc: 6d5f7472 rt_m DCD 1834972274 - 0x01007ae0: 65686d65 emhe DCD 1701342565 - 0x01007ae4: 645f7061 ap_d DCD 1683976289 - 0x01007ae8: 63617465 etac DCD 1667331173 - 0x01007aec: 0068 h. DCW 104 - __FUNCTION__ - 0x01007aee: 7472 rt DCW 29810 - 0x01007af0: 6d656d5f _mem DCD 1835363679 - 0x01007af4: 70616568 heap DCD 1885431144 - 0x01007af8: 6c6c615f _all DCD 1819042143 - 0x01007afc: 636f oc DCW 25455 - 0x01007afe: 00 . DCB 0 - __FUNCTION__ - 0x01007aff: 72 r DCB 114 - 0x01007b00: 656d5f74 t_me DCD 1701666676 - 0x01007b04: 6165686d mhea DCD 1634035821 - 0x01007b08: 65725f70 p_re DCD 1701994352 - 0x01007b0c: 6f6c6c61 allo DCD 1869376609 - 0x01007b10: 0063 c. DCW 99 - __FUNCTION__ - 0x01007b12: 7472 rt DCW 29810 - 0x01007b14: 6d656d5f _mem DCD 1835363679 - 0x01007b18: 70616568 heap DCD 1885431144 - 0x01007b1c: 6572665f _fre DCD 1701996127 - 0x01007b20: 0065 e. DCW 101 - __FUNCTION__ - 0x01007b22: 7472 rt DCW 29810 - 0x01007b24: 6d656d5f _mem DCD 1835363679 - 0x01007b28: 70616568 heap DCD 1885431144 - 0x01007b2c: 6d75645f _dum DCD 1836409951 - 0x01007b30: 0070 p. DCW 112 - .constdata - __FUNCTION__ - 0x01007b32: 745f _t DCW 29791 - 0x01007b34: 61657268 hrea DCD 1634038376 - 0x01007b38: 6e695f64 d_in DCD 1852399460 - 0x01007b3c: 7469 it DCW 29801 - 0x01007b3e: 00 . DCB 0 - __FUNCTION__ - 0x01007b3f: 72 r DCB 114 - 0x01007b40: 68745f74 t_th DCD 1752457076 - 0x01007b44: 64616572 read DCD 1684104562 - 0x01007b48: 696e695f _ini DCD 1768843615 - 0x01007b4c: 0074 t. DCW 116 - __FUNCTION__ - 0x01007b4e: 7472 rt DCW 29810 - 0x01007b50: 7268745f _thr DCD 1919448159 - 0x01007b54: 5f646165 ead_ DCD 1600414053 - 0x01007b58: 72617473 star DCD 1918989427 - 0x01007b5c: 00707574 tup. DCD 7370100 - __FUNCTION__ - 0x01007b60: 745f7472 rt_t DCD 1952412786 - 0x01007b64: 61657268 hrea DCD 1634038376 - 0x01007b68: 65645f64 d_de DCD 1701076836 - 0x01007b6c: 68636174 tach DCD 1751343476 - 0x01007b70: 00 . DCB 0 - __FUNCTION__ - 0x01007b71: 72745f rt_ DCB 114,116,95 - 0x01007b74: 65726874 thre DCD 1701996660 - 0x01007b78: 645f6461 ad_d DCD 1683973217 - 0x01007b7c: 74656c65 elet DCD 1952803941 - 0x01007b80: 0065 e. DCW 101 - __FUNCTION__ - 0x01007b82: 7472 rt DCW 29810 - 0x01007b84: 7268745f _thr DCD 1919448159 - 0x01007b88: 5f646165 ead_ DCD 1600414053 - 0x01007b8c: 65656c73 slee DCD 1701145715 - 0x01007b90: 0070 p. DCW 112 - __FUNCTION__ - 0x01007b92: 7472 rt DCW 29810 - 0x01007b94: 7268745f _thr DCD 1919448159 - 0x01007b98: 5f646165 ead_ DCD 1600414053 - 0x01007b9c: 616c6564 dela DCD 1634493796 - 0x01007ba0: 6e755f79 y_un DCD 1853185913 - 0x01007ba4: 006c6974 til. DCD 7104884 - __FUNCTION__ - 0x01007ba8: 745f7472 rt_t DCD 1952412786 - 0x01007bac: 61657268 hrea DCD 1634038376 - 0x01007bb0: 6f635f64 d_co DCD 1868783460 - 0x01007bb4: 6f72746e ntro DCD 1869771886 - 0x01007bb8: 006c l. DCW 108 - __FUNCTION__ - 0x01007bba: 7472 rt DCW 29810 - 0x01007bbc: 7268745f _thr DCD 1919448159 - 0x01007bc0: 5f646165 ead_ DCD 1600414053 - 0x01007bc4: 70737573 susp DCD 1886614899 - 0x01007bc8: 00646e65 end. DCD 6581861 - __FUNCTION__ - 0x01007bcc: 745f7472 rt_t DCD 1952412786 - 0x01007bd0: 61657268 hrea DCD 1634038376 - 0x01007bd4: 65725f64 d_re DCD 1701994340 - 0x01007bd8: 656d7573 sume DCD 1701672307 - 0x01007bdc: 00 . DCB 0 - __FUNCTION__ - 0x01007bdd: 72745f rt_ DCB 114,116,95 - 0x01007be0: 65726874 thre DCD 1701996660 - 0x01007be4: 745f6461 ad_t DCD 1952408673 - 0x01007be8: 6f656d69 imeo DCD 1868918121 - 0x01007bec: 7475 ut DCW 29813 - 0x01007bee: 00 . DCB 0 - .constdata - __FUNCTION__ - 0x01007bef: 70 p DCB 112 - 0x01007bf0: 5f67756c lug_ DCD 1600615788 - 0x01007bf4: 656c6f68 hole DCD 1701605224 - 0x01007bf8: 0073 s. DCW 115 - __FUNCTION__ - 0x01007bfa: 7472 rt DCW 29810 - 0x01007bfc: 7379735f _sys DCD 1937339231 - 0x01007c00: 5f6d6574 tem_ DCD 1601004916 - 0x01007c04: 70616568 heap DCD 1885431144 - 0x01007c08: 696e695f _ini DCD 1768843615 - 0x01007c0c: 0074 t. DCW 116 - __FUNCTION__ - 0x01007c0e: 7472 rt DCW 29810 - 0x01007c10: 6c616d5f _mal DCD 1818324319 - 0x01007c14: 00636f6c loc. DCD 6516588 - __FUNCTION__ - 0x01007c18: 725f7472 rt_r DCD 1918858354 - 0x01007c1c: 6c6c6165 eall DCD 1819042149 - 0x01007c20: 636f oc DCW 25455 - 0x01007c22: 00 . DCB 0 - __FUNCTION__ - 0x01007c23: 72 r DCB 114 - 0x01007c24: 72665f74 t_fr DCD 1919311732 - 0x01007c28: 6565 ee DCW 25957 - 0x01007c2a: 00 . DCB 0 - .constdata - __FUNCTION__ - 0x01007c2b: 55 U DCB 85 - 0x01007c2c: 5f545241 ART_ DCD 1599361601 - 0x01007c30: 6f747541 Auto DCD 1869903169 - 0x01007c34: 776f6c46 Flow DCD 2003790918 - 0x01007c38: 6c727443 Ctrl DCD 1819440195 - 0x01007c3c: 00646d43 Cmd. DCD 6581571 - __FUNCTION__ - 0x01007c40: 54524155 UART DCD 1414676821 - 0x01007c44: 4965445f _DeI DCD 1231373407 - 0x01007c48: 0074696e nit. DCD 7629166 - __FUNCTION__ - 0x01007c4c: 54524155 UART DCD 1414676821 - 0x01007c50: 414d445f _DMA DCD 1095582815 - 0x01007c54: 646e6553 Send DCD 1684956499 - 0x01007c58: 00667542 Buf. DCD 6714690 - __FUNCTION__ - 0x01007c5c: 54524155 UART DCD 1414676821 - 0x01007c60: 696e495f _Ini DCD 1768835423 - 0x01007c64: 0074 t. DCW 116 - __FUNCTION__ - 0x01007c66: 4155 UA DCW 16725 - 0x01007c68: 495f5452 RT_I DCD 1230984274 - 0x01007c6c: 46585273 sRXF DCD 1180193395 - 0x01007c70: 464f4649 IFOF DCD 1179600457 - 0x01007c74: 006c6c75 ull. DCD 7105653 - __FUNCTION__ - 0x01007c78: 54524155 UART DCD 1414676821 - 0x01007c7c: 5273495f _IsR DCD 1383287135 - 0x01007c80: 46494658 XFIF DCD 1179207256 - 0x01007c84: 746f4e4f ONot DCD 1953451599 - 0x01007c88: 74706d45 Empt DCD 1953525061 - 0x01007c8c: 0079 y. DCW 121 - __FUNCTION__ - 0x01007c8e: 4155 UA DCW 16725 - 0x01007c90: 495f5452 RT_I DCD 1230984274 - 0x01007c94: 52415573 sUAR DCD 1380013427 - 0x01007c98: 73754254 TBus DCD 1937064532 - 0x01007c9c: 0079 y. DCW 121 - __FUNCTION__ - 0x01007c9e: 4155 UA DCW 16725 - 0x01007ca0: 495f5452 RT_I DCD 1230984274 - 0x01007ca4: 6e6f4354 TCon DCD 1852785492 - 0x01007ca8: 00676966 fig. DCD 6777190 - __FUNCTION__ - 0x01007cac: 54524155 UART DCD 1414676821 - 0x01007cb0: 6365525f _Rec DCD 1667584607 - 0x01007cb4: 65766965 eive DCD 1702259045 - 0x01007cb8: 61746144 Data DCD 1635017028 - 0x01007cbc: 00 . DCB 0 - __FUNCTION__ - 0x01007cbd: 554152 UAR DCB 85,65,82 - 0x01007cc0: 65525f54 T_Re DCD 1699897172 - 0x01007cc4: 75427663 cvBu DCD 1967289955 - 0x01007cc8: 0066 f. DCW 102 - __FUNCTION__ - 0x01007cca: 4155 UA DCW 16725 - 0x01007ccc: 535f5452 RT_S DCD 1398756434 - 0x01007cd0: 42646e65 endB DCD 1113878117 - 0x01007cd4: 6675 uf DCW 26229 - 0x01007cd6: 00 . DCB 0 - __FUNCTION__ - 0x01007cd7: 55 U DCB 85 - 0x01007cd8: 5f545241 ART_ DCD 1599361601 - 0x01007cdc: 52746553 SetR DCD 1383359827 - 0x01007ce0: 4e544978 xITN DCD 1314146680 - 0x01007ce4: 6d75 um DCW 28021 - 0x01007ce6: 00 . DCB 0 - __FUNCTION__ - 0x01007ce7: 55 U DCB 85 - 0x01007ce8: 5f545241 ART_ DCD 1599361601 - 0x01007cec: 65636552 Rece DCD 1701012818 - 0x01007cf0: 44657669 iveD DCD 1147500137 - 0x01007cf4: 4c617461 ataL DCD 1281455201 - 0x01007cf8: 00006e65 en.. DCD 28261 - .conststring - 0x01007cfc: 6e726157 Warn DCD 1852989783 - 0x01007d00: 3a676e69 ing: DCD 979857001 - 0x01007d04: 65685420 The DCD 1701336096 - 0x01007d08: 69206572 re i DCD 1763730802 - 0x01007d0c: 6f6e2073 s no DCD 1869488243 - 0x01007d10: 6f6e6520 eno DCD 1869505824 - 0x01007d14: 20686775 ugh DCD 543713141 - 0x01007d18: 66667562 buff DCD 1717990754 - 0x01007d1c: 66207265 er f DCD 1713402469 - 0x01007d20: 7320726f or s DCD 1931506287 - 0x01007d24: 6e697661 avin DCD 1852405345 - 0x01007d28: 61642067 g da DCD 1633951847 - 0x01007d2c: 202c6174 ta, DCD 539779444 - 0x01007d30: 61656c70 plea DCD 1634036848 - 0x01007d34: 69206573 se i DCD 1763730803 - 0x01007d38: 6572636e ncre DCD 1701995374 - 0x01007d3c: 20657361 ase DCD 543519585 - 0x01007d40: 20656874 the DCD 543516788 - 0x01007d44: 535f5452 RT_S DCD 1398756434 - 0x01007d48: 41495245 ERIA DCD 1095324229 - 0x01007d4c: 42525f4c L_RB DCD 1112694604 - 0x01007d50: 4655425f _BUF DCD 1179992671 - 0x01007d54: 6f205a53 SZ o DCD 1864391251 - 0x01007d58: 6f697470 ptio DCD 1869182064 - 0x01007d5c: 00002e6e n... DCD 11886 - .conststring - 0x01007d60: 2e2a2d25 %-*. DCD 774516005 - 0x01007d64: 72702073 s pr DCD 1919950963 - 0x01007d68: 73202069 i s DCD 1931485289 - 0x01007d6c: 75746174 tatu DCD 1970561396 - 0x01007d70: 20202073 s DCD 538976371 - 0x01007d74: 73202020 s DCD 1931485216 - 0x01007d78: 20202070 p DCD 538976368 - 0x01007d7c: 74732020 st DCD 1953701920 - 0x01007d80: 206b6361 ack DCD 543908705 - 0x01007d84: 657a6973 size DCD 1702521203 - 0x01007d88: 78616d20 max DCD 2019650848 - 0x01007d8c: 65737520 use DCD 1702065440 - 0x01007d90: 656c2064 d le DCD 1701584996 - 0x01007d94: 74207466 ft t DCD 1948284006 - 0x01007d98: 206b6369 ick DCD 543908713 - 0x01007d9c: 72726520 err DCD 1920099616 - 0x01007da0: 000a726f or.. DCD 684655 - 0x01007da4: 00435452 RTC. DCD 4412498 - 0x01007da8: 7774654e Netw DCD 2004116814 - 0x01007dac: 206b726f ork DCD 543912559 - 0x01007db0: 65746e49 Inte DCD 1702129225 - 0x01007db4: 63616672 rfac DCD 1667327602 - 0x01007db8: 00000065 e... DCD 101 - 0x01007dbc: 2044544d MTD DCD 541348941 - 0x01007dc0: 69766544 Devi DCD 1769366852 - 0x01007dc4: 00006563 ce.. DCD 25955 - 0x01007dc8: 20495053 SPI DCD 541675603 - 0x01007dcc: 69766544 Devi DCD 1769366852 - 0x01007dd0: 00006563 ce.. DCD 25955 - 0x01007dd4: 204e4143 CAN DCD 541999427 - 0x01007dd8: 69766544 Devi DCD 1769366852 - 0x01007ddc: 00006563 ce.. DCD 25955 - 0x01007de0: 70617247 Grap DCD 1885434439 - 0x01007de4: 20636968 hic DCD 543385960 - 0x01007de8: 69766544 Devi DCD 1769366852 - 0x01007dec: 00006563 ce.. DCD 25955 - 0x01007df0: 6e756f53 Soun DCD 1853189971 - 0x01007df4: 65442064 d De DCD 1698963556 - 0x01007df8: 65636976 vice DCD 1701013878 - 0x01007dfc: 00000000 .... DCD 0 - 0x01007e00: 20425355 USB DCD 541217621 - 0x01007e04: 76616c53 Slav DCD 1986096211 - 0x01007e08: 65442065 e De DCD 1698963557 - 0x01007e0c: 65636976 vice DCD 1701013878 - 0x01007e10: 00000000 .... DCD 0 - 0x01007e14: 63756f54 Touc DCD 1668640596 - 0x01007e18: 65442068 h De DCD 1698963560 - 0x01007e1c: 65636976 vice DCD 1701013878 - 0x01007e20: 00000000 .... DCD 0 - 0x01007e24: 636f6c42 Bloc DCD 1668246594 - 0x01007e28: 6544206b k De DCD 1698963563 - 0x01007e2c: 65636976 vice DCD 1701013878 - 0x01007e30: 00000000 .... DCD 0 - 0x01007e34: 74726f50 Port DCD 1953656656 - 0x01007e38: 44206c61 al D DCD 1142975585 - 0x01007e3c: 63697665 evic DCD 1667855973 - 0x01007e40: 00000065 e... DCD 101 - 0x01007e44: 50204d50 PM P DCD 1344294224 - 0x01007e48: 64756573 seud DCD 1685415283 - 0x01007e4c: 6544206f o De DCD 1698963567 - 0x01007e50: 65636976 vice DCD 1701013878 - 0x01007e54: 00000000 .... DCD 0 - 0x01007e58: 656d6954 Time DCD 1701669204 - 0x01007e5c: 65442072 r De DCD 1698963570 - 0x01007e60: 65636976 vice DCD 1701013878 - 0x01007e64: 00000000 .... DCD 0 - 0x01007e68: 72616843 Char DCD 1918986307 - 0x01007e6c: 65746361 acte DCD 1702126433 - 0x01007e70: 65442072 r De DCD 1698963570 - 0x01007e74: 65636976 vice DCD 1701013878 - 0x01007e78: 00000000 .... DCD 0 - 0x01007e7c: 736e6553 Sens DCD 1936614739 - 0x01007e80: 4420726f or D DCD 1142977135 - 0x01007e84: 63697665 evic DCD 1667855973 - 0x01007e88: 00000065 e... DCD 101 - 0x01007e8c: 6373694d Misc DCD 1668507981 - 0x01007e90: 616c6c65 ella DCD 1634495589 - 0x01007e94: 756f656e neou DCD 1970234734 - 0x01007e98: 65442073 s De DCD 1698963571 - 0x01007e9c: 65636976 vice DCD 1701013878 - 0x01007ea0: 00000000 .... DCD 0 - 0x01007ea4: 20796850 Phy DCD 544827472 - 0x01007ea8: 69766544 Devi DCD 1769366852 - 0x01007eac: 00006563 ce.. DCD 25955 - 0x01007eb0: 75636553 Secu DCD 1969448275 - 0x01007eb4: 79746972 rity DCD 2037672306 - 0x01007eb8: 76654420 Dev DCD 1986348064 - 0x01007ebc: 00656369 ice. DCD 6644585 - 0x01007ec0: 65706950 Pipe DCD 1701865808 - 0x01007ec4: 00000000 .... DCD 0 - 0x01007ec8: 6e6b6e55 Unkn DCD 1852534357 - 0x01007ecc: 006e776f own. DCD 7239535 - 0x01007ed0: 20433249 I2C DCD 541274697 - 0x01007ed4: 00737542 Bus. DCD 7566658 - 0x01007ed8: 20425355 USB DCD 541217621 - 0x01007edc: 2047544f OTG DCD 541545551 - 0x01007ee0: 00737542 Bus. DCD 7566658 - 0x01007ee4: 20495053 SPI DCD 541675603 - 0x01007ee8: 00737542 Bus. DCD 7566658 - 0x01007eec: 4f494453 SDIO DCD 1330201683 - 0x01007ef0: 73754220 Bus DCD 1937064480 - 0x01007ef4: 00000000 .... DCD 0 - 0x01007ef8: 20425355 USB DCD 541217621 - 0x01007efc: 74736f48 Host DCD 1953722184 - 0x01007f00: 73754220 Bus DCD 1937064480 - 0x01007f04: 00000000 .... DCD 0 - .conststring - 0x01007f08: 6f5f7472 rt_o DCD 1868526706 - 0x01007f0c: 63656a62 bjec DCD 1667590754 - 0x01007f10: 65675f74 t_ge DCD 1701273460 - 0x01007f14: 79745f74 t_ty DCD 2037669748 - 0x01007f18: 26286570 pe(& DCD 640181616 - 0x01007f1c: 2d6d6573 sem- DCD 762144115 - 0x01007f20: 7261703e >par DCD 1918988350 - 0x01007f24: 2e746e65 ent. DCD 779382373 - 0x01007f28: 65726170 pare DCD 1701994864 - 0x01007f2c: 2029746e nt) DCD 539587694 - 0x01007f30: 52203d3d == R DCD 1377844541 - 0x01007f34: 624f5f54 T_Ob DCD 1649368916 - 0x01007f38: 7463656a ject DCD 1952671082 - 0x01007f3c: 616c435f _Cla DCD 1634485087 - 0x01007f40: 535f7373 ss_S DCD 1398764403 - 0x01007f44: 70616d65 emap DCD 1885433189 - 0x01007f48: 65726f68 hore DCD 1701998440 - 0x01007f4c: 00000000 .... DCD 0 - .conststring - 0x01007f50: 6f5f7472 rt_o DCD 1868526706 - 0x01007f54: 63656a62 bjec DCD 1667590754 - 0x01007f58: 65675f74 t_ge DCD 1701273460 - 0x01007f5c: 79745f74 t_ty DCD 2037669748 - 0x01007f60: 28286570 pe(( DCD 673736048 - 0x01007f64: 6f5f7472 rt_o DCD 1868526706 - 0x01007f68: 63656a62 bjec DCD 1667590754 - 0x01007f6c: 29745f74 t_t) DCD 695492468 - 0x01007f70: 65726874 thre DCD 1701996660 - 0x01007f74: 20296461 ad) DCD 539583585 - 0x01007f78: 52203d3d == R DCD 1377844541 - 0x01007f7c: 624f5f54 T_Ob DCD 1649368916 - 0x01007f80: 7463656a ject DCD 1952671082 - 0x01007f84: 616c435f _Cla DCD 1634485087 - 0x01007f88: 545f7373 ss_T DCD 1415541619 - 0x01007f8c: 61657268 hrea DCD 1634038376 - 0x01007f90: 00000064 d... DCD 100 - .conststring - 0x01007f94: 5f747228 (rt_ DCD 1601466920 - 0x01007f98: 73616275 ubas DCD 1935762037 - 0x01007f9c: 29745f65 e_t) DCD 695492453 - 0x01007fa0: 74722828 ((rt DCD 1953638440 - 0x01007fa4: 6e69755f _uin DCD 1852405087 - 0x01007fa8: 745f3874 t8_t DCD 1952397428 - 0x01007fac: 6d292a20 *)m DCD 1831414304 - 0x01007fb0: 2b206d65 em + DCD 723545445 - 0x01007fb4: 5a495320 SIZ DCD 1514754848 - 0x01007fb8: 5f464f45 EOF_ DCD 1598443333 - 0x01007fbc: 55525453 STRU DCD 1431458899 - 0x01007fc0: 4d5f5443 CT_M DCD 1298093123 - 0x01007fc4: 20294d45 EM) DCD 539577669 - 0x01007fc8: 54522025 % RT DCD 1414668325 - 0x01007fcc: 494c415f _ALI DCD 1229734239 - 0x01007fd0: 535f4e47 GN_S DCD 1398754887 - 0x01007fd4: 20455a49 IZE DCD 541416009 - 0x01007fd8: 30203d3d == 0 DCD 807419197 - 0x01007fdc: 00000000 .... DCD 0 - 0x01007fe0: 5f747228 (rt_ DCD 1601466920 - 0x01007fe4: 746e6975 uint DCD 1953393013 - 0x01007fe8: 20745f38 8_t DCD 544497464 - 0x01007fec: 6d72292a *)rm DCD 1836198186 - 0x01007ff0: 3e206d65 em > DCD 1042312549 - 0x01007ff4: 7228203d = (r DCD 1915232317 - 0x01007ff8: 69755f74 t_ui DCD 1769299828 - 0x01007ffc: 5f38746e nt8_ DCD 1597535342 - 0x01008000: 292a2074 t *) DCD 690626676 - 0x01008004: 70616568 heap DCD 1885431144 - 0x01008008: 7274705f _ptr DCD 1920233567 - 0x0100800c: 20262620 && DCD 539371040 - 0x01008010: 5f747228 (rt_ DCD 1601466920 - 0x01008014: 746e6975 uint DCD 1953393013 - 0x01008018: 20745f38 8_t DCD 544497464 - 0x0100801c: 6d72292a *)rm DCD 1836198186 - 0x01008020: 3c206d65 em < DCD 1008758117 - 0x01008024: 74722820 (rt DCD 1953638432 - 0x01008028: 6e69755f _uin DCD 1852405087 - 0x0100802c: 745f3874 t8_t DCD 1952397428 - 0x01008030: 68292a20 *)h DCD 1747528224 - 0x01008034: 5f706165 eap_ DCD 1601200485 - 0x01008038: 00646e65 end. DCD 6581861 - 0x0100803c: 5f747228 (rt_ DCD 1601466920 - 0x01008040: 73616275 ubas DCD 1935762037 - 0x01008044: 29745f65 e_t) DCD 695492453 - 0x01008048: 206d656d mem DCD 544040301 - 0x0100804c: 4953202b + SI DCD 1230184491 - 0x01008050: 464f455a ZEOF DCD 1179600218 - 0x01008054: 5254535f _STR DCD 1381258079 - 0x01008058: 5f544355 UCT_ DCD 1599357781 - 0x0100805c: 204d454d MEM DCD 541934925 - 0x01008060: 6973202b + si DCD 1769152555 - 0x01008064: 3c20657a ze < DCD 1008756090 - 0x01008068: 7228203d = (r DCD 1915232317 - 0x0100806c: 62755f74 t_ub DCD 1651859316 - 0x01008070: 5f657361 ase_ DCD 1600484193 - 0x01008074: 65682974 t)he DCD 1701325172 - 0x01008078: 655f7061 ap_e DCD 1700753505 - 0x0100807c: 646e nd DCW 25710 - 0x0100807e: 00 . DCB 0 - .rodata.name - __fsym_help_name - 0x0100807f: 68 h DCB 104 - 0x01008080: 00706c65 elp. DCD 7367781 - __fsym_help_desc - 0x01008084: 2d205452 RT - DCD 757093458 - 0x01008088: 72685420 Thr DCD 1919439904 - 0x0100808c: 20646165 ead DCD 543449445 - 0x01008090: 6c656873 shel DCD 1818585203 - 0x01008094: 6568206c l he DCD 1701322860 - 0x01008098: 002e706c lp.. DCD 3043436 - __fsym_ps_name - 0x0100809c: 7370 ps DCW 29552 - 0x0100809e: 00 . DCB 0 - __fsym_ps_desc - 0x0100809f: 4c L DCB 76 - 0x010080a0: 20747369 ist DCD 544502633 - 0x010080a4: 65726874 thre DCD 1701996660 - 0x010080a8: 20736461 ads DCD 544433249 - 0x010080ac: 74206e69 in t DCD 1948282473 - 0x010080b0: 73206568 he s DCD 1931502952 - 0x010080b4: 65747379 yste DCD 1702130553 - 0x010080b8: 2e6d m. DCW 11885 - 0x010080ba: 00 . DCB 0 - __fsym_free_name - 0x010080bb: 66 f DCB 102 - 0x010080bc: 00656572 ree. DCD 6645106 - __fsym_free_desc - 0x010080c0: 776f6853 Show DCD 2003789907 - 0x010080c4: 65687420 the DCD 1701344288 - 0x010080c8: 6d656d20 mem DCD 1835363616 - 0x010080cc: 2079726f ory DCD 544830063 - 0x010080d0: 67617375 usag DCD 1734439797 - 0x010080d4: 6e692065 e in DCD 1852383333 - 0x010080d8: 65687420 the DCD 1701344288 - 0x010080dc: 73797320 sys DCD 1937339168 - 0x010080e0: 2e6d6574 tem. DCD 778921332 - 0x010080e4: 00 . DCB 0 - .rodata.name - __fsym_hello_name - 0x010080e5: 68656c hel DCB 104,101,108 - 0x010080e8: 6f6c lo DCW 28524 - 0x010080ea: 00 . DCB 0 - __fsym_hello_desc - 0x010080eb: 73 s DCB 115 - 0x010080ec: 68207961 ay h DCD 1746958689 - 0x010080f0: 6f6c6c65 ello DCD 1869376613 - 0x010080f4: 726f7720 wor DCD 1919907616 - 0x010080f8: 646c ld DCW 25708 - 0x010080fa: 00 . DCB 0 - __fsym_clear_name - 0x010080fb: 63 c DCB 99 - 0x010080fc: 7261656c lear DCD 1918985580 - 0x01008100: 00 . DCB 0 - __fsym_clear_desc - 0x01008101: 636c65 cle DCB 99,108,101 - 0x01008104: 74207261 ar t DCD 1948283489 - 0x01008108: 74206568 he t DCD 1948280168 - 0x0100810c: 696d7265 ermi DCD 1768780389 - 0x01008110: 206c616e nal DCD 543973742 - 0x01008114: 65726373 scre DCD 1701995379 - 0x01008118: 6e65 en DCW 28261 - 0x0100811a: 00 . DCB 0 - __fsym_version_name - 0x0100811b: 76 v DCB 118 - 0x0100811c: 69737265 ersi DCD 1769173605 - 0x01008120: 6e6f on DCW 28271 - 0x01008122: 00 . DCB 0 - __fsym_version_desc - 0x01008123: 73 s DCB 115 - 0x01008124: 20776f68 how DCD 544698216 - 0x01008128: 2d205452 RT - DCD 757093458 - 0x0100812c: 72685420 Thr DCD 1919439904 - 0x01008130: 20646165 ead DCD 543449445 - 0x01008134: 73726576 vers DCD 1936876918 - 0x01008138: 206e6f69 ion DCD 544108393 - 0x0100813c: 6f666e69 info DCD 1868983913 - 0x01008140: 74616d72 rmat DCD 1952542066 - 0x01008144: 006e6f69 ion. DCD 7237481 - __fsym_list_thread_name - 0x01008148: 7473696c list DCD 1953720684 - 0x0100814c: 7268745f _thr DCD 1919448159 - 0x01008150: 00646165 ead. DCD 6578533 - __fsym_list_thread_desc - 0x01008154: 7473696c list DCD 1953720684 - 0x01008158: 72687420 thr DCD 1919448096 - 0x0100815c: 00646165 ead. DCD 6578533 - __fsym_list_sem_name - 0x01008160: 7473696c list DCD 1953720684 - 0x01008164: 6d65735f _sem DCD 1835365215 - 0x01008168: 00 . DCB 0 - __fsym_list_sem_desc - 0x01008169: 6c6973 lis DCB 108,105,115 - 0x0100816c: 65732074 t se DCD 1702043764 - 0x01008170: 6870616d maph DCD 1752195437 - 0x01008174: 2065726f ore DCD 543519343 - 0x01008178: 73206e69 in s DCD 1931505257 - 0x0100817c: 65747379 yste DCD 1702130553 - 0x01008180: 006d m. DCW 109 - __fsym_list_event_name - 0x01008182: 696c li DCW 26988 - 0x01008184: 655f7473 st_e DCD 1700754547 - 0x01008188: 746e6576 vent DCD 1953391990 - 0x0100818c: 00 . DCB 0 - __fsym_list_event_desc - 0x0100818d: 6c6973 lis DCB 108,105,115 - 0x01008190: 76652074 t ev DCD 1986338932 - 0x01008194: 20746e65 ent DCD 544501349 - 0x01008198: 73206e69 in s DCD 1931505257 - 0x0100819c: 65747379 yste DCD 1702130553 - 0x010081a0: 006d m. DCW 109 - __fsym_list_mutex_name - 0x010081a2: 696c li DCW 26988 - 0x010081a4: 6d5f7473 st_m DCD 1834972275 - 0x010081a8: 78657475 utex DCD 2019914869 - 0x010081ac: 00 . DCB 0 - __fsym_list_mutex_desc - 0x010081ad: 6c6973 lis DCB 108,105,115 - 0x010081b0: 756d2074 t mu DCD 1970086004 - 0x010081b4: 20786574 tex DCD 544761204 - 0x010081b8: 73206e69 in s DCD 1931505257 - 0x010081bc: 65747379 yste DCD 1702130553 - 0x010081c0: 006d m. DCW 109 - __fsym_list_mailbox_name - 0x010081c2: 696c li DCW 26988 - 0x010081c4: 6d5f7473 st_m DCD 1834972275 - 0x010081c8: 626c6961 ailb DCD 1651272033 - 0x010081cc: 786f ox DCW 30831 - 0x010081ce: 00 . DCB 0 - __fsym_list_mailbox_desc - 0x010081cf: 6c l DCB 108 - 0x010081d0: 20747369 ist DCD 544502633 - 0x010081d4: 6c69616d mail DCD 1818845549 - 0x010081d8: 786f6220 box DCD 2020565536 - 0x010081dc: 206e6920 in DCD 544106784 - 0x010081e0: 74737973 syst DCD 1953724787 - 0x010081e4: 6d65 em DCW 28005 - 0x010081e6: 00 . DCB 0 - __fsym_list_msgqueue_name - 0x010081e7: 6c l DCB 108 - 0x010081e8: 5f747369 ist_ DCD 1601467241 - 0x010081ec: 7167736d msgq DCD 1902605165 - 0x010081f0: 65756575 ueue DCD 1702192501 - 0x010081f4: 00 . DCB 0 - __fsym_list_msgqueue_desc - 0x010081f5: 6c6973 lis DCB 108,105,115 - 0x010081f8: 656d2074 t me DCD 1701650548 - 0x010081fc: 67617373 ssag DCD 1734439795 - 0x01008200: 75712065 e qu DCD 1970348133 - 0x01008204: 20657565 eue DCD 543520101 - 0x01008208: 73206e69 in s DCD 1931505257 - 0x0100820c: 65747379 yste DCD 1702130553 - 0x01008210: 006d m. DCW 109 - __fsym_list_memheap_name - 0x01008212: 696c li DCW 26988 - 0x01008214: 6d5f7473 st_m DCD 1834972275 - 0x01008218: 65686d65 emhe DCD 1701342565 - 0x0100821c: 7061 ap DCW 28769 - 0x0100821e: 00 . DCB 0 - __fsym_list_memheap_desc - 0x0100821f: 6c l DCB 108 - 0x01008220: 20747369 ist DCD 544502633 - 0x01008224: 6f6d656d memo DCD 1869440365 - 0x01008228: 68207972 ry h DCD 1746958706 - 0x0100822c: 20706165 eap DCD 544235877 - 0x01008230: 73206e69 in s DCD 1931505257 - 0x01008234: 65747379 yste DCD 1702130553 - 0x01008238: 006d m. DCW 109 - __fsym_list_mempool_name - 0x0100823a: 696c li DCW 26988 - 0x0100823c: 6d5f7473 st_m DCD 1834972275 - 0x01008240: 6f706d65 empo DCD 1869639013 - 0x01008244: 6c6f ol DCW 27759 - 0x01008246: 00 . DCB 0 - __fsym_list_mempool_desc - 0x01008247: 6c l DCB 108 - 0x01008248: 20747369 ist DCD 544502633 - 0x0100824c: 6f6d656d memo DCD 1869440365 - 0x01008250: 70207972 ry p DCD 1881176434 - 0x01008254: 206c6f6f ool DCD 543977327 - 0x01008258: 73206e69 in s DCD 1931505257 - 0x0100825c: 65747379 yste DCD 1702130553 - 0x01008260: 006d m. DCW 109 - __fsym_list_timer_name - 0x01008262: 696c li DCW 26988 - 0x01008264: 745f7473 st_t DCD 1952412787 - 0x01008268: 72656d69 imer DCD 1919249769 - 0x0100826c: 00 . DCB 0 - __fsym_list_timer_desc - 0x0100826d: 6c6973 lis DCB 108,105,115 - 0x01008270: 69742074 t ti DCD 1769218164 - 0x01008274: 2072656d mer DCD 544367981 - 0x01008278: 73206e69 in s DCD 1931505257 - 0x0100827c: 65747379 yste DCD 1702130553 - 0x01008280: 006d m. DCW 109 - __fsym_list_device_name - 0x01008282: 696c li DCW 26988 - 0x01008284: 645f7473 st_d DCD 1683977331 - 0x01008288: 63697665 evic DCD 1667855973 - 0x0100828c: 0065 e. DCW 101 - __fsym_list_device_desc - 0x0100828e: 696c li DCW 26988 - 0x01008290: 64207473 st d DCD 1679848563 - 0x01008294: 63697665 evic DCD 1667855973 - 0x01008298: 6e692065 e in DCD 1852383333 - 0x0100829c: 73797320 sys DCD 1937339168 - 0x010082a0: 006d6574 tem. DCD 7169396 - __fsym_list_name - 0x010082a4: 7473696c list DCD 1953720684 - 0x010082a8: 00 . DCB 0 - __fsym_list_desc - 0x010082a9: 6c6973 lis DCB 108,105,115 - 0x010082ac: 6c612074 t al DCD 1818304628 - 0x010082b0: 6f63206c l co DCD 1868767340 - 0x010082b4: 6e616d6d mman DCD 1851878765 - 0x010082b8: 69207364 ds i DCD 1763734372 - 0x010082bc: 7973206e n sy DCD 2037588078 - 0x010082c0: 6d657473 stem DCD 1835365491 - 0x010082c4: 00 . DCB 0 - .rodata.name - __fsym_memheaptrace_name - 0x010082c5: 6d656d mem DCB 109,101,109 - 0x010082c8: 70616568 heap DCD 1885431144 - 0x010082cc: 63617274 trac DCD 1667330676 - 0x010082d0: 0065 e. DCW 101 - __fsym_memheaptrace_desc - 0x010082d2: 7564 du DCW 30052 - 0x010082d4: 6d20706d mp m DCD 1830842477 - 0x010082d8: 726f6d65 emor DCD 1919905125 - 0x010082dc: 72742079 y tr DCD 1920213113 - 0x010082e0: 20656361 ace DCD 543515489 - 0x010082e4: 6f666e69 info DCD 1868983913 - 0x010082e8: 74616d72 rmat DCD 1952542066 - 0x010082ec: 006e6f69 ion. DCD 7237481 - .rti_fn.0 - __tagsym$$used - __rt_init_rti_start - 0x010082f0: 01006c6b kl.. DCD 16804971 - .rti_fn.0.end - __tagsym$$used - __rt_init_rti_board_start - 0x010082f4: 01006c63 cl.. DCD 16804963 - .rti_fn.1 - __tagsym$$used - __rt_init_rt_hw_pin_init - 0x010082f8: 0100420d .B.. DCD 16794125 - .rti_fn.1 - __tagsym$$used - __rt_init_rt_hw_uart_init - 0x010082fc: 010043e9 .C.. DCD 16794601 - .rti_fn.1.end - __tagsym$$used - __rt_init_rti_board_end - 0x01008300: 01006c5f _l.. DCD 16804959 - .rti_fn.6 - __tagsym$$used - __rt_init_finsh_system_init - 0x01008304: 01001a29 )... DCD 16783913 - .rti_fn.6.end - __tagsym$$used - __rt_init_rti_end - 0x01008308: 01006c67 gl.. DCD 16804967 - FSymTab - __tagsym$$used - FSymTab$$Base - __fsym_help - 0x0100830c: 0100807f .... DCD 16810111 - 0x01008310: 01008084 .... DCD 16810116 - 0x01008314: 01003191 .1.. DCD 16789905 - __tagsym$$used - __fsym_ps - 0x01008318: 0100809c .... DCD 16810140 - 0x0100831c: 0100809f .... DCD 16810143 - 0x01008320: 010017b3 .... DCD 16783283 - __tagsym$$used - __fsym_free - 0x01008324: 010080bb .... DCD 16810171 - 0x01008328: 010080c0 .... DCD 16810176 - 0x0100832c: 010017a5 .... DCD 16783269 - FSymTab - __tagsym$$used - __fsym_hello - 0x01008330: 010080e5 .... DCD 16810213 - 0x01008334: 010080eb .... DCD 16810219 - 0x01008338: 010020c5 . .. DCD 16785605 - __tagsym$$used - __fsym_clear - 0x0100833c: 010080fb .... DCD 16810235 - 0x01008340: 01008101 .... DCD 16810241 - 0x01008344: 01001791 .... DCD 16783249 - __tagsym$$used - __fsym_version - 0x01008348: 0100811b .... DCD 16810267 - 0x0100834c: 01008123 #... DCD 16810275 - 0x01008350: 01006e59 Yn.. DCD 16805465 - __tagsym$$used - __fsym_list_thread - 0x01008354: 01008148 H... DCD 16810312 - 0x01008358: 01008154 T... DCD 16810324 - 0x0100835c: 01002c51 Q,.. DCD 16788561 - __tagsym$$used - __fsym_list_sem - 0x01008360: 01008160 `... DCD 16810336 - 0x01008364: 01008169 i... DCD 16810345 - 0x01008368: 01002b19 .+.. DCD 16788249 - __tagsym$$used - __fsym_list_event - 0x0100836c: 01008182 .... DCD 16810370 - 0x01008370: 0100818d .... DCD 16810381 - 0x01008374: 01002261 a".. DCD 16786017 - __tagsym$$used - __fsym_list_mutex - 0x01008378: 010081a2 .... DCD 16810402 - 0x0100837c: 010081ad .... DCD 16810413 - 0x01008380: 01002a0d .*.. DCD 16787981 - __tagsym$$used - __fsym_list_mailbox - 0x01008384: 010081c2 .... DCD 16810434 - 0x01008388: 010081cf .... DCD 16810447 - 0x0100838c: 01002465 e$.. DCD 16786533 - __tagsym$$used - __fsym_list_msgqueue - 0x01008390: 010081e7 .... DCD 16810471 - 0x01008394: 010081f5 .... DCD 16810485 - 0x01008398: 010028c9 .(.. DCD 16787657 - __tagsym$$used - __fsym_list_memheap - 0x0100839c: 01008212 .... DCD 16810514 - 0x010083a0: 0100821f .... DCD 16810527 - 0x010083a4: 01002639 9&.. DCD 16787001 - __tagsym$$used - __fsym_list_mempool - 0x010083a8: 0100823a :... DCD 16810554 - 0x010083ac: 01008247 G... DCD 16810567 - 0x010083b0: 01002755 U'.. DCD 16787285 - __tagsym$$used - __fsym_list_timer - 0x010083b4: 01008262 b... DCD 16810594 - 0x010083b8: 0100826d m... DCD 16810605 - 0x010083bc: 01002e3d =... DCD 16789053 - __tagsym$$used - __fsym_list_device - 0x010083c0: 01008282 .... DCD 16810626 - 0x010083c4: 0100828e .... DCD 16810638 - 0x010083c8: 0100214d M!.. DCD 16785741 - __tagsym$$used - __fsym_list - 0x010083cc: 010082a4 .... DCD 16810660 - 0x010083d0: 010082a9 .... DCD 16810665 - 0x010083d4: 010020e5 . .. DCD 16785637 - FSymTab - __tagsym$$used - __fsym_memheaptrace - 0x010083d8: 010082c5 .... DCD 16810693 - 0x010083dc: 010082d2 .... DCD 16810706 - 0x010083e0: 01002fe1 ./.. DCD 16789473 - FSymTab$$Limit - Region$$Table$$Base - 0x010083e4: 01008404 .... DCD 16811012 - 0x010083e8: 00020000 .... DCD 131072 - 0x010083ec: 00000158 X... DCD 344 - 0x010083f0: 01000a32 2... DCD 16779826 - 0x010083f4: 01008468 h... DCD 16811112 - 0x010083f8: 00020158 X... DCD 131416 - 0x010083fc: 00000db8 .... DCD 3512 - 0x01008400: 01000444 D... DCD 16778308 - Region$$Table$$Limit - -** Section #5 'RW_IRAM1' (SHT_PROGBITS) [SHF_ALLOC + SHF_WRITE] - Size : 100 bytes (alignment 4) - Address: 0x00020000 - - -** Section #6 'RW_IRAM1' (SHT_NOBITS) [SHF_ALLOC + SHF_WRITE] - Size : 3512 bytes (alignment 16) - Address: 0x00020158 - - -** Section #7 '.debug_abbrev' (SHT_PROGBITS) - Size : 1476 bytes - - -** Section #8 '.debug_frame' (SHT_PROGBITS) - Size : 7560 bytes - - -** Section #9 '.debug_info' (SHT_PROGBITS) - Size : 124416 bytes - - -** Section #10 '.debug_line' (SHT_PROGBITS) - Size : 47496 bytes - - -** Section #11 '.debug_loc' (SHT_PROGBITS) - Size : 29452 bytes - - -** Section #12 '.debug_macinfo' (SHT_PROGBITS) - Size : 48792 bytes - - -** Section #13 '.debug_pubnames' (SHT_PROGBITS) - Size : 10286 bytes - - -** Section #14 '.symtab' (SHT_SYMTAB) - Size : 23392 bytes (alignment 4) - String table #15 '.strtab' - Last local symbol no. 1064 - - -** Section #15 '.strtab' (SHT_STRTAB) - Size : 15520 bytes - - -** Section #16 '.note' (SHT_NOTE) - Size : 40 bytes (alignment 4) - - -** Section #17 '.comment' (SHT_PROGBITS) - Size : 42332 bytes - - -** Section #18 '.shstrtab' (SHT_STRTAB) - Size : 184 bytes - - -address size variable name type -0x00020154 0x4 SystickCount tick - -address size variable name type -0x000205a4 0x400 uart0_DMA_buf array[1024] of uint8_t - -address size variable name type -0x000209a4 0x400 uart1_DMA_buf array[1024] of uint8_t - -address size variable name type -0x00020140 0x4 heap_end pointer to heap_mem - -address size variable name type -0x0002013c 0x4 heap_ptr pointer to rt_uint8_t - -address size variable name type -0x00020584 0x20 heap_sem rt_semaphore -0x00020584 0x1c heap_sem.parent rt_ipc_object -0x00020584 0x14 heap_sem.parent.parent rt_object -0x00020584 0x8 heap_sem.parent.parent.name array[8] of char -0x0002058c 0x1 heap_sem.parent.parent.type rt_uint8_t -0x0002058d 0x1 * heap_sem.parent.parent.flag rt_uint8_t -0x00020590 0x8 heap_sem.parent.parent.list rt_list_t -0x00020590 0x4 heap_sem.parent.parent.list.next pointer to rt_list_node -0x00020594 0x4 heap_sem.parent.parent.list.prev pointer to rt_list_node -0x00020598 0x8 heap_sem.parent.suspend_thread rt_list_t -0x00020598 0x4 heap_sem.parent.suspend_thread.next pointer to rt_list_node -0x0002059c 0x4 heap_sem.parent.suspend_thread.prev pointer to rt_list_node -0x000205a0 0x2 heap_sem.value rt_uint16_t -0x000205a2 0x2 heap_sem.reserved rt_uint16_t - -address size variable name type -0x00020144 0x4 lfree pointer to heap_mem - -address size variable name type -0x00020150 0x4 max_mem rt_size_t - -address size variable name type -0x00020148 0x4 mem_size_aligned rt_size_t - -address size variable name type -0x00020138 0x4 rt_free_hook pointer to function - -address size variable name type -0x00020134 0x4 rt_malloc_hook pointer to function - -address size variable name type -0x0002014c 0x4 used_mem rt_size_t - -address size variable name type -0x00020130 0x4 rt_thread_inited_hook pointer to function - -address size variable name type -0x0002012c 0x4 rt_thread_resume_hook pointer to function - -address size variable name type -0x00020128 0x4 rt_thread_suspend_hook pointer to function - -address size variable name type -0x0002011c 0x4 rt_interrupt_enter_hook pointer to function - -address size variable name type -0x00020120 0x4 rt_interrupt_leave_hook pointer to function - -address size variable name type -0x00020124 0x1 rt_interrupt_nest volatile rt_uint8_t - -address size variable name type -0x010083d8 0xc __fsym_memheaptrace const finsh_syscall -0x010083d8 0x4 __fsym_memheaptrace.name pointer to const char -0x010083dc 0x4 __fsym_memheaptrace.desc pointer to const char -0x010083e0 0x4 __fsym_memheaptrace.func syscall_func - -address size variable name type -0x010082d2 0x1e __fsym_memheaptrace_desc array[30] of const char - -address size variable name type -0x010082c5 0xd __fsym_memheaptrace_name array[13] of const char - -address size variable name type -0x00020068 0xa0 _object_container array[10] of rt_object_information - -address size variable name type -0x00020108 0x4 rt_object_attach_hook pointer to function - -address size variable name type -0x0002010c 0x4 rt_object_detach_hook pointer to function - -address size variable name type -0x00020118 0x4 rt_object_put_hook pointer to function - -address size variable name type -0x00020114 0x4 rt_object_take_hook pointer to function - -address size variable name type -0x00020110 0x4 rt_object_trytake_hook pointer to function - -address size variable name type -0x00020054 0x8 _timer_list array[1] of rt_list_t - -address size variable name type -0x0002005c 0x4 rt_timer_enter_hook pointer to function - -address size variable name type -0x00020060 0x4 rt_timer_exit_hook pointer to function - -address size variable name type -0x010076b3 0x100 __lowest_bit_bitmap array[256] of const rt_uint8_t - -address size variable name type -0x00020048 0x4 __rt_errno volatile int - -address size variable name type -0x0002004c 0x4 _console_device rt_device_t - -address size variable name type -0x00020050 0x4 rt_assert_hook pointer to function - -address size variable name type -0x00020044 0x4 rt_tick volatile rt_tick_t - -address size variable name type -0x0002003c 0x8 _rt_thread_defunct rt_list_t -0x0002003c 0x4 _rt_thread_defunct.next pointer to rt_list_node -0x00020040 0x4 _rt_thread_defunct.prev pointer to rt_list_node - -address size variable name type -0x00020374 0x80 idle array[1] of rt_thread - -address size variable name type -0x000204f4 0x10 idle_hook_list array[4] of pointer to function - -address size variable name type -0x000203f4 0x100 rt_thread_stack array[1] of array[256] of rt_uint8_t - -address size variable name type -0x00020030 0x1 rt_current_priority rt_uint8_t - -address size variable name type -0x0002002c 0x4 rt_current_thread pointer to rt_thread - -address size variable name type -0x00020034 0x4 rt_scheduler_hook pointer to function - -address size variable name type -0x00020028 0x2 rt_scheduler_lock_nest rt_int16_t - -address size variable name type -0x00020038 0x4 rt_scheduler_switch_hook pointer to function - -address size variable name type -0x00020274 0x100 rt_thread_priority_table array[32] of rt_list_t - -address size variable name type -0x00020024 0x4 rt_thread_ready_priority_group rt_uint32_t - -address size variable name type -0x01008300 0x4 __rt_init_rti_board_end const init_fn_t - -address size variable name type -0x010082f4 0x4 __rt_init_rti_board_start const init_fn_t - -address size variable name type -0x01008308 0x4 __rt_init_rti_end const init_fn_t - -address size variable name type -0x010082f0 0x4 __rt_init_rti_start const init_fn_t - -address size variable name type -0x0100833c 0xc __fsym_clear const finsh_syscall -0x0100833c 0x4 __fsym_clear.name pointer to const char -0x01008340 0x4 __fsym_clear.desc pointer to const char -0x01008344 0x4 __fsym_clear.func syscall_func - -address size variable name type -0x01008101 0x1a __fsym_clear_desc array[26] of const char - -address size variable name type -0x010080fb 0x6 __fsym_clear_name array[6] of const char - -address size variable name type -0x01008330 0xc __fsym_hello const finsh_syscall -0x01008330 0x4 __fsym_hello.name pointer to const char -0x01008334 0x4 __fsym_hello.desc pointer to const char -0x01008338 0x4 __fsym_hello.func syscall_func - -address size variable name type -0x010080eb 0x10 __fsym_hello_desc array[16] of const char - -address size variable name type -0x010080e5 0x6 __fsym_hello_name array[6] of const char - -address size variable name type -0x010083cc 0xc __fsym_list const finsh_syscall -0x010083cc 0x4 __fsym_list.name pointer to const char -0x010083d0 0x4 __fsym_list.desc pointer to const char -0x010083d4 0x4 __fsym_list.func syscall_func - -address size variable name type -0x010082a9 0x1c __fsym_list_desc array[28] of const char - -address size variable name type -0x010083c0 0xc __fsym_list_device const finsh_syscall -0x010083c0 0x4 __fsym_list_device.name pointer to const char -0x010083c4 0x4 __fsym_list_device.desc pointer to const char -0x010083c8 0x4 __fsym_list_device.func syscall_func - -address size variable name type -0x0100828e 0x16 __fsym_list_device_desc array[22] of const char - -address size variable name type -0x01008282 0xc __fsym_list_device_name array[12] of const char - -address size variable name type -0x0100836c 0xc __fsym_list_event const finsh_syscall -0x0100836c 0x4 __fsym_list_event.name pointer to const char -0x01008370 0x4 __fsym_list_event.desc pointer to const char -0x01008374 0x4 __fsym_list_event.func syscall_func - -address size variable name type -0x0100818d 0x15 __fsym_list_event_desc array[21] of const char - -address size variable name type -0x01008182 0xb __fsym_list_event_name array[11] of const char - -address size variable name type -0x01008384 0xc __fsym_list_mailbox const finsh_syscall -0x01008384 0x4 __fsym_list_mailbox.name pointer to const char -0x01008388 0x4 __fsym_list_mailbox.desc pointer to const char -0x0100838c 0x4 __fsym_list_mailbox.func syscall_func - -address size variable name type -0x010081cf 0x18 __fsym_list_mailbox_desc array[24] of const char - -address size variable name type -0x010081c2 0xd __fsym_list_mailbox_name array[13] of const char - -address size variable name type -0x0100839c 0xc __fsym_list_memheap const finsh_syscall -0x0100839c 0x4 __fsym_list_memheap.name pointer to const char -0x010083a0 0x4 __fsym_list_memheap.desc pointer to const char -0x010083a4 0x4 __fsym_list_memheap.func syscall_func - -address size variable name type -0x0100821f 0x1b __fsym_list_memheap_desc array[27] of const char - -address size variable name type -0x01008212 0xd __fsym_list_memheap_name array[13] of const char - -address size variable name type -0x010083a8 0xc __fsym_list_mempool const finsh_syscall -0x010083a8 0x4 __fsym_list_mempool.name pointer to const char -0x010083ac 0x4 __fsym_list_mempool.desc pointer to const char -0x010083b0 0x4 __fsym_list_mempool.func syscall_func - -address size variable name type -0x01008247 0x1b __fsym_list_mempool_desc array[27] of const char - -address size variable name type -0x0100823a 0xd __fsym_list_mempool_name array[13] of const char - -address size variable name type -0x01008390 0xc __fsym_list_msgqueue const finsh_syscall -0x01008390 0x4 __fsym_list_msgqueue.name pointer to const char -0x01008394 0x4 __fsym_list_msgqueue.desc pointer to const char -0x01008398 0x4 __fsym_list_msgqueue.func syscall_func - -address size variable name type -0x010081f5 0x1d __fsym_list_msgqueue_desc array[29] of const char - -address size variable name type -0x010081e7 0xe __fsym_list_msgqueue_name array[14] of const char - -address size variable name type -0x01008378 0xc __fsym_list_mutex const finsh_syscall -0x01008378 0x4 __fsym_list_mutex.name pointer to const char -0x0100837c 0x4 __fsym_list_mutex.desc pointer to const char -0x01008380 0x4 __fsym_list_mutex.func syscall_func - -address size variable name type -0x010081ad 0x15 __fsym_list_mutex_desc array[21] of const char - -address size variable name type -0x010081a2 0xb __fsym_list_mutex_name array[11] of const char - -address size variable name type -0x010082a4 0x5 __fsym_list_name array[5] of const char - -address size variable name type -0x01008360 0xc __fsym_list_sem const finsh_syscall -0x01008360 0x4 __fsym_list_sem.name pointer to const char -0x01008364 0x4 __fsym_list_sem.desc pointer to const char -0x01008368 0x4 __fsym_list_sem.func syscall_func - -address size variable name type -0x01008169 0x19 __fsym_list_sem_desc array[25] of const char - -address size variable name type -0x01008160 0x9 __fsym_list_sem_name array[9] of const char - -address size variable name type -0x01008354 0xc __fsym_list_thread const finsh_syscall -0x01008354 0x4 __fsym_list_thread.name pointer to const char -0x01008358 0x4 __fsym_list_thread.desc pointer to const char -0x0100835c 0x4 __fsym_list_thread.func syscall_func - -address size variable name type -0x01008154 0xc __fsym_list_thread_desc array[12] of const char - -address size variable name type -0x01008148 0xc __fsym_list_thread_name array[12] of const char - -address size variable name type -0x010083b4 0xc __fsym_list_timer const finsh_syscall -0x010083b4 0x4 __fsym_list_timer.name pointer to const char -0x010083b8 0x4 __fsym_list_timer.desc pointer to const char -0x010083bc 0x4 __fsym_list_timer.func syscall_func - -address size variable name type -0x0100826d 0x15 __fsym_list_timer_desc array[21] of const char - -address size variable name type -0x01008262 0xb __fsym_list_timer_name array[11] of const char - -address size variable name type -0x01008348 0xc __fsym_version const finsh_syscall -0x01008348 0x4 __fsym_version.name pointer to const char -0x0100834c 0x4 __fsym_version.desc pointer to const char -0x01008350 0x4 __fsym_version.func syscall_func - -address size variable name type -0x01008123 0x25 __fsym_version_desc array[37] of const char - -address size variable name type -0x0100811b 0x8 __fsym_version_name array[8] of const char - -address size variable name type -0x01007520 0x64 device_type_str array[25] of const pointer to char - -address size variable name type -0x01008324 0xc __fsym_free const finsh_syscall -0x01008324 0x4 __fsym_free.name pointer to const char -0x01008328 0x4 __fsym_free.desc pointer to const char -0x0100832c 0x4 __fsym_free.func syscall_func - -address size variable name type -0x010080c0 0x25 __fsym_free_desc array[37] of const char - -address size variable name type -0x010080bb 0x5 __fsym_free_name array[5] of const char - -address size variable name type -0x0100830c 0xc __fsym_help const finsh_syscall -0x0100830c 0x4 __fsym_help.name pointer to const char -0x01008310 0x4 __fsym_help.desc pointer to const char -0x01008314 0x4 __fsym_help.func syscall_func - -address size variable name type -0x01008084 0x18 __fsym_help_desc array[24] of const char - -address size variable name type -0x0100807f 0x5 __fsym_help_name array[5] of const char - -address size variable name type -0x01008318 0xc __fsym_ps const finsh_syscall -0x01008318 0x4 __fsym_ps.name pointer to const char -0x0100831c 0x4 __fsym_ps.desc pointer to const char -0x01008320 0x4 __fsym_ps.func syscall_func - -address size variable name type -0x0100809f 0x1c __fsym_ps_desc array[28] of const char - -address size variable name type -0x0100809c 0x3 __fsym_ps_name array[3] of const char - -address size variable name type -0x01008304 0x4 __rt_init_finsh_system_init const init_fn_t - -address size variable name type -0x00020014 0x4 _syscall_table_begin pointer to finsh_syscall - -address size variable name type -0x00020018 0x4 _syscall_table_end pointer to finsh_syscall - -address size variable name type -0x00020020 0x4 finsh_prompt_custom pointer to char - -address size variable name type -0x0002001c 0x4 shell pointer to finsh_shell - -address size variable name type -0x010082fc 0x4 __rt_init_rt_hw_uart_init const init_fn_t - -address size variable name type -0x0002019c 0x54 serial0 rt_serial_device -0x0002019c 0x40 serial0.parent rt_device -0x0002019c 0x14 serial0.parent.parent rt_object -0x0002019c 0x8 serial0.parent.parent.name array[8] of char -0x000201a4 0x1 serial0.parent.parent.type rt_uint8_t -0x000201a5 0x1 * serial0.parent.parent.flag rt_uint8_t -0x000201a8 0x8 serial0.parent.parent.list rt_list_t -0x000201a8 0x4 serial0.parent.parent.list.next pointer to rt_list_node -0x000201ac 0x4 serial0.parent.parent.list.prev pointer to rt_list_node -0x000201b0 0x1 * serial0.parent.type rt_device_class_type -0x000201b2 0x2 serial0.parent.flag rt_uint16_t -0x000201b4 0x2 serial0.parent.open_flag rt_uint16_t -0x000201b6 0x1 serial0.parent.ref_count rt_uint8_t -0x000201b7 0x1 serial0.parent.device_id rt_uint8_t -0x000201b8 0x4 serial0.parent.rx_indicate pointer to function -0x000201bc 0x4 serial0.parent.tx_complete pointer to function -0x000201c0 0x4 serial0.parent.init pointer to function -0x000201c4 0x4 serial0.parent.open pointer to function -0x000201c8 0x4 serial0.parent.close pointer to function -0x000201cc 0x4 serial0.parent.read pointer to function -0x000201d0 0x4 serial0.parent.write pointer to function -0x000201d4 0x4 serial0.parent.control pointer to function -0x000201d8 0x4 serial0.parent.user_data pointer to unknown Type -0x000201dc 0x4 serial0.ops pointer to const rt_uart_ops -0x000201e0 0x8 serial0.config serial_configure -0x000201e0 0x4 serial0.config.baud_rate rt_uint32_t -0x000201e4 0x4(28:4) serial0.config.data_bits rt_uint32_t -0x000201e4 0x4(26:2) serial0.config.stop_bits rt_uint32_t -0x000201e4 0x4(24:2) serial0.config.parity rt_uint32_t -0x000201e4 0x4(23:1) serial0.config.bit_order rt_uint32_t -0x000201e4 0x4(22:1) serial0.config.invert rt_uint32_t -0x000201e4 0x4(6:16) serial0.config.bufsz rt_uint32_t -0x000201e4 0x4(0:6) serial0.config.reserved rt_uint32_t -0x000201e8 0x4 serial0.serial_rx pointer to unknown Type -0x000201ec 0x4 serial0.serial_tx pointer to unknown Type - -address size variable name type -0x00020010 0x2 uart0 yc3121_uart -0x00020010 0x1 uart0.uart UART_TypeDef -0x00020011 0x1 uart0.irq IRQn_Type - -address size variable name type -0x01007420 0x14 yc3121_uart_ops const rt_uart_ops -0x01007420 0x4 yc3121_uart_ops.configure pointer to function -0x01007424 0x4 yc3121_uart_ops.control pointer to function -0x01007428 0x4 yc3121_uart_ops.putc pointer to function -0x0100742c 0x4 yc3121_uart_ops.getc pointer to function -0x01007430 0x4 yc3121_uart_ops.dma_transmit pointer to function - -address size variable name type -0x010082f8 0x4 __rt_init_rt_hw_pin_init const init_fn_t - -address size variable name type -0x01007404 0x1c yc3121_pin_ops const rt_pin_ops -0x01007404 0x4 yc3121_pin_ops.pin_mode pointer to function -0x01007408 0x4 yc3121_pin_ops.pin_write pointer to function -0x0100740c 0x4 yc3121_pin_ops.pin_read pointer to function -0x01007410 0x4 yc3121_pin_ops.pin_attach_irq pointer to unknown Type -0x01007414 0x4 yc3121_pin_ops.pin_detach_irq pointer to function -0x01007418 0x4 yc3121_pin_ops.pin_irq_enable pointer to function -0x0100741c 0x4 yc3121_pin_ops.pin_get pointer to function - -address size variable name type -0x00020158 0x44 _hw_pin rt_device_pin -0x00020158 0x40 _hw_pin.parent rt_device -0x00020158 0x14 _hw_pin.parent.parent rt_object -0x00020158 0x8 _hw_pin.parent.parent.name array[8] of char -0x00020160 0x1 _hw_pin.parent.parent.type rt_uint8_t -0x00020161 0x1 * _hw_pin.parent.parent.flag rt_uint8_t -0x00020164 0x8 _hw_pin.parent.parent.list rt_list_t -0x00020164 0x4 _hw_pin.parent.parent.list.next pointer to rt_list_node -0x00020168 0x4 _hw_pin.parent.parent.list.prev pointer to rt_list_node -0x0002016c 0x1 * _hw_pin.parent.type rt_device_class_type -0x0002016e 0x2 _hw_pin.parent.flag rt_uint16_t -0x00020170 0x2 _hw_pin.parent.open_flag rt_uint16_t -0x00020172 0x1 _hw_pin.parent.ref_count rt_uint8_t -0x00020173 0x1 _hw_pin.parent.device_id rt_uint8_t -0x00020174 0x4 _hw_pin.parent.rx_indicate pointer to function -0x00020178 0x4 _hw_pin.parent.tx_complete pointer to function -0x0002017c 0x4 _hw_pin.parent.init pointer to function -0x00020180 0x4 _hw_pin.parent.open pointer to function -0x00020184 0x4 _hw_pin.parent.close pointer to function -0x00020188 0x4 _hw_pin.parent.read pointer to function -0x0002018c 0x4 _hw_pin.parent.write pointer to function -0x00020190 0x4 _hw_pin.parent.control pointer to function -0x00020194 0x4 _hw_pin.parent.user_data pointer to unknown Type -0x00020198 0x4 _hw_pin.ops pointer to const rt_pin_ops - -address size variable name type -0x00020000 0x4 rt_interrupt_from_thread rt_uint32_t - -address size variable name type -0x00020004 0x4 rt_interrupt_to_thread rt_uint32_t - -address size variable name type -0x00020008 0x4 rt_thread_switch_interrupt_flag rt_uint32_t - -- cgit v1.3.1 From a5f7da8ec1d5764df77458e185b953e286fe2dd7 Mon Sep 17 00:00:00 2001 From: fzxhub Date: Mon, 27 Sep 2021 22:29:53 +0800 Subject: 修改lpc408x中ADC驱动的版权信息 MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit --- bsp/lpc408x/drivers/drv_adc.c | 8 +++++++- bsp/lpc408x/drivers/drv_adc.h | 8 +++++++- 2 files changed, 14 insertions(+), 2 deletions(-) (limited to 'bsp') diff --git a/bsp/lpc408x/drivers/drv_adc.c b/bsp/lpc408x/drivers/drv_adc.c index 0d9501b505..77d5c3c9d9 100644 --- a/bsp/lpc408x/drivers/drv_adc.c +++ b/bsp/lpc408x/drivers/drv_adc.c @@ -1,5 +1,11 @@ /* - * Copyright (c) 2006-2021, fzxhub + * Copyright (c) 2006-2021, RT-Thread Development Team + * + * SPDX-License-Identifier: Apache-2.0 + * + * Change Logs: + * Date Author Notes + * 2021-09-27 fzxhub the first version */ #include diff --git a/bsp/lpc408x/drivers/drv_adc.h b/bsp/lpc408x/drivers/drv_adc.h index 2ef13ad96c..a3e878c417 100644 --- a/bsp/lpc408x/drivers/drv_adc.h +++ b/bsp/lpc408x/drivers/drv_adc.h @@ -1,5 +1,11 @@ /* - * Copyright (c) 2006-2021, fzxhub + * Copyright (c) 2006-2021, RT-Thread Development Team + * + * SPDX-License-Identifier: Apache-2.0 + * + * Change Logs: + * Date Author Notes + * 2021-09-27 fzxhub the first version */ #ifndef DRV_ADC_H__ -- cgit v1.3.1 From ab2e2a9767c72febb17d567693d251ccae207af6 Mon Sep 17 00:00:00 2001 From: aisino2200 Date: Wed, 22 Sep 2021 17:14:47 +0800 Subject: ACM32F4XX bsp add --- bsp/acm32f4xx-nucleo/.ignore_format.yml | 6 + bsp/acm32f4xx-nucleo/Kconfig | 22 + bsp/acm32f4xx-nucleo/README.md | 56 + bsp/acm32f4xx-nucleo/SConscript | 14 + bsp/acm32f4xx-nucleo/SConstruct | 34 + bsp/acm32f4xx-nucleo/applications/SConscript | 11 + bsp/acm32f4xx-nucleo/applications/main.c | 29 + bsp/acm32f4xx-nucleo/drivers/Kconfig | 387 +++ bsp/acm32f4xx-nucleo/drivers/SConscript | 15 + bsp/acm32f4xx-nucleo/drivers/board.c | 74 + bsp/acm32f4xx-nucleo/drivers/board.h | 137 + bsp/acm32f4xx-nucleo/drivers/drv_gpio.c | 479 ++++ bsp/acm32f4xx-nucleo/drivers/drv_uart.c | 663 +++++ .../drivers/linker_scripts/link.icf | 34 + .../drivers/linker_scripts/link.lds | 156 ++ .../drivers/linker_scripts/link.sct | 16 + bsp/acm32f4xx-nucleo/drivers/uart_config.h | 211 ++ .../libraries/CMSIS/cmsis_armclang.h | 1444 ++++++++++ .../libraries/CMSIS/cmsis_compiler.h | 283 ++ bsp/acm32f4xx-nucleo/libraries/CMSIS/cmsis_gcc.h | 2177 +++++++++++++++ .../libraries/CMSIS/cmsis_iccarm.h | 968 +++++++ .../libraries/CMSIS/cmsis_version.h | 39 + bsp/acm32f4xx-nucleo/libraries/CMSIS/core_cm33.h | 2910 ++++++++++++++++++++ bsp/acm32f4xx-nucleo/libraries/CMSIS/mpu_armv8.h | 346 +++ bsp/acm32f4xx-nucleo/libraries/Device/ACM32F4.h | 848 ++++++ .../libraries/Device/Startup_ACM32F4.s | 271 ++ .../libraries/Device/Startup_ACM32F4_iar.s | 362 +++ .../libraries/Device/System_ACM32F4.c | 744 +++++ .../libraries/Device/System_ACM32F4.h | 671 +++++ .../libraries/Device/System_Accelerate.h | 28 + .../libraries/Device/startup_ACM32F4_gcc.s | 344 +++ .../libraries/HAL_Driver/Inc/ACM32Fxx_HAL.h | 207 ++ .../libraries/HAL_Driver/Inc/HAL_ADC.h | 637 +++++ .../libraries/HAL_Driver/Inc/HAL_AES.h | 94 + .../libraries/HAL_Driver/Inc/HAL_CAN.h | 394 +++ .../libraries/HAL_Driver/Inc/HAL_COMP.h | 216 ++ .../libraries/HAL_Driver/Inc/HAL_CRC.h | 154 ++ .../libraries/HAL_Driver/Inc/HAL_DAC.h | 589 ++++ .../libraries/HAL_Driver/Inc/HAL_DMA.h | 297 ++ .../libraries/HAL_Driver/Inc/HAL_EFlash.h | 45 + .../libraries/HAL_Driver/Inc/HAL_EFlash_EX.h | 26 + .../libraries/HAL_Driver/Inc/HAL_EXTI.h | 166 ++ .../libraries/HAL_Driver/Inc/HAL_FAU.h | 170 ++ .../libraries/HAL_Driver/Inc/HAL_FSUSB.h | 105 + .../libraries/HAL_Driver/Inc/HAL_GPIO.h | 214 ++ .../libraries/HAL_Driver/Inc/HAL_HRNG.h | 53 + .../libraries/HAL_Driver/Inc/HAL_I2C.h | 253 ++ .../libraries/HAL_Driver/Inc/HAL_I2S.h | 248 ++ .../libraries/HAL_Driver/Inc/HAL_IWDT.h | 56 + .../libraries/HAL_Driver/Inc/HAL_LPUART.h | 173 ++ .../libraries/HAL_Driver/Inc/HAL_OPA.h | 187 ++ .../libraries/HAL_Driver/Inc/HAL_RTC.h | 685 +++++ .../libraries/HAL_Driver/Inc/HAL_SHA1.h | 77 + .../libraries/HAL_Driver/Inc/HAL_SHA256.h | 77 + .../libraries/HAL_Driver/Inc/HAL_SPI.h | 301 ++ .../libraries/HAL_Driver/Inc/HAL_TIMER.h | 520 ++++ .../libraries/HAL_Driver/Inc/HAL_TIMER_EX.h | 128 + .../libraries/HAL_Driver/Inc/HAL_UART.h | 305 ++ .../libraries/HAL_Driver/Inc/HAL_UART_EX.h | 36 + .../libraries/HAL_Driver/Inc/HAL_WDT.h | 118 + .../libraries/HAL_Driver/Src/HAL_ADC.c | 913 ++++++ .../libraries/HAL_Driver/Src/HAL_CAN.c | 732 +++++ .../libraries/HAL_Driver/Src/HAL_COMP.c | 320 +++ .../libraries/HAL_Driver/Src/HAL_CRC.c | 54 + .../libraries/HAL_Driver/Src/HAL_DAC.c | 828 ++++++ .../libraries/HAL_Driver/Src/HAL_DMA.c | 422 +++ .../libraries/HAL_Driver/Src/HAL_EFlash.c | 114 + .../libraries/HAL_Driver/Src/HAL_EXTI.c | 184 ++ .../libraries/HAL_Driver/Src/HAL_FSUSB.c | 372 +++ .../libraries/HAL_Driver/Src/HAL_GPIO.c | 703 +++++ .../libraries/HAL_Driver/Src/HAL_I2C.c | 1143 ++++++++ .../libraries/HAL_Driver/Src/HAL_I2S.c | 491 ++++ .../libraries/HAL_Driver/Src/HAL_IWDT.c | 72 + .../libraries/HAL_Driver/Src/HAL_LPUART.c | 452 +++ .../libraries/HAL_Driver/Src/HAL_OPA.c | 329 +++ .../libraries/HAL_Driver/Src/HAL_RTC.c | 485 ++++ .../libraries/HAL_Driver/Src/HAL_SPI.c | 1080 ++++++++ .../libraries/HAL_Driver/Src/HAL_TIMER.c | 1553 +++++++++++ .../libraries/HAL_Driver/Src/HAL_TIMER_EX.c | 160 ++ .../libraries/HAL_Driver/Src/HAL_UART.c | 904 ++++++ .../libraries/HAL_Driver/Src/HAL_UART_EX.c | 247 ++ .../libraries/HAL_Driver/Src/HAL_WDT.c | 110 + bsp/acm32f4xx-nucleo/libraries/SConscript | 35 + bsp/acm32f4xx-nucleo/project.uvoptx | 985 +++++++ bsp/acm32f4xx-nucleo/project.uvprojx | 693 +++++ bsp/acm32f4xx-nucleo/rtconfig.h | 215 ++ bsp/acm32f4xx-nucleo/rtconfig.py | 151 + bsp/acm32f4xx-nucleo/template.uvoptx | 321 +++ bsp/acm32f4xx-nucleo/template.uvprojx | 401 +++ 89 files changed, 34779 insertions(+) create mode 100644 bsp/acm32f4xx-nucleo/.ignore_format.yml create mode 100644 bsp/acm32f4xx-nucleo/Kconfig create mode 100644 bsp/acm32f4xx-nucleo/README.md create mode 100644 bsp/acm32f4xx-nucleo/SConscript create mode 100644 bsp/acm32f4xx-nucleo/SConstruct create mode 100644 bsp/acm32f4xx-nucleo/applications/SConscript create mode 100644 bsp/acm32f4xx-nucleo/applications/main.c create mode 100644 bsp/acm32f4xx-nucleo/drivers/Kconfig create mode 100644 bsp/acm32f4xx-nucleo/drivers/SConscript create mode 100644 bsp/acm32f4xx-nucleo/drivers/board.c create mode 100644 bsp/acm32f4xx-nucleo/drivers/board.h create mode 100644 bsp/acm32f4xx-nucleo/drivers/drv_gpio.c create mode 100644 bsp/acm32f4xx-nucleo/drivers/drv_uart.c create mode 100644 bsp/acm32f4xx-nucleo/drivers/linker_scripts/link.icf create mode 100644 bsp/acm32f4xx-nucleo/drivers/linker_scripts/link.lds create mode 100644 bsp/acm32f4xx-nucleo/drivers/linker_scripts/link.sct create mode 100644 bsp/acm32f4xx-nucleo/drivers/uart_config.h create mode 100644 bsp/acm32f4xx-nucleo/libraries/CMSIS/cmsis_armclang.h create mode 100644 bsp/acm32f4xx-nucleo/libraries/CMSIS/cmsis_compiler.h create mode 100644 bsp/acm32f4xx-nucleo/libraries/CMSIS/cmsis_gcc.h create mode 100644 bsp/acm32f4xx-nucleo/libraries/CMSIS/cmsis_iccarm.h create mode 100644 bsp/acm32f4xx-nucleo/libraries/CMSIS/cmsis_version.h create mode 100644 bsp/acm32f4xx-nucleo/libraries/CMSIS/core_cm33.h create mode 100644 bsp/acm32f4xx-nucleo/libraries/CMSIS/mpu_armv8.h create mode 100644 bsp/acm32f4xx-nucleo/libraries/Device/ACM32F4.h create mode 100644 bsp/acm32f4xx-nucleo/libraries/Device/Startup_ACM32F4.s create mode 100644 bsp/acm32f4xx-nucleo/libraries/Device/Startup_ACM32F4_iar.s create mode 100644 bsp/acm32f4xx-nucleo/libraries/Device/System_ACM32F4.c create mode 100644 bsp/acm32f4xx-nucleo/libraries/Device/System_ACM32F4.h create mode 100644 bsp/acm32f4xx-nucleo/libraries/Device/System_Accelerate.h create mode 100644 bsp/acm32f4xx-nucleo/libraries/Device/startup_ACM32F4_gcc.s create mode 100644 bsp/acm32f4xx-nucleo/libraries/HAL_Driver/Inc/ACM32Fxx_HAL.h create mode 100644 bsp/acm32f4xx-nucleo/libraries/HAL_Driver/Inc/HAL_ADC.h create mode 100644 bsp/acm32f4xx-nucleo/libraries/HAL_Driver/Inc/HAL_AES.h create mode 100644 bsp/acm32f4xx-nucleo/libraries/HAL_Driver/Inc/HAL_CAN.h create mode 100644 bsp/acm32f4xx-nucleo/libraries/HAL_Driver/Inc/HAL_COMP.h create mode 100644 bsp/acm32f4xx-nucleo/libraries/HAL_Driver/Inc/HAL_CRC.h create mode 100644 bsp/acm32f4xx-nucleo/libraries/HAL_Driver/Inc/HAL_DAC.h create mode 100644 bsp/acm32f4xx-nucleo/libraries/HAL_Driver/Inc/HAL_DMA.h create mode 100644 bsp/acm32f4xx-nucleo/libraries/HAL_Driver/Inc/HAL_EFlash.h create mode 100644 bsp/acm32f4xx-nucleo/libraries/HAL_Driver/Inc/HAL_EFlash_EX.h create mode 100644 bsp/acm32f4xx-nucleo/libraries/HAL_Driver/Inc/HAL_EXTI.h create mode 100644 bsp/acm32f4xx-nucleo/libraries/HAL_Driver/Inc/HAL_FAU.h create mode 100644 bsp/acm32f4xx-nucleo/libraries/HAL_Driver/Inc/HAL_FSUSB.h create mode 100644 bsp/acm32f4xx-nucleo/libraries/HAL_Driver/Inc/HAL_GPIO.h create mode 100644 bsp/acm32f4xx-nucleo/libraries/HAL_Driver/Inc/HAL_HRNG.h create mode 100644 bsp/acm32f4xx-nucleo/libraries/HAL_Driver/Inc/HAL_I2C.h create mode 100644 bsp/acm32f4xx-nucleo/libraries/HAL_Driver/Inc/HAL_I2S.h create mode 100644 bsp/acm32f4xx-nucleo/libraries/HAL_Driver/Inc/HAL_IWDT.h create mode 100644 bsp/acm32f4xx-nucleo/libraries/HAL_Driver/Inc/HAL_LPUART.h create mode 100644 bsp/acm32f4xx-nucleo/libraries/HAL_Driver/Inc/HAL_OPA.h create mode 100644 bsp/acm32f4xx-nucleo/libraries/HAL_Driver/Inc/HAL_RTC.h create mode 100644 bsp/acm32f4xx-nucleo/libraries/HAL_Driver/Inc/HAL_SHA1.h create mode 100644 bsp/acm32f4xx-nucleo/libraries/HAL_Driver/Inc/HAL_SHA256.h create mode 100644 bsp/acm32f4xx-nucleo/libraries/HAL_Driver/Inc/HAL_SPI.h create mode 100644 bsp/acm32f4xx-nucleo/libraries/HAL_Driver/Inc/HAL_TIMER.h create mode 100644 bsp/acm32f4xx-nucleo/libraries/HAL_Driver/Inc/HAL_TIMER_EX.h create mode 100644 bsp/acm32f4xx-nucleo/libraries/HAL_Driver/Inc/HAL_UART.h create mode 100644 bsp/acm32f4xx-nucleo/libraries/HAL_Driver/Inc/HAL_UART_EX.h create mode 100644 bsp/acm32f4xx-nucleo/libraries/HAL_Driver/Inc/HAL_WDT.h create mode 100644 bsp/acm32f4xx-nucleo/libraries/HAL_Driver/Src/HAL_ADC.c create mode 100644 bsp/acm32f4xx-nucleo/libraries/HAL_Driver/Src/HAL_CAN.c create mode 100644 bsp/acm32f4xx-nucleo/libraries/HAL_Driver/Src/HAL_COMP.c create mode 100644 bsp/acm32f4xx-nucleo/libraries/HAL_Driver/Src/HAL_CRC.c create mode 100644 bsp/acm32f4xx-nucleo/libraries/HAL_Driver/Src/HAL_DAC.c create mode 100644 bsp/acm32f4xx-nucleo/libraries/HAL_Driver/Src/HAL_DMA.c create mode 100644 bsp/acm32f4xx-nucleo/libraries/HAL_Driver/Src/HAL_EFlash.c create mode 100644 bsp/acm32f4xx-nucleo/libraries/HAL_Driver/Src/HAL_EXTI.c create mode 100644 bsp/acm32f4xx-nucleo/libraries/HAL_Driver/Src/HAL_FSUSB.c create mode 100644 bsp/acm32f4xx-nucleo/libraries/HAL_Driver/Src/HAL_GPIO.c create mode 100644 bsp/acm32f4xx-nucleo/libraries/HAL_Driver/Src/HAL_I2C.c create mode 100644 bsp/acm32f4xx-nucleo/libraries/HAL_Driver/Src/HAL_I2S.c create mode 100644 bsp/acm32f4xx-nucleo/libraries/HAL_Driver/Src/HAL_IWDT.c create mode 100644 bsp/acm32f4xx-nucleo/libraries/HAL_Driver/Src/HAL_LPUART.c create mode 100644 bsp/acm32f4xx-nucleo/libraries/HAL_Driver/Src/HAL_OPA.c create mode 100644 bsp/acm32f4xx-nucleo/libraries/HAL_Driver/Src/HAL_RTC.c create mode 100644 bsp/acm32f4xx-nucleo/libraries/HAL_Driver/Src/HAL_SPI.c create mode 100644 bsp/acm32f4xx-nucleo/libraries/HAL_Driver/Src/HAL_TIMER.c create mode 100644 bsp/acm32f4xx-nucleo/libraries/HAL_Driver/Src/HAL_TIMER_EX.c create mode 100644 bsp/acm32f4xx-nucleo/libraries/HAL_Driver/Src/HAL_UART.c create mode 100644 bsp/acm32f4xx-nucleo/libraries/HAL_Driver/Src/HAL_UART_EX.c create mode 100644 bsp/acm32f4xx-nucleo/libraries/HAL_Driver/Src/HAL_WDT.c create mode 100644 bsp/acm32f4xx-nucleo/libraries/SConscript create mode 100644 bsp/acm32f4xx-nucleo/project.uvoptx create mode 100644 bsp/acm32f4xx-nucleo/project.uvprojx create mode 100644 bsp/acm32f4xx-nucleo/rtconfig.h create mode 100644 bsp/acm32f4xx-nucleo/rtconfig.py create mode 100644 bsp/acm32f4xx-nucleo/template.uvoptx create mode 100644 bsp/acm32f4xx-nucleo/template.uvprojx (limited to 'bsp') diff --git a/bsp/acm32f4xx-nucleo/.ignore_format.yml b/bsp/acm32f4xx-nucleo/.ignore_format.yml new file mode 100644 index 0000000000..29b7c31648 --- /dev/null +++ b/bsp/acm32f4xx-nucleo/.ignore_format.yml @@ -0,0 +1,6 @@ +# files format check exclude path, please follow the instructions below to modify; +# If you need to exclude an entire folder, add the folder path in dir_path; +# If you need to exclude a file, add the path to the file in file_path. + +dir_path: +- libraries diff --git a/bsp/acm32f4xx-nucleo/Kconfig b/bsp/acm32f4xx-nucleo/Kconfig new file mode 100644 index 0000000000..3053a7980a --- /dev/null +++ b/bsp/acm32f4xx-nucleo/Kconfig @@ -0,0 +1,22 @@ +mainmenu "RT-Thread Project Configuration" + +config BSP_DIR + string + option env="BSP_ROOT" + default "." + +config RTT_DIR + string + option env="RTT_ROOT" + default "../.." + +config PKGS_DIR + string + option env="PKGS_ROOT" + default "packages" + +source "$RTT_DIR/Kconfig" +source "$PKGS_DIR/Kconfig" + +source "$BSP_DIR/drivers/Kconfig" + diff --git a/bsp/acm32f4xx-nucleo/README.md b/bsp/acm32f4xx-nucleo/README.md new file mode 100644 index 0000000000..0c4d6243d2 --- /dev/null +++ b/bsp/acm32f4xx-nucleo/README.md @@ -0,0 +1,56 @@ +# acm32f0x0板级支持包 + +## 1. 简介 + +ACM32F4xx芯片是上海爱信诺航芯电子科技有限公司(后续简称上海航芯)一系列支持多种低功耗模式的通用MCU。包括如下硬件特性： + +|--------------------------|--------------------| +| 硬件 | 描述 | +| -------------------------|--------------------| +|芯片型号 | ACM32F4XX系列 | +|CPU | ARM Cortex-M33 | +|主频 | 180MHz | +|片内SRAM | 192K | +|片内Flash | 512K | +|--------------------------|--------------------| + +具体型号及资源请参考上海航芯官方网站[ACM32F4](www.aisinochip.com/index.php/product/child1/id/219.html)。 + +## 2. 编译说明 + +推荐使用[env工具][1]，可以在console下进入到`bsp/acm32f4xx-nucleo`目录中，运行以下命令： + +`scons` + +来编译这个板级支持包。如果编译正确无误，会产生rtthread.elf、rtthread.bin文件。其中rtthread.bin需要烧写到设备中进行运行。 + +也可以通过`scons --target=mdk5`生成keil工程，再使用keil进行编译。 + +## 3. 烧写及执行 + +开发板的使用请参考上海航芯官方网站相应型号的[开发工具](www.aisinochip.com/index.php/product/detail/id/25.html)。 + +### 3.1 运行结果 + +如果编译 & 烧写无误，当复位设备后，会在串口上看到RT-Thread的启动logo信息： + +## 4. 驱动支持情况及计划 + +| **片上外设** | **支持情况** | **备注** | +| ------------- | ------------ | ------------------------------------- | +| GPIO | 支持 | PA0, PA1... PF4 ---> PIN: 0, 1...83 | +| UART | 支持 | UART1/UART2 | +| LED | 支持 | LED1 | + +## 5. 联系人信息 + +维护人：AisinoChip < xiangfeng.liu@aisinochip.com > + +## 6. 参考 + +* 板子[数据手册][2] +* 芯片[数据手册][3] + + [1]: https://www.rt-thread.org/page/download.html + [2]: www.aisinochip.com/index.php/product/detail/id/50.html + [3]: www.aisinochip.com/index.php/product/detail/id/50.html diff --git a/bsp/acm32f4xx-nucleo/SConscript b/bsp/acm32f4xx-nucleo/SConscript new file mode 100644 index 0000000000..744d8d7821 --- /dev/null +++ b/bsp/acm32f4xx-nucleo/SConscript @@ -0,0 +1,14 @@ +# for module compiling +import os +from building import * + +cwd = GetCurrentDir() +objs = [] +list = os.listdir(cwd) + +for d in list: + path = os.path.join(cwd, d) + if os.path.isfile(os.path.join(path, 'SConscript')): + objs = objs + SConscript(os.path.join(d, 'SConscript')) + +Return('objs') diff --git a/bsp/acm32f4xx-nucleo/SConstruct b/bsp/acm32f4xx-nucleo/SConstruct new file mode 100644 index 0000000000..8b56517bc3 --- /dev/null +++ b/bsp/acm32f4xx-nucleo/SConstruct @@ -0,0 +1,34 @@ +import os +import sys +import rtconfig + +if os.getenv('RTT_ROOT'): + RTT_ROOT = os.getenv('RTT_ROOT') +else: + RTT_ROOT = os.path.normpath(os.getcwd() + '/../..') + +sys.path = sys.path + [os.path.join(RTT_ROOT, 'tools')] +from building import * + +TARGET = 'rtthread_acm32f4xx.' + rtconfig.TARGET_EXT + +env = Environment(tools = ['mingw'], + AS = rtconfig.AS, ASFLAGS = rtconfig.AFLAGS, + CC = rtconfig.CC, CCFLAGS = rtconfig.CFLAGS, + AR = rtconfig.AR, ARFLAGS = '-rc', + LINK = rtconfig.LINK, LINKFLAGS = rtconfig.LFLAGS) +env.PrependENVPath('PATH', rtconfig.EXEC_PATH) + +if rtconfig.PLATFORM == 'iar': + env.Replace(CCCOM = ['$CC $CCFLAGS $CPPFLAGS $_CPPDEFFLAGS $_CPPINCFLAGS -o $TARGET $SOURCES']) + env.Replace(ARFLAGS = ['']) + env.Replace(LINKCOM = ['$LINK $SOURCES $LINKFLAGS -o $TARGET --map project.map']) + +Export('RTT_ROOT') +Export('rtconfig') + +# prepare building environment +objs = PrepareBuilding(env, RTT_ROOT, has_libcpu=False) + +# make a building +DoBuilding(TARGET, objs) diff --git a/bsp/acm32f4xx-nucleo/applications/SConscript b/bsp/acm32f4xx-nucleo/applications/SConscript new file mode 100644 index 0000000000..fc2501998c --- /dev/null +++ b/bsp/acm32f4xx-nucleo/applications/SConscript @@ -0,0 +1,11 @@ +Import('RTT_ROOT') +Import('rtconfig') +from building import * + +cwd = os.path.join(str(Dir('#')), 'applications') +src = Glob('*.c') +CPPPATH = [cwd, str(Dir('#'))] + +group = DefineGroup('Applications', src, depend = [''], CPPPATH = CPPPATH) + +Return('group') diff --git a/bsp/acm32f4xx-nucleo/applications/main.c b/bsp/acm32f4xx-nucleo/applications/main.c new file mode 100644 index 0000000000..cc4acc7fc6 --- /dev/null +++ b/bsp/acm32f4xx-nucleo/applications/main.c @@ -0,0 +1,29 @@ +/* + * Copyright (c) 2006-2021, RT-Thread Development Team + * + * SPDX-License-Identifier: Apache-2.0 + * + * Change Logs: + * Date Author Notes + * 2021-09-17 AisinoChip the first version + */ + +#include +#include +#include "board.h" +#include + +#define LED_PIN_NUM 83 /* PF3 */ + +int main(void) +{ + rt_pin_mode(LED_PIN_NUM, PIN_MODE_OUTPUT); + + while (1) + { + rt_pin_write(LED_PIN_NUM, PIN_LOW); + rt_thread_delay(RT_TICK_PER_SECOND / 2); + rt_pin_write(LED_PIN_NUM, PIN_HIGH); + rt_thread_delay(RT_TICK_PER_SECOND / 2); + } +} diff --git a/bsp/acm32f4xx-nucleo/drivers/Kconfig b/bsp/acm32f4xx-nucleo/drivers/Kconfig new file mode 100644 index 0000000000..a760743f7b --- /dev/null +++ b/bsp/acm32f4xx-nucleo/drivers/Kconfig @@ -0,0 +1,387 @@ +menu "Hardware Drivers Config" + +choice + prompt "select chip type" + default SOC_ACM32F403RET7 + + config SOC_ACM32F403KCU7 + bool "SOC_ACM32F403KCU7" + select RT_USING_COMPONENTS_INIT + select RT_USING_USER_MAIN + help + Refer to ACM32F403 DataSheet + + config SOC_ACM32F403KEU7 + bool "SOC_ACM32F403KEU7" + select RT_USING_COMPONENTS_INIT + select RT_USING_USER_MAIN + help + Refer to ACM32F403 DataSheet + + config SOC_ACM32F403CCT7 + bool "SOC_ACM32F403CCT7" + select RT_USING_COMPONENTS_INIT + select RT_USING_USER_MAIN + help + Refer to ACM32F403 DataSheet + + config SOC_ACM32F403CET7 + bool "SOC_ACM32F403CET7" + select RT_USING_COMPONENTS_INIT + select RT_USING_USER_MAIN + help + Refer to ACM32F403 DataSheet + + config SOC_ACM32F403RCT7 + bool "SOC_ACM32F403RCT7" + select RT_USING_COMPONENTS_INIT + select RT_USING_USER_MAIN + help + Refer to ACM32F403 DataSheet + + config SOC_ACM32F403RET7 + bool "SOC_ACM32F403RET7" + select RT_USING_COMPONENTS_INIT + select RT_USING_USER_MAIN + help + Refer to ACM32F403 DataSheet + + config SOC_ACM32F403VCT7 + bool "SOC_ACM32F403VCT7" + select RT_USING_COMPONENTS_INIT + select RT_USING_USER_MAIN + help + Refer to ACM32F403 DataSheet + + config SOC_ACM32F403VET7 + bool "SOC_ACM32F403VET7" + select RT_USING_COMPONENTS_INIT + select RT_USING_USER_MAIN + help + Refer to ACM32F403 DataSheet +endchoice + +menu "ACM32F403RET7" + depends on SOC_ACM32F403RET7 + + config SOC_SRAM_START_ADDR + hex "sram start address" + default 0x20000000 + + config SOC_SRAM_SIZE + hex "sram size(KBytes)" + default 0xC0 + + config SOC_FLASH_START_ADDR + hex "EFlash Start Address" + default 0x00000000 + + config SOC_FLASH_SIZE + hex "EFlash Size(KBytes)" + default 0x8000 +endmenu + +menu "Onboard Peripheral Drivers" + +endmenu + +menu "On-chip Peripheral Drivers" + + menu "Hardware GPIO" + config BSP_USING_GPIO1 + bool "Enable GPIOAB" + default y + select RT_USING_PIN + config BSP_USING_GPIO2 + bool "Enable GPIOCD" + default y + select RT_USING_PIN + config BSP_USING_GPIO3 + bool "Enable GPIOEF" + default y + select RT_USING_PIN + endmenu + + config BSP_USING_ADC + bool "Enable ADC" + select RT_USING_ADC + default n + + config BSP_USING_DAC + bool "Enable DAC" + select RT_USING_DAC + default n + + menu "Hardware UART" + config BSP_USING_UART1 + bool "Enable UART1 (PA9/PA10)" + default y + select RT_USING_SERIAL + + config BSP_USING_UART2 + bool "Enable UART2 (PA2/PA3)" + default y + select RT_USING_SERIAL + + if BSP_USING_UART2 + config BSP_UART2_RX_USING_DMA + bool "Enable UART2 RX DMA" + depends on BSP_USING_UART2 + select RT_SERIAL_USING_DMA + default n + + config BSP_UART2_TX_USING_DMA + bool "Enable UART2 TX DMA" + depends on BSP_USING_UART2 + select RT_SERIAL_USING_DMA + default n + endif + + config BSP_USING_UART3 + bool "Enable UART3 (PC4/PC5)" + default n + select RT_USING_SERIAL + + if BSP_USING_UART3 + config BSP_UART3_RX_USING_DMA + bool "Enable UART3 RX DMA" + depends on BSP_USING_UART3 + select RT_SERIAL_USING_DMA + default n + + config BSP_UART3_TX_USING_DMA + bool "Enable UART3 TX DMA" + depends on BSP_USING_UART3 + select RT_SERIAL_USING_DMA + default n + endif + + config BSP_USING_UART4 + bool "Enable UART4 (PC11/PC10)" + default n + select RT_USING_SERIAL + + if BSP_USING_UART4 + config BSP_UART4_RX_USING_DMA + bool "Enable UART4 RX DMA" + depends on BSP_USING_UART4 + select RT_SERIAL_USING_DMA + default n + + config BSP_UART4_TX_USING_DMA + bool "Enable UART4 TX DMA" + depends on BSP_USING_UART4 + select RT_SERIAL_USING_DMA + default n + endif + endmenu + + config BSP_USING_RTC + bool "Enable RTC" + select RT_USING_RTC + default n + + config BSP_USING_LPUART + bool "Enable LPUART" + select RT_USING_UART + default n + + menu "Hardware I2C" + config BSP_USING_I2C1 + bool "Enable I2C1" + default n + select RT_USING_I2C + config BSP_USING_I2C2 + bool "Enable I2C2" + default n + select RT_USING_I2C + endmenu + + menu "Hardware I2S" + config BSP_USING_I2S1 + bool "Enable I2S1" + default n + select RT_USING_I2S + endmenu + + menu "Hardware CAN" + config BSP_USING_CAN1 + bool "Enable CAN1" + default n + select RT_USING_CAN + config BSP_USING_CAN2 + bool "Enable CAN2" + default n + select RT_USING_CAN + endmenu + + menu "Hardware TIMER" + config BSP_USING_TIM1 + bool "Enable Timer1" + default n + select RT_USING_HWTIMER + config BSP_USING_TIM2 + bool "Enable Timer2" + default n + select RT_USING_HWTIMER + config BSP_USING_TIM3 + bool "Enable Timer3" + default n + select RT_USING_HWTIMER + config BSP_USING_TIM4 + bool "Enable Timer4" + default n + select RT_USING_HWTIMER + config BSP_USING_TIM6 + bool "Enable Timer6" + default n + select RT_USING_HWTIMER + config BSP_USING_TIM7 + bool "Enable Timer7" + default n + select RT_USING_HWTIMER + config BSP_USING_TIM14 + bool "Enable Timer14" + default n + select RT_USING_HWTIMER + config BSP_USING_TIM15 + bool "Enable Timer15" + default n + select RT_USING_HWTIMER + config BSP_USING_TIM16 + bool "Enable Timer16" + default n + select RT_USING_HWTIMER + config BSP_USING_TIM17 + bool "Enable Timer17" + default n + select RT_USING_HWTIMER + endmenu + + menu "Hardware WDT" + config BSP_USING_WDT + bool "Enable Watch Dog Timer" + default n + select RT_USING_WDT + config BSP_USING_IWDT + bool "Enable Independent Watch Dog Timer" + default n + select RT_USING_WDT + endmenu + + config BSP_USING_LCD + bool "Enable LCD" + default n + + menu "Hardware SPI" + config BSP_USING_SPI1 + bool "Enable SPI1" + select RT_USING_SPI + default n + + if BSP_USING_SPI1 + config BSP_SPI1_RX_USING_DMA + bool "Enable SPI1 RX DMA" + default n + + config BSP_SPI1_TX_USING_DMA + bool "Enable SPI1 TX DMA" + default n + endif + + config BSP_USING_SPI2 + bool "Enable SPI2" + select RT_USING_SPI + default n + + if BSP_USING_SPI2 + config BSP_SPI2_RX_USING_DMA + bool "Enable SPI2 RX DMA" + default n + + config BSP_SPI2_TX_USING_DMA + bool "Enable SPI2 TX DMA" + default n + endif + + config BSP_USING_SPI3 + bool "Enable SPI3" + select RT_USING_SPI + default n + + if BSP_USING_SPI3 + config BSP_SPI3_RX_USING_DMA + bool "Enable SPI3 RX DMA" + default n + + config BSP_SPI3_TX_USING_DMA + bool "Enable SPI3 TX DMA" + default n + endif + + config BSP_USING_SPI4 + bool "Enable SPI4" + select RT_USING_SPI + default n + + if BSP_USING_SPI4 + config BSP_SPI4_RX_USING_DMA + bool "Enable SPI4 RX DMA" + default n + + config BSP_SPI4_TX_USING_DMA + bool "Enable SPI4 TX DMA" + default n + endif + endmenu + + menu "Hardware CRYPTO" + config BSP_USING_CRC + select RT_HWCRYPTO_USING_CRC + bool "Enable CRC" + default n + select RT_USING_HWCRYPTO + config BSP_USING_AES + select RT_HWCRYPTO_USING_AES + bool "Enable AES" + default n + select RT_USING_HWCRYPTO + + config BSP_USING_HRNG + select RT_HWCRYPTO_USING_RNG + bool "Enable HRNG" + default n + select RT_USING_HWCRYPTO + endmenu + + config BSP_USING_CMP + bool "Enable Analog Voltage Comparer" + default n + + config BSP_USING_OPA + bool "Enable Operational Amplifier" + default n + + config BSP_USING_TKEY + bool "Enable Touch Key" + select RT_USING_TOUCH + default n + + config BSP_USING_RPMU + bool "Enable RTC PMU" + select RT_USING_PM + default n + + config BSP_USING_USBD + bool "Enable USB Device" + select RT_USING_USB + default n + +endmenu + +menu "Board extended module Drivers" + +endmenu + +endmenu + diff --git a/bsp/acm32f4xx-nucleo/drivers/SConscript b/bsp/acm32f4xx-nucleo/drivers/SConscript new file mode 100644 index 0000000000..af6c70499f --- /dev/null +++ b/bsp/acm32f4xx-nucleo/drivers/SConscript @@ -0,0 +1,15 @@ +Import('RTT_ROOT') +Import('rtconfig') +from building import * + +cwd = GetCurrentDir() +src = Glob('*.c') +CPPPATH = [cwd] + +#remove other no use files +#SrcRemove(src, '*.c') + +group = DefineGroup('Drivers', src, depend = [''], CPPPATH = CPPPATH) + +Return('group') + diff --git a/bsp/acm32f4xx-nucleo/drivers/board.c b/bsp/acm32f4xx-nucleo/drivers/board.c new file mode 100644 index 0000000000..050db7656b --- /dev/null +++ b/bsp/acm32f4xx-nucleo/drivers/board.c @@ -0,0 +1,74 @@ +/* + * Copyright (c) 2006-2021, RT-Thread Development Team + * + * SPDX-License-Identifier: Apache-2.0 + * + * Change Logs: + * Date Author Notes + * 2021-08-25 AisinoChip first implementation + */ + +#include +#include +#include "board.h" +#include + +#define SOC_SRAM_END_ADDR (SOC_SRAM_START_ADDR+SOC_SRAM_SIZE*1024) + +extern int rt_application_init(void); + +#if defined(__CC_ARM) || defined(__CLANG_ARM) + extern int Image$$RW_IRAM1$$ZI$$Limit; +#elif __ICCARM__ + #pragma section="HEAP" +#else + extern int __bss_end; +#endif + +extern void rt_hw_uart_init(void); + +/** + * This is the timer interrupt service routine. + * + */ +void SysTick_Handler(void) +{ + /* enter interrupt */ + rt_interrupt_enter(); + + rt_tick_increase(); + + /* leave interrupt */ + rt_interrupt_leave(); +} + +/** + * This function will initial EVB board. + */ +void rt_hw_board_init(void) +{ + /* system init, clock, NVIC */ + System_Init(); + + /* Configure the SysTick */ + SysTick_Config(System_Get_SystemClock() / RT_TICK_PER_SECOND); + + rt_hw_uart_init(); + rt_console_set_device(RT_CONSOLE_DEVICE_NAME); + +#ifdef RT_USING_HEAP +#if defined(__CC_ARM) || defined(__CLANG_ARM) + rt_system_heap_init((void *)&Image$$RW_IRAM1$$ZI$$Limit, (void *)SOC_SRAM_END_ADDR); +#elif __ICCARM__ + rt_system_heap_init(__segment_end("HEAP"), (void *)SOC_SRAM_END_ADDR); +#else + /* init memory system */ + rt_system_heap_init((void *)&__bss_end, (void *)SOC_SRAM_END_ADDR); +#endif +#endif /* RT_USING_HEAP */ + +#ifdef RT_USING_COMPONENTS_INIT + rt_components_board_init(); +#endif +} + diff --git a/bsp/acm32f4xx-nucleo/drivers/board.h b/bsp/acm32f4xx-nucleo/drivers/board.h new file mode 100644 index 0000000000..48c75f9176 --- /dev/null +++ b/bsp/acm32f4xx-nucleo/drivers/board.h @@ -0,0 +1,137 @@ +/* + * Copyright (c) 2006-2021, RT-Thread Development Team + * + * SPDX-License-Identifier: Apache-2.0 + * + * Change Logs: + * Date Author Notes + * 2021-09-22 AisinoCip add board.h to this bsp + */ + +#ifndef __BOARD_H__ +#define __BOARD_H__ + +#include +#include "ACM32Fxx_HAL.h" + +/*-------------------------- UART CONFIG BEGIN --------------------------*/ + +/** After configuring corresponding UART or UART DMA, you can use it. + * + * STEP 1, define macro define related to the serial port opening based on the serial port number + * such as #define BSP_USING_UATR1 + * + * STEP 2, according to the corresponding pin of serial port, modify the related serial port information + * such as #define UART1_TX_PORT GPIOX -> GPIOA + * #define UART1_RX_PORT GPIOX -> GPIOA + * #define UART1_TX_PIN GPIO_PIN_X -> GPIO_PIN_9 + * #define UART1_RX_PIN GPIO_PIN_X -> GPIO_PIN_10 + * + * STEP 3, if you want using SERIAL DMA, you must open it in the RT-Thread Settings. + * RT-Thread Setting -> Components -> Device Drivers -> Serial Device Drivers -> Enable Serial DMA Mode + * + * STEP 4, according to serial port number to define serial port tx/rx DMA function in the board.h file + * such as #define BSP_UART1_RX_USING_DMA + * + */ + +#if defined(BSP_USING_UART1) + #define UART1_TX_PORT GPIOA + #define UART1_RX_PORT GPIOA + #define UART1_TX_PIN GPIO_PIN_9 + #define UART1_RX_PIN GPIO_PIN_10 + + #if defined(BSP_UART1_RX_USING_DMA) + #define UART1_RX_DMA_INSTANCE DMA_Channel0 + #define UART1_RX_DMA_RCC BIT12 + #define UART1_RX_DMA_IRQ DMA_IRQn + #define UART1_RX_DMA_CHANNEL 0 + #define UART1_RX_DMA_REQUEST REQ6_UART1_RECV + #endif /* BSP_UART1_RX_USING_DMA */ + + #if defined(BSP_UART1_TX_USING_DMA) + #define UART1_TX_DMA_INSTANCE DMA_Channel1 + #define UART1_TX_DMA_RCC BIT12 + #define UART1_TX_DMA_IRQ DMA_IRQn + #define UART1_TX_DMA_CHANNEL 1 + #define UART1_TX_DMA_REQUEST REQ5_UART1_SEND + #endif /* BSP_UART1_TX_USING_DMA */ + +#endif /* BSP_USING_UART1 */ + +#if defined(BSP_USING_UART2) + #define UART2_TX_PORT GPIOA + #define UART2_RX_PORT GPIOA + #define UART2_TX_PIN GPIO_PIN_2 + #define UART2_RX_PIN GPIO_PIN_3 + + #if defined(BSP_UART2_RX_USING_DMA) + #define UART2_RX_DMA_INSTANCE DMA_Channel0 + #define UART2_RX_DMA_RCC BIT12 + #define UART2_RX_DMA_IRQ DMA_IRQn + #define UART2_RX_DMA_CHANNEL 0 + #define UART2_RX_DMA_REQUEST REQ8_UART2_RECV + #endif /* BSP_UART2_RX_USING_DMA */ + + #if defined(BSP_UART2_TX_USING_DMA) + #define UART2_TX_DMA_INSTANCE DMA_Channel1 + #define UART2_TX_DMA_RCC BIT12 + #define UART2_TX_DMA_IRQ DMA_IRQn + #define UART2_TX_DMA_CHANNEL 1 + #define UART2_TX_DMA_REQUEST REQ7_UART2_SEND + #endif /* BSP_UART2_TX_USING_DMA */ +#endif /* BSP_USING_UART2 */ + +#if defined(BSP_USING_UART3) + #define UART3_TX_PORT GPIOB + #define UART3_RX_PORT GPIOB + #define UART3_TX_PIN GPIO_PIN_10 + #define UART3_RX_PIN GPIO_PIN_11 + + #if defined(BSP_UART3_RX_USING_DMA) + #define UART3_RX_DMA_INSTANCE DMA_Channel2 + #define UART3_RX_DMA_RCC BIT12 + #define UART3_RX_DMA_IRQ DMA_IRQn + #define UART3_RX_DMA_CHANNEL 2 + #define UART3_RX_DMA_REQUEST REQ29_UART3_RECV + #endif /* BSP_UART3_RX_USING_DMA */ + + #if defined(BSP_UART3_TX_USING_DMA) + #define UART3_TX_DMA_INSTANCE DMA_Channel3 + #define UART3_TX_DMA_RCC BIT12 + #define UART3_TX_DMA_IRQ DMA_IRQn + #define UART3_TX_DMA_CHANNEL 3 + #define UART3_TX_DMA_REQUEST REQ27_UART3_SEND + #endif /* BSP_UART3_TX_USING_DMA */ +#endif /* BSP_USING_UART3 */ + +#if defined(BSP_USING_UART4) + #define UART4_TX_PORT GPIOC + #define UART4_RX_PORT GPIOC + #define UART4_TX_PIN GPIO_PIN_10 + #define UART4_RX_PIN GPIO_PIN_11 + + #if defined(BSP_UART4_RX_USING_DMA) + #define UART4_RX_DMA_INSTANCE DMA_Channel4 + #define UART4_RX_DMA_RCC BIT12 + #define UART4_RX_DMA_IRQ DMA_IRQn + #define UART4_RX_DMA_CHANNEL 4 + #define UART4_RX_DMA_REQUEST REQ46_UART4_RECV + #endif /* BSP_UART4_RX_USING_DMA */ + + #if defined(BSP_UART4_TX_USING_DMA) + #define UART4_TX_DMA_INSTANCE DMA_Channel5 + #define UART4_TX_DMA_RCC BIT12 + #define UART4_TX_DMA_IRQ DMA_IRQn + #define UART4_TX_DMA_CHANNEL 5 + #define UART4_TX_DMA_REQUEST REQ45_UART4_SEND + #endif /* BSP_UART4_TX_USING_DMA */ +#endif /* BSP_USING_UART4 */ +/*-------------------------- UART CONFIG END --------------------------*/ + +/* board configuration */ + +void rt_hw_board_init(void); + +#endif /* __BOARD_H__ */ + diff --git a/bsp/acm32f4xx-nucleo/drivers/drv_gpio.c b/bsp/acm32f4xx-nucleo/drivers/drv_gpio.c new file mode 100644 index 0000000000..9ffef98853 --- /dev/null +++ b/bsp/acm32f4xx-nucleo/drivers/drv_gpio.c @@ -0,0 +1,479 @@ +/* + * Copyright (c) 2006-2021, RT-Thread Development Team + * + * SPDX-License-Identifier: Apache-2.0 + * + * Change Logs: + * Date Author Notes + * 2021-09-18 AisinoChip first version + */ + +#include +#include +#include "board.h" + +#ifdef RT_USING_PIN + +#define __ACM32_PIN(index, gpio, gpio_index) \ + { \ + index, GPIO##gpio, GPIO_PIN_##gpio_index \ + } + +#define __ACM32_PIN_RESERVE \ + { \ + -1, 0, 0 \ + } + +/* ACM32 GPIO driver */ +struct pin_index +{ + int index; + enum_GPIOx_t gpio; + uint32_t pin; +}; + +struct pin_irq_map +{ + rt_uint16_t line; + EXTI_HandleTypeDef handle; +}; + +static const struct pin_index pins[] = +{ +#if defined(BSP_USING_GPIO1) + __ACM32_PIN(0, A, 0), + __ACM32_PIN(1, A, 1), + __ACM32_PIN(2, A, 2), + __ACM32_PIN(3, A, 3), + __ACM32_PIN(4, A, 4), + __ACM32_PIN(5, A, 5), + __ACM32_PIN(6, A, 6), + __ACM32_PIN(7, A, 7), + __ACM32_PIN(8, A, 8), + __ACM32_PIN(9, A, 9), + __ACM32_PIN(10, A, 10), + __ACM32_PIN(11, A, 11), + __ACM32_PIN(12, A, 12), + __ACM32_PIN(13, A, 13), + __ACM32_PIN(14, A, 14), + __ACM32_PIN(15, A, 15), + __ACM32_PIN(16, B, 0), + __ACM32_PIN(17, B, 1), + __ACM32_PIN(18, B, 2), + __ACM32_PIN(19, B, 3), + __ACM32_PIN(20, B, 4), + __ACM32_PIN(21, B, 5), + __ACM32_PIN(22, B, 6), + __ACM32_PIN(23, B, 7), + __ACM32_PIN(24, B, 8), + __ACM32_PIN(25, B, 9), + __ACM32_PIN(26, B, 10), + __ACM32_PIN(27, B, 11), + __ACM32_PIN(28, B, 12), + __ACM32_PIN(29, B, 13), + __ACM32_PIN(30, B, 14), + __ACM32_PIN(31, B, 15), +#if defined(BSP_USING_GPIO2) + __ACM32_PIN(32, C, 0), + __ACM32_PIN(33, C, 1), + __ACM32_PIN(34, C, 2), + __ACM32_PIN(35, C, 3), + __ACM32_PIN(36, C, 4), + __ACM32_PIN(37, C, 5), + __ACM32_PIN(38, C, 6), + __ACM32_PIN(39, C, 7), + __ACM32_PIN(40, C, 8), + __ACM32_PIN(41, C, 9), + __ACM32_PIN(42, C, 10), + __ACM32_PIN(43, C, 11), + __ACM32_PIN(44, C, 12), + __ACM32_PIN(45, C, 13), + __ACM32_PIN(46, C, 14), + __ACM32_PIN(47, C, 15), + __ACM32_PIN(48, D, 0), + __ACM32_PIN(49, D, 1), + __ACM32_PIN(50, D, 2), + __ACM32_PIN(51, D, 3), + __ACM32_PIN(52, D, 4), + __ACM32_PIN(53, D, 5), + __ACM32_PIN(54, D, 6), + __ACM32_PIN(55, D, 7), + __ACM32_PIN(56, D, 8), + __ACM32_PIN(57, D, 9), + __ACM32_PIN(58, D, 10), + __ACM32_PIN(59, D, 11), + __ACM32_PIN(60, D, 12), + __ACM32_PIN(61, D, 13), + __ACM32_PIN(62, D, 14), + __ACM32_PIN(63, D, 15), +#if defined(BSP_USING_GPIO3) + __ACM32_PIN(64, E, 0), + __ACM32_PIN(65, E, 1), + __ACM32_PIN(66, E, 2), + __ACM32_PIN(67, E, 3), + __ACM32_PIN(68, E, 4), + __ACM32_PIN(69, E, 5), + __ACM32_PIN(70, E, 6), + __ACM32_PIN(71, E, 7), + __ACM32_PIN(72, E, 8), + __ACM32_PIN(73, E, 9), + __ACM32_PIN(74, E, 10), + __ACM32_PIN(75, E, 11), + __ACM32_PIN(76, E, 12), + __ACM32_PIN(77, E, 13), + __ACM32_PIN(78, E, 14), + __ACM32_PIN(79, E, 15), + __ACM32_PIN(80, F, 0), + __ACM32_PIN(81, F, 1), + __ACM32_PIN(82, F, 2), + __ACM32_PIN(83, F, 3), + __ACM32_PIN(84, F, 4), +#endif /* defined(BSP_USING_GPIO3) */ +#endif /* defined(BSP_USING_GPIO2) */ +#endif /* defined(BSP_USING_GPIO1) */ +}; + +static struct pin_irq_map pin_irq_map[] = +{ + {EXTI_LINE_0, {0}}, + {EXTI_LINE_1, {0}}, + {EXTI_LINE_2, {0}}, + {EXTI_LINE_3, {0}}, + {EXTI_LINE_4, {0}}, + {EXTI_LINE_5, {0}}, + {EXTI_LINE_6, {0}}, + {EXTI_LINE_7, {0}}, + {EXTI_LINE_8, {0}}, + {EXTI_LINE_9, {0}}, + {EXTI_LINE_10, {0}}, + {EXTI_LINE_11, {0}}, + {EXTI_LINE_12, {0}}, + {EXTI_LINE_13, {0}}, + {EXTI_LINE_14, {0}}, + {EXTI_LINE_15, {0}}, +}; + +static struct rt_pin_irq_hdr pin_irq_hdr_tab[] = +{ + {-1, 0, RT_NULL, RT_NULL}, + {-1, 0, RT_NULL, RT_NULL}, + {-1, 0, RT_NULL, RT_NULL}, + {-1, 0, RT_NULL, RT_NULL}, + {-1, 0, RT_NULL, RT_NULL}, + {-1, 0, RT_NULL, RT_NULL}, + {-1, 0, RT_NULL, RT_NULL}, + {-1, 0, RT_NULL, RT_NULL}, + {-1, 0, RT_NULL, RT_NULL}, + {-1, 0, RT_NULL, RT_NULL}, + {-1, 0, RT_NULL, RT_NULL}, + {-1, 0, RT_NULL, RT_NULL}, + {-1, 0, RT_NULL, RT_NULL}, + {-1, 0, RT_NULL, RT_NULL}, + {-1, 0, RT_NULL, RT_NULL}, + {-1, 0, RT_NULL, RT_NULL}, +}; +static uint32_t pin_irq_enable_mask = 0; + +#define ITEM_NUM(items) sizeof(items) / sizeof(items[0]) +static const struct pin_index *get_pin(uint8_t pin) +{ + const struct pin_index *index; + + if (pin < ITEM_NUM(pins)) + { + index = &pins[pin]; + if (index->index == -1) + index = RT_NULL; + } + else + { + index = RT_NULL; + } + + return index; +}; + +static void _pin_write(rt_device_t dev, rt_base_t pin, rt_base_t value) +{ + const struct pin_index *index; + + index = get_pin(pin); + if (index == RT_NULL) + { + return; + } + + HAL_GPIO_WritePin(index->gpio, index->pin, (enum_PinState_t)value); +} + +static int _pin_read(rt_device_t dev, rt_base_t pin) +{ + int value; + const struct pin_index *index; + + value = PIN_LOW; + + index = get_pin(pin); + if (index == RT_NULL) + { + return value; + } + + value = HAL_GPIO_ReadPin(index->gpio, index->pin); + + return value; +} + +static void _pin_mode(rt_device_t dev, rt_base_t pin, rt_base_t mode) +{ + const struct pin_index *index; + GPIO_InitTypeDef GPIO_InitStruct; + + index = get_pin(pin); + if (index == RT_NULL) + { + return; + } + + /* Configure GPIO_InitStructure */ + GPIO_InitStruct.Pin = index->pin; + GPIO_InitStruct.Mode = GPIO_MODE_OUTPUT_PP; + GPIO_InitStruct.Pull = GPIO_NOPULL; + GPIO_InitStruct.Alternate = GPIO_FUNCTION_0; + + if (mode == PIN_MODE_OUTPUT) + { + /* output setting */ + GPIO_InitStruct.Mode = GPIO_MODE_OUTPUT_PP; + GPIO_InitStruct.Pull = GPIO_NOPULL; + } + else if (mode == PIN_MODE_INPUT) + { + /* input setting: not pull. */ + GPIO_InitStruct.Mode = GPIO_MODE_INPUT; + GPIO_InitStruct.Pull = GPIO_NOPULL; + } + else if (mode == PIN_MODE_INPUT_PULLUP) + { + /* input setting: pull up. */ + GPIO_InitStruct.Mode = GPIO_MODE_INPUT; + GPIO_InitStruct.Pull = GPIO_PULLUP; + } + else if (mode == PIN_MODE_INPUT_PULLDOWN) + { + /* input setting: pull down. */ + GPIO_InitStruct.Mode = GPIO_MODE_INPUT; + GPIO_InitStruct.Pull = GPIO_PULLDOWN; + } + else if (mode == PIN_MODE_OUTPUT_OD) + { + /* output setting: od. */ + GPIO_InitStruct.Mode = GPIO_MODE_OUTPUT_OD; + GPIO_InitStruct.Pull = GPIO_NOPULL; + } + + /* special PIN process */ + __HAL_RTC_PC13_DIGIT(); + + HAL_GPIO_Init(index->gpio, &GPIO_InitStruct); +} + +#define PIN2INDEX(pin) ((pin) % 16) + +static rt_err_t _pin_attach_irq(struct rt_device *device, rt_int32_t pin, + rt_uint32_t mode, void (*hdr)(void *args), void *args) +{ + const struct pin_index *index; + rt_base_t level; + rt_int32_t irqindex = -1; + + index = get_pin(pin); + if (index == RT_NULL) + { + return RT_ENOSYS; + } + + irqindex = PIN2INDEX(pin); + + level = rt_hw_interrupt_disable(); + if (pin_irq_hdr_tab[irqindex].pin == pin && + pin_irq_hdr_tab[irqindex].hdr == hdr && + pin_irq_hdr_tab[irqindex].mode == mode && + pin_irq_hdr_tab[irqindex].args == args) + { + rt_hw_interrupt_enable(level); + return RT_EOK; + } + + if (pin_irq_hdr_tab[irqindex].pin != -1) + { + rt_hw_interrupt_enable(level); + return RT_EBUSY; + } + + pin_irq_hdr_tab[irqindex].pin = pin; + pin_irq_hdr_tab[irqindex].hdr = hdr; + pin_irq_hdr_tab[irqindex].mode = mode; + pin_irq_hdr_tab[irqindex].args = args; + rt_hw_interrupt_enable(level); + + return RT_EOK; +} + +static rt_err_t _pin_dettach_irq(struct rt_device *device, rt_int32_t pin) +{ + const struct pin_index *index; + rt_base_t level; + rt_int32_t irqindex = -1; + + index = get_pin(pin); + if (index == RT_NULL) + { + return RT_ENOSYS; + } + + irqindex = PIN2INDEX(pin); + + level = rt_hw_interrupt_disable(); + if (pin_irq_hdr_tab[irqindex].pin == -1) + { + rt_hw_interrupt_enable(level); + return RT_EOK; + } + pin_irq_hdr_tab[irqindex].pin = -1; + pin_irq_hdr_tab[irqindex].hdr = RT_NULL; + pin_irq_hdr_tab[irqindex].mode = 0; + pin_irq_hdr_tab[irqindex].args = RT_NULL; + rt_hw_interrupt_enable(level); + + return RT_EOK; +} + +static rt_err_t _pin_irq_enable(struct rt_device *device, rt_base_t pin, + rt_uint32_t enabled) +{ + const struct pin_index *index; + struct pin_irq_map *irqmap; + rt_base_t level; + rt_int32_t irqindex = -1; + GPIO_InitTypeDef GPIO_InitStruct; + + index = get_pin(pin); + if (index == RT_NULL) + { + return RT_ENOSYS; + } + + irqindex = PIN2INDEX(pin); + irqmap = &pin_irq_map[irqindex]; + + if (enabled == PIN_IRQ_ENABLE) + { + level = rt_hw_interrupt_disable(); + + if (pin_irq_hdr_tab[irqindex].pin == -1) + { + rt_hw_interrupt_enable(level); + return RT_ENOSYS; + } + + /* Configure GPIO_InitStructure */ + GPIO_InitStruct.Pin = index->pin; + GPIO_InitStruct.Alternate = GPIO_FUNCTION_0; + GPIO_InitStruct.Mode = GPIO_MODE_INPUT; + + irqmap->handle.u32_Line = irqmap->line; + irqmap->handle.u32_Mode = EXTI_MODE_INTERRUPT; + + switch (pin_irq_hdr_tab[irqindex].mode) + { + case PIN_IRQ_MODE_RISING: + GPIO_InitStruct.Pull = GPIO_PULLDOWN; + irqmap->handle.u32_Trigger = EXTI_TRIGGER_RISING; + break; + case PIN_IRQ_MODE_FALLING: + GPIO_InitStruct.Pull = GPIO_PULLUP; + irqmap->handle.u32_Trigger = EXTI_TRIGGER_FALLING; + break; + case PIN_IRQ_MODE_RISING_FALLING: + GPIO_InitStruct.Pull = GPIO_NOPULL; + irqmap->handle.u32_Trigger = EXTI_TRIGGER_RISING_FALLING; + break; + } + HAL_GPIO_Init(index->gpio, &GPIO_InitStruct); + + irqmap->handle.u32_GPIOSel = pin / 16; + + HAL_EXTI_SetConfigLine(&irqmap->handle); + + pin_irq_enable_mask |= 1 << irqindex; + + rt_hw_interrupt_enable(level); + } + else if (enabled == PIN_IRQ_DISABLE) + { + if ((pin_irq_enable_mask & (1 << irqindex)) == 0) + { + return RT_ENOSYS; + } + + level = rt_hw_interrupt_disable(); + + EXTI->IENR &= ~irqmap->line; + EXTI->EENR &= ~irqmap->line; + + rt_hw_interrupt_enable(level); + } + else + { + return -RT_ENOSYS; + } + + return RT_EOK; +} + +const static struct rt_pin_ops _acm32_pin_ops = +{ + _pin_mode, + _pin_write, + _pin_read, + _pin_attach_irq, + _pin_dettach_irq, + _pin_irq_enable, +}; + +rt_inline void pin_irq_hdr(int irqno) +{ + if (pin_irq_hdr_tab[irqno].hdr) + { + pin_irq_hdr_tab[irqno].hdr(pin_irq_hdr_tab[irqno].args); + } +} + +int rt_hw_pin_init(void) +{ + return rt_device_pin_register("pin", &_acm32_pin_ops, RT_NULL); +} +INIT_BOARD_EXPORT(rt_hw_pin_init); + +void EXTI_IRQHandler(void) +{ + /* enter interrupt */ + rt_interrupt_enter(); + + for (int i = 0; i < 16; i++) + { + if (EXTI->PDR & pin_irq_map[i].line) + { + EXTI->PDR = pin_irq_map[i].line; + pin_irq_hdr(i); + break; + } + } + + /* leave interrupt */ + rt_interrupt_leave(); +} + +#endif /* RT_USING_PIN */ + diff --git a/bsp/acm32f4xx-nucleo/drivers/drv_uart.c b/bsp/acm32f4xx-nucleo/drivers/drv_uart.c new file mode 100644 index 0000000000..c84c6bfeff --- /dev/null +++ b/bsp/acm32f4xx-nucleo/drivers/drv_uart.c @@ -0,0 +1,663 @@ +/* + * Copyright (c) 2006-2021, RT-Thread Development Team + * + * SPDX-License-Identifier: Apache-2.0 + * + * Change Logs: + * Date Author Notes + * 2021-08-23 AisinoChip the first version + */ + +#include +#include +#include +#include "board.h" +#include "uart_config.h" + +#ifdef RT_USING_SERIAL + +#ifdef RT_SERIAL_USING_DMA +struct dma_config +{ + DMA_Channel_TypeDef *Instance; + rt_uint32_t dma_rcc; + IRQn_Type dma_irq; + + rt_uint32_t channel; + rt_uint32_t request; +}; +#endif + +#ifdef RT_SERIAL_USING_DMA + static void DMA_Configuration(struct rt_serial_device *serial, rt_uint32_t flag); +#endif /* RT_SERIAL_USING_DMA */ + +struct acm32_uart_config +{ + const char *name; + UART_TypeDef *Instance; + IRQn_Type irq_type; + enum_Enable_ID_t enable_id; + +#ifdef RT_SERIAL_USING_DMA + struct dma_config *dma_rx; + struct dma_config *dma_tx; +#endif + + enum_GPIOx_t tx_port; + enum_GPIOx_t rx_port; + rt_uint32_t tx_pin; + rt_uint32_t rx_pin; +}; + +struct acm32_uart +{ + UART_HandleTypeDef handle; + struct acm32_uart_config *config; +#ifdef RT_SERIAL_USING_DMA + struct + { + DMA_HandleTypeDef handle; + rt_size_t last_index; + } dma_rx; + + struct + { + DMA_HandleTypeDef handle; + } dma_tx; +#endif + + rt_uint16_t uart_dma_flag; + struct rt_serial_device serial; +}; + +static rt_err_t uart_rx_indicate_cb(rt_device_t dev, rt_size_t size) +{ + return RT_EOK; +} + +static rt_err_t _uart_configure(struct rt_serial_device *serial, struct serial_configure *cfg) +{ + struct acm32_uart *uart; + + RT_ASSERT(serial != RT_NULL); + RT_ASSERT(cfg != RT_NULL); + + uart = rt_container_of(serial, struct acm32_uart, serial); + + uart->handle.Instance = uart->config->Instance; + + uart->handle.Init.BaudRate = cfg->baud_rate; + if (cfg->data_bits == DATA_BITS_8) + { + uart->handle.Init.WordLength = UART_WORDLENGTH_8B; + } + else /* not support */ + { + return -RT_EINVAL; + } + + if (cfg->stop_bits == STOP_BITS_1) + { + uart->handle.Init.StopBits = UART_STOPBITS_1; + } + else if (cfg->stop_bits == STOP_BITS_2) + { + uart->handle.Init.StopBits = UART_STOPBITS_2; + } + else /* not support */ + { + return -RT_EINVAL; + } + + if (cfg->parity == PARITY_NONE) + { + uart->handle.Init.Parity = UART_PARITY_NONE; + } + else if (cfg->parity == PARITY_ODD) + { + uart->handle.Init.Parity = UART_PARITY_ODD; + } + else if (cfg->parity == PARITY_EVEN) + { + uart->handle.Init.Parity = UART_PARITY_EVEN; + } + else /* not support */ + { + return -RT_EINVAL; + } + + uart->handle.Init.Mode = UART_MODE_TX_RX; + uart->handle.Init.HwFlowCtl = UART_HWCONTROL_NONE; + + HAL_UART_Init(&uart->handle); + + uart->handle.Instance->LCRH &= ~UART_LCRH_FEN; + return RT_EOK; +} + +static rt_err_t _uart_control(struct rt_serial_device *serial, int cmd, void *arg) +{ + struct acm32_uart *uart; +#ifdef RT_SERIAL_USING_DMA + rt_ubase_t ctrl_arg = (rt_ubase_t)arg; +#endif + + RT_ASSERT(serial != RT_NULL); + + uart = rt_container_of(serial, struct acm32_uart, serial); + + switch (cmd) + { + /* disable interrupt */ + case RT_DEVICE_CTRL_CLR_INT: + NVIC_DisableIRQ(uart->config->irq_type); + /* Disable RX interrupt */ + uart->handle.Instance->IE &= ~UART_IE_RXI; + break; + /* enable interrupt */ + case RT_DEVICE_CTRL_SET_INT: + NVIC_EnableIRQ(uart->config->irq_type); + /* Enable RX interrupt */ + uart->handle.Instance->IE |= UART_IE_RXI; + break; +#ifdef RT_SERIAL_USING_DMA + /* UART config */ + case RT_DEVICE_CTRL_CONFIG : + DMA_Configuration(serial, (rt_uint32_t)ctrl_arg); + rt_device_set_rx_indicate((rt_device_t)serial, uart_rx_indicate_cb); + break; +#endif /* RT_SERIAL_USING_DMA */ + } + return RT_EOK; +} + +static int _uart_putc(struct rt_serial_device *serial, char c) +{ + struct acm32_uart *uart; + + RT_ASSERT(serial != RT_NULL); + + uart = rt_container_of(serial, struct acm32_uart, serial); + + while (uart->handle.Instance->FR & UART_FR_TXFF); /* wait Tx FIFO not full */ + uart->handle.Instance->DR = c; + while ((uart->handle.Instance->FR & UART_FR_BUSY)); /* wait TX Complete */ + + return 1; +} + +static int _uart_getc(struct rt_serial_device *serial) +{ + struct acm32_uart *uart; + + int ch; + + RT_ASSERT(serial != RT_NULL); + + uart = rt_container_of(serial, struct acm32_uart, serial); + + ch = -1; + if (!(uart->handle.Instance->FR & UART_FR_RXFE)) /* Rx FIFO not empty */ + { + ch = uart->handle.Instance->DR & 0xff; + } + + return ch; +} + +#ifdef RT_SERIAL_USING_DMA +/** + * Serial port receive idle process. This need add to uart idle ISR. + * + * @param serial serial device + */ +static void dma_uart_rx_idle_isr(struct rt_serial_device *serial) +{ + struct acm32_uart *uart; + + RT_ASSERT(serial != RT_NULL); + + uart = rt_container_of(serial, struct acm32_uart, serial); + + rt_size_t recv_total_index, recv_len; + rt_base_t level; + + /* disable interrupt */ + level = rt_hw_interrupt_disable(); + + recv_total_index = uart->handle.lu32_RxSize - (uart->handle.HDMA_Rx->Instance->CTRL & 0xFFF); + recv_len = recv_total_index - uart->handle.lu32_RxCount; + uart->handle.lu32_RxCount = recv_total_index; + /* enable interrupt */ + rt_hw_interrupt_enable(level); + + if (recv_len) + { + rt_hw_serial_isr(serial, RT_SERIAL_EVENT_RX_DMADONE | (recv_len << 8)); + } +} + +/* + DMA receive done process. This need add to DMA receive done ISR. + + @param serial serial device +*/ +static void dma_rx_done_isr(struct rt_serial_device *serial) +{ + struct acm32_uart *uart; + struct rt_serial_rx_fifo *rx_fifo = (struct rt_serial_rx_fifo *)serial->serial_rx; + + RT_ASSERT(serial != RT_NULL); + + uart = rt_container_of(serial, struct acm32_uart, serial); + + rt_size_t recv_len; + rt_base_t level; + + /* disable interrupt */ + level = rt_hw_interrupt_disable(); + + recv_len = serial->config.bufsz - (uart->handle.HDMA_Rx->Instance->CTRL & 0xFFF); + uart->dma_rx.last_index = 0; + + DMA->INT_TC_CLR |= 1 << (uart->config->dma_rx->channel); /* clear channel0 TC flag */ + + /* enable interrupt */ + rt_hw_interrupt_enable(level); + + if (recv_len) + { + rt_hw_serial_isr(serial, RT_SERIAL_EVENT_RX_DMADONE | (recv_len << 8)); + } + + HAL_UART_Receive_DMA(&(uart->handle), &rx_fifo->buffer[rx_fifo->put_index], serial->config.bufsz); +} + +static rt_size_t _uart_dma_transmit(struct rt_serial_device *serial, rt_uint8_t *buf, rt_size_t size, int direction) +{ + struct acm32_uart *uart; + RT_ASSERT(serial != RT_NULL); + uart = rt_container_of(serial, struct acm32_uart, serial); + + if (size == 0) + { + return 0; + } + + if (RT_SERIAL_DMA_TX == direction) + { + if (HAL_UART_Transmit_DMA(&uart->handle, buf, size) == HAL_OK) + { + rt_hw_serial_isr(serial, RT_SERIAL_EVENT_TX_DMADONE); + return size; + } + else + { + return 0; + } + } + return 0; +} + +#endif /* RT_SERIAL_USING_DMA */ + +static const struct rt_uart_ops acm32_uart_ops = +{ + _uart_configure, + _uart_control, + _uart_putc, + _uart_getc, +#ifdef RT_SERIAL_USING_DMA + _uart_dma_transmit, +#endif +}; + +#ifdef RT_SERIAL_USING_DMA +static void DMA_Configuration(struct rt_serial_device *serial, rt_uint32_t flag) +{ + struct rt_serial_rx_fifo *rx_fifo; + DMA_HandleTypeDef *DMA_Handle; + struct dma_config *dma_config; + struct acm32_uart *uart; + + RT_ASSERT(serial != RT_NULL); + + uart = rt_container_of(serial, struct acm32_uart, serial); + + if (RT_DEVICE_FLAG_DMA_RX == flag) + { + DMA_Handle = &uart->dma_rx.handle; + dma_config = uart->config->dma_rx; + } + else if (RT_DEVICE_FLAG_DMA_TX == flag) + { + DMA_Handle = &uart->dma_tx.handle; + dma_config = uart->config->dma_tx; + } + else + { + return; + } + + DMA_Handle->Instance = dma_config->Instance; + + if (RT_DEVICE_FLAG_DMA_RX == flag) + { + DMA_Handle->Init.Data_Flow = DMA_DATA_FLOW_P2M; + DMA_Handle->Init.Mode = DMA_NORMAL; + DMA_Handle->Init.Source_Inc = DMA_SOURCE_ADDR_INCREASE_DISABLE; + DMA_Handle->Init.Desination_Inc = DMA_DST_ADDR_INCREASE_ENABLE; + + } + else if (RT_DEVICE_FLAG_DMA_TX == flag) + { + DMA_Handle->Init.Data_Flow = DMA_DATA_FLOW_M2P; + DMA_Handle->Init.Mode = DMA_NORMAL; + DMA_Handle->Init.Source_Inc = DMA_SOURCE_ADDR_INCREASE_ENABLE; + DMA_Handle->Init.Desination_Inc = DMA_DST_ADDR_INCREASE_DISABLE; + } + + DMA_Handle->Init.Request_ID = dma_config->request; + DMA_Handle->Init.Source_Width = DMA_SRC_WIDTH_BYTE; + DMA_Handle->Init.Desination_Width = DMA_DST_WIDTH_BYTE; + + if (HAL_DMA_Init(DMA_Handle) != HAL_OK) + { + RT_ASSERT(0); + } + + if (RT_DEVICE_FLAG_DMA_RX == flag) + { + __HAL_LINK_DMA(uart->handle, HDMA_Rx, uart->dma_rx.handle); + } + else if (RT_DEVICE_FLAG_DMA_TX == flag) + { + __HAL_LINK_DMA(uart->handle, HDMA_Tx, uart->dma_tx.handle); + } + /* enable interrupt */ + if (flag == RT_DEVICE_FLAG_DMA_RX) + { + rx_fifo = (struct rt_serial_rx_fifo *)serial->serial_rx; + /* Start DMA transfer */ + if (HAL_UART_Receive_DMA(&(uart->handle), rx_fifo->buffer, serial->config.bufsz) != HAL_OK) + { + /* Transfer error in reception process */ + RT_ASSERT(0); + } + + } +} +#endif /* RT_SERIAL_USING_DMA */ + +enum +{ +#ifdef BSP_USING_UART1 + UART1_INDEX, +#endif +#ifdef BSP_USING_UART2 + UART2_INDEX, +#endif +#ifdef BSP_USING_UART3 + UART3_INDEX, +#endif +#ifdef BSP_USING_UART4 + UART4_INDEX, +#endif + UART_MAX_INDEX, +}; + +static struct acm32_uart_config uart_config[] = +{ +#ifdef BSP_USING_UART1 + UART1_CONFIG, +#endif +#ifdef BSP_USING_UART2 + UART2_CONFIG, +#endif +#ifdef BSP_USING_UART3 + UART3_CONFIG, +#endif +#ifdef BSP_USING_UART4 + UART4_CONFIG, +#endif +}; + +static struct acm32_uart uart_obj[sizeof(uart_config) / sizeof(uart_config[0])] = {0}; +#ifdef RT_SERIAL_USING_DMA +static void uart_get_dma_config(void) +{ +#if defined(BSP_USING_UART1) +#if defined(BSP_UART1_RX_USING_DMA) + static struct dma_config uart1_rx_dma_conf = UART1_DMA_RX_CONFIG; + uart_obj[UART1_INDEX].uart_dma_flag |= RT_DEVICE_FLAG_DMA_RX; + uart_config[UART1_INDEX].dma_rx = &uart1_rx_dma_conf; +#endif /* BSP_UART1_RX_USING_DMA */ +#if defined(BSP_UART1_TX_USING_DMA) + static struct dma_config uart1_tx_dma_conf = UART1_DMA_TX_CONFIG; + uart_obj[UART1_INDEX].uart_dma_flag |= RT_DEVICE_FLAG_DMA_TX; + uart_config[UART1_INDEX].dma_tx = &uart1_tx_dma_conf; +#endif /* BSP_UART1_TX_USING_DMA */ +#endif /* BSP_USING_UART1 */ + +#if defined(BSP_USING_UART2) +#if defined(BSP_UART2_RX_USING_DMA) + static struct dma_config uart2_rx_dma_conf = UART2_DMA_RX_CONFIG; + uart_obj[UART2_INDEX].uart_dma_flag |= RT_DEVICE_FLAG_DMA_RX; + uart_config[UART2_INDEX].dma_rx = &uart2_rx_dma_conf; +#endif /* BSP_UART2_RX_USING_DMA */ +#if defined(BSP_UART2_TX_USING_DMA) + static struct dma_config uart2_tx_dma_conf = UART2_DMA_TX_CONFIG; + uart_obj[UART2_INDEX].uart_dma_flag |= RT_DEVICE_FLAG_DMA_TX; + uart_config[UART2_INDEX].dma_tx = &uart2_tx_dma_conf; +#endif /* BSP_UART2_TX_USING_DMA */ +#endif /* BSP_USING_UART2 */ + +#if defined(BSP_USING_UART3) +#if defined(BSP_UART3_RX_USING_DMA) + static struct dma_config uart3_rx_dma_conf = UART3_DMA_RX_CONFIG; + uart_obj[UART3_INDEX].uart_dma_flag |= RT_DEVICE_FLAG_DMA_RX; + uart_config[UART3_INDEX].dma_rx = &uart3_rx_dma_conf; +#endif /* BSP_UART3_RX_USING_DMA */ +#if defined(BSP_UART3_TX_USING_DMA) + static struct dma_config uart3_tx_dma_conf = UART3_DMA_TX_CONFIG; + uart_obj[UART3_INDEX].uart_dma_flag |= RT_DEVICE_FLAG_DMA_TX; + uart_config[UART3_INDEX].dma_tx = &uart3_tx_dma_conf; +#endif /* BSP_UART3_TX_USING_DMA */ +#endif /* BSP_USING_UART3 */ + +#if defined(BSP_USING_UART4) +#if defined(BSP_UART4_RX_USING_DMA) + static struct dma_config uart4_rx_dma_conf = UART4_DMA_RX_CONFIG; + uart_obj[UART4_INDEX].uart_dma_flag |= RT_DEVICE_FLAG_DMA_RX; + uart_config[UART4_INDEX].dma_rx = &uart4_rx_dma_conf; +#endif /* BSP_UART4_RX_USING_DMA */ +#if defined(BSP_UART3_TX_USING_DMA) + static struct dma_config uart4_tx_dma_conf = UART4_DMA_TX_CONFIG; + uart_obj[UART4_INDEX].uart_dma_flag |= RT_DEVICE_FLAG_DMA_TX; + uart_config[UART4_INDEX].dma_tx = &uart4_tx_dma_conf; +#endif /* BSP_UART4_TX_USING_DMA */ +#endif /* BSP_USING_UART4 */ +} +#endif + +rt_err_t rt_hw_uart_init(void) +{ + rt_size_t obj_num = sizeof(uart_obj) / sizeof(struct acm32_uart); + struct serial_configure config = RT_SERIAL_CONFIG_DEFAULT; + rt_err_t rc = RT_EOK; + +#ifdef RT_SERIAL_USING_DMA + uart_get_dma_config(); +#endif + + for (int i = 0; i < obj_num; i++) + { + uart_obj[i].config = &uart_config[i]; + + uart_obj[i].serial.ops = &acm32_uart_ops; + uart_obj[i].serial.config = config; + + /* register UART device */ + rc = rt_hw_serial_register(&uart_obj[i].serial, uart_obj[i].config->name, + RT_DEVICE_FLAG_RDWR + | RT_DEVICE_FLAG_INT_RX + | RT_DEVICE_FLAG_INT_TX + | uart_obj[i].uart_dma_flag + , NULL); + RT_ASSERT(rc == RT_EOK); + } + + return rc; +} + +static void uart_isr(struct rt_serial_device *serial) +{ + struct acm32_uart *uart = rt_container_of(serial, struct acm32_uart, serial); + + RT_ASSERT(serial != RT_NULL); + + /* receive interrupt enabled */ + if (uart->handle.Instance->IE & UART_IE_RXI) + { + if (uart->handle.Instance->RIS & UART_RIS_RXI) + { + rt_hw_serial_isr(serial, RT_SERIAL_EVENT_RX_IND); + } + } + +#ifdef RT_SERIAL_USING_DMA + if (uart->handle.Instance->IE & UART_IE_RTI) /* Receive TimeOut Interrupt */ + { + dma_uart_rx_idle_isr(serial); + /* Clear RTI Status */ + uart->handle.Instance->ICR = UART_ICR_RTI; + } +#endif /* RT_SERIAL_USING_DMA */ + + if (uart->handle.Instance->IE & UART_IE_TXI && \ + uart->handle.Instance->RIS & UART_RIS_TXI) + { + /* Clear TXI Status */ + uart->handle.Instance->ICR = UART_ICR_TXI; + if (serial->parent.open_flag & RT_DEVICE_FLAG_INT_TX) + { + rt_hw_serial_isr(serial, RT_SERIAL_EVENT_TX_DONE); + } + /* Disable TX interrupt */ + uart->handle.Instance->IE &= ~UART_IE_TXI; + } +} + +#if defined(BSP_USING_UART1) +void UART1_IRQHandler(void) +{ + /* enter interrupt */ + rt_interrupt_enter(); + + uart_isr(&uart_obj[UART1_INDEX].serial); + + /* leave interrupt */ + rt_interrupt_leave(); +} +#endif /* BSP_USING_UART1 */ + +#if defined(BSP_USING_UART2) +void UART2_IRQHandler(void) +{ + /* enter interrupt */ + rt_interrupt_enter(); + + uart_isr(&uart_obj[UART2_INDEX].serial); + + /* leave interrupt */ + rt_interrupt_leave(); +} +#endif /* BSP_USING_UART2 */ + +#if defined(BSP_USING_UART3) +void UART3_IRQHandler(void) +{ + /* enter interrupt */ + rt_interrupt_enter(); + + uart_isr(&uart_obj[UART3_INDEX].serial); + + /* leave interrupt */ + rt_interrupt_leave(); +} +#endif /* BSP_USING_UART3 */ + +#if defined(BSP_USING_UART4) +void UART4_IRQHandler(void) +{ + /* enter interrupt */ + rt_interrupt_enter(); + + uart_isr(&uart_obj[UART4_INDEX].serial); + + /* leave interrupt */ + rt_interrupt_leave(); +} +#endif /* BSP_USING_UART4 */ + +#ifdef RT_SERIAL_USING_DMA +void DMA_IRQHandler(void) +{ + /* enter interrupt */ + rt_interrupt_enter(); + + for (int i = 0; i < UART_MAX_INDEX; i++) + { + if (DMA->RAW_INT_TC_STATUS & (1 << uart_obj[i].config->dma_rx->channel)) + { + dma_rx_done_isr(&uart_obj[i].serial); + break; + } + + if (DMA->RAW_INT_TC_STATUS & (1 << uart_obj[i].config->dma_tx->channel)) + { + DMA->INT_TC_CLR |= 1 << (uart_obj[i].config->dma_tx->channel); /* clear channel0 TC flag */ + break; + } + } + + /* leave interrupt */ + rt_interrupt_leave(); +} +#endif /* RT_SERIAL_USING_DMA */ + +void HAL_UART_MspInit(UART_HandleTypeDef *huart) +{ + struct acm32_uart *uart; + GPIO_InitTypeDef GPIO_Uart; + + RT_ASSERT(huart != RT_NULL); + + /* get uart object */ + uart = rt_container_of(huart, struct acm32_uart, handle); + + /* Enable Clock */ + System_Module_Enable(uart->config->enable_id); + + /* Initialization GPIO */ + GPIO_Uart.Pin = uart->config->tx_pin; + GPIO_Uart.Mode = GPIO_MODE_AF_PP; + GPIO_Uart.Pull = GPIO_PULLUP; + GPIO_Uart.Alternate = GPIO_FUNCTION_2; + HAL_GPIO_Init(uart->config->tx_port, &GPIO_Uart); + + GPIO_Uart.Pin = uart->config->rx_pin; + GPIO_Uart.Mode = GPIO_MODE_AF_PP; + GPIO_Uart.Pull = GPIO_PULLUP; + GPIO_Uart.Alternate = GPIO_FUNCTION_2; + HAL_GPIO_Init(uart->config->rx_port, &GPIO_Uart); + + /* NVIC Config */ + NVIC_ClearPendingIRQ(uart->config->irq_type); + NVIC_SetPriority(uart->config->irq_type, 5); + NVIC_EnableIRQ(uart->config->irq_type); +} + +#endif /* RT_USING_SEARIAL */ + diff --git a/bsp/acm32f4xx-nucleo/drivers/linker_scripts/link.icf b/bsp/acm32f4xx-nucleo/drivers/linker_scripts/link.icf new file mode 100644 index 0000000000..9b0aee84ff --- /dev/null +++ b/bsp/acm32f4xx-nucleo/drivers/linker_scripts/link.icf @@ -0,0 +1,34 @@ +/*###ICF### Section handled by ICF editor, don't touch! ****/ +/*-Editor annotation file-*/ +/* IcfEditorFile="$TOOLKIT_DIR$\config\ide\IcfEditor\cortex_v1_0.xml" */ +/*-Specials-*/ +define symbol __ICFEDIT_intvec_start__ = 0x00000000; +/*-Memory Regions-*/ +define symbol __ICFEDIT_region_ROM_start__ = 0x00000000; +define symbol __ICFEDIT_region_ROM_end__ = 0x0007FFFF; +define symbol __ICFEDIT_region_RAM_start__ = 0x20000000; +define symbol __ICFEDIT_region_RAM_end__ = 0x2002FFFF; +/*-Sizes-*/ +define symbol __ICFEDIT_size_cstack__ = 0x0800; +define symbol __ICFEDIT_size_heap__ = 0x0000; +/**** End of ICF editor section. ###ICF###*/ + +define memory mem with size = 4G; +define region ROM_region = mem:[from __ICFEDIT_region_ROM_start__ to __ICFEDIT_region_ROM_end__]; +define region RAM_region = mem:[from __ICFEDIT_region_RAM_start__ to __ICFEDIT_region_RAM_end__]; + +define block CSTACK with alignment = 8, size = __ICFEDIT_size_cstack__ { }; +define block HEAP with alignment = 8, size = __ICFEDIT_size_heap__ { }; + +initialize by copy { readwrite }; +do not initialize { section .noinit }; + +place at address mem:__ICFEDIT_intvec_start__ { readonly section .intvec }; + +place in ROM_region { readonly }; +place in RAM_region { readwrite, + block CSTACK, block HEAP }; + +export symbol __ICFEDIT_region_RAM_start__; +export symbol __ICFEDIT_region_RAM_end__; + diff --git a/bsp/acm32f4xx-nucleo/drivers/linker_scripts/link.lds b/bsp/acm32f4xx-nucleo/drivers/linker_scripts/link.lds new file mode 100644 index 0000000000..8ed114c07a --- /dev/null +++ b/bsp/acm32f4xx-nucleo/drivers/linker_scripts/link.lds @@ -0,0 +1,156 @@ +/* + * linker script for ACM32F4xx with GNU ld + */ + +/* describes the location and size of blocks of memory in the target. */ +MEMORY +{ + CODE (rx) : ORIGIN = 0x00000000, LENGTH = 512k /* 512KB flash */ + DATA (rw) : ORIGIN = 0x20000000, LENGTH = 192k /* 192KB sram */ +} +/* Program Entry, set to mark it as "used" and avoid gc */ +ENTRY(Reset_Handler) +_system_stack_size = 0x800; + +SECTIONS +{ + .text : + { + . = ALIGN(4); + _stext = .; + KEEP(*(.isr_vector)) /* Startup code */ + . = ALIGN(4); + *(.text) /* remaining code */ + *(.text.*) /* remaining code */ + *(.rodata) /* read-only data (constants) */ + *(.rodata*) + *(.glue_7) + *(.glue_7t) + *(.gnu.linkonce.t*) + + /* section information for finsh shell */ + . = ALIGN(4); + __fsymtab_start = .; + KEEP(*(FSymTab)) + __fsymtab_end = .; + . = ALIGN(4); + __vsymtab_start = .; + KEEP(*(VSymTab)) + __vsymtab_end = .; + . = ALIGN(4); + + /* section information for initial. */ + . = ALIGN(4); + __rt_init_start = .; + KEEP(*(SORT(.rti_fn*))) + __rt_init_end = .; + . = ALIGN(4); + + PROVIDE(__ctors_start__ = .); + KEEP (*(SORT(.init_array.*))) + KEEP (*(.init_array)) + PROVIDE(__ctors_end__ = .); + + . = ALIGN(4); + _etext = .; + } > CODE + + /* .ARM.exidx is sorted, so has to go in its own output section. */ + __exidx_start = .; + .ARM.exidx : + { + *(.ARM.exidx* .gnu.linkonce.armexidx.*) + + /* This is used by the startup in order to initialize the .data secion */ + _sidata = .; + } > CODE + __exidx_end = .; + + /* .data section which is used for initialized data */ + + .data : AT (_sidata) + { + . = ALIGN(4); + /* This is used by the startup in order to initialize the .data secion */ + _sdata = . ; + + *(.data) + *(.data.*) + *(.gnu.linkonce.d*) + + + PROVIDE(__dtors_start__ = .); + KEEP(*(SORT(.dtors.*))) + KEEP(*(.dtors)) + PROVIDE(__dtors_end__ = .); + + . = ALIGN(4); + /* This is used by the startup in order to initialize the .data secion */ + _edata = . ; + } >DATA + + .stack : + { + . = ALIGN(8); + _sstack = .; + . = . + _system_stack_size; + . = ALIGN(8); + _estack = .; + } >DATA + + __bss_start = .; + .bss : + { + . = ALIGN(4); + /* This is used by the startup in order to initialize the .bss secion */ + _sbss = .; + + *(.bss) + *(.bss.*) + *(COMMON) + + . = ALIGN(4); + /* This is used by the startup in order to initialize the .bss secion */ + _ebss = . ; + + *(.bss.init) + } > DATA + __bss_end = .; + + _end = .; + + /* Stabs debugging sections. */ + .stab 0 : { *(.stab) } + .stabstr 0 : { *(.stabstr) } + .stab.excl 0 : { *(.stab.excl) } + .stab.exclstr 0 : { *(.stab.exclstr) } + .stab.index 0 : { *(.stab.index) } + .stab.indexstr 0 : { *(.stab.indexstr) } + .comment 0 : { *(.comment) } + /* DWARF debug sections. + * Symbols in the DWARF debugging sections are relative to the beginning + * of the section so we begin them at 0. */ + /* DWARF 1 */ + .debug 0 : { *(.debug) } + .line 0 : { *(.line) } + /* GNU DWARF 1 extensions */ + .debug_srcinfo 0 : { *(.debug_srcinfo) } + .debug_sfnames 0 : { *(.debug_sfnames) } + /* DWARF 1.1 and DWARF 2 */ + .debug_aranges 0 : { *(.debug_aranges) } + .debug_pubnames 0 : { *(.debug_pubnames) } + /* DWARF 2 */ + .debug_info 0 : { *(.debug_info .gnu.linkonce.wi.*) } + .debug_abbrev 0 : { *(.debug_abbrev) } + .debug_line 0 : { *(.debug_line) } + .debug_frame 0 : { *(.debug_frame) } + .debug_str 0 : { *(.debug_str) } + .debug_loc 0 : { *(.debug_loc) } + .debug_macinfo 0 : { *(.debug_macinfo) } + /* SGI/MIPS DWARF 2 extensions */ + .debug_weaknames 0 : { *(.debug_weaknames) } + .debug_funcnames 0 : { *(.debug_funcnames) } + .debug_typenames 0 : { *(.debug_typenames) } + .debug_varnames 0 : { *(.debug_varnames) } +} + diff --git a/bsp/acm32f4xx-nucleo/drivers/linker_scripts/link.sct b/bsp/acm32f4xx-nucleo/drivers/linker_scripts/link.sct new file mode 100644 index 0000000000..770eeb2aee --- /dev/null +++ b/bsp/acm32f4xx-nucleo/drivers/linker_scripts/link.sct @@ -0,0 +1,16 @@ +; ************************************************************* +; *** Scatter-Loading Description File generated by uVision *** +; ************************************************************* + +LR_IROM1 0x00000000 0x00080000 { ; load region size_region + ER_IROM1 0x00000000 0x00080000 { ; load address = execution address + *.o (RESET, +First) + *(InRoot$$Sections) + .ANY (+RO) + .ANY (+XO) + } + RW_IRAM1 0x20000000 0x00030000 { ; RW data + .ANY (+RW +ZI) + } +} + diff --git a/bsp/acm32f4xx-nucleo/drivers/uart_config.h b/bsp/acm32f4xx-nucleo/drivers/uart_config.h new file mode 100644 index 0000000000..1425b8e568 --- /dev/null +++ b/bsp/acm32f4xx-nucleo/drivers/uart_config.h @@ -0,0 +1,211 @@ +/* + * Copyright (c) 2006-2021, RT-Thread Development Team + * + * SPDX-License-Identifier: Apache-2.0 + * + * Change Logs: + * Date Author Notes + * 2021-08-23 AisinoChip the first version + */ + +#ifndef __UART_CONFIG_H__ +#define __UART_CONFIG_H__ + +#include +#include "board.h" + + +#ifdef __cplusplus +extern "C" { +#endif + +#if defined(RT_USING_SERIAL) + +#if defined(BSP_USING_UART1) + +#if defined(RT_SERIAL_USING_DMA) +#if defined(BSP_UART1_RX_USING_DMA) +#ifndef UART1_DMA_RX_CONFIG +#define UART1_DMA_RX_CONFIG \ + { \ + .Instance = UART1_RX_DMA_INSTANCE, \ + .dma_rcc = UART1_RX_DMA_RCC, \ + .dma_irq = UART1_RX_DMA_IRQ, \ + .channel = UART1_RX_DMA_CHANNEL, \ + .request = UART1_RX_DMA_REQUEST, \ + } +#endif /* UART1_DMA_RX_CONFIG */ +#endif /* BSP_UART1_RX_USING_DMA */ + +#if defined(BSP_UART1_TX_USING_DMA) +#ifndef UART1_DMA_TX_CONFIG +#define UART1_DMA_TX_CONFIG \ + { \ + .Instance = UART1_TX_DMA_INSTANCE, \ + .dma_rcc = UART1_TX_DMA_RCC, \ + .dma_irq = UART1_TX_DMA_IRQ, \ + .channel = UART1_RX_DMA_CHANNEL, \ + .request = UART1_RX_DMA_REQUEST, \ + } +#endif /* UART1_DMA_TX_CONFIG */ +#endif /* BSP_UART1_TX_USING_DMA */ +#endif /* RT_SERIAL_USING_DMA */ + +#ifndef UART1_CONFIG +#define UART1_CONFIG \ + { \ + .name = "uart1", \ + .Instance = UART1, \ + .irq_type = UART1_IRQn, \ + .enable_id = EN_UART1, \ + .tx_port = UART1_TX_PORT, \ + .rx_port = UART1_RX_PORT, \ + .tx_pin = UART1_TX_PIN, \ + .rx_pin = UART1_RX_PIN, \ + } +#endif /* UART1_CONFIG */ +#endif /* BSP_USING_UART1 */ + +#if defined(BSP_USING_UART2) + +#if defined(RT_SERIAL_USING_DMA) +#if defined(BSP_UART2_RX_USING_DMA) +#ifndef UART2_DMA_RX_CONFIG +#define UART2_DMA_RX_CONFIG \ + { \ + .Instance = UART2_RX_DMA_INSTANCE, \ + .dma_rcc = UART2_RX_DMA_RCC, \ + .dma_irq = UART2_RX_DMA_IRQ, \ + .channel = UART2_RX_DMA_CHANNEL, \ + .request = UART2_RX_DMA_REQUEST, \ + } +#endif /* UART2_DMA_RX_CONFIG */ +#endif /* BSP_UART2_RX_USING_DMA */ + +#if defined(BSP_UART2_TX_USING_DMA) +#ifndef UART2_DMA_TX_CONFIG +#define UART2_DMA_TX_CONFIG \ + { \ + .Instance = UART2_TX_DMA_INSTANCE, \ + .dma_rcc = UART2_TX_DMA_RCC, \ + .dma_irq = UART2_TX_DMA_IRQ, \ + .channel = UART2_TX_DMA_CHANNEL, \ + .request = UART2_TX_DMA_REQUEST, \ + } +#endif /* UART2_DMA_TX_CONFIG */ +#endif /* BSP_UART2_TX_USING_DMA */ +#endif /* RT_SERIAL_USING_DMA */ + +#ifndef UART2_CONFIG +#define UART2_CONFIG \ + { \ + .name = "uart2", \ + .Instance = UART2, \ + .irq_type = UART2_IRQn, \ + .enable_id = EN_UART2, \ + .tx_port = UART2_TX_PORT, \ + .rx_port = UART2_RX_PORT, \ + .tx_pin = UART2_TX_PIN, \ + .rx_pin = UART2_RX_PIN, \ + } +#endif /* UART2_CONFIG */ +#endif /* BSP_USING_UART2 */ + +#if defined(BSP_USING_UART3) + +#if defined(RT_SERIAL_USING_DMA) +#if defined(BSP_UART3_RX_USING_DMA) +#ifndef UART3_DMA_RX_CONFIG +#define UART3_DMA_RX_CONFIG \ + { \ + .Instance = UART3_RX_DMA_INSTANCE, \ + .dma_rcc = UART3_RX_DMA_RCC, \ + .dma_irq = UART3_RX_DMA_IRQ, \ + .channel = UART3_RX_DMA_CHANNEL, \ + .request = UART3_RX_DMA_REQUEST, \ + } +#endif /* UART3_DMA_RX_CONFIG */ +#endif /* BSP_UART3_RX_USING_DMA */ + +#if defined(BSP_UART3_TX_USING_DMA) +#ifndef UART3_DMA_TX_CONFIG +#define UART3_DMA_TX_CONFIG \ + { \ + .Instance = UART3_TX_DMA_INSTANCE, \ + .dma_rcc = UART3_TX_DMA_RCC, \ + .dma_irq = UART3_TX_DMA_IRQ, \ + .channel = UART3_TX_DMA_CHANNEL, \ + .request = UART3_TX_DMA_REQUEST, \ + } +#endif /* UART3_DMA_TX_CONFIG */ +#endif /* BSP_UART3_TX_USING_DMA */ +#endif /* RT_SERIAL_USING_DMA */ + +#ifndef UART3_CONFIG +#define UART3_CONFIG \ + { \ + .name = "uart3", \ + .Instance = UART3, \ + .irq_type = UART3_IRQn, \ + .enable_id = EN_UART3, \ + .tx_port = UART3_TX_PORT, \ + .rx_port = UART3_RX_PORT, \ + .tx_pin = UART3_TX_PIN, \ + .rx_pin = UART3_RX_PIN, \ + } +#endif /* UART3_CONFIG */ +#endif /* BSP_USING_UART3 */ + +#if defined(BSP_USING_UART4) + +#if defined(RT_SERIAL_USING_DMA) +#if defined(BSP_UART4_RX_USING_DMA) +#ifndef UART4_DMA_RX_CONFIG +#define UART4_DMA_RX_CONFIG \ + { \ + .Instance = UART4_RX_DMA_INSTANCE, \ + .dma_rcc = UART4_RX_DMA_RCC, \ + .dma_irq = UART4_RX_DMA_IRQ, \ + .channel = UART4_RX_DMA_CHANNEL, \ + .request = UART4_RX_DMA_REQUEST, \ + } +#endif /* UART4_DMA_RX_CONFIG */ +#endif /* BSP_UART4_RX_USING_DMA */ + +#if defined(BSP_UART4_TX_USING_DMA) +#ifndef UART4_DMA_TX_CONFIG +#define UART4_DMA_TX_CONFIG \ + { \ + .Instance = UART4_TX_DMA_INSTANCE, \ + .dma_rcc = UART4_TX_DMA_RCC, \ + .dma_irq = UART4_TX_DMA_IRQ, \ + .channel = UART4_TX_DMA_CHANNEL, \ + .request = UART4_TX_DMA_REQUEST, \ + } +#endif /* UART4_DMA_TX_CONFIG */ +#endif /* BSP_UART4_TX_USING_DMA */ +#endif /* RT_SERIAL_USING_DMA */ + +#ifndef UART4_CONFIG +#define UART4_CONFIG \ + { \ + .name = "uart4", \ + .Instance = UART4, \ + .irq_type = UART4_IRQn, \ + .enable_id = EN_UART4, \ + .tx_port = UART4_TX_PORT, \ + .rx_port = UART4_RX_PORT, \ + .tx_pin = UART4_TX_PIN, \ + .rx_pin = UART4_RX_PIN, \ + } +#endif /* UART4_CONFIG */ +#endif /* BSP_USING_UART4 */ + +#ifdef __cplusplus +} +#endif + +#endif /* RT_USING_SERIAL */ + +#endif /* __UART_CONFIG_H__ */ + diff --git a/bsp/acm32f4xx-nucleo/libraries/CMSIS/cmsis_armclang.h b/bsp/acm32f4xx-nucleo/libraries/CMSIS/cmsis_armclang.h new file mode 100644 index 0000000000..e917f357a3 --- /dev/null +++ b/bsp/acm32f4xx-nucleo/libraries/CMSIS/cmsis_armclang.h @@ -0,0 +1,1444 @@ +/**************************************************************************//** + * @file cmsis_armclang.h + * @brief CMSIS compiler armclang (Arm Compiler 6) header file + * @version V5.2.0 + * @date 08. May 2019 + ******************************************************************************/ +/* + * Copyright (c) 2009-2019 Arm Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +/*lint -esym(9058, IRQn)*/ /* disable MISRA 2012 Rule 2.4 for IRQn */ + +#ifndef __CMSIS_ARMCLANG_H +#define __CMSIS_ARMCLANG_H + +#pragma clang system_header /* treat file as system include file */ + +#ifndef __ARM_COMPAT_H +#include /* Compatibility header for Arm Compiler 5 intrinsics */ +#endif + +/* CMSIS compiler specific defines */ +#ifndef __ASM + #define __ASM __asm +#endif +#ifndef __INLINE + #define __INLINE __inline +#endif +#ifndef __STATIC_INLINE + #define __STATIC_INLINE static __inline +#endif +#ifndef __STATIC_FORCEINLINE + #define __STATIC_FORCEINLINE __attribute__((always_inline)) static __inline +#endif +#ifndef __NO_RETURN + #define __NO_RETURN __attribute__((__noreturn__)) +#endif +#ifndef __USED + #define __USED __attribute__((used)) +#endif +#ifndef __WEAK + #define __WEAK __attribute__((weak)) +#endif +#ifndef __PACKED + #define __PACKED __attribute__((packed, aligned(1))) +#endif +#ifndef __PACKED_STRUCT + #define __PACKED_STRUCT struct __attribute__((packed, aligned(1))) +#endif +#ifndef __PACKED_UNION + #define __PACKED_UNION union __attribute__((packed, aligned(1))) +#endif +#ifndef __UNALIGNED_UINT32 /* deprecated */ + #pragma clang diagnostic push + #pragma clang diagnostic ignored "-Wpacked" +/*lint -esym(9058, T_UINT32)*/ /* disable MISRA 2012 Rule 2.4 for T_UINT32 */ + struct __attribute__((packed)) T_UINT32 { uint32_t v; }; + #pragma clang diagnostic pop + #define __UNALIGNED_UINT32(x) (((struct T_UINT32 *)(x))->v) +#endif +#ifndef __UNALIGNED_UINT16_WRITE + #pragma clang diagnostic push + #pragma clang diagnostic ignored "-Wpacked" +/*lint -esym(9058, T_UINT16_WRITE)*/ /* disable MISRA 2012 Rule 2.4 for T_UINT16_WRITE */ + __PACKED_STRUCT T_UINT16_WRITE { uint16_t v; }; + #pragma clang diagnostic pop + #define __UNALIGNED_UINT16_WRITE(addr, val) (void)((((struct T_UINT16_WRITE *)(void *)(addr))->v) = (val)) +#endif +#ifndef __UNALIGNED_UINT16_READ + #pragma clang diagnostic push + #pragma clang diagnostic ignored "-Wpacked" +/*lint -esym(9058, T_UINT16_READ)*/ /* disable MISRA 2012 Rule 2.4 for T_UINT16_READ */ + __PACKED_STRUCT T_UINT16_READ { uint16_t v; }; + #pragma clang diagnostic pop + #define __UNALIGNED_UINT16_READ(addr) (((const struct T_UINT16_READ *)(const void *)(addr))->v) +#endif +#ifndef __UNALIGNED_UINT32_WRITE + #pragma clang diagnostic push + #pragma clang diagnostic ignored "-Wpacked" +/*lint -esym(9058, T_UINT32_WRITE)*/ /* disable MISRA 2012 Rule 2.4 for T_UINT32_WRITE */ + __PACKED_STRUCT T_UINT32_WRITE { uint32_t v; }; + #pragma clang diagnostic pop + #define __UNALIGNED_UINT32_WRITE(addr, val) (void)((((struct T_UINT32_WRITE *)(void *)(addr))->v) = (val)) +#endif +#ifndef __UNALIGNED_UINT32_READ + #pragma clang diagnostic push + #pragma clang diagnostic ignored "-Wpacked" +/*lint -esym(9058, T_UINT32_READ)*/ /* disable MISRA 2012 Rule 2.4 for T_UINT32_READ */ + __PACKED_STRUCT T_UINT32_READ { uint32_t v; }; + #pragma clang diagnostic pop + #define __UNALIGNED_UINT32_READ(addr) (((const struct T_UINT32_READ *)(const void *)(addr))->v) +#endif +#ifndef __ALIGNED + #define __ALIGNED(x) __attribute__((aligned(x))) +#endif +#ifndef __RESTRICT + #define __RESTRICT __restrict +#endif +#ifndef __COMPILER_BARRIER + #define __COMPILER_BARRIER() __ASM volatile("":::"memory") +#endif + +/* ######################### Startup and Lowlevel Init ######################## */ + +#ifndef __PROGRAM_START +#define __PROGRAM_START __main +#endif + +#ifndef __INITIAL_SP +#define __INITIAL_SP Image$$ARM_LIB_STACK$$ZI$$Limit +#endif + +#ifndef __STACK_LIMIT +#define __STACK_LIMIT Image$$ARM_LIB_STACK$$ZI$$Base +#endif + +#ifndef __VECTOR_TABLE +#define __VECTOR_TABLE __Vectors +#endif + +#ifndef __VECTOR_TABLE_ATTRIBUTE +#define __VECTOR_TABLE_ATTRIBUTE __attribute((used, section("RESET"))) +#endif + +/* ########################### Core Function Access ########################### */ +/** \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_RegAccFunctions CMSIS Core Register Access Functions + @{ + */ + +/** + \brief Enable IRQ Interrupts + \details Enables IRQ interrupts by clearing the I-bit in the CPSR. + Can only be executed in Privileged modes. + */ +/* intrinsic void __enable_irq(); see arm_compat.h */ + + +/** + \brief Disable IRQ Interrupts + \details Disables IRQ interrupts by setting the I-bit in the CPSR. + Can only be executed in Privileged modes. + */ +/* intrinsic void __disable_irq(); see arm_compat.h */ + + +/** + \brief Get Control Register + \details Returns the content of the Control Register. + \return Control Register value + */ +__STATIC_FORCEINLINE uint32_t __get_CONTROL(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, control" : "=r" (result) ); + return(result); +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Get Control Register (non-secure) + \details Returns the content of the non-secure Control Register when in secure mode. + \return non-secure Control Register value + */ +__STATIC_FORCEINLINE uint32_t __TZ_get_CONTROL_NS(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, control_ns" : "=r" (result) ); + return(result); +} +#endif + + +/** + \brief Set Control Register + \details Writes the given value to the Control Register. + \param [in] control Control Register value to set + */ +__STATIC_FORCEINLINE void __set_CONTROL(uint32_t control) +{ + __ASM volatile ("MSR control, %0" : : "r" (control) : "memory"); +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Set Control Register (non-secure) + \details Writes the given value to the non-secure Control Register when in secure state. + \param [in] control Control Register value to set + */ +__STATIC_FORCEINLINE void __TZ_set_CONTROL_NS(uint32_t control) +{ + __ASM volatile ("MSR control_ns, %0" : : "r" (control) : "memory"); +} +#endif + + +/** + \brief Get IPSR Register + \details Returns the content of the IPSR Register. + \return IPSR Register value + */ +__STATIC_FORCEINLINE uint32_t __get_IPSR(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, ipsr" : "=r" (result) ); + return(result); +} + + +/** + \brief Get APSR Register + \details Returns the content of the APSR Register. + \return APSR Register value + */ +__STATIC_FORCEINLINE uint32_t __get_APSR(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, apsr" : "=r" (result) ); + return(result); +} + + +/** + \brief Get xPSR Register + \details Returns the content of the xPSR Register. + \return xPSR Register value + */ +__STATIC_FORCEINLINE uint32_t __get_xPSR(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, xpsr" : "=r" (result) ); + return(result); +} + + +/** + \brief Get Process Stack Pointer + \details Returns the current value of the Process Stack Pointer (PSP). + \return PSP Register value + */ +__STATIC_FORCEINLINE uint32_t __get_PSP(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, psp" : "=r" (result) ); + return(result); +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Get Process Stack Pointer (non-secure) + \details Returns the current value of the non-secure Process Stack Pointer (PSP) when in secure state. + \return PSP Register value + */ +__STATIC_FORCEINLINE uint32_t __TZ_get_PSP_NS(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, psp_ns" : "=r" (result) ); + return(result); +} +#endif + + +/** + \brief Set Process Stack Pointer + \details Assigns the given value to the Process Stack Pointer (PSP). + \param [in] topOfProcStack Process Stack Pointer value to set + */ +__STATIC_FORCEINLINE void __set_PSP(uint32_t topOfProcStack) +{ + __ASM volatile ("MSR psp, %0" : : "r" (topOfProcStack) : ); +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Set Process Stack Pointer (non-secure) + \details Assigns the given value to the non-secure Process Stack Pointer (PSP) when in secure state. + \param [in] topOfProcStack Process Stack Pointer value to set + */ +__STATIC_FORCEINLINE void __TZ_set_PSP_NS(uint32_t topOfProcStack) +{ + __ASM volatile ("MSR psp_ns, %0" : : "r" (topOfProcStack) : ); +} +#endif + + +/** + \brief Get Main Stack Pointer + \details Returns the current value of the Main Stack Pointer (MSP). + \return MSP Register value + */ +__STATIC_FORCEINLINE uint32_t __get_MSP(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, msp" : "=r" (result) ); + return(result); +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Get Main Stack Pointer (non-secure) + \details Returns the current value of the non-secure Main Stack Pointer (MSP) when in secure state. + \return MSP Register value + */ +__STATIC_FORCEINLINE uint32_t __TZ_get_MSP_NS(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, msp_ns" : "=r" (result) ); + return(result); +} +#endif + + +/** + \brief Set Main Stack Pointer + \details Assigns the given value to the Main Stack Pointer (MSP). + \param [in] topOfMainStack Main Stack Pointer value to set + */ +__STATIC_FORCEINLINE void __set_MSP(uint32_t topOfMainStack) +{ + __ASM volatile ("MSR msp, %0" : : "r" (topOfMainStack) : ); +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Set Main Stack Pointer (non-secure) + \details Assigns the given value to the non-secure Main Stack Pointer (MSP) when in secure state. + \param [in] topOfMainStack Main Stack Pointer value to set + */ +__STATIC_FORCEINLINE void __TZ_set_MSP_NS(uint32_t topOfMainStack) +{ + __ASM volatile ("MSR msp_ns, %0" : : "r" (topOfMainStack) : ); +} +#endif + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Get Stack Pointer (non-secure) + \details Returns the current value of the non-secure Stack Pointer (SP) when in secure state. + \return SP Register value + */ +__STATIC_FORCEINLINE uint32_t __TZ_get_SP_NS(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, sp_ns" : "=r" (result) ); + return(result); +} + + +/** + \brief Set Stack Pointer (non-secure) + \details Assigns the given value to the non-secure Stack Pointer (SP) when in secure state. + \param [in] topOfStack Stack Pointer value to set + */ +__STATIC_FORCEINLINE void __TZ_set_SP_NS(uint32_t topOfStack) +{ + __ASM volatile ("MSR sp_ns, %0" : : "r" (topOfStack) : ); +} +#endif + + +/** + \brief Get Priority Mask + \details Returns the current state of the priority mask bit from the Priority Mask Register. + \return Priority Mask value + */ +__STATIC_FORCEINLINE uint32_t __get_PRIMASK(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, primask" : "=r" (result) ); + return(result); +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Get Priority Mask (non-secure) + \details Returns the current state of the non-secure priority mask bit from the Priority Mask Register when in secure state. + \return Priority Mask value + */ +__STATIC_FORCEINLINE uint32_t __TZ_get_PRIMASK_NS(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, primask_ns" : "=r" (result) ); + return(result); +} +#endif + + +/** + \brief Set Priority Mask + \details Assigns the given value to the Priority Mask Register. + \param [in] priMask Priority Mask + */ +__STATIC_FORCEINLINE void __set_PRIMASK(uint32_t priMask) +{ + __ASM volatile ("MSR primask, %0" : : "r" (priMask) : "memory"); +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Set Priority Mask (non-secure) + \details Assigns the given value to the non-secure Priority Mask Register when in secure state. + \param [in] priMask Priority Mask + */ +__STATIC_FORCEINLINE void __TZ_set_PRIMASK_NS(uint32_t priMask) +{ + __ASM volatile ("MSR primask_ns, %0" : : "r" (priMask) : "memory"); +} +#endif + + +#if ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \ + (defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) || \ + (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) ) +/** + \brief Enable FIQ + \details Enables FIQ interrupts by clearing the F-bit in the CPSR. + Can only be executed in Privileged modes. + */ +#define __enable_fault_irq __enable_fiq /* see arm_compat.h */ + + +/** + \brief Disable FIQ + \details Disables FIQ interrupts by setting the F-bit in the CPSR. + Can only be executed in Privileged modes. + */ +#define __disable_fault_irq __disable_fiq /* see arm_compat.h */ + + +/** + \brief Get Base Priority + \details Returns the current value of the Base Priority register. + \return Base Priority register value + */ +__STATIC_FORCEINLINE uint32_t __get_BASEPRI(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, basepri" : "=r" (result) ); + return(result); +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Get Base Priority (non-secure) + \details Returns the current value of the non-secure Base Priority register when in secure state. + \return Base Priority register value + */ +__STATIC_FORCEINLINE uint32_t __TZ_get_BASEPRI_NS(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, basepri_ns" : "=r" (result) ); + return(result); +} +#endif + + +/** + \brief Set Base Priority + \details Assigns the given value to the Base Priority register. + \param [in] basePri Base Priority value to set + */ +__STATIC_FORCEINLINE void __set_BASEPRI(uint32_t basePri) +{ + __ASM volatile ("MSR basepri, %0" : : "r" (basePri) : "memory"); +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Set Base Priority (non-secure) + \details Assigns the given value to the non-secure Base Priority register when in secure state. + \param [in] basePri Base Priority value to set + */ +__STATIC_FORCEINLINE void __TZ_set_BASEPRI_NS(uint32_t basePri) +{ + __ASM volatile ("MSR basepri_ns, %0" : : "r" (basePri) : "memory"); +} +#endif + + +/** + \brief Set Base Priority with condition + \details Assigns the given value to the Base Priority register only if BASEPRI masking is disabled, + or the new value increases the BASEPRI priority level. + \param [in] basePri Base Priority value to set + */ +__STATIC_FORCEINLINE void __set_BASEPRI_MAX(uint32_t basePri) +{ + __ASM volatile ("MSR basepri_max, %0" : : "r" (basePri) : "memory"); +} + + +/** + \brief Get Fault Mask + \details Returns the current value of the Fault Mask register. + \return Fault Mask register value + */ +__STATIC_FORCEINLINE uint32_t __get_FAULTMASK(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, faultmask" : "=r" (result) ); + return(result); +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Get Fault Mask (non-secure) + \details Returns the current value of the non-secure Fault Mask register when in secure state. + \return Fault Mask register value + */ +__STATIC_FORCEINLINE uint32_t __TZ_get_FAULTMASK_NS(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, faultmask_ns" : "=r" (result) ); + return(result); +} +#endif + + +/** + \brief Set Fault Mask + \details Assigns the given value to the Fault Mask register. + \param [in] faultMask Fault Mask value to set + */ +__STATIC_FORCEINLINE void __set_FAULTMASK(uint32_t faultMask) +{ + __ASM volatile ("MSR faultmask, %0" : : "r" (faultMask) : "memory"); +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Set Fault Mask (non-secure) + \details Assigns the given value to the non-secure Fault Mask register when in secure state. + \param [in] faultMask Fault Mask value to set + */ +__STATIC_FORCEINLINE void __TZ_set_FAULTMASK_NS(uint32_t faultMask) +{ + __ASM volatile ("MSR faultmask_ns, %0" : : "r" (faultMask) : "memory"); +} +#endif + +#endif /* ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \ + (defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) || \ + (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) ) */ + + +#if ((defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \ + (defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1)) ) + +/** + \brief Get Process Stack Pointer Limit + Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure + Stack Pointer Limit register hence zero is returned always in non-secure + mode. + + \details Returns the current value of the Process Stack Pointer Limit (PSPLIM). + \return PSPLIM Register value + */ +__STATIC_FORCEINLINE uint32_t __get_PSPLIM(void) +{ +#if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \ + (!defined (__ARM_FEATURE_CMSE) || (__ARM_FEATURE_CMSE < 3))) + // without main extensions, the non-secure PSPLIM is RAZ/WI + return 0U; +#else + uint32_t result; + __ASM volatile ("MRS %0, psplim" : "=r" (result) ); + return result; +#endif +} + +#if (defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Get Process Stack Pointer Limit (non-secure) + Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure + Stack Pointer Limit register hence zero is returned always in non-secure + mode. + + \details Returns the current value of the non-secure Process Stack Pointer Limit (PSPLIM) when in secure state. + \return PSPLIM Register value + */ +__STATIC_FORCEINLINE uint32_t __TZ_get_PSPLIM_NS(void) +{ +#if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1))) + // without main extensions, the non-secure PSPLIM is RAZ/WI + return 0U; +#else + uint32_t result; + __ASM volatile ("MRS %0, psplim_ns" : "=r" (result) ); + return result; +#endif +} +#endif + + +/** + \brief Set Process Stack Pointer Limit + Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure + Stack Pointer Limit register hence the write is silently ignored in non-secure + mode. + + \details Assigns the given value to the Process Stack Pointer Limit (PSPLIM). + \param [in] ProcStackPtrLimit Process Stack Pointer Limit value to set + */ +__STATIC_FORCEINLINE void __set_PSPLIM(uint32_t ProcStackPtrLimit) +{ +#if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \ + (!defined (__ARM_FEATURE_CMSE) || (__ARM_FEATURE_CMSE < 3))) + // without main extensions, the non-secure PSPLIM is RAZ/WI + (void)ProcStackPtrLimit; +#else + __ASM volatile ("MSR psplim, %0" : : "r" (ProcStackPtrLimit)); +#endif +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Set Process Stack Pointer (non-secure) + Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure + Stack Pointer Limit register hence the write is silently ignored in non-secure + mode. + + \details Assigns the given value to the non-secure Process Stack Pointer Limit (PSPLIM) when in secure state. + \param [in] ProcStackPtrLimit Process Stack Pointer Limit value to set + */ +__STATIC_FORCEINLINE void __TZ_set_PSPLIM_NS(uint32_t ProcStackPtrLimit) +{ +#if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1))) + // without main extensions, the non-secure PSPLIM is RAZ/WI + (void)ProcStackPtrLimit; +#else + __ASM volatile ("MSR psplim_ns, %0\n" : : "r" (ProcStackPtrLimit)); +#endif +} +#endif + + +/** + \brief Get Main Stack Pointer Limit + Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure + Stack Pointer Limit register hence zero is returned always. + + \details Returns the current value of the Main Stack Pointer Limit (MSPLIM). + \return MSPLIM Register value + */ +__STATIC_FORCEINLINE uint32_t __get_MSPLIM(void) +{ +#if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \ + (!defined (__ARM_FEATURE_CMSE) || (__ARM_FEATURE_CMSE < 3))) + // without main extensions, the non-secure MSPLIM is RAZ/WI + return 0U; +#else + uint32_t result; + __ASM volatile ("MRS %0, msplim" : "=r" (result) ); + return result; +#endif +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Get Main Stack Pointer Limit (non-secure) + Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure + Stack Pointer Limit register hence zero is returned always. + + \details Returns the current value of the non-secure Main Stack Pointer Limit(MSPLIM) when in secure state. + \return MSPLIM Register value + */ +__STATIC_FORCEINLINE uint32_t __TZ_get_MSPLIM_NS(void) +{ +#if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1))) + // without main extensions, the non-secure MSPLIM is RAZ/WI + return 0U; +#else + uint32_t result; + __ASM volatile ("MRS %0, msplim_ns" : "=r" (result) ); + return result; +#endif +} +#endif + + +/** + \brief Set Main Stack Pointer Limit + Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure + Stack Pointer Limit register hence the write is silently ignored. + + \details Assigns the given value to the Main Stack Pointer Limit (MSPLIM). + \param [in] MainStackPtrLimit Main Stack Pointer Limit value to set + */ +__STATIC_FORCEINLINE void __set_MSPLIM(uint32_t MainStackPtrLimit) +{ +#if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \ + (!defined (__ARM_FEATURE_CMSE) || (__ARM_FEATURE_CMSE < 3))) + // without main extensions, the non-secure MSPLIM is RAZ/WI + (void)MainStackPtrLimit; +#else + __ASM volatile ("MSR msplim, %0" : : "r" (MainStackPtrLimit)); +#endif +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Set Main Stack Pointer Limit (non-secure) + Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure + Stack Pointer Limit register hence the write is silently ignored. + + \details Assigns the given value to the non-secure Main Stack Pointer Limit (MSPLIM) when in secure state. + \param [in] MainStackPtrLimit Main Stack Pointer value to set + */ +__STATIC_FORCEINLINE void __TZ_set_MSPLIM_NS(uint32_t MainStackPtrLimit) +{ +#if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1))) + // without main extensions, the non-secure MSPLIM is RAZ/WI + (void)MainStackPtrLimit; +#else + __ASM volatile ("MSR msplim_ns, %0" : : "r" (MainStackPtrLimit)); +#endif +} +#endif + +#endif /* ((defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \ + (defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1)) ) */ + +/** + \brief Get FPSCR + \details Returns the current value of the Floating Point Status/Control register. + \return Floating Point Status/Control register value + */ +#if ((defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)) && \ + (defined (__FPU_USED ) && (__FPU_USED == 1U)) ) +#define __get_FPSCR (uint32_t)__builtin_arm_get_fpscr +#else +#define __get_FPSCR() ((uint32_t)0U) +#endif + +/** + \brief Set FPSCR + \details Assigns the given value to the Floating Point Status/Control register. + \param [in] fpscr Floating Point Status/Control value to set + */ +#if ((defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)) && \ + (defined (__FPU_USED ) && (__FPU_USED == 1U)) ) +#define __set_FPSCR __builtin_arm_set_fpscr +#else +#define __set_FPSCR(x) ((void)(x)) +#endif + + +/*@} end of CMSIS_Core_RegAccFunctions */ + + +/* ########################## Core Instruction Access ######################### */ +/** \defgroup CMSIS_Core_InstructionInterface CMSIS Core Instruction Interface + Access to dedicated instructions + @{ +*/ + +/* Define macros for porting to both thumb1 and thumb2. + * For thumb1, use low register (r0-r7), specified by constraint "l" + * Otherwise, use general registers, specified by constraint "r" */ +#if defined (__thumb__) && !defined (__thumb2__) +#define __CMSIS_GCC_OUT_REG(r) "=l" (r) +#define __CMSIS_GCC_RW_REG(r) "+l" (r) +#define __CMSIS_GCC_USE_REG(r) "l" (r) +#else +#define __CMSIS_GCC_OUT_REG(r) "=r" (r) +#define __CMSIS_GCC_RW_REG(r) "+r" (r) +#define __CMSIS_GCC_USE_REG(r) "r" (r) +#endif + +/** + \brief No Operation + \details No Operation does nothing. This instruction can be used for code alignment purposes. + */ +#define __NOP __builtin_arm_nop + +/** + \brief Wait For Interrupt + \details Wait For Interrupt is a hint instruction that suspends execution until one of a number of events occurs. + */ +#define __WFI __builtin_arm_wfi + + +/** + \brief Wait For Event + \details Wait For Event is a hint instruction that permits the processor to enter + a low-power state until one of a number of events occurs. + */ +#define __WFE __builtin_arm_wfe + + +/** + \brief Send Event + \details Send Event is a hint instruction. It causes an event to be signaled to the CPU. + */ +#define __SEV __builtin_arm_sev + + +/** + \brief Instruction Synchronization Barrier + \details Instruction Synchronization Barrier flushes the pipeline in the processor, + so that all instructions following the ISB are fetched from cache or memory, + after the instruction has been completed. + */ +#define __ISB() __builtin_arm_isb(0xF) + +/** + \brief Data Synchronization Barrier + \details Acts as a special kind of Data Memory Barrier. + It completes when all explicit memory accesses before this instruction complete. + */ +#define __DSB() __builtin_arm_dsb(0xF) + + +/** + \brief Data Memory Barrier + \details Ensures the apparent order of the explicit memory operations before + and after the instruction, without ensuring their completion. + */ +#define __DMB() __builtin_arm_dmb(0xF) + + +/** + \brief Reverse byte order (32 bit) + \details Reverses the byte order in unsigned integer value. For example, 0x12345678 becomes 0x78563412. + \param [in] value Value to reverse + \return Reversed value + */ +#define __REV(value) __builtin_bswap32(value) + + +/** + \brief Reverse byte order (16 bit) + \details Reverses the byte order within each halfword of a word. For example, 0x12345678 becomes 0x34127856. + \param [in] value Value to reverse + \return Reversed value + */ +#define __REV16(value) __ROR(__REV(value), 16) + + +/** + \brief Reverse byte order (16 bit) + \details Reverses the byte order in a 16-bit value and returns the signed 16-bit result. For example, 0x0080 becomes 0x8000. + \param [in] value Value to reverse + \return Reversed value + */ +#define __REVSH(value) (int16_t)__builtin_bswap16(value) + + +/** + \brief Rotate Right in unsigned value (32 bit) + \details Rotate Right (immediate) provides the value of the contents of a register rotated by a variable number of bits. + \param [in] op1 Value to rotate + \param [in] op2 Number of Bits to rotate + \return Rotated value + */ +__STATIC_FORCEINLINE uint32_t __ROR(uint32_t op1, uint32_t op2) +{ + op2 %= 32U; + if (op2 == 0U) + { + return op1; + } + return (op1 >> op2) | (op1 << (32U - op2)); +} + + +/** + \brief Breakpoint + \details Causes the processor to enter Debug state. + Debug tools can use this to investigate system state when the instruction at a particular address is reached. + \param [in] value is ignored by the processor. + If required, a debugger can use it to store additional information about the breakpoint. + */ +#define __BKPT(value) __ASM volatile ("bkpt "#value) + + +/** + \brief Reverse bit order of value + \details Reverses the bit order of the given value. + \param [in] value Value to reverse + \return Reversed value + */ +#define __RBIT __builtin_arm_rbit + +/** + \brief Count leading zeros + \details Counts the number of leading zeros of a data value. + \param [in] value Value to count the leading zeros + \return number of leading zeros in value + */ +__STATIC_FORCEINLINE uint8_t __CLZ(uint32_t value) +{ + /* Even though __builtin_clz produces a CLZ instruction on ARM, formally + __builtin_clz(0) is undefined behaviour, so handle this case specially. + This guarantees ARM-compatible results if happening to compile on a non-ARM + target, and ensures the compiler doesn't decide to activate any + optimisations using the logic "value was passed to __builtin_clz, so it + is non-zero". + ARM Compiler 6.10 and possibly earlier will optimise this test away, leaving a + single CLZ instruction. + */ + if (value == 0U) + { + return 32U; + } + return __builtin_clz(value); +} + + +#if ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \ + (defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) || \ + (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \ + (defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1)) ) +/** + \brief LDR Exclusive (8 bit) + \details Executes a exclusive LDR instruction for 8 bit value. + \param [in] ptr Pointer to data + \return value of type uint8_t at (*ptr) + */ +#define __LDREXB (uint8_t)__builtin_arm_ldrex + + +/** + \brief LDR Exclusive (16 bit) + \details Executes a exclusive LDR instruction for 16 bit values. + \param [in] ptr Pointer to data + \return value of type uint16_t at (*ptr) + */ +#define __LDREXH (uint16_t)__builtin_arm_ldrex + + +/** + \brief LDR Exclusive (32 bit) + \details Executes a exclusive LDR instruction for 32 bit values. + \param [in] ptr Pointer to data + \return value of type uint32_t at (*ptr) + */ +#define __LDREXW (uint32_t)__builtin_arm_ldrex + + +/** + \brief STR Exclusive (8 bit) + \details Executes a exclusive STR instruction for 8 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + \return 0 Function succeeded + \return 1 Function failed + */ +#define __STREXB (uint32_t)__builtin_arm_strex + + +/** + \brief STR Exclusive (16 bit) + \details Executes a exclusive STR instruction for 16 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + \return 0 Function succeeded + \return 1 Function failed + */ +#define __STREXH (uint32_t)__builtin_arm_strex + + +/** + \brief STR Exclusive (32 bit) + \details Executes a exclusive STR instruction for 32 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + \return 0 Function succeeded + \return 1 Function failed + */ +#define __STREXW (uint32_t)__builtin_arm_strex + + +/** + \brief Remove the exclusive lock + \details Removes the exclusive lock which is created by LDREX. + */ +#define __CLREX __builtin_arm_clrex + +#endif /* ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \ + (defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) || \ + (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \ + (defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1)) ) */ + + +#if ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \ + (defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) || \ + (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) ) + +/** + \brief Signed Saturate + \details Saturates a signed value. + \param [in] value Value to be saturated + \param [in] sat Bit position to saturate to (1..32) + \return Saturated value + */ +#define __SSAT __builtin_arm_ssat + + +/** + \brief Unsigned Saturate + \details Saturates an unsigned value. + \param [in] value Value to be saturated + \param [in] sat Bit position to saturate to (0..31) + \return Saturated value + */ +#define __USAT __builtin_arm_usat + + +/** + \brief Rotate Right with Extend (32 bit) + \details Moves each bit of a bitstring right by one bit. + The carry input is shifted in at the left end of the bitstring. + \param [in] value Value to rotate + \return Rotated value + */ +__STATIC_FORCEINLINE uint32_t __RRX(uint32_t value) +{ + uint32_t result; + + __ASM volatile ("rrx %0, %1" : __CMSIS_GCC_OUT_REG (result) : __CMSIS_GCC_USE_REG (value) ); + return(result); +} + + +/** + \brief LDRT Unprivileged (8 bit) + \details Executes a Unprivileged LDRT instruction for 8 bit value. + \param [in] ptr Pointer to data + \return value of type uint8_t at (*ptr) + */ +__STATIC_FORCEINLINE uint8_t __LDRBT(volatile uint8_t *ptr) +{ + uint32_t result; + + __ASM volatile ("ldrbt %0, %1" : "=r" (result) : "Q" (*ptr) ); + return ((uint8_t) result); /* Add explicit type cast here */ +} + + +/** + \brief LDRT Unprivileged (16 bit) + \details Executes a Unprivileged LDRT instruction for 16 bit values. + \param [in] ptr Pointer to data + \return value of type uint16_t at (*ptr) + */ +__STATIC_FORCEINLINE uint16_t __LDRHT(volatile uint16_t *ptr) +{ + uint32_t result; + + __ASM volatile ("ldrht %0, %1" : "=r" (result) : "Q" (*ptr) ); + return ((uint16_t) result); /* Add explicit type cast here */ +} + + +/** + \brief LDRT Unprivileged (32 bit) + \details Executes a Unprivileged LDRT instruction for 32 bit values. + \param [in] ptr Pointer to data + \return value of type uint32_t at (*ptr) + */ +__STATIC_FORCEINLINE uint32_t __LDRT(volatile uint32_t *ptr) +{ + uint32_t result; + + __ASM volatile ("ldrt %0, %1" : "=r" (result) : "Q" (*ptr) ); + return(result); +} + + +/** + \brief STRT Unprivileged (8 bit) + \details Executes a Unprivileged STRT instruction for 8 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + */ +__STATIC_FORCEINLINE void __STRBT(uint8_t value, volatile uint8_t *ptr) +{ + __ASM volatile ("strbt %1, %0" : "=Q" (*ptr) : "r" ((uint32_t)value) ); +} + + +/** + \brief STRT Unprivileged (16 bit) + \details Executes a Unprivileged STRT instruction for 16 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + */ +__STATIC_FORCEINLINE void __STRHT(uint16_t value, volatile uint16_t *ptr) +{ + __ASM volatile ("strht %1, %0" : "=Q" (*ptr) : "r" ((uint32_t)value) ); +} + + +/** + \brief STRT Unprivileged (32 bit) + \details Executes a Unprivileged STRT instruction for 32 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + */ +__STATIC_FORCEINLINE void __STRT(uint32_t value, volatile uint32_t *ptr) +{ + __ASM volatile ("strt %1, %0" : "=Q" (*ptr) : "r" (value) ); +} + +#else /* ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \ + (defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) || \ + (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) ) */ + +/** + \brief Signed Saturate + \details Saturates a signed value. + \param [in] value Value to be saturated + \param [in] sat Bit position to saturate to (1..32) + \return Saturated value + */ +__STATIC_FORCEINLINE int32_t __SSAT(int32_t val, uint32_t sat) +{ + if ((sat >= 1U) && (sat <= 32U)) + { + const int32_t max = (int32_t)((1U << (sat - 1U)) - 1U); + const int32_t min = -1 - max ; + if (val > max) + { + return max; + } + else if (val < min) + { + return min; + } + } + return val; +} + +/** + \brief Unsigned Saturate + \details Saturates an unsigned value. + \param [in] value Value to be saturated + \param [in] sat Bit position to saturate to (0..31) + \return Saturated value + */ +__STATIC_FORCEINLINE uint32_t __USAT(int32_t val, uint32_t sat) +{ + if (sat <= 31U) + { + const uint32_t max = ((1U << sat) - 1U); + if (val > (int32_t)max) + { + return max; + } + else if (val < 0) + { + return 0U; + } + } + return (uint32_t)val; +} + +#endif /* ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \ + (defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) || \ + (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) ) */ + + +#if ((defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \ + (defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1)) ) +/** + \brief Load-Acquire (8 bit) + \details Executes a LDAB instruction for 8 bit value. + \param [in] ptr Pointer to data + \return value of type uint8_t at (*ptr) + */ +__STATIC_FORCEINLINE uint8_t __LDAB(volatile uint8_t *ptr) +{ + uint32_t result; + + __ASM volatile ("ldab %0, %1" : "=r" (result) : "Q" (*ptr) ); + return ((uint8_t) result); +} + + +/** + \brief Load-Acquire (16 bit) + \details Executes a LDAH instruction for 16 bit values. + \param [in] ptr Pointer to data + \return value of type uint16_t at (*ptr) + */ +__STATIC_FORCEINLINE uint16_t __LDAH(volatile uint16_t *ptr) +{ + uint32_t result; + + __ASM volatile ("ldah %0, %1" : "=r" (result) : "Q" (*ptr) ); + return ((uint16_t) result); +} + + +/** + \brief Load-Acquire (32 bit) + \details Executes a LDA instruction for 32 bit values. + \param [in] ptr Pointer to data + \return value of type uint32_t at (*ptr) + */ +__STATIC_FORCEINLINE uint32_t __LDA(volatile uint32_t *ptr) +{ + uint32_t result; + + __ASM volatile ("lda %0, %1" : "=r" (result) : "Q" (*ptr) ); + return(result); +} + + +/** + \brief Store-Release (8 bit) + \details Executes a STLB instruction for 8 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + */ +__STATIC_FORCEINLINE void __STLB(uint8_t value, volatile uint8_t *ptr) +{ + __ASM volatile ("stlb %1, %0" : "=Q" (*ptr) : "r" ((uint32_t)value) ); +} + + +/** + \brief Store-Release (16 bit) + \details Executes a STLH instruction for 16 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + */ +__STATIC_FORCEINLINE void __STLH(uint16_t value, volatile uint16_t *ptr) +{ + __ASM volatile ("stlh %1, %0" : "=Q" (*ptr) : "r" ((uint32_t)value) ); +} + + +/** + \brief Store-Release (32 bit) + \details Executes a STL instruction for 32 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + */ +__STATIC_FORCEINLINE void __STL(uint32_t value, volatile uint32_t *ptr) +{ + __ASM volatile ("stl %1, %0" : "=Q" (*ptr) : "r" ((uint32_t)value) ); +} + + +/** + \brief Load-Acquire Exclusive (8 bit) + \details Executes a LDAB exclusive instruction for 8 bit value. + \param [in] ptr Pointer to data + \return value of type uint8_t at (*ptr) + */ +#define __LDAEXB (uint8_t)__builtin_arm_ldaex + + +/** + \brief Load-Acquire Exclusive (16 bit) + \details Executes a LDAH exclusive instruction for 16 bit values. + \param [in] ptr Pointer to data + \return value of type uint16_t at (*ptr) + */ +#define __LDAEXH (uint16_t)__builtin_arm_ldaex + + +/** + \brief Load-Acquire Exclusive (32 bit) + \details Executes a LDA exclusive instruction for 32 bit values. + \param [in] ptr Pointer to data + \return value of type uint32_t at (*ptr) + */ +#define __LDAEX (uint32_t)__builtin_arm_ldaex + + +/** + \brief Store-Release Exclusive (8 bit) + \details Executes a STLB exclusive instruction for 8 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + \return 0 Function succeeded + \return 1 Function failed + */ +#define __STLEXB (uint32_t)__builtin_arm_stlex + + +/** + \brief Store-Release Exclusive (16 bit) + \details Executes a STLH exclusive instruction for 16 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + \return 0 Function succeeded + \return 1 Function failed + */ +#define __STLEXH (uint32_t)__builtin_arm_stlex + + +/** + \brief Store-Release Exclusive (32 bit) + \details Executes a STL exclusive instruction for 32 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + \return 0 Function succeeded + \return 1 Function failed + */ +#define __STLEX (uint32_t)__builtin_arm_stlex + +#endif /* ((defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \ + (defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1)) ) */ + +/*@}*/ /* end of group CMSIS_Core_InstructionInterface */ + + +/* ################### Compiler specific Intrinsics ########################### */ +/** \defgroup CMSIS_SIMD_intrinsics CMSIS SIMD Intrinsics + Access to dedicated SIMD instructions + @{ +*/ + +#if (defined (__ARM_FEATURE_DSP) && (__ARM_FEATURE_DSP == 1)) + +#define __SADD8 __builtin_arm_sadd8 +#define __QADD8 __builtin_arm_qadd8 +#define __SHADD8 __builtin_arm_shadd8 +#define __UADD8 __builtin_arm_uadd8 +#define __UQADD8 __builtin_arm_uqadd8 +#define __UHADD8 __builtin_arm_uhadd8 +#define __SSUB8 __builtin_arm_ssub8 +#define __QSUB8 __builtin_arm_qsub8 +#define __SHSUB8 __builtin_arm_shsub8 +#define __USUB8 __builtin_arm_usub8 +#define __UQSUB8 __builtin_arm_uqsub8 +#define __UHSUB8 __builtin_arm_uhsub8 +#define __SADD16 __builtin_arm_sadd16 +#define __QADD16 __builtin_arm_qadd16 +#define __SHADD16 __builtin_arm_shadd16 +#define __UADD16 __builtin_arm_uadd16 +#define __UQADD16 __builtin_arm_uqadd16 +#define __UHADD16 __builtin_arm_uhadd16 +#define __SSUB16 __builtin_arm_ssub16 +#define __QSUB16 __builtin_arm_qsub16 +#define __SHSUB16 __builtin_arm_shsub16 +#define __USUB16 __builtin_arm_usub16 +#define __UQSUB16 __builtin_arm_uqsub16 +#define __UHSUB16 __builtin_arm_uhsub16 +#define __SASX __builtin_arm_sasx +#define __QASX __builtin_arm_qasx +#define __SHASX __builtin_arm_shasx +#define __UASX __builtin_arm_uasx +#define __UQASX __builtin_arm_uqasx +#define __UHASX __builtin_arm_uhasx +#define __SSAX __builtin_arm_ssax +#define __QSAX __builtin_arm_qsax +#define __SHSAX __builtin_arm_shsax +#define __USAX __builtin_arm_usax +#define __UQSAX __builtin_arm_uqsax +#define __UHSAX __builtin_arm_uhsax +#define __USAD8 __builtin_arm_usad8 +#define __USADA8 __builtin_arm_usada8 +#define __SSAT16 __builtin_arm_ssat16 +#define __USAT16 __builtin_arm_usat16 +#define __UXTB16 __builtin_arm_uxtb16 +#define __UXTAB16 __builtin_arm_uxtab16 +#define __SXTB16 __builtin_arm_sxtb16 +#define __SXTAB16 __builtin_arm_sxtab16 +#define __SMUAD __builtin_arm_smuad +#define __SMUADX __builtin_arm_smuadx +#define __SMLAD __builtin_arm_smlad +#define __SMLADX __builtin_arm_smladx +#define __SMLALD __builtin_arm_smlald +#define __SMLALDX __builtin_arm_smlaldx +#define __SMUSD __builtin_arm_smusd +#define __SMUSDX __builtin_arm_smusdx +#define __SMLSD __builtin_arm_smlsd +#define __SMLSDX __builtin_arm_smlsdx +#define __SMLSLD __builtin_arm_smlsld +#define __SMLSLDX __builtin_arm_smlsldx +#define __SEL __builtin_arm_sel +#define __QADD __builtin_arm_qadd +#define __QSUB __builtin_arm_qsub + +#define __PKHBT(ARG1,ARG2,ARG3) ( ((((uint32_t)(ARG1)) ) & 0x0000FFFFUL) | \ + ((((uint32_t)(ARG2)) << (ARG3)) & 0xFFFF0000UL) ) + +#define __PKHTB(ARG1,ARG2,ARG3) ( ((((uint32_t)(ARG1)) ) & 0xFFFF0000UL) | \ + ((((uint32_t)(ARG2)) >> (ARG3)) & 0x0000FFFFUL) ) + +__STATIC_FORCEINLINE int32_t __SMMLA (int32_t op1, int32_t op2, int32_t op3) +{ + int32_t result; + + __ASM volatile ("smmla %0, %1, %2, %3" : "=r" (result): "r" (op1), "r" (op2), "r" (op3) ); + return(result); +} + +#endif /* (__ARM_FEATURE_DSP == 1) */ +/*@} end of group CMSIS_SIMD_intrinsics */ + + +#endif /* __CMSIS_ARMCLANG_H */ diff --git a/bsp/acm32f4xx-nucleo/libraries/CMSIS/cmsis_compiler.h b/bsp/acm32f4xx-nucleo/libraries/CMSIS/cmsis_compiler.h new file mode 100644 index 0000000000..adbf296f15 --- /dev/null +++ b/bsp/acm32f4xx-nucleo/libraries/CMSIS/cmsis_compiler.h @@ -0,0 +1,283 @@ +/**************************************************************************//** + * @file cmsis_compiler.h + * @brief CMSIS compiler generic header file + * @version V5.1.0 + * @date 09. October 2018 + ******************************************************************************/ +/* + * Copyright (c) 2009-2018 Arm Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#ifndef __CMSIS_COMPILER_H +#define __CMSIS_COMPILER_H + +#include + +/* + * Arm Compiler 4/5 + */ +#if defined ( __CC_ARM ) + #include "cmsis_armcc.h" + + +/* + * Arm Compiler 6.6 LTM (armclang) + */ +#elif defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) && (__ARMCC_VERSION < 6100100) + #include "cmsis_armclang_ltm.h" + + /* + * Arm Compiler above 6.10.1 (armclang) + */ +#elif defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6100100) + #include "cmsis_armclang.h" + + +/* + * GNU Compiler + */ +#elif defined ( __GNUC__ ) + #include "cmsis_gcc.h" + + +/* + * IAR Compiler + */ +#elif defined ( __ICCARM__ ) + #include + + +/* + * TI Arm Compiler + */ +#elif defined ( __TI_ARM__ ) + #include + + #ifndef __ASM + #define __ASM __asm + #endif + #ifndef __INLINE + #define __INLINE inline + #endif + #ifndef __STATIC_INLINE + #define __STATIC_INLINE static inline + #endif + #ifndef __STATIC_FORCEINLINE + #define __STATIC_FORCEINLINE __STATIC_INLINE + #endif + #ifndef __NO_RETURN + #define __NO_RETURN __attribute__((noreturn)) + #endif + #ifndef __USED + #define __USED __attribute__((used)) + #endif + #ifndef __WEAK + #define __WEAK __attribute__((weak)) + #endif + #ifndef __PACKED + #define __PACKED __attribute__((packed)) + #endif + #ifndef __PACKED_STRUCT + #define __PACKED_STRUCT struct __attribute__((packed)) + #endif + #ifndef __PACKED_UNION + #define __PACKED_UNION union __attribute__((packed)) + #endif + #ifndef __UNALIGNED_UINT32 /* deprecated */ + struct __attribute__((packed)) T_UINT32 { uint32_t v; }; + #define __UNALIGNED_UINT32(x) (((struct T_UINT32 *)(x))->v) + #endif + #ifndef __UNALIGNED_UINT16_WRITE + __PACKED_STRUCT T_UINT16_WRITE { uint16_t v; }; + #define __UNALIGNED_UINT16_WRITE(addr, val) (void)((((struct T_UINT16_WRITE *)(void*)(addr))->v) = (val)) + #endif + #ifndef __UNALIGNED_UINT16_READ + __PACKED_STRUCT T_UINT16_READ { uint16_t v; }; + #define __UNALIGNED_UINT16_READ(addr) (((const struct T_UINT16_READ *)(const void *)(addr))->v) + #endif + #ifndef __UNALIGNED_UINT32_WRITE + __PACKED_STRUCT T_UINT32_WRITE { uint32_t v; }; + #define __UNALIGNED_UINT32_WRITE(addr, val) (void)((((struct T_UINT32_WRITE *)(void *)(addr))->v) = (val)) + #endif + #ifndef __UNALIGNED_UINT32_READ + __PACKED_STRUCT T_UINT32_READ { uint32_t v; }; + #define __UNALIGNED_UINT32_READ(addr) (((const struct T_UINT32_READ *)(const void *)(addr))->v) + #endif + #ifndef __ALIGNED + #define __ALIGNED(x) __attribute__((aligned(x))) + #endif + #ifndef __RESTRICT + #define __RESTRICT __restrict + #endif + #ifndef __COMPILER_BARRIER + #warning No compiler specific solution for __COMPILER_BARRIER. __COMPILER_BARRIER is ignored. + #define __COMPILER_BARRIER() (void)0 + #endif + + +/* + * TASKING Compiler + */ +#elif defined ( __TASKING__ ) + /* + * The CMSIS functions have been implemented as intrinsics in the compiler. + * Please use "carm -?i" to get an up to date list of all intrinsics, + * Including the CMSIS ones. + */ + + #ifndef __ASM + #define __ASM __asm + #endif + #ifndef __INLINE + #define __INLINE inline + #endif + #ifndef __STATIC_INLINE + #define __STATIC_INLINE static inline + #endif + #ifndef __STATIC_FORCEINLINE + #define __STATIC_FORCEINLINE __STATIC_INLINE + #endif + #ifndef __NO_RETURN + #define __NO_RETURN __attribute__((noreturn)) + #endif + #ifndef __USED + #define __USED __attribute__((used)) + #endif + #ifndef __WEAK + #define __WEAK __attribute__((weak)) + #endif + #ifndef __PACKED + #define __PACKED __packed__ + #endif + #ifndef __PACKED_STRUCT + #define __PACKED_STRUCT struct __packed__ + #endif + #ifndef __PACKED_UNION + #define __PACKED_UNION union __packed__ + #endif + #ifndef __UNALIGNED_UINT32 /* deprecated */ + struct __packed__ T_UINT32 { uint32_t v; }; + #define __UNALIGNED_UINT32(x) (((struct T_UINT32 *)(x))->v) + #endif + #ifndef __UNALIGNED_UINT16_WRITE + __PACKED_STRUCT T_UINT16_WRITE { uint16_t v; }; + #define __UNALIGNED_UINT16_WRITE(addr, val) (void)((((struct T_UINT16_WRITE *)(void *)(addr))->v) = (val)) + #endif + #ifndef __UNALIGNED_UINT16_READ + __PACKED_STRUCT T_UINT16_READ { uint16_t v; }; + #define __UNALIGNED_UINT16_READ(addr) (((const struct T_UINT16_READ *)(const void *)(addr))->v) + #endif + #ifndef __UNALIGNED_UINT32_WRITE + __PACKED_STRUCT T_UINT32_WRITE { uint32_t v; }; + #define __UNALIGNED_UINT32_WRITE(addr, val) (void)((((struct T_UINT32_WRITE *)(void *)(addr))->v) = (val)) + #endif + #ifndef __UNALIGNED_UINT32_READ + __PACKED_STRUCT T_UINT32_READ { uint32_t v; }; + #define __UNALIGNED_UINT32_READ(addr) (((const struct T_UINT32_READ *)(const void *)(addr))->v) + #endif + #ifndef __ALIGNED + #define __ALIGNED(x) __align(x) + #endif + #ifndef __RESTRICT + #warning No compiler specific solution for __RESTRICT. __RESTRICT is ignored. + #define __RESTRICT + #endif + #ifndef __COMPILER_BARRIER + #warning No compiler specific solution for __COMPILER_BARRIER. __COMPILER_BARRIER is ignored. + #define __COMPILER_BARRIER() (void)0 + #endif + + +/* + * COSMIC Compiler + */ +#elif defined ( __CSMC__ ) + #include + + #ifndef __ASM + #define __ASM _asm + #endif + #ifndef __INLINE + #define __INLINE inline + #endif + #ifndef __STATIC_INLINE + #define __STATIC_INLINE static inline + #endif + #ifndef __STATIC_FORCEINLINE + #define __STATIC_FORCEINLINE __STATIC_INLINE + #endif + #ifndef __NO_RETURN + // NO RETURN is automatically detected hence no warning here + #define __NO_RETURN + #endif + #ifndef __USED + #warning No compiler specific solution for __USED. __USED is ignored. + #define __USED + #endif + #ifndef __WEAK + #define __WEAK __weak + #endif + #ifndef __PACKED + #define __PACKED @packed + #endif + #ifndef __PACKED_STRUCT + #define __PACKED_STRUCT @packed struct + #endif + #ifndef __PACKED_UNION + #define __PACKED_UNION @packed union + #endif + #ifndef __UNALIGNED_UINT32 /* deprecated */ + @packed struct T_UINT32 { uint32_t v; }; + #define __UNALIGNED_UINT32(x) (((struct T_UINT32 *)(x))->v) + #endif + #ifndef __UNALIGNED_UINT16_WRITE + __PACKED_STRUCT T_UINT16_WRITE { uint16_t v; }; + #define __UNALIGNED_UINT16_WRITE(addr, val) (void)((((struct T_UINT16_WRITE *)(void *)(addr))->v) = (val)) + #endif + #ifndef __UNALIGNED_UINT16_READ + __PACKED_STRUCT T_UINT16_READ { uint16_t v; }; + #define __UNALIGNED_UINT16_READ(addr) (((const struct T_UINT16_READ *)(const void *)(addr))->v) + #endif + #ifndef __UNALIGNED_UINT32_WRITE + __PACKED_STRUCT T_UINT32_WRITE { uint32_t v; }; + #define __UNALIGNED_UINT32_WRITE(addr, val) (void)((((struct T_UINT32_WRITE *)(void *)(addr))->v) = (val)) + #endif + #ifndef __UNALIGNED_UINT32_READ + __PACKED_STRUCT T_UINT32_READ { uint32_t v; }; + #define __UNALIGNED_UINT32_READ(addr) (((const struct T_UINT32_READ *)(const void *)(addr))->v) + #endif + #ifndef __ALIGNED + #warning No compiler specific solution for __ALIGNED. __ALIGNED is ignored. + #define __ALIGNED(x) + #endif + #ifndef __RESTRICT + #warning No compiler specific solution for __RESTRICT. __RESTRICT is ignored. + #define __RESTRICT + #endif + #ifndef __COMPILER_BARRIER + #warning No compiler specific solution for __COMPILER_BARRIER. __COMPILER_BARRIER is ignored. + #define __COMPILER_BARRIER() (void)0 + #endif + + +#else + #error Unknown compiler. +#endif + + +#endif /* __CMSIS_COMPILER_H */ + diff --git a/bsp/acm32f4xx-nucleo/libraries/CMSIS/cmsis_gcc.h b/bsp/acm32f4xx-nucleo/libraries/CMSIS/cmsis_gcc.h new file mode 100644 index 0000000000..a2778f58e8 --- /dev/null +++ b/bsp/acm32f4xx-nucleo/libraries/CMSIS/cmsis_gcc.h @@ -0,0 +1,2177 @@ +/**************************************************************************//** + * @file cmsis_gcc.h + * @brief CMSIS compiler GCC header file + * @version V5.3.0 + * @date 26. March 2020 + ******************************************************************************/ +/* + * Copyright (c) 2009-2020 Arm Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#ifndef __CMSIS_GCC_H +#define __CMSIS_GCC_H + +/* ignore some GCC warnings */ +#pragma GCC diagnostic push +#pragma GCC diagnostic ignored "-Wsign-conversion" +#pragma GCC diagnostic ignored "-Wconversion" +#pragma GCC diagnostic ignored "-Wunused-parameter" + +/* Fallback for __has_builtin */ +#ifndef __has_builtin + #define __has_builtin(x) (0) +#endif + +/* CMSIS compiler specific defines */ +#ifndef __ASM + #define __ASM __asm +#endif +#ifndef __INLINE + #define __INLINE inline +#endif +#ifndef __STATIC_INLINE + #define __STATIC_INLINE static inline +#endif +#ifndef __STATIC_FORCEINLINE + #define __STATIC_FORCEINLINE __attribute__((always_inline)) static inline +#endif +#ifndef __NO_RETURN + #define __NO_RETURN __attribute__((__noreturn__)) +#endif +#ifndef __USED + #define __USED __attribute__((used)) +#endif +#ifndef __WEAK + #define __WEAK __attribute__((weak)) +#endif +#ifndef __PACKED + #define __PACKED __attribute__((packed, aligned(1))) +#endif +#ifndef __PACKED_STRUCT + #define __PACKED_STRUCT struct __attribute__((packed, aligned(1))) +#endif +#ifndef __PACKED_UNION + #define __PACKED_UNION union __attribute__((packed, aligned(1))) +#endif +#ifndef __UNALIGNED_UINT32 /* deprecated */ + #pragma GCC diagnostic push + #pragma GCC diagnostic ignored "-Wpacked" + #pragma GCC diagnostic ignored "-Wattributes" + struct __attribute__((packed)) T_UINT32 { uint32_t v; }; + #pragma GCC diagnostic pop + #define __UNALIGNED_UINT32(x) (((struct T_UINT32 *)(x))->v) +#endif +#ifndef __UNALIGNED_UINT16_WRITE + #pragma GCC diagnostic push + #pragma GCC diagnostic ignored "-Wpacked" + #pragma GCC diagnostic ignored "-Wattributes" + __PACKED_STRUCT T_UINT16_WRITE { uint16_t v; }; + #pragma GCC diagnostic pop + #define __UNALIGNED_UINT16_WRITE(addr, val) (void)((((struct T_UINT16_WRITE *)(void *)(addr))->v) = (val)) +#endif +#ifndef __UNALIGNED_UINT16_READ + #pragma GCC diagnostic push + #pragma GCC diagnostic ignored "-Wpacked" + #pragma GCC diagnostic ignored "-Wattributes" + __PACKED_STRUCT T_UINT16_READ { uint16_t v; }; + #pragma GCC diagnostic pop + #define __UNALIGNED_UINT16_READ(addr) (((const struct T_UINT16_READ *)(const void *)(addr))->v) +#endif +#ifndef __UNALIGNED_UINT32_WRITE + #pragma GCC diagnostic push + #pragma GCC diagnostic ignored "-Wpacked" + #pragma GCC diagnostic ignored "-Wattributes" + __PACKED_STRUCT T_UINT32_WRITE { uint32_t v; }; + #pragma GCC diagnostic pop + #define __UNALIGNED_UINT32_WRITE(addr, val) (void)((((struct T_UINT32_WRITE *)(void *)(addr))->v) = (val)) +#endif +#ifndef __UNALIGNED_UINT32_READ + #pragma GCC diagnostic push + #pragma GCC diagnostic ignored "-Wpacked" + #pragma GCC diagnostic ignored "-Wattributes" + __PACKED_STRUCT T_UINT32_READ { uint32_t v; }; + #pragma GCC diagnostic pop + #define __UNALIGNED_UINT32_READ(addr) (((const struct T_UINT32_READ *)(const void *)(addr))->v) +#endif +#ifndef __ALIGNED + #define __ALIGNED(x) __attribute__((aligned(x))) +#endif +#ifndef __RESTRICT + #define __RESTRICT __restrict +#endif +#ifndef __COMPILER_BARRIER + #define __COMPILER_BARRIER() __ASM volatile("":::"memory") +#endif + +/* ######################### Startup and Lowlevel Init ######################## */ + +#ifndef __PROGRAM_START + +/** + \brief Initializes data and bss sections + \details This default implementations initialized all data and additional bss + sections relying on .copy.table and .zero.table specified properly + in the used linker script. + + */ +__STATIC_FORCEINLINE __NO_RETURN void __cmsis_start(void) +{ + extern void _start(void) __NO_RETURN; + + typedef struct { + uint32_t const* src; + uint32_t* dest; + uint32_t wlen; + } __copy_table_t; + + typedef struct { + uint32_t* dest; + uint32_t wlen; + } __zero_table_t; + + extern const __copy_table_t __copy_table_start__; + extern const __copy_table_t __copy_table_end__; + extern const __zero_table_t __zero_table_start__; + extern const __zero_table_t __zero_table_end__; + + for (__copy_table_t const* pTable = &__copy_table_start__; pTable < &__copy_table_end__; ++pTable) { + for(uint32_t i=0u; iwlen; ++i) { + pTable->dest[i] = pTable->src[i]; + } + } + + for (__zero_table_t const* pTable = &__zero_table_start__; pTable < &__zero_table_end__; ++pTable) { + for(uint32_t i=0u; iwlen; ++i) { + pTable->dest[i] = 0u; + } + } + + _start(); +} + +#define __PROGRAM_START __cmsis_start +#endif + +#ifndef __INITIAL_SP +#define __INITIAL_SP __StackTop +#endif + +#ifndef __STACK_LIMIT +#define __STACK_LIMIT __StackLimit +#endif + +#ifndef __VECTOR_TABLE +#define __VECTOR_TABLE __Vectors +#endif + +#ifndef __VECTOR_TABLE_ATTRIBUTE +#define __VECTOR_TABLE_ATTRIBUTE __attribute__((used, section(".vectors"))) +#endif + +/* ########################### Core Function Access ########################### */ +/** \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_RegAccFunctions CMSIS Core Register Access Functions + @{ + */ + +/** + \brief Enable IRQ Interrupts + \details Enables IRQ interrupts by clearing the I-bit in the CPSR. + Can only be executed in Privileged modes. + */ +__STATIC_FORCEINLINE void __enable_irq(void) +{ + __ASM volatile ("cpsie i" : : : "memory"); +} + + +/** + \brief Disable IRQ Interrupts + \details Disables IRQ interrupts by setting the I-bit in the CPSR. + Can only be executed in Privileged modes. + */ +__STATIC_FORCEINLINE void __disable_irq(void) +{ + __ASM volatile ("cpsid i" : : : "memory"); +} + + +/** + \brief Get Control Register + \details Returns the content of the Control Register. + \return Control Register value + */ +__STATIC_FORCEINLINE uint32_t __get_CONTROL(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, control" : "=r" (result) ); + return(result); +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Get Control Register (non-secure) + \details Returns the content of the non-secure Control Register when in secure mode. + \return non-secure Control Register value + */ +__STATIC_FORCEINLINE uint32_t __TZ_get_CONTROL_NS(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, control_ns" : "=r" (result) ); + return(result); +} +#endif + + +/** + \brief Set Control Register + \details Writes the given value to the Control Register. + \param [in] control Control Register value to set + */ +__STATIC_FORCEINLINE void __set_CONTROL(uint32_t control) +{ + __ASM volatile ("MSR control, %0" : : "r" (control) : "memory"); +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Set Control Register (non-secure) + \details Writes the given value to the non-secure Control Register when in secure state. + \param [in] control Control Register value to set + */ +__STATIC_FORCEINLINE void __TZ_set_CONTROL_NS(uint32_t control) +{ + __ASM volatile ("MSR control_ns, %0" : : "r" (control) : "memory"); +} +#endif + + +/** + \brief Get IPSR Register + \details Returns the content of the IPSR Register. + \return IPSR Register value + */ +__STATIC_FORCEINLINE uint32_t __get_IPSR(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, ipsr" : "=r" (result) ); + return(result); +} + + +/** + \brief Get APSR Register + \details Returns the content of the APSR Register. + \return APSR Register value + */ +__STATIC_FORCEINLINE uint32_t __get_APSR(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, apsr" : "=r" (result) ); + return(result); +} + + +/** + \brief Get xPSR Register + \details Returns the content of the xPSR Register. + \return xPSR Register value + */ +__STATIC_FORCEINLINE uint32_t __get_xPSR(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, xpsr" : "=r" (result) ); + return(result); +} + + +/** + \brief Get Process Stack Pointer + \details Returns the current value of the Process Stack Pointer (PSP). + \return PSP Register value + */ +__STATIC_FORCEINLINE uint32_t __get_PSP(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, psp" : "=r" (result) ); + return(result); +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Get Process Stack Pointer (non-secure) + \details Returns the current value of the non-secure Process Stack Pointer (PSP) when in secure state. + \return PSP Register value + */ +__STATIC_FORCEINLINE uint32_t __TZ_get_PSP_NS(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, psp_ns" : "=r" (result) ); + return(result); +} +#endif + + +/** + \brief Set Process Stack Pointer + \details Assigns the given value to the Process Stack Pointer (PSP). + \param [in] topOfProcStack Process Stack Pointer value to set + */ +__STATIC_FORCEINLINE void __set_PSP(uint32_t topOfProcStack) +{ + __ASM volatile ("MSR psp, %0" : : "r" (topOfProcStack) : ); +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Set Process Stack Pointer (non-secure) + \details Assigns the given value to the non-secure Process Stack Pointer (PSP) when in secure state. + \param [in] topOfProcStack Process Stack Pointer value to set + */ +__STATIC_FORCEINLINE void __TZ_set_PSP_NS(uint32_t topOfProcStack) +{ + __ASM volatile ("MSR psp_ns, %0" : : "r" (topOfProcStack) : ); +} +#endif + + +/** + \brief Get Main Stack Pointer + \details Returns the current value of the Main Stack Pointer (MSP). + \return MSP Register value + */ +__STATIC_FORCEINLINE uint32_t __get_MSP(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, msp" : "=r" (result) ); + return(result); +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Get Main Stack Pointer (non-secure) + \details Returns the current value of the non-secure Main Stack Pointer (MSP) when in secure state. + \return MSP Register value + */ +__STATIC_FORCEINLINE uint32_t __TZ_get_MSP_NS(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, msp_ns" : "=r" (result) ); + return(result); +} +#endif + + +/** + \brief Set Main Stack Pointer + \details Assigns the given value to the Main Stack Pointer (MSP). + \param [in] topOfMainStack Main Stack Pointer value to set + */ +__STATIC_FORCEINLINE void __set_MSP(uint32_t topOfMainStack) +{ + __ASM volatile ("MSR msp, %0" : : "r" (topOfMainStack) : ); +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Set Main Stack Pointer (non-secure) + \details Assigns the given value to the non-secure Main Stack Pointer (MSP) when in secure state. + \param [in] topOfMainStack Main Stack Pointer value to set + */ +__STATIC_FORCEINLINE void __TZ_set_MSP_NS(uint32_t topOfMainStack) +{ + __ASM volatile ("MSR msp_ns, %0" : : "r" (topOfMainStack) : ); +} +#endif + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Get Stack Pointer (non-secure) + \details Returns the current value of the non-secure Stack Pointer (SP) when in secure state. + \return SP Register value + */ +__STATIC_FORCEINLINE uint32_t __TZ_get_SP_NS(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, sp_ns" : "=r" (result) ); + return(result); +} + + +/** + \brief Set Stack Pointer (non-secure) + \details Assigns the given value to the non-secure Stack Pointer (SP) when in secure state. + \param [in] topOfStack Stack Pointer value to set + */ +__STATIC_FORCEINLINE void __TZ_set_SP_NS(uint32_t topOfStack) +{ + __ASM volatile ("MSR sp_ns, %0" : : "r" (topOfStack) : ); +} +#endif + + +/** + \brief Get Priority Mask + \details Returns the current state of the priority mask bit from the Priority Mask Register. + \return Priority Mask value + */ +__STATIC_FORCEINLINE uint32_t __get_PRIMASK(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, primask" : "=r" (result) ); + return(result); +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Get Priority Mask (non-secure) + \details Returns the current state of the non-secure priority mask bit from the Priority Mask Register when in secure state. + \return Priority Mask value + */ +__STATIC_FORCEINLINE uint32_t __TZ_get_PRIMASK_NS(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, primask_ns" : "=r" (result) ); + return(result); +} +#endif + + +/** + \brief Set Priority Mask + \details Assigns the given value to the Priority Mask Register. + \param [in] priMask Priority Mask + */ +__STATIC_FORCEINLINE void __set_PRIMASK(uint32_t priMask) +{ + __ASM volatile ("MSR primask, %0" : : "r" (priMask) : "memory"); +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Set Priority Mask (non-secure) + \details Assigns the given value to the non-secure Priority Mask Register when in secure state. + \param [in] priMask Priority Mask + */ +__STATIC_FORCEINLINE void __TZ_set_PRIMASK_NS(uint32_t priMask) +{ + __ASM volatile ("MSR primask_ns, %0" : : "r" (priMask) : "memory"); +} +#endif + + +#if ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \ + (defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) || \ + (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) ) +/** + \brief Enable FIQ + \details Enables FIQ interrupts by clearing the F-bit in the CPSR. + Can only be executed in Privileged modes. + */ +__STATIC_FORCEINLINE void __enable_fault_irq(void) +{ + __ASM volatile ("cpsie f" : : : "memory"); +} + + +/** + \brief Disable FIQ + \details Disables FIQ interrupts by setting the F-bit in the CPSR. + Can only be executed in Privileged modes. + */ +__STATIC_FORCEINLINE void __disable_fault_irq(void) +{ + __ASM volatile ("cpsid f" : : : "memory"); +} + + +/** + \brief Get Base Priority + \details Returns the current value of the Base Priority register. + \return Base Priority register value + */ +__STATIC_FORCEINLINE uint32_t __get_BASEPRI(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, basepri" : "=r" (result) ); + return(result); +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Get Base Priority (non-secure) + \details Returns the current value of the non-secure Base Priority register when in secure state. + \return Base Priority register value + */ +__STATIC_FORCEINLINE uint32_t __TZ_get_BASEPRI_NS(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, basepri_ns" : "=r" (result) ); + return(result); +} +#endif + + +/** + \brief Set Base Priority + \details Assigns the given value to the Base Priority register. + \param [in] basePri Base Priority value to set + */ +__STATIC_FORCEINLINE void __set_BASEPRI(uint32_t basePri) +{ + __ASM volatile ("MSR basepri, %0" : : "r" (basePri) : "memory"); +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Set Base Priority (non-secure) + \details Assigns the given value to the non-secure Base Priority register when in secure state. + \param [in] basePri Base Priority value to set + */ +__STATIC_FORCEINLINE void __TZ_set_BASEPRI_NS(uint32_t basePri) +{ + __ASM volatile ("MSR basepri_ns, %0" : : "r" (basePri) : "memory"); +} +#endif + + +/** + \brief Set Base Priority with condition + \details Assigns the given value to the Base Priority register only if BASEPRI masking is disabled, + or the new value increases the BASEPRI priority level. + \param [in] basePri Base Priority value to set + */ +__STATIC_FORCEINLINE void __set_BASEPRI_MAX(uint32_t basePri) +{ + __ASM volatile ("MSR basepri_max, %0" : : "r" (basePri) : "memory"); +} + + +/** + \brief Get Fault Mask + \details Returns the current value of the Fault Mask register. + \return Fault Mask register value + */ +__STATIC_FORCEINLINE uint32_t __get_FAULTMASK(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, faultmask" : "=r" (result) ); + return(result); +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Get Fault Mask (non-secure) + \details Returns the current value of the non-secure Fault Mask register when in secure state. + \return Fault Mask register value + */ +__STATIC_FORCEINLINE uint32_t __TZ_get_FAULTMASK_NS(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, faultmask_ns" : "=r" (result) ); + return(result); +} +#endif + + +/** + \brief Set Fault Mask + \details Assigns the given value to the Fault Mask register. + \param [in] faultMask Fault Mask value to set + */ +__STATIC_FORCEINLINE void __set_FAULTMASK(uint32_t faultMask) +{ + __ASM volatile ("MSR faultmask, %0" : : "r" (faultMask) : "memory"); +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Set Fault Mask (non-secure) + \details Assigns the given value to the non-secure Fault Mask register when in secure state. + \param [in] faultMask Fault Mask value to set + */ +__STATIC_FORCEINLINE void __TZ_set_FAULTMASK_NS(uint32_t faultMask) +{ + __ASM volatile ("MSR faultmask_ns, %0" : : "r" (faultMask) : "memory"); +} +#endif + +#endif /* ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \ + (defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) || \ + (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) ) */ + + +#if ((defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \ + (defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1)) ) + +/** + \brief Get Process Stack Pointer Limit + Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure + Stack Pointer Limit register hence zero is returned always in non-secure + mode. + + \details Returns the current value of the Process Stack Pointer Limit (PSPLIM). + \return PSPLIM Register value + */ +__STATIC_FORCEINLINE uint32_t __get_PSPLIM(void) +{ +#if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \ + (!defined (__ARM_FEATURE_CMSE) || (__ARM_FEATURE_CMSE < 3))) + // without main extensions, the non-secure PSPLIM is RAZ/WI + return 0U; +#else + uint32_t result; + __ASM volatile ("MRS %0, psplim" : "=r" (result) ); + return result; +#endif +} + +#if (defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Get Process Stack Pointer Limit (non-secure) + Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure + Stack Pointer Limit register hence zero is returned always. + + \details Returns the current value of the non-secure Process Stack Pointer Limit (PSPLIM) when in secure state. + \return PSPLIM Register value + */ +__STATIC_FORCEINLINE uint32_t __TZ_get_PSPLIM_NS(void) +{ +#if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1))) + // without main extensions, the non-secure PSPLIM is RAZ/WI + return 0U; +#else + uint32_t result; + __ASM volatile ("MRS %0, psplim_ns" : "=r" (result) ); + return result; +#endif +} +#endif + + +/** + \brief Set Process Stack Pointer Limit + Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure + Stack Pointer Limit register hence the write is silently ignored in non-secure + mode. + + \details Assigns the given value to the Process Stack Pointer Limit (PSPLIM). + \param [in] ProcStackPtrLimit Process Stack Pointer Limit value to set + */ +__STATIC_FORCEINLINE void __set_PSPLIM(uint32_t ProcStackPtrLimit) +{ +#if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \ + (!defined (__ARM_FEATURE_CMSE) || (__ARM_FEATURE_CMSE < 3))) + // without main extensions, the non-secure PSPLIM is RAZ/WI + (void)ProcStackPtrLimit; +#else + __ASM volatile ("MSR psplim, %0" : : "r" (ProcStackPtrLimit)); +#endif +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Set Process Stack Pointer (non-secure) + Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure + Stack Pointer Limit register hence the write is silently ignored. + + \details Assigns the given value to the non-secure Process Stack Pointer Limit (PSPLIM) when in secure state. + \param [in] ProcStackPtrLimit Process Stack Pointer Limit value to set + */ +__STATIC_FORCEINLINE void __TZ_set_PSPLIM_NS(uint32_t ProcStackPtrLimit) +{ +#if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1))) + // without main extensions, the non-secure PSPLIM is RAZ/WI + (void)ProcStackPtrLimit; +#else + __ASM volatile ("MSR psplim_ns, %0\n" : : "r" (ProcStackPtrLimit)); +#endif +} +#endif + + +/** + \brief Get Main Stack Pointer Limit + Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure + Stack Pointer Limit register hence zero is returned always in non-secure + mode. + + \details Returns the current value of the Main Stack Pointer Limit (MSPLIM). + \return MSPLIM Register value + */ +__STATIC_FORCEINLINE uint32_t __get_MSPLIM(void) +{ +#if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \ + (!defined (__ARM_FEATURE_CMSE) || (__ARM_FEATURE_CMSE < 3))) + // without main extensions, the non-secure MSPLIM is RAZ/WI + return 0U; +#else + uint32_t result; + __ASM volatile ("MRS %0, msplim" : "=r" (result) ); + return result; +#endif +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Get Main Stack Pointer Limit (non-secure) + Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure + Stack Pointer Limit register hence zero is returned always. + + \details Returns the current value of the non-secure Main Stack Pointer Limit(MSPLIM) when in secure state. + \return MSPLIM Register value + */ +__STATIC_FORCEINLINE uint32_t __TZ_get_MSPLIM_NS(void) +{ +#if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1))) + // without main extensions, the non-secure MSPLIM is RAZ/WI + return 0U; +#else + uint32_t result; + __ASM volatile ("MRS %0, msplim_ns" : "=r" (result) ); + return result; +#endif +} +#endif + + +/** + \brief Set Main Stack Pointer Limit + Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure + Stack Pointer Limit register hence the write is silently ignored in non-secure + mode. + + \details Assigns the given value to the Main Stack Pointer Limit (MSPLIM). + \param [in] MainStackPtrLimit Main Stack Pointer Limit value to set + */ +__STATIC_FORCEINLINE void __set_MSPLIM(uint32_t MainStackPtrLimit) +{ +#if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \ + (!defined (__ARM_FEATURE_CMSE) || (__ARM_FEATURE_CMSE < 3))) + // without main extensions, the non-secure MSPLIM is RAZ/WI + (void)MainStackPtrLimit; +#else + __ASM volatile ("MSR msplim, %0" : : "r" (MainStackPtrLimit)); +#endif +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Set Main Stack Pointer Limit (non-secure) + Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure + Stack Pointer Limit register hence the write is silently ignored. + + \details Assigns the given value to the non-secure Main Stack Pointer Limit (MSPLIM) when in secure state. + \param [in] MainStackPtrLimit Main Stack Pointer value to set + */ +__STATIC_FORCEINLINE void __TZ_set_MSPLIM_NS(uint32_t MainStackPtrLimit) +{ +#if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1))) + // without main extensions, the non-secure MSPLIM is RAZ/WI + (void)MainStackPtrLimit; +#else + __ASM volatile ("MSR msplim_ns, %0" : : "r" (MainStackPtrLimit)); +#endif +} +#endif + +#endif /* ((defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \ + (defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1)) ) */ + + +/** + \brief Get FPSCR + \details Returns the current value of the Floating Point Status/Control register. + \return Floating Point Status/Control register value + */ +__STATIC_FORCEINLINE uint32_t __get_FPSCR(void) +{ +#if ((defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)) && \ + (defined (__FPU_USED ) && (__FPU_USED == 1U)) ) +#if __has_builtin(__builtin_arm_get_fpscr) +// Re-enable using built-in when GCC has been fixed +// || (__GNUC__ > 7) || (__GNUC__ == 7 && __GNUC_MINOR__ >= 2) + /* see https://gcc.gnu.org/ml/gcc-patches/2017-04/msg00443.html */ + return __builtin_arm_get_fpscr(); +#else + uint32_t result; + + __ASM volatile ("VMRS %0, fpscr" : "=r" (result) ); + return(result); +#endif +#else + return(0U); +#endif +} + + +/** + \brief Set FPSCR + \details Assigns the given value to the Floating Point Status/Control register. + \param [in] fpscr Floating Point Status/Control value to set + */ +__STATIC_FORCEINLINE void __set_FPSCR(uint32_t fpscr) +{ +#if ((defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)) && \ + (defined (__FPU_USED ) && (__FPU_USED == 1U)) ) +#if __has_builtin(__builtin_arm_set_fpscr) +// Re-enable using built-in when GCC has been fixed +// || (__GNUC__ > 7) || (__GNUC__ == 7 && __GNUC_MINOR__ >= 2) + /* see https://gcc.gnu.org/ml/gcc-patches/2017-04/msg00443.html */ + __builtin_arm_set_fpscr(fpscr); +#else + __ASM volatile ("VMSR fpscr, %0" : : "r" (fpscr) : "vfpcc", "memory"); +#endif +#else + (void)fpscr; +#endif +} + + +/*@} end of CMSIS_Core_RegAccFunctions */ + + +/* ########################## Core Instruction Access ######################### */ +/** \defgroup CMSIS_Core_InstructionInterface CMSIS Core Instruction Interface + Access to dedicated instructions + @{ +*/ + +/* Define macros for porting to both thumb1 and thumb2. + * For thumb1, use low register (r0-r7), specified by constraint "l" + * Otherwise, use general registers, specified by constraint "r" */ +#if defined (__thumb__) && !defined (__thumb2__) +#define __CMSIS_GCC_OUT_REG(r) "=l" (r) +#define __CMSIS_GCC_RW_REG(r) "+l" (r) +#define __CMSIS_GCC_USE_REG(r) "l" (r) +#else +#define __CMSIS_GCC_OUT_REG(r) "=r" (r) +#define __CMSIS_GCC_RW_REG(r) "+r" (r) +#define __CMSIS_GCC_USE_REG(r) "r" (r) +#endif + +/** + \brief No Operation + \details No Operation does nothing. This instruction can be used for code alignment purposes. + */ +#define __NOP() __ASM volatile ("nop") + +/** + \brief Wait For Interrupt + \details Wait For Interrupt is a hint instruction that suspends execution until one of a number of events occurs. + */ +#define __WFI() __ASM volatile ("wfi":::"memory") + + +/** + \brief Wait For Event + \details Wait For Event is a hint instruction that permits the processor to enter + a low-power state until one of a number of events occurs. + */ +#define __WFE() __ASM volatile ("wfe":::"memory") + + +/** + \brief Send Event + \details Send Event is a hint instruction. It causes an event to be signaled to the CPU. + */ +#define __SEV() __ASM volatile ("sev") + + +/** + \brief Instruction Synchronization Barrier + \details Instruction Synchronization Barrier flushes the pipeline in the processor, + so that all instructions following the ISB are fetched from cache or memory, + after the instruction has been completed. + */ +__STATIC_FORCEINLINE void __ISB(void) +{ + __ASM volatile ("isb 0xF":::"memory"); +} + + +/** + \brief Data Synchronization Barrier + \details Acts as a special kind of Data Memory Barrier. + It completes when all explicit memory accesses before this instruction complete. + */ +__STATIC_FORCEINLINE void __DSB(void) +{ + __ASM volatile ("dsb 0xF":::"memory"); +} + + +/** + \brief Data Memory Barrier + \details Ensures the apparent order of the explicit memory operations before + and after the instruction, without ensuring their completion. + */ +__STATIC_FORCEINLINE void __DMB(void) +{ + __ASM volatile ("dmb 0xF":::"memory"); +} + + +/** + \brief Reverse byte order (32 bit) + \details Reverses the byte order in unsigned integer value. For example, 0x12345678 becomes 0x78563412. + \param [in] value Value to reverse + \return Reversed value + */ +__STATIC_FORCEINLINE uint32_t __REV(uint32_t value) +{ +#if (__GNUC__ > 4) || (__GNUC__ == 4 && __GNUC_MINOR__ >= 5) + return __builtin_bswap32(value); +#else + uint32_t result; + + __ASM ("rev %0, %1" : __CMSIS_GCC_OUT_REG (result) : __CMSIS_GCC_USE_REG (value) ); + return result; +#endif +} + + +/** + \brief Reverse byte order (16 bit) + \details Reverses the byte order within each halfword of a word. For example, 0x12345678 becomes 0x34127856. + \param [in] value Value to reverse + \return Reversed value + */ +__STATIC_FORCEINLINE uint32_t __REV16(uint32_t value) +{ + uint32_t result; + + __ASM ("rev16 %0, %1" : __CMSIS_GCC_OUT_REG (result) : __CMSIS_GCC_USE_REG (value) ); + return result; +} + + +/** + \brief Reverse byte order (16 bit) + \details Reverses the byte order in a 16-bit value and returns the signed 16-bit result. For example, 0x0080 becomes 0x8000. + \param [in] value Value to reverse + \return Reversed value + */ +__STATIC_FORCEINLINE int16_t __REVSH(int16_t value) +{ +#if (__GNUC__ > 4) || (__GNUC__ == 4 && __GNUC_MINOR__ >= 8) + return (int16_t)__builtin_bswap16(value); +#else + int16_t result; + + __ASM ("revsh %0, %1" : __CMSIS_GCC_OUT_REG (result) : __CMSIS_GCC_USE_REG (value) ); + return result; +#endif +} + + +/** + \brief Rotate Right in unsigned value (32 bit) + \details Rotate Right (immediate) provides the value of the contents of a register rotated by a variable number of bits. + \param [in] op1 Value to rotate + \param [in] op2 Number of Bits to rotate + \return Rotated value + */ +__STATIC_FORCEINLINE uint32_t __ROR(uint32_t op1, uint32_t op2) +{ + op2 %= 32U; + if (op2 == 0U) + { + return op1; + } + return (op1 >> op2) | (op1 << (32U - op2)); +} + + +/** + \brief Breakpoint + \details Causes the processor to enter Debug state. + Debug tools can use this to investigate system state when the instruction at a particular address is reached. + \param [in] value is ignored by the processor. + If required, a debugger can use it to store additional information about the breakpoint. + */ +#define __BKPT(value) __ASM volatile ("bkpt "#value) + + +/** + \brief Reverse bit order of value + \details Reverses the bit order of the given value. + \param [in] value Value to reverse + \return Reversed value + */ +__STATIC_FORCEINLINE uint32_t __RBIT(uint32_t value) +{ + uint32_t result; + +#if ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \ + (defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) || \ + (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) ) + __ASM ("rbit %0, %1" : "=r" (result) : "r" (value) ); +#else + uint32_t s = (4U /*sizeof(v)*/ * 8U) - 1U; /* extra shift needed at end */ + + result = value; /* r will be reversed bits of v; first get LSB of v */ + for (value >>= 1U; value != 0U; value >>= 1U) + { + result <<= 1U; + result |= value & 1U; + s--; + } + result <<= s; /* shift when v's highest bits are zero */ +#endif + return result; +} + + +/** + \brief Count leading zeros + \details Counts the number of leading zeros of a data value. + \param [in] value Value to count the leading zeros + \return number of leading zeros in value + */ +__STATIC_FORCEINLINE uint8_t __CLZ(uint32_t value) +{ + /* Even though __builtin_clz produces a CLZ instruction on ARM, formally + __builtin_clz(0) is undefined behaviour, so handle this case specially. + This guarantees ARM-compatible results if happening to compile on a non-ARM + target, and ensures the compiler doesn't decide to activate any + optimisations using the logic "value was passed to __builtin_clz, so it + is non-zero". + ARM GCC 7.3 and possibly earlier will optimise this test away, leaving a + single CLZ instruction. + */ + if (value == 0U) + { + return 32U; + } + return __builtin_clz(value); +} + + +#if ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \ + (defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) || \ + (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \ + (defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1)) ) +/** + \brief LDR Exclusive (8 bit) + \details Executes a exclusive LDR instruction for 8 bit value. + \param [in] ptr Pointer to data + \return value of type uint8_t at (*ptr) + */ +__STATIC_FORCEINLINE uint8_t __LDREXB(volatile uint8_t *addr) +{ + uint32_t result; + +#if (__GNUC__ > 4) || (__GNUC__ == 4 && __GNUC_MINOR__ >= 8) + __ASM volatile ("ldrexb %0, %1" : "=r" (result) : "Q" (*addr) ); +#else + /* Prior to GCC 4.8, "Q" will be expanded to [rx, #0] which is not + accepted by assembler. So has to use following less efficient pattern. + */ + __ASM volatile ("ldrexb %0, [%1]" : "=r" (result) : "r" (addr) : "memory" ); +#endif + return ((uint8_t) result); /* Add explicit type cast here */ +} + + +/** + \brief LDR Exclusive (16 bit) + \details Executes a exclusive LDR instruction for 16 bit values. + \param [in] ptr Pointer to data + \return value of type uint16_t at (*ptr) + */ +__STATIC_FORCEINLINE uint16_t __LDREXH(volatile uint16_t *addr) +{ + uint32_t result; + +#if (__GNUC__ > 4) || (__GNUC__ == 4 && __GNUC_MINOR__ >= 8) + __ASM volatile ("ldrexh %0, %1" : "=r" (result) : "Q" (*addr) ); +#else + /* Prior to GCC 4.8, "Q" will be expanded to [rx, #0] which is not + accepted by assembler. So has to use following less efficient pattern. + */ + __ASM volatile ("ldrexh %0, [%1]" : "=r" (result) : "r" (addr) : "memory" ); +#endif + return ((uint16_t) result); /* Add explicit type cast here */ +} + + +/** + \brief LDR Exclusive (32 bit) + \details Executes a exclusive LDR instruction for 32 bit values. + \param [in] ptr Pointer to data + \return value of type uint32_t at (*ptr) + */ +__STATIC_FORCEINLINE uint32_t __LDREXW(volatile uint32_t *addr) +{ + uint32_t result; + + __ASM volatile ("ldrex %0, %1" : "=r" (result) : "Q" (*addr) ); + return(result); +} + + +/** + \brief STR Exclusive (8 bit) + \details Executes a exclusive STR instruction for 8 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + \return 0 Function succeeded + \return 1 Function failed + */ +__STATIC_FORCEINLINE uint32_t __STREXB(uint8_t value, volatile uint8_t *addr) +{ + uint32_t result; + + __ASM volatile ("strexb %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" ((uint32_t)value) ); + return(result); +} + + +/** + \brief STR Exclusive (16 bit) + \details Executes a exclusive STR instruction for 16 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + \return 0 Function succeeded + \return 1 Function failed + */ +__STATIC_FORCEINLINE uint32_t __STREXH(uint16_t value, volatile uint16_t *addr) +{ + uint32_t result; + + __ASM volatile ("strexh %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" ((uint32_t)value) ); + return(result); +} + + +/** + \brief STR Exclusive (32 bit) + \details Executes a exclusive STR instruction for 32 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + \return 0 Function succeeded + \return 1 Function failed + */ +__STATIC_FORCEINLINE uint32_t __STREXW(uint32_t value, volatile uint32_t *addr) +{ + uint32_t result; + + __ASM volatile ("strex %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" (value) ); + return(result); +} + + +/** + \brief Remove the exclusive lock + \details Removes the exclusive lock which is created by LDREX. + */ +__STATIC_FORCEINLINE void __CLREX(void) +{ + __ASM volatile ("clrex" ::: "memory"); +} + +#endif /* ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \ + (defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) || \ + (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \ + (defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1)) ) */ + + +#if ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \ + (defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) || \ + (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) ) +/** + \brief Signed Saturate + \details Saturates a signed value. + \param [in] ARG1 Value to be saturated + \param [in] ARG2 Bit position to saturate to (1..32) + \return Saturated value + */ +#define __SSAT(ARG1, ARG2) \ +__extension__ \ +({ \ + int32_t __RES, __ARG1 = (ARG1); \ + __ASM volatile ("ssat %0, %1, %2" : "=r" (__RES) : "I" (ARG2), "r" (__ARG1) : "cc" ); \ + __RES; \ + }) + + +/** + \brief Unsigned Saturate + \details Saturates an unsigned value. + \param [in] ARG1 Value to be saturated + \param [in] ARG2 Bit position to saturate to (0..31) + \return Saturated value + */ +#define __USAT(ARG1, ARG2) \ + __extension__ \ +({ \ + uint32_t __RES, __ARG1 = (ARG1); \ + __ASM volatile ("usat %0, %1, %2" : "=r" (__RES) : "I" (ARG2), "r" (__ARG1) : "cc" ); \ + __RES; \ + }) + + +/** + \brief Rotate Right with Extend (32 bit) + \details Moves each bit of a bitstring right by one bit. + The carry input is shifted in at the left end of the bitstring. + \param [in] value Value to rotate + \return Rotated value + */ +__STATIC_FORCEINLINE uint32_t __RRX(uint32_t value) +{ + uint32_t result; + + __ASM volatile ("rrx %0, %1" : __CMSIS_GCC_OUT_REG (result) : __CMSIS_GCC_USE_REG (value) ); + return(result); +} + + +/** + \brief LDRT Unprivileged (8 bit) + \details Executes a Unprivileged LDRT instruction for 8 bit value. + \param [in] ptr Pointer to data + \return value of type uint8_t at (*ptr) + */ +__STATIC_FORCEINLINE uint8_t __LDRBT(volatile uint8_t *ptr) +{ + uint32_t result; + +#if (__GNUC__ > 4) || (__GNUC__ == 4 && __GNUC_MINOR__ >= 8) + __ASM volatile ("ldrbt %0, %1" : "=r" (result) : "Q" (*ptr) ); +#else + /* Prior to GCC 4.8, "Q" will be expanded to [rx, #0] which is not + accepted by assembler. So has to use following less efficient pattern. + */ + __ASM volatile ("ldrbt %0, [%1]" : "=r" (result) : "r" (ptr) : "memory" ); +#endif + return ((uint8_t) result); /* Add explicit type cast here */ +} + + +/** + \brief LDRT Unprivileged (16 bit) + \details Executes a Unprivileged LDRT instruction for 16 bit values. + \param [in] ptr Pointer to data + \return value of type uint16_t at (*ptr) + */ +__STATIC_FORCEINLINE uint16_t __LDRHT(volatile uint16_t *ptr) +{ + uint32_t result; + +#if (__GNUC__ > 4) || (__GNUC__ == 4 && __GNUC_MINOR__ >= 8) + __ASM volatile ("ldrht %0, %1" : "=r" (result) : "Q" (*ptr) ); +#else + /* Prior to GCC 4.8, "Q" will be expanded to [rx, #0] which is not + accepted by assembler. So has to use following less efficient pattern. + */ + __ASM volatile ("ldrht %0, [%1]" : "=r" (result) : "r" (ptr) : "memory" ); +#endif + return ((uint16_t) result); /* Add explicit type cast here */ +} + + +/** + \brief LDRT Unprivileged (32 bit) + \details Executes a Unprivileged LDRT instruction for 32 bit values. + \param [in] ptr Pointer to data + \return value of type uint32_t at (*ptr) + */ +__STATIC_FORCEINLINE uint32_t __LDRT(volatile uint32_t *ptr) +{ + uint32_t result; + + __ASM volatile ("ldrt %0, %1" : "=r" (result) : "Q" (*ptr) ); + return(result); +} + + +/** + \brief STRT Unprivileged (8 bit) + \details Executes a Unprivileged STRT instruction for 8 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + */ +__STATIC_FORCEINLINE void __STRBT(uint8_t value, volatile uint8_t *ptr) +{ + __ASM volatile ("strbt %1, %0" : "=Q" (*ptr) : "r" ((uint32_t)value) ); +} + + +/** + \brief STRT Unprivileged (16 bit) + \details Executes a Unprivileged STRT instruction for 16 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + */ +__STATIC_FORCEINLINE void __STRHT(uint16_t value, volatile uint16_t *ptr) +{ + __ASM volatile ("strht %1, %0" : "=Q" (*ptr) : "r" ((uint32_t)value) ); +} + + +/** + \brief STRT Unprivileged (32 bit) + \details Executes a Unprivileged STRT instruction for 32 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + */ +__STATIC_FORCEINLINE void __STRT(uint32_t value, volatile uint32_t *ptr) +{ + __ASM volatile ("strt %1, %0" : "=Q" (*ptr) : "r" (value) ); +} + +#else /* ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \ + (defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) || \ + (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) ) */ + +/** + \brief Signed Saturate + \details Saturates a signed value. + \param [in] value Value to be saturated + \param [in] sat Bit position to saturate to (1..32) + \return Saturated value + */ +__STATIC_FORCEINLINE int32_t __SSAT(int32_t val, uint32_t sat) +{ + if ((sat >= 1U) && (sat <= 32U)) + { + const int32_t max = (int32_t)((1U << (sat - 1U)) - 1U); + const int32_t min = -1 - max ; + if (val > max) + { + return max; + } + else if (val < min) + { + return min; + } + } + return val; +} + +/** + \brief Unsigned Saturate + \details Saturates an unsigned value. + \param [in] value Value to be saturated + \param [in] sat Bit position to saturate to (0..31) + \return Saturated value + */ +__STATIC_FORCEINLINE uint32_t __USAT(int32_t val, uint32_t sat) +{ + if (sat <= 31U) + { + const uint32_t max = ((1U << sat) - 1U); + if (val > (int32_t)max) + { + return max; + } + else if (val < 0) + { + return 0U; + } + } + return (uint32_t)val; +} + +#endif /* ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \ + (defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) || \ + (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) ) */ + + +#if ((defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \ + (defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1)) ) +/** + \brief Load-Acquire (8 bit) + \details Executes a LDAB instruction for 8 bit value. + \param [in] ptr Pointer to data + \return value of type uint8_t at (*ptr) + */ +__STATIC_FORCEINLINE uint8_t __LDAB(volatile uint8_t *ptr) +{ + uint32_t result; + + __ASM volatile ("ldab %0, %1" : "=r" (result) : "Q" (*ptr) : "memory" ); + return ((uint8_t) result); +} + + +/** + \brief Load-Acquire (16 bit) + \details Executes a LDAH instruction for 16 bit values. + \param [in] ptr Pointer to data + \return value of type uint16_t at (*ptr) + */ +__STATIC_FORCEINLINE uint16_t __LDAH(volatile uint16_t *ptr) +{ + uint32_t result; + + __ASM volatile ("ldah %0, %1" : "=r" (result) : "Q" (*ptr) : "memory" ); + return ((uint16_t) result); +} + + +/** + \brief Load-Acquire (32 bit) + \details Executes a LDA instruction for 32 bit values. + \param [in] ptr Pointer to data + \return value of type uint32_t at (*ptr) + */ +__STATIC_FORCEINLINE uint32_t __LDA(volatile uint32_t *ptr) +{ + uint32_t result; + + __ASM volatile ("lda %0, %1" : "=r" (result) : "Q" (*ptr) : "memory" ); + return(result); +} + + +/** + \brief Store-Release (8 bit) + \details Executes a STLB instruction for 8 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + */ +__STATIC_FORCEINLINE void __STLB(uint8_t value, volatile uint8_t *ptr) +{ + __ASM volatile ("stlb %1, %0" : "=Q" (*ptr) : "r" ((uint32_t)value) : "memory" ); +} + + +/** + \brief Store-Release (16 bit) + \details Executes a STLH instruction for 16 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + */ +__STATIC_FORCEINLINE void __STLH(uint16_t value, volatile uint16_t *ptr) +{ + __ASM volatile ("stlh %1, %0" : "=Q" (*ptr) : "r" ((uint32_t)value) : "memory" ); +} + + +/** + \brief Store-Release (32 bit) + \details Executes a STL instruction for 32 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + */ +__STATIC_FORCEINLINE void __STL(uint32_t value, volatile uint32_t *ptr) +{ + __ASM volatile ("stl %1, %0" : "=Q" (*ptr) : "r" ((uint32_t)value) : "memory" ); +} + + +/** + \brief Load-Acquire Exclusive (8 bit) + \details Executes a LDAB exclusive instruction for 8 bit value. + \param [in] ptr Pointer to data + \return value of type uint8_t at (*ptr) + */ +__STATIC_FORCEINLINE uint8_t __LDAEXB(volatile uint8_t *ptr) +{ + uint32_t result; + + __ASM volatile ("ldaexb %0, %1" : "=r" (result) : "Q" (*ptr) : "memory" ); + return ((uint8_t) result); +} + + +/** + \brief Load-Acquire Exclusive (16 bit) + \details Executes a LDAH exclusive instruction for 16 bit values. + \param [in] ptr Pointer to data + \return value of type uint16_t at (*ptr) + */ +__STATIC_FORCEINLINE uint16_t __LDAEXH(volatile uint16_t *ptr) +{ + uint32_t result; + + __ASM volatile ("ldaexh %0, %1" : "=r" (result) : "Q" (*ptr) : "memory" ); + return ((uint16_t) result); +} + + +/** + \brief Load-Acquire Exclusive (32 bit) + \details Executes a LDA exclusive instruction for 32 bit values. + \param [in] ptr Pointer to data + \return value of type uint32_t at (*ptr) + */ +__STATIC_FORCEINLINE uint32_t __LDAEX(volatile uint32_t *ptr) +{ + uint32_t result; + + __ASM volatile ("ldaex %0, %1" : "=r" (result) : "Q" (*ptr) : "memory" ); + return(result); +} + + +/** + \brief Store-Release Exclusive (8 bit) + \details Executes a STLB exclusive instruction for 8 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + \return 0 Function succeeded + \return 1 Function failed + */ +__STATIC_FORCEINLINE uint32_t __STLEXB(uint8_t value, volatile uint8_t *ptr) +{ + uint32_t result; + + __ASM volatile ("stlexb %0, %2, %1" : "=&r" (result), "=Q" (*ptr) : "r" ((uint32_t)value) : "memory" ); + return(result); +} + + +/** + \brief Store-Release Exclusive (16 bit) + \details Executes a STLH exclusive instruction for 16 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + \return 0 Function succeeded + \return 1 Function failed + */ +__STATIC_FORCEINLINE uint32_t __STLEXH(uint16_t value, volatile uint16_t *ptr) +{ + uint32_t result; + + __ASM volatile ("stlexh %0, %2, %1" : "=&r" (result), "=Q" (*ptr) : "r" ((uint32_t)value) : "memory" ); + return(result); +} + + +/** + \brief Store-Release Exclusive (32 bit) + \details Executes a STL exclusive instruction for 32 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + \return 0 Function succeeded + \return 1 Function failed + */ +__STATIC_FORCEINLINE uint32_t __STLEX(uint32_t value, volatile uint32_t *ptr) +{ + uint32_t result; + + __ASM volatile ("stlex %0, %2, %1" : "=&r" (result), "=Q" (*ptr) : "r" ((uint32_t)value) : "memory" ); + return(result); +} + +#endif /* ((defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \ + (defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1)) ) */ + +/*@}*/ /* end of group CMSIS_Core_InstructionInterface */ + + +/* ################### Compiler specific Intrinsics ########################### */ +/** \defgroup CMSIS_SIMD_intrinsics CMSIS SIMD Intrinsics + Access to dedicated SIMD instructions + @{ +*/ + +#if (defined (__ARM_FEATURE_DSP) && (__ARM_FEATURE_DSP == 1)) + +__STATIC_FORCEINLINE uint32_t __SADD8(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("sadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __QADD8(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM ("qadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __SHADD8(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM ("shadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __UADD8(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("uadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __UQADD8(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM ("uqadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __UHADD8(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM ("uhadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + + +__STATIC_FORCEINLINE uint32_t __SSUB8(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("ssub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __QSUB8(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM ("qsub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __SHSUB8(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM ("shsub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __USUB8(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("usub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __UQSUB8(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM ("uqsub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __UHSUB8(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM ("uhsub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + + +__STATIC_FORCEINLINE uint32_t __SADD16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("sadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __QADD16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM ("qadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __SHADD16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM ("shadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __UADD16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("uadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __UQADD16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM ("uqadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __UHADD16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM ("uhadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __SSUB16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("ssub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __QSUB16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM ("qsub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __SHSUB16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM ("shsub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __USUB16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("usub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __UQSUB16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM ("uqsub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __UHSUB16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM ("uhsub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __SASX(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("sasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __QASX(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM ("qasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __SHASX(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM ("shasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __UASX(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("uasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __UQASX(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM ("uqasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __UHASX(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM ("uhasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __SSAX(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("ssax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __QSAX(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM ("qsax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __SHSAX(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM ("shsax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __USAX(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("usax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __UQSAX(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM ("uqsax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __UHSAX(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM ("uhsax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __USAD8(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM ("usad8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __USADA8(uint32_t op1, uint32_t op2, uint32_t op3) +{ + uint32_t result; + + __ASM ("usada8 %0, %1, %2, %3" : "=r" (result) : "r" (op1), "r" (op2), "r" (op3) ); + return(result); +} + +#define __SSAT16(ARG1, ARG2) \ +({ \ + int32_t __RES, __ARG1 = (ARG1); \ + __ASM volatile ("ssat16 %0, %1, %2" : "=r" (__RES) : "I" (ARG2), "r" (__ARG1) : "cc" ); \ + __RES; \ + }) + +#define __USAT16(ARG1, ARG2) \ +({ \ + uint32_t __RES, __ARG1 = (ARG1); \ + __ASM volatile ("usat16 %0, %1, %2" : "=r" (__RES) : "I" (ARG2), "r" (__ARG1) : "cc" ); \ + __RES; \ + }) + +__STATIC_FORCEINLINE uint32_t __UXTB16(uint32_t op1) +{ + uint32_t result; + + __ASM ("uxtb16 %0, %1" : "=r" (result) : "r" (op1)); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __UXTAB16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM ("uxtab16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __SXTB16(uint32_t op1) +{ + uint32_t result; + + __ASM ("sxtb16 %0, %1" : "=r" (result) : "r" (op1)); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __SXTB16_RORn(uint32_t op1, uint32_t rotate) +{ + uint32_t result; + + __ASM ("sxtb16 %0, %1, ROR %2" : "=r" (result) : "r" (op1), "i" (rotate) ); + + return result; +} + +__STATIC_FORCEINLINE uint32_t __SXTAB16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM ("sxtab16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __SMUAD (uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("smuad %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __SMUADX (uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("smuadx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __SMLAD (uint32_t op1, uint32_t op2, uint32_t op3) +{ + uint32_t result; + + __ASM volatile ("smlad %0, %1, %2, %3" : "=r" (result) : "r" (op1), "r" (op2), "r" (op3) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __SMLADX (uint32_t op1, uint32_t op2, uint32_t op3) +{ + uint32_t result; + + __ASM volatile ("smladx %0, %1, %2, %3" : "=r" (result) : "r" (op1), "r" (op2), "r" (op3) ); + return(result); +} + +__STATIC_FORCEINLINE uint64_t __SMLALD (uint32_t op1, uint32_t op2, uint64_t acc) +{ + union llreg_u{ + uint32_t w32[2]; + uint64_t w64; + } llr; + llr.w64 = acc; + +#ifndef __ARMEB__ /* Little endian */ + __ASM volatile ("smlald %0, %1, %2, %3" : "=r" (llr.w32[0]), "=r" (llr.w32[1]): "r" (op1), "r" (op2) , "0" (llr.w32[0]), "1" (llr.w32[1]) ); +#else /* Big endian */ + __ASM volatile ("smlald %0, %1, %2, %3" : "=r" (llr.w32[1]), "=r" (llr.w32[0]): "r" (op1), "r" (op2) , "0" (llr.w32[1]), "1" (llr.w32[0]) ); +#endif + + return(llr.w64); +} + +__STATIC_FORCEINLINE uint64_t __SMLALDX (uint32_t op1, uint32_t op2, uint64_t acc) +{ + union llreg_u{ + uint32_t w32[2]; + uint64_t w64; + } llr; + llr.w64 = acc; + +#ifndef __ARMEB__ /* Little endian */ + __ASM volatile ("smlaldx %0, %1, %2, %3" : "=r" (llr.w32[0]), "=r" (llr.w32[1]): "r" (op1), "r" (op2) , "0" (llr.w32[0]), "1" (llr.w32[1]) ); +#else /* Big endian */ + __ASM volatile ("smlaldx %0, %1, %2, %3" : "=r" (llr.w32[1]), "=r" (llr.w32[0]): "r" (op1), "r" (op2) , "0" (llr.w32[1]), "1" (llr.w32[0]) ); +#endif + + return(llr.w64); +} + +__STATIC_FORCEINLINE uint32_t __SMUSD (uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("smusd %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __SMUSDX (uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("smusdx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __SMLSD (uint32_t op1, uint32_t op2, uint32_t op3) +{ + uint32_t result; + + __ASM volatile ("smlsd %0, %1, %2, %3" : "=r" (result) : "r" (op1), "r" (op2), "r" (op3) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __SMLSDX (uint32_t op1, uint32_t op2, uint32_t op3) +{ + uint32_t result; + + __ASM volatile ("smlsdx %0, %1, %2, %3" : "=r" (result) : "r" (op1), "r" (op2), "r" (op3) ); + return(result); +} + +__STATIC_FORCEINLINE uint64_t __SMLSLD (uint32_t op1, uint32_t op2, uint64_t acc) +{ + union llreg_u{ + uint32_t w32[2]; + uint64_t w64; + } llr; + llr.w64 = acc; + +#ifndef __ARMEB__ /* Little endian */ + __ASM volatile ("smlsld %0, %1, %2, %3" : "=r" (llr.w32[0]), "=r" (llr.w32[1]): "r" (op1), "r" (op2) , "0" (llr.w32[0]), "1" (llr.w32[1]) ); +#else /* Big endian */ + __ASM volatile ("smlsld %0, %1, %2, %3" : "=r" (llr.w32[1]), "=r" (llr.w32[0]): "r" (op1), "r" (op2) , "0" (llr.w32[1]), "1" (llr.w32[0]) ); +#endif + + return(llr.w64); +} + +__STATIC_FORCEINLINE uint64_t __SMLSLDX (uint32_t op1, uint32_t op2, uint64_t acc) +{ + union llreg_u{ + uint32_t w32[2]; + uint64_t w64; + } llr; + llr.w64 = acc; + +#ifndef __ARMEB__ /* Little endian */ + __ASM volatile ("smlsldx %0, %1, %2, %3" : "=r" (llr.w32[0]), "=r" (llr.w32[1]): "r" (op1), "r" (op2) , "0" (llr.w32[0]), "1" (llr.w32[1]) ); +#else /* Big endian */ + __ASM volatile ("smlsldx %0, %1, %2, %3" : "=r" (llr.w32[1]), "=r" (llr.w32[0]): "r" (op1), "r" (op2) , "0" (llr.w32[1]), "1" (llr.w32[0]) ); +#endif + + return(llr.w64); +} + +__STATIC_FORCEINLINE uint32_t __SEL (uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("sel %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE int32_t __QADD( int32_t op1, int32_t op2) +{ + int32_t result; + + __ASM volatile ("qadd %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE int32_t __QSUB( int32_t op1, int32_t op2) +{ + int32_t result; + + __ASM volatile ("qsub %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +#if 0 +#define __PKHBT(ARG1,ARG2,ARG3) \ +({ \ + uint32_t __RES, __ARG1 = (ARG1), __ARG2 = (ARG2); \ + __ASM ("pkhbt %0, %1, %2, lsl %3" : "=r" (__RES) : "r" (__ARG1), "r" (__ARG2), "I" (ARG3) ); \ + __RES; \ + }) + +#define __PKHTB(ARG1,ARG2,ARG3) \ +({ \ + uint32_t __RES, __ARG1 = (ARG1), __ARG2 = (ARG2); \ + if (ARG3 == 0) \ + __ASM ("pkhtb %0, %1, %2" : "=r" (__RES) : "r" (__ARG1), "r" (__ARG2) ); \ + else \ + __ASM ("pkhtb %0, %1, %2, asr %3" : "=r" (__RES) : "r" (__ARG1), "r" (__ARG2), "I" (ARG3) ); \ + __RES; \ + }) +#endif + +#define __PKHBT(ARG1,ARG2,ARG3) ( ((((uint32_t)(ARG1)) ) & 0x0000FFFFUL) | \ + ((((uint32_t)(ARG2)) << (ARG3)) & 0xFFFF0000UL) ) + +#define __PKHTB(ARG1,ARG2,ARG3) ( ((((uint32_t)(ARG1)) ) & 0xFFFF0000UL) | \ + ((((uint32_t)(ARG2)) >> (ARG3)) & 0x0000FFFFUL) ) + +__STATIC_FORCEINLINE int32_t __SMMLA (int32_t op1, int32_t op2, int32_t op3) +{ + int32_t result; + + __ASM ("smmla %0, %1, %2, %3" : "=r" (result): "r" (op1), "r" (op2), "r" (op3) ); + return(result); +} + +#endif /* (__ARM_FEATURE_DSP == 1) */ +/*@} end of group CMSIS_SIMD_intrinsics */ + + +#pragma GCC diagnostic pop + +#endif /* __CMSIS_GCC_H */ diff --git a/bsp/acm32f4xx-nucleo/libraries/CMSIS/cmsis_iccarm.h b/bsp/acm32f4xx-nucleo/libraries/CMSIS/cmsis_iccarm.h new file mode 100644 index 0000000000..7eeffca5c7 --- /dev/null +++ b/bsp/acm32f4xx-nucleo/libraries/CMSIS/cmsis_iccarm.h @@ -0,0 +1,968 @@ +/**************************************************************************//** + * @file cmsis_iccarm.h + * @brief CMSIS compiler ICCARM (IAR Compiler for Arm) header file + * @version V5.2.0 + * @date 28. January 2020 + ******************************************************************************/ + +//------------------------------------------------------------------------------ +// +// Copyright (c) 2017-2019 IAR Systems +// Copyright (c) 2017-2019 Arm Limited. All rights reserved. +// +// SPDX-License-Identifier: Apache-2.0 +// +// Licensed under the Apache License, Version 2.0 (the "License") +// you may not use this file except in compliance with the License. +// You may obtain a copy of the License at +// http://www.apache.org/licenses/LICENSE-2.0 +// +// Unless required by applicable law or agreed to in writing, software +// distributed under the License is distributed on an "AS IS" BASIS, +// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +// See the License for the specific language governing permissions and +// limitations under the License. +// +//------------------------------------------------------------------------------ + + +#ifndef __CMSIS_ICCARM_H__ +#define __CMSIS_ICCARM_H__ + +#ifndef __ICCARM__ + #error This file should only be compiled by ICCARM +#endif + +#pragma system_include + +#define __IAR_FT _Pragma("inline=forced") __intrinsic + +#if (__VER__ >= 8000000) + #define __ICCARM_V8 1 +#else + #define __ICCARM_V8 0 +#endif + +#ifndef __ALIGNED + #if __ICCARM_V8 + #define __ALIGNED(x) __attribute__((aligned(x))) + #elif (__VER__ >= 7080000) + /* Needs IAR language extensions */ + #define __ALIGNED(x) __attribute__((aligned(x))) + #else + #warning No compiler specific solution for __ALIGNED.__ALIGNED is ignored. + #define __ALIGNED(x) + #endif +#endif + + +/* Define compiler macros for CPU architecture, used in CMSIS 5. + */ +#if __ARM_ARCH_6M__ || __ARM_ARCH_7M__ || __ARM_ARCH_7EM__ || __ARM_ARCH_8M_BASE__ || __ARM_ARCH_8M_MAIN__ +/* Macros already defined */ +#else + #if defined(__ARM8M_MAINLINE__) || defined(__ARM8EM_MAINLINE__) + #define __ARM_ARCH_8M_MAIN__ 1 + #elif defined(__ARM8M_BASELINE__) + #define __ARM_ARCH_8M_BASE__ 1 + #elif defined(__ARM_ARCH_PROFILE) && __ARM_ARCH_PROFILE == 'M' + #if __ARM_ARCH == 6 + #define __ARM_ARCH_6M__ 1 + #elif __ARM_ARCH == 7 + #if __ARM_FEATURE_DSP + #define __ARM_ARCH_7EM__ 1 + #else + #define __ARM_ARCH_7M__ 1 + #endif + #endif /* __ARM_ARCH */ + #endif /* __ARM_ARCH_PROFILE == 'M' */ +#endif + +/* Alternativ core deduction for older ICCARM's */ +#if !defined(__ARM_ARCH_6M__) && !defined(__ARM_ARCH_7M__) && !defined(__ARM_ARCH_7EM__) && \ + !defined(__ARM_ARCH_8M_BASE__) && !defined(__ARM_ARCH_8M_MAIN__) + #if defined(__ARM6M__) && (__CORE__ == __ARM6M__) + #define __ARM_ARCH_6M__ 1 + #elif defined(__ARM7M__) && (__CORE__ == __ARM7M__) + #define __ARM_ARCH_7M__ 1 + #elif defined(__ARM7EM__) && (__CORE__ == __ARM7EM__) + #define __ARM_ARCH_7EM__ 1 + #elif defined(__ARM8M_BASELINE__) && (__CORE == __ARM8M_BASELINE__) + #define __ARM_ARCH_8M_BASE__ 1 + #elif defined(__ARM8M_MAINLINE__) && (__CORE == __ARM8M_MAINLINE__) + #define __ARM_ARCH_8M_MAIN__ 1 + #elif defined(__ARM8EM_MAINLINE__) && (__CORE == __ARM8EM_MAINLINE__) + #define __ARM_ARCH_8M_MAIN__ 1 + #else + #error "Unknown target." + #endif +#endif + + + +#if defined(__ARM_ARCH_6M__) && __ARM_ARCH_6M__==1 + #define __IAR_M0_FAMILY 1 +#elif defined(__ARM_ARCH_8M_BASE__) && __ARM_ARCH_8M_BASE__==1 + #define __IAR_M0_FAMILY 1 +#else + #define __IAR_M0_FAMILY 0 +#endif + + +#ifndef __ASM + #define __ASM __asm +#endif + +#ifndef __COMPILER_BARRIER + #define __COMPILER_BARRIER() __ASM volatile("":::"memory") +#endif + +#ifndef __INLINE + #define __INLINE inline +#endif + +#ifndef __NO_RETURN + #if __ICCARM_V8 + #define __NO_RETURN __attribute__((__noreturn__)) + #else + #define __NO_RETURN _Pragma("object_attribute=__noreturn") + #endif +#endif + +#ifndef __PACKED + #if __ICCARM_V8 + #define __PACKED __attribute__((packed, aligned(1))) + #else + /* Needs IAR language extensions */ + #define __PACKED __packed + #endif +#endif + +#ifndef __PACKED_STRUCT + #if __ICCARM_V8 + #define __PACKED_STRUCT struct __attribute__((packed, aligned(1))) + #else + /* Needs IAR language extensions */ + #define __PACKED_STRUCT __packed struct + #endif +#endif + +#ifndef __PACKED_UNION + #if __ICCARM_V8 + #define __PACKED_UNION union __attribute__((packed, aligned(1))) + #else + /* Needs IAR language extensions */ + #define __PACKED_UNION __packed union + #endif +#endif + +#ifndef __RESTRICT + #if __ICCARM_V8 + #define __RESTRICT __restrict + #else + /* Needs IAR language extensions */ + #define __RESTRICT restrict + #endif +#endif + +#ifndef __STATIC_INLINE + #define __STATIC_INLINE static inline +#endif + +#ifndef __FORCEINLINE + #define __FORCEINLINE _Pragma("inline=forced") +#endif + +#ifndef __STATIC_FORCEINLINE + #define __STATIC_FORCEINLINE __FORCEINLINE __STATIC_INLINE +#endif + +#ifndef __UNALIGNED_UINT16_READ +#pragma language=save +#pragma language=extended +__IAR_FT uint16_t __iar_uint16_read(void const *ptr) +{ + return *(__packed uint16_t*)(ptr); +} +#pragma language=restore +#define __UNALIGNED_UINT16_READ(PTR) __iar_uint16_read(PTR) +#endif + + +#ifndef __UNALIGNED_UINT16_WRITE +#pragma language=save +#pragma language=extended +__IAR_FT void __iar_uint16_write(void const *ptr, uint16_t val) +{ + *(__packed uint16_t*)(ptr) = val;; +} +#pragma language=restore +#define __UNALIGNED_UINT16_WRITE(PTR,VAL) __iar_uint16_write(PTR,VAL) +#endif + +#ifndef __UNALIGNED_UINT32_READ +#pragma language=save +#pragma language=extended +__IAR_FT uint32_t __iar_uint32_read(void const *ptr) +{ + return *(__packed uint32_t*)(ptr); +} +#pragma language=restore +#define __UNALIGNED_UINT32_READ(PTR) __iar_uint32_read(PTR) +#endif + +#ifndef __UNALIGNED_UINT32_WRITE +#pragma language=save +#pragma language=extended +__IAR_FT void __iar_uint32_write(void const *ptr, uint32_t val) +{ + *(__packed uint32_t*)(ptr) = val;; +} +#pragma language=restore +#define __UNALIGNED_UINT32_WRITE(PTR,VAL) __iar_uint32_write(PTR,VAL) +#endif + +#ifndef __UNALIGNED_UINT32 /* deprecated */ +#pragma language=save +#pragma language=extended +__packed struct __iar_u32 { uint32_t v; }; +#pragma language=restore +#define __UNALIGNED_UINT32(PTR) (((struct __iar_u32 *)(PTR))->v) +#endif + +#ifndef __USED + #if __ICCARM_V8 + #define __USED __attribute__((used)) + #else + #define __USED _Pragma("__root") + #endif +#endif + +#ifndef __WEAK + #if __ICCARM_V8 + #define __WEAK __attribute__((weak)) + #else + #define __WEAK _Pragma("__weak") + #endif +#endif + +#ifndef __PROGRAM_START +#define __PROGRAM_START __iar_program_start +#endif + +#ifndef __INITIAL_SP +#define __INITIAL_SP CSTACK$$Limit +#endif + +#ifndef __STACK_LIMIT +#define __STACK_LIMIT CSTACK$$Base +#endif + +#ifndef __VECTOR_TABLE +#define __VECTOR_TABLE __vector_table +#endif + +#ifndef __VECTOR_TABLE_ATTRIBUTE +#define __VECTOR_TABLE_ATTRIBUTE @".intvec" +#endif + +#ifndef __ICCARM_INTRINSICS_VERSION__ + #define __ICCARM_INTRINSICS_VERSION__ 0 +#endif + +#if __ICCARM_INTRINSICS_VERSION__ == 2 + + #if defined(__CLZ) + #undef __CLZ + #endif + #if defined(__REVSH) + #undef __REVSH + #endif + #if defined(__RBIT) + #undef __RBIT + #endif + #if defined(__SSAT) + #undef __SSAT + #endif + #if defined(__USAT) + #undef __USAT + #endif + + #include "iccarm_builtin.h" + + #define __disable_fault_irq __iar_builtin_disable_fiq + #define __disable_irq __iar_builtin_disable_interrupt + #define __enable_fault_irq __iar_builtin_enable_fiq + #define __enable_irq __iar_builtin_enable_interrupt + #define __arm_rsr __iar_builtin_rsr + #define __arm_wsr __iar_builtin_wsr + + + #define __get_APSR() (__arm_rsr("APSR")) + #define __get_BASEPRI() (__arm_rsr("BASEPRI")) + #define __get_CONTROL() (__arm_rsr("CONTROL")) + #define __get_FAULTMASK() (__arm_rsr("FAULTMASK")) + + #if ((defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)) && \ + (defined (__FPU_USED ) && (__FPU_USED == 1U)) ) + #define __get_FPSCR() (__arm_rsr("FPSCR")) + #define __set_FPSCR(VALUE) (__arm_wsr("FPSCR", (VALUE))) + #else + #define __get_FPSCR() ( 0 ) + #define __set_FPSCR(VALUE) ((void)VALUE) + #endif + + #define __get_IPSR() (__arm_rsr("IPSR")) + #define __get_MSP() (__arm_rsr("MSP")) + #if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \ + (!defined (__ARM_FEATURE_CMSE) || (__ARM_FEATURE_CMSE < 3))) + // without main extensions, the non-secure MSPLIM is RAZ/WI + #define __get_MSPLIM() (0U) + #else + #define __get_MSPLIM() (__arm_rsr("MSPLIM")) + #endif + #define __get_PRIMASK() (__arm_rsr("PRIMASK")) + #define __get_PSP() (__arm_rsr("PSP")) + + #if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \ + (!defined (__ARM_FEATURE_CMSE) || (__ARM_FEATURE_CMSE < 3))) + // without main extensions, the non-secure PSPLIM is RAZ/WI + #define __get_PSPLIM() (0U) + #else + #define __get_PSPLIM() (__arm_rsr("PSPLIM")) + #endif + + #define __get_xPSR() (__arm_rsr("xPSR")) + + #define __set_BASEPRI(VALUE) (__arm_wsr("BASEPRI", (VALUE))) + #define __set_BASEPRI_MAX(VALUE) (__arm_wsr("BASEPRI_MAX", (VALUE))) + #define __set_CONTROL(VALUE) (__arm_wsr("CONTROL", (VALUE))) + #define __set_FAULTMASK(VALUE) (__arm_wsr("FAULTMASK", (VALUE))) + #define __set_MSP(VALUE) (__arm_wsr("MSP", (VALUE))) + + #if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \ + (!defined (__ARM_FEATURE_CMSE) || (__ARM_FEATURE_CMSE < 3))) + // without main extensions, the non-secure MSPLIM is RAZ/WI + #define __set_MSPLIM(VALUE) ((void)(VALUE)) + #else + #define __set_MSPLIM(VALUE) (__arm_wsr("MSPLIM", (VALUE))) + #endif + #define __set_PRIMASK(VALUE) (__arm_wsr("PRIMASK", (VALUE))) + #define __set_PSP(VALUE) (__arm_wsr("PSP", (VALUE))) + #if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \ + (!defined (__ARM_FEATURE_CMSE) || (__ARM_FEATURE_CMSE < 3))) + // without main extensions, the non-secure PSPLIM is RAZ/WI + #define __set_PSPLIM(VALUE) ((void)(VALUE)) + #else + #define __set_PSPLIM(VALUE) (__arm_wsr("PSPLIM", (VALUE))) + #endif + + #define __TZ_get_CONTROL_NS() (__arm_rsr("CONTROL_NS")) + #define __TZ_set_CONTROL_NS(VALUE) (__arm_wsr("CONTROL_NS", (VALUE))) + #define __TZ_get_PSP_NS() (__arm_rsr("PSP_NS")) + #define __TZ_set_PSP_NS(VALUE) (__arm_wsr("PSP_NS", (VALUE))) + #define __TZ_get_MSP_NS() (__arm_rsr("MSP_NS")) + #define __TZ_set_MSP_NS(VALUE) (__arm_wsr("MSP_NS", (VALUE))) + #define __TZ_get_SP_NS() (__arm_rsr("SP_NS")) + #define __TZ_set_SP_NS(VALUE) (__arm_wsr("SP_NS", (VALUE))) + #define __TZ_get_PRIMASK_NS() (__arm_rsr("PRIMASK_NS")) + #define __TZ_set_PRIMASK_NS(VALUE) (__arm_wsr("PRIMASK_NS", (VALUE))) + #define __TZ_get_BASEPRI_NS() (__arm_rsr("BASEPRI_NS")) + #define __TZ_set_BASEPRI_NS(VALUE) (__arm_wsr("BASEPRI_NS", (VALUE))) + #define __TZ_get_FAULTMASK_NS() (__arm_rsr("FAULTMASK_NS")) + #define __TZ_set_FAULTMASK_NS(VALUE)(__arm_wsr("FAULTMASK_NS", (VALUE))) + + #if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \ + (!defined (__ARM_FEATURE_CMSE) || (__ARM_FEATURE_CMSE < 3))) + // without main extensions, the non-secure PSPLIM is RAZ/WI + #define __TZ_get_PSPLIM_NS() (0U) + #define __TZ_set_PSPLIM_NS(VALUE) ((void)(VALUE)) + #else + #define __TZ_get_PSPLIM_NS() (__arm_rsr("PSPLIM_NS")) + #define __TZ_set_PSPLIM_NS(VALUE) (__arm_wsr("PSPLIM_NS", (VALUE))) + #endif + + #define __TZ_get_MSPLIM_NS() (__arm_rsr("MSPLIM_NS")) + #define __TZ_set_MSPLIM_NS(VALUE) (__arm_wsr("MSPLIM_NS", (VALUE))) + + #define __NOP __iar_builtin_no_operation + + #define __CLZ __iar_builtin_CLZ + #define __CLREX __iar_builtin_CLREX + + #define __DMB __iar_builtin_DMB + #define __DSB __iar_builtin_DSB + #define __ISB __iar_builtin_ISB + + #define __LDREXB __iar_builtin_LDREXB + #define __LDREXH __iar_builtin_LDREXH + #define __LDREXW __iar_builtin_LDREX + + #define __RBIT __iar_builtin_RBIT + #define __REV __iar_builtin_REV + #define __REV16 __iar_builtin_REV16 + + __IAR_FT int16_t __REVSH(int16_t val) + { + return (int16_t) __iar_builtin_REVSH(val); + } + + #define __ROR __iar_builtin_ROR + #define __RRX __iar_builtin_RRX + + #define __SEV __iar_builtin_SEV + + #if !__IAR_M0_FAMILY + #define __SSAT __iar_builtin_SSAT + #endif + + #define __STREXB __iar_builtin_STREXB + #define __STREXH __iar_builtin_STREXH + #define __STREXW __iar_builtin_STREX + + #if !__IAR_M0_FAMILY + #define __USAT __iar_builtin_USAT + #endif + + #define __WFE __iar_builtin_WFE + #define __WFI __iar_builtin_WFI + + #if __ARM_MEDIA__ + #define __SADD8 __iar_builtin_SADD8 + #define __QADD8 __iar_builtin_QADD8 + #define __SHADD8 __iar_builtin_SHADD8 + #define __UADD8 __iar_builtin_UADD8 + #define __UQADD8 __iar_builtin_UQADD8 + #define __UHADD8 __iar_builtin_UHADD8 + #define __SSUB8 __iar_builtin_SSUB8 + #define __QSUB8 __iar_builtin_QSUB8 + #define __SHSUB8 __iar_builtin_SHSUB8 + #define __USUB8 __iar_builtin_USUB8 + #define __UQSUB8 __iar_builtin_UQSUB8 + #define __UHSUB8 __iar_builtin_UHSUB8 + #define __SADD16 __iar_builtin_SADD16 + #define __QADD16 __iar_builtin_QADD16 + #define __SHADD16 __iar_builtin_SHADD16 + #define __UADD16 __iar_builtin_UADD16 + #define __UQADD16 __iar_builtin_UQADD16 + #define __UHADD16 __iar_builtin_UHADD16 + #define __SSUB16 __iar_builtin_SSUB16 + #define __QSUB16 __iar_builtin_QSUB16 + #define __SHSUB16 __iar_builtin_SHSUB16 + #define __USUB16 __iar_builtin_USUB16 + #define __UQSUB16 __iar_builtin_UQSUB16 + #define __UHSUB16 __iar_builtin_UHSUB16 + #define __SASX __iar_builtin_SASX + #define __QASX __iar_builtin_QASX + #define __SHASX __iar_builtin_SHASX + #define __UASX __iar_builtin_UASX + #define __UQASX __iar_builtin_UQASX + #define __UHASX __iar_builtin_UHASX + #define __SSAX __iar_builtin_SSAX + #define __QSAX __iar_builtin_QSAX + #define __SHSAX __iar_builtin_SHSAX + #define __USAX __iar_builtin_USAX + #define __UQSAX __iar_builtin_UQSAX + #define __UHSAX __iar_builtin_UHSAX + #define __USAD8 __iar_builtin_USAD8 + #define __USADA8 __iar_builtin_USADA8 + #define __SSAT16 __iar_builtin_SSAT16 + #define __USAT16 __iar_builtin_USAT16 + #define __UXTB16 __iar_builtin_UXTB16 + #define __UXTAB16 __iar_builtin_UXTAB16 + #define __SXTB16 __iar_builtin_SXTB16 + #define __SXTAB16 __iar_builtin_SXTAB16 + #define __SMUAD __iar_builtin_SMUAD + #define __SMUADX __iar_builtin_SMUADX + #define __SMMLA __iar_builtin_SMMLA + #define __SMLAD __iar_builtin_SMLAD + #define __SMLADX __iar_builtin_SMLADX + #define __SMLALD __iar_builtin_SMLALD + #define __SMLALDX __iar_builtin_SMLALDX + #define __SMUSD __iar_builtin_SMUSD + #define __SMUSDX __iar_builtin_SMUSDX + #define __SMLSD __iar_builtin_SMLSD + #define __SMLSDX __iar_builtin_SMLSDX + #define __SMLSLD __iar_builtin_SMLSLD + #define __SMLSLDX __iar_builtin_SMLSLDX + #define __SEL __iar_builtin_SEL + #define __QADD __iar_builtin_QADD + #define __QSUB __iar_builtin_QSUB + #define __PKHBT __iar_builtin_PKHBT + #define __PKHTB __iar_builtin_PKHTB + #endif + +#else /* __ICCARM_INTRINSICS_VERSION__ == 2 */ + + #if __IAR_M0_FAMILY + /* Avoid clash between intrinsics.h and arm_math.h when compiling for Cortex-M0. */ + #define __CLZ __cmsis_iar_clz_not_active + #define __SSAT __cmsis_iar_ssat_not_active + #define __USAT __cmsis_iar_usat_not_active + #define __RBIT __cmsis_iar_rbit_not_active + #define __get_APSR __cmsis_iar_get_APSR_not_active + #endif + + + #if (!((defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)) && \ + (defined (__FPU_USED ) && (__FPU_USED == 1U)) )) + #define __get_FPSCR __cmsis_iar_get_FPSR_not_active + #define __set_FPSCR __cmsis_iar_set_FPSR_not_active + #endif + + #ifdef __INTRINSICS_INCLUDED + #error intrinsics.h is already included previously! + #endif + + #include + + #if __IAR_M0_FAMILY + /* Avoid clash between intrinsics.h and arm_math.h when compiling for Cortex-M0. */ + #undef __CLZ + #undef __SSAT + #undef __USAT + #undef __RBIT + #undef __get_APSR + + __STATIC_INLINE uint8_t __CLZ(uint32_t data) + { + if (data == 0U) { return 32U; } + + uint32_t count = 0U; + uint32_t mask = 0x80000000U; + + while ((data & mask) == 0U) + { + count += 1U; + mask = mask >> 1U; + } + return count; + } + + __STATIC_INLINE uint32_t __RBIT(uint32_t v) + { + uint8_t sc = 31U; + uint32_t r = v; + for (v >>= 1U; v; v >>= 1U) + { + r <<= 1U; + r |= v & 1U; + sc--; + } + return (r << sc); + } + + __STATIC_INLINE uint32_t __get_APSR(void) + { + uint32_t res; + __asm("MRS %0,APSR" : "=r" (res)); + return res; + } + + #endif + + #if (!((defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)) && \ + (defined (__FPU_USED ) && (__FPU_USED == 1U)) )) + #undef __get_FPSCR + #undef __set_FPSCR + #define __get_FPSCR() (0) + #define __set_FPSCR(VALUE) ((void)VALUE) + #endif + + #pragma diag_suppress=Pe940 + #pragma diag_suppress=Pe177 + + #define __enable_irq __enable_interrupt + #define __disable_irq __disable_interrupt + #define __NOP __no_operation + + #define __get_xPSR __get_PSR + + #if (!defined(__ARM_ARCH_6M__) || __ARM_ARCH_6M__==0) + + __IAR_FT uint32_t __LDREXW(uint32_t volatile *ptr) + { + return __LDREX((unsigned long *)ptr); + } + + __IAR_FT uint32_t __STREXW(uint32_t value, uint32_t volatile *ptr) + { + return __STREX(value, (unsigned long *)ptr); + } + #endif + + + /* __CORTEX_M is defined in core_cm0.h, core_cm3.h and core_cm4.h. */ + #if (__CORTEX_M >= 0x03) + + __IAR_FT uint32_t __RRX(uint32_t value) + { + uint32_t result; + __ASM volatile("RRX %0, %1" : "=r"(result) : "r" (value)); + return(result); + } + + __IAR_FT void __set_BASEPRI_MAX(uint32_t value) + { + __asm volatile("MSR BASEPRI_MAX,%0"::"r" (value)); + } + + + #define __enable_fault_irq __enable_fiq + #define __disable_fault_irq __disable_fiq + + + #endif /* (__CORTEX_M >= 0x03) */ + + __IAR_FT uint32_t __ROR(uint32_t op1, uint32_t op2) + { + return (op1 >> op2) | (op1 << ((sizeof(op1)*8)-op2)); + } + + #if ((defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \ + (defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1)) ) + + __IAR_FT uint32_t __get_MSPLIM(void) + { + uint32_t res; + #if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \ + (!defined (__ARM_FEATURE_CMSE ) || (__ARM_FEATURE_CMSE < 3))) + // without main extensions, the non-secure MSPLIM is RAZ/WI + res = 0U; + #else + __asm volatile("MRS %0,MSPLIM" : "=r" (res)); + #endif + return res; + } + + __IAR_FT void __set_MSPLIM(uint32_t value) + { + #if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \ + (!defined (__ARM_FEATURE_CMSE ) || (__ARM_FEATURE_CMSE < 3))) + // without main extensions, the non-secure MSPLIM is RAZ/WI + (void)value; + #else + __asm volatile("MSR MSPLIM,%0" :: "r" (value)); + #endif + } + + __IAR_FT uint32_t __get_PSPLIM(void) + { + uint32_t res; + #if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \ + (!defined (__ARM_FEATURE_CMSE ) || (__ARM_FEATURE_CMSE < 3))) + // without main extensions, the non-secure PSPLIM is RAZ/WI + res = 0U; + #else + __asm volatile("MRS %0,PSPLIM" : "=r" (res)); + #endif + return res; + } + + __IAR_FT void __set_PSPLIM(uint32_t value) + { + #if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \ + (!defined (__ARM_FEATURE_CMSE ) || (__ARM_FEATURE_CMSE < 3))) + // without main extensions, the non-secure PSPLIM is RAZ/WI + (void)value; + #else + __asm volatile("MSR PSPLIM,%0" :: "r" (value)); + #endif + } + + __IAR_FT uint32_t __TZ_get_CONTROL_NS(void) + { + uint32_t res; + __asm volatile("MRS %0,CONTROL_NS" : "=r" (res)); + return res; + } + + __IAR_FT void __TZ_set_CONTROL_NS(uint32_t value) + { + __asm volatile("MSR CONTROL_NS,%0" :: "r" (value)); + } + + __IAR_FT uint32_t __TZ_get_PSP_NS(void) + { + uint32_t res; + __asm volatile("MRS %0,PSP_NS" : "=r" (res)); + return res; + } + + __IAR_FT void __TZ_set_PSP_NS(uint32_t value) + { + __asm volatile("MSR PSP_NS,%0" :: "r" (value)); + } + + __IAR_FT uint32_t __TZ_get_MSP_NS(void) + { + uint32_t res; + __asm volatile("MRS %0,MSP_NS" : "=r" (res)); + return res; + } + + __IAR_FT void __TZ_set_MSP_NS(uint32_t value) + { + __asm volatile("MSR MSP_NS,%0" :: "r" (value)); + } + + __IAR_FT uint32_t __TZ_get_SP_NS(void) + { + uint32_t res; + __asm volatile("MRS %0,SP_NS" : "=r" (res)); + return res; + } + __IAR_FT void __TZ_set_SP_NS(uint32_t value) + { + __asm volatile("MSR SP_NS,%0" :: "r" (value)); + } + + __IAR_FT uint32_t __TZ_get_PRIMASK_NS(void) + { + uint32_t res; + __asm volatile("MRS %0,PRIMASK_NS" : "=r" (res)); + return res; + } + + __IAR_FT void __TZ_set_PRIMASK_NS(uint32_t value) + { + __asm volatile("MSR PRIMASK_NS,%0" :: "r" (value)); + } + + __IAR_FT uint32_t __TZ_get_BASEPRI_NS(void) + { + uint32_t res; + __asm volatile("MRS %0,BASEPRI_NS" : "=r" (res)); + return res; + } + + __IAR_FT void __TZ_set_BASEPRI_NS(uint32_t value) + { + __asm volatile("MSR BASEPRI_NS,%0" :: "r" (value)); + } + + __IAR_FT uint32_t __TZ_get_FAULTMASK_NS(void) + { + uint32_t res; + __asm volatile("MRS %0,FAULTMASK_NS" : "=r" (res)); + return res; + } + + __IAR_FT void __TZ_set_FAULTMASK_NS(uint32_t value) + { + __asm volatile("MSR FAULTMASK_NS,%0" :: "r" (value)); + } + + __IAR_FT uint32_t __TZ_get_PSPLIM_NS(void) + { + uint32_t res; + #if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \ + (!defined (__ARM_FEATURE_CMSE ) || (__ARM_FEATURE_CMSE < 3))) + // without main extensions, the non-secure PSPLIM is RAZ/WI + res = 0U; + #else + __asm volatile("MRS %0,PSPLIM_NS" : "=r" (res)); + #endif + return res; + } + + __IAR_FT void __TZ_set_PSPLIM_NS(uint32_t value) + { + #if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \ + (!defined (__ARM_FEATURE_CMSE ) || (__ARM_FEATURE_CMSE < 3))) + // without main extensions, the non-secure PSPLIM is RAZ/WI + (void)value; + #else + __asm volatile("MSR PSPLIM_NS,%0" :: "r" (value)); + #endif + } + + __IAR_FT uint32_t __TZ_get_MSPLIM_NS(void) + { + uint32_t res; + __asm volatile("MRS %0,MSPLIM_NS" : "=r" (res)); + return res; + } + + __IAR_FT void __TZ_set_MSPLIM_NS(uint32_t value) + { + __asm volatile("MSR MSPLIM_NS,%0" :: "r" (value)); + } + + #endif /* __ARM_ARCH_8M_MAIN__ or __ARM_ARCH_8M_BASE__ */ + +#endif /* __ICCARM_INTRINSICS_VERSION__ == 2 */ + +#define __BKPT(value) __asm volatile ("BKPT %0" : : "i"(value)) + +#if __IAR_M0_FAMILY + __STATIC_INLINE int32_t __SSAT(int32_t val, uint32_t sat) + { + if ((sat >= 1U) && (sat <= 32U)) + { + const int32_t max = (int32_t)((1U << (sat - 1U)) - 1U); + const int32_t min = -1 - max ; + if (val > max) + { + return max; + } + else if (val < min) + { + return min; + } + } + return val; + } + + __STATIC_INLINE uint32_t __USAT(int32_t val, uint32_t sat) + { + if (sat <= 31U) + { + const uint32_t max = ((1U << sat) - 1U); + if (val > (int32_t)max) + { + return max; + } + else if (val < 0) + { + return 0U; + } + } + return (uint32_t)val; + } +#endif + +#if (__CORTEX_M >= 0x03) /* __CORTEX_M is defined in core_cm0.h, core_cm3.h and core_cm4.h. */ + + __IAR_FT uint8_t __LDRBT(volatile uint8_t *addr) + { + uint32_t res; + __ASM volatile ("LDRBT %0, [%1]" : "=r" (res) : "r" (addr) : "memory"); + return ((uint8_t)res); + } + + __IAR_FT uint16_t __LDRHT(volatile uint16_t *addr) + { + uint32_t res; + __ASM volatile ("LDRHT %0, [%1]" : "=r" (res) : "r" (addr) : "memory"); + return ((uint16_t)res); + } + + __IAR_FT uint32_t __LDRT(volatile uint32_t *addr) + { + uint32_t res; + __ASM volatile ("LDRT %0, [%1]" : "=r" (res) : "r" (addr) : "memory"); + return res; + } + + __IAR_FT void __STRBT(uint8_t value, volatile uint8_t *addr) + { + __ASM volatile ("STRBT %1, [%0]" : : "r" (addr), "r" ((uint32_t)value) : "memory"); + } + + __IAR_FT void __STRHT(uint16_t value, volatile uint16_t *addr) + { + __ASM volatile ("STRHT %1, [%0]" : : "r" (addr), "r" ((uint32_t)value) : "memory"); + } + + __IAR_FT void __STRT(uint32_t value, volatile uint32_t *addr) + { + __ASM volatile ("STRT %1, [%0]" : : "r" (addr), "r" (value) : "memory"); + } + +#endif /* (__CORTEX_M >= 0x03) */ + +#if ((defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \ + (defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1)) ) + + + __IAR_FT uint8_t __LDAB(volatile uint8_t *ptr) + { + uint32_t res; + __ASM volatile ("LDAB %0, [%1]" : "=r" (res) : "r" (ptr) : "memory"); + return ((uint8_t)res); + } + + __IAR_FT uint16_t __LDAH(volatile uint16_t *ptr) + { + uint32_t res; + __ASM volatile ("LDAH %0, [%1]" : "=r" (res) : "r" (ptr) : "memory"); + return ((uint16_t)res); + } + + __IAR_FT uint32_t __LDA(volatile uint32_t *ptr) + { + uint32_t res; + __ASM volatile ("LDA %0, [%1]" : "=r" (res) : "r" (ptr) : "memory"); + return res; + } + + __IAR_FT void __STLB(uint8_t value, volatile uint8_t *ptr) + { + __ASM volatile ("STLB %1, [%0]" :: "r" (ptr), "r" (value) : "memory"); + } + + __IAR_FT void __STLH(uint16_t value, volatile uint16_t *ptr) + { + __ASM volatile ("STLH %1, [%0]" :: "r" (ptr), "r" (value) : "memory"); + } + + __IAR_FT void __STL(uint32_t value, volatile uint32_t *ptr) + { + __ASM volatile ("STL %1, [%0]" :: "r" (ptr), "r" (value) : "memory"); + } + + __IAR_FT uint8_t __LDAEXB(volatile uint8_t *ptr) + { + uint32_t res; + __ASM volatile ("LDAEXB %0, [%1]" : "=r" (res) : "r" (ptr) : "memory"); + return ((uint8_t)res); + } + + __IAR_FT uint16_t __LDAEXH(volatile uint16_t *ptr) + { + uint32_t res; + __ASM volatile ("LDAEXH %0, [%1]" : "=r" (res) : "r" (ptr) : "memory"); + return ((uint16_t)res); + } + + __IAR_FT uint32_t __LDAEX(volatile uint32_t *ptr) + { + uint32_t res; + __ASM volatile ("LDAEX %0, [%1]" : "=r" (res) : "r" (ptr) : "memory"); + return res; + } + + __IAR_FT uint32_t __STLEXB(uint8_t value, volatile uint8_t *ptr) + { + uint32_t res; + __ASM volatile ("STLEXB %0, %2, [%1]" : "=r" (res) : "r" (ptr), "r" (value) : "memory"); + return res; + } + + __IAR_FT uint32_t __STLEXH(uint16_t value, volatile uint16_t *ptr) + { + uint32_t res; + __ASM volatile ("STLEXH %0, %2, [%1]" : "=r" (res) : "r" (ptr), "r" (value) : "memory"); + return res; + } + + __IAR_FT uint32_t __STLEX(uint32_t value, volatile uint32_t *ptr) + { + uint32_t res; + __ASM volatile ("STLEX %0, %2, [%1]" : "=r" (res) : "r" (ptr), "r" (value) : "memory"); + return res; + } + +#endif /* __ARM_ARCH_8M_MAIN__ or __ARM_ARCH_8M_BASE__ */ + +#undef __IAR_FT +#undef __IAR_M0_FAMILY +#undef __ICCARM_V8 + +#pragma diag_default=Pe940 +#pragma diag_default=Pe177 + +#define __SXTB16_RORn(ARG1, ARG2) __SXTB16(__ROR(ARG1, ARG2)) + +#endif /* __CMSIS_ICCARM_H__ */ diff --git a/bsp/acm32f4xx-nucleo/libraries/CMSIS/cmsis_version.h b/bsp/acm32f4xx-nucleo/libraries/CMSIS/cmsis_version.h new file mode 100644 index 0000000000..f2e2746626 --- /dev/null +++ b/bsp/acm32f4xx-nucleo/libraries/CMSIS/cmsis_version.h @@ -0,0 +1,39 @@ +/**************************************************************************//** + * @file cmsis_version.h + * @brief CMSIS Core(M) Version definitions + * @version V5.0.3 + * @date 24. June 2019 + ******************************************************************************/ +/* + * Copyright (c) 2009-2019 ARM Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#if defined ( __ICCARM__ ) + #pragma system_include /* treat file as system include file for MISRA check */ +#elif defined (__clang__) + #pragma clang system_header /* treat file as system include file */ +#endif + +#ifndef __CMSIS_VERSION_H +#define __CMSIS_VERSION_H + +/* CMSIS Version definitions */ +#define __CM_CMSIS_VERSION_MAIN ( 5U) /*!< [31:16] CMSIS Core(M) main version */ +#define __CM_CMSIS_VERSION_SUB ( 3U) /*!< [15:0] CMSIS Core(M) sub version */ +#define __CM_CMSIS_VERSION ((__CM_CMSIS_VERSION_MAIN << 16U) | \ + __CM_CMSIS_VERSION_SUB ) /*!< CMSIS Core(M) version number */ +#endif diff --git a/bsp/acm32f4xx-nucleo/libraries/CMSIS/core_cm33.h b/bsp/acm32f4xx-nucleo/libraries/CMSIS/core_cm33.h new file mode 100644 index 0000000000..e9a2c35409 --- /dev/null +++ b/bsp/acm32f4xx-nucleo/libraries/CMSIS/core_cm33.h @@ -0,0 +1,2910 @@ +/**************************************************************************//** + * @file core_cm33.h + * @brief CMSIS Cortex-M33 Core Peripheral Access Layer Header File + * @version V5.1.0 + * @date 12. November 2018 + ******************************************************************************/ +/* + * Copyright (c) 2009-2018 Arm Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#if defined ( __ICCARM__ ) + #pragma system_include /* treat file as system include file for MISRA check */ +#elif defined (__clang__) + #pragma clang system_header /* treat file as system include file */ +#endif + +#ifndef __CORE_CM33_H_GENERIC +#define __CORE_CM33_H_GENERIC + +#include + +#ifdef __cplusplus + extern "C" { +#endif + +/** + \page CMSIS_MISRA_Exceptions MISRA-C:2004 Compliance Exceptions + CMSIS violates the following MISRA-C:2004 rules: + + \li Required Rule 8.5, object/function definition in header file.
+ Function definitions in header files are used to allow 'inlining'. + + \li Required Rule 18.4, declaration of union type or object of union type: '{...}'.
+ Unions are used for effective representation of core registers. + + \li Advisory Rule 19.7, Function-like macro defined.
+ Function-like macros are used to allow more efficient code. + */ + + +/******************************************************************************* + * CMSIS definitions + ******************************************************************************/ +/** + \ingroup Cortex_M33 + @{ + */ + +#include "cmsis_version.h" + +/* CMSIS CM33 definitions */ +#define __CM33_CMSIS_VERSION_MAIN (__CM_CMSIS_VERSION_MAIN) /*!< \deprecated [31:16] CMSIS HAL main version */ +#define __CM33_CMSIS_VERSION_SUB (__CM_CMSIS_VERSION_SUB) /*!< \deprecated [15:0] CMSIS HAL sub version */ +#define __CM33_CMSIS_VERSION ((__CM33_CMSIS_VERSION_MAIN << 16U) | \ + __CM33_CMSIS_VERSION_SUB ) /*!< \deprecated CMSIS HAL version number */ + +#define __CORTEX_M (33U) /*!< Cortex-M Core */ + +/** __FPU_USED indicates whether an FPU is used or not. + For this, __FPU_PRESENT has to be checked prior to making use of FPU specific registers and functions. +*/ +#if defined ( __CC_ARM ) + #if defined (__TARGET_FPU_VFP) + #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) + #define __FPU_USED 1U + #else + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #define __FPU_USED 0U + #endif + #else + #define __FPU_USED 0U + #endif + + #if defined (__ARM_FEATURE_DSP) && (__ARM_FEATURE_DSP == 1U) + #if defined (__DSP_PRESENT) && (__DSP_PRESENT == 1U) + #define __DSP_USED 1U + #else + #error "Compiler generates DSP (SIMD) instructions for a devices without DSP extensions (check __DSP_PRESENT)" + #define __DSP_USED 0U + #endif + #else + #define __DSP_USED 0U + #endif + +#elif defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) + #if defined (__ARM_FP) + #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) + #define __FPU_USED 1U + #else + #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #define __FPU_USED 0U + #endif + #else + #define __FPU_USED 0U + #endif + + #if defined (__ARM_FEATURE_DSP) && (__ARM_FEATURE_DSP == 1U) + #if defined (__DSP_PRESENT) && (__DSP_PRESENT == 1U) + #define __DSP_USED 1U + #else + #error "Compiler generates DSP (SIMD) instructions for a devices without DSP extensions (check __DSP_PRESENT)" + #define __DSP_USED 0U + #endif + #else + #define __DSP_USED 0U + #endif + +#elif defined ( __GNUC__ ) + #if defined (__VFP_FP__) && !defined(__SOFTFP__) + #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) + #define __FPU_USED 1U + #else + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #define __FPU_USED 0U + #endif + #else + #define __FPU_USED 0U + #endif + + #if defined (__ARM_FEATURE_DSP) && (__ARM_FEATURE_DSP == 1U) + #if defined (__DSP_PRESENT) && (__DSP_PRESENT == 1U) + #define __DSP_USED 1U + #else + #error "Compiler generates DSP (SIMD) instructions for a devices without DSP extensions (check __DSP_PRESENT)" + #define __DSP_USED 0U + #endif + #else + #define __DSP_USED 0U + #endif + +#elif defined ( __ICCARM__ ) + #if defined (__ARMVFP__) + #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) + #define __FPU_USED 1U + #else + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #define __FPU_USED 0U + #endif + #else + #define __FPU_USED 0U + #endif + + #if defined (__ARM_FEATURE_DSP) && (__ARM_FEATURE_DSP == 1U) + #if defined (__DSP_PRESENT) && (__DSP_PRESENT == 1U) + #define __DSP_USED 1U + #else + #error "Compiler generates DSP (SIMD) instructions for a devices without DSP extensions (check __DSP_PRESENT)" + #define __DSP_USED 0U + #endif + #else + #define __DSP_USED 0U + #endif + +#elif defined ( __TI_ARM__ ) + #if defined (__TI_VFP_SUPPORT__) + #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) + #define __FPU_USED 1U + #else + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #define __FPU_USED 0U + #endif + #else + #define __FPU_USED 0U + #endif + +#elif defined ( __TASKING__ ) + #if defined (__FPU_VFP__) + #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) + #define __FPU_USED 1U + #else + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #define __FPU_USED 0U + #endif + #else + #define __FPU_USED 0U + #endif + +#elif defined ( __CSMC__ ) + #if ( __CSMC__ & 0x400U) + #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) + #define __FPU_USED 1U + #else + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #define __FPU_USED 0U + #endif + #else + #define __FPU_USED 0U + #endif + +#endif + +#include "cmsis_compiler.h" /* CMSIS compiler specific defines */ + + +#ifdef __cplusplus +} +#endif + +#endif /* __CORE_CM33_H_GENERIC */ + +#ifndef __CMSIS_GENERIC + +#ifndef __CORE_CM33_H_DEPENDANT +#define __CORE_CM33_H_DEPENDANT + +#ifdef __cplusplus + extern "C" { +#endif + +/* check device defines and use defaults */ +#if defined __CHECK_DEVICE_DEFINES + #ifndef __CM33_REV + #define __CM33_REV 0x0000U + #warning "__CM33_REV not defined in device header file; using default!" + #endif + + #ifndef __FPU_PRESENT + #define __FPU_PRESENT 0U + #warning "__FPU_PRESENT not defined in device header file; using default!" + #endif + + #ifndef __MPU_PRESENT + #define __MPU_PRESENT 0U + #warning "__MPU_PRESENT not defined in device header file; using default!" + #endif + + #ifndef __SAUREGION_PRESENT + #define __SAUREGION_PRESENT 0U + #warning "__SAUREGION_PRESENT not defined in device header file; using default!" + #endif + + #ifndef __DSP_PRESENT + #define __DSP_PRESENT 0U + #warning "__DSP_PRESENT not defined in device header file; using default!" + #endif + + #ifndef __NVIC_PRIO_BITS + #define __NVIC_PRIO_BITS 3U + #warning "__NVIC_PRIO_BITS not defined in device header file; using default!" + #endif + + #ifndef __Vendor_SysTickConfig + #define __Vendor_SysTickConfig 1U + #warning "__Vendor_SysTickConfig not defined in device header file; using default!" + #endif +#endif + +/* IO definitions (access restrictions to peripheral registers) */ +/** + \defgroup CMSIS_glob_defs CMSIS Global Defines + + IO Type Qualifiers are used + \li to specify the access to peripheral variables. + \li for automatic generation of peripheral register debug information. +*/ +#ifdef __cplusplus + #define __I volatile /*!< Defines 'read only' permissions */ +#else + #define __I volatile const /*!< Defines 'read only' permissions */ +#endif +#define __O volatile /*!< Defines 'write only' permissions */ +#define __IO volatile /*!< Defines 'read / write' permissions */ + +/* following defines should be used for structure members */ +#define __IM volatile const /*! Defines 'read only' structure member permissions */ +#define __OM volatile /*! Defines 'write only' structure member permissions */ +#define __IOM volatile /*! Defines 'read / write' structure member permissions */ + +/*@} end of group Cortex_M33 */ + + + +/******************************************************************************* + * Register Abstraction + Core Register contain: + - Core Register + - Core NVIC Register + - Core SCB Register + - Core SysTick Register + - Core Debug Register + - Core MPU Register + - Core SAU Register + - Core FPU Register + ******************************************************************************/ +/** + \defgroup CMSIS_core_register Defines and Type Definitions + \brief Type definitions and defines for Cortex-M processor based devices. +*/ + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_CORE Status and Control Registers + \brief Core Register type definitions. + @{ + */ + +/** + \brief Union type to access the Application Program Status Register (APSR). + */ +typedef union +{ + struct + { + uint32_t _reserved0:16; /*!< bit: 0..15 Reserved */ + uint32_t GE:4; /*!< bit: 16..19 Greater than or Equal flags */ + uint32_t _reserved1:7; /*!< bit: 20..26 Reserved */ + uint32_t Q:1; /*!< bit: 27 Saturation condition flag */ + uint32_t V:1; /*!< bit: 28 Overflow condition code flag */ + uint32_t C:1; /*!< bit: 29 Carry condition code flag */ + uint32_t Z:1; /*!< bit: 30 Zero condition code flag */ + uint32_t N:1; /*!< bit: 31 Negative condition code flag */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} APSR_Type; + +/* APSR Register Definitions */ +#define APSR_N_Pos 31U /*!< APSR: N Position */ +#define APSR_N_Msk (1UL << APSR_N_Pos) /*!< APSR: N Mask */ + +#define APSR_Z_Pos 30U /*!< APSR: Z Position */ +#define APSR_Z_Msk (1UL << APSR_Z_Pos) /*!< APSR: Z Mask */ + +#define APSR_C_Pos 29U /*!< APSR: C Position */ +#define APSR_C_Msk (1UL << APSR_C_Pos) /*!< APSR: C Mask */ + +#define APSR_V_Pos 28U /*!< APSR: V Position */ +#define APSR_V_Msk (1UL << APSR_V_Pos) /*!< APSR: V Mask */ + +#define APSR_Q_Pos 27U /*!< APSR: Q Position */ +#define APSR_Q_Msk (1UL << APSR_Q_Pos) /*!< APSR: Q Mask */ + +#define APSR_GE_Pos 16U /*!< APSR: GE Position */ +#define APSR_GE_Msk (0xFUL << APSR_GE_Pos) /*!< APSR: GE Mask */ + + +/** + \brief Union type to access the Interrupt Program Status Register (IPSR). + */ +typedef union +{ + struct + { + uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */ + uint32_t _reserved0:23; /*!< bit: 9..31 Reserved */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} IPSR_Type; + +/* IPSR Register Definitions */ +#define IPSR_ISR_Pos 0U /*!< IPSR: ISR Position */ +#define IPSR_ISR_Msk (0x1FFUL /*<< IPSR_ISR_Pos*/) /*!< IPSR: ISR Mask */ + + +/** + \brief Union type to access the Special-Purpose Program Status Registers (xPSR). + */ +typedef union +{ + struct + { + uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */ + uint32_t _reserved0:7; /*!< bit: 9..15 Reserved */ + uint32_t GE:4; /*!< bit: 16..19 Greater than or Equal flags */ + uint32_t _reserved1:4; /*!< bit: 20..23 Reserved */ + uint32_t T:1; /*!< bit: 24 Thumb bit (read 0) */ + uint32_t IT:2; /*!< bit: 25..26 saved IT state (read 0) */ + uint32_t Q:1; /*!< bit: 27 Saturation condition flag */ + uint32_t V:1; /*!< bit: 28 Overflow condition code flag */ + uint32_t C:1; /*!< bit: 29 Carry condition code flag */ + uint32_t Z:1; /*!< bit: 30 Zero condition code flag */ + uint32_t N:1; /*!< bit: 31 Negative condition code flag */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} xPSR_Type; + +/* xPSR Register Definitions */ +#define xPSR_N_Pos 31U /*!< xPSR: N Position */ +#define xPSR_N_Msk (1UL << xPSR_N_Pos) /*!< xPSR: N Mask */ + +#define xPSR_Z_Pos 30U /*!< xPSR: Z Position */ +#define xPSR_Z_Msk (1UL << xPSR_Z_Pos) /*!< xPSR: Z Mask */ + +#define xPSR_C_Pos 29U /*!< xPSR: C Position */ +#define xPSR_C_Msk (1UL << xPSR_C_Pos) /*!< xPSR: C Mask */ + +#define xPSR_V_Pos 28U /*!< xPSR: V Position */ +#define xPSR_V_Msk (1UL << xPSR_V_Pos) /*!< xPSR: V Mask */ + +#define xPSR_Q_Pos 27U /*!< xPSR: Q Position */ +#define xPSR_Q_Msk (1UL << xPSR_Q_Pos) /*!< xPSR: Q Mask */ + +#define xPSR_IT_Pos 25U /*!< xPSR: IT Position */ +#define xPSR_IT_Msk (3UL << xPSR_IT_Pos) /*!< xPSR: IT Mask */ + +#define xPSR_T_Pos 24U /*!< xPSR: T Position */ +#define xPSR_T_Msk (1UL << xPSR_T_Pos) /*!< xPSR: T Mask */ + +#define xPSR_GE_Pos 16U /*!< xPSR: GE Position */ +#define xPSR_GE_Msk (0xFUL << xPSR_GE_Pos) /*!< xPSR: GE Mask */ + +#define xPSR_ISR_Pos 0U /*!< xPSR: ISR Position */ +#define xPSR_ISR_Msk (0x1FFUL /*<< xPSR_ISR_Pos*/) /*!< xPSR: ISR Mask */ + + +/** + \brief Union type to access the Control Registers (CONTROL). + */ +typedef union +{ + struct + { + uint32_t nPRIV:1; /*!< bit: 0 Execution privilege in Thread mode */ + uint32_t SPSEL:1; /*!< bit: 1 Stack-pointer select */ + uint32_t FPCA:1; /*!< bit: 2 Floating-point context active */ + uint32_t SFPA:1; /*!< bit: 3 Secure floating-point active */ + uint32_t _reserved1:28; /*!< bit: 4..31 Reserved */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} CONTROL_Type; + +/* CONTROL Register Definitions */ +#define CONTROL_SFPA_Pos 3U /*!< CONTROL: SFPA Position */ +#define CONTROL_SFPA_Msk (1UL << CONTROL_SFPA_Pos) /*!< CONTROL: SFPA Mask */ + +#define CONTROL_FPCA_Pos 2U /*!< CONTROL: FPCA Position */ +#define CONTROL_FPCA_Msk (1UL << CONTROL_FPCA_Pos) /*!< CONTROL: FPCA Mask */ + +#define CONTROL_SPSEL_Pos 1U /*!< CONTROL: SPSEL Position */ +#define CONTROL_SPSEL_Msk (1UL << CONTROL_SPSEL_Pos) /*!< CONTROL: SPSEL Mask */ + +#define CONTROL_nPRIV_Pos 0U /*!< CONTROL: nPRIV Position */ +#define CONTROL_nPRIV_Msk (1UL /*<< CONTROL_nPRIV_Pos*/) /*!< CONTROL: nPRIV Mask */ + +/*@} end of group CMSIS_CORE */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_NVIC Nested Vectored Interrupt Controller (NVIC) + \brief Type definitions for the NVIC Registers + @{ + */ + +/** + \brief Structure type to access the Nested Vectored Interrupt Controller (NVIC). + */ +typedef struct +{ + __IOM uint32_t ISER[16U]; /*!< Offset: 0x000 (R/W) Interrupt Set Enable Register */ + uint32_t RESERVED0[16U]; + __IOM uint32_t ICER[16U]; /*!< Offset: 0x080 (R/W) Interrupt Clear Enable Register */ + uint32_t RSERVED1[16U]; + __IOM uint32_t ISPR[16U]; /*!< Offset: 0x100 (R/W) Interrupt Set Pending Register */ + uint32_t RESERVED2[16U]; + __IOM uint32_t ICPR[16U]; /*!< Offset: 0x180 (R/W) Interrupt Clear Pending Register */ + uint32_t RESERVED3[16U]; + __IOM uint32_t IABR[16U]; /*!< Offset: 0x200 (R/W) Interrupt Active bit Register */ + uint32_t RESERVED4[16U]; + __IOM uint32_t ITNS[16U]; /*!< Offset: 0x280 (R/W) Interrupt Non-Secure State Register */ + uint32_t RESERVED5[16U]; + __IOM uint8_t IPR[496U]; /*!< Offset: 0x300 (R/W) Interrupt Priority Register (8Bit wide) */ + uint32_t RESERVED6[580U]; + __OM uint32_t STIR; /*!< Offset: 0xE00 ( /W) Software Trigger Interrupt Register */ +} NVIC_Type; + +/* Software Triggered Interrupt Register Definitions */ +#define NVIC_STIR_INTID_Pos 0U /*!< STIR: INTLINESNUM Position */ +#define NVIC_STIR_INTID_Msk (0x1FFUL /*<< NVIC_STIR_INTID_Pos*/) /*!< STIR: INTLINESNUM Mask */ + +/*@} end of group CMSIS_NVIC */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_SCB System Control Block (SCB) + \brief Type definitions for the System Control Block Registers + @{ + */ + +/** + \brief Structure type to access the System Control Block (SCB). + */ +typedef struct +{ + __IM uint32_t CPUID; /*!< Offset: 0x000 (R/ ) CPUID Base Register */ + __IOM uint32_t ICSR; /*!< Offset: 0x004 (R/W) Interrupt Control and State Register */ + __IOM uint32_t VTOR; /*!< Offset: 0x008 (R/W) Vector Table Offset Register */ + __IOM uint32_t AIRCR; /*!< Offset: 0x00C (R/W) Application Interrupt and Reset Control Register */ + __IOM uint32_t SCR; /*!< Offset: 0x010 (R/W) System Control Register */ + __IOM uint32_t CCR; /*!< Offset: 0x014 (R/W) Configuration Control Register */ + __IOM uint8_t SHPR[12U]; /*!< Offset: 0x018 (R/W) System Handlers Priority Registers (4-7, 8-11, 12-15) */ + __IOM uint32_t SHCSR; /*!< Offset: 0x024 (R/W) System Handler Control and State Register */ + __IOM uint32_t CFSR; /*!< Offset: 0x028 (R/W) Configurable Fault Status Register */ + __IOM uint32_t HFSR; /*!< Offset: 0x02C (R/W) HardFault Status Register */ + __IOM uint32_t DFSR; /*!< Offset: 0x030 (R/W) Debug Fault Status Register */ + __IOM uint32_t MMFAR; /*!< Offset: 0x034 (R/W) MemManage Fault Address Register */ + __IOM uint32_t BFAR; /*!< Offset: 0x038 (R/W) BusFault Address Register */ + __IOM uint32_t AFSR; /*!< Offset: 0x03C (R/W) Auxiliary Fault Status Register */ + __IM uint32_t ID_PFR[2U]; /*!< Offset: 0x040 (R/ ) Processor Feature Register */ + __IM uint32_t ID_DFR; /*!< Offset: 0x048 (R/ ) Debug Feature Register */ + __IM uint32_t ID_ADR; /*!< Offset: 0x04C (R/ ) Auxiliary Feature Register */ + __IM uint32_t ID_MMFR[4U]; /*!< Offset: 0x050 (R/ ) Memory Model Feature Register */ + __IM uint32_t ID_ISAR[6U]; /*!< Offset: 0x060 (R/ ) Instruction Set Attributes Register */ + __IM uint32_t CLIDR; /*!< Offset: 0x078 (R/ ) Cache Level ID register */ + __IM uint32_t CTR; /*!< Offset: 0x07C (R/ ) Cache Type register */ + __IM uint32_t CCSIDR; /*!< Offset: 0x080 (R/ ) Cache Size ID Register */ + __IOM uint32_t CSSELR; /*!< Offset: 0x084 (R/W) Cache Size Selection Register */ + __IOM uint32_t CPACR; /*!< Offset: 0x088 (R/W) Coprocessor Access Control Register */ + __IOM uint32_t NSACR; /*!< Offset: 0x08C (R/W) Non-Secure Access Control Register */ + uint32_t RESERVED3[92U]; + __OM uint32_t STIR; /*!< Offset: 0x200 ( /W) Software Triggered Interrupt Register */ + uint32_t RESERVED4[15U]; + __IM uint32_t MVFR0; /*!< Offset: 0x240 (R/ ) Media and VFP Feature Register 0 */ + __IM uint32_t MVFR1; /*!< Offset: 0x244 (R/ ) Media and VFP Feature Register 1 */ + __IM uint32_t MVFR2; /*!< Offset: 0x248 (R/ ) Media and VFP Feature Register 2 */ + uint32_t RESERVED5[1U]; + __OM uint32_t ICIALLU; /*!< Offset: 0x250 ( /W) I-Cache Invalidate All to PoU */ + uint32_t RESERVED6[1U]; + __OM uint32_t ICIMVAU; /*!< Offset: 0x258 ( /W) I-Cache Invalidate by MVA to PoU */ + __OM uint32_t DCIMVAC; /*!< Offset: 0x25C ( /W) D-Cache Invalidate by MVA to PoC */ + __OM uint32_t DCISW; /*!< Offset: 0x260 ( /W) D-Cache Invalidate by Set-way */ + __OM uint32_t DCCMVAU; /*!< Offset: 0x264 ( /W) D-Cache Clean by MVA to PoU */ + __OM uint32_t DCCMVAC; /*!< Offset: 0x268 ( /W) D-Cache Clean by MVA to PoC */ + __OM uint32_t DCCSW; /*!< Offset: 0x26C ( /W) D-Cache Clean by Set-way */ + __OM uint32_t DCCIMVAC; /*!< Offset: 0x270 ( /W) D-Cache Clean and Invalidate by MVA to PoC */ + __OM uint32_t DCCISW; /*!< Offset: 0x274 ( /W) D-Cache Clean and Invalidate by Set-way */ +} SCB_Type; + +/* SCB CPUID Register Definitions */ +#define SCB_CPUID_IMPLEMENTER_Pos 24U /*!< SCB CPUID: IMPLEMENTER Position */ +#define SCB_CPUID_IMPLEMENTER_Msk (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos) /*!< SCB CPUID: IMPLEMENTER Mask */ + +#define SCB_CPUID_VARIANT_Pos 20U /*!< SCB CPUID: VARIANT Position */ +#define SCB_CPUID_VARIANT_Msk (0xFUL << SCB_CPUID_VARIANT_Pos) /*!< SCB CPUID: VARIANT Mask */ + +#define SCB_CPUID_ARCHITECTURE_Pos 16U /*!< SCB CPUID: ARCHITECTURE Position */ +#define SCB_CPUID_ARCHITECTURE_Msk (0xFUL << SCB_CPUID_ARCHITECTURE_Pos) /*!< SCB CPUID: ARCHITECTURE Mask */ + +#define SCB_CPUID_PARTNO_Pos 4U /*!< SCB CPUID: PARTNO Position */ +#define SCB_CPUID_PARTNO_Msk (0xFFFUL << SCB_CPUID_PARTNO_Pos) /*!< SCB CPUID: PARTNO Mask */ + +#define SCB_CPUID_REVISION_Pos 0U /*!< SCB CPUID: REVISION Position */ +#define SCB_CPUID_REVISION_Msk (0xFUL /*<< SCB_CPUID_REVISION_Pos*/) /*!< SCB CPUID: REVISION Mask */ + +/* SCB Interrupt Control State Register Definitions */ +#define SCB_ICSR_PENDNMISET_Pos 31U /*!< SCB ICSR: PENDNMISET Position */ +#define SCB_ICSR_PENDNMISET_Msk (1UL << SCB_ICSR_PENDNMISET_Pos) /*!< SCB ICSR: PENDNMISET Mask */ + +#define SCB_ICSR_NMIPENDSET_Pos SCB_ICSR_PENDNMISET_Pos /*!< SCB ICSR: NMIPENDSET Position, backward compatibility */ +#define SCB_ICSR_NMIPENDSET_Msk SCB_ICSR_PENDNMISET_Msk /*!< SCB ICSR: NMIPENDSET Mask, backward compatibility */ + +#define SCB_ICSR_PENDNMICLR_Pos 30U /*!< SCB ICSR: PENDNMICLR Position */ +#define SCB_ICSR_PENDNMICLR_Msk (1UL << SCB_ICSR_PENDNMICLR_Pos) /*!< SCB ICSR: PENDNMICLR Mask */ + +#define SCB_ICSR_PENDSVSET_Pos 28U /*!< SCB ICSR: PENDSVSET Position */ +#define SCB_ICSR_PENDSVSET_Msk (1UL << SCB_ICSR_PENDSVSET_Pos) /*!< SCB ICSR: PENDSVSET Mask */ + +#define SCB_ICSR_PENDSVCLR_Pos 27U /*!< SCB ICSR: PENDSVCLR Position */ +#define SCB_ICSR_PENDSVCLR_Msk (1UL << SCB_ICSR_PENDSVCLR_Pos) /*!< SCB ICSR: PENDSVCLR Mask */ + +#define SCB_ICSR_PENDSTSET_Pos 26U /*!< SCB ICSR: PENDSTSET Position */ +#define SCB_ICSR_PENDSTSET_Msk (1UL << SCB_ICSR_PENDSTSET_Pos) /*!< SCB ICSR: PENDSTSET Mask */ + +#define SCB_ICSR_PENDSTCLR_Pos 25U /*!< SCB ICSR: PENDSTCLR Position */ +#define SCB_ICSR_PENDSTCLR_Msk (1UL << SCB_ICSR_PENDSTCLR_Pos) /*!< SCB ICSR: PENDSTCLR Mask */ + +#define SCB_ICSR_STTNS_Pos 24U /*!< SCB ICSR: STTNS Position (Security Extension) */ +#define SCB_ICSR_STTNS_Msk (1UL << SCB_ICSR_STTNS_Pos) /*!< SCB ICSR: STTNS Mask (Security Extension) */ + +#define SCB_ICSR_ISRPREEMPT_Pos 23U /*!< SCB ICSR: ISRPREEMPT Position */ +#define SCB_ICSR_ISRPREEMPT_Msk (1UL << SCB_ICSR_ISRPREEMPT_Pos) /*!< SCB ICSR: ISRPREEMPT Mask */ + +#define SCB_ICSR_ISRPENDING_Pos 22U /*!< SCB ICSR: ISRPENDING Position */ +#define SCB_ICSR_ISRPENDING_Msk (1UL << SCB_ICSR_ISRPENDING_Pos) /*!< SCB ICSR: ISRPENDING Mask */ + +#define SCB_ICSR_VECTPENDING_Pos 12U /*!< SCB ICSR: VECTPENDING Position */ +#define SCB_ICSR_VECTPENDING_Msk (0x1FFUL << SCB_ICSR_VECTPENDING_Pos) /*!< SCB ICSR: VECTPENDING Mask */ + +#define SCB_ICSR_RETTOBASE_Pos 11U /*!< SCB ICSR: RETTOBASE Position */ +#define SCB_ICSR_RETTOBASE_Msk (1UL << SCB_ICSR_RETTOBASE_Pos) /*!< SCB ICSR: RETTOBASE Mask */ + +#define SCB_ICSR_VECTACTIVE_Pos 0U /*!< SCB ICSR: VECTACTIVE Position */ +#define SCB_ICSR_VECTACTIVE_Msk (0x1FFUL /*<< SCB_ICSR_VECTACTIVE_Pos*/) /*!< SCB ICSR: VECTACTIVE Mask */ + +/* SCB Vector Table Offset Register Definitions */ +#define SCB_VTOR_TBLOFF_Pos 7U /*!< SCB VTOR: TBLOFF Position */ +#define SCB_VTOR_TBLOFF_Msk (0x1FFFFFFUL << SCB_VTOR_TBLOFF_Pos) /*!< SCB VTOR: TBLOFF Mask */ + +/* SCB Application Interrupt and Reset Control Register Definitions */ +#define SCB_AIRCR_VECTKEY_Pos 16U /*!< SCB AIRCR: VECTKEY Position */ +#define SCB_AIRCR_VECTKEY_Msk (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos) /*!< SCB AIRCR: VECTKEY Mask */ + +#define SCB_AIRCR_VECTKEYSTAT_Pos 16U /*!< SCB AIRCR: VECTKEYSTAT Position */ +#define SCB_AIRCR_VECTKEYSTAT_Msk (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos) /*!< SCB AIRCR: VECTKEYSTAT Mask */ + +#define SCB_AIRCR_ENDIANESS_Pos 15U /*!< SCB AIRCR: ENDIANESS Position */ +#define SCB_AIRCR_ENDIANESS_Msk (1UL << SCB_AIRCR_ENDIANESS_Pos) /*!< SCB AIRCR: ENDIANESS Mask */ + +#define SCB_AIRCR_PRIS_Pos 14U /*!< SCB AIRCR: PRIS Position */ +#define SCB_AIRCR_PRIS_Msk (1UL << SCB_AIRCR_PRIS_Pos) /*!< SCB AIRCR: PRIS Mask */ + +#define SCB_AIRCR_BFHFNMINS_Pos 13U /*!< SCB AIRCR: BFHFNMINS Position */ +#define SCB_AIRCR_BFHFNMINS_Msk (1UL << SCB_AIRCR_BFHFNMINS_Pos) /*!< SCB AIRCR: BFHFNMINS Mask */ + +#define SCB_AIRCR_PRIGROUP_Pos 8U /*!< SCB AIRCR: PRIGROUP Position */ +#define SCB_AIRCR_PRIGROUP_Msk (7UL << SCB_AIRCR_PRIGROUP_Pos) /*!< SCB AIRCR: PRIGROUP Mask */ + +#define SCB_AIRCR_SYSRESETREQS_Pos 3U /*!< SCB AIRCR: SYSRESETREQS Position */ +#define SCB_AIRCR_SYSRESETREQS_Msk (1UL << SCB_AIRCR_SYSRESETREQS_Pos) /*!< SCB AIRCR: SYSRESETREQS Mask */ + +#define SCB_AIRCR_SYSRESETREQ_Pos 2U /*!< SCB AIRCR: SYSRESETREQ Position */ +#define SCB_AIRCR_SYSRESETREQ_Msk (1UL << SCB_AIRCR_SYSRESETREQ_Pos) /*!< SCB AIRCR: SYSRESETREQ Mask */ + +#define SCB_AIRCR_VECTCLRACTIVE_Pos 1U /*!< SCB AIRCR: VECTCLRACTIVE Position */ +#define SCB_AIRCR_VECTCLRACTIVE_Msk (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos) /*!< SCB AIRCR: VECTCLRACTIVE Mask */ + +/* SCB System Control Register Definitions */ +#define SCB_SCR_SEVONPEND_Pos 4U /*!< SCB SCR: SEVONPEND Position */ +#define SCB_SCR_SEVONPEND_Msk (1UL << SCB_SCR_SEVONPEND_Pos) /*!< SCB SCR: SEVONPEND Mask */ + +#define SCB_SCR_SLEEPDEEPS_Pos 3U /*!< SCB SCR: SLEEPDEEPS Position */ +#define SCB_SCR_SLEEPDEEPS_Msk (1UL << SCB_SCR_SLEEPDEEPS_Pos) /*!< SCB SCR: SLEEPDEEPS Mask */ + +#define SCB_SCR_SLEEPDEEP_Pos 2U /*!< SCB SCR: SLEEPDEEP Position */ +#define SCB_SCR_SLEEPDEEP_Msk (1UL << SCB_SCR_SLEEPDEEP_Pos) /*!< SCB SCR: SLEEPDEEP Mask */ + +#define SCB_SCR_SLEEPONEXIT_Pos 1U /*!< SCB SCR: SLEEPONEXIT Position */ +#define SCB_SCR_SLEEPONEXIT_Msk (1UL << SCB_SCR_SLEEPONEXIT_Pos) /*!< SCB SCR: SLEEPONEXIT Mask */ + +/* SCB Configuration Control Register Definitions */ +#define SCB_CCR_BP_Pos 18U /*!< SCB CCR: BP Position */ +#define SCB_CCR_BP_Msk (1UL << SCB_CCR_BP_Pos) /*!< SCB CCR: BP Mask */ + +#define SCB_CCR_IC_Pos 17U /*!< SCB CCR: IC Position */ +#define SCB_CCR_IC_Msk (1UL << SCB_CCR_IC_Pos) /*!< SCB CCR: IC Mask */ + +#define SCB_CCR_DC_Pos 16U /*!< SCB CCR: DC Position */ +#define SCB_CCR_DC_Msk (1UL << SCB_CCR_DC_Pos) /*!< SCB CCR: DC Mask */ + +#define SCB_CCR_STKOFHFNMIGN_Pos 10U /*!< SCB CCR: STKOFHFNMIGN Position */ +#define SCB_CCR_STKOFHFNMIGN_Msk (1UL << SCB_CCR_STKOFHFNMIGN_Pos) /*!< SCB CCR: STKOFHFNMIGN Mask */ + +#define SCB_CCR_BFHFNMIGN_Pos 8U /*!< SCB CCR: BFHFNMIGN Position */ +#define SCB_CCR_BFHFNMIGN_Msk (1UL << SCB_CCR_BFHFNMIGN_Pos) /*!< SCB CCR: BFHFNMIGN Mask */ + +#define SCB_CCR_DIV_0_TRP_Pos 4U /*!< SCB CCR: DIV_0_TRP Position */ +#define SCB_CCR_DIV_0_TRP_Msk (1UL << SCB_CCR_DIV_0_TRP_Pos) /*!< SCB CCR: DIV_0_TRP Mask */ + +#define SCB_CCR_UNALIGN_TRP_Pos 3U /*!< SCB CCR: UNALIGN_TRP Position */ +#define SCB_CCR_UNALIGN_TRP_Msk (1UL << SCB_CCR_UNALIGN_TRP_Pos) /*!< SCB CCR: UNALIGN_TRP Mask */ + +#define SCB_CCR_USERSETMPEND_Pos 1U /*!< SCB CCR: USERSETMPEND Position */ +#define SCB_CCR_USERSETMPEND_Msk (1UL << SCB_CCR_USERSETMPEND_Pos) /*!< SCB CCR: USERSETMPEND Mask */ + +/* SCB System Handler Control and State Register Definitions */ +#define SCB_SHCSR_HARDFAULTPENDED_Pos 21U /*!< SCB SHCSR: HARDFAULTPENDED Position */ +#define SCB_SHCSR_HARDFAULTPENDED_Msk (1UL << SCB_SHCSR_HARDFAULTPENDED_Pos) /*!< SCB SHCSR: HARDFAULTPENDED Mask */ + +#define SCB_SHCSR_SECUREFAULTPENDED_Pos 20U /*!< SCB SHCSR: SECUREFAULTPENDED Position */ +#define SCB_SHCSR_SECUREFAULTPENDED_Msk (1UL << SCB_SHCSR_SECUREFAULTPENDED_Pos) /*!< SCB SHCSR: SECUREFAULTPENDED Mask */ + +#define SCB_SHCSR_SECUREFAULTENA_Pos 19U /*!< SCB SHCSR: SECUREFAULTENA Position */ +#define SCB_SHCSR_SECUREFAULTENA_Msk (1UL << SCB_SHCSR_SECUREFAULTENA_Pos) /*!< SCB SHCSR: SECUREFAULTENA Mask */ + +#define SCB_SHCSR_USGFAULTENA_Pos 18U /*!< SCB SHCSR: USGFAULTENA Position */ +#define SCB_SHCSR_USGFAULTENA_Msk (1UL << SCB_SHCSR_USGFAULTENA_Pos) /*!< SCB SHCSR: USGFAULTENA Mask */ + +#define SCB_SHCSR_BUSFAULTENA_Pos 17U /*!< SCB SHCSR: BUSFAULTENA Position */ +#define SCB_SHCSR_BUSFAULTENA_Msk (1UL << SCB_SHCSR_BUSFAULTENA_Pos) /*!< SCB SHCSR: BUSFAULTENA Mask */ + +#define SCB_SHCSR_MEMFAULTENA_Pos 16U /*!< SCB SHCSR: MEMFAULTENA Position */ +#define SCB_SHCSR_MEMFAULTENA_Msk (1UL << SCB_SHCSR_MEMFAULTENA_Pos) /*!< SCB SHCSR: MEMFAULTENA Mask */ + +#define SCB_SHCSR_SVCALLPENDED_Pos 15U /*!< SCB SHCSR: SVCALLPENDED Position */ +#define SCB_SHCSR_SVCALLPENDED_Msk (1UL << SCB_SHCSR_SVCALLPENDED_Pos) /*!< SCB SHCSR: SVCALLPENDED Mask */ + +#define SCB_SHCSR_BUSFAULTPENDED_Pos 14U /*!< SCB SHCSR: BUSFAULTPENDED Position */ +#define SCB_SHCSR_BUSFAULTPENDED_Msk (1UL << SCB_SHCSR_BUSFAULTPENDED_Pos) /*!< SCB SHCSR: BUSFAULTPENDED Mask */ + +#define SCB_SHCSR_MEMFAULTPENDED_Pos 13U /*!< SCB SHCSR: MEMFAULTPENDED Position */ +#define SCB_SHCSR_MEMFAULTPENDED_Msk (1UL << SCB_SHCSR_MEMFAULTPENDED_Pos) /*!< SCB SHCSR: MEMFAULTPENDED Mask */ + +#define SCB_SHCSR_USGFAULTPENDED_Pos 12U /*!< SCB SHCSR: USGFAULTPENDED Position */ +#define SCB_SHCSR_USGFAULTPENDED_Msk (1UL << SCB_SHCSR_USGFAULTPENDED_Pos) /*!< SCB SHCSR: USGFAULTPENDED Mask */ + +#define SCB_SHCSR_SYSTICKACT_Pos 11U /*!< SCB SHCSR: SYSTICKACT Position */ +#define SCB_SHCSR_SYSTICKACT_Msk (1UL << SCB_SHCSR_SYSTICKACT_Pos) /*!< SCB SHCSR: SYSTICKACT Mask */ + +#define SCB_SHCSR_PENDSVACT_Pos 10U /*!< SCB SHCSR: PENDSVACT Position */ +#define SCB_SHCSR_PENDSVACT_Msk (1UL << SCB_SHCSR_PENDSVACT_Pos) /*!< SCB SHCSR: PENDSVACT Mask */ + +#define SCB_SHCSR_MONITORACT_Pos 8U /*!< SCB SHCSR: MONITORACT Position */ +#define SCB_SHCSR_MONITORACT_Msk (1UL << SCB_SHCSR_MONITORACT_Pos) /*!< SCB SHCSR: MONITORACT Mask */ + +#define SCB_SHCSR_SVCALLACT_Pos 7U /*!< SCB SHCSR: SVCALLACT Position */ +#define SCB_SHCSR_SVCALLACT_Msk (1UL << SCB_SHCSR_SVCALLACT_Pos) /*!< SCB SHCSR: SVCALLACT Mask */ + +#define SCB_SHCSR_NMIACT_Pos 5U /*!< SCB SHCSR: NMIACT Position */ +#define SCB_SHCSR_NMIACT_Msk (1UL << SCB_SHCSR_NMIACT_Pos) /*!< SCB SHCSR: NMIACT Mask */ + +#define SCB_SHCSR_SECUREFAULTACT_Pos 4U /*!< SCB SHCSR: SECUREFAULTACT Position */ +#define SCB_SHCSR_SECUREFAULTACT_Msk (1UL << SCB_SHCSR_SECUREFAULTACT_Pos) /*!< SCB SHCSR: SECUREFAULTACT Mask */ + +#define SCB_SHCSR_USGFAULTACT_Pos 3U /*!< SCB SHCSR: USGFAULTACT Position */ +#define SCB_SHCSR_USGFAULTACT_Msk (1UL << SCB_SHCSR_USGFAULTACT_Pos) /*!< SCB SHCSR: USGFAULTACT Mask */ + +#define SCB_SHCSR_HARDFAULTACT_Pos 2U /*!< SCB SHCSR: HARDFAULTACT Position */ +#define SCB_SHCSR_HARDFAULTACT_Msk (1UL << SCB_SHCSR_HARDFAULTACT_Pos) /*!< SCB SHCSR: HARDFAULTACT Mask */ + +#define SCB_SHCSR_BUSFAULTACT_Pos 1U /*!< SCB SHCSR: BUSFAULTACT Position */ +#define SCB_SHCSR_BUSFAULTACT_Msk (1UL << SCB_SHCSR_BUSFAULTACT_Pos) /*!< SCB SHCSR: BUSFAULTACT Mask */ + +#define SCB_SHCSR_MEMFAULTACT_Pos 0U /*!< SCB SHCSR: MEMFAULTACT Position */ +#define SCB_SHCSR_MEMFAULTACT_Msk (1UL /*<< SCB_SHCSR_MEMFAULTACT_Pos*/) /*!< SCB SHCSR: MEMFAULTACT Mask */ + +/* SCB Configurable Fault Status Register Definitions */ +#define SCB_CFSR_USGFAULTSR_Pos 16U /*!< SCB CFSR: Usage Fault Status Register Position */ +#define SCB_CFSR_USGFAULTSR_Msk (0xFFFFUL << SCB_CFSR_USGFAULTSR_Pos) /*!< SCB CFSR: Usage Fault Status Register Mask */ + +#define SCB_CFSR_BUSFAULTSR_Pos 8U /*!< SCB CFSR: Bus Fault Status Register Position */ +#define SCB_CFSR_BUSFAULTSR_Msk (0xFFUL << SCB_CFSR_BUSFAULTSR_Pos) /*!< SCB CFSR: Bus Fault Status Register Mask */ + +#define SCB_CFSR_MEMFAULTSR_Pos 0U /*!< SCB CFSR: Memory Manage Fault Status Register Position */ +#define SCB_CFSR_MEMFAULTSR_Msk (0xFFUL /*<< SCB_CFSR_MEMFAULTSR_Pos*/) /*!< SCB CFSR: Memory Manage Fault Status Register Mask */ + +/* MemManage Fault Status Register (part of SCB Configurable Fault Status Register) */ +#define SCB_CFSR_MMARVALID_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 7U) /*!< SCB CFSR (MMFSR): MMARVALID Position */ +#define SCB_CFSR_MMARVALID_Msk (1UL << SCB_CFSR_MMARVALID_Pos) /*!< SCB CFSR (MMFSR): MMARVALID Mask */ + +#define SCB_CFSR_MLSPERR_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 5U) /*!< SCB CFSR (MMFSR): MLSPERR Position */ +#define SCB_CFSR_MLSPERR_Msk (1UL << SCB_CFSR_MLSPERR_Pos) /*!< SCB CFSR (MMFSR): MLSPERR Mask */ + +#define SCB_CFSR_MSTKERR_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 4U) /*!< SCB CFSR (MMFSR): MSTKERR Position */ +#define SCB_CFSR_MSTKERR_Msk (1UL << SCB_CFSR_MSTKERR_Pos) /*!< SCB CFSR (MMFSR): MSTKERR Mask */ + +#define SCB_CFSR_MUNSTKERR_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 3U) /*!< SCB CFSR (MMFSR): MUNSTKERR Position */ +#define SCB_CFSR_MUNSTKERR_Msk (1UL << SCB_CFSR_MUNSTKERR_Pos) /*!< SCB CFSR (MMFSR): MUNSTKERR Mask */ + +#define SCB_CFSR_DACCVIOL_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 1U) /*!< SCB CFSR (MMFSR): DACCVIOL Position */ +#define SCB_CFSR_DACCVIOL_Msk (1UL << SCB_CFSR_DACCVIOL_Pos) /*!< SCB CFSR (MMFSR): DACCVIOL Mask */ + +#define SCB_CFSR_IACCVIOL_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 0U) /*!< SCB CFSR (MMFSR): IACCVIOL Position */ +#define SCB_CFSR_IACCVIOL_Msk (1UL /*<< SCB_CFSR_IACCVIOL_Pos*/) /*!< SCB CFSR (MMFSR): IACCVIOL Mask */ + +/* BusFault Status Register (part of SCB Configurable Fault Status Register) */ +#define SCB_CFSR_BFARVALID_Pos (SCB_CFSR_BUSFAULTSR_Pos + 7U) /*!< SCB CFSR (BFSR): BFARVALID Position */ +#define SCB_CFSR_BFARVALID_Msk (1UL << SCB_CFSR_BFARVALID_Pos) /*!< SCB CFSR (BFSR): BFARVALID Mask */ + +#define SCB_CFSR_LSPERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 5U) /*!< SCB CFSR (BFSR): LSPERR Position */ +#define SCB_CFSR_LSPERR_Msk (1UL << SCB_CFSR_LSPERR_Pos) /*!< SCB CFSR (BFSR): LSPERR Mask */ + +#define SCB_CFSR_STKERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 4U) /*!< SCB CFSR (BFSR): STKERR Position */ +#define SCB_CFSR_STKERR_Msk (1UL << SCB_CFSR_STKERR_Pos) /*!< SCB CFSR (BFSR): STKERR Mask */ + +#define SCB_CFSR_UNSTKERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 3U) /*!< SCB CFSR (BFSR): UNSTKERR Position */ +#define SCB_CFSR_UNSTKERR_Msk (1UL << SCB_CFSR_UNSTKERR_Pos) /*!< SCB CFSR (BFSR): UNSTKERR Mask */ + +#define SCB_CFSR_IMPRECISERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 2U) /*!< SCB CFSR (BFSR): IMPRECISERR Position */ +#define SCB_CFSR_IMPRECISERR_Msk (1UL << SCB_CFSR_IMPRECISERR_Pos) /*!< SCB CFSR (BFSR): IMPRECISERR Mask */ + +#define SCB_CFSR_PRECISERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 1U) /*!< SCB CFSR (BFSR): PRECISERR Position */ +#define SCB_CFSR_PRECISERR_Msk (1UL << SCB_CFSR_PRECISERR_Pos) /*!< SCB CFSR (BFSR): PRECISERR Mask */ + +#define SCB_CFSR_IBUSERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 0U) /*!< SCB CFSR (BFSR): IBUSERR Position */ +#define SCB_CFSR_IBUSERR_Msk (1UL << SCB_CFSR_IBUSERR_Pos) /*!< SCB CFSR (BFSR): IBUSERR Mask */ + +/* UsageFault Status Register (part of SCB Configurable Fault Status Register) */ +#define SCB_CFSR_DIVBYZERO_Pos (SCB_CFSR_USGFAULTSR_Pos + 9U) /*!< SCB CFSR (UFSR): DIVBYZERO Position */ +#define SCB_CFSR_DIVBYZERO_Msk (1UL << SCB_CFSR_DIVBYZERO_Pos) /*!< SCB CFSR (UFSR): DIVBYZERO Mask */ + +#define SCB_CFSR_UNALIGNED_Pos (SCB_CFSR_USGFAULTSR_Pos + 8U) /*!< SCB CFSR (UFSR): UNALIGNED Position */ +#define SCB_CFSR_UNALIGNED_Msk (1UL << SCB_CFSR_UNALIGNED_Pos) /*!< SCB CFSR (UFSR): UNALIGNED Mask */ + +#define SCB_CFSR_STKOF_Pos (SCB_CFSR_USGFAULTSR_Pos + 4U) /*!< SCB CFSR (UFSR): STKOF Position */ +#define SCB_CFSR_STKOF_Msk (1UL << SCB_CFSR_STKOF_Pos) /*!< SCB CFSR (UFSR): STKOF Mask */ + +#define SCB_CFSR_NOCP_Pos (SCB_CFSR_USGFAULTSR_Pos + 3U) /*!< SCB CFSR (UFSR): NOCP Position */ +#define SCB_CFSR_NOCP_Msk (1UL << SCB_CFSR_NOCP_Pos) /*!< SCB CFSR (UFSR): NOCP Mask */ + +#define SCB_CFSR_INVPC_Pos (SCB_CFSR_USGFAULTSR_Pos + 2U) /*!< SCB CFSR (UFSR): INVPC Position */ +#define SCB_CFSR_INVPC_Msk (1UL << SCB_CFSR_INVPC_Pos) /*!< SCB CFSR (UFSR): INVPC Mask */ + +#define SCB_CFSR_INVSTATE_Pos (SCB_CFSR_USGFAULTSR_Pos + 1U) /*!< SCB CFSR (UFSR): INVSTATE Position */ +#define SCB_CFSR_INVSTATE_Msk (1UL << SCB_CFSR_INVSTATE_Pos) /*!< SCB CFSR (UFSR): INVSTATE Mask */ + +#define SCB_CFSR_UNDEFINSTR_Pos (SCB_CFSR_USGFAULTSR_Pos + 0U) /*!< SCB CFSR (UFSR): UNDEFINSTR Position */ +#define SCB_CFSR_UNDEFINSTR_Msk (1UL << SCB_CFSR_UNDEFINSTR_Pos) /*!< SCB CFSR (UFSR): UNDEFINSTR Mask */ + +/* SCB Hard Fault Status Register Definitions */ +#define SCB_HFSR_DEBUGEVT_Pos 31U /*!< SCB HFSR: DEBUGEVT Position */ +#define SCB_HFSR_DEBUGEVT_Msk (1UL << SCB_HFSR_DEBUGEVT_Pos) /*!< SCB HFSR: DEBUGEVT Mask */ + +#define SCB_HFSR_FORCED_Pos 30U /*!< SCB HFSR: FORCED Position */ +#define SCB_HFSR_FORCED_Msk (1UL << SCB_HFSR_FORCED_Pos) /*!< SCB HFSR: FORCED Mask */ + +#define SCB_HFSR_VECTTBL_Pos 1U /*!< SCB HFSR: VECTTBL Position */ +#define SCB_HFSR_VECTTBL_Msk (1UL << SCB_HFSR_VECTTBL_Pos) /*!< SCB HFSR: VECTTBL Mask */ + +/* SCB Debug Fault Status Register Definitions */ +#define SCB_DFSR_EXTERNAL_Pos 4U /*!< SCB DFSR: EXTERNAL Position */ +#define SCB_DFSR_EXTERNAL_Msk (1UL << SCB_DFSR_EXTERNAL_Pos) /*!< SCB DFSR: EXTERNAL Mask */ + +#define SCB_DFSR_VCATCH_Pos 3U /*!< SCB DFSR: VCATCH Position */ +#define SCB_DFSR_VCATCH_Msk (1UL << SCB_DFSR_VCATCH_Pos) /*!< SCB DFSR: VCATCH Mask */ + +#define SCB_DFSR_DWTTRAP_Pos 2U /*!< SCB DFSR: DWTTRAP Position */ +#define SCB_DFSR_DWTTRAP_Msk (1UL << SCB_DFSR_DWTTRAP_Pos) /*!< SCB DFSR: DWTTRAP Mask */ + +#define SCB_DFSR_BKPT_Pos 1U /*!< SCB DFSR: BKPT Position */ +#define SCB_DFSR_BKPT_Msk (1UL << SCB_DFSR_BKPT_Pos) /*!< SCB DFSR: BKPT Mask */ + +#define SCB_DFSR_HALTED_Pos 0U /*!< SCB DFSR: HALTED Position */ +#define SCB_DFSR_HALTED_Msk (1UL /*<< SCB_DFSR_HALTED_Pos*/) /*!< SCB DFSR: HALTED Mask */ + +/* SCB Non-Secure Access Control Register Definitions */ +#define SCB_NSACR_CP11_Pos 11U /*!< SCB NSACR: CP11 Position */ +#define SCB_NSACR_CP11_Msk (1UL << SCB_NSACR_CP11_Pos) /*!< SCB NSACR: CP11 Mask */ + +#define SCB_NSACR_CP10_Pos 10U /*!< SCB NSACR: CP10 Position */ +#define SCB_NSACR_CP10_Msk (1UL << SCB_NSACR_CP10_Pos) /*!< SCB NSACR: CP10 Mask */ + +#define SCB_NSACR_CPn_Pos 0U /*!< SCB NSACR: CPn Position */ +#define SCB_NSACR_CPn_Msk (1UL /*<< SCB_NSACR_CPn_Pos*/) /*!< SCB NSACR: CPn Mask */ + +/* SCB Cache Level ID Register Definitions */ +#define SCB_CLIDR_LOUU_Pos 27U /*!< SCB CLIDR: LoUU Position */ +#define SCB_CLIDR_LOUU_Msk (7UL << SCB_CLIDR_LOUU_Pos) /*!< SCB CLIDR: LoUU Mask */ + +#define SCB_CLIDR_LOC_Pos 24U /*!< SCB CLIDR: LoC Position */ +#define SCB_CLIDR_LOC_Msk (7UL << SCB_CLIDR_LOC_Pos) /*!< SCB CLIDR: LoC Mask */ + +/* SCB Cache Type Register Definitions */ +#define SCB_CTR_FORMAT_Pos 29U /*!< SCB CTR: Format Position */ +#define SCB_CTR_FORMAT_Msk (7UL << SCB_CTR_FORMAT_Pos) /*!< SCB CTR: Format Mask */ + +#define SCB_CTR_CWG_Pos 24U /*!< SCB CTR: CWG Position */ +#define SCB_CTR_CWG_Msk (0xFUL << SCB_CTR_CWG_Pos) /*!< SCB CTR: CWG Mask */ + +#define SCB_CTR_ERG_Pos 20U /*!< SCB CTR: ERG Position */ +#define SCB_CTR_ERG_Msk (0xFUL << SCB_CTR_ERG_Pos) /*!< SCB CTR: ERG Mask */ + +#define SCB_CTR_DMINLINE_Pos 16U /*!< SCB CTR: DminLine Position */ +#define SCB_CTR_DMINLINE_Msk (0xFUL << SCB_CTR_DMINLINE_Pos) /*!< SCB CTR: DminLine Mask */ + +#define SCB_CTR_IMINLINE_Pos 0U /*!< SCB CTR: ImInLine Position */ +#define SCB_CTR_IMINLINE_Msk (0xFUL /*<< SCB_CTR_IMINLINE_Pos*/) /*!< SCB CTR: ImInLine Mask */ + +/* SCB Cache Size ID Register Definitions */ +#define SCB_CCSIDR_WT_Pos 31U /*!< SCB CCSIDR: WT Position */ +#define SCB_CCSIDR_WT_Msk (1UL << SCB_CCSIDR_WT_Pos) /*!< SCB CCSIDR: WT Mask */ + +#define SCB_CCSIDR_WB_Pos 30U /*!< SCB CCSIDR: WB Position */ +#define SCB_CCSIDR_WB_Msk (1UL << SCB_CCSIDR_WB_Pos) /*!< SCB CCSIDR: WB Mask */ + +#define SCB_CCSIDR_RA_Pos 29U /*!< SCB CCSIDR: RA Position */ +#define SCB_CCSIDR_RA_Msk (1UL << SCB_CCSIDR_RA_Pos) /*!< SCB CCSIDR: RA Mask */ + +#define SCB_CCSIDR_WA_Pos 28U /*!< SCB CCSIDR: WA Position */ +#define SCB_CCSIDR_WA_Msk (1UL << SCB_CCSIDR_WA_Pos) /*!< SCB CCSIDR: WA Mask */ + +#define SCB_CCSIDR_NUMSETS_Pos 13U /*!< SCB CCSIDR: NumSets Position */ +#define SCB_CCSIDR_NUMSETS_Msk (0x7FFFUL << SCB_CCSIDR_NUMSETS_Pos) /*!< SCB CCSIDR: NumSets Mask */ + +#define SCB_CCSIDR_ASSOCIATIVITY_Pos 3U /*!< SCB CCSIDR: Associativity Position */ +#define SCB_CCSIDR_ASSOCIATIVITY_Msk (0x3FFUL << SCB_CCSIDR_ASSOCIATIVITY_Pos) /*!< SCB CCSIDR: Associativity Mask */ + +#define SCB_CCSIDR_LINESIZE_Pos 0U /*!< SCB CCSIDR: LineSize Position */ +#define SCB_CCSIDR_LINESIZE_Msk (7UL /*<< SCB_CCSIDR_LINESIZE_Pos*/) /*!< SCB CCSIDR: LineSize Mask */ + +/* SCB Cache Size Selection Register Definitions */ +#define SCB_CSSELR_LEVEL_Pos 1U /*!< SCB CSSELR: Level Position */ +#define SCB_CSSELR_LEVEL_Msk (7UL << SCB_CSSELR_LEVEL_Pos) /*!< SCB CSSELR: Level Mask */ + +#define SCB_CSSELR_IND_Pos 0U /*!< SCB CSSELR: InD Position */ +#define SCB_CSSELR_IND_Msk (1UL /*<< SCB_CSSELR_IND_Pos*/) /*!< SCB CSSELR: InD Mask */ + +/* SCB Software Triggered Interrupt Register Definitions */ +#define SCB_STIR_INTID_Pos 0U /*!< SCB STIR: INTID Position */ +#define SCB_STIR_INTID_Msk (0x1FFUL /*<< SCB_STIR_INTID_Pos*/) /*!< SCB STIR: INTID Mask */ + +/* SCB D-Cache Invalidate by Set-way Register Definitions */ +#define SCB_DCISW_WAY_Pos 30U /*!< SCB DCISW: Way Position */ +#define SCB_DCISW_WAY_Msk (3UL << SCB_DCISW_WAY_Pos) /*!< SCB DCISW: Way Mask */ + +#define SCB_DCISW_SET_Pos 5U /*!< SCB DCISW: Set Position */ +#define SCB_DCISW_SET_Msk (0x1FFUL << SCB_DCISW_SET_Pos) /*!< SCB DCISW: Set Mask */ + +/* SCB D-Cache Clean by Set-way Register Definitions */ +#define SCB_DCCSW_WAY_Pos 30U /*!< SCB DCCSW: Way Position */ +#define SCB_DCCSW_WAY_Msk (3UL << SCB_DCCSW_WAY_Pos) /*!< SCB DCCSW: Way Mask */ + +#define SCB_DCCSW_SET_Pos 5U /*!< SCB DCCSW: Set Position */ +#define SCB_DCCSW_SET_Msk (0x1FFUL << SCB_DCCSW_SET_Pos) /*!< SCB DCCSW: Set Mask */ + +/* SCB D-Cache Clean and Invalidate by Set-way Register Definitions */ +#define SCB_DCCISW_WAY_Pos 30U /*!< SCB DCCISW: Way Position */ +#define SCB_DCCISW_WAY_Msk (3UL << SCB_DCCISW_WAY_Pos) /*!< SCB DCCISW: Way Mask */ + +#define SCB_DCCISW_SET_Pos 5U /*!< SCB DCCISW: Set Position */ +#define SCB_DCCISW_SET_Msk (0x1FFUL << SCB_DCCISW_SET_Pos) /*!< SCB DCCISW: Set Mask */ + +/*@} end of group CMSIS_SCB */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_SCnSCB System Controls not in SCB (SCnSCB) + \brief Type definitions for the System Control and ID Register not in the SCB + @{ + */ + +/** + \brief Structure type to access the System Control and ID Register not in the SCB. + */ +typedef struct +{ + uint32_t RESERVED0[1U]; + __IM uint32_t ICTR; /*!< Offset: 0x004 (R/ ) Interrupt Controller Type Register */ + __IOM uint32_t ACTLR; /*!< Offset: 0x008 (R/W) Auxiliary Control Register */ + __IOM uint32_t CPPWR; /*!< Offset: 0x00C (R/W) Coprocessor Power Control Register */ +} SCnSCB_Type; + +/* Interrupt Controller Type Register Definitions */ +#define SCnSCB_ICTR_INTLINESNUM_Pos 0U /*!< ICTR: INTLINESNUM Position */ +#define SCnSCB_ICTR_INTLINESNUM_Msk (0xFUL /*<< SCnSCB_ICTR_INTLINESNUM_Pos*/) /*!< ICTR: INTLINESNUM Mask */ + +/*@} end of group CMSIS_SCnotSCB */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_SysTick System Tick Timer (SysTick) + \brief Type definitions for the System Timer Registers. + @{ + */ + +/** + \brief Structure type to access the System Timer (SysTick). + */ +typedef struct +{ + __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) SysTick Control and Status Register */ + __IOM uint32_t LOAD; /*!< Offset: 0x004 (R/W) SysTick Reload Value Register */ + __IOM uint32_t VAL; /*!< Offset: 0x008 (R/W) SysTick Current Value Register */ + __IM uint32_t CALIB; /*!< Offset: 0x00C (R/ ) SysTick Calibration Register */ +} SysTick_Type; + +/* SysTick Control / Status Register Definitions */ +#define SysTick_CTRL_COUNTFLAG_Pos 16U /*!< SysTick CTRL: COUNTFLAG Position */ +#define SysTick_CTRL_COUNTFLAG_Msk (1UL << SysTick_CTRL_COUNTFLAG_Pos) /*!< SysTick CTRL: COUNTFLAG Mask */ + +#define SysTick_CTRL_CLKSOURCE_Pos 2U /*!< SysTick CTRL: CLKSOURCE Position */ +#define SysTick_CTRL_CLKSOURCE_Msk (1UL << SysTick_CTRL_CLKSOURCE_Pos) /*!< SysTick CTRL: CLKSOURCE Mask */ + +#define SysTick_CTRL_TICKINT_Pos 1U /*!< SysTick CTRL: TICKINT Position */ +#define SysTick_CTRL_TICKINT_Msk (1UL << SysTick_CTRL_TICKINT_Pos) /*!< SysTick CTRL: TICKINT Mask */ + +#define SysTick_CTRL_ENABLE_Pos 0U /*!< SysTick CTRL: ENABLE Position */ +#define SysTick_CTRL_ENABLE_Msk (1UL /*<< SysTick_CTRL_ENABLE_Pos*/) /*!< SysTick CTRL: ENABLE Mask */ + +/* SysTick Reload Register Definitions */ +#define SysTick_LOAD_RELOAD_Pos 0U /*!< SysTick LOAD: RELOAD Position */ +#define SysTick_LOAD_RELOAD_Msk (0xFFFFFFUL /*<< SysTick_LOAD_RELOAD_Pos*/) /*!< SysTick LOAD: RELOAD Mask */ + +/* SysTick Current Register Definitions */ +#define SysTick_VAL_CURRENT_Pos 0U /*!< SysTick VAL: CURRENT Position */ +#define SysTick_VAL_CURRENT_Msk (0xFFFFFFUL /*<< SysTick_VAL_CURRENT_Pos*/) /*!< SysTick VAL: CURRENT Mask */ + +/* SysTick Calibration Register Definitions */ +#define SysTick_CALIB_NOREF_Pos 31U /*!< SysTick CALIB: NOREF Position */ +#define SysTick_CALIB_NOREF_Msk (1UL << SysTick_CALIB_NOREF_Pos) /*!< SysTick CALIB: NOREF Mask */ + +#define SysTick_CALIB_SKEW_Pos 30U /*!< SysTick CALIB: SKEW Position */ +#define SysTick_CALIB_SKEW_Msk (1UL << SysTick_CALIB_SKEW_Pos) /*!< SysTick CALIB: SKEW Mask */ + +#define SysTick_CALIB_TENMS_Pos 0U /*!< SysTick CALIB: TENMS Position */ +#define SysTick_CALIB_TENMS_Msk (0xFFFFFFUL /*<< SysTick_CALIB_TENMS_Pos*/) /*!< SysTick CALIB: TENMS Mask */ + +/*@} end of group CMSIS_SysTick */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_ITM Instrumentation Trace Macrocell (ITM) + \brief Type definitions for the Instrumentation Trace Macrocell (ITM) + @{ + */ + +/** + \brief Structure type to access the Instrumentation Trace Macrocell Register (ITM). + */ +typedef struct +{ + __OM union + { + __OM uint8_t u8; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 8-bit */ + __OM uint16_t u16; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 16-bit */ + __OM uint32_t u32; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 32-bit */ + } PORT [32U]; /*!< Offset: 0x000 ( /W) ITM Stimulus Port Registers */ + uint32_t RESERVED0[864U]; + __IOM uint32_t TER; /*!< Offset: 0xE00 (R/W) ITM Trace Enable Register */ + uint32_t RESERVED1[15U]; + __IOM uint32_t TPR; /*!< Offset: 0xE40 (R/W) ITM Trace Privilege Register */ + uint32_t RESERVED2[15U]; + __IOM uint32_t TCR; /*!< Offset: 0xE80 (R/W) ITM Trace Control Register */ + uint32_t RESERVED3[32U]; + uint32_t RESERVED4[43U]; + __OM uint32_t LAR; /*!< Offset: 0xFB0 ( /W) ITM Lock Access Register */ + __IM uint32_t LSR; /*!< Offset: 0xFB4 (R/ ) ITM Lock Status Register */ + uint32_t RESERVED5[1U]; + __IM uint32_t DEVARCH; /*!< Offset: 0xFBC (R/ ) ITM Device Architecture Register */ + uint32_t RESERVED6[4U]; + __IM uint32_t PID4; /*!< Offset: 0xFD0 (R/ ) ITM Peripheral Identification Register #4 */ + __IM uint32_t PID5; /*!< Offset: 0xFD4 (R/ ) ITM Peripheral Identification Register #5 */ + __IM uint32_t PID6; /*!< Offset: 0xFD8 (R/ ) ITM Peripheral Identification Register #6 */ + __IM uint32_t PID7; /*!< Offset: 0xFDC (R/ ) ITM Peripheral Identification Register #7 */ + __IM uint32_t PID0; /*!< Offset: 0xFE0 (R/ ) ITM Peripheral Identification Register #0 */ + __IM uint32_t PID1; /*!< Offset: 0xFE4 (R/ ) ITM Peripheral Identification Register #1 */ + __IM uint32_t PID2; /*!< Offset: 0xFE8 (R/ ) ITM Peripheral Identification Register #2 */ + __IM uint32_t PID3; /*!< Offset: 0xFEC (R/ ) ITM Peripheral Identification Register #3 */ + __IM uint32_t CID0; /*!< Offset: 0xFF0 (R/ ) ITM Component Identification Register #0 */ + __IM uint32_t CID1; /*!< Offset: 0xFF4 (R/ ) ITM Component Identification Register #1 */ + __IM uint32_t CID2; /*!< Offset: 0xFF8 (R/ ) ITM Component Identification Register #2 */ + __IM uint32_t CID3; /*!< Offset: 0xFFC (R/ ) ITM Component Identification Register #3 */ +} ITM_Type; + +/* ITM Stimulus Port Register Definitions */ +#define ITM_STIM_DISABLED_Pos 1U /*!< ITM STIM: DISABLED Position */ +#define ITM_STIM_DISABLED_Msk (0x1UL << ITM_STIM_DISABLED_Pos) /*!< ITM STIM: DISABLED Mask */ + +#define ITM_STIM_FIFOREADY_Pos 0U /*!< ITM STIM: FIFOREADY Position */ +#define ITM_STIM_FIFOREADY_Msk (0x1UL /*<< ITM_STIM_FIFOREADY_Pos*/) /*!< ITM STIM: FIFOREADY Mask */ + +/* ITM Trace Privilege Register Definitions */ +#define ITM_TPR_PRIVMASK_Pos 0U /*!< ITM TPR: PRIVMASK Position */ +#define ITM_TPR_PRIVMASK_Msk (0xFFFFFFFFUL /*<< ITM_TPR_PRIVMASK_Pos*/) /*!< ITM TPR: PRIVMASK Mask */ + +/* ITM Trace Control Register Definitions */ +#define ITM_TCR_BUSY_Pos 23U /*!< ITM TCR: BUSY Position */ +#define ITM_TCR_BUSY_Msk (1UL << ITM_TCR_BUSY_Pos) /*!< ITM TCR: BUSY Mask */ + +#define ITM_TCR_TRACEBUSID_Pos 16U /*!< ITM TCR: ATBID Position */ +#define ITM_TCR_TRACEBUSID_Msk (0x7FUL << ITM_TCR_TRACEBUSID_Pos) /*!< ITM TCR: ATBID Mask */ + +#define ITM_TCR_GTSFREQ_Pos 10U /*!< ITM TCR: Global timestamp frequency Position */ +#define ITM_TCR_GTSFREQ_Msk (3UL << ITM_TCR_GTSFREQ_Pos) /*!< ITM TCR: Global timestamp frequency Mask */ + +#define ITM_TCR_TSPRESCALE_Pos 8U /*!< ITM TCR: TSPRESCALE Position */ +#define ITM_TCR_TSPRESCALE_Msk (3UL << ITM_TCR_TSPRESCALE_Pos) /*!< ITM TCR: TSPRESCALE Mask */ + +#define ITM_TCR_STALLENA_Pos 5U /*!< ITM TCR: STALLENA Position */ +#define ITM_TCR_STALLENA_Msk (1UL << ITM_TCR_STALLENA_Pos) /*!< ITM TCR: STALLENA Mask */ + +#define ITM_TCR_SWOENA_Pos 4U /*!< ITM TCR: SWOENA Position */ +#define ITM_TCR_SWOENA_Msk (1UL << ITM_TCR_SWOENA_Pos) /*!< ITM TCR: SWOENA Mask */ + +#define ITM_TCR_DWTENA_Pos 3U /*!< ITM TCR: DWTENA Position */ +#define ITM_TCR_DWTENA_Msk (1UL << ITM_TCR_DWTENA_Pos) /*!< ITM TCR: DWTENA Mask */ + +#define ITM_TCR_SYNCENA_Pos 2U /*!< ITM TCR: SYNCENA Position */ +#define ITM_TCR_SYNCENA_Msk (1UL << ITM_TCR_SYNCENA_Pos) /*!< ITM TCR: SYNCENA Mask */ + +#define ITM_TCR_TSENA_Pos 1U /*!< ITM TCR: TSENA Position */ +#define ITM_TCR_TSENA_Msk (1UL << ITM_TCR_TSENA_Pos) /*!< ITM TCR: TSENA Mask */ + +#define ITM_TCR_ITMENA_Pos 0U /*!< ITM TCR: ITM Enable bit Position */ +#define ITM_TCR_ITMENA_Msk (1UL /*<< ITM_TCR_ITMENA_Pos*/) /*!< ITM TCR: ITM Enable bit Mask */ + +/* ITM Lock Status Register Definitions */ +#define ITM_LSR_ByteAcc_Pos 2U /*!< ITM LSR: ByteAcc Position */ +#define ITM_LSR_ByteAcc_Msk (1UL << ITM_LSR_ByteAcc_Pos) /*!< ITM LSR: ByteAcc Mask */ + +#define ITM_LSR_Access_Pos 1U /*!< ITM LSR: Access Position */ +#define ITM_LSR_Access_Msk (1UL << ITM_LSR_Access_Pos) /*!< ITM LSR: Access Mask */ + +#define ITM_LSR_Present_Pos 0U /*!< ITM LSR: Present Position */ +#define ITM_LSR_Present_Msk (1UL /*<< ITM_LSR_Present_Pos*/) /*!< ITM LSR: Present Mask */ + +/*@}*/ /* end of group CMSIS_ITM */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_DWT Data Watchpoint and Trace (DWT) + \brief Type definitions for the Data Watchpoint and Trace (DWT) + @{ + */ + +/** + \brief Structure type to access the Data Watchpoint and Trace Register (DWT). + */ +typedef struct +{ + __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) Control Register */ + __IOM uint32_t CYCCNT; /*!< Offset: 0x004 (R/W) Cycle Count Register */ + __IOM uint32_t CPICNT; /*!< Offset: 0x008 (R/W) CPI Count Register */ + __IOM uint32_t EXCCNT; /*!< Offset: 0x00C (R/W) Exception Overhead Count Register */ + __IOM uint32_t SLEEPCNT; /*!< Offset: 0x010 (R/W) Sleep Count Register */ + __IOM uint32_t LSUCNT; /*!< Offset: 0x014 (R/W) LSU Count Register */ + __IOM uint32_t FOLDCNT; /*!< Offset: 0x018 (R/W) Folded-instruction Count Register */ + __IM uint32_t PCSR; /*!< Offset: 0x01C (R/ ) Program Counter Sample Register */ + __IOM uint32_t COMP0; /*!< Offset: 0x020 (R/W) Comparator Register 0 */ + uint32_t RESERVED1[1U]; + __IOM uint32_t FUNCTION0; /*!< Offset: 0x028 (R/W) Function Register 0 */ + uint32_t RESERVED2[1U]; + __IOM uint32_t COMP1; /*!< Offset: 0x030 (R/W) Comparator Register 1 */ + uint32_t RESERVED3[1U]; + __IOM uint32_t FUNCTION1; /*!< Offset: 0x038 (R/W) Function Register 1 */ + uint32_t RESERVED4[1U]; + __IOM uint32_t COMP2; /*!< Offset: 0x040 (R/W) Comparator Register 2 */ + uint32_t RESERVED5[1U]; + __IOM uint32_t FUNCTION2; /*!< Offset: 0x048 (R/W) Function Register 2 */ + uint32_t RESERVED6[1U]; + __IOM uint32_t COMP3; /*!< Offset: 0x050 (R/W) Comparator Register 3 */ + uint32_t RESERVED7[1U]; + __IOM uint32_t FUNCTION3; /*!< Offset: 0x058 (R/W) Function Register 3 */ + uint32_t RESERVED8[1U]; + __IOM uint32_t COMP4; /*!< Offset: 0x060 (R/W) Comparator Register 4 */ + uint32_t RESERVED9[1U]; + __IOM uint32_t FUNCTION4; /*!< Offset: 0x068 (R/W) Function Register 4 */ + uint32_t RESERVED10[1U]; + __IOM uint32_t COMP5; /*!< Offset: 0x070 (R/W) Comparator Register 5 */ + uint32_t RESERVED11[1U]; + __IOM uint32_t FUNCTION5; /*!< Offset: 0x078 (R/W) Function Register 5 */ + uint32_t RESERVED12[1U]; + __IOM uint32_t COMP6; /*!< Offset: 0x080 (R/W) Comparator Register 6 */ + uint32_t RESERVED13[1U]; + __IOM uint32_t FUNCTION6; /*!< Offset: 0x088 (R/W) Function Register 6 */ + uint32_t RESERVED14[1U]; + __IOM uint32_t COMP7; /*!< Offset: 0x090 (R/W) Comparator Register 7 */ + uint32_t RESERVED15[1U]; + __IOM uint32_t FUNCTION7; /*!< Offset: 0x098 (R/W) Function Register 7 */ + uint32_t RESERVED16[1U]; + __IOM uint32_t COMP8; /*!< Offset: 0x0A0 (R/W) Comparator Register 8 */ + uint32_t RESERVED17[1U]; + __IOM uint32_t FUNCTION8; /*!< Offset: 0x0A8 (R/W) Function Register 8 */ + uint32_t RESERVED18[1U]; + __IOM uint32_t COMP9; /*!< Offset: 0x0B0 (R/W) Comparator Register 9 */ + uint32_t RESERVED19[1U]; + __IOM uint32_t FUNCTION9; /*!< Offset: 0x0B8 (R/W) Function Register 9 */ + uint32_t RESERVED20[1U]; + __IOM uint32_t COMP10; /*!< Offset: 0x0C0 (R/W) Comparator Register 10 */ + uint32_t RESERVED21[1U]; + __IOM uint32_t FUNCTION10; /*!< Offset: 0x0C8 (R/W) Function Register 10 */ + uint32_t RESERVED22[1U]; + __IOM uint32_t COMP11; /*!< Offset: 0x0D0 (R/W) Comparator Register 11 */ + uint32_t RESERVED23[1U]; + __IOM uint32_t FUNCTION11; /*!< Offset: 0x0D8 (R/W) Function Register 11 */ + uint32_t RESERVED24[1U]; + __IOM uint32_t COMP12; /*!< Offset: 0x0E0 (R/W) Comparator Register 12 */ + uint32_t RESERVED25[1U]; + __IOM uint32_t FUNCTION12; /*!< Offset: 0x0E8 (R/W) Function Register 12 */ + uint32_t RESERVED26[1U]; + __IOM uint32_t COMP13; /*!< Offset: 0x0F0 (R/W) Comparator Register 13 */ + uint32_t RESERVED27[1U]; + __IOM uint32_t FUNCTION13; /*!< Offset: 0x0F8 (R/W) Function Register 13 */ + uint32_t RESERVED28[1U]; + __IOM uint32_t COMP14; /*!< Offset: 0x100 (R/W) Comparator Register 14 */ + uint32_t RESERVED29[1U]; + __IOM uint32_t FUNCTION14; /*!< Offset: 0x108 (R/W) Function Register 14 */ + uint32_t RESERVED30[1U]; + __IOM uint32_t COMP15; /*!< Offset: 0x110 (R/W) Comparator Register 15 */ + uint32_t RESERVED31[1U]; + __IOM uint32_t FUNCTION15; /*!< Offset: 0x118 (R/W) Function Register 15 */ + uint32_t RESERVED32[934U]; + __IM uint32_t LSR; /*!< Offset: 0xFB4 (R ) Lock Status Register */ + uint32_t RESERVED33[1U]; + __IM uint32_t DEVARCH; /*!< Offset: 0xFBC (R/ ) Device Architecture Register */ +} DWT_Type; + +/* DWT Control Register Definitions */ +#define DWT_CTRL_NUMCOMP_Pos 28U /*!< DWT CTRL: NUMCOMP Position */ +#define DWT_CTRL_NUMCOMP_Msk (0xFUL << DWT_CTRL_NUMCOMP_Pos) /*!< DWT CTRL: NUMCOMP Mask */ + +#define DWT_CTRL_NOTRCPKT_Pos 27U /*!< DWT CTRL: NOTRCPKT Position */ +#define DWT_CTRL_NOTRCPKT_Msk (0x1UL << DWT_CTRL_NOTRCPKT_Pos) /*!< DWT CTRL: NOTRCPKT Mask */ + +#define DWT_CTRL_NOEXTTRIG_Pos 26U /*!< DWT CTRL: NOEXTTRIG Position */ +#define DWT_CTRL_NOEXTTRIG_Msk (0x1UL << DWT_CTRL_NOEXTTRIG_Pos) /*!< DWT CTRL: NOEXTTRIG Mask */ + +#define DWT_CTRL_NOCYCCNT_Pos 25U /*!< DWT CTRL: NOCYCCNT Position */ +#define DWT_CTRL_NOCYCCNT_Msk (0x1UL << DWT_CTRL_NOCYCCNT_Pos) /*!< DWT CTRL: NOCYCCNT Mask */ + +#define DWT_CTRL_NOPRFCNT_Pos 24U /*!< DWT CTRL: NOPRFCNT Position */ +#define DWT_CTRL_NOPRFCNT_Msk (0x1UL << DWT_CTRL_NOPRFCNT_Pos) /*!< DWT CTRL: NOPRFCNT Mask */ + +#define DWT_CTRL_CYCDISS_Pos 23U /*!< DWT CTRL: CYCDISS Position */ +#define DWT_CTRL_CYCDISS_Msk (0x1UL << DWT_CTRL_CYCDISS_Pos) /*!< DWT CTRL: CYCDISS Mask */ + +#define DWT_CTRL_CYCEVTENA_Pos 22U /*!< DWT CTRL: CYCEVTENA Position */ +#define DWT_CTRL_CYCEVTENA_Msk (0x1UL << DWT_CTRL_CYCEVTENA_Pos) /*!< DWT CTRL: CYCEVTENA Mask */ + +#define DWT_CTRL_FOLDEVTENA_Pos 21U /*!< DWT CTRL: FOLDEVTENA Position */ +#define DWT_CTRL_FOLDEVTENA_Msk (0x1UL << DWT_CTRL_FOLDEVTENA_Pos) /*!< DWT CTRL: FOLDEVTENA Mask */ + +#define DWT_CTRL_LSUEVTENA_Pos 20U /*!< DWT CTRL: LSUEVTENA Position */ +#define DWT_CTRL_LSUEVTENA_Msk (0x1UL << DWT_CTRL_LSUEVTENA_Pos) /*!< DWT CTRL: LSUEVTENA Mask */ + +#define DWT_CTRL_SLEEPEVTENA_Pos 19U /*!< DWT CTRL: SLEEPEVTENA Position */ +#define DWT_CTRL_SLEEPEVTENA_Msk (0x1UL << DWT_CTRL_SLEEPEVTENA_Pos) /*!< DWT CTRL: SLEEPEVTENA Mask */ + +#define DWT_CTRL_EXCEVTENA_Pos 18U /*!< DWT CTRL: EXCEVTENA Position */ +#define DWT_CTRL_EXCEVTENA_Msk (0x1UL << DWT_CTRL_EXCEVTENA_Pos) /*!< DWT CTRL: EXCEVTENA Mask */ + +#define DWT_CTRL_CPIEVTENA_Pos 17U /*!< DWT CTRL: CPIEVTENA Position */ +#define DWT_CTRL_CPIEVTENA_Msk (0x1UL << DWT_CTRL_CPIEVTENA_Pos) /*!< DWT CTRL: CPIEVTENA Mask */ + +#define DWT_CTRL_EXCTRCENA_Pos 16U /*!< DWT CTRL: EXCTRCENA Position */ +#define DWT_CTRL_EXCTRCENA_Msk (0x1UL << DWT_CTRL_EXCTRCENA_Pos) /*!< DWT CTRL: EXCTRCENA Mask */ + +#define DWT_CTRL_PCSAMPLENA_Pos 12U /*!< DWT CTRL: PCSAMPLENA Position */ +#define DWT_CTRL_PCSAMPLENA_Msk (0x1UL << DWT_CTRL_PCSAMPLENA_Pos) /*!< DWT CTRL: PCSAMPLENA Mask */ + +#define DWT_CTRL_SYNCTAP_Pos 10U /*!< DWT CTRL: SYNCTAP Position */ +#define DWT_CTRL_SYNCTAP_Msk (0x3UL << DWT_CTRL_SYNCTAP_Pos) /*!< DWT CTRL: SYNCTAP Mask */ + +#define DWT_CTRL_CYCTAP_Pos 9U /*!< DWT CTRL: CYCTAP Position */ +#define DWT_CTRL_CYCTAP_Msk (0x1UL << DWT_CTRL_CYCTAP_Pos) /*!< DWT CTRL: CYCTAP Mask */ + +#define DWT_CTRL_POSTINIT_Pos 5U /*!< DWT CTRL: POSTINIT Position */ +#define DWT_CTRL_POSTINIT_Msk (0xFUL << DWT_CTRL_POSTINIT_Pos) /*!< DWT CTRL: POSTINIT Mask */ + +#define DWT_CTRL_POSTPRESET_Pos 1U /*!< DWT CTRL: POSTPRESET Position */ +#define DWT_CTRL_POSTPRESET_Msk (0xFUL << DWT_CTRL_POSTPRESET_Pos) /*!< DWT CTRL: POSTPRESET Mask */ + +#define DWT_CTRL_CYCCNTENA_Pos 0U /*!< DWT CTRL: CYCCNTENA Position */ +#define DWT_CTRL_CYCCNTENA_Msk (0x1UL /*<< DWT_CTRL_CYCCNTENA_Pos*/) /*!< DWT CTRL: CYCCNTENA Mask */ + +/* DWT CPI Count Register Definitions */ +#define DWT_CPICNT_CPICNT_Pos 0U /*!< DWT CPICNT: CPICNT Position */ +#define DWT_CPICNT_CPICNT_Msk (0xFFUL /*<< DWT_CPICNT_CPICNT_Pos*/) /*!< DWT CPICNT: CPICNT Mask */ + +/* DWT Exception Overhead Count Register Definitions */ +#define DWT_EXCCNT_EXCCNT_Pos 0U /*!< DWT EXCCNT: EXCCNT Position */ +#define DWT_EXCCNT_EXCCNT_Msk (0xFFUL /*<< DWT_EXCCNT_EXCCNT_Pos*/) /*!< DWT EXCCNT: EXCCNT Mask */ + +/* DWT Sleep Count Register Definitions */ +#define DWT_SLEEPCNT_SLEEPCNT_Pos 0U /*!< DWT SLEEPCNT: SLEEPCNT Position */ +#define DWT_SLEEPCNT_SLEEPCNT_Msk (0xFFUL /*<< DWT_SLEEPCNT_SLEEPCNT_Pos*/) /*!< DWT SLEEPCNT: SLEEPCNT Mask */ + +/* DWT LSU Count Register Definitions */ +#define DWT_LSUCNT_LSUCNT_Pos 0U /*!< DWT LSUCNT: LSUCNT Position */ +#define DWT_LSUCNT_LSUCNT_Msk (0xFFUL /*<< DWT_LSUCNT_LSUCNT_Pos*/) /*!< DWT LSUCNT: LSUCNT Mask */ + +/* DWT Folded-instruction Count Register Definitions */ +#define DWT_FOLDCNT_FOLDCNT_Pos 0U /*!< DWT FOLDCNT: FOLDCNT Position */ +#define DWT_FOLDCNT_FOLDCNT_Msk (0xFFUL /*<< DWT_FOLDCNT_FOLDCNT_Pos*/) /*!< DWT FOLDCNT: FOLDCNT Mask */ + +/* DWT Comparator Function Register Definitions */ +#define DWT_FUNCTION_ID_Pos 27U /*!< DWT FUNCTION: ID Position */ +#define DWT_FUNCTION_ID_Msk (0x1FUL << DWT_FUNCTION_ID_Pos) /*!< DWT FUNCTION: ID Mask */ + +#define DWT_FUNCTION_MATCHED_Pos 24U /*!< DWT FUNCTION: MATCHED Position */ +#define DWT_FUNCTION_MATCHED_Msk (0x1UL << DWT_FUNCTION_MATCHED_Pos) /*!< DWT FUNCTION: MATCHED Mask */ + +#define DWT_FUNCTION_DATAVSIZE_Pos 10U /*!< DWT FUNCTION: DATAVSIZE Position */ +#define DWT_FUNCTION_DATAVSIZE_Msk (0x3UL << DWT_FUNCTION_DATAVSIZE_Pos) /*!< DWT FUNCTION: DATAVSIZE Mask */ + +#define DWT_FUNCTION_ACTION_Pos 4U /*!< DWT FUNCTION: ACTION Position */ +#define DWT_FUNCTION_ACTION_Msk (0x1UL << DWT_FUNCTION_ACTION_Pos) /*!< DWT FUNCTION: ACTION Mask */ + +#define DWT_FUNCTION_MATCH_Pos 0U /*!< DWT FUNCTION: MATCH Position */ +#define DWT_FUNCTION_MATCH_Msk (0xFUL /*<< DWT_FUNCTION_MATCH_Pos*/) /*!< DWT FUNCTION: MATCH Mask */ + +/*@}*/ /* end of group CMSIS_DWT */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_TPI Trace Port Interface (TPI) + \brief Type definitions for the Trace Port Interface (TPI) + @{ + */ + +/** + \brief Structure type to access the Trace Port Interface Register (TPI). + */ +typedef struct +{ + __IM uint32_t SSPSR; /*!< Offset: 0x000 (R/ ) Supported Parallel Port Size Register */ + __IOM uint32_t CSPSR; /*!< Offset: 0x004 (R/W) Current Parallel Port Size Register */ + uint32_t RESERVED0[2U]; + __IOM uint32_t ACPR; /*!< Offset: 0x010 (R/W) Asynchronous Clock Prescaler Register */ + uint32_t RESERVED1[55U]; + __IOM uint32_t SPPR; /*!< Offset: 0x0F0 (R/W) Selected Pin Protocol Register */ + uint32_t RESERVED2[131U]; + __IM uint32_t FFSR; /*!< Offset: 0x300 (R/ ) Formatter and Flush Status Register */ + __IOM uint32_t FFCR; /*!< Offset: 0x304 (R/W) Formatter and Flush Control Register */ + __IOM uint32_t PSCR; /*!< Offset: 0x308 (R/W) Periodic Synchronization Control Register */ + uint32_t RESERVED3[759U]; + __IM uint32_t TRIGGER; /*!< Offset: 0xEE8 (R/ ) TRIGGER Register */ + __IM uint32_t ITFTTD0; /*!< Offset: 0xEEC (R/ ) Integration Test FIFO Test Data 0 Register */ + __IOM uint32_t ITATBCTR2; /*!< Offset: 0xEF0 (R/W) Integration Test ATB Control Register 2 */ + uint32_t RESERVED4[1U]; + __IM uint32_t ITATBCTR0; /*!< Offset: 0xEF8 (R/ ) Integration Test ATB Control Register 0 */ + __IM uint32_t ITFTTD1; /*!< Offset: 0xEFC (R/ ) Integration Test FIFO Test Data 1 Register */ + __IOM uint32_t ITCTRL; /*!< Offset: 0xF00 (R/W) Integration Mode Control */ + uint32_t RESERVED5[39U]; + __IOM uint32_t CLAIMSET; /*!< Offset: 0xFA0 (R/W) Claim tag set */ + __IOM uint32_t CLAIMCLR; /*!< Offset: 0xFA4 (R/W) Claim tag clear */ + uint32_t RESERVED7[8U]; + __IM uint32_t DEVID; /*!< Offset: 0xFC8 (R/ ) Device Configuration Register */ + __IM uint32_t DEVTYPE; /*!< Offset: 0xFCC (R/ ) Device Type Identifier Register */ +} TPI_Type; + +/* TPI Asynchronous Clock Prescaler Register Definitions */ +#define TPI_ACPR_PRESCALER_Pos 0U /*!< TPI ACPR: PRESCALER Position */ +#define TPI_ACPR_PRESCALER_Msk (0x1FFFUL /*<< TPI_ACPR_PRESCALER_Pos*/) /*!< TPI ACPR: PRESCALER Mask */ + +/* TPI Selected Pin Protocol Register Definitions */ +#define TPI_SPPR_TXMODE_Pos 0U /*!< TPI SPPR: TXMODE Position */ +#define TPI_SPPR_TXMODE_Msk (0x3UL /*<< TPI_SPPR_TXMODE_Pos*/) /*!< TPI SPPR: TXMODE Mask */ + +/* TPI Formatter and Flush Status Register Definitions */ +#define TPI_FFSR_FtNonStop_Pos 3U /*!< TPI FFSR: FtNonStop Position */ +#define TPI_FFSR_FtNonStop_Msk (0x1UL << TPI_FFSR_FtNonStop_Pos) /*!< TPI FFSR: FtNonStop Mask */ + +#define TPI_FFSR_TCPresent_Pos 2U /*!< TPI FFSR: TCPresent Position */ +#define TPI_FFSR_TCPresent_Msk (0x1UL << TPI_FFSR_TCPresent_Pos) /*!< TPI FFSR: TCPresent Mask */ + +#define TPI_FFSR_FtStopped_Pos 1U /*!< TPI FFSR: FtStopped Position */ +#define TPI_FFSR_FtStopped_Msk (0x1UL << TPI_FFSR_FtStopped_Pos) /*!< TPI FFSR: FtStopped Mask */ + +#define TPI_FFSR_FlInProg_Pos 0U /*!< TPI FFSR: FlInProg Position */ +#define TPI_FFSR_FlInProg_Msk (0x1UL /*<< TPI_FFSR_FlInProg_Pos*/) /*!< TPI FFSR: FlInProg Mask */ + +/* TPI Formatter and Flush Control Register Definitions */ +#define TPI_FFCR_TrigIn_Pos 8U /*!< TPI FFCR: TrigIn Position */ +#define TPI_FFCR_TrigIn_Msk (0x1UL << TPI_FFCR_TrigIn_Pos) /*!< TPI FFCR: TrigIn Mask */ + +#define TPI_FFCR_FOnMan_Pos 6U /*!< TPI FFCR: FOnMan Position */ +#define TPI_FFCR_FOnMan_Msk (0x1UL << TPI_FFCR_FOnMan_Pos) /*!< TPI FFCR: FOnMan Mask */ + +#define TPI_FFCR_EnFCont_Pos 1U /*!< TPI FFCR: EnFCont Position */ +#define TPI_FFCR_EnFCont_Msk (0x1UL << TPI_FFCR_EnFCont_Pos) /*!< TPI FFCR: EnFCont Mask */ + +/* TPI TRIGGER Register Definitions */ +#define TPI_TRIGGER_TRIGGER_Pos 0U /*!< TPI TRIGGER: TRIGGER Position */ +#define TPI_TRIGGER_TRIGGER_Msk (0x1UL /*<< TPI_TRIGGER_TRIGGER_Pos*/) /*!< TPI TRIGGER: TRIGGER Mask */ + +/* TPI Integration Test FIFO Test Data 0 Register Definitions */ +#define TPI_ITFTTD0_ATB_IF2_ATVALID_Pos 29U /*!< TPI ITFTTD0: ATB Interface 2 ATVALIDPosition */ +#define TPI_ITFTTD0_ATB_IF2_ATVALID_Msk (0x3UL << TPI_ITFTTD0_ATB_IF2_ATVALID_Pos) /*!< TPI ITFTTD0: ATB Interface 2 ATVALID Mask */ + +#define TPI_ITFTTD0_ATB_IF2_bytecount_Pos 27U /*!< TPI ITFTTD0: ATB Interface 2 byte count Position */ +#define TPI_ITFTTD0_ATB_IF2_bytecount_Msk (0x3UL << TPI_ITFTTD0_ATB_IF2_bytecount_Pos) /*!< TPI ITFTTD0: ATB Interface 2 byte count Mask */ + +#define TPI_ITFTTD0_ATB_IF1_ATVALID_Pos 26U /*!< TPI ITFTTD0: ATB Interface 1 ATVALID Position */ +#define TPI_ITFTTD0_ATB_IF1_ATVALID_Msk (0x3UL << TPI_ITFTTD0_ATB_IF1_ATVALID_Pos) /*!< TPI ITFTTD0: ATB Interface 1 ATVALID Mask */ + +#define TPI_ITFTTD0_ATB_IF1_bytecount_Pos 24U /*!< TPI ITFTTD0: ATB Interface 1 byte count Position */ +#define TPI_ITFTTD0_ATB_IF1_bytecount_Msk (0x3UL << TPI_ITFTTD0_ATB_IF1_bytecount_Pos) /*!< TPI ITFTTD0: ATB Interface 1 byte countt Mask */ + +#define TPI_ITFTTD0_ATB_IF1_data2_Pos 16U /*!< TPI ITFTTD0: ATB Interface 1 data2 Position */ +#define TPI_ITFTTD0_ATB_IF1_data2_Msk (0xFFUL << TPI_ITFTTD0_ATB_IF1_data1_Pos) /*!< TPI ITFTTD0: ATB Interface 1 data2 Mask */ + +#define TPI_ITFTTD0_ATB_IF1_data1_Pos 8U /*!< TPI ITFTTD0: ATB Interface 1 data1 Position */ +#define TPI_ITFTTD0_ATB_IF1_data1_Msk (0xFFUL << TPI_ITFTTD0_ATB_IF1_data1_Pos) /*!< TPI ITFTTD0: ATB Interface 1 data1 Mask */ + +#define TPI_ITFTTD0_ATB_IF1_data0_Pos 0U /*!< TPI ITFTTD0: ATB Interface 1 data0 Position */ +#define TPI_ITFTTD0_ATB_IF1_data0_Msk (0xFFUL /*<< TPI_ITFTTD0_ATB_IF1_data0_Pos*/) /*!< TPI ITFTTD0: ATB Interface 1 data0 Mask */ + +/* TPI Integration Test ATB Control Register 2 Register Definitions */ +#define TPI_ITATBCTR2_AFVALID2S_Pos 1U /*!< TPI ITATBCTR2: AFVALID2S Position */ +#define TPI_ITATBCTR2_AFVALID2S_Msk (0x1UL << TPI_ITATBCTR2_AFVALID2S_Pos) /*!< TPI ITATBCTR2: AFVALID2SS Mask */ + +#define TPI_ITATBCTR2_AFVALID1S_Pos 1U /*!< TPI ITATBCTR2: AFVALID1S Position */ +#define TPI_ITATBCTR2_AFVALID1S_Msk (0x1UL << TPI_ITATBCTR2_AFVALID1S_Pos) /*!< TPI ITATBCTR2: AFVALID1SS Mask */ + +#define TPI_ITATBCTR2_ATREADY2S_Pos 0U /*!< TPI ITATBCTR2: ATREADY2S Position */ +#define TPI_ITATBCTR2_ATREADY2S_Msk (0x1UL /*<< TPI_ITATBCTR2_ATREADY2S_Pos*/) /*!< TPI ITATBCTR2: ATREADY2S Mask */ + +#define TPI_ITATBCTR2_ATREADY1S_Pos 0U /*!< TPI ITATBCTR2: ATREADY1S Position */ +#define TPI_ITATBCTR2_ATREADY1S_Msk (0x1UL /*<< TPI_ITATBCTR2_ATREADY1S_Pos*/) /*!< TPI ITATBCTR2: ATREADY1S Mask */ + +/* TPI Integration Test FIFO Test Data 1 Register Definitions */ +#define TPI_ITFTTD1_ATB_IF2_ATVALID_Pos 29U /*!< TPI ITFTTD1: ATB Interface 2 ATVALID Position */ +#define TPI_ITFTTD1_ATB_IF2_ATVALID_Msk (0x3UL << TPI_ITFTTD1_ATB_IF2_ATVALID_Pos) /*!< TPI ITFTTD1: ATB Interface 2 ATVALID Mask */ + +#define TPI_ITFTTD1_ATB_IF2_bytecount_Pos 27U /*!< TPI ITFTTD1: ATB Interface 2 byte count Position */ +#define TPI_ITFTTD1_ATB_IF2_bytecount_Msk (0x3UL << TPI_ITFTTD1_ATB_IF2_bytecount_Pos) /*!< TPI ITFTTD1: ATB Interface 2 byte count Mask */ + +#define TPI_ITFTTD1_ATB_IF1_ATVALID_Pos 26U /*!< TPI ITFTTD1: ATB Interface 1 ATVALID Position */ +#define TPI_ITFTTD1_ATB_IF1_ATVALID_Msk (0x3UL << TPI_ITFTTD1_ATB_IF1_ATVALID_Pos) /*!< TPI ITFTTD1: ATB Interface 1 ATVALID Mask */ + +#define TPI_ITFTTD1_ATB_IF1_bytecount_Pos 24U /*!< TPI ITFTTD1: ATB Interface 1 byte count Position */ +#define TPI_ITFTTD1_ATB_IF1_bytecount_Msk (0x3UL << TPI_ITFTTD1_ATB_IF1_bytecount_Pos) /*!< TPI ITFTTD1: ATB Interface 1 byte countt Mask */ + +#define TPI_ITFTTD1_ATB_IF2_data2_Pos 16U /*!< TPI ITFTTD1: ATB Interface 2 data2 Position */ +#define TPI_ITFTTD1_ATB_IF2_data2_Msk (0xFFUL << TPI_ITFTTD1_ATB_IF2_data1_Pos) /*!< TPI ITFTTD1: ATB Interface 2 data2 Mask */ + +#define TPI_ITFTTD1_ATB_IF2_data1_Pos 8U /*!< TPI ITFTTD1: ATB Interface 2 data1 Position */ +#define TPI_ITFTTD1_ATB_IF2_data1_Msk (0xFFUL << TPI_ITFTTD1_ATB_IF2_data1_Pos) /*!< TPI ITFTTD1: ATB Interface 2 data1 Mask */ + +#define TPI_ITFTTD1_ATB_IF2_data0_Pos 0U /*!< TPI ITFTTD1: ATB Interface 2 data0 Position */ +#define TPI_ITFTTD1_ATB_IF2_data0_Msk (0xFFUL /*<< TPI_ITFTTD1_ATB_IF2_data0_Pos*/) /*!< TPI ITFTTD1: ATB Interface 2 data0 Mask */ + +/* TPI Integration Test ATB Control Register 0 Definitions */ +#define TPI_ITATBCTR0_AFVALID2S_Pos 1U /*!< TPI ITATBCTR0: AFVALID2S Position */ +#define TPI_ITATBCTR0_AFVALID2S_Msk (0x1UL << TPI_ITATBCTR0_AFVALID2S_Pos) /*!< TPI ITATBCTR0: AFVALID2SS Mask */ + +#define TPI_ITATBCTR0_AFVALID1S_Pos 1U /*!< TPI ITATBCTR0: AFVALID1S Position */ +#define TPI_ITATBCTR0_AFVALID1S_Msk (0x1UL << TPI_ITATBCTR0_AFVALID1S_Pos) /*!< TPI ITATBCTR0: AFVALID1SS Mask */ + +#define TPI_ITATBCTR0_ATREADY2S_Pos 0U /*!< TPI ITATBCTR0: ATREADY2S Position */ +#define TPI_ITATBCTR0_ATREADY2S_Msk (0x1UL /*<< TPI_ITATBCTR0_ATREADY2S_Pos*/) /*!< TPI ITATBCTR0: ATREADY2S Mask */ + +#define TPI_ITATBCTR0_ATREADY1S_Pos 0U /*!< TPI ITATBCTR0: ATREADY1S Position */ +#define TPI_ITATBCTR0_ATREADY1S_Msk (0x1UL /*<< TPI_ITATBCTR0_ATREADY1S_Pos*/) /*!< TPI ITATBCTR0: ATREADY1S Mask */ + +/* TPI Integration Mode Control Register Definitions */ +#define TPI_ITCTRL_Mode_Pos 0U /*!< TPI ITCTRL: Mode Position */ +#define TPI_ITCTRL_Mode_Msk (0x3UL /*<< TPI_ITCTRL_Mode_Pos*/) /*!< TPI ITCTRL: Mode Mask */ + +/* TPI DEVID Register Definitions */ +#define TPI_DEVID_NRZVALID_Pos 11U /*!< TPI DEVID: NRZVALID Position */ +#define TPI_DEVID_NRZVALID_Msk (0x1UL << TPI_DEVID_NRZVALID_Pos) /*!< TPI DEVID: NRZVALID Mask */ + +#define TPI_DEVID_MANCVALID_Pos 10U /*!< TPI DEVID: MANCVALID Position */ +#define TPI_DEVID_MANCVALID_Msk (0x1UL << TPI_DEVID_MANCVALID_Pos) /*!< TPI DEVID: MANCVALID Mask */ + +#define TPI_DEVID_PTINVALID_Pos 9U /*!< TPI DEVID: PTINVALID Position */ +#define TPI_DEVID_PTINVALID_Msk (0x1UL << TPI_DEVID_PTINVALID_Pos) /*!< TPI DEVID: PTINVALID Mask */ + +#define TPI_DEVID_FIFOSZ_Pos 6U /*!< TPI DEVID: FIFOSZ Position */ +#define TPI_DEVID_FIFOSZ_Msk (0x7UL << TPI_DEVID_FIFOSZ_Pos) /*!< TPI DEVID: FIFOSZ Mask */ + +#define TPI_DEVID_NrTraceInput_Pos 0U /*!< TPI DEVID: NrTraceInput Position */ +#define TPI_DEVID_NrTraceInput_Msk (0x3FUL /*<< TPI_DEVID_NrTraceInput_Pos*/) /*!< TPI DEVID: NrTraceInput Mask */ + +/* TPI DEVTYPE Register Definitions */ +#define TPI_DEVTYPE_SubType_Pos 4U /*!< TPI DEVTYPE: SubType Position */ +#define TPI_DEVTYPE_SubType_Msk (0xFUL /*<< TPI_DEVTYPE_SubType_Pos*/) /*!< TPI DEVTYPE: SubType Mask */ + +#define TPI_DEVTYPE_MajorType_Pos 0U /*!< TPI DEVTYPE: MajorType Position */ +#define TPI_DEVTYPE_MajorType_Msk (0xFUL << TPI_DEVTYPE_MajorType_Pos) /*!< TPI DEVTYPE: MajorType Mask */ + +/*@}*/ /* end of group CMSIS_TPI */ + + +#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_MPU Memory Protection Unit (MPU) + \brief Type definitions for the Memory Protection Unit (MPU) + @{ + */ + +/** + \brief Structure type to access the Memory Protection Unit (MPU). + */ +typedef struct +{ + __IM uint32_t TYPE; /*!< Offset: 0x000 (R/ ) MPU Type Register */ + __IOM uint32_t CTRL; /*!< Offset: 0x004 (R/W) MPU Control Register */ + __IOM uint32_t RNR; /*!< Offset: 0x008 (R/W) MPU Region Number Register */ + __IOM uint32_t RBAR; /*!< Offset: 0x00C (R/W) MPU Region Base Address Register */ + __IOM uint32_t RLAR; /*!< Offset: 0x010 (R/W) MPU Region Limit Address Register */ + __IOM uint32_t RBAR_A1; /*!< Offset: 0x014 (R/W) MPU Region Base Address Register Alias 1 */ + __IOM uint32_t RLAR_A1; /*!< Offset: 0x018 (R/W) MPU Region Limit Address Register Alias 1 */ + __IOM uint32_t RBAR_A2; /*!< Offset: 0x01C (R/W) MPU Region Base Address Register Alias 2 */ + __IOM uint32_t RLAR_A2; /*!< Offset: 0x020 (R/W) MPU Region Limit Address Register Alias 2 */ + __IOM uint32_t RBAR_A3; /*!< Offset: 0x024 (R/W) MPU Region Base Address Register Alias 3 */ + __IOM uint32_t RLAR_A3; /*!< Offset: 0x028 (R/W) MPU Region Limit Address Register Alias 3 */ + uint32_t RESERVED0[1]; + union { + __IOM uint32_t MAIR[2]; + struct { + __IOM uint32_t MAIR0; /*!< Offset: 0x030 (R/W) MPU Memory Attribute Indirection Register 0 */ + __IOM uint32_t MAIR1; /*!< Offset: 0x034 (R/W) MPU Memory Attribute Indirection Register 1 */ + }; + }; +} MPU_Type; + +#define MPU_TYPE_RALIASES 4U + +/* MPU Type Register Definitions */ +#define MPU_TYPE_IREGION_Pos 16U /*!< MPU TYPE: IREGION Position */ +#define MPU_TYPE_IREGION_Msk (0xFFUL << MPU_TYPE_IREGION_Pos) /*!< MPU TYPE: IREGION Mask */ + +#define MPU_TYPE_DREGION_Pos 8U /*!< MPU TYPE: DREGION Position */ +#define MPU_TYPE_DREGION_Msk (0xFFUL << MPU_TYPE_DREGION_Pos) /*!< MPU TYPE: DREGION Mask */ + +#define MPU_TYPE_SEPARATE_Pos 0U /*!< MPU TYPE: SEPARATE Position */ +#define MPU_TYPE_SEPARATE_Msk (1UL /*<< MPU_TYPE_SEPARATE_Pos*/) /*!< MPU TYPE: SEPARATE Mask */ + +/* MPU Control Register Definitions */ +#define MPU_CTRL_PRIVDEFENA_Pos 2U /*!< MPU CTRL: PRIVDEFENA Position */ +#define MPU_CTRL_PRIVDEFENA_Msk (1UL << MPU_CTRL_PRIVDEFENA_Pos) /*!< MPU CTRL: PRIVDEFENA Mask */ + +#define MPU_CTRL_HFNMIENA_Pos 1U /*!< MPU CTRL: HFNMIENA Position */ +#define MPU_CTRL_HFNMIENA_Msk (1UL << MPU_CTRL_HFNMIENA_Pos) /*!< MPU CTRL: HFNMIENA Mask */ + +#define MPU_CTRL_ENABLE_Pos 0U /*!< MPU CTRL: ENABLE Position */ +#define MPU_CTRL_ENABLE_Msk (1UL /*<< MPU_CTRL_ENABLE_Pos*/) /*!< MPU CTRL: ENABLE Mask */ + +/* MPU Region Number Register Definitions */ +#define MPU_RNR_REGION_Pos 0U /*!< MPU RNR: REGION Position */ +#define MPU_RNR_REGION_Msk (0xFFUL /*<< MPU_RNR_REGION_Pos*/) /*!< MPU RNR: REGION Mask */ + +/* MPU Region Base Address Register Definitions */ +#define MPU_RBAR_BASE_Pos 5U /*!< MPU RBAR: BASE Position */ +#define MPU_RBAR_BASE_Msk (0x7FFFFFFUL << MPU_RBAR_BASE_Pos) /*!< MPU RBAR: BASE Mask */ + +#define MPU_RBAR_SH_Pos 3U /*!< MPU RBAR: SH Position */ +#define MPU_RBAR_SH_Msk (0x3UL << MPU_RBAR_SH_Pos) /*!< MPU RBAR: SH Mask */ + +#define MPU_RBAR_AP_Pos 1U /*!< MPU RBAR: AP Position */ +#define MPU_RBAR_AP_Msk (0x3UL << MPU_RBAR_AP_Pos) /*!< MPU RBAR: AP Mask */ + +#define MPU_RBAR_XN_Pos 0U /*!< MPU RBAR: XN Position */ +#define MPU_RBAR_XN_Msk (01UL /*<< MPU_RBAR_XN_Pos*/) /*!< MPU RBAR: XN Mask */ + +/* MPU Region Limit Address Register Definitions */ +#define MPU_RLAR_LIMIT_Pos 5U /*!< MPU RLAR: LIMIT Position */ +#define MPU_RLAR_LIMIT_Msk (0x7FFFFFFUL << MPU_RLAR_LIMIT_Pos) /*!< MPU RLAR: LIMIT Mask */ + +#define MPU_RLAR_AttrIndx_Pos 1U /*!< MPU RLAR: AttrIndx Position */ +#define MPU_RLAR_AttrIndx_Msk (0x7UL << MPU_RLAR_AttrIndx_Pos) /*!< MPU RLAR: AttrIndx Mask */ + +#define MPU_RLAR_EN_Pos 0U /*!< MPU RLAR: Region enable bit Position */ +#define MPU_RLAR_EN_Msk (1UL /*<< MPU_RLAR_EN_Pos*/) /*!< MPU RLAR: Region enable bit Disable Mask */ + +/* MPU Memory Attribute Indirection Register 0 Definitions */ +#define MPU_MAIR0_Attr3_Pos 24U /*!< MPU MAIR0: Attr3 Position */ +#define MPU_MAIR0_Attr3_Msk (0xFFUL << MPU_MAIR0_Attr3_Pos) /*!< MPU MAIR0: Attr3 Mask */ + +#define MPU_MAIR0_Attr2_Pos 16U /*!< MPU MAIR0: Attr2 Position */ +#define MPU_MAIR0_Attr2_Msk (0xFFUL << MPU_MAIR0_Attr2_Pos) /*!< MPU MAIR0: Attr2 Mask */ + +#define MPU_MAIR0_Attr1_Pos 8U /*!< MPU MAIR0: Attr1 Position */ +#define MPU_MAIR0_Attr1_Msk (0xFFUL << MPU_MAIR0_Attr1_Pos) /*!< MPU MAIR0: Attr1 Mask */ + +#define MPU_MAIR0_Attr0_Pos 0U /*!< MPU MAIR0: Attr0 Position */ +#define MPU_MAIR0_Attr0_Msk (0xFFUL /*<< MPU_MAIR0_Attr0_Pos*/) /*!< MPU MAIR0: Attr0 Mask */ + +/* MPU Memory Attribute Indirection Register 1 Definitions */ +#define MPU_MAIR1_Attr7_Pos 24U /*!< MPU MAIR1: Attr7 Position */ +#define MPU_MAIR1_Attr7_Msk (0xFFUL << MPU_MAIR1_Attr7_Pos) /*!< MPU MAIR1: Attr7 Mask */ + +#define MPU_MAIR1_Attr6_Pos 16U /*!< MPU MAIR1: Attr6 Position */ +#define MPU_MAIR1_Attr6_Msk (0xFFUL << MPU_MAIR1_Attr6_Pos) /*!< MPU MAIR1: Attr6 Mask */ + +#define MPU_MAIR1_Attr5_Pos 8U /*!< MPU MAIR1: Attr5 Position */ +#define MPU_MAIR1_Attr5_Msk (0xFFUL << MPU_MAIR1_Attr5_Pos) /*!< MPU MAIR1: Attr5 Mask */ + +#define MPU_MAIR1_Attr4_Pos 0U /*!< MPU MAIR1: Attr4 Position */ +#define MPU_MAIR1_Attr4_Msk (0xFFUL /*<< MPU_MAIR1_Attr4_Pos*/) /*!< MPU MAIR1: Attr4 Mask */ + +/*@} end of group CMSIS_MPU */ +#endif + + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_SAU Security Attribution Unit (SAU) + \brief Type definitions for the Security Attribution Unit (SAU) + @{ + */ + +/** + \brief Structure type to access the Security Attribution Unit (SAU). + */ +typedef struct +{ + __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) SAU Control Register */ + __IM uint32_t TYPE; /*!< Offset: 0x004 (R/ ) SAU Type Register */ +#if defined (__SAUREGION_PRESENT) && (__SAUREGION_PRESENT == 1U) + __IOM uint32_t RNR; /*!< Offset: 0x008 (R/W) SAU Region Number Register */ + __IOM uint32_t RBAR; /*!< Offset: 0x00C (R/W) SAU Region Base Address Register */ + __IOM uint32_t RLAR; /*!< Offset: 0x010 (R/W) SAU Region Limit Address Register */ +#else + uint32_t RESERVED0[3]; +#endif + __IOM uint32_t SFSR; /*!< Offset: 0x014 (R/W) Secure Fault Status Register */ + __IOM uint32_t SFAR; /*!< Offset: 0x018 (R/W) Secure Fault Address Register */ +} SAU_Type; + +/* SAU Control Register Definitions */ +#define SAU_CTRL_ALLNS_Pos 1U /*!< SAU CTRL: ALLNS Position */ +#define SAU_CTRL_ALLNS_Msk (1UL << SAU_CTRL_ALLNS_Pos) /*!< SAU CTRL: ALLNS Mask */ + +#define SAU_CTRL_ENABLE_Pos 0U /*!< SAU CTRL: ENABLE Position */ +#define SAU_CTRL_ENABLE_Msk (1UL /*<< SAU_CTRL_ENABLE_Pos*/) /*!< SAU CTRL: ENABLE Mask */ + +/* SAU Type Register Definitions */ +#define SAU_TYPE_SREGION_Pos 0U /*!< SAU TYPE: SREGION Position */ +#define SAU_TYPE_SREGION_Msk (0xFFUL /*<< SAU_TYPE_SREGION_Pos*/) /*!< SAU TYPE: SREGION Mask */ + +#if defined (__SAUREGION_PRESENT) && (__SAUREGION_PRESENT == 1U) +/* SAU Region Number Register Definitions */ +#define SAU_RNR_REGION_Pos 0U /*!< SAU RNR: REGION Position */ +#define SAU_RNR_REGION_Msk (0xFFUL /*<< SAU_RNR_REGION_Pos*/) /*!< SAU RNR: REGION Mask */ + +/* SAU Region Base Address Register Definitions */ +#define SAU_RBAR_BADDR_Pos 5U /*!< SAU RBAR: BADDR Position */ +#define SAU_RBAR_BADDR_Msk (0x7FFFFFFUL << SAU_RBAR_BADDR_Pos) /*!< SAU RBAR: BADDR Mask */ + +/* SAU Region Limit Address Register Definitions */ +#define SAU_RLAR_LADDR_Pos 5U /*!< SAU RLAR: LADDR Position */ +#define SAU_RLAR_LADDR_Msk (0x7FFFFFFUL << SAU_RLAR_LADDR_Pos) /*!< SAU RLAR: LADDR Mask */ + +#define SAU_RLAR_NSC_Pos 1U /*!< SAU RLAR: NSC Position */ +#define SAU_RLAR_NSC_Msk (1UL << SAU_RLAR_NSC_Pos) /*!< SAU RLAR: NSC Mask */ + +#define SAU_RLAR_ENABLE_Pos 0U /*!< SAU RLAR: ENABLE Position */ +#define SAU_RLAR_ENABLE_Msk (1UL /*<< SAU_RLAR_ENABLE_Pos*/) /*!< SAU RLAR: ENABLE Mask */ + +#endif /* defined (__SAUREGION_PRESENT) && (__SAUREGION_PRESENT == 1U) */ + +/* Secure Fault Status Register Definitions */ +#define SAU_SFSR_LSERR_Pos 7U /*!< SAU SFSR: LSERR Position */ +#define SAU_SFSR_LSERR_Msk (1UL << SAU_SFSR_LSERR_Pos) /*!< SAU SFSR: LSERR Mask */ + +#define SAU_SFSR_SFARVALID_Pos 6U /*!< SAU SFSR: SFARVALID Position */ +#define SAU_SFSR_SFARVALID_Msk (1UL << SAU_SFSR_SFARVALID_Pos) /*!< SAU SFSR: SFARVALID Mask */ + +#define SAU_SFSR_LSPERR_Pos 5U /*!< SAU SFSR: LSPERR Position */ +#define SAU_SFSR_LSPERR_Msk (1UL << SAU_SFSR_LSPERR_Pos) /*!< SAU SFSR: LSPERR Mask */ + +#define SAU_SFSR_INVTRAN_Pos 4U /*!< SAU SFSR: INVTRAN Position */ +#define SAU_SFSR_INVTRAN_Msk (1UL << SAU_SFSR_INVTRAN_Pos) /*!< SAU SFSR: INVTRAN Mask */ + +#define SAU_SFSR_AUVIOL_Pos 3U /*!< SAU SFSR: AUVIOL Position */ +#define SAU_SFSR_AUVIOL_Msk (1UL << SAU_SFSR_AUVIOL_Pos) /*!< SAU SFSR: AUVIOL Mask */ + +#define SAU_SFSR_INVER_Pos 2U /*!< SAU SFSR: INVER Position */ +#define SAU_SFSR_INVER_Msk (1UL << SAU_SFSR_INVER_Pos) /*!< SAU SFSR: INVER Mask */ + +#define SAU_SFSR_INVIS_Pos 1U /*!< SAU SFSR: INVIS Position */ +#define SAU_SFSR_INVIS_Msk (1UL << SAU_SFSR_INVIS_Pos) /*!< SAU SFSR: INVIS Mask */ + +#define SAU_SFSR_INVEP_Pos 0U /*!< SAU SFSR: INVEP Position */ +#define SAU_SFSR_INVEP_Msk (1UL /*<< SAU_SFSR_INVEP_Pos*/) /*!< SAU SFSR: INVEP Mask */ + +/*@} end of group CMSIS_SAU */ +#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_FPU Floating Point Unit (FPU) + \brief Type definitions for the Floating Point Unit (FPU) + @{ + */ + +/** + \brief Structure type to access the Floating Point Unit (FPU). + */ +typedef struct +{ + uint32_t RESERVED0[1U]; + __IOM uint32_t FPCCR; /*!< Offset: 0x004 (R/W) Floating-Point Context Control Register */ + __IOM uint32_t FPCAR; /*!< Offset: 0x008 (R/W) Floating-Point Context Address Register */ + __IOM uint32_t FPDSCR; /*!< Offset: 0x00C (R/W) Floating-Point Default Status Control Register */ + __IM uint32_t MVFR0; /*!< Offset: 0x010 (R/ ) Media and FP Feature Register 0 */ + __IM uint32_t MVFR1; /*!< Offset: 0x014 (R/ ) Media and FP Feature Register 1 */ +} FPU_Type; + +/* Floating-Point Context Control Register Definitions */ +#define FPU_FPCCR_ASPEN_Pos 31U /*!< FPCCR: ASPEN bit Position */ +#define FPU_FPCCR_ASPEN_Msk (1UL << FPU_FPCCR_ASPEN_Pos) /*!< FPCCR: ASPEN bit Mask */ + +#define FPU_FPCCR_LSPEN_Pos 30U /*!< FPCCR: LSPEN Position */ +#define FPU_FPCCR_LSPEN_Msk (1UL << FPU_FPCCR_LSPEN_Pos) /*!< FPCCR: LSPEN bit Mask */ + +#define FPU_FPCCR_LSPENS_Pos 29U /*!< FPCCR: LSPENS Position */ +#define FPU_FPCCR_LSPENS_Msk (1UL << FPU_FPCCR_LSPENS_Pos) /*!< FPCCR: LSPENS bit Mask */ + +#define FPU_FPCCR_CLRONRET_Pos 28U /*!< FPCCR: CLRONRET Position */ +#define FPU_FPCCR_CLRONRET_Msk (1UL << FPU_FPCCR_CLRONRET_Pos) /*!< FPCCR: CLRONRET bit Mask */ + +#define FPU_FPCCR_CLRONRETS_Pos 27U /*!< FPCCR: CLRONRETS Position */ +#define FPU_FPCCR_CLRONRETS_Msk (1UL << FPU_FPCCR_CLRONRETS_Pos) /*!< FPCCR: CLRONRETS bit Mask */ + +#define FPU_FPCCR_TS_Pos 26U /*!< FPCCR: TS Position */ +#define FPU_FPCCR_TS_Msk (1UL << FPU_FPCCR_TS_Pos) /*!< FPCCR: TS bit Mask */ + +#define FPU_FPCCR_UFRDY_Pos 10U /*!< FPCCR: UFRDY Position */ +#define FPU_FPCCR_UFRDY_Msk (1UL << FPU_FPCCR_UFRDY_Pos) /*!< FPCCR: UFRDY bit Mask */ + +#define FPU_FPCCR_SPLIMVIOL_Pos 9U /*!< FPCCR: SPLIMVIOL Position */ +#define FPU_FPCCR_SPLIMVIOL_Msk (1UL << FPU_FPCCR_SPLIMVIOL_Pos) /*!< FPCCR: SPLIMVIOL bit Mask */ + +#define FPU_FPCCR_MONRDY_Pos 8U /*!< FPCCR: MONRDY Position */ +#define FPU_FPCCR_MONRDY_Msk (1UL << FPU_FPCCR_MONRDY_Pos) /*!< FPCCR: MONRDY bit Mask */ + +#define FPU_FPCCR_SFRDY_Pos 7U /*!< FPCCR: SFRDY Position */ +#define FPU_FPCCR_SFRDY_Msk (1UL << FPU_FPCCR_SFRDY_Pos) /*!< FPCCR: SFRDY bit Mask */ + +#define FPU_FPCCR_BFRDY_Pos 6U /*!< FPCCR: BFRDY Position */ +#define FPU_FPCCR_BFRDY_Msk (1UL << FPU_FPCCR_BFRDY_Pos) /*!< FPCCR: BFRDY bit Mask */ + +#define FPU_FPCCR_MMRDY_Pos 5U /*!< FPCCR: MMRDY Position */ +#define FPU_FPCCR_MMRDY_Msk (1UL << FPU_FPCCR_MMRDY_Pos) /*!< FPCCR: MMRDY bit Mask */ + +#define FPU_FPCCR_HFRDY_Pos 4U /*!< FPCCR: HFRDY Position */ +#define FPU_FPCCR_HFRDY_Msk (1UL << FPU_FPCCR_HFRDY_Pos) /*!< FPCCR: HFRDY bit Mask */ + +#define FPU_FPCCR_THREAD_Pos 3U /*!< FPCCR: processor mode bit Position */ +#define FPU_FPCCR_THREAD_Msk (1UL << FPU_FPCCR_THREAD_Pos) /*!< FPCCR: processor mode active bit Mask */ + +#define FPU_FPCCR_S_Pos 2U /*!< FPCCR: Security status of the FP context bit Position */ +#define FPU_FPCCR_S_Msk (1UL << FPU_FPCCR_S_Pos) /*!< FPCCR: Security status of the FP context bit Mask */ + +#define FPU_FPCCR_USER_Pos 1U /*!< FPCCR: privilege level bit Position */ +#define FPU_FPCCR_USER_Msk (1UL << FPU_FPCCR_USER_Pos) /*!< FPCCR: privilege level bit Mask */ + +#define FPU_FPCCR_LSPACT_Pos 0U /*!< FPCCR: Lazy state preservation active bit Position */ +#define FPU_FPCCR_LSPACT_Msk (1UL /*<< FPU_FPCCR_LSPACT_Pos*/) /*!< FPCCR: Lazy state preservation active bit Mask */ + +/* Floating-Point Context Address Register Definitions */ +#define FPU_FPCAR_ADDRESS_Pos 3U /*!< FPCAR: ADDRESS bit Position */ +#define FPU_FPCAR_ADDRESS_Msk (0x1FFFFFFFUL << FPU_FPCAR_ADDRESS_Pos) /*!< FPCAR: ADDRESS bit Mask */ + +/* Floating-Point Default Status Control Register Definitions */ +#define FPU_FPDSCR_AHP_Pos 26U /*!< FPDSCR: AHP bit Position */ +#define FPU_FPDSCR_AHP_Msk (1UL << FPU_FPDSCR_AHP_Pos) /*!< FPDSCR: AHP bit Mask */ + +#define FPU_FPDSCR_DN_Pos 25U /*!< FPDSCR: DN bit Position */ +#define FPU_FPDSCR_DN_Msk (1UL << FPU_FPDSCR_DN_Pos) /*!< FPDSCR: DN bit Mask */ + +#define FPU_FPDSCR_FZ_Pos 24U /*!< FPDSCR: FZ bit Position */ +#define FPU_FPDSCR_FZ_Msk (1UL << FPU_FPDSCR_FZ_Pos) /*!< FPDSCR: FZ bit Mask */ + +#define FPU_FPDSCR_RMode_Pos 22U /*!< FPDSCR: RMode bit Position */ +#define FPU_FPDSCR_RMode_Msk (3UL << FPU_FPDSCR_RMode_Pos) /*!< FPDSCR: RMode bit Mask */ + +/* Media and FP Feature Register 0 Definitions */ +#define FPU_MVFR0_FP_rounding_modes_Pos 28U /*!< MVFR0: FP rounding modes bits Position */ +#define FPU_MVFR0_FP_rounding_modes_Msk (0xFUL << FPU_MVFR0_FP_rounding_modes_Pos) /*!< MVFR0: FP rounding modes bits Mask */ + +#define FPU_MVFR0_Short_vectors_Pos 24U /*!< MVFR0: Short vectors bits Position */ +#define FPU_MVFR0_Short_vectors_Msk (0xFUL << FPU_MVFR0_Short_vectors_Pos) /*!< MVFR0: Short vectors bits Mask */ + +#define FPU_MVFR0_Square_root_Pos 20U /*!< MVFR0: Square root bits Position */ +#define FPU_MVFR0_Square_root_Msk (0xFUL << FPU_MVFR0_Square_root_Pos) /*!< MVFR0: Square root bits Mask */ + +#define FPU_MVFR0_Divide_Pos 16U /*!< MVFR0: Divide bits Position */ +#define FPU_MVFR0_Divide_Msk (0xFUL << FPU_MVFR0_Divide_Pos) /*!< MVFR0: Divide bits Mask */ + +#define FPU_MVFR0_FP_excep_trapping_Pos 12U /*!< MVFR0: FP exception trapping bits Position */ +#define FPU_MVFR0_FP_excep_trapping_Msk (0xFUL << FPU_MVFR0_FP_excep_trapping_Pos) /*!< MVFR0: FP exception trapping bits Mask */ + +#define FPU_MVFR0_Double_precision_Pos 8U /*!< MVFR0: Double-precision bits Position */ +#define FPU_MVFR0_Double_precision_Msk (0xFUL << FPU_MVFR0_Double_precision_Pos) /*!< MVFR0: Double-precision bits Mask */ + +#define FPU_MVFR0_Single_precision_Pos 4U /*!< MVFR0: Single-precision bits Position */ +#define FPU_MVFR0_Single_precision_Msk (0xFUL << FPU_MVFR0_Single_precision_Pos) /*!< MVFR0: Single-precision bits Mask */ + +#define FPU_MVFR0_A_SIMD_registers_Pos 0U /*!< MVFR0: A_SIMD registers bits Position */ +#define FPU_MVFR0_A_SIMD_registers_Msk (0xFUL /*<< FPU_MVFR0_A_SIMD_registers_Pos*/) /*!< MVFR0: A_SIMD registers bits Mask */ + +/* Media and FP Feature Register 1 Definitions */ +#define FPU_MVFR1_FP_fused_MAC_Pos 28U /*!< MVFR1: FP fused MAC bits Position */ +#define FPU_MVFR1_FP_fused_MAC_Msk (0xFUL << FPU_MVFR1_FP_fused_MAC_Pos) /*!< MVFR1: FP fused MAC bits Mask */ + +#define FPU_MVFR1_FP_HPFP_Pos 24U /*!< MVFR1: FP HPFP bits Position */ +#define FPU_MVFR1_FP_HPFP_Msk (0xFUL << FPU_MVFR1_FP_HPFP_Pos) /*!< MVFR1: FP HPFP bits Mask */ + +#define FPU_MVFR1_D_NaN_mode_Pos 4U /*!< MVFR1: D_NaN mode bits Position */ +#define FPU_MVFR1_D_NaN_mode_Msk (0xFUL << FPU_MVFR1_D_NaN_mode_Pos) /*!< MVFR1: D_NaN mode bits Mask */ + +#define FPU_MVFR1_FtZ_mode_Pos 0U /*!< MVFR1: FtZ mode bits Position */ +#define FPU_MVFR1_FtZ_mode_Msk (0xFUL /*<< FPU_MVFR1_FtZ_mode_Pos*/) /*!< MVFR1: FtZ mode bits Mask */ + +/*@} end of group CMSIS_FPU */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_CoreDebug Core Debug Registers (CoreDebug) + \brief Type definitions for the Core Debug Registers + @{ + */ + +/** + \brief Structure type to access the Core Debug Register (CoreDebug). + */ +typedef struct +{ + __IOM uint32_t DHCSR; /*!< Offset: 0x000 (R/W) Debug Halting Control and Status Register */ + __OM uint32_t DCRSR; /*!< Offset: 0x004 ( /W) Debug Core Register Selector Register */ + __IOM uint32_t DCRDR; /*!< Offset: 0x008 (R/W) Debug Core Register Data Register */ + __IOM uint32_t DEMCR; /*!< Offset: 0x00C (R/W) Debug Exception and Monitor Control Register */ + uint32_t RESERVED4[1U]; + __IOM uint32_t DAUTHCTRL; /*!< Offset: 0x014 (R/W) Debug Authentication Control Register */ + __IOM uint32_t DSCSR; /*!< Offset: 0x018 (R/W) Debug Security Control and Status Register */ +} CoreDebug_Type; + +/* Debug Halting Control and Status Register Definitions */ +#define CoreDebug_DHCSR_DBGKEY_Pos 16U /*!< CoreDebug DHCSR: DBGKEY Position */ +#define CoreDebug_DHCSR_DBGKEY_Msk (0xFFFFUL << CoreDebug_DHCSR_DBGKEY_Pos) /*!< CoreDebug DHCSR: DBGKEY Mask */ + +#define CoreDebug_DHCSR_S_RESTART_ST_Pos 26U /*!< CoreDebug DHCSR: S_RESTART_ST Position */ +#define CoreDebug_DHCSR_S_RESTART_ST_Msk (1UL << CoreDebug_DHCSR_S_RESTART_ST_Pos) /*!< CoreDebug DHCSR: S_RESTART_ST Mask */ + +#define CoreDebug_DHCSR_S_RESET_ST_Pos 25U /*!< CoreDebug DHCSR: S_RESET_ST Position */ +#define CoreDebug_DHCSR_S_RESET_ST_Msk (1UL << CoreDebug_DHCSR_S_RESET_ST_Pos) /*!< CoreDebug DHCSR: S_RESET_ST Mask */ + +#define CoreDebug_DHCSR_S_RETIRE_ST_Pos 24U /*!< CoreDebug DHCSR: S_RETIRE_ST Position */ +#define CoreDebug_DHCSR_S_RETIRE_ST_Msk (1UL << CoreDebug_DHCSR_S_RETIRE_ST_Pos) /*!< CoreDebug DHCSR: S_RETIRE_ST Mask */ + +#define CoreDebug_DHCSR_S_LOCKUP_Pos 19U /*!< CoreDebug DHCSR: S_LOCKUP Position */ +#define CoreDebug_DHCSR_S_LOCKUP_Msk (1UL << CoreDebug_DHCSR_S_LOCKUP_Pos) /*!< CoreDebug DHCSR: S_LOCKUP Mask */ + +#define CoreDebug_DHCSR_S_SLEEP_Pos 18U /*!< CoreDebug DHCSR: S_SLEEP Position */ +#define CoreDebug_DHCSR_S_SLEEP_Msk (1UL << CoreDebug_DHCSR_S_SLEEP_Pos) /*!< CoreDebug DHCSR: S_SLEEP Mask */ + +#define CoreDebug_DHCSR_S_HALT_Pos 17U /*!< CoreDebug DHCSR: S_HALT Position */ +#define CoreDebug_DHCSR_S_HALT_Msk (1UL << CoreDebug_DHCSR_S_HALT_Pos) /*!< CoreDebug DHCSR: S_HALT Mask */ + +#define CoreDebug_DHCSR_S_REGRDY_Pos 16U /*!< CoreDebug DHCSR: S_REGRDY Position */ +#define CoreDebug_DHCSR_S_REGRDY_Msk (1UL << CoreDebug_DHCSR_S_REGRDY_Pos) /*!< CoreDebug DHCSR: S_REGRDY Mask */ + +#define CoreDebug_DHCSR_C_SNAPSTALL_Pos 5U /*!< CoreDebug DHCSR: C_SNAPSTALL Position */ +#define CoreDebug_DHCSR_C_SNAPSTALL_Msk (1UL << CoreDebug_DHCSR_C_SNAPSTALL_Pos) /*!< CoreDebug DHCSR: C_SNAPSTALL Mask */ + +#define CoreDebug_DHCSR_C_MASKINTS_Pos 3U /*!< CoreDebug DHCSR: C_MASKINTS Position */ +#define CoreDebug_DHCSR_C_MASKINTS_Msk (1UL << CoreDebug_DHCSR_C_MASKINTS_Pos) /*!< CoreDebug DHCSR: C_MASKINTS Mask */ + +#define CoreDebug_DHCSR_C_STEP_Pos 2U /*!< CoreDebug DHCSR: C_STEP Position */ +#define CoreDebug_DHCSR_C_STEP_Msk (1UL << CoreDebug_DHCSR_C_STEP_Pos) /*!< CoreDebug DHCSR: C_STEP Mask */ + +#define CoreDebug_DHCSR_C_HALT_Pos 1U /*!< CoreDebug DHCSR: C_HALT Position */ +#define CoreDebug_DHCSR_C_HALT_Msk (1UL << CoreDebug_DHCSR_C_HALT_Pos) /*!< CoreDebug DHCSR: C_HALT Mask */ + +#define CoreDebug_DHCSR_C_DEBUGEN_Pos 0U /*!< CoreDebug DHCSR: C_DEBUGEN Position */ +#define CoreDebug_DHCSR_C_DEBUGEN_Msk (1UL /*<< CoreDebug_DHCSR_C_DEBUGEN_Pos*/) /*!< CoreDebug DHCSR: C_DEBUGEN Mask */ + +/* Debug Core Register Selector Register Definitions */ +#define CoreDebug_DCRSR_REGWnR_Pos 16U /*!< CoreDebug DCRSR: REGWnR Position */ +#define CoreDebug_DCRSR_REGWnR_Msk (1UL << CoreDebug_DCRSR_REGWnR_Pos) /*!< CoreDebug DCRSR: REGWnR Mask */ + +#define CoreDebug_DCRSR_REGSEL_Pos 0U /*!< CoreDebug DCRSR: REGSEL Position */ +#define CoreDebug_DCRSR_REGSEL_Msk (0x1FUL /*<< CoreDebug_DCRSR_REGSEL_Pos*/) /*!< CoreDebug DCRSR: REGSEL Mask */ + +/* Debug Exception and Monitor Control Register Definitions */ +#define CoreDebug_DEMCR_TRCENA_Pos 24U /*!< CoreDebug DEMCR: TRCENA Position */ +#define CoreDebug_DEMCR_TRCENA_Msk (1UL << CoreDebug_DEMCR_TRCENA_Pos) /*!< CoreDebug DEMCR: TRCENA Mask */ + +#define CoreDebug_DEMCR_MON_REQ_Pos 19U /*!< CoreDebug DEMCR: MON_REQ Position */ +#define CoreDebug_DEMCR_MON_REQ_Msk (1UL << CoreDebug_DEMCR_MON_REQ_Pos) /*!< CoreDebug DEMCR: MON_REQ Mask */ + +#define CoreDebug_DEMCR_MON_STEP_Pos 18U /*!< CoreDebug DEMCR: MON_STEP Position */ +#define CoreDebug_DEMCR_MON_STEP_Msk (1UL << CoreDebug_DEMCR_MON_STEP_Pos) /*!< CoreDebug DEMCR: MON_STEP Mask */ + +#define CoreDebug_DEMCR_MON_PEND_Pos 17U /*!< CoreDebug DEMCR: MON_PEND Position */ +#define CoreDebug_DEMCR_MON_PEND_Msk (1UL << CoreDebug_DEMCR_MON_PEND_Pos) /*!< CoreDebug DEMCR: MON_PEND Mask */ + +#define CoreDebug_DEMCR_MON_EN_Pos 16U /*!< CoreDebug DEMCR: MON_EN Position */ +#define CoreDebug_DEMCR_MON_EN_Msk (1UL << CoreDebug_DEMCR_MON_EN_Pos) /*!< CoreDebug DEMCR: MON_EN Mask */ + +#define CoreDebug_DEMCR_VC_HARDERR_Pos 10U /*!< CoreDebug DEMCR: VC_HARDERR Position */ +#define CoreDebug_DEMCR_VC_HARDERR_Msk (1UL << CoreDebug_DEMCR_VC_HARDERR_Pos) /*!< CoreDebug DEMCR: VC_HARDERR Mask */ + +#define CoreDebug_DEMCR_VC_INTERR_Pos 9U /*!< CoreDebug DEMCR: VC_INTERR Position */ +#define CoreDebug_DEMCR_VC_INTERR_Msk (1UL << CoreDebug_DEMCR_VC_INTERR_Pos) /*!< CoreDebug DEMCR: VC_INTERR Mask */ + +#define CoreDebug_DEMCR_VC_BUSERR_Pos 8U /*!< CoreDebug DEMCR: VC_BUSERR Position */ +#define CoreDebug_DEMCR_VC_BUSERR_Msk (1UL << CoreDebug_DEMCR_VC_BUSERR_Pos) /*!< CoreDebug DEMCR: VC_BUSERR Mask */ + +#define CoreDebug_DEMCR_VC_STATERR_Pos 7U /*!< CoreDebug DEMCR: VC_STATERR Position */ +#define CoreDebug_DEMCR_VC_STATERR_Msk (1UL << CoreDebug_DEMCR_VC_STATERR_Pos) /*!< CoreDebug DEMCR: VC_STATERR Mask */ + +#define CoreDebug_DEMCR_VC_CHKERR_Pos 6U /*!< CoreDebug DEMCR: VC_CHKERR Position */ +#define CoreDebug_DEMCR_VC_CHKERR_Msk (1UL << CoreDebug_DEMCR_VC_CHKERR_Pos) /*!< CoreDebug DEMCR: VC_CHKERR Mask */ + +#define CoreDebug_DEMCR_VC_NOCPERR_Pos 5U /*!< CoreDebug DEMCR: VC_NOCPERR Position */ +#define CoreDebug_DEMCR_VC_NOCPERR_Msk (1UL << CoreDebug_DEMCR_VC_NOCPERR_Pos) /*!< CoreDebug DEMCR: VC_NOCPERR Mask */ + +#define CoreDebug_DEMCR_VC_MMERR_Pos 4U /*!< CoreDebug DEMCR: VC_MMERR Position */ +#define CoreDebug_DEMCR_VC_MMERR_Msk (1UL << CoreDebug_DEMCR_VC_MMERR_Pos) /*!< CoreDebug DEMCR: VC_MMERR Mask */ + +#define CoreDebug_DEMCR_VC_CORERESET_Pos 0U /*!< CoreDebug DEMCR: VC_CORERESET Position */ +#define CoreDebug_DEMCR_VC_CORERESET_Msk (1UL /*<< CoreDebug_DEMCR_VC_CORERESET_Pos*/) /*!< CoreDebug DEMCR: VC_CORERESET Mask */ + +/* Debug Authentication Control Register Definitions */ +#define CoreDebug_DAUTHCTRL_INTSPNIDEN_Pos 3U /*!< CoreDebug DAUTHCTRL: INTSPNIDEN, Position */ +#define CoreDebug_DAUTHCTRL_INTSPNIDEN_Msk (1UL << CoreDebug_DAUTHCTRL_INTSPNIDEN_Pos) /*!< CoreDebug DAUTHCTRL: INTSPNIDEN, Mask */ + +#define CoreDebug_DAUTHCTRL_SPNIDENSEL_Pos 2U /*!< CoreDebug DAUTHCTRL: SPNIDENSEL Position */ +#define CoreDebug_DAUTHCTRL_SPNIDENSEL_Msk (1UL << CoreDebug_DAUTHCTRL_SPNIDENSEL_Pos) /*!< CoreDebug DAUTHCTRL: SPNIDENSEL Mask */ + +#define CoreDebug_DAUTHCTRL_INTSPIDEN_Pos 1U /*!< CoreDebug DAUTHCTRL: INTSPIDEN Position */ +#define CoreDebug_DAUTHCTRL_INTSPIDEN_Msk (1UL << CoreDebug_DAUTHCTRL_INTSPIDEN_Pos) /*!< CoreDebug DAUTHCTRL: INTSPIDEN Mask */ + +#define CoreDebug_DAUTHCTRL_SPIDENSEL_Pos 0U /*!< CoreDebug DAUTHCTRL: SPIDENSEL Position */ +#define CoreDebug_DAUTHCTRL_SPIDENSEL_Msk (1UL /*<< CoreDebug_DAUTHCTRL_SPIDENSEL_Pos*/) /*!< CoreDebug DAUTHCTRL: SPIDENSEL Mask */ + +/* Debug Security Control and Status Register Definitions */ +#define CoreDebug_DSCSR_CDS_Pos 16U /*!< CoreDebug DSCSR: CDS Position */ +#define CoreDebug_DSCSR_CDS_Msk (1UL << CoreDebug_DSCSR_CDS_Pos) /*!< CoreDebug DSCSR: CDS Mask */ + +#define CoreDebug_DSCSR_SBRSEL_Pos 1U /*!< CoreDebug DSCSR: SBRSEL Position */ +#define CoreDebug_DSCSR_SBRSEL_Msk (1UL << CoreDebug_DSCSR_SBRSEL_Pos) /*!< CoreDebug DSCSR: SBRSEL Mask */ + +#define CoreDebug_DSCSR_SBRSELEN_Pos 0U /*!< CoreDebug DSCSR: SBRSELEN Position */ +#define CoreDebug_DSCSR_SBRSELEN_Msk (1UL /*<< CoreDebug_DSCSR_SBRSELEN_Pos*/) /*!< CoreDebug DSCSR: SBRSELEN Mask */ + +/*@} end of group CMSIS_CoreDebug */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_core_bitfield Core register bit field macros + \brief Macros for use with bit field definitions (xxx_Pos, xxx_Msk). + @{ + */ + +/** + \brief Mask and shift a bit field value for use in a register bit range. + \param[in] field Name of the register bit field. + \param[in] value Value of the bit field. This parameter is interpreted as an uint32_t type. + \return Masked and shifted value. +*/ +#define _VAL2FLD(field, value) (((uint32_t)(value) << field ## _Pos) & field ## _Msk) + +/** + \brief Mask and shift a register value to extract a bit filed value. + \param[in] field Name of the register bit field. + \param[in] value Value of register. This parameter is interpreted as an uint32_t type. + \return Masked and shifted bit field value. +*/ +#define _FLD2VAL(field, value) (((uint32_t)(value) & field ## _Msk) >> field ## _Pos) + +/*@} end of group CMSIS_core_bitfield */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_core_base Core Definitions + \brief Definitions for base addresses, unions, and structures. + @{ + */ + +/* Memory mapping of Core Hardware */ + #define SCS_BASE (0xE000E000UL) /*!< System Control Space Base Address */ + #define ITM_BASE (0xE0000000UL) /*!< ITM Base Address */ + #define DWT_BASE (0xE0001000UL) /*!< DWT Base Address */ + #define TPI_BASE (0xE0040000UL) /*!< TPI Base Address */ + #define CoreDebug_BASE (0xE000EDF0UL) /*!< Core Debug Base Address */ + #define SysTick_BASE (SCS_BASE + 0x0010UL) /*!< SysTick Base Address */ + #define NVIC_BASE (SCS_BASE + 0x0100UL) /*!< NVIC Base Address */ + #define SCB_BASE (SCS_BASE + 0x0D00UL) /*!< System Control Block Base Address */ + + #define SCnSCB ((SCnSCB_Type *) SCS_BASE ) /*!< System control Register not in SCB */ + #define SCB ((SCB_Type *) SCB_BASE ) /*!< SCB configuration struct */ + #define SysTick ((SysTick_Type *) SysTick_BASE ) /*!< SysTick configuration struct */ + #define NVIC ((NVIC_Type *) NVIC_BASE ) /*!< NVIC configuration struct */ + #define ITM ((ITM_Type *) ITM_BASE ) /*!< ITM configuration struct */ + #define DWT ((DWT_Type *) DWT_BASE ) /*!< DWT configuration struct */ + #define TPI ((TPI_Type *) TPI_BASE ) /*!< TPI configuration struct */ + #define CoreDebug ((CoreDebug_Type *) CoreDebug_BASE ) /*!< Core Debug configuration struct */ + + #if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) + #define MPU_BASE (SCS_BASE + 0x0D90UL) /*!< Memory Protection Unit */ + #define MPU ((MPU_Type *) MPU_BASE ) /*!< Memory Protection Unit */ + #endif + + #if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) + #define SAU_BASE (SCS_BASE + 0x0DD0UL) /*!< Security Attribution Unit */ + #define SAU ((SAU_Type *) SAU_BASE ) /*!< Security Attribution Unit */ + #endif + + #define FPU_BASE (SCS_BASE + 0x0F30UL) /*!< Floating Point Unit */ + #define FPU ((FPU_Type *) FPU_BASE ) /*!< Floating Point Unit */ + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) + #define SCS_BASE_NS (0xE002E000UL) /*!< System Control Space Base Address (non-secure address space) */ + #define CoreDebug_BASE_NS (0xE002EDF0UL) /*!< Core Debug Base Address (non-secure address space) */ + #define SysTick_BASE_NS (SCS_BASE_NS + 0x0010UL) /*!< SysTick Base Address (non-secure address space) */ + #define NVIC_BASE_NS (SCS_BASE_NS + 0x0100UL) /*!< NVIC Base Address (non-secure address space) */ + #define SCB_BASE_NS (SCS_BASE_NS + 0x0D00UL) /*!< System Control Block Base Address (non-secure address space) */ + + #define SCnSCB_NS ((SCnSCB_Type *) SCS_BASE_NS ) /*!< System control Register not in SCB(non-secure address space) */ + #define SCB_NS ((SCB_Type *) SCB_BASE_NS ) /*!< SCB configuration struct (non-secure address space) */ + #define SysTick_NS ((SysTick_Type *) SysTick_BASE_NS ) /*!< SysTick configuration struct (non-secure address space) */ + #define NVIC_NS ((NVIC_Type *) NVIC_BASE_NS ) /*!< NVIC configuration struct (non-secure address space) */ + #define CoreDebug_NS ((CoreDebug_Type *) CoreDebug_BASE_NS) /*!< Core Debug configuration struct (non-secure address space) */ + + #if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) + #define MPU_BASE_NS (SCS_BASE_NS + 0x0D90UL) /*!< Memory Protection Unit (non-secure address space) */ + #define MPU_NS ((MPU_Type *) MPU_BASE_NS ) /*!< Memory Protection Unit (non-secure address space) */ + #endif + + #define FPU_BASE_NS (SCS_BASE_NS + 0x0F30UL) /*!< Floating Point Unit (non-secure address space) */ + #define FPU_NS ((FPU_Type *) FPU_BASE_NS ) /*!< Floating Point Unit (non-secure address space) */ + +#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */ +/*@} */ + + + +/******************************************************************************* + * Hardware Abstraction Layer + Core Function Interface contains: + - Core NVIC Functions + - Core SysTick Functions + - Core Debug Functions + - Core Register Access Functions + ******************************************************************************/ +/** + \defgroup CMSIS_Core_FunctionInterface Functions and Instructions Reference +*/ + + + +/* ########################## NVIC functions #################################### */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_NVICFunctions NVIC Functions + \brief Functions that manage interrupts and exceptions via the NVIC. + @{ + */ + +#ifdef CMSIS_NVIC_VIRTUAL + #ifndef CMSIS_NVIC_VIRTUAL_HEADER_FILE + #define CMSIS_NVIC_VIRTUAL_HEADER_FILE "cmsis_nvic_virtual.h" + #endif + #include CMSIS_NVIC_VIRTUAL_HEADER_FILE +#else + #define NVIC_SetPriorityGrouping __NVIC_SetPriorityGrouping + #define NVIC_GetPriorityGrouping __NVIC_GetPriorityGrouping + #define NVIC_EnableIRQ __NVIC_EnableIRQ + #define NVIC_GetEnableIRQ __NVIC_GetEnableIRQ + #define NVIC_DisableIRQ __NVIC_DisableIRQ + #define NVIC_GetPendingIRQ __NVIC_GetPendingIRQ + #define NVIC_SetPendingIRQ __NVIC_SetPendingIRQ + #define NVIC_ClearPendingIRQ __NVIC_ClearPendingIRQ + #define NVIC_GetActive __NVIC_GetActive + #define NVIC_SetPriority __NVIC_SetPriority + #define NVIC_GetPriority __NVIC_GetPriority + #define NVIC_SystemReset __NVIC_SystemReset +#endif /* CMSIS_NVIC_VIRTUAL */ + +#ifdef CMSIS_VECTAB_VIRTUAL + #ifndef CMSIS_VECTAB_VIRTUAL_HEADER_FILE + #define CMSIS_VECTAB_VIRTUAL_HEADER_FILE "cmsis_vectab_virtual.h" + #endif + #include CMSIS_VECTAB_VIRTUAL_HEADER_FILE +#else + #define NVIC_SetVector __NVIC_SetVector + #define NVIC_GetVector __NVIC_GetVector +#endif /* (CMSIS_VECTAB_VIRTUAL) */ + +#define NVIC_USER_IRQ_OFFSET 16 + + +/* Special LR values for Secure/Non-Secure call handling and exception handling */ + +/* Function Return Payload (from ARMv8-M Architecture Reference Manual) LR value on entry from Secure BLXNS */ +#define FNC_RETURN (0xFEFFFFFFUL) /* bit [0] ignored when processing a branch */ + +/* The following EXC_RETURN mask values are used to evaluate the LR on exception entry */ +#define EXC_RETURN_PREFIX (0xFF000000UL) /* bits [31:24] set to indicate an EXC_RETURN value */ +#define EXC_RETURN_S (0x00000040UL) /* bit [6] stack used to push registers: 0=Non-secure 1=Secure */ +#define EXC_RETURN_DCRS (0x00000020UL) /* bit [5] stacking rules for called registers: 0=skipped 1=saved */ +#define EXC_RETURN_FTYPE (0x00000010UL) /* bit [4] allocate stack for floating-point context: 0=done 1=skipped */ +#define EXC_RETURN_MODE (0x00000008UL) /* bit [3] processor mode for return: 0=Handler mode 1=Thread mode */ +#define EXC_RETURN_SPSEL (0x00000004UL) /* bit [2] stack pointer used to restore context: 0=MSP 1=PSP */ +#define EXC_RETURN_ES (0x00000001UL) /* bit [0] security state exception was taken to: 0=Non-secure 1=Secure */ + +/* Integrity Signature (from ARMv8-M Architecture Reference Manual) for exception context stacking */ +#if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) /* Value for processors with floating-point extension: */ +#define EXC_INTEGRITY_SIGNATURE (0xFEFA125AUL) /* bit [0] SFTC must match LR bit[4] EXC_RETURN_FTYPE */ +#else +#define EXC_INTEGRITY_SIGNATURE (0xFEFA125BUL) /* Value for processors without floating-point extension */ +#endif + + +/** + \brief Set Priority Grouping + \details Sets the priority grouping field using the required unlock sequence. + The parameter PriorityGroup is assigned to the field SCB->AIRCR [10:8] PRIGROUP field. + Only values from 0..7 are used. + In case of a conflict between priority grouping and available + priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set. + \param [in] PriorityGroup Priority grouping field. + */ +__STATIC_INLINE void __NVIC_SetPriorityGrouping(uint32_t PriorityGroup) +{ + uint32_t reg_value; + uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ + + reg_value = SCB->AIRCR; /* read old register configuration */ + reg_value &= ~((uint32_t)(SCB_AIRCR_VECTKEY_Msk | SCB_AIRCR_PRIGROUP_Msk)); /* clear bits to change */ + reg_value = (reg_value | + ((uint32_t)0x5FAUL << SCB_AIRCR_VECTKEY_Pos) | + (PriorityGroupTmp << SCB_AIRCR_PRIGROUP_Pos) ); /* Insert write key and priority group */ + SCB->AIRCR = reg_value; +} + + +/** + \brief Get Priority Grouping + \details Reads the priority grouping field from the NVIC Interrupt Controller. + \return Priority grouping field (SCB->AIRCR [10:8] PRIGROUP field). + */ +__STATIC_INLINE uint32_t __NVIC_GetPriorityGrouping(void) +{ + return ((uint32_t)((SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) >> SCB_AIRCR_PRIGROUP_Pos)); +} + + +/** + \brief Enable Interrupt + \details Enables a device specific interrupt in the NVIC interrupt controller. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_EnableIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + __COMPILER_BARRIER(); + NVIC->ISER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + __COMPILER_BARRIER(); + } +} + + +/** + \brief Get Interrupt Enable status + \details Returns a device specific interrupt enable status from the NVIC interrupt controller. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt is not enabled. + \return 1 Interrupt is enabled. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t __NVIC_GetEnableIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC->ISER[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Disable Interrupt + \details Disables a device specific interrupt in the NVIC interrupt controller. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_DisableIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ICER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + __DSB(); + __ISB(); + } +} + + +/** + \brief Get Pending Interrupt + \details Reads the NVIC pending register and returns the pending bit for the specified device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt status is not pending. + \return 1 Interrupt status is pending. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t __NVIC_GetPendingIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC->ISPR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Set Pending Interrupt + \details Sets the pending bit of a device specific interrupt in the NVIC pending register. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_SetPendingIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ISPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Clear Pending Interrupt + \details Clears the pending bit of a device specific interrupt in the NVIC pending register. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_ClearPendingIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ICPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Get Active Interrupt + \details Reads the active register in the NVIC and returns the active bit for the device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt status is not active. + \return 1 Interrupt status is active. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t __NVIC_GetActive(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC->IABR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) +/** + \brief Get Interrupt Target State + \details Reads the interrupt target field in the NVIC and returns the interrupt target bit for the device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 if interrupt is assigned to Secure + \return 1 if interrupt is assigned to Non Secure + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t NVIC_GetTargetState(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC->ITNS[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Set Interrupt Target State + \details Sets the interrupt target field in the NVIC and returns the interrupt target bit for the device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 if interrupt is assigned to Secure + 1 if interrupt is assigned to Non Secure + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t NVIC_SetTargetState(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ITNS[(((uint32_t)IRQn) >> 5UL)] |= ((uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL))); + return((uint32_t)(((NVIC->ITNS[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Clear Interrupt Target State + \details Clears the interrupt target field in the NVIC and returns the interrupt target bit for the device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 if interrupt is assigned to Secure + 1 if interrupt is assigned to Non Secure + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t NVIC_ClearTargetState(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ITNS[(((uint32_t)IRQn) >> 5UL)] &= ~((uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL))); + return((uint32_t)(((NVIC->ITNS[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} +#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */ + + +/** + \brief Set Interrupt Priority + \details Sets the priority of a device specific interrupt or a processor exception. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \param [in] priority Priority to set. + \note The priority cannot be set for every processor exception. + */ +__STATIC_INLINE void __NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->IPR[((uint32_t)IRQn)] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL); + } + else + { + SCB->SHPR[(((uint32_t)IRQn) & 0xFUL)-4UL] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL); + } +} + + +/** + \brief Get Interrupt Priority + \details Reads the priority of a device specific interrupt or a processor exception. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \return Interrupt Priority. + Value is aligned automatically to the implemented priority bits of the microcontroller. + */ +__STATIC_INLINE uint32_t __NVIC_GetPriority(IRQn_Type IRQn) +{ + + if ((int32_t)(IRQn) >= 0) + { + return(((uint32_t)NVIC->IPR[((uint32_t)IRQn)] >> (8U - __NVIC_PRIO_BITS))); + } + else + { + return(((uint32_t)SCB->SHPR[(((uint32_t)IRQn) & 0xFUL)-4UL] >> (8U - __NVIC_PRIO_BITS))); + } +} + + +/** + \brief Encode Priority + \details Encodes the priority for an interrupt with the given priority group, + preemptive priority value, and subpriority value. + In case of a conflict between priority grouping and available + priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set. + \param [in] PriorityGroup Used priority group. + \param [in] PreemptPriority Preemptive priority value (starting from 0). + \param [in] SubPriority Subpriority value (starting from 0). + \return Encoded priority. Value can be used in the function \ref NVIC_SetPriority(). + */ +__STATIC_INLINE uint32_t NVIC_EncodePriority (uint32_t PriorityGroup, uint32_t PreemptPriority, uint32_t SubPriority) +{ + uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ + uint32_t PreemptPriorityBits; + uint32_t SubPriorityBits; + + PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp); + SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS)); + + return ( + ((PreemptPriority & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL)) << SubPriorityBits) | + ((SubPriority & (uint32_t)((1UL << (SubPriorityBits )) - 1UL))) + ); +} + + +/** + \brief Decode Priority + \details Decodes an interrupt priority value with a given priority group to + preemptive priority value and subpriority value. + In case of a conflict between priority grouping and available + priority bits (__NVIC_PRIO_BITS) the smallest possible priority group is set. + \param [in] Priority Priority value, which can be retrieved with the function \ref NVIC_GetPriority(). + \param [in] PriorityGroup Used priority group. + \param [out] pPreemptPriority Preemptive priority value (starting from 0). + \param [out] pSubPriority Subpriority value (starting from 0). + */ +__STATIC_INLINE void NVIC_DecodePriority (uint32_t Priority, uint32_t PriorityGroup, uint32_t* const pPreemptPriority, uint32_t* const pSubPriority) +{ + uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ + uint32_t PreemptPriorityBits; + uint32_t SubPriorityBits; + + PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp); + SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS)); + + *pPreemptPriority = (Priority >> SubPriorityBits) & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL); + *pSubPriority = (Priority ) & (uint32_t)((1UL << (SubPriorityBits )) - 1UL); +} + + +/** + \brief Set Interrupt Vector + \details Sets an interrupt vector in SRAM based interrupt vector table. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + VTOR must been relocated to SRAM before. + \param [in] IRQn Interrupt number + \param [in] vector Address of interrupt handler function + */ +__STATIC_INLINE void __NVIC_SetVector(IRQn_Type IRQn, uint32_t vector) +{ + uint32_t *vectors = (uint32_t *)SCB->VTOR; + vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET] = vector; + __DSB(); +} + + +/** + \brief Get Interrupt Vector + \details Reads an interrupt vector from interrupt vector table. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \return Address of interrupt handler function + */ +__STATIC_INLINE uint32_t __NVIC_GetVector(IRQn_Type IRQn) +{ + uint32_t *vectors = (uint32_t *)SCB->VTOR; + return vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET]; +} + + +/** + \brief System Reset + \details Initiates a system reset request to reset the MCU. + */ +__NO_RETURN __STATIC_INLINE void __NVIC_SystemReset(void) +{ + __DSB(); /* Ensure all outstanding memory accesses included + buffered write are completed before reset */ + SCB->AIRCR = (uint32_t)((0x5FAUL << SCB_AIRCR_VECTKEY_Pos) | + (SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) | + SCB_AIRCR_SYSRESETREQ_Msk ); /* Keep priority group unchanged */ + __DSB(); /* Ensure completion of memory access */ + + for(;;) /* wait until reset */ + { + __NOP(); + } +} + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) +/** + \brief Set Priority Grouping (non-secure) + \details Sets the non-secure priority grouping field when in secure state using the required unlock sequence. + The parameter PriorityGroup is assigned to the field SCB->AIRCR [10:8] PRIGROUP field. + Only values from 0..7 are used. + In case of a conflict between priority grouping and available + priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set. + \param [in] PriorityGroup Priority grouping field. + */ +__STATIC_INLINE void TZ_NVIC_SetPriorityGrouping_NS(uint32_t PriorityGroup) +{ + uint32_t reg_value; + uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ + + reg_value = SCB_NS->AIRCR; /* read old register configuration */ + reg_value &= ~((uint32_t)(SCB_AIRCR_VECTKEY_Msk | SCB_AIRCR_PRIGROUP_Msk)); /* clear bits to change */ + reg_value = (reg_value | + ((uint32_t)0x5FAUL << SCB_AIRCR_VECTKEY_Pos) | + (PriorityGroupTmp << SCB_AIRCR_PRIGROUP_Pos) ); /* Insert write key and priority group */ + SCB_NS->AIRCR = reg_value; +} + + +/** + \brief Get Priority Grouping (non-secure) + \details Reads the priority grouping field from the non-secure NVIC when in secure state. + \return Priority grouping field (SCB->AIRCR [10:8] PRIGROUP field). + */ +__STATIC_INLINE uint32_t TZ_NVIC_GetPriorityGrouping_NS(void) +{ + return ((uint32_t)((SCB_NS->AIRCR & SCB_AIRCR_PRIGROUP_Msk) >> SCB_AIRCR_PRIGROUP_Pos)); +} + + +/** + \brief Enable Interrupt (non-secure) + \details Enables a device specific interrupt in the non-secure NVIC interrupt controller when in secure state. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void TZ_NVIC_EnableIRQ_NS(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC_NS->ISER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Get Interrupt Enable status (non-secure) + \details Returns a device specific interrupt enable status from the non-secure NVIC interrupt controller when in secure state. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt is not enabled. + \return 1 Interrupt is enabled. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t TZ_NVIC_GetEnableIRQ_NS(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC_NS->ISER[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Disable Interrupt (non-secure) + \details Disables a device specific interrupt in the non-secure NVIC interrupt controller when in secure state. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void TZ_NVIC_DisableIRQ_NS(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC_NS->ICER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Get Pending Interrupt (non-secure) + \details Reads the NVIC pending register in the non-secure NVIC when in secure state and returns the pending bit for the specified device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt status is not pending. + \return 1 Interrupt status is pending. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t TZ_NVIC_GetPendingIRQ_NS(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC_NS->ISPR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Set Pending Interrupt (non-secure) + \details Sets the pending bit of a device specific interrupt in the non-secure NVIC pending register when in secure state. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void TZ_NVIC_SetPendingIRQ_NS(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC_NS->ISPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Clear Pending Interrupt (non-secure) + \details Clears the pending bit of a device specific interrupt in the non-secure NVIC pending register when in secure state. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void TZ_NVIC_ClearPendingIRQ_NS(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC_NS->ICPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Get Active Interrupt (non-secure) + \details Reads the active register in non-secure NVIC when in secure state and returns the active bit for the device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt status is not active. + \return 1 Interrupt status is active. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t TZ_NVIC_GetActive_NS(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC_NS->IABR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Set Interrupt Priority (non-secure) + \details Sets the priority of a non-secure device specific interrupt or a non-secure processor exception when in secure state. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \param [in] priority Priority to set. + \note The priority cannot be set for every non-secure processor exception. + */ +__STATIC_INLINE void TZ_NVIC_SetPriority_NS(IRQn_Type IRQn, uint32_t priority) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC_NS->IPR[((uint32_t)IRQn)] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL); + } + else + { + SCB_NS->SHPR[(((uint32_t)IRQn) & 0xFUL)-4UL] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL); + } +} + + +/** + \brief Get Interrupt Priority (non-secure) + \details Reads the priority of a non-secure device specific interrupt or a non-secure processor exception when in secure state. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \return Interrupt Priority. Value is aligned automatically to the implemented priority bits of the microcontroller. + */ +__STATIC_INLINE uint32_t TZ_NVIC_GetPriority_NS(IRQn_Type IRQn) +{ + + if ((int32_t)(IRQn) >= 0) + { + return(((uint32_t)NVIC_NS->IPR[((uint32_t)IRQn)] >> (8U - __NVIC_PRIO_BITS))); + } + else + { + return(((uint32_t)SCB_NS->SHPR[(((uint32_t)IRQn) & 0xFUL)-4UL] >> (8U - __NVIC_PRIO_BITS))); + } +} +#endif /* defined (__ARM_FEATURE_CMSE) &&(__ARM_FEATURE_CMSE == 3U) */ + +/*@} end of CMSIS_Core_NVICFunctions */ + +/* ########################## MPU functions #################################### */ + +#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) + +#include "mpu_armv8.h" + +#endif + +/* ########################## FPU functions #################################### */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_FpuFunctions FPU Functions + \brief Function that provides FPU type. + @{ + */ + +/** + \brief get FPU type + \details returns the FPU type + \returns + - \b 0: No FPU + - \b 1: Single precision FPU + - \b 2: Double + Single precision FPU + */ +__STATIC_INLINE uint32_t SCB_GetFPUType(void) +{ + uint32_t mvfr0; + + mvfr0 = FPU->MVFR0; + if ((mvfr0 & (FPU_MVFR0_Single_precision_Msk | FPU_MVFR0_Double_precision_Msk)) == 0x220U) + { + return 2U; /* Double + Single precision FPU */ + } + else if ((mvfr0 & (FPU_MVFR0_Single_precision_Msk | FPU_MVFR0_Double_precision_Msk)) == 0x020U) + { + return 1U; /* Single precision FPU */ + } + else + { + return 0U; /* No FPU */ + } +} + + +/*@} end of CMSIS_Core_FpuFunctions */ + + + +/* ########################## SAU functions #################################### */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_SAUFunctions SAU Functions + \brief Functions that configure the SAU. + @{ + */ + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) + +/** + \brief Enable SAU + \details Enables the Security Attribution Unit (SAU). + */ +__STATIC_INLINE void TZ_SAU_Enable(void) +{ + SAU->CTRL |= (SAU_CTRL_ENABLE_Msk); +} + + + +/** + \brief Disable SAU + \details Disables the Security Attribution Unit (SAU). + */ +__STATIC_INLINE void TZ_SAU_Disable(void) +{ + SAU->CTRL &= ~(SAU_CTRL_ENABLE_Msk); +} + +#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */ + +/*@} end of CMSIS_Core_SAUFunctions */ + + + + +/* ################################## SysTick function ############################################ */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_SysTickFunctions SysTick Functions + \brief Functions that configure the System. + @{ + */ + +#if defined (__Vendor_SysTickConfig) && (__Vendor_SysTickConfig == 0U) + +/** + \brief System Tick Configuration + \details Initializes the System Timer and its interrupt, and starts the System Tick Timer. + Counter is in free running mode to generate periodic interrupts. + \param [in] ticks Number of ticks between two interrupts. + \return 0 Function succeeded. + \return 1 Function failed. + \note When the variable __Vendor_SysTickConfig is set to 1, then the + function SysTick_Config is not included. In this case, the file device.h + must contain a vendor-specific implementation of this function. + */ +__STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks) +{ + if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk) + { + return (1UL); /* Reload value impossible */ + } + + SysTick->LOAD = (uint32_t)(ticks - 1UL); /* set reload register */ + NVIC_SetPriority (SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */ + SysTick->VAL = 0UL; /* Load the SysTick Counter Value */ + SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk | + SysTick_CTRL_TICKINT_Msk | + SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */ + return (0UL); /* Function successful */ +} + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) +/** + \brief System Tick Configuration (non-secure) + \details Initializes the non-secure System Timer and its interrupt when in secure state, and starts the System Tick Timer. + Counter is in free running mode to generate periodic interrupts. + \param [in] ticks Number of ticks between two interrupts. + \return 0 Function succeeded. + \return 1 Function failed. + \note When the variable __Vendor_SysTickConfig is set to 1, then the + function TZ_SysTick_Config_NS is not included. In this case, the file device.h + must contain a vendor-specific implementation of this function. + + */ +__STATIC_INLINE uint32_t TZ_SysTick_Config_NS(uint32_t ticks) +{ + if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk) + { + return (1UL); /* Reload value impossible */ + } + + SysTick_NS->LOAD = (uint32_t)(ticks - 1UL); /* set reload register */ + TZ_NVIC_SetPriority_NS (SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */ + SysTick_NS->VAL = 0UL; /* Load the SysTick Counter Value */ + SysTick_NS->CTRL = SysTick_CTRL_CLKSOURCE_Msk | + SysTick_CTRL_TICKINT_Msk | + SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */ + return (0UL); /* Function successful */ +} +#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */ + +#endif + +/*@} end of CMSIS_Core_SysTickFunctions */ + + + +/* ##################################### Debug In/Output function ########################################### */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_core_DebugFunctions ITM Functions + \brief Functions that access the ITM debug interface. + @{ + */ + +extern volatile int32_t ITM_RxBuffer; /*!< External variable to receive characters. */ +#define ITM_RXBUFFER_EMPTY ((int32_t)0x5AA55AA5U) /*!< Value identifying \ref ITM_RxBuffer is ready for next character. */ + + +/** + \brief ITM Send Character + \details Transmits a character via the ITM channel 0, and + \li Just returns when no debugger is connected that has booked the output. + \li Is blocking when a debugger is connected, but the previous character sent has not been transmitted. + \param [in] ch Character to transmit. + \returns Character to transmit. + */ +__STATIC_INLINE uint32_t ITM_SendChar (uint32_t ch) +{ + if (((ITM->TCR & ITM_TCR_ITMENA_Msk) != 0UL) && /* ITM enabled */ + ((ITM->TER & 1UL ) != 0UL) ) /* ITM Port #0 enabled */ + { + while (ITM->PORT[0U].u32 == 0UL) + { + __NOP(); + } + ITM->PORT[0U].u8 = (uint8_t)ch; + } + return (ch); +} + + +/** + \brief ITM Receive Character + \details Inputs a character via the external variable \ref ITM_RxBuffer. + \return Received character. + \return -1 No character pending. + */ +__STATIC_INLINE int32_t ITM_ReceiveChar (void) +{ + int32_t ch = -1; /* no character available */ + + if (ITM_RxBuffer != ITM_RXBUFFER_EMPTY) + { + ch = ITM_RxBuffer; + ITM_RxBuffer = ITM_RXBUFFER_EMPTY; /* ready for next character */ + } + + return (ch); +} + + +/** + \brief ITM Check Character + \details Checks whether a character is pending for reading in the variable \ref ITM_RxBuffer. + \return 0 No character available. + \return 1 Character available. + */ +__STATIC_INLINE int32_t ITM_CheckChar (void) +{ + + if (ITM_RxBuffer == ITM_RXBUFFER_EMPTY) + { + return (0); /* no character available */ + } + else + { + return (1); /* character available */ + } +} + +/*@} end of CMSIS_core_DebugFunctions */ + + + + +#ifdef __cplusplus +} +#endif + +#endif /* __CORE_CM33_H_DEPENDANT */ + +#endif /* __CMSIS_GENERIC */ diff --git a/bsp/acm32f4xx-nucleo/libraries/CMSIS/mpu_armv8.h b/bsp/acm32f4xx-nucleo/libraries/CMSIS/mpu_armv8.h new file mode 100644 index 0000000000..0041d4dc6f --- /dev/null +++ b/bsp/acm32f4xx-nucleo/libraries/CMSIS/mpu_armv8.h @@ -0,0 +1,346 @@ +/****************************************************************************** + * @file mpu_armv8.h + * @brief CMSIS MPU API for Armv8-M and Armv8.1-M MPU + * @version V5.1.0 + * @date 08. March 2019 + ******************************************************************************/ +/* + * Copyright (c) 2017-2019 Arm Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#if defined ( __ICCARM__ ) + #pragma system_include /* treat file as system include file for MISRA check */ +#elif defined (__clang__) + #pragma clang system_header /* treat file as system include file */ +#endif + +#ifndef ARM_MPU_ARMV8_H +#define ARM_MPU_ARMV8_H + +/** \brief Attribute for device memory (outer only) */ +#define ARM_MPU_ATTR_DEVICE ( 0U ) + +/** \brief Attribute for non-cacheable, normal memory */ +#define ARM_MPU_ATTR_NON_CACHEABLE ( 4U ) + +/** \brief Attribute for normal memory (outer and inner) +* \param NT Non-Transient: Set to 1 for non-transient data. +* \param WB Write-Back: Set to 1 to use write-back update policy. +* \param RA Read Allocation: Set to 1 to use cache allocation on read miss. +* \param WA Write Allocation: Set to 1 to use cache allocation on write miss. +*/ +#define ARM_MPU_ATTR_MEMORY_(NT, WB, RA, WA) \ + (((NT & 1U) << 3U) | ((WB & 1U) << 2U) | ((RA & 1U) << 1U) | (WA & 1U)) + +/** \brief Device memory type non Gathering, non Re-ordering, non Early Write Acknowledgement */ +#define ARM_MPU_ATTR_DEVICE_nGnRnE (0U) + +/** \brief Device memory type non Gathering, non Re-ordering, Early Write Acknowledgement */ +#define ARM_MPU_ATTR_DEVICE_nGnRE (1U) + +/** \brief Device memory type non Gathering, Re-ordering, Early Write Acknowledgement */ +#define ARM_MPU_ATTR_DEVICE_nGRE (2U) + +/** \brief Device memory type Gathering, Re-ordering, Early Write Acknowledgement */ +#define ARM_MPU_ATTR_DEVICE_GRE (3U) + +/** \brief Memory Attribute +* \param O Outer memory attributes +* \param I O == ARM_MPU_ATTR_DEVICE: Device memory attributes, else: Inner memory attributes +*/ +#define ARM_MPU_ATTR(O, I) (((O & 0xFU) << 4U) | (((O & 0xFU) != 0U) ? (I & 0xFU) : ((I & 0x3U) << 2U))) + +/** \brief Normal memory non-shareable */ +#define ARM_MPU_SH_NON (0U) + +/** \brief Normal memory outer shareable */ +#define ARM_MPU_SH_OUTER (2U) + +/** \brief Normal memory inner shareable */ +#define ARM_MPU_SH_INNER (3U) + +/** \brief Memory access permissions +* \param RO Read-Only: Set to 1 for read-only memory. +* \param NP Non-Privileged: Set to 1 for non-privileged memory. +*/ +#define ARM_MPU_AP_(RO, NP) (((RO & 1U) << 1U) | (NP & 1U)) + +/** \brief Region Base Address Register value +* \param BASE The base address bits [31:5] of a memory region. The value is zero extended. Effective address gets 32 byte aligned. +* \param SH Defines the Shareability domain for this memory region. +* \param RO Read-Only: Set to 1 for a read-only memory region. +* \param NP Non-Privileged: Set to 1 for a non-privileged memory region. +* \oaram XN eXecute Never: Set to 1 for a non-executable memory region. +*/ +#define ARM_MPU_RBAR(BASE, SH, RO, NP, XN) \ + ((BASE & MPU_RBAR_BASE_Msk) | \ + ((SH << MPU_RBAR_SH_Pos) & MPU_RBAR_SH_Msk) | \ + ((ARM_MPU_AP_(RO, NP) << MPU_RBAR_AP_Pos) & MPU_RBAR_AP_Msk) | \ + ((XN << MPU_RBAR_XN_Pos) & MPU_RBAR_XN_Msk)) + +/** \brief Region Limit Address Register value +* \param LIMIT The limit address bits [31:5] for this memory region. The value is one extended. +* \param IDX The attribute index to be associated with this memory region. +*/ +#define ARM_MPU_RLAR(LIMIT, IDX) \ + ((LIMIT & MPU_RLAR_LIMIT_Msk) | \ + ((IDX << MPU_RLAR_AttrIndx_Pos) & MPU_RLAR_AttrIndx_Msk) | \ + (MPU_RLAR_EN_Msk)) + +#if defined(MPU_RLAR_PXN_Pos) + +/** \brief Region Limit Address Register with PXN value +* \param LIMIT The limit address bits [31:5] for this memory region. The value is one extended. +* \param PXN Privileged execute never. Defines whether code can be executed from this privileged region. +* \param IDX The attribute index to be associated with this memory region. +*/ +#define ARM_MPU_RLAR_PXN(LIMIT, PXN, IDX) \ + ((LIMIT & MPU_RLAR_LIMIT_Msk) | \ + ((PXN << MPU_RLAR_PXN_Pos) & MPU_RLAR_PXN_Msk) | \ + ((IDX << MPU_RLAR_AttrIndx_Pos) & MPU_RLAR_AttrIndx_Msk) | \ + (MPU_RLAR_EN_Msk)) + +#endif + +/** +* Struct for a single MPU Region +*/ +typedef struct { + uint32_t RBAR; /*!< Region Base Address Register value */ + uint32_t RLAR; /*!< Region Limit Address Register value */ +} ARM_MPU_Region_t; + +/** Enable the MPU. +* \param MPU_Control Default access permissions for unconfigured regions. +*/ +__STATIC_INLINE void ARM_MPU_Enable(uint32_t MPU_Control) +{ + MPU->CTRL = MPU_Control | MPU_CTRL_ENABLE_Msk; +#ifdef SCB_SHCSR_MEMFAULTENA_Msk + SCB->SHCSR |= SCB_SHCSR_MEMFAULTENA_Msk; +#endif + __DSB(); + __ISB(); +} + +/** Disable the MPU. +*/ +__STATIC_INLINE void ARM_MPU_Disable(void) +{ + __DMB(); +#ifdef SCB_SHCSR_MEMFAULTENA_Msk + SCB->SHCSR &= ~SCB_SHCSR_MEMFAULTENA_Msk; +#endif + MPU->CTRL &= ~MPU_CTRL_ENABLE_Msk; +} + +#ifdef MPU_NS +/** Enable the Non-secure MPU. +* \param MPU_Control Default access permissions for unconfigured regions. +*/ +__STATIC_INLINE void ARM_MPU_Enable_NS(uint32_t MPU_Control) +{ + MPU_NS->CTRL = MPU_Control | MPU_CTRL_ENABLE_Msk; +#ifdef SCB_SHCSR_MEMFAULTENA_Msk + SCB_NS->SHCSR |= SCB_SHCSR_MEMFAULTENA_Msk; +#endif + __DSB(); + __ISB(); +} + +/** Disable the Non-secure MPU. +*/ +__STATIC_INLINE void ARM_MPU_Disable_NS(void) +{ + __DMB(); +#ifdef SCB_SHCSR_MEMFAULTENA_Msk + SCB_NS->SHCSR &= ~SCB_SHCSR_MEMFAULTENA_Msk; +#endif + MPU_NS->CTRL &= ~MPU_CTRL_ENABLE_Msk; +} +#endif + +/** Set the memory attribute encoding to the given MPU. +* \param mpu Pointer to the MPU to be configured. +* \param idx The attribute index to be set [0-7] +* \param attr The attribute value to be set. +*/ +__STATIC_INLINE void ARM_MPU_SetMemAttrEx(MPU_Type* mpu, uint8_t idx, uint8_t attr) +{ + const uint8_t reg = idx / 4U; + const uint32_t pos = ((idx % 4U) * 8U); + const uint32_t mask = 0xFFU << pos; + + if (reg >= (sizeof(mpu->MAIR) / sizeof(mpu->MAIR[0]))) { + return; // invalid index + } + + mpu->MAIR[reg] = ((mpu->MAIR[reg] & ~mask) | ((attr << pos) & mask)); +} + +/** Set the memory attribute encoding. +* \param idx The attribute index to be set [0-7] +* \param attr The attribute value to be set. +*/ +__STATIC_INLINE void ARM_MPU_SetMemAttr(uint8_t idx, uint8_t attr) +{ + ARM_MPU_SetMemAttrEx(MPU, idx, attr); +} + +#ifdef MPU_NS +/** Set the memory attribute encoding to the Non-secure MPU. +* \param idx The attribute index to be set [0-7] +* \param attr The attribute value to be set. +*/ +__STATIC_INLINE void ARM_MPU_SetMemAttr_NS(uint8_t idx, uint8_t attr) +{ + ARM_MPU_SetMemAttrEx(MPU_NS, idx, attr); +} +#endif + +/** Clear and disable the given MPU region of the given MPU. +* \param mpu Pointer to MPU to be used. +* \param rnr Region number to be cleared. +*/ +__STATIC_INLINE void ARM_MPU_ClrRegionEx(MPU_Type* mpu, uint32_t rnr) +{ + mpu->RNR = rnr; + mpu->RLAR = 0U; +} + +/** Clear and disable the given MPU region. +* \param rnr Region number to be cleared. +*/ +__STATIC_INLINE void ARM_MPU_ClrRegion(uint32_t rnr) +{ + ARM_MPU_ClrRegionEx(MPU, rnr); +} + +#ifdef MPU_NS +/** Clear and disable the given Non-secure MPU region. +* \param rnr Region number to be cleared. +*/ +__STATIC_INLINE void ARM_MPU_ClrRegion_NS(uint32_t rnr) +{ + ARM_MPU_ClrRegionEx(MPU_NS, rnr); +} +#endif + +/** Configure the given MPU region of the given MPU. +* \param mpu Pointer to MPU to be used. +* \param rnr Region number to be configured. +* \param rbar Value for RBAR register. +* \param rlar Value for RLAR register. +*/ +__STATIC_INLINE void ARM_MPU_SetRegionEx(MPU_Type* mpu, uint32_t rnr, uint32_t rbar, uint32_t rlar) +{ + mpu->RNR = rnr; + mpu->RBAR = rbar; + mpu->RLAR = rlar; +} + +/** Configure the given MPU region. +* \param rnr Region number to be configured. +* \param rbar Value for RBAR register. +* \param rlar Value for RLAR register. +*/ +__STATIC_INLINE void ARM_MPU_SetRegion(uint32_t rnr, uint32_t rbar, uint32_t rlar) +{ + ARM_MPU_SetRegionEx(MPU, rnr, rbar, rlar); +} + +#ifdef MPU_NS +/** Configure the given Non-secure MPU region. +* \param rnr Region number to be configured. +* \param rbar Value for RBAR register. +* \param rlar Value for RLAR register. +*/ +__STATIC_INLINE void ARM_MPU_SetRegion_NS(uint32_t rnr, uint32_t rbar, uint32_t rlar) +{ + ARM_MPU_SetRegionEx(MPU_NS, rnr, rbar, rlar); +} +#endif + +/** Memcopy with strictly ordered memory access, e.g. for register targets. +* \param dst Destination data is copied to. +* \param src Source data is copied from. +* \param len Amount of data words to be copied. +*/ +__STATIC_INLINE void ARM_MPU_OrderedMemcpy(volatile uint32_t* dst, const uint32_t* __RESTRICT src, uint32_t len) +{ + uint32_t i; + for (i = 0U; i < len; ++i) + { + dst[i] = src[i]; + } +} + +/** Load the given number of MPU regions from a table to the given MPU. +* \param mpu Pointer to the MPU registers to be used. +* \param rnr First region number to be configured. +* \param table Pointer to the MPU configuration table. +* \param cnt Amount of regions to be configured. +*/ +__STATIC_INLINE void ARM_MPU_LoadEx(MPU_Type* mpu, uint32_t rnr, ARM_MPU_Region_t const* table, uint32_t cnt) +{ + const uint32_t rowWordSize = sizeof(ARM_MPU_Region_t)/4U; + if (cnt == 1U) { + mpu->RNR = rnr; + ARM_MPU_OrderedMemcpy(&(mpu->RBAR), &(table->RBAR), rowWordSize); + } else { + uint32_t rnrBase = rnr & ~(MPU_TYPE_RALIASES-1U); + uint32_t rnrOffset = rnr % MPU_TYPE_RALIASES; + + mpu->RNR = rnrBase; + while ((rnrOffset + cnt) > MPU_TYPE_RALIASES) { + uint32_t c = MPU_TYPE_RALIASES - rnrOffset; + ARM_MPU_OrderedMemcpy(&(mpu->RBAR)+(rnrOffset*2U), &(table->RBAR), c*rowWordSize); + table += c; + cnt -= c; + rnrOffset = 0U; + rnrBase += MPU_TYPE_RALIASES; + mpu->RNR = rnrBase; + } + + ARM_MPU_OrderedMemcpy(&(mpu->RBAR)+(rnrOffset*2U), &(table->RBAR), cnt*rowWordSize); + } +} + +/** Load the given number of MPU regions from a table. +* \param rnr First region number to be configured. +* \param table Pointer to the MPU configuration table. +* \param cnt Amount of regions to be configured. +*/ +__STATIC_INLINE void ARM_MPU_Load(uint32_t rnr, ARM_MPU_Region_t const* table, uint32_t cnt) +{ + ARM_MPU_LoadEx(MPU, rnr, table, cnt); +} + +#ifdef MPU_NS +/** Load the given number of MPU regions from a table to the Non-secure MPU. +* \param rnr First region number to be configured. +* \param table Pointer to the MPU configuration table. +* \param cnt Amount of regions to be configured. +*/ +__STATIC_INLINE void ARM_MPU_Load_NS(uint32_t rnr, ARM_MPU_Region_t const* table, uint32_t cnt) +{ + ARM_MPU_LoadEx(MPU_NS, rnr, table, cnt); +} +#endif + +#endif + diff --git a/bsp/acm32f4xx-nucleo/libraries/Device/ACM32F4.h b/bsp/acm32f4xx-nucleo/libraries/Device/ACM32F4.h new file mode 100644 index 0000000000..2cb6a50436 --- /dev/null +++ b/bsp/acm32f4xx-nucleo/libraries/Device/ACM32F4.h @@ -0,0 +1,848 @@ +/* + ****************************************************************************** + * @file ACM32F4.h + * @brief CMSIS ACM32F4 Device Peripheral Access Layer Header File. + * + * This file contains: + * - Data structures and the address mapping for all peripherals + * - Peripheral's registers declarations and bits definition + * - Macros to access peripherals registers hardware + * + ****************************************************************************** +*/ +#ifndef __ACM32F4_H__ +#define __ACM32F4_H__ + +#ifdef __cplusplus +extern "C" +{ +#endif + +///*------------------- Interrupt Number Definition ----------------------*/ +typedef enum IRQn +{ +/* ---------------------------------- Cortex-M33 Processor Exceptions Numbers ----------------------------------- */ + Reset_IRQn = -15, /* -15 Reset Vector, invoked on Power up and warm reset */ + NonMaskableInt_IRQn = -14, /* -14 Non maskable Interrupt, cannot be stopped or preempted */ + HardFault_IRQn = -13, /* -13 Hard Fault, all classes of Fault */ + MemoryManagement_IRQn = -12, /* -12 Memory Management, MPU mismatch, including Access Violation + and No Match */ + BusFault_IRQn = -11, /* -11 Bus Fault, Pre-Fetch-, Memory Access Fault, other address/memory + related Fault */ + UsageFault_IRQn = -10, /* -10 Usage Fault, i.e. Undef Instruction, Illegal State Transition */ + SVCall_IRQn = -5, /* -5 System Service Call via SVC instruction */ + DebugMonitor_IRQn = -4, /* -4 Debug Monitor */ + PendSV_IRQn = -2, /* -2 Pendable request for system service */ + SysTick_IRQn = -1, /* -1 System Tick Timer */ + +/* ------------------------------------- ARMCM0 Specific Interrupt Numbers -------------------------------------- */ + WDT_IRQn = 0, /* 0: WDT_IRQHandler */ + RTC_IRQn = 1, /* 1: RTC_IRQHandler */ + EFC_IRQn = 2, /* 2: EFC_IRQHandler */ + GPIOAB_IRQn = 3, /* 3: GPIOAB_IRQHandler */ + GPIOCD_IRQn = 4, /* 4: GPIOCD_IRQHandler */ + EXTI_IRQn = 5, /* 5: EXTI_IRQHandler */ + SRAM_PARITY_IRQn = 6, /* 6: SRAM_PARITY_IRQHandler */ + CLKRDY_IRQn = 7, /* 7: CLKRDY_IRQHandler */ + UART4_IRQn = 8, /* 8: UART4_IRQHandler */ + DMA_IRQn = 9, /* 9: DMA_IRQHandler */ + UART3_IRQn = 10, /* 10: UART3_IRQHandler */ + ADC_IRQn = 12, /* 12: ADC_IRQHandler */ + TIM1_BRK_UP_TRG_COM_IRQn = 13, /* 13: TIM1_BRK_UP_TRG_COM_IRQHandler */ + TIM1_CC_IRQn = 14, /* 14: TIM1_CC_IRQHandler */ + TIM2_IRQn = 15, /* 15: TIM2_IRQHandler */ + TIM3_IRQn = 16, /* 16: TIM3_IRQHandler */ + TIM6_IRQn = 17, /* 17: TIM6_IRQHandler */ + TIM7_IRQn = 18, /* 18: TIM7_IRQHandler */ + TIM14_IRQn = 19, /* 19: TIM14_IRQHandler */ + TIM15_IRQn = 20, /* 20: TIM15_IRQHandler */ + TIM16_IRQn = 21, /* 21: TIM16_IRQHandler */ + TIM17_IRQn = 22, /* 22: TIM17_IRQHandler */ + I2C1_IRQn = 23, /* 23: I2C1_IRQHandler */ + I2C2_IRQn = 24, /* 24: I2C2_IRQHandler */ + SPI1_IRQn = 25, /* 25: SPI1_IRQHandler */ + SPI2_IRQn = 26, /* 26: SPI2_IRQHandler */ + UART1_IRQn = 27, /* 27: UART1_IRQHandler */ + UART2_IRQn = 28, /* 28: UART2_IRQHandler */ + LPUART_IRQn = 29, /* 29: LPUART_IRQHandler */ + SPI3_IRQn = 30, /* 30: SPI3_IRQHandler */ + AES_IRQn = 31, /* 31: AES_IRQHandler */ + USB_IRQn = 32, /* 32: USB_IRQHandler */ + DAC_IRQn = 33, /* 33: DAC_IRQHandler */ + I2S_IRQn = 34, /* 34: I2S_IRQHandler */ + GPIOEF_IRQ = 35, /* 35: GPIOEF_IRQHandler */ + CAN1_IRQn = 36, /* 36: CAN1_IRQHandler */ + CAN2_IRQn = 37, /* 37: CAN2_IRQHandler */ + FPU_IRQn = 38, /* 38: FPU_IRQHandler */ + TIM4_IRQn = 39, /* 39: TIM4_IRQHandler */ + SPI4_IRQn = 40, /* 40: SPI4_IRQHandler */ +} IRQn_Type; + +/* ================================================================================ */ +/* ================ Processor and Core Peripheral Section ================ */ +/* ================================================================================ */ + +/* Configuration of the Cortex-M33 Processor and Core Peripherals */ +#define __MPU_PRESENT 1 /*!< mcu does not provide a MPU present or not */ +#define __NVIC_PRIO_BITS 3 /*!< mcu Supports 3 Bits for the Priority Levels */ +#define __Vendor_SysTickConfig 0 /*!< Set to 1 if different SysTick Config is used */ + +#define ARM_MATH_CM4 1 +#define __TARGET_FPU_VFP 1 +#define __FPU_PRESENT 1 +#define __DSP_PRESENT 1 +#define __ARM_COMPAT_H 1 +#define __ACCELERATE_PRESENT 1 +#define __ACCELERATE_EH_PRESENT 0 + +#include "core_cm33.h" /* Processor and core peripherals */ + +#include "stdio.h" +#include "stdint.h" +#include "stdbool.h" +#include "string.h" + +///*------------------- Bit Opertions ----------------------*/ +#define BIT0 (1U << 0) +#define BIT1 (1U << 1) +#define BIT2 (1U << 2) +#define BIT3 (1U << 3) +#define BIT4 (1U << 4) +#define BIT5 (1U << 5) +#define BIT6 (1U << 6) +#define BIT7 (1U << 7) +#define BIT8 (1U << 8) +#define BIT9 (1U << 9) +#define BIT10 (1U << 10) +#define BIT11 (1U << 11) +#define BIT12 (1U << 12) +#define BIT13 (1U << 13) +#define BIT14 (1U << 14) +#define BIT15 (1U << 15) +#define BIT16 (1U << 16) +#define BIT17 (1U << 17) +#define BIT18 (1U << 18) +#define BIT19 (1U << 19) +#define BIT20 (1U << 20) +#define BIT21 (1U << 21) +#define BIT22 (1U << 22) +#define BIT23 (1U << 23) +#define BIT24 (1U << 24) +#define BIT25 (1U << 25) +#define BIT26 (1U << 26) +#define BIT27 (1U << 27) +#define BIT28 (1U << 28) +#define BIT29 (1U << 29) +#define BIT30 (1U << 30) +#define BIT31 (1U << 31) + + +/** @Addtogroup Peripheral_Registers_Structures + * @{ + */ + +///*------------------- FLASH Registers ----------------------*/ +typedef struct +{ + __IO uint32_t CTRL; + __IO uint32_t SEC; + __IO uint32_t ADCT; + __IO uint32_t TERASE; + __IO uint32_t TPROG; + __IO uint32_t STATUS; + __IO uint32_t INTSTATUS; + __IO uint32_t INTEN; + __IO uint32_t CONFIG; + __IO uint32_t EDCTRL; + __IO uint32_t RDN0; + __IO uint32_t RDN1; + __IO uint32_t RDN2; + __IO uint32_t RDN3; + __IO uint32_t TNVS; + __IO uint32_t TMODE_SEC; + __IO uint32_t TDOUT; + __IO uint32_t TDIN; + __IO uint32_t TCTRL; +}EFC_TypeDef; + + +///*------------------- Timer Registers ----------------------*/ +typedef struct +{ + __IO uint32_t CR1; + __IO uint32_t CR2; + __IO uint32_t SMCR; + __IO uint32_t DIER; + __IO uint32_t SR; + __IO uint32_t EGR; + __IO uint32_t CCMR1; + __IO uint32_t CCMR2; + __IO uint32_t CCER; + __IO uint32_t CNT; + __IO uint32_t PSC; + __IO uint32_t ARR; + __IO uint32_t RCR; + __IO uint32_t CCR1; + __IO uint32_t CCR2; + __IO uint32_t CCR3; + __IO uint32_t CCR4; + __IO uint32_t BDTR; + __IO uint32_t DCR; + __IO uint32_t DMAR; + __IO uint32_t RSV0[4]; + __IO uint32_t AF1; + __IO uint32_t RSV1; + __IO uint32_t TISEL; + __IO uint32_t DBER; +}TIM_TypeDef; + + +///*------------------- RTCPMU Registers ----------------------*/ +typedef struct +{ + __IO uint32_t WP; + __IO uint32_t IE; + __IO uint32_t SR; + __IO uint32_t SEC; + __IO uint32_t MIN; + __IO uint32_t HOUR; + __IO uint32_t DATE; + __IO uint32_t WEEK; + __IO uint32_t MONTH; + __IO uint32_t YEAR; + __IO uint32_t ALM; + __IO uint32_t CR; + __IO uint32_t ADJUST; + __IO uint32_t RSV0[4]; + __IO uint32_t CLKSTAMP1_TIME; + __IO uint32_t CALSTAMP1_DATE; + __IO uint32_t CLKSTAMP2_TIME; + __IO uint32_t CALSTAMP2_DATE; + __IO uint32_t RSV2[7]; + __IO uint32_t BAKUP[5]; +}RTC_TypeDef; + +typedef struct +{ + __IO uint32_t CR1; + __IO uint32_t SR; + __IO uint32_t IOSEL; + __IO uint32_t IOCR; + __IO uint32_t ANACR; + __IO uint32_t CR2; +}PMU_TypeDef; + + +///*------------------- WDT Registers ----------------------*/ +typedef struct +{ + __IO uint32_t LOAD; + __IO uint32_t COUNT; + __IO uint32_t CTRL; + __IO uint32_t FEED; + __IO uint32_t INTCLRTIME; + __IO uint32_t RIS; +}WDT_TypeDef; + + +///*------------------- IWDT Registers ----------------------*/ +typedef struct +{ + __IO uint32_t CMDR; + __IO uint32_t PR; + __IO uint32_t RLR; + __IO uint32_t SR; + __IO uint32_t WINR; + __IO uint32_t WUTR; +}IWDT_TypeDef; + + +///*------------------- UART Registers ----------------------*/ +typedef struct +{ + __IO uint32_t DR; + __IO uint32_t RSR; + __IO uint32_t RSV0[4]; + __IO uint32_t FR; + __IO uint32_t RSV1; + __IO uint32_t ILPR; + __IO uint32_t IBRD; + __IO uint32_t FBRD; + __IO uint32_t LCRH; + __IO uint32_t CR; + __IO uint32_t IFLS; + __IO uint32_t IE; + __IO uint32_t RIS; + __IO uint32_t MIS; + __IO uint32_t ICR; + __IO uint32_t DMACR; + __IO uint32_t RSV2[2]; + __IO uint32_t CR2; + __IO uint32_t BCNT; +}UART_TypeDef; + + +///*------------------- I2C Registers ----------------------*/ +typedef struct +{ + __IO uint32_t SLAVE_ADDR1; + __IO uint32_t CLK_DIV; + __IO uint32_t CR; + __IO uint32_t SR; + __IO uint32_t DR; + __IO uint32_t SLAVE_ADDR2_3; + __IO uint32_t RSV[3]; + __IO uint32_t TIMEOUT; +}I2C_TypeDef; + + +///*------------------- CAN Registers ----------------------*/ +typedef struct +{ + __IO uint32_t ACR[4]; + __IO uint32_t AMR[4]; + __IO uint32_t RSV[5]; +}Filter_typedef; + +typedef union +{ + __IO uint32_t DATABUF[13]; + Filter_typedef FILTER; +}DF_typedef; + +typedef struct +{ + __IO uint32_t MOD; + __IO uint32_t CMR; + __IO uint32_t SR; + __IO uint32_t IR; + __IO uint32_t IER; + __IO uint32_t RSV0; + __IO uint32_t BTR0; + __IO uint32_t BTR1; + __IO uint32_t OCR; + __IO uint32_t RSV1; + __IO uint32_t RSV2; + __IO uint32_t ALC; + __IO uint32_t ECC; + __IO uint32_t EWLR; + __IO uint32_t RXERR; + __IO uint32_t TXERR; + __IO DF_typedef DF; + __IO uint32_t RMC; + __IO uint32_t RBSA; + __IO uint32_t CDR; + __IO uint32_t RXFIFO[64]; + __IO uint32_t TXFIFO[13]; +}CAN_TypeDef; + + +///*------------------- DAC Registers ----------------------*/ +typedef struct +{ + __IO uint32_t CR; + __IO uint32_t SWTRIGR; + __IO uint32_t DHR12R1; + __IO uint32_t DHR12L1; + __IO uint32_t DHR8R1; + __IO uint32_t DHR12R2; + __IO uint32_t DHR12L2; + __IO uint32_t DHR8R2; + __IO uint32_t DHR12RD; + __IO uint32_t DHR12LD; + __IO uint32_t DHR8RD; + __IO uint32_t DOR1; + __IO uint32_t DOR2; + __IO uint32_t SR; + __IO uint32_t CCR; + __IO uint32_t MCR; + __IO uint32_t SHSR1; + __IO uint32_t SHSR2; + __IO uint32_t SHHR; + __IO uint32_t SHRR; +}DAC_TypeDef; + + +///*------------------- LPUART Registers ----------------------*/ +typedef struct +{ + __IO uint32_t RXDR; + __IO uint32_t TXDR; + __IO uint32_t LCR; + __IO uint32_t CR; + __IO uint32_t IBAUD; + __IO uint32_t FBAUD; + __IO uint32_t IE; + __IO uint32_t SR; + __IO uint32_t ADDR; +}LPUART_TypeDef; + + +///*------------------- COMP Registers ----------------------*/ +typedef struct +{ + __IO uint32_t CR1; + __IO uint32_t CR2; + __IO uint32_t SR; +}COMP_TypeDef; + + +///*------------------- OPA Registers ----------------------*/ +typedef struct +{ + __IO uint32_t OPA1_CSR; + __IO uint32_t OPA2_CSR; + __IO uint32_t OPA3_CSR; +}OPA_TypeDef; + + +///*------------------- EXTI Registers ----------------------*/ +typedef struct +{ + __IO uint32_t IENR; + __IO uint32_t EENR; + __IO uint32_t RTENR; + __IO uint32_t FTENR; + __IO uint32_t SWIER; + __IO uint32_t PDR; + __IO uint32_t EXTICR1; + __IO uint32_t EXTICR2; +}EXTI_TypeDef; + + +///*------------------- SCU Registers ----------------------*/ +typedef struct +{ + __IO uint32_t RCR; + __IO uint32_t RSR; + __IO uint32_t IPRST2; + __IO uint32_t IPRST1; + __IO uint32_t CCR1; + __IO uint32_t CCR2; + __IO uint32_t CIR; + __IO uint32_t IPCKENR1; + __IO uint32_t IPCKENR2; + __IO uint32_t RCHCR; + __IO uint32_t XTHCR; + __IO uint32_t PLLCR; + __IO uint32_t LDOCR; + __IO uint32_t RSV0; + __IO uint32_t WMR; + __IO uint32_t CLKOCR; + __IO uint32_t VER; + __IO uint32_t SYSCFG1; + __IO uint32_t LVDCFG; + __IO uint32_t STOPCFG; + __IO uint32_t RSV1; + __IO uint32_t PHYCR; + __IO uint32_t MEMCFG; + __IO uint32_t DUMMY; + __IO uint32_t PASEL1; + __IO uint32_t PASEL2; + __IO uint32_t PBSEL1; + __IO uint32_t PBSEL2; + __IO uint32_t PABPUR; + __IO uint32_t PABPDR; + __IO uint32_t PASTR; + __IO uint32_t PBSTR; + __IO uint32_t PABSMTR; + __IO uint32_t PABODR; + __IO uint32_t PABADS; + __IO uint32_t RSV2; + __IO uint32_t PCSEL1; + __IO uint32_t PCSEL2; + __IO uint32_t PDSEL1; + __IO uint32_t PDSEL2; + __IO uint32_t PCDPUR; + __IO uint32_t PCDPDR; + __IO uint32_t PCSTR; + __IO uint32_t PDSTR; + __IO uint32_t PCDSMTR; + __IO uint32_t PCDODR; + __IO uint32_t PCDADS; + __IO uint32_t RSV3; + __IO uint32_t PESEL1; + __IO uint32_t PESEL2; + __IO uint32_t PFSEL1; + __IO uint32_t RSV4; + __IO uint32_t PEFPUR; + __IO uint32_t PEFPDR; + __IO uint32_t PESTR; + __IO uint32_t PFSTR; + __IO uint32_t PEFSMTR; + __IO uint32_t PEFODR; + __IO uint32_t PEFADS; +}SCU_TypeDef; + + +///*------------------- CRC Registers ----------------------*/ +typedef struct +{ + __IO uint32_t DATA; + __IO uint32_t CTRL; + __IO uint32_t INIT; + __IO uint32_t RSV0; + __IO uint32_t OUTXOR; + __IO uint32_t POLY; + __IO uint32_t FDATA; +}CRC_TypeDef; + + +///*------------------- ADC Registers ----------------------*/ +typedef struct +{ + __IO uint32_t SR; + __IO uint32_t IE; + __IO uint32_t CR1; + __IO uint32_t CR2; + __IO uint32_t SMPR1; + __IO uint32_t SMPR2; + __IO uint32_t HTR; + __IO uint32_t LTR; + __IO uint32_t SQR1; + __IO uint32_t SQR2; + __IO uint32_t SQR3; + __IO uint32_t JSQR; + __IO uint32_t JDR; + __IO uint32_t DR; + __IO uint32_t DIFF; + __IO uint32_t SIGN; + __IO uint32_t TSREF; + __IO uint32_t SMPR3; +}ADC_TypeDef; + + +///*------------------- I2S Registers ----------------------*/ +typedef struct +{ + __IO uint32_t DAT; + __IO uint32_t CTL; + __IO uint32_t PSC; + __IO uint32_t IE; + __IO uint32_t STATUS; +}I2S_TypeDef; + + +///*------------------- GPIO Registers ----------------------*/ +typedef struct +{ + __IO uint32_t DIR; + __IO uint32_t RSV0; + __IO uint32_t SET; + __IO uint32_t CLR; + __IO uint32_t ODATA; + __IO uint32_t IDATA; + __IO uint32_t IEN; + __IO uint32_t IS; + __IO uint32_t IBE; + __IO uint32_t IEV; + __IO uint32_t IC; + __IO uint32_t RIS; + __IO uint32_t MIS; +}GPIO_TypeDef; + + +///*------------------- SPI Registers ----------------------*/ +typedef struct +{ + __IO uint32_t DAT; + __IO uint32_t BAUD; + __IO uint32_t CTL; + __IO uint32_t TX_CTL; + __IO uint32_t RX_CTL; + __IO uint32_t IE; + __IO uint32_t STATUS; + __IO uint32_t TX_DELAY; + __IO uint32_t BATCH; + __IO uint32_t CS; + __IO uint32_t OUT_EN; + __IO uint32_t MEMO_ACC; + __IO uint32_t CMD; + __IO uint32_t PARA; +}SPI_TypeDef; + + +///*------------------- DMA Registers ----------------------*/ +typedef struct +{ + __IO uint32_t INT_STATUS; + __IO uint32_t INT_TC_STATUS; + __IO uint32_t INT_TC_CLR; + __IO uint32_t INT_ERR_STATUS; + __IO uint32_t INT_ERR_CLR; + __IO uint32_t RAW_INT_TC_STATUS; + __IO uint32_t RAW_INT_ERR_STATUS; + __IO uint32_t EN_CH_STATUS; + __IO uint32_t RSV0[4]; + __IO uint32_t CONFIG; + __IO uint32_t SYNCLO; + __IO uint32_t SYNCHI; +}DMA_TypeDef; + +typedef struct +{ + __IO uint32_t SRC_ADDR; + __IO uint32_t DEST_ADDR; + __IO uint32_t LLI; + __IO uint32_t CTRL; + __IO uint32_t CONFIG; +}DMA_Channel_TypeDef; + + +///*------------------- AES Registers ----------------------*/ +typedef struct +{ + __IO uint32_t DATAIN; + __IO uint32_t KEYIN; + __IO uint32_t RSV0; + __IO uint32_t CONTROL; + __IO uint32_t STATE; + __IO uint32_t DATAOUT; +}AES_TypeDef; + + +///*------------------- FAU Registers ----------------------*/ +typedef struct +{ + __IO uint32_t CTRL1; //0x00 + __IO uint32_t STAUTS; //0x04 + + __IO uint32_t CORDIC_X_DATAIN; //0x08 + __IO uint32_t CORDIC_Y_DATAIN; //0x0c + __IO uint32_t RESULT1; //0x10 + __IO uint32_t RESULT2; //0x14 +}FAU_TypeDef; + + +///*------------------- HRNG Registers ----------------------*/ +typedef struct +{ + __IO uint32_t CTRL; + __IO uint32_t LFSR; +}HRNG_TypeDef; + + +///*------------------- HASH Registers ----------------------*/ +typedef struct +{ + __IO uint32_t DATAIN; + __IO uint32_t MIDDATA; + __IO uint32_t CTRL; + __IO uint32_t DATAOUT; +}HASH_TypeDef; + + +///*------------------- USB Registers ----------------------*/ +typedef struct +{ + __IO uint32_t WORKING_MODE; + __IO uint32_t EPxCSR[5]; + __IO uint32_t USB_ADDR; + __IO uint32_t SETIP_0_3_DATA; + __IO uint32_t SETIP_4_7_DATA; + __IO uint32_t EPADDR_CFG; + __IO uint32_t CURRENT_PID; + __IO uint32_t CURRENT_FRAME_NUMBER; + __IO uint32_t CRC_ERROR_CNT; + __IO uint32_t USB_STATUS_DETECT_CNT; + __IO uint32_t RSV0; + __IO uint32_t RSV1; + __IO uint32_t EPxSENDBN[5]; +}USB_CTRLTypeDef; + +///*------------------- USB interrupt access Registers ----------------------*/ +typedef struct +{ + __IO uint32_t INT_STAT_RAW; + __IO uint32_t INT_EN; + __IO uint32_t RSV; + __IO uint32_t INT_CLR; +}USB_INTTypeDef; + +/** + * @} + */ + + + +/** @addtogroup Peripheral_memory_map + * @{ + */ + +///*------------------- Peripheral memory map ----------------------*/ +#define EFLASH_BASE (0x00000000UL) +#define SRAM_BASE (0x20000000UL) +#define PERIPH_BASE (0x40000000UL) +#define QSPI_BASE (0x90000000UL) + +#define APB1PERIPH_BASE (PERIPH_BASE) +#define APB2PERIPH_BASE (PERIPH_BASE + 0x00010000UL) +#define AHBPERIPH_BASE (PERIPH_BASE + 0x00020000UL) + +///*---------------------- EFC peripherals ------------------------*/ +#define EFLASH_REG_BASE (EFLASH_BASE + 0x00100000) + +///*---------------------- APB1 peripherals ------------------------*/ +#define TIM2_BASE (APB1PERIPH_BASE + 0x00000000UL) +#define TIM3_BASE (APB1PERIPH_BASE + 0x00000400UL) +#define TIM4_BASE (APB1PERIPH_BASE + 0x00000800UL) +#define TIM6_BASE (APB1PERIPH_BASE + 0x00001000UL) +#define TIM7_BASE (APB1PERIPH_BASE + 0x00001400UL) +#define TIM14_BASE (APB1PERIPH_BASE + 0x00002000UL) +#define PMU_BASE (APB1PERIPH_BASE + 0x00002400UL) +#define RTC_BASE (APB1PERIPH_BASE + 0x00002800UL) +#define WDT_BASE (APB1PERIPH_BASE + 0x00002C00UL) +#define IWDT_BASE (APB1PERIPH_BASE + 0x00003000UL) +#define UART2_BASE (APB1PERIPH_BASE + 0x00004400UL) +#define UART3_BASE (APB1PERIPH_BASE + 0x00004800UL) +#define UART4_BASE (APB1PERIPH_BASE + 0x00004C00UL) +#define I2C1_BASE (APB1PERIPH_BASE + 0x00005400UL) +#define I2C2_BASE (APB1PERIPH_BASE + 0x00005800UL) +#define CAN1_BASE (APB1PERIPH_BASE + 0x00006400UL) +#define CAN2_BASE (APB1PERIPH_BASE + 0x00006800UL) +#define DAC_BASE (APB1PERIPH_BASE + 0x00007400UL) +#define LPUART_BASE (APB1PERIPH_BASE + 0x00008000UL) + +///*---------------------- APB2 peripherals ------------------------*/ +#define COMP_BASE (APB2PERIPH_BASE + 0x00000200UL) +#define OPA_BASE (APB2PERIPH_BASE + 0x00000300UL) +#define EXTI_BASE (APB2PERIPH_BASE + 0x00000400UL) +#define SCU_BASE (APB2PERIPH_BASE + 0x00000800UL) +#define CRC_BASE (APB2PERIPH_BASE + 0x00000C00UL) +#define ADC_BASE (APB2PERIPH_BASE + 0x00002400UL) +#define TIM1_BASE (APB2PERIPH_BASE + 0x00002C00UL) +#define I2S1_BASE (APB2PERIPH_BASE + 0x00003000UL) +#define UART1_BASE (APB2PERIPH_BASE + 0x00003800UL) +#define TIM15_BASE (APB2PERIPH_BASE + 0x00004000UL) +#define TIM16_BASE (APB2PERIPH_BASE + 0x00004400UL) +#define TIM17_BASE (APB2PERIPH_BASE + 0x00004800UL) +#define GPIOAB_BASE (APB2PERIPH_BASE + 0x0000F000UL) +#define GPIOCD_BASE (APB2PERIPH_BASE + 0x0000F400UL) +#define GPIOEF_BASE (APB2PERIPH_BASE + 0x0000F800UL) + +///*---------------------- AHB peripherals ------------------------*/ +#define SPI1_BASE (AHBPERIPH_BASE) +#define SPI2_BASE (AHBPERIPH_BASE + 0x00000400UL) +#define SPI3_BASE (AHBPERIPH_BASE + 0x00000800UL) +#define SPI4_BASE (AHBPERIPH_BASE + 0x00000C00UL) +#define DMA_BASE (AHBPERIPH_BASE + 0x00001000UL) +#define DMA_Channel0_BASE (AHBPERIPH_BASE + 0x00001100UL) +#define DMA_Channel1_BASE (AHBPERIPH_BASE + 0x00001120UL) +#define DMA_Channel2_BASE (AHBPERIPH_BASE + 0x00001140UL) +#define DMA_Channel3_BASE (AHBPERIPH_BASE + 0x00001160UL) +#define DMA_Channel4_BASE (AHBPERIPH_BASE + 0x00001180UL) +#define DMA_Channel5_BASE (AHBPERIPH_BASE + 0x000011A0UL) +#define DMA_Channel6_BASE (AHBPERIPH_BASE + 0x000011C0UL) +#define DMA_Channel7_BASE (AHBPERIPH_BASE + 0x000011E0UL) +#define AES_BASE (AHBPERIPH_BASE + 0x00010000UL) +#define FAU_BASE (AHBPERIPH_BASE + 0x00010400UL) +#define HRNG_BASE (AHBPERIPH_BASE + 0x00010800UL) +#define HASH_BASE (AHBPERIPH_BASE + 0x00010C00UL) +#define USB_BASE (AHBPERIPH_BASE + 0x00020000UL) + +///*---------------------- QSPI Memory ------------------------*/ +#define QSPI3_BASE (QSPI_BASE) + +/** + * @} + */ + + + +/** @addtogroup Peripheral_declaration + * @{ + */ +#define EFC ((EFC_TypeDef *)EFLASH_REG_BASE) +#define TIM2 ((TIM_TypeDef *)TIM2_BASE) +#define TIM3 ((TIM_TypeDef *)TIM3_BASE) +#define TIM4 ((TIM_TypeDef *)TIM4_BASE) +#define TIM6 ((TIM_TypeDef *)TIM6_BASE) +#define TIM7 ((TIM_TypeDef *)TIM7_BASE) +#define TIM14 ((TIM_TypeDef *)TIM14_BASE) +#define PMU ((PMU_TypeDef *)PMU_BASE) +#define RTC ((RTC_TypeDef *)RTC_BASE) +#define WDT ((WDT_TypeDef *)WDT_BASE) +#define IWDT ((IWDT_TypeDef *)IWDT_BASE) +#define UART2 ((UART_TypeDef *)UART2_BASE) +#define UART3 ((UART_TypeDef *)UART3_BASE) +#define UART4 ((UART_TypeDef *)UART4_BASE) +#define I2C1 ((I2C_TypeDef *)I2C1_BASE) +#define I2C2 ((I2C_TypeDef *)I2C2_BASE) +#define CAN1 ((CAN_TypeDef *)CAN1_BASE) +#define CAN2 ((CAN_TypeDef *)CAN2_BASE) +#define DAC ((DAC_TypeDef *)DAC_BASE) +#define LPUART ((LPUART_TypeDef *)LPUART_BASE) +#define COMP ((COMP_TypeDef *)COMP_BASE) +#define OPA ((OPA_TypeDef *)OPA_BASE) +#define EXTI ((EXTI_TypeDef *)EXTI_BASE) +#define SCU ((SCU_TypeDef *)SCU_BASE) +#define CRC ((CRC_TypeDef *)CRC_BASE) +#define ADC ((ADC_TypeDef *)ADC_BASE) +#define TIM1 ((TIM_TypeDef *)TIM1_BASE) +#define I2S1 ((I2S_TypeDef *)I2S1_BASE) +#define UART1 ((UART_TypeDef *)UART1_BASE) +#define TIM15 ((TIM_TypeDef *)TIM15_BASE) +#define TIM16 ((TIM_TypeDef *)TIM16_BASE) +#define TIM17 ((TIM_TypeDef *)TIM17_BASE) +#define GPIOAB ((GPIO_TypeDef *)GPIOAB_BASE) +#define GPIOCD ((GPIO_TypeDef *)GPIOCD_BASE) +#define GPIOEF ((GPIO_TypeDef *)GPIOEF_BASE) +#define SPI1 ((SPI_TypeDef *)SPI1_BASE) +#define SPI2 ((SPI_TypeDef *)SPI2_BASE) +#define SPI3 ((SPI_TypeDef *)SPI3_BASE) +#define SPI4 ((SPI_TypeDef *)SPI4_BASE) +#define DMA ((DMA_TypeDef *)DMA_BASE) +#define DMA_Channel0 ((DMA_Channel_TypeDef *)DMA_Channel0_BASE) +#define DMA_Channel1 ((DMA_Channel_TypeDef *)DMA_Channel1_BASE) +#define DMA_Channel2 ((DMA_Channel_TypeDef *)DMA_Channel2_BASE) +#define DMA_Channel3 ((DMA_Channel_TypeDef *)DMA_Channel3_BASE) +#define DMA_Channel4 ((DMA_Channel_TypeDef *)DMA_Channel4_BASE) +#define DMA_Channel5 ((DMA_Channel_TypeDef *)DMA_Channel5_BASE) +#define DMA_Channel6 ((DMA_Channel_TypeDef *)DMA_Channel6_BASE) +#define DMA_Channel7 ((DMA_Channel_TypeDef *)DMA_Channel7_BASE) +#define AES ((AES_TypeDef *)AES_BASE) +#define FAU ((FAU_TypeDef *)FAU_BASE) +#define HRNG ((HRNG_TypeDef *)HRNG_BASE) +#define HASH ((HASH_TypeDef *)HASH_BASE) +#define USBCTRL ((USB_CTRLTypeDef *)USB_BASE) +#define USBINT ((USB_INTTypeDef *)(USB_BASE+0xFFE4)) +/** + * @} + */ + + +/** @addtogroup Exported_macros + * @{ + */ +#define SET_BIT(REG, BIT) ((REG) |= (BIT)) + +#define CLEAR_BIT(REG, BIT) ((REG) &= ~(BIT)) + +#define READ_BIT(REG, BIT) ((REG) & (BIT)) + +#define CLEAR_REG(REG) ((REG) = (0x0)) + +#define WRITE_REG(REG, VAL) ((REG) = (VAL)) + +#define READ_REG(REG) ((REG)) + +#define MODIFY_REG(REG,MASK,BITS) ((REG) = (((REG)&(~(MASK)))|((BITS)&(MASK)))) + +typedef signed char INT8; +typedef signed short int INT16; +typedef signed int INT32; + + /* exact-width unsigned integer types */ +typedef unsigned char UINT8; +typedef unsigned short int UINT16; +typedef unsigned int UINT32; + +/** + * @} + */ + +#ifdef __cplusplus +} +#endif + +#endif /* ACM32F4_H */ diff --git a/bsp/acm32f4xx-nucleo/libraries/Device/Startup_ACM32F4.s b/bsp/acm32f4xx-nucleo/libraries/Device/Startup_ACM32F4.s new file mode 100644 index 0000000000..873e37e017 --- /dev/null +++ b/bsp/acm32f4xx-nucleo/libraries/Device/Startup_ACM32F4.s @@ -0,0 +1,271 @@ +;* File Name : Startup_ACM32F4.s +;* Version : V1.0.0 +;* Date : 2020 +;* Description : ACM32F4 Devices vector table for MDK-ARM toolchain. +;* This module performs: +;* - Set the initial SP +;* - Set the initial PC == Reset_Handler +;* - Set the vector table entries with the exceptions ISR address +;* - Configure the clock system +;* - Branches to __main in the C library (which eventually +;* calls main()). +;* After Reset the Cortex-M33 processor is in Thread mode, +;* priority is Privileged, and the Stack is set to Main. +;******************************************************************************** +;* @attention +;* +;* All rights reserved. +;******************************************************************************* + +Stack_Size EQU 0x00000800 +Heap_Size EQU 0x00000000 + + AREA STACK, NOINIT, READWRITE, ALIGN=3 +Stack_Mem SPACE Stack_Size +__initial_sp + + AREA HEAP, NOINIT, READWRITE, ALIGN=3 +__heap_base +Heap_Mem SPACE Heap_Size +__heap_limit + + PRESERVE8 + THUMB + +; Vector Table Mapped to Address 0 at Reset + + AREA RESET, DATA, READONLY + EXPORT __Vectors + +__Vectors + DCD __initial_sp ; Top of Stack + DCD Reset_Handler ; Reset Handler + DCD NMI_Handler ; NMI Handler + DCD HardFault_Handler ; Hard Fault Handler + DCD MemManage_Handler ; MPU Fault Handler + DCD BusFault_Handler ; Bus Fault Handler + DCD UsageFault_Handler ; Usage Fault Handler + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD SVC_Handler ; SVCall Handler + DCD DebugMon_Handler ; Debug Monitor Handler + DCD 0 ; Reserved + DCD PendSV_Handler ; PendSV Handler + DCD SysTick_Handler ; SysTick Handler + + ; External Interrupts + DCD WDT_IRQHandler ; 0: WDT_IRQHandler + DCD RTC_IRQHandler ; 1: RTC_IRQHandler + DCD EFC_IRQHandler ; 2: EFC_IRQHandler + DCD GPIOAB_IRQHandler ; 3: GPIOAB_IRQHandler + DCD GPIOCD_IRQHandler ; 4: GPIOCD_IRQHandler + DCD EXTI_IRQHandler ; 5: EXTI_IRQHandler + DCD SRAM_PARITY_IRQHandler ; 6: SRAM_PARITY_IRQHandler + DCD CLKRDY_IRQHandler ; 7: CLKRDY_IRQHandler + DCD UART4_IRQHandler ; 8: UART4_IRQHandler + DCD DMA_IRQHandler ; 9: DMA_IRQHandler + DCD UART3_IRQHandler ; 10: UART3_IRQHandler + DCD RSV_IRQHandler ; 11: RSV + DCD ADC_IRQHandler ; 12: ADC_IRQHandler + DCD TIM1_BRK_UP_TRG_COM_IRQHandler ; 13: TIM1_BRK_UP_TRG_COM_IRQHandler + DCD TIM1_CC_IRQHandler ; 14: TIM1_CC_IRQHandler + DCD TIM2_IRQHandler ; 15: TIM2_IRQHandler + DCD TIM3_IRQHandler ; 16: TIM3_IRQHandler + DCD TIM6_IRQHandler ; 17: TIM6_IRQHandler + DCD TIM7_IRQHandler ; 18: TIM7_IRQHandler + DCD TIM14_IRQHandler ; 19: TIM14_IRQHandler + DCD TIM15_IRQHandler ; 20: TIM15_IRQHandler + DCD TIM16_IRQHandler ; 21: TIM16_IRQHandler + DCD TIM17_IRQHandler ; 22: TIM17_IRQHandler + DCD I2C1_IRQHandler ; 23: I2C1_IRQHandler + DCD I2C2_IRQHandler ; 24: I2C2_IRQHandler + DCD SPI1_IRQHandler ; 25: SPI1_IRQHandler + DCD SPI2_IRQHandler ; 26: SPI2_IRQHandler + DCD UART1_IRQHandler ; 27: UART1_IRQHandler + DCD UART2_IRQHandler ; 28: UART2_IRQHandler + DCD LPUART_IRQHandler ; 29: LPUART_IRQHandler + DCD SPI3_IRQHandler ; 30: SPI3_IRQHandler + DCD AES_IRQHandler ; 31: AES_IRQHandler + DCD USB_IRQHandler ; 32: USB_IRQHandler + DCD DAC_IRQHandler ; 33: DAC_IRQHandler + DCD I2S_IRQHandler ; 34: I2S_IRQHandler + DCD GPIOEF_IRQHandler ; 35: GPIOEF_IRQHandler + DCD CAN1_IRQHandler ; 36: CAN1_IRQHandler + DCD CAN2_IRQHandler ; 37: CAN2_IRQHandler + DCD FPU_IRQHandler ; 38: FPU_IRQHandler + DCD TIM4_IRQHandler ; 39: TIM4_IRQHandler + DCD SPI4_IRQHandler ; 40: SPI4_IRQHandler + AREA |.text|, CODE, READONLY + +Reset_Handler PROC + EXPORT Reset_Handler [WEAK] + IMPORT System_Core_Config + IMPORT __main + LDR R0, =System_Core_Config + BLX R0 + LDR R0, =__main + BX R0 + ENDP + + +NMI_Handler PROC + EXPORT NMI_Handler [WEAK] + B . + ENDP +HardFault_Handler\ + PROC + EXPORT HardFault_Handler [WEAK] + B . + ENDP +MemManage_Handler\ + PROC + EXPORT MemManage_Handler [WEAK] + B . + ENDP +BusFault_Handler\ + PROC + EXPORT BusFault_Handler [WEAK] + B . + ENDP +UsageFault_Handler\ + PROC + EXPORT UsageFault_Handler [WEAK] + B . + ENDP +SVC_Handler PROC + EXPORT SVC_Handler [WEAK] + B . + ENDP +DebugMon_Handler\ + PROC + EXPORT DebugMon_Handler [WEAK] + B . + ENDP +PendSV_Handler PROC + EXPORT PendSV_Handler [WEAK] + B . + ENDP +SysTick_Handler PROC + EXPORT SysTick_Handler [WEAK] + B . + ENDP + +Default_Handler PROC + EXPORT WDT_IRQHandler [WEAK] + EXPORT RTC_IRQHandler [WEAK] + EXPORT EFC_IRQHandler [WEAK] + EXPORT GPIOAB_IRQHandler [WEAK] + EXPORT GPIOCD_IRQHandler [WEAK] + EXPORT EXTI_IRQHandler [WEAK] + EXPORT SRAM_PARITY_IRQHandler [WEAK] + EXPORT CLKRDY_IRQHandler [WEAK] + EXPORT UART4_IRQHandler [WEAK] + EXPORT DMA_IRQHandler [WEAK] + EXPORT UART3_IRQHandler [WEAK] + EXPORT RSV_IRQHandler [WEAK] + EXPORT ADC_IRQHandler [WEAK] + EXPORT TIM1_BRK_UP_TRG_COM_IRQHandler [WEAK] + EXPORT TIM1_CC_IRQHandler [WEAK] + EXPORT TIM2_IRQHandler [WEAK] + EXPORT TIM3_IRQHandler [WEAK] + EXPORT TIM6_IRQHandler [WEAK] + EXPORT TIM7_IRQHandler [WEAK] + EXPORT TIM14_IRQHandler [WEAK] + EXPORT TIM15_IRQHandler [WEAK] + EXPORT TIM16_IRQHandler [WEAK] + EXPORT TIM17_IRQHandler [WEAK] + EXPORT I2C1_IRQHandler [WEAK] + EXPORT I2C2_IRQHandler [WEAK] + EXPORT SPI1_IRQHandler [WEAK] + EXPORT SPI2_IRQHandler [WEAK] + EXPORT UART1_IRQHandler [WEAK] + EXPORT UART2_IRQHandler [WEAK] + EXPORT LPUART_IRQHandler [WEAK] + EXPORT SPI3_IRQHandler [WEAK] + EXPORT AES_IRQHandler [WEAK] + EXPORT USB_IRQHandler [WEAK] + EXPORT RSV_IRQHandler [WEAK] + EXPORT DAC_IRQHandler [WEAK] + EXPORT I2S_IRQHandler [WEAK] + EXPORT GPIOEF_IRQHandler [WEAK] + EXPORT CAN1_IRQHandler [WEAK] + EXPORT CAN2_IRQHandler [WEAK] + EXPORT FPU_IRQHandler [WEAK] + EXPORT TIM4_IRQHandler [WEAK] + EXPORT SPI4_IRQHandler [WEAK] +WDT_IRQHandler +RTC_IRQHandler +EFC_IRQHandler +GPIOAB_IRQHandler +GPIOCD_IRQHandler +EXTI_IRQHandler +SRAM_PARITY_IRQHandler +CLKRDY_IRQHandler +UART4_IRQHandler +DMA_IRQHandler +UART3_IRQHandler +ADC_IRQHandler +TIM1_BRK_UP_TRG_COM_IRQHandler +TIM1_CC_IRQHandler +TIM2_IRQHandler +TIM3_IRQHandler +TIM6_IRQHandler +TIM7_IRQHandler +TIM14_IRQHandler +TIM15_IRQHandler +TIM16_IRQHandler +TIM17_IRQHandler +I2C1_IRQHandler +I2C2_IRQHandler +SPI1_IRQHandler +SPI2_IRQHandler +UART1_IRQHandler +UART2_IRQHandler +LPUART_IRQHandler +SPI3_IRQHandler +AES_IRQHandler +USB_IRQHandler +RSV_IRQHandler +DAC_IRQHandler +I2S_IRQHandler +GPIOEF_IRQHandler +CAN1_IRQHandler +CAN2_IRQHandler +FPU_IRQHandler +TIM4_IRQHandler +SPI4_IRQHandler + + B . + + ENDP + + ALIGN +;******************************************************************************* +; User Stack and Heap initialization +;******************************************************************************* + + IF :DEF:__MICROLIB + + EXPORT __initial_sp + EXPORT __heap_base + EXPORT __heap_limit + + ELSE + + IMPORT __use_two_region_memory + EXPORT __user_initial_stackheap +__user_initial_stackheap + + LDR R0, = Heap_Mem + LDR R1, =(Stack_Mem + Stack_Size) + LDR R2, = (Heap_Mem + Heap_Size) + LDR R3, = Stack_Mem + BX LR + + ALIGN + + ENDIF + + END diff --git a/bsp/acm32f4xx-nucleo/libraries/Device/Startup_ACM32F4_iar.s b/bsp/acm32f4xx-nucleo/libraries/Device/Startup_ACM32F4_iar.s new file mode 100644 index 0000000000..414c6ac6aa --- /dev/null +++ b/bsp/acm32f4xx-nucleo/libraries/Device/Startup_ACM32F4_iar.s @@ -0,0 +1,362 @@ +;******************************************************************************** +;* File Name : Startup_ACM32F4.s +;* Description : This module performs: +;* - Set the initial SP +;* - Set the initial PC == _iar_program_start, +;* - Set the vector table entries with the exceptions ISR +;* address. +;* - Branches to main in the C library (which eventually +;* calls main()). +;* After Reset the Cortex-M33 processor is in Thread mode, +;* priority is Privileged, and the Stack is set to Main. +;******************************************************************************** +;* +;*

© Copyright (c) 2021 Aisinochip. +;* All rights reserved.

+;* +;******************************************************************************* + + + MODULE ?cstartup + + ;; Forward declaration of sections. + SECTION CSTACK:DATA:NOROOT(3) + + SECTION .intvec:CODE:NOROOT(2) + + EXTERN __iar_program_start + PUBLIC __vector_table + PUBLIC __Vectors + PUBLIC __Vectors_End + PUBLIC __Vectors_Size + + DATA +__vector_table + DCD sfe(CSTACK) + DCD Reset_Handler ; Reset Handler + DCD NMI_Handler ; NMI Handler + DCD HardFault_Handler ; Hard Fault Handler + DCD MemManage_Handler ; MPU Fault Handler + DCD BusFault_Handler ; Bus Fault Handler + DCD UsageFault_Handler ; Usage Fault Handler + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD SVC_Handler ; SVCall Handler + DCD DebugMon_Handler ; Debug Monitor Handler + DCD 0 ; Reserved + DCD PendSV_Handler ; PendSV Handler + DCD SysTick_Handler ; SysTick Handler + + ; External Interrupts + DCD WDT_IRQHandler ; WDT_IRQHandle + DCD RTC_IRQHandler ; RTC_IRQHandler + DCD EFC_IRQHandler ; EFC_IRQHandler + DCD GPIOAB_IRQHandler ; GPIOAB_IRQHandler + DCD GPIOCD_IRQHandler ; GPIOCD_IRQHandler + DCD EXTI_IRQHandler ; EXTI_IRQHandler + DCD SRAM_PARITY_IRQHandler ; SRAM_PARITY_IRQHandler + DCD CLKRDY_IRQHandler ; CLKRDY_IRQHandler + DCD UART4_IRQHandler ; UART4_IRQHandler + DCD DMA_IRQHandler ; DMA_IRQHandler + DCD UART3_IRQHandler ; UART3_IRQHandler + DCD RSV_IRQHandler ; RSV_IRQHandler + DCD ADC_IRQHandler ; ADC_IRQHandler + DCD TIM1_BRK_UP_TRG_COM_IRQHandler ; TIM1_BRK_UP_TRG_COM_IRQHandler + DCD TIM1_CC_IRQHandler ; TIM1_CC_IRQHandler + DCD TIM2_IRQHandler ; TIM2_IRQHandler + DCD TIM3_IRQHandler ; TIM3_IRQHandler + DCD TIM6_IRQHandler ; TIM6_IRQHandler + DCD TIM7_IRQHandler ; TIM7_IRQHandler + DCD TIM14_IRQHandler ; TIM14_IRQHandler + DCD TIM15_IRQHandler ; TIM15_IRQHandler + DCD TIM16_IRQHandler ; TIM16_IRQHandler + DCD TIM17_IRQHandler ; TIM17_IRQHandler + DCD I2C1_IRQHandler ; I2C1_IRQHandler + DCD I2C2_IRQHandler ; I2C2_IRQHandler + DCD SPI1_IRQHandler ; SPI1_IRQHandler + DCD SPI2_IRQHandler ; SPI2_IRQHandler + DCD UART1_IRQHandler ; UART1_IRQHandler + DCD UART2_IRQHandler ; UART2_IRQHandler + DCD LPUART_IRQHandler ; LPUART_IRQHandler + DCD SPI3_IRQHandler ; SPI3_IRQHandler + DCD AES_IRQHandler ; AES_IRQHandler + DCD USB_IRQHandler ; USB_IRQHandler + DCD DAC_IRQHandler ; DAC_IRQHandler + DCD I2S_IRQHandler ; I2S_IRQHandler + DCD GPIOEF_IRQHandler ; GPIOEF_IRQHandler + DCD CAN1_IRQHandler ; CAN1_IRQHandler + DCD CAN2_IRQHandler ; CAN2_IRQHandler + DCD FPU_IRQHandler ; FPU_IRQHandler + DCD TIM4_IRQHandler ; TIM4_IRQHandler + DCD SPI4_IRQHandler ; SPI4_IRQHandler +__Vectors_End + +__Vectors EQU __vector_table +__Vectors_Size EQU __Vectors_End - __Vectors + +;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; +;; +;; Default interrupt handlers. +;; + THUMB + PUBWEAK Reset_Handler + SECTION .text:CODE:NOROOT:REORDER(2) +Reset_Handler + LDR R0, =__iar_program_start + BX R0 + + PUBWEAK NMI_Handler + SECTION .text:CODE:NOROOT:REORDER(1) +NMI_Handler + B NMI_Handler + + PUBWEAK HardFault_Handler + SECTION .text:CODE:NOROOT:REORDER(1) +HardFault_Handler + B HardFault_Handler + + PUBWEAK MemManage_Handler + SECTION .text:CODE:NOROOT:REORDER(1) +MemManage_Handler + B MemManage_Handler + + PUBWEAK BusFault_Handler + SECTION .text:CODE:NOROOT:REORDER(1) +BusFault_Handler + B BusFault_Handler + + PUBWEAK UsageFault_Handler + SECTION .text:CODE:NOROOT:REORDER(1) +UsageFault_Handler + B UsageFault_Handler + + PUBWEAK SVC_Handler + SECTION .text:CODE:NOROOT:REORDER(1) +SVC_Handler + B SVC_Handler + + PUBWEAK DebugMon_Handler + SECTION .text:CODE:NOROOT:REORDER(1) +DebugMon_Handler + B DebugMon_Handler + + PUBWEAK PendSV_Handler + SECTION .text:CODE:NOROOT:REORDER(1) +PendSV_Handler + B PendSV_Handler + + PUBWEAK SysTick_Handler + SECTION .text:CODE:NOROOT:REORDER(1) +SysTick_Handler + B SysTick_Handler + + PUBWEAK WDT_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +WDT_IRQHandler + B WDT_IRQHandler + + PUBWEAK RTC_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +RTC_IRQHandler + B RTC_IRQHandler + + PUBWEAK EFC_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +EFC_IRQHandler + B EFC_IRQHandler + + PUBWEAK GPIOAB_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +GPIOAB_IRQHandler + B GPIOAB_IRQHandler + + PUBWEAK GPIOCD_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +GPIOCD_IRQHandler + B GPIOCD_IRQHandler + + PUBWEAK EXTI_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +EXTI_IRQHandler + B EXTI_IRQHandler + + PUBWEAK SRAM_PARITY_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +SRAM_PARITY_IRQHandler + B SRAM_PARITY_IRQHandler + + PUBWEAK CLKRDY_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +CLKRDY_IRQHandler + B CLKRDY_IRQHandler + + PUBWEAK UART4_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +UART4_IRQHandler + B UART4_IRQHandler + + PUBWEAK DMA_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +DMA_IRQHandler + B DMA_IRQHandler + + PUBWEAK UART3_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +UART3_IRQHandler + B UART3_IRQHandler + + PUBWEAK RSV_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +RSV_IRQHandler + B RSV_IRQHandler + + PUBWEAK ADC_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +ADC_IRQHandler + B ADC_IRQHandler + + PUBWEAK TIM1_BRK_UP_TRG_COM_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +TIM1_BRK_UP_TRG_COM_IRQHandler + B TIM1_BRK_UP_TRG_COM_IRQHandler + + PUBWEAK TIM1_CC_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +TIM1_CC_IRQHandler + B TIM1_CC_IRQHandler + + PUBWEAK TIM2_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +TIM2_IRQHandler + B TIM2_IRQHandler + + PUBWEAK TIM3_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +TIM3_IRQHandler + B TIM3_IRQHandler + + PUBWEAK TIM6_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +TIM6_IRQHandler + B TIM6_IRQHandler + + PUBWEAK TIM7_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +TIM7_IRQHandler + B TIM7_IRQHandler + + PUBWEAK TIM14_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +TIM14_IRQHandler + B TIM14_IRQHandler + + PUBWEAK TIM15_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +TIM15_IRQHandler + B TIM15_IRQHandler + + PUBWEAK TIM16_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +TIM16_IRQHandler + B TIM16_IRQHandler + + PUBWEAK TIM17_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +TIM17_IRQHandler + B TIM17_IRQHandler + + PUBWEAK I2C1_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +I2C1_IRQHandler + B I2C1_IRQHandler + + PUBWEAK I2C2_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +I2C2_IRQHandler + B I2C2_IRQHandler + + PUBWEAK SPI1_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +SPI1_IRQHandler + B SPI1_IRQHandler + + PUBWEAK SPI2_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +SPI2_IRQHandler + B SPI2_IRQHandler + + PUBWEAK UART1_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +UART1_IRQHandler + B UART1_IRQHandler + + PUBWEAK UART2_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +UART2_IRQHandler + B UART2_IRQHandler + + PUBWEAK LPUART_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +LPUART_IRQHandler + B LPUART_IRQHandler + + PUBWEAK SPI3_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +SPI3_IRQHandler + B SPI3_IRQHandler + + PUBWEAK AES_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +AES_IRQHandler + B AES_IRQHandler + + PUBWEAK USB_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +USB_IRQHandler + B USB_IRQHandler + + PUBWEAK DAC_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +DAC_IRQHandler + B DAC_IRQHandler + + PUBWEAK I2S_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +I2S_IRQHandler + B I2S_IRQHandler + + PUBWEAK GPIOEF_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +GPIOEF_IRQHandler + B GPIOEF_IRQHandler + + PUBWEAK CAN1_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +CAN1_IRQHandler + B CAN1_IRQHandler + + PUBWEAK CAN2_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +CAN2_IRQHandler + B CAN2_IRQHandler + + PUBWEAK FPU_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +FPU_IRQHandler + B FPU_IRQHandler + + PUBWEAK TIM4_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +TIM4_IRQHandler + B TIM4_IRQHandler + + PUBWEAK SPI4_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +SPI4_IRQHandler + B SPI4_IRQHandler + + + END +/************************ (C) COPYRIGHT Aisinochip *****END OF FILE****/ diff --git a/bsp/acm32f4xx-nucleo/libraries/Device/System_ACM32F4.c b/bsp/acm32f4xx-nucleo/libraries/Device/System_ACM32F4.c new file mode 100644 index 0000000000..6382903de9 --- /dev/null +++ b/bsp/acm32f4xx-nucleo/libraries/Device/System_ACM32F4.c @@ -0,0 +1,744 @@ +/* + ****************************************************************************** + * @file System_ACM32F4.c + * @version V1.0.0 + * @date 2021 + * @brief System Source File, includes clock management, reset management + * and IO configuration, ... + ****************************************************************************** +*/ +#include "ACM32Fxx_HAL.h" + +uint32_t gu32_SystemClock; +uint32_t gu32_APBClock; + +/* System count in SysTick_Handler */ +volatile uint32_t gu32_SystemCount; + +/************************* Miscellaneous Configuration ************************/ +/*!< Uncomment the following line if you need to relocate your vector Table in + Internal SRAM. */ +/* #define VECT_TAB_SRAM */ +#define VECT_TAB_OFFSET 0x0U /*!< Vector Table base offset field. + This value must be a multiple of 0x200. */ +/******************************************************************************/ + +/********************************************************************************* +* Function : HardFault_Handler +* Description : Hard Fault handle, while(1) loop, wait for debug +* Input : none +* Output : none +* Author : xwl +**********************************************************************************/ +//void HardFault_Handler(void) //implemented in context_rvds.S +//{ +// while(1); +//} + +/********************************************************************************* +* Function : SysTick_Handler +* Description : System tick handler +* Input : none +* Output : none +* Author : Chris_Kyle +**********************************************************************************/ +//void SysTick_Handler(void) //implemented in board.c +//{ +// gu32_SystemCount++; +//} + +/********************************************************************************* +* Function : System_SysTick_Init +* Description : System Tick Init. Period is 1 ms +* Input : none +* Output : none +* Author : Chris_Kyle +**********************************************************************************/ +//void System_SysTick_Init(void) //implemented in board.c/rt_hw_board_init() +//{ +// gu32_SystemCount = 0; +// SysTick_Config(gu32_SystemClock / 1000); //1ms/tick +//} + +/********************************************************************************* +* Function : System_SysTick_Off +* Description : Turn off System Tick +* Input : none +* Output : none +* Author : xwl +**********************************************************************************/ +//void System_SysTick_Off(void) +//{ +// SysTick->CTRL = 0; +//} +/********************************************************************************* +* Function : System_Init +* Description : Initialize the system clock, accelerate function and system tick. +* Input : none +* Output : none +* Author : Chris_Kyle +**********************************************************************************/ +void System_Init(void) +{ + SCU->RCR |= SCU_RCR_REMAP_EN; // always remap enabled + System_Set_Buzzer_Divider(80, FUNC_DISABLE); // disable clock out + /* 3 bits for pre-emption priority, 0 bits for subpriority */ + NVIC_SetPriorityGrouping(NVIC_PRIORITY_GROUP_3); + + /* Initialize the system clock */ + if (false == System_Clock_Init(DEFAULT_SYSTEM_CLOCK)) + { + while(1); + } + +#if (__ACCELERATE_PRESENT == 1) + System_EnableIAccelerate(); +#endif + +#if (__ACCELERATE_EH_PRESENT == 1) + System_EnableDAccelerate(); +#endif + +#ifdef HAL_SYSTICK_ENABLED // To activate macro in ACM32Fxx_HAL.h + //System_SysTick_Init(); +#endif +} + +/********************************************************************************* +* Function : System_Core_Config +* Description : configure FPU and vector table address +* Input : none +* Output : none +* Author : Chris_Kyle +**********************************************************************************/ +void System_Core_Config(void) +{ +#if (__FPU_PRESENT == 1) && (__FPU_USED == 1) + /* set CP10 and CP11 Full Access */ + SCB->CPACR |= ((3UL << 10*2) | (3UL << 11*2)); +#endif + + /* Configure the Vector Table location add offset address ------------------*/ +#ifdef VECT_TAB_SRAM + SCB->VTOR = SRAM_BASE | VECT_TAB_OFFSET; /* Vector Table Relocation in Internal SRAM */ +#else + SCB->VTOR = EFLASH_BASE | VECT_TAB_OFFSET; /* Vector Table Relocation in Internal FLASH */ +#endif +} + + +/********************************************************************************* +* Function : System_Clock_Init +* Description : Clock init +* Input : fu32_Clock: System core clock frequency, measured as Hz +* Output : 0: success, other value: fail reason +* Author : xwl +**********************************************************************************/ +bool System_Clock_Init(uint32_t fu32_Clock) +{ + volatile uint32_t lu32_sysdiv, lu32_pclkdiv, lu32_timeout, lu32_pll_src, lu32_pclk_div_para, lu32_result; + + SET_EFC_RD_WAIT(RD_WAIT_ENSURE_OK) + lu32_result = 0; + lu32_pll_src = PLL_SOURCE_FROM; + + if(0 == (SCU->RCHCR & SCU_RCHCR_RCHRDY)) + { + SCU->RCHCR |= SCU_RCHCR_RCH_EN; + while(0 == (SCU->RCHCR & SCU_RCHCR_RCHRDY)); // wait RCH ready + } + SCU->CCR1 = 0; // select RC64M as default + + if (fu32_Clock <= 64000000) + { + if ((SCU->RCHCR) & SCU_RCHCR_RCH_DIV) + { + SCU->RCHCR &= (~SCU_RCHCR_RCH_DIV); + while(0 == (SCU->RCHCR & SCU_RCHCR_RCHRDY)); + } + + if (fu32_Clock == 32000000) + { + gu32_SystemClock = fu32_Clock; + lu32_sysdiv = 2; + lu32_pclkdiv = 1; // pclk = hclk + } + else + { + gu32_SystemClock = 64000000; + lu32_sysdiv = 1; + lu32_pclkdiv = 1; + } + + gu32_APBClock = gu32_SystemClock/lu32_pclkdiv; + } + // select pll as system clock + else + { + if (PLLCLK_SRC_RC4M == lu32_pll_src) + { + SCU->RCHCR |= SCU_RCHCR_RCH_DIV; + while(!(SCU->RCHCR & SCU_RCHCR_RCHRDY)); + + SCU->PLLCR |= SCU_PLLCR_PLL_EN; + SCU->PLLCR &= ~(SCU_PLLCR_PLL_SLEEP); + while(!(SCU->PLLCR & SCU_PLLCR_PLL_FREE_RUN)); + + switch(fu32_Clock) + { + case 180000000: // 180M + { + SCU->PLLCR = (SCU->PLLCR & ~(0xFFFF8)) | (33 << 3); + SCU->PLLCR |= SCU_PLLCR_PLL_UPDATE_EN; + while(!(SCU->PLLCR & (SCU_PLLCR_PLL_FREE_RUN) ) ); + + lu32_sysdiv = 1; + lu32_pclkdiv = 2; // pclk = hclk/2 + }break; + + case 120000000: // 120M + { + SCU->PLLCR = (SCU->PLLCR & ~(0xFFFF8)) | (18U << 3); + SCU->PLLCR |= SCU_PLLCR_PLL_UPDATE_EN; + while(!(SCU->PLLCR & (SCU_PLLCR_PLL_FREE_RUN) ) ); + + lu32_sysdiv = 1; + lu32_pclkdiv = 2; // pclk = hclk/2 + }break; + + default: lu32_result = 1; break; + } + gu32_SystemClock = fu32_Clock; + gu32_APBClock = gu32_SystemClock/lu32_pclkdiv; + SCU->CCR1 = SCU_CCR1_SYS_PLL; // configure system clock as PLL clock + } + else if (SCU_XTHCR_XTH_EN == lu32_pll_src) + { + lu32_timeout = 0; + + SCU->XTHCR = SCU_XTHCR_XTH_EN | SCU_XTHCR_READYTIME_32768; + while (0 == (SCU->XTHCR & SCU_XTHCR_XTHRDY)) + { + if (lu32_timeout == SYSTEM_TIMEOUT) + { + lu32_result = 2; + break; + } + lu32_timeout++; + } + + if (0 == lu32_result) + { + SCU->PLLCR |= SCU_PLLCR_PLL_EN; + SCU->PLLCR &= ~(SCU_PLLCR_PLL_SLEEP); + while(!(SCU->PLLCR & (SCU_PLLCR_PLL_FREE_RUN) )); + + switch(fu32_Clock) + { + case 180000000: // 180M + { + SCU->PLLCR = (SCU->PLLCR &(~(0x1FFFFU << 3))) | (18U << 3) | (1U << 12) | (0U << 16); + SCU->PLLCR = (SCU->PLLCR & (~(0x3U << 1)) ) | (3 << 1); + SCU->PLLCR |= SCU_PLLCR_PLL_UPDATE_EN; + while(!(SCU->PLLCR & (SCU_PLLCR_PLL_FREE_RUN) ) ); + + lu32_sysdiv = 1; + lu32_pclkdiv = 2; // pclk = hclk/2 + }break; + + case 120000000: // 120M + { + SCU->PLLCR = (SCU->PLLCR &(~(0x1FFFFU << 3))) | (18U << 3) | (2U << 12) | (0U << 16); + SCU->PLLCR = (SCU->PLLCR & (~(0x3U << 1)) ) | (3 << 1); // select XTH + SCU->PLLCR |= SCU_PLLCR_PLL_UPDATE_EN; + while(!(SCU->PLLCR & (SCU_PLLCR_PLL_FREE_RUN) ) ); + + lu32_sysdiv = 1; + lu32_pclkdiv = 2; // pclk = hclk/2 + }break; + + default: lu32_result = 1; break; + } + } + gu32_SystemClock = fu32_Clock; + gu32_APBClock = gu32_SystemClock/lu32_pclkdiv; + SCU->CCR1 = SCU_CCR1_SYS_PLL; // configure system clock as PLL clock + } + else + { + lu32_result = 3; + } + } + + if (0 == lu32_result) + { + if (1 == lu32_pclkdiv) + { + lu32_pclk_div_para = 0; + } + else if (2 == lu32_pclkdiv) + { + lu32_pclk_div_para = 4; // pclk = hclk/2 + } + else + { + lu32_pclk_div_para = 5; // pclk = hclk/4 + } + } + else + { + lu32_sysdiv = 1; + lu32_pclk_div_para = 0; + } + + SCU->CCR2 = (SCU->CCR2 & (~0x7FFU)) | (lu32_sysdiv-1) | (lu32_pclk_div_para << 8); + while((SCU->CCR2 & SCU_CCR2_DIVDONE) == 0x00); // wait divide done + + HAL_EFlash_Init(gu32_SystemClock); + + return (lu32_result == 0); +} + +/********************************************************************************* +* Function : System_Get_SystemClock +* Description : get AHB clock frequency +* Input : none +* Output : frequency, measured as Hz +* Author : Chris_Kyle +**********************************************************************************/ +uint32_t System_Get_SystemClock(void) +{ + return gu32_SystemClock; +} + +/********************************************************************************* +* Function : System_Get_APBClock +* Description : get APB clock frequency +* Input : none +* Output : frequency, measured as Hz +* Author : Chris_Kyle +**********************************************************************************/ +uint32_t System_Get_APBClock(void) +{ + return gu32_APBClock; +} + +/********************************************************************************* +* Function : System_Module_Reset +* Description : reset module +* Input : module id +* Output : none +* Author : Chris_Kyle +**********************************************************************************/ +void System_Module_Reset(enum_RST_ID_t fe_ID_Index) +{ + if (fe_ID_Index > 31) + { + SCU->IPRST2 &= ~(1 << (fe_ID_Index - 32)); + System_Delay(5); + SCU->IPRST2 |= 1 << (fe_ID_Index - 32); + } + else + { + SCU->IPRST1 &= ~(1 << fe_ID_Index); + System_Delay(5); + SCU->IPRST1 |= 1 << fe_ID_Index; + } +} + +/********************************************************************************* +* Function : System_Module_Enable +* Description : enable module clock +* Input : module id +* Output : none +* Author : Chris_Kyle +**********************************************************************************/ +void System_Module_Enable(enum_Enable_ID_t fe_ID_Index) +{ + if (fe_ID_Index > 13) + { + SCU->IPCKENR1 |= 1 << (fe_ID_Index - 14); + } + else + { + SCU->IPCKENR2 |= 1 << fe_ID_Index; + } + + System_Delay(2); +} + +/********************************************************************************* +* Function : System_Module_Disable +* Description : disable module clock +* Input : module id +* Output : none +* Author : Chris_Kyle +**********************************************************************************/ +void System_Module_Disable(enum_Enable_ID_t fe_ID_Index) +{ + if (fe_ID_Index > 13) + { + SCU->IPCKENR1 &= ~(1 << (fe_ID_Index - 14)); + } + else + { + SCU->IPCKENR2 &= ~(1 << fe_ID_Index); + } +} + +/********************************************************************************* +* Function : System_Delay +* Description : NOP delay +* Input : count +* Output : none +* Author : Chris_Kyle +**********************************************************************************/ +void System_Delay(volatile uint32_t fu32_Delay) +{ + while (fu32_Delay--); +} + +/********************************************************************************* +* Function : System_Delay_MS +* Description : ms delay. Use this Function must call System_SysTick_Init() +* Input : delay period, measured as ms +* Output : none +* Author : Chris_Kyle +**********************************************************************************/ +void System_Delay_MS(volatile uint32_t fu32_Delay) +{ + uint32_t lu32_SystemCountBackup; + + lu32_SystemCountBackup = gu32_SystemCount; + + while ( (gu32_SystemCount - lu32_SystemCountBackup) < fu32_Delay); +} + +/********************************************************************************* +* Function : System_Enable_RC32K +* Description : Enable RC32K, make sure RTC Domain Access is allowed +* Input : none +* Output : none +* Author : CWT +**********************************************************************************/ +void System_Enable_RC32K(void) +{ + PMU->ANACR |= (1 << 8); + while(0 == ((PMU->ANACR) & (1U << 9))); +} + +/********************************************************************************* +* Function : System_Disable_RC32K +* Description : Disable RC32K +* Input : none +* Output : none +* Author : CWT +**********************************************************************************/ +void System_Disable_RC32K(void) +{ + PMU->ANACR &= (~(1 << 8)); +} + +/********************************************************************************* +* Function : System_Enable_XTAL +* Description : Enable XTAL, make sure RTC Domain Access is allowed +* Input : none +* Output : none +* Author : CWT +**********************************************************************************/ +void System_Enable_XTAL(void) +{ + PMU->ANACR = (PMU->ANACR & ~RPMU_ANACR_XTLDRV) | (RPMU_ANACR_XTLDRV_1 | RPMU_ANACR_XTLDRV_0); + PMU->ANACR |= RPMU_ANACR_XTLEN; + while(!(PMU->ANACR & RPMU_ANACR_XTLRDY)); + PMU->CR1 |= RTC_CLOCK_XTL; +} + +/********************************************************************************* +* Function : System_Disable_XTAL +* Description : Disable XTAL +* Input : none +* Output : none +* Author : CWT +**********************************************************************************/ +void System_Disable_XTAL(void) +{ + PMU->ANACR &= (~(RPMU_ANACR_XTLEN)); +} + +/********************************************************************************* +* Function : System_Enable_Disable_RTC_Domain_Access +* Description : Enable or Disable RTC Domain Access. +* Input : enable or disable +* Output : none +* Author : CWT +**********************************************************************************/ +void System_Enable_Disable_RTC_Domain_Access(FUNC_DISABLE_ENABLE enable_disable) +{ + if (FUNC_DISABLE == enable_disable) + { + SCU->STOPCFG &= (~SCU_STOPCFG_RTC_WE); + } + else + { + SCU->STOPCFG |= SCU_STOPCFG_RTC_WE; + System_Delay(1); + RTC->WP = 0xCA53CA53U; + } +} + +/********************************************************************************* +* Function : System_Enable_Disable_Reset +* Description : Enable or Disable System Reset source. +* Input : none +* Output : none +* Author : CWT +**********************************************************************************/ +void System_Enable_Disable_Reset(RESET_ENABLE_SOURCE source, FUNC_DISABLE_ENABLE enable_disable) +{ + switch(source) + { + /* reset source: from bit0 to bit3 */ + case RESET_ENABLE_SOURCE_LVD: + case RESET_ENABLE_SOURCE_WDT: + case RESET_ENABLE_SOURCE_IWDT: + case RESET_ENABLE_SOURCE_LOCKUP: + + if (FUNC_DISABLE == enable_disable) + { + SCU->RCR &= (~(1U << source)); + } + else + { + SCU->RCR |= (1U << source); + } + break; + + default: break; + } +} + +/********************************************************************************* +* Function : System_Reset_MCU +* Description : reset mcu +* Input : reset source +* Output : none +* Author : xwl +**********************************************************************************/ +void System_Reset_MCU(RESET_SOURCE source) +{ + switch(source) + { + case RESET_SOURCE_EFC: + { + SCU->RCR &= (~BIT29); + while(1); + }break; + + case RESET_SOURCE_NVIC_RESET: + { + NVIC_SystemReset(); + while(1); + }break; + + case RESET_SOFT_RESET: + { + SCU->RCR &= (~BIT30); + while(1); + }break; + + default: break; + } +} + +/********************************************************************************* +* Function : System_Enter_Standby_Mode +* Description : try to enter standby mode +* Input : none +* Output : none +* Author : xwl Date : 2021 +**********************************************************************************/ +void System_Enter_Standby_Mode(void) +{ + __set_PRIMASK(1); // disable interrupt + SysTick->CTRL = 0; // disable systick + SCU->STOPCFG |= BIT11; // set PDDS=1 + + /* Set SLEEPDEEP bit of Cortex System Control Register */ + SET_BIT(SCB->SCR, ((uint32_t)SCB_SCR_SLEEPDEEP_Msk)); + __WFI(); + CLEAR_BIT(SCB->SCR, ((uint32_t)SCB_SCR_SLEEPDEEP_Msk)); + System_Delay(100); + + printfS("Enter Standby Mode Failed! \n"); // should not go here +} + +/********************************************************************************* +* Function : System_Clear_Stop_Wakeup +* Description : clear all stop setting and status +* Input : none +* Output : none +* Author : CWT Date : 2021? +**********************************************************************************/ +void System_Clear_Stop_Wakeup(void) +{ + EXTI->IENR = 0; + EXTI->RTENR = 0; + EXTI->FTENR = 0; + EXTI->SWIER = 0; + EXTI->PDR = 0x7FFFFFU; +} + +/********************************************************************************* +* Function : System_Enter_Stop_Mode +* Description : try to enter stop mode +* Input : STOPEntry: STOPENTRY_WFI or STOPENTRY_WFE +* Output : none +* Author : CWT Date : 2021 +**********************************************************************************/ +void System_Enter_Stop_Mode(uint8_t STOPEntry) +{ + /* Set SLEEPDEEP bit of Cortex System Control Register */ + SET_BIT(SCB->SCR, ((uint32_t)SCB_SCR_SLEEPDEEP_Msk)); + + SCU->STOPCFG &= (~BIT11); // PDDS=0 + + //System_SysTick_Off(); + /* Select Stop mode entry */ + if(STOPEntry == STOPENTRY_WFI) + { + /* Wait For Interrupt */ + __WFI(); + } + else + { + __SEV(); + __WFE(); + __WFE(); /* Wait For Event */ + } + + CLEAR_BIT(SCB->SCR, ((uint32_t)SCB_SCR_SLEEPDEEP_Msk)); + +#ifdef HAL_SYSTICK_ENABLED // To activate macro in ACM32Fxx_HAL.h + //System_SysTick_Init(); +#endif +} + +/********************************************************************************* +* Function : System_Enter_Sleep_Mode +* Description : try to enter sleep mode +* Input : SleepEntry: SLEEPENTRY_WFI or SLEEPENTRY_WFE +* Output : none +* Author : CWT Date : 2021 +**********************************************************************************/ +void System_Enter_Sleep_Mode(uint8_t SleepEntry) +{ + /* clear SLEEPDEEP bit of Cortex System Control Register */ + CLEAR_BIT(SCB->SCR, ((uint32_t)SCB_SCR_SLEEPDEEP_Msk)); + + /* Select Stop mode entry */ + if(SleepEntry == SLEEPENTRY_WFI) + { + /* Wait For Interrupt */ + __WFI(); + } + else + { + + __SEV(); + __WFE(); + __WFE(); /*Wait For Event */ + } + +} + + + /********************************************************************************* +* Function : System_Return_Last_Reset_Reason +* Description : Get System Last Reset Reason +* Input : none +* Output : RESET_REASON +* Author : CWT Date : 2021? +**********************************************************************************/ +RESET_REASON System_Return_Last_Reset_Reason(void) +{ + RESET_REASON Reset_Reason_Save; + RESET_REASON i = RESET_REASON_POR; + + for(i = RESET_REASON_POR; i >= RESET_REASON_POR12; i--) + { + if ((SCU->RSR) & (1U << i)) + { + SCU->RSR |= SCU_RSR_RSTFLAG_CLR; // clear reset reason flags + Reset_Reason_Save = i; + return i; + } + } + + for(i = RESET_REASON_LOW_VOLTAGE; i <= RESET_REASON_SOFT; i++) + { + if ((SCU->RSR) & (1U << i)) + { + SCU->RSR |= SCU_RSR_RSTFLAG_CLR; // clear reset reason flags + Reset_Reason_Save = i; + return i; + } + } + + return RESET_REASON_INVALID; // this should not happen +} + + /********************************************************************************* +* Function : System_Set_Buzzer_Divider +* Description : set buzzer divide factor +* Input : + div: div factor, if div = 80 then output buzzer freq=HCLK/80 + enable: FUNC_DISABLE and FUNC_ENABLE +* Output : none +* Author : xwl Date : 2021?o +**********************************************************************************/ +void System_Set_Buzzer_Divider(uint32_t div, FUNC_DISABLE_ENABLE enable) +{ + if (FUNC_ENABLE == enable) + { + SCU->CLKOCR = (SCU->CLKOCR & (~(0x1FFFFU << 5) ) ) | (div << 5); + SCU->CLKOCR |= BIT23; + } + else + { + SCU->CLKOCR &= (~BIT23); + } +} + +/********************************************************************************* +* Function : System_USB_PHY_Config +* Description : Configure USB PHY, such as clock select, pll... +* Input : none +* Output : 0: fail, 1:success +* Author : xwl Date : 2021? +**********************************************************************************/ +uint32_t System_USB_PHY_Config(void) +{ + volatile uint32_t delay_count; + + SCU->PHYCR &= (~BIT2); // exit power down, auto select clock source + + delay_count = SYSTEM_TIMEOUT; + while(delay_count--) + { + if (SCU->PHYCR & (BIT19)) // clksel_end flag = 1 + { + break; + } + } + + if (delay_count) + { + return HAL_OK; + } + else + { + return HAL_TIMEOUT; + } +} + diff --git a/bsp/acm32f4xx-nucleo/libraries/Device/System_ACM32F4.h b/bsp/acm32f4xx-nucleo/libraries/Device/System_ACM32F4.h new file mode 100644 index 0000000000..e4c604dc90 --- /dev/null +++ b/bsp/acm32f4xx-nucleo/libraries/Device/System_ACM32F4.h @@ -0,0 +1,671 @@ +/* + ****************************************************************************** + * @file System_ACM32F4.h + * @version V1.0.0 + * @date 2020 + * @brief CMSIS Cortex-M33 Device Peripheral Access Layer System Headler File. + ****************************************************************************** +*/ +#ifndef __SYSTEM_ACM32F4_H__ +#define __SYSTEM_ACM32F4_H__ + +#include "ACM32Fxx_HAL.h" + +/* ================================================================================ */ +/* ======================= Use Uart to Debug print ======================== */ +/* ================================================================================ */ +#define UART_DEBUG_ENABLE + +#ifdef UART_DEBUG_ENABLE + #define printfS printf +#else + #define printfS(format, ...) ((void)0) +#endif +/* ================================================================================ */ + +#define PLLCLK_SRC_RC4M (0x00) +#define PLLCLK_SRC_XTH (0x01) + +#define DEFAULT_SYSTEM_CLOCK (180000000) // system clock frequency, 32M/64M/120M/180M +#define PLL_SOURCE_FROM (PLLCLK_SRC_RC4M) + +/* CLK source Index */ +#define SYS_CLK_SRC_RCH (0x00) // CLK source from RC64M +#define SYS_CLK_SRC_RC32K (0x01) // CLK source from RC32K +#define SYS_CLK_SRC_XTH (0x02) // CLK source from XTH +#define SYS_CLK_SRC_XTL (0x03) // CLK source from XTL +#define SYS_CLK_SRC_PLLCLK (0x04) // CLK source from PLLCLK + +/* APB Frequencey Division */ +#define APB_CLK_DIV_0 (0 << 8) +#define APB_CLK_DIV_2 (4 << 8) +#define APB_CLK_DIV_4 (5 << 8) +#define APB_CLK_DIV_8 (6 << 8) +#define APB_CLK_DIV_16 (7 << 8) + +/* STOP WAKEUP Sorce */ +#define STOP_WAKEUP_GPIO_PIN0 BIT0 +#define STOP_WAKEUP_GPIO_PIN1 BIT1 +#define STOP_WAKEUP_GPIO_PIN2 BIT2 +#define STOP_WAKEUP_GPIO_PIN3 BIT3 +#define STOP_WAKEUP_GPIO_PIN4 BIT4 +#define STOP_WAKEUP_GPIO_PIN5 BIT5 +#define STOP_WAKEUP_GPIO_PIN6 BIT6 +#define STOP_WAKEUP_GPIO_PIN7 BIT7 +#define STOP_WAKEUP_GPIO_PIN8 BIT8 +#define STOP_WAKEUP_GPIO_PIN9 BIT9 +#define STOP_WAKEUP_GPIO_PIN10 BIT10 +#define STOP_WAKEUP_GPIO_PIN11 BIT11 +#define STOP_WAKEUP_GPIO_PIN12 BIT12 +#define STOP_WAKEUP_GPIO_PIN13 BIT13 +#define STOP_WAKEUP_GPIO_PIN14 BIT14 +#define STOP_WAKEUP_GPIO_PIN15 BIT15 +#define STOP_WAKEUP_PERIPHERAL_LVD BIT16 +#define STOP_WAKEUP_PERIPHERAL_RTC BIT17 +#define STOP_WAKEUP_PERIPHERAL_LPUART BIT18 +#define STOP_WAKEUP_PERIPHERAL_IWDT BIT19 +#define STOP_WAKEUP_PERIPHERAL_COMP1 BIT20 +#define STOP_WAKEUP_PERIPHERAL_COMP2 BIT21 +#define STOP_WAKEUP_RESERVE BIT22 +#define STOP_WAKEUP_PERIPHERAL_USB BIT23 +#define STOP_WAKEUP_ALL (0xFFFFFFU) + +#define STANDBY_WAKEUP_PINS 6 +#define STANDBY_WAKEUP_SOURCE_IO1 BIT0 +#define STANDBY_WAKEUP_SOURCE_IO2 BIT1 +#define STANDBY_WAKEUP_SOURCE_IO3 BIT2 +#define STANDBY_WAKEUP_SOURCE_IO4 BIT3 +#define STANDBY_WAKEUP_SOURCE_IO5 BIT4 +#define STANDBY_WAKEUP_SOURCE_IO6 BIT5 +#define STANDBY_WAKEUP_SOURCE_RTC BIT6 +#define STANDBY_WAKEUP_SOURCE_ALL 0x7FU + +// sleep/low power mode definition +#define STOPENTRY_WFI 0 +#define STOPENTRY_WFE 1 + +#define SLEEPENTRY_WFI 0 +#define SLEEPENTRY_WFE 1 +/* + * @brief STOP WAKEUP EDGE structures definition + */ +typedef enum +{ + WAKEUP_RISING = 0, + WAKEUP_FALLING = 1, + WAKEUP_RISING_FALLING = 2, // 0:rising, 1:falling, 2: rising and falling +}STOP_WAKEUP_EDGE; + +typedef enum +{ + FUNC_DISABLE = 0x00U, + FUNC_ENABLE = 0x01U, +}FUNC_DISABLE_ENABLE; + +typedef enum +{ + RESET_ENABLE_SOURCE_LVD = 0x00U, + RESET_ENABLE_SOURCE_WDT = 0x01U, + RESET_ENABLE_SOURCE_IWDT = 0x02U, + RESET_ENABLE_SOURCE_LOCKUP = 0x03U, +}RESET_ENABLE_SOURCE; + +typedef enum +{ + RESET_SOURCE_EFC = 0x00U, + RESET_SOURCE_NVIC_RESET = 0x01U, + RESET_SOFT_RESET = 0x02U, +}RESET_SOURCE; + +/* + * @brief Peripheral Reset structures definition + */ +typedef enum +{ + RST_SPI4 = 38, + RST_GPIOEF = 37, + RST_SPI3 = 36, + RST_UART4 = 35, + RST_TIM4 = 34, + RST_CAN2 = 33, + RST_I2S1 = 32, + + RST_CAN1 = 31, + RST_TIM2 = 30, + RST_USB = 29, + RST_UAC = 28, + RST_TIM17 = 27, + RST_TIM16 = 26, + RST_TIM15 = 25, + RST_TIM14 = 24, + RST_TIM7 = 23, + RST_TIM6 = 22, + RST_TIM3 = 21, + RST_TIM1 = 20, + RST_UART3 = 19, + RST_EXTI = 18, + RST_OPA = 17, + RST_COMP = 16, + RST_TKEY = 15, + RST_ADC = 14, + RST_DAC = 13, + RST_DMA = 12, + RST_CRC = 11, + RST_IWDT = 10, + RST_WDT = 9, + RST_LPUART = 8, + RST_I2C2 = 7, + RST_I2C1 = 6, + RST_SPI2 = 5, + RST_SPI1 = 4, + RST_UART2 = 3, + RST_UART1 = 2, + RST_GPIOCD = 1, + RST_GPIOAB = 0, +}enum_RST_ID_t; + +/**************** Bit definition for SCU RCR register ***********************/ +#define SCU_RCR_SOFT_RST BIT30 +#define SCU_RCR_EFC_RST BIT29 +#define SCU_RCR_REMAP_EN BIT16 +#define SCU_RCR_LOCKRST_EN BIT3 +#define SCU_RCR_IWDTRST_EN BIT2 +#define SCU_RCR_WDTRST_EN BIT1 +#define SCU_RCR_LVDRST_EN BIT0 + +/**************** Bit definition for SCU RSR register ***********************/ +#define SCU_RSR_RSTFLAG_CLR BIT16 +#define SCU_RSR_PWRRST_F BIT10 +#define SCU_RSR_POR12RST_F BIT9 +#define SCU_RSR_SRST_F BIT8 +#define SCU_RSR_SRSTNM_F BIT7 +#define SCU_RSR_EFC_RST_F BIT6 +#define SCU_RSR_RSTN_F BIT5 +#define SCU_RSR_SYSREQRST_F BIT4 +#define SCU_RSR_LOCKRST_F BIT3 +#define SCU_RSR_IWDTRST_F BIT2 +#define SCU_RSR_WDTRST_F BIT1 +#define SCU_RSR_VDLRST_F BIT0 + +/**************** Bit definition for SCU IPRST register **********************/ +#define SCU_IPRST_UACRST BIT28 +#define SCU_IPRST_TIM17RST BIT27 +#define SCU_IPRST_TIM16RST BIT26 +#define SCU_IPRST_TIM15RST BIT25 +#define SCU_IPRST_TIM14RST BIT24 +#define SCU_IPRST_TIM6RST BIT22 +#define SCU_IPRST_TIM3RST BIT21 +#define SCU_IPRST_TIM1RST BIT20 +#define SCU_IPRST_UART3RST BIT19 +#define SCU_IPRST_EXTIRST BIT18 +#define SCU_IPRST_OPARST BIT17 +#define SCU_IPRST_CMPRST BIT16 +#define SCU_IPRST_TKEYRST BIT15 +#define SCU_IPRST_ADCRST BIT14 +#define SCU_IPRST_DMACRST BIT12 +#define SCU_IPRST_CRCRST BIT11 +#define SCU_IPRST_IWDTRST BIT10 +#define SCU_IPRST_WDTRST BIT9 +#define SCU_IPRST_LPUART BIT8 +#define SCU_IPRST_I2C2RST BIT7 +#define SCU_IPRST_I2C1RST BIT6 +#define SCU_IPRST_SPI2RST BIT5 +#define SCU_IPRST_SPI1RST BIT4 +#define SCU_IPRST_UART2RST BIT3 +#define SCU_IPRST_UART1RST BIT2 +#define SCU_IPRST_GPIO2RST BIT1 +#define SCU_IPRST_GPIO1RST BIT0 + +/**************** Bit definition for SCU CCR1 register ***********************/ +#define SCU_CCR1_SYS_CLK_SEL (BIT2|BIT1|BIT0) +#define SCU_CCR1_SYS_PLL (BIT2) + +/**************** Bit definition for SCU CCR2 register ***********************/ +#define SCU_CCR2_DIVDONE BIT31 +#define SCU_CCR2_TKSCLK_SEL BIT16 +#define SCU_CCR2_FLTCLK_SEL BIT15 +#define SCU_CCR2_LPUCLK_SEL (BIT14|BIT13) +#define SCU_CCR2_LPUARTDIV (BIT12|BIT11) +#define SCU_CCR2_PCLKDIV (BIT10|BIT9|BIT8) +#define SCU_CCR2_SYSDIV1 (BIT7|BIT6|BIT5|BIT4) +#define SCU_CCR2_SYSDIV0 (BIT3|BIT2|BIT1|BIT0) + +/**************** Bit definition for SCU CIR register ***********************/ +#define SCU_CIR_RC4MRDYIC BIT21 +#define SCU_CIR_PLLLOCKIC BIT20 +#define SCU_CIR_XTHRDYIC BIT19 +#define SCU_CIR_RCHRDYIC BIT18 +#define SCU_CIR_XTLRDYIC BIT17 +#define SCU_CIR_RC32KRDYIC BIT16 +#define SCU_CIR_RC4MRDYIE BIT13 +#define SCU_CIR_PLLLOCKIE BIT12 +#define SCU_CIR_XTHRDYIE BIT11 +#define SCU_CIR_RCHRDYIE BIT10 +#define SCU_CIR_XTLRDYIE BIT9 +#define SCU_CIR_RC32KRDYIE BIT8 +#define SCU_CIR_RC4MRDYIF BIT5 +#define SCU_CIR_PLLLOCKIF BIT4 +#define SCU_CIR_XTHRDYIF BIT3 +#define SCU_CIR_RCHRDYIF BIT2 +#define SCU_CIR_XTLRDYIF BIT1 +#define SCU_CIR_RC32KRDYIF BIT0 + +/**************** Bit definition for SCU IPCKENR register ********************/ +#define SCU_IPCKENR_ROMCLKEN BIT30 +#define SCU_IPCKENR_HRNGCLKEN BIT29 +#define SCU_IPCKENR_AESCLKEN BIT28 +#define SCU_IPCKENR_TIM17CLKEN BIT27 +#define SCU_IPCKENR_TIM16CLKEN BIT26 +#define SCU_IPCKENR_TIM15CLKEN BIT25 +#define SCU_IPCKENR_TIM14CLKEN BIT24 +#define SCU_IPCKENR_TIM6CLKEN BIT22 +#define SCU_IPCKENR_TIM3CLKEN BIT21 +#define SCU_IPCKENR_TIM1CLKEN BIT20 +#define SCU_IPCKENR_UART3CLKEN BIT19 +#define SCU_IPCKENR_OPACLKEN BIT17 +#define SCU_IPCKENR_CMPCLKEN BIT16 +#define SCU_IPCKENR_TKEYCLKEN BIT15 +#define SCU_IPCKENR_ADCCLKEN BIT14 +#define SCU_IPCKENR_RTCCLKEN BIT13 +#define SCU_IPCKENR_DMACCLKEN BIT12 +#define SCU_IPCKENR_CRCCLKEN BIT11 +#define SCU_IPCKENR_LPUARTCLKEN BIT8 +#define SCU_IPCKENR_I2C2CLKEN BIT7 +#define SCU_IPCKENR_I2C1CLKEN BIT6 +#define SCU_IPCKENR_SPI2CLKEN BIT5 +#define SCU_IPCKENR_SPI1CLKEN BIT4 +#define SCU_IPCKENR_UART2CLKEN BIT3 +#define SCU_IPCKENR_UART1CLKEN BIT2 + +/**************** Bit definition for SCU IPCKENR2 register ********************/ +#define SCU_IPCKENR2_EFCCLKEN BIT6 +#define SCU_IPCKENR2_SRAMCLKEN BIT5 +#define SCU_IPCKENR2_EXTICLKEN BIT4 +#define SCU_IPCKENR2_IWDTCLKEN BIT3 +#define SCU_IPCKENR2_WDTCLKEN BIT2 +#define SCU_IPCKENR2_GPIO2CLKEN BIT1 +#define SCU_IPCKENR2_GPIO1CLKEN BIT0 + +/**************** Bit definition for SCU RCHCR register **********************/ +#define SCU_RCHCR_RC4MRDY BIT22 +#define SCU_RCHCR_RC4M_TRIM (BIT21|BIT20|BIT19|BIT18|BIT17) +#define SCU_RCHCR_RC4M_EN BIT16 +#define SCU_RCHCR_RCHRDY BIT9 +#define SCU_RCHCR_RCH_DIV BIT8 +#define SCU_RCHCR_RCH_TRIM (BIT7|BIT6|BIT5|BIT4|BIT3|BIT2|BIT1) +#define SCU_RCHCR_RCH_EN BIT0 + +/**************** Bit definition for SCU RCHCR register **********************/ +#define SCU_XTHCR_XTHRDY BIT4 +#define SCU_XTHCR_XTH_RDYTIME (BIT3|BIT2) +#define SCU_XTHCR_XTH_BYP BIT1 +#define SCU_XTHCR_XTH_EN BIT0 +#define SCU_XTHCR_READYTIME_1024 0 +#define SCU_XTHCR_READYTIME_4096 BIT2 +#define SCU_XTHCR_READYTIME_16384 BIT3 +#define SCU_XTHCR_READYTIME_32768 (BIT3|BIT2) + +/**************** Bit definition for SCU PLLCR register **********************/ +#define SCU_PLLCR_PLL_LOCK_SEL BIT31 +#define SCU_PLLCR_PLL_FREE_RUN BIT30 +#define SCU_PLLCR_PLL_LOCK BIT29 +#define SCU_PLLCR_PLL_RUN_DLY (BIT28|BIT27|BIT26|BIT25|BIT24|BIT23) +#define SCU_PLLCR_PLL_UPDATE_EN BIT22 +#define SCU_PLLCR_PLL_SLEEP BIT21 +#define SCU_PLLCR_PLL_OD (BIT19|BIT18) +#define SCU_PLLCR_PLL_N (BIT15|BIT14) +#define SCU_PLLCR_PLL_M (BIT6|BIT5|BIT4|BIT3) +#define SCU_PLLCR_PLL_SRC_SEL (BIT2|BIT1) +#define SCU_PLLCR_PLL_EN (BIT0) + +/**************** Bit definition for SCU LDOCR register **********************/ +#define SCU_LDOCR_LPLDO12_TRIM (BIT28|BIT27|BIT26) +#define SCU_LDOCR_LPSTP_SFT BIT25 +#define SCU_LDOCR_LPLDO12_EN_SFT BIT24 +#define SCU_LDOCR_MLDO12_LOWP_SFT BIT22 +#define SCU_LDOCR_MLDO12_LV_SFT (BIT21|BIT20) +#define SCU_LDOCR_LDO18A_EN BIT19 +#define SCU_LDOCR_ANATEST_SEL (BIT18|BIT17|BIT16) +#define SCU_LDOCR_LDO18A_TRIM (BIT15|BIT14|BIT13) +#define SCU_LDOCR_LDO18_TRIM (BIT12|BIT11|BIT10) +#define SCU_LDOCR_LDO18_EN BIT9 +#define SCU_LDOCR_LDOCTL_SEL BIT8 +#define SCU_LDOCR_LDO12_TRIM (BIT7|BIT6|BIT5|BIT4) +#define SCU_LDOCR_VREF_TRIM (BIT2|BIT1|BIT0) + +/**************** Bit definition for SCU WMR register ***********************/ +#define SCU_WMR_RTC_READY BIT6 +#define SCU_WMR_REMAP_FLAG BIT4 +#define SCU_WMR_BOOTPIN BIT3 + +/**************** Bit definition for SCU CLKOCR register ********************/ +#define SCU_CLKOCR_BUZZER2_EN BIT31 +#define SCU_CLKOCR_BUZZER2_POL BIT30 +#define SCU_CLKOCR_BUZZER2_DIV (BIT29|BIT28|BIT27|BIT26|BIT25|BIT24) +#define SCU_CLKOCR_BUZZER_EN BIT23 +#define SCU_CLKOCR_BUZZER_POL BIT22 +#define SCU_CLKOCR_BUZZER_DIV (0x3FFFE0) +#define SCU_CLKOCR_CLKOUT_SEL BIT4 +#define SCU_CLKOCR_CLKTEST_SEL (BIT3|BIT2|BIT1|BIT0) + +/**************** Bit definition for SCU SYSCFG1 register ********************/ +#define SCU_SYSCFG1_TIM15_CH2_SEL (BIT25|BIT24) +#define SCU_SYSCFG1_TIM15_CH1_SEL (BIT23|BIT22) +#define SCU_SYSCFG1_TIM14_CH1_SEL BIT20 +#define SCU_SYSCFG1_IR_MODE (BIT18|BIT17) +#define SCU_SYSCFG1_IR_POL BIT16 +#define SCU_SYSCFG1_SRAM_PEF BIT8 +#define SCU_SYSCFG1_LVD_LOCK BIT2 +#define SCU_SYSCFG1_SRAM_PARITY_LOCK BIT1 +#define SCU_SYSCFG1_LOCKUP_LOCK BIT0 + +/**************** Bit definition for SCU LVDCFG register ********************/ +#define SCU_LVDCFG_LVD_VALUE BIT15 +#define SCU_LVDCFG_LVD_FILTER BIT14 +#define SCU_LVDCFG_FLT_TIME (BIT11|BIT10|BIT9) +#define SCU_LVDCFG_LVD_FLTEN BIT8 +#define SCU_LVDCFG_LVD_TRIM (BIT4|BIT3|BIT2|BIT1) +#define SCU_LVDCFG_LVDEN BIT0 + +/**************** Bit definition for SCU STOPCFG register ********************/ +#define SCU_STOPCFG_LPLDO12_LV (BIT15|BIT14|BIT13) +#define SCU_STOPCFG_TKPCLK_SEL BIT12 +#define SCU_STOPCFG_PDDS BIT11 +#define SCU_STOPCFG_TK_LPLDOLV BIT10 +#define SCU_STOPCFG_LPSTOP BIT9 +#define SCU_STOPCFG_RCH_DIV_EN BIT8 +#define SCU_STOPCFG_MLDO12_LOWP BIT6 +#define SCU_STOPCFG_MLDO12_LV (BIT5|BIT4) +#define SCU_STOPCFG_RC64MPDEN BIT3 +#define SCU_STOPCFG_RTC_WE BIT0 + +/************** Bit definition for SCU VECTOROFFSET register *****************/ +#define SCU_VECTOROFFSET_VOFFSETEN BIT0 + +/**************** Bit definition for SCU PASEL1 register *********************/ +#define SCU_PASEL1_PA7_SEL (BIT31|BIT30|BIT29|BIT28) +#define SCU_PASEL1_PA6_SEL (BIT27|BIT26|BIT25|BIT24) +#define SCU_PASEL1_PA5_SEL (BIT23|BIT22|BIT21|BIT20) +#define SCU_PASEL1_PA4_SEL (BIT19|BIT18|BIT17|BIT16) +#define SCU_PASEL1_PA3_SEL (BIT15|BIT14|BIT13|BIT12) +#define SCU_PASEL1_PA2_SEL (BIT11|BIT10|BIT9|BIT8) +#define SCU_PASEL1_PA1_SEL (BIT7|BIT6|BIT5|BIT4) +#define SCU_PASEL1_PA0_SEL (BIT3|BIT2|BIT1|BIT0) + +/**************** Bit definition for SCU PASEL2 register *********************/ +#define SCU_PASEL2_PA15_SEL (BIT31|BIT30|BIT29|BIT28) +#define SCU_PASEL2_PA14_SEL (BIT27|BIT26|BIT25|BIT24) +#define SCU_PASEL2_PA13_SEL (BIT23|BIT22|BIT21|BIT20) +#define SCU_PASEL2_PA12_SEL (BIT19|BIT18|BIT17|BIT16) +#define SCU_PASEL2_PA11_SEL (BIT15|BIT14|BIT13|BIT12) +#define SCU_PASEL2_PA10_SEL (BIT11|BIT10|BIT9|BIT8) +#define SCU_PASEL2_PA9_SEL (BIT7|BIT6|BIT5|BIT4) +#define SCU_PASEL2_PA8_SEL (BIT3|BIT2|BIT1|BIT0) + +/**************** Bit definition for SCU PBSEL1 register *********************/ +#define SCU_PBSEL1_PB7_SEL (BIT31|BIT30|BIT29|BIT28) +#define SCU_PBSEL1_PB6_SEL (BIT27|BIT26|BIT25|BIT24) +#define SCU_PBSEL1_PB5_SEL (BIT23|BIT22|BIT21|BIT20) +#define SCU_PBSEL1_PB4_SEL (BIT19|BIT18|BIT17|BIT16) +#define SCU_PBSEL1_PB3_SEL (BIT15|BIT14|BIT13|BIT12) +#define SCU_PBSEL1_PB2_SEL (BIT11|BIT10|BIT9|BIT8) +#define SCU_PBSEL1_PB1_SEL (BIT7|BIT6|BIT5|BIT4) +#define SCU_PBSEL1_PB0_SEL (BIT3|BIT2|BIT1|BIT0) + +/**************** Bit definition for SCU PBSEL2 register *********************/ +#define SCU_PBSEL2_PB15_SEL (BIT31|BIT30|BIT29|BIT28) +#define SCU_PBSEL2_PB14_SEL (BIT27|BIT26|BIT25|BIT24) +#define SCU_PBSEL2_PB13_SEL (BIT23|BIT22|BIT21|BIT20) +#define SCU_PBSEL2_PB12_SEL (BIT19|BIT18|BIT17|BIT16) +#define SCU_PBSEL2_PB11_SEL (BIT15|BIT14|BIT13|BIT12) +#define SCU_PBSEL2_PB10_SEL (BIT11|BIT10|BIT9|BIT8) +#define SCU_PBSEL2_PB9_SEL (BIT7|BIT6|BIT5|BIT4) +#define SCU_PBSEL2_PB8_SEL (BIT3|BIT2|BIT1|BIT0) + +/**************** Bit definition for SCU PASTR register **********************/ +#define SCU_PASTR_PA15_STH (BIT31|BIT30) +#define SCU_PASTR_PA14_STH (BIT29|BIT28) +#define SCU_PASTR_PA13_STH (BIT27|BIT26) +#define SCU_PASTR_PA12_STH (BIT25|BIT24) +#define SCU_PASTR_PA11_STH (BIT23|BIT22) +#define SCU_PASTR_PA10_STH (BIT21|BIT20) +#define SCU_PASTR_PA9_STH (BIT19|BIT18) +#define SCU_PASTR_PA8_STH (BIT17|BIT16) +#define SCU_PASTR_PA7_STH (BIT15|BIT14) +#define SCU_PASTR_PA6_STH (BIT13|BIT12) +#define SCU_PASTR_PA5_STH (BIT11|BIT10) +#define SCU_PASTR_PA4_STH (BIT9|BIT8) +#define SCU_PASTR_PA3_STH (BIT7|BIT6) +#define SCU_PASTR_PA2_STH (BIT5|BIT4) +#define SCU_PASTR_PA1_STH (BIT3|BIT2) +#define SCU_PASTR_PA0_STH (BIT1|BIT0) + +/**************** Bit definition for SCU PBSTR register **********************/ +#define SCU_PBSTR_PB15_STH (BIT31|BIT30) +#define SCU_PBSTR_PB14_STH (BIT29|BIT28) +#define SCU_PBSTR_PB13_STH (BIT27|BIT26) +#define SCU_PBSTR_PB12_STH (BIT25|BIT24) +#define SCU_PBSTR_PB11_STH (BIT23|BIT22) +#define SCU_PBSTR_PB10_STH (BIT21|BIT20) +#define SCU_PBSTR_PB9_STH (BIT19|BIT18) +#define SCU_PBSTR_PB8_STH (BIT17|BIT16) +#define SCU_PBSTR_PB7_STH (BIT15|BIT14) +#define SCU_PBSTR_PB6_STH (BIT13|BIT12) +#define SCU_PBSTR_PB5_STH (BIT11|BIT10) +#define SCU_PBSTR_PB4_STH (BIT9|BIT8) +#define SCU_PBSTR_PB3_STH (BIT7|BIT6) +#define SCU_PBSTR_PB2_STH (BIT5|BIT4) +#define SCU_PBSTR_PB1_STH (BIT3|BIT2) +#define SCU_PBSTR_PB0_STH (BIT1|BIT0) + +/**************** Bit definition for SCU PCSEL1 register *********************/ +#define SCU_PCSEL1_PC7_SEL (BIT31|BIT30|BIT29|BIT28) +#define SCU_PCSEL1_PC6_SEL (BIT27|BIT26|BIT25|BIT24) +#define SCU_PCSEL1_PC5_SEL (BIT23|BIT22|BIT21|BIT20) +#define SCU_PCSEL1_PC4_SEL (BIT19|BIT18|BIT17|BIT16) +#define SCU_PCSEL1_PC3_SEL (BIT15|BIT14|BIT13|BIT12) +#define SCU_PCSEL1_PC2_SEL (BIT11|BIT10|BIT9|BIT8) +#define SCU_PCSEL1_PC1_SEL (BIT7|BIT6|BIT5|BIT4) +#define SCU_PCSEL1_PC0_SEL (BIT3|BIT2|BIT1|BIT0) + +/**************** Bit definition for SCU PCSEL2 register *********************/ +#define SCU_PCSEL2_PC15_SEL (BIT31|BIT30|BIT29|BIT28) +#define SCU_PCSEL2_PC14_SEL (BIT27|BIT26|BIT25|BIT24) +#define SCU_PCSEL2_PC13_SEL (BIT23|BIT22|BIT21|BIT20) +#define SCU_PCSEL2_PC12_SEL (BIT19|BIT18|BIT17|BIT16) +#define SCU_PCSEL2_PC11_SEL (BIT15|BIT14|BIT13|BIT12) +#define SCU_PCSEL2_PC10_SEL (BIT11|BIT10|BIT9|BIT8) +#define SCU_PCSEL2_PC9_SEL (BIT7|BIT6|BIT5|BIT4) +#define SCU_PCSEL2_PC8_SEL (BIT3|BIT2|BIT1|BIT0) + +/**************** Bit definition for SCU PDSEL1 register *********************/ +#define SCU_PDSEL1_PD7_SEL (BIT31|BIT30|BIT29|BIT28) +#define SCU_PDSEL1_PD6_SEL (BIT27|BIT26|BIT25|BIT24) +#define SCU_PDSEL1_PD5_SEL (BIT23|BIT22|BIT21|BIT20) +#define SCU_PDSEL1_PD4_SEL (BIT19|BIT18|BIT17|BIT16) +#define SCU_PDSEL1_PD3_SEL (BIT15|BIT14|BIT13|BIT12) +#define SCU_PDSEL1_PD2_SEL (BIT11|BIT10|BIT9|BIT8) +#define SCU_PDSEL1_PD1_SEL (BIT7|BIT6|BIT5|BIT4) +#define SCU_PDSEL1_PD0_SEL (BIT3|BIT2|BIT1|BIT0) + +/**************** Bit definition for SCU PCSTR register **********************/ +#define SCU_PCSTR_PC12_STH (BIT25|BIT24) +#define SCU_PCSTR_PC11_STH (BIT23|BIT22) +#define SCU_PCSTR_PC10_STH (BIT21|BIT20) +#define SCU_PCSTR_PC9_STH (BIT19|BIT18) +#define SCU_PCSTR_PC8_STH (BIT17|BIT16) +#define SCU_PCSTR_PC7_STH (BIT15|BIT14) +#define SCU_PCSTR_PC6_STH (BIT13|BIT12) +#define SCU_PCSTR_PC5_STH (BIT11|BIT10) +#define SCU_PCSTR_PC4_STH (BIT9|BIT8) +#define SCU_PCSTR_PC3_STH (BIT7|BIT6) +#define SCU_PCSTR_PC2_STH (BIT5|BIT4) +#define SCU_PCSTR_PC1_STH (BIT3|BIT2) +#define SCU_PCSTR_PC0_STH (BIT1|BIT0) + +/**************** Bit definition for SCU PDSTR register **********************/ +#define SCU_PDSTR_PD7_STH (BIT15|BIT14) +#define SCU_PDSTR_PD6_STH (BIT13|BIT12) +#define SCU_PDSTR_PD5_STH (BIT11|BIT10) +#define SCU_PDSTR_PD4_STH (BIT9|BIT8) +#define SCU_PDSTR_PD3_STH (BIT7|BIT6) +#define SCU_PDSTR_PD2_STH (BIT5|BIT4) +#define SCU_PDSTR_PD1_STH (BIT3|BIT2) +#define SCU_PDSTR_PD0_STH (BIT1|BIT0) + +/* + * @brief Peripheral Enable structures definition + */ +typedef enum +{ + EN_CAN1 = 45, + EN_ROM = 44, + EN_HRNG = 43, + EN_AES = 42, + EN_TIM17 = 41, + EN_TIM16 = 40, + EN_TIM15 = 39, + EN_TIM14 = 38, + EN_TIM7 = 37, + EN_TIM6 = 36, + EN_TIM3 = 35, + EN_TIM1 = 34, + EN_UART3 = 33, + EN_TIM2 = 32, + EN_OPA = 31, + EN_COMP = 30, + EN_TKEY = 29, + EN_ADC = 28, + EN_RTC = 27, + EN_DMA = 26, + EN_CRC = 25, + EN_DAC = 24, + EN_USB = 23, + EN_LPUART = 22, + EN_I2C2 = 21, + EN_I2C1 = 20, + EN_SPI2 = 19, + EN_SPI1 = 18, + EN_UART2 = 17, + EN_UART1 = 16, + EN_CAN2 = 15, + EN_I2S1 = 14, + + EN_SPI4 = 13, + EN_GPIOEF = 12, + EN_SPI3 = 11, + EN_UART4 = 10, + EN_TIM4 = 9, + EN_FAU = 8, + EN_EFC = 6, + EN_SRAM = 5, + EN_EXTI = 4, + EN_IWDT = 3, + EN_WDT = 2, + EN_GPIOCD = 1, + EN_GPIOAB = 0, +}enum_Enable_ID_t; + +typedef enum +{ + RESET_REASON_LOW_VOLTAGE = 0x00U, // low voltage detected, leads to reset + RESET_REASON_WDT = 0x01U, // System WDT reset + RESET_REASON_IWDT = 0x02U, // IWDT reset + RESET_REASON_LOCKUP = 0x03U, // cortex-m0 lockup leads to reset + RESET_REASON_SYSREQ = 0x04U, // system reset + RESET_REASON_RSTN = 0x05U, // RSTN negative pulse leads to reset + RESET_REASON_EFC = 0x06U, // efc reset leads to reset + RESET_REASON_SOFT = 0x07U, // soft reset + RESET_REASON_POR12 = 0x09U, // core power on reset, rtc not reset, eg:wakeup from standby + RESET_REASON_POR = 0x0AU, // chip power on reset + RESET_REASON_INVALID, +}RESET_REASON; + +#define NVIC_PRIORITY_GROUP_3 0x00000004U // 3 bits for pre-emption priority, 0 bit for subpriority +#define NVIC_PRIORITY_GROUP_2 0x00000005U // 2 bits for pre-emption priority, 1 bit for subpriority +#define NVIC_PRIORITY_GROUP_1 0x00000006U // 1 bits for pre-emption priority, 2 bit for subpriority +#define NVIC_PRIORITY_GROUP_0 0x00000007U // 0 bits for pre-emption priority, 3 bit for subpriority + +#define SYSTEM_TIMEOUT (1000000) + + +/* System_Init */ +void System_Init(void); + +/* System_Core_Config */ +void System_Core_Config(void); + +/* System_Clock_Init */ +bool System_Clock_Init(uint32_t fu32_Clock); + +/* System_SysTick_Init */ +void System_SysTick_Init(void); + +/* System_Get_SystemClock */ +uint32_t System_Get_SystemClock(void); + +/* System_Get_APBClock */ +uint32_t System_Get_APBClock(void); + +/* System_Module_Reset */ +void System_Module_Reset(enum_RST_ID_t fe_ID_Index); + +/* System_Module_Enable */ +void System_Module_Enable(enum_Enable_ID_t fe_ID_Index); + +/* System_Module_Disable */ +void System_Module_Disable(enum_Enable_ID_t fe_ID_Index); + +/* System_Delay */ +void System_Delay(volatile uint32_t fu32_Delay); + +/* System_Delay_MS */ +void System_Delay_MS(volatile uint32_t fu32_Delay); + +/* System_Enable_RC32K */ +void System_Enable_RC32K(void); + +/* System_Disable_RC32K */ +void System_Disable_RC32K(void); + +/* System_Enable_XTAL */ +void System_Enable_XTAL(void); + +/* System_Disable_XTAL */ +void System_Disable_XTAL(void); + +/* System_Clear_Stop_Wakeup */ +void System_Clear_Stop_Wakeup(void); + +/* System_Enter_Standby_Mode */ +void System_Enter_Standby_Mode(void); + +/* System_Enter_Stop_Mode */ +void System_Enter_Stop_Mode(uint8_t STOPEntry); + +/* System_Enter_Sleep_Mode */ +void System_Enter_Sleep_Mode(uint8_t SleepEntry); + +/* System_Enable_Disable_Reset */ +void System_Enable_Disable_Reset(RESET_ENABLE_SOURCE source, FUNC_DISABLE_ENABLE enable_disable); + +/* System_Reset_MCU */ +void System_Reset_MCU(RESET_SOURCE source); + +/* System_Enable_Disable_RTC_Domain_Access */ +void System_Enable_Disable_RTC_Domain_Access(FUNC_DISABLE_ENABLE enable_disable); + +/* System_Return_Last_Reset_Reason */ +RESET_REASON System_Return_Last_Reset_Reason(void) ; + +/* System_Set_Buzzer_Divider */ +void System_Set_Buzzer_Divider(uint32_t div, FUNC_DISABLE_ENABLE enable); + +/* System_USB_PHY_Config */ +uint32_t System_USB_PHY_Config(void); + +#endif + + + + diff --git a/bsp/acm32f4xx-nucleo/libraries/Device/System_Accelerate.h b/bsp/acm32f4xx-nucleo/libraries/Device/System_Accelerate.h new file mode 100644 index 0000000000..4e0c2a6fa7 --- /dev/null +++ b/bsp/acm32f4xx-nucleo/libraries/Device/System_Accelerate.h @@ -0,0 +1,28 @@ +/* + ****************************************************************************** + * @file System_Accelerate.h + * @version V1.0.0 + * @date 2020 + * @brief MCU Accelerate Peripheral Access Layer System header File. + ****************************************************************************** +*/ +#ifndef __SYSTEM_ACCELERATE_H__ +#define __SYSTEM_ACCELERATE_H__ + + + +/* System_EnableIAccelerate */ +void System_EnableIAccelerate(void); + +/* System_DisableIAccelerate */ +void System_DisableIAccelerate(void); + +/* System_EnableDAccelerate */ +void System_EnableDAccelerate(void); + +/* System_DisableDAccelerate */ +void System_DisableDAccelerate(void); + + +#endif + diff --git a/bsp/acm32f4xx-nucleo/libraries/Device/startup_ACM32F4_gcc.s b/bsp/acm32f4xx-nucleo/libraries/Device/startup_ACM32F4_gcc.s new file mode 100644 index 0000000000..2dd0e3e75e --- /dev/null +++ b/bsp/acm32f4xx-nucleo/libraries/Device/startup_ACM32F4_gcc.s @@ -0,0 +1,344 @@ +/*********************** (C) COPYRIGHT 2020 Aisinochip ************************* +;* File Name : Startup_ACM32F4.s +;* Author : AisinoChip Firmware Team +;* Version : V1.0.0 +;* Date : 2020 +;* Description : ACM32F4 Devices vector table for GCC toolchain. +;* This module performs: +;* - Set the initial SP +;* - Set the initial PC == Reset_Handler +;* - Set the vector table entries with the exceptions ISR address +;* - Configure the clock system +;* - Branches to __main in the C library (which eventually +;* calls main()). +;* After Reset the Cortex-M33 processor is in Thread mode, +;* priority is Privileged, and the Stack is set to Main. +;******************************************************************************** +;* @attention +;* +;* Copyright (c) 2020 AisinoChip. +;* All rights reserved. +;*******************************************************************************/ + + .syntax unified + .cpu cortex-m33 + .fpu softvfp + .thumb + +.global g_pfnVectors +.global Default_Handler + +/* start address for the initialization values of the .data section. +defined in linker script */ +.word _sidata +/* start address for the .data section. defined in linker script */ +.word _sdata +/* end address for the .data section. defined in linker script */ +.word _edata +/* start address for the .bss section. defined in linker script */ +.word _sbss +/* end address for the .bss section. defined in linker script */ +.word _ebss + +/*.equ BootRAM, 0xF108F85F */ + +/** + * @brief This is the code that gets called when the processor first + * starts execution following a reset event. Only the absolutely + * necessary set is performed, after which the application + * supplied main() routine is called. + * @param None + * @retval : None +*/ + + .section .text.Reset_Handler + .weak Reset_Handler + .type Reset_Handler, %function +Reset_Handler: + +/* Copy the data segment initializers from flash to SRAM */ + movs r1, #0 + b LoopCopyDataInit + +CopyDataInit: + ldr r3, =_sidata + ldr r3, [r3, r1] + str r3, [r0, r1] + adds r1, r1, #4 + +LoopCopyDataInit: + ldr r0, =_sdata + ldr r3, =_edata + adds r2, r0, r1 + cmp r2, r3 + bcc CopyDataInit + ldr r2, =_sbss + b LoopFillZerobss +/* Zero fill the bss segment. */ +FillZerobss: + movs r3, #0 + str r3, [r2], #4 + +LoopFillZerobss: + ldr r3, = _ebss + cmp r2, r3 + bcc FillZerobss + +/* Call the clock system intitialization function.*/ + /* bl SystemInit */ +/* Call static constructors */ + /* bl __libc_init_array */ +/* Call the application's entry point.*/ + bl entry + bx lr +.size Reset_Handler, .-Reset_Handler + +/** + * @brief This is the code that gets called when the processor receives an + * unexpected interrupt. This simply enters an infinite loop, preserving + * the system state for examination by a debugger. + * + * @param None + * @retval : None +*/ + .section .text.Default_Handler,"ax",%progbits +Default_Handler: +Infinite_Loop: + b Infinite_Loop + .size Default_Handler, .-Default_Handler +/****************************************************************************** +* +* The minimal vector table for a Cortex M3. Note that the proper constructs +* must be placed on this to ensure that it ends up at physical address +* 0x0000.0000. +* +******************************************************************************/ + .section .isr_vector,"a",%progbits + .type g_pfnVectors, %object + .size g_pfnVectors, .-g_pfnVectors + + +g_pfnVectors: + + .word _estack + .word Reset_Handler + .word NMI_Handler + .word HardFault_Handler + .word MemManage_Handler + .word BusFault_Handler + .word UsageFault_Handler + .word 0 + .word 0 + .word 0 + .word 0 + .word SVC_Handler + .word DebugMon_Handler + .word 0 + .word PendSV_Handler + .word SysTick_Handler + + /* External Interrupts */ + .word WDT_IRQHandler + .word RTC_IRQHandler + .word EFC_IRQHandler + .word GPIOAB_IRQHandler + .word GPIOCD_IRQHandler + .word EXIT_IRQHandler + .word SRAM_PAPITY_IRQHandler + .word CLKRDY_IRQHandler + .word UART4_IRQHandler + .word DMA_IRQHandler + .word UART3_IRQHandler + .word RSV_IRQHandler + .word ADC_IRQHandler + .word TIM1_BRK_UP_TRG_COM_IRQHandler + .word TIM1_CC_IRQHandler + .word TIM2_IRQHandler + .word TIM3_IRQHandler + .word TIM6_IRQHandler + .word TIM7_IRQHandler + .word TIM14_IRQHandler + .word TIM15_IRQHandler + .word TIM16_IRQHandler + .word TIM17_IRQHandler + .word I2C1_IRQHandler + .word I2C2_IRQHandler + .word SPI1_IRQHandler + .word SPI2_IRQHandler + .word UART1_IRQHandler + .word UART2_IRQHandler + .word LPUART_IRQHandler + .word SPI3_IRQHandler + .word AES_IRQHandler + .word USB_IRQHandler + .word DAC_IRQHandler + .word I2S_IRQHandler + .word GPIOEF_IRQHandler + .word CAN1_IRQHandler + .word CAN2_IRQHandler + .word FPU_IRQHandler + .word TIM4_IRQHandler + .word SPI4_IRQHandler + + + +/******************************************************************************* +* +* Provide weak aliases for each Exception handler to the Default_Handler. +* As they are weak aliases, any function with the same name will override +* this definition. +* +*******************************************************************************/ + + .weak NMI_Handler + .thumb_set NMI_Handler,Default_Handler + + .weak HardFault_Handler + .thumb_set HardFault_Handler,Default_Handler + + .weak MemManage_Handler + .thumb_set MemManage_Handler,Default_Handler + + .weak BusFault_Handler + .thumb_set BusFault_Handler,Default_Handler + + .weak UsageFault_Handler + .thumb_set UsageFault_Handler,Default_Handler + + .weak SVC_Handler + .thumb_set SVC_Handler,Default_Handler + + .weak DebugMon_Handler + .thumb_set DebugMon_Handler,Default_Handler + + .weak PendSV_Handler + .thumb_set PendSV_Handler,Default_Handler + + .weak SysTick_Handler + .thumb_set SysTick_Handler,Default_Handler + + .weak WDT_IRQHandler + .thumb_set WDT_IRQHandler,Default_Handler + + .weak RTC_IRQHandler + .thumb_set RTC_IRQHandler,Default_Handler + + .weak EFC_IRQHandler + .thumb_set EFC_IRQHandler,Default_Handler + + .weak GPIOAB_IRQHandler + .thumb_set GPIOAB_IRQHandler,Default_Handler + + .weak GPIOCD_IRQHandler + .thumb_set GPIOCD_IRQHandler,Default_Handler + + .weak EXIT_IRQHandler + .thumb_set EXIT_IRQHandler,Default_Handler + + .weak SRAM_PAPITY_IRQHandler + .thumb_set SRAM_PAPITY_IRQHandler,Default_Handler + + .weak CLKRDY_IRQHandler + .thumb_set CLKRDY_IRQHandler,Default_Handler + + .weak UART4_IRQHandler + .thumb_set UART4_IRQHandler,Default_Handler + + .weak DMA_IRQHandler + .thumb_set DMA_IRQHandler,Default_Handler + + .weak UART3_IRQHandler + .thumb_set UART3_IRQHandler,Default_Handler + + .weak RSV_IRQHandler + .thumb_set RSV_IRQHandler,Default_Handler + + .weak ADC_IRQHandler + .thumb_set ADC_IRQHandler,Default_Handler + + .weak TIM1_BRK_UP_TRG_COM_IRQHandler + .thumb_set TIM1_BRK_UP_TRG_COM_IRQHandler,Default_Handler + + .weak TIM1_CC_IRQHandler + .thumb_set TIM1_CC_IRQHandler,Default_Handler + + .weak TIM2_IRQHandler + .thumb_set TIM2_IRQHandler,Default_Handler + + .weak TIM3_IRQHandler + .thumb_set TIM3_IRQHandler,Default_Handler + + .weak TIM6_IRQHandler + .thumb_set TIM6_IRQHandler,Default_Handler + + .weak TIM7_IRQHandler + .thumb_set TIM7_IRQHandler,Default_Handler + + .weak TIM14_IRQHandler + .thumb_set TIM14_IRQHandler,Default_Handler + + .weak TIM15_IRQHandler + .thumb_set TIM15_IRQHandler,Default_Handler + + .weak TIM16_IRQHandler + .thumb_set TIM16_IRQHandler,Default_Handler + + .weak TIM17_IRQHandler + .thumb_set TIM17_IRQHandler,Default_Handler + + .weak I2C1_IRQHandler + .thumb_set I2C1_IRQHandler,Default_Handler + + .weak I2C2_IRQHandler + .thumb_set I2C2_IRQHandler,Default_Handler + + .weak SPI1_IRQHandler + .thumb_set SPI1_IRQHandler,Default_Handler + + .weak SPI2_IRQHandler + .thumb_set SPI2_IRQHandler,Default_Handler + + .weak UART1_IRQHandler + .thumb_set UART1_IRQHandler,Default_Handler + + .weak UART2_IRQHandler + .thumb_set UART2_IRQHandler,Default_Handler + + .weak LPUART_IRQHandler + .thumb_set LPUART_IRQHandler,Default_Handler + + .weak SPI3_IRQHandler + .thumb_set SPI3_IRQHandler,Default_Handler + + .weak AES_IRQHandler + .thumb_set AES_IRQHandler,Default_Handler + + .weak USB_IRQHandler + .thumb_set USB_IRQHandler,Default_Handler + + .weak DAC_IRQHandler + .thumb_set DAC_IRQHandler,Default_Handler + + .weak I2S_IRQHandler + .thumb_set I2S_IRQHandler,Default_Handler + + .weak GPIOEF_IRQHandler + .thumb_set GPIOEF_IRQHandler,Default_Handler + + .weak CAN1_IRQHandler + .thumb_set CAN1_IRQHandler,Default_Handler + + .weak CAN2_IRQHandler + .thumb_set CAN2_IRQHandler,Default_Handler + + .weak FPU_IRQHandler + .thumb_set FPU_IRQHandler,Default_Handler + + .weak TIM4_IRQHandler + .thumb_set TIM4_IRQHandler,Default_Handler + + .weak SPI4_IRQHandler + .thumb_set SPI4_IRQHandler,Default_Handler + + + diff --git a/bsp/acm32f4xx-nucleo/libraries/HAL_Driver/Inc/ACM32Fxx_HAL.h b/bsp/acm32f4xx-nucleo/libraries/HAL_Driver/Inc/ACM32Fxx_HAL.h new file mode 100644 index 0000000000..ea5b28ffbd --- /dev/null +++ b/bsp/acm32f4xx-nucleo/libraries/HAL_Driver/Inc/ACM32Fxx_HAL.h @@ -0,0 +1,207 @@ +/* + ****************************************************************************** + * @file ACM32Fxx_HAL.h + * @version V1.0.0 + * @date 2020 + * @brief HAL Config header file. + ****************************************************************************** +*/ +#ifndef __ACM32FXX_HAL_H__ +#define __ACM32FXX_HAL_H__ + +/* + Uncomment the line below according to the target device used in your application +*/ +/* #define ACM32F3XX */ /*!< ACM32F303xx */ + #define ACM32F4XX /*!< ACM32F403xx */ +/* #define ACM32FPXX */ /*!< ACM32FP400xx ACM32FP401xx */ + + +/** @addtogroup Device_Included + * @{ + */ +#if defined(ACM32F3XX) + #include "ACM32F3.h" +#elif defined(ACM32F4XX) + #include "ACM32F4.h" +#elif defined(ACM32FPXX) + #include "ACM32FP.h" +#else + #error "Please select first the target device used in your application (in ACM32Fxx_HAL.h file)" +#endif +/** + * @} + */ + + +/* + * @brief HAL Status structures definition + */ +typedef enum +{ + HAL_OK = 0x00U, + HAL_ERROR = 0x01U, + HAL_BUSY = 0x02U, + HAL_TIMEOUT = 0x03U +}HAL_StatusTypeDef; + + +//#if defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) /* ARM Compiler V6 */ + #ifndef __weak + #define __weak __attribute__((weak)) + #endif +//#endif + + +/* USE FULL ASSERT */ +#define USE_FULL_ASSERT (1) + + +#define HAL_DMA_MODULE_ENABLED +#define HAL_GPIO_MODULE_ENABLED +#define HAL_UART_MODULE_ENABLED +#define HAL_ADC_MODULE_ENABLED +#define HAL_DAC_MODULE_ENABLED +#define HAL_EXTI_MODULE_ENABLED +#define HAL_I2C_MODULE_ENABLED +#define HAL_I2S_MODULE_ENABLED +#define HAL_IWDT_MODULE_ENABLED +#define HAL_RTC_MODULE_ENABLED +#define HAL_SPI_MODULE_ENABLED +#define HAL_TIMER_MODULE_ENABLED +#define HAL_EFLASH_MODULE_ENABLED +#ifdef ACM32F4XX +#define HAL_OPA_MODULE_ENABLED +#endif +#ifndef ACM32FPXX +#define HAL_COMP_MODULE_ENABLED +#define HAL_CAN_MODULE_ENABLED +#endif +#define HAL_LPUART_MODULE_ENABLED +#define HAL_WDT_MODULE_ENABLED +#define HAL_FSUSB_MODULE_ENABLED +#define HAL_SYSTICK_ENABLED +#define HAL_CRC_ENABLED +#define HAL_FAU_ENABLED +#define HAL_AES_ENABLED +#define HAL_HASH_SHA1_ENABLED +#define HAL_HASH_SHA256_ENABLED +#define HAL_HRNG_ENABLED + +#if defined(ACM32F3XX) + #include "System_ACM32F3.h" +#elif defined(ACM32F4XX) + #include "System_ACM32F4.h" +#elif defined(ACM32FPXX) + #include "System_ACM32FP.h" +#else + #error "Please select first the target device used in your application (in ACM32Fxx_HAL.h file)" +#endif + +#include "System_Accelerate.h" + +#ifdef HAL_DMA_MODULE_ENABLED + #include "HAL_DMA.h" +#endif + +#ifdef HAL_GPIO_MODULE_ENABLED + #include "HAL_GPIO.h" +#endif + +#ifdef HAL_UART_MODULE_ENABLED + #include "HAL_UART.h" + #include "HAL_UART_EX.h" +#endif + +#ifdef HAL_ADC_MODULE_ENABLED + #include "HAL_ADC.h" +#endif + +#ifdef HAL_DAC_MODULE_ENABLED + #include "HAL_DAC.h" +#endif + +#ifdef HAL_EXTI_MODULE_ENABLED + #include "HAL_EXTI.h" +#endif + +#ifdef HAL_I2C_MODULE_ENABLED + #include "HAL_I2C.h" +#endif + +#ifdef HAL_I2S_MODULE_ENABLED + #include "HAL_I2S.h" +#endif + +#ifdef HAL_RTC_MODULE_ENABLED + #include "HAL_RTC.h" +#endif + +#ifdef HAL_SPI_MODULE_ENABLED + #include "HAL_SPI.h" +#endif + +#ifdef HAL_IWDT_MODULE_ENABLED + #include "HAL_IWDT.h" +#endif + +#ifdef HAL_EFLASH_MODULE_ENABLED + #include "HAL_EFlash.h" + #include "HAL_EFlash_EX.h" +#endif + +#ifdef HAL_OPA_MODULE_ENABLED + #include "HAL_OPA.h" +#endif + +#ifdef HAL_COMP_MODULE_ENABLED + #include "HAL_COMP.h" +#endif + +#ifdef HAL_CAN_MODULE_ENABLED + #include "HAL_CAN.h" +#endif + +#ifdef HAL_LPUART_MODULE_ENABLED + #include "HAL_LPUART.h" +#endif + +#ifdef HAL_WDT_MODULE_ENABLED + #include "HAL_WDT.h" +#endif + +#ifdef HAL_TIMER_MODULE_ENABLED + #include "HAL_TIMER.h" + #include "HAL_TIMER_EX.h" +#endif + +#ifdef HAL_FSUSB_MODULE_ENABLED + #include "HAL_FSUSB.h" +#endif + +#ifdef HAL_CRC_ENABLED +#include "HAL_CRC.h" +#endif + +#ifdef HAL_AES_ENABLED +#include "HAL_AES.h" +#endif + +#ifdef HAL_FAU_ENABLED +#include "HAL_FAU.h" +#endif + +#ifdef HAL_HASH_SHA1_ENABLED +#include "HAL_SHA1.h" +#endif + +#ifdef HAL_HASH_SHA256_ENABLED +#include "HAL_SHA256.h" +#endif + +#ifdef HAL_HRNG_ENABLED +#include "HAL_HRNG.h" +#endif + + +#endif diff --git a/bsp/acm32f4xx-nucleo/libraries/HAL_Driver/Inc/HAL_ADC.h b/bsp/acm32f4xx-nucleo/libraries/HAL_Driver/Inc/HAL_ADC.h new file mode 100644 index 0000000000..48e6e6e1af --- /dev/null +++ b/bsp/acm32f4xx-nucleo/libraries/HAL_Driver/Inc/HAL_ADC.h @@ -0,0 +1,637 @@ +/* + ****************************************************************************** + * @file HAL_ADC.h + * @version V1.0.0 + * @date 2020 + * @brief Header file of ADC HAL module. + ****************************************************************************** +*/ +#ifndef __HAL_ADC_H__ +#define __HAL_ADC_H__ + +#include "ACM32Fxx_HAL.h" + +/**************** Total definition for ADC **************************/ +#define ADC_CH_MASK (BIT4|BIT3|BIT2|BIT1|BIT0) + +/**************** Bit definition for ADC_SR register **************************/ +#define ADC_SR_AWD (BIT5) +#define ADC_SR_OVERF (BIT4) +#define ADC_SR_EOG (BIT3) +#define ADC_SR_JEOC (BIT2) +#define ADC_SR_EOC (BIT1) +#define ADC_SR_ADRDY (BIT0) + +/**************** Bit definition for ADC_IE register **************************/ +#define ADC_IE_AWDIE (BIT5) +#define ADC_IE_OVERFIE (BIT4) +#define ADC_IE_EOGIE (BIT3) +#define ADC_IE_JEOCIE (BIT2) +#define ADC_IE_EOCIE (BIT1) + +/**************** Bit definition for ADC_CR1 register **************************/ +#define ADC_CR1_AWDJCH_POS (27U) +#define ADC_CR1_AWDJCH_MASK (BIT31|BIT30|BIT29|BIT28|BIT27) +#define ADC_CR1_DISCNUM_POS (23U) +#define ADC_CR1_DISCNUM_MASK (BIT26|BIT25|BIT24|BIT23) +#define ADC_CR1_DISCEN BIT22 +#define ADC_CR1_CONT BIT21 +#define ADC_CR1_SWSTART BIT20 +#define ADC_CR1_JSWSTART BIT19 +#define ADC_CR1_EXTSEL_POS (16U) +#define ADC_CR1_EXTSEL_MASK (BIT18|BIT17|BIT16) +#define ADC_CR1_JEXTSEL_POS (13U) +#define ADC_CR1_JEXTSEL_MASK (BIT15|BIT14|BIT13) +#define ADC_CR1_DMA BIT12 +#define ADC_CR1_AWDEN BIT11 +#define ADC_CR1_JAWDEN BIT10 +#define ADC_CR1_JEN BIT9 +#define ADC_CR1_AWDSGL BIT8 +#define ADC_CR1_AWDCH_POS (0U) +#define ADC_CR1_AWDCH_MASK (BIT4|BIT3|BIT2|BIT1|BIT0) + +/**************** Bit definition for ADC_CR2 register **************************/ +#define ADC_CR2_FASTMOD BIT27 +#define ADC_CR2_AFE_RSTN BIT26 +#define ADC_CR2_JOVSE BIT25 +#define ADC_CR2_JTOVS BIT24 +#define ADC_CR2_OVSS_POS (20U) +#define ADC_CR2_OVSS_MASK (BIT23|BIT22|BIT21|BIT20) +#define ADC_CR2_OVSR_POS (17U) +#define ADC_CR2_OVSR_MASK (BIT19|BIT18|BIT17) +#define ADC_CR2_OVSE BIT16 +#define ADC_CR2_BUF_STIME_POS (8U) +#define ADC_CR2_BUF_STIME_MASK (BIT15|BIT14|BIT13|BIT12|BIT11|BIT10|BIT9|BIT8) +#define ADC_CR2_EN_BUF BIT7 +#define ADC_CR2_DIV_POS (3U) +#define ADC_CR2_DIV_MASK (BIT6|BIT5|BIT4|BIT3) +#define ADC_CR2_ADC_STP BIT2 +#define ADC_CR2_OVRMOD BIT1 +#define ADC_CR2_ADC_EN BIT0 + +/**************** Bit definition for ADC_SMPR1 register **************************/ +#define ADC_SMPR_CH_MASK (BIT3|BIT2|BIT1|BIT0) + +/**************** Bit definition for ADC_DIFF register **************************/ +#define ADC_DIFF_DIFF7_F BIT7 +#define ADC_DIFF_DIFF6_E BIT6 +#define ADC_DIFF_DIFF5_D BIT5 +#define ADC_DIFF_DIFF4_C BIT4 +#define ADC_DIFF_DIFF3_B BIT3 +#define ADC_DIFF_DIFF2_A BIT2 +#define ADC_DIFF_DIFF1_9 BIT1 +#define ADC_DIFF_DIFF0_8 BIT0 + +/**************** Bit definition for ADC_HTR register ***********************/ +#define ADC_HTR_DHT (BIT27|BIT26|BIT25|BIT24|BIT23|BIT22|BIT21|BIT20|BIT19|BIT18|BIT17|BIT16) +#define ADC_HTR_HT (BIT11|BIT10|BIT9|BIT8|BIT7|BIT6|BIT5|BIT4|BIT3|BIT2|BIT1|BIT0) + +/**************** Bit definition for ADC_LTR register ***********************/ +#define ADC_LTR_DLT (BIT27|BIT26|BIT25|BIT24|BIT23|BIT22|BIT21|BIT20|BIT19|BIT18|BIT17|BIT16) +#define ADC_LTR_LT (BIT11|BIT10|BIT9|BIT8|BIT7|BIT6|BIT5|BIT4|BIT3|BIT2|BIT1|BIT0) + +/**************** Bit definition for ADC_SQR1 register ***********************/ +#define ADC_SQR1_L (BIT3|BIT2|BIT1|BIT0) + +/**************** Bit definition for ADC_JSQR register ***********************/ +#define ADC_JSQR_JSQ (BIT4|BIT3|BIT2|BIT1|BIT0) + +/**************** Bit definition for ADC_JDR register ***********************/ +#define ADC_JDR_JCH (BIT20|BIT19|BIT18|BIT17|BIT16) + +/**************** Bit definition for ADC_DR register ***********************/ +#define ADC_DR_CH (BIT20|BIT19|BIT18|BIT17|BIT16) + +/**************** Bit definition for ADC_SIGN register ***********************/ +#define ADC_SIGN_SIGN7_F BIT7 +#define ADC_SIGN_SIGN6_E BIT6 +#define ADC_SIGN_SIGN5_D BIT5 +#define ADC_SIGN_SIGN4_C BIT4 +#define ADC_SIGN_SIGN3_B BIT3 +#define ADC_SIGN_SIGN2_A BIT2 +#define ADC_SIGN_SIGN1_9 BIT1 +#define ADC_SIGN_SIGN0_8 BIT0 + +/**************** Bit definition for ADC_TSREF register ***********************/ +#define ADC_TSREF_HIZ_EN BIT27 +#define ADC_TSREF_VREFBI_SEL_POS (25U) +#define ADC_TSREF_VREFBI_SEL_MASK (BIT26|BIT25) +#define ADC_TSREF_VREFBI_EN BIT24 +#define ADC_TSREF_VTRIM_POS (19U) +#define ADC_TSREF_VTRIM_MASK (BIT23|BIT22|BIT21|BIT20|BIT19) +#define ADC_TSREF_TTRIM_POS (15U) +#define ADC_TSREF_TTRIM_MASK (BIT18|BIT17|BIT16|BIT15) +#define ADC_TSREF_ALG_MEAN_POS (9U) +#define ADC_TSREF_ALG_MEAN_MASK (BIT10|BIT9) +#define ADC_TSREF_ADJ_TD_OS_POS (5U) +#define ADC_TSREF_ADJ_TD_OS_MASK (BIT8|BIT7|BIT6|BIT5) +#define ADC_TSREF_ADJ_TD_GA_POS (1U) +#define ADC_TSREF_ADJ_TD_GA_MASK (BIT4|BIT3|BIT2|BIT1) +#define ADC_TSREF_EN_TS BIT0 + +/**************** Macro definition for register operation **************************/ + + +/**************** Enable the specified ADC. **************************/ +#define __HAL_ADC_ENABLE(__HANDLE__) \ + (SET_BIT((__HANDLE__)->Instance->CR2, (ADC_CR2_ADC_EN))) + +/**************** Disable the specified ADC. **************************/ +#define __HAL_ADC_DISABLE(__HANDLE__) \ + (CLEAR_BIT((__HANDLE__)->Instance->CR2, (ADC_CR2_ADC_EN))) + +/**************** Enable the specified ADC interrupt source. **************************/ +#define __HAL_ADC_ENABLE_IT(__HANDLE__, __INTERRUPT__) \ + (SET_BIT((__HANDLE__)->Instance->IE, (__INTERRUPT__))) + +/**************** Disable the specified ADC interrupt source. **************************/ +#define __HAL_ADC_DISABLE_IT(__HANDLE__, __INTERRUPT__) \ + (CLEAR_BIT((__HANDLE__)->Instance->IE, (__INTERRUPT__))) + +/**************** Checks if the specified ADC interrupt source is enabled or disabled. **************************/ +#define __HAL_ADC_GET_IT_SOURCE(__HANDLE__, __INTERRUPT__) \ + (((__HANDLE__)->Instance->IE & (__INTERRUPT__)) == (__INTERRUPT__)) + +/**************** Get the selected ADC's flag status. **************************/ +#define __HAL_ADC_GET_FLAG(__HANDLE__, __FLAG__) \ + ((((__HANDLE__)->Instance->SR) & (__FLAG__)) == (__FLAG__)) + +/**************** Clear the selected ADC's flag status. **************************/ +#define __HAL_ADC_CLEAR_FLAG(__HANDLE__, __FLAG__) \ + (SET_BIT((__HANDLE__)->Instance->SR, (__FLAG__))) + +/**************** Checks if the ADC regular group trig source is the specified source. **************************/ +#define __HAL_ADC_CHECK_TRIG_REGULAR(__HANDLE__, __TRIGSOURCE__) \ + ((((__HANDLE__)->Instance->CR1 & ADC_CR1_EXTSEL_MASK) >> ADC_CR1_EXTSEL_POS) == (__TRIGSOURCE__)) + +/**************** Checks if the ADC injected channel trig source is the specified source. **************************/ +#define __HAL_ADC_CHECK_TRIG_INJECTED(__HANDLE__, __TRIGSOURCE__) \ + ((((__HANDLE__)->Instance->CR1 & ADC_CR1_JEXTSEL_MASK) >> ADC_CR1_JEXTSEL_POS) == (__TRIGSOURCE__)) + +/**************** Bit definition for ADC_SMPR3 register **************************/ +#define ADC_SMPR3_CONV_PLUS_POS (20U) +#define ADC_SMPR3_CONV_PLUS_MASK (BIT21|BIT20) + +/** + * @brief ADC ExTigger structure definition + */ +typedef struct +{ + uint32_t ExTrigSel; /*!< Configures the regular channel trig mode. */ + uint32_t JExTrigSel; /*!< Configures the inject channel trig mode. */ +}ADC_ExTrigTypeDef; + +/** + * @brief ADC group regular oversampling structure definition + */ +typedef struct +{ + uint32_t Ratio; /*!< Configures the oversampling ratio. + This parameter can be a value of @ref ADC_CR2_OVSR_2X*/ + + uint32_t RightBitShift; /*!< Configures the division coefficient for the Oversampler. + This parameter can be a value of @ref ADC_CR2_OVSS_0 */ + + uint32_t TriggeredMode; /*!< Selects the regular triggered oversampling mode. + This parameter can be a value of + 0 : trig 1 time; other: trig N times, N refer to the oversampling Ratio*/ +}ADC_OversamplingTypeDef; + +/******************************** ADC Init mode define *******************************/ +/******************************** ConConvMode define *******************************/ +#define ADC_CONCONVMODE_DISABLE (0) +#define ADC_CONCONVMODE_ENABLE (1) + +/******************************** JChannelMode define *******************************/ +#define ADC_JCHANNELMODE_DISABLE (0) +#define ADC_JCHANNELMODE_ENABLE (1) + +/******************************** DiffMode define *******************************/ +#define ADC_DIFFMODE_DISABLE (0) +#define ADC_DIFFMODE_ENABLE (1) + +/******************************** DMAMode define *******************************/ +#define ADC_DMAMODE_DISABLE (0) +#define ADC_DMAMODE_ENABLE (1) + +/******************************** OverMode define *******************************/ +#define ADC_OVERMODE_DISABLE (0) +#define ADC_OVERMODE_ENABLE (1) + +/******************************** OverSampMode define *******************************/ +#define ADC_OVERSAMPMODE_DISABLE (0) +#define ADC_OVERSAMPMODE_ENABLE (1) + +/******************************** AnalogWDGEn define *******************************/ +#define ADC_ANALOGWDGEN_DISABLE (0) +#define ADC_ANALOGWDGEN_ENABLE (1) + +/** + * @brief ADC Configuration Structure definition + */ +typedef struct +{ + uint32_t ClockDiv; /*!< Specify the ADC clock div from the PCLK. + This parameter can be set to ADC_CLOCK_DIV1 | ADC_CLOCK_DIV2 |... ADC_CLOCK_DIV16 */ + + uint32_t ConConvMode; /*!< Specify whether the conversion is performed in single mode (one conversion) or continuous mode for ADC group regular, + after the first ADC conversion start trigger occurred (software start or external trigger). + This parameter can be set to ADC_CONCONVMODE_DISABLE or ADC_CONCONVMODE_ENABLE. */ + uint32_t JChannelMode; /*!< Specify if support inject channel. This parameter can be set to ADC_JCHANNELMODE_DISABLE or ADC_JCHANNELMODE_ENABLE*/ + uint32_t DiffMode; /*!< Specify the differential parameters. + ADC_DIFFMODE_DISABLE:single end mode, + ADC_DIFFMODE_ENABLE:differential end mode */ + uint32_t ChannelEn; /*!< Specify the enable ADC channels. + This parameter can be set to ADC_CHANNEL_0_EN | ADC_CHANNEL_1_EN |... ADC_CHANNEL_15_EN*/ + + ADC_ExTrigTypeDef ExTrigMode; /*!< ADC ExTigger structure, config the regular and inject channel trig mode */ + + uint32_t DMAMode; /*!< Specify whether the DMA requests are performed in one shot mode (DMA transfer stops when number of conversions is reached) + or in continuous mode (DMA transfer unlimited, whatever number of conversions). + This parameter can be set to ADC_DMAMODE_ENABLE or ADC_DMAMODE_DISABLE. + Note: In continuous mode, DMA must be configured in circular mode. Otherwise an overrun will be triggered when DMA buffer maximum pointer is reached. */ + + uint32_t OverMode; /*!< ADC_OVERMODE_DISABLE,ADC_OVERMODE_ENABLE*/ + + uint32_t OverSampMode; /*!< Specify whether the oversampling feature is enabled or disabled. + This parameter can be set to ADC_OVERSAMPMODE_ENABLE or ADC_OVERSAMPMODE_DISABLE. + Note: This parameter can be modified only if there is no conversion is ongoing on ADC group regular. */ + ADC_OversamplingTypeDef Oversampling; /*!< Specify ADC group regular oversampling structure. */ + + uint32_t AnalogWDGEn; +}ADC_InitTypeDef; + + +typedef struct +{ + uint32_t RjMode; /*!< Specify the channel mode, 0:regular, Other:inject*/ + uint32_t Channel; /*!< Specify the channel to configure into ADC regular group. + This parameter can be a value of @ref ADC_CHANNEL_0 + Note: Depending on devices and ADC instances, some channels may not be available on device package pins. Refer to device datasheet for channels availability. */ + + uint32_t Sq; /*!< Add or remove the channel from ADC regular group sequencer and specify its conversion rank. + This parameter is dependent on ScanConvMode: + - sequencer configured to fully configurable: + Channels ordering into each rank of scan sequence: + whatever channel can be placed into whatever rank. + - sequencer configured to not fully configurable: + rank of each channel is fixed by channel HW number. + (channel 0 fixed on rank 0, channel 1 fixed on rank1, ...). + Despite the channel rank is fixed, this parameter allow an additional possibility: to remove the selected rank (selected channel) from sequencer. + This parameter can be a value of @ref ADC_SEQUENCE_SQ1 */ + + uint32_t Smp; /*!< Sampling time value to be set for the selected channel. + Unit: ADC clock cycles + This parameter can be a value of @ref ADC_SMP_CLOCK_3 */ +}ADC_ChannelConfTypeDef; + +typedef struct +{ + uint32_t WatchdogMode; /*!< Configure the ADC analog watchdog mode: single/all/none channels. + For Analog Watchdog 1: Configure the ADC analog watchdog mode: single channel or all channels, ADC group regular. + For Analog Watchdog 2 and 3: Several channels can be monitored by applying successively the AWD init structure. + This parameter can be a value of @ref ADC_ANALOGWATCHDOG_RCH_ALL. */ + + uint32_t Channel; /*!< Select which ADC channel to monitor by analog watchdog. + For Analog Watchdog 1: this parameter has an effect only if parameter 'WatchdogMode' is configured on single channel (only 1 channel can be monitored). + For Analog Watchdog 2 and 3: Several channels can be monitored. To use this feature, call successively the function HAL_ADC_AnalogWDGConfig() for each channel to be added (or removed with value 'ADC_ANALOGWATCHDOG_NONE'). + This parameter can be a value of @ref ADC_CHANNEL_0. */ + + uint32_t ITMode; /*!< Specify whether the analog watchdog is configured in interrupt or polling mode. + This parameter can be set to ENABLE or DISABLE */ + + uint32_t HighThreshold; /*!< Configure the ADC analog watchdog High threshold value. */ + + uint32_t LowThreshold; /*!< Configures the ADC analog watchdog Low threshold value. */ +}ADC_AnalogWDGConfTypeDef; + +/******************************** ADC Over Sample Shift define *******************************/ +#define ADC_CR2_OVSS_0 (0U) +#define ADC_CR2_OVSS_1 (1U) +#define ADC_CR2_OVSS_2 (2U) +#define ADC_CR2_OVSS_3 (3U) +#define ADC_CR2_OVSS_4 (4U) +#define ADC_CR2_OVSS_5 (5U) +#define ADC_CR2_OVSS_6 (6U) +#define ADC_CR2_OVSS_7 (7U) +#define ADC_CR2_OVSS_8 (8U) + +/******************************** ADC Over Sample Rate define *******************************/ +#define ADC_CR2_OVSR_2X (0U) +#define ADC_CR2_OVSR_4X (1U) +#define ADC_CR2_OVSR_8X (2U) +#define ADC_CR2_OVSR_16X (3U) +#define ADC_CR2_OVSR_32X (4U) +#define ADC_CR2_OVSR_64X (5U) +#define ADC_CR2_OVSR_128X (6U) +#define ADC_CR2_OVSR_256X (7U) + +/******************************** ADC Sample period define *******************************/ +#define ADC_SMP_CLOCK_3 (0U) +#define ADC_SMP_CLOCK_5 (1U) +#define ADC_SMP_CLOCK_7 (2U) +#define ADC_SMP_CLOCK_10 (3U) +#define ADC_SMP_CLOCK_13 (4U) +#define ADC_SMP_CLOCK_16 (5U) +#define ADC_SMP_CLOCK_20 (6U) +#define ADC_SMP_CLOCK_30 (7U) +#define ADC_SMP_CLOCK_60 (8U) +#define ADC_SMP_CLOCK_80 (9U) +#define ADC_SMP_CLOCK_100 (10U) +#define ADC_SMP_CLOCK_120 (11U) +#define ADC_SMP_CLOCK_160 (12U) +#define ADC_SMP_CLOCK_320 (13U) +#define ADC_SMP_CLOCK_480 (14U) +#define ADC_SMP_CLOCK_640 (15U) + + +/******************************** ADC ClockPrescale define *******************************/ +#define ADC_CLOCK_DIV1 (0U) +#define ADC_CLOCK_DIV2 (1U) +#define ADC_CLOCK_DIV3 (2U) +#define ADC_CLOCK_DIV4 (3U) +#define ADC_CLOCK_DIV5 (4U) +#define ADC_CLOCK_DIV6 (5U) +#define ADC_CLOCK_DIV7 (6U) +#define ADC_CLOCK_DIV8 (7U) +#define ADC_CLOCK_DIV9 (8U) +#define ADC_CLOCK_DIV10 (9U) +#define ADC_CLOCK_DIV11 (10U) +#define ADC_CLOCK_DIV12 (11U) +#define ADC_CLOCK_DIV13 (12U) +#define ADC_CLOCK_DIV14 (13U) +#define ADC_CLOCK_DIV15 (14U) +#define ADC_CLOCK_DIV16 (15U) + +/************************ADC_AnalogWDGConfTypeDef->WatchdogMode define********************/ +#define ADC_ANALOGWATCHDOG_RCH_ALL (1U) //All regular channels +#define ADC_ANALOGWATCHDOG_JCH_ALL (2U) //All inject channels +#define ADC_ANALOGWATCHDOG_RCH_AND_JCH_ALL (3U) //All regular and inject channels +#define ADC_ANALOGWATCHDOG_RCH_SINGLE (4U) //Single regular channel +#define ADC_ANALOGWATCHDOG_JCH_SINGLE (5U) //Single Inject channel +#define ADC_ANALOGWATCHDOG_RCH_OR_JCH_SINGLE (6U) //Regular or inject channel + +/******************************** ADC sequence number define *******************************/ +#define ADC_SEQUENCE_SQ1 (1U) +#define ADC_SEQUENCE_SQ2 (2U) +#define ADC_SEQUENCE_SQ3 (3U) +#define ADC_SEQUENCE_SQ4 (4U) +#define ADC_SEQUENCE_SQ5 (5U) +#define ADC_SEQUENCE_SQ6 (6U) +#define ADC_SEQUENCE_SQ7 (7U) +#define ADC_SEQUENCE_SQ8 (8U) +#define ADC_SEQUENCE_SQ9 (9U) +#define ADC_SEQUENCE_SQ10 (10U) +#define ADC_SEQUENCE_SQ11 (11U) +#define ADC_SEQUENCE_SQ12 (12U) +#define ADC_SEQUENCE_SQ13 (13U) +#define ADC_SEQUENCE_SQ14 (14U) +#define ADC_SEQUENCE_SQ15 (15U) +#define ADC_SEQUENCE_SQ16 (16U) + +/******************************** ADC channel number define *******************************/ +#define ADC_CHANNEL_0 (0U) +#define ADC_CHANNEL_1 (1U) +#define ADC_CHANNEL_2 (2U) +#define ADC_CHANNEL_3 (3U) +#define ADC_CHANNEL_4 (4U) +#define ADC_CHANNEL_5 (5U) +#define ADC_CHANNEL_6 (6U) +#define ADC_CHANNEL_7 (7U) +#define ADC_CHANNEL_8 (8U) +#define ADC_CHANNEL_9 (9U) +#define ADC_CHANNEL_10 (10U) +#define ADC_CHANNEL_11 (11U) +#define ADC_CHANNEL_12 (12U) +#define ADC_CHANNEL_13 (13U) +#define ADC_CHANNEL_14 (14U) +#define ADC_CHANNEL_15 (15U) +#define ADC_CHANNEL_TEMP (16U) +#define ADC_CHANNEL_VBAT (17U) +#define ADC_CHANNEL_VBGR (18U) +#define ADC_CHANNEL_EXT2 (19U) +#define ADC_CHANNEL_EXT3 (20U) + +/******************************** ADC channel enable define *******************************/ +#define ADC_CHANNEL_0_EN (BIT0) +#define ADC_CHANNEL_1_EN (BIT1) +#define ADC_CHANNEL_2_EN (BIT2) +#define ADC_CHANNEL_3_EN (BIT3) +#define ADC_CHANNEL_4_EN (BIT4) +#define ADC_CHANNEL_5_EN (BIT5) +#define ADC_CHANNEL_6_EN (BIT6) +#define ADC_CHANNEL_7_EN (BIT7) +#define ADC_CHANNEL_8_EN (BIT8) +#define ADC_CHANNEL_9_EN (BIT9) +#define ADC_CHANNEL_10_EN (BIT10) +#define ADC_CHANNEL_11_EN (BIT11) +#define ADC_CHANNEL_12_EN (BIT12) +#define ADC_CHANNEL_13_EN (BIT13) +#define ADC_CHANNEL_14_EN (BIT14) +#define ADC_CHANNEL_15_EN (BIT15) +#define ADC_CHANNEL_TEMP_EN (BIT16) +#define ADC_CHANNEL_VBAT_EN (BIT17) +#define ADC_CHANNEL_VBGR_EN (BIT18) +#define ADC_CHANNEL_EXT2_EN (BIT19) +#define ADC_CHANNEL_EXT3_EN (BIT20) + +/******************************** ADC Trig source define******************************* + * | Trig Source | ACM32FXXX/FPXXX | ACM32F0X0 | * + * | ADC_SOFTWARE_START | SWSTART/JSWSTART | SWSTART/JSWSTART | * + * | ADC_EXTERNAL_TIG1 | TIM1_TRGO | TIM1_TRGO | * + * | ADC_EXTERNAL_TIG2 | TIM1_CC4 | TIM1_CC4 | * + * | ADC_EXTERNAL_TIG3 | TIM2_TRGO | RSV | * + * | ADC_EXTERNAL_TIG4 | TIM3_TRGO | TIM3_TRGO | * + * | ADC_EXTERNAL_TIG5 | TIM4_TRGO | TIM15_TRGO | * + * | ADC_EXTERNAL_TIG6 | TIM6_TRGO | TIM6_TRGO | * + * | ADC_EXTERNAL_TIG7 | EXTi Line 11 | EXTi Line 11 | */ +#define ADC_SOFTWARE_START (0U) +#define ADC_EXTERNAL_TIG1 (1U) +#define ADC_EXTERNAL_TIG2 (2U) +#define ADC_EXTERNAL_TIG3 (3U) +#define ADC_EXTERNAL_TIG4 (4U) +#define ADC_EXTERNAL_TIG5 (5U) +#define ADC_EXTERNAL_TIG6 (6U) +#define ADC_EXTERNAL_TIG7 (7U) + + +/******************************** ADC results flag define for HAL level*******************************/ +#define HAL_ADC_EOC_FLAG 0x80000000 +#define HAL_ADC_JEOC_FLAG 0x40000000 +#define HAL_ADC_AWD_FLAG 0x20000000 + +/** + * @brief ADC handle Structure definition + */ +typedef struct __ADC_HandleTypeDef +{ + ADC_TypeDef *Instance; /*!< Register base address */ + ADC_InitTypeDef Init; /*!< ADC initialization parameters and regular conversions setting */ + DMA_HandleTypeDef *DMA_Handle; /*!< Pointer DMA Handler */ + uint32_t ChannelNum; /*!< Total enable regular group channel number*/ + uint32_t *AdcResults; /*!< Point to the convert results*/ + void (*ConvCpltCallback)(struct __ADC_HandleTypeDef *hadc); /*!< ADC conversion complete callback */ + void (*GroupCpltCallback)(struct __ADC_HandleTypeDef *hadc); /*!< ADC regular group conversion complete callback */ + void (*InjectedConvCpltCallback)(struct __ADC_HandleTypeDef *hadc); /*!< ADC injected conversion complete callback */ + void (*LevelOutOfWindowCallback)(struct __ADC_HandleTypeDef *hadc); /*!< ADC analog watchdog callback */ +}ADC_HandleTypeDef; + +/******************************** ADC Instances *******************************/ +#define IS_ADC_ALL_INSTANCE(INSTANCE) ((INSTANCE) == ADC) +#define IS_ADC_ALL_CONCONVMODE(CONCONVMODE) (((CONCONVMODE) == ADC_CONCONVMODE_DISABLE) || \ + ((CONCONVMODE) == ADC_CONCONVMODE_ENABLE)) + +#define IS_ADC_ALL_JCHANNELMODE(JCHANNELMODE) (((JCHANNELMODE) == ADC_JCHANNELMODE_DISABLE) || \ + ((JCHANNELMODE) == ADC_JCHANNELMODE_ENABLE)) + +#define IS_ADC_ALL_DIFFMODE(DIFFMODE) (((DIFFMODE) == ADC_DIFFMODE_DISABLE) || \ + ((DIFFMODE) == ADC_DIFFMODE_ENABLE)) + +#define IS_ADC_ALL_DMAMODE(DMAMODE) (((DMAMODE) == ADC_DMAMODE_DISABLE) || \ + ((DMAMODE) == ADC_DMAMODE_ENABLE)) + +#define IS_ADC_ALL_OVERMODE(OVERMODE) (((OVERMODE) == ADC_OVERMODE_DISABLE) || \ + ((OVERMODE) == ADC_OVERMODE_ENABLE)) + +#define IS_ADC_ALL_OVERSAMPMODE(OVERSAMPMODE) (((OVERSAMPMODE) == ADC_OVERSAMPMODE_DISABLE) || \ + ((OVERSAMPMODE) == ADC_OVERSAMPMODE_ENABLE)) + +#define IS_ADC_ALL_OVSS(_OVSS) (((_OVSS) == ADC_CR2_OVSS_0) || \ + ((_OVSS) == ADC_CR2_OVSS_1) || \ + ((_OVSS) == ADC_CR2_OVSS_2) || \ + ((_OVSS) == ADC_CR2_OVSS_3) || \ + ((_OVSS) == ADC_CR2_OVSS_4) || \ + ((_OVSS) == ADC_CR2_OVSS_5) || \ + ((_OVSS) == ADC_CR2_OVSS_6) || \ + ((_OVSS) == ADC_CR2_OVSS_7) || \ + ((_OVSS) == ADC_CR2_OVSS_8)) + +#define IS_ADC_ALL_OVSR(_OVSR) (((_OVSR) == ADC_CR2_OVSR_2X) || \ + ((_OVSR) == ADC_CR2_OVSR_4X) || \ + ((_OVSR) == ADC_CR2_OVSR_8X) || \ + ((_OVSR) == ADC_CR2_OVSR_16X) || \ + ((_OVSR) == ADC_CR2_OVSR_32X) || \ + ((_OVSR) == ADC_CR2_OVSR_64X) || \ + ((_OVSR) == ADC_CR2_OVSR_128X) || \ + ((_OVSR) == ADC_CR2_OVSR_256X)) + +#define IS_ADC_ALL_ANALOGWDGEN(ANALOGWDGEN) (((ANALOGWDGEN) == ADC_ANALOGWDGEN_DISABLE) || \ + ((ANALOGWDGEN) == ADC_ANALOGWDGEN_ENABLE)) + +#define IS_ADC_ALL_CLOCKDIV(CLOCKDIV) (((CLOCKDIV) == ADC_CLOCK_DIV1) || \ + ((CLOCKDIV) == ADC_CLOCK_DIV2) || \ + ((CLOCKDIV) == ADC_CLOCK_DIV3) || \ + ((CLOCKDIV) == ADC_CLOCK_DIV4) || \ + ((CLOCKDIV) == ADC_CLOCK_DIV5) || \ + ((CLOCKDIV) == ADC_CLOCK_DIV6) || \ + ((CLOCKDIV) == ADC_CLOCK_DIV7) || \ + ((CLOCKDIV) == ADC_CLOCK_DIV8) || \ + ((CLOCKDIV) == ADC_CLOCK_DIV9) || \ + ((CLOCKDIV) == ADC_CLOCK_DIV10) || \ + ((CLOCKDIV) == ADC_CLOCK_DIV11) || \ + ((CLOCKDIV) == ADC_CLOCK_DIV12) || \ + ((CLOCKDIV) == ADC_CLOCK_DIV13) || \ + ((CLOCKDIV) == ADC_CLOCK_DIV14) || \ + ((CLOCKDIV) == ADC_CLOCK_DIV15) || \ + ((CLOCKDIV) == ADC_CLOCK_DIV16)) + +#define IS_ADC_ALL_SEQUENCE(SEQUENCE) (((SEQUENCE) == ADC_SEQUENCE_SQ1) || \ + ((SEQUENCE) == ADC_SEQUENCE_SQ2) || \ + ((SEQUENCE) == ADC_SEQUENCE_SQ3) || \ + ((SEQUENCE) == ADC_SEQUENCE_SQ4) || \ + ((SEQUENCE) == ADC_SEQUENCE_SQ5) || \ + ((SEQUENCE) == ADC_SEQUENCE_SQ6) || \ + ((SEQUENCE) == ADC_SEQUENCE_SQ7) || \ + ((SEQUENCE) == ADC_SEQUENCE_SQ8) || \ + ((SEQUENCE) == ADC_SEQUENCE_SQ9) || \ + ((SEQUENCE) == ADC_SEQUENCE_SQ10) || \ + ((SEQUENCE) == ADC_SEQUENCE_SQ11) || \ + ((SEQUENCE) == ADC_SEQUENCE_SQ12) || \ + ((SEQUENCE) == ADC_SEQUENCE_SQ13) || \ + ((SEQUENCE) == ADC_SEQUENCE_SQ14) || \ + ((SEQUENCE) == ADC_SEQUENCE_SQ15) || \ + ((SEQUENCE) == ADC_SEQUENCE_SQ16)) + +#define IS_ADC_ALL_CHANNEL(CHANNEL) (((CHANNEL) == ADC_CHANNEL_0) || \ + ((CHANNEL) == ADC_CHANNEL_1) || \ + ((CHANNEL) == ADC_CHANNEL_2) || \ + ((CHANNEL) == ADC_CHANNEL_3) || \ + ((CHANNEL) == ADC_CHANNEL_4) || \ + ((CHANNEL) == ADC_CHANNEL_5) || \ + ((CHANNEL) == ADC_CHANNEL_6) || \ + ((CHANNEL) == ADC_CHANNEL_7) || \ + ((CHANNEL) == ADC_CHANNEL_8) || \ + ((CHANNEL) == ADC_CHANNEL_9) || \ + ((CHANNEL) == ADC_CHANNEL_10) || \ + ((CHANNEL) == ADC_CHANNEL_11) || \ + ((CHANNEL) == ADC_CHANNEL_12) || \ + ((CHANNEL) == ADC_CHANNEL_13) || \ + ((CHANNEL) == ADC_CHANNEL_14) || \ + ((CHANNEL) == ADC_CHANNEL_15) || \ + ((CHANNEL) == ADC_CHANNEL_TEMP) || \ + ((CHANNEL) == ADC_CHANNEL_VBAT) || \ + ((CHANNEL) == ADC_CHANNEL_VBGR) || \ + ((CHANNEL) == ADC_CHANNEL_EXT2) || \ + ((CHANNEL) == ADC_CHANNEL_EXT3)) + +#define IS_ADC_ALL_CHANNELEN(CHANNELEN) ((CHANNELEN) <= 0x1FFFFF) + +#define IS_ADC_ALL_SMPCLOCK(SMPCLOCK) (((SMPCLOCK) == ADC_SMP_CLOCK_3) || \ + ((SMPCLOCK) == ADC_SMP_CLOCK_5) || \ + ((SMPCLOCK) == ADC_SMP_CLOCK_7) || \ + ((SMPCLOCK) == ADC_SMP_CLOCK_10) || \ + ((SMPCLOCK) == ADC_SMP_CLOCK_13) || \ + ((SMPCLOCK) == ADC_SMP_CLOCK_16) || \ + ((SMPCLOCK) == ADC_SMP_CLOCK_20) || \ + ((SMPCLOCK) == ADC_SMP_CLOCK_30) || \ + ((SMPCLOCK) == ADC_SMP_CLOCK_60) || \ + ((SMPCLOCK) == ADC_SMP_CLOCK_80) || \ + ((SMPCLOCK) == ADC_SMP_CLOCK_100) || \ + ((SMPCLOCK) == ADC_SMP_CLOCK_120) || \ + ((SMPCLOCK) == ADC_SMP_CLOCK_160) || \ + ((SMPCLOCK) == ADC_SMP_CLOCK_320) || \ + ((SMPCLOCK) == ADC_SMP_CLOCK_480) || \ + ((SMPCLOCK) == ADC_SMP_CLOCK_640)) + +#define IS_ADC_ALL_TRIG(_TRIG) (((_TRIG) == ADC_SOFTWARE_START) || \ + ((_TRIG) == ADC_EXTERNAL_TIG1) || \ + ((_TRIG) == ADC_EXTERNAL_TIG2) || \ + ((_TRIG) == ADC_EXTERNAL_TIG3) || \ + ((_TRIG) == ADC_EXTERNAL_TIG4) || \ + ((_TRIG) == ADC_EXTERNAL_TIG5) || \ + ((_TRIG) == ADC_EXTERNAL_TIG6) || \ + ((_TRIG) == ADC_EXTERNAL_TIG7)) + +#define IS_ADC_EVENT_TYPE(_EVENT) (((_EVENT) == ADC_SR_AWD) || \ + ((_EVENT) == ADC_SR_OVERF) || \ + ((_EVENT) == ADC_SR_EOG) || \ + ((_EVENT) == ADC_SR_JEOC) || \ + ((_EVENT) == ADC_SR_EOC)) + +/* Function : HAL_ADC_IRQHandler */ +void HAL_ADC_IRQHandler(ADC_HandleTypeDef *hadc); +void HAL_ADC_MspInit(ADC_HandleTypeDef* hadc); +void HAL_ADC_MspDeInit(ADC_HandleTypeDef* hadc); +HAL_StatusTypeDef HAL_ADC_Init(ADC_HandleTypeDef* hadc); +HAL_StatusTypeDef HAL_ADC_DeInit(ADC_HandleTypeDef* hadc); +HAL_StatusTypeDef HAL_ADC_ConfigChannel(ADC_HandleTypeDef* hadc, ADC_ChannelConfTypeDef* sConfig); +HAL_StatusTypeDef HAL_ADC_AnalogWDGConfig(ADC_HandleTypeDef* hadc, ADC_AnalogWDGConfTypeDef* AnalogWDGConfig); +HAL_StatusTypeDef HAL_ADC_Start(ADC_HandleTypeDef* hadc); +HAL_StatusTypeDef HAL_ADC_Stop(ADC_HandleTypeDef* hadc); +HAL_StatusTypeDef HAL_ADC_Start_IT(ADC_HandleTypeDef* hadc); +HAL_StatusTypeDef HAL_ADC_Stop_IT(ADC_HandleTypeDef* hadc); +HAL_StatusTypeDef HAL_ADC_Start_DMA(ADC_HandleTypeDef* hadc, uint32_t* pData, uint32_t Length); +HAL_StatusTypeDef HAL_ADC_Stop_DMA(ADC_HandleTypeDef* hadc); +uint32_t HAL_ADC_GetValue(ADC_HandleTypeDef *hadc); +HAL_StatusTypeDef HAL_ADC_PollForEvent(ADC_HandleTypeDef *hadc, uint32_t EventType, uint32_t Timeout); +HAL_StatusTypeDef HAL_ADC_InjectedStart_IT(ADC_HandleTypeDef* hadc); +HAL_StatusTypeDef HAL_ADC_InjectedStop_IT(ADC_HandleTypeDef* hadc); +uint32_t HAL_ADC_InjectedGetValue(ADC_HandleTypeDef *hadc); +HAL_StatusTypeDef HAL_ADC_Polling(ADC_HandleTypeDef* hadc, uint32_t* pData, uint32_t Length, uint32_t Timeout); + +#endif + + + + + diff --git a/bsp/acm32f4xx-nucleo/libraries/HAL_Driver/Inc/HAL_AES.h b/bsp/acm32f4xx-nucleo/libraries/HAL_Driver/Inc/HAL_AES.h new file mode 100644 index 0000000000..97a7ce4135 --- /dev/null +++ b/bsp/acm32f4xx-nucleo/libraries/HAL_Driver/Inc/HAL_AES.h @@ -0,0 +1,94 @@ +/*********************************************************************** + * All rights reserved. + * Filename : aes.h + * Description : aes driver header file + * Author(s) : Eric + * version : V1.0 + * Modify date : 2016-03-24 + ***********************************************************************/ +#ifndef __AES_H__ +#define __AES_H__ + +#include "ACM32Fxx_HAL.h" + +#define AES_ENCRYPTION 1 +#define AES_DECRYPTION 0 +#define AES_ECB_MODE 0 +#define AES_CBC_MODE 1 +#define AES_SWAP_ENABLE 1 +#define AES_SWAP_DISABLE 0 + +#define AES_NORMAL_MODE 0x12345678 +#define AES_SECURITY_MODE 0 + +#define AES_KEY_128 0 +#define AES_KEY_192 1 +#define AES_KEY_256 2 + +#define AES_FAIL 0x00 +#define AES_PASS 0xa59ada68 + +#define BIT_AES (1<<28) + +/************************************************************************ + * function : delay + * Description: delay for a while. + * input : + * count: count to decrease + * return: none + ************************************************************************/ + extern void delay(uint32_t count); + + +/****************************************************************************** + * Name: HAL_AES_SetKey + * Function: set key of AES + * Input: + keyin -- pointer to buffer of key + key_len -- select length of key(AES_KEY_128/ AES_KEY_192/ AES_KEY_256) + swap_en -- AES_SWAP_ENABLE, AES_SWAP_DISABLE + * Return: None +*******************************************************************************/ +void HAL_AES_SetKey(UINT32 *keyin, UINT8 key_len, UINT8 swap_en); +void HAL_AES_SetKey_U8(UINT8 *keyin, UINT8 key_len, UINT8 swap_en); + + +/****************************************************************************** +Name: HAL_AES_Crypt +Function: Function for AES encryption and decryption +Input: + indata -- pointer to buffer of input + outdata -- pointer to buffer of result + block_len -- block(128bit) length for aes cryption + operation -- AES_ENCRYPTION,AES_DECRYPTION + mode -- AES_ECB_MODE, AES_CBC_MODE, + iv -- initial vector for CBC mode + security_mode -- AES_NORMAL_MODE, AES_SECURITY_MDOE +Return: None + +*******************************************************************************/ +uint32_t HAL_AES_Crypt( + uint32_t *indata, + uint32_t *outdata, + uint32_t block_len, + uint8_t operation, + uint8_t mode, + uint32_t *iv, + uint32_t security_mode +); + + +uint32_t HAL_AES_Crypt_U8( + uint8_t *indata, + uint8_t *outdata, + uint32_t block_len, + uint8_t operation, + uint8_t mode, + uint8_t *iv, + uint32_t security_mode +); + +#endif +/****************************************************************************** + * end of file +*******************************************************************************/ diff --git a/bsp/acm32f4xx-nucleo/libraries/HAL_Driver/Inc/HAL_CAN.h b/bsp/acm32f4xx-nucleo/libraries/HAL_Driver/Inc/HAL_CAN.h new file mode 100644 index 0000000000..2cfc44c5c3 --- /dev/null +++ b/bsp/acm32f4xx-nucleo/libraries/HAL_Driver/Inc/HAL_CAN.h @@ -0,0 +1,394 @@ +/* + ****************************************************************************** + * @file HAL_Can.h + * @version V1.0.0 + * @date 2020 + * @brief Header file of CAN HAL module. + ****************************************************************************** +*/ +#ifndef __HAL_CAN_H__ +#define __HAL_CAN_H__ + +#include "ACM32Fxx_HAL.h" + +/** + * @} + */ + +/******************************************************************************/ +/* Peripheral Registers Bits Definition */ +/******************************************************************************/ +/******************************************************************************/ +/* (CAN) */ +/******************************************************************************/ + +/**************** Bit definition for CAN MOD register ***********************/ +#define CAN_MOD_RM BIT0 +#define CAN_MOD_LOM BIT1 +#define CAN_MOD_STM BIT2 +#define CAN_MOD_AFM BIT3 +#define CAN_MOD_SM BIT4 +/**************** Bit definition for CAN CMR register ***********************/ +#define CAN_CMR_TR BIT0 +#define CAN_CMR_AT BIT1 +#define CAN_CMR_RRB BIT2 +#define CAN_CMR_CDO BIT3 +#define CAN_CMR_SRR BIT4 +/**************** Bit definition for CAN SR register ***********************/ +#define CAN_SR_RBS BIT0 +#define CAN_SR_DOS BIT1 +#define CAN_SR_TBS BIT2 +#define CAN_SR_TCS BIT3 +#define CAN_SR_RS BIT4 +#define CAN_SR_TS BIT5 +#define CAN_SR_ES BIT6 +#define CAN_SR_BS BIT7 +/**************** Bit definition for CAN IR register ***********************/ +#define CAN_IR_RI BIT0 +#define CAN_IR_TI BIT1 +#define CAN_IR_EI BIT2 +#define CAN_IR_DOI BIT3 +#define CAN_IR_WUI BIT4 +#define CAN_IR_EPI BIT5 +#define CAN_IR_ALI BIT6 +#define CAN_IR_BEI BIT7 +/**************** Bit definition for CAN IER register ***********************/ +#define CAN_IER_RIE BIT0 +#define CAN_IER_TIE BIT1 +#define CAN_IER_EIE BIT2 +#define CAN_IER_DOIE BIT3 +#define CAN_IER_WUIE BIT4 +#define CAN_IER_EPIE BIT5 +#define CAN_IER_ALIE BIT6 +#define CAN_IER_BEIE BIT7 + +/** + * @brief CAN init structure definition + */ +typedef struct +{ + uint32_t CAN_Mode; /*!< Specifies the CAN operating mode. + This parameter can be a value of + @ref CAN_mode e.g:CAN_Mode_Normal CAN_Mode_Normal*/ + + uint32_t CAN_SJW; /*!< Specifies the maximum number of time quanta + the CAN hardware is allowed to lengthen or + shorten a bit to perform resynchronization. + This parameter can be a value of + @ref CAN_SJW e.g:CAN_SJW_1tq--CAN_SJW_4tq*/ + + uint32_t CAN_BRP ; /*!< Specifies the number of time quanta in Bit + Segment 1. This parameter can be a value between 0 and 63 */ + + uint32_t CAN_TSEG1; /*!< Specifies the number of time quanta in Bit + Segment 1. This parameter can be a value of + @ref CAN_TSEG1 e.g: CAN_TSEG1_1tq-CAN_TSEG1_16tq*/ + + uint32_t CAN_TSEG2; /*!< Specifies the number of time quanta in Bit + Segment 2.This parameter can be a value of + @ref CAN_TSEG2 e.g:CAN_TSEG1_1tq-CAN_TSEG16_tq*/ + + uint32_t CAN_SAM ; /*!< Specifies the CAN operating mode. + This parameter can be a value of + @ref CAN_SAM e.g:CAN_SAM_1time CAN_SAM_3time*/ +} CAN_InitTypeDef; + + +/** + * @brief CAN filter init structure definition + */ + +typedef struct +{ + uint32_t CAN_FilterMode; /*!< Specifies the filter mode to be initialized. + This parameter can be a value of + @ref CAN_filter_mode e.g:CAN_FilterMode_Dual CAN_FilterMode_Single*/ + + uint32_t CAN_FilterId1; /*!< Specifies the filter identification number + This parameter can be a value between 0x0000 and 0x1FFFFFFF */ + + uint32_t CAN_FilterId2; /*!< Specifies the filter identification number + only CAN_FilterMode=CAN_FilterMode_Dual Enable + This parameter can be a value between 0x0000 and 0x1FFFFFFF */ + + uint32_t CAN_FilterMaskId1; /*!< Specifies the filter identification mask number + This parameter can be a value between 0x0000 and 0x1FFFFFFF */ + + uint32_t CAN_FilterMaskId2; /*!< Specifies the filter identification mask number + only CAN_FilterMode=CAN_FilterMode_Dual Enable + This parameter can be a value between 0x0000 and 0x1FFFFFFF */ +} CAN_FilterInitTypeDef; + + + +/** + * @brief CAN RxTxMessege structure definition + */ +typedef struct +{ + uint32_t StdId; /*!< Specifies the standard identifier. + This parameter can be a value between 0 to 0x7FF. */ + + uint32_t ExtId; /*!< Specifies the extended identifier. + This parameter can be a value between 0 to 0x1FFFFFFF. */ + + uint32_t IDE; /*!< Specifies the type of identifier for the message that + will be transmitted. This parameter can be a value + of @ref CAN_identifier_type e.g: CAN_Id_Standard CAN_Id_Extended*/ + + uint32_t RTR; /*!< Specifies the type of frame for the message that will + be transmitted. This parameter can be a value of + @ref CAN_remote_transmission e.g: CAN_RTR_Data CAN_RTR_Remote */ + + uint32_t DLC; /*!< Specifies the length of the frame that will be + transmitted. This parameter can be a value between 0 to 8 */ + + uint8_t Data[8]; /*!< Contains the data to be transmitted. It ranges from 0 to 0xFF. */ +} CanTxRxMsg; + + +/** + * @brief CAN handle Structure definition + */ +typedef struct __CAN_HandleTypeDef +{ + CAN_TypeDef *Instance; /*!< Register base address */ + + CAN_InitTypeDef Init; /*!< CAN required parameters */ + + CanTxRxMsg *RxMessage; /*!< CAN RxMessage */ + + void (*CAN_ReceiveIT_Callback)(struct __CAN_HandleTypeDef *hcan); /* CAN ReceiveIT complete callback */ + + void (*CAN_TransmitIT_Callback)(struct __CAN_HandleTypeDef *hcan); /* CAN TransmitIT complete callback */ + +} CAN_HandleTypeDef; + +typedef enum {DISABLE = 0, ENABLE = !DISABLE} FunctionalState; + +#define IS_FUNCTIONAL_STATE(STATE) (((STATE) == DISABLE) || ((STATE) == ENABLE)) + +#define IS_CAN_ALL_PERIPH(PERIPH) (((PERIPH) == CAN1) || \ + ((PERIPH) == CAN2)) + +/** @defgroup CAN_identifier_type + * @{ + */ + +#define CAN_Id_Standard ((uint32_t)0x00000000) /*!< Standard Id */ +#define CAN_Id_Extended ((uint32_t)0x00000001) /*!< Extended Id */ +#define IS_CAN_IDTYPE(IDTYPE) (((IDTYPE) == CAN_Id_Standard) || \ + ((IDTYPE) == CAN_Id_Extended)) +/** + * @} + */ +/** @defgroup CAN_remote_transmission + * @{ + */ + +#define CAN_RTR_Data ((uint32_t)0x00000000) /*!< Data frame */ +#define CAN_RTR_Remote ((uint32_t)0x00000001) /*!< Remote frame */ +#define IS_CAN_RTR(RTR) (((RTR) == CAN_RTR_Data) || ((RTR) == CAN_RTR_Remote)) + +/** + * @} + */ +/** @defgroup CAN_TxRxMessege + * @{ + */ + +#define IS_CAN_STDID(STDID) ((STDID) <= ((uint32_t)0x7FF)) +#define IS_CAN_EXTID(EXTID) ((EXTID) <= ((uint32_t)0x1FFFFFFF)) +#define IS_CAN_DLC(DLC) ((DLC) <= ((uint8_t)0x08)) + + +#define IS_CAN_GET_FLAG(FLAG) (((FLAG) == CAN_SR_RBS) || ((FLAG) == CAN_SR_DOS) || \ + ((FLAG) == CAN_SR_TBS) || ((FLAG) == CAN_SR_TCS) || \ + ((FLAG) == CAN_SR_RS) || ((FLAG) == CAN_SR_TS) || \ + ((FLAG) == CAN_SR_ES) || ((FLAG) == CAN_SR_BS)) + +#define IS_CAN_BRP(BRP) (((BRP) >= 0) && ((BRP) <= 63)) + +/** + * @defgroup CAN_Mode + * @{ + */ +#define CAN_Mode_Normal ((uint8_t)0x00) /*!< Normal mode */ +#define CAN_Mode_SlefTest ((uint8_t)0x01) /*!< SlefTest mode */ + +#define IS_CAN_MODE(MODE) (((MODE) == CAN_Mode_Normal) ||\ + ((MODE) == CAN_Mode_SlefTest)) +/** + * @} + */ + +/** + * @defgroup CAN_Operating_Mode + * @{ + */ +#define CAN_OperatingMode_Normal ((uint8_t)0x00) /*!< Initialization mode */ +#define CAN_OperatingMode_Initialization ((uint8_t)0x01) /*!< Normal mode */ +#define CAN_OperatingMode_Listen ((uint8_t)0x02) /*!< Listen mode */ +#define CAN_OperatingMode_SelfTest ((uint8_t)0x04) /*!< Listen mode */ +#define CAN_OperatingMode_Sleep ((uint8_t)0x10) /*!< sleep mode */ + + +#define IS_CAN_OPERATING_MODE(MODE) (((MODE) == CAN_OperatingMode_Initialization) ||\ + ((MODE) == CAN_OperatingMode_Normal)|| \ + ((MODE) == CAN_OperatingMode_Sleep)|| \ + ((MODE) == CAN_OperatingMode_SelfTest)|| \ + ((MODE) == CAN_OperatingMode_Listen)) +/** + * @} + */ + +/** @defgroup CAN_SAM + * @{ + */ + +#define CAN_SAM_1time ((uint8_t)0x00) /*!< 1 time quantum */ +#define CAN_SAM_3time ((uint8_t)0x01) /*!< 2 time quantum */ + +#define IS_CAN_SAM(SAM) (((SAM) == CAN_SAM_1time) || ((SAM) == CAN_SAM_3time)) +/** + * @} + */ + + +/** @defgroup CAN_synchronisation_jump_width + * @{ + */ + +#define CAN_SJW_1tq ((uint8_t)0x00) /*!< 1 time quantum */ +#define CAN_SJW_2tq ((uint8_t)0x01) /*!< 2 time quantum */ +#define CAN_SJW_3tq ((uint8_t)0x02) /*!< 3 time quantum */ +#define CAN_SJW_4tq ((uint8_t)0x03) /*!< 4 time quantum */ + +#define IS_CAN_SJW(SJW) (((SJW) == CAN_SJW_1tq) || ((SJW) == CAN_SJW_2tq)|| \ + ((SJW) == CAN_SJW_3tq) || ((SJW) == CAN_SJW_4tq)) +/** + * @} + */ + + /** @defgroup CAN_time_quantum_in_bit_segment_1 + * @{ + */ + +#define CAN_TSEG1_1tq ((uint8_t)0x00) /*!< 1 time quantum */ +#define CAN_TSEG1_2tq ((uint8_t)0x01) /*!< 2 time quantum */ +#define CAN_TSEG1_3tq ((uint8_t)0x02) /*!< 3 time quantum */ +#define CAN_TSEG1_4tq ((uint8_t)0x03) /*!< 4 time quantum */ +#define CAN_TSEG1_5tq ((uint8_t)0x04) /*!< 5 time quantum */ +#define CAN_TSEG1_6tq ((uint8_t)0x05) /*!< 6 time quantum */ +#define CAN_TSEG1_7tq ((uint8_t)0x06) /*!< 7 time quantum */ +#define CAN_TSEG1_8tq ((uint8_t)0x07) /*!< 8 time quantum */ +#define CAN_TSEG1_9tq ((uint8_t)0x08) /*!< 9 time quantum */ +#define CAN_TSEG1_10tq ((uint8_t)0x09) /*!< 10 time quantum */ +#define CAN_TSEG1_11tq ((uint8_t)0x0A) /*!< 11 time quantum */ +#define CAN_TSEG1_12tq ((uint8_t)0x0B) /*!< 12 time quantum */ +#define CAN_TSEG1_13tq ((uint8_t)0x0C) /*!< 13 time quantum */ +#define CAN_TSEG1_14tq ((uint8_t)0x0D) /*!< 14 time quantum */ +#define CAN_TSEG1_15tq ((uint8_t)0x0E) /*!< 15 time quantum */ +#define CAN_TSEG1_16tq ((uint8_t)0x0F) /*!< 16 time quantum */ + +#define IS_CAN_TSEG1(TSEG1) ((TSEG1) <= CAN_TSEG1_16tq) +/** + * @} + */ + +/** @defgroup CAN_time_quantum_in_bit_segment_2 + * @{ + */ + +#define CAN_TSEG2_1tq ((uint8_t)0x00) /*!< 1 time quantum */ +#define CAN_TSEG2_2tq ((uint8_t)0x01) /*!< 2 time quantum */ +#define CAN_TSEG2_3tq ((uint8_t)0x02) /*!< 3 time quantum */ +#define CAN_TSEG2_4tq ((uint8_t)0x03) /*!< 4 time quantum */ +#define CAN_TSEG2_5tq ((uint8_t)0x04) /*!< 5 time quantum */ +#define CAN_TSEG2_6tq ((uint8_t)0x05) /*!< 6 time quantum */ +#define CAN_TSEG2_7tq ((uint8_t)0x06) /*!< 7 time quantum */ +#define CAN_TSEG2_8tq ((uint8_t)0x07) /*!< 8 time quantum */ +#define IS_CAN_TSEG2(TSEG) ((TSEG) <= CAN_TSEG2_8tq) +/** + * @} + */ + + +/** @defgroup CAN_filter_mode + * @{ + */ +#define CAN_FilterMode_Dual ((uint8_t)0x00) /*!< identifier list mode */ +#define CAN_FilterMode_Single ((uint8_t)0x01) /*!< identifier/mask mode */ +#define IS_CAN_FILTER_MODE(MODE) (((MODE) == CAN_FilterMode_Dual) || \ + ((MODE) == CAN_FilterMode_Single)) + + /** + * @} + */ + +/** @defgroup CAN_ErrorCode + * @{ + */ +#define CAN_ErrorType_ErrCode ((uint8_t)0xC0) /*!< identifier list mode */ +#define CAN_ErrorType_Direction ((uint8_t)0x20) /*!< identifier/mask mode */ +#define CAN_ErrorType_SegCode ((uint8_t)0x1F) /*!< identifier/mask mode */ +#define IS_CAN_ErrorType(ErrorType) (((ErrorType) == CAN_ErrorType_ErrCode) || \ + ((ErrorType) == CAN_ErrorType_Direction)|| \ + ((ErrorType) == CAN_ErrorType_SegCode)) +/** + * @} + */ +/* Initialization and Configuration functions *********************************/ +void HAL_CAN_MspInit(CAN_HandleTypeDef *hcan); + +void HAL_CAN_MspDeInit(CAN_HandleTypeDef *hcan); + +HAL_StatusTypeDef HAL_CAN_Init(CAN_HandleTypeDef *hcan); + +HAL_StatusTypeDef HAL_CAN_DeInit(CAN_HandleTypeDef *hcan); + +void HAL_CAN_ConfigFilter(CAN_HandleTypeDef *hcan,CAN_FilterInitTypeDef* CAN_FilterInitStruct); + +/* Transmit functions *********************************************************/ +HAL_StatusTypeDef HAL_CAN_Transmit(CAN_HandleTypeDef *hcan, CanTxRxMsg* TxMessage); + +void HAL_CAN_CancelTransmit(CAN_HandleTypeDef *hcan); + +/* Receive functions **********************************************************/ +HAL_StatusTypeDef HAL_CAN_Receive(CAN_HandleTypeDef *hcan, CanTxRxMsg* RxMessage); + +HAL_StatusTypeDef HAL_CAN_Receive_IT(CAN_HandleTypeDef *hcan, CanTxRxMsg* RxMessage); + +int8_t HAL_CAN_GetReceiveFiFoCounter(CAN_HandleTypeDef *hcan); + +int8_t HAL_CAN_GetReceiveFiFoAddr(CAN_HandleTypeDef *hcan); + +void HAL_CAN_ReleaseReceiveFIFO(CAN_HandleTypeDef *hcan); + +void HAL_CAN_GetRxMessage(CAN_HandleTypeDef *hcan, CanTxRxMsg* RxMessage); + +/* Operation modes functions **************************************************/ +HAL_StatusTypeDef HAL_CAN_OperatingModeRequest(CAN_HandleTypeDef *hcan, uint8_t CAN_OperatingMode); + +void HAL_CAN_ClearOverload(CAN_HandleTypeDef *hcan); + +void HAL_CAN_SelfReceive(CAN_HandleTypeDef *hcan); + +HAL_StatusTypeDef HAL_CAN_Sleep(CAN_HandleTypeDef *hcan); + +HAL_StatusTypeDef HAL_CAN_WakeUp(CAN_HandleTypeDef *hcan); + +/* Error Code management functions **********************************/ +int8_t HAL_CAN_GetErrorCode(CAN_HandleTypeDef *hcan,uint32_t Error_Type); + +int8_t HAL_CAN_GetErrorAlarmCounter(CAN_HandleTypeDef *hcan); + +int8_t HAL_CAN_GetArbitrationErrorPosition(CAN_HandleTypeDef *hcan); + +int8_t HAL_CAN_GetReceiveErrorCounter(CAN_HandleTypeDef *hcan); + +int8_t HAL_CAN_GetTransmitErrorCounter(CAN_HandleTypeDef *hcan); + +void HAL_CAN_IRQHandler(CAN_HandleTypeDef *hcan); + +#endif diff --git a/bsp/acm32f4xx-nucleo/libraries/HAL_Driver/Inc/HAL_COMP.h b/bsp/acm32f4xx-nucleo/libraries/HAL_Driver/Inc/HAL_COMP.h new file mode 100644 index 0000000000..e83cc0b8d6 --- /dev/null +++ b/bsp/acm32f4xx-nucleo/libraries/HAL_Driver/Inc/HAL_COMP.h @@ -0,0 +1,216 @@ +/* + ****************************************************************************** + * @file HAL_COMP.h + * @version V1.0.0 + * @date 2020 + * @brief Header file of COMP HAL module. + ****************************************************************************** +*/ +#ifndef __HAL_COMP_H__ +#define __HAL_COMP_H__ + +#include "ACM32Fxx_HAL.h" + +#define COMP1 (0x01) +#define COMP2 (0x02) + +/**************** Bit definition for COMP_CR1 and COMP_CR2 register **************************/ +#define COMP_CR_LOCK (BIT31) +#define COMP_CR_BLANKTIME_POS (29U) +#define COMP_CR_BLANKTIME_MASK (BIT30|BIT29) +#define COMP_CR_CRV_CFG_POS (25U) +#define COMP_CR_CRV_CFG_MASK (BIT28|BIT27|BIT26|BIT25) +#define COMP_CR_CRV_SEL (BIT24) +#define COMP_CR_CRV_EN (BIT23) +#define COMP_CR_WINMODE (BIT22) +#define COMP_CR_WINOUT (BIT21) +#define COMP_CR_POLARITY (BIT20) +#define COMP_CR_FLTEN (BIT19) +#define COMP_CR_FLTTIME_POS (16U) +#define COMP_CR_FLTTIME_MASK (BIT18|BIT17|BIT16) +#define COMP_CR_BLANKSEL_POS (12U) +#define COMP_CR_BLANKSEL_MASK (BIT15|BIT14|BIT13|BIT12) +#define COMP_CR_INPSEL_POS (8U) +#define COMP_CR_INPSEL_MASK (BIT11|BIT10|BIT9|BIT8) +#define COMP_CR_INMSEL_POS (4U) +#define COMP_CR_INMSEL_MASK (BIT7|BIT6|BIT5|BIT4) +#define COMP_CR_HYS_POS (1U) +#define COMP_CR_HYS_MASK (BIT3|BIT2|BIT1) +#define COMP_CR_EN (BIT0) + +/**************** Bit definition for COMP_SR register **************************/ +#define COMP_SR_VCOUT2_ORG (BIT3) +#define COMP_SR_VCOUT1_ORG (BIT2) +#define COMP_SR_VCOUT2 (BIT1) +#define COMP_SR_VCOUT1 (BIT0) + +/** + * @brief COMP Configuration Structure definition + */ +typedef struct +{ + uint8_t Comparator; /*!< Specify witch comparator be selected */ + uint32_t Crv_En; + uint32_t BlankTime; + uint32_t Crv_Sel; + uint32_t Crv_Cfg; + uint32_t WinMode; + uint32_t WinOut; + uint32_t Polarity; + uint32_t FltEn; + uint32_t FltTime; + uint32_t BlankSel; + uint32_t InPSel; + uint32_t InMSel; + uint32_t HYS; +}COMP_InitTypeDef; + +/** + * @brief COMP handle Structure definition + */ +typedef struct +{ + COMP_TypeDef *Instance; /*!< Register base address */ + COMP_InitTypeDef Init; /*!< COMP required parameters */ + uint8_t OutputLevel_Org; /*!< COMP OutputLevel original */ + uint8_t OutputLevel; /*!< COMP OutputLevel with filter */ +} COMP_HandleTypeDef; + +#define COMP_CR_CRV_EN_DISABLE (0U) +#define COMP_CR_CRV_EN_ENABLE (1U) + +#define COMP_CR_CRV_SEL_AVDD (0U) +#define COMP_CR_CRV_SEL_VREF (1U) + +#define COMP_CR1_WINMODE_COMP1_INPSEL (0U) +#define COMP_CR1_WINMODE_COMP2_INPSEL (1U) + +#define COMP_CR2_WINMODE_COMP2_INPSEL (0U) +#define COMP_CR2_WINMODE_COMP1_INPSEL (1U) + +#define COMP_CR1_WINOUT_VCOUT1 (0U) +#define COMP_CR2_WINOUT_VCOUT2 (0U) +#define COMP_CR_WINOUT_VCOUT12 (1U) + +#define COMP_CR_POLARITY_P (0U) +#define COMP_CR_POLARITY_N (1U) + +#define COMP_CR_FLTEN_DISABLE (0U) +#define COMP_CR_FLTEN_ENABLE (1U) + +#define COMP_CR_FLTTIME_1_CLK (0U) +#define COMP_CR_FLTTIME_2_CLK (1U) +#define COMP_CR_FLTTIME_4_CLK (2U) +#define COMP_CR_FLTTIME_16_CLK (3U) +#define COMP_CR_FLTTIME_64_CLK (4U) +#define COMP_CR_FLTTIME_256_CLK (5U) +#define COMP_CR_FLTTIME_1024_CLK (6U) +#define COMP_CR_FLTTIME_4095_CLK (7U) + +#define COMP_CR_BLANKTIME_32_CLK (0U) +#define COMP_CR_BLANKTIME_64_CLK (1U) +#define COMP_CR_BLANKTIME_128_CLK (2U) +#define COMP_CR_BLANKTIME_256_CLK (3U) + +#define COMP_CR_BLANKSEL_NONE (0U) +#define COMP_CR_BLANKSEL_1 (1U) +#define COMP_CR_BLANKSEL_2 (2U) +#define COMP_CR_BLANKSEL_3 (4U) +#define COMP_CR_BLANKSEL_4 (8U) + +#define COMP_CR_INPSEL_0 (0U) +#define COMP_CR_INPSEL_1 (1U) +#define COMP_CR_INPSEL_2 (2U) + +#define COMP_CR_INMSEL_0 (0U) +#define COMP_CR_INMSEL_1 (1U) +#define COMP_CR_INMSEL_2 (2U) +#define COMP_CR_INMSEL_3 (3U) + +#define COMP_CR_HYS_DISABLE (0U) +#define COMP_CR_HYS_1 (4U) +#define COMP_CR_HYS_2 (5U) +#define COMP_CR_HYS_3 (6U) +#define COMP_CR_HYS_4 (7U) + +/******************************** COMP Instances *******************************/ +#define IS_COMP_ALL_INSTANCE(INSTANCE) ((INSTANCE) == COMP) +#define IS_COMP_ALL_COMP(_COMP) (((_COMP) == COMP1) || \ + ((_COMP) == COMP2)) + +#define IS_COMP_ALL_CRV_EN(_CRV_EN) (((_CRV_EN) == COMP_CR_CRV_EN_DISABLE) || \ + ((_CRV_EN) == COMP_CR_CRV_EN_ENABLE)) + +#define IS_COMP_ALL_CRV_SEL(_CRV_SEL) (((_CRV_SEL) == COMP_CR_CRV_SEL_AVDD) || \ + ((_CRV_SEL) == COMP_CR_CRV_SEL_VREF)) + +#define IS_COMP_ALL_CRV_CFG(_CRV_CFG) ((_CRV_CFG) <= 15U) + +#define IS_COMP_ALL_WINMODE(WINMODE) (((WINMODE) == COMP_CR1_WINMODE_COMP1_INPSEL) || \ + ((WINMODE) == COMP_CR1_WINMODE_COMP2_INPSEL) || \ + ((WINMODE) == COMP_CR2_WINMODE_COMP2_INPSEL) || \ + ((WINMODE) == COMP_CR2_WINMODE_COMP1_INPSEL)) + +#define IS_COMP_ALL_WINOUT(_WINOUT) (((_WINOUT) == COMP_CR1_WINOUT_VCOUT1) || \ + ((_WINOUT) == COMP_CR2_WINOUT_VCOUT2) || \ + ((_WINOUT) == COMP_CR_WINOUT_VCOUT12)) + +#define IS_COMP_ALL_POLARITY(POLARITY) (((POLARITY) == COMP_CR_POLARITY_N) || \ + ((POLARITY) == COMP_CR_POLARITY_P)) + +#define IS_COMP_ALL_FLTEN(FLTEN) (((FLTEN) == COMP_CR_FLTEN_DISABLE) || \ + ((FLTEN) == COMP_CR_FLTEN_ENABLE)) + +#define IS_COMP_ALL_FLTTIME(FLTTIME) (((FLTTIME) == COMP_CR_FLTTIME_1_CLK) || \ + ((FLTTIME) == COMP_CR_FLTTIME_2_CLK) || \ + ((FLTTIME) == COMP_CR_FLTTIME_4_CLK) || \ + ((FLTTIME) == COMP_CR_FLTTIME_16_CLK) || \ + ((FLTTIME) == COMP_CR_FLTTIME_64_CLK) || \ + ((FLTTIME) == COMP_CR_FLTTIME_256_CLK) || \ + ((FLTTIME) == COMP_CR_FLTTIME_1024_CLK) || \ + ((FLTTIME) == COMP_CR_FLTTIME_4095_CLK)) + +#define IS_COMP_ALL_BLANKTIME(BLANKTIME) (((BLANKTIME) == COMP_CR_BLANKTIME_32_CLK) || \ + ((BLANKTIME) == COMP_CR_BLANKTIME_64_CLK) || \ + ((BLANKTIME) == COMP_CR_BLANKTIME_128_CLK) || \ + ((BLANKTIME) == COMP_CR_BLANKTIME_256_CLK)) + +#define IS_COMP_ALL_BLANKSEL(BLANKSEL) (((BLANKSEL) == COMP_CR_BLANKSEL_NONE) || \ + ((BLANKSEL) == COMP_CR_BLANKSEL_1) || \ + ((BLANKSEL) == COMP_CR_BLANKSEL_2) || \ + ((BLANKSEL) == COMP_CR_BLANKSEL_3) || \ + ((BLANKSEL) == COMP_CR_BLANKSEL_4)) + +#define IS_COMP_ALL_INPSEL(INPSEL) (((INPSEL) == COMP_CR_INPSEL_0) || \ + ((INPSEL) == COMP_CR_INPSEL_1) || \ + ((INPSEL) == COMP_CR_INPSEL_2)) + +#define IS_COMP_ALL_INMSEL(INMSEL) (((INMSEL) == COMP_CR_INMSEL_0 ) || \ + ((INMSEL) == COMP_CR_INMSEL_1 ) || \ + ((INMSEL) == COMP_CR_INMSEL_2 ) || \ + ((INMSEL) == COMP_CR_INMSEL_3 )) + +#define IS_COMP_ALL_HYS(_HYS) (((_HYS) == COMP_CR_HYS_DISABLE) || \ + ((_HYS) == COMP_CR_HYS_1) || \ + ((_HYS) == COMP_CR_HYS_2) || \ + ((_HYS) == COMP_CR_HYS_3) || \ + ((_HYS) == COMP_CR_HYS_4)) + +/* Function */ +void HAL_COMP_MspInit(COMP_HandleTypeDef* hcomp); +void HAL_COMP_MspDeInit(COMP_HandleTypeDef* hcomp); +HAL_StatusTypeDef HAL_COMP_Init(COMP_HandleTypeDef* hcomp); +HAL_StatusTypeDef HAL_COMP_DeInit(COMP_HandleTypeDef* hcomp); +HAL_StatusTypeDef HAL_COMP_Enable(COMP_HandleTypeDef* hcomp); +HAL_StatusTypeDef HAL_COMP_Disable(COMP_HandleTypeDef* hcomp); +HAL_StatusTypeDef HAL_COMP_GetOutputLevel(COMP_HandleTypeDef* hcomp); +HAL_StatusTypeDef HAL_COMP_Lock(COMP_HandleTypeDef* hcomp); +HAL_StatusTypeDef HAL_COMP_Start(COMP_HandleTypeDef *hcomp); +HAL_StatusTypeDef HAL_COMP_Stop(COMP_HandleTypeDef *hcomp); + +#endif + + + + + diff --git a/bsp/acm32f4xx-nucleo/libraries/HAL_Driver/Inc/HAL_CRC.h b/bsp/acm32f4xx-nucleo/libraries/HAL_Driver/Inc/HAL_CRC.h new file mode 100644 index 0000000000..c1da7bed84 --- /dev/null +++ b/bsp/acm32f4xx-nucleo/libraries/HAL_Driver/Inc/HAL_CRC.h @@ -0,0 +1,154 @@ +/* + ****************************************************************************** + * @file HAL_CRC.h + * @version V1.0.0 + * @date 2021 + * @brief Header file of CRC HAL module. + ****************************************************************************** +*/ +#ifndef __HAL_CRC_H__ +#define __HAL_CRC_H__ +#include "ACM32Fxx_HAL.h" + +/** @defgroup CRC POLY Reverse + * @{ + */ + #define CRC_POLY_REV_EN (0x00000400U) /*!< Poly Reverse Enable */ + #define CRC_POLY_REV_DIS (0x00000000U) /*!< Poly Reverse Disable */ +/** + * @} + */ + +/** @defgroup CRC OUTXOR Reverse + * @{ + */ + #define CRC_OUTXOR_REV_EN (0x00000200U) /*!< OUTXOR Reverse Enable */ + #define CRC_OUTXOR_REV_DIS (0x00000000U) /*!< OUTXOR Reverse Disable */ +/** + * @} + */ + +/** @defgroup CRC INIT Reverse + * @{ + */ + #define CRC_INIT_REV_EN (0x00000100U) /*!< INIT Reverse Enable */ + #define CRC_INIT_REV_DIS (0x00000000U) /*!< INIT Reverse Disable */ +/** + * @} + */ + +/** @defgroup CRC RSLT Reverse + * @{ + */ + #define CRC_RSLT_REV_EN (0x00000080U) /*!< RSLT Reverse Enable */ + #define CRC_RSLT_REV_DIS (0x00000000U) /*!< RSLT Reverse Disable */ +/** + * @} + */ + +/** @defgroup CRC DATA Reverse + * @{ + */ + #define CRC_DATA_REV_DISABLE (0x00000000U) /*!< DATA Reverse Disable */ + #define CRC_DATA_REV_BY_BYTE (0x00000020U) /*!< DATA Reverse By Byte */ + #define CRC_DATA_REV_BY_HALFWORD (0x00000040U) /*!< DATA Reverse By HalfWord */ + #define CRC_DATA_REV_BY_WORD (0x00000060U) /*!< DATA Reverse By Word */ +/** + * @} + */ + +/** @defgroup CRC Poly Len + * @{ + */ + #define CRC_POLTY_LEN_32 (0x00000000U) /*!< POLY len = 32bit */ + #define CRC_POLTY_LEN_16 (0x00000008U) /*!< POLY len = 16bit */ + #define CRC_POLTY_LEN_8 (0x00000010U) /*!< POLY len = 8bit */ + #define CRC_POLTY_LEN_7 (0x00000018U) /*!< POLY len = 7bit */ +/** + * @} + */ + +/** @defgroup CRC Data Len + * @{ + */ + #define CRC_DATA_LEN_1B (0x00000000U) /*!< DATA len = 1 Byte */ + #define CRC_DATA_LEN_2B (0x00000002U) /*!< DATA len = 2 Byte */ + #define CRC_DATA_LEN_3B (0x00000004U) /*!< DATA len = 3 Byte */ + #define CRC_DATA_LEN_4B (0x00000006U) /*!< DATA len = 4 Byte */ +/** + * @} + */ + +/** @defgroup CRC RST + * @{ + */ + #define CRC_RST_EN (0x00000001U) /*!< RST CRC_DATA To CRC_INIT */ + #define CRC_RST_DIS (0x00000000U) /*!< RST CRC_DATA To CRC_INIT */ + +/** + * @} + */ + +/* + * @brief CRC Init Structure definition + */ +typedef struct +{ + uint32_t PolyRev; /*!< Specifies if the Poly is reversed in CRC + This parameter can be a value of @ref CRC POLY Reverse. */ + uint32_t OutxorRev; /*!< Specifies if the Outxor is reversed in CRC + This parameter can be a value of @ref CRC OUTXOR Reverse. */ + uint32_t InitRev; /*!< Specifies if the Init is reversed in CRC + This parameter can be a value of @ref CRC INIT Reverse. */ + uint32_t RsltRev; /*!< Specifies if the Result is reversed in CRC + This parameter can be a value of @ref CRC RSLT Reverse. */ + uint32_t DataRev; /*!< Specifies if the Data is reversed in CRC + This parameter can be a value of @ref CRC DATA Reverse. */ + uint32_t PolyLen; /*!< Specifies the Poly Len in CRC + This parameter can be a value of @ref CRC Poly Len. */ + uint32_t DataLen; /*!< Specifies the Data Len in CRC + This parameter can be a value of @ref CRC Data Len. */ + uint32_t RST; /*!< Specifies if CRC is reset + This parameter can be a value of @ref CRC RST. */ + + uint32_t InitData; /*!< This member configures the InitData. */ + + uint32_t OutXorData; /*!< This member configures the OutXorData. */ + + uint32_t PolyData; /*!< This member configures the PolyData. */ + + uint32_t FData; /*!< This member configures the FData. */ + +}CRC_InitTypeDef; + +/* + * @brief UART handle Structure definition + */ +typedef struct +{ + CRC_TypeDef *Instance; /*!< CRC registers base address */ + + CRC_InitTypeDef Init; /*!< CRC calculate parameters */ + + uint8_t* CRC_Data_Buff; /*!< CRC databuff base address */ + + uint32_t CRC_Data_Len; /*!< amount of CRC data to be calculated */ + +}CRC_HandleTypeDef; + + +/********************************************************************************* +* Function : HAL_CRC_Calculate +* Description : Calculate the crc calue of input data. +* Input : hcrc: CRC handle. +* Output : CRC value +* Author : cl Data : 2021 +**********************************************************************************/ +uint32_t HAL_CRC_Calculate(CRC_HandleTypeDef *hcrc); + + +#endif + + + + diff --git a/bsp/acm32f4xx-nucleo/libraries/HAL_Driver/Inc/HAL_DAC.h b/bsp/acm32f4xx-nucleo/libraries/HAL_Driver/Inc/HAL_DAC.h new file mode 100644 index 0000000000..64efee2c98 --- /dev/null +++ b/bsp/acm32f4xx-nucleo/libraries/HAL_Driver/Inc/HAL_DAC.h @@ -0,0 +1,589 @@ +/* + ****************************************************************************** + * @file HAL_Can.h + * @version V1.0.0 + * @date 2020 + * @brief Header file of CAN HAL module. + ****************************************************************************** +*/ +#ifndef __HAL_DAC_H__ +#define __HAL_DAC_H__ + +#include "ACM32Fxx_HAL.h" + +/** + * @} + */ + +/******************************************************************************/ +/* Peripheral Registers Bits Definition */ +/******************************************************************************/ +/******************************************************************************/ +/* (DAC) */ +/******************************************************************************/ + +/**************** Bit definition for DAC CR register ***********************/ +#define DAC_CR_EN1_Pos (0U) +#define DAC_CR_EN1_Msk (0x1UL << DAC_CR_EN1_Pos) /*!< 0x00000001 */ +#define DAC_CR_EN1 DAC_CR_EN1_Msk /*!*/ + +#define DAC_CR_CEN1_Pos (14U) +#define DAC_CR_CEN1_Msk (0x1UL << DAC_CR_CEN1_Pos) /*!< 0x00004000 */ +#define DAC_CR_CEN1 DAC_CR_CEN1_Msk /*!*/ + +#define DAC_CR_EN2_Pos (16U) +#define DAC_CR_EN2_Msk (0x1UL << DAC_CR_EN2_Pos) /*!< 0x00010000 */ +#define DAC_CR_EN2 DAC_CR_EN2_Msk /*!*/ + +#define DAC_CR_CEN2_Pos (30U) +#define DAC_CR_CEN2_Msk (0x1UL << DAC_CR_CEN2_Pos) /*!< 0x40000000 */ +#define DAC_CR_CEN2 DAC_CR_CEN2_Msk /*!*/ + +/**************** Bit definition for DAC SWTRIGR register ***********************/ +#define DAC_SWTRIGR_SWTRIG1_Pos (0U) +#define DAC_SWTRIGR_SWTRIG1_Msk (0x1UL << DAC_SWTRIGR_SWTRIG1_Pos) /*!< 0x00000001 */ +#define DAC_SWTRIGR_SWTRIG1 DAC_SWTRIGR_SWTRIG1_Msk /*!CTRL = (EFC->CTRL & ~(0x1F << 7)) | (wait << 7);} + +/* Exported functions --------------------------------------------------------*/ + +/* HAL_EFlash_Init */ +void HAL_EFlash_Init(uint32_t fu32_freq); +/* HAL_EFlash_ErasePage */ +bool HAL_EFlash_ErasePage(uint32_t fu32_Addr); + +/* HAL_EFlash_Program_Word */ +bool HAL_EFlash_Program_Word(uint32_t fu32_Addr, uint32_t fu32_Data); + +#endif diff --git a/bsp/acm32f4xx-nucleo/libraries/HAL_Driver/Inc/HAL_EFlash_EX.h b/bsp/acm32f4xx-nucleo/libraries/HAL_Driver/Inc/HAL_EFlash_EX.h new file mode 100644 index 0000000000..602883c40c --- /dev/null +++ b/bsp/acm32f4xx-nucleo/libraries/HAL_Driver/Inc/HAL_EFlash_EX.h @@ -0,0 +1,26 @@ +/* + ****************************************************************************** + * @file HAL_EFlash_EX.h + * @version V1.0.0 + * @date 2021 + * @brief Header file of EFlash extention module + ****************************************************************************** +*/ +#ifndef __HAL_EFlash_EX_H__ +#define __HAL_EFlash_EX_H__ + +#include "stdint.h" + +/* HAL_EFlash_Return_To_Boot */ +void HAL_EFlash_Return_to_Boot(void); + +/* HAL_EFlash_Init_Para */ +void HAL_EFlash_Init_Para(uint32_t fu32_freq); + +/* HAL_EFlash_ErasePage_EX */ +void HAL_EFlash_ErasePage_EX(uint32_t fu32_Addr); + +/* HAL_EFlash_Program_Word_EX */ +void HAL_EFlash_Program_Word_EX(uint32_t fu32_Addr, uint32_t fu32_Data); + +#endif diff --git a/bsp/acm32f4xx-nucleo/libraries/HAL_Driver/Inc/HAL_EXTI.h b/bsp/acm32f4xx-nucleo/libraries/HAL_Driver/Inc/HAL_EXTI.h new file mode 100644 index 0000000000..0dcf0fed74 --- /dev/null +++ b/bsp/acm32f4xx-nucleo/libraries/HAL_Driver/Inc/HAL_EXTI.h @@ -0,0 +1,166 @@ +/* + ****************************************************************************** + * @file HAL_EXTI.h + * @version V1.0.0 + * @date 2020 + * @brief Header file of EXTI HAL module. + ****************************************************************************** +*/ +#ifndef __HAL_EXTI_H__ +#define __HAL_EXTI_H__ + +#include "ACM32Fxx_HAL.h" + +/** @defgroup EXTI_Line EXTI Line + * @{ + */ +#define EXTI_LINE_0 (0x000001) +#define EXTI_LINE_1 (0x000002) +#define EXTI_LINE_2 (0x000004) +#define EXTI_LINE_3 (0x000008) +#define EXTI_LINE_4 (0x000010) +#define EXTI_LINE_5 (0x000020) +#define EXTI_LINE_6 (0x000040) +#define EXTI_LINE_7 (0x000080) +#define EXTI_LINE_8 (0x000100) +#define EXTI_LINE_9 (0x000200) +#define EXTI_LINE_10 (0x000300) +#define EXTI_LINE_11 (0x000400) +#define EXTI_LINE_12 (0x001000) +#define EXTI_LINE_13 (0x002000) +#define EXTI_LINE_14 (0x004000) +#define EXTI_LINE_15 (0x008000) +#define EXTI_LINE_16 (0x010000) +#define EXTI_LINE_17 (0x020000) +#define EXTI_LINE_18 (0x040000) +#define EXTI_LINE_19 (0x080000) +#define EXTI_LINE_20 (0x100000) +#define EXTI_LINE_21 (0x200000) +#define EXTI_LINE_22 (0x400000) +#define EXTI_LINE_23 (0x800000) +#define EXTI_LINE_MASK (0xFFFFFFU) +/** + * @} + */ + + +/** @defgroup EXTI_Mode EXTI Mode + * @{ + */ +#define EXTI_MODE_INTERRUPT (0x00000001) +#define EXTI_MODE_EVENT (0x00000002) +/** + * @} + */ + + +/** @defgroup EXTI_Trigger EXTI Trigger + * @{ + */ +#define EXTI_TRIGGER_RISING (0x00000001) +#define EXTI_TRIGGER_FALLING (0x00000002) +#define EXTI_TRIGGER_RISING_FALLING (EXTI_TRIGGER_RISING | EXTI_TRIGGER_FALLING) +/** + * @} + */ + + +/** @defgroup EXTI_GPIOSel EXTI GPIOSel + * @brief + * @{ + */ +#define EXTI_GPIOA 0x00000000u +#define EXTI_GPIOB 0x00000001u +#define EXTI_GPIOC 0x00000002u +#define EXTI_GPIOD 0x00000003u +#define EXTI_GPIOE 0x00000004u +#define EXTI_GPIOF 0x00000005u +/** + * @} + */ + + +/** + * @brief EXTI Configuration structure definition + */ +typedef struct +{ + uint32_t u32_Line; /*!< The Exti line to be configured. This parameter + can be a value of @ref EXTI_Line */ + uint32_t u32_Mode; /*!< The Exit Mode to be configured for a core. + This parameter can be a combination of @ref EXTI_Mode */ + uint32_t u32_Trigger; /*!< The Exti Trigger to be configured. This parameter + can be a value of @ref EXTI_Trigger */ + uint32_t u32_GPIOSel; /*!< The Exti GPIO multiplexer selection to be configured. + This parameter is only possible for line 0 to 15. It + can be a value of @ref EXTI_GPIOSel */ +}EXTI_HandleTypeDef; + + +/** @defgroup EXTI Private Macros + * @{ + */ +#define IS_EXTI_ALL_LINE(LINE) ( (LINE) | (EXTI_LINE_MASK) ) + +#define IS_EXTI_MODE(__MODE__) (((__MODE__) == EXTI_MODE_INTERRUPT) || \ + ((__MODE__) == EXTI_MODE_EVENT)) + +#define IS_EXTI_TRIGGER(__TRIGGER__) (((__TRIGGER__) == EXTI_TRIGGER_RISING) || \ + ((__TRIGGER__) == EXTI_TRIGGER_FALLING) || \ + ((__TRIGGER__) == EXTI_TRIGGER_RISING_FALLING)) + +#define IS_EXTI_GPIOSEL(__GPIOSEL__) (((__GPIOSEL__) == EXTI_GPIOA) || \ + ((__GPIOSEL__) == EXTI_GPIOB) || \ + ((__GPIOSEL__) == EXTI_GPIOC) || \ + ((__GPIOSEL__) == EXTI_GPIOD) || \ + ((__GPIOSEL__) == EXTI_GPIOE) || \ + ((__GPIOSEL__) == EXTI_GPIOF)) +/** + * @} + */ + +/** @brief __HAL_EXTI_LINE_IT_ENABLE + * @param __LINE__: EXTI line. + * This parameter can be a value of @ref EXTI_Line + */ +#define __HAL_EXTI_LINE_IT_ENABLE(__LINE__) (EXTI->IENR |= (__LINE__)) + +/** @brief __HAL_EXTI_LINE_IT_DISABLE + * @param __LINE__: EXTI line. + * This parameter can be a value of @ref EXTI_Line + */ +#define __HAL_EXTI_LINE_IT_DISABLE(__LINE__) (EXTI->IENR &= ~(__LINE__)) + +/** @brief __HAL_EXTI_LINE_EVENT_ENABLE + * @param __LINE__: EXTI line. + * This parameter can be a value of @ref EXTI_Line + */ +#define __HAL_EXTI_LINE_EVENT_ENABLE(__LINE__) (EXTI->EENR |= (__LINE__)) + +/** @brief __HAL_EXTI_LINE_EVENT_DISABLE + * @param __LINE__: EXTI line. + * This parameter can be a value of @ref EXTI_Line + */ +#define __HAL_EXTI_LINE_EVENT_DISABLE(__LINE__) (EXTI->EENR &= ~(__LINE__)) + + +/* HAL_EXTI_IRQHandler */ +void HAL_EXTI_IRQHandler(EXTI_HandleTypeDef *huart); + +/* HAL_EXTI_SetConfigLine */ +HAL_StatusTypeDef HAL_EXTI_SetConfigLine(EXTI_HandleTypeDef *hexti); + +/* HAL_EXTI_SoftTrigger */ +void HAL_EXTI_SoftTrigger(EXTI_HandleTypeDef *hexti); + +/* HAL_EXTI_GetPending */ +bool HAL_EXTI_GetPending(EXTI_HandleTypeDef *hexti); + +/* HAL_EXTI_ClearPending */ +void HAL_EXTI_ClearPending(EXTI_HandleTypeDef *hexti); + +/* HAL_EXTI_ClearAllPending */ +void HAL_EXTI_ClearAllPending(void); + +#endif + diff --git a/bsp/acm32f4xx-nucleo/libraries/HAL_Driver/Inc/HAL_FAU.h b/bsp/acm32f4xx-nucleo/libraries/HAL_Driver/Inc/HAL_FAU.h new file mode 100644 index 0000000000..617035702c --- /dev/null +++ b/bsp/acm32f4xx-nucleo/libraries/HAL_Driver/Inc/HAL_FAU.h @@ -0,0 +1,170 @@ + +#ifndef __FAU_H_ +#define __FAU_H_ + +#define RANGE 2147483648U //2^31 +#define CORDIC_F_31 0xD2C90A46 // CORDIC gain F + +/************************************************************************** +* Function Name : HAL_CORDIC_CosSin( precision 1 ) +* Description : calculate the sin & cos value of the input angle +* Input : - angle_para : input angle data in radians, divided by [range[-1,1],Q31 format]; +* Output : - * cos_data : the cos value of the input angle[range[-1,1],Q31 format] + - * sin_data : the sin value of the input angle[range[-1,1],Q31 format] +* Return : None +**************************************************************************/ +void HAL_CORDIC_CosSin_1(int angle_para, int* cos_data, int* sin_data); +/************************************************************************** +* Function Name : HAL_CORDIC_CosSin( precision 2 ) +* Description : calculate the sin & cos value of the input angle +* Input : - angle_para : input angle data in radians, divided by [range[-1,1],Q31 format]; +* Output : - * cos_data : the cos value of the input angle[range[-1,1],Q31 format] + - * sin_data : the sin value of the input angle[range[-1,1],Q31 format] +* Return : None +**************************************************************************/ +void HAL_CORDIC_CosSin_2(int angle_para, int* cos_data, int* sin_data); +/************************************************************************** +* Function Name : HAL_CORDIC_CosSin( precision 3 ) +* Description : calculate the sin & cos value of the input angle +* Input : - angle_para : input angle data in radians, divided by [range[-1,1],Q31 format]; +* Output : - * cos_data : the cos value of the input angle[range[-1,1],Q31 format] + - * sin_data : the sin value of the input angle[range[-1,1],Q31 format] +* Return : None +**************************************************************************/ +void HAL_CORDIC_CosSin_3(int angle_para, int* cos_data, int* sin_data); +/************************************************************************** +* Function Name : HAL_CORDIC_CosSin( precision 4 ) +* Description : calculate the sin & cos value of the input angle +* Input : - angle_para : input angle data in radians, divided by [range[-1,1],Q31 format]; +* Output : - * cos_data : the cos value of the input angle[range[-1,1],Q31 format] + - * sin_data : the sin value of the input angle[range[-1,1],Q31 format] +* Return : None +**************************************************************************/ +void HAL_CORDIC_CosSin_4(int angle_para, int* cos_data, int* sin_data); +/************************************************************************** +* Function Name : HAL_CORDIC_CosSin( precision 5 ) +* Description : calculate the sin & cos value of the input angle +* Input : - angle_para : input angle data in radians, divided by [range[-1,1],Q31 format]; +* Output : - * cos_data : the cos value of the input angle[range[-1,1],Q31 format] + - * sin_data : the sin value of the input angle[range[-1,1],Q31 format] +* Return : None +**************************************************************************/ +void HAL_CORDIC_CosSin_5(int angle_para, int* cos_data, int* sin_data); +/************************************************************************** +* Function Name : HAL_CORDIC_CosSin( precision 6 ) +* Description : calculate the sin & cos value of the input angle +* Input : - angle_para : input angle data in radians, divided by [range[-1,1],Q31 format]; +* Output : - * cos_data : the cos value of the input angle[range[-1,1],Q31 format] + - * sin_data : the sin value of the input angle[range[-1,1],Q31 format] +* Return : None +**************************************************************************/ +void HAL_CORDIC_CosSin_6(int angle_para, int* cos_data, int* sin_data); +/************************************************************************** +* Function Name : HAL_CORDIC_CosSin( precision 7 ) +* Description : calculate the sin & cos value of the input angle +* Input : - angle_para : input angle data in radians, divided by [range[-1,1],Q31 format]; +* Output : - * cos_data : the cos value of the input angle[range[-1,1],Q31 format] + - * sin_data : the sin value of the input angle[range[-1,1],Q31 format] +* Return : None +**************************************************************************/ +void HAL_CORDIC_CosSin_7(int angle_para, int* cos_data, int* sin_data); +/************************************************************************** +* Function Name : HAL_CORDIC_CosSin( precision 8 ) +* Description : calculate the sin & cos value of the input angle +* Input : - angle_para : input angle data in radians, divided by [range[-1,1],Q31 format]; +* Output : - * cos_data : the cos value of the input angle[range[-1,1],Q31 format] + - * sin_data : the sin value of the input angle[range[-1,1],Q31 format] +* Return : None +**************************************************************************/ +void HAL_CORDIC_CosSin_8(int angle_para, int* cos_data, int* sin_data); + +/************************************************************************** +* Function Name : HAL_CORDIC_AtanSqrt( precision 1 ) +* Description : calculate the atan & sqrt value of the input x,y +* Input : - x : input x data[range[-1,1],Q31 format]; +* : - y : input y data[range[-1,1],Q31 format]; + : - precision : the precison used in calculation +* Output : - * sqrt_data : the sqrt value of the input x,y[Q31 format] + - * atan_data : the atan value of the input x,y[Q31 format] +* Return : None +**************************************************************************/ +void HAL_CORDIC_AtanSqrt_1(int x, int y, int*sqrt_data, int* atan_data); +/************************************************************************** +* Function Name : HAL_CORDIC_AtanSqrt( precision 2 ) +* Description : calculate the atan & sqrt value of the input x,y +* Input : - x : input x data[range[-1,1],Q31 format]; +* : - y : input y data[range[-1,1],Q31 format]; + : - precision : the precison used in calculation +* Output : - * sqrt_data : the sqrt value of the input x,y[Q31 format] + - * atan_data : the atan value of the input x,y[Q31 format] +* Return : None +**************************************************************************/ +void HAL_CORDIC_AtanSqrt_2(int x, int y, int*sqrt_data, int* atan_data); +/************************************************************************** +* Function Name : HAL_CORDIC_AtanSqrt( precision 3 ) +* Description : calculate the atan & sqrt value of the input x,y +* Input : - x : input x data[range[-1,1],Q31 format]; +* : - y : input y data[range[-1,1],Q31 format]; + : - precision : the precison used in calculation +* Output : - * sqrt_data : the sqrt value of the input x,y[Q31 format] + - * atan_data : the atan value of the input x,y[Q31 format] +* Return : None +**************************************************************************/ +void HAL_CORDIC_AtanSqrt_3(int x, int y, int*sqrt_data, int* atan_data); +/************************************************************************** +* Function Name : HAL_CORDIC_AtanSqrt( precision 4 ) +* Description : calculate the atan & sqrt value of the input x,y +* Input : - x : input x data[range[-1,1],Q31 format]; +* : - y : input y data[range[-1,1],Q31 format]; + : - precision : the precison used in calculation +* Output : - * sqrt_data : the sqrt value of the input x,y[Q31 format] + - * atan_data : the atan value of the input x,y[Q31 format] +* Return : None +**************************************************************************/ +void HAL_CORDIC_AtanSqrt_4(int x, int y, int*sqrt_data, int* atan_data); +/************************************************************************** +* Function Name : HAL_CORDIC_AtanSqrt( precision 5 ) +* Description : calculate the atan & sqrt value of the input x,y +* Input : - x : input x data[range[-1,1],Q31 format]; +* : - y : input y data[range[-1,1],Q31 format]; + : - precision : the precison used in calculation +* Output : - * sqrt_data : the sqrt value of the input x,y[Q31 format] + - * atan_data : the atan value of the input x,y[Q31 format] +* Return : None +**************************************************************************/ +void HAL_CORDIC_AtanSqrt_5(int x, int y, int*sqrt_data, int* atan_data); +/************************************************************************** +* Function Name : HAL_CORDIC_AtanSqrt( precision 6 ) +* Description : calculate the atan & sqrt value of the input x,y +* Input : - x : input x data[range[-1,1],Q31 format]; +* : - y : input y data[range[-1,1],Q31 format]; + : - precision : the precison used in calculation +* Output : - * sqrt_data : the sqrt value of the input x,y[Q31 format] + - * atan_data : the atan value of the input x,y[Q31 format] +* Return : None +**************************************************************************/ +void HAL_CORDIC_AtanSqrt_6(int x, int y, int*sqrt_data, int* atan_data); +/************************************************************************** +* Function Name : HAL_CORDIC_AtanSqrt( precision 7 ) +* Description : calculate the atan & sqrt value of the input x,y +* Input : - x : input x data[range[-1,1],Q31 format]; +* : - y : input y data[range[-1,1],Q31 format]; + : - precision : the precison used in calculation +* Output : - * sqrt_data : the sqrt value of the input x,y[Q31 format] + - * atan_data : the atan value of the input x,y[Q31 format] +* Return : None +**************************************************************************/ +void HAL_CORDIC_AtanSqrt_7(int x, int y, int*sqrt_data, int* atan_data); +/************************************************************************** +* Function Name : HAL_CORDIC_AtanSqrt( precision 8 ) +* Description : calculate the atan & sqrt value of the input x,y +* Input : - x : input x data[range[-1,1],Q31 format]; +* : - y : input y data[range[-1,1],Q31 format]; + : - precision : the precison used in calculation +* Output : - * sqrt_data : the sqrt value of the input x,y[Q31 format] + - * atan_data : the atan value of the input x,y[Q31 format] +* Return : None +**************************************************************************/ +void HAL_CORDIC_AtanSqrt_8(int x, int y, int*sqrt_data, int* atan_data); + +#endif \ No newline at end of file diff --git a/bsp/acm32f4xx-nucleo/libraries/HAL_Driver/Inc/HAL_FSUSB.h b/bsp/acm32f4xx-nucleo/libraries/HAL_Driver/Inc/HAL_FSUSB.h new file mode 100644 index 0000000000..9600b4ded6 --- /dev/null +++ b/bsp/acm32f4xx-nucleo/libraries/HAL_Driver/Inc/HAL_FSUSB.h @@ -0,0 +1,105 @@ +/* + ****************************************************************************** + * @file HAL_Uart.h + * @version V1.0.0 + * @date 2020 + * @brief Header file of UART HAL module. + ****************************************************************************** +*/ +#ifndef __HAL_FSUSB_H__ +#define __HAL_FSUSB_H__ + +#include "ACM32Fxx_HAL.h" + + +#define HIGH_SPEED 1 +#define FULL_SPEED 0 + +#define USB_EP0 0 +#define USB_EP1 1 +#define USB_EP2 2 +#define USB_EP3 3 +#define USB_EP4 4 + +#define USB_EP_IN USB_EP1 +#define USB_EP_OUT USB_EP1 + +#define EP_DIR_IN 0x80 +#define EP_DIR_OUT 0x00 + +#define HID_REPORT_SIZE 1024 + +#define EP0_MAX_PACKET_SIZE 64 +#define EPX_MAX_PACKET_SIZE 64 +//#define EPX_MAX_PACKET_SIZE_HS 512 +//#define EPX_MAX_PACKET_SIZE_FS 64 + +#define MASK_EPX_IN(x) (1<<(6+3*x)) +#define MASK_EPX_OUT(x) (1<<(7+3*x)) +#define MASK_EPX_ACK(x) (1<<(8+3*x)) +#define MASK_EPX_TIMEOUT(x) (1<< (25+x)) + +typedef __PACKED_STRUCT _device_request +{ + uint8_t bmRequestType; + uint8_t bRequest; + uint16_t wValue; + uint16_t wIndex; + uint16_t wLength; +} DEVICE_REQUEST; + + + +#define USB_BUS_RESET 0x01 +#define USB_SUSPEND 0x02 +#define USB_RESUME 0x04 +#define USB_SOF 0x08 +#define USB_SETUPTOK 0x10 +#define USB_EP0_SETUP_PACKET 0x20 +#define USB_EP0_IN 0x40 +#define USB_EP0_OUT_PACKET 0x80 +#define USB_EP0_ACK 0x100 +#define USB_EP1_IN 0x200 +#define USB_EP1_OUT_PACKET 0x400 +#define USB_EP1_ACK 0x800 +#define USB_EP2_IN 0x1000 +#define USB_EP2_OUT_PACKET 0x2000 +#define USB_EP2_ACK 0x4000 +#define USB_EP3_IN 0x8000 +#define USB_EP3_OUT_PACKET 0x10000 +#define USB_EP3_ACK 0x20000 +#define USB_EP4_IN 0x40000 +#define USB_EP4_OUT_PACKET 0x80000 +#define USB_EP4_ACK 0x100000 +#define USB_IN_TIMEOUT 0x200000 +#define USB_SETADDR 0x400000 +#define USB_CRC_ERR 0x800000 +#define USB_MORETHAN_64 0x1000000 +#define USB_EP0_IN_ERR 0x2000000 +#define USB_EP1_IN_ERR 0x4000000 +#define USB_EP2_IN_ERR 0x8000000 +#define USB_EP3_IN_ERR 0x10000000 +#define USB_EP4_IN_ERR 0x20000000 +#define USB_NOEOP_ERR 0x40000000 +#define USB_TOGGLE_ERR 0x80000000 + + + +#define ERROR_OUT_OUT 4 // received a same out packet +#define ERROR_IN_OUT 2 // received a pakcet when try to send packet + + + +uint32_t HAL_FSUSB_Init(void); +void HAL_FSUSB_Read_EP_MEM8(uint8_t *dst, uint32_t length, uint32_t fifo_offset, uint8_t ep_index); +uint8_t HAL_FSUSB_Send_Data(uint8_t *buffer,uint32_t length,uint8_t ep_index); +void HAL_FSUSB_Receive_Data(uint8_t *buffer,uint32_t length,uint8_t ep_index); +uint16_t HAL_USB_Get_Stall_Status(uint8_t ep_index, uint8_t ep_dir); +void HAL_FSUSB_EP0_Send_Empty_Packet(void); +void HAL_FSUSB_EP0_Send_Stall(void); +void usb_clear_stall(uint8_t ep_index, uint8_t ep_dir); +void usb_send_stall(uint8_t ep_index, uint8_t ep_dir); +uint16_t HAL_FSUSB_Get_FIFO_Length(uint8_t ep_index); + +#endif + diff --git a/bsp/acm32f4xx-nucleo/libraries/HAL_Driver/Inc/HAL_GPIO.h b/bsp/acm32f4xx-nucleo/libraries/HAL_Driver/Inc/HAL_GPIO.h new file mode 100644 index 0000000000..cd66909380 --- /dev/null +++ b/bsp/acm32f4xx-nucleo/libraries/HAL_Driver/Inc/HAL_GPIO.h @@ -0,0 +1,214 @@ +/* + ****************************************************************************** + * @file HAL_GPIO.h + * @version V1.0.0 + * @date 2020 + * @brief Header file of GPIO HAL module. + ****************************************************************************** +*/ +#ifndef __HAL_GPIO_H__ +#define __HAL_GPIO_H__ + +#include "ACM32Fxx_HAL.h" + +/** @defgroup GPIO_pins GPIO pins + * @{ + */ +#define GPIO_PIN_0 ((uint16_t)0x0001) /* Pin 0 selected */ +#define GPIO_PIN_1 ((uint16_t)0x0002) /* Pin 1 selected */ +#define GPIO_PIN_2 ((uint16_t)0x0004) /* Pin 2 selected */ +#define GPIO_PIN_3 ((uint16_t)0x0008) /* Pin 3 selected */ +#define GPIO_PIN_4 ((uint16_t)0x0010) /* Pin 4 selected */ +#define GPIO_PIN_5 ((uint16_t)0x0020) /* Pin 5 selected */ +#define GPIO_PIN_6 ((uint16_t)0x0040) /* Pin 6 selected */ +#define GPIO_PIN_7 ((uint16_t)0x0080) /* Pin 7 selected */ +#define GPIO_PIN_8 ((uint16_t)0x0100) /* Pin 8 selected */ +#define GPIO_PIN_9 ((uint16_t)0x0200) /* Pin 9 selected */ +#define GPIO_PIN_10 ((uint16_t)0x0400) /* Pin 10 selected */ +#define GPIO_PIN_11 ((uint16_t)0x0800) /* Pin 11 selected */ +#define GPIO_PIN_12 ((uint16_t)0x1000) /* Pin 12 selected */ +#define GPIO_PIN_13 ((uint16_t)0x2000) /* Pin 13 selected */ +#define GPIO_PIN_14 ((uint16_t)0x4000) /* Pin 14 selected */ +#define GPIO_PIN_15 ((uint16_t)0x8000) /* Pin 15 selected */ + +#define GPIO_PIN_MASK (0x0000FFFFu) /* PIN mask for assert test */ +/** + * @} + */ + + +/** @defgroup GPIO_mode GPIO mode + * @{ + */ +#define GPIO_MODE_INPUT (0x00010000u) /*!< Input Floating Mode */ +#define GPIO_MODE_OUTPUT_PP (0x00010001u) /*!< Output Push Pull Mode */ +#define GPIO_MODE_OUTPUT_OD (0x00011002u) /*!< Output Open Drain Mode */ +#define GPIO_MODE_AF_PP (0x00000003u) /*!< Alternate Function Push Pull Mode */ +#define GPIO_MODE_AF_OD (0x00001004u) /*!< Alternate Function Open Drain Mode */ +#define GPIO_MODE_ANALOG (0x00000005u) /*!< Analog Mode */ +#define GPIO_MODE_IT_RISING (0x10010000u) /*!< External Interrupt Mode with Rising edge trigger detection */ +#define GPIO_MODE_IT_FALLING (0x10010001u) /*!< External Interrupt Mode with Falling edge trigger detection */ +#define GPIO_MODE_IT_RISING_FALLING (0x10010002u) /*!< External Interrupt Mode with Rising/Falling edge trigger detection */ +#define GPIO_MODE_IT_HIGH_LEVEL (0x10010003u) /*!< External Interrupt Mode with high level trigger detection */ +#define GPIO_MODE_IT_LOW_LEVEL (0x10010004u) /*!< External Interrupt Mode with low level trigger detection */ + +#define GPIO_MODE_OD_MASK (0x00001000u) /*!< OD Mode Mask */ +#define GPIO_MODE_IO_MASK (0x00010000u) /*!< Use GPIO Function Mask */ +#define GPIO_MODE_IT_MASK (0x10000000u) /*!< GPIO interrupt Mask */ +/** + * @} + */ + + +/** @defgroup GPIO_pull GPIO pull + * @{ + */ +#define GPIO_NOPULL (0x00000000u) /*!< No Pull-up or Pull-down activation */ +#define GPIO_PULLUP (0x00000001u) /*!< Pull-up activation */ +#define GPIO_PULLDOWN (0x00000002u) /*!< Pull-down activation */ +/** + * @} + */ + + +/** @defgroup GPIOEx_function_selection GPIO pull + * @{ + */ +#define GPIO_FUNCTION_0 (0x00000000u) +#define GPIO_FUNCTION_1 (0x00000001u) +#define GPIO_FUNCTION_2 (0x00000002u) +#define GPIO_FUNCTION_3 (0x00000003u) +#define GPIO_FUNCTION_4 (0x00000004u) +#define GPIO_FUNCTION_5 (0x00000005u) +#define GPIO_FUNCTION_6 (0x00000006u) +#define GPIO_FUNCTION_7 (0x00000007u) +#define GPIO_FUNCTION_8 (0x00000008u) +#define GPIO_FUNCTION_9 (0x00000009u) +/** + * @} + */ + + + +/** @defgroup GPIOx Index + * @{ + */ +typedef enum +{ + GPIOA, + GPIOB, + GPIOC, + GPIOD, + GPIOE, + GPIOF, +}enum_GPIOx_t; +/** + * @} + */ + + +/** @defgroup GPIO Bit SET and Bit RESET enumeration + * @{ + */ +typedef enum +{ + GPIO_PIN_CLEAR = 0u, + GPIO_PIN_SET = 1u, +}enum_PinState_t; +/** + * @} + */ + + + +/* + * @brief GPIO Init structure definition + */ +typedef struct +{ + uint32_t Pin; /*!< Specifies the GPIO pins to be configured. + This parameter can be any value of @ref GPIO_pins */ + + uint32_t Mode; /*!< Specifies the operating mode for the selected pins. + This parameter can be a value of @ref GPIO_mode */ + + uint32_t Pull; /*!< Specifies the Pull-up or Pull-Down activation for the selected pins. + This parameter can be a value of @ref GPIO_pull */ + + uint32_t Alternate; /*!< Peripheral to be connected to the selected pins + This parameter can be a value of @ref GPIOEx_function_selection */ +} GPIO_InitTypeDef; + + +/** @defgroup GPIO Private Macros + * @{ + */ +#define IS_GPIO_ALL_INSTANCE(INSTANCE) (((INSTANCE) == GPIOA) || \ + ((INSTANCE) == GPIOB) || \ + ((INSTANCE) == GPIOC) || \ + ((INSTANCE) == GPIOD) || \ + ((INSTANCE) == GPIOE) || \ + ((INSTANCE) == GPIOF)) + +#define IS_GPIO_PIN(__PIN__) ((((uint32_t)(__PIN__) & GPIO_PIN_MASK) != 0x00u) &&\ + (((uint32_t)(__PIN__) & ~GPIO_PIN_MASK) == 0x00u)) + + +#define IS_GPIO_MODE(__MODE__) (((__MODE__) == GPIO_MODE_INPUT) ||\ + ((__MODE__) == GPIO_MODE_OUTPUT_PP) ||\ + ((__MODE__) == GPIO_MODE_OUTPUT_OD) ||\ + ((__MODE__) == GPIO_MODE_AF_PP) ||\ + ((__MODE__) == GPIO_MODE_AF_OD) ||\ + ((__MODE__) == GPIO_MODE_IT_RISING) ||\ + ((__MODE__) == GPIO_MODE_IT_FALLING) ||\ + ((__MODE__) == GPIO_MODE_IT_RISING_FALLING) ||\ + ((__MODE__) == GPIO_MODE_IT_HIGH_LEVEL) ||\ + ((__MODE__) == GPIO_MODE_IT_LOW_LEVEL) ||\ + ((__MODE__) == GPIO_MODE_ANALOG)) + + + + +#define IS_GPIO_PULL(__PULL__) (((__PULL__) == GPIO_NOPULL) ||\ + ((__PULL__) == GPIO_PULLUP) ||\ + ((__PULL__) == GPIO_PULLDOWN)) + +#define IS_GPIO_PIN_ACTION(ACTION) (((ACTION) == GPIO_PIN_CLEAR) || ((ACTION) == GPIO_PIN_SET)) + +#define IS_GPIO_FUNCTION(__FUNCTION__) (((__FUNCTION__) == GPIO_FUNCTION_0) ||\ + ((__FUNCTION__) == GPIO_FUNCTION_1) ||\ + ((__FUNCTION__) == GPIO_FUNCTION_2) ||\ + ((__FUNCTION__) == GPIO_FUNCTION_3) ||\ + ((__FUNCTION__) == GPIO_FUNCTION_4) ||\ + ((__FUNCTION__) == GPIO_FUNCTION_5) ||\ + ((__FUNCTION__) == GPIO_FUNCTION_6) ||\ + ((__FUNCTION__) == GPIO_FUNCTION_7) ||\ + ((__FUNCTION__) == GPIO_FUNCTION_8) ||\ + ((__FUNCTION__) == GPIO_FUNCTION_9)) + +/** + * @} + */ + + +/* Exported functions --------------------------------------------------------*/ + +/* HAL_GPIO_IRQHandler */ +void HAL_GPIO_IRQHandler(enum_GPIOx_t fe_GPIO, uint32_t fu32_GPIO_Pin); + +/* HAL_GPIO_Init */ +void HAL_GPIO_Init(enum_GPIOx_t fe_GPIO, GPIO_InitTypeDef *GPIO_Init); + +/* HAL_GPIO_DeInit */ +void HAL_GPIO_DeInit(enum_GPIOx_t fe_GPIO, uint32_t fu32_Pin); + +/* HAL_GPIO_AnalogEnable */ +void HAL_GPIO_AnalogEnable(enum_GPIOx_t fe_GPIO, uint32_t fu32_Pin); + +/* HAL_GPIO_WritePin */ +void HAL_GPIO_WritePin(enum_GPIOx_t fe_GPIO, uint32_t fu32_GPIO_Pin, enum_PinState_t fe_PinState); + +/* HAL_GPIO_ReadPin */ +enum_PinState_t HAL_GPIO_ReadPin(enum_GPIOx_t fe_GPIO, uint32_t fu32_GPIO_Pin); + +#endif diff --git a/bsp/acm32f4xx-nucleo/libraries/HAL_Driver/Inc/HAL_HRNG.h b/bsp/acm32f4xx-nucleo/libraries/HAL_Driver/Inc/HAL_HRNG.h new file mode 100644 index 0000000000..75798eb923 --- /dev/null +++ b/bsp/acm32f4xx-nucleo/libraries/HAL_Driver/Inc/HAL_HRNG.h @@ -0,0 +1,53 @@ +/***********************************************************************f + * Filename : hrng.h + * Description : hrng header file + * Author(s) : cc + * version : V1.0 + * Modify date : 2021-03-24 + ***********************************************************************/ + +#ifndef __HRNG_H__ +#define __HRNG_H__ + +#include "ACM32Fxx_HAL.h" + +/********************************************************************************* +* Function Name : HAL_HRNG_Initial +* Description : initial hrng module +* Input : None +* Output : None +* Return : None +*********************************************************************************/ +void HAL_HRNG_Initial(void); + +/********************************************************************************* +* Function Name : HAL_HRNG_GetHrng_8 +* Description : get 8bit random number +* Input : None +* Output : None +* Return : 8 bit random number +*********************************************************************************/ +UINT8 HAL_HRNG_GetHrng_8(void); + +/********************************************************************************* +* Function Name : HAL_HRNG_GetHrng_32 +* Description : get 32bit random number +* Input : None +* Output : None +* Return : 32 bit random number +*********************************************************************************/ +UINT32 HAL_HRNG_GetHrng_32(void); + +/********************************************************************************* +* Function Name : HAL_HRNG_GetHrng +* Description : get random number +* Input : byte_len : the byte length of random number +* Output : *hdata : the start address of random number +* Return : 0: hrng data is ok; 1: hrng data is bad +*********************************************************************************/ +UINT8 HAL_HRNG_GetHrng(UINT8 *hdata, UINT32 byte_len); + +#endif + + + diff --git a/bsp/acm32f4xx-nucleo/libraries/HAL_Driver/Inc/HAL_I2C.h b/bsp/acm32f4xx-nucleo/libraries/HAL_Driver/Inc/HAL_I2C.h new file mode 100644 index 0000000000..d753486fde --- /dev/null +++ b/bsp/acm32f4xx-nucleo/libraries/HAL_Driver/Inc/HAL_I2C.h @@ -0,0 +1,253 @@ +/* + ****************************************************************************** + * @file HAL_I2C.h + * @version V1.0.0 + * @date 2020 + * @brief Header file of I2C HAL module. + ****************************************************************************** +*/ + +#ifndef __HAL_I2C_H__ +#define __HAL_I2C_H__ + +#include "ACM32Fxx_HAL.h" + +/**************** Bit definition for I2C CR register ********************/ +#define I2C_CR_STOPF_INTEN BIT20 +#define I2C_CR_RX_ADDR3_INTEN BIT19 +#define I2C_CR_DMA_EN BIT18 +#define I2C_CR_TXE_SEL BIT17 +#define I2C_CR_MARLO_INTEN BIT16 +#define I2C_CR_TX_AUTO_EN BIT15 +#define I2C_CR_OD_MODE BIT14 +#define I2C_CR_RX_ADDR2_INT_EN BIT12 +#define I2C_CR_OVR_INT_EN BIT11 +#define I2C_CR_RXNE_INT_EN BIT10 +#define I2C_CR_TXE_INT_EN BIT9 +#define I2C_CR_RX_ADDR1_INT_EN BIT8 +#define I2C_CR_MTF_INT_EN BIT7 +#define I2C_CR_TACK BIT6 +#define I2C_CR_STOP BIT5 +#define I2C_CR_START BIT4 +#define I2C_CR_TX BIT3 +#define I2C_CR_MASTER BIT2 +#define I2C_CR_NOSTRETCH BIT1 +#define I2C_CR_MEN BIT0 + +/**************** Bit definition for I2C SR register ********************/ +#define I2C_SR_TIMEOUTBF BIT16 +#define I2C_SR_TIMEOUTAF BIT15 +#define I2C_SR_RX_ADDR3 BIT14 +#define I2C_SR_RX_ADDR2 BIT12 +#define I2C_SR_OVR BIT11 +#define I2C_SR_RXNE BIT10 +#define I2C_SR_TXE BIT9 +#define I2C_SR_RX_ADDR1 BIT8 +#define I2C_SR_MTF BIT7 +#define I2C_SR_MARLO BIT6 +#define I2C_SR_TX_RX_FLAG BIT5 +#define I2C_SR_BUS_BUSY BIT4 +#define I2C_SR_SRW BIT3 +#define I2C_SR_STOPF BIT2 +#define I2C_SR_STARTF BIT1 +#define I2C_SR_RACK BIT0 + +/************** Bit definition for I2C SLAVE ADDR2/3 register **************/ +#define I2C_ADDR3_EN BIT8 +#define I2C_ADDR2_EN BIT0 + +/************** Bit definition for I2C TIMEOUT register **************/ +#define I2C_TIMEOUT_EXTEN BIT31 +#define I2C_TOUTB_INTEN BIT30 +#define I2C_EXT_MODE BIT29 +#define I2C_TIMEOUT_TIMOUTEN BIT15 +#define I2C_TOUTA_INTEN BIT14 + +/** @defgroup I2C_MODE + * @{ + */ +#define I2C_MODE_SLAVE (0U) +#define I2C_MODE_MASTER (1U) +/** + * @} + */ + +/** @defgroup CLOCK_SPEED + * @{ + */ +#define CLOCK_SPEED_STANDARD (100000U) +#define CLOCK_SPEED_FAST (400000U) +#define CLOCK_SPEED_FAST_PLUS (1000000U) +/** + * @} + */ + + +/** @defgroup TX_AUTO_EN + * @{ + */ +#define TX_AUTO_EN_DISABLE (0U) +#define TX_AUTO_EN_ENABLE (1U) +/** + * @} + */ + + +/** @defgroup NO_STRETCH_MODE + * @{ + */ +#define NO_STRETCH_MODE_STRETCH (0U) +#define NO_STRETCH_MODE_NOSTRETCH (1U) +/** + * @} + */ + +/** @defgroup SLAVE State machine + * @{ + */ +#define SLAVE_RX_STATE_IDLE (0U) +#define SLAVE_RX_STATE_RECEIVING (1U) +#define SLAVE_TX_STATE_IDLE (0U) +#define SLAVE_TX_STATE_SENDING (1U) +/** + * @} + */ + + /** @defgroup I2C_Memory_Address_Size I2C Memory Address Size + * @{ + */ +#define I2C_MEMADD_SIZE_8BIT (0U) +#define I2C_MEMADD_SIZE_16BIT (1U) +/** + * @} + */ + + +/* Private macros ------------------------------------------------------------*/ +/** @defgroup I2C_Private_Macros I2C Private Macros + * @{ + */ +#define I2C_MEM_ADD_MSB(__ADDRESS__) ((uint8_t)((uint16_t)(((uint16_t)((__ADDRESS__) & (uint16_t)0xFF00)) >> 8))) +#define I2C_MEM_ADD_LSB(__ADDRESS__) ((uint8_t)((uint16_t)((__ADDRESS__) & (uint16_t)0x00FF))) + +/** + * @brief I2C Configuration Structure definition + */ + +#define __HAL_I2C_GET_FLAG(__HANDLE__, __FLAG__) (((((__HANDLE__)->Instance->SR) & (__FLAG__)) == (__FLAG__) ) ? 1 : 0) + +typedef enum +{ + RESET = 0, + SET = !RESET +} FlagStatus, ITStatus; + +typedef struct +{ + uint32_t I2C_Mode; /* This parameter can be a value of @ref I2C_MODE */ + + uint32_t Tx_Auto_En; /* This parameter can be a value of @ref TX_AUTO_EN */ + + uint32_t No_Stretch_Mode; /* This parameter can be a value of @ref NO_STRETCH_MODE */ + + uint32_t Own_Address; /* This parameter can be a 7-bit address */ + + uint32_t Clock_Speed; /* This parameter can be a value of @ref CLOCK_SPEED */ +} I2C_InitTypeDef; + +/******************************** Check I2C Parameter *******************************/ +#define IS_I2C_ALL_MODE(I2C_MODE) (((I2C_MODE) == I2C_MODE_SLAVE) || \ + ((I2C_MODE) == I2C_MODE_MASTER)) + +#define IS_I2C_CLOCK_SPEED(CLOCK_SPEED) (((CLOCK_SPEED) > 0U) && ((CLOCK_SPEED) <=1000000U)) + +#define IS_I2C_TX_AUTO_EN(TX_AUTO_EN) (((TX_AUTO_EN) == TX_AUTO_EN_DISABLE) || \ + ((TX_AUTO_EN) == TX_AUTO_EN_ENABLE)) + +#define IS_I2C_STRETCH_EN(STRETCH_EN) (((STRETCH_EN) == NO_STRETCH_MODE_STRETCH) || \ + ((STRETCH_EN) == NO_STRETCH_MODE_NOSTRETCH)) + +/** + * @brief I2C handle Structure definition + */ +typedef struct +{ + I2C_TypeDef *Instance; /* I2C registers base address */ + + I2C_InitTypeDef Init; /* I2C communication parameters */ + + uint32_t Slave_RxState; /* I2C Slave state machine */ + uint32_t Slave_TxState; /* I2C Slave state machine */ + + uint8_t *Rx_Buffer; /* I2C Rx Buffer */ + uint8_t *Tx_Buffer; /* I2C Tx Buffer */ + + uint32_t Rx_Size; /* I2C Rx Size */ + uint32_t Tx_Size; /* I2C Tx Size */ + + uint32_t Rx_Count; /* I2C Rx Count */ + uint32_t Tx_Count; /* I2C Tx Count */ + + DMA_HandleTypeDef *HDMA_Rx; /* I2C Rx DMA handle parameters */ + DMA_HandleTypeDef *HDMA_Tx; /* I2C Tx DMA handle parameters */ + + void (*I2C_STOPF_Callback)(void); /* I2C STOP flag interrupt callback */ + +}I2C_HandleTypeDef; + +/******************************** I2C Instances *******************************/ +#define IS_I2C_ALL_INSTANCE(INSTANCE) (((INSTANCE) == I2C1) || ((INSTANCE) == I2C2)) + +/* Function : HAL_I2C_IRQHandler */ +void HAL_I2C_IRQHandler(I2C_HandleTypeDef *hi2c); + +/* Function : HAL_I2C_MspInit */ +void HAL_I2C_MspInit(I2C_HandleTypeDef *hi2c); + +/* Function : HAL_I2C_MspDeInit */ +void HAL_I2C_MspDeInit(I2C_HandleTypeDef *hi2c); + +/* Function : HAL_I2C_Init */ +HAL_StatusTypeDef HAL_I2C_Init(I2C_HandleTypeDef *hi2c); + +/* Function : HAL_I2C_DeInit */ +HAL_StatusTypeDef HAL_I2C_DeInit(I2C_HandleTypeDef *hi2c); + +/* Function : HAL_I2C_Master_Transmit */ +HAL_StatusTypeDef HAL_I2C_Master_Transmit(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint8_t *pData, uint16_t Size, uint32_t Timeout); + +/* Function : HAL_I2C_Master_Receive */ +HAL_StatusTypeDef HAL_I2C_Master_Receive(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint8_t *pData, uint16_t Size, uint32_t Timeout); + +/* Function : HAL_I2C_Slave_Transmit */ +HAL_StatusTypeDef HAL_I2C_Slave_Transmit(I2C_HandleTypeDef *hi2c, uint8_t *pData, uint32_t Size, uint32_t Timeout); + +/* Function : HAL_I2C_Slave_Receive */ +HAL_StatusTypeDef HAL_I2C_Slave_Receive(I2C_HandleTypeDef *hi2c, uint8_t *pData, uint32_t Size, uint32_t Timeout); + +/* Function : HAL_I2C_Slave_Transmit_IT */ +HAL_StatusTypeDef HAL_I2C_Slave_Transmit_IT(I2C_HandleTypeDef *hi2c, uint8_t *pData, uint32_t Size); + + +/* Function : HAL_I2C_Slave_Receive_IT */ +HAL_StatusTypeDef HAL_I2C_Slave_Receive_IT(I2C_HandleTypeDef *hi2c, uint8_t *pData, uint32_t Size); + +/* Function : HAL_I2C_Slave_Receive_DMA */ +HAL_StatusTypeDef HAL_I2C_Slave_Receive_DMA(I2C_HandleTypeDef *hi2c, uint8_t *pData, uint32_t Size); + +/* Function : HAL_I2C_Slave_Transmit_DMA */ +HAL_StatusTypeDef HAL_I2C_Slave_Transmit_DMA(I2C_HandleTypeDef *hi2c, uint8_t *pData, uint32_t Size); + +/* Function : HAL_I2C_Mem_Write */ +HAL_StatusTypeDef HAL_I2C_Mem_Write(I2C_HandleTypeDef *hi2c, uint8_t DevAddress, uint16_t MemAddress, uint16_t MemAddSize, uint8_t *pData, uint16_t Size, uint32_t Timeout); + +/* Function : HAL_I2C_Mem_Read */ +HAL_StatusTypeDef HAL_I2C_Mem_Read(I2C_HandleTypeDef *hi2c, uint8_t DevAddress, uint16_t MemAddress, uint16_t MemAddSize, uint8_t *pData, uint16_t Size, uint32_t Timeout); + +/* Function : HAL_I2C_GetSlaveRxState */ +uint8_t HAL_I2C_GetSlaveRxState(I2C_HandleTypeDef *hi2c); + +/* Function : HAL_I2C_GetSlaveTxState */ +uint8_t HAL_I2C_GetSlaveTxState(I2C_HandleTypeDef *hi2c); + +#endif diff --git a/bsp/acm32f4xx-nucleo/libraries/HAL_Driver/Inc/HAL_I2S.h b/bsp/acm32f4xx-nucleo/libraries/HAL_Driver/Inc/HAL_I2S.h new file mode 100644 index 0000000000..aa7ad5091c --- /dev/null +++ b/bsp/acm32f4xx-nucleo/libraries/HAL_Driver/Inc/HAL_I2S.h @@ -0,0 +1,248 @@ +/* + ****************************************************************************** + * @file HAL_I2S.h + * @version V1.0.0 + * @date 2020 + * @brief Header file of I2S HAL module. + ****************************************************************************** +*/ + +#ifndef __HAL_I2S_H__ +#define __HAL_I2S_H__ + +#include "ACM32Fxx_HAL.h" + +/************************************************************************************/ +/* Registers Bits Definition */ +/************************************************************************************/ + +/**************** Bit definition for I2S CTL Register ***********************/ +#define I2S_CTL_I2SEN (BIT10) +#define I2S_CTL_I2SOPMOD (BIT9|BIT8) +#define I2S_CTL_PCMSMOD (BIT7) +#define I2S_CTL_I2SSTD (BIT5|BIT4) +#define I2S_CTL_CKPL (BIT3) +#define I2S_CTL_DTLEN (BIT2|BIT1) +#define I2S_CTL_CHLEN (BIT0) + +/**************** Bit definition for I2S PSC Register ***********************/ +#define I2S_PSC_MCKOEN (BIT10) +#define I2S_PSC_OF (BIT9) +#define I2S_PSC_DIV (0x1FF) + +/**************** Bit definition for I2S DIE Register ***********************/ +#define I2S_DIE_TBEIE (BIT7) +#define I2S_DIE_RBNEIE (BIT6) +#define I2S_DIE_ERRIE (BIT5) +#define I2S_DIE_DMATEN (BIT1) +#define I2S_DIE_DMAREN (BIT0) + +/**************** Bit definition for I2S STATUS Register ***********************/ +#define I2S_STATUS_FERR (BIT8) +#define I2S_STATUS_TRANS (BIT7) +#define I2S_STATUS_RXORERR (BIT6) +#define I2S_STATUS_TXURERR (BIT3) +#define I2S_STATUS_I2SCH (BIT2) +#define I2S_STATUS_TXBE (BIT1) +#define I2S_STATUS_RXBNE (BIT0) + + + +/** @defgroup I2S_Mode I2S Mode + * @{ + */ +#define I2S_MODE_SLAVE_TX (0x00000000) +#define I2S_MODE_SLAVE_RX (0x00000100) +#define I2S_MODE_MASTER_TX (0x00000200) +#define I2S_MODE_MASTER_RX (I2S_CTL_I2SOPMOD) +/** + * @} + */ + + +/** @defgroup I2S_Standard I2S Standard + * @{ + */ +#define I2S_STANDARD_PHILIPS (0x00000000U) +#define I2S_STANDARD_MSB (0x00000010U) +#define I2S_STANDARD_LSB (0x00000020U) +#define I2S_STANDARD_PCM_SHORT (I2S_CTL_I2SSTD) +#define I2S_STANDARD_PCM_LONG (I2S_CTL_I2SSTD | I2S_CTL_PCMSMOD) +/** + * @} + */ + + +/** @defgroup I2S_Data_Format I2S Data Format + * @{ + */ +#define I2S_DATAFORMAT_16B (0x00000000U) +#define I2S_DATAFORMAT_16B_EXTENDED (I2S_CTL_CHLEN) +#define I2S_DATAFORMAT_24B (I2S_CTL_CHLEN | 0x02) +#define I2S_DATAFORMAT_32B (I2S_CTL_CHLEN | 0x04) +/** + * @} + */ + + +/** @defgroup I2S_MCLK_Output I2S MCLK Output + * @{ + */ +#define I2S_MCLKOUTPUT_ENABLE (I2S_PSC_MCKOEN) +#define I2S_MCLKOUTPUT_DISABLE (0x00000000U) +/** + * @} + */ + + +/** @defgroup I2S_Clock_Polarity I2S Clock Polarity + * @{ + */ +#define I2S_CPOL_LOW (0x00000000U) +#define I2S_CPOL_HIGH (I2S_CTL_CKPL) +/** + * @} + */ + + +/** @defgroup I2S_Audio_FrequencyOF I2S Clock Frequency OF + * @{ + */ +#define I2S_FREQ_OF_DISABLE (0x00000000U) +#define I2S_FREQ_OF_ENABLE (I2S_PSC_OF) +/** + * @} + */ + +/** + * @brief HAL State structures definition + */ +typedef enum +{ + HAL_I2S_STATE_RESET = 0x00U, /*!< I2S not yet initialized or disabled */ + HAL_I2S_STATE_READY = 0x01U, /*!< I2S initialized and ready for use */ + HAL_I2S_STATE_BUSY = 0x02U, /*!< I2S internal process is ongoing */ + HAL_I2S_STATE_BUSY_TX = 0x03U, /*!< Data Transmission process is ongoing */ + HAL_I2S_STATE_BUSY_RX = 0x04U, /*!< Data Reception process is ongoing */ + HAL_I2S_STATE_TIMEOUT = 0x06U, /*!< I2S timeout state */ + HAL_I2S_STATE_ERROR = 0x07U /*!< I2S error state */ +}enum_I2S_State; + + +/** + * @brief I2S Init structure definition + */ +typedef struct +{ + uint32_t u32_Mode; /*!< Specifies the I2S operating mode. + This parameter can be a value of @ref I2S_Mode */ + + uint32_t u32_Standard; /*!< Specifies the standard used for the I2S communication. + This parameter can be a value of @ref I2S_Standard */ + + uint32_t u32_DataFormat; /*!< Specifies the data format for the I2S communication. + This parameter can be a value of @ref I2S_Data_Format */ + + uint32_t u32_MCLKOutput; /*!< Specifies whether the I2S MCLK output is enabled or not. + This parameter can be a value of @ref I2S_MCLK_Output */ + + uint32_t u32_CPOL; /*!< Specifies the idle state of the I2S clock. + This parameter can be a value of @ref I2S_Clock_Polarity */ + + uint32_t u32_FreqOF; /*!< Specifies the frequency selected for the I2S communication. + This parameter can be a value of @ref I2S_Audio_FrequencyFO */ + + uint32_t u32_FreqDIV; /*!< Specifies the frequency selected for the I2S communication. + This parameter must be a number between Min_Data = 0x001 and Max_Data = 0x1FF */ +}I2S_InitTypeDef; + + + +/** + * @brief I2S handle Structure definition + */ +typedef struct +{ + I2S_TypeDef *Instance; /*!< I2S registers base address */ + + I2S_InitTypeDef Init; /*!< I2S communication parameters */ + + enum_I2S_State I2S_Status; + + uint32_t *u32_Rx_Buffer; /* I2S Rx Buffer */ + uint32_t *u32_Tx_Buffer; /* I2S Tx Buffer */ + + uint32_t u32_Rx_Size; /* I2S Rx Size */ + uint32_t u32_Tx_Size; /* I2S Tx Size */ + + uint32_t u32_Rx_Count; /* I2S RX Count */ + uint32_t u32_Tx_Count; /* I2S TX Count */ + + DMA_HandleTypeDef *HDMA_Rx; /* SPI Rx DMA handle parameters */ + DMA_HandleTypeDef *HDMA_Tx; /* SPI Tx DMA handle parameters */ + +}I2S_HandleTypeDef; + + +/** @defgroup RTC Private Macros + * @{ + */ +#define IS_I2S_MODE(__MODE__) (((__MODE__) == I2S_MODE_SLAVE_TX) || \ + ((__MODE__) == I2S_MODE_SLAVE_RX) || \ + ((__MODE__) == I2S_MODE_MASTER_TX) || \ + ((__MODE__) == I2S_MODE_MASTER_RX)) + +#define IS_I2S_STANDARD(__STANDARD__) (((__STANDARD__) == I2S_STANDARD_PHILIPS) || \ + ((__STANDARD__) == I2S_STANDARD_MSB) || \ + ((__STANDARD__) == I2S_STANDARD_LSB) || \ + ((__STANDARD__) == I2S_STANDARD_PCM_SHORT) || \ + ((__STANDARD__) == I2S_STANDARD_PCM_LONG)) + +#define IS_I2S_DATAFORMAT(__DATAFORMAT__) (((__DATAFORMAT__) == I2S_DATAFORMAT_16B) || \ + ((__DATAFORMAT__) == I2S_DATAFORMAT_16B_EXTENDED) || \ + ((__DATAFORMAT__) == I2S_DATAFORMAT_24B) || \ + ((__DATAFORMAT__) == I2S_DATAFORMAT_32B)) + +#define IS_I2S_MCLK_OUTPUT(__MCLK_OUTPUT__) (((__MCLK_OUTPUT__) == I2S_MCLKOUTPUT_ENABLE) || \ + ((__MCLK_OUTPUT__) == I2S_MCLKOUTPUT_DISABLE)) + +#define IS_I2S_MCLK_CPOL(__CPOL__) (((__CPOL__) == I2S_CPOL_LOW) || \ + ((__CPOL__) == I2S_CPOL_HIGH)) + +#define IS_I2S_OF(__OF__) (((__OF__) == I2S_FREQ_OF_DISABLE) || \ + ((__OF__) == I2S_FREQ_OF_ENABLE)) + +#define IS_I2S_DIV(__DIV__) ((__DIV__) >= 0x001 && (__DIV__) <= 0x1FF) +/** + * @} + */ + +/* HAL_I2S_IRQHandler */ +void HAL_I2S_IRQHandler(I2S_HandleTypeDef *hi2s); + +/* HAL_I2S_MspInit */ +void HAL_I2S_MspInit(I2S_HandleTypeDef *hspi); + +/* HAL_I2S_Init */ +HAL_StatusTypeDef HAL_I2S_Init(I2S_HandleTypeDef *hi2s); + +/* HAL_I2S_Transmit */ +HAL_StatusTypeDef HAL_I2S_Transmit(I2S_HandleTypeDef *hi2s, uint32_t *fp32_Data, uint32_t fu32_Size, uint32_t fu32_Timeout); + +/* HAL_I2S_Receive */ +HAL_StatusTypeDef HAL_I2S_Receive(I2S_HandleTypeDef *hi2s, uint32_t *fp32_Data, uint32_t fu32_Size, uint32_t fu32_Timeout); + +/* HAL_I2S_Transmit_IT */ +HAL_StatusTypeDef HAL_I2S_Transmit_IT(I2S_HandleTypeDef *hi2s, uint32_t *fp32_Data, uint32_t fu32_Size); + +/* HAL_I2S_Receive_IT */ +HAL_StatusTypeDef HAL_I2S_Receive_IT(I2S_HandleTypeDef *hi2s, uint32_t *fp32_Data, uint32_t fu32_Size); + +/* HAL_I2S_Transmit_DMA */ +HAL_StatusTypeDef HAL_I2S_Transmit_DMA(I2S_HandleTypeDef *hi2s, uint32_t *fp32_Data, uint32_t fu32_Size); + +/* HAL_I2S_Receive_DMA */ +HAL_StatusTypeDef HAL_I2S_Receive_DMA(I2S_HandleTypeDef *hi2s, uint32_t *fp32_Data, uint32_t fu32_Size); + +#endif + diff --git a/bsp/acm32f4xx-nucleo/libraries/HAL_Driver/Inc/HAL_IWDT.h b/bsp/acm32f4xx-nucleo/libraries/HAL_Driver/Inc/HAL_IWDT.h new file mode 100644 index 0000000000..a7291ed2a2 --- /dev/null +++ b/bsp/acm32f4xx-nucleo/libraries/HAL_Driver/Inc/HAL_IWDT.h @@ -0,0 +1,56 @@ + +/*********************************************************************** + * Filename : HAL_IWDT.h + * Description : IHAL WDT driver header file + * Author(s) : CWT + * version : V1.0 + * Modify date : 2020-04-17 + ***********************************************************************/ + +#ifndef __HAL_IWDT_H__ +#define __HAL_IWDT_H__ + +#include "ACM32Fxx_HAL.h" + + +/**************** Bit definition for IWDT register ***********************/ + + +/*----------------------macro definition------------------------*/ +#define IWDT_ENABLE_COMMAND (0xCCCCU) +#define IWDT_WRITE_ENABLE_COMMAND (0x5555U) +#define IWDT_WAKEUP_ENABLE_COMMAND (0x6666U) +#define IWDT_WAKEUP_DISABLE_COMMAND (0x9999U) +#define IWDT_RELOAD_COMMAND (0xAAAAU) + +#define IWDT_RELOAD_MAX_VALUE (0x0FFFU) + +/*----------------------type definition------------------------*/ +typedef enum _IWDT_CLOCK_PRESCALER{ + IWDT_CLOCK_PRESCALER_4 = 0, + IWDT_CLOCK_PRESCALER_8 = 1, + IWDT_CLOCK_PRESCALER_16 = 2, + IWDT_CLOCK_PRESCALER_32 = 3, + IWDT_CLOCK_PRESCALER_64 = 4, + IWDT_CLOCK_PRESCALER_128 = 5, + IWDT_CLOCK_PRESCALER_256 = 6, +}IWDT_CLOCK_PRESCALER; + +typedef struct +{ + uint32_t Prescaler; + uint32_t Reload; + uint32_t Window; + uint32_t Wakeup; +} IWDT_InitTypeDef; + +typedef struct +{ + IWDT_TypeDef *Instance; /*!< Register base address */ + IWDT_InitTypeDef Init; /*!< IWDT required parameters */ +} IWDT_HandleTypeDef; + + + HAL_StatusTypeDef HAL_IWDT_Init(IWDT_HandleTypeDef * hidt); + HAL_StatusTypeDef HAL_IWDT_Kick_Watchdog_Wait_For_Done(IWDT_HandleTypeDef * hidt); +#endif diff --git a/bsp/acm32f4xx-nucleo/libraries/HAL_Driver/Inc/HAL_LPUART.h b/bsp/acm32f4xx-nucleo/libraries/HAL_Driver/Inc/HAL_LPUART.h new file mode 100644 index 0000000000..a30bbd03a9 --- /dev/null +++ b/bsp/acm32f4xx-nucleo/libraries/HAL_Driver/Inc/HAL_LPUART.h @@ -0,0 +1,173 @@ +/* + ****************************************************************************** + * @file HAL_LPUART.h + * @version V1.0.0 + * @date 2020 + * @brief Header file of CAN HAL module. + ****************************************************************************** +*/ +#ifndef __HAL_LPUART_H__ +#define __HAL_LPUART_H__ + +#include "ACM32Fxx_HAL.h" + + +#define IS_LPUART_INSTANCE(INSTANCE) ((INSTANCE) == LPUART) + +#define LPUART_PEN_INDEX 0 +#define LPUART_SPS_INDEX 1 +#define LPUART_EPS_INDEX 2 + +#define LPUART_IE_RX_INDEX 0 //has wakeup function +#define LPUART_IE_TX_FINISH_INDEX 1 +#define LPUART_IE_TX_EMPTY_INDEX 2 + +#define LPUART_SR_RX_INDEX 0 +#define LPUART_SR_TX_FINISH_INDEX 1 +#define LPUART_SR_TX_EMPTY_INDEX 2 +#define LPUART_SR_RX_FULL_INDEX 6 +#define LPUART_SR_MATCH_INDEX 8 //has wakeup function +#define LPUART_SR_START_INDEX 9 //has wakeup function +#define LPUART_SR_BITS_ALL 0x1FFU + +#define LPUART_WAKEUP_RX_BIT BIT0 +#define LPUART_WAKEUP_MATCH_BIT BIT8 +#define LPUART_WAKEUP_START_BIT BIT9 + +#define LPUART_CR_RXE_INDEX 0 +#define LPUART_CR_TXE_INDEX 1 +#define LPUART_CR_DMA_EN_INDEX 2 + +/** @defgroup GPIO Private Macros + * @{ + */ +typedef enum +{ + LPUART_RXWKS_START = 0x00, + LPUART_RXWKS_OneByte = 0x01, + LPUART_RXWKS_DataCompare = 0x02, + LPUART_RXWKS_NoWake = 0x03, +} LPUART_RXWKS; + +typedef enum +{ + LPUART_WKCK_Check = 0x00, + LPUART_WKCK_NoCheck = 0x01, +} LPUART_WKCK ; + +/** + * @} + */ + + + +/* + * @brief LPUART DATABITS definition + */ +typedef enum +{ + LPUART_DATABITS_8 = 0x00, + LPUART_DATABITS_7 = 0x01, +} LPUART_DATABITS; + +/* + * @brief LPUART STOPBITS definition + */ +typedef enum +{ + LPUART_STOPBITS_ONE = 0x00U, + LPUART_STOPBITS_TWO = 0x01U, +}LPUART_STOPBITS; + +/* + * @brief LPUART CLOCK_SOURCE definition + */ +typedef enum +{ + LPUART_CLOCK_SOURCE_RC32K = 0x00U, + LPUART_CLOCK_SOURCE_XTAL = 0x01U, + LPUART_CLOCK_SOURCE_PLL_DIV = 0x02U, +}LPUART_CLOCK_SOURCE; + +/* + * @brief LPUART PARITY definition + */ +typedef enum +{ + LPUART_PARITY_NONE = 0x00U, + LPUART_PARITY_SELECT_ODD = 0x01U, + LPUART_PARITY_SELECT_EVEN = 0x02U, + LPUART_PARITY_SELECT_ONE = 0x03U, + LPUART_PARITY_SELECT_ZERO = 0x04U, +}LPUART_PARITY_SELECT; + +/** + * @brief LPUART Config structure definition + */ +typedef struct +{ + uint8_t WordLength; // LPUART_DATABITS + uint8_t StopBits; // LPUART_STOPBITS + uint8_t Parity; // LPUART_PARITY_SELECT + uint8_t ClockSrc; // LPUART_CLOCK_SOURCE + uint32_t BaudRate; +}LPUART_ConfigParam; + +/** + * @brief LPUART Config structure definition + */ +typedef struct +{ + uint8_t Wakeup_Source; // Wakeup_Source + uint8_t Wakeup_Check; // Wakeup_Check + uint8_t Wakeup_Addr; // Wakeup_Addr + +}LPUART_StopWakeupDef; + + + +/** + * @brief LPUART init structure definition + */ +typedef struct +{ + LPUART_TypeDef *Instance; + LPUART_ConfigParam ConfigParam; + LPUART_StopWakeupDef StopWakeup; + volatile uint8_t *rx_buffer; + volatile uint16_t rx_buffer_size; + volatile uint16_t rx_write_index; + volatile uint16_t rx_read_index; + volatile uint16_t tx_busy; + DMA_HandleTypeDef *dma_rx_handler; + DMA_HandleTypeDef *dma_tx_handler; +}LPUART_HandleTypeDef; + +/* HAL_LPUART_Init */ +HAL_StatusTypeDef HAL_LPUART_Init(LPUART_HandleTypeDef *hlpuart); + +HAL_StatusTypeDef HAL_LPUART_DeInit(LPUART_HandleTypeDef *hlpuart); + +void HAL_LPUART_MSPInit(LPUART_HandleTypeDef *hlpuart); + +void HAL_LPUART_MspDeInit(LPUART_HandleTypeDef *hlpuart); + +/* HAL_LPUART_Send_Bytes */ +void HAL_LPUART_Send_Bytes(LPUART_HandleTypeDef *hlpuart, uint8_t *buff, uint32_t length); + +/* HAL_LPUART_IRQHander */ +void HAL_LPUART_IRQHander(LPUART_HandleTypeDef *hlpuart); + +/* HAL_LPUART_Receive_Bytes_Timeout */ +uint32_t HAL_LPUART_Receive_Bytes_Timeout(LPUART_HandleTypeDef *hlpuart, uint8_t * rxbuff, uint32_t length, uint32_t ms); + +/* HAL_LPUART_Receive_Bytes */ +uint32_t HAL_LPUART_Receive_Bytes(LPUART_HandleTypeDef *hlpuart, uint8_t * rxbuff, uint32_t length); + +/* HAL_LPUART_DMA_Send_Bytes */ +void HAL_LPUART_DMA_Send_Bytes(LPUART_HandleTypeDef *hlpuart, uint8_t *buff, uint32_t length); + +/* HAL_LPUART_Clear_Wakeup_Flags */ +void HAL_LPUART_Clear_Wakeup_Flags(LPUART_HandleTypeDef *hlpuart, uint32_t Wakeup_Bits); + +#endif \ No newline at end of file diff --git a/bsp/acm32f4xx-nucleo/libraries/HAL_Driver/Inc/HAL_OPA.h b/bsp/acm32f4xx-nucleo/libraries/HAL_Driver/Inc/HAL_OPA.h new file mode 100644 index 0000000000..2026f33bae --- /dev/null +++ b/bsp/acm32f4xx-nucleo/libraries/HAL_Driver/Inc/HAL_OPA.h @@ -0,0 +1,187 @@ +/* + ****************************************************************************** + * @file HAL_OPA.h + * @version V1.0.0 + * @date 2020 + * @brief Header file of OPA HAL module. + ****************************************************************************** +*/ +#ifndef __HAL_OPA_H__ +#define __HAL_OPA_H__ + +#include "ACM32Fxx_HAL.h" + +/**************** Bit definition for OPA_CR1 and OPA_CR2 register **************************/ +#define OPA_CSR_LOCK (BIT31) +#define OPA_CSR_HSM (BIT28) +#define OPA_CSR_GAIN_SEL_POS (23U) +#define OPA_CSR_GAIN_SEL_MASK (BIT27|BIT26|BIT25|BIT24|BIT23) +#define OPA_CSR_POL_SEL_POS (21U) +#define OPA_CSR_POL_SEL_MASK (BIT22|BIT21) +#define OPA_CSR_VINM0_SEL_POS (BIT20) +#define OPA_CSR_MODE_SEL_POS (18U) +#define OPA_CSR_MODE_SEL_MASK (BIT19|BIT18) +#define OPA_CSR_VINP_SEL_POS (16U) +#define OPA_CSR_VINP_SEL_MASK (BIT17|BIT16) +#define OPA_CSR_OUT_SEL_POS (14U) +#define OPA_CSR_OUT_SEL_MASK (BIT14|BIT15) +#define OPA_CSR_TRIM_OSN_POS (9U) +#define OPA_CSR_TRIM_OSN_MASK (BIT13|BIT12|BIT11|BIT10|BIT9) +#define OPA_CSR_TRIM_OSP_POS (4U) +#define OPA_CSR_TRIM_OSP_MASK (BIT8|BIT7|BIT6|BIT5|BIT4) +#define OPA_CSR_CAL_OUT (BIT3) +#define OPA_CSR_CAL_NEN (BIT2) +#define OPA_CSR_CAL_PEN (BIT1) +#define OPA_CSR_EN (BIT0) + +/** @defgroup OPAx Index + * @{ + */ +#define OPA1 (0x01) +#define OPA2 (0x02) +#define OPA3 (0x03) + +/** @defgroup HSM driver mode + * @{ + */ +#define OPA_HSM_LOW (0u) +#define OPA_HSM_HIGH (1u) + +/** @defgroup OPA Gain select. + * @{ + */ +#define OPA_GAIN_64_63 (0u) +#define OPA_GAIN_32_31 (1u) +#define OPA_GAIN_16_15 (2u) +#define OPA_GAIN_8_7 (4u) +#define OPA_GAIN_4_3 (8u) +#define OPA_GAIN_2_1 (16u) + +/** @defgroup Polarity select. + * @{ + */ +#define OPA_POL_NONINVERT (0u) +#define OPA_POL_INVERT (1u) + +/** @defgroup OPA work mode select. + * @{ + */ +#define OPA_MODE_SA (0u) +#define OPA_MODE_UG (1u) +#define OPA_MODE_PGA (2u) +#define OPA_MODE_SA1 (3u) + +/** @defgroup OPA VINP vin p select. + * @{ + */ +#define OPA_VINP_0 (0u) +#define OPA_VINP_1 (1u) +#define OPA_VINP_2 (2u) +#define OPA_VINP_3 (3u) + +/** @defgroup OPA output select. + * @{ + */ +#define OPA_OUT_GPIO (0u) +#define OPA_OUT_INTERNAL (1u) + +/** @defgroup OPA VINM0 enable. + * @{ + */ +#define OPA_CSR_VINM0_DISABLE (0U) +#define OPA_CSR_VINM0_ENABLE (1U) + +/** @defgroup OPA trim enable. + * @{ + */ +#define OPA_CSR_TRIM_DISABLE (0U) +#define OPA_CSR_TRIM_ENABLE (1U) + +/** + * @brief OPA Configuration Structure definition + */ +typedef struct +{ + uint8_t OpaX; /*!< Specify witch opa be selected */ + uint8_t Hsm; /*!< Specify the opa HSM driver mode:OPA_HSM_LOW or OPA_HSM_HIGH */ + uint8_t Gain; /*!< Specify the opa gain select */ + uint8_t PolSel; /*!< Specify the opa Polarity select */ + uint8_t VinM0En; /*!< Specify the opa VinM0 enable */ + uint8_t OpaMode; /*!< Specify the opa work mode select */ + uint8_t VinPSel; /*!< Specify the opa VINP vin p select */ + uint8_t OutSel; /*!< Specify the opa output select */ + uint8_t TrimEn; /*!< Specify if the opa auto trim */ +}OPA_InitTypeDef; + +/** + * @brief OPA handle Structure definition + */ +typedef struct +{ + OPA_TypeDef *Instance; /*!< Register base address */ + OPA_InitTypeDef Init; /*!< OPA required parameters */ +} OPA_HandleTypeDef; + +/******************************** OPA Instances *******************************/ +#define IS_OPA_ALL_INSTANCE(INSTANCE) (((INSTANCE) == OPA)) + +/******************************** OPA OPAX definition*******************************/ +#define IS_OPA_ALL_OPAX(_OPAX) (((_OPAX) == OPA1) || \ + ((_OPAX) == OPA2) || \ + ((_OPAX) == OPA3)) + +/******************************** OPA HSM definition*******************************/ +#define IS_OPA_ALL_HSM(_HSM) (((_HSM) == OPA_HSM_LOW) || \ + ((_HSM) == OPA_HSM_HIGH)) + +/******************************** OPA GAIN definition*******************************/ +#define IS_OPA_ALL_GAIN(_GAIN) (((_GAIN) == OPA_GAIN_64_63) || \ + ((_GAIN) == OPA_GAIN_32_31) || \ + ((_GAIN) == OPA_GAIN_16_15) || \ + ((_GAIN) == OPA_GAIN_8_7) || \ + ((_GAIN) == OPA_GAIN_4_3) || \ + ((_GAIN) == OPA_GAIN_2_1)) + +/******************************** OPA Polarity definition*******************************/ +#define IS_OPA_ALL_POL(_POL) (((_POL) == OPA_POL_NONINVERT) || \ + ((_POL) == OPA_POL_INVERT)) + +/******************************** OPA work mode definition*******************************/ +#define IS_OPA_ALL_MODE(_MODE) (((_MODE) == OPA_MODE_SA) || \ + ((_MODE) == OPA_MODE_UG) || \ + ((_MODE) == OPA_MODE_PGA) || \ + ((_MODE) == OPA_MODE_SA1)) + +/******************************** OPA VINP select definition*******************************/ +#define IS_OPA_ALL_VINP(_VINP) (((_VINP) == OPA_VINP_0) || \ + ((_VINP) == OPA_VINP_1) || \ + ((_VINP) == OPA_VINP_2) || \ + ((_VINP) == OPA_VINP_3)) + +/******************************** OPA OUT select definition*******************************/ +#define IS_OPA_ALL_OUT(_OUT) (((_OUT) == OPA_OUT_GPIO) || \ + ((_OUT) == OPA_OUT_INTERNAL)) + +/******************************** OPA VINM0 enable definition*******************************/ +#define IS_OPA_ALL_VINM0(_VINM0) (((_VINM0) == OPA_CSR_VINM0_DISABLE) || \ + ((_VINM0) == OPA_CSR_VINM0_ENABLE)) + +/******************************** OPA trim enable definition*******************************/ +#define IS_OPA_ALL_TRIM(_TRIM) (((_TRIM) == OPA_CSR_TRIM_DISABLE) || \ + ((_TRIM) == OPA_CSR_TRIM_ENABLE)) + +/* Function : HAL_OPA */ +void HAL_OPA_MspInit(OPA_HandleTypeDef* hopa); +void HAL_OPA_MspDeInit(OPA_HandleTypeDef* hopa); +HAL_StatusTypeDef HAL_OPA_Init(OPA_HandleTypeDef* hopa); +HAL_StatusTypeDef HAL_OPA_DeInit(OPA_HandleTypeDef* hopa); +HAL_StatusTypeDef HAL_OPA_Enable(OPA_HandleTypeDef* hopa); +HAL_StatusTypeDef HAL_OPA_Disable(OPA_HandleTypeDef* hopa); +HAL_StatusTypeDef HAL_OPA_Lock(OPA_HandleTypeDef* hopa); + +#endif + + + + + diff --git a/bsp/acm32f4xx-nucleo/libraries/HAL_Driver/Inc/HAL_RTC.h b/bsp/acm32f4xx-nucleo/libraries/HAL_Driver/Inc/HAL_RTC.h new file mode 100644 index 0000000000..8cc7f50a2b --- /dev/null +++ b/bsp/acm32f4xx-nucleo/libraries/HAL_Driver/Inc/HAL_RTC.h @@ -0,0 +1,685 @@ +/* + ****************************************************************************** + * @file HAL_RTC.h + * @version V1.0.0 + * @date 2020 + * @brief Header file of RTC HAL module. + ****************************************************************************** +*/ + +#ifndef __HAL_RTC_H__ +#define __HAL_RTC_H__ + +#include "ACM32Fxx_HAL.h" + +/************************************************************************************/ +/* Registers Bits Definition */ +/************************************************************************************/ + +/**************** Bit definition for RTC IE Register ***********************/ +#define RTC_IE_STP2RIE (BIT16) +#define RTC_IE_STP2FIE (BIT15) +#define RTC_IE_STP1RIE (BIT14) +#define RTC_IE_STP1FIE (BIT13) +#define RTC_IE_ADJ32 (BIT12) +#define RTC_IE_ALM (BIT11) +#define RTC_IE_1KHZ (BIT10) +#define RTC_IE_256HZ (BIT9) +#define RTC_IE_64HZ (BIT8) +#define RTC_IE_16HZ (BIT7) +#define RTC_IE_8HZ (BIT6) +#define RTC_IE_4HZ (BIT5) +#define RTC_IE_2HZ (BIT4) +#define RTC_IE_SEC (BIT3) +#define RTC_IE_MIN (BIT2) +#define RTC_IE_HOUR (BIT1) +#define RTC_IE_DATE (BIT0) + +/**************** Bit definition for RTC SR Register ***********************/ +#define RTC_SR_STP2RIE (BIT16) +#define RTC_SR_STP2FIE (BIT15) +#define RTC_SR_STP1RIE (BIT14) +#define RTC_SR_STP1FIE (BIT13) +#define RTC_SR_ADJ32 (BIT12) +#define RTC_SR_ALM (BIT11) +#define RTC_SR_1KHZ (BIT10) +#define RTC_SR_256HZ (BIT9) +#define RTC_SR_64HZ (BIT8) +#define RTC_SR_16HZ (BIT7) +#define RTC_SR_8HZ (BIT6) +#define RTC_SR_4HZ (BIT5) +#define RTC_SR_2HZ (BIT4) +#define RTC_SR_SEC (BIT3) +#define RTC_SR_MIN (BIT2) +#define RTC_SR_HOUR (BIT1) +#define RTC_SR_DATE (BIT0) + +/**************** Bit definition for RTC CR Register ***********************/ +#define RTC_CR_TAMPFLTCLK (BIT22) +#define RTC_CR_TS2EDGE (BIT21) +#define RTC_CR_TAMP2FLT (BIT19|BIT20) +#define RTC_CR_TAMP2FLTEN (BIT18) +#define RTC_CR_TAMP2FCLR (BIT17) +#define RTC_CR_TAMP2RCLR (BIT16) +#define RTC_CR_TS1EDGE (BIT15) +#define RTC_CR_TAMP1FLT (BIT13|BIT14) +#define RTC_CR_TAMP1FLTEN (BIT12) +#define RTC_CR_ALM_MKSD (BIT11) +#define RTC_CR_ALM_MSKH (BIT10) +#define RTC_CR_ALM_MSKM (BIT9) +#define RTC_CR_TAMP1FCLR (BIT8) +#define RTC_CR_TAMP1RCLR (BIT7) +#define RTC_CR_TAMP2EN (BIT6) +#define RTC_CR_TAMP1EN (BIT5) +#define RTC_CR_ALM_EN (BIT4) +#define RTC_CR_FSEL (BIT0|BIT1|BIT2|BIT3) + +/**************** Bit definition for RTC_PMU CR Register ***********************/ +#define RPMU_CR_WU6FILEN BIT29 +#define RPMU_CR_WU5FILEN BIT28 +#define RPMU_CR_WU4FILEN BIT27 +#define RPMU_CR_WU3FILEN BIT26 +#define RPMU_CR_WU2FILEN BIT25 +#define RPMU_CR_WU1FILEN BIT24 +#define RPMU_CR_EWUP6 BIT21 +#define RPMU_CR_EWUP5 BIT20 +#define RPMU_CR_EWUP4 BIT19 +#define RPMU_CR_EWUP3 BIT18 +#define RPMU_CR_EWUP2 BIT17 +#define RPMU_CR_EWUP1 BIT16 +#define RPMU_CR_BORRST_EN BIT12 +#define RPMU_CR_WK_TIME (BIT9|BIT10|BIT11) +#define RPMU_CR_STB_EN BIT8 +#define RPMU_CR_BDRST BIT6 +#define RPMU_CR_RTCEN BIT5 +#define RPMU_CR_RTCSEL (BIT2|BIT3) +#define RPMU_CR_CWUF BIT1 +#define RPMU_CR_CSBF BIT0 + +/**************** Bit definition for RTC_PMU ANACR Register ***********************/ +#define RPMU_SR_BORWUF BIT13 +#define RPMU_SR_IWDTWUF BIT12 +#define RPMU_SR_RSTWUF BIT11 +#define RPMU_SR_RTCWUF BIT10 +#define RPMU_SR_WUP6F BIT6 +#define RPMU_SR_WUP5F BIT5 +#define RPMU_SR_WUP4F BIT4 +#define RPMU_SR_WUP3F BIT3 +#define RPMU_SR_WUP2F BIT2 +#define RPMU_SR_WUP1F BIT1 +#define RPMU_SR_SBF BIT0 + +/**************** Bit definition for RTC_PMU ANACR Register ***********************/ +#define RPMU_ANACR_BOR_CFG (BIT24|BIT25) +#define RPMU_ANACR_BOR_EN BIT23 +#define RPMU_ANACR_LPBGR_TRIM (BIT20|BIT21|BIT22) +#define RPMU_ANACR_RC32K_TRIM (BIT10|BIT11|BIT12|BIT13|BIT14|BIT15) +#define RPMU_ANACR_RC32K_RDY BIT9 +#define RPMU_ANACR_RC32K_EN BIT8 +#define RPMU_ANACR_XTLDRV_2 BIT5 +#define RPMU_ANACR_XTLDRV_1 BIT4 +#define RPMU_ANACR_XTLDRV_0 BIT3 +#define RPMU_ANACR_XTLDRV (BIT3|BIT4|BIT5) +#define RPMU_ANACR_XTLBYO BIT2 +#define RPMU_ANACR_XTLRDY BIT1 +#define RPMU_ANACR_XTLEN BIT0 + + +/** @defgroup ClockSource + * @{ + */ +#define RTC_CLOCK_RC32K (0x00000000) +#define RTC_CLOCK_XTL (0x00000004) +/** + * @} + */ + + +/** @defgroup Clock_Compensation + * @{ + */ +#define COMPENSATION_INCREASE (0x00000000) +#define COMPENSATION_DECREASE (0x00000400) +/** + * @} + */ + + +/** @defgroup RTC_Month_Date_Definitions RTC Month Date Definitions + * @{ + */ + +/* Coded in BCD format */ +#define RTC_MONTH_JANUARY (0x01) +#define RTC_MONTH_FEBRUARY (0x02) +#define RTC_MONTH_MARCH (0x03) +#define RTC_MONTH_APRIL (0x04) +#define RTC_MONTH_MAY (0x05) +#define RTC_MONTH_JUNE (0x06) +#define RTC_MONTH_JULY (0x07) +#define RTC_MONTH_AUGUST (0x08) +#define RTC_MONTH_SEPTEMBER (0x09) +#define RTC_MONTH_OCTOBER (0x10) +#define RTC_MONTH_NOVEMBER (0x11) +#define RTC_MONTH_DECEMBER (0x12) +/** + * @} + */ + + +/** @defgroup RTC_WeekDay_Definitions RTC WeekDay Definitions + * @{ + */ +#define RTC_WEEKDAY_MONDAY (0x01) +#define RTC_WEEKDAY_TUESDAY (0x02) +#define RTC_WEEKDAY_WEDNESDAY (0x03) +#define RTC_WEEKDAY_THURSDAY (0x04) +#define RTC_WEEKDAY_FRIDAY (0x05) +#define RTC_WEEKDAY_SATURDAY (0x06) +#define RTC_WEEKDAY_SUNDAY (0x07) +/** + * @} + */ + + +/** @defgroup RTC_Alarm_Mode Definitions + * @{ + */ +#define RTC_ALARM_WEEK_MODE (0x00000000) +#define RTC_ALARM_DAY_MODE (0x80000000) +/** + * @} + */ + + +/** @defgroup RTC_AlarmInterrupt Definitions + * @{ + */ +#define RTC_ALARM_INT_ENABLE (0x00000000) +#define RTC_ALARM_INT_DISABLE (0x00000001) +/** + * @} + */ + + +/** @defgroup RTC_DayMask Definitions + * @{ + */ +#define RTC_ALARM_DAY_MASK_ENABLE RTC_CR_ALM_MKSD +#define RTC_ALARM_DAY_MASK_DISABLE (0x00000000) +/** + * @} + */ + + +/** @defgroup RTC_HourMask Definitions + * @{ + */ +#define RTC_ALARM_HOUR_MASK_ENABLE RTC_CR_ALM_MSKH +#define RTC_ALARM_HOUR_MASK_DISABLE (0x00000000) +/** + * @} + */ + + +/** @defgroup RTC_MinMask Definitions + * @{ + */ +#define RTC_ALARM_MIN_MASK_ENABLE RTC_CR_ALM_MSKM +#define RTC_ALARM_MIN_MASK_DISABLE (0x00000000) +/** + * @} + */ + + +/** @defgroup RTC_Alarm_WeekSelect Definitions + * @{ + */ +#define RTC_ALARM_WEEK_SUNDAY (0x01000000) +#define RTC_ALARM_WEEK_MONDAY (0x02000000) +#define RTC_ALARM_WEEK_TUESDAY (0x04000000) +#define RTC_ALARM_WEEK_WEDNESDAY (0x08000000) +#define RTC_ALARM_WEEK_THURSDAY (0x10000000) +#define RTC_ALARM_WEEK_FRIDAY (0x20000000) +#define RTC_ALARM_WEEK_SATURDAY (0x40000000) +/** + * @} + */ + + +/** @defgroup RTC_Temper_edge Definitions + * @{ + */ +#define RTC_TEMP_EDGE_RISING (0x00000000) +#define RTC_TEMP_EDGE_FALLING (0x00000001) +/** + * @} + */ + + +/** @defgroup RTC_TemperInterrupt Definitions + * @{ + */ +#define RTC_TEMP_INT_DISABLE (0x00000000) +#define RTC_TEMP_INT_ENABLE (0x00000001) +/** + * @} + */ + + +/** @defgroup RTC_ClearBackup Definitions + * @{ + */ +#define RTC_TEMP_CLEAR_DISABLE (0x00000000) +#define RTC_TEMP_CLEAR_ENABLE (0x00000001) +/** + * @} + */ + + +/** @defgroup RTC_TemperFilter Definitions + * @{ + */ +#define RTC_TEMP_FILTER_DISABLE (0x00000000) +#define RTC_TEMP_FILTER_512_RTCCLK (0x00000001) +#define RTC_TEMP_FILTER_1_RTCCLK (0x00000002) +#define RTC_TEMP_FILTER_2_RTCCLK (0x00000003) +#define RTC_TEMP_FILTER_4_RTCCLK (0x00000004) +#define RTC_TEMP_FILTER_8_RTCCLK (0x00000005) +/** + * @} + */ + + +/** + * @brief RTC Temper index definition + */ +typedef enum +{ + RTC_TEMPER_1, + RTC_TEMPER_2, +}enum_Temper_t; +/** + * @} + */ + + +/** + * @brief RTC wakeup source form standby + */ +typedef enum +{ + RTC_WAKEUP_RTC_INT = 0, + RTC_WAKEUP_WKUP1 = 0x00010000, // PA0 + RTC_WAKEUP_WKUP2 = 0x00020000, // PC13 + RTC_WAKEUP_WKUP3 = 0x00040000, // PA2 + RTC_WAKEUP_WKUP4 = 0x00080000, // PC5 + RTC_WAKEUP_WKUP5 = 0x00100000, // PB5 + RTC_WAKEUP_WKUP6 = 0x00200000, // PB15 + RTC_WAKEUP_STAMP2 = (RTC_IE_STP2RIE | RTC_IE_STP2FIE), + RTC_WAKEUP_STAMP1 = (RTC_IE_STP1RIE | RTC_IE_STP1FIE), + RTC_WAKEUP_32S = RTC_IE_ADJ32, + RTC_WAKEUP_ALARM = RTC_IE_ALM, + RTC_WAKEUP_SEC = RTC_IE_SEC, + RTC_WAKEUP_MIN = RTC_IE_MIN, + RTC_WAKEUP_HOUR = RTC_IE_HOUR, + RTC_WAKEUP_DATE = RTC_IE_DATE, +}enum_WKUP_t; + +#define STANDBY_WAKEUP_RISING 0 +#define STANDBY_WAKEUP_FALLING 1 + +/** + * @} + */ + +/** + * @brief Check RTC wakeup source form standby + */ +#define RTC_WAKEUP_SOURCE_BORWUF (0x00002000) +#define RTC_WAKEUP_SOURCE_IWDTWUF (0x00001000) +#define RTC_WAKEUP_SOURCE_RSTWUF (0x00000800) +#define RTC_WAKEUP_SOURCE_RTCWUF (0x00000400) +#define RTC_WAKEUP_SOURCE_WKUP6 (0x00000040) +#define RTC_WAKEUP_SOURCE_WKUP5 (0x00000020) +#define RTC_WAKEUP_SOURCE_WKUP4 (0x00000010) +#define RTC_WAKEUP_SOURCE_WKUP3 (0x00000008) +#define RTC_WAKEUP_SOURCE_WKUP2 (0x00000004) +#define RTC_WAKEUP_SOURCE_WKUP1 (0x00000002) +/** + * @} + */ + +/** + * @brief RTC Configuration Structure definition + */ +typedef struct +{ + uint32_t u32_ClockSource; /*!< The RTC Clock Source to be configured. + This parameter can be a value of @ref ClockSource */ + + uint32_t u32_Compensation; /*!< The RTC Clock Compensation to be configured. + This parameter can be a value of @ref Clock_Compensation */ + + uint32_t u32_CompensationValue; /*!< The RTC Clock Compensation Value to be configured. + This parameter must be a number between Min_Data = 0x000 and Max_Data = 0x1FF */ +}RTC_ConfigTypeDef; + + +/** + * @brief RTC Date structure definition + */ +typedef struct +{ + uint8_t u8_Year; /*!< Specifies the RTC Date Year. + This parameter must be a number between Min_Data = 0x00 and Max_Data = 0x99 */ + + uint8_t u8_Month; /*!< Specifies the RTC Date Month (in BCD format). + This parameter can be a value of @ref RTC_Month_Date_Definitions */ + + uint8_t u8_Date; /*!< Specifies the RTC Date. + This parameter must be a number between Min_Data = 0x01 and Max_Data = 0x31 */ + + uint8_t u8_WeekDay; /*!< Specifies the RTC Date WeekDay. + This parameter can be a value of @ref RTC_WeekDay_Definitions */ +}RTC_DateTypeDef; +/* Attention: YearMonthDateWeek use BCD code */ + + +/** + * @brief RTC Time structure definition + */ +typedef struct +{ + uint8_t u8_Hours; /*!< Specifies the RTC Time Hour. + This parameter must be a number between Min_Data = 0x00 and Max_Data = 0x23 */ + + uint8_t u8_Minutes; /*!< Specifies the RTC Time Minutes. + This parameter must be a number between Min_Data = 0x00 and Max_Data = 0x59 */ + + uint8_t u8_Seconds; /*!< Specifies the RTC Time Seconds. + This parameter must be a number between Min_Data = 0x00 and Max_Data = 0x59 */ +}RTC_TimeTypeDef; +/* Attention: HourMinuteSecond use BCD code */ + + +/** + * @brief RTC Time structure definition + */ +typedef struct +{ + uint32_t u32_AlarmMode; /*!< Specifies the RTC alarm Mode. + This parameter can be a value of @ref RTC_Alarm_Mode */ + + uint32_t u32_AlarmInterrupt; /*!< Specifies the RTC alarm interrupt Enable or Disable. + This parameter can be a value of @ref RTC_AlarmInterrupt */ + + uint32_t u32_DayMask; /*!< Specifies the RTC alarm Day/Week Mask. + This parameter can be a value of @ref RTC_DayMask */ + + uint32_t u32_HourMask; /*!< Specifies the RTC alarm Hour Mask. + This parameter can be a value of @ref RTC_HourMask */ + + uint32_t u32_MinMask; /*!< Specifies the RTC alarm Min Mask. + This parameter can be a value of @ref RTC_MinMask */ + + uint32_t u32_AlarmWeek; /*!< Specifies the RTC alarm week select(Select WeekMode this parameter is valid). + This parameter can be a value of @ref RTC_Alarm_WeekSelect */ + + uint32_t u32_AlarmDay; /*!< Specifies the RTC alarm day select(Select DayMode this parameter is valid). + This parameter must be a number between Min_Data = 0x01 and Max_Data = 0x31 */ + + uint32_t u32_Hours; /*!< Specifies the RTC alarm Hour. + This parameter must be a number between Min_Data = 0x00 and Max_Data = 0x23 */ + + uint32_t u32_Minutes; /*!< Specifies the RTC alarm Minutes. + This parameter must be a number between Min_Data = 0x00 and Max_Data = 0x59 */ + + uint32_t u32_Seconds; /*!< Specifies the RTC alarm Seconds. + This parameter must be a number between Min_Data = 0x00 and Max_Data = 0x59 */ +}RTC_AlarmTypeDef; + + +/** + * @brief RTC Temper structure definition + */ +typedef struct +{ + uint32_t u32_TemperEdge; /*!< Specifies the RTC Temper edge select. + This parameter can be a value of @ref RTC_Temper_edge */ + + uint32_t u32_InterruptEN; /*!< Specifies the RTC Temper interrupt enable. + This parameter can be a value of @ref RTC_TemperInterrupt */ + + uint32_t u32_ClearBackup; /*!< Specifies the RTC Temper clear backup register. + This parameter can be a value of @ref RTC_ClearBackup */ + + uint32_t u32_Filter; /*!< Specifies the RTC Temper Filter select. + This parameter can be a value of @ref RTC_TemperFilter */ +}RTC_TemperTypeDef; + + +/** @brief PC13 function select + * @param __FUNC__: PC13 function select. + * This parameter can be 0: GPIO1RTC Fout2RTC tamper 3PC13 Value + */ +#define __HAL_RTC_PC13_SEL(__FUNC__) (PMU->IOSEL |= (PMU->IOSEL & ~(0x3)) | (__FUNC__)) + +/** @brief PC14 function select + * @param __FUNC__: PC14 function select. + * This parameter can be 0: GPIO1PC14 Value + */ +#define __HAL_RTC_PC14_SEL(__FUNC__) (PMU->IOSEL |= (PMU->IOSEL & ~(0x3 << 3)) | (__FUNC__ << 3)) + +/** @brief PC15 function select + * @param __FUNC__: PC15 function select. + * This parameter can be 0: GPIO1PC15 Value + */ +#define __HAL_RTC_PC15_SEL(__FUNC__) (PMU->IOSEL |= (PMU->IOSEL & ~(0x3 << 5)) | (__FUNC__ << 5)) + +/** @brief PC13 Value set + * @param __FUNC__: PC13 Value set. + * This parameter can be 0: set1claer + */ +#define __HAL_RTC_PC13_VALUE(__VALUE__) (PMU->IOSEL |= (PMU->IOSEL & ~(1 << 8)) | (__VALUE__ << 8)) + +/** @brief PC14 Value set + * @param __FUNC__: PC14 Value set. + * This parameter can be 0: set1claer + */ +#define __HAL_RTC_PC14_VALUE(__VALUE__) (PMU->IOSEL |= (PMU->IOSEL & ~(1 << 9)) | (__VALUE__ << 9)) + +/** @brief PC15 Value set + * @param __FUNC__: PC15 Value set. + * This parameter can be 0: set1claer + */ +#define __HAL_RTC_PC15_VALUE(__VALUE__) (PMU->IOSEL |= (PMU->IOSEL & ~(1 << 10)) | (__VALUE__ << 10)) + +/* @brief PC13PC14PC15 pull up or pull down */ +#define __HAL_RTC_PC13_PULL_UP_ENABLE() (PMU->IOCR |= BIT0) +#define __HAL_RTC_PC13_PULL_UP_DISABLE() (PMU->IOCR &= ~BIT0) +#define __HAL_RTC_PC13_PULL_DOWN_ENABLE() (PMU->IOCR |= BIT1) +#define __HAL_RTC_PC13_PULL_DOWN_DISABLE() (PMU->IOCR &= ~BIT1) + +#define __HAL_RTC_PC14_PULL_UP_ENABLE() (PMU->IOCR |= BIT8) +#define __HAL_RTC_PC14_PULL_UP_DISABLE() (PMU->IOCR &= ~BIT8) +#define __HAL_RTC_PC14_PULL_DOWN_ENABLE() (PMU->IOCR |= BIT9) +#define __HAL_RTC_PC14_PULL_DOWN_DISABLE() (PMU->IOCR &= ~BIT9) + +#define __HAL_RTC_PC15_PULL_UP_ENABLE() (PMU->IOCR |= BIT16) +#define __HAL_RTC_PC15_PULL_UP_DISABLE() (PMU->IOCR &= ~BIT16) +#define __HAL_RTC_PC15_PULL_DOWN_ENABLE() (PMU->IOCR |= BIT17) +#define __HAL_RTC_PC15_PULL_DOWN_DISABLE() (PMU->IOCR &= ~BIT17) + +/* @brief PC13PC14PC15 digit or analog */ +#define __HAL_RTC_PC13_ANALOG() (PMU->IOCR |= BIT6) +#define __HAL_RTC_PC13_DIGIT() (PMU->IOCR &= ~BIT6) + +#define __HAL_RTC_PC14_ANALOG() (PMU->IOCR |= BIT14) +#define __HAL_RTC_PC14_DIGIT() (PMU->IOCR &= ~BIT14) + +#define __HAL_RTC_PC15_ANALOG() (PMU->IOCR |= BIT22) +#define __HAL_RTC_PC15_DIGIT() (PMU->IOCR &= ~BIT22) + + +/** @defgroup RTC Private Macros + * @{ + */ +#define IS_RTC_CLOCKSRC(__CLOCKSRC__) (((__CLOCKSRC__) == RTC_CLOCK_RC32K) || \ + ((__CLOCKSRC__) == RTC_CLOCK_XTL)) + +#define IS_RTC_COMPENSATION(__COMPENSATION__) (((__COMPENSATION__) == COMPENSATION_INCREASE) || \ + ((__COMPENSATION__) == COMPENSATION_DECREASE)) + +#define IS_RTC_YEAR(__YEAR__) ((__YEAR__) >= 0x00 && (__YEAR__) <= 0x99) + +#define IS_RTC_MONTH(__MONTH__) (((__MONTH__) == RTC_MONTH_JANUARY) || \ + ((__MONTH__) == RTC_MONTH_FEBRUARY) || \ + ((__MONTH__) == RTC_MONTH_MARCH) || \ + ((__MONTH__) == RTC_MONTH_APRIL) || \ + ((__MONTH__) == RTC_MONTH_MAY) || \ + ((__MONTH__) == RTC_MONTH_JUNE) || \ + ((__MONTH__) == RTC_MONTH_JULY) || \ + ((__MONTH__) == RTC_MONTH_AUGUST) || \ + ((__MONTH__) == RTC_MONTH_SEPTEMBER) || \ + ((__MONTH__) == RTC_MONTH_OCTOBER) || \ + ((__MONTH__) == RTC_MONTH_NOVEMBER) || \ + ((__MONTH__) == RTC_MONTH_DECEMBER)) + +#define IS_RTC_DAY(__DAY__) ((__DAY__) >= 0x01 && (__DAY__) <= 0x31) + +#define IS_RTC_WEEKDAY(__WEEKDAY__) (((__WEEKDAY__) == RTC_WEEKDAY_MONDAY) || \ + ((__WEEKDAY__) == RTC_WEEKDAY_TUESDAY) || \ + ((__WEEKDAY__) == RTC_WEEKDAY_WEDNESDAY) || \ + ((__WEEKDAY__) == RTC_WEEKDAY_THURSDAY) || \ + ((__WEEKDAY__) == RTC_WEEKDAY_FRIDAY) || \ + ((__WEEKDAY__) == RTC_WEEKDAY_SATURDAY) || \ + ((__WEEKDAY__) == RTC_WEEKDAY_SUNDAY)) + +#define IS_RTC_HOUR(__HOUR__) ((__HOUR__) >= 0x00 && (__HOUR__) <= 0x23) + +#define IS_RTC_MIN(__MIN__) ((__MIN__) >= 0x00 && (__MIN__) <= 0x59) + +#define IS_RTC_SEC(__SEC__) ((__SEC__) >= 0x00 && (__SEC__) <= 0x59) + + +#define IS_RTC_ALARM_MODE(__MODE__) (((__MODE__) == RTC_ALARM_WEEK_MODE) || \ + ((__MODE__) == RTC_ALARM_DAY_MODE)) + +#define IS_RTC_ALARM_INT(__INT__) (((__INT__) == RTC_ALARM_INT_ENABLE) || \ + ((__INT__) == RTC_ALARM_INT_DISABLE)) + +#define IS_RTC_ALARM_DAY_MASK(__MASKD__) (((__MASKD__) == RTC_ALARM_DAY_MASK_ENABLE) || \ + ((__MASKD__) == RTC_ALARM_DAY_MASK_DISABLE)) + +#define IS_RTC_ALARM_HOUR_MASK(__MASKH__) (((__MASKH__) == RTC_ALARM_HOUR_MASK_ENABLE) || \ + ((__MASKH__) == RTC_ALARM_HOUR_MASK_DISABLE)) + +#define IS_RTC_ALARM_MIN_MASK(__MASKM__) (((__MASKM__) == RTC_ALARM_MIN_MASK_ENABLE) || \ + ((__MASKM__) == RTC_ALARM_MIN_MASK_DISABLE)) + +#define IS_RTC_ALARM_WEEKDAY(__WEEKDAY__) (((__WEEKDAY__) == RTC_ALARM_WEEK_SUNDAY) || \ + ((__WEEKDAY__) == RTC_ALARM_WEEK_MONDAY) || \ + ((__WEEKDAY__) == RTC_ALARM_WEEK_TUESDAY) || \ + ((__WEEKDAY__) == RTC_ALARM_WEEK_WEDNESDAY) || \ + ((__WEEKDAY__) == RTC_ALARM_WEEK_THURSDAY) || \ + ((__WEEKDAY__) == RTC_ALARM_WEEK_FRIDAY) || \ + ((__WEEKDAY__) == RTC_ALARM_WEEK_SATURDAY) || \ + ((__WEEKDAY__) >= 0x01000000 && (__WEEKDAY__) <= 0x7F000000)) + + +#define IS_RTC_TEMP_EDGE(__EDGE__) (((__EDGE__) == RTC_TEMP_EDGE_RISING) || \ + ((__EDGE__) == RTC_TEMP_EDGE_FALLING)) + +#define IS_RTC_TEMP_INT(__INT__) (((__INT__) == RTC_TEMP_INT_ENABLE) || \ + ((__INT__) == RTC_TEMP_INT_DISABLE)) + +#define IS_RTC_TEMP_CLEAR_BACKUP(__CLEAR__) (((__CLEAR__) == RTC_TEMP_CLEAR_DISABLE) || \ + ((__CLEAR__) == RTC_TEMP_CLEAR_ENABLE)) + +#define IS_RTC_TEMP_FILTER(__FILTER__) (((__FILTER__) == RTC_TEMP_FILTER_DISABLE) || \ + ((__FILTER__) == RTC_TEMP_FILTER_512_RTCCLK) || \ + ((__FILTER__) == RTC_TEMP_FILTER_1_RTCCLK) || \ + ((__FILTER__) == RTC_TEMP_FILTER_2_RTCCLK) || \ + ((__FILTER__) == RTC_TEMP_FILTER_4_RTCCLK) || \ + ((__FILTER__) == RTC_TEMP_FILTER_8_RTCCLK)) +/** + * @} + */ + +/* RTC stamp1 interrupt enabledisable */ +#define __HAL_RTC_ENABLE_STAMP1_IT (RTC->IE |= (RTC_IE_STP1RIE | RTC_IE_STP1FIE)) +#define __HAL_RTC_DISABLE_STAMP1_IT (RTC->IE &= ~(RTC_IE_STP1RIE | RTC_IE_STP1FIE)) + +/* RTC stamp2 interrupt enabledisable */ +#define __HAL_RTC_ENABLE_STAMP2_IT (RTC->IE |= (RTC_IE_STP2RIE | RTC_IE_STP2FIE)) +#define __HAL_RTC_DISABLE_STAMP2_IT (RTC->IE &= ~(RTC_IE_STP2RIE | RTC_IE_STP2FIE)) + +/* RTC 32S interrupt enabledisable */ +#define __HAL_RTC_ENABLE_32S_IT (RTC->IE |= RTC_IE_ADJ32) +#define __HAL_RTC_DISABLE_32S_IT (RTC->IE &= ~RTC_IE_ADJ32) + +/* RTC alarm interrupt enabledisable */ +#define __HAL_RTC_ENABLE_ALM_IT (RTC->IE |= RTC_IE_ALM) +#define __HAL_RTC_DISABLE_ALM_IT (RTC->IE &= RTC_IE_ALM) + +/* RTC sec interrupt enabledisable */ +#define __HAL_RTC_ENABLE_SEC_IT (RTC->IE |= RTC_IE_SEC) +#define __HAL_RTC_DISABLE_SEC_IT (RTC->IE &= ~RTC_IE_SEC) + +/* RTC Minutes interrupt enabledisable */ +#define __HAL_RTC_ENABLE_MIN_IT (RTC->IE |= RTC_IE_MIN) +#define __HAL_RTC_DISABLE_MIN_IT (RTC->IE &= ~RTC_IE_MIN) + +/* RTC Hour interrupt enabledisable */ +#define __HAL_RTC_ENABLE_HOUR_IT (RTC->IE |= RTC_IE_HOUR) +#define __HAL_RTC_DISABLE_HOUR_IT (RTC->IE &= ~RTC_IE_HOUR) + +/* RTC Date interrupt enabledisable */ +#define __HAL_RTC_ENABLE_DATE_IT (RTC->IE |= RTC_IE_DATE) +#define __HAL_RTC_DISABLE_DATE_IT (RTC->IE &= ~RTC_IE_DATE) + +/* HAL_RTC_Config */ +HAL_StatusTypeDef HAL_RTC_Config(RTC_ConfigTypeDef *hrtc); + +/* HAL_RTC_SetTime */ +void HAL_RTC_SetTime(RTC_TimeTypeDef *fp_Time); + +/* HAL_RTC_GetTime */ +void HAL_RTC_GetTime(RTC_TimeTypeDef *fp_Time); + +/* HAL_RTC_SetDate */ +void HAL_RTC_SetDate(RTC_DateTypeDef *fp_Date); + +/* HAL_RTC_GetDate */ +void HAL_RTC_GetDate(RTC_DateTypeDef *fp_Date); + + +/* HAL_RTC_AlarmConfig */ +void HAL_RTC_AlarmConfig(RTC_AlarmTypeDef *fp_Alarm); + +/* HAL_RTC_AlarmEnable */ +void HAL_RTC_AlarmEnable(void); + +/* HAL_RTC_AlarmDisable */ +void HAL_RTC_AlarmDisable(void); + +/* HAL_RTC_Tamper */ +void HAL_RTC_Tamper(enum_Temper_t fe_Temper, RTC_TemperTypeDef *fp_Temper); + +/* HAL_RTC_TamperEnable */ +void HAL_RTC_TamperEnable(enum_Temper_t fe_Temper); + +/* HAL_RTC_TamperDisable */ +void HAL_RTC_TamperDisable(enum_Temper_t fe_Temper); + +/* HAL_RTC_Standby_Wakeup */ +void HAL_RTC_Standby_Wakeup(enum_WKUP_t fe_Wakeup, uint32_t fu32_Edge); + +/* HAL_RTC_Get_StandbyStatus */ +bool HAL_RTC_Get_StandbyStatus(void); + +/* HAL_RTC_Get_StandbyWakeupSource */ +uint32_t HAL_RTC_Get_StandbyWakeupSource(void); + +#endif diff --git a/bsp/acm32f4xx-nucleo/libraries/HAL_Driver/Inc/HAL_SHA1.h b/bsp/acm32f4xx-nucleo/libraries/HAL_Driver/Inc/HAL_SHA1.h new file mode 100644 index 0000000000..02c906def7 --- /dev/null +++ b/bsp/acm32f4xx-nucleo/libraries/HAL_Driver/Inc/HAL_SHA1.h @@ -0,0 +1,77 @@ +/*********************************************************************** + * Filename : sha1.h + * Description : sha1 header file + * Author(s) : firmware team + * version : V1.0 + * Modify date : 2020-07-29 + ***********************************************************************/ +#ifndef __SHA1_H__ +#define __SHA1_H__ + +#include "ACM32Fxx_HAL.h" +/********************************************************** +* structure +**********************************************************/ +//SHA1 context +typedef struct { + UINT32 state[5]; //state (ABCD) + UINT32 count[2]; // number of bits, modulo 2^64 (msb first) + uint8_t buffer[64]; // input buffer +} SHA1_CTX; + +/************************************************************************** +* Function Name : HAL_SHA1_Init +* Description : SHA1 initialization. Begins an SHA1 operation, writing a new context. +* Input : None +* Output : - *context : the point of sha1 context +* Return : None +**************************************************************************/ +void HAL_SHA1_Init(SHA1_CTX *context); + +/************************************************************************** +* Function Name : HAL_SHA1_Update +* Description : SHA1 block update operation. Continues an SHA1 message-digest +* : operation, processing another message block, and updating the +* : context. +* Input : - *context : context before transform +* : - *input : input message +* : - inputlen : the byte length of input message +* Output : - *context : context after transform +* Return : None +**************************************************************************/ +void HAL_SHA1_Update(SHA1_CTX *context,uint8_t *input,UINT32 inputLen); + +/************************************************************************** +* Function Name : HAL_SHA1_Final +* Description : SHA1 finalization. Ends an MD5 message-digest operation, writing the +* : the message digest and zeroizing the context. +* Input : - *context : context before transform +* Output : - *digest : message digest +* Return : None +**************************************************************************/ +void HAL_SHA1_Final(uint8_t *digest, SHA1_CTX *context); + +/************************************************************************** +* Function Name : HAL_SHA1_Hash +* Description : transform message to digest in SHA1 algorithm +* Input : - *pDataIn : input message to be tranformed; + : - DataLen : the byte length of message; +* Output : - *pDigest : output the digest; +* Return : None +**************************************************************************/ +void HAL_SHA1_Hash(uint8_t *pDataIn,UINT32 DataLen,uint8_t *pDigest); + +/************************************************************************** +* Function Name : SHA_encode +* Description : Encodes input (UINT32) into output (unsigned char)[Big-Endian] +* Input : - *input : input data to be tranformed; + : - len : byte len of the input data(len is a multiple of 4); +* Output : - *output : output data; +* Return : None +**************************************************************************/ +void SHA_encode (uint8_t *output, UINT32 *input, UINT32 len); +void SHA_memcpy (uint8_t *output,uint8_t *input, UINT32 len); +void SHA_memset (uint8_t *output, int value, UINT32 len); + + +#endif diff --git a/bsp/acm32f4xx-nucleo/libraries/HAL_Driver/Inc/HAL_SHA256.h b/bsp/acm32f4xx-nucleo/libraries/HAL_Driver/Inc/HAL_SHA256.h new file mode 100644 index 0000000000..9fc93387ce --- /dev/null +++ b/bsp/acm32f4xx-nucleo/libraries/HAL_Driver/Inc/HAL_SHA256.h @@ -0,0 +1,77 @@ +/*********************************************************************** + * Filename : sha256.h + * Description : sha256 header file + * Author(s) : Eric + * version : V1.0 + * Modify date : 2020-07-09 + ***********************************************************************/ + +#ifndef __SHA256_H__ +#define __SHA256_H__ + +#include "ACM32Fxx_HAL.h" + +/********************************************************** +* structure +**********************************************************/ +//SHA256 context +typedef struct { + UINT32 state[8]; //state (ABCD) + UINT32 count[2]; // number of bits, modulo 2^64 (msb first) + uint8_t buffer[64]; // input buffer +} SHA256_CTX; + +/********************************************************** +* extern functions +***********************************************************/ +void SHA_memcpy (uint8_t *output,uint8_t *input, UINT32 len); +void SHA_memset (uint8_t *output, int value, UINT32 len); +void SHA_encode (uint8_t *output, UINT32 *input, UINT32 len); +/********************************************************** +* extern variable +***********************************************************/ +extern const unsigned char PADDING[128]; + +/************************************************************************** +* Function Name : HAL_SHA256_Init +* Description : SHA256 initialization. Begins an SHA1 operation, writing a new context. +* Input : None +* Output : - *context : the point of sha1 context +* Return : None +**************************************************************************/ +void HAL_SHA256_Init(SHA256_CTX *context); + +/************************************************************************** +* Function Name : HAL_SHA256_Update +* Description : SHA256 block update operation. Continues an SHA1 message-digest +* : operation, processing another message block, and updating the +* : context. +* Input : - *context : context before transform +* : - *input : input message +* : - inputlen : the byte length of input message +* Output : - *context : context after transform +* Return : None +**************************************************************************/ +void HAL_SHA256_Update(SHA256_CTX *context, uint8_t *input,UINT32 inputLen); + +/************************************************************************** +* Function Name : HAL_SHA256_Final +* Description : SHA256 finalization. Ends an SHA256 message-digest operation, writing the +* : the message digest and zeroizing the context. +* Input : - *context : context before transform +* Output : - *digest : message digest +* Return : None +**************************************************************************/ +void HAL_SHA256_Final(uint8_t *digest, SHA256_CTX *context); + +/************************************************************************** +* Function Name : HAL_SHA256_Hash +* Description : transform message to digest in SHA1 algorithm +* Input : - *pDataIn : input message to be tranformed; + : - DataLen : the byte length of message; +* Output : - *pDigest : output the digest; +* Return : None +**************************************************************************/ +void HAL_SHA256_Hash(uint8_t *pDataIn,UINT32 DataLen,uint8_t *pDigest); + +#endif diff --git a/bsp/acm32f4xx-nucleo/libraries/HAL_Driver/Inc/HAL_SPI.h b/bsp/acm32f4xx-nucleo/libraries/HAL_Driver/Inc/HAL_SPI.h new file mode 100644 index 0000000000..519b2a27d4 --- /dev/null +++ b/bsp/acm32f4xx-nucleo/libraries/HAL_Driver/Inc/HAL_SPI.h @@ -0,0 +1,301 @@ +/* + ****************************************************************************** + * @file HAL_SPI.h + * @version V1.0.0 + * @date 2020 + * @brief Header file of SPI HAL module. + ****************************************************************************** +*/ +#ifndef __HAL_SPI_H__ +#define __HAL_SPI_H__ + +#include "ACM32Fxx_HAL.h" + +/**************** Bit definition for SPI_CTL register **************************/ +#define SPI_CTL_CS_TIME (BIT11|BIT12|BIT13|BIT14|BIT15|BIT16|BIT17|BIT18) +#define SPI_CTL_CS_FILTER BIT10 +#define SPI_CTL_CS_RST BIT9 +#define SPI_CTL_SLAVE_EN BIT8 +#define SPI_CTL_IO_MODE BIT7 +#define SPI_CTL_X_MODE (BIT6|BIT5) +#define SPI_CTL_LSB_FIRST BIT4 +#define SPI_CTL_CPOL BIT3 +#define SPI_CTL_CPHA BIT2 +#define SPI_CTL_SFILTER BIT1 +#define SPI_CTL_MST_MODE BIT0 + +/**************** Bit definition for SPI_TX_CTL register ***********************/ +#define SPI_TX_CTL_DMA_LEVEL (BIT4|BIT5|BIT6|BIT7) +#define SPI_TX_CTL_DMA_LEVEL_3 BIT7 +#define SPI_TX_CTL_DMA_LEVEL_2 BIT6 +#define SPI_TX_CTL_DMA_LEVEL_1 BIT5 +#define SPI_TX_CTL_DMA_LEVEL_0 BIT4 +#define SPI_TX_CTL_DMA_REQ_EN BIT3 +#define SPI_TX_CTL_MODE BIT2 +#define SPI_TX_CTL_FIFO_RESET BIT1 +#define SPI_TX_CTL_EN BIT0 + +/**************** Bit definition for SPI_RX_CTL register ***********************/ +#define SPI_RX_CTL_DMA_LEVEL (BIT4|BIT5|BIT6|BIT7) +#define SPI_RX_CTL_DMA_LEVEL_3 BIT7 +#define SPI_RX_CTL_DMA_LEVEL_2 BIT6 +#define SPI_RX_CTL_DMA_LEVEL_1 BIT5 +#define SPI_RX_CTL_DMA_LEVEL_0 BIT4 +#define SPI_RX_CTL_DMA_REQ_EN BIT3 +#define SPI_RX_CTL_FIFO_RESET BIT1 +#define SPI_RX_CTL_EN BIT0 + +/**************** Bit definition for SPI_IE register ***************************/ +#define SPI_IE_RX_BATCH_DONE_EN BIT15 +#define SPI_IE_TX_BATCH_DONE_EN BIT14 +#define SPI_IE_RX_FIFO_FULL_OV_EN BIT13 +#define SPI_IE_RX_FIFO_EMPTY_OV_EN BIT12 +#define SPI_IE_RX_NOT_EMPTY_EN BIT11 +#define SPI_IE_CS_POS_EN BIT10 +#define SPI_IE_RX_FIFO_HALF_FULL_EN BIT9 +#define SPI_IE_RX_FIFO_HALF_EMPTY_EN BIT8 +#define SPI_IE_TX_FIFO_HALF_FULL_EN BIT7 +#define SPI_IE_TX_FIFO_HALF_EMPTY_EN BIT6 +#define SPI_IE_RX_FIFO_FULL_EN BIT5 +#define SPI_IE_RX_FIFO_EMPTY_EN BIT4 +#define SPI_IE_TX_FIFO_FULL_EN BIT3 +#define SPI_IE_TX_FIFO_EMPTY_EN BIT2 +#define SPI_IE_BATCH_DONE_EN BIT1 + +/**************** Bit definition for SPI_STATUS register ***********************/ +#define SPI_STATUS_RX_BATCH_DONE BIT15 +#define SPI_STATUS_TX_BATCH_DONE BIT14 +#define SPI_STATUS_RX_FIFO_FULL_OV BIT13 +#define SPI_STATUS_RX_FIFO_EMPTY_OV BIT12 +#define SPI_STATUS_RX_NOT_EMPTY BIT11 +#define SPI_STATUS_CS_POS BIT10 +#define SPI_STATUS_RX_FIFO_HALF_FULL BIT9 +#define SPI_STATUS_RX_FIFO_HALF_EMPTY BIT8 +#define SPI_STATUS_TX_FIFO_HALF_FULL BIT7 +#define SPI_STATUS_TX_FIFO_HALF_EMPTY BIT6 +#define SPI_STATUS_RX_FIFO_FULL BIT5 +#define SPI_STATUS_RX_FIFO_EMPTY BIT4 +#define SPI_STATUS_TX_FIFO_FULL BIT3 +#define SPI_STATUS_TX_FIFO_EMPTY BIT2 +#define SPI_STATUS_BATCH_DONE BIT1 +#define SPI_STATUS_TX_BUSY BIT0 + +/**************** Bit definition for SPI_CS register ***************************/ +#define SPI_CS_CSX BIT1 +#define SPI_CS_CS0 BIT0 + +/**************** Bit definition for SPI_OUT_EN register ***********************/ +#define SPI_HOLD_EN BIT3 +#define SPI_HOLD_WP_EN BIT2 +#define SPI_HOLD_MISO_EN BIT1 +#define SPI_HOLD_MOSI_EN BIT0 + +/**************** Bit definition for SPI_MEMO_ACC register ***********************/ +#define SPI_ADDR_WIDTH (BIT14|BIT15|BIT16|BIT17|BIT18) +#define SPI_PARA_NO2 (BIT9|BIT10|BIT11|BIT12|BIT13) +#define SPI_PARA_NO1 (BIT5|BIT6|BIT7|BIT8) +#define SPI_CON_RD_EN BIT3 +#define SPI_PARA_ORD2 BIT2 +#define SPI_PARA_ORD1 BIT1 +#define SPI_ACC_EN BIT0 + +/** @defgroup SLAVE State machine + * @{ + */ +#define SPI_RX_STATE_IDLE (0U) +#define SPI_RX_STATE_RECEIVING (1U) +#define SPI_TX_STATE_IDLE (0U) +#define SPI_TX_STATE_SENDING (1U) +/** + * @} + */ + + +/** @defgroup SPI_MODE + * @{ + */ +#define SPI_MODE_SLAVE (0U) +#define SPI_MODE_MASTER (1U) +/** + * @} + */ + + +/** @defgroup SPI_WORK_MODE + * @{ + */ +#define SPI_WORK_MODE_0 (0x00000000) +#define SPI_WORK_MODE_1 (0x00000004) +#define SPI_WORK_MODE_2 (0x00000008) +#define SPI_WORK_MODE_3 (0x0000000C) +/** + * @} + */ + + +/** @defgroup SPI_CLOCK_PHASE SPI Clock Phase + * @{ + */ +#define SPI_PHASE_1EDGE (0U) +#define SPI_PHASE_2EDGE (1U) +/** + * @} + */ + + +/** @defgroup X_MODE SPI Clock Phase + * @{ + */ +#define SPI_1X_MODE (0x00000000) +#define SPI_2X_MODE (0x00000020) +#define SPI_4X_MODE (0x00000040) +/** + * @} + */ + + +/** @defgroup SPI_MSB_LSB_FIRST + * @{ + */ +#define SPI_FIRSTBIT_MSB (0U) +#define SPI_FIRSTBIT_LSB (1U) +/** + * @} + */ + + +/** @defgroup BAUDRATE_PRESCALER + * @{ + */ +#define SPI_BAUDRATE_PRESCALER_4 (4U) +#define SPI_BAUDRATE_PRESCALER_8 (8U) +#define SPI_BAUDRATE_PRESCALER_16 (16U) +#define SPI_BAUDRATE_PRESCALER_32 (32U) +#define SPI_BAUDRATE_PRESCALER_64 (64U) +#define SPI_BAUDRATE_PRESCALER_128 (128U) +#define SPI_BAUDRATE_PRESCALER_254 (254U) +/** + * @} + */ + + +/** + * @brief SPI Configuration Structure definition + */ +typedef struct +{ + uint32_t SPI_Mode; /* This parameter can be a value of @ref SPI_MODE */ + + uint32_t SPI_Work_Mode; /* This parameter can be a value of @ref SPI_WORK_MODE */ + + uint32_t X_Mode; /* This parameter can be a value of @ref X_MODE */ + + uint32_t First_Bit; /* This parameter can be a value of @ref SPI_MSB_LSB_FIRST */ + + uint32_t BaudRate_Prescaler; /* This parameter can be a value of @ref BAUDRATE_PRESCALER */ +}SPI_InitTypeDef; + +/******************************** Check SPI Parameter *******************************/ +#define IS_SPI_ALL_MODE(SPI_Mode) (((SPI_Mode) == SPI_MODE_SLAVE) || \ + ((SPI_Mode) == SPI_MODE_MASTER)) + +#define IS_SPI_WORK_MODE(WORK_MODE) (((WORK_MODE) == SPI_WORK_MODE_0) || \ + ((WORK_MODE) == SPI_WORK_MODE_1) || \ + ((WORK_MODE) == SPI_WORK_MODE_2) || \ + ((WORK_MODE) == SPI_WORK_MODE_3)) + +#define IS_SPI_X_MODE(X_MODE) (((X_MODE) == SPI_1X_MODE) || \ + ((X_MODE) == SPI_2X_MODE) || \ + ((X_MODE) == SPI_4X_MODE)) + +#define IS_SPI_FIRST_BIT(FIRST_BIT) (((FIRST_BIT) == SPI_FIRSTBIT_MSB) || \ + ((FIRST_BIT) == SPI_FIRSTBIT_LSB)) + +#define IS_SPI_BAUDRATE_PRESCALER(BAUDRATE) (((BAUDRATE) == SPI_BAUDRATE_PRESCALER_4) || \ + ((BAUDRATE) == SPI_BAUDRATE_PRESCALER_8) || \ + ((BAUDRATE) == SPI_BAUDRATE_PRESCALER_16) || \ + ((BAUDRATE) == SPI_BAUDRATE_PRESCALER_32) || \ + ((BAUDRATE) == SPI_BAUDRATE_PRESCALER_64) || \ + ((BAUDRATE) == SPI_BAUDRATE_PRESCALER_128) || \ + ((BAUDRATE) == SPI_BAUDRATE_PRESCALER_254)) + +/** + * @brief SPI handle Structure definition + */ +typedef struct +{ + SPI_TypeDef *Instance; /* SPI registers base address */ + + SPI_InitTypeDef Init; /* SPI communication parameters */ + + uint32_t RxState; /* SPI state machine */ + uint32_t TxState; /* SPI state machine */ + + uint8_t *Rx_Buffer; /* SPI Rx Buffer */ + uint8_t *Tx_Buffer; /* SPI Tx Buffer */ + + uint32_t Rx_Size; /* SPI Rx Size */ + uint32_t Tx_Size; /* SPI Tx Size */ + + uint32_t Rx_Count; /* SPI RX Count */ + uint32_t Tx_Count; /* SPI TX Count */ + + DMA_HandleTypeDef *HDMA_Rx; /* SPI Rx DMA handle parameters */ + DMA_HandleTypeDef *HDMA_Tx; /* SPI Tx DMA handle parameters */ + +}SPI_HandleTypeDef; + +/******************************** SPI Instances *******************************/ +#define IS_SPI_ALL_INSTANCE(INSTANCE) (((INSTANCE) == SPI1) || ((INSTANCE) == SPI2) || ((INSTANCE) == SPI3) || ((INSTANCE) == SPI4)) + +/* Function : HAL_SPI_IRQHandler */ +void HAL_SPI_IRQHandler(SPI_HandleTypeDef *hspi); + +/* Function : HAL_SPI_MspInit */ +void HAL_SPI_MspInit(SPI_HandleTypeDef *hspi); + +/* Function : HAL_SPI_MspDeInit */ +void HAL_SPI_MspDeInit(SPI_HandleTypeDef *hspi); + +/* Function : HAL_SPI_Init */ +HAL_StatusTypeDef HAL_SPI_Init(SPI_HandleTypeDef *hspi); + +/* Function : HAL_SPI_DeInit */ +HAL_StatusTypeDef HAL_SPI_DeInit(SPI_HandleTypeDef *hspi); + +/* Function : HAL_SPI_Transmit */ +HAL_StatusTypeDef HAL_SPI_Transmit(SPI_HandleTypeDef *hspi, uint8_t *pData, uint32_t Size, uint32_t Timeout); + +/* Function : HAL_SPI_Transmit_DMA */ +HAL_StatusTypeDef HAL_SPI_Transmit_DMA(SPI_HandleTypeDef *hspi, uint8_t *pData, uint32_t Size); + +/* Function : HAL_SPI_Receive */ +HAL_StatusTypeDef HAL_SPI_Receive(SPI_HandleTypeDef *hspi, uint8_t *pData, uint32_t Size, uint32_t Timeout); + +/* Function : HAL_SPI_Receive_DMA */ +HAL_StatusTypeDef HAL_SPI_Receive_DMA(SPI_HandleTypeDef *hspi, uint8_t *pData, uint32_t Size); + +/* Function : HAL_SPI_Wire_Config */ +HAL_StatusTypeDef HAL_SPI_Wire_Config(SPI_HandleTypeDef *hspi, uint32_t X_Mode); + +/* Function : HAL_SPI_Transmit_IT */ +HAL_StatusTypeDef HAL_SPI_Transmit_IT(SPI_HandleTypeDef *hspi, uint8_t *pData, uint32_t Size); + +/* Function : HAL_SPI_Receive_IT */ +HAL_StatusTypeDef HAL_SPI_Receive_IT(SPI_HandleTypeDef *hspi, uint8_t *pData, uint32_t Size); + +/* Function : HAL_SPI_TransmitReceive */ +HAL_StatusTypeDef HAL_SPI_TransmitReceive(SPI_HandleTypeDef *hspi, uint8_t *pTxData, uint8_t *pRxData, uint32_t Size, uint32_t Timeout); + +/* Function : HAL_SPI_GetTxState */ +uint8_t HAL_SPI_GetTxState(SPI_HandleTypeDef *hspi); + +/* Function : HAL_SPI_GetRxState */ +uint8_t HAL_SPI_GetRxState(SPI_HandleTypeDef *hspi); + +#endif + + + + + diff --git a/bsp/acm32f4xx-nucleo/libraries/HAL_Driver/Inc/HAL_TIMER.h b/bsp/acm32f4xx-nucleo/libraries/HAL_Driver/Inc/HAL_TIMER.h new file mode 100644 index 0000000000..d9f895581e --- /dev/null +++ b/bsp/acm32f4xx-nucleo/libraries/HAL_Driver/Inc/HAL_TIMER.h @@ -0,0 +1,520 @@ +/*********************************************************************** + * Filename : hal_timer.h + * Description : timer driver header file + * Author(s) : Eric + * version : V1.0 + * Modify date : 2016-03-24 + ***********************************************************************/ +#ifndef __HAL_TIMER_H__ +#define __HAL_TIMER_H__ + +#include "ACM32Fxx_HAL.h" + +#define IS_TIMER_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || ((INSTANCE) == TIM2) || ((INSTANCE) == TIM3) \ + || ((INSTANCE) == TIM4) || ((INSTANCE) == TIM6) || ((INSTANCE) == TIM7)\ + || ((INSTANCE) == TIM14) || ((INSTANCE) == TIM15) || ((INSTANCE) == TIM16)\ + | ((INSTANCE) == TIM17) ) + +/****************** TIM Instances : supporting the break function *************/ +#define IS_TIM_BREAK_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \ + ((INSTANCE) == TIM15) || \ + ((INSTANCE) == TIM16) || \ + ((INSTANCE) == TIM17)) + +/************** TIM Instances : supporting Break source selection *************/ +#define IS_TIM_BREAKSOURCE_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \ + ((INSTANCE) == TIM15) || \ + ((INSTANCE) == TIM16) || \ + ((INSTANCE) == TIM17)) + + +/************* TIM Instances : at least 1 capture/compare channel *************/ +#define IS_TIM_CC1_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \ + ((INSTANCE) == TIM2) || \ + ((INSTANCE) == TIM3) || \ + ((INSTANCE) == TIM4) || \ + ((INSTANCE) == TIM14) || \ + ((INSTANCE) == TIM15) || \ + ((INSTANCE) == TIM16) || \ + ((INSTANCE) == TIM17)) + +/************ TIM Instances : at least 2 capture/compare channels *************/ +#define IS_TIM_CC2_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \ + ((INSTANCE) == TIM2) || \ + ((INSTANCE) == TIM3) || \ + ((INSTANCE) == TIM4) || \ + ((INSTANCE) == TIM15)) + +/************ TIM Instances : at least 3 capture/compare channels *************/ +#define IS_TIM_CC3_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \ + ((INSTANCE) == TIM2) || \ + ((INSTANCE) == TIM3) || \ + ((INSTANCE) == TIM4)) + +/************ TIM Instances : at least 4 capture/compare channels *************/ +#define IS_TIM_CC4_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \ + ((INSTANCE) == TIM2) || \ + ((INSTANCE) == TIM3) || \ + ((INSTANCE) == TIM4)) + + +/****************** TIM Instances : DMA requests generation (TIMx_DIER.UDE) ***/ +#define IS_TIM_UDMA_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \ + ((INSTANCE) == TIM3) || \ + ((INSTANCE) == TIM6) || \ + ((INSTANCE) == TIM7) || \ + ((INSTANCE) == TIM15) || \ + ((INSTANCE) == TIM16) || \ + ((INSTANCE) == TIM17)) + +/******************* TIM Instances : output(s) available **********************/ +#define IS_TIM_CCX_INSTANCE(INSTANCE, CHANNEL) \ + ( (((INSTANCE) == TIM1) && \ + (((CHANNEL) == TIM_CHANNEL_1) || \ + ((CHANNEL) == TIM_CHANNEL_2) || \ + ((CHANNEL) == TIM_CHANNEL_3) || \ + ((CHANNEL) == TIM_CHANNEL_4) ) ) \ + || \ + (((INSTANCE) == TIM2) && \ + (((CHANNEL) == TIM_CHANNEL_1) || \ + ((CHANNEL) == TIM_CHANNEL_2) || \ + ((CHANNEL) == TIM_CHANNEL_3) || \ + ((CHANNEL) == TIM_CHANNEL_4)) ) \ + || \ + (((INSTANCE) == TIM3) && \ + (((CHANNEL) == TIM_CHANNEL_1) || \ + ((CHANNEL) == TIM_CHANNEL_2) || \ + ((CHANNEL) == TIM_CHANNEL_3) || \ + ((CHANNEL) == TIM_CHANNEL_4)) ) \ + || \ + (((INSTANCE) == TIM4) && \ + (((CHANNEL) == TIM_CHANNEL_1) || \ + ((CHANNEL) == TIM_CHANNEL_2) || \ + ((CHANNEL) == TIM_CHANNEL_3) || \ + ((CHANNEL) == TIM_CHANNEL_4)) ) \ + || \ + (((INSTANCE) == TIM14) && \ + (((CHANNEL) == TIM_CHANNEL_1)) ) \ + || \ + (((INSTANCE) == TIM15) && \ + (((CHANNEL) == TIM_CHANNEL_1) || \ + ((CHANNEL) == TIM_CHANNEL_2)) ) \ + || \ + (((INSTANCE) == TIM16) && \ + (((CHANNEL) == TIM_CHANNEL_1)) ) \ + || \ + (((INSTANCE) == TIM17) && \ + ((CHANNEL) == TIM_CHANNEL_1) ) ) + +/****************** TIM Instances : supporting complementary output(s) ********/ +#define IS_TIM_CCXN_INSTANCE(INSTANCE, CHANNEL) \ + ((( (INSTANCE) == TIM1) && \ + (((CHANNEL) == TIM_CHANNEL_1) || \ + ((CHANNEL) == TIM_CHANNEL_2) || \ + ((CHANNEL) == TIM_CHANNEL_3)) ) \ + || \ + (((INSTANCE) == TIM15) && \ + ((CHANNEL) == TIM_CHANNEL_1)) \ + || \ + (((INSTANCE) == TIM16) && \ + ((CHANNEL) == TIM_CHANNEL_1)) \ + || \ + (((INSTANCE) == TIM17) && \ + ((CHANNEL) == TIM_CHANNEL_1) ) ) + +/****************** TIM Instances : supporting clock division *****************/ +#define IS_TIM_CLOCK_DIVISION_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \ + ((INSTANCE) == TIM2) || \ + ((INSTANCE) == TIM3) || \ + ((INSTANCE) == TIM4) || \ + ((INSTANCE) == TIM14) || \ + ((INSTANCE) == TIM15) || \ + ((INSTANCE) == TIM16) || \ + ((INSTANCE) == TIM17)) + +/****** TIM Instances : supporting external clock mode 1 for ETRF input *******/ +#define IS_TIM_CLOCKSOURCE_ETRMODE1_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \ + ((INSTANCE) == TIM2) \ + ((INSTANCE) == TIM3) \ + ((INSTANCE) == TIM4) ) + +/****** TIM Instances : supporting external clock mode 2 for ETRF input *******/ +#define IS_TIM_CLOCKSOURCE_ETRMODE2_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \ + ((INSTANCE) == TIM2) \ + ((INSTANCE) == TIM3) \ + ((INSTANCE) == TIM4) ) + +/****************** TIM Instances : supporting combined 3-phase PWM mode ******/ +#define IS_TIM_COMBINED3PHASEPWM_INSTANCE(INSTANCE) ((INSTANCE) == TIM1) + +/****************** TIM Instances : supporting commutation event generation ***/ +#define IS_TIM_COMMUTATION_EVENT_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \ + ((INSTANCE) == TIM15) || \ + ((INSTANCE) == TIM16) || \ + ((INSTANCE) == TIM17)) + +/****************** TIM Instances : supporting encoder interface **************/ +#define IS_TIM_ENCODER_INTERFACE_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \ + ((INSTANCE) == TIM2) \ + ((INSTANCE) == TIM3) \ + ((INSTANCE) == TIM4) ) + +/****************** TIM Instances : supporting Hall sensor interface **********/ +#define IS_TIM_HALL_SENSOR_INTERFACE_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \ + ((INSTANCE) == TIM2) \ + ((INSTANCE) == TIM3) \ + ((INSTANCE) == TIM4) ) + +/*********** TIM Instances : Slave mode available (TIMx_SMCR available )*******/ +#define IS_TIM_SLAVE_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \ + ((INSTANCE) == TIM2) || \ + ((INSTANCE) == TIM3) || \ + ((INSTANCE) == TIM4) || \ + ((INSTANCE) == TIM15)) + +/****************** TIM Instances : supporting repetition counter *************/ +#define IS_TIM_REPETITION_COUNTER_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \ + ((INSTANCE) == TIM15) || \ + ((INSTANCE) == TIM16) || \ + ((INSTANCE) == TIM17)) + +#define HAL_TIM_ENABLE_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->DIER |= (__INTERRUPT__)) +#define HAL_TIM_DISABLE_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->DIER &= ~(__INTERRUPT__)) + +#define HAL_TIM_ENABLE_IT_EX(__INSTANCE__, __INTERRUPT__) ((__INSTANCE__)->DIER |= (__INTERRUPT__)) +#define HAL_TIM_DISABLE_IT_EX(__INSTANCE__, __INTERRUPT__) ((__INSTANCE__)->DIER &= ~(__INTERRUPT__)) + +#define HAL_TIM_ENABLE_DMA(__HANDLE__, __DMA_REQ__) ((__HANDLE__)->Instance->DIER |= (__DMA_REQ__)) +#define HAL_TIM_DISABLE_DMA(__HANDLE__, __DMA_REQ__) ((__HANDLE__)->Instance->DIER &= ~(__DMA_REQ__)) + + + +#define TIM_CR2_CCPC_Pos (0U) +#define TIM_CR2_CCPC_Msk (0x1UL << TIM_CR2_CCPC_Pos) +#define TIM_CR2_CCPC TIM_CR2_CCPC_Msk +#define TIM_CR2_CCUS_Pos (2U) +#define TIM_CR2_CCUS_Msk (0x1UL << TIM_CR2_CCUS_Pos) +#define TIM_CR2_CCUS TIM_CR2_CCUS_Msk +#define TIM_CR2_CCDS_Pos (3U) +#define TIM_CR2_CCDS_Msk (0x1UL << TIM_CR2_CCDS_Pos) +#define TIM_CR2_CCDS TIM_CR2_CCDS_Msk + +#define TIM_COMMUTATION_TRGI TIM_CR2_CCUS +#define TIM_COMMUTATION_SOFTWARE 0x00000000U + +#define TIM_IT_UPDATE BIT0 +#define TIM_IT_CC1 BIT1 +#define TIM_IT_CC2 BIT2 +#define TIM_IT_CC3 BIT3 +#define TIM_IT_CC4 BIT4 +#define TIM_IT_COM BIT5 +#define TIM_IT_TRIGGER BIT6 +#define TIM_IT_BREAK BIT7 + +#define TIM_DMA_UPDATE BIT8 +#define TIM_DMA_CC1 BIT9 +#define TIM_DMA_CC2 BIT10 +#define TIM_DMA_CC3 BIT11 +#define TIM_DMA_CC4 BIT12 +#define TIM_DMA_COM BIT13 +#define TIM_DMA_TRIGGER BIT14 +#define TIM_DMA_BREAK BIT15 + + + +#define TIM_EVENTSOURCE_UPDATE BIT0 /*!< Reinitialize the counter and generates an update of the registers */ +#define TIM_EVENTSOURCE_CC1 BIT1 /*!< A capture/compare event is generated on channel 1 */ +#define TIM_EVENTSOURCE_CC2 BIT2 /*!< A capture/compare event is generated on channel 2 */ +#define TIM_EVENTSOURCE_CC3 BIT3 /*!< A capture/compare event is generated on channel 3 */ +#define TIM_EVENTSOURCE_CC4 BIT4 /*!< A capture/compare event is generated on channel 4 */ +#define TIM_EVENTSOURCE_COM BIT5 /*!< A commutation event is generated */ +#define TIM_EVENTSOURCE_TRIGGER BIT6 /*!< A trigger event is generated */ +#define TIM_EVENTSOURCE_BREAK BIT7 /*!< A break event is generated */ + +#define TIM_ARR_PRELOAD_DISABLE 0 +#define TIM_ARR_PRELOAD_ENABLE 1 + +#define TIM_COUNTERMODE_DIR_INDEX 4 +#define TIM_COUNTERMODE_UP (0 << TIM_COUNTERMODE_DIR_INDEX) +#define TIM_COUNTERMODE_DOWN (1 << TIM_COUNTERMODE_DIR_INDEX) + +#define TIM_COUNTERMODE_CMS_INDEX 5 +#define TIM_COUNTERMODE_CENTERALIGNED1 (1 << TIM_COUNTERMODE_CMS_INDEX) +#define TIM_COUNTERMODE_CENTERALIGNED2 (2 << TIM_COUNTERMODE_CMS_INDEX) +#define TIM_COUNTERMODE_CENTERALIGNED3 (3 << TIM_COUNTERMODE_CMS_INDEX) + +#define TIM_CLKCK_DIV_INDEX 8 +#define TIM_CLOCKDIVISION_DIV1 0x00000000U /*!< Clock division: tDTS=tCK_INT */ +#define TIM_CLOCKDIVISION_DIV2 (1U << TIM_CLKCK_DIV_INDEX) /*!< Clock division: tDTS=2*tCK_INT */ +#define TIM_CLOCKDIVISION_DIV4 (2U << TIM_CLKCK_DIV_INDEX) /*!< Clock division: tDTS=4*tCK_INT */ + +#define TIM_TRGO_RESET (0 << 4) +#define TIM_TRGO_ENABLE (1 << 4) +#define TIM_TRGO_UPDATE (2 << 4) +#define TIM_TRGO_CMP_PULSE (3 << 4) +#define TIM_TRGO_OC1REF (4 << 4) +#define TIM_TRGO_OC2REF (5 << 4) +#define TIM_TRGO_OC3REF (6 << 4) +#define TIM_TRGO_OC4REF (7 << 4) + +#define TIM_MASTERSLAVEMODE_DISABLE 0 +#define TIM_MASTERSLAVEMODE_ENABLE BIT7 + + +#define TIM_SLAVE_MODE_INDEX 0 +#define TIM_SLAVE_MODE_DIS (0U << TIM_SLAVE_MODE_INDEX) +#define TIM_SLAVE_MODE_ENC1 (1U << TIM_SLAVE_MODE_INDEX) +#define TIM_SLAVE_MODE_ENC2 (2U << TIM_SLAVE_MODE_INDEX) +#define TIM_SLAVE_MODE_ENC3 (3U << TIM_SLAVE_MODE_INDEX) +#define TIM_SLAVE_MODE_RST (4U << TIM_SLAVE_MODE_INDEX) +#define TIM_SLAVE_MODE_GATE (5U << TIM_SLAVE_MODE_INDEX) +#define TIM_SLAVE_MODE_TRIG (6U << TIM_SLAVE_MODE_INDEX) +#define TIM_SLAVE_MODE_EXT1 (7U << TIM_SLAVE_MODE_INDEX) + +#define TIM_TRIGGER_SOURCE_INDEX 4 +#define TIM_TRIGGER_SOURCE_ITR0 (0U << TIM_TRIGGER_SOURCE_INDEX) +#define TIM_TRIGGER_SOURCE_ITR1 (1U << TIM_TRIGGER_SOURCE_INDEX) +#define TIM_TRIGGER_SOURCE_ITR2 (2U << TIM_TRIGGER_SOURCE_INDEX) +#define TIM_TRIGGER_SOURCE_ITR3 (3U << TIM_TRIGGER_SOURCE_INDEX) +#define TIM_TRIGGER_SOURCE_TI1F_ED (4U << TIM_TRIGGER_SOURCE_INDEX) +#define TIM_TRIGGER_SOURCE_TI1FP1 (5U << TIM_TRIGGER_SOURCE_INDEX) +#define TIM_TRIGGER_SOURCE_TI2FP2 (6U << TIM_TRIGGER_SOURCE_INDEX) +#define TIM_TRIGGER_SOURCE_ETRF (7U << TIM_TRIGGER_SOURCE_INDEX) + +#define TIMER_SR_UIF BIT0 +#define TIMER_SR_CC1IF BIT1 +#define TIMER_SR_CC2IF BIT2 +#define TIMER_SR_CC3IF BIT3 +#define TIMER_SR_CC4IF BIT4 +#define TIMER_SR_COMIF BIT5 +#define TIMER_SR_TIF BIT6 +#define TIMER_SR_BIF BIT7 +#define TIMER_SR_CC1OF BIT9 +#define TIMER_SR_CC2OF BIT10 +#define TIMER_SR_CC3OF BIT11 +#define TIMER_SR_CC4OF BIT12 + +#define TIMER_INT_EN_UPD BIT0 +#define TIMER_INT_EN_CC1 BIT1 +#define TIMER_INT_EN_CC2 BIT2 +#define TIMER_INT_EN_CC3 BIT3 +#define TIMER_INT_EN_CC4 BIT4 +#define TIMER_INT_EN_COM BIT5 +#define TIMER_INT_EN_TRI BIT6 +#define TIMER_INT_EN_BRK BIT7 + +#define TIMER_DMA_EN_UPD BIT8 +#define TIMER_DMA_EN_CC1 BIT9 +#define TIMER_DMA_EN_CC2 BIT10 +#define TIMER_DMA_EN_CC3 BIT11 +#define TIMER_DMA_EN_CC4 BIT12 +#define TIMER_DMA_EN_COM BIT13 +#define TIMER_DMA_EN_TRI BIT14 + +#define TIM_CHANNEL_1 0 +#define TIM_CHANNEL_2 1 +#define TIM_CHANNEL_3 2 +#define TIM_CHANNEL_4 3 + +#define OUTPUT_FAST_MODE_DISABLE 0 +#define OUTPUT_FAST_MODE_ENABLE 1 + +#define OUTPUT_POL_ACTIVE_HIGH 0 +#define OUTPUT_POL_ACTIVE_LOW 1 + +#define OUTPUT_DISABLE_IDLE_STATE 0 +#define OUTPUT_ENABLE_IDLE_STATE 1 + +#define OUTPUT_IDLE_STATE_0 0 +#define OUTPUT_IDLE_STATE_1 1 + +#define OUTPUT_MODE_FROZEN 0 +#define OUTPUT_MODE_MATCH_HIGH 1 +#define OUTPUT_MODE_MATCH_LOW 2 +#define OUTPUT_MODE_MATCH_TOGGLE 3 +#define OUTPUT_MODE_FORCE_LOW 4 +#define OUTPUT_MODE_FORCE_HIGH 5 +#define OUTPUT_MODE_PWM1 6 +#define OUTPUT_MODE_PWM2 7 + +#define TIM_CLOCKSOURCE_INT 0 +#define TIM_CLOCKSOURCE_ITR0 1 +#define TIM_CLOCKSOURCE_ITR1 2 +#define TIM_CLOCKSOURCE_ITR2 3 +#define TIM_CLOCKSOURCE_ITR3 4 +#define TIM_CLOCKSOURCE_TI1FP1 5 +#define TIM_CLOCKSOURCE_TI2FP2 6 +#define TIM_CLOCKSOURCE_ETR 7 + +#define TIM_ETR_POLAIRTY_HIGH 0 +#define TIM_ETR_POLAIRTY_LOW (BIT15) +#define TIM_ETR_FILTER_LVL(x) (x << 8) //BIT8-BIT11 + +#define TIM_ETR_PRESCALER_1 0 +#define TIM_ETR_PRESCALER_2 (BIT12) +#define TIM_ETR_PRESCALER_4 (BIT13) +#define TIM_ETR_PRESCALER_8 (BIT12|BIT13) + +#define ETR_SELECT_GPIO 0 +#define ETR_SELECT_COMP1_OUT BIT14 +#define ETR_SELECT_COMP2_OUT BIT15 +#define ETR_SELECT_ADC_AWD BIT14|BIT15 +#define ETR_SELECT_MASK (BIT14|BIT15) + +#define TIM_TI1_FILTER_LVL(x) (x << 4) +#define TIM_TI2_FILTER_LVL(x) (x << 12) +#define TIM_TI3_FILTER_LVL(x) (x << 4) +#define TIM_TI4_FILTER_LVL(x) (x << 12) + +#define TIM_IC1_PRESCALER_1 0 +#define TIM_IC1_PRESCALER_2 (BIT2) +#define TIM_IC1_PRESCALER_4 (BIT3) +#define TIM_IC1_PRESCALER_8 (BIT2|BIT3) + +#define TIM_IC2_PRESCALER_1 0 +#define TIM_IC2_PRESCALER_2 (BIT10) +#define TIM_IC2_PRESCALER_4 (BIT11) +#define TIM_IC2_PRESCALER_8 (BIT10|BIT11) + +#define TIM_IC3_PRESCALER_1 0 +#define TIM_IC3_PRESCALER_2 (BIT2) +#define TIM_IC3_PRESCALER_4 (BIT3) +#define TIM_IC3_PRESCALER_8 (BIT2|BIT3) + +#define TIM_IC4_PRESCALER_1 0 +#define TIM_IC4_PRESCALER_2 (BIT10) +#define TIM_IC4_PRESCALER_4 (BIT11) +#define TIM_IC4_PRESCALER_8 (BIT10|BIT11) + +typedef struct +{ + uint32_t ClockSource; //TIMER clock sources + uint32_t ClockPolarity; //TIMER clock polarity + uint32_t ClockPrescaler; //TIMER clock prescaler + uint32_t ClockFilter; //TIMER clock filter +} TIM_ClockConfigTypeDef; + +typedef struct +{ + uint32_t OCMode; // Specifies the TIM mode. + uint32_t Pulse; // Specifies the pulse value to be loaded into the Capture Compare Register. + uint32_t OCPolarity; // Specifies the output polarity. + uint32_t OCNPolarity; // Specifies the complementary output polarity. + uint32_t OCFastMode; // Specifies the Fast mode state. + uint32_t OCIdleState; // Specifies the TIM Output Compare pin state during Idle state. + uint32_t OCNIdleState; // Specifies the TIM Output Compare complementary pin state during Idle state. +} TIM_OC_InitTypeDef; + + +#define TIM_SLAVE_CAPTURE_ACTIVE_RISING 0 +#define TIM_SLAVE_CAPTURE_ACTIVE_FALLING 1 +#define TIM_SLAVE_CAPTURE_ACTIVE_RISING_FALLING 2 + +#define TIM_ICSELECTION_DIRECTTI 0 +#define TIM_ICSELECTION_INDIRECTTI 1 + +#define TIM_CC1_SLAVE_CAPTURE_POL_RISING (0) +#define TIM_CC1_SLAVE_CAPTURE_POL_FALLING (BIT1) +#define TIM_CC1_SLAVE_CAPTURE_POL_BOTH (BIT1 | BIT3) + +#define TIM_CC2_SLAVE_CAPTURE_POL_RISING (0) +#define TIM_CC2_SLAVE_CAPTURE_POL_FALLING (BIT5) +#define TIM_CC2_SLAVE_CAPTURE_POL_BOTH (BIT5 | BIT7) + +#define TIM_CC3_SLAVE_CAPTURE_POL_RISING (0) +#define TIM_CC3_SLAVE_CAPTURE_POL_FALLING (BIT9) +#define TIM_CC3_SLAVE_CAPTURE_POL_BOTH (BIT9 | BIT11) + +#define TIM_CC4_SLAVE_CAPTURE_POL_RISING (0) +#define TIM_CC4_SLAVE_CAPTURE_POL_FALLING (BIT13) +#define TIM_CC4_SLAVE_CAPTURE_POL_BOTH (BIT13 | BIT15) + +typedef struct +{ + uint32_t SlaveMode; // Slave mode selection + uint32_t InputTrigger; // Input Trigger source + uint32_t TriggerPolarity; // Input Trigger polarity + uint32_t TriggerPrescaler; // input prescaler, only for ETR input + uint32_t TriggerFilter; // Input trigger filter +} TIM_SlaveConfigTypeDef; + +typedef struct +{ + uint32_t ICPolarity; // Specifies the active edge of the input signal. + uint32_t ICSelection; // Specifies the input + uint32_t ICPrescaler; // Specifies the Input Capture Prescaler. + uint32_t TIFilter; // Specifies the input capture filter. +} TIM_IC_InitTypeDef; + +typedef struct +{ + uint32_t MasterOutputTrigger; // Trigger output (TRGO) selection + uint32_t MasterSlaveMode; // Master/slave mode selection +} TIM_MasterConfigTypeDef; + +#define TIM_DMA_UPDATE_INDEX 0 +#define TIM_DMA_CC1_INDEX 1 +#define TIM_DMA_CC2_INDEX 2 +#define TIM_DMA_CC3_INDEX 3 +#define TIM_DMA_CC4_INDEX 4 +#define TIM_DMA_COM_INDEX 5 +#define TIM_DMA_TRIG_INDEX 6 + +#define MAX_DMA_REQ_ONE_TIMER 7 + +typedef struct +{ + uint32_t Prescaler; // Specifies the prescaler value used to divide the TIM clock. + uint32_t Period; // Specifies the ARR value + uint32_t ARRPreLoadEn; // Specifies the preload enable or disable + uint32_t RepetitionCounter; // Specifies the repetition counter value + uint32_t CounterMode; // Specifies the counter mode.Up/Down/Center + uint32_t ClockDivision; // Specifies the clock division, used for deadtime or sampling +} TIM_Base_InitTypeDef; + +typedef struct +{ + TIM_TypeDef *Instance; + TIM_Base_InitTypeDef Init; /*!< TIM Time Base required parameters */ + DMA_HandleTypeDef *hdma[MAX_DMA_REQ_ONE_TIMER]; +}TIM_HandleTypeDef; + +/* HAL_TIMER_MSP_Init */ +extern uint32_t HAL_TIMER_MSP_Init(TIM_HandleTypeDef * htim); +/* HAL_TIMER_Slave_Mode_Config */ +extern uint32_t HAL_TIMER_Slave_Mode_Config(TIM_HandleTypeDef *htim, TIM_SlaveConfigTypeDef *sSlaveConfig); +/* HAL_TIMER_Base_Init */ +extern uint32_t HAL_TIMER_Base_Init(TIM_HandleTypeDef * htim); +/* HAL_TIMER_Output_Config */ +extern uint32_t HAL_TIMER_Output_Config(TIM_TypeDef *TIMx, TIM_OC_InitTypeDef * Output_Config, uint32_t Channel); +/* HAL_TIMER_Base_Start */ +extern void HAL_TIMER_Base_Start(TIM_TypeDef *TIMx); +/* HAL_TIM_PWM_Output_Start */ +extern uint32_t HAL_TIM_PWM_Output_Start(TIM_TypeDef *TIMx, uint32_t Channel); +/* HAL_TIM_PWM_Output_Stop */ +extern HAL_StatusTypeDef HAL_TIM_PWM_Output_Stop(TIM_TypeDef *TIMx, uint32_t Channel); +/* HAL_TIMER_OC_Start */ +extern uint32_t HAL_TIMER_OC_Start(TIM_TypeDef *TIMx, uint32_t Channel); +/* HAL_TIMER_OCxN_Start */ +extern uint32_t HAL_TIMER_OCxN_Start(TIM_TypeDef *TIMx, uint32_t Channel); +/* HAL_TIMER_OC_Stop */ +extern HAL_StatusTypeDef HAL_TIM_OC_Stop(TIM_TypeDef *TIMx, uint32_t Channel); +/* HAL_TIM_Capture_Start */ +extern uint32_t HAL_TIM_Capture_Start(TIM_TypeDef *TIMx, uint32_t Channel); +/* HAL_TIM_Capture_Stop */ +extern uint32_t HAL_TIM_Capture_Stop(TIM_TypeDef *TIMx, uint32_t Channel); +/* HAL_TIMER_Capture_Config */ +extern uint32_t HAL_TIMER_Capture_Config(TIM_TypeDef *TIMx, TIM_IC_InitTypeDef * Capture_Config, uint32_t Channel); +/* HAL_TIMER_Master_Mode_Config */ +extern uint32_t HAL_TIMER_Master_Mode_Config(TIM_TypeDef *TIMx, TIM_MasterConfigTypeDef * sMasterConfig); +/* HAL_TIMER_SelectClockSource */ +extern HAL_StatusTypeDef HAL_TIMER_SelectClockSource(TIM_HandleTypeDef *htim, TIM_ClockConfigTypeDef * sClockSourceConfig); +/* HAL_TIMER_ReadCapturedValue */ +extern uint32_t HAL_TIMER_ReadCapturedValue(TIM_HandleTypeDef *htim, uint32_t Channel); +/* HAL_TIMER_Clear_Capture_Flag */ +extern void HAL_TIMER_Clear_Capture_Flag(TIM_HandleTypeDef *htim, uint32_t Channel); +#endif + + + + diff --git a/bsp/acm32f4xx-nucleo/libraries/HAL_Driver/Inc/HAL_TIMER_EX.h b/bsp/acm32f4xx-nucleo/libraries/HAL_Driver/Inc/HAL_TIMER_EX.h new file mode 100644 index 0000000000..2635fb77a0 --- /dev/null +++ b/bsp/acm32f4xx-nucleo/libraries/HAL_Driver/Inc/HAL_TIMER_EX.h @@ -0,0 +1,128 @@ +/*********************************************************************** + * Filename : hal_timer_ex.h + * Description : timer driver header file + * Author(s) : xwl + * version : V1.0 + * Modify date : 2021-03-24 + ***********************************************************************/ +#ifndef __HAL_TIMER_EX_H__ +#define __HAL_TIMER_EX_H__ + +#include "ACM32Fxx_HAL.h" + + +#define TIM_BDTR_DTG_Pos (0U) +#define TIM_BDTR_DTG_Msk (0xFFUL << TIM_BDTR_DTG_Pos) /*!< 0x000000FF */ +#define TIM_BDTR_DTG TIM_BDTR_DTG_Msk /*!Instance)) return; + if(!IS_ADC_ALL_CONCONVMODE(hadc->Init.ConConvMode)) return; + + Status = hadc->Instance->SR; + /************ Check End of Conversion flag for injected ************/ + if(__HAL_ADC_GET_IT_SOURCE(hadc, ADC_IE_JEOCIE)) + { + if((Status & ADC_SR_JEOC) == ADC_SR_JEOC) + { + if(__HAL_ADC_CHECK_TRIG_INJECTED(hadc, ADC_SOFTWARE_START) || + ((__HAL_ADC_CHECK_TRIG_REGULAR(hadc, ADC_SOFTWARE_START)) && + (hadc->Init.ConConvMode == 0))) + { + /* Disable ADC end of conversion interrupt on group injected */ + __HAL_ADC_DISABLE_IT(hadc, ADC_IE_JEOCIE); + + } + + /* Conversion complete callback */ + if (NULL != hadc->InjectedConvCpltCallback) + hadc->InjectedConvCpltCallback(hadc); + + /* Clear injected group conversion flag */ + __HAL_ADC_CLEAR_FLAG(hadc, ADC_SR_JEOC); + } + } + + /************ Check Conversion flag for regular group ************/ + if(__HAL_ADC_GET_IT_SOURCE(hadc, ADC_IE_EOCIE)) + { + if((Status & ADC_SR_EOC) == ADC_SR_EOC) + { + /* Conversion complete callback */ + if (NULL != hadc->ConvCpltCallback) + hadc->ConvCpltCallback(hadc); + + /* Clear conversion flag */ + __HAL_ADC_CLEAR_FLAG(hadc, ADC_SR_EOC); + } + } + + /************ Check Analog watchdog flags ************/ + if(__HAL_ADC_GET_IT_SOURCE(hadc, ADC_IE_AWDIE)) + { + if((Status & ADC_SR_AWD) == ADC_SR_AWD) + { + /* Level out of window callback */ + if (NULL != hadc->LevelOutOfWindowCallback) + hadc->LevelOutOfWindowCallback(hadc); + + /* Clear the ADC analog watchdog flag */ + __HAL_ADC_CLEAR_FLAG(hadc, ADC_SR_AWD); + } + } + + /************ Check End of Conversion flag for regular group ************/ + if(__HAL_ADC_GET_IT_SOURCE(hadc, ADC_IE_EOGIE)) + { + if((Status & ADC_SR_EOG) == ADC_SR_EOG) + { + if((__HAL_ADC_CHECK_TRIG_REGULAR(hadc, ADC_SOFTWARE_START)) && + (hadc->Init.ConConvMode == 0)) + { + /* Disable ADC end of conversion interrupt on group regular */ + __HAL_ADC_DISABLE_IT(hadc, ADC_IE_EOGIE); + } + + /* Conversion complete callback */ + if (NULL != hadc->GroupCpltCallback) + hadc->GroupCpltCallback(hadc); + + /* Clear regular group conversion flag */ + __HAL_ADC_CLEAR_FLAG(hadc, ADC_SR_EOG); + } + } +} + +/************************************************************************ + * function : HAL_ADC_MspInit + * Description: + * input : hadc : pointer to a ADC_HandleTypeDef structure that contains + * the configuration information for ADC module + * return : none + ************************************************************************/ +__weak void HAL_ADC_MspInit(ADC_HandleTypeDef* hadc) +{ + uint32_t i; + uint32_t ADC_Pin_Map[][3] = + { + { ADC_CHANNEL_0_EN, GPIOC, GPIO_PIN_5 }, + { ADC_CHANNEL_1_EN, GPIOA, GPIO_PIN_7 }, + { ADC_CHANNEL_2_EN, GPIOA, GPIO_PIN_5 }, + { ADC_CHANNEL_3_EN, GPIOA, GPIO_PIN_3 }, + { ADC_CHANNEL_4_EN, GPIOC, GPIO_PIN_3 }, + { ADC_CHANNEL_5_EN, GPIOC, GPIO_PIN_1 }, + { ADC_CHANNEL_6_EN, GPIOA, GPIO_PIN_0 }, + { ADC_CHANNEL_8_EN, GPIOC, GPIO_PIN_4 }, + { ADC_CHANNEL_9_EN, GPIOA, GPIO_PIN_6 }, + { ADC_CHANNEL_10_EN, GPIOA, GPIO_PIN_4 }, + { ADC_CHANNEL_11_EN, GPIOA, GPIO_PIN_2 }, + { ADC_CHANNEL_12_EN, GPIOC, GPIO_PIN_2 }, + { ADC_CHANNEL_13_EN, GPIOC, GPIO_PIN_0 }, + { ADC_CHANNEL_VBAT_EN, GPIOA, GPIO_PIN_1 }, + { ADC_CHANNEL_EXT2_EN, GPIOB, GPIO_PIN_1 }, + { ADC_CHANNEL_EXT3_EN, GPIOB, GPIO_PIN_2 }, + { 0xffffffff, 0 }, //结束标志 + }; + /* + NOTE : This function should be modified by the user. + */ + + /* For Example */ + GPIO_InitTypeDef GPIO_Handle; + + //Set gpio to analog. + for(i = 0; ADC_Pin_Map[i][0] != 0xffffffff; i++) + { + if(hadc->Init.ChannelEn & ADC_Pin_Map[i][0]) + { + GPIO_Handle.Pin = ADC_Pin_Map[i][2]; + GPIO_Handle.Mode = GPIO_MODE_ANALOG; + GPIO_Handle.Pull = GPIO_NOPULL; + HAL_GPIO_Init(ADC_Pin_Map[i][1], &GPIO_Handle); + } + } + + /* Enable ADC Clock */ + System_Module_Enable(EN_ADC); + + /* Clear Pending Interrupt */ + NVIC_ClearPendingIRQ(ADC_IRQn); + + /* Enable External Interrupt */ + NVIC_EnableIRQ(ADC_IRQn); +} + +/************************************************************************ + * function : HAL_ADC_MspDeInit + * Description: + * input : hadc : pointer to a ADC_HandleTypeDef structure that contains + * the configuration information for ADC module + * return : none + ************************************************************************/ +__weak void HAL_ADC_MspDeInit(ADC_HandleTypeDef* hadc) +{ + /* + NOTE : This function should be modified by the user. + */ + + /* For Example */ + if(hadc->Init.DMAMode) + { + HAL_DMA_DeInit(hadc->DMA_Handle); + + hadc->DMA_Handle = NULL; + } + + /* Disable ADC Clock */ + System_Module_Disable(EN_ADC); + + /* Clear Pending Interrupt */ + NVIC_ClearPendingIRQ(ADC_IRQn); + + /* Disable External Interrupt */ + NVIC_DisableIRQ(ADC_IRQn); +} + +/************************************************************************ + * function : HAL_ADC_Init + * Description: Init the ADC module + * input : hadc : pointer to a ADC_HandleTypeDef structure that contains + * the configuration information for ADC module + * return : HAL_StatusTypeDef + ************************************************************************/ +HAL_StatusTypeDef HAL_ADC_Init(ADC_HandleTypeDef* hadc) +{ + /* Check the ADC handle allocation */ + if (hadc == NULL) + { + return HAL_ERROR; + } + + /* Check the parameters */ + if(!IS_ADC_ALL_INSTANCE(hadc->Instance)) return HAL_ERROR; + if(!IS_ADC_ALL_CONCONVMODE(hadc->Init.ConConvMode)) return HAL_ERROR; + if(!IS_ADC_ALL_JCHANNELMODE(hadc->Init.JChannelMode)) return HAL_ERROR; + if(!IS_ADC_ALL_DIFFMODE(hadc->Init.DiffMode)) return HAL_ERROR; + if(!IS_ADC_ALL_DMAMODE(hadc->Init.DMAMode)) return HAL_ERROR; + if(!IS_ADC_ALL_OVERMODE(hadc->Init.OverMode)) return HAL_ERROR; + if(!IS_ADC_ALL_OVERSAMPMODE(hadc->Init.OverSampMode)) return HAL_ERROR; + if(!IS_ADC_ALL_OVSR(hadc->Init.Oversampling.Ratio)) return HAL_ERROR; + if(!IS_ADC_ALL_OVSS(hadc->Init.Oversampling.RightBitShift)) return HAL_ERROR; + if(!IS_ADC_ALL_ANALOGWDGEN(hadc->Init.AnalogWDGEn)) return HAL_ERROR; + if(!IS_ADC_ALL_CLOCKDIV(hadc->Init.ClockDiv)) return HAL_ERROR; + if(!IS_ADC_ALL_CHANNELEN(hadc->Init.ChannelEn)) return HAL_ERROR; + if(!IS_ADC_ALL_TRIG(hadc->Init.ExTrigMode.ExTrigSel)) return HAL_ERROR; + if(!IS_ADC_ALL_CHANNELEN(hadc->Init.ExTrigMode.JExTrigSel)) return HAL_ERROR; + + /* Init the low level hardware : GPIO, CLOCK, NVIC, DMA */ + HAL_ADC_MspInit(hadc); + + //Reset AFE. + SET_BIT(hadc->Instance->CR2,ADC_CR2_AFE_RSTN); + //Set Clock DIV. + MODIFY_REG(hadc->Instance->CR2,ADC_CR2_DIV_MASK,hadc->Init.ClockDiv<Init.ConConvMode) + SET_BIT(hadc->Instance->CR1,ADC_CR1_CONT); + else + CLEAR_BIT(hadc->Instance->CR1,ADC_CR1_CONT); + + //Overflow + if(hadc->Init.OverMode == ADC_OVERMODE_ENABLE) + SET_BIT(hadc->Instance->CR2,ADC_CR2_OVRMOD); + else + CLEAR_BIT(hadc->Instance->CR2,ADC_CR2_OVRMOD); + + //Over Sample Set + if(hadc->Init.OverSampMode) + { + if(hadc->Init.JChannelMode) + { + SET_BIT(hadc->Instance->CR2,ADC_CR2_JOVSE); // Inject channel over sample en. + if(hadc->Init.Oversampling.TriggeredMode) + SET_BIT(hadc->Instance->CR2,ADC_CR2_JTOVS); // N times sample every trig. + else + CLEAR_BIT(hadc->Instance->CR2,ADC_CR2_JTOVS); // 1 time sample every trig. + } + + MODIFY_REG(hadc->Instance->CR2,ADC_CR2_OVSR_MASK,hadc->Init.Oversampling.Ratio<Instance->CR2,ADC_CR2_OVSS_MASK,hadc->Init.Oversampling.RightBitShift<Instance->CR2,ADC_CR2_OVSE); // Regular channel over sample en. + } + + //ExTrigSel set + MODIFY_REG(hadc->Instance->CR1,ADC_CR1_EXTSEL_MASK,hadc->Init.ExTrigMode.ExTrigSel<Init.JChannelMode) + { + /* Enable the inject channel */ + SET_BIT(hadc->Instance->CR1, ADC_CR1_JEN); + //JExTrigSel set + MODIFY_REG(hadc->Instance->CR1,ADC_CR1_JEXTSEL_MASK,hadc->Init.ExTrigMode.JExTrigSel<Instance->SQR1,ADC_SQR1_L); //Clear the sequence length. + + return HAL_OK; +} + +/************************************************************************ + * function : HAL_ADC_DeInit + * Description: DeInit the ADC module + * input : hadc : pointer to a ADC_HandleTypeDef structure that contains + * the configuration information for ADC module + * return : HAL_StatusTypeDef + ************************************************************************/ +HAL_StatusTypeDef HAL_ADC_DeInit(ADC_HandleTypeDef* hadc) +{ + /* Check the ADC handle allocation */ + if (hadc == NULL) + { + return HAL_ERROR; + } + + HAL_ADC_MspDeInit(hadc); + + hadc->ChannelNum = 0; + hadc->ConvCpltCallback = NULL; + hadc->InjectedConvCpltCallback = NULL; + hadc->LevelOutOfWindowCallback = NULL; + memset(&hadc->Init, 0, sizeof(hadc->Init)); + + return HAL_OK; +} + +/************************************************************************ + * function : HAL_ADC_ConfigChannel + * Description: Config the regular channel + * input : hadc : pointer to a ADC_HandleTypeDef structure that contains + * the configuration information for ADC module + * sConfig : pointer to a ADC_ChannelConfTypeDef structure that contains + * the configuration information for ADC channel + * return : HAL_StatusTypeDef + ************************************************************************/ +HAL_StatusTypeDef HAL_ADC_ConfigChannel(ADC_HandleTypeDef* hadc, ADC_ChannelConfTypeDef* sConfig) +{ + if(!IS_ADC_ALL_INSTANCE(hadc->Instance)) return HAL_ERROR; + if(!IS_ADC_ALL_CHANNEL(sConfig->Channel)) return HAL_ERROR; + if(!IS_ADC_ALL_SMPCLOCK(sConfig->Smp)) return HAL_ERROR; + if(!IS_ADC_ALL_SEQUENCE(sConfig->Sq)) return HAL_ERROR; + + /* Differential mode set*/ + if(hadc->Init.DiffMode) + { + if(sConfig->Channel < 8) + { + SET_BIT(hadc->Instance->DIFF,1<Channel); + SET_BIT(hadc->Instance->SIGN,1<Channel); //If define differential mode ,set as sign resault + } + else + return HAL_ERROR; + } + else if(sConfig->Channel < 8) + { + CLEAR_BIT(hadc->Instance->DIFF,1<Channel); + CLEAR_BIT(hadc->Instance->SIGN,1<Channel); //If define differential mode ,set as unsign resault + } + + if((sConfig->Channel >= 8) && (hadc->Instance->DIFF & (1<<(sConfig->Channel-8)))) return HAL_ERROR; + + if(sConfig->RjMode == 0) + { + if((sConfig->Sq >= 1)&&(sConfig->Sq <= 5)) + MODIFY_REG(hadc->Instance->SQR1,(ADC_CH_MASK << (5*sConfig->Sq )),(sConfig->Channel << (5*sConfig->Sq ))); + else if((sConfig->Sq >= 6)&&(sConfig->Sq <= 11)) + MODIFY_REG(hadc->Instance->SQR2,(ADC_CH_MASK << (5*(sConfig->Sq-6))),(sConfig->Channel << (5*(sConfig->Sq-6)))); + else if((sConfig->Sq >= 12)&&(sConfig->Sq <= 16)) + MODIFY_REG(hadc->Instance->SQR3,(ADC_CH_MASK << (5*(sConfig->Sq-12))),(sConfig->Channel << (5*(sConfig->Sq-12)))); + else + return HAL_ERROR; + } + else + { + /* Inject channel */ + MODIFY_REG(hadc->Instance->JSQR,ADC_CH_MASK,sConfig->Channel); + } + + MODIFY_REG(hadc->Instance->SQR1,ADC_SQR1_L,(ADC_Handle.ChannelNum-1)); + + /* Set the SMPR to every register*/ + if(sConfig->Channel <= ADC_CHANNEL_7) + MODIFY_REG(hadc->Instance->SMPR1,(ADC_SMPR_CH_MASK << (4*sConfig->Channel )),(sConfig->Smp << (4*sConfig->Channel ))); + else if((sConfig->Channel >= ADC_CHANNEL_8)&&(sConfig->Channel <= ADC_CHANNEL_15)) + MODIFY_REG(hadc->Instance->SMPR2,(ADC_SMPR_CH_MASK << (4*(sConfig->Channel-8))),(sConfig->Smp << (4*(sConfig->Channel-8)))); + else if((sConfig->Channel >= ADC_CHANNEL_TEMP)&&(sConfig->Channel <= ADC_CHANNEL_EXT3)) + MODIFY_REG(hadc->Instance->SMPR3,(ADC_SMPR_CH_MASK << (4*(sConfig->Channel-16))),(sConfig->Smp << (4*(sConfig->Channel-16)))); + else + return HAL_ERROR; + + if(hadc->Init.ChannelEn & ADC_CHANNEL_TEMP_EN) + { + SET_BIT(hadc->Instance->TSREF,ADC_TSREF_EN_TS);//Enable the temperature sensor + System_Delay(1000); + } + + if(hadc->Init.ChannelEn & (ADC_CHANNEL_VBGR_EN | ADC_CHANNEL_EXT2_EN | ADC_CHANNEL_EXT3_EN)) + { + SET_BIT(hadc->Instance->CR2,ADC_CR2_EN_BUF);//Enable the buffer + System_Delay(1000); + } + + return HAL_OK; +} + +/************************************************************************ + * function : HAL_ADC_AnalogWDGConfig + * Description: Config the analog watchdog + * input : hadc : pointer to a ADC_HandleTypeDef structure that contains + * the configuration information for ADC module + * AnalogWDGConfig : pointer to a ADC_AnalogWDGConfTypeDef structure that contains + * the configuration information for ADC analog watchdog + * return : HAL_StatusTypeDef + ************************************************************************/ +HAL_StatusTypeDef HAL_ADC_AnalogWDGConfig(ADC_HandleTypeDef* hadc, ADC_AnalogWDGConfTypeDef* AnalogWDGConfig) +{ + if(!IS_ADC_ALL_INSTANCE(hadc->Instance)) return HAL_ERROR; + if(!IS_ADC_ALL_CHANNEL(AnalogWDGConfig->Channel)) return HAL_ERROR; + + if (hadc->Init.AnalogWDGEn) + { + switch(AnalogWDGConfig->WatchdogMode) + { + /* AWDSGL:0; AWDEN:1; JAWDEN:0 */ + case ADC_ANALOGWATCHDOG_RCH_ALL: + CLEAR_BIT(hadc->Instance->CR1,ADC_CR1_AWDSGL); + SET_BIT(hadc->Instance->CR1,ADC_CR1_AWDEN); + CLEAR_BIT(hadc->Instance->CR1,ADC_CR1_JAWDEN); + break; + /* AWDSGL:0; AWDEN:0; JAWDEN:1 */ + case ADC_ANALOGWATCHDOG_JCH_ALL: + CLEAR_BIT(hadc->Instance->CR1,ADC_CR1_AWDSGL); + CLEAR_BIT(hadc->Instance->CR1,ADC_CR1_AWDEN); + SET_BIT(hadc->Instance->CR1,ADC_CR1_JAWDEN); + break; + /* AWDSGL:0; AWDEN:1; JAWDEN:1 */ + case ADC_ANALOGWATCHDOG_RCH_AND_JCH_ALL: + CLEAR_BIT(hadc->Instance->CR1,ADC_CR1_AWDSGL); + SET_BIT(hadc->Instance->CR1,ADC_CR1_AWDEN); + SET_BIT(hadc->Instance->CR1,ADC_CR1_JAWDEN); + break; + /* AWDSGL:1; AWDEN:1; JAWDEN:0 */ + case ADC_ANALOGWATCHDOG_RCH_SINGLE: + SET_BIT(hadc->Instance->CR1,ADC_CR1_AWDSGL); + SET_BIT(hadc->Instance->CR1,ADC_CR1_AWDEN); + CLEAR_BIT(hadc->Instance->CR1,ADC_CR1_JAWDEN); + MODIFY_REG(hadc->Instance->CR1,ADC_CH_MASK,AnalogWDGConfig->Channel); //The regular watchdog channel set + break; + /* AWDSGL:1; AWDEN:0; JAWDEN:1 */ + case ADC_ANALOGWATCHDOG_JCH_SINGLE: + SET_BIT(hadc->Instance->CR1,ADC_CR1_AWDSGL); + CLEAR_BIT(hadc->Instance->CR1,ADC_CR1_AWDEN); + SET_BIT(hadc->Instance->CR1,ADC_CR1_JAWDEN); + MODIFY_REG(hadc->Instance->CR1,(ADC_CH_MASK<<27),AnalogWDGConfig->Channel<<27); //The inject watchdog channel set + break; + /* AWDSGL:1; AWDEN:1; JAWDEN:1 */ + case ADC_ANALOGWATCHDOG_RCH_OR_JCH_SINGLE: + SET_BIT(hadc->Instance->CR1,ADC_CR1_AWDSGL); + SET_BIT(hadc->Instance->CR1,ADC_CR1_AWDEN); + SET_BIT(hadc->Instance->CR1,ADC_CR1_JAWDEN); + MODIFY_REG(hadc->Instance->CR1,ADC_CH_MASK,AnalogWDGConfig->Channel); //The regular watchdog channel set + MODIFY_REG(hadc->Instance->CR1,(ADC_CH_MASK<<27),AnalogWDGConfig->Channel<<27); //The inject watchdog channel set + break; + + /* AWDSGL:x; AWDEN:0; JAWDEN:0 */ + default: /* ADC_ANALOGWATCHDOG_NONE */ + CLEAR_BIT(hadc->Instance->CR1,ADC_CR1_AWDEN); + CLEAR_BIT(hadc->Instance->CR1,ADC_CR1_JAWDEN); + break; + } + + /* Configure ADC analog watchdog interrupt */ + if(AnalogWDGConfig->ITMode) + __HAL_ADC_ENABLE_IT(hadc,ADC_IE_AWDIE); + else + __HAL_ADC_DISABLE_IT(hadc,ADC_IE_AWDIE); + } + + if(hadc->Init.DiffMode) + { + hadc->Instance->HTR = AnalogWDGConfig->HighThreshold<<16; + hadc->Instance->LTR = AnalogWDGConfig->LowThreshold<<16; + } + else + { + hadc->Instance->HTR = AnalogWDGConfig->HighThreshold; + hadc->Instance->LTR = AnalogWDGConfig->LowThreshold; + } + /* Return function status */ + return HAL_OK; +} + +/************************************************************************ + * function : HAL_ADC_Start + * Description: Enable and start the ADC convertion + * input : hadc : pointer to a ADC_HandleTypeDef structure that contains + * the configuration information for ADC module + * return : HAL_StatusTypeDef + ************************************************************************/ +HAL_StatusTypeDef HAL_ADC_Start(ADC_HandleTypeDef* hadc) +{ + /* Check the parameters */ + if(!IS_ADC_ALL_INSTANCE(hadc->Instance)) return HAL_ERROR; + + /* check the total number of the enabled channels */ + if((READ_BIT(hadc->Instance->SQR1,ADC_SQR1_L)+1) != hadc->ChannelNum) return HAL_ERROR; + + /* Enable the ADC */ + __HAL_ADC_ENABLE(hadc); + + /* Clear the SR register */ + __HAL_ADC_CLEAR_FLAG(hadc,ADC_SR_AWD | ADC_SR_OVERF | ADC_SR_EOG | ADC_SR_JEOC | ADC_SR_EOC | ADC_SR_ADRDY); + + /* Wait ADC ready */ + while(!(hadc->Instance->SR & ADC_SR_ADRDY)); + + if(__HAL_ADC_CHECK_TRIG_REGULAR(hadc, ADC_SOFTWARE_START)) + { + /* Start covertion */ + SET_BIT(hadc->Instance->CR1,ADC_CR1_SWSTART); + } + + /* Return function status */ + return HAL_OK; +} + +/************************************************************************ + * function : HAL_ADC_Stop + * Description: Stop ADC conversion of regular group (and injected channels in + * case of auto_injection mode), disable ADC peripheral. + * input : hadc : pointer to a ADC_HandleTypeDef structure that contains + * the configuration information for ADC module + * return : HAL_StatusTypeDef + ************************************************************************/ +HAL_StatusTypeDef HAL_ADC_Stop(ADC_HandleTypeDef* hadc) +{ + /* Check the parameters */ + if(!IS_ADC_ALL_INSTANCE(hadc->Instance)) return HAL_ERROR; + + if(hadc->Init.ConConvMode) + { + /* Set stop flag */ + SET_BIT(hadc->Instance->CR2, ADC_CR2_ADC_STP); + /* Waitting stop flag be cleared */ + while(READ_BIT(hadc->Instance->CR2, ADC_CR2_ADC_STP)); + } + + /* Disable the ADC peripheral */ + __HAL_ADC_DISABLE(hadc); + + /* Clear the SR register */ + __HAL_ADC_CLEAR_FLAG(hadc,ADC_SR_AWD | ADC_SR_OVERF | ADC_SR_EOG | ADC_SR_JEOC | ADC_SR_EOC | ADC_SR_ADRDY); + + /* Return function status */ + return HAL_OK; +} + +/************************************************************************ + * function : HAL_ADC_Start_IT + * Description: Enable ADC, start conversion of regular group with interruption. + * input : hadc : pointer to a ADC_HandleTypeDef structure that contains + * the configuration information for ADC module + * return : HAL_StatusTypeDef + ************************************************************************/ +HAL_StatusTypeDef HAL_ADC_Start_IT(ADC_HandleTypeDef* hadc) +{ + /* Check the parameters */ + if(!IS_ADC_ALL_INSTANCE(hadc->Instance)) return HAL_ERROR; + + /* Enable the ADC */ + __HAL_ADC_ENABLE(hadc); + + /* Clear the SR register */ + __HAL_ADC_CLEAR_FLAG(hadc,ADC_SR_AWD | ADC_SR_OVERF | ADC_SR_EOG | ADC_SR_JEOC | ADC_SR_EOC | ADC_SR_ADRDY); + + /* Disable all interruptions before enabling the desired ones */ + __HAL_ADC_DISABLE_IT(hadc, ADC_IE_EOCIE | ADC_IE_EOGIE | ADC_IE_OVERFIE | ADC_IE_JEOCIE); + + __HAL_ADC_ENABLE_IT(hadc, ADC_IE_EOCIE | ADC_IE_EOGIE); + + + /* Enable ADC overrun interrupt */ + /* If hadc->Init.OverMode is set to ADC_OVERMODE_DISABLE, only then is + ADC_IE_OVERFIE enabled; otherwise data overwrite is considered as normal + behavior and no CPU time is lost for a non-processed interruption */ + if (hadc->Init.OverMode == ADC_OVERMODE_DISABLE) + { + __HAL_ADC_ENABLE_IT(hadc, ADC_IE_OVERFIE); + } + + if(__HAL_ADC_CHECK_TRIG_REGULAR(hadc, ADC_SOFTWARE_START)) + { + /* Start covertion */ + SET_BIT(hadc->Instance->CR1,ADC_CR1_SWSTART); + } + + /* Return function status */ + return HAL_OK; +} + +/************************************************************************ + * function : HAL_ADC_Stop_IT + * Description: Stop ADC conversion of regular group (and injected group in + * case of auto_injection mode), disable interrution of + * end-of-conversion, disable ADC peripheral. + * input : hadc : pointer to a ADC_HandleTypeDef structure that contains + * the configuration information for ADC module + * return : HAL_StatusTypeDef + ************************************************************************/ +HAL_StatusTypeDef HAL_ADC_Stop_IT(ADC_HandleTypeDef* hadc) +{ + /* Check the parameters */ + if(!IS_ADC_ALL_INSTANCE(hadc->Instance)) return HAL_ERROR; + + if(hadc->Init.ConConvMode) + { + /* Set stop flag */ + SET_BIT(hadc->Instance->CR2, ADC_CR2_ADC_STP); + /* Waitting stop flag be cleared */ + while(READ_BIT(hadc->Instance->CR2, ADC_CR2_ADC_STP)); + } + + /* Disable the ADC peripheral */ + __HAL_ADC_DISABLE(hadc); + + /* Disable all interruptions before enabling the desired ones */ + __HAL_ADC_DISABLE_IT(hadc, ADC_IE_EOCIE | ADC_IE_EOGIE | ADC_IE_OVERFIE | ADC_IE_JEOCIE); + + /* Clear the SR register */ + __HAL_ADC_CLEAR_FLAG(hadc,ADC_SR_AWD | ADC_SR_OVERF | ADC_SR_EOG | ADC_SR_JEOC | ADC_SR_EOC | ADC_SR_ADRDY); + + /* Return function status */ + return HAL_OK; +} + +/************************************************************************ + * function : HAL_ADC_Start_DMA + * Description: Enable ADC, start conversion of regular group and transfer result through DMA. + * input : hadc : pointer to a ADC_HandleTypeDef structure that contains + * the configuration information for ADC module + * : pData : Destination Buffer address. + * : Length : Number of data to be transferred from ADC peripheral to memory. + * return : HAL_StatusTypeDef + ************************************************************************/ +HAL_StatusTypeDef HAL_ADC_Start_DMA(ADC_HandleTypeDef* hadc, uint32_t* pData, uint32_t Length) +{ + HAL_StatusTypeDef tmp_hal_status; + + /* Check the parameters */ + if(!IS_ADC_ALL_INSTANCE(hadc->Instance)) return HAL_ERROR; + + /* Specific case for first call occurrence of this function (DMA transfer */ + /* not activated and ADC disabled), DMA transfer must be activated */ + /* with ADC disabled. */ + if (READ_BIT(hadc->Instance->CR1,ADC_CR1_DMA) == 0UL) + { + if(READ_BIT(hadc->Instance->CR2, ADC_CR2_ADC_EN)) + { + /* Disable ADC */ + __HAL_ADC_DISABLE(hadc); + } + + /* Enable ADC DMA mode */ + SET_BIT(hadc->Instance->CR1,ADC_CR1_DMA); + } + + /* Enable the ADC peripheral */ + __HAL_ADC_ENABLE(hadc); + + /* Clear the SR register */ + __HAL_ADC_CLEAR_FLAG(hadc,ADC_SR_AWD | ADC_SR_OVERF | ADC_SR_EOG | ADC_SR_JEOC | ADC_SR_EOC | ADC_SR_ADRDY); + + /* Disable all interruptions before enabling the desired ones */ + __HAL_ADC_DISABLE_IT(hadc, ADC_IE_EOCIE | ADC_IE_EOGIE | ADC_IE_OVERFIE | ADC_IE_JEOCIE); + + /* Start the DMA channel */ + tmp_hal_status = HAL_DMA_Start_IT(hadc->DMA_Handle, (uint32_t)&hadc->Instance->DR, (uint32_t)pData, Length); + + /* Enable conversion of regular group. */ + /* If software start has been selected, conversion starts immediately. */ + /* If external trigger has been selected, conversion will start at next */ + /* trigger event. */ + + /* Start ADC group regular conversion */ + if(__HAL_ADC_CHECK_TRIG_REGULAR(hadc, ADC_SOFTWARE_START)) + { + /* Start covertion */ + SET_BIT(hadc->Instance->CR1,ADC_CR1_SWSTART); + } + + /* Return function status */ + return tmp_hal_status; +} + +/************************************************************************ + * function : HAL_ADC_Stop_DMA + * Description: Stop ADC conversion of regular group (and injected group in + * case of auto_injection mode), disable ADC DMA transfer, disable + * ADC peripheral. + * input : hadc : pointer to a ADC_HandleTypeDef structure that contains + * the configuration information for ADC module + * return : HAL_StatusTypeDef + ************************************************************************/ +HAL_StatusTypeDef HAL_ADC_Stop_DMA(ADC_HandleTypeDef* hadc) +{ + /* Check the parameters */ + if(!IS_ADC_ALL_INSTANCE(hadc->Instance)) return HAL_ERROR; + + if(hadc->Init.ConConvMode) + { + /* Set stop flag */ + SET_BIT(hadc->Instance->CR2, ADC_CR2_ADC_STP); + /* Waitting stop flag be cleared */ + while(READ_BIT(hadc->Instance->CR2, ADC_CR2_ADC_STP)); + } + + /* Waitting stop flag be cleared */ + while(READ_BIT(hadc->Instance->CR2, ADC_CR2_ADC_STP)); + + /* Disable the DMA channel (in case of DMA in circular mode or stop */ + /* while DMA transfer is on going) */ + HAL_DMA_Abort(hadc->DMA_Handle); + + /* Disable ADC overrun interrupt */ + __HAL_ADC_DISABLE_IT(hadc, ADC_IE_OVERFIE); + + /* 2. Disable the ADC peripheral */ + /* Update "tmp_hal_status" only if DMA channel disabling passed, to keep */ + /* in memory a potential failing status. */ + + /* Disable the ADC peripheral */ + __HAL_ADC_DISABLE(hadc); + + /* Disable all interruptions before enabling the desired ones */ + __HAL_ADC_DISABLE_IT(hadc, ADC_IE_EOCIE | ADC_IE_EOGIE | ADC_IE_OVERFIE | ADC_IE_JEOCIE); + + /* Clear the SR register */ + __HAL_ADC_CLEAR_FLAG(hadc,ADC_SR_AWD | ADC_SR_OVERF | ADC_SR_EOG | ADC_SR_JEOC | ADC_SR_EOC | ADC_SR_ADRDY); + + /* Disable ADC DMA (ADC DMA configuration of continuous requests is kept) */ + CLEAR_BIT(hadc->Instance->CR1,ADC_CR1_DMA); + + /* Return function status */ + return HAL_OK; +} + +/************************************************************************ + * function : HAL_ADC_GetValue + * Description: ADC retrieve conversion value intended to be used with polling or interruption + * input : hadc : pointer to a ADC_HandleTypeDef structure that contains + * the configuration information for ADC module + * return : uint32_t the ADC covert result. + ************************************************************************/ +uint32_t HAL_ADC_GetValue(ADC_HandleTypeDef *hadc) +{ + /* Check the parameters */ + if(!IS_ADC_ALL_INSTANCE(hadc->Instance)) return HAL_ERROR; + + return (hadc->Instance->DR); +} + +/************************************************************************ + * function : HAL_ADC_PollForEvent + * Description: Poll for ADC event. + * input : hadc : pointer to a ADC_HandleTypeDef structure that contains + * the configuration information for ADC module + * : EventType: the ADC event type. can be ：ADC_SR_AWD,ADC_SR_OVERF,ADC_SR_EOG,ADC_SR_JEOC,ADC_SR_EOC + * : Timeout : Polling timeout. + * return : HAL_StatusTypeDef + ************************************************************************/ +HAL_StatusTypeDef HAL_ADC_PollForEvent(ADC_HandleTypeDef *hadc, uint32_t EventType, uint32_t Timeout) +{ + __IO uint32_t uiTimeout; + + /* Check the parameters */ + if(!IS_ADC_ALL_INSTANCE(hadc->Instance)) return HAL_ERROR; + if(!IS_ADC_EVENT_TYPE(EventType)) return HAL_ERROR; + + uiTimeout = Timeout; + /* Check selected event flag */ + while (__HAL_ADC_GET_FLAG(hadc, EventType) == 0UL) + { + /* Check if timeout is disabled (set to infinite wait) */ + if(uiTimeout) + { + uiTimeout--; + if(uiTimeout == 0) + return HAL_TIMEOUT; + } + } + + if(EventType == ADC_SR_OVERF) + { + __HAL_ADC_CLEAR_FLAG(hadc, ADC_SR_OVERF); + if (hadc->Init.OverMode == ADC_OVERMODE_ENABLE) + { + /* Clear ADC Overrun flag only if Overrun is set to ADC_OVERMODE_ENABLE(Over written) */ + return HAL_ERROR; + } + } + else + { + __HAL_ADC_CLEAR_FLAG(hadc, EventType); + } + + /* Return function status */ + return HAL_OK; +} + +/************************************************************************ + * function : HAL_ADC_InjectedStart_IT + * Description: Enable ADC, start conversion of injected channel with interruption. + * input : hadc : pointer to a ADC_HandleTypeDef structure that contains + * the configuration information for ADC module + * return : HAL_StatusTypeDef + ************************************************************************/ +HAL_StatusTypeDef HAL_ADC_InjectedStart_IT(ADC_HandleTypeDef* hadc) +{ + /* Check the parameters */ + if(!IS_ADC_ALL_INSTANCE(hadc->Instance)) return HAL_ERROR; + + /* Clear the SR register */ + __HAL_ADC_CLEAR_FLAG(hadc, ADC_SR_JEOC); + + __HAL_ADC_ENABLE_IT(hadc, ADC_IE_JEOCIE); + + /* Enable ADC overrun interrupt */ + /* If hadc->Init.OverMode is set to ADC_OVERMODE_DISABLE, only then is + ADC_IE_OVERFIE enabled; otherwise data overwrite is considered as normal + behavior and no CPU time is lost for a non-processed interruption */ + if (hadc->Init.OverMode == ADC_OVERMODE_DISABLE) + { + __HAL_ADC_ENABLE_IT(hadc, ADC_IE_OVERFIE); + } + + if(__HAL_ADC_CHECK_TRIG_INJECTED(hadc, ADC_SOFTWARE_START)) + { + /* Start covertion */ + SET_BIT(hadc->Instance->CR1,ADC_CR1_JSWSTART); + } + + /* Return function status */ + return HAL_OK; +} + +/************************************************************************ + * function : HAL_ADC_InjectedStop_IT + * Description: Stop ADC conversion of injected channel, disable interrution of + * end-of-conversion, disable ADC peripheral. + * input : hadc : pointer to a ADC_HandleTypeDef structure that contains + * the configuration information for ADC module + * return : HAL_StatusTypeDef + ************************************************************************/ +HAL_StatusTypeDef HAL_ADC_InjectedStop_IT(ADC_HandleTypeDef* hadc) +{ + /* Return function status */ + return (HAL_ADC_Stop_IT(hadc)); +} + +/************************************************************************ + * function : HAL_ADC_InjectedGetValue + * Description: ADC retrieve injected channel conversion value intended to be used with polling or interruption + * input : hadc : pointer to a ADC_HandleTypeDef structure that contains + * the configuration information for ADC module + * return : uint32_t the ADC covert result. + ************************************************************************/ +uint32_t HAL_ADC_InjectedGetValue(ADC_HandleTypeDef *hadc) +{ + /* Check the parameters */ + if(!IS_ADC_ALL_INSTANCE(hadc->Instance)) return HAL_ERROR; + + return (hadc->Instance->JDR); +} + +/************************************************************************ + * function : HAL_ADC_Polling + * Description: Polling to get the results of the ADC converter. + * input : hadc : pointer to a ADC_HandleTypeDef structure that contains + * the configuration information for ADC module + * : pData : Destination Buffer address. + * : Length : Number of data to be transferred from ADC peripheral to memory. + * : Timeout : Polling timeout. + * return : HAL_StatusTypeDef + ************************************************************************/ +HAL_StatusTypeDef HAL_ADC_Polling(ADC_HandleTypeDef* hadc, uint32_t* pData, uint32_t Length, uint32_t Timeout) +{ + uint32_t tmp_hal_status; + __IO uint32_t uiTimeout; + + if(HAL_ADC_Start(hadc) != HAL_OK) return HAL_ERROR; + if(!pData) return HAL_ERROR; + + hadc->AdcResults = pData; + uiTimeout = Timeout; + + while(Length) + { + tmp_hal_status = hadc->Instance->SR; + if(tmp_hal_status & ADC_SR_EOC) + { + *hadc->AdcResults = hadc->Instance->DR | HAL_ADC_EOC_FLAG; + __HAL_ADC_CLEAR_FLAG(hadc, ADC_SR_EOC); + + hadc->AdcResults++; + Length--; + } + if(tmp_hal_status & ADC_SR_JEOC) + { + *hadc->AdcResults = hadc->Instance->JDR | HAL_ADC_JEOC_FLAG; + __HAL_ADC_CLEAR_FLAG(hadc, ADC_SR_JEOC); + hadc->AdcResults++; + Length--; + } + if(tmp_hal_status & ADC_SR_OVERF) + { + __HAL_ADC_CLEAR_FLAG(hadc, ADC_SR_OVERF); + } + if(tmp_hal_status & ADC_SR_EOG) + { + __HAL_ADC_CLEAR_FLAG(hadc, ADC_SR_EOG); + break; + } + + if(uiTimeout) + { + uiTimeout--; + if(uiTimeout == 0) + return HAL_TIMEOUT; + } + } + + HAL_ADC_Stop(hadc); + + return HAL_OK; +} diff --git a/bsp/acm32f4xx-nucleo/libraries/HAL_Driver/Src/HAL_CAN.c b/bsp/acm32f4xx-nucleo/libraries/HAL_Driver/Src/HAL_CAN.c new file mode 100644 index 0000000000..972eb8bcb2 --- /dev/null +++ b/bsp/acm32f4xx-nucleo/libraries/HAL_Driver/Src/HAL_CAN.c @@ -0,0 +1,732 @@ +/* + ****************************************************************************** + * @file HAL_Can.c + * @version V1.0.0 + * @date 2020 + * @brief CAN HAL module driver. + * This file provides firmware functions to manage the following + * functionalities of the Universal Asynchronous Receiver Transmitter Peripheral (CAN). + * @ Initialization and de-initialization functions + * @ IO operation functions + * @ Peripheral Control functions + ****************************************************************************** +*/ +#include "ACM32Fxx_HAL.h" + +/********************************************************************************* +* Function : HAL_CAN_OperatingModeRequest +* Description : Select the CAN Operation mode. +* Input : hcan : pointer to a CAN_HandleTypeDef structure that contains +* the configuration information for CAN module +* Input : CAN_OperatingMode:CAN Operating Mode. This parameter can be one of @ref CAN_OperatingMode enumeration. +* Output : HAL status +* Author : CWT Data : 2020 +**********************************************************************************/ +HAL_StatusTypeDef HAL_CAN_OperatingModeRequest(CAN_HandleTypeDef *hcan, uint8_t CAN_OperatingMode) +{ + uint8_t status = HAL_ERROR; + /* Check the parameters */ + if(!IS_CAN_ALL_PERIPH(hcan->Instance)) return HAL_ERROR; + if(!IS_CAN_OPERATING_MODE(CAN_OperatingMode)) return HAL_ERROR; + if (CAN_OperatingMode == CAN_OperatingMode_Initialization) + { + hcan->Instance->MOD |= CAN_OperatingMode_Initialization; // enter Initialization + if ((hcan->Instance->MOD & CAN_MOD_RM) != CAN_OperatingMode_Initialization) + { + status = HAL_ERROR; + } + else + { + status = HAL_OK; + } + } + else if(CAN_OperatingMode == CAN_OperatingMode_Normal) + { + hcan->Instance->MOD &=~ CAN_OperatingMode_Initialization; //1-->0 enter Normal + if ((hcan->Instance->MOD & CAN_MOD_RM) != CAN_OperatingMode_Normal) + { + status = HAL_ERROR; + } + else + { + status = HAL_OK; + } + } + else if (CAN_OperatingMode == CAN_OperatingMode_Sleep) + { + hcan->Instance->MOD |= CAN_OperatingMode_Sleep; // enter Normal + if ((hcan->Instance->MOD & CAN_MOD_SM) != CAN_OperatingMode_Sleep) + { + status = HAL_ERROR; + } + else + { + status = HAL_OK; + } + } + else if(CAN_OperatingMode == CAN_OperatingMode_Listen) + { + hcan->Instance->MOD |= CAN_OperatingMode_Listen; // enter Normal + if((hcan->Instance->MOD & CAN_MOD_LOM) != CAN_OperatingMode_Listen) + { + status = HAL_ERROR; + } + else + { + status = HAL_OK; + } + } + else + { + status = HAL_ERROR; + } + return (uint8_t) status; +} + + +/********************************************************************************* +* Function : HAL_CAN_MspInit +* Description : Initialize the CAN MSP. +* Input : hcan : pointer to a CAN_HandleTypeDef structure that contains +* the configuration information for CAN module +* Output : +* Author : CWT Data : 2020 +**********************************************************************************/ + +__weak void HAL_CAN_MspInit(CAN_HandleTypeDef *hcan) +{ + /* NOTE : This function should not be modified, when the callback is needed, + the HAL_UART_MspInit can be implemented in the user file + */ + /* For Example */ + GPIO_InitTypeDef GPIO_InitStruct; + if(hcan->Instance==CAN1) + { + /* Enable CAN clock */ + System_Module_Enable(EN_CAN1); + GPIO_InitTypeDef GPIO_InitStructure; + /* Initialization GPIO */ + /* PA11:Rx */ /* PA12:Tx */ + GPIO_InitStructure.Pin = GPIO_PIN_11|GPIO_PIN_12; + GPIO_InitStructure.Alternate=GPIO_FUNCTION_5; + GPIO_InitStructure.Pull=GPIO_PULLUP; + GPIO_InitStructure.Mode = GPIO_MODE_AF_PP; + HAL_GPIO_Init(GPIOA, &GPIO_InitStructure); + + } + else if(hcan->Instance==CAN2) + { + /* Enable CAN clock */ + System_Module_Enable(EN_CAN2); + GPIO_InitTypeDef GPIO_InitStructure; + /* Initialization GPIO */ + /* PB5:Rx */ /* PB6:Tx */ + GPIO_InitStructure.Pin = GPIO_PIN_5|GPIO_PIN_6; + GPIO_InitStructure.Alternate=GPIO_FUNCTION_5; + GPIO_InitStructure.Pull=GPIO_PULLUP; + GPIO_InitStructure.Mode = GPIO_MODE_AF_PP; + HAL_GPIO_Init(GPIOB, &GPIO_InitStructure); + + /* Enable the CAN Receive interrupt */ + hcan->Instance->IER |= CAN_IER_RIE; + NVIC_ClearPendingIRQ(CAN2_IRQn); + NVIC_SetPriority(CAN2_IRQn, 5); + NVIC_EnableIRQ(CAN2_IRQn); + } + +} +/********************************************************************************* +* Function : HAL_CAN_MspDeInit +* Description : CAN MSP De-Initialization +* This function frees the hardware resources used in this example: +* - Disable the Peripheral's clock +* - Revert GPIO configuration to their default state +* Input : hcan : pointer to a CAN_HandleTypeDef structure that contains +* the configuration information for CAN module +* Output : +* Author : CWT Data : 2020 +**********************************************************************************/ +void HAL_CAN_MspDeInit(CAN_HandleTypeDef *hcan) +{ + if(hcan->Instance==CAN1) + { + /* Reset CAN clock */ + System_Module_Disable(EN_CAN1); + GPIO_InitTypeDef GPIO_InitStructure; + /* Initialization GPIO */ + /* PA11:Rx */ /* PA12:Tx */ + HAL_GPIO_DeInit(GPIOA, GPIO_PIN_11); + HAL_GPIO_DeInit(GPIOA, GPIO_PIN_12); + } + else if(hcan->Instance==CAN2) + { + /* Reset CAN clock */ + System_Module_Disable(EN_CAN2); + GPIO_InitTypeDef GPIO_InitStructure; + /* Initialization GPIO */ + /* PB5:Rx */ /* PB6:Tx */ + HAL_GPIO_DeInit(GPIOB, GPIO_PIN_5); + HAL_GPIO_DeInit(GPIOB, GPIO_PIN_6); + } +} +/********************************************************************************* +* Function : HAL_CAN_Init +* Description : Initializes the CAN peripheral according to the specified parameters in the CAN_HandleTypeDef.. +* Input : hcan : pointer to a CAN_HandleTypeDef structure that contains +* the configuration information for CAN module +* Output : HAL status +* Author : CWT Data : 2020 +**********************************************************************************/ +HAL_StatusTypeDef HAL_CAN_Init(CAN_HandleTypeDef *hcan) +{ + uint8_t InitStatus = HAL_ERROR; + /* Check the parameters */ + if(!IS_CAN_ALL_PERIPH(hcan->Instance)) return HAL_ERROR; + if(!IS_CAN_MODE(hcan->Init.CAN_Mode)) return HAL_ERROR; + if(!IS_CAN_SJW(hcan->Init.CAN_SJW)) return HAL_ERROR; + if(!IS_CAN_TSEG1(hcan->Init.CAN_TSEG1)) return HAL_ERROR; + if(!IS_CAN_TSEG2(hcan->Init.CAN_TSEG2)) return HAL_ERROR; + if(!IS_CAN_BRP(hcan->Init.CAN_BRP)) return HAL_ERROR; + if(!IS_CAN_SAM(hcan->Init.CAN_SAM)) return HAL_ERROR; + /* Reset the CANx */ + if(hcan->Instance==CAN1) + { + System_Module_Reset(RST_CAN1); + } + else + { + System_Module_Reset(RST_CAN2); + } + HAL_CAN_MspInit(hcan); + HAL_CAN_OperatingModeRequest(hcan,CAN_OperatingMode_Initialization);//enter CAN_OperatingMode_Initialization + hcan->Instance->BTR0=0xff; + hcan->Instance->BTR0=(hcan->Init.CAN_SJW<<6)|(hcan->Init.CAN_BRP); + hcan->Instance->BTR1=(hcan->Init.CAN_SAM<<7)|(hcan->Init.CAN_TSEG2<<4)|(hcan->Init.CAN_TSEG1); + HAL_CAN_OperatingModeRequest(hcan,CAN_OperatingMode_Normal);//enter CAN_OperatingMode_Normal + return HAL_OK; +} + + +/********************************************************************************* +* Function : HAL_CAN_DeInit +* Description : Deinitializes the CAN peripheral registers to their default +* reset values. +* Input : hcan : pointer to a CAN_HandleTypeDef structure that contains +* the configuration information for CAN module +* Output : HAL status +* Author : CWT Data : 2020 +**********************************************************************************/ +HAL_StatusTypeDef HAL_CAN_DeInit(CAN_HandleTypeDef *hcan) +{ + /* Check CAN handle */ + if(!IS_CAN_ALL_PERIPH(hcan->Instance)) return HAL_ERROR; + + HAL_CAN_MspDeInit(hcan); + + /* Reset the CAN peripheral */ + SET_BIT(hcan->Instance->MOD, CAN_MOD_RM); + + /* Return function status */ + return HAL_OK; +} +/********************************************************************************* +* Function : HAL_CAN_Transmit +* Description : Initiates the transmission of a message. +* Input : hcan : pointer to a CAN_HandleTypeDef structure that contains +* the configuration information for CAN module +* Input : TxMessage : ppointer to a structure which contains CAN Id, CAN + * DLC and CAN data. +* Output : +* Author : CWT Data : 2020 +**********************************************************************************/ +HAL_StatusTypeDef HAL_CAN_Transmit(CAN_HandleTypeDef *hcan, CanTxRxMsg* TxMessage) +{ + uint8_t i = 0; + uint8_t can_id[4]; + uint32_t frame_header; + /* Check the parameters */ + if(!IS_CAN_ALL_PERIPH(hcan->Instance)) return HAL_ERROR ; + if(!IS_CAN_IDTYPE(TxMessage->IDE)) return HAL_ERROR; + if(!IS_CAN_RTR(TxMessage->RTR)) return HAL_ERROR; + if(!IS_CAN_DLC(TxMessage->DLC)) return HAL_ERROR; + /* Set up the DLC */ + frame_header =TxMessage->DLC & 0x0F; // standard data frame + /* Set up the Id */ + if(TxMessage->IDE==CAN_Id_Standard)//Standard ID + { + can_id[0] = TxMessage->StdId >>3; + can_id[1] = (TxMessage->StdId&0x07)<<5; + for(i=0;i<2;i++) + { + hcan->Instance->DF.DATABUF[1+i] = can_id[i]; + } + } + else//Id_Extended + { + can_id[0] = TxMessage->ExtId>>21; + can_id[1] = (TxMessage->ExtId&0x1FE000)>>13; + can_id[2] = (TxMessage->ExtId&0x1FE0)>>5; + can_id[3] = (TxMessage->ExtId&0x1F)<<3; + frame_header |= (CAN_Id_Extended<<7); // extended data frame + for(i=0;i<4;i++) + { + hcan->Instance->DF.DATABUF[1+i] = can_id[i]; + } + } + if(TxMessage->RTR==CAN_RTR_Data)//CAN_RTR_Data + { + frame_header&=~(CAN_RTR_Remote<<6); + for(i=0; iDLC; i++) + { + hcan->Instance->DF.DATABUF[3+(TxMessage->IDE*2)+i] = TxMessage->Data[i]; + } + } + else//CAN_RTR_Remote + { + frame_header|=(CAN_RTR_Remote<<6); + } + hcan->Instance->DF.DATABUF[0]=frame_header; + hcan->Instance->CMR = CAN_CMR_TR; // transfer request + while((hcan->Instance->SR & CAN_SR_TCS)==0x00); //wait for send ok + return HAL_OK; +} + +/********************************************************************************* +* Function : HAL_CAN_CancelTransmit +* Description : Cancels a transmit request. +* Input : hcan : pointer to a CAN_HandleTypeDef structure that contains +* the configuration information for CAN module +* Output : +* Author : CWT Data : 2020 +**********************************************************************************/ +void HAL_CAN_CancelTransmit(CAN_HandleTypeDef *hcan) +{ + /* Check the parameters */ + if(!IS_CAN_ALL_PERIPH(hcan->Instance)) return ; + /* abort transmission */ + hcan->Instance->CMR |= CAN_CMR_AT; //Abort Transmission +} + +/********************************************************************************* +* Function : HAL_CAN_Receive +* Description : Receives a message. +* Input : hcan : pointer to a CAN_HandleTypeDef structure that contains +* the configuration information for CAN module +* Input : RxMessage : pointer to a structure receive message which contains +* CAN Id, CAN DLC, CAN datas . +* Output : +* Author : CWT Data : 2020 +**********************************************************************************/ +HAL_StatusTypeDef HAL_CAN_Receive_IT(CAN_HandleTypeDef *hcan, CanTxRxMsg* RxMessage) +{ + /* Check the parameters */ + if(!IS_CAN_ALL_PERIPH(hcan->Instance)) return HAL_ERROR ; + + hcan->RxMessage=RxMessage; + + /* Enable the CAN Receive interrupt */ + hcan->Instance->IER |= CAN_IER_RIE; + NVIC_ClearPendingIRQ(CAN1_IRQn); + NVIC_SetPriority(CAN1_IRQn, 5); + NVIC_EnableIRQ(CAN1_IRQn); + + return HAL_OK; +} + + +/********************************************************************************* +* Function : HAL_CAN_Receive +* Description : Receives a message. +* Input : hcan : pointer to a CAN_HandleTypeDef structure that contains +* the configuration information for CAN module +* Input : RxMessage : pointer to a structure receive message which contains +* CAN Id, CAN DLC, CAN datas . +* Output : +* Author : CWT Data : 2020 +**********************************************************************************/ +HAL_StatusTypeDef HAL_CAN_Receive(CAN_HandleTypeDef *hcan, CanTxRxMsg* RxMessage) +{ + /* Check the parameters */ + if(!IS_CAN_ALL_PERIPH(hcan->Instance)) return HAL_ERROR ; + while(!(hcan->Instance->SR & CAN_SR_RBS)); + HAL_CAN_GetRxMessage(hcan, RxMessage); + return HAL_OK; +} + +void HAL_CAN_GetRxMessage(CAN_HandleTypeDef *hcan, CanTxRxMsg* RxMessage) +{ + uint8_t i=0; + /* Check the parameters */ + if(!IS_CAN_ALL_PERIPH(hcan->Instance)) return ; + if(0 == (hcan->Instance->SR & CAN_SR_RBS) ) return; // receive fifo not empty + /* Get the IDE */ + RxMessage->IDE = (uint8_t)(0x80 & hcan->Instance->DF.DATABUF[0])>>7; + /* Get the RTR */ + RxMessage->RTR = (uint8_t)(0x40 & hcan->Instance->DF.DATABUF[0])>>6; + /* Get the DLC */ + RxMessage->DLC = (uint8_t)0x0F & hcan->Instance->DF.DATABUF[0]; + if (RxMessage->IDE == CAN_Id_Standard) + { + RxMessage->StdId = (uint32_t)(( hcan->Instance->DF.DATABUF[1]<<8) | hcan->Instance->DF.DATABUF[2])>>5;; + for(i=0; iDLC; i++) + { + RxMessage->Data[i] = hcan->Instance->DF.DATABUF[3+i]; + } + } + else + { + RxMessage->ExtId = (uint32_t)(( hcan->Instance->DF.DATABUF[1]<<24) | ( hcan->Instance->DF.DATABUF[2]<<16) | ( hcan->Instance->DF.DATABUF[3]<<8) | (hcan->Instance->DF.DATABUF[4] ))>>3;; + for(i=0; iDLC; i++) + { + RxMessage->Data[i] = hcan->Instance->DF.DATABUF[5+i]; + } + } + /* Release the FIFO */ + hcan->Instance->CMR |= CAN_CMR_RRB; //Release Receive Buffer +} + +/** + * @brief Initializes the CAN peripheral according to the specified + * parameters in the CAN_FilterInitStruct. + * @param CANx: where x can be 1 or 2 to to select the CAN peripheral. + CAN_FilterInitStruct: pointer to a CAN_FilterInitTypeDef + * structure that contains the configuration + * information. + * @retval None. + */ + +/********************************************************************************* +* Function : HAL_CAN_ConfigFilter +* Description : Initializes the CAN peripheral according to the specified parameters in the CAN_FilterInitStruct. +* Input : hcan : pointer to a CAN_HandleTypeDef structure that contains +* the configuration information for CAN module +* Input : CAN_FilterInitStruct : pointer to a CAN_FilterInitTypeDef structure that contains the configuration +* information. +* Output : +* Author : CWT Data : 2020 +**********************************************************************************/ +void HAL_CAN_ConfigFilter(CAN_HandleTypeDef *hcan,CAN_FilterInitTypeDef* CAN_FilterInitStruct) +{ + HAL_CAN_OperatingModeRequest(hcan,CAN_OperatingMode_Initialization);//enter CAN_OperatingMode_Initialization + /* Filter Mode */ + if (CAN_FilterInitStruct->CAN_FilterMode ==CAN_FilterMode_Dual) /*Dual mode*/ + { + hcan->Instance->MOD &= ~CAN_MOD_AFM; + /*Dual mode ACR set*/ + hcan->Instance->DF.FILTER.ACR[0] = (CAN_FilterInitStruct->CAN_FilterId1&0x1FE00000)>>21; /*Dual mode ACR0=ID28...ID21 of ID1*/ + hcan->Instance->DF.FILTER.ACR[1] = (CAN_FilterInitStruct->CAN_FilterId1&0x1FE000)>>13; /*Dual mode ACR0=ID20...ID13 of ID1*/ + hcan->Instance->DF.FILTER.ACR[2] = (CAN_FilterInitStruct->CAN_FilterId2&0x1FE00000)>>21; /*Dual mode ACR0=ID28...ID21 of ID2*/ + hcan->Instance->DF.FILTER.ACR[3] = (CAN_FilterInitStruct->CAN_FilterId2&0x1FE000)>>13; /*Dual mode ACR0=ID20...ID13 of ID2*/ + /*Dual mode AMR set*/ + hcan->Instance->DF.FILTER.AMR[0] = (CAN_FilterInitStruct->CAN_FilterMaskId1)>>24; + hcan->Instance->DF.FILTER.AMR[1] = (CAN_FilterInitStruct->CAN_FilterMaskId1&0xFF0000)>>16; + hcan->Instance->DF.FILTER.AMR[2] = (CAN_FilterInitStruct->CAN_FilterMaskId2)>>24; + hcan->Instance->DF.FILTER.AMR[3] = (CAN_FilterInitStruct->CAN_FilterMaskId2&0xFF0000)>>16; + } + else /*Single mode*/ + { + hcan->Instance->MOD |= CAN_MOD_AFM; + /*Single mode ACR set*/ + hcan->Instance->DF.FILTER.ACR[0] = (CAN_FilterInitStruct->CAN_FilterId1&0x1FE00000)>>21; /*Single mode ACR0=ID28...ID21*/ + hcan->Instance->DF.FILTER.ACR[1] = (CAN_FilterInitStruct->CAN_FilterId1&0x1FE000)>>13; /*Single mode ACR1=ID20...ID13*/ + hcan->Instance->DF.FILTER.ACR[2] = (CAN_FilterInitStruct->CAN_FilterId1&0x1FE0)>>5; /*Single mode ACR2=ID12...ID5*/ + hcan->Instance->DF.FILTER.ACR[3] = (CAN_FilterInitStruct->CAN_FilterId1&0x1F)<<3; /*Single mode ACR3=ID4...ID0*/ + /*Single mode AMR set*/ + hcan->Instance->DF.FILTER.AMR[0] = (CAN_FilterInitStruct->CAN_FilterMaskId1)>>24; + hcan->Instance->DF.FILTER.AMR[1] = (CAN_FilterInitStruct->CAN_FilterMaskId1&0xFF0000)>>16; + hcan->Instance->DF.FILTER.AMR[2] = (CAN_FilterInitStruct->CAN_FilterMaskId1&0xFF00)>>8; + hcan->Instance->DF.FILTER.AMR[3] = (CAN_FilterInitStruct->CAN_FilterMaskId1&0xFF); + } + + HAL_CAN_OperatingModeRequest(hcan,CAN_OperatingMode_Normal);//enter CAN_OperatingMode_Initialization +} + + +/********************************************************************************* +* Function : HAL_CAN_Sleep +* Description : Enters the sleep mode. +* Input : hcan : pointer to a CAN_HandleTypeDef structure that contains +* the configuration information for CAN module +* Output : +* Author : CWT Data : 2020 +**********************************************************************************/ +HAL_StatusTypeDef HAL_CAN_Sleep(CAN_HandleTypeDef *hcan) +{ + HAL_StatusTypeDef status; + /* Check the parameters */ + if(!IS_CAN_ALL_PERIPH(hcan->Instance)) return HAL_ERROR; + /* Request Sleep mode */ + hcan->Instance->MOD |= CAN_MOD_SM; //Enter Sleep Mode + + /* Sleep mode status */ + if ((hcan->Instance->MOD & CAN_MOD_SM) == CAN_MOD_SM) + { + /* Sleep mode entered */ + status= HAL_OK; + }else + { + status=HAL_ERROR; + } + /* return sleep mode status */ + return status; +} + +/********************************************************************************* +* Function : HAL_CAN_WakeUp +* Description : Wakes the CAN up. +* Input : hcan : pointer to a CAN_HandleTypeDef structure that contains +* the configuration information for CAN module +* Output : +* Author : CWT Data : 2020 +**********************************************************************************/ +HAL_StatusTypeDef HAL_CAN_WakeUp(CAN_HandleTypeDef *hcan) +{ + HAL_StatusTypeDef status; + /* Check the parameters */ + if(!IS_CAN_ALL_PERIPH(hcan->Instance)) return HAL_ERROR; + /* sleep wake mode */ + hcan->Instance->MOD &=~ CAN_MOD_SM; //Enter Sleep Mode + + /* sleep wake status */ + if ((hcan->Instance->MOD & CAN_MOD_SM)== CAN_MOD_SM) + { + /* sleep wake not entered */ + status= HAL_ERROR; + }else + { + status=HAL_OK; + } + /* return sleep mode status */ + return status; +} + +/********************************************************************************* +* Function : HAL_CAN_GetTransmitErrorCounter +* Description : Returns the CANx Transmit Error Counter(TXERR). +* Input : hcan : pointer to a CAN_HandleTypeDef structure that contains +* the configuration information for CAN module +* Output : +* Author : CWT Data : 2020 +**********************************************************************************/ +int8_t HAL_CAN_GetTransmitErrorCounter(CAN_HandleTypeDef *hcan) +{ + uint8_t counter=0; + /* Check the parameters */ + if(!IS_CAN_ALL_PERIPH(hcan->Instance)) return -1; + /* Get the CANx Transmit Error Counter(TXERR) */ + counter = (uint8_t)(hcan->Instance->TXERR); + /* Return the CANx Transmit Error Counter(TXERR) */ + return counter; +} + + +/********************************************************************************* +* Function : HAL_CAN_GetReceiveErrorCounter +* Description : Returns the CANx Receive Error Counter(RXERR). +* Input : hcan : pointer to a CAN_HandleTypeDef structure that contains +* the configuration information for CAN module +* Output : +* Author : CWT Data : 2020 +**********************************************************************************/ +int8_t HAL_CAN_GetReceiveErrorCounter(CAN_HandleTypeDef *hcan) +{ + uint8_t counter=0; + /* Check the parameters */ + if(!IS_CAN_ALL_PERIPH(hcan->Instance)) return -1; + /* Get the CANx Receive Error Counter(RXERR) */ + counter = (uint8_t)(hcan->Instance->RXERR); + /* Return the CANx Receive Error Counter(RXERR) */ + return counter; +} + + +/********************************************************************************* +* Function : HAL_CAN_GetErrorCode +* Description : Returns the CANx's error code (ECC). +* Input : hcan : pointer to a CAN_HandleTypeDef structure that contains +* the configuration information for CAN module +* Input : Error_Type:This parameter can be one of the following flags: +* CAN_ErrorType_SegCode +* CAN_ErrorType_Direction +* CAN_ErrorType_ErrCode +* Output : +* Author : CWT Data : 2020 +**********************************************************************************/ +int8_t HAL_CAN_GetErrorCode(CAN_HandleTypeDef *hcan,uint32_t Error_Type) +{ + uint8_t ErrorCode=0; + if(!IS_CAN_ALL_PERIPH(hcan->Instance)) return -1; + if(!IS_CAN_ErrorType(Error_Type)) return -1; + /* Get the CANx Error SegCode */ + if(Error_Type==CAN_ErrorType_SegCode) + { + ErrorCode= (uint8_t)(hcan->Instance->ECC & CAN_ErrorType_SegCode); + } + /* Get the CANx Error Direction */ + else if(Error_Type==CAN_ErrorType_Direction) + { + ErrorCode= (uint8_t)((hcan->Instance->ECC & CAN_ErrorType_Direction)>>5); + } + /* Get the CANx Error ErrCode */ + else + { + ErrorCode= (uint8_t)((hcan->Instance->ECC & CAN_ErrorType_ErrCode)>>6); + } + return ErrorCode; +} + +/********************************************************************************* +* Function : HAL_CAN_GetErrorAlarmCounter +* Description : Returns the CANx Error Alarm Counter(EWLR). +* Input : hcan : pointer to a CAN_HandleTypeDef structure that contains +* the configuration information for CAN module +* Output : +* Author : CWT Data : 2020 +**********************************************************************************/ +int8_t HAL_CAN_GetErrorAlarmCounter(CAN_HandleTypeDef *hcan) +{ + uint8_t counter=0; + /* Check the parameters */ + if(!IS_CAN_ALL_PERIPH(hcan->Instance)) return -1; + /* Get the CANx Error Alarm Counter(EWLR) */ + counter = (uint8_t)(hcan->Instance->EWLR); + /* Return the CANx Error Alarm Counter(EWLR) */ + return counter; +} + +/********************************************************************************* +* Function : HAL_CAN_GetArbitrationErrorPosition +* Description : Returns the CANx Arbitration Error Position(ALC). +* Input : hcan : pointer to a CAN_HandleTypeDef structure that contains +* the configuration information for CAN module +* Output : +* Author : CWT Data : 2020 +**********************************************************************************/ +int8_t HAL_CAN_GetArbitrationErrorPosition(CAN_HandleTypeDef *hcan) +{ + uint8_t position=0; + /* Check the parameters */ + if(!IS_CAN_ALL_PERIPH(hcan->Instance)) return -1; + /* Get the CANx Arbitration Error Counter(ALC) */ + position = (uint8_t)((hcan->Instance->ALC)+1); + /* Return the CANx Arbitration Error Counter(ALC) */ + return position; +} + + +/********************************************************************************* +* Function : HAL_CAN_GetReceiveFiFoCounter +* Description : Returns the CANx Receive FiFo Counter(RMC). +* Input : hcan : pointer to a CAN_HandleTypeDef structure that contains +* the configuration information for CAN module +* Output : +* Author : CWT Data : 2020 +**********************************************************************************/ +int8_t HAL_CAN_GetReceiveFiFoCounter(CAN_HandleTypeDef *hcan) +{ + uint8_t counter=0; + /* Check the parameters */ + if(!IS_CAN_ALL_PERIPH(hcan->Instance)) return -1; + /* Get the CANx Receive FiFo Counter(RMC) */ + counter = (uint8_t)(hcan->Instance->RMC); + /* Return the CANx Receive FiFo Counter(RMC) */ + return counter; +} + + +/********************************************************************************* +* Function : HAL_CAN_GetReceiveFiFoAddr +* Description : Returns the CANx Receive FiFo start address(RBSA). +* Input : hcan : pointer to a CAN_HandleTypeDef structure that contains +* the configuration information for CAN module +* Output : +* Author : CWT Data : 2020 +**********************************************************************************/ +int8_t HAL_CAN_GetReceiveFiFoAddr(CAN_HandleTypeDef *hcan) +{ + uint8_t addr=0; + /* Check the parameters */ + if(!IS_CAN_ALL_PERIPH(hcan->Instance)) return -1; + /* Get the CANx Receive FiFo start address(RBSA) */ + addr = (uint8_t)(hcan->Instance->RBSA); + /* Return the CANx Receive FiFo start address(RBSA) */ + return addr; +} + + +/********************************************************************************* +* Function : HAL_CAN_ReleaseReceiveFIFO +* Description : Releases the Receive FIFO. +* Input : hcan : pointer to a CAN_HandleTypeDef structure that contains +* the configuration information for CAN module +* Output : +* Author : CWT Data : 2020 +**********************************************************************************/ +void HAL_CAN_ReleaseReceiveFIFO(CAN_HandleTypeDef *hcan) +{ + /* Check the parameters */ + if(!IS_CAN_ALL_PERIPH(hcan->Instance)) return; + /* Releases the Receive FIFO. */ + hcan->Instance->CMR|=CAN_CMR_RRB; +} + + +/********************************************************************************* +* Function : HAL_CAN_ClearOverload +* Description : Clear Overload +* Input : hcan : pointer to a CAN_HandleTypeDef structure that contains +* the configuration information for CAN module +* Output : +* Author : CWT Data : 2020 +**********************************************************************************/ +void HAL_CAN_ClearOverload(CAN_HandleTypeDef *hcan) +{ + /* Check the parameters */ + if(!IS_CAN_ALL_PERIPH(hcan->Instance)) return; + /* Clear Overload. */ + hcan->Instance->CMR|=CAN_CMR_CDO; +} + + +/********************************************************************************* +* Function : HAL_CAN_SlefReceive +* Description : Slef Receive +* Input : hcan : pointer to a CAN_HandleTypeDef structure that contains +* the configuration information for CAN module +* Output : +* Author : CWT Data : 2020 +**********************************************************************************/ +void HAL_CAN_SelfReceive(CAN_HandleTypeDef *hcan) +{ + /* Check the parameters */ + if(!IS_CAN_ALL_PERIPH(hcan->Instance)) return; + /* Slef Receive. */ + hcan->Instance->CMR|=CAN_CMR_SRR; + while((hcan->Instance->SR & CAN_SR_TCS)==0x00); //wait for send ok +} + +/********************************************************************************* +* Function : HAL_CAN_IRQHandler +* Description : This function handles CAN interrupt request. +* Input : hdma : pointer to a CAN_HandleTypeDef structure that contains +* the configuration information for CAN module +* Outpu : +* Author : Chris_Kyle Data : 2020 +**********************************************************************************/ +void HAL_CAN_IRQHandler(CAN_HandleTypeDef *hcan) +{ + volatile uint32_t lu32_IR; + lu32_IR = hcan->Instance->IR;//read clear + + if(lu32_IR & CAN_IR_RI) //RI + { + /* CAN ReceiveIT complete callback */ + HAL_CAN_GetRxMessage(hcan, hcan->RxMessage); + hcan->CAN_ReceiveIT_Callback(hcan); + } + if(lu32_IR & CAN_IR_TI) //TI + { + /* CAN TransmitIT complete callback */ + hcan->CAN_TransmitIT_Callback(hcan); + } +} \ No newline at end of file diff --git a/bsp/acm32f4xx-nucleo/libraries/HAL_Driver/Src/HAL_COMP.c b/bsp/acm32f4xx-nucleo/libraries/HAL_Driver/Src/HAL_COMP.c new file mode 100644 index 0000000000..53554b1079 --- /dev/null +++ b/bsp/acm32f4xx-nucleo/libraries/HAL_Driver/Src/HAL_COMP.c @@ -0,0 +1,320 @@ +/* + ****************************************************************************** + * @file HAL_COMP.c + * @version V1.0.0 + * @date 2020 + * @brief COMP HAL module driver. + * This file provides firmware functions to manage the following + * functionalities of the Comparator Peripheral (COMP). + * @ Initialization and de-initialization functions + * @ IO operation functions + * @ Peripheral Control functions + ****************************************************************************** +*/ +#include "ACM32Fxx_HAL.h" + +/************************************************************************ + * function : HAL_COMP_MspInit + * Description: Inition the comparator gpio and clock + * input : COMP_HandleTypeDef* hcomp: pointer to comparator structure. + * output : none + ************************************************************************/ +__weak void HAL_COMP_MspInit(COMP_HandleTypeDef* hcomp) +{ + /* + NOTE : This function should be modified by the user. + */ + + /* For Example */ + GPIO_InitTypeDef GPIO_Handle; + + System_Module_Enable(EN_COMP); + + if(hcomp->Init.Comparator == COMP1 ) + { + /* COMP1 GPIO inition VINP:PC4(INP_0)*/ + /* COMP1 GPIO inition VINM:PA4(INM_0)*/ + /* COMP1 GPIO inition VOUT:PA0(FUNCTION_7)*/ + GPIO_Handle.Pin = GPIO_PIN_4; + GPIO_Handle.Mode = GPIO_MODE_ANALOG; + GPIO_Handle.Pull = GPIO_NOPULL; + HAL_GPIO_Init(GPIOC, &GPIO_Handle); + + GPIO_Handle.Pin = GPIO_PIN_4; + GPIO_Handle.Mode = GPIO_MODE_ANALOG; + GPIO_Handle.Pull = GPIO_NOPULL; + HAL_GPIO_Init(GPIOA, &GPIO_Handle); + + GPIO_Handle.Pin = GPIO_PIN_0; + GPIO_Handle.Mode = GPIO_MODE_AF_PP; + GPIO_Handle.Alternate = GPIO_FUNCTION_7; + GPIO_Handle.Pull = GPIO_NOPULL; + HAL_GPIO_Init(GPIOA, &GPIO_Handle); + } + else if(hcomp->Init.Comparator == COMP2 ) + { + /* COMP2 GPIO inition VINP:PA3(INP_1)*/ + /* COMP2 GPIO inition VOUT:PA7(FUNCTION_7)*/ + GPIO_Handle.Pin = GPIO_PIN_3; + GPIO_Handle.Mode = GPIO_MODE_ANALOG; + GPIO_Handle.Pull = GPIO_NOPULL; + HAL_GPIO_Init(GPIOA, &GPIO_Handle); + + GPIO_Handle.Pin = GPIO_PIN_7; + GPIO_Handle.Mode = GPIO_MODE_AF_PP; + GPIO_Handle.Alternate = GPIO_FUNCTION_7; + GPIO_Handle.Pull = GPIO_NOPULL; + HAL_GPIO_Init(GPIOA, &GPIO_Handle); + } +} + +/************************************************************************ + * function : HAL_COMP_MspDeInit + * Description: De-Inition the comparator gpio and clock + * input : COMP_HandleTypeDef* hcomp: pointer to comparator structure. + * output : none + ************************************************************************/ +__weak void HAL_COMP_MspDeInit(COMP_HandleTypeDef* hcomp) +{ + /* + NOTE : This function should be modified by the user. + */ + + /* For Example */ + System_Module_Reset(RST_COMP); + System_Module_Enable(EN_COMP); +} + +/************************************************************************ + * function : HAL_COMP_Init + * Description: Inition the comparator + * input : COMP_HandleTypeDef* hcomp: pointer to comparator structure. + ************************************************************************/ +HAL_StatusTypeDef HAL_COMP_Init(COMP_HandleTypeDef* hcomp) +{ + uint32_t u32RegTemp; + __IO uint32_t *gu32RegCrx; + + /* Check the COMP handle allocation */ + if (hcomp == NULL) + { + return HAL_ERROR; + } + + /* Check the parameters */ + if(!IS_COMP_ALL_INSTANCE(hcomp->Instance)) return HAL_ERROR; + if(!IS_COMP_ALL_COMP(hcomp->Init.Comparator)) return HAL_ERROR; + if(!IS_COMP_ALL_CRV_EN(hcomp->Init.Crv_En)) return HAL_ERROR; + if(!IS_COMP_ALL_CRV_SEL(hcomp->Init.Crv_Sel)) return HAL_ERROR; + if(!IS_COMP_ALL_CRV_CFG(hcomp->Init.Crv_Cfg)) return HAL_ERROR; + if(!IS_COMP_ALL_WINMODE(hcomp->Init.WinMode)) return HAL_ERROR; + if(!IS_COMP_ALL_WINOUT(hcomp->Init.WinOut)) return HAL_ERROR; + if(!IS_COMP_ALL_POLARITY(hcomp->Init.Polarity)) return HAL_ERROR; + if(!IS_COMP_ALL_FLTEN(hcomp->Init.FltEn)) return HAL_ERROR; + if(!IS_COMP_ALL_FLTTIME(hcomp->Init.FltTime)) return HAL_ERROR; + if(!IS_COMP_ALL_BLANKTIME(hcomp->Init.BlankTime)) return HAL_ERROR; + if(!IS_COMP_ALL_BLANKSEL(hcomp->Init.BlankSel)) return HAL_ERROR; + if(!IS_COMP_ALL_INPSEL(hcomp->Init.InPSel)) return HAL_ERROR; + if(!IS_COMP_ALL_INMSEL(hcomp->Init.InMSel)) return HAL_ERROR; + if(!IS_COMP_ALL_HYS(hcomp->Init.HYS)) return HAL_ERROR; + + /* Init the low level hardware : GPIO, CLOCK */ + HAL_COMP_MspInit(hcomp); + + if(hcomp->Init.Comparator == COMP1 ) + gu32RegCrx = &hcomp->Instance->CR1; + else + gu32RegCrx = &hcomp->Instance->CR2; + + //Check if the register is locked + if(READ_BIT(*gu32RegCrx , COMP_CR_LOCK)) + { + System_Module_Reset(RST_COMP); + } + + //Check if the comparetor is enable + if(READ_BIT(*gu32RegCrx , COMP_CR_EN)) + CLEAR_BIT(*gu32RegCrx , COMP_CR_EN); + + u32RegTemp = *gu32RegCrx ; + + u32RegTemp = u32RegTemp | ((hcomp->Init.Crv_Cfg << COMP_CR_CRV_CFG_POS)& COMP_CR_CRV_CFG_MASK) | \ + ((hcomp->Init.Crv_Sel << 24) & COMP_CR_CRV_SEL) | \ + ((hcomp->Init.Crv_En << 23) & COMP_CR_CRV_EN) | \ + ((hcomp->Init.WinMode << 22) & COMP_CR_WINMODE) | \ + ((hcomp->Init.WinOut << 21) & COMP_CR_WINOUT) | \ + ((hcomp->Init.Polarity << 20) & COMP_CR_POLARITY) | \ + ((hcomp->Init.FltEn << 19) & COMP_CR_FLTEN) | \ + ((hcomp->Init.FltTime << COMP_CR_FLTTIME_POS)& COMP_CR_FLTTIME_MASK) | \ + ((hcomp->Init.BlankTime << COMP_CR_BLANKTIME_POS)& COMP_CR_BLANKTIME_MASK) | \ + ((hcomp->Init.BlankSel << COMP_CR_BLANKSEL_POS)& COMP_CR_BLANKSEL_MASK) | \ + ((hcomp->Init.InPSel << COMP_CR_INPSEL_POS)& COMP_CR_INPSEL_MASK) | \ + ((hcomp->Init.InMSel << COMP_CR_INMSEL_POS)& COMP_CR_INMSEL_MASK) | \ + ((hcomp->Init.HYS << COMP_CR_HYS_POS)& COMP_CR_HYS_MASK); + + //Write the COMP_CR register . + WRITE_REG(*gu32RegCrx,u32RegTemp); + + SET_BIT(*gu32RegCrx , COMP_CR_EN); //enable + + return HAL_OK; +} + +/************************************************************************ + * function : HAL_COMP_Enable + * Description: Enable the comparator + * input : COMP_HandleTypeDef* hcomp: pointer to comparator structure. + ************************************************************************/ +HAL_StatusTypeDef HAL_COMP_Enable(COMP_HandleTypeDef* hcomp) +{ + __IO uint32_t *gu32RegCrx; + + /* Check the COMP handle allocation */ + if (hcomp == NULL) + { + return HAL_ERROR; + } + + /* Check the parameters */ + if(!IS_COMP_ALL_INSTANCE(hcomp->Instance)) return HAL_ERROR; + if(!IS_COMP_ALL_COMP(hcomp->Init.Comparator)) return HAL_ERROR; + + if(hcomp->Init.Comparator == COMP1 ) + gu32RegCrx = &hcomp->Instance->CR1; + else + gu32RegCrx = &hcomp->Instance->CR2; + + SET_BIT(*gu32RegCrx , COMP_CR_EN); //enable + + /* Return function status */ + return HAL_OK; +} + +/************************************************************************ + * function : HAL_COMP_DeInit + * Description: Deinit and reset the comparator + * input : COMP_HandleTypeDef* hcomp: pointer to comparator structure. + ************************************************************************/ +HAL_StatusTypeDef HAL_COMP_DeInit(COMP_HandleTypeDef* hcomp) +{ + /* Check the COMP handle allocation */ + if (hcomp == NULL) + { + return HAL_ERROR; + } + + HAL_COMP_MspDeInit(hcomp); + + memset(&hcomp->Init, 0, sizeof(hcomp->Init)); + /* Return function status */ + return HAL_OK; +} + +/************************************************************************ + * function : HAL_COMP_Disable + * Description: Disable the comparator + * input : COMP_HandleTypeDef* hcomp: pointer to comparator structure. + ************************************************************************/ +HAL_StatusTypeDef HAL_COMP_Disable(COMP_HandleTypeDef* hcomp) +{ + __IO uint32_t *gu32RegCrx; + + /* Check the COMP handle allocation */ + if (hcomp == NULL) + { + return HAL_ERROR; + } + + /* Check the parameters */ + if(!IS_COMP_ALL_INSTANCE(hcomp->Instance)) return HAL_ERROR; + if(!IS_COMP_ALL_COMP(hcomp->Init.Comparator)) return HAL_ERROR; + + if(hcomp->Init.Comparator == COMP1 ) + gu32RegCrx = &hcomp->Instance->CR1; + else + gu32RegCrx = &hcomp->Instance->CR2; + + CLEAR_BIT(*gu32RegCrx , COMP_CR_EN); //disable + + /* Return function status */ + return HAL_OK; +} + +/************************************************************************ + * function : HAL_COMP_GetOutputLevel + * Description: Get the output level of the comparator + * input : COMP_HandleTypeDef* hcomp: pointer to comparator structure. + ************************************************************************/ +HAL_StatusTypeDef HAL_COMP_GetOutputLevel(COMP_HandleTypeDef* hcomp) +{ + uint32_t u32RegTemp; + /* Check the parameters */ + if(!IS_COMP_ALL_INSTANCE(hcomp->Instance)) return HAL_ERROR; + if(!IS_COMP_ALL_COMP(hcomp->Init.Comparator)) return HAL_ERROR; + + u32RegTemp = READ_REG(hcomp->Instance->SR); + + if(hcomp->Init.Comparator == COMP1 ) + { + hcomp->OutputLevel_Org = (u32RegTemp & COMP_SR_VCOUT1_ORG)? 1:0; + hcomp->OutputLevel = (u32RegTemp & COMP_SR_VCOUT1)? 1:0; + } + else + { + hcomp->OutputLevel_Org = (u32RegTemp & COMP_SR_VCOUT2_ORG)? 1:0; + hcomp->OutputLevel = (u32RegTemp & COMP_SR_VCOUT2)? 1:0; + } + + /* Return function status */ + return HAL_OK; +} + +/************************************************************************ + * function : HAL_COMP_Lock + * Description: Lock the comparator + * input : COMP_HandleTypeDef* hcomp: pointer to comparator structure. + ************************************************************************/ +HAL_StatusTypeDef HAL_COMP_Lock(COMP_HandleTypeDef* hcomp) +{ + __IO uint32_t *gu32RegCrx; + + /* Check the COMP handle allocation */ + if (hcomp == NULL) + { + return HAL_ERROR; + } + + /* Check the parameters */ + if(!IS_COMP_ALL_INSTANCE(hcomp->Instance)) return HAL_ERROR; + if(!IS_COMP_ALL_COMP(hcomp->Init.Comparator)) return HAL_ERROR; + + if(hcomp->Init.Comparator == COMP1 ) + gu32RegCrx = &hcomp->Instance->CR1; + else + gu32RegCrx = &hcomp->Instance->CR2; + + SET_BIT(*gu32RegCrx , COMP_CR_LOCK); //lock + /* Return function status */ + return HAL_OK; +} + +/************************************************************************ + * function : HAL_COMP_Start + * Description: Start the comparator + * input : COMP_HandleTypeDef* hcomp: pointer to comparator structure. + ************************************************************************/ +HAL_StatusTypeDef HAL_COMP_Start(COMP_HandleTypeDef *hcomp) +{ + return(HAL_COMP_Enable(hcomp)); +} + + +/************************************************************************ + * function : HAL_COMP_Stop + * Description: Stop the comparator + * input : COMP_HandleTypeDef* hcomp: pointer to comparator structure. + ************************************************************************/ +HAL_StatusTypeDef HAL_COMP_Stop(COMP_HandleTypeDef *hcomp) +{ + return(HAL_COMP_Disable(hcomp)); +} diff --git a/bsp/acm32f4xx-nucleo/libraries/HAL_Driver/Src/HAL_CRC.c b/bsp/acm32f4xx-nucleo/libraries/HAL_Driver/Src/HAL_CRC.c new file mode 100644 index 0000000000..bdd086b0b0 --- /dev/null +++ b/bsp/acm32f4xx-nucleo/libraries/HAL_Driver/Src/HAL_CRC.c @@ -0,0 +1,54 @@ +/* + ****************************************************************************** + * @file HAL_Crc.c + * @author Firmware Team + * @version V1.0.0 + * @date 2020 + * @brief CRC HAL module driver. + * This file provides firmware functions to manage the following + * functionalities of the Universal Asynchronous Receiver Transmitter Peripheral (UART). + * @ Initialization and de-initialization functions + * @ IO operation functions + * @ Peripheral Control functions + ****************************************************************************** +*/ +#include "ACM32Fxx_HAL.h" + +/********************************************************************************* +* Function : HAL_CRC_Init +* Description : Initialize the CRC MSP. +* Input : hcrc: CRC handle. +* Output : +* Author : cl Data : 2021 +**********************************************************************************/ +void HAL_CRC_Init(CRC_HandleTypeDef *hcrc) +{ + System_Module_Enable(EN_CRC); + hcrc->Instance->CTRL = hcrc->Init.PolyRev | hcrc->Init.OutxorRev | hcrc->Init.InitRev | hcrc->Init.RsltRev | + hcrc->Init.DataRev | hcrc->Init.PolyLen | hcrc->Init.DataLen; + + hcrc->Instance->INIT = hcrc->Init.InitData; + hcrc->Instance->OUTXOR = hcrc->Init.OutXorData; + hcrc->Instance->POLY = hcrc->Init.PolyData; +} + +/********************************************************************************* +* Function : HAL_CRC_Calculate +* Description : Calculate the crc calue of input data. +* Input : hcrc: CRC handle. +* Output : CRC value +* Author : cl Data : 2021 +**********************************************************************************/ +uint32_t HAL_CRC_Calculate(CRC_HandleTypeDef *hcrc) +{ + HAL_CRC_Init(hcrc); + + while(hcrc->CRC_Data_Len--) + { + hcrc->Instance->DATA = *hcrc->CRC_Data_Buff++; + } + + return (hcrc->Instance->DATA); +} + + diff --git a/bsp/acm32f4xx-nucleo/libraries/HAL_Driver/Src/HAL_DAC.c b/bsp/acm32f4xx-nucleo/libraries/HAL_Driver/Src/HAL_DAC.c new file mode 100644 index 0000000000..694b2624bc --- /dev/null +++ b/bsp/acm32f4xx-nucleo/libraries/HAL_Driver/Src/HAL_DAC.c @@ -0,0 +1,828 @@ +/* + ****************************************************************************** + * @file HAL_DAC.c + * @version V1.0.0 + * @date 2020 + * @brief DAC HAL module driver. + * This file provides firmware functions to manage the following + * functionalities of the Universal Asynchronous Receiver Transmitter Peripheral (DAC). + * @ Initialization and de-initialization functions + * @ IO operation functions + * @ Peripheral Control functions + ****************************************************************************** +*/ +#include "ACM32Fxx_HAL.h" + + /********************************************************************************* +* Function : HAL_DAC_IRQHandler +* Description : This function uses the interruption of DMA underrun. +* Input : hdac : pointer to a DAC_HandleTypeDef structure that contains +* the configuration information for DAC module +* Output : +* Author : CWT Data : 2020 +**********************************************************************************/ +void HAL_DAC_IRQHandler(DAC_HandleTypeDef *hdac) +{ + if((hdac->Instance->SR&DAC_SR_DMAUDR1)==DAC_SR_DMAUDR1||(hdac->Instance->SR &DAC_SR_DMAUDR2)==DAC_SR_DMAUDR2) + { + //clear the DMA underrun + hdac->Instance->SR|=DAC_SR_DMAUDR1|DAC_SR_DMAUDR2; + } +} +/********************************************************************************* +* Function : HAL_DAC_MspInit +* Description : Initialize the DAC MSP. +* Input : hdac : pointer to a DAC_HandleTypeDef structure that contains +* the configuration information for DAC module +* Output : +* Author : CWT Data : 2020 +**********************************************************************************/ + +__weak void HAL_DAC_MspInit(DAC_HandleTypeDef *hdac) +{ + /* NOTE : This function should not be modified, when the callback is needed, + the HAL_DAC_MspInit can be implemented in the user file + */ + /* For Example */ + if(hdac->Instance==DAC) + { + /* Enable DAC clock */ + System_Module_Enable(EN_DAC); + GPIO_InitTypeDef GPIO_InitStructure; + /* Initialization GPIO */ + /**DAC1 GPIO Configuration + PB1 ------> DAC_OUT1 + PB0 ------> DAC_OUT2 + */ + GPIO_InitStructure.Pin = GPIO_PIN_1|GPIO_PIN_0; + GPIO_InitStructure.Pull=GPIO_NOPULL; + GPIO_InitStructure.Mode = GPIO_MODE_ANALOG; + HAL_GPIO_Init(GPIOB, &GPIO_InitStructure); + + /* Enable the DAC DMA underrun interrupt */ + hdac->Instance->CR |= DAC_CR_DMAUDRIE1|DAC_CR_DMAUDRIE2; + NVIC_ClearPendingIRQ(DAC_IRQn); + NVIC_SetPriority(DAC_IRQn, 5); + NVIC_EnableIRQ(DAC_IRQn); + } +} + +/********************************************************************************* +* Function : HAL_DAC_MspDeInit +* Description : DAC MSP De-Initialization. +* Input : hdac : pointer to a DAC_HandleTypeDef structure that contains +* the configuration information for DAC module +* Output : +* Author : CWT Data : 2020 +**********************************************************************************/ +void HAL_DAC_MspDeInit(DAC_HandleTypeDef* hdac) +{ + if(hdac->Instance==DAC) + { + /* USER CODE BEGIN DAC1_MspDeInit 0 */ + + /* USER CODE END DAC1_MspDeInit 0 */ + /* Peripheral clock disable */ + System_Module_Disable(EN_DAC); + /**DAC1 GPIO Configuration + PB1 ------> DAC_OUT1 + PB0 ------> DAC_OUT2 + */ + HAL_GPIO_DeInit(GPIOB, GPIO_PIN_0); + HAL_GPIO_DeInit(GPIOB, GPIO_PIN_1); + /* DAC1 DMA DeInit */ + HAL_DMA_DeInit(hdac->DMA_Handle1); + HAL_DMA_DeInit(hdac->DMA_Handle2); + /* USER CODE BEGIN DAC1_MspDeInit 1 */ + + /* USER CODE END DAC1_MspDeInit 1 */ + } + +} + +/********************************************************************************* +* Function : HAL_DAC_Init +* Description : Initializes the CAN peripheral according to the specified parameters in the DAC_HandleTypeDef.. +* Input : hdac : pointer to a DAC_HandleTypeDef structure that contains +* the configuration information for DAC module +* Output : HAL status +* Author : CWT Data : 2020 +**********************************************************************************/ +HAL_StatusTypeDef HAL_DAC_Init(DAC_HandleTypeDef *hdac) +{ + uint8_t InitStatus = HAL_ERROR; + /* Check the parameters */ + if(!IS_DAC_ALL_PERIPH(hdac->Instance)) return HAL_ERROR; + + System_Module_Reset(RST_DAC); + HAL_DAC_MspInit(hdac); + return HAL_OK; +} + +/********************************************************************************* +* Function : HAL_DAC_DeInit +* Description : Deinitialize the DAC peripheral registers to their default reset values. +* Input : hdac : pointer to a DAC_HandleTypeDef structure that contains +* the configuration information for DAC module +* Output : HAL status +* Author : CWT Data : 2020 +**********************************************************************************/ +HAL_StatusTypeDef HAL_DAC_DeInit(DAC_HandleTypeDef* hdac) +{ + /* Check DAC handle */ + if (hdac == NULL) + { + return HAL_ERROR; + } + /* Check the parameters */ + if(!IS_DAC_ALL_PERIPH(hdac->Instance)) return HAL_ERROR; + HAL_DAC_MspDeInit(hdac); + + /* Return function status */ + return HAL_OK; +} + +/********************************************************************************* +* Function : HAL_DAC_ConfigChannel +* Description : Configures the selected DAC channel. +* Input : hdac : hdac pointer to a DAC_HandleTypeDef structure that contains +* the configuration information for the specified DAC. +* sConfig:DAC configuration structure +* Channel:This parameter can be one of the following values: @arg DAC_CHANNEL_1 @argDAC_CHANNEL_2 +* Output : HAL status +* Author : CWT Data : 2020 +**********************************************************************************/ +HAL_StatusTypeDef HAL_DAC_ConfigChannel(DAC_HandleTypeDef* hdac, DAC_ChannelConfTypeDef* sConfig, uint32_t Channel) +{ + uint32_t tmpreg1, tmpreg2; + uint32_t tickstart = 0U; + uint32_t ConnectOnChipPeripheral=0U; + /* Check the DAC parameters */ + if(!IS_DAC_ALL_PERIPH(hdac->Instance)) return HAL_ERROR; + if(!IS_DAC_TRIGGER(sConfig->DAC_Trigger)) return HAL_ERROR; + if(!IS_DAC_OUTPUT_BUFFER_STATE(sConfig->DAC_OutputBuffer)) return HAL_ERROR; + if(!IS_DAC_CHIP_CONNECTION(sConfig->DAC_ConnectOnChipPeripheral)) return HAL_ERROR; + if(!IS_DAC_TRIMMING(sConfig->DAC_UserTrimming)) return HAL_ERROR; + if ((sConfig->DAC_UserTrimming) == DAC_TRIMMING_USER) + { + if(!IS_DAC_TRIMMINGVALUE(sConfig->DAC_TrimmingValue)) return HAL_ERROR; + } + if(!IS_DAC_SAMPLEANDHOLD(sConfig->DAC_SampleAndHold)) return HAL_ERROR; + if ((sConfig->DAC_SampleAndHold) == DAC_SAMPLEANDHOLD_ENABLE) + { + if(!IS_DAC_SAMPLETIME(sConfig->DAC_SampleAndHoldConfig.DAC_SampleTime)) return HAL_ERROR; + if(!IS_DAC_HOLDTIME(sConfig->DAC_SampleAndHoldConfig.DAC_HoldTime)) return HAL_ERROR; + if(!IS_DAC_REFRESHTIME(sConfig->DAC_SampleAndHoldConfig.DAC_RefreshTime)) return HAL_ERROR; + } + if(!IS_DAC_CHANNEL(Channel)) return HAL_ERROR; + + + + if (sConfig->DAC_SampleAndHold == DAC_SAMPLEANDHOLD_ENABLE) + /* Sample on old configuration */ + { + /* SampleTime */ + if (Channel == DAC_CHANNEL_1) + { + hdac->Instance->SHSR1 = sConfig->DAC_SampleAndHoldConfig.DAC_SampleTime; + } + else /* Channel 2 */ + + hdac->Instance->SHSR2 = sConfig->DAC_SampleAndHoldConfig.DAC_SampleTime; + + /* HoldTime */ + MODIFY_REG(hdac->Instance->SHHR, DAC_SHHR_THOLD1 << (Channel & 0x10UL), (sConfig->DAC_SampleAndHoldConfig.DAC_HoldTime) << (Channel & 0x10UL)); + /* RefreshTime */ + MODIFY_REG(hdac->Instance->SHRR, DAC_SHRR_TREFRESH1 << (Channel & 0x10UL), (sConfig->DAC_SampleAndHoldConfig.DAC_RefreshTime) << (Channel & 0x10UL)); + } + + if (sConfig->DAC_UserTrimming == DAC_TRIMMING_USER) + /* USER TRIMMING */ + { + /* Get the DAC CCR value */ + tmpreg1 = hdac->Instance->CCR; + /* Clear trimming value */ + tmpreg1 &= ~(((uint32_t)(DAC_CCR_OTRIM1)) << (Channel & 0x10UL)); + /* Configure for the selected trimming offset */ + tmpreg2 = sConfig->DAC_TrimmingValue; + /* Calculate CCR register value depending on DAC_Channel */ + tmpreg1 |= tmpreg2 << (Channel & 0x10UL); + /* Write to DAC CCR */ + hdac->Instance->CCR = tmpreg1; + } + else + { + /* factory trimming in NVR,read to DAC_CCR */ + uint32_t OTRIM=*(uint32_t *)(0x80248); + uint32_t OTRIM_high=(OTRIM&0xffff0000)>>16; + uint32_t OTRIM_low=(OTRIM&0xffff); + if (OTRIM_low==((~OTRIM_high)&0xffff)) + { + tmpreg1=(OTRIM_low&0x1f)|(((OTRIM_low&0x3E0)>>5)<<16); + hdac->Instance->CCR = tmpreg1; + } + } + + + /* Get the DAC MCR value */ + tmpreg1 = hdac->Instance->MCR; + /* Clear DAC_MCR_MODEx bits */ + tmpreg1 &= ~(((uint32_t)(DAC_MCR_MODE1)) << (Channel & 0x10UL)); + /* Configure for the selected DAC channel: mode, buffer output & on chip peripheral connect */ + ConnectOnChipPeripheral=sConfig->DAC_ConnectOnChipPeripheral; + if((sConfig->DAC_SampleAndHold == DAC_SAMPLEANDHOLD_ENABLE)&&(sConfig->DAC_OutputBuffer==DAC_OUTPUTBUFFER_DISABLE)) + { + ConnectOnChipPeripheral=(!ConnectOnChipPeripheral); + } + tmpreg2 = (sConfig->DAC_SampleAndHold | sConfig->DAC_OutputBuffer | ConnectOnChipPeripheral); + /* Calculate MCR register value depending on DAC_Channel */ + tmpreg1 |= tmpreg2 << (Channel & 0x10UL); + /* Write to DAC MCR */ + hdac->Instance->MCR = tmpreg1; + + /* DAC in normal operating mode hence clear DAC_CR_CENx bit */ + CLEAR_BIT(hdac->Instance->CR, DAC_CR_CEN1 << (Channel & 0x10UL)); + + /* Get the DAC CR value */ + tmpreg1 = hdac->Instance->CR; + /* Clear TENx, TSELx, WAVEx and MAMPx bits */ + tmpreg1 &= ~(((uint32_t)(DAC_CR_MAMP1 | DAC_CR_WAVE1 | DAC_CR_TSEL1 | DAC_CR_TEN1)) << (Channel & 0x10UL)); + /* Configure for the selected DAC channel: trigger */ + /* Set TSELx and TENx bits according to DAC_Trigger value */ + tmpreg2 = sConfig->DAC_Trigger; + /* Calculate CR register value depending on DAC_Channel */ + tmpreg1 |= tmpreg2 << (Channel & 0x10UL); + /* Write to DAC CR */ + hdac->Instance->CR = tmpreg1; + + /* Disable wave generation */ + hdac->Instance->CR &= ~(DAC_CR_WAVE1 << (Channel & 0x10UL)); + + + /* Return function status */ + return HAL_OK; +} + +/********************************************************************************* +* Function : HAL_DAC_Start +* Description : Enables DAC and starts conversion of channel. +* Input : hdac : hdac pointer to a DAC_HandleTypeDef structure that contains +* the configuration information for the specified DAC. +* Channel:This parameter can be one of the following values: @arg DAC_CHANNEL_1 @argDAC_CHANNEL_2 +* Output : HAL status +* Author : CWT Data : 2020 +**********************************************************************************/ +HAL_StatusTypeDef HAL_DAC_Start(DAC_HandleTypeDef *hdac, uint32_t Channel) +{ + /* Check the parameters */ + if(!IS_DAC_ALL_PERIPH(hdac->Instance)) return HAL_ERROR; + if(!IS_DAC_CHANNEL(Channel)) return HAL_ERROR; + uint32_t tmp1 = 0U, tmp2 = 0U; + + if (Channel == DAC_CHANNEL_1) + { + hdac->Instance->CR|=DAC_CR_EN1; + tmp1 = hdac->Instance->CR & DAC_CR_TEN1; + tmp2 = hdac->Instance->CR & DAC_CR_TSEL1; + /* Check if software trigger enabled */ + if((tmp1 == DAC_CR_TEN1) && (tmp2 == DAC_CR_TSEL1)) + { + /* Enable the selected DAC software conversion */ + hdac->Instance->SWTRIGR|=DAC_SWTRIGR_SWTRIG1; + } + } + else + { + hdac->Instance->CR|=DAC_CR_EN2; + tmp1 = hdac->Instance->CR & DAC_CR_TEN2; + tmp2 = hdac->Instance->CR & DAC_CR_TSEL2; + /* Check if software trigger enabled */ + if((tmp1 == DAC_CR_TEN2) && (tmp2 == DAC_CR_TSEL2)) + { + /* Enable the selected DAC software conversion */ + hdac->Instance->SWTRIGR|=DAC_SWTRIGR_SWTRIG2; + } + } + /* Return function status */ + return HAL_OK; +} + +/********************************************************************************* +* Function : HAL_DAC_Stop +* Description : Disables DAC and stop conversion of channel. +* Input : hdac : hdac pointer to a DAC_HandleTypeDef structure that contains +* the configuration information for the specified DAC. +* Channel:This parameter can be one of the following values: @arg DAC_CHANNEL_1 @argDAC_CHANNEL_2 +* Output : HAL status +* Author : CWT Data : 2020 +**********************************************************************************/ +HAL_StatusTypeDef HAL_DAC_Stop(DAC_HandleTypeDef* hdac, uint32_t Channel) +{ + /* Check the parameters */ + if(!IS_DAC_ALL_PERIPH(hdac->Instance)) return HAL_ERROR; + if(!IS_DAC_CHANNEL(Channel)) return HAL_ERROR; + + /* Disable the Peripheral */ + if (Channel == DAC_CHANNEL_1) + { + hdac->Instance->CR&=~DAC_CR_EN1; + } + else + { + hdac->Instance->CR&=~DAC_CR_EN2; + } + + /* Return function status */ + return HAL_OK; +} + +/********************************************************************************* +* Function : HAL_DAC_Start_DMA +* Description : Enables DAC and starts conversion of channel. +* Input : hdac : hdac pointer to a DAC_HandleTypeDef structure that contains +* the configuration information for the specified DAC. +* Channel:This parameter can be one of the following values: @arg DAC_CHANNEL_1 @argDAC_CHANNEL_2 @arg DAC_CHANNEL_Dual +* pData: The destination peripheral Buffer address. +* Length: The length of data to be transferred from memory to DAC peripheral +* Alignment: Specifies the data alignment for DAC channel.This parameter can be one of the following values: + @arg DAC_ALIGN_8B_R @arg DAC_ALIGN_12B_L @arg DAC_ALIGN_12B_R +* Output : HAL status +* Author : CWT Data : 2020 +**********************************************************************************/ +HAL_StatusTypeDef HAL_DAC_Start_DMA(DAC_HandleTypeDef *hdac, uint32_t Channel, uint32_t *pData, uint32_t Length, uint32_t Alignment) +{ + HAL_StatusTypeDef status; + uint32_t DstAddr = 0U; + /* Check the parameters */ + if(!IS_DAC_ALL_PERIPH(hdac->Instance)) return HAL_ERROR; + if(!IS_DAC_CHANNEL(Channel)) return HAL_ERROR; + if(!IS_DAC_ALIGN(Alignment)) return HAL_ERROR; + + if (Channel == DAC_CHANNEL_1) + { + /* Enable the DAC DMA underrun interrupt */ + /* Enable the selected DAC channel2 DMA request */ + hdac->Instance->CR |= DAC_CR_EN1|DAC_CR_DMAEN1|DAC_CR_DMAUDRIE1; + /* Case of use of channel 1 */ + switch (Alignment) + { + case DAC_ALIGN_12B_R: + /* Get DHR12R1 address */ + DstAddr = (uint32_t)&hdac->Instance->DHR12R1; + break; + case DAC_ALIGN_12B_L: + /* Get DHR12L1 address */ + DstAddr = (uint32_t)&hdac->Instance->DHR12L1; + break; + case DAC_ALIGN_8B_R: + /* Get DHR8R1 address */ + DstAddr = (uint32_t)&hdac->Instance->DHR8R1; + break; + default: + break; + } + status = HAL_DMA_Start_IT(hdac->DMA_Handle1, (uint32_t)pData, DstAddr, Length); + } + else if(Channel == DAC_CHANNEL_2) + { + /* Enable the DAC DMA underrun interrupt */ + /* Enable the selected DAC channel2 DMA request */ + hdac->Instance->CR |= DAC_CR_EN2|DAC_CR_DMAEN2|DAC_CR_DMAUDRIE2; + + /* Case of use of channel 1 */ + switch (Alignment) + { + case DAC_ALIGN_12B_R: + /* Get DHR12R1 address */ + DstAddr = (uint32_t)&hdac->Instance->DHR12R2; + break; + case DAC_ALIGN_12B_L: + /* Get DHR12L1 address */ + DstAddr = (uint32_t)&hdac->Instance->DHR12L2; + break; + case DAC_ALIGN_8B_R: + /* Get DHR8R1 address */ + DstAddr = (uint32_t)&hdac->Instance->DHR8R2; + break; + default: + break; + } + status = HAL_DMA_Start_IT(hdac->DMA_Handle2, (uint32_t)pData, DstAddr, Length); + } + else/* DualChannel */ + { + hdac->Instance->CR |= DAC_CR_EN1|DAC_CR_DMAEN1|DAC_CR_DMAUDRIE1|DAC_CR_EN2 ; + /* Case of use of channel_1 DMA change two DAC channel */ + switch (Alignment) + { + case DAC_ALIGN_12B_R: + /* Get DHR12R1 address */ + DstAddr = (uint32_t)&hdac->Instance->DHR12RD; + break; + case DAC_ALIGN_12B_L: + /* Get DHR12L1 address */ + DstAddr = (uint32_t)&hdac->Instance->DHR12LD; + break; + case DAC_ALIGN_8B_R: + /* Get DHR8R1 address */ + DstAddr = (uint32_t)&hdac->Instance->DHR8RD; + break; + default: + break; + } + status = HAL_DMA_Start_IT(hdac->DMA_Handle1, (uint32_t)pData, DstAddr, Length); + } + /* Return function status */ + return status; +} + +/********************************************************************************* +* Function : HAL_DAC_Stop_DMA +* Description : Disables DAC and stop conversion of channel. +* Input : hdac : hdac pointer to a DAC_HandleTypeDef structure that contains +* the configuration information for the specified DAC. +* Channel:This parameter can be one of the following values: @arg DAC_CHANNEL_1 @argDAC_CHANNEL_2 @arg DAC_CHANNEL_Dual +* Output : HAL status +* Author : CWT Data : 2020 +**********************************************************************************/ +HAL_StatusTypeDef HAL_DAC_Stop_DMA(DAC_HandleTypeDef* hdac, uint32_t Channel) +{ + HAL_StatusTypeDef status = HAL_OK; + + /* Check the parameters */ + if(!IS_DAC_ALL_PERIPH(hdac->Instance)) return HAL_ERROR; + if(!IS_DAC_CHANNEL(Channel)) return HAL_ERROR; + + /* Disable the selected DAC channel DMA request */ + /* Disable the DMA Channel */ + /* Channel1 is used */ + if(Channel == DAC_CHANNEL_1) + { + hdac->Instance->CR &= ~DAC_CR_DMAEN1; + /* Disable the Peripheral */ + hdac->Instance->CR&=~DAC_CR_EN1; + status = HAL_DMA_Abort(hdac->DMA_Handle1); + } + + else if(Channel == DAC_CHANNEL_2) /* Channel2 is used for */ + { + hdac->Instance->CR &= ~DAC_CR_DMAEN2; + hdac->Instance->CR&=~DAC_CR_EN2; + status = HAL_DMA_Abort(hdac->DMA_Handle2); + } + else + { + hdac->Instance->CR &= ~DAC_CR_DMAEN1; + hdac->Instance->CR &= ~DAC_CR_DMAEN2; + /* Disable the Peripheral */ + hdac->Instance->CR&=~DAC_CR_EN1; + hdac->Instance->CR&=~DAC_CR_EN2; + status = HAL_DMA_Abort(hdac->DMA_Handle1)|HAL_DMA_Abort(hdac->DMA_Handle2); + } + + /* Return function status */ + return status; +} + +/********************************************************************************* +* Function : HAL_DAC_SetChannelValue +* Description : Set the specified data holding register value for DAC channel. +* Input : hdac : hdac pointer to a DAC_HandleTypeDef structure that contains +* the configuration information for the specified DAC. +* Channel:This parameter can be one of the following values: @arg DAC_CHANNEL_1 @argDAC_CHANNEL_2 +* Alignment: Specifies the data alignment for DAC channel.This parameter can be one of the following values: +* @arg DAC_ALIGN_8B_R @arg DAC_ALIGN_12B_L @arg DAC_ALIGN_12B_R +* Data:The destination peripheral Buffer address. +* Output : HAL status +* Author : CWT Data : 2020 +**********************************************************************************/ +HAL_StatusTypeDef HAL_DAC_SetValue(DAC_HandleTypeDef *hdac, uint32_t Channel, uint32_t Alignment, uint32_t Data) +{ + __IO uint32_t tmp = 0; + + /* Check the parameters */ + if(!IS_DAC_ALL_PERIPH(hdac->Instance)) return HAL_ERROR; + if(!IS_DAC_CHANNEL(Channel)) return HAL_ERROR; + if(!IS_DAC_ALIGN(Alignment)) return HAL_ERROR; + + tmp = (uint32_t)hdac->Instance; + if (Channel == DAC_CHANNEL_1) + { + tmp += DAC_DHR12R1_ALIGNMENT(Alignment); + } + else + { + tmp += DAC_DHR12R2_ALIGNMENT(Alignment); + } + + /* Calculate and set dual DAC data holding register value */ + if (Alignment == DAC_ALIGN_12B_L) + { + Data = (uint32_t)Data << 4; + } + + /* Set the DAC channel selected data holding register */ + *(__IO uint32_t *) tmp = Data; + + /* Return function status */ + return HAL_OK; +} + +/********************************************************************************* +* Function : HAL_DACEx_DualSetValue +* Description : Set the specified data holding register value for dual DAC channel. +* Input : hdac : hdac pointer to a DAC_HandleTypeDef structure that contains +* the configuration information for the specified DAC. +* Alignment: Specifies the data alignment for DAC channel.This parameter can be one of the following values: +* @arg DAC_ALIGN_8B_R @arg DAC_ALIGN_12B_L @arg DAC_ALIGN_12B_R +* Datax:The destination peripheral Buffer address. +* Output : HAL status +* Author : CWT Data : 2020 +**********************************************************************************/ +HAL_StatusTypeDef HAL_DACEx_DualSetValue(DAC_HandleTypeDef *hdac, uint32_t Alignment, uint32_t Data1, uint32_t Data2) +{ + uint32_t data, tmp; + /* Check the parameters */ + if(!IS_DAC_ALL_PERIPH(hdac->Instance)) return HAL_ERROR; + if(!IS_DAC_ALIGN(Alignment)) return HAL_ERROR; + + /* Calculate and set dual DAC data holding register value */ + if (Alignment == DAC_ALIGN_12B_L) + { + data = ((uint32_t)Data2 << 20U) | (Data1<<4); + } + else + { + data = ((uint32_t)Data2 << 16U) | Data1; + } + + tmp = (uint32_t)hdac->Instance; + tmp += DAC_DHR12RD_ALIGNMENT(Alignment); + + /* Set the dual DAC selected data holding register */ + *(__IO uint32_t *)tmp = data; + + /* Return function status */ + return HAL_OK; +} + +/********************************************************************************* +* Function : HAL_DAC_GetValue +* Description : Returns the last data output value of the selected DAC channel. +* Input : hdac : hdac pointer to a DAC_HandleTypeDef structure that contains +* the configuration information for the specified DAC. +* Channel:This parameter can be one of the following values: @arg DAC_CHANNEL_1 @arg DAC_CHANNEL_2 +* Output : The selected DAC channel data output value. +* Author : CWT Data : 2020 +**********************************************************************************/ +uint32_t HAL_DAC_GetValue(DAC_HandleTypeDef* hdac, uint32_t Channel) +{ + /* Check the parameters */ + if(!IS_DAC_ALL_PERIPH(hdac->Instance)) return HAL_ERROR; + if(!IS_DAC_CHANNEL(Channel)) return HAL_ERROR; + + /* Returns the DAC channel data output register value */ + if(Channel == DAC_CHANNEL_1) + { + return hdac->Instance->DOR1; + } + else + { + return hdac->Instance->DOR2; + } + +} + + +/********************************************************************************* +* Function : HAL_DACEx_DualGetValue +* Description : Return the last data output value of the selected DAC channel. +* Input : hdac : hdac pointer to a DAC_HandleTypeDef structure that contains +* the configuration information for the specified DAC. +* Output : The selected DAC channel data output value. +* Author : CWT Data : 2020 +**********************************************************************************/ +uint32_t HAL_DACEx_DualGetValue(DAC_HandleTypeDef *hdac) +{ + /* Check the parameters */ + if(!IS_DAC_ALL_PERIPH(hdac->Instance)) return HAL_ERROR; + uint32_t tmp = 0U; + + tmp |= hdac->Instance->DOR1; + + tmp |= hdac->Instance->DOR2 << 16U; + + /* Returns the DAC channel data output register value */ + return tmp; +} + +/********************************************************************************* +* Function :HAL_DACEx_TriangleWaveGenerate +* Description : Enable or disable the selected DAC channel wave generation. +* Input : hdac : hdac pointer to a DAC_HandleTypeDef structure that contains +* the configuration information for the specified DAC. +* Channel:The selected DAC channel. This parameter can be one of the following values: +* @arg DAC_CHANNEL_1: DAC Channel1 selected +* @arg DAC_CHANNEL_2: DAC Channel2 selected +* Amplitude: Amplitude Select max triangle amplitude. +* This parameter can be one of the following values: +* @arg DAC_TRIANGLEAMPLITUDE_1: Select max triangle amplitude of 1 +* @arg DAC_TRIANGLEAMPLITUDE_3: Select max triangle amplitude of 3 +* @arg DAC_TRIANGLEAMPLITUDE_7: Select max triangle amplitude of 7 +* @arg DAC_TRIANGLEAMPLITUDE_15: Select max triangle amplitude of 15 +* @arg DAC_TRIANGLEAMPLITUDE_31: Select max triangle amplitude of 31 +* @arg DAC_TRIANGLEAMPLITUDE_63: Select max triangle amplitude of 63 +* @arg DAC_TRIANGLEAMPLITUDE_127: Select max triangle amplitude of 127 +* @arg DAC_TRIANGLEAMPLITUDE_255: Select max triangle amplitude of 255 +* @arg DAC_TRIANGLEAMPLITUDE_511: Select max triangle amplitude of 511 +* @arg DAC_TRIANGLEAMPLITUDE_1023: Select max triangle amplitude of 1023 +* @arg DAC_TRIANGLEAMPLITUDE_2047: Select max triangle amplitude of 2047 +* @arg DAC_TRIANGLEAMPLITUDE_4095: Select max triangle amplitude of 4095 +* Author : CWT Data : 2020 +**********************************************************************************/ + +HAL_StatusTypeDef HAL_DACEx_TriangleWaveGenerate(DAC_HandleTypeDef *hdac, uint32_t Channel, uint32_t Amplitude) +{ + /* Check the parameters */ + if(!IS_DAC_ALL_PERIPH(hdac->Instance)) return HAL_ERROR; + if(!IS_DAC_CHANNEL(Channel)) return HAL_ERROR; + if(!IS_DAC_LFSR_UNMASK_TRIANGLE_AMPLITUDE(Amplitude)) return HAL_ERROR; + /* Enable the triangle wave generation for the selected DAC channel */ + MODIFY_REG(hdac->Instance->CR, ((DAC_CR_WAVE1) | (DAC_CR_MAMP1)) << (Channel & 0x10UL), (DAC_CR_WAVE1_1 | Amplitude) << (Channel & 0x10UL)); + + /* Return function status */ + return HAL_OK; +} + + + + /********************************************************************************* +* Function : HAL_DACEx_NoiseWaveGenerate +* Description : Enable or disable the selected DAC channel wave generation +* Input : hdac : hdac pointer to a DAC_HandleTypeDef structure that contains +* the configuration information for the specified DAC. +* Channel:The selected DAC channel. This parameter can be one of the following values: +* @arg DAC_CHANNEL_1: DAC Channel1 selected +* @arg DAC_CHANNEL_2: DAC Channel2 selected +* Amplitude: Amplitude Unmask DAC channel LFSR for noise wave generation. +* This parameter can be one of the following values: +* @arg DAC_LFSRUNMASK_BIT0: Unmask DAC channel LFSR bit0 for noise wave generation +* @arg DAC_LFSRUNMASK_BITS1_0: Unmask DAC channel LFSR bit[1:0] for noise wave generation +* @arg DAC_LFSRUNMASK_BITS2_0: Unmask DAC channel LFSR bit[2:0] for noise wave generation +* @arg DAC_LFSRUNMASK_BITS3_0: Unmask DAC channel LFSR bit[3:0] for noise wave generation +* @arg DAC_LFSRUNMASK_BITS4_0: Unmask DAC channel LFSR bit[4:0] for noise wave generation +* @arg DAC_LFSRUNMASK_BITS5_0: Unmask DAC channel LFSR bit[5:0] for noise wave generation +* @arg DAC_LFSRUNMASK_BITS6_0: Unmask DAC channel LFSR bit[6:0] for noise wave generation +* @arg DAC_LFSRUNMASK_BITS7_0: Unmask DAC channel LFSR bit[7:0] for noise wave generation +* @arg DAC_LFSRUNMASK_BITS8_0: Unmask DAC channel LFSR bit[8:0] for noise wave generation +* @arg DAC_LFSRUNMASK_BITS9_0: Unmask DAC channel LFSR bit[9:0] for noise wave generation +* @arg DAC_LFSRUNMASK_BITS10_0: Unmask DAC channel LFSR bit[10:0] for noise wave generation +* @arg DAC_LFSRUNMASK_BITS11_0: Unmask DAC channel LFSR bit[11:0] for noise wave generation +* Output : HAL status +* Author : CWT Data : 2020 +**********************************************************************************/ +HAL_StatusTypeDef HAL_DACEx_NoiseWaveGenerate(DAC_HandleTypeDef *hdac, uint32_t Channel, uint32_t Amplitude) +{ + /* Check the parameters */ + if(!IS_DAC_ALL_PERIPH(hdac->Instance)) return HAL_ERROR; + if(!IS_DAC_CHANNEL(Channel)) return HAL_ERROR; + if(!IS_DAC_LFSR_UNMASK_TRIANGLE_AMPLITUDE(Amplitude)) return HAL_ERROR; + /* Enable the noise wave generation for the selected DAC channel */ + MODIFY_REG(hdac->Instance->CR, ((DAC_CR_WAVE1) | (DAC_CR_MAMP1)) << (Channel & 0x10UL), (DAC_CR_WAVE1_0 | Amplitude) << (Channel & 0x10UL)); + /* Return function status */ + return HAL_OK; +} + + +/********************************************************************************* +* Function : HAL_DACEx_SelfCalibrate +* Description : SRun the self calibration of one DAC channel. +* Input : hdac : hdac pointer to a DAC_HandleTypeDef structure that contains +* the configuration information for the specified DAC. +* sConfig:sConfig DAC channel configuration structure +* Channel:The selected DAC channel. This parameter can be one of the following values: +* @arg DAC_CHANNEL_1: DAC Channel1 selected +* @arg DAC_CHANNEL_2: DAC Channel2 selected +* Output : HAL status +* Author : CWT Data : 2020 +**********************************************************************************/ +HAL_StatusTypeDef HAL_DACEx_SelfCalibrate(DAC_HandleTypeDef *hdac, DAC_ChannelConfTypeDef *sConfig, uint32_t Channel) +{ + /* Check the parameters */ + if(!IS_DAC_ALL_PERIPH(hdac->Instance)) return HAL_ERROR; + if(!IS_DAC_CHANNEL(Channel)) return HAL_ERROR; + + HAL_StatusTypeDef status = HAL_OK; + + __IO uint32_t tmp; + uint32_t trimmingvalue; + uint32_t laststatus=0; + uint32_t nowstatus=0; + + SET_BIT((hdac->Instance->CR), (DAC_CR_EN1 << (Channel & 0x10UL))); + tmp = (uint32_t)hdac->Instance; + if (Channel == DAC_CHANNEL_1) + { + tmp += DAC_DHR12R1_ALIGNMENT(DAC_ALIGN_12B_R); + } + else + { + tmp += DAC_DHR12R2_ALIGNMENT(DAC_ALIGN_12B_R); + } + + *(__IO uint32_t *) tmp = 0x0800U; + + /* Enable the selected DAC channel calibration */ + /* i.e. set DAC_CR_CENx bit */ + SET_BIT((hdac->Instance->CR), (DAC_CR_CEN1 << (Channel & 0x10UL))); + + /* Init trimming counter */ + /* Medium value ,trimmingvalue:0-31(0x1f)*/ + for(trimmingvalue=0;trimmingvalue<32;trimmingvalue++) + { + /* Set candidate trimming */ + MODIFY_REG(hdac->Instance->CCR, (DAC_CCR_OTRIM1 << (Channel & 0x10UL)), (trimmingvalue << (Channel & 0x10UL))); + System_Delay_MS(1); + laststatus=nowstatus; + nowstatus=(hdac->Instance->SR & (DAC_SR_CAL_FLAG1 << (Channel & 0x10UL)))>>(DAC_SR_CAL_FLAG1_Pos +Channel); + /* tOFFTRIMmax delay x ms as per datasheet (electrical characteristics */ + /* i.e. minimum time needed between two calibration steps */ + if (nowstatus==1&&laststatus==0) + { + break; + } + } + + /* Disable the selected DAC channel calibration */ + /* i.e. clear DAC_CR_CENx bit */ + CLEAR_BIT((hdac->Instance->CR), (DAC_CR_CEN1 << (Channel & 0x10UL))); + + /* Disable the selected DAC channel */ + CLEAR_BIT((hdac->Instance->CR), (DAC_CR_EN1 << (Channel & 0x10UL))); + + sConfig->DAC_TrimmingValue = trimmingvalue; + sConfig->DAC_UserTrimming = DAC_TRIMMING_USER; + + return status; +} + + +/********************************************************************************* +* Function : HAL_DACEx_SetUserTrimming +* Description : Set the trimming mode and trimming value (user trimming mode applied). +* Input : hdac : hdac pointer to a DAC_HandleTypeDef structure that contains +* the configuration information for the specified DAC. +* sConfig:sConfig DAC channel configuration structure +* Channel:The selected DAC channel. This parameter can be one of the following values: +* @arg DAC_CHANNEL_1: DAC Channel1 selected +* @arg DAC_CHANNEL_2: DAC Channel2 selected +* NewTrimmingValue: DAC new trimming value +* Output : HAL status +* Author : CWT Data : 2020 +**********************************************************************************/ +HAL_StatusTypeDef HAL_DACEx_SetUserTrimming(DAC_HandleTypeDef *hdac, DAC_ChannelConfTypeDef *sConfig, uint32_t Channel, uint32_t NewTrimmingValue) +{ + HAL_StatusTypeDef status = HAL_OK; + + /* Check the parameters */ + if(!IS_DAC_ALL_PERIPH(hdac->Instance)) return HAL_ERROR; + if(!IS_DAC_CHANNEL(Channel)) return HAL_ERROR; + if(!IS_DAC_Calibration_TRIM(NewTrimmingValue)) return HAL_ERROR; + + /* Check the DAC handle allocation */ + if (hdac == NULL) + { + status = HAL_ERROR; + } + else + { + /* Set new trimming */ + MODIFY_REG(hdac->Instance->CCR, (DAC_CCR_OTRIM1 << (Channel & 0x10UL)), (NewTrimmingValue << (Channel & 0x10UL))); + /* Update trimming mode */ + sConfig->DAC_UserTrimming = DAC_TRIMMING_USER; + sConfig->DAC_TrimmingValue = NewTrimmingValue; + } + return status; +} + + +/********************************************************************************* +* Function : HAL_DACEx_GetTrimOffset +* Description : Return the DAC trimming value. +* Input : hdac : hdac pointer to a DAC_HandleTypeDef structure that contains +* the configuration information for the specified DAC. +* Channel:The selected DAC channel. This parameter can be one of the following values: +* @arg DAC_CHANNEL_1: DAC Channel1 selected +* @arg DAC_CHANNEL_2: DAC Channel2 selected +* Output : Trimming value : range: 0->31 +* Author : CWT Data : 2020 +**********************************************************************************/ +uint32_t HAL_DACEx_GetTrimOffset(DAC_HandleTypeDef *hdac, uint32_t Channel) +{ + /* Check the parameters */ + if(!IS_DAC_ALL_PERIPH(hdac->Instance)) return HAL_ERROR; + if(!IS_DAC_CHANNEL(Channel)) return HAL_ERROR; + + /* Retrieve trimming */ + return ((hdac->Instance->CCR & (DAC_CCR_OTRIM1 << (Channel & 0x10UL))) >> (Channel & 0x10UL)); +} diff --git a/bsp/acm32f4xx-nucleo/libraries/HAL_Driver/Src/HAL_DMA.c b/bsp/acm32f4xx-nucleo/libraries/HAL_Driver/Src/HAL_DMA.c new file mode 100644 index 0000000000..06a742d89d --- /dev/null +++ b/bsp/acm32f4xx-nucleo/libraries/HAL_Driver/Src/HAL_DMA.c @@ -0,0 +1,422 @@ +/* + ****************************************************************************** + * @file HAL_DMA.c + * @version V1.0.0 + * @date 2020 + * @brief DMA HAL module driver. + * This file provides firmware functions to manage the following + * functionalities of the Direct Memory Access (DMA) peripheral: + * @ Initialization and de-initialization functions + * @ IO operation functions + ****************************************************************************** +*/ +#include "ACM32Fxx_HAL.h" + +/**************** Used in cycle mode ****************/ +static DMA_LLI_InitTypeDef Cycle_Channel[DMA_CHANNEL_NUM]; + +/********************************************************************************* +* Function : HAL_DMA_IRQHandler +* Description : This function handles DMA interrupt request. +* Input : hdma : pointer to a DMA_HandleTypeDef structure that contains +* the configuration information for DMA module +* Output : +* Author : Chris_Kyle Data : 2020 +**********************************************************************************/ +__weak void HAL_DMA_IRQHandler(DMA_HandleTypeDef *hdma) +{ + uint32_t lu32_Channel_Index; + + /* Get DMA Channel number */ + lu32_Channel_Index = ((uint32_t)(hdma->Instance) - (uint32_t)(DMA_Channel0)) / 0x20; + + /* Channel has been interrupted */ + if (DMA->INT_STATUS & (1 << lu32_Channel_Index)) + { + /* Transfer complete interrupt */ + if (DMA->INT_TC_STATUS & (1 << lu32_Channel_Index)) + { + DMA->INT_TC_CLR |= (1 << lu32_Channel_Index); + + if (NULL != hdma->DMA_ITC_Callback) + { + hdma->DMA_ITC_Callback(); + } + } + + /* Transfer error interrupt */ + if (DMA->INT_ERR_STATUS & (1 << lu32_Channel_Index)) + { + DMA->INT_ERR_CLR |= (1 << lu32_Channel_Index); + + if (NULL != hdma->DMA_IE_Callback) + { + hdma->DMA_IE_Callback(); + } + } + } +} + +/********************************************************************************* +* Function : HAL_DMA_Init +* Description : DMA initial with parameters. +* Input : hdma : pointer to a DMA_HandleTypeDef structure that contains +* the configuration information for DMA module +* Output : +* Author : Chris_Kyle Data : 2020 +**********************************************************************************/ +HAL_StatusTypeDef HAL_DMA_Init(DMA_HandleTypeDef *hdma) +{ +#if (USE_FULL_ASSERT == 1) + /* Check DMA Parameter */ + if (!IS_DMA_ALL_INSTANCE(hdma->Instance)) return HAL_ERROR; + if (!IS_DMA_DATA_FLOW(hdma->Init.Data_Flow)) return HAL_ERROR; + if (!IS_DMA_REQUEST_ID(hdma->Init.Request_ID)) return HAL_ERROR; + if (!IS_DMA_SRC_WIDTH(hdma->Init.Source_Width)) return HAL_ERROR; + if (!IS_DMA_DST_WIDTH(hdma->Init.Desination_Width)) return HAL_ERROR; +#endif + + /* Enable DMA Module */ + System_Module_Enable(EN_DMA); + + /* Enable External Interrupt */ + NVIC_ClearPendingIRQ(DMA_IRQn); + NVIC_EnableIRQ(DMA_IRQn); + + /* Default Little-Endian、Enable DMA */ + DMA->CONFIG = DMA_CONFIG_EN; + + /* Clear Channel Config */ + hdma->Instance->CONFIG = 0x00000000; + + if (hdma->Init.Data_Flow == DMA_DATA_FLOW_M2P) + { + hdma->Init.Request_ID <<= DMA_CHANNEL_CONFIG_DEST_PERIPH_POS; + } + else if (hdma->Init.Data_Flow == DMA_DATA_FLOW_P2M) + { + hdma->Init.Request_ID <<= DMA_CHANNEL_CONFIG_SRC_PERIPH_POS; + } + + hdma->Instance->CONFIG = hdma->Init.Data_Flow | hdma->Init.Request_ID; + + /* Config Channel Control */ + hdma->Instance->CTRL = DMA_CHANNEL_CTRL_ITC; + /* Source or Desination address increase */ + hdma->Instance->CTRL |= (hdma->Init.Desination_Inc | hdma->Init.Source_Inc); + /* Source or Desination date width */ + hdma->Instance->CTRL |= (hdma->Init.Desination_Width | hdma->Init.Source_Width); + + return HAL_OK; +} + +/********************************************************************************* +* Function : HAL_DMA_DeInit +* Description : DMA De-initial with parameters. +* Input : hdma : pointer to a DMA_HandleTypeDef structure that contains +* the configuration information for DMA module +* Output : +* Author : Chris_Kyle Data : 2020 +**********************************************************************************/ +HAL_StatusTypeDef HAL_DMA_DeInit(DMA_HandleTypeDef *hdma) +{ +#if (USE_FULL_ASSERT == 1) + /* Check DMA Parameter */ + if (!IS_DMA_ALL_INSTANCE(hdma->Instance)) return HAL_ERROR; + if (!IS_DMA_DATA_FLOW(hdma->Init.Data_Flow)) return HAL_ERROR; + if (!IS_DMA_REQUEST_ID(hdma->Init.Request_ID)) return HAL_ERROR; + if (!IS_DMA_SRC_WIDTH(hdma->Init.Source_Width)) return HAL_ERROR; + if (!IS_DMA_DST_WIDTH(hdma->Init.Desination_Width)) return HAL_ERROR; +#endif + + /* Reset DMA Module */ + System_Module_Reset(RST_DMA); + + /* Disable DMA Module */ + System_Module_Disable(EN_DMA); + + /* Disable Interrupt */ + NVIC_ClearPendingIRQ(DMA_IRQn); + NVIC_DisableIRQ(DMA_IRQn); + + hdma->DMA_IE_Callback = NULL; + hdma->DMA_ITC_Callback = NULL; + + memset(&hdma->Init, 0, sizeof(hdma->Init)); + + return HAL_OK; +} + +/********************************************************************************* +* Function : HAL_DMA_NormalMode_Start +* Description : DMA transfer start. +* Input : hdma : pointer to a DMA_HandleTypeDef structure that contains +* the configuration information for DMA module +* Input : fu32_SrcAddr: source address +* Input : fu32_DstAddr: desination address +* Input : fu32_Size: transfer size (This parameter can be a 12-bit Size) +* Output : +* Author : Chris_Kyle Data : 2020 +**********************************************************************************/ +HAL_StatusTypeDef HAL_DMA_NormalMode_Start(DMA_HandleTypeDef *hdma, uint32_t fu32_SrcAddr, uint32_t fu32_DstAddr, uint32_t fu32_Size) +{ +#if (USE_FULL_ASSERT == 1) + /* Check DMA Parameter */ + if (!IS_DMA_ALL_INSTANCE(hdma->Instance)) return HAL_ERROR; +#endif + + if (fu32_Size > 0xFFF) + { + return HAL_ERROR; + } + + /* Set source address and desination address */ + hdma->Instance->SRC_ADDR = fu32_SrcAddr; + hdma->Instance->DEST_ADDR = fu32_DstAddr; + + /* Set Transfer Size */ + hdma->Instance->CTRL = (hdma->Instance->CTRL & (~0xFFF)) | fu32_Size; + + /* DMA Channel Enable */ + hdma->Instance->CONFIG |= DMA_CHANNEL_CONFIG_EN; + + return HAL_OK; +} + +/********************************************************************************* +* Function : HAL_DMA_NormalMode_Start_IT +* Description : DMA transfer start with interrupt. +* Input : hdma : pointer to a DMA_HandleTypeDef structure that contains +* the configuration information for DMA module +* Input : fu32_SrcAddr: source address +* Input : fu32_DstAddr: desination address +* Input : fu32_Size: transfer size (This parameter can be a 12-bit Size) +* Output : +* Author : Chris_Kyle Data : 2020 +**********************************************************************************/ +HAL_StatusTypeDef HAL_DMA_NormalMode_Start_IT(DMA_HandleTypeDef *hdma, uint32_t fu32_SrcAddr, uint32_t fu32_DstAddr, uint32_t fu32_Size) +{ +#if (USE_FULL_ASSERT == 1) + /* Check DMA Parameter */ + if (!IS_DMA_ALL_INSTANCE(hdma->Instance)) return HAL_ERROR; +#endif + + /* Set source address and desination address */ + hdma->Instance->SRC_ADDR = fu32_SrcAddr; + hdma->Instance->DEST_ADDR = fu32_DstAddr; + + /* Set Transfer Size and enable LLI interrupt */ + hdma->Instance->CTRL = (hdma->Instance->CTRL & (~0xFFF)) | fu32_Size; + + /* DMA Channel Enable and enable transfer error interrupt and transfer complete interrupt*/ + hdma->Instance->CONFIG |= DMA_CHANNEL_CONFIG_ITC | DMA_CHANNEL_CONFIG_IE | DMA_CHANNEL_CONFIG_EN; + + return HAL_OK; +} + +/********************************************************************************* +* Function : HAL_DMA_CycleMode_Start +* Description : DMA Cycle transfer start. +* Input : hdma : pointer to a DMA_HandleTypeDef structure that contains +* the configuration information for DMA module +* Input : fu32_SrcAddr: source address +* Input : fu32_DstAddr: desination address +* Input : fu32_Size: transfer size (This parameter can be a 12-bit Size) +* Output : +* Author : Chris_Kyle Data : 2020 +**********************************************************************************/ +HAL_StatusTypeDef HAL_DMA_CycleMode_Start(DMA_HandleTypeDef *hdma, uint32_t fu32_SrcAddr, uint32_t fu32_DstAddr, uint32_t fu32_Size) +{ + uint32_t lu32_Channel_Index; + +#if (USE_FULL_ASSERT == 1) + /* Check DMA Parameter */ + if (!IS_DMA_ALL_INSTANCE(hdma->Instance)) return HAL_ERROR; +#endif + + /* Get DMA Channel number */ + lu32_Channel_Index = ((uint32_t)(hdma->Instance) - (uint32_t)(DMA_Channel0)) / 0x20; + + /* Set source address and desination address */ + hdma->Instance->SRC_ADDR = fu32_SrcAddr; + hdma->Instance->DEST_ADDR = fu32_DstAddr; + + /* Set Next Link */ + hdma->Instance->LLI = (uint32_t)&Cycle_Channel[lu32_Channel_Index]; + + /* Set Transfer Size */ + hdma->Instance->CTRL = (hdma->Instance->CTRL & (~0xFFF)) | fu32_Size; + + /* The list point to oneself */ + Cycle_Channel[lu32_Channel_Index].SrcAddr = fu32_SrcAddr; + Cycle_Channel[lu32_Channel_Index].DstAddr = fu32_DstAddr; + Cycle_Channel[lu32_Channel_Index].Next = &Cycle_Channel[lu32_Channel_Index]; + Cycle_Channel[lu32_Channel_Index].Control = (hdma->Instance->CTRL & (~0xFFF)) | fu32_Size; + + /* DMA Channel Enable */ + hdma->Instance->CONFIG |= DMA_CHANNEL_CONFIG_EN; + + return HAL_OK; +} + +/********************************************************************************* +* Function : HAL_DMA_CycleMode_Start_IT +* Description : DMA Cycle transfer start with interrupt. +* Input : hdma : pointer to a DMA_HandleTypeDef structure that contains +* the configuration information for DMA module +* Input : fu32_SrcAddr: source address +* Input : fu32_DstAddr: desination address +* Input : fu32_Size: transfer size (This parameter can be a 12-bit Size) +* Output : +* Author : Chris_Kyle Data : 2020 +**********************************************************************************/ +HAL_StatusTypeDef HAL_DMA_CycleMode_Start_IT(DMA_HandleTypeDef *hdma, uint32_t fu32_SrcAddr, uint32_t fu32_DstAddr, uint32_t fu32_Size) +{ + uint32_t lu32_Channel_Index; + +#if (USE_FULL_ASSERT == 1) + /* Check DMA Parameter */ + if (!IS_DMA_ALL_INSTANCE(hdma->Instance)) return HAL_ERROR; +#endif + + /* Get DMA Channel number */ + lu32_Channel_Index = ((uint32_t)(hdma->Instance) - (uint32_t)(DMA_Channel0)) / 0x20; + + /* Set source address and desination address */ + hdma->Instance->SRC_ADDR = fu32_SrcAddr; + hdma->Instance->DEST_ADDR = fu32_DstAddr; + + /* Set Next Link */ + hdma->Instance->LLI = (uint32_t)&Cycle_Channel[lu32_Channel_Index]; + + /* Set Transfer Size */ + hdma->Instance->CTRL = (hdma->Instance->CTRL & (~0xFFF)) | fu32_Size; + + /* The list point to oneself */ + Cycle_Channel[lu32_Channel_Index].SrcAddr = fu32_SrcAddr; + Cycle_Channel[lu32_Channel_Index].DstAddr = fu32_DstAddr; + Cycle_Channel[lu32_Channel_Index].Next = &Cycle_Channel[lu32_Channel_Index]; + Cycle_Channel[lu32_Channel_Index].Control = (hdma->Instance->CTRL & (~0xFFF)) | fu32_Size; + + /* DMA Channel Enable and enable transfer error interrupt and transfer complete interrupt*/ + hdma->Instance->CONFIG |= DMA_CHANNEL_CONFIG_ITC | DMA_CHANNEL_CONFIG_IE | DMA_CHANNEL_CONFIG_EN; + + return HAL_OK; +} + +/********************************************************************************* +* Function : HAL_DMA_Start +* Description : DMA transfer start. +* Input : hdma : pointer to a DMA_HandleTypeDef structure that contains +* the configuration information for DMA module +* Input : fu32_SrcAddr: source address +* Input : fu32_DstAddr: desination address +* Input : fu32_Size: transfer size (This parameter can be a 12-bit Size) +* Output : +* Author : Chris_Kyle Data : 2020 +**********************************************************************************/ +HAL_StatusTypeDef HAL_DMA_Start(DMA_HandleTypeDef *hdma, uint32_t fu32_SrcAddr, uint32_t fu32_DstAddr, uint32_t fu32_Size) +{ + /* Check DMA Parameter */ + if (!IS_DMA_MODE(hdma->Init.Mode)) return HAL_ERROR; + + if (hdma->Init.Mode == DMA_NORMAL) + { + return HAL_DMA_NormalMode_Start(hdma, fu32_SrcAddr, fu32_DstAddr, fu32_Size); + } + else + { + return HAL_DMA_CycleMode_Start(hdma, fu32_SrcAddr, fu32_DstAddr, fu32_Size); + } +} + +/********************************************************************************* +* Function : HAL_DMA_Start_IT +* Description : DMA transfer start with interrupt. +* Input : hdma : pointer to a DMA_HandleTypeDef structure that contains +* the configuration information for DMA module +* Input : fu32_SrcAddr: source address +* Input : fu32_DstAddr: desination address +* Input : fu32_Size: transfer size (This parameter can be a 12-bit Size) +* Output : +* Author : Chris_Kyle Data : 2020 +**********************************************************************************/ +HAL_StatusTypeDef HAL_DMA_Start_IT(DMA_HandleTypeDef *hdma, uint32_t fu32_SrcAddr, uint32_t fu32_DstAddr, uint32_t fu32_Size) +{ + /* Check DMA Parameter */ + if (!IS_DMA_MODE(hdma->Init.Mode)) return HAL_ERROR; + + if (hdma->Init.Mode == DMA_NORMAL) + { + return HAL_DMA_NormalMode_Start_IT(hdma, fu32_SrcAddr, fu32_DstAddr, fu32_Size); + } + else + { + return HAL_DMA_CycleMode_Start_IT(hdma, fu32_SrcAddr, fu32_DstAddr, fu32_Size); + } +} + +/********************************************************************************* +* Function : HAL_DMA_Abort +* Description : Abort the DMA Transfer +* Input : hdma : pointer to a DMA_HandleTypeDef structure that contains +* the configuration information for DMA module +* Output : +* Author : Chris_Kyle Data : 2020 +**********************************************************************************/ +HAL_StatusTypeDef HAL_DMA_Abort(DMA_HandleTypeDef *hdma) +{ + uint32_t lu32_Channel_Index; + +#if (USE_FULL_ASSERT == 1) + /* Check DMA Parameter */ + if (!IS_DMA_ALL_INSTANCE(hdma->Instance)) return HAL_ERROR; +#endif + + /* Get DMA Channel number */ + lu32_Channel_Index = ((uint32_t)(hdma->Instance) - (uint32_t)(DMA_Channel0)) / 0x20; + + /* DMA Channel Disable */ + hdma->Instance->CONFIG &= ~(1 << 0); + + /* Clear TC ERR Falg */ + DMA->INT_TC_CLR |= (1 << lu32_Channel_Index); + DMA->INT_ERR_CLR |= (1 << lu32_Channel_Index); + + return HAL_OK; +} + +/********************************************************************************* +* Function : HAL_DMA_GetState +* Description : Returns the DMA state.. +* Input : hdma : pointer to a DMA_HandleTypeDef structure that contains +* the configuration information for DMA module +* Output : +* Author : Data : 2021 +**********************************************************************************/ +HAL_StatusTypeDef HAL_DMA_GetState(DMA_HandleTypeDef *hdma) +{ + uint32_t lu32_Channel_Index; + HAL_StatusTypeDef States = HAL_ERROR; + + /* Get DMA Channel number */ + lu32_Channel_Index = ((uint32_t)(hdma->Instance) - (uint32_t)(DMA_Channel0)) / 0x20; + + /* Transfer complete interrupt */ + if (DMA->RAW_INT_TC_STATUS & (1 << lu32_Channel_Index)) + { + DMA->INT_TC_CLR |= (1 << lu32_Channel_Index); + + States = HAL_OK; + } + + /* Transfer error interrupt */ + if (DMA->RAW_INT_ERR_STATUS & (1 << lu32_Channel_Index)) + { + DMA->INT_ERR_CLR |= (1 << lu32_Channel_Index); + + States = HAL_ERROR; + } + + return States; +} diff --git a/bsp/acm32f4xx-nucleo/libraries/HAL_Driver/Src/HAL_EFlash.c b/bsp/acm32f4xx-nucleo/libraries/HAL_Driver/Src/HAL_EFlash.c new file mode 100644 index 0000000000..df6a00e1f5 --- /dev/null +++ b/bsp/acm32f4xx-nucleo/libraries/HAL_Driver/Src/HAL_EFlash.c @@ -0,0 +1,114 @@ +/* + ****************************************************************************** + * @file HAL_EFlash.c + * @version V1.0.0 + * @date 2020 + * @brief EFlash HAL module driver. + * This file provides firmware functions to manage the following + * functionalities of the internal FLASH memory: + * @ Program operations functions + * @ Erase operations functions + ****************************************************************************** +*/ +#include "ACM32Fxx_HAL.h" + +/********************************************************************************* +* Function : HAL_EFlash_Init +* Description : Configure eflash parameter as system clock +* Input : system clock frequency +* Output : None +* Author : Chris_Kyle +**********************************************************************************/ +void HAL_EFlash_Init(uint32_t fu32_freq) +{ + HAL_EFlash_Init_Para(fu32_freq); +} + +#if (__ACCELERATE_EH_PRESENT == 0) +/********************************************************************************* +* Function : HAL_EFlash_Erase_Page +* Description : Erase a Page, TERASE has been configured in System_Clock_Init() +* Input : +* Output : false: FAIL + true: SUCCESS +* Author : Chris_Kyle +**********************************************************************************/ +bool HAL_EFlash_ErasePage(uint32_t fu32_Addr) +{ + EFC->CTRL |= EFC_CTRL_PAGE_ERASE_MODE; + + EFC->SEC = 0x55AAAA55; + + *((volatile uint32_t *)fu32_Addr) = 0; + + while (!(EFC->STATUS & EFC_STATUS_EFLASH_RDY)); + + EFC->CTRL &= ~EFC_CTRL_PAGE_ERASE_MODE; + + return true; +} + +/********************************************************************************* +* Function : HAL_EFlash_Programe +* Description : Program a word, TPROG has been configured in System_Clock_Init() +* Input : +* Output : false: FAIL + true: SUCCESS +* Author : Chris_Kyle +**********************************************************************************/ +bool HAL_EFlash_Program_Word(uint32_t fu32_Addr, uint32_t fu32_Data) +{ + if (fu32_Addr % 4) + { + return false; + } + + EFC->CTRL |= EFC_CTRL_PROGRAM_MODE; + + EFC->SEC = 0x55AAAA55; + + *((volatile uint32_t *)fu32_Addr) = fu32_Data; + + while (!(EFC->STATUS & EFC_STATUS_EFLASH_RDY)); + + EFC->CTRL &= ~EFC_CTRL_PROGRAM_MODE; + + return true; +} +#else +/********************************************************************************* +* Function : HAL_EFlash_Erase_Page +* Description : Erase a Page, TERASE has been configured in System_Clock_Init() +* Input : +* Output : false: FAIL + true: SUCCESS +* Author : Chris_Kyle +**********************************************************************************/ +bool HAL_EFlash_ErasePage(uint32_t fu32_Addr) +{ + HAL_EFlash_ErasePage_EX(fu32_Addr); + + return true; +} + +/********************************************************************************* +* Function : HAL_EFlash_Programe +* Description : Program a word, TPROG has been configured in System_Clock_Init() +* Input : +* Output : false: FAIL + true: SUCCESS +* Author : Chris_Kyle +**********************************************************************************/ +bool HAL_EFlash_Program_Word(uint32_t fu32_Addr, uint32_t fu32_Data) +{ + if (fu32_Addr % 4) + { + return false; + } + + HAL_EFlash_Program_Word_EX(fu32_Addr, fu32_Data); + + return true; +} + +#endif diff --git a/bsp/acm32f4xx-nucleo/libraries/HAL_Driver/Src/HAL_EXTI.c b/bsp/acm32f4xx-nucleo/libraries/HAL_Driver/Src/HAL_EXTI.c new file mode 100644 index 0000000000..ff2ab720cf --- /dev/null +++ b/bsp/acm32f4xx-nucleo/libraries/HAL_Driver/Src/HAL_EXTI.c @@ -0,0 +1,184 @@ +/* + ****************************************************************************** + * @file HAL_EXTI.c + * @version V1.0.0 + * @date 2020 + * @brief EXTI HAL module driver. + * This file provides firmware functions to manage the following + * functionalities of the General Purpose Input/Output (EXTI) peripheral: + * + Initialization functions + * + IO operation functions + ****************************************************************************** +*/ +#include "ACM32Fxx_HAL.h" + +/********************************************************************************* +* Function : HAL_EXTI_IRQHandler +* Description : Handle EXTI interrupt request. +* Input : huart: EXTI handle. +* Output : +* Author : Chris_Kyle Data : 2020�� +**********************************************************************************/ +void HAL_EXTI_IRQHandler(EXTI_HandleTypeDef *hexti) +{ + if (EXTI->PDR & hexti->u32_Line) + { + EXTI->PDR = hexti->u32_Line; + } +} + +/********************************************************************************* +* Function : HAL_EXTI_SetConfigLine +* Description : +* Input : +* Outpu : +* Author : Chris_Kyle Data : 2020年 +**********************************************************************************/ +HAL_StatusTypeDef HAL_EXTI_SetConfigLine(EXTI_HandleTypeDef *hexti) +{ + uint32_t lu32_IndexLine; + +#if (USE_FULL_ASSERT == 1) + if (!IS_EXTI_ALL_LINE(hexti->u32_Line)) return HAL_ERROR; + if (!IS_EXTI_MODE(hexti->u32_Mode)) return HAL_ERROR; + if (!IS_EXTI_TRIGGER(hexti->u32_Trigger)) return HAL_ERROR; + + /* Line0 ~ 15 trigger from GPIO */ + if (!(hexti->u32_Line >> 16)) + { + if (!IS_EXTI_GPIOSEL(hexti->u32_GPIOSel)) return HAL_ERROR; + } +#endif + + lu32_IndexLine = hexti->u32_Line; + + /* Interrupt Mode */ + if (hexti->u32_Mode == EXTI_MODE_INTERRUPT) + { + EXTI->IENR |= lu32_IndexLine; + EXTI->EENR &= ~lu32_IndexLine; + + NVIC_ClearPendingIRQ(EXTI_IRQn); + NVIC_EnableIRQ(EXTI_IRQn); + } + /* Event Mode */ + else if (hexti->u32_Mode == EXTI_MODE_EVENT) + { + EXTI->EENR |= lu32_IndexLine; + EXTI->IENR &= ~lu32_IndexLine; + } + + + if (hexti->u32_Trigger == EXTI_TRIGGER_RISING) + { + EXTI->RTENR |= lu32_IndexLine; + EXTI->FTENR &= ~lu32_IndexLine; + } + else if (hexti->u32_Trigger == EXTI_TRIGGER_FALLING) + { + EXTI->FTENR |= lu32_IndexLine; + EXTI->RTENR &= ~lu32_IndexLine; + } + else + { + EXTI->FTENR |= lu32_IndexLine; + EXTI->RTENR |= lu32_IndexLine; + } + + /* Line0 ~ 15 trigger from GPIO */ + if (!(hexti->u32_Line >> 16)) + { + lu32_IndexLine = 0; + + while(hexti->u32_Line >> lu32_IndexLine != 0x01) + { + lu32_IndexLine++; + } + + /* Line0 ~ 7 */ + if (lu32_IndexLine < 8) + { + EXTI->EXTICR1 = (EXTI->EXTICR1 & ~(0x0F << (lu32_IndexLine * 4))) | hexti->u32_GPIOSel << (lu32_IndexLine * 4); + } + /* Line8 ~ 15 */ + else + { + lu32_IndexLine -= 8; + + EXTI->EXTICR2 = (EXTI->EXTICR2 & ~(0x0F << (lu32_IndexLine * 4))) | hexti->u32_GPIOSel << (lu32_IndexLine * 4); + } + } + + return HAL_OK; +} + +/********************************************************************************* +* Function : HAL_EXTI_SoftTrigger +* Description : Software trigger EXTI +* Input : +* Outpu : +* Author : Chris_Kyle Data : 2020年 +**********************************************************************************/ +void HAL_EXTI_SoftTrigger(EXTI_HandleTypeDef *hexti) +{ +#if (USE_FULL_ASSERT == 1) + if (!IS_EXTI_ALL_LINE(hexti->u32_Line)) return; +#endif + + /* Set pending BIT */ + EXTI->SWIER |= hexti->u32_Line; +} + +/********************************************************************************* +* Function : HAL_EXTI_GetPending +* Description : Get interrupt pending bit of a dedicated line. +* Input : +* Outpu : +* Author : Chris_Kyle Data : 2020年 +**********************************************************************************/ +bool HAL_EXTI_GetPending(EXTI_HandleTypeDef *hexti) +{ +#if (USE_FULL_ASSERT == 1) + if (!IS_EXTI_ALL_LINE(hexti->u32_Line)) return HAL_ERROR; +#endif + + if (hexti->u32_Line & EXTI->PDR) + { + return true; + } + else + { + return false; + } +} + +/********************************************************************************* +* Function : HAL_EXTI_ClearPending +* Description : Clear interrupt pending bit of a dedicated line. +* Input : +* Outpu : +* Author : Chris_Kyle Data : 2020年 +**********************************************************************************/ +void HAL_EXTI_ClearPending(EXTI_HandleTypeDef *hexti) +{ +#if (USE_FULL_ASSERT == 1) + if (!IS_EXTI_ALL_LINE(hexti->u32_Line)) return; +#endif + + /* Clear pending status */ + EXTI->PDR |= hexti->u32_Line; +} + +/********************************************************************************* +* Function : HAL_EXTI_ClearAllPending +* Description : Clear all interrupt pending bit. +* Input : +* Outpu : +* Author : xwl Data : 2021年 +**********************************************************************************/ +void HAL_EXTI_ClearAllPending(void) +{ + /* Clear pending status */ + EXTI->PDR |= EXTI_LINE_MASK; +} + diff --git a/bsp/acm32f4xx-nucleo/libraries/HAL_Driver/Src/HAL_FSUSB.c b/bsp/acm32f4xx-nucleo/libraries/HAL_Driver/Src/HAL_FSUSB.c new file mode 100644 index 0000000000..fbae483272 --- /dev/null +++ b/bsp/acm32f4xx-nucleo/libraries/HAL_Driver/Src/HAL_FSUSB.c @@ -0,0 +1,372 @@ +/*********************************************************************** + * Filename : hal_lpuart.c + * Description : lpuart driver source file + * Author(s) : xwl + * version : V1.0 + * Modify date : 2019-11-19 + ***********************************************************************/ +#include "ACM32Fxx_HAL.h" + +static uint16_t ep1_stall[2]= {0}; // EP1 stall״̬ +static uint16_t ep2_stall[2]= {0}; // EP2 stall״̬ +static uint16_t ep3_stall[2]= {0}; // EP3 stall״̬ +static uint16_t ep4_stall[2]= {0}; // EP3 stall״̬ + +uint32_t HAL_FSUSB_MSP_Init(void) +{ + GPIO_InitTypeDef GPIO_init_para; + + System_Module_Reset(RST_USB); + System_Module_Enable(EN_USB); + + if( HAL_OK != System_USB_PHY_Config()) + { + return HAL_ERROR; + } + + SCU->PABADS = (SCU->PABADS | ( (0x3 << 11)) ); +// GPIO_init_para.Pin = GPIO_PIN_11 | GPIO_PIN_12; +// GPIO_init_para.Mode = GPIO_MODE_ANALOG; +// GPIO_init_para.Pull = GPIO_NOPULL; +// GPIO_init_para.Alternate = GPIO_FUNCTION_0; +// HAL_GPIO_Init(GPIOA, &GPIO_init_para); + + NVIC_ClearPendingIRQ(USB_IRQn); + NVIC_EnableIRQ(USB_IRQn); + + return HAL_OK; +} + +uint32_t HAL_FSUSB_Init(void) +{ + if (HAL_OK != HAL_FSUSB_MSP_Init()) + { + return HAL_ERROR; + } + + System_Delay(10); + + USBCTRL->WORKING_MODE = 0x04; //disconnect usb/ reset USBC + System_Delay(3000); + USBCTRL->WORKING_MODE = 0x09 ; //auto reset, fullspeed + + USBCTRL->EPxCSR[0] |= 1<<8; //enable EP0 + USBCTRL->EPxCSR[1] |= 1<<8; //enable EP1 + USBCTRL->EPxCSR[2] |= 1<<8; //enable EP2 + USBCTRL->EPxCSR[3] |= 1<<8; //enable EP3 + USBCTRL->EPxCSR[4] |= 1<<8; //enable EP4 + USBCTRL->EPADDR_CFG = 0x4321; + + USBINT->INT_EN = 0x92427; // enable Reset,Resume,Suspend,setup, EP1/2/3/4 OUT interrupt + + USBCTRL->WORKING_MODE |= (1<<6)|(1<<4); //connect + + return HAL_OK; +} + +uint16_t HAL_FSUSB_Get_FIFO_Length(uint8_t ep_index) +{ + return USBCTRL->EPxCSR[ep_index]&0xff; +} + +void HAL_USB_Clear_FIFO(uint8_t ep_index, uint8_t ep_dir) +{ + USBCTRL->EPxCSR[ep_index] |= 1<<9; +} + +uint16_t HAL_USB_Get_Stall_Status(uint8_t ep_index, uint8_t ep_dir) +{ + switch(ep_index) + { + case USB_EP1: + { + if(ep_dir == EP_DIR_IN) return ep1_stall[0]; //in + else return ep1_stall[1]; //out + } + case USB_EP2: + { + if(ep_dir == EP_DIR_IN) return ep2_stall[0]; //in + else return ep2_stall[1]; //out + } + case USB_EP3: + { + if(ep_dir == EP_DIR_IN) return ep3_stall[0]; //in + else return ep3_stall[1]; //out + } + case USB_EP4: + { + if(ep_dir == EP_DIR_IN) return ep4_stall[0]; //in + else return ep4_stall[1]; //out + } + + default: return 0xff; + } +} + +void usb_clear_stall(uint8_t ep_index, uint8_t ep_dir) +{ + switch(ep_index) + { + case USB_EP1: + { + if(ep_dir == EP_DIR_IN) ep1_stall[0]=0x0000; //in + else ep1_stall[1]=0x0000; //out + break; + } + case USB_EP2: + { + if(ep_dir == EP_DIR_IN) ep2_stall[0]=0x0000; //in + else ep2_stall[1]=0x0000; //out + break; + } + case USB_EP3: + { + if(ep_dir == EP_DIR_IN) ep3_stall[0]=0x0000; //in + else ep3_stall[1]=0x0000; //out + break; + } + case USB_EP4: + { + if(ep_dir == EP_DIR_IN) ep4_stall[0]=0x0000; //in + else ep4_stall[1]=0x0000; //out + break; + } + + default: return; + } + + USBCTRL->EPxCSR[ep_index] = 0x02100; //clear in/out toggle,stall,stall status + USBCTRL->EPxCSR[ep_index] |= (1<<18)|(1<<15); //enable change +// flag_clear_stall=0; +} + + + +void usb_send_stall(uint8_t ep_index, uint8_t ep_dir) +{ + switch(ep_index) + { + case USB_EP1: + { + if(ep_dir == EP_DIR_IN) ep1_stall[0]=0x0001; //in + else ep1_stall[1]=0x0001; //out + break; + } + case USB_EP2: + { + if(ep_dir == EP_DIR_IN) ep2_stall[0]=0x0001; //in + else ep2_stall[1]=0x0001; //out + break; + } + case USB_EP3: + { + if(ep_dir == EP_DIR_IN) ep3_stall[0]=0x0001; //in + else ep3_stall[1]=0x0001; //out + break; + } + case USB_EP4: + { + if(ep_dir == EP_DIR_IN) ep4_stall[0]=0x0001; //in + else ep4_stall[1]=0x0001; //out + break; + } + + default: return; + } + + USBCTRL->EPxCSR[ep_index] |= (1<<12); +} + + +void HAL_FSUSB_Read_EP_MEM8(uint8_t *dst, uint32_t length, uint32_t fifo_offset, uint8_t ep_index) +{ + uint8_t *src; + + src = (uint8_t *)(USB_BASE+0x200+(ep_index<<6)+fifo_offset); + while(length--) + { + *dst++ = *src++; + } +} + +void HAL_FSUSB_Write_EP_MEM8(uint8_t *src, uint32_t length, uint32_t fifo_offset, uint8_t ep_index) +{ + + uint8_t *dst; + + dst = (uint8_t *)(USB_BASE+0x200+(ep_index<<6)+fifo_offset); + + while(length--) + { + *dst++ = *src++; + } +} + + +uint8_t HAL_FSUSB_Start_EP_Transfer(uint32_t length,uint8_t ep_index) +{ + uint8_t intoken_cnt; + + USBCTRL->EPxSENDBN[ep_index]= length; + + while(1) + { + // if a new out data packet received, return error to caller + if( (USBINT->INT_STAT_RAW & MASK_EPX_OUT(ep_index)) && (USBINT->INT_STAT_RAW & MASK_EPX_ACK(ep_index)) ) + { + USBINT->INT_CLR = MASK_EPX_OUT(ep_index); + USBINT->INT_CLR = MASK_EPX_ACK(ep_index); + return ERROR_OUT_OUT; + } + // wait for IN token to start transfer + if(USBINT->INT_STAT_RAW & MASK_EPX_IN(ep_index) ) + { + USBINT->INT_CLR = MASK_EPX_IN(ep_index); + USBCTRL->WORKING_MODE |= (1<<11);//return NAK when timeout + USBCTRL->EPxCSR[ep_index] |= (1<<10);//data is ready for tx + break; + } + } + + + while(1) + { + if( USBCTRL->EPxCSR[ep_index]&0x1000000 ) //received ACK from host + { + USBINT->INT_CLR = MASK_EPX_ACK(ep_index); + USBINT->INT_CLR = MASK_EPX_IN(ep_index); + return 0;//pass + } + + if(USBINT->INT_STAT_RAW & (1<<21) ) // timeout occurs when wait ACK + { + USBINT->INT_CLR = (1<<21); + intoken_cnt = 4; + while(intoken_cnt) // wait 3 SOF frame for bad signal, during this time, device will send NACK when IN token received + { + if(USBINT->INT_STAT_RAW & (1<<3)) + { + intoken_cnt --; + USBINT->INT_CLR = (1<<3); + } + } + USBINT->INT_CLR = MASK_EPX_TIMEOUT(ep_index); // device recover to send data packet after IN token received + } + + if(USBINT->INT_STAT_RAW & MASK_EPX_OUT(ep_index)) + { + return ERROR_IN_OUT; + } + } +} + + +uint8_t HAL_FSUSB_Send_Data(uint8_t *buffer,uint32_t length,uint8_t ep_index) +{ + uint8_t ret; + + while(length>=EPX_MAX_PACKET_SIZE) + { + HAL_FSUSB_Write_EP_MEM8(buffer,EPX_MAX_PACKET_SIZE,0, ep_index); + ret = HAL_FSUSB_Start_EP_Transfer(EPX_MAX_PACKET_SIZE, ep_index); + if(ret == ERROR_OUT_OUT) + { + if( USBCTRL->EPxCSR[ep_index] & ( 1<< 19) )//Toggle error + { + USBCTRL->EPxCSR[ep_index] ^= (1<<17); //out toggle want + USBCTRL->EPxCSR[ep_index] |= (1<<18); //update want toggle; + } + USBCTRL->EPxCSR[ep_index] |= 1<<11; //set rx ready + continue; // received a same packet, has processed this packet, just fill respoonse to fifo and send it to host + } + else if(ret != 0) + { + return 1; // send data fail, exit with error code to let caller know + } + length -= EPX_MAX_PACKET_SIZE; + buffer += EPX_MAX_PACKET_SIZE; + } + // remaining data, less than EPX_MAX_PACKET_SIZE + while(length>0) + { + HAL_FSUSB_Write_EP_MEM8(buffer,length,0,ep_index); + ret = HAL_FSUSB_Start_EP_Transfer(length,ep_index); + if(ret == ERROR_OUT_OUT) + { + if( USBCTRL->EPxCSR[ep_index] & ( 1<< 19) )//Toggle error + { + USBCTRL->EPxCSR[ep_index] ^= (1<<17); //out toggle want + USBCTRL->EPxCSR[ep_index] |= (1<<18); //update want toggle; + } + USBCTRL->EPxCSR[ep_index] |= 1<<11; //set rx ready + continue; + } + else if(ret != 0) + { + return 1; // send data fail, exit with error code to let caller know + } + length -= length; + buffer += length; + } + + return 0; +} + + +void HAL_FSUSB_Receive_Data(uint8_t *buffer,uint32_t length,uint8_t ep_index) +{ + uint32_t len; + + while(length>0) + { + while(1) + { + // wait an out data packet and device has sent an ACK to HOST + if( (USBINT->INT_STAT_RAW & MASK_EPX_OUT(ep_index)) && (USBINT->INT_STAT_RAW & MASK_EPX_ACK(ep_index)) ) + { + break; + } + } + USBINT->INT_CLR = MASK_EPX_OUT(ep_index); + USBINT->INT_CLR = MASK_EPX_ACK(ep_index); + + if( USBCTRL->EPxCSR[ep_index] & ( 1<< 19) )//Toggle error + { + USBCTRL->EPxCSR[ep_index] ^= (1<<17); //out toggle want + USBCTRL->EPxCSR[ep_index] |= (1<<18); //update want toggle; + USBCTRL->EPxCSR[ep_index] |= 1<<11; //set rx ready, wait for a new packet + continue; //discard this packet + } + + len =HAL_FSUSB_Get_FIFO_Length(ep_index); + HAL_FSUSB_Read_EP_MEM8(buffer,len,0,ep_index); + USBCTRL->EPxCSR[ep_index] |= 1<<11; //set rx ready to wait next packet + + length -= len; + buffer += len; + } +} + + +//ep_indexʾ˵ +void HAL_FSUSB_EP0_Send_Empty_Packet(void) +{ + HAL_FSUSB_Start_EP_Transfer(0,USB_EP0); +} + +void HAL_FSUSB_EP0_Send_Stall(void) +{ + USBCTRL->EPxCSR[0] |= 1<<12; + while(!(USBCTRL->EPxCSR[0] &0x2000)); + USBCTRL->EPxCSR[0] |= 0x2000; +} + + + + + + + + + + diff --git a/bsp/acm32f4xx-nucleo/libraries/HAL_Driver/Src/HAL_GPIO.c b/bsp/acm32f4xx-nucleo/libraries/HAL_Driver/Src/HAL_GPIO.c new file mode 100644 index 0000000000..8f8108aef4 --- /dev/null +++ b/bsp/acm32f4xx-nucleo/libraries/HAL_Driver/Src/HAL_GPIO.c @@ -0,0 +1,703 @@ +/* + ****************************************************************************** + * @file HAL_GPIO.c + * @version V1.0.0 + * @date 2020 + * @brief GPIO HAL module driver. + * This file provides firmware functions to manage the following + * functionalities of the General Purpose Input/Output (GPIO) peripheral: + * @ Initialization functions + * @ IO operation functions + ****************************************************************************** +*/ +#include "ACM32Fxx_HAL.h" + +/********************************************************************************* +* Function : HAL_GPIO_IRQHandler +* Description : GPIO interrupt Handler +* Input : +* Outpu : +* Author : Chris_Kyle Data : 2020? +**********************************************************************************/ +void HAL_GPIO_IRQHandler(enum_GPIOx_t fe_GPIO, uint32_t fu32_GPIO_Pin) +{ + GPIO_TypeDef *GPIOx; + + switch (fe_GPIO) + { + case GPIOA: + case GPIOB: + { + GPIOx = GPIOAB; + }break; + + case GPIOC: + case GPIOD: + { + GPIOx = GPIOCD; + }break; + + case GPIOE: + case GPIOF: + { + GPIOx = GPIOEF; + }break; + + default: break; + } + + if (fe_GPIO == GPIOB || fe_GPIO == GPIOD || fe_GPIO == GPIOF) + { + fu32_GPIO_Pin <<= 16; + } + + if (GPIOx->RIS & fu32_GPIO_Pin) + { + GPIOx->IC = fu32_GPIO_Pin; + + /* user can call your application process function here */ + /* ...... */ + } +} + +/********************************************************************************* +* Function : HAL_GPIO_Init +* Description : Initializes the GPIOx peripheral according to the specified parameters in the GPIO_Init +* Input : fe_GPIO: to select the GPIO peripheral. +* Input : GPIO_Init: pointer to a GPIO_InitTypeDef structure that contains + the configuration information for the specified GPIO peripheral. +* Outpu : +* Author : Chris_Kyle Data : 2020? +**********************************************************************************/ +void HAL_GPIO_Init(enum_GPIOx_t fe_GPIO, GPIO_InitTypeDef *GPIO_Init) +{ + uint32_t lu32_Position = 0; + uint32_t lu32_Current_Pin; + uint32_t lu32_Position_Mask; + + volatile uint32_t *lu32_SEL1 = NULL; // ??? -> 1???䨮?????1 + volatile uint32_t *lu32_SEL2 = NULL; // ??? -> 1???䨮?????2 + volatile uint32_t *lu32_PollUP = NULL; // ??? -> ?-???????? + volatile uint32_t *lu32_PollDown = NULL; // ??? -> ??-???????? + volatile uint32_t *lu32_ODEnable = NULL; // ??? -> ?a??1????? + volatile uint32_t *lu32_ADS = NULL; // ??? -> y????a???????? + + GPIO_TypeDef *GPIOx; + +#if (USE_FULL_ASSERT == 1) + /* Check the parameters */ + if (!IS_GPIO_ALL_INSTANCE(fe_GPIO)) return; + if (!IS_GPIO_PIN(GPIO_Init->Pin)) return; + if (!IS_GPIO_MODE(GPIO_Init->Mode)) return; +#endif + + switch (fe_GPIO) + { + case GPIOA: + case GPIOB: + { + GPIOx = GPIOAB; + + System_Module_Enable(EN_GPIOAB); + + lu32_PollUP = &(SCU->PABPUR); + lu32_PollDown = &(SCU->PABPDR); + lu32_ODEnable = &(SCU->PABODR); + lu32_ADS = &(SCU->PABADS); + + if (fe_GPIO == GPIOB) + { + GPIO_Init->Pin <<= 16; + + lu32_SEL1 = &(SCU->PBSEL1); + lu32_SEL2 = &(SCU->PBSEL2); + } + else + { + lu32_SEL1 = &(SCU->PASEL1); + lu32_SEL2 = &(SCU->PASEL2); + } + }break; + + case GPIOC: + case GPIOD: + { + GPIOx = GPIOCD; + + System_Module_Enable(EN_GPIOCD); + + lu32_PollUP = &(SCU->PCDPUR); + lu32_PollDown = &(SCU->PCDPDR); + lu32_ODEnable = &(SCU->PCDODR); + lu32_ADS = &(SCU->PCDADS); + + if (fe_GPIO == GPIOD) + { + GPIO_Init->Pin <<= 16; + + lu32_SEL1 = &(SCU->PDSEL1); + lu32_SEL2 = &(SCU->PDSEL2); + } + else + { + lu32_SEL1 = &(SCU->PCSEL1); + lu32_SEL2 = &(SCU->PCSEL2); + } + }break; + + case GPIOE: + case GPIOF: + { + GPIOx = GPIOEF; + + System_Module_Enable(EN_GPIOEF); + + lu32_PollUP = &(SCU->PEFPUR); + lu32_PollDown = &(SCU->PEFPDR); + lu32_ODEnable = &(SCU->PEFODR); + lu32_ADS = &(SCU->PEFADS); + + if (fe_GPIO == GPIOF) + { + GPIO_Init->Pin <<= 16; + + lu32_SEL1 = &(SCU->PFSEL1); + } + else + { + lu32_SEL1 = &(SCU->PESEL1); + lu32_SEL2 = &(SCU->PESEL2); + } + }break; + + default: break; + } + + /* Configure Select pins */ + while ((GPIO_Init->Pin) >> lu32_Position != 0) + { + /* Get current pin position */ + lu32_Current_Pin = (GPIO_Init->Pin) & (1uL << lu32_Position); + + if (lu32_Current_Pin) + { + switch (GPIO_Init->Mode) + { + /* GPIO IN Function */ + case GPIO_MODE_INPUT: + { + GPIOx->DIR &= ~lu32_Current_Pin; + }break; + + /* GPIO OUT Function */ + case GPIO_MODE_OUTPUT_PP: + case GPIO_MODE_OUTPUT_OD: + { + GPIOx->DIR |= lu32_Current_Pin; + }break; + + /* Alternate Function */ + case GPIO_MODE_AF_PP: + case GPIO_MODE_AF_OD: + { + /* Get Position Mask */ + if (lu32_Position < 16) + { /* GOIOA?GPIOC?GPIOE */ + lu32_Position_Mask = lu32_Position; + } + else + { /* GPIOB?GPIOD?GPIOF */ + lu32_Position_Mask = lu32_Position - 16; + } + + /* SET GPIO Function */ + if (lu32_Position_Mask < 8) + { + *lu32_SEL1 = (*lu32_SEL1 & ~(0xF << (lu32_Position_Mask * 4))) | (GPIO_Init->Alternate << (lu32_Position_Mask * 4)); + } + else + { + *lu32_SEL2 = (*lu32_SEL2 & ~(0xF << ((lu32_Position_Mask - 8) * 4))) | (GPIO_Init->Alternate << ((lu32_Position_Mask - 8) * 4)); + } + }break; + + /* GPIO INT Function */ + case GPIO_MODE_IT_RISING: + case GPIO_MODE_IT_FALLING: + case GPIO_MODE_IT_RISING_FALLING: + case GPIO_MODE_IT_HIGH_LEVEL: + case GPIO_MODE_IT_LOW_LEVEL: + { + /* Set direction Input?Enable INT */ + GPIOx->DIR &= ~lu32_Current_Pin; + GPIOx->IEN |= lu32_Current_Pin; + + /* Single edge */ + if (GPIO_Init->Mode == GPIO_MODE_IT_RISING || GPIO_Init->Mode == GPIO_MODE_IT_FALLING) + { + /* edge trigger */ + GPIOx->IS &= ~lu32_Current_Pin; + /* Single trigger */ + GPIOx->IBE &= ~lu32_Current_Pin; + + if (GPIO_Init->Mode == GPIO_MODE_IT_RISING) + { + GPIOx->IEV |= lu32_Current_Pin; + } + else + { + GPIOx->IEV &= ~lu32_Current_Pin; + } + } + + /* Double edge */ + if (GPIO_Init->Mode == GPIO_MODE_IT_RISING_FALLING) + { + /* edge trigger */ + GPIOx->IS &= ~lu32_Current_Pin; + /* Double trigger */ + GPIOx->IBE |= lu32_Current_Pin; + } + + /* LEVEL trigger */ + if (GPIO_Init->Mode == GPIO_MODE_IT_HIGH_LEVEL || GPIO_Init->Mode == GPIO_MODE_IT_LOW_LEVEL) + { + /* LEVEL trigger */ + GPIOx->IS |= lu32_Current_Pin; + + if (GPIO_Init->Mode == GPIO_MODE_IT_HIGH_LEVEL) + { + GPIOx->IEV |= lu32_Current_Pin; + } + else + { + GPIOx->IEV &= ~lu32_Current_Pin; + } + } + }break; + + default: break; + } + + /* Set Pull UP or DOWN or NO */ + if (GPIO_Init->Pull == GPIO_NOPULL) + { + *lu32_PollUP &= ~lu32_Current_Pin; + *lu32_PollDown &= ~lu32_Current_Pin; + } + else if (GPIO_Init->Pull == GPIO_PULLUP) + { + *lu32_PollUP |= lu32_Current_Pin; + *lu32_PollDown &= ~lu32_Current_Pin; + } + else if (GPIO_Init->Pull == GPIO_PULLDOWN) + { + *lu32_PollUP &= ~lu32_Current_Pin; + *lu32_PollDown |= lu32_Current_Pin; + } + + /* Set Open Drain Mode */ + if (GPIO_Init->Mode & GPIO_MODE_OD_MASK) + { + *lu32_ODEnable |= lu32_Current_Pin; + } + else + { + *lu32_ODEnable &= ~lu32_Current_Pin; + } + + /* GPIO Function */ + if (GPIO_Init->Mode & GPIO_MODE_IO_MASK) + { + /* Get Position Mask */ + if (lu32_Position < 16) + { /* GOIOA?GPIOC?GPIOE */ + lu32_Position_Mask = lu32_Position; + } + else + { /* GPIOB?GPIOD?GPIOF */ + lu32_Position_Mask = lu32_Position - 16; + } + + /* SET GPIO Function */ + if (lu32_Position_Mask < 8) + { + *lu32_SEL1 = (*lu32_SEL1 & ~(0xF << (lu32_Position_Mask * 4))) | (GPIO_FUNCTION_0 << (lu32_Position_Mask * 4)); + } + else + { + *lu32_SEL2 = (*lu32_SEL2 & ~(0xF << ((lu32_Position_Mask - 8) * 4))) | (GPIO_FUNCTION_0 << ((lu32_Position_Mask - 8) * 4)); + } + } + + /* SET Digital or Analog */ + if (GPIO_Init->Mode == GPIO_MODE_ANALOG) + { + *lu32_ADS |= lu32_Current_Pin; + } + else + { + *lu32_ADS &= ~lu32_Current_Pin; + } + } + + lu32_Position++; + } +} + +/********************************************************************************* +* Function : HAL_GPIO_DeInit +* Description : De-initializes the GPIOx peripheral registers to their default reset values. +* Input : fe_GPIOoto select the GPIO peripheral. +* Input : fu32_Pinospecifies the port bit to be written. + This parameter can be one of GPIO_PIN_x where x can be (0..15). +* Outpu : +* Author : Chris_Kyle Data : 2020 +**********************************************************************************/ +void HAL_GPIO_DeInit(enum_GPIOx_t fe_GPIO, uint32_t fu32_Pin) +{ + uint32_t lu32_Position = 0; + uint32_t lu32_Current_Pin; + uint32_t lu32_Position_Mask; + + volatile uint32_t *lu32_SEL1 = NULL; // ??? -> 1???䨮?????1 + volatile uint32_t *lu32_SEL2 = NULL; // ??? -> 1???䨮?????2 + volatile uint32_t *lu32_PollUP = NULL; // ??? -> ?-???????? + volatile uint32_t *lu32_PollDown = NULL; // ??? -> ??-???????? + volatile uint32_t *lu32_ODEnable = NULL; // ??? -> ?a??1????? + volatile uint32_t *lu32_ADS = NULL; // ??? -> y????a???????? + + GPIO_TypeDef *GPIOx; + +#if (USE_FULL_ASSERT == 1) + /* Check the parameters */ + if (!IS_GPIO_ALL_INSTANCE(fe_GPIO)) return; + if (!IS_GPIO_PIN(fu32_Pin)) return; +#endif + + switch (fe_GPIO) + { + case GPIOA: + case GPIOB: + { + GPIOx = GPIOAB; + + System_Module_Enable(EN_GPIOAB); + + lu32_PollUP = &(SCU->PABPUR); + lu32_PollDown = &(SCU->PABPDR); + lu32_ODEnable = &(SCU->PABODR); + lu32_ADS = &(SCU->PABADS); + + if (fe_GPIO == GPIOB) + { + fu32_Pin <<= 16; + + lu32_SEL1 = &(SCU->PBSEL1); + lu32_SEL2 = &(SCU->PBSEL2); + } + else + { + lu32_SEL1 = &(SCU->PASEL1); + lu32_SEL2 = &(SCU->PASEL2); + } + }break; + + case GPIOC: + case GPIOD: + { + GPIOx = GPIOCD; + + System_Module_Enable(EN_GPIOCD); + + lu32_PollUP = &(SCU->PCDPUR); + lu32_PollDown = &(SCU->PCDPDR); + lu32_ODEnable = &(SCU->PCDODR); + lu32_ADS = &(SCU->PCDADS); + + if (fe_GPIO == GPIOD) + { + fu32_Pin <<= 16; + + lu32_SEL1 = &(SCU->PDSEL1); + lu32_SEL2 = &(SCU->PDSEL2); + } + else + { + lu32_SEL1 = &(SCU->PCSEL1); + lu32_SEL2 = &(SCU->PCSEL2); + } + }break; + + case GPIOE: + case GPIOF: + { + GPIOx = GPIOEF; + + System_Module_Enable(EN_GPIOEF); + + lu32_PollUP = &(SCU->PEFPUR); + lu32_PollDown = &(SCU->PEFPDR); + lu32_ODEnable = &(SCU->PEFODR); + lu32_ADS = &(SCU->PEFADS); + + if (fe_GPIO == GPIOF) + { + fu32_Pin <<= 16; + + lu32_SEL1 = &(SCU->PFSEL1); + } + else + { + lu32_SEL1 = &(SCU->PESEL1); + lu32_SEL2 = &(SCU->PESEL2); + } + }break; + + default: break; + } + + /* Configure Select pins */ + while (fu32_Pin >> lu32_Position != 0) + { + /* Get current pin position */ + lu32_Current_Pin = fu32_Pin & (1uL << lu32_Position); + + if (lu32_Current_Pin) + { + /* GPIO IN Function */ + GPIOx->DIR &= ~lu32_Current_Pin; + GPIOx->CLR |= lu32_Current_Pin; + + /* Disable Enable INT */ + GPIOx->IEN &= ~lu32_Current_Pin; + + /* Clear trigger config */ + GPIOx->IS &= ~lu32_Current_Pin; + GPIOx->IBE &= ~lu32_Current_Pin; + GPIOx->IEV &= ~lu32_Current_Pin; + + + /* Get Position Mask */ + if (lu32_Position < 16) + { /* GOIOA?GPIOC?GPIOE */ + lu32_Position_Mask = lu32_Position; + } + else + { /* GPIOB?GPIOD?GPIOF */ + lu32_Position_Mask = lu32_Position - 16; + } + + /* SET GPIO Function */ + if (lu32_Position_Mask < 8) + { + *lu32_SEL1 &= ~(0xF << (lu32_Position_Mask * 4)); + } + else + { + *lu32_SEL2 &= ~(0xF << ((lu32_Position_Mask - 8) * 4)); + } + + /* NO Pull */ + *lu32_PollUP &= ~lu32_Current_Pin; + *lu32_PollDown &= ~lu32_Current_Pin; + + /* Not Open Drain */ + *lu32_ODEnable &= ~lu32_Current_Pin; + + /* Analog Mode */ + *lu32_ADS |= lu32_Current_Pin; + } + + lu32_Position++; + } +} + +/********************************************************************************* +* Function : HAL_GPIO_AnalogEnable +* Description : Quickly Configure to analog function +* Input : fe_GPIOoto select the GPIO peripheral. +* Input : fu32_Pinospecifies the port bit to be written. + This parameter can be one of GPIO_PIN_x where x can be (0..15). +* Outpu : +* Author : Chris_Kyle Data : 2020? +**********************************************************************************/ +void HAL_GPIO_AnalogEnable(enum_GPIOx_t fe_GPIO, uint32_t fu32_Pin) +{ + uint32_t lu32_Position = 0; + uint32_t lu32_Current_Pin; + + volatile uint32_t *lp32_ADS = NULL; // ??? -> y????a???????? + + GPIO_TypeDef *GPIOx; + +#if (USE_FULL_ASSERT == 1) + /* Check the parameters */ + if (!IS_GPIO_ALL_INSTANCE(fe_GPIO)) return; + if (!IS_GPIO_PIN(fu32_Pin)) return; +#endif + + switch (fe_GPIO) + { + case GPIOA: + case GPIOB: + { + System_Module_Enable(EN_GPIOAB); + + lp32_ADS = &(SCU->PABADS); + + if (fe_GPIO == GPIOB) + { + fu32_Pin <<= 16; + } + }break; + + case GPIOC: + case GPIOD: + { + System_Module_Enable(EN_GPIOCD); + + lp32_ADS = &(SCU->PCDADS); + + if (fe_GPIO == GPIOD) + { + fu32_Pin <<= 16; + } + }break; + + case GPIOE: + case GPIOF: + { + System_Module_Enable(EN_GPIOEF); + + lp32_ADS = &(SCU->PEFADS); + + if (fe_GPIO == GPIOF) + { + fu32_Pin <<= 16; + } + }break; + + default: break; + } + + /* Configure Select pins */ + while ((fu32_Pin) >> lu32_Position != 0) + { + /* Get current pin position */ + lu32_Current_Pin = (fu32_Pin) & (1uL << lu32_Position); + + if (lu32_Current_Pin) + { + *lp32_ADS |= lu32_Current_Pin; + } + + lu32_Position++; + } +} + +/********************************************************************************* +* Function : HAL_GPIO_WritePin +* Description : Set or clear the selected data port bit. +* Input : +* Outpu : +* Author : Chris_Kyle Data : 2020? +**********************************************************************************/ +void HAL_GPIO_WritePin(enum_GPIOx_t fe_GPIO, uint32_t fu32_GPIO_Pin, enum_PinState_t fe_PinState) +{ + GPIO_TypeDef *GPIOx; + +#if (USE_FULL_ASSERT == 1) + /* Check the parameters */ + if (!IS_GPIO_ALL_INSTANCE(fe_GPIO)) return; + if (!IS_GPIO_PIN(fu32_GPIO_Pin)) return; + if (!IS_GPIO_PIN_ACTION(fe_PinState)) return; +#endif + + switch (fe_GPIO) + { + case GPIOA: + case GPIOB: + { + GPIOx = GPIOAB; + }break; + + case GPIOC: + case GPIOD: + { + GPIOx = GPIOCD; + }break; + + case GPIOE: + case GPIOF: + { + GPIOx = GPIOEF; + }break; + + default: break; + } + + if (fe_GPIO == GPIOB || fe_GPIO == GPIOD || fe_GPIO == GPIOF) + { + fu32_GPIO_Pin <<= 16; + } + + if (GPIO_PIN_SET == fe_PinState) + { + GPIOx->ODATA |= fu32_GPIO_Pin; + } + else + { + GPIOx->ODATA &= ~fu32_GPIO_Pin; + } +} + +/********************************************************************************* +* Function : HAL_GPIO_ReadPin +* Description : Read the specified input port pin. +* Input : +* Outpu : +* Author : Chris_Kyle Data : 2020? +**********************************************************************************/ +enum_PinState_t HAL_GPIO_ReadPin(enum_GPIOx_t fe_GPIO, uint32_t fu32_GPIO_Pin) +{ + GPIO_TypeDef *GPIOx; + + switch (fe_GPIO) + { + case GPIOA: + case GPIOB: + { + GPIOx = GPIOAB; + }break; + + case GPIOC: + case GPIOD: + { + GPIOx = GPIOCD; + }break; + + case GPIOE: + case GPIOF: + { + GPIOx = GPIOEF; + }break; + + default: break; + } + + if (fe_GPIO == GPIOB || fe_GPIO == GPIOD || fe_GPIO == GPIOF) + { + fu32_GPIO_Pin <<= 16; + } + + if (GPIOx->IDATA & fu32_GPIO_Pin) + { + return GPIO_PIN_SET; + } + else + { + return GPIO_PIN_CLEAR; + } +} + diff --git a/bsp/acm32f4xx-nucleo/libraries/HAL_Driver/Src/HAL_I2C.c b/bsp/acm32f4xx-nucleo/libraries/HAL_Driver/Src/HAL_I2C.c new file mode 100644 index 0000000000..a35494ecc3 --- /dev/null +++ b/bsp/acm32f4xx-nucleo/libraries/HAL_Driver/Src/HAL_I2C.c @@ -0,0 +1,1143 @@ +/* + ****************************************************************************** + * @file HAL_I2C.c + * @version V1.0.0 + * @date 2020 + * @brief I2C HAL module driver. + * This file provides firmware functions to manage the following + * functionalities of the Inter Integrated Circuit (I2C) peripheral: + * @ Initialization and de-initialization functions + * @ IO operation functions + * @ Peripheral Control functions + ****************************************************************************** +*/ +#include "ACM32Fxx_HAL.h" + +/* Private functions for I2C */ +static HAL_StatusTypeDef I2C_Set_Clock_Speed(I2C_HandleTypeDef *hi2c, uint32_t ClockSpeed); +static HAL_StatusTypeDef I2C_Master_Request_Write(I2C_HandleTypeDef *hi2c, uint8_t DevAddress, uint32_t Timeout); +static HAL_StatusTypeDef I2C_Master_Request_Read(I2C_HandleTypeDef *hi2c, uint8_t DevAddress, uint32_t Timeout); +static HAL_StatusTypeDef I2C_Check_Device_Ready(I2C_HandleTypeDef *hi2c, uint8_t DevAddress, uint32_t Timeout); +static HAL_StatusTypeDef I2C_WaitOnFlagUntilTimeout(I2C_HandleTypeDef *hi2c, uint32_t Flag, FlagStatus Status, uint32_t Timeout); +/************************************************************************ + * function : HAL_I2C_IRQHandler + * Description: This function handles I2C interrupt request. + * input : hi2c : pointer to a I2C_HandleTypeDef structure that contains + * the configuration information for I2C module + ************************************************************************/ +__weak void HAL_I2C_IRQHandler(I2C_HandleTypeDef *hi2c) +{ + uint32_t i; + + /* Slave ADDR1 Interrupt */ + if (READ_BIT(hi2c->Instance->SR, I2C_SR_RX_ADDR1)) + { + /* Clear ADDR1 Interrupt Flag */ + hi2c->Instance->SR = READ_BIT(hi2c->Instance->SR, I2C_SR_RX_ADDR1); + + /* Slave Transmit */ + if (READ_BIT(hi2c->Instance->SR, I2C_SR_SRW)) + { + i = 1; + + /* Wait for transmission End*/ + while(!READ_BIT(hi2c->Instance->SR, I2C_SR_MTF)); + /* Clear MTF */ + hi2c->Instance->SR = READ_BIT(hi2c->Instance->SR, I2C_SR_MTF); + + /* BUS BUSY */ + while(READ_BIT(hi2c->Instance->SR, I2C_SR_BUS_BUSY)) + { + if (i >= hi2c->Tx_Size && hi2c->Tx_Size != 0) + { + break; + } + + if (READ_BIT(hi2c->Instance->SR, I2C_SR_MTF)) + { + /* Clear MTF */ + hi2c->Instance->SR = READ_BIT(hi2c->Instance->SR, I2C_SR_MTF); + + } + + if (READ_BIT(hi2c->Instance->SR, I2C_SR_TXE)) + { + hi2c->Instance->DR = hi2c->Tx_Buffer[i++]; + hi2c->Tx_Count++; + } + } + + /* Set Slave machine is DILE */ + hi2c->Slave_TxState = SLAVE_TX_STATE_IDLE; + } + /* Slave Receive */ + else + { + i = 0; + + /* Wait for transmission End*/ + while(!READ_BIT(hi2c->Instance->SR, I2C_SR_MTF)); + /* Clear MTF */ + hi2c->Instance->SR = READ_BIT(hi2c->Instance->SR, I2C_SR_MTF); + + /* BUS BUSY */ + while(READ_BIT(hi2c->Instance->SR, I2C_SR_BUS_BUSY)) + { + /* Receive Data */ + if (READ_BIT(hi2c->Instance->SR, I2C_SR_RXNE)) + { + hi2c->Rx_Buffer[i++] = hi2c->Instance->DR; + + /* Wait for transmission End*/ + while(!READ_BIT(hi2c->Instance->SR, I2C_SR_MTF)); + /* Clear MTF */ + hi2c->Instance->SR = READ_BIT(hi2c->Instance->SR, I2C_SR_MTF); + + hi2c->Rx_Count++; + + if (hi2c->Rx_Size != 0) + { + if (i >= hi2c->Rx_Size) + { + break; + } + } + } + } + + /* Set Slave machine is DILE */ + hi2c->Slave_RxState = SLAVE_RX_STATE_IDLE; + } + + if (hi2c->Slave_RxState == SLAVE_RX_STATE_IDLE && hi2c->Slave_TxState == SLAVE_TX_STATE_IDLE) + { + /* Disable RX_ADDR1_INT_EN */ + CLEAR_BIT(hi2c->Instance->CR, I2C_CR_RX_ADDR1_INT_EN); + } + } + + /* STOP Flag Interrupt */ + if (READ_BIT(hi2c->Instance->SR, I2C_SR_STOPF)) + { + /* Clear STOPF Interrupt Flag */ + hi2c->Instance->SR = READ_BIT(hi2c->Instance->SR, I2C_SR_STOPF); + + /* Clear STOPF */ + CLEAR_BIT(hi2c->Instance->CR, I2C_CR_STOPF_INTEN); + + if (hi2c->I2C_STOPF_Callback != NULL) + { + hi2c->I2C_STOPF_Callback(); + } + } +} + +/************************************************************************ + * function : HAL_I2C_MspInit + * Description: + * input : hi2c : pointer to a I2C_HandleTypeDef structure that contains + * the configuration information for I2C module + ************************************************************************/ +__weak void HAL_I2C_MspInit(I2C_HandleTypeDef *hi2c) +{ + /* + NOTE : This function should be modified by the user. + */ + + /* For Example */ + GPIO_InitTypeDef GPIO_Handle; + + /* I2C1 */ + if (hi2c->Instance == I2C1) + { + /* Enable Clock */ + System_Module_Enable(EN_I2C1); + System_Module_Enable(EN_GPIOAB); + + /* I2C1 SDA PortB Pin7 */ + /* I2C1 SCL PortB Pin6 */ + GPIO_Handle.Pin = GPIO_PIN_6 | GPIO_PIN_7; + GPIO_Handle.Mode = GPIO_MODE_AF_PP; + GPIO_Handle.Pull = GPIO_PULLUP; + GPIO_Handle.Alternate = GPIO_FUNCTION_6; + HAL_GPIO_Init(GPIOB, &GPIO_Handle); + + /* Clear Pending Interrupt */ + NVIC_ClearPendingIRQ(I2C1_IRQn); + + /* Enable External Interrupt */ + NVIC_EnableIRQ(I2C1_IRQn); + } + /* I2C2 */ + else if (hi2c->Instance == I2C2) + { + } +} + +/************************************************************************ + * function : HAL_I2C_MspDeInit + * Description: + * input : hi2c : pointer to a I2C_HandleTypeDef structure that contains + * the configuration information for I2C module + ************************************************************************/ +__weak void HAL_I2C_MspDeInit(I2C_HandleTypeDef *hi2c) +{ + /* + NOTE : This function should be modified by the user. + */ + + /* For Example */ + GPIO_InitTypeDef GPIO_Handle; + + /* I2C1 */ + if (hi2c->Instance == I2C1) + { + /* Disable Clock */ + System_Module_Disable(EN_I2C1); + + /* I2C1 SDA PortB Pin7 */ + /* I2C1 SCL PortB Pin6 */ + HAL_GPIO_DeInit(GPIOB, GPIO_PIN_6 | GPIO_PIN_7); + /* Clear Pending Interrupt */ + NVIC_ClearPendingIRQ(I2C1_IRQn); + + /* Disable External Interrupt */ + NVIC_DisableIRQ(I2C1_IRQn); + } + /* I2C2 */ + else if (hi2c->Instance == I2C2) + { + } +} + +/************************************************************************ + * function : HAL_I2C_Init + * Description: I2c initial with parameters. + * input : hi2c : pointer to a I2C_HandleTypeDef structure that contains + * the configuration information for I2C module + ************************************************************************/ +HAL_StatusTypeDef HAL_I2C_Init(I2C_HandleTypeDef *hi2c) +{ + /* Check I2C Parameter */ + if (!IS_I2C_ALL_INSTANCE(hi2c->Instance)) return HAL_ERROR; + if (!IS_I2C_ALL_MODE(hi2c->Init.I2C_Mode)) return HAL_ERROR; + if (!IS_I2C_CLOCK_SPEED(hi2c->Init.Clock_Speed)) return HAL_ERROR; + if (!IS_I2C_TX_AUTO_EN(hi2c->Init.Tx_Auto_En)) return HAL_ERROR; + if (!IS_I2C_STRETCH_EN(hi2c->Init.No_Stretch_Mode)) return HAL_ERROR; + + /* Disable the selected I2C peripheral */ + CLEAR_BIT(hi2c->Instance->CR, I2C_CR_MEN); + + /* Init the low level hardware : GPIO, CLOCK, NVIC */ + HAL_I2C_MspInit(hi2c); + + switch (hi2c->Init.I2C_Mode) + { + /* Master Mode */ + case I2C_MODE_MASTER: + { + /* Set Master Mode */ + SET_BIT(hi2c->Instance->CR, I2C_CR_MASTER); + + /* Set Clock Speed */ + I2C_Set_Clock_Speed(hi2c, hi2c->Init.Clock_Speed); + + /* Set SDA auto change the direction */ + if (hi2c->Init.Tx_Auto_En == TX_AUTO_EN_ENABLE) + SET_BIT(hi2c->Instance->CR, I2C_CR_TX_AUTO_EN); + else + CLEAR_BIT(hi2c->Instance->CR, I2C_CR_TX_AUTO_EN); + + /* Enable the selected I2C peripheral */ + SET_BIT(hi2c->Instance->CR, I2C_CR_MEN); + }break; + + /* Slave Mode */ + case I2C_MODE_SLAVE: + { + SET_BIT(hi2c->Instance->CR, I2C_CR_TXE_SEL); + + /* Set SDA auto change the direction */ + if (hi2c->Init.Tx_Auto_En == TX_AUTO_EN_ENABLE) + SET_BIT(hi2c->Instance->CR, I2C_CR_TX_AUTO_EN); + else + CLEAR_BIT(hi2c->Instance->CR, I2C_CR_TX_AUTO_EN); + + /* Set Clock Stretch Mode */ + if (hi2c->Init.No_Stretch_Mode == NO_STRETCH_MODE_NOSTRETCH) + SET_BIT(hi2c->Instance->CR, I2C_CR_NOSTRETCH); + else + CLEAR_BIT(hi2c->Instance->CR, I2C_CR_NOSTRETCH); + + /* Set Address 1 */ + hi2c->Instance->SLAVE_ADDR1 = hi2c->Init.Own_Address; + + /* Enable the selected I2C peripheral */ + SET_BIT(hi2c->Instance->CR, I2C_CR_MEN); + }break; + + default: break; + } + + return HAL_OK; +} + +/************************************************************************ + * function : HAL_I2C_DeInit + * Description: I2c De-initial with parameters. + * input : hi2c : pointer to a I2C_HandleTypeDef structure that contains + * the configuration information for I2C module + ************************************************************************/ +HAL_StatusTypeDef HAL_I2C_DeInit(I2C_HandleTypeDef *hi2c) +{ + /* Check I2C Parameter */ + if (!IS_I2C_ALL_INSTANCE(hi2c->Instance)) return HAL_ERROR; + + hi2c->Slave_RxState = SLAVE_RX_STATE_IDLE; + hi2c->Slave_TxState = SLAVE_TX_STATE_IDLE; + + HAL_I2C_MspDeInit(hi2c); + + hi2c->Tx_Size = 0; + hi2c->Rx_Size = 0; + hi2c->Tx_Count = 0; + hi2c->Rx_Count = 0; + + return HAL_OK; +} + +/************************************************************************ + * function : HAL_I2C_Master_Transmit + * Description: Transmits in master mode an amount of data in blocking mode. + * input : hi2c : pointer to a I2C_HandleTypeDef structure that contains + * the configuration information for I2C module + * DevAddress : Target device address + * pData : Pointer to data buffer + * Size : Amount of data to be sent + * Timeout : Timeout value +************************************************************************/ +HAL_StatusTypeDef HAL_I2C_Master_Transmit(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint8_t *pData, uint16_t Size, uint32_t Timeout) +{ + uint32_t i; + + /* Check I2C Parameter */ + if (!IS_I2C_ALL_INSTANCE(hi2c->Instance)) return HAL_ERROR; + + hi2c->Tx_Buffer = pData; + hi2c->Tx_Size = Size; + hi2c->Tx_Count = 0; + + /* Send Write Access Request */ + if (I2C_Master_Request_Write(hi2c, DevAddress, 0) == HAL_OK) + { + for (i = 0; i < hi2c->Tx_Size; i++) + { + /* Wait TXE Flag */ + if(I2C_WaitOnFlagUntilTimeout(hi2c, I2C_SR_TXE, RESET, Timeout) != HAL_OK) return HAL_ERROR; + + /* Send Data */ + hi2c->Instance->DR = hi2c->Tx_Buffer[hi2c->Tx_Count++]; + + /* Wait for transmission End*/ + if(I2C_WaitOnFlagUntilTimeout(hi2c, I2C_SR_MTF, RESET, Timeout) != HAL_OK) return HAL_ERROR; + + /* Clear MTF */ + hi2c->Instance->SR = READ_BIT(hi2c->Instance->SR, I2C_SR_MTF); + + /* Get NACK */ + if (READ_BIT(hi2c->Instance->SR, I2C_SR_RACK)) + { + /* Generate Stop */ + SET_BIT(hi2c->Instance->CR, I2C_CR_STOP); + + /* Wait for the bus to idle */ + if(I2C_WaitOnFlagUntilTimeout(hi2c, I2C_SR_BUS_BUSY, SET, Timeout) != HAL_OK) return HAL_ERROR; + + return HAL_ERROR; + } + } + + /* Generate Stop */ + SET_BIT(hi2c->Instance->CR, I2C_CR_STOP); + + /* Wait for the bus to idle */ + if(I2C_WaitOnFlagUntilTimeout(hi2c, I2C_SR_BUS_BUSY, SET, Timeout) != HAL_OK) return HAL_ERROR; + } + else + { + return HAL_ERROR; + } + + return HAL_OK; +} + +/************************************************************************ + * function : HAL_I2C_Master_Receive + * Description: Transmits in master mode an amount of data in blocking mode. + * input : hi2c : pointer to a I2C_HandleTypeDef structure that contains + * the configuration information for I2C module + * DevAddress : Target device address + * pData : Pointer to data buffer + * Size : Amount of data to be Receive + * Timeout : Timeout value + ************************************************************************/ +HAL_StatusTypeDef HAL_I2C_Master_Receive(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint8_t *pData, uint16_t Size, uint32_t Timeout) +{ + uint32_t i; + + /* Check I2C Parameter */ + if (!IS_I2C_ALL_INSTANCE(hi2c->Instance)) return HAL_ERROR; + + hi2c->Rx_Buffer = pData; + hi2c->Rx_Size = Size; + hi2c->Rx_Count = 0; + + /* Send Read Access Request */ + if (I2C_Master_Request_Read(hi2c, DevAddress, Timeout) == HAL_OK) + { + /* Wait Master Transition receiving state */ + if(I2C_WaitOnFlagUntilTimeout(hi2c, I2C_SR_TX_RX_FLAG, RESET, Timeout) != HAL_OK) return HAL_ERROR; + /* Clear TX_RX_FLAG */ + hi2c->Instance->SR = READ_BIT(hi2c->Instance->SR, I2C_SR_TX_RX_FLAG); + /* Generate ACK */ + CLEAR_BIT(hi2c->Instance->CR, I2C_CR_TACK); + + for (i = 0; i < hi2c->Rx_Size - 1; i++) + { + /* Wait RXNE Flag */ + if(I2C_WaitOnFlagUntilTimeout(hi2c, I2C_SR_RXNE, RESET, Timeout) != HAL_OK) return HAL_ERROR; + /* Read Data */ + hi2c->Rx_Buffer[hi2c->Rx_Count++] = hi2c->Instance->DR; + /* Wait for transmission End*/ + if(I2C_WaitOnFlagUntilTimeout(hi2c, I2C_SR_MTF, RESET, Timeout) != HAL_OK) return HAL_ERROR; + /* Clear MTF */ + hi2c->Instance->SR = READ_BIT(hi2c->Instance->SR, I2C_SR_MTF); + } + + /* Prepare for Generate NACK */ + SET_BIT(hi2c->Instance->CR, I2C_CR_TACK); + /* Prepare for Generate STOP */ + SET_BIT(hi2c->Instance->CR, I2C_CR_STOP); + + /* Wait RXNE Flag */ + if(I2C_WaitOnFlagUntilTimeout(hi2c, I2C_SR_RXNE, RESET, Timeout) != HAL_OK) return HAL_ERROR; + /* Read Data */ + hi2c->Rx_Buffer[hi2c->Rx_Count++] = hi2c->Instance->DR; + /* Wait for transmission End*/ + if(I2C_WaitOnFlagUntilTimeout(hi2c, I2C_SR_MTF, RESET, Timeout) != HAL_OK) return HAL_ERROR; + /* Clear MTF */ + hi2c->Instance->SR = READ_BIT(hi2c->Instance->SR, I2C_SR_MTF); + + /* Wait for the bus to idle */ + if(I2C_WaitOnFlagUntilTimeout(hi2c, I2C_SR_BUS_BUSY, SET, Timeout) != HAL_OK) return HAL_ERROR; + + /* Generate ACK */ + CLEAR_BIT(hi2c->Instance->CR, I2C_CR_TACK); + } + else + { + return HAL_ERROR; + } + + return HAL_OK; +} + +/************************************************************************ + * function : HAL_I2C_Slave_Transmit + * Description: Transmits in Slave mode an amount of data in blocking mode. + * input : hi2c : pointer to a I2C_HandleTypeDef structure that contains + * the configuration information for I2C module + * pData : Pointer to data buffer + * Size : Amount of data to be sent + * Timeout : Timeout value + ************************************************************************/ +HAL_StatusTypeDef HAL_I2C_Slave_Transmit(I2C_HandleTypeDef *hi2c, uint8_t *pData, uint32_t Size, uint32_t Timeout) +{ + uint32_t i = 0; + + /* Check I2C Parameter */ + if (!IS_I2C_ALL_INSTANCE(hi2c->Instance)) return HAL_ERROR; + + hi2c->Tx_Buffer = pData; + hi2c->Tx_Size = Size; + hi2c->Tx_Count = 0; + + /* Clear RX_ADDR1 Flag */ + hi2c->Instance->SR = READ_BIT(hi2c->Instance->SR, I2C_SR_RX_ADDR1); + /* Match the Address 1 */ + if(I2C_WaitOnFlagUntilTimeout(hi2c, I2C_SR_RX_ADDR1, RESET, Timeout) != HAL_OK) return HAL_ERROR; + /* Clear RX_ADDR1 Flag */ + hi2c->Instance->SR = READ_BIT(hi2c->Instance->SR, I2C_SR_RX_ADDR1); + + /* Slave Transmit */ + if (READ_BIT(hi2c->Instance->SR, I2C_SR_SRW)) + { + /* BUS BUSY */ + while(READ_BIT(hi2c->Instance->SR, I2C_SR_BUS_BUSY)) + { + if (READ_BIT(hi2c->Instance->SR, I2C_SR_MTF)) + { + /* Clear MTF */ + hi2c->Instance->SR = READ_BIT(hi2c->Instance->SR, I2C_SR_MTF); + + hi2c->Tx_Count++; + } + + if (READ_BIT(hi2c->Instance->SR, I2C_SR_TXE)) + { + if (i < hi2c->Tx_Size || hi2c->Tx_Size == 0) + { + hi2c->Instance->DR = hi2c->Tx_Buffer[i++]; + } + } + } + hi2c->Instance->SR = READ_REG(hi2c->Instance->SR); + } + else + { + return HAL_ERROR; + } + + hi2c->Tx_Count--; + + return HAL_OK; +} + +/************************************************************************ + * function : HAL_I2C_Slave_Transmit_IT + * Description: Transmit in slave mode an amount of data in non-blocking mode with Interrupt + * input : hi2c : pointer to a I2C_HandleTypeDef structure that contains + * the configuration information for I2C module + * pData : Pointer to data buffer + * Size : Amount of data to be sent + * return : HAL_StatusTypeDef + ************************************************************************/ +HAL_StatusTypeDef HAL_I2C_Slave_Transmit_IT(I2C_HandleTypeDef *hi2c, uint8_t *pData, uint32_t Size) +{ + /* Check I2C Parameter */ + if (!IS_I2C_ALL_INSTANCE(hi2c->Instance)) return HAL_ERROR; + + /* Rx machine is running */ + if (hi2c->Slave_TxState != SLAVE_TX_STATE_IDLE) + return HAL_ERROR; + + /* Set Slave machine is sending */ + hi2c->Slave_TxState = SLAVE_TX_STATE_SENDING; + + hi2c->Tx_Buffer = pData; + hi2c->Tx_Size = Size; + hi2c->Tx_Count = 0; + + CLEAR_BIT(hi2c->Instance->CR, I2C_CR_TXE_SEL); + + hi2c->Instance->DR = hi2c->Tx_Buffer[0]; + + hi2c->Tx_Count++; + + /* Clear RX ADDR1 Flag */ + SET_BIT(hi2c->Instance->SR, I2C_SR_RX_ADDR1); + /* RX ADDR1 Interrupt Enable */ + SET_BIT(hi2c->Instance->CR, I2C_CR_RX_ADDR1_INT_EN); + + return HAL_OK; +} + +/************************************************************************ + * function : HAL_I2C_Slave_Receive + * Description: Receive in Slave mode an amount of data in blocking mode. + * input : hi2c : pointer to a I2C_HandleTypeDef structure that contains + * the configuration information for I2C module + * pData : Pointer to data buffer + * Size : Amount of data to be sent + * Timeout : Timeout value + * return : HAL_StatusTypeDef + ************************************************************************/ +HAL_StatusTypeDef HAL_I2C_Slave_Receive(I2C_HandleTypeDef *hi2c, uint8_t *pData, uint32_t Size, uint32_t Timeout) +{ + uint32_t i = 0; + HAL_StatusTypeDef Status; + + /* Check I2C Parameter */ + if (!IS_I2C_ALL_INSTANCE(hi2c->Instance)) return HAL_ERROR;; + + hi2c->Rx_Buffer = pData; + hi2c->Rx_Size = Size; + hi2c->Rx_Count = 0; + + /* Match the Address 1 */ + if(I2C_WaitOnFlagUntilTimeout(hi2c, I2C_SR_RX_ADDR1, RESET, Timeout) != HAL_OK) return HAL_ERROR; + /* Clear RX_ADDR1 Flag */ + hi2c->Instance->SR = READ_BIT(hi2c->Instance->SR, I2C_SR_RX_ADDR1); + + /* Slave Receive */ + if (!READ_BIT(hi2c->Instance->SR, I2C_SR_SRW)) + { + /* Wait for transmission End*/ + if(I2C_WaitOnFlagUntilTimeout(hi2c, I2C_SR_MTF, RESET, Timeout) != HAL_OK) return HAL_ERROR; + /* Clear MTF */ + hi2c->Instance->SR = READ_BIT(hi2c->Instance->SR, I2C_SR_MTF); + + /* BUS BUSY */ + while(READ_BIT(hi2c->Instance->SR, I2C_SR_BUS_BUSY)) + { + /* Receive Data */ + if (READ_BIT(hi2c->Instance->SR, I2C_SR_RXNE)) + { + hi2c->Rx_Buffer[hi2c->Rx_Count++] = hi2c->Instance->DR; + + /* Wait for transmission End*/ + if(I2C_WaitOnFlagUntilTimeout(hi2c, I2C_SR_MTF, RESET, Timeout) != HAL_OK) return HAL_ERROR; + /* Clear MTF */ + hi2c->Instance->SR = READ_BIT(hi2c->Instance->SR, I2C_SR_MTF); + + if (hi2c->Rx_Size != 0) + { + if (hi2c->Rx_Count >= hi2c->Rx_Size) + { + break; + } + } + } + } + + /* Generate ACK */ + CLEAR_BIT(hi2c->Instance->CR, I2C_CR_TACK); + + hi2c->Instance->SR = READ_REG(hi2c->Instance->SR); + } + /* Slave Transmit */ + else + { + return HAL_ERROR; + } + + return HAL_OK; +} + +/************************************************************************ + * function : HAL_I2C_Slave_Receive_IT + * Description: Receive in slave mode an amount of data in non-blocking mode with Interrupt + * input : hi2c : pointer to a I2C_HandleTypeDef structure that contains + * the configuration information for I2C module + * pData : Pointer to data buffer + * Size : Amount of data to be sent + ************************************************************************/ +HAL_StatusTypeDef HAL_I2C_Slave_Receive_IT(I2C_HandleTypeDef *hi2c, uint8_t *pData, uint32_t Size) +{ + /* Check I2C Parameter */ + if (!IS_I2C_ALL_INSTANCE(hi2c->Instance)) return HAL_ERROR; + + /* Rx machine is running */ + if (hi2c->Slave_RxState != SLAVE_RX_STATE_IDLE) + return HAL_ERROR; + + /* Set Slave machine is receiving */ + hi2c->Slave_RxState = SLAVE_RX_STATE_RECEIVING; + + hi2c->Rx_Buffer = pData; + hi2c->Rx_Size = Size; + hi2c->Rx_Count = 0; + + /* Clear RX ADDR1 Flag */ + SET_BIT(hi2c->Instance->SR, I2C_SR_RX_ADDR1); + /* RX ADDR1 Interrupt Enable */ + SET_BIT(hi2c->Instance->CR, I2C_CR_RX_ADDR1_INT_EN); + + return HAL_OK; +} + +/************************************************************************ + * function : HAL_I2C_Slave_Receive_DMA + * Description: Receive in slave mode an amount of data in non-blocking mode with DMA + * input : hi2c : pointer to a I2C_HandleTypeDef structure that contains + * the configuration information for I2C module + * pData : Pointer to data buffer + * Size : Amount of data to be sent + ************************************************************************/ +HAL_StatusTypeDef HAL_I2C_Slave_Receive_DMA(I2C_HandleTypeDef *hi2c, uint8_t *pData, uint32_t Size) +{ + /* Check I2C Parameter */ + if (!IS_I2C_ALL_INSTANCE(hi2c->Instance)) return HAL_ERROR; + + hi2c->Rx_Buffer = pData; + hi2c->Rx_Size = Size; + hi2c->Rx_Count = Size; + + /* DMA Enable */ + SET_BIT(hi2c->Instance->CR, I2C_CR_DMA_EN); + + /* Clear STOPF Interrupt Flag */ + hi2c->Instance->SR = READ_BIT(hi2c->Instance->SR, I2C_SR_STOPF); + /* STOPF Interrupt Enable */ + SET_BIT(hi2c->Instance->CR, I2C_CR_STOPF_INTEN); + + HAL_DMA_Start(hi2c->HDMA_Rx, (uint32_t)&hi2c->Instance->DR, (uint32_t)hi2c->Rx_Buffer, hi2c->Rx_Size); + + return HAL_OK; +} + +/************************************************************************ + * function : HAL_I2C_Slave_Transmit_DMA + * Description: Transmit in slave mode an amount of data in non-blocking mode with DMA + * input : hi2c : pointer to a I2C_HandleTypeDef structure that contains + * the configuration information for I2C module + * pData : Pointer to data buffer + * Size : Amount of data to be sent + ************************************************************************/ +HAL_StatusTypeDef HAL_I2C_Slave_Transmit_DMA(I2C_HandleTypeDef *hi2c, uint8_t *pData, uint32_t Size) +{ + /* Check I2C Parameter */ + if (!IS_I2C_ALL_INSTANCE(hi2c->Instance)) return HAL_ERROR; + + hi2c->Tx_Buffer = pData; + hi2c->Tx_Size = Size; + hi2c->Tx_Count = Size; + + /* Must Set TXE_SEL In DMA Mode !!! */ + SET_BIT(hi2c->Instance->CR, I2C_CR_TXE_SEL); + /* DMA Enable */ + SET_BIT(hi2c->Instance->CR, I2C_CR_DMA_EN); + + HAL_DMA_Start_IT(hi2c->HDMA_Tx, (uint32_t)hi2c->Tx_Buffer, (uint32_t)&hi2c->Instance->DR, hi2c->Tx_Size); + + return HAL_OK; +} + +/************************************************************************ + * function : HAL_I2C_Mem_Write + * Description: Write an amount of data in blocking mode to a specific memory address + * input : hi2c : pointer to a I2C_HandleTypeDef structure that contains + * the configuration information for I2C module + * DevAddress : Target device address + * MemAddress : MemAddress Internal memory address + * MemAddSize : MemAddSize Size of internal memory address + * pData : Pointer to data buffer + * Size : Amount of data to be sent + * Timeout : Timeout value + ************************************************************************/ +HAL_StatusTypeDef HAL_I2C_Mem_Write(I2C_HandleTypeDef *hi2c, uint8_t DevAddress, uint16_t MemAddress, uint16_t MemAddSize, uint8_t *pData, uint16_t Size, uint32_t Timeout) +{ + uint32_t i; + + /* Check I2C Parameter */ + if (!IS_I2C_ALL_INSTANCE(hi2c->Instance)) return HAL_ERROR; + + hi2c->Tx_Buffer = pData; + hi2c->Tx_Size = Size; + hi2c->Tx_Count = 0; + + /* Bus Busy */ + if (READ_BIT(hi2c->Instance->SR, I2C_SR_BUS_BUSY)) + return HAL_ERROR; + + /* Send Write Access Request */ + if (I2C_Master_Request_Write(hi2c, DevAddress,0) == HAL_OK) + { + /* If Memory address size is 8Bit */ + if (MemAddSize == I2C_MEMADD_SIZE_8BIT) + { + /* Send Memory Address */ + hi2c->Instance->DR = I2C_MEM_ADD_LSB(MemAddress); + } + /* If Memory address size is 16Bit */ + else + { + /* Send Memory Address MSB*/ + hi2c->Instance->DR = I2C_MEM_ADD_MSB(MemAddress); + /* Wait for transmission End*/ + if(I2C_WaitOnFlagUntilTimeout(hi2c, I2C_SR_MTF, RESET, Timeout) != HAL_OK) return HAL_ERROR; + /* Clear MTF */ + hi2c->Instance->SR = READ_BIT(hi2c->Instance->SR, I2C_SR_MTF); + /* Send Memory Address LSB*/ + hi2c->Instance->DR = I2C_MEM_ADD_LSB(MemAddress); + } + + /* Wait for transmission End*/ + if(I2C_WaitOnFlagUntilTimeout(hi2c, I2C_SR_MTF, RESET, Timeout) != HAL_OK) return HAL_ERROR; + /* Clear MTF */ + hi2c->Instance->SR = READ_BIT(hi2c->Instance->SR, I2C_SR_MTF); + + /* Get NACK */ + if (READ_BIT(hi2c->Instance->SR, I2C_SR_RACK)) + { + /* Generate Stop */ + SET_BIT(hi2c->Instance->CR, I2C_CR_STOP); + + /* Wait for the bus to idle */ + if(I2C_WaitOnFlagUntilTimeout(hi2c, I2C_SR_BUS_BUSY, SET, Timeout) != HAL_OK) return HAL_ERROR; + + return HAL_ERROR; + } + /* Get ACK */ + else + { + for (i = 0; i < hi2c->Tx_Size; i++) + { + /* Wait TXE Flag */ + if(I2C_WaitOnFlagUntilTimeout(hi2c, I2C_SR_TXE, RESET, Timeout)!= HAL_OK) return HAL_ERROR; + + /* Send Data */ + hi2c->Instance->DR = hi2c->Tx_Buffer[hi2c->Tx_Count++]; + + /* Wait for transmission End*/ + if(I2C_WaitOnFlagUntilTimeout(hi2c, I2C_SR_MTF, RESET, Timeout) != HAL_OK) return HAL_ERROR; + /* Clear MTF */ + hi2c->Instance->SR = READ_BIT(hi2c->Instance->SR, I2C_SR_MTF); + + /* Get NACK */ + if (READ_BIT(hi2c->Instance->SR, I2C_SR_RACK)) + { + /* Generate Stop */ + SET_BIT(hi2c->Instance->CR, I2C_CR_STOP); + + /* Wait for the bus to idle */ + if(I2C_WaitOnFlagUntilTimeout(hi2c, I2C_SR_BUS_BUSY, SET, Timeout) != HAL_OK) return HAL_ERROR; + return HAL_ERROR; + } + } + + /* Generate Stop */ + SET_BIT(hi2c->Instance->CR, I2C_CR_STOP); + + /* Wait for the bus to idle */ + if(I2C_WaitOnFlagUntilTimeout(hi2c, I2C_SR_BUS_BUSY, SET, Timeout) != HAL_OK) return HAL_ERROR; + /* Check Device Ready */ + while(I2C_Check_Device_Ready(hi2c, DevAddress, Timeout) != HAL_OK); + } + } + else + { + return HAL_ERROR; + } + + return HAL_OK; +} + +/************************************************************************ + * function : HAL_I2C_Mem_Read + * Description: Read an amount of data in blocking mode to a specific memory address + * input : hi2c : pointer to a I2C_HandleTypeDef structure that contains + * the configuration information for I2C module + * DevAddress : Target device address + * MemAddress : MemAddress Internal memory address + * MemAddSize : MemAddSize Size of internal memory address + * pData : Pointer to data buffer + * Size : Amount of data to be sent + * Timeout : Timeout value + ************************************************************************/ +HAL_StatusTypeDef HAL_I2C_Mem_Read(I2C_HandleTypeDef *hi2c, uint8_t DevAddress, uint16_t MemAddress, uint16_t MemAddSize, uint8_t *pData, uint16_t Size, uint32_t Timeout) +{ + uint32_t i; + + /* Check I2C Parameter */ + if (!IS_I2C_ALL_INSTANCE(hi2c->Instance)) return HAL_ERROR; + + hi2c->Rx_Buffer = pData; + hi2c->Rx_Size = Size; + hi2c->Rx_Count = 0; + + /* Bus Busy */ + if (READ_BIT(hi2c->Instance->SR, I2C_SR_BUS_BUSY)) + return HAL_ERROR; + + /* Send Write Access Request */ + if (I2C_Master_Request_Write(hi2c, DevAddress,0) == HAL_OK) + { + /* If Memory address size is 8Bit */ + if (MemAddSize == I2C_MEMADD_SIZE_8BIT) + { + /* Send Memory Address */ + hi2c->Instance->DR = I2C_MEM_ADD_LSB(MemAddress); + } + /* If Memory address size is 16Bit */ + else + { + /* Send Memory Address MSB*/ + hi2c->Instance->DR = I2C_MEM_ADD_MSB(MemAddress); + /* Wait for transmission End*/ + if(I2C_WaitOnFlagUntilTimeout(hi2c, I2C_SR_MTF, RESET, Timeout) != HAL_OK) return HAL_ERROR; + /* Clear MTF */ + hi2c->Instance->SR = READ_BIT(hi2c->Instance->SR, I2C_SR_MTF); + /* Send Memory Address LSB*/ + hi2c->Instance->DR = I2C_MEM_ADD_LSB(MemAddress); + } + + /* Wait for transmission End*/ + if(I2C_WaitOnFlagUntilTimeout(hi2c, I2C_SR_MTF, RESET, Timeout) != HAL_OK) return HAL_ERROR; + /* Clear MTF */ + hi2c->Instance->SR = READ_BIT(hi2c->Instance->SR, I2C_SR_MTF); + + /* Get NACK */ + if (READ_BIT(hi2c->Instance->SR, I2C_SR_RACK)) + { + /* Generate Stop */ + SET_BIT(hi2c->Instance->CR, I2C_CR_STOP); + + /* Wait for the bus to idle */ + if(I2C_WaitOnFlagUntilTimeout(hi2c, I2C_SR_BUS_BUSY, SET, Timeout) != HAL_OK) return HAL_ERROR; + + return HAL_ERROR; + } + /* Get ACK */ + else + { + /* Send Write Read Request */ + if (I2C_Master_Request_Read(hi2c, DevAddress, Timeout) == HAL_OK) + { + /* Wait Master Transition receiving state */ + if(I2C_WaitOnFlagUntilTimeout(hi2c, I2C_SR_TX_RX_FLAG, RESET, Timeout) != HAL_OK) return HAL_ERROR; + /* Clear TX_RX_FLAG */ + hi2c->Instance->SR = READ_BIT(hi2c->Instance->SR, I2C_SR_TX_RX_FLAG); + + /* Generate ACK */ + CLEAR_BIT(hi2c->Instance->CR, I2C_CR_TACK); + + for (i = 0; i < hi2c->Rx_Size - 1; i++) + { + /* Wait RXNE Flag */ + if(I2C_WaitOnFlagUntilTimeout(hi2c, I2C_SR_RXNE, RESET, Timeout) != HAL_OK) return HAL_ERROR; + /* Read Data */ + hi2c->Rx_Buffer[hi2c->Rx_Count++] = hi2c->Instance->DR; + /* Wait for transmission End*/ + if(I2C_WaitOnFlagUntilTimeout(hi2c, I2C_SR_MTF, RESET, Timeout) != HAL_OK) return HAL_ERROR; + /* Clear MTF */ + hi2c->Instance->SR = READ_BIT(hi2c->Instance->SR, I2C_SR_MTF); + } + + /* Prepare for Generate NACK */ + SET_BIT(hi2c->Instance->CR, I2C_CR_TACK); + /* Prepare for Generate STOP */ + SET_BIT(hi2c->Instance->CR, I2C_CR_STOP); + + /* Wait RXNE Flag */ + if(I2C_WaitOnFlagUntilTimeout(hi2c, I2C_SR_RXNE, RESET, Timeout) != HAL_OK) return HAL_ERROR; + /* Read Data */ + hi2c->Rx_Buffer[hi2c->Rx_Count++] = hi2c->Instance->DR; + /* Wait for transmission End*/ + if(I2C_WaitOnFlagUntilTimeout(hi2c, I2C_SR_MTF, RESET, Timeout) != HAL_OK) return HAL_ERROR; + /* Clear MTF */ + hi2c->Instance->SR = READ_BIT(hi2c->Instance->SR, I2C_SR_MTF); + + /* Wait for the bus to idle */ + if(I2C_WaitOnFlagUntilTimeout(hi2c, I2C_SR_BUS_BUSY, SET, Timeout) != HAL_OK) return HAL_ERROR; + /* Generate ACK */ + CLEAR_BIT(hi2c->Instance->CR, I2C_CR_TACK); + } + else + { + /* Get NACK */ + return HAL_ERROR; + } + } + } + else + { + return HAL_ERROR; + } + + return HAL_OK; +} + +/************************************************************************ + * function : HAL_I2C_GetSlaveRxState + * Description: Get Slave Rx State + * input : hi2c : pointer to a I2C_HandleTypeDef structure that contains + * the configuration information for I2C module + * return : Slave State + ************************************************************************/ +uint8_t HAL_I2C_GetSlaveRxState(I2C_HandleTypeDef *hi2c) +{ + return hi2c->Slave_RxState; +} + +/************************************************************************ + * function : HAL_I2C_GetSlaveTxState + * Description: Get Slave Tx State + * input : hi2c : pointer to a I2C_HandleTypeDef structure that contains + * the configuration information for I2C module + * return : Slave State + ************************************************************************/ +uint8_t HAL_I2C_GetSlaveTxState(I2C_HandleTypeDef *hi2c) +{ + return hi2c->Slave_TxState; +} + +/************************************************************************ + * function : I2C_Set_Clock_Speed + * Description: Set I2C Clock Speed + * input : hi2c : pointer to a I2C_HandleTypeDef structure that contains + * the configuration information for I2C module + * ClockSpeed: I2C Clock Speed + ************************************************************************/ +static HAL_StatusTypeDef I2C_Set_Clock_Speed(I2C_HandleTypeDef *hi2c, uint32_t ClockSpeed) +{ + uint32_t APB_Clock; + + APB_Clock = System_Get_APBClock(); + + hi2c->Instance->CLK_DIV = APB_Clock / (4 * ClockSpeed) - 1; + + return HAL_OK; +} + +/** + * @brief This function handles I2C Communication Timeout. + * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains + * the configuration information for I2C module + * @param Flag specifies the I2C flag to check. + * @param Status The new Flag status (SET or RESET). + * @param Timeout Timeout duration + * @param Tickstart Tick start value + * @retval HAL status + */ +static HAL_StatusTypeDef I2C_WaitOnFlagUntilTimeout(I2C_HandleTypeDef *hi2c, uint32_t Flag, FlagStatus Status, uint32_t Timeout) +{ + __IO uint32_t lu32_Timeout; + /* have no timeout */ + if (Timeout == 0) + { + while (__HAL_I2C_GET_FLAG(hi2c, Flag)==Status); + } + else + { + lu32_Timeout = Timeout * 0xFF; + + while (__HAL_I2C_GET_FLAG(hi2c, Flag)==Status) + { + if (lu32_Timeout-- == 0) + { + return HAL_ERROR; + } + } + } + return HAL_OK; +} +/************************************************************************ + * function : I2C_Master_Request_Write + * Description: I2C Write Access Request + * input : hi2c : pointer to a I2C_HandleTypeDef structure + * DevAddress: Device address + * Timeout: Timeout value + ************************************************************************/ +static HAL_StatusTypeDef I2C_Master_Request_Write(I2C_HandleTypeDef *hi2c, uint8_t DevAddress, uint32_t Timeout) +{ + /* Generate Start */ + SET_BIT(hi2c->Instance->CR, I2C_CR_START); + + /* Clear MTF, To Prevent Errors */ + hi2c->Instance->SR = READ_BIT(hi2c->Instance->SR, I2C_SR_MTF); + + /* Send Device Address */ + hi2c->Instance->DR = DevAddress & 0xFE; + + /* Wait for transmission End*/ + if(I2C_WaitOnFlagUntilTimeout(hi2c, I2C_SR_MTF, RESET, Timeout) != HAL_OK) return HAL_ERROR; + /* Clear MTF */ + hi2c->Instance->SR = READ_BIT(hi2c->Instance->SR, I2C_SR_MTF); + + /* Get NACK */ + if (READ_BIT(hi2c->Instance->SR, I2C_SR_RACK)) + { + /* Generate Stop */ + SET_BIT(hi2c->Instance->CR, I2C_CR_STOP); + + /* Wait for the bus to idle */ + if(I2C_WaitOnFlagUntilTimeout(hi2c, I2C_SR_BUS_BUSY, SET, Timeout) != HAL_OK) return HAL_ERROR; + + return HAL_ERROR; + } + /* Get ACK */ + else + { + return HAL_OK; + } +} + +/************************************************************************ + * function : I2C_Master_Request_Read + * Description: I2C Read Access Request + * input : hi2c : pointer to a I2C_HandleTypeDef structure + * DevAddress: Device address + * Timeout: Timeout value + ************************************************************************/ +static HAL_StatusTypeDef I2C_Master_Request_Read(I2C_HandleTypeDef *hi2c, uint8_t DevAddress, uint32_t Timeout) +{ + /* Generate Start */ + SET_BIT(hi2c->Instance->CR, I2C_CR_START); + + /* Clear MTF, To Prevent Errors */ + hi2c->Instance->SR = READ_BIT(hi2c->Instance->SR, I2C_SR_MTF); + + /* Send Device Address */ + hi2c->Instance->DR = DevAddress | 0x01; + + /* Wait for transmission End */ + if(I2C_WaitOnFlagUntilTimeout(hi2c, I2C_SR_MTF, RESET, Timeout) != HAL_OK) return HAL_ERROR; + /* Clear MTF */ + hi2c->Instance->SR = READ_BIT(hi2c->Instance->SR, I2C_SR_MTF); + + /* Get NACK */ + if (READ_BIT(hi2c->Instance->SR, I2C_SR_RACK)) + { + /* Generate Stop */ + SET_BIT(hi2c->Instance->CR, I2C_CR_STOP); + + /* Wait for the bus to idle */ + if(I2C_WaitOnFlagUntilTimeout(hi2c, I2C_SR_BUS_BUSY, SET, Timeout) != HAL_OK) return HAL_ERROR; + + return HAL_ERROR; + } + /* Get ACK */ + else + { + return HAL_OK; + } +} + +/************************************************************************ + * function : I2C_Check_Device_Ready + * Description: Check Device Ready + * input : hi2c : pointer to a I2C_HandleTypeDef structure + * DevAddress: Device address + * Timeout: Timeout value + ************************************************************************/ +static HAL_StatusTypeDef I2C_Check_Device_Ready(I2C_HandleTypeDef *hi2c, uint8_t DevAddress, uint32_t Timeout) +{ + /* Bus Busy */ + if (READ_BIT(hi2c->Instance->SR, I2C_SR_BUS_BUSY)) + return HAL_ERROR; + + /* Generate Start */ + SET_BIT(hi2c->Instance->CR, I2C_CR_START); + + /* Send Device Address */ + hi2c->Instance->DR = DevAddress; + + /* Wait for transmission End */ + if(I2C_WaitOnFlagUntilTimeout(hi2c, I2C_SR_MTF, RESET, Timeout) != HAL_OK) return HAL_ERROR; + /* Clear MTF */ + hi2c->Instance->SR = READ_BIT(hi2c->Instance->SR, I2C_SR_MTF); + + /* Get NACK */ + if (READ_BIT(hi2c->Instance->SR, I2C_SR_RACK)) + { + /* Generate Stop */ + SET_BIT(hi2c->Instance->CR, I2C_CR_STOP); + + /* Wait for the bus to idle */ + if(I2C_WaitOnFlagUntilTimeout(hi2c, I2C_SR_BUS_BUSY, SET, Timeout) != HAL_OK) return HAL_ERROR; + + return HAL_ERROR; + } + /* Get ACK */ + else + { + /* Generate Stop */ + SET_BIT(hi2c->Instance->CR, I2C_CR_STOP); + + /* Wait for the bus to idle */ + if(I2C_WaitOnFlagUntilTimeout(hi2c, I2C_SR_BUS_BUSY, SET, Timeout) != HAL_OK) return HAL_ERROR; + + return HAL_OK; + } +} diff --git a/bsp/acm32f4xx-nucleo/libraries/HAL_Driver/Src/HAL_I2S.c b/bsp/acm32f4xx-nucleo/libraries/HAL_Driver/Src/HAL_I2S.c new file mode 100644 index 0000000000..6c6b677cae --- /dev/null +++ b/bsp/acm32f4xx-nucleo/libraries/HAL_Driver/Src/HAL_I2S.c @@ -0,0 +1,491 @@ +/* + ****************************************************************************** + * @file HAL_I2S.c + * @version V1.0.0 + * @date 2020 + * @brief I2S HAL module driver. + * This file provides firmware functions to manage the following + * functionalities of the Integrated Interchip Sound (I2S) peripheral: + * + Initialization functions + * + IO operation functions + * + Peripheral State + ****************************************************************************** +*/ +#include "ACM32Fxx_HAL.h" + +/********************************************************************************* +* Function : HAL_I2S_IRQHandler +* Description : This function handles I2S interrupt request. +* Input : +* Outpu : +* Author : Chris_Kyle Data : 2020 +**********************************************************************************/ +void HAL_I2S_IRQHandler(I2S_HandleTypeDef *hi2s) +{ + /* Tx Buffer empty */ + if (hi2s->Instance->STATUS & I2S_STATUS_TXBE) + { + if (hi2s->u32_Tx_Count < hi2s->u32_Tx_Size) + { + hi2s->Instance->DAT = hi2s->u32_Tx_Buffer[hi2s->u32_Tx_Count++]; + } + else + { + hi2s->Instance->IE &= ~I2S_DIE_TBEIE; + + hi2s->I2S_Status = HAL_I2S_STATE_READY; + } + } + + /* Rx Buffer not empty */ + if (hi2s->Instance->STATUS & I2S_STATUS_RXBNE) + { + if (hi2s->u32_Rx_Count < hi2s->u32_Rx_Size) + { + hi2s->u32_Tx_Buffer[hi2s->u32_Rx_Count++] = hi2s->Instance->DAT; + } + else + { + /* Disable I2S */ + hi2s->Instance->CTL &= ~I2S_CTL_I2SEN; + + hi2s->Instance->IE &= ~I2S_DIE_RBNEIE; + + hi2s->I2S_Status = HAL_I2S_STATE_READY; + } + } +} + +/********************************************************************************* +* Function : HAL_I2S_MspInit +* Description : +* Input : +* Outpu : +* Author : Chris_Kyle Data : 2020 +**********************************************************************************/ +__weak void HAL_I2S_MspInit(I2S_HandleTypeDef *hi2s) +{ + /* + NOTE : This function should be modified by the user. + */ + + /* For Example */ + GPIO_InitTypeDef GPIO_Handle; + + if (hi2s->Instance == I2S1) + { + /* Enable Clock */ + System_Module_Enable(EN_I2S1); + System_Module_Enable(EN_GPIOAB); + + /* I2S1 WS PortA Pin4 */ + /* I2S1 CLK PortA Pin5 */ + /* I2S1 MCK PortA Pin6 */ + /* I2S1 SD PortA Pin7 */ + GPIO_Handle.Pin = GPIO_PIN_4 | GPIO_PIN_5 | GPIO_PIN_6 | GPIO_PIN_7; + GPIO_Handle.Mode = GPIO_MODE_AF_PP; + GPIO_Handle.Pull = GPIO_PULLUP; + GPIO_Handle.Alternate = GPIO_FUNCTION_8; + HAL_GPIO_Init(GPIOA, &GPIO_Handle); + + /* Clear Pending Interrupt */ + NVIC_ClearPendingIRQ(I2S_IRQn); + + /* Enable External Interrupt */ + NVIC_EnableIRQ(I2S_IRQn); + } +} + +/********************************************************************************* +* Function : HAL_I2S_MspDeInit +* Description : +* Input : +* Outpu : +* Author : Chris_Kyle Data : 2020 +**********************************************************************************/ +__weak void HAL_I2S_MspDeInit(I2S_HandleTypeDef *hi2s) +{ + /* + NOTE : This function should be modified by the user. + */ + + /* For Example */ + if (hi2s->Instance == I2S1) + { + /* I2S1 WS PortA Pin4 */ + /* I2S1 CLK PortA Pin5 */ + /* I2S1 MCK PortA Pin6 */ + /* I2S1 SD PortA Pin7 */ + HAL_GPIO_DeInit(GPIOA, GPIO_PIN_4 | GPIO_PIN_5 | GPIO_PIN_6 | GPIO_PIN_7); + + /* Clear Pending Interrupt */ + NVIC_ClearPendingIRQ(I2S_IRQn); + + /* Disable External Interrupt */ + NVIC_DisableIRQ(I2S_IRQn); + } +} + +/********************************************************************************* +* Function : HAL_I2S_Init +* Description : Initializes the I2S according to the specified parameters +* in the I2S_InitTypeDef and create the associated handle. +* Input : hi2s: pointer to a I2S_HandleTypeDef structure that contains +* the configuration information for I2S module +* Outpu : +* Author : Chris_Kyle Data : 2020 +**********************************************************************************/ +HAL_StatusTypeDef HAL_I2S_Init(I2S_HandleTypeDef *hi2s) +{ +#if (USE_FULL_ASSERT == 1) + /* Check I2S Parameter */ + if (!IS_I2S_MODE(hi2s->Init.u32_Mode)) return HAL_ERROR; + if (!IS_I2S_STANDARD(hi2s->Init.u32_Standard)) return HAL_ERROR; + if (!IS_I2S_DATAFORMAT(hi2s->Init.u32_DataFormat)) return HAL_ERROR; + if (!IS_I2S_MCLK_OUTPUT(hi2s->Init.u32_MCLKOutput)) return HAL_ERROR; + if (!IS_I2S_MCLK_CPOL(hi2s->Init.u32_CPOL)) return HAL_ERROR; + if (!IS_I2S_OF(hi2s->Init.u32_FreqOF)) return HAL_ERROR; + if (!IS_I2S_DIV(hi2s->Init.u32_FreqDIV)) return HAL_ERROR; +#endif + + /* Init the low level hardware : GPIO, CLOCK, CORTEX...etc */ + HAL_I2S_MspInit(hi2s); + + /* Clear Config */ + hi2s->Instance->CTL = 0x00000000; + hi2s->Instance->PSC = 0x00000000; + + /* ModeStandardCPOLDataformat */ + hi2s->Instance->CTL = hi2s->Init.u32_Mode | hi2s->Init.u32_Standard | hi2s->Init.u32_CPOL | hi2s->Init.u32_DataFormat; + /* Frequency */ + hi2s->Instance->PSC = hi2s->Init.u32_MCLKOutput | hi2s->Init.u32_FreqOF | hi2s->Init.u32_FreqDIV; + + /* I2S Enable */ + if (hi2s->Init.u32_Mode != I2S_MODE_MASTER_RX) + { + hi2s->Instance->CTL |= I2S_CTL_I2SEN; + } + + /* I2S Status ready */ + hi2s->I2S_Status = HAL_I2S_STATE_READY; + + return HAL_OK; +} + +/********************************************************************************* +* Function : HAL_I2S_DeInit +* Description : DeInitializes the I2S peripheral +* Input : hi2s: pointer to a I2S_HandleTypeDef structure that contains +* the configuration information for I2S module +* Outpu : +* Author : Chris_Kyle Data : 2020 +**********************************************************************************/ +HAL_StatusTypeDef HAL_I2S_DeInit(I2S_HandleTypeDef *hi2s) +{ + /* Check the I2S handle allocation */ + if (hi2s == NULL) + { + return HAL_ERROR; + } + + /* DeInit the low level hardware: GPIO, CLOCK, NVIC... */ + HAL_I2S_MspDeInit(hi2s); + + System_Module_Reset(RST_I2S1); + + return HAL_OK; +} + +/********************************************************************************* +* Function : HAL_I2S_Transmit +* Description : Transmit an amount of data in blocking mode +* Input : hi2s: pointer to a I2S_HandleTypeDef structure that contains +* the configuration information for I2S module +* Input : fp32_Data: 32-bit pointer to data buffer. +* Input : Size: number of data sample to be sent +* Input : fu32_Timeout: Timeout duration +* Outpu : +* Author : Chris_Kyle Data : 2020 +**********************************************************************************/ +HAL_StatusTypeDef HAL_I2S_Transmit(I2S_HandleTypeDef *hi2s, uint32_t *fp32_Data, uint32_t fu32_Size, uint32_t fu32_Timeout) +{ + uint32_t i; + + uint32_t lu32_Timeout; + + /* Parameter Check */ + if ((fp32_Data == NULL) || (fu32_Size == 0U)) + { + return HAL_ERROR; + } + + /* I2S Ready? */ + if (hi2s->I2S_Status != HAL_I2S_STATE_READY) + { + return HAL_BUSY; + } + + hi2s->I2S_Status = HAL_I2S_STATE_BUSY_TX; + + /* transmit */ + for (i = 0; i < fu32_Size; i++) + { + hi2s->Instance->DAT = fp32_Data[i]; + + /* have no timeout */ + if (fu32_Timeout == 0) + { + while(!(hi2s->Instance->STATUS & I2S_STATUS_TXBE)); + } + else + { + lu32_Timeout = fu32_Timeout * 0xFF; + + while(!(hi2s->Instance->STATUS & I2S_STATUS_TXBE)) + { + if (lu32_Timeout-- == 0) + { + hi2s->I2S_Status = HAL_I2S_STATE_READY; + + return HAL_TIMEOUT; + } + } + } + } + + /* Wait for the last Byte */ + while (hi2s->Instance->STATUS & I2S_STATUS_TRANS); + + hi2s->I2S_Status = HAL_I2S_STATE_READY; + + return HAL_OK; +} + +/********************************************************************************* +* Function : HAL_I2S_Receive +* Description : Receive an amount of data in blocking mode +* Input : hi2s pointer to a I2S_HandleTypeDef structure that contains +* the configuration information for I2S module +* Input : fp32_Data: a 32-bit pointer to data buffer. +* Input : Size: number of data sample to be Receive +* Input : fu32_Timeout: Timeout duration +* Outpu : +* Author : Chris_Kyle Data : 2020 +**********************************************************************************/ +HAL_StatusTypeDef HAL_I2S_Receive(I2S_HandleTypeDef *hi2s, uint32_t *fp32_Data, uint32_t fu32_Size, uint32_t fu32_Timeout) +{ + uint32_t i; + + uint32_t lu32_Timeout; + + /* Parameter Check */ + if ((fp32_Data == NULL) || (fu32_Size == 0U)) + { + return HAL_ERROR; + } + + /* I2S Ready? */ + if (hi2s->I2S_Status != HAL_I2S_STATE_READY) + { + return HAL_BUSY; + } + + hi2s->I2S_Status = HAL_I2S_STATE_BUSY_RX; + + /* I2S Enable */ + hi2s->Instance->CTL |= I2S_CTL_I2SEN; + + /* Receive */ + for (i = 0; i < fu32_Size; i++) + { + /* have no timeout */ + if (fu32_Timeout == 0) + { + while(!(hi2s->Instance->STATUS & I2S_STATUS_RXBNE)); + fp32_Data[i] = hi2s->Instance->DAT; + } + else + { + lu32_Timeout = fu32_Timeout * 0xFF; + + while(!(hi2s->Instance->STATUS & I2S_STATUS_RXBNE)) + { + if (lu32_Timeout-- == 0) + { + hi2s->I2S_Status = HAL_I2S_STATE_READY; + + return HAL_TIMEOUT; + } + } + + fp32_Data[i] = hi2s->Instance->DAT; + } + } + + /* Disable I2S */ + hi2s->Instance->CTL &= ~I2S_CTL_I2SEN; + + hi2s->I2S_Status = HAL_I2S_STATE_READY; + + return HAL_OK; +} + +/********************************************************************************* +* Function : HAL_I2S_Transmit_IT +* Description : Transmit an amount of data in non-blocking mode with Interrupt +* Input : hi2s pointer to a I2S_HandleTypeDef structure that contains +* the configuration information for I2S module +* Input : fp32_Data: a 32-bit pointer to data buffer. +* Input : Size: number of data sample to be send +* Outpu : +* Author : Chris_Kyle Data : 2020 +**********************************************************************************/ +HAL_StatusTypeDef HAL_I2S_Transmit_IT(I2S_HandleTypeDef *hi2s, uint32_t *fp32_Data, uint32_t fu32_Size) +{ + /* Parameter Check */ + if ((fp32_Data == NULL) || (fu32_Size == 0U)) + { + return HAL_ERROR; + } + + /* I2S Ready? */ + if (hi2s->I2S_Status != HAL_I2S_STATE_READY) + { + return HAL_BUSY; + } + + hi2s->I2S_Status = HAL_I2S_STATE_BUSY_TX; + + hi2s->u32_Tx_Buffer = fp32_Data; + hi2s->u32_Tx_Size = fu32_Size; + hi2s->u32_Tx_Count = 0; + + hi2s->Instance->IE |= I2S_DIE_TBEIE; + + return HAL_OK; +} + +/********************************************************************************* +* Function : HAL_I2S_Receive_IT +* Description : Receive an amount of data in non-blocking mode with Interrupt +* Input : hi2s pointer to a I2S_HandleTypeDef structure that contains +* the configuration information for I2S module +* Input : fp32_Data: a 32-bit pointer to data buffer. +* Input : Size: number of data sample to be Receive +* Outpu : +* Author : Chris_Kyle Data : 2020 +**********************************************************************************/ +HAL_StatusTypeDef HAL_I2S_Receive_IT(I2S_HandleTypeDef *hi2s, uint32_t *fp32_Data, uint32_t fu32_Size) +{ + uint32_t lu32_Tempvalue; + + /* Parameter Check */ + if ((fp32_Data == NULL) || (fu32_Size == 0U)) + { + return HAL_ERROR; + } + + /* I2S Ready? */ + if (hi2s->I2S_Status != HAL_I2S_STATE_READY) + { + return HAL_BUSY; + } + + /* Clear Rx Buffer */ + while (hi2s->Instance->STATUS & I2S_STATUS_RXBNE) + { + lu32_Tempvalue = hi2s->Instance->DAT; + } + + hi2s->I2S_Status = HAL_I2S_STATE_BUSY_RX; + + hi2s->u32_Rx_Buffer = fp32_Data; + hi2s->u32_Rx_Size = fu32_Size; + hi2s->u32_Rx_Count = 0; + + hi2s->Instance->IE |= I2S_DIE_RBNEIE; + + /* I2S Enable */ + hi2s->Instance->CTL |= I2S_CTL_I2SEN; + + return HAL_OK; +} + +/********************************************************************************* +* Function : HAL_I2S_Transmit_DMA +* Description : Transmit an amount of data in non-blocking mode with DMA +* Input : hi2s: pointer to a I2S_HandleTypeDef structure that contains +* the configuration information for I2S module +* Input : fp32_Data: 32-bit pointer to data buffer. +* Input : Size: number of data sample to be sent +* Outpu : +* Author : Chris_Kyle Data : 2020 +**********************************************************************************/ +HAL_StatusTypeDef HAL_I2S_Transmit_DMA(I2S_HandleTypeDef *hi2s, uint32_t *fp32_Data, uint32_t fu32_Size) +{ + /* Parameter Check */ + if ((fp32_Data == NULL) || (fu32_Size == 0U)) + { + return HAL_ERROR; + } + + /* DMA transfer complete */ + if (!(hi2s->I2S_Status & I2S_STATUS_TRANS)) + { + hi2s->I2S_Status = HAL_I2S_STATE_READY; + } + + /* I2S Ready? */ + if (hi2s->I2S_Status != HAL_I2S_STATE_READY) + { + return HAL_BUSY; + } + + hi2s->I2S_Status = HAL_I2S_STATE_BUSY_TX; + + hi2s->Instance->IE |= I2S_DIE_DMATEN; + + HAL_DMA_Start_IT(hi2s->HDMA_Tx, (uint32_t)fp32_Data, (uint32_t)&hi2s->Instance->DAT, fu32_Size); + + return HAL_OK; +} + +/********************************************************************************* +* Function : HAL_I2S_Receive_DMA +* Description : Receive an amount of data in non-blocking mode with DMA +* Input : hi2s pointer to a I2S_HandleTypeDef structure that contains +* the configuration information for I2S module +* Input : fp32_Data: a 32-bit pointer to data buffer. +* Input : Size: number of data sample to be Receive +* Outpu : +* Author : Chris_Kyle Data : 2020 +**********************************************************************************/ +HAL_StatusTypeDef HAL_I2S_Receive_DMA(I2S_HandleTypeDef *hi2s, uint32_t *fp32_Data, uint32_t fu32_Size) +{ + /* Parameter Check */ + if ((fp32_Data == NULL) || (fu32_Size == 0U)) + { + return HAL_ERROR; + } + + /* DMA transfer complete */ + if (!(hi2s->I2S_Status & I2S_STATUS_TRANS)) + { + hi2s->I2S_Status = HAL_I2S_STATE_READY; + } + + /* I2S Ready? */ + if (hi2s->I2S_Status != HAL_I2S_STATE_READY) + { + return HAL_BUSY; + } + + hi2s->I2S_Status = HAL_I2S_STATE_BUSY_RX; + + hi2s->Instance->IE |= I2S_DIE_DMATEN; + + HAL_DMA_Start_IT(hi2s->HDMA_Rx, (uint32_t)&hi2s->Instance->DAT, (uint32_t)fp32_Data, fu32_Size); + + return HAL_OK; +} + diff --git a/bsp/acm32f4xx-nucleo/libraries/HAL_Driver/Src/HAL_IWDT.c b/bsp/acm32f4xx-nucleo/libraries/HAL_Driver/Src/HAL_IWDT.c new file mode 100644 index 0000000000..ba9bda6662 --- /dev/null +++ b/bsp/acm32f4xx-nucleo/libraries/HAL_Driver/Src/HAL_IWDT.c @@ -0,0 +1,72 @@ +/*********************************************************************** + * Filename : HAL_IWDT.c + * Description : HAL IWDT driver source file + * Author(s) : CWT + * version : V1.0 + * Modify date : 2020-04-17 + ***********************************************************************/ +#include "ACM32Fxx_HAL.h" + + +HAL_StatusTypeDef HAL_IWDT_Init(IWDT_HandleTypeDef * hidt) +{ + if (hidt == NULL) + { + return HAL_ERROR; + } + + System_Module_Enable(EN_IWDT); + System_Delay(1); + + System_Enable_Disable_RTC_Domain_Access(FUNC_ENABLE); + System_Enable_RC32K(); + System_Enable_Disable_Reset(RESET_ENABLE_SOURCE_IWDT, FUNC_ENABLE); + /*Enable IWDT */ + hidt->Instance->CMDR = IWDT_ENABLE_COMMAND; + System_Delay(10); + /*Enable Write */ + hidt->Instance->CMDR = IWDT_WRITE_ENABLE_COMMAND; + System_Delay(10); + + hidt->Instance->PR = hidt->Init.Prescaler; + hidt->Instance->RLR = hidt->Init.Reload; + hidt->Instance->WINR = hidt->Init.Window; + hidt->Instance->WUTR = hidt->Init.Wakeup; + System_Delay(1); + while(hidt->Instance->SR & (0x0F)){}; // wait for configuration done + + if (hidt->Init.Reload > hidt->Init.Wakeup) + { + /*Enable Wake up */ + hidt->Instance->CMDR = IWDT_WAKEUP_ENABLE_COMMAND; + } + + hidt->Instance->CMDR = IWDT_RELOAD_COMMAND; + System_Delay(1); + while(hidt->Instance->SR & (1 << 4)){}; + + return HAL_OK; + +} + +HAL_StatusTypeDef HAL_IWDT_Kick_Watchdog_Wait_For_Done(IWDT_HandleTypeDef * hidt) +{ + hidt->Instance->CMDR = IWDT_RELOAD_COMMAND; + System_Delay(1); + while(hidt->Instance->SR & (1 << 4)){}; //wait for kick watchdog done + + return HAL_OK; +} + + + + + + + + + + + + + diff --git a/bsp/acm32f4xx-nucleo/libraries/HAL_Driver/Src/HAL_LPUART.c b/bsp/acm32f4xx-nucleo/libraries/HAL_Driver/Src/HAL_LPUART.c new file mode 100644 index 0000000000..babb114db3 --- /dev/null +++ b/bsp/acm32f4xx-nucleo/libraries/HAL_Driver/Src/HAL_LPUART.c @@ -0,0 +1,452 @@ +/* + ****************************************************************************** + * @file HAL_LPUART.c + * @version V1.0.0 + * @date 2020 + * @brief LPUART HAL module driver. + * This file provides firmware functions to manage the following + * functionalities of the Universal Asynchronous Receiver Transmitter Peripheral (LPUART). + * @ Initialization and de-initialization functions + * @ IO operation functions + * @ Peripheral Control functions + ****************************************************************************** +*/ +#include "ACM32Fxx_HAL.h" + +/********************************************************************************* +* Function : HAL_LPUART_IRQHander +* Description : LPUART IRQHander +* Input : +* Outpu : +* Author : CWT Data : 2020 +**********************************************************************************/ +void HAL_LPUART_IRQHander(LPUART_HandleTypeDef *hlpuart) +{ + while ( (hlpuart->Instance->SR) & (1U << LPUART_SR_RX_INDEX)) + { + if(hlpuart->rx_read_index != (((hlpuart->rx_write_index) + 1)% (hlpuart->rx_buffer_size) ) ) + { + hlpuart->rx_buffer[hlpuart->rx_write_index] = hlpuart->Instance->RXDR; + hlpuart->rx_write_index = ((hlpuart->rx_write_index + 1)%(hlpuart->rx_buffer_size) ); + } + else + { + hlpuart->Instance->SR = (1U << LPUART_SR_RX_INDEX); // buffer overflow + return; + } + } +} +/************************************************************************ + * function : HAL_UART_Buffer_Init + * Description: uart buffer initiation. + * input : + * UART_HandleTypeDef *huart: pointer to uart handle structure + * return: 0: FAIL; 1: SUCCESS + ************************************************************************/ +HAL_StatusTypeDef HAL_LPUART_Buffer_Init(LPUART_HandleTypeDef *hlpuart) +{ + if(0x00 == IS_LPUART_INSTANCE(hlpuart->Instance)) + { + return HAL_ERROR; + } + hlpuart->rx_read_index = 0; + hlpuart->rx_write_index = 0; + hlpuart->tx_busy = 0; + return HAL_OK; +} + +/********************************************************************************** + * function : HAL_LPUART_MSPInit + * Description: UART MCU specific initiation, such as IO share, module clock, ... + * input : + * UART_HandleTypeDef *huart: pointer to uart handle structure + * return: 0: FAIL; 1: SUCCESS + ***************************************************************************************/ + +__weak void HAL_LPUART_MSPInit(LPUART_HandleTypeDef *hlpuart) +{ + GPIO_InitTypeDef gpio_init; + + System_Module_Reset(RST_LPUART); + gpio_init.Pin = GPIO_PIN_2|GPIO_PIN_3; // TX PA2 RX PA3 + gpio_init.Mode = GPIO_MODE_AF_PP; + gpio_init.Pull = GPIO_PULLUP; + gpio_init.Alternate = GPIO_FUNCTION_6; + HAL_GPIO_Init(GPIOA,&gpio_init); + System_Module_Enable(EN_LPUART); +} + +/********************************************************************************* +* Function : HAL_LPUART_MspDeInit +* Description : LPUART MSP De-Initialization +* This function frees the hardware resources used in this example: +* - Disable the Peripheral's clock +* - Revert GPIO configuration to their default state +* Input : hcan : pointer to a CAN_HandleTypeDef structure that contains +* the configuration information for CAN module +* Output : +* Author : CWT Data : 2020 +**********************************************************************************/ +void HAL_LPUART_MspDeInit(LPUART_HandleTypeDef *hlpuart) +{ + GPIO_InitTypeDef GPIO_InitStructure; + /* Initialization GPIO */ + /* // TX PA2 RX PA3 */ + HAL_GPIO_DeInit(GPIOA, GPIO_PIN_2); + HAL_GPIO_DeInit(GPIOA, GPIO_PIN_3); +} +/********************************************************************************** + * function : HAL_LPUART_Set_Baud_Rate + * Description: set uart module's baud rate. It should be set when UART is disabled. + * input : + * UART_HandleTypeDef *huart: pointer to uart handle structure + * return: 0: FAIL; 1: SUCCESS + ***************************************************************************************/ +uint8_t HAL_LPUART_Set_Baud_Rate(LPUART_HandleTypeDef *hlpuart, uint32_t lpuart_clk, uint32_t baud_rate) +{ + uint32_t ibaud, fbaud, rxsamp; + + if(0x00 == IS_LPUART_INSTANCE(hlpuart->Instance)) + { + return 0; + } + ibaud = 2; + fbaud = 0x952; + rxsamp = 1; + switch(lpuart_clk) + { + case 32000: + case 32768: + switch(baud_rate) + { + case 9600: + ibaud = 2; + fbaud = 0x952; + break; + + case 4800: + ibaud = 5; + fbaud = 0xefb; + break; + + case 2400: + ibaud = 12; + fbaud = 0x6db; + break; + + case 1200: + ibaud = 26; + fbaud = 0x492; + break; + default: + ibaud = 2; + fbaud = 0x952; + break; + } + rxsamp = ibaud >> 1; + break; + + case 1875000: // for ABP CLK=120M/2=60M lpuart clk = 60M/32=1.875M + switch(baud_rate) + { + case 256000: + ibaud = 6; + fbaud = 0x888; + break; + + case 115200: + ibaud = 15; + fbaud = 0x888; + break; + } + rxsamp = ibaud >> 1; + break; + + default: // for ABP CLK=180M/2=90M lpuart clk = 90M/32=2.8125M + switch(baud_rate) + { + case 256000: + ibaud = 9; //2.8125M/256000=10.984 ibaud=(10-1) + fbaud = 0x7FE; // 0.984 *11=10 + break; + + case 115200: + ibaud = 23; //2.8125M/115200=24.4140625 ibaud=(24-1) + fbaud = 0x249; //0.4140625*11=4 + break; + } + rxsamp = ibaud >> 1; + break; + } + hlpuart->Instance->IBAUD = ibaud | (rxsamp << 8); + hlpuart->Instance->FBAUD = fbaud; + return 1; +} + +/************************************************************************ + * function : HAL_LPUART_Config + * Description: Configure UART module parameters, such as baudrate, parity, + * stop bits, dataword. + * input : + * UART_HandleTypeDef *huart: pointer to uart handle structure + * return: 0: FAIL; 1: SUCCESS + ************************************************************************/ +uint8_t HAL_LPUART_Config(LPUART_HandleTypeDef *hlpuart) +{ + volatile uint32_t temp_reg; + if(0x00 == IS_LPUART_INSTANCE(hlpuart->Instance)) + { + return 0; + } + temp_reg = 1U << 7; // default value + temp_reg |= ((hlpuart->ConfigParam.WordLength << 4) | (hlpuart->ConfigParam.StopBits << 3)); + switch(hlpuart->ConfigParam.Parity) + { + case LPUART_PARITY_NONE: + break; // do nothing + + case LPUART_PARITY_SELECT_ODD: + case LPUART_PARITY_SELECT_EVEN: + temp_reg |= (((hlpuart->ConfigParam.Parity - LPUART_PARITY_SELECT_ODD) << LPUART_EPS_INDEX) | (1 << LPUART_PEN_INDEX)); + break; + + case LPUART_PARITY_SELECT_ONE: + case LPUART_PARITY_SELECT_ZERO: + temp_reg |= (((hlpuart->ConfigParam.Parity - LPUART_PARITY_SELECT_ONE) << LPUART_EPS_INDEX) | (1 << LPUART_SPS_INDEX) | (1 << LPUART_PEN_INDEX) ); + break; + } + hlpuart->Instance->LCR = temp_reg; + return 1; +} + +/********************************************************************************* +* Function : LPUART_Clock_Select +* Description : Select the LPUART clock. +* Input : lpuart_clk_src:Could be LPUART_CLOCK_SOURCE_RC32K LPUART_CLOCK_SOURCE_XTAL LPUART_CLOCK_SOURCE_PLL_DIV +* Outpu : +* Author : CWT Data : 2020 +**********************************************************************************/ +void LPUART_Clock_Select(uint8_t lpuart_clk_src) +{ + if (0 == lpuart_clk_src) + { + SCU->CCR2 &= (~(BIT13 | BIT14) ); // RC32K + } + else if (1 == lpuart_clk_src) + { + SCU->CCR2 = (SCU->CCR2 & (~(BIT13 | BIT14) )) | (BIT13); // XTAL + } + else + { + SCU->CCR2 = (SCU->CCR2 & (~(BIT11 | BIT12| BIT13 | BIT14) )) | (BIT11 | BIT12 | BIT14); // pclk/32 + } +} +/************************************************************************ + * function : HAL_LPUART_Init + * Description: uart initial with parameters. + * input : + * UART_HandleTypeDef *huart: pointer to uart handle structure + * return: 0: FAIL; 1: SUCCESS + ************************************************************************/ +HAL_StatusTypeDef HAL_LPUART_Init(LPUART_HandleTypeDef *hlpuart) +{ + uint32_t lpuart_clock; + if(0x00 == IS_LPUART_INSTANCE(hlpuart->Instance)) + { + return HAL_ERROR;; + } + + HAL_LPUART_Buffer_Init(hlpuart); + /*reset module, configure tx and rx, enable module clock*/ + HAL_LPUART_MSPInit(hlpuart); + + if (LPUART_CLOCK_SOURCE_RC32K == hlpuart->ConfigParam.ClockSrc) + { + lpuart_clock = 32000; + System_Module_Enable(EN_RTC); + System_Enable_Disable_RTC_Domain_Access(FUNC_ENABLE); + System_Enable_RC32K(); + LPUART_Clock_Select(0); + } + else if (LPUART_CLOCK_SOURCE_XTAL == hlpuart->ConfigParam.ClockSrc) + { + lpuart_clock = 32768; + System_Module_Enable(EN_RTC); + System_Enable_Disable_RTC_Domain_Access(FUNC_ENABLE); + System_Enable_XTAL(); + LPUART_Clock_Select(1); + } + else + { + lpuart_clock = System_Get_APBClock()/32; + LPUART_Clock_Select(2); + } + HAL_LPUART_Set_Baud_Rate(hlpuart, lpuart_clock, hlpuart->ConfigParam.BaudRate); + + HAL_LPUART_Config(hlpuart); + + hlpuart->Instance->SR = LPUART_SR_BITS_ALL; + hlpuart->Instance->IE = (1U << LPUART_IE_RX_INDEX); + hlpuart->Instance->CR = (1U << LPUART_CR_RXE_INDEX) | (1 << LPUART_CR_TXE_INDEX); + hlpuart->Instance->LCR=((hlpuart->StopWakeup.Wakeup_Source<<5)|(hlpuart->StopWakeup.Wakeup_Check<<7)); + hlpuart->Instance->ADDR=(hlpuart->StopWakeup.Wakeup_Addr); + NVIC_ClearPendingIRQ(LPUART_IRQn); + NVIC_EnableIRQ(LPUART_IRQn); + return HAL_OK;; +} +HAL_StatusTypeDef HAL_LPUART_DeInit(LPUART_HandleTypeDef *hlpuart) +{ + /* Check handle */ + if(!IS_LPUART_INSTANCE(hlpuart->Instance)) return HAL_ERROR; + HAL_LPUART_MspDeInit(hlpuart); + /* Disable LPUART clock */ + System_Module_Disable(EN_LPUART); + /* Return function status */ + return HAL_OK; +} +/************************************************************************ + * function : HAL_LPUART_Wait_TX_Done + * Description: wait uart not busy + * input : + * UART_HandleTypeDef *huart: pointer to uart handle structure + * return: 0: FAIL; 1: SUCCESS + ************************************************************************/ +HAL_StatusTypeDef HAL_LPUART_Wait_TX_Done(LPUART_HandleTypeDef *hlpuart) +{ + while (0 == (hlpuart->Instance->SR & (1 << LPUART_SR_TX_FINISH_INDEX) ) ) {}; + hlpuart->Instance->SR = (1 << LPUART_SR_TX_FINISH_INDEX); + return HAL_OK; +} + +void HAL_LPUART_Output(LPUART_HandleTypeDef *hlpuart, unsigned char c) +{ + if ((hlpuart->Instance->SR) & (1U << LPUART_SR_TX_EMPTY_INDEX) ) + { + hlpuart->Instance->TXDR = c; + } + + HAL_LPUART_Wait_TX_Done(hlpuart); +} + +/************************************************************************ + * function : uart_send_bytes + * Description: uart send bytes + * input : + * UINT32 uart_index: Serial port number + * UINT8* buff: out buffer + * UINT32 length: buffer length + * return: none + ************************************************************************/ +void HAL_LPUART_Send_Bytes(LPUART_HandleTypeDef *hlpuart, uint8_t *buff, uint32_t length) +{ + uint32_t i; + for (i = 0; i < length; i++) + { + HAL_LPUART_Output(hlpuart, *buff++); + } +} + +/************************************************************************ + * function : HAL_LPUART_Receive_Bytes_Timeout + * Description: uart receive bytes + * input : + * UART_HandleTypeDef *huart: pointer to uart handle structure + * UINT8* buff: out buffer + * UINT32 length: buffer length + * UINT32 ms: number of ms to delay one byte + * return: received bytes + ************************************************************************/ +uint32_t HAL_LPUART_Receive_Bytes_Timeout(LPUART_HandleTypeDef *hlpuart, uint8_t * rxbuff, uint32_t length, uint32_t ms) +{ + volatile uint32_t i, timeout, count;; + if(0x00 == IS_LPUART_INSTANCE(hlpuart->Instance)) + { + return 0; + } + timeout = (System_Get_APBClock() >> 13) * ms; + count = timeout; + i = 0; + while(i < length) + { + if((hlpuart->rx_read_index) != (hlpuart->rx_write_index)) + { + rxbuff[i] = hlpuart->rx_buffer[hlpuart->rx_read_index]; + hlpuart->rx_read_index = (((hlpuart->rx_read_index) + 1)%(hlpuart->rx_buffer_size) ); + count = timeout; + i++; + } + else + { + if (0 == count)//timeout + { + break; + } + else + { + count--; + } + } + } + return i; +} +/************************************************************************ + * function : HAL_LPUART_Receive_Bytes + * Description: LPUART receive bytes. + * input : + * UART_HandleTypeDef *huart: pointer to uart handle structure + * buff:receive data buff + * length:length of buff + * return:length + ************************************************************************/ +uint32_t HAL_LPUART_Receive_Bytes(LPUART_HandleTypeDef *hlpuart, uint8_t * rxbuff, uint32_t length) +{ + volatile uint32_t i, ie_backup; + if(0x00 == IS_LPUART_INSTANCE(hlpuart->Instance)) + { + return 0; + } + ie_backup = hlpuart->Instance->IE; + hlpuart->Instance->IE = 0; + i = 0; + while(i < length) + { + if( (hlpuart->Instance->SR) & (1U << LPUART_SR_RX_INDEX) ) + { + rxbuff[i] = hlpuart->Instance->RXDR; + i++; + } + } + hlpuart->Instance->IE = ie_backup; + return length; +} +/************************************************************************ + * function : HAL_LPUART_DMA_Send_Bytes + * Description: LPUART send bytes by DMA. + * input : + * UART_HandleTypeDef *huart: pointer to uart handle structure + * buff:send data buff + * length:length of buff + * return:none + ************************************************************************/ +void HAL_LPUART_DMA_Send_Bytes(LPUART_HandleTypeDef *hlpuart, uint8_t *buff, uint32_t length) +{ + hlpuart->Instance->CR |= (1U << LPUART_CR_DMA_EN_INDEX); + hlpuart->tx_busy = 1; + HAL_DMA_Start_IT(hlpuart->dma_tx_handler, (uint32_t)buff, (uint32_t)&hlpuart->Instance->TXDR, length); + } + +/************************************************************************ + * function : HAL_LPUART_Clear_Wakeup_Flags + * Description: Clear the LPUART STOP wake up flag. + * input : + * UART_HandleTypeDef *huart: pointer to uart handle structure + * Wakeup_Bits:LPUART wakeup flag,could be: LPUART_WAKEUP_RX_BIT LPUART_WAKEUP_MATCH_BIT LPUART_WAKEUP_START_BIT + * return:none + ************************************************************************/ + +void HAL_LPUART_Clear_Wakeup_Flags(LPUART_HandleTypeDef *hlpuart, uint32_t Wakeup_Bits) +{ + hlpuart->Instance->SR = Wakeup_Bits; +} + + diff --git a/bsp/acm32f4xx-nucleo/libraries/HAL_Driver/Src/HAL_OPA.c b/bsp/acm32f4xx-nucleo/libraries/HAL_Driver/Src/HAL_OPA.c new file mode 100644 index 0000000000..a5f84cdbdb --- /dev/null +++ b/bsp/acm32f4xx-nucleo/libraries/HAL_Driver/Src/HAL_OPA.c @@ -0,0 +1,329 @@ +/* + ****************************************************************************** + * @file HAL_OPA.c + * @version V1.0.0 + * @date 2020 + * @brief OPA HAL module driver. + * This file provides firmware functions to manage the following + * functionalities of the Operational Amplifier (OPA). + * @ Initialization and de-initialization functions + * @ IO operation functions + * @ Peripheral Control functions + ****************************************************************************** +*/ +#include "ACM32Fxx_HAL.h" + +/************************************************************************ + * function : HAL_OPA_MspInit + * Description: OPA MCU specific initiation, such as IO share, module clock, ... + * input : + * OPA_HandleTypeDef *hopa: pointer to opa handle structure + * return: none +************************************************************************/ +__weak void HAL_OPA_MspInit(OPA_HandleTypeDef* hopa) +{ + /* + NOTE : This function should be modified by the user. + */ + + /* For Example */ + GPIO_InitTypeDef GPIO_OPA; + + /* Enable Clock */ + System_Module_Enable(EN_OPA); + + if(hopa->Init.OpaX == OPA1) + { + /* OPA1 GPIO inition VINP:PC4*/ + /* OPA1 GPIO inition VINM:PA3*/ + /* OPA1 GPIO inition OPA1_VOUT:PA2*/ + GPIO_OPA.Pin = GPIO_PIN_2 | GPIO_PIN_3; + GPIO_OPA.Mode = GPIO_MODE_ANALOG; + GPIO_OPA.Pull = GPIO_NOPULL; + HAL_GPIO_Init(GPIOA, &GPIO_OPA); + + GPIO_OPA.Pin = GPIO_PIN_4; + GPIO_OPA.Mode = GPIO_MODE_ANALOG; + GPIO_OPA.Pull = GPIO_NOPULL; + HAL_GPIO_Init(GPIOC, &GPIO_OPA); + } + + else if(hopa->Init.OpaX == OPA2) + { + /* OPA2 GPIO inition VINP:PA7*/ + /* OPA2 GPIO inition VINM:PC5*/ + /* OPA2 GPIO inition OPA2_VOUT:PA6*/ + GPIO_OPA.Pin = GPIO_PIN_6 | GPIO_PIN_7; + GPIO_OPA.Mode = GPIO_MODE_ANALOG; + GPIO_OPA.Pull = GPIO_NOPULL; + HAL_GPIO_Init(GPIOA, &GPIO_OPA); + + GPIO_OPA.Pin = GPIO_PIN_5; + GPIO_OPA.Mode = GPIO_MODE_ANALOG; + GPIO_OPA.Pull = GPIO_NOPULL; + HAL_GPIO_Init(GPIOC, &GPIO_OPA); + + } + else if(hopa->Init.OpaX == OPA3) + { + /* OPA3 GPIO inition VINP:PA4*/ + /* OPA3 GPIO inition VINM:PB10*/ + /* OPA3 GPIO inition OPA2_VOUT:PB1*/ + GPIO_OPA.Pin = GPIO_PIN_4; + GPIO_OPA.Mode = GPIO_MODE_ANALOG; + GPIO_OPA.Pull = GPIO_NOPULL; + HAL_GPIO_Init(GPIOA, &GPIO_OPA); + + GPIO_OPA.Pin = GPIO_PIN_1 | GPIO_PIN_10; + GPIO_OPA.Mode = GPIO_MODE_ANALOG; + GPIO_OPA.Pull = GPIO_NOPULL; + HAL_GPIO_Init(GPIOB, &GPIO_OPA); + } +} + +/************************************************************************ + * function : HAL_OPA_MspDeInit + * Description: OPA MCU De-initiation, such as IO share, module clock, ... + * input : + * OPA_HandleTypeDef *hopa: pointer to opa handle structure + * return: none +************************************************************************/ +__weak void HAL_OPA_MspDeInit(OPA_HandleTypeDef* hopa) +{ + /* + NOTE : This function should be modified by the user. + */ + + /* For Example */ + + /* Reset the OPA */ + System_Module_Reset(RST_OPA); + /* Disable Clock */ + System_Module_Disable(EN_OPA); + +} + +/************************************************************************ + * function : HAL_OPA_Init + * Description: opa initial with parameters. + * input : + * OPA_HandleTypeDef *hopa: pointer to opa handle structure + ************************************************************************/ +HAL_StatusTypeDef HAL_OPA_Init(OPA_HandleTypeDef* hopa) +{ + uint32_t u32RegTemp, u32NvrTrimValue; + __IO uint32_t *gu32RegCrx; + uint8_t trim_value; + + /* Check the OPA handle allocation */ + if (hopa == NULL) + { + return HAL_ERROR; + } + + /* Check the parameters */ + if(!IS_OPA_ALL_INSTANCE(hopa->Instance)) return HAL_ERROR; + if(!IS_OPA_ALL_OPAX(hopa->Init.OpaX)) return HAL_ERROR; + if(!IS_OPA_ALL_HSM(hopa->Init.Hsm)) return HAL_ERROR; + if(!IS_OPA_ALL_GAIN(hopa->Init.Gain)) return HAL_ERROR; + if(!IS_OPA_ALL_POL(hopa->Init.PolSel)) return HAL_ERROR; + if(!IS_OPA_ALL_MODE(hopa->Init.OpaMode)) return HAL_ERROR; + if(!IS_OPA_ALL_VINP(hopa->Init.VinPSel)) return HAL_ERROR; + if(!IS_OPA_ALL_OUT(hopa->Init.OutSel)) return HAL_ERROR; + if(!IS_OPA_ALL_VINM0(hopa->Init.VinM0En)) return HAL_ERROR; + if(!IS_OPA_ALL_TRIM(hopa->Init.TrimEn)) return HAL_ERROR; + + if(hopa->Init.OpaX == OPA1) + gu32RegCrx = &hopa->Instance->OPA1_CSR; + else if(hopa->Init.OpaX == OPA2) + gu32RegCrx = &hopa->Instance->OPA2_CSR; + else if(hopa->Init.OpaX == OPA3) + gu32RegCrx = &hopa->Instance->OPA3_CSR; + + /* Init the low level hardware : GPIO, CLOCK */ + HAL_OPA_MspInit(hopa); + + if(READ_BIT(*gu32RegCrx, OPA_CSR_LOCK)) + { + System_Module_Reset(RST_OPA); + } + + u32RegTemp = *gu32RegCrx; + + u32RegTemp = ((hopa->Init.Hsm << 28) & OPA_CSR_HSM) | \ + ((hopa->Init.Gain << OPA_CSR_GAIN_SEL_POS) & OPA_CSR_GAIN_SEL_MASK) | \ + ((hopa->Init.PolSel << OPA_CSR_POL_SEL_POS) & OPA_CSR_POL_SEL_MASK) | \ + ((hopa->Init.VinM0En << 20) & OPA_CSR_VINM0_SEL_POS) | \ + ((hopa->Init.OpaMode << OPA_CSR_MODE_SEL_POS) & OPA_CSR_MODE_SEL_MASK) | \ + ((hopa->Init.VinPSel << OPA_CSR_VINP_SEL_POS) & OPA_CSR_VINP_SEL_MASK) | \ + ((hopa->Init.OutSel << OPA_CSR_OUT_SEL_POS) & OPA_CSR_OUT_SEL_MASK); + + *gu32RegCrx = u32RegTemp; + + /* Enable the opa */ + SET_BIT(*gu32RegCrx, OPA_CSR_EN); + + if(hopa->Init.TrimEn == OPA_CSR_TRIM_ENABLE) + { + /* Trim the OPA_CSR_CAL_H N channel */ + SET_BIT(*gu32RegCrx, OPA_CSR_CAL_NEN); + CLEAR_BIT(*gu32RegCrx, OPA_CSR_CAL_PEN); + + for(trim_value=0;trim_value<31;trim_value++) + { + MODIFY_REG(*gu32RegCrx,OPA_CSR_TRIM_OSN_MASK,(trim_value)<Init.OpaX-1)*4); //Read the OPA trim value; + if(((~(u32NvrTrimValue>>16))&0xFFFF) != (u32NvrTrimValue&0xFFFF)) return HAL_ERROR; + + u32NvrTrimValue = u32NvrTrimValue & 0xFFFF; + + MODIFY_REG(*gu32RegCrx,OPA_CSR_TRIM_OSN_MASK,((u32NvrTrimValue&0x1F)<>5)&0x1F)<Init, 0, sizeof(hopa->Init)); + + return HAL_OK; +} +/************************************************************************ + * function : HAL_OPA_Enable + * Description: opa enable. + * input : + * OPA_HandleTypeDef *hopa: pointer to opa handle structure + ************************************************************************/ +HAL_StatusTypeDef HAL_OPA_Enable(OPA_HandleTypeDef* hopa) +{ + uint32_t u32RegTemp; + __IO uint32_t *gu32RegCrx; + + /* Check the OPA handle allocation */ + if (hopa == NULL) + { + return HAL_ERROR; + } + + /* Check the parameters */ + if(!IS_OPA_ALL_INSTANCE(hopa->Instance)) return HAL_ERROR; + if(!IS_OPA_ALL_OPAX(hopa->Init.OpaX)) return HAL_ERROR; + + if(hopa->Init.OpaX == OPA1) + gu32RegCrx = &hopa->Instance->OPA1_CSR; + else if(hopa->Init.OpaX == OPA2) + gu32RegCrx = &hopa->Instance->OPA2_CSR; + else if(hopa->Init.OpaX == OPA3) + gu32RegCrx = &hopa->Instance->OPA3_CSR; + + /* Enable the opa */ + SET_BIT(*gu32RegCrx, OPA_CSR_EN); + + return HAL_OK; +} + +/************************************************************************ + * function : HAL_OPA_Disable + * Description: opa disable. + * input : + * OPA_HandleTypeDef *hopa: pointer to opa handle structure + ************************************************************************/ +HAL_StatusTypeDef HAL_OPA_Disable(OPA_HandleTypeDef* hopa) +{ + uint32_t u32RegTemp; + __IO uint32_t *gu32RegCrx; + + /* Check the OPA handle allocation */ + if (hopa == NULL) + { + return HAL_ERROR; + } + + /* Check the parameters */ + if(!IS_OPA_ALL_INSTANCE(hopa->Instance)) return HAL_ERROR; + if(!IS_OPA_ALL_OPAX(hopa->Init.OpaX)) return HAL_ERROR; + + if(hopa->Init.OpaX == OPA1) + gu32RegCrx = &hopa->Instance->OPA1_CSR; + else if(hopa->Init.OpaX == OPA2) + gu32RegCrx = &hopa->Instance->OPA2_CSR; + else if(hopa->Init.OpaX == OPA3) + gu32RegCrx = &hopa->Instance->OPA3_CSR; + + /* Disable the opa */ + CLEAR_BIT(*gu32RegCrx, OPA_CSR_EN); + + return HAL_OK; +} + +/************************************************************************ + * function : HAL_OPA_Lock + * Description: opa lock. + * input : + * OPA_HandleTypeDef *hopa: pointer to opa handle structure + ************************************************************************/ +HAL_StatusTypeDef HAL_OPA_Lock(OPA_HandleTypeDef* hopa) +{ + uint32_t u32RegTemp; + __IO uint32_t *gu32RegCrx; + + /* Check the OPA handle allocation */ + if (hopa == NULL) + { + return HAL_ERROR; + } + + /* Check the parameters */ + if(!IS_OPA_ALL_INSTANCE(hopa->Instance)) return HAL_ERROR; + if(!IS_OPA_ALL_OPAX(hopa->Init.OpaX)) return HAL_ERROR; + + if(hopa->Init.OpaX == OPA1) + gu32RegCrx = &hopa->Instance->OPA1_CSR; + else if(hopa->Init.OpaX == OPA2) + gu32RegCrx = &hopa->Instance->OPA2_CSR; + else if(hopa->Init.OpaX == OPA3) + gu32RegCrx = &hopa->Instance->OPA3_CSR; + + /* Lock the opa */ + SET_BIT(*gu32RegCrx, OPA_CSR_LOCK); + + return HAL_OK; +} diff --git a/bsp/acm32f4xx-nucleo/libraries/HAL_Driver/Src/HAL_RTC.c b/bsp/acm32f4xx-nucleo/libraries/HAL_Driver/Src/HAL_RTC.c new file mode 100644 index 0000000000..c72bc2a084 --- /dev/null +++ b/bsp/acm32f4xx-nucleo/libraries/HAL_Driver/Src/HAL_RTC.c @@ -0,0 +1,485 @@ +/* + ****************************************************************************** + * @file HAL_RTC.c + * @version V1.0.0 + * @date 2020 + * @brief RTC HAL module driver. + * This file provides firmware functions to manage the following + * functionalities of the Real-Time Clock (RTC) peripheral: + * + Initialization functions + * + Time and Date configuration + * + Alarm configuration + * + WakeUp Timer configuration + * + TimeStamp configuration + * + Tampers configuration + * + Backup Data Registers configuration + * + RTC Tamper and TimeStamp Pins Selection + * + Interrupts and flags management + ****************************************************************************** +*/ +#include "ACM32Fxx_HAL.h" + +/********************************************************************************* +* Function : HAL_RTC_Config +* Description : Initialize the RTC peripheral +* Input : +* Outpu : +* Author : Chris_Kyle Data : 2020 +**********************************************************************************/ +HAL_StatusTypeDef HAL_RTC_Config(RTC_ConfigTypeDef *hrtc) +{ +#if (USE_FULL_ASSERT == 1) + /* Check RTC Parameter */ + if (!IS_RTC_CLOCKSRC(hrtc->u32_ClockSource)) return HAL_ERROR; + if (!IS_RTC_COMPENSATION(hrtc->u32_Compensation)) return HAL_ERROR; +#endif + + /* RTC domain write enable */ + SCU->STOPCFG |= (1 << 0); + + PMU->CR1 |= RPMU_CR_RTCEN; + + switch (hrtc->u32_ClockSource) + { + case RTC_CLOCK_RC32K: + { + PMU->ANACR |= RPMU_ANACR_RC32K_EN; + while(!(PMU->ANACR & RPMU_ANACR_RC32K_RDY)); + + PMU->CR1 &= ~RTC_CLOCK_XTL; + }break; + + case RTC_CLOCK_XTL: + { + PMU->ANACR = (PMU->ANACR & ~RPMU_ANACR_XTLDRV) | (RPMU_ANACR_XTLDRV_1 | RPMU_ANACR_XTLDRV_0); + + PMU->ANACR |= RPMU_ANACR_XTLEN; + while(!(PMU->ANACR & RPMU_ANACR_XTLRDY)); + + PMU->CR1 |= RTC_CLOCK_XTL; + }break; + + default: break; + } + + if (hrtc->u32_CompensationValue) + { + RTC->ADJUST = hrtc->u32_Compensation | hrtc->u32_CompensationValue; + } + + return HAL_OK; +} + +/********************************************************************************* +* Function : HAL_RTC_SetTime +* Description : Set RTC current time. +* Input : fp_Time Pointer to Time structure. +* Outpu : +* Author : Chris_Kyle Data : 2020 +**********************************************************************************/ +void HAL_RTC_SetTime(RTC_TimeTypeDef *fp_Time) +{ +#if (USE_FULL_ASSERT == 1) + /* Check RTC Parameter */ + if (!IS_RTC_HOUR(fp_Time->u8_Hours)) return; + if (!IS_RTC_MIN(fp_Time->u8_Minutes)) return; + if (!IS_RTC_SEC(fp_Time->u8_Seconds)) return; +#endif + + /* Write-Protect Disable */ + RTC->WP = 0xCA53CA53; + + RTC->HOUR = fp_Time->u8_Hours; + RTC->MIN = fp_Time->u8_Minutes; + RTC->SEC = fp_Time->u8_Seconds; + + /* Write-Protect Enable */ + RTC->WP = 0; +} + +/********************************************************************************* +* Function : HAL_RTC_GetTime +* Description : Get RTC current time. +* Input : fp_Time Pointer to Time structure. +* Outpu : +* Author : Chris_Kyle Data : 2020 +**********************************************************************************/ +void HAL_RTC_GetTime(RTC_TimeTypeDef *fp_Time) +{ + fp_Time->u8_Hours = RTC->HOUR; + fp_Time->u8_Minutes = RTC->MIN; + fp_Time->u8_Seconds = RTC->SEC; +} + +/********************************************************************************* +* Function : HAL_RTC_SetDate +* Description : Set RTC current Date. +* Input : fp_Date Pointer to Date structure. +* Outpu : +* Author : Chris_Kyle Data : 2020 +**********************************************************************************/ +void HAL_RTC_SetDate(RTC_DateTypeDef *fp_Date) +{ +#if (USE_FULL_ASSERT == 1) + /* Check RTC Parameter */ + if (!IS_RTC_YEAR(fp_Date->u8_Year)) return; + if (!IS_RTC_MONTH(fp_Date->u8_Month)) return; + if (!IS_RTC_DAY(fp_Date->u8_Date)) return; + if (!IS_RTC_WEEKDAY(fp_Date->u8_WeekDay)) return; +#endif + + /* Write-Protect Disable */ + RTC->WP = 0xCA53CA53; + + RTC->YEAR = fp_Date->u8_Year; + RTC->MONTH = fp_Date->u8_Month; + RTC->DATE = fp_Date->u8_Date; + RTC->WEEK = fp_Date->u8_WeekDay; + + /* Write-Protect Enable */ + RTC->WP = 0; +} + +/********************************************************************************* +* Function : HAL_RTC_GetDate +* Description : Get RTC current Date. +* Input : fp_Date Pointer to Date structure. +* Outpu : +* Author : Chris_Kyle Data : 2020 +**********************************************************************************/ +void HAL_RTC_GetDate(RTC_DateTypeDef *fp_Date) +{ + fp_Date->u8_Year = RTC->YEAR; + fp_Date->u8_Month = RTC->MONTH; + fp_Date->u8_Date = RTC->DATE; + fp_Date->u8_WeekDay = RTC->WEEK; +} + +/********************************************************************************* +* Function : HAL_RTC_AlarmConfig +* Description : Alarm Config +* Input : fp_Alarm Pointer to ALarm structure. +* Outpu : +* Author : Chris_Kyle Data : 2020 +**********************************************************************************/ +void HAL_RTC_AlarmConfig(RTC_AlarmTypeDef *fp_Alarm) +{ + uint32_t lu32_WeekDay; + +#if (USE_FULL_ASSERT == 1) + /* Check RTC Parameter */ + if (!IS_RTC_ALARM_MODE(fp_Alarm->u32_AlarmMode)) return; + if (!IS_RTC_ALARM_INT(fp_Alarm->u32_AlarmInterrupt)) return; + if (!IS_RTC_ALARM_DAY_MASK(fp_Alarm->u32_DayMask)) return; + if (!IS_RTC_ALARM_HOUR_MASK(fp_Alarm->u32_HourMask)) return; + if (!IS_RTC_ALARM_MIN_MASK(fp_Alarm->u32_MinMask)) return; + + if (fp_Alarm->u32_AlarmMode == RTC_ALARM_WEEK_MODE) + { + if (!IS_RTC_ALARM_WEEKDAY(fp_Alarm->u32_AlarmWeek)) return; + } + else + { + if (!IS_RTC_DAY(fp_Alarm->u32_AlarmDay)) return; + } + + if (!IS_RTC_HOUR(fp_Alarm->u32_Hours)) return; + if (!IS_RTC_MIN(fp_Alarm->u32_Minutes)) return; + if (!IS_RTC_SEC(fp_Alarm->u32_Seconds)) return; +#endif + + if (fp_Alarm->u32_AlarmMode == RTC_ALARM_WEEK_MODE) + { + lu32_WeekDay = fp_Alarm->u32_AlarmWeek; + } + else + { + lu32_WeekDay = fp_Alarm->u32_AlarmDay; + } + + /* Coinfig Week/DayHourMinSec */ + RTC->ALM = fp_Alarm->u32_AlarmMode | lu32_WeekDay | fp_Alarm->u32_Hours << 16 | fp_Alarm->u32_Minutes << 8 | fp_Alarm->u32_Seconds; + + /* Interrupt Enable */ + if (RTC_ALARM_INT_ENABLE == fp_Alarm->u32_AlarmInterrupt) + { + RTC->IE |= RTC_IE_ALM; + } + + RTC->CR |= (fp_Alarm->u32_DayMask) ? RTC_ALARM_DAY_MASK_ENABLE : RTC_ALARM_DAY_MASK_DISABLE; + + RTC->CR |= (fp_Alarm->u32_HourMask) ? RTC_ALARM_HOUR_MASK_ENABLE : RTC_ALARM_HOUR_MASK_DISABLE; + + RTC->CR |= (fp_Alarm->u32_MinMask) ? RTC_ALARM_MIN_MASK_ENABLE : RTC_ALARM_MIN_MASK_DISABLE; +} + +/********************************************************************************* +* Function : HAL_RTC_AlarmEnable +* Description : Alarm Enable +* Input : +* Outpu : +* Author : Chris_Kyle Data : 2020 +**********************************************************************************/ +void HAL_RTC_AlarmEnable(void) +{ + RTC->CR |= RTC_CR_ALM_EN; +} + +/********************************************************************************* +* Function : HAL_RTC_AlarmDisable +* Description : Alarm Disable +* Input : +* Outpu : +* Author : Chris_Kyle Data : 2020 +**********************************************************************************/ +void HAL_RTC_AlarmDisable(void) +{ + RTC->CR &= ~RTC_CR_ALM_EN; +} + +/********************************************************************************* +* Function : HAL_RTC_Tamper +* Description : Temper1 use PC13Temper2 use PA0 +* Input : +* Outpu : +* Author : Chris_Kyle Data : 2020 +**********************************************************************************/ +void HAL_RTC_Tamper(enum_Temper_t fe_Temper, RTC_TemperTypeDef *fp_Temper) +{ +#if (USE_FULL_ASSERT == 1) + /* Check RTC Parameter */ + if (!IS_RTC_TEMP_EDGE(fp_Temper->u32_TemperEdge)) return; + if (!IS_RTC_TEMP_INT(fp_Temper->u32_InterruptEN)) return; + if (!IS_RTC_TEMP_CLEAR_BACKUP(fp_Temper->u32_ClearBackup)) return; + if (!IS_RTC_TEMP_FILTER(fp_Temper->u32_Filter)) return; +#endif + + switch (fe_Temper) + { + case RTC_TEMPER_1: + { + PMU->IOCR &= ~0x40; // Configure PC13 as digital IO + PMU->IOSEL |= 0x02; // Configure PC13 as tamper function + + /* Clear Config */ + RTC->CR &= ~(RTC_CR_TAMP1RCLR | RTC_CR_TAMP1FCLR | RTC_CR_TAMP1FLTEN | RTC_CR_TAMP1FLT | RTC_CR_TS1EDGE | RTC_CR_TAMPFLTCLK); + /* Edge select */ + RTC->CR |= fp_Temper->u32_TemperEdge ? RTC_CR_TS1EDGE : 0x00; + /* Auto clear backup register */ + if (fp_Temper->u32_ClearBackup) + { + RTC->CR |= fp_Temper->u32_TemperEdge ? RTC_CR_TAMP1FCLR : RTC_CR_TAMP1RCLR; + } + /* Temper filter */ + if (fp_Temper->u32_Filter) + { + if (fp_Temper->u32_Filter == RTC_TEMP_FILTER_512_RTCCLK) + { + RTC->CR |= RTC_CR_TAMPFLTCLK; + } + else + { + RTC->CR |= (fp_Temper->u32_Filter - 2) << 13; + } + } + + RTC->CR |= RTC_CR_TAMP1EN; + System_Delay(2000); + RTC->SR |= (RTC_SR_STP1FIE|RTC_SR_STP1RIE); + RTC->IE &= (~(RTC_IE_STP1FIE|RTC_IE_STP1RIE)); + + /* Put Temper Interrupt enable here !!!*/ + if (fp_Temper->u32_InterruptEN) + { + RTC->IE |= fp_Temper->u32_TemperEdge ? RTC_IE_STP1FIE : RTC_IE_STP1RIE; + } + + }break; + + case RTC_TEMPER_2: + { + /* Clear Config */ + RTC->CR &= ~(RTC_CR_TAMP2RCLR | RTC_CR_TAMP2FCLR | RTC_CR_TAMP2FLTEN | RTC_CR_TAMP2FLT | RTC_CR_TS2EDGE | RTC_CR_TAMPFLTCLK); + /* Edge select */ + RTC->CR |= fp_Temper->u32_TemperEdge ? RTC_CR_TS2EDGE : 0x00; + /* Auto clear backup register */ + if (fp_Temper->u32_ClearBackup) + { + RTC->CR |= fp_Temper->u32_TemperEdge ? RTC_CR_TAMP2FCLR : RTC_CR_TAMP2RCLR; + } + /* Temper filter */ + if (fp_Temper->u32_Filter) + { + if (fp_Temper->u32_Filter == RTC_TEMP_FILTER_512_RTCCLK) + { + RTC->CR |= RTC_CR_TAMPFLTCLK; + } + else + { + RTC->CR |= (fp_Temper->u32_Filter - 2) << 19; + } + } + + RTC->CR |= RTC_CR_TAMP2EN; + System_Delay(2000); + RTC->SR |= (RTC_SR_STP2FIE|RTC_SR_STP2RIE); + RTC->IE &= (~(RTC_IE_STP2FIE|RTC_IE_STP2RIE)); + + /* Temper Interrupt */ + if (fp_Temper->u32_InterruptEN) + { + RTC->IE |= fp_Temper->u32_TemperEdge ? RTC_IE_STP2FIE : RTC_IE_STP2RIE; + } + + }break; + + default: break; + } +} + +/********************************************************************************* +* Function : HAL_RTC_TamperEnable +* Description : +* Input : +* Outpu : +* Author : Chris_Kyle Data : 2020 +**********************************************************************************/ +void HAL_RTC_TamperEnable(enum_Temper_t fe_Temper) +{ + if (fe_Temper == RTC_TEMPER_1) + { + RTC->CR |= RTC_CR_TAMP1EN; + } + else + { + RTC->CR |= RTC_CR_TAMP2EN; + } +} + +/********************************************************************************* +* Function : HAL_RTC_TamperDisable +* Description : +* Input : +* Outpu : +* Author : Chris_Kyle Data : 2020 +**********************************************************************************/ +void HAL_RTC_TamperDisable(enum_Temper_t fe_Temper) +{ + if (fe_Temper == RTC_TEMPER_1) + { + RTC->CR &= ~RTC_CR_TAMP1EN; + } + else + { + RTC->CR &= ~RTC_CR_TAMP2EN; + } +} + +/*************************************************************************************************** +* Function : HAL_RTC_Standby_Wakeup +* Description : wakeup source select +* Input : fu32_Edge 0: Rising edge +* 1: Falling edge +* fe_Wakeup : wakeup source select, STANDBY_WAKEUP_RISING, STANDBY_WAKEUP_FALLING +* Outpu : +* Author : Chris_Kyle Data : 2020 +*******************************************************************************************************/ +void HAL_RTC_Standby_Wakeup(enum_WKUP_t fe_Wakeup, uint32_t fu32_Edge) +{ + switch (fe_Wakeup) + { + case RTC_WAKEUP_WKUP1: + case RTC_WAKEUP_WKUP2: + case RTC_WAKEUP_WKUP3: + case RTC_WAKEUP_WKUP4: + case RTC_WAKEUP_WKUP5: + case RTC_WAKEUP_WKUP6: + { + /* Clear flagsStandby Enable */ + PMU->CR1 |= RPMU_CR_STB_EN | RPMU_CR_CWUF | RPMU_CR_CSBF; + + /* Wakeup IO Filter Enable */ + PMU->CR1 |= fe_Wakeup << 8; + /* Wakeup IO Enable */ + PMU->CR1 |= fe_Wakeup; + + if (fe_Wakeup == RTC_WAKEUP_WKUP2) + { + /* PC13 */ + PMU->IOCR &= ~0x40; // must configure PC13 as digital function + } + + if (fu32_Edge) + { + PMU->CR2 |= fe_Wakeup >> 16; + } + else + { + PMU->CR2 &= ~(fe_Wakeup >> 16); + } + + PMU->CR1 |= RPMU_CR_CWUF; // clear wakeup flag + System_Enter_Standby_Mode(); + }break; + + case RTC_WAKEUP_STAMP2: + case RTC_WAKEUP_STAMP1: + case RTC_WAKEUP_32S: + case RTC_WAKEUP_SEC: + case RTC_WAKEUP_MIN: + case RTC_WAKEUP_HOUR: + case RTC_WAKEUP_DATE: + { + /* Clear flagsStandby Enable */ + PMU->CR1 |= RPMU_CR_STB_EN | RPMU_CR_CWUF | RPMU_CR_CSBF; + + RTC->SR |= fe_Wakeup; + RTC->IE |= fe_Wakeup; + + System_Enter_Standby_Mode(); + }break; + + default: break; + } +} + +/********************************************************************************* +* Function : HAL_RTC_GetStandbyStatus +* Description : Check MCU have entered standby mode +* Input : +* Outpu : 0: Not Enter Standby Mode + 1: Entered Standby Mode +* Author : Chris_Kyle Data : 2020 +**********************************************************************************/ +bool HAL_RTC_Get_StandbyStatus(void) +{ + if (PMU->SR & RPMU_SR_SBF) + { + return true; + } + else + { + return false; + } +} + +/********************************************************************************* +* Function : HAL_RTC_Get_StandbyWakeupSource +* Description : Get MCU Standby Wakeup Source +* Input : +* Outpu : RTC_WAKEUP_SOURCE_BORWUF + RTC_WAKEUP_SOURCE_IWDTWUF + RTC_WAKEUP_SOURCE_RSTWUF + RTC_WAKEUP_SOURCE_RTCWUF + RTC_WAKEUP_SOURCE_WKUP6 + RTC_WAKEUP_SOURCE_WKUP5 + RTC_WAKEUP_SOURCE_WKUP4 + RTC_WAKEUP_SOURCE_WKUP3 + RTC_WAKEUP_SOURCE_WKUP2 + RTC_WAKEUP_SOURCE_WKUP1 +* Author : Chris_Kyle Data : 2020 +**********************************************************************************/ +uint32_t HAL_RTC_Get_StandbyWakeupSource(void) +{ + return PMU->SR; +} diff --git a/bsp/acm32f4xx-nucleo/libraries/HAL_Driver/Src/HAL_SPI.c b/bsp/acm32f4xx-nucleo/libraries/HAL_Driver/Src/HAL_SPI.c new file mode 100644 index 0000000000..88e6f434c3 --- /dev/null +++ b/bsp/acm32f4xx-nucleo/libraries/HAL_Driver/Src/HAL_SPI.c @@ -0,0 +1,1080 @@ +/* + ****************************************************************************** + * @file HAL_Spi.c + * @version V1.0.0 + * @date 2020 + * @brief SPI HAL module driver. + * This file provides firmware functions to manage the following + * functionalities of the Serial Peripheral Interface (SPI) peripheral. + * @ Initialization and de-initialization functions + * @ IO operation functions + * @ Peripheral Control functions + ****************************************************************************** +*/ +#include "ACM32Fxx_HAL.h" + +#define SPI_RX_TIMEOUT 2000 +#define SPI_TX_DMA_TIMEOUT 2000 +volatile uint32_t lu32_ReceiveTimeOut = SPI_RX_TIMEOUT; +volatile uint32_t lu32_TX_DMA_TimeOut = SPI_TX_DMA_TIMEOUT; +/************************************************************************ + * function : HAL_SPI_IRQHandler + * Description: This function handles SPI interrupt request. + * input : hspi : pointer to a SPI_HandleTypeDef structure that contains + * the configuration information for SPI module + ************************************************************************/ +__weak void HAL_SPI_IRQHandler(SPI_HandleTypeDef *hspi) +{ + uint8_t lu8_TempValue = 0; + + uint32_t lu32_Length = 0; + + /* + NOTE : This function should be modified by the user. + */ + if ( (hspi->Instance->STATUS & SPI_STATUS_RX_NOT_EMPTY) && ((hspi->Instance->IE) & SPI_STATUS_RX_NOT_EMPTY) ) + { + /* In master mode */ + if (hspi->Instance->CTL & SPI_CTL_MST_MODE) + { + while (hspi->Instance->STATUS & SPI_STATUS_RX_NOT_EMPTY) + { + hspi->Rx_Buffer[hspi->Rx_Count++] = hspi->Instance->DAT; + + if (hspi->Rx_Count >= hspi->Rx_Size) + { + /* Wait Transmit Done */ + while (!(hspi->Instance->STATUS & SPI_STATUS_RX_BATCH_DONE)); + + /* Clear Batch Done Flag */ + SET_BIT(hspi->Instance->STATUS, SPI_STATUS_RX_BATCH_DONE); + SET_BIT(hspi->Instance->STATUS, SPI_STATUS_BATCH_DONE); + + /* Rx Disable */ + hspi->Instance->RX_CTL &= (~SPI_RX_CTL_EN); + + /* Receive End */ + hspi->Instance->CS &= (~SPI_CS_CS0); + + + /* Disable Rx Not Empty Interrupt */ + CLEAR_BIT(hspi->Instance->IE, SPI_STATUS_RX_NOT_EMPTY); + + if(hspi->Instance == SPI1) + NVIC_ClearPendingIRQ(SPI1_IRQn); + else if(hspi->Instance == SPI2) + NVIC_ClearPendingIRQ(SPI2_IRQn); + else if(hspi->Instance == SPI3) + NVIC_ClearPendingIRQ(SPI3_IRQn); + else if(hspi->Instance == SPI4) + NVIC_ClearPendingIRQ(SPI4_IRQn); + + /* Clear Batch Done Flag */ + SET_BIT(hspi->Instance->STATUS, SPI_STATUS_RX_BATCH_DONE); + SET_BIT(hspi->Instance->STATUS, SPI_STATUS_BATCH_DONE); + + /* Set machine is DILE */ + hspi->RxState = SPI_RX_STATE_IDLE; + } + } + } + /* In Slave mode */ + else + { + while ((hspi->Rx_Count < hspi->Rx_Size) && (lu32_ReceiveTimeOut > 0) ) + { + if (hspi->Instance->STATUS & SPI_STATUS_RX_NOT_EMPTY) + { + hspi->Rx_Buffer[hspi->Rx_Count++] = hspi->Instance->DAT; + lu32_ReceiveTimeOut = SPI_RX_TIMEOUT; //If recieve data, Reset the timeout value + } + else + { + lu32_ReceiveTimeOut--; + } + + } + + /* Rx Disable */ + hspi->Instance->RX_CTL &= (~SPI_RX_CTL_EN); + + /* Disable Rx Not Empty Interrupt */ + CLEAR_BIT(hspi->Instance->IE, SPI_STATUS_RX_NOT_EMPTY); + + if(hspi->Instance == SPI1) + NVIC_ClearPendingIRQ(SPI1_IRQn); + else if(hspi->Instance == SPI2) + NVIC_ClearPendingIRQ(SPI2_IRQn); + else if(hspi->Instance == SPI3) + NVIC_ClearPendingIRQ(SPI3_IRQn); + else if(hspi->Instance == SPI4) + NVIC_ClearPendingIRQ(SPI4_IRQn); + + /* Clear Batch Done Flag */ + SET_BIT(hspi->Instance->STATUS, SPI_STATUS_RX_BATCH_DONE); + SET_BIT(hspi->Instance->STATUS, SPI_STATUS_BATCH_DONE); + + /* Set machine is DILE */ + hspi->RxState = SPI_RX_STATE_IDLE; + } + } + + if ( (hspi->Instance->STATUS & SPI_STATUS_TX_FIFO_HALF_EMPTY) && ((hspi->Instance->IE) & SPI_IE_TX_FIFO_HALF_EMPTY_EN) ) + { + while (hspi->Tx_Count < hspi->Tx_Size) + { + if (!(hspi->Instance->STATUS & SPI_STATUS_TX_FIFO_FULL)) + { + hspi->Instance->DAT = hspi->Tx_Buffer[hspi->Tx_Count++]; + } + else + { + break; + } + + } + /* Clear Tx FIFO half empty Flag */ + SET_BIT(hspi->Instance->STATUS, SPI_STATUS_TX_FIFO_HALF_EMPTY); + if(hspi->Tx_Count == hspi->Tx_Size) + { + /* Disable Tx FIFO half empty Interrupt */ + CLEAR_BIT(hspi->Instance->IE, SPI_IE_TX_FIFO_HALF_EMPTY_EN); + } + } + if ((hspi->Instance->STATUS & SPI_STATUS_TX_BATCH_DONE) && ((hspi->Instance->IE) & SPI_IE_TX_BATCH_DONE_EN) ) + { + /* Clear Batch Done Flag */ + SET_BIT(hspi->Instance->STATUS, SPI_STATUS_TX_BATCH_DONE); + SET_BIT(hspi->Instance->STATUS, SPI_STATUS_BATCH_DONE); + + /* Disable TX Batch Done Interrupt */ + CLEAR_BIT(hspi->Instance->IE, SPI_STATUS_TX_BATCH_DONE); + /* Disable Tx FIFO half empty Interrupt */ + CLEAR_BIT(hspi->Instance->IE, SPI_IE_TX_FIFO_HALF_EMPTY_EN); + + if(hspi->Instance == SPI1) + NVIC_ClearPendingIRQ(SPI1_IRQn); + else if(hspi->Instance == SPI2) + NVIC_ClearPendingIRQ(SPI2_IRQn); + else if(hspi->Instance == SPI3) + NVIC_ClearPendingIRQ(SPI3_IRQn); + else if(hspi->Instance == SPI4) + NVIC_ClearPendingIRQ(SPI4_IRQn); + + lu32_TX_DMA_TimeOut = SPI_TX_DMA_TIMEOUT; + while (hspi->Instance->STATUS & SPI_STATUS_TX_BUSY) + { + lu32_TX_DMA_TimeOut--; + if(0 == lu32_TX_DMA_TimeOut) + { + break; + } + } + + /* Tx Disable */ + hspi->Instance->TX_CTL &= (~SPI_TX_CTL_EN); + hspi->Instance->TX_CTL &= (~SPI_TX_CTL_DMA_REQ_EN); + + if (hspi->Init.SPI_Mode == SPI_MODE_MASTER) + { + /* Transmit End */ + hspi->Instance->CS &= (~SPI_CS_CS0); + } + + /* Tx Disable */ + hspi->Instance->TX_CTL &= (~SPI_TX_CTL_EN); + + hspi->TxState = SPI_TX_STATE_IDLE; + } + + if ( (hspi->Instance->STATUS & SPI_STATUS_RX_BATCH_DONE) && ((hspi->Instance->IE) & SPI_STATUS_RX_BATCH_DONE) ) + { + /* Clear Batch Done Flag */ + SET_BIT(hspi->Instance->STATUS, SPI_STATUS_RX_BATCH_DONE); + SET_BIT(hspi->Instance->STATUS, SPI_STATUS_BATCH_DONE); + + /* Disable RX Batch Done Interrupt */ + CLEAR_BIT(hspi->Instance->IE, SPI_STATUS_RX_BATCH_DONE); + + if(hspi->Instance == SPI1) + NVIC_ClearPendingIRQ(SPI1_IRQn); + else if(hspi->Instance == SPI2) + NVIC_ClearPendingIRQ(SPI2_IRQn); + else if(hspi->Instance == SPI3) + NVIC_ClearPendingIRQ(SPI3_IRQn); + else if(hspi->Instance == SPI4) + NVIC_ClearPendingIRQ(SPI4_IRQn); + + /* Rx Disable */ + hspi->Instance->RX_CTL &= (~SPI_RX_CTL_DMA_REQ_EN); + hspi->Instance->RX_CTL &= (~SPI_RX_CTL_EN); + + if (hspi->Init.SPI_Mode == SPI_MODE_MASTER) + { + /* Receive End */ + hspi->Instance->CS &= (~SPI_CS_CS0); + } + + hspi->RxState = SPI_RX_STATE_IDLE; + } +} + +/************************************************************************ + * function : HAL_SPI_MspInit + * Description: + * input : hspi : pointer to a SPI_HandleTypeDef structure that contains + * the configuration information for SPI module + ************************************************************************/ +__weak void HAL_SPI_MspInit(SPI_HandleTypeDef *hspi) +{ + /* + NOTE : This function should be modified by the user. + */ + + /* For Example */ + GPIO_InitTypeDef GPIO_Handle; + + /* SPI1 */ + if (hspi->Instance == SPI1) + { + } + /* SPI2 */ + else if (hspi->Instance == SPI2) + { + } + /* SPI3 */ + else if (hspi->Instance == SPI3) + { + /* Enable Clock */ + System_Module_Enable(EN_SPI3); + + /* SPI3 CS PortA Pin15 */ + /* SPI3 CLK PortC Pin10 */ + /* SPI3 MOSI PortC Pin12 */ + /* SPI3 MISO PortC Pin11 */ + GPIO_Handle.Pin = GPIO_PIN_10 | GPIO_PIN_11 | GPIO_PIN_12; + GPIO_Handle.Mode = GPIO_MODE_AF_PP; + GPIO_Handle.Pull = GPIO_PULLUP; + GPIO_Handle.Alternate = GPIO_FUNCTION_3; + HAL_GPIO_Init(GPIOC, &GPIO_Handle); + + GPIO_Handle.Pin = GPIO_PIN_15; + GPIO_Handle.Mode = GPIO_MODE_AF_PP; + GPIO_Handle.Pull = GPIO_PULLUP; + GPIO_Handle.Alternate = GPIO_FUNCTION_5; + HAL_GPIO_Init(GPIOA, &GPIO_Handle); + + if (hspi->Init.X_Mode == SPI_4X_MODE) + { + /* SPI3 IO3 PortC Pin8 */ + /* SPI3 IO2 PortC Pin9 */ + GPIO_Handle.Pin = GPIO_PIN_8 | GPIO_PIN_9; + GPIO_Handle.Mode = GPIO_MODE_AF_PP; + GPIO_Handle.Pull = GPIO_PULLUP; + GPIO_Handle.Alternate = GPIO_FUNCTION_3; + HAL_GPIO_Init(GPIOC, &GPIO_Handle); + } + + /* Clear Pending Interrupt */ + NVIC_ClearPendingIRQ(SPI3_IRQn); + + /* Enable External Interrupt */ + NVIC_EnableIRQ(SPI3_IRQn); + } +} + +/************************************************************************ + * function : HAL_SPI_MspDeInit + * Description: SPI De-Initialize the SPI clock, GPIO, IRQ. + * input : hspi : pointer to a SPI_HandleTypeDef structure that contains + * the configuration information for SPI module + ************************************************************************/ +__weak void HAL_SPI_MspDeInit(SPI_HandleTypeDef *hspi) +{ + /* + NOTE : This function should be modified by the user. + */ + + /* For Example */ + + /* SPI1 */ + if (hspi->Instance == SPI1) + { + } + /* SPI2 */ + else if (hspi->Instance == SPI2) + { + } + /* SPI3 */ + else if (hspi->Instance == SPI3) + { + /* Disable Clock */ + System_Module_Disable(EN_SPI3); + + /* Reset the used GPIO to analog */ + HAL_GPIO_DeInit(GPIOC, GPIO_PIN_10 | GPIO_PIN_11 | GPIO_PIN_12); + HAL_GPIO_DeInit(GPIOA, GPIO_PIN_15); + + if (hspi->Init.X_Mode == SPI_4X_MODE) + { + HAL_GPIO_DeInit(GPIOA, GPIO_PIN_8 | GPIO_PIN_9); + } + + /* Clear Pending Interrupt */ + NVIC_ClearPendingIRQ(SPI3_IRQn); + + /* Disable External Interrupt */ + NVIC_DisableIRQ(SPI3_IRQn); + } +} + +/************************************************************************ + * function : HAL_SPI_Init + * Description: SPI initial with parameters. + * input : hspi : pointer to a SPI_HandleTypeDef structure that contains + * the configuration information for SPI module + ************************************************************************/ +HAL_StatusTypeDef HAL_SPI_Init(SPI_HandleTypeDef *hspi) +{ + /* Check SPI Parameter */ + if (!IS_SPI_ALL_INSTANCE(hspi->Instance)) return HAL_ERROR; + if (!IS_SPI_ALL_MODE(hspi->Init.SPI_Mode)) return HAL_ERROR; + if (!IS_SPI_WORK_MODE(hspi->Init.SPI_Work_Mode)) return HAL_ERROR; + if (!IS_SPI_X_MODE(hspi->Init.X_Mode)) return HAL_ERROR; + if (!IS_SPI_FIRST_BIT(hspi->Init.First_Bit)) return HAL_ERROR; + if (!IS_SPI_BAUDRATE_PRESCALER(hspi->Init.BaudRate_Prescaler)) return HAL_ERROR; + + /* Init the low level hardware : GPIO, CLOCK, NVIC */ + HAL_SPI_MspInit(hspi); + + /* Automatic change direction */ + hspi->Instance->CTL |= (SPI_CTL_IO_MODE); + + /* Set SPI Work mode */ + if (hspi->Init.SPI_Mode == SPI_MODE_MASTER) + { + SET_BIT(hspi->Instance->CTL, SPI_CTL_MST_MODE); + } + else + { + CLEAR_BIT(hspi->Instance->CTL, SPI_CTL_MST_MODE); + + hspi->Instance->BATCH = (hspi->Instance->BATCH & (~0x000FFFFFU)) | (1 << 0); + + hspi->Instance->TX_CTL |= SPI_TX_CTL_MODE | (0x88 << 8); // dummy data = 0x88 + + if (hspi->Init.X_Mode != SPI_1X_MODE) + { + hspi->Instance->CTL |= SPI_CTL_SFILTER; + } + + /* Slave Alternate Enable */ + hspi->Instance->CTL |= SPI_CTL_SLAVE_EN; + + /* Slave Mode Enable Rx By Default */ + hspi->Instance->RX_CTL |= SPI_RX_CTL_EN; + } + + /* Set SPI First Bit */ + if (hspi->Init.First_Bit == SPI_FIRSTBIT_LSB) + SET_BIT(hspi->Instance->CTL, SPI_CTL_LSB_FIRST); + else + CLEAR_BIT(hspi->Instance->CTL, SPI_CTL_LSB_FIRST); + + /* Set SPI Work Mode */ + hspi->Instance->CTL = ((hspi->Instance->CTL) & (~(SPI_CTL_CPHA | SPI_CTL_CPOL))) | (hspi->Init.SPI_Work_Mode); + + /* Set SPI X_Mode */ + hspi->Instance->CTL = ((hspi->Instance->CTL) & (~SPI_CTL_X_MODE)) | (hspi->Init.X_Mode); + + /* Set SPI BaudRate Prescaler */ + hspi->Instance->BAUD = ((hspi->Instance->BAUD) & (~0x0000FFFF)) | (hspi->Init.BaudRate_Prescaler); + + /* Disable All Interrupt */ + hspi->Instance->IE = 0x00000000; + + return HAL_OK; +} + +/************************************************************************ + * function : HAL_SPI_DeInit + * Description: De-Initialize the SPI peripheral. + * input : hspi : pointer to a SPI_HandleTypeDef structure that contains + * the configuration information for SPI module + * return : HAL_StatusTypeDef : HAL status + ************************************************************************/ +HAL_StatusTypeDef HAL_SPI_DeInit(SPI_HandleTypeDef *hspi) +{ + /* Check the SPI handle allocation */ + if (hspi == NULL) + { + return HAL_ERROR; + } + + /* Check SPI Instance parameter */ + if (!IS_SPI_ALL_INSTANCE(hspi->Instance)) return HAL_ERROR; + + hspi->RxState = SPI_RX_STATE_IDLE; + hspi->TxState = SPI_TX_STATE_IDLE; + + /* DeInit the low level hardware: GPIO, CLOCK, NVIC... */ + HAL_SPI_MspDeInit(hspi); + + hspi->Rx_Size = 0; + hspi->Tx_Size = 0; + hspi->Rx_Count = 0; + hspi->Tx_Count = 0; + + return HAL_OK; +} + +/************************************************************************ + * function : HAL_SPI_Transmit + * Description: Transmits an amount of data in blocking mode. + * input : hspi : pointer to a SPI_HandleTypeDef structure that contains + * the configuration information for SPI module + * pData : Pointer to data buffer + * Size : Amount of data to be sent + * Timeout : Transmit Timeout + ************************************************************************/ +HAL_StatusTypeDef HAL_SPI_Transmit(SPI_HandleTypeDef *hspi, uint8_t *pData, uint32_t Size, uint32_t Timeout) +{ + uint32_t i; + HAL_StatusTypeDef Status = HAL_OK; + __IO uint32_t uiTimeout; + + /* Check SPI Parameter */ + if (!IS_SPI_ALL_INSTANCE(hspi->Instance)) return HAL_ERROR; + if(!Size) return HAL_ERROR; + if (pData == NULL) return HAL_ERROR; + + hspi->Tx_Count = 0; + hspi->Tx_Size = Size; + hspi->Tx_Buffer = pData; + + uiTimeout = Timeout; + + /* Clear Batch Done Flag */ + SET_BIT(hspi->Instance->STATUS, SPI_STATUS_TX_BATCH_DONE); + SET_BIT(hspi->Instance->STATUS, SPI_STATUS_BATCH_DONE); + + /* Clear TX FIFO */ + SET_BIT(hspi->Instance->TX_CTL, SPI_TX_CTL_FIFO_RESET); + CLEAR_BIT(hspi->Instance->TX_CTL, SPI_TX_CTL_FIFO_RESET); + + /* Set Data Size */ + hspi->Instance->BATCH = Size; + + /* Tx Enable */ + hspi->Instance->TX_CTL |= SPI_TX_CTL_EN; + + if (hspi->Init.SPI_Mode == SPI_MODE_MASTER) + { + /* Transmit Start */ + hspi->Instance->CS |= SPI_CS_CS0; + } + else + { + /* Rx Disable */ + hspi->Instance->RX_CTL &= (~SPI_RX_CTL_EN); + } + + while(hspi->Tx_Size > 0) + { + /* Wait Tx FIFO Not Full */ + while (hspi->Instance->STATUS & SPI_STATUS_TX_FIFO_FULL) + { + if(uiTimeout) + { + uiTimeout--; + if (uiTimeout == 0) + { + Status = HAL_TIMEOUT; + goto End; + } + } + } + hspi->Instance->DAT = hspi->Tx_Buffer[hspi->Tx_Count++]; + hspi->Tx_Size--; + uiTimeout = Timeout; + } + + if (hspi->Init.SPI_Mode == SPI_MODE_SLAVE) + { + /* Wait Transmit Done */ + while (!(hspi->Instance->STATUS & SPI_STATUS_TX_BUSY)); + while (hspi->Instance->STATUS & SPI_STATUS_TX_BUSY) + { + if(uiTimeout) + { + uiTimeout--; + if (uiTimeout == 0) + { + Status = HAL_TIMEOUT; + goto End; + } + } + } + } + else + { + /* Wait Transmit Done */ + while (!(hspi->Instance->STATUS & SPI_STATUS_TX_BATCH_DONE)); + Status = HAL_OK; + } + +End: + /* Clear Batch Done Flag */ + SET_BIT(hspi->Instance->STATUS, SPI_STATUS_TX_BATCH_DONE); + SET_BIT(hspi->Instance->STATUS, SPI_STATUS_BATCH_DONE); + + /* Tx Disable */ + hspi->Instance->TX_CTL &= (~SPI_TX_CTL_EN); + + if (hspi->Init.SPI_Mode == SPI_MODE_MASTER) + { + /* Transmit End */ + hspi->Instance->CS &= (~SPI_CS_CS0); + } + + return Status; +} + +/************************************************************************ + * function : HAL_SPI_Transmit_DMA + * Description: Transmits an amount of data in blocking mode with DMA. + * input : hspi : pointer to a SPI_HandleTypeDef structure that contains + * the configuration information for SPI module + * pData : Pointer to data buffer + * Size : Amount of data to be sent + ************************************************************************/ +HAL_StatusTypeDef HAL_SPI_Transmit_DMA(SPI_HandleTypeDef *hspi, uint8_t *pData, uint32_t Size) +{ + /* Check SPI Parameter */ + if (!IS_SPI_ALL_INSTANCE(hspi->Instance)) return HAL_ERROR; + + /* Rx machine is running */ + if (hspi->TxState != SPI_TX_STATE_IDLE) + { + return HAL_ERROR; + } + /* Set machine is Sending */ + hspi->TxState = SPI_TX_STATE_SENDING; + + + /* Clear Batch Done Flag */ + SET_BIT(hspi->Instance->STATUS, SPI_STATUS_TX_BATCH_DONE); + SET_BIT(hspi->Instance->STATUS, SPI_STATUS_BATCH_DONE); + + /* Enable Tx Batch Done Interrupt */ + SET_BIT(hspi->Instance->IE, SPI_STATUS_TX_BATCH_DONE); + + /* Set Data Size */ + hspi->Instance->BATCH = Size; + + /* Tx FIFO */ + hspi->Instance->TX_CTL &= ~SPI_TX_CTL_DMA_LEVEL; + hspi->Instance->TX_CTL |= SPI_TX_CTL_DMA_LEVEL_0; + + /* Tx Enable */ + hspi->Instance->TX_CTL |= SPI_TX_CTL_EN; + + if (hspi->Init.SPI_Mode == SPI_MODE_MASTER) + { + /* Transmit Start */ + hspi->Instance->CS |= SPI_CS_CS0; + } + else + { + /* Rx Disable */ + hspi->Instance->RX_CTL &= (~SPI_RX_CTL_EN); + } + + HAL_DMA_Start(hspi->HDMA_Tx, (uint32_t)pData, (uint32_t)&hspi->Instance->DAT, Size); + + hspi->Instance->TX_CTL |= SPI_TX_CTL_DMA_REQ_EN; + return HAL_OK; +} + +/************************************************************************ + * function : HAL_SPI_Receive + * Description: Receive an amount of data in blocking mode. + * input : hspi : pointer to a SPI_HandleTypeDef structure that contains + * the configuration information for SPI module + * pData : Pointer to data buffer + * Size : Amount of data to be Receive + * Timeout : Receive Timeout + ************************************************************************/ +HAL_StatusTypeDef HAL_SPI_Receive(SPI_HandleTypeDef *hspi, uint8_t *pData, uint32_t Size, uint32_t Timeout) +{ + uint32_t i; + HAL_StatusTypeDef Status = HAL_OK; + __IO uint32_t uiTimeout; + + /* Check SPI Parameter */ + if (!IS_SPI_ALL_INSTANCE(hspi->Instance)) return HAL_ERROR; + if (pData == NULL) return HAL_ERROR; + + hspi->Rx_Count = 0; + hspi->Rx_Size = Size; + hspi->Rx_Buffer = pData; + uiTimeout = Timeout; + + if (hspi->Init.SPI_Mode == SPI_MODE_SLAVE) + { + hspi->Instance->BATCH = 1; + /* Rx Enable */ + hspi->Instance->RX_CTL |= SPI_RX_CTL_EN; + + while ( hspi->Rx_Size > 0) + { + while (READ_BIT(hspi->Instance->STATUS, SPI_STATUS_RX_FIFO_EMPTY)) + { + if(uiTimeout) + { + uiTimeout--; + if (uiTimeout == 0) + { + /* Rx Disable */ + hspi->Instance->RX_CTL &= (~SPI_RX_CTL_EN); + return HAL_TIMEOUT; + } + } + } + + hspi->Rx_Buffer[hspi->Rx_Count++] = hspi->Instance->DAT; + hspi->Rx_Size--; + uiTimeout = Timeout; + } + + /* Rx Disable */ + hspi->Instance->RX_CTL &= (~SPI_RX_CTL_EN); + + return HAL_OK; + } + + /* Clear Batch Done Flag */ + SET_BIT(hspi->Instance->STATUS, SPI_STATUS_RX_BATCH_DONE); + SET_BIT(hspi->Instance->STATUS, SPI_STATUS_BATCH_DONE); + + /* Set Data Size */ + hspi->Instance->BATCH = Size; + + /* Rx Enable */ + hspi->Instance->RX_CTL |= SPI_RX_CTL_EN; + + /* Receive Start */ + hspi->Instance->CS |= SPI_CS_CS0; + + while(hspi->Rx_Size > 0) + { + /* have no timeout */ + if (uiTimeout == 0) + { + /* Wait Rx FIFO Not Empty */ + while (hspi->Instance->STATUS & SPI_STATUS_RX_FIFO_EMPTY); + } + else + { + while (hspi->Instance->STATUS & SPI_STATUS_RX_FIFO_EMPTY) + { + if (uiTimeout-- == 0) + { + Status = HAL_TIMEOUT; + goto End; + } + } + } + + hspi->Rx_Buffer[hspi->Rx_Count++] = hspi->Instance->DAT; + hspi->Rx_Size--; + } + + Status = HAL_OK; + + /* Wait Transmit Done */ + while (!(hspi->Instance->STATUS & SPI_STATUS_RX_BATCH_DONE)); + +End: + /* Clear Batch Done Flag */ + SET_BIT(hspi->Instance->STATUS, SPI_STATUS_RX_BATCH_DONE); + SET_BIT(hspi->Instance->STATUS, SPI_STATUS_BATCH_DONE); + + /* Rx Disable */ + hspi->Instance->RX_CTL &= (~SPI_RX_CTL_EN); + + /* Receive End */ + hspi->Instance->CS &= (~SPI_CS_CS0); + + return Status; +} + +/************************************************************************ + * function : HAL_SPI_Receive_DMA + * Description: Receive an amount of data in blocking mode with DMA. + * input : hspi : pointer to a SPI_HandleTypeDef structure that contains + * the configuration information for SPI module + * pData : Pointer to data buffer + * Size : Amount of data to be Receive + ************************************************************************/ +HAL_StatusTypeDef HAL_SPI_Receive_DMA(SPI_HandleTypeDef *hspi, uint8_t *pData, uint32_t Size) +{ + /* Check SPI Parameter */ + if (!IS_SPI_ALL_INSTANCE(hspi->Instance)) return HAL_ERROR; + + /* Rx machine is running */ + if (hspi->RxState != SPI_RX_STATE_IDLE) + { + return HAL_ERROR; + } + /* Set Slave machine is receiving */ + hspi->RxState = SPI_RX_STATE_RECEIVING; + + + /* Clear Batch Done Flag */ + SET_BIT(hspi->Instance->STATUS, SPI_STATUS_RX_BATCH_DONE); + SET_BIT(hspi->Instance->STATUS, SPI_STATUS_BATCH_DONE); + + /* Enable Rx Batch Done Interrupt */ + SET_BIT(hspi->Instance->IE, SPI_STATUS_RX_BATCH_DONE); + + /* Set Data Size */ + hspi->Instance->BATCH = Size; + + /* Rx Enable */ + hspi->Instance->RX_CTL |= SPI_RX_CTL_EN; + /* Rx FIFO */ + hspi->Instance->RX_CTL |= SPI_RX_CTL_DMA_LEVEL_0; + + if (hspi->Init.SPI_Mode == SPI_MODE_MASTER) + { + /* Receive Start */ + hspi->Instance->CS |= SPI_CS_CS0; + } + + HAL_DMA_Start(hspi->HDMA_Rx, (uint32_t)&hspi->Instance->DAT, (uint32_t)pData, Size); + + hspi->Instance->RX_CTL |= SPI_RX_CTL_DMA_REQ_EN; + + return HAL_OK; +} + +/************************************************************************ + * function : HAL_SPI_Wire_Config + * Description: SPI Wire Config + * input : hspi : pointer to a SPI_HandleTypeDef structure that contains + * the configuration information for SPI module + * Mode : This parameter can be a value of @ref X_MODE + ************************************************************************/ +HAL_StatusTypeDef HAL_SPI_Wire_Config(SPI_HandleTypeDef *hspi, uint32_t X_Mode) +{ + /* Check SPI Parameter */ + if (!IS_SPI_ALL_INSTANCE(hspi->Instance)) return HAL_ERROR; + + /* Set SPI X_Mode */ + hspi->Instance->CTL = ((hspi->Instance->CTL) & (~SPI_CTL_X_MODE)) | X_Mode; + + return HAL_OK; +} +/************************************************************************ + * function : HAL_SPI_Transmit_IT + * Description: Transmit an amount of data in blocking mode with interrupt. + * input : hspi : pointer to a SPI_HandleTypeDef structure that contains + * the configuration information for SPI module + * pData : Pointer to data buffer + ************************************************************************/ +HAL_StatusTypeDef HAL_SPI_Transmit_IT(SPI_HandleTypeDef *hspi, uint8_t *pData, uint32_t Size) +{ + /* Check SPI Parameter */ + if (!IS_SPI_ALL_INSTANCE(hspi->Instance)) return HAL_ERROR; + + /* Tx machine is running */ + if (hspi->TxState != SPI_TX_STATE_IDLE) + { + return HAL_ERROR; + } + + hspi->Tx_Size = Size; + hspi->Tx_Buffer = pData; + hspi->Tx_Count = 0; + + /* Set machine is Sending */ + hspi->TxState = SPI_TX_STATE_SENDING; + + /* Clear TX FIFO */ + SET_BIT(hspi->Instance->TX_CTL, SPI_TX_CTL_FIFO_RESET); + CLEAR_BIT(hspi->Instance->TX_CTL, SPI_TX_CTL_FIFO_RESET); + + /* Clear Batch Done Flag */ + SET_BIT(hspi->Instance->STATUS, SPI_STATUS_TX_BATCH_DONE); + SET_BIT(hspi->Instance->STATUS, SPI_STATUS_BATCH_DONE); + + /* Set Data Size */ + hspi->Instance->BATCH = Size; + + /* Tx Enable */ + hspi->Instance->TX_CTL |= SPI_TX_CTL_EN; + + if (hspi->Init.SPI_Mode == SPI_MODE_MASTER) + { + /* Transmit Start */ + hspi->Instance->CS |= SPI_CS_CS0; + } + else + { + /* Rx Disable */ + hspi->Instance->RX_CTL &= (~SPI_RX_CTL_EN); + } + + while (hspi->Tx_Count < hspi->Tx_Size) + { + if (!(hspi->Instance->STATUS & SPI_STATUS_TX_FIFO_FULL)) + hspi->Instance->DAT = hspi->Tx_Buffer[hspi->Tx_Count++]; + else + break; + } + /* Clear Tx FIFO half empty Flag */ + SET_BIT(hspi->Instance->STATUS, SPI_STATUS_TX_FIFO_HALF_EMPTY); + + + /* Enable Tx FIFO half empty Interrupt and Tx batch done Interrupt*/ + SET_BIT(hspi->Instance->IE, (SPI_IE_TX_FIFO_HALF_EMPTY_EN | SPI_IE_TX_BATCH_DONE_EN)); + + + return HAL_OK; +} + +/************************************************************************ + * function : HAL_SPI_Receive_IT + * Description: Receive an amount of data in blocking mode with interrupt. + * input : hspi : pointer to a SPI_HandleTypeDef structure that contains + * the configuration information for SPI module + * pData : Pointer to data buffer + ************************************************************************/ +HAL_StatusTypeDef HAL_SPI_Receive_IT(SPI_HandleTypeDef *hspi, uint8_t *pData, uint32_t Size) +{ + /* Check SPI Parameter */ + if (!IS_SPI_ALL_INSTANCE(hspi->Instance)) return HAL_ERROR; + + /* Rx machine is running */ + if (hspi->RxState != SPI_RX_STATE_IDLE) + { + return HAL_ERROR; + } + + /* Set Slave machine is receiving */ + hspi->RxState = SPI_RX_STATE_RECEIVING; + + if (hspi->Init.SPI_Mode == SPI_MODE_MASTER) + { + /* Clear Batch Done Flag */ + SET_BIT(hspi->Instance->STATUS, SPI_STATUS_RX_BATCH_DONE); + SET_BIT(hspi->Instance->STATUS, SPI_STATUS_BATCH_DONE); + + /* Set Data Size */ + hspi->Instance->BATCH = Size; + + /* Rx Enable */ + hspi->Instance->RX_CTL |= SPI_RX_CTL_EN; + + /* Receive Start */ + hspi->Instance->CS |= SPI_CS_CS0; + } + else + { + /* Reset BATCH register */ + hspi->Instance->BATCH = 1; + hspi->Instance->RX_CTL |= SPI_RX_CTL_EN; + } + + hspi->Rx_Size = Size; + hspi->Rx_Buffer = pData; + hspi->Rx_Count = 0; + lu32_ReceiveTimeOut = SPI_RX_TIMEOUT; + + /* Enable Rx FIFO Not Empty Interrupt */ + SET_BIT(hspi->Instance->IE, SPI_STATUS_RX_NOT_EMPTY); + + return HAL_OK; +} + +/************************************************************************ + * function : HAL_SPI_TransmitReceive + * Description: Transmits and recieve an amount of data in blocking mode. + * input : hspi : pointer to a SPI_HandleTypeDef structure that contains + * the configuration information for SPI module + * pTxData : Pointer to transmit data buffer + * pRxData : Pointer to recieve data buffer + * Size : Amount of data to be sent + * Timeout : TransmitReceive Timeout + ************************************************************************/ +HAL_StatusTypeDef HAL_SPI_TransmitReceive(SPI_HandleTypeDef *hspi, uint8_t *pTxData, uint8_t *pRxData, uint32_t Size, uint32_t Timeout) +{ + uint32_t i; + __IO uint32_t TxFlag = 1U, uiTimeout; + HAL_StatusTypeDef Status = HAL_OK; + + /* Check SPI Parameter */ + if (!IS_SPI_ALL_INSTANCE(hspi->Instance)) return HAL_ERROR; + if ((pTxData == NULL)||(pRxData == NULL)) return HAL_ERROR; + + hspi->Tx_Count = 0; + hspi->Rx_Count = 0; + hspi->Tx_Buffer = pTxData; + hspi->Rx_Buffer = pRxData; + hspi->Tx_Size = Size; + hspi->Rx_Size = Size; + uiTimeout = Timeout; + + /* Clear Batch Done Flag */ + SET_BIT(hspi->Instance->STATUS, SPI_STATUS_TX_BATCH_DONE); + SET_BIT(hspi->Instance->STATUS, SPI_STATUS_BATCH_DONE); + + /* Tx Enable */ + hspi->Instance->TX_CTL |= SPI_TX_CTL_EN; + + /* Rx Enable */ + hspi->Instance->RX_CTL |= SPI_RX_CTL_EN; + + /* Clear TX FIFO */ + SET_BIT(hspi->Instance->TX_CTL, SPI_TX_CTL_FIFO_RESET); + CLEAR_BIT(hspi->Instance->TX_CTL, SPI_TX_CTL_FIFO_RESET); + + + if (hspi->Init.SPI_Mode == SPI_MODE_SLAVE) + { + hspi->Instance->DAT = hspi->Tx_Buffer[hspi->Tx_Count++]; + hspi->Tx_Size--; + TxFlag = 0; + } + else + { + /* Set Data Size */ + hspi->Instance->BATCH = hspi->Tx_Size; + + /* Transmit Start */ + hspi->Instance->CS |= SPI_CS_CS0; + TxFlag = 1; + } + + while((hspi->Tx_Size>0) || (hspi->Rx_Size>0)) + { + if (hspi->Init.SPI_Mode == SPI_MODE_SLAVE) + { + /* Wait Rx FIFO Not Empty */ + if((!(hspi->Instance->STATUS & SPI_STATUS_RX_FIFO_EMPTY)) && (hspi->Rx_Size>0)) + { + hspi->Rx_Buffer[hspi->Rx_Count++] = hspi->Instance->DAT; + hspi->Rx_Size--; + TxFlag = 1U; + } + /* Wait Tx FIFO Not Full */ + if((!(hspi->Instance->STATUS & SPI_STATUS_TX_FIFO_FULL)) && (hspi->Tx_Size>0) && (TxFlag == 1U)) + { + hspi->Instance->DAT = hspi->Tx_Buffer[hspi->Tx_Count++]; + hspi->Tx_Size--; + TxFlag = 0; + } + } + else + { + /* Wait Tx FIFO Not Full */ + if((!(hspi->Instance->STATUS & SPI_STATUS_TX_FIFO_FULL)) && (hspi->Tx_Size>0) && (TxFlag == 1U)) + { + hspi->Instance->DAT = hspi->Tx_Buffer[hspi->Tx_Count++]; + hspi->Tx_Size--; + TxFlag = 0; + } + + /* Wait Rx FIFO Not Empty */ + if((!(hspi->Instance->STATUS & SPI_STATUS_RX_FIFO_EMPTY)) && (hspi->Rx_Size>0)) + { + hspi->Rx_Buffer[hspi->Rx_Count++] = hspi->Instance->DAT; + hspi->Rx_Size--; + TxFlag = 1U; + } + } + + /* Wait Timeout */ + if(uiTimeout) + { + uiTimeout--; + if(uiTimeout == 0) + { + Status = HAL_TIMEOUT; + goto End; + } + } + } + /* Wait Transmit Done */ + while (!(hspi->Instance->STATUS & SPI_STATUS_TX_BATCH_DONE)); + + Status = HAL_OK; + +End: + /* Clear Batch Done Flag */ + SET_BIT(hspi->Instance->STATUS, SPI_STATUS_TX_BATCH_DONE); + SET_BIT(hspi->Instance->STATUS, SPI_STATUS_BATCH_DONE); + + /* Tx Disable */ + hspi->Instance->TX_CTL &= (~SPI_TX_CTL_EN); + + /* Rx Disable */ + hspi->Instance->RX_CTL &= (~SPI_RX_CTL_EN); + + if (hspi->Init.SPI_Mode == SPI_MODE_MASTER) + { + /* Transmit End */ + hspi->Instance->CS &= (~SPI_CS_CS0); + } + + return Status; +} + +/************************************************************************ + * function : HAL_SPI_GetTxState + * Description: Get Tx state. + * input : hspi : pointer to a SPI_HandleTypeDef structure that contains + * the configuration information for SPI module + ************************************************************************/ +uint8_t HAL_SPI_GetTxState(SPI_HandleTypeDef *hspi) +{ + return hspi->TxState; +} + +/************************************************************************ + * function : HAL_SPI_GetRxState + * Description: Get Rx state. + * input : hspi : pointer to a SPI_HandleTypeDef structure that contains + * the configuration information for SPI module + ************************************************************************/ +uint8_t HAL_SPI_GetRxState(SPI_HandleTypeDef *hspi) +{ + return hspi->RxState; +} + + + + + + + + + + + + + + + + + + + + + + + + + + diff --git a/bsp/acm32f4xx-nucleo/libraries/HAL_Driver/Src/HAL_TIMER.c b/bsp/acm32f4xx-nucleo/libraries/HAL_Driver/Src/HAL_TIMER.c new file mode 100644 index 0000000000..681ab5b136 --- /dev/null +++ b/bsp/acm32f4xx-nucleo/libraries/HAL_Driver/Src/HAL_TIMER.c @@ -0,0 +1,1553 @@ +/*********************************************************************** + * Filename : hal_lpuart.c + * Description : lpuart driver source file + * Author(s) : xwl + * version : V1.0 + * Modify date : 2019-11-19 + ***********************************************************************/ +#include "ACM32Fxx_HAL.h" + +static void TIMER_ETR_SetConfig(TIM_TypeDef* TIMx, uint32_t TIM_ExtTRGPrescaler, + uint32_t TIM_ExtTRGPolarity, uint32_t ExtTRGFilter); +static void TIMER_TI1FP1_ConfigInputStage(TIM_TypeDef *TIMx, uint32_t TIM_ICPolarity, uint32_t TIM_ICFilter); +static void TIMER_TI2FP2_ConfigInputStage(TIM_TypeDef *TIMx, uint32_t TIM_ICPolarity, uint32_t TIM_ICFilter); +static void TIMER_IC1_SetConfig(TIM_TypeDef *TIMx, uint32_t TIM_ICPolarity, uint32_t TIM_ICSelection, uint32_t filter); +static void TIMER_IC2_SetConfig(TIM_TypeDef *TIMx, uint32_t TIM_ICPolarity, uint32_t TIM_ICSelection, uint32_t filter); +static void TIMER_IC3_SetConfig(TIM_TypeDef *TIMx, uint32_t TIM_ICPolarity, uint32_t TIM_ICSelection, uint32_t filter); +static void TIMER_IC4_SetConfig(TIM_TypeDef *TIMx, uint32_t TIM_ICPolarity, uint32_t TIM_ICSelection, uint32_t filter); + +/********************************************************************************* +* Function : HAL_TIMER_MSP_Init +* Description : MSP init, mainly about clock, nvic +* Input : timer handler +* Output : 0: success; else:error +* Author : xwl +**********************************************************************************/ +__weak uint32_t HAL_TIMER_MSP_Init(TIM_HandleTypeDef * htim) +{ + uint32_t Timer_Instance; + + if (0 == IS_TIMER_INSTANCE(htim->Instance)) + { + return HAL_ERROR; //instance error + } + + Timer_Instance = (uint32_t)(htim->Instance); + + switch(Timer_Instance) + { + case TIM1_BASE: + System_Module_Reset(RST_TIM1); + System_Module_Enable(EN_TIM1); + NVIC_ClearPendingIRQ(TIM1_BRK_UP_TRG_COM_IRQn); + NVIC_EnableIRQ(TIM1_BRK_UP_TRG_COM_IRQn); + break; + + case TIM2_BASE: + System_Module_Reset(RST_TIM2); + System_Module_Enable(EN_TIM2); + NVIC_ClearPendingIRQ(TIM2_IRQn); + NVIC_EnableIRQ(TIM2_IRQn); + break; + + case TIM3_BASE: + System_Module_Reset(RST_TIM3); + System_Module_Enable(EN_TIM3); + NVIC_ClearPendingIRQ(TIM3_IRQn); + NVIC_EnableIRQ(TIM3_IRQn); + break; + + case TIM4_BASE: + System_Module_Reset(RST_TIM4); + System_Module_Enable(EN_TIM4); + NVIC_ClearPendingIRQ(TIM4_IRQn); + NVIC_EnableIRQ(TIM4_IRQn); + break; + + case TIM6_BASE: + System_Module_Reset(RST_TIM6); + System_Module_Enable(EN_TIM6); + NVIC_ClearPendingIRQ(TIM6_IRQn); + NVIC_EnableIRQ(TIM6_IRQn); + break; + + case TIM7_BASE: + System_Module_Reset(RST_TIM7); + System_Module_Enable(EN_TIM7); + NVIC_ClearPendingIRQ(TIM7_IRQn); + NVIC_EnableIRQ(TIM7_IRQn); + break; + + case TIM14_BASE: + System_Module_Reset(RST_TIM14); + System_Module_Enable(EN_TIM14); + NVIC_ClearPendingIRQ(TIM14_IRQn); + NVIC_EnableIRQ(TIM14_IRQn); + break; + + case TIM15_BASE: + System_Module_Reset(RST_TIM15); + System_Module_Enable(EN_TIM15); + NVIC_ClearPendingIRQ(TIM15_IRQn); + NVIC_EnableIRQ(TIM15_IRQn); + break; + + case TIM16_BASE: + System_Module_Reset(RST_TIM16); + System_Module_Enable(EN_TIM16); + NVIC_ClearPendingIRQ(TIM16_IRQn); + NVIC_EnableIRQ(TIM16_IRQn); + break; + + case TIM17_BASE: + System_Module_Reset(RST_TIM17); + System_Module_Enable(EN_TIM17); + NVIC_ClearPendingIRQ(TIM17_IRQn); + NVIC_EnableIRQ(TIM17_IRQn); + break; + + default: + return HAL_ERROR; + } + + return HAL_OK; +} + + +__weak uint32_t HAL_TIMER_Base_MspDeInit(TIM_HandleTypeDef * htim) +{ + uint32_t Timer_Instance; + + if (0 == IS_TIMER_INSTANCE(htim->Instance)) + { + return HAL_ERROR; //instance error + } + + Timer_Instance = (uint32_t)(htim->Instance); + + switch(Timer_Instance) + { + case TIM1_BASE: + System_Module_Disable(EN_TIM1); + NVIC_ClearPendingIRQ(TIM1_BRK_UP_TRG_COM_IRQn); + NVIC_DisableIRQ(TIM1_BRK_UP_TRG_COM_IRQn); + break; + + case TIM2_BASE: + System_Module_Disable(EN_TIM2); + NVIC_ClearPendingIRQ(TIM2_IRQn); + NVIC_DisableIRQ(TIM2_IRQn); + break; + + case TIM3_BASE: + System_Module_Disable(EN_TIM3); + NVIC_ClearPendingIRQ(TIM3_IRQn); + NVIC_DisableIRQ(TIM3_IRQn); + break; + + case TIM4_BASE: + System_Module_Disable(EN_TIM4); + NVIC_ClearPendingIRQ(TIM4_IRQn); + NVIC_DisableIRQ(TIM4_IRQn); + break; + + case TIM6_BASE: + System_Module_Disable(EN_TIM6); + NVIC_ClearPendingIRQ(TIM6_IRQn); + NVIC_DisableIRQ(TIM6_IRQn); + break; + + case TIM7_BASE: + System_Module_Disable(EN_TIM7); + NVIC_ClearPendingIRQ(TIM7_IRQn); + NVIC_DisableIRQ(TIM7_IRQn); + break; + + case TIM14_BASE: + System_Module_Disable(EN_TIM14); + NVIC_ClearPendingIRQ(TIM14_IRQn); + NVIC_DisableIRQ(TIM14_IRQn); + break; + + case TIM15_BASE: + System_Module_Disable(EN_TIM15); + NVIC_ClearPendingIRQ(TIM15_IRQn); + NVIC_DisableIRQ(TIM15_IRQn); + break; + + case TIM16_BASE: + System_Module_Disable(EN_TIM16); + NVIC_ClearPendingIRQ(TIM16_IRQn); + NVIC_DisableIRQ(TIM16_IRQn); + break; + + case TIM17_BASE: + System_Module_Disable(EN_TIM17); + NVIC_ClearPendingIRQ(TIM17_IRQn); + NVIC_DisableIRQ(TIM17_IRQn); + break; + + default: + return HAL_ERROR; + } + + return HAL_OK; +} +/********************************************************************************* +* Function : HAL_TIMER_Slave_Mode_Config +* Description : configure timer in slave mode +* Input : + htim: timer handler + sSlaveConfig: slave mode parameter strcture + SlaveMode: TIM_SLAVE_MODE_DIS, TIM_SLAVE_MODE_ENC1... + InputTrigger: TIM_TRIGGER_SOURCE_ITR0, TIM_TRIGGER_SOURCE_ITR1... + TriggerPolarity: TIM_SLAVE_CAPTURE_ACTIVE_RISING, TIM_SLAVE_CAPTURE_ACTIVE_FALLING... + TriggerPrescaler: TIM_ETR_PRESCALER_1, TIM_ETR_PRESCALER_2... +* Output : 0: success; else:error +* Author : xwl +**********************************************************************************/ +uint32_t HAL_TIMER_Slave_Mode_Config(TIM_HandleTypeDef *htim, TIM_SlaveConfigTypeDef *sSlaveConfig) +{ + if (0 == IS_TIM_SLAVE_INSTANCE(htim->Instance) ) + { + return 1; // not supported + } + /*reset SMS and TS bits*/ + htim->Instance->SMCR &= (~(BIT0|BIT1|BIT2|BIT4|BIT5|BIT6)); + /*SET SMS bits*/ + htim->Instance->SMCR |= (sSlaveConfig->SlaveMode & (BIT0|BIT1|BIT2) ); + /*SET TS bits*/ + htim->Instance->SMCR |= (sSlaveConfig->InputTrigger & (BIT4|BIT5|BIT6) ); + + switch (sSlaveConfig->InputTrigger) + { + case TIM_TRIGGER_SOURCE_TI1FP1: + TIMER_TI1FP1_ConfigInputStage(htim->Instance, sSlaveConfig->TriggerPolarity, sSlaveConfig->TriggerFilter); + break; + + case TIM_TRIGGER_SOURCE_TI2FP2: + TIMER_TI2FP2_ConfigInputStage(htim->Instance, sSlaveConfig->TriggerPolarity, sSlaveConfig->TriggerFilter); + break; + + case TIM_TRIGGER_SOURCE_ETRF: + TIMER_ETR_SetConfig(htim->Instance, sSlaveConfig->TriggerPrescaler, sSlaveConfig->TriggerPolarity, sSlaveConfig->TriggerFilter); + break; + + case TIM_TRIGGER_SOURCE_ITR0: + case TIM_TRIGGER_SOURCE_ITR1: + case TIM_TRIGGER_SOURCE_ITR2: + case TIM_TRIGGER_SOURCE_ITR3: + // don't need do anything here + break; + + default: + return 1; + } + + return 0; +} + +/********************************************************************************* +* Function : HAL_TIMER_Master_Mode_Config +* Description : configure timer in master mode +* Input : + TIMx: timer instance + sMasterConfig: master mode parameter structure + MasterSlaveMode: TIM_TRGO_RESET, TIM_TRGO_ENABLE... + MasterOutputTrigger: TIM_MASTERSLAVEMODE_DISABLE, TIM_MASTERSLAVEMODE_ENABLE +* Output : 0: success; else:error +* Author : xwl +**********************************************************************************/ +uint32_t HAL_TIMER_Master_Mode_Config(TIM_TypeDef *TIMx, TIM_MasterConfigTypeDef * sMasterConfig) +{ + /*reset bits*/ + TIMx->SMCR &= (~BIT7); + TIMx->CR2 &= (~(BIT4|BIT5|BIT6)); + + TIMx->SMCR |= sMasterConfig->MasterSlaveMode; + TIMx->CR2 |= sMasterConfig->MasterOutputTrigger; + + return 0; +} + +/********************************************************************************* +* Function : HAL_TIMER_Output_Config +* Description : configure output parameter +* Input : + TIMx: timer instance + Output_Config: output configration parameter structure + OCMode: OUTPUT_MODE_FROZEN, OUTPUT_MODE_MATCH_HIGH... + Pulse: write to ccrx register + OCPolarity: OC channel output polarity: OUTPUT_POL_ACTIVE_HIGH, OUTPUT_POL_ACTIVE_LOW + OCNPolarity: OCN channel output polarity: OUTPUT_POL_ACTIVE_HIGH, OUTPUT_POL_ACTIVE_LOW + OCFastMode: OUTPUT_FAST_MODE_DISABLE, OUTPUT_FAST_MODE_ENABLE + OCIdleState: OC channel idle state, OUTPUT_IDLE_STATE_0, OUTPUT_IDLE_STATE_1 + OCNIdleState: OCN channel idle state, OUTPUT_IDLE_STATE_0, OUTPUT_IDLE_STATE_1 + Channel: TIM_CHANNEL_1, TIM_CHANNEL_2... +* Output : 0: success; else:error +* Author : xwl +**********************************************************************************/ +uint32_t HAL_TIMER_Output_Config(TIM_TypeDef *TIMx, TIM_OC_InitTypeDef * Output_Config, uint32_t Channel) +{ + if (0 == IS_TIM_CCX_INSTANCE(TIMx, Channel) ) + { + return 1; // error parameter + } + + switch(Channel) + { + case TIM_CHANNEL_1: + TIMx->CCER &= (~BIT0); //disable OC1 + if (OUTPUT_POL_ACTIVE_HIGH == Output_Config->OCPolarity) + { + TIMx->CCER &= (~BIT1); + } + else + { + TIMx->CCER |= (BIT1); + } + + if (IS_TIM_CCXN_INSTANCE(TIMx, Channel) ) + { + TIMx->CCER &= (~BIT2); //disable OC1N + + if (OUTPUT_POL_ACTIVE_HIGH == Output_Config->OCNPolarity) + { + TIMx->CCER &= (~BIT3); + } + else + { + TIMx->CCER |= (BIT3); + } + } + + TIMx->CCMR1 &= (~0x00FFU); // reset low 8 bits + TIMx->CCR1 = Output_Config->Pulse; + if (OUTPUT_FAST_MODE_ENABLE == Output_Config->OCFastMode) + { + TIMx->CCMR1 |= (BIT2); + } + TIMx->CCMR1 |= (BIT3); // preload enable + + if (IS_TIM_BREAK_INSTANCE(TIMx)) + { + if (OUTPUT_IDLE_STATE_0 == Output_Config->OCIdleState) + { + TIMx->CR2 &= (~BIT8); + } + else + { + TIMx->CR2 |= BIT8; + } + + if (OUTPUT_IDLE_STATE_0 == Output_Config->OCNIdleState) + { + TIMx->CR2 &= (~BIT9); + } + else + { + TIMx->CR2 |= BIT9; + } + + } + TIMx->CCMR1 = (TIMx->CCMR1 & (~(BIT4|BIT5|BIT6))) | (Output_Config->OCMode << 4); + break; + + case TIM_CHANNEL_2: + TIMx->CCER &= (~BIT4); //disable OC2 + if (OUTPUT_POL_ACTIVE_HIGH == Output_Config->OCPolarity) + { + TIMx->CCER &= (~BIT5); + } + else + { + TIMx->CCER |= (BIT5); + } + + if (IS_TIM_CCXN_INSTANCE(TIMx, Channel) ) + { + TIMx->CCER &= (~BIT6); //disable OC2N + + if (OUTPUT_POL_ACTIVE_HIGH == Output_Config->OCNPolarity) + { + TIMx->CCER &= (~BIT7); + } + else + { + TIMx->CCER |= (BIT7); + } + } + + TIMx->CCMR1 &= (~0xFF00U); // reset high 8 bits + TIMx->CCR2 = Output_Config->Pulse; // write value to ccr before preload enable + if (OUTPUT_FAST_MODE_ENABLE == Output_Config->OCFastMode) + { + TIMx->CCMR1 |= (BIT10); + } + TIMx->CCMR1 |= (BIT11); // preload enable + + if (IS_TIM_BREAK_INSTANCE(TIMx)) + { + if (OUTPUT_IDLE_STATE_0 == Output_Config->OCIdleState) + { + TIMx->CR2 &= (~BIT10); + } + else + { + TIMx->CR2 |= BIT10; + } + + if (OUTPUT_IDLE_STATE_0 == Output_Config->OCNIdleState) + { + TIMx->CR2 &= (~BIT11); + } + else + { + TIMx->CR2 |= BIT11; + } + + } + TIMx->CCMR1 = (TIMx->CCMR1 & (~(BIT12|BIT13|BIT14))) | (Output_Config->OCMode << 12); + break; + + case TIM_CHANNEL_3: + TIMx->CCER &= (~BIT8); //disable OC3 + if (OUTPUT_POL_ACTIVE_HIGH == Output_Config->OCPolarity) + { + TIMx->CCER &= (~BIT9); + } + else + { + TIMx->CCER |= (BIT9); + } + + if (IS_TIM_CCXN_INSTANCE(TIMx, Channel) ) + { + TIMx->CCER &= (~BIT10); //disable OC3N + + if (OUTPUT_POL_ACTIVE_HIGH == Output_Config->OCNPolarity) + { + TIMx->CCER &= (~BIT11); + } + else + { + TIMx->CCER |= (BIT11); + } + } + + TIMx->CCMR2 &= (~0x00FF); // reset low 8 bits + TIMx->CCMR2 |= (BIT3); // preload enable + if (OUTPUT_FAST_MODE_ENABLE == Output_Config->OCFastMode) + { + TIMx->CCMR2 |= (BIT2); + } + + TIMx->CCR3 = Output_Config->Pulse; + if (IS_TIM_BREAK_INSTANCE(TIMx)) + { + if (OUTPUT_IDLE_STATE_0 == Output_Config->OCIdleState) + { + TIMx->CR2 &= (~BIT12); + } + else + { + TIMx->CR2 |= BIT12; + } + + if (OUTPUT_IDLE_STATE_0 == Output_Config->OCNIdleState) + { + TIMx->CR2 &= (~BIT13); + } + else + { + TIMx->CR2 |= BIT13; + } + + } + TIMx->CCMR2 = (TIMx->CCMR2 & (~(BIT4|BIT5|BIT6))) | (Output_Config->OCMode << 4); + break; + + case TIM_CHANNEL_4: + TIMx->CCER &= (~BIT12); //disable OC4 + if (OUTPUT_POL_ACTIVE_HIGH == Output_Config->OCPolarity) + { + TIMx->CCER &= (~BIT13); + } + else + { + TIMx->CCER |= (BIT13); + } + + TIMx->CCMR2 &= (~0xFF00); // reset high 8 bits + TIMx->CCR4 = Output_Config->Pulse; + if (OUTPUT_FAST_MODE_ENABLE == Output_Config->OCFastMode) + { + TIMx->CCMR2 |= (BIT10); // fast mode + } + TIMx->CCMR2 |= (BIT11); // preload enable + + if (IS_TIM_BREAK_INSTANCE(TIMx)) + { + if (OUTPUT_IDLE_STATE_0 == Output_Config->OCIdleState) + { + TIMx->CR2 &= (~BIT14); + } + else + { + TIMx->CR2 |= BIT14; + } + + } + TIMx->CCMR2 = (TIMx->CCMR2 & (~(BIT12|BIT13|BIT14))) | (Output_Config->OCMode << 12); + break; + + default: + return 1; // error parameter + } + + return 0; +} + + +/********************************************************************************* +* Function : HAL_TIMER_Capture_Config +* Description : configure capture parameters +* Input : + TIMx: timer instance + Capture_Config: capture configuration parameter strcture + ICPolarity: TIM_SLAVE_CAPTURE_ACTIVE_RISING, TIM_SLAVE_CAPTURE_ACTIVE_FALLING... + ICSelection: TIM_ICSELECTION_DIRECTTI, TIM_ICSELECTION_INDIRECTTI + ICFilter: TIM_IC1_FILTER_LVL(x), TIM_IC2_FILTER_LVL(x), x:0-15 + ICPrescaler: TIM_IC1_PRESCALER_1, TIM_IC2_PRESCALER_1... + Channel: channel id, TIM_CHANNEL_1, TIM_CHANNEL_2... +* Output : 0: success; else:error +* Author : xwl +**********************************************************************************/ +uint32_t HAL_TIMER_Capture_Config(TIM_TypeDef *TIMx, TIM_IC_InitTypeDef * Capture_Config, uint32_t Channel) +{ + switch(Channel) + { + case TIM_CHANNEL_1: + TIMER_IC1_SetConfig(TIMx, Capture_Config->ICPolarity, Capture_Config->ICSelection, Capture_Config->TIFilter); + + /* Reset the IC1PSC Bits */ + TIMx->CCMR1 &= (~BIT2|BIT3); + /* Set the IC1PSC value */ + TIMx->CCMR1 |= Capture_Config->ICPrescaler; + break; + + case TIM_CHANNEL_2: + TIMER_IC2_SetConfig(TIMx, Capture_Config->ICPolarity, Capture_Config->ICSelection, Capture_Config->TIFilter); + + + /* Reset the IC2PSC Bits */ + TIMx->CCMR1 &= (~BIT10|BIT11); + /* Set the IC2PSC value */ + TIMx->CCMR1 |= Capture_Config->ICPrescaler; + break; + + case TIM_CHANNEL_3: + TIMER_IC3_SetConfig(TIMx, Capture_Config->ICPolarity, Capture_Config->ICSelection, Capture_Config->TIFilter); + + /* Reset the IC3PSC Bits */ + TIMx->CCMR2 &= (~BIT2|BIT3); + /* Set the IC3PSC value */ + TIMx->CCMR2 |= Capture_Config->ICPrescaler; + + break; + + case TIM_CHANNEL_4: + TIMER_IC4_SetConfig(TIMx, Capture_Config->ICPolarity, Capture_Config->ICSelection, Capture_Config->TIFilter); + + /* Reset the IC4PSC Bits */ + TIMx->CCMR2 &= (~BIT10|BIT11); + /* Set the IC4PSC value */ + TIMx->CCMR2 |= Capture_Config->ICPrescaler; + break; + + default: + return 1; + } + + return 0; +} + + + +/********************************************************************************* +* Function : HAL_TIMER_SelectClockSource +* Description : select timer counter source, internal or external +* Input: + htim : timer handler + sClockSourceConfig: configuration parameters, includes following members: + ClockSource: TIM_CLOCKSOURCE_INT, TIM_CLOCKSOURCE_ETR... + ClockPolarity: TIM_SLAVE_CAPTURE_ACTIVE_RISING, TIM_SLAVE_CAPTURE_ACTIVE_FALLING... + ClockPrescaler: TIM_ETR_PRESCALER_1, TIM_ETR_PRESCALER_2... + ClockFilter: TIM_ETR_FILTER_LVL(x), TIM_IC1_FILTER_LVL(x), TIM_IC2_FILTER_LVL(x) +* Output : HAL_ERROR:error, HAL_OK:OK +* Author : xwl +**********************************************************************************/ +HAL_StatusTypeDef HAL_TIMER_SelectClockSource(TIM_HandleTypeDef *htim, TIM_ClockConfigTypeDef * sClockSourceConfig) +{ + htim->Instance->SMCR &= (~(BIT0|BIT1|BIT2)); + + switch (sClockSourceConfig->ClockSource) + { + case TIM_CLOCKSOURCE_INT: + { + // do nothing here + break; + } + + case TIM_CLOCKSOURCE_ETR: + { + + /* Configure the ETR Clock source */ + TIMER_ETR_SetConfig(htim->Instance, + sClockSourceConfig->ClockPrescaler, + sClockSourceConfig->ClockPolarity, + sClockSourceConfig->ClockFilter); + /* Enable the External clock mode2 */ + htim->Instance->SMCR |= BIT14; // ECE=1,external clock mode 2 + break; + } + + case TIM_CLOCKSOURCE_TI1FP1: + { + + TIMER_TI1FP1_ConfigInputStage(htim->Instance, + sClockSourceConfig->ClockPolarity, + sClockSourceConfig->ClockFilter); + + htim->Instance->SMCR &= (~(BIT4|BIT5|BIT6)); // trigger selection + htim->Instance->SMCR |= (5 << 4); // Trigger select TI1FP1 + + htim->Instance->SMCR |= (BIT0|BIT1|BIT2); // select external clock mode 1 + break; + } + + case TIM_CLOCKSOURCE_TI2FP2: + { + TIMER_TI2FP2_ConfigInputStage(htim->Instance, + sClockSourceConfig->ClockPolarity, + sClockSourceConfig->ClockFilter); + + htim->Instance->SMCR &= (~(BIT4|BIT5|BIT6)); // trigger selection + htim->Instance->SMCR |= (6 << 4); // Trigger select TI2FP2 + + htim->Instance->SMCR |= (BIT0|BIT1|BIT2); // select external clock mode 1 + break; + } + + case TIM_CLOCKSOURCE_ITR0: + case TIM_CLOCKSOURCE_ITR1: + case TIM_CLOCKSOURCE_ITR2: + case TIM_CLOCKSOURCE_ITR3: + { + htim->Instance->SMCR &= (~(BIT4|BIT5|BIT6)); + htim->Instance->SMCR |= ( (sClockSourceConfig->ClockSource - TIM_CLOCKSOURCE_ITR0) << 4); + + htim->Instance->SMCR |= (BIT0|BIT1|BIT2); // select external clock mode 1 + break; + } + + default: + return HAL_ERROR; + } + + return HAL_OK; +} + +/********************************************************************************* +* Function : HAL_TIMER_Base_Init +* Description : timer base initiation +* Input : timer handler +* Output : 0: success; else:error +* Author : xwl +**********************************************************************************/ +uint32_t HAL_TIMER_Base_Init(TIM_HandleTypeDef * htim) +{ + if (0 == IS_TIMER_INSTANCE(htim->Instance)) + { + return 1; //instance error + } + + htim->Instance->CR1 = BIT2; // CEN=0, URS=1, OPM = 0 + + if (htim->Init.ARRPreLoadEn) + { + htim->Instance->CR1 |= (BIT7); + } + else + { + htim->Instance->CR1 &= (~BIT7); + } + htim->Instance->ARR = htim->Init.Period; + htim->Instance->PSC = htim->Init.Prescaler; + if (IS_TIM_REPETITION_COUNTER_INSTANCE(htim->Instance)) + { + htim->Instance->RCR = htim->Init.RepetitionCounter; + } + htim->Instance->EGR = BIT0; // no UIF generated because URS=1 + + if (IS_TIM_CLOCK_DIVISION_INSTANCE(htim->Instance)) + { + htim->Instance->CR1 = (htim->Instance->CR1 & (~(BIT8|BIT9))) | ((htim->Init.ClockDivision) & (BIT8|BIT9)); + } + //up/down/center mode + htim->Instance->CR1 = (htim->Instance->CR1 & (~(BIT4|BIT5|BIT6))) | ((htim->Init.CounterMode) & (BIT4|BIT5|BIT6)); + + htim->Instance->CR1 &= (~BIT2); //URS = 0 + + return 0; +} + +/********************************************************************************* +* Function : HAL_TIMER_Base_DeInit +* Description : timer base deinitiation, disable Timer, turn off module clock and nvic +* Input : timer handler +* Output : HAL_OK: success; HAL_ERROR:error +* Author : xwl +**********************************************************************************/ +HAL_StatusTypeDef HAL_TIMER_Base_DeInit(TIM_HandleTypeDef *htim) +{ + htim->Instance->CR1 &= (~BIT0); + + HAL_TIMER_Base_MspDeInit(htim); + + return HAL_OK; +} + +/********************************************************************************* +* Function : HAL_TIMER_Base_Start +* Description : start timer +* Input : timer instance +* Output : none +* Author : xwl +**********************************************************************************/ +void HAL_TIMER_Base_Start(TIM_TypeDef *TIMx) +{ + if (0 == IS_TIM_SLAVE_INSTANCE(TIMx) ) + { + TIMx->CR1 |= BIT0; + return; + } + + if (TIM_SLAVE_MODE_TRIG != (TIMx->SMCR & (BIT0|BIT1|BIT2) ) ) + { + TIMx->CR1 |= BIT0; + return; + } + + return; +} + +/********************************************************************************* +* Function : HAL_TIMER_Base_Stop +* Description : stop timer +* Input : timer handler +* Output : none +* Author : xwl +**********************************************************************************/ +HAL_StatusTypeDef HAL_TIMER_Base_Stop(TIM_TypeDef *TIMx) +{ + TIMx->CR1 &= (~BIT0); + HAL_TIM_DISABLE_IT_EX(TIMx, TIM_IT_UPDATE); + + return HAL_OK; +} + +/********************************************************************************* +* Function : HAL_TIMER_OnePulse_Init +* Description : start timer with one pulse mode +* Input : + htim: timer handler + mode: 0 means normal mode, 1 means one pulse mode +* Output : HAL_OK, success; HAL_ERROR, fail +* Author : xwl +**********************************************************************************/ +HAL_StatusTypeDef HAL_TIMER_OnePulse_Init(TIM_HandleTypeDef *htim, uint32_t mode) +{ + /* Check the TIM handle allocation */ + if(htim == NULL) + { + return HAL_ERROR; + } + + HAL_TIMER_Base_Init(htim); + + /*reset the OPM Bit */ + htim->Instance->CR1 &= (~BIT3); + if (0 != mode) + { + /*set the OPM Bit */ + htim->Instance->CR1 |= BIT3; + } + + return HAL_OK; +} + +/********************************************************************************* +* Function : HAL_TIM_PWM_Output_Start +* Description : start timer output +* Input : + TIMx: timer instance + Channel: TIM_CHANNEL_1, TIM_CHANNEL_2... +* Output : : 0: success; else:error +* Author : xwl +**********************************************************************************/ +uint32_t HAL_TIM_PWM_Output_Start(TIM_TypeDef *TIMx, uint32_t Channel) +{ + if (0 == IS_TIM_CCX_INSTANCE(TIMx, Channel) ) + { + return 1; // error parameter + } + + switch(Channel) + { + case TIM_CHANNEL_1: + TIMx->CCER |= BIT0; + if (IS_TIM_CCXN_INSTANCE(TIMx, Channel) ) + { + TIMx->CCER |= BIT2; + } + break; + + case TIM_CHANNEL_2: + TIMx->CCER |= BIT4; + if (IS_TIM_CCXN_INSTANCE(TIMx, Channel) ) + { + TIMx->CCER |= BIT6; + } + break; + + case TIM_CHANNEL_3: + TIMx->CCER |= BIT8; + if (IS_TIM_CCXN_INSTANCE(TIMx, Channel) ) + { + TIMx->CCER |= BIT10; + } + break; + + case TIM_CHANNEL_4: + TIMx->CCER |= BIT12; + break; + + default: + return 1; + } + + if(IS_TIM_BREAK_INSTANCE(TIMx) != 0) + { + /* Enable the main output */ + TIMx->BDTR |= BIT15; + } + + if (TIM_SLAVE_MODE_TRIG != (TIMx->SMCR & (BIT0|BIT1|BIT2) ) ) + { + TIMx->CR1 |= BIT0; + } + + return 0; +} +/********************************************************************************* +* Function : HAL_TIM_PWM_Output_Stop +* Description : stop timer pwm output +* Input : + TIMx: timer instance + Channel: TIM_CHANNEL_1, TIM_CHANNEL_2... +* Output : : 0: success; else:error +* Author : xwl +**********************************************************************************/ +HAL_StatusTypeDef HAL_TIM_PWM_Output_Stop(TIM_TypeDef *TIMx, uint32_t Channel) +{ + if (0 == IS_TIM_CCX_INSTANCE(TIMx, Channel) ) + { + return 1; // error parameter + } + + switch(Channel) + { + case TIM_CHANNEL_1: + TIMx->CCER &= (~(BIT0 | BIT2)); + break; + + case TIM_CHANNEL_2: + TIMx->CCER &= (~(BIT4 | BIT6)); + break; + + case TIM_CHANNEL_3: + TIMx->CCER &= (~(BIT8 | BIT10)); + break; + + case TIM_CHANNEL_4: + TIMx->CCER &= (~(BIT12)); + break; + + default: + return 1; + } + + if(IS_TIM_BREAK_INSTANCE(TIMx) != 0) + { + /* Enable the main output */ + TIMx->BDTR &= (~BIT15); + } + + if (TIM_SLAVE_MODE_TRIG != (TIMx->SMCR & (BIT0|BIT1|BIT2) ) ) + { + TIMx->CR1 &= (~BIT0); + } + + /* Return function status */ + return HAL_OK; +} + +/********************************************************************************* +* Function : HAL_TIMER_OC_Start +* Description : start timer output +* Input : + TIMx: timer instance + Channel: TIM_CHANNEL_1, TIM_CHANNEL_2... +* Output : : 0: success; else:error +* Author : xwl +**********************************************************************************/ +uint32_t HAL_TIMER_OC_Start(TIM_TypeDef *TIMx, uint32_t Channel) +{ + if (0 == IS_TIM_CCX_INSTANCE(TIMx, Channel) ) + { + return 1; // error parameter + } + + switch(Channel) + { + case TIM_CHANNEL_1: + TIMx->CCER |= BIT0; + if (IS_TIM_CCXN_INSTANCE(TIMx, Channel) ) + { + TIMx->CCER |= BIT2; + } + break; + + case TIM_CHANNEL_2: + TIMx->CCER |= BIT4; + if (IS_TIM_CCXN_INSTANCE(TIMx, Channel) ) + { + TIMx->CCER |= BIT6; + } + break; + + case TIM_CHANNEL_3: + TIMx->CCER |= BIT8; + if (IS_TIM_CCXN_INSTANCE(TIMx, Channel) ) + { + TIMx->CCER |= BIT10; + } + break; + + case TIM_CHANNEL_4: + TIMx->CCER |= BIT12; + break; + + default: + return 1; + } + + if(IS_TIM_BREAK_INSTANCE(TIMx) != 0) + { + /* Enable the main output */ + TIMx->BDTR |= BIT15; + } + + if (TIM_SLAVE_MODE_TRIG != (TIMx->SMCR & (BIT0|BIT1|BIT2) ) ) + { + TIMx->CR1 |= BIT0; + } + + return 0; +} + +/********************************************************************************* +* Function : HAL_TIMER_OCxN_Start +* Description : start timer OCxN output +* Input : + TIMx: timer instance + Channel: TIM_CHANNEL_1, TIM_CHANNEL_2... +* Output : : 0: success; else:error +* Author : xwl +**********************************************************************************/ +uint32_t HAL_TIMER_OCxN_Start(TIM_TypeDef *TIMx, uint32_t Channel) +{ + if (0 == IS_TIM_CCX_INSTANCE(TIMx, Channel) ) + { + return 1; // error parameter + } + + switch(Channel) + { + case TIM_CHANNEL_1: + if (IS_TIM_CCXN_INSTANCE(TIMx, Channel) ) + { + TIMx->CCER |= BIT2; + } + break; + + case TIM_CHANNEL_2: + if (IS_TIM_CCXN_INSTANCE(TIMx, Channel) ) + { + TIMx->CCER |= BIT6; + } + break; + + case TIM_CHANNEL_3: + if (IS_TIM_CCXN_INSTANCE(TIMx, Channel) ) + { + TIMx->CCER |= BIT10; + } + break; + + case TIM_CHANNEL_4: + TIMx->CCER |= BIT12; + break; + + default: + return 1; + } + + if(IS_TIM_BREAK_INSTANCE(TIMx) != 0) + { + /* Enable the main output */ + TIMx->BDTR |= BIT15; + } + + if (TIM_SLAVE_MODE_TRIG != (TIMx->SMCR & (BIT0|BIT1|BIT2) ) ) + { + TIMx->CR1 |= BIT0; + } + + return 0; +} + +/********************************************************************************* +* Function : HAL_TIMER_OC_Stop +* Description : stop timer output +* Input : + TIMx: timer instance + Channel: TIM_CHANNEL_1, TIM_CHANNEL_2... +* Output : : 0: success; else:error +* Author : xwl +**********************************************************************************/ +HAL_StatusTypeDef HAL_TIMER_OC_Stop(TIM_TypeDef *TIMx, uint32_t Channel) +{ + if (0 == IS_TIM_CCX_INSTANCE(TIMx, Channel) ) + { + return 1; // error parameter + } + + switch(Channel) + { + case TIM_CHANNEL_1: + TIMx->CCER &= (~(BIT0 | BIT2)); + break; + + case TIM_CHANNEL_2: + TIMx->CCER &= (~(BIT4 | BIT6)); + break; + + case TIM_CHANNEL_3: + TIMx->CCER &= (~(BIT8 | BIT10)); + break; + + case TIM_CHANNEL_4: + TIMx->CCER &= (~(BIT12)); + break; + + default: + return 1; + } + + if(IS_TIM_BREAK_INSTANCE(TIMx) != 0) + { + /* Enable the main output */ + TIMx->BDTR &= (~BIT15); + } + + if (TIM_SLAVE_MODE_TRIG != (TIMx->SMCR & (BIT0|BIT1|BIT2) ) ) + { + TIMx->CR1 &= (~BIT0); + } + + /* Return function status */ + return HAL_OK; +} + +/********************************************************************************* +* Function : HAL_TIM_Capture_Start +* Description : start timer capture +* Input : + TIMx: timer instance + Channel: TIM_CHANNEL_1, TIM_CHANNEL_2... +* Output : : 0: success; else:error +* Author : xwl +**********************************************************************************/ +uint32_t HAL_TIM_Capture_Start(TIM_TypeDef *TIMx, uint32_t Channel) +{ + if (0 == IS_TIM_CCX_INSTANCE(TIMx, Channel) ) + { + return 1; // error parameter + } + + switch(Channel) + { + case TIM_CHANNEL_1: + TIMx->CCER |= BIT0; + break; + + case TIM_CHANNEL_2: + TIMx->CCER |= BIT4; + break; + + case TIM_CHANNEL_3: + TIMx->CCER |= BIT8; + break; + + case TIM_CHANNEL_4: + TIMx->CCER |= BIT12; + break; + + default: + return 1; + } + + if (TIM_SLAVE_MODE_TRIG != (TIMx->SMCR & (BIT0|BIT1|BIT2) ) ) + { + TIMx->CR1 |= BIT0; + } + + return 0; +} + + +/********************************************************************************* +* Function : HAL_TIM_Capture_Stop +* Description : stop timer capture +* Input : + TIMx: timer instance + Channel: TIM_CHANNEL_1, TIM_CHANNEL_2... +* Output : : 0: success; else:error +* Author : xwl +**********************************************************************************/ +uint32_t HAL_TIM_Capture_Stop(TIM_TypeDef *TIMx, uint32_t Channel) +{ + if (0 == IS_TIM_CCX_INSTANCE(TIMx, Channel) ) + { + return 1; // error parameter + } + + switch(Channel) + { + case TIM_CHANNEL_1: + TIMx->CCER &= (~BIT0); + break; + + case TIM_CHANNEL_2: + TIMx->CCER &= (~BIT4); + break; + + case TIM_CHANNEL_3: + TIMx->CCER &= (~BIT8); + break; + + case TIM_CHANNEL_4: + TIMx->CCER &= (~BIT12); + break; + + default: + return 1; + } + + if (TIM_SLAVE_MODE_TRIG != (TIMx->SMCR & (BIT0|BIT1|BIT2) ) ) + { + TIMx->CR1 &= (~BIT0); + } + + return 0; +} + + +/********************************************************************************* +* Function : HAL_TIMEx_ETRSelection +* Description : select ETR signal, it can ben GPIO, COMP1_OUT, COMP2_OUT, ADC analog watchdog output +* Input : + htim: timer handler + ETRSelection: ETR_SELECT_GPIO, ETR_SELECT_COMP1_OUT... +* Output : HAL_OK, Success; HAL_ERROR:Fail +* Author : xwl +**********************************************************************************/ +HAL_StatusTypeDef HAL_TIMEx_ETRSelection(TIM_HandleTypeDef *htim, uint32_t ETRSelection) +{ + HAL_StatusTypeDef status = HAL_OK; + + htim->Instance->AF1 &= (~ETR_SELECT_MASK); + htim->Instance->AF1 |= ETRSelection; + + return status; +} + +/********************************************************************************* +* Function : HAL_TIMER_ReadCapturedValue +* Description : read capture value as channel +* Input : + htim: timer handler + Channel: TIM_CHANNEL_1, TIM_CHANNEL_2... +* Output : capture value +* Author : xwl +**********************************************************************************/ +uint32_t HAL_TIMER_ReadCapturedValue(TIM_HandleTypeDef *htim, uint32_t Channel) +{ + uint32_t capture_data = 0U; + + switch (Channel) + { + case TIM_CHANNEL_1: + { + /* Return the capture 1 value */ + capture_data = htim->Instance->CCR1; + break; + } + case TIM_CHANNEL_2: + { + /* Return the capture 2 value */ + capture_data = htim->Instance->CCR2; + break; + } + case TIM_CHANNEL_3: + { + /* Return the capture 3 value */ + capture_data = htim->Instance->CCR3; + break; + } + case TIM_CHANNEL_4: + { + /* Return the capture 4 value */ + capture_data = htim->Instance->CCR4; + break; + } + default: + break; + } + + return capture_data; +} + +/********************************************************************************* +* Function : HAL_TIMER_GenerateEvent +* Description : Generate event by software +* Input: + htim : timer handler + EventSource: TIM_EVENTSOURCE_UPDATE, TIM_EVENTSOURCE_CC1... +* Output : HAL_ERROR:error, HAL_OK:OK +* Author : xwl +**********************************************************************************/ +HAL_StatusTypeDef HAL_TIMER_GenerateEvent(TIM_HandleTypeDef *htim, uint32_t EventSource) +{ + htim->Instance->EGR = EventSource; + + return HAL_OK; +} + +/********************************************************************************* +* Function : HAL_TIMER_Clear_Capture_Flag +* Description : clear capture flag as channel id +* Input : + htim: timer handler + Channel: TIM_CHANNEL_1, TIM_CHANNEL_2... +* Output : capture value +* Author : xwl +**********************************************************************************/ +void HAL_TIMER_Clear_Capture_Flag(TIM_HandleTypeDef *htim, uint32_t Channel) +{ + switch (Channel) + { + case TIM_CHANNEL_1: + { + htim->Instance->SR &= (~(BIT1|BIT9)); + break; + } + case TIM_CHANNEL_2: + { + htim->Instance->SR &= (~(BIT2|BIT10)); + break; + } + case TIM_CHANNEL_3: + { + htim->Instance->SR &= (~(BIT3|BIT11)); + break; + } + case TIM_CHANNEL_4: + { + htim->Instance->SR &= (~(BIT4|BIT12)); + break; + } + default: + break; + } +} + +/********************************************************************************* +* Function : TIMER_ETR_SetConfig +* Description : configure ETR channel polarity, prescaler and filter +* Input: + TIMx : timer instance + TIM_ExtTRGPrescaler: TIM_ETR_PRESCALER_1, TIM_ETR_PRESCALER_2... + TIM_ExtTRGPolarity: TIM_ETR_POLAIRTY_HIGH, TIM_ETR_POLAIRTY_LOW + ExtTRGFilter: TIM_ETR_FILTER_LVL(x), x=0-15 +* Output : none +* Author : xwl +**********************************************************************************/ +static void TIMER_ETR_SetConfig(TIM_TypeDef* TIMx, uint32_t TIM_ExtTRGPrescaler, uint32_t TIM_ExtTRGPolarity, uint32_t ExtTRGFilter) +{ + /* Reset the ETR Bits */ + TIMx->SMCR &= (~0xFF00U); + + /* Set the Prescaler, the Filter value and the Polarity */ + TIMx->SMCR |= (TIM_ExtTRGPrescaler | TIM_ExtTRGPolarity | ExtTRGFilter); +} + +/********************************************************************************* +* Function : TIMER_TI1FP1_ConfigInputStage +* Description : configure TI1FP1 channel polarity and filter +* Input: + TIMx : timer instance + TIM_ICPolarity: TIM_SLAVE_CAPTURE_ACTIVE_RISING, TIM_SLAVE_CAPTURE_ACTIVE_FALLING... + Filter: TIM_TI1_FILTER_LVL(x), x=0-15 +* Output : none +* Author : xwl +**********************************************************************************/ +static void TIMER_TI1FP1_ConfigInputStage(TIM_TypeDef *TIMx, uint32_t TIM_ICPolarity, uint32_t Filter) +{ + TIMx->CCER &= (~BIT0); //Disable the Channel 1: Reset the CC1E Bit + TIMx->CCMR1 = (TIMx->CCMR1 & (~(BIT0|BIT1)) | BIT0); // CH1 as input + + TIMx->CCMR1 &= (~0xF0U); // reset TI1 filter + TIMx->CCMR1 |= Filter; + + if(TIM_SLAVE_CAPTURE_ACTIVE_RISING == TIM_ICPolarity) + { + TIMx->CCER |= TIM_CC1_SLAVE_CAPTURE_POL_RISING; + } + else if (TIM_SLAVE_CAPTURE_ACTIVE_FALLING == TIM_ICPolarity) + { + TIMx->CCER |= TIM_CC1_SLAVE_CAPTURE_POL_FALLING; + } + else + { + TIMx->CCER |= TIM_CC1_SLAVE_CAPTURE_POL_BOTH; + } +} + +/********************************************************************************* +* Function : TIMER_TI2FP2_ConfigInputStage +* Description : configure TI2FP2 channel polarity and filter +* Input: + TIMx : timer instance + TIM_ICPolarity: TIM_SLAVE_CAPTURE_ACTIVE_RISING, TIM_SLAVE_CAPTURE_ACTIVE_FALLING... + Filter: TIM_TI2_FILTER_LVL(x), x=0-15 +* Output : none +* Author : xwl +**********************************************************************************/ +static void TIMER_TI2FP2_ConfigInputStage(TIM_TypeDef *TIMx, uint32_t TIM_ICPolarity, uint32_t Filter) +{ + TIMx->CCER &= (~BIT4); //Disable the Channel 2: Reset the CC2E Bit + TIMx->CCMR1 = (TIMx->CCMR1 & (~(BIT8|BIT9)) | BIT8); // CH2 as input + + TIMx->CCMR1 &= (~0xF000U); // reset TI2 filter + TIMx->CCMR1 |= Filter; + + if(TIM_SLAVE_CAPTURE_ACTIVE_RISING == TIM_ICPolarity) + { + TIMx->CCER |= TIM_CC2_SLAVE_CAPTURE_POL_RISING; + } + else if (TIM_SLAVE_CAPTURE_ACTIVE_FALLING == TIM_ICPolarity) + { + TIMx->CCER |= TIM_CC2_SLAVE_CAPTURE_POL_FALLING; + } + else + { + TIMx->CCER |= TIM_CC2_SLAVE_CAPTURE_POL_BOTH; + } +} + +/********************************************************************************* +* Function : TIMER_IC1_SetConfig +* Description : configure TI1FP1 or TI2FP1 channel polarity and filter +* Input: + TIMx : timer instance + TIM_ICPolarity: TIM_SLAVE_CAPTURE_ACTIVE_RISING, TIM_SLAVE_CAPTURE_ACTIVE_FALLING... + Filter: TIM_TI1_FILTER_LVL(x), x=0-15 +* Output : none +* Author : xwl +**********************************************************************************/ +void TIMER_IC1_SetConfig(TIM_TypeDef *TIMx, uint32_t TIM_ICPolarity, uint32_t TIM_ICSelection, uint32_t Filter) +{ + /* Disable the Channel 1: Reset the CC1E Bit */ + TIMx->CCER &= (~BIT0); + + if(TIM_SLAVE_CAPTURE_ACTIVE_RISING == TIM_ICPolarity) + { + TIMx->CCER |= TIM_CC1_SLAVE_CAPTURE_POL_RISING; + } + else if (TIM_SLAVE_CAPTURE_ACTIVE_FALLING == TIM_ICPolarity) + { + TIMx->CCER |= TIM_CC1_SLAVE_CAPTURE_POL_FALLING; + } + else if (TIM_SLAVE_CAPTURE_ACTIVE_RISING_FALLING == TIM_ICPolarity) + { + TIMx->CCER |= TIM_CC1_SLAVE_CAPTURE_POL_BOTH; + } + + if(TIM_ICSELECTION_DIRECTTI == TIM_ICSelection) + { + TIMx->CCMR1 = (TIMx->CCMR1 & (~(BIT0|BIT1))) | BIT0; + TIMx->CCMR1 &= (~0xF0U); + } + else + { + TIMx->CCMR1 = (TIMx->CCMR1 & (~(BIT0|BIT1))) | BIT1; + TIMx->CCMR1 &= (~0xF000U); + } + + TIMx->CCMR1 |= Filter; + +} + +/********************************************************************************* +* Function : TIMER_IC2_SetConfig +* Description : configure TI1FP2 or TI2FP2 channel polarity and filter +* Input: + TIMx : timer instance + TIM_ICPolarity: TIM_SLAVE_CAPTURE_ACTIVE_RISING, TIM_SLAVE_CAPTURE_ACTIVE_FALLING... + Filter: TIM_TI2_FILTER_LVL(x), x=0-15 +* Output : none +* Author : xwl +**********************************************************************************/ +static void TIMER_IC2_SetConfig(TIM_TypeDef *TIMx, uint32_t TIM_ICPolarity, uint32_t TIM_ICSelection, uint32_t Filter) +{ + /* Disable the Channel 2, Reset the CC2E Bit */ + TIMx->CCER &= (~BIT4); + if(TIM_SLAVE_CAPTURE_ACTIVE_RISING == TIM_ICPolarity) + { + TIMx->CCER |= TIM_CC2_SLAVE_CAPTURE_POL_RISING; + } + else if (TIM_SLAVE_CAPTURE_ACTIVE_FALLING == TIM_ICPolarity) + { + TIMx->CCER |= TIM_CC2_SLAVE_CAPTURE_POL_FALLING; + } + else if (TIM_SLAVE_CAPTURE_ACTIVE_RISING_FALLING == TIM_ICPolarity) + { + TIMx->CCER |= TIM_CC2_SLAVE_CAPTURE_POL_BOTH; + } + + if(TIM_ICSELECTION_DIRECTTI == TIM_ICSelection) + { + TIMx->CCMR1 = (TIMx->CCMR1 & (~(BIT8|BIT9))) | BIT8; + TIMx->CCMR1 &= (~0xF000U); + } + else + { + TIMx->CCMR1 = (TIMx->CCMR1 & (~(BIT8|BIT9))) | BIT9; + TIMx->CCMR1 &= (~0xF0U); + } + + TIMx->CCMR1 |= Filter; + +} + +/********************************************************************************* +* Function : TIMER_IC3_SetConfig +* Description : configure TI3FP3 or TI4FP3 channel polarity and filter +* Input: + TIMx : timer instance + TIM_ICPolarity: TIM_SLAVE_CAPTURE_ACTIVE_RISING, TIM_SLAVE_CAPTURE_ACTIVE_FALLING... + Filter: TIM_TI3_FILTER_LVL(x), x=0-15 +* Output : none +* Author : xwl +**********************************************************************************/ +static void TIMER_IC3_SetConfig(TIM_TypeDef *TIMx, uint32_t TIM_ICPolarity, uint32_t TIM_ICSelection, uint32_t Filter) +{ + /* Disable the Channel 3, Reset the CC3E Bit */ + TIMx->CCER &= (~BIT8); + + if(TIM_SLAVE_CAPTURE_ACTIVE_RISING == TIM_ICPolarity) + { + TIMx->CCER |= TIM_CC3_SLAVE_CAPTURE_POL_RISING; + } + else if (TIM_SLAVE_CAPTURE_ACTIVE_FALLING == TIM_ICPolarity) + { + TIMx->CCER |= TIM_CC3_SLAVE_CAPTURE_POL_FALLING; + } + else if (TIM_SLAVE_CAPTURE_ACTIVE_RISING_FALLING == TIM_ICPolarity) + { + TIMx->CCER |= TIM_CC3_SLAVE_CAPTURE_POL_BOTH; + } + + if(TIM_ICSELECTION_DIRECTTI == TIM_ICSelection) + { + TIMx->CCMR2 = (TIMx->CCMR2 & (~(BIT0|BIT1))) | BIT0; + TIMx->CCMR2 &= (~0xF0U); + } + else + { + TIMx->CCMR2 = (TIMx->CCMR2 & (~(BIT0|BIT1))) | BIT1; + TIMx->CCMR2 &= (~0xF000U); + } + + + TIMx->CCMR2 |= Filter; +} + + +/********************************************************************************* +* Function : TIMER_IC4_SetConfig +* Description : configure TI3FP4 or TI4FP4 channel polarity and filter +* Input: + TIMx : timer instance + TIM_ICPolarity: TIM_SLAVE_CAPTURE_ACTIVE_RISING, TIM_SLAVE_CAPTURE_ACTIVE_FALLING... + Filter: TIM_TI4_FILTER_LVL(x), x=0-15 +* Output : none +* Author : xwl +**********************************************************************************/ +static void TIMER_IC4_SetConfig(TIM_TypeDef *TIMx, uint32_t TIM_ICPolarity, uint32_t TIM_ICSelection, uint32_t Filter) +{ + /* Disable the Channel 3, Reset the CC3E Bit */ + TIMx->CCER &= (~BIT12); + + if(TIM_SLAVE_CAPTURE_ACTIVE_RISING == TIM_ICPolarity) + { + TIMx->CCER |= TIM_CC4_SLAVE_CAPTURE_POL_RISING; + } + else if (TIM_SLAVE_CAPTURE_ACTIVE_FALLING == TIM_ICPolarity) + { + TIMx->CCER |= TIM_CC4_SLAVE_CAPTURE_POL_FALLING; + } + else if (TIM_SLAVE_CAPTURE_ACTIVE_RISING_FALLING == TIM_ICPolarity) + { + TIMx->CCER |= TIM_CC4_SLAVE_CAPTURE_POL_BOTH; + } + + if(TIM_ICSELECTION_DIRECTTI == TIM_ICSelection) + { + TIMx->CCMR2 = (TIMx->CCMR2 & (~(BIT8|BIT9))) | BIT8; + TIMx->CCMR2 &= (~0xF000U); + } + else + { + TIMx->CCMR2 = (TIMx->CCMR2 & (~(BIT8|BIT9))) | BIT9; + TIMx->CCMR2 &= (~0xF0U); + } + + TIMx->CCMR2 |= Filter; + +} + + diff --git a/bsp/acm32f4xx-nucleo/libraries/HAL_Driver/Src/HAL_TIMER_EX.c b/bsp/acm32f4xx-nucleo/libraries/HAL_Driver/Src/HAL_TIMER_EX.c new file mode 100644 index 0000000000..ce8e65693a --- /dev/null +++ b/bsp/acm32f4xx-nucleo/libraries/HAL_Driver/Src/HAL_TIMER_EX.c @@ -0,0 +1,160 @@ +/*********************************************************************** + * Filename : hal_lpuart.c + * Description : lpuart driver source file + * Author(s) : xwl + * version : V1.0 + * Modify date : 2021-04-02 + ***********************************************************************/ +#include "ACM32Fxx_HAL.h" + + +/********************************************************************************* +* Function : HAL_TIMER_ConfigBreakDeadTime +* Description : configure deadtime parameter +* Input : timer handler, break and deadtime configuration +* Output : none +* Author : xwl +**********************************************************************************/ +void HAL_TIMEx_ConfigBreakDeadTime(TIM_HandleTypeDef *htim, TIM_BreakDeadTimeConfigTypeDef * sBreakDeadTimeConfig) +{ + /* Keep this variable initialized to 0 as it is used to configure BDTR register */ + uint32_t break_deadtime_reg = 0U; + + /* Set the BDTR bits */ + MODIFY_REG(break_deadtime_reg, TIM_BDTR_DTG, sBreakDeadTimeConfig->DeadTime); + MODIFY_REG(break_deadtime_reg, TIM_BDTR_LOCK, sBreakDeadTimeConfig->LockLevel); + MODIFY_REG(break_deadtime_reg, TIM_BDTR_OSSI, sBreakDeadTimeConfig->OffStateIDLEMode); + MODIFY_REG(break_deadtime_reg, TIM_BDTR_OSSR, sBreakDeadTimeConfig->OffStateRunMode); + MODIFY_REG(break_deadtime_reg, TIM_BDTR_BKE, sBreakDeadTimeConfig->BreakState); + MODIFY_REG(break_deadtime_reg, TIM_BDTR_BKP, sBreakDeadTimeConfig->BreakPolarity); + MODIFY_REG(break_deadtime_reg, TIM_BDTR_AOE, sBreakDeadTimeConfig->AutomaticOutput); + MODIFY_REG(break_deadtime_reg, TIM_BDTR_BKF, (sBreakDeadTimeConfig->BreakFilter << TIM_BDTR_BKF_Pos)); + + /* Set TIMx_BDTR */ + htim->Instance->BDTR = break_deadtime_reg; + +} + +/********************************************************************************* +* Function : HAL_TIMEx_ConfigBreakInput +* Description : Configures the break input source. +* Input : + htim: timer handler + BreakInput: TIM_BREAKINPUT_BRK + sBreakInputConfig: Break input source configuration +* Output : +* Author : xwl +**********************************************************************************/ +HAL_StatusTypeDef HAL_TIMEx_ConfigBreakInput(TIM_HandleTypeDef *htim, uint32_t BreakInput, + TIMEx_BreakInputConfigTypeDef *sBreakInputConfig) +{ + uint32_t tmporx; + uint32_t bkin_enable_mask; + uint32_t bkin_polarity_mask; + uint32_t bkin_enable_bitpos; + uint32_t bkin_polarity_bitpos; + + switch(sBreakInputConfig->Source) + { + case TIM_BREAKINPUTSOURCE_BKIN: + { + bkin_enable_mask = TIM1_AF1_BKINE; + bkin_enable_bitpos = TIM1_AF1_BKINE_Pos; + bkin_polarity_mask = TIM1_AF1_BKINP; + bkin_polarity_bitpos = TIM1_AF1_BKINP_Pos; + break; + } +#ifdef HAL_COMP_MODULE_ENABLED + case TIM_BREAKINPUTSOURCE_COMP1: + { + bkin_enable_mask = TIM1_AF1_BKCMP1E; + bkin_enable_bitpos = TIM1_AF1_BKCMP1E_Pos; + bkin_polarity_mask = TIM1_AF1_BKCMP1P; + bkin_polarity_bitpos = TIM1_AF1_BKCMP1P_Pos; + break; + } + case TIM_BREAKINPUTSOURCE_COMP2: + { + bkin_enable_mask = TIM1_AF1_BKCMP2E; + bkin_enable_bitpos = TIM1_AF1_BKCMP2E_Pos; + bkin_polarity_mask = TIM1_AF1_BKCMP2P; + bkin_polarity_bitpos = TIM1_AF1_BKCMP2P_Pos; + break; + } +#endif /* COMP1 && COMP2 */ + + default: + { + bkin_enable_mask = 0U; + bkin_enable_bitpos = 0U; + bkin_polarity_mask = 0U; + bkin_polarity_bitpos = 0U; + break; + } + } + + switch(BreakInput) + { + case TIM_BREAKINPUT_BRK: + { + /* Get the TIMx_AF1 register value */ + tmporx = htim->Instance->AF1; + + /* Enable the break input */ + tmporx &= ~bkin_enable_mask; + tmporx |= (sBreakInputConfig->Enable << bkin_enable_bitpos) & bkin_enable_mask; + + /* Set the break input polarity */ + tmporx &= ~bkin_polarity_mask; + tmporx |= (sBreakInputConfig->Polarity << bkin_polarity_bitpos) & bkin_polarity_mask; + + /* Set TIMx_AF1 */ + htim->Instance->AF1 = tmporx; + break; + } + + default: + break; + } + + return HAL_OK; +} + + +/********************************************************************************* +* Function : HAL_TIMEx_ConfigCommutEvent +* Description : Configure the TIM commutation event sequence. This function is mandatory to use the commutation event + in order to update the configuration at each commutation detection on the TRGI input of the Timer. +* Input : + htim: timer handler + InputTrigger: TIM_TRIGGER_SOURCE_ITR0, TIM_TRIGGER_SOURCE_ITR1... + CommutationSource: TIM_COMMUTATION_TRGI, TIM_COMMUTATION_SOFTWARE +* Output : +* Author : xwl +**********************************************************************************/ +void HAL_TIMEx_ConfigCommutEvent(TIM_HandleTypeDef *htim, uint32_t InputTrigger, uint32_t CommutationSource) +{ + + if ((InputTrigger == TIM_TRIGGER_SOURCE_ITR0) || (InputTrigger == TIM_TRIGGER_SOURCE_ITR1) || + (InputTrigger == TIM_TRIGGER_SOURCE_ITR2) || (InputTrigger == TIM_TRIGGER_SOURCE_ITR3)) + { + /* Select the Input trigger */ + htim->Instance->SMCR &= (~(BIT4|BIT5|BIT6)); + htim->Instance->SMCR |= InputTrigger; + } + + /* Select the Capture Compare preload feature */ + htim->Instance->CR2 |= TIM_CR2_CCPC; + /* Select the Commutation event source */ + htim->Instance->CR2 &= ~TIM_CR2_CCUS; + htim->Instance->CR2 |= CommutationSource; + + /* Disable Commutation Interrupt */ + HAL_TIM_DISABLE_IT(htim, TIM_IT_COM); + + /* Disable Commutation DMA request */ + HAL_TIM_DISABLE_DMA(htim, TIM_DMA_COM); + +} + + diff --git a/bsp/acm32f4xx-nucleo/libraries/HAL_Driver/Src/HAL_UART.c b/bsp/acm32f4xx-nucleo/libraries/HAL_Driver/Src/HAL_UART.c new file mode 100644 index 0000000000..14530ea921 --- /dev/null +++ b/bsp/acm32f4xx-nucleo/libraries/HAL_Driver/Src/HAL_UART.c @@ -0,0 +1,904 @@ +/* + ****************************************************************************** + * @file HAL_Uart.c + * @version V1.0.0 + * @date 2020 + * @brief UART HAL module driver. + * This file provides firmware functions to manage the following + * functionalities of the Universal Asynchronous Receiver Transmitter Peripheral (UART). + * @ Initialization and de-initialization functions + * @ IO operation functions + * @ Peripheral Control functions + ****************************************************************************** +*/ +#include "ACM32Fxx_HAL.h" + + +/* If Use 'UART_MODE_TX_RX_DEBUG', Point to Debug Uart */ +UART_TypeDef *Uart_Debug = NULL; + +/* Private function prototypes -----------------------------------------------*/ +static void UART_Config_BaudRate(UART_HandleTypeDef *huart); +static HAL_StatusTypeDef HAL_UART_Wait_Tx_Done(UART_HandleTypeDef *huart); +__weak void HAL_UART_TxCpltCallback(UART_HandleTypeDef *huart); +__weak void HAL_UART_RxCpltCallback(UART_HandleTypeDef *huart); +__weak void HAL_UART_ErrorCallback(UART_HandleTypeDef *huart); + +/********************************************************************************* +* Function : HAL_UART_IRQHandler +* Description : Handle UART interrupt request. +* Input : huart: UART handle. +* Output : +* Author : Chris_Kyle Data : 2020 +**********************************************************************************/ +void HAL_UART_IRQHandler(UART_HandleTypeDef *huart) +{ + uint32_t read_bytes_number; + +#if (USE_FULL_ASSERT == 1) + if (!IS_UART_ALL_INSTANCE(huart->Instance)) return; +#endif + + uint32_t isrflags =READ_REG(huart->Instance->RIS); + uint32_t ieits =READ_REG(huart->Instance->IE); + uint32_t errorflags =0x00U; + errorflags =(isrflags & (uint32_t)(UART_ICR_PEI|UART_ICR_OEI|UART_ICR_FEI|UART_ICR_BEI)); + + /* Enable TXI */ + if (huart->Instance->IE & UART_IE_TXI) + { + if (huart->Instance->RIS & UART_RIS_TXI) + { + /* Clear TXI Status */ + SET_BIT(huart->Instance->ICR , UART_ICR_TXI); + + for(;;) + { + if(huart->lu32_TxCount == huart->lu32_TxSize) + { + huart->lu8_TxBusy = false; + + /* Disable TX interrupt */ + CLEAR_BIT(huart->Instance->IE, UART_IE_TXI); + + HAL_UART_TxCpltCallback(huart); + break; + } + + if (READ_BIT(huart->Instance->FR, UART_FR_TXFF)) + { + break; + } + + huart->Instance->DR = huart->lu8_TxData[huart->lu32_TxCount++]; + } + } + } + + /* RXI */ + if ((huart->Instance->IE & UART_IE_RXI || huart->Instance->IE& UART_IE_RTI) && errorflags == 0) + { + if (huart->Instance->RIS & UART_RIS_RXI) + { + read_bytes_number = 0; + /* Clear RXI Status */ + SET_BIT(huart->Instance->ICR, UART_ICR_RXI); + + /* Receive end */ + while(huart->lu32_RxCount lu32_RxSize ) + { + if(!READ_BIT(huart->Instance->FR, UART_FR_RXFE)) + { + /* Store Data in buffer */ + huart->lu8_RxData[huart->lu32_RxCount++] = huart->Instance->DR; + read_bytes_number++; + } + else + { + break; + } + if (read_bytes_number == huart->lu32_fifo_level_minus1) + { + break; + } + } + if(huart->lu32_RxCount ==huart->lu32_RxSize ) + { + huart->lu8_RxBusy = false; + + /* Disable RX and RTI interrupt */ + CLEAR_BIT(huart->Instance->IE, (UART_IE_RXI|UART_IE_RTI)); + + /* clear error interrupt */ + CLEAR_BIT(huart->Instance->IE, UART_IE_OEI|UART_IE_BEI|UART_IE_PEI|UART_IE_FEI); + + HAL_UART_RxCpltCallback(huart); + } + } + else if(huart->Instance->RIS & UART_RIS_RTI) + { + /*clear RTI Status */ + SET_BIT(huart->Instance->ICR ,UART_ICR_RTI); + + while(!READ_BIT(huart->Instance->FR, UART_FR_RXFE)) + { + huart->lu8_RxData[huart->lu32_RxCount++] = huart->Instance->DR; + } + + huart->lu8_RxBusy = false; + + /* Disable RX and RTI interrupt */ + CLEAR_BIT(huart->Instance->IE, (UART_IE_RXI|UART_IE_RTI)); + + /* clear error interrupt */ + CLEAR_BIT(huart->Instance->IE, UART_IE_OEI|UART_IE_BEI|UART_IE_PEI|UART_IE_FEI); + + HAL_UART_RxCpltCallback(huart); + } + } + /* if some errors occurred */ + if(errorflags != 0 &&(ieits & (UART_IE_OEI|UART_IE_BEI|UART_IE_PEI|UART_IE_FEI))) + { + /* UART parity error interrupt occurred */ + if (((isrflags & UART_RIS_PEI) != 0) && ((ieits & UART_IE_PEI) != 0)) + { + /* Clear parity error status */ + SET_BIT(huart->Instance->ICR, UART_ICR_PEI); + huart->ErrorCode |= HAL_UART_ERROR_PE; + } + + /* UART break error interrupt occurred */ + if (((isrflags & UART_RIS_BEI) != 0) && ((ieits & UART_IE_BEI) != 0)) + { + SET_BIT(huart->Instance->ICR, UART_RIS_BEI); + huart->ErrorCode |= HAL_UART_ERROR_NE; + } + + /* UART frame error interrupt occurred */ + if (((isrflags & UART_RIS_FEI) != 0) && ((ieits & UART_IE_FEI) != 0)) + { + SET_BIT(huart->Instance->ICR, UART_RIS_FEI); + huart->ErrorCode |= HAL_UART_ERROR_FE; + } + + /* UART Over-Run interrupt occurred */ + if (((isrflags & UART_RIS_OEI) != 0) && ((ieits & UART_IE_OEI) != 0)) + { + SET_BIT(huart->Instance->ICR, UART_RIS_OEI); + huart->ErrorCode |= HAL_UART_ERROR_ORE; + } + + /* clear error interrupt */ + CLEAR_BIT(huart->Instance->IE, UART_IE_OEI|UART_IE_BEI|UART_IE_PEI|UART_IE_FEI); + + HAL_UART_ErrorCallback(huart); + } +} + +/********************************************************************************* +* Function : HAL_UART_Wait_Tx_Done +* Description : wait Tx FIFO empty +* Input : huart: UART handle. +* Output : +**********************************************************************************/ +static HAL_StatusTypeDef HAL_UART_Wait_Tx_Done(UART_HandleTypeDef *huart) +{ +#if (USE_FULL_ASSERT == 1) + if (!IS_UART_ALL_INSTANCE(huart->Instance)) return HAL_ERROR; +#endif + /* wait FIFO empty */ + while(READ_BIT(huart->Instance->FR, UART_FR_BUSY)); + + return HAL_OK; +} + +/********************************************************************************* +* Function : HAL_UART_MspInit +* Description : Initialize the UART MSP. +* Input : huart: UART handle. +* Output : +* Author : Chris_Kyle Data : 2020 +**********************************************************************************/ +__weak void HAL_UART_MspInit(UART_HandleTypeDef *huart) +{ + /* + NOTE: This function should be modified, when the callback is needed, + the HAL_UART_MspInit can be implemented in the user file. + */ + + /* For Example */ + GPIO_InitTypeDef GPIO_Uart1; + + if (huart->Instance == UART1) + { + /* Enable Clock */ + System_Module_Enable(EN_UART1); + //System_Module_Enable(EN_GPIOAB); + + /* Initialization GPIO */ + /* A9:Tx A10:Rx */ + GPIO_Uart1.Pin = GPIO_PIN_9 | GPIO_PIN_10; + GPIO_Uart1.Mode = GPIO_MODE_AF_PP; + GPIO_Uart1.Pull = GPIO_PULLUP; + GPIO_Uart1.Alternate = GPIO_FUNCTION_2; + + HAL_GPIO_Init(GPIOA, &GPIO_Uart1); + + if (huart->Init.HwFlowCtl & UART_HWCONTROL_CTS) + { + /* A11:CTS */ + GPIO_Uart1.Pin = GPIO_PIN_11; + + HAL_GPIO_Init(GPIOA, &GPIO_Uart1); + } + + if (huart->Init.HwFlowCtl & UART_HWCONTROL_RTS) + { + /* A12:RTS */ + GPIO_Uart1.Pin = GPIO_PIN_12; + + HAL_GPIO_Init(GPIOA, &GPIO_Uart1); + } + + /* NVIC Config */ + NVIC_ClearPendingIRQ(UART1_IRQn); + NVIC_SetPriority(UART1_IRQn, 5); + NVIC_EnableIRQ(UART1_IRQn); + } +} + +/********************************************************************************* +* Function : HAL_UART_Init +* Description : Initialize the UART mode according to the specified parameters +* in the UART_InitTypeDef +* Input : huart: UART handle. +* Output : +* Author : Chris_Kyle Data : 2020 +**********************************************************************************/ +HAL_StatusTypeDef HAL_UART_Init(UART_HandleTypeDef *huart) +{ + +#if (USE_FULL_ASSERT == 1) + if (!IS_UART_ALL_INSTANCE(huart->Instance)) return HAL_ERROR; + if (!IS_UART_WORDLENGTH(huart->Init.WordLength)) return HAL_ERROR; + if (!IS_UART_STOPBITS(huart->Init.StopBits)) return HAL_ERROR; + if (!IS_UART_PARITY(huart->Init.Parity)) return HAL_ERROR; + if (!IS_UART_MODE(huart->Init.Mode)) return HAL_ERROR; + if (!IS_UART_HARDWARE_FLOW_CONTROL(huart->Init.HwFlowCtl)) return HAL_ERROR; +#endif + + /* Init the low level hardware : GPIO, CLOCK, NVIC */ + HAL_UART_MspInit(huart); + + /* Config BaudRate */ + UART_Config_BaudRate(huart); + + /* Set the UART Communication parameters */ + //huart->Instance->LCRH = huart->Init.WordLength | UART_LCRH_FEN | huart->Init.StopBits | huart->Init.Parity; + huart->Instance->LCRH = huart->Init.WordLength | huart->Init.StopBits | huart->Init.Parity; + huart->Instance->CR = huart->Init.HwFlowCtl | huart->Init.Mode | UART_CR_UARTEN; + + if (huart->Init.Mode == UART_MODE_TX_RX_DEBUG) + { + Uart_Debug = huart->Instance; + } + else if (huart->Init.Mode == UART_MODE_HALF_DUPLEX) + { + huart->Instance->CR2 = UART_CR2_TXOE_SEL; + } + return HAL_OK; +} + +/********************************************************************************* +* Function : HAL_UART_MspDeInit +* Description : DeInitialize the UART MSP. +* Input : huart: UART handle. +* Output : +**********************************************************************************/ +__weak void HAL_UART_MspDeInit(UART_HandleTypeDef *huart) +{ + /* + NOTE: This function should be modified, when the callback is needed, + the HAL_UART_MspDeInit can be implemented in the user file. + */ + if (huart->Instance == UART1) + { + /* Disable Clock */ + System_Module_Disable(EN_UART1); + + /* DeInitialization GPIO */ + /* A9:Tx A10:Rx */ + HAL_GPIO_DeInit(GPIOA,GPIO_PIN_9 | GPIO_PIN_10); + + if (huart->Init.HwFlowCtl & UART_HWCONTROL_CTS) + { + /* A11:CTS */ + HAL_GPIO_DeInit(GPIOA, GPIO_PIN_11); + } + + if (huart->Init.HwFlowCtl & UART_HWCONTROL_RTS) + { + /* A12:RTS */ + HAL_GPIO_DeInit(GPIOA, GPIO_PIN_12); + } + + /* NVIC DeInit */ + NVIC_DisableIRQ(UART1_IRQn); + + } + else if(huart->Instance == UART2) + { + + } +} + +/********************************************************************************* +* Function : HAL_UART_Init +* Description : Initialize the UART mode according to the specified parameters +* in the UART_InitTypeDef +* Input : huart: UART handle. +* Output : +**********************************************************************************/ +HAL_StatusTypeDef HAL_UART_DeInit(UART_HandleTypeDef *huart) +{ + +#if (USE_FULL_ASSERT == 1) + if (!IS_UART_ALL_INSTANCE(huart->Instance)) return HAL_ERROR; +#endif + + /* DeInit the low level hardware : GPIO, CLOCK, NVIC */ + HAL_UART_MspDeInit(huart); + + return HAL_OK; + +} + + +/********************************************************************************* +* Function : HAL_UART_Transmit +* Description : Send an amount of data in blocking mode. +* Input : huart: UART handle. +* Input : fu8_Data: Pointer to data buffer. +* Input : fu32_Size: Amount of data elements to be sent. +* Input : fu32_Timeout: Timeout duration. +* Output : HAL status +* Author : Chris_Kyle Data : 2020 +**********************************************************************************/ +HAL_StatusTypeDef HAL_UART_Transmit(UART_HandleTypeDef *huart, uint8_t *fu8_Data, uint32_t fu32_Size, uint32_t fu32_Timeout) +{ + uint32_t lu32_Timeout; + +#if (USE_FULL_ASSERT == 1) + if (!IS_UART_ALL_INSTANCE(huart->Instance)) return HAL_ERROR; +#endif + + huart->lu32_TxCount = 0; + + while (fu32_Size--) + { + huart->Instance->DR = *fu8_Data++; + + huart->lu32_TxCount++; + + /* have no timeout */ + if (fu32_Timeout == 0) + { + while (huart->Instance->FR & UART_FR_TXFF); + } + else + { + lu32_Timeout = fu32_Timeout *256; + + while (huart->Instance->FR & UART_FR_TXFF) + { + if (lu32_Timeout-- == 0) + { + return HAL_TIMEOUT; + } + } + } + } + + while ((huart->Instance->FR & UART_FR_BUSY)); + return HAL_OK; +} + +/********************************************************************************* +* Function : HAL_UART_Receive +* Description : Receive an amount of data in blocking mode. +* Input : huart: UART handle. +* Input : fu8_Data: Pointer to data buffer. +* Input : fu32_Size: Amount of data elements to be receive. +* Input : fu32_Timeout: Timeout duration. +* Output : HAL status +* Author : Chris_Kyle Data : 2020 +**********************************************************************************/ +HAL_StatusTypeDef HAL_UART_Receive(UART_HandleTypeDef *huart, uint8_t *fu8_Data, uint32_t fu32_Size, uint32_t fu32_Timeout) +{ + uint32_t lu32_Timeout; + +#if (USE_FULL_ASSERT == 1) + if (!IS_UART_ALL_INSTANCE(huart->Instance)) return HAL_ERROR; +#endif + + huart->lu32_RxCount = 0; + + /* Half duplex Use Tx GPIO Receive Data */ + if (huart->Init.Mode == UART_MODE_HALF_DUPLEX) + { + huart->Instance->CR2 |= UART_CR2_RX_SEL; + } + + while (fu32_Size--) + { + if (fu32_Timeout == 0) + { + while(huart->Instance->FR & UART_FR_RXFE); + + *fu8_Data++ = huart->Instance->DR; + + huart->lu32_RxCount++; + } + else + { + lu32_Timeout = fu32_Timeout * 256; + + while(huart->Instance->FR & UART_FR_RXFE) + { + if (lu32_Timeout-- == 0) + { + /* Clear Half duplex */ + huart->Instance->CR2 &= ~UART_CR2_RX_SEL; + + return HAL_TIMEOUT; + } + } + + *fu8_Data++ = huart->Instance->DR; + + huart->lu32_RxCount++; + } + } + + /* Clear Half duplex */ + huart->Instance->CR2 &= ~UART_CR2_RX_SEL; + + return HAL_OK; +} + +/********************************************************************************* +* Function : HAL_UART_Transmit_IT +* Description : Send an amount of data in interrupt mode. +* Input : huart: UART handle. +* Input : fu8_Data: Pointer to data buffer. +* Input : fu32_Size: Amount of data elements to be receive. +* Output : +* Author : Chris_Kyle Data : 2020 +**********************************************************************************/ +HAL_StatusTypeDef HAL_UART_Transmit_IT(UART_HandleTypeDef *huart, uint8_t *fu8_Data, uint32_t fu32_Size) +{ +#if (USE_FULL_ASSERT == 1) + if (!IS_UART_ALL_INSTANCE(huart->Instance)) return HAL_ERROR; +#endif + + if (huart->lu8_TxBusy == true) + { + return HAL_BUSY; + } + + if (fu32_Size == 0 || fu8_Data == NULL) + { + return HAL_ERROR; + } + + huart->lu32_TxSize = fu32_Size; + huart->lu32_TxCount = 0; + huart->lu8_TxData = fu8_Data; + huart->lu8_TxBusy = true; + + /* Clear TXI Status */ + huart->Instance->ICR = UART_ICR_TXI; + /* FIFO Enable */ + SET_BIT(huart->Instance->LCRH, UART_LCRH_FEN); + /*FIFO Select*/ + SET_BIT(huart->Instance->IFLS,UART_TX_FIFO_1_2); + + for(;;) + { + /*Data Size less than 16Byte */ + if(fu32_Size == huart->lu32_TxCount) + { + huart->lu8_TxBusy = false; + + while ((huart->Instance->FR & UART_FR_BUSY)){} + + HAL_UART_TxCpltCallback(huart); + + return HAL_OK; + } + if(READ_BIT(huart->Instance->FR, UART_FR_TXFF)) + { + break; + } + huart->Instance->DR = huart->lu8_TxData[huart->lu32_TxCount++]; + } + + /* Enable TX interrupt */ + huart->Instance->IE |= UART_IE_TXI; + + return HAL_OK; +} + +/********************************************************************************* +* Function : HAL_UART_Receive_IT +* Description : Receive an amount of data in interrupt mode. +* Input : +* Output : +* Author : Chris_Kyle Data : 2020 +**********************************************************************************/ +HAL_StatusTypeDef HAL_UART_Receive_IT(UART_HandleTypeDef *huart, uint8_t *fu8_Data, uint32_t fu32_Size) +{ +#if (USE_FULL_ASSERT == 1) + if (!IS_UART_ALL_INSTANCE(huart->Instance)) return HAL_ERROR; +#endif + + if (huart->lu8_RxBusy == true) + { + return HAL_BUSY; + } + + if (fu32_Size == 0 || fu8_Data == NULL) + { + return HAL_ERROR; + } + + huart->lu32_RxSize = fu32_Size; + huart->lu32_RxCount = 0; + huart->lu8_RxData = fu8_Data; + huart->lu8_RxBusy = true; + + /* Clear RXI Status */ + huart->Instance->ICR = UART_ICR_RXI; + /* FIFO Enable */ + SET_BIT(huart->Instance->LCRH, UART_LCRH_FEN); + /*FIFO Select*/ + MODIFY_REG(huart->Instance->IFLS, UART_IFLS_RXIFLSEL, UART_RX_FIFO_1_2); + huart->lu32_fifo_level_minus1 = 8-1; // 16/2 - 1 + /* Enable the UART Errors interrupt */ + SET_BIT(huart->Instance->IE,UART_IE_OEI|UART_IE_BEI|UART_IE_PEI|UART_IE_FEI); + /* Enable RX and RTI interrupt */ + SET_BIT(huart->Instance->IE,UART_IE_RXI|UART_IE_RTI); + + return HAL_OK; +} + +/********************************************************************************* +* Function : HAL_UART_Transmit_DMA +* Description : Send an amount of data in DMA mode. +* Input : huart: UART handle. +* Input : fu8_Data: Pointer to data buffer. +* Input : fu32_Size: Amount of data elements to be Send. +* Output : +* Author : Chris_Kyle Data : 2020 +**********************************************************************************/ +HAL_StatusTypeDef HAL_UART_Transmit_DMA(UART_HandleTypeDef *huart, uint8_t *fu8_Data, uint32_t fu32_Size) +{ +#if (USE_FULL_ASSERT == 1) + if (!IS_UART_ALL_INSTANCE(huart->Instance)) return HAL_ERROR; +#endif + + if (huart->lu8_TxBusy == true) + { + return HAL_BUSY; + } + + if (fu32_Size == 0 || fu8_Data == NULL) + { + return HAL_ERROR; + } + + huart->Instance->DMACR |= UART_DMACR_TXDMAE; + + if (HAL_DMA_Start_IT(huart->HDMA_Tx, (uint32_t)fu8_Data, (uint32_t)(&huart->Instance->DR), fu32_Size)) + { + return HAL_ERROR; + } + + return HAL_OK; +} + +/********************************************************************************* +<<<<<<< .mine +* Function : HAL_UART_Receive_DMA +* Description : Receive an amount of data in DMA mode. +* Input : huart: UART handle. +* Input : fu8_Data: Pointer to data buffer. +* Input : fu32_Size: Amount of data elements to be receive. +* Output : +**********************************************************************************/ +HAL_StatusTypeDef HAL_UART_Receive_DMA(UART_HandleTypeDef *huart, uint8_t *fu8_Data, uint32_t fu32_Size) +{ +#if (USE_FULL_ASSERT == 1) + if (!IS_UART_ALL_INSTANCE(huart->Instance)) return HAL_ERROR; +#endif + + if (huart->lu8_RxBusy == true) + { + return HAL_BUSY; + } + + if (fu32_Size == 0 || fu8_Data == NULL) + { + return HAL_ERROR; + } + + huart->Instance->DMACR |= UART_DMACR_RXDMAE; + + if (HAL_DMA_Start_IT(huart->HDMA_Rx, (uint32_t)(&huart->Instance->DR), (uint32_t)fu8_Data, fu32_Size)) + { + return HAL_ERROR; + } + + return HAL_OK; +} + + + +/********************************************************************************* +* Function : HAL_UART_TxCpltCallback +* Description : Tx Transfer completed callbacks. +* Input : +* Output : +* Author : Chris_Kyle Data : 2020 +**********************************************************************************/ +__weak void HAL_UART_TxCpltCallback(UART_HandleTypeDef *huart) +{ + /* + NOTE: This function Should be modified, when the callback is needed, + the HAL_UART_TxCpltCallback could be implemented in the user file. + */ +} + +/********************************************************************************* +* Function : HAL_UART_RxCpltCallback +* Description : Rx Transfer completed callbacks. +* Input : +* Output : +* Author : Chris_Kyle Data : 2020 +**********************************************************************************/ +__weak void HAL_UART_RxCpltCallback(UART_HandleTypeDef *huart) +{ + /* + NOTE: This function Should be modified, when the callback is needed, + the HAL_UART_RxCpltCallback could be implemented in the user file. + */ +} + +/********************************************************************************* +* Function : HAL_UART_ErrorCallBack +* Description : Recv Error callbacks. +* Input : +* Output : +**********************************************************************************/ +__weak void HAL_UART_ErrorCallBack(UART_HandleTypeDef *huart) +{ + /* + NOTE: This function Should be modified, when the callback is needed, + the HAL_UART_ErrorCallBack could be implemented in the user file. + */ +} + +/********************************************************************************* +* Function : UART_Config_BaudRate +* Description : Config BaudRate +* Input : +* Output : +* Author : Chris_Kyle Data : 2020 +**********************************************************************************/ +static void UART_Config_BaudRate(UART_HandleTypeDef *huart) +{ + uint32_t lu32_PCLK; + uint32_t lu32_IBAUD, lu32_FBAUD; + uint64_t lu64_TempValue; + + lu32_PCLK = System_Get_APBClock(); + + /* Integral part */ + lu32_IBAUD = lu32_PCLK / (huart->Init.BaudRate * 16); + + /* Fractional part */ + lu64_TempValue = lu32_PCLK % (huart->Init.BaudRate * 16); + lu64_TempValue = (lu64_TempValue * 1000000) / (huart->Init.BaudRate * 16); + lu32_FBAUD = (lu64_TempValue * 64 + 500000) / 1000000; + + if (lu32_FBAUD >= 64) + { + huart->Instance->IBRD = lu32_IBAUD + 1; + huart->Instance->FBRD = 0; + } + else + { + huart->Instance->IBRD = lu32_IBAUD; + huart->Instance->FBRD = lu32_FBAUD; + } +} + +/********************************************************************************* +* Function : HAL_UART_GetState +* Description : Return the uart State +* Input : +* Output : +**********************************************************************************/ +HAL_StatusTypeDef HAL_UART_GetState(UART_HandleTypeDef *huart) +{ + +#if (USE_FULL_ASSERT == 1) + if (!IS_UART_ALL_INSTANCE(huart->Instance)) return HAL_ERROR; +#endif + + if(huart->lu8_TxBusy || huart->lu8_RxBusy) + { + return HAL_BUSY; + } + + return HAL_OK; +} + + +/********************************************************************************* +* Function : HAL_UART_GetError +* Description : Return the uart Error +* Input : +* Output : +**********************************************************************************/ +uint32_t HAL_UART_GetError(UART_HandleTypeDef *huart) +{ + return huart->ErrorCode; +} + +/********************************************************************************* +* Function : HAL_UART_Abort +* Description : Abort ongoing transfers(blocking mode) +* Input : UART handle +* Output : +**********************************************************************************/ +HAL_StatusTypeDef HAL_UART_Abort(UART_HandleTypeDef *huart) +{ +#if (USE_FULL_ASSERT == 1) + if (!IS_UART_ALL_INSTANCE(huart->Instance)) return HAL_ERROR; +#endif + + /*disble all interrupt*/ + huart->Instance->IE =0x00; + + /* Disable the UART DMA Tx request if enable */ + if(READ_BIT(huart->Instance->DMACR, UART_DMACR_TXDMAE)) + { + CLEAR_BIT(huart->Instance->DMACR, UART_DMACR_TXDMAE); + + /* Abort the UART Tx Channel */ + if(huart->HDMA_Tx) + { + /*Set the UART DMA Abort callback to Null */ + huart->HDMA_Tx->DMA_ITC_Callback =NULL; + + if(HAL_DMA_Abort(huart->HDMA_Tx)!=HAL_OK) + { + return HAL_TIMEOUT; + } + } + } + + /* Disable the UART DMA Rx request if enable */ + if(READ_BIT(huart->Instance->DMACR, UART_DMACR_RXDMAE)) + { + CLEAR_BIT(huart->Instance->DMACR, UART_DMACR_RXDMAE); + + /* Abort the UART Rx Channel */ + if(huart->HDMA_Rx) + { + /*Set the UART DMA Abort callback to Null */ + huart->HDMA_Rx->DMA_ITC_Callback =NULL; + + if(HAL_DMA_Abort(huart->HDMA_Rx)!=HAL_OK) + { + return HAL_TIMEOUT; + } + } + } + + /*Reset Tx and Rx Transfer size*/ + huart->lu32_TxSize = 0; + huart->lu32_RxSize = 0; + + /* Restore huart->lu8_TxBusy and huart->lu8_RxBusy to Ready */ + huart->lu8_TxBusy = false; + huart->lu8_RxBusy = false; + + return HAL_OK; +} + +/********************************************************************************* +* Function : HAL_UART_DMAPause +* Description : Pause the DMA Transfer +* Input : UART handle +* Output : +**********************************************************************************/ +HAL_StatusTypeDef HAL_UART_DMAPause(UART_HandleTypeDef *huart) +{ +#if (USE_FULL_ASSERT == 1) + if (!IS_UART_ALL_INSTANCE(huart->Instance)) return HAL_ERROR; +#endif + + if(READ_BIT(huart->Instance->DMACR, UART_DMACR_TXDMAE)) + { + /* Disable the UART DMA Tx request */ + CLEAR_BIT(huart->Instance->DMACR, UART_DMACR_TXDMAE); + } + + if (READ_BIT(huart->Instance->DMACR, UART_DMACR_RXDMAE)) + { + /* Disable RXNE, PE and ERR (Frame error, noise error, overrun error) interrupts */ + CLEAR_BIT(huart->Instance->IE, UART_IE_OEI|UART_IE_BEI|UART_IE_FEI); + + /* Disable the UART DMA Rx request */ + CLEAR_BIT(huart->Instance->DMACR, UART_DMACR_RXDMAE); + } + + return HAL_OK; +} + + +/********************************************************************************* +* Function : HAL_UART_DMAResume +* Description : Resume the DMA Transfer +* Input : UART handle +* Output : +**********************************************************************************/ +HAL_StatusTypeDef HAL_UART_DMAResume(UART_HandleTypeDef *huart) +{ +#if (USE_FULL_ASSERT == 1) + if (!IS_UART_ALL_INSTANCE(huart->Instance)) return HAL_ERROR; +#endif + + if (huart->lu8_TxBusy == false) + { + /* Enable the UART DMA Tx request */ + SET_BIT(huart->Instance->DMACR, UART_DMACR_TXDMAE); + } + + if (huart->lu8_RxBusy == false) + { + /* Reenable PE and ERR (Frame error, noise error, overrun error) interrupts */ + SET_BIT(huart->Instance->IE, UART_IE_OEI|UART_IE_BEI|UART_IE_FEI); + + /* Enable the UART DMA Rx request */ + SET_BIT(huart->Instance->DMACR, UART_DMACR_RXDMAE); + } + + return HAL_OK; +} + +#if 0 +/********************************************************************************* +* Function : fputc +* Description : +* Input : +* Output : +* Author : Chris_Kyle Data : 2020 +**********************************************************************************/ +__weak int fputc(int ch, FILE *f) +{ + if (Uart_Debug == NULL) + { + return 0; + } + + Uart_Debug->DR = ch; + + while ((Uart_Debug->FR & UART_FR_BUSY)); + + return ch; +} +#endif + diff --git a/bsp/acm32f4xx-nucleo/libraries/HAL_Driver/Src/HAL_UART_EX.c b/bsp/acm32f4xx-nucleo/libraries/HAL_Driver/Src/HAL_UART_EX.c new file mode 100644 index 0000000000..adc4f1bd94 --- /dev/null +++ b/bsp/acm32f4xx-nucleo/libraries/HAL_Driver/Src/HAL_UART_EX.c @@ -0,0 +1,247 @@ +/* + ****************************************************************************** + * @file HAL_UART_EX.c + * @version V1.0.0 + * @date 2021 + * @brief LIN HAL module driver. + * This file provides firmware functions to manage the following + * functionalities of the extensional module: Local Interconnect Network Peripheral (LIN). + * @ Initialization and de-initialization functions + * @ IO operation functions + * @ Peripheral Control functions + ****************************************************************************** +*/ +#include "ACM32Fxx_HAL.h" + +/************************************************************************ + * function : HAL_UART_LIN_Master_Transmit + * Description: Uart lin master transmit data + * input :none + * UART_HandleTypeDef *huart: Serial port number + * uint8_t Lin_Version: LIN version ,should be UART_LIN_V1D3 or UART_LIN_V2DX. + * uint8_t Lin_Id: LIN id + * uint8_t *pData: point to the transmit data buffer. + * uint8_t Size: Transmit buffer Size. + * return: none + ************************************************************************/ +void HAL_UART_LIN_Master_Transmit(UART_HandleTypeDef *huart, uint8_t Lin_Version, uint8_t Lin_Id, uint8_t *pData, uint8_t Size) +{ + uint8_t Lin_P0,Lin_P1,ucI; + uint16_t Lin_Check_Sum = 0; + + if((Size>8)||(pData == 0)) + return; + + CLEAR_BIT(huart->Instance->IE, UART_EX_IE_LBDI); + huart->Instance->CR = 0x0101; //disable uart_rx + + MODIFY_REG(huart->Instance->BCNT, UART_EX_BCNT_VALUE_MASK, (13)<Instance->BCNT, UART_EX_BCNT_START); + SET_BIT(huart->Instance->LCRH, UART_LCRH_BRK); + + while(!(READ_BIT(huart->Instance->RIS, UART_EX_RIS_BCNTI))){} //Check BCNTI. + CLEAR_BIT(huart->Instance->LCRH, UART_LCRH_BRK); + + HAL_UART_Transmit(huart, (uint8_t*)"\x55", 1, 0); //Transmit sync field + + Lin_Id &= 0x3F; //Lin address check, 0-63. + Lin_P0 = (Lin_Id^(Lin_Id>>1)^(Lin_Id>>2)^(Lin_Id>>4))&0x01; //P0 = ID0^ID1^ID2^ID4 + Lin_P1 = (~((Lin_Id>>1)^(Lin_Id>>3)^(Lin_Id>>4)^(Lin_Id>>5)))&0x01; //P1 = ~(ID1^ID3^ID4^ID5) + Lin_Id = Lin_Id | (Lin_P0<<6) | (Lin_P1<<7); + + HAL_UART_Transmit(huart, &Lin_Id, 1, 0); //Transmit pid field + + if(Lin_Version==UART_LIN_V2DX) + Lin_Check_Sum = Lin_Id; //LIN 2.X check sum calc with PID. + + if(Size) + { + for(ucI=0;ucI0xFF) + Lin_Check_Sum = ((Lin_Check_Sum>>8)+Lin_Check_Sum)&0xFF; + } + Lin_Check_Sum = (~Lin_Check_Sum) & 0xFF; + + HAL_UART_Transmit(huart, pData, Size, 0); //Transmit data field + + HAL_UART_Transmit(huart, (uint8_t*)&Lin_Check_Sum, 1, 0); //Transmit Lin_Check_Sum field + } +} + +/************************************************************************ + * function : HAL_UART_LIN_Slave_Transmit + * Description: Uart lin slave transmit data + * input :none + * UART_HandleTypeDef *huart: Serial port number + * uint8_t Lin_Version: LIN version ,should be UART_LIN_V1D3 or UART_LIN_V2DX. + * uint8_t Lin_Id: LIN id + * uint8_t *pData: point to the transmit data buffer. + * uint8_t Size: Transmit buffer Size. + * return: none + ************************************************************************/ +void HAL_UART_LIN_Slave_Transmit(UART_HandleTypeDef *huart, uint8_t Lin_Version, uint8_t Lin_Id, uint8_t *pData, uint8_t Size) +{ + uint8_t Lin_P0,Lin_P1,ucI; + uint16_t Lin_Check_Sum = 0; + + if((Size>8)||(pData == 0)) + return; + + CLEAR_BIT(huart->Instance->IE, UART_EX_IE_LBDI);//disable LBDI int + huart->Instance->CR = 0x0101; //disable uart_rx + + if(Lin_Version==UART_LIN_V2DX) + Lin_Check_Sum = Lin_Id; //LIN 2.X check sum calc with PID. + + for(ucI=0;ucI0xFF) + Lin_Check_Sum = ((Lin_Check_Sum>>8)+Lin_Check_Sum)&0xFF; + } + Lin_Check_Sum = (~Lin_Check_Sum) & 0xFF; + + HAL_UART_Transmit(huart, pData, Size, 0); //Transmit data field + + HAL_UART_Transmit(huart, (uint8_t*)&Lin_Check_Sum, 1, 0); //Transmit Lin_Check_Sum field +} + +/************************************************************************ + * function : HAL_UART_LIN_Master_Receive + * Description: Uart lin master receive data + * input :none + * UART_HandleTypeDef *huart: Serial port number + * uint8_t Lin_Version: LIN version ,should be UART_LIN_V1D3 or UART_LIN_V2DX. + * uint8_t Lin_Id: LIN id + * uint8_t *pData: point to the data buffer. + * return: uint8_t RxSize + ************************************************************************/ +uint8_t HAL_UART_LIN_Master_Receive(UART_HandleTypeDef *huart, uint8_t Lin_Version, uint8_t Lin_Id, uint8_t *pData, uint32_t Timeout) +{ + uint8_t Lin_P0,Lin_P1,ucI,RxSize; + uint8_t Lin_Rx_Buf[16]; + uint8_t ucStatus; + uint16_t Lin_Check_Sum = 0; + uint32_t u32_Timeout; + + if(pData == 0) + return 0; + + huart->Instance->CR = 0x0201; //disable uart_tx + huart->Instance->ICR = 0xfff; //clear int + huart->Instance->LCRH = 0x70; //8 data bit,1 stop bit,0 verify bit,enable FIFO + huart->Instance->IFLS = 0x12; //FIFO send and receive number is 8 + huart->Instance->IE = 0x00; //Disable all interrupt + + HAL_UART_Receive(huart, Lin_Rx_Buf, sizeof(Lin_Rx_Buf), Timeout); + + if(Lin_Version==UART_LIN_V2DX) + Lin_Check_Sum = Lin_Id; //LIN 2.X check sum calc with PID. + + if(huart->lu32_RxCount) + { + for(ucI=0;ucI<(huart->lu32_RxCount-1);ucI++) + { + Lin_Check_Sum += Lin_Rx_Buf[ucI]; + if(Lin_Check_Sum>0xFF) + Lin_Check_Sum = ((Lin_Check_Sum>>8)+Lin_Check_Sum)&0xFF; + } + Lin_Check_Sum = (~Lin_Check_Sum) & 0xFF; + if((uint8_t)Lin_Check_Sum == Lin_Rx_Buf[ucI]) + { + RxSize = huart->lu32_RxCount; + memcpy(pData, (uint8_t*)Lin_Rx_Buf, RxSize); + } + else + RxSize = 0xFF; + } + else + RxSize = 0; + + return RxSize; +} + +/************************************************************************ + * function : HAL_UART_LIN_Slave_Receive + * Description: Uart lin slave receive head + * input :none + * UART_HandleTypeDef *huart: Serial port number + * uint8_t Lin_Version: LIN version ,should be UART_LIN_V1D3 or UART_LIN_V2DX. + * uint8_t *pData: point to the data buffer. + * return: uint8_t RxSize + ************************************************************************/ +uint8_t HAL_UART_LIN_Slave_Receive(UART_HandleTypeDef *huart, uint8_t Lin_Version, uint8_t *pData, uint32_t Timeout) +{ + uint8_t Lin_P0,Lin_P1,ucI,RxSize; + uint8_t Lin_Rx_Buf[16]; + uint8_t ucStatus; + uint16_t Lin_Check_Sum = 0; + uint32_t u32_Timeout; + + if(pData == 0) + return 0; + + huart->Instance->CR = 0x0201; //disable uart_tx + huart->Instance->ICR = 0xfff; //clear int + CLEAR_BIT(huart->Instance->IE, UART_EX_IE_LBDI); //Disable LBDI int + + if (Timeout == 0) + { + while(!READ_BIT(huart->Instance->RIS, UART_EX_RIS_LBDI)); + } + else + { + u32_Timeout = Timeout * 0xFF; + + while(!READ_BIT(huart->Instance->RIS, UART_EX_RIS_LBDI)) + { + if (u32_Timeout-- == 0) + { + return 0; + } + } + } + CLEAR_BIT(huart->Instance->RIS, UART_EX_RIS_LBDI); + + huart->Instance->LCRH = 0x70; //8 data bit,1 stop bit,0 verify bit,enable FIFO + huart->Instance->IFLS = 0x12; //FIFO send and receive number is 8 + huart->Instance->IE = 0x00; //Disable all interrupt + + HAL_UART_Receive(huart, Lin_Rx_Buf, sizeof(Lin_Rx_Buf), Timeout); //waitting rx completed. + + if(huart->lu32_RxCount > 3) + { + if(Lin_Version==UART_LIN_V2DX) + Lin_Check_Sum = Lin_Rx_Buf[2]; //LIN 2.X check sum calc with PID. + + if(huart->lu32_RxCount) + { + for(ucI=3;ucI<(huart->lu32_RxCount-1);ucI++) + { + Lin_Check_Sum += Lin_Rx_Buf[ucI]; + if(Lin_Check_Sum>0xFF) + Lin_Check_Sum = ((Lin_Check_Sum>>8)+Lin_Check_Sum)&0xFF; + } + Lin_Check_Sum = (~Lin_Check_Sum) & 0xFF; + if((uint8_t)Lin_Check_Sum == Lin_Rx_Buf[ucI]) + { + RxSize = huart->lu32_RxCount; + memcpy(pData, (uint8_t*)Lin_Rx_Buf, RxSize); + } + else + RxSize = 0xFF; + } + } + else if(huart->lu32_RxCount<=3) + { + RxSize = huart->lu32_RxCount; + memcpy(pData, (uint8_t*)Lin_Rx_Buf, RxSize); + } + else + RxSize = 0; + + return RxSize; +} diff --git a/bsp/acm32f4xx-nucleo/libraries/HAL_Driver/Src/HAL_WDT.c b/bsp/acm32f4xx-nucleo/libraries/HAL_Driver/Src/HAL_WDT.c new file mode 100644 index 0000000000..f0d23007dc --- /dev/null +++ b/bsp/acm32f4xx-nucleo/libraries/HAL_Driver/Src/HAL_WDT.c @@ -0,0 +1,110 @@ +/*********************************************************************** + * Filename : HAL_WDT.c + * Description : HAL WDT driver source file + * Author(s) : CWT + * version : V1.0 + * Modify date : 2020-04-17 + ***********************************************************************/ +#include "ACM32Fxx_HAL.h" + +/************************************************************************ + * function : HAL_WDT_Feed + * Description: WDT feed. + * input : + * none + * return: none + ************************************************************************/ +void HAL_WDT_Feed(WDT_HandleTypeDef* hwdt) +{ + hwdt->Instance->FEED = 0xAA55A55A; +} +/************************************************************************ + * function : HAL_WDT_IRQHandler + * Description: WDT interrupt service routine. + * input : + * none + * return: none + ************************************************************************/ +void HAL_WDT_IRQHandler(WDT_HandleTypeDef* hwdt) +{ + volatile uint32_t wdt_ris = 0; + wdt_ris = hwdt->Instance->RIS; + HAL_WDT_Feed(hwdt); + NVIC_ClearPendingIRQ(WDT_IRQn); +} + +/************************************************************************ + * function : HAL_WDT_Init + * Description: WDT initiation. + * input : + * pinit initiation parameters + * return: none + ************************************************************************/ +void HAL_WDT_Init(WDT_HandleTypeDef* hwdt) +{ + System_Module_Enable(EN_WDT); + System_Delay(1); + System_Enable_Disable_RTC_Domain_Access(FUNC_ENABLE); + System_Enable_Disable_Reset(RESET_ENABLE_SOURCE_WDT, FUNC_ENABLE); + + hwdt->Instance->LOAD = hwdt->Init.WDTLoad; + hwdt->Instance->CTRL = (hwdt->Instance->CTRL & ~0x47) | (hwdt->Init.WDTDivisor) | (hwdt->Init.WDTMode << 6); + + if (WDT_MODE_INT == hwdt->Init.WDTMode) + { + hwdt->Instance->INTCLRTIME = hwdt->Init.WDTINTCLRTIME; + HAL_WDT_Int_Enable(hwdt); + } +} + +/************************************************************************ + * function : HAL_WDT_Start + * Description: WDT start + * input : none + * + * return: none + ************************************************************************/ +void HAL_WDT_Start(WDT_HandleTypeDef* hwdt) +{ + hwdt->Instance->CTRL |= WDT_ENABLE; +} + +/************************************************************************ + * function : WDT_Stop + * Description: WDT stop + * input : none + * + * return: none + ************************************************************************/ +void HAL_WDT_Stop(WDT_HandleTypeDef* hwdt) +{ + hwdt->Instance->CTRL &= WDT_DISABLE; +} + +/************************************************************************ + * function : WDT_Int_Enable + * Description: WDT int enable + * input : none + * + * return: none + ************************************************************************/ +void HAL_WDT_Int_Enable(WDT_HandleTypeDef* hwdt) +{ + hwdt->Instance->CTRL |= WDT_INT_ENABLE; + NVIC_ClearPendingIRQ(WDT_IRQn); + NVIC_EnableIRQ(WDT_IRQn); +} + +/************************************************************************ + * function : WDT_Int_Disable + * Description: WDT int disable + * input : none + * + * return: none + ************************************************************************/ +void HAL_WDT_Int_Disable(WDT_HandleTypeDef* hwdt) +{ + hwdt->Instance->CTRL &= WDT_INT_DISABLE; +} + + diff --git a/bsp/acm32f4xx-nucleo/libraries/SConscript b/bsp/acm32f4xx-nucleo/libraries/SConscript new file mode 100644 index 0000000000..a5d24ec76e --- /dev/null +++ b/bsp/acm32f4xx-nucleo/libraries/SConscript @@ -0,0 +1,35 @@ +import rtconfig +Import('RTT_ROOT') +from building import * + +# get current directory +cwd = GetCurrentDir() + +src = Split(""" +Device/System_ACM32F4.c +HAL_Driver/Src/HAL_EFlash.c +HAL_Driver/Src/HAL_DMA.c +HAL_Driver/Src/HAL_GPIO.c +HAL_Driver/Src/HAL_UART.c +HAL_Driver/Src/HAL_EXTI.c +""") + + +libpath = ['.', cwd + '/Device', cwd + '/HAL_Driver/Src'] +libs = ['System_Accelerate', 'HAL_EFlash_EX'] + +if rtconfig.CROSS_TOOL == 'gcc': + src += ['Device/Startup_ACM32F4_gcc.s'] +elif rtconfig.CROSS_TOOL == 'keil': + src += ['Device/Startup_ACM32F4.s'] +elif rtconfig.CROSS_TOOL == 'iar': + src += ['Device/Startup_ACM32F4_iar.s'] + +path = [cwd + '/HAL_Driver/Inc', + cwd + '/Device', + cwd + '/CMSIS'] + +group = DefineGroup('ACM32_HAL', src, depend = [''], CPPPATH = path, LIBS = libs, LIBPATH = libpath) + +Return('group') + diff --git a/bsp/acm32f4xx-nucleo/project.uvoptx b/bsp/acm32f4xx-nucleo/project.uvoptx new file mode 100644 index 0000000000..ab33c87161 --- /dev/null +++ b/bsp/acm32f4xx-nucleo/project.uvoptx @@ -0,0 +1,985 @@ + + + + 1.0 + +
### uVision Project, (C) Keil Software
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..\..\components\libc\compilers\armlibc\mem_std.c + mem_std.c + 0 + 0 + + + 8 + 49 + 1 + 0 + 0 + 0 + ..\..\components\libc\compilers\common\stdlib.c + stdlib.c + 0 + 0 + + + 8 + 50 + 1 + 0 + 0 + 0 + ..\..\components\libc\compilers\common\time.c + time.c + 0 + 0 + + + + diff --git a/bsp/acm32f4xx-nucleo/project.uvprojx b/bsp/acm32f4xx-nucleo/project.uvprojx new file mode 100644 index 0000000000..3fc340a646 --- /dev/null +++ b/bsp/acm32f4xx-nucleo/project.uvprojx @@ -0,0 +1,693 @@ + + + + 2.1 + +
### uVision Project, (C) Keil Software
+ + + + ACM32F4XX + 0x4 + ARM-ADS + 6150000::V6.15::ARMCLANG + 1 + + + ARMCM33_DSP_FP + ARM + ARM.CMSIS.5.7.0 + http://www.keil.com/pack/ + IRAM(0x20000000,0x00020000) IRAM2(0x20200000,0x00020000) IROM(0x00000000,0x00200000) IROM2(0x00200000,0x00200000) CPUTYPE("Cortex-M33") FPU3(SFPU) DSP CLOCK(12000000) ESEL ELITTLE + + + UL2V8M(-S0 -C0 -P0 -FD20000000 -FC1000) + 0 + $$Device:ARMCM33_DSP_FP$Device\ARM\ARMCM33\Include\ARMCM33_DSP_FP.h + + + + + + + + + + + 0 + 0 + + + + + + + 0 + 0 + 0 + 0 + 1 + + .\build\keil\ + ACM32F4XX + 1 + 0 + 1 + 1 + 1 + .\build\keil\ + 1 + 0 + 0 + + 0 + 0 + + + 0 + 0 + 0 + 0 + + + 0 + 0 + + + 0 + 0 + 0 + 0 + + + 1 + 0 + fromelf.exe --bin --output ./build/ACM32F4.bin ./build/ACM32F4.axf + + 0 + 0 + 0 + 0 + + 0 + + + + 0 + 0 + 0 + 0 + 0 + 1 + 0 + 0 + 0 + 0 + 3 + + + 1 + + + + + + + SARMV8M.DLL + -MPU + TCM.DLL + -pCM33 + + + + 1 + 0 + 0 + 0 + 16 + + + + + 1 + 0 + 0 + 0 + 1 + 4102 + + 1 + BIN\UL2V8M.DLL + "" () + + + + + 0 + + + + 0 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 0 + 1 + 1 + 0 + 1 + 1 + 0 + 0 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 0 + 0 + "Cortex-M33" + + 0 + 0 + 0 + 1 + 1 + 0 + 0 + 2 + 0 + 0 + 1 + 1 + 8 + 1 + 1 + 0 + 0 + 3 + 4 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 1 + 0 + 0 + 0 + 0 + 1 + 0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x20000000 + 0x20000 + + + 1 + 0x0 + 0x200000 + + + 0 + 0x0 + 0x0 + + + 1 + 0x0 + 0x0 + + + 1 + 0x0 + 0x0 + + + 1 + 0x0 + 0x0 + + + 1 + 0x0 + 0x200000 + + + 1 + 0x200000 + 0x200000 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x20000000 + 0x20000 + + + 0 + 0x20200000 + 0x20000 + + + + + + 1 + 2 + 0 + 0 + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 3 + 3 + 1 + 1 + 0 + 0 + 0 + + + RT_USING_ARM_LIBC, __RTTHREAD__, __CLK_TCK=RT_TICK_PER_SECOND + + libraries\HAL_Driver\Inc;libraries\Device;libraries\CMSIS;applications;.;..\..\libcpu\arm\common;..\..\libcpu\arm\cortex-m33;..\..\components\drivers\include;..\..\components\drivers\include;..\..\components\drivers\include;drivers;..\..\components\finsh;.;..\..\include;..\..\components\libc\compilers\armlibc;..\..\components\libc\compilers\common;..\..\components\libc\compilers\common\nogcc;..\..\examples\utest\testcases\kernel + + + + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 4 + + + + + + + + + 1 + 0 + 0 + 0 + 1 + 0 + 0x00000000 + 0x20000000 + + + + + + + + + + + + + ACM32_HAL + + + HAL_UART.c + 1 + libraries\HAL_Driver\Src\HAL_UART.c + + + HAL_EXTI.c + 1 + libraries\HAL_Driver\Src\HAL_EXTI.c + + + HAL_DMA.c + 1 + libraries\HAL_Driver\Src\HAL_DMA.c + + + Startup_ACM32F4.s + 2 + libraries\Device\Startup_ACM32F4.s + + + System_ACM32F4.c + 1 + libraries\Device\System_ACM32F4.c + + + HAL_GPIO.c + 1 + libraries\HAL_Driver\Src\HAL_GPIO.c + + + HAL_EFlash.c + 1 + libraries\HAL_Driver\Src\HAL_EFlash.c + + + System_Accelerate.lib + 4 + libraries\Device\System_Accelerate.lib + + + HAL_EFlash_EX.lib + 4 + libraries\HAL_Driver\Src\HAL_EFlash_EX.lib + + + + + Applications + + + main.c + 1 + applications\main.c + + + + + CPU + + + backtrace.c + 1 + ..\..\libcpu\arm\common\backtrace.c + + + showmem.c + 1 + ..\..\libcpu\arm\common\showmem.c + + + div0.c + 1 + ..\..\libcpu\arm\common\div0.c + + + syscall_rvds.S + 2 + ..\..\libcpu\arm\cortex-m33\syscall_rvds.S + + + context_rvds.S + 2 + ..\..\libcpu\arm\cortex-m33\context_rvds.S + + + trustzone.c + 1 + ..\..\libcpu\arm\cortex-m33\trustzone.c + + + cpuport.c + 1 + ..\..\libcpu\arm\cortex-m33\cpuport.c + + + + + DeviceDrivers + + + pin.c + 1 + ..\..\components\drivers\misc\pin.c + + + serial.c + 1 + ..\..\components\drivers\serial\serial.c + + + pipe.c + 1 + ..\..\components\drivers\src\pipe.c + + + ringbuffer.c + 1 + ..\..\components\drivers\src\ringbuffer.c + + + ringblk_buf.c + 1 + ..\..\components\drivers\src\ringblk_buf.c + + + waitqueue.c + 1 + ..\..\components\drivers\src\waitqueue.c + + + dataqueue.c + 1 + ..\..\components\drivers\src\dataqueue.c + + + workqueue.c + 1 + ..\..\components\drivers\src\workqueue.c + + + completion.c + 1 + ..\..\components\drivers\src\completion.c + + + + + Drivers + + + drv_gpio.c + 1 + drivers\drv_gpio.c + + + board.c + 1 + drivers\board.c + + + drv_uart.c + 1 + drivers\drv_uart.c + + + + + Finsh + + + shell.c + 1 + ..\..\components\finsh\shell.c + + + msh.c + 1 + ..\..\components\finsh\msh.c + + + cmd.c + 1 + ..\..\components\finsh\cmd.c + + + + + Kernel + + + mem.c + 1 + ..\..\src\mem.c + + + idle.c + 1 + ..\..\src\idle.c + + + irq.c + 1 + ..\..\src\irq.c + + + scheduler.c + 1 + ..\..\src\scheduler.c + + + mempool.c + 1 + ..\..\src\mempool.c + + + ipc.c + 1 + ..\..\src\ipc.c + + + clock.c + 1 + ..\..\src\clock.c + + + device.c + 1 + ..\..\src\device.c + + + object.c + 1 + ..\..\src\object.c + + + kservice.c + 1 + ..\..\src\kservice.c + + + thread.c + 1 + ..\..\src\thread.c + + + timer.c + 1 + ..\..\src\timer.c + + + components.c + 1 + ..\..\src\components.c + + + + + libc + + + libc.c + 1 + ..\..\components\libc\compilers\armlibc\libc.c + + + syscalls.c + 1 + ..\..\components\libc\compilers\armlibc\syscalls.c + + + mem_std.c + 1 + ..\..\components\libc\compilers\armlibc\mem_std.c + + + stdlib.c + 1 + ..\..\components\libc\compilers\common\stdlib.c + + + time.c + 1 + ..\..\components\libc\compilers\common\time.c + + + + + + + + + + + + + + + + + <Project Info> + 0 + 1 + + + + + diff --git a/bsp/acm32f4xx-nucleo/rtconfig.h b/bsp/acm32f4xx-nucleo/rtconfig.h new file mode 100644 index 0000000000..210adaa714 --- /dev/null +++ b/bsp/acm32f4xx-nucleo/rtconfig.h @@ -0,0 +1,215 @@ +#ifndef RT_CONFIG_H__ +#define RT_CONFIG_H__ + +/* Automatically generated file; DO NOT EDIT. */ +/* RT-Thread Project Configuration */ + +/* RT-Thread Kernel */ + +#define RT_NAME_MAX 8 +#define RT_ALIGN_SIZE 4 +#define RT_THREAD_PRIORITY_32 +#define RT_THREAD_PRIORITY_MAX 32 +#define RT_TICK_PER_SECOND 100 +#define RT_USING_OVERFLOW_CHECK +#define RT_USING_HOOK +#define RT_USING_IDLE_HOOK +#define RT_IDLE_HOOK_LIST_SIZE 4 +#define IDLE_THREAD_STACK_SIZE 256 +#define RT_USING_TIMER_SOFT +#define RT_TIMER_THREAD_PRIO 4 +#define RT_TIMER_THREAD_STACK_SIZE 512 + +/* kservice optimization */ + +#define RT_DEBUG + +/* Inter-Thread communication */ + +#define RT_USING_SEMAPHORE +#define RT_USING_MUTEX +#define RT_USING_EVENT +#define RT_USING_MAILBOX +#define RT_USING_MESSAGEQUEUE + +/* Memory Management */ + +#define RT_USING_MEMPOOL +#define RT_USING_SMALL_MEM +#define RT_USING_HEAP + +/* Kernel Device Object */ + +#define RT_USING_DEVICE +#define RT_USING_DEVICE_OPS +#define RT_USING_CONSOLE +#define RT_CONSOLEBUF_SIZE 128 +#define RT_CONSOLE_DEVICE_NAME "uart1" +#define RT_VER_NUM 0x40004 + +/* RT-Thread Components */ + +#define RT_USING_COMPONENTS_INIT +#define RT_USING_USER_MAIN +#define RT_MAIN_THREAD_STACK_SIZE 2048 +#define RT_MAIN_THREAD_PRIORITY 10 + +/* C++ features */ + + +/* Command shell */ + +#define RT_USING_FINSH +#define RT_USING_MSH +#define FINSH_USING_MSH +#define FINSH_THREAD_NAME "tshell" +#define FINSH_THREAD_PRIORITY 20 +#define FINSH_THREAD_STACK_SIZE 4096 +#define FINSH_USING_HISTORY +#define FINSH_HISTORY_LINES 5 +#define FINSH_USING_SYMTAB +#define FINSH_CMD_SIZE 80 +#define MSH_USING_BUILT_IN_COMMANDS +#define FINSH_USING_DESCRIPTION +#define FINSH_ARG_MAX 10 + +/* Device virtual file system */ + + +/* Device Drivers */ + +#define RT_USING_DEVICE_IPC +#define RT_PIPE_BUFSZ 512 +#define RT_USING_SERIAL +#define RT_USING_SERIAL_V1 +#define RT_SERIAL_USING_DMA +#define RT_SERIAL_RB_BUFSZ 64 +#define RT_USING_PIN + +/* Using USB */ + + +/* POSIX layer and C standard library */ + +#define RT_USING_LIBC +#define RT_LIBC_DEFAULT_TIMEZONE 8 + +/* Network */ + +/* Socket abstraction layer */ + + +/* Network interface device */ + + +/* light weight TCP/IP stack */ + + +/* AT commands */ + + +/* VBUS(Virtual Software BUS) */ + + +/* Utilities */ + + +/* RT-Thread Utestcases */ + + +/* RT-Thread online packages */ + +/* IoT - internet of things */ + + +/* Wi-Fi */ + +/* Marvell WiFi */ + + +/* Wiced WiFi */ + + +/* IoT Cloud */ + + +/* security packages */ + + +/* language packages */ + + +/* multimedia packages */ + + +/* tools packages */ + + +/* system packages */ + + +/* peripheral libraries and drivers */ + + +/* miscellaneous packages */ + + +/* samples: kernel and components samples */ + + +/* Hardware Drivers Config */ + +#define SOC_ACM32F403RET7 + +/* ACM32F403RET7 */ + +#define SOC_SRAM_START_ADDR 0x20000000 +#define SOC_SRAM_SIZE 0xC0 +#define SOC_FLASH_START_ADDR 0x00000000 +#define SOC_FLASH_SIZE 0x8000 + +/* Onboard Peripheral Drivers */ + +/* On-chip Peripheral Drivers */ + +/* Hardware GPIO */ + +#define BSP_USING_GPIO1 +#define BSP_USING_GPIO2 +#define BSP_USING_GPIO3 + +/* Hardware UART */ + +#define BSP_USING_UART1 +#define BSP_USING_UART2 +#define BSP_UART2_RX_USING_DMA +#define BSP_UART2_TX_USING_DMA +#define BSP_USING_UART3 +#define BSP_UART3_RX_USING_DMA +#define BSP_UART3_TX_USING_DMA +#define BSP_USING_UART4 +#define BSP_UART4_RX_USING_DMA +#define BSP_UART4_TX_USING_DMA + +/* Hardware I2C */ + + +/* Hardware CAN */ + + +/* Hardware TIMER */ + + +/* Hardware WDT */ + + +/* Hardware SPI */ + + +/* Hardware CRYPTO */ + + +/* Board extended module Drivers */ + + +#endif diff --git a/bsp/acm32f4xx-nucleo/rtconfig.py b/bsp/acm32f4xx-nucleo/rtconfig.py new file mode 100644 index 0000000000..589422785b --- /dev/null +++ b/bsp/acm32f4xx-nucleo/rtconfig.py @@ -0,0 +1,151 @@ +import os + +# toolchains options +ARCH='arm' +CPU='cortex-m33' +CROSS_TOOL='gcc' + +# bsp lib config +BSP_LIBRARY_TYPE = None + +if os.getenv('RTT_CC'): + CROSS_TOOL = os.getenv('RTT_CC') +if os.getenv('RTT_ROOT'): + RTT_ROOT = os.getenv('RTT_ROOT') + +# cross_tool provides the cross compiler +# EXEC_PATH is the compiler execute path, for example, CodeSourcery, Keil MDK, IAR + +if CROSS_TOOL == 'gcc': + PLATFORM = 'gcc' + EXEC_PATH = r'/opt/gcc-arm-none-eabi-6_2-2016q4/bin' +elif CROSS_TOOL == 'keil': + PLATFORM = 'armcc' + EXEC_PATH = r'D:/Keil_v5' +elif CROSS_TOOL == 'iar': + PLATFORM = 'iar' + EXEC_PATH = r'D:/Program Files (x86)/IAR Systems/Embedded Workbench 8.2' + +if os.getenv('RTT_EXEC_PATH'): + EXEC_PATH = os.getenv('RTT_EXEC_PATH') + +BUILD = 'debug' +#BUILD = 'release' + +if PLATFORM == 'gcc': + # toolchains + PREFIX = 'arm-none-eabi-' + CC = PREFIX + 'gcc' + AS = PREFIX + 'gcc' + AR = PREFIX + 'ar' + CXX = PREFIX + 'g++' + LINK = PREFIX + 'gcc' + TARGET_EXT = 'elf' + SIZE = PREFIX + 'size' + OBJDUMP = PREFIX + 'objdump' + OBJCPY = PREFIX + 'objcopy' + + DEVICE = ' -mcpu=' + CPU + ' -mthumb -mfpu=fpv5-sp-d16 -mfloat-abi=hard -ffunction-sections -fdata-sections' + CFLAGS = DEVICE + AFLAGS = ' -c' + DEVICE + ' -x assembler-with-cpp -Wa,-mimplicit-it=thumb ' + LFLAGS = DEVICE + ' -Wl,--gc-sections,-Map=rtthread.map,-cref,-u,Reset_Handler -T drivers/linker_scripts/link.lds' + + CPATH = '' + LPATH = '' + + if BUILD == 'debug': + CFLAGS += ' -O0 -gdwarf-2 -g' + AFLAGS += ' -gdwarf-2' + else: + CFLAGS += ' -O2' + + CXXFLAGS = CFLAGS + + POST_ACTION = OBJCPY + ' -O binary $TARGET rtthread.bin\n' + SIZE + ' $TARGET \n' + +elif PLATFORM == 'armcc': + # toolchains + CC = 'armclang' + AS = 'armasm' + AR = 'armar' + LINK = 'armlink' + TARGET_EXT = 'axf' + + DEVICE = ' --cpu ' + CPU + CFLAGS = ' -xc -std=c99 --target=arm-arm-none-eabi -mcpu=cortex-m33 -mfpu=fpv5-sp-d16 -mfloat-abi=hard -c' + CFLAGS += ' -fno-rtti -funsigned-char -fshort-enums -fshort-wchar -D__MICROLIB -mlittle-endian -ffunction-sections' + + AFLAGS = ' --cpu=Cortex-M33 --fpu=FPv5-SP --li --pd "__MICROLIB SETA 1" --pd "__UVISION_VERSION SETA 531" --pd "ARMCM33_DSP_FP SETA 1"' + + LFLAGS = ' --cpu=Cortex-M33 --info sizes --info totals --info unused --info veneers --list ./build/ACM32F4.map --scatter ./build/ACM32F4.sct' + LFLAGS += ' --library_type=microlib --strict' + LFLAGS += ' --summary_stderr --info summarysizes --map --load_addr_map_info --xref --callgraph --symbols' + + EXEC_PATH += '/ARM/ARMCLANG/bin' + + if BUILD == 'debug': + CFLAGS += ' -gdwarf-3 -O0' + AFLAGS += ' -g' + else: + CFLAGS += ' -gdwarf-3 -O1' + + POST_ACTION = 'fromelf --bin $TARGET --output rtthread.bin \nfromelf -z $TARGET' +elif PLATFORM == 'iar': + # toolchains + CC = 'iccarm' + CXX = 'iccarm' + AS = 'iasmarm' + AR = 'iarchive' + LINK = 'ilinkarm' + TARGET_EXT = 'out' + + DEVICE = '-Dewarm' + + CFLAGS = DEVICE + CFLAGS += ' --diag_suppress Pa050' + CFLAGS += ' --no_cse' + CFLAGS += ' --no_unroll' + CFLAGS += ' --no_inline' + CFLAGS += ' --no_code_motion' + CFLAGS += ' --no_tbaa' + CFLAGS += ' --no_clustering' + CFLAGS += ' --no_scheduling' + CFLAGS += ' --debug' + CFLAGS += ' --endian=little' + CFLAGS += ' --cpu=' + CPU + CFLAGS += ' -e' + CFLAGS += ' --fpu=VFPv4_sp' + CFLAGS += ' --dlib_config "' + EXEC_PATH + '/arm/INC/c/DLib_Config_Normal.h"' + CFLAGS += ' --silent' + + AFLAGS = DEVICE + AFLAGS += ' -s+' + AFLAGS += ' -w+' + AFLAGS += ' -r' + AFLAGS += ' --cpu ' + CPU + AFLAGS += ' --fpu VFPv4_sp' + AFLAGS += ' -S' + + if BUILD == 'debug': + CFLAGS += ' --debug' + CFLAGS += ' -On' + else: + CFLAGS += ' -Oh' + + CXXFLAGS = CFLAGS + LFLAGS = ' --config "drivers/linker_scripts/link.icf"' + LFLAGS += ' --entry __iar_program_start' + + + CXXFLAGS = CFLAGS + + EXEC_PATH = EXEC_PATH + '/arm/bin/' + POST_ACTION = 'ielftool --bin $TARGET rtthread.bin' + +def dist_handle(BSP_ROOT, dist_dir): + import sys + cwd_path = os.getcwd() + sys.path.append(os.path.join(os.path.dirname(BSP_ROOT), 'tools')) + from sdk_dist import dist_do_building + dist_do_building(BSP_ROOT, dist_dir) + diff --git a/bsp/acm32f4xx-nucleo/template.uvoptx b/bsp/acm32f4xx-nucleo/template.uvoptx new file mode 100644 index 0000000000..6668d384aa --- /dev/null +++ b/bsp/acm32f4xx-nucleo/template.uvoptx @@ -0,0 +1,321 @@ + + + + 1.0 + +
### uVision Project, (C) Keil Software
+ + + *.c + *.s*; *.src; *.a* + *.obj; *.o + *.lib + *.txt; *.h; *.inc; *.md + *.plm + *.cpp + 0 + + + + 0 + 0 + + + + ACM32F4XX + 0x4 + ARM-ADS + + 12000000 + + 1 + 1 + 0 + 1 + 0 + + + 1 + 65535 + 0 + 0 + 0 + + + 79 + 66 + 8 + .\build\keil\ + + + 1 + 1 + 1 + 0 + 1 + 1 + 0 + 1 + 0 + 0 + 0 + 0 + + + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 0 + 0 + + + 1 + 0 + 1 + + 7 + + 0 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 0 + 1 + 1 + 1 + 1 + 0 + 0 + 1 + 0 + 0 + 14 + + + + + + + + + + + BIN\CMSIS_AGDI_V8M.DLL + + + + 0 + CMSIS_AGDI_V8M + -X"CMSIS-DAP AISINOCHIP V1.0" -UCMSIS-DAP AISINOCHIP V1.0 -O206 -S10 -C0 -P00000000 -N00("ARM CoreSight SW-DP") -D00(1BE12AEB) -L00(0) -TO65554 -TC10000000 -TT10000000 -TP20 -TDS8007 -TDT0 -TDC1F -TIEFFFFFFFF -TIP8 -FO7 -FD20000000 -FC1000 -FN1 -FF0ACM32F4_eflash -FS00 -FL080000 + + + 0 + UL2V8M + -UV0VVV123 -O206 -S0 -C0 -P00 -N00("ARM CoreSight SW-DP") -D00(1BE12AEB) -L00(0) -TO65554 -TC10000000 -TT10000000 -TP21 -TDS8007 -TDT0 -TDC1F -TIEFFFFFFFF -TIP8 -FO7 -FD20000000 -FC1000 -FN1 -FF0ACM32F4_eflash -FS00 -FL080000 + + + 0 + DLGTARM + (6010=-1,-1,-1,-1,0)(6018=-1,-1,-1,-1,0)(6019=-1,-1,-1,-1,0)(6008=-1,-1,-1,-1,0)(6009=-1,-1,-1,-1,0)(6014=-1,-1,-1,-1,0)(6015=-1,-1,-1,-1,0)(6003=-1,-1,-1,-1,0)(6000=-1,-1,-1,-1,0) + + + 0 + ARMDBGFLAGS + + + + 0 + DLGUARM + + + + + + 0 + 0 + 69 + 1 +
10834
+ 0 + 0 + 0 + 0 + 0 + 1 + Z:\Aisinochip\rt-thread\bsp\RT_Thread_v3.13\bsp\uart.c + + \\ACM32F4\../RT_Thread_v3.13/bsp/uart.c\69 + + + 1 + 0 + 140 + 1 +
21958
+ 0 + 0 + 0 + 0 + 0 + 1 + Z:\Aisinochip\rt-thread\bsp\RT_Thread_v3.13\components\finsh\shell.c + + \\ACM32F4\../RT_Thread_v3.13/components/finsh/shell.c\140 + + + + + 0 + 1 + gu32_DataBackup + + + 1 + 1 + gu8_EncrptionData + + + 2 + 1 + lp32_Data + + + 3 + 1 + str_GPIOAB + + + 4 + 1 + str_SCU + + + 5 + 1 + gu32_GPIOCD + + + 6 + 1 + gu32_GPIOAB + + + 7 + 1 + gu8_TxBuffer + + + 8 + 1 + UART1_Handle + + + 9 + 1 + gu8_RxBuffer + + + 10 + 1 + DMA1 + + + 11 + 1 + gu32_APBClock,0x0A + + + 12 + 1 + gu32_SystemClock,0x0A + + + 13 + 1 + shell + + + + + 1 + 1 + shell + 0 + + + + + 2 + 1 + 0x40010800 + 0 + + + + + 3 + 1 + 0x10080800 + 0 + + + + 0 + + + 0 + 1 + 1 + 0 + 0 + 0 + 0 + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + + + + 0 + 0 + 0 + + + + + + + + + + + + diff --git a/bsp/acm32f4xx-nucleo/template.uvprojx b/bsp/acm32f4xx-nucleo/template.uvprojx new file mode 100644 index 0000000000..f7bcb79435 --- /dev/null +++ b/bsp/acm32f4xx-nucleo/template.uvprojx @@ -0,0 +1,401 @@ + + + + 2.1 + +
### uVision Project, (C) Keil Software
+ + + + ACM32F4XX + 0x4 + ARM-ADS + 6140000::V6.14::ARMCLANG + 1 + + + ARMCM33_DSP_FP + ARM + ARM.CMSIS.5.7.0 + http://www.keil.com/pack/ + IRAM(0x20000000,0x00020000) IRAM2(0x20200000,0x00020000) IROM(0x00000000,0x00200000) IROM2(0x00200000,0x00200000) CPUTYPE("Cortex-M33") FPU3(SFPU) DSP CLOCK(12000000) ESEL ELITTLE + + + UL2V8M(-S0 -C0 -P0 -FD20000000 -FC1000) + 0 + $$Device:ARMCM33_DSP_FP$Device\ARM\ARMCM33\Include\ARMCM33_DSP_FP.h + + + + + + + + + + + 0 + 0 + + + + + + + 0 + 0 + 0 + 0 + 1 + + .\build\keil\ + ACM32F4XX + 1 + 0 + 1 + 1 + 1 + .\build\keil\ + 1 + 0 + 0 + + 0 + 0 + + + 0 + 0 + 0 + 0 + + + 0 + 0 + + + 0 + 0 + 0 + 0 + + + 1 + 0 + fromelf.exe --bin --output ./build/ACM32F4.bin ./build/ACM32F4.axf + + 0 + 0 + 0 + 0 + + 0 + + + + 0 + 0 + 0 + 0 + 0 + 1 + 0 + 0 + 0 + 0 + 3 + + + 1 + + + + + + + SARMV8M.DLL + -MPU + TCM.DLL + -pCM33 + + + + 1 + 0 + 0 + 0 + 16 + + + + + 1 + 0 + 0 + 0 + 1 + 4102 + + 1 + BIN\UL2V8M.DLL + "" () + + + + + 0 + + + + 0 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 0 + 1 + 1 + 0 + 1 + 1 + 0 + 0 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 0 + 0 + "Cortex-M33" + + 0 + 0 + 0 + 1 + 1 + 0 + 0 + 2 + 0 + 0 + 1 + 1 + 8 + 1 + 1 + 0 + 0 + 3 + 4 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 1 + 0 + 0 + 0 + 0 + 1 + 0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x20000000 + 0x20000 + + + 1 + 0x0 + 0x200000 + + + 0 + 0x0 + 0x0 + + + 1 + 0x0 + 0x0 + + + 1 + 0x0 + 0x0 + + + 1 + 0x0 + 0x0 + + + 1 + 0x0 + 0x200000 + + + 1 + 0x200000 + 0x200000 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x20000000 + 0x20000 + + + 0 + 0x20200000 + 0x20000 + + + + + + 1 + 2 + 0 + 0 + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 3 + 3 + 1 + 1 + 0 + 0 + 0 + + + + + + + + + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 4 + + + + + + + + + 1 + 0 + 0 + 0 + 1 + 0 + 0x00000000 + 0x20000000 + + + + + + + + + + + + + + + + + + + + + + + <Project Info> + 0 + 1 + + + + + -- cgit v1.3.1 From 47d0508a74cc378a2e66a0e813a149abfbb3d77e Mon Sep 17 00:00:00 2001 From: yanmowudi Date: Thu, 30 Sep 2021 17:55:16 +0800 Subject: update lib --- bsp/swm320-lq100/.config | 387 +- bsp/swm320-lq100/Kconfig | 8 +- .../CMSIS/CoreSupport/arm_common_tables.h | 35 +- .../CMSIS/CoreSupport/arm_const_structs.h | 62 +- .../Libraries/CMSIS/CoreSupport/arm_math.h | 7465 ++++++++++---------- .../Libraries/CMSIS/CoreSupport/core_cm0.h | 741 +- .../Libraries/CMSIS/CoreSupport/core_cm0plus.h | 872 ++- .../Libraries/CMSIS/CoreSupport/core_cm3.h | 1936 +++-- .../Libraries/CMSIS/CoreSupport/core_cm4.h | 2157 +++--- .../Libraries/CMSIS/CoreSupport/core_cm7.h | 2794 ++++---- .../Libraries/CMSIS/CoreSupport/core_cmFunc.h | 328 +- .../Libraries/CMSIS/CoreSupport/core_cmInstr.h | 410 +- .../Libraries/CMSIS/CoreSupport/core_cmSimd.h | 895 ++- .../Libraries/CMSIS/DeviceSupport/SWM320.h | 1437 ++-- .../DeviceSupport/startup/arm/startup_SWM320.s | 174 +- .../DeviceSupport/startup/iar/startup_SWM320.s | 74 +- .../Libraries/CMSIS/DeviceSupport/system_SWM320.c | 146 +- .../Libraries/CMSIS/DeviceSupport/system_SWM320.h | 20 +- .../Libraries/SWM320_StdPeriph_Driver/SWM320_adc.c | 65 +- .../Libraries/SWM320_StdPeriph_Driver/SWM320_adc.h | 26 +- .../Libraries/SWM320_StdPeriph_Driver/SWM320_can.c | 272 +- .../Libraries/SWM320_StdPeriph_Driver/SWM320_can.h | 125 +- .../Libraries/SWM320_StdPeriph_Driver/SWM320_crc.c | 31 +- .../Libraries/SWM320_StdPeriph_Driver/SWM320_crc.h | 33 +- .../Libraries/SWM320_StdPeriph_Driver/SWM320_dma.c | 108 +- .../Libraries/SWM320_StdPeriph_Driver/SWM320_dma.h | 23 +- .../SWM320_StdPeriph_Driver/SWM320_exti.c | 110 +- .../SWM320_StdPeriph_Driver/SWM320_exti.h | 24 +- .../SWM320_StdPeriph_Driver/SWM320_flash.c | 118 +- .../SWM320_StdPeriph_Driver/SWM320_flash.h | 14 +- .../SWM320_StdPeriph_Driver/SWM320_gpio.c | 248 +- .../SWM320_StdPeriph_Driver/SWM320_gpio.h | 25 +- .../Libraries/SWM320_StdPeriph_Driver/SWM320_i2c.c | 131 +- .../Libraries/SWM320_StdPeriph_Driver/SWM320_i2c.h | 28 +- .../Libraries/SWM320_StdPeriph_Driver/SWM320_lcd.c | 228 +- .../Libraries/SWM320_StdPeriph_Driver/SWM320_lcd.h | 130 +- .../SWM320_StdPeriph_Driver/SWM320_norflash.c | 129 +- .../SWM320_StdPeriph_Driver/SWM320_norflash.h | 35 +- .../SWM320_StdPeriph_Driver/SWM320_port.c | 31 +- .../SWM320_StdPeriph_Driver/SWM320_port.h | 838 ++- .../Libraries/SWM320_StdPeriph_Driver/SWM320_pwm.c | 52 +- .../Libraries/SWM320_StdPeriph_Driver/SWM320_rtc.c | 318 +- .../Libraries/SWM320_StdPeriph_Driver/SWM320_rtc.h | 53 +- .../SWM320_StdPeriph_Driver/SWM320_sdio.c | 438 +- .../SWM320_StdPeriph_Driver/SWM320_sdio.h | 208 +- .../SWM320_StdPeriph_Driver/SWM320_sdram.c | 106 +- .../SWM320_StdPeriph_Driver/SWM320_sdram.h | 78 +- .../Libraries/SWM320_StdPeriph_Driver/SWM320_spi.c | 446 +- .../Libraries/SWM320_StdPeriph_Driver/SWM320_spi.h | 71 +- .../SWM320_StdPeriph_Driver/SWM320_sram.c | 56 + .../SWM320_StdPeriph_Driver/SWM320_sram.h | 29 + .../SWM320_StdPeriph_Driver/SWM320_timr.c | 218 +- .../SWM320_StdPeriph_Driver/SWM320_timr.h | 34 +- .../SWM320_StdPeriph_Driver/SWM320_uart.c | 422 +- .../SWM320_StdPeriph_Driver/SWM320_uart.h | 73 +- .../Libraries/SWM320_StdPeriph_Driver/SWM320_wdt.c | 95 +- .../Libraries/SWM320_StdPeriph_Driver/SWM320_wdt.h | 19 +- bsp/swm320-lq100/README.md | 50 +- bsp/swm320-lq100/SConscript | 5 +- bsp/swm320-lq100/SConstruct | 13 +- bsp/swm320-lq100/applications/main.c | 556 +- bsp/swm320-lq100/drivers/Kconfig | 413 +- bsp/swm320-lq100/drivers/SConscript | 66 +- bsp/swm320-lq100/drivers/board.c | 54 +- bsp/swm320-lq100/drivers/board.h | 43 +- bsp/swm320-lq100/drivers/drv_adc.c | 217 + bsp/swm320-lq100/drivers/drv_adc.h | 71 + bsp/swm320-lq100/drivers/drv_crypto.c | 226 + bsp/swm320-lq100/drivers/drv_crypto.h | 40 + bsp/swm320-lq100/drivers/drv_gpio.c | 755 +- bsp/swm320-lq100/drivers/drv_gpio.h | 25 +- bsp/swm320-lq100/drivers/drv_hwtimer.c | 386 +- bsp/swm320-lq100/drivers/drv_hwtimer.h | 91 +- bsp/swm320-lq100/drivers/drv_i2c.c | 70 - bsp/swm320-lq100/drivers/drv_i2c.h | 16 - bsp/swm320-lq100/drivers/drv_iwg.c | 77 - bsp/swm320-lq100/drivers/drv_iwg.h | 16 - bsp/swm320-lq100/drivers/drv_log.h | 27 + bsp/swm320-lq100/drivers/drv_nor_flash.c | 111 +- bsp/swm320-lq100/drivers/drv_nor_flash.h | 7 + bsp/swm320-lq100/drivers/drv_pwm.c | 309 +- bsp/swm320-lq100/drivers/drv_pwm.h | 154 +- bsp/swm320-lq100/drivers/drv_rtc.c | 210 +- bsp/swm320-lq100/drivers/drv_rtc.h | 9 +- bsp/swm320-lq100/drivers/drv_sdio.c | 664 ++ bsp/swm320-lq100/drivers/drv_sdio.h | 42 + bsp/swm320-lq100/drivers/drv_soft_i2c.c | 197 + bsp/swm320-lq100/drivers/drv_soft_i2c.h | 51 + bsp/swm320-lq100/drivers/drv_spi.c | 289 +- bsp/swm320-lq100/drivers/drv_spi.h | 71 +- bsp/swm320-lq100/drivers/drv_sram.c | 54 +- bsp/swm320-lq100/drivers/drv_sram.h | 8 + bsp/swm320-lq100/drivers/drv_uart.c | 316 +- bsp/swm320-lq100/drivers/drv_uart.h | 107 +- bsp/swm320-lq100/drivers/drv_wdt.c | 88 + bsp/swm320-lq100/drivers/drv_wdt.h | 31 + bsp/swm320-lq100/keilkill.bat | 37 + bsp/swm320-lq100/project.ewd | 20 +- bsp/swm320-lq100/project.ewp | 4520 ++++++------ bsp/swm320-lq100/project.eww | 20 +- bsp/swm320-lq100/project.uvopt | 162 + bsp/swm320-lq100/project.uvoptx | 808 ++- bsp/swm320-lq100/project.uvproj | 786 +++ bsp/swm320-lq100/project.uvprojx | 564 +- bsp/swm320-lq100/rtconfig.h | 74 +- bsp/swm320-lq100/rtconfig.py | 108 +- bsp/swm320-lq100/template.ewp | 4063 ++++++----- bsp/swm320-lq100/template.eww | 20 +- bsp/swm320-lq100/template.uvopt | 28 +- bsp/swm320-lq100/template.uvoptx | 18 +- bsp/swm320-lq100/template.uvproj | 407 ++ bsp/swm320-lq100/template.uvprojx | 25 +- 112 files changed, 24399 insertions(+), 18625 deletions(-) create mode 100644 bsp/swm320-lq100/Libraries/SWM320_StdPeriph_Driver/SWM320_sram.c create mode 100644 bsp/swm320-lq100/Libraries/SWM320_StdPeriph_Driver/SWM320_sram.h create mode 100644 bsp/swm320-lq100/drivers/drv_adc.c create mode 100644 bsp/swm320-lq100/drivers/drv_adc.h create mode 100644 bsp/swm320-lq100/drivers/drv_crypto.c create mode 100644 bsp/swm320-lq100/drivers/drv_crypto.h delete mode 100644 bsp/swm320-lq100/drivers/drv_i2c.c delete mode 100644 bsp/swm320-lq100/drivers/drv_i2c.h delete mode 100644 bsp/swm320-lq100/drivers/drv_iwg.c delete mode 100644 bsp/swm320-lq100/drivers/drv_iwg.h create mode 100644 bsp/swm320-lq100/drivers/drv_log.h create mode 100644 bsp/swm320-lq100/drivers/drv_sdio.c create mode 100644 bsp/swm320-lq100/drivers/drv_sdio.h create mode 100644 bsp/swm320-lq100/drivers/drv_soft_i2c.c create mode 100644 bsp/swm320-lq100/drivers/drv_soft_i2c.h create mode 100644 bsp/swm320-lq100/drivers/drv_wdt.c create mode 100644 bsp/swm320-lq100/drivers/drv_wdt.h create mode 100644 bsp/swm320-lq100/keilkill.bat create mode 100644 bsp/swm320-lq100/project.uvopt create mode 100644 bsp/swm320-lq100/project.uvproj create mode 100644 bsp/swm320-lq100/template.uvproj (limited to 'bsp') diff --git a/bsp/swm320-lq100/.config b/bsp/swm320-lq100/.config index 12a39ca43b..f5b76827e9 100644 --- a/bsp/swm320-lq100/.config +++ b/bsp/swm320-lq100/.config @@ -7,19 +7,27 @@ # RT-Thread Kernel # CONFIG_RT_NAME_MAX=8 +# CONFIG_RT_USING_ARCH_DATA_TYPE is not set # CONFIG_RT_USING_SMP is not set CONFIG_RT_ALIGN_SIZE=4 # CONFIG_RT_THREAD_PRIORITY_8 is not set CONFIG_RT_THREAD_PRIORITY_32=y # CONFIG_RT_THREAD_PRIORITY_256 is not set CONFIG_RT_THREAD_PRIORITY_MAX=32 -CONFIG_RT_TICK_PER_SECOND=100 +CONFIG_RT_TICK_PER_SECOND=1000 CONFIG_RT_USING_OVERFLOW_CHECK=y CONFIG_RT_USING_HOOK=y CONFIG_RT_USING_IDLE_HOOK=y CONFIG_RT_IDLE_HOOK_LIST_SIZE=4 CONFIG_IDLE_THREAD_STACK_SIZE=256 # CONFIG_RT_USING_TIMER_SOFT is not set + +# +# kservice optimization +# +# CONFIG_RT_KSERVICE_USING_STDLIB is not set +# CONFIG_RT_KSERVICE_USING_TINY_SIZE is not set +# CONFIG_RT_USING_ASM_MEMCPY is not set CONFIG_RT_DEBUG=y CONFIG_RT_DEBUG_COLOR=y # CONFIG_RT_DEBUG_INIT_CONFIG is not set @@ -48,10 +56,12 @@ CONFIG_RT_USING_MESSAGEQUEUE=y # CONFIG_RT_USING_MEMPOOL=y CONFIG_RT_USING_MEMHEAP=y +CONFIG_RT_USING_MEMHEAP_AUTO_BINDING=y # CONFIG_RT_USING_NOHEAP is not set -CONFIG_RT_USING_SMALL_MEM=y +# CONFIG_RT_USING_SMALL_MEM is not set # CONFIG_RT_USING_SLAB is not set -# CONFIG_RT_USING_MEMHEAP_AS_HEAP is not set +CONFIG_RT_USING_MEMHEAP_AS_HEAP=y +# CONFIG_RT_USING_USERHEAP is not set # CONFIG_RT_USING_MEMTRACE is not set CONFIG_RT_USING_HEAP=y @@ -64,7 +74,12 @@ CONFIG_RT_USING_DEVICE=y CONFIG_RT_USING_CONSOLE=y CONFIG_RT_CONSOLEBUF_SIZE=128 CONFIG_RT_CONSOLE_DEVICE_NAME="uart0" -CONFIG_RT_VER_NUM=0x40000 +# CONFIG_RT_PRINTF_LONGLONG is not set +CONFIG_RT_VER_NUM=0x40004 +CONFIG_ARCH_ARM=y +CONFIG_RT_USING_CPU_FFS=y +CONFIG_ARCH_ARM_CORTEX_M=y +CONFIG_ARCH_ARM_CORTEX_M4=y # CONFIG_ARCH_CPU_STACK_GROWS_UPWARD is not set # @@ -84,53 +99,67 @@ CONFIG_RT_MAIN_THREAD_PRIORITY=10 # Command shell # CONFIG_RT_USING_FINSH=y +CONFIG_RT_USING_MSH=y +CONFIG_FINSH_USING_MSH=y CONFIG_FINSH_THREAD_NAME="tshell" +CONFIG_FINSH_THREAD_PRIORITY=20 +CONFIG_FINSH_THREAD_STACK_SIZE=4096 CONFIG_FINSH_USING_HISTORY=y CONFIG_FINSH_HISTORY_LINES=5 CONFIG_FINSH_USING_SYMTAB=y +CONFIG_FINSH_CMD_SIZE=80 +CONFIG_MSH_USING_BUILT_IN_COMMANDS=y CONFIG_FINSH_USING_DESCRIPTION=y # CONFIG_FINSH_ECHO_DISABLE_DEFAULT is not set -CONFIG_FINSH_THREAD_PRIORITY=20 -CONFIG_FINSH_THREAD_STACK_SIZE=4096 -CONFIG_FINSH_CMD_SIZE=80 # CONFIG_FINSH_USING_AUTH is not set -CONFIG_FINSH_USING_MSH=y -CONFIG_FINSH_USING_MSH_DEFAULT=y -# CONFIG_FINSH_USING_MSH_ONLY is not set CONFIG_FINSH_ARG_MAX=10 # # Device virtual file system # # CONFIG_RT_USING_DFS is not set +# CONFIG_RT_DFS_ELM_USE_LFN_0 is not set +# CONFIG_RT_DFS_ELM_USE_LFN_1 is not set +# CONFIG_RT_DFS_ELM_USE_LFN_2 is not set +# CONFIG_RT_DFS_ELM_USE_LFN_3 is not set +# CONFIG_RT_DFS_ELM_LFN_UNICODE_0 is not set +# CONFIG_RT_DFS_ELM_LFN_UNICODE_1 is not set +# CONFIG_RT_DFS_ELM_LFN_UNICODE_2 is not set +# CONFIG_RT_DFS_ELM_LFN_UNICODE_3 is not set # # Device Drivers # CONFIG_RT_USING_DEVICE_IPC=y CONFIG_RT_PIPE_BUFSZ=512 +# CONFIG_RT_USING_SYSTEM_WORKQUEUE is not set CONFIG_RT_USING_SERIAL=y +CONFIG_RT_USING_SERIAL_V1=y +# CONFIG_RT_USING_SERIAL_V2 is not set # CONFIG_RT_SERIAL_USING_DMA is not set +CONFIG_RT_SERIAL_RB_BUFSZ=64 # CONFIG_RT_USING_CAN is not set -CONFIG_RT_USING_HWTIMER=y +# CONFIG_RT_USING_HWTIMER is not set # CONFIG_RT_USING_CPUTIME is not set # CONFIG_RT_USING_I2C is not set +# CONFIG_RT_USING_PHY is not set CONFIG_RT_USING_PIN=y # CONFIG_RT_USING_ADC is not set -CONFIG_RT_USING_PWM=y +# CONFIG_RT_USING_DAC is not set +# CONFIG_RT_USING_PWM is not set # CONFIG_RT_USING_MTD_NOR is not set # CONFIG_RT_USING_MTD_NAND is not set -# CONFIG_RT_USING_MTD is not set # CONFIG_RT_USING_PM is not set # CONFIG_RT_USING_RTC is not set # CONFIG_RT_USING_SDIO is not set # CONFIG_RT_USING_SPI is not set # CONFIG_RT_USING_WDT is not set # CONFIG_RT_USING_AUDIO is not set - -# -# Using WiFi -# +# CONFIG_RT_USING_SENSOR is not set +# CONFIG_RT_USING_TOUCH is not set +# CONFIG_RT_USING_HWCRYPTO is not set +# CONFIG_RT_USING_PULSE_ENCODER is not set +# CONFIG_RT_USING_INPUT_CAPTURE is not set # CONFIG_RT_USING_WIFI is not set # @@ -142,8 +171,11 @@ CONFIG_RT_USING_PWM=y # # POSIX layer and C standard library # -# CONFIG_RT_USING_LIBC is not set +CONFIG_RT_USING_LIBC=y # CONFIG_RT_USING_PTHREADS is not set +CONFIG_RT_LIBC_USING_TIME=y +# CONFIG_RT_USING_MODULE is not set +CONFIG_RT_LIBC_DEFAULT_TIMEZONE=8 # # Network @@ -155,14 +187,14 @@ CONFIG_RT_USING_PWM=y # CONFIG_RT_USING_SAL is not set # -# light weight TCP/IP stack +# Network interface device # -# CONFIG_RT_USING_LWIP is not set +# CONFIG_RT_USING_NETDEV is not set # -# Modbus master and slave stack +# light weight TCP/IP stack # -# CONFIG_RT_USING_MODBUS is not set +# CONFIG_RT_USING_LWIP is not set # # AT commands @@ -177,10 +209,16 @@ CONFIG_RT_USING_PWM=y # # Utilities # -# CONFIG_RT_USING_LOGTRACE is not set # CONFIG_RT_USING_RYM is not set # CONFIG_RT_USING_ULOG is not set # CONFIG_RT_USING_UTEST is not set +# CONFIG_RT_USING_RT_LINK is not set +# CONFIG_RT_USING_LWP is not set + +# +# RT-Thread Utestcases +# +# CONFIG_RT_USING_UTESTCASES is not set # # RT-Thread online packages @@ -189,13 +227,20 @@ CONFIG_RT_USING_PWM=y # # IoT - internet of things # +# CONFIG_PKG_USING_LORAWAN_DRIVER is not set # CONFIG_PKG_USING_PAHOMQTT is not set +# CONFIG_PKG_USING_UMQTT is not set # CONFIG_PKG_USING_WEBCLIENT is not set # CONFIG_PKG_USING_WEBNET is not set # CONFIG_PKG_USING_MONGOOSE is not set +# CONFIG_PKG_USING_MYMQTT is not set +# CONFIG_PKG_USING_KAWAII_MQTT is not set +# CONFIG_PKG_USING_BC28_MQTT is not set # CONFIG_PKG_USING_WEBTERMINAL is not set # CONFIG_PKG_USING_CJSON is not set # CONFIG_PKG_USING_JSMN is not set +# CONFIG_PKG_USING_LIBMODBUS is not set +# CONFIG_PKG_USING_FREEMODBUS is not set # CONFIG_PKG_USING_LJSON is not set # CONFIG_PKG_USING_EZXML is not set # CONFIG_PKG_USING_NANOPB is not set @@ -213,11 +258,16 @@ CONFIG_RT_USING_PWM=y # Wiced WiFi # # CONFIG_PKG_USING_WLAN_WICED is not set +# CONFIG_PKG_USING_RW007 is not set # CONFIG_PKG_USING_COAP is not set # CONFIG_PKG_USING_NOPOLL is not set # CONFIG_PKG_USING_NETUTILS is not set +# CONFIG_PKG_USING_CMUX is not set +# CONFIG_PKG_USING_PPP_DEVICE is not set # CONFIG_PKG_USING_AT_DEVICE is not set +# CONFIG_PKG_USING_ATSRV_SOCKET is not set # CONFIG_PKG_USING_WIZNET is not set +# CONFIG_PKG_USING_ZB_COORDINATOR is not set # # IoT Cloud @@ -226,7 +276,39 @@ CONFIG_RT_USING_PWM=y # CONFIG_PKG_USING_GAGENT_CLOUD is not set # CONFIG_PKG_USING_ALI_IOTKIT is not set # CONFIG_PKG_USING_AZURE is not set -# CONFIG_PKG_USING_TENCENT_IOTKIT is not set +# CONFIG_PKG_USING_TENCENT_IOT_EXPLORER is not set +# CONFIG_PKG_USING_JIOT-C-SDK is not set +# CONFIG_PKG_USING_UCLOUD_IOT_SDK is not set +# CONFIG_PKG_USING_JOYLINK is not set +# CONFIG_PKG_USING_NIMBLE is not set +# CONFIG_PKG_USING_OTA_DOWNLOADER is not set +# CONFIG_PKG_USING_IPMSG is not set +# CONFIG_PKG_USING_LSSDP is not set +# CONFIG_PKG_USING_AIRKISS_OPEN is not set +# CONFIG_PKG_USING_LIBRWS is not set +# CONFIG_PKG_USING_TCPSERVER is not set +# CONFIG_PKG_USING_PROTOBUF_C is not set +# CONFIG_PKG_USING_DLT645 is not set +# CONFIG_PKG_USING_QXWZ is not set +# CONFIG_PKG_USING_SMTP_CLIENT is not set +# CONFIG_PKG_USING_ABUP_FOTA is not set +# CONFIG_PKG_USING_LIBCURL2RTT is not set +# CONFIG_PKG_USING_CAPNP is not set +# CONFIG_PKG_USING_RT_CJSON_TOOLS is not set +# CONFIG_PKG_USING_AGILE_TELNET is not set +# CONFIG_PKG_USING_NMEALIB is not set +# CONFIG_PKG_USING_AGILE_JSMN is not set +# CONFIG_PKG_USING_PDULIB is not set +# CONFIG_PKG_USING_BTSTACK is not set +# CONFIG_PKG_USING_LORAWAN_ED_STACK is not set +# CONFIG_PKG_USING_WAYZ_IOTKIT is not set +# CONFIG_PKG_USING_MAVLINK is not set +# CONFIG_PKG_USING_RAPIDJSON is not set +# CONFIG_PKG_USING_BSAL is not set +# CONFIG_PKG_USING_AGILE_MODBUS is not set +# CONFIG_PKG_USING_AGILE_FTP is not set +# CONFIG_PKG_USING_EMBEDDEDPROTO is not set +# CONFIG_PKG_USING_RT_LINK_HW is not set # # security packages @@ -234,6 +316,8 @@ CONFIG_RT_USING_PWM=y # CONFIG_PKG_USING_MBEDTLS is not set # CONFIG_PKG_USING_libsodium is not set # CONFIG_PKG_USING_TINYCRYPT is not set +# CONFIG_PKG_USING_TFM is not set +# CONFIG_PKG_USING_YD_CRYPTO is not set # # language packages @@ -241,12 +325,23 @@ CONFIG_RT_USING_PWM=y # CONFIG_PKG_USING_LUA is not set # CONFIG_PKG_USING_JERRYSCRIPT is not set # CONFIG_PKG_USING_MICROPYTHON is not set +# CONFIG_PKG_USING_PIKASCRIPT is not set # # multimedia packages # # CONFIG_PKG_USING_OPENMV is not set # CONFIG_PKG_USING_MUPDF is not set +# CONFIG_PKG_USING_STEMWIN is not set +# CONFIG_PKG_USING_WAVPLAYER is not set +# CONFIG_PKG_USING_TJPGD is not set +# CONFIG_PKG_USING_PDFGEN is not set +# CONFIG_PKG_USING_HELIX is not set +# CONFIG_PKG_USING_AZUREGUIX is not set +# CONFIG_PKG_USING_TOUCHGFX2RTT is not set +# CONFIG_PKG_USING_NUEMWIN is not set +# CONFIG_PKG_USING_MP3PLAYER is not set +# CONFIG_PKG_USING_TINYJPEG is not set # # tools packages @@ -255,120 +350,262 @@ CONFIG_RT_USING_PWM=y # CONFIG_PKG_USING_EASYFLASH is not set # CONFIG_PKG_USING_EASYLOGGER is not set # CONFIG_PKG_USING_SYSTEMVIEW is not set +# CONFIG_PKG_USING_SEGGER_RTT is not set # CONFIG_PKG_USING_RDB is not set # CONFIG_PKG_USING_QRCODE is not set # CONFIG_PKG_USING_ULOG_EASYFLASH is not set +# CONFIG_PKG_USING_ULOG_FILE is not set +# CONFIG_PKG_USING_LOGMGR is not set +# CONFIG_PKG_USING_ADBD is not set +# CONFIG_PKG_USING_COREMARK is not set +# CONFIG_PKG_USING_DHRYSTONE is not set +# CONFIG_PKG_USING_MEMORYPERF is not set +# CONFIG_PKG_USING_NR_MICRO_SHELL is not set +# CONFIG_PKG_USING_CHINESE_FONT_LIBRARY is not set +# CONFIG_PKG_USING_LUNAR_CALENDAR is not set +# CONFIG_PKG_USING_BS8116A is not set +# CONFIG_PKG_USING_GPS_RMC is not set +# CONFIG_PKG_USING_URLENCODE is not set +# CONFIG_PKG_USING_UMCN is not set +# CONFIG_PKG_USING_LWRB2RTT is not set +# CONFIG_PKG_USING_CPU_USAGE is not set +# CONFIG_PKG_USING_GBK2UTF8 is not set +# CONFIG_PKG_USING_VCONSOLE is not set +# CONFIG_PKG_USING_KDB is not set +# CONFIG_PKG_USING_WAMR is not set +# CONFIG_PKG_USING_MICRO_XRCE_DDS_CLIENT is not set +# CONFIG_PKG_USING_LWLOG is not set +# CONFIG_PKG_USING_ANV_TRACE is not set +# CONFIG_PKG_USING_ANV_MEMLEAK is not set +# CONFIG_PKG_USING_ANV_TESTSUIT is not set +# CONFIG_PKG_USING_ANV_BENCH is not set +# CONFIG_PKG_USING_DEVMEM is not set +# CONFIG_PKG_USING_REGEX is not set +# CONFIG_PKG_USING_MEM_SANDBOX is not set +# CONFIG_PKG_USING_SOLAR_TERMS is not set +# CONFIG_PKG_USING_GAN_ZHI is not set # # system packages # + +# +# acceleration: Assembly language or algorithmic acceleration packages +# +# CONFIG_PKG_USING_RT_MEMCPY_CM is not set +# CONFIG_PKG_USING_QFPLIB_M0_FULL is not set +# CONFIG_PKG_USING_QFPLIB_M0_TINY is not set +# CONFIG_PKG_USING_QFPLIB_M3 is not set + +# +# Micrium: Micrium software products porting for RT-Thread +# +# CONFIG_PKG_USING_UCOSIII_WRAPPER is not set +# CONFIG_PKG_USING_UCOSII_WRAPPER is not set +# CONFIG_PKG_USING_UC_CRC is not set +# CONFIG_PKG_USING_UC_CLK is not set +# CONFIG_PKG_USING_UC_COMMON is not set +# CONFIG_PKG_USING_UC_MODBUS is not set # CONFIG_PKG_USING_GUIENGINE is not set +# CONFIG_PKG_USING_PERSIMMON is not set # CONFIG_PKG_USING_CAIRO is not set # CONFIG_PKG_USING_PIXMAN is not set -# CONFIG_PKG_USING_LWEXT4 is not set # CONFIG_PKG_USING_PARTITION is not set # CONFIG_PKG_USING_FAL is not set +# CONFIG_PKG_USING_FLASHDB is not set # CONFIG_PKG_USING_SQLITE is not set # CONFIG_PKG_USING_RTI is not set # CONFIG_PKG_USING_LITTLEVGL2RTT is not set # CONFIG_PKG_USING_CMSIS is not set # CONFIG_PKG_USING_DFS_YAFFS is not set # CONFIG_PKG_USING_LITTLEFS is not set +# CONFIG_PKG_USING_DFS_JFFS2 is not set +# CONFIG_PKG_USING_DFS_UFFS is not set +# CONFIG_PKG_USING_LWEXT4 is not set +# CONFIG_PKG_USING_THREAD_POOL is not set +# CONFIG_PKG_USING_ROBOTS is not set +# CONFIG_PKG_USING_EV is not set +# CONFIG_PKG_USING_SYSWATCH is not set +# CONFIG_PKG_USING_SYS_LOAD_MONITOR is not set +# CONFIG_PKG_USING_PLCCORE is not set +# CONFIG_PKG_USING_RAMDISK is not set +# CONFIG_PKG_USING_MININI is not set +# CONFIG_PKG_USING_QBOOT is not set +# CONFIG_PKG_USING_PPOOL is not set +# CONFIG_PKG_USING_OPENAMP is not set +# CONFIG_PKG_USING_RT_KPRINTF_THREADSAFE is not set +# CONFIG_PKG_USING_LPM is not set +# CONFIG_PKG_USING_TLSF is not set +# CONFIG_PKG_USING_EVENT_RECORDER is not set +# CONFIG_PKG_USING_ARM_2D is not set +# CONFIG_PKG_USING_WCWIDTH is not set # # peripheral libraries and drivers # +# CONFIG_PKG_USING_SENSORS_DRIVERS is not set # CONFIG_PKG_USING_REALTEK_AMEBA is not set # CONFIG_PKG_USING_SHT2X is not set -# CONFIG_PKG_USING_AHT10 is not set -# CONFIG_PKG_USING_AP3216C is not set +# CONFIG_PKG_USING_SHT3X is not set +# CONFIG_PKG_USING_AS7341 is not set # CONFIG_PKG_USING_STM32_SDIO is not set # CONFIG_PKG_USING_ICM20608 is not set # CONFIG_PKG_USING_U8G2 is not set # CONFIG_PKG_USING_BUTTON is not set -# CONFIG_PKG_USING_MPU6XXX is not set # CONFIG_PKG_USING_PCF8574 is not set +# CONFIG_PKG_USING_SX12XX is not set +# CONFIG_PKG_USING_SIGNAL_LED is not set +# CONFIG_PKG_USING_LEDBLINK is not set +# CONFIG_PKG_USING_LITTLED is not set +# CONFIG_PKG_USING_LKDGUI is not set +# CONFIG_PKG_USING_NRF5X_SDK is not set +# CONFIG_PKG_USING_NRFX is not set +# CONFIG_PKG_USING_WM_LIBRARIES is not set # CONFIG_PKG_USING_KENDRYTE_SDK is not set +# CONFIG_PKG_USING_INFRARED is not set +# CONFIG_PKG_USING_AGILE_BUTTON is not set +# CONFIG_PKG_USING_AGILE_LED is not set +# CONFIG_PKG_USING_AT24CXX is not set +# CONFIG_PKG_USING_MOTIONDRIVER2RTT is not set +# CONFIG_PKG_USING_AD7746 is not set +# CONFIG_PKG_USING_PCA9685 is not set +# CONFIG_PKG_USING_I2C_TOOLS is not set +# CONFIG_PKG_USING_NRF24L01 is not set +# CONFIG_PKG_USING_TOUCH_DRIVERS is not set +# CONFIG_PKG_USING_MAX17048 is not set +# CONFIG_PKG_USING_RPLIDAR is not set +# CONFIG_PKG_USING_AS608 is not set +# CONFIG_PKG_USING_RC522 is not set +# CONFIG_PKG_USING_WS2812B is not set +# CONFIG_PKG_USING_EMBARC_BSP is not set +# CONFIG_PKG_USING_EXTERN_RTC_DRIVERS is not set +# CONFIG_PKG_USING_MULTI_RTIMER is not set +# CONFIG_PKG_USING_MAX7219 is not set +# CONFIG_PKG_USING_BEEP is not set +# CONFIG_PKG_USING_EASYBLINK is not set +# CONFIG_PKG_USING_PMS_SERIES is not set +# CONFIG_PKG_USING_CAN_YMODEM is not set +# CONFIG_PKG_USING_LORA_RADIO_DRIVER is not set +# CONFIG_PKG_USING_QLED is not set +# CONFIG_PKG_USING_PAJ7620 is not set +# CONFIG_PKG_USING_AGILE_CONSOLE is not set +# CONFIG_PKG_USING_LD3320 is not set +# CONFIG_PKG_USING_WK2124 is not set +# CONFIG_PKG_USING_LY68L6400 is not set +# CONFIG_PKG_USING_DM9051 is not set +# CONFIG_PKG_USING_SSD1306 is not set +# CONFIG_PKG_USING_QKEY is not set +# CONFIG_PKG_USING_RS485 is not set +# CONFIG_PKG_USING_NES is not set +# CONFIG_PKG_USING_VIRTUAL_SENSOR is not set +# CONFIG_PKG_USING_VDEVICE is not set +# CONFIG_PKG_USING_SGM706 is not set +# CONFIG_PKG_USING_STM32WB55_SDK is not set +# CONFIG_PKG_USING_RDA58XX is not set +# CONFIG_PKG_USING_LIBNFC is not set +# CONFIG_PKG_USING_MFOC is not set +# CONFIG_PKG_USING_TMC51XX is not set +# CONFIG_PKG_USING_TCA9534 is not set +# CONFIG_PKG_USING_KOBUKI is not set +# CONFIG_PKG_USING_ROSSERIAL is not set +# CONFIG_PKG_USING_MICRO_ROS is not set +# CONFIG_PKG_USING_MCP23008 is not set +# CONFIG_PKG_USING_BLUETRUM_SDK is not set + +# +# AI packages +# +# CONFIG_PKG_USING_LIBANN is not set +# CONFIG_PKG_USING_NNOM is not set +# CONFIG_PKG_USING_ONNX_BACKEND is not set +# CONFIG_PKG_USING_ONNX_PARSER is not set +# CONFIG_PKG_USING_TENSORFLOWLITEMICRO is not set +# CONFIG_PKG_USING_ELAPACK is not set +# CONFIG_PKG_USING_ULAPACK is not set +# CONFIG_PKG_USING_QUEST is not set +# CONFIG_PKG_USING_NAXOS is not set # # miscellaneous packages # + +# +# samples: kernel and components samples +# +# CONFIG_PKG_USING_KERNEL_SAMPLES is not set +# CONFIG_PKG_USING_FILESYSTEM_SAMPLES is not set +# CONFIG_PKG_USING_NETWORK_SAMPLES is not set +# CONFIG_PKG_USING_PERIPHERAL_SAMPLES is not set + +# +# entertainment: terminal games and other interesting software packages +# +# CONFIG_PKG_USING_CMATRIX is not set +# CONFIG_PKG_USING_SL is not set +# CONFIG_PKG_USING_CAL is not set +# CONFIG_PKG_USING_ACLOCK is not set +# CONFIG_PKG_USING_THREES is not set +# CONFIG_PKG_USING_2048 is not set +# CONFIG_PKG_USING_SNAKE is not set +# CONFIG_PKG_USING_TETRIS is not set +# CONFIG_PKG_USING_DONUT is not set # CONFIG_PKG_USING_LIBCSV is not set # CONFIG_PKG_USING_OPTPARSE is not set # CONFIG_PKG_USING_FASTLZ is not set # CONFIG_PKG_USING_MINILZO is not set # CONFIG_PKG_USING_QUICKLZ is not set +# CONFIG_PKG_USING_LZMA is not set # CONFIG_PKG_USING_MULTIBUTTON is not set +# CONFIG_PKG_USING_FLEXIBLE_BUTTON is not set # CONFIG_PKG_USING_CANFESTIVAL is not set # CONFIG_PKG_USING_ZLIB is not set +# CONFIG_PKG_USING_MINIZIP is not set # CONFIG_PKG_USING_DSTR is not set # CONFIG_PKG_USING_TINYFRAME is not set - -# -# samples: kernel and components samples -# -# CONFIG_PKG_USING_KERNEL_SAMPLES is not set -# CONFIG_PKG_USING_FILESYSTEM_SAMPLES is not set -# CONFIG_PKG_USING_NETWORK_SAMPLES is not set -# CONFIG_PKG_USING_PERIPHERAL_SAMPLES is not set +# CONFIG_PKG_USING_KENDRYTE_DEMO is not set +# CONFIG_PKG_USING_DIGITALCTRL is not set +# CONFIG_PKG_USING_UPACKER is not set +# CONFIG_PKG_USING_UPARAM is not set # CONFIG_PKG_USING_HELLO is not set -CONFIG_SOC_SWM320VET7=y +# CONFIG_PKG_USING_VI is not set +# CONFIG_PKG_USING_KI is not set +# CONFIG_PKG_USING_ARMv7M_DWT is not set +# CONFIG_PKG_USING_VT100 is not set +# CONFIG_PKG_USING_UKAL is not set +# CONFIG_PKG_USING_CRCLIB is not set +# CONFIG_PKG_USING_LWGPS is not set +# CONFIG_PKG_USING_STATE_MACHINE is not set +# CONFIG_PKG_USING_MCURSES is not set +# CONFIG_PKG_USING_COWSAY is not set +# CONFIG_PKG_USING_TERMBOX is not set # # Hardware Drivers Config # +CONFIG_SOC_SWM320=y # # On-chip Peripheral Drivers # -CONFIG_BSP_USING_GPIO=y -# CONFIG_BSP_USING_WDT is not set - -# -# UART Drivers -# +CONFIG_BSP_USING_UART=y CONFIG_BSP_USING_UART0=y # CONFIG_BSP_USING_UART1 is not set # CONFIG_BSP_USING_UART2 is not set # CONFIG_BSP_USING_UART3 is not set - -# -# SPI Drivers -# -# CONFIG_BSP_USING_SPI0 is not set -# CONFIG_BSP_USING_SPI1 is not set - -# -# I2C Drivers -# +CONFIG_BSP_USING_GPIO=y +# CONFIG_BSP_USING_ADC is not set +# CONFIG_BSP_USING_TIM is not set # CONFIG_BSP_USING_I2C is not set - -# -# PWM Drivers -# -# CONFIG_BSP_USING_PWM0 is not set -# CONFIG_BSP_USING_PWM1 is not set -# CONFIG_BSP_USING_PWM2 is not set -# CONFIG_BSP_USING_PWM3 is not set - -# -# RTC Drivers -# +# CONFIG_BSP_USING_PWM is not set # CONFIG_BSP_USING_RTC is not set - -# -# HWtimer Drivers -# -# CONFIG_BSP_USING_HWTIMER0 is not set -# CONFIG_BSP_USING_HWTIMER1 is not set -# CONFIG_BSP_USING_HWTIMER2 is not set -# CONFIG_BSP_USING_HWTIMER3 is not set -# CONFIG_BSP_USING_HWTIMER4 is not set -# CONFIG_BSP_USING_HWTIMER5 is not set +# CONFIG_BSP_USING_SPI is not set +# CONFIG_BSP_USING_WDT is not set +# CONFIG_BSP_USING_CRC is not set # # Onboard Peripheral Drivers # +# CONFIG_BSP_USING_SDIO is not set # CONFIG_BSP_USING_EXT_SRAM is not set # CONFIG_BSP_USING_NOR_FLASH is not set diff --git a/bsp/swm320-lq100/Kconfig b/bsp/swm320-lq100/Kconfig index 59dcef1b29..126a6a1f5c 100644 --- a/bsp/swm320-lq100/Kconfig +++ b/bsp/swm320-lq100/Kconfig @@ -17,11 +17,9 @@ config PKGS_DIR source "$RTT_DIR/Kconfig" source "$PKGS_DIR/Kconfig" +source "drivers/Kconfig" -config SOC_SWM320VET7 +config SOC_SWM320 bool - select RT_USING_COMPONENTS_INIT - select RT_USING_USER_MAIN + select ARCH_ARM_CORTEX_M4 default y - -source "drivers/Kconfig" diff --git a/bsp/swm320-lq100/Libraries/CMSIS/CoreSupport/arm_common_tables.h b/bsp/swm320-lq100/Libraries/CMSIS/CoreSupport/arm_common_tables.h index 76aadca490..368705e1c2 100644 --- a/bsp/swm320-lq100/Libraries/CMSIS/CoreSupport/arm_common_tables.h +++ b/bsp/swm320-lq100/Libraries/CMSIS/CoreSupport/arm_common_tables.h @@ -2,12 +2,12 @@ * Copyright (C) 2010-2014 ARM Limited. All rights reserved. * * $Date: 31. July 2014 -* $Revision: V1.4.4 +* $Revision: V1.4.4 * -* Project: CMSIS DSP Library -* Title: arm_common_tables.h +* Project: CMSIS DSP Library +* Title: arm_common_tables.h * -* Description: This file has extern declaration for common tables like Bitreverse, reciprocal etc which are used across different functions +* Description: This file has extern declaration for common tables like Bitreverse, reciprocal etc which are used across different functions * * Target Processor: Cortex-M4/Cortex-M3 * @@ -85,14 +85,13 @@ extern const float32_t twiddleCoef_rfft_1024[1024]; extern const float32_t twiddleCoef_rfft_2048[2048]; extern const float32_t twiddleCoef_rfft_4096[4096]; - /* floating-point bit reversal tables */ -#define ARMBITREVINDEXTABLE__16_TABLE_LENGTH ((uint16_t)20 ) -#define ARMBITREVINDEXTABLE__32_TABLE_LENGTH ((uint16_t)48 ) -#define ARMBITREVINDEXTABLE__64_TABLE_LENGTH ((uint16_t)56 ) -#define ARMBITREVINDEXTABLE_128_TABLE_LENGTH ((uint16_t)208 ) -#define ARMBITREVINDEXTABLE_256_TABLE_LENGTH ((uint16_t)440 ) -#define ARMBITREVINDEXTABLE_512_TABLE_LENGTH ((uint16_t)448 ) +#define ARMBITREVINDEXTABLE__16_TABLE_LENGTH ((uint16_t)20) +#define ARMBITREVINDEXTABLE__32_TABLE_LENGTH ((uint16_t)48) +#define ARMBITREVINDEXTABLE__64_TABLE_LENGTH ((uint16_t)56) +#define ARMBITREVINDEXTABLE_128_TABLE_LENGTH ((uint16_t)208) +#define ARMBITREVINDEXTABLE_256_TABLE_LENGTH ((uint16_t)440) +#define ARMBITREVINDEXTABLE_512_TABLE_LENGTH ((uint16_t)448) #define ARMBITREVINDEXTABLE1024_TABLE_LENGTH ((uint16_t)1800) #define ARMBITREVINDEXTABLE2048_TABLE_LENGTH ((uint16_t)3808) #define ARMBITREVINDEXTABLE4096_TABLE_LENGTH ((uint16_t)4032) @@ -108,13 +107,13 @@ extern const uint16_t armBitRevIndexTable2048[ARMBITREVINDEXTABLE2048_TABLE_LENG extern const uint16_t armBitRevIndexTable4096[ARMBITREVINDEXTABLE4096_TABLE_LENGTH]; /* fixed-point bit reversal tables */ -#define ARMBITREVINDEXTABLE_FIXED___16_TABLE_LENGTH ((uint16_t)12 ) -#define ARMBITREVINDEXTABLE_FIXED___32_TABLE_LENGTH ((uint16_t)24 ) -#define ARMBITREVINDEXTABLE_FIXED___64_TABLE_LENGTH ((uint16_t)56 ) -#define ARMBITREVINDEXTABLE_FIXED__128_TABLE_LENGTH ((uint16_t)112 ) -#define ARMBITREVINDEXTABLE_FIXED__256_TABLE_LENGTH ((uint16_t)240 ) -#define ARMBITREVINDEXTABLE_FIXED__512_TABLE_LENGTH ((uint16_t)480 ) -#define ARMBITREVINDEXTABLE_FIXED_1024_TABLE_LENGTH ((uint16_t)992 ) +#define ARMBITREVINDEXTABLE_FIXED___16_TABLE_LENGTH ((uint16_t)12) +#define ARMBITREVINDEXTABLE_FIXED___32_TABLE_LENGTH ((uint16_t)24) +#define ARMBITREVINDEXTABLE_FIXED___64_TABLE_LENGTH ((uint16_t)56) +#define ARMBITREVINDEXTABLE_FIXED__128_TABLE_LENGTH ((uint16_t)112) +#define ARMBITREVINDEXTABLE_FIXED__256_TABLE_LENGTH ((uint16_t)240) +#define ARMBITREVINDEXTABLE_FIXED__512_TABLE_LENGTH ((uint16_t)480) +#define ARMBITREVINDEXTABLE_FIXED_1024_TABLE_LENGTH ((uint16_t)992) #define ARMBITREVINDEXTABLE_FIXED_2048_TABLE_LENGTH ((uint16_t)1984) #define ARMBITREVINDEXTABLE_FIXED_4096_TABLE_LENGTH ((uint16_t)4032) diff --git a/bsp/swm320-lq100/Libraries/CMSIS/CoreSupport/arm_const_structs.h b/bsp/swm320-lq100/Libraries/CMSIS/CoreSupport/arm_const_structs.h index 217f1d50e2..2033c5e375 100644 --- a/bsp/swm320-lq100/Libraries/CMSIS/CoreSupport/arm_const_structs.h +++ b/bsp/swm320-lq100/Libraries/CMSIS/CoreSupport/arm_const_structs.h @@ -2,12 +2,12 @@ * Copyright (C) 2010-2014 ARM Limited. All rights reserved. * * $Date: 31. July 2014 -* $Revision: V1.4.4 +* $Revision: V1.4.4 * -* Project: CMSIS DSP Library -* Title: arm_const_structs.h +* Project: CMSIS DSP Library +* Title: arm_const_structs.h * -* Description: This file has constant structs that are initialized for +* Description: This file has constant structs that are initialized for * user convenience. For example, some can be given as * arguments to the arm_cfft_f32() function. * @@ -46,34 +46,34 @@ #include "arm_math.h" #include "arm_common_tables.h" - extern const arm_cfft_instance_f32 arm_cfft_sR_f32_len16; - extern const arm_cfft_instance_f32 arm_cfft_sR_f32_len32; - extern const arm_cfft_instance_f32 arm_cfft_sR_f32_len64; - extern const arm_cfft_instance_f32 arm_cfft_sR_f32_len128; - extern const arm_cfft_instance_f32 arm_cfft_sR_f32_len256; - extern const arm_cfft_instance_f32 arm_cfft_sR_f32_len512; - extern const arm_cfft_instance_f32 arm_cfft_sR_f32_len1024; - extern const arm_cfft_instance_f32 arm_cfft_sR_f32_len2048; - extern const arm_cfft_instance_f32 arm_cfft_sR_f32_len4096; +extern const arm_cfft_instance_f32 arm_cfft_sR_f32_len16; +extern const arm_cfft_instance_f32 arm_cfft_sR_f32_len32; +extern const arm_cfft_instance_f32 arm_cfft_sR_f32_len64; +extern const arm_cfft_instance_f32 arm_cfft_sR_f32_len128; +extern const arm_cfft_instance_f32 arm_cfft_sR_f32_len256; +extern const arm_cfft_instance_f32 arm_cfft_sR_f32_len512; +extern const arm_cfft_instance_f32 arm_cfft_sR_f32_len1024; +extern const arm_cfft_instance_f32 arm_cfft_sR_f32_len2048; +extern const arm_cfft_instance_f32 arm_cfft_sR_f32_len4096; - extern const arm_cfft_instance_q31 arm_cfft_sR_q31_len16; - extern const arm_cfft_instance_q31 arm_cfft_sR_q31_len32; - extern const arm_cfft_instance_q31 arm_cfft_sR_q31_len64; - extern const arm_cfft_instance_q31 arm_cfft_sR_q31_len128; - extern const arm_cfft_instance_q31 arm_cfft_sR_q31_len256; - extern const arm_cfft_instance_q31 arm_cfft_sR_q31_len512; - extern const arm_cfft_instance_q31 arm_cfft_sR_q31_len1024; - extern const arm_cfft_instance_q31 arm_cfft_sR_q31_len2048; - extern const arm_cfft_instance_q31 arm_cfft_sR_q31_len4096; +extern const arm_cfft_instance_q31 arm_cfft_sR_q31_len16; +extern const arm_cfft_instance_q31 arm_cfft_sR_q31_len32; +extern const arm_cfft_instance_q31 arm_cfft_sR_q31_len64; +extern const arm_cfft_instance_q31 arm_cfft_sR_q31_len128; +extern const arm_cfft_instance_q31 arm_cfft_sR_q31_len256; +extern const arm_cfft_instance_q31 arm_cfft_sR_q31_len512; +extern const arm_cfft_instance_q31 arm_cfft_sR_q31_len1024; +extern const arm_cfft_instance_q31 arm_cfft_sR_q31_len2048; +extern const arm_cfft_instance_q31 arm_cfft_sR_q31_len4096; - extern const arm_cfft_instance_q15 arm_cfft_sR_q15_len16; - extern const arm_cfft_instance_q15 arm_cfft_sR_q15_len32; - extern const arm_cfft_instance_q15 arm_cfft_sR_q15_len64; - extern const arm_cfft_instance_q15 arm_cfft_sR_q15_len128; - extern const arm_cfft_instance_q15 arm_cfft_sR_q15_len256; - extern const arm_cfft_instance_q15 arm_cfft_sR_q15_len512; - extern const arm_cfft_instance_q15 arm_cfft_sR_q15_len1024; - extern const arm_cfft_instance_q15 arm_cfft_sR_q15_len2048; - extern const arm_cfft_instance_q15 arm_cfft_sR_q15_len4096; +extern const arm_cfft_instance_q15 arm_cfft_sR_q15_len16; +extern const arm_cfft_instance_q15 arm_cfft_sR_q15_len32; +extern const arm_cfft_instance_q15 arm_cfft_sR_q15_len64; +extern const arm_cfft_instance_q15 arm_cfft_sR_q15_len128; +extern const arm_cfft_instance_q15 arm_cfft_sR_q15_len256; +extern const arm_cfft_instance_q15 arm_cfft_sR_q15_len512; +extern const arm_cfft_instance_q15 arm_cfft_sR_q15_len1024; +extern const arm_cfft_instance_q15 arm_cfft_sR_q15_len2048; +extern const arm_cfft_instance_q15 arm_cfft_sR_q15_len4096; #endif diff --git a/bsp/swm320-lq100/Libraries/CMSIS/CoreSupport/arm_math.h b/bsp/swm320-lq100/Libraries/CMSIS/CoreSupport/arm_math.h index f06a0713eb..5698fe08ab 100644 --- a/bsp/swm320-lq100/Libraries/CMSIS/CoreSupport/arm_math.h +++ b/bsp/swm320-lq100/Libraries/CMSIS/CoreSupport/arm_math.h @@ -2,12 +2,12 @@ * Copyright (C) 2010-2014 ARM Limited. All rights reserved. * * $Date: 12. March 2014 -* $Revision: V1.4.4 +* $Revision: V1.4.4 * -* Project: CMSIS DSP Library -* Title: arm_math.h +* Project: CMSIS DSP Library +* Title: arm_math.h * -* Description: Public header file for CMSIS DSP Library +* Description: Public header file for CMSIS DSP Library * * Target Processor: Cortex-M7/Cortex-M4/Cortex-M3/Cortex-M0 * @@ -134,7 +134,7 @@ *
* CMSIS-DSP in ARM::CMSIS Pack * ----------------------------- - * + * * The following files relevant to CMSIS-DSP are present in the ARM::CMSIS Pack directories: * |File/Folder |Content | * |------------------------------|------------------------------------------------------------------------| @@ -142,7 +142,7 @@ * |\b CMSIS\\DSP_Lib | Software license agreement (license.txt) | * |\b CMSIS\\DSP_Lib\\Examples | Example projects demonstrating the usage of the library functions | * |\b CMSIS\\DSP_Lib\\Source | Source files for rebuilding the library | - * + * *
* Revision History of CMSIS-DSP * ------------ @@ -154,7 +154,6 @@ * Copyright (C) 2010-2014 ARM Limited. All rights reserved. */ - /** * @defgroup groupMath Basic Math Functions */ @@ -281,122 +280,121 @@ #ifndef _ARM_MATH_H #define _ARM_MATH_H -#define __CMSIS_GENERIC /* disable NVIC and Systick functions */ +#define __CMSIS_GENERIC /* disable NVIC and Systick functions */ #if defined(ARM_MATH_CM7) - #include "core_cm7.h" -#elif defined (ARM_MATH_CM4) - #include "core_cm4.h" -#elif defined (ARM_MATH_CM3) - #include "core_cm3.h" -#elif defined (ARM_MATH_CM0) - #include "core_cm0.h" +#include "core_cm7.h" +#elif defined(ARM_MATH_CM4) +#include "core_cm4.h" +#elif defined(ARM_MATH_CM3) +#include "core_cm3.h" +#elif defined(ARM_MATH_CM0) +#include "core_cm0.h" #define ARM_MATH_CM0_FAMILY - #elif defined (ARM_MATH_CM0PLUS) +#elif defined(ARM_MATH_CM0PLUS) #include "core_cm0plus.h" - #define ARM_MATH_CM0_FAMILY +#define ARM_MATH_CM0_FAMILY #else - #error "Define according the used Cortex core ARM_MATH_CM7, ARM_MATH_CM4, ARM_MATH_CM3, ARM_MATH_CM0PLUS or ARM_MATH_CM0" +#error "Define according the used Cortex core ARM_MATH_CM7, ARM_MATH_CM4, ARM_MATH_CM3, ARM_MATH_CM0PLUS or ARM_MATH_CM0" #endif -#undef __CMSIS_GENERIC /* enable NVIC and Systick functions */ +#undef __CMSIS_GENERIC /* enable NVIC and Systick functions */ #include "string.h" #include "math.h" -#ifdef __cplusplus +#ifdef __cplusplus extern "C" { #endif - - /** + /** * @brief Macros required for reciprocal calculation in Normalized LMS */ -#define DELTA_Q31 (0x100) -#define DELTA_Q15 0x5 -#define INDEX_MASK 0x0000003F +#define DELTA_Q31 (0x100) +#define DELTA_Q15 0x5 +#define INDEX_MASK 0x0000003F #ifndef PI -#define PI 3.14159265358979f +#define PI 3.14159265358979f #endif - /** + /** * @brief Macros required for SINE and COSINE Fast math approximations */ -#define FAST_MATH_TABLE_SIZE 512 -#define FAST_MATH_Q31_SHIFT (32 - 10) -#define FAST_MATH_Q15_SHIFT (16 - 10) -#define CONTROLLER_Q31_SHIFT (32 - 9) -#define TABLE_SIZE 256 -#define TABLE_SPACING_Q31 0x400000 -#define TABLE_SPACING_Q15 0x80 +#define FAST_MATH_TABLE_SIZE 512 +#define FAST_MATH_Q31_SHIFT (32 - 10) +#define FAST_MATH_Q15_SHIFT (16 - 10) +#define CONTROLLER_Q31_SHIFT (32 - 9) +#define TABLE_SIZE 256 +#define TABLE_SPACING_Q31 0x400000 +#define TABLE_SPACING_Q15 0x80 - /** + /** * @brief Macros required for SINE and COSINE Controller functions */ - /* 1.31(q31) Fixed value of 2/360 */ - /* -1 to +1 is divided into 360 values so total spacing is (2/360) */ -#define INPUT_SPACING 0xB60B61 + /* 1.31(q31) Fixed value of 2/360 */ + /* -1 to +1 is divided into 360 values so total spacing is (2/360) */ +#define INPUT_SPACING 0xB60B61 - /** + /** * @brief Macro for Unaligned Support */ #ifndef UNALIGNED_SUPPORT_DISABLE - #define ALIGN4 +#define ALIGN4 +#else +#if defined(__GNUC__) +#define ALIGN4 __attribute__((aligned(4))) #else - #if defined (__GNUC__) - #define ALIGN4 __attribute__((aligned(4))) - #else - #define ALIGN4 __align(4) - #endif -#endif /* #ifndef UNALIGNED_SUPPORT_DISABLE */ - - /** +#define ALIGN4 __align(4) +#endif +#endif /* #ifndef UNALIGNED_SUPPORT_DISABLE */ + + /** * @brief Error status returned by some functions in the library. */ - typedef enum - { - ARM_MATH_SUCCESS = 0, /**< No error */ - ARM_MATH_ARGUMENT_ERROR = -1, /**< One or more arguments are incorrect */ - ARM_MATH_LENGTH_ERROR = -2, /**< Length of data buffer is incorrect */ - ARM_MATH_SIZE_MISMATCH = -3, /**< Size of matrices is not compatible with the operation. */ - ARM_MATH_NANINF = -4, /**< Not-a-number (NaN) or infinity is generated */ - ARM_MATH_SINGULAR = -5, /**< Generated by matrix inversion if the input matrix is singular and cannot be inverted. */ - ARM_MATH_TEST_FAILURE = -6 /**< Test Failed */ - } arm_status; + typedef enum + { + ARM_MATH_SUCCESS = 0, /**< No error */ + ARM_MATH_ARGUMENT_ERROR = -1, /**< One or more arguments are incorrect */ + ARM_MATH_LENGTH_ERROR = -2, /**< Length of data buffer is incorrect */ + ARM_MATH_SIZE_MISMATCH = -3, /**< Size of matrices is not compatible with the operation. */ + ARM_MATH_NANINF = -4, /**< Not-a-number (NaN) or infinity is generated */ + ARM_MATH_SINGULAR = -5, /**< Generated by matrix inversion if the input matrix is singular and cannot be inverted. */ + ARM_MATH_TEST_FAILURE = -6 /**< Test Failed */ + } arm_status; - /** + /** * @brief 8-bit fractional data type in 1.7 format. */ - typedef int8_t q7_t; + typedef int8_t q7_t; - /** + /** * @brief 16-bit fractional data type in 1.15 format. */ - typedef int16_t q15_t; + typedef int16_t q15_t; - /** + /** * @brief 32-bit fractional data type in 1.31 format. */ - typedef int32_t q31_t; + typedef int32_t q31_t; - /** + /** * @brief 64-bit fractional data type in 1.63 format. */ - typedef int64_t q63_t; + typedef int64_t q63_t; - /** + /** * @brief 32-bit floating-point type definition. */ - typedef float float32_t; + typedef float float32_t; - /** + /** * @brief 64-bit floating-point type definition. */ - typedef double float64_t; + typedef double float64_t; - /** + /** * @brief definition to read/write two 16 bit values. */ #if defined __CC_ARM @@ -408,704 +406,681 @@ extern "C" #elif defined __GNUC__ #define __SIMD32_TYPE int32_t #define CMSIS_UNUSED __attribute__((unused)) -#elif defined __CSMC__ /* Cosmic */ +#elif defined __CSMC__ /* Cosmic */ #define CMSIS_UNUSED #define __SIMD32_TYPE int32_t #else #error Unknown compiler #endif -#define __SIMD32(addr) (*(__SIMD32_TYPE **) & (addr)) -#define __SIMD32_CONST(addr) ((__SIMD32_TYPE *)(addr)) +#define __SIMD32(addr) (*(__SIMD32_TYPE **)&(addr)) +#define __SIMD32_CONST(addr) ((__SIMD32_TYPE *)(addr)) -#define _SIMD32_OFFSET(addr) (*(__SIMD32_TYPE *) (addr)) +#define _SIMD32_OFFSET(addr) (*(__SIMD32_TYPE *)(addr)) -#define __SIMD64(addr) (*(int64_t **) & (addr)) +#define __SIMD64(addr) (*(int64_t **)&(addr)) -#if defined (ARM_MATH_CM3) || defined (ARM_MATH_CM0_FAMILY) - /** +#if defined(ARM_MATH_CM3) || defined(ARM_MATH_CM0_FAMILY) + /** * @brief definition to pack two 16 bit values. */ -#define __PKHBT(ARG1, ARG2, ARG3) ( (((int32_t)(ARG1) << 0) & (int32_t)0x0000FFFF) | \ - (((int32_t)(ARG2) << ARG3) & (int32_t)0xFFFF0000) ) -#define __PKHTB(ARG1, ARG2, ARG3) ( (((int32_t)(ARG1) << 0) & (int32_t)0xFFFF0000) | \ - (((int32_t)(ARG2) >> ARG3) & (int32_t)0x0000FFFF) ) +#define __PKHBT(ARG1, ARG2, ARG3) ((((int32_t)(ARG1) << 0) & (int32_t)0x0000FFFF) | \ + (((int32_t)(ARG2) << ARG3) & (int32_t)0xFFFF0000)) +#define __PKHTB(ARG1, ARG2, ARG3) ((((int32_t)(ARG1) << 0) & (int32_t)0xFFFF0000) | \ + (((int32_t)(ARG2) >> ARG3) & (int32_t)0x0000FFFF)) #endif - - /** + /** * @brief definition to pack four 8 bit values. */ #ifndef ARM_MATH_BIG_ENDIAN -#define __PACKq7(v0,v1,v2,v3) ( (((int32_t)(v0) << 0) & (int32_t)0x000000FF) | \ - (((int32_t)(v1) << 8) & (int32_t)0x0000FF00) | \ - (((int32_t)(v2) << 16) & (int32_t)0x00FF0000) | \ - (((int32_t)(v3) << 24) & (int32_t)0xFF000000) ) +#define __PACKq7(v0, v1, v2, v3) ((((int32_t)(v0) << 0) & (int32_t)0x000000FF) | \ + (((int32_t)(v1) << 8) & (int32_t)0x0000FF00) | \ + (((int32_t)(v2) << 16) & (int32_t)0x00FF0000) | \ + (((int32_t)(v3) << 24) & (int32_t)0xFF000000)) #else -#define __PACKq7(v0,v1,v2,v3) ( (((int32_t)(v3) << 0) & (int32_t)0x000000FF) | \ - (((int32_t)(v2) << 8) & (int32_t)0x0000FF00) | \ - (((int32_t)(v1) << 16) & (int32_t)0x00FF0000) | \ - (((int32_t)(v0) << 24) & (int32_t)0xFF000000) ) +#define __PACKq7(v0, v1, v2, v3) ((((int32_t)(v3) << 0) & (int32_t)0x000000FF) | \ + (((int32_t)(v2) << 8) & (int32_t)0x0000FF00) | \ + (((int32_t)(v1) << 16) & (int32_t)0x00FF0000) | \ + (((int32_t)(v0) << 24) & (int32_t)0xFF000000)) #endif - - /** + /** * @brief Clips Q63 to Q31 values. */ - static __INLINE q31_t clip_q63_to_q31( - q63_t x) - { - return ((q31_t) (x >> 32) != ((q31_t) x >> 31)) ? - ((0x7FFFFFFF ^ ((q31_t) (x >> 63)))) : (q31_t) x; - } + static __INLINE q31_t clip_q63_to_q31( + q63_t x) + { + return ((q31_t)(x >> 32) != ((q31_t)x >> 31)) ? ((0x7FFFFFFF ^ ((q31_t)(x >> 63)))) : (q31_t)x; + } - /** + /** * @brief Clips Q63 to Q15 values. */ - static __INLINE q15_t clip_q63_to_q15( - q63_t x) - { - return ((q31_t) (x >> 32) != ((q31_t) x >> 31)) ? - ((0x7FFF ^ ((q15_t) (x >> 63)))) : (q15_t) (x >> 15); - } + static __INLINE q15_t clip_q63_to_q15( + q63_t x) + { + return ((q31_t)(x >> 32) != ((q31_t)x >> 31)) ? ((0x7FFF ^ ((q15_t)(x >> 63)))) : (q15_t)(x >> 15); + } - /** + /** * @brief Clips Q31 to Q7 values. */ - static __INLINE q7_t clip_q31_to_q7( - q31_t x) - { - return ((q31_t) (x >> 24) != ((q31_t) x >> 23)) ? - ((0x7F ^ ((q7_t) (x >> 31)))) : (q7_t) x; - } + static __INLINE q7_t clip_q31_to_q7( + q31_t x) + { + return ((q31_t)(x >> 24) != ((q31_t)x >> 23)) ? ((0x7F ^ ((q7_t)(x >> 31)))) : (q7_t)x; + } - /** + /** * @brief Clips Q31 to Q15 values. */ - static __INLINE q15_t clip_q31_to_q15( - q31_t x) - { - return ((q31_t) (x >> 16) != ((q31_t) x >> 15)) ? - ((0x7FFF ^ ((q15_t) (x >> 31)))) : (q15_t) x; - } + static __INLINE q15_t clip_q31_to_q15( + q31_t x) + { + return ((q31_t)(x >> 16) != ((q31_t)x >> 15)) ? ((0x7FFF ^ ((q15_t)(x >> 31)))) : (q15_t)x; + } - /** + /** * @brief Multiplies 32 X 64 and returns 32 bit result in 2.30 format. */ - static __INLINE q63_t mult32x64( - q63_t x, - q31_t y) - { - return ((((q63_t) (x & 0x00000000FFFFFFFF) * y) >> 32) + - (((q63_t) (x >> 32) * y))); - } - + static __INLINE q63_t mult32x64( + q63_t x, + q31_t y) + { + return ((((q63_t)(x & 0x00000000FFFFFFFF) * y) >> 32) + + (((q63_t)(x >> 32) * y))); + } -#if defined (ARM_MATH_CM0_FAMILY) && defined ( __CC_ARM ) +#if defined(ARM_MATH_CM0_FAMILY) && defined(__CC_ARM) #define __CLZ __clz #endif -#if defined (ARM_MATH_CM0_FAMILY) && ((defined (__ICCARM__)) ||(defined (__GNUC__)) || defined (__TASKING__) ) - - static __INLINE uint32_t __CLZ( - q31_t data); +#if defined(ARM_MATH_CM0_FAMILY) && ((defined(__ICCARM__)) || (defined(__GNUC__)) || defined(__TASKING__)) + static __INLINE uint32_t __CLZ( + q31_t data); - static __INLINE uint32_t __CLZ( - q31_t data) - { - uint32_t count = 0; - uint32_t mask = 0x80000000; - - while((data & mask) == 0) + static __INLINE uint32_t __CLZ( + q31_t data) { - count += 1u; - mask = mask >> 1u; - } + uint32_t count = 0; + uint32_t mask = 0x80000000; - return (count); + while ((data & mask) == 0) + { + count += 1u; + mask = mask >> 1u; + } - } + return (count); + } #endif - /** + /** * @brief Function to Calculates 1/in (reciprocal) value of Q31 Data type. */ - static __INLINE uint32_t arm_recip_q31( - q31_t in, - q31_t * dst, - q31_t * pRecipTable) - { - - uint32_t out, tempVal; - uint32_t index, i; - uint32_t signBits; - - if(in > 0) + static __INLINE uint32_t arm_recip_q31( + q31_t in, + q31_t *dst, + q31_t *pRecipTable) { - signBits = __CLZ(in) - 1; - } - else - { - signBits = __CLZ(-in) - 1; - } - - /* Convert input sample to 1.31 format */ - in = in << signBits; - /* calculation of index for initial approximated Val */ - index = (uint32_t) (in >> 24u); - index = (index & INDEX_MASK); - - /* 1.31 with exp 1 */ - out = pRecipTable[index]; - - /* calculation of reciprocal value */ - /* running approximation for two iterations */ - for (i = 0u; i < 2u; i++) - { - tempVal = (q31_t) (((q63_t) in * out) >> 31u); - tempVal = 0x7FFFFFFF - tempVal; - /* 1.31 with exp 1 */ - //out = (q31_t) (((q63_t) out * tempVal) >> 30u); - out = (q31_t) clip_q63_to_q31(((q63_t) out * tempVal) >> 30u); + uint32_t out, tempVal; + uint32_t index, i; + uint32_t signBits; + + if (in > 0) + { + signBits = __CLZ(in) - 1; + } + else + { + signBits = __CLZ(-in) - 1; + } + + /* Convert input sample to 1.31 format */ + in = in << signBits; + + /* calculation of index for initial approximated Val */ + index = (uint32_t)(in >> 24u); + index = (index & INDEX_MASK); + + /* 1.31 with exp 1 */ + out = pRecipTable[index]; + + /* calculation of reciprocal value */ + /* running approximation for two iterations */ + for (i = 0u; i < 2u; i++) + { + tempVal = (q31_t)(((q63_t)in * out) >> 31u); + tempVal = 0x7FFFFFFF - tempVal; + /* 1.31 with exp 1 */ + //out = (q31_t) (((q63_t) out * tempVal) >> 30u); + out = (q31_t)clip_q63_to_q31(((q63_t)out * tempVal) >> 30u); + } + + /* write output */ + *dst = out; + + /* return num of signbits of out = 1/in value */ + return (signBits + 1u); } - /* write output */ - *dst = out; - - /* return num of signbits of out = 1/in value */ - return (signBits + 1u); - - } - - /** + /** * @brief Function to Calculates 1/in (reciprocal) value of Q15 Data type. */ - static __INLINE uint32_t arm_recip_q15( - q15_t in, - q15_t * dst, - q15_t * pRecipTable) - { - - uint32_t out = 0, tempVal = 0; - uint32_t index = 0, i = 0; - uint32_t signBits = 0; - - if(in > 0) - { - signBits = __CLZ(in) - 17; - } - else + static __INLINE uint32_t arm_recip_q15( + q15_t in, + q15_t *dst, + q15_t *pRecipTable) { - signBits = __CLZ(-in) - 17; - } - /* Convert input sample to 1.15 format */ - in = in << signBits; - - /* calculation of index for initial approximated Val */ - index = in >> 8; - index = (index & INDEX_MASK); - - /* 1.15 with exp 1 */ - out = pRecipTable[index]; - - /* calculation of reciprocal value */ - /* running approximation for two iterations */ - for (i = 0; i < 2; i++) - { - tempVal = (q15_t) (((q31_t) in * out) >> 15); - tempVal = 0x7FFF - tempVal; - /* 1.15 with exp 1 */ - out = (q15_t) (((q31_t) out * tempVal) >> 14); + uint32_t out = 0, tempVal = 0; + uint32_t index = 0, i = 0; + uint32_t signBits = 0; + + if (in > 0) + { + signBits = __CLZ(in) - 17; + } + else + { + signBits = __CLZ(-in) - 17; + } + + /* Convert input sample to 1.15 format */ + in = in << signBits; + + /* calculation of index for initial approximated Val */ + index = in >> 8; + index = (index & INDEX_MASK); + + /* 1.15 with exp 1 */ + out = pRecipTable[index]; + + /* calculation of reciprocal value */ + /* running approximation for two iterations */ + for (i = 0; i < 2; i++) + { + tempVal = (q15_t)(((q31_t)in * out) >> 15); + tempVal = 0x7FFF - tempVal; + /* 1.15 with exp 1 */ + out = (q15_t)(((q31_t)out * tempVal) >> 14); + } + + /* write output */ + *dst = out; + + /* return num of signbits of out = 1/in value */ + return (signBits + 1); } - /* write output */ - *dst = out; - - /* return num of signbits of out = 1/in value */ - return (signBits + 1); - - } - - - /* + /* * @brief C custom defined intrinisic function for only M0 processors */ #if defined(ARM_MATH_CM0_FAMILY) - static __INLINE q31_t __SSAT( - q31_t x, - uint32_t y) - { - int32_t posMax, negMin; - uint32_t i; - - posMax = 1; - for (i = 0; i < (y - 1); i++) - { - posMax = posMax * 2; - } - - if(x > 0) + static __INLINE q31_t __SSAT( + q31_t x, + uint32_t y) { - posMax = (posMax - 1); - - if(x > posMax) - { - x = posMax; - } - } - else - { - negMin = -posMax; - - if(x < negMin) - { - x = negMin; - } + int32_t posMax, negMin; + uint32_t i; + + posMax = 1; + for (i = 0; i < (y - 1); i++) + { + posMax = posMax * 2; + } + + if (x > 0) + { + posMax = (posMax - 1); + + if (x > posMax) + { + x = posMax; + } + } + else + { + negMin = -posMax; + + if (x < negMin) + { + x = negMin; + } + } + return (x); } - return (x); - - - } #endif /* end of ARM_MATH_CM0_FAMILY */ - - - /* + /* * @brief C custom defined intrinsic function for M3 and M0 processors */ -#if defined (ARM_MATH_CM3) || defined (ARM_MATH_CM0_FAMILY) +#if defined(ARM_MATH_CM3) || defined(ARM_MATH_CM0_FAMILY) - /* + /* * @brief C custom defined QADD8 for M3 and M0 processors */ - static __INLINE q31_t __QADD8( - q31_t x, - q31_t y) - { - - q31_t sum; - q7_t r, s, t, u; + static __INLINE q31_t __QADD8( + q31_t x, + q31_t y) + { - r = (q7_t) x; - s = (q7_t) y; + q31_t sum; + q7_t r, s, t, u; - r = __SSAT((q31_t) (r + s), 8); - s = __SSAT(((q31_t) (((x << 16) >> 24) + ((y << 16) >> 24))), 8); - t = __SSAT(((q31_t) (((x << 8) >> 24) + ((y << 8) >> 24))), 8); - u = __SSAT(((q31_t) ((x >> 24) + (y >> 24))), 8); + r = (q7_t)x; + s = (q7_t)y; - sum = - (((q31_t) u << 24) & 0xFF000000) | (((q31_t) t << 16) & 0x00FF0000) | - (((q31_t) s << 8) & 0x0000FF00) | (r & 0x000000FF); + r = __SSAT((q31_t)(r + s), 8); + s = __SSAT(((q31_t)(((x << 16) >> 24) + ((y << 16) >> 24))), 8); + t = __SSAT(((q31_t)(((x << 8) >> 24) + ((y << 8) >> 24))), 8); + u = __SSAT(((q31_t)((x >> 24) + (y >> 24))), 8); - return sum; + sum = + (((q31_t)u << 24) & 0xFF000000) | (((q31_t)t << 16) & 0x00FF0000) | + (((q31_t)s << 8) & 0x0000FF00) | (r & 0x000000FF); - } + return sum; + } - /* + /* * @brief C custom defined QSUB8 for M3 and M0 processors */ - static __INLINE q31_t __QSUB8( - q31_t x, - q31_t y) - { + static __INLINE q31_t __QSUB8( + q31_t x, + q31_t y) + { - q31_t sum; - q31_t r, s, t, u; + q31_t sum; + q31_t r, s, t, u; - r = (q7_t) x; - s = (q7_t) y; + r = (q7_t)x; + s = (q7_t)y; - r = __SSAT((r - s), 8); - s = __SSAT(((q31_t) (((x << 16) >> 24) - ((y << 16) >> 24))), 8) << 8; - t = __SSAT(((q31_t) (((x << 8) >> 24) - ((y << 8) >> 24))), 8) << 16; - u = __SSAT(((q31_t) ((x >> 24) - (y >> 24))), 8) << 24; + r = __SSAT((r - s), 8); + s = __SSAT(((q31_t)(((x << 16) >> 24) - ((y << 16) >> 24))), 8) << 8; + t = __SSAT(((q31_t)(((x << 8) >> 24) - ((y << 8) >> 24))), 8) << 16; + u = __SSAT(((q31_t)((x >> 24) - (y >> 24))), 8) << 24; - sum = - (u & 0xFF000000) | (t & 0x00FF0000) | (s & 0x0000FF00) | (r & - 0x000000FF); + sum = + (u & 0xFF000000) | (t & 0x00FF0000) | (s & 0x0000FF00) | (r & 0x000000FF); - return sum; - } + return sum; + } - /* + /* * @brief C custom defined QADD16 for M3 and M0 processors */ - /* + /* * @brief C custom defined QADD16 for M3 and M0 processors */ - static __INLINE q31_t __QADD16( - q31_t x, - q31_t y) - { - - q31_t sum; - q31_t r, s; + static __INLINE q31_t __QADD16( + q31_t x, + q31_t y) + { - r = (q15_t) x; - s = (q15_t) y; + q31_t sum; + q31_t r, s; - r = __SSAT(r + s, 16); - s = __SSAT(((q31_t) ((x >> 16) + (y >> 16))), 16) << 16; + r = (q15_t)x; + s = (q15_t)y; - sum = (s & 0xFFFF0000) | (r & 0x0000FFFF); + r = __SSAT(r + s, 16); + s = __SSAT(((q31_t)((x >> 16) + (y >> 16))), 16) << 16; - return sum; + sum = (s & 0xFFFF0000) | (r & 0x0000FFFF); - } + return sum; + } - /* + /* * @brief C custom defined SHADD16 for M3 and M0 processors */ - static __INLINE q31_t __SHADD16( - q31_t x, - q31_t y) - { - - q31_t sum; - q31_t r, s; + static __INLINE q31_t __SHADD16( + q31_t x, + q31_t y) + { - r = (q15_t) x; - s = (q15_t) y; + q31_t sum; + q31_t r, s; - r = ((r >> 1) + (s >> 1)); - s = ((q31_t) ((x >> 17) + (y >> 17))) << 16; + r = (q15_t)x; + s = (q15_t)y; - sum = (s & 0xFFFF0000) | (r & 0x0000FFFF); + r = ((r >> 1) + (s >> 1)); + s = ((q31_t)((x >> 17) + (y >> 17))) << 16; - return sum; + sum = (s & 0xFFFF0000) | (r & 0x0000FFFF); - } + return sum; + } - /* + /* * @brief C custom defined QSUB16 for M3 and M0 processors */ - static __INLINE q31_t __QSUB16( - q31_t x, - q31_t y) - { + static __INLINE q31_t __QSUB16( + q31_t x, + q31_t y) + { - q31_t sum; - q31_t r, s; + q31_t sum; + q31_t r, s; - r = (q15_t) x; - s = (q15_t) y; + r = (q15_t)x; + s = (q15_t)y; - r = __SSAT(r - s, 16); - s = __SSAT(((q31_t) ((x >> 16) - (y >> 16))), 16) << 16; + r = __SSAT(r - s, 16); + s = __SSAT(((q31_t)((x >> 16) - (y >> 16))), 16) << 16; - sum = (s & 0xFFFF0000) | (r & 0x0000FFFF); + sum = (s & 0xFFFF0000) | (r & 0x0000FFFF); - return sum; - } + return sum; + } - /* + /* * @brief C custom defined SHSUB16 for M3 and M0 processors */ - static __INLINE q31_t __SHSUB16( - q31_t x, - q31_t y) - { + static __INLINE q31_t __SHSUB16( + q31_t x, + q31_t y) + { - q31_t diff; - q31_t r, s; + q31_t diff; + q31_t r, s; - r = (q15_t) x; - s = (q15_t) y; + r = (q15_t)x; + s = (q15_t)y; - r = ((r >> 1) - (s >> 1)); - s = (((x >> 17) - (y >> 17)) << 16); + r = ((r >> 1) - (s >> 1)); + s = (((x >> 17) - (y >> 17)) << 16); - diff = (s & 0xFFFF0000) | (r & 0x0000FFFF); + diff = (s & 0xFFFF0000) | (r & 0x0000FFFF); - return diff; - } + return diff; + } - /* + /* * @brief C custom defined QASX for M3 and M0 processors */ - static __INLINE q31_t __QASX( - q31_t x, - q31_t y) - { + static __INLINE q31_t __QASX( + q31_t x, + q31_t y) + { - q31_t sum = 0; + q31_t sum = 0; - sum = - ((sum + - clip_q31_to_q15((q31_t) ((q15_t) (x >> 16) + (q15_t) y))) << 16) + - clip_q31_to_q15((q31_t) ((q15_t) x - (q15_t) (y >> 16))); + sum = + ((sum + + clip_q31_to_q15((q31_t)((q15_t)(x >> 16) + (q15_t)y))) + << 16) + + clip_q31_to_q15((q31_t)((q15_t)x - (q15_t)(y >> 16))); - return sum; - } + return sum; + } - /* + /* * @brief C custom defined SHASX for M3 and M0 processors */ - static __INLINE q31_t __SHASX( - q31_t x, - q31_t y) - { - - q31_t sum; - q31_t r, s; + static __INLINE q31_t __SHASX( + q31_t x, + q31_t y) + { - r = (q15_t) x; - s = (q15_t) y; + q31_t sum; + q31_t r, s; - r = ((r >> 1) - (y >> 17)); - s = (((x >> 17) + (s >> 1)) << 16); + r = (q15_t)x; + s = (q15_t)y; - sum = (s & 0xFFFF0000) | (r & 0x0000FFFF); + r = ((r >> 1) - (y >> 17)); + s = (((x >> 17) + (s >> 1)) << 16); - return sum; - } + sum = (s & 0xFFFF0000) | (r & 0x0000FFFF); + return sum; + } - /* + /* * @brief C custom defined QSAX for M3 and M0 processors */ - static __INLINE q31_t __QSAX( - q31_t x, - q31_t y) - { + static __INLINE q31_t __QSAX( + q31_t x, + q31_t y) + { - q31_t sum = 0; + q31_t sum = 0; - sum = - ((sum + - clip_q31_to_q15((q31_t) ((q15_t) (x >> 16) - (q15_t) y))) << 16) + - clip_q31_to_q15((q31_t) ((q15_t) x + (q15_t) (y >> 16))); + sum = + ((sum + + clip_q31_to_q15((q31_t)((q15_t)(x >> 16) - (q15_t)y))) + << 16) + + clip_q31_to_q15((q31_t)((q15_t)x + (q15_t)(y >> 16))); - return sum; - } + return sum; + } - /* + /* * @brief C custom defined SHSAX for M3 and M0 processors */ - static __INLINE q31_t __SHSAX( - q31_t x, - q31_t y) - { + static __INLINE q31_t __SHSAX( + q31_t x, + q31_t y) + { - q31_t sum; - q31_t r, s; + q31_t sum; + q31_t r, s; - r = (q15_t) x; - s = (q15_t) y; + r = (q15_t)x; + s = (q15_t)y; - r = ((r >> 1) + (y >> 17)); - s = (((x >> 17) - (s >> 1)) << 16); + r = ((r >> 1) + (y >> 17)); + s = (((x >> 17) - (s >> 1)) << 16); - sum = (s & 0xFFFF0000) | (r & 0x0000FFFF); + sum = (s & 0xFFFF0000) | (r & 0x0000FFFF); - return sum; - } + return sum; + } - /* + /* * @brief C custom defined SMUSDX for M3 and M0 processors */ - static __INLINE q31_t __SMUSDX( - q31_t x, - q31_t y) - { + static __INLINE q31_t __SMUSDX( + q31_t x, + q31_t y) + { - return ((q31_t) (((q15_t) x * (q15_t) (y >> 16)) - - ((q15_t) (x >> 16) * (q15_t) y))); - } + return ((q31_t)(((q15_t)x * (q15_t)(y >> 16)) - + ((q15_t)(x >> 16) * (q15_t)y))); + } - /* + /* * @brief C custom defined SMUADX for M3 and M0 processors */ - static __INLINE q31_t __SMUADX( - q31_t x, - q31_t y) - { + static __INLINE q31_t __SMUADX( + q31_t x, + q31_t y) + { - return ((q31_t) (((q15_t) x * (q15_t) (y >> 16)) + - ((q15_t) (x >> 16) * (q15_t) y))); - } + return ((q31_t)(((q15_t)x * (q15_t)(y >> 16)) + + ((q15_t)(x >> 16) * (q15_t)y))); + } - /* + /* * @brief C custom defined QADD for M3 and M0 processors */ - static __INLINE q31_t __QADD( - q31_t x, - q31_t y) - { - return clip_q63_to_q31((q63_t) x + y); - } + static __INLINE q31_t __QADD( + q31_t x, + q31_t y) + { + return clip_q63_to_q31((q63_t)x + y); + } - /* + /* * @brief C custom defined QSUB for M3 and M0 processors */ - static __INLINE q31_t __QSUB( - q31_t x, - q31_t y) - { - return clip_q63_to_q31((q63_t) x - y); - } + static __INLINE q31_t __QSUB( + q31_t x, + q31_t y) + { + return clip_q63_to_q31((q63_t)x - y); + } - /* + /* * @brief C custom defined SMLAD for M3 and M0 processors */ - static __INLINE q31_t __SMLAD( - q31_t x, - q31_t y, - q31_t sum) - { + static __INLINE q31_t __SMLAD( + q31_t x, + q31_t y, + q31_t sum) + { - return (sum + ((q15_t) (x >> 16) * (q15_t) (y >> 16)) + - ((q15_t) x * (q15_t) y)); - } + return (sum + ((q15_t)(x >> 16) * (q15_t)(y >> 16)) + + ((q15_t)x * (q15_t)y)); + } - /* + /* * @brief C custom defined SMLADX for M3 and M0 processors */ - static __INLINE q31_t __SMLADX( - q31_t x, - q31_t y, - q31_t sum) - { + static __INLINE q31_t __SMLADX( + q31_t x, + q31_t y, + q31_t sum) + { - return (sum + ((q15_t) (x >> 16) * (q15_t) (y)) + - ((q15_t) x * (q15_t) (y >> 16))); - } + return (sum + ((q15_t)(x >> 16) * (q15_t)(y)) + + ((q15_t)x * (q15_t)(y >> 16))); + } - /* + /* * @brief C custom defined SMLSDX for M3 and M0 processors */ - static __INLINE q31_t __SMLSDX( - q31_t x, - q31_t y, - q31_t sum) - { + static __INLINE q31_t __SMLSDX( + q31_t x, + q31_t y, + q31_t sum) + { - return (sum - ((q15_t) (x >> 16) * (q15_t) (y)) + - ((q15_t) x * (q15_t) (y >> 16))); - } + return (sum - ((q15_t)(x >> 16) * (q15_t)(y)) + + ((q15_t)x * (q15_t)(y >> 16))); + } - /* + /* * @brief C custom defined SMLALD for M3 and M0 processors */ - static __INLINE q63_t __SMLALD( - q31_t x, - q31_t y, - q63_t sum) - { + static __INLINE q63_t __SMLALD( + q31_t x, + q31_t y, + q63_t sum) + { - return (sum + ((q15_t) (x >> 16) * (q15_t) (y >> 16)) + - ((q15_t) x * (q15_t) y)); - } + return (sum + ((q15_t)(x >> 16) * (q15_t)(y >> 16)) + + ((q15_t)x * (q15_t)y)); + } - /* + /* * @brief C custom defined SMLALDX for M3 and M0 processors */ - static __INLINE q63_t __SMLALDX( - q31_t x, - q31_t y, - q63_t sum) - { + static __INLINE q63_t __SMLALDX( + q31_t x, + q31_t y, + q63_t sum) + { - return (sum + ((q15_t) (x >> 16) * (q15_t) y)) + - ((q15_t) x * (q15_t) (y >> 16)); - } + return (sum + ((q15_t)(x >> 16) * (q15_t)y)) + + ((q15_t)x * (q15_t)(y >> 16)); + } - /* + /* * @brief C custom defined SMUAD for M3 and M0 processors */ - static __INLINE q31_t __SMUAD( - q31_t x, - q31_t y) - { + static __INLINE q31_t __SMUAD( + q31_t x, + q31_t y) + { - return (((x >> 16) * (y >> 16)) + - (((x << 16) >> 16) * ((y << 16) >> 16))); - } + return (((x >> 16) * (y >> 16)) + + (((x << 16) >> 16) * ((y << 16) >> 16))); + } - /* + /* * @brief C custom defined SMUSD for M3 and M0 processors */ - static __INLINE q31_t __SMUSD( - q31_t x, - q31_t y) - { - - return (-((x >> 16) * (y >> 16)) + - (((x << 16) >> 16) * ((y << 16) >> 16))); - } + static __INLINE q31_t __SMUSD( + q31_t x, + q31_t y) + { + return (-((x >> 16) * (y >> 16)) + + (((x << 16) >> 16) * ((y << 16) >> 16))); + } - /* + /* * @brief C custom defined SXTB16 for M3 and M0 processors */ - static __INLINE q31_t __SXTB16( - q31_t x) - { - - return ((((x << 24) >> 24) & 0x0000FFFF) | - (((x << 8) >> 8) & 0xFFFF0000)); - } + static __INLINE q31_t __SXTB16( + q31_t x) + { + return ((((x << 24) >> 24) & 0x0000FFFF) | + (((x << 8) >> 8) & 0xFFFF0000)); + } #endif /* defined (ARM_MATH_CM3) || defined (ARM_MATH_CM0_FAMILY) */ - - /** + /** * @brief Instance structure for the Q7 FIR filter. */ - typedef struct - { - uint16_t numTaps; /**< number of filter coefficients in the filter. */ - q7_t *pState; /**< points to the state variable array. The array is of length numTaps+blockSize-1. */ - q7_t *pCoeffs; /**< points to the coefficient array. The array is of length numTaps.*/ - } arm_fir_instance_q7; + typedef struct + { + uint16_t numTaps; /**< number of filter coefficients in the filter. */ + q7_t *pState; /**< points to the state variable array. The array is of length numTaps+blockSize-1. */ + q7_t *pCoeffs; /**< points to the coefficient array. The array is of length numTaps.*/ + } arm_fir_instance_q7; - /** + /** * @brief Instance structure for the Q15 FIR filter. */ - typedef struct - { - uint16_t numTaps; /**< number of filter coefficients in the filter. */ - q15_t *pState; /**< points to the state variable array. The array is of length numTaps+blockSize-1. */ - q15_t *pCoeffs; /**< points to the coefficient array. The array is of length numTaps.*/ - } arm_fir_instance_q15; + typedef struct + { + uint16_t numTaps; /**< number of filter coefficients in the filter. */ + q15_t *pState; /**< points to the state variable array. The array is of length numTaps+blockSize-1. */ + q15_t *pCoeffs; /**< points to the coefficient array. The array is of length numTaps.*/ + } arm_fir_instance_q15; - /** + /** * @brief Instance structure for the Q31 FIR filter. */ - typedef struct - { - uint16_t numTaps; /**< number of filter coefficients in the filter. */ - q31_t *pState; /**< points to the state variable array. The array is of length numTaps+blockSize-1. */ - q31_t *pCoeffs; /**< points to the coefficient array. The array is of length numTaps. */ - } arm_fir_instance_q31; + typedef struct + { + uint16_t numTaps; /**< number of filter coefficients in the filter. */ + q31_t *pState; /**< points to the state variable array. The array is of length numTaps+blockSize-1. */ + q31_t *pCoeffs; /**< points to the coefficient array. The array is of length numTaps. */ + } arm_fir_instance_q31; - /** + /** * @brief Instance structure for the floating-point FIR filter. */ - typedef struct - { - uint16_t numTaps; /**< number of filter coefficients in the filter. */ - float32_t *pState; /**< points to the state variable array. The array is of length numTaps+blockSize-1. */ - float32_t *pCoeffs; /**< points to the coefficient array. The array is of length numTaps. */ - } arm_fir_instance_f32; - + typedef struct + { + uint16_t numTaps; /**< number of filter coefficients in the filter. */ + float32_t *pState; /**< points to the state variable array. The array is of length numTaps+blockSize-1. */ + float32_t *pCoeffs; /**< points to the coefficient array. The array is of length numTaps. */ + } arm_fir_instance_f32; - /** + /** * @brief Processing function for the Q7 FIR filter. * @param[in] *S points to an instance of the Q7 FIR filter structure. * @param[in] *pSrc points to the block of input data. @@ -1113,14 +1088,13 @@ extern "C" * @param[in] blockSize number of samples to process. * @return none. */ - void arm_fir_q7( - const arm_fir_instance_q7 * S, - q7_t * pSrc, - q7_t * pDst, - uint32_t blockSize); - + void arm_fir_q7( + const arm_fir_instance_q7 *S, + q7_t *pSrc, + q7_t *pDst, + uint32_t blockSize); - /** + /** * @brief Initialization function for the Q7 FIR filter. * @param[in,out] *S points to an instance of the Q7 FIR structure. * @param[in] numTaps Number of filter coefficients in the filter. @@ -1129,15 +1103,14 @@ extern "C" * @param[in] blockSize number of samples that are processed. * @return none */ - void arm_fir_init_q7( - arm_fir_instance_q7 * S, - uint16_t numTaps, - q7_t * pCoeffs, - q7_t * pState, - uint32_t blockSize); - + void arm_fir_init_q7( + arm_fir_instance_q7 *S, + uint16_t numTaps, + q7_t *pCoeffs, + q7_t *pState, + uint32_t blockSize); - /** + /** * @brief Processing function for the Q15 FIR filter. * @param[in] *S points to an instance of the Q15 FIR structure. * @param[in] *pSrc points to the block of input data. @@ -1145,13 +1118,13 @@ extern "C" * @param[in] blockSize number of samples to process. * @return none. */ - void arm_fir_q15( - const arm_fir_instance_q15 * S, - q15_t * pSrc, - q15_t * pDst, - uint32_t blockSize); + void arm_fir_q15( + const arm_fir_instance_q15 *S, + q15_t *pSrc, + q15_t *pDst, + uint32_t blockSize); - /** + /** * @brief Processing function for the fast Q15 FIR filter for Cortex-M3 and Cortex-M4. * @param[in] *S points to an instance of the Q15 FIR filter structure. * @param[in] *pSrc points to the block of input data. @@ -1159,13 +1132,13 @@ extern "C" * @param[in] blockSize number of samples to process. * @return none. */ - void arm_fir_fast_q15( - const arm_fir_instance_q15 * S, - q15_t * pSrc, - q15_t * pDst, - uint32_t blockSize); + void arm_fir_fast_q15( + const arm_fir_instance_q15 *S, + q15_t *pSrc, + q15_t *pDst, + uint32_t blockSize); - /** + /** * @brief Initialization function for the Q15 FIR filter. * @param[in,out] *S points to an instance of the Q15 FIR filter structure. * @param[in] numTaps Number of filter coefficients in the filter. Must be even and greater than or equal to 4. @@ -1176,14 +1149,14 @@ extern "C" * numTaps is not a supported value. */ - arm_status arm_fir_init_q15( - arm_fir_instance_q15 * S, - uint16_t numTaps, - q15_t * pCoeffs, - q15_t * pState, - uint32_t blockSize); + arm_status arm_fir_init_q15( + arm_fir_instance_q15 *S, + uint16_t numTaps, + q15_t *pCoeffs, + q15_t *pState, + uint32_t blockSize); - /** + /** * @brief Processing function for the Q31 FIR filter. * @param[in] *S points to an instance of the Q31 FIR filter structure. * @param[in] *pSrc points to the block of input data. @@ -1191,13 +1164,13 @@ extern "C" * @param[in] blockSize number of samples to process. * @return none. */ - void arm_fir_q31( - const arm_fir_instance_q31 * S, - q31_t * pSrc, - q31_t * pDst, - uint32_t blockSize); + void arm_fir_q31( + const arm_fir_instance_q31 *S, + q31_t *pSrc, + q31_t *pDst, + uint32_t blockSize); - /** + /** * @brief Processing function for the fast Q31 FIR filter for Cortex-M3 and Cortex-M4. * @param[in] *S points to an instance of the Q31 FIR structure. * @param[in] *pSrc points to the block of input data. @@ -1205,29 +1178,29 @@ extern "C" * @param[in] blockSize number of samples to process. * @return none. */ - void arm_fir_fast_q31( - const arm_fir_instance_q31 * S, - q31_t * pSrc, - q31_t * pDst, - uint32_t blockSize); + void arm_fir_fast_q31( + const arm_fir_instance_q31 *S, + q31_t *pSrc, + q31_t *pDst, + uint32_t blockSize); - /** + /** * @brief Initialization function for the Q31 FIR filter. * @param[in,out] *S points to an instance of the Q31 FIR structure. - * @param[in] numTaps Number of filter coefficients in the filter. - * @param[in] *pCoeffs points to the filter coefficients. - * @param[in] *pState points to the state buffer. - * @param[in] blockSize number of samples that are processed at a time. - * @return none. - */ - void arm_fir_init_q31( - arm_fir_instance_q31 * S, - uint16_t numTaps, - q31_t * pCoeffs, - q31_t * pState, - uint32_t blockSize); - - /** + * @param[in] numTaps Number of filter coefficients in the filter. + * @param[in] *pCoeffs points to the filter coefficients. + * @param[in] *pState points to the state buffer. + * @param[in] blockSize number of samples that are processed at a time. + * @return none. + */ + void arm_fir_init_q31( + arm_fir_instance_q31 *S, + uint16_t numTaps, + q31_t *pCoeffs, + q31_t *pState, + uint32_t blockSize); + + /** * @brief Processing function for the floating-point FIR filter. * @param[in] *S points to an instance of the floating-point FIR structure. * @param[in] *pSrc points to the block of input data. @@ -1235,69 +1208,64 @@ extern "C" * @param[in] blockSize number of samples to process. * @return none. */ - void arm_fir_f32( - const arm_fir_instance_f32 * S, - float32_t * pSrc, - float32_t * pDst, - uint32_t blockSize); + void arm_fir_f32( + const arm_fir_instance_f32 *S, + float32_t *pSrc, + float32_t *pDst, + uint32_t blockSize); - /** + /** * @brief Initialization function for the floating-point FIR filter. * @param[in,out] *S points to an instance of the floating-point FIR filter structure. - * @param[in] numTaps Number of filter coefficients in the filter. - * @param[in] *pCoeffs points to the filter coefficients. - * @param[in] *pState points to the state buffer. - * @param[in] blockSize number of samples that are processed at a time. - * @return none. - */ - void arm_fir_init_f32( - arm_fir_instance_f32 * S, - uint16_t numTaps, - float32_t * pCoeffs, - float32_t * pState, - uint32_t blockSize); + * @param[in] numTaps Number of filter coefficients in the filter. + * @param[in] *pCoeffs points to the filter coefficients. + * @param[in] *pState points to the state buffer. + * @param[in] blockSize number of samples that are processed at a time. + * @return none. + */ + void arm_fir_init_f32( + arm_fir_instance_f32 *S, + uint16_t numTaps, + float32_t *pCoeffs, + float32_t *pState, + uint32_t blockSize); - - /** + /** * @brief Instance structure for the Q15 Biquad cascade filter. */ - typedef struct - { - int8_t numStages; /**< number of 2nd order stages in the filter. Overall order is 2*numStages. */ - q15_t *pState; /**< Points to the array of state coefficients. The array is of length 4*numStages. */ - q15_t *pCoeffs; /**< Points to the array of coefficients. The array is of length 5*numStages. */ - int8_t postShift; /**< Additional shift, in bits, applied to each output sample. */ - - } arm_biquad_casd_df1_inst_q15; + typedef struct + { + int8_t numStages; /**< number of 2nd order stages in the filter. Overall order is 2*numStages. */ + q15_t *pState; /**< Points to the array of state coefficients. The array is of length 4*numStages. */ + q15_t *pCoeffs; /**< Points to the array of coefficients. The array is of length 5*numStages. */ + int8_t postShift; /**< Additional shift, in bits, applied to each output sample. */ + } arm_biquad_casd_df1_inst_q15; - /** + /** * @brief Instance structure for the Q31 Biquad cascade filter. */ - typedef struct - { - uint32_t numStages; /**< number of 2nd order stages in the filter. Overall order is 2*numStages. */ - q31_t *pState; /**< Points to the array of state coefficients. The array is of length 4*numStages. */ - q31_t *pCoeffs; /**< Points to the array of coefficients. The array is of length 5*numStages. */ - uint8_t postShift; /**< Additional shift, in bits, applied to each output sample. */ + typedef struct + { + uint32_t numStages; /**< number of 2nd order stages in the filter. Overall order is 2*numStages. */ + q31_t *pState; /**< Points to the array of state coefficients. The array is of length 4*numStages. */ + q31_t *pCoeffs; /**< Points to the array of coefficients. The array is of length 5*numStages. */ + uint8_t postShift; /**< Additional shift, in bits, applied to each output sample. */ - } arm_biquad_casd_df1_inst_q31; + } arm_biquad_casd_df1_inst_q31; - /** + /** * @brief Instance structure for the floating-point Biquad cascade filter. */ - typedef struct - { - uint32_t numStages; /**< number of 2nd order stages in the filter. Overall order is 2*numStages. */ - float32_t *pState; /**< Points to the array of state coefficients. The array is of length 4*numStages. */ - float32_t *pCoeffs; /**< Points to the array of coefficients. The array is of length 5*numStages. */ - - - } arm_biquad_casd_df1_inst_f32; - + typedef struct + { + uint32_t numStages; /**< number of 2nd order stages in the filter. Overall order is 2*numStages. */ + float32_t *pState; /**< Points to the array of state coefficients. The array is of length 4*numStages. */ + float32_t *pCoeffs; /**< Points to the array of coefficients. The array is of length 5*numStages. */ + } arm_biquad_casd_df1_inst_f32; - /** + /** * @brief Processing function for the Q15 Biquad cascade filter. * @param[in] *S points to an instance of the Q15 Biquad cascade structure. * @param[in] *pSrc points to the block of input data. @@ -1306,13 +1274,13 @@ extern "C" * @return none. */ - void arm_biquad_cascade_df1_q15( - const arm_biquad_casd_df1_inst_q15 * S, - q15_t * pSrc, - q15_t * pDst, - uint32_t blockSize); + void arm_biquad_cascade_df1_q15( + const arm_biquad_casd_df1_inst_q15 *S, + q15_t *pSrc, + q15_t *pDst, + uint32_t blockSize); - /** + /** * @brief Initialization function for the Q15 Biquad cascade filter. * @param[in,out] *S points to an instance of the Q15 Biquad cascade structure. * @param[in] numStages number of 2nd order stages in the filter. @@ -1322,15 +1290,14 @@ extern "C" * @return none */ - void arm_biquad_cascade_df1_init_q15( - arm_biquad_casd_df1_inst_q15 * S, - uint8_t numStages, - q15_t * pCoeffs, - q15_t * pState, - int8_t postShift); - + void arm_biquad_cascade_df1_init_q15( + arm_biquad_casd_df1_inst_q15 *S, + uint8_t numStages, + q15_t *pCoeffs, + q15_t *pState, + int8_t postShift); - /** + /** * @brief Fast but less precise processing function for the Q15 Biquad cascade filter for Cortex-M3 and Cortex-M4. * @param[in] *S points to an instance of the Q15 Biquad cascade structure. * @param[in] *pSrc points to the block of input data. @@ -1339,14 +1306,13 @@ extern "C" * @return none. */ - void arm_biquad_cascade_df1_fast_q15( - const arm_biquad_casd_df1_inst_q15 * S, - q15_t * pSrc, - q15_t * pDst, - uint32_t blockSize); - + void arm_biquad_cascade_df1_fast_q15( + const arm_biquad_casd_df1_inst_q15 *S, + q15_t *pSrc, + q15_t *pDst, + uint32_t blockSize); - /** + /** * @brief Processing function for the Q31 Biquad cascade filter * @param[in] *S points to an instance of the Q31 Biquad cascade structure. * @param[in] *pSrc points to the block of input data. @@ -1355,13 +1321,13 @@ extern "C" * @return none. */ - void arm_biquad_cascade_df1_q31( - const arm_biquad_casd_df1_inst_q31 * S, - q31_t * pSrc, - q31_t * pDst, - uint32_t blockSize); + void arm_biquad_cascade_df1_q31( + const arm_biquad_casd_df1_inst_q31 *S, + q31_t *pSrc, + q31_t *pDst, + uint32_t blockSize); - /** + /** * @brief Fast but less precise processing function for the Q31 Biquad cascade filter for Cortex-M3 and Cortex-M4. * @param[in] *S points to an instance of the Q31 Biquad cascade structure. * @param[in] *pSrc points to the block of input data. @@ -1370,13 +1336,13 @@ extern "C" * @return none. */ - void arm_biquad_cascade_df1_fast_q31( - const arm_biquad_casd_df1_inst_q31 * S, - q31_t * pSrc, - q31_t * pDst, - uint32_t blockSize); + void arm_biquad_cascade_df1_fast_q31( + const arm_biquad_casd_df1_inst_q31 *S, + q31_t *pSrc, + q31_t *pDst, + uint32_t blockSize); - /** + /** * @brief Initialization function for the Q31 Biquad cascade filter. * @param[in,out] *S points to an instance of the Q31 Biquad cascade structure. * @param[in] numStages number of 2nd order stages in the filter. @@ -1386,14 +1352,14 @@ extern "C" * @return none */ - void arm_biquad_cascade_df1_init_q31( - arm_biquad_casd_df1_inst_q31 * S, - uint8_t numStages, - q31_t * pCoeffs, - q31_t * pState, - int8_t postShift); + void arm_biquad_cascade_df1_init_q31( + arm_biquad_casd_df1_inst_q31 *S, + uint8_t numStages, + q31_t *pCoeffs, + q31_t *pState, + int8_t postShift); - /** + /** * @brief Processing function for the floating-point Biquad cascade filter. * @param[in] *S points to an instance of the floating-point Biquad cascade structure. * @param[in] *pSrc points to the block of input data. @@ -1402,13 +1368,13 @@ extern "C" * @return none. */ - void arm_biquad_cascade_df1_f32( - const arm_biquad_casd_df1_inst_f32 * S, - float32_t * pSrc, - float32_t * pDst, - uint32_t blockSize); + void arm_biquad_cascade_df1_f32( + const arm_biquad_casd_df1_inst_f32 *S, + float32_t *pSrc, + float32_t *pDst, + uint32_t blockSize); - /** + /** * @brief Initialization function for the floating-point Biquad cascade filter. * @param[in,out] *S points to an instance of the floating-point Biquad cascade structure. * @param[in] numStages number of 2nd order stages in the filter. @@ -1417,63 +1383,59 @@ extern "C" * @return none */ - void arm_biquad_cascade_df1_init_f32( - arm_biquad_casd_df1_inst_f32 * S, - uint8_t numStages, - float32_t * pCoeffs, - float32_t * pState); - + void arm_biquad_cascade_df1_init_f32( + arm_biquad_casd_df1_inst_f32 *S, + uint8_t numStages, + float32_t *pCoeffs, + float32_t *pState); - /** + /** * @brief Instance structure for the floating-point matrix structure. */ - typedef struct - { - uint16_t numRows; /**< number of rows of the matrix. */ - uint16_t numCols; /**< number of columns of the matrix. */ - float32_t *pData; /**< points to the data of the matrix. */ - } arm_matrix_instance_f32; - + typedef struct + { + uint16_t numRows; /**< number of rows of the matrix. */ + uint16_t numCols; /**< number of columns of the matrix. */ + float32_t *pData; /**< points to the data of the matrix. */ + } arm_matrix_instance_f32; - /** + /** * @brief Instance structure for the floating-point matrix structure. */ - typedef struct - { - uint16_t numRows; /**< number of rows of the matrix. */ - uint16_t numCols; /**< number of columns of the matrix. */ - float64_t *pData; /**< points to the data of the matrix. */ - } arm_matrix_instance_f64; + typedef struct + { + uint16_t numRows; /**< number of rows of the matrix. */ + uint16_t numCols; /**< number of columns of the matrix. */ + float64_t *pData; /**< points to the data of the matrix. */ + } arm_matrix_instance_f64; - /** + /** * @brief Instance structure for the Q15 matrix structure. */ - typedef struct - { - uint16_t numRows; /**< number of rows of the matrix. */ - uint16_t numCols; /**< number of columns of the matrix. */ - q15_t *pData; /**< points to the data of the matrix. */ + typedef struct + { + uint16_t numRows; /**< number of rows of the matrix. */ + uint16_t numCols; /**< number of columns of the matrix. */ + q15_t *pData; /**< points to the data of the matrix. */ - } arm_matrix_instance_q15; + } arm_matrix_instance_q15; - /** + /** * @brief Instance structure for the Q31 matrix structure. */ - typedef struct - { - uint16_t numRows; /**< number of rows of the matrix. */ - uint16_t numCols; /**< number of columns of the matrix. */ - q31_t *pData; /**< points to the data of the matrix. */ - - } arm_matrix_instance_q31; - + typedef struct + { + uint16_t numRows; /**< number of rows of the matrix. */ + uint16_t numCols; /**< number of columns of the matrix. */ + q31_t *pData; /**< points to the data of the matrix. */ + } arm_matrix_instance_q31; - /** + /** * @brief Floating-point matrix addition. * @param[in] *pSrcA points to the first input matrix structure * @param[in] *pSrcB points to the second input matrix structure @@ -1482,12 +1444,12 @@ extern "C" * ARM_MATH_SIZE_MISMATCH or ARM_MATH_SUCCESS based on the outcome of size checking. */ - arm_status arm_mat_add_f32( - const arm_matrix_instance_f32 * pSrcA, - const arm_matrix_instance_f32 * pSrcB, - arm_matrix_instance_f32 * pDst); + arm_status arm_mat_add_f32( + const arm_matrix_instance_f32 *pSrcA, + const arm_matrix_instance_f32 *pSrcB, + arm_matrix_instance_f32 *pDst); - /** + /** * @brief Q15 matrix addition. * @param[in] *pSrcA points to the first input matrix structure * @param[in] *pSrcB points to the second input matrix structure @@ -1496,12 +1458,12 @@ extern "C" * ARM_MATH_SIZE_MISMATCH or ARM_MATH_SUCCESS based on the outcome of size checking. */ - arm_status arm_mat_add_q15( - const arm_matrix_instance_q15 * pSrcA, - const arm_matrix_instance_q15 * pSrcB, - arm_matrix_instance_q15 * pDst); + arm_status arm_mat_add_q15( + const arm_matrix_instance_q15 *pSrcA, + const arm_matrix_instance_q15 *pSrcB, + arm_matrix_instance_q15 *pDst); - /** + /** * @brief Q31 matrix addition. * @param[in] *pSrcA points to the first input matrix structure * @param[in] *pSrcB points to the second input matrix structure @@ -1510,12 +1472,12 @@ extern "C" * ARM_MATH_SIZE_MISMATCH or ARM_MATH_SUCCESS based on the outcome of size checking. */ - arm_status arm_mat_add_q31( - const arm_matrix_instance_q31 * pSrcA, - const arm_matrix_instance_q31 * pSrcB, - arm_matrix_instance_q31 * pDst); + arm_status arm_mat_add_q31( + const arm_matrix_instance_q31 *pSrcA, + const arm_matrix_instance_q31 *pSrcB, + arm_matrix_instance_q31 *pDst); - /** + /** * @brief Floating-point, complex, matrix multiplication. * @param[in] *pSrcA points to the first input matrix structure * @param[in] *pSrcB points to the second input matrix structure @@ -1524,12 +1486,12 @@ extern "C" * ARM_MATH_SIZE_MISMATCH or ARM_MATH_SUCCESS based on the outcome of size checking. */ - arm_status arm_mat_cmplx_mult_f32( - const arm_matrix_instance_f32 * pSrcA, - const arm_matrix_instance_f32 * pSrcB, - arm_matrix_instance_f32 * pDst); + arm_status arm_mat_cmplx_mult_f32( + const arm_matrix_instance_f32 *pSrcA, + const arm_matrix_instance_f32 *pSrcB, + arm_matrix_instance_f32 *pDst); - /** + /** * @brief Q15, complex, matrix multiplication. * @param[in] *pSrcA points to the first input matrix structure * @param[in] *pSrcB points to the second input matrix structure @@ -1538,13 +1500,13 @@ extern "C" * ARM_MATH_SIZE_MISMATCH or ARM_MATH_SUCCESS based on the outcome of size checking. */ - arm_status arm_mat_cmplx_mult_q15( - const arm_matrix_instance_q15 * pSrcA, - const arm_matrix_instance_q15 * pSrcB, - arm_matrix_instance_q15 * pDst, - q15_t * pScratch); + arm_status arm_mat_cmplx_mult_q15( + const arm_matrix_instance_q15 *pSrcA, + const arm_matrix_instance_q15 *pSrcB, + arm_matrix_instance_q15 *pDst, + q15_t *pScratch); - /** + /** * @brief Q31, complex, matrix multiplication. * @param[in] *pSrcA points to the first input matrix structure * @param[in] *pSrcB points to the second input matrix structure @@ -1553,51 +1515,48 @@ extern "C" * ARM_MATH_SIZE_MISMATCH or ARM_MATH_SUCCESS based on the outcome of size checking. */ - arm_status arm_mat_cmplx_mult_q31( - const arm_matrix_instance_q31 * pSrcA, - const arm_matrix_instance_q31 * pSrcB, - arm_matrix_instance_q31 * pDst); - + arm_status arm_mat_cmplx_mult_q31( + const arm_matrix_instance_q31 *pSrcA, + const arm_matrix_instance_q31 *pSrcB, + arm_matrix_instance_q31 *pDst); - /** + /** * @brief Floating-point matrix transpose. * @param[in] *pSrc points to the input matrix * @param[out] *pDst points to the output matrix - * @return The function returns either ARM_MATH_SIZE_MISMATCH + * @return The function returns either ARM_MATH_SIZE_MISMATCH * or ARM_MATH_SUCCESS based on the outcome of size checking. */ - arm_status arm_mat_trans_f32( - const arm_matrix_instance_f32 * pSrc, - arm_matrix_instance_f32 * pDst); - + arm_status arm_mat_trans_f32( + const arm_matrix_instance_f32 *pSrc, + arm_matrix_instance_f32 *pDst); - /** + /** * @brief Q15 matrix transpose. * @param[in] *pSrc points to the input matrix * @param[out] *pDst points to the output matrix - * @return The function returns either ARM_MATH_SIZE_MISMATCH + * @return The function returns either ARM_MATH_SIZE_MISMATCH * or ARM_MATH_SUCCESS based on the outcome of size checking. */ - arm_status arm_mat_trans_q15( - const arm_matrix_instance_q15 * pSrc, - arm_matrix_instance_q15 * pDst); + arm_status arm_mat_trans_q15( + const arm_matrix_instance_q15 *pSrc, + arm_matrix_instance_q15 *pDst); - /** + /** * @brief Q31 matrix transpose. * @param[in] *pSrc points to the input matrix * @param[out] *pDst points to the output matrix - * @return The function returns either ARM_MATH_SIZE_MISMATCH + * @return The function returns either ARM_MATH_SIZE_MISMATCH * or ARM_MATH_SUCCESS based on the outcome of size checking. */ - arm_status arm_mat_trans_q31( - const arm_matrix_instance_q31 * pSrc, - arm_matrix_instance_q31 * pDst); + arm_status arm_mat_trans_q31( + const arm_matrix_instance_q31 *pSrc, + arm_matrix_instance_q31 *pDst); - - /** + /** * @brief Floating-point matrix multiplication * @param[in] *pSrcA points to the first input matrix structure * @param[in] *pSrcB points to the second input matrix structure @@ -1606,44 +1565,44 @@ extern "C" * ARM_MATH_SIZE_MISMATCH or ARM_MATH_SUCCESS based on the outcome of size checking. */ - arm_status arm_mat_mult_f32( - const arm_matrix_instance_f32 * pSrcA, - const arm_matrix_instance_f32 * pSrcB, - arm_matrix_instance_f32 * pDst); + arm_status arm_mat_mult_f32( + const arm_matrix_instance_f32 *pSrcA, + const arm_matrix_instance_f32 *pSrcB, + arm_matrix_instance_f32 *pDst); - /** + /** * @brief Q15 matrix multiplication * @param[in] *pSrcA points to the first input matrix structure * @param[in] *pSrcB points to the second input matrix structure * @param[out] *pDst points to output matrix structure - * @param[in] *pState points to the array for storing intermediate results + * @param[in] *pState points to the array for storing intermediate results * @return The function returns either * ARM_MATH_SIZE_MISMATCH or ARM_MATH_SUCCESS based on the outcome of size checking. */ - arm_status arm_mat_mult_q15( - const arm_matrix_instance_q15 * pSrcA, - const arm_matrix_instance_q15 * pSrcB, - arm_matrix_instance_q15 * pDst, - q15_t * pState); + arm_status arm_mat_mult_q15( + const arm_matrix_instance_q15 *pSrcA, + const arm_matrix_instance_q15 *pSrcB, + arm_matrix_instance_q15 *pDst, + q15_t *pState); - /** + /** * @brief Q15 matrix multiplication (fast variant) for Cortex-M3 and Cortex-M4 * @param[in] *pSrcA points to the first input matrix structure * @param[in] *pSrcB points to the second input matrix structure * @param[out] *pDst points to output matrix structure - * @param[in] *pState points to the array for storing intermediate results + * @param[in] *pState points to the array for storing intermediate results * @return The function returns either * ARM_MATH_SIZE_MISMATCH or ARM_MATH_SUCCESS based on the outcome of size checking. */ - arm_status arm_mat_mult_fast_q15( - const arm_matrix_instance_q15 * pSrcA, - const arm_matrix_instance_q15 * pSrcB, - arm_matrix_instance_q15 * pDst, - q15_t * pState); + arm_status arm_mat_mult_fast_q15( + const arm_matrix_instance_q15 *pSrcA, + const arm_matrix_instance_q15 *pSrcB, + arm_matrix_instance_q15 *pDst, + q15_t *pState); - /** + /** * @brief Q31 matrix multiplication * @param[in] *pSrcA points to the first input matrix structure * @param[in] *pSrcB points to the second input matrix structure @@ -1652,12 +1611,12 @@ extern "C" * ARM_MATH_SIZE_MISMATCH or ARM_MATH_SUCCESS based on the outcome of size checking. */ - arm_status arm_mat_mult_q31( - const arm_matrix_instance_q31 * pSrcA, - const arm_matrix_instance_q31 * pSrcB, - arm_matrix_instance_q31 * pDst); + arm_status arm_mat_mult_q31( + const arm_matrix_instance_q31 *pSrcA, + const arm_matrix_instance_q31 *pSrcB, + arm_matrix_instance_q31 *pDst); - /** + /** * @brief Q31 matrix multiplication (fast variant) for Cortex-M3 and Cortex-M4 * @param[in] *pSrcA points to the first input matrix structure * @param[in] *pSrcB points to the second input matrix structure @@ -1666,13 +1625,12 @@ extern "C" * ARM_MATH_SIZE_MISMATCH or ARM_MATH_SUCCESS based on the outcome of size checking. */ - arm_status arm_mat_mult_fast_q31( - const arm_matrix_instance_q31 * pSrcA, - const arm_matrix_instance_q31 * pSrcB, - arm_matrix_instance_q31 * pDst); + arm_status arm_mat_mult_fast_q31( + const arm_matrix_instance_q31 *pSrcA, + const arm_matrix_instance_q31 *pSrcB, + arm_matrix_instance_q31 *pDst); - - /** + /** * @brief Floating-point matrix subtraction * @param[in] *pSrcA points to the first input matrix structure * @param[in] *pSrcB points to the second input matrix structure @@ -1681,12 +1639,12 @@ extern "C" * ARM_MATH_SIZE_MISMATCH or ARM_MATH_SUCCESS based on the outcome of size checking. */ - arm_status arm_mat_sub_f32( - const arm_matrix_instance_f32 * pSrcA, - const arm_matrix_instance_f32 * pSrcB, - arm_matrix_instance_f32 * pDst); + arm_status arm_mat_sub_f32( + const arm_matrix_instance_f32 *pSrcA, + const arm_matrix_instance_f32 *pSrcB, + arm_matrix_instance_f32 *pDst); - /** + /** * @brief Q15 matrix subtraction * @param[in] *pSrcA points to the first input matrix structure * @param[in] *pSrcB points to the second input matrix structure @@ -1695,12 +1653,12 @@ extern "C" * ARM_MATH_SIZE_MISMATCH or ARM_MATH_SUCCESS based on the outcome of size checking. */ - arm_status arm_mat_sub_q15( - const arm_matrix_instance_q15 * pSrcA, - const arm_matrix_instance_q15 * pSrcB, - arm_matrix_instance_q15 * pDst); + arm_status arm_mat_sub_q15( + const arm_matrix_instance_q15 *pSrcA, + const arm_matrix_instance_q15 *pSrcB, + arm_matrix_instance_q15 *pDst); - /** + /** * @brief Q31 matrix subtraction * @param[in] *pSrcA points to the first input matrix structure * @param[in] *pSrcB points to the second input matrix structure @@ -1709,12 +1667,12 @@ extern "C" * ARM_MATH_SIZE_MISMATCH or ARM_MATH_SUCCESS based on the outcome of size checking. */ - arm_status arm_mat_sub_q31( - const arm_matrix_instance_q31 * pSrcA, - const arm_matrix_instance_q31 * pSrcB, - arm_matrix_instance_q31 * pDst); + arm_status arm_mat_sub_q31( + const arm_matrix_instance_q31 *pSrcA, + const arm_matrix_instance_q31 *pSrcB, + arm_matrix_instance_q31 *pDst); - /** + /** * @brief Floating-point matrix scaling. * @param[in] *pSrc points to the input matrix * @param[in] scale scale factor @@ -1723,12 +1681,12 @@ extern "C" * ARM_MATH_SIZE_MISMATCH or ARM_MATH_SUCCESS based on the outcome of size checking. */ - arm_status arm_mat_scale_f32( - const arm_matrix_instance_f32 * pSrc, - float32_t scale, - arm_matrix_instance_f32 * pDst); + arm_status arm_mat_scale_f32( + const arm_matrix_instance_f32 *pSrc, + float32_t scale, + arm_matrix_instance_f32 *pDst); - /** + /** * @brief Q15 matrix scaling. * @param[in] *pSrc points to input matrix * @param[in] scaleFract fractional portion of the scale factor @@ -1738,13 +1696,13 @@ extern "C" * ARM_MATH_SIZE_MISMATCH or ARM_MATH_SUCCESS based on the outcome of size checking. */ - arm_status arm_mat_scale_q15( - const arm_matrix_instance_q15 * pSrc, - q15_t scaleFract, - int32_t shift, - arm_matrix_instance_q15 * pDst); + arm_status arm_mat_scale_q15( + const arm_matrix_instance_q15 *pSrc, + q15_t scaleFract, + int32_t shift, + arm_matrix_instance_q15 *pDst); - /** + /** * @brief Q31 matrix scaling. * @param[in] *pSrc points to input matrix * @param[in] scaleFract fractional portion of the scale factor @@ -1754,224 +1712,215 @@ extern "C" * ARM_MATH_SIZE_MISMATCH or ARM_MATH_SUCCESS based on the outcome of size checking. */ - arm_status arm_mat_scale_q31( - const arm_matrix_instance_q31 * pSrc, - q31_t scaleFract, - int32_t shift, - arm_matrix_instance_q31 * pDst); - + arm_status arm_mat_scale_q31( + const arm_matrix_instance_q31 *pSrc, + q31_t scaleFract, + int32_t shift, + arm_matrix_instance_q31 *pDst); - /** + /** * @brief Q31 matrix initialization. * @param[in,out] *S points to an instance of the floating-point matrix structure. * @param[in] nRows number of rows in the matrix. * @param[in] nColumns number of columns in the matrix. - * @param[in] *pData points to the matrix data array. + * @param[in] *pData points to the matrix data array. * @return none */ - void arm_mat_init_q31( - arm_matrix_instance_q31 * S, - uint16_t nRows, - uint16_t nColumns, - q31_t * pData); + void arm_mat_init_q31( + arm_matrix_instance_q31 *S, + uint16_t nRows, + uint16_t nColumns, + q31_t *pData); - /** + /** * @brief Q15 matrix initialization. * @param[in,out] *S points to an instance of the floating-point matrix structure. * @param[in] nRows number of rows in the matrix. * @param[in] nColumns number of columns in the matrix. - * @param[in] *pData points to the matrix data array. + * @param[in] *pData points to the matrix data array. * @return none */ - void arm_mat_init_q15( - arm_matrix_instance_q15 * S, - uint16_t nRows, - uint16_t nColumns, - q15_t * pData); + void arm_mat_init_q15( + arm_matrix_instance_q15 *S, + uint16_t nRows, + uint16_t nColumns, + q15_t *pData); - /** + /** * @brief Floating-point matrix initialization. * @param[in,out] *S points to an instance of the floating-point matrix structure. * @param[in] nRows number of rows in the matrix. * @param[in] nColumns number of columns in the matrix. - * @param[in] *pData points to the matrix data array. + * @param[in] *pData points to the matrix data array. * @return none */ - void arm_mat_init_f32( - arm_matrix_instance_f32 * S, - uint16_t nRows, - uint16_t nColumns, - float32_t * pData); - + void arm_mat_init_f32( + arm_matrix_instance_f32 *S, + uint16_t nRows, + uint16_t nColumns, + float32_t *pData); - - /** + /** * @brief Instance structure for the Q15 PID Control. */ - typedef struct - { - q15_t A0; /**< The derived gain, A0 = Kp + Ki + Kd . */ + typedef struct + { + q15_t A0; /**< The derived gain, A0 = Kp + Ki + Kd . */ #ifdef ARM_MATH_CM0_FAMILY - q15_t A1; - q15_t A2; + q15_t A1; + q15_t A2; #else - q31_t A1; /**< The derived gain A1 = -Kp - 2Kd | Kd.*/ + q31_t A1; /**< The derived gain A1 = -Kp - 2Kd | Kd.*/ #endif - q15_t state[3]; /**< The state array of length 3. */ - q15_t Kp; /**< The proportional gain. */ - q15_t Ki; /**< The integral gain. */ - q15_t Kd; /**< The derivative gain. */ - } arm_pid_instance_q15; + q15_t state[3]; /**< The state array of length 3. */ + q15_t Kp; /**< The proportional gain. */ + q15_t Ki; /**< The integral gain. */ + q15_t Kd; /**< The derivative gain. */ + } arm_pid_instance_q15; - /** + /** * @brief Instance structure for the Q31 PID Control. */ - typedef struct - { - q31_t A0; /**< The derived gain, A0 = Kp + Ki + Kd . */ - q31_t A1; /**< The derived gain, A1 = -Kp - 2Kd. */ - q31_t A2; /**< The derived gain, A2 = Kd . */ - q31_t state[3]; /**< The state array of length 3. */ - q31_t Kp; /**< The proportional gain. */ - q31_t Ki; /**< The integral gain. */ - q31_t Kd; /**< The derivative gain. */ + typedef struct + { + q31_t A0; /**< The derived gain, A0 = Kp + Ki + Kd . */ + q31_t A1; /**< The derived gain, A1 = -Kp - 2Kd. */ + q31_t A2; /**< The derived gain, A2 = Kd . */ + q31_t state[3]; /**< The state array of length 3. */ + q31_t Kp; /**< The proportional gain. */ + q31_t Ki; /**< The integral gain. */ + q31_t Kd; /**< The derivative gain. */ - } arm_pid_instance_q31; + } arm_pid_instance_q31; - /** + /** * @brief Instance structure for the floating-point PID Control. */ - typedef struct - { - float32_t A0; /**< The derived gain, A0 = Kp + Ki + Kd . */ - float32_t A1; /**< The derived gain, A1 = -Kp - 2Kd. */ - float32_t A2; /**< The derived gain, A2 = Kd . */ - float32_t state[3]; /**< The state array of length 3. */ - float32_t Kp; /**< The proportional gain. */ - float32_t Ki; /**< The integral gain. */ - float32_t Kd; /**< The derivative gain. */ - } arm_pid_instance_f32; - - + typedef struct + { + float32_t A0; /**< The derived gain, A0 = Kp + Ki + Kd . */ + float32_t A1; /**< The derived gain, A1 = -Kp - 2Kd. */ + float32_t A2; /**< The derived gain, A2 = Kd . */ + float32_t state[3]; /**< The state array of length 3. */ + float32_t Kp; /**< The proportional gain. */ + float32_t Ki; /**< The integral gain. */ + float32_t Kd; /**< The derivative gain. */ + } arm_pid_instance_f32; - /** + /** * @brief Initialization function for the floating-point PID Control. * @param[in,out] *S points to an instance of the PID structure. * @param[in] resetStateFlag flag to reset the state. 0 = no change in state 1 = reset the state. * @return none. */ - void arm_pid_init_f32( - arm_pid_instance_f32 * S, - int32_t resetStateFlag); + void arm_pid_init_f32( + arm_pid_instance_f32 *S, + int32_t resetStateFlag); - /** + /** * @brief Reset function for the floating-point PID Control. * @param[in,out] *S is an instance of the floating-point PID Control structure * @return none */ - void arm_pid_reset_f32( - arm_pid_instance_f32 * S); - + void arm_pid_reset_f32( + arm_pid_instance_f32 *S); - /** + /** * @brief Initialization function for the Q31 PID Control. * @param[in,out] *S points to an instance of the Q15 PID structure. * @param[in] resetStateFlag flag to reset the state. 0 = no change in state 1 = reset the state. * @return none. */ - void arm_pid_init_q31( - arm_pid_instance_q31 * S, - int32_t resetStateFlag); - + void arm_pid_init_q31( + arm_pid_instance_q31 *S, + int32_t resetStateFlag); - /** + /** * @brief Reset function for the Q31 PID Control. * @param[in,out] *S points to an instance of the Q31 PID Control structure * @return none */ - void arm_pid_reset_q31( - arm_pid_instance_q31 * S); + void arm_pid_reset_q31( + arm_pid_instance_q31 *S); - /** + /** * @brief Initialization function for the Q15 PID Control. * @param[in,out] *S points to an instance of the Q15 PID structure. * @param[in] resetStateFlag flag to reset the state. 0 = no change in state 1 = reset the state. * @return none. */ - void arm_pid_init_q15( - arm_pid_instance_q15 * S, - int32_t resetStateFlag); + void arm_pid_init_q15( + arm_pid_instance_q15 *S, + int32_t resetStateFlag); - /** + /** * @brief Reset function for the Q15 PID Control. * @param[in,out] *S points to an instance of the q15 PID Control structure * @return none */ - void arm_pid_reset_q15( - arm_pid_instance_q15 * S); - + void arm_pid_reset_q15( + arm_pid_instance_q15 *S); - /** + /** * @brief Instance structure for the floating-point Linear Interpolate function. */ - typedef struct - { - uint32_t nValues; /**< nValues */ - float32_t x1; /**< x1 */ - float32_t xSpacing; /**< xSpacing */ - float32_t *pYData; /**< pointer to the table of Y values */ - } arm_linear_interp_instance_f32; + typedef struct + { + uint32_t nValues; /**< nValues */ + float32_t x1; /**< x1 */ + float32_t xSpacing; /**< xSpacing */ + float32_t *pYData; /**< pointer to the table of Y values */ + } arm_linear_interp_instance_f32; - /** + /** * @brief Instance structure for the floating-point bilinear interpolation function. */ - typedef struct - { - uint16_t numRows; /**< number of rows in the data table. */ - uint16_t numCols; /**< number of columns in the data table. */ - float32_t *pData; /**< points to the data table. */ - } arm_bilinear_interp_instance_f32; + typedef struct + { + uint16_t numRows; /**< number of rows in the data table. */ + uint16_t numCols; /**< number of columns in the data table. */ + float32_t *pData; /**< points to the data table. */ + } arm_bilinear_interp_instance_f32; - /** + /** * @brief Instance structure for the Q31 bilinear interpolation function. */ - typedef struct - { - uint16_t numRows; /**< number of rows in the data table. */ - uint16_t numCols; /**< number of columns in the data table. */ - q31_t *pData; /**< points to the data table. */ - } arm_bilinear_interp_instance_q31; + typedef struct + { + uint16_t numRows; /**< number of rows in the data table. */ + uint16_t numCols; /**< number of columns in the data table. */ + q31_t *pData; /**< points to the data table. */ + } arm_bilinear_interp_instance_q31; - /** + /** * @brief Instance structure for the Q15 bilinear interpolation function. */ - typedef struct - { - uint16_t numRows; /**< number of rows in the data table. */ - uint16_t numCols; /**< number of columns in the data table. */ - q15_t *pData; /**< points to the data table. */ - } arm_bilinear_interp_instance_q15; + typedef struct + { + uint16_t numRows; /**< number of rows in the data table. */ + uint16_t numCols; /**< number of columns in the data table. */ + q15_t *pData; /**< points to the data table. */ + } arm_bilinear_interp_instance_q15; - /** + /** * @brief Instance structure for the Q15 bilinear interpolation function. */ - typedef struct - { - uint16_t numRows; /**< number of rows in the data table. */ - uint16_t numCols; /**< number of columns in the data table. */ - q7_t *pData; /**< points to the data table. */ - } arm_bilinear_interp_instance_q7; - + typedef struct + { + uint16_t numRows; /**< number of rows in the data table. */ + uint16_t numCols; /**< number of columns in the data table. */ + q7_t *pData; /**< points to the data table. */ + } arm_bilinear_interp_instance_q7; - /** + /** * @brief Q7 vector multiplication. * @param[in] *pSrcA points to the first input vector * @param[in] *pSrcB points to the second input vector @@ -1980,13 +1929,13 @@ extern "C" * @return none. */ - void arm_mult_q7( - q7_t * pSrcA, - q7_t * pSrcB, - q7_t * pDst, - uint32_t blockSize); + void arm_mult_q7( + q7_t *pSrcA, + q7_t *pSrcB, + q7_t *pDst, + uint32_t blockSize); - /** + /** * @brief Q15 vector multiplication. * @param[in] *pSrcA points to the first input vector * @param[in] *pSrcB points to the second input vector @@ -1995,13 +1944,13 @@ extern "C" * @return none. */ - void arm_mult_q15( - q15_t * pSrcA, - q15_t * pSrcB, - q15_t * pDst, - uint32_t blockSize); + void arm_mult_q15( + q15_t *pSrcA, + q15_t *pSrcB, + q15_t *pDst, + uint32_t blockSize); - /** + /** * @brief Q31 vector multiplication. * @param[in] *pSrcA points to the first input vector * @param[in] *pSrcB points to the second input vector @@ -2010,13 +1959,13 @@ extern "C" * @return none. */ - void arm_mult_q31( - q31_t * pSrcA, - q31_t * pSrcB, - q31_t * pDst, - uint32_t blockSize); + void arm_mult_q31( + q31_t *pSrcA, + q31_t *pSrcB, + q31_t *pDst, + uint32_t blockSize); - /** + /** * @brief Floating-point vector multiplication. * @param[in] *pSrcA points to the first input vector * @param[in] *pSrcB points to the second input vector @@ -2025,353 +1974,346 @@ extern "C" * @return none. */ - void arm_mult_f32( - float32_t * pSrcA, - float32_t * pSrcB, - float32_t * pDst, - uint32_t blockSize); - - - + void arm_mult_f32( + float32_t *pSrcA, + float32_t *pSrcB, + float32_t *pDst, + uint32_t blockSize); + /** + * @brief Instance structure for the Q15 CFFT/CIFFT function. + */ + typedef struct + { + uint16_t fftLen; /**< length of the FFT. */ + uint8_t ifftFlag; /**< flag that selects forward (ifftFlag=0) or inverse (ifftFlag=1) transform. */ + uint8_t bitReverseFlag; /**< flag that enables (bitReverseFlag=1) or disables (bitReverseFlag=0) bit reversal of output. */ + q15_t *pTwiddle; /**< points to the Sin twiddle factor table. */ + uint16_t *pBitRevTable; /**< points to the bit reversal table. */ + uint16_t twidCoefModifier; /**< twiddle coefficient modifier that supports different size FFTs with the same twiddle factor table. */ + uint16_t bitRevFactor; /**< bit reversal modifier that supports different size FFTs with the same bit reversal table. */ + } arm_cfft_radix2_instance_q15; + + /* Deprecated */ + arm_status arm_cfft_radix2_init_q15( + arm_cfft_radix2_instance_q15 *S, + uint16_t fftLen, + uint8_t ifftFlag, + uint8_t bitReverseFlag); + + /* Deprecated */ + void arm_cfft_radix2_q15( + const arm_cfft_radix2_instance_q15 *S, + q15_t *pSrc); - /** + /** * @brief Instance structure for the Q15 CFFT/CIFFT function. */ - typedef struct - { - uint16_t fftLen; /**< length of the FFT. */ - uint8_t ifftFlag; /**< flag that selects forward (ifftFlag=0) or inverse (ifftFlag=1) transform. */ - uint8_t bitReverseFlag; /**< flag that enables (bitReverseFlag=1) or disables (bitReverseFlag=0) bit reversal of output. */ - q15_t *pTwiddle; /**< points to the Sin twiddle factor table. */ - uint16_t *pBitRevTable; /**< points to the bit reversal table. */ - uint16_t twidCoefModifier; /**< twiddle coefficient modifier that supports different size FFTs with the same twiddle factor table. */ - uint16_t bitRevFactor; /**< bit reversal modifier that supports different size FFTs with the same bit reversal table. */ - } arm_cfft_radix2_instance_q15; - -/* Deprecated */ - arm_status arm_cfft_radix2_init_q15( - arm_cfft_radix2_instance_q15 * S, - uint16_t fftLen, - uint8_t ifftFlag, - uint8_t bitReverseFlag); - -/* Deprecated */ - void arm_cfft_radix2_q15( - const arm_cfft_radix2_instance_q15 * S, - q15_t * pSrc); - - - - /** - * @brief Instance structure for the Q15 CFFT/CIFFT function. - */ + typedef struct + { + uint16_t fftLen; /**< length of the FFT. */ + uint8_t ifftFlag; /**< flag that selects forward (ifftFlag=0) or inverse (ifftFlag=1) transform. */ + uint8_t bitReverseFlag; /**< flag that enables (bitReverseFlag=1) or disables (bitReverseFlag=0) bit reversal of output. */ + q15_t *pTwiddle; /**< points to the twiddle factor table. */ + uint16_t *pBitRevTable; /**< points to the bit reversal table. */ + uint16_t twidCoefModifier; /**< twiddle coefficient modifier that supports different size FFTs with the same twiddle factor table. */ + uint16_t bitRevFactor; /**< bit reversal modifier that supports different size FFTs with the same bit reversal table. */ + } arm_cfft_radix4_instance_q15; + + /* Deprecated */ + arm_status arm_cfft_radix4_init_q15( + arm_cfft_radix4_instance_q15 *S, + uint16_t fftLen, + uint8_t ifftFlag, + uint8_t bitReverseFlag); + + /* Deprecated */ + void arm_cfft_radix4_q15( + const arm_cfft_radix4_instance_q15 *S, + q15_t *pSrc); - typedef struct - { - uint16_t fftLen; /**< length of the FFT. */ - uint8_t ifftFlag; /**< flag that selects forward (ifftFlag=0) or inverse (ifftFlag=1) transform. */ - uint8_t bitReverseFlag; /**< flag that enables (bitReverseFlag=1) or disables (bitReverseFlag=0) bit reversal of output. */ - q15_t *pTwiddle; /**< points to the twiddle factor table. */ - uint16_t *pBitRevTable; /**< points to the bit reversal table. */ - uint16_t twidCoefModifier; /**< twiddle coefficient modifier that supports different size FFTs with the same twiddle factor table. */ - uint16_t bitRevFactor; /**< bit reversal modifier that supports different size FFTs with the same bit reversal table. */ - } arm_cfft_radix4_instance_q15; - -/* Deprecated */ - arm_status arm_cfft_radix4_init_q15( - arm_cfft_radix4_instance_q15 * S, - uint16_t fftLen, - uint8_t ifftFlag, - uint8_t bitReverseFlag); - -/* Deprecated */ - void arm_cfft_radix4_q15( - const arm_cfft_radix4_instance_q15 * S, - q15_t * pSrc); - - /** + /** * @brief Instance structure for the Radix-2 Q31 CFFT/CIFFT function. */ - typedef struct - { - uint16_t fftLen; /**< length of the FFT. */ - uint8_t ifftFlag; /**< flag that selects forward (ifftFlag=0) or inverse (ifftFlag=1) transform. */ - uint8_t bitReverseFlag; /**< flag that enables (bitReverseFlag=1) or disables (bitReverseFlag=0) bit reversal of output. */ - q31_t *pTwiddle; /**< points to the Twiddle factor table. */ - uint16_t *pBitRevTable; /**< points to the bit reversal table. */ - uint16_t twidCoefModifier; /**< twiddle coefficient modifier that supports different size FFTs with the same twiddle factor table. */ - uint16_t bitRevFactor; /**< bit reversal modifier that supports different size FFTs with the same bit reversal table. */ - } arm_cfft_radix2_instance_q31; - -/* Deprecated */ - arm_status arm_cfft_radix2_init_q31( - arm_cfft_radix2_instance_q31 * S, - uint16_t fftLen, - uint8_t ifftFlag, - uint8_t bitReverseFlag); - -/* Deprecated */ - void arm_cfft_radix2_q31( - const arm_cfft_radix2_instance_q31 * S, - q31_t * pSrc); - - /** + typedef struct + { + uint16_t fftLen; /**< length of the FFT. */ + uint8_t ifftFlag; /**< flag that selects forward (ifftFlag=0) or inverse (ifftFlag=1) transform. */ + uint8_t bitReverseFlag; /**< flag that enables (bitReverseFlag=1) or disables (bitReverseFlag=0) bit reversal of output. */ + q31_t *pTwiddle; /**< points to the Twiddle factor table. */ + uint16_t *pBitRevTable; /**< points to the bit reversal table. */ + uint16_t twidCoefModifier; /**< twiddle coefficient modifier that supports different size FFTs with the same twiddle factor table. */ + uint16_t bitRevFactor; /**< bit reversal modifier that supports different size FFTs with the same bit reversal table. */ + } arm_cfft_radix2_instance_q31; + + /* Deprecated */ + arm_status arm_cfft_radix2_init_q31( + arm_cfft_radix2_instance_q31 *S, + uint16_t fftLen, + uint8_t ifftFlag, + uint8_t bitReverseFlag); + + /* Deprecated */ + void arm_cfft_radix2_q31( + const arm_cfft_radix2_instance_q31 *S, + q31_t *pSrc); + + /** * @brief Instance structure for the Q31 CFFT/CIFFT function. */ - typedef struct - { - uint16_t fftLen; /**< length of the FFT. */ - uint8_t ifftFlag; /**< flag that selects forward (ifftFlag=0) or inverse (ifftFlag=1) transform. */ - uint8_t bitReverseFlag; /**< flag that enables (bitReverseFlag=1) or disables (bitReverseFlag=0) bit reversal of output. */ - q31_t *pTwiddle; /**< points to the twiddle factor table. */ - uint16_t *pBitRevTable; /**< points to the bit reversal table. */ - uint16_t twidCoefModifier; /**< twiddle coefficient modifier that supports different size FFTs with the same twiddle factor table. */ - uint16_t bitRevFactor; /**< bit reversal modifier that supports different size FFTs with the same bit reversal table. */ - } arm_cfft_radix4_instance_q31; - -/* Deprecated */ - void arm_cfft_radix4_q31( - const arm_cfft_radix4_instance_q31 * S, - q31_t * pSrc); - -/* Deprecated */ - arm_status arm_cfft_radix4_init_q31( - arm_cfft_radix4_instance_q31 * S, - uint16_t fftLen, - uint8_t ifftFlag, - uint8_t bitReverseFlag); - - /** + typedef struct + { + uint16_t fftLen; /**< length of the FFT. */ + uint8_t ifftFlag; /**< flag that selects forward (ifftFlag=0) or inverse (ifftFlag=1) transform. */ + uint8_t bitReverseFlag; /**< flag that enables (bitReverseFlag=1) or disables (bitReverseFlag=0) bit reversal of output. */ + q31_t *pTwiddle; /**< points to the twiddle factor table. */ + uint16_t *pBitRevTable; /**< points to the bit reversal table. */ + uint16_t twidCoefModifier; /**< twiddle coefficient modifier that supports different size FFTs with the same twiddle factor table. */ + uint16_t bitRevFactor; /**< bit reversal modifier that supports different size FFTs with the same bit reversal table. */ + } arm_cfft_radix4_instance_q31; + + /* Deprecated */ + void arm_cfft_radix4_q31( + const arm_cfft_radix4_instance_q31 *S, + q31_t *pSrc); + + /* Deprecated */ + arm_status arm_cfft_radix4_init_q31( + arm_cfft_radix4_instance_q31 *S, + uint16_t fftLen, + uint8_t ifftFlag, + uint8_t bitReverseFlag); + + /** * @brief Instance structure for the floating-point CFFT/CIFFT function. */ - typedef struct - { - uint16_t fftLen; /**< length of the FFT. */ - uint8_t ifftFlag; /**< flag that selects forward (ifftFlag=0) or inverse (ifftFlag=1) transform. */ - uint8_t bitReverseFlag; /**< flag that enables (bitReverseFlag=1) or disables (bitReverseFlag=0) bit reversal of output. */ - float32_t *pTwiddle; /**< points to the Twiddle factor table. */ - uint16_t *pBitRevTable; /**< points to the bit reversal table. */ - uint16_t twidCoefModifier; /**< twiddle coefficient modifier that supports different size FFTs with the same twiddle factor table. */ - uint16_t bitRevFactor; /**< bit reversal modifier that supports different size FFTs with the same bit reversal table. */ - float32_t onebyfftLen; /**< value of 1/fftLen. */ - } arm_cfft_radix2_instance_f32; - -/* Deprecated */ - arm_status arm_cfft_radix2_init_f32( - arm_cfft_radix2_instance_f32 * S, - uint16_t fftLen, - uint8_t ifftFlag, - uint8_t bitReverseFlag); - -/* Deprecated */ - void arm_cfft_radix2_f32( - const arm_cfft_radix2_instance_f32 * S, - float32_t * pSrc); - - /** + typedef struct + { + uint16_t fftLen; /**< length of the FFT. */ + uint8_t ifftFlag; /**< flag that selects forward (ifftFlag=0) or inverse (ifftFlag=1) transform. */ + uint8_t bitReverseFlag; /**< flag that enables (bitReverseFlag=1) or disables (bitReverseFlag=0) bit reversal of output. */ + float32_t *pTwiddle; /**< points to the Twiddle factor table. */ + uint16_t *pBitRevTable; /**< points to the bit reversal table. */ + uint16_t twidCoefModifier; /**< twiddle coefficient modifier that supports different size FFTs with the same twiddle factor table. */ + uint16_t bitRevFactor; /**< bit reversal modifier that supports different size FFTs with the same bit reversal table. */ + float32_t onebyfftLen; /**< value of 1/fftLen. */ + } arm_cfft_radix2_instance_f32; + + /* Deprecated */ + arm_status arm_cfft_radix2_init_f32( + arm_cfft_radix2_instance_f32 *S, + uint16_t fftLen, + uint8_t ifftFlag, + uint8_t bitReverseFlag); + + /* Deprecated */ + void arm_cfft_radix2_f32( + const arm_cfft_radix2_instance_f32 *S, + float32_t *pSrc); + + /** * @brief Instance structure for the floating-point CFFT/CIFFT function. */ - typedef struct - { - uint16_t fftLen; /**< length of the FFT. */ - uint8_t ifftFlag; /**< flag that selects forward (ifftFlag=0) or inverse (ifftFlag=1) transform. */ - uint8_t bitReverseFlag; /**< flag that enables (bitReverseFlag=1) or disables (bitReverseFlag=0) bit reversal of output. */ - float32_t *pTwiddle; /**< points to the Twiddle factor table. */ - uint16_t *pBitRevTable; /**< points to the bit reversal table. */ - uint16_t twidCoefModifier; /**< twiddle coefficient modifier that supports different size FFTs with the same twiddle factor table. */ - uint16_t bitRevFactor; /**< bit reversal modifier that supports different size FFTs with the same bit reversal table. */ - float32_t onebyfftLen; /**< value of 1/fftLen. */ - } arm_cfft_radix4_instance_f32; - -/* Deprecated */ - arm_status arm_cfft_radix4_init_f32( - arm_cfft_radix4_instance_f32 * S, - uint16_t fftLen, - uint8_t ifftFlag, - uint8_t bitReverseFlag); - -/* Deprecated */ - void arm_cfft_radix4_f32( - const arm_cfft_radix4_instance_f32 * S, - float32_t * pSrc); - - /** + typedef struct + { + uint16_t fftLen; /**< length of the FFT. */ + uint8_t ifftFlag; /**< flag that selects forward (ifftFlag=0) or inverse (ifftFlag=1) transform. */ + uint8_t bitReverseFlag; /**< flag that enables (bitReverseFlag=1) or disables (bitReverseFlag=0) bit reversal of output. */ + float32_t *pTwiddle; /**< points to the Twiddle factor table. */ + uint16_t *pBitRevTable; /**< points to the bit reversal table. */ + uint16_t twidCoefModifier; /**< twiddle coefficient modifier that supports different size FFTs with the same twiddle factor table. */ + uint16_t bitRevFactor; /**< bit reversal modifier that supports different size FFTs with the same bit reversal table. */ + float32_t onebyfftLen; /**< value of 1/fftLen. */ + } arm_cfft_radix4_instance_f32; + + /* Deprecated */ + arm_status arm_cfft_radix4_init_f32( + arm_cfft_radix4_instance_f32 *S, + uint16_t fftLen, + uint8_t ifftFlag, + uint8_t bitReverseFlag); + + /* Deprecated */ + void arm_cfft_radix4_f32( + const arm_cfft_radix4_instance_f32 *S, + float32_t *pSrc); + + /** * @brief Instance structure for the fixed-point CFFT/CIFFT function. */ - typedef struct - { - uint16_t fftLen; /**< length of the FFT. */ - const q15_t *pTwiddle; /**< points to the Twiddle factor table. */ - const uint16_t *pBitRevTable; /**< points to the bit reversal table. */ - uint16_t bitRevLength; /**< bit reversal table length. */ - } arm_cfft_instance_q15; - -void arm_cfft_q15( - const arm_cfft_instance_q15 * S, - q15_t * p1, - uint8_t ifftFlag, - uint8_t bitReverseFlag); + typedef struct + { + uint16_t fftLen; /**< length of the FFT. */ + const q15_t *pTwiddle; /**< points to the Twiddle factor table. */ + const uint16_t *pBitRevTable; /**< points to the bit reversal table. */ + uint16_t bitRevLength; /**< bit reversal table length. */ + } arm_cfft_instance_q15; + + void arm_cfft_q15( + const arm_cfft_instance_q15 *S, + q15_t *p1, + uint8_t ifftFlag, + uint8_t bitReverseFlag); - /** + /** * @brief Instance structure for the fixed-point CFFT/CIFFT function. */ - typedef struct - { - uint16_t fftLen; /**< length of the FFT. */ - const q31_t *pTwiddle; /**< points to the Twiddle factor table. */ - const uint16_t *pBitRevTable; /**< points to the bit reversal table. */ - uint16_t bitRevLength; /**< bit reversal table length. */ - } arm_cfft_instance_q31; - -void arm_cfft_q31( - const arm_cfft_instance_q31 * S, - q31_t * p1, - uint8_t ifftFlag, - uint8_t bitReverseFlag); - - /** + typedef struct + { + uint16_t fftLen; /**< length of the FFT. */ + const q31_t *pTwiddle; /**< points to the Twiddle factor table. */ + const uint16_t *pBitRevTable; /**< points to the bit reversal table. */ + uint16_t bitRevLength; /**< bit reversal table length. */ + } arm_cfft_instance_q31; + + void arm_cfft_q31( + const arm_cfft_instance_q31 *S, + q31_t *p1, + uint8_t ifftFlag, + uint8_t bitReverseFlag); + + /** * @brief Instance structure for the floating-point CFFT/CIFFT function. */ - typedef struct - { - uint16_t fftLen; /**< length of the FFT. */ - const float32_t *pTwiddle; /**< points to the Twiddle factor table. */ - const uint16_t *pBitRevTable; /**< points to the bit reversal table. */ - uint16_t bitRevLength; /**< bit reversal table length. */ - } arm_cfft_instance_f32; - - void arm_cfft_f32( - const arm_cfft_instance_f32 * S, - float32_t * p1, - uint8_t ifftFlag, - uint8_t bitReverseFlag); + typedef struct + { + uint16_t fftLen; /**< length of the FFT. */ + const float32_t *pTwiddle; /**< points to the Twiddle factor table. */ + const uint16_t *pBitRevTable; /**< points to the bit reversal table. */ + uint16_t bitRevLength; /**< bit reversal table length. */ + } arm_cfft_instance_f32; + + void arm_cfft_f32( + const arm_cfft_instance_f32 *S, + float32_t *p1, + uint8_t ifftFlag, + uint8_t bitReverseFlag); - /** + /** * @brief Instance structure for the Q15 RFFT/RIFFT function. */ - typedef struct - { - uint32_t fftLenReal; /**< length of the real FFT. */ - uint8_t ifftFlagR; /**< flag that selects forward (ifftFlagR=0) or inverse (ifftFlagR=1) transform. */ - uint8_t bitReverseFlagR; /**< flag that enables (bitReverseFlagR=1) or disables (bitReverseFlagR=0) bit reversal of output. */ - uint32_t twidCoefRModifier; /**< twiddle coefficient modifier that supports different size FFTs with the same twiddle factor table. */ - q15_t *pTwiddleAReal; /**< points to the real twiddle factor table. */ - q15_t *pTwiddleBReal; /**< points to the imag twiddle factor table. */ - const arm_cfft_instance_q15 *pCfft; /**< points to the complex FFT instance. */ - } arm_rfft_instance_q15; - - arm_status arm_rfft_init_q15( - arm_rfft_instance_q15 * S, - uint32_t fftLenReal, - uint32_t ifftFlagR, - uint32_t bitReverseFlag); - - void arm_rfft_q15( - const arm_rfft_instance_q15 * S, - q15_t * pSrc, - q15_t * pDst); - - /** + typedef struct + { + uint32_t fftLenReal; /**< length of the real FFT. */ + uint8_t ifftFlagR; /**< flag that selects forward (ifftFlagR=0) or inverse (ifftFlagR=1) transform. */ + uint8_t bitReverseFlagR; /**< flag that enables (bitReverseFlagR=1) or disables (bitReverseFlagR=0) bit reversal of output. */ + uint32_t twidCoefRModifier; /**< twiddle coefficient modifier that supports different size FFTs with the same twiddle factor table. */ + q15_t *pTwiddleAReal; /**< points to the real twiddle factor table. */ + q15_t *pTwiddleBReal; /**< points to the imag twiddle factor table. */ + const arm_cfft_instance_q15 *pCfft; /**< points to the complex FFT instance. */ + } arm_rfft_instance_q15; + + arm_status arm_rfft_init_q15( + arm_rfft_instance_q15 *S, + uint32_t fftLenReal, + uint32_t ifftFlagR, + uint32_t bitReverseFlag); + + void arm_rfft_q15( + const arm_rfft_instance_q15 *S, + q15_t *pSrc, + q15_t *pDst); + + /** * @brief Instance structure for the Q31 RFFT/RIFFT function. */ - typedef struct - { - uint32_t fftLenReal; /**< length of the real FFT. */ - uint8_t ifftFlagR; /**< flag that selects forward (ifftFlagR=0) or inverse (ifftFlagR=1) transform. */ - uint8_t bitReverseFlagR; /**< flag that enables (bitReverseFlagR=1) or disables (bitReverseFlagR=0) bit reversal of output. */ - uint32_t twidCoefRModifier; /**< twiddle coefficient modifier that supports different size FFTs with the same twiddle factor table. */ - q31_t *pTwiddleAReal; /**< points to the real twiddle factor table. */ - q31_t *pTwiddleBReal; /**< points to the imag twiddle factor table. */ - const arm_cfft_instance_q31 *pCfft; /**< points to the complex FFT instance. */ - } arm_rfft_instance_q31; - - arm_status arm_rfft_init_q31( - arm_rfft_instance_q31 * S, - uint32_t fftLenReal, - uint32_t ifftFlagR, - uint32_t bitReverseFlag); - - void arm_rfft_q31( - const arm_rfft_instance_q31 * S, - q31_t * pSrc, - q31_t * pDst); - - /** + typedef struct + { + uint32_t fftLenReal; /**< length of the real FFT. */ + uint8_t ifftFlagR; /**< flag that selects forward (ifftFlagR=0) or inverse (ifftFlagR=1) transform. */ + uint8_t bitReverseFlagR; /**< flag that enables (bitReverseFlagR=1) or disables (bitReverseFlagR=0) bit reversal of output. */ + uint32_t twidCoefRModifier; /**< twiddle coefficient modifier that supports different size FFTs with the same twiddle factor table. */ + q31_t *pTwiddleAReal; /**< points to the real twiddle factor table. */ + q31_t *pTwiddleBReal; /**< points to the imag twiddle factor table. */ + const arm_cfft_instance_q31 *pCfft; /**< points to the complex FFT instance. */ + } arm_rfft_instance_q31; + + arm_status arm_rfft_init_q31( + arm_rfft_instance_q31 *S, + uint32_t fftLenReal, + uint32_t ifftFlagR, + uint32_t bitReverseFlag); + + void arm_rfft_q31( + const arm_rfft_instance_q31 *S, + q31_t *pSrc, + q31_t *pDst); + + /** * @brief Instance structure for the floating-point RFFT/RIFFT function. */ - typedef struct - { - uint32_t fftLenReal; /**< length of the real FFT. */ - uint16_t fftLenBy2; /**< length of the complex FFT. */ - uint8_t ifftFlagR; /**< flag that selects forward (ifftFlagR=0) or inverse (ifftFlagR=1) transform. */ - uint8_t bitReverseFlagR; /**< flag that enables (bitReverseFlagR=1) or disables (bitReverseFlagR=0) bit reversal of output. */ - uint32_t twidCoefRModifier; /**< twiddle coefficient modifier that supports different size FFTs with the same twiddle factor table. */ - float32_t *pTwiddleAReal; /**< points to the real twiddle factor table. */ - float32_t *pTwiddleBReal; /**< points to the imag twiddle factor table. */ - arm_cfft_radix4_instance_f32 *pCfft; /**< points to the complex FFT instance. */ - } arm_rfft_instance_f32; - - arm_status arm_rfft_init_f32( - arm_rfft_instance_f32 * S, - arm_cfft_radix4_instance_f32 * S_CFFT, - uint32_t fftLenReal, - uint32_t ifftFlagR, - uint32_t bitReverseFlag); - - void arm_rfft_f32( - const arm_rfft_instance_f32 * S, - float32_t * pSrc, - float32_t * pDst); - - /** + typedef struct + { + uint32_t fftLenReal; /**< length of the real FFT. */ + uint16_t fftLenBy2; /**< length of the complex FFT. */ + uint8_t ifftFlagR; /**< flag that selects forward (ifftFlagR=0) or inverse (ifftFlagR=1) transform. */ + uint8_t bitReverseFlagR; /**< flag that enables (bitReverseFlagR=1) or disables (bitReverseFlagR=0) bit reversal of output. */ + uint32_t twidCoefRModifier; /**< twiddle coefficient modifier that supports different size FFTs with the same twiddle factor table. */ + float32_t *pTwiddleAReal; /**< points to the real twiddle factor table. */ + float32_t *pTwiddleBReal; /**< points to the imag twiddle factor table. */ + arm_cfft_radix4_instance_f32 *pCfft; /**< points to the complex FFT instance. */ + } arm_rfft_instance_f32; + + arm_status arm_rfft_init_f32( + arm_rfft_instance_f32 *S, + arm_cfft_radix4_instance_f32 *S_CFFT, + uint32_t fftLenReal, + uint32_t ifftFlagR, + uint32_t bitReverseFlag); + + void arm_rfft_f32( + const arm_rfft_instance_f32 *S, + float32_t *pSrc, + float32_t *pDst); + + /** * @brief Instance structure for the floating-point RFFT/RIFFT function. */ -typedef struct - { - arm_cfft_instance_f32 Sint; /**< Internal CFFT structure. */ - uint16_t fftLenRFFT; /**< length of the real sequence */ - float32_t * pTwiddleRFFT; /**< Twiddle factors real stage */ - } arm_rfft_fast_instance_f32 ; + typedef struct + { + arm_cfft_instance_f32 Sint; /**< Internal CFFT structure. */ + uint16_t fftLenRFFT; /**< length of the real sequence */ + float32_t *pTwiddleRFFT; /**< Twiddle factors real stage */ + } arm_rfft_fast_instance_f32; -arm_status arm_rfft_fast_init_f32 ( - arm_rfft_fast_instance_f32 * S, - uint16_t fftLen); + arm_status arm_rfft_fast_init_f32( + arm_rfft_fast_instance_f32 *S, + uint16_t fftLen); -void arm_rfft_fast_f32( - arm_rfft_fast_instance_f32 * S, - float32_t * p, float32_t * pOut, - uint8_t ifftFlag); + void arm_rfft_fast_f32( + arm_rfft_fast_instance_f32 *S, + float32_t *p, float32_t *pOut, + uint8_t ifftFlag); - /** + /** * @brief Instance structure for the floating-point DCT4/IDCT4 function. */ - typedef struct - { - uint16_t N; /**< length of the DCT4. */ - uint16_t Nby2; /**< half of the length of the DCT4. */ - float32_t normalize; /**< normalizing factor. */ - float32_t *pTwiddle; /**< points to the twiddle factor table. */ - float32_t *pCosFactor; /**< points to the cosFactor table. */ - arm_rfft_instance_f32 *pRfft; /**< points to the real FFT instance. */ - arm_cfft_radix4_instance_f32 *pCfft; /**< points to the complex FFT instance. */ - } arm_dct4_instance_f32; + typedef struct + { + uint16_t N; /**< length of the DCT4. */ + uint16_t Nby2; /**< half of the length of the DCT4. */ + float32_t normalize; /**< normalizing factor. */ + float32_t *pTwiddle; /**< points to the twiddle factor table. */ + float32_t *pCosFactor; /**< points to the cosFactor table. */ + arm_rfft_instance_f32 *pRfft; /**< points to the real FFT instance. */ + arm_cfft_radix4_instance_f32 *pCfft; /**< points to the complex FFT instance. */ + } arm_dct4_instance_f32; - /** + /** * @brief Initialization function for the floating-point DCT4/IDCT4. * @param[in,out] *S points to an instance of floating-point DCT4/IDCT4 structure. * @param[in] *S_RFFT points to an instance of floating-point RFFT/RIFFT structure. @@ -2379,18 +2321,18 @@ void arm_rfft_fast_f32( * @param[in] N length of the DCT4. * @param[in] Nby2 half of the length of the DCT4. * @param[in] normalize normalizing factor. - * @return arm_status function returns ARM_MATH_SUCCESS if initialization is successful or ARM_MATH_ARGUMENT_ERROR if fftLenReal is not a supported transform length. + * @return arm_status function returns ARM_MATH_SUCCESS if initialization is successful or ARM_MATH_ARGUMENT_ERROR if fftLenReal is not a supported transform length. */ - arm_status arm_dct4_init_f32( - arm_dct4_instance_f32 * S, - arm_rfft_instance_f32 * S_RFFT, - arm_cfft_radix4_instance_f32 * S_CFFT, - uint16_t N, - uint16_t Nby2, - float32_t normalize); + arm_status arm_dct4_init_f32( + arm_dct4_instance_f32 *S, + arm_rfft_instance_f32 *S_RFFT, + arm_cfft_radix4_instance_f32 *S_CFFT, + uint16_t N, + uint16_t Nby2, + float32_t normalize); - /** + /** * @brief Processing function for the floating-point DCT4/IDCT4. * @param[in] *S points to an instance of the floating-point DCT4/IDCT4 structure. * @param[in] *pState points to state buffer. @@ -2398,27 +2340,27 @@ void arm_rfft_fast_f32( * @return none. */ - void arm_dct4_f32( - const arm_dct4_instance_f32 * S, - float32_t * pState, - float32_t * pInlineBuffer); + void arm_dct4_f32( + const arm_dct4_instance_f32 *S, + float32_t *pState, + float32_t *pInlineBuffer); - /** + /** * @brief Instance structure for the Q31 DCT4/IDCT4 function. */ - typedef struct - { - uint16_t N; /**< length of the DCT4. */ - uint16_t Nby2; /**< half of the length of the DCT4. */ - q31_t normalize; /**< normalizing factor. */ - q31_t *pTwiddle; /**< points to the twiddle factor table. */ - q31_t *pCosFactor; /**< points to the cosFactor table. */ - arm_rfft_instance_q31 *pRfft; /**< points to the real FFT instance. */ - arm_cfft_radix4_instance_q31 *pCfft; /**< points to the complex FFT instance. */ - } arm_dct4_instance_q31; + typedef struct + { + uint16_t N; /**< length of the DCT4. */ + uint16_t Nby2; /**< half of the length of the DCT4. */ + q31_t normalize; /**< normalizing factor. */ + q31_t *pTwiddle; /**< points to the twiddle factor table. */ + q31_t *pCosFactor; /**< points to the cosFactor table. */ + arm_rfft_instance_q31 *pRfft; /**< points to the real FFT instance. */ + arm_cfft_radix4_instance_q31 *pCfft; /**< points to the complex FFT instance. */ + } arm_dct4_instance_q31; - /** + /** * @brief Initialization function for the Q31 DCT4/IDCT4. * @param[in,out] *S points to an instance of Q31 DCT4/IDCT4 structure. * @param[in] *S_RFFT points to an instance of Q31 RFFT/RIFFT structure @@ -2426,18 +2368,18 @@ void arm_rfft_fast_f32( * @param[in] N length of the DCT4. * @param[in] Nby2 half of the length of the DCT4. * @param[in] normalize normalizing factor. - * @return arm_status function returns ARM_MATH_SUCCESS if initialization is successful or ARM_MATH_ARGUMENT_ERROR if N is not a supported transform length. + * @return arm_status function returns ARM_MATH_SUCCESS if initialization is successful or ARM_MATH_ARGUMENT_ERROR if N is not a supported transform length. */ - arm_status arm_dct4_init_q31( - arm_dct4_instance_q31 * S, - arm_rfft_instance_q31 * S_RFFT, - arm_cfft_radix4_instance_q31 * S_CFFT, - uint16_t N, - uint16_t Nby2, - q31_t normalize); + arm_status arm_dct4_init_q31( + arm_dct4_instance_q31 *S, + arm_rfft_instance_q31 *S_RFFT, + arm_cfft_radix4_instance_q31 *S_CFFT, + uint16_t N, + uint16_t Nby2, + q31_t normalize); - /** + /** * @brief Processing function for the Q31 DCT4/IDCT4. * @param[in] *S points to an instance of the Q31 DCT4 structure. * @param[in] *pState points to state buffer. @@ -2445,27 +2387,27 @@ void arm_rfft_fast_f32( * @return none. */ - void arm_dct4_q31( - const arm_dct4_instance_q31 * S, - q31_t * pState, - q31_t * pInlineBuffer); + void arm_dct4_q31( + const arm_dct4_instance_q31 *S, + q31_t *pState, + q31_t *pInlineBuffer); - /** + /** * @brief Instance structure for the Q15 DCT4/IDCT4 function. */ - typedef struct - { - uint16_t N; /**< length of the DCT4. */ - uint16_t Nby2; /**< half of the length of the DCT4. */ - q15_t normalize; /**< normalizing factor. */ - q15_t *pTwiddle; /**< points to the twiddle factor table. */ - q15_t *pCosFactor; /**< points to the cosFactor table. */ - arm_rfft_instance_q15 *pRfft; /**< points to the real FFT instance. */ - arm_cfft_radix4_instance_q15 *pCfft; /**< points to the complex FFT instance. */ - } arm_dct4_instance_q15; + typedef struct + { + uint16_t N; /**< length of the DCT4. */ + uint16_t Nby2; /**< half of the length of the DCT4. */ + q15_t normalize; /**< normalizing factor. */ + q15_t *pTwiddle; /**< points to the twiddle factor table. */ + q15_t *pCosFactor; /**< points to the cosFactor table. */ + arm_rfft_instance_q15 *pRfft; /**< points to the real FFT instance. */ + arm_cfft_radix4_instance_q15 *pCfft; /**< points to the complex FFT instance. */ + } arm_dct4_instance_q15; - /** + /** * @brief Initialization function for the Q15 DCT4/IDCT4. * @param[in,out] *S points to an instance of Q15 DCT4/IDCT4 structure. * @param[in] *S_RFFT points to an instance of Q15 RFFT/RIFFT structure. @@ -2473,18 +2415,18 @@ void arm_rfft_fast_f32( * @param[in] N length of the DCT4. * @param[in] Nby2 half of the length of the DCT4. * @param[in] normalize normalizing factor. - * @return arm_status function returns ARM_MATH_SUCCESS if initialization is successful or ARM_MATH_ARGUMENT_ERROR if N is not a supported transform length. + * @return arm_status function returns ARM_MATH_SUCCESS if initialization is successful or ARM_MATH_ARGUMENT_ERROR if N is not a supported transform length. */ - arm_status arm_dct4_init_q15( - arm_dct4_instance_q15 * S, - arm_rfft_instance_q15 * S_RFFT, - arm_cfft_radix4_instance_q15 * S_CFFT, - uint16_t N, - uint16_t Nby2, - q15_t normalize); + arm_status arm_dct4_init_q15( + arm_dct4_instance_q15 *S, + arm_rfft_instance_q15 *S_RFFT, + arm_cfft_radix4_instance_q15 *S_CFFT, + uint16_t N, + uint16_t Nby2, + q15_t normalize); - /** + /** * @brief Processing function for the Q15 DCT4/IDCT4. * @param[in] *S points to an instance of the Q15 DCT4 structure. * @param[in] *pState points to state buffer. @@ -2492,12 +2434,12 @@ void arm_rfft_fast_f32( * @return none. */ - void arm_dct4_q15( - const arm_dct4_instance_q15 * S, - q15_t * pState, - q15_t * pInlineBuffer); + void arm_dct4_q15( + const arm_dct4_instance_q15 *S, + q15_t *pState, + q15_t *pInlineBuffer); - /** + /** * @brief Floating-point vector addition. * @param[in] *pSrcA points to the first input vector * @param[in] *pSrcB points to the second input vector @@ -2506,13 +2448,13 @@ void arm_rfft_fast_f32( * @return none. */ - void arm_add_f32( - float32_t * pSrcA, - float32_t * pSrcB, - float32_t * pDst, - uint32_t blockSize); + void arm_add_f32( + float32_t *pSrcA, + float32_t *pSrcB, + float32_t *pDst, + uint32_t blockSize); - /** + /** * @brief Q7 vector addition. * @param[in] *pSrcA points to the first input vector * @param[in] *pSrcB points to the second input vector @@ -2521,13 +2463,13 @@ void arm_rfft_fast_f32( * @return none. */ - void arm_add_q7( - q7_t * pSrcA, - q7_t * pSrcB, - q7_t * pDst, - uint32_t blockSize); + void arm_add_q7( + q7_t *pSrcA, + q7_t *pSrcB, + q7_t *pDst, + uint32_t blockSize); - /** + /** * @brief Q15 vector addition. * @param[in] *pSrcA points to the first input vector * @param[in] *pSrcB points to the second input vector @@ -2536,13 +2478,13 @@ void arm_rfft_fast_f32( * @return none. */ - void arm_add_q15( - q15_t * pSrcA, - q15_t * pSrcB, - q15_t * pDst, - uint32_t blockSize); + void arm_add_q15( + q15_t *pSrcA, + q15_t *pSrcB, + q15_t *pDst, + uint32_t blockSize); - /** + /** * @brief Q31 vector addition. * @param[in] *pSrcA points to the first input vector * @param[in] *pSrcB points to the second input vector @@ -2551,13 +2493,13 @@ void arm_rfft_fast_f32( * @return none. */ - void arm_add_q31( - q31_t * pSrcA, - q31_t * pSrcB, - q31_t * pDst, - uint32_t blockSize); + void arm_add_q31( + q31_t *pSrcA, + q31_t *pSrcB, + q31_t *pDst, + uint32_t blockSize); - /** + /** * @brief Floating-point vector subtraction. * @param[in] *pSrcA points to the first input vector * @param[in] *pSrcB points to the second input vector @@ -2566,13 +2508,13 @@ void arm_rfft_fast_f32( * @return none. */ - void arm_sub_f32( - float32_t * pSrcA, - float32_t * pSrcB, - float32_t * pDst, - uint32_t blockSize); + void arm_sub_f32( + float32_t *pSrcA, + float32_t *pSrcB, + float32_t *pDst, + uint32_t blockSize); - /** + /** * @brief Q7 vector subtraction. * @param[in] *pSrcA points to the first input vector * @param[in] *pSrcB points to the second input vector @@ -2581,13 +2523,13 @@ void arm_rfft_fast_f32( * @return none. */ - void arm_sub_q7( - q7_t * pSrcA, - q7_t * pSrcB, - q7_t * pDst, - uint32_t blockSize); + void arm_sub_q7( + q7_t *pSrcA, + q7_t *pSrcB, + q7_t *pDst, + uint32_t blockSize); - /** + /** * @brief Q15 vector subtraction. * @param[in] *pSrcA points to the first input vector * @param[in] *pSrcB points to the second input vector @@ -2596,13 +2538,13 @@ void arm_rfft_fast_f32( * @return none. */ - void arm_sub_q15( - q15_t * pSrcA, - q15_t * pSrcB, - q15_t * pDst, - uint32_t blockSize); + void arm_sub_q15( + q15_t *pSrcA, + q15_t *pSrcB, + q15_t *pDst, + uint32_t blockSize); - /** + /** * @brief Q31 vector subtraction. * @param[in] *pSrcA points to the first input vector * @param[in] *pSrcB points to the second input vector @@ -2611,13 +2553,13 @@ void arm_rfft_fast_f32( * @return none. */ - void arm_sub_q31( - q31_t * pSrcA, - q31_t * pSrcB, - q31_t * pDst, - uint32_t blockSize); + void arm_sub_q31( + q31_t *pSrcA, + q31_t *pSrcB, + q31_t *pDst, + uint32_t blockSize); - /** + /** * @brief Multiplies a floating-point vector by a scalar. * @param[in] *pSrc points to the input vector * @param[in] scale scale factor to be applied @@ -2626,13 +2568,13 @@ void arm_rfft_fast_f32( * @return none. */ - void arm_scale_f32( - float32_t * pSrc, - float32_t scale, - float32_t * pDst, - uint32_t blockSize); + void arm_scale_f32( + float32_t *pSrc, + float32_t scale, + float32_t *pDst, + uint32_t blockSize); - /** + /** * @brief Multiplies a Q7 vector by a scalar. * @param[in] *pSrc points to the input vector * @param[in] scaleFract fractional portion of the scale value @@ -2642,14 +2584,14 @@ void arm_rfft_fast_f32( * @return none. */ - void arm_scale_q7( - q7_t * pSrc, - q7_t scaleFract, - int8_t shift, - q7_t * pDst, - uint32_t blockSize); + void arm_scale_q7( + q7_t *pSrc, + q7_t scaleFract, + int8_t shift, + q7_t *pDst, + uint32_t blockSize); - /** + /** * @brief Multiplies a Q15 vector by a scalar. * @param[in] *pSrc points to the input vector * @param[in] scaleFract fractional portion of the scale value @@ -2659,14 +2601,14 @@ void arm_rfft_fast_f32( * @return none. */ - void arm_scale_q15( - q15_t * pSrc, - q15_t scaleFract, - int8_t shift, - q15_t * pDst, - uint32_t blockSize); + void arm_scale_q15( + q15_t *pSrc, + q15_t scaleFract, + int8_t shift, + q15_t *pDst, + uint32_t blockSize); - /** + /** * @brief Multiplies a Q31 vector by a scalar. * @param[in] *pSrc points to the input vector * @param[in] scaleFract fractional portion of the scale value @@ -2676,14 +2618,14 @@ void arm_rfft_fast_f32( * @return none. */ - void arm_scale_q31( - q31_t * pSrc, - q31_t scaleFract, - int8_t shift, - q31_t * pDst, - uint32_t blockSize); + void arm_scale_q31( + q31_t *pSrc, + q31_t scaleFract, + int8_t shift, + q31_t *pDst, + uint32_t blockSize); - /** + /** * @brief Q7 vector absolute value. * @param[in] *pSrc points to the input buffer * @param[out] *pDst points to the output buffer @@ -2691,12 +2633,12 @@ void arm_rfft_fast_f32( * @return none. */ - void arm_abs_q7( - q7_t * pSrc, - q7_t * pDst, - uint32_t blockSize); + void arm_abs_q7( + q7_t *pSrc, + q7_t *pDst, + uint32_t blockSize); - /** + /** * @brief Floating-point vector absolute value. * @param[in] *pSrc points to the input buffer * @param[out] *pDst points to the output buffer @@ -2704,12 +2646,12 @@ void arm_rfft_fast_f32( * @return none. */ - void arm_abs_f32( - float32_t * pSrc, - float32_t * pDst, - uint32_t blockSize); + void arm_abs_f32( + float32_t *pSrc, + float32_t *pDst, + uint32_t blockSize); - /** + /** * @brief Q15 vector absolute value. * @param[in] *pSrc points to the input buffer * @param[out] *pDst points to the output buffer @@ -2717,12 +2659,12 @@ void arm_rfft_fast_f32( * @return none. */ - void arm_abs_q15( - q15_t * pSrc, - q15_t * pDst, - uint32_t blockSize); + void arm_abs_q15( + q15_t *pSrc, + q15_t *pDst, + uint32_t blockSize); - /** + /** * @brief Q31 vector absolute value. * @param[in] *pSrc points to the input buffer * @param[out] *pDst points to the output buffer @@ -2730,12 +2672,12 @@ void arm_rfft_fast_f32( * @return none. */ - void arm_abs_q31( - q31_t * pSrc, - q31_t * pDst, - uint32_t blockSize); + void arm_abs_q31( + q31_t *pSrc, + q31_t *pDst, + uint32_t blockSize); - /** + /** * @brief Dot product of floating-point vectors. * @param[in] *pSrcA points to the first input vector * @param[in] *pSrcB points to the second input vector @@ -2744,13 +2686,13 @@ void arm_rfft_fast_f32( * @return none. */ - void arm_dot_prod_f32( - float32_t * pSrcA, - float32_t * pSrcB, - uint32_t blockSize, - float32_t * result); + void arm_dot_prod_f32( + float32_t *pSrcA, + float32_t *pSrcB, + uint32_t blockSize, + float32_t *result); - /** + /** * @brief Dot product of Q7 vectors. * @param[in] *pSrcA points to the first input vector * @param[in] *pSrcB points to the second input vector @@ -2759,13 +2701,13 @@ void arm_rfft_fast_f32( * @return none. */ - void arm_dot_prod_q7( - q7_t * pSrcA, - q7_t * pSrcB, - uint32_t blockSize, - q31_t * result); + void arm_dot_prod_q7( + q7_t *pSrcA, + q7_t *pSrcB, + uint32_t blockSize, + q31_t *result); - /** + /** * @brief Dot product of Q15 vectors. * @param[in] *pSrcA points to the first input vector * @param[in] *pSrcB points to the second input vector @@ -2774,13 +2716,13 @@ void arm_rfft_fast_f32( * @return none. */ - void arm_dot_prod_q15( - q15_t * pSrcA, - q15_t * pSrcB, - uint32_t blockSize, - q63_t * result); + void arm_dot_prod_q15( + q15_t *pSrcA, + q15_t *pSrcB, + uint32_t blockSize, + q63_t *result); - /** + /** * @brief Dot product of Q31 vectors. * @param[in] *pSrcA points to the first input vector * @param[in] *pSrcB points to the second input vector @@ -2789,13 +2731,13 @@ void arm_rfft_fast_f32( * @return none. */ - void arm_dot_prod_q31( - q31_t * pSrcA, - q31_t * pSrcB, - uint32_t blockSize, - q63_t * result); + void arm_dot_prod_q31( + q31_t *pSrcA, + q31_t *pSrcB, + uint32_t blockSize, + q63_t *result); - /** + /** * @brief Shifts the elements of a Q7 vector a specified number of bits. * @param[in] *pSrc points to the input vector * @param[in] shiftBits number of bits to shift. A positive value shifts left; a negative value shifts right. @@ -2804,13 +2746,13 @@ void arm_rfft_fast_f32( * @return none. */ - void arm_shift_q7( - q7_t * pSrc, - int8_t shiftBits, - q7_t * pDst, - uint32_t blockSize); + void arm_shift_q7( + q7_t *pSrc, + int8_t shiftBits, + q7_t *pDst, + uint32_t blockSize); - /** + /** * @brief Shifts the elements of a Q15 vector a specified number of bits. * @param[in] *pSrc points to the input vector * @param[in] shiftBits number of bits to shift. A positive value shifts left; a negative value shifts right. @@ -2819,13 +2761,13 @@ void arm_rfft_fast_f32( * @return none. */ - void arm_shift_q15( - q15_t * pSrc, - int8_t shiftBits, - q15_t * pDst, - uint32_t blockSize); + void arm_shift_q15( + q15_t *pSrc, + int8_t shiftBits, + q15_t *pDst, + uint32_t blockSize); - /** + /** * @brief Shifts the elements of a Q31 vector a specified number of bits. * @param[in] *pSrc points to the input vector * @param[in] shiftBits number of bits to shift. A positive value shifts left; a negative value shifts right. @@ -2834,13 +2776,13 @@ void arm_rfft_fast_f32( * @return none. */ - void arm_shift_q31( - q31_t * pSrc, - int8_t shiftBits, - q31_t * pDst, - uint32_t blockSize); + void arm_shift_q31( + q31_t *pSrc, + int8_t shiftBits, + q31_t *pDst, + uint32_t blockSize); - /** + /** * @brief Adds a constant offset to a floating-point vector. * @param[in] *pSrc points to the input vector * @param[in] offset is the offset to be added @@ -2849,13 +2791,13 @@ void arm_rfft_fast_f32( * @return none. */ - void arm_offset_f32( - float32_t * pSrc, - float32_t offset, - float32_t * pDst, - uint32_t blockSize); + void arm_offset_f32( + float32_t *pSrc, + float32_t offset, + float32_t *pDst, + uint32_t blockSize); - /** + /** * @brief Adds a constant offset to a Q7 vector. * @param[in] *pSrc points to the input vector * @param[in] offset is the offset to be added @@ -2864,13 +2806,13 @@ void arm_rfft_fast_f32( * @return none. */ - void arm_offset_q7( - q7_t * pSrc, - q7_t offset, - q7_t * pDst, - uint32_t blockSize); + void arm_offset_q7( + q7_t *pSrc, + q7_t offset, + q7_t *pDst, + uint32_t blockSize); - /** + /** * @brief Adds a constant offset to a Q15 vector. * @param[in] *pSrc points to the input vector * @param[in] offset is the offset to be added @@ -2879,13 +2821,13 @@ void arm_rfft_fast_f32( * @return none. */ - void arm_offset_q15( - q15_t * pSrc, - q15_t offset, - q15_t * pDst, - uint32_t blockSize); + void arm_offset_q15( + q15_t *pSrc, + q15_t offset, + q15_t *pDst, + uint32_t blockSize); - /** + /** * @brief Adds a constant offset to a Q31 vector. * @param[in] *pSrc points to the input vector * @param[in] offset is the offset to be added @@ -2894,13 +2836,13 @@ void arm_rfft_fast_f32( * @return none. */ - void arm_offset_q31( - q31_t * pSrc, - q31_t offset, - q31_t * pDst, - uint32_t blockSize); + void arm_offset_q31( + q31_t *pSrc, + q31_t offset, + q31_t *pDst, + uint32_t blockSize); - /** + /** * @brief Negates the elements of a floating-point vector. * @param[in] *pSrc points to the input vector * @param[out] *pDst points to the output vector @@ -2908,12 +2850,12 @@ void arm_rfft_fast_f32( * @return none. */ - void arm_negate_f32( - float32_t * pSrc, - float32_t * pDst, - uint32_t blockSize); + void arm_negate_f32( + float32_t *pSrc, + float32_t *pDst, + uint32_t blockSize); - /** + /** * @brief Negates the elements of a Q7 vector. * @param[in] *pSrc points to the input vector * @param[out] *pDst points to the output vector @@ -2921,12 +2863,12 @@ void arm_rfft_fast_f32( * @return none. */ - void arm_negate_q7( - q7_t * pSrc, - q7_t * pDst, - uint32_t blockSize); + void arm_negate_q7( + q7_t *pSrc, + q7_t *pDst, + uint32_t blockSize); - /** + /** * @brief Negates the elements of a Q15 vector. * @param[in] *pSrc points to the input vector * @param[out] *pDst points to the output vector @@ -2934,12 +2876,12 @@ void arm_rfft_fast_f32( * @return none. */ - void arm_negate_q15( - q15_t * pSrc, - q15_t * pDst, - uint32_t blockSize); + void arm_negate_q15( + q15_t *pSrc, + q15_t *pDst, + uint32_t blockSize); - /** + /** * @brief Negates the elements of a Q31 vector. * @param[in] *pSrc points to the input vector * @param[out] *pDst points to the output vector @@ -2947,106 +2889,106 @@ void arm_rfft_fast_f32( * @return none. */ - void arm_negate_q31( - q31_t * pSrc, - q31_t * pDst, - uint32_t blockSize); - /** + void arm_negate_q31( + q31_t *pSrc, + q31_t *pDst, + uint32_t blockSize); + /** * @brief Copies the elements of a floating-point vector. * @param[in] *pSrc input pointer * @param[out] *pDst output pointer * @param[in] blockSize number of samples to process * @return none. */ - void arm_copy_f32( - float32_t * pSrc, - float32_t * pDst, - uint32_t blockSize); + void arm_copy_f32( + float32_t *pSrc, + float32_t *pDst, + uint32_t blockSize); - /** + /** * @brief Copies the elements of a Q7 vector. * @param[in] *pSrc input pointer * @param[out] *pDst output pointer * @param[in] blockSize number of samples to process * @return none. */ - void arm_copy_q7( - q7_t * pSrc, - q7_t * pDst, - uint32_t blockSize); + void arm_copy_q7( + q7_t *pSrc, + q7_t *pDst, + uint32_t blockSize); - /** + /** * @brief Copies the elements of a Q15 vector. * @param[in] *pSrc input pointer * @param[out] *pDst output pointer * @param[in] blockSize number of samples to process * @return none. */ - void arm_copy_q15( - q15_t * pSrc, - q15_t * pDst, - uint32_t blockSize); + void arm_copy_q15( + q15_t *pSrc, + q15_t *pDst, + uint32_t blockSize); - /** + /** * @brief Copies the elements of a Q31 vector. * @param[in] *pSrc input pointer * @param[out] *pDst output pointer * @param[in] blockSize number of samples to process * @return none. */ - void arm_copy_q31( - q31_t * pSrc, - q31_t * pDst, - uint32_t blockSize); - /** + void arm_copy_q31( + q31_t *pSrc, + q31_t *pDst, + uint32_t blockSize); + /** * @brief Fills a constant value into a floating-point vector. * @param[in] value input value to be filled * @param[out] *pDst output pointer * @param[in] blockSize number of samples to process * @return none. */ - void arm_fill_f32( - float32_t value, - float32_t * pDst, - uint32_t blockSize); + void arm_fill_f32( + float32_t value, + float32_t *pDst, + uint32_t blockSize); - /** + /** * @brief Fills a constant value into a Q7 vector. * @param[in] value input value to be filled * @param[out] *pDst output pointer * @param[in] blockSize number of samples to process * @return none. */ - void arm_fill_q7( - q7_t value, - q7_t * pDst, - uint32_t blockSize); + void arm_fill_q7( + q7_t value, + q7_t *pDst, + uint32_t blockSize); - /** + /** * @brief Fills a constant value into a Q15 vector. * @param[in] value input value to be filled * @param[out] *pDst output pointer * @param[in] blockSize number of samples to process * @return none. */ - void arm_fill_q15( - q15_t value, - q15_t * pDst, - uint32_t blockSize); + void arm_fill_q15( + q15_t value, + q15_t *pDst, + uint32_t blockSize); - /** + /** * @brief Fills a constant value into a Q31 vector. * @param[in] value input value to be filled * @param[out] *pDst output pointer * @param[in] blockSize number of samples to process * @return none. */ - void arm_fill_q31( - q31_t value, - q31_t * pDst, - uint32_t blockSize); + void arm_fill_q31( + q31_t value, + q31_t *pDst, + uint32_t blockSize); -/** + /** * @brief Convolution of floating-point sequences. * @param[in] *pSrcA points to the first input sequence. * @param[in] srcALen length of the first input sequence. @@ -3056,15 +2998,14 @@ void arm_rfft_fast_f32( * @return none. */ - void arm_conv_f32( - float32_t * pSrcA, - uint32_t srcALen, - float32_t * pSrcB, - uint32_t srcBLen, - float32_t * pDst); + void arm_conv_f32( + float32_t *pSrcA, + uint32_t srcALen, + float32_t *pSrcB, + uint32_t srcBLen, + float32_t *pDst); - - /** + /** * @brief Convolution of Q15 sequences. * @param[in] *pSrcA points to the first input sequence. * @param[in] srcALen length of the first input sequence. @@ -3076,18 +3017,16 @@ void arm_rfft_fast_f32( * @return none. */ + void arm_conv_opt_q15( + q15_t *pSrcA, + uint32_t srcALen, + q15_t *pSrcB, + uint32_t srcBLen, + q15_t *pDst, + q15_t *pScratch1, + q15_t *pScratch2); - void arm_conv_opt_q15( - q15_t * pSrcA, - uint32_t srcALen, - q15_t * pSrcB, - uint32_t srcBLen, - q15_t * pDst, - q15_t * pScratch1, - q15_t * pScratch2); - - -/** + /** * @brief Convolution of Q15 sequences. * @param[in] *pSrcA points to the first input sequence. * @param[in] srcALen length of the first input sequence. @@ -3097,14 +3036,14 @@ void arm_rfft_fast_f32( * @return none. */ - void arm_conv_q15( - q15_t * pSrcA, - uint32_t srcALen, - q15_t * pSrcB, - uint32_t srcBLen, - q15_t * pDst); + void arm_conv_q15( + q15_t *pSrcA, + uint32_t srcALen, + q15_t *pSrcB, + uint32_t srcBLen, + q15_t *pDst); - /** + /** * @brief Convolution of Q15 sequences (fast version) for Cortex-M3 and Cortex-M4 * @param[in] *pSrcA points to the first input sequence. * @param[in] srcALen length of the first input sequence. @@ -3114,14 +3053,14 @@ void arm_rfft_fast_f32( * @return none. */ - void arm_conv_fast_q15( - q15_t * pSrcA, - uint32_t srcALen, - q15_t * pSrcB, - uint32_t srcBLen, - q15_t * pDst); + void arm_conv_fast_q15( + q15_t *pSrcA, + uint32_t srcALen, + q15_t *pSrcB, + uint32_t srcBLen, + q15_t *pDst); - /** + /** * @brief Convolution of Q15 sequences (fast version) for Cortex-M3 and Cortex-M4 * @param[in] *pSrcA points to the first input sequence. * @param[in] srcALen length of the first input sequence. @@ -3133,18 +3072,16 @@ void arm_rfft_fast_f32( * @return none. */ - void arm_conv_fast_opt_q15( - q15_t * pSrcA, - uint32_t srcALen, - q15_t * pSrcB, - uint32_t srcBLen, - q15_t * pDst, - q15_t * pScratch1, - q15_t * pScratch2); - - + void arm_conv_fast_opt_q15( + q15_t *pSrcA, + uint32_t srcALen, + q15_t *pSrcB, + uint32_t srcBLen, + q15_t *pDst, + q15_t *pScratch1, + q15_t *pScratch2); - /** + /** * @brief Convolution of Q31 sequences. * @param[in] *pSrcA points to the first input sequence. * @param[in] srcALen length of the first input sequence. @@ -3154,14 +3091,14 @@ void arm_rfft_fast_f32( * @return none. */ - void arm_conv_q31( - q31_t * pSrcA, - uint32_t srcALen, - q31_t * pSrcB, - uint32_t srcBLen, - q31_t * pDst); + void arm_conv_q31( + q31_t *pSrcA, + uint32_t srcALen, + q31_t *pSrcB, + uint32_t srcBLen, + q31_t *pDst); - /** + /** * @brief Convolution of Q31 sequences (fast version) for Cortex-M3 and Cortex-M4 * @param[in] *pSrcA points to the first input sequence. * @param[in] srcALen length of the first input sequence. @@ -3171,13 +3108,12 @@ void arm_rfft_fast_f32( * @return none. */ - void arm_conv_fast_q31( - q31_t * pSrcA, - uint32_t srcALen, - q31_t * pSrcB, - uint32_t srcBLen, - q31_t * pDst); - + void arm_conv_fast_q31( + q31_t *pSrcA, + uint32_t srcALen, + q31_t *pSrcB, + uint32_t srcBLen, + q31_t *pDst); /** * @brief Convolution of Q7 sequences. @@ -3191,18 +3127,16 @@ void arm_rfft_fast_f32( * @return none. */ - void arm_conv_opt_q7( - q7_t * pSrcA, - uint32_t srcALen, - q7_t * pSrcB, - uint32_t srcBLen, - q7_t * pDst, - q15_t * pScratch1, - q15_t * pScratch2); - + void arm_conv_opt_q7( + q7_t *pSrcA, + uint32_t srcALen, + q7_t *pSrcB, + uint32_t srcBLen, + q7_t *pDst, + q15_t *pScratch1, + q15_t *pScratch2); - - /** + /** * @brief Convolution of Q7 sequences. * @param[in] *pSrcA points to the first input sequence. * @param[in] srcALen length of the first input sequence. @@ -3212,15 +3146,14 @@ void arm_rfft_fast_f32( * @return none. */ - void arm_conv_q7( - q7_t * pSrcA, - uint32_t srcALen, - q7_t * pSrcB, - uint32_t srcBLen, - q7_t * pDst); + void arm_conv_q7( + q7_t *pSrcA, + uint32_t srcALen, + q7_t *pSrcB, + uint32_t srcBLen, + q7_t *pDst); - - /** + /** * @brief Partial convolution of floating-point sequences. * @param[in] *pSrcA points to the first input sequence. * @param[in] srcALen length of the first input sequence. @@ -3232,14 +3165,14 @@ void arm_rfft_fast_f32( * @return Returns either ARM_MATH_SUCCESS if the function completed correctly or ARM_MATH_ARGUMENT_ERROR if the requested subset is not in the range [0 srcALen+srcBLen-2]. */ - arm_status arm_conv_partial_f32( - float32_t * pSrcA, - uint32_t srcALen, - float32_t * pSrcB, - uint32_t srcBLen, - float32_t * pDst, - uint32_t firstIndex, - uint32_t numPoints); + arm_status arm_conv_partial_f32( + float32_t *pSrcA, + uint32_t srcALen, + float32_t *pSrcB, + uint32_t srcBLen, + float32_t *pDst, + uint32_t firstIndex, + uint32_t numPoints); /** * @brief Partial convolution of Q15 sequences. @@ -3255,19 +3188,18 @@ void arm_rfft_fast_f32( * @return Returns either ARM_MATH_SUCCESS if the function completed correctly or ARM_MATH_ARGUMENT_ERROR if the requested subset is not in the range [0 srcALen+srcBLen-2]. */ - arm_status arm_conv_partial_opt_q15( - q15_t * pSrcA, - uint32_t srcALen, - q15_t * pSrcB, - uint32_t srcBLen, - q15_t * pDst, - uint32_t firstIndex, - uint32_t numPoints, - q15_t * pScratch1, - q15_t * pScratch2); + arm_status arm_conv_partial_opt_q15( + q15_t *pSrcA, + uint32_t srcALen, + q15_t *pSrcB, + uint32_t srcBLen, + q15_t *pDst, + uint32_t firstIndex, + uint32_t numPoints, + q15_t *pScratch1, + q15_t *pScratch2); - -/** + /** * @brief Partial convolution of Q15 sequences. * @param[in] *pSrcA points to the first input sequence. * @param[in] srcALen length of the first input sequence. @@ -3279,16 +3211,16 @@ void arm_rfft_fast_f32( * @return Returns either ARM_MATH_SUCCESS if the function completed correctly or ARM_MATH_ARGUMENT_ERROR if the requested subset is not in the range [0 srcALen+srcBLen-2]. */ - arm_status arm_conv_partial_q15( - q15_t * pSrcA, - uint32_t srcALen, - q15_t * pSrcB, - uint32_t srcBLen, - q15_t * pDst, - uint32_t firstIndex, - uint32_t numPoints); + arm_status arm_conv_partial_q15( + q15_t *pSrcA, + uint32_t srcALen, + q15_t *pSrcB, + uint32_t srcBLen, + q15_t *pDst, + uint32_t firstIndex, + uint32_t numPoints); - /** + /** * @brief Partial convolution of Q15 sequences (fast version) for Cortex-M3 and Cortex-M4 * @param[in] *pSrcA points to the first input sequence. * @param[in] srcALen length of the first input sequence. @@ -3300,17 +3232,16 @@ void arm_rfft_fast_f32( * @return Returns either ARM_MATH_SUCCESS if the function completed correctly or ARM_MATH_ARGUMENT_ERROR if the requested subset is not in the range [0 srcALen+srcBLen-2]. */ - arm_status arm_conv_partial_fast_q15( - q15_t * pSrcA, - uint32_t srcALen, - q15_t * pSrcB, - uint32_t srcBLen, - q15_t * pDst, - uint32_t firstIndex, - uint32_t numPoints); + arm_status arm_conv_partial_fast_q15( + q15_t *pSrcA, + uint32_t srcALen, + q15_t *pSrcB, + uint32_t srcBLen, + q15_t *pDst, + uint32_t firstIndex, + uint32_t numPoints); - - /** + /** * @brief Partial convolution of Q15 sequences (fast version) for Cortex-M3 and Cortex-M4 * @param[in] *pSrcA points to the first input sequence. * @param[in] srcALen length of the first input sequence. @@ -3324,19 +3255,18 @@ void arm_rfft_fast_f32( * @return Returns either ARM_MATH_SUCCESS if the function completed correctly or ARM_MATH_ARGUMENT_ERROR if the requested subset is not in the range [0 srcALen+srcBLen-2]. */ - arm_status arm_conv_partial_fast_opt_q15( - q15_t * pSrcA, - uint32_t srcALen, - q15_t * pSrcB, - uint32_t srcBLen, - q15_t * pDst, - uint32_t firstIndex, - uint32_t numPoints, - q15_t * pScratch1, - q15_t * pScratch2); + arm_status arm_conv_partial_fast_opt_q15( + q15_t *pSrcA, + uint32_t srcALen, + q15_t *pSrcB, + uint32_t srcBLen, + q15_t *pDst, + uint32_t firstIndex, + uint32_t numPoints, + q15_t *pScratch1, + q15_t *pScratch2); - - /** + /** * @brief Partial convolution of Q31 sequences. * @param[in] *pSrcA points to the first input sequence. * @param[in] srcALen length of the first input sequence. @@ -3348,17 +3278,16 @@ void arm_rfft_fast_f32( * @return Returns either ARM_MATH_SUCCESS if the function completed correctly or ARM_MATH_ARGUMENT_ERROR if the requested subset is not in the range [0 srcALen+srcBLen-2]. */ - arm_status arm_conv_partial_q31( - q31_t * pSrcA, - uint32_t srcALen, - q31_t * pSrcB, - uint32_t srcBLen, - q31_t * pDst, - uint32_t firstIndex, - uint32_t numPoints); + arm_status arm_conv_partial_q31( + q31_t *pSrcA, + uint32_t srcALen, + q31_t *pSrcB, + uint32_t srcBLen, + q31_t *pDst, + uint32_t firstIndex, + uint32_t numPoints); - - /** + /** * @brief Partial convolution of Q31 sequences (fast version) for Cortex-M3 and Cortex-M4 * @param[in] *pSrcA points to the first input sequence. * @param[in] srcALen length of the first input sequence. @@ -3370,17 +3299,16 @@ void arm_rfft_fast_f32( * @return Returns either ARM_MATH_SUCCESS if the function completed correctly or ARM_MATH_ARGUMENT_ERROR if the requested subset is not in the range [0 srcALen+srcBLen-2]. */ - arm_status arm_conv_partial_fast_q31( - q31_t * pSrcA, - uint32_t srcALen, - q31_t * pSrcB, - uint32_t srcBLen, - q31_t * pDst, - uint32_t firstIndex, - uint32_t numPoints); + arm_status arm_conv_partial_fast_q31( + q31_t *pSrcA, + uint32_t srcALen, + q31_t *pSrcB, + uint32_t srcBLen, + q31_t *pDst, + uint32_t firstIndex, + uint32_t numPoints); - - /** + /** * @brief Partial convolution of Q7 sequences * @param[in] *pSrcA points to the first input sequence. * @param[in] srcALen length of the first input sequence. @@ -3394,19 +3322,18 @@ void arm_rfft_fast_f32( * @return Returns either ARM_MATH_SUCCESS if the function completed correctly or ARM_MATH_ARGUMENT_ERROR if the requested subset is not in the range [0 srcALen+srcBLen-2]. */ - arm_status arm_conv_partial_opt_q7( - q7_t * pSrcA, - uint32_t srcALen, - q7_t * pSrcB, - uint32_t srcBLen, - q7_t * pDst, - uint32_t firstIndex, - uint32_t numPoints, - q15_t * pScratch1, - q15_t * pScratch2); + arm_status arm_conv_partial_opt_q7( + q7_t *pSrcA, + uint32_t srcALen, + q7_t *pSrcB, + uint32_t srcBLen, + q7_t *pDst, + uint32_t firstIndex, + uint32_t numPoints, + q15_t *pScratch1, + q15_t *pScratch2); - -/** + /** * @brief Partial convolution of Q7 sequences. * @param[in] *pSrcA points to the first input sequence. * @param[in] srcALen length of the first input sequence. @@ -3418,58 +3345,54 @@ void arm_rfft_fast_f32( * @return Returns either ARM_MATH_SUCCESS if the function completed correctly or ARM_MATH_ARGUMENT_ERROR if the requested subset is not in the range [0 srcALen+srcBLen-2]. */ - arm_status arm_conv_partial_q7( - q7_t * pSrcA, - uint32_t srcALen, - q7_t * pSrcB, - uint32_t srcBLen, - q7_t * pDst, - uint32_t firstIndex, - uint32_t numPoints); - + arm_status arm_conv_partial_q7( + q7_t *pSrcA, + uint32_t srcALen, + q7_t *pSrcB, + uint32_t srcBLen, + q7_t *pDst, + uint32_t firstIndex, + uint32_t numPoints); - - /** + /** * @brief Instance structure for the Q15 FIR decimator. */ - typedef struct - { - uint8_t M; /**< decimation factor. */ - uint16_t numTaps; /**< number of coefficients in the filter. */ - q15_t *pCoeffs; /**< points to the coefficient array. The array is of length numTaps.*/ - q15_t *pState; /**< points to the state variable array. The array is of length numTaps+blockSize-1. */ - } arm_fir_decimate_instance_q15; + typedef struct + { + uint8_t M; /**< decimation factor. */ + uint16_t numTaps; /**< number of coefficients in the filter. */ + q15_t *pCoeffs; /**< points to the coefficient array. The array is of length numTaps.*/ + q15_t *pState; /**< points to the state variable array. The array is of length numTaps+blockSize-1. */ + } arm_fir_decimate_instance_q15; - /** + /** * @brief Instance structure for the Q31 FIR decimator. */ - typedef struct - { - uint8_t M; /**< decimation factor. */ - uint16_t numTaps; /**< number of coefficients in the filter. */ - q31_t *pCoeffs; /**< points to the coefficient array. The array is of length numTaps.*/ - q31_t *pState; /**< points to the state variable array. The array is of length numTaps+blockSize-1. */ + typedef struct + { + uint8_t M; /**< decimation factor. */ + uint16_t numTaps; /**< number of coefficients in the filter. */ + q31_t *pCoeffs; /**< points to the coefficient array. The array is of length numTaps.*/ + q31_t *pState; /**< points to the state variable array. The array is of length numTaps+blockSize-1. */ - } arm_fir_decimate_instance_q31; + } arm_fir_decimate_instance_q31; - /** + /** * @brief Instance structure for the floating-point FIR decimator. */ - typedef struct - { - uint8_t M; /**< decimation factor. */ - uint16_t numTaps; /**< number of coefficients in the filter. */ - float32_t *pCoeffs; /**< points to the coefficient array. The array is of length numTaps.*/ - float32_t *pState; /**< points to the state variable array. The array is of length numTaps+blockSize-1. */ - - } arm_fir_decimate_instance_f32; - + typedef struct + { + uint8_t M; /**< decimation factor. */ + uint16_t numTaps; /**< number of coefficients in the filter. */ + float32_t *pCoeffs; /**< points to the coefficient array. The array is of length numTaps.*/ + float32_t *pState; /**< points to the state variable array. The array is of length numTaps+blockSize-1. */ + } arm_fir_decimate_instance_f32; - /** + /** * @brief Processing function for the floating-point FIR decimator. * @param[in] *S points to an instance of the floating-point FIR decimator structure. * @param[in] *pSrc points to the block of input data. @@ -3478,14 +3401,13 @@ void arm_rfft_fast_f32( * @return none */ - void arm_fir_decimate_f32( - const arm_fir_decimate_instance_f32 * S, - float32_t * pSrc, - float32_t * pDst, - uint32_t blockSize); + void arm_fir_decimate_f32( + const arm_fir_decimate_instance_f32 *S, + float32_t *pSrc, + float32_t *pDst, + uint32_t blockSize); - - /** + /** * @brief Initialization function for the floating-point FIR decimator. * @param[in,out] *S points to an instance of the floating-point FIR decimator structure. * @param[in] numTaps number of coefficients in the filter. @@ -3497,15 +3419,15 @@ void arm_rfft_fast_f32( * blockSize is not a multiple of M. */ - arm_status arm_fir_decimate_init_f32( - arm_fir_decimate_instance_f32 * S, - uint16_t numTaps, - uint8_t M, - float32_t * pCoeffs, - float32_t * pState, - uint32_t blockSize); + arm_status arm_fir_decimate_init_f32( + arm_fir_decimate_instance_f32 *S, + uint16_t numTaps, + uint8_t M, + float32_t *pCoeffs, + float32_t *pState, + uint32_t blockSize); - /** + /** * @brief Processing function for the Q15 FIR decimator. * @param[in] *S points to an instance of the Q15 FIR decimator structure. * @param[in] *pSrc points to the block of input data. @@ -3514,13 +3436,13 @@ void arm_rfft_fast_f32( * @return none */ - void arm_fir_decimate_q15( - const arm_fir_decimate_instance_q15 * S, - q15_t * pSrc, - q15_t * pDst, - uint32_t blockSize); + void arm_fir_decimate_q15( + const arm_fir_decimate_instance_q15 *S, + q15_t *pSrc, + q15_t *pDst, + uint32_t blockSize); - /** + /** * @brief Processing function for the Q15 FIR decimator (fast variant) for Cortex-M3 and Cortex-M4. * @param[in] *S points to an instance of the Q15 FIR decimator structure. * @param[in] *pSrc points to the block of input data. @@ -3529,15 +3451,13 @@ void arm_rfft_fast_f32( * @return none */ - void arm_fir_decimate_fast_q15( - const arm_fir_decimate_instance_q15 * S, - q15_t * pSrc, - q15_t * pDst, - uint32_t blockSize); - - + void arm_fir_decimate_fast_q15( + const arm_fir_decimate_instance_q15 *S, + q15_t *pSrc, + q15_t *pDst, + uint32_t blockSize); - /** + /** * @brief Initialization function for the Q15 FIR decimator. * @param[in,out] *S points to an instance of the Q15 FIR decimator structure. * @param[in] numTaps number of coefficients in the filter. @@ -3549,15 +3469,15 @@ void arm_rfft_fast_f32( * blockSize is not a multiple of M. */ - arm_status arm_fir_decimate_init_q15( - arm_fir_decimate_instance_q15 * S, - uint16_t numTaps, - uint8_t M, - q15_t * pCoeffs, - q15_t * pState, - uint32_t blockSize); + arm_status arm_fir_decimate_init_q15( + arm_fir_decimate_instance_q15 *S, + uint16_t numTaps, + uint8_t M, + q15_t *pCoeffs, + q15_t *pState, + uint32_t blockSize); - /** + /** * @brief Processing function for the Q31 FIR decimator. * @param[in] *S points to an instance of the Q31 FIR decimator structure. * @param[in] *pSrc points to the block of input data. @@ -3566,13 +3486,13 @@ void arm_rfft_fast_f32( * @return none */ - void arm_fir_decimate_q31( - const arm_fir_decimate_instance_q31 * S, - q31_t * pSrc, - q31_t * pDst, - uint32_t blockSize); + void arm_fir_decimate_q31( + const arm_fir_decimate_instance_q31 *S, + q31_t *pSrc, + q31_t *pDst, + uint32_t blockSize); - /** + /** * @brief Processing function for the Q31 FIR decimator (fast variant) for Cortex-M3 and Cortex-M4. * @param[in] *S points to an instance of the Q31 FIR decimator structure. * @param[in] *pSrc points to the block of input data. @@ -3581,14 +3501,13 @@ void arm_rfft_fast_f32( * @return none */ - void arm_fir_decimate_fast_q31( - arm_fir_decimate_instance_q31 * S, - q31_t * pSrc, - q31_t * pDst, - uint32_t blockSize); - + void arm_fir_decimate_fast_q31( + arm_fir_decimate_instance_q31 *S, + q31_t *pSrc, + q31_t *pDst, + uint32_t blockSize); - /** + /** * @brief Initialization function for the Q31 FIR decimator. * @param[in,out] *S points to an instance of the Q31 FIR decimator structure. * @param[in] numTaps number of coefficients in the filter. @@ -3600,54 +3519,51 @@ void arm_rfft_fast_f32( * blockSize is not a multiple of M. */ - arm_status arm_fir_decimate_init_q31( - arm_fir_decimate_instance_q31 * S, - uint16_t numTaps, - uint8_t M, - q31_t * pCoeffs, - q31_t * pState, - uint32_t blockSize); - + arm_status arm_fir_decimate_init_q31( + arm_fir_decimate_instance_q31 *S, + uint16_t numTaps, + uint8_t M, + q31_t *pCoeffs, + q31_t *pState, + uint32_t blockSize); - - /** + /** * @brief Instance structure for the Q15 FIR interpolator. */ - typedef struct - { - uint8_t L; /**< upsample factor. */ - uint16_t phaseLength; /**< length of each polyphase filter component. */ - q15_t *pCoeffs; /**< points to the coefficient array. The array is of length L*phaseLength. */ - q15_t *pState; /**< points to the state variable array. The array is of length blockSize+phaseLength-1. */ - } arm_fir_interpolate_instance_q15; + typedef struct + { + uint8_t L; /**< upsample factor. */ + uint16_t phaseLength; /**< length of each polyphase filter component. */ + q15_t *pCoeffs; /**< points to the coefficient array. The array is of length L*phaseLength. */ + q15_t *pState; /**< points to the state variable array. The array is of length blockSize+phaseLength-1. */ + } arm_fir_interpolate_instance_q15; - /** + /** * @brief Instance structure for the Q31 FIR interpolator. */ - typedef struct - { - uint8_t L; /**< upsample factor. */ - uint16_t phaseLength; /**< length of each polyphase filter component. */ - q31_t *pCoeffs; /**< points to the coefficient array. The array is of length L*phaseLength. */ - q31_t *pState; /**< points to the state variable array. The array is of length blockSize+phaseLength-1. */ - } arm_fir_interpolate_instance_q31; + typedef struct + { + uint8_t L; /**< upsample factor. */ + uint16_t phaseLength; /**< length of each polyphase filter component. */ + q31_t *pCoeffs; /**< points to the coefficient array. The array is of length L*phaseLength. */ + q31_t *pState; /**< points to the state variable array. The array is of length blockSize+phaseLength-1. */ + } arm_fir_interpolate_instance_q31; - /** + /** * @brief Instance structure for the floating-point FIR interpolator. */ - typedef struct - { - uint8_t L; /**< upsample factor. */ - uint16_t phaseLength; /**< length of each polyphase filter component. */ - float32_t *pCoeffs; /**< points to the coefficient array. The array is of length L*phaseLength. */ - float32_t *pState; /**< points to the state variable array. The array is of length phaseLength+numTaps-1. */ - } arm_fir_interpolate_instance_f32; - + typedef struct + { + uint8_t L; /**< upsample factor. */ + uint16_t phaseLength; /**< length of each polyphase filter component. */ + float32_t *pCoeffs; /**< points to the coefficient array. The array is of length L*phaseLength. */ + float32_t *pState; /**< points to the state variable array. The array is of length phaseLength+numTaps-1. */ + } arm_fir_interpolate_instance_f32; - /** + /** * @brief Processing function for the Q15 FIR interpolator. * @param[in] *S points to an instance of the Q15 FIR interpolator structure. * @param[in] *pSrc points to the block of input data. @@ -3656,14 +3572,13 @@ void arm_rfft_fast_f32( * @return none. */ - void arm_fir_interpolate_q15( - const arm_fir_interpolate_instance_q15 * S, - q15_t * pSrc, - q15_t * pDst, - uint32_t blockSize); - + void arm_fir_interpolate_q15( + const arm_fir_interpolate_instance_q15 *S, + q15_t *pSrc, + q15_t *pDst, + uint32_t blockSize); - /** + /** * @brief Initialization function for the Q15 FIR interpolator. * @param[in,out] *S points to an instance of the Q15 FIR interpolator structure. * @param[in] L upsample factor. @@ -3675,15 +3590,15 @@ void arm_rfft_fast_f32( * the filter length numTaps is not a multiple of the interpolation factor L. */ - arm_status arm_fir_interpolate_init_q15( - arm_fir_interpolate_instance_q15 * S, - uint8_t L, - uint16_t numTaps, - q15_t * pCoeffs, - q15_t * pState, - uint32_t blockSize); + arm_status arm_fir_interpolate_init_q15( + arm_fir_interpolate_instance_q15 *S, + uint8_t L, + uint16_t numTaps, + q15_t *pCoeffs, + q15_t *pState, + uint32_t blockSize); - /** + /** * @brief Processing function for the Q31 FIR interpolator. * @param[in] *S points to an instance of the Q15 FIR interpolator structure. * @param[in] *pSrc points to the block of input data. @@ -3692,13 +3607,13 @@ void arm_rfft_fast_f32( * @return none. */ - void arm_fir_interpolate_q31( - const arm_fir_interpolate_instance_q31 * S, - q31_t * pSrc, - q31_t * pDst, - uint32_t blockSize); + void arm_fir_interpolate_q31( + const arm_fir_interpolate_instance_q31 *S, + q31_t *pSrc, + q31_t *pDst, + uint32_t blockSize); - /** + /** * @brief Initialization function for the Q31 FIR interpolator. * @param[in,out] *S points to an instance of the Q31 FIR interpolator structure. * @param[in] L upsample factor. @@ -3710,16 +3625,15 @@ void arm_rfft_fast_f32( * the filter length numTaps is not a multiple of the interpolation factor L. */ - arm_status arm_fir_interpolate_init_q31( - arm_fir_interpolate_instance_q31 * S, - uint8_t L, - uint16_t numTaps, - q31_t * pCoeffs, - q31_t * pState, - uint32_t blockSize); - + arm_status arm_fir_interpolate_init_q31( + arm_fir_interpolate_instance_q31 *S, + uint8_t L, + uint16_t numTaps, + q31_t *pCoeffs, + q31_t *pState, + uint32_t blockSize); - /** + /** * @brief Processing function for the floating-point FIR interpolator. * @param[in] *S points to an instance of the floating-point FIR interpolator structure. * @param[in] *pSrc points to the block of input data. @@ -3728,13 +3642,13 @@ void arm_rfft_fast_f32( * @return none. */ - void arm_fir_interpolate_f32( - const arm_fir_interpolate_instance_f32 * S, - float32_t * pSrc, - float32_t * pDst, - uint32_t blockSize); + void arm_fir_interpolate_f32( + const arm_fir_interpolate_instance_f32 *S, + float32_t *pSrc, + float32_t *pDst, + uint32_t blockSize); - /** + /** * @brief Initialization function for the floating-point FIR interpolator. * @param[in,out] *S points to an instance of the floating-point FIR interpolator structure. * @param[in] L upsample factor. @@ -3746,29 +3660,28 @@ void arm_rfft_fast_f32( * the filter length numTaps is not a multiple of the interpolation factor L. */ - arm_status arm_fir_interpolate_init_f32( - arm_fir_interpolate_instance_f32 * S, - uint8_t L, - uint16_t numTaps, - float32_t * pCoeffs, - float32_t * pState, - uint32_t blockSize); + arm_status arm_fir_interpolate_init_f32( + arm_fir_interpolate_instance_f32 *S, + uint8_t L, + uint16_t numTaps, + float32_t *pCoeffs, + float32_t *pState, + uint32_t blockSize); - /** + /** * @brief Instance structure for the high precision Q31 Biquad cascade filter. */ - typedef struct - { - uint8_t numStages; /**< number of 2nd order stages in the filter. Overall order is 2*numStages. */ - q63_t *pState; /**< points to the array of state coefficients. The array is of length 4*numStages. */ - q31_t *pCoeffs; /**< points to the array of coefficients. The array is of length 5*numStages. */ - uint8_t postShift; /**< additional shift, in bits, applied to each output sample. */ - - } arm_biquad_cas_df1_32x64_ins_q31; + typedef struct + { + uint8_t numStages; /**< number of 2nd order stages in the filter. Overall order is 2*numStages. */ + q63_t *pState; /**< points to the array of state coefficients. The array is of length 4*numStages. */ + q31_t *pCoeffs; /**< points to the array of coefficients. The array is of length 5*numStages. */ + uint8_t postShift; /**< additional shift, in bits, applied to each output sample. */ + } arm_biquad_cas_df1_32x64_ins_q31; - /** + /** * @param[in] *S points to an instance of the high precision Q31 Biquad cascade filter structure. * @param[in] *pSrc points to the block of input data. * @param[out] *pDst points to the block of output data @@ -3776,14 +3689,13 @@ void arm_rfft_fast_f32( * @return none. */ - void arm_biquad_cas_df1_32x64_q31( - const arm_biquad_cas_df1_32x64_ins_q31 * S, - q31_t * pSrc, - q31_t * pDst, - uint32_t blockSize); + void arm_biquad_cas_df1_32x64_q31( + const arm_biquad_cas_df1_32x64_ins_q31 *S, + q31_t *pSrc, + q31_t *pDst, + uint32_t blockSize); - - /** + /** * @param[in,out] *S points to an instance of the high precision Q31 Biquad cascade filter structure. * @param[in] numStages number of 2nd order stages in the filter. * @param[in] *pCoeffs points to the filter coefficients. @@ -3792,54 +3704,47 @@ void arm_rfft_fast_f32( * @return none */ - void arm_biquad_cas_df1_32x64_init_q31( - arm_biquad_cas_df1_32x64_ins_q31 * S, - uint8_t numStages, - q31_t * pCoeffs, - q63_t * pState, - uint8_t postShift); + void arm_biquad_cas_df1_32x64_init_q31( + arm_biquad_cas_df1_32x64_ins_q31 *S, + uint8_t numStages, + q31_t *pCoeffs, + q63_t *pState, + uint8_t postShift); - - - /** + /** * @brief Instance structure for the floating-point transposed direct form II Biquad cascade filter. */ - typedef struct - { - uint8_t numStages; /**< number of 2nd order stages in the filter. Overall order is 2*numStages. */ - float32_t *pState; /**< points to the array of state coefficients. The array is of length 2*numStages. */ - float32_t *pCoeffs; /**< points to the array of coefficients. The array is of length 5*numStages. */ - } arm_biquad_cascade_df2T_instance_f32; - - + typedef struct + { + uint8_t numStages; /**< number of 2nd order stages in the filter. Overall order is 2*numStages. */ + float32_t *pState; /**< points to the array of state coefficients. The array is of length 2*numStages. */ + float32_t *pCoeffs; /**< points to the array of coefficients. The array is of length 5*numStages. */ + } arm_biquad_cascade_df2T_instance_f32; - /** + /** * @brief Instance structure for the floating-point transposed direct form II Biquad cascade filter. */ - typedef struct - { - uint8_t numStages; /**< number of 2nd order stages in the filter. Overall order is 2*numStages. */ - float32_t *pState; /**< points to the array of state coefficients. The array is of length 4*numStages. */ - float32_t *pCoeffs; /**< points to the array of coefficients. The array is of length 5*numStages. */ - } arm_biquad_cascade_stereo_df2T_instance_f32; - - + typedef struct + { + uint8_t numStages; /**< number of 2nd order stages in the filter. Overall order is 2*numStages. */ + float32_t *pState; /**< points to the array of state coefficients. The array is of length 4*numStages. */ + float32_t *pCoeffs; /**< points to the array of coefficients. The array is of length 5*numStages. */ + } arm_biquad_cascade_stereo_df2T_instance_f32; - /** + /** * @brief Instance structure for the floating-point transposed direct form II Biquad cascade filter. */ - typedef struct - { - uint8_t numStages; /**< number of 2nd order stages in the filter. Overall order is 2*numStages. */ - float64_t *pState; /**< points to the array of state coefficients. The array is of length 2*numStages. */ - float64_t *pCoeffs; /**< points to the array of coefficients. The array is of length 5*numStages. */ - } arm_biquad_cascade_df2T_instance_f64; - + typedef struct + { + uint8_t numStages; /**< number of 2nd order stages in the filter. Overall order is 2*numStages. */ + float64_t *pState; /**< points to the array of state coefficients. The array is of length 2*numStages. */ + float64_t *pCoeffs; /**< points to the array of coefficients. The array is of length 5*numStages. */ + } arm_biquad_cascade_df2T_instance_f64; - /** + /** * @brief Processing function for the floating-point transposed direct form II Biquad cascade filter. * @param[in] *S points to an instance of the filter data structure. * @param[in] *pSrc points to the block of input data. @@ -3848,14 +3753,13 @@ void arm_rfft_fast_f32( * @return none. */ - void arm_biquad_cascade_df2T_f32( - const arm_biquad_cascade_df2T_instance_f32 * S, - float32_t * pSrc, - float32_t * pDst, - uint32_t blockSize); + void arm_biquad_cascade_df2T_f32( + const arm_biquad_cascade_df2T_instance_f32 *S, + float32_t *pSrc, + float32_t *pDst, + uint32_t blockSize); - - /** + /** * @brief Processing function for the floating-point transposed direct form II Biquad cascade filter. 2 channels * @param[in] *S points to an instance of the filter data structure. * @param[in] *pSrc points to the block of input data. @@ -3864,13 +3768,13 @@ void arm_rfft_fast_f32( * @return none. */ - void arm_biquad_cascade_stereo_df2T_f32( - const arm_biquad_cascade_stereo_df2T_instance_f32 * S, - float32_t * pSrc, - float32_t * pDst, - uint32_t blockSize); + void arm_biquad_cascade_stereo_df2T_f32( + const arm_biquad_cascade_stereo_df2T_instance_f32 *S, + float32_t *pSrc, + float32_t *pDst, + uint32_t blockSize); - /** + /** * @brief Processing function for the floating-point transposed direct form II Biquad cascade filter. * @param[in] *S points to an instance of the filter data structure. * @param[in] *pSrc points to the block of input data. @@ -3879,14 +3783,13 @@ void arm_rfft_fast_f32( * @return none. */ - void arm_biquad_cascade_df2T_f64( - const arm_biquad_cascade_df2T_instance_f64 * S, - float64_t * pSrc, - float64_t * pDst, - uint32_t blockSize); - + void arm_biquad_cascade_df2T_f64( + const arm_biquad_cascade_df2T_instance_f64 *S, + float64_t *pSrc, + float64_t *pDst, + uint32_t blockSize); - /** + /** * @brief Initialization function for the floating-point transposed direct form II Biquad cascade filter. * @param[in,out] *S points to an instance of the filter data structure. * @param[in] numStages number of 2nd order stages in the filter. @@ -3895,14 +3798,13 @@ void arm_rfft_fast_f32( * @return none */ - void arm_biquad_cascade_df2T_init_f32( - arm_biquad_cascade_df2T_instance_f32 * S, - uint8_t numStages, - float32_t * pCoeffs, - float32_t * pState); - + void arm_biquad_cascade_df2T_init_f32( + arm_biquad_cascade_df2T_instance_f32 *S, + uint8_t numStages, + float32_t *pCoeffs, + float32_t *pState); - /** + /** * @brief Initialization function for the floating-point transposed direct form II Biquad cascade filter. * @param[in,out] *S points to an instance of the filter data structure. * @param[in] numStages number of 2nd order stages in the filter. @@ -3911,14 +3813,13 @@ void arm_rfft_fast_f32( * @return none */ - void arm_biquad_cascade_stereo_df2T_init_f32( - arm_biquad_cascade_stereo_df2T_instance_f32 * S, - uint8_t numStages, - float32_t * pCoeffs, - float32_t * pState); - + void arm_biquad_cascade_stereo_df2T_init_f32( + arm_biquad_cascade_stereo_df2T_instance_f32 *S, + uint8_t numStages, + float32_t *pCoeffs, + float32_t *pState); - /** + /** * @brief Initialization function for the floating-point transposed direct form II Biquad cascade filter. * @param[in,out] *S points to an instance of the filter data structure. * @param[in] numStages number of 2nd order stages in the filter. @@ -3927,48 +3828,46 @@ void arm_rfft_fast_f32( * @return none */ - void arm_biquad_cascade_df2T_init_f64( - arm_biquad_cascade_df2T_instance_f64 * S, - uint8_t numStages, - float64_t * pCoeffs, - float64_t * pState); - + void arm_biquad_cascade_df2T_init_f64( + arm_biquad_cascade_df2T_instance_f64 *S, + uint8_t numStages, + float64_t *pCoeffs, + float64_t *pState); - - /** + /** * @brief Instance structure for the Q15 FIR lattice filter. */ - typedef struct - { - uint16_t numStages; /**< number of filter stages. */ - q15_t *pState; /**< points to the state variable array. The array is of length numStages. */ - q15_t *pCoeffs; /**< points to the coefficient array. The array is of length numStages. */ - } arm_fir_lattice_instance_q15; + typedef struct + { + uint16_t numStages; /**< number of filter stages. */ + q15_t *pState; /**< points to the state variable array. The array is of length numStages. */ + q15_t *pCoeffs; /**< points to the coefficient array. The array is of length numStages. */ + } arm_fir_lattice_instance_q15; - /** + /** * @brief Instance structure for the Q31 FIR lattice filter. */ - typedef struct - { - uint16_t numStages; /**< number of filter stages. */ - q31_t *pState; /**< points to the state variable array. The array is of length numStages. */ - q31_t *pCoeffs; /**< points to the coefficient array. The array is of length numStages. */ - } arm_fir_lattice_instance_q31; + typedef struct + { + uint16_t numStages; /**< number of filter stages. */ + q31_t *pState; /**< points to the state variable array. The array is of length numStages. */ + q31_t *pCoeffs; /**< points to the coefficient array. The array is of length numStages. */ + } arm_fir_lattice_instance_q31; - /** + /** * @brief Instance structure for the floating-point FIR lattice filter. */ - typedef struct - { - uint16_t numStages; /**< number of filter stages. */ - float32_t *pState; /**< points to the state variable array. The array is of length numStages. */ - float32_t *pCoeffs; /**< points to the coefficient array. The array is of length numStages. */ - } arm_fir_lattice_instance_f32; + typedef struct + { + uint16_t numStages; /**< number of filter stages. */ + float32_t *pState; /**< points to the state variable array. The array is of length numStages. */ + float32_t *pCoeffs; /**< points to the coefficient array. The array is of length numStages. */ + } arm_fir_lattice_instance_f32; - /** + /** * @brief Initialization function for the Q15 FIR lattice filter. * @param[in] *S points to an instance of the Q15 FIR lattice structure. * @param[in] numStages number of filter stages. @@ -3977,14 +3876,13 @@ void arm_rfft_fast_f32( * @return none. */ - void arm_fir_lattice_init_q15( - arm_fir_lattice_instance_q15 * S, - uint16_t numStages, - q15_t * pCoeffs, - q15_t * pState); + void arm_fir_lattice_init_q15( + arm_fir_lattice_instance_q15 *S, + uint16_t numStages, + q15_t *pCoeffs, + q15_t *pState); - - /** + /** * @brief Processing function for the Q15 FIR lattice filter. * @param[in] *S points to an instance of the Q15 FIR lattice structure. * @param[in] *pSrc points to the block of input data. @@ -3992,13 +3890,13 @@ void arm_rfft_fast_f32( * @param[in] blockSize number of samples to process. * @return none. */ - void arm_fir_lattice_q15( - const arm_fir_lattice_instance_q15 * S, - q15_t * pSrc, - q15_t * pDst, - uint32_t blockSize); + void arm_fir_lattice_q15( + const arm_fir_lattice_instance_q15 *S, + q15_t *pSrc, + q15_t *pDst, + uint32_t blockSize); - /** + /** * @brief Initialization function for the Q31 FIR lattice filter. * @param[in] *S points to an instance of the Q31 FIR lattice structure. * @param[in] numStages number of filter stages. @@ -4007,14 +3905,13 @@ void arm_rfft_fast_f32( * @return none. */ - void arm_fir_lattice_init_q31( - arm_fir_lattice_instance_q31 * S, - uint16_t numStages, - q31_t * pCoeffs, - q31_t * pState); - + void arm_fir_lattice_init_q31( + arm_fir_lattice_instance_q31 *S, + uint16_t numStages, + q31_t *pCoeffs, + q31_t *pState); - /** + /** * @brief Processing function for the Q31 FIR lattice filter. * @param[in] *S points to an instance of the Q31 FIR lattice structure. * @param[in] *pSrc points to the block of input data. @@ -4023,13 +3920,13 @@ void arm_rfft_fast_f32( * @return none. */ - void arm_fir_lattice_q31( - const arm_fir_lattice_instance_q31 * S, - q31_t * pSrc, - q31_t * pDst, - uint32_t blockSize); + void arm_fir_lattice_q31( + const arm_fir_lattice_instance_q31 *S, + q31_t *pSrc, + q31_t *pDst, + uint32_t blockSize); -/** + /** * @brief Initialization function for the floating-point FIR lattice filter. * @param[in] *S points to an instance of the floating-point FIR lattice structure. * @param[in] numStages number of filter stages. @@ -4038,13 +3935,13 @@ void arm_rfft_fast_f32( * @return none. */ - void arm_fir_lattice_init_f32( - arm_fir_lattice_instance_f32 * S, - uint16_t numStages, - float32_t * pCoeffs, - float32_t * pState); + void arm_fir_lattice_init_f32( + arm_fir_lattice_instance_f32 *S, + uint16_t numStages, + float32_t *pCoeffs, + float32_t *pState); - /** + /** * @brief Processing function for the floating-point FIR lattice filter. * @param[in] *S points to an instance of the floating-point FIR lattice structure. * @param[in] *pSrc points to the block of input data. @@ -4053,46 +3950,46 @@ void arm_rfft_fast_f32( * @return none. */ - void arm_fir_lattice_f32( - const arm_fir_lattice_instance_f32 * S, - float32_t * pSrc, - float32_t * pDst, - uint32_t blockSize); + void arm_fir_lattice_f32( + const arm_fir_lattice_instance_f32 *S, + float32_t *pSrc, + float32_t *pDst, + uint32_t blockSize); - /** + /** * @brief Instance structure for the Q15 IIR lattice filter. */ - typedef struct - { - uint16_t numStages; /**< number of stages in the filter. */ - q15_t *pState; /**< points to the state variable array. The array is of length numStages+blockSize. */ - q15_t *pkCoeffs; /**< points to the reflection coefficient array. The array is of length numStages. */ - q15_t *pvCoeffs; /**< points to the ladder coefficient array. The array is of length numStages+1. */ - } arm_iir_lattice_instance_q15; + typedef struct + { + uint16_t numStages; /**< number of stages in the filter. */ + q15_t *pState; /**< points to the state variable array. The array is of length numStages+blockSize. */ + q15_t *pkCoeffs; /**< points to the reflection coefficient array. The array is of length numStages. */ + q15_t *pvCoeffs; /**< points to the ladder coefficient array. The array is of length numStages+1. */ + } arm_iir_lattice_instance_q15; - /** + /** * @brief Instance structure for the Q31 IIR lattice filter. */ - typedef struct - { - uint16_t numStages; /**< number of stages in the filter. */ - q31_t *pState; /**< points to the state variable array. The array is of length numStages+blockSize. */ - q31_t *pkCoeffs; /**< points to the reflection coefficient array. The array is of length numStages. */ - q31_t *pvCoeffs; /**< points to the ladder coefficient array. The array is of length numStages+1. */ - } arm_iir_lattice_instance_q31; + typedef struct + { + uint16_t numStages; /**< number of stages in the filter. */ + q31_t *pState; /**< points to the state variable array. The array is of length numStages+blockSize. */ + q31_t *pkCoeffs; /**< points to the reflection coefficient array. The array is of length numStages. */ + q31_t *pvCoeffs; /**< points to the ladder coefficient array. The array is of length numStages+1. */ + } arm_iir_lattice_instance_q31; - /** + /** * @brief Instance structure for the floating-point IIR lattice filter. */ - typedef struct - { - uint16_t numStages; /**< number of stages in the filter. */ - float32_t *pState; /**< points to the state variable array. The array is of length numStages+blockSize. */ - float32_t *pkCoeffs; /**< points to the reflection coefficient array. The array is of length numStages. */ - float32_t *pvCoeffs; /**< points to the ladder coefficient array. The array is of length numStages+1. */ - } arm_iir_lattice_instance_f32; + typedef struct + { + uint16_t numStages; /**< number of stages in the filter. */ + float32_t *pState; /**< points to the state variable array. The array is of length numStages+blockSize. */ + float32_t *pkCoeffs; /**< points to the reflection coefficient array. The array is of length numStages. */ + float32_t *pvCoeffs; /**< points to the ladder coefficient array. The array is of length numStages+1. */ + } arm_iir_lattice_instance_f32; - /** + /** * @brief Processing function for the floating-point IIR lattice filter. * @param[in] *S points to an instance of the floating-point IIR lattice structure. * @param[in] *pSrc points to the block of input data. @@ -4101,13 +3998,13 @@ void arm_rfft_fast_f32( * @return none. */ - void arm_iir_lattice_f32( - const arm_iir_lattice_instance_f32 * S, - float32_t * pSrc, - float32_t * pDst, - uint32_t blockSize); + void arm_iir_lattice_f32( + const arm_iir_lattice_instance_f32 *S, + float32_t *pSrc, + float32_t *pDst, + uint32_t blockSize); - /** + /** * @brief Initialization function for the floating-point IIR lattice filter. * @param[in] *S points to an instance of the floating-point IIR lattice structure. * @param[in] numStages number of stages in the filter. @@ -4118,16 +4015,15 @@ void arm_rfft_fast_f32( * @return none. */ - void arm_iir_lattice_init_f32( - arm_iir_lattice_instance_f32 * S, - uint16_t numStages, - float32_t * pkCoeffs, - float32_t * pvCoeffs, - float32_t * pState, - uint32_t blockSize); + void arm_iir_lattice_init_f32( + arm_iir_lattice_instance_f32 *S, + uint16_t numStages, + float32_t *pkCoeffs, + float32_t *pvCoeffs, + float32_t *pState, + uint32_t blockSize); - - /** + /** * @brief Processing function for the Q31 IIR lattice filter. * @param[in] *S points to an instance of the Q31 IIR lattice structure. * @param[in] *pSrc points to the block of input data. @@ -4136,14 +4032,13 @@ void arm_rfft_fast_f32( * @return none. */ - void arm_iir_lattice_q31( - const arm_iir_lattice_instance_q31 * S, - q31_t * pSrc, - q31_t * pDst, - uint32_t blockSize); + void arm_iir_lattice_q31( + const arm_iir_lattice_instance_q31 *S, + q31_t *pSrc, + q31_t *pDst, + uint32_t blockSize); - - /** + /** * @brief Initialization function for the Q31 IIR lattice filter. * @param[in] *S points to an instance of the Q31 IIR lattice structure. * @param[in] numStages number of stages in the filter. @@ -4154,16 +4049,15 @@ void arm_rfft_fast_f32( * @return none. */ - void arm_iir_lattice_init_q31( - arm_iir_lattice_instance_q31 * S, - uint16_t numStages, - q31_t * pkCoeffs, - q31_t * pvCoeffs, - q31_t * pState, - uint32_t blockSize); + void arm_iir_lattice_init_q31( + arm_iir_lattice_instance_q31 *S, + uint16_t numStages, + q31_t *pkCoeffs, + q31_t *pvCoeffs, + q31_t *pState, + uint32_t blockSize); - - /** + /** * @brief Processing function for the Q15 IIR lattice filter. * @param[in] *S points to an instance of the Q15 IIR lattice structure. * @param[in] *pSrc points to the block of input data. @@ -4172,14 +4066,13 @@ void arm_rfft_fast_f32( * @return none. */ - void arm_iir_lattice_q15( - const arm_iir_lattice_instance_q15 * S, - q15_t * pSrc, - q15_t * pDst, - uint32_t blockSize); + void arm_iir_lattice_q15( + const arm_iir_lattice_instance_q15 *S, + q15_t *pSrc, + q15_t *pDst, + uint32_t blockSize); - -/** + /** * @brief Initialization function for the Q15 IIR lattice filter. * @param[in] *S points to an instance of the fixed-point Q15 IIR lattice structure. * @param[in] numStages number of stages in the filter. @@ -4190,27 +4083,27 @@ void arm_rfft_fast_f32( * @return none. */ - void arm_iir_lattice_init_q15( - arm_iir_lattice_instance_q15 * S, - uint16_t numStages, - q15_t * pkCoeffs, - q15_t * pvCoeffs, - q15_t * pState, - uint32_t blockSize); + void arm_iir_lattice_init_q15( + arm_iir_lattice_instance_q15 *S, + uint16_t numStages, + q15_t *pkCoeffs, + q15_t *pvCoeffs, + q15_t *pState, + uint32_t blockSize); - /** + /** * @brief Instance structure for the floating-point LMS filter. */ - typedef struct - { - uint16_t numTaps; /**< number of coefficients in the filter. */ - float32_t *pState; /**< points to the state variable array. The array is of length numTaps+blockSize-1. */ - float32_t *pCoeffs; /**< points to the coefficient array. The array is of length numTaps. */ - float32_t mu; /**< step size that controls filter coefficient updates. */ - } arm_lms_instance_f32; + typedef struct + { + uint16_t numTaps; /**< number of coefficients in the filter. */ + float32_t *pState; /**< points to the state variable array. The array is of length numTaps+blockSize-1. */ + float32_t *pCoeffs; /**< points to the coefficient array. The array is of length numTaps. */ + float32_t mu; /**< step size that controls filter coefficient updates. */ + } arm_lms_instance_f32; - /** + /** * @brief Processing function for floating-point LMS filter. * @param[in] *S points to an instance of the floating-point LMS filter structure. * @param[in] *pSrc points to the block of input data. @@ -4221,15 +4114,15 @@ void arm_rfft_fast_f32( * @return none. */ - void arm_lms_f32( - const arm_lms_instance_f32 * S, - float32_t * pSrc, - float32_t * pRef, - float32_t * pOut, - float32_t * pErr, - uint32_t blockSize); + void arm_lms_f32( + const arm_lms_instance_f32 *S, + float32_t *pSrc, + float32_t *pRef, + float32_t *pOut, + float32_t *pErr, + uint32_t blockSize); - /** + /** * @brief Initialization function for floating-point LMS filter. * @param[in] *S points to an instance of the floating-point LMS filter structure. * @param[in] numTaps number of filter coefficients. @@ -4240,29 +4133,28 @@ void arm_rfft_fast_f32( * @return none. */ - void arm_lms_init_f32( - arm_lms_instance_f32 * S, - uint16_t numTaps, - float32_t * pCoeffs, - float32_t * pState, - float32_t mu, - uint32_t blockSize); + void arm_lms_init_f32( + arm_lms_instance_f32 *S, + uint16_t numTaps, + float32_t *pCoeffs, + float32_t *pState, + float32_t mu, + uint32_t blockSize); - /** + /** * @brief Instance structure for the Q15 LMS filter. */ - typedef struct - { - uint16_t numTaps; /**< number of coefficients in the filter. */ - q15_t *pState; /**< points to the state variable array. The array is of length numTaps+blockSize-1. */ - q15_t *pCoeffs; /**< points to the coefficient array. The array is of length numTaps. */ - q15_t mu; /**< step size that controls filter coefficient updates. */ - uint32_t postShift; /**< bit shift applied to coefficients. */ - } arm_lms_instance_q15; - + typedef struct + { + uint16_t numTaps; /**< number of coefficients in the filter. */ + q15_t *pState; /**< points to the state variable array. The array is of length numTaps+blockSize-1. */ + q15_t *pCoeffs; /**< points to the coefficient array. The array is of length numTaps. */ + q15_t mu; /**< step size that controls filter coefficient updates. */ + uint32_t postShift; /**< bit shift applied to coefficients. */ + } arm_lms_instance_q15; - /** + /** * @brief Initialization function for the Q15 LMS filter. * @param[in] *S points to an instance of the Q15 LMS filter structure. * @param[in] numTaps number of filter coefficients. @@ -4274,16 +4166,16 @@ void arm_rfft_fast_f32( * @return none. */ - void arm_lms_init_q15( - arm_lms_instance_q15 * S, - uint16_t numTaps, - q15_t * pCoeffs, - q15_t * pState, - q15_t mu, - uint32_t blockSize, - uint32_t postShift); + void arm_lms_init_q15( + arm_lms_instance_q15 *S, + uint16_t numTaps, + q15_t *pCoeffs, + q15_t *pState, + q15_t mu, + uint32_t blockSize, + uint32_t postShift); - /** + /** * @brief Processing function for Q15 LMS filter. * @param[in] *S points to an instance of the Q15 LMS filter structure. * @param[in] *pSrc points to the block of input data. @@ -4294,30 +4186,29 @@ void arm_rfft_fast_f32( * @return none. */ - void arm_lms_q15( - const arm_lms_instance_q15 * S, - q15_t * pSrc, - q15_t * pRef, - q15_t * pOut, - q15_t * pErr, - uint32_t blockSize); + void arm_lms_q15( + const arm_lms_instance_q15 *S, + q15_t *pSrc, + q15_t *pRef, + q15_t *pOut, + q15_t *pErr, + uint32_t blockSize); - - /** + /** * @brief Instance structure for the Q31 LMS filter. */ - typedef struct - { - uint16_t numTaps; /**< number of coefficients in the filter. */ - q31_t *pState; /**< points to the state variable array. The array is of length numTaps+blockSize-1. */ - q31_t *pCoeffs; /**< points to the coefficient array. The array is of length numTaps. */ - q31_t mu; /**< step size that controls filter coefficient updates. */ - uint32_t postShift; /**< bit shift applied to coefficients. */ + typedef struct + { + uint16_t numTaps; /**< number of coefficients in the filter. */ + q31_t *pState; /**< points to the state variable array. The array is of length numTaps+blockSize-1. */ + q31_t *pCoeffs; /**< points to the coefficient array. The array is of length numTaps. */ + q31_t mu; /**< step size that controls filter coefficient updates. */ + uint32_t postShift; /**< bit shift applied to coefficients. */ - } arm_lms_instance_q31; + } arm_lms_instance_q31; - /** + /** * @brief Processing function for Q31 LMS filter. * @param[in] *S points to an instance of the Q15 LMS filter structure. * @param[in] *pSrc points to the block of input data. @@ -4328,15 +4219,15 @@ void arm_rfft_fast_f32( * @return none. */ - void arm_lms_q31( - const arm_lms_instance_q31 * S, - q31_t * pSrc, - q31_t * pRef, - q31_t * pOut, - q31_t * pErr, - uint32_t blockSize); + void arm_lms_q31( + const arm_lms_instance_q31 *S, + q31_t *pSrc, + q31_t *pRef, + q31_t *pOut, + q31_t *pErr, + uint32_t blockSize); - /** + /** * @brief Initialization function for Q31 LMS filter. * @param[in] *S points to an instance of the Q31 LMS filter structure. * @param[in] numTaps number of filter coefficients. @@ -4348,30 +4239,30 @@ void arm_rfft_fast_f32( * @return none. */ - void arm_lms_init_q31( - arm_lms_instance_q31 * S, - uint16_t numTaps, - q31_t * pCoeffs, - q31_t * pState, - q31_t mu, - uint32_t blockSize, - uint32_t postShift); + void arm_lms_init_q31( + arm_lms_instance_q31 *S, + uint16_t numTaps, + q31_t *pCoeffs, + q31_t *pState, + q31_t mu, + uint32_t blockSize, + uint32_t postShift); - /** + /** * @brief Instance structure for the floating-point normalized LMS filter. */ - typedef struct - { - uint16_t numTaps; /**< number of coefficients in the filter. */ - float32_t *pState; /**< points to the state variable array. The array is of length numTaps+blockSize-1. */ - float32_t *pCoeffs; /**< points to the coefficient array. The array is of length numTaps. */ - float32_t mu; /**< step size that control filter coefficient updates. */ - float32_t energy; /**< saves previous frame energy. */ - float32_t x0; /**< saves previous input sample. */ - } arm_lms_norm_instance_f32; + typedef struct + { + uint16_t numTaps; /**< number of coefficients in the filter. */ + float32_t *pState; /**< points to the state variable array. The array is of length numTaps+blockSize-1. */ + float32_t *pCoeffs; /**< points to the coefficient array. The array is of length numTaps. */ + float32_t mu; /**< step size that control filter coefficient updates. */ + float32_t energy; /**< saves previous frame energy. */ + float32_t x0; /**< saves previous input sample. */ + } arm_lms_norm_instance_f32; - /** + /** * @brief Processing function for floating-point normalized LMS filter. * @param[in] *S points to an instance of the floating-point normalized LMS filter structure. * @param[in] *pSrc points to the block of input data. @@ -4382,15 +4273,15 @@ void arm_rfft_fast_f32( * @return none. */ - void arm_lms_norm_f32( - arm_lms_norm_instance_f32 * S, - float32_t * pSrc, - float32_t * pRef, - float32_t * pOut, - float32_t * pErr, - uint32_t blockSize); + void arm_lms_norm_f32( + arm_lms_norm_instance_f32 *S, + float32_t *pSrc, + float32_t *pRef, + float32_t *pOut, + float32_t *pErr, + uint32_t blockSize); - /** + /** * @brief Initialization function for floating-point normalized LMS filter. * @param[in] *S points to an instance of the floating-point LMS filter structure. * @param[in] numTaps number of filter coefficients. @@ -4401,31 +4292,30 @@ void arm_rfft_fast_f32( * @return none. */ - void arm_lms_norm_init_f32( - arm_lms_norm_instance_f32 * S, - uint16_t numTaps, - float32_t * pCoeffs, - float32_t * pState, - float32_t mu, - uint32_t blockSize); - + void arm_lms_norm_init_f32( + arm_lms_norm_instance_f32 *S, + uint16_t numTaps, + float32_t *pCoeffs, + float32_t *pState, + float32_t mu, + uint32_t blockSize); - /** + /** * @brief Instance structure for the Q31 normalized LMS filter. */ - typedef struct - { - uint16_t numTaps; /**< number of coefficients in the filter. */ - q31_t *pState; /**< points to the state variable array. The array is of length numTaps+blockSize-1. */ - q31_t *pCoeffs; /**< points to the coefficient array. The array is of length numTaps. */ - q31_t mu; /**< step size that controls filter coefficient updates. */ - uint8_t postShift; /**< bit shift applied to coefficients. */ - q31_t *recipTable; /**< points to the reciprocal initial value table. */ - q31_t energy; /**< saves previous frame energy. */ - q31_t x0; /**< saves previous input sample. */ - } arm_lms_norm_instance_q31; - - /** + typedef struct + { + uint16_t numTaps; /**< number of coefficients in the filter. */ + q31_t *pState; /**< points to the state variable array. The array is of length numTaps+blockSize-1. */ + q31_t *pCoeffs; /**< points to the coefficient array. The array is of length numTaps. */ + q31_t mu; /**< step size that controls filter coefficient updates. */ + uint8_t postShift; /**< bit shift applied to coefficients. */ + q31_t *recipTable; /**< points to the reciprocal initial value table. */ + q31_t energy; /**< saves previous frame energy. */ + q31_t x0; /**< saves previous input sample. */ + } arm_lms_norm_instance_q31; + + /** * @brief Processing function for Q31 normalized LMS filter. * @param[in] *S points to an instance of the Q31 normalized LMS filter structure. * @param[in] *pSrc points to the block of input data. @@ -4436,15 +4326,15 @@ void arm_rfft_fast_f32( * @return none. */ - void arm_lms_norm_q31( - arm_lms_norm_instance_q31 * S, - q31_t * pSrc, - q31_t * pRef, - q31_t * pOut, - q31_t * pErr, - uint32_t blockSize); + void arm_lms_norm_q31( + arm_lms_norm_instance_q31 *S, + q31_t *pSrc, + q31_t *pRef, + q31_t *pOut, + q31_t *pErr, + uint32_t blockSize); - /** + /** * @brief Initialization function for Q31 normalized LMS filter. * @param[in] *S points to an instance of the Q31 normalized LMS filter structure. * @param[in] numTaps number of filter coefficients. @@ -4456,32 +4346,32 @@ void arm_rfft_fast_f32( * @return none. */ - void arm_lms_norm_init_q31( - arm_lms_norm_instance_q31 * S, - uint16_t numTaps, - q31_t * pCoeffs, - q31_t * pState, - q31_t mu, - uint32_t blockSize, - uint8_t postShift); + void arm_lms_norm_init_q31( + arm_lms_norm_instance_q31 *S, + uint16_t numTaps, + q31_t *pCoeffs, + q31_t *pState, + q31_t mu, + uint32_t blockSize, + uint8_t postShift); - /** + /** * @brief Instance structure for the Q15 normalized LMS filter. */ - typedef struct - { - uint16_t numTaps; /**< Number of coefficients in the filter. */ - q15_t *pState; /**< points to the state variable array. The array is of length numTaps+blockSize-1. */ - q15_t *pCoeffs; /**< points to the coefficient array. The array is of length numTaps. */ - q15_t mu; /**< step size that controls filter coefficient updates. */ - uint8_t postShift; /**< bit shift applied to coefficients. */ - q15_t *recipTable; /**< Points to the reciprocal initial value table. */ - q15_t energy; /**< saves previous frame energy. */ - q15_t x0; /**< saves previous input sample. */ - } arm_lms_norm_instance_q15; + typedef struct + { + uint16_t numTaps; /**< Number of coefficients in the filter. */ + q15_t *pState; /**< points to the state variable array. The array is of length numTaps+blockSize-1. */ + q15_t *pCoeffs; /**< points to the coefficient array. The array is of length numTaps. */ + q15_t mu; /**< step size that controls filter coefficient updates. */ + uint8_t postShift; /**< bit shift applied to coefficients. */ + q15_t *recipTable; /**< Points to the reciprocal initial value table. */ + q15_t energy; /**< saves previous frame energy. */ + q15_t x0; /**< saves previous input sample. */ + } arm_lms_norm_instance_q15; - /** + /** * @brief Processing function for Q15 normalized LMS filter. * @param[in] *S points to an instance of the Q15 normalized LMS filter structure. * @param[in] *pSrc points to the block of input data. @@ -4492,16 +4382,15 @@ void arm_rfft_fast_f32( * @return none. */ - void arm_lms_norm_q15( - arm_lms_norm_instance_q15 * S, - q15_t * pSrc, - q15_t * pRef, - q15_t * pOut, - q15_t * pErr, - uint32_t blockSize); + void arm_lms_norm_q15( + arm_lms_norm_instance_q15 *S, + q15_t *pSrc, + q15_t *pRef, + q15_t *pOut, + q15_t *pErr, + uint32_t blockSize); - - /** + /** * @brief Initialization function for Q15 normalized LMS filter. * @param[in] *S points to an instance of the Q15 normalized LMS filter structure. * @param[in] numTaps number of filter coefficients. @@ -4513,16 +4402,16 @@ void arm_rfft_fast_f32( * @return none. */ - void arm_lms_norm_init_q15( - arm_lms_norm_instance_q15 * S, - uint16_t numTaps, - q15_t * pCoeffs, - q15_t * pState, - q15_t mu, - uint32_t blockSize, - uint8_t postShift); + void arm_lms_norm_init_q15( + arm_lms_norm_instance_q15 *S, + uint16_t numTaps, + q15_t *pCoeffs, + q15_t *pState, + q15_t mu, + uint32_t blockSize, + uint8_t postShift); - /** + /** * @brief Correlation of floating-point sequences. * @param[in] *pSrcA points to the first input sequence. * @param[in] srcALen length of the first input sequence. @@ -4532,15 +4421,14 @@ void arm_rfft_fast_f32( * @return none. */ - void arm_correlate_f32( - float32_t * pSrcA, - uint32_t srcALen, - float32_t * pSrcB, - uint32_t srcBLen, - float32_t * pDst); + void arm_correlate_f32( + float32_t *pSrcA, + uint32_t srcALen, + float32_t *pSrcB, + uint32_t srcBLen, + float32_t *pDst); - - /** + /** * @brief Correlation of Q15 sequences * @param[in] *pSrcA points to the first input sequence. * @param[in] srcALen length of the first input sequence. @@ -4550,16 +4438,15 @@ void arm_rfft_fast_f32( * @param[in] *pScratch points to scratch buffer of size max(srcALen, srcBLen) + 2*min(srcALen, srcBLen) - 2. * @return none. */ - void arm_correlate_opt_q15( - q15_t * pSrcA, - uint32_t srcALen, - q15_t * pSrcB, - uint32_t srcBLen, - q15_t * pDst, - q15_t * pScratch); - + void arm_correlate_opt_q15( + q15_t *pSrcA, + uint32_t srcALen, + q15_t *pSrcB, + uint32_t srcBLen, + q15_t *pDst, + q15_t *pScratch); - /** + /** * @brief Correlation of Q15 sequences. * @param[in] *pSrcA points to the first input sequence. * @param[in] srcALen length of the first input sequence. @@ -4569,14 +4456,14 @@ void arm_rfft_fast_f32( * @return none. */ - void arm_correlate_q15( - q15_t * pSrcA, - uint32_t srcALen, - q15_t * pSrcB, - uint32_t srcBLen, - q15_t * pDst); + void arm_correlate_q15( + q15_t *pSrcA, + uint32_t srcALen, + q15_t *pSrcB, + uint32_t srcBLen, + q15_t *pDst); - /** + /** * @brief Correlation of Q15 sequences (fast version) for Cortex-M3 and Cortex-M4. * @param[in] *pSrcA points to the first input sequence. * @param[in] srcALen length of the first input sequence. @@ -4586,16 +4473,14 @@ void arm_rfft_fast_f32( * @return none. */ - void arm_correlate_fast_q15( - q15_t * pSrcA, - uint32_t srcALen, - q15_t * pSrcB, - uint32_t srcBLen, - q15_t * pDst); - + void arm_correlate_fast_q15( + q15_t *pSrcA, + uint32_t srcALen, + q15_t *pSrcB, + uint32_t srcBLen, + q15_t *pDst); - - /** + /** * @brief Correlation of Q15 sequences (fast version) for Cortex-M3 and Cortex-M4. * @param[in] *pSrcA points to the first input sequence. * @param[in] srcALen length of the first input sequence. @@ -4606,15 +4491,15 @@ void arm_rfft_fast_f32( * @return none. */ - void arm_correlate_fast_opt_q15( - q15_t * pSrcA, - uint32_t srcALen, - q15_t * pSrcB, - uint32_t srcBLen, - q15_t * pDst, - q15_t * pScratch); + void arm_correlate_fast_opt_q15( + q15_t *pSrcA, + uint32_t srcALen, + q15_t *pSrcB, + uint32_t srcBLen, + q15_t *pDst, + q15_t *pScratch); - /** + /** * @brief Correlation of Q31 sequences. * @param[in] *pSrcA points to the first input sequence. * @param[in] srcALen length of the first input sequence. @@ -4624,14 +4509,14 @@ void arm_rfft_fast_f32( * @return none. */ - void arm_correlate_q31( - q31_t * pSrcA, - uint32_t srcALen, - q31_t * pSrcB, - uint32_t srcBLen, - q31_t * pDst); + void arm_correlate_q31( + q31_t *pSrcA, + uint32_t srcALen, + q31_t *pSrcB, + uint32_t srcBLen, + q31_t *pDst); - /** + /** * @brief Correlation of Q31 sequences (fast version) for Cortex-M3 and Cortex-M4 * @param[in] *pSrcA points to the first input sequence. * @param[in] srcALen length of the first input sequence. @@ -4641,16 +4526,14 @@ void arm_rfft_fast_f32( * @return none. */ - void arm_correlate_fast_q31( - q31_t * pSrcA, - uint32_t srcALen, - q31_t * pSrcB, - uint32_t srcBLen, - q31_t * pDst); + void arm_correlate_fast_q31( + q31_t *pSrcA, + uint32_t srcALen, + q31_t *pSrcB, + uint32_t srcBLen, + q31_t *pDst); - - - /** + /** * @brief Correlation of Q7 sequences. * @param[in] *pSrcA points to the first input sequence. * @param[in] srcALen length of the first input sequence. @@ -4662,17 +4545,16 @@ void arm_rfft_fast_f32( * @return none. */ - void arm_correlate_opt_q7( - q7_t * pSrcA, - uint32_t srcALen, - q7_t * pSrcB, - uint32_t srcBLen, - q7_t * pDst, - q15_t * pScratch1, - q15_t * pScratch2); + void arm_correlate_opt_q7( + q7_t *pSrcA, + uint32_t srcALen, + q7_t *pSrcB, + uint32_t srcBLen, + q7_t *pDst, + q15_t *pScratch1, + q15_t *pScratch2); - - /** + /** * @brief Correlation of Q7 sequences. * @param[in] *pSrcA points to the first input sequence. * @param[in] srcALen length of the first input sequence. @@ -4682,70 +4564,69 @@ void arm_rfft_fast_f32( * @return none. */ - void arm_correlate_q7( - q7_t * pSrcA, - uint32_t srcALen, - q7_t * pSrcB, - uint32_t srcBLen, - q7_t * pDst); - + void arm_correlate_q7( + q7_t *pSrcA, + uint32_t srcALen, + q7_t *pSrcB, + uint32_t srcBLen, + q7_t *pDst); - /** + /** * @brief Instance structure for the floating-point sparse FIR filter. */ - typedef struct - { - uint16_t numTaps; /**< number of coefficients in the filter. */ - uint16_t stateIndex; /**< state buffer index. Points to the oldest sample in the state buffer. */ - float32_t *pState; /**< points to the state buffer array. The array is of length maxDelay+blockSize-1. */ - float32_t *pCoeffs; /**< points to the coefficient array. The array is of length numTaps.*/ - uint16_t maxDelay; /**< maximum offset specified by the pTapDelay array. */ - int32_t *pTapDelay; /**< points to the array of delay values. The array is of length numTaps. */ - } arm_fir_sparse_instance_f32; - - /** + typedef struct + { + uint16_t numTaps; /**< number of coefficients in the filter. */ + uint16_t stateIndex; /**< state buffer index. Points to the oldest sample in the state buffer. */ + float32_t *pState; /**< points to the state buffer array. The array is of length maxDelay+blockSize-1. */ + float32_t *pCoeffs; /**< points to the coefficient array. The array is of length numTaps.*/ + uint16_t maxDelay; /**< maximum offset specified by the pTapDelay array. */ + int32_t *pTapDelay; /**< points to the array of delay values. The array is of length numTaps. */ + } arm_fir_sparse_instance_f32; + + /** * @brief Instance structure for the Q31 sparse FIR filter. */ - typedef struct - { - uint16_t numTaps; /**< number of coefficients in the filter. */ - uint16_t stateIndex; /**< state buffer index. Points to the oldest sample in the state buffer. */ - q31_t *pState; /**< points to the state buffer array. The array is of length maxDelay+blockSize-1. */ - q31_t *pCoeffs; /**< points to the coefficient array. The array is of length numTaps.*/ - uint16_t maxDelay; /**< maximum offset specified by the pTapDelay array. */ - int32_t *pTapDelay; /**< points to the array of delay values. The array is of length numTaps. */ - } arm_fir_sparse_instance_q31; + typedef struct + { + uint16_t numTaps; /**< number of coefficients in the filter. */ + uint16_t stateIndex; /**< state buffer index. Points to the oldest sample in the state buffer. */ + q31_t *pState; /**< points to the state buffer array. The array is of length maxDelay+blockSize-1. */ + q31_t *pCoeffs; /**< points to the coefficient array. The array is of length numTaps.*/ + uint16_t maxDelay; /**< maximum offset specified by the pTapDelay array. */ + int32_t *pTapDelay; /**< points to the array of delay values. The array is of length numTaps. */ + } arm_fir_sparse_instance_q31; - /** + /** * @brief Instance structure for the Q15 sparse FIR filter. */ - typedef struct - { - uint16_t numTaps; /**< number of coefficients in the filter. */ - uint16_t stateIndex; /**< state buffer index. Points to the oldest sample in the state buffer. */ - q15_t *pState; /**< points to the state buffer array. The array is of length maxDelay+blockSize-1. */ - q15_t *pCoeffs; /**< points to the coefficient array. The array is of length numTaps.*/ - uint16_t maxDelay; /**< maximum offset specified by the pTapDelay array. */ - int32_t *pTapDelay; /**< points to the array of delay values. The array is of length numTaps. */ - } arm_fir_sparse_instance_q15; + typedef struct + { + uint16_t numTaps; /**< number of coefficients in the filter. */ + uint16_t stateIndex; /**< state buffer index. Points to the oldest sample in the state buffer. */ + q15_t *pState; /**< points to the state buffer array. The array is of length maxDelay+blockSize-1. */ + q15_t *pCoeffs; /**< points to the coefficient array. The array is of length numTaps.*/ + uint16_t maxDelay; /**< maximum offset specified by the pTapDelay array. */ + int32_t *pTapDelay; /**< points to the array of delay values. The array is of length numTaps. */ + } arm_fir_sparse_instance_q15; - /** + /** * @brief Instance structure for the Q7 sparse FIR filter. */ - typedef struct - { - uint16_t numTaps; /**< number of coefficients in the filter. */ - uint16_t stateIndex; /**< state buffer index. Points to the oldest sample in the state buffer. */ - q7_t *pState; /**< points to the state buffer array. The array is of length maxDelay+blockSize-1. */ - q7_t *pCoeffs; /**< points to the coefficient array. The array is of length numTaps.*/ - uint16_t maxDelay; /**< maximum offset specified by the pTapDelay array. */ - int32_t *pTapDelay; /**< points to the array of delay values. The array is of length numTaps. */ - } arm_fir_sparse_instance_q7; + typedef struct + { + uint16_t numTaps; /**< number of coefficients in the filter. */ + uint16_t stateIndex; /**< state buffer index. Points to the oldest sample in the state buffer. */ + q7_t *pState; /**< points to the state buffer array. The array is of length maxDelay+blockSize-1. */ + q7_t *pCoeffs; /**< points to the coefficient array. The array is of length numTaps.*/ + uint16_t maxDelay; /**< maximum offset specified by the pTapDelay array. */ + int32_t *pTapDelay; /**< points to the array of delay values. The array is of length numTaps. */ + } arm_fir_sparse_instance_q7; - /** + /** * @brief Processing function for the floating-point sparse FIR filter. * @param[in] *S points to an instance of the floating-point sparse FIR structure. * @param[in] *pSrc points to the block of input data. @@ -4755,14 +4636,14 @@ void arm_rfft_fast_f32( * @return none. */ - void arm_fir_sparse_f32( - arm_fir_sparse_instance_f32 * S, - float32_t * pSrc, - float32_t * pDst, - float32_t * pScratchIn, - uint32_t blockSize); + void arm_fir_sparse_f32( + arm_fir_sparse_instance_f32 *S, + float32_t *pSrc, + float32_t *pDst, + float32_t *pScratchIn, + uint32_t blockSize); - /** + /** * @brief Initialization function for the floating-point sparse FIR filter. * @param[in,out] *S points to an instance of the floating-point sparse FIR structure. * @param[in] numTaps number of nonzero coefficients in the filter. @@ -4774,16 +4655,16 @@ void arm_rfft_fast_f32( * @return none */ - void arm_fir_sparse_init_f32( - arm_fir_sparse_instance_f32 * S, - uint16_t numTaps, - float32_t * pCoeffs, - float32_t * pState, - int32_t * pTapDelay, - uint16_t maxDelay, - uint32_t blockSize); + void arm_fir_sparse_init_f32( + arm_fir_sparse_instance_f32 *S, + uint16_t numTaps, + float32_t *pCoeffs, + float32_t *pState, + int32_t *pTapDelay, + uint16_t maxDelay, + uint32_t blockSize); - /** + /** * @brief Processing function for the Q31 sparse FIR filter. * @param[in] *S points to an instance of the Q31 sparse FIR structure. * @param[in] *pSrc points to the block of input data. @@ -4793,14 +4674,14 @@ void arm_rfft_fast_f32( * @return none. */ - void arm_fir_sparse_q31( - arm_fir_sparse_instance_q31 * S, - q31_t * pSrc, - q31_t * pDst, - q31_t * pScratchIn, - uint32_t blockSize); + void arm_fir_sparse_q31( + arm_fir_sparse_instance_q31 *S, + q31_t *pSrc, + q31_t *pDst, + q31_t *pScratchIn, + uint32_t blockSize); - /** + /** * @brief Initialization function for the Q31 sparse FIR filter. * @param[in,out] *S points to an instance of the Q31 sparse FIR structure. * @param[in] numTaps number of nonzero coefficients in the filter. @@ -4812,16 +4693,16 @@ void arm_rfft_fast_f32( * @return none */ - void arm_fir_sparse_init_q31( - arm_fir_sparse_instance_q31 * S, - uint16_t numTaps, - q31_t * pCoeffs, - q31_t * pState, - int32_t * pTapDelay, - uint16_t maxDelay, - uint32_t blockSize); + void arm_fir_sparse_init_q31( + arm_fir_sparse_instance_q31 *S, + uint16_t numTaps, + q31_t *pCoeffs, + q31_t *pState, + int32_t *pTapDelay, + uint16_t maxDelay, + uint32_t blockSize); - /** + /** * @brief Processing function for the Q15 sparse FIR filter. * @param[in] *S points to an instance of the Q15 sparse FIR structure. * @param[in] *pSrc points to the block of input data. @@ -4832,16 +4713,15 @@ void arm_rfft_fast_f32( * @return none. */ - void arm_fir_sparse_q15( - arm_fir_sparse_instance_q15 * S, - q15_t * pSrc, - q15_t * pDst, - q15_t * pScratchIn, - q31_t * pScratchOut, - uint32_t blockSize); - + void arm_fir_sparse_q15( + arm_fir_sparse_instance_q15 *S, + q15_t *pSrc, + q15_t *pDst, + q15_t *pScratchIn, + q31_t *pScratchOut, + uint32_t blockSize); - /** + /** * @brief Initialization function for the Q15 sparse FIR filter. * @param[in,out] *S points to an instance of the Q15 sparse FIR structure. * @param[in] numTaps number of nonzero coefficients in the filter. @@ -4853,16 +4733,16 @@ void arm_rfft_fast_f32( * @return none */ - void arm_fir_sparse_init_q15( - arm_fir_sparse_instance_q15 * S, - uint16_t numTaps, - q15_t * pCoeffs, - q15_t * pState, - int32_t * pTapDelay, - uint16_t maxDelay, - uint32_t blockSize); + void arm_fir_sparse_init_q15( + arm_fir_sparse_instance_q15 *S, + uint16_t numTaps, + q15_t *pCoeffs, + q15_t *pState, + int32_t *pTapDelay, + uint16_t maxDelay, + uint32_t blockSize); - /** + /** * @brief Processing function for the Q7 sparse FIR filter. * @param[in] *S points to an instance of the Q7 sparse FIR structure. * @param[in] *pSrc points to the block of input data. @@ -4873,15 +4753,15 @@ void arm_rfft_fast_f32( * @return none. */ - void arm_fir_sparse_q7( - arm_fir_sparse_instance_q7 * S, - q7_t * pSrc, - q7_t * pDst, - q7_t * pScratchIn, - q31_t * pScratchOut, - uint32_t blockSize); + void arm_fir_sparse_q7( + arm_fir_sparse_instance_q7 *S, + q7_t *pSrc, + q7_t *pDst, + q7_t *pScratchIn, + q31_t *pScratchOut, + uint32_t blockSize); - /** + /** * @brief Initialization function for the Q7 sparse FIR filter. * @param[in,out] *S points to an instance of the Q7 sparse FIR structure. * @param[in] numTaps number of nonzero coefficients in the filter. @@ -4893,17 +4773,16 @@ void arm_rfft_fast_f32( * @return none */ - void arm_fir_sparse_init_q7( - arm_fir_sparse_instance_q7 * S, - uint16_t numTaps, - q7_t * pCoeffs, - q7_t * pState, - int32_t * pTapDelay, - uint16_t maxDelay, - uint32_t blockSize); - + void arm_fir_sparse_init_q7( + arm_fir_sparse_instance_q7 *S, + uint16_t numTaps, + q7_t *pCoeffs, + q7_t *pState, + int32_t *pTapDelay, + uint16_t maxDelay, + uint32_t blockSize); - /* + /* * @brief Floating-point sin_cos function. * @param[in] theta input value in degrees * @param[out] *pSinVal points to the processed sine output. @@ -4911,12 +4790,12 @@ void arm_rfft_fast_f32( * @return none. */ - void arm_sin_cos_f32( - float32_t theta, - float32_t * pSinVal, - float32_t * pCcosVal); + void arm_sin_cos_f32( + float32_t theta, + float32_t *pSinVal, + float32_t *pCcosVal); - /* + /* * @brief Q31 sin_cos function. * @param[in] theta scaled input value in degrees * @param[out] *pSinVal points to the processed sine output. @@ -4924,13 +4803,12 @@ void arm_rfft_fast_f32( * @return none. */ - void arm_sin_cos_q31( - q31_t theta, - q31_t * pSinVal, - q31_t * pCosVal); + void arm_sin_cos_q31( + q31_t theta, + q31_t *pSinVal, + q31_t *pCosVal); - - /** + /** * @brief Floating-point complex conjugate. * @param[in] *pSrc points to the input vector * @param[out] *pDst points to the output vector @@ -4938,12 +4816,12 @@ void arm_rfft_fast_f32( * @return none. */ - void arm_cmplx_conj_f32( - float32_t * pSrc, - float32_t * pDst, - uint32_t numSamples); + void arm_cmplx_conj_f32( + float32_t *pSrc, + float32_t *pDst, + uint32_t numSamples); - /** + /** * @brief Q31 complex conjugate. * @param[in] *pSrc points to the input vector * @param[out] *pDst points to the output vector @@ -4951,12 +4829,12 @@ void arm_rfft_fast_f32( * @return none. */ - void arm_cmplx_conj_q31( - q31_t * pSrc, - q31_t * pDst, - uint32_t numSamples); + void arm_cmplx_conj_q31( + q31_t *pSrc, + q31_t *pDst, + uint32_t numSamples); - /** + /** * @brief Q15 complex conjugate. * @param[in] *pSrc points to the input vector * @param[out] *pDst points to the output vector @@ -4964,14 +4842,12 @@ void arm_rfft_fast_f32( * @return none. */ - void arm_cmplx_conj_q15( - q15_t * pSrc, - q15_t * pDst, - uint32_t numSamples); - - + void arm_cmplx_conj_q15( + q15_t *pSrc, + q15_t *pDst, + uint32_t numSamples); - /** + /** * @brief Floating-point complex magnitude squared * @param[in] *pSrc points to the complex input vector * @param[out] *pDst points to the real output vector @@ -4979,12 +4855,12 @@ void arm_rfft_fast_f32( * @return none. */ - void arm_cmplx_mag_squared_f32( - float32_t * pSrc, - float32_t * pDst, - uint32_t numSamples); + void arm_cmplx_mag_squared_f32( + float32_t *pSrc, + float32_t *pDst, + uint32_t numSamples); - /** + /** * @brief Q31 complex magnitude squared * @param[in] *pSrc points to the complex input vector * @param[out] *pDst points to the real output vector @@ -4992,12 +4868,12 @@ void arm_rfft_fast_f32( * @return none. */ - void arm_cmplx_mag_squared_q31( - q31_t * pSrc, - q31_t * pDst, - uint32_t numSamples); + void arm_cmplx_mag_squared_q31( + q31_t *pSrc, + q31_t *pDst, + uint32_t numSamples); - /** + /** * @brief Q15 complex magnitude squared * @param[in] *pSrc points to the complex input vector * @param[out] *pDst points to the real output vector @@ -5005,17 +4881,16 @@ void arm_rfft_fast_f32( * @return none. */ - void arm_cmplx_mag_squared_q15( - q15_t * pSrc, - q15_t * pDst, - uint32_t numSamples); + void arm_cmplx_mag_squared_q15( + q15_t *pSrc, + q15_t *pDst, + uint32_t numSamples); - - /** + /** * @ingroup groupController */ - /** + /** * @defgroup PID PID Motor Control * * A Proportional Integral Derivative (PID) controller is a generic feedback control @@ -5072,40 +4947,38 @@ void arm_rfft_fast_f32( * Refer to the function specific documentation below for usage guidelines. */ - /** + /** * @addtogroup PID * @{ */ - /** + /** * @brief Process function for the floating-point PID Control. * @param[in,out] *S is an instance of the floating-point PID Control structure * @param[in] in input sample to process * @return out processed output sample. */ + static __INLINE float32_t arm_pid_f32( + arm_pid_instance_f32 *S, + float32_t in) + { + float32_t out; - static __INLINE float32_t arm_pid_f32( - arm_pid_instance_f32 * S, - float32_t in) - { - float32_t out; - - /* y[n] = y[n-1] + A0 * x[n] + A1 * x[n-1] + A2 * x[n-2] */ - out = (S->A0 * in) + - (S->A1 * S->state[0]) + (S->A2 * S->state[1]) + (S->state[2]); - - /* Update state */ - S->state[1] = S->state[0]; - S->state[0] = in; - S->state[2] = out; + /* y[n] = y[n-1] + A0 * x[n] + A1 * x[n-1] + A2 * x[n-2] */ + out = (S->A0 * in) + + (S->A1 * S->state[0]) + (S->A2 * S->state[1]) + (S->state[2]); - /* return to application */ - return (out); + /* Update state */ + S->state[1] = S->state[0]; + S->state[0] = in; + S->state[2] = out; - } + /* return to application */ + return (out); + } - /** + /** * @brief Process function for the Q31 PID Control. * @param[in,out] *S points to an instance of the Q31 PID Control structure * @param[in] in input sample to process @@ -5120,39 +4993,38 @@ void arm_rfft_fast_f32( * After all multiply-accumulates are performed, the 2.62 accumulator is truncated to 1.32 format and then saturated to 1.31 format. */ - static __INLINE q31_t arm_pid_q31( - arm_pid_instance_q31 * S, - q31_t in) - { - q63_t acc; - q31_t out; - - /* acc = A0 * x[n] */ - acc = (q63_t) S->A0 * in; + static __INLINE q31_t arm_pid_q31( + arm_pid_instance_q31 *S, + q31_t in) + { + q63_t acc; + q31_t out; - /* acc += A1 * x[n-1] */ - acc += (q63_t) S->A1 * S->state[0]; + /* acc = A0 * x[n] */ + acc = (q63_t)S->A0 * in; - /* acc += A2 * x[n-2] */ - acc += (q63_t) S->A2 * S->state[1]; + /* acc += A1 * x[n-1] */ + acc += (q63_t)S->A1 * S->state[0]; - /* convert output to 1.31 format to add y[n-1] */ - out = (q31_t) (acc >> 31u); + /* acc += A2 * x[n-2] */ + acc += (q63_t)S->A2 * S->state[1]; - /* out += y[n-1] */ - out += S->state[2]; + /* convert output to 1.31 format to add y[n-1] */ + out = (q31_t)(acc >> 31u); - /* Update state */ - S->state[1] = S->state[0]; - S->state[0] = in; - S->state[2] = out; + /* out += y[n-1] */ + out += S->state[2]; - /* return to application */ - return (out); + /* Update state */ + S->state[1] = S->state[0]; + S->state[0] = in; + S->state[2] = out; - } + /* return to application */ + return (out); + } - /** + /** * @brief Process function for the Q15 PID Control. * @param[in,out] *S points to an instance of the Q15 PID Control structure * @param[in] in input sample to process @@ -5168,57 +5040,55 @@ void arm_rfft_fast_f32( * Lastly, the accumulator is saturated to yield a result in 1.15 format. */ - static __INLINE q15_t arm_pid_q15( - arm_pid_instance_q15 * S, - q15_t in) - { - q63_t acc; - q15_t out; + static __INLINE q15_t arm_pid_q15( + arm_pid_instance_q15 *S, + q15_t in) + { + q63_t acc; + q15_t out; #ifndef ARM_MATH_CM0_FAMILY - __SIMD32_TYPE *vstate; + __SIMD32_TYPE *vstate; - /* Implementation of PID controller */ + /* Implementation of PID controller */ - /* acc = A0 * x[n] */ - acc = (q31_t) __SMUAD(S->A0, in); + /* acc = A0 * x[n] */ + acc = (q31_t)__SMUAD(S->A0, in); - /* acc += A1 * x[n-1] + A2 * x[n-2] */ - vstate = __SIMD32_CONST(S->state); - acc = __SMLALD(S->A1, (q31_t) *vstate, acc); + /* acc += A1 * x[n-1] + A2 * x[n-2] */ + vstate = __SIMD32_CONST(S->state); + acc = __SMLALD(S->A1, (q31_t)*vstate, acc); #else /* acc = A0 * x[n] */ - acc = ((q31_t) S->A0) * in; + acc = ((q31_t)S->A0) * in; /* acc += A1 * x[n-1] + A2 * x[n-2] */ - acc += (q31_t) S->A1 * S->state[0]; - acc += (q31_t) S->A2 * S->state[1]; + acc += (q31_t)S->A1 * S->state[0]; + acc += (q31_t)S->A2 * S->state[1]; #endif - /* acc += y[n-1] */ - acc += (q31_t) S->state[2] << 15; - - /* saturate the output */ - out = (q15_t) (__SSAT((acc >> 15), 16)); + /* acc += y[n-1] */ + acc += (q31_t)S->state[2] << 15; - /* Update state */ - S->state[1] = S->state[0]; - S->state[0] = in; - S->state[2] = out; + /* saturate the output */ + out = (q15_t)(__SSAT((acc >> 15), 16)); - /* return to application */ - return (out); + /* Update state */ + S->state[1] = S->state[0]; + S->state[0] = in; + S->state[2] = out; - } + /* return to application */ + return (out); + } - /** + /** * @} end of PID group */ - - /** + /** * @brief Floating-point matrix inverse. * @param[in] *src points to the instance of the input floating-point matrix structure. * @param[out] *dst points to the instance of the output floating-point matrix structure. @@ -5226,12 +5096,11 @@ void arm_rfft_fast_f32( * If the input matrix is singular (does not have an inverse), then the algorithm terminates and returns error status ARM_MATH_SINGULAR. */ - arm_status arm_mat_inverse_f32( - const arm_matrix_instance_f32 * src, - arm_matrix_instance_f32 * dst); - + arm_status arm_mat_inverse_f32( + const arm_matrix_instance_f32 *src, + arm_matrix_instance_f32 *dst); - /** + /** * @brief Floating-point matrix inverse. * @param[in] *src points to the instance of the input floating-point matrix structure. * @param[out] *dst points to the instance of the output floating-point matrix structure. @@ -5239,18 +5108,15 @@ void arm_rfft_fast_f32( * If the input matrix is singular (does not have an inverse), then the algorithm terminates and returns error status ARM_MATH_SINGULAR. */ - arm_status arm_mat_inverse_f64( - const arm_matrix_instance_f64 * src, - arm_matrix_instance_f64 * dst); + arm_status arm_mat_inverse_f64( + const arm_matrix_instance_f64 *src, + arm_matrix_instance_f64 *dst); - - - /** + /** * @ingroup groupController */ - - /** + /** * @defgroup clarke Vector Clarke Transform * Forward Clarke transform converts the instantaneous stator phases into a two-coordinate time invariant vector. * Generally the Clarke transform uses three-phase currents Ia, Ib and Ic to calculate currents @@ -5272,12 +5138,12 @@ void arm_rfft_fast_f32( * Refer to the function specific documentation below for usage guidelines. */ - /** + /** * @addtogroup clarke * @{ */ - /** + /** * * @brief Floating-point Clarke transform * @param[in] Ia input three-phase coordinate a @@ -5287,22 +5153,21 @@ void arm_rfft_fast_f32( * @return none. */ - static __INLINE void arm_clarke_f32( - float32_t Ia, - float32_t Ib, - float32_t * pIalpha, - float32_t * pIbeta) - { - /* Calculate pIalpha using the equation, pIalpha = Ia */ - *pIalpha = Ia; - - /* Calculate pIbeta using the equation, pIbeta = (1/sqrt(3)) * Ia + (2/sqrt(3)) * Ib */ - *pIbeta = - ((float32_t) 0.57735026919 * Ia + (float32_t) 1.15470053838 * Ib); + static __INLINE void arm_clarke_f32( + float32_t Ia, + float32_t Ib, + float32_t *pIalpha, + float32_t *pIbeta) + { + /* Calculate pIalpha using the equation, pIalpha = Ia */ + *pIalpha = Ia; - } + /* Calculate pIbeta using the equation, pIbeta = (1/sqrt(3)) * Ia + (2/sqrt(3)) * Ib */ + *pIbeta = + ((float32_t)0.57735026919 * Ia + (float32_t)1.15470053838 * Ib); + } - /** + /** * @brief Clarke transform for Q31 version * @param[in] Ia input three-phase coordinate a * @param[in] Ib input three-phase coordinate b @@ -5317,51 +5182,48 @@ void arm_rfft_fast_f32( * There is saturation on the addition, hence there is no risk of overflow. */ - static __INLINE void arm_clarke_q31( - q31_t Ia, - q31_t Ib, - q31_t * pIalpha, - q31_t * pIbeta) - { - q31_t product1, product2; /* Temporary variables used to store intermediate results */ + static __INLINE void arm_clarke_q31( + q31_t Ia, + q31_t Ib, + q31_t *pIalpha, + q31_t *pIbeta) + { + q31_t product1, product2; /* Temporary variables used to store intermediate results */ - /* Calculating pIalpha from Ia by equation pIalpha = Ia */ - *pIalpha = Ia; + /* Calculating pIalpha from Ia by equation pIalpha = Ia */ + *pIalpha = Ia; - /* Intermediate product is calculated by (1/(sqrt(3)) * Ia) */ - product1 = (q31_t) (((q63_t) Ia * 0x24F34E8B) >> 30); + /* Intermediate product is calculated by (1/(sqrt(3)) * Ia) */ + product1 = (q31_t)(((q63_t)Ia * 0x24F34E8B) >> 30); - /* Intermediate product is calculated by (2/sqrt(3) * Ib) */ - product2 = (q31_t) (((q63_t) Ib * 0x49E69D16) >> 30); + /* Intermediate product is calculated by (2/sqrt(3) * Ib) */ + product2 = (q31_t)(((q63_t)Ib * 0x49E69D16) >> 30); - /* pIbeta is calculated by adding the intermediate products */ - *pIbeta = __QADD(product1, product2); - } + /* pIbeta is calculated by adding the intermediate products */ + *pIbeta = __QADD(product1, product2); + } - /** + /** * @} end of clarke group */ - /** + /** * @brief Converts the elements of the Q7 vector to Q31 vector. * @param[in] *pSrc input pointer * @param[out] *pDst output pointer * @param[in] blockSize number of samples to process * @return none. */ - void arm_q7_to_q31( - q7_t * pSrc, - q31_t * pDst, - uint32_t blockSize); - + void arm_q7_to_q31( + q7_t *pSrc, + q31_t *pDst, + uint32_t blockSize); - - - /** + /** * @ingroup groupController */ - /** + /** * @defgroup inv_clarke Vector Inverse Clarke Transform * Inverse Clarke transform converts the two-coordinate time invariant vector into instantaneous stator phases. * @@ -5377,12 +5239,12 @@ void arm_rfft_fast_f32( * Refer to the function specific documentation below for usage guidelines. */ - /** + /** * @addtogroup inv_clarke * @{ */ - /** + /** * @brief Floating-point Inverse Clarke transform * @param[in] Ialpha input two-phase orthogonal vector axis alpha * @param[in] Ibeta input two-phase orthogonal vector axis beta @@ -5391,22 +5253,20 @@ void arm_rfft_fast_f32( * @return none. */ + static __INLINE void arm_inv_clarke_f32( + float32_t Ialpha, + float32_t Ibeta, + float32_t *pIa, + float32_t *pIb) + { + /* Calculating pIa from Ialpha by equation pIa = Ialpha */ + *pIa = Ialpha; - static __INLINE void arm_inv_clarke_f32( - float32_t Ialpha, - float32_t Ibeta, - float32_t * pIa, - float32_t * pIb) - { - /* Calculating pIa from Ialpha by equation pIa = Ialpha */ - *pIa = Ialpha; - - /* Calculating pIb from Ialpha and Ibeta by equation pIb = -(1/2) * Ialpha + (sqrt(3)/2) * Ibeta */ - *pIb = -0.5 * Ialpha + (float32_t) 0.8660254039 *Ibeta; - - } + /* Calculating pIb from Ialpha and Ibeta by equation pIb = -(1/2) * Ialpha + (sqrt(3)/2) * Ibeta */ + *pIb = -0.5 * Ialpha + (float32_t)0.8660254039 * Ibeta; + } - /** + /** * @brief Inverse Clarke transform for Q31 version * @param[in] Ialpha input two-phase orthogonal vector axis alpha * @param[in] Ibeta input two-phase orthogonal vector axis beta @@ -5421,51 +5281,48 @@ void arm_rfft_fast_f32( * There is saturation on the subtraction, hence there is no risk of overflow. */ - static __INLINE void arm_inv_clarke_q31( - q31_t Ialpha, - q31_t Ibeta, - q31_t * pIa, - q31_t * pIb) - { - q31_t product1, product2; /* Temporary variables used to store intermediate results */ - - /* Calculating pIa from Ialpha by equation pIa = Ialpha */ - *pIa = Ialpha; + static __INLINE void arm_inv_clarke_q31( + q31_t Ialpha, + q31_t Ibeta, + q31_t *pIa, + q31_t *pIb) + { + q31_t product1, product2; /* Temporary variables used to store intermediate results */ - /* Intermediate product is calculated by (1/(2*sqrt(3)) * Ia) */ - product1 = (q31_t) (((q63_t) (Ialpha) * (0x40000000)) >> 31); + /* Calculating pIa from Ialpha by equation pIa = Ialpha */ + *pIa = Ialpha; - /* Intermediate product is calculated by (1/sqrt(3) * pIb) */ - product2 = (q31_t) (((q63_t) (Ibeta) * (0x6ED9EBA1)) >> 31); + /* Intermediate product is calculated by (1/(2*sqrt(3)) * Ia) */ + product1 = (q31_t)(((q63_t)(Ialpha) * (0x40000000)) >> 31); - /* pIb is calculated by subtracting the products */ - *pIb = __QSUB(product2, product1); + /* Intermediate product is calculated by (1/sqrt(3) * pIb) */ + product2 = (q31_t)(((q63_t)(Ibeta) * (0x6ED9EBA1)) >> 31); - } + /* pIb is calculated by subtracting the products */ + *pIb = __QSUB(product2, product1); + } - /** + /** * @} end of inv_clarke group */ - /** + /** * @brief Converts the elements of the Q7 vector to Q15 vector. * @param[in] *pSrc input pointer * @param[out] *pDst output pointer * @param[in] blockSize number of samples to process * @return none. */ - void arm_q7_to_q15( - q7_t * pSrc, - q15_t * pDst, - uint32_t blockSize); + void arm_q7_to_q15( + q7_t *pSrc, + q15_t *pDst, + uint32_t blockSize); - - - /** + /** * @ingroup groupController */ - /** + /** * @defgroup park Vector Park Transform * * Forward Park transform converts the input two-coordinate vector to flux and torque components. @@ -5489,17 +5346,17 @@ void arm_rfft_fast_f32( * Refer to the function specific documentation below for usage guidelines. */ - /** + /** * @addtogroup park * @{ */ - /** + /** * @brief Floating-point Park transform * @param[in] Ialpha input two-phase vector coordinate alpha * @param[in] Ibeta input two-phase vector coordinate beta - * @param[out] *pId points to output rotor reference frame d - * @param[out] *pIq points to output rotor reference frame q + * @param[out] *pId points to output rotor reference frame d + * @param[out] *pIq points to output rotor reference frame q * @param[in] sinVal sine value of rotation angle theta * @param[in] cosVal cosine value of rotation angle theta * @return none. @@ -5508,23 +5365,22 @@ void arm_rfft_fast_f32( * */ - static __INLINE void arm_park_f32( - float32_t Ialpha, - float32_t Ibeta, - float32_t * pId, - float32_t * pIq, - float32_t sinVal, - float32_t cosVal) - { - /* Calculate pId using the equation, pId = Ialpha * cosVal + Ibeta * sinVal */ - *pId = Ialpha * cosVal + Ibeta * sinVal; - - /* Calculate pIq using the equation, pIq = - Ialpha * sinVal + Ibeta * cosVal */ - *pIq = -Ialpha * sinVal + Ibeta * cosVal; + static __INLINE void arm_park_f32( + float32_t Ialpha, + float32_t Ibeta, + float32_t *pId, + float32_t *pIq, + float32_t sinVal, + float32_t cosVal) + { + /* Calculate pId using the equation, pId = Ialpha * cosVal + Ibeta * sinVal */ + *pId = Ialpha * cosVal + Ibeta * sinVal; - } + /* Calculate pIq using the equation, pIq = - Ialpha * sinVal + Ibeta * cosVal */ + *pIq = -Ialpha * sinVal + Ibeta * cosVal; + } - /** + /** * @brief Park transform for Q31 version * @param[in] Ialpha input two-phase vector coordinate alpha * @param[in] Ibeta input two-phase vector coordinate beta @@ -5541,60 +5397,57 @@ void arm_rfft_fast_f32( * There is saturation on the addition and subtraction, hence there is no risk of overflow. */ + static __INLINE void arm_park_q31( + q31_t Ialpha, + q31_t Ibeta, + q31_t *pId, + q31_t *pIq, + q31_t sinVal, + q31_t cosVal) + { + q31_t product1, product2; /* Temporary variables used to store intermediate results */ + q31_t product3, product4; /* Temporary variables used to store intermediate results */ - static __INLINE void arm_park_q31( - q31_t Ialpha, - q31_t Ibeta, - q31_t * pId, - q31_t * pIq, - q31_t sinVal, - q31_t cosVal) - { - q31_t product1, product2; /* Temporary variables used to store intermediate results */ - q31_t product3, product4; /* Temporary variables used to store intermediate results */ - - /* Intermediate product is calculated by (Ialpha * cosVal) */ - product1 = (q31_t) (((q63_t) (Ialpha) * (cosVal)) >> 31); - - /* Intermediate product is calculated by (Ibeta * sinVal) */ - product2 = (q31_t) (((q63_t) (Ibeta) * (sinVal)) >> 31); + /* Intermediate product is calculated by (Ialpha * cosVal) */ + product1 = (q31_t)(((q63_t)(Ialpha) * (cosVal)) >> 31); + /* Intermediate product is calculated by (Ibeta * sinVal) */ + product2 = (q31_t)(((q63_t)(Ibeta) * (sinVal)) >> 31); - /* Intermediate product is calculated by (Ialpha * sinVal) */ - product3 = (q31_t) (((q63_t) (Ialpha) * (sinVal)) >> 31); + /* Intermediate product is calculated by (Ialpha * sinVal) */ + product3 = (q31_t)(((q63_t)(Ialpha) * (sinVal)) >> 31); - /* Intermediate product is calculated by (Ibeta * cosVal) */ - product4 = (q31_t) (((q63_t) (Ibeta) * (cosVal)) >> 31); + /* Intermediate product is calculated by (Ibeta * cosVal) */ + product4 = (q31_t)(((q63_t)(Ibeta) * (cosVal)) >> 31); - /* Calculate pId by adding the two intermediate products 1 and 2 */ - *pId = __QADD(product1, product2); + /* Calculate pId by adding the two intermediate products 1 and 2 */ + *pId = __QADD(product1, product2); - /* Calculate pIq by subtracting the two intermediate products 3 from 4 */ - *pIq = __QSUB(product4, product3); - } + /* Calculate pIq by subtracting the two intermediate products 3 from 4 */ + *pIq = __QSUB(product4, product3); + } - /** + /** * @} end of park group */ - /** + /** * @brief Converts the elements of the Q7 vector to floating-point vector. * @param[in] *pSrc is input pointer * @param[out] *pDst is output pointer * @param[in] blockSize is the number of samples to process * @return none. */ - void arm_q7_to_float( - q7_t * pSrc, - float32_t * pDst, - uint32_t blockSize); - + void arm_q7_to_float( + q7_t *pSrc, + float32_t *pDst, + uint32_t blockSize); - /** + /** * @ingroup groupController */ - /** + /** * @defgroup inv_park Vector Inverse Park transform * Inverse Park transform converts the input flux and torque components to two-coordinate vector. * @@ -5611,12 +5464,12 @@ void arm_rfft_fast_f32( * Refer to the function specific documentation below for usage guidelines. */ - /** + /** * @addtogroup inv_park * @{ */ - /** + /** * @brief Floating-point Inverse Park transform * @param[in] Id input coordinate of rotor reference frame d * @param[in] Iq input coordinate of rotor reference frame q @@ -5627,25 +5480,23 @@ void arm_rfft_fast_f32( * @return none. */ - static __INLINE void arm_inv_park_f32( - float32_t Id, - float32_t Iq, - float32_t * pIalpha, - float32_t * pIbeta, - float32_t sinVal, - float32_t cosVal) - { - /* Calculate pIalpha using the equation, pIalpha = Id * cosVal - Iq * sinVal */ - *pIalpha = Id * cosVal - Iq * sinVal; - - /* Calculate pIbeta using the equation, pIbeta = Id * sinVal + Iq * cosVal */ - *pIbeta = Id * sinVal + Iq * cosVal; - - } + static __INLINE void arm_inv_park_f32( + float32_t Id, + float32_t Iq, + float32_t *pIalpha, + float32_t *pIbeta, + float32_t sinVal, + float32_t cosVal) + { + /* Calculate pIalpha using the equation, pIalpha = Id * cosVal - Iq * sinVal */ + *pIalpha = Id * cosVal - Iq * sinVal; + /* Calculate pIbeta using the equation, pIbeta = Id * sinVal + Iq * cosVal */ + *pIbeta = Id * sinVal + Iq * cosVal; + } - /** - * @brief Inverse Park transform for Q31 version + /** + * @brief Inverse Park transform for Q31 version * @param[in] Id input coordinate of rotor reference frame d * @param[in] Iq input coordinate of rotor reference frame q * @param[out] *pIalpha points to output two-phase orthogonal vector axis alpha @@ -5661,61 +5512,57 @@ void arm_rfft_fast_f32( * There is saturation on the addition, hence there is no risk of overflow. */ + static __INLINE void arm_inv_park_q31( + q31_t Id, + q31_t Iq, + q31_t *pIalpha, + q31_t *pIbeta, + q31_t sinVal, + q31_t cosVal) + { + q31_t product1, product2; /* Temporary variables used to store intermediate results */ + q31_t product3, product4; /* Temporary variables used to store intermediate results */ - static __INLINE void arm_inv_park_q31( - q31_t Id, - q31_t Iq, - q31_t * pIalpha, - q31_t * pIbeta, - q31_t sinVal, - q31_t cosVal) - { - q31_t product1, product2; /* Temporary variables used to store intermediate results */ - q31_t product3, product4; /* Temporary variables used to store intermediate results */ - - /* Intermediate product is calculated by (Id * cosVal) */ - product1 = (q31_t) (((q63_t) (Id) * (cosVal)) >> 31); - - /* Intermediate product is calculated by (Iq * sinVal) */ - product2 = (q31_t) (((q63_t) (Iq) * (sinVal)) >> 31); - + /* Intermediate product is calculated by (Id * cosVal) */ + product1 = (q31_t)(((q63_t)(Id) * (cosVal)) >> 31); - /* Intermediate product is calculated by (Id * sinVal) */ - product3 = (q31_t) (((q63_t) (Id) * (sinVal)) >> 31); + /* Intermediate product is calculated by (Iq * sinVal) */ + product2 = (q31_t)(((q63_t)(Iq) * (sinVal)) >> 31); - /* Intermediate product is calculated by (Iq * cosVal) */ - product4 = (q31_t) (((q63_t) (Iq) * (cosVal)) >> 31); + /* Intermediate product is calculated by (Id * sinVal) */ + product3 = (q31_t)(((q63_t)(Id) * (sinVal)) >> 31); - /* Calculate pIalpha by using the two intermediate products 1 and 2 */ - *pIalpha = __QSUB(product1, product2); + /* Intermediate product is calculated by (Iq * cosVal) */ + product4 = (q31_t)(((q63_t)(Iq) * (cosVal)) >> 31); - /* Calculate pIbeta by using the two intermediate products 3 and 4 */ - *pIbeta = __QADD(product4, product3); + /* Calculate pIalpha by using the two intermediate products 1 and 2 */ + *pIalpha = __QSUB(product1, product2); - } + /* Calculate pIbeta by using the two intermediate products 3 and 4 */ + *pIbeta = __QADD(product4, product3); + } - /** + /** * @} end of Inverse park group */ - - /** + /** * @brief Converts the elements of the Q31 vector to floating-point vector. * @param[in] *pSrc is input pointer * @param[out] *pDst is output pointer * @param[in] blockSize is the number of samples to process * @return none. */ - void arm_q31_to_float( - q31_t * pSrc, - float32_t * pDst, - uint32_t blockSize); + void arm_q31_to_float( + q31_t *pSrc, + float32_t *pDst, + uint32_t blockSize); - /** + /** * @ingroup groupInterpolation */ - /** + /** * @defgroup LinearInterpolate Linear Interpolation * * Linear interpolation is a method of curve fitting using linear polynomials. @@ -5747,12 +5594,12 @@ void arm_rfft_fast_f32( * if x is below input range and returns last value of table if x is above range. */ - /** + /** * @addtogroup LinearInterpolate * @{ */ - /** + /** * @brief Process function for the floating-point Linear Interpolation Function. * @param[in,out] *S is an instance of the floating-point Linear Interpolation structure * @param[in] x input sample to process @@ -5760,51 +5607,50 @@ void arm_rfft_fast_f32( * */ - static __INLINE float32_t arm_linear_interp_f32( - arm_linear_interp_instance_f32 * S, - float32_t x) - { - - float32_t y; - float32_t x0, x1; /* Nearest input values */ - float32_t y0, y1; /* Nearest output values */ - float32_t xSpacing = S->xSpacing; /* spacing between input values */ - int32_t i; /* Index variable */ - float32_t *pYData = S->pYData; /* pointer to output table */ - - /* Calculation of index */ - i = (int32_t) ((x - S->x1) / xSpacing); - - if(i < 0) - { - /* Iniatilize output for below specified range as least output value of table */ - y = pYData[0]; - } - else if((uint32_t)i >= S->nValues) + static __INLINE float32_t arm_linear_interp_f32( + arm_linear_interp_instance_f32 *S, + float32_t x) { - /* Iniatilize output for above specified range as last output value of table */ - y = pYData[S->nValues - 1]; - } - else - { - /* Calculation of nearest input values */ - x0 = S->x1 + i * xSpacing; - x1 = S->x1 + (i + 1) * xSpacing; - - /* Read of nearest output values */ - y0 = pYData[i]; - y1 = pYData[i + 1]; - - /* Calculation of output */ - y = y0 + (x - x0) * ((y1 - y0) / (x1 - x0)); + float32_t y; + float32_t x0, x1; /* Nearest input values */ + float32_t y0, y1; /* Nearest output values */ + float32_t xSpacing = S->xSpacing; /* spacing between input values */ + int32_t i; /* Index variable */ + float32_t *pYData = S->pYData; /* pointer to output table */ + + /* Calculation of index */ + i = (int32_t)((x - S->x1) / xSpacing); + + if (i < 0) + { + /* Iniatilize output for below specified range as least output value of table */ + y = pYData[0]; + } + else if ((uint32_t)i >= S->nValues) + { + /* Iniatilize output for above specified range as last output value of table */ + y = pYData[S->nValues - 1]; + } + else + { + /* Calculation of nearest input values */ + x0 = S->x1 + i * xSpacing; + x1 = S->x1 + (i + 1) * xSpacing; + + /* Read of nearest output values */ + y0 = pYData[i]; + y1 = pYData[i + 1]; + + /* Calculation of output */ + y = y0 + (x - x0) * ((y1 - y0) / (x1 - x0)); + } + + /* returns output value */ + return (y); } - /* returns output value */ - return (y); - } - - /** + /** * * @brief Process function for the Q31 Linear Interpolation Function. * @param[in] *pYData pointer to Q31 Linear Interpolation table @@ -5818,55 +5664,52 @@ void arm_rfft_fast_f32( * */ - - static __INLINE q31_t arm_linear_interp_q31( - q31_t * pYData, - q31_t x, - uint32_t nValues) - { - q31_t y; /* output */ - q31_t y0, y1; /* Nearest output values */ - q31_t fract; /* fractional part */ - int32_t index; /* Index to read nearest output values */ - - /* Input is in 12.20 format */ - /* 12 bits for the table index */ - /* Index value calculation */ - index = ((x & 0xFFF00000) >> 20); - - if(index >= (int32_t)(nValues - 1)) - { - return (pYData[nValues - 1]); - } - else if(index < 0) + static __INLINE q31_t arm_linear_interp_q31( + q31_t *pYData, + q31_t x, + uint32_t nValues) { - return (pYData[0]); + q31_t y; /* output */ + q31_t y0, y1; /* Nearest output values */ + q31_t fract; /* fractional part */ + int32_t index; /* Index to read nearest output values */ + + /* Input is in 12.20 format */ + /* 12 bits for the table index */ + /* Index value calculation */ + index = ((x & 0xFFF00000) >> 20); + + if (index >= (int32_t)(nValues - 1)) + { + return (pYData[nValues - 1]); + } + else if (index < 0) + { + return (pYData[0]); + } + else + { + + /* 20 bits for the fractional part */ + /* shift left by 11 to keep fract in 1.31 format */ + fract = (x & 0x000FFFFF) << 11; + + /* Read two nearest output values from the index in 1.31(q31) format */ + y0 = pYData[index]; + y1 = pYData[index + 1u]; + + /* Calculation of y0 * (1-fract) and y is in 2.30 format */ + y = ((q31_t)((q63_t)y0 * (0x7FFFFFFF - fract) >> 32)); + + /* Calculation of y0 * (1-fract) + y1 *fract and y is in 2.30 format */ + y += ((q31_t)(((q63_t)y1 * fract) >> 32)); + + /* Convert y to 1.31 format */ + return (y << 1u); + } } - else - { - - /* 20 bits for the fractional part */ - /* shift left by 11 to keep fract in 1.31 format */ - fract = (x & 0x000FFFFF) << 11; - /* Read two nearest output values from the index in 1.31(q31) format */ - y0 = pYData[index]; - y1 = pYData[index + 1u]; - - /* Calculation of y0 * (1-fract) and y is in 2.30 format */ - y = ((q31_t) ((q63_t) y0 * (0x7FFFFFFF - fract) >> 32)); - - /* Calculation of y0 * (1-fract) + y1 *fract and y is in 2.30 format */ - y += ((q31_t) (((q63_t) y1 * fract) >> 32)); - - /* Convert y to 1.31 format */ - return (y << 1u); - - } - - } - - /** + /** * * @brief Process function for the Q15 Linear Interpolation Function. * @param[in] *pYData pointer to Q15 Linear Interpolation table @@ -5880,54 +5723,51 @@ void arm_rfft_fast_f32( * */ - - static __INLINE q15_t arm_linear_interp_q15( - q15_t * pYData, - q31_t x, - uint32_t nValues) - { - q63_t y; /* output */ - q15_t y0, y1; /* Nearest output values */ - q31_t fract; /* fractional part */ - int32_t index; /* Index to read nearest output values */ - - /* Input is in 12.20 format */ - /* 12 bits for the table index */ - /* Index value calculation */ - index = ((x & 0xFFF00000) >> 20u); - - if(index >= (int32_t)(nValues - 1)) - { - return (pYData[nValues - 1]); - } - else if(index < 0) - { - return (pYData[0]); - } - else + static __INLINE q15_t arm_linear_interp_q15( + q15_t *pYData, + q31_t x, + uint32_t nValues) { - /* 20 bits for the fractional part */ - /* fract is in 12.20 format */ - fract = (x & 0x000FFFFF); - - /* Read two nearest output values from the index */ - y0 = pYData[index]; - y1 = pYData[index + 1u]; - - /* Calculation of y0 * (1-fract) and y is in 13.35 format */ - y = ((q63_t) y0 * (0xFFFFF - fract)); - - /* Calculation of (y0 * (1-fract) + y1 * fract) and y is in 13.35 format */ - y += ((q63_t) y1 * (fract)); - - /* convert y to 1.15 format */ - return (y >> 20); + q63_t y; /* output */ + q15_t y0, y1; /* Nearest output values */ + q31_t fract; /* fractional part */ + int32_t index; /* Index to read nearest output values */ + + /* Input is in 12.20 format */ + /* 12 bits for the table index */ + /* Index value calculation */ + index = ((x & 0xFFF00000) >> 20u); + + if (index >= (int32_t)(nValues - 1)) + { + return (pYData[nValues - 1]); + } + else if (index < 0) + { + return (pYData[0]); + } + else + { + /* 20 bits for the fractional part */ + /* fract is in 12.20 format */ + fract = (x & 0x000FFFFF); + + /* Read two nearest output values from the index */ + y0 = pYData[index]; + y1 = pYData[index + 1u]; + + /* Calculation of y0 * (1-fract) and y is in 13.35 format */ + y = ((q63_t)y0 * (0xFFFFF - fract)); + + /* Calculation of (y0 * (1-fract) + y1 * fract) and y is in 13.35 format */ + y += ((q63_t)y1 * (fract)); + + /* convert y to 1.15 format */ + return (y >> 20); + } } - - } - - /** + /** * * @brief Process function for the Q7 Linear Interpolation Function. * @param[in] *pYData pointer to Q7 Linear Interpolation table @@ -5940,119 +5780,113 @@ void arm_rfft_fast_f32( * This function can support maximum of table size 2^12. */ - - static __INLINE q7_t arm_linear_interp_q7( - q7_t * pYData, - q31_t x, - uint32_t nValues) - { - q31_t y; /* output */ - q7_t y0, y1; /* Nearest output values */ - q31_t fract; /* fractional part */ - uint32_t index; /* Index to read nearest output values */ - - /* Input is in 12.20 format */ - /* 12 bits for the table index */ - /* Index value calculation */ - if (x < 0) + static __INLINE q7_t arm_linear_interp_q7( + q7_t *pYData, + q31_t x, + uint32_t nValues) { - return (pYData[0]); + q31_t y; /* output */ + q7_t y0, y1; /* Nearest output values */ + q31_t fract; /* fractional part */ + uint32_t index; /* Index to read nearest output values */ + + /* Input is in 12.20 format */ + /* 12 bits for the table index */ + /* Index value calculation */ + if (x < 0) + { + return (pYData[0]); + } + index = (x >> 20) & 0xfff; + + if (index >= (nValues - 1)) + { + return (pYData[nValues - 1]); + } + else + { + + /* 20 bits for the fractional part */ + /* fract is in 12.20 format */ + fract = (x & 0x000FFFFF); + + /* Read two nearest output values from the index and are in 1.7(q7) format */ + y0 = pYData[index]; + y1 = pYData[index + 1u]; + + /* Calculation of y0 * (1-fract ) and y is in 13.27(q27) format */ + y = ((y0 * (0xFFFFF - fract))); + + /* Calculation of y1 * fract + y0 * (1-fract) and y is in 13.27(q27) format */ + y += (y1 * fract); + + /* convert y to 1.7(q7) format */ + return (y >> 20u); + } } - index = (x >> 20) & 0xfff; - - - if(index >= (nValues - 1)) - { - return (pYData[nValues - 1]); - } - else - { - - /* 20 bits for the fractional part */ - /* fract is in 12.20 format */ - fract = (x & 0x000FFFFF); - - /* Read two nearest output values from the index and are in 1.7(q7) format */ - y0 = pYData[index]; - y1 = pYData[index + 1u]; - - /* Calculation of y0 * (1-fract ) and y is in 13.27(q27) format */ - y = ((y0 * (0xFFFFF - fract))); - - /* Calculation of y1 * fract + y0 * (1-fract) and y is in 13.27(q27) format */ - y += (y1 * fract); - - /* convert y to 1.7(q7) format */ - return (y >> 20u); - - } - - } - /** + /** * @} end of LinearInterpolate group */ - /** + /** * @brief Fast approximation to the trigonometric sine function for floating-point data. * @param[in] x input value in radians. * @return sin(x). */ - float32_t arm_sin_f32( - float32_t x); + float32_t arm_sin_f32( + float32_t x); - /** + /** * @brief Fast approximation to the trigonometric sine function for Q31 data. * @param[in] x Scaled input value in radians. * @return sin(x). */ - q31_t arm_sin_q31( - q31_t x); + q31_t arm_sin_q31( + q31_t x); - /** + /** * @brief Fast approximation to the trigonometric sine function for Q15 data. * @param[in] x Scaled input value in radians. * @return sin(x). */ - q15_t arm_sin_q15( - q15_t x); + q15_t arm_sin_q15( + q15_t x); - /** + /** * @brief Fast approximation to the trigonometric cosine function for floating-point data. * @param[in] x input value in radians. * @return cos(x). */ - float32_t arm_cos_f32( - float32_t x); + float32_t arm_cos_f32( + float32_t x); - /** + /** * @brief Fast approximation to the trigonometric cosine function for Q31 data. * @param[in] x Scaled input value in radians. * @return cos(x). */ - q31_t arm_cos_q31( - q31_t x); + q31_t arm_cos_q31( + q31_t x); - /** + /** * @brief Fast approximation to the trigonometric cosine function for Q15 data. * @param[in] x Scaled input value in radians. * @return cos(x). */ - q15_t arm_cos_q15( - q15_t x); + q15_t arm_cos_q15( + q15_t x); - - /** + /** * @ingroup groupFastMath */ - - /** + /** * @defgroup SQRT Square Root * * Computes the square root of a number. @@ -6072,13 +5906,12 @@ void arm_rfft_fast_f32( * */ - - /** + /** * @addtogroup SQRT * @{ */ - /** + /** * @brief Floating-point square root function. * @param[in] in input value. * @param[out] *pOut square root of input value. @@ -6086,367 +5919,352 @@ void arm_rfft_fast_f32( * in is negative value and returns zero output for negative values. */ - static __INLINE arm_status arm_sqrt_f32( - float32_t in, - float32_t * pOut) - { - if(in > 0) + static __INLINE arm_status arm_sqrt_f32( + float32_t in, + float32_t *pOut) { + if (in > 0) + { // #if __FPU_USED -#if (__FPU_USED == 1) && defined ( __CC_ARM ) - *pOut = __sqrtf(in); +#if (__FPU_USED == 1) && defined(__CC_ARM) + *pOut = __sqrtf(in); #else - *pOut = sqrtf(in); + *pOut = sqrtf(in); #endif - return (ARM_MATH_SUCCESS); - } - else - { - *pOut = 0.0f; - return (ARM_MATH_ARGUMENT_ERROR); + return (ARM_MATH_SUCCESS); + } + else + { + *pOut = 0.0f; + return (ARM_MATH_ARGUMENT_ERROR); + } } - } - - - /** + /** * @brief Q31 square root function. * @param[in] in input value. The range of the input value is [0 +1) or 0x00000000 to 0x7FFFFFFF. * @param[out] *pOut square root of input value. * @return The function returns ARM_MATH_SUCCESS if input value is positive value or ARM_MATH_ARGUMENT_ERROR if * in is negative value and returns zero output for negative values. */ - arm_status arm_sqrt_q31( - q31_t in, - q31_t * pOut); + arm_status arm_sqrt_q31( + q31_t in, + q31_t *pOut); - /** + /** * @brief Q15 square root function. * @param[in] in input value. The range of the input value is [0 +1) or 0x0000 to 0x7FFF. * @param[out] *pOut square root of input value. * @return The function returns ARM_MATH_SUCCESS if input value is positive value or ARM_MATH_ARGUMENT_ERROR if * in is negative value and returns zero output for negative values. */ - arm_status arm_sqrt_q15( - q15_t in, - q15_t * pOut); + arm_status arm_sqrt_q15( + q15_t in, + q15_t *pOut); - /** + /** * @} end of SQRT group */ - - - - - - /** + /** * @brief floating-point Circular write function. */ - static __INLINE void arm_circularWrite_f32( - int32_t * circBuffer, - int32_t L, - uint16_t * writeOffset, - int32_t bufferInc, - const int32_t * src, - int32_t srcInc, - uint32_t blockSize) - { - uint32_t i = 0u; - int32_t wOffset; + static __INLINE void arm_circularWrite_f32( + int32_t *circBuffer, + int32_t L, + uint16_t *writeOffset, + int32_t bufferInc, + const int32_t *src, + int32_t srcInc, + uint32_t blockSize) + { + uint32_t i = 0u; + int32_t wOffset; - /* Copy the value of Index pointer that points + /* Copy the value of Index pointer that points * to the current location where the input samples to be copied */ - wOffset = *writeOffset; + wOffset = *writeOffset; - /* Loop over the blockSize */ - i = blockSize; + /* Loop over the blockSize */ + i = blockSize; - while(i > 0u) - { - /* copy the input sample to the circular buffer */ - circBuffer[wOffset] = *src; + while (i > 0u) + { + /* copy the input sample to the circular buffer */ + circBuffer[wOffset] = *src; - /* Update the input pointer */ - src += srcInc; - - /* Circularly update wOffset. Watch out for positive and negative value */ - wOffset += bufferInc; - if(wOffset >= L) - wOffset -= L; - - /* Decrement the loop counter */ - i--; - } + /* Update the input pointer */ + src += srcInc; - /* Update the index pointer */ - *writeOffset = wOffset; - } + /* Circularly update wOffset. Watch out for positive and negative value */ + wOffset += bufferInc; + if (wOffset >= L) + wOffset -= L; + /* Decrement the loop counter */ + i--; + } + /* Update the index pointer */ + *writeOffset = wOffset; + } - /** + /** * @brief floating-point Circular Read function. */ - static __INLINE void arm_circularRead_f32( - int32_t * circBuffer, - int32_t L, - int32_t * readOffset, - int32_t bufferInc, - int32_t * dst, - int32_t * dst_base, - int32_t dst_length, - int32_t dstInc, - uint32_t blockSize) - { - uint32_t i = 0u; - int32_t rOffset, dst_end; - - /* Copy the value of Index pointer that points + static __INLINE void arm_circularRead_f32( + int32_t *circBuffer, + int32_t L, + int32_t *readOffset, + int32_t bufferInc, + int32_t *dst, + int32_t *dst_base, + int32_t dst_length, + int32_t dstInc, + uint32_t blockSize) + { + uint32_t i = 0u; + int32_t rOffset, dst_end; + + /* Copy the value of Index pointer that points * to the current location from where the input samples to be read */ - rOffset = *readOffset; - dst_end = (int32_t) (dst_base + dst_length); + rOffset = *readOffset; + dst_end = (int32_t)(dst_base + dst_length); - /* Loop over the blockSize */ - i = blockSize; + /* Loop over the blockSize */ + i = blockSize; - while(i > 0u) - { - /* copy the sample from the circular buffer to the destination buffer */ - *dst = circBuffer[rOffset]; + while (i > 0u) + { + /* copy the sample from the circular buffer to the destination buffer */ + *dst = circBuffer[rOffset]; - /* Update the input pointer */ - dst += dstInc; + /* Update the input pointer */ + dst += dstInc; - if(dst == (int32_t *) dst_end) - { - dst = dst_base; - } + if (dst == (int32_t *)dst_end) + { + dst = dst_base; + } - /* Circularly update rOffset. Watch out for positive and negative value */ - rOffset += bufferInc; + /* Circularly update rOffset. Watch out for positive and negative value */ + rOffset += bufferInc; - if(rOffset >= L) - { - rOffset -= L; - } + if (rOffset >= L) + { + rOffset -= L; + } - /* Decrement the loop counter */ - i--; - } + /* Decrement the loop counter */ + i--; + } - /* Update the index pointer */ - *readOffset = rOffset; - } + /* Update the index pointer */ + *readOffset = rOffset; + } - /** + /** * @brief Q15 Circular write function. */ - static __INLINE void arm_circularWrite_q15( - q15_t * circBuffer, - int32_t L, - uint16_t * writeOffset, - int32_t bufferInc, - const q15_t * src, - int32_t srcInc, - uint32_t blockSize) - { - uint32_t i = 0u; - int32_t wOffset; + static __INLINE void arm_circularWrite_q15( + q15_t *circBuffer, + int32_t L, + uint16_t *writeOffset, + int32_t bufferInc, + const q15_t *src, + int32_t srcInc, + uint32_t blockSize) + { + uint32_t i = 0u; + int32_t wOffset; - /* Copy the value of Index pointer that points + /* Copy the value of Index pointer that points * to the current location where the input samples to be copied */ - wOffset = *writeOffset; - - /* Loop over the blockSize */ - i = blockSize; - - while(i > 0u) - { - /* copy the input sample to the circular buffer */ - circBuffer[wOffset] = *src; + wOffset = *writeOffset; - /* Update the input pointer */ - src += srcInc; + /* Loop over the blockSize */ + i = blockSize; - /* Circularly update wOffset. Watch out for positive and negative value */ - wOffset += bufferInc; - if(wOffset >= L) - wOffset -= L; + while (i > 0u) + { + /* copy the input sample to the circular buffer */ + circBuffer[wOffset] = *src; - /* Decrement the loop counter */ - i--; - } + /* Update the input pointer */ + src += srcInc; - /* Update the index pointer */ - *writeOffset = wOffset; - } + /* Circularly update wOffset. Watch out for positive and negative value */ + wOffset += bufferInc; + if (wOffset >= L) + wOffset -= L; + /* Decrement the loop counter */ + i--; + } + /* Update the index pointer */ + *writeOffset = wOffset; + } - /** + /** * @brief Q15 Circular Read function. */ - static __INLINE void arm_circularRead_q15( - q15_t * circBuffer, - int32_t L, - int32_t * readOffset, - int32_t bufferInc, - q15_t * dst, - q15_t * dst_base, - int32_t dst_length, - int32_t dstInc, - uint32_t blockSize) - { - uint32_t i = 0; - int32_t rOffset, dst_end; - - /* Copy the value of Index pointer that points - * to the current location from where the input samples to be read */ - rOffset = *readOffset; + static __INLINE void arm_circularRead_q15( + q15_t *circBuffer, + int32_t L, + int32_t *readOffset, + int32_t bufferInc, + q15_t *dst, + q15_t *dst_base, + int32_t dst_length, + int32_t dstInc, + uint32_t blockSize) + { + uint32_t i = 0; + int32_t rOffset, dst_end; - dst_end = (int32_t) (dst_base + dst_length); + /* Copy the value of Index pointer that points + * to the current location from where the input samples to be read */ + rOffset = *readOffset; - /* Loop over the blockSize */ - i = blockSize; + dst_end = (int32_t)(dst_base + dst_length); - while(i > 0u) - { - /* copy the sample from the circular buffer to the destination buffer */ - *dst = circBuffer[rOffset]; + /* Loop over the blockSize */ + i = blockSize; - /* Update the input pointer */ - dst += dstInc; + while (i > 0u) + { + /* copy the sample from the circular buffer to the destination buffer */ + *dst = circBuffer[rOffset]; - if(dst == (q15_t *) dst_end) - { - dst = dst_base; - } + /* Update the input pointer */ + dst += dstInc; - /* Circularly update wOffset. Watch out for positive and negative value */ - rOffset += bufferInc; + if (dst == (q15_t *)dst_end) + { + dst = dst_base; + } - if(rOffset >= L) - { - rOffset -= L; - } + /* Circularly update wOffset. Watch out for positive and negative value */ + rOffset += bufferInc; - /* Decrement the loop counter */ - i--; - } + if (rOffset >= L) + { + rOffset -= L; + } - /* Update the index pointer */ - *readOffset = rOffset; - } + /* Decrement the loop counter */ + i--; + } + /* Update the index pointer */ + *readOffset = rOffset; + } - /** + /** * @brief Q7 Circular write function. */ - static __INLINE void arm_circularWrite_q7( - q7_t * circBuffer, - int32_t L, - uint16_t * writeOffset, - int32_t bufferInc, - const q7_t * src, - int32_t srcInc, - uint32_t blockSize) - { - uint32_t i = 0u; - int32_t wOffset; + static __INLINE void arm_circularWrite_q7( + q7_t *circBuffer, + int32_t L, + uint16_t *writeOffset, + int32_t bufferInc, + const q7_t *src, + int32_t srcInc, + uint32_t blockSize) + { + uint32_t i = 0u; + int32_t wOffset; - /* Copy the value of Index pointer that points + /* Copy the value of Index pointer that points * to the current location where the input samples to be copied */ - wOffset = *writeOffset; + wOffset = *writeOffset; - /* Loop over the blockSize */ - i = blockSize; + /* Loop over the blockSize */ + i = blockSize; - while(i > 0u) - { - /* copy the input sample to the circular buffer */ - circBuffer[wOffset] = *src; + while (i > 0u) + { + /* copy the input sample to the circular buffer */ + circBuffer[wOffset] = *src; - /* Update the input pointer */ - src += srcInc; + /* Update the input pointer */ + src += srcInc; - /* Circularly update wOffset. Watch out for positive and negative value */ - wOffset += bufferInc; - if(wOffset >= L) - wOffset -= L; - - /* Decrement the loop counter */ - i--; - } - - /* Update the index pointer */ - *writeOffset = wOffset; - } + /* Circularly update wOffset. Watch out for positive and negative value */ + wOffset += bufferInc; + if (wOffset >= L) + wOffset -= L; + /* Decrement the loop counter */ + i--; + } + /* Update the index pointer */ + *writeOffset = wOffset; + } - /** + /** * @brief Q7 Circular Read function. */ - static __INLINE void arm_circularRead_q7( - q7_t * circBuffer, - int32_t L, - int32_t * readOffset, - int32_t bufferInc, - q7_t * dst, - q7_t * dst_base, - int32_t dst_length, - int32_t dstInc, - uint32_t blockSize) - { - uint32_t i = 0; - int32_t rOffset, dst_end; - - /* Copy the value of Index pointer that points - * to the current location from where the input samples to be read */ - rOffset = *readOffset; + static __INLINE void arm_circularRead_q7( + q7_t *circBuffer, + int32_t L, + int32_t *readOffset, + int32_t bufferInc, + q7_t *dst, + q7_t *dst_base, + int32_t dst_length, + int32_t dstInc, + uint32_t blockSize) + { + uint32_t i = 0; + int32_t rOffset, dst_end; - dst_end = (int32_t) (dst_base + dst_length); + /* Copy the value of Index pointer that points + * to the current location from where the input samples to be read */ + rOffset = *readOffset; - /* Loop over the blockSize */ - i = blockSize; + dst_end = (int32_t)(dst_base + dst_length); - while(i > 0u) - { - /* copy the sample from the circular buffer to the destination buffer */ - *dst = circBuffer[rOffset]; + /* Loop over the blockSize */ + i = blockSize; - /* Update the input pointer */ - dst += dstInc; + while (i > 0u) + { + /* copy the sample from the circular buffer to the destination buffer */ + *dst = circBuffer[rOffset]; - if(dst == (q7_t *) dst_end) - { - dst = dst_base; - } + /* Update the input pointer */ + dst += dstInc; - /* Circularly update rOffset. Watch out for positive and negative value */ - rOffset += bufferInc; + if (dst == (q7_t *)dst_end) + { + dst = dst_base; + } - if(rOffset >= L) - { - rOffset -= L; - } + /* Circularly update rOffset. Watch out for positive and negative value */ + rOffset += bufferInc; - /* Decrement the loop counter */ - i--; - } + if (rOffset >= L) + { + rOffset -= L; + } - /* Update the index pointer */ - *readOffset = rOffset; - } + /* Decrement the loop counter */ + i--; + } + /* Update the index pointer */ + *readOffset = rOffset; + } - /** + /** * @brief Sum of the squares of the elements of a Q31 vector. * @param[in] *pSrc is input pointer * @param[in] blockSize is the number of samples to process @@ -6454,12 +6272,12 @@ void arm_rfft_fast_f32( * @return none. */ - void arm_power_q31( - q31_t * pSrc, - uint32_t blockSize, - q63_t * pResult); + void arm_power_q31( + q31_t *pSrc, + uint32_t blockSize, + q63_t *pResult); - /** + /** * @brief Sum of the squares of the elements of a floating-point vector. * @param[in] *pSrc is input pointer * @param[in] blockSize is the number of samples to process @@ -6467,12 +6285,12 @@ void arm_rfft_fast_f32( * @return none. */ - void arm_power_f32( - float32_t * pSrc, - uint32_t blockSize, - float32_t * pResult); + void arm_power_f32( + float32_t *pSrc, + uint32_t blockSize, + float32_t *pResult); - /** + /** * @brief Sum of the squares of the elements of a Q15 vector. * @param[in] *pSrc is input pointer * @param[in] blockSize is the number of samples to process @@ -6480,12 +6298,12 @@ void arm_rfft_fast_f32( * @return none. */ - void arm_power_q15( - q15_t * pSrc, - uint32_t blockSize, - q63_t * pResult); + void arm_power_q15( + q15_t *pSrc, + uint32_t blockSize, + q63_t *pResult); - /** + /** * @brief Sum of the squares of the elements of a Q7 vector. * @param[in] *pSrc is input pointer * @param[in] blockSize is the number of samples to process @@ -6493,12 +6311,12 @@ void arm_rfft_fast_f32( * @return none. */ - void arm_power_q7( - q7_t * pSrc, - uint32_t blockSize, - q31_t * pResult); + void arm_power_q7( + q7_t *pSrc, + uint32_t blockSize, + q31_t *pResult); - /** + /** * @brief Mean value of a Q7 vector. * @param[in] *pSrc is input pointer * @param[in] blockSize is the number of samples to process @@ -6506,48 +6324,48 @@ void arm_rfft_fast_f32( * @return none. */ - void arm_mean_q7( - q7_t * pSrc, - uint32_t blockSize, - q7_t * pResult); + void arm_mean_q7( + q7_t *pSrc, + uint32_t blockSize, + q7_t *pResult); - /** + /** * @brief Mean value of a Q15 vector. * @param[in] *pSrc is input pointer * @param[in] blockSize is the number of samples to process * @param[out] *pResult is output value. * @return none. */ - void arm_mean_q15( - q15_t * pSrc, - uint32_t blockSize, - q15_t * pResult); + void arm_mean_q15( + q15_t *pSrc, + uint32_t blockSize, + q15_t *pResult); - /** + /** * @brief Mean value of a Q31 vector. * @param[in] *pSrc is input pointer * @param[in] blockSize is the number of samples to process * @param[out] *pResult is output value. * @return none. */ - void arm_mean_q31( - q31_t * pSrc, - uint32_t blockSize, - q31_t * pResult); + void arm_mean_q31( + q31_t *pSrc, + uint32_t blockSize, + q31_t *pResult); - /** + /** * @brief Mean value of a floating-point vector. * @param[in] *pSrc is input pointer * @param[in] blockSize is the number of samples to process * @param[out] *pResult is output value. * @return none. */ - void arm_mean_f32( - float32_t * pSrc, - uint32_t blockSize, - float32_t * pResult); + void arm_mean_f32( + float32_t *pSrc, + uint32_t blockSize, + float32_t *pResult); - /** + /** * @brief Variance of the elements of a floating-point vector. * @param[in] *pSrc is input pointer * @param[in] blockSize is the number of samples to process @@ -6555,12 +6373,12 @@ void arm_rfft_fast_f32( * @return none. */ - void arm_var_f32( - float32_t * pSrc, - uint32_t blockSize, - float32_t * pResult); + void arm_var_f32( + float32_t *pSrc, + uint32_t blockSize, + float32_t *pResult); - /** + /** * @brief Variance of the elements of a Q31 vector. * @param[in] *pSrc is input pointer * @param[in] blockSize is the number of samples to process @@ -6568,12 +6386,12 @@ void arm_rfft_fast_f32( * @return none. */ - void arm_var_q31( - q31_t * pSrc, - uint32_t blockSize, - q31_t * pResult); + void arm_var_q31( + q31_t *pSrc, + uint32_t blockSize, + q31_t *pResult); - /** + /** * @brief Variance of the elements of a Q15 vector. * @param[in] *pSrc is input pointer * @param[in] blockSize is the number of samples to process @@ -6581,12 +6399,12 @@ void arm_rfft_fast_f32( * @return none. */ - void arm_var_q15( - q15_t * pSrc, - uint32_t blockSize, - q15_t * pResult); + void arm_var_q15( + q15_t *pSrc, + uint32_t blockSize, + q15_t *pResult); - /** + /** * @brief Root Mean Square of the elements of a floating-point vector. * @param[in] *pSrc is input pointer * @param[in] blockSize is the number of samples to process @@ -6594,12 +6412,12 @@ void arm_rfft_fast_f32( * @return none. */ - void arm_rms_f32( - float32_t * pSrc, - uint32_t blockSize, - float32_t * pResult); + void arm_rms_f32( + float32_t *pSrc, + uint32_t blockSize, + float32_t *pResult); - /** + /** * @brief Root Mean Square of the elements of a Q31 vector. * @param[in] *pSrc is input pointer * @param[in] blockSize is the number of samples to process @@ -6607,12 +6425,12 @@ void arm_rfft_fast_f32( * @return none. */ - void arm_rms_q31( - q31_t * pSrc, - uint32_t blockSize, - q31_t * pResult); + void arm_rms_q31( + q31_t *pSrc, + uint32_t blockSize, + q31_t *pResult); - /** + /** * @brief Root Mean Square of the elements of a Q15 vector. * @param[in] *pSrc is input pointer * @param[in] blockSize is the number of samples to process @@ -6620,12 +6438,12 @@ void arm_rfft_fast_f32( * @return none. */ - void arm_rms_q15( - q15_t * pSrc, - uint32_t blockSize, - q15_t * pResult); + void arm_rms_q15( + q15_t *pSrc, + uint32_t blockSize, + q15_t *pResult); - /** + /** * @brief Standard deviation of the elements of a floating-point vector. * @param[in] *pSrc is input pointer * @param[in] blockSize is the number of samples to process @@ -6633,12 +6451,12 @@ void arm_rfft_fast_f32( * @return none. */ - void arm_std_f32( - float32_t * pSrc, - uint32_t blockSize, - float32_t * pResult); + void arm_std_f32( + float32_t *pSrc, + uint32_t blockSize, + float32_t *pResult); - /** + /** * @brief Standard deviation of the elements of a Q31 vector. * @param[in] *pSrc is input pointer * @param[in] blockSize is the number of samples to process @@ -6646,12 +6464,12 @@ void arm_rfft_fast_f32( * @return none. */ - void arm_std_q31( - q31_t * pSrc, - uint32_t blockSize, - q31_t * pResult); + void arm_std_q31( + q31_t *pSrc, + uint32_t blockSize, + q31_t *pResult); - /** + /** * @brief Standard deviation of the elements of a Q15 vector. * @param[in] *pSrc is input pointer * @param[in] blockSize is the number of samples to process @@ -6659,12 +6477,12 @@ void arm_rfft_fast_f32( * @return none. */ - void arm_std_q15( - q15_t * pSrc, - uint32_t blockSize, - q15_t * pResult); + void arm_std_q15( + q15_t *pSrc, + uint32_t blockSize, + q15_t *pResult); - /** + /** * @brief Floating-point complex magnitude * @param[in] *pSrc points to the complex input vector * @param[out] *pDst points to the real output vector @@ -6672,12 +6490,12 @@ void arm_rfft_fast_f32( * @return none. */ - void arm_cmplx_mag_f32( - float32_t * pSrc, - float32_t * pDst, - uint32_t numSamples); + void arm_cmplx_mag_f32( + float32_t *pSrc, + float32_t *pDst, + uint32_t numSamples); - /** + /** * @brief Q31 complex magnitude * @param[in] *pSrc points to the complex input vector * @param[out] *pDst points to the real output vector @@ -6685,12 +6503,12 @@ void arm_rfft_fast_f32( * @return none. */ - void arm_cmplx_mag_q31( - q31_t * pSrc, - q31_t * pDst, - uint32_t numSamples); + void arm_cmplx_mag_q31( + q31_t *pSrc, + q31_t *pDst, + uint32_t numSamples); - /** + /** * @brief Q15 complex magnitude * @param[in] *pSrc points to the complex input vector * @param[out] *pDst points to the real output vector @@ -6698,12 +6516,12 @@ void arm_rfft_fast_f32( * @return none. */ - void arm_cmplx_mag_q15( - q15_t * pSrc, - q15_t * pDst, - uint32_t numSamples); + void arm_cmplx_mag_q15( + q15_t *pSrc, + q15_t *pDst, + uint32_t numSamples); - /** + /** * @brief Q15 complex dot product * @param[in] *pSrcA points to the first input vector * @param[in] *pSrcB points to the second input vector @@ -6713,14 +6531,14 @@ void arm_rfft_fast_f32( * @return none. */ - void arm_cmplx_dot_prod_q15( - q15_t * pSrcA, - q15_t * pSrcB, - uint32_t numSamples, - q31_t * realResult, - q31_t * imagResult); + void arm_cmplx_dot_prod_q15( + q15_t *pSrcA, + q15_t *pSrcB, + uint32_t numSamples, + q31_t *realResult, + q31_t *imagResult); - /** + /** * @brief Q31 complex dot product * @param[in] *pSrcA points to the first input vector * @param[in] *pSrcB points to the second input vector @@ -6730,14 +6548,14 @@ void arm_rfft_fast_f32( * @return none. */ - void arm_cmplx_dot_prod_q31( - q31_t * pSrcA, - q31_t * pSrcB, - uint32_t numSamples, - q63_t * realResult, - q63_t * imagResult); + void arm_cmplx_dot_prod_q31( + q31_t *pSrcA, + q31_t *pSrcB, + uint32_t numSamples, + q63_t *realResult, + q63_t *imagResult); - /** + /** * @brief Floating-point complex dot product * @param[in] *pSrcA points to the first input vector * @param[in] *pSrcB points to the second input vector @@ -6747,14 +6565,14 @@ void arm_rfft_fast_f32( * @return none. */ - void arm_cmplx_dot_prod_f32( - float32_t * pSrcA, - float32_t * pSrcB, - uint32_t numSamples, - float32_t * realResult, - float32_t * imagResult); + void arm_cmplx_dot_prod_f32( + float32_t *pSrcA, + float32_t *pSrcB, + uint32_t numSamples, + float32_t *realResult, + float32_t *imagResult); - /** + /** * @brief Q15 complex-by-real multiplication * @param[in] *pSrcCmplx points to the complex input vector * @param[in] *pSrcReal points to the real input vector @@ -6763,13 +6581,13 @@ void arm_rfft_fast_f32( * @return none. */ - void arm_cmplx_mult_real_q15( - q15_t * pSrcCmplx, - q15_t * pSrcReal, - q15_t * pCmplxDst, - uint32_t numSamples); + void arm_cmplx_mult_real_q15( + q15_t *pSrcCmplx, + q15_t *pSrcReal, + q15_t *pCmplxDst, + uint32_t numSamples); - /** + /** * @brief Q31 complex-by-real multiplication * @param[in] *pSrcCmplx points to the complex input vector * @param[in] *pSrcReal points to the real input vector @@ -6778,13 +6596,13 @@ void arm_rfft_fast_f32( * @return none. */ - void arm_cmplx_mult_real_q31( - q31_t * pSrcCmplx, - q31_t * pSrcReal, - q31_t * pCmplxDst, - uint32_t numSamples); + void arm_cmplx_mult_real_q31( + q31_t *pSrcCmplx, + q31_t *pSrcReal, + q31_t *pCmplxDst, + uint32_t numSamples); - /** + /** * @brief Floating-point complex-by-real multiplication * @param[in] *pSrcCmplx points to the complex input vector * @param[in] *pSrcReal points to the real input vector @@ -6793,13 +6611,13 @@ void arm_rfft_fast_f32( * @return none. */ - void arm_cmplx_mult_real_f32( - float32_t * pSrcCmplx, - float32_t * pSrcReal, - float32_t * pCmplxDst, - uint32_t numSamples); + void arm_cmplx_mult_real_f32( + float32_t *pSrcCmplx, + float32_t *pSrcReal, + float32_t *pCmplxDst, + uint32_t numSamples); - /** + /** * @brief Minimum value of a Q7 vector. * @param[in] *pSrc is input pointer * @param[in] blockSize is the number of samples to process @@ -6808,13 +6626,13 @@ void arm_rfft_fast_f32( * @return none. */ - void arm_min_q7( - q7_t * pSrc, - uint32_t blockSize, - q7_t * result, - uint32_t * index); + void arm_min_q7( + q7_t *pSrc, + uint32_t blockSize, + q7_t *result, + uint32_t *index); - /** + /** * @brief Minimum value of a Q15 vector. * @param[in] *pSrc is input pointer * @param[in] blockSize is the number of samples to process @@ -6823,13 +6641,13 @@ void arm_rfft_fast_f32( * @return none. */ - void arm_min_q15( - q15_t * pSrc, - uint32_t blockSize, - q15_t * pResult, - uint32_t * pIndex); + void arm_min_q15( + q15_t *pSrc, + uint32_t blockSize, + q15_t *pResult, + uint32_t *pIndex); - /** + /** * @brief Minimum value of a Q31 vector. * @param[in] *pSrc is input pointer * @param[in] blockSize is the number of samples to process @@ -6837,13 +6655,13 @@ void arm_rfft_fast_f32( * @param[out] *pIndex is the array index of the minimum value in the input buffer. * @return none. */ - void arm_min_q31( - q31_t * pSrc, - uint32_t blockSize, - q31_t * pResult, - uint32_t * pIndex); + void arm_min_q31( + q31_t *pSrc, + uint32_t blockSize, + q31_t *pResult, + uint32_t *pIndex); - /** + /** * @brief Minimum value of a floating-point vector. * @param[in] *pSrc is input pointer * @param[in] blockSize is the number of samples to process @@ -6852,13 +6670,13 @@ void arm_rfft_fast_f32( * @return none. */ - void arm_min_f32( - float32_t * pSrc, - uint32_t blockSize, - float32_t * pResult, - uint32_t * pIndex); + void arm_min_f32( + float32_t *pSrc, + uint32_t blockSize, + float32_t *pResult, + uint32_t *pIndex); -/** + /** * @brief Maximum value of a Q7 vector. * @param[in] *pSrc points to the input buffer * @param[in] blockSize length of the input vector @@ -6867,13 +6685,13 @@ void arm_rfft_fast_f32( * @return none. */ - void arm_max_q7( - q7_t * pSrc, - uint32_t blockSize, - q7_t * pResult, - uint32_t * pIndex); + void arm_max_q7( + q7_t *pSrc, + uint32_t blockSize, + q7_t *pResult, + uint32_t *pIndex); -/** + /** * @brief Maximum value of a Q15 vector. * @param[in] *pSrc points to the input buffer * @param[in] blockSize length of the input vector @@ -6882,13 +6700,13 @@ void arm_rfft_fast_f32( * @return none. */ - void arm_max_q15( - q15_t * pSrc, - uint32_t blockSize, - q15_t * pResult, - uint32_t * pIndex); + void arm_max_q15( + q15_t *pSrc, + uint32_t blockSize, + q15_t *pResult, + uint32_t *pIndex); -/** + /** * @brief Maximum value of a Q31 vector. * @param[in] *pSrc points to the input buffer * @param[in] blockSize length of the input vector @@ -6897,13 +6715,13 @@ void arm_rfft_fast_f32( * @return none. */ - void arm_max_q31( - q31_t * pSrc, - uint32_t blockSize, - q31_t * pResult, - uint32_t * pIndex); + void arm_max_q31( + q31_t *pSrc, + uint32_t blockSize, + q31_t *pResult, + uint32_t *pIndex); -/** + /** * @brief Maximum value of a floating-point vector. * @param[in] *pSrc points to the input buffer * @param[in] blockSize length of the input vector @@ -6912,13 +6730,13 @@ void arm_rfft_fast_f32( * @return none. */ - void arm_max_f32( - float32_t * pSrc, - uint32_t blockSize, - float32_t * pResult, - uint32_t * pIndex); + void arm_max_f32( + float32_t *pSrc, + uint32_t blockSize, + float32_t *pResult, + uint32_t *pIndex); - /** + /** * @brief Q15 complex-by-complex multiplication * @param[in] *pSrcA points to the first input vector * @param[in] *pSrcB points to the second input vector @@ -6927,13 +6745,13 @@ void arm_rfft_fast_f32( * @return none. */ - void arm_cmplx_mult_cmplx_q15( - q15_t * pSrcA, - q15_t * pSrcB, - q15_t * pDst, - uint32_t numSamples); + void arm_cmplx_mult_cmplx_q15( + q15_t *pSrcA, + q15_t *pSrcB, + q15_t *pDst, + uint32_t numSamples); - /** + /** * @brief Q31 complex-by-complex multiplication * @param[in] *pSrcA points to the first input vector * @param[in] *pSrcB points to the second input vector @@ -6942,13 +6760,13 @@ void arm_rfft_fast_f32( * @return none. */ - void arm_cmplx_mult_cmplx_q31( - q31_t * pSrcA, - q31_t * pSrcB, - q31_t * pDst, - uint32_t numSamples); + void arm_cmplx_mult_cmplx_q31( + q31_t *pSrcA, + q31_t *pSrcB, + q31_t *pDst, + uint32_t numSamples); - /** + /** * @brief Floating-point complex-by-complex multiplication * @param[in] *pSrcA points to the first input vector * @param[in] *pSrcB points to the second input vector @@ -6957,117 +6775,113 @@ void arm_rfft_fast_f32( * @return none. */ - void arm_cmplx_mult_cmplx_f32( - float32_t * pSrcA, - float32_t * pSrcB, - float32_t * pDst, - uint32_t numSamples); + void arm_cmplx_mult_cmplx_f32( + float32_t *pSrcA, + float32_t *pSrcB, + float32_t *pDst, + uint32_t numSamples); - /** + /** * @brief Converts the elements of the floating-point vector to Q31 vector. * @param[in] *pSrc points to the floating-point input vector * @param[out] *pDst points to the Q31 output vector * @param[in] blockSize length of the input vector * @return none. */ - void arm_float_to_q31( - float32_t * pSrc, - q31_t * pDst, - uint32_t blockSize); + void arm_float_to_q31( + float32_t *pSrc, + q31_t *pDst, + uint32_t blockSize); - /** + /** * @brief Converts the elements of the floating-point vector to Q15 vector. * @param[in] *pSrc points to the floating-point input vector * @param[out] *pDst points to the Q15 output vector * @param[in] blockSize length of the input vector * @return none */ - void arm_float_to_q15( - float32_t * pSrc, - q15_t * pDst, - uint32_t blockSize); + void arm_float_to_q15( + float32_t *pSrc, + q15_t *pDst, + uint32_t blockSize); - /** + /** * @brief Converts the elements of the floating-point vector to Q7 vector. * @param[in] *pSrc points to the floating-point input vector * @param[out] *pDst points to the Q7 output vector * @param[in] blockSize length of the input vector * @return none */ - void arm_float_to_q7( - float32_t * pSrc, - q7_t * pDst, - uint32_t blockSize); - + void arm_float_to_q7( + float32_t *pSrc, + q7_t *pDst, + uint32_t blockSize); - /** + /** * @brief Converts the elements of the Q31 vector to Q15 vector. * @param[in] *pSrc is input pointer * @param[out] *pDst is output pointer * @param[in] blockSize is the number of samples to process * @return none. */ - void arm_q31_to_q15( - q31_t * pSrc, - q15_t * pDst, - uint32_t blockSize); + void arm_q31_to_q15( + q31_t *pSrc, + q15_t *pDst, + uint32_t blockSize); - /** + /** * @brief Converts the elements of the Q31 vector to Q7 vector. * @param[in] *pSrc is input pointer * @param[out] *pDst is output pointer * @param[in] blockSize is the number of samples to process * @return none. */ - void arm_q31_to_q7( - q31_t * pSrc, - q7_t * pDst, - uint32_t blockSize); + void arm_q31_to_q7( + q31_t *pSrc, + q7_t *pDst, + uint32_t blockSize); - /** + /** * @brief Converts the elements of the Q15 vector to floating-point vector. * @param[in] *pSrc is input pointer * @param[out] *pDst is output pointer * @param[in] blockSize is the number of samples to process * @return none. */ - void arm_q15_to_float( - q15_t * pSrc, - float32_t * pDst, - uint32_t blockSize); - + void arm_q15_to_float( + q15_t *pSrc, + float32_t *pDst, + uint32_t blockSize); - /** + /** * @brief Converts the elements of the Q15 vector to Q31 vector. * @param[in] *pSrc is input pointer * @param[out] *pDst is output pointer * @param[in] blockSize is the number of samples to process * @return none. */ - void arm_q15_to_q31( - q15_t * pSrc, - q31_t * pDst, - uint32_t blockSize); - + void arm_q15_to_q31( + q15_t *pSrc, + q31_t *pDst, + uint32_t blockSize); - /** + /** * @brief Converts the elements of the Q15 vector to Q7 vector. * @param[in] *pSrc is input pointer * @param[out] *pDst is output pointer * @param[in] blockSize is the number of samples to process * @return none. */ - void arm_q15_to_q7( - q15_t * pSrc, - q7_t * pDst, - uint32_t blockSize); + void arm_q15_to_q7( + q15_t *pSrc, + q7_t *pDst, + uint32_t blockSize); - - /** + /** * @ingroup groupInterpolation */ - /** + /** * @defgroup BilinearInterpolate Bilinear Interpolation * * Bilinear interpolation is an extension of linear interpolation applied to a two dimensional grid. @@ -7119,12 +6933,12 @@ void arm_rfft_fast_f32( * if (x,y) are outside of the table boundary, Bilinear interpolation returns zero output. */ - /** + /** * @addtogroup BilinearInterpolate * @{ */ - /** + /** * * @brief Floating-point bilinear interpolation. * @param[in,out] *S points to an instance of the interpolation structure. @@ -7133,67 +6947,62 @@ void arm_rfft_fast_f32( * @return out interpolated value. */ - - static __INLINE float32_t arm_bilinear_interp_f32( - const arm_bilinear_interp_instance_f32 * S, - float32_t X, - float32_t Y) - { - float32_t out; - float32_t f00, f01, f10, f11; - float32_t *pData = S->pData; - int32_t xIndex, yIndex, index; - float32_t xdiff, ydiff; - float32_t b1, b2, b3, b4; - - xIndex = (int32_t) X; - yIndex = (int32_t) Y; - - /* Care taken for table outside boundary */ - /* Returns zero output when values are outside table boundary */ - if(xIndex < 0 || xIndex > (S->numRows - 1) || yIndex < 0 - || yIndex > (S->numCols - 1)) + static __INLINE float32_t arm_bilinear_interp_f32( + const arm_bilinear_interp_instance_f32 *S, + float32_t X, + float32_t Y) { - return (0); + float32_t out; + float32_t f00, f01, f10, f11; + float32_t *pData = S->pData; + int32_t xIndex, yIndex, index; + float32_t xdiff, ydiff; + float32_t b1, b2, b3, b4; + + xIndex = (int32_t)X; + yIndex = (int32_t)Y; + + /* Care taken for table outside boundary */ + /* Returns zero output when values are outside table boundary */ + if (xIndex < 0 || xIndex > (S->numRows - 1) || yIndex < 0 || yIndex > (S->numCols - 1)) + { + return (0); + } + + /* Calculation of index for two nearest points in X-direction */ + index = (xIndex - 1) + (yIndex - 1) * S->numCols; + + /* Read two nearest points in X-direction */ + f00 = pData[index]; + f01 = pData[index + 1]; + + /* Calculation of index for two nearest points in Y-direction */ + index = (xIndex - 1) + (yIndex)*S->numCols; + + /* Read two nearest points in Y-direction */ + f10 = pData[index]; + f11 = pData[index + 1]; + + /* Calculation of intermediate values */ + b1 = f00; + b2 = f01 - f00; + b3 = f10 - f00; + b4 = f00 - f01 - f10 + f11; + + /* Calculation of fractional part in X */ + xdiff = X - xIndex; + + /* Calculation of fractional part in Y */ + ydiff = Y - yIndex; + + /* Calculation of bi-linear interpolated output */ + out = b1 + b2 * xdiff + b3 * ydiff + b4 * xdiff * ydiff; + + /* return to application */ + return (out); } - /* Calculation of index for two nearest points in X-direction */ - index = (xIndex - 1) + (yIndex - 1) * S->numCols; - - - /* Read two nearest points in X-direction */ - f00 = pData[index]; - f01 = pData[index + 1]; - - /* Calculation of index for two nearest points in Y-direction */ - index = (xIndex - 1) + (yIndex) * S->numCols; - - - /* Read two nearest points in Y-direction */ - f10 = pData[index]; - f11 = pData[index + 1]; - - /* Calculation of intermediate values */ - b1 = f00; - b2 = f01 - f00; - b3 = f10 - f00; - b4 = f00 - f01 - f10 + f11; - - /* Calculation of fractional part in X */ - xdiff = X - xIndex; - - /* Calculation of fractional part in Y */ - ydiff = Y - yIndex; - - /* Calculation of bi-linear interpolated output */ - out = b1 + b2 * xdiff + b3 * ydiff + b4 * xdiff * ydiff; - - /* return to application */ - return (out); - - } - - /** + /** * * @brief Q31 bilinear interpolation. * @param[in,out] *S points to an instance of the interpolation structure. @@ -7202,75 +7011,73 @@ void arm_rfft_fast_f32( * @return out interpolated value. */ - static __INLINE q31_t arm_bilinear_interp_q31( - arm_bilinear_interp_instance_q31 * S, - q31_t X, - q31_t Y) - { - q31_t out; /* Temporary output */ - q31_t acc = 0; /* output */ - q31_t xfract, yfract; /* X, Y fractional parts */ - q31_t x1, x2, y1, y2; /* Nearest output values */ - int32_t rI, cI; /* Row and column indices */ - q31_t *pYData = S->pData; /* pointer to output table values */ - uint32_t nCols = S->numCols; /* num of rows */ - - - /* Input is in 12.20 format */ - /* 12 bits for the table index */ - /* Index value calculation */ - rI = ((X & 0xFFF00000) >> 20u); - - /* Input is in 12.20 format */ - /* 12 bits for the table index */ - /* Index value calculation */ - cI = ((Y & 0xFFF00000) >> 20u); - - /* Care taken for table outside boundary */ - /* Returns zero output when values are outside table boundary */ - if(rI < 0 || rI > (S->numRows - 1) || cI < 0 || cI > (S->numCols - 1)) + static __INLINE q31_t arm_bilinear_interp_q31( + arm_bilinear_interp_instance_q31 *S, + q31_t X, + q31_t Y) { - return (0); + q31_t out; /* Temporary output */ + q31_t acc = 0; /* output */ + q31_t xfract, yfract; /* X, Y fractional parts */ + q31_t x1, x2, y1, y2; /* Nearest output values */ + int32_t rI, cI; /* Row and column indices */ + q31_t *pYData = S->pData; /* pointer to output table values */ + uint32_t nCols = S->numCols; /* num of rows */ + + /* Input is in 12.20 format */ + /* 12 bits for the table index */ + /* Index value calculation */ + rI = ((X & 0xFFF00000) >> 20u); + + /* Input is in 12.20 format */ + /* 12 bits for the table index */ + /* Index value calculation */ + cI = ((Y & 0xFFF00000) >> 20u); + + /* Care taken for table outside boundary */ + /* Returns zero output when values are outside table boundary */ + if (rI < 0 || rI > (S->numRows - 1) || cI < 0 || cI > (S->numCols - 1)) + { + return (0); + } + + /* 20 bits for the fractional part */ + /* shift left xfract by 11 to keep 1.31 format */ + xfract = (X & 0x000FFFFF) << 11u; + + /* Read two nearest output values from the index */ + x1 = pYData[(rI) + nCols * (cI)]; + x2 = pYData[(rI) + nCols * (cI) + 1u]; + + /* 20 bits for the fractional part */ + /* shift left yfract by 11 to keep 1.31 format */ + yfract = (Y & 0x000FFFFF) << 11u; + + /* Read two nearest output values from the index */ + y1 = pYData[(rI) + nCols * (cI + 1)]; + y2 = pYData[(rI) + nCols * (cI + 1) + 1u]; + + /* Calculation of x1 * (1-xfract ) * (1-yfract) and acc is in 3.29(q29) format */ + out = ((q31_t)(((q63_t)x1 * (0x7FFFFFFF - xfract)) >> 32)); + acc = ((q31_t)(((q63_t)out * (0x7FFFFFFF - yfract)) >> 32)); + + /* x2 * (xfract) * (1-yfract) in 3.29(q29) and adding to acc */ + out = ((q31_t)((q63_t)x2 * (0x7FFFFFFF - yfract) >> 32)); + acc += ((q31_t)((q63_t)out * (xfract) >> 32)); + + /* y1 * (1 - xfract) * (yfract) in 3.29(q29) and adding to acc */ + out = ((q31_t)((q63_t)y1 * (0x7FFFFFFF - xfract) >> 32)); + acc += ((q31_t)((q63_t)out * (yfract) >> 32)); + + /* y2 * (xfract) * (yfract) in 3.29(q29) and adding to acc */ + out = ((q31_t)((q63_t)y2 * (xfract) >> 32)); + acc += ((q31_t)((q63_t)out * (yfract) >> 32)); + + /* Convert acc to 1.31(q31) format */ + return (acc << 2u); } - /* 20 bits for the fractional part */ - /* shift left xfract by 11 to keep 1.31 format */ - xfract = (X & 0x000FFFFF) << 11u; - - /* Read two nearest output values from the index */ - x1 = pYData[(rI) + nCols * (cI)]; - x2 = pYData[(rI) + nCols * (cI) + 1u]; - - /* 20 bits for the fractional part */ - /* shift left yfract by 11 to keep 1.31 format */ - yfract = (Y & 0x000FFFFF) << 11u; - - /* Read two nearest output values from the index */ - y1 = pYData[(rI) + nCols * (cI + 1)]; - y2 = pYData[(rI) + nCols * (cI + 1) + 1u]; - - /* Calculation of x1 * (1-xfract ) * (1-yfract) and acc is in 3.29(q29) format */ - out = ((q31_t) (((q63_t) x1 * (0x7FFFFFFF - xfract)) >> 32)); - acc = ((q31_t) (((q63_t) out * (0x7FFFFFFF - yfract)) >> 32)); - - /* x2 * (xfract) * (1-yfract) in 3.29(q29) and adding to acc */ - out = ((q31_t) ((q63_t) x2 * (0x7FFFFFFF - yfract) >> 32)); - acc += ((q31_t) ((q63_t) out * (xfract) >> 32)); - - /* y1 * (1 - xfract) * (yfract) in 3.29(q29) and adding to acc */ - out = ((q31_t) ((q63_t) y1 * (0x7FFFFFFF - xfract) >> 32)); - acc += ((q31_t) ((q63_t) out * (yfract) >> 32)); - - /* y2 * (xfract) * (yfract) in 3.29(q29) and adding to acc */ - out = ((q31_t) ((q63_t) y2 * (xfract) >> 32)); - acc += ((q31_t) ((q63_t) out * (yfract) >> 32)); - - /* Convert acc to 1.31(q31) format */ - return (acc << 2u); - - } - - /** + /** * @brief Q15 bilinear interpolation. * @param[in,out] *S points to an instance of the interpolation structure. * @param[in] X interpolation coordinate in 12.20 format. @@ -7278,79 +7085,77 @@ void arm_rfft_fast_f32( * @return out interpolated value. */ - static __INLINE q15_t arm_bilinear_interp_q15( - arm_bilinear_interp_instance_q15 * S, - q31_t X, - q31_t Y) - { - q63_t acc = 0; /* output */ - q31_t out; /* Temporary output */ - q15_t x1, x2, y1, y2; /* Nearest output values */ - q31_t xfract, yfract; /* X, Y fractional parts */ - int32_t rI, cI; /* Row and column indices */ - q15_t *pYData = S->pData; /* pointer to output table values */ - uint32_t nCols = S->numCols; /* num of rows */ - - /* Input is in 12.20 format */ - /* 12 bits for the table index */ - /* Index value calculation */ - rI = ((X & 0xFFF00000) >> 20); - - /* Input is in 12.20 format */ - /* 12 bits for the table index */ - /* Index value calculation */ - cI = ((Y & 0xFFF00000) >> 20); - - /* Care taken for table outside boundary */ - /* Returns zero output when values are outside table boundary */ - if(rI < 0 || rI > (S->numRows - 1) || cI < 0 || cI > (S->numCols - 1)) + static __INLINE q15_t arm_bilinear_interp_q15( + arm_bilinear_interp_instance_q15 *S, + q31_t X, + q31_t Y) { - return (0); + q63_t acc = 0; /* output */ + q31_t out; /* Temporary output */ + q15_t x1, x2, y1, y2; /* Nearest output values */ + q31_t xfract, yfract; /* X, Y fractional parts */ + int32_t rI, cI; /* Row and column indices */ + q15_t *pYData = S->pData; /* pointer to output table values */ + uint32_t nCols = S->numCols; /* num of rows */ + + /* Input is in 12.20 format */ + /* 12 bits for the table index */ + /* Index value calculation */ + rI = ((X & 0xFFF00000) >> 20); + + /* Input is in 12.20 format */ + /* 12 bits for the table index */ + /* Index value calculation */ + cI = ((Y & 0xFFF00000) >> 20); + + /* Care taken for table outside boundary */ + /* Returns zero output when values are outside table boundary */ + if (rI < 0 || rI > (S->numRows - 1) || cI < 0 || cI > (S->numCols - 1)) + { + return (0); + } + + /* 20 bits for the fractional part */ + /* xfract should be in 12.20 format */ + xfract = (X & 0x000FFFFF); + + /* Read two nearest output values from the index */ + x1 = pYData[(rI) + nCols * (cI)]; + x2 = pYData[(rI) + nCols * (cI) + 1u]; + + /* 20 bits for the fractional part */ + /* yfract should be in 12.20 format */ + yfract = (Y & 0x000FFFFF); + + /* Read two nearest output values from the index */ + y1 = pYData[(rI) + nCols * (cI + 1)]; + y2 = pYData[(rI) + nCols * (cI + 1) + 1u]; + + /* Calculation of x1 * (1-xfract ) * (1-yfract) and acc is in 13.51 format */ + + /* x1 is in 1.15(q15), xfract in 12.20 format and out is in 13.35 format */ + /* convert 13.35 to 13.31 by right shifting and out is in 1.31 */ + out = (q31_t)(((q63_t)x1 * (0xFFFFF - xfract)) >> 4u); + acc = ((q63_t)out * (0xFFFFF - yfract)); + + /* x2 * (xfract) * (1-yfract) in 1.51 and adding to acc */ + out = (q31_t)(((q63_t)x2 * (0xFFFFF - yfract)) >> 4u); + acc += ((q63_t)out * (xfract)); + + /* y1 * (1 - xfract) * (yfract) in 1.51 and adding to acc */ + out = (q31_t)(((q63_t)y1 * (0xFFFFF - xfract)) >> 4u); + acc += ((q63_t)out * (yfract)); + + /* y2 * (xfract) * (yfract) in 1.51 and adding to acc */ + out = (q31_t)(((q63_t)y2 * (xfract)) >> 4u); + acc += ((q63_t)out * (yfract)); + + /* acc is in 13.51 format and down shift acc by 36 times */ + /* Convert out to 1.15 format */ + return (acc >> 36); } - /* 20 bits for the fractional part */ - /* xfract should be in 12.20 format */ - xfract = (X & 0x000FFFFF); - - /* Read two nearest output values from the index */ - x1 = pYData[(rI) + nCols * (cI)]; - x2 = pYData[(rI) + nCols * (cI) + 1u]; - - - /* 20 bits for the fractional part */ - /* yfract should be in 12.20 format */ - yfract = (Y & 0x000FFFFF); - - /* Read two nearest output values from the index */ - y1 = pYData[(rI) + nCols * (cI + 1)]; - y2 = pYData[(rI) + nCols * (cI + 1) + 1u]; - - /* Calculation of x1 * (1-xfract ) * (1-yfract) and acc is in 13.51 format */ - - /* x1 is in 1.15(q15), xfract in 12.20 format and out is in 13.35 format */ - /* convert 13.35 to 13.31 by right shifting and out is in 1.31 */ - out = (q31_t) (((q63_t) x1 * (0xFFFFF - xfract)) >> 4u); - acc = ((q63_t) out * (0xFFFFF - yfract)); - - /* x2 * (xfract) * (1-yfract) in 1.51 and adding to acc */ - out = (q31_t) (((q63_t) x2 * (0xFFFFF - yfract)) >> 4u); - acc += ((q63_t) out * (xfract)); - - /* y1 * (1 - xfract) * (yfract) in 1.51 and adding to acc */ - out = (q31_t) (((q63_t) y1 * (0xFFFFF - xfract)) >> 4u); - acc += ((q63_t) out * (yfract)); - - /* y2 * (xfract) * (yfract) in 1.51 and adding to acc */ - out = (q31_t) (((q63_t) y2 * (xfract)) >> 4u); - acc += ((q63_t) out * (yfract)); - - /* acc is in 13.51 format and down shift acc by 36 times */ - /* Convert out to 1.15 format */ - return (acc >> 36); - - } - - /** + /** * @brief Q7 bilinear interpolation. * @param[in,out] *S points to an instance of the interpolation structure. * @param[in] X interpolation coordinate in 12.20 format. @@ -7358,164 +7163,160 @@ void arm_rfft_fast_f32( * @return out interpolated value. */ - static __INLINE q7_t arm_bilinear_interp_q7( - arm_bilinear_interp_instance_q7 * S, - q31_t X, - q31_t Y) - { - q63_t acc = 0; /* output */ - q31_t out; /* Temporary output */ - q31_t xfract, yfract; /* X, Y fractional parts */ - q7_t x1, x2, y1, y2; /* Nearest output values */ - int32_t rI, cI; /* Row and column indices */ - q7_t *pYData = S->pData; /* pointer to output table values */ - uint32_t nCols = S->numCols; /* num of rows */ - - /* Input is in 12.20 format */ - /* 12 bits for the table index */ - /* Index value calculation */ - rI = ((X & 0xFFF00000) >> 20); - - /* Input is in 12.20 format */ - /* 12 bits for the table index */ - /* Index value calculation */ - cI = ((Y & 0xFFF00000) >> 20); - - /* Care taken for table outside boundary */ - /* Returns zero output when values are outside table boundary */ - if(rI < 0 || rI > (S->numRows - 1) || cI < 0 || cI > (S->numCols - 1)) + static __INLINE q7_t arm_bilinear_interp_q7( + arm_bilinear_interp_instance_q7 *S, + q31_t X, + q31_t Y) { - return (0); + q63_t acc = 0; /* output */ + q31_t out; /* Temporary output */ + q31_t xfract, yfract; /* X, Y fractional parts */ + q7_t x1, x2, y1, y2; /* Nearest output values */ + int32_t rI, cI; /* Row and column indices */ + q7_t *pYData = S->pData; /* pointer to output table values */ + uint32_t nCols = S->numCols; /* num of rows */ + + /* Input is in 12.20 format */ + /* 12 bits for the table index */ + /* Index value calculation */ + rI = ((X & 0xFFF00000) >> 20); + + /* Input is in 12.20 format */ + /* 12 bits for the table index */ + /* Index value calculation */ + cI = ((Y & 0xFFF00000) >> 20); + + /* Care taken for table outside boundary */ + /* Returns zero output when values are outside table boundary */ + if (rI < 0 || rI > (S->numRows - 1) || cI < 0 || cI > (S->numCols - 1)) + { + return (0); + } + + /* 20 bits for the fractional part */ + /* xfract should be in 12.20 format */ + xfract = (X & 0x000FFFFF); + + /* Read two nearest output values from the index */ + x1 = pYData[(rI) + nCols * (cI)]; + x2 = pYData[(rI) + nCols * (cI) + 1u]; + + /* 20 bits for the fractional part */ + /* yfract should be in 12.20 format */ + yfract = (Y & 0x000FFFFF); + + /* Read two nearest output values from the index */ + y1 = pYData[(rI) + nCols * (cI + 1)]; + y2 = pYData[(rI) + nCols * (cI + 1) + 1u]; + + /* Calculation of x1 * (1-xfract ) * (1-yfract) and acc is in 16.47 format */ + out = ((x1 * (0xFFFFF - xfract))); + acc = (((q63_t)out * (0xFFFFF - yfract))); + + /* x2 * (xfract) * (1-yfract) in 2.22 and adding to acc */ + out = ((x2 * (0xFFFFF - yfract))); + acc += (((q63_t)out * (xfract))); + + /* y1 * (1 - xfract) * (yfract) in 2.22 and adding to acc */ + out = ((y1 * (0xFFFFF - xfract))); + acc += (((q63_t)out * (yfract))); + + /* y2 * (xfract) * (yfract) in 2.22 and adding to acc */ + out = ((y2 * (yfract))); + acc += (((q63_t)out * (xfract))); + + /* acc in 16.47 format and down shift by 40 to convert to 1.7 format */ + return (acc >> 40); } - /* 20 bits for the fractional part */ - /* xfract should be in 12.20 format */ - xfract = (X & 0x000FFFFF); - - /* Read two nearest output values from the index */ - x1 = pYData[(rI) + nCols * (cI)]; - x2 = pYData[(rI) + nCols * (cI) + 1u]; - - - /* 20 bits for the fractional part */ - /* yfract should be in 12.20 format */ - yfract = (Y & 0x000FFFFF); - - /* Read two nearest output values from the index */ - y1 = pYData[(rI) + nCols * (cI + 1)]; - y2 = pYData[(rI) + nCols * (cI + 1) + 1u]; - - /* Calculation of x1 * (1-xfract ) * (1-yfract) and acc is in 16.47 format */ - out = ((x1 * (0xFFFFF - xfract))); - acc = (((q63_t) out * (0xFFFFF - yfract))); - - /* x2 * (xfract) * (1-yfract) in 2.22 and adding to acc */ - out = ((x2 * (0xFFFFF - yfract))); - acc += (((q63_t) out * (xfract))); - - /* y1 * (1 - xfract) * (yfract) in 2.22 and adding to acc */ - out = ((y1 * (0xFFFFF - xfract))); - acc += (((q63_t) out * (yfract))); - - /* y2 * (xfract) * (yfract) in 2.22 and adding to acc */ - out = ((y2 * (yfract))); - acc += (((q63_t) out * (xfract))); - - /* acc in 16.47 format and down shift by 40 to convert to 1.7 format */ - return (acc >> 40); - - } - - /** + /** * @} end of BilinearInterpolate group */ - //SMMLAR #define multAcc_32x32_keep32_R(a, x, y) \ - a = (q31_t) (((((q63_t) a) << 32) + ((q63_t) x * y) + 0x80000000LL ) >> 32) + a = (q31_t)(((((q63_t)a) << 32) + ((q63_t)x * y) + 0x80000000LL) >> 32) //SMMLSR #define multSub_32x32_keep32_R(a, x, y) \ - a = (q31_t) (((((q63_t) a) << 32) - ((q63_t) x * y) + 0x80000000LL ) >> 32) + a = (q31_t)(((((q63_t)a) << 32) - ((q63_t)x * y) + 0x80000000LL) >> 32) //SMMULR #define mult_32x32_keep32_R(a, x, y) \ - a = (q31_t) (((q63_t) x * y + 0x80000000LL ) >> 32) + a = (q31_t)(((q63_t)x * y + 0x80000000LL) >> 32) //SMMLA #define multAcc_32x32_keep32(a, x, y) \ - a += (q31_t) (((q63_t) x * y) >> 32) + a += (q31_t)(((q63_t)x * y) >> 32) //SMMLS #define multSub_32x32_keep32(a, x, y) \ - a -= (q31_t) (((q63_t) x * y) >> 32) + a -= (q31_t)(((q63_t)x * y) >> 32) //SMMUL #define mult_32x32_keep32(a, x, y) \ - a = (q31_t) (((q63_t) x * y ) >> 32) - + a = (q31_t)(((q63_t)x * y) >> 32) -#if defined ( __CC_ARM ) //Keil +#if defined(__CC_ARM) //Keil -//Enter low optimization region - place directly above function definition - #ifdef ARM_MATH_CM4 - #define LOW_OPTIMIZATION_ENTER \ - _Pragma ("push") \ - _Pragma ("O1") - #else - #define LOW_OPTIMIZATION_ENTER - #endif + //Enter low optimization region - place directly above function definition +#ifdef ARM_MATH_CM4 +#define LOW_OPTIMIZATION_ENTER \ + _Pragma("push") \ + _Pragma("O1") +#else +#define LOW_OPTIMIZATION_ENTER +#endif -//Exit low optimization region - place directly after end of function definition - #ifdef ARM_MATH_CM4 - #define LOW_OPTIMIZATION_EXIT \ - _Pragma ("pop") - #else - #define LOW_OPTIMIZATION_EXIT - #endif + //Exit low optimization region - place directly after end of function definition +#ifdef ARM_MATH_CM4 +#define LOW_OPTIMIZATION_EXIT \ + _Pragma("pop") +#else +#define LOW_OPTIMIZATION_EXIT +#endif -//Enter low optimization region - place directly above function definition - #define IAR_ONLY_LOW_OPTIMIZATION_ENTER + //Enter low optimization region - place directly above function definition +#define IAR_ONLY_LOW_OPTIMIZATION_ENTER -//Exit low optimization region - place directly after end of function definition - #define IAR_ONLY_LOW_OPTIMIZATION_EXIT + //Exit low optimization region - place directly after end of function definition +#define IAR_ONLY_LOW_OPTIMIZATION_EXIT #elif defined(__ICCARM__) //IAR //Enter low optimization region - place directly above function definition - #ifdef ARM_MATH_CM4 - #define LOW_OPTIMIZATION_ENTER \ - _Pragma ("optimize=low") - #else - #define LOW_OPTIMIZATION_ENTER - #endif +#ifdef ARM_MATH_CM4 +#define LOW_OPTIMIZATION_ENTER \ + _Pragma("optimize=low") +#else +#define LOW_OPTIMIZATION_ENTER +#endif //Exit low optimization region - place directly after end of function definition - #define LOW_OPTIMIZATION_EXIT +#define LOW_OPTIMIZATION_EXIT //Enter low optimization region - place directly above function definition - #ifdef ARM_MATH_CM4 - #define IAR_ONLY_LOW_OPTIMIZATION_ENTER \ - _Pragma ("optimize=low") - #else - #define IAR_ONLY_LOW_OPTIMIZATION_ENTER - #endif +#ifdef ARM_MATH_CM4 +#define IAR_ONLY_LOW_OPTIMIZATION_ENTER \ + _Pragma("optimize=low") +#else +#define IAR_ONLY_LOW_OPTIMIZATION_ENTER +#endif //Exit low optimization region - place directly after end of function definition - #define IAR_ONLY_LOW_OPTIMIZATION_EXIT +#define IAR_ONLY_LOW_OPTIMIZATION_EXIT #elif defined(__GNUC__) - #define LOW_OPTIMIZATION_ENTER __attribute__(( optimize("-O1") )) +#define LOW_OPTIMIZATION_ENTER __attribute__((optimize("-O1"))) - #define LOW_OPTIMIZATION_EXIT +#define LOW_OPTIMIZATION_EXIT - #define IAR_ONLY_LOW_OPTIMIZATION_ENTER +#define IAR_ONLY_LOW_OPTIMIZATION_ENTER - #define IAR_ONLY_LOW_OPTIMIZATION_EXIT +#define IAR_ONLY_LOW_OPTIMIZATION_EXIT -#elif defined(__CSMC__) // Cosmic +#elif defined(__CSMC__) // Cosmic #define LOW_OPTIMIZATION_ENTER #define LOW_OPTIMIZATION_EXIT @@ -7524,12 +7325,10 @@ void arm_rfft_fast_f32( #endif - -#ifdef __cplusplus +#ifdef __cplusplus } #endif - #endif /* _ARM_MATH_H */ /** diff --git a/bsp/swm320-lq100/Libraries/CMSIS/CoreSupport/core_cm0.h b/bsp/swm320-lq100/Libraries/CMSIS/CoreSupport/core_cm0.h index 5186cb4838..da584c05a6 100644 --- a/bsp/swm320-lq100/Libraries/CMSIS/CoreSupport/core_cm0.h +++ b/bsp/swm320-lq100/Libraries/CMSIS/CoreSupport/core_cm0.h @@ -1,4 +1,4 @@ -/**************************************************************************//** +/**************************************************************************/ /** * @file core_cm0.h * @brief CMSIS Cortex-M0 Core Peripheral Access Layer Header File * @version V4.00 @@ -34,16 +34,16 @@ POSSIBILITY OF SUCH DAMAGE. ---------------------------------------------------------------------------*/ - -#if defined ( __ICCARM__ ) - #pragma system_include /* treat file as system include file for MISRA check */ +#if defined(__ICCARM__) +#pragma system_include /* treat file as system include file for MISRA check */ #endif #ifndef __CORE_CM0_H_GENERIC #define __CORE_CM0_H_GENERIC #ifdef __cplusplus - extern "C" { +extern "C" +{ #endif /** \page CMSIS_MISRA_Exceptions MISRA-C:2004 Compliance Exceptions @@ -59,7 +59,6 @@ Function-like macros are used to allow more efficient code. */ - /******************************************************************************* * CMSIS definitions ******************************************************************************/ @@ -68,85 +67,84 @@ */ /* CMSIS CM0 definitions */ -#define __CM0_CMSIS_VERSION_MAIN (0x04) /*!< [31:16] CMSIS HAL main version */ -#define __CM0_CMSIS_VERSION_SUB (0x00) /*!< [15:0] CMSIS HAL sub version */ -#define __CM0_CMSIS_VERSION ((__CM0_CMSIS_VERSION_MAIN << 16) | \ - __CM0_CMSIS_VERSION_SUB ) /*!< CMSIS HAL version number */ +#define __CM0_CMSIS_VERSION_MAIN (0x04) /*!< [31:16] CMSIS HAL main version */ +#define __CM0_CMSIS_VERSION_SUB (0x00) /*!< [15:0] CMSIS HAL sub version */ +#define __CM0_CMSIS_VERSION ((__CM0_CMSIS_VERSION_MAIN << 16) | \ + __CM0_CMSIS_VERSION_SUB) /*!< CMSIS HAL version number */ + +#define __CORTEX_M (0x00) /*!< Cortex-M Core */ + +#if defined(__CC_ARM) +#define __ASM __asm /*!< asm keyword for ARM Compiler */ +#define __INLINE __inline /*!< inline keyword for ARM Compiler */ +#define __STATIC_INLINE static __inline + +#elif defined(__GNUC__) +#define __ASM __asm /*!< asm keyword for GNU Compiler */ +#define __INLINE inline /*!< inline keyword for GNU Compiler */ +#define __STATIC_INLINE static inline + +#elif defined(__ICCARM__) +#define __ASM __asm /*!< asm keyword for IAR Compiler */ +#define __INLINE inline /*!< inline keyword for IAR Compiler. Only available in High optimization mode! */ +#define __STATIC_INLINE static inline + +#elif defined(__TMS470__) +#define __ASM __asm /*!< asm keyword for TI CCS Compiler */ +#define __STATIC_INLINE static inline + +#elif defined(__TASKING__) +#define __ASM __asm /*!< asm keyword for TASKING Compiler */ +#define __INLINE inline /*!< inline keyword for TASKING Compiler */ +#define __STATIC_INLINE static inline + +#elif defined(__CSMC__) +#define __packed +#define __ASM _asm /*!< asm keyword for COSMIC Compiler */ +#define __INLINE inline /*use -pc99 on compile line !< inline keyword for COSMIC Compiler */ +#define __STATIC_INLINE static inline -#define __CORTEX_M (0x00) /*!< Cortex-M Core */ - - -#if defined ( __CC_ARM ) - #define __ASM __asm /*!< asm keyword for ARM Compiler */ - #define __INLINE __inline /*!< inline keyword for ARM Compiler */ - #define __STATIC_INLINE static __inline +#endif -#elif defined ( __GNUC__ ) - #define __ASM __asm /*!< asm keyword for GNU Compiler */ - #define __INLINE inline /*!< inline keyword for GNU Compiler */ - #define __STATIC_INLINE static inline +/** __FPU_USED indicates whether an FPU is used or not. + This core does not support an FPU at all +*/ +#define __FPU_USED 0 -#elif defined ( __ICCARM__ ) - #define __ASM __asm /*!< asm keyword for IAR Compiler */ - #define __INLINE inline /*!< inline keyword for IAR Compiler. Only available in High optimization mode! */ - #define __STATIC_INLINE static inline +#if defined(__CC_ARM) +#if defined __TARGET_FPU_VFP +#warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" +#endif -#elif defined ( __TMS470__ ) - #define __ASM __asm /*!< asm keyword for TI CCS Compiler */ - #define __STATIC_INLINE static inline +#elif defined(__GNUC__) +#if defined(__VFP_FP__) && !defined(__SOFTFP__) +#warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" +#endif -#elif defined ( __TASKING__ ) - #define __ASM __asm /*!< asm keyword for TASKING Compiler */ - #define __INLINE inline /*!< inline keyword for TASKING Compiler */ - #define __STATIC_INLINE static inline +#elif defined(__ICCARM__) +#if defined __ARMVFP__ +#warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" +#endif -#elif defined ( __CSMC__ ) - #define __packed - #define __ASM _asm /*!< asm keyword for COSMIC Compiler */ - #define __INLINE inline /*use -pc99 on compile line !< inline keyword for COSMIC Compiler */ - #define __STATIC_INLINE static inline +#elif defined(__TMS470__) +#if defined __TI__VFP_SUPPORT____ +#warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" +#endif +#elif defined(__TASKING__) +#if defined __FPU_VFP__ +#error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" #endif -/** __FPU_USED indicates whether an FPU is used or not. - This core does not support an FPU at all -*/ -#define __FPU_USED 0 - -#if defined ( __CC_ARM ) - #if defined __TARGET_FPU_VFP - #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" - #endif - -#elif defined ( __GNUC__ ) - #if defined (__VFP_FP__) && !defined(__SOFTFP__) - #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" - #endif - -#elif defined ( __ICCARM__ ) - #if defined __ARMVFP__ - #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" - #endif - -#elif defined ( __TMS470__ ) - #if defined __TI__VFP_SUPPORT____ - #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" - #endif - -#elif defined ( __TASKING__ ) - #if defined __FPU_VFP__ - #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" - #endif - -#elif defined ( __CSMC__ ) /* Cosmic */ - #if ( __CSMC__ & 0x400) // FPU present for parser - #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" - #endif +#elif defined(__CSMC__) /* Cosmic */ +#if (__CSMC__ & 0x400) // FPU present for parser +#error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" +#endif #endif -#include /* standard types definitions */ -#include /* Core Instruction Access */ -#include /* Core Function Access */ +#include /* standard types definitions */ +#include /* Core Instruction Access */ +#include /* Core Function Access */ #ifdef __cplusplus } @@ -160,25 +158,26 @@ #define __CORE_CM0_H_DEPENDANT #ifdef __cplusplus - extern "C" { +extern "C" +{ #endif /* check device defines and use defaults */ #if defined __CHECK_DEVICE_DEFINES - #ifndef __CM0_REV - #define __CM0_REV 0x0000 - #warning "__CM0_REV not defined in device header file; using default!" - #endif - - #ifndef __NVIC_PRIO_BITS - #define __NVIC_PRIO_BITS 2 - #warning "__NVIC_PRIO_BITS not defined in device header file; using default!" - #endif - - #ifndef __Vendor_SysTickConfig - #define __Vendor_SysTickConfig 0 - #warning "__Vendor_SysTickConfig not defined in device header file; using default!" - #endif +#ifndef __CM0_REV +#define __CM0_REV 0x0000 +#warning "__CM0_REV not defined in device header file; using default!" +#endif + +#ifndef __NVIC_PRIO_BITS +#define __NVIC_PRIO_BITS 2 +#warning "__NVIC_PRIO_BITS not defined in device header file; using default!" +#endif + +#ifndef __Vendor_SysTickConfig +#define __Vendor_SysTickConfig 0 +#warning "__Vendor_SysTickConfig not defined in device header file; using default!" +#endif #endif /* IO definitions (access restrictions to peripheral registers) */ @@ -190,18 +189,16 @@ \li for automatic generation of peripheral register debug information. */ #ifdef __cplusplus - #define __I volatile /*!< Defines 'read only' permissions */ +#define __I volatile /*!< Defines 'read only' permissions */ #else - #define __I volatile const /*!< Defines 'read only' permissions */ +#define __I volatile const /*!< Defines 'read only' permissions */ #endif -#define __O volatile /*!< Defines 'write only' permissions */ -#define __IO volatile /*!< Defines 'read / write' permissions */ - -/*@} end of group Cortex_M0 */ - +#define __O volatile /*!< Defines 'write only' permissions */ +#define __IO volatile /*!< Defines 'read / write' permissions */ + /*@} end of group Cortex_M0 */ -/******************************************************************************* + /******************************************************************************* * Register Abstraction Core Register contain: - Core Register @@ -209,275 +206,268 @@ - Core SCB Register - Core SysTick Register ******************************************************************************/ -/** \defgroup CMSIS_core_register Defines and Type Definitions + /** \defgroup CMSIS_core_register Defines and Type Definitions \brief Type definitions and defines for Cortex-M processor based devices. */ -/** \ingroup CMSIS_core_register + /** \ingroup CMSIS_core_register \defgroup CMSIS_CORE Status and Control Registers \brief Core Register type definitions. @{ */ -/** \brief Union type to access the Application Program Status Register (APSR). + /** \brief Union type to access the Application Program Status Register (APSR). */ -typedef union -{ - struct - { + typedef union + { + struct + { #if (__CORTEX_M != 0x04) - uint32_t _reserved0:27; /*!< bit: 0..26 Reserved */ + uint32_t _reserved0 : 27; /*!< bit: 0..26 Reserved */ #else - uint32_t _reserved0:16; /*!< bit: 0..15 Reserved */ - uint32_t GE:4; /*!< bit: 16..19 Greater than or Equal flags */ - uint32_t _reserved1:7; /*!< bit: 20..26 Reserved */ + uint32_t _reserved0 : 16; /*!< bit: 0..15 Reserved */ + uint32_t GE : 4; /*!< bit: 16..19 Greater than or Equal flags */ + uint32_t _reserved1 : 7; /*!< bit: 20..26 Reserved */ #endif - uint32_t Q:1; /*!< bit: 27 Saturation condition flag */ - uint32_t V:1; /*!< bit: 28 Overflow condition code flag */ - uint32_t C:1; /*!< bit: 29 Carry condition code flag */ - uint32_t Z:1; /*!< bit: 30 Zero condition code flag */ - uint32_t N:1; /*!< bit: 31 Negative condition code flag */ - } b; /*!< Structure used for bit access */ - uint32_t w; /*!< Type used for word access */ -} APSR_Type; - - -/** \brief Union type to access the Interrupt Program Status Register (IPSR). + uint32_t Q : 1; /*!< bit: 27 Saturation condition flag */ + uint32_t V : 1; /*!< bit: 28 Overflow condition code flag */ + uint32_t C : 1; /*!< bit: 29 Carry condition code flag */ + uint32_t Z : 1; /*!< bit: 30 Zero condition code flag */ + uint32_t N : 1; /*!< bit: 31 Negative condition code flag */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ + } APSR_Type; + + /** \brief Union type to access the Interrupt Program Status Register (IPSR). */ -typedef union -{ - struct - { - uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */ - uint32_t _reserved0:23; /*!< bit: 9..31 Reserved */ - } b; /*!< Structure used for bit access */ - uint32_t w; /*!< Type used for word access */ -} IPSR_Type; - - -/** \brief Union type to access the Special-Purpose Program Status Registers (xPSR). + typedef union + { + struct + { + uint32_t ISR : 9; /*!< bit: 0.. 8 Exception number */ + uint32_t _reserved0 : 23; /*!< bit: 9..31 Reserved */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ + } IPSR_Type; + + /** \brief Union type to access the Special-Purpose Program Status Registers (xPSR). */ -typedef union -{ - struct - { - uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */ + typedef union + { + struct + { + uint32_t ISR : 9; /*!< bit: 0.. 8 Exception number */ #if (__CORTEX_M != 0x04) - uint32_t _reserved0:15; /*!< bit: 9..23 Reserved */ + uint32_t _reserved0 : 15; /*!< bit: 9..23 Reserved */ #else - uint32_t _reserved0:7; /*!< bit: 9..15 Reserved */ - uint32_t GE:4; /*!< bit: 16..19 Greater than or Equal flags */ - uint32_t _reserved1:4; /*!< bit: 20..23 Reserved */ + uint32_t _reserved0 : 7; /*!< bit: 9..15 Reserved */ + uint32_t GE : 4; /*!< bit: 16..19 Greater than or Equal flags */ + uint32_t _reserved1 : 4; /*!< bit: 20..23 Reserved */ #endif - uint32_t T:1; /*!< bit: 24 Thumb bit (read 0) */ - uint32_t IT:2; /*!< bit: 25..26 saved IT state (read 0) */ - uint32_t Q:1; /*!< bit: 27 Saturation condition flag */ - uint32_t V:1; /*!< bit: 28 Overflow condition code flag */ - uint32_t C:1; /*!< bit: 29 Carry condition code flag */ - uint32_t Z:1; /*!< bit: 30 Zero condition code flag */ - uint32_t N:1; /*!< bit: 31 Negative condition code flag */ - } b; /*!< Structure used for bit access */ - uint32_t w; /*!< Type used for word access */ -} xPSR_Type; - - -/** \brief Union type to access the Control Registers (CONTROL). + uint32_t T : 1; /*!< bit: 24 Thumb bit (read 0) */ + uint32_t IT : 2; /*!< bit: 25..26 saved IT state (read 0) */ + uint32_t Q : 1; /*!< bit: 27 Saturation condition flag */ + uint32_t V : 1; /*!< bit: 28 Overflow condition code flag */ + uint32_t C : 1; /*!< bit: 29 Carry condition code flag */ + uint32_t Z : 1; /*!< bit: 30 Zero condition code flag */ + uint32_t N : 1; /*!< bit: 31 Negative condition code flag */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ + } xPSR_Type; + + /** \brief Union type to access the Control Registers (CONTROL). */ -typedef union -{ - struct - { - uint32_t nPRIV:1; /*!< bit: 0 Execution privilege in Thread mode */ - uint32_t SPSEL:1; /*!< bit: 1 Stack to be used */ - uint32_t FPCA:1; /*!< bit: 2 FP extension active flag */ - uint32_t _reserved0:29; /*!< bit: 3..31 Reserved */ - } b; /*!< Structure used for bit access */ - uint32_t w; /*!< Type used for word access */ -} CONTROL_Type; - -/*@} end of group CMSIS_CORE */ - - -/** \ingroup CMSIS_core_register + typedef union + { + struct + { + uint32_t nPRIV : 1; /*!< bit: 0 Execution privilege in Thread mode */ + uint32_t SPSEL : 1; /*!< bit: 1 Stack to be used */ + uint32_t FPCA : 1; /*!< bit: 2 FP extension active flag */ + uint32_t _reserved0 : 29; /*!< bit: 3..31 Reserved */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ + } CONTROL_Type; + + /*@} end of group CMSIS_CORE */ + + /** \ingroup CMSIS_core_register \defgroup CMSIS_NVIC Nested Vectored Interrupt Controller (NVIC) \brief Type definitions for the NVIC Registers @{ */ -/** \brief Structure type to access the Nested Vectored Interrupt Controller (NVIC). + /** \brief Structure type to access the Nested Vectored Interrupt Controller (NVIC). */ -typedef struct -{ - __IO uint32_t ISER[1]; /*!< Offset: 0x000 (R/W) Interrupt Set Enable Register */ - uint32_t RESERVED0[31]; - __IO uint32_t ICER[1]; /*!< Offset: 0x080 (R/W) Interrupt Clear Enable Register */ - uint32_t RSERVED1[31]; - __IO uint32_t ISPR[1]; /*!< Offset: 0x100 (R/W) Interrupt Set Pending Register */ - uint32_t RESERVED2[31]; - __IO uint32_t ICPR[1]; /*!< Offset: 0x180 (R/W) Interrupt Clear Pending Register */ - uint32_t RESERVED3[31]; - uint32_t RESERVED4[64]; - __IO uint32_t IP[8]; /*!< Offset: 0x300 (R/W) Interrupt Priority Register */ -} NVIC_Type; - -/*@} end of group CMSIS_NVIC */ - - -/** \ingroup CMSIS_core_register + typedef struct + { + __IO uint32_t ISER[1]; /*!< Offset: 0x000 (R/W) Interrupt Set Enable Register */ + uint32_t RESERVED0[31]; + __IO uint32_t ICER[1]; /*!< Offset: 0x080 (R/W) Interrupt Clear Enable Register */ + uint32_t RSERVED1[31]; + __IO uint32_t ISPR[1]; /*!< Offset: 0x100 (R/W) Interrupt Set Pending Register */ + uint32_t RESERVED2[31]; + __IO uint32_t ICPR[1]; /*!< Offset: 0x180 (R/W) Interrupt Clear Pending Register */ + uint32_t RESERVED3[31]; + uint32_t RESERVED4[64]; + __IO uint32_t IP[8]; /*!< Offset: 0x300 (R/W) Interrupt Priority Register */ + } NVIC_Type; + + /*@} end of group CMSIS_NVIC */ + + /** \ingroup CMSIS_core_register \defgroup CMSIS_SCB System Control Block (SCB) \brief Type definitions for the System Control Block Registers @{ */ -/** \brief Structure type to access the System Control Block (SCB). + /** \brief Structure type to access the System Control Block (SCB). */ -typedef struct -{ - __I uint32_t CPUID; /*!< Offset: 0x000 (R/ ) CPUID Base Register */ - __IO uint32_t ICSR; /*!< Offset: 0x004 (R/W) Interrupt Control and State Register */ - uint32_t RESERVED0; - __IO uint32_t AIRCR; /*!< Offset: 0x00C (R/W) Application Interrupt and Reset Control Register */ - __IO uint32_t SCR; /*!< Offset: 0x010 (R/W) System Control Register */ - __IO uint32_t CCR; /*!< Offset: 0x014 (R/W) Configuration Control Register */ - uint32_t RESERVED1; - __IO uint32_t SHP[2]; /*!< Offset: 0x01C (R/W) System Handlers Priority Registers. [0] is RESERVED */ - __IO uint32_t SHCSR; /*!< Offset: 0x024 (R/W) System Handler Control and State Register */ -} SCB_Type; + typedef struct + { + __I uint32_t CPUID; /*!< Offset: 0x000 (R/ ) CPUID Base Register */ + __IO uint32_t ICSR; /*!< Offset: 0x004 (R/W) Interrupt Control and State Register */ + uint32_t RESERVED0; + __IO uint32_t AIRCR; /*!< Offset: 0x00C (R/W) Application Interrupt and Reset Control Register */ + __IO uint32_t SCR; /*!< Offset: 0x010 (R/W) System Control Register */ + __IO uint32_t CCR; /*!< Offset: 0x014 (R/W) Configuration Control Register */ + uint32_t RESERVED1; + __IO uint32_t SHP[2]; /*!< Offset: 0x01C (R/W) System Handlers Priority Registers. [0] is RESERVED */ + __IO uint32_t SHCSR; /*!< Offset: 0x024 (R/W) System Handler Control and State Register */ + } SCB_Type; /* SCB CPUID Register Definitions */ -#define SCB_CPUID_IMPLEMENTER_Pos 24 /*!< SCB CPUID: IMPLEMENTER Position */ -#define SCB_CPUID_IMPLEMENTER_Msk (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos) /*!< SCB CPUID: IMPLEMENTER Mask */ +#define SCB_CPUID_IMPLEMENTER_Pos 24 /*!< SCB CPUID: IMPLEMENTER Position */ +#define SCB_CPUID_IMPLEMENTER_Msk (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos) /*!< SCB CPUID: IMPLEMENTER Mask */ -#define SCB_CPUID_VARIANT_Pos 20 /*!< SCB CPUID: VARIANT Position */ -#define SCB_CPUID_VARIANT_Msk (0xFUL << SCB_CPUID_VARIANT_Pos) /*!< SCB CPUID: VARIANT Mask */ +#define SCB_CPUID_VARIANT_Pos 20 /*!< SCB CPUID: VARIANT Position */ +#define SCB_CPUID_VARIANT_Msk (0xFUL << SCB_CPUID_VARIANT_Pos) /*!< SCB CPUID: VARIANT Mask */ -#define SCB_CPUID_ARCHITECTURE_Pos 16 /*!< SCB CPUID: ARCHITECTURE Position */ -#define SCB_CPUID_ARCHITECTURE_Msk (0xFUL << SCB_CPUID_ARCHITECTURE_Pos) /*!< SCB CPUID: ARCHITECTURE Mask */ +#define SCB_CPUID_ARCHITECTURE_Pos 16 /*!< SCB CPUID: ARCHITECTURE Position */ +#define SCB_CPUID_ARCHITECTURE_Msk (0xFUL << SCB_CPUID_ARCHITECTURE_Pos) /*!< SCB CPUID: ARCHITECTURE Mask */ -#define SCB_CPUID_PARTNO_Pos 4 /*!< SCB CPUID: PARTNO Position */ -#define SCB_CPUID_PARTNO_Msk (0xFFFUL << SCB_CPUID_PARTNO_Pos) /*!< SCB CPUID: PARTNO Mask */ +#define SCB_CPUID_PARTNO_Pos 4 /*!< SCB CPUID: PARTNO Position */ +#define SCB_CPUID_PARTNO_Msk (0xFFFUL << SCB_CPUID_PARTNO_Pos) /*!< SCB CPUID: PARTNO Mask */ -#define SCB_CPUID_REVISION_Pos 0 /*!< SCB CPUID: REVISION Position */ -#define SCB_CPUID_REVISION_Msk (0xFUL << SCB_CPUID_REVISION_Pos) /*!< SCB CPUID: REVISION Mask */ +#define SCB_CPUID_REVISION_Pos 0 /*!< SCB CPUID: REVISION Position */ +#define SCB_CPUID_REVISION_Msk (0xFUL << SCB_CPUID_REVISION_Pos) /*!< SCB CPUID: REVISION Mask */ /* SCB Interrupt Control State Register Definitions */ -#define SCB_ICSR_NMIPENDSET_Pos 31 /*!< SCB ICSR: NMIPENDSET Position */ -#define SCB_ICSR_NMIPENDSET_Msk (1UL << SCB_ICSR_NMIPENDSET_Pos) /*!< SCB ICSR: NMIPENDSET Mask */ +#define SCB_ICSR_NMIPENDSET_Pos 31 /*!< SCB ICSR: NMIPENDSET Position */ +#define SCB_ICSR_NMIPENDSET_Msk (1UL << SCB_ICSR_NMIPENDSET_Pos) /*!< SCB ICSR: NMIPENDSET Mask */ -#define SCB_ICSR_PENDSVSET_Pos 28 /*!< SCB ICSR: PENDSVSET Position */ -#define SCB_ICSR_PENDSVSET_Msk (1UL << SCB_ICSR_PENDSVSET_Pos) /*!< SCB ICSR: PENDSVSET Mask */ +#define SCB_ICSR_PENDSVSET_Pos 28 /*!< SCB ICSR: PENDSVSET Position */ +#define SCB_ICSR_PENDSVSET_Msk (1UL << SCB_ICSR_PENDSVSET_Pos) /*!< SCB ICSR: PENDSVSET Mask */ -#define SCB_ICSR_PENDSVCLR_Pos 27 /*!< SCB ICSR: PENDSVCLR Position */ -#define SCB_ICSR_PENDSVCLR_Msk (1UL << SCB_ICSR_PENDSVCLR_Pos) /*!< SCB ICSR: PENDSVCLR Mask */ +#define SCB_ICSR_PENDSVCLR_Pos 27 /*!< SCB ICSR: PENDSVCLR Position */ +#define SCB_ICSR_PENDSVCLR_Msk (1UL << SCB_ICSR_PENDSVCLR_Pos) /*!< SCB ICSR: PENDSVCLR Mask */ -#define SCB_ICSR_PENDSTSET_Pos 26 /*!< SCB ICSR: PENDSTSET Position */ -#define SCB_ICSR_PENDSTSET_Msk (1UL << SCB_ICSR_PENDSTSET_Pos) /*!< SCB ICSR: PENDSTSET Mask */ +#define SCB_ICSR_PENDSTSET_Pos 26 /*!< SCB ICSR: PENDSTSET Position */ +#define SCB_ICSR_PENDSTSET_Msk (1UL << SCB_ICSR_PENDSTSET_Pos) /*!< SCB ICSR: PENDSTSET Mask */ -#define SCB_ICSR_PENDSTCLR_Pos 25 /*!< SCB ICSR: PENDSTCLR Position */ -#define SCB_ICSR_PENDSTCLR_Msk (1UL << SCB_ICSR_PENDSTCLR_Pos) /*!< SCB ICSR: PENDSTCLR Mask */ +#define SCB_ICSR_PENDSTCLR_Pos 25 /*!< SCB ICSR: PENDSTCLR Position */ +#define SCB_ICSR_PENDSTCLR_Msk (1UL << SCB_ICSR_PENDSTCLR_Pos) /*!< SCB ICSR: PENDSTCLR Mask */ -#define SCB_ICSR_ISRPREEMPT_Pos 23 /*!< SCB ICSR: ISRPREEMPT Position */ -#define SCB_ICSR_ISRPREEMPT_Msk (1UL << SCB_ICSR_ISRPREEMPT_Pos) /*!< SCB ICSR: ISRPREEMPT Mask */ +#define SCB_ICSR_ISRPREEMPT_Pos 23 /*!< SCB ICSR: ISRPREEMPT Position */ +#define SCB_ICSR_ISRPREEMPT_Msk (1UL << SCB_ICSR_ISRPREEMPT_Pos) /*!< SCB ICSR: ISRPREEMPT Mask */ -#define SCB_ICSR_ISRPENDING_Pos 22 /*!< SCB ICSR: ISRPENDING Position */ -#define SCB_ICSR_ISRPENDING_Msk (1UL << SCB_ICSR_ISRPENDING_Pos) /*!< SCB ICSR: ISRPENDING Mask */ +#define SCB_ICSR_ISRPENDING_Pos 22 /*!< SCB ICSR: ISRPENDING Position */ +#define SCB_ICSR_ISRPENDING_Msk (1UL << SCB_ICSR_ISRPENDING_Pos) /*!< SCB ICSR: ISRPENDING Mask */ -#define SCB_ICSR_VECTPENDING_Pos 12 /*!< SCB ICSR: VECTPENDING Position */ -#define SCB_ICSR_VECTPENDING_Msk (0x1FFUL << SCB_ICSR_VECTPENDING_Pos) /*!< SCB ICSR: VECTPENDING Mask */ +#define SCB_ICSR_VECTPENDING_Pos 12 /*!< SCB ICSR: VECTPENDING Position */ +#define SCB_ICSR_VECTPENDING_Msk (0x1FFUL << SCB_ICSR_VECTPENDING_Pos) /*!< SCB ICSR: VECTPENDING Mask */ -#define SCB_ICSR_VECTACTIVE_Pos 0 /*!< SCB ICSR: VECTACTIVE Position */ -#define SCB_ICSR_VECTACTIVE_Msk (0x1FFUL << SCB_ICSR_VECTACTIVE_Pos) /*!< SCB ICSR: VECTACTIVE Mask */ +#define SCB_ICSR_VECTACTIVE_Pos 0 /*!< SCB ICSR: VECTACTIVE Position */ +#define SCB_ICSR_VECTACTIVE_Msk (0x1FFUL << SCB_ICSR_VECTACTIVE_Pos) /*!< SCB ICSR: VECTACTIVE Mask */ /* SCB Application Interrupt and Reset Control Register Definitions */ -#define SCB_AIRCR_VECTKEY_Pos 16 /*!< SCB AIRCR: VECTKEY Position */ -#define SCB_AIRCR_VECTKEY_Msk (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos) /*!< SCB AIRCR: VECTKEY Mask */ +#define SCB_AIRCR_VECTKEY_Pos 16 /*!< SCB AIRCR: VECTKEY Position */ +#define SCB_AIRCR_VECTKEY_Msk (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos) /*!< SCB AIRCR: VECTKEY Mask */ -#define SCB_AIRCR_VECTKEYSTAT_Pos 16 /*!< SCB AIRCR: VECTKEYSTAT Position */ -#define SCB_AIRCR_VECTKEYSTAT_Msk (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos) /*!< SCB AIRCR: VECTKEYSTAT Mask */ +#define SCB_AIRCR_VECTKEYSTAT_Pos 16 /*!< SCB AIRCR: VECTKEYSTAT Position */ +#define SCB_AIRCR_VECTKEYSTAT_Msk (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos) /*!< SCB AIRCR: VECTKEYSTAT Mask */ -#define SCB_AIRCR_ENDIANESS_Pos 15 /*!< SCB AIRCR: ENDIANESS Position */ -#define SCB_AIRCR_ENDIANESS_Msk (1UL << SCB_AIRCR_ENDIANESS_Pos) /*!< SCB AIRCR: ENDIANESS Mask */ +#define SCB_AIRCR_ENDIANESS_Pos 15 /*!< SCB AIRCR: ENDIANESS Position */ +#define SCB_AIRCR_ENDIANESS_Msk (1UL << SCB_AIRCR_ENDIANESS_Pos) /*!< SCB AIRCR: ENDIANESS Mask */ -#define SCB_AIRCR_SYSRESETREQ_Pos 2 /*!< SCB AIRCR: SYSRESETREQ Position */ -#define SCB_AIRCR_SYSRESETREQ_Msk (1UL << SCB_AIRCR_SYSRESETREQ_Pos) /*!< SCB AIRCR: SYSRESETREQ Mask */ +#define SCB_AIRCR_SYSRESETREQ_Pos 2 /*!< SCB AIRCR: SYSRESETREQ Position */ +#define SCB_AIRCR_SYSRESETREQ_Msk (1UL << SCB_AIRCR_SYSRESETREQ_Pos) /*!< SCB AIRCR: SYSRESETREQ Mask */ -#define SCB_AIRCR_VECTCLRACTIVE_Pos 1 /*!< SCB AIRCR: VECTCLRACTIVE Position */ -#define SCB_AIRCR_VECTCLRACTIVE_Msk (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos) /*!< SCB AIRCR: VECTCLRACTIVE Mask */ +#define SCB_AIRCR_VECTCLRACTIVE_Pos 1 /*!< SCB AIRCR: VECTCLRACTIVE Position */ +#define SCB_AIRCR_VECTCLRACTIVE_Msk (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos) /*!< SCB AIRCR: VECTCLRACTIVE Mask */ /* SCB System Control Register Definitions */ -#define SCB_SCR_SEVONPEND_Pos 4 /*!< SCB SCR: SEVONPEND Position */ -#define SCB_SCR_SEVONPEND_Msk (1UL << SCB_SCR_SEVONPEND_Pos) /*!< SCB SCR: SEVONPEND Mask */ +#define SCB_SCR_SEVONPEND_Pos 4 /*!< SCB SCR: SEVONPEND Position */ +#define SCB_SCR_SEVONPEND_Msk (1UL << SCB_SCR_SEVONPEND_Pos) /*!< SCB SCR: SEVONPEND Mask */ -#define SCB_SCR_SLEEPDEEP_Pos 2 /*!< SCB SCR: SLEEPDEEP Position */ -#define SCB_SCR_SLEEPDEEP_Msk (1UL << SCB_SCR_SLEEPDEEP_Pos) /*!< SCB SCR: SLEEPDEEP Mask */ +#define SCB_SCR_SLEEPDEEP_Pos 2 /*!< SCB SCR: SLEEPDEEP Position */ +#define SCB_SCR_SLEEPDEEP_Msk (1UL << SCB_SCR_SLEEPDEEP_Pos) /*!< SCB SCR: SLEEPDEEP Mask */ -#define SCB_SCR_SLEEPONEXIT_Pos 1 /*!< SCB SCR: SLEEPONEXIT Position */ -#define SCB_SCR_SLEEPONEXIT_Msk (1UL << SCB_SCR_SLEEPONEXIT_Pos) /*!< SCB SCR: SLEEPONEXIT Mask */ +#define SCB_SCR_SLEEPONEXIT_Pos 1 /*!< SCB SCR: SLEEPONEXIT Position */ +#define SCB_SCR_SLEEPONEXIT_Msk (1UL << SCB_SCR_SLEEPONEXIT_Pos) /*!< SCB SCR: SLEEPONEXIT Mask */ /* SCB Configuration Control Register Definitions */ -#define SCB_CCR_STKALIGN_Pos 9 /*!< SCB CCR: STKALIGN Position */ -#define SCB_CCR_STKALIGN_Msk (1UL << SCB_CCR_STKALIGN_Pos) /*!< SCB CCR: STKALIGN Mask */ +#define SCB_CCR_STKALIGN_Pos 9 /*!< SCB CCR: STKALIGN Position */ +#define SCB_CCR_STKALIGN_Msk (1UL << SCB_CCR_STKALIGN_Pos) /*!< SCB CCR: STKALIGN Mask */ -#define SCB_CCR_UNALIGN_TRP_Pos 3 /*!< SCB CCR: UNALIGN_TRP Position */ -#define SCB_CCR_UNALIGN_TRP_Msk (1UL << SCB_CCR_UNALIGN_TRP_Pos) /*!< SCB CCR: UNALIGN_TRP Mask */ +#define SCB_CCR_UNALIGN_TRP_Pos 3 /*!< SCB CCR: UNALIGN_TRP Position */ +#define SCB_CCR_UNALIGN_TRP_Msk (1UL << SCB_CCR_UNALIGN_TRP_Pos) /*!< SCB CCR: UNALIGN_TRP Mask */ /* SCB System Handler Control and State Register Definitions */ -#define SCB_SHCSR_SVCALLPENDED_Pos 15 /*!< SCB SHCSR: SVCALLPENDED Position */ -#define SCB_SHCSR_SVCALLPENDED_Msk (1UL << SCB_SHCSR_SVCALLPENDED_Pos) /*!< SCB SHCSR: SVCALLPENDED Mask */ - -/*@} end of group CMSIS_SCB */ +#define SCB_SHCSR_SVCALLPENDED_Pos 15 /*!< SCB SHCSR: SVCALLPENDED Position */ +#define SCB_SHCSR_SVCALLPENDED_Msk (1UL << SCB_SHCSR_SVCALLPENDED_Pos) /*!< SCB SHCSR: SVCALLPENDED Mask */ + /*@} end of group CMSIS_SCB */ -/** \ingroup CMSIS_core_register + /** \ingroup CMSIS_core_register \defgroup CMSIS_SysTick System Tick Timer (SysTick) \brief Type definitions for the System Timer Registers. @{ */ -/** \brief Structure type to access the System Timer (SysTick). + /** \brief Structure type to access the System Timer (SysTick). */ -typedef struct -{ - __IO uint32_t CTRL; /*!< Offset: 0x000 (R/W) SysTick Control and Status Register */ - __IO uint32_t LOAD; /*!< Offset: 0x004 (R/W) SysTick Reload Value Register */ - __IO uint32_t VAL; /*!< Offset: 0x008 (R/W) SysTick Current Value Register */ - __I uint32_t CALIB; /*!< Offset: 0x00C (R/ ) SysTick Calibration Register */ -} SysTick_Type; + typedef struct + { + __IO uint32_t CTRL; /*!< Offset: 0x000 (R/W) SysTick Control and Status Register */ + __IO uint32_t LOAD; /*!< Offset: 0x004 (R/W) SysTick Reload Value Register */ + __IO uint32_t VAL; /*!< Offset: 0x008 (R/W) SysTick Current Value Register */ + __I uint32_t CALIB; /*!< Offset: 0x00C (R/ ) SysTick Calibration Register */ + } SysTick_Type; /* SysTick Control / Status Register Definitions */ -#define SysTick_CTRL_COUNTFLAG_Pos 16 /*!< SysTick CTRL: COUNTFLAG Position */ -#define SysTick_CTRL_COUNTFLAG_Msk (1UL << SysTick_CTRL_COUNTFLAG_Pos) /*!< SysTick CTRL: COUNTFLAG Mask */ +#define SysTick_CTRL_COUNTFLAG_Pos 16 /*!< SysTick CTRL: COUNTFLAG Position */ +#define SysTick_CTRL_COUNTFLAG_Msk (1UL << SysTick_CTRL_COUNTFLAG_Pos) /*!< SysTick CTRL: COUNTFLAG Mask */ -#define SysTick_CTRL_CLKSOURCE_Pos 2 /*!< SysTick CTRL: CLKSOURCE Position */ -#define SysTick_CTRL_CLKSOURCE_Msk (1UL << SysTick_CTRL_CLKSOURCE_Pos) /*!< SysTick CTRL: CLKSOURCE Mask */ +#define SysTick_CTRL_CLKSOURCE_Pos 2 /*!< SysTick CTRL: CLKSOURCE Position */ +#define SysTick_CTRL_CLKSOURCE_Msk (1UL << SysTick_CTRL_CLKSOURCE_Pos) /*!< SysTick CTRL: CLKSOURCE Mask */ -#define SysTick_CTRL_TICKINT_Pos 1 /*!< SysTick CTRL: TICKINT Position */ -#define SysTick_CTRL_TICKINT_Msk (1UL << SysTick_CTRL_TICKINT_Pos) /*!< SysTick CTRL: TICKINT Mask */ +#define SysTick_CTRL_TICKINT_Pos 1 /*!< SysTick CTRL: TICKINT Position */ +#define SysTick_CTRL_TICKINT_Msk (1UL << SysTick_CTRL_TICKINT_Pos) /*!< SysTick CTRL: TICKINT Mask */ -#define SysTick_CTRL_ENABLE_Pos 0 /*!< SysTick CTRL: ENABLE Position */ -#define SysTick_CTRL_ENABLE_Msk (1UL << SysTick_CTRL_ENABLE_Pos) /*!< SysTick CTRL: ENABLE Mask */ +#define SysTick_CTRL_ENABLE_Pos 0 /*!< SysTick CTRL: ENABLE Position */ +#define SysTick_CTRL_ENABLE_Msk (1UL << SysTick_CTRL_ENABLE_Pos) /*!< SysTick CTRL: ENABLE Mask */ /* SysTick Reload Register Definitions */ -#define SysTick_LOAD_RELOAD_Pos 0 /*!< SysTick LOAD: RELOAD Position */ -#define SysTick_LOAD_RELOAD_Msk (0xFFFFFFUL << SysTick_LOAD_RELOAD_Pos) /*!< SysTick LOAD: RELOAD Mask */ +#define SysTick_LOAD_RELOAD_Pos 0 /*!< SysTick LOAD: RELOAD Position */ +#define SysTick_LOAD_RELOAD_Msk (0xFFFFFFUL << SysTick_LOAD_RELOAD_Pos) /*!< SysTick LOAD: RELOAD Mask */ /* SysTick Current Register Definitions */ -#define SysTick_VAL_CURRENT_Pos 0 /*!< SysTick VAL: CURRENT Position */ -#define SysTick_VAL_CURRENT_Msk (0xFFFFFFUL << SysTick_VAL_CURRENT_Pos) /*!< SysTick VAL: CURRENT Mask */ +#define SysTick_VAL_CURRENT_Pos 0 /*!< SysTick VAL: CURRENT Position */ +#define SysTick_VAL_CURRENT_Msk (0xFFFFFFUL << SysTick_VAL_CURRENT_Pos) /*!< SysTick VAL: CURRENT Mask */ /* SysTick Calibration Register Definitions */ -#define SysTick_CALIB_NOREF_Pos 31 /*!< SysTick CALIB: NOREF Position */ -#define SysTick_CALIB_NOREF_Msk (1UL << SysTick_CALIB_NOREF_Pos) /*!< SysTick CALIB: NOREF Mask */ +#define SysTick_CALIB_NOREF_Pos 31 /*!< SysTick CALIB: NOREF Position */ +#define SysTick_CALIB_NOREF_Msk (1UL << SysTick_CALIB_NOREF_Pos) /*!< SysTick CALIB: NOREF Mask */ -#define SysTick_CALIB_SKEW_Pos 30 /*!< SysTick CALIB: SKEW Position */ -#define SysTick_CALIB_SKEW_Msk (1UL << SysTick_CALIB_SKEW_Pos) /*!< SysTick CALIB: SKEW Mask */ +#define SysTick_CALIB_SKEW_Pos 30 /*!< SysTick CALIB: SKEW Position */ +#define SysTick_CALIB_SKEW_Msk (1UL << SysTick_CALIB_SKEW_Pos) /*!< SysTick CALIB: SKEW Mask */ -#define SysTick_CALIB_TENMS_Pos 0 /*!< SysTick CALIB: TENMS Position */ -#define SysTick_CALIB_TENMS_Msk (0xFFFFFFUL << SysTick_CALIB_TENMS_Pos) /*!< SysTick CALIB: TENMS Mask */ +#define SysTick_CALIB_TENMS_Pos 0 /*!< SysTick CALIB: TENMS Position */ +#define SysTick_CALIB_TENMS_Msk (0xFFFFFFUL << SysTick_CALIB_TENMS_Pos) /*!< SysTick CALIB: TENMS Mask */ /*@} end of group CMSIS_SysTick */ - /** \ingroup CMSIS_core_register \defgroup CMSIS_CoreDebug Core Debug Registers (CoreDebug) \brief Cortex-M0 Core Debug Registers (DCB registers, SHCSR, and DFSR) @@ -487,7 +477,6 @@ typedef struct */ /*@} end of group CMSIS_CoreDebug */ - /** \ingroup CMSIS_core_register \defgroup CMSIS_core_base Core Definitions \brief Definitions for base addresses, unions, and structures. @@ -495,20 +484,17 @@ typedef struct */ /* Memory mapping of Cortex-M0 Hardware */ -#define SCS_BASE (0xE000E000UL) /*!< System Control Space Base Address */ -#define SysTick_BASE (SCS_BASE + 0x0010UL) /*!< SysTick Base Address */ -#define NVIC_BASE (SCS_BASE + 0x0100UL) /*!< NVIC Base Address */ -#define SCB_BASE (SCS_BASE + 0x0D00UL) /*!< System Control Block Base Address */ - -#define SCB ((SCB_Type *) SCB_BASE ) /*!< SCB configuration struct */ -#define SysTick ((SysTick_Type *) SysTick_BASE ) /*!< SysTick configuration struct */ -#define NVIC ((NVIC_Type *) NVIC_BASE ) /*!< NVIC configuration struct */ +#define SCS_BASE (0xE000E000UL) /*!< System Control Space Base Address */ +#define SysTick_BASE (SCS_BASE + 0x0010UL) /*!< SysTick Base Address */ +#define NVIC_BASE (SCS_BASE + 0x0100UL) /*!< NVIC Base Address */ +#define SCB_BASE (SCS_BASE + 0x0D00UL) /*!< System Control Block Base Address */ +#define SCB ((SCB_Type *)SCB_BASE) /*!< SCB configuration struct */ +#define SysTick ((SysTick_Type *)SysTick_BASE) /*!< SysTick configuration struct */ +#define NVIC ((NVIC_Type *)NVIC_BASE) /*!< NVIC configuration struct */ /*@} */ - - /******************************************************************************* * Hardware Abstraction Layer Core Function Interface contains: @@ -519,8 +505,6 @@ typedef struct /** \defgroup CMSIS_Core_FunctionInterface Functions and Instructions Reference */ - - /* ########################## NVIC functions #################################### */ /** \ingroup CMSIS_Core_FunctionInterface \defgroup CMSIS_Core_NVICFunctions NVIC Functions @@ -530,36 +514,33 @@ typedef struct /* Interrupt Priorities are WORD accessible only under ARMv6M */ /* The following MACROS handle generation of the register offset and byte masks */ -#define _BIT_SHIFT(IRQn) ( (((uint32_t)(IRQn) ) & 0x03) * 8 ) -#define _SHP_IDX(IRQn) ( ((((uint32_t)(IRQn) & 0x0F)-8) >> 2) ) -#define _IP_IDX(IRQn) ( ((uint32_t)(IRQn) >> 2) ) +#define _BIT_SHIFT(IRQn) ((((uint32_t)(IRQn)) & 0x03) * 8) +#define _SHP_IDX(IRQn) (((((uint32_t)(IRQn)&0x0F) - 8) >> 2)) +#define _IP_IDX(IRQn) (((uint32_t)(IRQn) >> 2)) - -/** \brief Enable External Interrupt + /** \brief Enable External Interrupt The function enables a device-specific interrupt in the NVIC interrupt controller. \param [in] IRQn External interrupt number. Value cannot be negative. */ -__STATIC_INLINE void NVIC_EnableIRQ(IRQn_Type IRQn) -{ - NVIC->ISER[0] = (1 << ((uint32_t)(IRQn) & 0x1F)); -} + __STATIC_INLINE void NVIC_EnableIRQ(IRQn_Type IRQn) + { + NVIC->ISER[0] = (1 << ((uint32_t)(IRQn)&0x1F)); + } - -/** \brief Disable External Interrupt + /** \brief Disable External Interrupt The function disables a device-specific interrupt in the NVIC interrupt controller. \param [in] IRQn External interrupt number. Value cannot be negative. */ -__STATIC_INLINE void NVIC_DisableIRQ(IRQn_Type IRQn) -{ - NVIC->ICER[0] = (1 << ((uint32_t)(IRQn) & 0x1F)); -} + __STATIC_INLINE void NVIC_DisableIRQ(IRQn_Type IRQn) + { + NVIC->ICER[0] = (1 << ((uint32_t)(IRQn)&0x1F)); + } - -/** \brief Get Pending Interrupt + /** \brief Get Pending Interrupt The function reads the pending register in the NVIC and returns the pending bit for the specified interrupt. @@ -569,37 +550,34 @@ __STATIC_INLINE void NVIC_DisableIRQ(IRQn_Type IRQn) \return 0 Interrupt status is not pending. \return 1 Interrupt status is pending. */ -__STATIC_INLINE uint32_t NVIC_GetPendingIRQ(IRQn_Type IRQn) -{ - return((uint32_t) ((NVIC->ISPR[0] & (1 << ((uint32_t)(IRQn) & 0x1F)))?1:0)); -} + __STATIC_INLINE uint32_t NVIC_GetPendingIRQ(IRQn_Type IRQn) + { + return ((uint32_t)((NVIC->ISPR[0] & (1 << ((uint32_t)(IRQn)&0x1F))) ? 1 : 0)); + } - -/** \brief Set Pending Interrupt + /** \brief Set Pending Interrupt The function sets the pending bit of an external interrupt. \param [in] IRQn Interrupt number. Value cannot be negative. */ -__STATIC_INLINE void NVIC_SetPendingIRQ(IRQn_Type IRQn) -{ - NVIC->ISPR[0] = (1 << ((uint32_t)(IRQn) & 0x1F)); -} - + __STATIC_INLINE void NVIC_SetPendingIRQ(IRQn_Type IRQn) + { + NVIC->ISPR[0] = (1 << ((uint32_t)(IRQn)&0x1F)); + } -/** \brief Clear Pending Interrupt + /** \brief Clear Pending Interrupt The function clears the pending bit of an external interrupt. \param [in] IRQn External interrupt number. Value cannot be negative. */ -__STATIC_INLINE void NVIC_ClearPendingIRQ(IRQn_Type IRQn) -{ - NVIC->ICPR[0] = (1 << ((uint32_t)(IRQn) & 0x1F)); /* Clear pending interrupt */ -} - + __STATIC_INLINE void NVIC_ClearPendingIRQ(IRQn_Type IRQn) + { + NVIC->ICPR[0] = (1 << ((uint32_t)(IRQn)&0x1F)); /* Clear pending interrupt */ + } -/** \brief Set Interrupt Priority + /** \brief Set Interrupt Priority The function sets the priority of an interrupt. @@ -608,18 +586,21 @@ __STATIC_INLINE void NVIC_ClearPendingIRQ(IRQn_Type IRQn) \param [in] IRQn Interrupt number. \param [in] priority Priority to set. */ -__STATIC_INLINE void NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority) -{ - if(IRQn < 0) { - SCB->SHP[_SHP_IDX(IRQn)] = (SCB->SHP[_SHP_IDX(IRQn)] & ~(0xFF << _BIT_SHIFT(IRQn))) | - (((priority << (8 - __NVIC_PRIO_BITS)) & 0xFF) << _BIT_SHIFT(IRQn)); } - else { - NVIC->IP[_IP_IDX(IRQn)] = (NVIC->IP[_IP_IDX(IRQn)] & ~(0xFF << _BIT_SHIFT(IRQn))) | - (((priority << (8 - __NVIC_PRIO_BITS)) & 0xFF) << _BIT_SHIFT(IRQn)); } -} - - -/** \brief Get Interrupt Priority + __STATIC_INLINE void NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority) + { + if (IRQn < 0) + { + SCB->SHP[_SHP_IDX(IRQn)] = (SCB->SHP[_SHP_IDX(IRQn)] & ~(0xFF << _BIT_SHIFT(IRQn))) | + (((priority << (8 - __NVIC_PRIO_BITS)) & 0xFF) << _BIT_SHIFT(IRQn)); + } + else + { + NVIC->IP[_IP_IDX(IRQn)] = (NVIC->IP[_IP_IDX(IRQn)] & ~(0xFF << _BIT_SHIFT(IRQn))) | + (((priority << (8 - __NVIC_PRIO_BITS)) & 0xFF) << _BIT_SHIFT(IRQn)); + } + } + + /** \brief Get Interrupt Priority The function reads the priority of an interrupt. The interrupt number can be positive to specify an external (device specific) @@ -630,36 +611,38 @@ __STATIC_INLINE void NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority) \return Interrupt Priority. Value is aligned automatically to the implemented priority bits of the microcontroller. */ -__STATIC_INLINE uint32_t NVIC_GetPriority(IRQn_Type IRQn) -{ - - if(IRQn < 0) { - return((uint32_t)(((SCB->SHP[_SHP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) & 0xFF) >> (8 - __NVIC_PRIO_BITS))); } /* get priority for Cortex-M0 system interrupts */ - else { - return((uint32_t)(((NVIC->IP[ _IP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) & 0xFF) >> (8 - __NVIC_PRIO_BITS))); } /* get priority for device specific interrupts */ -} + __STATIC_INLINE uint32_t NVIC_GetPriority(IRQn_Type IRQn) + { + if (IRQn < 0) + { + return ((uint32_t)(((SCB->SHP[_SHP_IDX(IRQn)] >> _BIT_SHIFT(IRQn)) & 0xFF) >> (8 - __NVIC_PRIO_BITS))); + } /* get priority for Cortex-M0 system interrupts */ + else + { + return ((uint32_t)(((NVIC->IP[_IP_IDX(IRQn)] >> _BIT_SHIFT(IRQn)) & 0xFF) >> (8 - __NVIC_PRIO_BITS))); + } /* get priority for device specific interrupts */ + } -/** \brief System Reset + /** \brief System Reset The function initiates a system reset request to reset the MCU. */ -__STATIC_INLINE void NVIC_SystemReset(void) -{ - __DSB(); /* Ensure all outstanding memory accesses included + __STATIC_INLINE void NVIC_SystemReset(void) + { + __DSB(); /* Ensure all outstanding memory accesses included buffered write are completed before reset */ - SCB->AIRCR = ((0x5FA << SCB_AIRCR_VECTKEY_Pos) | - SCB_AIRCR_SYSRESETREQ_Msk); - __DSB(); /* Ensure completion of memory access */ - while(1); /* wait until reset */ -} + SCB->AIRCR = ((0x5FA << SCB_AIRCR_VECTKEY_Pos) | + SCB_AIRCR_SYSRESETREQ_Msk); + __DSB(); /* Ensure completion of memory access */ + while (1) + ; /* wait until reset */ + } -/*@} end of CMSIS_Core_NVICFunctions */ + /*@} end of CMSIS_Core_NVICFunctions */ - - -/* ################################## SysTick function ############################################ */ -/** \ingroup CMSIS_Core_FunctionInterface + /* ################################## SysTick function ############################################ */ + /** \ingroup CMSIS_Core_FunctionInterface \defgroup CMSIS_Core_SysTickFunctions SysTick Functions \brief Functions that configure the System. @{ @@ -667,7 +650,7 @@ __STATIC_INLINE void NVIC_SystemReset(void) #if (__Vendor_SysTickConfig == 0) -/** \brief System Tick Configuration + /** \brief System Tick Configuration The function initializes the System Timer and its interrupt, and starts the System Tick Timer. Counter is in free running mode to generate periodic interrupts. @@ -682,25 +665,23 @@ __STATIC_INLINE void NVIC_SystemReset(void) must contain a vendor-specific implementation of this function. */ -__STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks) -{ - if ((ticks - 1) > SysTick_LOAD_RELOAD_Msk) return (1); /* Reload value impossible */ - - SysTick->LOAD = ticks - 1; /* set reload register */ - NVIC_SetPriority (SysTick_IRQn, (1<<__NVIC_PRIO_BITS) - 1); /* set Priority for Systick Interrupt */ - SysTick->VAL = 0; /* Load the SysTick Counter Value */ - SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk | - SysTick_CTRL_TICKINT_Msk | - SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */ - return (0); /* Function successful */ -} + __STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks) + { + if ((ticks - 1) > SysTick_LOAD_RELOAD_Msk) + return (1); /* Reload value impossible */ + + SysTick->LOAD = ticks - 1; /* set reload register */ + NVIC_SetPriority(SysTick_IRQn, (1 << __NVIC_PRIO_BITS) - 1); /* set Priority for Systick Interrupt */ + SysTick->VAL = 0; /* Load the SysTick Counter Value */ + SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk | + SysTick_CTRL_TICKINT_Msk | + SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */ + return (0); /* Function successful */ + } #endif -/*@} end of CMSIS_Core_SysTickFunctions */ - - - + /*@} end of CMSIS_Core_SysTickFunctions */ #ifdef __cplusplus } diff --git a/bsp/swm320-lq100/Libraries/CMSIS/CoreSupport/core_cm0plus.h b/bsp/swm320-lq100/Libraries/CMSIS/CoreSupport/core_cm0plus.h index 17e43984fc..a8af6dba6d 100644 --- a/bsp/swm320-lq100/Libraries/CMSIS/CoreSupport/core_cm0plus.h +++ b/bsp/swm320-lq100/Libraries/CMSIS/CoreSupport/core_cm0plus.h @@ -1,4 +1,4 @@ -/**************************************************************************//** +/**************************************************************************/ /** * @file core_cm0plus.h * @brief CMSIS Cortex-M0+ Core Peripheral Access Layer Header File * @version V4.00 @@ -34,16 +34,16 @@ POSSIBILITY OF SUCH DAMAGE. ---------------------------------------------------------------------------*/ - -#if defined ( __ICCARM__ ) - #pragma system_include /* treat file as system include file for MISRA check */ +#if defined(__ICCARM__) +#pragma system_include /* treat file as system include file for MISRA check */ #endif #ifndef __CORE_CM0PLUS_H_GENERIC #define __CORE_CM0PLUS_H_GENERIC #ifdef __cplusplus - extern "C" { +extern "C" +{ #endif /** \page CMSIS_MISRA_Exceptions MISRA-C:2004 Compliance Exceptions @@ -59,7 +59,6 @@ Function-like macros are used to allow more efficient code. */ - /******************************************************************************* * CMSIS definitions ******************************************************************************/ @@ -68,85 +67,84 @@ */ /* CMSIS CM0P definitions */ -#define __CM0PLUS_CMSIS_VERSION_MAIN (0x04) /*!< [31:16] CMSIS HAL main version */ -#define __CM0PLUS_CMSIS_VERSION_SUB (0x00) /*!< [15:0] CMSIS HAL sub version */ -#define __CM0PLUS_CMSIS_VERSION ((__CM0PLUS_CMSIS_VERSION_MAIN << 16) | \ - __CM0PLUS_CMSIS_VERSION_SUB) /*!< CMSIS HAL version number */ +#define __CM0PLUS_CMSIS_VERSION_MAIN (0x04) /*!< [31:16] CMSIS HAL main version */ +#define __CM0PLUS_CMSIS_VERSION_SUB (0x00) /*!< [15:0] CMSIS HAL sub version */ +#define __CM0PLUS_CMSIS_VERSION ((__CM0PLUS_CMSIS_VERSION_MAIN << 16) | \ + __CM0PLUS_CMSIS_VERSION_SUB) /*!< CMSIS HAL version number */ + +#define __CORTEX_M (0x00) /*!< Cortex-M Core */ + +#if defined(__CC_ARM) +#define __ASM __asm /*!< asm keyword for ARM Compiler */ +#define __INLINE __inline /*!< inline keyword for ARM Compiler */ +#define __STATIC_INLINE static __inline + +#elif defined(__GNUC__) +#define __ASM __asm /*!< asm keyword for GNU Compiler */ +#define __INLINE inline /*!< inline keyword for GNU Compiler */ +#define __STATIC_INLINE static inline + +#elif defined(__ICCARM__) +#define __ASM __asm /*!< asm keyword for IAR Compiler */ +#define __INLINE inline /*!< inline keyword for IAR Compiler. Only available in High optimization mode! */ +#define __STATIC_INLINE static inline + +#elif defined(__TMS470__) +#define __ASM __asm /*!< asm keyword for TI CCS Compiler */ +#define __STATIC_INLINE static inline + +#elif defined(__TASKING__) +#define __ASM __asm /*!< asm keyword for TASKING Compiler */ +#define __INLINE inline /*!< inline keyword for TASKING Compiler */ +#define __STATIC_INLINE static inline + +#elif defined(__CSMC__) +#define __packed +#define __ASM _asm /*!< asm keyword for COSMIC Compiler */ +#define __INLINE inline /*use -pc99 on compile line !< inline keyword for COSMIC Compiler */ +#define __STATIC_INLINE static inline -#define __CORTEX_M (0x00) /*!< Cortex-M Core */ - - -#if defined ( __CC_ARM ) - #define __ASM __asm /*!< asm keyword for ARM Compiler */ - #define __INLINE __inline /*!< inline keyword for ARM Compiler */ - #define __STATIC_INLINE static __inline +#endif -#elif defined ( __GNUC__ ) - #define __ASM __asm /*!< asm keyword for GNU Compiler */ - #define __INLINE inline /*!< inline keyword for GNU Compiler */ - #define __STATIC_INLINE static inline +/** __FPU_USED indicates whether an FPU is used or not. + This core does not support an FPU at all +*/ +#define __FPU_USED 0 -#elif defined ( __ICCARM__ ) - #define __ASM __asm /*!< asm keyword for IAR Compiler */ - #define __INLINE inline /*!< inline keyword for IAR Compiler. Only available in High optimization mode! */ - #define __STATIC_INLINE static inline +#if defined(__CC_ARM) +#if defined __TARGET_FPU_VFP +#warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" +#endif -#elif defined ( __TMS470__ ) - #define __ASM __asm /*!< asm keyword for TI CCS Compiler */ - #define __STATIC_INLINE static inline +#elif defined(__GNUC__) +#if defined(__VFP_FP__) && !defined(__SOFTFP__) +#warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" +#endif -#elif defined ( __TASKING__ ) - #define __ASM __asm /*!< asm keyword for TASKING Compiler */ - #define __INLINE inline /*!< inline keyword for TASKING Compiler */ - #define __STATIC_INLINE static inline +#elif defined(__ICCARM__) +#if defined __ARMVFP__ +#warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" +#endif -#elif defined ( __CSMC__ ) - #define __packed - #define __ASM _asm /*!< asm keyword for COSMIC Compiler */ - #define __INLINE inline /*use -pc99 on compile line !< inline keyword for COSMIC Compiler */ - #define __STATIC_INLINE static inline +#elif defined(__TMS470__) +#if defined __TI__VFP_SUPPORT____ +#warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" +#endif +#elif defined(__TASKING__) +#if defined __FPU_VFP__ +#error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" #endif -/** __FPU_USED indicates whether an FPU is used or not. - This core does not support an FPU at all -*/ -#define __FPU_USED 0 - -#if defined ( __CC_ARM ) - #if defined __TARGET_FPU_VFP - #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" - #endif - -#elif defined ( __GNUC__ ) - #if defined (__VFP_FP__) && !defined(__SOFTFP__) - #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" - #endif - -#elif defined ( __ICCARM__ ) - #if defined __ARMVFP__ - #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" - #endif - -#elif defined ( __TMS470__ ) - #if defined __TI__VFP_SUPPORT____ - #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" - #endif - -#elif defined ( __TASKING__ ) - #if defined __FPU_VFP__ - #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" - #endif - -#elif defined ( __CSMC__ ) /* Cosmic */ - #if ( __CSMC__ & 0x400) // FPU present for parser - #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" - #endif +#elif defined(__CSMC__) /* Cosmic */ +#if (__CSMC__ & 0x400) // FPU present for parser +#error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" +#endif #endif -#include /* standard types definitions */ -#include /* Core Instruction Access */ -#include /* Core Function Access */ +#include /* standard types definitions */ +#include /* Core Instruction Access */ +#include /* Core Function Access */ #ifdef __cplusplus } @@ -160,35 +158,36 @@ #define __CORE_CM0PLUS_H_DEPENDANT #ifdef __cplusplus - extern "C" { +extern "C" +{ #endif /* check device defines and use defaults */ #if defined __CHECK_DEVICE_DEFINES - #ifndef __CM0PLUS_REV - #define __CM0PLUS_REV 0x0000 - #warning "__CM0PLUS_REV not defined in device header file; using default!" - #endif - - #ifndef __MPU_PRESENT - #define __MPU_PRESENT 0 - #warning "__MPU_PRESENT not defined in device header file; using default!" - #endif - - #ifndef __VTOR_PRESENT - #define __VTOR_PRESENT 0 - #warning "__VTOR_PRESENT not defined in device header file; using default!" - #endif - - #ifndef __NVIC_PRIO_BITS - #define __NVIC_PRIO_BITS 2 - #warning "__NVIC_PRIO_BITS not defined in device header file; using default!" - #endif - - #ifndef __Vendor_SysTickConfig - #define __Vendor_SysTickConfig 0 - #warning "__Vendor_SysTickConfig not defined in device header file; using default!" - #endif +#ifndef __CM0PLUS_REV +#define __CM0PLUS_REV 0x0000 +#warning "__CM0PLUS_REV not defined in device header file; using default!" +#endif + +#ifndef __MPU_PRESENT +#define __MPU_PRESENT 0 +#warning "__MPU_PRESENT not defined in device header file; using default!" +#endif + +#ifndef __VTOR_PRESENT +#define __VTOR_PRESENT 0 +#warning "__VTOR_PRESENT not defined in device header file; using default!" +#endif + +#ifndef __NVIC_PRIO_BITS +#define __NVIC_PRIO_BITS 2 +#warning "__NVIC_PRIO_BITS not defined in device header file; using default!" +#endif + +#ifndef __Vendor_SysTickConfig +#define __Vendor_SysTickConfig 0 +#warning "__Vendor_SysTickConfig not defined in device header file; using default!" +#endif #endif /* IO definitions (access restrictions to peripheral registers) */ @@ -200,18 +199,16 @@ \li for automatic generation of peripheral register debug information. */ #ifdef __cplusplus - #define __I volatile /*!< Defines 'read only' permissions */ +#define __I volatile /*!< Defines 'read only' permissions */ #else - #define __I volatile const /*!< Defines 'read only' permissions */ +#define __I volatile const /*!< Defines 'read only' permissions */ #endif -#define __O volatile /*!< Defines 'write only' permissions */ -#define __IO volatile /*!< Defines 'read / write' permissions */ +#define __O volatile /*!< Defines 'write only' permissions */ +#define __IO volatile /*!< Defines 'read / write' permissions */ -/*@} end of group Cortex-M0+ */ + /*@} end of group Cortex-M0+ */ - - -/******************************************************************************* + /******************************************************************************* * Register Abstraction Core Register contain: - Core Register @@ -220,371 +217,364 @@ - Core SysTick Register - Core MPU Register ******************************************************************************/ -/** \defgroup CMSIS_core_register Defines and Type Definitions + /** \defgroup CMSIS_core_register Defines and Type Definitions \brief Type definitions and defines for Cortex-M processor based devices. */ -/** \ingroup CMSIS_core_register + /** \ingroup CMSIS_core_register \defgroup CMSIS_CORE Status and Control Registers \brief Core Register type definitions. @{ */ -/** \brief Union type to access the Application Program Status Register (APSR). + /** \brief Union type to access the Application Program Status Register (APSR). */ -typedef union -{ - struct - { + typedef union + { + struct + { #if (__CORTEX_M != 0x04) - uint32_t _reserved0:27; /*!< bit: 0..26 Reserved */ + uint32_t _reserved0 : 27; /*!< bit: 0..26 Reserved */ #else - uint32_t _reserved0:16; /*!< bit: 0..15 Reserved */ - uint32_t GE:4; /*!< bit: 16..19 Greater than or Equal flags */ - uint32_t _reserved1:7; /*!< bit: 20..26 Reserved */ + uint32_t _reserved0 : 16; /*!< bit: 0..15 Reserved */ + uint32_t GE : 4; /*!< bit: 16..19 Greater than or Equal flags */ + uint32_t _reserved1 : 7; /*!< bit: 20..26 Reserved */ #endif - uint32_t Q:1; /*!< bit: 27 Saturation condition flag */ - uint32_t V:1; /*!< bit: 28 Overflow condition code flag */ - uint32_t C:1; /*!< bit: 29 Carry condition code flag */ - uint32_t Z:1; /*!< bit: 30 Zero condition code flag */ - uint32_t N:1; /*!< bit: 31 Negative condition code flag */ - } b; /*!< Structure used for bit access */ - uint32_t w; /*!< Type used for word access */ -} APSR_Type; - - -/** \brief Union type to access the Interrupt Program Status Register (IPSR). + uint32_t Q : 1; /*!< bit: 27 Saturation condition flag */ + uint32_t V : 1; /*!< bit: 28 Overflow condition code flag */ + uint32_t C : 1; /*!< bit: 29 Carry condition code flag */ + uint32_t Z : 1; /*!< bit: 30 Zero condition code flag */ + uint32_t N : 1; /*!< bit: 31 Negative condition code flag */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ + } APSR_Type; + + /** \brief Union type to access the Interrupt Program Status Register (IPSR). */ -typedef union -{ - struct - { - uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */ - uint32_t _reserved0:23; /*!< bit: 9..31 Reserved */ - } b; /*!< Structure used for bit access */ - uint32_t w; /*!< Type used for word access */ -} IPSR_Type; - - -/** \brief Union type to access the Special-Purpose Program Status Registers (xPSR). + typedef union + { + struct + { + uint32_t ISR : 9; /*!< bit: 0.. 8 Exception number */ + uint32_t _reserved0 : 23; /*!< bit: 9..31 Reserved */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ + } IPSR_Type; + + /** \brief Union type to access the Special-Purpose Program Status Registers (xPSR). */ -typedef union -{ - struct - { - uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */ + typedef union + { + struct + { + uint32_t ISR : 9; /*!< bit: 0.. 8 Exception number */ #if (__CORTEX_M != 0x04) - uint32_t _reserved0:15; /*!< bit: 9..23 Reserved */ + uint32_t _reserved0 : 15; /*!< bit: 9..23 Reserved */ #else - uint32_t _reserved0:7; /*!< bit: 9..15 Reserved */ - uint32_t GE:4; /*!< bit: 16..19 Greater than or Equal flags */ - uint32_t _reserved1:4; /*!< bit: 20..23 Reserved */ + uint32_t _reserved0 : 7; /*!< bit: 9..15 Reserved */ + uint32_t GE : 4; /*!< bit: 16..19 Greater than or Equal flags */ + uint32_t _reserved1 : 4; /*!< bit: 20..23 Reserved */ #endif - uint32_t T:1; /*!< bit: 24 Thumb bit (read 0) */ - uint32_t IT:2; /*!< bit: 25..26 saved IT state (read 0) */ - uint32_t Q:1; /*!< bit: 27 Saturation condition flag */ - uint32_t V:1; /*!< bit: 28 Overflow condition code flag */ - uint32_t C:1; /*!< bit: 29 Carry condition code flag */ - uint32_t Z:1; /*!< bit: 30 Zero condition code flag */ - uint32_t N:1; /*!< bit: 31 Negative condition code flag */ - } b; /*!< Structure used for bit access */ - uint32_t w; /*!< Type used for word access */ -} xPSR_Type; - - -/** \brief Union type to access the Control Registers (CONTROL). + uint32_t T : 1; /*!< bit: 24 Thumb bit (read 0) */ + uint32_t IT : 2; /*!< bit: 25..26 saved IT state (read 0) */ + uint32_t Q : 1; /*!< bit: 27 Saturation condition flag */ + uint32_t V : 1; /*!< bit: 28 Overflow condition code flag */ + uint32_t C : 1; /*!< bit: 29 Carry condition code flag */ + uint32_t Z : 1; /*!< bit: 30 Zero condition code flag */ + uint32_t N : 1; /*!< bit: 31 Negative condition code flag */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ + } xPSR_Type; + + /** \brief Union type to access the Control Registers (CONTROL). */ -typedef union -{ - struct - { - uint32_t nPRIV:1; /*!< bit: 0 Execution privilege in Thread mode */ - uint32_t SPSEL:1; /*!< bit: 1 Stack to be used */ - uint32_t FPCA:1; /*!< bit: 2 FP extension active flag */ - uint32_t _reserved0:29; /*!< bit: 3..31 Reserved */ - } b; /*!< Structure used for bit access */ - uint32_t w; /*!< Type used for word access */ -} CONTROL_Type; - -/*@} end of group CMSIS_CORE */ - - -/** \ingroup CMSIS_core_register + typedef union + { + struct + { + uint32_t nPRIV : 1; /*!< bit: 0 Execution privilege in Thread mode */ + uint32_t SPSEL : 1; /*!< bit: 1 Stack to be used */ + uint32_t FPCA : 1; /*!< bit: 2 FP extension active flag */ + uint32_t _reserved0 : 29; /*!< bit: 3..31 Reserved */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ + } CONTROL_Type; + + /*@} end of group CMSIS_CORE */ + + /** \ingroup CMSIS_core_register \defgroup CMSIS_NVIC Nested Vectored Interrupt Controller (NVIC) \brief Type definitions for the NVIC Registers @{ */ -/** \brief Structure type to access the Nested Vectored Interrupt Controller (NVIC). + /** \brief Structure type to access the Nested Vectored Interrupt Controller (NVIC). */ -typedef struct -{ - __IO uint32_t ISER[1]; /*!< Offset: 0x000 (R/W) Interrupt Set Enable Register */ - uint32_t RESERVED0[31]; - __IO uint32_t ICER[1]; /*!< Offset: 0x080 (R/W) Interrupt Clear Enable Register */ - uint32_t RSERVED1[31]; - __IO uint32_t ISPR[1]; /*!< Offset: 0x100 (R/W) Interrupt Set Pending Register */ - uint32_t RESERVED2[31]; - __IO uint32_t ICPR[1]; /*!< Offset: 0x180 (R/W) Interrupt Clear Pending Register */ - uint32_t RESERVED3[31]; - uint32_t RESERVED4[64]; - __IO uint32_t IP[8]; /*!< Offset: 0x300 (R/W) Interrupt Priority Register */ -} NVIC_Type; - -/*@} end of group CMSIS_NVIC */ - - -/** \ingroup CMSIS_core_register + typedef struct + { + __IO uint32_t ISER[1]; /*!< Offset: 0x000 (R/W) Interrupt Set Enable Register */ + uint32_t RESERVED0[31]; + __IO uint32_t ICER[1]; /*!< Offset: 0x080 (R/W) Interrupt Clear Enable Register */ + uint32_t RSERVED1[31]; + __IO uint32_t ISPR[1]; /*!< Offset: 0x100 (R/W) Interrupt Set Pending Register */ + uint32_t RESERVED2[31]; + __IO uint32_t ICPR[1]; /*!< Offset: 0x180 (R/W) Interrupt Clear Pending Register */ + uint32_t RESERVED3[31]; + uint32_t RESERVED4[64]; + __IO uint32_t IP[8]; /*!< Offset: 0x300 (R/W) Interrupt Priority Register */ + } NVIC_Type; + + /*@} end of group CMSIS_NVIC */ + + /** \ingroup CMSIS_core_register \defgroup CMSIS_SCB System Control Block (SCB) \brief Type definitions for the System Control Block Registers @{ */ -/** \brief Structure type to access the System Control Block (SCB). + /** \brief Structure type to access the System Control Block (SCB). */ -typedef struct -{ - __I uint32_t CPUID; /*!< Offset: 0x000 (R/ ) CPUID Base Register */ - __IO uint32_t ICSR; /*!< Offset: 0x004 (R/W) Interrupt Control and State Register */ + typedef struct + { + __I uint32_t CPUID; /*!< Offset: 0x000 (R/ ) CPUID Base Register */ + __IO uint32_t ICSR; /*!< Offset: 0x004 (R/W) Interrupt Control and State Register */ #if (__VTOR_PRESENT == 1) - __IO uint32_t VTOR; /*!< Offset: 0x008 (R/W) Vector Table Offset Register */ + __IO uint32_t VTOR; /*!< Offset: 0x008 (R/W) Vector Table Offset Register */ #else - uint32_t RESERVED0; + uint32_t RESERVED0; #endif - __IO uint32_t AIRCR; /*!< Offset: 0x00C (R/W) Application Interrupt and Reset Control Register */ - __IO uint32_t SCR; /*!< Offset: 0x010 (R/W) System Control Register */ - __IO uint32_t CCR; /*!< Offset: 0x014 (R/W) Configuration Control Register */ - uint32_t RESERVED1; - __IO uint32_t SHP[2]; /*!< Offset: 0x01C (R/W) System Handlers Priority Registers. [0] is RESERVED */ - __IO uint32_t SHCSR; /*!< Offset: 0x024 (R/W) System Handler Control and State Register */ -} SCB_Type; + __IO uint32_t AIRCR; /*!< Offset: 0x00C (R/W) Application Interrupt and Reset Control Register */ + __IO uint32_t SCR; /*!< Offset: 0x010 (R/W) System Control Register */ + __IO uint32_t CCR; /*!< Offset: 0x014 (R/W) Configuration Control Register */ + uint32_t RESERVED1; + __IO uint32_t SHP[2]; /*!< Offset: 0x01C (R/W) System Handlers Priority Registers. [0] is RESERVED */ + __IO uint32_t SHCSR; /*!< Offset: 0x024 (R/W) System Handler Control and State Register */ + } SCB_Type; /* SCB CPUID Register Definitions */ -#define SCB_CPUID_IMPLEMENTER_Pos 24 /*!< SCB CPUID: IMPLEMENTER Position */ -#define SCB_CPUID_IMPLEMENTER_Msk (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos) /*!< SCB CPUID: IMPLEMENTER Mask */ +#define SCB_CPUID_IMPLEMENTER_Pos 24 /*!< SCB CPUID: IMPLEMENTER Position */ +#define SCB_CPUID_IMPLEMENTER_Msk (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos) /*!< SCB CPUID: IMPLEMENTER Mask */ -#define SCB_CPUID_VARIANT_Pos 20 /*!< SCB CPUID: VARIANT Position */ -#define SCB_CPUID_VARIANT_Msk (0xFUL << SCB_CPUID_VARIANT_Pos) /*!< SCB CPUID: VARIANT Mask */ +#define SCB_CPUID_VARIANT_Pos 20 /*!< SCB CPUID: VARIANT Position */ +#define SCB_CPUID_VARIANT_Msk (0xFUL << SCB_CPUID_VARIANT_Pos) /*!< SCB CPUID: VARIANT Mask */ -#define SCB_CPUID_ARCHITECTURE_Pos 16 /*!< SCB CPUID: ARCHITECTURE Position */ -#define SCB_CPUID_ARCHITECTURE_Msk (0xFUL << SCB_CPUID_ARCHITECTURE_Pos) /*!< SCB CPUID: ARCHITECTURE Mask */ +#define SCB_CPUID_ARCHITECTURE_Pos 16 /*!< SCB CPUID: ARCHITECTURE Position */ +#define SCB_CPUID_ARCHITECTURE_Msk (0xFUL << SCB_CPUID_ARCHITECTURE_Pos) /*!< SCB CPUID: ARCHITECTURE Mask */ -#define SCB_CPUID_PARTNO_Pos 4 /*!< SCB CPUID: PARTNO Position */ -#define SCB_CPUID_PARTNO_Msk (0xFFFUL << SCB_CPUID_PARTNO_Pos) /*!< SCB CPUID: PARTNO Mask */ +#define SCB_CPUID_PARTNO_Pos 4 /*!< SCB CPUID: PARTNO Position */ +#define SCB_CPUID_PARTNO_Msk (0xFFFUL << SCB_CPUID_PARTNO_Pos) /*!< SCB CPUID: PARTNO Mask */ -#define SCB_CPUID_REVISION_Pos 0 /*!< SCB CPUID: REVISION Position */ -#define SCB_CPUID_REVISION_Msk (0xFUL << SCB_CPUID_REVISION_Pos) /*!< SCB CPUID: REVISION Mask */ +#define SCB_CPUID_REVISION_Pos 0 /*!< SCB CPUID: REVISION Position */ +#define SCB_CPUID_REVISION_Msk (0xFUL << SCB_CPUID_REVISION_Pos) /*!< SCB CPUID: REVISION Mask */ /* SCB Interrupt Control State Register Definitions */ -#define SCB_ICSR_NMIPENDSET_Pos 31 /*!< SCB ICSR: NMIPENDSET Position */ -#define SCB_ICSR_NMIPENDSET_Msk (1UL << SCB_ICSR_NMIPENDSET_Pos) /*!< SCB ICSR: NMIPENDSET Mask */ +#define SCB_ICSR_NMIPENDSET_Pos 31 /*!< SCB ICSR: NMIPENDSET Position */ +#define SCB_ICSR_NMIPENDSET_Msk (1UL << SCB_ICSR_NMIPENDSET_Pos) /*!< SCB ICSR: NMIPENDSET Mask */ -#define SCB_ICSR_PENDSVSET_Pos 28 /*!< SCB ICSR: PENDSVSET Position */ -#define SCB_ICSR_PENDSVSET_Msk (1UL << SCB_ICSR_PENDSVSET_Pos) /*!< SCB ICSR: PENDSVSET Mask */ +#define SCB_ICSR_PENDSVSET_Pos 28 /*!< SCB ICSR: PENDSVSET Position */ +#define SCB_ICSR_PENDSVSET_Msk (1UL << SCB_ICSR_PENDSVSET_Pos) /*!< SCB ICSR: PENDSVSET Mask */ -#define SCB_ICSR_PENDSVCLR_Pos 27 /*!< SCB ICSR: PENDSVCLR Position */ -#define SCB_ICSR_PENDSVCLR_Msk (1UL << SCB_ICSR_PENDSVCLR_Pos) /*!< SCB ICSR: PENDSVCLR Mask */ +#define SCB_ICSR_PENDSVCLR_Pos 27 /*!< SCB ICSR: PENDSVCLR Position */ +#define SCB_ICSR_PENDSVCLR_Msk (1UL << SCB_ICSR_PENDSVCLR_Pos) /*!< SCB ICSR: PENDSVCLR Mask */ -#define SCB_ICSR_PENDSTSET_Pos 26 /*!< SCB ICSR: PENDSTSET Position */ -#define SCB_ICSR_PENDSTSET_Msk (1UL << SCB_ICSR_PENDSTSET_Pos) /*!< SCB ICSR: PENDSTSET Mask */ +#define SCB_ICSR_PENDSTSET_Pos 26 /*!< SCB ICSR: PENDSTSET Position */ +#define SCB_ICSR_PENDSTSET_Msk (1UL << SCB_ICSR_PENDSTSET_Pos) /*!< SCB ICSR: PENDSTSET Mask */ -#define SCB_ICSR_PENDSTCLR_Pos 25 /*!< SCB ICSR: PENDSTCLR Position */ -#define SCB_ICSR_PENDSTCLR_Msk (1UL << SCB_ICSR_PENDSTCLR_Pos) /*!< SCB ICSR: PENDSTCLR Mask */ +#define SCB_ICSR_PENDSTCLR_Pos 25 /*!< SCB ICSR: PENDSTCLR Position */ +#define SCB_ICSR_PENDSTCLR_Msk (1UL << SCB_ICSR_PENDSTCLR_Pos) /*!< SCB ICSR: PENDSTCLR Mask */ -#define SCB_ICSR_ISRPREEMPT_Pos 23 /*!< SCB ICSR: ISRPREEMPT Position */ -#define SCB_ICSR_ISRPREEMPT_Msk (1UL << SCB_ICSR_ISRPREEMPT_Pos) /*!< SCB ICSR: ISRPREEMPT Mask */ +#define SCB_ICSR_ISRPREEMPT_Pos 23 /*!< SCB ICSR: ISRPREEMPT Position */ +#define SCB_ICSR_ISRPREEMPT_Msk (1UL << SCB_ICSR_ISRPREEMPT_Pos) /*!< SCB ICSR: ISRPREEMPT Mask */ -#define SCB_ICSR_ISRPENDING_Pos 22 /*!< SCB ICSR: ISRPENDING Position */ -#define SCB_ICSR_ISRPENDING_Msk (1UL << SCB_ICSR_ISRPENDING_Pos) /*!< SCB ICSR: ISRPENDING Mask */ +#define SCB_ICSR_ISRPENDING_Pos 22 /*!< SCB ICSR: ISRPENDING Position */ +#define SCB_ICSR_ISRPENDING_Msk (1UL << SCB_ICSR_ISRPENDING_Pos) /*!< SCB ICSR: ISRPENDING Mask */ -#define SCB_ICSR_VECTPENDING_Pos 12 /*!< SCB ICSR: VECTPENDING Position */ -#define SCB_ICSR_VECTPENDING_Msk (0x1FFUL << SCB_ICSR_VECTPENDING_Pos) /*!< SCB ICSR: VECTPENDING Mask */ +#define SCB_ICSR_VECTPENDING_Pos 12 /*!< SCB ICSR: VECTPENDING Position */ +#define SCB_ICSR_VECTPENDING_Msk (0x1FFUL << SCB_ICSR_VECTPENDING_Pos) /*!< SCB ICSR: VECTPENDING Mask */ -#define SCB_ICSR_VECTACTIVE_Pos 0 /*!< SCB ICSR: VECTACTIVE Position */ -#define SCB_ICSR_VECTACTIVE_Msk (0x1FFUL << SCB_ICSR_VECTACTIVE_Pos) /*!< SCB ICSR: VECTACTIVE Mask */ +#define SCB_ICSR_VECTACTIVE_Pos 0 /*!< SCB ICSR: VECTACTIVE Position */ +#define SCB_ICSR_VECTACTIVE_Msk (0x1FFUL << SCB_ICSR_VECTACTIVE_Pos) /*!< SCB ICSR: VECTACTIVE Mask */ #if (__VTOR_PRESENT == 1) /* SCB Interrupt Control State Register Definitions */ -#define SCB_VTOR_TBLOFF_Pos 8 /*!< SCB VTOR: TBLOFF Position */ -#define SCB_VTOR_TBLOFF_Msk (0xFFFFFFUL << SCB_VTOR_TBLOFF_Pos) /*!< SCB VTOR: TBLOFF Mask */ +#define SCB_VTOR_TBLOFF_Pos 8 /*!< SCB VTOR: TBLOFF Position */ +#define SCB_VTOR_TBLOFF_Msk (0xFFFFFFUL << SCB_VTOR_TBLOFF_Pos) /*!< SCB VTOR: TBLOFF Mask */ #endif /* SCB Application Interrupt and Reset Control Register Definitions */ -#define SCB_AIRCR_VECTKEY_Pos 16 /*!< SCB AIRCR: VECTKEY Position */ -#define SCB_AIRCR_VECTKEY_Msk (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos) /*!< SCB AIRCR: VECTKEY Mask */ +#define SCB_AIRCR_VECTKEY_Pos 16 /*!< SCB AIRCR: VECTKEY Position */ +#define SCB_AIRCR_VECTKEY_Msk (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos) /*!< SCB AIRCR: VECTKEY Mask */ -#define SCB_AIRCR_VECTKEYSTAT_Pos 16 /*!< SCB AIRCR: VECTKEYSTAT Position */ -#define SCB_AIRCR_VECTKEYSTAT_Msk (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos) /*!< SCB AIRCR: VECTKEYSTAT Mask */ +#define SCB_AIRCR_VECTKEYSTAT_Pos 16 /*!< SCB AIRCR: VECTKEYSTAT Position */ +#define SCB_AIRCR_VECTKEYSTAT_Msk (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos) /*!< SCB AIRCR: VECTKEYSTAT Mask */ -#define SCB_AIRCR_ENDIANESS_Pos 15 /*!< SCB AIRCR: ENDIANESS Position */ -#define SCB_AIRCR_ENDIANESS_Msk (1UL << SCB_AIRCR_ENDIANESS_Pos) /*!< SCB AIRCR: ENDIANESS Mask */ +#define SCB_AIRCR_ENDIANESS_Pos 15 /*!< SCB AIRCR: ENDIANESS Position */ +#define SCB_AIRCR_ENDIANESS_Msk (1UL << SCB_AIRCR_ENDIANESS_Pos) /*!< SCB AIRCR: ENDIANESS Mask */ -#define SCB_AIRCR_SYSRESETREQ_Pos 2 /*!< SCB AIRCR: SYSRESETREQ Position */ -#define SCB_AIRCR_SYSRESETREQ_Msk (1UL << SCB_AIRCR_SYSRESETREQ_Pos) /*!< SCB AIRCR: SYSRESETREQ Mask */ +#define SCB_AIRCR_SYSRESETREQ_Pos 2 /*!< SCB AIRCR: SYSRESETREQ Position */ +#define SCB_AIRCR_SYSRESETREQ_Msk (1UL << SCB_AIRCR_SYSRESETREQ_Pos) /*!< SCB AIRCR: SYSRESETREQ Mask */ -#define SCB_AIRCR_VECTCLRACTIVE_Pos 1 /*!< SCB AIRCR: VECTCLRACTIVE Position */ -#define SCB_AIRCR_VECTCLRACTIVE_Msk (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos) /*!< SCB AIRCR: VECTCLRACTIVE Mask */ +#define SCB_AIRCR_VECTCLRACTIVE_Pos 1 /*!< SCB AIRCR: VECTCLRACTIVE Position */ +#define SCB_AIRCR_VECTCLRACTIVE_Msk (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos) /*!< SCB AIRCR: VECTCLRACTIVE Mask */ /* SCB System Control Register Definitions */ -#define SCB_SCR_SEVONPEND_Pos 4 /*!< SCB SCR: SEVONPEND Position */ -#define SCB_SCR_SEVONPEND_Msk (1UL << SCB_SCR_SEVONPEND_Pos) /*!< SCB SCR: SEVONPEND Mask */ +#define SCB_SCR_SEVONPEND_Pos 4 /*!< SCB SCR: SEVONPEND Position */ +#define SCB_SCR_SEVONPEND_Msk (1UL << SCB_SCR_SEVONPEND_Pos) /*!< SCB SCR: SEVONPEND Mask */ -#define SCB_SCR_SLEEPDEEP_Pos 2 /*!< SCB SCR: SLEEPDEEP Position */ -#define SCB_SCR_SLEEPDEEP_Msk (1UL << SCB_SCR_SLEEPDEEP_Pos) /*!< SCB SCR: SLEEPDEEP Mask */ +#define SCB_SCR_SLEEPDEEP_Pos 2 /*!< SCB SCR: SLEEPDEEP Position */ +#define SCB_SCR_SLEEPDEEP_Msk (1UL << SCB_SCR_SLEEPDEEP_Pos) /*!< SCB SCR: SLEEPDEEP Mask */ -#define SCB_SCR_SLEEPONEXIT_Pos 1 /*!< SCB SCR: SLEEPONEXIT Position */ -#define SCB_SCR_SLEEPONEXIT_Msk (1UL << SCB_SCR_SLEEPONEXIT_Pos) /*!< SCB SCR: SLEEPONEXIT Mask */ +#define SCB_SCR_SLEEPONEXIT_Pos 1 /*!< SCB SCR: SLEEPONEXIT Position */ +#define SCB_SCR_SLEEPONEXIT_Msk (1UL << SCB_SCR_SLEEPONEXIT_Pos) /*!< SCB SCR: SLEEPONEXIT Mask */ /* SCB Configuration Control Register Definitions */ -#define SCB_CCR_STKALIGN_Pos 9 /*!< SCB CCR: STKALIGN Position */ -#define SCB_CCR_STKALIGN_Msk (1UL << SCB_CCR_STKALIGN_Pos) /*!< SCB CCR: STKALIGN Mask */ +#define SCB_CCR_STKALIGN_Pos 9 /*!< SCB CCR: STKALIGN Position */ +#define SCB_CCR_STKALIGN_Msk (1UL << SCB_CCR_STKALIGN_Pos) /*!< SCB CCR: STKALIGN Mask */ -#define SCB_CCR_UNALIGN_TRP_Pos 3 /*!< SCB CCR: UNALIGN_TRP Position */ -#define SCB_CCR_UNALIGN_TRP_Msk (1UL << SCB_CCR_UNALIGN_TRP_Pos) /*!< SCB CCR: UNALIGN_TRP Mask */ +#define SCB_CCR_UNALIGN_TRP_Pos 3 /*!< SCB CCR: UNALIGN_TRP Position */ +#define SCB_CCR_UNALIGN_TRP_Msk (1UL << SCB_CCR_UNALIGN_TRP_Pos) /*!< SCB CCR: UNALIGN_TRP Mask */ /* SCB System Handler Control and State Register Definitions */ -#define SCB_SHCSR_SVCALLPENDED_Pos 15 /*!< SCB SHCSR: SVCALLPENDED Position */ -#define SCB_SHCSR_SVCALLPENDED_Msk (1UL << SCB_SHCSR_SVCALLPENDED_Pos) /*!< SCB SHCSR: SVCALLPENDED Mask */ - -/*@} end of group CMSIS_SCB */ +#define SCB_SHCSR_SVCALLPENDED_Pos 15 /*!< SCB SHCSR: SVCALLPENDED Position */ +#define SCB_SHCSR_SVCALLPENDED_Msk (1UL << SCB_SHCSR_SVCALLPENDED_Pos) /*!< SCB SHCSR: SVCALLPENDED Mask */ + /*@} end of group CMSIS_SCB */ -/** \ingroup CMSIS_core_register + /** \ingroup CMSIS_core_register \defgroup CMSIS_SysTick System Tick Timer (SysTick) \brief Type definitions for the System Timer Registers. @{ */ -/** \brief Structure type to access the System Timer (SysTick). + /** \brief Structure type to access the System Timer (SysTick). */ -typedef struct -{ - __IO uint32_t CTRL; /*!< Offset: 0x000 (R/W) SysTick Control and Status Register */ - __IO uint32_t LOAD; /*!< Offset: 0x004 (R/W) SysTick Reload Value Register */ - __IO uint32_t VAL; /*!< Offset: 0x008 (R/W) SysTick Current Value Register */ - __I uint32_t CALIB; /*!< Offset: 0x00C (R/ ) SysTick Calibration Register */ -} SysTick_Type; + typedef struct + { + __IO uint32_t CTRL; /*!< Offset: 0x000 (R/W) SysTick Control and Status Register */ + __IO uint32_t LOAD; /*!< Offset: 0x004 (R/W) SysTick Reload Value Register */ + __IO uint32_t VAL; /*!< Offset: 0x008 (R/W) SysTick Current Value Register */ + __I uint32_t CALIB; /*!< Offset: 0x00C (R/ ) SysTick Calibration Register */ + } SysTick_Type; /* SysTick Control / Status Register Definitions */ -#define SysTick_CTRL_COUNTFLAG_Pos 16 /*!< SysTick CTRL: COUNTFLAG Position */ -#define SysTick_CTRL_COUNTFLAG_Msk (1UL << SysTick_CTRL_COUNTFLAG_Pos) /*!< SysTick CTRL: COUNTFLAG Mask */ +#define SysTick_CTRL_COUNTFLAG_Pos 16 /*!< SysTick CTRL: COUNTFLAG Position */ +#define SysTick_CTRL_COUNTFLAG_Msk (1UL << SysTick_CTRL_COUNTFLAG_Pos) /*!< SysTick CTRL: COUNTFLAG Mask */ -#define SysTick_CTRL_CLKSOURCE_Pos 2 /*!< SysTick CTRL: CLKSOURCE Position */ -#define SysTick_CTRL_CLKSOURCE_Msk (1UL << SysTick_CTRL_CLKSOURCE_Pos) /*!< SysTick CTRL: CLKSOURCE Mask */ +#define SysTick_CTRL_CLKSOURCE_Pos 2 /*!< SysTick CTRL: CLKSOURCE Position */ +#define SysTick_CTRL_CLKSOURCE_Msk (1UL << SysTick_CTRL_CLKSOURCE_Pos) /*!< SysTick CTRL: CLKSOURCE Mask */ -#define SysTick_CTRL_TICKINT_Pos 1 /*!< SysTick CTRL: TICKINT Position */ -#define SysTick_CTRL_TICKINT_Msk (1UL << SysTick_CTRL_TICKINT_Pos) /*!< SysTick CTRL: TICKINT Mask */ +#define SysTick_CTRL_TICKINT_Pos 1 /*!< SysTick CTRL: TICKINT Position */ +#define SysTick_CTRL_TICKINT_Msk (1UL << SysTick_CTRL_TICKINT_Pos) /*!< SysTick CTRL: TICKINT Mask */ -#define SysTick_CTRL_ENABLE_Pos 0 /*!< SysTick CTRL: ENABLE Position */ -#define SysTick_CTRL_ENABLE_Msk (1UL << SysTick_CTRL_ENABLE_Pos) /*!< SysTick CTRL: ENABLE Mask */ +#define SysTick_CTRL_ENABLE_Pos 0 /*!< SysTick CTRL: ENABLE Position */ +#define SysTick_CTRL_ENABLE_Msk (1UL << SysTick_CTRL_ENABLE_Pos) /*!< SysTick CTRL: ENABLE Mask */ /* SysTick Reload Register Definitions */ -#define SysTick_LOAD_RELOAD_Pos 0 /*!< SysTick LOAD: RELOAD Position */ -#define SysTick_LOAD_RELOAD_Msk (0xFFFFFFUL << SysTick_LOAD_RELOAD_Pos) /*!< SysTick LOAD: RELOAD Mask */ +#define SysTick_LOAD_RELOAD_Pos 0 /*!< SysTick LOAD: RELOAD Position */ +#define SysTick_LOAD_RELOAD_Msk (0xFFFFFFUL << SysTick_LOAD_RELOAD_Pos) /*!< SysTick LOAD: RELOAD Mask */ /* SysTick Current Register Definitions */ -#define SysTick_VAL_CURRENT_Pos 0 /*!< SysTick VAL: CURRENT Position */ -#define SysTick_VAL_CURRENT_Msk (0xFFFFFFUL << SysTick_VAL_CURRENT_Pos) /*!< SysTick VAL: CURRENT Mask */ +#define SysTick_VAL_CURRENT_Pos 0 /*!< SysTick VAL: CURRENT Position */ +#define SysTick_VAL_CURRENT_Msk (0xFFFFFFUL << SysTick_VAL_CURRENT_Pos) /*!< SysTick VAL: CURRENT Mask */ /* SysTick Calibration Register Definitions */ -#define SysTick_CALIB_NOREF_Pos 31 /*!< SysTick CALIB: NOREF Position */ -#define SysTick_CALIB_NOREF_Msk (1UL << SysTick_CALIB_NOREF_Pos) /*!< SysTick CALIB: NOREF Mask */ +#define SysTick_CALIB_NOREF_Pos 31 /*!< SysTick CALIB: NOREF Position */ +#define SysTick_CALIB_NOREF_Msk (1UL << SysTick_CALIB_NOREF_Pos) /*!< SysTick CALIB: NOREF Mask */ -#define SysTick_CALIB_SKEW_Pos 30 /*!< SysTick CALIB: SKEW Position */ -#define SysTick_CALIB_SKEW_Msk (1UL << SysTick_CALIB_SKEW_Pos) /*!< SysTick CALIB: SKEW Mask */ +#define SysTick_CALIB_SKEW_Pos 30 /*!< SysTick CALIB: SKEW Position */ +#define SysTick_CALIB_SKEW_Msk (1UL << SysTick_CALIB_SKEW_Pos) /*!< SysTick CALIB: SKEW Mask */ -#define SysTick_CALIB_TENMS_Pos 0 /*!< SysTick CALIB: TENMS Position */ -#define SysTick_CALIB_TENMS_Msk (0xFFFFFFUL << SysTick_CALIB_TENMS_Pos) /*!< SysTick CALIB: TENMS Mask */ +#define SysTick_CALIB_TENMS_Pos 0 /*!< SysTick CALIB: TENMS Position */ +#define SysTick_CALIB_TENMS_Msk (0xFFFFFFUL << SysTick_CALIB_TENMS_Pos) /*!< SysTick CALIB: TENMS Mask */ -/*@} end of group CMSIS_SysTick */ + /*@} end of group CMSIS_SysTick */ #if (__MPU_PRESENT == 1) -/** \ingroup CMSIS_core_register + /** \ingroup CMSIS_core_register \defgroup CMSIS_MPU Memory Protection Unit (MPU) \brief Type definitions for the Memory Protection Unit (MPU) @{ */ -/** \brief Structure type to access the Memory Protection Unit (MPU). + /** \brief Structure type to access the Memory Protection Unit (MPU). */ -typedef struct -{ - __I uint32_t TYPE; /*!< Offset: 0x000 (R/ ) MPU Type Register */ - __IO uint32_t CTRL; /*!< Offset: 0x004 (R/W) MPU Control Register */ - __IO uint32_t RNR; /*!< Offset: 0x008 (R/W) MPU Region RNRber Register */ - __IO uint32_t RBAR; /*!< Offset: 0x00C (R/W) MPU Region Base Address Register */ - __IO uint32_t RASR; /*!< Offset: 0x010 (R/W) MPU Region Attribute and Size Register */ -} MPU_Type; + typedef struct + { + __I uint32_t TYPE; /*!< Offset: 0x000 (R/ ) MPU Type Register */ + __IO uint32_t CTRL; /*!< Offset: 0x004 (R/W) MPU Control Register */ + __IO uint32_t RNR; /*!< Offset: 0x008 (R/W) MPU Region RNRber Register */ + __IO uint32_t RBAR; /*!< Offset: 0x00C (R/W) MPU Region Base Address Register */ + __IO uint32_t RASR; /*!< Offset: 0x010 (R/W) MPU Region Attribute and Size Register */ + } MPU_Type; /* MPU Type Register */ -#define MPU_TYPE_IREGION_Pos 16 /*!< MPU TYPE: IREGION Position */ -#define MPU_TYPE_IREGION_Msk (0xFFUL << MPU_TYPE_IREGION_Pos) /*!< MPU TYPE: IREGION Mask */ +#define MPU_TYPE_IREGION_Pos 16 /*!< MPU TYPE: IREGION Position */ +#define MPU_TYPE_IREGION_Msk (0xFFUL << MPU_TYPE_IREGION_Pos) /*!< MPU TYPE: IREGION Mask */ -#define MPU_TYPE_DREGION_Pos 8 /*!< MPU TYPE: DREGION Position */ -#define MPU_TYPE_DREGION_Msk (0xFFUL << MPU_TYPE_DREGION_Pos) /*!< MPU TYPE: DREGION Mask */ +#define MPU_TYPE_DREGION_Pos 8 /*!< MPU TYPE: DREGION Position */ +#define MPU_TYPE_DREGION_Msk (0xFFUL << MPU_TYPE_DREGION_Pos) /*!< MPU TYPE: DREGION Mask */ -#define MPU_TYPE_SEPARATE_Pos 0 /*!< MPU TYPE: SEPARATE Position */ -#define MPU_TYPE_SEPARATE_Msk (1UL << MPU_TYPE_SEPARATE_Pos) /*!< MPU TYPE: SEPARATE Mask */ +#define MPU_TYPE_SEPARATE_Pos 0 /*!< MPU TYPE: SEPARATE Position */ +#define MPU_TYPE_SEPARATE_Msk (1UL << MPU_TYPE_SEPARATE_Pos) /*!< MPU TYPE: SEPARATE Mask */ /* MPU Control Register */ -#define MPU_CTRL_PRIVDEFENA_Pos 2 /*!< MPU CTRL: PRIVDEFENA Position */ -#define MPU_CTRL_PRIVDEFENA_Msk (1UL << MPU_CTRL_PRIVDEFENA_Pos) /*!< MPU CTRL: PRIVDEFENA Mask */ +#define MPU_CTRL_PRIVDEFENA_Pos 2 /*!< MPU CTRL: PRIVDEFENA Position */ +#define MPU_CTRL_PRIVDEFENA_Msk (1UL << MPU_CTRL_PRIVDEFENA_Pos) /*!< MPU CTRL: PRIVDEFENA Mask */ -#define MPU_CTRL_HFNMIENA_Pos 1 /*!< MPU CTRL: HFNMIENA Position */ -#define MPU_CTRL_HFNMIENA_Msk (1UL << MPU_CTRL_HFNMIENA_Pos) /*!< MPU CTRL: HFNMIENA Mask */ +#define MPU_CTRL_HFNMIENA_Pos 1 /*!< MPU CTRL: HFNMIENA Position */ +#define MPU_CTRL_HFNMIENA_Msk (1UL << MPU_CTRL_HFNMIENA_Pos) /*!< MPU CTRL: HFNMIENA Mask */ -#define MPU_CTRL_ENABLE_Pos 0 /*!< MPU CTRL: ENABLE Position */ -#define MPU_CTRL_ENABLE_Msk (1UL << MPU_CTRL_ENABLE_Pos) /*!< MPU CTRL: ENABLE Mask */ +#define MPU_CTRL_ENABLE_Pos 0 /*!< MPU CTRL: ENABLE Position */ +#define MPU_CTRL_ENABLE_Msk (1UL << MPU_CTRL_ENABLE_Pos) /*!< MPU CTRL: ENABLE Mask */ /* MPU Region Number Register */ -#define MPU_RNR_REGION_Pos 0 /*!< MPU RNR: REGION Position */ -#define MPU_RNR_REGION_Msk (0xFFUL << MPU_RNR_REGION_Pos) /*!< MPU RNR: REGION Mask */ +#define MPU_RNR_REGION_Pos 0 /*!< MPU RNR: REGION Position */ +#define MPU_RNR_REGION_Msk (0xFFUL << MPU_RNR_REGION_Pos) /*!< MPU RNR: REGION Mask */ /* MPU Region Base Address Register */ -#define MPU_RBAR_ADDR_Pos 8 /*!< MPU RBAR: ADDR Position */ -#define MPU_RBAR_ADDR_Msk (0xFFFFFFUL << MPU_RBAR_ADDR_Pos) /*!< MPU RBAR: ADDR Mask */ +#define MPU_RBAR_ADDR_Pos 8 /*!< MPU RBAR: ADDR Position */ +#define MPU_RBAR_ADDR_Msk (0xFFFFFFUL << MPU_RBAR_ADDR_Pos) /*!< MPU RBAR: ADDR Mask */ -#define MPU_RBAR_VALID_Pos 4 /*!< MPU RBAR: VALID Position */ -#define MPU_RBAR_VALID_Msk (1UL << MPU_RBAR_VALID_Pos) /*!< MPU RBAR: VALID Mask */ +#define MPU_RBAR_VALID_Pos 4 /*!< MPU RBAR: VALID Position */ +#define MPU_RBAR_VALID_Msk (1UL << MPU_RBAR_VALID_Pos) /*!< MPU RBAR: VALID Mask */ -#define MPU_RBAR_REGION_Pos 0 /*!< MPU RBAR: REGION Position */ -#define MPU_RBAR_REGION_Msk (0xFUL << MPU_RBAR_REGION_Pos) /*!< MPU RBAR: REGION Mask */ +#define MPU_RBAR_REGION_Pos 0 /*!< MPU RBAR: REGION Position */ +#define MPU_RBAR_REGION_Msk (0xFUL << MPU_RBAR_REGION_Pos) /*!< MPU RBAR: REGION Mask */ /* MPU Region Attribute and Size Register */ -#define MPU_RASR_ATTRS_Pos 16 /*!< MPU RASR: MPU Region Attribute field Position */ -#define MPU_RASR_ATTRS_Msk (0xFFFFUL << MPU_RASR_ATTRS_Pos) /*!< MPU RASR: MPU Region Attribute field Mask */ +#define MPU_RASR_ATTRS_Pos 16 /*!< MPU RASR: MPU Region Attribute field Position */ +#define MPU_RASR_ATTRS_Msk (0xFFFFUL << MPU_RASR_ATTRS_Pos) /*!< MPU RASR: MPU Region Attribute field Mask */ -#define MPU_RASR_XN_Pos 28 /*!< MPU RASR: ATTRS.XN Position */ -#define MPU_RASR_XN_Msk (1UL << MPU_RASR_XN_Pos) /*!< MPU RASR: ATTRS.XN Mask */ +#define MPU_RASR_XN_Pos 28 /*!< MPU RASR: ATTRS.XN Position */ +#define MPU_RASR_XN_Msk (1UL << MPU_RASR_XN_Pos) /*!< MPU RASR: ATTRS.XN Mask */ -#define MPU_RASR_AP_Pos 24 /*!< MPU RASR: ATTRS.AP Position */ -#define MPU_RASR_AP_Msk (0x7UL << MPU_RASR_AP_Pos) /*!< MPU RASR: ATTRS.AP Mask */ +#define MPU_RASR_AP_Pos 24 /*!< MPU RASR: ATTRS.AP Position */ +#define MPU_RASR_AP_Msk (0x7UL << MPU_RASR_AP_Pos) /*!< MPU RASR: ATTRS.AP Mask */ -#define MPU_RASR_TEX_Pos 19 /*!< MPU RASR: ATTRS.TEX Position */ -#define MPU_RASR_TEX_Msk (0x7UL << MPU_RASR_TEX_Pos) /*!< MPU RASR: ATTRS.TEX Mask */ +#define MPU_RASR_TEX_Pos 19 /*!< MPU RASR: ATTRS.TEX Position */ +#define MPU_RASR_TEX_Msk (0x7UL << MPU_RASR_TEX_Pos) /*!< MPU RASR: ATTRS.TEX Mask */ -#define MPU_RASR_S_Pos 18 /*!< MPU RASR: ATTRS.S Position */ -#define MPU_RASR_S_Msk (1UL << MPU_RASR_S_Pos) /*!< MPU RASR: ATTRS.S Mask */ +#define MPU_RASR_S_Pos 18 /*!< MPU RASR: ATTRS.S Position */ +#define MPU_RASR_S_Msk (1UL << MPU_RASR_S_Pos) /*!< MPU RASR: ATTRS.S Mask */ -#define MPU_RASR_C_Pos 17 /*!< MPU RASR: ATTRS.C Position */ -#define MPU_RASR_C_Msk (1UL << MPU_RASR_C_Pos) /*!< MPU RASR: ATTRS.C Mask */ +#define MPU_RASR_C_Pos 17 /*!< MPU RASR: ATTRS.C Position */ +#define MPU_RASR_C_Msk (1UL << MPU_RASR_C_Pos) /*!< MPU RASR: ATTRS.C Mask */ -#define MPU_RASR_B_Pos 16 /*!< MPU RASR: ATTRS.B Position */ -#define MPU_RASR_B_Msk (1UL << MPU_RASR_B_Pos) /*!< MPU RASR: ATTRS.B Mask */ +#define MPU_RASR_B_Pos 16 /*!< MPU RASR: ATTRS.B Position */ +#define MPU_RASR_B_Msk (1UL << MPU_RASR_B_Pos) /*!< MPU RASR: ATTRS.B Mask */ -#define MPU_RASR_SRD_Pos 8 /*!< MPU RASR: Sub-Region Disable Position */ -#define MPU_RASR_SRD_Msk (0xFFUL << MPU_RASR_SRD_Pos) /*!< MPU RASR: Sub-Region Disable Mask */ +#define MPU_RASR_SRD_Pos 8 /*!< MPU RASR: Sub-Region Disable Position */ +#define MPU_RASR_SRD_Msk (0xFFUL << MPU_RASR_SRD_Pos) /*!< MPU RASR: Sub-Region Disable Mask */ -#define MPU_RASR_SIZE_Pos 1 /*!< MPU RASR: Region Size Field Position */ -#define MPU_RASR_SIZE_Msk (0x1FUL << MPU_RASR_SIZE_Pos) /*!< MPU RASR: Region Size Field Mask */ +#define MPU_RASR_SIZE_Pos 1 /*!< MPU RASR: Region Size Field Position */ +#define MPU_RASR_SIZE_Msk (0x1FUL << MPU_RASR_SIZE_Pos) /*!< MPU RASR: Region Size Field Mask */ -#define MPU_RASR_ENABLE_Pos 0 /*!< MPU RASR: Region enable bit Position */ -#define MPU_RASR_ENABLE_Msk (1UL << MPU_RASR_ENABLE_Pos) /*!< MPU RASR: Region enable bit Disable Mask */ +#define MPU_RASR_ENABLE_Pos 0 /*!< MPU RASR: Region enable bit Position */ +#define MPU_RASR_ENABLE_Msk (1UL << MPU_RASR_ENABLE_Pos) /*!< MPU RASR: Region enable bit Disable Mask */ /*@} end of group CMSIS_MPU */ #endif - /** \ingroup CMSIS_core_register \defgroup CMSIS_CoreDebug Core Debug Registers (CoreDebug) \brief Cortex-M0+ Core Debug Registers (DCB registers, SHCSR, and DFSR) @@ -594,7 +584,6 @@ typedef struct */ /*@} end of group CMSIS_CoreDebug */ - /** \ingroup CMSIS_core_register \defgroup CMSIS_core_base Core Definitions \brief Definitions for base addresses, unions, and structures. @@ -602,24 +591,22 @@ typedef struct */ /* Memory mapping of Cortex-M0+ Hardware */ -#define SCS_BASE (0xE000E000UL) /*!< System Control Space Base Address */ -#define SysTick_BASE (SCS_BASE + 0x0010UL) /*!< SysTick Base Address */ -#define NVIC_BASE (SCS_BASE + 0x0100UL) /*!< NVIC Base Address */ -#define SCB_BASE (SCS_BASE + 0x0D00UL) /*!< System Control Block Base Address */ +#define SCS_BASE (0xE000E000UL) /*!< System Control Space Base Address */ +#define SysTick_BASE (SCS_BASE + 0x0010UL) /*!< SysTick Base Address */ +#define NVIC_BASE (SCS_BASE + 0x0100UL) /*!< NVIC Base Address */ +#define SCB_BASE (SCS_BASE + 0x0D00UL) /*!< System Control Block Base Address */ -#define SCB ((SCB_Type *) SCB_BASE ) /*!< SCB configuration struct */ -#define SysTick ((SysTick_Type *) SysTick_BASE ) /*!< SysTick configuration struct */ -#define NVIC ((NVIC_Type *) NVIC_BASE ) /*!< NVIC configuration struct */ +#define SCB ((SCB_Type *)SCB_BASE) /*!< SCB configuration struct */ +#define SysTick ((SysTick_Type *)SysTick_BASE) /*!< SysTick configuration struct */ +#define NVIC ((NVIC_Type *)NVIC_BASE) /*!< NVIC configuration struct */ #if (__MPU_PRESENT == 1) - #define MPU_BASE (SCS_BASE + 0x0D90UL) /*!< Memory Protection Unit */ - #define MPU ((MPU_Type *) MPU_BASE ) /*!< Memory Protection Unit */ +#define MPU_BASE (SCS_BASE + 0x0D90UL) /*!< Memory Protection Unit */ +#define MPU ((MPU_Type *)MPU_BASE) /*!< Memory Protection Unit */ #endif /*@} */ - - /******************************************************************************* * Hardware Abstraction Layer Core Function Interface contains: @@ -630,8 +617,6 @@ typedef struct /** \defgroup CMSIS_Core_FunctionInterface Functions and Instructions Reference */ - - /* ########################## NVIC functions #################################### */ /** \ingroup CMSIS_Core_FunctionInterface \defgroup CMSIS_Core_NVICFunctions NVIC Functions @@ -641,36 +626,33 @@ typedef struct /* Interrupt Priorities are WORD accessible only under ARMv6M */ /* The following MACROS handle generation of the register offset and byte masks */ -#define _BIT_SHIFT(IRQn) ( (((uint32_t)(IRQn) ) & 0x03) * 8 ) -#define _SHP_IDX(IRQn) ( ((((uint32_t)(IRQn) & 0x0F)-8) >> 2) ) -#define _IP_IDX(IRQn) ( ((uint32_t)(IRQn) >> 2) ) - +#define _BIT_SHIFT(IRQn) ((((uint32_t)(IRQn)) & 0x03) * 8) +#define _SHP_IDX(IRQn) (((((uint32_t)(IRQn)&0x0F) - 8) >> 2)) +#define _IP_IDX(IRQn) (((uint32_t)(IRQn) >> 2)) -/** \brief Enable External Interrupt + /** \brief Enable External Interrupt The function enables a device-specific interrupt in the NVIC interrupt controller. \param [in] IRQn External interrupt number. Value cannot be negative. */ -__STATIC_INLINE void NVIC_EnableIRQ(IRQn_Type IRQn) -{ - NVIC->ISER[0] = (1 << ((uint32_t)(IRQn) & 0x1F)); -} - + __STATIC_INLINE void NVIC_EnableIRQ(IRQn_Type IRQn) + { + NVIC->ISER[0] = (1 << ((uint32_t)(IRQn)&0x1F)); + } -/** \brief Disable External Interrupt + /** \brief Disable External Interrupt The function disables a device-specific interrupt in the NVIC interrupt controller. \param [in] IRQn External interrupt number. Value cannot be negative. */ -__STATIC_INLINE void NVIC_DisableIRQ(IRQn_Type IRQn) -{ - NVIC->ICER[0] = (1 << ((uint32_t)(IRQn) & 0x1F)); -} - + __STATIC_INLINE void NVIC_DisableIRQ(IRQn_Type IRQn) + { + NVIC->ICER[0] = (1 << ((uint32_t)(IRQn)&0x1F)); + } -/** \brief Get Pending Interrupt + /** \brief Get Pending Interrupt The function reads the pending register in the NVIC and returns the pending bit for the specified interrupt. @@ -680,37 +662,34 @@ __STATIC_INLINE void NVIC_DisableIRQ(IRQn_Type IRQn) \return 0 Interrupt status is not pending. \return 1 Interrupt status is pending. */ -__STATIC_INLINE uint32_t NVIC_GetPendingIRQ(IRQn_Type IRQn) -{ - return((uint32_t) ((NVIC->ISPR[0] & (1 << ((uint32_t)(IRQn) & 0x1F)))?1:0)); -} - + __STATIC_INLINE uint32_t NVIC_GetPendingIRQ(IRQn_Type IRQn) + { + return ((uint32_t)((NVIC->ISPR[0] & (1 << ((uint32_t)(IRQn)&0x1F))) ? 1 : 0)); + } -/** \brief Set Pending Interrupt + /** \brief Set Pending Interrupt The function sets the pending bit of an external interrupt. \param [in] IRQn Interrupt number. Value cannot be negative. */ -__STATIC_INLINE void NVIC_SetPendingIRQ(IRQn_Type IRQn) -{ - NVIC->ISPR[0] = (1 << ((uint32_t)(IRQn) & 0x1F)); -} - + __STATIC_INLINE void NVIC_SetPendingIRQ(IRQn_Type IRQn) + { + NVIC->ISPR[0] = (1 << ((uint32_t)(IRQn)&0x1F)); + } -/** \brief Clear Pending Interrupt + /** \brief Clear Pending Interrupt The function clears the pending bit of an external interrupt. \param [in] IRQn External interrupt number. Value cannot be negative. */ -__STATIC_INLINE void NVIC_ClearPendingIRQ(IRQn_Type IRQn) -{ - NVIC->ICPR[0] = (1 << ((uint32_t)(IRQn) & 0x1F)); /* Clear pending interrupt */ -} - + __STATIC_INLINE void NVIC_ClearPendingIRQ(IRQn_Type IRQn) + { + NVIC->ICPR[0] = (1 << ((uint32_t)(IRQn)&0x1F)); /* Clear pending interrupt */ + } -/** \brief Set Interrupt Priority + /** \brief Set Interrupt Priority The function sets the priority of an interrupt. @@ -719,18 +698,21 @@ __STATIC_INLINE void NVIC_ClearPendingIRQ(IRQn_Type IRQn) \param [in] IRQn Interrupt number. \param [in] priority Priority to set. */ -__STATIC_INLINE void NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority) -{ - if(IRQn < 0) { - SCB->SHP[_SHP_IDX(IRQn)] = (SCB->SHP[_SHP_IDX(IRQn)] & ~(0xFF << _BIT_SHIFT(IRQn))) | - (((priority << (8 - __NVIC_PRIO_BITS)) & 0xFF) << _BIT_SHIFT(IRQn)); } - else { - NVIC->IP[_IP_IDX(IRQn)] = (NVIC->IP[_IP_IDX(IRQn)] & ~(0xFF << _BIT_SHIFT(IRQn))) | - (((priority << (8 - __NVIC_PRIO_BITS)) & 0xFF) << _BIT_SHIFT(IRQn)); } -} - - -/** \brief Get Interrupt Priority + __STATIC_INLINE void NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority) + { + if (IRQn < 0) + { + SCB->SHP[_SHP_IDX(IRQn)] = (SCB->SHP[_SHP_IDX(IRQn)] & ~(0xFF << _BIT_SHIFT(IRQn))) | + (((priority << (8 - __NVIC_PRIO_BITS)) & 0xFF) << _BIT_SHIFT(IRQn)); + } + else + { + NVIC->IP[_IP_IDX(IRQn)] = (NVIC->IP[_IP_IDX(IRQn)] & ~(0xFF << _BIT_SHIFT(IRQn))) | + (((priority << (8 - __NVIC_PRIO_BITS)) & 0xFF) << _BIT_SHIFT(IRQn)); + } + } + + /** \brief Get Interrupt Priority The function reads the priority of an interrupt. The interrupt number can be positive to specify an external (device specific) @@ -741,36 +723,38 @@ __STATIC_INLINE void NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority) \return Interrupt Priority. Value is aligned automatically to the implemented priority bits of the microcontroller. */ -__STATIC_INLINE uint32_t NVIC_GetPriority(IRQn_Type IRQn) -{ + __STATIC_INLINE uint32_t NVIC_GetPriority(IRQn_Type IRQn) + { - if(IRQn < 0) { - return((uint32_t)(((SCB->SHP[_SHP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) & 0xFF) >> (8 - __NVIC_PRIO_BITS))); } /* get priority for Cortex-M0 system interrupts */ - else { - return((uint32_t)(((NVIC->IP[ _IP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) & 0xFF) >> (8 - __NVIC_PRIO_BITS))); } /* get priority for device specific interrupts */ -} + if (IRQn < 0) + { + return ((uint32_t)(((SCB->SHP[_SHP_IDX(IRQn)] >> _BIT_SHIFT(IRQn)) & 0xFF) >> (8 - __NVIC_PRIO_BITS))); + } /* get priority for Cortex-M0 system interrupts */ + else + { + return ((uint32_t)(((NVIC->IP[_IP_IDX(IRQn)] >> _BIT_SHIFT(IRQn)) & 0xFF) >> (8 - __NVIC_PRIO_BITS))); + } /* get priority for device specific interrupts */ + } - -/** \brief System Reset + /** \brief System Reset The function initiates a system reset request to reset the MCU. */ -__STATIC_INLINE void NVIC_SystemReset(void) -{ - __DSB(); /* Ensure all outstanding memory accesses included + __STATIC_INLINE void NVIC_SystemReset(void) + { + __DSB(); /* Ensure all outstanding memory accesses included buffered write are completed before reset */ - SCB->AIRCR = ((0x5FA << SCB_AIRCR_VECTKEY_Pos) | - SCB_AIRCR_SYSRESETREQ_Msk); - __DSB(); /* Ensure completion of memory access */ - while(1); /* wait until reset */ -} + SCB->AIRCR = ((0x5FA << SCB_AIRCR_VECTKEY_Pos) | + SCB_AIRCR_SYSRESETREQ_Msk); + __DSB(); /* Ensure completion of memory access */ + while (1) + ; /* wait until reset */ + } -/*@} end of CMSIS_Core_NVICFunctions */ + /*@} end of CMSIS_Core_NVICFunctions */ - - -/* ################################## SysTick function ############################################ */ -/** \ingroup CMSIS_Core_FunctionInterface + /* ################################## SysTick function ############################################ */ + /** \ingroup CMSIS_Core_FunctionInterface \defgroup CMSIS_Core_SysTickFunctions SysTick Functions \brief Functions that configure the System. @{ @@ -778,7 +762,7 @@ __STATIC_INLINE void NVIC_SystemReset(void) #if (__Vendor_SysTickConfig == 0) -/** \brief System Tick Configuration + /** \brief System Tick Configuration The function initializes the System Timer and its interrupt, and starts the System Tick Timer. Counter is in free running mode to generate periodic interrupts. @@ -793,25 +777,23 @@ __STATIC_INLINE void NVIC_SystemReset(void) must contain a vendor-specific implementation of this function. */ -__STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks) -{ - if ((ticks - 1) > SysTick_LOAD_RELOAD_Msk) return (1); /* Reload value impossible */ - - SysTick->LOAD = ticks - 1; /* set reload register */ - NVIC_SetPriority (SysTick_IRQn, (1<<__NVIC_PRIO_BITS) - 1); /* set Priority for Systick Interrupt */ - SysTick->VAL = 0; /* Load the SysTick Counter Value */ - SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk | - SysTick_CTRL_TICKINT_Msk | - SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */ - return (0); /* Function successful */ -} + __STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks) + { + if ((ticks - 1) > SysTick_LOAD_RELOAD_Msk) + return (1); /* Reload value impossible */ + + SysTick->LOAD = ticks - 1; /* set reload register */ + NVIC_SetPriority(SysTick_IRQn, (1 << __NVIC_PRIO_BITS) - 1); /* set Priority for Systick Interrupt */ + SysTick->VAL = 0; /* Load the SysTick Counter Value */ + SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk | + SysTick_CTRL_TICKINT_Msk | + SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */ + return (0); /* Function successful */ + } #endif -/*@} end of CMSIS_Core_SysTickFunctions */ - - - + /*@} end of CMSIS_Core_SysTickFunctions */ #ifdef __cplusplus } diff --git a/bsp/swm320-lq100/Libraries/CMSIS/CoreSupport/core_cm3.h b/bsp/swm320-lq100/Libraries/CMSIS/CoreSupport/core_cm3.h index e1357c6735..2e6ec11a45 100644 --- a/bsp/swm320-lq100/Libraries/CMSIS/CoreSupport/core_cm3.h +++ b/bsp/swm320-lq100/Libraries/CMSIS/CoreSupport/core_cm3.h @@ -1,4 +1,4 @@ -/**************************************************************************//** +/**************************************************************************/ /** * @file core_cm3.h * @brief CMSIS Cortex-M3 Core Peripheral Access Layer Header File * @version V4.00 @@ -34,16 +34,16 @@ POSSIBILITY OF SUCH DAMAGE. ---------------------------------------------------------------------------*/ - -#if defined ( __ICCARM__ ) - #pragma system_include /* treat file as system include file for MISRA check */ +#if defined(__ICCARM__) +#pragma system_include /* treat file as system include file for MISRA check */ #endif #ifndef __CORE_CM3_H_GENERIC #define __CORE_CM3_H_GENERIC #ifdef __cplusplus - extern "C" { +extern "C" +{ #endif /** \page CMSIS_MISRA_Exceptions MISRA-C:2004 Compliance Exceptions @@ -59,7 +59,6 @@ Function-like macros are used to allow more efficient code. */ - /******************************************************************************* * CMSIS definitions ******************************************************************************/ @@ -68,85 +67,84 @@ */ /* CMSIS CM3 definitions */ -#define __CM3_CMSIS_VERSION_MAIN (0x04) /*!< [31:16] CMSIS HAL main version */ -#define __CM3_CMSIS_VERSION_SUB (0x00) /*!< [15:0] CMSIS HAL sub version */ -#define __CM3_CMSIS_VERSION ((__CM3_CMSIS_VERSION_MAIN << 16) | \ - __CM3_CMSIS_VERSION_SUB ) /*!< CMSIS HAL version number */ - -#define __CORTEX_M (0x03) /*!< Cortex-M Core */ +#define __CM3_CMSIS_VERSION_MAIN (0x04) /*!< [31:16] CMSIS HAL main version */ +#define __CM3_CMSIS_VERSION_SUB (0x00) /*!< [15:0] CMSIS HAL sub version */ +#define __CM3_CMSIS_VERSION ((__CM3_CMSIS_VERSION_MAIN << 16) | \ + __CM3_CMSIS_VERSION_SUB) /*!< CMSIS HAL version number */ + +#define __CORTEX_M (0x03) /*!< Cortex-M Core */ + +#if defined(__CC_ARM) +#define __ASM __asm /*!< asm keyword for ARM Compiler */ +#define __INLINE __inline /*!< inline keyword for ARM Compiler */ +#define __STATIC_INLINE static __inline + +#elif defined(__GNUC__) +#define __ASM __asm /*!< asm keyword for GNU Compiler */ +#define __INLINE inline /*!< inline keyword for GNU Compiler */ +#define __STATIC_INLINE static inline + +#elif defined(__ICCARM__) +#define __ASM __asm /*!< asm keyword for IAR Compiler */ +#define __INLINE inline /*!< inline keyword for IAR Compiler. Only available in High optimization mode! */ +#define __STATIC_INLINE static inline + +#elif defined(__TMS470__) +#define __ASM __asm /*!< asm keyword for TI CCS Compiler */ +#define __STATIC_INLINE static inline + +#elif defined(__TASKING__) +#define __ASM __asm /*!< asm keyword for TASKING Compiler */ +#define __INLINE inline /*!< inline keyword for TASKING Compiler */ +#define __STATIC_INLINE static inline + +#elif defined(__CSMC__) +#define __packed +#define __ASM _asm /*!< asm keyword for COSMIC Compiler */ +#define __INLINE inline /*use -pc99 on compile line !< inline keyword for COSMIC Compiler */ +#define __STATIC_INLINE static inline +#endif -#if defined ( __CC_ARM ) - #define __ASM __asm /*!< asm keyword for ARM Compiler */ - #define __INLINE __inline /*!< inline keyword for ARM Compiler */ - #define __STATIC_INLINE static __inline - -#elif defined ( __GNUC__ ) - #define __ASM __asm /*!< asm keyword for GNU Compiler */ - #define __INLINE inline /*!< inline keyword for GNU Compiler */ - #define __STATIC_INLINE static inline +/** __FPU_USED indicates whether an FPU is used or not. + This core does not support an FPU at all +*/ +#define __FPU_USED 0 -#elif defined ( __ICCARM__ ) - #define __ASM __asm /*!< asm keyword for IAR Compiler */ - #define __INLINE inline /*!< inline keyword for IAR Compiler. Only available in High optimization mode! */ - #define __STATIC_INLINE static inline +#if defined(__CC_ARM) +#if defined __TARGET_FPU_VFP +#warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" +#endif -#elif defined ( __TMS470__ ) - #define __ASM __asm /*!< asm keyword for TI CCS Compiler */ - #define __STATIC_INLINE static inline +#elif defined(__GNUC__) +#if defined(__VFP_FP__) && !defined(__SOFTFP__) +#warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" +#endif -#elif defined ( __TASKING__ ) - #define __ASM __asm /*!< asm keyword for TASKING Compiler */ - #define __INLINE inline /*!< inline keyword for TASKING Compiler */ - #define __STATIC_INLINE static inline +#elif defined(__ICCARM__) +#if defined __ARMVFP__ +#warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" +#endif -#elif defined ( __CSMC__ ) - #define __packed - #define __ASM _asm /*!< asm keyword for COSMIC Compiler */ - #define __INLINE inline /*use -pc99 on compile line !< inline keyword for COSMIC Compiler */ - #define __STATIC_INLINE static inline +#elif defined(__TMS470__) +#if defined __TI__VFP_SUPPORT____ +#warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" +#endif +#elif defined(__TASKING__) +#if defined __FPU_VFP__ +#error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" #endif -/** __FPU_USED indicates whether an FPU is used or not. - This core does not support an FPU at all -*/ -#define __FPU_USED 0 - -#if defined ( __CC_ARM ) - #if defined __TARGET_FPU_VFP - #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" - #endif - -#elif defined ( __GNUC__ ) - #if defined (__VFP_FP__) && !defined(__SOFTFP__) - #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" - #endif - -#elif defined ( __ICCARM__ ) - #if defined __ARMVFP__ - #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" - #endif - -#elif defined ( __TMS470__ ) - #if defined __TI__VFP_SUPPORT____ - #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" - #endif - -#elif defined ( __TASKING__ ) - #if defined __FPU_VFP__ - #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" - #endif - -#elif defined ( __CSMC__ ) /* Cosmic */ - #if ( __CSMC__ & 0x400) // FPU present for parser - #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" - #endif +#elif defined(__CSMC__) /* Cosmic */ +#if (__CSMC__ & 0x400) // FPU present for parser +#error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" +#endif #endif -#include /* standard types definitions */ -#include /* Core Instruction Access */ -#include /* Core Function Access */ +#include /* standard types definitions */ +#include /* Core Instruction Access */ +#include /* Core Function Access */ #ifdef __cplusplus } @@ -160,30 +158,31 @@ #define __CORE_CM3_H_DEPENDANT #ifdef __cplusplus - extern "C" { +extern "C" +{ #endif /* check device defines and use defaults */ #if defined __CHECK_DEVICE_DEFINES - #ifndef __CM3_REV - #define __CM3_REV 0x0200 - #warning "__CM3_REV not defined in device header file; using default!" - #endif - - #ifndef __MPU_PRESENT - #define __MPU_PRESENT 0 - #warning "__MPU_PRESENT not defined in device header file; using default!" - #endif - - #ifndef __NVIC_PRIO_BITS - #define __NVIC_PRIO_BITS 4 - #warning "__NVIC_PRIO_BITS not defined in device header file; using default!" - #endif - - #ifndef __Vendor_SysTickConfig - #define __Vendor_SysTickConfig 0 - #warning "__Vendor_SysTickConfig not defined in device header file; using default!" - #endif +#ifndef __CM3_REV +#define __CM3_REV 0x0200 +#warning "__CM3_REV not defined in device header file; using default!" +#endif + +#ifndef __MPU_PRESENT +#define __MPU_PRESENT 0 +#warning "__MPU_PRESENT not defined in device header file; using default!" +#endif + +#ifndef __NVIC_PRIO_BITS +#define __NVIC_PRIO_BITS 4 +#warning "__NVIC_PRIO_BITS not defined in device header file; using default!" +#endif + +#ifndef __Vendor_SysTickConfig +#define __Vendor_SysTickConfig 0 +#warning "__Vendor_SysTickConfig not defined in device header file; using default!" +#endif #endif /* IO definitions (access restrictions to peripheral registers) */ @@ -195,18 +194,16 @@ \li for automatic generation of peripheral register debug information. */ #ifdef __cplusplus - #define __I volatile /*!< Defines 'read only' permissions */ +#define __I volatile /*!< Defines 'read only' permissions */ #else - #define __I volatile const /*!< Defines 'read only' permissions */ +#define __I volatile const /*!< Defines 'read only' permissions */ #endif -#define __O volatile /*!< Defines 'write only' permissions */ -#define __IO volatile /*!< Defines 'read / write' permissions */ - -/*@} end of group Cortex_M3 */ +#define __O volatile /*!< Defines 'write only' permissions */ +#define __IO volatile /*!< Defines 'read / write' permissions */ + /*@} end of group Cortex_M3 */ - -/******************************************************************************* + /******************************************************************************* * Register Abstraction Core Register contain: - Core Register @@ -216,1034 +213,1021 @@ - Core Debug Register - Core MPU Register ******************************************************************************/ -/** \defgroup CMSIS_core_register Defines and Type Definitions + /** \defgroup CMSIS_core_register Defines and Type Definitions \brief Type definitions and defines for Cortex-M processor based devices. */ -/** \ingroup CMSIS_core_register + /** \ingroup CMSIS_core_register \defgroup CMSIS_CORE Status and Control Registers \brief Core Register type definitions. @{ */ -/** \brief Union type to access the Application Program Status Register (APSR). + /** \brief Union type to access the Application Program Status Register (APSR). */ -typedef union -{ - struct - { + typedef union + { + struct + { #if (__CORTEX_M != 0x04) - uint32_t _reserved0:27; /*!< bit: 0..26 Reserved */ + uint32_t _reserved0 : 27; /*!< bit: 0..26 Reserved */ #else - uint32_t _reserved0:16; /*!< bit: 0..15 Reserved */ - uint32_t GE:4; /*!< bit: 16..19 Greater than or Equal flags */ - uint32_t _reserved1:7; /*!< bit: 20..26 Reserved */ + uint32_t _reserved0 : 16; /*!< bit: 0..15 Reserved */ + uint32_t GE : 4; /*!< bit: 16..19 Greater than or Equal flags */ + uint32_t _reserved1 : 7; /*!< bit: 20..26 Reserved */ #endif - uint32_t Q:1; /*!< bit: 27 Saturation condition flag */ - uint32_t V:1; /*!< bit: 28 Overflow condition code flag */ - uint32_t C:1; /*!< bit: 29 Carry condition code flag */ - uint32_t Z:1; /*!< bit: 30 Zero condition code flag */ - uint32_t N:1; /*!< bit: 31 Negative condition code flag */ - } b; /*!< Structure used for bit access */ - uint32_t w; /*!< Type used for word access */ -} APSR_Type; - - -/** \brief Union type to access the Interrupt Program Status Register (IPSR). + uint32_t Q : 1; /*!< bit: 27 Saturation condition flag */ + uint32_t V : 1; /*!< bit: 28 Overflow condition code flag */ + uint32_t C : 1; /*!< bit: 29 Carry condition code flag */ + uint32_t Z : 1; /*!< bit: 30 Zero condition code flag */ + uint32_t N : 1; /*!< bit: 31 Negative condition code flag */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ + } APSR_Type; + + /** \brief Union type to access the Interrupt Program Status Register (IPSR). */ -typedef union -{ - struct - { - uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */ - uint32_t _reserved0:23; /*!< bit: 9..31 Reserved */ - } b; /*!< Structure used for bit access */ - uint32_t w; /*!< Type used for word access */ -} IPSR_Type; - - -/** \brief Union type to access the Special-Purpose Program Status Registers (xPSR). + typedef union + { + struct + { + uint32_t ISR : 9; /*!< bit: 0.. 8 Exception number */ + uint32_t _reserved0 : 23; /*!< bit: 9..31 Reserved */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ + } IPSR_Type; + + /** \brief Union type to access the Special-Purpose Program Status Registers (xPSR). */ -typedef union -{ - struct - { - uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */ + typedef union + { + struct + { + uint32_t ISR : 9; /*!< bit: 0.. 8 Exception number */ #if (__CORTEX_M != 0x04) - uint32_t _reserved0:15; /*!< bit: 9..23 Reserved */ + uint32_t _reserved0 : 15; /*!< bit: 9..23 Reserved */ #else - uint32_t _reserved0:7; /*!< bit: 9..15 Reserved */ - uint32_t GE:4; /*!< bit: 16..19 Greater than or Equal flags */ - uint32_t _reserved1:4; /*!< bit: 20..23 Reserved */ + uint32_t _reserved0 : 7; /*!< bit: 9..15 Reserved */ + uint32_t GE : 4; /*!< bit: 16..19 Greater than or Equal flags */ + uint32_t _reserved1 : 4; /*!< bit: 20..23 Reserved */ #endif - uint32_t T:1; /*!< bit: 24 Thumb bit (read 0) */ - uint32_t IT:2; /*!< bit: 25..26 saved IT state (read 0) */ - uint32_t Q:1; /*!< bit: 27 Saturation condition flag */ - uint32_t V:1; /*!< bit: 28 Overflow condition code flag */ - uint32_t C:1; /*!< bit: 29 Carry condition code flag */ - uint32_t Z:1; /*!< bit: 30 Zero condition code flag */ - uint32_t N:1; /*!< bit: 31 Negative condition code flag */ - } b; /*!< Structure used for bit access */ - uint32_t w; /*!< Type used for word access */ -} xPSR_Type; - - -/** \brief Union type to access the Control Registers (CONTROL). + uint32_t T : 1; /*!< bit: 24 Thumb bit (read 0) */ + uint32_t IT : 2; /*!< bit: 25..26 saved IT state (read 0) */ + uint32_t Q : 1; /*!< bit: 27 Saturation condition flag */ + uint32_t V : 1; /*!< bit: 28 Overflow condition code flag */ + uint32_t C : 1; /*!< bit: 29 Carry condition code flag */ + uint32_t Z : 1; /*!< bit: 30 Zero condition code flag */ + uint32_t N : 1; /*!< bit: 31 Negative condition code flag */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ + } xPSR_Type; + + /** \brief Union type to access the Control Registers (CONTROL). */ -typedef union -{ - struct - { - uint32_t nPRIV:1; /*!< bit: 0 Execution privilege in Thread mode */ - uint32_t SPSEL:1; /*!< bit: 1 Stack to be used */ - uint32_t FPCA:1; /*!< bit: 2 FP extension active flag */ - uint32_t _reserved0:29; /*!< bit: 3..31 Reserved */ - } b; /*!< Structure used for bit access */ - uint32_t w; /*!< Type used for word access */ -} CONTROL_Type; - -/*@} end of group CMSIS_CORE */ - - -/** \ingroup CMSIS_core_register + typedef union + { + struct + { + uint32_t nPRIV : 1; /*!< bit: 0 Execution privilege in Thread mode */ + uint32_t SPSEL : 1; /*!< bit: 1 Stack to be used */ + uint32_t FPCA : 1; /*!< bit: 2 FP extension active flag */ + uint32_t _reserved0 : 29; /*!< bit: 3..31 Reserved */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ + } CONTROL_Type; + + /*@} end of group CMSIS_CORE */ + + /** \ingroup CMSIS_core_register \defgroup CMSIS_NVIC Nested Vectored Interrupt Controller (NVIC) \brief Type definitions for the NVIC Registers @{ */ -/** \brief Structure type to access the Nested Vectored Interrupt Controller (NVIC). + /** \brief Structure type to access the Nested Vectored Interrupt Controller (NVIC). */ -typedef struct -{ - __IO uint32_t ISER[8]; /*!< Offset: 0x000 (R/W) Interrupt Set Enable Register */ - uint32_t RESERVED0[24]; - __IO uint32_t ICER[8]; /*!< Offset: 0x080 (R/W) Interrupt Clear Enable Register */ - uint32_t RSERVED1[24]; - __IO uint32_t ISPR[8]; /*!< Offset: 0x100 (R/W) Interrupt Set Pending Register */ - uint32_t RESERVED2[24]; - __IO uint32_t ICPR[8]; /*!< Offset: 0x180 (R/W) Interrupt Clear Pending Register */ - uint32_t RESERVED3[24]; - __IO uint32_t IABR[8]; /*!< Offset: 0x200 (R/W) Interrupt Active bit Register */ - uint32_t RESERVED4[56]; - __IO uint8_t IP[240]; /*!< Offset: 0x300 (R/W) Interrupt Priority Register (8Bit wide) */ - uint32_t RESERVED5[644]; - __O uint32_t STIR; /*!< Offset: 0xE00 ( /W) Software Trigger Interrupt Register */ -} NVIC_Type; + typedef struct + { + __IO uint32_t ISER[8]; /*!< Offset: 0x000 (R/W) Interrupt Set Enable Register */ + uint32_t RESERVED0[24]; + __IO uint32_t ICER[8]; /*!< Offset: 0x080 (R/W) Interrupt Clear Enable Register */ + uint32_t RSERVED1[24]; + __IO uint32_t ISPR[8]; /*!< Offset: 0x100 (R/W) Interrupt Set Pending Register */ + uint32_t RESERVED2[24]; + __IO uint32_t ICPR[8]; /*!< Offset: 0x180 (R/W) Interrupt Clear Pending Register */ + uint32_t RESERVED3[24]; + __IO uint32_t IABR[8]; /*!< Offset: 0x200 (R/W) Interrupt Active bit Register */ + uint32_t RESERVED4[56]; + __IO uint8_t IP[240]; /*!< Offset: 0x300 (R/W) Interrupt Priority Register (8Bit wide) */ + uint32_t RESERVED5[644]; + __O uint32_t STIR; /*!< Offset: 0xE00 ( /W) Software Trigger Interrupt Register */ + } NVIC_Type; /* Software Triggered Interrupt Register Definitions */ -#define NVIC_STIR_INTID_Pos 0 /*!< STIR: INTLINESNUM Position */ -#define NVIC_STIR_INTID_Msk (0x1FFUL << NVIC_STIR_INTID_Pos) /*!< STIR: INTLINESNUM Mask */ - -/*@} end of group CMSIS_NVIC */ +#define NVIC_STIR_INTID_Pos 0 /*!< STIR: INTLINESNUM Position */ +#define NVIC_STIR_INTID_Msk (0x1FFUL << NVIC_STIR_INTID_Pos) /*!< STIR: INTLINESNUM Mask */ + /*@} end of group CMSIS_NVIC */ -/** \ingroup CMSIS_core_register + /** \ingroup CMSIS_core_register \defgroup CMSIS_SCB System Control Block (SCB) \brief Type definitions for the System Control Block Registers @{ */ -/** \brief Structure type to access the System Control Block (SCB). + /** \brief Structure type to access the System Control Block (SCB). */ -typedef struct -{ - __I uint32_t CPUID; /*!< Offset: 0x000 (R/ ) CPUID Base Register */ - __IO uint32_t ICSR; /*!< Offset: 0x004 (R/W) Interrupt Control and State Register */ - __IO uint32_t VTOR; /*!< Offset: 0x008 (R/W) Vector Table Offset Register */ - __IO uint32_t AIRCR; /*!< Offset: 0x00C (R/W) Application Interrupt and Reset Control Register */ - __IO uint32_t SCR; /*!< Offset: 0x010 (R/W) System Control Register */ - __IO uint32_t CCR; /*!< Offset: 0x014 (R/W) Configuration Control Register */ - __IO uint8_t SHP[12]; /*!< Offset: 0x018 (R/W) System Handlers Priority Registers (4-7, 8-11, 12-15) */ - __IO uint32_t SHCSR; /*!< Offset: 0x024 (R/W) System Handler Control and State Register */ - __IO uint32_t CFSR; /*!< Offset: 0x028 (R/W) Configurable Fault Status Register */ - __IO uint32_t HFSR; /*!< Offset: 0x02C (R/W) HardFault Status Register */ - __IO uint32_t DFSR; /*!< Offset: 0x030 (R/W) Debug Fault Status Register */ - __IO uint32_t MMFAR; /*!< Offset: 0x034 (R/W) MemManage Fault Address Register */ - __IO uint32_t BFAR; /*!< Offset: 0x038 (R/W) BusFault Address Register */ - __IO uint32_t AFSR; /*!< Offset: 0x03C (R/W) Auxiliary Fault Status Register */ - __I uint32_t PFR[2]; /*!< Offset: 0x040 (R/ ) Processor Feature Register */ - __I uint32_t DFR; /*!< Offset: 0x048 (R/ ) Debug Feature Register */ - __I uint32_t ADR; /*!< Offset: 0x04C (R/ ) Auxiliary Feature Register */ - __I uint32_t MMFR[4]; /*!< Offset: 0x050 (R/ ) Memory Model Feature Register */ - __I uint32_t ISAR[5]; /*!< Offset: 0x060 (R/ ) Instruction Set Attributes Register */ - uint32_t RESERVED0[5]; - __IO uint32_t CPACR; /*!< Offset: 0x088 (R/W) Coprocessor Access Control Register */ -} SCB_Type; + typedef struct + { + __I uint32_t CPUID; /*!< Offset: 0x000 (R/ ) CPUID Base Register */ + __IO uint32_t ICSR; /*!< Offset: 0x004 (R/W) Interrupt Control and State Register */ + __IO uint32_t VTOR; /*!< Offset: 0x008 (R/W) Vector Table Offset Register */ + __IO uint32_t AIRCR; /*!< Offset: 0x00C (R/W) Application Interrupt and Reset Control Register */ + __IO uint32_t SCR; /*!< Offset: 0x010 (R/W) System Control Register */ + __IO uint32_t CCR; /*!< Offset: 0x014 (R/W) Configuration Control Register */ + __IO uint8_t SHP[12]; /*!< Offset: 0x018 (R/W) System Handlers Priority Registers (4-7, 8-11, 12-15) */ + __IO uint32_t SHCSR; /*!< Offset: 0x024 (R/W) System Handler Control and State Register */ + __IO uint32_t CFSR; /*!< Offset: 0x028 (R/W) Configurable Fault Status Register */ + __IO uint32_t HFSR; /*!< Offset: 0x02C (R/W) HardFault Status Register */ + __IO uint32_t DFSR; /*!< Offset: 0x030 (R/W) Debug Fault Status Register */ + __IO uint32_t MMFAR; /*!< Offset: 0x034 (R/W) MemManage Fault Address Register */ + __IO uint32_t BFAR; /*!< Offset: 0x038 (R/W) BusFault Address Register */ + __IO uint32_t AFSR; /*!< Offset: 0x03C (R/W) Auxiliary Fault Status Register */ + __I uint32_t PFR[2]; /*!< Offset: 0x040 (R/ ) Processor Feature Register */ + __I uint32_t DFR; /*!< Offset: 0x048 (R/ ) Debug Feature Register */ + __I uint32_t ADR; /*!< Offset: 0x04C (R/ ) Auxiliary Feature Register */ + __I uint32_t MMFR[4]; /*!< Offset: 0x050 (R/ ) Memory Model Feature Register */ + __I uint32_t ISAR[5]; /*!< Offset: 0x060 (R/ ) Instruction Set Attributes Register */ + uint32_t RESERVED0[5]; + __IO uint32_t CPACR; /*!< Offset: 0x088 (R/W) Coprocessor Access Control Register */ + } SCB_Type; /* SCB CPUID Register Definitions */ -#define SCB_CPUID_IMPLEMENTER_Pos 24 /*!< SCB CPUID: IMPLEMENTER Position */ -#define SCB_CPUID_IMPLEMENTER_Msk (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos) /*!< SCB CPUID: IMPLEMENTER Mask */ +#define SCB_CPUID_IMPLEMENTER_Pos 24 /*!< SCB CPUID: IMPLEMENTER Position */ +#define SCB_CPUID_IMPLEMENTER_Msk (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos) /*!< SCB CPUID: IMPLEMENTER Mask */ -#define SCB_CPUID_VARIANT_Pos 20 /*!< SCB CPUID: VARIANT Position */ -#define SCB_CPUID_VARIANT_Msk (0xFUL << SCB_CPUID_VARIANT_Pos) /*!< SCB CPUID: VARIANT Mask */ +#define SCB_CPUID_VARIANT_Pos 20 /*!< SCB CPUID: VARIANT Position */ +#define SCB_CPUID_VARIANT_Msk (0xFUL << SCB_CPUID_VARIANT_Pos) /*!< SCB CPUID: VARIANT Mask */ -#define SCB_CPUID_ARCHITECTURE_Pos 16 /*!< SCB CPUID: ARCHITECTURE Position */ -#define SCB_CPUID_ARCHITECTURE_Msk (0xFUL << SCB_CPUID_ARCHITECTURE_Pos) /*!< SCB CPUID: ARCHITECTURE Mask */ +#define SCB_CPUID_ARCHITECTURE_Pos 16 /*!< SCB CPUID: ARCHITECTURE Position */ +#define SCB_CPUID_ARCHITECTURE_Msk (0xFUL << SCB_CPUID_ARCHITECTURE_Pos) /*!< SCB CPUID: ARCHITECTURE Mask */ -#define SCB_CPUID_PARTNO_Pos 4 /*!< SCB CPUID: PARTNO Position */ -#define SCB_CPUID_PARTNO_Msk (0xFFFUL << SCB_CPUID_PARTNO_Pos) /*!< SCB CPUID: PARTNO Mask */ +#define SCB_CPUID_PARTNO_Pos 4 /*!< SCB CPUID: PARTNO Position */ +#define SCB_CPUID_PARTNO_Msk (0xFFFUL << SCB_CPUID_PARTNO_Pos) /*!< SCB CPUID: PARTNO Mask */ -#define SCB_CPUID_REVISION_Pos 0 /*!< SCB CPUID: REVISION Position */ -#define SCB_CPUID_REVISION_Msk (0xFUL << SCB_CPUID_REVISION_Pos) /*!< SCB CPUID: REVISION Mask */ +#define SCB_CPUID_REVISION_Pos 0 /*!< SCB CPUID: REVISION Position */ +#define SCB_CPUID_REVISION_Msk (0xFUL << SCB_CPUID_REVISION_Pos) /*!< SCB CPUID: REVISION Mask */ /* SCB Interrupt Control State Register Definitions */ -#define SCB_ICSR_NMIPENDSET_Pos 31 /*!< SCB ICSR: NMIPENDSET Position */ -#define SCB_ICSR_NMIPENDSET_Msk (1UL << SCB_ICSR_NMIPENDSET_Pos) /*!< SCB ICSR: NMIPENDSET Mask */ +#define SCB_ICSR_NMIPENDSET_Pos 31 /*!< SCB ICSR: NMIPENDSET Position */ +#define SCB_ICSR_NMIPENDSET_Msk (1UL << SCB_ICSR_NMIPENDSET_Pos) /*!< SCB ICSR: NMIPENDSET Mask */ -#define SCB_ICSR_PENDSVSET_Pos 28 /*!< SCB ICSR: PENDSVSET Position */ -#define SCB_ICSR_PENDSVSET_Msk (1UL << SCB_ICSR_PENDSVSET_Pos) /*!< SCB ICSR: PENDSVSET Mask */ +#define SCB_ICSR_PENDSVSET_Pos 28 /*!< SCB ICSR: PENDSVSET Position */ +#define SCB_ICSR_PENDSVSET_Msk (1UL << SCB_ICSR_PENDSVSET_Pos) /*!< SCB ICSR: PENDSVSET Mask */ -#define SCB_ICSR_PENDSVCLR_Pos 27 /*!< SCB ICSR: PENDSVCLR Position */ -#define SCB_ICSR_PENDSVCLR_Msk (1UL << SCB_ICSR_PENDSVCLR_Pos) /*!< SCB ICSR: PENDSVCLR Mask */ +#define SCB_ICSR_PENDSVCLR_Pos 27 /*!< SCB ICSR: PENDSVCLR Position */ +#define SCB_ICSR_PENDSVCLR_Msk (1UL << SCB_ICSR_PENDSVCLR_Pos) /*!< SCB ICSR: PENDSVCLR Mask */ -#define SCB_ICSR_PENDSTSET_Pos 26 /*!< SCB ICSR: PENDSTSET Position */ -#define SCB_ICSR_PENDSTSET_Msk (1UL << SCB_ICSR_PENDSTSET_Pos) /*!< SCB ICSR: PENDSTSET Mask */ +#define SCB_ICSR_PENDSTSET_Pos 26 /*!< SCB ICSR: PENDSTSET Position */ +#define SCB_ICSR_PENDSTSET_Msk (1UL << SCB_ICSR_PENDSTSET_Pos) /*!< SCB ICSR: PENDSTSET Mask */ -#define SCB_ICSR_PENDSTCLR_Pos 25 /*!< SCB ICSR: PENDSTCLR Position */ -#define SCB_ICSR_PENDSTCLR_Msk (1UL << SCB_ICSR_PENDSTCLR_Pos) /*!< SCB ICSR: PENDSTCLR Mask */ +#define SCB_ICSR_PENDSTCLR_Pos 25 /*!< SCB ICSR: PENDSTCLR Position */ +#define SCB_ICSR_PENDSTCLR_Msk (1UL << SCB_ICSR_PENDSTCLR_Pos) /*!< SCB ICSR: PENDSTCLR Mask */ -#define SCB_ICSR_ISRPREEMPT_Pos 23 /*!< SCB ICSR: ISRPREEMPT Position */ -#define SCB_ICSR_ISRPREEMPT_Msk (1UL << SCB_ICSR_ISRPREEMPT_Pos) /*!< SCB ICSR: ISRPREEMPT Mask */ +#define SCB_ICSR_ISRPREEMPT_Pos 23 /*!< SCB ICSR: ISRPREEMPT Position */ +#define SCB_ICSR_ISRPREEMPT_Msk (1UL << SCB_ICSR_ISRPREEMPT_Pos) /*!< SCB ICSR: ISRPREEMPT Mask */ -#define SCB_ICSR_ISRPENDING_Pos 22 /*!< SCB ICSR: ISRPENDING Position */ -#define SCB_ICSR_ISRPENDING_Msk (1UL << SCB_ICSR_ISRPENDING_Pos) /*!< SCB ICSR: ISRPENDING Mask */ +#define SCB_ICSR_ISRPENDING_Pos 22 /*!< SCB ICSR: ISRPENDING Position */ +#define SCB_ICSR_ISRPENDING_Msk (1UL << SCB_ICSR_ISRPENDING_Pos) /*!< SCB ICSR: ISRPENDING Mask */ -#define SCB_ICSR_VECTPENDING_Pos 12 /*!< SCB ICSR: VECTPENDING Position */ -#define SCB_ICSR_VECTPENDING_Msk (0x1FFUL << SCB_ICSR_VECTPENDING_Pos) /*!< SCB ICSR: VECTPENDING Mask */ +#define SCB_ICSR_VECTPENDING_Pos 12 /*!< SCB ICSR: VECTPENDING Position */ +#define SCB_ICSR_VECTPENDING_Msk (0x1FFUL << SCB_ICSR_VECTPENDING_Pos) /*!< SCB ICSR: VECTPENDING Mask */ -#define SCB_ICSR_RETTOBASE_Pos 11 /*!< SCB ICSR: RETTOBASE Position */ -#define SCB_ICSR_RETTOBASE_Msk (1UL << SCB_ICSR_RETTOBASE_Pos) /*!< SCB ICSR: RETTOBASE Mask */ +#define SCB_ICSR_RETTOBASE_Pos 11 /*!< SCB ICSR: RETTOBASE Position */ +#define SCB_ICSR_RETTOBASE_Msk (1UL << SCB_ICSR_RETTOBASE_Pos) /*!< SCB ICSR: RETTOBASE Mask */ -#define SCB_ICSR_VECTACTIVE_Pos 0 /*!< SCB ICSR: VECTACTIVE Position */ -#define SCB_ICSR_VECTACTIVE_Msk (0x1FFUL << SCB_ICSR_VECTACTIVE_Pos) /*!< SCB ICSR: VECTACTIVE Mask */ +#define SCB_ICSR_VECTACTIVE_Pos 0 /*!< SCB ICSR: VECTACTIVE Position */ +#define SCB_ICSR_VECTACTIVE_Msk (0x1FFUL << SCB_ICSR_VECTACTIVE_Pos) /*!< SCB ICSR: VECTACTIVE Mask */ /* SCB Vector Table Offset Register Definitions */ -#if (__CM3_REV < 0x0201) /* core r2p1 */ -#define SCB_VTOR_TBLBASE_Pos 29 /*!< SCB VTOR: TBLBASE Position */ -#define SCB_VTOR_TBLBASE_Msk (1UL << SCB_VTOR_TBLBASE_Pos) /*!< SCB VTOR: TBLBASE Mask */ +#if (__CM3_REV < 0x0201) /* core r2p1 */ +#define SCB_VTOR_TBLBASE_Pos 29 /*!< SCB VTOR: TBLBASE Position */ +#define SCB_VTOR_TBLBASE_Msk (1UL << SCB_VTOR_TBLBASE_Pos) /*!< SCB VTOR: TBLBASE Mask */ -#define SCB_VTOR_TBLOFF_Pos 7 /*!< SCB VTOR: TBLOFF Position */ -#define SCB_VTOR_TBLOFF_Msk (0x3FFFFFUL << SCB_VTOR_TBLOFF_Pos) /*!< SCB VTOR: TBLOFF Mask */ +#define SCB_VTOR_TBLOFF_Pos 7 /*!< SCB VTOR: TBLOFF Position */ +#define SCB_VTOR_TBLOFF_Msk (0x3FFFFFUL << SCB_VTOR_TBLOFF_Pos) /*!< SCB VTOR: TBLOFF Mask */ #else -#define SCB_VTOR_TBLOFF_Pos 7 /*!< SCB VTOR: TBLOFF Position */ -#define SCB_VTOR_TBLOFF_Msk (0x1FFFFFFUL << SCB_VTOR_TBLOFF_Pos) /*!< SCB VTOR: TBLOFF Mask */ +#define SCB_VTOR_TBLOFF_Pos 7 /*!< SCB VTOR: TBLOFF Position */ +#define SCB_VTOR_TBLOFF_Msk (0x1FFFFFFUL << SCB_VTOR_TBLOFF_Pos) /*!< SCB VTOR: TBLOFF Mask */ #endif /* SCB Application Interrupt and Reset Control Register Definitions */ -#define SCB_AIRCR_VECTKEY_Pos 16 /*!< SCB AIRCR: VECTKEY Position */ -#define SCB_AIRCR_VECTKEY_Msk (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos) /*!< SCB AIRCR: VECTKEY Mask */ +#define SCB_AIRCR_VECTKEY_Pos 16 /*!< SCB AIRCR: VECTKEY Position */ +#define SCB_AIRCR_VECTKEY_Msk (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos) /*!< SCB AIRCR: VECTKEY Mask */ -#define SCB_AIRCR_VECTKEYSTAT_Pos 16 /*!< SCB AIRCR: VECTKEYSTAT Position */ -#define SCB_AIRCR_VECTKEYSTAT_Msk (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos) /*!< SCB AIRCR: VECTKEYSTAT Mask */ +#define SCB_AIRCR_VECTKEYSTAT_Pos 16 /*!< SCB AIRCR: VECTKEYSTAT Position */ +#define SCB_AIRCR_VECTKEYSTAT_Msk (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos) /*!< SCB AIRCR: VECTKEYSTAT Mask */ -#define SCB_AIRCR_ENDIANESS_Pos 15 /*!< SCB AIRCR: ENDIANESS Position */ -#define SCB_AIRCR_ENDIANESS_Msk (1UL << SCB_AIRCR_ENDIANESS_Pos) /*!< SCB AIRCR: ENDIANESS Mask */ +#define SCB_AIRCR_ENDIANESS_Pos 15 /*!< SCB AIRCR: ENDIANESS Position */ +#define SCB_AIRCR_ENDIANESS_Msk (1UL << SCB_AIRCR_ENDIANESS_Pos) /*!< SCB AIRCR: ENDIANESS Mask */ -#define SCB_AIRCR_PRIGROUP_Pos 8 /*!< SCB AIRCR: PRIGROUP Position */ -#define SCB_AIRCR_PRIGROUP_Msk (7UL << SCB_AIRCR_PRIGROUP_Pos) /*!< SCB AIRCR: PRIGROUP Mask */ +#define SCB_AIRCR_PRIGROUP_Pos 8 /*!< SCB AIRCR: PRIGROUP Position */ +#define SCB_AIRCR_PRIGROUP_Msk (7UL << SCB_AIRCR_PRIGROUP_Pos) /*!< SCB AIRCR: PRIGROUP Mask */ -#define SCB_AIRCR_SYSRESETREQ_Pos 2 /*!< SCB AIRCR: SYSRESETREQ Position */ -#define SCB_AIRCR_SYSRESETREQ_Msk (1UL << SCB_AIRCR_SYSRESETREQ_Pos) /*!< SCB AIRCR: SYSRESETREQ Mask */ +#define SCB_AIRCR_SYSRESETREQ_Pos 2 /*!< SCB AIRCR: SYSRESETREQ Position */ +#define SCB_AIRCR_SYSRESETREQ_Msk (1UL << SCB_AIRCR_SYSRESETREQ_Pos) /*!< SCB AIRCR: SYSRESETREQ Mask */ -#define SCB_AIRCR_VECTCLRACTIVE_Pos 1 /*!< SCB AIRCR: VECTCLRACTIVE Position */ -#define SCB_AIRCR_VECTCLRACTIVE_Msk (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos) /*!< SCB AIRCR: VECTCLRACTIVE Mask */ +#define SCB_AIRCR_VECTCLRACTIVE_Pos 1 /*!< SCB AIRCR: VECTCLRACTIVE Position */ +#define SCB_AIRCR_VECTCLRACTIVE_Msk (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos) /*!< SCB AIRCR: VECTCLRACTIVE Mask */ -#define SCB_AIRCR_VECTRESET_Pos 0 /*!< SCB AIRCR: VECTRESET Position */ -#define SCB_AIRCR_VECTRESET_Msk (1UL << SCB_AIRCR_VECTRESET_Pos) /*!< SCB AIRCR: VECTRESET Mask */ +#define SCB_AIRCR_VECTRESET_Pos 0 /*!< SCB AIRCR: VECTRESET Position */ +#define SCB_AIRCR_VECTRESET_Msk (1UL << SCB_AIRCR_VECTRESET_Pos) /*!< SCB AIRCR: VECTRESET Mask */ /* SCB System Control Register Definitions */ -#define SCB_SCR_SEVONPEND_Pos 4 /*!< SCB SCR: SEVONPEND Position */ -#define SCB_SCR_SEVONPEND_Msk (1UL << SCB_SCR_SEVONPEND_Pos) /*!< SCB SCR: SEVONPEND Mask */ +#define SCB_SCR_SEVONPEND_Pos 4 /*!< SCB SCR: SEVONPEND Position */ +#define SCB_SCR_SEVONPEND_Msk (1UL << SCB_SCR_SEVONPEND_Pos) /*!< SCB SCR: SEVONPEND Mask */ -#define SCB_SCR_SLEEPDEEP_Pos 2 /*!< SCB SCR: SLEEPDEEP Position */ -#define SCB_SCR_SLEEPDEEP_Msk (1UL << SCB_SCR_SLEEPDEEP_Pos) /*!< SCB SCR: SLEEPDEEP Mask */ +#define SCB_SCR_SLEEPDEEP_Pos 2 /*!< SCB SCR: SLEEPDEEP Position */ +#define SCB_SCR_SLEEPDEEP_Msk (1UL << SCB_SCR_SLEEPDEEP_Pos) /*!< SCB SCR: SLEEPDEEP Mask */ -#define SCB_SCR_SLEEPONEXIT_Pos 1 /*!< SCB SCR: SLEEPONEXIT Position */ -#define SCB_SCR_SLEEPONEXIT_Msk (1UL << SCB_SCR_SLEEPONEXIT_Pos) /*!< SCB SCR: SLEEPONEXIT Mask */ +#define SCB_SCR_SLEEPONEXIT_Pos 1 /*!< SCB SCR: SLEEPONEXIT Position */ +#define SCB_SCR_SLEEPONEXIT_Msk (1UL << SCB_SCR_SLEEPONEXIT_Pos) /*!< SCB SCR: SLEEPONEXIT Mask */ /* SCB Configuration Control Register Definitions */ -#define SCB_CCR_STKALIGN_Pos 9 /*!< SCB CCR: STKALIGN Position */ -#define SCB_CCR_STKALIGN_Msk (1UL << SCB_CCR_STKALIGN_Pos) /*!< SCB CCR: STKALIGN Mask */ +#define SCB_CCR_STKALIGN_Pos 9 /*!< SCB CCR: STKALIGN Position */ +#define SCB_CCR_STKALIGN_Msk (1UL << SCB_CCR_STKALIGN_Pos) /*!< SCB CCR: STKALIGN Mask */ -#define SCB_CCR_BFHFNMIGN_Pos 8 /*!< SCB CCR: BFHFNMIGN Position */ -#define SCB_CCR_BFHFNMIGN_Msk (1UL << SCB_CCR_BFHFNMIGN_Pos) /*!< SCB CCR: BFHFNMIGN Mask */ +#define SCB_CCR_BFHFNMIGN_Pos 8 /*!< SCB CCR: BFHFNMIGN Position */ +#define SCB_CCR_BFHFNMIGN_Msk (1UL << SCB_CCR_BFHFNMIGN_Pos) /*!< SCB CCR: BFHFNMIGN Mask */ -#define SCB_CCR_DIV_0_TRP_Pos 4 /*!< SCB CCR: DIV_0_TRP Position */ -#define SCB_CCR_DIV_0_TRP_Msk (1UL << SCB_CCR_DIV_0_TRP_Pos) /*!< SCB CCR: DIV_0_TRP Mask */ +#define SCB_CCR_DIV_0_TRP_Pos 4 /*!< SCB CCR: DIV_0_TRP Position */ +#define SCB_CCR_DIV_0_TRP_Msk (1UL << SCB_CCR_DIV_0_TRP_Pos) /*!< SCB CCR: DIV_0_TRP Mask */ -#define SCB_CCR_UNALIGN_TRP_Pos 3 /*!< SCB CCR: UNALIGN_TRP Position */ -#define SCB_CCR_UNALIGN_TRP_Msk (1UL << SCB_CCR_UNALIGN_TRP_Pos) /*!< SCB CCR: UNALIGN_TRP Mask */ +#define SCB_CCR_UNALIGN_TRP_Pos 3 /*!< SCB CCR: UNALIGN_TRP Position */ +#define SCB_CCR_UNALIGN_TRP_Msk (1UL << SCB_CCR_UNALIGN_TRP_Pos) /*!< SCB CCR: UNALIGN_TRP Mask */ -#define SCB_CCR_USERSETMPEND_Pos 1 /*!< SCB CCR: USERSETMPEND Position */ -#define SCB_CCR_USERSETMPEND_Msk (1UL << SCB_CCR_USERSETMPEND_Pos) /*!< SCB CCR: USERSETMPEND Mask */ +#define SCB_CCR_USERSETMPEND_Pos 1 /*!< SCB CCR: USERSETMPEND Position */ +#define SCB_CCR_USERSETMPEND_Msk (1UL << SCB_CCR_USERSETMPEND_Pos) /*!< SCB CCR: USERSETMPEND Mask */ -#define SCB_CCR_NONBASETHRDENA_Pos 0 /*!< SCB CCR: NONBASETHRDENA Position */ -#define SCB_CCR_NONBASETHRDENA_Msk (1UL << SCB_CCR_NONBASETHRDENA_Pos) /*!< SCB CCR: NONBASETHRDENA Mask */ +#define SCB_CCR_NONBASETHRDENA_Pos 0 /*!< SCB CCR: NONBASETHRDENA Position */ +#define SCB_CCR_NONBASETHRDENA_Msk (1UL << SCB_CCR_NONBASETHRDENA_Pos) /*!< SCB CCR: NONBASETHRDENA Mask */ /* SCB System Handler Control and State Register Definitions */ -#define SCB_SHCSR_USGFAULTENA_Pos 18 /*!< SCB SHCSR: USGFAULTENA Position */ -#define SCB_SHCSR_USGFAULTENA_Msk (1UL << SCB_SHCSR_USGFAULTENA_Pos) /*!< SCB SHCSR: USGFAULTENA Mask */ +#define SCB_SHCSR_USGFAULTENA_Pos 18 /*!< SCB SHCSR: USGFAULTENA Position */ +#define SCB_SHCSR_USGFAULTENA_Msk (1UL << SCB_SHCSR_USGFAULTENA_Pos) /*!< SCB SHCSR: USGFAULTENA Mask */ -#define SCB_SHCSR_BUSFAULTENA_Pos 17 /*!< SCB SHCSR: BUSFAULTENA Position */ -#define SCB_SHCSR_BUSFAULTENA_Msk (1UL << SCB_SHCSR_BUSFAULTENA_Pos) /*!< SCB SHCSR: BUSFAULTENA Mask */ +#define SCB_SHCSR_BUSFAULTENA_Pos 17 /*!< SCB SHCSR: BUSFAULTENA Position */ +#define SCB_SHCSR_BUSFAULTENA_Msk (1UL << SCB_SHCSR_BUSFAULTENA_Pos) /*!< SCB SHCSR: BUSFAULTENA Mask */ -#define SCB_SHCSR_MEMFAULTENA_Pos 16 /*!< SCB SHCSR: MEMFAULTENA Position */ -#define SCB_SHCSR_MEMFAULTENA_Msk (1UL << SCB_SHCSR_MEMFAULTENA_Pos) /*!< SCB SHCSR: MEMFAULTENA Mask */ +#define SCB_SHCSR_MEMFAULTENA_Pos 16 /*!< SCB SHCSR: MEMFAULTENA Position */ +#define SCB_SHCSR_MEMFAULTENA_Msk (1UL << SCB_SHCSR_MEMFAULTENA_Pos) /*!< SCB SHCSR: MEMFAULTENA Mask */ -#define SCB_SHCSR_SVCALLPENDED_Pos 15 /*!< SCB SHCSR: SVCALLPENDED Position */ -#define SCB_SHCSR_SVCALLPENDED_Msk (1UL << SCB_SHCSR_SVCALLPENDED_Pos) /*!< SCB SHCSR: SVCALLPENDED Mask */ +#define SCB_SHCSR_SVCALLPENDED_Pos 15 /*!< SCB SHCSR: SVCALLPENDED Position */ +#define SCB_SHCSR_SVCALLPENDED_Msk (1UL << SCB_SHCSR_SVCALLPENDED_Pos) /*!< SCB SHCSR: SVCALLPENDED Mask */ -#define SCB_SHCSR_BUSFAULTPENDED_Pos 14 /*!< SCB SHCSR: BUSFAULTPENDED Position */ -#define SCB_SHCSR_BUSFAULTPENDED_Msk (1UL << SCB_SHCSR_BUSFAULTPENDED_Pos) /*!< SCB SHCSR: BUSFAULTPENDED Mask */ +#define SCB_SHCSR_BUSFAULTPENDED_Pos 14 /*!< SCB SHCSR: BUSFAULTPENDED Position */ +#define SCB_SHCSR_BUSFAULTPENDED_Msk (1UL << SCB_SHCSR_BUSFAULTPENDED_Pos) /*!< SCB SHCSR: BUSFAULTPENDED Mask */ -#define SCB_SHCSR_MEMFAULTPENDED_Pos 13 /*!< SCB SHCSR: MEMFAULTPENDED Position */ -#define SCB_SHCSR_MEMFAULTPENDED_Msk (1UL << SCB_SHCSR_MEMFAULTPENDED_Pos) /*!< SCB SHCSR: MEMFAULTPENDED Mask */ +#define SCB_SHCSR_MEMFAULTPENDED_Pos 13 /*!< SCB SHCSR: MEMFAULTPENDED Position */ +#define SCB_SHCSR_MEMFAULTPENDED_Msk (1UL << SCB_SHCSR_MEMFAULTPENDED_Pos) /*!< SCB SHCSR: MEMFAULTPENDED Mask */ -#define SCB_SHCSR_USGFAULTPENDED_Pos 12 /*!< SCB SHCSR: USGFAULTPENDED Position */ -#define SCB_SHCSR_USGFAULTPENDED_Msk (1UL << SCB_SHCSR_USGFAULTPENDED_Pos) /*!< SCB SHCSR: USGFAULTPENDED Mask */ +#define SCB_SHCSR_USGFAULTPENDED_Pos 12 /*!< SCB SHCSR: USGFAULTPENDED Position */ +#define SCB_SHCSR_USGFAULTPENDED_Msk (1UL << SCB_SHCSR_USGFAULTPENDED_Pos) /*!< SCB SHCSR: USGFAULTPENDED Mask */ -#define SCB_SHCSR_SYSTICKACT_Pos 11 /*!< SCB SHCSR: SYSTICKACT Position */ -#define SCB_SHCSR_SYSTICKACT_Msk (1UL << SCB_SHCSR_SYSTICKACT_Pos) /*!< SCB SHCSR: SYSTICKACT Mask */ +#define SCB_SHCSR_SYSTICKACT_Pos 11 /*!< SCB SHCSR: SYSTICKACT Position */ +#define SCB_SHCSR_SYSTICKACT_Msk (1UL << SCB_SHCSR_SYSTICKACT_Pos) /*!< SCB SHCSR: SYSTICKACT Mask */ -#define SCB_SHCSR_PENDSVACT_Pos 10 /*!< SCB SHCSR: PENDSVACT Position */ -#define SCB_SHCSR_PENDSVACT_Msk (1UL << SCB_SHCSR_PENDSVACT_Pos) /*!< SCB SHCSR: PENDSVACT Mask */ +#define SCB_SHCSR_PENDSVACT_Pos 10 /*!< SCB SHCSR: PENDSVACT Position */ +#define SCB_SHCSR_PENDSVACT_Msk (1UL << SCB_SHCSR_PENDSVACT_Pos) /*!< SCB SHCSR: PENDSVACT Mask */ -#define SCB_SHCSR_MONITORACT_Pos 8 /*!< SCB SHCSR: MONITORACT Position */ -#define SCB_SHCSR_MONITORACT_Msk (1UL << SCB_SHCSR_MONITORACT_Pos) /*!< SCB SHCSR: MONITORACT Mask */ +#define SCB_SHCSR_MONITORACT_Pos 8 /*!< SCB SHCSR: MONITORACT Position */ +#define SCB_SHCSR_MONITORACT_Msk (1UL << SCB_SHCSR_MONITORACT_Pos) /*!< SCB SHCSR: MONITORACT Mask */ -#define SCB_SHCSR_SVCALLACT_Pos 7 /*!< SCB SHCSR: SVCALLACT Position */ -#define SCB_SHCSR_SVCALLACT_Msk (1UL << SCB_SHCSR_SVCALLACT_Pos) /*!< SCB SHCSR: SVCALLACT Mask */ +#define SCB_SHCSR_SVCALLACT_Pos 7 /*!< SCB SHCSR: SVCALLACT Position */ +#define SCB_SHCSR_SVCALLACT_Msk (1UL << SCB_SHCSR_SVCALLACT_Pos) /*!< SCB SHCSR: SVCALLACT Mask */ -#define SCB_SHCSR_USGFAULTACT_Pos 3 /*!< SCB SHCSR: USGFAULTACT Position */ -#define SCB_SHCSR_USGFAULTACT_Msk (1UL << SCB_SHCSR_USGFAULTACT_Pos) /*!< SCB SHCSR: USGFAULTACT Mask */ +#define SCB_SHCSR_USGFAULTACT_Pos 3 /*!< SCB SHCSR: USGFAULTACT Position */ +#define SCB_SHCSR_USGFAULTACT_Msk (1UL << SCB_SHCSR_USGFAULTACT_Pos) /*!< SCB SHCSR: USGFAULTACT Mask */ -#define SCB_SHCSR_BUSFAULTACT_Pos 1 /*!< SCB SHCSR: BUSFAULTACT Position */ -#define SCB_SHCSR_BUSFAULTACT_Msk (1UL << SCB_SHCSR_BUSFAULTACT_Pos) /*!< SCB SHCSR: BUSFAULTACT Mask */ +#define SCB_SHCSR_BUSFAULTACT_Pos 1 /*!< SCB SHCSR: BUSFAULTACT Position */ +#define SCB_SHCSR_BUSFAULTACT_Msk (1UL << SCB_SHCSR_BUSFAULTACT_Pos) /*!< SCB SHCSR: BUSFAULTACT Mask */ -#define SCB_SHCSR_MEMFAULTACT_Pos 0 /*!< SCB SHCSR: MEMFAULTACT Position */ -#define SCB_SHCSR_MEMFAULTACT_Msk (1UL << SCB_SHCSR_MEMFAULTACT_Pos) /*!< SCB SHCSR: MEMFAULTACT Mask */ +#define SCB_SHCSR_MEMFAULTACT_Pos 0 /*!< SCB SHCSR: MEMFAULTACT Position */ +#define SCB_SHCSR_MEMFAULTACT_Msk (1UL << SCB_SHCSR_MEMFAULTACT_Pos) /*!< SCB SHCSR: MEMFAULTACT Mask */ /* SCB Configurable Fault Status Registers Definitions */ -#define SCB_CFSR_USGFAULTSR_Pos 16 /*!< SCB CFSR: Usage Fault Status Register Position */ -#define SCB_CFSR_USGFAULTSR_Msk (0xFFFFUL << SCB_CFSR_USGFAULTSR_Pos) /*!< SCB CFSR: Usage Fault Status Register Mask */ +#define SCB_CFSR_USGFAULTSR_Pos 16 /*!< SCB CFSR: Usage Fault Status Register Position */ +#define SCB_CFSR_USGFAULTSR_Msk (0xFFFFUL << SCB_CFSR_USGFAULTSR_Pos) /*!< SCB CFSR: Usage Fault Status Register Mask */ -#define SCB_CFSR_BUSFAULTSR_Pos 8 /*!< SCB CFSR: Bus Fault Status Register Position */ -#define SCB_CFSR_BUSFAULTSR_Msk (0xFFUL << SCB_CFSR_BUSFAULTSR_Pos) /*!< SCB CFSR: Bus Fault Status Register Mask */ +#define SCB_CFSR_BUSFAULTSR_Pos 8 /*!< SCB CFSR: Bus Fault Status Register Position */ +#define SCB_CFSR_BUSFAULTSR_Msk (0xFFUL << SCB_CFSR_BUSFAULTSR_Pos) /*!< SCB CFSR: Bus Fault Status Register Mask */ -#define SCB_CFSR_MEMFAULTSR_Pos 0 /*!< SCB CFSR: Memory Manage Fault Status Register Position */ -#define SCB_CFSR_MEMFAULTSR_Msk (0xFFUL << SCB_CFSR_MEMFAULTSR_Pos) /*!< SCB CFSR: Memory Manage Fault Status Register Mask */ +#define SCB_CFSR_MEMFAULTSR_Pos 0 /*!< SCB CFSR: Memory Manage Fault Status Register Position */ +#define SCB_CFSR_MEMFAULTSR_Msk (0xFFUL << SCB_CFSR_MEMFAULTSR_Pos) /*!< SCB CFSR: Memory Manage Fault Status Register Mask */ /* SCB Hard Fault Status Registers Definitions */ -#define SCB_HFSR_DEBUGEVT_Pos 31 /*!< SCB HFSR: DEBUGEVT Position */ -#define SCB_HFSR_DEBUGEVT_Msk (1UL << SCB_HFSR_DEBUGEVT_Pos) /*!< SCB HFSR: DEBUGEVT Mask */ +#define SCB_HFSR_DEBUGEVT_Pos 31 /*!< SCB HFSR: DEBUGEVT Position */ +#define SCB_HFSR_DEBUGEVT_Msk (1UL << SCB_HFSR_DEBUGEVT_Pos) /*!< SCB HFSR: DEBUGEVT Mask */ -#define SCB_HFSR_FORCED_Pos 30 /*!< SCB HFSR: FORCED Position */ -#define SCB_HFSR_FORCED_Msk (1UL << SCB_HFSR_FORCED_Pos) /*!< SCB HFSR: FORCED Mask */ +#define SCB_HFSR_FORCED_Pos 30 /*!< SCB HFSR: FORCED Position */ +#define SCB_HFSR_FORCED_Msk (1UL << SCB_HFSR_FORCED_Pos) /*!< SCB HFSR: FORCED Mask */ -#define SCB_HFSR_VECTTBL_Pos 1 /*!< SCB HFSR: VECTTBL Position */ -#define SCB_HFSR_VECTTBL_Msk (1UL << SCB_HFSR_VECTTBL_Pos) /*!< SCB HFSR: VECTTBL Mask */ +#define SCB_HFSR_VECTTBL_Pos 1 /*!< SCB HFSR: VECTTBL Position */ +#define SCB_HFSR_VECTTBL_Msk (1UL << SCB_HFSR_VECTTBL_Pos) /*!< SCB HFSR: VECTTBL Mask */ /* SCB Debug Fault Status Register Definitions */ -#define SCB_DFSR_EXTERNAL_Pos 4 /*!< SCB DFSR: EXTERNAL Position */ -#define SCB_DFSR_EXTERNAL_Msk (1UL << SCB_DFSR_EXTERNAL_Pos) /*!< SCB DFSR: EXTERNAL Mask */ - -#define SCB_DFSR_VCATCH_Pos 3 /*!< SCB DFSR: VCATCH Position */ -#define SCB_DFSR_VCATCH_Msk (1UL << SCB_DFSR_VCATCH_Pos) /*!< SCB DFSR: VCATCH Mask */ +#define SCB_DFSR_EXTERNAL_Pos 4 /*!< SCB DFSR: EXTERNAL Position */ +#define SCB_DFSR_EXTERNAL_Msk (1UL << SCB_DFSR_EXTERNAL_Pos) /*!< SCB DFSR: EXTERNAL Mask */ -#define SCB_DFSR_DWTTRAP_Pos 2 /*!< SCB DFSR: DWTTRAP Position */ -#define SCB_DFSR_DWTTRAP_Msk (1UL << SCB_DFSR_DWTTRAP_Pos) /*!< SCB DFSR: DWTTRAP Mask */ +#define SCB_DFSR_VCATCH_Pos 3 /*!< SCB DFSR: VCATCH Position */ +#define SCB_DFSR_VCATCH_Msk (1UL << SCB_DFSR_VCATCH_Pos) /*!< SCB DFSR: VCATCH Mask */ -#define SCB_DFSR_BKPT_Pos 1 /*!< SCB DFSR: BKPT Position */ -#define SCB_DFSR_BKPT_Msk (1UL << SCB_DFSR_BKPT_Pos) /*!< SCB DFSR: BKPT Mask */ +#define SCB_DFSR_DWTTRAP_Pos 2 /*!< SCB DFSR: DWTTRAP Position */ +#define SCB_DFSR_DWTTRAP_Msk (1UL << SCB_DFSR_DWTTRAP_Pos) /*!< SCB DFSR: DWTTRAP Mask */ -#define SCB_DFSR_HALTED_Pos 0 /*!< SCB DFSR: HALTED Position */ -#define SCB_DFSR_HALTED_Msk (1UL << SCB_DFSR_HALTED_Pos) /*!< SCB DFSR: HALTED Mask */ +#define SCB_DFSR_BKPT_Pos 1 /*!< SCB DFSR: BKPT Position */ +#define SCB_DFSR_BKPT_Msk (1UL << SCB_DFSR_BKPT_Pos) /*!< SCB DFSR: BKPT Mask */ -/*@} end of group CMSIS_SCB */ +#define SCB_DFSR_HALTED_Pos 0 /*!< SCB DFSR: HALTED Position */ +#define SCB_DFSR_HALTED_Msk (1UL << SCB_DFSR_HALTED_Pos) /*!< SCB DFSR: HALTED Mask */ + /*@} end of group CMSIS_SCB */ -/** \ingroup CMSIS_core_register + /** \ingroup CMSIS_core_register \defgroup CMSIS_SCnSCB System Controls not in SCB (SCnSCB) \brief Type definitions for the System Control and ID Register not in the SCB @{ */ -/** \brief Structure type to access the System Control and ID Register not in the SCB. + /** \brief Structure type to access the System Control and ID Register not in the SCB. */ -typedef struct -{ - uint32_t RESERVED0[1]; - __I uint32_t ICTR; /*!< Offset: 0x004 (R/ ) Interrupt Controller Type Register */ + typedef struct + { + uint32_t RESERVED0[1]; + __I uint32_t ICTR; /*!< Offset: 0x004 (R/ ) Interrupt Controller Type Register */ #if ((defined __CM3_REV) && (__CM3_REV >= 0x200)) - __IO uint32_t ACTLR; /*!< Offset: 0x008 (R/W) Auxiliary Control Register */ + __IO uint32_t ACTLR; /*!< Offset: 0x008 (R/W) Auxiliary Control Register */ #else - uint32_t RESERVED1[1]; + uint32_t RESERVED1[1]; #endif -} SCnSCB_Type; + } SCnSCB_Type; /* Interrupt Controller Type Register Definitions */ -#define SCnSCB_ICTR_INTLINESNUM_Pos 0 /*!< ICTR: INTLINESNUM Position */ -#define SCnSCB_ICTR_INTLINESNUM_Msk (0xFUL << SCnSCB_ICTR_INTLINESNUM_Pos) /*!< ICTR: INTLINESNUM Mask */ - -/* Auxiliary Control Register Definitions */ +#define SCnSCB_ICTR_INTLINESNUM_Pos 0 /*!< ICTR: INTLINESNUM Position */ +#define SCnSCB_ICTR_INTLINESNUM_Msk (0xFUL << SCnSCB_ICTR_INTLINESNUM_Pos) /*!< ICTR: INTLINESNUM Mask */ -#define SCnSCB_ACTLR_DISFOLD_Pos 2 /*!< ACTLR: DISFOLD Position */ -#define SCnSCB_ACTLR_DISFOLD_Msk (1UL << SCnSCB_ACTLR_DISFOLD_Pos) /*!< ACTLR: DISFOLD Mask */ + /* Auxiliary Control Register Definitions */ -#define SCnSCB_ACTLR_DISDEFWBUF_Pos 1 /*!< ACTLR: DISDEFWBUF Position */ -#define SCnSCB_ACTLR_DISDEFWBUF_Msk (1UL << SCnSCB_ACTLR_DISDEFWBUF_Pos) /*!< ACTLR: DISDEFWBUF Mask */ +#define SCnSCB_ACTLR_DISFOLD_Pos 2 /*!< ACTLR: DISFOLD Position */ +#define SCnSCB_ACTLR_DISFOLD_Msk (1UL << SCnSCB_ACTLR_DISFOLD_Pos) /*!< ACTLR: DISFOLD Mask */ -#define SCnSCB_ACTLR_DISMCYCINT_Pos 0 /*!< ACTLR: DISMCYCINT Position */ -#define SCnSCB_ACTLR_DISMCYCINT_Msk (1UL << SCnSCB_ACTLR_DISMCYCINT_Pos) /*!< ACTLR: DISMCYCINT Mask */ +#define SCnSCB_ACTLR_DISDEFWBUF_Pos 1 /*!< ACTLR: DISDEFWBUF Position */ +#define SCnSCB_ACTLR_DISDEFWBUF_Msk (1UL << SCnSCB_ACTLR_DISDEFWBUF_Pos) /*!< ACTLR: DISDEFWBUF Mask */ -/*@} end of group CMSIS_SCnotSCB */ +#define SCnSCB_ACTLR_DISMCYCINT_Pos 0 /*!< ACTLR: DISMCYCINT Position */ +#define SCnSCB_ACTLR_DISMCYCINT_Msk (1UL << SCnSCB_ACTLR_DISMCYCINT_Pos) /*!< ACTLR: DISMCYCINT Mask */ + /*@} end of group CMSIS_SCnotSCB */ -/** \ingroup CMSIS_core_register + /** \ingroup CMSIS_core_register \defgroup CMSIS_SysTick System Tick Timer (SysTick) \brief Type definitions for the System Timer Registers. @{ */ -/** \brief Structure type to access the System Timer (SysTick). + /** \brief Structure type to access the System Timer (SysTick). */ -typedef struct -{ - __IO uint32_t CTRL; /*!< Offset: 0x000 (R/W) SysTick Control and Status Register */ - __IO uint32_t LOAD; /*!< Offset: 0x004 (R/W) SysTick Reload Value Register */ - __IO uint32_t VAL; /*!< Offset: 0x008 (R/W) SysTick Current Value Register */ - __I uint32_t CALIB; /*!< Offset: 0x00C (R/ ) SysTick Calibration Register */ -} SysTick_Type; + typedef struct + { + __IO uint32_t CTRL; /*!< Offset: 0x000 (R/W) SysTick Control and Status Register */ + __IO uint32_t LOAD; /*!< Offset: 0x004 (R/W) SysTick Reload Value Register */ + __IO uint32_t VAL; /*!< Offset: 0x008 (R/W) SysTick Current Value Register */ + __I uint32_t CALIB; /*!< Offset: 0x00C (R/ ) SysTick Calibration Register */ + } SysTick_Type; /* SysTick Control / Status Register Definitions */ -#define SysTick_CTRL_COUNTFLAG_Pos 16 /*!< SysTick CTRL: COUNTFLAG Position */ -#define SysTick_CTRL_COUNTFLAG_Msk (1UL << SysTick_CTRL_COUNTFLAG_Pos) /*!< SysTick CTRL: COUNTFLAG Mask */ +#define SysTick_CTRL_COUNTFLAG_Pos 16 /*!< SysTick CTRL: COUNTFLAG Position */ +#define SysTick_CTRL_COUNTFLAG_Msk (1UL << SysTick_CTRL_COUNTFLAG_Pos) /*!< SysTick CTRL: COUNTFLAG Mask */ -#define SysTick_CTRL_CLKSOURCE_Pos 2 /*!< SysTick CTRL: CLKSOURCE Position */ -#define SysTick_CTRL_CLKSOURCE_Msk (1UL << SysTick_CTRL_CLKSOURCE_Pos) /*!< SysTick CTRL: CLKSOURCE Mask */ +#define SysTick_CTRL_CLKSOURCE_Pos 2 /*!< SysTick CTRL: CLKSOURCE Position */ +#define SysTick_CTRL_CLKSOURCE_Msk (1UL << SysTick_CTRL_CLKSOURCE_Pos) /*!< SysTick CTRL: CLKSOURCE Mask */ -#define SysTick_CTRL_TICKINT_Pos 1 /*!< SysTick CTRL: TICKINT Position */ -#define SysTick_CTRL_TICKINT_Msk (1UL << SysTick_CTRL_TICKINT_Pos) /*!< SysTick CTRL: TICKINT Mask */ +#define SysTick_CTRL_TICKINT_Pos 1 /*!< SysTick CTRL: TICKINT Position */ +#define SysTick_CTRL_TICKINT_Msk (1UL << SysTick_CTRL_TICKINT_Pos) /*!< SysTick CTRL: TICKINT Mask */ -#define SysTick_CTRL_ENABLE_Pos 0 /*!< SysTick CTRL: ENABLE Position */ -#define SysTick_CTRL_ENABLE_Msk (1UL << SysTick_CTRL_ENABLE_Pos) /*!< SysTick CTRL: ENABLE Mask */ +#define SysTick_CTRL_ENABLE_Pos 0 /*!< SysTick CTRL: ENABLE Position */ +#define SysTick_CTRL_ENABLE_Msk (1UL << SysTick_CTRL_ENABLE_Pos) /*!< SysTick CTRL: ENABLE Mask */ /* SysTick Reload Register Definitions */ -#define SysTick_LOAD_RELOAD_Pos 0 /*!< SysTick LOAD: RELOAD Position */ -#define SysTick_LOAD_RELOAD_Msk (0xFFFFFFUL << SysTick_LOAD_RELOAD_Pos) /*!< SysTick LOAD: RELOAD Mask */ +#define SysTick_LOAD_RELOAD_Pos 0 /*!< SysTick LOAD: RELOAD Position */ +#define SysTick_LOAD_RELOAD_Msk (0xFFFFFFUL << SysTick_LOAD_RELOAD_Pos) /*!< SysTick LOAD: RELOAD Mask */ /* SysTick Current Register Definitions */ -#define SysTick_VAL_CURRENT_Pos 0 /*!< SysTick VAL: CURRENT Position */ -#define SysTick_VAL_CURRENT_Msk (0xFFFFFFUL << SysTick_VAL_CURRENT_Pos) /*!< SysTick VAL: CURRENT Mask */ +#define SysTick_VAL_CURRENT_Pos 0 /*!< SysTick VAL: CURRENT Position */ +#define SysTick_VAL_CURRENT_Msk (0xFFFFFFUL << SysTick_VAL_CURRENT_Pos) /*!< SysTick VAL: CURRENT Mask */ /* SysTick Calibration Register Definitions */ -#define SysTick_CALIB_NOREF_Pos 31 /*!< SysTick CALIB: NOREF Position */ -#define SysTick_CALIB_NOREF_Msk (1UL << SysTick_CALIB_NOREF_Pos) /*!< SysTick CALIB: NOREF Mask */ - -#define SysTick_CALIB_SKEW_Pos 30 /*!< SysTick CALIB: SKEW Position */ -#define SysTick_CALIB_SKEW_Msk (1UL << SysTick_CALIB_SKEW_Pos) /*!< SysTick CALIB: SKEW Mask */ +#define SysTick_CALIB_NOREF_Pos 31 /*!< SysTick CALIB: NOREF Position */ +#define SysTick_CALIB_NOREF_Msk (1UL << SysTick_CALIB_NOREF_Pos) /*!< SysTick CALIB: NOREF Mask */ -#define SysTick_CALIB_TENMS_Pos 0 /*!< SysTick CALIB: TENMS Position */ -#define SysTick_CALIB_TENMS_Msk (0xFFFFFFUL << SysTick_CALIB_TENMS_Pos) /*!< SysTick CALIB: TENMS Mask */ +#define SysTick_CALIB_SKEW_Pos 30 /*!< SysTick CALIB: SKEW Position */ +#define SysTick_CALIB_SKEW_Msk (1UL << SysTick_CALIB_SKEW_Pos) /*!< SysTick CALIB: SKEW Mask */ -/*@} end of group CMSIS_SysTick */ +#define SysTick_CALIB_TENMS_Pos 0 /*!< SysTick CALIB: TENMS Position */ +#define SysTick_CALIB_TENMS_Msk (0xFFFFFFUL << SysTick_CALIB_TENMS_Pos) /*!< SysTick CALIB: TENMS Mask */ + /*@} end of group CMSIS_SysTick */ -/** \ingroup CMSIS_core_register + /** \ingroup CMSIS_core_register \defgroup CMSIS_ITM Instrumentation Trace Macrocell (ITM) \brief Type definitions for the Instrumentation Trace Macrocell (ITM) @{ */ -/** \brief Structure type to access the Instrumentation Trace Macrocell Register (ITM). + /** \brief Structure type to access the Instrumentation Trace Macrocell Register (ITM). */ -typedef struct -{ - __O union - { - __O uint8_t u8; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 8-bit */ - __O uint16_t u16; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 16-bit */ - __O uint32_t u32; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 32-bit */ - } PORT [32]; /*!< Offset: 0x000 ( /W) ITM Stimulus Port Registers */ - uint32_t RESERVED0[864]; - __IO uint32_t TER; /*!< Offset: 0xE00 (R/W) ITM Trace Enable Register */ - uint32_t RESERVED1[15]; - __IO uint32_t TPR; /*!< Offset: 0xE40 (R/W) ITM Trace Privilege Register */ - uint32_t RESERVED2[15]; - __IO uint32_t TCR; /*!< Offset: 0xE80 (R/W) ITM Trace Control Register */ - uint32_t RESERVED3[29]; - __O uint32_t IWR; /*!< Offset: 0xEF8 ( /W) ITM Integration Write Register */ - __I uint32_t IRR; /*!< Offset: 0xEFC (R/ ) ITM Integration Read Register */ - __IO uint32_t IMCR; /*!< Offset: 0xF00 (R/W) ITM Integration Mode Control Register */ - uint32_t RESERVED4[43]; - __O uint32_t LAR; /*!< Offset: 0xFB0 ( /W) ITM Lock Access Register */ - __I uint32_t LSR; /*!< Offset: 0xFB4 (R/ ) ITM Lock Status Register */ - uint32_t RESERVED5[6]; - __I uint32_t PID4; /*!< Offset: 0xFD0 (R/ ) ITM Peripheral Identification Register #4 */ - __I uint32_t PID5; /*!< Offset: 0xFD4 (R/ ) ITM Peripheral Identification Register #5 */ - __I uint32_t PID6; /*!< Offset: 0xFD8 (R/ ) ITM Peripheral Identification Register #6 */ - __I uint32_t PID7; /*!< Offset: 0xFDC (R/ ) ITM Peripheral Identification Register #7 */ - __I uint32_t PID0; /*!< Offset: 0xFE0 (R/ ) ITM Peripheral Identification Register #0 */ - __I uint32_t PID1; /*!< Offset: 0xFE4 (R/ ) ITM Peripheral Identification Register #1 */ - __I uint32_t PID2; /*!< Offset: 0xFE8 (R/ ) ITM Peripheral Identification Register #2 */ - __I uint32_t PID3; /*!< Offset: 0xFEC (R/ ) ITM Peripheral Identification Register #3 */ - __I uint32_t CID0; /*!< Offset: 0xFF0 (R/ ) ITM Component Identification Register #0 */ - __I uint32_t CID1; /*!< Offset: 0xFF4 (R/ ) ITM Component Identification Register #1 */ - __I uint32_t CID2; /*!< Offset: 0xFF8 (R/ ) ITM Component Identification Register #2 */ - __I uint32_t CID3; /*!< Offset: 0xFFC (R/ ) ITM Component Identification Register #3 */ -} ITM_Type; + typedef struct + { + __O union + { + __O uint8_t u8; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 8-bit */ + __O uint16_t u16; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 16-bit */ + __O uint32_t u32; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 32-bit */ + } PORT[32]; /*!< Offset: 0x000 ( /W) ITM Stimulus Port Registers */ + uint32_t RESERVED0[864]; + __IO uint32_t TER; /*!< Offset: 0xE00 (R/W) ITM Trace Enable Register */ + uint32_t RESERVED1[15]; + __IO uint32_t TPR; /*!< Offset: 0xE40 (R/W) ITM Trace Privilege Register */ + uint32_t RESERVED2[15]; + __IO uint32_t TCR; /*!< Offset: 0xE80 (R/W) ITM Trace Control Register */ + uint32_t RESERVED3[29]; + __O uint32_t IWR; /*!< Offset: 0xEF8 ( /W) ITM Integration Write Register */ + __I uint32_t IRR; /*!< Offset: 0xEFC (R/ ) ITM Integration Read Register */ + __IO uint32_t IMCR; /*!< Offset: 0xF00 (R/W) ITM Integration Mode Control Register */ + uint32_t RESERVED4[43]; + __O uint32_t LAR; /*!< Offset: 0xFB0 ( /W) ITM Lock Access Register */ + __I uint32_t LSR; /*!< Offset: 0xFB4 (R/ ) ITM Lock Status Register */ + uint32_t RESERVED5[6]; + __I uint32_t PID4; /*!< Offset: 0xFD0 (R/ ) ITM Peripheral Identification Register #4 */ + __I uint32_t PID5; /*!< Offset: 0xFD4 (R/ ) ITM Peripheral Identification Register #5 */ + __I uint32_t PID6; /*!< Offset: 0xFD8 (R/ ) ITM Peripheral Identification Register #6 */ + __I uint32_t PID7; /*!< Offset: 0xFDC (R/ ) ITM Peripheral Identification Register #7 */ + __I uint32_t PID0; /*!< Offset: 0xFE0 (R/ ) ITM Peripheral Identification Register #0 */ + __I uint32_t PID1; /*!< Offset: 0xFE4 (R/ ) ITM Peripheral Identification Register #1 */ + __I uint32_t PID2; /*!< Offset: 0xFE8 (R/ ) ITM Peripheral Identification Register #2 */ + __I uint32_t PID3; /*!< Offset: 0xFEC (R/ ) ITM Peripheral Identification Register #3 */ + __I uint32_t CID0; /*!< Offset: 0xFF0 (R/ ) ITM Component Identification Register #0 */ + __I uint32_t CID1; /*!< Offset: 0xFF4 (R/ ) ITM Component Identification Register #1 */ + __I uint32_t CID2; /*!< Offset: 0xFF8 (R/ ) ITM Component Identification Register #2 */ + __I uint32_t CID3; /*!< Offset: 0xFFC (R/ ) ITM Component Identification Register #3 */ + } ITM_Type; /* ITM Trace Privilege Register Definitions */ -#define ITM_TPR_PRIVMASK_Pos 0 /*!< ITM TPR: PRIVMASK Position */ -#define ITM_TPR_PRIVMASK_Msk (0xFUL << ITM_TPR_PRIVMASK_Pos) /*!< ITM TPR: PRIVMASK Mask */ +#define ITM_TPR_PRIVMASK_Pos 0 /*!< ITM TPR: PRIVMASK Position */ +#define ITM_TPR_PRIVMASK_Msk (0xFUL << ITM_TPR_PRIVMASK_Pos) /*!< ITM TPR: PRIVMASK Mask */ /* ITM Trace Control Register Definitions */ -#define ITM_TCR_BUSY_Pos 23 /*!< ITM TCR: BUSY Position */ -#define ITM_TCR_BUSY_Msk (1UL << ITM_TCR_BUSY_Pos) /*!< ITM TCR: BUSY Mask */ +#define ITM_TCR_BUSY_Pos 23 /*!< ITM TCR: BUSY Position */ +#define ITM_TCR_BUSY_Msk (1UL << ITM_TCR_BUSY_Pos) /*!< ITM TCR: BUSY Mask */ -#define ITM_TCR_TraceBusID_Pos 16 /*!< ITM TCR: ATBID Position */ -#define ITM_TCR_TraceBusID_Msk (0x7FUL << ITM_TCR_TraceBusID_Pos) /*!< ITM TCR: ATBID Mask */ +#define ITM_TCR_TraceBusID_Pos 16 /*!< ITM TCR: ATBID Position */ +#define ITM_TCR_TraceBusID_Msk (0x7FUL << ITM_TCR_TraceBusID_Pos) /*!< ITM TCR: ATBID Mask */ -#define ITM_TCR_GTSFREQ_Pos 10 /*!< ITM TCR: Global timestamp frequency Position */ -#define ITM_TCR_GTSFREQ_Msk (3UL << ITM_TCR_GTSFREQ_Pos) /*!< ITM TCR: Global timestamp frequency Mask */ +#define ITM_TCR_GTSFREQ_Pos 10 /*!< ITM TCR: Global timestamp frequency Position */ +#define ITM_TCR_GTSFREQ_Msk (3UL << ITM_TCR_GTSFREQ_Pos) /*!< ITM TCR: Global timestamp frequency Mask */ -#define ITM_TCR_TSPrescale_Pos 8 /*!< ITM TCR: TSPrescale Position */ -#define ITM_TCR_TSPrescale_Msk (3UL << ITM_TCR_TSPrescale_Pos) /*!< ITM TCR: TSPrescale Mask */ +#define ITM_TCR_TSPrescale_Pos 8 /*!< ITM TCR: TSPrescale Position */ +#define ITM_TCR_TSPrescale_Msk (3UL << ITM_TCR_TSPrescale_Pos) /*!< ITM TCR: TSPrescale Mask */ -#define ITM_TCR_SWOENA_Pos 4 /*!< ITM TCR: SWOENA Position */ -#define ITM_TCR_SWOENA_Msk (1UL << ITM_TCR_SWOENA_Pos) /*!< ITM TCR: SWOENA Mask */ +#define ITM_TCR_SWOENA_Pos 4 /*!< ITM TCR: SWOENA Position */ +#define ITM_TCR_SWOENA_Msk (1UL << ITM_TCR_SWOENA_Pos) /*!< ITM TCR: SWOENA Mask */ -#define ITM_TCR_DWTENA_Pos 3 /*!< ITM TCR: DWTENA Position */ -#define ITM_TCR_DWTENA_Msk (1UL << ITM_TCR_DWTENA_Pos) /*!< ITM TCR: DWTENA Mask */ +#define ITM_TCR_DWTENA_Pos 3 /*!< ITM TCR: DWTENA Position */ +#define ITM_TCR_DWTENA_Msk (1UL << ITM_TCR_DWTENA_Pos) /*!< ITM TCR: DWTENA Mask */ -#define ITM_TCR_SYNCENA_Pos 2 /*!< ITM TCR: SYNCENA Position */ -#define ITM_TCR_SYNCENA_Msk (1UL << ITM_TCR_SYNCENA_Pos) /*!< ITM TCR: SYNCENA Mask */ +#define ITM_TCR_SYNCENA_Pos 2 /*!< ITM TCR: SYNCENA Position */ +#define ITM_TCR_SYNCENA_Msk (1UL << ITM_TCR_SYNCENA_Pos) /*!< ITM TCR: SYNCENA Mask */ -#define ITM_TCR_TSENA_Pos 1 /*!< ITM TCR: TSENA Position */ -#define ITM_TCR_TSENA_Msk (1UL << ITM_TCR_TSENA_Pos) /*!< ITM TCR: TSENA Mask */ +#define ITM_TCR_TSENA_Pos 1 /*!< ITM TCR: TSENA Position */ +#define ITM_TCR_TSENA_Msk (1UL << ITM_TCR_TSENA_Pos) /*!< ITM TCR: TSENA Mask */ -#define ITM_TCR_ITMENA_Pos 0 /*!< ITM TCR: ITM Enable bit Position */ -#define ITM_TCR_ITMENA_Msk (1UL << ITM_TCR_ITMENA_Pos) /*!< ITM TCR: ITM Enable bit Mask */ +#define ITM_TCR_ITMENA_Pos 0 /*!< ITM TCR: ITM Enable bit Position */ +#define ITM_TCR_ITMENA_Msk (1UL << ITM_TCR_ITMENA_Pos) /*!< ITM TCR: ITM Enable bit Mask */ /* ITM Integration Write Register Definitions */ -#define ITM_IWR_ATVALIDM_Pos 0 /*!< ITM IWR: ATVALIDM Position */ -#define ITM_IWR_ATVALIDM_Msk (1UL << ITM_IWR_ATVALIDM_Pos) /*!< ITM IWR: ATVALIDM Mask */ +#define ITM_IWR_ATVALIDM_Pos 0 /*!< ITM IWR: ATVALIDM Position */ +#define ITM_IWR_ATVALIDM_Msk (1UL << ITM_IWR_ATVALIDM_Pos) /*!< ITM IWR: ATVALIDM Mask */ /* ITM Integration Read Register Definitions */ -#define ITM_IRR_ATREADYM_Pos 0 /*!< ITM IRR: ATREADYM Position */ -#define ITM_IRR_ATREADYM_Msk (1UL << ITM_IRR_ATREADYM_Pos) /*!< ITM IRR: ATREADYM Mask */ +#define ITM_IRR_ATREADYM_Pos 0 /*!< ITM IRR: ATREADYM Position */ +#define ITM_IRR_ATREADYM_Msk (1UL << ITM_IRR_ATREADYM_Pos) /*!< ITM IRR: ATREADYM Mask */ /* ITM Integration Mode Control Register Definitions */ -#define ITM_IMCR_INTEGRATION_Pos 0 /*!< ITM IMCR: INTEGRATION Position */ -#define ITM_IMCR_INTEGRATION_Msk (1UL << ITM_IMCR_INTEGRATION_Pos) /*!< ITM IMCR: INTEGRATION Mask */ +#define ITM_IMCR_INTEGRATION_Pos 0 /*!< ITM IMCR: INTEGRATION Position */ +#define ITM_IMCR_INTEGRATION_Msk (1UL << ITM_IMCR_INTEGRATION_Pos) /*!< ITM IMCR: INTEGRATION Mask */ /* ITM Lock Status Register Definitions */ -#define ITM_LSR_ByteAcc_Pos 2 /*!< ITM LSR: ByteAcc Position */ -#define ITM_LSR_ByteAcc_Msk (1UL << ITM_LSR_ByteAcc_Pos) /*!< ITM LSR: ByteAcc Mask */ - -#define ITM_LSR_Access_Pos 1 /*!< ITM LSR: Access Position */ -#define ITM_LSR_Access_Msk (1UL << ITM_LSR_Access_Pos) /*!< ITM LSR: Access Mask */ +#define ITM_LSR_ByteAcc_Pos 2 /*!< ITM LSR: ByteAcc Position */ +#define ITM_LSR_ByteAcc_Msk (1UL << ITM_LSR_ByteAcc_Pos) /*!< ITM LSR: ByteAcc Mask */ -#define ITM_LSR_Present_Pos 0 /*!< ITM LSR: Present Position */ -#define ITM_LSR_Present_Msk (1UL << ITM_LSR_Present_Pos) /*!< ITM LSR: Present Mask */ +#define ITM_LSR_Access_Pos 1 /*!< ITM LSR: Access Position */ +#define ITM_LSR_Access_Msk (1UL << ITM_LSR_Access_Pos) /*!< ITM LSR: Access Mask */ -/*@}*/ /* end of group CMSIS_ITM */ +#define ITM_LSR_Present_Pos 0 /*!< ITM LSR: Present Position */ +#define ITM_LSR_Present_Msk (1UL << ITM_LSR_Present_Pos) /*!< ITM LSR: Present Mask */ + /*@}*/ /* end of group CMSIS_ITM */ -/** \ingroup CMSIS_core_register + /** \ingroup CMSIS_core_register \defgroup CMSIS_DWT Data Watchpoint and Trace (DWT) \brief Type definitions for the Data Watchpoint and Trace (DWT) @{ */ -/** \brief Structure type to access the Data Watchpoint and Trace Register (DWT). + /** \brief Structure type to access the Data Watchpoint and Trace Register (DWT). */ -typedef struct -{ - __IO uint32_t CTRL; /*!< Offset: 0x000 (R/W) Control Register */ - __IO uint32_t CYCCNT; /*!< Offset: 0x004 (R/W) Cycle Count Register */ - __IO uint32_t CPICNT; /*!< Offset: 0x008 (R/W) CPI Count Register */ - __IO uint32_t EXCCNT; /*!< Offset: 0x00C (R/W) Exception Overhead Count Register */ - __IO uint32_t SLEEPCNT; /*!< Offset: 0x010 (R/W) Sleep Count Register */ - __IO uint32_t LSUCNT; /*!< Offset: 0x014 (R/W) LSU Count Register */ - __IO uint32_t FOLDCNT; /*!< Offset: 0x018 (R/W) Folded-instruction Count Register */ - __I uint32_t PCSR; /*!< Offset: 0x01C (R/ ) Program Counter Sample Register */ - __IO uint32_t COMP0; /*!< Offset: 0x020 (R/W) Comparator Register 0 */ - __IO uint32_t MASK0; /*!< Offset: 0x024 (R/W) Mask Register 0 */ - __IO uint32_t FUNCTION0; /*!< Offset: 0x028 (R/W) Function Register 0 */ - uint32_t RESERVED0[1]; - __IO uint32_t COMP1; /*!< Offset: 0x030 (R/W) Comparator Register 1 */ - __IO uint32_t MASK1; /*!< Offset: 0x034 (R/W) Mask Register 1 */ - __IO uint32_t FUNCTION1; /*!< Offset: 0x038 (R/W) Function Register 1 */ - uint32_t RESERVED1[1]; - __IO uint32_t COMP2; /*!< Offset: 0x040 (R/W) Comparator Register 2 */ - __IO uint32_t MASK2; /*!< Offset: 0x044 (R/W) Mask Register 2 */ - __IO uint32_t FUNCTION2; /*!< Offset: 0x048 (R/W) Function Register 2 */ - uint32_t RESERVED2[1]; - __IO uint32_t COMP3; /*!< Offset: 0x050 (R/W) Comparator Register 3 */ - __IO uint32_t MASK3; /*!< Offset: 0x054 (R/W) Mask Register 3 */ - __IO uint32_t FUNCTION3; /*!< Offset: 0x058 (R/W) Function Register 3 */ -} DWT_Type; + typedef struct + { + __IO uint32_t CTRL; /*!< Offset: 0x000 (R/W) Control Register */ + __IO uint32_t CYCCNT; /*!< Offset: 0x004 (R/W) Cycle Count Register */ + __IO uint32_t CPICNT; /*!< Offset: 0x008 (R/W) CPI Count Register */ + __IO uint32_t EXCCNT; /*!< Offset: 0x00C (R/W) Exception Overhead Count Register */ + __IO uint32_t SLEEPCNT; /*!< Offset: 0x010 (R/W) Sleep Count Register */ + __IO uint32_t LSUCNT; /*!< Offset: 0x014 (R/W) LSU Count Register */ + __IO uint32_t FOLDCNT; /*!< Offset: 0x018 (R/W) Folded-instruction Count Register */ + __I uint32_t PCSR; /*!< Offset: 0x01C (R/ ) Program Counter Sample Register */ + __IO uint32_t COMP0; /*!< Offset: 0x020 (R/W) Comparator Register 0 */ + __IO uint32_t MASK0; /*!< Offset: 0x024 (R/W) Mask Register 0 */ + __IO uint32_t FUNCTION0; /*!< Offset: 0x028 (R/W) Function Register 0 */ + uint32_t RESERVED0[1]; + __IO uint32_t COMP1; /*!< Offset: 0x030 (R/W) Comparator Register 1 */ + __IO uint32_t MASK1; /*!< Offset: 0x034 (R/W) Mask Register 1 */ + __IO uint32_t FUNCTION1; /*!< Offset: 0x038 (R/W) Function Register 1 */ + uint32_t RESERVED1[1]; + __IO uint32_t COMP2; /*!< Offset: 0x040 (R/W) Comparator Register 2 */ + __IO uint32_t MASK2; /*!< Offset: 0x044 (R/W) Mask Register 2 */ + __IO uint32_t FUNCTION2; /*!< Offset: 0x048 (R/W) Function Register 2 */ + uint32_t RESERVED2[1]; + __IO uint32_t COMP3; /*!< Offset: 0x050 (R/W) Comparator Register 3 */ + __IO uint32_t MASK3; /*!< Offset: 0x054 (R/W) Mask Register 3 */ + __IO uint32_t FUNCTION3; /*!< Offset: 0x058 (R/W) Function Register 3 */ + } DWT_Type; /* DWT Control Register Definitions */ -#define DWT_CTRL_NUMCOMP_Pos 28 /*!< DWT CTRL: NUMCOMP Position */ -#define DWT_CTRL_NUMCOMP_Msk (0xFUL << DWT_CTRL_NUMCOMP_Pos) /*!< DWT CTRL: NUMCOMP Mask */ +#define DWT_CTRL_NUMCOMP_Pos 28 /*!< DWT CTRL: NUMCOMP Position */ +#define DWT_CTRL_NUMCOMP_Msk (0xFUL << DWT_CTRL_NUMCOMP_Pos) /*!< DWT CTRL: NUMCOMP Mask */ -#define DWT_CTRL_NOTRCPKT_Pos 27 /*!< DWT CTRL: NOTRCPKT Position */ -#define DWT_CTRL_NOTRCPKT_Msk (0x1UL << DWT_CTRL_NOTRCPKT_Pos) /*!< DWT CTRL: NOTRCPKT Mask */ +#define DWT_CTRL_NOTRCPKT_Pos 27 /*!< DWT CTRL: NOTRCPKT Position */ +#define DWT_CTRL_NOTRCPKT_Msk (0x1UL << DWT_CTRL_NOTRCPKT_Pos) /*!< DWT CTRL: NOTRCPKT Mask */ -#define DWT_CTRL_NOEXTTRIG_Pos 26 /*!< DWT CTRL: NOEXTTRIG Position */ -#define DWT_CTRL_NOEXTTRIG_Msk (0x1UL << DWT_CTRL_NOEXTTRIG_Pos) /*!< DWT CTRL: NOEXTTRIG Mask */ +#define DWT_CTRL_NOEXTTRIG_Pos 26 /*!< DWT CTRL: NOEXTTRIG Position */ +#define DWT_CTRL_NOEXTTRIG_Msk (0x1UL << DWT_CTRL_NOEXTTRIG_Pos) /*!< DWT CTRL: NOEXTTRIG Mask */ -#define DWT_CTRL_NOCYCCNT_Pos 25 /*!< DWT CTRL: NOCYCCNT Position */ -#define DWT_CTRL_NOCYCCNT_Msk (0x1UL << DWT_CTRL_NOCYCCNT_Pos) /*!< DWT CTRL: NOCYCCNT Mask */ +#define DWT_CTRL_NOCYCCNT_Pos 25 /*!< DWT CTRL: NOCYCCNT Position */ +#define DWT_CTRL_NOCYCCNT_Msk (0x1UL << DWT_CTRL_NOCYCCNT_Pos) /*!< DWT CTRL: NOCYCCNT Mask */ -#define DWT_CTRL_NOPRFCNT_Pos 24 /*!< DWT CTRL: NOPRFCNT Position */ -#define DWT_CTRL_NOPRFCNT_Msk (0x1UL << DWT_CTRL_NOPRFCNT_Pos) /*!< DWT CTRL: NOPRFCNT Mask */ +#define DWT_CTRL_NOPRFCNT_Pos 24 /*!< DWT CTRL: NOPRFCNT Position */ +#define DWT_CTRL_NOPRFCNT_Msk (0x1UL << DWT_CTRL_NOPRFCNT_Pos) /*!< DWT CTRL: NOPRFCNT Mask */ -#define DWT_CTRL_CYCEVTENA_Pos 22 /*!< DWT CTRL: CYCEVTENA Position */ -#define DWT_CTRL_CYCEVTENA_Msk (0x1UL << DWT_CTRL_CYCEVTENA_Pos) /*!< DWT CTRL: CYCEVTENA Mask */ +#define DWT_CTRL_CYCEVTENA_Pos 22 /*!< DWT CTRL: CYCEVTENA Position */ +#define DWT_CTRL_CYCEVTENA_Msk (0x1UL << DWT_CTRL_CYCEVTENA_Pos) /*!< DWT CTRL: CYCEVTENA Mask */ -#define DWT_CTRL_FOLDEVTENA_Pos 21 /*!< DWT CTRL: FOLDEVTENA Position */ -#define DWT_CTRL_FOLDEVTENA_Msk (0x1UL << DWT_CTRL_FOLDEVTENA_Pos) /*!< DWT CTRL: FOLDEVTENA Mask */ +#define DWT_CTRL_FOLDEVTENA_Pos 21 /*!< DWT CTRL: FOLDEVTENA Position */ +#define DWT_CTRL_FOLDEVTENA_Msk (0x1UL << DWT_CTRL_FOLDEVTENA_Pos) /*!< DWT CTRL: FOLDEVTENA Mask */ -#define DWT_CTRL_LSUEVTENA_Pos 20 /*!< DWT CTRL: LSUEVTENA Position */ -#define DWT_CTRL_LSUEVTENA_Msk (0x1UL << DWT_CTRL_LSUEVTENA_Pos) /*!< DWT CTRL: LSUEVTENA Mask */ +#define DWT_CTRL_LSUEVTENA_Pos 20 /*!< DWT CTRL: LSUEVTENA Position */ +#define DWT_CTRL_LSUEVTENA_Msk (0x1UL << DWT_CTRL_LSUEVTENA_Pos) /*!< DWT CTRL: LSUEVTENA Mask */ -#define DWT_CTRL_SLEEPEVTENA_Pos 19 /*!< DWT CTRL: SLEEPEVTENA Position */ -#define DWT_CTRL_SLEEPEVTENA_Msk (0x1UL << DWT_CTRL_SLEEPEVTENA_Pos) /*!< DWT CTRL: SLEEPEVTENA Mask */ +#define DWT_CTRL_SLEEPEVTENA_Pos 19 /*!< DWT CTRL: SLEEPEVTENA Position */ +#define DWT_CTRL_SLEEPEVTENA_Msk (0x1UL << DWT_CTRL_SLEEPEVTENA_Pos) /*!< DWT CTRL: SLEEPEVTENA Mask */ -#define DWT_CTRL_EXCEVTENA_Pos 18 /*!< DWT CTRL: EXCEVTENA Position */ -#define DWT_CTRL_EXCEVTENA_Msk (0x1UL << DWT_CTRL_EXCEVTENA_Pos) /*!< DWT CTRL: EXCEVTENA Mask */ +#define DWT_CTRL_EXCEVTENA_Pos 18 /*!< DWT CTRL: EXCEVTENA Position */ +#define DWT_CTRL_EXCEVTENA_Msk (0x1UL << DWT_CTRL_EXCEVTENA_Pos) /*!< DWT CTRL: EXCEVTENA Mask */ -#define DWT_CTRL_CPIEVTENA_Pos 17 /*!< DWT CTRL: CPIEVTENA Position */ -#define DWT_CTRL_CPIEVTENA_Msk (0x1UL << DWT_CTRL_CPIEVTENA_Pos) /*!< DWT CTRL: CPIEVTENA Mask */ +#define DWT_CTRL_CPIEVTENA_Pos 17 /*!< DWT CTRL: CPIEVTENA Position */ +#define DWT_CTRL_CPIEVTENA_Msk (0x1UL << DWT_CTRL_CPIEVTENA_Pos) /*!< DWT CTRL: CPIEVTENA Mask */ -#define DWT_CTRL_EXCTRCENA_Pos 16 /*!< DWT CTRL: EXCTRCENA Position */ -#define DWT_CTRL_EXCTRCENA_Msk (0x1UL << DWT_CTRL_EXCTRCENA_Pos) /*!< DWT CTRL: EXCTRCENA Mask */ +#define DWT_CTRL_EXCTRCENA_Pos 16 /*!< DWT CTRL: EXCTRCENA Position */ +#define DWT_CTRL_EXCTRCENA_Msk (0x1UL << DWT_CTRL_EXCTRCENA_Pos) /*!< DWT CTRL: EXCTRCENA Mask */ -#define DWT_CTRL_PCSAMPLENA_Pos 12 /*!< DWT CTRL: PCSAMPLENA Position */ -#define DWT_CTRL_PCSAMPLENA_Msk (0x1UL << DWT_CTRL_PCSAMPLENA_Pos) /*!< DWT CTRL: PCSAMPLENA Mask */ +#define DWT_CTRL_PCSAMPLENA_Pos 12 /*!< DWT CTRL: PCSAMPLENA Position */ +#define DWT_CTRL_PCSAMPLENA_Msk (0x1UL << DWT_CTRL_PCSAMPLENA_Pos) /*!< DWT CTRL: PCSAMPLENA Mask */ -#define DWT_CTRL_SYNCTAP_Pos 10 /*!< DWT CTRL: SYNCTAP Position */ -#define DWT_CTRL_SYNCTAP_Msk (0x3UL << DWT_CTRL_SYNCTAP_Pos) /*!< DWT CTRL: SYNCTAP Mask */ +#define DWT_CTRL_SYNCTAP_Pos 10 /*!< DWT CTRL: SYNCTAP Position */ +#define DWT_CTRL_SYNCTAP_Msk (0x3UL << DWT_CTRL_SYNCTAP_Pos) /*!< DWT CTRL: SYNCTAP Mask */ -#define DWT_CTRL_CYCTAP_Pos 9 /*!< DWT CTRL: CYCTAP Position */ -#define DWT_CTRL_CYCTAP_Msk (0x1UL << DWT_CTRL_CYCTAP_Pos) /*!< DWT CTRL: CYCTAP Mask */ +#define DWT_CTRL_CYCTAP_Pos 9 /*!< DWT CTRL: CYCTAP Position */ +#define DWT_CTRL_CYCTAP_Msk (0x1UL << DWT_CTRL_CYCTAP_Pos) /*!< DWT CTRL: CYCTAP Mask */ -#define DWT_CTRL_POSTINIT_Pos 5 /*!< DWT CTRL: POSTINIT Position */ -#define DWT_CTRL_POSTINIT_Msk (0xFUL << DWT_CTRL_POSTINIT_Pos) /*!< DWT CTRL: POSTINIT Mask */ +#define DWT_CTRL_POSTINIT_Pos 5 /*!< DWT CTRL: POSTINIT Position */ +#define DWT_CTRL_POSTINIT_Msk (0xFUL << DWT_CTRL_POSTINIT_Pos) /*!< DWT CTRL: POSTINIT Mask */ -#define DWT_CTRL_POSTPRESET_Pos 1 /*!< DWT CTRL: POSTPRESET Position */ -#define DWT_CTRL_POSTPRESET_Msk (0xFUL << DWT_CTRL_POSTPRESET_Pos) /*!< DWT CTRL: POSTPRESET Mask */ +#define DWT_CTRL_POSTPRESET_Pos 1 /*!< DWT CTRL: POSTPRESET Position */ +#define DWT_CTRL_POSTPRESET_Msk (0xFUL << DWT_CTRL_POSTPRESET_Pos) /*!< DWT CTRL: POSTPRESET Mask */ -#define DWT_CTRL_CYCCNTENA_Pos 0 /*!< DWT CTRL: CYCCNTENA Position */ -#define DWT_CTRL_CYCCNTENA_Msk (0x1UL << DWT_CTRL_CYCCNTENA_Pos) /*!< DWT CTRL: CYCCNTENA Mask */ +#define DWT_CTRL_CYCCNTENA_Pos 0 /*!< DWT CTRL: CYCCNTENA Position */ +#define DWT_CTRL_CYCCNTENA_Msk (0x1UL << DWT_CTRL_CYCCNTENA_Pos) /*!< DWT CTRL: CYCCNTENA Mask */ /* DWT CPI Count Register Definitions */ -#define DWT_CPICNT_CPICNT_Pos 0 /*!< DWT CPICNT: CPICNT Position */ -#define DWT_CPICNT_CPICNT_Msk (0xFFUL << DWT_CPICNT_CPICNT_Pos) /*!< DWT CPICNT: CPICNT Mask */ +#define DWT_CPICNT_CPICNT_Pos 0 /*!< DWT CPICNT: CPICNT Position */ +#define DWT_CPICNT_CPICNT_Msk (0xFFUL << DWT_CPICNT_CPICNT_Pos) /*!< DWT CPICNT: CPICNT Mask */ /* DWT Exception Overhead Count Register Definitions */ -#define DWT_EXCCNT_EXCCNT_Pos 0 /*!< DWT EXCCNT: EXCCNT Position */ -#define DWT_EXCCNT_EXCCNT_Msk (0xFFUL << DWT_EXCCNT_EXCCNT_Pos) /*!< DWT EXCCNT: EXCCNT Mask */ +#define DWT_EXCCNT_EXCCNT_Pos 0 /*!< DWT EXCCNT: EXCCNT Position */ +#define DWT_EXCCNT_EXCCNT_Msk (0xFFUL << DWT_EXCCNT_EXCCNT_Pos) /*!< DWT EXCCNT: EXCCNT Mask */ /* DWT Sleep Count Register Definitions */ -#define DWT_SLEEPCNT_SLEEPCNT_Pos 0 /*!< DWT SLEEPCNT: SLEEPCNT Position */ -#define DWT_SLEEPCNT_SLEEPCNT_Msk (0xFFUL << DWT_SLEEPCNT_SLEEPCNT_Pos) /*!< DWT SLEEPCNT: SLEEPCNT Mask */ +#define DWT_SLEEPCNT_SLEEPCNT_Pos 0 /*!< DWT SLEEPCNT: SLEEPCNT Position */ +#define DWT_SLEEPCNT_SLEEPCNT_Msk (0xFFUL << DWT_SLEEPCNT_SLEEPCNT_Pos) /*!< DWT SLEEPCNT: SLEEPCNT Mask */ /* DWT LSU Count Register Definitions */ -#define DWT_LSUCNT_LSUCNT_Pos 0 /*!< DWT LSUCNT: LSUCNT Position */ -#define DWT_LSUCNT_LSUCNT_Msk (0xFFUL << DWT_LSUCNT_LSUCNT_Pos) /*!< DWT LSUCNT: LSUCNT Mask */ +#define DWT_LSUCNT_LSUCNT_Pos 0 /*!< DWT LSUCNT: LSUCNT Position */ +#define DWT_LSUCNT_LSUCNT_Msk (0xFFUL << DWT_LSUCNT_LSUCNT_Pos) /*!< DWT LSUCNT: LSUCNT Mask */ /* DWT Folded-instruction Count Register Definitions */ -#define DWT_FOLDCNT_FOLDCNT_Pos 0 /*!< DWT FOLDCNT: FOLDCNT Position */ -#define DWT_FOLDCNT_FOLDCNT_Msk (0xFFUL << DWT_FOLDCNT_FOLDCNT_Pos) /*!< DWT FOLDCNT: FOLDCNT Mask */ +#define DWT_FOLDCNT_FOLDCNT_Pos 0 /*!< DWT FOLDCNT: FOLDCNT Position */ +#define DWT_FOLDCNT_FOLDCNT_Msk (0xFFUL << DWT_FOLDCNT_FOLDCNT_Pos) /*!< DWT FOLDCNT: FOLDCNT Mask */ /* DWT Comparator Mask Register Definitions */ -#define DWT_MASK_MASK_Pos 0 /*!< DWT MASK: MASK Position */ -#define DWT_MASK_MASK_Msk (0x1FUL << DWT_MASK_MASK_Pos) /*!< DWT MASK: MASK Mask */ +#define DWT_MASK_MASK_Pos 0 /*!< DWT MASK: MASK Position */ +#define DWT_MASK_MASK_Msk (0x1FUL << DWT_MASK_MASK_Pos) /*!< DWT MASK: MASK Mask */ /* DWT Comparator Function Register Definitions */ -#define DWT_FUNCTION_MATCHED_Pos 24 /*!< DWT FUNCTION: MATCHED Position */ -#define DWT_FUNCTION_MATCHED_Msk (0x1UL << DWT_FUNCTION_MATCHED_Pos) /*!< DWT FUNCTION: MATCHED Mask */ - -#define DWT_FUNCTION_DATAVADDR1_Pos 16 /*!< DWT FUNCTION: DATAVADDR1 Position */ -#define DWT_FUNCTION_DATAVADDR1_Msk (0xFUL << DWT_FUNCTION_DATAVADDR1_Pos) /*!< DWT FUNCTION: DATAVADDR1 Mask */ +#define DWT_FUNCTION_MATCHED_Pos 24 /*!< DWT FUNCTION: MATCHED Position */ +#define DWT_FUNCTION_MATCHED_Msk (0x1UL << DWT_FUNCTION_MATCHED_Pos) /*!< DWT FUNCTION: MATCHED Mask */ -#define DWT_FUNCTION_DATAVADDR0_Pos 12 /*!< DWT FUNCTION: DATAVADDR0 Position */ -#define DWT_FUNCTION_DATAVADDR0_Msk (0xFUL << DWT_FUNCTION_DATAVADDR0_Pos) /*!< DWT FUNCTION: DATAVADDR0 Mask */ +#define DWT_FUNCTION_DATAVADDR1_Pos 16 /*!< DWT FUNCTION: DATAVADDR1 Position */ +#define DWT_FUNCTION_DATAVADDR1_Msk (0xFUL << DWT_FUNCTION_DATAVADDR1_Pos) /*!< DWT FUNCTION: DATAVADDR1 Mask */ -#define DWT_FUNCTION_DATAVSIZE_Pos 10 /*!< DWT FUNCTION: DATAVSIZE Position */ -#define DWT_FUNCTION_DATAVSIZE_Msk (0x3UL << DWT_FUNCTION_DATAVSIZE_Pos) /*!< DWT FUNCTION: DATAVSIZE Mask */ +#define DWT_FUNCTION_DATAVADDR0_Pos 12 /*!< DWT FUNCTION: DATAVADDR0 Position */ +#define DWT_FUNCTION_DATAVADDR0_Msk (0xFUL << DWT_FUNCTION_DATAVADDR0_Pos) /*!< DWT FUNCTION: DATAVADDR0 Mask */ -#define DWT_FUNCTION_LNK1ENA_Pos 9 /*!< DWT FUNCTION: LNK1ENA Position */ -#define DWT_FUNCTION_LNK1ENA_Msk (0x1UL << DWT_FUNCTION_LNK1ENA_Pos) /*!< DWT FUNCTION: LNK1ENA Mask */ +#define DWT_FUNCTION_DATAVSIZE_Pos 10 /*!< DWT FUNCTION: DATAVSIZE Position */ +#define DWT_FUNCTION_DATAVSIZE_Msk (0x3UL << DWT_FUNCTION_DATAVSIZE_Pos) /*!< DWT FUNCTION: DATAVSIZE Mask */ -#define DWT_FUNCTION_DATAVMATCH_Pos 8 /*!< DWT FUNCTION: DATAVMATCH Position */ -#define DWT_FUNCTION_DATAVMATCH_Msk (0x1UL << DWT_FUNCTION_DATAVMATCH_Pos) /*!< DWT FUNCTION: DATAVMATCH Mask */ +#define DWT_FUNCTION_LNK1ENA_Pos 9 /*!< DWT FUNCTION: LNK1ENA Position */ +#define DWT_FUNCTION_LNK1ENA_Msk (0x1UL << DWT_FUNCTION_LNK1ENA_Pos) /*!< DWT FUNCTION: LNK1ENA Mask */ -#define DWT_FUNCTION_CYCMATCH_Pos 7 /*!< DWT FUNCTION: CYCMATCH Position */ -#define DWT_FUNCTION_CYCMATCH_Msk (0x1UL << DWT_FUNCTION_CYCMATCH_Pos) /*!< DWT FUNCTION: CYCMATCH Mask */ +#define DWT_FUNCTION_DATAVMATCH_Pos 8 /*!< DWT FUNCTION: DATAVMATCH Position */ +#define DWT_FUNCTION_DATAVMATCH_Msk (0x1UL << DWT_FUNCTION_DATAVMATCH_Pos) /*!< DWT FUNCTION: DATAVMATCH Mask */ -#define DWT_FUNCTION_EMITRANGE_Pos 5 /*!< DWT FUNCTION: EMITRANGE Position */ -#define DWT_FUNCTION_EMITRANGE_Msk (0x1UL << DWT_FUNCTION_EMITRANGE_Pos) /*!< DWT FUNCTION: EMITRANGE Mask */ +#define DWT_FUNCTION_CYCMATCH_Pos 7 /*!< DWT FUNCTION: CYCMATCH Position */ +#define DWT_FUNCTION_CYCMATCH_Msk (0x1UL << DWT_FUNCTION_CYCMATCH_Pos) /*!< DWT FUNCTION: CYCMATCH Mask */ -#define DWT_FUNCTION_FUNCTION_Pos 0 /*!< DWT FUNCTION: FUNCTION Position */ -#define DWT_FUNCTION_FUNCTION_Msk (0xFUL << DWT_FUNCTION_FUNCTION_Pos) /*!< DWT FUNCTION: FUNCTION Mask */ +#define DWT_FUNCTION_EMITRANGE_Pos 5 /*!< DWT FUNCTION: EMITRANGE Position */ +#define DWT_FUNCTION_EMITRANGE_Msk (0x1UL << DWT_FUNCTION_EMITRANGE_Pos) /*!< DWT FUNCTION: EMITRANGE Mask */ -/*@}*/ /* end of group CMSIS_DWT */ +#define DWT_FUNCTION_FUNCTION_Pos 0 /*!< DWT FUNCTION: FUNCTION Position */ +#define DWT_FUNCTION_FUNCTION_Msk (0xFUL << DWT_FUNCTION_FUNCTION_Pos) /*!< DWT FUNCTION: FUNCTION Mask */ + /*@}*/ /* end of group CMSIS_DWT */ -/** \ingroup CMSIS_core_register + /** \ingroup CMSIS_core_register \defgroup CMSIS_TPI Trace Port Interface (TPI) \brief Type definitions for the Trace Port Interface (TPI) @{ */ -/** \brief Structure type to access the Trace Port Interface Register (TPI). + /** \brief Structure type to access the Trace Port Interface Register (TPI). */ -typedef struct -{ - __IO uint32_t SSPSR; /*!< Offset: 0x000 (R/ ) Supported Parallel Port Size Register */ - __IO uint32_t CSPSR; /*!< Offset: 0x004 (R/W) Current Parallel Port Size Register */ - uint32_t RESERVED0[2]; - __IO uint32_t ACPR; /*!< Offset: 0x010 (R/W) Asynchronous Clock Prescaler Register */ - uint32_t RESERVED1[55]; - __IO uint32_t SPPR; /*!< Offset: 0x0F0 (R/W) Selected Pin Protocol Register */ - uint32_t RESERVED2[131]; - __I uint32_t FFSR; /*!< Offset: 0x300 (R/ ) Formatter and Flush Status Register */ - __IO uint32_t FFCR; /*!< Offset: 0x304 (R/W) Formatter and Flush Control Register */ - __I uint32_t FSCR; /*!< Offset: 0x308 (R/ ) Formatter Synchronization Counter Register */ - uint32_t RESERVED3[759]; - __I uint32_t TRIGGER; /*!< Offset: 0xEE8 (R/ ) TRIGGER */ - __I uint32_t FIFO0; /*!< Offset: 0xEEC (R/ ) Integration ETM Data */ - __I uint32_t ITATBCTR2; /*!< Offset: 0xEF0 (R/ ) ITATBCTR2 */ - uint32_t RESERVED4[1]; - __I uint32_t ITATBCTR0; /*!< Offset: 0xEF8 (R/ ) ITATBCTR0 */ - __I uint32_t FIFO1; /*!< Offset: 0xEFC (R/ ) Integration ITM Data */ - __IO uint32_t ITCTRL; /*!< Offset: 0xF00 (R/W) Integration Mode Control */ - uint32_t RESERVED5[39]; - __IO uint32_t CLAIMSET; /*!< Offset: 0xFA0 (R/W) Claim tag set */ - __IO uint32_t CLAIMCLR; /*!< Offset: 0xFA4 (R/W) Claim tag clear */ - uint32_t RESERVED7[8]; - __I uint32_t DEVID; /*!< Offset: 0xFC8 (R/ ) TPIU_DEVID */ - __I uint32_t DEVTYPE; /*!< Offset: 0xFCC (R/ ) TPIU_DEVTYPE */ -} TPI_Type; + typedef struct + { + __IO uint32_t SSPSR; /*!< Offset: 0x000 (R/ ) Supported Parallel Port Size Register */ + __IO uint32_t CSPSR; /*!< Offset: 0x004 (R/W) Current Parallel Port Size Register */ + uint32_t RESERVED0[2]; + __IO uint32_t ACPR; /*!< Offset: 0x010 (R/W) Asynchronous Clock Prescaler Register */ + uint32_t RESERVED1[55]; + __IO uint32_t SPPR; /*!< Offset: 0x0F0 (R/W) Selected Pin Protocol Register */ + uint32_t RESERVED2[131]; + __I uint32_t FFSR; /*!< Offset: 0x300 (R/ ) Formatter and Flush Status Register */ + __IO uint32_t FFCR; /*!< Offset: 0x304 (R/W) Formatter and Flush Control Register */ + __I uint32_t FSCR; /*!< Offset: 0x308 (R/ ) Formatter Synchronization Counter Register */ + uint32_t RESERVED3[759]; + __I uint32_t TRIGGER; /*!< Offset: 0xEE8 (R/ ) TRIGGER */ + __I uint32_t FIFO0; /*!< Offset: 0xEEC (R/ ) Integration ETM Data */ + __I uint32_t ITATBCTR2; /*!< Offset: 0xEF0 (R/ ) ITATBCTR2 */ + uint32_t RESERVED4[1]; + __I uint32_t ITATBCTR0; /*!< Offset: 0xEF8 (R/ ) ITATBCTR0 */ + __I uint32_t FIFO1; /*!< Offset: 0xEFC (R/ ) Integration ITM Data */ + __IO uint32_t ITCTRL; /*!< Offset: 0xF00 (R/W) Integration Mode Control */ + uint32_t RESERVED5[39]; + __IO uint32_t CLAIMSET; /*!< Offset: 0xFA0 (R/W) Claim tag set */ + __IO uint32_t CLAIMCLR; /*!< Offset: 0xFA4 (R/W) Claim tag clear */ + uint32_t RESERVED7[8]; + __I uint32_t DEVID; /*!< Offset: 0xFC8 (R/ ) TPIU_DEVID */ + __I uint32_t DEVTYPE; /*!< Offset: 0xFCC (R/ ) TPIU_DEVTYPE */ + } TPI_Type; /* TPI Asynchronous Clock Prescaler Register Definitions */ -#define TPI_ACPR_PRESCALER_Pos 0 /*!< TPI ACPR: PRESCALER Position */ -#define TPI_ACPR_PRESCALER_Msk (0x1FFFUL << TPI_ACPR_PRESCALER_Pos) /*!< TPI ACPR: PRESCALER Mask */ +#define TPI_ACPR_PRESCALER_Pos 0 /*!< TPI ACPR: PRESCALER Position */ +#define TPI_ACPR_PRESCALER_Msk (0x1FFFUL << TPI_ACPR_PRESCALER_Pos) /*!< TPI ACPR: PRESCALER Mask */ /* TPI Selected Pin Protocol Register Definitions */ -#define TPI_SPPR_TXMODE_Pos 0 /*!< TPI SPPR: TXMODE Position */ -#define TPI_SPPR_TXMODE_Msk (0x3UL << TPI_SPPR_TXMODE_Pos) /*!< TPI SPPR: TXMODE Mask */ +#define TPI_SPPR_TXMODE_Pos 0 /*!< TPI SPPR: TXMODE Position */ +#define TPI_SPPR_TXMODE_Msk (0x3UL << TPI_SPPR_TXMODE_Pos) /*!< TPI SPPR: TXMODE Mask */ /* TPI Formatter and Flush Status Register Definitions */ -#define TPI_FFSR_FtNonStop_Pos 3 /*!< TPI FFSR: FtNonStop Position */ -#define TPI_FFSR_FtNonStop_Msk (0x1UL << TPI_FFSR_FtNonStop_Pos) /*!< TPI FFSR: FtNonStop Mask */ +#define TPI_FFSR_FtNonStop_Pos 3 /*!< TPI FFSR: FtNonStop Position */ +#define TPI_FFSR_FtNonStop_Msk (0x1UL << TPI_FFSR_FtNonStop_Pos) /*!< TPI FFSR: FtNonStop Mask */ -#define TPI_FFSR_TCPresent_Pos 2 /*!< TPI FFSR: TCPresent Position */ -#define TPI_FFSR_TCPresent_Msk (0x1UL << TPI_FFSR_TCPresent_Pos) /*!< TPI FFSR: TCPresent Mask */ +#define TPI_FFSR_TCPresent_Pos 2 /*!< TPI FFSR: TCPresent Position */ +#define TPI_FFSR_TCPresent_Msk (0x1UL << TPI_FFSR_TCPresent_Pos) /*!< TPI FFSR: TCPresent Mask */ -#define TPI_FFSR_FtStopped_Pos 1 /*!< TPI FFSR: FtStopped Position */ -#define TPI_FFSR_FtStopped_Msk (0x1UL << TPI_FFSR_FtStopped_Pos) /*!< TPI FFSR: FtStopped Mask */ +#define TPI_FFSR_FtStopped_Pos 1 /*!< TPI FFSR: FtStopped Position */ +#define TPI_FFSR_FtStopped_Msk (0x1UL << TPI_FFSR_FtStopped_Pos) /*!< TPI FFSR: FtStopped Mask */ -#define TPI_FFSR_FlInProg_Pos 0 /*!< TPI FFSR: FlInProg Position */ -#define TPI_FFSR_FlInProg_Msk (0x1UL << TPI_FFSR_FlInProg_Pos) /*!< TPI FFSR: FlInProg Mask */ +#define TPI_FFSR_FlInProg_Pos 0 /*!< TPI FFSR: FlInProg Position */ +#define TPI_FFSR_FlInProg_Msk (0x1UL << TPI_FFSR_FlInProg_Pos) /*!< TPI FFSR: FlInProg Mask */ /* TPI Formatter and Flush Control Register Definitions */ -#define TPI_FFCR_TrigIn_Pos 8 /*!< TPI FFCR: TrigIn Position */ -#define TPI_FFCR_TrigIn_Msk (0x1UL << TPI_FFCR_TrigIn_Pos) /*!< TPI FFCR: TrigIn Mask */ +#define TPI_FFCR_TrigIn_Pos 8 /*!< TPI FFCR: TrigIn Position */ +#define TPI_FFCR_TrigIn_Msk (0x1UL << TPI_FFCR_TrigIn_Pos) /*!< TPI FFCR: TrigIn Mask */ -#define TPI_FFCR_EnFCont_Pos 1 /*!< TPI FFCR: EnFCont Position */ -#define TPI_FFCR_EnFCont_Msk (0x1UL << TPI_FFCR_EnFCont_Pos) /*!< TPI FFCR: EnFCont Mask */ +#define TPI_FFCR_EnFCont_Pos 1 /*!< TPI FFCR: EnFCont Position */ +#define TPI_FFCR_EnFCont_Msk (0x1UL << TPI_FFCR_EnFCont_Pos) /*!< TPI FFCR: EnFCont Mask */ /* TPI TRIGGER Register Definitions */ -#define TPI_TRIGGER_TRIGGER_Pos 0 /*!< TPI TRIGGER: TRIGGER Position */ -#define TPI_TRIGGER_TRIGGER_Msk (0x1UL << TPI_TRIGGER_TRIGGER_Pos) /*!< TPI TRIGGER: TRIGGER Mask */ +#define TPI_TRIGGER_TRIGGER_Pos 0 /*!< TPI TRIGGER: TRIGGER Position */ +#define TPI_TRIGGER_TRIGGER_Msk (0x1UL << TPI_TRIGGER_TRIGGER_Pos) /*!< TPI TRIGGER: TRIGGER Mask */ /* TPI Integration ETM Data Register Definitions (FIFO0) */ -#define TPI_FIFO0_ITM_ATVALID_Pos 29 /*!< TPI FIFO0: ITM_ATVALID Position */ -#define TPI_FIFO0_ITM_ATVALID_Msk (0x3UL << TPI_FIFO0_ITM_ATVALID_Pos) /*!< TPI FIFO0: ITM_ATVALID Mask */ +#define TPI_FIFO0_ITM_ATVALID_Pos 29 /*!< TPI FIFO0: ITM_ATVALID Position */ +#define TPI_FIFO0_ITM_ATVALID_Msk (0x3UL << TPI_FIFO0_ITM_ATVALID_Pos) /*!< TPI FIFO0: ITM_ATVALID Mask */ -#define TPI_FIFO0_ITM_bytecount_Pos 27 /*!< TPI FIFO0: ITM_bytecount Position */ -#define TPI_FIFO0_ITM_bytecount_Msk (0x3UL << TPI_FIFO0_ITM_bytecount_Pos) /*!< TPI FIFO0: ITM_bytecount Mask */ +#define TPI_FIFO0_ITM_bytecount_Pos 27 /*!< TPI FIFO0: ITM_bytecount Position */ +#define TPI_FIFO0_ITM_bytecount_Msk (0x3UL << TPI_FIFO0_ITM_bytecount_Pos) /*!< TPI FIFO0: ITM_bytecount Mask */ -#define TPI_FIFO0_ETM_ATVALID_Pos 26 /*!< TPI FIFO0: ETM_ATVALID Position */ -#define TPI_FIFO0_ETM_ATVALID_Msk (0x3UL << TPI_FIFO0_ETM_ATVALID_Pos) /*!< TPI FIFO0: ETM_ATVALID Mask */ +#define TPI_FIFO0_ETM_ATVALID_Pos 26 /*!< TPI FIFO0: ETM_ATVALID Position */ +#define TPI_FIFO0_ETM_ATVALID_Msk (0x3UL << TPI_FIFO0_ETM_ATVALID_Pos) /*!< TPI FIFO0: ETM_ATVALID Mask */ -#define TPI_FIFO0_ETM_bytecount_Pos 24 /*!< TPI FIFO0: ETM_bytecount Position */ -#define TPI_FIFO0_ETM_bytecount_Msk (0x3UL << TPI_FIFO0_ETM_bytecount_Pos) /*!< TPI FIFO0: ETM_bytecount Mask */ +#define TPI_FIFO0_ETM_bytecount_Pos 24 /*!< TPI FIFO0: ETM_bytecount Position */ +#define TPI_FIFO0_ETM_bytecount_Msk (0x3UL << TPI_FIFO0_ETM_bytecount_Pos) /*!< TPI FIFO0: ETM_bytecount Mask */ -#define TPI_FIFO0_ETM2_Pos 16 /*!< TPI FIFO0: ETM2 Position */ -#define TPI_FIFO0_ETM2_Msk (0xFFUL << TPI_FIFO0_ETM2_Pos) /*!< TPI FIFO0: ETM2 Mask */ +#define TPI_FIFO0_ETM2_Pos 16 /*!< TPI FIFO0: ETM2 Position */ +#define TPI_FIFO0_ETM2_Msk (0xFFUL << TPI_FIFO0_ETM2_Pos) /*!< TPI FIFO0: ETM2 Mask */ -#define TPI_FIFO0_ETM1_Pos 8 /*!< TPI FIFO0: ETM1 Position */ -#define TPI_FIFO0_ETM1_Msk (0xFFUL << TPI_FIFO0_ETM1_Pos) /*!< TPI FIFO0: ETM1 Mask */ +#define TPI_FIFO0_ETM1_Pos 8 /*!< TPI FIFO0: ETM1 Position */ +#define TPI_FIFO0_ETM1_Msk (0xFFUL << TPI_FIFO0_ETM1_Pos) /*!< TPI FIFO0: ETM1 Mask */ -#define TPI_FIFO0_ETM0_Pos 0 /*!< TPI FIFO0: ETM0 Position */ -#define TPI_FIFO0_ETM0_Msk (0xFFUL << TPI_FIFO0_ETM0_Pos) /*!< TPI FIFO0: ETM0 Mask */ +#define TPI_FIFO0_ETM0_Pos 0 /*!< TPI FIFO0: ETM0 Position */ +#define TPI_FIFO0_ETM0_Msk (0xFFUL << TPI_FIFO0_ETM0_Pos) /*!< TPI FIFO0: ETM0 Mask */ /* TPI ITATBCTR2 Register Definitions */ -#define TPI_ITATBCTR2_ATREADY_Pos 0 /*!< TPI ITATBCTR2: ATREADY Position */ -#define TPI_ITATBCTR2_ATREADY_Msk (0x1UL << TPI_ITATBCTR2_ATREADY_Pos) /*!< TPI ITATBCTR2: ATREADY Mask */ +#define TPI_ITATBCTR2_ATREADY_Pos 0 /*!< TPI ITATBCTR2: ATREADY Position */ +#define TPI_ITATBCTR2_ATREADY_Msk (0x1UL << TPI_ITATBCTR2_ATREADY_Pos) /*!< TPI ITATBCTR2: ATREADY Mask */ /* TPI Integration ITM Data Register Definitions (FIFO1) */ -#define TPI_FIFO1_ITM_ATVALID_Pos 29 /*!< TPI FIFO1: ITM_ATVALID Position */ -#define TPI_FIFO1_ITM_ATVALID_Msk (0x3UL << TPI_FIFO1_ITM_ATVALID_Pos) /*!< TPI FIFO1: ITM_ATVALID Mask */ +#define TPI_FIFO1_ITM_ATVALID_Pos 29 /*!< TPI FIFO1: ITM_ATVALID Position */ +#define TPI_FIFO1_ITM_ATVALID_Msk (0x3UL << TPI_FIFO1_ITM_ATVALID_Pos) /*!< TPI FIFO1: ITM_ATVALID Mask */ -#define TPI_FIFO1_ITM_bytecount_Pos 27 /*!< TPI FIFO1: ITM_bytecount Position */ -#define TPI_FIFO1_ITM_bytecount_Msk (0x3UL << TPI_FIFO1_ITM_bytecount_Pos) /*!< TPI FIFO1: ITM_bytecount Mask */ +#define TPI_FIFO1_ITM_bytecount_Pos 27 /*!< TPI FIFO1: ITM_bytecount Position */ +#define TPI_FIFO1_ITM_bytecount_Msk (0x3UL << TPI_FIFO1_ITM_bytecount_Pos) /*!< TPI FIFO1: ITM_bytecount Mask */ -#define TPI_FIFO1_ETM_ATVALID_Pos 26 /*!< TPI FIFO1: ETM_ATVALID Position */ -#define TPI_FIFO1_ETM_ATVALID_Msk (0x3UL << TPI_FIFO1_ETM_ATVALID_Pos) /*!< TPI FIFO1: ETM_ATVALID Mask */ +#define TPI_FIFO1_ETM_ATVALID_Pos 26 /*!< TPI FIFO1: ETM_ATVALID Position */ +#define TPI_FIFO1_ETM_ATVALID_Msk (0x3UL << TPI_FIFO1_ETM_ATVALID_Pos) /*!< TPI FIFO1: ETM_ATVALID Mask */ -#define TPI_FIFO1_ETM_bytecount_Pos 24 /*!< TPI FIFO1: ETM_bytecount Position */ -#define TPI_FIFO1_ETM_bytecount_Msk (0x3UL << TPI_FIFO1_ETM_bytecount_Pos) /*!< TPI FIFO1: ETM_bytecount Mask */ +#define TPI_FIFO1_ETM_bytecount_Pos 24 /*!< TPI FIFO1: ETM_bytecount Position */ +#define TPI_FIFO1_ETM_bytecount_Msk (0x3UL << TPI_FIFO1_ETM_bytecount_Pos) /*!< TPI FIFO1: ETM_bytecount Mask */ -#define TPI_FIFO1_ITM2_Pos 16 /*!< TPI FIFO1: ITM2 Position */ -#define TPI_FIFO1_ITM2_Msk (0xFFUL << TPI_FIFO1_ITM2_Pos) /*!< TPI FIFO1: ITM2 Mask */ +#define TPI_FIFO1_ITM2_Pos 16 /*!< TPI FIFO1: ITM2 Position */ +#define TPI_FIFO1_ITM2_Msk (0xFFUL << TPI_FIFO1_ITM2_Pos) /*!< TPI FIFO1: ITM2 Mask */ -#define TPI_FIFO1_ITM1_Pos 8 /*!< TPI FIFO1: ITM1 Position */ -#define TPI_FIFO1_ITM1_Msk (0xFFUL << TPI_FIFO1_ITM1_Pos) /*!< TPI FIFO1: ITM1 Mask */ +#define TPI_FIFO1_ITM1_Pos 8 /*!< TPI FIFO1: ITM1 Position */ +#define TPI_FIFO1_ITM1_Msk (0xFFUL << TPI_FIFO1_ITM1_Pos) /*!< TPI FIFO1: ITM1 Mask */ -#define TPI_FIFO1_ITM0_Pos 0 /*!< TPI FIFO1: ITM0 Position */ -#define TPI_FIFO1_ITM0_Msk (0xFFUL << TPI_FIFO1_ITM0_Pos) /*!< TPI FIFO1: ITM0 Mask */ +#define TPI_FIFO1_ITM0_Pos 0 /*!< TPI FIFO1: ITM0 Position */ +#define TPI_FIFO1_ITM0_Msk (0xFFUL << TPI_FIFO1_ITM0_Pos) /*!< TPI FIFO1: ITM0 Mask */ /* TPI ITATBCTR0 Register Definitions */ -#define TPI_ITATBCTR0_ATREADY_Pos 0 /*!< TPI ITATBCTR0: ATREADY Position */ -#define TPI_ITATBCTR0_ATREADY_Msk (0x1UL << TPI_ITATBCTR0_ATREADY_Pos) /*!< TPI ITATBCTR0: ATREADY Mask */ +#define TPI_ITATBCTR0_ATREADY_Pos 0 /*!< TPI ITATBCTR0: ATREADY Position */ +#define TPI_ITATBCTR0_ATREADY_Msk (0x1UL << TPI_ITATBCTR0_ATREADY_Pos) /*!< TPI ITATBCTR0: ATREADY Mask */ /* TPI Integration Mode Control Register Definitions */ -#define TPI_ITCTRL_Mode_Pos 0 /*!< TPI ITCTRL: Mode Position */ -#define TPI_ITCTRL_Mode_Msk (0x1UL << TPI_ITCTRL_Mode_Pos) /*!< TPI ITCTRL: Mode Mask */ +#define TPI_ITCTRL_Mode_Pos 0 /*!< TPI ITCTRL: Mode Position */ +#define TPI_ITCTRL_Mode_Msk (0x1UL << TPI_ITCTRL_Mode_Pos) /*!< TPI ITCTRL: Mode Mask */ /* TPI DEVID Register Definitions */ -#define TPI_DEVID_NRZVALID_Pos 11 /*!< TPI DEVID: NRZVALID Position */ -#define TPI_DEVID_NRZVALID_Msk (0x1UL << TPI_DEVID_NRZVALID_Pos) /*!< TPI DEVID: NRZVALID Mask */ +#define TPI_DEVID_NRZVALID_Pos 11 /*!< TPI DEVID: NRZVALID Position */ +#define TPI_DEVID_NRZVALID_Msk (0x1UL << TPI_DEVID_NRZVALID_Pos) /*!< TPI DEVID: NRZVALID Mask */ -#define TPI_DEVID_MANCVALID_Pos 10 /*!< TPI DEVID: MANCVALID Position */ -#define TPI_DEVID_MANCVALID_Msk (0x1UL << TPI_DEVID_MANCVALID_Pos) /*!< TPI DEVID: MANCVALID Mask */ +#define TPI_DEVID_MANCVALID_Pos 10 /*!< TPI DEVID: MANCVALID Position */ +#define TPI_DEVID_MANCVALID_Msk (0x1UL << TPI_DEVID_MANCVALID_Pos) /*!< TPI DEVID: MANCVALID Mask */ -#define TPI_DEVID_PTINVALID_Pos 9 /*!< TPI DEVID: PTINVALID Position */ -#define TPI_DEVID_PTINVALID_Msk (0x1UL << TPI_DEVID_PTINVALID_Pos) /*!< TPI DEVID: PTINVALID Mask */ +#define TPI_DEVID_PTINVALID_Pos 9 /*!< TPI DEVID: PTINVALID Position */ +#define TPI_DEVID_PTINVALID_Msk (0x1UL << TPI_DEVID_PTINVALID_Pos) /*!< TPI DEVID: PTINVALID Mask */ -#define TPI_DEVID_MinBufSz_Pos 6 /*!< TPI DEVID: MinBufSz Position */ -#define TPI_DEVID_MinBufSz_Msk (0x7UL << TPI_DEVID_MinBufSz_Pos) /*!< TPI DEVID: MinBufSz Mask */ +#define TPI_DEVID_MinBufSz_Pos 6 /*!< TPI DEVID: MinBufSz Position */ +#define TPI_DEVID_MinBufSz_Msk (0x7UL << TPI_DEVID_MinBufSz_Pos) /*!< TPI DEVID: MinBufSz Mask */ -#define TPI_DEVID_AsynClkIn_Pos 5 /*!< TPI DEVID: AsynClkIn Position */ -#define TPI_DEVID_AsynClkIn_Msk (0x1UL << TPI_DEVID_AsynClkIn_Pos) /*!< TPI DEVID: AsynClkIn Mask */ +#define TPI_DEVID_AsynClkIn_Pos 5 /*!< TPI DEVID: AsynClkIn Position */ +#define TPI_DEVID_AsynClkIn_Msk (0x1UL << TPI_DEVID_AsynClkIn_Pos) /*!< TPI DEVID: AsynClkIn Mask */ -#define TPI_DEVID_NrTraceInput_Pos 0 /*!< TPI DEVID: NrTraceInput Position */ -#define TPI_DEVID_NrTraceInput_Msk (0x1FUL << TPI_DEVID_NrTraceInput_Pos) /*!< TPI DEVID: NrTraceInput Mask */ +#define TPI_DEVID_NrTraceInput_Pos 0 /*!< TPI DEVID: NrTraceInput Position */ +#define TPI_DEVID_NrTraceInput_Msk (0x1FUL << TPI_DEVID_NrTraceInput_Pos) /*!< TPI DEVID: NrTraceInput Mask */ /* TPI DEVTYPE Register Definitions */ -#define TPI_DEVTYPE_SubType_Pos 0 /*!< TPI DEVTYPE: SubType Position */ -#define TPI_DEVTYPE_SubType_Msk (0xFUL << TPI_DEVTYPE_SubType_Pos) /*!< TPI DEVTYPE: SubType Mask */ - -#define TPI_DEVTYPE_MajorType_Pos 4 /*!< TPI DEVTYPE: MajorType Position */ -#define TPI_DEVTYPE_MajorType_Msk (0xFUL << TPI_DEVTYPE_MajorType_Pos) /*!< TPI DEVTYPE: MajorType Mask */ +#define TPI_DEVTYPE_SubType_Pos 0 /*!< TPI DEVTYPE: SubType Position */ +#define TPI_DEVTYPE_SubType_Msk (0xFUL << TPI_DEVTYPE_SubType_Pos) /*!< TPI DEVTYPE: SubType Mask */ -/*@}*/ /* end of group CMSIS_TPI */ +#define TPI_DEVTYPE_MajorType_Pos 4 /*!< TPI DEVTYPE: MajorType Position */ +#define TPI_DEVTYPE_MajorType_Msk (0xFUL << TPI_DEVTYPE_MajorType_Pos) /*!< TPI DEVTYPE: MajorType Mask */ + /*@}*/ /* end of group CMSIS_TPI */ #if (__MPU_PRESENT == 1) -/** \ingroup CMSIS_core_register + /** \ingroup CMSIS_core_register \defgroup CMSIS_MPU Memory Protection Unit (MPU) \brief Type definitions for the Memory Protection Unit (MPU) @{ */ -/** \brief Structure type to access the Memory Protection Unit (MPU). + /** \brief Structure type to access the Memory Protection Unit (MPU). */ -typedef struct -{ - __I uint32_t TYPE; /*!< Offset: 0x000 (R/ ) MPU Type Register */ - __IO uint32_t CTRL; /*!< Offset: 0x004 (R/W) MPU Control Register */ - __IO uint32_t RNR; /*!< Offset: 0x008 (R/W) MPU Region RNRber Register */ - __IO uint32_t RBAR; /*!< Offset: 0x00C (R/W) MPU Region Base Address Register */ - __IO uint32_t RASR; /*!< Offset: 0x010 (R/W) MPU Region Attribute and Size Register */ - __IO uint32_t RBAR_A1; /*!< Offset: 0x014 (R/W) MPU Alias 1 Region Base Address Register */ - __IO uint32_t RASR_A1; /*!< Offset: 0x018 (R/W) MPU Alias 1 Region Attribute and Size Register */ - __IO uint32_t RBAR_A2; /*!< Offset: 0x01C (R/W) MPU Alias 2 Region Base Address Register */ - __IO uint32_t RASR_A2; /*!< Offset: 0x020 (R/W) MPU Alias 2 Region Attribute and Size Register */ - __IO uint32_t RBAR_A3; /*!< Offset: 0x024 (R/W) MPU Alias 3 Region Base Address Register */ - __IO uint32_t RASR_A3; /*!< Offset: 0x028 (R/W) MPU Alias 3 Region Attribute and Size Register */ -} MPU_Type; + typedef struct + { + __I uint32_t TYPE; /*!< Offset: 0x000 (R/ ) MPU Type Register */ + __IO uint32_t CTRL; /*!< Offset: 0x004 (R/W) MPU Control Register */ + __IO uint32_t RNR; /*!< Offset: 0x008 (R/W) MPU Region RNRber Register */ + __IO uint32_t RBAR; /*!< Offset: 0x00C (R/W) MPU Region Base Address Register */ + __IO uint32_t RASR; /*!< Offset: 0x010 (R/W) MPU Region Attribute and Size Register */ + __IO uint32_t RBAR_A1; /*!< Offset: 0x014 (R/W) MPU Alias 1 Region Base Address Register */ + __IO uint32_t RASR_A1; /*!< Offset: 0x018 (R/W) MPU Alias 1 Region Attribute and Size Register */ + __IO uint32_t RBAR_A2; /*!< Offset: 0x01C (R/W) MPU Alias 2 Region Base Address Register */ + __IO uint32_t RASR_A2; /*!< Offset: 0x020 (R/W) MPU Alias 2 Region Attribute and Size Register */ + __IO uint32_t RBAR_A3; /*!< Offset: 0x024 (R/W) MPU Alias 3 Region Base Address Register */ + __IO uint32_t RASR_A3; /*!< Offset: 0x028 (R/W) MPU Alias 3 Region Attribute and Size Register */ + } MPU_Type; /* MPU Type Register */ -#define MPU_TYPE_IREGION_Pos 16 /*!< MPU TYPE: IREGION Position */ -#define MPU_TYPE_IREGION_Msk (0xFFUL << MPU_TYPE_IREGION_Pos) /*!< MPU TYPE: IREGION Mask */ +#define MPU_TYPE_IREGION_Pos 16 /*!< MPU TYPE: IREGION Position */ +#define MPU_TYPE_IREGION_Msk (0xFFUL << MPU_TYPE_IREGION_Pos) /*!< MPU TYPE: IREGION Mask */ -#define MPU_TYPE_DREGION_Pos 8 /*!< MPU TYPE: DREGION Position */ -#define MPU_TYPE_DREGION_Msk (0xFFUL << MPU_TYPE_DREGION_Pos) /*!< MPU TYPE: DREGION Mask */ +#define MPU_TYPE_DREGION_Pos 8 /*!< MPU TYPE: DREGION Position */ +#define MPU_TYPE_DREGION_Msk (0xFFUL << MPU_TYPE_DREGION_Pos) /*!< MPU TYPE: DREGION Mask */ -#define MPU_TYPE_SEPARATE_Pos 0 /*!< MPU TYPE: SEPARATE Position */ -#define MPU_TYPE_SEPARATE_Msk (1UL << MPU_TYPE_SEPARATE_Pos) /*!< MPU TYPE: SEPARATE Mask */ +#define MPU_TYPE_SEPARATE_Pos 0 /*!< MPU TYPE: SEPARATE Position */ +#define MPU_TYPE_SEPARATE_Msk (1UL << MPU_TYPE_SEPARATE_Pos) /*!< MPU TYPE: SEPARATE Mask */ /* MPU Control Register */ -#define MPU_CTRL_PRIVDEFENA_Pos 2 /*!< MPU CTRL: PRIVDEFENA Position */ -#define MPU_CTRL_PRIVDEFENA_Msk (1UL << MPU_CTRL_PRIVDEFENA_Pos) /*!< MPU CTRL: PRIVDEFENA Mask */ +#define MPU_CTRL_PRIVDEFENA_Pos 2 /*!< MPU CTRL: PRIVDEFENA Position */ +#define MPU_CTRL_PRIVDEFENA_Msk (1UL << MPU_CTRL_PRIVDEFENA_Pos) /*!< MPU CTRL: PRIVDEFENA Mask */ -#define MPU_CTRL_HFNMIENA_Pos 1 /*!< MPU CTRL: HFNMIENA Position */ -#define MPU_CTRL_HFNMIENA_Msk (1UL << MPU_CTRL_HFNMIENA_Pos) /*!< MPU CTRL: HFNMIENA Mask */ +#define MPU_CTRL_HFNMIENA_Pos 1 /*!< MPU CTRL: HFNMIENA Position */ +#define MPU_CTRL_HFNMIENA_Msk (1UL << MPU_CTRL_HFNMIENA_Pos) /*!< MPU CTRL: HFNMIENA Mask */ -#define MPU_CTRL_ENABLE_Pos 0 /*!< MPU CTRL: ENABLE Position */ -#define MPU_CTRL_ENABLE_Msk (1UL << MPU_CTRL_ENABLE_Pos) /*!< MPU CTRL: ENABLE Mask */ +#define MPU_CTRL_ENABLE_Pos 0 /*!< MPU CTRL: ENABLE Position */ +#define MPU_CTRL_ENABLE_Msk (1UL << MPU_CTRL_ENABLE_Pos) /*!< MPU CTRL: ENABLE Mask */ /* MPU Region Number Register */ -#define MPU_RNR_REGION_Pos 0 /*!< MPU RNR: REGION Position */ -#define MPU_RNR_REGION_Msk (0xFFUL << MPU_RNR_REGION_Pos) /*!< MPU RNR: REGION Mask */ +#define MPU_RNR_REGION_Pos 0 /*!< MPU RNR: REGION Position */ +#define MPU_RNR_REGION_Msk (0xFFUL << MPU_RNR_REGION_Pos) /*!< MPU RNR: REGION Mask */ /* MPU Region Base Address Register */ -#define MPU_RBAR_ADDR_Pos 5 /*!< MPU RBAR: ADDR Position */ -#define MPU_RBAR_ADDR_Msk (0x7FFFFFFUL << MPU_RBAR_ADDR_Pos) /*!< MPU RBAR: ADDR Mask */ +#define MPU_RBAR_ADDR_Pos 5 /*!< MPU RBAR: ADDR Position */ +#define MPU_RBAR_ADDR_Msk (0x7FFFFFFUL << MPU_RBAR_ADDR_Pos) /*!< MPU RBAR: ADDR Mask */ -#define MPU_RBAR_VALID_Pos 4 /*!< MPU RBAR: VALID Position */ -#define MPU_RBAR_VALID_Msk (1UL << MPU_RBAR_VALID_Pos) /*!< MPU RBAR: VALID Mask */ +#define MPU_RBAR_VALID_Pos 4 /*!< MPU RBAR: VALID Position */ +#define MPU_RBAR_VALID_Msk (1UL << MPU_RBAR_VALID_Pos) /*!< MPU RBAR: VALID Mask */ -#define MPU_RBAR_REGION_Pos 0 /*!< MPU RBAR: REGION Position */ -#define MPU_RBAR_REGION_Msk (0xFUL << MPU_RBAR_REGION_Pos) /*!< MPU RBAR: REGION Mask */ +#define MPU_RBAR_REGION_Pos 0 /*!< MPU RBAR: REGION Position */ +#define MPU_RBAR_REGION_Msk (0xFUL << MPU_RBAR_REGION_Pos) /*!< MPU RBAR: REGION Mask */ /* MPU Region Attribute and Size Register */ -#define MPU_RASR_ATTRS_Pos 16 /*!< MPU RASR: MPU Region Attribute field Position */ -#define MPU_RASR_ATTRS_Msk (0xFFFFUL << MPU_RASR_ATTRS_Pos) /*!< MPU RASR: MPU Region Attribute field Mask */ +#define MPU_RASR_ATTRS_Pos 16 /*!< MPU RASR: MPU Region Attribute field Position */ +#define MPU_RASR_ATTRS_Msk (0xFFFFUL << MPU_RASR_ATTRS_Pos) /*!< MPU RASR: MPU Region Attribute field Mask */ -#define MPU_RASR_XN_Pos 28 /*!< MPU RASR: ATTRS.XN Position */ -#define MPU_RASR_XN_Msk (1UL << MPU_RASR_XN_Pos) /*!< MPU RASR: ATTRS.XN Mask */ +#define MPU_RASR_XN_Pos 28 /*!< MPU RASR: ATTRS.XN Position */ +#define MPU_RASR_XN_Msk (1UL << MPU_RASR_XN_Pos) /*!< MPU RASR: ATTRS.XN Mask */ -#define MPU_RASR_AP_Pos 24 /*!< MPU RASR: ATTRS.AP Position */ -#define MPU_RASR_AP_Msk (0x7UL << MPU_RASR_AP_Pos) /*!< MPU RASR: ATTRS.AP Mask */ +#define MPU_RASR_AP_Pos 24 /*!< MPU RASR: ATTRS.AP Position */ +#define MPU_RASR_AP_Msk (0x7UL << MPU_RASR_AP_Pos) /*!< MPU RASR: ATTRS.AP Mask */ -#define MPU_RASR_TEX_Pos 19 /*!< MPU RASR: ATTRS.TEX Position */ -#define MPU_RASR_TEX_Msk (0x7UL << MPU_RASR_TEX_Pos) /*!< MPU RASR: ATTRS.TEX Mask */ +#define MPU_RASR_TEX_Pos 19 /*!< MPU RASR: ATTRS.TEX Position */ +#define MPU_RASR_TEX_Msk (0x7UL << MPU_RASR_TEX_Pos) /*!< MPU RASR: ATTRS.TEX Mask */ -#define MPU_RASR_S_Pos 18 /*!< MPU RASR: ATTRS.S Position */ -#define MPU_RASR_S_Msk (1UL << MPU_RASR_S_Pos) /*!< MPU RASR: ATTRS.S Mask */ +#define MPU_RASR_S_Pos 18 /*!< MPU RASR: ATTRS.S Position */ +#define MPU_RASR_S_Msk (1UL << MPU_RASR_S_Pos) /*!< MPU RASR: ATTRS.S Mask */ -#define MPU_RASR_C_Pos 17 /*!< MPU RASR: ATTRS.C Position */ -#define MPU_RASR_C_Msk (1UL << MPU_RASR_C_Pos) /*!< MPU RASR: ATTRS.C Mask */ +#define MPU_RASR_C_Pos 17 /*!< MPU RASR: ATTRS.C Position */ +#define MPU_RASR_C_Msk (1UL << MPU_RASR_C_Pos) /*!< MPU RASR: ATTRS.C Mask */ -#define MPU_RASR_B_Pos 16 /*!< MPU RASR: ATTRS.B Position */ -#define MPU_RASR_B_Msk (1UL << MPU_RASR_B_Pos) /*!< MPU RASR: ATTRS.B Mask */ +#define MPU_RASR_B_Pos 16 /*!< MPU RASR: ATTRS.B Position */ +#define MPU_RASR_B_Msk (1UL << MPU_RASR_B_Pos) /*!< MPU RASR: ATTRS.B Mask */ -#define MPU_RASR_SRD_Pos 8 /*!< MPU RASR: Sub-Region Disable Position */ -#define MPU_RASR_SRD_Msk (0xFFUL << MPU_RASR_SRD_Pos) /*!< MPU RASR: Sub-Region Disable Mask */ +#define MPU_RASR_SRD_Pos 8 /*!< MPU RASR: Sub-Region Disable Position */ +#define MPU_RASR_SRD_Msk (0xFFUL << MPU_RASR_SRD_Pos) /*!< MPU RASR: Sub-Region Disable Mask */ -#define MPU_RASR_SIZE_Pos 1 /*!< MPU RASR: Region Size Field Position */ -#define MPU_RASR_SIZE_Msk (0x1FUL << MPU_RASR_SIZE_Pos) /*!< MPU RASR: Region Size Field Mask */ +#define MPU_RASR_SIZE_Pos 1 /*!< MPU RASR: Region Size Field Position */ +#define MPU_RASR_SIZE_Msk (0x1FUL << MPU_RASR_SIZE_Pos) /*!< MPU RASR: Region Size Field Mask */ -#define MPU_RASR_ENABLE_Pos 0 /*!< MPU RASR: Region enable bit Position */ -#define MPU_RASR_ENABLE_Msk (1UL << MPU_RASR_ENABLE_Pos) /*!< MPU RASR: Region enable bit Disable Mask */ +#define MPU_RASR_ENABLE_Pos 0 /*!< MPU RASR: Region enable bit Position */ +#define MPU_RASR_ENABLE_Msk (1UL << MPU_RASR_ENABLE_Pos) /*!< MPU RASR: Region enable bit Disable Mask */ /*@} end of group CMSIS_MPU */ #endif - -/** \ingroup CMSIS_core_register + /** \ingroup CMSIS_core_register \defgroup CMSIS_CoreDebug Core Debug Registers (CoreDebug) \brief Type definitions for the Core Debug Registers @{ */ -/** \brief Structure type to access the Core Debug Register (CoreDebug). + /** \brief Structure type to access the Core Debug Register (CoreDebug). */ -typedef struct -{ - __IO uint32_t DHCSR; /*!< Offset: 0x000 (R/W) Debug Halting Control and Status Register */ - __O uint32_t DCRSR; /*!< Offset: 0x004 ( /W) Debug Core Register Selector Register */ - __IO uint32_t DCRDR; /*!< Offset: 0x008 (R/W) Debug Core Register Data Register */ - __IO uint32_t DEMCR; /*!< Offset: 0x00C (R/W) Debug Exception and Monitor Control Register */ -} CoreDebug_Type; + typedef struct + { + __IO uint32_t DHCSR; /*!< Offset: 0x000 (R/W) Debug Halting Control and Status Register */ + __O uint32_t DCRSR; /*!< Offset: 0x004 ( /W) Debug Core Register Selector Register */ + __IO uint32_t DCRDR; /*!< Offset: 0x008 (R/W) Debug Core Register Data Register */ + __IO uint32_t DEMCR; /*!< Offset: 0x00C (R/W) Debug Exception and Monitor Control Register */ + } CoreDebug_Type; /* Debug Halting Control and Status Register */ -#define CoreDebug_DHCSR_DBGKEY_Pos 16 /*!< CoreDebug DHCSR: DBGKEY Position */ -#define CoreDebug_DHCSR_DBGKEY_Msk (0xFFFFUL << CoreDebug_DHCSR_DBGKEY_Pos) /*!< CoreDebug DHCSR: DBGKEY Mask */ +#define CoreDebug_DHCSR_DBGKEY_Pos 16 /*!< CoreDebug DHCSR: DBGKEY Position */ +#define CoreDebug_DHCSR_DBGKEY_Msk (0xFFFFUL << CoreDebug_DHCSR_DBGKEY_Pos) /*!< CoreDebug DHCSR: DBGKEY Mask */ -#define CoreDebug_DHCSR_S_RESET_ST_Pos 25 /*!< CoreDebug DHCSR: S_RESET_ST Position */ -#define CoreDebug_DHCSR_S_RESET_ST_Msk (1UL << CoreDebug_DHCSR_S_RESET_ST_Pos) /*!< CoreDebug DHCSR: S_RESET_ST Mask */ +#define CoreDebug_DHCSR_S_RESET_ST_Pos 25 /*!< CoreDebug DHCSR: S_RESET_ST Position */ +#define CoreDebug_DHCSR_S_RESET_ST_Msk (1UL << CoreDebug_DHCSR_S_RESET_ST_Pos) /*!< CoreDebug DHCSR: S_RESET_ST Mask */ -#define CoreDebug_DHCSR_S_RETIRE_ST_Pos 24 /*!< CoreDebug DHCSR: S_RETIRE_ST Position */ -#define CoreDebug_DHCSR_S_RETIRE_ST_Msk (1UL << CoreDebug_DHCSR_S_RETIRE_ST_Pos) /*!< CoreDebug DHCSR: S_RETIRE_ST Mask */ +#define CoreDebug_DHCSR_S_RETIRE_ST_Pos 24 /*!< CoreDebug DHCSR: S_RETIRE_ST Position */ +#define CoreDebug_DHCSR_S_RETIRE_ST_Msk (1UL << CoreDebug_DHCSR_S_RETIRE_ST_Pos) /*!< CoreDebug DHCSR: S_RETIRE_ST Mask */ -#define CoreDebug_DHCSR_S_LOCKUP_Pos 19 /*!< CoreDebug DHCSR: S_LOCKUP Position */ -#define CoreDebug_DHCSR_S_LOCKUP_Msk (1UL << CoreDebug_DHCSR_S_LOCKUP_Pos) /*!< CoreDebug DHCSR: S_LOCKUP Mask */ +#define CoreDebug_DHCSR_S_LOCKUP_Pos 19 /*!< CoreDebug DHCSR: S_LOCKUP Position */ +#define CoreDebug_DHCSR_S_LOCKUP_Msk (1UL << CoreDebug_DHCSR_S_LOCKUP_Pos) /*!< CoreDebug DHCSR: S_LOCKUP Mask */ -#define CoreDebug_DHCSR_S_SLEEP_Pos 18 /*!< CoreDebug DHCSR: S_SLEEP Position */ -#define CoreDebug_DHCSR_S_SLEEP_Msk (1UL << CoreDebug_DHCSR_S_SLEEP_Pos) /*!< CoreDebug DHCSR: S_SLEEP Mask */ +#define CoreDebug_DHCSR_S_SLEEP_Pos 18 /*!< CoreDebug DHCSR: S_SLEEP Position */ +#define CoreDebug_DHCSR_S_SLEEP_Msk (1UL << CoreDebug_DHCSR_S_SLEEP_Pos) /*!< CoreDebug DHCSR: S_SLEEP Mask */ -#define CoreDebug_DHCSR_S_HALT_Pos 17 /*!< CoreDebug DHCSR: S_HALT Position */ -#define CoreDebug_DHCSR_S_HALT_Msk (1UL << CoreDebug_DHCSR_S_HALT_Pos) /*!< CoreDebug DHCSR: S_HALT Mask */ +#define CoreDebug_DHCSR_S_HALT_Pos 17 /*!< CoreDebug DHCSR: S_HALT Position */ +#define CoreDebug_DHCSR_S_HALT_Msk (1UL << CoreDebug_DHCSR_S_HALT_Pos) /*!< CoreDebug DHCSR: S_HALT Mask */ -#define CoreDebug_DHCSR_S_REGRDY_Pos 16 /*!< CoreDebug DHCSR: S_REGRDY Position */ -#define CoreDebug_DHCSR_S_REGRDY_Msk (1UL << CoreDebug_DHCSR_S_REGRDY_Pos) /*!< CoreDebug DHCSR: S_REGRDY Mask */ +#define CoreDebug_DHCSR_S_REGRDY_Pos 16 /*!< CoreDebug DHCSR: S_REGRDY Position */ +#define CoreDebug_DHCSR_S_REGRDY_Msk (1UL << CoreDebug_DHCSR_S_REGRDY_Pos) /*!< CoreDebug DHCSR: S_REGRDY Mask */ -#define CoreDebug_DHCSR_C_SNAPSTALL_Pos 5 /*!< CoreDebug DHCSR: C_SNAPSTALL Position */ -#define CoreDebug_DHCSR_C_SNAPSTALL_Msk (1UL << CoreDebug_DHCSR_C_SNAPSTALL_Pos) /*!< CoreDebug DHCSR: C_SNAPSTALL Mask */ +#define CoreDebug_DHCSR_C_SNAPSTALL_Pos 5 /*!< CoreDebug DHCSR: C_SNAPSTALL Position */ +#define CoreDebug_DHCSR_C_SNAPSTALL_Msk (1UL << CoreDebug_DHCSR_C_SNAPSTALL_Pos) /*!< CoreDebug DHCSR: C_SNAPSTALL Mask */ -#define CoreDebug_DHCSR_C_MASKINTS_Pos 3 /*!< CoreDebug DHCSR: C_MASKINTS Position */ -#define CoreDebug_DHCSR_C_MASKINTS_Msk (1UL << CoreDebug_DHCSR_C_MASKINTS_Pos) /*!< CoreDebug DHCSR: C_MASKINTS Mask */ +#define CoreDebug_DHCSR_C_MASKINTS_Pos 3 /*!< CoreDebug DHCSR: C_MASKINTS Position */ +#define CoreDebug_DHCSR_C_MASKINTS_Msk (1UL << CoreDebug_DHCSR_C_MASKINTS_Pos) /*!< CoreDebug DHCSR: C_MASKINTS Mask */ -#define CoreDebug_DHCSR_C_STEP_Pos 2 /*!< CoreDebug DHCSR: C_STEP Position */ -#define CoreDebug_DHCSR_C_STEP_Msk (1UL << CoreDebug_DHCSR_C_STEP_Pos) /*!< CoreDebug DHCSR: C_STEP Mask */ +#define CoreDebug_DHCSR_C_STEP_Pos 2 /*!< CoreDebug DHCSR: C_STEP Position */ +#define CoreDebug_DHCSR_C_STEP_Msk (1UL << CoreDebug_DHCSR_C_STEP_Pos) /*!< CoreDebug DHCSR: C_STEP Mask */ -#define CoreDebug_DHCSR_C_HALT_Pos 1 /*!< CoreDebug DHCSR: C_HALT Position */ -#define CoreDebug_DHCSR_C_HALT_Msk (1UL << CoreDebug_DHCSR_C_HALT_Pos) /*!< CoreDebug DHCSR: C_HALT Mask */ +#define CoreDebug_DHCSR_C_HALT_Pos 1 /*!< CoreDebug DHCSR: C_HALT Position */ +#define CoreDebug_DHCSR_C_HALT_Msk (1UL << CoreDebug_DHCSR_C_HALT_Pos) /*!< CoreDebug DHCSR: C_HALT Mask */ -#define CoreDebug_DHCSR_C_DEBUGEN_Pos 0 /*!< CoreDebug DHCSR: C_DEBUGEN Position */ -#define CoreDebug_DHCSR_C_DEBUGEN_Msk (1UL << CoreDebug_DHCSR_C_DEBUGEN_Pos) /*!< CoreDebug DHCSR: C_DEBUGEN Mask */ +#define CoreDebug_DHCSR_C_DEBUGEN_Pos 0 /*!< CoreDebug DHCSR: C_DEBUGEN Position */ +#define CoreDebug_DHCSR_C_DEBUGEN_Msk (1UL << CoreDebug_DHCSR_C_DEBUGEN_Pos) /*!< CoreDebug DHCSR: C_DEBUGEN Mask */ /* Debug Core Register Selector Register */ -#define CoreDebug_DCRSR_REGWnR_Pos 16 /*!< CoreDebug DCRSR: REGWnR Position */ -#define CoreDebug_DCRSR_REGWnR_Msk (1UL << CoreDebug_DCRSR_REGWnR_Pos) /*!< CoreDebug DCRSR: REGWnR Mask */ +#define CoreDebug_DCRSR_REGWnR_Pos 16 /*!< CoreDebug DCRSR: REGWnR Position */ +#define CoreDebug_DCRSR_REGWnR_Msk (1UL << CoreDebug_DCRSR_REGWnR_Pos) /*!< CoreDebug DCRSR: REGWnR Mask */ -#define CoreDebug_DCRSR_REGSEL_Pos 0 /*!< CoreDebug DCRSR: REGSEL Position */ -#define CoreDebug_DCRSR_REGSEL_Msk (0x1FUL << CoreDebug_DCRSR_REGSEL_Pos) /*!< CoreDebug DCRSR: REGSEL Mask */ +#define CoreDebug_DCRSR_REGSEL_Pos 0 /*!< CoreDebug DCRSR: REGSEL Position */ +#define CoreDebug_DCRSR_REGSEL_Msk (0x1FUL << CoreDebug_DCRSR_REGSEL_Pos) /*!< CoreDebug DCRSR: REGSEL Mask */ /* Debug Exception and Monitor Control Register */ -#define CoreDebug_DEMCR_TRCENA_Pos 24 /*!< CoreDebug DEMCR: TRCENA Position */ -#define CoreDebug_DEMCR_TRCENA_Msk (1UL << CoreDebug_DEMCR_TRCENA_Pos) /*!< CoreDebug DEMCR: TRCENA Mask */ +#define CoreDebug_DEMCR_TRCENA_Pos 24 /*!< CoreDebug DEMCR: TRCENA Position */ +#define CoreDebug_DEMCR_TRCENA_Msk (1UL << CoreDebug_DEMCR_TRCENA_Pos) /*!< CoreDebug DEMCR: TRCENA Mask */ -#define CoreDebug_DEMCR_MON_REQ_Pos 19 /*!< CoreDebug DEMCR: MON_REQ Position */ -#define CoreDebug_DEMCR_MON_REQ_Msk (1UL << CoreDebug_DEMCR_MON_REQ_Pos) /*!< CoreDebug DEMCR: MON_REQ Mask */ +#define CoreDebug_DEMCR_MON_REQ_Pos 19 /*!< CoreDebug DEMCR: MON_REQ Position */ +#define CoreDebug_DEMCR_MON_REQ_Msk (1UL << CoreDebug_DEMCR_MON_REQ_Pos) /*!< CoreDebug DEMCR: MON_REQ Mask */ -#define CoreDebug_DEMCR_MON_STEP_Pos 18 /*!< CoreDebug DEMCR: MON_STEP Position */ -#define CoreDebug_DEMCR_MON_STEP_Msk (1UL << CoreDebug_DEMCR_MON_STEP_Pos) /*!< CoreDebug DEMCR: MON_STEP Mask */ +#define CoreDebug_DEMCR_MON_STEP_Pos 18 /*!< CoreDebug DEMCR: MON_STEP Position */ +#define CoreDebug_DEMCR_MON_STEP_Msk (1UL << CoreDebug_DEMCR_MON_STEP_Pos) /*!< CoreDebug DEMCR: MON_STEP Mask */ -#define CoreDebug_DEMCR_MON_PEND_Pos 17 /*!< CoreDebug DEMCR: MON_PEND Position */ -#define CoreDebug_DEMCR_MON_PEND_Msk (1UL << CoreDebug_DEMCR_MON_PEND_Pos) /*!< CoreDebug DEMCR: MON_PEND Mask */ +#define CoreDebug_DEMCR_MON_PEND_Pos 17 /*!< CoreDebug DEMCR: MON_PEND Position */ +#define CoreDebug_DEMCR_MON_PEND_Msk (1UL << CoreDebug_DEMCR_MON_PEND_Pos) /*!< CoreDebug DEMCR: MON_PEND Mask */ -#define CoreDebug_DEMCR_MON_EN_Pos 16 /*!< CoreDebug DEMCR: MON_EN Position */ -#define CoreDebug_DEMCR_MON_EN_Msk (1UL << CoreDebug_DEMCR_MON_EN_Pos) /*!< CoreDebug DEMCR: MON_EN Mask */ +#define CoreDebug_DEMCR_MON_EN_Pos 16 /*!< CoreDebug DEMCR: MON_EN Position */ +#define CoreDebug_DEMCR_MON_EN_Msk (1UL << CoreDebug_DEMCR_MON_EN_Pos) /*!< CoreDebug DEMCR: MON_EN Mask */ -#define CoreDebug_DEMCR_VC_HARDERR_Pos 10 /*!< CoreDebug DEMCR: VC_HARDERR Position */ -#define CoreDebug_DEMCR_VC_HARDERR_Msk (1UL << CoreDebug_DEMCR_VC_HARDERR_Pos) /*!< CoreDebug DEMCR: VC_HARDERR Mask */ +#define CoreDebug_DEMCR_VC_HARDERR_Pos 10 /*!< CoreDebug DEMCR: VC_HARDERR Position */ +#define CoreDebug_DEMCR_VC_HARDERR_Msk (1UL << CoreDebug_DEMCR_VC_HARDERR_Pos) /*!< CoreDebug DEMCR: VC_HARDERR Mask */ -#define CoreDebug_DEMCR_VC_INTERR_Pos 9 /*!< CoreDebug DEMCR: VC_INTERR Position */ -#define CoreDebug_DEMCR_VC_INTERR_Msk (1UL << CoreDebug_DEMCR_VC_INTERR_Pos) /*!< CoreDebug DEMCR: VC_INTERR Mask */ +#define CoreDebug_DEMCR_VC_INTERR_Pos 9 /*!< CoreDebug DEMCR: VC_INTERR Position */ +#define CoreDebug_DEMCR_VC_INTERR_Msk (1UL << CoreDebug_DEMCR_VC_INTERR_Pos) /*!< CoreDebug DEMCR: VC_INTERR Mask */ -#define CoreDebug_DEMCR_VC_BUSERR_Pos 8 /*!< CoreDebug DEMCR: VC_BUSERR Position */ -#define CoreDebug_DEMCR_VC_BUSERR_Msk (1UL << CoreDebug_DEMCR_VC_BUSERR_Pos) /*!< CoreDebug DEMCR: VC_BUSERR Mask */ +#define CoreDebug_DEMCR_VC_BUSERR_Pos 8 /*!< CoreDebug DEMCR: VC_BUSERR Position */ +#define CoreDebug_DEMCR_VC_BUSERR_Msk (1UL << CoreDebug_DEMCR_VC_BUSERR_Pos) /*!< CoreDebug DEMCR: VC_BUSERR Mask */ -#define CoreDebug_DEMCR_VC_STATERR_Pos 7 /*!< CoreDebug DEMCR: VC_STATERR Position */ -#define CoreDebug_DEMCR_VC_STATERR_Msk (1UL << CoreDebug_DEMCR_VC_STATERR_Pos) /*!< CoreDebug DEMCR: VC_STATERR Mask */ +#define CoreDebug_DEMCR_VC_STATERR_Pos 7 /*!< CoreDebug DEMCR: VC_STATERR Position */ +#define CoreDebug_DEMCR_VC_STATERR_Msk (1UL << CoreDebug_DEMCR_VC_STATERR_Pos) /*!< CoreDebug DEMCR: VC_STATERR Mask */ -#define CoreDebug_DEMCR_VC_CHKERR_Pos 6 /*!< CoreDebug DEMCR: VC_CHKERR Position */ -#define CoreDebug_DEMCR_VC_CHKERR_Msk (1UL << CoreDebug_DEMCR_VC_CHKERR_Pos) /*!< CoreDebug DEMCR: VC_CHKERR Mask */ +#define CoreDebug_DEMCR_VC_CHKERR_Pos 6 /*!< CoreDebug DEMCR: VC_CHKERR Position */ +#define CoreDebug_DEMCR_VC_CHKERR_Msk (1UL << CoreDebug_DEMCR_VC_CHKERR_Pos) /*!< CoreDebug DEMCR: VC_CHKERR Mask */ -#define CoreDebug_DEMCR_VC_NOCPERR_Pos 5 /*!< CoreDebug DEMCR: VC_NOCPERR Position */ -#define CoreDebug_DEMCR_VC_NOCPERR_Msk (1UL << CoreDebug_DEMCR_VC_NOCPERR_Pos) /*!< CoreDebug DEMCR: VC_NOCPERR Mask */ +#define CoreDebug_DEMCR_VC_NOCPERR_Pos 5 /*!< CoreDebug DEMCR: VC_NOCPERR Position */ +#define CoreDebug_DEMCR_VC_NOCPERR_Msk (1UL << CoreDebug_DEMCR_VC_NOCPERR_Pos) /*!< CoreDebug DEMCR: VC_NOCPERR Mask */ -#define CoreDebug_DEMCR_VC_MMERR_Pos 4 /*!< CoreDebug DEMCR: VC_MMERR Position */ -#define CoreDebug_DEMCR_VC_MMERR_Msk (1UL << CoreDebug_DEMCR_VC_MMERR_Pos) /*!< CoreDebug DEMCR: VC_MMERR Mask */ +#define CoreDebug_DEMCR_VC_MMERR_Pos 4 /*!< CoreDebug DEMCR: VC_MMERR Position */ +#define CoreDebug_DEMCR_VC_MMERR_Msk (1UL << CoreDebug_DEMCR_VC_MMERR_Pos) /*!< CoreDebug DEMCR: VC_MMERR Mask */ -#define CoreDebug_DEMCR_VC_CORERESET_Pos 0 /*!< CoreDebug DEMCR: VC_CORERESET Position */ -#define CoreDebug_DEMCR_VC_CORERESET_Msk (1UL << CoreDebug_DEMCR_VC_CORERESET_Pos) /*!< CoreDebug DEMCR: VC_CORERESET Mask */ +#define CoreDebug_DEMCR_VC_CORERESET_Pos 0 /*!< CoreDebug DEMCR: VC_CORERESET Position */ +#define CoreDebug_DEMCR_VC_CORERESET_Msk (1UL << CoreDebug_DEMCR_VC_CORERESET_Pos) /*!< CoreDebug DEMCR: VC_CORERESET Mask */ /*@} end of group CMSIS_CoreDebug */ - /** \ingroup CMSIS_core_register \defgroup CMSIS_core_base Core Definitions \brief Definitions for base addresses, unions, and structures. @@ -1251,34 +1235,32 @@ typedef struct */ /* Memory mapping of Cortex-M3 Hardware */ -#define SCS_BASE (0xE000E000UL) /*!< System Control Space Base Address */ -#define ITM_BASE (0xE0000000UL) /*!< ITM Base Address */ -#define DWT_BASE (0xE0001000UL) /*!< DWT Base Address */ -#define TPI_BASE (0xE0040000UL) /*!< TPI Base Address */ -#define CoreDebug_BASE (0xE000EDF0UL) /*!< Core Debug Base Address */ -#define SysTick_BASE (SCS_BASE + 0x0010UL) /*!< SysTick Base Address */ -#define NVIC_BASE (SCS_BASE + 0x0100UL) /*!< NVIC Base Address */ -#define SCB_BASE (SCS_BASE + 0x0D00UL) /*!< System Control Block Base Address */ - -#define SCnSCB ((SCnSCB_Type *) SCS_BASE ) /*!< System control Register not in SCB */ -#define SCB ((SCB_Type *) SCB_BASE ) /*!< SCB configuration struct */ -#define SysTick ((SysTick_Type *) SysTick_BASE ) /*!< SysTick configuration struct */ -#define NVIC ((NVIC_Type *) NVIC_BASE ) /*!< NVIC configuration struct */ -#define ITM ((ITM_Type *) ITM_BASE ) /*!< ITM configuration struct */ -#define DWT ((DWT_Type *) DWT_BASE ) /*!< DWT configuration struct */ -#define TPI ((TPI_Type *) TPI_BASE ) /*!< TPI configuration struct */ -#define CoreDebug ((CoreDebug_Type *) CoreDebug_BASE) /*!< Core Debug configuration struct */ +#define SCS_BASE (0xE000E000UL) /*!< System Control Space Base Address */ +#define ITM_BASE (0xE0000000UL) /*!< ITM Base Address */ +#define DWT_BASE (0xE0001000UL) /*!< DWT Base Address */ +#define TPI_BASE (0xE0040000UL) /*!< TPI Base Address */ +#define CoreDebug_BASE (0xE000EDF0UL) /*!< Core Debug Base Address */ +#define SysTick_BASE (SCS_BASE + 0x0010UL) /*!< SysTick Base Address */ +#define NVIC_BASE (SCS_BASE + 0x0100UL) /*!< NVIC Base Address */ +#define SCB_BASE (SCS_BASE + 0x0D00UL) /*!< System Control Block Base Address */ + +#define SCnSCB ((SCnSCB_Type *)SCS_BASE) /*!< System control Register not in SCB */ +#define SCB ((SCB_Type *)SCB_BASE) /*!< SCB configuration struct */ +#define SysTick ((SysTick_Type *)SysTick_BASE) /*!< SysTick configuration struct */ +#define NVIC ((NVIC_Type *)NVIC_BASE) /*!< NVIC configuration struct */ +#define ITM ((ITM_Type *)ITM_BASE) /*!< ITM configuration struct */ +#define DWT ((DWT_Type *)DWT_BASE) /*!< DWT configuration struct */ +#define TPI ((TPI_Type *)TPI_BASE) /*!< TPI configuration struct */ +#define CoreDebug ((CoreDebug_Type *)CoreDebug_BASE) /*!< Core Debug configuration struct */ #if (__MPU_PRESENT == 1) - #define MPU_BASE (SCS_BASE + 0x0D90UL) /*!< Memory Protection Unit */ - #define MPU ((MPU_Type *) MPU_BASE ) /*!< Memory Protection Unit */ +#define MPU_BASE (SCS_BASE + 0x0D90UL) /*!< Memory Protection Unit */ +#define MPU ((MPU_Type *)MPU_BASE) /*!< Memory Protection Unit */ #endif -/*@} */ + /*@} */ - - -/******************************************************************************* + /******************************************************************************* * Hardware Abstraction Layer Core Function Interface contains: - Core NVIC Functions @@ -1286,19 +1268,17 @@ typedef struct - Core Debug Functions - Core Register Access Functions ******************************************************************************/ -/** \defgroup CMSIS_Core_FunctionInterface Functions and Instructions Reference + /** \defgroup CMSIS_Core_FunctionInterface Functions and Instructions Reference */ - - -/* ########################## NVIC functions #################################### */ -/** \ingroup CMSIS_Core_FunctionInterface + /* ########################## NVIC functions #################################### */ + /** \ingroup CMSIS_Core_FunctionInterface \defgroup CMSIS_Core_NVICFunctions NVIC Functions \brief Functions that manage interrupts and exceptions via the NVIC. @{ */ -/** \brief Set Priority Grouping + /** \brief Set Priority Grouping The function sets the priority grouping field using the required unlock sequence. The parameter PriorityGroup is assigned to the field SCB->AIRCR [10:8] PRIGROUP field. @@ -1308,57 +1288,53 @@ typedef struct \param [in] PriorityGroup Priority grouping field. */ -__STATIC_INLINE void NVIC_SetPriorityGrouping(uint32_t PriorityGroup) -{ - uint32_t reg_value; - uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07); /* only values 0..7 are used */ - - reg_value = SCB->AIRCR; /* read old register configuration */ - reg_value &= ~(SCB_AIRCR_VECTKEY_Msk | SCB_AIRCR_PRIGROUP_Msk); /* clear bits to change */ - reg_value = (reg_value | - ((uint32_t)0x5FA << SCB_AIRCR_VECTKEY_Pos) | - (PriorityGroupTmp << 8)); /* Insert write key and priorty group */ - SCB->AIRCR = reg_value; -} + __STATIC_INLINE void NVIC_SetPriorityGrouping(uint32_t PriorityGroup) + { + uint32_t reg_value; + uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07); /* only values 0..7 are used */ + reg_value = SCB->AIRCR; /* read old register configuration */ + reg_value &= ~(SCB_AIRCR_VECTKEY_Msk | SCB_AIRCR_PRIGROUP_Msk); /* clear bits to change */ + reg_value = (reg_value | + ((uint32_t)0x5FA << SCB_AIRCR_VECTKEY_Pos) | + (PriorityGroupTmp << 8)); /* Insert write key and priorty group */ + SCB->AIRCR = reg_value; + } -/** \brief Get Priority Grouping + /** \brief Get Priority Grouping The function reads the priority grouping field from the NVIC Interrupt Controller. \return Priority grouping field (SCB->AIRCR [10:8] PRIGROUP field). */ -__STATIC_INLINE uint32_t NVIC_GetPriorityGrouping(void) -{ - return ((SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) >> SCB_AIRCR_PRIGROUP_Pos); /* read priority grouping field */ -} + __STATIC_INLINE uint32_t NVIC_GetPriorityGrouping(void) + { + return ((SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) >> SCB_AIRCR_PRIGROUP_Pos); /* read priority grouping field */ + } - -/** \brief Enable External Interrupt + /** \brief Enable External Interrupt The function enables a device-specific interrupt in the NVIC interrupt controller. \param [in] IRQn External interrupt number. Value cannot be negative. */ -__STATIC_INLINE void NVIC_EnableIRQ(IRQn_Type IRQn) -{ - NVIC->ISER[((uint32_t)(IRQn) >> 5)] = (1 << ((uint32_t)(IRQn) & 0x1F)); /* enable interrupt */ -} - + __STATIC_INLINE void NVIC_EnableIRQ(IRQn_Type IRQn) + { + NVIC->ISER[((uint32_t)(IRQn) >> 5)] = (1 << ((uint32_t)(IRQn)&0x1F)); /* enable interrupt */ + } -/** \brief Disable External Interrupt + /** \brief Disable External Interrupt The function disables a device-specific interrupt in the NVIC interrupt controller. \param [in] IRQn External interrupt number. Value cannot be negative. */ -__STATIC_INLINE void NVIC_DisableIRQ(IRQn_Type IRQn) -{ - NVIC->ICER[((uint32_t)(IRQn) >> 5)] = (1 << ((uint32_t)(IRQn) & 0x1F)); /* disable interrupt */ -} + __STATIC_INLINE void NVIC_DisableIRQ(IRQn_Type IRQn) + { + NVIC->ICER[((uint32_t)(IRQn) >> 5)] = (1 << ((uint32_t)(IRQn)&0x1F)); /* disable interrupt */ + } - -/** \brief Get Pending Interrupt + /** \brief Get Pending Interrupt The function reads the pending register in the NVIC and returns the pending bit for the specified interrupt. @@ -1368,37 +1344,34 @@ __STATIC_INLINE void NVIC_DisableIRQ(IRQn_Type IRQn) \return 0 Interrupt status is not pending. \return 1 Interrupt status is pending. */ -__STATIC_INLINE uint32_t NVIC_GetPendingIRQ(IRQn_Type IRQn) -{ - return((uint32_t) ((NVIC->ISPR[(uint32_t)(IRQn) >> 5] & (1 << ((uint32_t)(IRQn) & 0x1F)))?1:0)); /* Return 1 if pending else 0 */ -} - + __STATIC_INLINE uint32_t NVIC_GetPendingIRQ(IRQn_Type IRQn) + { + return ((uint32_t)((NVIC->ISPR[(uint32_t)(IRQn) >> 5] & (1 << ((uint32_t)(IRQn)&0x1F))) ? 1 : 0)); /* Return 1 if pending else 0 */ + } -/** \brief Set Pending Interrupt + /** \brief Set Pending Interrupt The function sets the pending bit of an external interrupt. \param [in] IRQn Interrupt number. Value cannot be negative. */ -__STATIC_INLINE void NVIC_SetPendingIRQ(IRQn_Type IRQn) -{ - NVIC->ISPR[((uint32_t)(IRQn) >> 5)] = (1 << ((uint32_t)(IRQn) & 0x1F)); /* set interrupt pending */ -} + __STATIC_INLINE void NVIC_SetPendingIRQ(IRQn_Type IRQn) + { + NVIC->ISPR[((uint32_t)(IRQn) >> 5)] = (1 << ((uint32_t)(IRQn)&0x1F)); /* set interrupt pending */ + } - -/** \brief Clear Pending Interrupt + /** \brief Clear Pending Interrupt The function clears the pending bit of an external interrupt. \param [in] IRQn External interrupt number. Value cannot be negative. */ -__STATIC_INLINE void NVIC_ClearPendingIRQ(IRQn_Type IRQn) -{ - NVIC->ICPR[((uint32_t)(IRQn) >> 5)] = (1 << ((uint32_t)(IRQn) & 0x1F)); /* Clear pending interrupt */ -} - + __STATIC_INLINE void NVIC_ClearPendingIRQ(IRQn_Type IRQn) + { + NVIC->ICPR[((uint32_t)(IRQn) >> 5)] = (1 << ((uint32_t)(IRQn)&0x1F)); /* Clear pending interrupt */ + } -/** \brief Get Active Interrupt + /** \brief Get Active Interrupt The function reads the active register in NVIC and returns the active bit. @@ -1407,13 +1380,12 @@ __STATIC_INLINE void NVIC_ClearPendingIRQ(IRQn_Type IRQn) \return 0 Interrupt status is not active. \return 1 Interrupt status is active. */ -__STATIC_INLINE uint32_t NVIC_GetActive(IRQn_Type IRQn) -{ - return((uint32_t)((NVIC->IABR[(uint32_t)(IRQn) >> 5] & (1 << ((uint32_t)(IRQn) & 0x1F)))?1:0)); /* Return 1 if active else 0 */ -} + __STATIC_INLINE uint32_t NVIC_GetActive(IRQn_Type IRQn) + { + return ((uint32_t)((NVIC->IABR[(uint32_t)(IRQn) >> 5] & (1 << ((uint32_t)(IRQn)&0x1F))) ? 1 : 0)); /* Return 1 if active else 0 */ + } - -/** \brief Set Interrupt Priority + /** \brief Set Interrupt Priority The function sets the priority of an interrupt. @@ -1422,16 +1394,19 @@ __STATIC_INLINE uint32_t NVIC_GetActive(IRQn_Type IRQn) \param [in] IRQn Interrupt number. \param [in] priority Priority to set. */ -__STATIC_INLINE void NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority) -{ - if(IRQn < 0) { - SCB->SHP[((uint32_t)(IRQn) & 0xF)-4] = ((priority << (8 - __NVIC_PRIO_BITS)) & 0xff); } /* set Priority for Cortex-M System Interrupts */ - else { - NVIC->IP[(uint32_t)(IRQn)] = ((priority << (8 - __NVIC_PRIO_BITS)) & 0xff); } /* set Priority for device specific Interrupts */ -} - - -/** \brief Get Interrupt Priority + __STATIC_INLINE void NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority) + { + if (IRQn < 0) + { + SCB->SHP[((uint32_t)(IRQn)&0xF) - 4] = ((priority << (8 - __NVIC_PRIO_BITS)) & 0xff); + } /* set Priority for Cortex-M System Interrupts */ + else + { + NVIC->IP[(uint32_t)(IRQn)] = ((priority << (8 - __NVIC_PRIO_BITS)) & 0xff); + } /* set Priority for device specific Interrupts */ + } + + /** \brief Get Interrupt Priority The function reads the priority of an interrupt. The interrupt number can be positive to specify an external (device specific) @@ -1442,17 +1417,20 @@ __STATIC_INLINE void NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority) \return Interrupt Priority. Value is aligned automatically to the implemented priority bits of the microcontroller. */ -__STATIC_INLINE uint32_t NVIC_GetPriority(IRQn_Type IRQn) -{ + __STATIC_INLINE uint32_t NVIC_GetPriority(IRQn_Type IRQn) + { - if(IRQn < 0) { - return((uint32_t)(SCB->SHP[((uint32_t)(IRQn) & 0xF)-4] >> (8 - __NVIC_PRIO_BITS))); } /* get priority for Cortex-M system interrupts */ - else { - return((uint32_t)(NVIC->IP[(uint32_t)(IRQn)] >> (8 - __NVIC_PRIO_BITS))); } /* get priority for device specific interrupts */ -} + if (IRQn < 0) + { + return ((uint32_t)(SCB->SHP[((uint32_t)(IRQn)&0xF) - 4] >> (8 - __NVIC_PRIO_BITS))); + } /* get priority for Cortex-M system interrupts */ + else + { + return ((uint32_t)(NVIC->IP[(uint32_t)(IRQn)] >> (8 - __NVIC_PRIO_BITS))); + } /* get priority for device specific interrupts */ + } - -/** \brief Encode Priority + /** \brief Encode Priority The function encodes the priority for an interrupt with the given priority group, preemptive priority value, and subpriority value. @@ -1464,23 +1442,21 @@ __STATIC_INLINE uint32_t NVIC_GetPriority(IRQn_Type IRQn) \param [in] SubPriority Subpriority value (starting from 0). \return Encoded priority. Value can be used in the function \ref NVIC_SetPriority(). */ -__STATIC_INLINE uint32_t NVIC_EncodePriority (uint32_t PriorityGroup, uint32_t PreemptPriority, uint32_t SubPriority) -{ - uint32_t PriorityGroupTmp = (PriorityGroup & 0x07); /* only values 0..7 are used */ - uint32_t PreemptPriorityBits; - uint32_t SubPriorityBits; + __STATIC_INLINE uint32_t NVIC_EncodePriority(uint32_t PriorityGroup, uint32_t PreemptPriority, uint32_t SubPriority) + { + uint32_t PriorityGroupTmp = (PriorityGroup & 0x07); /* only values 0..7 are used */ + uint32_t PreemptPriorityBits; + uint32_t SubPriorityBits; - PreemptPriorityBits = ((7 - PriorityGroupTmp) > __NVIC_PRIO_BITS) ? __NVIC_PRIO_BITS : 7 - PriorityGroupTmp; - SubPriorityBits = ((PriorityGroupTmp + __NVIC_PRIO_BITS) < 7) ? 0 : PriorityGroupTmp - 7 + __NVIC_PRIO_BITS; - - return ( - ((PreemptPriority & ((1 << (PreemptPriorityBits)) - 1)) << SubPriorityBits) | - ((SubPriority & ((1 << (SubPriorityBits )) - 1))) - ); -} + PreemptPriorityBits = ((7 - PriorityGroupTmp) > __NVIC_PRIO_BITS) ? __NVIC_PRIO_BITS : 7 - PriorityGroupTmp; + SubPriorityBits = ((PriorityGroupTmp + __NVIC_PRIO_BITS) < 7) ? 0 : PriorityGroupTmp - 7 + __NVIC_PRIO_BITS; + return ( + ((PreemptPriority & ((1 << (PreemptPriorityBits)) - 1)) << SubPriorityBits) | + ((SubPriority & ((1 << (SubPriorityBits)) - 1)))); + } -/** \brief Decode Priority + /** \brief Decode Priority The function decodes an interrupt priority value with a given priority group to preemptive priority value and subpriority value. @@ -1492,41 +1468,39 @@ __STATIC_INLINE uint32_t NVIC_EncodePriority (uint32_t PriorityGroup, uint32_t P \param [out] pPreemptPriority Preemptive priority value (starting from 0). \param [out] pSubPriority Subpriority value (starting from 0). */ -__STATIC_INLINE void NVIC_DecodePriority (uint32_t Priority, uint32_t PriorityGroup, uint32_t* pPreemptPriority, uint32_t* pSubPriority) -{ - uint32_t PriorityGroupTmp = (PriorityGroup & 0x07); /* only values 0..7 are used */ - uint32_t PreemptPriorityBits; - uint32_t SubPriorityBits; - - PreemptPriorityBits = ((7 - PriorityGroupTmp) > __NVIC_PRIO_BITS) ? __NVIC_PRIO_BITS : 7 - PriorityGroupTmp; - SubPriorityBits = ((PriorityGroupTmp + __NVIC_PRIO_BITS) < 7) ? 0 : PriorityGroupTmp - 7 + __NVIC_PRIO_BITS; + __STATIC_INLINE void NVIC_DecodePriority(uint32_t Priority, uint32_t PriorityGroup, uint32_t *pPreemptPriority, uint32_t *pSubPriority) + { + uint32_t PriorityGroupTmp = (PriorityGroup & 0x07); /* only values 0..7 are used */ + uint32_t PreemptPriorityBits; + uint32_t SubPriorityBits; - *pPreemptPriority = (Priority >> SubPriorityBits) & ((1 << (PreemptPriorityBits)) - 1); - *pSubPriority = (Priority ) & ((1 << (SubPriorityBits )) - 1); -} + PreemptPriorityBits = ((7 - PriorityGroupTmp) > __NVIC_PRIO_BITS) ? __NVIC_PRIO_BITS : 7 - PriorityGroupTmp; + SubPriorityBits = ((PriorityGroupTmp + __NVIC_PRIO_BITS) < 7) ? 0 : PriorityGroupTmp - 7 + __NVIC_PRIO_BITS; + *pPreemptPriority = (Priority >> SubPriorityBits) & ((1 << (PreemptPriorityBits)) - 1); + *pSubPriority = (Priority) & ((1 << (SubPriorityBits)) - 1); + } -/** \brief System Reset + /** \brief System Reset The function initiates a system reset request to reset the MCU. */ -__STATIC_INLINE void NVIC_SystemReset(void) -{ - __DSB(); /* Ensure all outstanding memory accesses included + __STATIC_INLINE void NVIC_SystemReset(void) + { + __DSB(); /* Ensure all outstanding memory accesses included buffered write are completed before reset */ - SCB->AIRCR = ((0x5FA << SCB_AIRCR_VECTKEY_Pos) | - (SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) | - SCB_AIRCR_SYSRESETREQ_Msk); /* Keep priority group unchanged */ - __DSB(); /* Ensure completion of memory access */ - while(1); /* wait until reset */ -} - -/*@} end of CMSIS_Core_NVICFunctions */ - - - -/* ################################## SysTick function ############################################ */ -/** \ingroup CMSIS_Core_FunctionInterface + SCB->AIRCR = ((0x5FA << SCB_AIRCR_VECTKEY_Pos) | + (SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) | + SCB_AIRCR_SYSRESETREQ_Msk); /* Keep priority group unchanged */ + __DSB(); /* Ensure completion of memory access */ + while (1) + ; /* wait until reset */ + } + + /*@} end of CMSIS_Core_NVICFunctions */ + + /* ################################## SysTick function ############################################ */ + /** \ingroup CMSIS_Core_FunctionInterface \defgroup CMSIS_Core_SysTickFunctions SysTick Functions \brief Functions that configure the System. @{ @@ -1534,7 +1508,7 @@ __STATIC_INLINE void NVIC_SystemReset(void) #if (__Vendor_SysTickConfig == 0) -/** \brief System Tick Configuration + /** \brief System Tick Configuration The function initializes the System Timer and its interrupt, and starts the System Tick Timer. Counter is in free running mode to generate periodic interrupts. @@ -1549,37 +1523,35 @@ __STATIC_INLINE void NVIC_SystemReset(void) must contain a vendor-specific implementation of this function. */ -__STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks) -{ - if ((ticks - 1) > SysTick_LOAD_RELOAD_Msk) return (1); /* Reload value impossible */ - - SysTick->LOAD = ticks - 1; /* set reload register */ - NVIC_SetPriority (SysTick_IRQn, (1<<__NVIC_PRIO_BITS) - 1); /* set Priority for Systick Interrupt */ - SysTick->VAL = 0; /* Load the SysTick Counter Value */ - SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk | - SysTick_CTRL_TICKINT_Msk | - SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */ - return (0); /* Function successful */ -} + __STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks) + { + if ((ticks - 1) > SysTick_LOAD_RELOAD_Msk) + return (1); /* Reload value impossible */ + + SysTick->LOAD = ticks - 1; /* set reload register */ + NVIC_SetPriority(SysTick_IRQn, (1 << __NVIC_PRIO_BITS) - 1); /* set Priority for Systick Interrupt */ + SysTick->VAL = 0; /* Load the SysTick Counter Value */ + SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk | + SysTick_CTRL_TICKINT_Msk | + SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */ + return (0); /* Function successful */ + } #endif -/*@} end of CMSIS_Core_SysTickFunctions */ + /*@} end of CMSIS_Core_SysTickFunctions */ - - -/* ##################################### Debug In/Output function ########################################### */ -/** \ingroup CMSIS_Core_FunctionInterface + /* ##################################### Debug In/Output function ########################################### */ + /** \ingroup CMSIS_Core_FunctionInterface \defgroup CMSIS_core_DebugFunctions ITM Functions \brief Functions that access the ITM debug interface. @{ */ -extern volatile int32_t ITM_RxBuffer; /*!< External variable to receive characters. */ -#define ITM_RXBUFFER_EMPTY 0x5AA55AA5 /*!< Value identifying \ref ITM_RxBuffer is ready for next character. */ + extern volatile int32_t ITM_RxBuffer; /*!< External variable to receive characters. */ +#define ITM_RXBUFFER_EMPTY 0x5AA55AA5 /*!< Value identifying \ref ITM_RxBuffer is ready for next character. */ - -/** \brief ITM Send Character + /** \brief ITM Send Character The function transmits a character via the ITM channel 0, and \li Just returns when no debugger is connected that has booked the output. @@ -1589,57 +1561,59 @@ extern volatile int32_t ITM_RxBuffer; /*!< External variable \returns Character to transmit. */ -__STATIC_INLINE uint32_t ITM_SendChar (uint32_t ch) -{ - if ((ITM->TCR & ITM_TCR_ITMENA_Msk) && /* ITM enabled */ - (ITM->TER & (1UL << 0) ) ) /* ITM Port #0 enabled */ - { - while (ITM->PORT[0].u32 == 0); - ITM->PORT[0].u8 = (uint8_t) ch; - } - return (ch); -} - - -/** \brief ITM Receive Character + __STATIC_INLINE uint32_t ITM_SendChar(uint32_t ch) + { + if ((ITM->TCR & ITM_TCR_ITMENA_Msk) && /* ITM enabled */ + (ITM->TER & (1UL << 0))) /* ITM Port #0 enabled */ + { + while (ITM->PORT[0].u32 == 0) + ; + ITM->PORT[0].u8 = (uint8_t)ch; + } + return (ch); + } + + /** \brief ITM Receive Character The function inputs a character via the external variable \ref ITM_RxBuffer. \return Received character. \return -1 No character pending. */ -__STATIC_INLINE int32_t ITM_ReceiveChar (void) { - int32_t ch = -1; /* no character available */ + __STATIC_INLINE int32_t ITM_ReceiveChar(void) + { + int32_t ch = -1; /* no character available */ - if (ITM_RxBuffer != ITM_RXBUFFER_EMPTY) { - ch = ITM_RxBuffer; - ITM_RxBuffer = ITM_RXBUFFER_EMPTY; /* ready for next character */ - } + if (ITM_RxBuffer != ITM_RXBUFFER_EMPTY) + { + ch = ITM_RxBuffer; + ITM_RxBuffer = ITM_RXBUFFER_EMPTY; /* ready for next character */ + } - return (ch); -} + return (ch); + } - -/** \brief ITM Check Character + /** \brief ITM Check Character The function checks whether a character is pending for reading in the variable \ref ITM_RxBuffer. \return 0 No character available. \return 1 Character available. */ -__STATIC_INLINE int32_t ITM_CheckChar (void) { - - if (ITM_RxBuffer == ITM_RXBUFFER_EMPTY) { - return (0); /* no character available */ - } else { - return (1); /* character available */ - } -} - -/*@} end of CMSIS_core_DebugFunctions */ - - - + __STATIC_INLINE int32_t ITM_CheckChar(void) + { + + if (ITM_RxBuffer == ITM_RXBUFFER_EMPTY) + { + return (0); /* no character available */ + } + else + { + return (1); /* character available */ + } + } + + /*@} end of CMSIS_core_DebugFunctions */ #ifdef __cplusplus } diff --git a/bsp/swm320-lq100/Libraries/CMSIS/CoreSupport/core_cm4.h b/bsp/swm320-lq100/Libraries/CMSIS/CoreSupport/core_cm4.h index bb6be1305d..178cf5b3ea 100644 --- a/bsp/swm320-lq100/Libraries/CMSIS/CoreSupport/core_cm4.h +++ b/bsp/swm320-lq100/Libraries/CMSIS/CoreSupport/core_cm4.h @@ -1,4 +1,4 @@ -/**************************************************************************//** +/**************************************************************************/ /** * @file core_cm4.h * @brief CMSIS Cortex-M4 Core Peripheral Access Layer Header File * @version V4.00 @@ -34,16 +34,16 @@ POSSIBILITY OF SUCH DAMAGE. ---------------------------------------------------------------------------*/ - -#if defined ( __ICCARM__ ) - #pragma system_include /* treat file as system include file for MISRA check */ +#if defined(__ICCARM__) +#pragma system_include /* treat file as system include file for MISRA check */ #endif #ifndef __CORE_CM4_H_GENERIC #define __CORE_CM4_H_GENERIC #ifdef __cplusplus - extern "C" { +extern "C" +{ #endif /** \page CMSIS_MISRA_Exceptions MISRA-C:2004 Compliance Exceptions @@ -59,7 +59,6 @@ Function-like macros are used to allow more efficient code. */ - /******************************************************************************* * CMSIS definitions ******************************************************************************/ @@ -68,126 +67,125 @@ */ /* CMSIS CM4 definitions */ -#define __CM4_CMSIS_VERSION_MAIN (0x04) /*!< [31:16] CMSIS HAL main version */ -#define __CM4_CMSIS_VERSION_SUB (0x00) /*!< [15:0] CMSIS HAL sub version */ -#define __CM4_CMSIS_VERSION ((__CM4_CMSIS_VERSION_MAIN << 16) | \ - __CM4_CMSIS_VERSION_SUB ) /*!< CMSIS HAL version number */ - -#define __CORTEX_M (0x04) /*!< Cortex-M Core */ - +#define __CM4_CMSIS_VERSION_MAIN (0x04) /*!< [31:16] CMSIS HAL main version */ +#define __CM4_CMSIS_VERSION_SUB (0x00) /*!< [15:0] CMSIS HAL sub version */ +#define __CM4_CMSIS_VERSION ((__CM4_CMSIS_VERSION_MAIN << 16) | \ + __CM4_CMSIS_VERSION_SUB) /*!< CMSIS HAL version number */ + +#define __CORTEX_M (0x04) /*!< Cortex-M Core */ + +#if defined(__CC_ARM) +#define __ASM __asm /*!< asm keyword for ARM Compiler */ +#define __INLINE __inline /*!< inline keyword for ARM Compiler */ +#define __STATIC_INLINE static __inline + +#elif defined(__GNUC__) +#define __ASM __asm /*!< asm keyword for GNU Compiler */ +#define __INLINE inline /*!< inline keyword for GNU Compiler */ +#define __STATIC_INLINE static inline + +#elif defined(__ICCARM__) +#define __ASM __asm /*!< asm keyword for IAR Compiler */ +#define __INLINE inline /*!< inline keyword for IAR Compiler. Only available in High optimization mode! */ +#define __STATIC_INLINE static inline + +#elif defined(__TMS470__) +#define __ASM __asm /*!< asm keyword for TI CCS Compiler */ +#define __STATIC_INLINE static inline + +#elif defined(__TASKING__) +#define __ASM __asm /*!< asm keyword for TASKING Compiler */ +#define __INLINE inline /*!< inline keyword for TASKING Compiler */ +#define __STATIC_INLINE static inline + +#elif defined(__CSMC__) +#define __packed +#define __ASM _asm /*!< asm keyword for COSMIC Compiler */ +#define __INLINE inline /*use -pc99 on compile line !< inline keyword for COSMIC Compiler */ +#define __STATIC_INLINE static inline -#if defined ( __CC_ARM ) - #define __ASM __asm /*!< asm keyword for ARM Compiler */ - #define __INLINE __inline /*!< inline keyword for ARM Compiler */ - #define __STATIC_INLINE static __inline - -#elif defined ( __GNUC__ ) - #define __ASM __asm /*!< asm keyword for GNU Compiler */ - #define __INLINE inline /*!< inline keyword for GNU Compiler */ - #define __STATIC_INLINE static inline +#endif -#elif defined ( __ICCARM__ ) - #define __ASM __asm /*!< asm keyword for IAR Compiler */ - #define __INLINE inline /*!< inline keyword for IAR Compiler. Only available in High optimization mode! */ - #define __STATIC_INLINE static inline +/** __FPU_USED indicates whether an FPU is used or not. + For this, __FPU_PRESENT has to be checked prior to making use of FPU specific registers and functions. +*/ +#if defined(__CC_ARM) +#if defined __TARGET_FPU_VFP +#if (__FPU_PRESENT == 1) +#define __FPU_USED 1 +#else +#warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" +#define __FPU_USED 0 +#endif +#else +#define __FPU_USED 0 +#endif -#elif defined ( __TMS470__ ) - #define __ASM __asm /*!< asm keyword for TI CCS Compiler */ - #define __STATIC_INLINE static inline +#elif defined(__GNUC__) +#if defined(__VFP_FP__) && !defined(__SOFTFP__) +#if (__FPU_PRESENT == 1) +#define __FPU_USED 1 +#else +#warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" +#define __FPU_USED 0 +#endif +#else +#define __FPU_USED 0 +#endif -#elif defined ( __TASKING__ ) - #define __ASM __asm /*!< asm keyword for TASKING Compiler */ - #define __INLINE inline /*!< inline keyword for TASKING Compiler */ - #define __STATIC_INLINE static inline +#elif defined(__ICCARM__) +#if defined __ARMVFP__ +#if (__FPU_PRESENT == 1) +#define __FPU_USED 1 +#else +#warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" +#define __FPU_USED 0 +#endif +#else +#define __FPU_USED 0 +#endif -#elif defined ( __CSMC__ ) - #define __packed - #define __ASM _asm /*!< asm keyword for COSMIC Compiler */ - #define __INLINE inline /*use -pc99 on compile line !< inline keyword for COSMIC Compiler */ - #define __STATIC_INLINE static inline +#elif defined(__TMS470__) +#if defined __TI_VFP_SUPPORT__ +#if (__FPU_PRESENT == 1) +#define __FPU_USED 1 +#else +#warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" +#define __FPU_USED 0 +#endif +#else +#define __FPU_USED 0 +#endif +#elif defined(__TASKING__) +#if defined __FPU_VFP__ +#if (__FPU_PRESENT == 1) +#define __FPU_USED 1 +#else +#error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" +#define __FPU_USED 0 +#endif +#else +#define __FPU_USED 0 #endif -/** __FPU_USED indicates whether an FPU is used or not. - For this, __FPU_PRESENT has to be checked prior to making use of FPU specific registers and functions. -*/ -#if defined ( __CC_ARM ) - #if defined __TARGET_FPU_VFP - #if (__FPU_PRESENT == 1) - #define __FPU_USED 1 - #else - #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" - #define __FPU_USED 0 - #endif - #else - #define __FPU_USED 0 - #endif - -#elif defined ( __GNUC__ ) - #if defined (__VFP_FP__) && !defined(__SOFTFP__) - #if (__FPU_PRESENT == 1) - #define __FPU_USED 1 - #else - #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" - #define __FPU_USED 0 - #endif - #else - #define __FPU_USED 0 - #endif - -#elif defined ( __ICCARM__ ) - #if defined __ARMVFP__ - #if (__FPU_PRESENT == 1) - #define __FPU_USED 1 - #else - #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" - #define __FPU_USED 0 - #endif - #else - #define __FPU_USED 0 - #endif - -#elif defined ( __TMS470__ ) - #if defined __TI_VFP_SUPPORT__ - #if (__FPU_PRESENT == 1) - #define __FPU_USED 1 - #else - #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" - #define __FPU_USED 0 - #endif - #else - #define __FPU_USED 0 - #endif - -#elif defined ( __TASKING__ ) - #if defined __FPU_VFP__ - #if (__FPU_PRESENT == 1) - #define __FPU_USED 1 - #else - #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" - #define __FPU_USED 0 - #endif - #else - #define __FPU_USED 0 - #endif - -#elif defined ( __CSMC__ ) /* Cosmic */ - #if ( __CSMC__ & 0x400) // FPU present for parser - #if (__FPU_PRESENT == 1) - #define __FPU_USED 1 - #else - #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" - #define __FPU_USED 0 - #endif - #else - #define __FPU_USED 0 - #endif +#elif defined(__CSMC__) /* Cosmic */ +#if (__CSMC__ & 0x400) // FPU present for parser +#if (__FPU_PRESENT == 1) +#define __FPU_USED 1 +#else +#error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" +#define __FPU_USED 0 +#endif +#else +#define __FPU_USED 0 +#endif #endif -#include /* standard types definitions */ -#include /* Core Instruction Access */ -#include /* Core Function Access */ -#include /* Compiler specific SIMD Intrinsics */ +#include /* standard types definitions */ +#include /* Core Instruction Access */ +#include /* Core Function Access */ +#include /* Compiler specific SIMD Intrinsics */ #ifdef __cplusplus } @@ -201,35 +199,36 @@ #define __CORE_CM4_H_DEPENDANT #ifdef __cplusplus - extern "C" { +extern "C" +{ #endif /* check device defines and use defaults */ #if defined __CHECK_DEVICE_DEFINES - #ifndef __CM4_REV - #define __CM4_REV 0x0000 - #warning "__CM4_REV not defined in device header file; using default!" - #endif - - #ifndef __FPU_PRESENT - #define __FPU_PRESENT 0 - #warning "__FPU_PRESENT not defined in device header file; using default!" - #endif - - #ifndef __MPU_PRESENT - #define __MPU_PRESENT 0 - #warning "__MPU_PRESENT not defined in device header file; using default!" - #endif - - #ifndef __NVIC_PRIO_BITS - #define __NVIC_PRIO_BITS 4 - #warning "__NVIC_PRIO_BITS not defined in device header file; using default!" - #endif - - #ifndef __Vendor_SysTickConfig - #define __Vendor_SysTickConfig 0 - #warning "__Vendor_SysTickConfig not defined in device header file; using default!" - #endif +#ifndef __CM4_REV +#define __CM4_REV 0x0000 +#warning "__CM4_REV not defined in device header file; using default!" +#endif + +#ifndef __FPU_PRESENT +#define __FPU_PRESENT 0 +#warning "__FPU_PRESENT not defined in device header file; using default!" +#endif + +#ifndef __MPU_PRESENT +#define __MPU_PRESENT 0 +#warning "__MPU_PRESENT not defined in device header file; using default!" +#endif + +#ifndef __NVIC_PRIO_BITS +#define __NVIC_PRIO_BITS 4 +#warning "__NVIC_PRIO_BITS not defined in device header file; using default!" +#endif + +#ifndef __Vendor_SysTickConfig +#define __Vendor_SysTickConfig 0 +#warning "__Vendor_SysTickConfig not defined in device header file; using default!" +#endif #endif /* IO definitions (access restrictions to peripheral registers) */ @@ -241,18 +240,16 @@ \li for automatic generation of peripheral register debug information. */ #ifdef __cplusplus - #define __I volatile /*!< Defines 'read only' permissions */ +#define __I volatile /*!< Defines 'read only' permissions */ #else - #define __I volatile const /*!< Defines 'read only' permissions */ +#define __I volatile const /*!< Defines 'read only' permissions */ #endif -#define __O volatile /*!< Defines 'write only' permissions */ -#define __IO volatile /*!< Defines 'read / write' permissions */ - -/*@} end of group Cortex_M4 */ +#define __O volatile /*!< Defines 'write only' permissions */ +#define __IO volatile /*!< Defines 'read / write' permissions */ + /*@} end of group Cortex_M4 */ - -/******************************************************************************* + /******************************************************************************* * Register Abstraction Core Register contain: - Core Register @@ -263,1133 +260,1119 @@ - Core MPU Register - Core FPU Register ******************************************************************************/ -/** \defgroup CMSIS_core_register Defines and Type Definitions + /** \defgroup CMSIS_core_register Defines and Type Definitions \brief Type definitions and defines for Cortex-M processor based devices. */ -/** \ingroup CMSIS_core_register + /** \ingroup CMSIS_core_register \defgroup CMSIS_CORE Status and Control Registers \brief Core Register type definitions. @{ */ -/** \brief Union type to access the Application Program Status Register (APSR). + /** \brief Union type to access the Application Program Status Register (APSR). */ -typedef union -{ - struct - { + typedef union + { + struct + { #if (__CORTEX_M != 0x04) - uint32_t _reserved0:27; /*!< bit: 0..26 Reserved */ + uint32_t _reserved0 : 27; /*!< bit: 0..26 Reserved */ #else - uint32_t _reserved0:16; /*!< bit: 0..15 Reserved */ - uint32_t GE:4; /*!< bit: 16..19 Greater than or Equal flags */ - uint32_t _reserved1:7; /*!< bit: 20..26 Reserved */ + uint32_t _reserved0 : 16; /*!< bit: 0..15 Reserved */ + uint32_t GE : 4; /*!< bit: 16..19 Greater than or Equal flags */ + uint32_t _reserved1 : 7; /*!< bit: 20..26 Reserved */ #endif - uint32_t Q:1; /*!< bit: 27 Saturation condition flag */ - uint32_t V:1; /*!< bit: 28 Overflow condition code flag */ - uint32_t C:1; /*!< bit: 29 Carry condition code flag */ - uint32_t Z:1; /*!< bit: 30 Zero condition code flag */ - uint32_t N:1; /*!< bit: 31 Negative condition code flag */ - } b; /*!< Structure used for bit access */ - uint32_t w; /*!< Type used for word access */ -} APSR_Type; - - -/** \brief Union type to access the Interrupt Program Status Register (IPSR). + uint32_t Q : 1; /*!< bit: 27 Saturation condition flag */ + uint32_t V : 1; /*!< bit: 28 Overflow condition code flag */ + uint32_t C : 1; /*!< bit: 29 Carry condition code flag */ + uint32_t Z : 1; /*!< bit: 30 Zero condition code flag */ + uint32_t N : 1; /*!< bit: 31 Negative condition code flag */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ + } APSR_Type; + + /** \brief Union type to access the Interrupt Program Status Register (IPSR). */ -typedef union -{ - struct - { - uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */ - uint32_t _reserved0:23; /*!< bit: 9..31 Reserved */ - } b; /*!< Structure used for bit access */ - uint32_t w; /*!< Type used for word access */ -} IPSR_Type; - - -/** \brief Union type to access the Special-Purpose Program Status Registers (xPSR). + typedef union + { + struct + { + uint32_t ISR : 9; /*!< bit: 0.. 8 Exception number */ + uint32_t _reserved0 : 23; /*!< bit: 9..31 Reserved */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ + } IPSR_Type; + + /** \brief Union type to access the Special-Purpose Program Status Registers (xPSR). */ -typedef union -{ - struct - { - uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */ + typedef union + { + struct + { + uint32_t ISR : 9; /*!< bit: 0.. 8 Exception number */ #if (__CORTEX_M != 0x04) - uint32_t _reserved0:15; /*!< bit: 9..23 Reserved */ + uint32_t _reserved0 : 15; /*!< bit: 9..23 Reserved */ #else - uint32_t _reserved0:7; /*!< bit: 9..15 Reserved */ - uint32_t GE:4; /*!< bit: 16..19 Greater than or Equal flags */ - uint32_t _reserved1:4; /*!< bit: 20..23 Reserved */ + uint32_t _reserved0 : 7; /*!< bit: 9..15 Reserved */ + uint32_t GE : 4; /*!< bit: 16..19 Greater than or Equal flags */ + uint32_t _reserved1 : 4; /*!< bit: 20..23 Reserved */ #endif - uint32_t T:1; /*!< bit: 24 Thumb bit (read 0) */ - uint32_t IT:2; /*!< bit: 25..26 saved IT state (read 0) */ - uint32_t Q:1; /*!< bit: 27 Saturation condition flag */ - uint32_t V:1; /*!< bit: 28 Overflow condition code flag */ - uint32_t C:1; /*!< bit: 29 Carry condition code flag */ - uint32_t Z:1; /*!< bit: 30 Zero condition code flag */ - uint32_t N:1; /*!< bit: 31 Negative condition code flag */ - } b; /*!< Structure used for bit access */ - uint32_t w; /*!< Type used for word access */ -} xPSR_Type; - - -/** \brief Union type to access the Control Registers (CONTROL). + uint32_t T : 1; /*!< bit: 24 Thumb bit (read 0) */ + uint32_t IT : 2; /*!< bit: 25..26 saved IT state (read 0) */ + uint32_t Q : 1; /*!< bit: 27 Saturation condition flag */ + uint32_t V : 1; /*!< bit: 28 Overflow condition code flag */ + uint32_t C : 1; /*!< bit: 29 Carry condition code flag */ + uint32_t Z : 1; /*!< bit: 30 Zero condition code flag */ + uint32_t N : 1; /*!< bit: 31 Negative condition code flag */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ + } xPSR_Type; + + /** \brief Union type to access the Control Registers (CONTROL). */ -typedef union -{ - struct - { - uint32_t nPRIV:1; /*!< bit: 0 Execution privilege in Thread mode */ - uint32_t SPSEL:1; /*!< bit: 1 Stack to be used */ - uint32_t FPCA:1; /*!< bit: 2 FP extension active flag */ - uint32_t _reserved0:29; /*!< bit: 3..31 Reserved */ - } b; /*!< Structure used for bit access */ - uint32_t w; /*!< Type used for word access */ -} CONTROL_Type; - -/*@} end of group CMSIS_CORE */ - - -/** \ingroup CMSIS_core_register + typedef union + { + struct + { + uint32_t nPRIV : 1; /*!< bit: 0 Execution privilege in Thread mode */ + uint32_t SPSEL : 1; /*!< bit: 1 Stack to be used */ + uint32_t FPCA : 1; /*!< bit: 2 FP extension active flag */ + uint32_t _reserved0 : 29; /*!< bit: 3..31 Reserved */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ + } CONTROL_Type; + + /*@} end of group CMSIS_CORE */ + + /** \ingroup CMSIS_core_register \defgroup CMSIS_NVIC Nested Vectored Interrupt Controller (NVIC) \brief Type definitions for the NVIC Registers @{ */ -/** \brief Structure type to access the Nested Vectored Interrupt Controller (NVIC). + /** \brief Structure type to access the Nested Vectored Interrupt Controller (NVIC). */ -typedef struct -{ - __IO uint32_t ISER[8]; /*!< Offset: 0x000 (R/W) Interrupt Set Enable Register */ - uint32_t RESERVED0[24]; - __IO uint32_t ICER[8]; /*!< Offset: 0x080 (R/W) Interrupt Clear Enable Register */ - uint32_t RSERVED1[24]; - __IO uint32_t ISPR[8]; /*!< Offset: 0x100 (R/W) Interrupt Set Pending Register */ - uint32_t RESERVED2[24]; - __IO uint32_t ICPR[8]; /*!< Offset: 0x180 (R/W) Interrupt Clear Pending Register */ - uint32_t RESERVED3[24]; - __IO uint32_t IABR[8]; /*!< Offset: 0x200 (R/W) Interrupt Active bit Register */ - uint32_t RESERVED4[56]; - __IO uint8_t IP[240]; /*!< Offset: 0x300 (R/W) Interrupt Priority Register (8Bit wide) */ - uint32_t RESERVED5[644]; - __O uint32_t STIR; /*!< Offset: 0xE00 ( /W) Software Trigger Interrupt Register */ -} NVIC_Type; + typedef struct + { + __IO uint32_t ISER[8]; /*!< Offset: 0x000 (R/W) Interrupt Set Enable Register */ + uint32_t RESERVED0[24]; + __IO uint32_t ICER[8]; /*!< Offset: 0x080 (R/W) Interrupt Clear Enable Register */ + uint32_t RSERVED1[24]; + __IO uint32_t ISPR[8]; /*!< Offset: 0x100 (R/W) Interrupt Set Pending Register */ + uint32_t RESERVED2[24]; + __IO uint32_t ICPR[8]; /*!< Offset: 0x180 (R/W) Interrupt Clear Pending Register */ + uint32_t RESERVED3[24]; + __IO uint32_t IABR[8]; /*!< Offset: 0x200 (R/W) Interrupt Active bit Register */ + uint32_t RESERVED4[56]; + __IO uint8_t IP[240]; /*!< Offset: 0x300 (R/W) Interrupt Priority Register (8Bit wide) */ + uint32_t RESERVED5[644]; + __O uint32_t STIR; /*!< Offset: 0xE00 ( /W) Software Trigger Interrupt Register */ + } NVIC_Type; /* Software Triggered Interrupt Register Definitions */ -#define NVIC_STIR_INTID_Pos 0 /*!< STIR: INTLINESNUM Position */ -#define NVIC_STIR_INTID_Msk (0x1FFUL << NVIC_STIR_INTID_Pos) /*!< STIR: INTLINESNUM Mask */ - -/*@} end of group CMSIS_NVIC */ +#define NVIC_STIR_INTID_Pos 0 /*!< STIR: INTLINESNUM Position */ +#define NVIC_STIR_INTID_Msk (0x1FFUL << NVIC_STIR_INTID_Pos) /*!< STIR: INTLINESNUM Mask */ + /*@} end of group CMSIS_NVIC */ -/** \ingroup CMSIS_core_register + /** \ingroup CMSIS_core_register \defgroup CMSIS_SCB System Control Block (SCB) \brief Type definitions for the System Control Block Registers @{ */ -/** \brief Structure type to access the System Control Block (SCB). + /** \brief Structure type to access the System Control Block (SCB). */ -typedef struct -{ - __I uint32_t CPUID; /*!< Offset: 0x000 (R/ ) CPUID Base Register */ - __IO uint32_t ICSR; /*!< Offset: 0x004 (R/W) Interrupt Control and State Register */ - __IO uint32_t VTOR; /*!< Offset: 0x008 (R/W) Vector Table Offset Register */ - __IO uint32_t AIRCR; /*!< Offset: 0x00C (R/W) Application Interrupt and Reset Control Register */ - __IO uint32_t SCR; /*!< Offset: 0x010 (R/W) System Control Register */ - __IO uint32_t CCR; /*!< Offset: 0x014 (R/W) Configuration Control Register */ - __IO uint8_t SHP[12]; /*!< Offset: 0x018 (R/W) System Handlers Priority Registers (4-7, 8-11, 12-15) */ - __IO uint32_t SHCSR; /*!< Offset: 0x024 (R/W) System Handler Control and State Register */ - __IO uint32_t CFSR; /*!< Offset: 0x028 (R/W) Configurable Fault Status Register */ - __IO uint32_t HFSR; /*!< Offset: 0x02C (R/W) HardFault Status Register */ - __IO uint32_t DFSR; /*!< Offset: 0x030 (R/W) Debug Fault Status Register */ - __IO uint32_t MMFAR; /*!< Offset: 0x034 (R/W) MemManage Fault Address Register */ - __IO uint32_t BFAR; /*!< Offset: 0x038 (R/W) BusFault Address Register */ - __IO uint32_t AFSR; /*!< Offset: 0x03C (R/W) Auxiliary Fault Status Register */ - __I uint32_t PFR[2]; /*!< Offset: 0x040 (R/ ) Processor Feature Register */ - __I uint32_t DFR; /*!< Offset: 0x048 (R/ ) Debug Feature Register */ - __I uint32_t ADR; /*!< Offset: 0x04C (R/ ) Auxiliary Feature Register */ - __I uint32_t MMFR[4]; /*!< Offset: 0x050 (R/ ) Memory Model Feature Register */ - __I uint32_t ISAR[5]; /*!< Offset: 0x060 (R/ ) Instruction Set Attributes Register */ - uint32_t RESERVED0[5]; - __IO uint32_t CPACR; /*!< Offset: 0x088 (R/W) Coprocessor Access Control Register */ -} SCB_Type; + typedef struct + { + __I uint32_t CPUID; /*!< Offset: 0x000 (R/ ) CPUID Base Register */ + __IO uint32_t ICSR; /*!< Offset: 0x004 (R/W) Interrupt Control and State Register */ + __IO uint32_t VTOR; /*!< Offset: 0x008 (R/W) Vector Table Offset Register */ + __IO uint32_t AIRCR; /*!< Offset: 0x00C (R/W) Application Interrupt and Reset Control Register */ + __IO uint32_t SCR; /*!< Offset: 0x010 (R/W) System Control Register */ + __IO uint32_t CCR; /*!< Offset: 0x014 (R/W) Configuration Control Register */ + __IO uint8_t SHP[12]; /*!< Offset: 0x018 (R/W) System Handlers Priority Registers (4-7, 8-11, 12-15) */ + __IO uint32_t SHCSR; /*!< Offset: 0x024 (R/W) System Handler Control and State Register */ + __IO uint32_t CFSR; /*!< Offset: 0x028 (R/W) Configurable Fault Status Register */ + __IO uint32_t HFSR; /*!< Offset: 0x02C (R/W) HardFault Status Register */ + __IO uint32_t DFSR; /*!< Offset: 0x030 (R/W) Debug Fault Status Register */ + __IO uint32_t MMFAR; /*!< Offset: 0x034 (R/W) MemManage Fault Address Register */ + __IO uint32_t BFAR; /*!< Offset: 0x038 (R/W) BusFault Address Register */ + __IO uint32_t AFSR; /*!< Offset: 0x03C (R/W) Auxiliary Fault Status Register */ + __I uint32_t PFR[2]; /*!< Offset: 0x040 (R/ ) Processor Feature Register */ + __I uint32_t DFR; /*!< Offset: 0x048 (R/ ) Debug Feature Register */ + __I uint32_t ADR; /*!< Offset: 0x04C (R/ ) Auxiliary Feature Register */ + __I uint32_t MMFR[4]; /*!< Offset: 0x050 (R/ ) Memory Model Feature Register */ + __I uint32_t ISAR[5]; /*!< Offset: 0x060 (R/ ) Instruction Set Attributes Register */ + uint32_t RESERVED0[5]; + __IO uint32_t CPACR; /*!< Offset: 0x088 (R/W) Coprocessor Access Control Register */ + } SCB_Type; /* SCB CPUID Register Definitions */ -#define SCB_CPUID_IMPLEMENTER_Pos 24 /*!< SCB CPUID: IMPLEMENTER Position */ -#define SCB_CPUID_IMPLEMENTER_Msk (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos) /*!< SCB CPUID: IMPLEMENTER Mask */ +#define SCB_CPUID_IMPLEMENTER_Pos 24 /*!< SCB CPUID: IMPLEMENTER Position */ +#define SCB_CPUID_IMPLEMENTER_Msk (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos) /*!< SCB CPUID: IMPLEMENTER Mask */ -#define SCB_CPUID_VARIANT_Pos 20 /*!< SCB CPUID: VARIANT Position */ -#define SCB_CPUID_VARIANT_Msk (0xFUL << SCB_CPUID_VARIANT_Pos) /*!< SCB CPUID: VARIANT Mask */ +#define SCB_CPUID_VARIANT_Pos 20 /*!< SCB CPUID: VARIANT Position */ +#define SCB_CPUID_VARIANT_Msk (0xFUL << SCB_CPUID_VARIANT_Pos) /*!< SCB CPUID: VARIANT Mask */ -#define SCB_CPUID_ARCHITECTURE_Pos 16 /*!< SCB CPUID: ARCHITECTURE Position */ -#define SCB_CPUID_ARCHITECTURE_Msk (0xFUL << SCB_CPUID_ARCHITECTURE_Pos) /*!< SCB CPUID: ARCHITECTURE Mask */ +#define SCB_CPUID_ARCHITECTURE_Pos 16 /*!< SCB CPUID: ARCHITECTURE Position */ +#define SCB_CPUID_ARCHITECTURE_Msk (0xFUL << SCB_CPUID_ARCHITECTURE_Pos) /*!< SCB CPUID: ARCHITECTURE Mask */ -#define SCB_CPUID_PARTNO_Pos 4 /*!< SCB CPUID: PARTNO Position */ -#define SCB_CPUID_PARTNO_Msk (0xFFFUL << SCB_CPUID_PARTNO_Pos) /*!< SCB CPUID: PARTNO Mask */ +#define SCB_CPUID_PARTNO_Pos 4 /*!< SCB CPUID: PARTNO Position */ +#define SCB_CPUID_PARTNO_Msk (0xFFFUL << SCB_CPUID_PARTNO_Pos) /*!< SCB CPUID: PARTNO Mask */ -#define SCB_CPUID_REVISION_Pos 0 /*!< SCB CPUID: REVISION Position */ -#define SCB_CPUID_REVISION_Msk (0xFUL << SCB_CPUID_REVISION_Pos) /*!< SCB CPUID: REVISION Mask */ +#define SCB_CPUID_REVISION_Pos 0 /*!< SCB CPUID: REVISION Position */ +#define SCB_CPUID_REVISION_Msk (0xFUL << SCB_CPUID_REVISION_Pos) /*!< SCB CPUID: REVISION Mask */ /* SCB Interrupt Control State Register Definitions */ -#define SCB_ICSR_NMIPENDSET_Pos 31 /*!< SCB ICSR: NMIPENDSET Position */ -#define SCB_ICSR_NMIPENDSET_Msk (1UL << SCB_ICSR_NMIPENDSET_Pos) /*!< SCB ICSR: NMIPENDSET Mask */ +#define SCB_ICSR_NMIPENDSET_Pos 31 /*!< SCB ICSR: NMIPENDSET Position */ +#define SCB_ICSR_NMIPENDSET_Msk (1UL << SCB_ICSR_NMIPENDSET_Pos) /*!< SCB ICSR: NMIPENDSET Mask */ -#define SCB_ICSR_PENDSVSET_Pos 28 /*!< SCB ICSR: PENDSVSET Position */ -#define SCB_ICSR_PENDSVSET_Msk (1UL << SCB_ICSR_PENDSVSET_Pos) /*!< SCB ICSR: PENDSVSET Mask */ +#define SCB_ICSR_PENDSVSET_Pos 28 /*!< SCB ICSR: PENDSVSET Position */ +#define SCB_ICSR_PENDSVSET_Msk (1UL << SCB_ICSR_PENDSVSET_Pos) /*!< SCB ICSR: PENDSVSET Mask */ -#define SCB_ICSR_PENDSVCLR_Pos 27 /*!< SCB ICSR: PENDSVCLR Position */ -#define SCB_ICSR_PENDSVCLR_Msk (1UL << SCB_ICSR_PENDSVCLR_Pos) /*!< SCB ICSR: PENDSVCLR Mask */ +#define SCB_ICSR_PENDSVCLR_Pos 27 /*!< SCB ICSR: PENDSVCLR Position */ +#define SCB_ICSR_PENDSVCLR_Msk (1UL << SCB_ICSR_PENDSVCLR_Pos) /*!< SCB ICSR: PENDSVCLR Mask */ -#define SCB_ICSR_PENDSTSET_Pos 26 /*!< SCB ICSR: PENDSTSET Position */ -#define SCB_ICSR_PENDSTSET_Msk (1UL << SCB_ICSR_PENDSTSET_Pos) /*!< SCB ICSR: PENDSTSET Mask */ +#define SCB_ICSR_PENDSTSET_Pos 26 /*!< SCB ICSR: PENDSTSET Position */ +#define SCB_ICSR_PENDSTSET_Msk (1UL << SCB_ICSR_PENDSTSET_Pos) /*!< SCB ICSR: PENDSTSET Mask */ -#define SCB_ICSR_PENDSTCLR_Pos 25 /*!< SCB ICSR: PENDSTCLR Position */ -#define SCB_ICSR_PENDSTCLR_Msk (1UL << SCB_ICSR_PENDSTCLR_Pos) /*!< SCB ICSR: PENDSTCLR Mask */ +#define SCB_ICSR_PENDSTCLR_Pos 25 /*!< SCB ICSR: PENDSTCLR Position */ +#define SCB_ICSR_PENDSTCLR_Msk (1UL << SCB_ICSR_PENDSTCLR_Pos) /*!< SCB ICSR: PENDSTCLR Mask */ -#define SCB_ICSR_ISRPREEMPT_Pos 23 /*!< SCB ICSR: ISRPREEMPT Position */ -#define SCB_ICSR_ISRPREEMPT_Msk (1UL << SCB_ICSR_ISRPREEMPT_Pos) /*!< SCB ICSR: ISRPREEMPT Mask */ +#define SCB_ICSR_ISRPREEMPT_Pos 23 /*!< SCB ICSR: ISRPREEMPT Position */ +#define SCB_ICSR_ISRPREEMPT_Msk (1UL << SCB_ICSR_ISRPREEMPT_Pos) /*!< SCB ICSR: ISRPREEMPT Mask */ -#define SCB_ICSR_ISRPENDING_Pos 22 /*!< SCB ICSR: ISRPENDING Position */ -#define SCB_ICSR_ISRPENDING_Msk (1UL << SCB_ICSR_ISRPENDING_Pos) /*!< SCB ICSR: ISRPENDING Mask */ +#define SCB_ICSR_ISRPENDING_Pos 22 /*!< SCB ICSR: ISRPENDING Position */ +#define SCB_ICSR_ISRPENDING_Msk (1UL << SCB_ICSR_ISRPENDING_Pos) /*!< SCB ICSR: ISRPENDING Mask */ -#define SCB_ICSR_VECTPENDING_Pos 12 /*!< SCB ICSR: VECTPENDING Position */ -#define SCB_ICSR_VECTPENDING_Msk (0x1FFUL << SCB_ICSR_VECTPENDING_Pos) /*!< SCB ICSR: VECTPENDING Mask */ +#define SCB_ICSR_VECTPENDING_Pos 12 /*!< SCB ICSR: VECTPENDING Position */ +#define SCB_ICSR_VECTPENDING_Msk (0x1FFUL << SCB_ICSR_VECTPENDING_Pos) /*!< SCB ICSR: VECTPENDING Mask */ -#define SCB_ICSR_RETTOBASE_Pos 11 /*!< SCB ICSR: RETTOBASE Position */ -#define SCB_ICSR_RETTOBASE_Msk (1UL << SCB_ICSR_RETTOBASE_Pos) /*!< SCB ICSR: RETTOBASE Mask */ +#define SCB_ICSR_RETTOBASE_Pos 11 /*!< SCB ICSR: RETTOBASE Position */ +#define SCB_ICSR_RETTOBASE_Msk (1UL << SCB_ICSR_RETTOBASE_Pos) /*!< SCB ICSR: RETTOBASE Mask */ -#define SCB_ICSR_VECTACTIVE_Pos 0 /*!< SCB ICSR: VECTACTIVE Position */ -#define SCB_ICSR_VECTACTIVE_Msk (0x1FFUL << SCB_ICSR_VECTACTIVE_Pos) /*!< SCB ICSR: VECTACTIVE Mask */ +#define SCB_ICSR_VECTACTIVE_Pos 0 /*!< SCB ICSR: VECTACTIVE Position */ +#define SCB_ICSR_VECTACTIVE_Msk (0x1FFUL << SCB_ICSR_VECTACTIVE_Pos) /*!< SCB ICSR: VECTACTIVE Mask */ /* SCB Vector Table Offset Register Definitions */ -#define SCB_VTOR_TBLOFF_Pos 7 /*!< SCB VTOR: TBLOFF Position */ -#define SCB_VTOR_TBLOFF_Msk (0x1FFFFFFUL << SCB_VTOR_TBLOFF_Pos) /*!< SCB VTOR: TBLOFF Mask */ +#define SCB_VTOR_TBLOFF_Pos 7 /*!< SCB VTOR: TBLOFF Position */ +#define SCB_VTOR_TBLOFF_Msk (0x1FFFFFFUL << SCB_VTOR_TBLOFF_Pos) /*!< SCB VTOR: TBLOFF Mask */ /* SCB Application Interrupt and Reset Control Register Definitions */ -#define SCB_AIRCR_VECTKEY_Pos 16 /*!< SCB AIRCR: VECTKEY Position */ -#define SCB_AIRCR_VECTKEY_Msk (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos) /*!< SCB AIRCR: VECTKEY Mask */ +#define SCB_AIRCR_VECTKEY_Pos 16 /*!< SCB AIRCR: VECTKEY Position */ +#define SCB_AIRCR_VECTKEY_Msk (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos) /*!< SCB AIRCR: VECTKEY Mask */ -#define SCB_AIRCR_VECTKEYSTAT_Pos 16 /*!< SCB AIRCR: VECTKEYSTAT Position */ -#define SCB_AIRCR_VECTKEYSTAT_Msk (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos) /*!< SCB AIRCR: VECTKEYSTAT Mask */ +#define SCB_AIRCR_VECTKEYSTAT_Pos 16 /*!< SCB AIRCR: VECTKEYSTAT Position */ +#define SCB_AIRCR_VECTKEYSTAT_Msk (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos) /*!< SCB AIRCR: VECTKEYSTAT Mask */ -#define SCB_AIRCR_ENDIANESS_Pos 15 /*!< SCB AIRCR: ENDIANESS Position */ -#define SCB_AIRCR_ENDIANESS_Msk (1UL << SCB_AIRCR_ENDIANESS_Pos) /*!< SCB AIRCR: ENDIANESS Mask */ +#define SCB_AIRCR_ENDIANESS_Pos 15 /*!< SCB AIRCR: ENDIANESS Position */ +#define SCB_AIRCR_ENDIANESS_Msk (1UL << SCB_AIRCR_ENDIANESS_Pos) /*!< SCB AIRCR: ENDIANESS Mask */ -#define SCB_AIRCR_PRIGROUP_Pos 8 /*!< SCB AIRCR: PRIGROUP Position */ -#define SCB_AIRCR_PRIGROUP_Msk (7UL << SCB_AIRCR_PRIGROUP_Pos) /*!< SCB AIRCR: PRIGROUP Mask */ +#define SCB_AIRCR_PRIGROUP_Pos 8 /*!< SCB AIRCR: PRIGROUP Position */ +#define SCB_AIRCR_PRIGROUP_Msk (7UL << SCB_AIRCR_PRIGROUP_Pos) /*!< SCB AIRCR: PRIGROUP Mask */ -#define SCB_AIRCR_SYSRESETREQ_Pos 2 /*!< SCB AIRCR: SYSRESETREQ Position */ -#define SCB_AIRCR_SYSRESETREQ_Msk (1UL << SCB_AIRCR_SYSRESETREQ_Pos) /*!< SCB AIRCR: SYSRESETREQ Mask */ +#define SCB_AIRCR_SYSRESETREQ_Pos 2 /*!< SCB AIRCR: SYSRESETREQ Position */ +#define SCB_AIRCR_SYSRESETREQ_Msk (1UL << SCB_AIRCR_SYSRESETREQ_Pos) /*!< SCB AIRCR: SYSRESETREQ Mask */ -#define SCB_AIRCR_VECTCLRACTIVE_Pos 1 /*!< SCB AIRCR: VECTCLRACTIVE Position */ -#define SCB_AIRCR_VECTCLRACTIVE_Msk (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos) /*!< SCB AIRCR: VECTCLRACTIVE Mask */ +#define SCB_AIRCR_VECTCLRACTIVE_Pos 1 /*!< SCB AIRCR: VECTCLRACTIVE Position */ +#define SCB_AIRCR_VECTCLRACTIVE_Msk (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos) /*!< SCB AIRCR: VECTCLRACTIVE Mask */ -#define SCB_AIRCR_VECTRESET_Pos 0 /*!< SCB AIRCR: VECTRESET Position */ -#define SCB_AIRCR_VECTRESET_Msk (1UL << SCB_AIRCR_VECTRESET_Pos) /*!< SCB AIRCR: VECTRESET Mask */ +#define SCB_AIRCR_VECTRESET_Pos 0 /*!< SCB AIRCR: VECTRESET Position */ +#define SCB_AIRCR_VECTRESET_Msk (1UL << SCB_AIRCR_VECTRESET_Pos) /*!< SCB AIRCR: VECTRESET Mask */ /* SCB System Control Register Definitions */ -#define SCB_SCR_SEVONPEND_Pos 4 /*!< SCB SCR: SEVONPEND Position */ -#define SCB_SCR_SEVONPEND_Msk (1UL << SCB_SCR_SEVONPEND_Pos) /*!< SCB SCR: SEVONPEND Mask */ +#define SCB_SCR_SEVONPEND_Pos 4 /*!< SCB SCR: SEVONPEND Position */ +#define SCB_SCR_SEVONPEND_Msk (1UL << SCB_SCR_SEVONPEND_Pos) /*!< SCB SCR: SEVONPEND Mask */ -#define SCB_SCR_SLEEPDEEP_Pos 2 /*!< SCB SCR: SLEEPDEEP Position */ -#define SCB_SCR_SLEEPDEEP_Msk (1UL << SCB_SCR_SLEEPDEEP_Pos) /*!< SCB SCR: SLEEPDEEP Mask */ +#define SCB_SCR_SLEEPDEEP_Pos 2 /*!< SCB SCR: SLEEPDEEP Position */ +#define SCB_SCR_SLEEPDEEP_Msk (1UL << SCB_SCR_SLEEPDEEP_Pos) /*!< SCB SCR: SLEEPDEEP Mask */ -#define SCB_SCR_SLEEPONEXIT_Pos 1 /*!< SCB SCR: SLEEPONEXIT Position */ -#define SCB_SCR_SLEEPONEXIT_Msk (1UL << SCB_SCR_SLEEPONEXIT_Pos) /*!< SCB SCR: SLEEPONEXIT Mask */ +#define SCB_SCR_SLEEPONEXIT_Pos 1 /*!< SCB SCR: SLEEPONEXIT Position */ +#define SCB_SCR_SLEEPONEXIT_Msk (1UL << SCB_SCR_SLEEPONEXIT_Pos) /*!< SCB SCR: SLEEPONEXIT Mask */ /* SCB Configuration Control Register Definitions */ -#define SCB_CCR_STKALIGN_Pos 9 /*!< SCB CCR: STKALIGN Position */ -#define SCB_CCR_STKALIGN_Msk (1UL << SCB_CCR_STKALIGN_Pos) /*!< SCB CCR: STKALIGN Mask */ +#define SCB_CCR_STKALIGN_Pos 9 /*!< SCB CCR: STKALIGN Position */ +#define SCB_CCR_STKALIGN_Msk (1UL << SCB_CCR_STKALIGN_Pos) /*!< SCB CCR: STKALIGN Mask */ -#define SCB_CCR_BFHFNMIGN_Pos 8 /*!< SCB CCR: BFHFNMIGN Position */ -#define SCB_CCR_BFHFNMIGN_Msk (1UL << SCB_CCR_BFHFNMIGN_Pos) /*!< SCB CCR: BFHFNMIGN Mask */ +#define SCB_CCR_BFHFNMIGN_Pos 8 /*!< SCB CCR: BFHFNMIGN Position */ +#define SCB_CCR_BFHFNMIGN_Msk (1UL << SCB_CCR_BFHFNMIGN_Pos) /*!< SCB CCR: BFHFNMIGN Mask */ -#define SCB_CCR_DIV_0_TRP_Pos 4 /*!< SCB CCR: DIV_0_TRP Position */ -#define SCB_CCR_DIV_0_TRP_Msk (1UL << SCB_CCR_DIV_0_TRP_Pos) /*!< SCB CCR: DIV_0_TRP Mask */ +#define SCB_CCR_DIV_0_TRP_Pos 4 /*!< SCB CCR: DIV_0_TRP Position */ +#define SCB_CCR_DIV_0_TRP_Msk (1UL << SCB_CCR_DIV_0_TRP_Pos) /*!< SCB CCR: DIV_0_TRP Mask */ -#define SCB_CCR_UNALIGN_TRP_Pos 3 /*!< SCB CCR: UNALIGN_TRP Position */ -#define SCB_CCR_UNALIGN_TRP_Msk (1UL << SCB_CCR_UNALIGN_TRP_Pos) /*!< SCB CCR: UNALIGN_TRP Mask */ +#define SCB_CCR_UNALIGN_TRP_Pos 3 /*!< SCB CCR: UNALIGN_TRP Position */ +#define SCB_CCR_UNALIGN_TRP_Msk (1UL << SCB_CCR_UNALIGN_TRP_Pos) /*!< SCB CCR: UNALIGN_TRP Mask */ -#define SCB_CCR_USERSETMPEND_Pos 1 /*!< SCB CCR: USERSETMPEND Position */ -#define SCB_CCR_USERSETMPEND_Msk (1UL << SCB_CCR_USERSETMPEND_Pos) /*!< SCB CCR: USERSETMPEND Mask */ +#define SCB_CCR_USERSETMPEND_Pos 1 /*!< SCB CCR: USERSETMPEND Position */ +#define SCB_CCR_USERSETMPEND_Msk (1UL << SCB_CCR_USERSETMPEND_Pos) /*!< SCB CCR: USERSETMPEND Mask */ -#define SCB_CCR_NONBASETHRDENA_Pos 0 /*!< SCB CCR: NONBASETHRDENA Position */ -#define SCB_CCR_NONBASETHRDENA_Msk (1UL << SCB_CCR_NONBASETHRDENA_Pos) /*!< SCB CCR: NONBASETHRDENA Mask */ +#define SCB_CCR_NONBASETHRDENA_Pos 0 /*!< SCB CCR: NONBASETHRDENA Position */ +#define SCB_CCR_NONBASETHRDENA_Msk (1UL << SCB_CCR_NONBASETHRDENA_Pos) /*!< SCB CCR: NONBASETHRDENA Mask */ /* SCB System Handler Control and State Register Definitions */ -#define SCB_SHCSR_USGFAULTENA_Pos 18 /*!< SCB SHCSR: USGFAULTENA Position */ -#define SCB_SHCSR_USGFAULTENA_Msk (1UL << SCB_SHCSR_USGFAULTENA_Pos) /*!< SCB SHCSR: USGFAULTENA Mask */ +#define SCB_SHCSR_USGFAULTENA_Pos 18 /*!< SCB SHCSR: USGFAULTENA Position */ +#define SCB_SHCSR_USGFAULTENA_Msk (1UL << SCB_SHCSR_USGFAULTENA_Pos) /*!< SCB SHCSR: USGFAULTENA Mask */ -#define SCB_SHCSR_BUSFAULTENA_Pos 17 /*!< SCB SHCSR: BUSFAULTENA Position */ -#define SCB_SHCSR_BUSFAULTENA_Msk (1UL << SCB_SHCSR_BUSFAULTENA_Pos) /*!< SCB SHCSR: BUSFAULTENA Mask */ +#define SCB_SHCSR_BUSFAULTENA_Pos 17 /*!< SCB SHCSR: BUSFAULTENA Position */ +#define SCB_SHCSR_BUSFAULTENA_Msk (1UL << SCB_SHCSR_BUSFAULTENA_Pos) /*!< SCB SHCSR: BUSFAULTENA Mask */ -#define SCB_SHCSR_MEMFAULTENA_Pos 16 /*!< SCB SHCSR: MEMFAULTENA Position */ -#define SCB_SHCSR_MEMFAULTENA_Msk (1UL << SCB_SHCSR_MEMFAULTENA_Pos) /*!< SCB SHCSR: MEMFAULTENA Mask */ +#define SCB_SHCSR_MEMFAULTENA_Pos 16 /*!< SCB SHCSR: MEMFAULTENA Position */ +#define SCB_SHCSR_MEMFAULTENA_Msk (1UL << SCB_SHCSR_MEMFAULTENA_Pos) /*!< SCB SHCSR: MEMFAULTENA Mask */ -#define SCB_SHCSR_SVCALLPENDED_Pos 15 /*!< SCB SHCSR: SVCALLPENDED Position */ -#define SCB_SHCSR_SVCALLPENDED_Msk (1UL << SCB_SHCSR_SVCALLPENDED_Pos) /*!< SCB SHCSR: SVCALLPENDED Mask */ +#define SCB_SHCSR_SVCALLPENDED_Pos 15 /*!< SCB SHCSR: SVCALLPENDED Position */ +#define SCB_SHCSR_SVCALLPENDED_Msk (1UL << SCB_SHCSR_SVCALLPENDED_Pos) /*!< SCB SHCSR: SVCALLPENDED Mask */ -#define SCB_SHCSR_BUSFAULTPENDED_Pos 14 /*!< SCB SHCSR: BUSFAULTPENDED Position */ -#define SCB_SHCSR_BUSFAULTPENDED_Msk (1UL << SCB_SHCSR_BUSFAULTPENDED_Pos) /*!< SCB SHCSR: BUSFAULTPENDED Mask */ +#define SCB_SHCSR_BUSFAULTPENDED_Pos 14 /*!< SCB SHCSR: BUSFAULTPENDED Position */ +#define SCB_SHCSR_BUSFAULTPENDED_Msk (1UL << SCB_SHCSR_BUSFAULTPENDED_Pos) /*!< SCB SHCSR: BUSFAULTPENDED Mask */ -#define SCB_SHCSR_MEMFAULTPENDED_Pos 13 /*!< SCB SHCSR: MEMFAULTPENDED Position */ -#define SCB_SHCSR_MEMFAULTPENDED_Msk (1UL << SCB_SHCSR_MEMFAULTPENDED_Pos) /*!< SCB SHCSR: MEMFAULTPENDED Mask */ +#define SCB_SHCSR_MEMFAULTPENDED_Pos 13 /*!< SCB SHCSR: MEMFAULTPENDED Position */ +#define SCB_SHCSR_MEMFAULTPENDED_Msk (1UL << SCB_SHCSR_MEMFAULTPENDED_Pos) /*!< SCB SHCSR: MEMFAULTPENDED Mask */ -#define SCB_SHCSR_USGFAULTPENDED_Pos 12 /*!< SCB SHCSR: USGFAULTPENDED Position */ -#define SCB_SHCSR_USGFAULTPENDED_Msk (1UL << SCB_SHCSR_USGFAULTPENDED_Pos) /*!< SCB SHCSR: USGFAULTPENDED Mask */ +#define SCB_SHCSR_USGFAULTPENDED_Pos 12 /*!< SCB SHCSR: USGFAULTPENDED Position */ +#define SCB_SHCSR_USGFAULTPENDED_Msk (1UL << SCB_SHCSR_USGFAULTPENDED_Pos) /*!< SCB SHCSR: USGFAULTPENDED Mask */ -#define SCB_SHCSR_SYSTICKACT_Pos 11 /*!< SCB SHCSR: SYSTICKACT Position */ -#define SCB_SHCSR_SYSTICKACT_Msk (1UL << SCB_SHCSR_SYSTICKACT_Pos) /*!< SCB SHCSR: SYSTICKACT Mask */ +#define SCB_SHCSR_SYSTICKACT_Pos 11 /*!< SCB SHCSR: SYSTICKACT Position */ +#define SCB_SHCSR_SYSTICKACT_Msk (1UL << SCB_SHCSR_SYSTICKACT_Pos) /*!< SCB SHCSR: SYSTICKACT Mask */ -#define SCB_SHCSR_PENDSVACT_Pos 10 /*!< SCB SHCSR: PENDSVACT Position */ -#define SCB_SHCSR_PENDSVACT_Msk (1UL << SCB_SHCSR_PENDSVACT_Pos) /*!< SCB SHCSR: PENDSVACT Mask */ +#define SCB_SHCSR_PENDSVACT_Pos 10 /*!< SCB SHCSR: PENDSVACT Position */ +#define SCB_SHCSR_PENDSVACT_Msk (1UL << SCB_SHCSR_PENDSVACT_Pos) /*!< SCB SHCSR: PENDSVACT Mask */ -#define SCB_SHCSR_MONITORACT_Pos 8 /*!< SCB SHCSR: MONITORACT Position */ -#define SCB_SHCSR_MONITORACT_Msk (1UL << SCB_SHCSR_MONITORACT_Pos) /*!< SCB SHCSR: MONITORACT Mask */ +#define SCB_SHCSR_MONITORACT_Pos 8 /*!< SCB SHCSR: MONITORACT Position */ +#define SCB_SHCSR_MONITORACT_Msk (1UL << SCB_SHCSR_MONITORACT_Pos) /*!< SCB SHCSR: MONITORACT Mask */ -#define SCB_SHCSR_SVCALLACT_Pos 7 /*!< SCB SHCSR: SVCALLACT Position */ -#define SCB_SHCSR_SVCALLACT_Msk (1UL << SCB_SHCSR_SVCALLACT_Pos) /*!< SCB SHCSR: SVCALLACT Mask */ +#define SCB_SHCSR_SVCALLACT_Pos 7 /*!< SCB SHCSR: SVCALLACT Position */ +#define SCB_SHCSR_SVCALLACT_Msk (1UL << SCB_SHCSR_SVCALLACT_Pos) /*!< SCB SHCSR: SVCALLACT Mask */ -#define SCB_SHCSR_USGFAULTACT_Pos 3 /*!< SCB SHCSR: USGFAULTACT Position */ -#define SCB_SHCSR_USGFAULTACT_Msk (1UL << SCB_SHCSR_USGFAULTACT_Pos) /*!< SCB SHCSR: USGFAULTACT Mask */ +#define SCB_SHCSR_USGFAULTACT_Pos 3 /*!< SCB SHCSR: USGFAULTACT Position */ +#define SCB_SHCSR_USGFAULTACT_Msk (1UL << SCB_SHCSR_USGFAULTACT_Pos) /*!< SCB SHCSR: USGFAULTACT Mask */ -#define SCB_SHCSR_BUSFAULTACT_Pos 1 /*!< SCB SHCSR: BUSFAULTACT Position */ -#define SCB_SHCSR_BUSFAULTACT_Msk (1UL << SCB_SHCSR_BUSFAULTACT_Pos) /*!< SCB SHCSR: BUSFAULTACT Mask */ +#define SCB_SHCSR_BUSFAULTACT_Pos 1 /*!< SCB SHCSR: BUSFAULTACT Position */ +#define SCB_SHCSR_BUSFAULTACT_Msk (1UL << SCB_SHCSR_BUSFAULTACT_Pos) /*!< SCB SHCSR: BUSFAULTACT Mask */ -#define SCB_SHCSR_MEMFAULTACT_Pos 0 /*!< SCB SHCSR: MEMFAULTACT Position */ -#define SCB_SHCSR_MEMFAULTACT_Msk (1UL << SCB_SHCSR_MEMFAULTACT_Pos) /*!< SCB SHCSR: MEMFAULTACT Mask */ +#define SCB_SHCSR_MEMFAULTACT_Pos 0 /*!< SCB SHCSR: MEMFAULTACT Position */ +#define SCB_SHCSR_MEMFAULTACT_Msk (1UL << SCB_SHCSR_MEMFAULTACT_Pos) /*!< SCB SHCSR: MEMFAULTACT Mask */ /* SCB Configurable Fault Status Registers Definitions */ -#define SCB_CFSR_USGFAULTSR_Pos 16 /*!< SCB CFSR: Usage Fault Status Register Position */ -#define SCB_CFSR_USGFAULTSR_Msk (0xFFFFUL << SCB_CFSR_USGFAULTSR_Pos) /*!< SCB CFSR: Usage Fault Status Register Mask */ +#define SCB_CFSR_USGFAULTSR_Pos 16 /*!< SCB CFSR: Usage Fault Status Register Position */ +#define SCB_CFSR_USGFAULTSR_Msk (0xFFFFUL << SCB_CFSR_USGFAULTSR_Pos) /*!< SCB CFSR: Usage Fault Status Register Mask */ -#define SCB_CFSR_BUSFAULTSR_Pos 8 /*!< SCB CFSR: Bus Fault Status Register Position */ -#define SCB_CFSR_BUSFAULTSR_Msk (0xFFUL << SCB_CFSR_BUSFAULTSR_Pos) /*!< SCB CFSR: Bus Fault Status Register Mask */ +#define SCB_CFSR_BUSFAULTSR_Pos 8 /*!< SCB CFSR: Bus Fault Status Register Position */ +#define SCB_CFSR_BUSFAULTSR_Msk (0xFFUL << SCB_CFSR_BUSFAULTSR_Pos) /*!< SCB CFSR: Bus Fault Status Register Mask */ -#define SCB_CFSR_MEMFAULTSR_Pos 0 /*!< SCB CFSR: Memory Manage Fault Status Register Position */ -#define SCB_CFSR_MEMFAULTSR_Msk (0xFFUL << SCB_CFSR_MEMFAULTSR_Pos) /*!< SCB CFSR: Memory Manage Fault Status Register Mask */ +#define SCB_CFSR_MEMFAULTSR_Pos 0 /*!< SCB CFSR: Memory Manage Fault Status Register Position */ +#define SCB_CFSR_MEMFAULTSR_Msk (0xFFUL << SCB_CFSR_MEMFAULTSR_Pos) /*!< SCB CFSR: Memory Manage Fault Status Register Mask */ /* SCB Hard Fault Status Registers Definitions */ -#define SCB_HFSR_DEBUGEVT_Pos 31 /*!< SCB HFSR: DEBUGEVT Position */ -#define SCB_HFSR_DEBUGEVT_Msk (1UL << SCB_HFSR_DEBUGEVT_Pos) /*!< SCB HFSR: DEBUGEVT Mask */ +#define SCB_HFSR_DEBUGEVT_Pos 31 /*!< SCB HFSR: DEBUGEVT Position */ +#define SCB_HFSR_DEBUGEVT_Msk (1UL << SCB_HFSR_DEBUGEVT_Pos) /*!< SCB HFSR: DEBUGEVT Mask */ -#define SCB_HFSR_FORCED_Pos 30 /*!< SCB HFSR: FORCED Position */ -#define SCB_HFSR_FORCED_Msk (1UL << SCB_HFSR_FORCED_Pos) /*!< SCB HFSR: FORCED Mask */ +#define SCB_HFSR_FORCED_Pos 30 /*!< SCB HFSR: FORCED Position */ +#define SCB_HFSR_FORCED_Msk (1UL << SCB_HFSR_FORCED_Pos) /*!< SCB HFSR: FORCED Mask */ -#define SCB_HFSR_VECTTBL_Pos 1 /*!< SCB HFSR: VECTTBL Position */ -#define SCB_HFSR_VECTTBL_Msk (1UL << SCB_HFSR_VECTTBL_Pos) /*!< SCB HFSR: VECTTBL Mask */ +#define SCB_HFSR_VECTTBL_Pos 1 /*!< SCB HFSR: VECTTBL Position */ +#define SCB_HFSR_VECTTBL_Msk (1UL << SCB_HFSR_VECTTBL_Pos) /*!< SCB HFSR: VECTTBL Mask */ /* SCB Debug Fault Status Register Definitions */ -#define SCB_DFSR_EXTERNAL_Pos 4 /*!< SCB DFSR: EXTERNAL Position */ -#define SCB_DFSR_EXTERNAL_Msk (1UL << SCB_DFSR_EXTERNAL_Pos) /*!< SCB DFSR: EXTERNAL Mask */ - -#define SCB_DFSR_VCATCH_Pos 3 /*!< SCB DFSR: VCATCH Position */ -#define SCB_DFSR_VCATCH_Msk (1UL << SCB_DFSR_VCATCH_Pos) /*!< SCB DFSR: VCATCH Mask */ +#define SCB_DFSR_EXTERNAL_Pos 4 /*!< SCB DFSR: EXTERNAL Position */ +#define SCB_DFSR_EXTERNAL_Msk (1UL << SCB_DFSR_EXTERNAL_Pos) /*!< SCB DFSR: EXTERNAL Mask */ -#define SCB_DFSR_DWTTRAP_Pos 2 /*!< SCB DFSR: DWTTRAP Position */ -#define SCB_DFSR_DWTTRAP_Msk (1UL << SCB_DFSR_DWTTRAP_Pos) /*!< SCB DFSR: DWTTRAP Mask */ +#define SCB_DFSR_VCATCH_Pos 3 /*!< SCB DFSR: VCATCH Position */ +#define SCB_DFSR_VCATCH_Msk (1UL << SCB_DFSR_VCATCH_Pos) /*!< SCB DFSR: VCATCH Mask */ -#define SCB_DFSR_BKPT_Pos 1 /*!< SCB DFSR: BKPT Position */ -#define SCB_DFSR_BKPT_Msk (1UL << SCB_DFSR_BKPT_Pos) /*!< SCB DFSR: BKPT Mask */ +#define SCB_DFSR_DWTTRAP_Pos 2 /*!< SCB DFSR: DWTTRAP Position */ +#define SCB_DFSR_DWTTRAP_Msk (1UL << SCB_DFSR_DWTTRAP_Pos) /*!< SCB DFSR: DWTTRAP Mask */ -#define SCB_DFSR_HALTED_Pos 0 /*!< SCB DFSR: HALTED Position */ -#define SCB_DFSR_HALTED_Msk (1UL << SCB_DFSR_HALTED_Pos) /*!< SCB DFSR: HALTED Mask */ +#define SCB_DFSR_BKPT_Pos 1 /*!< SCB DFSR: BKPT Position */ +#define SCB_DFSR_BKPT_Msk (1UL << SCB_DFSR_BKPT_Pos) /*!< SCB DFSR: BKPT Mask */ -/*@} end of group CMSIS_SCB */ +#define SCB_DFSR_HALTED_Pos 0 /*!< SCB DFSR: HALTED Position */ +#define SCB_DFSR_HALTED_Msk (1UL << SCB_DFSR_HALTED_Pos) /*!< SCB DFSR: HALTED Mask */ + /*@} end of group CMSIS_SCB */ -/** \ingroup CMSIS_core_register + /** \ingroup CMSIS_core_register \defgroup CMSIS_SCnSCB System Controls not in SCB (SCnSCB) \brief Type definitions for the System Control and ID Register not in the SCB @{ */ -/** \brief Structure type to access the System Control and ID Register not in the SCB. + /** \brief Structure type to access the System Control and ID Register not in the SCB. */ -typedef struct -{ - uint32_t RESERVED0[1]; - __I uint32_t ICTR; /*!< Offset: 0x004 (R/ ) Interrupt Controller Type Register */ - __IO uint32_t ACTLR; /*!< Offset: 0x008 (R/W) Auxiliary Control Register */ -} SCnSCB_Type; + typedef struct + { + uint32_t RESERVED0[1]; + __I uint32_t ICTR; /*!< Offset: 0x004 (R/ ) Interrupt Controller Type Register */ + __IO uint32_t ACTLR; /*!< Offset: 0x008 (R/W) Auxiliary Control Register */ + } SCnSCB_Type; /* Interrupt Controller Type Register Definitions */ -#define SCnSCB_ICTR_INTLINESNUM_Pos 0 /*!< ICTR: INTLINESNUM Position */ -#define SCnSCB_ICTR_INTLINESNUM_Msk (0xFUL << SCnSCB_ICTR_INTLINESNUM_Pos) /*!< ICTR: INTLINESNUM Mask */ +#define SCnSCB_ICTR_INTLINESNUM_Pos 0 /*!< ICTR: INTLINESNUM Position */ +#define SCnSCB_ICTR_INTLINESNUM_Msk (0xFUL << SCnSCB_ICTR_INTLINESNUM_Pos) /*!< ICTR: INTLINESNUM Mask */ /* Auxiliary Control Register Definitions */ -#define SCnSCB_ACTLR_DISOOFP_Pos 9 /*!< ACTLR: DISOOFP Position */ -#define SCnSCB_ACTLR_DISOOFP_Msk (1UL << SCnSCB_ACTLR_DISOOFP_Pos) /*!< ACTLR: DISOOFP Mask */ - -#define SCnSCB_ACTLR_DISFPCA_Pos 8 /*!< ACTLR: DISFPCA Position */ -#define SCnSCB_ACTLR_DISFPCA_Msk (1UL << SCnSCB_ACTLR_DISFPCA_Pos) /*!< ACTLR: DISFPCA Mask */ +#define SCnSCB_ACTLR_DISOOFP_Pos 9 /*!< ACTLR: DISOOFP Position */ +#define SCnSCB_ACTLR_DISOOFP_Msk (1UL << SCnSCB_ACTLR_DISOOFP_Pos) /*!< ACTLR: DISOOFP Mask */ -#define SCnSCB_ACTLR_DISFOLD_Pos 2 /*!< ACTLR: DISFOLD Position */ -#define SCnSCB_ACTLR_DISFOLD_Msk (1UL << SCnSCB_ACTLR_DISFOLD_Pos) /*!< ACTLR: DISFOLD Mask */ +#define SCnSCB_ACTLR_DISFPCA_Pos 8 /*!< ACTLR: DISFPCA Position */ +#define SCnSCB_ACTLR_DISFPCA_Msk (1UL << SCnSCB_ACTLR_DISFPCA_Pos) /*!< ACTLR: DISFPCA Mask */ -#define SCnSCB_ACTLR_DISDEFWBUF_Pos 1 /*!< ACTLR: DISDEFWBUF Position */ -#define SCnSCB_ACTLR_DISDEFWBUF_Msk (1UL << SCnSCB_ACTLR_DISDEFWBUF_Pos) /*!< ACTLR: DISDEFWBUF Mask */ +#define SCnSCB_ACTLR_DISFOLD_Pos 2 /*!< ACTLR: DISFOLD Position */ +#define SCnSCB_ACTLR_DISFOLD_Msk (1UL << SCnSCB_ACTLR_DISFOLD_Pos) /*!< ACTLR: DISFOLD Mask */ -#define SCnSCB_ACTLR_DISMCYCINT_Pos 0 /*!< ACTLR: DISMCYCINT Position */ -#define SCnSCB_ACTLR_DISMCYCINT_Msk (1UL << SCnSCB_ACTLR_DISMCYCINT_Pos) /*!< ACTLR: DISMCYCINT Mask */ +#define SCnSCB_ACTLR_DISDEFWBUF_Pos 1 /*!< ACTLR: DISDEFWBUF Position */ +#define SCnSCB_ACTLR_DISDEFWBUF_Msk (1UL << SCnSCB_ACTLR_DISDEFWBUF_Pos) /*!< ACTLR: DISDEFWBUF Mask */ -/*@} end of group CMSIS_SCnotSCB */ +#define SCnSCB_ACTLR_DISMCYCINT_Pos 0 /*!< ACTLR: DISMCYCINT Position */ +#define SCnSCB_ACTLR_DISMCYCINT_Msk (1UL << SCnSCB_ACTLR_DISMCYCINT_Pos) /*!< ACTLR: DISMCYCINT Mask */ + /*@} end of group CMSIS_SCnotSCB */ -/** \ingroup CMSIS_core_register + /** \ingroup CMSIS_core_register \defgroup CMSIS_SysTick System Tick Timer (SysTick) \brief Type definitions for the System Timer Registers. @{ */ -/** \brief Structure type to access the System Timer (SysTick). + /** \brief Structure type to access the System Timer (SysTick). */ -typedef struct -{ - __IO uint32_t CTRL; /*!< Offset: 0x000 (R/W) SysTick Control and Status Register */ - __IO uint32_t LOAD; /*!< Offset: 0x004 (R/W) SysTick Reload Value Register */ - __IO uint32_t VAL; /*!< Offset: 0x008 (R/W) SysTick Current Value Register */ - __I uint32_t CALIB; /*!< Offset: 0x00C (R/ ) SysTick Calibration Register */ -} SysTick_Type; + typedef struct + { + __IO uint32_t CTRL; /*!< Offset: 0x000 (R/W) SysTick Control and Status Register */ + __IO uint32_t LOAD; /*!< Offset: 0x004 (R/W) SysTick Reload Value Register */ + __IO uint32_t VAL; /*!< Offset: 0x008 (R/W) SysTick Current Value Register */ + __I uint32_t CALIB; /*!< Offset: 0x00C (R/ ) SysTick Calibration Register */ + } SysTick_Type; /* SysTick Control / Status Register Definitions */ -#define SysTick_CTRL_COUNTFLAG_Pos 16 /*!< SysTick CTRL: COUNTFLAG Position */ -#define SysTick_CTRL_COUNTFLAG_Msk (1UL << SysTick_CTRL_COUNTFLAG_Pos) /*!< SysTick CTRL: COUNTFLAG Mask */ +#define SysTick_CTRL_COUNTFLAG_Pos 16 /*!< SysTick CTRL: COUNTFLAG Position */ +#define SysTick_CTRL_COUNTFLAG_Msk (1UL << SysTick_CTRL_COUNTFLAG_Pos) /*!< SysTick CTRL: COUNTFLAG Mask */ -#define SysTick_CTRL_CLKSOURCE_Pos 2 /*!< SysTick CTRL: CLKSOURCE Position */ -#define SysTick_CTRL_CLKSOURCE_Msk (1UL << SysTick_CTRL_CLKSOURCE_Pos) /*!< SysTick CTRL: CLKSOURCE Mask */ +#define SysTick_CTRL_CLKSOURCE_Pos 2 /*!< SysTick CTRL: CLKSOURCE Position */ +#define SysTick_CTRL_CLKSOURCE_Msk (1UL << SysTick_CTRL_CLKSOURCE_Pos) /*!< SysTick CTRL: CLKSOURCE Mask */ -#define SysTick_CTRL_TICKINT_Pos 1 /*!< SysTick CTRL: TICKINT Position */ -#define SysTick_CTRL_TICKINT_Msk (1UL << SysTick_CTRL_TICKINT_Pos) /*!< SysTick CTRL: TICKINT Mask */ +#define SysTick_CTRL_TICKINT_Pos 1 /*!< SysTick CTRL: TICKINT Position */ +#define SysTick_CTRL_TICKINT_Msk (1UL << SysTick_CTRL_TICKINT_Pos) /*!< SysTick CTRL: TICKINT Mask */ -#define SysTick_CTRL_ENABLE_Pos 0 /*!< SysTick CTRL: ENABLE Position */ -#define SysTick_CTRL_ENABLE_Msk (1UL << SysTick_CTRL_ENABLE_Pos) /*!< SysTick CTRL: ENABLE Mask */ +#define SysTick_CTRL_ENABLE_Pos 0 /*!< SysTick CTRL: ENABLE Position */ +#define SysTick_CTRL_ENABLE_Msk (1UL << SysTick_CTRL_ENABLE_Pos) /*!< SysTick CTRL: ENABLE Mask */ /* SysTick Reload Register Definitions */ -#define SysTick_LOAD_RELOAD_Pos 0 /*!< SysTick LOAD: RELOAD Position */ -#define SysTick_LOAD_RELOAD_Msk (0xFFFFFFUL << SysTick_LOAD_RELOAD_Pos) /*!< SysTick LOAD: RELOAD Mask */ +#define SysTick_LOAD_RELOAD_Pos 0 /*!< SysTick LOAD: RELOAD Position */ +#define SysTick_LOAD_RELOAD_Msk (0xFFFFFFUL << SysTick_LOAD_RELOAD_Pos) /*!< SysTick LOAD: RELOAD Mask */ /* SysTick Current Register Definitions */ -#define SysTick_VAL_CURRENT_Pos 0 /*!< SysTick VAL: CURRENT Position */ -#define SysTick_VAL_CURRENT_Msk (0xFFFFFFUL << SysTick_VAL_CURRENT_Pos) /*!< SysTick VAL: CURRENT Mask */ +#define SysTick_VAL_CURRENT_Pos 0 /*!< SysTick VAL: CURRENT Position */ +#define SysTick_VAL_CURRENT_Msk (0xFFFFFFUL << SysTick_VAL_CURRENT_Pos) /*!< SysTick VAL: CURRENT Mask */ /* SysTick Calibration Register Definitions */ -#define SysTick_CALIB_NOREF_Pos 31 /*!< SysTick CALIB: NOREF Position */ -#define SysTick_CALIB_NOREF_Msk (1UL << SysTick_CALIB_NOREF_Pos) /*!< SysTick CALIB: NOREF Mask */ - -#define SysTick_CALIB_SKEW_Pos 30 /*!< SysTick CALIB: SKEW Position */ -#define SysTick_CALIB_SKEW_Msk (1UL << SysTick_CALIB_SKEW_Pos) /*!< SysTick CALIB: SKEW Mask */ +#define SysTick_CALIB_NOREF_Pos 31 /*!< SysTick CALIB: NOREF Position */ +#define SysTick_CALIB_NOREF_Msk (1UL << SysTick_CALIB_NOREF_Pos) /*!< SysTick CALIB: NOREF Mask */ -#define SysTick_CALIB_TENMS_Pos 0 /*!< SysTick CALIB: TENMS Position */ -#define SysTick_CALIB_TENMS_Msk (0xFFFFFFUL << SysTick_CALIB_TENMS_Pos) /*!< SysTick CALIB: TENMS Mask */ +#define SysTick_CALIB_SKEW_Pos 30 /*!< SysTick CALIB: SKEW Position */ +#define SysTick_CALIB_SKEW_Msk (1UL << SysTick_CALIB_SKEW_Pos) /*!< SysTick CALIB: SKEW Mask */ -/*@} end of group CMSIS_SysTick */ +#define SysTick_CALIB_TENMS_Pos 0 /*!< SysTick CALIB: TENMS Position */ +#define SysTick_CALIB_TENMS_Msk (0xFFFFFFUL << SysTick_CALIB_TENMS_Pos) /*!< SysTick CALIB: TENMS Mask */ + /*@} end of group CMSIS_SysTick */ -/** \ingroup CMSIS_core_register + /** \ingroup CMSIS_core_register \defgroup CMSIS_ITM Instrumentation Trace Macrocell (ITM) \brief Type definitions for the Instrumentation Trace Macrocell (ITM) @{ */ -/** \brief Structure type to access the Instrumentation Trace Macrocell Register (ITM). + /** \brief Structure type to access the Instrumentation Trace Macrocell Register (ITM). */ -typedef struct -{ - __O union - { - __O uint8_t u8; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 8-bit */ - __O uint16_t u16; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 16-bit */ - __O uint32_t u32; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 32-bit */ - } PORT [32]; /*!< Offset: 0x000 ( /W) ITM Stimulus Port Registers */ - uint32_t RESERVED0[864]; - __IO uint32_t TER; /*!< Offset: 0xE00 (R/W) ITM Trace Enable Register */ - uint32_t RESERVED1[15]; - __IO uint32_t TPR; /*!< Offset: 0xE40 (R/W) ITM Trace Privilege Register */ - uint32_t RESERVED2[15]; - __IO uint32_t TCR; /*!< Offset: 0xE80 (R/W) ITM Trace Control Register */ - uint32_t RESERVED3[29]; - __O uint32_t IWR; /*!< Offset: 0xEF8 ( /W) ITM Integration Write Register */ - __I uint32_t IRR; /*!< Offset: 0xEFC (R/ ) ITM Integration Read Register */ - __IO uint32_t IMCR; /*!< Offset: 0xF00 (R/W) ITM Integration Mode Control Register */ - uint32_t RESERVED4[43]; - __O uint32_t LAR; /*!< Offset: 0xFB0 ( /W) ITM Lock Access Register */ - __I uint32_t LSR; /*!< Offset: 0xFB4 (R/ ) ITM Lock Status Register */ - uint32_t RESERVED5[6]; - __I uint32_t PID4; /*!< Offset: 0xFD0 (R/ ) ITM Peripheral Identification Register #4 */ - __I uint32_t PID5; /*!< Offset: 0xFD4 (R/ ) ITM Peripheral Identification Register #5 */ - __I uint32_t PID6; /*!< Offset: 0xFD8 (R/ ) ITM Peripheral Identification Register #6 */ - __I uint32_t PID7; /*!< Offset: 0xFDC (R/ ) ITM Peripheral Identification Register #7 */ - __I uint32_t PID0; /*!< Offset: 0xFE0 (R/ ) ITM Peripheral Identification Register #0 */ - __I uint32_t PID1; /*!< Offset: 0xFE4 (R/ ) ITM Peripheral Identification Register #1 */ - __I uint32_t PID2; /*!< Offset: 0xFE8 (R/ ) ITM Peripheral Identification Register #2 */ - __I uint32_t PID3; /*!< Offset: 0xFEC (R/ ) ITM Peripheral Identification Register #3 */ - __I uint32_t CID0; /*!< Offset: 0xFF0 (R/ ) ITM Component Identification Register #0 */ - __I uint32_t CID1; /*!< Offset: 0xFF4 (R/ ) ITM Component Identification Register #1 */ - __I uint32_t CID2; /*!< Offset: 0xFF8 (R/ ) ITM Component Identification Register #2 */ - __I uint32_t CID3; /*!< Offset: 0xFFC (R/ ) ITM Component Identification Register #3 */ -} ITM_Type; + typedef struct + { + __O union + { + __O uint8_t u8; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 8-bit */ + __O uint16_t u16; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 16-bit */ + __O uint32_t u32; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 32-bit */ + } PORT[32]; /*!< Offset: 0x000 ( /W) ITM Stimulus Port Registers */ + uint32_t RESERVED0[864]; + __IO uint32_t TER; /*!< Offset: 0xE00 (R/W) ITM Trace Enable Register */ + uint32_t RESERVED1[15]; + __IO uint32_t TPR; /*!< Offset: 0xE40 (R/W) ITM Trace Privilege Register */ + uint32_t RESERVED2[15]; + __IO uint32_t TCR; /*!< Offset: 0xE80 (R/W) ITM Trace Control Register */ + uint32_t RESERVED3[29]; + __O uint32_t IWR; /*!< Offset: 0xEF8 ( /W) ITM Integration Write Register */ + __I uint32_t IRR; /*!< Offset: 0xEFC (R/ ) ITM Integration Read Register */ + __IO uint32_t IMCR; /*!< Offset: 0xF00 (R/W) ITM Integration Mode Control Register */ + uint32_t RESERVED4[43]; + __O uint32_t LAR; /*!< Offset: 0xFB0 ( /W) ITM Lock Access Register */ + __I uint32_t LSR; /*!< Offset: 0xFB4 (R/ ) ITM Lock Status Register */ + uint32_t RESERVED5[6]; + __I uint32_t PID4; /*!< Offset: 0xFD0 (R/ ) ITM Peripheral Identification Register #4 */ + __I uint32_t PID5; /*!< Offset: 0xFD4 (R/ ) ITM Peripheral Identification Register #5 */ + __I uint32_t PID6; /*!< Offset: 0xFD8 (R/ ) ITM Peripheral Identification Register #6 */ + __I uint32_t PID7; /*!< Offset: 0xFDC (R/ ) ITM Peripheral Identification Register #7 */ + __I uint32_t PID0; /*!< Offset: 0xFE0 (R/ ) ITM Peripheral Identification Register #0 */ + __I uint32_t PID1; /*!< Offset: 0xFE4 (R/ ) ITM Peripheral Identification Register #1 */ + __I uint32_t PID2; /*!< Offset: 0xFE8 (R/ ) ITM Peripheral Identification Register #2 */ + __I uint32_t PID3; /*!< Offset: 0xFEC (R/ ) ITM Peripheral Identification Register #3 */ + __I uint32_t CID0; /*!< Offset: 0xFF0 (R/ ) ITM Component Identification Register #0 */ + __I uint32_t CID1; /*!< Offset: 0xFF4 (R/ ) ITM Component Identification Register #1 */ + __I uint32_t CID2; /*!< Offset: 0xFF8 (R/ ) ITM Component Identification Register #2 */ + __I uint32_t CID3; /*!< Offset: 0xFFC (R/ ) ITM Component Identification Register #3 */ + } ITM_Type; /* ITM Trace Privilege Register Definitions */ -#define ITM_TPR_PRIVMASK_Pos 0 /*!< ITM TPR: PRIVMASK Position */ -#define ITM_TPR_PRIVMASK_Msk (0xFUL << ITM_TPR_PRIVMASK_Pos) /*!< ITM TPR: PRIVMASK Mask */ +#define ITM_TPR_PRIVMASK_Pos 0 /*!< ITM TPR: PRIVMASK Position */ +#define ITM_TPR_PRIVMASK_Msk (0xFUL << ITM_TPR_PRIVMASK_Pos) /*!< ITM TPR: PRIVMASK Mask */ /* ITM Trace Control Register Definitions */ -#define ITM_TCR_BUSY_Pos 23 /*!< ITM TCR: BUSY Position */ -#define ITM_TCR_BUSY_Msk (1UL << ITM_TCR_BUSY_Pos) /*!< ITM TCR: BUSY Mask */ +#define ITM_TCR_BUSY_Pos 23 /*!< ITM TCR: BUSY Position */ +#define ITM_TCR_BUSY_Msk (1UL << ITM_TCR_BUSY_Pos) /*!< ITM TCR: BUSY Mask */ -#define ITM_TCR_TraceBusID_Pos 16 /*!< ITM TCR: ATBID Position */ -#define ITM_TCR_TraceBusID_Msk (0x7FUL << ITM_TCR_TraceBusID_Pos) /*!< ITM TCR: ATBID Mask */ +#define ITM_TCR_TraceBusID_Pos 16 /*!< ITM TCR: ATBID Position */ +#define ITM_TCR_TraceBusID_Msk (0x7FUL << ITM_TCR_TraceBusID_Pos) /*!< ITM TCR: ATBID Mask */ -#define ITM_TCR_GTSFREQ_Pos 10 /*!< ITM TCR: Global timestamp frequency Position */ -#define ITM_TCR_GTSFREQ_Msk (3UL << ITM_TCR_GTSFREQ_Pos) /*!< ITM TCR: Global timestamp frequency Mask */ +#define ITM_TCR_GTSFREQ_Pos 10 /*!< ITM TCR: Global timestamp frequency Position */ +#define ITM_TCR_GTSFREQ_Msk (3UL << ITM_TCR_GTSFREQ_Pos) /*!< ITM TCR: Global timestamp frequency Mask */ -#define ITM_TCR_TSPrescale_Pos 8 /*!< ITM TCR: TSPrescale Position */ -#define ITM_TCR_TSPrescale_Msk (3UL << ITM_TCR_TSPrescale_Pos) /*!< ITM TCR: TSPrescale Mask */ +#define ITM_TCR_TSPrescale_Pos 8 /*!< ITM TCR: TSPrescale Position */ +#define ITM_TCR_TSPrescale_Msk (3UL << ITM_TCR_TSPrescale_Pos) /*!< ITM TCR: TSPrescale Mask */ -#define ITM_TCR_SWOENA_Pos 4 /*!< ITM TCR: SWOENA Position */ -#define ITM_TCR_SWOENA_Msk (1UL << ITM_TCR_SWOENA_Pos) /*!< ITM TCR: SWOENA Mask */ +#define ITM_TCR_SWOENA_Pos 4 /*!< ITM TCR: SWOENA Position */ +#define ITM_TCR_SWOENA_Msk (1UL << ITM_TCR_SWOENA_Pos) /*!< ITM TCR: SWOENA Mask */ -#define ITM_TCR_DWTENA_Pos 3 /*!< ITM TCR: DWTENA Position */ -#define ITM_TCR_DWTENA_Msk (1UL << ITM_TCR_DWTENA_Pos) /*!< ITM TCR: DWTENA Mask */ +#define ITM_TCR_DWTENA_Pos 3 /*!< ITM TCR: DWTENA Position */ +#define ITM_TCR_DWTENA_Msk (1UL << ITM_TCR_DWTENA_Pos) /*!< ITM TCR: DWTENA Mask */ -#define ITM_TCR_SYNCENA_Pos 2 /*!< ITM TCR: SYNCENA Position */ -#define ITM_TCR_SYNCENA_Msk (1UL << ITM_TCR_SYNCENA_Pos) /*!< ITM TCR: SYNCENA Mask */ +#define ITM_TCR_SYNCENA_Pos 2 /*!< ITM TCR: SYNCENA Position */ +#define ITM_TCR_SYNCENA_Msk (1UL << ITM_TCR_SYNCENA_Pos) /*!< ITM TCR: SYNCENA Mask */ -#define ITM_TCR_TSENA_Pos 1 /*!< ITM TCR: TSENA Position */ -#define ITM_TCR_TSENA_Msk (1UL << ITM_TCR_TSENA_Pos) /*!< ITM TCR: TSENA Mask */ +#define ITM_TCR_TSENA_Pos 1 /*!< ITM TCR: TSENA Position */ +#define ITM_TCR_TSENA_Msk (1UL << ITM_TCR_TSENA_Pos) /*!< ITM TCR: TSENA Mask */ -#define ITM_TCR_ITMENA_Pos 0 /*!< ITM TCR: ITM Enable bit Position */ -#define ITM_TCR_ITMENA_Msk (1UL << ITM_TCR_ITMENA_Pos) /*!< ITM TCR: ITM Enable bit Mask */ +#define ITM_TCR_ITMENA_Pos 0 /*!< ITM TCR: ITM Enable bit Position */ +#define ITM_TCR_ITMENA_Msk (1UL << ITM_TCR_ITMENA_Pos) /*!< ITM TCR: ITM Enable bit Mask */ /* ITM Integration Write Register Definitions */ -#define ITM_IWR_ATVALIDM_Pos 0 /*!< ITM IWR: ATVALIDM Position */ -#define ITM_IWR_ATVALIDM_Msk (1UL << ITM_IWR_ATVALIDM_Pos) /*!< ITM IWR: ATVALIDM Mask */ +#define ITM_IWR_ATVALIDM_Pos 0 /*!< ITM IWR: ATVALIDM Position */ +#define ITM_IWR_ATVALIDM_Msk (1UL << ITM_IWR_ATVALIDM_Pos) /*!< ITM IWR: ATVALIDM Mask */ /* ITM Integration Read Register Definitions */ -#define ITM_IRR_ATREADYM_Pos 0 /*!< ITM IRR: ATREADYM Position */ -#define ITM_IRR_ATREADYM_Msk (1UL << ITM_IRR_ATREADYM_Pos) /*!< ITM IRR: ATREADYM Mask */ +#define ITM_IRR_ATREADYM_Pos 0 /*!< ITM IRR: ATREADYM Position */ +#define ITM_IRR_ATREADYM_Msk (1UL << ITM_IRR_ATREADYM_Pos) /*!< ITM IRR: ATREADYM Mask */ /* ITM Integration Mode Control Register Definitions */ -#define ITM_IMCR_INTEGRATION_Pos 0 /*!< ITM IMCR: INTEGRATION Position */ -#define ITM_IMCR_INTEGRATION_Msk (1UL << ITM_IMCR_INTEGRATION_Pos) /*!< ITM IMCR: INTEGRATION Mask */ +#define ITM_IMCR_INTEGRATION_Pos 0 /*!< ITM IMCR: INTEGRATION Position */ +#define ITM_IMCR_INTEGRATION_Msk (1UL << ITM_IMCR_INTEGRATION_Pos) /*!< ITM IMCR: INTEGRATION Mask */ /* ITM Lock Status Register Definitions */ -#define ITM_LSR_ByteAcc_Pos 2 /*!< ITM LSR: ByteAcc Position */ -#define ITM_LSR_ByteAcc_Msk (1UL << ITM_LSR_ByteAcc_Pos) /*!< ITM LSR: ByteAcc Mask */ - -#define ITM_LSR_Access_Pos 1 /*!< ITM LSR: Access Position */ -#define ITM_LSR_Access_Msk (1UL << ITM_LSR_Access_Pos) /*!< ITM LSR: Access Mask */ +#define ITM_LSR_ByteAcc_Pos 2 /*!< ITM LSR: ByteAcc Position */ +#define ITM_LSR_ByteAcc_Msk (1UL << ITM_LSR_ByteAcc_Pos) /*!< ITM LSR: ByteAcc Mask */ -#define ITM_LSR_Present_Pos 0 /*!< ITM LSR: Present Position */ -#define ITM_LSR_Present_Msk (1UL << ITM_LSR_Present_Pos) /*!< ITM LSR: Present Mask */ +#define ITM_LSR_Access_Pos 1 /*!< ITM LSR: Access Position */ +#define ITM_LSR_Access_Msk (1UL << ITM_LSR_Access_Pos) /*!< ITM LSR: Access Mask */ -/*@}*/ /* end of group CMSIS_ITM */ +#define ITM_LSR_Present_Pos 0 /*!< ITM LSR: Present Position */ +#define ITM_LSR_Present_Msk (1UL << ITM_LSR_Present_Pos) /*!< ITM LSR: Present Mask */ + /*@}*/ /* end of group CMSIS_ITM */ -/** \ingroup CMSIS_core_register + /** \ingroup CMSIS_core_register \defgroup CMSIS_DWT Data Watchpoint and Trace (DWT) \brief Type definitions for the Data Watchpoint and Trace (DWT) @{ */ -/** \brief Structure type to access the Data Watchpoint and Trace Register (DWT). + /** \brief Structure type to access the Data Watchpoint and Trace Register (DWT). */ -typedef struct -{ - __IO uint32_t CTRL; /*!< Offset: 0x000 (R/W) Control Register */ - __IO uint32_t CYCCNT; /*!< Offset: 0x004 (R/W) Cycle Count Register */ - __IO uint32_t CPICNT; /*!< Offset: 0x008 (R/W) CPI Count Register */ - __IO uint32_t EXCCNT; /*!< Offset: 0x00C (R/W) Exception Overhead Count Register */ - __IO uint32_t SLEEPCNT; /*!< Offset: 0x010 (R/W) Sleep Count Register */ - __IO uint32_t LSUCNT; /*!< Offset: 0x014 (R/W) LSU Count Register */ - __IO uint32_t FOLDCNT; /*!< Offset: 0x018 (R/W) Folded-instruction Count Register */ - __I uint32_t PCSR; /*!< Offset: 0x01C (R/ ) Program Counter Sample Register */ - __IO uint32_t COMP0; /*!< Offset: 0x020 (R/W) Comparator Register 0 */ - __IO uint32_t MASK0; /*!< Offset: 0x024 (R/W) Mask Register 0 */ - __IO uint32_t FUNCTION0; /*!< Offset: 0x028 (R/W) Function Register 0 */ - uint32_t RESERVED0[1]; - __IO uint32_t COMP1; /*!< Offset: 0x030 (R/W) Comparator Register 1 */ - __IO uint32_t MASK1; /*!< Offset: 0x034 (R/W) Mask Register 1 */ - __IO uint32_t FUNCTION1; /*!< Offset: 0x038 (R/W) Function Register 1 */ - uint32_t RESERVED1[1]; - __IO uint32_t COMP2; /*!< Offset: 0x040 (R/W) Comparator Register 2 */ - __IO uint32_t MASK2; /*!< Offset: 0x044 (R/W) Mask Register 2 */ - __IO uint32_t FUNCTION2; /*!< Offset: 0x048 (R/W) Function Register 2 */ - uint32_t RESERVED2[1]; - __IO uint32_t COMP3; /*!< Offset: 0x050 (R/W) Comparator Register 3 */ - __IO uint32_t MASK3; /*!< Offset: 0x054 (R/W) Mask Register 3 */ - __IO uint32_t FUNCTION3; /*!< Offset: 0x058 (R/W) Function Register 3 */ -} DWT_Type; + typedef struct + { + __IO uint32_t CTRL; /*!< Offset: 0x000 (R/W) Control Register */ + __IO uint32_t CYCCNT; /*!< Offset: 0x004 (R/W) Cycle Count Register */ + __IO uint32_t CPICNT; /*!< Offset: 0x008 (R/W) CPI Count Register */ + __IO uint32_t EXCCNT; /*!< Offset: 0x00C (R/W) Exception Overhead Count Register */ + __IO uint32_t SLEEPCNT; /*!< Offset: 0x010 (R/W) Sleep Count Register */ + __IO uint32_t LSUCNT; /*!< Offset: 0x014 (R/W) LSU Count Register */ + __IO uint32_t FOLDCNT; /*!< Offset: 0x018 (R/W) Folded-instruction Count Register */ + __I uint32_t PCSR; /*!< Offset: 0x01C (R/ ) Program Counter Sample Register */ + __IO uint32_t COMP0; /*!< Offset: 0x020 (R/W) Comparator Register 0 */ + __IO uint32_t MASK0; /*!< Offset: 0x024 (R/W) Mask Register 0 */ + __IO uint32_t FUNCTION0; /*!< Offset: 0x028 (R/W) Function Register 0 */ + uint32_t RESERVED0[1]; + __IO uint32_t COMP1; /*!< Offset: 0x030 (R/W) Comparator Register 1 */ + __IO uint32_t MASK1; /*!< Offset: 0x034 (R/W) Mask Register 1 */ + __IO uint32_t FUNCTION1; /*!< Offset: 0x038 (R/W) Function Register 1 */ + uint32_t RESERVED1[1]; + __IO uint32_t COMP2; /*!< Offset: 0x040 (R/W) Comparator Register 2 */ + __IO uint32_t MASK2; /*!< Offset: 0x044 (R/W) Mask Register 2 */ + __IO uint32_t FUNCTION2; /*!< Offset: 0x048 (R/W) Function Register 2 */ + uint32_t RESERVED2[1]; + __IO uint32_t COMP3; /*!< Offset: 0x050 (R/W) Comparator Register 3 */ + __IO uint32_t MASK3; /*!< Offset: 0x054 (R/W) Mask Register 3 */ + __IO uint32_t FUNCTION3; /*!< Offset: 0x058 (R/W) Function Register 3 */ + } DWT_Type; /* DWT Control Register Definitions */ -#define DWT_CTRL_NUMCOMP_Pos 28 /*!< DWT CTRL: NUMCOMP Position */ -#define DWT_CTRL_NUMCOMP_Msk (0xFUL << DWT_CTRL_NUMCOMP_Pos) /*!< DWT CTRL: NUMCOMP Mask */ +#define DWT_CTRL_NUMCOMP_Pos 28 /*!< DWT CTRL: NUMCOMP Position */ +#define DWT_CTRL_NUMCOMP_Msk (0xFUL << DWT_CTRL_NUMCOMP_Pos) /*!< DWT CTRL: NUMCOMP Mask */ -#define DWT_CTRL_NOTRCPKT_Pos 27 /*!< DWT CTRL: NOTRCPKT Position */ -#define DWT_CTRL_NOTRCPKT_Msk (0x1UL << DWT_CTRL_NOTRCPKT_Pos) /*!< DWT CTRL: NOTRCPKT Mask */ +#define DWT_CTRL_NOTRCPKT_Pos 27 /*!< DWT CTRL: NOTRCPKT Position */ +#define DWT_CTRL_NOTRCPKT_Msk (0x1UL << DWT_CTRL_NOTRCPKT_Pos) /*!< DWT CTRL: NOTRCPKT Mask */ -#define DWT_CTRL_NOEXTTRIG_Pos 26 /*!< DWT CTRL: NOEXTTRIG Position */ -#define DWT_CTRL_NOEXTTRIG_Msk (0x1UL << DWT_CTRL_NOEXTTRIG_Pos) /*!< DWT CTRL: NOEXTTRIG Mask */ +#define DWT_CTRL_NOEXTTRIG_Pos 26 /*!< DWT CTRL: NOEXTTRIG Position */ +#define DWT_CTRL_NOEXTTRIG_Msk (0x1UL << DWT_CTRL_NOEXTTRIG_Pos) /*!< DWT CTRL: NOEXTTRIG Mask */ -#define DWT_CTRL_NOCYCCNT_Pos 25 /*!< DWT CTRL: NOCYCCNT Position */ -#define DWT_CTRL_NOCYCCNT_Msk (0x1UL << DWT_CTRL_NOCYCCNT_Pos) /*!< DWT CTRL: NOCYCCNT Mask */ +#define DWT_CTRL_NOCYCCNT_Pos 25 /*!< DWT CTRL: NOCYCCNT Position */ +#define DWT_CTRL_NOCYCCNT_Msk (0x1UL << DWT_CTRL_NOCYCCNT_Pos) /*!< DWT CTRL: NOCYCCNT Mask */ -#define DWT_CTRL_NOPRFCNT_Pos 24 /*!< DWT CTRL: NOPRFCNT Position */ -#define DWT_CTRL_NOPRFCNT_Msk (0x1UL << DWT_CTRL_NOPRFCNT_Pos) /*!< DWT CTRL: NOPRFCNT Mask */ +#define DWT_CTRL_NOPRFCNT_Pos 24 /*!< DWT CTRL: NOPRFCNT Position */ +#define DWT_CTRL_NOPRFCNT_Msk (0x1UL << DWT_CTRL_NOPRFCNT_Pos) /*!< DWT CTRL: NOPRFCNT Mask */ -#define DWT_CTRL_CYCEVTENA_Pos 22 /*!< DWT CTRL: CYCEVTENA Position */ -#define DWT_CTRL_CYCEVTENA_Msk (0x1UL << DWT_CTRL_CYCEVTENA_Pos) /*!< DWT CTRL: CYCEVTENA Mask */ +#define DWT_CTRL_CYCEVTENA_Pos 22 /*!< DWT CTRL: CYCEVTENA Position */ +#define DWT_CTRL_CYCEVTENA_Msk (0x1UL << DWT_CTRL_CYCEVTENA_Pos) /*!< DWT CTRL: CYCEVTENA Mask */ -#define DWT_CTRL_FOLDEVTENA_Pos 21 /*!< DWT CTRL: FOLDEVTENA Position */ -#define DWT_CTRL_FOLDEVTENA_Msk (0x1UL << DWT_CTRL_FOLDEVTENA_Pos) /*!< DWT CTRL: FOLDEVTENA Mask */ +#define DWT_CTRL_FOLDEVTENA_Pos 21 /*!< DWT CTRL: FOLDEVTENA Position */ +#define DWT_CTRL_FOLDEVTENA_Msk (0x1UL << DWT_CTRL_FOLDEVTENA_Pos) /*!< DWT CTRL: FOLDEVTENA Mask */ -#define DWT_CTRL_LSUEVTENA_Pos 20 /*!< DWT CTRL: LSUEVTENA Position */ -#define DWT_CTRL_LSUEVTENA_Msk (0x1UL << DWT_CTRL_LSUEVTENA_Pos) /*!< DWT CTRL: LSUEVTENA Mask */ +#define DWT_CTRL_LSUEVTENA_Pos 20 /*!< DWT CTRL: LSUEVTENA Position */ +#define DWT_CTRL_LSUEVTENA_Msk (0x1UL << DWT_CTRL_LSUEVTENA_Pos) /*!< DWT CTRL: LSUEVTENA Mask */ -#define DWT_CTRL_SLEEPEVTENA_Pos 19 /*!< DWT CTRL: SLEEPEVTENA Position */ -#define DWT_CTRL_SLEEPEVTENA_Msk (0x1UL << DWT_CTRL_SLEEPEVTENA_Pos) /*!< DWT CTRL: SLEEPEVTENA Mask */ +#define DWT_CTRL_SLEEPEVTENA_Pos 19 /*!< DWT CTRL: SLEEPEVTENA Position */ +#define DWT_CTRL_SLEEPEVTENA_Msk (0x1UL << DWT_CTRL_SLEEPEVTENA_Pos) /*!< DWT CTRL: SLEEPEVTENA Mask */ -#define DWT_CTRL_EXCEVTENA_Pos 18 /*!< DWT CTRL: EXCEVTENA Position */ -#define DWT_CTRL_EXCEVTENA_Msk (0x1UL << DWT_CTRL_EXCEVTENA_Pos) /*!< DWT CTRL: EXCEVTENA Mask */ +#define DWT_CTRL_EXCEVTENA_Pos 18 /*!< DWT CTRL: EXCEVTENA Position */ +#define DWT_CTRL_EXCEVTENA_Msk (0x1UL << DWT_CTRL_EXCEVTENA_Pos) /*!< DWT CTRL: EXCEVTENA Mask */ -#define DWT_CTRL_CPIEVTENA_Pos 17 /*!< DWT CTRL: CPIEVTENA Position */ -#define DWT_CTRL_CPIEVTENA_Msk (0x1UL << DWT_CTRL_CPIEVTENA_Pos) /*!< DWT CTRL: CPIEVTENA Mask */ +#define DWT_CTRL_CPIEVTENA_Pos 17 /*!< DWT CTRL: CPIEVTENA Position */ +#define DWT_CTRL_CPIEVTENA_Msk (0x1UL << DWT_CTRL_CPIEVTENA_Pos) /*!< DWT CTRL: CPIEVTENA Mask */ -#define DWT_CTRL_EXCTRCENA_Pos 16 /*!< DWT CTRL: EXCTRCENA Position */ -#define DWT_CTRL_EXCTRCENA_Msk (0x1UL << DWT_CTRL_EXCTRCENA_Pos) /*!< DWT CTRL: EXCTRCENA Mask */ +#define DWT_CTRL_EXCTRCENA_Pos 16 /*!< DWT CTRL: EXCTRCENA Position */ +#define DWT_CTRL_EXCTRCENA_Msk (0x1UL << DWT_CTRL_EXCTRCENA_Pos) /*!< DWT CTRL: EXCTRCENA Mask */ -#define DWT_CTRL_PCSAMPLENA_Pos 12 /*!< DWT CTRL: PCSAMPLENA Position */ -#define DWT_CTRL_PCSAMPLENA_Msk (0x1UL << DWT_CTRL_PCSAMPLENA_Pos) /*!< DWT CTRL: PCSAMPLENA Mask */ +#define DWT_CTRL_PCSAMPLENA_Pos 12 /*!< DWT CTRL: PCSAMPLENA Position */ +#define DWT_CTRL_PCSAMPLENA_Msk (0x1UL << DWT_CTRL_PCSAMPLENA_Pos) /*!< DWT CTRL: PCSAMPLENA Mask */ -#define DWT_CTRL_SYNCTAP_Pos 10 /*!< DWT CTRL: SYNCTAP Position */ -#define DWT_CTRL_SYNCTAP_Msk (0x3UL << DWT_CTRL_SYNCTAP_Pos) /*!< DWT CTRL: SYNCTAP Mask */ +#define DWT_CTRL_SYNCTAP_Pos 10 /*!< DWT CTRL: SYNCTAP Position */ +#define DWT_CTRL_SYNCTAP_Msk (0x3UL << DWT_CTRL_SYNCTAP_Pos) /*!< DWT CTRL: SYNCTAP Mask */ -#define DWT_CTRL_CYCTAP_Pos 9 /*!< DWT CTRL: CYCTAP Position */ -#define DWT_CTRL_CYCTAP_Msk (0x1UL << DWT_CTRL_CYCTAP_Pos) /*!< DWT CTRL: CYCTAP Mask */ +#define DWT_CTRL_CYCTAP_Pos 9 /*!< DWT CTRL: CYCTAP Position */ +#define DWT_CTRL_CYCTAP_Msk (0x1UL << DWT_CTRL_CYCTAP_Pos) /*!< DWT CTRL: CYCTAP Mask */ -#define DWT_CTRL_POSTINIT_Pos 5 /*!< DWT CTRL: POSTINIT Position */ -#define DWT_CTRL_POSTINIT_Msk (0xFUL << DWT_CTRL_POSTINIT_Pos) /*!< DWT CTRL: POSTINIT Mask */ +#define DWT_CTRL_POSTINIT_Pos 5 /*!< DWT CTRL: POSTINIT Position */ +#define DWT_CTRL_POSTINIT_Msk (0xFUL << DWT_CTRL_POSTINIT_Pos) /*!< DWT CTRL: POSTINIT Mask */ -#define DWT_CTRL_POSTPRESET_Pos 1 /*!< DWT CTRL: POSTPRESET Position */ -#define DWT_CTRL_POSTPRESET_Msk (0xFUL << DWT_CTRL_POSTPRESET_Pos) /*!< DWT CTRL: POSTPRESET Mask */ +#define DWT_CTRL_POSTPRESET_Pos 1 /*!< DWT CTRL: POSTPRESET Position */ +#define DWT_CTRL_POSTPRESET_Msk (0xFUL << DWT_CTRL_POSTPRESET_Pos) /*!< DWT CTRL: POSTPRESET Mask */ -#define DWT_CTRL_CYCCNTENA_Pos 0 /*!< DWT CTRL: CYCCNTENA Position */ -#define DWT_CTRL_CYCCNTENA_Msk (0x1UL << DWT_CTRL_CYCCNTENA_Pos) /*!< DWT CTRL: CYCCNTENA Mask */ +#define DWT_CTRL_CYCCNTENA_Pos 0 /*!< DWT CTRL: CYCCNTENA Position */ +#define DWT_CTRL_CYCCNTENA_Msk (0x1UL << DWT_CTRL_CYCCNTENA_Pos) /*!< DWT CTRL: CYCCNTENA Mask */ /* DWT CPI Count Register Definitions */ -#define DWT_CPICNT_CPICNT_Pos 0 /*!< DWT CPICNT: CPICNT Position */ -#define DWT_CPICNT_CPICNT_Msk (0xFFUL << DWT_CPICNT_CPICNT_Pos) /*!< DWT CPICNT: CPICNT Mask */ +#define DWT_CPICNT_CPICNT_Pos 0 /*!< DWT CPICNT: CPICNT Position */ +#define DWT_CPICNT_CPICNT_Msk (0xFFUL << DWT_CPICNT_CPICNT_Pos) /*!< DWT CPICNT: CPICNT Mask */ /* DWT Exception Overhead Count Register Definitions */ -#define DWT_EXCCNT_EXCCNT_Pos 0 /*!< DWT EXCCNT: EXCCNT Position */ -#define DWT_EXCCNT_EXCCNT_Msk (0xFFUL << DWT_EXCCNT_EXCCNT_Pos) /*!< DWT EXCCNT: EXCCNT Mask */ +#define DWT_EXCCNT_EXCCNT_Pos 0 /*!< DWT EXCCNT: EXCCNT Position */ +#define DWT_EXCCNT_EXCCNT_Msk (0xFFUL << DWT_EXCCNT_EXCCNT_Pos) /*!< DWT EXCCNT: EXCCNT Mask */ /* DWT Sleep Count Register Definitions */ -#define DWT_SLEEPCNT_SLEEPCNT_Pos 0 /*!< DWT SLEEPCNT: SLEEPCNT Position */ -#define DWT_SLEEPCNT_SLEEPCNT_Msk (0xFFUL << DWT_SLEEPCNT_SLEEPCNT_Pos) /*!< DWT SLEEPCNT: SLEEPCNT Mask */ +#define DWT_SLEEPCNT_SLEEPCNT_Pos 0 /*!< DWT SLEEPCNT: SLEEPCNT Position */ +#define DWT_SLEEPCNT_SLEEPCNT_Msk (0xFFUL << DWT_SLEEPCNT_SLEEPCNT_Pos) /*!< DWT SLEEPCNT: SLEEPCNT Mask */ /* DWT LSU Count Register Definitions */ -#define DWT_LSUCNT_LSUCNT_Pos 0 /*!< DWT LSUCNT: LSUCNT Position */ -#define DWT_LSUCNT_LSUCNT_Msk (0xFFUL << DWT_LSUCNT_LSUCNT_Pos) /*!< DWT LSUCNT: LSUCNT Mask */ +#define DWT_LSUCNT_LSUCNT_Pos 0 /*!< DWT LSUCNT: LSUCNT Position */ +#define DWT_LSUCNT_LSUCNT_Msk (0xFFUL << DWT_LSUCNT_LSUCNT_Pos) /*!< DWT LSUCNT: LSUCNT Mask */ /* DWT Folded-instruction Count Register Definitions */ -#define DWT_FOLDCNT_FOLDCNT_Pos 0 /*!< DWT FOLDCNT: FOLDCNT Position */ -#define DWT_FOLDCNT_FOLDCNT_Msk (0xFFUL << DWT_FOLDCNT_FOLDCNT_Pos) /*!< DWT FOLDCNT: FOLDCNT Mask */ +#define DWT_FOLDCNT_FOLDCNT_Pos 0 /*!< DWT FOLDCNT: FOLDCNT Position */ +#define DWT_FOLDCNT_FOLDCNT_Msk (0xFFUL << DWT_FOLDCNT_FOLDCNT_Pos) /*!< DWT FOLDCNT: FOLDCNT Mask */ /* DWT Comparator Mask Register Definitions */ -#define DWT_MASK_MASK_Pos 0 /*!< DWT MASK: MASK Position */ -#define DWT_MASK_MASK_Msk (0x1FUL << DWT_MASK_MASK_Pos) /*!< DWT MASK: MASK Mask */ +#define DWT_MASK_MASK_Pos 0 /*!< DWT MASK: MASK Position */ +#define DWT_MASK_MASK_Msk (0x1FUL << DWT_MASK_MASK_Pos) /*!< DWT MASK: MASK Mask */ /* DWT Comparator Function Register Definitions */ -#define DWT_FUNCTION_MATCHED_Pos 24 /*!< DWT FUNCTION: MATCHED Position */ -#define DWT_FUNCTION_MATCHED_Msk (0x1UL << DWT_FUNCTION_MATCHED_Pos) /*!< DWT FUNCTION: MATCHED Mask */ +#define DWT_FUNCTION_MATCHED_Pos 24 /*!< DWT FUNCTION: MATCHED Position */ +#define DWT_FUNCTION_MATCHED_Msk (0x1UL << DWT_FUNCTION_MATCHED_Pos) /*!< DWT FUNCTION: MATCHED Mask */ -#define DWT_FUNCTION_DATAVADDR1_Pos 16 /*!< DWT FUNCTION: DATAVADDR1 Position */ -#define DWT_FUNCTION_DATAVADDR1_Msk (0xFUL << DWT_FUNCTION_DATAVADDR1_Pos) /*!< DWT FUNCTION: DATAVADDR1 Mask */ +#define DWT_FUNCTION_DATAVADDR1_Pos 16 /*!< DWT FUNCTION: DATAVADDR1 Position */ +#define DWT_FUNCTION_DATAVADDR1_Msk (0xFUL << DWT_FUNCTION_DATAVADDR1_Pos) /*!< DWT FUNCTION: DATAVADDR1 Mask */ -#define DWT_FUNCTION_DATAVADDR0_Pos 12 /*!< DWT FUNCTION: DATAVADDR0 Position */ -#define DWT_FUNCTION_DATAVADDR0_Msk (0xFUL << DWT_FUNCTION_DATAVADDR0_Pos) /*!< DWT FUNCTION: DATAVADDR0 Mask */ +#define DWT_FUNCTION_DATAVADDR0_Pos 12 /*!< DWT FUNCTION: DATAVADDR0 Position */ +#define DWT_FUNCTION_DATAVADDR0_Msk (0xFUL << DWT_FUNCTION_DATAVADDR0_Pos) /*!< DWT FUNCTION: DATAVADDR0 Mask */ -#define DWT_FUNCTION_DATAVSIZE_Pos 10 /*!< DWT FUNCTION: DATAVSIZE Position */ -#define DWT_FUNCTION_DATAVSIZE_Msk (0x3UL << DWT_FUNCTION_DATAVSIZE_Pos) /*!< DWT FUNCTION: DATAVSIZE Mask */ +#define DWT_FUNCTION_DATAVSIZE_Pos 10 /*!< DWT FUNCTION: DATAVSIZE Position */ +#define DWT_FUNCTION_DATAVSIZE_Msk (0x3UL << DWT_FUNCTION_DATAVSIZE_Pos) /*!< DWT FUNCTION: DATAVSIZE Mask */ -#define DWT_FUNCTION_LNK1ENA_Pos 9 /*!< DWT FUNCTION: LNK1ENA Position */ -#define DWT_FUNCTION_LNK1ENA_Msk (0x1UL << DWT_FUNCTION_LNK1ENA_Pos) /*!< DWT FUNCTION: LNK1ENA Mask */ +#define DWT_FUNCTION_LNK1ENA_Pos 9 /*!< DWT FUNCTION: LNK1ENA Position */ +#define DWT_FUNCTION_LNK1ENA_Msk (0x1UL << DWT_FUNCTION_LNK1ENA_Pos) /*!< DWT FUNCTION: LNK1ENA Mask */ -#define DWT_FUNCTION_DATAVMATCH_Pos 8 /*!< DWT FUNCTION: DATAVMATCH Position */ -#define DWT_FUNCTION_DATAVMATCH_Msk (0x1UL << DWT_FUNCTION_DATAVMATCH_Pos) /*!< DWT FUNCTION: DATAVMATCH Mask */ +#define DWT_FUNCTION_DATAVMATCH_Pos 8 /*!< DWT FUNCTION: DATAVMATCH Position */ +#define DWT_FUNCTION_DATAVMATCH_Msk (0x1UL << DWT_FUNCTION_DATAVMATCH_Pos) /*!< DWT FUNCTION: DATAVMATCH Mask */ -#define DWT_FUNCTION_CYCMATCH_Pos 7 /*!< DWT FUNCTION: CYCMATCH Position */ -#define DWT_FUNCTION_CYCMATCH_Msk (0x1UL << DWT_FUNCTION_CYCMATCH_Pos) /*!< DWT FUNCTION: CYCMATCH Mask */ +#define DWT_FUNCTION_CYCMATCH_Pos 7 /*!< DWT FUNCTION: CYCMATCH Position */ +#define DWT_FUNCTION_CYCMATCH_Msk (0x1UL << DWT_FUNCTION_CYCMATCH_Pos) /*!< DWT FUNCTION: CYCMATCH Mask */ -#define DWT_FUNCTION_EMITRANGE_Pos 5 /*!< DWT FUNCTION: EMITRANGE Position */ -#define DWT_FUNCTION_EMITRANGE_Msk (0x1UL << DWT_FUNCTION_EMITRANGE_Pos) /*!< DWT FUNCTION: EMITRANGE Mask */ +#define DWT_FUNCTION_EMITRANGE_Pos 5 /*!< DWT FUNCTION: EMITRANGE Position */ +#define DWT_FUNCTION_EMITRANGE_Msk (0x1UL << DWT_FUNCTION_EMITRANGE_Pos) /*!< DWT FUNCTION: EMITRANGE Mask */ -#define DWT_FUNCTION_FUNCTION_Pos 0 /*!< DWT FUNCTION: FUNCTION Position */ -#define DWT_FUNCTION_FUNCTION_Msk (0xFUL << DWT_FUNCTION_FUNCTION_Pos) /*!< DWT FUNCTION: FUNCTION Mask */ +#define DWT_FUNCTION_FUNCTION_Pos 0 /*!< DWT FUNCTION: FUNCTION Position */ +#define DWT_FUNCTION_FUNCTION_Msk (0xFUL << DWT_FUNCTION_FUNCTION_Pos) /*!< DWT FUNCTION: FUNCTION Mask */ -/*@}*/ /* end of group CMSIS_DWT */ + /*@}*/ /* end of group CMSIS_DWT */ - -/** \ingroup CMSIS_core_register + /** \ingroup CMSIS_core_register \defgroup CMSIS_TPI Trace Port Interface (TPI) \brief Type definitions for the Trace Port Interface (TPI) @{ */ -/** \brief Structure type to access the Trace Port Interface Register (TPI). + /** \brief Structure type to access the Trace Port Interface Register (TPI). */ -typedef struct -{ - __IO uint32_t SSPSR; /*!< Offset: 0x000 (R/ ) Supported Parallel Port Size Register */ - __IO uint32_t CSPSR; /*!< Offset: 0x004 (R/W) Current Parallel Port Size Register */ - uint32_t RESERVED0[2]; - __IO uint32_t ACPR; /*!< Offset: 0x010 (R/W) Asynchronous Clock Prescaler Register */ - uint32_t RESERVED1[55]; - __IO uint32_t SPPR; /*!< Offset: 0x0F0 (R/W) Selected Pin Protocol Register */ - uint32_t RESERVED2[131]; - __I uint32_t FFSR; /*!< Offset: 0x300 (R/ ) Formatter and Flush Status Register */ - __IO uint32_t FFCR; /*!< Offset: 0x304 (R/W) Formatter and Flush Control Register */ - __I uint32_t FSCR; /*!< Offset: 0x308 (R/ ) Formatter Synchronization Counter Register */ - uint32_t RESERVED3[759]; - __I uint32_t TRIGGER; /*!< Offset: 0xEE8 (R/ ) TRIGGER */ - __I uint32_t FIFO0; /*!< Offset: 0xEEC (R/ ) Integration ETM Data */ - __I uint32_t ITATBCTR2; /*!< Offset: 0xEF0 (R/ ) ITATBCTR2 */ - uint32_t RESERVED4[1]; - __I uint32_t ITATBCTR0; /*!< Offset: 0xEF8 (R/ ) ITATBCTR0 */ - __I uint32_t FIFO1; /*!< Offset: 0xEFC (R/ ) Integration ITM Data */ - __IO uint32_t ITCTRL; /*!< Offset: 0xF00 (R/W) Integration Mode Control */ - uint32_t RESERVED5[39]; - __IO uint32_t CLAIMSET; /*!< Offset: 0xFA0 (R/W) Claim tag set */ - __IO uint32_t CLAIMCLR; /*!< Offset: 0xFA4 (R/W) Claim tag clear */ - uint32_t RESERVED7[8]; - __I uint32_t DEVID; /*!< Offset: 0xFC8 (R/ ) TPIU_DEVID */ - __I uint32_t DEVTYPE; /*!< Offset: 0xFCC (R/ ) TPIU_DEVTYPE */ -} TPI_Type; + typedef struct + { + __IO uint32_t SSPSR; /*!< Offset: 0x000 (R/ ) Supported Parallel Port Size Register */ + __IO uint32_t CSPSR; /*!< Offset: 0x004 (R/W) Current Parallel Port Size Register */ + uint32_t RESERVED0[2]; + __IO uint32_t ACPR; /*!< Offset: 0x010 (R/W) Asynchronous Clock Prescaler Register */ + uint32_t RESERVED1[55]; + __IO uint32_t SPPR; /*!< Offset: 0x0F0 (R/W) Selected Pin Protocol Register */ + uint32_t RESERVED2[131]; + __I uint32_t FFSR; /*!< Offset: 0x300 (R/ ) Formatter and Flush Status Register */ + __IO uint32_t FFCR; /*!< Offset: 0x304 (R/W) Formatter and Flush Control Register */ + __I uint32_t FSCR; /*!< Offset: 0x308 (R/ ) Formatter Synchronization Counter Register */ + uint32_t RESERVED3[759]; + __I uint32_t TRIGGER; /*!< Offset: 0xEE8 (R/ ) TRIGGER */ + __I uint32_t FIFO0; /*!< Offset: 0xEEC (R/ ) Integration ETM Data */ + __I uint32_t ITATBCTR2; /*!< Offset: 0xEF0 (R/ ) ITATBCTR2 */ + uint32_t RESERVED4[1]; + __I uint32_t ITATBCTR0; /*!< Offset: 0xEF8 (R/ ) ITATBCTR0 */ + __I uint32_t FIFO1; /*!< Offset: 0xEFC (R/ ) Integration ITM Data */ + __IO uint32_t ITCTRL; /*!< Offset: 0xF00 (R/W) Integration Mode Control */ + uint32_t RESERVED5[39]; + __IO uint32_t CLAIMSET; /*!< Offset: 0xFA0 (R/W) Claim tag set */ + __IO uint32_t CLAIMCLR; /*!< Offset: 0xFA4 (R/W) Claim tag clear */ + uint32_t RESERVED7[8]; + __I uint32_t DEVID; /*!< Offset: 0xFC8 (R/ ) TPIU_DEVID */ + __I uint32_t DEVTYPE; /*!< Offset: 0xFCC (R/ ) TPIU_DEVTYPE */ + } TPI_Type; /* TPI Asynchronous Clock Prescaler Register Definitions */ -#define TPI_ACPR_PRESCALER_Pos 0 /*!< TPI ACPR: PRESCALER Position */ -#define TPI_ACPR_PRESCALER_Msk (0x1FFFUL << TPI_ACPR_PRESCALER_Pos) /*!< TPI ACPR: PRESCALER Mask */ +#define TPI_ACPR_PRESCALER_Pos 0 /*!< TPI ACPR: PRESCALER Position */ +#define TPI_ACPR_PRESCALER_Msk (0x1FFFUL << TPI_ACPR_PRESCALER_Pos) /*!< TPI ACPR: PRESCALER Mask */ /* TPI Selected Pin Protocol Register Definitions */ -#define TPI_SPPR_TXMODE_Pos 0 /*!< TPI SPPR: TXMODE Position */ -#define TPI_SPPR_TXMODE_Msk (0x3UL << TPI_SPPR_TXMODE_Pos) /*!< TPI SPPR: TXMODE Mask */ +#define TPI_SPPR_TXMODE_Pos 0 /*!< TPI SPPR: TXMODE Position */ +#define TPI_SPPR_TXMODE_Msk (0x3UL << TPI_SPPR_TXMODE_Pos) /*!< TPI SPPR: TXMODE Mask */ /* TPI Formatter and Flush Status Register Definitions */ -#define TPI_FFSR_FtNonStop_Pos 3 /*!< TPI FFSR: FtNonStop Position */ -#define TPI_FFSR_FtNonStop_Msk (0x1UL << TPI_FFSR_FtNonStop_Pos) /*!< TPI FFSR: FtNonStop Mask */ +#define TPI_FFSR_FtNonStop_Pos 3 /*!< TPI FFSR: FtNonStop Position */ +#define TPI_FFSR_FtNonStop_Msk (0x1UL << TPI_FFSR_FtNonStop_Pos) /*!< TPI FFSR: FtNonStop Mask */ -#define TPI_FFSR_TCPresent_Pos 2 /*!< TPI FFSR: TCPresent Position */ -#define TPI_FFSR_TCPresent_Msk (0x1UL << TPI_FFSR_TCPresent_Pos) /*!< TPI FFSR: TCPresent Mask */ +#define TPI_FFSR_TCPresent_Pos 2 /*!< TPI FFSR: TCPresent Position */ +#define TPI_FFSR_TCPresent_Msk (0x1UL << TPI_FFSR_TCPresent_Pos) /*!< TPI FFSR: TCPresent Mask */ -#define TPI_FFSR_FtStopped_Pos 1 /*!< TPI FFSR: FtStopped Position */ -#define TPI_FFSR_FtStopped_Msk (0x1UL << TPI_FFSR_FtStopped_Pos) /*!< TPI FFSR: FtStopped Mask */ +#define TPI_FFSR_FtStopped_Pos 1 /*!< TPI FFSR: FtStopped Position */ +#define TPI_FFSR_FtStopped_Msk (0x1UL << TPI_FFSR_FtStopped_Pos) /*!< TPI FFSR: FtStopped Mask */ -#define TPI_FFSR_FlInProg_Pos 0 /*!< TPI FFSR: FlInProg Position */ -#define TPI_FFSR_FlInProg_Msk (0x1UL << TPI_FFSR_FlInProg_Pos) /*!< TPI FFSR: FlInProg Mask */ +#define TPI_FFSR_FlInProg_Pos 0 /*!< TPI FFSR: FlInProg Position */ +#define TPI_FFSR_FlInProg_Msk (0x1UL << TPI_FFSR_FlInProg_Pos) /*!< TPI FFSR: FlInProg Mask */ /* TPI Formatter and Flush Control Register Definitions */ -#define TPI_FFCR_TrigIn_Pos 8 /*!< TPI FFCR: TrigIn Position */ -#define TPI_FFCR_TrigIn_Msk (0x1UL << TPI_FFCR_TrigIn_Pos) /*!< TPI FFCR: TrigIn Mask */ +#define TPI_FFCR_TrigIn_Pos 8 /*!< TPI FFCR: TrigIn Position */ +#define TPI_FFCR_TrigIn_Msk (0x1UL << TPI_FFCR_TrigIn_Pos) /*!< TPI FFCR: TrigIn Mask */ -#define TPI_FFCR_EnFCont_Pos 1 /*!< TPI FFCR: EnFCont Position */ -#define TPI_FFCR_EnFCont_Msk (0x1UL << TPI_FFCR_EnFCont_Pos) /*!< TPI FFCR: EnFCont Mask */ +#define TPI_FFCR_EnFCont_Pos 1 /*!< TPI FFCR: EnFCont Position */ +#define TPI_FFCR_EnFCont_Msk (0x1UL << TPI_FFCR_EnFCont_Pos) /*!< TPI FFCR: EnFCont Mask */ /* TPI TRIGGER Register Definitions */ -#define TPI_TRIGGER_TRIGGER_Pos 0 /*!< TPI TRIGGER: TRIGGER Position */ -#define TPI_TRIGGER_TRIGGER_Msk (0x1UL << TPI_TRIGGER_TRIGGER_Pos) /*!< TPI TRIGGER: TRIGGER Mask */ +#define TPI_TRIGGER_TRIGGER_Pos 0 /*!< TPI TRIGGER: TRIGGER Position */ +#define TPI_TRIGGER_TRIGGER_Msk (0x1UL << TPI_TRIGGER_TRIGGER_Pos) /*!< TPI TRIGGER: TRIGGER Mask */ /* TPI Integration ETM Data Register Definitions (FIFO0) */ -#define TPI_FIFO0_ITM_ATVALID_Pos 29 /*!< TPI FIFO0: ITM_ATVALID Position */ -#define TPI_FIFO0_ITM_ATVALID_Msk (0x3UL << TPI_FIFO0_ITM_ATVALID_Pos) /*!< TPI FIFO0: ITM_ATVALID Mask */ +#define TPI_FIFO0_ITM_ATVALID_Pos 29 /*!< TPI FIFO0: ITM_ATVALID Position */ +#define TPI_FIFO0_ITM_ATVALID_Msk (0x3UL << TPI_FIFO0_ITM_ATVALID_Pos) /*!< TPI FIFO0: ITM_ATVALID Mask */ -#define TPI_FIFO0_ITM_bytecount_Pos 27 /*!< TPI FIFO0: ITM_bytecount Position */ -#define TPI_FIFO0_ITM_bytecount_Msk (0x3UL << TPI_FIFO0_ITM_bytecount_Pos) /*!< TPI FIFO0: ITM_bytecount Mask */ +#define TPI_FIFO0_ITM_bytecount_Pos 27 /*!< TPI FIFO0: ITM_bytecount Position */ +#define TPI_FIFO0_ITM_bytecount_Msk (0x3UL << TPI_FIFO0_ITM_bytecount_Pos) /*!< TPI FIFO0: ITM_bytecount Mask */ -#define TPI_FIFO0_ETM_ATVALID_Pos 26 /*!< TPI FIFO0: ETM_ATVALID Position */ -#define TPI_FIFO0_ETM_ATVALID_Msk (0x3UL << TPI_FIFO0_ETM_ATVALID_Pos) /*!< TPI FIFO0: ETM_ATVALID Mask */ +#define TPI_FIFO0_ETM_ATVALID_Pos 26 /*!< TPI FIFO0: ETM_ATVALID Position */ +#define TPI_FIFO0_ETM_ATVALID_Msk (0x3UL << TPI_FIFO0_ETM_ATVALID_Pos) /*!< TPI FIFO0: ETM_ATVALID Mask */ -#define TPI_FIFO0_ETM_bytecount_Pos 24 /*!< TPI FIFO0: ETM_bytecount Position */ -#define TPI_FIFO0_ETM_bytecount_Msk (0x3UL << TPI_FIFO0_ETM_bytecount_Pos) /*!< TPI FIFO0: ETM_bytecount Mask */ +#define TPI_FIFO0_ETM_bytecount_Pos 24 /*!< TPI FIFO0: ETM_bytecount Position */ +#define TPI_FIFO0_ETM_bytecount_Msk (0x3UL << TPI_FIFO0_ETM_bytecount_Pos) /*!< TPI FIFO0: ETM_bytecount Mask */ -#define TPI_FIFO0_ETM2_Pos 16 /*!< TPI FIFO0: ETM2 Position */ -#define TPI_FIFO0_ETM2_Msk (0xFFUL << TPI_FIFO0_ETM2_Pos) /*!< TPI FIFO0: ETM2 Mask */ +#define TPI_FIFO0_ETM2_Pos 16 /*!< TPI FIFO0: ETM2 Position */ +#define TPI_FIFO0_ETM2_Msk (0xFFUL << TPI_FIFO0_ETM2_Pos) /*!< TPI FIFO0: ETM2 Mask */ -#define TPI_FIFO0_ETM1_Pos 8 /*!< TPI FIFO0: ETM1 Position */ -#define TPI_FIFO0_ETM1_Msk (0xFFUL << TPI_FIFO0_ETM1_Pos) /*!< TPI FIFO0: ETM1 Mask */ +#define TPI_FIFO0_ETM1_Pos 8 /*!< TPI FIFO0: ETM1 Position */ +#define TPI_FIFO0_ETM1_Msk (0xFFUL << TPI_FIFO0_ETM1_Pos) /*!< TPI FIFO0: ETM1 Mask */ -#define TPI_FIFO0_ETM0_Pos 0 /*!< TPI FIFO0: ETM0 Position */ -#define TPI_FIFO0_ETM0_Msk (0xFFUL << TPI_FIFO0_ETM0_Pos) /*!< TPI FIFO0: ETM0 Mask */ +#define TPI_FIFO0_ETM0_Pos 0 /*!< TPI FIFO0: ETM0 Position */ +#define TPI_FIFO0_ETM0_Msk (0xFFUL << TPI_FIFO0_ETM0_Pos) /*!< TPI FIFO0: ETM0 Mask */ /* TPI ITATBCTR2 Register Definitions */ -#define TPI_ITATBCTR2_ATREADY_Pos 0 /*!< TPI ITATBCTR2: ATREADY Position */ -#define TPI_ITATBCTR2_ATREADY_Msk (0x1UL << TPI_ITATBCTR2_ATREADY_Pos) /*!< TPI ITATBCTR2: ATREADY Mask */ +#define TPI_ITATBCTR2_ATREADY_Pos 0 /*!< TPI ITATBCTR2: ATREADY Position */ +#define TPI_ITATBCTR2_ATREADY_Msk (0x1UL << TPI_ITATBCTR2_ATREADY_Pos) /*!< TPI ITATBCTR2: ATREADY Mask */ /* TPI Integration ITM Data Register Definitions (FIFO1) */ -#define TPI_FIFO1_ITM_ATVALID_Pos 29 /*!< TPI FIFO1: ITM_ATVALID Position */ -#define TPI_FIFO1_ITM_ATVALID_Msk (0x3UL << TPI_FIFO1_ITM_ATVALID_Pos) /*!< TPI FIFO1: ITM_ATVALID Mask */ +#define TPI_FIFO1_ITM_ATVALID_Pos 29 /*!< TPI FIFO1: ITM_ATVALID Position */ +#define TPI_FIFO1_ITM_ATVALID_Msk (0x3UL << TPI_FIFO1_ITM_ATVALID_Pos) /*!< TPI FIFO1: ITM_ATVALID Mask */ -#define TPI_FIFO1_ITM_bytecount_Pos 27 /*!< TPI FIFO1: ITM_bytecount Position */ -#define TPI_FIFO1_ITM_bytecount_Msk (0x3UL << TPI_FIFO1_ITM_bytecount_Pos) /*!< TPI FIFO1: ITM_bytecount Mask */ +#define TPI_FIFO1_ITM_bytecount_Pos 27 /*!< TPI FIFO1: ITM_bytecount Position */ +#define TPI_FIFO1_ITM_bytecount_Msk (0x3UL << TPI_FIFO1_ITM_bytecount_Pos) /*!< TPI FIFO1: ITM_bytecount Mask */ -#define TPI_FIFO1_ETM_ATVALID_Pos 26 /*!< TPI FIFO1: ETM_ATVALID Position */ -#define TPI_FIFO1_ETM_ATVALID_Msk (0x3UL << TPI_FIFO1_ETM_ATVALID_Pos) /*!< TPI FIFO1: ETM_ATVALID Mask */ +#define TPI_FIFO1_ETM_ATVALID_Pos 26 /*!< TPI FIFO1: ETM_ATVALID Position */ +#define TPI_FIFO1_ETM_ATVALID_Msk (0x3UL << TPI_FIFO1_ETM_ATVALID_Pos) /*!< TPI FIFO1: ETM_ATVALID Mask */ -#define TPI_FIFO1_ETM_bytecount_Pos 24 /*!< TPI FIFO1: ETM_bytecount Position */ -#define TPI_FIFO1_ETM_bytecount_Msk (0x3UL << TPI_FIFO1_ETM_bytecount_Pos) /*!< TPI FIFO1: ETM_bytecount Mask */ +#define TPI_FIFO1_ETM_bytecount_Pos 24 /*!< TPI FIFO1: ETM_bytecount Position */ +#define TPI_FIFO1_ETM_bytecount_Msk (0x3UL << TPI_FIFO1_ETM_bytecount_Pos) /*!< TPI FIFO1: ETM_bytecount Mask */ -#define TPI_FIFO1_ITM2_Pos 16 /*!< TPI FIFO1: ITM2 Position */ -#define TPI_FIFO1_ITM2_Msk (0xFFUL << TPI_FIFO1_ITM2_Pos) /*!< TPI FIFO1: ITM2 Mask */ +#define TPI_FIFO1_ITM2_Pos 16 /*!< TPI FIFO1: ITM2 Position */ +#define TPI_FIFO1_ITM2_Msk (0xFFUL << TPI_FIFO1_ITM2_Pos) /*!< TPI FIFO1: ITM2 Mask */ -#define TPI_FIFO1_ITM1_Pos 8 /*!< TPI FIFO1: ITM1 Position */ -#define TPI_FIFO1_ITM1_Msk (0xFFUL << TPI_FIFO1_ITM1_Pos) /*!< TPI FIFO1: ITM1 Mask */ +#define TPI_FIFO1_ITM1_Pos 8 /*!< TPI FIFO1: ITM1 Position */ +#define TPI_FIFO1_ITM1_Msk (0xFFUL << TPI_FIFO1_ITM1_Pos) /*!< TPI FIFO1: ITM1 Mask */ -#define TPI_FIFO1_ITM0_Pos 0 /*!< TPI FIFO1: ITM0 Position */ -#define TPI_FIFO1_ITM0_Msk (0xFFUL << TPI_FIFO1_ITM0_Pos) /*!< TPI FIFO1: ITM0 Mask */ +#define TPI_FIFO1_ITM0_Pos 0 /*!< TPI FIFO1: ITM0 Position */ +#define TPI_FIFO1_ITM0_Msk (0xFFUL << TPI_FIFO1_ITM0_Pos) /*!< TPI FIFO1: ITM0 Mask */ /* TPI ITATBCTR0 Register Definitions */ -#define TPI_ITATBCTR0_ATREADY_Pos 0 /*!< TPI ITATBCTR0: ATREADY Position */ -#define TPI_ITATBCTR0_ATREADY_Msk (0x1UL << TPI_ITATBCTR0_ATREADY_Pos) /*!< TPI ITATBCTR0: ATREADY Mask */ +#define TPI_ITATBCTR0_ATREADY_Pos 0 /*!< TPI ITATBCTR0: ATREADY Position */ +#define TPI_ITATBCTR0_ATREADY_Msk (0x1UL << TPI_ITATBCTR0_ATREADY_Pos) /*!< TPI ITATBCTR0: ATREADY Mask */ /* TPI Integration Mode Control Register Definitions */ -#define TPI_ITCTRL_Mode_Pos 0 /*!< TPI ITCTRL: Mode Position */ -#define TPI_ITCTRL_Mode_Msk (0x1UL << TPI_ITCTRL_Mode_Pos) /*!< TPI ITCTRL: Mode Mask */ +#define TPI_ITCTRL_Mode_Pos 0 /*!< TPI ITCTRL: Mode Position */ +#define TPI_ITCTRL_Mode_Msk (0x1UL << TPI_ITCTRL_Mode_Pos) /*!< TPI ITCTRL: Mode Mask */ /* TPI DEVID Register Definitions */ -#define TPI_DEVID_NRZVALID_Pos 11 /*!< TPI DEVID: NRZVALID Position */ -#define TPI_DEVID_NRZVALID_Msk (0x1UL << TPI_DEVID_NRZVALID_Pos) /*!< TPI DEVID: NRZVALID Mask */ +#define TPI_DEVID_NRZVALID_Pos 11 /*!< TPI DEVID: NRZVALID Position */ +#define TPI_DEVID_NRZVALID_Msk (0x1UL << TPI_DEVID_NRZVALID_Pos) /*!< TPI DEVID: NRZVALID Mask */ -#define TPI_DEVID_MANCVALID_Pos 10 /*!< TPI DEVID: MANCVALID Position */ -#define TPI_DEVID_MANCVALID_Msk (0x1UL << TPI_DEVID_MANCVALID_Pos) /*!< TPI DEVID: MANCVALID Mask */ +#define TPI_DEVID_MANCVALID_Pos 10 /*!< TPI DEVID: MANCVALID Position */ +#define TPI_DEVID_MANCVALID_Msk (0x1UL << TPI_DEVID_MANCVALID_Pos) /*!< TPI DEVID: MANCVALID Mask */ -#define TPI_DEVID_PTINVALID_Pos 9 /*!< TPI DEVID: PTINVALID Position */ -#define TPI_DEVID_PTINVALID_Msk (0x1UL << TPI_DEVID_PTINVALID_Pos) /*!< TPI DEVID: PTINVALID Mask */ +#define TPI_DEVID_PTINVALID_Pos 9 /*!< TPI DEVID: PTINVALID Position */ +#define TPI_DEVID_PTINVALID_Msk (0x1UL << TPI_DEVID_PTINVALID_Pos) /*!< TPI DEVID: PTINVALID Mask */ -#define TPI_DEVID_MinBufSz_Pos 6 /*!< TPI DEVID: MinBufSz Position */ -#define TPI_DEVID_MinBufSz_Msk (0x7UL << TPI_DEVID_MinBufSz_Pos) /*!< TPI DEVID: MinBufSz Mask */ +#define TPI_DEVID_MinBufSz_Pos 6 /*!< TPI DEVID: MinBufSz Position */ +#define TPI_DEVID_MinBufSz_Msk (0x7UL << TPI_DEVID_MinBufSz_Pos) /*!< TPI DEVID: MinBufSz Mask */ -#define TPI_DEVID_AsynClkIn_Pos 5 /*!< TPI DEVID: AsynClkIn Position */ -#define TPI_DEVID_AsynClkIn_Msk (0x1UL << TPI_DEVID_AsynClkIn_Pos) /*!< TPI DEVID: AsynClkIn Mask */ +#define TPI_DEVID_AsynClkIn_Pos 5 /*!< TPI DEVID: AsynClkIn Position */ +#define TPI_DEVID_AsynClkIn_Msk (0x1UL << TPI_DEVID_AsynClkIn_Pos) /*!< TPI DEVID: AsynClkIn Mask */ -#define TPI_DEVID_NrTraceInput_Pos 0 /*!< TPI DEVID: NrTraceInput Position */ -#define TPI_DEVID_NrTraceInput_Msk (0x1FUL << TPI_DEVID_NrTraceInput_Pos) /*!< TPI DEVID: NrTraceInput Mask */ +#define TPI_DEVID_NrTraceInput_Pos 0 /*!< TPI DEVID: NrTraceInput Position */ +#define TPI_DEVID_NrTraceInput_Msk (0x1FUL << TPI_DEVID_NrTraceInput_Pos) /*!< TPI DEVID: NrTraceInput Mask */ /* TPI DEVTYPE Register Definitions */ -#define TPI_DEVTYPE_SubType_Pos 0 /*!< TPI DEVTYPE: SubType Position */ -#define TPI_DEVTYPE_SubType_Msk (0xFUL << TPI_DEVTYPE_SubType_Pos) /*!< TPI DEVTYPE: SubType Mask */ +#define TPI_DEVTYPE_SubType_Pos 0 /*!< TPI DEVTYPE: SubType Position */ +#define TPI_DEVTYPE_SubType_Msk (0xFUL << TPI_DEVTYPE_SubType_Pos) /*!< TPI DEVTYPE: SubType Mask */ -#define TPI_DEVTYPE_MajorType_Pos 4 /*!< TPI DEVTYPE: MajorType Position */ -#define TPI_DEVTYPE_MajorType_Msk (0xFUL << TPI_DEVTYPE_MajorType_Pos) /*!< TPI DEVTYPE: MajorType Mask */ - -/*@}*/ /* end of group CMSIS_TPI */ +#define TPI_DEVTYPE_MajorType_Pos 4 /*!< TPI DEVTYPE: MajorType Position */ +#define TPI_DEVTYPE_MajorType_Msk (0xFUL << TPI_DEVTYPE_MajorType_Pos) /*!< TPI DEVTYPE: MajorType Mask */ + /*@}*/ /* end of group CMSIS_TPI */ #if (__MPU_PRESENT == 1) -/** \ingroup CMSIS_core_register + /** \ingroup CMSIS_core_register \defgroup CMSIS_MPU Memory Protection Unit (MPU) \brief Type definitions for the Memory Protection Unit (MPU) @{ */ -/** \brief Structure type to access the Memory Protection Unit (MPU). + /** \brief Structure type to access the Memory Protection Unit (MPU). */ -typedef struct -{ - __I uint32_t TYPE; /*!< Offset: 0x000 (R/ ) MPU Type Register */ - __IO uint32_t CTRL; /*!< Offset: 0x004 (R/W) MPU Control Register */ - __IO uint32_t RNR; /*!< Offset: 0x008 (R/W) MPU Region RNRber Register */ - __IO uint32_t RBAR; /*!< Offset: 0x00C (R/W) MPU Region Base Address Register */ - __IO uint32_t RASR; /*!< Offset: 0x010 (R/W) MPU Region Attribute and Size Register */ - __IO uint32_t RBAR_A1; /*!< Offset: 0x014 (R/W) MPU Alias 1 Region Base Address Register */ - __IO uint32_t RASR_A1; /*!< Offset: 0x018 (R/W) MPU Alias 1 Region Attribute and Size Register */ - __IO uint32_t RBAR_A2; /*!< Offset: 0x01C (R/W) MPU Alias 2 Region Base Address Register */ - __IO uint32_t RASR_A2; /*!< Offset: 0x020 (R/W) MPU Alias 2 Region Attribute and Size Register */ - __IO uint32_t RBAR_A3; /*!< Offset: 0x024 (R/W) MPU Alias 3 Region Base Address Register */ - __IO uint32_t RASR_A3; /*!< Offset: 0x028 (R/W) MPU Alias 3 Region Attribute and Size Register */ -} MPU_Type; + typedef struct + { + __I uint32_t TYPE; /*!< Offset: 0x000 (R/ ) MPU Type Register */ + __IO uint32_t CTRL; /*!< Offset: 0x004 (R/W) MPU Control Register */ + __IO uint32_t RNR; /*!< Offset: 0x008 (R/W) MPU Region RNRber Register */ + __IO uint32_t RBAR; /*!< Offset: 0x00C (R/W) MPU Region Base Address Register */ + __IO uint32_t RASR; /*!< Offset: 0x010 (R/W) MPU Region Attribute and Size Register */ + __IO uint32_t RBAR_A1; /*!< Offset: 0x014 (R/W) MPU Alias 1 Region Base Address Register */ + __IO uint32_t RASR_A1; /*!< Offset: 0x018 (R/W) MPU Alias 1 Region Attribute and Size Register */ + __IO uint32_t RBAR_A2; /*!< Offset: 0x01C (R/W) MPU Alias 2 Region Base Address Register */ + __IO uint32_t RASR_A2; /*!< Offset: 0x020 (R/W) MPU Alias 2 Region Attribute and Size Register */ + __IO uint32_t RBAR_A3; /*!< Offset: 0x024 (R/W) MPU Alias 3 Region Base Address Register */ + __IO uint32_t RASR_A3; /*!< Offset: 0x028 (R/W) MPU Alias 3 Region Attribute and Size Register */ + } MPU_Type; /* MPU Type Register */ -#define MPU_TYPE_IREGION_Pos 16 /*!< MPU TYPE: IREGION Position */ -#define MPU_TYPE_IREGION_Msk (0xFFUL << MPU_TYPE_IREGION_Pos) /*!< MPU TYPE: IREGION Mask */ +#define MPU_TYPE_IREGION_Pos 16 /*!< MPU TYPE: IREGION Position */ +#define MPU_TYPE_IREGION_Msk (0xFFUL << MPU_TYPE_IREGION_Pos) /*!< MPU TYPE: IREGION Mask */ -#define MPU_TYPE_DREGION_Pos 8 /*!< MPU TYPE: DREGION Position */ -#define MPU_TYPE_DREGION_Msk (0xFFUL << MPU_TYPE_DREGION_Pos) /*!< MPU TYPE: DREGION Mask */ +#define MPU_TYPE_DREGION_Pos 8 /*!< MPU TYPE: DREGION Position */ +#define MPU_TYPE_DREGION_Msk (0xFFUL << MPU_TYPE_DREGION_Pos) /*!< MPU TYPE: DREGION Mask */ -#define MPU_TYPE_SEPARATE_Pos 0 /*!< MPU TYPE: SEPARATE Position */ -#define MPU_TYPE_SEPARATE_Msk (1UL << MPU_TYPE_SEPARATE_Pos) /*!< MPU TYPE: SEPARATE Mask */ +#define MPU_TYPE_SEPARATE_Pos 0 /*!< MPU TYPE: SEPARATE Position */ +#define MPU_TYPE_SEPARATE_Msk (1UL << MPU_TYPE_SEPARATE_Pos) /*!< MPU TYPE: SEPARATE Mask */ /* MPU Control Register */ -#define MPU_CTRL_PRIVDEFENA_Pos 2 /*!< MPU CTRL: PRIVDEFENA Position */ -#define MPU_CTRL_PRIVDEFENA_Msk (1UL << MPU_CTRL_PRIVDEFENA_Pos) /*!< MPU CTRL: PRIVDEFENA Mask */ +#define MPU_CTRL_PRIVDEFENA_Pos 2 /*!< MPU CTRL: PRIVDEFENA Position */ +#define MPU_CTRL_PRIVDEFENA_Msk (1UL << MPU_CTRL_PRIVDEFENA_Pos) /*!< MPU CTRL: PRIVDEFENA Mask */ -#define MPU_CTRL_HFNMIENA_Pos 1 /*!< MPU CTRL: HFNMIENA Position */ -#define MPU_CTRL_HFNMIENA_Msk (1UL << MPU_CTRL_HFNMIENA_Pos) /*!< MPU CTRL: HFNMIENA Mask */ +#define MPU_CTRL_HFNMIENA_Pos 1 /*!< MPU CTRL: HFNMIENA Position */ +#define MPU_CTRL_HFNMIENA_Msk (1UL << MPU_CTRL_HFNMIENA_Pos) /*!< MPU CTRL: HFNMIENA Mask */ -#define MPU_CTRL_ENABLE_Pos 0 /*!< MPU CTRL: ENABLE Position */ -#define MPU_CTRL_ENABLE_Msk (1UL << MPU_CTRL_ENABLE_Pos) /*!< MPU CTRL: ENABLE Mask */ +#define MPU_CTRL_ENABLE_Pos 0 /*!< MPU CTRL: ENABLE Position */ +#define MPU_CTRL_ENABLE_Msk (1UL << MPU_CTRL_ENABLE_Pos) /*!< MPU CTRL: ENABLE Mask */ /* MPU Region Number Register */ -#define MPU_RNR_REGION_Pos 0 /*!< MPU RNR: REGION Position */ -#define MPU_RNR_REGION_Msk (0xFFUL << MPU_RNR_REGION_Pos) /*!< MPU RNR: REGION Mask */ +#define MPU_RNR_REGION_Pos 0 /*!< MPU RNR: REGION Position */ +#define MPU_RNR_REGION_Msk (0xFFUL << MPU_RNR_REGION_Pos) /*!< MPU RNR: REGION Mask */ /* MPU Region Base Address Register */ -#define MPU_RBAR_ADDR_Pos 5 /*!< MPU RBAR: ADDR Position */ -#define MPU_RBAR_ADDR_Msk (0x7FFFFFFUL << MPU_RBAR_ADDR_Pos) /*!< MPU RBAR: ADDR Mask */ +#define MPU_RBAR_ADDR_Pos 5 /*!< MPU RBAR: ADDR Position */ +#define MPU_RBAR_ADDR_Msk (0x7FFFFFFUL << MPU_RBAR_ADDR_Pos) /*!< MPU RBAR: ADDR Mask */ -#define MPU_RBAR_VALID_Pos 4 /*!< MPU RBAR: VALID Position */ -#define MPU_RBAR_VALID_Msk (1UL << MPU_RBAR_VALID_Pos) /*!< MPU RBAR: VALID Mask */ +#define MPU_RBAR_VALID_Pos 4 /*!< MPU RBAR: VALID Position */ +#define MPU_RBAR_VALID_Msk (1UL << MPU_RBAR_VALID_Pos) /*!< MPU RBAR: VALID Mask */ -#define MPU_RBAR_REGION_Pos 0 /*!< MPU RBAR: REGION Position */ -#define MPU_RBAR_REGION_Msk (0xFUL << MPU_RBAR_REGION_Pos) /*!< MPU RBAR: REGION Mask */ +#define MPU_RBAR_REGION_Pos 0 /*!< MPU RBAR: REGION Position */ +#define MPU_RBAR_REGION_Msk (0xFUL << MPU_RBAR_REGION_Pos) /*!< MPU RBAR: REGION Mask */ /* MPU Region Attribute and Size Register */ -#define MPU_RASR_ATTRS_Pos 16 /*!< MPU RASR: MPU Region Attribute field Position */ -#define MPU_RASR_ATTRS_Msk (0xFFFFUL << MPU_RASR_ATTRS_Pos) /*!< MPU RASR: MPU Region Attribute field Mask */ +#define MPU_RASR_ATTRS_Pos 16 /*!< MPU RASR: MPU Region Attribute field Position */ +#define MPU_RASR_ATTRS_Msk (0xFFFFUL << MPU_RASR_ATTRS_Pos) /*!< MPU RASR: MPU Region Attribute field Mask */ -#define MPU_RASR_XN_Pos 28 /*!< MPU RASR: ATTRS.XN Position */ -#define MPU_RASR_XN_Msk (1UL << MPU_RASR_XN_Pos) /*!< MPU RASR: ATTRS.XN Mask */ +#define MPU_RASR_XN_Pos 28 /*!< MPU RASR: ATTRS.XN Position */ +#define MPU_RASR_XN_Msk (1UL << MPU_RASR_XN_Pos) /*!< MPU RASR: ATTRS.XN Mask */ -#define MPU_RASR_AP_Pos 24 /*!< MPU RASR: ATTRS.AP Position */ -#define MPU_RASR_AP_Msk (0x7UL << MPU_RASR_AP_Pos) /*!< MPU RASR: ATTRS.AP Mask */ +#define MPU_RASR_AP_Pos 24 /*!< MPU RASR: ATTRS.AP Position */ +#define MPU_RASR_AP_Msk (0x7UL << MPU_RASR_AP_Pos) /*!< MPU RASR: ATTRS.AP Mask */ -#define MPU_RASR_TEX_Pos 19 /*!< MPU RASR: ATTRS.TEX Position */ -#define MPU_RASR_TEX_Msk (0x7UL << MPU_RASR_TEX_Pos) /*!< MPU RASR: ATTRS.TEX Mask */ +#define MPU_RASR_TEX_Pos 19 /*!< MPU RASR: ATTRS.TEX Position */ +#define MPU_RASR_TEX_Msk (0x7UL << MPU_RASR_TEX_Pos) /*!< MPU RASR: ATTRS.TEX Mask */ -#define MPU_RASR_S_Pos 18 /*!< MPU RASR: ATTRS.S Position */ -#define MPU_RASR_S_Msk (1UL << MPU_RASR_S_Pos) /*!< MPU RASR: ATTRS.S Mask */ +#define MPU_RASR_S_Pos 18 /*!< MPU RASR: ATTRS.S Position */ +#define MPU_RASR_S_Msk (1UL << MPU_RASR_S_Pos) /*!< MPU RASR: ATTRS.S Mask */ -#define MPU_RASR_C_Pos 17 /*!< MPU RASR: ATTRS.C Position */ -#define MPU_RASR_C_Msk (1UL << MPU_RASR_C_Pos) /*!< MPU RASR: ATTRS.C Mask */ +#define MPU_RASR_C_Pos 17 /*!< MPU RASR: ATTRS.C Position */ +#define MPU_RASR_C_Msk (1UL << MPU_RASR_C_Pos) /*!< MPU RASR: ATTRS.C Mask */ -#define MPU_RASR_B_Pos 16 /*!< MPU RASR: ATTRS.B Position */ -#define MPU_RASR_B_Msk (1UL << MPU_RASR_B_Pos) /*!< MPU RASR: ATTRS.B Mask */ +#define MPU_RASR_B_Pos 16 /*!< MPU RASR: ATTRS.B Position */ +#define MPU_RASR_B_Msk (1UL << MPU_RASR_B_Pos) /*!< MPU RASR: ATTRS.B Mask */ -#define MPU_RASR_SRD_Pos 8 /*!< MPU RASR: Sub-Region Disable Position */ -#define MPU_RASR_SRD_Msk (0xFFUL << MPU_RASR_SRD_Pos) /*!< MPU RASR: Sub-Region Disable Mask */ +#define MPU_RASR_SRD_Pos 8 /*!< MPU RASR: Sub-Region Disable Position */ +#define MPU_RASR_SRD_Msk (0xFFUL << MPU_RASR_SRD_Pos) /*!< MPU RASR: Sub-Region Disable Mask */ -#define MPU_RASR_SIZE_Pos 1 /*!< MPU RASR: Region Size Field Position */ -#define MPU_RASR_SIZE_Msk (0x1FUL << MPU_RASR_SIZE_Pos) /*!< MPU RASR: Region Size Field Mask */ +#define MPU_RASR_SIZE_Pos 1 /*!< MPU RASR: Region Size Field Position */ +#define MPU_RASR_SIZE_Msk (0x1FUL << MPU_RASR_SIZE_Pos) /*!< MPU RASR: Region Size Field Mask */ -#define MPU_RASR_ENABLE_Pos 0 /*!< MPU RASR: Region enable bit Position */ -#define MPU_RASR_ENABLE_Msk (1UL << MPU_RASR_ENABLE_Pos) /*!< MPU RASR: Region enable bit Disable Mask */ +#define MPU_RASR_ENABLE_Pos 0 /*!< MPU RASR: Region enable bit Position */ +#define MPU_RASR_ENABLE_Msk (1UL << MPU_RASR_ENABLE_Pos) /*!< MPU RASR: Region enable bit Disable Mask */ /*@} end of group CMSIS_MPU */ #endif - #if (__FPU_PRESENT == 1) -/** \ingroup CMSIS_core_register + /** \ingroup CMSIS_core_register \defgroup CMSIS_FPU Floating Point Unit (FPU) \brief Type definitions for the Floating Point Unit (FPU) @{ */ -/** \brief Structure type to access the Floating Point Unit (FPU). + /** \brief Structure type to access the Floating Point Unit (FPU). */ -typedef struct -{ - uint32_t RESERVED0[1]; - __IO uint32_t FPCCR; /*!< Offset: 0x004 (R/W) Floating-Point Context Control Register */ - __IO uint32_t FPCAR; /*!< Offset: 0x008 (R/W) Floating-Point Context Address Register */ - __IO uint32_t FPDSCR; /*!< Offset: 0x00C (R/W) Floating-Point Default Status Control Register */ - __I uint32_t MVFR0; /*!< Offset: 0x010 (R/ ) Media and FP Feature Register 0 */ - __I uint32_t MVFR1; /*!< Offset: 0x014 (R/ ) Media and FP Feature Register 1 */ -} FPU_Type; + typedef struct + { + uint32_t RESERVED0[1]; + __IO uint32_t FPCCR; /*!< Offset: 0x004 (R/W) Floating-Point Context Control Register */ + __IO uint32_t FPCAR; /*!< Offset: 0x008 (R/W) Floating-Point Context Address Register */ + __IO uint32_t FPDSCR; /*!< Offset: 0x00C (R/W) Floating-Point Default Status Control Register */ + __I uint32_t MVFR0; /*!< Offset: 0x010 (R/ ) Media and FP Feature Register 0 */ + __I uint32_t MVFR1; /*!< Offset: 0x014 (R/ ) Media and FP Feature Register 1 */ + } FPU_Type; /* Floating-Point Context Control Register */ -#define FPU_FPCCR_ASPEN_Pos 31 /*!< FPCCR: ASPEN bit Position */ -#define FPU_FPCCR_ASPEN_Msk (1UL << FPU_FPCCR_ASPEN_Pos) /*!< FPCCR: ASPEN bit Mask */ +#define FPU_FPCCR_ASPEN_Pos 31 /*!< FPCCR: ASPEN bit Position */ +#define FPU_FPCCR_ASPEN_Msk (1UL << FPU_FPCCR_ASPEN_Pos) /*!< FPCCR: ASPEN bit Mask */ -#define FPU_FPCCR_LSPEN_Pos 30 /*!< FPCCR: LSPEN Position */ -#define FPU_FPCCR_LSPEN_Msk (1UL << FPU_FPCCR_LSPEN_Pos) /*!< FPCCR: LSPEN bit Mask */ +#define FPU_FPCCR_LSPEN_Pos 30 /*!< FPCCR: LSPEN Position */ +#define FPU_FPCCR_LSPEN_Msk (1UL << FPU_FPCCR_LSPEN_Pos) /*!< FPCCR: LSPEN bit Mask */ -#define FPU_FPCCR_MONRDY_Pos 8 /*!< FPCCR: MONRDY Position */ -#define FPU_FPCCR_MONRDY_Msk (1UL << FPU_FPCCR_MONRDY_Pos) /*!< FPCCR: MONRDY bit Mask */ +#define FPU_FPCCR_MONRDY_Pos 8 /*!< FPCCR: MONRDY Position */ +#define FPU_FPCCR_MONRDY_Msk (1UL << FPU_FPCCR_MONRDY_Pos) /*!< FPCCR: MONRDY bit Mask */ -#define FPU_FPCCR_BFRDY_Pos 6 /*!< FPCCR: BFRDY Position */ -#define FPU_FPCCR_BFRDY_Msk (1UL << FPU_FPCCR_BFRDY_Pos) /*!< FPCCR: BFRDY bit Mask */ +#define FPU_FPCCR_BFRDY_Pos 6 /*!< FPCCR: BFRDY Position */ +#define FPU_FPCCR_BFRDY_Msk (1UL << FPU_FPCCR_BFRDY_Pos) /*!< FPCCR: BFRDY bit Mask */ -#define FPU_FPCCR_MMRDY_Pos 5 /*!< FPCCR: MMRDY Position */ -#define FPU_FPCCR_MMRDY_Msk (1UL << FPU_FPCCR_MMRDY_Pos) /*!< FPCCR: MMRDY bit Mask */ +#define FPU_FPCCR_MMRDY_Pos 5 /*!< FPCCR: MMRDY Position */ +#define FPU_FPCCR_MMRDY_Msk (1UL << FPU_FPCCR_MMRDY_Pos) /*!< FPCCR: MMRDY bit Mask */ -#define FPU_FPCCR_HFRDY_Pos 4 /*!< FPCCR: HFRDY Position */ -#define FPU_FPCCR_HFRDY_Msk (1UL << FPU_FPCCR_HFRDY_Pos) /*!< FPCCR: HFRDY bit Mask */ +#define FPU_FPCCR_HFRDY_Pos 4 /*!< FPCCR: HFRDY Position */ +#define FPU_FPCCR_HFRDY_Msk (1UL << FPU_FPCCR_HFRDY_Pos) /*!< FPCCR: HFRDY bit Mask */ -#define FPU_FPCCR_THREAD_Pos 3 /*!< FPCCR: processor mode bit Position */ -#define FPU_FPCCR_THREAD_Msk (1UL << FPU_FPCCR_THREAD_Pos) /*!< FPCCR: processor mode active bit Mask */ +#define FPU_FPCCR_THREAD_Pos 3 /*!< FPCCR: processor mode bit Position */ +#define FPU_FPCCR_THREAD_Msk (1UL << FPU_FPCCR_THREAD_Pos) /*!< FPCCR: processor mode active bit Mask */ -#define FPU_FPCCR_USER_Pos 1 /*!< FPCCR: privilege level bit Position */ -#define FPU_FPCCR_USER_Msk (1UL << FPU_FPCCR_USER_Pos) /*!< FPCCR: privilege level bit Mask */ +#define FPU_FPCCR_USER_Pos 1 /*!< FPCCR: privilege level bit Position */ +#define FPU_FPCCR_USER_Msk (1UL << FPU_FPCCR_USER_Pos) /*!< FPCCR: privilege level bit Mask */ -#define FPU_FPCCR_LSPACT_Pos 0 /*!< FPCCR: Lazy state preservation active bit Position */ -#define FPU_FPCCR_LSPACT_Msk (1UL << FPU_FPCCR_LSPACT_Pos) /*!< FPCCR: Lazy state preservation active bit Mask */ +#define FPU_FPCCR_LSPACT_Pos 0 /*!< FPCCR: Lazy state preservation active bit Position */ +#define FPU_FPCCR_LSPACT_Msk (1UL << FPU_FPCCR_LSPACT_Pos) /*!< FPCCR: Lazy state preservation active bit Mask */ /* Floating-Point Context Address Register */ -#define FPU_FPCAR_ADDRESS_Pos 3 /*!< FPCAR: ADDRESS bit Position */ -#define FPU_FPCAR_ADDRESS_Msk (0x1FFFFFFFUL << FPU_FPCAR_ADDRESS_Pos) /*!< FPCAR: ADDRESS bit Mask */ +#define FPU_FPCAR_ADDRESS_Pos 3 /*!< FPCAR: ADDRESS bit Position */ +#define FPU_FPCAR_ADDRESS_Msk (0x1FFFFFFFUL << FPU_FPCAR_ADDRESS_Pos) /*!< FPCAR: ADDRESS bit Mask */ /* Floating-Point Default Status Control Register */ -#define FPU_FPDSCR_AHP_Pos 26 /*!< FPDSCR: AHP bit Position */ -#define FPU_FPDSCR_AHP_Msk (1UL << FPU_FPDSCR_AHP_Pos) /*!< FPDSCR: AHP bit Mask */ +#define FPU_FPDSCR_AHP_Pos 26 /*!< FPDSCR: AHP bit Position */ +#define FPU_FPDSCR_AHP_Msk (1UL << FPU_FPDSCR_AHP_Pos) /*!< FPDSCR: AHP bit Mask */ -#define FPU_FPDSCR_DN_Pos 25 /*!< FPDSCR: DN bit Position */ -#define FPU_FPDSCR_DN_Msk (1UL << FPU_FPDSCR_DN_Pos) /*!< FPDSCR: DN bit Mask */ +#define FPU_FPDSCR_DN_Pos 25 /*!< FPDSCR: DN bit Position */ +#define FPU_FPDSCR_DN_Msk (1UL << FPU_FPDSCR_DN_Pos) /*!< FPDSCR: DN bit Mask */ -#define FPU_FPDSCR_FZ_Pos 24 /*!< FPDSCR: FZ bit Position */ -#define FPU_FPDSCR_FZ_Msk (1UL << FPU_FPDSCR_FZ_Pos) /*!< FPDSCR: FZ bit Mask */ +#define FPU_FPDSCR_FZ_Pos 24 /*!< FPDSCR: FZ bit Position */ +#define FPU_FPDSCR_FZ_Msk (1UL << FPU_FPDSCR_FZ_Pos) /*!< FPDSCR: FZ bit Mask */ -#define FPU_FPDSCR_RMode_Pos 22 /*!< FPDSCR: RMode bit Position */ -#define FPU_FPDSCR_RMode_Msk (3UL << FPU_FPDSCR_RMode_Pos) /*!< FPDSCR: RMode bit Mask */ +#define FPU_FPDSCR_RMode_Pos 22 /*!< FPDSCR: RMode bit Position */ +#define FPU_FPDSCR_RMode_Msk (3UL << FPU_FPDSCR_RMode_Pos) /*!< FPDSCR: RMode bit Mask */ /* Media and FP Feature Register 0 */ -#define FPU_MVFR0_FP_rounding_modes_Pos 28 /*!< MVFR0: FP rounding modes bits Position */ -#define FPU_MVFR0_FP_rounding_modes_Msk (0xFUL << FPU_MVFR0_FP_rounding_modes_Pos) /*!< MVFR0: FP rounding modes bits Mask */ +#define FPU_MVFR0_FP_rounding_modes_Pos 28 /*!< MVFR0: FP rounding modes bits Position */ +#define FPU_MVFR0_FP_rounding_modes_Msk (0xFUL << FPU_MVFR0_FP_rounding_modes_Pos) /*!< MVFR0: FP rounding modes bits Mask */ -#define FPU_MVFR0_Short_vectors_Pos 24 /*!< MVFR0: Short vectors bits Position */ -#define FPU_MVFR0_Short_vectors_Msk (0xFUL << FPU_MVFR0_Short_vectors_Pos) /*!< MVFR0: Short vectors bits Mask */ +#define FPU_MVFR0_Short_vectors_Pos 24 /*!< MVFR0: Short vectors bits Position */ +#define FPU_MVFR0_Short_vectors_Msk (0xFUL << FPU_MVFR0_Short_vectors_Pos) /*!< MVFR0: Short vectors bits Mask */ -#define FPU_MVFR0_Square_root_Pos 20 /*!< MVFR0: Square root bits Position */ -#define FPU_MVFR0_Square_root_Msk (0xFUL << FPU_MVFR0_Square_root_Pos) /*!< MVFR0: Square root bits Mask */ +#define FPU_MVFR0_Square_root_Pos 20 /*!< MVFR0: Square root bits Position */ +#define FPU_MVFR0_Square_root_Msk (0xFUL << FPU_MVFR0_Square_root_Pos) /*!< MVFR0: Square root bits Mask */ -#define FPU_MVFR0_Divide_Pos 16 /*!< MVFR0: Divide bits Position */ -#define FPU_MVFR0_Divide_Msk (0xFUL << FPU_MVFR0_Divide_Pos) /*!< MVFR0: Divide bits Mask */ +#define FPU_MVFR0_Divide_Pos 16 /*!< MVFR0: Divide bits Position */ +#define FPU_MVFR0_Divide_Msk (0xFUL << FPU_MVFR0_Divide_Pos) /*!< MVFR0: Divide bits Mask */ -#define FPU_MVFR0_FP_excep_trapping_Pos 12 /*!< MVFR0: FP exception trapping bits Position */ -#define FPU_MVFR0_FP_excep_trapping_Msk (0xFUL << FPU_MVFR0_FP_excep_trapping_Pos) /*!< MVFR0: FP exception trapping bits Mask */ +#define FPU_MVFR0_FP_excep_trapping_Pos 12 /*!< MVFR0: FP exception trapping bits Position */ +#define FPU_MVFR0_FP_excep_trapping_Msk (0xFUL << FPU_MVFR0_FP_excep_trapping_Pos) /*!< MVFR0: FP exception trapping bits Mask */ -#define FPU_MVFR0_Double_precision_Pos 8 /*!< MVFR0: Double-precision bits Position */ -#define FPU_MVFR0_Double_precision_Msk (0xFUL << FPU_MVFR0_Double_precision_Pos) /*!< MVFR0: Double-precision bits Mask */ +#define FPU_MVFR0_Double_precision_Pos 8 /*!< MVFR0: Double-precision bits Position */ +#define FPU_MVFR0_Double_precision_Msk (0xFUL << FPU_MVFR0_Double_precision_Pos) /*!< MVFR0: Double-precision bits Mask */ -#define FPU_MVFR0_Single_precision_Pos 4 /*!< MVFR0: Single-precision bits Position */ -#define FPU_MVFR0_Single_precision_Msk (0xFUL << FPU_MVFR0_Single_precision_Pos) /*!< MVFR0: Single-precision bits Mask */ +#define FPU_MVFR0_Single_precision_Pos 4 /*!< MVFR0: Single-precision bits Position */ +#define FPU_MVFR0_Single_precision_Msk (0xFUL << FPU_MVFR0_Single_precision_Pos) /*!< MVFR0: Single-precision bits Mask */ -#define FPU_MVFR0_A_SIMD_registers_Pos 0 /*!< MVFR0: A_SIMD registers bits Position */ -#define FPU_MVFR0_A_SIMD_registers_Msk (0xFUL << FPU_MVFR0_A_SIMD_registers_Pos) /*!< MVFR0: A_SIMD registers bits Mask */ +#define FPU_MVFR0_A_SIMD_registers_Pos 0 /*!< MVFR0: A_SIMD registers bits Position */ +#define FPU_MVFR0_A_SIMD_registers_Msk (0xFUL << FPU_MVFR0_A_SIMD_registers_Pos) /*!< MVFR0: A_SIMD registers bits Mask */ /* Media and FP Feature Register 1 */ -#define FPU_MVFR1_FP_fused_MAC_Pos 28 /*!< MVFR1: FP fused MAC bits Position */ -#define FPU_MVFR1_FP_fused_MAC_Msk (0xFUL << FPU_MVFR1_FP_fused_MAC_Pos) /*!< MVFR1: FP fused MAC bits Mask */ +#define FPU_MVFR1_FP_fused_MAC_Pos 28 /*!< MVFR1: FP fused MAC bits Position */ +#define FPU_MVFR1_FP_fused_MAC_Msk (0xFUL << FPU_MVFR1_FP_fused_MAC_Pos) /*!< MVFR1: FP fused MAC bits Mask */ -#define FPU_MVFR1_FP_HPFP_Pos 24 /*!< MVFR1: FP HPFP bits Position */ -#define FPU_MVFR1_FP_HPFP_Msk (0xFUL << FPU_MVFR1_FP_HPFP_Pos) /*!< MVFR1: FP HPFP bits Mask */ +#define FPU_MVFR1_FP_HPFP_Pos 24 /*!< MVFR1: FP HPFP bits Position */ +#define FPU_MVFR1_FP_HPFP_Msk (0xFUL << FPU_MVFR1_FP_HPFP_Pos) /*!< MVFR1: FP HPFP bits Mask */ -#define FPU_MVFR1_D_NaN_mode_Pos 4 /*!< MVFR1: D_NaN mode bits Position */ -#define FPU_MVFR1_D_NaN_mode_Msk (0xFUL << FPU_MVFR1_D_NaN_mode_Pos) /*!< MVFR1: D_NaN mode bits Mask */ +#define FPU_MVFR1_D_NaN_mode_Pos 4 /*!< MVFR1: D_NaN mode bits Position */ +#define FPU_MVFR1_D_NaN_mode_Msk (0xFUL << FPU_MVFR1_D_NaN_mode_Pos) /*!< MVFR1: D_NaN mode bits Mask */ -#define FPU_MVFR1_FtZ_mode_Pos 0 /*!< MVFR1: FtZ mode bits Position */ -#define FPU_MVFR1_FtZ_mode_Msk (0xFUL << FPU_MVFR1_FtZ_mode_Pos) /*!< MVFR1: FtZ mode bits Mask */ +#define FPU_MVFR1_FtZ_mode_Pos 0 /*!< MVFR1: FtZ mode bits Position */ +#define FPU_MVFR1_FtZ_mode_Msk (0xFUL << FPU_MVFR1_FtZ_mode_Pos) /*!< MVFR1: FtZ mode bits Mask */ /*@} end of group CMSIS_FPU */ #endif - -/** \ingroup CMSIS_core_register + /** \ingroup CMSIS_core_register \defgroup CMSIS_CoreDebug Core Debug Registers (CoreDebug) \brief Type definitions for the Core Debug Registers @{ */ -/** \brief Structure type to access the Core Debug Register (CoreDebug). + /** \brief Structure type to access the Core Debug Register (CoreDebug). */ -typedef struct -{ - __IO uint32_t DHCSR; /*!< Offset: 0x000 (R/W) Debug Halting Control and Status Register */ - __O uint32_t DCRSR; /*!< Offset: 0x004 ( /W) Debug Core Register Selector Register */ - __IO uint32_t DCRDR; /*!< Offset: 0x008 (R/W) Debug Core Register Data Register */ - __IO uint32_t DEMCR; /*!< Offset: 0x00C (R/W) Debug Exception and Monitor Control Register */ -} CoreDebug_Type; + typedef struct + { + __IO uint32_t DHCSR; /*!< Offset: 0x000 (R/W) Debug Halting Control and Status Register */ + __O uint32_t DCRSR; /*!< Offset: 0x004 ( /W) Debug Core Register Selector Register */ + __IO uint32_t DCRDR; /*!< Offset: 0x008 (R/W) Debug Core Register Data Register */ + __IO uint32_t DEMCR; /*!< Offset: 0x00C (R/W) Debug Exception and Monitor Control Register */ + } CoreDebug_Type; /* Debug Halting Control and Status Register */ -#define CoreDebug_DHCSR_DBGKEY_Pos 16 /*!< CoreDebug DHCSR: DBGKEY Position */ -#define CoreDebug_DHCSR_DBGKEY_Msk (0xFFFFUL << CoreDebug_DHCSR_DBGKEY_Pos) /*!< CoreDebug DHCSR: DBGKEY Mask */ +#define CoreDebug_DHCSR_DBGKEY_Pos 16 /*!< CoreDebug DHCSR: DBGKEY Position */ +#define CoreDebug_DHCSR_DBGKEY_Msk (0xFFFFUL << CoreDebug_DHCSR_DBGKEY_Pos) /*!< CoreDebug DHCSR: DBGKEY Mask */ -#define CoreDebug_DHCSR_S_RESET_ST_Pos 25 /*!< CoreDebug DHCSR: S_RESET_ST Position */ -#define CoreDebug_DHCSR_S_RESET_ST_Msk (1UL << CoreDebug_DHCSR_S_RESET_ST_Pos) /*!< CoreDebug DHCSR: S_RESET_ST Mask */ +#define CoreDebug_DHCSR_S_RESET_ST_Pos 25 /*!< CoreDebug DHCSR: S_RESET_ST Position */ +#define CoreDebug_DHCSR_S_RESET_ST_Msk (1UL << CoreDebug_DHCSR_S_RESET_ST_Pos) /*!< CoreDebug DHCSR: S_RESET_ST Mask */ -#define CoreDebug_DHCSR_S_RETIRE_ST_Pos 24 /*!< CoreDebug DHCSR: S_RETIRE_ST Position */ -#define CoreDebug_DHCSR_S_RETIRE_ST_Msk (1UL << CoreDebug_DHCSR_S_RETIRE_ST_Pos) /*!< CoreDebug DHCSR: S_RETIRE_ST Mask */ +#define CoreDebug_DHCSR_S_RETIRE_ST_Pos 24 /*!< CoreDebug DHCSR: S_RETIRE_ST Position */ +#define CoreDebug_DHCSR_S_RETIRE_ST_Msk (1UL << CoreDebug_DHCSR_S_RETIRE_ST_Pos) /*!< CoreDebug DHCSR: S_RETIRE_ST Mask */ -#define CoreDebug_DHCSR_S_LOCKUP_Pos 19 /*!< CoreDebug DHCSR: S_LOCKUP Position */ -#define CoreDebug_DHCSR_S_LOCKUP_Msk (1UL << CoreDebug_DHCSR_S_LOCKUP_Pos) /*!< CoreDebug DHCSR: S_LOCKUP Mask */ +#define CoreDebug_DHCSR_S_LOCKUP_Pos 19 /*!< CoreDebug DHCSR: S_LOCKUP Position */ +#define CoreDebug_DHCSR_S_LOCKUP_Msk (1UL << CoreDebug_DHCSR_S_LOCKUP_Pos) /*!< CoreDebug DHCSR: S_LOCKUP Mask */ -#define CoreDebug_DHCSR_S_SLEEP_Pos 18 /*!< CoreDebug DHCSR: S_SLEEP Position */ -#define CoreDebug_DHCSR_S_SLEEP_Msk (1UL << CoreDebug_DHCSR_S_SLEEP_Pos) /*!< CoreDebug DHCSR: S_SLEEP Mask */ +#define CoreDebug_DHCSR_S_SLEEP_Pos 18 /*!< CoreDebug DHCSR: S_SLEEP Position */ +#define CoreDebug_DHCSR_S_SLEEP_Msk (1UL << CoreDebug_DHCSR_S_SLEEP_Pos) /*!< CoreDebug DHCSR: S_SLEEP Mask */ -#define CoreDebug_DHCSR_S_HALT_Pos 17 /*!< CoreDebug DHCSR: S_HALT Position */ -#define CoreDebug_DHCSR_S_HALT_Msk (1UL << CoreDebug_DHCSR_S_HALT_Pos) /*!< CoreDebug DHCSR: S_HALT Mask */ +#define CoreDebug_DHCSR_S_HALT_Pos 17 /*!< CoreDebug DHCSR: S_HALT Position */ +#define CoreDebug_DHCSR_S_HALT_Msk (1UL << CoreDebug_DHCSR_S_HALT_Pos) /*!< CoreDebug DHCSR: S_HALT Mask */ -#define CoreDebug_DHCSR_S_REGRDY_Pos 16 /*!< CoreDebug DHCSR: S_REGRDY Position */ -#define CoreDebug_DHCSR_S_REGRDY_Msk (1UL << CoreDebug_DHCSR_S_REGRDY_Pos) /*!< CoreDebug DHCSR: S_REGRDY Mask */ +#define CoreDebug_DHCSR_S_REGRDY_Pos 16 /*!< CoreDebug DHCSR: S_REGRDY Position */ +#define CoreDebug_DHCSR_S_REGRDY_Msk (1UL << CoreDebug_DHCSR_S_REGRDY_Pos) /*!< CoreDebug DHCSR: S_REGRDY Mask */ -#define CoreDebug_DHCSR_C_SNAPSTALL_Pos 5 /*!< CoreDebug DHCSR: C_SNAPSTALL Position */ -#define CoreDebug_DHCSR_C_SNAPSTALL_Msk (1UL << CoreDebug_DHCSR_C_SNAPSTALL_Pos) /*!< CoreDebug DHCSR: C_SNAPSTALL Mask */ +#define CoreDebug_DHCSR_C_SNAPSTALL_Pos 5 /*!< CoreDebug DHCSR: C_SNAPSTALL Position */ +#define CoreDebug_DHCSR_C_SNAPSTALL_Msk (1UL << CoreDebug_DHCSR_C_SNAPSTALL_Pos) /*!< CoreDebug DHCSR: C_SNAPSTALL Mask */ -#define CoreDebug_DHCSR_C_MASKINTS_Pos 3 /*!< CoreDebug DHCSR: C_MASKINTS Position */ -#define CoreDebug_DHCSR_C_MASKINTS_Msk (1UL << CoreDebug_DHCSR_C_MASKINTS_Pos) /*!< CoreDebug DHCSR: C_MASKINTS Mask */ +#define CoreDebug_DHCSR_C_MASKINTS_Pos 3 /*!< CoreDebug DHCSR: C_MASKINTS Position */ +#define CoreDebug_DHCSR_C_MASKINTS_Msk (1UL << CoreDebug_DHCSR_C_MASKINTS_Pos) /*!< CoreDebug DHCSR: C_MASKINTS Mask */ -#define CoreDebug_DHCSR_C_STEP_Pos 2 /*!< CoreDebug DHCSR: C_STEP Position */ -#define CoreDebug_DHCSR_C_STEP_Msk (1UL << CoreDebug_DHCSR_C_STEP_Pos) /*!< CoreDebug DHCSR: C_STEP Mask */ +#define CoreDebug_DHCSR_C_STEP_Pos 2 /*!< CoreDebug DHCSR: C_STEP Position */ +#define CoreDebug_DHCSR_C_STEP_Msk (1UL << CoreDebug_DHCSR_C_STEP_Pos) /*!< CoreDebug DHCSR: C_STEP Mask */ -#define CoreDebug_DHCSR_C_HALT_Pos 1 /*!< CoreDebug DHCSR: C_HALT Position */ -#define CoreDebug_DHCSR_C_HALT_Msk (1UL << CoreDebug_DHCSR_C_HALT_Pos) /*!< CoreDebug DHCSR: C_HALT Mask */ +#define CoreDebug_DHCSR_C_HALT_Pos 1 /*!< CoreDebug DHCSR: C_HALT Position */ +#define CoreDebug_DHCSR_C_HALT_Msk (1UL << CoreDebug_DHCSR_C_HALT_Pos) /*!< CoreDebug DHCSR: C_HALT Mask */ -#define CoreDebug_DHCSR_C_DEBUGEN_Pos 0 /*!< CoreDebug DHCSR: C_DEBUGEN Position */ -#define CoreDebug_DHCSR_C_DEBUGEN_Msk (1UL << CoreDebug_DHCSR_C_DEBUGEN_Pos) /*!< CoreDebug DHCSR: C_DEBUGEN Mask */ +#define CoreDebug_DHCSR_C_DEBUGEN_Pos 0 /*!< CoreDebug DHCSR: C_DEBUGEN Position */ +#define CoreDebug_DHCSR_C_DEBUGEN_Msk (1UL << CoreDebug_DHCSR_C_DEBUGEN_Pos) /*!< CoreDebug DHCSR: C_DEBUGEN Mask */ /* Debug Core Register Selector Register */ -#define CoreDebug_DCRSR_REGWnR_Pos 16 /*!< CoreDebug DCRSR: REGWnR Position */ -#define CoreDebug_DCRSR_REGWnR_Msk (1UL << CoreDebug_DCRSR_REGWnR_Pos) /*!< CoreDebug DCRSR: REGWnR Mask */ +#define CoreDebug_DCRSR_REGWnR_Pos 16 /*!< CoreDebug DCRSR: REGWnR Position */ +#define CoreDebug_DCRSR_REGWnR_Msk (1UL << CoreDebug_DCRSR_REGWnR_Pos) /*!< CoreDebug DCRSR: REGWnR Mask */ -#define CoreDebug_DCRSR_REGSEL_Pos 0 /*!< CoreDebug DCRSR: REGSEL Position */ -#define CoreDebug_DCRSR_REGSEL_Msk (0x1FUL << CoreDebug_DCRSR_REGSEL_Pos) /*!< CoreDebug DCRSR: REGSEL Mask */ +#define CoreDebug_DCRSR_REGSEL_Pos 0 /*!< CoreDebug DCRSR: REGSEL Position */ +#define CoreDebug_DCRSR_REGSEL_Msk (0x1FUL << CoreDebug_DCRSR_REGSEL_Pos) /*!< CoreDebug DCRSR: REGSEL Mask */ /* Debug Exception and Monitor Control Register */ -#define CoreDebug_DEMCR_TRCENA_Pos 24 /*!< CoreDebug DEMCR: TRCENA Position */ -#define CoreDebug_DEMCR_TRCENA_Msk (1UL << CoreDebug_DEMCR_TRCENA_Pos) /*!< CoreDebug DEMCR: TRCENA Mask */ +#define CoreDebug_DEMCR_TRCENA_Pos 24 /*!< CoreDebug DEMCR: TRCENA Position */ +#define CoreDebug_DEMCR_TRCENA_Msk (1UL << CoreDebug_DEMCR_TRCENA_Pos) /*!< CoreDebug DEMCR: TRCENA Mask */ -#define CoreDebug_DEMCR_MON_REQ_Pos 19 /*!< CoreDebug DEMCR: MON_REQ Position */ -#define CoreDebug_DEMCR_MON_REQ_Msk (1UL << CoreDebug_DEMCR_MON_REQ_Pos) /*!< CoreDebug DEMCR: MON_REQ Mask */ +#define CoreDebug_DEMCR_MON_REQ_Pos 19 /*!< CoreDebug DEMCR: MON_REQ Position */ +#define CoreDebug_DEMCR_MON_REQ_Msk (1UL << CoreDebug_DEMCR_MON_REQ_Pos) /*!< CoreDebug DEMCR: MON_REQ Mask */ -#define CoreDebug_DEMCR_MON_STEP_Pos 18 /*!< CoreDebug DEMCR: MON_STEP Position */ -#define CoreDebug_DEMCR_MON_STEP_Msk (1UL << CoreDebug_DEMCR_MON_STEP_Pos) /*!< CoreDebug DEMCR: MON_STEP Mask */ +#define CoreDebug_DEMCR_MON_STEP_Pos 18 /*!< CoreDebug DEMCR: MON_STEP Position */ +#define CoreDebug_DEMCR_MON_STEP_Msk (1UL << CoreDebug_DEMCR_MON_STEP_Pos) /*!< CoreDebug DEMCR: MON_STEP Mask */ -#define CoreDebug_DEMCR_MON_PEND_Pos 17 /*!< CoreDebug DEMCR: MON_PEND Position */ -#define CoreDebug_DEMCR_MON_PEND_Msk (1UL << CoreDebug_DEMCR_MON_PEND_Pos) /*!< CoreDebug DEMCR: MON_PEND Mask */ +#define CoreDebug_DEMCR_MON_PEND_Pos 17 /*!< CoreDebug DEMCR: MON_PEND Position */ +#define CoreDebug_DEMCR_MON_PEND_Msk (1UL << CoreDebug_DEMCR_MON_PEND_Pos) /*!< CoreDebug DEMCR: MON_PEND Mask */ -#define CoreDebug_DEMCR_MON_EN_Pos 16 /*!< CoreDebug DEMCR: MON_EN Position */ -#define CoreDebug_DEMCR_MON_EN_Msk (1UL << CoreDebug_DEMCR_MON_EN_Pos) /*!< CoreDebug DEMCR: MON_EN Mask */ +#define CoreDebug_DEMCR_MON_EN_Pos 16 /*!< CoreDebug DEMCR: MON_EN Position */ +#define CoreDebug_DEMCR_MON_EN_Msk (1UL << CoreDebug_DEMCR_MON_EN_Pos) /*!< CoreDebug DEMCR: MON_EN Mask */ -#define CoreDebug_DEMCR_VC_HARDERR_Pos 10 /*!< CoreDebug DEMCR: VC_HARDERR Position */ -#define CoreDebug_DEMCR_VC_HARDERR_Msk (1UL << CoreDebug_DEMCR_VC_HARDERR_Pos) /*!< CoreDebug DEMCR: VC_HARDERR Mask */ +#define CoreDebug_DEMCR_VC_HARDERR_Pos 10 /*!< CoreDebug DEMCR: VC_HARDERR Position */ +#define CoreDebug_DEMCR_VC_HARDERR_Msk (1UL << CoreDebug_DEMCR_VC_HARDERR_Pos) /*!< CoreDebug DEMCR: VC_HARDERR Mask */ -#define CoreDebug_DEMCR_VC_INTERR_Pos 9 /*!< CoreDebug DEMCR: VC_INTERR Position */ -#define CoreDebug_DEMCR_VC_INTERR_Msk (1UL << CoreDebug_DEMCR_VC_INTERR_Pos) /*!< CoreDebug DEMCR: VC_INTERR Mask */ +#define CoreDebug_DEMCR_VC_INTERR_Pos 9 /*!< CoreDebug DEMCR: VC_INTERR Position */ +#define CoreDebug_DEMCR_VC_INTERR_Msk (1UL << CoreDebug_DEMCR_VC_INTERR_Pos) /*!< CoreDebug DEMCR: VC_INTERR Mask */ -#define CoreDebug_DEMCR_VC_BUSERR_Pos 8 /*!< CoreDebug DEMCR: VC_BUSERR Position */ -#define CoreDebug_DEMCR_VC_BUSERR_Msk (1UL << CoreDebug_DEMCR_VC_BUSERR_Pos) /*!< CoreDebug DEMCR: VC_BUSERR Mask */ +#define CoreDebug_DEMCR_VC_BUSERR_Pos 8 /*!< CoreDebug DEMCR: VC_BUSERR Position */ +#define CoreDebug_DEMCR_VC_BUSERR_Msk (1UL << CoreDebug_DEMCR_VC_BUSERR_Pos) /*!< CoreDebug DEMCR: VC_BUSERR Mask */ -#define CoreDebug_DEMCR_VC_STATERR_Pos 7 /*!< CoreDebug DEMCR: VC_STATERR Position */ -#define CoreDebug_DEMCR_VC_STATERR_Msk (1UL << CoreDebug_DEMCR_VC_STATERR_Pos) /*!< CoreDebug DEMCR: VC_STATERR Mask */ +#define CoreDebug_DEMCR_VC_STATERR_Pos 7 /*!< CoreDebug DEMCR: VC_STATERR Position */ +#define CoreDebug_DEMCR_VC_STATERR_Msk (1UL << CoreDebug_DEMCR_VC_STATERR_Pos) /*!< CoreDebug DEMCR: VC_STATERR Mask */ -#define CoreDebug_DEMCR_VC_CHKERR_Pos 6 /*!< CoreDebug DEMCR: VC_CHKERR Position */ -#define CoreDebug_DEMCR_VC_CHKERR_Msk (1UL << CoreDebug_DEMCR_VC_CHKERR_Pos) /*!< CoreDebug DEMCR: VC_CHKERR Mask */ +#define CoreDebug_DEMCR_VC_CHKERR_Pos 6 /*!< CoreDebug DEMCR: VC_CHKERR Position */ +#define CoreDebug_DEMCR_VC_CHKERR_Msk (1UL << CoreDebug_DEMCR_VC_CHKERR_Pos) /*!< CoreDebug DEMCR: VC_CHKERR Mask */ -#define CoreDebug_DEMCR_VC_NOCPERR_Pos 5 /*!< CoreDebug DEMCR: VC_NOCPERR Position */ -#define CoreDebug_DEMCR_VC_NOCPERR_Msk (1UL << CoreDebug_DEMCR_VC_NOCPERR_Pos) /*!< CoreDebug DEMCR: VC_NOCPERR Mask */ +#define CoreDebug_DEMCR_VC_NOCPERR_Pos 5 /*!< CoreDebug DEMCR: VC_NOCPERR Position */ +#define CoreDebug_DEMCR_VC_NOCPERR_Msk (1UL << CoreDebug_DEMCR_VC_NOCPERR_Pos) /*!< CoreDebug DEMCR: VC_NOCPERR Mask */ -#define CoreDebug_DEMCR_VC_MMERR_Pos 4 /*!< CoreDebug DEMCR: VC_MMERR Position */ -#define CoreDebug_DEMCR_VC_MMERR_Msk (1UL << CoreDebug_DEMCR_VC_MMERR_Pos) /*!< CoreDebug DEMCR: VC_MMERR Mask */ +#define CoreDebug_DEMCR_VC_MMERR_Pos 4 /*!< CoreDebug DEMCR: VC_MMERR Position */ +#define CoreDebug_DEMCR_VC_MMERR_Msk (1UL << CoreDebug_DEMCR_VC_MMERR_Pos) /*!< CoreDebug DEMCR: VC_MMERR Mask */ -#define CoreDebug_DEMCR_VC_CORERESET_Pos 0 /*!< CoreDebug DEMCR: VC_CORERESET Position */ -#define CoreDebug_DEMCR_VC_CORERESET_Msk (1UL << CoreDebug_DEMCR_VC_CORERESET_Pos) /*!< CoreDebug DEMCR: VC_CORERESET Mask */ +#define CoreDebug_DEMCR_VC_CORERESET_Pos 0 /*!< CoreDebug DEMCR: VC_CORERESET Position */ +#define CoreDebug_DEMCR_VC_CORERESET_Msk (1UL << CoreDebug_DEMCR_VC_CORERESET_Pos) /*!< CoreDebug DEMCR: VC_CORERESET Mask */ /*@} end of group CMSIS_CoreDebug */ - /** \ingroup CMSIS_core_register \defgroup CMSIS_core_base Core Definitions \brief Definitions for base addresses, unions, and structures. @@ -1397,39 +1380,37 @@ typedef struct */ /* Memory mapping of Cortex-M4 Hardware */ -#define SCS_BASE (0xE000E000UL) /*!< System Control Space Base Address */ -#define ITM_BASE (0xE0000000UL) /*!< ITM Base Address */ -#define DWT_BASE (0xE0001000UL) /*!< DWT Base Address */ -#define TPI_BASE (0xE0040000UL) /*!< TPI Base Address */ -#define CoreDebug_BASE (0xE000EDF0UL) /*!< Core Debug Base Address */ -#define SysTick_BASE (SCS_BASE + 0x0010UL) /*!< SysTick Base Address */ -#define NVIC_BASE (SCS_BASE + 0x0100UL) /*!< NVIC Base Address */ -#define SCB_BASE (SCS_BASE + 0x0D00UL) /*!< System Control Block Base Address */ - -#define SCnSCB ((SCnSCB_Type *) SCS_BASE ) /*!< System control Register not in SCB */ -#define SCB ((SCB_Type *) SCB_BASE ) /*!< SCB configuration struct */ -#define SysTick ((SysTick_Type *) SysTick_BASE ) /*!< SysTick configuration struct */ -#define NVIC ((NVIC_Type *) NVIC_BASE ) /*!< NVIC configuration struct */ -#define ITM ((ITM_Type *) ITM_BASE ) /*!< ITM configuration struct */ -#define DWT ((DWT_Type *) DWT_BASE ) /*!< DWT configuration struct */ -#define TPI ((TPI_Type *) TPI_BASE ) /*!< TPI configuration struct */ -#define CoreDebug ((CoreDebug_Type *) CoreDebug_BASE) /*!< Core Debug configuration struct */ +#define SCS_BASE (0xE000E000UL) /*!< System Control Space Base Address */ +#define ITM_BASE (0xE0000000UL) /*!< ITM Base Address */ +#define DWT_BASE (0xE0001000UL) /*!< DWT Base Address */ +#define TPI_BASE (0xE0040000UL) /*!< TPI Base Address */ +#define CoreDebug_BASE (0xE000EDF0UL) /*!< Core Debug Base Address */ +#define SysTick_BASE (SCS_BASE + 0x0010UL) /*!< SysTick Base Address */ +#define NVIC_BASE (SCS_BASE + 0x0100UL) /*!< NVIC Base Address */ +#define SCB_BASE (SCS_BASE + 0x0D00UL) /*!< System Control Block Base Address */ + +#define SCnSCB ((SCnSCB_Type *)SCS_BASE) /*!< System control Register not in SCB */ +#define SCB ((SCB_Type *)SCB_BASE) /*!< SCB configuration struct */ +#define SysTick ((SysTick_Type *)SysTick_BASE) /*!< SysTick configuration struct */ +#define NVIC ((NVIC_Type *)NVIC_BASE) /*!< NVIC configuration struct */ +#define ITM ((ITM_Type *)ITM_BASE) /*!< ITM configuration struct */ +#define DWT ((DWT_Type *)DWT_BASE) /*!< DWT configuration struct */ +#define TPI ((TPI_Type *)TPI_BASE) /*!< TPI configuration struct */ +#define CoreDebug ((CoreDebug_Type *)CoreDebug_BASE) /*!< Core Debug configuration struct */ #if (__MPU_PRESENT == 1) - #define MPU_BASE (SCS_BASE + 0x0D90UL) /*!< Memory Protection Unit */ - #define MPU ((MPU_Type *) MPU_BASE ) /*!< Memory Protection Unit */ +#define MPU_BASE (SCS_BASE + 0x0D90UL) /*!< Memory Protection Unit */ +#define MPU ((MPU_Type *)MPU_BASE) /*!< Memory Protection Unit */ #endif #if (__FPU_PRESENT == 1) - #define FPU_BASE (SCS_BASE + 0x0F30UL) /*!< Floating Point Unit */ - #define FPU ((FPU_Type *) FPU_BASE ) /*!< Floating Point Unit */ +#define FPU_BASE (SCS_BASE + 0x0F30UL) /*!< Floating Point Unit */ +#define FPU ((FPU_Type *)FPU_BASE) /*!< Floating Point Unit */ #endif -/*@} */ - + /*@} */ - -/******************************************************************************* + /******************************************************************************* * Hardware Abstraction Layer Core Function Interface contains: - Core NVIC Functions @@ -1437,19 +1418,17 @@ typedef struct - Core Debug Functions - Core Register Access Functions ******************************************************************************/ -/** \defgroup CMSIS_Core_FunctionInterface Functions and Instructions Reference + /** \defgroup CMSIS_Core_FunctionInterface Functions and Instructions Reference */ - - -/* ########################## NVIC functions #################################### */ -/** \ingroup CMSIS_Core_FunctionInterface + /* ########################## NVIC functions #################################### */ + /** \ingroup CMSIS_Core_FunctionInterface \defgroup CMSIS_Core_NVICFunctions NVIC Functions \brief Functions that manage interrupts and exceptions via the NVIC. @{ */ -/** \brief Set Priority Grouping + /** \brief Set Priority Grouping The function sets the priority grouping field using the required unlock sequence. The parameter PriorityGroup is assigned to the field SCB->AIRCR [10:8] PRIGROUP field. @@ -1459,58 +1438,54 @@ typedef struct \param [in] PriorityGroup Priority grouping field. */ -__STATIC_INLINE void NVIC_SetPriorityGrouping(uint32_t PriorityGroup) -{ - uint32_t reg_value; - uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07); /* only values 0..7 are used */ - - reg_value = SCB->AIRCR; /* read old register configuration */ - reg_value &= ~(SCB_AIRCR_VECTKEY_Msk | SCB_AIRCR_PRIGROUP_Msk); /* clear bits to change */ - reg_value = (reg_value | - ((uint32_t)0x5FA << SCB_AIRCR_VECTKEY_Pos) | - (PriorityGroupTmp << 8)); /* Insert write key and priorty group */ - SCB->AIRCR = reg_value; -} + __STATIC_INLINE void NVIC_SetPriorityGrouping(uint32_t PriorityGroup) + { + uint32_t reg_value; + uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07); /* only values 0..7 are used */ + reg_value = SCB->AIRCR; /* read old register configuration */ + reg_value &= ~(SCB_AIRCR_VECTKEY_Msk | SCB_AIRCR_PRIGROUP_Msk); /* clear bits to change */ + reg_value = (reg_value | + ((uint32_t)0x5FA << SCB_AIRCR_VECTKEY_Pos) | + (PriorityGroupTmp << 8)); /* Insert write key and priorty group */ + SCB->AIRCR = reg_value; + } -/** \brief Get Priority Grouping + /** \brief Get Priority Grouping The function reads the priority grouping field from the NVIC Interrupt Controller. \return Priority grouping field (SCB->AIRCR [10:8] PRIGROUP field). */ -__STATIC_INLINE uint32_t NVIC_GetPriorityGrouping(void) -{ - return ((SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) >> SCB_AIRCR_PRIGROUP_Pos); /* read priority grouping field */ -} - + __STATIC_INLINE uint32_t NVIC_GetPriorityGrouping(void) + { + return ((SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) >> SCB_AIRCR_PRIGROUP_Pos); /* read priority grouping field */ + } -/** \brief Enable External Interrupt + /** \brief Enable External Interrupt The function enables a device-specific interrupt in the NVIC interrupt controller. \param [in] IRQn External interrupt number. Value cannot be negative. */ -__STATIC_INLINE void NVIC_EnableIRQ(IRQn_Type IRQn) -{ -/* NVIC->ISER[((uint32_t)(IRQn) >> 5)] = (1 << ((uint32_t)(IRQn) & 0x1F)); enable interrupt */ - NVIC->ISER[(uint32_t)((int32_t)IRQn) >> 5] = (uint32_t)(1 << ((uint32_t)((int32_t)IRQn) & (uint32_t)0x1F)); /* enable interrupt */ -} + __STATIC_INLINE void NVIC_EnableIRQ(IRQn_Type IRQn) + { + /* NVIC->ISER[((uint32_t)(IRQn) >> 5)] = (1 << ((uint32_t)(IRQn) & 0x1F)); enable interrupt */ + NVIC->ISER[(uint32_t)((int32_t)IRQn) >> 5] = (uint32_t)(1 << ((uint32_t)((int32_t)IRQn) & (uint32_t)0x1F)); /* enable interrupt */ + } - -/** \brief Disable External Interrupt + /** \brief Disable External Interrupt The function disables a device-specific interrupt in the NVIC interrupt controller. \param [in] IRQn External interrupt number. Value cannot be negative. */ -__STATIC_INLINE void NVIC_DisableIRQ(IRQn_Type IRQn) -{ - NVIC->ICER[((uint32_t)(IRQn) >> 5)] = (1 << ((uint32_t)(IRQn) & 0x1F)); /* disable interrupt */ -} + __STATIC_INLINE void NVIC_DisableIRQ(IRQn_Type IRQn) + { + NVIC->ICER[((uint32_t)(IRQn) >> 5)] = (1 << ((uint32_t)(IRQn)&0x1F)); /* disable interrupt */ + } - -/** \brief Get Pending Interrupt + /** \brief Get Pending Interrupt The function reads the pending register in the NVIC and returns the pending bit for the specified interrupt. @@ -1520,37 +1495,34 @@ __STATIC_INLINE void NVIC_DisableIRQ(IRQn_Type IRQn) \return 0 Interrupt status is not pending. \return 1 Interrupt status is pending. */ -__STATIC_INLINE uint32_t NVIC_GetPendingIRQ(IRQn_Type IRQn) -{ - return((uint32_t) ((NVIC->ISPR[(uint32_t)(IRQn) >> 5] & (1 << ((uint32_t)(IRQn) & 0x1F)))?1:0)); /* Return 1 if pending else 0 */ -} - + __STATIC_INLINE uint32_t NVIC_GetPendingIRQ(IRQn_Type IRQn) + { + return ((uint32_t)((NVIC->ISPR[(uint32_t)(IRQn) >> 5] & (1 << ((uint32_t)(IRQn)&0x1F))) ? 1 : 0)); /* Return 1 if pending else 0 */ + } -/** \brief Set Pending Interrupt + /** \brief Set Pending Interrupt The function sets the pending bit of an external interrupt. \param [in] IRQn Interrupt number. Value cannot be negative. */ -__STATIC_INLINE void NVIC_SetPendingIRQ(IRQn_Type IRQn) -{ - NVIC->ISPR[((uint32_t)(IRQn) >> 5)] = (1 << ((uint32_t)(IRQn) & 0x1F)); /* set interrupt pending */ -} - + __STATIC_INLINE void NVIC_SetPendingIRQ(IRQn_Type IRQn) + { + NVIC->ISPR[((uint32_t)(IRQn) >> 5)] = (1 << ((uint32_t)(IRQn)&0x1F)); /* set interrupt pending */ + } -/** \brief Clear Pending Interrupt + /** \brief Clear Pending Interrupt The function clears the pending bit of an external interrupt. \param [in] IRQn External interrupt number. Value cannot be negative. */ -__STATIC_INLINE void NVIC_ClearPendingIRQ(IRQn_Type IRQn) -{ - NVIC->ICPR[((uint32_t)(IRQn) >> 5)] = (1 << ((uint32_t)(IRQn) & 0x1F)); /* Clear pending interrupt */ -} + __STATIC_INLINE void NVIC_ClearPendingIRQ(IRQn_Type IRQn) + { + NVIC->ICPR[((uint32_t)(IRQn) >> 5)] = (1 << ((uint32_t)(IRQn)&0x1F)); /* Clear pending interrupt */ + } - -/** \brief Get Active Interrupt + /** \brief Get Active Interrupt The function reads the active register in NVIC and returns the active bit. @@ -1559,13 +1531,12 @@ __STATIC_INLINE void NVIC_ClearPendingIRQ(IRQn_Type IRQn) \return 0 Interrupt status is not active. \return 1 Interrupt status is active. */ -__STATIC_INLINE uint32_t NVIC_GetActive(IRQn_Type IRQn) -{ - return((uint32_t)((NVIC->IABR[(uint32_t)(IRQn) >> 5] & (1 << ((uint32_t)(IRQn) & 0x1F)))?1:0)); /* Return 1 if active else 0 */ -} - + __STATIC_INLINE uint32_t NVIC_GetActive(IRQn_Type IRQn) + { + return ((uint32_t)((NVIC->IABR[(uint32_t)(IRQn) >> 5] & (1 << ((uint32_t)(IRQn)&0x1F))) ? 1 : 0)); /* Return 1 if active else 0 */ + } -/** \brief Set Interrupt Priority + /** \brief Set Interrupt Priority The function sets the priority of an interrupt. @@ -1574,16 +1545,19 @@ __STATIC_INLINE uint32_t NVIC_GetActive(IRQn_Type IRQn) \param [in] IRQn Interrupt number. \param [in] priority Priority to set. */ -__STATIC_INLINE void NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority) -{ - if(IRQn < 0) { - SCB->SHP[((uint32_t)(IRQn) & 0xF)-4] = ((priority << (8 - __NVIC_PRIO_BITS)) & 0xff); } /* set Priority for Cortex-M System Interrupts */ - else { - NVIC->IP[(uint32_t)(IRQn)] = ((priority << (8 - __NVIC_PRIO_BITS)) & 0xff); } /* set Priority for device specific Interrupts */ -} - - -/** \brief Get Interrupt Priority + __STATIC_INLINE void NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority) + { + if (IRQn < 0) + { + SCB->SHP[((uint32_t)(IRQn)&0xF) - 4] = ((priority << (8 - __NVIC_PRIO_BITS)) & 0xff); + } /* set Priority for Cortex-M System Interrupts */ + else + { + NVIC->IP[(uint32_t)(IRQn)] = ((priority << (8 - __NVIC_PRIO_BITS)) & 0xff); + } /* set Priority for device specific Interrupts */ + } + + /** \brief Get Interrupt Priority The function reads the priority of an interrupt. The interrupt number can be positive to specify an external (device specific) @@ -1594,17 +1568,20 @@ __STATIC_INLINE void NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority) \return Interrupt Priority. Value is aligned automatically to the implemented priority bits of the microcontroller. */ -__STATIC_INLINE uint32_t NVIC_GetPriority(IRQn_Type IRQn) -{ + __STATIC_INLINE uint32_t NVIC_GetPriority(IRQn_Type IRQn) + { - if(IRQn < 0) { - return((uint32_t)(SCB->SHP[((uint32_t)(IRQn) & 0xF)-4] >> (8 - __NVIC_PRIO_BITS))); } /* get priority for Cortex-M system interrupts */ - else { - return((uint32_t)(NVIC->IP[(uint32_t)(IRQn)] >> (8 - __NVIC_PRIO_BITS))); } /* get priority for device specific interrupts */ -} + if (IRQn < 0) + { + return ((uint32_t)(SCB->SHP[((uint32_t)(IRQn)&0xF) - 4] >> (8 - __NVIC_PRIO_BITS))); + } /* get priority for Cortex-M system interrupts */ + else + { + return ((uint32_t)(NVIC->IP[(uint32_t)(IRQn)] >> (8 - __NVIC_PRIO_BITS))); + } /* get priority for device specific interrupts */ + } - -/** \brief Encode Priority + /** \brief Encode Priority The function encodes the priority for an interrupt with the given priority group, preemptive priority value, and subpriority value. @@ -1616,23 +1593,21 @@ __STATIC_INLINE uint32_t NVIC_GetPriority(IRQn_Type IRQn) \param [in] SubPriority Subpriority value (starting from 0). \return Encoded priority. Value can be used in the function \ref NVIC_SetPriority(). */ -__STATIC_INLINE uint32_t NVIC_EncodePriority (uint32_t PriorityGroup, uint32_t PreemptPriority, uint32_t SubPriority) -{ - uint32_t PriorityGroupTmp = (PriorityGroup & 0x07); /* only values 0..7 are used */ - uint32_t PreemptPriorityBits; - uint32_t SubPriorityBits; + __STATIC_INLINE uint32_t NVIC_EncodePriority(uint32_t PriorityGroup, uint32_t PreemptPriority, uint32_t SubPriority) + { + uint32_t PriorityGroupTmp = (PriorityGroup & 0x07); /* only values 0..7 are used */ + uint32_t PreemptPriorityBits; + uint32_t SubPriorityBits; - PreemptPriorityBits = ((7 - PriorityGroupTmp) > __NVIC_PRIO_BITS) ? __NVIC_PRIO_BITS : 7 - PriorityGroupTmp; - SubPriorityBits = ((PriorityGroupTmp + __NVIC_PRIO_BITS) < 7) ? 0 : PriorityGroupTmp - 7 + __NVIC_PRIO_BITS; - - return ( - ((PreemptPriority & ((1 << (PreemptPriorityBits)) - 1)) << SubPriorityBits) | - ((SubPriority & ((1 << (SubPriorityBits )) - 1))) - ); -} + PreemptPriorityBits = ((7 - PriorityGroupTmp) > __NVIC_PRIO_BITS) ? __NVIC_PRIO_BITS : 7 - PriorityGroupTmp; + SubPriorityBits = ((PriorityGroupTmp + __NVIC_PRIO_BITS) < 7) ? 0 : PriorityGroupTmp - 7 + __NVIC_PRIO_BITS; + return ( + ((PreemptPriority & ((1 << (PreemptPriorityBits)) - 1)) << SubPriorityBits) | + ((SubPriority & ((1 << (SubPriorityBits)) - 1)))); + } -/** \brief Decode Priority + /** \brief Decode Priority The function decodes an interrupt priority value with a given priority group to preemptive priority value and subpriority value. @@ -1644,41 +1619,39 @@ __STATIC_INLINE uint32_t NVIC_EncodePriority (uint32_t PriorityGroup, uint32_t P \param [out] pPreemptPriority Preemptive priority value (starting from 0). \param [out] pSubPriority Subpriority value (starting from 0). */ -__STATIC_INLINE void NVIC_DecodePriority (uint32_t Priority, uint32_t PriorityGroup, uint32_t* pPreemptPriority, uint32_t* pSubPriority) -{ - uint32_t PriorityGroupTmp = (PriorityGroup & 0x07); /* only values 0..7 are used */ - uint32_t PreemptPriorityBits; - uint32_t SubPriorityBits; + __STATIC_INLINE void NVIC_DecodePriority(uint32_t Priority, uint32_t PriorityGroup, uint32_t *pPreemptPriority, uint32_t *pSubPriority) + { + uint32_t PriorityGroupTmp = (PriorityGroup & 0x07); /* only values 0..7 are used */ + uint32_t PreemptPriorityBits; + uint32_t SubPriorityBits; - PreemptPriorityBits = ((7 - PriorityGroupTmp) > __NVIC_PRIO_BITS) ? __NVIC_PRIO_BITS : 7 - PriorityGroupTmp; - SubPriorityBits = ((PriorityGroupTmp + __NVIC_PRIO_BITS) < 7) ? 0 : PriorityGroupTmp - 7 + __NVIC_PRIO_BITS; - - *pPreemptPriority = (Priority >> SubPriorityBits) & ((1 << (PreemptPriorityBits)) - 1); - *pSubPriority = (Priority ) & ((1 << (SubPriorityBits )) - 1); -} + PreemptPriorityBits = ((7 - PriorityGroupTmp) > __NVIC_PRIO_BITS) ? __NVIC_PRIO_BITS : 7 - PriorityGroupTmp; + SubPriorityBits = ((PriorityGroupTmp + __NVIC_PRIO_BITS) < 7) ? 0 : PriorityGroupTmp - 7 + __NVIC_PRIO_BITS; + *pPreemptPriority = (Priority >> SubPriorityBits) & ((1 << (PreemptPriorityBits)) - 1); + *pSubPriority = (Priority) & ((1 << (SubPriorityBits)) - 1); + } -/** \brief System Reset + /** \brief System Reset The function initiates a system reset request to reset the MCU. */ -__STATIC_INLINE void NVIC_SystemReset(void) -{ - __DSB(); /* Ensure all outstanding memory accesses included + __STATIC_INLINE void NVIC_SystemReset(void) + { + __DSB(); /* Ensure all outstanding memory accesses included buffered write are completed before reset */ - SCB->AIRCR = ((0x5FA << SCB_AIRCR_VECTKEY_Pos) | - (SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) | - SCB_AIRCR_SYSRESETREQ_Msk); /* Keep priority group unchanged */ - __DSB(); /* Ensure completion of memory access */ - while(1); /* wait until reset */ -} - -/*@} end of CMSIS_Core_NVICFunctions */ - - - -/* ################################## SysTick function ############################################ */ -/** \ingroup CMSIS_Core_FunctionInterface + SCB->AIRCR = ((0x5FA << SCB_AIRCR_VECTKEY_Pos) | + (SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) | + SCB_AIRCR_SYSRESETREQ_Msk); /* Keep priority group unchanged */ + __DSB(); /* Ensure completion of memory access */ + while (1) + ; /* wait until reset */ + } + + /*@} end of CMSIS_Core_NVICFunctions */ + + /* ################################## SysTick function ############################################ */ + /** \ingroup CMSIS_Core_FunctionInterface \defgroup CMSIS_Core_SysTickFunctions SysTick Functions \brief Functions that configure the System. @{ @@ -1686,7 +1659,7 @@ __STATIC_INLINE void NVIC_SystemReset(void) #if (__Vendor_SysTickConfig == 0) -/** \brief System Tick Configuration + /** \brief System Tick Configuration The function initializes the System Timer and its interrupt, and starts the System Tick Timer. Counter is in free running mode to generate periodic interrupts. @@ -1701,37 +1674,35 @@ __STATIC_INLINE void NVIC_SystemReset(void) must contain a vendor-specific implementation of this function. */ -__STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks) -{ - if ((ticks - 1) > SysTick_LOAD_RELOAD_Msk) return (1); /* Reload value impossible */ - - SysTick->LOAD = ticks - 1; /* set reload register */ - NVIC_SetPriority (SysTick_IRQn, (1<<__NVIC_PRIO_BITS) - 1); /* set Priority for Systick Interrupt */ - SysTick->VAL = 0; /* Load the SysTick Counter Value */ - SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk | - SysTick_CTRL_TICKINT_Msk | - SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */ - return (0); /* Function successful */ -} + __STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks) + { + if ((ticks - 1) > SysTick_LOAD_RELOAD_Msk) + return (1); /* Reload value impossible */ + + SysTick->LOAD = ticks - 1; /* set reload register */ + NVIC_SetPriority(SysTick_IRQn, (1 << __NVIC_PRIO_BITS) - 1); /* set Priority for Systick Interrupt */ + SysTick->VAL = 0; /* Load the SysTick Counter Value */ + SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk | + SysTick_CTRL_TICKINT_Msk | + SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */ + return (0); /* Function successful */ + } #endif -/*@} end of CMSIS_Core_SysTickFunctions */ - + /*@} end of CMSIS_Core_SysTickFunctions */ - -/* ##################################### Debug In/Output function ########################################### */ -/** \ingroup CMSIS_Core_FunctionInterface + /* ##################################### Debug In/Output function ########################################### */ + /** \ingroup CMSIS_Core_FunctionInterface \defgroup CMSIS_core_DebugFunctions ITM Functions \brief Functions that access the ITM debug interface. @{ */ -extern volatile int32_t ITM_RxBuffer; /*!< External variable to receive characters. */ -#define ITM_RXBUFFER_EMPTY 0x5AA55AA5 /*!< Value identifying \ref ITM_RxBuffer is ready for next character. */ - + extern volatile int32_t ITM_RxBuffer; /*!< External variable to receive characters. */ +#define ITM_RXBUFFER_EMPTY 0x5AA55AA5 /*!< Value identifying \ref ITM_RxBuffer is ready for next character. */ -/** \brief ITM Send Character + /** \brief ITM Send Character The function transmits a character via the ITM channel 0, and \li Just returns when no debugger is connected that has booked the output. @@ -1741,57 +1712,59 @@ extern volatile int32_t ITM_RxBuffer; /*!< External variable \returns Character to transmit. */ -__STATIC_INLINE uint32_t ITM_SendChar (uint32_t ch) -{ - if ((ITM->TCR & ITM_TCR_ITMENA_Msk) && /* ITM enabled */ - (ITM->TER & (1UL << 0) ) ) /* ITM Port #0 enabled */ - { - while (ITM->PORT[0].u32 == 0); - ITM->PORT[0].u8 = (uint8_t) ch; - } - return (ch); -} - - -/** \brief ITM Receive Character + __STATIC_INLINE uint32_t ITM_SendChar(uint32_t ch) + { + if ((ITM->TCR & ITM_TCR_ITMENA_Msk) && /* ITM enabled */ + (ITM->TER & (1UL << 0))) /* ITM Port #0 enabled */ + { + while (ITM->PORT[0].u32 == 0) + ; + ITM->PORT[0].u8 = (uint8_t)ch; + } + return (ch); + } + + /** \brief ITM Receive Character The function inputs a character via the external variable \ref ITM_RxBuffer. \return Received character. \return -1 No character pending. */ -__STATIC_INLINE int32_t ITM_ReceiveChar (void) { - int32_t ch = -1; /* no character available */ - - if (ITM_RxBuffer != ITM_RXBUFFER_EMPTY) { - ch = ITM_RxBuffer; - ITM_RxBuffer = ITM_RXBUFFER_EMPTY; /* ready for next character */ - } + __STATIC_INLINE int32_t ITM_ReceiveChar(void) + { + int32_t ch = -1; /* no character available */ - return (ch); -} + if (ITM_RxBuffer != ITM_RXBUFFER_EMPTY) + { + ch = ITM_RxBuffer; + ITM_RxBuffer = ITM_RXBUFFER_EMPTY; /* ready for next character */ + } + return (ch); + } -/** \brief ITM Check Character + /** \brief ITM Check Character The function checks whether a character is pending for reading in the variable \ref ITM_RxBuffer. \return 0 No character available. \return 1 Character available. */ -__STATIC_INLINE int32_t ITM_CheckChar (void) { - - if (ITM_RxBuffer == ITM_RXBUFFER_EMPTY) { - return (0); /* no character available */ - } else { - return (1); /* character available */ - } -} - -/*@} end of CMSIS_core_DebugFunctions */ - - - + __STATIC_INLINE int32_t ITM_CheckChar(void) + { + + if (ITM_RxBuffer == ITM_RXBUFFER_EMPTY) + { + return (0); /* no character available */ + } + else + { + return (1); /* character available */ + } + } + + /*@} end of CMSIS_core_DebugFunctions */ #ifdef __cplusplus } diff --git a/bsp/swm320-lq100/Libraries/CMSIS/CoreSupport/core_cm7.h b/bsp/swm320-lq100/Libraries/CMSIS/CoreSupport/core_cm7.h index 242540f8b1..265d3bc735 100644 --- a/bsp/swm320-lq100/Libraries/CMSIS/CoreSupport/core_cm7.h +++ b/bsp/swm320-lq100/Libraries/CMSIS/CoreSupport/core_cm7.h @@ -1,4 +1,4 @@ -/**************************************************************************//** +/**************************************************************************/ /** * @file core_cm7.h * @brief CMSIS Cortex-M7 Core Peripheral Access Layer Header File * @version V4.00 @@ -34,16 +34,16 @@ POSSIBILITY OF SUCH DAMAGE. ---------------------------------------------------------------------------*/ - -#if defined ( __ICCARM__ ) - #pragma system_include /* treat file as system include file for MISRA check */ +#if defined(__ICCARM__) +#pragma system_include /* treat file as system include file for MISRA check */ #endif #ifndef __CORE_CM7_H_GENERIC #define __CORE_CM7_H_GENERIC #ifdef __cplusplus - extern "C" { +extern "C" +{ #endif /** \page CMSIS_MISRA_Exceptions MISRA-C:2004 Compliance Exceptions @@ -59,7 +59,6 @@ Function-like macros are used to allow more efficient code. */ - /******************************************************************************* * CMSIS definitions ******************************************************************************/ @@ -68,126 +67,125 @@ */ /* CMSIS CM7 definitions */ -#define __CM7_CMSIS_VERSION_MAIN (0x04) /*!< [31:16] CMSIS HAL main version */ -#define __CM7_CMSIS_VERSION_SUB (0x00) /*!< [15:0] CMSIS HAL sub version */ -#define __CM7_CMSIS_VERSION ((__CM7_CMSIS_VERSION_MAIN << 16) | \ - __CM7_CMSIS_VERSION_SUB ) /*!< CMSIS HAL version number */ - -#define __CORTEX_M (0x07) /*!< Cortex-M Core */ +#define __CM7_CMSIS_VERSION_MAIN (0x04) /*!< [31:16] CMSIS HAL main version */ +#define __CM7_CMSIS_VERSION_SUB (0x00) /*!< [15:0] CMSIS HAL sub version */ +#define __CM7_CMSIS_VERSION ((__CM7_CMSIS_VERSION_MAIN << 16) | \ + __CM7_CMSIS_VERSION_SUB) /*!< CMSIS HAL version number */ + +#define __CORTEX_M (0x07) /*!< Cortex-M Core */ + +#if defined(__CC_ARM) +#define __ASM __asm /*!< asm keyword for ARM Compiler */ +#define __INLINE __inline /*!< inline keyword for ARM Compiler */ +#define __STATIC_INLINE static __inline + +#elif defined(__GNUC__) +#define __ASM __asm /*!< asm keyword for GNU Compiler */ +#define __INLINE inline /*!< inline keyword for GNU Compiler */ +#define __STATIC_INLINE static inline + +#elif defined(__ICCARM__) +#define __ASM __asm /*!< asm keyword for IAR Compiler */ +#define __INLINE inline /*!< inline keyword for IAR Compiler. Only available in High optimization mode! */ +#define __STATIC_INLINE static inline + +#elif defined(__TMS470__) +#define __ASM __asm /*!< asm keyword for TI CCS Compiler */ +#define __STATIC_INLINE static inline + +#elif defined(__TASKING__) +#define __ASM __asm /*!< asm keyword for TASKING Compiler */ +#define __INLINE inline /*!< inline keyword for TASKING Compiler */ +#define __STATIC_INLINE static inline + +#elif defined(__CSMC__) +#define __packed +#define __ASM _asm /*!< asm keyword for COSMIC Compiler */ +#define __INLINE inline /*use -pc99 on compile line !< inline keyword for COSMIC Compiler */ +#define __STATIC_INLINE static inline +#endif -#if defined ( __CC_ARM ) - #define __ASM __asm /*!< asm keyword for ARM Compiler */ - #define __INLINE __inline /*!< inline keyword for ARM Compiler */ - #define __STATIC_INLINE static __inline - -#elif defined ( __GNUC__ ) - #define __ASM __asm /*!< asm keyword for GNU Compiler */ - #define __INLINE inline /*!< inline keyword for GNU Compiler */ - #define __STATIC_INLINE static inline - -#elif defined ( __ICCARM__ ) - #define __ASM __asm /*!< asm keyword for IAR Compiler */ - #define __INLINE inline /*!< inline keyword for IAR Compiler. Only available in High optimization mode! */ - #define __STATIC_INLINE static inline +/** __FPU_USED indicates whether an FPU is used or not. + For this, __FPU_PRESENT has to be checked prior to making use of FPU specific registers and functions. +*/ +#if defined(__CC_ARM) +#if defined __TARGET_FPU_VFP +#if (__FPU_PRESENT == 1) +#define __FPU_USED 1 +#else +#warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" +#define __FPU_USED 0 +#endif +#else +#define __FPU_USED 0 +#endif -#elif defined ( __TMS470__ ) - #define __ASM __asm /*!< asm keyword for TI CCS Compiler */ - #define __STATIC_INLINE static inline +#elif defined(__GNUC__) +#if defined(__VFP_FP__) && !defined(__SOFTFP__) +#if (__FPU_PRESENT == 1) +#define __FPU_USED 1 +#else +#warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" +#define __FPU_USED 0 +#endif +#else +#define __FPU_USED 0 +#endif -#elif defined ( __TASKING__ ) - #define __ASM __asm /*!< asm keyword for TASKING Compiler */ - #define __INLINE inline /*!< inline keyword for TASKING Compiler */ - #define __STATIC_INLINE static inline +#elif defined(__ICCARM__) +#if defined __ARMVFP__ +#if (__FPU_PRESENT == 1) +#define __FPU_USED 1 +#else +#warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" +#define __FPU_USED 0 +#endif +#else +#define __FPU_USED 0 +#endif -#elif defined ( __CSMC__ ) - #define __packed - #define __ASM _asm /*!< asm keyword for COSMIC Compiler */ - #define __INLINE inline /*use -pc99 on compile line !< inline keyword for COSMIC Compiler */ - #define __STATIC_INLINE static inline +#elif defined(__TMS470__) +#if defined __TI_VFP_SUPPORT__ +#if (__FPU_PRESENT == 1) +#define __FPU_USED 1 +#else +#warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" +#define __FPU_USED 0 +#endif +#else +#define __FPU_USED 0 +#endif +#elif defined(__TASKING__) +#if defined __FPU_VFP__ +#if (__FPU_PRESENT == 1) +#define __FPU_USED 1 +#else +#error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" +#define __FPU_USED 0 +#endif +#else +#define __FPU_USED 0 #endif -/** __FPU_USED indicates whether an FPU is used or not. - For this, __FPU_PRESENT has to be checked prior to making use of FPU specific registers and functions. -*/ -#if defined ( __CC_ARM ) - #if defined __TARGET_FPU_VFP - #if (__FPU_PRESENT == 1) - #define __FPU_USED 1 - #else - #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" - #define __FPU_USED 0 - #endif - #else - #define __FPU_USED 0 - #endif - -#elif defined ( __GNUC__ ) - #if defined (__VFP_FP__) && !defined(__SOFTFP__) - #if (__FPU_PRESENT == 1) - #define __FPU_USED 1 - #else - #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" - #define __FPU_USED 0 - #endif - #else - #define __FPU_USED 0 - #endif - -#elif defined ( __ICCARM__ ) - #if defined __ARMVFP__ - #if (__FPU_PRESENT == 1) - #define __FPU_USED 1 - #else - #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" - #define __FPU_USED 0 - #endif - #else - #define __FPU_USED 0 - #endif - -#elif defined ( __TMS470__ ) - #if defined __TI_VFP_SUPPORT__ - #if (__FPU_PRESENT == 1) - #define __FPU_USED 1 - #else - #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" - #define __FPU_USED 0 - #endif - #else - #define __FPU_USED 0 - #endif - -#elif defined ( __TASKING__ ) - #if defined __FPU_VFP__ - #if (__FPU_PRESENT == 1) - #define __FPU_USED 1 - #else - #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" - #define __FPU_USED 0 - #endif - #else - #define __FPU_USED 0 - #endif - -#elif defined ( __CSMC__ ) /* Cosmic */ - #if ( __CSMC__ & 0x400) // FPU present for parser - #if (__FPU_PRESENT == 1) - #define __FPU_USED 1 - #else - #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" - #define __FPU_USED 0 - #endif - #else - #define __FPU_USED 0 - #endif +#elif defined(__CSMC__) /* Cosmic */ +#if (__CSMC__ & 0x400) // FPU present for parser +#if (__FPU_PRESENT == 1) +#define __FPU_USED 1 +#else +#error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" +#define __FPU_USED 0 +#endif +#else +#define __FPU_USED 0 +#endif #endif -#include /* standard types definitions */ -#include /* Core Instruction Access */ -#include /* Core Function Access */ -#include /* Compiler specific SIMD Intrinsics */ +#include /* standard types definitions */ +#include /* Core Instruction Access */ +#include /* Core Function Access */ +#include /* Compiler specific SIMD Intrinsics */ #ifdef __cplusplus } @@ -201,50 +199,51 @@ #define __CORE_CM7_H_DEPENDANT #ifdef __cplusplus - extern "C" { +extern "C" +{ #endif /* check device defines and use defaults */ #if defined __CHECK_DEVICE_DEFINES - #ifndef __CM7_REV - #define __CM7_REV 0x0000 - #warning "__CM7_REV not defined in device header file; using default!" - #endif - - #ifndef __FPU_PRESENT - #define __FPU_PRESENT 0 - #warning "__FPU_PRESENT not defined in device header file; using default!" - #endif - - #ifndef __MPU_PRESENT - #define __MPU_PRESENT 0 - #warning "__MPU_PRESENT not defined in device header file; using default!" - #endif - - #ifndef __ICACHE_PRESENT - #define __ICACHE_PRESENT 0 - #warning "__ICACHE_PRESENT not defined in device header file; using default!" - #endif - - #ifndef __DCACHE_PRESENT - #define __DCACHE_PRESENT 0 - #warning "__DCACHE_PRESENT not defined in device header file; using default!" - #endif - - #ifndef __DTCM_PRESENT - #define __DTCM_PRESENT 0 - #warning "__DTCM_PRESENT not defined in device header file; using default!" - #endif - - #ifndef __NVIC_PRIO_BITS - #define __NVIC_PRIO_BITS 3 - #warning "__NVIC_PRIO_BITS not defined in device header file; using default!" - #endif - - #ifndef __Vendor_SysTickConfig - #define __Vendor_SysTickConfig 0 - #warning "__Vendor_SysTickConfig not defined in device header file; using default!" - #endif +#ifndef __CM7_REV +#define __CM7_REV 0x0000 +#warning "__CM7_REV not defined in device header file; using default!" +#endif + +#ifndef __FPU_PRESENT +#define __FPU_PRESENT 0 +#warning "__FPU_PRESENT not defined in device header file; using default!" +#endif + +#ifndef __MPU_PRESENT +#define __MPU_PRESENT 0 +#warning "__MPU_PRESENT not defined in device header file; using default!" +#endif + +#ifndef __ICACHE_PRESENT +#define __ICACHE_PRESENT 0 +#warning "__ICACHE_PRESENT not defined in device header file; using default!" +#endif + +#ifndef __DCACHE_PRESENT +#define __DCACHE_PRESENT 0 +#warning "__DCACHE_PRESENT not defined in device header file; using default!" +#endif + +#ifndef __DTCM_PRESENT +#define __DTCM_PRESENT 0 +#warning "__DTCM_PRESENT not defined in device header file; using default!" +#endif + +#ifndef __NVIC_PRIO_BITS +#define __NVIC_PRIO_BITS 3 +#warning "__NVIC_PRIO_BITS not defined in device header file; using default!" +#endif + +#ifndef __Vendor_SysTickConfig +#define __Vendor_SysTickConfig 0 +#warning "__Vendor_SysTickConfig not defined in device header file; using default!" +#endif #endif /* IO definitions (access restrictions to peripheral registers) */ @@ -256,18 +255,16 @@ \li for automatic generation of peripheral register debug information. */ #ifdef __cplusplus - #define __I volatile /*!< Defines 'read only' permissions */ +#define __I volatile /*!< Defines 'read only' permissions */ #else - #define __I volatile const /*!< Defines 'read only' permissions */ +#define __I volatile const /*!< Defines 'read only' permissions */ #endif -#define __O volatile /*!< Defines 'write only' permissions */ -#define __IO volatile /*!< Defines 'read / write' permissions */ - -/*@} end of group Cortex_M7 */ - +#define __O volatile /*!< Defines 'write only' permissions */ +#define __IO volatile /*!< Defines 'read / write' permissions */ + /*@} end of group Cortex_M7 */ -/******************************************************************************* + /******************************************************************************* * Register Abstraction Core Register contain: - Core Register @@ -278,1305 +275,1291 @@ - Core MPU Register - Core FPU Register ******************************************************************************/ -/** \defgroup CMSIS_core_register Defines and Type Definitions + /** \defgroup CMSIS_core_register Defines and Type Definitions \brief Type definitions and defines for Cortex-M processor based devices. */ -/** \ingroup CMSIS_core_register + /** \ingroup CMSIS_core_register \defgroup CMSIS_CORE Status and Control Registers \brief Core Register type definitions. @{ */ -/** \brief Union type to access the Application Program Status Register (APSR). + /** \brief Union type to access the Application Program Status Register (APSR). */ -typedef union -{ - struct - { + typedef union + { + struct + { #if (__CORTEX_M != 0x07) - uint32_t _reserved0:27; /*!< bit: 0..26 Reserved */ + uint32_t _reserved0 : 27; /*!< bit: 0..26 Reserved */ #else - uint32_t _reserved0:16; /*!< bit: 0..15 Reserved */ - uint32_t GE:4; /*!< bit: 16..19 Greater than or Equal flags */ - uint32_t _reserved1:7; /*!< bit: 20..26 Reserved */ + uint32_t _reserved0 : 16; /*!< bit: 0..15 Reserved */ + uint32_t GE : 4; /*!< bit: 16..19 Greater than or Equal flags */ + uint32_t _reserved1 : 7; /*!< bit: 20..26 Reserved */ #endif - uint32_t Q:1; /*!< bit: 27 Saturation condition flag */ - uint32_t V:1; /*!< bit: 28 Overflow condition code flag */ - uint32_t C:1; /*!< bit: 29 Carry condition code flag */ - uint32_t Z:1; /*!< bit: 30 Zero condition code flag */ - uint32_t N:1; /*!< bit: 31 Negative condition code flag */ - } b; /*!< Structure used for bit access */ - uint32_t w; /*!< Type used for word access */ -} APSR_Type; - - -/** \brief Union type to access the Interrupt Program Status Register (IPSR). + uint32_t Q : 1; /*!< bit: 27 Saturation condition flag */ + uint32_t V : 1; /*!< bit: 28 Overflow condition code flag */ + uint32_t C : 1; /*!< bit: 29 Carry condition code flag */ + uint32_t Z : 1; /*!< bit: 30 Zero condition code flag */ + uint32_t N : 1; /*!< bit: 31 Negative condition code flag */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ + } APSR_Type; + + /** \brief Union type to access the Interrupt Program Status Register (IPSR). */ -typedef union -{ - struct - { - uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */ - uint32_t _reserved0:23; /*!< bit: 9..31 Reserved */ - } b; /*!< Structure used for bit access */ - uint32_t w; /*!< Type used for word access */ -} IPSR_Type; - - -/** \brief Union type to access the Special-Purpose Program Status Registers (xPSR). + typedef union + { + struct + { + uint32_t ISR : 9; /*!< bit: 0.. 8 Exception number */ + uint32_t _reserved0 : 23; /*!< bit: 9..31 Reserved */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ + } IPSR_Type; + + /** \brief Union type to access the Special-Purpose Program Status Registers (xPSR). */ -typedef union -{ - struct - { - uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */ + typedef union + { + struct + { + uint32_t ISR : 9; /*!< bit: 0.. 8 Exception number */ #if (__CORTEX_M != 0x07) - uint32_t _reserved0:15; /*!< bit: 9..23 Reserved */ + uint32_t _reserved0 : 15; /*!< bit: 9..23 Reserved */ #else - uint32_t _reserved0:7; /*!< bit: 9..15 Reserved */ - uint32_t GE:4; /*!< bit: 16..19 Greater than or Equal flags */ - uint32_t _reserved1:4; /*!< bit: 20..23 Reserved */ + uint32_t _reserved0 : 7; /*!< bit: 9..15 Reserved */ + uint32_t GE : 4; /*!< bit: 16..19 Greater than or Equal flags */ + uint32_t _reserved1 : 4; /*!< bit: 20..23 Reserved */ #endif - uint32_t T:1; /*!< bit: 24 Thumb bit (read 0) */ - uint32_t IT:2; /*!< bit: 25..26 saved IT state (read 0) */ - uint32_t Q:1; /*!< bit: 27 Saturation condition flag */ - uint32_t V:1; /*!< bit: 28 Overflow condition code flag */ - uint32_t C:1; /*!< bit: 29 Carry condition code flag */ - uint32_t Z:1; /*!< bit: 30 Zero condition code flag */ - uint32_t N:1; /*!< bit: 31 Negative condition code flag */ - } b; /*!< Structure used for bit access */ - uint32_t w; /*!< Type used for word access */ -} xPSR_Type; - - -/** \brief Union type to access the Control Registers (CONTROL). + uint32_t T : 1; /*!< bit: 24 Thumb bit (read 0) */ + uint32_t IT : 2; /*!< bit: 25..26 saved IT state (read 0) */ + uint32_t Q : 1; /*!< bit: 27 Saturation condition flag */ + uint32_t V : 1; /*!< bit: 28 Overflow condition code flag */ + uint32_t C : 1; /*!< bit: 29 Carry condition code flag */ + uint32_t Z : 1; /*!< bit: 30 Zero condition code flag */ + uint32_t N : 1; /*!< bit: 31 Negative condition code flag */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ + } xPSR_Type; + + /** \brief Union type to access the Control Registers (CONTROL). */ -typedef union -{ - struct - { - uint32_t nPRIV:1; /*!< bit: 0 Execution privilege in Thread mode */ - uint32_t SPSEL:1; /*!< bit: 1 Stack to be used */ - uint32_t FPCA:1; /*!< bit: 2 FP extension active flag */ - uint32_t _reserved0:29; /*!< bit: 3..31 Reserved */ - } b; /*!< Structure used for bit access */ - uint32_t w; /*!< Type used for word access */ -} CONTROL_Type; - -/*@} end of group CMSIS_CORE */ - - -/** \ingroup CMSIS_core_register + typedef union + { + struct + { + uint32_t nPRIV : 1; /*!< bit: 0 Execution privilege in Thread mode */ + uint32_t SPSEL : 1; /*!< bit: 1 Stack to be used */ + uint32_t FPCA : 1; /*!< bit: 2 FP extension active flag */ + uint32_t _reserved0 : 29; /*!< bit: 3..31 Reserved */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ + } CONTROL_Type; + + /*@} end of group CMSIS_CORE */ + + /** \ingroup CMSIS_core_register \defgroup CMSIS_NVIC Nested Vectored Interrupt Controller (NVIC) \brief Type definitions for the NVIC Registers @{ */ -/** \brief Structure type to access the Nested Vectored Interrupt Controller (NVIC). + /** \brief Structure type to access the Nested Vectored Interrupt Controller (NVIC). */ -typedef struct -{ - __IO uint32_t ISER[8]; /*!< Offset: 0x000 (R/W) Interrupt Set Enable Register */ - uint32_t RESERVED0[24]; - __IO uint32_t ICER[8]; /*!< Offset: 0x080 (R/W) Interrupt Clear Enable Register */ - uint32_t RSERVED1[24]; - __IO uint32_t ISPR[8]; /*!< Offset: 0x100 (R/W) Interrupt Set Pending Register */ - uint32_t RESERVED2[24]; - __IO uint32_t ICPR[8]; /*!< Offset: 0x180 (R/W) Interrupt Clear Pending Register */ - uint32_t RESERVED3[24]; - __IO uint32_t IABR[8]; /*!< Offset: 0x200 (R/W) Interrupt Active bit Register */ - uint32_t RESERVED4[56]; - __IO uint8_t IP[240]; /*!< Offset: 0x300 (R/W) Interrupt Priority Register (8Bit wide) */ - uint32_t RESERVED5[644]; - __O uint32_t STIR; /*!< Offset: 0xE00 ( /W) Software Trigger Interrupt Register */ -} NVIC_Type; + typedef struct + { + __IO uint32_t ISER[8]; /*!< Offset: 0x000 (R/W) Interrupt Set Enable Register */ + uint32_t RESERVED0[24]; + __IO uint32_t ICER[8]; /*!< Offset: 0x080 (R/W) Interrupt Clear Enable Register */ + uint32_t RSERVED1[24]; + __IO uint32_t ISPR[8]; /*!< Offset: 0x100 (R/W) Interrupt Set Pending Register */ + uint32_t RESERVED2[24]; + __IO uint32_t ICPR[8]; /*!< Offset: 0x180 (R/W) Interrupt Clear Pending Register */ + uint32_t RESERVED3[24]; + __IO uint32_t IABR[8]; /*!< Offset: 0x200 (R/W) Interrupt Active bit Register */ + uint32_t RESERVED4[56]; + __IO uint8_t IP[240]; /*!< Offset: 0x300 (R/W) Interrupt Priority Register (8Bit wide) */ + uint32_t RESERVED5[644]; + __O uint32_t STIR; /*!< Offset: 0xE00 ( /W) Software Trigger Interrupt Register */ + } NVIC_Type; /* Software Triggered Interrupt Register Definitions */ -#define NVIC_STIR_INTID_Pos 0 /*!< STIR: INTLINESNUM Position */ -#define NVIC_STIR_INTID_Msk (0x1FFUL << NVIC_STIR_INTID_Pos) /*!< STIR: INTLINESNUM Mask */ +#define NVIC_STIR_INTID_Pos 0 /*!< STIR: INTLINESNUM Position */ +#define NVIC_STIR_INTID_Msk (0x1FFUL << NVIC_STIR_INTID_Pos) /*!< STIR: INTLINESNUM Mask */ -/*@} end of group CMSIS_NVIC */ + /*@} end of group CMSIS_NVIC */ - -/** \ingroup CMSIS_core_register + /** \ingroup CMSIS_core_register \defgroup CMSIS_SCB System Control Block (SCB) \brief Type definitions for the System Control Block Registers @{ */ -/** \brief Structure type to access the System Control Block (SCB). + /** \brief Structure type to access the System Control Block (SCB). */ -typedef struct -{ - __I uint32_t CPUID; /*!< Offset: 0x000 (R/ ) CPUID Base Register */ - __IO uint32_t ICSR; /*!< Offset: 0x004 (R/W) Interrupt Control and State Register */ - __IO uint32_t VTOR; /*!< Offset: 0x008 (R/W) Vector Table Offset Register */ - __IO uint32_t AIRCR; /*!< Offset: 0x00C (R/W) Application Interrupt and Reset Control Register */ - __IO uint32_t SCR; /*!< Offset: 0x010 (R/W) System Control Register */ - __IO uint32_t CCR; /*!< Offset: 0x014 (R/W) Configuration Control Register */ - __IO uint8_t SHPR[12]; /*!< Offset: 0x018 (R/W) System Handlers Priority Registers (4-7, 8-11, 12-15) */ - __IO uint32_t SHCSR; /*!< Offset: 0x024 (R/W) System Handler Control and State Register */ - __IO uint32_t CFSR; /*!< Offset: 0x028 (R/W) Configurable Fault Status Register */ - __IO uint32_t HFSR; /*!< Offset: 0x02C (R/W) HardFault Status Register */ - __IO uint32_t DFSR; /*!< Offset: 0x030 (R/W) Debug Fault Status Register */ - __IO uint32_t MMFAR; /*!< Offset: 0x034 (R/W) MemManage Fault Address Register */ - __IO uint32_t BFAR; /*!< Offset: 0x038 (R/W) BusFault Address Register */ - __IO uint32_t AFSR; /*!< Offset: 0x03C (R/W) Auxiliary Fault Status Register */ - __I uint32_t ID_PFR[2]; /*!< Offset: 0x040 (R/ ) Processor Feature Register */ - __I uint32_t ID_DFR; /*!< Offset: 0x048 (R/ ) Debug Feature Register */ - __I uint32_t ID_AFR; /*!< Offset: 0x04C (R/ ) Auxiliary Feature Register */ - __I uint32_t ID_MFR[4]; /*!< Offset: 0x050 (R/ ) Memory Model Feature Register */ - __I uint32_t ID_ISAR[5]; /*!< Offset: 0x060 (R/ ) Instruction Set Attributes Register */ - uint32_t RESERVED0[1]; - __I uint32_t CLIDR; /*!< Offset: 0x078 (R/ ) Cache Level ID register */ - __I uint32_t CTR; /*!< Offset: 0x07C (R/ ) Cache Type register */ - __I uint32_t CCSIDR; /*!< Offset: 0x080 (R/ ) Cache Size ID Register */ - __IO uint32_t CSSELR; /*!< Offset: 0x084 (R/W) Cache Size Selection Register */ - __IO uint32_t CPACR; /*!< Offset: 0x088 (R/W) Coprocessor Access Control Register */ - uint32_t RESERVED3[93]; - __O uint32_t STIR; /*!< Offset: 0x200 ( /W) Software Triggered Interrupt Register */ - uint32_t RESERVED4[15]; - __I uint32_t MVFR0; /*!< Offset: 0x240 (R/ ) Media and VFP Feature Register 0 */ - __I uint32_t MVFR1; /*!< Offset: 0x244 (R/ ) Media and VFP Feature Register 1 */ - __I uint32_t MVFR2; /*!< Offset: 0x248 (R/ ) Media and VFP Feature Register 1 */ - uint32_t RESERVED5[1]; - __O uint32_t ICIALLU; /*!< Offset: 0x250 ( /W) I-Cache Invalidate All to PoU */ - uint32_t RESERVED6[1]; - __O uint32_t ICIMVAU; /*!< Offset: 0x258 ( /W) I-Cache Invalidate by MVA to PoU */ - __O uint32_t DCIMVAU; /*!< Offset: 0x25C ( /W) D-Cache Invalidate by MVA to PoC */ - __O uint32_t DCISW; /*!< Offset: 0x260 ( /W) D-Cache Invalidate by Set-way */ - __O uint32_t DCCMVAU; /*!< Offset: 0x264 ( /W) D-Cache Clean by MVA to PoU */ - __O uint32_t DCCMVAC; /*!< Offset: 0x268 ( /W) D-Cache Clean by MVA to PoC */ - __O uint32_t DCCSW; /*!< Offset: 0x26C ( /W) D-Cache Clean by Set-way */ - __O uint32_t DCCIMVAC; /*!< Offset: 0x270 ( /W) D-Cache Clean and Invalidate by MVA to PoC */ - __O uint32_t DCCISW; /*!< Offset: 0x274 ( /W) D-Cache Clean and Invalidate by Set-way */ - uint32_t RESERVED7[6]; - __IO uint32_t ITCMCR; /*!< Offset: 0x290 (R/W) Instruction Tightly-Coupled Memory Control Register */ - __IO uint32_t DTCMCR; /*!< Offset: 0x294 (R/W) Data Tightly-Coupled Memory Control Registers */ - __IO uint32_t AHBPCR; /*!< Offset: 0x298 (R/W) AHBP Control Register */ - __IO uint32_t CACR; /*!< Offset: 0x29C (R/W) L1 Cache Control Register */ - __IO uint32_t AHBSCR; /*!< Offset: 0x2A0 (R/W) AHB Slave Control Register */ - uint32_t RESERVED8[1]; - __IO uint32_t ABFSR; /*!< Offset: 0x2A8 (R/W) Auxiliary Bus Fault Status Register */ -} SCB_Type; + typedef struct + { + __I uint32_t CPUID; /*!< Offset: 0x000 (R/ ) CPUID Base Register */ + __IO uint32_t ICSR; /*!< Offset: 0x004 (R/W) Interrupt Control and State Register */ + __IO uint32_t VTOR; /*!< Offset: 0x008 (R/W) Vector Table Offset Register */ + __IO uint32_t AIRCR; /*!< Offset: 0x00C (R/W) Application Interrupt and Reset Control Register */ + __IO uint32_t SCR; /*!< Offset: 0x010 (R/W) System Control Register */ + __IO uint32_t CCR; /*!< Offset: 0x014 (R/W) Configuration Control Register */ + __IO uint8_t SHPR[12]; /*!< Offset: 0x018 (R/W) System Handlers Priority Registers (4-7, 8-11, 12-15) */ + __IO uint32_t SHCSR; /*!< Offset: 0x024 (R/W) System Handler Control and State Register */ + __IO uint32_t CFSR; /*!< Offset: 0x028 (R/W) Configurable Fault Status Register */ + __IO uint32_t HFSR; /*!< Offset: 0x02C (R/W) HardFault Status Register */ + __IO uint32_t DFSR; /*!< Offset: 0x030 (R/W) Debug Fault Status Register */ + __IO uint32_t MMFAR; /*!< Offset: 0x034 (R/W) MemManage Fault Address Register */ + __IO uint32_t BFAR; /*!< Offset: 0x038 (R/W) BusFault Address Register */ + __IO uint32_t AFSR; /*!< Offset: 0x03C (R/W) Auxiliary Fault Status Register */ + __I uint32_t ID_PFR[2]; /*!< Offset: 0x040 (R/ ) Processor Feature Register */ + __I uint32_t ID_DFR; /*!< Offset: 0x048 (R/ ) Debug Feature Register */ + __I uint32_t ID_AFR; /*!< Offset: 0x04C (R/ ) Auxiliary Feature Register */ + __I uint32_t ID_MFR[4]; /*!< Offset: 0x050 (R/ ) Memory Model Feature Register */ + __I uint32_t ID_ISAR[5]; /*!< Offset: 0x060 (R/ ) Instruction Set Attributes Register */ + uint32_t RESERVED0[1]; + __I uint32_t CLIDR; /*!< Offset: 0x078 (R/ ) Cache Level ID register */ + __I uint32_t CTR; /*!< Offset: 0x07C (R/ ) Cache Type register */ + __I uint32_t CCSIDR; /*!< Offset: 0x080 (R/ ) Cache Size ID Register */ + __IO uint32_t CSSELR; /*!< Offset: 0x084 (R/W) Cache Size Selection Register */ + __IO uint32_t CPACR; /*!< Offset: 0x088 (R/W) Coprocessor Access Control Register */ + uint32_t RESERVED3[93]; + __O uint32_t STIR; /*!< Offset: 0x200 ( /W) Software Triggered Interrupt Register */ + uint32_t RESERVED4[15]; + __I uint32_t MVFR0; /*!< Offset: 0x240 (R/ ) Media and VFP Feature Register 0 */ + __I uint32_t MVFR1; /*!< Offset: 0x244 (R/ ) Media and VFP Feature Register 1 */ + __I uint32_t MVFR2; /*!< Offset: 0x248 (R/ ) Media and VFP Feature Register 1 */ + uint32_t RESERVED5[1]; + __O uint32_t ICIALLU; /*!< Offset: 0x250 ( /W) I-Cache Invalidate All to PoU */ + uint32_t RESERVED6[1]; + __O uint32_t ICIMVAU; /*!< Offset: 0x258 ( /W) I-Cache Invalidate by MVA to PoU */ + __O uint32_t DCIMVAU; /*!< Offset: 0x25C ( /W) D-Cache Invalidate by MVA to PoC */ + __O uint32_t DCISW; /*!< Offset: 0x260 ( /W) D-Cache Invalidate by Set-way */ + __O uint32_t DCCMVAU; /*!< Offset: 0x264 ( /W) D-Cache Clean by MVA to PoU */ + __O uint32_t DCCMVAC; /*!< Offset: 0x268 ( /W) D-Cache Clean by MVA to PoC */ + __O uint32_t DCCSW; /*!< Offset: 0x26C ( /W) D-Cache Clean by Set-way */ + __O uint32_t DCCIMVAC; /*!< Offset: 0x270 ( /W) D-Cache Clean and Invalidate by MVA to PoC */ + __O uint32_t DCCISW; /*!< Offset: 0x274 ( /W) D-Cache Clean and Invalidate by Set-way */ + uint32_t RESERVED7[6]; + __IO uint32_t ITCMCR; /*!< Offset: 0x290 (R/W) Instruction Tightly-Coupled Memory Control Register */ + __IO uint32_t DTCMCR; /*!< Offset: 0x294 (R/W) Data Tightly-Coupled Memory Control Registers */ + __IO uint32_t AHBPCR; /*!< Offset: 0x298 (R/W) AHBP Control Register */ + __IO uint32_t CACR; /*!< Offset: 0x29C (R/W) L1 Cache Control Register */ + __IO uint32_t AHBSCR; /*!< Offset: 0x2A0 (R/W) AHB Slave Control Register */ + uint32_t RESERVED8[1]; + __IO uint32_t ABFSR; /*!< Offset: 0x2A8 (R/W) Auxiliary Bus Fault Status Register */ + } SCB_Type; /* SCB CPUID Register Definitions */ -#define SCB_CPUID_IMPLEMENTER_Pos 24 /*!< SCB CPUID: IMPLEMENTER Position */ -#define SCB_CPUID_IMPLEMENTER_Msk (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos) /*!< SCB CPUID: IMPLEMENTER Mask */ +#define SCB_CPUID_IMPLEMENTER_Pos 24 /*!< SCB CPUID: IMPLEMENTER Position */ +#define SCB_CPUID_IMPLEMENTER_Msk (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos) /*!< SCB CPUID: IMPLEMENTER Mask */ -#define SCB_CPUID_VARIANT_Pos 20 /*!< SCB CPUID: VARIANT Position */ -#define SCB_CPUID_VARIANT_Msk (0xFUL << SCB_CPUID_VARIANT_Pos) /*!< SCB CPUID: VARIANT Mask */ +#define SCB_CPUID_VARIANT_Pos 20 /*!< SCB CPUID: VARIANT Position */ +#define SCB_CPUID_VARIANT_Msk (0xFUL << SCB_CPUID_VARIANT_Pos) /*!< SCB CPUID: VARIANT Mask */ -#define SCB_CPUID_ARCHITECTURE_Pos 16 /*!< SCB CPUID: ARCHITECTURE Position */ -#define SCB_CPUID_ARCHITECTURE_Msk (0xFUL << SCB_CPUID_ARCHITECTURE_Pos) /*!< SCB CPUID: ARCHITECTURE Mask */ +#define SCB_CPUID_ARCHITECTURE_Pos 16 /*!< SCB CPUID: ARCHITECTURE Position */ +#define SCB_CPUID_ARCHITECTURE_Msk (0xFUL << SCB_CPUID_ARCHITECTURE_Pos) /*!< SCB CPUID: ARCHITECTURE Mask */ -#define SCB_CPUID_PARTNO_Pos 4 /*!< SCB CPUID: PARTNO Position */ -#define SCB_CPUID_PARTNO_Msk (0xFFFUL << SCB_CPUID_PARTNO_Pos) /*!< SCB CPUID: PARTNO Mask */ +#define SCB_CPUID_PARTNO_Pos 4 /*!< SCB CPUID: PARTNO Position */ +#define SCB_CPUID_PARTNO_Msk (0xFFFUL << SCB_CPUID_PARTNO_Pos) /*!< SCB CPUID: PARTNO Mask */ -#define SCB_CPUID_REVISION_Pos 0 /*!< SCB CPUID: REVISION Position */ -#define SCB_CPUID_REVISION_Msk (0xFUL << SCB_CPUID_REVISION_Pos) /*!< SCB CPUID: REVISION Mask */ +#define SCB_CPUID_REVISION_Pos 0 /*!< SCB CPUID: REVISION Position */ +#define SCB_CPUID_REVISION_Msk (0xFUL << SCB_CPUID_REVISION_Pos) /*!< SCB CPUID: REVISION Mask */ /* SCB Interrupt Control State Register Definitions */ -#define SCB_ICSR_NMIPENDSET_Pos 31 /*!< SCB ICSR: NMIPENDSET Position */ -#define SCB_ICSR_NMIPENDSET_Msk (1UL << SCB_ICSR_NMIPENDSET_Pos) /*!< SCB ICSR: NMIPENDSET Mask */ +#define SCB_ICSR_NMIPENDSET_Pos 31 /*!< SCB ICSR: NMIPENDSET Position */ +#define SCB_ICSR_NMIPENDSET_Msk (1UL << SCB_ICSR_NMIPENDSET_Pos) /*!< SCB ICSR: NMIPENDSET Mask */ -#define SCB_ICSR_PENDSVSET_Pos 28 /*!< SCB ICSR: PENDSVSET Position */ -#define SCB_ICSR_PENDSVSET_Msk (1UL << SCB_ICSR_PENDSVSET_Pos) /*!< SCB ICSR: PENDSVSET Mask */ +#define SCB_ICSR_PENDSVSET_Pos 28 /*!< SCB ICSR: PENDSVSET Position */ +#define SCB_ICSR_PENDSVSET_Msk (1UL << SCB_ICSR_PENDSVSET_Pos) /*!< SCB ICSR: PENDSVSET Mask */ -#define SCB_ICSR_PENDSVCLR_Pos 27 /*!< SCB ICSR: PENDSVCLR Position */ -#define SCB_ICSR_PENDSVCLR_Msk (1UL << SCB_ICSR_PENDSVCLR_Pos) /*!< SCB ICSR: PENDSVCLR Mask */ +#define SCB_ICSR_PENDSVCLR_Pos 27 /*!< SCB ICSR: PENDSVCLR Position */ +#define SCB_ICSR_PENDSVCLR_Msk (1UL << SCB_ICSR_PENDSVCLR_Pos) /*!< SCB ICSR: PENDSVCLR Mask */ -#define SCB_ICSR_PENDSTSET_Pos 26 /*!< SCB ICSR: PENDSTSET Position */ -#define SCB_ICSR_PENDSTSET_Msk (1UL << SCB_ICSR_PENDSTSET_Pos) /*!< SCB ICSR: PENDSTSET Mask */ +#define SCB_ICSR_PENDSTSET_Pos 26 /*!< SCB ICSR: PENDSTSET Position */ +#define SCB_ICSR_PENDSTSET_Msk (1UL << SCB_ICSR_PENDSTSET_Pos) /*!< SCB ICSR: PENDSTSET Mask */ -#define SCB_ICSR_PENDSTCLR_Pos 25 /*!< SCB ICSR: PENDSTCLR Position */ -#define SCB_ICSR_PENDSTCLR_Msk (1UL << SCB_ICSR_PENDSTCLR_Pos) /*!< SCB ICSR: PENDSTCLR Mask */ +#define SCB_ICSR_PENDSTCLR_Pos 25 /*!< SCB ICSR: PENDSTCLR Position */ +#define SCB_ICSR_PENDSTCLR_Msk (1UL << SCB_ICSR_PENDSTCLR_Pos) /*!< SCB ICSR: PENDSTCLR Mask */ -#define SCB_ICSR_ISRPREEMPT_Pos 23 /*!< SCB ICSR: ISRPREEMPT Position */ -#define SCB_ICSR_ISRPREEMPT_Msk (1UL << SCB_ICSR_ISRPREEMPT_Pos) /*!< SCB ICSR: ISRPREEMPT Mask */ +#define SCB_ICSR_ISRPREEMPT_Pos 23 /*!< SCB ICSR: ISRPREEMPT Position */ +#define SCB_ICSR_ISRPREEMPT_Msk (1UL << SCB_ICSR_ISRPREEMPT_Pos) /*!< SCB ICSR: ISRPREEMPT Mask */ -#define SCB_ICSR_ISRPENDING_Pos 22 /*!< SCB ICSR: ISRPENDING Position */ -#define SCB_ICSR_ISRPENDING_Msk (1UL << SCB_ICSR_ISRPENDING_Pos) /*!< SCB ICSR: ISRPENDING Mask */ +#define SCB_ICSR_ISRPENDING_Pos 22 /*!< SCB ICSR: ISRPENDING Position */ +#define SCB_ICSR_ISRPENDING_Msk (1UL << SCB_ICSR_ISRPENDING_Pos) /*!< SCB ICSR: ISRPENDING Mask */ -#define SCB_ICSR_VECTPENDING_Pos 12 /*!< SCB ICSR: VECTPENDING Position */ -#define SCB_ICSR_VECTPENDING_Msk (0x1FFUL << SCB_ICSR_VECTPENDING_Pos) /*!< SCB ICSR: VECTPENDING Mask */ +#define SCB_ICSR_VECTPENDING_Pos 12 /*!< SCB ICSR: VECTPENDING Position */ +#define SCB_ICSR_VECTPENDING_Msk (0x1FFUL << SCB_ICSR_VECTPENDING_Pos) /*!< SCB ICSR: VECTPENDING Mask */ -#define SCB_ICSR_RETTOBASE_Pos 11 /*!< SCB ICSR: RETTOBASE Position */ -#define SCB_ICSR_RETTOBASE_Msk (1UL << SCB_ICSR_RETTOBASE_Pos) /*!< SCB ICSR: RETTOBASE Mask */ +#define SCB_ICSR_RETTOBASE_Pos 11 /*!< SCB ICSR: RETTOBASE Position */ +#define SCB_ICSR_RETTOBASE_Msk (1UL << SCB_ICSR_RETTOBASE_Pos) /*!< SCB ICSR: RETTOBASE Mask */ -#define SCB_ICSR_VECTACTIVE_Pos 0 /*!< SCB ICSR: VECTACTIVE Position */ -#define SCB_ICSR_VECTACTIVE_Msk (0x1FFUL << SCB_ICSR_VECTACTIVE_Pos) /*!< SCB ICSR: VECTACTIVE Mask */ +#define SCB_ICSR_VECTACTIVE_Pos 0 /*!< SCB ICSR: VECTACTIVE Position */ +#define SCB_ICSR_VECTACTIVE_Msk (0x1FFUL << SCB_ICSR_VECTACTIVE_Pos) /*!< SCB ICSR: VECTACTIVE Mask */ /* SCB Vector Table Offset Register Definitions */ -#define SCB_VTOR_TBLOFF_Pos 7 /*!< SCB VTOR: TBLOFF Position */ -#define SCB_VTOR_TBLOFF_Msk (0x1FFFFFFUL << SCB_VTOR_TBLOFF_Pos) /*!< SCB VTOR: TBLOFF Mask */ +#define SCB_VTOR_TBLOFF_Pos 7 /*!< SCB VTOR: TBLOFF Position */ +#define SCB_VTOR_TBLOFF_Msk (0x1FFFFFFUL << SCB_VTOR_TBLOFF_Pos) /*!< SCB VTOR: TBLOFF Mask */ /* SCB Application Interrupt and Reset Control Register Definitions */ -#define SCB_AIRCR_VECTKEY_Pos 16 /*!< SCB AIRCR: VECTKEY Position */ -#define SCB_AIRCR_VECTKEY_Msk (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos) /*!< SCB AIRCR: VECTKEY Mask */ +#define SCB_AIRCR_VECTKEY_Pos 16 /*!< SCB AIRCR: VECTKEY Position */ +#define SCB_AIRCR_VECTKEY_Msk (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos) /*!< SCB AIRCR: VECTKEY Mask */ -#define SCB_AIRCR_VECTKEYSTAT_Pos 16 /*!< SCB AIRCR: VECTKEYSTAT Position */ -#define SCB_AIRCR_VECTKEYSTAT_Msk (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos) /*!< SCB AIRCR: VECTKEYSTAT Mask */ +#define SCB_AIRCR_VECTKEYSTAT_Pos 16 /*!< SCB AIRCR: VECTKEYSTAT Position */ +#define SCB_AIRCR_VECTKEYSTAT_Msk (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos) /*!< SCB AIRCR: VECTKEYSTAT Mask */ -#define SCB_AIRCR_ENDIANESS_Pos 15 /*!< SCB AIRCR: ENDIANESS Position */ -#define SCB_AIRCR_ENDIANESS_Msk (1UL << SCB_AIRCR_ENDIANESS_Pos) /*!< SCB AIRCR: ENDIANESS Mask */ +#define SCB_AIRCR_ENDIANESS_Pos 15 /*!< SCB AIRCR: ENDIANESS Position */ +#define SCB_AIRCR_ENDIANESS_Msk (1UL << SCB_AIRCR_ENDIANESS_Pos) /*!< SCB AIRCR: ENDIANESS Mask */ -#define SCB_AIRCR_PRIGROUP_Pos 8 /*!< SCB AIRCR: PRIGROUP Position */ -#define SCB_AIRCR_PRIGROUP_Msk (7UL << SCB_AIRCR_PRIGROUP_Pos) /*!< SCB AIRCR: PRIGROUP Mask */ +#define SCB_AIRCR_PRIGROUP_Pos 8 /*!< SCB AIRCR: PRIGROUP Position */ +#define SCB_AIRCR_PRIGROUP_Msk (7UL << SCB_AIRCR_PRIGROUP_Pos) /*!< SCB AIRCR: PRIGROUP Mask */ -#define SCB_AIRCR_SYSRESETREQ_Pos 2 /*!< SCB AIRCR: SYSRESETREQ Position */ -#define SCB_AIRCR_SYSRESETREQ_Msk (1UL << SCB_AIRCR_SYSRESETREQ_Pos) /*!< SCB AIRCR: SYSRESETREQ Mask */ +#define SCB_AIRCR_SYSRESETREQ_Pos 2 /*!< SCB AIRCR: SYSRESETREQ Position */ +#define SCB_AIRCR_SYSRESETREQ_Msk (1UL << SCB_AIRCR_SYSRESETREQ_Pos) /*!< SCB AIRCR: SYSRESETREQ Mask */ -#define SCB_AIRCR_VECTCLRACTIVE_Pos 1 /*!< SCB AIRCR: VECTCLRACTIVE Position */ -#define SCB_AIRCR_VECTCLRACTIVE_Msk (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos) /*!< SCB AIRCR: VECTCLRACTIVE Mask */ +#define SCB_AIRCR_VECTCLRACTIVE_Pos 1 /*!< SCB AIRCR: VECTCLRACTIVE Position */ +#define SCB_AIRCR_VECTCLRACTIVE_Msk (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos) /*!< SCB AIRCR: VECTCLRACTIVE Mask */ -#define SCB_AIRCR_VECTRESET_Pos 0 /*!< SCB AIRCR: VECTRESET Position */ -#define SCB_AIRCR_VECTRESET_Msk (1UL << SCB_AIRCR_VECTRESET_Pos) /*!< SCB AIRCR: VECTRESET Mask */ +#define SCB_AIRCR_VECTRESET_Pos 0 /*!< SCB AIRCR: VECTRESET Position */ +#define SCB_AIRCR_VECTRESET_Msk (1UL << SCB_AIRCR_VECTRESET_Pos) /*!< SCB AIRCR: VECTRESET Mask */ /* SCB System Control Register Definitions */ -#define SCB_SCR_SEVONPEND_Pos 4 /*!< SCB SCR: SEVONPEND Position */ -#define SCB_SCR_SEVONPEND_Msk (1UL << SCB_SCR_SEVONPEND_Pos) /*!< SCB SCR: SEVONPEND Mask */ +#define SCB_SCR_SEVONPEND_Pos 4 /*!< SCB SCR: SEVONPEND Position */ +#define SCB_SCR_SEVONPEND_Msk (1UL << SCB_SCR_SEVONPEND_Pos) /*!< SCB SCR: SEVONPEND Mask */ -#define SCB_SCR_SLEEPDEEP_Pos 2 /*!< SCB SCR: SLEEPDEEP Position */ -#define SCB_SCR_SLEEPDEEP_Msk (1UL << SCB_SCR_SLEEPDEEP_Pos) /*!< SCB SCR: SLEEPDEEP Mask */ +#define SCB_SCR_SLEEPDEEP_Pos 2 /*!< SCB SCR: SLEEPDEEP Position */ +#define SCB_SCR_SLEEPDEEP_Msk (1UL << SCB_SCR_SLEEPDEEP_Pos) /*!< SCB SCR: SLEEPDEEP Mask */ -#define SCB_SCR_SLEEPONEXIT_Pos 1 /*!< SCB SCR: SLEEPONEXIT Position */ -#define SCB_SCR_SLEEPONEXIT_Msk (1UL << SCB_SCR_SLEEPONEXIT_Pos) /*!< SCB SCR: SLEEPONEXIT Mask */ +#define SCB_SCR_SLEEPONEXIT_Pos 1 /*!< SCB SCR: SLEEPONEXIT Position */ +#define SCB_SCR_SLEEPONEXIT_Msk (1UL << SCB_SCR_SLEEPONEXIT_Pos) /*!< SCB SCR: SLEEPONEXIT Mask */ /* SCB Configuration Control Register Definitions */ -#define SCB_CCR_BP_Pos 18 /*!< SCB CCR: Branch prediction enable bit Position */ -#define SCB_CCR_BP_Msk (1UL << SCB_CCR_BP_Pos) /*!< SCB CCR: Branch prediction enable bit Mask */ +#define SCB_CCR_BP_Pos 18 /*!< SCB CCR: Branch prediction enable bit Position */ +#define SCB_CCR_BP_Msk (1UL << SCB_CCR_BP_Pos) /*!< SCB CCR: Branch prediction enable bit Mask */ -#define SCB_CCR_IC_Pos 17 /*!< SCB CCR: Instruction cache enable bit Position */ -#define SCB_CCR_IC_Msk (1UL << SCB_CCR_IC_Pos) /*!< SCB CCR: Instruction cache enable bit Mask */ +#define SCB_CCR_IC_Pos 17 /*!< SCB CCR: Instruction cache enable bit Position */ +#define SCB_CCR_IC_Msk (1UL << SCB_CCR_IC_Pos) /*!< SCB CCR: Instruction cache enable bit Mask */ -#define SCB_CCR_DC_Pos 16 /*!< SCB CCR: Cache enable bit Position */ -#define SCB_CCR_DC_Msk (1UL << SCB_CCR_DC_Pos) /*!< SCB CCR: Cache enable bit Mask */ +#define SCB_CCR_DC_Pos 16 /*!< SCB CCR: Cache enable bit Position */ +#define SCB_CCR_DC_Msk (1UL << SCB_CCR_DC_Pos) /*!< SCB CCR: Cache enable bit Mask */ -#define SCB_CCR_STKALIGN_Pos 9 /*!< SCB CCR: STKALIGN Position */ -#define SCB_CCR_STKALIGN_Msk (1UL << SCB_CCR_STKALIGN_Pos) /*!< SCB CCR: STKALIGN Mask */ +#define SCB_CCR_STKALIGN_Pos 9 /*!< SCB CCR: STKALIGN Position */ +#define SCB_CCR_STKALIGN_Msk (1UL << SCB_CCR_STKALIGN_Pos) /*!< SCB CCR: STKALIGN Mask */ -#define SCB_CCR_BFHFNMIGN_Pos 8 /*!< SCB CCR: BFHFNMIGN Position */ -#define SCB_CCR_BFHFNMIGN_Msk (1UL << SCB_CCR_BFHFNMIGN_Pos) /*!< SCB CCR: BFHFNMIGN Mask */ +#define SCB_CCR_BFHFNMIGN_Pos 8 /*!< SCB CCR: BFHFNMIGN Position */ +#define SCB_CCR_BFHFNMIGN_Msk (1UL << SCB_CCR_BFHFNMIGN_Pos) /*!< SCB CCR: BFHFNMIGN Mask */ -#define SCB_CCR_DIV_0_TRP_Pos 4 /*!< SCB CCR: DIV_0_TRP Position */ -#define SCB_CCR_DIV_0_TRP_Msk (1UL << SCB_CCR_DIV_0_TRP_Pos) /*!< SCB CCR: DIV_0_TRP Mask */ +#define SCB_CCR_DIV_0_TRP_Pos 4 /*!< SCB CCR: DIV_0_TRP Position */ +#define SCB_CCR_DIV_0_TRP_Msk (1UL << SCB_CCR_DIV_0_TRP_Pos) /*!< SCB CCR: DIV_0_TRP Mask */ -#define SCB_CCR_UNALIGN_TRP_Pos 3 /*!< SCB CCR: UNALIGN_TRP Position */ -#define SCB_CCR_UNALIGN_TRP_Msk (1UL << SCB_CCR_UNALIGN_TRP_Pos) /*!< SCB CCR: UNALIGN_TRP Mask */ +#define SCB_CCR_UNALIGN_TRP_Pos 3 /*!< SCB CCR: UNALIGN_TRP Position */ +#define SCB_CCR_UNALIGN_TRP_Msk (1UL << SCB_CCR_UNALIGN_TRP_Pos) /*!< SCB CCR: UNALIGN_TRP Mask */ -#define SCB_CCR_USERSETMPEND_Pos 1 /*!< SCB CCR: USERSETMPEND Position */ -#define SCB_CCR_USERSETMPEND_Msk (1UL << SCB_CCR_USERSETMPEND_Pos) /*!< SCB CCR: USERSETMPEND Mask */ +#define SCB_CCR_USERSETMPEND_Pos 1 /*!< SCB CCR: USERSETMPEND Position */ +#define SCB_CCR_USERSETMPEND_Msk (1UL << SCB_CCR_USERSETMPEND_Pos) /*!< SCB CCR: USERSETMPEND Mask */ -#define SCB_CCR_NONBASETHRDENA_Pos 0 /*!< SCB CCR: NONBASETHRDENA Position */ -#define SCB_CCR_NONBASETHRDENA_Msk (1UL << SCB_CCR_NONBASETHRDENA_Pos) /*!< SCB CCR: NONBASETHRDENA Mask */ +#define SCB_CCR_NONBASETHRDENA_Pos 0 /*!< SCB CCR: NONBASETHRDENA Position */ +#define SCB_CCR_NONBASETHRDENA_Msk (1UL << SCB_CCR_NONBASETHRDENA_Pos) /*!< SCB CCR: NONBASETHRDENA Mask */ /* SCB System Handler Control and State Register Definitions */ -#define SCB_SHCSR_USGFAULTENA_Pos 18 /*!< SCB SHCSR: USGFAULTENA Position */ -#define SCB_SHCSR_USGFAULTENA_Msk (1UL << SCB_SHCSR_USGFAULTENA_Pos) /*!< SCB SHCSR: USGFAULTENA Mask */ +#define SCB_SHCSR_USGFAULTENA_Pos 18 /*!< SCB SHCSR: USGFAULTENA Position */ +#define SCB_SHCSR_USGFAULTENA_Msk (1UL << SCB_SHCSR_USGFAULTENA_Pos) /*!< SCB SHCSR: USGFAULTENA Mask */ -#define SCB_SHCSR_BUSFAULTENA_Pos 17 /*!< SCB SHCSR: BUSFAULTENA Position */ -#define SCB_SHCSR_BUSFAULTENA_Msk (1UL << SCB_SHCSR_BUSFAULTENA_Pos) /*!< SCB SHCSR: BUSFAULTENA Mask */ +#define SCB_SHCSR_BUSFAULTENA_Pos 17 /*!< SCB SHCSR: BUSFAULTENA Position */ +#define SCB_SHCSR_BUSFAULTENA_Msk (1UL << SCB_SHCSR_BUSFAULTENA_Pos) /*!< SCB SHCSR: BUSFAULTENA Mask */ -#define SCB_SHCSR_MEMFAULTENA_Pos 16 /*!< SCB SHCSR: MEMFAULTENA Position */ -#define SCB_SHCSR_MEMFAULTENA_Msk (1UL << SCB_SHCSR_MEMFAULTENA_Pos) /*!< SCB SHCSR: MEMFAULTENA Mask */ +#define SCB_SHCSR_MEMFAULTENA_Pos 16 /*!< SCB SHCSR: MEMFAULTENA Position */ +#define SCB_SHCSR_MEMFAULTENA_Msk (1UL << SCB_SHCSR_MEMFAULTENA_Pos) /*!< SCB SHCSR: MEMFAULTENA Mask */ -#define SCB_SHCSR_SVCALLPENDED_Pos 15 /*!< SCB SHCSR: SVCALLPENDED Position */ -#define SCB_SHCSR_SVCALLPENDED_Msk (1UL << SCB_SHCSR_SVCALLPENDED_Pos) /*!< SCB SHCSR: SVCALLPENDED Mask */ +#define SCB_SHCSR_SVCALLPENDED_Pos 15 /*!< SCB SHCSR: SVCALLPENDED Position */ +#define SCB_SHCSR_SVCALLPENDED_Msk (1UL << SCB_SHCSR_SVCALLPENDED_Pos) /*!< SCB SHCSR: SVCALLPENDED Mask */ -#define SCB_SHCSR_BUSFAULTPENDED_Pos 14 /*!< SCB SHCSR: BUSFAULTPENDED Position */ -#define SCB_SHCSR_BUSFAULTPENDED_Msk (1UL << SCB_SHCSR_BUSFAULTPENDED_Pos) /*!< SCB SHCSR: BUSFAULTPENDED Mask */ +#define SCB_SHCSR_BUSFAULTPENDED_Pos 14 /*!< SCB SHCSR: BUSFAULTPENDED Position */ +#define SCB_SHCSR_BUSFAULTPENDED_Msk (1UL << SCB_SHCSR_BUSFAULTPENDED_Pos) /*!< SCB SHCSR: BUSFAULTPENDED Mask */ -#define SCB_SHCSR_MEMFAULTPENDED_Pos 13 /*!< SCB SHCSR: MEMFAULTPENDED Position */ -#define SCB_SHCSR_MEMFAULTPENDED_Msk (1UL << SCB_SHCSR_MEMFAULTPENDED_Pos) /*!< SCB SHCSR: MEMFAULTPENDED Mask */ +#define SCB_SHCSR_MEMFAULTPENDED_Pos 13 /*!< SCB SHCSR: MEMFAULTPENDED Position */ +#define SCB_SHCSR_MEMFAULTPENDED_Msk (1UL << SCB_SHCSR_MEMFAULTPENDED_Pos) /*!< SCB SHCSR: MEMFAULTPENDED Mask */ -#define SCB_SHCSR_USGFAULTPENDED_Pos 12 /*!< SCB SHCSR: USGFAULTPENDED Position */ -#define SCB_SHCSR_USGFAULTPENDED_Msk (1UL << SCB_SHCSR_USGFAULTPENDED_Pos) /*!< SCB SHCSR: USGFAULTPENDED Mask */ +#define SCB_SHCSR_USGFAULTPENDED_Pos 12 /*!< SCB SHCSR: USGFAULTPENDED Position */ +#define SCB_SHCSR_USGFAULTPENDED_Msk (1UL << SCB_SHCSR_USGFAULTPENDED_Pos) /*!< SCB SHCSR: USGFAULTPENDED Mask */ -#define SCB_SHCSR_SYSTICKACT_Pos 11 /*!< SCB SHCSR: SYSTICKACT Position */ -#define SCB_SHCSR_SYSTICKACT_Msk (1UL << SCB_SHCSR_SYSTICKACT_Pos) /*!< SCB SHCSR: SYSTICKACT Mask */ +#define SCB_SHCSR_SYSTICKACT_Pos 11 /*!< SCB SHCSR: SYSTICKACT Position */ +#define SCB_SHCSR_SYSTICKACT_Msk (1UL << SCB_SHCSR_SYSTICKACT_Pos) /*!< SCB SHCSR: SYSTICKACT Mask */ -#define SCB_SHCSR_PENDSVACT_Pos 10 /*!< SCB SHCSR: PENDSVACT Position */ -#define SCB_SHCSR_PENDSVACT_Msk (1UL << SCB_SHCSR_PENDSVACT_Pos) /*!< SCB SHCSR: PENDSVACT Mask */ +#define SCB_SHCSR_PENDSVACT_Pos 10 /*!< SCB SHCSR: PENDSVACT Position */ +#define SCB_SHCSR_PENDSVACT_Msk (1UL << SCB_SHCSR_PENDSVACT_Pos) /*!< SCB SHCSR: PENDSVACT Mask */ -#define SCB_SHCSR_MONITORACT_Pos 8 /*!< SCB SHCSR: MONITORACT Position */ -#define SCB_SHCSR_MONITORACT_Msk (1UL << SCB_SHCSR_MONITORACT_Pos) /*!< SCB SHCSR: MONITORACT Mask */ +#define SCB_SHCSR_MONITORACT_Pos 8 /*!< SCB SHCSR: MONITORACT Position */ +#define SCB_SHCSR_MONITORACT_Msk (1UL << SCB_SHCSR_MONITORACT_Pos) /*!< SCB SHCSR: MONITORACT Mask */ -#define SCB_SHCSR_SVCALLACT_Pos 7 /*!< SCB SHCSR: SVCALLACT Position */ -#define SCB_SHCSR_SVCALLACT_Msk (1UL << SCB_SHCSR_SVCALLACT_Pos) /*!< SCB SHCSR: SVCALLACT Mask */ +#define SCB_SHCSR_SVCALLACT_Pos 7 /*!< SCB SHCSR: SVCALLACT Position */ +#define SCB_SHCSR_SVCALLACT_Msk (1UL << SCB_SHCSR_SVCALLACT_Pos) /*!< SCB SHCSR: SVCALLACT Mask */ -#define SCB_SHCSR_USGFAULTACT_Pos 3 /*!< SCB SHCSR: USGFAULTACT Position */ -#define SCB_SHCSR_USGFAULTACT_Msk (1UL << SCB_SHCSR_USGFAULTACT_Pos) /*!< SCB SHCSR: USGFAULTACT Mask */ +#define SCB_SHCSR_USGFAULTACT_Pos 3 /*!< SCB SHCSR: USGFAULTACT Position */ +#define SCB_SHCSR_USGFAULTACT_Msk (1UL << SCB_SHCSR_USGFAULTACT_Pos) /*!< SCB SHCSR: USGFAULTACT Mask */ -#define SCB_SHCSR_BUSFAULTACT_Pos 1 /*!< SCB SHCSR: BUSFAULTACT Position */ -#define SCB_SHCSR_BUSFAULTACT_Msk (1UL << SCB_SHCSR_BUSFAULTACT_Pos) /*!< SCB SHCSR: BUSFAULTACT Mask */ +#define SCB_SHCSR_BUSFAULTACT_Pos 1 /*!< SCB SHCSR: BUSFAULTACT Position */ +#define SCB_SHCSR_BUSFAULTACT_Msk (1UL << SCB_SHCSR_BUSFAULTACT_Pos) /*!< SCB SHCSR: BUSFAULTACT Mask */ -#define SCB_SHCSR_MEMFAULTACT_Pos 0 /*!< SCB SHCSR: MEMFAULTACT Position */ -#define SCB_SHCSR_MEMFAULTACT_Msk (1UL << SCB_SHCSR_MEMFAULTACT_Pos) /*!< SCB SHCSR: MEMFAULTACT Mask */ +#define SCB_SHCSR_MEMFAULTACT_Pos 0 /*!< SCB SHCSR: MEMFAULTACT Position */ +#define SCB_SHCSR_MEMFAULTACT_Msk (1UL << SCB_SHCSR_MEMFAULTACT_Pos) /*!< SCB SHCSR: MEMFAULTACT Mask */ /* SCB Configurable Fault Status Registers Definitions */ -#define SCB_CFSR_USGFAULTSR_Pos 16 /*!< SCB CFSR: Usage Fault Status Register Position */ -#define SCB_CFSR_USGFAULTSR_Msk (0xFFFFUL << SCB_CFSR_USGFAULTSR_Pos) /*!< SCB CFSR: Usage Fault Status Register Mask */ +#define SCB_CFSR_USGFAULTSR_Pos 16 /*!< SCB CFSR: Usage Fault Status Register Position */ +#define SCB_CFSR_USGFAULTSR_Msk (0xFFFFUL << SCB_CFSR_USGFAULTSR_Pos) /*!< SCB CFSR: Usage Fault Status Register Mask */ -#define SCB_CFSR_BUSFAULTSR_Pos 8 /*!< SCB CFSR: Bus Fault Status Register Position */ -#define SCB_CFSR_BUSFAULTSR_Msk (0xFFUL << SCB_CFSR_BUSFAULTSR_Pos) /*!< SCB CFSR: Bus Fault Status Register Mask */ +#define SCB_CFSR_BUSFAULTSR_Pos 8 /*!< SCB CFSR: Bus Fault Status Register Position */ +#define SCB_CFSR_BUSFAULTSR_Msk (0xFFUL << SCB_CFSR_BUSFAULTSR_Pos) /*!< SCB CFSR: Bus Fault Status Register Mask */ -#define SCB_CFSR_MEMFAULTSR_Pos 0 /*!< SCB CFSR: Memory Manage Fault Status Register Position */ -#define SCB_CFSR_MEMFAULTSR_Msk (0xFFUL << SCB_CFSR_MEMFAULTSR_Pos) /*!< SCB CFSR: Memory Manage Fault Status Register Mask */ +#define SCB_CFSR_MEMFAULTSR_Pos 0 /*!< SCB CFSR: Memory Manage Fault Status Register Position */ +#define SCB_CFSR_MEMFAULTSR_Msk (0xFFUL << SCB_CFSR_MEMFAULTSR_Pos) /*!< SCB CFSR: Memory Manage Fault Status Register Mask */ /* SCB Hard Fault Status Registers Definitions */ -#define SCB_HFSR_DEBUGEVT_Pos 31 /*!< SCB HFSR: DEBUGEVT Position */ -#define SCB_HFSR_DEBUGEVT_Msk (1UL << SCB_HFSR_DEBUGEVT_Pos) /*!< SCB HFSR: DEBUGEVT Mask */ +#define SCB_HFSR_DEBUGEVT_Pos 31 /*!< SCB HFSR: DEBUGEVT Position */ +#define SCB_HFSR_DEBUGEVT_Msk (1UL << SCB_HFSR_DEBUGEVT_Pos) /*!< SCB HFSR: DEBUGEVT Mask */ -#define SCB_HFSR_FORCED_Pos 30 /*!< SCB HFSR: FORCED Position */ -#define SCB_HFSR_FORCED_Msk (1UL << SCB_HFSR_FORCED_Pos) /*!< SCB HFSR: FORCED Mask */ +#define SCB_HFSR_FORCED_Pos 30 /*!< SCB HFSR: FORCED Position */ +#define SCB_HFSR_FORCED_Msk (1UL << SCB_HFSR_FORCED_Pos) /*!< SCB HFSR: FORCED Mask */ -#define SCB_HFSR_VECTTBL_Pos 1 /*!< SCB HFSR: VECTTBL Position */ -#define SCB_HFSR_VECTTBL_Msk (1UL << SCB_HFSR_VECTTBL_Pos) /*!< SCB HFSR: VECTTBL Mask */ +#define SCB_HFSR_VECTTBL_Pos 1 /*!< SCB HFSR: VECTTBL Position */ +#define SCB_HFSR_VECTTBL_Msk (1UL << SCB_HFSR_VECTTBL_Pos) /*!< SCB HFSR: VECTTBL Mask */ /* SCB Debug Fault Status Register Definitions */ -#define SCB_DFSR_EXTERNAL_Pos 4 /*!< SCB DFSR: EXTERNAL Position */ -#define SCB_DFSR_EXTERNAL_Msk (1UL << SCB_DFSR_EXTERNAL_Pos) /*!< SCB DFSR: EXTERNAL Mask */ +#define SCB_DFSR_EXTERNAL_Pos 4 /*!< SCB DFSR: EXTERNAL Position */ +#define SCB_DFSR_EXTERNAL_Msk (1UL << SCB_DFSR_EXTERNAL_Pos) /*!< SCB DFSR: EXTERNAL Mask */ -#define SCB_DFSR_VCATCH_Pos 3 /*!< SCB DFSR: VCATCH Position */ -#define SCB_DFSR_VCATCH_Msk (1UL << SCB_DFSR_VCATCH_Pos) /*!< SCB DFSR: VCATCH Mask */ +#define SCB_DFSR_VCATCH_Pos 3 /*!< SCB DFSR: VCATCH Position */ +#define SCB_DFSR_VCATCH_Msk (1UL << SCB_DFSR_VCATCH_Pos) /*!< SCB DFSR: VCATCH Mask */ -#define SCB_DFSR_DWTTRAP_Pos 2 /*!< SCB DFSR: DWTTRAP Position */ -#define SCB_DFSR_DWTTRAP_Msk (1UL << SCB_DFSR_DWTTRAP_Pos) /*!< SCB DFSR: DWTTRAP Mask */ +#define SCB_DFSR_DWTTRAP_Pos 2 /*!< SCB DFSR: DWTTRAP Position */ +#define SCB_DFSR_DWTTRAP_Msk (1UL << SCB_DFSR_DWTTRAP_Pos) /*!< SCB DFSR: DWTTRAP Mask */ -#define SCB_DFSR_BKPT_Pos 1 /*!< SCB DFSR: BKPT Position */ -#define SCB_DFSR_BKPT_Msk (1UL << SCB_DFSR_BKPT_Pos) /*!< SCB DFSR: BKPT Mask */ +#define SCB_DFSR_BKPT_Pos 1 /*!< SCB DFSR: BKPT Position */ +#define SCB_DFSR_BKPT_Msk (1UL << SCB_DFSR_BKPT_Pos) /*!< SCB DFSR: BKPT Mask */ -#define SCB_DFSR_HALTED_Pos 0 /*!< SCB DFSR: HALTED Position */ -#define SCB_DFSR_HALTED_Msk (1UL << SCB_DFSR_HALTED_Pos) /*!< SCB DFSR: HALTED Mask */ +#define SCB_DFSR_HALTED_Pos 0 /*!< SCB DFSR: HALTED Position */ +#define SCB_DFSR_HALTED_Msk (1UL << SCB_DFSR_HALTED_Pos) /*!< SCB DFSR: HALTED Mask */ /* Cache Level ID register */ -#define SCB_CLIDR_LOUU_Pos 27 /*!< SCB CLIDR: LoUU Position */ -#define SCB_CLIDR_LOUU_Msk (7UL << SCB_CLIDR_LOUU_Pos) /*!< SCB CLIDR: LoUU Mask */ +#define SCB_CLIDR_LOUU_Pos 27 /*!< SCB CLIDR: LoUU Position */ +#define SCB_CLIDR_LOUU_Msk (7UL << SCB_CLIDR_LOUU_Pos) /*!< SCB CLIDR: LoUU Mask */ -#define SCB_CLIDR_LOC_Pos 24 /*!< SCB CLIDR: LoC Position */ -#define SCB_CLIDR_LOC_Msk (7UL << SCB_CLIDR_FORMAT_Pos) /*!< SCB CLIDR: LoC Mask */ +#define SCB_CLIDR_LOC_Pos 24 /*!< SCB CLIDR: LoC Position */ +#define SCB_CLIDR_LOC_Msk (7UL << SCB_CLIDR_FORMAT_Pos) /*!< SCB CLIDR: LoC Mask */ /* Cache Type register */ -#define SCB_CTR_FORMAT_Pos 29 /*!< SCB CTR: Format Position */ -#define SCB_CTR_FORMAT_Msk (7UL << SCB_CTR_FORMAT_Pos) /*!< SCB CTR: Format Mask */ +#define SCB_CTR_FORMAT_Pos 29 /*!< SCB CTR: Format Position */ +#define SCB_CTR_FORMAT_Msk (7UL << SCB_CTR_FORMAT_Pos) /*!< SCB CTR: Format Mask */ -#define SCB_CTR_CWG_Pos 24 /*!< SCB CTR: CWG Position */ -#define SCB_CTR_CWG_Msk (0xFUL << SCB_CTR_CWG_Pos) /*!< SCB CTR: CWG Mask */ +#define SCB_CTR_CWG_Pos 24 /*!< SCB CTR: CWG Position */ +#define SCB_CTR_CWG_Msk (0xFUL << SCB_CTR_CWG_Pos) /*!< SCB CTR: CWG Mask */ -#define SCB_CTR_ERG_Pos 20 /*!< SCB CTR: ERG Position */ -#define SCB_CTR_ERG_Msk (0xFUL << SCB_CTR_ERG_Pos) /*!< SCB CTR: ERG Mask */ +#define SCB_CTR_ERG_Pos 20 /*!< SCB CTR: ERG Position */ +#define SCB_CTR_ERG_Msk (0xFUL << SCB_CTR_ERG_Pos) /*!< SCB CTR: ERG Mask */ -#define SCB_CTR_DMINLINE_Pos 16 /*!< SCB CTR: DminLine Position */ -#define SCB_CTR_DMINLINE_Msk (0xFUL << SCB_CTR_DMINLINE_Pos) /*!< SCB CTR: DminLine Mask */ +#define SCB_CTR_DMINLINE_Pos 16 /*!< SCB CTR: DminLine Position */ +#define SCB_CTR_DMINLINE_Msk (0xFUL << SCB_CTR_DMINLINE_Pos) /*!< SCB CTR: DminLine Mask */ -#define SCB_CTR_IMINLINE_Pos 0 /*!< SCB CTR: ImInLine Position */ -#define SCB_CTR_IMINLINE_Msk (0xFUL << SCB_CTR_IMINLINE_Pos) /*!< SCB CTR: ImInLine Mask */ +#define SCB_CTR_IMINLINE_Pos 0 /*!< SCB CTR: ImInLine Position */ +#define SCB_CTR_IMINLINE_Msk (0xFUL << SCB_CTR_IMINLINE_Pos) /*!< SCB CTR: ImInLine Mask */ /* Cache Size ID Register */ -#define SCB_CCSIDR_WT_Pos 31 /*!< SCB CCSIDR: WT Position */ -#define SCB_CCSIDR_WT_Msk (7UL << SCB_CCSIDR_WT_Pos) /*!< SCB CCSIDR: WT Mask */ +#define SCB_CCSIDR_WT_Pos 31 /*!< SCB CCSIDR: WT Position */ +#define SCB_CCSIDR_WT_Msk (7UL << SCB_CCSIDR_WT_Pos) /*!< SCB CCSIDR: WT Mask */ -#define SCB_CCSIDR_WB_Pos 30 /*!< SCB CCSIDR: WB Position */ -#define SCB_CCSIDR_WB_Msk (7UL << SCB_CCSIDR_WB_Pos) /*!< SCB CCSIDR: WB Mask */ +#define SCB_CCSIDR_WB_Pos 30 /*!< SCB CCSIDR: WB Position */ +#define SCB_CCSIDR_WB_Msk (7UL << SCB_CCSIDR_WB_Pos) /*!< SCB CCSIDR: WB Mask */ -#define SCB_CCSIDR_RA_Pos 29 /*!< SCB CCSIDR: RA Position */ -#define SCB_CCSIDR_RA_Msk (7UL << SCB_CCSIDR_RA_Pos) /*!< SCB CCSIDR: RA Mask */ +#define SCB_CCSIDR_RA_Pos 29 /*!< SCB CCSIDR: RA Position */ +#define SCB_CCSIDR_RA_Msk (7UL << SCB_CCSIDR_RA_Pos) /*!< SCB CCSIDR: RA Mask */ -#define SCB_CCSIDR_WA_Pos 28 /*!< SCB CCSIDR: WA Position */ -#define SCB_CCSIDR_WA_Msk (7UL << SCB_CCSIDR_WA_Pos) /*!< SCB CCSIDR: WA Mask */ +#define SCB_CCSIDR_WA_Pos 28 /*!< SCB CCSIDR: WA Position */ +#define SCB_CCSIDR_WA_Msk (7UL << SCB_CCSIDR_WA_Pos) /*!< SCB CCSIDR: WA Mask */ -#define SCB_CCSIDR_NUMSETS_Pos 13 /*!< SCB CCSIDR: NumSets Position */ -#define SCB_CCSIDR_NUMSETS_Msk (0x7FFFUL << SCB_CCSIDR_NUMSETS_Pos) /*!< SCB CCSIDR: NumSets Mask */ +#define SCB_CCSIDR_NUMSETS_Pos 13 /*!< SCB CCSIDR: NumSets Position */ +#define SCB_CCSIDR_NUMSETS_Msk (0x7FFFUL << SCB_CCSIDR_NUMSETS_Pos) /*!< SCB CCSIDR: NumSets Mask */ -#define SCB_CCSIDR_ASSOCIATIVITY_Pos 3 /*!< SCB CCSIDR: Associativity Position */ -#define SCB_CCSIDR_ASSOCIATIVITY_Msk (0x3FFUL << SCB_CCSIDR_ASSOCIATIVITY_Pos) /*!< SCB CCSIDR: Associativity Mask */ +#define SCB_CCSIDR_ASSOCIATIVITY_Pos 3 /*!< SCB CCSIDR: Associativity Position */ +#define SCB_CCSIDR_ASSOCIATIVITY_Msk (0x3FFUL << SCB_CCSIDR_ASSOCIATIVITY_Pos) /*!< SCB CCSIDR: Associativity Mask */ -#define SCB_CCSIDR_LINESIZE_Pos 0 /*!< SCB CCSIDR: LineSize Position */ -#define SCB_CCSIDR_LINESIZE_Msk (7UL << SCB_CCSIDR_LINESIZE_Pos) /*!< SCB CCSIDR: LineSize Mask */ +#define SCB_CCSIDR_LINESIZE_Pos 0 /*!< SCB CCSIDR: LineSize Position */ +#define SCB_CCSIDR_LINESIZE_Msk (7UL << SCB_CCSIDR_LINESIZE_Pos) /*!< SCB CCSIDR: LineSize Mask */ /* Cache Size Selection Register */ -#define SCB_CSSELR_LEVEL_Pos 0 /*!< SCB CSSELR: Level Position */ -#define SCB_CSSELR_LEVEL_Msk (1UL << SCB_CSSELR_LEVEL_Pos) /*!< SCB CSSELR: Level Mask */ +#define SCB_CSSELR_LEVEL_Pos 0 /*!< SCB CSSELR: Level Position */ +#define SCB_CSSELR_LEVEL_Msk (1UL << SCB_CSSELR_LEVEL_Pos) /*!< SCB CSSELR: Level Mask */ -#define SCB_CSSELR_IND_Pos 0 /*!< SCB CSSELR: InD Position */ -#define SCB_CSSELR_IND_Msk (1UL << SCB_CSSELR_IND_Pos) /*!< SCB CSSELR: InD Mask */ +#define SCB_CSSELR_IND_Pos 0 /*!< SCB CSSELR: InD Position */ +#define SCB_CSSELR_IND_Msk (1UL << SCB_CSSELR_IND_Pos) /*!< SCB CSSELR: InD Mask */ /* SCB Software Triggered Interrupt Register */ -#define SCB_STIR_INTID_Pos 0 /*!< SCB STIR: INTID Position */ -#define SCB_STIR_INTID_Msk (0x1FFUL << SCB_STIR_INTID_Pos) /*!< SCB STIR: INTID Mask */ +#define SCB_STIR_INTID_Pos 0 /*!< SCB STIR: INTID Position */ +#define SCB_STIR_INTID_Msk (0x1FFUL << SCB_STIR_INTID_Pos) /*!< SCB STIR: INTID Mask */ /* Instruction Tightly-Coupled Memory Control Register*/ -#define SCB_ITCMCR_SZ_Pos 3 /*!< SCB ITCMCR: SZ Position */ -#define SCB_ITCMCR_SZ_Msk (0xFUL << SCB_ITCMCR_SZ_Pos) /*!< SCB ITCMCR: SZ Mask */ +#define SCB_ITCMCR_SZ_Pos 3 /*!< SCB ITCMCR: SZ Position */ +#define SCB_ITCMCR_SZ_Msk (0xFUL << SCB_ITCMCR_SZ_Pos) /*!< SCB ITCMCR: SZ Mask */ -#define SCB_ITCMCR_RETEN_Pos 2 /*!< SCB ITCMCR: RETEN Position */ -#define SCB_ITCMCR_RETEN_Msk (1FFUL << SCB_ITCMCR_RETEN_Pos) /*!< SCB ITCMCR: RETEN Mask */ +#define SCB_ITCMCR_RETEN_Pos 2 /*!< SCB ITCMCR: RETEN Position */ +#define SCB_ITCMCR_RETEN_Msk (1FFUL << SCB_ITCMCR_RETEN_Pos) /*!< SCB ITCMCR: RETEN Mask */ -#define SCB_ITCMCR_RMW_Pos 1 /*!< SCB ITCMCR: RMW Position */ -#define SCB_ITCMCR_RMW_Msk (1FFUL << SCB_ITCMCR_RMW_Pos) /*!< SCB ITCMCR: RMW Mask */ +#define SCB_ITCMCR_RMW_Pos 1 /*!< SCB ITCMCR: RMW Position */ +#define SCB_ITCMCR_RMW_Msk (1FFUL << SCB_ITCMCR_RMW_Pos) /*!< SCB ITCMCR: RMW Mask */ -#define SCB_ITCMCR_EN_Pos 0 /*!< SCB ITCMCR: EN Position */ -#define SCB_ITCMCR_EN_Msk (1FFUL << SCB_ITCMCR_EN_Pos) /*!< SCB ITCMCR: EN Mask */ +#define SCB_ITCMCR_EN_Pos 0 /*!< SCB ITCMCR: EN Position */ +#define SCB_ITCMCR_EN_Msk (1FFUL << SCB_ITCMCR_EN_Pos) /*!< SCB ITCMCR: EN Mask */ /* Data Tightly-Coupled Memory Control Registers */ -#define SCB_DTCMCR_SZ_Pos 3 /*!< SCB DTCMCR: SZ Position */ -#define SCB_DTCMCR_SZ_Msk (0xFUL << SCB_DTCMCR_SZ_Pos) /*!< SCB DTCMCR: SZ Mask */ +#define SCB_DTCMCR_SZ_Pos 3 /*!< SCB DTCMCR: SZ Position */ +#define SCB_DTCMCR_SZ_Msk (0xFUL << SCB_DTCMCR_SZ_Pos) /*!< SCB DTCMCR: SZ Mask */ -#define SCB_DTCMCR_RETEN_Pos 2 /*!< SCB DTCMCR: RETEN Position */ -#define SCB_DTCMCR_RETEN_Msk (1UL << SCB_DTCMCR_RETEN_Pos) /*!< SCB DTCMCR: RETEN Mask */ +#define SCB_DTCMCR_RETEN_Pos 2 /*!< SCB DTCMCR: RETEN Position */ +#define SCB_DTCMCR_RETEN_Msk (1UL << SCB_DTCMCR_RETEN_Pos) /*!< SCB DTCMCR: RETEN Mask */ -#define SCB_DTCMCR_RMW_Pos 1 /*!< SCB DTCMCR: RMW Position */ -#define SCB_DTCMCR_RMW_Msk (1UL << SCB_DTCMCR_RMW_Pos) /*!< SCB DTCMCR: RMW Mask */ +#define SCB_DTCMCR_RMW_Pos 1 /*!< SCB DTCMCR: RMW Position */ +#define SCB_DTCMCR_RMW_Msk (1UL << SCB_DTCMCR_RMW_Pos) /*!< SCB DTCMCR: RMW Mask */ -#define SCB_DTCMCR_EN_Pos 0 /*!< SCB DTCMCR: EN Position */ -#define SCB_DTCMCR_EN_Msk (1UL << SCB_DTCMCR_EN_Pos) /*!< SCB DTCMCR: EN Mask */ +#define SCB_DTCMCR_EN_Pos 0 /*!< SCB DTCMCR: EN Position */ +#define SCB_DTCMCR_EN_Msk (1UL << SCB_DTCMCR_EN_Pos) /*!< SCB DTCMCR: EN Mask */ /* AHBP Control Register */ -#define SCB_AHBPCR_SZ_Pos 1 /*!< SCB AHBPCR: SZ Position */ -#define SCB_AHBPCR_SZ_Msk (7UL << SCB_AHBPCR_SZ_Pos) /*!< SCB AHBPCR: SZ Mask */ +#define SCB_AHBPCR_SZ_Pos 1 /*!< SCB AHBPCR: SZ Position */ +#define SCB_AHBPCR_SZ_Msk (7UL << SCB_AHBPCR_SZ_Pos) /*!< SCB AHBPCR: SZ Mask */ -#define SCB_AHBPCR_EN_Pos 0 /*!< SCB AHBPCR: EN Position */ -#define SCB_AHBPCR_EN_Msk (1UL << SCB_AHBPCR_EN_Pos) /*!< SCB AHBPCR: EN Mask */ +#define SCB_AHBPCR_EN_Pos 0 /*!< SCB AHBPCR: EN Position */ +#define SCB_AHBPCR_EN_Msk (1UL << SCB_AHBPCR_EN_Pos) /*!< SCB AHBPCR: EN Mask */ /* L1 Cache Control Register */ -#define SCB_CACR_FORCEWT_Pos 2 /*!< SCB CACR: FORCEWT Position */ -#define SCB_CACR_FORCEWT_Msk (1UL << SCB_CACR_FORCEWT_Pos) /*!< SCB CACR: FORCEWT Mask */ +#define SCB_CACR_FORCEWT_Pos 2 /*!< SCB CACR: FORCEWT Position */ +#define SCB_CACR_FORCEWT_Msk (1UL << SCB_CACR_FORCEWT_Pos) /*!< SCB CACR: FORCEWT Mask */ -#define SCB_CACR_ECCEN_Pos 1 /*!< SCB CACR: ECCEN Position */ -#define SCB_CACR_ECCEN_Msk (1UL << SCB_CACR_ECCEN_Pos) /*!< SCB CACR: ECCEN Mask */ +#define SCB_CACR_ECCEN_Pos 1 /*!< SCB CACR: ECCEN Position */ +#define SCB_CACR_ECCEN_Msk (1UL << SCB_CACR_ECCEN_Pos) /*!< SCB CACR: ECCEN Mask */ -#define SCB_CACR_SIWT_Pos 0 /*!< SCB CACR: SIWT Position */ -#define SCB_CACR_SIWT_Msk (1UL << SCB_CACR_SIWT_Pos) /*!< SCB CACR: SIWT Mask */ +#define SCB_CACR_SIWT_Pos 0 /*!< SCB CACR: SIWT Position */ +#define SCB_CACR_SIWT_Msk (1UL << SCB_CACR_SIWT_Pos) /*!< SCB CACR: SIWT Mask */ /* AHBS control register */ -#define SCB_AHBSCR_INITCOUNT_Pos 11 /*!< SCB AHBSCR: INITCOUNT Position */ -#define SCB_AHBSCR_INITCOUNT_Msk (0x1FUL << SCB_AHBPCR_INITCOUNT_Pos) /*!< SCB AHBSCR: INITCOUNT Mask */ +#define SCB_AHBSCR_INITCOUNT_Pos 11 /*!< SCB AHBSCR: INITCOUNT Position */ +#define SCB_AHBSCR_INITCOUNT_Msk (0x1FUL << SCB_AHBPCR_INITCOUNT_Pos) /*!< SCB AHBSCR: INITCOUNT Mask */ -#define SCB_AHBSCR_TPRI_Pos 2 /*!< SCB AHBSCR: TPRI Position */ -#define SCB_AHBSCR_TPRI_Msk (0x1FFUL << SCB_AHBPCR_TPRI_Pos) /*!< SCB AHBSCR: TPRI Mask */ +#define SCB_AHBSCR_TPRI_Pos 2 /*!< SCB AHBSCR: TPRI Position */ +#define SCB_AHBSCR_TPRI_Msk (0x1FFUL << SCB_AHBPCR_TPRI_Pos) /*!< SCB AHBSCR: TPRI Mask */ -#define SCB_AHBSCR_CTL_Pos 0 /*!< SCB AHBSCR: CTL Position*/ -#define SCB_AHBSCR_CTL_Msk (3UL << SCB_AHBPCR_CTL_Pos) /*!< SCB AHBSCR: CTL Mask */ +#define SCB_AHBSCR_CTL_Pos 0 /*!< SCB AHBSCR: CTL Position*/ +#define SCB_AHBSCR_CTL_Msk (3UL << SCB_AHBPCR_CTL_Pos) /*!< SCB AHBSCR: CTL Mask */ /* Auxiliary Bus Fault Status Register */ -#define SCB_ABFSR_AXIMTYPE_Pos 8 /*!< SCB ABFSR: AXIMTYPE Position*/ -#define SCB_ABFSR_AXIMTYPE_Msk (3UL << SCB_ABFSR_AXIMTYPE_Pos) /*!< SCB ABFSR: AXIMTYPE Mask */ +#define SCB_ABFSR_AXIMTYPE_Pos 8 /*!< SCB ABFSR: AXIMTYPE Position*/ +#define SCB_ABFSR_AXIMTYPE_Msk (3UL << SCB_ABFSR_AXIMTYPE_Pos) /*!< SCB ABFSR: AXIMTYPE Mask */ -#define SCB_ABFSR_EPPB_Pos 4 /*!< SCB ABFSR: EPPB Position*/ -#define SCB_ABFSR_EPPB_Msk (1UL << SCB_ABFSR_EPPB_Pos) /*!< SCB ABFSR: EPPB Mask */ +#define SCB_ABFSR_EPPB_Pos 4 /*!< SCB ABFSR: EPPB Position*/ +#define SCB_ABFSR_EPPB_Msk (1UL << SCB_ABFSR_EPPB_Pos) /*!< SCB ABFSR: EPPB Mask */ -#define SCB_ABFSR_AXIM_Pos 3 /*!< SCB ABFSR: AXIM Position*/ -#define SCB_ABFSR_AXIM_Msk (1UL << SCB_ABFSR_AXIM_Pos) /*!< SCB ABFSR: AXIM Mask */ +#define SCB_ABFSR_AXIM_Pos 3 /*!< SCB ABFSR: AXIM Position*/ +#define SCB_ABFSR_AXIM_Msk (1UL << SCB_ABFSR_AXIM_Pos) /*!< SCB ABFSR: AXIM Mask */ -#define SCB_ABFSR_AHBP_Pos 2 /*!< SCB ABFSR: AHBP Position*/ -#define SCB_ABFSR_AHBP_Msk (1UL << SCB_ABFSR_AHBP_Pos) /*!< SCB ABFSR: AHBP Mask */ +#define SCB_ABFSR_AHBP_Pos 2 /*!< SCB ABFSR: AHBP Position*/ +#define SCB_ABFSR_AHBP_Msk (1UL << SCB_ABFSR_AHBP_Pos) /*!< SCB ABFSR: AHBP Mask */ -#define SCB_ABFSR_DTCM_Pos 1 /*!< SCB ABFSR: DTCM Position*/ -#define SCB_ABFSR_DTCM_Msk (1UL << SCB_ABFSR_DTCM_Pos) /*!< SCB ABFSR: DTCM Mask */ +#define SCB_ABFSR_DTCM_Pos 1 /*!< SCB ABFSR: DTCM Position*/ +#define SCB_ABFSR_DTCM_Msk (1UL << SCB_ABFSR_DTCM_Pos) /*!< SCB ABFSR: DTCM Mask */ -#define SCB_ABFSR_ITCM_Pos 0 /*!< SCB ABFSR: ITCM Position*/ -#define SCB_ABFSR_ITCM_Msk (1UL << SCB_ABFSR_ITCM_Pos) /*!< SCB ABFSR: ITCM Mask */ +#define SCB_ABFSR_ITCM_Pos 0 /*!< SCB ABFSR: ITCM Position*/ +#define SCB_ABFSR_ITCM_Msk (1UL << SCB_ABFSR_ITCM_Pos) /*!< SCB ABFSR: ITCM Mask */ -/*@} end of group CMSIS_SCB */ + /*@} end of group CMSIS_SCB */ - -/** \ingroup CMSIS_core_register + /** \ingroup CMSIS_core_register \defgroup CMSIS_SCnSCB System Controls not in SCB (SCnSCB) \brief Type definitions for the System Control and ID Register not in the SCB @{ */ -/** \brief Structure type to access the System Control and ID Register not in the SCB. + /** \brief Structure type to access the System Control and ID Register not in the SCB. */ -typedef struct -{ - uint32_t RESERVED0[1]; - __I uint32_t ICTR; /*!< Offset: 0x004 (R/ ) Interrupt Controller Type Register */ - __IO uint32_t ACTLR; /*!< Offset: 0x008 (R/W) Auxiliary Control Register */ -} SCnSCB_Type; + typedef struct + { + uint32_t RESERVED0[1]; + __I uint32_t ICTR; /*!< Offset: 0x004 (R/ ) Interrupt Controller Type Register */ + __IO uint32_t ACTLR; /*!< Offset: 0x008 (R/W) Auxiliary Control Register */ + } SCnSCB_Type; /* Interrupt Controller Type Register Definitions */ -#define SCnSCB_ICTR_INTLINESNUM_Pos 0 /*!< ICTR: INTLINESNUM Position */ -#define SCnSCB_ICTR_INTLINESNUM_Msk (0xFUL << SCnSCB_ICTR_INTLINESNUM_Pos) /*!< ICTR: INTLINESNUM Mask */ +#define SCnSCB_ICTR_INTLINESNUM_Pos 0 /*!< ICTR: INTLINESNUM Position */ +#define SCnSCB_ICTR_INTLINESNUM_Msk (0xFUL << SCnSCB_ICTR_INTLINESNUM_Pos) /*!< ICTR: INTLINESNUM Mask */ /* Auxiliary Control Register Definitions */ -#define SCnSCB_ACTLR_DISITMATBFLUSH_Pos 12 /*!< ACTLR: DISITMATBFLUSH Position */ -#define SCnSCB_ACTLR_DISITMATBFLUSH_Msk (1UL << SCnSCB_ACTLR_DISITMATBFLUSH_Pos) /*!< ACTLR: DISITMATBFLUSH Mask */ +#define SCnSCB_ACTLR_DISITMATBFLUSH_Pos 12 /*!< ACTLR: DISITMATBFLUSH Position */ +#define SCnSCB_ACTLR_DISITMATBFLUSH_Msk (1UL << SCnSCB_ACTLR_DISITMATBFLUSH_Pos) /*!< ACTLR: DISITMATBFLUSH Mask */ -#define SCnSCB_ACTLR_DISRAMODE_Pos 11 /*!< ACTLR: DISRAMODE Position */ -#define SCnSCB_ACTLR_DISRAMODE_Msk (1UL << SCnSCB_ACTLR_DISRAMODE_Pos) /*!< ACTLR: DISRAMODE Mask */ +#define SCnSCB_ACTLR_DISRAMODE_Pos 11 /*!< ACTLR: DISRAMODE Position */ +#define SCnSCB_ACTLR_DISRAMODE_Msk (1UL << SCnSCB_ACTLR_DISRAMODE_Pos) /*!< ACTLR: DISRAMODE Mask */ -#define SCnSCB_ACTLR_FPEXCODIS_Pos 10 /*!< ACTLR: FPEXCODIS Position */ -#define SCnSCB_ACTLR_FPEXCODIS_Msk (1UL << SCnSCB_ACTLR_FPEXCODIS_Pos) /*!< ACTLR: FPEXCODIS Mask */ +#define SCnSCB_ACTLR_FPEXCODIS_Pos 10 /*!< ACTLR: FPEXCODIS Position */ +#define SCnSCB_ACTLR_FPEXCODIS_Msk (1UL << SCnSCB_ACTLR_FPEXCODIS_Pos) /*!< ACTLR: FPEXCODIS Mask */ -#define SCnSCB_ACTLR_DISFOLD_Pos 2 /*!< ACTLR: DISFOLD Position */ -#define SCnSCB_ACTLR_DISFOLD_Msk (1UL << SCnSCB_ACTLR_DISFOLD_Pos) /*!< ACTLR: DISFOLD Mask */ +#define SCnSCB_ACTLR_DISFOLD_Pos 2 /*!< ACTLR: DISFOLD Position */ +#define SCnSCB_ACTLR_DISFOLD_Msk (1UL << SCnSCB_ACTLR_DISFOLD_Pos) /*!< ACTLR: DISFOLD Mask */ -#define SCnSCB_ACTLR_DISMCYCINT_Pos 0 /*!< ACTLR: DISMCYCINT Position */ -#define SCnSCB_ACTLR_DISMCYCINT_Msk (1UL << SCnSCB_ACTLR_DISMCYCINT_Pos) /*!< ACTLR: DISMCYCINT Mask */ +#define SCnSCB_ACTLR_DISMCYCINT_Pos 0 /*!< ACTLR: DISMCYCINT Position */ +#define SCnSCB_ACTLR_DISMCYCINT_Msk (1UL << SCnSCB_ACTLR_DISMCYCINT_Pos) /*!< ACTLR: DISMCYCINT Mask */ -/*@} end of group CMSIS_SCnotSCB */ + /*@} end of group CMSIS_SCnotSCB */ - -/** \ingroup CMSIS_core_register + /** \ingroup CMSIS_core_register \defgroup CMSIS_SysTick System Tick Timer (SysTick) \brief Type definitions for the System Timer Registers. @{ */ -/** \brief Structure type to access the System Timer (SysTick). + /** \brief Structure type to access the System Timer (SysTick). */ -typedef struct -{ - __IO uint32_t CTRL; /*!< Offset: 0x000 (R/W) SysTick Control and Status Register */ - __IO uint32_t LOAD; /*!< Offset: 0x004 (R/W) SysTick Reload Value Register */ - __IO uint32_t VAL; /*!< Offset: 0x008 (R/W) SysTick Current Value Register */ - __I uint32_t CALIB; /*!< Offset: 0x00C (R/ ) SysTick Calibration Register */ -} SysTick_Type; + typedef struct + { + __IO uint32_t CTRL; /*!< Offset: 0x000 (R/W) SysTick Control and Status Register */ + __IO uint32_t LOAD; /*!< Offset: 0x004 (R/W) SysTick Reload Value Register */ + __IO uint32_t VAL; /*!< Offset: 0x008 (R/W) SysTick Current Value Register */ + __I uint32_t CALIB; /*!< Offset: 0x00C (R/ ) SysTick Calibration Register */ + } SysTick_Type; /* SysTick Control / Status Register Definitions */ -#define SysTick_CTRL_COUNTFLAG_Pos 16 /*!< SysTick CTRL: COUNTFLAG Position */ -#define SysTick_CTRL_COUNTFLAG_Msk (1UL << SysTick_CTRL_COUNTFLAG_Pos) /*!< SysTick CTRL: COUNTFLAG Mask */ +#define SysTick_CTRL_COUNTFLAG_Pos 16 /*!< SysTick CTRL: COUNTFLAG Position */ +#define SysTick_CTRL_COUNTFLAG_Msk (1UL << SysTick_CTRL_COUNTFLAG_Pos) /*!< SysTick CTRL: COUNTFLAG Mask */ -#define SysTick_CTRL_CLKSOURCE_Pos 2 /*!< SysTick CTRL: CLKSOURCE Position */ -#define SysTick_CTRL_CLKSOURCE_Msk (1UL << SysTick_CTRL_CLKSOURCE_Pos) /*!< SysTick CTRL: CLKSOURCE Mask */ +#define SysTick_CTRL_CLKSOURCE_Pos 2 /*!< SysTick CTRL: CLKSOURCE Position */ +#define SysTick_CTRL_CLKSOURCE_Msk (1UL << SysTick_CTRL_CLKSOURCE_Pos) /*!< SysTick CTRL: CLKSOURCE Mask */ -#define SysTick_CTRL_TICKINT_Pos 1 /*!< SysTick CTRL: TICKINT Position */ -#define SysTick_CTRL_TICKINT_Msk (1UL << SysTick_CTRL_TICKINT_Pos) /*!< SysTick CTRL: TICKINT Mask */ +#define SysTick_CTRL_TICKINT_Pos 1 /*!< SysTick CTRL: TICKINT Position */ +#define SysTick_CTRL_TICKINT_Msk (1UL << SysTick_CTRL_TICKINT_Pos) /*!< SysTick CTRL: TICKINT Mask */ -#define SysTick_CTRL_ENABLE_Pos 0 /*!< SysTick CTRL: ENABLE Position */ -#define SysTick_CTRL_ENABLE_Msk (1UL << SysTick_CTRL_ENABLE_Pos) /*!< SysTick CTRL: ENABLE Mask */ +#define SysTick_CTRL_ENABLE_Pos 0 /*!< SysTick CTRL: ENABLE Position */ +#define SysTick_CTRL_ENABLE_Msk (1UL << SysTick_CTRL_ENABLE_Pos) /*!< SysTick CTRL: ENABLE Mask */ /* SysTick Reload Register Definitions */ -#define SysTick_LOAD_RELOAD_Pos 0 /*!< SysTick LOAD: RELOAD Position */ -#define SysTick_LOAD_RELOAD_Msk (0xFFFFFFUL << SysTick_LOAD_RELOAD_Pos) /*!< SysTick LOAD: RELOAD Mask */ +#define SysTick_LOAD_RELOAD_Pos 0 /*!< SysTick LOAD: RELOAD Position */ +#define SysTick_LOAD_RELOAD_Msk (0xFFFFFFUL << SysTick_LOAD_RELOAD_Pos) /*!< SysTick LOAD: RELOAD Mask */ /* SysTick Current Register Definitions */ -#define SysTick_VAL_CURRENT_Pos 0 /*!< SysTick VAL: CURRENT Position */ -#define SysTick_VAL_CURRENT_Msk (0xFFFFFFUL << SysTick_VAL_CURRENT_Pos) /*!< SysTick VAL: CURRENT Mask */ +#define SysTick_VAL_CURRENT_Pos 0 /*!< SysTick VAL: CURRENT Position */ +#define SysTick_VAL_CURRENT_Msk (0xFFFFFFUL << SysTick_VAL_CURRENT_Pos) /*!< SysTick VAL: CURRENT Mask */ /* SysTick Calibration Register Definitions */ -#define SysTick_CALIB_NOREF_Pos 31 /*!< SysTick CALIB: NOREF Position */ -#define SysTick_CALIB_NOREF_Msk (1UL << SysTick_CALIB_NOREF_Pos) /*!< SysTick CALIB: NOREF Mask */ - -#define SysTick_CALIB_SKEW_Pos 30 /*!< SysTick CALIB: SKEW Position */ -#define SysTick_CALIB_SKEW_Msk (1UL << SysTick_CALIB_SKEW_Pos) /*!< SysTick CALIB: SKEW Mask */ +#define SysTick_CALIB_NOREF_Pos 31 /*!< SysTick CALIB: NOREF Position */ +#define SysTick_CALIB_NOREF_Msk (1UL << SysTick_CALIB_NOREF_Pos) /*!< SysTick CALIB: NOREF Mask */ -#define SysTick_CALIB_TENMS_Pos 0 /*!< SysTick CALIB: TENMS Position */ -#define SysTick_CALIB_TENMS_Msk (0xFFFFFFUL << SysTick_CALIB_TENMS_Pos) /*!< SysTick CALIB: TENMS Mask */ +#define SysTick_CALIB_SKEW_Pos 30 /*!< SysTick CALIB: SKEW Position */ +#define SysTick_CALIB_SKEW_Msk (1UL << SysTick_CALIB_SKEW_Pos) /*!< SysTick CALIB: SKEW Mask */ -/*@} end of group CMSIS_SysTick */ +#define SysTick_CALIB_TENMS_Pos 0 /*!< SysTick CALIB: TENMS Position */ +#define SysTick_CALIB_TENMS_Msk (0xFFFFFFUL << SysTick_CALIB_TENMS_Pos) /*!< SysTick CALIB: TENMS Mask */ + /*@} end of group CMSIS_SysTick */ -/** \ingroup CMSIS_core_register + /** \ingroup CMSIS_core_register \defgroup CMSIS_ITM Instrumentation Trace Macrocell (ITM) \brief Type definitions for the Instrumentation Trace Macrocell (ITM) @{ */ -/** \brief Structure type to access the Instrumentation Trace Macrocell Register (ITM). + /** \brief Structure type to access the Instrumentation Trace Macrocell Register (ITM). */ -typedef struct -{ - __O union - { - __O uint8_t u8; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 8-bit */ - __O uint16_t u16; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 16-bit */ - __O uint32_t u32; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 32-bit */ - } PORT [32]; /*!< Offset: 0x000 ( /W) ITM Stimulus Port Registers */ - uint32_t RESERVED0[864]; - __IO uint32_t TER; /*!< Offset: 0xE00 (R/W) ITM Trace Enable Register */ - uint32_t RESERVED1[15]; - __IO uint32_t TPR; /*!< Offset: 0xE40 (R/W) ITM Trace Privilege Register */ - uint32_t RESERVED2[15]; - __IO uint32_t TCR; /*!< Offset: 0xE80 (R/W) ITM Trace Control Register */ - uint32_t RESERVED3[29]; - __O uint32_t IWR; /*!< Offset: 0xEF8 ( /W) ITM Integration Write Register */ - __I uint32_t IRR; /*!< Offset: 0xEFC (R/ ) ITM Integration Read Register */ - __IO uint32_t IMCR; /*!< Offset: 0xF00 (R/W) ITM Integration Mode Control Register */ - uint32_t RESERVED4[43]; - __O uint32_t LAR; /*!< Offset: 0xFB0 ( /W) ITM Lock Access Register */ - __I uint32_t LSR; /*!< Offset: 0xFB4 (R/ ) ITM Lock Status Register */ - uint32_t RESERVED5[6]; - __I uint32_t PID4; /*!< Offset: 0xFD0 (R/ ) ITM Peripheral Identification Register #4 */ - __I uint32_t PID5; /*!< Offset: 0xFD4 (R/ ) ITM Peripheral Identification Register #5 */ - __I uint32_t PID6; /*!< Offset: 0xFD8 (R/ ) ITM Peripheral Identification Register #6 */ - __I uint32_t PID7; /*!< Offset: 0xFDC (R/ ) ITM Peripheral Identification Register #7 */ - __I uint32_t PID0; /*!< Offset: 0xFE0 (R/ ) ITM Peripheral Identification Register #0 */ - __I uint32_t PID1; /*!< Offset: 0xFE4 (R/ ) ITM Peripheral Identification Register #1 */ - __I uint32_t PID2; /*!< Offset: 0xFE8 (R/ ) ITM Peripheral Identification Register #2 */ - __I uint32_t PID3; /*!< Offset: 0xFEC (R/ ) ITM Peripheral Identification Register #3 */ - __I uint32_t CID0; /*!< Offset: 0xFF0 (R/ ) ITM Component Identification Register #0 */ - __I uint32_t CID1; /*!< Offset: 0xFF4 (R/ ) ITM Component Identification Register #1 */ - __I uint32_t CID2; /*!< Offset: 0xFF8 (R/ ) ITM Component Identification Register #2 */ - __I uint32_t CID3; /*!< Offset: 0xFFC (R/ ) ITM Component Identification Register #3 */ -} ITM_Type; + typedef struct + { + __O union + { + __O uint8_t u8; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 8-bit */ + __O uint16_t u16; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 16-bit */ + __O uint32_t u32; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 32-bit */ + } PORT[32]; /*!< Offset: 0x000 ( /W) ITM Stimulus Port Registers */ + uint32_t RESERVED0[864]; + __IO uint32_t TER; /*!< Offset: 0xE00 (R/W) ITM Trace Enable Register */ + uint32_t RESERVED1[15]; + __IO uint32_t TPR; /*!< Offset: 0xE40 (R/W) ITM Trace Privilege Register */ + uint32_t RESERVED2[15]; + __IO uint32_t TCR; /*!< Offset: 0xE80 (R/W) ITM Trace Control Register */ + uint32_t RESERVED3[29]; + __O uint32_t IWR; /*!< Offset: 0xEF8 ( /W) ITM Integration Write Register */ + __I uint32_t IRR; /*!< Offset: 0xEFC (R/ ) ITM Integration Read Register */ + __IO uint32_t IMCR; /*!< Offset: 0xF00 (R/W) ITM Integration Mode Control Register */ + uint32_t RESERVED4[43]; + __O uint32_t LAR; /*!< Offset: 0xFB0 ( /W) ITM Lock Access Register */ + __I uint32_t LSR; /*!< Offset: 0xFB4 (R/ ) ITM Lock Status Register */ + uint32_t RESERVED5[6]; + __I uint32_t PID4; /*!< Offset: 0xFD0 (R/ ) ITM Peripheral Identification Register #4 */ + __I uint32_t PID5; /*!< Offset: 0xFD4 (R/ ) ITM Peripheral Identification Register #5 */ + __I uint32_t PID6; /*!< Offset: 0xFD8 (R/ ) ITM Peripheral Identification Register #6 */ + __I uint32_t PID7; /*!< Offset: 0xFDC (R/ ) ITM Peripheral Identification Register #7 */ + __I uint32_t PID0; /*!< Offset: 0xFE0 (R/ ) ITM Peripheral Identification Register #0 */ + __I uint32_t PID1; /*!< Offset: 0xFE4 (R/ ) ITM Peripheral Identification Register #1 */ + __I uint32_t PID2; /*!< Offset: 0xFE8 (R/ ) ITM Peripheral Identification Register #2 */ + __I uint32_t PID3; /*!< Offset: 0xFEC (R/ ) ITM Peripheral Identification Register #3 */ + __I uint32_t CID0; /*!< Offset: 0xFF0 (R/ ) ITM Component Identification Register #0 */ + __I uint32_t CID1; /*!< Offset: 0xFF4 (R/ ) ITM Component Identification Register #1 */ + __I uint32_t CID2; /*!< Offset: 0xFF8 (R/ ) ITM Component Identification Register #2 */ + __I uint32_t CID3; /*!< Offset: 0xFFC (R/ ) ITM Component Identification Register #3 */ + } ITM_Type; /* ITM Trace Privilege Register Definitions */ -#define ITM_TPR_PRIVMASK_Pos 0 /*!< ITM TPR: PRIVMASK Position */ -#define ITM_TPR_PRIVMASK_Msk (0xFUL << ITM_TPR_PRIVMASK_Pos) /*!< ITM TPR: PRIVMASK Mask */ +#define ITM_TPR_PRIVMASK_Pos 0 /*!< ITM TPR: PRIVMASK Position */ +#define ITM_TPR_PRIVMASK_Msk (0xFUL << ITM_TPR_PRIVMASK_Pos) /*!< ITM TPR: PRIVMASK Mask */ /* ITM Trace Control Register Definitions */ -#define ITM_TCR_BUSY_Pos 23 /*!< ITM TCR: BUSY Position */ -#define ITM_TCR_BUSY_Msk (1UL << ITM_TCR_BUSY_Pos) /*!< ITM TCR: BUSY Mask */ +#define ITM_TCR_BUSY_Pos 23 /*!< ITM TCR: BUSY Position */ +#define ITM_TCR_BUSY_Msk (1UL << ITM_TCR_BUSY_Pos) /*!< ITM TCR: BUSY Mask */ -#define ITM_TCR_TraceBusID_Pos 16 /*!< ITM TCR: ATBID Position */ -#define ITM_TCR_TraceBusID_Msk (0x7FUL << ITM_TCR_TraceBusID_Pos) /*!< ITM TCR: ATBID Mask */ +#define ITM_TCR_TraceBusID_Pos 16 /*!< ITM TCR: ATBID Position */ +#define ITM_TCR_TraceBusID_Msk (0x7FUL << ITM_TCR_TraceBusID_Pos) /*!< ITM TCR: ATBID Mask */ -#define ITM_TCR_GTSFREQ_Pos 10 /*!< ITM TCR: Global timestamp frequency Position */ -#define ITM_TCR_GTSFREQ_Msk (3UL << ITM_TCR_GTSFREQ_Pos) /*!< ITM TCR: Global timestamp frequency Mask */ +#define ITM_TCR_GTSFREQ_Pos 10 /*!< ITM TCR: Global timestamp frequency Position */ +#define ITM_TCR_GTSFREQ_Msk (3UL << ITM_TCR_GTSFREQ_Pos) /*!< ITM TCR: Global timestamp frequency Mask */ -#define ITM_TCR_TSPrescale_Pos 8 /*!< ITM TCR: TSPrescale Position */ -#define ITM_TCR_TSPrescale_Msk (3UL << ITM_TCR_TSPrescale_Pos) /*!< ITM TCR: TSPrescale Mask */ +#define ITM_TCR_TSPrescale_Pos 8 /*!< ITM TCR: TSPrescale Position */ +#define ITM_TCR_TSPrescale_Msk (3UL << ITM_TCR_TSPrescale_Pos) /*!< ITM TCR: TSPrescale Mask */ -#define ITM_TCR_SWOENA_Pos 4 /*!< ITM TCR: SWOENA Position */ -#define ITM_TCR_SWOENA_Msk (1UL << ITM_TCR_SWOENA_Pos) /*!< ITM TCR: SWOENA Mask */ +#define ITM_TCR_SWOENA_Pos 4 /*!< ITM TCR: SWOENA Position */ +#define ITM_TCR_SWOENA_Msk (1UL << ITM_TCR_SWOENA_Pos) /*!< ITM TCR: SWOENA Mask */ -#define ITM_TCR_DWTENA_Pos 3 /*!< ITM TCR: DWTENA Position */ -#define ITM_TCR_DWTENA_Msk (1UL << ITM_TCR_DWTENA_Pos) /*!< ITM TCR: DWTENA Mask */ +#define ITM_TCR_DWTENA_Pos 3 /*!< ITM TCR: DWTENA Position */ +#define ITM_TCR_DWTENA_Msk (1UL << ITM_TCR_DWTENA_Pos) /*!< ITM TCR: DWTENA Mask */ -#define ITM_TCR_SYNCENA_Pos 2 /*!< ITM TCR: SYNCENA Position */ -#define ITM_TCR_SYNCENA_Msk (1UL << ITM_TCR_SYNCENA_Pos) /*!< ITM TCR: SYNCENA Mask */ +#define ITM_TCR_SYNCENA_Pos 2 /*!< ITM TCR: SYNCENA Position */ +#define ITM_TCR_SYNCENA_Msk (1UL << ITM_TCR_SYNCENA_Pos) /*!< ITM TCR: SYNCENA Mask */ -#define ITM_TCR_TSENA_Pos 1 /*!< ITM TCR: TSENA Position */ -#define ITM_TCR_TSENA_Msk (1UL << ITM_TCR_TSENA_Pos) /*!< ITM TCR: TSENA Mask */ +#define ITM_TCR_TSENA_Pos 1 /*!< ITM TCR: TSENA Position */ +#define ITM_TCR_TSENA_Msk (1UL << ITM_TCR_TSENA_Pos) /*!< ITM TCR: TSENA Mask */ -#define ITM_TCR_ITMENA_Pos 0 /*!< ITM TCR: ITM Enable bit Position */ -#define ITM_TCR_ITMENA_Msk (1UL << ITM_TCR_ITMENA_Pos) /*!< ITM TCR: ITM Enable bit Mask */ +#define ITM_TCR_ITMENA_Pos 0 /*!< ITM TCR: ITM Enable bit Position */ +#define ITM_TCR_ITMENA_Msk (1UL << ITM_TCR_ITMENA_Pos) /*!< ITM TCR: ITM Enable bit Mask */ /* ITM Integration Write Register Definitions */ -#define ITM_IWR_ATVALIDM_Pos 0 /*!< ITM IWR: ATVALIDM Position */ -#define ITM_IWR_ATVALIDM_Msk (1UL << ITM_IWR_ATVALIDM_Pos) /*!< ITM IWR: ATVALIDM Mask */ +#define ITM_IWR_ATVALIDM_Pos 0 /*!< ITM IWR: ATVALIDM Position */ +#define ITM_IWR_ATVALIDM_Msk (1UL << ITM_IWR_ATVALIDM_Pos) /*!< ITM IWR: ATVALIDM Mask */ /* ITM Integration Read Register Definitions */ -#define ITM_IRR_ATREADYM_Pos 0 /*!< ITM IRR: ATREADYM Position */ -#define ITM_IRR_ATREADYM_Msk (1UL << ITM_IRR_ATREADYM_Pos) /*!< ITM IRR: ATREADYM Mask */ +#define ITM_IRR_ATREADYM_Pos 0 /*!< ITM IRR: ATREADYM Position */ +#define ITM_IRR_ATREADYM_Msk (1UL << ITM_IRR_ATREADYM_Pos) /*!< ITM IRR: ATREADYM Mask */ /* ITM Integration Mode Control Register Definitions */ -#define ITM_IMCR_INTEGRATION_Pos 0 /*!< ITM IMCR: INTEGRATION Position */ -#define ITM_IMCR_INTEGRATION_Msk (1UL << ITM_IMCR_INTEGRATION_Pos) /*!< ITM IMCR: INTEGRATION Mask */ +#define ITM_IMCR_INTEGRATION_Pos 0 /*!< ITM IMCR: INTEGRATION Position */ +#define ITM_IMCR_INTEGRATION_Msk (1UL << ITM_IMCR_INTEGRATION_Pos) /*!< ITM IMCR: INTEGRATION Mask */ /* ITM Lock Status Register Definitions */ -#define ITM_LSR_ByteAcc_Pos 2 /*!< ITM LSR: ByteAcc Position */ -#define ITM_LSR_ByteAcc_Msk (1UL << ITM_LSR_ByteAcc_Pos) /*!< ITM LSR: ByteAcc Mask */ - -#define ITM_LSR_Access_Pos 1 /*!< ITM LSR: Access Position */ -#define ITM_LSR_Access_Msk (1UL << ITM_LSR_Access_Pos) /*!< ITM LSR: Access Mask */ +#define ITM_LSR_ByteAcc_Pos 2 /*!< ITM LSR: ByteAcc Position */ +#define ITM_LSR_ByteAcc_Msk (1UL << ITM_LSR_ByteAcc_Pos) /*!< ITM LSR: ByteAcc Mask */ -#define ITM_LSR_Present_Pos 0 /*!< ITM LSR: Present Position */ -#define ITM_LSR_Present_Msk (1UL << ITM_LSR_Present_Pos) /*!< ITM LSR: Present Mask */ +#define ITM_LSR_Access_Pos 1 /*!< ITM LSR: Access Position */ +#define ITM_LSR_Access_Msk (1UL << ITM_LSR_Access_Pos) /*!< ITM LSR: Access Mask */ -/*@}*/ /* end of group CMSIS_ITM */ +#define ITM_LSR_Present_Pos 0 /*!< ITM LSR: Present Position */ +#define ITM_LSR_Present_Msk (1UL << ITM_LSR_Present_Pos) /*!< ITM LSR: Present Mask */ + /*@}*/ /* end of group CMSIS_ITM */ -/** \ingroup CMSIS_core_register + /** \ingroup CMSIS_core_register \defgroup CMSIS_DWT Data Watchpoint and Trace (DWT) \brief Type definitions for the Data Watchpoint and Trace (DWT) @{ */ -/** \brief Structure type to access the Data Watchpoint and Trace Register (DWT). + /** \brief Structure type to access the Data Watchpoint and Trace Register (DWT). */ -typedef struct -{ - __IO uint32_t CTRL; /*!< Offset: 0x000 (R/W) Control Register */ - __IO uint32_t CYCCNT; /*!< Offset: 0x004 (R/W) Cycle Count Register */ - __IO uint32_t CPICNT; /*!< Offset: 0x008 (R/W) CPI Count Register */ - __IO uint32_t EXCCNT; /*!< Offset: 0x00C (R/W) Exception Overhead Count Register */ - __IO uint32_t SLEEPCNT; /*!< Offset: 0x010 (R/W) Sleep Count Register */ - __IO uint32_t LSUCNT; /*!< Offset: 0x014 (R/W) LSU Count Register */ - __IO uint32_t FOLDCNT; /*!< Offset: 0x018 (R/W) Folded-instruction Count Register */ - __I uint32_t PCSR; /*!< Offset: 0x01C (R/ ) Program Counter Sample Register */ - __IO uint32_t COMP0; /*!< Offset: 0x020 (R/W) Comparator Register 0 */ - __IO uint32_t MASK0; /*!< Offset: 0x024 (R/W) Mask Register 0 */ - __IO uint32_t FUNCTION0; /*!< Offset: 0x028 (R/W) Function Register 0 */ - uint32_t RESERVED0[1]; - __IO uint32_t COMP1; /*!< Offset: 0x030 (R/W) Comparator Register 1 */ - __IO uint32_t MASK1; /*!< Offset: 0x034 (R/W) Mask Register 1 */ - __IO uint32_t FUNCTION1; /*!< Offset: 0x038 (R/W) Function Register 1 */ - uint32_t RESERVED1[1]; - __IO uint32_t COMP2; /*!< Offset: 0x040 (R/W) Comparator Register 2 */ - __IO uint32_t MASK2; /*!< Offset: 0x044 (R/W) Mask Register 2 */ - __IO uint32_t FUNCTION2; /*!< Offset: 0x048 (R/W) Function Register 2 */ - uint32_t RESERVED2[1]; - __IO uint32_t COMP3; /*!< Offset: 0x050 (R/W) Comparator Register 3 */ - __IO uint32_t MASK3; /*!< Offset: 0x054 (R/W) Mask Register 3 */ - __IO uint32_t FUNCTION3; /*!< Offset: 0x058 (R/W) Function Register 3 */ - uint32_t RESERVED3[981]; - __O uint32_t LAR; /*!< Offset: 0xFB0 ( W) Lock Access Register */ - __I uint32_t LSR; /*!< Offset: 0xFB4 (R ) Lock Status Register */ -} DWT_Type; + typedef struct + { + __IO uint32_t CTRL; /*!< Offset: 0x000 (R/W) Control Register */ + __IO uint32_t CYCCNT; /*!< Offset: 0x004 (R/W) Cycle Count Register */ + __IO uint32_t CPICNT; /*!< Offset: 0x008 (R/W) CPI Count Register */ + __IO uint32_t EXCCNT; /*!< Offset: 0x00C (R/W) Exception Overhead Count Register */ + __IO uint32_t SLEEPCNT; /*!< Offset: 0x010 (R/W) Sleep Count Register */ + __IO uint32_t LSUCNT; /*!< Offset: 0x014 (R/W) LSU Count Register */ + __IO uint32_t FOLDCNT; /*!< Offset: 0x018 (R/W) Folded-instruction Count Register */ + __I uint32_t PCSR; /*!< Offset: 0x01C (R/ ) Program Counter Sample Register */ + __IO uint32_t COMP0; /*!< Offset: 0x020 (R/W) Comparator Register 0 */ + __IO uint32_t MASK0; /*!< Offset: 0x024 (R/W) Mask Register 0 */ + __IO uint32_t FUNCTION0; /*!< Offset: 0x028 (R/W) Function Register 0 */ + uint32_t RESERVED0[1]; + __IO uint32_t COMP1; /*!< Offset: 0x030 (R/W) Comparator Register 1 */ + __IO uint32_t MASK1; /*!< Offset: 0x034 (R/W) Mask Register 1 */ + __IO uint32_t FUNCTION1; /*!< Offset: 0x038 (R/W) Function Register 1 */ + uint32_t RESERVED1[1]; + __IO uint32_t COMP2; /*!< Offset: 0x040 (R/W) Comparator Register 2 */ + __IO uint32_t MASK2; /*!< Offset: 0x044 (R/W) Mask Register 2 */ + __IO uint32_t FUNCTION2; /*!< Offset: 0x048 (R/W) Function Register 2 */ + uint32_t RESERVED2[1]; + __IO uint32_t COMP3; /*!< Offset: 0x050 (R/W) Comparator Register 3 */ + __IO uint32_t MASK3; /*!< Offset: 0x054 (R/W) Mask Register 3 */ + __IO uint32_t FUNCTION3; /*!< Offset: 0x058 (R/W) Function Register 3 */ + uint32_t RESERVED3[981]; + __O uint32_t LAR; /*!< Offset: 0xFB0 ( W) Lock Access Register */ + __I uint32_t LSR; /*!< Offset: 0xFB4 (R ) Lock Status Register */ + } DWT_Type; /* DWT Control Register Definitions */ -#define DWT_CTRL_NUMCOMP_Pos 28 /*!< DWT CTRL: NUMCOMP Position */ -#define DWT_CTRL_NUMCOMP_Msk (0xFUL << DWT_CTRL_NUMCOMP_Pos) /*!< DWT CTRL: NUMCOMP Mask */ +#define DWT_CTRL_NUMCOMP_Pos 28 /*!< DWT CTRL: NUMCOMP Position */ +#define DWT_CTRL_NUMCOMP_Msk (0xFUL << DWT_CTRL_NUMCOMP_Pos) /*!< DWT CTRL: NUMCOMP Mask */ -#define DWT_CTRL_NOTRCPKT_Pos 27 /*!< DWT CTRL: NOTRCPKT Position */ -#define DWT_CTRL_NOTRCPKT_Msk (0x1UL << DWT_CTRL_NOTRCPKT_Pos) /*!< DWT CTRL: NOTRCPKT Mask */ +#define DWT_CTRL_NOTRCPKT_Pos 27 /*!< DWT CTRL: NOTRCPKT Position */ +#define DWT_CTRL_NOTRCPKT_Msk (0x1UL << DWT_CTRL_NOTRCPKT_Pos) /*!< DWT CTRL: NOTRCPKT Mask */ -#define DWT_CTRL_NOEXTTRIG_Pos 26 /*!< DWT CTRL: NOEXTTRIG Position */ -#define DWT_CTRL_NOEXTTRIG_Msk (0x1UL << DWT_CTRL_NOEXTTRIG_Pos) /*!< DWT CTRL: NOEXTTRIG Mask */ +#define DWT_CTRL_NOEXTTRIG_Pos 26 /*!< DWT CTRL: NOEXTTRIG Position */ +#define DWT_CTRL_NOEXTTRIG_Msk (0x1UL << DWT_CTRL_NOEXTTRIG_Pos) /*!< DWT CTRL: NOEXTTRIG Mask */ -#define DWT_CTRL_NOCYCCNT_Pos 25 /*!< DWT CTRL: NOCYCCNT Position */ -#define DWT_CTRL_NOCYCCNT_Msk (0x1UL << DWT_CTRL_NOCYCCNT_Pos) /*!< DWT CTRL: NOCYCCNT Mask */ +#define DWT_CTRL_NOCYCCNT_Pos 25 /*!< DWT CTRL: NOCYCCNT Position */ +#define DWT_CTRL_NOCYCCNT_Msk (0x1UL << DWT_CTRL_NOCYCCNT_Pos) /*!< DWT CTRL: NOCYCCNT Mask */ -#define DWT_CTRL_NOPRFCNT_Pos 24 /*!< DWT CTRL: NOPRFCNT Position */ -#define DWT_CTRL_NOPRFCNT_Msk (0x1UL << DWT_CTRL_NOPRFCNT_Pos) /*!< DWT CTRL: NOPRFCNT Mask */ +#define DWT_CTRL_NOPRFCNT_Pos 24 /*!< DWT CTRL: NOPRFCNT Position */ +#define DWT_CTRL_NOPRFCNT_Msk (0x1UL << DWT_CTRL_NOPRFCNT_Pos) /*!< DWT CTRL: NOPRFCNT Mask */ -#define DWT_CTRL_CYCEVTENA_Pos 22 /*!< DWT CTRL: CYCEVTENA Position */ -#define DWT_CTRL_CYCEVTENA_Msk (0x1UL << DWT_CTRL_CYCEVTENA_Pos) /*!< DWT CTRL: CYCEVTENA Mask */ +#define DWT_CTRL_CYCEVTENA_Pos 22 /*!< DWT CTRL: CYCEVTENA Position */ +#define DWT_CTRL_CYCEVTENA_Msk (0x1UL << DWT_CTRL_CYCEVTENA_Pos) /*!< DWT CTRL: CYCEVTENA Mask */ -#define DWT_CTRL_FOLDEVTENA_Pos 21 /*!< DWT CTRL: FOLDEVTENA Position */ -#define DWT_CTRL_FOLDEVTENA_Msk (0x1UL << DWT_CTRL_FOLDEVTENA_Pos) /*!< DWT CTRL: FOLDEVTENA Mask */ +#define DWT_CTRL_FOLDEVTENA_Pos 21 /*!< DWT CTRL: FOLDEVTENA Position */ +#define DWT_CTRL_FOLDEVTENA_Msk (0x1UL << DWT_CTRL_FOLDEVTENA_Pos) /*!< DWT CTRL: FOLDEVTENA Mask */ -#define DWT_CTRL_LSUEVTENA_Pos 20 /*!< DWT CTRL: LSUEVTENA Position */ -#define DWT_CTRL_LSUEVTENA_Msk (0x1UL << DWT_CTRL_LSUEVTENA_Pos) /*!< DWT CTRL: LSUEVTENA Mask */ +#define DWT_CTRL_LSUEVTENA_Pos 20 /*!< DWT CTRL: LSUEVTENA Position */ +#define DWT_CTRL_LSUEVTENA_Msk (0x1UL << DWT_CTRL_LSUEVTENA_Pos) /*!< DWT CTRL: LSUEVTENA Mask */ -#define DWT_CTRL_SLEEPEVTENA_Pos 19 /*!< DWT CTRL: SLEEPEVTENA Position */ -#define DWT_CTRL_SLEEPEVTENA_Msk (0x1UL << DWT_CTRL_SLEEPEVTENA_Pos) /*!< DWT CTRL: SLEEPEVTENA Mask */ +#define DWT_CTRL_SLEEPEVTENA_Pos 19 /*!< DWT CTRL: SLEEPEVTENA Position */ +#define DWT_CTRL_SLEEPEVTENA_Msk (0x1UL << DWT_CTRL_SLEEPEVTENA_Pos) /*!< DWT CTRL: SLEEPEVTENA Mask */ -#define DWT_CTRL_EXCEVTENA_Pos 18 /*!< DWT CTRL: EXCEVTENA Position */ -#define DWT_CTRL_EXCEVTENA_Msk (0x1UL << DWT_CTRL_EXCEVTENA_Pos) /*!< DWT CTRL: EXCEVTENA Mask */ +#define DWT_CTRL_EXCEVTENA_Pos 18 /*!< DWT CTRL: EXCEVTENA Position */ +#define DWT_CTRL_EXCEVTENA_Msk (0x1UL << DWT_CTRL_EXCEVTENA_Pos) /*!< DWT CTRL: EXCEVTENA Mask */ -#define DWT_CTRL_CPIEVTENA_Pos 17 /*!< DWT CTRL: CPIEVTENA Position */ -#define DWT_CTRL_CPIEVTENA_Msk (0x1UL << DWT_CTRL_CPIEVTENA_Pos) /*!< DWT CTRL: CPIEVTENA Mask */ +#define DWT_CTRL_CPIEVTENA_Pos 17 /*!< DWT CTRL: CPIEVTENA Position */ +#define DWT_CTRL_CPIEVTENA_Msk (0x1UL << DWT_CTRL_CPIEVTENA_Pos) /*!< DWT CTRL: CPIEVTENA Mask */ -#define DWT_CTRL_EXCTRCENA_Pos 16 /*!< DWT CTRL: EXCTRCENA Position */ -#define DWT_CTRL_EXCTRCENA_Msk (0x1UL << DWT_CTRL_EXCTRCENA_Pos) /*!< DWT CTRL: EXCTRCENA Mask */ +#define DWT_CTRL_EXCTRCENA_Pos 16 /*!< DWT CTRL: EXCTRCENA Position */ +#define DWT_CTRL_EXCTRCENA_Msk (0x1UL << DWT_CTRL_EXCTRCENA_Pos) /*!< DWT CTRL: EXCTRCENA Mask */ -#define DWT_CTRL_PCSAMPLENA_Pos 12 /*!< DWT CTRL: PCSAMPLENA Position */ -#define DWT_CTRL_PCSAMPLENA_Msk (0x1UL << DWT_CTRL_PCSAMPLENA_Pos) /*!< DWT CTRL: PCSAMPLENA Mask */ +#define DWT_CTRL_PCSAMPLENA_Pos 12 /*!< DWT CTRL: PCSAMPLENA Position */ +#define DWT_CTRL_PCSAMPLENA_Msk (0x1UL << DWT_CTRL_PCSAMPLENA_Pos) /*!< DWT CTRL: PCSAMPLENA Mask */ -#define DWT_CTRL_SYNCTAP_Pos 10 /*!< DWT CTRL: SYNCTAP Position */ -#define DWT_CTRL_SYNCTAP_Msk (0x3UL << DWT_CTRL_SYNCTAP_Pos) /*!< DWT CTRL: SYNCTAP Mask */ +#define DWT_CTRL_SYNCTAP_Pos 10 /*!< DWT CTRL: SYNCTAP Position */ +#define DWT_CTRL_SYNCTAP_Msk (0x3UL << DWT_CTRL_SYNCTAP_Pos) /*!< DWT CTRL: SYNCTAP Mask */ -#define DWT_CTRL_CYCTAP_Pos 9 /*!< DWT CTRL: CYCTAP Position */ -#define DWT_CTRL_CYCTAP_Msk (0x1UL << DWT_CTRL_CYCTAP_Pos) /*!< DWT CTRL: CYCTAP Mask */ +#define DWT_CTRL_CYCTAP_Pos 9 /*!< DWT CTRL: CYCTAP Position */ +#define DWT_CTRL_CYCTAP_Msk (0x1UL << DWT_CTRL_CYCTAP_Pos) /*!< DWT CTRL: CYCTAP Mask */ -#define DWT_CTRL_POSTINIT_Pos 5 /*!< DWT CTRL: POSTINIT Position */ -#define DWT_CTRL_POSTINIT_Msk (0xFUL << DWT_CTRL_POSTINIT_Pos) /*!< DWT CTRL: POSTINIT Mask */ +#define DWT_CTRL_POSTINIT_Pos 5 /*!< DWT CTRL: POSTINIT Position */ +#define DWT_CTRL_POSTINIT_Msk (0xFUL << DWT_CTRL_POSTINIT_Pos) /*!< DWT CTRL: POSTINIT Mask */ -#define DWT_CTRL_POSTPRESET_Pos 1 /*!< DWT CTRL: POSTPRESET Position */ -#define DWT_CTRL_POSTPRESET_Msk (0xFUL << DWT_CTRL_POSTPRESET_Pos) /*!< DWT CTRL: POSTPRESET Mask */ +#define DWT_CTRL_POSTPRESET_Pos 1 /*!< DWT CTRL: POSTPRESET Position */ +#define DWT_CTRL_POSTPRESET_Msk (0xFUL << DWT_CTRL_POSTPRESET_Pos) /*!< DWT CTRL: POSTPRESET Mask */ -#define DWT_CTRL_CYCCNTENA_Pos 0 /*!< DWT CTRL: CYCCNTENA Position */ -#define DWT_CTRL_CYCCNTENA_Msk (0x1UL << DWT_CTRL_CYCCNTENA_Pos) /*!< DWT CTRL: CYCCNTENA Mask */ +#define DWT_CTRL_CYCCNTENA_Pos 0 /*!< DWT CTRL: CYCCNTENA Position */ +#define DWT_CTRL_CYCCNTENA_Msk (0x1UL << DWT_CTRL_CYCCNTENA_Pos) /*!< DWT CTRL: CYCCNTENA Mask */ /* DWT CPI Count Register Definitions */ -#define DWT_CPICNT_CPICNT_Pos 0 /*!< DWT CPICNT: CPICNT Position */ -#define DWT_CPICNT_CPICNT_Msk (0xFFUL << DWT_CPICNT_CPICNT_Pos) /*!< DWT CPICNT: CPICNT Mask */ +#define DWT_CPICNT_CPICNT_Pos 0 /*!< DWT CPICNT: CPICNT Position */ +#define DWT_CPICNT_CPICNT_Msk (0xFFUL << DWT_CPICNT_CPICNT_Pos) /*!< DWT CPICNT: CPICNT Mask */ /* DWT Exception Overhead Count Register Definitions */ -#define DWT_EXCCNT_EXCCNT_Pos 0 /*!< DWT EXCCNT: EXCCNT Position */ -#define DWT_EXCCNT_EXCCNT_Msk (0xFFUL << DWT_EXCCNT_EXCCNT_Pos) /*!< DWT EXCCNT: EXCCNT Mask */ +#define DWT_EXCCNT_EXCCNT_Pos 0 /*!< DWT EXCCNT: EXCCNT Position */ +#define DWT_EXCCNT_EXCCNT_Msk (0xFFUL << DWT_EXCCNT_EXCCNT_Pos) /*!< DWT EXCCNT: EXCCNT Mask */ /* DWT Sleep Count Register Definitions */ -#define DWT_SLEEPCNT_SLEEPCNT_Pos 0 /*!< DWT SLEEPCNT: SLEEPCNT Position */ -#define DWT_SLEEPCNT_SLEEPCNT_Msk (0xFFUL << DWT_SLEEPCNT_SLEEPCNT_Pos) /*!< DWT SLEEPCNT: SLEEPCNT Mask */ +#define DWT_SLEEPCNT_SLEEPCNT_Pos 0 /*!< DWT SLEEPCNT: SLEEPCNT Position */ +#define DWT_SLEEPCNT_SLEEPCNT_Msk (0xFFUL << DWT_SLEEPCNT_SLEEPCNT_Pos) /*!< DWT SLEEPCNT: SLEEPCNT Mask */ /* DWT LSU Count Register Definitions */ -#define DWT_LSUCNT_LSUCNT_Pos 0 /*!< DWT LSUCNT: LSUCNT Position */ -#define DWT_LSUCNT_LSUCNT_Msk (0xFFUL << DWT_LSUCNT_LSUCNT_Pos) /*!< DWT LSUCNT: LSUCNT Mask */ +#define DWT_LSUCNT_LSUCNT_Pos 0 /*!< DWT LSUCNT: LSUCNT Position */ +#define DWT_LSUCNT_LSUCNT_Msk (0xFFUL << DWT_LSUCNT_LSUCNT_Pos) /*!< DWT LSUCNT: LSUCNT Mask */ /* DWT Folded-instruction Count Register Definitions */ -#define DWT_FOLDCNT_FOLDCNT_Pos 0 /*!< DWT FOLDCNT: FOLDCNT Position */ -#define DWT_FOLDCNT_FOLDCNT_Msk (0xFFUL << DWT_FOLDCNT_FOLDCNT_Pos) /*!< DWT FOLDCNT: FOLDCNT Mask */ +#define DWT_FOLDCNT_FOLDCNT_Pos 0 /*!< DWT FOLDCNT: FOLDCNT Position */ +#define DWT_FOLDCNT_FOLDCNT_Msk (0xFFUL << DWT_FOLDCNT_FOLDCNT_Pos) /*!< DWT FOLDCNT: FOLDCNT Mask */ /* DWT Comparator Mask Register Definitions */ -#define DWT_MASK_MASK_Pos 0 /*!< DWT MASK: MASK Position */ -#define DWT_MASK_MASK_Msk (0x1FUL << DWT_MASK_MASK_Pos) /*!< DWT MASK: MASK Mask */ +#define DWT_MASK_MASK_Pos 0 /*!< DWT MASK: MASK Position */ +#define DWT_MASK_MASK_Msk (0x1FUL << DWT_MASK_MASK_Pos) /*!< DWT MASK: MASK Mask */ /* DWT Comparator Function Register Definitions */ -#define DWT_FUNCTION_MATCHED_Pos 24 /*!< DWT FUNCTION: MATCHED Position */ -#define DWT_FUNCTION_MATCHED_Msk (0x1UL << DWT_FUNCTION_MATCHED_Pos) /*!< DWT FUNCTION: MATCHED Mask */ +#define DWT_FUNCTION_MATCHED_Pos 24 /*!< DWT FUNCTION: MATCHED Position */ +#define DWT_FUNCTION_MATCHED_Msk (0x1UL << DWT_FUNCTION_MATCHED_Pos) /*!< DWT FUNCTION: MATCHED Mask */ -#define DWT_FUNCTION_DATAVADDR1_Pos 16 /*!< DWT FUNCTION: DATAVADDR1 Position */ -#define DWT_FUNCTION_DATAVADDR1_Msk (0xFUL << DWT_FUNCTION_DATAVADDR1_Pos) /*!< DWT FUNCTION: DATAVADDR1 Mask */ +#define DWT_FUNCTION_DATAVADDR1_Pos 16 /*!< DWT FUNCTION: DATAVADDR1 Position */ +#define DWT_FUNCTION_DATAVADDR1_Msk (0xFUL << DWT_FUNCTION_DATAVADDR1_Pos) /*!< DWT FUNCTION: DATAVADDR1 Mask */ -#define DWT_FUNCTION_DATAVADDR0_Pos 12 /*!< DWT FUNCTION: DATAVADDR0 Position */ -#define DWT_FUNCTION_DATAVADDR0_Msk (0xFUL << DWT_FUNCTION_DATAVADDR0_Pos) /*!< DWT FUNCTION: DATAVADDR0 Mask */ +#define DWT_FUNCTION_DATAVADDR0_Pos 12 /*!< DWT FUNCTION: DATAVADDR0 Position */ +#define DWT_FUNCTION_DATAVADDR0_Msk (0xFUL << DWT_FUNCTION_DATAVADDR0_Pos) /*!< DWT FUNCTION: DATAVADDR0 Mask */ -#define DWT_FUNCTION_DATAVSIZE_Pos 10 /*!< DWT FUNCTION: DATAVSIZE Position */ -#define DWT_FUNCTION_DATAVSIZE_Msk (0x3UL << DWT_FUNCTION_DATAVSIZE_Pos) /*!< DWT FUNCTION: DATAVSIZE Mask */ +#define DWT_FUNCTION_DATAVSIZE_Pos 10 /*!< DWT FUNCTION: DATAVSIZE Position */ +#define DWT_FUNCTION_DATAVSIZE_Msk (0x3UL << DWT_FUNCTION_DATAVSIZE_Pos) /*!< DWT FUNCTION: DATAVSIZE Mask */ -#define DWT_FUNCTION_LNK1ENA_Pos 9 /*!< DWT FUNCTION: LNK1ENA Position */ -#define DWT_FUNCTION_LNK1ENA_Msk (0x1UL << DWT_FUNCTION_LNK1ENA_Pos) /*!< DWT FUNCTION: LNK1ENA Mask */ +#define DWT_FUNCTION_LNK1ENA_Pos 9 /*!< DWT FUNCTION: LNK1ENA Position */ +#define DWT_FUNCTION_LNK1ENA_Msk (0x1UL << DWT_FUNCTION_LNK1ENA_Pos) /*!< DWT FUNCTION: LNK1ENA Mask */ -#define DWT_FUNCTION_DATAVMATCH_Pos 8 /*!< DWT FUNCTION: DATAVMATCH Position */ -#define DWT_FUNCTION_DATAVMATCH_Msk (0x1UL << DWT_FUNCTION_DATAVMATCH_Pos) /*!< DWT FUNCTION: DATAVMATCH Mask */ +#define DWT_FUNCTION_DATAVMATCH_Pos 8 /*!< DWT FUNCTION: DATAVMATCH Position */ +#define DWT_FUNCTION_DATAVMATCH_Msk (0x1UL << DWT_FUNCTION_DATAVMATCH_Pos) /*!< DWT FUNCTION: DATAVMATCH Mask */ -#define DWT_FUNCTION_CYCMATCH_Pos 7 /*!< DWT FUNCTION: CYCMATCH Position */ -#define DWT_FUNCTION_CYCMATCH_Msk (0x1UL << DWT_FUNCTION_CYCMATCH_Pos) /*!< DWT FUNCTION: CYCMATCH Mask */ +#define DWT_FUNCTION_CYCMATCH_Pos 7 /*!< DWT FUNCTION: CYCMATCH Position */ +#define DWT_FUNCTION_CYCMATCH_Msk (0x1UL << DWT_FUNCTION_CYCMATCH_Pos) /*!< DWT FUNCTION: CYCMATCH Mask */ -#define DWT_FUNCTION_EMITRANGE_Pos 5 /*!< DWT FUNCTION: EMITRANGE Position */ -#define DWT_FUNCTION_EMITRANGE_Msk (0x1UL << DWT_FUNCTION_EMITRANGE_Pos) /*!< DWT FUNCTION: EMITRANGE Mask */ +#define DWT_FUNCTION_EMITRANGE_Pos 5 /*!< DWT FUNCTION: EMITRANGE Position */ +#define DWT_FUNCTION_EMITRANGE_Msk (0x1UL << DWT_FUNCTION_EMITRANGE_Pos) /*!< DWT FUNCTION: EMITRANGE Mask */ -#define DWT_FUNCTION_FUNCTION_Pos 0 /*!< DWT FUNCTION: FUNCTION Position */ -#define DWT_FUNCTION_FUNCTION_Msk (0xFUL << DWT_FUNCTION_FUNCTION_Pos) /*!< DWT FUNCTION: FUNCTION Mask */ +#define DWT_FUNCTION_FUNCTION_Pos 0 /*!< DWT FUNCTION: FUNCTION Position */ +#define DWT_FUNCTION_FUNCTION_Msk (0xFUL << DWT_FUNCTION_FUNCTION_Pos) /*!< DWT FUNCTION: FUNCTION Mask */ -/*@}*/ /* end of group CMSIS_DWT */ + /*@}*/ /* end of group CMSIS_DWT */ - -/** \ingroup CMSIS_core_register + /** \ingroup CMSIS_core_register \defgroup CMSIS_TPI Trace Port Interface (TPI) \brief Type definitions for the Trace Port Interface (TPI) @{ */ -/** \brief Structure type to access the Trace Port Interface Register (TPI). + /** \brief Structure type to access the Trace Port Interface Register (TPI). */ -typedef struct -{ - __IO uint32_t SSPSR; /*!< Offset: 0x000 (R/ ) Supported Parallel Port Size Register */ - __IO uint32_t CSPSR; /*!< Offset: 0x004 (R/W) Current Parallel Port Size Register */ - uint32_t RESERVED0[2]; - __IO uint32_t ACPR; /*!< Offset: 0x010 (R/W) Asynchronous Clock Prescaler Register */ - uint32_t RESERVED1[55]; - __IO uint32_t SPPR; /*!< Offset: 0x0F0 (R/W) Selected Pin Protocol Register */ - uint32_t RESERVED2[131]; - __I uint32_t FFSR; /*!< Offset: 0x300 (R/ ) Formatter and Flush Status Register */ - __IO uint32_t FFCR; /*!< Offset: 0x304 (R/W) Formatter and Flush Control Register */ - __I uint32_t FSCR; /*!< Offset: 0x308 (R/ ) Formatter Synchronization Counter Register */ - uint32_t RESERVED3[759]; - __I uint32_t TRIGGER; /*!< Offset: 0xEE8 (R/ ) TRIGGER */ - __I uint32_t FIFO0; /*!< Offset: 0xEEC (R/ ) Integration ETM Data */ - __I uint32_t ITATBCTR2; /*!< Offset: 0xEF0 (R/ ) ITATBCTR2 */ - uint32_t RESERVED4[1]; - __I uint32_t ITATBCTR0; /*!< Offset: 0xEF8 (R/ ) ITATBCTR0 */ - __I uint32_t FIFO1; /*!< Offset: 0xEFC (R/ ) Integration ITM Data */ - __IO uint32_t ITCTRL; /*!< Offset: 0xF00 (R/W) Integration Mode Control */ - uint32_t RESERVED5[39]; - __IO uint32_t CLAIMSET; /*!< Offset: 0xFA0 (R/W) Claim tag set */ - __IO uint32_t CLAIMCLR; /*!< Offset: 0xFA4 (R/W) Claim tag clear */ - uint32_t RESERVED7[8]; - __I uint32_t DEVID; /*!< Offset: 0xFC8 (R/ ) TPIU_DEVID */ - __I uint32_t DEVTYPE; /*!< Offset: 0xFCC (R/ ) TPIU_DEVTYPE */ -} TPI_Type; + typedef struct + { + __IO uint32_t SSPSR; /*!< Offset: 0x000 (R/ ) Supported Parallel Port Size Register */ + __IO uint32_t CSPSR; /*!< Offset: 0x004 (R/W) Current Parallel Port Size Register */ + uint32_t RESERVED0[2]; + __IO uint32_t ACPR; /*!< Offset: 0x010 (R/W) Asynchronous Clock Prescaler Register */ + uint32_t RESERVED1[55]; + __IO uint32_t SPPR; /*!< Offset: 0x0F0 (R/W) Selected Pin Protocol Register */ + uint32_t RESERVED2[131]; + __I uint32_t FFSR; /*!< Offset: 0x300 (R/ ) Formatter and Flush Status Register */ + __IO uint32_t FFCR; /*!< Offset: 0x304 (R/W) Formatter and Flush Control Register */ + __I uint32_t FSCR; /*!< Offset: 0x308 (R/ ) Formatter Synchronization Counter Register */ + uint32_t RESERVED3[759]; + __I uint32_t TRIGGER; /*!< Offset: 0xEE8 (R/ ) TRIGGER */ + __I uint32_t FIFO0; /*!< Offset: 0xEEC (R/ ) Integration ETM Data */ + __I uint32_t ITATBCTR2; /*!< Offset: 0xEF0 (R/ ) ITATBCTR2 */ + uint32_t RESERVED4[1]; + __I uint32_t ITATBCTR0; /*!< Offset: 0xEF8 (R/ ) ITATBCTR0 */ + __I uint32_t FIFO1; /*!< Offset: 0xEFC (R/ ) Integration ITM Data */ + __IO uint32_t ITCTRL; /*!< Offset: 0xF00 (R/W) Integration Mode Control */ + uint32_t RESERVED5[39]; + __IO uint32_t CLAIMSET; /*!< Offset: 0xFA0 (R/W) Claim tag set */ + __IO uint32_t CLAIMCLR; /*!< Offset: 0xFA4 (R/W) Claim tag clear */ + uint32_t RESERVED7[8]; + __I uint32_t DEVID; /*!< Offset: 0xFC8 (R/ ) TPIU_DEVID */ + __I uint32_t DEVTYPE; /*!< Offset: 0xFCC (R/ ) TPIU_DEVTYPE */ + } TPI_Type; /* TPI Asynchronous Clock Prescaler Register Definitions */ -#define TPI_ACPR_PRESCALER_Pos 0 /*!< TPI ACPR: PRESCALER Position */ -#define TPI_ACPR_PRESCALER_Msk (0x1FFFUL << TPI_ACPR_PRESCALER_Pos) /*!< TPI ACPR: PRESCALER Mask */ +#define TPI_ACPR_PRESCALER_Pos 0 /*!< TPI ACPR: PRESCALER Position */ +#define TPI_ACPR_PRESCALER_Msk (0x1FFFUL << TPI_ACPR_PRESCALER_Pos) /*!< TPI ACPR: PRESCALER Mask */ /* TPI Selected Pin Protocol Register Definitions */ -#define TPI_SPPR_TXMODE_Pos 0 /*!< TPI SPPR: TXMODE Position */ -#define TPI_SPPR_TXMODE_Msk (0x3UL << TPI_SPPR_TXMODE_Pos) /*!< TPI SPPR: TXMODE Mask */ +#define TPI_SPPR_TXMODE_Pos 0 /*!< TPI SPPR: TXMODE Position */ +#define TPI_SPPR_TXMODE_Msk (0x3UL << TPI_SPPR_TXMODE_Pos) /*!< TPI SPPR: TXMODE Mask */ /* TPI Formatter and Flush Status Register Definitions */ -#define TPI_FFSR_FtNonStop_Pos 3 /*!< TPI FFSR: FtNonStop Position */ -#define TPI_FFSR_FtNonStop_Msk (0x1UL << TPI_FFSR_FtNonStop_Pos) /*!< TPI FFSR: FtNonStop Mask */ +#define TPI_FFSR_FtNonStop_Pos 3 /*!< TPI FFSR: FtNonStop Position */ +#define TPI_FFSR_FtNonStop_Msk (0x1UL << TPI_FFSR_FtNonStop_Pos) /*!< TPI FFSR: FtNonStop Mask */ -#define TPI_FFSR_TCPresent_Pos 2 /*!< TPI FFSR: TCPresent Position */ -#define TPI_FFSR_TCPresent_Msk (0x1UL << TPI_FFSR_TCPresent_Pos) /*!< TPI FFSR: TCPresent Mask */ +#define TPI_FFSR_TCPresent_Pos 2 /*!< TPI FFSR: TCPresent Position */ +#define TPI_FFSR_TCPresent_Msk (0x1UL << TPI_FFSR_TCPresent_Pos) /*!< TPI FFSR: TCPresent Mask */ -#define TPI_FFSR_FtStopped_Pos 1 /*!< TPI FFSR: FtStopped Position */ -#define TPI_FFSR_FtStopped_Msk (0x1UL << TPI_FFSR_FtStopped_Pos) /*!< TPI FFSR: FtStopped Mask */ +#define TPI_FFSR_FtStopped_Pos 1 /*!< TPI FFSR: FtStopped Position */ +#define TPI_FFSR_FtStopped_Msk (0x1UL << TPI_FFSR_FtStopped_Pos) /*!< TPI FFSR: FtStopped Mask */ -#define TPI_FFSR_FlInProg_Pos 0 /*!< TPI FFSR: FlInProg Position */ -#define TPI_FFSR_FlInProg_Msk (0x1UL << TPI_FFSR_FlInProg_Pos) /*!< TPI FFSR: FlInProg Mask */ +#define TPI_FFSR_FlInProg_Pos 0 /*!< TPI FFSR: FlInProg Position */ +#define TPI_FFSR_FlInProg_Msk (0x1UL << TPI_FFSR_FlInProg_Pos) /*!< TPI FFSR: FlInProg Mask */ /* TPI Formatter and Flush Control Register Definitions */ -#define TPI_FFCR_TrigIn_Pos 8 /*!< TPI FFCR: TrigIn Position */ -#define TPI_FFCR_TrigIn_Msk (0x1UL << TPI_FFCR_TrigIn_Pos) /*!< TPI FFCR: TrigIn Mask */ +#define TPI_FFCR_TrigIn_Pos 8 /*!< TPI FFCR: TrigIn Position */ +#define TPI_FFCR_TrigIn_Msk (0x1UL << TPI_FFCR_TrigIn_Pos) /*!< TPI FFCR: TrigIn Mask */ -#define TPI_FFCR_EnFCont_Pos 1 /*!< TPI FFCR: EnFCont Position */ -#define TPI_FFCR_EnFCont_Msk (0x1UL << TPI_FFCR_EnFCont_Pos) /*!< TPI FFCR: EnFCont Mask */ +#define TPI_FFCR_EnFCont_Pos 1 /*!< TPI FFCR: EnFCont Position */ +#define TPI_FFCR_EnFCont_Msk (0x1UL << TPI_FFCR_EnFCont_Pos) /*!< TPI FFCR: EnFCont Mask */ /* TPI TRIGGER Register Definitions */ -#define TPI_TRIGGER_TRIGGER_Pos 0 /*!< TPI TRIGGER: TRIGGER Position */ -#define TPI_TRIGGER_TRIGGER_Msk (0x1UL << TPI_TRIGGER_TRIGGER_Pos) /*!< TPI TRIGGER: TRIGGER Mask */ +#define TPI_TRIGGER_TRIGGER_Pos 0 /*!< TPI TRIGGER: TRIGGER Position */ +#define TPI_TRIGGER_TRIGGER_Msk (0x1UL << TPI_TRIGGER_TRIGGER_Pos) /*!< TPI TRIGGER: TRIGGER Mask */ /* TPI Integration ETM Data Register Definitions (FIFO0) */ -#define TPI_FIFO0_ITM_ATVALID_Pos 29 /*!< TPI FIFO0: ITM_ATVALID Position */ -#define TPI_FIFO0_ITM_ATVALID_Msk (0x3UL << TPI_FIFO0_ITM_ATVALID_Pos) /*!< TPI FIFO0: ITM_ATVALID Mask */ +#define TPI_FIFO0_ITM_ATVALID_Pos 29 /*!< TPI FIFO0: ITM_ATVALID Position */ +#define TPI_FIFO0_ITM_ATVALID_Msk (0x3UL << TPI_FIFO0_ITM_ATVALID_Pos) /*!< TPI FIFO0: ITM_ATVALID Mask */ -#define TPI_FIFO0_ITM_bytecount_Pos 27 /*!< TPI FIFO0: ITM_bytecount Position */ -#define TPI_FIFO0_ITM_bytecount_Msk (0x3UL << TPI_FIFO0_ITM_bytecount_Pos) /*!< TPI FIFO0: ITM_bytecount Mask */ +#define TPI_FIFO0_ITM_bytecount_Pos 27 /*!< TPI FIFO0: ITM_bytecount Position */ +#define TPI_FIFO0_ITM_bytecount_Msk (0x3UL << TPI_FIFO0_ITM_bytecount_Pos) /*!< TPI FIFO0: ITM_bytecount Mask */ -#define TPI_FIFO0_ETM_ATVALID_Pos 26 /*!< TPI FIFO0: ETM_ATVALID Position */ -#define TPI_FIFO0_ETM_ATVALID_Msk (0x3UL << TPI_FIFO0_ETM_ATVALID_Pos) /*!< TPI FIFO0: ETM_ATVALID Mask */ +#define TPI_FIFO0_ETM_ATVALID_Pos 26 /*!< TPI FIFO0: ETM_ATVALID Position */ +#define TPI_FIFO0_ETM_ATVALID_Msk (0x3UL << TPI_FIFO0_ETM_ATVALID_Pos) /*!< TPI FIFO0: ETM_ATVALID Mask */ -#define TPI_FIFO0_ETM_bytecount_Pos 24 /*!< TPI FIFO0: ETM_bytecount Position */ -#define TPI_FIFO0_ETM_bytecount_Msk (0x3UL << TPI_FIFO0_ETM_bytecount_Pos) /*!< TPI FIFO0: ETM_bytecount Mask */ +#define TPI_FIFO0_ETM_bytecount_Pos 24 /*!< TPI FIFO0: ETM_bytecount Position */ +#define TPI_FIFO0_ETM_bytecount_Msk (0x3UL << TPI_FIFO0_ETM_bytecount_Pos) /*!< TPI FIFO0: ETM_bytecount Mask */ -#define TPI_FIFO0_ETM2_Pos 16 /*!< TPI FIFO0: ETM2 Position */ -#define TPI_FIFO0_ETM2_Msk (0xFFUL << TPI_FIFO0_ETM2_Pos) /*!< TPI FIFO0: ETM2 Mask */ +#define TPI_FIFO0_ETM2_Pos 16 /*!< TPI FIFO0: ETM2 Position */ +#define TPI_FIFO0_ETM2_Msk (0xFFUL << TPI_FIFO0_ETM2_Pos) /*!< TPI FIFO0: ETM2 Mask */ -#define TPI_FIFO0_ETM1_Pos 8 /*!< TPI FIFO0: ETM1 Position */ -#define TPI_FIFO0_ETM1_Msk (0xFFUL << TPI_FIFO0_ETM1_Pos) /*!< TPI FIFO0: ETM1 Mask */ +#define TPI_FIFO0_ETM1_Pos 8 /*!< TPI FIFO0: ETM1 Position */ +#define TPI_FIFO0_ETM1_Msk (0xFFUL << TPI_FIFO0_ETM1_Pos) /*!< TPI FIFO0: ETM1 Mask */ -#define TPI_FIFO0_ETM0_Pos 0 /*!< TPI FIFO0: ETM0 Position */ -#define TPI_FIFO0_ETM0_Msk (0xFFUL << TPI_FIFO0_ETM0_Pos) /*!< TPI FIFO0: ETM0 Mask */ +#define TPI_FIFO0_ETM0_Pos 0 /*!< TPI FIFO0: ETM0 Position */ +#define TPI_FIFO0_ETM0_Msk (0xFFUL << TPI_FIFO0_ETM0_Pos) /*!< TPI FIFO0: ETM0 Mask */ /* TPI ITATBCTR2 Register Definitions */ -#define TPI_ITATBCTR2_ATREADY_Pos 0 /*!< TPI ITATBCTR2: ATREADY Position */ -#define TPI_ITATBCTR2_ATREADY_Msk (0x1UL << TPI_ITATBCTR2_ATREADY_Pos) /*!< TPI ITATBCTR2: ATREADY Mask */ +#define TPI_ITATBCTR2_ATREADY_Pos 0 /*!< TPI ITATBCTR2: ATREADY Position */ +#define TPI_ITATBCTR2_ATREADY_Msk (0x1UL << TPI_ITATBCTR2_ATREADY_Pos) /*!< TPI ITATBCTR2: ATREADY Mask */ /* TPI Integration ITM Data Register Definitions (FIFO1) */ -#define TPI_FIFO1_ITM_ATVALID_Pos 29 /*!< TPI FIFO1: ITM_ATVALID Position */ -#define TPI_FIFO1_ITM_ATVALID_Msk (0x3UL << TPI_FIFO1_ITM_ATVALID_Pos) /*!< TPI FIFO1: ITM_ATVALID Mask */ +#define TPI_FIFO1_ITM_ATVALID_Pos 29 /*!< TPI FIFO1: ITM_ATVALID Position */ +#define TPI_FIFO1_ITM_ATVALID_Msk (0x3UL << TPI_FIFO1_ITM_ATVALID_Pos) /*!< TPI FIFO1: ITM_ATVALID Mask */ -#define TPI_FIFO1_ITM_bytecount_Pos 27 /*!< TPI FIFO1: ITM_bytecount Position */ -#define TPI_FIFO1_ITM_bytecount_Msk (0x3UL << TPI_FIFO1_ITM_bytecount_Pos) /*!< TPI FIFO1: ITM_bytecount Mask */ +#define TPI_FIFO1_ITM_bytecount_Pos 27 /*!< TPI FIFO1: ITM_bytecount Position */ +#define TPI_FIFO1_ITM_bytecount_Msk (0x3UL << TPI_FIFO1_ITM_bytecount_Pos) /*!< TPI FIFO1: ITM_bytecount Mask */ -#define TPI_FIFO1_ETM_ATVALID_Pos 26 /*!< TPI FIFO1: ETM_ATVALID Position */ -#define TPI_FIFO1_ETM_ATVALID_Msk (0x3UL << TPI_FIFO1_ETM_ATVALID_Pos) /*!< TPI FIFO1: ETM_ATVALID Mask */ +#define TPI_FIFO1_ETM_ATVALID_Pos 26 /*!< TPI FIFO1: ETM_ATVALID Position */ +#define TPI_FIFO1_ETM_ATVALID_Msk (0x3UL << TPI_FIFO1_ETM_ATVALID_Pos) /*!< TPI FIFO1: ETM_ATVALID Mask */ -#define TPI_FIFO1_ETM_bytecount_Pos 24 /*!< TPI FIFO1: ETM_bytecount Position */ -#define TPI_FIFO1_ETM_bytecount_Msk (0x3UL << TPI_FIFO1_ETM_bytecount_Pos) /*!< TPI FIFO1: ETM_bytecount Mask */ +#define TPI_FIFO1_ETM_bytecount_Pos 24 /*!< TPI FIFO1: ETM_bytecount Position */ +#define TPI_FIFO1_ETM_bytecount_Msk (0x3UL << TPI_FIFO1_ETM_bytecount_Pos) /*!< TPI FIFO1: ETM_bytecount Mask */ -#define TPI_FIFO1_ITM2_Pos 16 /*!< TPI FIFO1: ITM2 Position */ -#define TPI_FIFO1_ITM2_Msk (0xFFUL << TPI_FIFO1_ITM2_Pos) /*!< TPI FIFO1: ITM2 Mask */ +#define TPI_FIFO1_ITM2_Pos 16 /*!< TPI FIFO1: ITM2 Position */ +#define TPI_FIFO1_ITM2_Msk (0xFFUL << TPI_FIFO1_ITM2_Pos) /*!< TPI FIFO1: ITM2 Mask */ -#define TPI_FIFO1_ITM1_Pos 8 /*!< TPI FIFO1: ITM1 Position */ -#define TPI_FIFO1_ITM1_Msk (0xFFUL << TPI_FIFO1_ITM1_Pos) /*!< TPI FIFO1: ITM1 Mask */ +#define TPI_FIFO1_ITM1_Pos 8 /*!< TPI FIFO1: ITM1 Position */ +#define TPI_FIFO1_ITM1_Msk (0xFFUL << TPI_FIFO1_ITM1_Pos) /*!< TPI FIFO1: ITM1 Mask */ -#define TPI_FIFO1_ITM0_Pos 0 /*!< TPI FIFO1: ITM0 Position */ -#define TPI_FIFO1_ITM0_Msk (0xFFUL << TPI_FIFO1_ITM0_Pos) /*!< TPI FIFO1: ITM0 Mask */ +#define TPI_FIFO1_ITM0_Pos 0 /*!< TPI FIFO1: ITM0 Position */ +#define TPI_FIFO1_ITM0_Msk (0xFFUL << TPI_FIFO1_ITM0_Pos) /*!< TPI FIFO1: ITM0 Mask */ /* TPI ITATBCTR0 Register Definitions */ -#define TPI_ITATBCTR0_ATREADY_Pos 0 /*!< TPI ITATBCTR0: ATREADY Position */ -#define TPI_ITATBCTR0_ATREADY_Msk (0x1UL << TPI_ITATBCTR0_ATREADY_Pos) /*!< TPI ITATBCTR0: ATREADY Mask */ +#define TPI_ITATBCTR0_ATREADY_Pos 0 /*!< TPI ITATBCTR0: ATREADY Position */ +#define TPI_ITATBCTR0_ATREADY_Msk (0x1UL << TPI_ITATBCTR0_ATREADY_Pos) /*!< TPI ITATBCTR0: ATREADY Mask */ /* TPI Integration Mode Control Register Definitions */ -#define TPI_ITCTRL_Mode_Pos 0 /*!< TPI ITCTRL: Mode Position */ -#define TPI_ITCTRL_Mode_Msk (0x1UL << TPI_ITCTRL_Mode_Pos) /*!< TPI ITCTRL: Mode Mask */ +#define TPI_ITCTRL_Mode_Pos 0 /*!< TPI ITCTRL: Mode Position */ +#define TPI_ITCTRL_Mode_Msk (0x1UL << TPI_ITCTRL_Mode_Pos) /*!< TPI ITCTRL: Mode Mask */ /* TPI DEVID Register Definitions */ -#define TPI_DEVID_NRZVALID_Pos 11 /*!< TPI DEVID: NRZVALID Position */ -#define TPI_DEVID_NRZVALID_Msk (0x1UL << TPI_DEVID_NRZVALID_Pos) /*!< TPI DEVID: NRZVALID Mask */ +#define TPI_DEVID_NRZVALID_Pos 11 /*!< TPI DEVID: NRZVALID Position */ +#define TPI_DEVID_NRZVALID_Msk (0x1UL << TPI_DEVID_NRZVALID_Pos) /*!< TPI DEVID: NRZVALID Mask */ -#define TPI_DEVID_MANCVALID_Pos 10 /*!< TPI DEVID: MANCVALID Position */ -#define TPI_DEVID_MANCVALID_Msk (0x1UL << TPI_DEVID_MANCVALID_Pos) /*!< TPI DEVID: MANCVALID Mask */ +#define TPI_DEVID_MANCVALID_Pos 10 /*!< TPI DEVID: MANCVALID Position */ +#define TPI_DEVID_MANCVALID_Msk (0x1UL << TPI_DEVID_MANCVALID_Pos) /*!< TPI DEVID: MANCVALID Mask */ -#define TPI_DEVID_PTINVALID_Pos 9 /*!< TPI DEVID: PTINVALID Position */ -#define TPI_DEVID_PTINVALID_Msk (0x1UL << TPI_DEVID_PTINVALID_Pos) /*!< TPI DEVID: PTINVALID Mask */ +#define TPI_DEVID_PTINVALID_Pos 9 /*!< TPI DEVID: PTINVALID Position */ +#define TPI_DEVID_PTINVALID_Msk (0x1UL << TPI_DEVID_PTINVALID_Pos) /*!< TPI DEVID: PTINVALID Mask */ -#define TPI_DEVID_MinBufSz_Pos 6 /*!< TPI DEVID: MinBufSz Position */ -#define TPI_DEVID_MinBufSz_Msk (0x7UL << TPI_DEVID_MinBufSz_Pos) /*!< TPI DEVID: MinBufSz Mask */ +#define TPI_DEVID_MinBufSz_Pos 6 /*!< TPI DEVID: MinBufSz Position */ +#define TPI_DEVID_MinBufSz_Msk (0x7UL << TPI_DEVID_MinBufSz_Pos) /*!< TPI DEVID: MinBufSz Mask */ -#define TPI_DEVID_AsynClkIn_Pos 5 /*!< TPI DEVID: AsynClkIn Position */ -#define TPI_DEVID_AsynClkIn_Msk (0x1UL << TPI_DEVID_AsynClkIn_Pos) /*!< TPI DEVID: AsynClkIn Mask */ +#define TPI_DEVID_AsynClkIn_Pos 5 /*!< TPI DEVID: AsynClkIn Position */ +#define TPI_DEVID_AsynClkIn_Msk (0x1UL << TPI_DEVID_AsynClkIn_Pos) /*!< TPI DEVID: AsynClkIn Mask */ -#define TPI_DEVID_NrTraceInput_Pos 0 /*!< TPI DEVID: NrTraceInput Position */ -#define TPI_DEVID_NrTraceInput_Msk (0x1FUL << TPI_DEVID_NrTraceInput_Pos) /*!< TPI DEVID: NrTraceInput Mask */ +#define TPI_DEVID_NrTraceInput_Pos 0 /*!< TPI DEVID: NrTraceInput Position */ +#define TPI_DEVID_NrTraceInput_Msk (0x1FUL << TPI_DEVID_NrTraceInput_Pos) /*!< TPI DEVID: NrTraceInput Mask */ /* TPI DEVTYPE Register Definitions */ -#define TPI_DEVTYPE_SubType_Pos 0 /*!< TPI DEVTYPE: SubType Position */ -#define TPI_DEVTYPE_SubType_Msk (0xFUL << TPI_DEVTYPE_SubType_Pos) /*!< TPI DEVTYPE: SubType Mask */ - -#define TPI_DEVTYPE_MajorType_Pos 4 /*!< TPI DEVTYPE: MajorType Position */ -#define TPI_DEVTYPE_MajorType_Msk (0xFUL << TPI_DEVTYPE_MajorType_Pos) /*!< TPI DEVTYPE: MajorType Mask */ +#define TPI_DEVTYPE_SubType_Pos 0 /*!< TPI DEVTYPE: SubType Position */ +#define TPI_DEVTYPE_SubType_Msk (0xFUL << TPI_DEVTYPE_SubType_Pos) /*!< TPI DEVTYPE: SubType Mask */ -/*@}*/ /* end of group CMSIS_TPI */ +#define TPI_DEVTYPE_MajorType_Pos 4 /*!< TPI DEVTYPE: MajorType Position */ +#define TPI_DEVTYPE_MajorType_Msk (0xFUL << TPI_DEVTYPE_MajorType_Pos) /*!< TPI DEVTYPE: MajorType Mask */ + /*@}*/ /* end of group CMSIS_TPI */ #if (__MPU_PRESENT == 1) -/** \ingroup CMSIS_core_register + /** \ingroup CMSIS_core_register \defgroup CMSIS_MPU Memory Protection Unit (MPU) \brief Type definitions for the Memory Protection Unit (MPU) @{ */ -/** \brief Structure type to access the Memory Protection Unit (MPU). + /** \brief Structure type to access the Memory Protection Unit (MPU). */ -typedef struct -{ - __I uint32_t TYPE; /*!< Offset: 0x000 (R/ ) MPU Type Register */ - __IO uint32_t CTRL; /*!< Offset: 0x004 (R/W) MPU Control Register */ - __IO uint32_t RNR; /*!< Offset: 0x008 (R/W) MPU Region RNRber Register */ - __IO uint32_t RBAR; /*!< Offset: 0x00C (R/W) MPU Region Base Address Register */ - __IO uint32_t RASR; /*!< Offset: 0x010 (R/W) MPU Region Attribute and Size Register */ - __IO uint32_t RBAR_A1; /*!< Offset: 0x014 (R/W) MPU Alias 1 Region Base Address Register */ - __IO uint32_t RASR_A1; /*!< Offset: 0x018 (R/W) MPU Alias 1 Region Attribute and Size Register */ - __IO uint32_t RBAR_A2; /*!< Offset: 0x01C (R/W) MPU Alias 2 Region Base Address Register */ - __IO uint32_t RASR_A2; /*!< Offset: 0x020 (R/W) MPU Alias 2 Region Attribute and Size Register */ - __IO uint32_t RBAR_A3; /*!< Offset: 0x024 (R/W) MPU Alias 3 Region Base Address Register */ - __IO uint32_t RASR_A3; /*!< Offset: 0x028 (R/W) MPU Alias 3 Region Attribute and Size Register */ -} MPU_Type; + typedef struct + { + __I uint32_t TYPE; /*!< Offset: 0x000 (R/ ) MPU Type Register */ + __IO uint32_t CTRL; /*!< Offset: 0x004 (R/W) MPU Control Register */ + __IO uint32_t RNR; /*!< Offset: 0x008 (R/W) MPU Region RNRber Register */ + __IO uint32_t RBAR; /*!< Offset: 0x00C (R/W) MPU Region Base Address Register */ + __IO uint32_t RASR; /*!< Offset: 0x010 (R/W) MPU Region Attribute and Size Register */ + __IO uint32_t RBAR_A1; /*!< Offset: 0x014 (R/W) MPU Alias 1 Region Base Address Register */ + __IO uint32_t RASR_A1; /*!< Offset: 0x018 (R/W) MPU Alias 1 Region Attribute and Size Register */ + __IO uint32_t RBAR_A2; /*!< Offset: 0x01C (R/W) MPU Alias 2 Region Base Address Register */ + __IO uint32_t RASR_A2; /*!< Offset: 0x020 (R/W) MPU Alias 2 Region Attribute and Size Register */ + __IO uint32_t RBAR_A3; /*!< Offset: 0x024 (R/W) MPU Alias 3 Region Base Address Register */ + __IO uint32_t RASR_A3; /*!< Offset: 0x028 (R/W) MPU Alias 3 Region Attribute and Size Register */ + } MPU_Type; /* MPU Type Register */ -#define MPU_TYPE_IREGION_Pos 16 /*!< MPU TYPE: IREGION Position */ -#define MPU_TYPE_IREGION_Msk (0xFFUL << MPU_TYPE_IREGION_Pos) /*!< MPU TYPE: IREGION Mask */ +#define MPU_TYPE_IREGION_Pos 16 /*!< MPU TYPE: IREGION Position */ +#define MPU_TYPE_IREGION_Msk (0xFFUL << MPU_TYPE_IREGION_Pos) /*!< MPU TYPE: IREGION Mask */ -#define MPU_TYPE_DREGION_Pos 8 /*!< MPU TYPE: DREGION Position */ -#define MPU_TYPE_DREGION_Msk (0xFFUL << MPU_TYPE_DREGION_Pos) /*!< MPU TYPE: DREGION Mask */ +#define MPU_TYPE_DREGION_Pos 8 /*!< MPU TYPE: DREGION Position */ +#define MPU_TYPE_DREGION_Msk (0xFFUL << MPU_TYPE_DREGION_Pos) /*!< MPU TYPE: DREGION Mask */ -#define MPU_TYPE_SEPARATE_Pos 0 /*!< MPU TYPE: SEPARATE Position */ -#define MPU_TYPE_SEPARATE_Msk (1UL << MPU_TYPE_SEPARATE_Pos) /*!< MPU TYPE: SEPARATE Mask */ +#define MPU_TYPE_SEPARATE_Pos 0 /*!< MPU TYPE: SEPARATE Position */ +#define MPU_TYPE_SEPARATE_Msk (1UL << MPU_TYPE_SEPARATE_Pos) /*!< MPU TYPE: SEPARATE Mask */ /* MPU Control Register */ -#define MPU_CTRL_PRIVDEFENA_Pos 2 /*!< MPU CTRL: PRIVDEFENA Position */ -#define MPU_CTRL_PRIVDEFENA_Msk (1UL << MPU_CTRL_PRIVDEFENA_Pos) /*!< MPU CTRL: PRIVDEFENA Mask */ +#define MPU_CTRL_PRIVDEFENA_Pos 2 /*!< MPU CTRL: PRIVDEFENA Position */ +#define MPU_CTRL_PRIVDEFENA_Msk (1UL << MPU_CTRL_PRIVDEFENA_Pos) /*!< MPU CTRL: PRIVDEFENA Mask */ -#define MPU_CTRL_HFNMIENA_Pos 1 /*!< MPU CTRL: HFNMIENA Position */ -#define MPU_CTRL_HFNMIENA_Msk (1UL << MPU_CTRL_HFNMIENA_Pos) /*!< MPU CTRL: HFNMIENA Mask */ +#define MPU_CTRL_HFNMIENA_Pos 1 /*!< MPU CTRL: HFNMIENA Position */ +#define MPU_CTRL_HFNMIENA_Msk (1UL << MPU_CTRL_HFNMIENA_Pos) /*!< MPU CTRL: HFNMIENA Mask */ -#define MPU_CTRL_ENABLE_Pos 0 /*!< MPU CTRL: ENABLE Position */ -#define MPU_CTRL_ENABLE_Msk (1UL << MPU_CTRL_ENABLE_Pos) /*!< MPU CTRL: ENABLE Mask */ +#define MPU_CTRL_ENABLE_Pos 0 /*!< MPU CTRL: ENABLE Position */ +#define MPU_CTRL_ENABLE_Msk (1UL << MPU_CTRL_ENABLE_Pos) /*!< MPU CTRL: ENABLE Mask */ /* MPU Region Number Register */ -#define MPU_RNR_REGION_Pos 0 /*!< MPU RNR: REGION Position */ -#define MPU_RNR_REGION_Msk (0xFFUL << MPU_RNR_REGION_Pos) /*!< MPU RNR: REGION Mask */ +#define MPU_RNR_REGION_Pos 0 /*!< MPU RNR: REGION Position */ +#define MPU_RNR_REGION_Msk (0xFFUL << MPU_RNR_REGION_Pos) /*!< MPU RNR: REGION Mask */ /* MPU Region Base Address Register */ -#define MPU_RBAR_ADDR_Pos 5 /*!< MPU RBAR: ADDR Position */ -#define MPU_RBAR_ADDR_Msk (0x7FFFFFFUL << MPU_RBAR_ADDR_Pos) /*!< MPU RBAR: ADDR Mask */ +#define MPU_RBAR_ADDR_Pos 5 /*!< MPU RBAR: ADDR Position */ +#define MPU_RBAR_ADDR_Msk (0x7FFFFFFUL << MPU_RBAR_ADDR_Pos) /*!< MPU RBAR: ADDR Mask */ -#define MPU_RBAR_VALID_Pos 4 /*!< MPU RBAR: VALID Position */ -#define MPU_RBAR_VALID_Msk (1UL << MPU_RBAR_VALID_Pos) /*!< MPU RBAR: VALID Mask */ +#define MPU_RBAR_VALID_Pos 4 /*!< MPU RBAR: VALID Position */ +#define MPU_RBAR_VALID_Msk (1UL << MPU_RBAR_VALID_Pos) /*!< MPU RBAR: VALID Mask */ -#define MPU_RBAR_REGION_Pos 0 /*!< MPU RBAR: REGION Position */ -#define MPU_RBAR_REGION_Msk (0xFUL << MPU_RBAR_REGION_Pos) /*!< MPU RBAR: REGION Mask */ +#define MPU_RBAR_REGION_Pos 0 /*!< MPU RBAR: REGION Position */ +#define MPU_RBAR_REGION_Msk (0xFUL << MPU_RBAR_REGION_Pos) /*!< MPU RBAR: REGION Mask */ /* MPU Region Attribute and Size Register */ -#define MPU_RASR_ATTRS_Pos 16 /*!< MPU RASR: MPU Region Attribute field Position */ -#define MPU_RASR_ATTRS_Msk (0xFFFFUL << MPU_RASR_ATTRS_Pos) /*!< MPU RASR: MPU Region Attribute field Mask */ +#define MPU_RASR_ATTRS_Pos 16 /*!< MPU RASR: MPU Region Attribute field Position */ +#define MPU_RASR_ATTRS_Msk (0xFFFFUL << MPU_RASR_ATTRS_Pos) /*!< MPU RASR: MPU Region Attribute field Mask */ -#define MPU_RASR_XN_Pos 28 /*!< MPU RASR: ATTRS.XN Position */ -#define MPU_RASR_XN_Msk (1UL << MPU_RASR_XN_Pos) /*!< MPU RASR: ATTRS.XN Mask */ +#define MPU_RASR_XN_Pos 28 /*!< MPU RASR: ATTRS.XN Position */ +#define MPU_RASR_XN_Msk (1UL << MPU_RASR_XN_Pos) /*!< MPU RASR: ATTRS.XN Mask */ -#define MPU_RASR_AP_Pos 24 /*!< MPU RASR: ATTRS.AP Position */ -#define MPU_RASR_AP_Msk (0x7UL << MPU_RASR_AP_Pos) /*!< MPU RASR: ATTRS.AP Mask */ +#define MPU_RASR_AP_Pos 24 /*!< MPU RASR: ATTRS.AP Position */ +#define MPU_RASR_AP_Msk (0x7UL << MPU_RASR_AP_Pos) /*!< MPU RASR: ATTRS.AP Mask */ -#define MPU_RASR_TEX_Pos 19 /*!< MPU RASR: ATTRS.TEX Position */ -#define MPU_RASR_TEX_Msk (0x7UL << MPU_RASR_TEX_Pos) /*!< MPU RASR: ATTRS.TEX Mask */ +#define MPU_RASR_TEX_Pos 19 /*!< MPU RASR: ATTRS.TEX Position */ +#define MPU_RASR_TEX_Msk (0x7UL << MPU_RASR_TEX_Pos) /*!< MPU RASR: ATTRS.TEX Mask */ -#define MPU_RASR_S_Pos 18 /*!< MPU RASR: ATTRS.S Position */ -#define MPU_RASR_S_Msk (1UL << MPU_RASR_S_Pos) /*!< MPU RASR: ATTRS.S Mask */ +#define MPU_RASR_S_Pos 18 /*!< MPU RASR: ATTRS.S Position */ +#define MPU_RASR_S_Msk (1UL << MPU_RASR_S_Pos) /*!< MPU RASR: ATTRS.S Mask */ -#define MPU_RASR_C_Pos 17 /*!< MPU RASR: ATTRS.C Position */ -#define MPU_RASR_C_Msk (1UL << MPU_RASR_C_Pos) /*!< MPU RASR: ATTRS.C Mask */ +#define MPU_RASR_C_Pos 17 /*!< MPU RASR: ATTRS.C Position */ +#define MPU_RASR_C_Msk (1UL << MPU_RASR_C_Pos) /*!< MPU RASR: ATTRS.C Mask */ -#define MPU_RASR_B_Pos 16 /*!< MPU RASR: ATTRS.B Position */ -#define MPU_RASR_B_Msk (1UL << MPU_RASR_B_Pos) /*!< MPU RASR: ATTRS.B Mask */ +#define MPU_RASR_B_Pos 16 /*!< MPU RASR: ATTRS.B Position */ +#define MPU_RASR_B_Msk (1UL << MPU_RASR_B_Pos) /*!< MPU RASR: ATTRS.B Mask */ -#define MPU_RASR_SRD_Pos 8 /*!< MPU RASR: Sub-Region Disable Position */ -#define MPU_RASR_SRD_Msk (0xFFUL << MPU_RASR_SRD_Pos) /*!< MPU RASR: Sub-Region Disable Mask */ +#define MPU_RASR_SRD_Pos 8 /*!< MPU RASR: Sub-Region Disable Position */ +#define MPU_RASR_SRD_Msk (0xFFUL << MPU_RASR_SRD_Pos) /*!< MPU RASR: Sub-Region Disable Mask */ -#define MPU_RASR_SIZE_Pos 1 /*!< MPU RASR: Region Size Field Position */ -#define MPU_RASR_SIZE_Msk (0x1FUL << MPU_RASR_SIZE_Pos) /*!< MPU RASR: Region Size Field Mask */ +#define MPU_RASR_SIZE_Pos 1 /*!< MPU RASR: Region Size Field Position */ +#define MPU_RASR_SIZE_Msk (0x1FUL << MPU_RASR_SIZE_Pos) /*!< MPU RASR: Region Size Field Mask */ -#define MPU_RASR_ENABLE_Pos 0 /*!< MPU RASR: Region enable bit Position */ -#define MPU_RASR_ENABLE_Msk (1UL << MPU_RASR_ENABLE_Pos) /*!< MPU RASR: Region enable bit Disable Mask */ +#define MPU_RASR_ENABLE_Pos 0 /*!< MPU RASR: Region enable bit Position */ +#define MPU_RASR_ENABLE_Msk (1UL << MPU_RASR_ENABLE_Pos) /*!< MPU RASR: Region enable bit Disable Mask */ /*@} end of group CMSIS_MPU */ #endif - #if (__FPU_PRESENT == 1) -/** \ingroup CMSIS_core_register + /** \ingroup CMSIS_core_register \defgroup CMSIS_FPU Floating Point Unit (FPU) \brief Type definitions for the Floating Point Unit (FPU) @{ */ -/** \brief Structure type to access the Floating Point Unit (FPU). + /** \brief Structure type to access the Floating Point Unit (FPU). */ -typedef struct -{ - uint32_t RESERVED0[1]; - __IO uint32_t FPCCR; /*!< Offset: 0x004 (R/W) Floating-Point Context Control Register */ - __IO uint32_t FPCAR; /*!< Offset: 0x008 (R/W) Floating-Point Context Address Register */ - __IO uint32_t FPDSCR; /*!< Offset: 0x00C (R/W) Floating-Point Default Status Control Register */ - __I uint32_t MVFR0; /*!< Offset: 0x010 (R/ ) Media and FP Feature Register 0 */ - __I uint32_t MVFR1; /*!< Offset: 0x014 (R/ ) Media and FP Feature Register 1 */ - __I uint32_t MVFR2; /*!< Offset: 0x018 (R/ ) Media and FP Feature Register 2 */ -} FPU_Type; + typedef struct + { + uint32_t RESERVED0[1]; + __IO uint32_t FPCCR; /*!< Offset: 0x004 (R/W) Floating-Point Context Control Register */ + __IO uint32_t FPCAR; /*!< Offset: 0x008 (R/W) Floating-Point Context Address Register */ + __IO uint32_t FPDSCR; /*!< Offset: 0x00C (R/W) Floating-Point Default Status Control Register */ + __I uint32_t MVFR0; /*!< Offset: 0x010 (R/ ) Media and FP Feature Register 0 */ + __I uint32_t MVFR1; /*!< Offset: 0x014 (R/ ) Media and FP Feature Register 1 */ + __I uint32_t MVFR2; /*!< Offset: 0x018 (R/ ) Media and FP Feature Register 2 */ + } FPU_Type; /* Floating-Point Context Control Register */ -#define FPU_FPCCR_ASPEN_Pos 31 /*!< FPCCR: ASPEN bit Position */ -#define FPU_FPCCR_ASPEN_Msk (1UL << FPU_FPCCR_ASPEN_Pos) /*!< FPCCR: ASPEN bit Mask */ +#define FPU_FPCCR_ASPEN_Pos 31 /*!< FPCCR: ASPEN bit Position */ +#define FPU_FPCCR_ASPEN_Msk (1UL << FPU_FPCCR_ASPEN_Pos) /*!< FPCCR: ASPEN bit Mask */ -#define FPU_FPCCR_LSPEN_Pos 30 /*!< FPCCR: LSPEN Position */ -#define FPU_FPCCR_LSPEN_Msk (1UL << FPU_FPCCR_LSPEN_Pos) /*!< FPCCR: LSPEN bit Mask */ +#define FPU_FPCCR_LSPEN_Pos 30 /*!< FPCCR: LSPEN Position */ +#define FPU_FPCCR_LSPEN_Msk (1UL << FPU_FPCCR_LSPEN_Pos) /*!< FPCCR: LSPEN bit Mask */ -#define FPU_FPCCR_MONRDY_Pos 8 /*!< FPCCR: MONRDY Position */ -#define FPU_FPCCR_MONRDY_Msk (1UL << FPU_FPCCR_MONRDY_Pos) /*!< FPCCR: MONRDY bit Mask */ +#define FPU_FPCCR_MONRDY_Pos 8 /*!< FPCCR: MONRDY Position */ +#define FPU_FPCCR_MONRDY_Msk (1UL << FPU_FPCCR_MONRDY_Pos) /*!< FPCCR: MONRDY bit Mask */ -#define FPU_FPCCR_BFRDY_Pos 6 /*!< FPCCR: BFRDY Position */ -#define FPU_FPCCR_BFRDY_Msk (1UL << FPU_FPCCR_BFRDY_Pos) /*!< FPCCR: BFRDY bit Mask */ +#define FPU_FPCCR_BFRDY_Pos 6 /*!< FPCCR: BFRDY Position */ +#define FPU_FPCCR_BFRDY_Msk (1UL << FPU_FPCCR_BFRDY_Pos) /*!< FPCCR: BFRDY bit Mask */ -#define FPU_FPCCR_MMRDY_Pos 5 /*!< FPCCR: MMRDY Position */ -#define FPU_FPCCR_MMRDY_Msk (1UL << FPU_FPCCR_MMRDY_Pos) /*!< FPCCR: MMRDY bit Mask */ +#define FPU_FPCCR_MMRDY_Pos 5 /*!< FPCCR: MMRDY Position */ +#define FPU_FPCCR_MMRDY_Msk (1UL << FPU_FPCCR_MMRDY_Pos) /*!< FPCCR: MMRDY bit Mask */ -#define FPU_FPCCR_HFRDY_Pos 4 /*!< FPCCR: HFRDY Position */ -#define FPU_FPCCR_HFRDY_Msk (1UL << FPU_FPCCR_HFRDY_Pos) /*!< FPCCR: HFRDY bit Mask */ +#define FPU_FPCCR_HFRDY_Pos 4 /*!< FPCCR: HFRDY Position */ +#define FPU_FPCCR_HFRDY_Msk (1UL << FPU_FPCCR_HFRDY_Pos) /*!< FPCCR: HFRDY bit Mask */ -#define FPU_FPCCR_THREAD_Pos 3 /*!< FPCCR: processor mode bit Position */ -#define FPU_FPCCR_THREAD_Msk (1UL << FPU_FPCCR_THREAD_Pos) /*!< FPCCR: processor mode active bit Mask */ +#define FPU_FPCCR_THREAD_Pos 3 /*!< FPCCR: processor mode bit Position */ +#define FPU_FPCCR_THREAD_Msk (1UL << FPU_FPCCR_THREAD_Pos) /*!< FPCCR: processor mode active bit Mask */ -#define FPU_FPCCR_USER_Pos 1 /*!< FPCCR: privilege level bit Position */ -#define FPU_FPCCR_USER_Msk (1UL << FPU_FPCCR_USER_Pos) /*!< FPCCR: privilege level bit Mask */ +#define FPU_FPCCR_USER_Pos 1 /*!< FPCCR: privilege level bit Position */ +#define FPU_FPCCR_USER_Msk (1UL << FPU_FPCCR_USER_Pos) /*!< FPCCR: privilege level bit Mask */ -#define FPU_FPCCR_LSPACT_Pos 0 /*!< FPCCR: Lazy state preservation active bit Position */ -#define FPU_FPCCR_LSPACT_Msk (1UL << FPU_FPCCR_LSPACT_Pos) /*!< FPCCR: Lazy state preservation active bit Mask */ +#define FPU_FPCCR_LSPACT_Pos 0 /*!< FPCCR: Lazy state preservation active bit Position */ +#define FPU_FPCCR_LSPACT_Msk (1UL << FPU_FPCCR_LSPACT_Pos) /*!< FPCCR: Lazy state preservation active bit Mask */ /* Floating-Point Context Address Register */ -#define FPU_FPCAR_ADDRESS_Pos 3 /*!< FPCAR: ADDRESS bit Position */ -#define FPU_FPCAR_ADDRESS_Msk (0x1FFFFFFFUL << FPU_FPCAR_ADDRESS_Pos) /*!< FPCAR: ADDRESS bit Mask */ +#define FPU_FPCAR_ADDRESS_Pos 3 /*!< FPCAR: ADDRESS bit Position */ +#define FPU_FPCAR_ADDRESS_Msk (0x1FFFFFFFUL << FPU_FPCAR_ADDRESS_Pos) /*!< FPCAR: ADDRESS bit Mask */ /* Floating-Point Default Status Control Register */ -#define FPU_FPDSCR_AHP_Pos 26 /*!< FPDSCR: AHP bit Position */ -#define FPU_FPDSCR_AHP_Msk (1UL << FPU_FPDSCR_AHP_Pos) /*!< FPDSCR: AHP bit Mask */ +#define FPU_FPDSCR_AHP_Pos 26 /*!< FPDSCR: AHP bit Position */ +#define FPU_FPDSCR_AHP_Msk (1UL << FPU_FPDSCR_AHP_Pos) /*!< FPDSCR: AHP bit Mask */ -#define FPU_FPDSCR_DN_Pos 25 /*!< FPDSCR: DN bit Position */ -#define FPU_FPDSCR_DN_Msk (1UL << FPU_FPDSCR_DN_Pos) /*!< FPDSCR: DN bit Mask */ +#define FPU_FPDSCR_DN_Pos 25 /*!< FPDSCR: DN bit Position */ +#define FPU_FPDSCR_DN_Msk (1UL << FPU_FPDSCR_DN_Pos) /*!< FPDSCR: DN bit Mask */ -#define FPU_FPDSCR_FZ_Pos 24 /*!< FPDSCR: FZ bit Position */ -#define FPU_FPDSCR_FZ_Msk (1UL << FPU_FPDSCR_FZ_Pos) /*!< FPDSCR: FZ bit Mask */ +#define FPU_FPDSCR_FZ_Pos 24 /*!< FPDSCR: FZ bit Position */ +#define FPU_FPDSCR_FZ_Msk (1UL << FPU_FPDSCR_FZ_Pos) /*!< FPDSCR: FZ bit Mask */ -#define FPU_FPDSCR_RMode_Pos 22 /*!< FPDSCR: RMode bit Position */ -#define FPU_FPDSCR_RMode_Msk (3UL << FPU_FPDSCR_RMode_Pos) /*!< FPDSCR: RMode bit Mask */ +#define FPU_FPDSCR_RMode_Pos 22 /*!< FPDSCR: RMode bit Position */ +#define FPU_FPDSCR_RMode_Msk (3UL << FPU_FPDSCR_RMode_Pos) /*!< FPDSCR: RMode bit Mask */ /* Media and FP Feature Register 0 */ -#define FPU_MVFR0_FP_rounding_modes_Pos 28 /*!< MVFR0: FP rounding modes bits Position */ -#define FPU_MVFR0_FP_rounding_modes_Msk (0xFUL << FPU_MVFR0_FP_rounding_modes_Pos) /*!< MVFR0: FP rounding modes bits Mask */ +#define FPU_MVFR0_FP_rounding_modes_Pos 28 /*!< MVFR0: FP rounding modes bits Position */ +#define FPU_MVFR0_FP_rounding_modes_Msk (0xFUL << FPU_MVFR0_FP_rounding_modes_Pos) /*!< MVFR0: FP rounding modes bits Mask */ -#define FPU_MVFR0_Short_vectors_Pos 24 /*!< MVFR0: Short vectors bits Position */ -#define FPU_MVFR0_Short_vectors_Msk (0xFUL << FPU_MVFR0_Short_vectors_Pos) /*!< MVFR0: Short vectors bits Mask */ +#define FPU_MVFR0_Short_vectors_Pos 24 /*!< MVFR0: Short vectors bits Position */ +#define FPU_MVFR0_Short_vectors_Msk (0xFUL << FPU_MVFR0_Short_vectors_Pos) /*!< MVFR0: Short vectors bits Mask */ -#define FPU_MVFR0_Square_root_Pos 20 /*!< MVFR0: Square root bits Position */ -#define FPU_MVFR0_Square_root_Msk (0xFUL << FPU_MVFR0_Square_root_Pos) /*!< MVFR0: Square root bits Mask */ +#define FPU_MVFR0_Square_root_Pos 20 /*!< MVFR0: Square root bits Position */ +#define FPU_MVFR0_Square_root_Msk (0xFUL << FPU_MVFR0_Square_root_Pos) /*!< MVFR0: Square root bits Mask */ -#define FPU_MVFR0_Divide_Pos 16 /*!< MVFR0: Divide bits Position */ -#define FPU_MVFR0_Divide_Msk (0xFUL << FPU_MVFR0_Divide_Pos) /*!< MVFR0: Divide bits Mask */ +#define FPU_MVFR0_Divide_Pos 16 /*!< MVFR0: Divide bits Position */ +#define FPU_MVFR0_Divide_Msk (0xFUL << FPU_MVFR0_Divide_Pos) /*!< MVFR0: Divide bits Mask */ -#define FPU_MVFR0_FP_excep_trapping_Pos 12 /*!< MVFR0: FP exception trapping bits Position */ -#define FPU_MVFR0_FP_excep_trapping_Msk (0xFUL << FPU_MVFR0_FP_excep_trapping_Pos) /*!< MVFR0: FP exception trapping bits Mask */ +#define FPU_MVFR0_FP_excep_trapping_Pos 12 /*!< MVFR0: FP exception trapping bits Position */ +#define FPU_MVFR0_FP_excep_trapping_Msk (0xFUL << FPU_MVFR0_FP_excep_trapping_Pos) /*!< MVFR0: FP exception trapping bits Mask */ -#define FPU_MVFR0_Double_precision_Pos 8 /*!< MVFR0: Double-precision bits Position */ -#define FPU_MVFR0_Double_precision_Msk (0xFUL << FPU_MVFR0_Double_precision_Pos) /*!< MVFR0: Double-precision bits Mask */ +#define FPU_MVFR0_Double_precision_Pos 8 /*!< MVFR0: Double-precision bits Position */ +#define FPU_MVFR0_Double_precision_Msk (0xFUL << FPU_MVFR0_Double_precision_Pos) /*!< MVFR0: Double-precision bits Mask */ -#define FPU_MVFR0_Single_precision_Pos 4 /*!< MVFR0: Single-precision bits Position */ -#define FPU_MVFR0_Single_precision_Msk (0xFUL << FPU_MVFR0_Single_precision_Pos) /*!< MVFR0: Single-precision bits Mask */ +#define FPU_MVFR0_Single_precision_Pos 4 /*!< MVFR0: Single-precision bits Position */ +#define FPU_MVFR0_Single_precision_Msk (0xFUL << FPU_MVFR0_Single_precision_Pos) /*!< MVFR0: Single-precision bits Mask */ -#define FPU_MVFR0_A_SIMD_registers_Pos 0 /*!< MVFR0: A_SIMD registers bits Position */ -#define FPU_MVFR0_A_SIMD_registers_Msk (0xFUL << FPU_MVFR0_A_SIMD_registers_Pos) /*!< MVFR0: A_SIMD registers bits Mask */ +#define FPU_MVFR0_A_SIMD_registers_Pos 0 /*!< MVFR0: A_SIMD registers bits Position */ +#define FPU_MVFR0_A_SIMD_registers_Msk (0xFUL << FPU_MVFR0_A_SIMD_registers_Pos) /*!< MVFR0: A_SIMD registers bits Mask */ /* Media and FP Feature Register 1 */ -#define FPU_MVFR1_FP_fused_MAC_Pos 28 /*!< MVFR1: FP fused MAC bits Position */ -#define FPU_MVFR1_FP_fused_MAC_Msk (0xFUL << FPU_MVFR1_FP_fused_MAC_Pos) /*!< MVFR1: FP fused MAC bits Mask */ +#define FPU_MVFR1_FP_fused_MAC_Pos 28 /*!< MVFR1: FP fused MAC bits Position */ +#define FPU_MVFR1_FP_fused_MAC_Msk (0xFUL << FPU_MVFR1_FP_fused_MAC_Pos) /*!< MVFR1: FP fused MAC bits Mask */ -#define FPU_MVFR1_FP_HPFP_Pos 24 /*!< MVFR1: FP HPFP bits Position */ -#define FPU_MVFR1_FP_HPFP_Msk (0xFUL << FPU_MVFR1_FP_HPFP_Pos) /*!< MVFR1: FP HPFP bits Mask */ +#define FPU_MVFR1_FP_HPFP_Pos 24 /*!< MVFR1: FP HPFP bits Position */ +#define FPU_MVFR1_FP_HPFP_Msk (0xFUL << FPU_MVFR1_FP_HPFP_Pos) /*!< MVFR1: FP HPFP bits Mask */ -#define FPU_MVFR1_D_NaN_mode_Pos 4 /*!< MVFR1: D_NaN mode bits Position */ -#define FPU_MVFR1_D_NaN_mode_Msk (0xFUL << FPU_MVFR1_D_NaN_mode_Pos) /*!< MVFR1: D_NaN mode bits Mask */ +#define FPU_MVFR1_D_NaN_mode_Pos 4 /*!< MVFR1: D_NaN mode bits Position */ +#define FPU_MVFR1_D_NaN_mode_Msk (0xFUL << FPU_MVFR1_D_NaN_mode_Pos) /*!< MVFR1: D_NaN mode bits Mask */ -#define FPU_MVFR1_FtZ_mode_Pos 0 /*!< MVFR1: FtZ mode bits Position */ -#define FPU_MVFR1_FtZ_mode_Msk (0xFUL << FPU_MVFR1_FtZ_mode_Pos) /*!< MVFR1: FtZ mode bits Mask */ +#define FPU_MVFR1_FtZ_mode_Pos 0 /*!< MVFR1: FtZ mode bits Position */ +#define FPU_MVFR1_FtZ_mode_Msk (0xFUL << FPU_MVFR1_FtZ_mode_Pos) /*!< MVFR1: FtZ mode bits Mask */ /* Media and FP Feature Register 2 */ /*@} end of group CMSIS_FPU */ #endif - -/** \ingroup CMSIS_core_register + /** \ingroup CMSIS_core_register \defgroup CMSIS_CoreDebug Core Debug Registers (CoreDebug) \brief Type definitions for the Core Debug Registers @{ */ -/** \brief Structure type to access the Core Debug Register (CoreDebug). + /** \brief Structure type to access the Core Debug Register (CoreDebug). */ -typedef struct -{ - __IO uint32_t DHCSR; /*!< Offset: 0x000 (R/W) Debug Halting Control and Status Register */ - __O uint32_t DCRSR; /*!< Offset: 0x004 ( /W) Debug Core Register Selector Register */ - __IO uint32_t DCRDR; /*!< Offset: 0x008 (R/W) Debug Core Register Data Register */ - __IO uint32_t DEMCR; /*!< Offset: 0x00C (R/W) Debug Exception and Monitor Control Register */ -} CoreDebug_Type; + typedef struct + { + __IO uint32_t DHCSR; /*!< Offset: 0x000 (R/W) Debug Halting Control and Status Register */ + __O uint32_t DCRSR; /*!< Offset: 0x004 ( /W) Debug Core Register Selector Register */ + __IO uint32_t DCRDR; /*!< Offset: 0x008 (R/W) Debug Core Register Data Register */ + __IO uint32_t DEMCR; /*!< Offset: 0x00C (R/W) Debug Exception and Monitor Control Register */ + } CoreDebug_Type; /* Debug Halting Control and Status Register */ -#define CoreDebug_DHCSR_DBGKEY_Pos 16 /*!< CoreDebug DHCSR: DBGKEY Position */ -#define CoreDebug_DHCSR_DBGKEY_Msk (0xFFFFUL << CoreDebug_DHCSR_DBGKEY_Pos) /*!< CoreDebug DHCSR: DBGKEY Mask */ +#define CoreDebug_DHCSR_DBGKEY_Pos 16 /*!< CoreDebug DHCSR: DBGKEY Position */ +#define CoreDebug_DHCSR_DBGKEY_Msk (0xFFFFUL << CoreDebug_DHCSR_DBGKEY_Pos) /*!< CoreDebug DHCSR: DBGKEY Mask */ -#define CoreDebug_DHCSR_S_RESET_ST_Pos 25 /*!< CoreDebug DHCSR: S_RESET_ST Position */ -#define CoreDebug_DHCSR_S_RESET_ST_Msk (1UL << CoreDebug_DHCSR_S_RESET_ST_Pos) /*!< CoreDebug DHCSR: S_RESET_ST Mask */ +#define CoreDebug_DHCSR_S_RESET_ST_Pos 25 /*!< CoreDebug DHCSR: S_RESET_ST Position */ +#define CoreDebug_DHCSR_S_RESET_ST_Msk (1UL << CoreDebug_DHCSR_S_RESET_ST_Pos) /*!< CoreDebug DHCSR: S_RESET_ST Mask */ -#define CoreDebug_DHCSR_S_RETIRE_ST_Pos 24 /*!< CoreDebug DHCSR: S_RETIRE_ST Position */ -#define CoreDebug_DHCSR_S_RETIRE_ST_Msk (1UL << CoreDebug_DHCSR_S_RETIRE_ST_Pos) /*!< CoreDebug DHCSR: S_RETIRE_ST Mask */ +#define CoreDebug_DHCSR_S_RETIRE_ST_Pos 24 /*!< CoreDebug DHCSR: S_RETIRE_ST Position */ +#define CoreDebug_DHCSR_S_RETIRE_ST_Msk (1UL << CoreDebug_DHCSR_S_RETIRE_ST_Pos) /*!< CoreDebug DHCSR: S_RETIRE_ST Mask */ -#define CoreDebug_DHCSR_S_LOCKUP_Pos 19 /*!< CoreDebug DHCSR: S_LOCKUP Position */ -#define CoreDebug_DHCSR_S_LOCKUP_Msk (1UL << CoreDebug_DHCSR_S_LOCKUP_Pos) /*!< CoreDebug DHCSR: S_LOCKUP Mask */ +#define CoreDebug_DHCSR_S_LOCKUP_Pos 19 /*!< CoreDebug DHCSR: S_LOCKUP Position */ +#define CoreDebug_DHCSR_S_LOCKUP_Msk (1UL << CoreDebug_DHCSR_S_LOCKUP_Pos) /*!< CoreDebug DHCSR: S_LOCKUP Mask */ -#define CoreDebug_DHCSR_S_SLEEP_Pos 18 /*!< CoreDebug DHCSR: S_SLEEP Position */ -#define CoreDebug_DHCSR_S_SLEEP_Msk (1UL << CoreDebug_DHCSR_S_SLEEP_Pos) /*!< CoreDebug DHCSR: S_SLEEP Mask */ +#define CoreDebug_DHCSR_S_SLEEP_Pos 18 /*!< CoreDebug DHCSR: S_SLEEP Position */ +#define CoreDebug_DHCSR_S_SLEEP_Msk (1UL << CoreDebug_DHCSR_S_SLEEP_Pos) /*!< CoreDebug DHCSR: S_SLEEP Mask */ -#define CoreDebug_DHCSR_S_HALT_Pos 17 /*!< CoreDebug DHCSR: S_HALT Position */ -#define CoreDebug_DHCSR_S_HALT_Msk (1UL << CoreDebug_DHCSR_S_HALT_Pos) /*!< CoreDebug DHCSR: S_HALT Mask */ +#define CoreDebug_DHCSR_S_HALT_Pos 17 /*!< CoreDebug DHCSR: S_HALT Position */ +#define CoreDebug_DHCSR_S_HALT_Msk (1UL << CoreDebug_DHCSR_S_HALT_Pos) /*!< CoreDebug DHCSR: S_HALT Mask */ -#define CoreDebug_DHCSR_S_REGRDY_Pos 16 /*!< CoreDebug DHCSR: S_REGRDY Position */ -#define CoreDebug_DHCSR_S_REGRDY_Msk (1UL << CoreDebug_DHCSR_S_REGRDY_Pos) /*!< CoreDebug DHCSR: S_REGRDY Mask */ +#define CoreDebug_DHCSR_S_REGRDY_Pos 16 /*!< CoreDebug DHCSR: S_REGRDY Position */ +#define CoreDebug_DHCSR_S_REGRDY_Msk (1UL << CoreDebug_DHCSR_S_REGRDY_Pos) /*!< CoreDebug DHCSR: S_REGRDY Mask */ -#define CoreDebug_DHCSR_C_SNAPSTALL_Pos 5 /*!< CoreDebug DHCSR: C_SNAPSTALL Position */ -#define CoreDebug_DHCSR_C_SNAPSTALL_Msk (1UL << CoreDebug_DHCSR_C_SNAPSTALL_Pos) /*!< CoreDebug DHCSR: C_SNAPSTALL Mask */ +#define CoreDebug_DHCSR_C_SNAPSTALL_Pos 5 /*!< CoreDebug DHCSR: C_SNAPSTALL Position */ +#define CoreDebug_DHCSR_C_SNAPSTALL_Msk (1UL << CoreDebug_DHCSR_C_SNAPSTALL_Pos) /*!< CoreDebug DHCSR: C_SNAPSTALL Mask */ -#define CoreDebug_DHCSR_C_MASKINTS_Pos 3 /*!< CoreDebug DHCSR: C_MASKINTS Position */ -#define CoreDebug_DHCSR_C_MASKINTS_Msk (1UL << CoreDebug_DHCSR_C_MASKINTS_Pos) /*!< CoreDebug DHCSR: C_MASKINTS Mask */ +#define CoreDebug_DHCSR_C_MASKINTS_Pos 3 /*!< CoreDebug DHCSR: C_MASKINTS Position */ +#define CoreDebug_DHCSR_C_MASKINTS_Msk (1UL << CoreDebug_DHCSR_C_MASKINTS_Pos) /*!< CoreDebug DHCSR: C_MASKINTS Mask */ -#define CoreDebug_DHCSR_C_STEP_Pos 2 /*!< CoreDebug DHCSR: C_STEP Position */ -#define CoreDebug_DHCSR_C_STEP_Msk (1UL << CoreDebug_DHCSR_C_STEP_Pos) /*!< CoreDebug DHCSR: C_STEP Mask */ +#define CoreDebug_DHCSR_C_STEP_Pos 2 /*!< CoreDebug DHCSR: C_STEP Position */ +#define CoreDebug_DHCSR_C_STEP_Msk (1UL << CoreDebug_DHCSR_C_STEP_Pos) /*!< CoreDebug DHCSR: C_STEP Mask */ -#define CoreDebug_DHCSR_C_HALT_Pos 1 /*!< CoreDebug DHCSR: C_HALT Position */ -#define CoreDebug_DHCSR_C_HALT_Msk (1UL << CoreDebug_DHCSR_C_HALT_Pos) /*!< CoreDebug DHCSR: C_HALT Mask */ +#define CoreDebug_DHCSR_C_HALT_Pos 1 /*!< CoreDebug DHCSR: C_HALT Position */ +#define CoreDebug_DHCSR_C_HALT_Msk (1UL << CoreDebug_DHCSR_C_HALT_Pos) /*!< CoreDebug DHCSR: C_HALT Mask */ -#define CoreDebug_DHCSR_C_DEBUGEN_Pos 0 /*!< CoreDebug DHCSR: C_DEBUGEN Position */ -#define CoreDebug_DHCSR_C_DEBUGEN_Msk (1UL << CoreDebug_DHCSR_C_DEBUGEN_Pos) /*!< CoreDebug DHCSR: C_DEBUGEN Mask */ +#define CoreDebug_DHCSR_C_DEBUGEN_Pos 0 /*!< CoreDebug DHCSR: C_DEBUGEN Position */ +#define CoreDebug_DHCSR_C_DEBUGEN_Msk (1UL << CoreDebug_DHCSR_C_DEBUGEN_Pos) /*!< CoreDebug DHCSR: C_DEBUGEN Mask */ /* Debug Core Register Selector Register */ -#define CoreDebug_DCRSR_REGWnR_Pos 16 /*!< CoreDebug DCRSR: REGWnR Position */ -#define CoreDebug_DCRSR_REGWnR_Msk (1UL << CoreDebug_DCRSR_REGWnR_Pos) /*!< CoreDebug DCRSR: REGWnR Mask */ +#define CoreDebug_DCRSR_REGWnR_Pos 16 /*!< CoreDebug DCRSR: REGWnR Position */ +#define CoreDebug_DCRSR_REGWnR_Msk (1UL << CoreDebug_DCRSR_REGWnR_Pos) /*!< CoreDebug DCRSR: REGWnR Mask */ -#define CoreDebug_DCRSR_REGSEL_Pos 0 /*!< CoreDebug DCRSR: REGSEL Position */ -#define CoreDebug_DCRSR_REGSEL_Msk (0x1FUL << CoreDebug_DCRSR_REGSEL_Pos) /*!< CoreDebug DCRSR: REGSEL Mask */ +#define CoreDebug_DCRSR_REGSEL_Pos 0 /*!< CoreDebug DCRSR: REGSEL Position */ +#define CoreDebug_DCRSR_REGSEL_Msk (0x1FUL << CoreDebug_DCRSR_REGSEL_Pos) /*!< CoreDebug DCRSR: REGSEL Mask */ /* Debug Exception and Monitor Control Register */ -#define CoreDebug_DEMCR_TRCENA_Pos 24 /*!< CoreDebug DEMCR: TRCENA Position */ -#define CoreDebug_DEMCR_TRCENA_Msk (1UL << CoreDebug_DEMCR_TRCENA_Pos) /*!< CoreDebug DEMCR: TRCENA Mask */ +#define CoreDebug_DEMCR_TRCENA_Pos 24 /*!< CoreDebug DEMCR: TRCENA Position */ +#define CoreDebug_DEMCR_TRCENA_Msk (1UL << CoreDebug_DEMCR_TRCENA_Pos) /*!< CoreDebug DEMCR: TRCENA Mask */ -#define CoreDebug_DEMCR_MON_REQ_Pos 19 /*!< CoreDebug DEMCR: MON_REQ Position */ -#define CoreDebug_DEMCR_MON_REQ_Msk (1UL << CoreDebug_DEMCR_MON_REQ_Pos) /*!< CoreDebug DEMCR: MON_REQ Mask */ +#define CoreDebug_DEMCR_MON_REQ_Pos 19 /*!< CoreDebug DEMCR: MON_REQ Position */ +#define CoreDebug_DEMCR_MON_REQ_Msk (1UL << CoreDebug_DEMCR_MON_REQ_Pos) /*!< CoreDebug DEMCR: MON_REQ Mask */ -#define CoreDebug_DEMCR_MON_STEP_Pos 18 /*!< CoreDebug DEMCR: MON_STEP Position */ -#define CoreDebug_DEMCR_MON_STEP_Msk (1UL << CoreDebug_DEMCR_MON_STEP_Pos) /*!< CoreDebug DEMCR: MON_STEP Mask */ +#define CoreDebug_DEMCR_MON_STEP_Pos 18 /*!< CoreDebug DEMCR: MON_STEP Position */ +#define CoreDebug_DEMCR_MON_STEP_Msk (1UL << CoreDebug_DEMCR_MON_STEP_Pos) /*!< CoreDebug DEMCR: MON_STEP Mask */ -#define CoreDebug_DEMCR_MON_PEND_Pos 17 /*!< CoreDebug DEMCR: MON_PEND Position */ -#define CoreDebug_DEMCR_MON_PEND_Msk (1UL << CoreDebug_DEMCR_MON_PEND_Pos) /*!< CoreDebug DEMCR: MON_PEND Mask */ +#define CoreDebug_DEMCR_MON_PEND_Pos 17 /*!< CoreDebug DEMCR: MON_PEND Position */ +#define CoreDebug_DEMCR_MON_PEND_Msk (1UL << CoreDebug_DEMCR_MON_PEND_Pos) /*!< CoreDebug DEMCR: MON_PEND Mask */ -#define CoreDebug_DEMCR_MON_EN_Pos 16 /*!< CoreDebug DEMCR: MON_EN Position */ -#define CoreDebug_DEMCR_MON_EN_Msk (1UL << CoreDebug_DEMCR_MON_EN_Pos) /*!< CoreDebug DEMCR: MON_EN Mask */ +#define CoreDebug_DEMCR_MON_EN_Pos 16 /*!< CoreDebug DEMCR: MON_EN Position */ +#define CoreDebug_DEMCR_MON_EN_Msk (1UL << CoreDebug_DEMCR_MON_EN_Pos) /*!< CoreDebug DEMCR: MON_EN Mask */ -#define CoreDebug_DEMCR_VC_HARDERR_Pos 10 /*!< CoreDebug DEMCR: VC_HARDERR Position */ -#define CoreDebug_DEMCR_VC_HARDERR_Msk (1UL << CoreDebug_DEMCR_VC_HARDERR_Pos) /*!< CoreDebug DEMCR: VC_HARDERR Mask */ +#define CoreDebug_DEMCR_VC_HARDERR_Pos 10 /*!< CoreDebug DEMCR: VC_HARDERR Position */ +#define CoreDebug_DEMCR_VC_HARDERR_Msk (1UL << CoreDebug_DEMCR_VC_HARDERR_Pos) /*!< CoreDebug DEMCR: VC_HARDERR Mask */ -#define CoreDebug_DEMCR_VC_INTERR_Pos 9 /*!< CoreDebug DEMCR: VC_INTERR Position */ -#define CoreDebug_DEMCR_VC_INTERR_Msk (1UL << CoreDebug_DEMCR_VC_INTERR_Pos) /*!< CoreDebug DEMCR: VC_INTERR Mask */ +#define CoreDebug_DEMCR_VC_INTERR_Pos 9 /*!< CoreDebug DEMCR: VC_INTERR Position */ +#define CoreDebug_DEMCR_VC_INTERR_Msk (1UL << CoreDebug_DEMCR_VC_INTERR_Pos) /*!< CoreDebug DEMCR: VC_INTERR Mask */ -#define CoreDebug_DEMCR_VC_BUSERR_Pos 8 /*!< CoreDebug DEMCR: VC_BUSERR Position */ -#define CoreDebug_DEMCR_VC_BUSERR_Msk (1UL << CoreDebug_DEMCR_VC_BUSERR_Pos) /*!< CoreDebug DEMCR: VC_BUSERR Mask */ +#define CoreDebug_DEMCR_VC_BUSERR_Pos 8 /*!< CoreDebug DEMCR: VC_BUSERR Position */ +#define CoreDebug_DEMCR_VC_BUSERR_Msk (1UL << CoreDebug_DEMCR_VC_BUSERR_Pos) /*!< CoreDebug DEMCR: VC_BUSERR Mask */ -#define CoreDebug_DEMCR_VC_STATERR_Pos 7 /*!< CoreDebug DEMCR: VC_STATERR Position */ -#define CoreDebug_DEMCR_VC_STATERR_Msk (1UL << CoreDebug_DEMCR_VC_STATERR_Pos) /*!< CoreDebug DEMCR: VC_STATERR Mask */ +#define CoreDebug_DEMCR_VC_STATERR_Pos 7 /*!< CoreDebug DEMCR: VC_STATERR Position */ +#define CoreDebug_DEMCR_VC_STATERR_Msk (1UL << CoreDebug_DEMCR_VC_STATERR_Pos) /*!< CoreDebug DEMCR: VC_STATERR Mask */ -#define CoreDebug_DEMCR_VC_CHKERR_Pos 6 /*!< CoreDebug DEMCR: VC_CHKERR Position */ -#define CoreDebug_DEMCR_VC_CHKERR_Msk (1UL << CoreDebug_DEMCR_VC_CHKERR_Pos) /*!< CoreDebug DEMCR: VC_CHKERR Mask */ +#define CoreDebug_DEMCR_VC_CHKERR_Pos 6 /*!< CoreDebug DEMCR: VC_CHKERR Position */ +#define CoreDebug_DEMCR_VC_CHKERR_Msk (1UL << CoreDebug_DEMCR_VC_CHKERR_Pos) /*!< CoreDebug DEMCR: VC_CHKERR Mask */ -#define CoreDebug_DEMCR_VC_NOCPERR_Pos 5 /*!< CoreDebug DEMCR: VC_NOCPERR Position */ -#define CoreDebug_DEMCR_VC_NOCPERR_Msk (1UL << CoreDebug_DEMCR_VC_NOCPERR_Pos) /*!< CoreDebug DEMCR: VC_NOCPERR Mask */ +#define CoreDebug_DEMCR_VC_NOCPERR_Pos 5 /*!< CoreDebug DEMCR: VC_NOCPERR Position */ +#define CoreDebug_DEMCR_VC_NOCPERR_Msk (1UL << CoreDebug_DEMCR_VC_NOCPERR_Pos) /*!< CoreDebug DEMCR: VC_NOCPERR Mask */ -#define CoreDebug_DEMCR_VC_MMERR_Pos 4 /*!< CoreDebug DEMCR: VC_MMERR Position */ -#define CoreDebug_DEMCR_VC_MMERR_Msk (1UL << CoreDebug_DEMCR_VC_MMERR_Pos) /*!< CoreDebug DEMCR: VC_MMERR Mask */ +#define CoreDebug_DEMCR_VC_MMERR_Pos 4 /*!< CoreDebug DEMCR: VC_MMERR Position */ +#define CoreDebug_DEMCR_VC_MMERR_Msk (1UL << CoreDebug_DEMCR_VC_MMERR_Pos) /*!< CoreDebug DEMCR: VC_MMERR Mask */ -#define CoreDebug_DEMCR_VC_CORERESET_Pos 0 /*!< CoreDebug DEMCR: VC_CORERESET Position */ -#define CoreDebug_DEMCR_VC_CORERESET_Msk (1UL << CoreDebug_DEMCR_VC_CORERESET_Pos) /*!< CoreDebug DEMCR: VC_CORERESET Mask */ +#define CoreDebug_DEMCR_VC_CORERESET_Pos 0 /*!< CoreDebug DEMCR: VC_CORERESET Position */ +#define CoreDebug_DEMCR_VC_CORERESET_Msk (1UL << CoreDebug_DEMCR_VC_CORERESET_Pos) /*!< CoreDebug DEMCR: VC_CORERESET Mask */ /*@} end of group CMSIS_CoreDebug */ - /** \ingroup CMSIS_core_register \defgroup CMSIS_core_base Core Definitions \brief Definitions for base addresses, unions, and structures. @@ -1584,39 +1567,37 @@ typedef struct */ /* Memory mapping of Cortex-M4 Hardware */ -#define SCS_BASE (0xE000E000UL) /*!< System Control Space Base Address */ -#define ITM_BASE (0xE0000000UL) /*!< ITM Base Address */ -#define DWT_BASE (0xE0001000UL) /*!< DWT Base Address */ -#define TPI_BASE (0xE0040000UL) /*!< TPI Base Address */ -#define CoreDebug_BASE (0xE000EDF0UL) /*!< Core Debug Base Address */ -#define SysTick_BASE (SCS_BASE + 0x0010UL) /*!< SysTick Base Address */ -#define NVIC_BASE (SCS_BASE + 0x0100UL) /*!< NVIC Base Address */ -#define SCB_BASE (SCS_BASE + 0x0D00UL) /*!< System Control Block Base Address */ - -#define SCnSCB ((SCnSCB_Type *) SCS_BASE ) /*!< System control Register not in SCB */ -#define SCB ((SCB_Type *) SCB_BASE ) /*!< SCB configuration struct */ -#define SysTick ((SysTick_Type *) SysTick_BASE ) /*!< SysTick configuration struct */ -#define NVIC ((NVIC_Type *) NVIC_BASE ) /*!< NVIC configuration struct */ -#define ITM ((ITM_Type *) ITM_BASE ) /*!< ITM configuration struct */ -#define DWT ((DWT_Type *) DWT_BASE ) /*!< DWT configuration struct */ -#define TPI ((TPI_Type *) TPI_BASE ) /*!< TPI configuration struct */ -#define CoreDebug ((CoreDebug_Type *) CoreDebug_BASE) /*!< Core Debug configuration struct */ +#define SCS_BASE (0xE000E000UL) /*!< System Control Space Base Address */ +#define ITM_BASE (0xE0000000UL) /*!< ITM Base Address */ +#define DWT_BASE (0xE0001000UL) /*!< DWT Base Address */ +#define TPI_BASE (0xE0040000UL) /*!< TPI Base Address */ +#define CoreDebug_BASE (0xE000EDF0UL) /*!< Core Debug Base Address */ +#define SysTick_BASE (SCS_BASE + 0x0010UL) /*!< SysTick Base Address */ +#define NVIC_BASE (SCS_BASE + 0x0100UL) /*!< NVIC Base Address */ +#define SCB_BASE (SCS_BASE + 0x0D00UL) /*!< System Control Block Base Address */ + +#define SCnSCB ((SCnSCB_Type *)SCS_BASE) /*!< System control Register not in SCB */ +#define SCB ((SCB_Type *)SCB_BASE) /*!< SCB configuration struct */ +#define SysTick ((SysTick_Type *)SysTick_BASE) /*!< SysTick configuration struct */ +#define NVIC ((NVIC_Type *)NVIC_BASE) /*!< NVIC configuration struct */ +#define ITM ((ITM_Type *)ITM_BASE) /*!< ITM configuration struct */ +#define DWT ((DWT_Type *)DWT_BASE) /*!< DWT configuration struct */ +#define TPI ((TPI_Type *)TPI_BASE) /*!< TPI configuration struct */ +#define CoreDebug ((CoreDebug_Type *)CoreDebug_BASE) /*!< Core Debug configuration struct */ #if (__MPU_PRESENT == 1) - #define MPU_BASE (SCS_BASE + 0x0D90UL) /*!< Memory Protection Unit */ - #define MPU ((MPU_Type *) MPU_BASE ) /*!< Memory Protection Unit */ +#define MPU_BASE (SCS_BASE + 0x0D90UL) /*!< Memory Protection Unit */ +#define MPU ((MPU_Type *)MPU_BASE) /*!< Memory Protection Unit */ #endif #if (__FPU_PRESENT == 1) - #define FPU_BASE (SCS_BASE + 0x0F30UL) /*!< Floating Point Unit */ - #define FPU ((FPU_Type *) FPU_BASE ) /*!< Floating Point Unit */ +#define FPU_BASE (SCS_BASE + 0x0F30UL) /*!< Floating Point Unit */ +#define FPU ((FPU_Type *)FPU_BASE) /*!< Floating Point Unit */ #endif -/*@} */ + /*@} */ - - -/******************************************************************************* + /******************************************************************************* * Hardware Abstraction Layer Core Function Interface contains: - Core NVIC Functions @@ -1624,19 +1605,17 @@ typedef struct - Core Debug Functions - Core Register Access Functions ******************************************************************************/ -/** \defgroup CMSIS_Core_FunctionInterface Functions and Instructions Reference + /** \defgroup CMSIS_Core_FunctionInterface Functions and Instructions Reference */ - - -/* ########################## NVIC functions #################################### */ -/** \ingroup CMSIS_Core_FunctionInterface + /* ########################## NVIC functions #################################### */ + /** \ingroup CMSIS_Core_FunctionInterface \defgroup CMSIS_Core_NVICFunctions NVIC Functions \brief Functions that manage interrupts and exceptions via the NVIC. @{ */ -/** \brief Set Priority Grouping + /** \brief Set Priority Grouping The function sets the priority grouping field using the required unlock sequence. The parameter PriorityGroup is assigned to the field SCB->AIRCR [10:8] PRIGROUP field. @@ -1646,58 +1625,54 @@ typedef struct \param [in] PriorityGroup Priority grouping field. */ -__STATIC_INLINE void NVIC_SetPriorityGrouping(uint32_t PriorityGroup) -{ - uint32_t reg_value; - uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07); /* only values 0..7 are used */ - - reg_value = SCB->AIRCR; /* read old register configuration */ - reg_value &= ~(SCB_AIRCR_VECTKEY_Msk | SCB_AIRCR_PRIGROUP_Msk); /* clear bits to change */ - reg_value = (reg_value | - ((uint32_t)0x5FA << SCB_AIRCR_VECTKEY_Pos) | - (PriorityGroupTmp << 8)); /* Insert write key and priorty group */ - SCB->AIRCR = reg_value; -} + __STATIC_INLINE void NVIC_SetPriorityGrouping(uint32_t PriorityGroup) + { + uint32_t reg_value; + uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07); /* only values 0..7 are used */ + reg_value = SCB->AIRCR; /* read old register configuration */ + reg_value &= ~(SCB_AIRCR_VECTKEY_Msk | SCB_AIRCR_PRIGROUP_Msk); /* clear bits to change */ + reg_value = (reg_value | + ((uint32_t)0x5FA << SCB_AIRCR_VECTKEY_Pos) | + (PriorityGroupTmp << 8)); /* Insert write key and priorty group */ + SCB->AIRCR = reg_value; + } -/** \brief Get Priority Grouping + /** \brief Get Priority Grouping The function reads the priority grouping field from the NVIC Interrupt Controller. \return Priority grouping field (SCB->AIRCR [10:8] PRIGROUP field). */ -__STATIC_INLINE uint32_t NVIC_GetPriorityGrouping(void) -{ - return ((SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) >> SCB_AIRCR_PRIGROUP_Pos); /* read priority grouping field */ -} + __STATIC_INLINE uint32_t NVIC_GetPriorityGrouping(void) + { + return ((SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) >> SCB_AIRCR_PRIGROUP_Pos); /* read priority grouping field */ + } - -/** \brief Enable External Interrupt + /** \brief Enable External Interrupt The function enables a device-specific interrupt in the NVIC interrupt controller. \param [in] IRQn External interrupt number. Value cannot be negative. */ -__STATIC_INLINE void NVIC_EnableIRQ(IRQn_Type IRQn) -{ -/* NVIC->ISER[((uint32_t)(IRQn) >> 5)] = (1 << ((uint32_t)(IRQn) & 0x1F)); enable interrupt */ - NVIC->ISER[(uint32_t)((int32_t)IRQn) >> 5] = (uint32_t)(1 << ((uint32_t)((int32_t)IRQn) & (uint32_t)0x1F)); /* enable interrupt */ -} + __STATIC_INLINE void NVIC_EnableIRQ(IRQn_Type IRQn) + { + /* NVIC->ISER[((uint32_t)(IRQn) >> 5)] = (1 << ((uint32_t)(IRQn) & 0x1F)); enable interrupt */ + NVIC->ISER[(uint32_t)((int32_t)IRQn) >> 5] = (uint32_t)(1 << ((uint32_t)((int32_t)IRQn) & (uint32_t)0x1F)); /* enable interrupt */ + } - -/** \brief Disable External Interrupt + /** \brief Disable External Interrupt The function disables a device-specific interrupt in the NVIC interrupt controller. \param [in] IRQn External interrupt number. Value cannot be negative. */ -__STATIC_INLINE void NVIC_DisableIRQ(IRQn_Type IRQn) -{ - NVIC->ICER[((uint32_t)(IRQn) >> 5)] = (1 << ((uint32_t)(IRQn) & 0x1F)); /* disable interrupt */ -} + __STATIC_INLINE void NVIC_DisableIRQ(IRQn_Type IRQn) + { + NVIC->ICER[((uint32_t)(IRQn) >> 5)] = (1 << ((uint32_t)(IRQn)&0x1F)); /* disable interrupt */ + } - -/** \brief Get Pending Interrupt + /** \brief Get Pending Interrupt The function reads the pending register in the NVIC and returns the pending bit for the specified interrupt. @@ -1707,37 +1682,34 @@ __STATIC_INLINE void NVIC_DisableIRQ(IRQn_Type IRQn) \return 0 Interrupt status is not pending. \return 1 Interrupt status is pending. */ -__STATIC_INLINE uint32_t NVIC_GetPendingIRQ(IRQn_Type IRQn) -{ - return((uint32_t) ((NVIC->ISPR[(uint32_t)(IRQn) >> 5] & (1 << ((uint32_t)(IRQn) & 0x1F)))?1:0)); /* Return 1 if pending else 0 */ -} + __STATIC_INLINE uint32_t NVIC_GetPendingIRQ(IRQn_Type IRQn) + { + return ((uint32_t)((NVIC->ISPR[(uint32_t)(IRQn) >> 5] & (1 << ((uint32_t)(IRQn)&0x1F))) ? 1 : 0)); /* Return 1 if pending else 0 */ + } - -/** \brief Set Pending Interrupt + /** \brief Set Pending Interrupt The function sets the pending bit of an external interrupt. \param [in] IRQn Interrupt number. Value cannot be negative. */ -__STATIC_INLINE void NVIC_SetPendingIRQ(IRQn_Type IRQn) -{ - NVIC->ISPR[((uint32_t)(IRQn) >> 5)] = (1 << ((uint32_t)(IRQn) & 0x1F)); /* set interrupt pending */ -} + __STATIC_INLINE void NVIC_SetPendingIRQ(IRQn_Type IRQn) + { + NVIC->ISPR[((uint32_t)(IRQn) >> 5)] = (1 << ((uint32_t)(IRQn)&0x1F)); /* set interrupt pending */ + } - -/** \brief Clear Pending Interrupt + /** \brief Clear Pending Interrupt The function clears the pending bit of an external interrupt. \param [in] IRQn External interrupt number. Value cannot be negative. */ -__STATIC_INLINE void NVIC_ClearPendingIRQ(IRQn_Type IRQn) -{ - NVIC->ICPR[((uint32_t)(IRQn) >> 5)] = (1 << ((uint32_t)(IRQn) & 0x1F)); /* Clear pending interrupt */ -} + __STATIC_INLINE void NVIC_ClearPendingIRQ(IRQn_Type IRQn) + { + NVIC->ICPR[((uint32_t)(IRQn) >> 5)] = (1 << ((uint32_t)(IRQn)&0x1F)); /* Clear pending interrupt */ + } - -/** \brief Get Active Interrupt + /** \brief Get Active Interrupt The function reads the active register in NVIC and returns the active bit. @@ -1746,13 +1718,12 @@ __STATIC_INLINE void NVIC_ClearPendingIRQ(IRQn_Type IRQn) \return 0 Interrupt status is not active. \return 1 Interrupt status is active. */ -__STATIC_INLINE uint32_t NVIC_GetActive(IRQn_Type IRQn) -{ - return((uint32_t)((NVIC->IABR[(uint32_t)(IRQn) >> 5] & (1 << ((uint32_t)(IRQn) & 0x1F)))?1:0)); /* Return 1 if active else 0 */ -} + __STATIC_INLINE uint32_t NVIC_GetActive(IRQn_Type IRQn) + { + return ((uint32_t)((NVIC->IABR[(uint32_t)(IRQn) >> 5] & (1 << ((uint32_t)(IRQn)&0x1F))) ? 1 : 0)); /* Return 1 if active else 0 */ + } - -/** \brief Set Interrupt Priority + /** \brief Set Interrupt Priority The function sets the priority of an interrupt. @@ -1761,16 +1732,19 @@ __STATIC_INLINE uint32_t NVIC_GetActive(IRQn_Type IRQn) \param [in] IRQn Interrupt number. \param [in] priority Priority to set. */ -__STATIC_INLINE void NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority) -{ - if(IRQn < 0) { - SCB->SHPR[((uint32_t)(IRQn) & 0xF)-4] = ((priority << (8 - __NVIC_PRIO_BITS)) & 0xff); } /* set Priority for Cortex-M System Interrupts */ - else { - NVIC->IP[(uint32_t)(IRQn)] = ((priority << (8 - __NVIC_PRIO_BITS)) & 0xff); } /* set Priority for device specific Interrupts */ -} - - -/** \brief Get Interrupt Priority + __STATIC_INLINE void NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority) + { + if (IRQn < 0) + { + SCB->SHPR[((uint32_t)(IRQn)&0xF) - 4] = ((priority << (8 - __NVIC_PRIO_BITS)) & 0xff); + } /* set Priority for Cortex-M System Interrupts */ + else + { + NVIC->IP[(uint32_t)(IRQn)] = ((priority << (8 - __NVIC_PRIO_BITS)) & 0xff); + } /* set Priority for device specific Interrupts */ + } + + /** \brief Get Interrupt Priority The function reads the priority of an interrupt. The interrupt number can be positive to specify an external (device specific) @@ -1781,17 +1755,20 @@ __STATIC_INLINE void NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority) \return Interrupt Priority. Value is aligned automatically to the implemented priority bits of the microcontroller. */ -__STATIC_INLINE uint32_t NVIC_GetPriority(IRQn_Type IRQn) -{ + __STATIC_INLINE uint32_t NVIC_GetPriority(IRQn_Type IRQn) + { - if(IRQn < 0) { - return((uint32_t)(SCB->SHPR[((uint32_t)(IRQn) & 0xF)-4] >> (8 - __NVIC_PRIO_BITS))); } /* get priority for Cortex-M system interrupts */ - else { - return((uint32_t)(NVIC->IP[(uint32_t)(IRQn)] >> (8 - __NVIC_PRIO_BITS))); } /* get priority for device specific interrupts */ -} + if (IRQn < 0) + { + return ((uint32_t)(SCB->SHPR[((uint32_t)(IRQn)&0xF) - 4] >> (8 - __NVIC_PRIO_BITS))); + } /* get priority for Cortex-M system interrupts */ + else + { + return ((uint32_t)(NVIC->IP[(uint32_t)(IRQn)] >> (8 - __NVIC_PRIO_BITS))); + } /* get priority for device specific interrupts */ + } - -/** \brief Encode Priority + /** \brief Encode Priority The function encodes the priority for an interrupt with the given priority group, preemptive priority value, and subpriority value. @@ -1803,23 +1780,21 @@ __STATIC_INLINE uint32_t NVIC_GetPriority(IRQn_Type IRQn) \param [in] SubPriority Subpriority value (starting from 0). \return Encoded priority. Value can be used in the function \ref NVIC_SetPriority(). */ -__STATIC_INLINE uint32_t NVIC_EncodePriority (uint32_t PriorityGroup, uint32_t PreemptPriority, uint32_t SubPriority) -{ - uint32_t PriorityGroupTmp = (PriorityGroup & 0x07); /* only values 0..7 are used */ - uint32_t PreemptPriorityBits; - uint32_t SubPriorityBits; + __STATIC_INLINE uint32_t NVIC_EncodePriority(uint32_t PriorityGroup, uint32_t PreemptPriority, uint32_t SubPriority) + { + uint32_t PriorityGroupTmp = (PriorityGroup & 0x07); /* only values 0..7 are used */ + uint32_t PreemptPriorityBits; + uint32_t SubPriorityBits; - PreemptPriorityBits = ((7 - PriorityGroupTmp) > __NVIC_PRIO_BITS) ? __NVIC_PRIO_BITS : 7 - PriorityGroupTmp; - SubPriorityBits = ((PriorityGroupTmp + __NVIC_PRIO_BITS) < 7) ? 0 : PriorityGroupTmp - 7 + __NVIC_PRIO_BITS; + PreemptPriorityBits = ((7 - PriorityGroupTmp) > __NVIC_PRIO_BITS) ? __NVIC_PRIO_BITS : 7 - PriorityGroupTmp; + SubPriorityBits = ((PriorityGroupTmp + __NVIC_PRIO_BITS) < 7) ? 0 : PriorityGroupTmp - 7 + __NVIC_PRIO_BITS; - return ( - ((PreemptPriority & ((1 << (PreemptPriorityBits)) - 1)) << SubPriorityBits) | - ((SubPriority & ((1 << (SubPriorityBits )) - 1))) - ); -} + return ( + ((PreemptPriority & ((1 << (PreemptPriorityBits)) - 1)) << SubPriorityBits) | + ((SubPriority & ((1 << (SubPriorityBits)) - 1)))); + } - -/** \brief Decode Priority + /** \brief Decode Priority The function decodes an interrupt priority value with a given priority group to preemptive priority value and subpriority value. @@ -1831,38 +1806,37 @@ __STATIC_INLINE uint32_t NVIC_EncodePriority (uint32_t PriorityGroup, uint32_t P \param [out] pPreemptPriority Preemptive priority value (starting from 0). \param [out] pSubPriority Subpriority value (starting from 0). */ -__STATIC_INLINE void NVIC_DecodePriority (uint32_t Priority, uint32_t PriorityGroup, uint32_t* pPreemptPriority, uint32_t* pSubPriority) -{ - uint32_t PriorityGroupTmp = (PriorityGroup & 0x07); /* only values 0..7 are used */ - uint32_t PreemptPriorityBits; - uint32_t SubPriorityBits; - - PreemptPriorityBits = ((7 - PriorityGroupTmp) > __NVIC_PRIO_BITS) ? __NVIC_PRIO_BITS : 7 - PriorityGroupTmp; - SubPriorityBits = ((PriorityGroupTmp + __NVIC_PRIO_BITS) < 7) ? 0 : PriorityGroupTmp - 7 + __NVIC_PRIO_BITS; + __STATIC_INLINE void NVIC_DecodePriority(uint32_t Priority, uint32_t PriorityGroup, uint32_t *pPreemptPriority, uint32_t *pSubPriority) + { + uint32_t PriorityGroupTmp = (PriorityGroup & 0x07); /* only values 0..7 are used */ + uint32_t PreemptPriorityBits; + uint32_t SubPriorityBits; - *pPreemptPriority = (Priority >> SubPriorityBits) & ((1 << (PreemptPriorityBits)) - 1); - *pSubPriority = (Priority ) & ((1 << (SubPriorityBits )) - 1); -} + PreemptPriorityBits = ((7 - PriorityGroupTmp) > __NVIC_PRIO_BITS) ? __NVIC_PRIO_BITS : 7 - PriorityGroupTmp; + SubPriorityBits = ((PriorityGroupTmp + __NVIC_PRIO_BITS) < 7) ? 0 : PriorityGroupTmp - 7 + __NVIC_PRIO_BITS; + *pPreemptPriority = (Priority >> SubPriorityBits) & ((1 << (PreemptPriorityBits)) - 1); + *pSubPriority = (Priority) & ((1 << (SubPriorityBits)) - 1); + } -/** \brief System Reset + /** \brief System Reset The function initiates a system reset request to reset the MCU. */ -__STATIC_INLINE void NVIC_SystemReset(void) -{ - __DSB(); /* Ensure all outstanding memory accesses included + __STATIC_INLINE void NVIC_SystemReset(void) + { + __DSB(); /* Ensure all outstanding memory accesses included buffered write are completed before reset */ - SCB->AIRCR = ((0x5FA << SCB_AIRCR_VECTKEY_Pos) | - (SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) | - SCB_AIRCR_SYSRESETREQ_Msk); /* Keep priority group unchanged */ - __DSB(); /* Ensure completion of memory access */ - while(1); /* wait until reset */ -} + SCB->AIRCR = ((0x5FA << SCB_AIRCR_VECTKEY_Pos) | + (SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) | + SCB_AIRCR_SYSRESETREQ_Msk); /* Keep priority group unchanged */ + __DSB(); /* Ensure completion of memory access */ + while (1) + ; /* wait until reset */ + } /*@} end of CMSIS_Core_NVICFunctions */ - /* ########################## Cache functions #################################### */ /** \ingroup CMSIS_Core_FunctionInterface \defgroup CMSIS_Core_CacheFunctions Cache Functions @@ -1871,233 +1845,231 @@ __STATIC_INLINE void NVIC_SystemReset(void) */ /* Cache Size ID Register Macros */ -#define CCSIDR_WAYS(x) (((x) & SCB_CCSIDR_ASSOCIATIVITY_Msk) >> SCB_CCSIDR_ASSOCIATIVITY_Pos) -#define CCSIDR_SETS(x) (((x) & SCB_CCSIDR_NUMSETS_Msk ) >> SCB_CCSIDR_NUMSETS_Pos ) -#define CCSIDR_LSSHIFT(x) (((x) & SCB_CCSIDR_LINESIZE_Msk ) >> SCB_CCSIDR_LINESIZE_Pos ) - +#define CCSIDR_WAYS(x) (((x)&SCB_CCSIDR_ASSOCIATIVITY_Msk) >> SCB_CCSIDR_ASSOCIATIVITY_Pos) +#define CCSIDR_SETS(x) (((x)&SCB_CCSIDR_NUMSETS_Msk) >> SCB_CCSIDR_NUMSETS_Pos) +#define CCSIDR_LSSHIFT(x) (((x)&SCB_CCSIDR_LINESIZE_Msk) >> SCB_CCSIDR_LINESIZE_Pos) -/** \brief Enable I-Cache + /** \brief Enable I-Cache The function turns on I-Cache */ -__STATIC_INLINE void SCB_EnableICache(void) -{ - #if (__ICACHE_PRESENT == 1) - __DSB(); - __ISB(); - SCB->ICIALLU = 0; // invalidate I-Cache - SCB->CCR |= SCB_CCR_IC_Msk; // enable I-Cache - __DSB(); - __ISB(); - #endif -} - + __STATIC_INLINE void SCB_EnableICache(void) + { +#if (__ICACHE_PRESENT == 1) + __DSB(); + __ISB(); + SCB->ICIALLU = 0; // invalidate I-Cache + SCB->CCR |= SCB_CCR_IC_Msk; // enable I-Cache + __DSB(); + __ISB(); +#endif + } -/** \brief Disable I-Cache + /** \brief Disable I-Cache The function turns off I-Cache */ -__STATIC_INLINE void SCB_DisableICache(void) -{ - #if (__ICACHE_PRESENT == 1) - __DSB(); - __ISB(); - SCB->CCR &= ~SCB_CCR_IC_Msk; // disable I-Cache - SCB->ICIALLU = 0; // invalidate I-Cache - __DSB(); - __ISB(); - #endif -} - + __STATIC_INLINE void SCB_DisableICache(void) + { +#if (__ICACHE_PRESENT == 1) + __DSB(); + __ISB(); + SCB->CCR &= ~SCB_CCR_IC_Msk; // disable I-Cache + SCB->ICIALLU = 0; // invalidate I-Cache + __DSB(); + __ISB(); +#endif + } -/** \brief Invalidate I-Cache + /** \brief Invalidate I-Cache The function invalidates I-Cache */ -__STATIC_INLINE void SCB_InvalidateICache(void) -{ - #if (__ICACHE_PRESENT == 1) - __DSB(); - __ISB(); - SCB->ICIALLU = 0; - __DSB(); - __ISB(); - #endif -} - + __STATIC_INLINE void SCB_InvalidateICache(void) + { +#if (__ICACHE_PRESENT == 1) + __DSB(); + __ISB(); + SCB->ICIALLU = 0; + __DSB(); + __ISB(); +#endif + } -/** \brief Enable D-Cache + /** \brief Enable D-Cache The function turns on D-Cache */ -__STATIC_INLINE void SCB_EnableDCache(void) -{ - #if (__DCACHE_PRESENT == 1) - uint32_t ccsidr, sshift, wshift, sw; - uint32_t sets, ways; - - ccsidr = SCB->CCSIDR; - sets = CCSIDR_SETS(ccsidr); - sshift = CCSIDR_LSSHIFT(ccsidr) + 4; - ways = CCSIDR_WAYS(ccsidr); - wshift = __CLZ(ways) & 0x1f; - - __DSB(); - - do { // invalidate D-Cache - int32_t tmpways = ways; - do { - sw = ((tmpways << wshift) | (sets << sshift)); - SCB->DCISW = sw; - } while(tmpways--); - } while(sets--); - __DSB(); - - SCB->CCR |= SCB_CCR_DC_Msk; // enable D-Cache - - __DSB(); - __ISB(); - #endif -} - + __STATIC_INLINE void SCB_EnableDCache(void) + { +#if (__DCACHE_PRESENT == 1) + uint32_t ccsidr, sshift, wshift, sw; + uint32_t sets, ways; + + ccsidr = SCB->CCSIDR; + sets = CCSIDR_SETS(ccsidr); + sshift = CCSIDR_LSSHIFT(ccsidr) + 4; + ways = CCSIDR_WAYS(ccsidr); + wshift = __CLZ(ways) & 0x1f; + + __DSB(); + + do + { // invalidate D-Cache + int32_t tmpways = ways; + do + { + sw = ((tmpways << wshift) | (sets << sshift)); + SCB->DCISW = sw; + } while (tmpways--); + } while (sets--); + __DSB(); + + SCB->CCR |= SCB_CCR_DC_Msk; // enable D-Cache + + __DSB(); + __ISB(); +#endif + } -/** \brief Disable D-Cache + /** \brief Disable D-Cache The function turns off D-Cache */ -__STATIC_INLINE void SCB_DisableDCache(void) -{ - #if (__DCACHE_PRESENT == 1) - uint32_t ccsidr, sshift, wshift, sw; - uint32_t sets, ways; - - ccsidr = SCB->CCSIDR; - sets = CCSIDR_SETS(ccsidr); - sshift = CCSIDR_LSSHIFT(ccsidr) + 4; - ways = CCSIDR_WAYS(ccsidr); - wshift = __CLZ(ways) & 0x1f; - - __DSB(); - - SCB->CCR &= ~SCB_CCR_DC_Msk; // disable D-Cache - - do { // clean & invalidate D-Cache - int32_t tmpways = ways; - do { - sw = ((tmpways << wshift) | (sets << sshift)); - SCB->DCCISW = sw; - } while(tmpways--); - } while(sets--); - - - __DSB(); - __ISB(); - #endif -} - + __STATIC_INLINE void SCB_DisableDCache(void) + { +#if (__DCACHE_PRESENT == 1) + uint32_t ccsidr, sshift, wshift, sw; + uint32_t sets, ways; + + ccsidr = SCB->CCSIDR; + sets = CCSIDR_SETS(ccsidr); + sshift = CCSIDR_LSSHIFT(ccsidr) + 4; + ways = CCSIDR_WAYS(ccsidr); + wshift = __CLZ(ways) & 0x1f; + + __DSB(); + + SCB->CCR &= ~SCB_CCR_DC_Msk; // disable D-Cache + + do + { // clean & invalidate D-Cache + int32_t tmpways = ways; + do + { + sw = ((tmpways << wshift) | (sets << sshift)); + SCB->DCCISW = sw; + } while (tmpways--); + } while (sets--); + + __DSB(); + __ISB(); +#endif + } -/** \brief Invalidate D-Cache + /** \brief Invalidate D-Cache The function invalidates D-Cache */ -__STATIC_INLINE void SCB_InvalidateDCache(void) -{ - #if (__DCACHE_PRESENT == 1) - uint32_t ccsidr, sshift, wshift, sw; - uint32_t sets, ways; - - ccsidr = SCB->CCSIDR; - sets = CCSIDR_SETS(ccsidr); - sshift = CCSIDR_LSSHIFT(ccsidr) + 4; - ways = CCSIDR_WAYS(ccsidr); - wshift = __CLZ(ways) & 0x1f; - - __DSB(); - - do { // invalidate D-Cache - int32_t tmpways = ways; - do { - sw = ((tmpways << wshift) | (sets << sshift)); - SCB->DCISW = sw; - } while(tmpways--); - } while(sets--); - - __DSB(); - __ISB(); - #endif -} - + __STATIC_INLINE void SCB_InvalidateDCache(void) + { +#if (__DCACHE_PRESENT == 1) + uint32_t ccsidr, sshift, wshift, sw; + uint32_t sets, ways; + + ccsidr = SCB->CCSIDR; + sets = CCSIDR_SETS(ccsidr); + sshift = CCSIDR_LSSHIFT(ccsidr) + 4; + ways = CCSIDR_WAYS(ccsidr); + wshift = __CLZ(ways) & 0x1f; + + __DSB(); + + do + { // invalidate D-Cache + int32_t tmpways = ways; + do + { + sw = ((tmpways << wshift) | (sets << sshift)); + SCB->DCISW = sw; + } while (tmpways--); + } while (sets--); + + __DSB(); + __ISB(); +#endif + } -/** \brief Clean D-Cache + /** \brief Clean D-Cache The function cleans D-Cache */ -__STATIC_INLINE void SCB_CleanDCache(void) -{ - #if (__DCACHE_PRESENT == 1) - uint32_t ccsidr, sshift, wshift, sw; - uint32_t sets, ways; - - ccsidr = SCB->CCSIDR; - sets = CCSIDR_SETS(ccsidr); - sshift = CCSIDR_LSSHIFT(ccsidr) + 4; - ways = CCSIDR_WAYS(ccsidr); - wshift = __CLZ(ways) & 0x1f; - - __DSB(); - - do { // clean D-Cache - int32_t tmpways = ways; - do { - sw = ((tmpways << wshift) | (sets << sshift)); - SCB->DCCSW = sw; - } while(tmpways--); - } while(sets--); - - __DSB(); - __ISB(); - #endif -} - + __STATIC_INLINE void SCB_CleanDCache(void) + { +#if (__DCACHE_PRESENT == 1) + uint32_t ccsidr, sshift, wshift, sw; + uint32_t sets, ways; + + ccsidr = SCB->CCSIDR; + sets = CCSIDR_SETS(ccsidr); + sshift = CCSIDR_LSSHIFT(ccsidr) + 4; + ways = CCSIDR_WAYS(ccsidr); + wshift = __CLZ(ways) & 0x1f; + + __DSB(); + + do + { // clean D-Cache + int32_t tmpways = ways; + do + { + sw = ((tmpways << wshift) | (sets << sshift)); + SCB->DCCSW = sw; + } while (tmpways--); + } while (sets--); + + __DSB(); + __ISB(); +#endif + } -/** \brief Clean & Invalidate D-Cache + /** \brief Clean & Invalidate D-Cache The function cleans and Invalidates D-Cache */ -__STATIC_INLINE void SCB_CleanInvalidateDCache(void) -{ - #if (__DCACHE_PRESENT == 1) - uint32_t ccsidr, sshift, wshift, sw; - uint32_t sets, ways; - - ccsidr = SCB->CCSIDR; - sets = CCSIDR_SETS(ccsidr); - sshift = CCSIDR_LSSHIFT(ccsidr) + 4; - ways = CCSIDR_WAYS(ccsidr); - wshift = __CLZ(ways) & 0x1f; - - __DSB(); - - do { // clean & invalidate D-Cache - int32_t tmpways = ways; - do { - sw = ((tmpways << wshift) | (sets << sshift)); - SCB->DCCISW = sw; - } while(tmpways--); - } while(sets--); - - __DSB(); - __ISB(); - #endif -} - - -/*@} end of CMSIS_Core_CacheFunctions */ - + __STATIC_INLINE void SCB_CleanInvalidateDCache(void) + { +#if (__DCACHE_PRESENT == 1) + uint32_t ccsidr, sshift, wshift, sw; + uint32_t sets, ways; + + ccsidr = SCB->CCSIDR; + sets = CCSIDR_SETS(ccsidr); + sshift = CCSIDR_LSSHIFT(ccsidr) + 4; + ways = CCSIDR_WAYS(ccsidr); + wshift = __CLZ(ways) & 0x1f; + + __DSB(); + + do + { // clean & invalidate D-Cache + int32_t tmpways = ways; + do + { + sw = ((tmpways << wshift) | (sets << sshift)); + SCB->DCCISW = sw; + } while (tmpways--); + } while (sets--); + + __DSB(); + __ISB(); +#endif + } + /*@} end of CMSIS_Core_CacheFunctions */ -/* ################################## SysTick function ############################################ */ -/** \ingroup CMSIS_Core_FunctionInterface + /* ################################## SysTick function ############################################ */ + /** \ingroup CMSIS_Core_FunctionInterface \defgroup CMSIS_Core_SysTickFunctions SysTick Functions \brief Functions that configure the System. @{ @@ -2105,7 +2077,7 @@ __STATIC_INLINE void SCB_CleanInvalidateDCache(void) #if (__Vendor_SysTickConfig == 0) -/** \brief System Tick Configuration + /** \brief System Tick Configuration The function initializes the System Timer and its interrupt, and starts the System Tick Timer. Counter is in free running mode to generate periodic interrupts. @@ -2120,37 +2092,35 @@ __STATIC_INLINE void SCB_CleanInvalidateDCache(void) must contain a vendor-specific implementation of this function. */ -__STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks) -{ - if ((ticks - 1) > SysTick_LOAD_RELOAD_Msk) return (1); /* Reload value impossible */ - - SysTick->LOAD = ticks - 1; /* set reload register */ - NVIC_SetPriority (SysTick_IRQn, (1<<__NVIC_PRIO_BITS) - 1); /* set Priority for Systick Interrupt */ - SysTick->VAL = 0; /* Load the SysTick Counter Value */ - SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk | - SysTick_CTRL_TICKINT_Msk | - SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */ - return (0); /* Function successful */ -} + __STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks) + { + if ((ticks - 1) > SysTick_LOAD_RELOAD_Msk) + return (1); /* Reload value impossible */ + + SysTick->LOAD = ticks - 1; /* set reload register */ + NVIC_SetPriority(SysTick_IRQn, (1 << __NVIC_PRIO_BITS) - 1); /* set Priority for Systick Interrupt */ + SysTick->VAL = 0; /* Load the SysTick Counter Value */ + SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk | + SysTick_CTRL_TICKINT_Msk | + SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */ + return (0); /* Function successful */ + } #endif -/*@} end of CMSIS_Core_SysTickFunctions */ - + /*@} end of CMSIS_Core_SysTickFunctions */ - -/* ##################################### Debug In/Output function ########################################### */ -/** \ingroup CMSIS_Core_FunctionInterface + /* ##################################### Debug In/Output function ########################################### */ + /** \ingroup CMSIS_Core_FunctionInterface \defgroup CMSIS_core_DebugFunctions ITM Functions \brief Functions that access the ITM debug interface. @{ */ -extern volatile int32_t ITM_RxBuffer; /*!< External variable to receive characters. */ -#define ITM_RXBUFFER_EMPTY 0x5AA55AA5 /*!< Value identifying \ref ITM_RxBuffer is ready for next character. */ - + extern volatile int32_t ITM_RxBuffer; /*!< External variable to receive characters. */ +#define ITM_RXBUFFER_EMPTY 0x5AA55AA5 /*!< Value identifying \ref ITM_RxBuffer is ready for next character. */ -/** \brief ITM Send Character + /** \brief ITM Send Character The function transmits a character via the ITM channel 0, and \li Just returns when no debugger is connected that has booked the output. @@ -2160,57 +2130,59 @@ extern volatile int32_t ITM_RxBuffer; /*!< External variable \returns Character to transmit. */ -__STATIC_INLINE uint32_t ITM_SendChar (uint32_t ch) -{ - if ((ITM->TCR & ITM_TCR_ITMENA_Msk) && /* ITM enabled */ - (ITM->TER & (1UL << 0) ) ) /* ITM Port #0 enabled */ - { - while (ITM->PORT[0].u32 == 0); - ITM->PORT[0].u8 = (uint8_t) ch; - } - return (ch); -} - - -/** \brief ITM Receive Character + __STATIC_INLINE uint32_t ITM_SendChar(uint32_t ch) + { + if ((ITM->TCR & ITM_TCR_ITMENA_Msk) && /* ITM enabled */ + (ITM->TER & (1UL << 0))) /* ITM Port #0 enabled */ + { + while (ITM->PORT[0].u32 == 0) + ; + ITM->PORT[0].u8 = (uint8_t)ch; + } + return (ch); + } + + /** \brief ITM Receive Character The function inputs a character via the external variable \ref ITM_RxBuffer. \return Received character. \return -1 No character pending. */ -__STATIC_INLINE int32_t ITM_ReceiveChar (void) { - int32_t ch = -1; /* no character available */ - - if (ITM_RxBuffer != ITM_RXBUFFER_EMPTY) { - ch = ITM_RxBuffer; - ITM_RxBuffer = ITM_RXBUFFER_EMPTY; /* ready for next character */ - } + __STATIC_INLINE int32_t ITM_ReceiveChar(void) + { + int32_t ch = -1; /* no character available */ - return (ch); -} + if (ITM_RxBuffer != ITM_RXBUFFER_EMPTY) + { + ch = ITM_RxBuffer; + ITM_RxBuffer = ITM_RXBUFFER_EMPTY; /* ready for next character */ + } + return (ch); + } -/** \brief ITM Check Character + /** \brief ITM Check Character The function checks whether a character is pending for reading in the variable \ref ITM_RxBuffer. \return 0 No character available. \return 1 Character available. */ -__STATIC_INLINE int32_t ITM_CheckChar (void) { - - if (ITM_RxBuffer == ITM_RXBUFFER_EMPTY) { - return (0); /* no character available */ - } else { - return (1); /* character available */ - } -} - -/*@} end of CMSIS_core_DebugFunctions */ - - - + __STATIC_INLINE int32_t ITM_CheckChar(void) + { + + if (ITM_RxBuffer == ITM_RXBUFFER_EMPTY) + { + return (0); /* no character available */ + } + else + { + return (1); /* character available */ + } + } + + /*@} end of CMSIS_core_DebugFunctions */ #ifdef __cplusplus } diff --git a/bsp/swm320-lq100/Libraries/CMSIS/CoreSupport/core_cmFunc.h b/bsp/swm320-lq100/Libraries/CMSIS/CoreSupport/core_cmFunc.h index 01089f1333..1ccdd1cb91 100644 --- a/bsp/swm320-lq100/Libraries/CMSIS/CoreSupport/core_cmFunc.h +++ b/bsp/swm320-lq100/Libraries/CMSIS/CoreSupport/core_cmFunc.h @@ -1,4 +1,4 @@ -/**************************************************************************//** +/**************************************************************************/ /** * @file core_cmFunc.h * @brief CMSIS Cortex-M Core Function Access Header File * @version V4.00 @@ -34,22 +34,20 @@ POSSIBILITY OF SUCH DAMAGE. ---------------------------------------------------------------------------*/ - #ifndef __CORE_CMFUNC_H #define __CORE_CMFUNC_H - /* ########################### Core Function Access ########################### */ /** \ingroup CMSIS_Core_FunctionInterface \defgroup CMSIS_Core_RegAccFunctions CMSIS Core Register Access Functions @{ */ -#if defined ( __CC_ARM ) /*------------------RealView Compiler -----------------*/ +#if defined(__CC_ARM) /*------------------RealView Compiler -----------------*/ /* ARM armcc specific functions */ #if (__ARMCC_VERSION < 400677) - #error "Please use ARM Compiler Toolchain V4.0.677 or later!" +#error "Please use ARM Compiler Toolchain V4.0.677 or later!" #endif /* intrinsic void __enable_irq(); */ @@ -63,11 +61,10 @@ */ __STATIC_INLINE uint32_t __get_CONTROL(void) { - register uint32_t __regControl __ASM("control"); - return(__regControl); + register uint32_t __regControl __ASM("control"); + return (__regControl); } - /** \brief Set Control Register This function writes the given value to the Control Register. @@ -76,11 +73,10 @@ __STATIC_INLINE uint32_t __get_CONTROL(void) */ __STATIC_INLINE void __set_CONTROL(uint32_t control) { - register uint32_t __regControl __ASM("control"); - __regControl = control; + register uint32_t __regControl __ASM("control"); + __regControl = control; } - /** \brief Get IPSR Register This function returns the content of the IPSR Register. @@ -89,11 +85,10 @@ __STATIC_INLINE void __set_CONTROL(uint32_t control) */ __STATIC_INLINE uint32_t __get_IPSR(void) { - register uint32_t __regIPSR __ASM("ipsr"); - return(__regIPSR); + register uint32_t __regIPSR __ASM("ipsr"); + return (__regIPSR); } - /** \brief Get APSR Register This function returns the content of the APSR Register. @@ -102,11 +97,10 @@ __STATIC_INLINE uint32_t __get_IPSR(void) */ __STATIC_INLINE uint32_t __get_APSR(void) { - register uint32_t __regAPSR __ASM("apsr"); - return(__regAPSR); + register uint32_t __regAPSR __ASM("apsr"); + return (__regAPSR); } - /** \brief Get xPSR Register This function returns the content of the xPSR Register. @@ -115,11 +109,10 @@ __STATIC_INLINE uint32_t __get_APSR(void) */ __STATIC_INLINE uint32_t __get_xPSR(void) { - register uint32_t __regXPSR __ASM("xpsr"); - return(__regXPSR); + register uint32_t __regXPSR __ASM("xpsr"); + return (__regXPSR); } - /** \brief Get Process Stack Pointer This function returns the current value of the Process Stack Pointer (PSP). @@ -128,11 +121,10 @@ __STATIC_INLINE uint32_t __get_xPSR(void) */ __STATIC_INLINE uint32_t __get_PSP(void) { - register uint32_t __regProcessStackPointer __ASM("psp"); - return(__regProcessStackPointer); + register uint32_t __regProcessStackPointer __ASM("psp"); + return (__regProcessStackPointer); } - /** \brief Set Process Stack Pointer This function assigns the given value to the Process Stack Pointer (PSP). @@ -141,11 +133,10 @@ __STATIC_INLINE uint32_t __get_PSP(void) */ __STATIC_INLINE void __set_PSP(uint32_t topOfProcStack) { - register uint32_t __regProcessStackPointer __ASM("psp"); - __regProcessStackPointer = topOfProcStack; + register uint32_t __regProcessStackPointer __ASM("psp"); + __regProcessStackPointer = topOfProcStack; } - /** \brief Get Main Stack Pointer This function returns the current value of the Main Stack Pointer (MSP). @@ -154,11 +145,10 @@ __STATIC_INLINE void __set_PSP(uint32_t topOfProcStack) */ __STATIC_INLINE uint32_t __get_MSP(void) { - register uint32_t __regMainStackPointer __ASM("msp"); - return(__regMainStackPointer); + register uint32_t __regMainStackPointer __ASM("msp"); + return (__regMainStackPointer); } - /** \brief Set Main Stack Pointer This function assigns the given value to the Main Stack Pointer (MSP). @@ -167,11 +157,10 @@ __STATIC_INLINE uint32_t __get_MSP(void) */ __STATIC_INLINE void __set_MSP(uint32_t topOfMainStack) { - register uint32_t __regMainStackPointer __ASM("msp"); - __regMainStackPointer = topOfMainStack; + register uint32_t __regMainStackPointer __ASM("msp"); + __regMainStackPointer = topOfMainStack; } - /** \brief Get Priority Mask This function returns the current state of the priority mask bit from the Priority Mask Register. @@ -180,11 +169,10 @@ __STATIC_INLINE void __set_MSP(uint32_t topOfMainStack) */ __STATIC_INLINE uint32_t __get_PRIMASK(void) { - register uint32_t __regPriMask __ASM("primask"); - return(__regPriMask); + register uint32_t __regPriMask __ASM("primask"); + return (__regPriMask); } - /** \brief Set Priority Mask This function assigns the given value to the Priority Mask Register. @@ -193,28 +181,25 @@ __STATIC_INLINE uint32_t __get_PRIMASK(void) */ __STATIC_INLINE void __set_PRIMASK(uint32_t priMask) { - register uint32_t __regPriMask __ASM("primask"); - __regPriMask = (priMask); + register uint32_t __regPriMask __ASM("primask"); + __regPriMask = (priMask); } - -#if (__CORTEX_M >= 0x03) || (__CORTEX_SC >= 300) +#if (__CORTEX_M >= 0x03) || (__CORTEX_SC >= 300) /** \brief Enable FIQ This function enables FIQ interrupts by clearing the F-bit in the CPSR. Can only be executed in Privileged modes. */ -#define __enable_fault_irq __enable_fiq - +#define __enable_fault_irq __enable_fiq /** \brief Disable FIQ This function disables FIQ interrupts by setting the F-bit in the CPSR. Can only be executed in Privileged modes. */ -#define __disable_fault_irq __disable_fiq - +#define __disable_fault_irq __disable_fiq /** \brief Get Base Priority @@ -222,13 +207,12 @@ __STATIC_INLINE void __set_PRIMASK(uint32_t priMask) \return Base Priority register value */ -__STATIC_INLINE uint32_t __get_BASEPRI(void) +__STATIC_INLINE uint32_t __get_BASEPRI(void) { - register uint32_t __regBasePri __ASM("basepri"); - return(__regBasePri); + register uint32_t __regBasePri __ASM("basepri"); + return (__regBasePri); } - /** \brief Set Base Priority This function assigns the given value to the Base Priority register. @@ -237,11 +221,10 @@ __STATIC_INLINE uint32_t __get_BASEPRI(void) */ __STATIC_INLINE void __set_BASEPRI(uint32_t basePri) { - register uint32_t __regBasePri __ASM("basepri"); - __regBasePri = (basePri & 0xff); + register uint32_t __regBasePri __ASM("basepri"); + __regBasePri = (basePri & 0xff); } - /** \brief Get Fault Mask This function returns the current value of the Fault Mask register. @@ -250,11 +233,10 @@ __STATIC_INLINE void __set_BASEPRI(uint32_t basePri) */ __STATIC_INLINE uint32_t __get_FAULTMASK(void) { - register uint32_t __regFaultMask __ASM("faultmask"); - return(__regFaultMask); + register uint32_t __regFaultMask __ASM("faultmask"); + return (__regFaultMask); } - /** \brief Set Fault Mask This function assigns the given value to the Fault Mask register. @@ -263,14 +245,13 @@ __STATIC_INLINE uint32_t __get_FAULTMASK(void) */ __STATIC_INLINE void __set_FAULTMASK(uint32_t faultMask) { - register uint32_t __regFaultMask __ASM("faultmask"); - __regFaultMask = (faultMask & (uint32_t)1); + register uint32_t __regFaultMask __ASM("faultmask"); + __regFaultMask = (faultMask & (uint32_t)1); } #endif /* (__CORTEX_M >= 0x03) || (__CORTEX_SC >= 300) */ - -#if (__CORTEX_M == 0x04) || (__CORTEX_M == 0x07) +#if (__CORTEX_M == 0x04) || (__CORTEX_M == 0x07) /** \brief Get FPSCR @@ -281,14 +262,13 @@ __STATIC_INLINE void __set_FAULTMASK(uint32_t faultMask) __STATIC_INLINE uint32_t __get_FPSCR(void) { #if (__FPU_PRESENT == 1) && (__FPU_USED == 1) - register uint32_t __regfpscr __ASM("fpscr"); - return(__regfpscr); + register uint32_t __regfpscr __ASM("fpscr"); + return (__regfpscr); #else - return(0); + return (0); #endif } - /** \brief Set FPSCR This function assigns the given value to the Floating Point Status/Control register. @@ -298,15 +278,14 @@ __STATIC_INLINE uint32_t __get_FPSCR(void) __STATIC_INLINE void __set_FPSCR(uint32_t fpscr) { #if (__FPU_PRESENT == 1) && (__FPU_USED == 1) - register uint32_t __regfpscr __ASM("fpscr"); - __regfpscr = (fpscr); + register uint32_t __regfpscr __ASM("fpscr"); + __regfpscr = (fpscr); #endif } #endif /* (__CORTEX_M == 0x04) || (__CORTEX_M == 0x07) */ - -#elif defined ( __GNUC__ ) /*------------------ GNU Compiler ---------------------*/ +#elif defined(__GNUC__) /*------------------ GNU Compiler ---------------------*/ /* GNU gcc specific functions */ /** \brief Enable IRQ Interrupts @@ -314,257 +293,277 @@ __STATIC_INLINE void __set_FPSCR(uint32_t fpscr) This function enables IRQ interrupts by clearing the I-bit in the CPSR. Can only be executed in Privileged modes. */ -__attribute__( ( always_inline ) ) __STATIC_INLINE void __enable_irq(void) +__attribute__((always_inline)) __STATIC_INLINE void __enable_irq(void) { - __ASM volatile ("cpsie i" : : : "memory"); + __ASM volatile("cpsie i" + : + : + : "memory"); } - /** \brief Disable IRQ Interrupts This function disables IRQ interrupts by setting the I-bit in the CPSR. Can only be executed in Privileged modes. */ -__attribute__( ( always_inline ) ) __STATIC_INLINE void __disable_irq(void) +__attribute__((always_inline)) __STATIC_INLINE void __disable_irq(void) { - __ASM volatile ("cpsid i" : : : "memory"); + __ASM volatile("cpsid i" + : + : + : "memory"); } - /** \brief Get Control Register This function returns the content of the Control Register. \return Control Register value */ -__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_CONTROL(void) +__attribute__((always_inline)) __STATIC_INLINE uint32_t __get_CONTROL(void) { - uint32_t result; + uint32_t result; - __ASM volatile ("MRS %0, control" : "=r" (result) ); - return(result); + __ASM volatile("MRS %0, control" + : "=r"(result)); + return (result); } - /** \brief Set Control Register This function writes the given value to the Control Register. \param [in] control Control Register value to set */ -__attribute__( ( always_inline ) ) __STATIC_INLINE void __set_CONTROL(uint32_t control) +__attribute__((always_inline)) __STATIC_INLINE void __set_CONTROL(uint32_t control) { - __ASM volatile ("MSR control, %0" : : "r" (control) : "memory"); + __ASM volatile("MSR control, %0" + : + : "r"(control) + : "memory"); } - /** \brief Get IPSR Register This function returns the content of the IPSR Register. \return IPSR Register value */ -__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_IPSR(void) +__attribute__((always_inline)) __STATIC_INLINE uint32_t __get_IPSR(void) { - uint32_t result; + uint32_t result; - __ASM volatile ("MRS %0, ipsr" : "=r" (result) ); - return(result); + __ASM volatile("MRS %0, ipsr" + : "=r"(result)); + return (result); } - /** \brief Get APSR Register This function returns the content of the APSR Register. \return APSR Register value */ -__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_APSR(void) +__attribute__((always_inline)) __STATIC_INLINE uint32_t __get_APSR(void) { - uint32_t result; + uint32_t result; - __ASM volatile ("MRS %0, apsr" : "=r" (result) ); - return(result); + __ASM volatile("MRS %0, apsr" + : "=r"(result)); + return (result); } - /** \brief Get xPSR Register This function returns the content of the xPSR Register. \return xPSR Register value */ -__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_xPSR(void) +__attribute__((always_inline)) __STATIC_INLINE uint32_t __get_xPSR(void) { - uint32_t result; + uint32_t result; - __ASM volatile ("MRS %0, xpsr" : "=r" (result) ); - return(result); + __ASM volatile("MRS %0, xpsr" + : "=r"(result)); + return (result); } - /** \brief Get Process Stack Pointer This function returns the current value of the Process Stack Pointer (PSP). \return PSP Register value */ -__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_PSP(void) +__attribute__((always_inline)) __STATIC_INLINE uint32_t __get_PSP(void) { - register uint32_t result; + register uint32_t result; - __ASM volatile ("MRS %0, psp\n" : "=r" (result) ); - return(result); + __ASM volatile("MRS %0, psp\n" + : "=r"(result)); + return (result); } - /** \brief Set Process Stack Pointer This function assigns the given value to the Process Stack Pointer (PSP). \param [in] topOfProcStack Process Stack Pointer value to set */ -__attribute__( ( always_inline ) ) __STATIC_INLINE void __set_PSP(uint32_t topOfProcStack) +__attribute__((always_inline)) __STATIC_INLINE void __set_PSP(uint32_t topOfProcStack) { - __ASM volatile ("MSR psp, %0\n" : : "r" (topOfProcStack) : "sp"); + __ASM volatile("MSR psp, %0\n" + : + : "r"(topOfProcStack) + : "sp"); } - /** \brief Get Main Stack Pointer This function returns the current value of the Main Stack Pointer (MSP). \return MSP Register value */ -__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_MSP(void) +__attribute__((always_inline)) __STATIC_INLINE uint32_t __get_MSP(void) { - register uint32_t result; + register uint32_t result; - __ASM volatile ("MRS %0, msp\n" : "=r" (result) ); - return(result); + __ASM volatile("MRS %0, msp\n" + : "=r"(result)); + return (result); } - /** \brief Set Main Stack Pointer This function assigns the given value to the Main Stack Pointer (MSP). \param [in] topOfMainStack Main Stack Pointer value to set */ -__attribute__( ( always_inline ) ) __STATIC_INLINE void __set_MSP(uint32_t topOfMainStack) +__attribute__((always_inline)) __STATIC_INLINE void __set_MSP(uint32_t topOfMainStack) { - __ASM volatile ("MSR msp, %0\n" : : "r" (topOfMainStack) : "sp"); + __ASM volatile("MSR msp, %0\n" + : + : "r"(topOfMainStack) + : "sp"); } - /** \brief Get Priority Mask This function returns the current state of the priority mask bit from the Priority Mask Register. \return Priority Mask value */ -__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_PRIMASK(void) +__attribute__((always_inline)) __STATIC_INLINE uint32_t __get_PRIMASK(void) { - uint32_t result; + uint32_t result; - __ASM volatile ("MRS %0, primask" : "=r" (result) ); - return(result); + __ASM volatile("MRS %0, primask" + : "=r"(result)); + return (result); } - /** \brief Set Priority Mask This function assigns the given value to the Priority Mask Register. \param [in] priMask Priority Mask */ -__attribute__( ( always_inline ) ) __STATIC_INLINE void __set_PRIMASK(uint32_t priMask) +__attribute__((always_inline)) __STATIC_INLINE void __set_PRIMASK(uint32_t priMask) { - __ASM volatile ("MSR primask, %0" : : "r" (priMask) : "memory"); + __ASM volatile("MSR primask, %0" + : + : "r"(priMask) + : "memory"); } - -#if (__CORTEX_M >= 0x03) +#if (__CORTEX_M >= 0x03) /** \brief Enable FIQ This function enables FIQ interrupts by clearing the F-bit in the CPSR. Can only be executed in Privileged modes. */ -__attribute__( ( always_inline ) ) __STATIC_INLINE void __enable_fault_irq(void) +__attribute__((always_inline)) __STATIC_INLINE void __enable_fault_irq(void) { - __ASM volatile ("cpsie f" : : : "memory"); + __ASM volatile("cpsie f" + : + : + : "memory"); } - /** \brief Disable FIQ This function disables FIQ interrupts by setting the F-bit in the CPSR. Can only be executed in Privileged modes. */ -__attribute__( ( always_inline ) ) __STATIC_INLINE void __disable_fault_irq(void) +__attribute__((always_inline)) __STATIC_INLINE void __disable_fault_irq(void) { - __ASM volatile ("cpsid f" : : : "memory"); + __ASM volatile("cpsid f" + : + : + : "memory"); } - /** \brief Get Base Priority This function returns the current value of the Base Priority register. \return Base Priority register value */ -__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_BASEPRI(void) +__attribute__((always_inline)) __STATIC_INLINE uint32_t __get_BASEPRI(void) { - uint32_t result; + uint32_t result; - __ASM volatile ("MRS %0, basepri_max" : "=r" (result) ); - return(result); + __ASM volatile("MRS %0, basepri_max" + : "=r"(result)); + return (result); } - /** \brief Set Base Priority This function assigns the given value to the Base Priority register. \param [in] basePri Base Priority value to set */ -__attribute__( ( always_inline ) ) __STATIC_INLINE void __set_BASEPRI(uint32_t value) +__attribute__((always_inline)) __STATIC_INLINE void __set_BASEPRI(uint32_t value) { - __ASM volatile ("MSR basepri, %0" : : "r" (value) : "memory"); + __ASM volatile("MSR basepri, %0" + : + : "r"(value) + : "memory"); } - /** \brief Get Fault Mask This function returns the current value of the Fault Mask register. \return Fault Mask register value */ -__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_FAULTMASK(void) +__attribute__((always_inline)) __STATIC_INLINE uint32_t __get_FAULTMASK(void) { - uint32_t result; + uint32_t result; - __ASM volatile ("MRS %0, faultmask" : "=r" (result) ); - return(result); + __ASM volatile("MRS %0, faultmask" + : "=r"(result)); + return (result); } - /** \brief Set Fault Mask This function assigns the given value to the Fault Mask register. \param [in] faultMask Fault Mask value to set */ -__attribute__( ( always_inline ) ) __STATIC_INLINE void __set_FAULTMASK(uint32_t faultMask) +__attribute__((always_inline)) __STATIC_INLINE void __set_FAULTMASK(uint32_t faultMask) { - __ASM volatile ("MSR faultmask, %0" : : "r" (faultMask) : "memory"); + __ASM volatile("MSR faultmask, %0" + : + : "r"(faultMask) + : "memory"); } #endif /* (__CORTEX_M >= 0x03) */ - -#if (__CORTEX_M == 0x04) || (__CORTEX_M == 0x07) +#if (__CORTEX_M == 0x04) || (__CORTEX_M == 0x07) /** \brief Get FPSCR @@ -572,52 +571,52 @@ __attribute__( ( always_inline ) ) __STATIC_INLINE void __set_FAULTMASK(uint32_t \return Floating Point Status/Control register value */ -__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_FPSCR(void) +__attribute__((always_inline)) __STATIC_INLINE uint32_t __get_FPSCR(void) { #if (__FPU_PRESENT == 1) && (__FPU_USED == 1) - uint32_t result; - - /* Empty asm statement works as a scheduling barrier */ - __ASM volatile (""); - __ASM volatile ("VMRS %0, fpscr" : "=r" (result) ); - __ASM volatile (""); - return(result); + uint32_t result; + + /* Empty asm statement works as a scheduling barrier */ + __ASM volatile(""); + __ASM volatile("VMRS %0, fpscr" + : "=r"(result)); + __ASM volatile(""); + return (result); #else - return(0); + return (0); #endif } - /** \brief Set FPSCR This function assigns the given value to the Floating Point Status/Control register. \param [in] fpscr Floating Point Status/Control value to set */ -__attribute__( ( always_inline ) ) __STATIC_INLINE void __set_FPSCR(uint32_t fpscr) +__attribute__((always_inline)) __STATIC_INLINE void __set_FPSCR(uint32_t fpscr) { #if (__FPU_PRESENT == 1) && (__FPU_USED == 1) - /* Empty asm statement works as a scheduling barrier */ - __ASM volatile (""); - __ASM volatile ("VMSR fpscr, %0" : : "r" (fpscr) : "vfpcc"); - __ASM volatile (""); + /* Empty asm statement works as a scheduling barrier */ + __ASM volatile(""); + __ASM volatile("VMSR fpscr, %0" + : + : "r"(fpscr) + : "vfpcc"); + __ASM volatile(""); #endif } #endif /* (__CORTEX_M == 0x04) || (__CORTEX_M == 0x07) */ - -#elif defined ( __ICCARM__ ) /*------------------ ICC Compiler -------------------*/ +#elif defined(__ICCARM__) /*------------------ ICC Compiler -------------------*/ /* IAR iccarm specific functions */ #include - -#elif defined ( __TMS470__ ) /*---------------- TI CCS Compiler ------------------*/ +#elif defined(__TMS470__) /*---------------- TI CCS Compiler ------------------*/ /* TI CCS specific functions */ #include - -#elif defined ( __TASKING__ ) /*------------------ TASKING Compiler --------------*/ +#elif defined(__TASKING__) /*------------------ TASKING Compiler --------------*/ /* TASKING carm specific functions */ /* * The CMSIS functions have been implemented as intrinsics in the compiler. @@ -625,8 +624,7 @@ __attribute__( ( always_inline ) ) __STATIC_INLINE void __set_FPSCR(uint32_t fps * Including the CMSIS ones. */ - -#elif defined ( __CSMC__ ) /*------------------ COSMIC Compiler -------------------*/ +#elif defined(__CSMC__) /*------------------ COSMIC Compiler -------------------*/ /* Cosmic specific functions */ #include diff --git a/bsp/swm320-lq100/Libraries/CMSIS/CoreSupport/core_cmInstr.h b/bsp/swm320-lq100/Libraries/CMSIS/CoreSupport/core_cmInstr.h index d14110b2ab..6d1a9e9f8f 100644 --- a/bsp/swm320-lq100/Libraries/CMSIS/CoreSupport/core_cmInstr.h +++ b/bsp/swm320-lq100/Libraries/CMSIS/CoreSupport/core_cmInstr.h @@ -1,4 +1,4 @@ -/**************************************************************************//** +/**************************************************************************/ /** * @file core_cmInstr.h * @brief CMSIS Cortex-M Core Instruction Access Header File * @version V4.00 @@ -34,54 +34,47 @@ POSSIBILITY OF SUCH DAMAGE. ---------------------------------------------------------------------------*/ - #ifndef __CORE_CMINSTR_H #define __CORE_CMINSTR_H - /* ########################## Core Instruction Access ######################### */ /** \defgroup CMSIS_Core_InstructionInterface CMSIS Core Instruction Interface Access to dedicated instructions @{ */ -#if defined ( __CC_ARM ) /*------------------RealView Compiler -----------------*/ +#if defined(__CC_ARM) /*------------------RealView Compiler -----------------*/ /* ARM armcc specific functions */ #if (__ARMCC_VERSION < 400677) - #error "Please use ARM Compiler Toolchain V4.0.677 or later!" +#error "Please use ARM Compiler Toolchain V4.0.677 or later!" #endif - /** \brief No Operation No Operation does nothing. This instruction can be used for code alignment purposes. */ -#define __NOP __nop - +#define __NOP __nop /** \brief Wait For Interrupt Wait For Interrupt is a hint instruction that suspends execution until one of a number of events occurs. */ -#define __WFI __wfi - +#define __WFI __wfi /** \brief Wait For Event Wait For Event is a hint instruction that permits the processor to enter a low-power state until one of a number of events occurs. */ -#define __WFE __wfe - +#define __WFE __wfe /** \brief Send Event Send Event is a hint instruction. It causes an event to be signaled to the CPU. */ -#define __SEV __sev - +#define __SEV __sev /** \brief Instruction Synchronization Barrier @@ -89,24 +82,21 @@ so that all instructions following the ISB are fetched from cache or memory, after the instruction has been completed. */ -#define __ISB() __isb(0xF) - +#define __ISB() __isb(0xF) /** \brief Data Synchronization Barrier This function acts as a special kind of Data Memory Barrier. It completes when all explicit memory accesses before this instruction complete. */ -#define __DSB() __dsb(0xF) - +#define __DSB() __dsb(0xF) /** \brief Data Memory Barrier This function ensures the apparent order of the explicit memory operations before and after the instruction, without ensuring their completion. */ -#define __DMB() __dmb(0xF) - +#define __DMB() __dmb(0xF) /** \brief Reverse byte order (32 bit) @@ -115,8 +105,7 @@ \param [in] value Value to reverse \return Reversed value */ -#define __REV __rev - +#define __REV __rev /** \brief Reverse byte order (16 bit) @@ -128,8 +117,8 @@ #ifndef __NO_EMBEDDED_ASM __attribute__((section(".rev16_text"))) __STATIC_INLINE __ASM uint32_t __REV16(uint32_t value) { - rev16 r0, r0 - bx lr + rev16 r0, r0 + bx lr } #endif @@ -143,12 +132,11 @@ __attribute__((section(".rev16_text"))) __STATIC_INLINE __ASM uint32_t __REV16(u #ifndef __NO_EMBEDDED_ASM __attribute__((section(".revsh_text"))) __STATIC_INLINE __ASM int32_t __REVSH(int32_t value) { - revsh r0, r0 - bx lr + revsh r0, r0 + bx lr } #endif - /** \brief Rotate Right in unsigned value (32 bit) This function Rotate Right (immediate) provides the value of the contents of a register rotated by a variable number of bits. @@ -157,8 +145,7 @@ __attribute__((section(".revsh_text"))) __STATIC_INLINE __ASM int32_t __REVSH(in \param [in] value Number of Bits to rotate \return Rotated value */ -#define __ROR __ror - +#define __ROR __ror /** \brief Breakpoint @@ -168,10 +155,9 @@ __attribute__((section(".revsh_text"))) __STATIC_INLINE __ASM int32_t __REVSH(in \param [in] value is ignored by the processor. If required, a debugger can use it to store additional information about the breakpoint. */ -#define __BKPT(value) __breakpoint(value) +#define __BKPT(value) __breakpoint(value) - -#if (__CORTEX_M >= 0x03) || (__CORTEX_SC >= 300) +#if (__CORTEX_M >= 0x03) || (__CORTEX_SC >= 300) /** \brief Reverse bit order of value @@ -180,8 +166,7 @@ __attribute__((section(".revsh_text"))) __STATIC_INLINE __ASM int32_t __REVSH(in \param [in] value Value to reverse \return Reversed value */ -#define __RBIT __rbit - +#define __RBIT __rbit /** \brief LDR Exclusive (8 bit) @@ -190,8 +175,7 @@ __attribute__((section(".revsh_text"))) __STATIC_INLINE __ASM int32_t __REVSH(in \param [in] ptr Pointer to data \return value of type uint8_t at (*ptr) */ -#define __LDREXB(ptr) ((uint8_t ) __ldrex(ptr)) - +#define __LDREXB(ptr) ((uint8_t)__ldrex(ptr)) /** \brief LDR Exclusive (16 bit) @@ -200,8 +184,7 @@ __attribute__((section(".revsh_text"))) __STATIC_INLINE __ASM int32_t __REVSH(in \param [in] ptr Pointer to data \return value of type uint16_t at (*ptr) */ -#define __LDREXH(ptr) ((uint16_t) __ldrex(ptr)) - +#define __LDREXH(ptr) ((uint16_t)__ldrex(ptr)) /** \brief LDR Exclusive (32 bit) @@ -210,8 +193,7 @@ __attribute__((section(".revsh_text"))) __STATIC_INLINE __ASM int32_t __REVSH(in \param [in] ptr Pointer to data \return value of type uint32_t at (*ptr) */ -#define __LDREXW(ptr) ((uint32_t ) __ldrex(ptr)) - +#define __LDREXW(ptr) ((uint32_t)__ldrex(ptr)) /** \brief STR Exclusive (8 bit) @@ -222,8 +204,7 @@ __attribute__((section(".revsh_text"))) __STATIC_INLINE __ASM int32_t __REVSH(in \return 0 Function succeeded \return 1 Function failed */ -#define __STREXB(value, ptr) __strex(value, ptr) - +#define __STREXB(value, ptr) __strex(value, ptr) /** \brief STR Exclusive (16 bit) @@ -234,8 +215,7 @@ __attribute__((section(".revsh_text"))) __STATIC_INLINE __ASM int32_t __REVSH(in \return 0 Function succeeded \return 1 Function failed */ -#define __STREXH(value, ptr) __strex(value, ptr) - +#define __STREXH(value, ptr) __strex(value, ptr) /** \brief STR Exclusive (32 bit) @@ -246,16 +226,14 @@ __attribute__((section(".revsh_text"))) __STATIC_INLINE __ASM int32_t __REVSH(in \return 0 Function succeeded \return 1 Function failed */ -#define __STREXW(value, ptr) __strex(value, ptr) - +#define __STREXW(value, ptr) __strex(value, ptr) /** \brief Remove the exclusive lock This function removes the exclusive lock which is created by LDREX. */ -#define __CLREX __clrex - +#define __CLREX __clrex /** \brief Signed Saturate @@ -265,8 +243,7 @@ __attribute__((section(".revsh_text"))) __STATIC_INLINE __ASM int32_t __REVSH(in \param [in] sat Bit position to saturate to (1..32) \return Saturated value */ -#define __SSAT __ssat - +#define __SSAT __ssat /** \brief Unsigned Saturate @@ -276,8 +253,7 @@ __attribute__((section(".revsh_text"))) __STATIC_INLINE __ASM int32_t __REVSH(in \param [in] sat Bit position to saturate to (0..31) \return Saturated value */ -#define __USAT __usat - +#define __USAT __usat /** \brief Count leading zeros @@ -286,8 +262,7 @@ __attribute__((section(".revsh_text"))) __STATIC_INLINE __ASM int32_t __REVSH(in \param [in] value Value to count the leading zeros \return number of leading zeros in value */ -#define __CLZ __clz - +#define __CLZ __clz /** \brief Rotate Right with Extend (32 bit) @@ -299,12 +274,11 @@ __attribute__((section(".revsh_text"))) __STATIC_INLINE __ASM int32_t __REVSH(in #ifndef __NO_EMBEDDED_ASM __attribute__((section(".rrx_text"))) __STATIC_INLINE __ASM uint32_t __RRX(uint32_t value) { - rrx r0, r0 - bx lr + rrx r0, r0 + bx lr } #endif - /** \brief LDRT Unprivileged (8 bit) This function executes a Unprivileged LDRT instruction for 8 bit value. @@ -312,8 +286,7 @@ __attribute__((section(".rrx_text"))) __STATIC_INLINE __ASM uint32_t __RRX(uint3 \param [in] ptr Pointer to data \return value of type uint8_t at (*ptr) */ -#define __LDRBT(ptr) ((uint8_t ) __ldrt(ptr)) - +#define __LDRBT(ptr) ((uint8_t)__ldrt(ptr)) /** \brief LDRT Unprivileged (16 bit) @@ -322,8 +295,7 @@ __attribute__((section(".rrx_text"))) __STATIC_INLINE __ASM uint32_t __RRX(uint3 \param [in] ptr Pointer to data \return value of type uint16_t at (*ptr) */ -#define __LDRHT(ptr) ((uint16_t) __ldrt(ptr)) - +#define __LDRHT(ptr) ((uint16_t)__ldrt(ptr)) /** \brief LDRT Unprivileged (32 bit) @@ -332,8 +304,7 @@ __attribute__((section(".rrx_text"))) __STATIC_INLINE __ASM uint32_t __RRX(uint3 \param [in] ptr Pointer to data \return value of type uint32_t at (*ptr) */ -#define __LDRT(ptr) ((uint32_t ) __ldrt(ptr)) - +#define __LDRT(ptr) ((uint32_t)__ldrt(ptr)) /** \brief STRT Unprivileged (8 bit) @@ -342,8 +313,7 @@ __attribute__((section(".rrx_text"))) __STATIC_INLINE __ASM uint32_t __RRX(uint3 \param [in] value Value to store \param [in] ptr Pointer to location */ -#define __STRBT(value, ptr) __strt(value, ptr) - +#define __STRBT(value, ptr) __strt(value, ptr) /** \brief STRT Unprivileged (16 bit) @@ -352,8 +322,7 @@ __attribute__((section(".rrx_text"))) __STATIC_INLINE __ASM uint32_t __RRX(uint3 \param [in] value Value to store \param [in] ptr Pointer to location */ -#define __STRHT(value, ptr) __strt(value, ptr) - +#define __STRHT(value, ptr) __strt(value, ptr) /** \brief STRT Unprivileged (32 bit) @@ -362,101 +331,93 @@ __attribute__((section(".rrx_text"))) __STATIC_INLINE __ASM uint32_t __RRX(uint3 \param [in] value Value to store \param [in] ptr Pointer to location */ -#define __STRT(value, ptr) __strt(value, ptr) +#define __STRT(value, ptr) __strt(value, ptr) #endif /* (__CORTEX_M >= 0x03) || (__CORTEX_SC >= 300) */ - -#elif defined ( __GNUC__ ) /*------------------ GNU Compiler ---------------------*/ +#elif defined(__GNUC__) /*------------------ GNU Compiler ---------------------*/ /* GNU gcc specific functions */ /* Define macros for porting to both thumb1 and thumb2. * For thumb1, use low register (r0-r7), specified by constrant "l" * Otherwise, use general registers, specified by constrant "r" */ -#if defined (__thumb__) && !defined (__thumb2__) -#define __CMSIS_GCC_OUT_REG(r) "=l" (r) -#define __CMSIS_GCC_USE_REG(r) "l" (r) +#if defined(__thumb__) && !defined(__thumb2__) +#define __CMSIS_GCC_OUT_REG(r) "=l"(r) +#define __CMSIS_GCC_USE_REG(r) "l"(r) #else -#define __CMSIS_GCC_OUT_REG(r) "=r" (r) -#define __CMSIS_GCC_USE_REG(r) "r" (r) +#define __CMSIS_GCC_OUT_REG(r) "=r"(r) +#define __CMSIS_GCC_USE_REG(r) "r"(r) #endif /** \brief No Operation No Operation does nothing. This instruction can be used for code alignment purposes. */ -__attribute__( ( always_inline ) ) __STATIC_INLINE void __NOP(void) +__attribute__((always_inline)) __STATIC_INLINE void __NOP(void) { - __ASM volatile ("nop"); + __ASM volatile("nop"); } - /** \brief Wait For Interrupt Wait For Interrupt is a hint instruction that suspends execution until one of a number of events occurs. */ -__attribute__( ( always_inline ) ) __STATIC_INLINE void __WFI(void) +__attribute__((always_inline)) __STATIC_INLINE void __WFI(void) { - __ASM volatile ("wfi"); + __ASM volatile("wfi"); } - /** \brief Wait For Event Wait For Event is a hint instruction that permits the processor to enter a low-power state until one of a number of events occurs. */ -__attribute__( ( always_inline ) ) __STATIC_INLINE void __WFE(void) +__attribute__((always_inline)) __STATIC_INLINE void __WFE(void) { - __ASM volatile ("wfe"); + __ASM volatile("wfe"); } - /** \brief Send Event Send Event is a hint instruction. It causes an event to be signaled to the CPU. */ -__attribute__( ( always_inline ) ) __STATIC_INLINE void __SEV(void) +__attribute__((always_inline)) __STATIC_INLINE void __SEV(void) { - __ASM volatile ("sev"); + __ASM volatile("sev"); } - /** \brief Instruction Synchronization Barrier Instruction Synchronization Barrier flushes the pipeline in the processor, so that all instructions following the ISB are fetched from cache or memory, after the instruction has been completed. */ -__attribute__( ( always_inline ) ) __STATIC_INLINE void __ISB(void) +__attribute__((always_inline)) __STATIC_INLINE void __ISB(void) { - __ASM volatile ("isb"); + __ASM volatile("isb"); } - /** \brief Data Synchronization Barrier This function acts as a special kind of Data Memory Barrier. It completes when all explicit memory accesses before this instruction complete. */ -__attribute__( ( always_inline ) ) __STATIC_INLINE void __DSB(void) +__attribute__((always_inline)) __STATIC_INLINE void __DSB(void) { - __ASM volatile ("dsb"); + __ASM volatile("dsb"); } - /** \brief Data Memory Barrier This function ensures the apparent order of the explicit memory operations before and after the instruction, without ensuring their completion. */ -__attribute__( ( always_inline ) ) __STATIC_INLINE void __DMB(void) +__attribute__((always_inline)) __STATIC_INLINE void __DMB(void) { - __ASM volatile ("dmb"); + __ASM volatile("dmb"); } - /** \brief Reverse byte order (32 bit) This function reverses the byte order in integer value. @@ -464,19 +425,20 @@ __attribute__( ( always_inline ) ) __STATIC_INLINE void __DMB(void) \param [in] value Value to reverse \return Reversed value */ -__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __REV(uint32_t value) +__attribute__((always_inline)) __STATIC_INLINE uint32_t __REV(uint32_t value) { #if (__GNUC__ > 4) || (__GNUC__ == 4 && __GNUC_MINOR__ >= 5) - return __builtin_bswap32(value); + return __builtin_bswap32(value); #else - uint32_t result; + uint32_t result; - __ASM volatile ("rev %0, %1" : __CMSIS_GCC_OUT_REG (result) : __CMSIS_GCC_USE_REG (value) ); - return(result); + __ASM volatile("rev %0, %1" + : __CMSIS_GCC_OUT_REG(result) + : __CMSIS_GCC_USE_REG(value)); + return (result); #endif } - /** \brief Reverse byte order (16 bit) This function reverses the byte order in two unsigned short values. @@ -484,15 +446,16 @@ __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __REV(uint32_t value \param [in] value Value to reverse \return Reversed value */ -__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __REV16(uint32_t value) +__attribute__((always_inline)) __STATIC_INLINE uint32_t __REV16(uint32_t value) { - uint32_t result; + uint32_t result; - __ASM volatile ("rev16 %0, %1" : __CMSIS_GCC_OUT_REG (result) : __CMSIS_GCC_USE_REG (value) ); - return(result); + __ASM volatile("rev16 %0, %1" + : __CMSIS_GCC_OUT_REG(result) + : __CMSIS_GCC_USE_REG(value)); + return (result); } - /** \brief Reverse byte order in signed short value This function reverses the byte order in a signed short value with sign extension to integer. @@ -500,19 +463,20 @@ __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __REV16(uint32_t val \param [in] value Value to reverse \return Reversed value */ -__attribute__( ( always_inline ) ) __STATIC_INLINE int32_t __REVSH(int32_t value) +__attribute__((always_inline)) __STATIC_INLINE int32_t __REVSH(int32_t value) { #if (__GNUC__ > 4) || (__GNUC__ == 4 && __GNUC_MINOR__ >= 8) - return (short)__builtin_bswap16(value); + return (short)__builtin_bswap16(value); #else - uint32_t result; + uint32_t result; - __ASM volatile ("revsh %0, %1" : __CMSIS_GCC_OUT_REG (result) : __CMSIS_GCC_USE_REG (value) ); - return(result); + __ASM volatile("revsh %0, %1" + : __CMSIS_GCC_OUT_REG(result) + : __CMSIS_GCC_USE_REG(value)); + return (result); #endif } - /** \brief Rotate Right in unsigned value (32 bit) This function Rotate Right (immediate) provides the value of the contents of a register rotated by a variable number of bits. @@ -521,12 +485,11 @@ __attribute__( ( always_inline ) ) __STATIC_INLINE int32_t __REVSH(int32_t value \param [in] value Number of Bits to rotate \return Rotated value */ -__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __ROR(uint32_t op1, uint32_t op2) +__attribute__((always_inline)) __STATIC_INLINE uint32_t __ROR(uint32_t op1, uint32_t op2) { - return (op1 >> op2) | (op1 << (32 - op2)); + return (op1 >> op2) | (op1 << (32 - op2)); } - /** \brief Breakpoint This function causes the processor to enter Debug state. @@ -535,10 +498,9 @@ __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __ROR(uint32_t op1, \param [in] value is ignored by the processor. If required, a debugger can use it to store additional information about the breakpoint. */ -#define __BKPT(value) __ASM volatile ("bkpt "#value) - +#define __BKPT(value) __ASM volatile("bkpt " #value) -#if (__CORTEX_M >= 0x03) || (__CORTEX_SC >= 300) +#if (__CORTEX_M >= 0x03) || (__CORTEX_SC >= 300) /** \brief Reverse bit order of value @@ -547,15 +509,16 @@ __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __ROR(uint32_t op1, \param [in] value Value to reverse \return Reversed value */ -__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __RBIT(uint32_t value) +__attribute__((always_inline)) __STATIC_INLINE uint32_t __RBIT(uint32_t value) { - uint32_t result; + uint32_t result; - __ASM volatile ("rbit %0, %1" : "=r" (result) : "r" (value) ); - return(result); + __ASM volatile("rbit %0, %1" + : "=r"(result) + : "r"(value)); + return (result); } - /** \brief LDR Exclusive (8 bit) This function executes a exclusive LDR instruction for 8 bit value. @@ -563,22 +526,26 @@ __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __RBIT(uint32_t valu \param [in] ptr Pointer to data \return value of type uint8_t at (*ptr) */ -__attribute__( ( always_inline ) ) __STATIC_INLINE uint8_t __LDREXB(volatile uint8_t *addr) +__attribute__((always_inline)) __STATIC_INLINE uint8_t __LDREXB(volatile uint8_t *addr) { uint32_t result; #if (__GNUC__ > 4) || (__GNUC__ == 4 && __GNUC_MINOR__ >= 8) - __ASM volatile ("ldrexb %0, %1" : "=r" (result) : "Q" (*addr) ); + __ASM volatile("ldrexb %0, %1" + : "=r"(result) + : "Q"(*addr)); #else /* Prior to GCC 4.8, "Q" will be expanded to [rx, #0] which is not accepted by assembler. So has to use following less efficient pattern. */ - __ASM volatile ("ldrexb %0, [%1]" : "=r" (result) : "r" (addr) : "memory" ); + __ASM volatile("ldrexb %0, [%1]" + : "=r"(result) + : "r"(addr) + : "memory"); #endif - return ((uint8_t) result); /* Add explicit type cast here */ + return ((uint8_t)result); /* Add explicit type cast here */ } - /** \brief LDR Exclusive (16 bit) This function executes a exclusive LDR instruction for 16 bit values. @@ -586,22 +553,26 @@ __attribute__( ( always_inline ) ) __STATIC_INLINE uint8_t __LDREXB(volatile uin \param [in] ptr Pointer to data \return value of type uint16_t at (*ptr) */ -__attribute__( ( always_inline ) ) __STATIC_INLINE uint16_t __LDREXH(volatile uint16_t *addr) +__attribute__((always_inline)) __STATIC_INLINE uint16_t __LDREXH(volatile uint16_t *addr) { uint32_t result; #if (__GNUC__ > 4) || (__GNUC__ == 4 && __GNUC_MINOR__ >= 8) - __ASM volatile ("ldrexh %0, %1" : "=r" (result) : "Q" (*addr) ); + __ASM volatile("ldrexh %0, %1" + : "=r"(result) + : "Q"(*addr)); #else /* Prior to GCC 4.8, "Q" will be expanded to [rx, #0] which is not accepted by assembler. So has to use following less efficient pattern. */ - __ASM volatile ("ldrexh %0, [%1]" : "=r" (result) : "r" (addr) : "memory" ); + __ASM volatile("ldrexh %0, [%1]" + : "=r"(result) + : "r"(addr) + : "memory"); #endif - return ((uint16_t) result); /* Add explicit type cast here */ + return ((uint16_t)result); /* Add explicit type cast here */ } - /** \brief LDR Exclusive (32 bit) This function executes a exclusive LDR instruction for 32 bit values. @@ -609,15 +580,16 @@ __attribute__( ( always_inline ) ) __STATIC_INLINE uint16_t __LDREXH(volatile ui \param [in] ptr Pointer to data \return value of type uint32_t at (*ptr) */ -__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __LDREXW(volatile uint32_t *addr) +__attribute__((always_inline)) __STATIC_INLINE uint32_t __LDREXW(volatile uint32_t *addr) { uint32_t result; - __ASM volatile ("ldrex %0, %1" : "=r" (result) : "Q" (*addr) ); - return(result); + __ASM volatile("ldrex %0, %1" + : "=r"(result) + : "Q"(*addr)); + return (result); } - /** \brief STR Exclusive (8 bit) This function executes a exclusive STR instruction for 8 bit values. @@ -627,15 +599,16 @@ __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __LDREXW(volatile ui \return 0 Function succeeded \return 1 Function failed */ -__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __STREXB(uint8_t value, volatile uint8_t *addr) +__attribute__((always_inline)) __STATIC_INLINE uint32_t __STREXB(uint8_t value, volatile uint8_t *addr) { - uint32_t result; + uint32_t result; - __ASM volatile ("strexb %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" ((uint32_t)value) ); - return(result); + __ASM volatile("strexb %0, %2, %1" + : "=&r"(result), "=Q"(*addr) + : "r"((uint32_t)value)); + return (result); } - /** \brief STR Exclusive (16 bit) This function executes a exclusive STR instruction for 16 bit values. @@ -645,15 +618,16 @@ __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __STREXB(uint8_t val \return 0 Function succeeded \return 1 Function failed */ -__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __STREXH(uint16_t value, volatile uint16_t *addr) +__attribute__((always_inline)) __STATIC_INLINE uint32_t __STREXH(uint16_t value, volatile uint16_t *addr) { - uint32_t result; + uint32_t result; - __ASM volatile ("strexh %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" ((uint32_t)value) ); - return(result); + __ASM volatile("strexh %0, %2, %1" + : "=&r"(result), "=Q"(*addr) + : "r"((uint32_t)value)); + return (result); } - /** \brief STR Exclusive (32 bit) This function executes a exclusive STR instruction for 32 bit values. @@ -663,26 +637,27 @@ __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __STREXH(uint16_t va \return 0 Function succeeded \return 1 Function failed */ -__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __STREXW(uint32_t value, volatile uint32_t *addr) +__attribute__((always_inline)) __STATIC_INLINE uint32_t __STREXW(uint32_t value, volatile uint32_t *addr) { - uint32_t result; + uint32_t result; - __ASM volatile ("strex %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" (value) ); - return(result); + __ASM volatile("strex %0, %2, %1" + : "=&r"(result), "=Q"(*addr) + : "r"(value)); + return (result); } - /** \brief Remove the exclusive lock This function removes the exclusive lock which is created by LDREX. */ -__attribute__( ( always_inline ) ) __STATIC_INLINE void __CLREX(void) +__attribute__((always_inline)) __STATIC_INLINE void __CLREX(void) { - __ASM volatile ("clrex" ::: "memory"); + __ASM volatile("clrex" :: + : "memory"); } - /** \brief Signed Saturate This function saturates a signed value. @@ -691,13 +666,15 @@ __attribute__( ( always_inline ) ) __STATIC_INLINE void __CLREX(void) \param [in] sat Bit position to saturate to (1..32) \return Saturated value */ -#define __SSAT(ARG1,ARG2) \ -({ \ - uint32_t __RES, __ARG1 = (ARG1); \ - __ASM ("ssat %0, %1, %2" : "=r" (__RES) : "I" (ARG2), "r" (__ARG1) ); \ - __RES; \ - }) - +#define __SSAT(ARG1, ARG2) \ + ( \ + { \ + uint32_t __RES, __ARG1 = (ARG1); \ + __ASM("ssat %0, %1, %2" \ + : "=r"(__RES) \ + : "I"(ARG2), "r"(__ARG1)); \ + __RES; \ + }) /** \brief Unsigned Saturate @@ -707,13 +684,15 @@ __attribute__( ( always_inline ) ) __STATIC_INLINE void __CLREX(void) \param [in] sat Bit position to saturate to (0..31) \return Saturated value */ -#define __USAT(ARG1,ARG2) \ -({ \ - uint32_t __RES, __ARG1 = (ARG1); \ - __ASM ("usat %0, %1, %2" : "=r" (__RES) : "I" (ARG2), "r" (__ARG1) ); \ - __RES; \ - }) - +#define __USAT(ARG1, ARG2) \ + ( \ + { \ + uint32_t __RES, __ARG1 = (ARG1); \ + __ASM("usat %0, %1, %2" \ + : "=r"(__RES) \ + : "I"(ARG2), "r"(__ARG1)); \ + __RES; \ + }) /** \brief Count leading zeros @@ -722,15 +701,16 @@ __attribute__( ( always_inline ) ) __STATIC_INLINE void __CLREX(void) \param [in] value Value to count the leading zeros \return number of leading zeros in value */ -__attribute__( ( always_inline ) ) __STATIC_INLINE uint8_t __CLZ(uint32_t value) +__attribute__((always_inline)) __STATIC_INLINE uint8_t __CLZ(uint32_t value) { - uint32_t result; + uint32_t result; - __ASM volatile ("clz %0, %1" : "=r" (result) : "r" (value) ); - return ((uint8_t) result); /* Add explicit type cast here */ + __ASM volatile("clz %0, %1" + : "=r"(result) + : "r"(value)); + return ((uint8_t)result); /* Add explicit type cast here */ } - /** \brief Rotate Right with Extend (32 bit) This function moves each bit of a bitstring right by one bit. The carry input is shifted in at the left end of the bitstring. @@ -738,15 +718,16 @@ __attribute__( ( always_inline ) ) __STATIC_INLINE uint8_t __CLZ(uint32_t value) \param [in] value Value to rotate \return Rotated value */ -__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __RRX(uint32_t value) +__attribute__((always_inline)) __STATIC_INLINE uint32_t __RRX(uint32_t value) { - uint32_t result; + uint32_t result; - __ASM volatile ("rrx %0, %1" : __CMSIS_GCC_OUT_REG (result) : __CMSIS_GCC_USE_REG (value) ); - return(result); + __ASM volatile("rrx %0, %1" + : __CMSIS_GCC_OUT_REG(result) + : __CMSIS_GCC_USE_REG(value)); + return (result); } - /** \brief LDRT Unprivileged (8 bit) This function executes a Unprivileged LDRT instruction for 8 bit value. @@ -754,22 +735,26 @@ __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __RRX(uint32_t value \param [in] ptr Pointer to data \return value of type uint8_t at (*ptr) */ -__attribute__( ( always_inline ) ) __STATIC_INLINE uint8_t __LDRBT(volatile uint8_t *addr) +__attribute__((always_inline)) __STATIC_INLINE uint8_t __LDRBT(volatile uint8_t *addr) { uint32_t result; #if (__GNUC__ > 4) || (__GNUC__ == 4 && __GNUC_MINOR__ >= 8) - __ASM volatile ("ldrbt %0, %1" : "=r" (result) : "Q" (*addr) ); + __ASM volatile("ldrbt %0, %1" + : "=r"(result) + : "Q"(*addr)); #else /* Prior to GCC 4.8, "Q" will be expanded to [rx, #0] which is not accepted by assembler. So has to use following less efficient pattern. */ - __ASM volatile ("ldrbt %0, [%1]" : "=r" (result) : "r" (addr) : "memory" ); + __ASM volatile("ldrbt %0, [%1]" + : "=r"(result) + : "r"(addr) + : "memory"); #endif - return ((uint8_t) result); /* Add explicit type cast here */ + return ((uint8_t)result); /* Add explicit type cast here */ } - /** \brief LDRT Unprivileged (16 bit) This function executes a Unprivileged LDRT instruction for 16 bit values. @@ -777,22 +762,26 @@ __attribute__( ( always_inline ) ) __STATIC_INLINE uint8_t __LDRBT(volatile uint \param [in] ptr Pointer to data \return value of type uint16_t at (*ptr) */ -__attribute__( ( always_inline ) ) __STATIC_INLINE uint16_t __LDRHT(volatile uint16_t *addr) +__attribute__((always_inline)) __STATIC_INLINE uint16_t __LDRHT(volatile uint16_t *addr) { uint32_t result; #if (__GNUC__ > 4) || (__GNUC__ == 4 && __GNUC_MINOR__ >= 8) - __ASM volatile ("ldrht %0, %1" : "=r" (result) : "Q" (*addr) ); + __ASM volatile("ldrht %0, %1" + : "=r"(result) + : "Q"(*addr)); #else /* Prior to GCC 4.8, "Q" will be expanded to [rx, #0] which is not accepted by assembler. So has to use following less efficient pattern. */ - __ASM volatile ("ldrht %0, [%1]" : "=r" (result) : "r" (addr) : "memory" ); + __ASM volatile("ldrht %0, [%1]" + : "=r"(result) + : "r"(addr) + : "memory"); #endif - return ((uint16_t) result); /* Add explicit type cast here */ + return ((uint16_t)result); /* Add explicit type cast here */ } - /** \brief LDRT Unprivileged (32 bit) This function executes a Unprivileged LDRT instruction for 32 bit values. @@ -800,15 +789,16 @@ __attribute__( ( always_inline ) ) __STATIC_INLINE uint16_t __LDRHT(volatile uin \param [in] ptr Pointer to data \return value of type uint32_t at (*ptr) */ -__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __LDRT(volatile uint32_t *addr) +__attribute__((always_inline)) __STATIC_INLINE uint32_t __LDRT(volatile uint32_t *addr) { uint32_t result; - __ASM volatile ("ldrt %0, %1" : "=r" (result) : "Q" (*addr) ); - return(result); + __ASM volatile("ldrt %0, %1" + : "=r"(result) + : "Q"(*addr)); + return (result); } - /** \brief STRT Unprivileged (8 bit) This function executes a Unprivileged STRT instruction for 8 bit values. @@ -816,12 +806,13 @@ __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __LDRT(volatile uint \param [in] value Value to store \param [in] ptr Pointer to location */ -__attribute__( ( always_inline ) ) __STATIC_INLINE void __STRBT(uint8_t value, volatile uint8_t *addr) +__attribute__((always_inline)) __STATIC_INLINE void __STRBT(uint8_t value, volatile uint8_t *addr) { - __ASM volatile ("strbt %1, %0" : "=Q" (*addr) : "r" ((uint32_t)value) ); + __ASM volatile("strbt %1, %0" + : "=Q"(*addr) + : "r"((uint32_t)value)); } - /** \brief STRT Unprivileged (16 bit) This function executes a Unprivileged STRT instruction for 16 bit values. @@ -829,12 +820,13 @@ __attribute__( ( always_inline ) ) __STATIC_INLINE void __STRBT(uint8_t value, v \param [in] value Value to store \param [in] ptr Pointer to location */ -__attribute__( ( always_inline ) ) __STATIC_INLINE void __STRHT(uint16_t value, volatile uint16_t *addr) +__attribute__((always_inline)) __STATIC_INLINE void __STRHT(uint16_t value, volatile uint16_t *addr) { - __ASM volatile ("strht %1, %0" : "=Q" (*addr) : "r" ((uint32_t)value) ); + __ASM volatile("strht %1, %0" + : "=Q"(*addr) + : "r"((uint32_t)value)); } - /** \brief STRT Unprivileged (32 bit) This function executes a Unprivileged STRT instruction for 32 bit values. @@ -842,25 +834,24 @@ __attribute__( ( always_inline ) ) __STATIC_INLINE void __STRHT(uint16_t value, \param [in] value Value to store \param [in] ptr Pointer to location */ -__attribute__( ( always_inline ) ) __STATIC_INLINE void __STRT(uint32_t value, volatile uint32_t *addr) +__attribute__((always_inline)) __STATIC_INLINE void __STRT(uint32_t value, volatile uint32_t *addr) { - __ASM volatile ("strt %1, %0" : "=Q" (*addr) : "r" (value) ); + __ASM volatile("strt %1, %0" + : "=Q"(*addr) + : "r"(value)); } #endif /* (__CORTEX_M >= 0x03) || (__CORTEX_SC >= 300) */ - -#elif defined ( __ICCARM__ ) /*------------------ ICC Compiler -------------------*/ +#elif defined(__ICCARM__) /*------------------ ICC Compiler -------------------*/ /* IAR iccarm specific functions */ #include - -#elif defined ( __TMS470__ ) /*---------------- TI CCS Compiler ------------------*/ +#elif defined(__TMS470__) /*---------------- TI CCS Compiler ------------------*/ /* TI CCS specific functions */ #include - -#elif defined ( __TASKING__ ) /*------------------ TASKING Compiler --------------*/ +#elif defined(__TASKING__) /*------------------ TASKING Compiler --------------*/ /* TASKING carm specific functions */ /* * The CMSIS functions have been implemented as intrinsics in the compiler. @@ -868,8 +859,7 @@ __attribute__( ( always_inline ) ) __STATIC_INLINE void __STRT(uint32_t value, v * Including the CMSIS ones. */ - -#elif defined ( __CSMC__ ) /*------------------ COSMIC Compiler -------------------*/ +#elif defined(__CSMC__) /*------------------ COSMIC Compiler -------------------*/ /* Cosmic specific functions */ #include diff --git a/bsp/swm320-lq100/Libraries/CMSIS/CoreSupport/core_cmSimd.h b/bsp/swm320-lq100/Libraries/CMSIS/CoreSupport/core_cmSimd.h index ee58eee56d..1997067d11 100644 --- a/bsp/swm320-lq100/Libraries/CMSIS/CoreSupport/core_cmSimd.h +++ b/bsp/swm320-lq100/Libraries/CMSIS/CoreSupport/core_cmSimd.h @@ -1,4 +1,4 @@ -/**************************************************************************//** +/**************************************************************************/ /** * @file core_cmSimd.h * @brief CMSIS Cortex-M SIMD Header File * @version V4.00 @@ -34,661 +34,794 @@ POSSIBILITY OF SUCH DAMAGE. ---------------------------------------------------------------------------*/ - -#if defined ( __ICCARM__ ) - #pragma system_include /* treat file as system include file for MISRA check */ +#if defined(__ICCARM__) +#pragma system_include /* treat file as system include file for MISRA check */ #endif #ifndef __CORE_CMSIMD_H #define __CORE_CMSIMD_H #ifdef __cplusplus - extern "C" { +extern "C" +{ #endif - -/******************************************************************************* + /******************************************************************************* * Hardware Abstraction Layer ******************************************************************************/ - -/* ################### Compiler specific Intrinsics ########################### */ -/** \defgroup CMSIS_SIMD_intrinsics CMSIS SIMD Intrinsics + /* ################### Compiler specific Intrinsics ########################### */ + /** \defgroup CMSIS_SIMD_intrinsics CMSIS SIMD Intrinsics Access to dedicated SIMD instructions @{ */ -#if defined ( __CC_ARM ) /*------------------RealView Compiler -----------------*/ +#if defined(__CC_ARM) /*------------------RealView Compiler -----------------*/ /* ARM armcc specific functions */ -#define __SADD8 __sadd8 -#define __QADD8 __qadd8 -#define __SHADD8 __shadd8 -#define __UADD8 __uadd8 -#define __UQADD8 __uqadd8 -#define __UHADD8 __uhadd8 -#define __SSUB8 __ssub8 -#define __QSUB8 __qsub8 -#define __SHSUB8 __shsub8 -#define __USUB8 __usub8 -#define __UQSUB8 __uqsub8 -#define __UHSUB8 __uhsub8 -#define __SADD16 __sadd16 -#define __QADD16 __qadd16 -#define __SHADD16 __shadd16 -#define __UADD16 __uadd16 -#define __UQADD16 __uqadd16 -#define __UHADD16 __uhadd16 -#define __SSUB16 __ssub16 -#define __QSUB16 __qsub16 -#define __SHSUB16 __shsub16 -#define __USUB16 __usub16 -#define __UQSUB16 __uqsub16 -#define __UHSUB16 __uhsub16 -#define __SASX __sasx -#define __QASX __qasx -#define __SHASX __shasx -#define __UASX __uasx -#define __UQASX __uqasx -#define __UHASX __uhasx -#define __SSAX __ssax -#define __QSAX __qsax -#define __SHSAX __shsax -#define __USAX __usax -#define __UQSAX __uqsax -#define __UHSAX __uhsax -#define __USAD8 __usad8 -#define __USADA8 __usada8 -#define __SSAT16 __ssat16 -#define __USAT16 __usat16 -#define __UXTB16 __uxtb16 -#define __UXTAB16 __uxtab16 -#define __SXTB16 __sxtb16 -#define __SXTAB16 __sxtab16 -#define __SMUAD __smuad -#define __SMUADX __smuadx -#define __SMLAD __smlad -#define __SMLADX __smladx -#define __SMLALD __smlald -#define __SMLALDX __smlaldx -#define __SMUSD __smusd -#define __SMUSDX __smusdx -#define __SMLSD __smlsd -#define __SMLSDX __smlsdx -#define __SMLSLD __smlsld -#define __SMLSLDX __smlsldx -#define __SEL __sel -#define __QADD __qadd -#define __QSUB __qsub - -#define __PKHBT(ARG1,ARG2,ARG3) ( ((((uint32_t)(ARG1)) ) & 0x0000FFFFUL) | \ - ((((uint32_t)(ARG2)) << (ARG3)) & 0xFFFF0000UL) ) - -#define __PKHTB(ARG1,ARG2,ARG3) ( ((((uint32_t)(ARG1)) ) & 0xFFFF0000UL) | \ - ((((uint32_t)(ARG2)) >> (ARG3)) & 0x0000FFFFUL) ) - -#define __SMMLA(ARG1,ARG2,ARG3) ( (int32_t)((((int64_t)(ARG1) * (ARG2)) + \ - ((int64_t)(ARG3) << 32) ) >> 32)) - - -#elif defined ( __GNUC__ ) /*------------------ GNU Compiler ---------------------*/ +#define __SADD8 __sadd8 +#define __QADD8 __qadd8 +#define __SHADD8 __shadd8 +#define __UADD8 __uadd8 +#define __UQADD8 __uqadd8 +#define __UHADD8 __uhadd8 +#define __SSUB8 __ssub8 +#define __QSUB8 __qsub8 +#define __SHSUB8 __shsub8 +#define __USUB8 __usub8 +#define __UQSUB8 __uqsub8 +#define __UHSUB8 __uhsub8 +#define __SADD16 __sadd16 +#define __QADD16 __qadd16 +#define __SHADD16 __shadd16 +#define __UADD16 __uadd16 +#define __UQADD16 __uqadd16 +#define __UHADD16 __uhadd16 +#define __SSUB16 __ssub16 +#define __QSUB16 __qsub16 +#define __SHSUB16 __shsub16 +#define __USUB16 __usub16 +#define __UQSUB16 __uqsub16 +#define __UHSUB16 __uhsub16 +#define __SASX __sasx +#define __QASX __qasx +#define __SHASX __shasx +#define __UASX __uasx +#define __UQASX __uqasx +#define __UHASX __uhasx +#define __SSAX __ssax +#define __QSAX __qsax +#define __SHSAX __shsax +#define __USAX __usax +#define __UQSAX __uqsax +#define __UHSAX __uhsax +#define __USAD8 __usad8 +#define __USADA8 __usada8 +#define __SSAT16 __ssat16 +#define __USAT16 __usat16 +#define __UXTB16 __uxtb16 +#define __UXTAB16 __uxtab16 +#define __SXTB16 __sxtb16 +#define __SXTAB16 __sxtab16 +#define __SMUAD __smuad +#define __SMUADX __smuadx +#define __SMLAD __smlad +#define __SMLADX __smladx +#define __SMLALD __smlald +#define __SMLALDX __smlaldx +#define __SMUSD __smusd +#define __SMUSDX __smusdx +#define __SMLSD __smlsd +#define __SMLSDX __smlsdx +#define __SMLSLD __smlsld +#define __SMLSLDX __smlsldx +#define __SEL __sel +#define __QADD __qadd +#define __QSUB __qsub + +#define __PKHBT(ARG1, ARG2, ARG3) (((((uint32_t)(ARG1))) & 0x0000FFFFUL) | \ + ((((uint32_t)(ARG2)) << (ARG3)) & 0xFFFF0000UL)) + +#define __PKHTB(ARG1, ARG2, ARG3) (((((uint32_t)(ARG1))) & 0xFFFF0000UL) | \ + ((((uint32_t)(ARG2)) >> (ARG3)) & 0x0000FFFFUL)) + +#define __SMMLA(ARG1, ARG2, ARG3) ((int32_t)((((int64_t)(ARG1) * (ARG2)) + \ + ((int64_t)(ARG3) << 32)) >> \ + 32)) + +#elif defined(__GNUC__) /*------------------ GNU Compiler ---------------------*/ /* GNU gcc specific functions */ -__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SADD8(uint32_t op1, uint32_t op2) +__attribute__((always_inline)) __STATIC_INLINE uint32_t __SADD8(uint32_t op1, uint32_t op2) { - uint32_t result; + uint32_t result; - __ASM volatile ("sadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); - return(result); + __ASM volatile("sadd8 %0, %1, %2" + : "=r"(result) + : "r"(op1), "r"(op2)); + return (result); } -__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __QADD8(uint32_t op1, uint32_t op2) +__attribute__((always_inline)) __STATIC_INLINE uint32_t __QADD8(uint32_t op1, uint32_t op2) { - uint32_t result; + uint32_t result; - __ASM volatile ("qadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); - return(result); + __ASM volatile("qadd8 %0, %1, %2" + : "=r"(result) + : "r"(op1), "r"(op2)); + return (result); } -__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SHADD8(uint32_t op1, uint32_t op2) +__attribute__((always_inline)) __STATIC_INLINE uint32_t __SHADD8(uint32_t op1, uint32_t op2) { - uint32_t result; + uint32_t result; - __ASM volatile ("shadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); - return(result); + __ASM volatile("shadd8 %0, %1, %2" + : "=r"(result) + : "r"(op1), "r"(op2)); + return (result); } -__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UADD8(uint32_t op1, uint32_t op2) +__attribute__((always_inline)) __STATIC_INLINE uint32_t __UADD8(uint32_t op1, uint32_t op2) { - uint32_t result; + uint32_t result; - __ASM volatile ("uadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); - return(result); + __ASM volatile("uadd8 %0, %1, %2" + : "=r"(result) + : "r"(op1), "r"(op2)); + return (result); } -__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UQADD8(uint32_t op1, uint32_t op2) +__attribute__((always_inline)) __STATIC_INLINE uint32_t __UQADD8(uint32_t op1, uint32_t op2) { - uint32_t result; + uint32_t result; - __ASM volatile ("uqadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); - return(result); + __ASM volatile("uqadd8 %0, %1, %2" + : "=r"(result) + : "r"(op1), "r"(op2)); + return (result); } -__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UHADD8(uint32_t op1, uint32_t op2) +__attribute__((always_inline)) __STATIC_INLINE uint32_t __UHADD8(uint32_t op1, uint32_t op2) { - uint32_t result; + uint32_t result; - __ASM volatile ("uhadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); - return(result); + __ASM volatile("uhadd8 %0, %1, %2" + : "=r"(result) + : "r"(op1), "r"(op2)); + return (result); } - -__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SSUB8(uint32_t op1, uint32_t op2) +__attribute__((always_inline)) __STATIC_INLINE uint32_t __SSUB8(uint32_t op1, uint32_t op2) { - uint32_t result; + uint32_t result; - __ASM volatile ("ssub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); - return(result); + __ASM volatile("ssub8 %0, %1, %2" + : "=r"(result) + : "r"(op1), "r"(op2)); + return (result); } -__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __QSUB8(uint32_t op1, uint32_t op2) +__attribute__((always_inline)) __STATIC_INLINE uint32_t __QSUB8(uint32_t op1, uint32_t op2) { - uint32_t result; + uint32_t result; - __ASM volatile ("qsub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); - return(result); + __ASM volatile("qsub8 %0, %1, %2" + : "=r"(result) + : "r"(op1), "r"(op2)); + return (result); } -__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SHSUB8(uint32_t op1, uint32_t op2) +__attribute__((always_inline)) __STATIC_INLINE uint32_t __SHSUB8(uint32_t op1, uint32_t op2) { - uint32_t result; + uint32_t result; - __ASM volatile ("shsub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); - return(result); + __ASM volatile("shsub8 %0, %1, %2" + : "=r"(result) + : "r"(op1), "r"(op2)); + return (result); } -__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __USUB8(uint32_t op1, uint32_t op2) +__attribute__((always_inline)) __STATIC_INLINE uint32_t __USUB8(uint32_t op1, uint32_t op2) { - uint32_t result; + uint32_t result; - __ASM volatile ("usub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); - return(result); + __ASM volatile("usub8 %0, %1, %2" + : "=r"(result) + : "r"(op1), "r"(op2)); + return (result); } -__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UQSUB8(uint32_t op1, uint32_t op2) +__attribute__((always_inline)) __STATIC_INLINE uint32_t __UQSUB8(uint32_t op1, uint32_t op2) { - uint32_t result; + uint32_t result; - __ASM volatile ("uqsub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); - return(result); + __ASM volatile("uqsub8 %0, %1, %2" + : "=r"(result) + : "r"(op1), "r"(op2)); + return (result); } -__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UHSUB8(uint32_t op1, uint32_t op2) +__attribute__((always_inline)) __STATIC_INLINE uint32_t __UHSUB8(uint32_t op1, uint32_t op2) { - uint32_t result; + uint32_t result; - __ASM volatile ("uhsub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); - return(result); + __ASM volatile("uhsub8 %0, %1, %2" + : "=r"(result) + : "r"(op1), "r"(op2)); + return (result); } - -__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SADD16(uint32_t op1, uint32_t op2) +__attribute__((always_inline)) __STATIC_INLINE uint32_t __SADD16(uint32_t op1, uint32_t op2) { - uint32_t result; + uint32_t result; - __ASM volatile ("sadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); - return(result); + __ASM volatile("sadd16 %0, %1, %2" + : "=r"(result) + : "r"(op1), "r"(op2)); + return (result); } -__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __QADD16(uint32_t op1, uint32_t op2) +__attribute__((always_inline)) __STATIC_INLINE uint32_t __QADD16(uint32_t op1, uint32_t op2) { - uint32_t result; + uint32_t result; - __ASM volatile ("qadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); - return(result); + __ASM volatile("qadd16 %0, %1, %2" + : "=r"(result) + : "r"(op1), "r"(op2)); + return (result); } -__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SHADD16(uint32_t op1, uint32_t op2) +__attribute__((always_inline)) __STATIC_INLINE uint32_t __SHADD16(uint32_t op1, uint32_t op2) { - uint32_t result; + uint32_t result; - __ASM volatile ("shadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); - return(result); + __ASM volatile("shadd16 %0, %1, %2" + : "=r"(result) + : "r"(op1), "r"(op2)); + return (result); } -__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UADD16(uint32_t op1, uint32_t op2) +__attribute__((always_inline)) __STATIC_INLINE uint32_t __UADD16(uint32_t op1, uint32_t op2) { - uint32_t result; + uint32_t result; - __ASM volatile ("uadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); - return(result); + __ASM volatile("uadd16 %0, %1, %2" + : "=r"(result) + : "r"(op1), "r"(op2)); + return (result); } -__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UQADD16(uint32_t op1, uint32_t op2) +__attribute__((always_inline)) __STATIC_INLINE uint32_t __UQADD16(uint32_t op1, uint32_t op2) { - uint32_t result; + uint32_t result; - __ASM volatile ("uqadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); - return(result); + __ASM volatile("uqadd16 %0, %1, %2" + : "=r"(result) + : "r"(op1), "r"(op2)); + return (result); } -__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UHADD16(uint32_t op1, uint32_t op2) +__attribute__((always_inline)) __STATIC_INLINE uint32_t __UHADD16(uint32_t op1, uint32_t op2) { - uint32_t result; + uint32_t result; - __ASM volatile ("uhadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); - return(result); + __ASM volatile("uhadd16 %0, %1, %2" + : "=r"(result) + : "r"(op1), "r"(op2)); + return (result); } -__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SSUB16(uint32_t op1, uint32_t op2) +__attribute__((always_inline)) __STATIC_INLINE uint32_t __SSUB16(uint32_t op1, uint32_t op2) { - uint32_t result; + uint32_t result; - __ASM volatile ("ssub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); - return(result); + __ASM volatile("ssub16 %0, %1, %2" + : "=r"(result) + : "r"(op1), "r"(op2)); + return (result); } -__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __QSUB16(uint32_t op1, uint32_t op2) +__attribute__((always_inline)) __STATIC_INLINE uint32_t __QSUB16(uint32_t op1, uint32_t op2) { - uint32_t result; + uint32_t result; - __ASM volatile ("qsub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); - return(result); + __ASM volatile("qsub16 %0, %1, %2" + : "=r"(result) + : "r"(op1), "r"(op2)); + return (result); } -__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SHSUB16(uint32_t op1, uint32_t op2) +__attribute__((always_inline)) __STATIC_INLINE uint32_t __SHSUB16(uint32_t op1, uint32_t op2) { - uint32_t result; + uint32_t result; - __ASM volatile ("shsub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); - return(result); + __ASM volatile("shsub16 %0, %1, %2" + : "=r"(result) + : "r"(op1), "r"(op2)); + return (result); } -__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __USUB16(uint32_t op1, uint32_t op2) +__attribute__((always_inline)) __STATIC_INLINE uint32_t __USUB16(uint32_t op1, uint32_t op2) { - uint32_t result; + uint32_t result; - __ASM volatile ("usub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); - return(result); + __ASM volatile("usub16 %0, %1, %2" + : "=r"(result) + : "r"(op1), "r"(op2)); + return (result); } -__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UQSUB16(uint32_t op1, uint32_t op2) +__attribute__((always_inline)) __STATIC_INLINE uint32_t __UQSUB16(uint32_t op1, uint32_t op2) { - uint32_t result; + uint32_t result; - __ASM volatile ("uqsub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); - return(result); + __ASM volatile("uqsub16 %0, %1, %2" + : "=r"(result) + : "r"(op1), "r"(op2)); + return (result); } -__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UHSUB16(uint32_t op1, uint32_t op2) +__attribute__((always_inline)) __STATIC_INLINE uint32_t __UHSUB16(uint32_t op1, uint32_t op2) { - uint32_t result; + uint32_t result; - __ASM volatile ("uhsub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); - return(result); + __ASM volatile("uhsub16 %0, %1, %2" + : "=r"(result) + : "r"(op1), "r"(op2)); + return (result); } -__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SASX(uint32_t op1, uint32_t op2) +__attribute__((always_inline)) __STATIC_INLINE uint32_t __SASX(uint32_t op1, uint32_t op2) { - uint32_t result; + uint32_t result; - __ASM volatile ("sasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); - return(result); + __ASM volatile("sasx %0, %1, %2" + : "=r"(result) + : "r"(op1), "r"(op2)); + return (result); } -__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __QASX(uint32_t op1, uint32_t op2) +__attribute__((always_inline)) __STATIC_INLINE uint32_t __QASX(uint32_t op1, uint32_t op2) { - uint32_t result; + uint32_t result; - __ASM volatile ("qasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); - return(result); + __ASM volatile("qasx %0, %1, %2" + : "=r"(result) + : "r"(op1), "r"(op2)); + return (result); } -__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SHASX(uint32_t op1, uint32_t op2) +__attribute__((always_inline)) __STATIC_INLINE uint32_t __SHASX(uint32_t op1, uint32_t op2) { - uint32_t result; + uint32_t result; - __ASM volatile ("shasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); - return(result); + __ASM volatile("shasx %0, %1, %2" + : "=r"(result) + : "r"(op1), "r"(op2)); + return (result); } -__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UASX(uint32_t op1, uint32_t op2) +__attribute__((always_inline)) __STATIC_INLINE uint32_t __UASX(uint32_t op1, uint32_t op2) { - uint32_t result; + uint32_t result; - __ASM volatile ("uasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); - return(result); + __ASM volatile("uasx %0, %1, %2" + : "=r"(result) + : "r"(op1), "r"(op2)); + return (result); } -__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UQASX(uint32_t op1, uint32_t op2) +__attribute__((always_inline)) __STATIC_INLINE uint32_t __UQASX(uint32_t op1, uint32_t op2) { - uint32_t result; + uint32_t result; - __ASM volatile ("uqasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); - return(result); + __ASM volatile("uqasx %0, %1, %2" + : "=r"(result) + : "r"(op1), "r"(op2)); + return (result); } -__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UHASX(uint32_t op1, uint32_t op2) +__attribute__((always_inline)) __STATIC_INLINE uint32_t __UHASX(uint32_t op1, uint32_t op2) { - uint32_t result; + uint32_t result; - __ASM volatile ("uhasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); - return(result); + __ASM volatile("uhasx %0, %1, %2" + : "=r"(result) + : "r"(op1), "r"(op2)); + return (result); } -__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SSAX(uint32_t op1, uint32_t op2) +__attribute__((always_inline)) __STATIC_INLINE uint32_t __SSAX(uint32_t op1, uint32_t op2) { - uint32_t result; + uint32_t result; - __ASM volatile ("ssax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); - return(result); + __ASM volatile("ssax %0, %1, %2" + : "=r"(result) + : "r"(op1), "r"(op2)); + return (result); } -__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __QSAX(uint32_t op1, uint32_t op2) +__attribute__((always_inline)) __STATIC_INLINE uint32_t __QSAX(uint32_t op1, uint32_t op2) { - uint32_t result; + uint32_t result; - __ASM volatile ("qsax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); - return(result); + __ASM volatile("qsax %0, %1, %2" + : "=r"(result) + : "r"(op1), "r"(op2)); + return (result); } -__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SHSAX(uint32_t op1, uint32_t op2) +__attribute__((always_inline)) __STATIC_INLINE uint32_t __SHSAX(uint32_t op1, uint32_t op2) { - uint32_t result; + uint32_t result; - __ASM volatile ("shsax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); - return(result); + __ASM volatile("shsax %0, %1, %2" + : "=r"(result) + : "r"(op1), "r"(op2)); + return (result); } -__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __USAX(uint32_t op1, uint32_t op2) +__attribute__((always_inline)) __STATIC_INLINE uint32_t __USAX(uint32_t op1, uint32_t op2) { - uint32_t result; + uint32_t result; - __ASM volatile ("usax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); - return(result); + __ASM volatile("usax %0, %1, %2" + : "=r"(result) + : "r"(op1), "r"(op2)); + return (result); } -__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UQSAX(uint32_t op1, uint32_t op2) +__attribute__((always_inline)) __STATIC_INLINE uint32_t __UQSAX(uint32_t op1, uint32_t op2) { - uint32_t result; + uint32_t result; - __ASM volatile ("uqsax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); - return(result); + __ASM volatile("uqsax %0, %1, %2" + : "=r"(result) + : "r"(op1), "r"(op2)); + return (result); } -__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UHSAX(uint32_t op1, uint32_t op2) +__attribute__((always_inline)) __STATIC_INLINE uint32_t __UHSAX(uint32_t op1, uint32_t op2) { - uint32_t result; + uint32_t result; - __ASM volatile ("uhsax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); - return(result); + __ASM volatile("uhsax %0, %1, %2" + : "=r"(result) + : "r"(op1), "r"(op2)); + return (result); } -__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __USAD8(uint32_t op1, uint32_t op2) +__attribute__((always_inline)) __STATIC_INLINE uint32_t __USAD8(uint32_t op1, uint32_t op2) { - uint32_t result; + uint32_t result; - __ASM volatile ("usad8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); - return(result); + __ASM volatile("usad8 %0, %1, %2" + : "=r"(result) + : "r"(op1), "r"(op2)); + return (result); } -__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __USADA8(uint32_t op1, uint32_t op2, uint32_t op3) +__attribute__((always_inline)) __STATIC_INLINE uint32_t __USADA8(uint32_t op1, uint32_t op2, uint32_t op3) { - uint32_t result; + uint32_t result; - __ASM volatile ("usada8 %0, %1, %2, %3" : "=r" (result) : "r" (op1), "r" (op2), "r" (op3) ); - return(result); + __ASM volatile("usada8 %0, %1, %2, %3" + : "=r"(result) + : "r"(op1), "r"(op2), "r"(op3)); + return (result); } -#define __SSAT16(ARG1,ARG2) \ -({ \ - uint32_t __RES, __ARG1 = (ARG1); \ - __ASM ("ssat16 %0, %1, %2" : "=r" (__RES) : "I" (ARG2), "r" (__ARG1) ); \ - __RES; \ - }) +#define __SSAT16(ARG1, ARG2) \ + ( \ + { \ + uint32_t __RES, __ARG1 = (ARG1); \ + __ASM("ssat16 %0, %1, %2" \ + : "=r"(__RES) \ + : "I"(ARG2), "r"(__ARG1)); \ + __RES; \ + }) -#define __USAT16(ARG1,ARG2) \ -({ \ - uint32_t __RES, __ARG1 = (ARG1); \ - __ASM ("usat16 %0, %1, %2" : "=r" (__RES) : "I" (ARG2), "r" (__ARG1) ); \ - __RES; \ - }) +#define __USAT16(ARG1, ARG2) \ + ( \ + { \ + uint32_t __RES, __ARG1 = (ARG1); \ + __ASM("usat16 %0, %1, %2" \ + : "=r"(__RES) \ + : "I"(ARG2), "r"(__ARG1)); \ + __RES; \ + }) -__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UXTB16(uint32_t op1) +__attribute__((always_inline)) __STATIC_INLINE uint32_t __UXTB16(uint32_t op1) { - uint32_t result; + uint32_t result; - __ASM volatile ("uxtb16 %0, %1" : "=r" (result) : "r" (op1)); - return(result); + __ASM volatile("uxtb16 %0, %1" + : "=r"(result) + : "r"(op1)); + return (result); } -__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UXTAB16(uint32_t op1, uint32_t op2) +__attribute__((always_inline)) __STATIC_INLINE uint32_t __UXTAB16(uint32_t op1, uint32_t op2) { - uint32_t result; + uint32_t result; - __ASM volatile ("uxtab16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); - return(result); + __ASM volatile("uxtab16 %0, %1, %2" + : "=r"(result) + : "r"(op1), "r"(op2)); + return (result); } -__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SXTB16(uint32_t op1) +__attribute__((always_inline)) __STATIC_INLINE uint32_t __SXTB16(uint32_t op1) { - uint32_t result; + uint32_t result; - __ASM volatile ("sxtb16 %0, %1" : "=r" (result) : "r" (op1)); - return(result); + __ASM volatile("sxtb16 %0, %1" + : "=r"(result) + : "r"(op1)); + return (result); } -__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SXTAB16(uint32_t op1, uint32_t op2) +__attribute__((always_inline)) __STATIC_INLINE uint32_t __SXTAB16(uint32_t op1, uint32_t op2) { - uint32_t result; + uint32_t result; - __ASM volatile ("sxtab16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); - return(result); + __ASM volatile("sxtab16 %0, %1, %2" + : "=r"(result) + : "r"(op1), "r"(op2)); + return (result); } -__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SMUAD (uint32_t op1, uint32_t op2) +__attribute__((always_inline)) __STATIC_INLINE uint32_t __SMUAD(uint32_t op1, uint32_t op2) { - uint32_t result; + uint32_t result; - __ASM volatile ("smuad %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); - return(result); + __ASM volatile("smuad %0, %1, %2" + : "=r"(result) + : "r"(op1), "r"(op2)); + return (result); } -__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SMUADX (uint32_t op1, uint32_t op2) +__attribute__((always_inline)) __STATIC_INLINE uint32_t __SMUADX(uint32_t op1, uint32_t op2) { - uint32_t result; + uint32_t result; - __ASM volatile ("smuadx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); - return(result); + __ASM volatile("smuadx %0, %1, %2" + : "=r"(result) + : "r"(op1), "r"(op2)); + return (result); } -__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SMLAD (uint32_t op1, uint32_t op2, uint32_t op3) +__attribute__((always_inline)) __STATIC_INLINE uint32_t __SMLAD(uint32_t op1, uint32_t op2, uint32_t op3) { - uint32_t result; + uint32_t result; - __ASM volatile ("smlad %0, %1, %2, %3" : "=r" (result) : "r" (op1), "r" (op2), "r" (op3) ); - return(result); + __ASM volatile("smlad %0, %1, %2, %3" + : "=r"(result) + : "r"(op1), "r"(op2), "r"(op3)); + return (result); } -__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SMLADX (uint32_t op1, uint32_t op2, uint32_t op3) +__attribute__((always_inline)) __STATIC_INLINE uint32_t __SMLADX(uint32_t op1, uint32_t op2, uint32_t op3) { - uint32_t result; + uint32_t result; - __ASM volatile ("smladx %0, %1, %2, %3" : "=r" (result) : "r" (op1), "r" (op2), "r" (op3) ); - return(result); + __ASM volatile("smladx %0, %1, %2, %3" + : "=r"(result) + : "r"(op1), "r"(op2), "r"(op3)); + return (result); } -__attribute__( ( always_inline ) ) __STATIC_INLINE uint64_t __SMLALD (uint32_t op1, uint32_t op2, uint64_t acc) +__attribute__((always_inline)) __STATIC_INLINE uint64_t __SMLALD(uint32_t op1, uint32_t op2, uint64_t acc) { - union llreg_u{ - uint32_t w32[2]; - uint64_t w64; - } llr; - llr.w64 = acc; + union llreg_u + { + uint32_t w32[2]; + uint64_t w64; + } llr; + llr.w64 = acc; -#ifndef __ARMEB__ // Little endian - __ASM volatile ("smlald %0, %1, %2, %3" : "=r" (llr.w32[0]), "=r" (llr.w32[1]): "r" (op1), "r" (op2) , "0" (llr.w32[0]), "1" (llr.w32[1]) ); -#else // Big endian - __ASM volatile ("smlald %0, %1, %2, %3" : "=r" (llr.w32[1]), "=r" (llr.w32[0]): "r" (op1), "r" (op2) , "0" (llr.w32[1]), "1" (llr.w32[0]) ); +#ifndef __ARMEB__ // Little endian + __ASM volatile("smlald %0, %1, %2, %3" + : "=r"(llr.w32[0]), "=r"(llr.w32[1]) + : "r"(op1), "r"(op2), "0"(llr.w32[0]), "1"(llr.w32[1])); +#else // Big endian + __ASM volatile("smlald %0, %1, %2, %3" + : "=r"(llr.w32[1]), "=r"(llr.w32[0]) + : "r"(op1), "r"(op2), "0"(llr.w32[1]), "1"(llr.w32[0])); #endif - return(llr.w64); + return (llr.w64); } -__attribute__( ( always_inline ) ) __STATIC_INLINE uint64_t __SMLALDX (uint32_t op1, uint32_t op2, uint64_t acc) +__attribute__((always_inline)) __STATIC_INLINE uint64_t __SMLALDX(uint32_t op1, uint32_t op2, uint64_t acc) { - union llreg_u{ - uint32_t w32[2]; - uint64_t w64; - } llr; - llr.w64 = acc; + union llreg_u + { + uint32_t w32[2]; + uint64_t w64; + } llr; + llr.w64 = acc; -#ifndef __ARMEB__ // Little endian - __ASM volatile ("smlaldx %0, %1, %2, %3" : "=r" (llr.w32[0]), "=r" (llr.w32[1]): "r" (op1), "r" (op2) , "0" (llr.w32[0]), "1" (llr.w32[1]) ); -#else // Big endian - __ASM volatile ("smlaldx %0, %1, %2, %3" : "=r" (llr.w32[1]), "=r" (llr.w32[0]): "r" (op1), "r" (op2) , "0" (llr.w32[1]), "1" (llr.w32[0]) ); +#ifndef __ARMEB__ // Little endian + __ASM volatile("smlaldx %0, %1, %2, %3" + : "=r"(llr.w32[0]), "=r"(llr.w32[1]) + : "r"(op1), "r"(op2), "0"(llr.w32[0]), "1"(llr.w32[1])); +#else // Big endian + __ASM volatile("smlaldx %0, %1, %2, %3" + : "=r"(llr.w32[1]), "=r"(llr.w32[0]) + : "r"(op1), "r"(op2), "0"(llr.w32[1]), "1"(llr.w32[0])); #endif - return(llr.w64); + return (llr.w64); } -__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SMUSD (uint32_t op1, uint32_t op2) +__attribute__((always_inline)) __STATIC_INLINE uint32_t __SMUSD(uint32_t op1, uint32_t op2) { - uint32_t result; + uint32_t result; - __ASM volatile ("smusd %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); - return(result); + __ASM volatile("smusd %0, %1, %2" + : "=r"(result) + : "r"(op1), "r"(op2)); + return (result); } -__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SMUSDX (uint32_t op1, uint32_t op2) +__attribute__((always_inline)) __STATIC_INLINE uint32_t __SMUSDX(uint32_t op1, uint32_t op2) { - uint32_t result; + uint32_t result; - __ASM volatile ("smusdx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); - return(result); + __ASM volatile("smusdx %0, %1, %2" + : "=r"(result) + : "r"(op1), "r"(op2)); + return (result); } -__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SMLSD (uint32_t op1, uint32_t op2, uint32_t op3) +__attribute__((always_inline)) __STATIC_INLINE uint32_t __SMLSD(uint32_t op1, uint32_t op2, uint32_t op3) { - uint32_t result; + uint32_t result; - __ASM volatile ("smlsd %0, %1, %2, %3" : "=r" (result) : "r" (op1), "r" (op2), "r" (op3) ); - return(result); + __ASM volatile("smlsd %0, %1, %2, %3" + : "=r"(result) + : "r"(op1), "r"(op2), "r"(op3)); + return (result); } -__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SMLSDX (uint32_t op1, uint32_t op2, uint32_t op3) +__attribute__((always_inline)) __STATIC_INLINE uint32_t __SMLSDX(uint32_t op1, uint32_t op2, uint32_t op3) { - uint32_t result; + uint32_t result; - __ASM volatile ("smlsdx %0, %1, %2, %3" : "=r" (result) : "r" (op1), "r" (op2), "r" (op3) ); - return(result); + __ASM volatile("smlsdx %0, %1, %2, %3" + : "=r"(result) + : "r"(op1), "r"(op2), "r"(op3)); + return (result); } -__attribute__( ( always_inline ) ) __STATIC_INLINE uint64_t __SMLSLD (uint32_t op1, uint32_t op2, uint64_t acc) +__attribute__((always_inline)) __STATIC_INLINE uint64_t __SMLSLD(uint32_t op1, uint32_t op2, uint64_t acc) { - union llreg_u{ - uint32_t w32[2]; - uint64_t w64; - } llr; - llr.w64 = acc; + union llreg_u + { + uint32_t w32[2]; + uint64_t w64; + } llr; + llr.w64 = acc; -#ifndef __ARMEB__ // Little endian - __ASM volatile ("smlsld %0, %1, %2, %3" : "=r" (llr.w32[0]), "=r" (llr.w32[1]): "r" (op1), "r" (op2) , "0" (llr.w32[0]), "1" (llr.w32[1]) ); -#else // Big endian - __ASM volatile ("smlsld %0, %1, %2, %3" : "=r" (llr.w32[1]), "=r" (llr.w32[0]): "r" (op1), "r" (op2) , "0" (llr.w32[1]), "1" (llr.w32[0]) ); +#ifndef __ARMEB__ // Little endian + __ASM volatile("smlsld %0, %1, %2, %3" + : "=r"(llr.w32[0]), "=r"(llr.w32[1]) + : "r"(op1), "r"(op2), "0"(llr.w32[0]), "1"(llr.w32[1])); +#else // Big endian + __ASM volatile("smlsld %0, %1, %2, %3" + : "=r"(llr.w32[1]), "=r"(llr.w32[0]) + : "r"(op1), "r"(op2), "0"(llr.w32[1]), "1"(llr.w32[0])); #endif - return(llr.w64); + return (llr.w64); } -__attribute__( ( always_inline ) ) __STATIC_INLINE uint64_t __SMLSLDX (uint32_t op1, uint32_t op2, uint64_t acc) +__attribute__((always_inline)) __STATIC_INLINE uint64_t __SMLSLDX(uint32_t op1, uint32_t op2, uint64_t acc) { - union llreg_u{ - uint32_t w32[2]; - uint64_t w64; - } llr; - llr.w64 = acc; + union llreg_u + { + uint32_t w32[2]; + uint64_t w64; + } llr; + llr.w64 = acc; -#ifndef __ARMEB__ // Little endian - __ASM volatile ("smlsldx %0, %1, %2, %3" : "=r" (llr.w32[0]), "=r" (llr.w32[1]): "r" (op1), "r" (op2) , "0" (llr.w32[0]), "1" (llr.w32[1]) ); -#else // Big endian - __ASM volatile ("smlsldx %0, %1, %2, %3" : "=r" (llr.w32[1]), "=r" (llr.w32[0]): "r" (op1), "r" (op2) , "0" (llr.w32[1]), "1" (llr.w32[0]) ); +#ifndef __ARMEB__ // Little endian + __ASM volatile("smlsldx %0, %1, %2, %3" + : "=r"(llr.w32[0]), "=r"(llr.w32[1]) + : "r"(op1), "r"(op2), "0"(llr.w32[0]), "1"(llr.w32[1])); +#else // Big endian + __ASM volatile("smlsldx %0, %1, %2, %3" + : "=r"(llr.w32[1]), "=r"(llr.w32[0]) + : "r"(op1), "r"(op2), "0"(llr.w32[1]), "1"(llr.w32[0])); #endif - return(llr.w64); + return (llr.w64); } -__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SEL (uint32_t op1, uint32_t op2) +__attribute__((always_inline)) __STATIC_INLINE uint32_t __SEL(uint32_t op1, uint32_t op2) { - uint32_t result; + uint32_t result; - __ASM volatile ("sel %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); - return(result); + __ASM volatile("sel %0, %1, %2" + : "=r"(result) + : "r"(op1), "r"(op2)); + return (result); } -__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __QADD(uint32_t op1, uint32_t op2) +__attribute__((always_inline)) __STATIC_INLINE uint32_t __QADD(uint32_t op1, uint32_t op2) { - uint32_t result; + uint32_t result; - __ASM volatile ("qadd %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); - return(result); + __ASM volatile("qadd %0, %1, %2" + : "=r"(result) + : "r"(op1), "r"(op2)); + return (result); } -__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __QSUB(uint32_t op1, uint32_t op2) +__attribute__((always_inline)) __STATIC_INLINE uint32_t __QSUB(uint32_t op1, uint32_t op2) { - uint32_t result; + uint32_t result; - __ASM volatile ("qsub %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); - return(result); + __ASM volatile("qsub %0, %1, %2" + : "=r"(result) + : "r"(op1), "r"(op2)); + return (result); } -#define __PKHBT(ARG1,ARG2,ARG3) \ -({ \ - uint32_t __RES, __ARG1 = (ARG1), __ARG2 = (ARG2); \ - __ASM ("pkhbt %0, %1, %2, lsl %3" : "=r" (__RES) : "r" (__ARG1), "r" (__ARG2), "I" (ARG3) ); \ - __RES; \ - }) +#define __PKHBT(ARG1, ARG2, ARG3) \ + ( \ + { \ + uint32_t __RES, __ARG1 = (ARG1), __ARG2 = (ARG2); \ + __ASM("pkhbt %0, %1, %2, lsl %3" \ + : "=r"(__RES) \ + : "r"(__ARG1), "r"(__ARG2), "I"(ARG3)); \ + __RES; \ + }) -#define __PKHTB(ARG1,ARG2,ARG3) \ -({ \ - uint32_t __RES, __ARG1 = (ARG1), __ARG2 = (ARG2); \ - if (ARG3 == 0) \ - __ASM ("pkhtb %0, %1, %2" : "=r" (__RES) : "r" (__ARG1), "r" (__ARG2) ); \ - else \ - __ASM ("pkhtb %0, %1, %2, asr %3" : "=r" (__RES) : "r" (__ARG1), "r" (__ARG2), "I" (ARG3) ); \ - __RES; \ - }) +#define __PKHTB(ARG1, ARG2, ARG3) \ + ( \ + { \ + uint32_t __RES, __ARG1 = (ARG1), __ARG2 = (ARG2); \ + if (ARG3 == 0) \ + __ASM("pkhtb %0, %1, %2" \ + : "=r"(__RES) \ + : "r"(__ARG1), "r"(__ARG2)); \ + else \ + __ASM("pkhtb %0, %1, %2, asr %3" \ + : "=r"(__RES) \ + : "r"(__ARG1), "r"(__ARG2), "I"(ARG3)); \ + __RES; \ + }) -__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SMMLA (int32_t op1, int32_t op2, int32_t op3) +__attribute__((always_inline)) __STATIC_INLINE uint32_t __SMMLA(int32_t op1, int32_t op2, int32_t op3) { - int32_t result; + int32_t result; - __ASM volatile ("smmla %0, %1, %2, %3" : "=r" (result): "r" (op1), "r" (op2), "r" (op3) ); - return(result); + __ASM volatile("smmla %0, %1, %2, %3" + : "=r"(result) + : "r"(op1), "r"(op2), "r"(op3)); + return (result); } - -#elif defined ( __ICCARM__ ) /*------------------ ICC Compiler -------------------*/ +#elif defined(__ICCARM__) /*------------------ ICC Compiler -------------------*/ /* IAR iccarm specific functions */ #include - -#elif defined ( __TMS470__ ) /*---------------- TI CCS Compiler ------------------*/ +#elif defined(__TMS470__) /*---------------- TI CCS Compiler ------------------*/ /* TI CCS specific functions */ #include - -#elif defined ( __TASKING__ ) /*------------------ TASKING Compiler --------------*/ +#elif defined(__TASKING__) /*------------------ TASKING Compiler --------------*/ /* TASKING carm specific functions */ /* not yet supported */ - -#elif defined ( __CSMC__ ) /*------------------ COSMIC Compiler -------------------*/ +#elif defined(__CSMC__) /*------------------ COSMIC Compiler -------------------*/ /* Cosmic specific functions */ #include #endif -/*@} end of group CMSIS_SIMD_intrinsics */ - + /*@} end of group CMSIS_SIMD_intrinsics */ #ifdef __cplusplus } diff --git a/bsp/swm320-lq100/Libraries/CMSIS/DeviceSupport/SWM320.h b/bsp/swm320-lq100/Libraries/CMSIS/DeviceSupport/SWM320.h index 79d9baa156..8e4a3e041c 100644 --- a/bsp/swm320-lq100/Libraries/CMSIS/DeviceSupport/SWM320.h +++ b/bsp/swm320-lq100/Libraries/CMSIS/DeviceSupport/SWM320.h @@ -68,7 +68,7 @@ typedef enum IRQn SPI0_IRQn = 46, ADC0_IRQn = 47, RTC_IRQn = 48, - ANAC_IRQn = 49, + BOD_IRQn = 49, SDIO_IRQn = 50, GPIOA_IRQn = 51, GPIOB_IRQn = 52, @@ -96,16 +96,16 @@ typedef enum IRQn /* Configuration of the Cortex-M0 Processor and Core Peripherals */ #define __CM4_REV 0x0001 /*!< Core revision r0p1 */ #define __MPU_PRESENT 1 /*!< SWM320 provides an MPU */ -#define __NVIC_PRIO_BITS 4 /*!< SWM320 uses 4 Bits for the Priority Levels */ +#define __NVIC_PRIO_BITS 3 /*!< SWM320 uses 3 Bits for the Priority Levels */ #define __Vendor_SysTickConfig 0 /*!< Set to 1 if different SysTick Config is used */ -#define __FPU_PRESENT 1 /*!< FPU present */ +#define __FPU_PRESENT 0 /*!< FPU present */ #if defined(__CC_ARM) - #pragma anon_unions +#pragma anon_unions #endif #include -#include "core_cm4.h" /* Cortex-M0 processor and core peripherals */ +#include "core_cm4.h" /* Cortex-M0 processor and core peripherals */ #include "system_SWM320.h" /******************************************************************************/ @@ -123,9 +123,9 @@ typedef struct uint32_t RESERVED0[6]; - __IO uint32_t RTCBKP_ISO; //[0] 1 RTC闁跨喐鏋婚幏鐑芥晸閹归顣幏閿嬬爱闁跨喐鏋婚幏鐑芥晸閼哄倿娼婚幏鐑芥晸閺傘倖瀚归悩鑸碘偓锟� 0 RTC闁跨喐鏋婚幏鐑芥晸閹归顣幏閿嬬爱闁跨喐鏋婚幏椋庡幖闁跨喐鏋婚幏鐑芥晸閿燂拷 + __IO uint32_t RTCBKP_ISO; //[0] 1 RTC备份电源域处于隔离状态 0 RTC备份电源域可访问 - __IO uint32_t RTCWKEN; //[0] 1 娴ｅ潡鏁撻弬銈嗗RTC闁跨喐鏋婚幏鐑芥晸缁愭牜娅㈤幏鐑芥晸閺傘倖瀚� + __IO uint32_t RTCWKEN; //[0] 1 使能RTC唤醒功能 uint32_t RESERVED[52 + 64]; @@ -135,25 +135,23 @@ typedef struct uint32_t RESERVED2[1 + 4]; - __IO uint32_t PAWKSR; //Port A Wakeup Status Register闁跨喐鏋婚幏宄板晸1闁跨喐鏋婚幏鐑芥晸閺傘倖瀚� + __IO uint32_t PAWKSR; //Port A Wakeup Status Register，写1清零 __IO uint32_t PBWKSR; __IO uint32_t PCWKSR; - uint32_t RESERVED3[64 - 11]; - - __IO uint32_t REMAP; //0 闁跨喐鏋婚幏鐑芥晸閺傘倖瀚归柨鐔告灮閹风úOM闁跨喐鏋婚幏閿嬪⒔闁跨喐鏋婚幏锟� 1 闁跨喐鏋婚幏鐑芥晸閺傘倖瀚归柨鐔告灮閹风éLASH闁跨喐鏋婚幏閿嬪⒔闁跨喐鏋婚幏锟� + uint32_t RESERVED3[64 - 10]; __IO uint32_t RSTCR; //Reset Control Register __IO uint32_t RSTSR; //Reset Status Register uint32_t RESERVED4[61 + 64]; - __IO uint32_t BKP[3]; //闁跨喐鏋婚幏鐑芥晸閹归攱鍞婚幏鐑芥晸閹瑰嘲鐦庢潏鐐闁跨喐鏋婚幏锟� + __IO uint32_t BKP[3]; //数据备份寄存器 //RTC Power Domain: 0x4001E000 uint32_t RESERVED5[(0x4001E000 - 0x40000508) / 4 - 1]; - __IO uint32_t RTCBKP[8]; //RTC闁跨喐鏋婚幏閿嬬爱闁跨喐鏋婚幏鐑芥晸閺傘倖瀚归柨鐔稿祹閹插瀚归柨鐔稿祹鐎靛嫯鎻幏鐑芥晸閺傘倖瀚� + __IO uint32_t RTCBKP[8]; //RTC电源域数据备份寄存器 __IO uint32_t LRCCR; //Low speed RC Control Register __IO uint32_t LRCTRIM0; //Low speed RC Trim @@ -166,45 +164,37 @@ typedef struct //Analog Control: 0x40031000 uint32_t RESERVED7[(0x40031000 - 0x4001E030) / 4 - 1]; - __IO uint32_t HRCCR; //High speed RC Control Register - __IO uint32_t HRC20M; //[24:0] High speed RC Trim Value for 20MHz - __IO uint32_t HRC40M; //[24:0] High speed RC Trim Value for 40MHz - - uint32_t RESERVED8[3]; - - __IO uint32_t BGTRIM; + __IO uint32_t HRCCR; //High speed RC Control Register - __IO uint32_t TEMPCR; //闁跨喖鎽惔锕佹彧閹风兘鏁撻弬銈嗗闁跨喐鏋婚幏鐑芥晸閺傘倖瀚归柨鐔哄珱鐎靛嫯鎻幏鐑芥晸閺傘倖瀚� + uint32_t RESERVED8[7]; __IO uint32_t XTALCR; __IO uint32_t PLLCR; __IO uint32_t PLLDIV; __IO uint32_t PLLSET; - __IO uint32_t PLLLOCK; //[0] 1 PLL闁跨喐鏋婚幏鐑芥晸閺傘倖瀚归柨鐔告灮閹凤拷 + __IO uint32_t PLLLOCK; //[0] 1 PLL已锁定 __IO uint32_t BODIE; __IO uint32_t BODIF; __IO uint32_t ADC1IN7; - - __IO uint32_t BODCR; } SYS_TypeDef; -#define SYS_CLKSEL_LFCK_Pos 0 //Low Frequency Clock Source 0 LRC 1 PLL +#define SYS_CLKSEL_LFCK_Pos 0 //Low Frequency Clock Source 0 LRC 1 PLL #define SYS_CLKSEL_LFCK_Msk (0x01 << SYS_CLKSEL_LFCK_Pos) -#define SYS_CLKSEL_HFCK_Pos 1 //High Frequency Clock Source 0 HRC 1 XTAL +#define SYS_CLKSEL_HFCK_Pos 1 //High Frequency Clock Source 0 HRC 1 XTAL #define SYS_CLKSEL_HFCK_Msk (0x01 << SYS_CLKSEL_HFCK_Pos) -#define SYS_CLKSEL_SYS_Pos 2 //缁崵绮洪弮鍫曟晸閺傘倖瀚归柅澶愭晸閺傘倖瀚� 0 LFCK 1 HFCK +#define SYS_CLKSEL_SYS_Pos 2 //系统时钟选择 0 LFCK 1 HFCK #define SYS_CLKSEL_SYS_Msk (0x01 << SYS_CLKSEL_SYS_Pos) -#define SYS_CLKDIV_SYS_Pos 0 //缁崵绮洪弮鍫曟晸閹恒儱鍤栭幏鐑筋暥 0 1闁跨喐鏋婚幏鐑筋暥 1 2闁跨喐鏋婚幏鐑筋暥 +#define SYS_CLKDIV_SYS_Pos 0 //系统时钟分频 0 1分频 1 2分频 #define SYS_CLKDIV_SYS_Msk (0x01 << SYS_CLKDIV_SYS_Pos) -#define SYS_CLKDIV_PWM_Pos 1 //PWM 閺冨爼鏁撻幒銉ュ殩閹风兘顣� 0 1闁跨喐鏋婚幏鐑筋暥 1 8闁跨喐鏋婚幏鐑筋暥 +#define SYS_CLKDIV_PWM_Pos 1 //PWM 时钟分频 0 1分频 1 8分频 #define SYS_CLKDIV_PWM_Msk (0x01 << SYS_CLKDIV_PWM_Pos) -#define SYS_CLKDIV_SDRAM_Pos 2 //SDRAM閺冨爼鏁撻幒銉ュ殩閹风兘顣� 0 1闁跨喐鏋婚幏鐑筋暥 1 2闁跨喐鏋婚幏鐑筋暥 2 4闁跨喐鏋婚幏鐑筋暥 +#define SYS_CLKDIV_SDRAM_Pos 2 //SDRAM时钟分频 0 1分频 1 2分频 2 4分频 #define SYS_CLKDIV_SDRAM_Msk (0x03 << SYS_CLKDIV_SDRAM_Pos) -#define SYS_CLKDIV_SDIO_Pos 4 //SDIO閺冨爼鏁撻幒銉ュ殩閹风兘顣� 0 1闁跨喐鏋婚幏鐑筋暥 1 2闁跨喐鏋婚幏鐑筋暥 2 4闁跨喐鏋婚幏鐑筋暥 3 8闁跨喐鏋婚幏鐑筋暥 +#define SYS_CLKDIV_SDIO_Pos 4 //SDIO时钟分频 0 1分频 1 2分频 2 4分频 3 8分频 #define SYS_CLKDIV_SDIO_Msk (0x03 << SYS_CLKDIV_SDIO_Pos) #define SYS_CLKEN_GPIOA_Pos 0 @@ -249,7 +239,7 @@ typedef struct #define SYS_CLKEN_LCD_Msk (0x01 << SYS_CLKEN_LCD_Pos) #define SYS_CLKEN_GPIOP_Pos 21 #define SYS_CLKEN_GPIOP_Msk (0x01 << SYS_CLKEN_GPIOP_Pos) -#define SYS_CLKEN_ANAC_Pos 22 //濡繝鏁撻弬銈嗗闁跨喐鏋婚幏鐑筋暥闁跨喓娈曢鈺傚敾閹风兘鏁撶紒鐐垫閹风兘鏁撻敓锟� +#define SYS_CLKEN_ANAC_Pos 22 //模拟控制单元时钟使能 #define SYS_CLKEN_ANAC_Msk (0x01 << SYS_CLKEN_ANAC_Pos) #define SYS_CLKEN_CRC_Pos 23 #define SYS_CLKEN_CRC_Msk (0x01 << SYS_CLKEN_CRC_Pos) @@ -267,59 +257,59 @@ typedef struct #define SYS_CLKEN_SDIO_Msk (0x01 << SYS_CLKEN_SDIO_Pos) #define SYS_CLKEN_ADC1_Pos 30 #define SYS_CLKEN_ADC1_Msk (0x01 << SYS_CLKEN_ADC1_Pos) -#define SYS_CLKEN_ALIVE_Pos 31 //CHIPALIVE闁跨喐鏋婚幏閿嬬爱闁跨喐鏋婚幏椋庨兇缂佺喐妞傞柨鐔告灮閹疯渹濞囬柨鐔告灮閹凤拷 +#define SYS_CLKEN_ALIVE_Pos 31 //CHIPALIVE电源域系统时钟使能 #define SYS_CLKEN_ALIVE_Msk (0x01 << SYS_CLKEN_ALIVE_Pos) -#define SYS_SLEEP_SLEEP_Pos 0 //闁跨喐鏋婚幏鐑芥晸閺傘倖瀚规担宥夋晸閺傘倖瀚�1闁跨喐鏋婚幏椋庨兇缂佺喖鏁撻弬銈嗗闁跨喐鏋婚幏鐑芥晸閺傘倖瀚筍LEEP濡€崇础 +#define SYS_SLEEP_SLEEP_Pos 0 //将该位置1后，系统将进入SLEEP模式 #define SYS_SLEEP_SLEEP_Msk (0x01 << SYS_SLEEP_SLEEP_Pos) -#define SYS_SLEEP_DEEP_Pos 1 //闁跨喐鏋婚幏鐑芥晸閺傘倖瀚规担宥夋晸閺傘倖瀚�1闁跨喐鏋婚幏椋庨兇缂佺喖鏁撻弬銈嗗闁跨喐鏋婚幏鐑芥晸閺傘倖瀚筍TOP SLEEP濡€崇础 +#define SYS_SLEEP_DEEP_Pos 1 //将该位置1后，系统将进入STOP SLEEP模式 #define SYS_SLEEP_DEEP_Msk (0x01 << SYS_SLEEP_DEEP_Pos) -#define SYS_RSTCR_SYS_Pos 0 //閸愶拷1闁跨喐鏋婚幏鐑芥晸閺傘倖瀚圭化鑽ょ埠闁跨喐鏋婚幏铚傜秴闁跨喐鏋婚幏椋庘€栭柨鐔告灮閹风兘鏁撻惃鍡氼啇閹风兘鏁撻弬銈嗗闁跨喐鏋婚幏锟� +#define SYS_RSTCR_SYS_Pos 0 //写1进行系统复位，硬件自动清零 #define SYS_RSTCR_SYS_Msk (0x01 << SYS_RSTCR_SYS_Pos) -#define SYS_RSTCR_FLASH_Pos 1 //閸愶拷1闁跨喐鏋婚幏绋ASH闁跨喐鏋婚幏鐑芥晸閺傘倖瀚归柨鐔告灮閹风兘鏁撻弬銈嗗闁跨喐鏋婚幏铚傜闁跨喕濞囬棃鈺傚娴ｅ秹鏁撻弬銈嗗绾剟鏁撻弬銈嗗闁跨喓娈曠拋瑙勫闁跨喐鏋婚幏鐑芥晸閺傘倖瀚� +#define SYS_RSTCR_FLASH_Pos 1 //写1对FLASH控制器进行一次复位，硬件自动清零 #define SYS_RSTCR_FLASH_Msk (0x01 << SYS_RSTCR_FLASH_Pos) -#define SYS_RSTCR_PWM_Pos 2 //閸愶拷1闁跨喐鏋婚幏绋癢M闁跨喐鏋婚幏鐑芥晸閺傘倖瀚规稉鈧柨鐔诲▏闂堚晜瀚规担宥夋晸閺傘倖瀚圭涵顒勬晸閺傘倖瀚归柨鐔烘畷鐠佽瀚归柨鐔告灮閹风兘鏁撻弬銈嗗 +#define SYS_RSTCR_PWM_Pos 2 //写1对PWM进行一次复位，硬件自动清零 #define SYS_RSTCR_PWM_Msk (0x01 << SYS_RSTCR_PWM_Pos) -#define SYS_RSTCR_CPU_Pos 3 //閸愶拷1闁跨喐鏋婚幏绋U闁跨喐鏋婚幏鐑芥晸閺傘倖瀚规稉鈧柨鐔诲▏闂堚晜瀚规担宥夋晸閺傘倖瀚圭涵顒勬晸閺傘倖瀚归柨鐔烘畷鐠佽瀚归柨鐔告灮閹风兘鏁撻弬銈嗗 +#define SYS_RSTCR_CPU_Pos 3 //写1对CPU进行一次复位，硬件自动清零 #define SYS_RSTCR_CPU_Msk (0x01 << SYS_RSTCR_CPU_Pos) -#define SYS_RSTCR_DMA_Pos 4 //閸愶拷1闁跨喐鏋婚幏绋A闁跨喐鏋婚幏鐑芥晸閺傘倖瀚规稉鈧柨鐔诲▏闂堚晜瀚规担宥夋晸閺傘倖瀚圭涵顒勬晸閺傘倖瀚归柨鐔烘畷鐠佽瀚归柨鐔告灮閹风兘鏁撻弬銈嗗 +#define SYS_RSTCR_DMA_Pos 4 //写1对DMA进行一次复位，硬件自动清零 #define SYS_RSTCR_DMA_Msk (0x01 << SYS_RSTCR_DMA_Pos) -#define SYS_RSTCR_NORFLASH_Pos 5 //閸愶拷1闁跨喐鏋婚幏绋甇R Flash闁跨喐鏋婚幏鐑芥晸閺傘倖瀚归柨鐔告灮閹风兘鏁撻弬銈嗗闁跨喐鏋婚幏铚傜闁跨喕濞囬棃鈺傚娴ｅ秹鏁撻弬銈嗗绾剟鏁撻弬銈嗗闁跨喓娈曠拋瑙勫闁跨喐鏋婚幏鐑芥晸閺傘倖瀚� +#define SYS_RSTCR_NORFLASH_Pos 5 //写1对NOR Flash控制器进行一次复位，硬件自动清零 #define SYS_RSTCR_NORFLASH_Msk (0x01 << SYS_RSTCR_NORFLASH_Pos) -#define SYS_RSTCR_SRAM_Pos 6 //閸愶拷1闁跨喐鏋婚幏绋碦AM闁跨喐鏋婚幏鐑芥晸閺傘倖瀚归柨鐔告灮閹风兘鏁撻弬銈嗗闁跨喐鏋婚幏铚傜闁跨喕濞囬棃鈺傚娴ｅ秹鏁撻弬銈嗗绾剟鏁撻弬銈嗗闁跨喓娈曠拋瑙勫闁跨喐鏋婚幏鐑芥晸閺傘倖瀚� +#define SYS_RSTCR_SRAM_Pos 6 //写1对SRAM控制器进行一次复位，硬件自动清零 #define SYS_RSTCR_SRAM_Msk (0x01 << SYS_RSTCR_SRAM_Pos) -#define SYS_RSTCR_SDRAM_Pos 7 //閸愶拷1闁跨喐鏋婚幏绋碊RAM闁跨喐鏋婚幏鐑芥晸閺傘倖瀚归柨鐔告灮閹风兘鏁撻弬銈嗗闁跨喐鏋婚幏铚傜闁跨喕濞囬棃鈺傚娴ｅ秹鏁撻弬銈嗗绾剟鏁撻弬銈嗗闁跨喓娈曠拋瑙勫闁跨喐鏋婚幏鐑芥晸閺傘倖瀚� +#define SYS_RSTCR_SDRAM_Pos 7 //写1对SDRAM控制器进行一次复位，硬件自动清零 #define SYS_RSTCR_SDRAM_Msk (0x01 << SYS_RSTCR_SDRAM_Pos) -#define SYS_RSTCR_SDIO_Pos 8 //閸愶拷1闁跨喐鏋婚幏绋碊IO闁跨喐鏋婚幏鐑芥晸閺傘倖瀚规稉鈧柨鐔诲▏闂堚晜瀚规担宥夋晸閺傘倖瀚圭涵顒勬晸閺傘倖瀚归柨鐔烘畷鐠佽瀚归柨鐔告灮閹风兘鏁撻弬銈嗗 +#define SYS_RSTCR_SDIO_Pos 8 //写1对SDIO进行一次复位，硬件自动清零 #define SYS_RSTCR_SDIO_Msk (0x01 << SYS_RSTCR_SDIO_Pos) -#define SYS_RSTCR_LCD_Pos 9 //閸愶拷1闁跨喐鏋婚幏绋珻D闁跨喐鏋婚幏鐑芥晸閺傘倖瀚规稉鈧柨鐔诲▏闂堚晜瀚规担宥夋晸閺傘倖瀚圭涵顒勬晸閺傘倖瀚归柨鐔烘畷鐠佽瀚归柨鐔告灮閹风兘鏁撻弬銈嗗 +#define SYS_RSTCR_LCD_Pos 9 //写1对LCD进行一次复位，硬件自动清零 #define SYS_RSTCR_LCD_Msk (0x01 << SYS_RSTCR_LCD_Pos) -#define SYS_RSTCR_CAN_Pos 10 //閸愶拷1闁跨喐鏋婚幏绋N闁跨喐鏋婚幏鐑芥晸閺傘倖瀚规稉鈧柨鐔诲▏闂堚晜瀚规担宥夋晸閺傘倖瀚圭涵顒勬晸閺傘倖瀚归柨鐔烘畷鐠佽瀚归柨鐔告灮閹风兘鏁撻弬銈嗗 +#define SYS_RSTCR_CAN_Pos 10 //写1对CAN进行一次复位，硬件自动清零 #define SYS_RSTCR_CAN_Msk (0x01 << SYS_RSTCR_CAN_Pos) -#define SYS_RSTSR_POR_Pos 0 //1 闁跨喐鏋婚幏鐑芥晸鐞涙娅㈤幏绋癘R闁跨喐鏋婚幏铚傜秴闁跨喐鏋婚幏宄板晸1闁跨喐鏋婚幏鐑芥晸閺傘倖瀚� +#define SYS_RSTSR_POR_Pos 0 //1 出现过POR复位，写1清零 #define SYS_RSTSR_POR_Msk (0x01 << SYS_RSTSR_POR_Pos) -#define SYS_RSTSR_BOD_Pos 1 //1 闁跨喐鏋婚幏鐑芥晸鐞涙娅㈤幏绋D闁跨喐鏋婚幏铚傜秴闁跨喐鏋婚幏宄板晸1闁跨喐鏋婚幏鐑芥晸閺傘倖瀚� +#define SYS_RSTSR_BOD_Pos 1 //1 出现过BOD复位，写1清零 #define SYS_RSTSR_BOD_Msk (0x01 << SYS_RSTSR_BOD_Pos) -#define SYS_RSTSR_PIN_Pos 2 //1 闁跨喐鏋婚幏鐑芥晸鐞涙娅㈤幏鐑芥晸鐟欙綁鍎撮柨鐔告灮閹风兘鏁撻懘姘舵交閹疯渹缍呴柨鐔告灮閹峰嘲鍟�1闁跨喐鏋婚幏鐑芥晸閺傘倖瀚� +#define SYS_RSTSR_PIN_Pos 2 //1 出现过外部引脚复位，写1清零 #define SYS_RSTSR_PIN_Msk (0x01 << SYS_RSTSR_PIN_Pos) -#define SYS_RSTSR_WDT_Pos 3 //1 闁跨喐鏋婚幏鐑芥晸鐞涙娅㈤幏绋篋T闁跨喐鏋婚幏铚傜秴闁跨喐鏋婚幏宄板晸1闁跨喐鏋婚幏鐑芥晸閺傘倖瀚� +#define SYS_RSTSR_WDT_Pos 3 //1 出现过WDT复位，写1清零 #define SYS_RSTSR_WDT_Msk (0x01 << SYS_RSTSR_WDT_Pos) -#define SYS_RSTSR_SWRST_Pos 4 //Software Reset, 1 闁跨喐鏋婚幏鐑芥晸鐞涙娅㈤幏鐑芥晸閺傘倖瀚归柨鐔告灮閹风兘鏁撴潪澶哥串閹风兘鏁撻崣顐嫹1闁跨喐鏋婚幏鐑芥晸閺傘倖瀚� +#define SYS_RSTSR_SWRST_Pos 4 //Software Reset, 1 出现过软件复位，写1清零 #define SYS_RSTSR_SWRST_Msk (0x01 << SYS_RSTSR_SWRST_Pos) #define SYS_LRCCR_OFF_Pos 0 //Low Speed RC Off #define SYS_LRCCR_OFF_Msk (0x01 << SYS_LRCCR_OFF_Pos) -#define SYS_LRCTRIM0_R_Pos 0 //LRC闁跨喕顢滅喊澶嬪闁跨喐鏋婚幏鐑芥晸閺傘倖瀚规担锟� +#define SYS_LRCTRIM0_R_Pos 0 //LRC粗调控制位 #define SYS_LRCTRIM0_R_Msk (0x7FFF << SYS_LRCTRIM0_R_Pos) -#define SYS_LRCTRIM0_M_Pos 15 //LRC闁跨喎褰ㄧ喊澶嬪闁跨喐鏋婚幏鐑芥晸閺傘倖瀚规担锟� +#define SYS_LRCTRIM0_M_Pos 15 //LRC中调控制位 #define SYS_LRCTRIM0_M_Msk (0x3F << SYS_LRCTRIM2_M_Pos) -#define SYS_LRCTRIM0_F_Pos 21 //LRC缂佸棝鏁撻弬銈嗗闁跨喐鏋婚幏鐑芥晸閺傘倖瀚规担锟� +#define SYS_LRCTRIM0_F_Pos 21 //LRC细调控制位 #define SYS_LRCTRIM0_F_Msk (0x7FF << SYS_LRCTRIM0_F_Pos) -#define SYS_LRCTRIM1_U_Pos 0 //LRC U闁跨喐鏋婚幏鐑芥晸閺傘倖瀚归柨鐔告灮閹疯渹缍� +#define SYS_LRCTRIM1_U_Pos 0 //LRC U调控制位 #define SYS_LRCTRIM1_U_Msk (0x7FFF << SYS_LRCTRIM1_U_Pos) #define SYS_HRCCR_DBL_Pos 0 //Double Frequency 0 20MHz 1 40MHz @@ -327,42 +317,27 @@ typedef struct #define SYS_HRCCR_OFF_Pos 1 //High speed RC Off #define SYS_HRCCR_OFF_Msk (0x01 << SYS_HRCCR_OFF_Pos) -#define SYS_HRC20M_R_Pos 0 //HRC 20MHz闁跨喕顢滅喊澶嬪闁跨喐鏋婚幏鐑芥晸閺傘倖瀚规担锟� -#define SYS_HRC20M_R_Msk (0x3FFF << SYS_HRC20M_R_Pos) -#define SYS_HRC20M_F_Pos 16 //HRC 20MHz缂佸棝鏁撻弬銈嗗闁跨喐鏋婚幏鐑芥晸閺傘倖瀚规担锟� -#define SYS_HRC20M_F_Msk (0x7FF << SYS_HRC20M_F_Pos) - -#define SYS_HRC40M_R_Pos 0 //HRC 40MHz闁跨喕顢滅喊澶嬪闁跨喐鏋婚幏鐑芥晸閺傘倖瀚规担锟� -#define SYS_HRC40M_R_Msk (0x3FFF << SYS_HRC40M_R_Pos) -#define SYS_HRC40M_F_Pos 16 //HRC 40MHz缂佸棝鏁撻弬銈嗗闁跨喐鏋婚幏鐑芥晸閺傘倖瀚规担锟� -#define SYS_HRC40M_F_Msk (0x7FF << SYS_HRC40M_F_Pos) - -#define SYS_TEMPCR_OFF_Pos 0 //闁跨喖鎽惔锕佹彧閹风兘鏁撻弬銈嗗闁跨喐鏋婚幏鐑芥晸閹搭亝鍞婚幏锟� -#define SYS_TEMPCR_OFF_Msk (0x01 << SYS_TEMPCR_OFF_Pos) -#define SYS_TEMPCR_TRIM_Pos 4 //闁跨喖鎽惔锕佹彧閹风兘鏁撻弬銈嗗闁跨喐鏋婚幏绋礡IM -#define SYS_TEMPCR_TRIM_Msk (0x3F << SYS_TEMPCR_TRIM_Pos) - #define SYS_XTALCR_EN_Pos 0 #define SYS_XTALCR_EN_Msk (0x01 << SYS_XTALCR_EN_Pos) -#define SYS_PLLCR_OUTEN_Pos 0 //閸欘亪鏁撻弬銈嗗LOCK闁跨喐鏋婚幏鐑芥晸閺傘倖瀚归柨鐔告灮閹凤拷 +#define SYS_PLLCR_OUTEN_Pos 0 //只能LOCK后设置 #define SYS_PLLCR_OUTEN_Msk (0x01 << SYS_PLLCR_OUTEN_Pos) #define SYS_PLLCR_INSEL_Pos 1 //0 XTAL 1 HRC #define SYS_PLLCR_INSEL_Msk (0x01 << SYS_PLLCR_INSEL_Pos) #define SYS_PLLCR_OFF_Pos 2 #define SYS_PLLCR_OFF_Msk (0x01 << SYS_PLLCR_OFF_Pos) -#define SYS_PLLDIV_FBDIV_Pos 0 //PLL FeedBack闁跨喐鏋婚幏鐑筋暥闁跨喍鑼庢潏鐐闁跨喐鏋婚幏锟� -//VCO闁跨喐鏋婚幏鐑芥晸閻欙紕顣幏鐑芥晸閿燂拷 = PLL闁跨喐鏋婚幏鐑芥晸閺傘倖瀚归弮鍫曟晸閺傘倖瀚� / INDIV * 4 * FBDIV -//PLL闁跨喐鏋婚幏鐑芥晸閻欙紕顣幏鐑芥晸閿燂拷 = PLL闁跨喐鏋婚幏鐑芥晸閺傘倖瀚归弮鍫曟晸閺傘倖瀚� / INDIV * 4 * FBDIV / OUTDIV = VCO闁跨喐鏋婚幏鐑芥晸閻欙紕顣幏鐑芥晸閿燂拷 / OUTDIV +#define SYS_PLLDIV_FBDIV_Pos 0 /* PLL FeedBack分频寄存器 \ + VCO输出频率 = PLL输入时钟 / INDIV * 4 * FBDIV \ + PLL输出频率 = PLL输入时钟 / INDIV * 4 * FBDIV / OUTDIV = VCO输出频率 / OUTDIV */ #define SYS_PLLDIV_FBDIV_Msk (0x1FF << SYS_PLLDIV_FBDIV_Pos) -#define SYS_PLLDIV_ADDIV_Pos 9 //ADC閺冨爼鏁撻幒銉ょ串閹风兘鏁撻弬銈嗗闁跨喐鏋婚幏绋窩O闁跨喐鏋婚幏鐑芥晸閺傘倖瀚归柨鐔哄珱绾板瀚归柨鐔告灮閹烽攱妞傞柨鐔稿复閿濆繑瀚归柨鐔告灮閹风DDIV闁跨喐鏋婚幏鐑筋暥闁跨喐鏋婚幏鐑芥晸閺傘倖瀚规稉绡圖C闁跨喐鏋婚幏鐤祮闁跨喐鏋婚幏閿嬫闁跨喐鏋婚幏锟� +#define SYS_PLLDIV_ADDIV_Pos 9 //ADC时钟基（即VCO输出分频后的时钟）经ADDIV分频后作为ADC的转换时钟 #define SYS_PLLDIV_ADDIV_Msk (0x1F << SYS_PLLDIV_ADDIV_Pos) -#define SYS_PLLDIV_ADVCO_Pos 14 //0 VCO闁跨喐鏋婚幏鐑芥晸閿燂拷16闁跨喐鏋婚幏鐑筋暥闁跨喐鏋婚幏铚傝礋ADC閺冨爼鏁撻幒銉ょ串閹凤拷 1 VCO闁跨喐鏋婚幏鐑芥晸閺傘倖瀚归柨鐔告灮閹风兘鏁撻敓锟�32闁跨喐鏋婚幏鐑筋暥闁跨喐鏋婚幏铚傝礋ADC閺冨爼鏁撻幒銉ょ串閹凤拷 2 VCO闁跨喐鏋婚幏鐑芥晸閺傘倖瀚归柨鐔告灮閹风兘鏁撻敓锟�64闁跨喐鏋婚幏鐑筋暥闁跨喐鏋婚幏铚傝礋ADC閺冨爼鏁撻幒銉ょ串閹凤拷 +#define SYS_PLLDIV_ADVCO_Pos 14 //0 VCO输出16分频作为ADC时钟基 1 VCO输出经过32分频作为ADC时钟基 2 VCO输出经过64分频作为ADC时钟基 #define SYS_PLLDIV_ADVCO_Msk (0x03 << SYS_PLLDIV_ADVCO_Pos) -#define SYS_PLLDIV_INDIV_Pos 16 //PLL 闁跨喐鏋婚幏鐑芥晸閺傘倖瀚瑰┃鎰闁跨喐甯撮崙銈嗗妫帮拷 +#define SYS_PLLDIV_INDIV_Pos 16 //PLL 输入源时钟分频 #define SYS_PLLDIV_INDIV_Msk (0x1F << SYS_PLLDIV_INDIV_Pos) -#define SYS_PLLDIV_OUTDIV_Pos 24 //PLL 闁跨喐鏋婚幏鐑芥晸閺傘倖瀚归柨鐔哄珱绾板瀚归柨鐕傛嫹0 8闁跨喐鏋婚幏鐑筋暥 1 4闁跨喐鏋婚幏鐑筋暥 0 2闁跨喐鏋婚幏鐑筋暥 +#define SYS_PLLDIV_OUTDIV_Pos 24 //PLL 输出分频，0 8分频 1 4分频 0 2分频 #define SYS_PLLDIV_OUTDIV_Msk (0x03 << SYS_PLLDIV_OUTDIV_Pos) #define SYS_PLLSET_LPFBW_Pos 0 //PLL Low Pass Filter Bandwidth @@ -376,28 +351,21 @@ typedef struct #define SYS_PLLSET_CHPADJM_Pos 11 //PLL charge pump MSB current Adjustment #define SYS_PLLSET_CHPADJM_Msk (0x03 << SYS_PLLSET_CHPADJM_Pos) -#define SYS_BODIE_1V9_Pos 0 //BOD 1.9V闁跨喖銈虹涵閿嬪闁跨喐鏋婚幏鐑芥晸閺傘倖瀚归柨鐔峰建鐠佽瀚规担鍧楁晸閺傘倖瀚� -#define SYS_BODIE_1V9_Msk (0x01 << SYS_BODIE_1V9_Pos) -#define SYS_BODIE_2V2_Pos 1 //BOD 2.2V闁跨喖銈虹涵閿嬪闁跨喐鏋婚幏鐑芥晸閺傘倖瀚归柨鐔峰建鐠佽瀚规担鍧楁晸閺傘倖瀚� +#define SYS_BODIE_2V2_Pos 1 //BOD 2.2V等级触发中断使能 #define SYS_BODIE_2V2_Msk (0x01 << SYS_BODIE_2V2_Pos) -#define SYS_BODIF_1V9_Pos 0 //BOD 1.9V闁跨喖銈虹涵閿嬪闁跨喐鏋婚幏鐑芥晸閺傘倖瀚归柨鐔峰建鐠佽瀚归悩鑸碘偓渚€鏁撻弬銈嗗閸愶拷1闁跨喐鏋婚幏鐑芥晸閺傘倖瀚� -#define SYS_BODIF_1V9_Msk (0x01 << SYS_BODIF_1V9_Pos) -#define SYS_BODIF_2V2_Pos 1 //BOD 2.2V闁跨喖銈虹涵閿嬪闁跨喐鏋婚幏鐑芥晸閺傘倖瀚归柨鐔峰建鐠佽瀚归悩鑸碘偓渚€鏁撻弬銈嗗閸愶拷1闁跨喐鏋婚幏鐑芥晸閺傘倖瀚� +#define SYS_BODIF_2V2_Pos 1 //BOD 2.2V等级触发中断状态，写1清零 #define SYS_BODIF_2V2_Msk (0x01 << SYS_BODIF_2V2_Pos) -#define SYS_ADC1IN7_SEL_Pos 0 //ADC1濡繝鏁撻弬銈嗗濡繝鏁撻弬銈嗗闁岸鏁撻弬銈嗗7闁跨喐鏋婚幏锟�1 闁跨喖鎽惔锕佹彧閹风兘鏁撻弬銈嗗闁跨喐鏋婚幏锟� 2 闁跨喐鏋婚幏閿嬬毉闁跨喓鐛ら敓锟� 3 RTC闁跨喐鏋婚幏閿嬬爱闁跨喐鏋婚幏绋 4 闁跨喐鏋婚幏鐑芥晸閺傘倖瀚瑰┃鎰版晸閺傘倖瀚笲G 5 PDM33 +#define SYS_ADC1IN7_SEL_Pos 0 //ADC1模块模拟通道7，1 温度传感器 2 电池电压 3 RTC电源域BG 4 主电源域BG 5 PDM33 #define SYS_ADC1IN7_SEL_Msk (0x0F << SYS_ADC1IN7_SEL_Pos) -#define SYS_ADC1IN7_IOON_Pos 4 //ADC1濡繝鏁撻弬銈嗗濡繝鏁撻弬銈嗗闁岸鏁撻弬銈嗗7闁跨喐鏋婚幏鐑芥晸閺傘倖瀚笽O闁跨喐鏋婚幏鐑芥晸閺傘倖瀚� +#define SYS_ADC1IN7_IOON_Pos 4 //ADC1模块模拟通道7所用IO开关 #define SYS_ADC1IN7_IOON_Msk (0x01 << SYS_ADC1IN7_IOON_Pos) -#define SYS_BODCR_EN_Pos 0 -#define SYS_BODCR_EN_Msk (0x01 << SYS_BODCR_EN_Pos) - typedef struct { - __IO uint32_t PORTA_SEL; //闁跨喐鏋婚幏绋癘RTA_SEL[2n+2:2n]闁跨喐鏋婚幏鐑芥晸閺傘倖瀚规惔鏃堟晸閺傘倖瀚归崐濂告晸閺傘倖瀚归柨鐔告灮閹风òORTA.PINn闁跨喐鏋婚幏鐑芥晸閺傘倖瀚归柨鐔告灮閹风兘鏁撻惌顐ゎ劜閹风ěPIO闁跨喐鏋婚幏閿嬆侀柨鐔恍掗妴渚€鏁撻弬銈嗗闁跨喕顢滅粵澶屾閹风兘鏁撻弬銈嗗 - //闁跨喐鏋婚幏鐑芥晸閺傘倖瀚归崐闂磋礋PORTA_PINn_FUNMUX閺冨爼鏁撻弬銈嗗PORTA.PINn闁跨喐鏋婚幏鐑芥晸閼存艾灏呴幏鐑解偓姘舵晸閺傘倖瀚筆ORTA_MUX闁跨喍鑼庢潏鐐闁跨喐鏋婚幏鐑芥晸閺傘倖瀚归柨鐔稿复绾板瀚归柨鐔告灮閹风兘鏁撻弬銈嗗闁跨喐鏋婚幏鐑芥晸閺傘倖瀚归柨鐔告灮閹风兘鏁撻弬銈嗗 + __IO uint32_t PORTA_SEL; /*给PORTA_SEL[2n+2:2n]赋相应的值，将PORTA.PINn引脚配置成GPIO、模拟、数字等功能 + 当赋值为PORTA_PINn_FUNMUX时，PORTA.PINn引脚可通过PORTA_MUX寄存器连接到各种数字外设 */ __IO uint32_t PORTB_SEL; __IO uint32_t PORTC_SEL; @@ -466,7 +434,7 @@ typedef struct uint32_t RESERVED9[28]; - __IO uint32_t PORTA_PULLU; //闁跨喐鏋婚幏鐑芥晸閺傘倖瀚规担鍧楁晸閺傘倖瀚� + __IO uint32_t PORTA_PULLU; //上拉使能 uint32_t RESERVED10[3]; @@ -482,7 +450,7 @@ typedef struct uint32_t RESERVED13[51]; - __IO uint32_t PORTB_PULLD; //闁跨喐鏋婚幏鐑芥晸閺傘倖瀚规担鍧楁晸閺傘倖瀚� + __IO uint32_t PORTB_PULLD; //下拉使能 uint32_t RESERVED14[3]; @@ -494,7 +462,7 @@ typedef struct uint32_t RESERVED16[135]; - __IO uint32_t PORTM_DRIVS; //闁跨喐鏋婚幏鐑芥晸閺傘倖瀚瑰娲晸閺傘倖瀚� + __IO uint32_t PORTM_DRIVS; //驱动强度 uint32_t RESERVED17[3]; @@ -506,7 +474,7 @@ typedef struct uint32_t RESERVED19[39]; - __IO uint32_t PORTA_INEN; //闁跨喐鏋婚幏鐑芥晸閺傘倖瀚规担鍧楁晸閺傘倖瀚� + __IO uint32_t PORTA_INEN; //输入使能 uint32_t RESERVED20[3]; @@ -529,6 +497,645 @@ typedef struct __IO uint32_t PORTP_INEN; } PORT_TypeDef; +#define PORT_PORTA_PULLU_PIN0_Pos 0 +#define PORT_PORTA_PULLU_PIN0_Msk (0x01 << PORT_PORTA_PULLU_PIN0_Pos) +#define PORT_PORTA_PULLU_PIN1_Pos 1 +#define PORT_PORTA_PULLU_PIN1_Msk (0x01 << PORT_PORTA_PULLU_PIN1_Pos) +#define PORT_PORTA_PULLU_PIN2_Pos 2 +#define PORT_PORTA_PULLU_PIN2_Msk (0x01 << PORT_PORTA_PULLU_PIN2_Pos) +#define PORT_PORTA_PULLU_PIN3_Pos 3 +#define PORT_PORTA_PULLU_PIN3_Msk (0x01 << PORT_PORTA_PULLU_PIN3_Pos) +#define PORT_PORTA_PULLU_PIN4_Pos 4 +#define PORT_PORTA_PULLU_PIN4_Msk (0x01 << PORT_PORTA_PULLU_PIN4_Pos) +#define PORT_PORTA_PULLU_PIN5_Pos 5 +#define PORT_PORTA_PULLU_PIN5_Msk (0x01 << PORT_PORTA_PULLU_PIN5_Pos) +#define PORT_PORTA_PULLU_PIN6_Pos 6 +#define PORT_PORTA_PULLU_PIN6_Msk (0x01 << PORT_PORTA_PULLU_PIN6_Pos) +#define PORT_PORTA_PULLU_PIN7_Pos 7 +#define PORT_PORTA_PULLU_PIN7_Msk (0x01 << PORT_PORTA_PULLU_PIN7_Pos) +#define PORT_PORTA_PULLU_PIN8_Pos 8 +#define PORT_PORTA_PULLU_PIN8_Msk (0x01 << PORT_PORTA_PULLU_PIN8_Pos) +#define PORT_PORTA_PULLU_PIN9_Pos 9 +#define PORT_PORTA_PULLU_PIN9_Msk (0x01 << PORT_PORTA_PULLU_PIN9_Pos) +#define PORT_PORTA_PULLU_PIN10_Pos 10 +#define PORT_PORTA_PULLU_PIN10_Msk (0x01 << PORT_PORTA_PULLU_PIN10_Pos) +#define PORT_PORTA_PULLU_PIN11_Pos 11 +#define PORT_PORTA_PULLU_PIN11_Msk (0x01 << PORT_PORTA_PULLU_PIN11_Pos) +#define PORT_PORTA_PULLU_PIN12_Pos 12 +#define PORT_PORTA_PULLU_PIN12_Msk (0x01 << PORT_PORTA_PULLU_PIN12_Pos) +#define PORT_PORTA_PULLU_PIN13_Pos 13 +#define PORT_PORTA_PULLU_PIN13_Msk (0x01 << PORT_PORTA_PULLU_PIN13_Pos) +#define PORT_PORTA_PULLU_PIN14_Pos 14 +#define PORT_PORTA_PULLU_PIN14_Msk (0x01 << PORT_PORTA_PULLU_PIN14_Pos) +#define PORT_PORTA_PULLU_PIN15_Pos 15 +#define PORT_PORTA_PULLU_PIN15_Msk (0x01 << PORT_PORTA_PULLU_PIN15_Pos) + +#define PORT_PORTC_PULLU_PIN0_Pos 0 +#define PORT_PORTC_PULLU_PIN0_Msk (0x01 << PORT_PORTC_PULLU_PIN0_Pos) +#define PORT_PORTC_PULLU_PIN1_Pos 1 +#define PORT_PORTC_PULLU_PIN1_Msk (0x01 << PORT_PORTC_PULLU_PIN1_Pos) +#define PORT_PORTC_PULLU_PIN2_Pos 2 +#define PORT_PORTC_PULLU_PIN2_Msk (0x01 << PORT_PORTC_PULLU_PIN2_Pos) +#define PORT_PORTC_PULLU_PIN3_Pos 3 +#define PORT_PORTC_PULLU_PIN3_Msk (0x01 << PORT_PORTC_PULLU_PIN3_Pos) +#define PORT_PORTC_PULLU_PIN4_Pos 4 +#define PORT_PORTC_PULLU_PIN4_Msk (0x01 << PORT_PORTC_PULLU_PIN4_Pos) +#define PORT_PORTC_PULLU_PIN5_Pos 5 +#define PORT_PORTC_PULLU_PIN5_Msk (0x01 << PORT_PORTC_PULLU_PIN5_Pos) +#define PORT_PORTC_PULLU_PIN6_Pos 6 +#define PORT_PORTC_PULLU_PIN6_Msk (0x01 << PORT_PORTC_PULLU_PIN6_Pos) +#define PORT_PORTC_PULLU_PIN7_Pos 7 +#define PORT_PORTC_PULLU_PIN7_Msk (0x01 << PORT_PORTC_PULLU_PIN7_Pos) +#define PORT_PORTC_PULLU_PIN8_Pos 8 +#define PORT_PORTC_PULLU_PIN8_Msk (0x01 << PORT_PORTC_PULLU_PIN8_Pos) +#define PORT_PORTC_PULLU_PIN9_Pos 9 +#define PORT_PORTC_PULLU_PIN9_Msk (0x01 << PORT_PORTC_PULLU_PIN9_Pos) +#define PORT_PORTC_PULLU_PIN10_Pos 10 +#define PORT_PORTC_PULLU_PIN10_Msk (0x01 << PORT_PORTC_PULLU_PIN10_Pos) +#define PORT_PORTC_PULLU_PIN11_Pos 11 +#define PORT_PORTC_PULLU_PIN11_Msk (0x01 << PORT_PORTC_PULLU_PIN11_Pos) +#define PORT_PORTC_PULLU_PIN12_Pos 12 +#define PORT_PORTC_PULLU_PIN12_Msk (0x01 << PORT_PORTC_PULLU_PIN12_Pos) +#define PORT_PORTC_PULLU_PIN13_Pos 13 +#define PORT_PORTC_PULLU_PIN13_Msk (0x01 << PORT_PORTC_PULLU_PIN13_Pos) +#define PORT_PORTC_PULLU_PIN14_Pos 14 +#define PORT_PORTC_PULLU_PIN14_Msk (0x01 << PORT_PORTC_PULLU_PIN14_Pos) +#define PORT_PORTC_PULLU_PIN15_Pos 15 +#define PORT_PORTC_PULLU_PIN15_Msk (0x01 << PORT_PORTC_PULLU_PIN15_Pos) + +#define PORT_PORTM_PULLU_PIN0_Pos 0 +#define PORT_PORTM_PULLU_PIN0_Msk (0x01 << PORT_PORTM_PULLU_PIN0_Pos) +#define PORT_PORTM_PULLU_PIN1_Pos 1 +#define PORT_PORTM_PULLU_PIN1_Msk (0x01 << PORT_PORTM_PULLU_PIN1_Pos) +#define PORT_PORTM_PULLU_PIN2_Pos 2 +#define PORT_PORTM_PULLU_PIN2_Msk (0x01 << PORT_PORTM_PULLU_PIN2_Pos) +#define PORT_PORTM_PULLU_PIN3_Pos 3 +#define PORT_PORTM_PULLU_PIN3_Msk (0x01 << PORT_PORTM_PULLU_PIN3_Pos) +#define PORT_PORTM_PULLU_PIN4_Pos 4 +#define PORT_PORTM_PULLU_PIN4_Msk (0x01 << PORT_PORTM_PULLU_PIN4_Pos) +#define PORT_PORTM_PULLU_PIN5_Pos 5 +#define PORT_PORTM_PULLU_PIN5_Msk (0x01 << PORT_PORTM_PULLU_PIN5_Pos) +#define PORT_PORTM_PULLU_PIN6_Pos 6 +#define PORT_PORTM_PULLU_PIN6_Msk (0x01 << PORT_PORTM_PULLU_PIN6_Pos) +#define PORT_PORTM_PULLU_PIN7_Pos 7 +#define PORT_PORTM_PULLU_PIN7_Msk (0x01 << PORT_PORTM_PULLU_PIN7_Pos) +#define PORT_PORTM_PULLU_PIN8_Pos 8 +#define PORT_PORTM_PULLU_PIN8_Msk (0x01 << PORT_PORTM_PULLU_PIN8_Pos) +#define PORT_PORTM_PULLU_PIN9_Pos 9 +#define PORT_PORTM_PULLU_PIN9_Msk (0x01 << PORT_PORTM_PULLU_PIN9_Pos) +#define PORT_PORTM_PULLU_PIN10_Pos 10 +#define PORT_PORTM_PULLU_PIN10_Msk (0x01 << PORT_PORTM_PULLU_PIN10_Pos) +#define PORT_PORTM_PULLU_PIN11_Pos 11 +#define PORT_PORTM_PULLU_PIN11_Msk (0x01 << PORT_PORTM_PULLU_PIN11_Pos) +#define PORT_PORTM_PULLU_PIN12_Pos 12 +#define PORT_PORTM_PULLU_PIN12_Msk (0x01 << PORT_PORTM_PULLU_PIN12_Pos) +#define PORT_PORTM_PULLU_PIN13_Pos 13 +#define PORT_PORTM_PULLU_PIN13_Msk (0x01 << PORT_PORTM_PULLU_PIN13_Pos) +#define PORT_PORTM_PULLU_PIN14_Pos 14 +#define PORT_PORTM_PULLU_PIN14_Msk (0x01 << PORT_PORTM_PULLU_PIN14_Pos) +#define PORT_PORTM_PULLU_PIN15_Pos 15 +#define PORT_PORTM_PULLU_PIN15_Msk (0x01 << PORT_PORTM_PULLU_PIN15_Pos) +#define PORT_PORTM_PULLU_PIN16_Pos 16 +#define PORT_PORTM_PULLU_PIN16_Msk (0x01 << PORT_PORTM_PULLU_PIN16_Pos) +#define PORT_PORTM_PULLU_PIN17_Pos 17 +#define PORT_PORTM_PULLU_PIN17_Msk (0x01 << PORT_PORTM_PULLU_PIN17_Pos) +#define PORT_PORTM_PULLU_PIN18_Pos 18 +#define PORT_PORTM_PULLU_PIN18_Msk (0x01 << PORT_PORTM_PULLU_PIN18_Pos) +#define PORT_PORTM_PULLU_PIN19_Pos 19 +#define PORT_PORTM_PULLU_PIN19_Msk (0x01 << PORT_PORTM_PULLU_PIN19_Pos) +#define PORT_PORTM_PULLU_PIN20_Pos 20 +#define PORT_PORTM_PULLU_PIN20_Msk (0x01 << PORT_PORTM_PULLU_PIN20_Pos) +#define PORT_PORTM_PULLU_PIN21_Pos 21 +#define PORT_PORTM_PULLU_PIN21_Msk (0x01 << PORT_PORTM_PULLU_PIN21_Pos) +#define PORT_PORTM_PULLU_PIN22_Pos 22 +#define PORT_PORTM_PULLU_PIN22_Msk (0x01 << PORT_PORTM_PULLU_PIN22_Pos) +#define PORT_PORTM_PULLU_PIN23_Pos 23 +#define PORT_PORTM_PULLU_PIN23_Msk (0x01 << PORT_PORTM_PULLU_PIN23_Pos) + +#define PORT_PORTP_PULLU_PIN0_Pos 0 +#define PORT_PORTP_PULLU_PIN0_Msk (0x01 << PORT_PORTP_PULLU_PIN0_Pos) +#define PORT_PORTP_PULLU_PIN1_Pos 1 +#define PORT_PORTP_PULLU_PIN1_Msk (0x01 << PORT_PORTP_PULLU_PIN1_Pos) +#define PORT_PORTP_PULLU_PIN2_Pos 2 +#define PORT_PORTP_PULLU_PIN2_Msk (0x01 << PORT_PORTP_PULLU_PIN2_Pos) +#define PORT_PORTP_PULLU_PIN3_Pos 3 +#define PORT_PORTP_PULLU_PIN3_Msk (0x01 << PORT_PORTP_PULLU_PIN3_Pos) +#define PORT_PORTP_PULLU_PIN4_Pos 4 +#define PORT_PORTP_PULLU_PIN4_Msk (0x01 << PORT_PORTP_PULLU_PIN4_Pos) +#define PORT_PORTP_PULLU_PIN5_Pos 5 +#define PORT_PORTP_PULLU_PIN5_Msk (0x01 << PORT_PORTP_PULLU_PIN5_Pos) +#define PORT_PORTP_PULLU_PIN6_Pos 6 +#define PORT_PORTP_PULLU_PIN6_Msk (0x01 << PORT_PORTP_PULLU_PIN6_Pos) +#define PORT_PORTP_PULLU_PIN7_Pos 7 +#define PORT_PORTP_PULLU_PIN7_Msk (0x01 << PORT_PORTP_PULLU_PIN7_Pos) +#define PORT_PORTP_PULLU_PIN8_Pos 8 +#define PORT_PORTP_PULLU_PIN8_Msk (0x01 << PORT_PORTP_PULLU_PIN8_Pos) +#define PORT_PORTP_PULLU_PIN9_Pos 9 +#define PORT_PORTP_PULLU_PIN9_Msk (0x01 << PORT_PORTP_PULLU_PIN9_Pos) +#define PORT_PORTP_PULLU_PIN10_Pos 10 +#define PORT_PORTP_PULLU_PIN10_Msk (0x01 << PORT_PORTP_PULLU_PIN10_Pos) +#define PORT_PORTP_PULLU_PIN11_Pos 11 +#define PORT_PORTP_PULLU_PIN11_Msk (0x01 << PORT_PORTP_PULLU_PIN11_Pos) +#define PORT_PORTP_PULLU_PIN12_Pos 12 +#define PORT_PORTP_PULLU_PIN12_Msk (0x01 << PORT_PORTP_PULLU_PIN12_Pos) +#define PORT_PORTP_PULLU_PIN13_Pos 13 +#define PORT_PORTP_PULLU_PIN13_Msk (0x01 << PORT_PORTP_PULLU_PIN13_Pos) +#define PORT_PORTP_PULLU_PIN14_Pos 14 +#define PORT_PORTP_PULLU_PIN14_Msk (0x01 << PORT_PORTP_PULLU_PIN14_Pos) +#define PORT_PORTP_PULLU_PIN15_Pos 15 +#define PORT_PORTP_PULLU_PIN15_Msk (0x01 << PORT_PORTP_PULLU_PIN15_Pos) +#define PORT_PORTP_PULLU_PIN16_Pos 16 +#define PORT_PORTP_PULLU_PIN16_Msk (0x01 << PORT_PORTP_PULLU_PIN16_Pos) +#define PORT_PORTP_PULLU_PIN17_Pos 17 +#define PORT_PORTP_PULLU_PIN17_Msk (0x01 << PORT_PORTP_PULLU_PIN17_Pos) +#define PORT_PORTP_PULLU_PIN18_Pos 18 +#define PORT_PORTP_PULLU_PIN18_Msk (0x01 << PORT_PORTP_PULLU_PIN18_Pos) +#define PORT_PORTP_PULLU_PIN19_Pos 19 +#define PORT_PORTP_PULLU_PIN19_Msk (0x01 << PORT_PORTP_PULLU_PIN19_Pos) +#define PORT_PORTP_PULLU_PIN20_Pos 20 +#define PORT_PORTP_PULLU_PIN20_Msk (0x01 << PORT_PORTP_PULLU_PIN20_Pos) +#define PORT_PORTP_PULLU_PIN21_Pos 21 +#define PORT_PORTP_PULLU_PIN21_Msk (0x01 << PORT_PORTP_PULLU_PIN21_Pos) +#define PORT_PORTP_PULLU_PIN22_Pos 22 +#define PORT_PORTP_PULLU_PIN22_Msk (0x01 << PORT_PORTP_PULLU_PIN22_Pos) +#define PORT_PORTP_PULLU_PIN23_Pos 23 +#define PORT_PORTP_PULLU_PIN23_Msk (0x01 << PORT_PORTP_PULLU_PIN23_Pos) + +#define PORT_PORTB_PULLD_PIN0_Pos 0 +#define PORT_PORTB_PULLD_PIN0_Msk (0x01 << PORT_PORTB_PULLD_PIN0_Pos) +#define PORT_PORTB_PULLD_PIN1_Pos 1 +#define PORT_PORTB_PULLD_PIN1_Msk (0x01 << PORT_PORTB_PULLD_PIN1_Pos) +#define PORT_PORTB_PULLD_PIN2_Pos 2 +#define PORT_PORTB_PULLD_PIN2_Msk (0x01 << PORT_PORTB_PULLD_PIN2_Pos) +#define PORT_PORTB_PULLD_PIN3_Pos 3 +#define PORT_PORTB_PULLD_PIN3_Msk (0x01 << PORT_PORTB_PULLD_PIN3_Pos) +#define PORT_PORTB_PULLD_PIN4_Pos 4 +#define PORT_PORTB_PULLD_PIN4_Msk (0x01 << PORT_PORTB_PULLD_PIN4_Pos) +#define PORT_PORTB_PULLD_PIN5_Pos 5 +#define PORT_PORTB_PULLD_PIN5_Msk (0x01 << PORT_PORTB_PULLD_PIN5_Pos) +#define PORT_PORTB_PULLD_PIN6_Pos 6 +#define PORT_PORTB_PULLD_PIN6_Msk (0x01 << PORT_PORTB_PULLD_PIN6_Pos) +#define PORT_PORTB_PULLD_PIN7_Pos 7 +#define PORT_PORTB_PULLD_PIN7_Msk (0x01 << PORT_PORTB_PULLD_PIN7_Pos) +#define PORT_PORTB_PULLD_PIN8_Pos 8 +#define PORT_PORTB_PULLD_PIN8_Msk (0x01 << PORT_PORTB_PULLD_PIN8_Pos) +#define PORT_PORTB_PULLD_PIN9_Pos 9 +#define PORT_PORTB_PULLD_PIN9_Msk (0x01 << PORT_PORTB_PULLD_PIN9_Pos) +#define PORT_PORTB_PULLD_PIN10_Pos 10 +#define PORT_PORTB_PULLD_PIN10_Msk (0x01 << PORT_PORTB_PULLD_PIN10_Pos) +#define PORT_PORTB_PULLD_PIN11_Pos 11 +#define PORT_PORTB_PULLD_PIN11_Msk (0x01 << PORT_PORTB_PULLD_PIN11_Pos) +#define PORT_PORTB_PULLD_PIN12_Pos 12 +#define PORT_PORTB_PULLD_PIN12_Msk (0x01 << PORT_PORTB_PULLD_PIN12_Pos) +#define PORT_PORTB_PULLD_PIN13_Pos 13 +#define PORT_PORTB_PULLD_PIN13_Msk (0x01 << PORT_PORTB_PULLD_PIN13_Pos) +#define PORT_PORTB_PULLD_PIN14_Pos 14 +#define PORT_PORTB_PULLD_PIN14_Msk (0x01 << PORT_PORTB_PULLD_PIN14_Pos) +#define PORT_PORTB_PULLD_PIN15_Pos 15 +#define PORT_PORTB_PULLD_PIN15_Msk (0x01 << PORT_PORTB_PULLD_PIN15_Pos) + +#define PORT_PORTN_PULLD_PIN0_Pos 0 +#define PORT_PORTN_PULLD_PIN0_Msk (0x01 << PORT_PORTN_PULLD_PIN0_Pos) +#define PORT_PORTN_PULLD_PIN1_Pos 1 +#define PORT_PORTN_PULLD_PIN1_Msk (0x01 << PORT_PORTN_PULLD_PIN1_Pos) +#define PORT_PORTN_PULLD_PIN2_Pos 2 +#define PORT_PORTN_PULLD_PIN2_Msk (0x01 << PORT_PORTN_PULLD_PIN2_Pos) +#define PORT_PORTN_PULLD_PIN3_Pos 3 +#define PORT_PORTN_PULLD_PIN3_Msk (0x01 << PORT_PORTN_PULLD_PIN3_Pos) +#define PORT_PORTN_PULLD_PIN4_Pos 4 +#define PORT_PORTN_PULLD_PIN4_Msk (0x01 << PORT_PORTN_PULLD_PIN4_Pos) +#define PORT_PORTN_PULLD_PIN5_Pos 5 +#define PORT_PORTN_PULLD_PIN5_Msk (0x01 << PORT_PORTN_PULLD_PIN5_Pos) +#define PORT_PORTN_PULLD_PIN6_Pos 6 +#define PORT_PORTN_PULLD_PIN6_Msk (0x01 << PORT_PORTN_PULLD_PIN6_Pos) +#define PORT_PORTN_PULLD_PIN7_Pos 7 +#define PORT_PORTN_PULLD_PIN7_Msk (0x01 << PORT_PORTN_PULLD_PIN7_Pos) +#define PORT_PORTN_PULLD_PIN8_Pos 8 +#define PORT_PORTN_PULLD_PIN8_Msk (0x01 << PORT_PORTN_PULLD_PIN8_Pos) +#define PORT_PORTN_PULLD_PIN9_Pos 9 +#define PORT_PORTN_PULLD_PIN9_Msk (0x01 << PORT_PORTN_PULLD_PIN9_Pos) +#define PORT_PORTN_PULLD_PIN10_Pos 10 +#define PORT_PORTN_PULLD_PIN10_Msk (0x01 << PORT_PORTN_PULLD_PIN10_Pos) +#define PORT_PORTN_PULLD_PIN11_Pos 11 +#define PORT_PORTN_PULLD_PIN11_Msk (0x01 << PORT_PORTN_PULLD_PIN11_Pos) +#define PORT_PORTN_PULLD_PIN12_Pos 12 +#define PORT_PORTN_PULLD_PIN12_Msk (0x01 << PORT_PORTN_PULLD_PIN12_Pos) +#define PORT_PORTN_PULLD_PIN13_Pos 13 +#define PORT_PORTN_PULLD_PIN13_Msk (0x01 << PORT_PORTN_PULLD_PIN13_Pos) +#define PORT_PORTN_PULLD_PIN14_Pos 14 +#define PORT_PORTN_PULLD_PIN14_Msk (0x01 << PORT_PORTN_PULLD_PIN14_Pos) +#define PORT_PORTN_PULLD_PIN15_Pos 15 +#define PORT_PORTN_PULLD_PIN15_Msk (0x01 << PORT_PORTN_PULLD_PIN15_Pos) +#define PORT_PORTN_PULLD_PIN16_Pos 16 +#define PORT_PORTN_PULLD_PIN16_Msk (0x01 << PORT_PORTN_PULLD_PIN16_Pos) +#define PORT_PORTN_PULLD_PIN17_Pos 17 +#define PORT_PORTN_PULLD_PIN17_Msk (0x01 << PORT_PORTN_PULLD_PIN17_Pos) +#define PORT_PORTN_PULLD_PIN18_Pos 18 +#define PORT_PORTN_PULLD_PIN18_Msk (0x01 << PORT_PORTN_PULLD_PIN18_Pos) +#define PORT_PORTN_PULLD_PIN19_Pos 19 +#define PORT_PORTN_PULLD_PIN19_Msk (0x01 << PORT_PORTN_PULLD_PIN19_Pos) +#define PORT_PORTN_PULLD_PIN20_Pos 20 +#define PORT_PORTN_PULLD_PIN20_Msk (0x01 << PORT_PORTN_PULLD_PIN20_Pos) +#define PORT_PORTN_PULLD_PIN21_Pos 21 +#define PORT_PORTN_PULLD_PIN21_Msk (0x01 << PORT_PORTN_PULLD_PIN21_Pos) +#define PORT_PORTN_PULLD_PIN22_Pos 22 +#define PORT_PORTN_PULLD_PIN22_Msk (0x01 << PORT_PORTN_PULLD_PIN22_Pos) +#define PORT_PORTN_PULLD_PIN23_Pos 23 +#define PORT_PORTN_PULLD_PIN23_Msk (0x01 << PORT_PORTN_PULLD_PIN23_Pos) + +#define PORT_PORTM_DRIVS_PIN0_Pos 0 +#define PORT_PORTM_DRIVS_PIN0_Msk (0x01 << PORT_PORTM_DRIVS_PIN0_Pos) +#define PORT_PORTM_DRIVS_PIN1_Pos 1 +#define PORT_PORTM_DRIVS_PIN1_Msk (0x01 << PORT_PORTM_DRIVS_PIN1_Pos) +#define PORT_PORTM_DRIVS_PIN2_Pos 2 +#define PORT_PORTM_DRIVS_PIN2_Msk (0x01 << PORT_PORTM_DRIVS_PIN2_Pos) +#define PORT_PORTM_DRIVS_PIN3_Pos 3 +#define PORT_PORTM_DRIVS_PIN3_Msk (0x01 << PORT_PORTM_DRIVS_PIN3_Pos) +#define PORT_PORTM_DRIVS_PIN4_Pos 4 +#define PORT_PORTM_DRIVS_PIN4_Msk (0x01 << PORT_PORTM_DRIVS_PIN4_Pos) +#define PORT_PORTM_DRIVS_PIN5_Pos 5 +#define PORT_PORTM_DRIVS_PIN5_Msk (0x01 << PORT_PORTM_DRIVS_PIN5_Pos) +#define PORT_PORTM_DRIVS_PIN6_Pos 6 +#define PORT_PORTM_DRIVS_PIN6_Msk (0x01 << PORT_PORTM_DRIVS_PIN6_Pos) +#define PORT_PORTM_DRIVS_PIN7_Pos 7 +#define PORT_PORTM_DRIVS_PIN7_Msk (0x01 << PORT_PORTM_DRIVS_PIN7_Pos) +#define PORT_PORTM_DRIVS_PIN8_Pos 8 +#define PORT_PORTM_DRIVS_PIN8_Msk (0x01 << PORT_PORTM_DRIVS_PIN8_Pos) +#define PORT_PORTM_DRIVS_PIN9_Pos 9 +#define PORT_PORTM_DRIVS_PIN9_Msk (0x01 << PORT_PORTM_DRIVS_PIN9_Pos) +#define PORT_PORTM_DRIVS_PIN10_Pos 10 +#define PORT_PORTM_DRIVS_PIN10_Msk (0x01 << PORT_PORTM_DRIVS_PIN10_Pos) +#define PORT_PORTM_DRIVS_PIN11_Pos 11 +#define PORT_PORTM_DRIVS_PIN11_Msk (0x01 << PORT_PORTM_DRIVS_PIN11_Pos) +#define PORT_PORTM_DRIVS_PIN12_Pos 12 +#define PORT_PORTM_DRIVS_PIN12_Msk (0x01 << PORT_PORTM_DRIVS_PIN12_Pos) +#define PORT_PORTM_DRIVS_PIN13_Pos 13 +#define PORT_PORTM_DRIVS_PIN13_Msk (0x01 << PORT_PORTM_DRIVS_PIN13_Pos) +#define PORT_PORTM_DRIVS_PIN14_Pos 14 +#define PORT_PORTM_DRIVS_PIN14_Msk (0x01 << PORT_PORTM_DRIVS_PIN14_Pos) +#define PORT_PORTM_DRIVS_PIN15_Pos 15 +#define PORT_PORTM_DRIVS_PIN15_Msk (0x01 << PORT_PORTM_DRIVS_PIN15_Pos) +#define PORT_PORTM_DRIVS_PIN16_Pos 16 +#define PORT_PORTM_DRIVS_PIN16_Msk (0x01 << PORT_PORTM_DRIVS_PIN16_Pos) +#define PORT_PORTM_DRIVS_PIN17_Pos 17 +#define PORT_PORTM_DRIVS_PIN17_Msk (0x01 << PORT_PORTM_DRIVS_PIN17_Pos) +#define PORT_PORTM_DRIVS_PIN18_Pos 18 +#define PORT_PORTM_DRIVS_PIN18_Msk (0x01 << PORT_PORTM_DRIVS_PIN18_Pos) +#define PORT_PORTM_DRIVS_PIN19_Pos 19 +#define PORT_PORTM_DRIVS_PIN19_Msk (0x01 << PORT_PORTM_DRIVS_PIN19_Pos) +#define PORT_PORTM_DRIVS_PIN20_Pos 20 +#define PORT_PORTM_DRIVS_PIN20_Msk (0x01 << PORT_PORTM_DRIVS_PIN20_Pos) +#define PORT_PORTM_DRIVS_PIN21_Pos 21 +#define PORT_PORTM_DRIVS_PIN21_Msk (0x01 << PORT_PORTM_DRIVS_PIN21_Pos) +#define PORT_PORTM_DRIVS_PIN22_Pos 22 +#define PORT_PORTM_DRIVS_PIN22_Msk (0x01 << PORT_PORTM_DRIVS_PIN22_Pos) +#define PORT_PORTM_DRIVS_PIN23_Pos 23 +#define PORT_PORTM_DRIVS_PIN23_Msk (0x01 << PORT_PORTM_DRIVS_PIN23_Pos) + +#define PORT_PORTN_DRIVS_PIN0_Pos 0 +#define PORT_PORTN_DRIVS_PIN0_Msk (0x01 << PORT_PORTN_DRIVS_PIN0_Pos) +#define PORT_PORTN_DRIVS_PIN1_Pos 1 +#define PORT_PORTN_DRIVS_PIN1_Msk (0x01 << PORT_PORTN_DRIVS_PIN1_Pos) +#define PORT_PORTN_DRIVS_PIN2_Pos 2 +#define PORT_PORTN_DRIVS_PIN2_Msk (0x01 << PORT_PORTN_DRIVS_PIN2_Pos) +#define PORT_PORTN_DRIVS_PIN3_Pos 3 +#define PORT_PORTN_DRIVS_PIN3_Msk (0x01 << PORT_PORTN_DRIVS_PIN3_Pos) +#define PORT_PORTN_DRIVS_PIN4_Pos 4 +#define PORT_PORTN_DRIVS_PIN4_Msk (0x01 << PORT_PORTN_DRIVS_PIN4_Pos) +#define PORT_PORTN_DRIVS_PIN5_Pos 5 +#define PORT_PORTN_DRIVS_PIN5_Msk (0x01 << PORT_PORTN_DRIVS_PIN5_Pos) +#define PORT_PORTN_DRIVS_PIN6_Pos 6 +#define PORT_PORTN_DRIVS_PIN6_Msk (0x01 << PORT_PORTN_DRIVS_PIN6_Pos) +#define PORT_PORTN_DRIVS_PIN7_Pos 7 +#define PORT_PORTN_DRIVS_PIN7_Msk (0x01 << PORT_PORTN_DRIVS_PIN7_Pos) +#define PORT_PORTN_DRIVS_PIN8_Pos 8 +#define PORT_PORTN_DRIVS_PIN8_Msk (0x01 << PORT_PORTN_DRIVS_PIN8_Pos) +#define PORT_PORTN_DRIVS_PIN9_Pos 9 +#define PORT_PORTN_DRIVS_PIN9_Msk (0x01 << PORT_PORTN_DRIVS_PIN9_Pos) +#define PORT_PORTN_DRIVS_PIN10_Pos 10 +#define PORT_PORTN_DRIVS_PIN10_Msk (0x01 << PORT_PORTN_DRIVS_PIN10_Pos) +#define PORT_PORTN_DRIVS_PIN11_Pos 11 +#define PORT_PORTN_DRIVS_PIN11_Msk (0x01 << PORT_PORTN_DRIVS_PIN11_Pos) +#define PORT_PORTN_DRIVS_PIN12_Pos 12 +#define PORT_PORTN_DRIVS_PIN12_Msk (0x01 << PORT_PORTN_DRIVS_PIN12_Pos) +#define PORT_PORTN_DRIVS_PIN13_Pos 13 +#define PORT_PORTN_DRIVS_PIN13_Msk (0x01 << PORT_PORTN_DRIVS_PIN13_Pos) +#define PORT_PORTN_DRIVS_PIN14_Pos 14 +#define PORT_PORTN_DRIVS_PIN14_Msk (0x01 << PORT_PORTN_DRIVS_PIN14_Pos) +#define PORT_PORTN_DRIVS_PIN15_Pos 15 +#define PORT_PORTN_DRIVS_PIN15_Msk (0x01 << PORT_PORTN_DRIVS_PIN15_Pos) +#define PORT_PORTN_DRIVS_PIN16_Pos 16 +#define PORT_PORTN_DRIVS_PIN16_Msk (0x01 << PORT_PORTN_DRIVS_PIN16_Pos) +#define PORT_PORTN_DRIVS_PIN17_Pos 17 +#define PORT_PORTN_DRIVS_PIN17_Msk (0x01 << PORT_PORTN_DRIVS_PIN17_Pos) +#define PORT_PORTN_DRIVS_PIN18_Pos 18 +#define PORT_PORTN_DRIVS_PIN18_Msk (0x01 << PORT_PORTN_DRIVS_PIN18_Pos) +#define PORT_PORTN_DRIVS_PIN19_Pos 19 +#define PORT_PORTN_DRIVS_PIN19_Msk (0x01 << PORT_PORTN_DRIVS_PIN19_Pos) +#define PORT_PORTN_DRIVS_PIN20_Pos 20 +#define PORT_PORTN_DRIVS_PIN20_Msk (0x01 << PORT_PORTN_DRIVS_PIN20_Pos) +#define PORT_PORTN_DRIVS_PIN21_Pos 21 +#define PORT_PORTN_DRIVS_PIN21_Msk (0x01 << PORT_PORTN_DRIVS_PIN21_Pos) +#define PORT_PORTN_DRIVS_PIN22_Pos 22 +#define PORT_PORTN_DRIVS_PIN22_Msk (0x01 << PORT_PORTN_DRIVS_PIN22_Pos) +#define PORT_PORTN_DRIVS_PIN23_Pos 23 +#define PORT_PORTN_DRIVS_PIN23_Msk (0x01 << PORT_PORTN_DRIVS_PIN23_Pos) + +#define PORT_PORTP_DRIVS_PIN0_Pos 0 +#define PORT_PORTP_DRIVS_PIN0_Msk (0x01 << PORT_PORTP_DRIVS_PIN0_Pos) +#define PORT_PORTP_DRIVS_PIN1_Pos 1 +#define PORT_PORTP_DRIVS_PIN1_Msk (0x01 << PORT_PORTP_DRIVS_PIN1_Pos) +#define PORT_PORTP_DRIVS_PIN2_Pos 2 +#define PORT_PORTP_DRIVS_PIN2_Msk (0x01 << PORT_PORTP_DRIVS_PIN2_Pos) +#define PORT_PORTP_DRIVS_PIN3_Pos 3 +#define PORT_PORTP_DRIVS_PIN3_Msk (0x01 << PORT_PORTP_DRIVS_PIN3_Pos) +#define PORT_PORTP_DRIVS_PIN4_Pos 4 +#define PORT_PORTP_DRIVS_PIN4_Msk (0x01 << PORT_PORTP_DRIVS_PIN4_Pos) +#define PORT_PORTP_DRIVS_PIN5_Pos 5 +#define PORT_PORTP_DRIVS_PIN5_Msk (0x01 << PORT_PORTP_DRIVS_PIN5_Pos) +#define PORT_PORTP_DRIVS_PIN6_Pos 6 +#define PORT_PORTP_DRIVS_PIN6_Msk (0x01 << PORT_PORTP_DRIVS_PIN6_Pos) +#define PORT_PORTP_DRIVS_PIN7_Pos 7 +#define PORT_PORTP_DRIVS_PIN7_Msk (0x01 << PORT_PORTP_DRIVS_PIN7_Pos) +#define PORT_PORTP_DRIVS_PIN8_Pos 8 +#define PORT_PORTP_DRIVS_PIN8_Msk (0x01 << PORT_PORTP_DRIVS_PIN8_Pos) +#define PORT_PORTP_DRIVS_PIN9_Pos 9 +#define PORT_PORTP_DRIVS_PIN9_Msk (0x01 << PORT_PORTP_DRIVS_PIN9_Pos) +#define PORT_PORTP_DRIVS_PIN10_Pos 10 +#define PORT_PORTP_DRIVS_PIN10_Msk (0x01 << PORT_PORTP_DRIVS_PIN10_Pos) +#define PORT_PORTP_DRIVS_PIN11_Pos 11 +#define PORT_PORTP_DRIVS_PIN11_Msk (0x01 << PORT_PORTP_DRIVS_PIN11_Pos) +#define PORT_PORTP_DRIVS_PIN12_Pos 12 +#define PORT_PORTP_DRIVS_PIN12_Msk (0x01 << PORT_PORTP_DRIVS_PIN12_Pos) +#define PORT_PORTP_DRIVS_PIN13_Pos 13 +#define PORT_PORTP_DRIVS_PIN13_Msk (0x01 << PORT_PORTP_DRIVS_PIN13_Pos) +#define PORT_PORTP_DRIVS_PIN14_Pos 14 +#define PORT_PORTP_DRIVS_PIN14_Msk (0x01 << PORT_PORTP_DRIVS_PIN14_Pos) +#define PORT_PORTP_DRIVS_PIN15_Pos 15 +#define PORT_PORTP_DRIVS_PIN15_Msk (0x01 << PORT_PORTP_DRIVS_PIN15_Pos) +#define PORT_PORTP_DRIVS_PIN16_Pos 16 +#define PORT_PORTP_DRIVS_PIN16_Msk (0x01 << PORT_PORTP_DRIVS_PIN16_Pos) +#define PORT_PORTP_DRIVS_PIN17_Pos 17 +#define PORT_PORTP_DRIVS_PIN17_Msk (0x01 << PORT_PORTP_DRIVS_PIN17_Pos) +#define PORT_PORTP_DRIVS_PIN18_Pos 18 +#define PORT_PORTP_DRIVS_PIN18_Msk (0x01 << PORT_PORTP_DRIVS_PIN18_Pos) +#define PORT_PORTP_DRIVS_PIN19_Pos 19 +#define PORT_PORTP_DRIVS_PIN19_Msk (0x01 << PORT_PORTP_DRIVS_PIN19_Pos) +#define PORT_PORTP_DRIVS_PIN20_Pos 20 +#define PORT_PORTP_DRIVS_PIN20_Msk (0x01 << PORT_PORTP_DRIVS_PIN20_Pos) +#define PORT_PORTP_DRIVS_PIN21_Pos 21 +#define PORT_PORTP_DRIVS_PIN21_Msk (0x01 << PORT_PORTP_DRIVS_PIN21_Pos) +#define PORT_PORTP_DRIVS_PIN22_Pos 22 +#define PORT_PORTP_DRIVS_PIN22_Msk (0x01 << PORT_PORTP_DRIVS_PIN22_Pos) +#define PORT_PORTP_DRIVS_PIN23_Pos 23 +#define PORT_PORTP_DRIVS_PIN23_Msk (0x01 << PORT_PORTP_DRIVS_PIN23_Pos) + +#define PORT_PORTA_INEN_PIN0_Pos 0 +#define PORT_PORTA_INEN_PIN0_Msk (0x01 << PORT_PORTA_INEN_PIN0_Pos) +#define PORT_PORTA_INEN_PIN1_Pos 1 +#define PORT_PORTA_INEN_PIN1_Msk (0x01 << PORT_PORTA_INEN_PIN1_Pos) +#define PORT_PORTA_INEN_PIN2_Pos 2 +#define PORT_PORTA_INEN_PIN2_Msk (0x01 << PORT_PORTA_INEN_PIN2_Pos) +#define PORT_PORTA_INEN_PIN3_Pos 3 +#define PORT_PORTA_INEN_PIN3_Msk (0x01 << PORT_PORTA_INEN_PIN3_Pos) +#define PORT_PORTA_INEN_PIN4_Pos 4 +#define PORT_PORTA_INEN_PIN4_Msk (0x01 << PORT_PORTA_INEN_PIN4_Pos) +#define PORT_PORTA_INEN_PIN5_Pos 5 +#define PORT_PORTA_INEN_PIN5_Msk (0x01 << PORT_PORTA_INEN_PIN5_Pos) +#define PORT_PORTA_INEN_PIN6_Pos 6 +#define PORT_PORTA_INEN_PIN6_Msk (0x01 << PORT_PORTA_INEN_PIN6_Pos) +#define PORT_PORTA_INEN_PIN7_Pos 7 +#define PORT_PORTA_INEN_PIN7_Msk (0x01 << PORT_PORTA_INEN_PIN7_Pos) +#define PORT_PORTA_INEN_PIN8_Pos 8 +#define PORT_PORTA_INEN_PIN8_Msk (0x01 << PORT_PORTA_INEN_PIN8_Pos) +#define PORT_PORTA_INEN_PIN9_Pos 9 +#define PORT_PORTA_INEN_PIN9_Msk (0x01 << PORT_PORTA_INEN_PIN9_Pos) +#define PORT_PORTA_INEN_PIN10_Pos 10 +#define PORT_PORTA_INEN_PIN10_Msk (0x01 << PORT_PORTA_INEN_PIN10_Pos) +#define PORT_PORTA_INEN_PIN11_Pos 11 +#define PORT_PORTA_INEN_PIN11_Msk (0x01 << PORT_PORTA_INEN_PIN11_Pos) +#define PORT_PORTA_INEN_PIN12_Pos 12 +#define PORT_PORTA_INEN_PIN12_Msk (0x01 << PORT_PORTA_INEN_PIN12_Pos) +#define PORT_PORTA_INEN_PIN13_Pos 13 +#define PORT_PORTA_INEN_PIN13_Msk (0x01 << PORT_PORTA_INEN_PIN13_Pos) +#define PORT_PORTA_INEN_PIN14_Pos 14 +#define PORT_PORTA_INEN_PIN14_Msk (0x01 << PORT_PORTA_INEN_PIN14_Pos) +#define PORT_PORTA_INEN_PIN15_Pos 15 +#define PORT_PORTA_INEN_PIN15_Msk (0x01 << PORT_PORTA_INEN_PIN15_Pos) + +#define PORT_PORTB_INEN_PIN0_Pos 0 +#define PORT_PORTB_INEN_PIN0_Msk (0x01 << PORT_PORTB_INEN_PIN0_Pos) +#define PORT_PORTB_INEN_PIN1_Pos 1 +#define PORT_PORTB_INEN_PIN1_Msk (0x01 << PORT_PORTB_INEN_PIN1_Pos) +#define PORT_PORTB_INEN_PIN2_Pos 2 +#define PORT_PORTB_INEN_PIN2_Msk (0x01 << PORT_PORTB_INEN_PIN2_Pos) +#define PORT_PORTB_INEN_PIN3_Pos 3 +#define PORT_PORTB_INEN_PIN3_Msk (0x01 << PORT_PORTB_INEN_PIN3_Pos) +#define PORT_PORTB_INEN_PIN4_Pos 4 +#define PORT_PORTB_INEN_PIN4_Msk (0x01 << PORT_PORTB_INEN_PIN4_Pos) +#define PORT_PORTB_INEN_PIN5_Pos 5 +#define PORT_PORTB_INEN_PIN5_Msk (0x01 << PORT_PORTB_INEN_PIN5_Pos) +#define PORT_PORTB_INEN_PIN6_Pos 6 +#define PORT_PORTB_INEN_PIN6_Msk (0x01 << PORT_PORTB_INEN_PIN6_Pos) +#define PORT_PORTB_INEN_PIN7_Pos 7 +#define PORT_PORTB_INEN_PIN7_Msk (0x01 << PORT_PORTB_INEN_PIN7_Pos) +#define PORT_PORTB_INEN_PIN8_Pos 8 +#define PORT_PORTB_INEN_PIN8_Msk (0x01 << PORT_PORTB_INEN_PIN8_Pos) +#define PORT_PORTB_INEN_PIN9_Pos 9 +#define PORT_PORTB_INEN_PIN9_Msk (0x01 << PORT_PORTB_INEN_PIN9_Pos) +#define PORT_PORTB_INEN_PIN10_Pos 10 +#define PORT_PORTB_INEN_PIN10_Msk (0x01 << PORT_PORTB_INEN_PIN10_Pos) +#define PORT_PORTB_INEN_PIN11_Pos 11 +#define PORT_PORTB_INEN_PIN11_Msk (0x01 << PORT_PORTB_INEN_PIN11_Pos) +#define PORT_PORTB_INEN_PIN12_Pos 12 +#define PORT_PORTB_INEN_PIN12_Msk (0x01 << PORT_PORTB_INEN_PIN12_Pos) +#define PORT_PORTB_INEN_PIN13_Pos 13 +#define PORT_PORTB_INEN_PIN13_Msk (0x01 << PORT_PORTB_INEN_PIN13_Pos) +#define PORT_PORTB_INEN_PIN14_Pos 14 +#define PORT_PORTB_INEN_PIN14_Msk (0x01 << PORT_PORTB_INEN_PIN14_Pos) +#define PORT_PORTB_INEN_PIN15_Pos 15 +#define PORT_PORTB_INEN_PIN15_Msk (0x01 << PORT_PORTB_INEN_PIN15_Pos) + +#define PORT_PORTC_INEN_PIN0_Pos 0 +#define PORT_PORTC_INEN_PIN0_Msk (0x01 << PORT_PORTC_INEN_PIN0_Pos) +#define PORT_PORTC_INEN_PIN1_Pos 1 +#define PORT_PORTC_INEN_PIN1_Msk (0x01 << PORT_PORTC_INEN_PIN1_Pos) +#define PORT_PORTC_INEN_PIN2_Pos 2 +#define PORT_PORTC_INEN_PIN2_Msk (0x01 << PORT_PORTC_INEN_PIN2_Pos) +#define PORT_PORTC_INEN_PIN3_Pos 3 +#define PORT_PORTC_INEN_PIN3_Msk (0x01 << PORT_PORTC_INEN_PIN3_Pos) +#define PORT_PORTC_INEN_PIN4_Pos 4 +#define PORT_PORTC_INEN_PIN4_Msk (0x01 << PORT_PORTC_INEN_PIN4_Pos) +#define PORT_PORTC_INEN_PIN5_Pos 5 +#define PORT_PORTC_INEN_PIN5_Msk (0x01 << PORT_PORTC_INEN_PIN5_Pos) +#define PORT_PORTC_INEN_PIN6_Pos 6 +#define PORT_PORTC_INEN_PIN6_Msk (0x01 << PORT_PORTC_INEN_PIN6_Pos) +#define PORT_PORTC_INEN_PIN7_Pos 7 +#define PORT_PORTC_INEN_PIN7_Msk (0x01 << PORT_PORTC_INEN_PIN7_Pos) +#define PORT_PORTC_INEN_PIN8_Pos 8 +#define PORT_PORTC_INEN_PIN8_Msk (0x01 << PORT_PORTC_INEN_PIN8_Pos) +#define PORT_PORTC_INEN_PIN9_Pos 9 +#define PORT_PORTC_INEN_PIN9_Msk (0x01 << PORT_PORTC_INEN_PIN9_Pos) +#define PORT_PORTC_INEN_PIN10_Pos 10 +#define PORT_PORTC_INEN_PIN10_Msk (0x01 << PORT_PORTC_INEN_PIN10_Pos) +#define PORT_PORTC_INEN_PIN11_Pos 11 +#define PORT_PORTC_INEN_PIN11_Msk (0x01 << PORT_PORTC_INEN_PIN11_Pos) +#define PORT_PORTC_INEN_PIN12_Pos 12 +#define PORT_PORTC_INEN_PIN12_Msk (0x01 << PORT_PORTC_INEN_PIN12_Pos) +#define PORT_PORTC_INEN_PIN13_Pos 13 +#define PORT_PORTC_INEN_PIN13_Msk (0x01 << PORT_PORTC_INEN_PIN13_Pos) +#define PORT_PORTC_INEN_PIN14_Pos 14 +#define PORT_PORTC_INEN_PIN14_Msk (0x01 << PORT_PORTC_INEN_PIN14_Pos) +#define PORT_PORTC_INEN_PIN15_Pos 15 +#define PORT_PORTC_INEN_PIN15_Msk (0x01 << PORT_PORTC_INEN_PIN15_Pos) + +#define PORT_PORTM_INEN_PIN0_Pos 0 +#define PORT_PORTM_INEN_PIN0_Msk (0x01 << PORT_PORTM_INEN_PIN0_Pos) +#define PORT_PORTM_INEN_PIN1_Pos 1 +#define PORT_PORTM_INEN_PIN1_Msk (0x01 << PORT_PORTM_INEN_PIN1_Pos) +#define PORT_PORTM_INEN_PIN2_Pos 2 +#define PORT_PORTM_INEN_PIN2_Msk (0x01 << PORT_PORTM_INEN_PIN2_Pos) +#define PORT_PORTM_INEN_PIN3_Pos 3 +#define PORT_PORTM_INEN_PIN3_Msk (0x01 << PORT_PORTM_INEN_PIN3_Pos) +#define PORT_PORTM_INEN_PIN4_Pos 4 +#define PORT_PORTM_INEN_PIN4_Msk (0x01 << PORT_PORTM_INEN_PIN4_Pos) +#define PORT_PORTM_INEN_PIN5_Pos 5 +#define PORT_PORTM_INEN_PIN5_Msk (0x01 << PORT_PORTM_INEN_PIN5_Pos) +#define PORT_PORTM_INEN_PIN6_Pos 6 +#define PORT_PORTM_INEN_PIN6_Msk (0x01 << PORT_PORTM_INEN_PIN6_Pos) +#define PORT_PORTM_INEN_PIN7_Pos 7 +#define PORT_PORTM_INEN_PIN7_Msk (0x01 << PORT_PORTM_INEN_PIN7_Pos) +#define PORT_PORTM_INEN_PIN8_Pos 8 +#define PORT_PORTM_INEN_PIN8_Msk (0x01 << PORT_PORTM_INEN_PIN8_Pos) +#define PORT_PORTM_INEN_PIN9_Pos 9 +#define PORT_PORTM_INEN_PIN9_Msk (0x01 << PORT_PORTM_INEN_PIN9_Pos) +#define PORT_PORTM_INEN_PIN10_Pos 10 +#define PORT_PORTM_INEN_PIN10_Msk (0x01 << PORT_PORTM_INEN_PIN10_Pos) +#define PORT_PORTM_INEN_PIN11_Pos 11 +#define PORT_PORTM_INEN_PIN11_Msk (0x01 << PORT_PORTM_INEN_PIN11_Pos) +#define PORT_PORTM_INEN_PIN12_Pos 12 +#define PORT_PORTM_INEN_PIN12_Msk (0x01 << PORT_PORTM_INEN_PIN12_Pos) +#define PORT_PORTM_INEN_PIN13_Pos 13 +#define PORT_PORTM_INEN_PIN13_Msk (0x01 << PORT_PORTM_INEN_PIN13_Pos) +#define PORT_PORTM_INEN_PIN14_Pos 14 +#define PORT_PORTM_INEN_PIN14_Msk (0x01 << PORT_PORTM_INEN_PIN14_Pos) +#define PORT_PORTM_INEN_PIN15_Pos 15 +#define PORT_PORTM_INEN_PIN15_Msk (0x01 << PORT_PORTM_INEN_PIN15_Pos) +#define PORT_PORTM_INEN_PIN16_Pos 16 +#define PORT_PORTM_INEN_PIN16_Msk (0x01 << PORT_PORTM_INEN_PIN16_Pos) +#define PORT_PORTM_INEN_PIN17_Pos 17 +#define PORT_PORTM_INEN_PIN17_Msk (0x01 << PORT_PORTM_INEN_PIN17_Pos) +#define PORT_PORTM_INEN_PIN18_Pos 18 +#define PORT_PORTM_INEN_PIN18_Msk (0x01 << PORT_PORTM_INEN_PIN18_Pos) +#define PORT_PORTM_INEN_PIN19_Pos 19 +#define PORT_PORTM_INEN_PIN19_Msk (0x01 << PORT_PORTM_INEN_PIN19_Pos) +#define PORT_PORTM_INEN_PIN20_Pos 20 +#define PORT_PORTM_INEN_PIN20_Msk (0x01 << PORT_PORTM_INEN_PIN20_Pos) +#define PORT_PORTM_INEN_PIN21_Pos 21 +#define PORT_PORTM_INEN_PIN21_Msk (0x01 << PORT_PORTM_INEN_PIN21_Pos) +#define PORT_PORTM_INEN_PIN22_Pos 22 +#define PORT_PORTM_INEN_PIN22_Msk (0x01 << PORT_PORTM_INEN_PIN22_Pos) +#define PORT_PORTM_INEN_PIN23_Pos 23 +#define PORT_PORTM_INEN_PIN23_Msk (0x01 << PORT_PORTM_INEN_PIN23_Pos) + +#define PORT_PORTN_INEN_PIN0_Pos 0 +#define PORT_PORTN_INEN_PIN0_Msk (0x01 << PORT_PORTN_INEN_PIN0_Pos) +#define PORT_PORTN_INEN_PIN1_Pos 1 +#define PORT_PORTN_INEN_PIN1_Msk (0x01 << PORT_PORTN_INEN_PIN1_Pos) +#define PORT_PORTN_INEN_PIN2_Pos 2 +#define PORT_PORTN_INEN_PIN2_Msk (0x01 << PORT_PORTN_INEN_PIN2_Pos) +#define PORT_PORTN_INEN_PIN3_Pos 3 +#define PORT_PORTN_INEN_PIN3_Msk (0x01 << PORT_PORTN_INEN_PIN3_Pos) +#define PORT_PORTN_INEN_PIN4_Pos 4 +#define PORT_PORTN_INEN_PIN4_Msk (0x01 << PORT_PORTN_INEN_PIN4_Pos) +#define PORT_PORTN_INEN_PIN5_Pos 5 +#define PORT_PORTN_INEN_PIN5_Msk (0x01 << PORT_PORTN_INEN_PIN5_Pos) +#define PORT_PORTN_INEN_PIN6_Pos 6 +#define PORT_PORTN_INEN_PIN6_Msk (0x01 << PORT_PORTN_INEN_PIN6_Pos) +#define PORT_PORTN_INEN_PIN7_Pos 7 +#define PORT_PORTN_INEN_PIN7_Msk (0x01 << PORT_PORTN_INEN_PIN7_Pos) +#define PORT_PORTN_INEN_PIN8_Pos 8 +#define PORT_PORTN_INEN_PIN8_Msk (0x01 << PORT_PORTN_INEN_PIN8_Pos) +#define PORT_PORTN_INEN_PIN9_Pos 9 +#define PORT_PORTN_INEN_PIN9_Msk (0x01 << PORT_PORTN_INEN_PIN9_Pos) +#define PORT_PORTN_INEN_PIN10_Pos 10 +#define PORT_PORTN_INEN_PIN10_Msk (0x01 << PORT_PORTN_INEN_PIN10_Pos) +#define PORT_PORTN_INEN_PIN11_Pos 11 +#define PORT_PORTN_INEN_PIN11_Msk (0x01 << PORT_PORTN_INEN_PIN11_Pos) +#define PORT_PORTN_INEN_PIN12_Pos 12 +#define PORT_PORTN_INEN_PIN12_Msk (0x01 << PORT_PORTN_INEN_PIN12_Pos) +#define PORT_PORTN_INEN_PIN13_Pos 13 +#define PORT_PORTN_INEN_PIN13_Msk (0x01 << PORT_PORTN_INEN_PIN13_Pos) +#define PORT_PORTN_INEN_PIN14_Pos 14 +#define PORT_PORTN_INEN_PIN14_Msk (0x01 << PORT_PORTN_INEN_PIN14_Pos) +#define PORT_PORTN_INEN_PIN15_Pos 15 +#define PORT_PORTN_INEN_PIN15_Msk (0x01 << PORT_PORTN_INEN_PIN15_Pos) +#define PORT_PORTN_INEN_PIN16_Pos 16 +#define PORT_PORTN_INEN_PIN16_Msk (0x01 << PORT_PORTN_INEN_PIN16_Pos) +#define PORT_PORTN_INEN_PIN17_Pos 17 +#define PORT_PORTN_INEN_PIN17_Msk (0x01 << PORT_PORTN_INEN_PIN17_Pos) +#define PORT_PORTN_INEN_PIN18_Pos 18 +#define PORT_PORTN_INEN_PIN18_Msk (0x01 << PORT_PORTN_INEN_PIN18_Pos) +#define PORT_PORTN_INEN_PIN19_Pos 19 +#define PORT_PORTN_INEN_PIN19_Msk (0x01 << PORT_PORTN_INEN_PIN19_Pos) +#define PORT_PORTN_INEN_PIN20_Pos 20 +#define PORT_PORTN_INEN_PIN20_Msk (0x01 << PORT_PORTN_INEN_PIN20_Pos) +#define PORT_PORTN_INEN_PIN21_Pos 21 +#define PORT_PORTN_INEN_PIN21_Msk (0x01 << PORT_PORTN_INEN_PIN21_Pos) +#define PORT_PORTN_INEN_PIN22_Pos 22 +#define PORT_PORTN_INEN_PIN22_Msk (0x01 << PORT_PORTN_INEN_PIN22_Pos) +#define PORT_PORTN_INEN_PIN23_Pos 23 +#define PORT_PORTN_INEN_PIN23_Msk (0x01 << PORT_PORTN_INEN_PIN23_Pos) + +#define PORT_PORTP_INEN_PIN0_Pos 0 +#define PORT_PORTP_INEN_PIN0_Msk (0x01 << PORT_PORTP_INEN_PIN0_Pos) +#define PORT_PORTP_INEN_PIN1_Pos 1 +#define PORT_PORTP_INEN_PIN1_Msk (0x01 << PORT_PORTP_INEN_PIN1_Pos) +#define PORT_PORTP_INEN_PIN2_Pos 2 +#define PORT_PORTP_INEN_PIN2_Msk (0x01 << PORT_PORTP_INEN_PIN2_Pos) +#define PORT_PORTP_INEN_PIN3_Pos 3 +#define PORT_PORTP_INEN_PIN3_Msk (0x01 << PORT_PORTP_INEN_PIN3_Pos) +#define PORT_PORTP_INEN_PIN4_Pos 4 +#define PORT_PORTP_INEN_PIN4_Msk (0x01 << PORT_PORTP_INEN_PIN4_Pos) +#define PORT_PORTP_INEN_PIN5_Pos 5 +#define PORT_PORTP_INEN_PIN5_Msk (0x01 << PORT_PORTP_INEN_PIN5_Pos) +#define PORT_PORTP_INEN_PIN6_Pos 6 +#define PORT_PORTP_INEN_PIN6_Msk (0x01 << PORT_PORTP_INEN_PIN6_Pos) +#define PORT_PORTP_INEN_PIN7_Pos 7 +#define PORT_PORTP_INEN_PIN7_Msk (0x01 << PORT_PORTP_INEN_PIN7_Pos) +#define PORT_PORTP_INEN_PIN8_Pos 8 +#define PORT_PORTP_INEN_PIN8_Msk (0x01 << PORT_PORTP_INEN_PIN8_Pos) +#define PORT_PORTP_INEN_PIN9_Pos 9 +#define PORT_PORTP_INEN_PIN9_Msk (0x01 << PORT_PORTP_INEN_PIN9_Pos) +#define PORT_PORTP_INEN_PIN10_Pos 10 +#define PORT_PORTP_INEN_PIN10_Msk (0x01 << PORT_PORTP_INEN_PIN10_Pos) +#define PORT_PORTP_INEN_PIN11_Pos 11 +#define PORT_PORTP_INEN_PIN11_Msk (0x01 << PORT_PORTP_INEN_PIN11_Pos) +#define PORT_PORTP_INEN_PIN12_Pos 12 +#define PORT_PORTP_INEN_PIN12_Msk (0x01 << PORT_PORTP_INEN_PIN12_Pos) +#define PORT_PORTP_INEN_PIN13_Pos 13 +#define PORT_PORTP_INEN_PIN13_Msk (0x01 << PORT_PORTP_INEN_PIN13_Pos) +#define PORT_PORTP_INEN_PIN14_Pos 14 +#define PORT_PORTP_INEN_PIN14_Msk (0x01 << PORT_PORTP_INEN_PIN14_Pos) +#define PORT_PORTP_INEN_PIN15_Pos 15 +#define PORT_PORTP_INEN_PIN15_Msk (0x01 << PORT_PORTP_INEN_PIN15_Pos) +#define PORT_PORTP_INEN_PIN16_Pos 16 +#define PORT_PORTP_INEN_PIN16_Msk (0x01 << PORT_PORTP_INEN_PIN16_Pos) +#define PORT_PORTP_INEN_PIN17_Pos 17 +#define PORT_PORTP_INEN_PIN17_Msk (0x01 << PORT_PORTP_INEN_PIN17_Pos) +#define PORT_PORTP_INEN_PIN18_Pos 18 +#define PORT_PORTP_INEN_PIN18_Msk (0x01 << PORT_PORTP_INEN_PIN18_Pos) +#define PORT_PORTP_INEN_PIN19_Pos 19 +#define PORT_PORTP_INEN_PIN19_Msk (0x01 << PORT_PORTP_INEN_PIN19_Pos) +#define PORT_PORTP_INEN_PIN20_Pos 20 +#define PORT_PORTP_INEN_PIN20_Msk (0x01 << PORT_PORTP_INEN_PIN20_Pos) +#define PORT_PORTP_INEN_PIN21_Pos 21 +#define PORT_PORTP_INEN_PIN21_Msk (0x01 << PORT_PORTP_INEN_PIN21_Pos) +#define PORT_PORTP_INEN_PIN22_Pos 22 +#define PORT_PORTP_INEN_PIN22_Msk (0x01 << PORT_PORTP_INEN_PIN22_Pos) +#define PORT_PORTP_INEN_PIN23_Pos 23 +#define PORT_PORTP_INEN_PIN23_Msk (0x01 << PORT_PORTP_INEN_PIN23_Pos) + typedef struct { __IO uint32_t DATA; @@ -558,44 +1165,44 @@ typedef struct #define PIN23 23 #define PIN24 24 - __IO uint32_t DIR; //0 闁跨喐鏋婚幏鐑芥晸閺傘倖瀚� 1 闁跨喐鏋婚幏鐑芥晸閿燂拷 + __IO uint32_t DIR; //0 输入 1 输出 - __IO uint32_t INTLVLTRG; //Interrupt Level Trigger 1 闁跨喐鏋婚幏宄伴挬闁跨喐鏋婚幏鐑芥晸閺傘倖瀚归柨鐔峰建鐠佽瀚� 0 闁跨喐鏋婚幏鐑芥晸閹搭亣鎻幏鐑芥晸閺傘倖瀚归柨鐔峰建鐠佽瀚� + __IO uint32_t INTLVLTRG; //Interrupt Level Trigger 1 电平触发中断 0 边沿触发中断 - __IO uint32_t INTBE; //Both Edge闁跨喐鏋婚幏鐑芥晸閺傘倖瀚笽NTLVLTRG闁跨喐鏋婚幏铚傝礋闁跨喐鏋婚幏鐑芥晸閹搭亣鎻幏鐑芥晸閺傘倖瀚归柨鐔峰建鐠佽瀚归弮鍫曟晸閺傘倖瀚归柨鐔告灮閹疯渹缍呴柨鐔告灮閹凤拷1闁跨喐鏋婚幏椋庛仛闁跨喐鏋婚幏鐑芥晸閺傘倖瀚归柨鐔稿焻閻氬瓨瀚归柨鐔兼應閺傘倖瀚归柨鐔稿焻鐠佽瀚归柨鐔告灮閹风兘鏁撻弬銈嗗闁跨喎褰ㄩ弬顓ㄧ秶閹风兘鏁撻弬銈嗗0閺冨爼鏁撻弬銈嗗闁跨喐鏋婚幏鐑芥晸閺傘倖瀚归柨鐔告灮閹风兘鏁撻弬銈嗗INTRISEEN闁鏁撻弬銈嗗 + __IO uint32_t INTBE; //Both Edge，当INTLVLTRG设为边沿触发中断时，此位置1表示上升沿和下降沿都触发中断，置0时触发边沿由INTRISEEN选择 - __IO uint32_t INTRISEEN; //Interrupt Rise Edge Enable 1 闁跨喐鏋婚幏鐑芥晸閺傘倖瀚归柨鐔告灮閹凤拷/闁跨喓顏喊澶嬪楠炴娊鏁撻弬銈嗗闁跨喐鏋婚幏鐑芥晸閸欘偉顔愰幏锟� 0 闁跨喖鎽弬銈嗗闁跨喐鏋婚幏锟�/闁跨喖鍙虹喊澶嬪楠炴娊鏁撻弬銈嗗闁跨喐鏋婚幏鐑芥晸閸欘偉顔愰幏锟� + __IO uint32_t INTRISEEN; //Interrupt Rise Edge Enable 1 上升沿/高电平触发中断 0 下降沿/低电平触发中断 - __IO uint32_t INTEN; //1 闁跨喎褰ㄧ拋瑙勫娴ｅ潡鏁撻弬銈嗗 0 闁跨喎褰ㄩ弬顓熸灮閹烽攱顒� + __IO uint32_t INTEN; //1 中断使能 0 中断禁止 - __IO uint32_t INTRAWSTAT; //闁跨喎褰ㄩ弬顓犮€嬮幏椋庡禃閵夋棏浜烽幏閿嬬懞闁跨喐鏋婚幏椋庡禃閺傘倖瀚归懜婊堟晸閺傘倖瀚归柨鐔告灮閹峰嘲宓忕化濠氭晸閺傘倖瀚归柨鐔告灮閹风兘鏁撻敓锟� 1 闁跨喐鏋婚幏椋庡禃閺傘倖瀚归柨鐔告灮閹峰嘲宓忓ú妤呮晸閺傘倖瀚归柨鐔告灮閹风兘鏁撻弬銈嗗闁跨噦鎷� 0 濞岋繝鏁撻崣顐ゃ€嬮幏椋庡禃閺傘倖瀚归崡鍛婄闁跨喐鏋婚幏鐑芥晸閺傘倖瀚归柨鐔告灮閹风兘鏁撻敓锟� + __IO uint32_t INTRAWSTAT; //中断检测单元是否检测到了触发中断的条件 1 检测到了中断触发条件 0 没有检测到中断触发条件 __IO uint32_t INTSTAT; //INTSTAT.PIN0 = INTRAWSTAT.PIN0 & INTEN.PIN0 - __IO uint32_t INTCLR; //閸愶拷1闁跨喐鏋婚幏鐑芥晸閺傘倖瀚归崡绋款€掗柨鐔活敎閹惧懏瀚归柨鐔活敎娴兼瑦瀚归崨姗€鏁撻弬銈嗗閸楊噣鏁撻弬銈嗗闁跨喐鏋婚幏宄板祻闁跨喐鏋婚幏鐑芥晸閺傘倖瀚归柨鐕傛嫹 + __IO uint32_t INTCLR; //写1清除中断标志，只对边沿触发中断有用 } GPIO_TypeDef; typedef struct { - __IO uint32_t LDVAL; //闁跨喐鏋婚幏閿嬫闁跨喐鏋婚幏鐑芥晸閺傘倖瀚归柨鐔告灮閹峰嘲鈧ジ鏁撻弬銈嗗娴ｅ潡鏁撻弶鎵皑閹烽攱妞傞柨鐔告灮閹风兘鏁撻幒銉ㄦ彧閹风兘鏁撻弬銈嗗閸婂ジ鏁撻弬銈嗗婵鏁撻弬銈嗗闁跨喖鎽柅鎺斻€嬮幏鐑芥晸閺傘倖瀚归柨鐔告灮閹凤拷 + __IO uint32_t LDVAL; //定时器加载值，使能后定时器从此数值开始向下递减计数 - __I uint32_t CVAL; //闁跨喐鏋婚幏閿嬫闁跨喐鏋婚幏鐑芥晸閺傘倖瀚归崜宥呪偓濂告晸閺傘倖瀚筁DVAL-CVAL 闁跨喓鍗崇涵閿嬪闁跨喐鏋婚幏鐑芥晸閺傘倖瀚归柨鐔虹哺缁楁梹鍞婚幏鐑芥晸閿燂拷 + __I uint32_t CVAL; //定时器当前值，LDVAL-CVAL 可计算出计时时长 __IO uint32_t CTRL; } TIMR_TypeDef; -#define TIMR_CTRL_EN_Pos 0 //闁跨喐鏋婚幏铚傜秴闁跨喐鏋婚幏锟�1闁跨喐鏋婚幏鐑芥晸閺傘倖瀚筎IMR闁跨喐鏋婚幏绋珼VAL闁跨喐鏋婚幏宄邦潗闁跨喐鏋婚幏鐑芥晸闁句即鈧帞銆嬮幏鐑芥晸閺傘倖瀚归柨鐔告灮閹凤拷 +#define TIMR_CTRL_EN_Pos 0 //此位赋1导致TIMR从LDVAL开始向下递减计数 #define TIMR_CTRL_EN_Msk (0x01 << TIMR_CTRL_EN_Pos) -#define TIMR_CTRL_CLKSRC_Pos 1 //閺冨爼鏁撻弬銈嗗濠ф劙鏁撻弬銈嗗0 闁跨喕濡拠褎瀚圭化鑽ょ埠閺冨爼鏁撻弬銈嗗 1 闁跨喕袙闁劑鏁撻弬銈嗗闁跨喐鏋婚幏鐑芥晸閺傘倖瀚归柨鐔告灮閹风兘鏁撻弬銈嗗闁跨噦鎷� +#define TIMR_CTRL_CLKSRC_Pos 1 //时钟源：0 内部系统时钟 1 外部引脚脉冲计数 #define TIMR_CTRL_CLKSRC_Msk (0x01 << TIMR_CTRL_CLKSRC_Pos) -#define TIMR_CTRL_CASCADE_Pos 2 //1 TIMRx闁跨喍鑼庣涵閿嬪闁跨喐鏋婚幏閿嬫闁跨喐鏋婚幏铚傝礋TIMRx-1闁跨喐鏋婚幏鐑芥晸閺傘倖瀚归柨鐔告灮閹风柉妫旈柨鐕傛嫹 +#define TIMR_CTRL_CASCADE_Pos 2 //1 TIMRx的计数时钟为TIMRx-1的溢出信号 #define TIMR_CTRL_CASCADE_Msk (0x01 << TIMR_CTRL_CASCADE_Pos) typedef struct { - __IO uint32_t PCTRL; //Pulse Control闁跨喐鏋婚幏鐑芥晸閺傘倖瀚归柨鐔告灮閹风兘鏁撻弬銈嗗闁跨喍鑼庨敐蹇斿闁跨喐鏋婚幏鐑芥晸閻欌€崇槑鏉堢偓瀚归柨鐔告灮閹凤拷 + __IO uint32_t PCTRL; //Pulse Control，脉宽测量模块控制寄存器 - __I uint32_t PCVAL; //闁跨喐鏋婚幏鐑芥晸閺傘倖瀚归柨鐔告灮閹风兘鏁撻弬銈嗗闁跨喓绮搁幉瀣闁跨喐鏋婚幏鐑芥晸鐟欐帞鍩滈敓锟� + __I uint32_t PCVAL; //脉宽测量定时器当前值 uint32_t RESERVED[2]; @@ -606,11 +1213,11 @@ typedef struct __IO uint32_t HALT; } TIMRG_TypeDef; -#define TIMRG_PCTRL_EN_Pos 0 //闁跨喐鏋婚幏宄邦潗闁跨喐鏋婚幏鐑芥晸閺傘倖瀚归柨鐔告灮閹风兘鏁撻弬銈嗗闁跨喐鏋婚幏鐑芥晸閺傘倖瀚归柨鐔告灮閹凤拷32娴ｅ秹鏁撻弬銈嗗闁跨喐鏋婚幏鐑芥晸閺傘倖瀚归柨鐔告灮閹凤拷0闁跨喐鏋婚幏宄邦潗闁跨喐鏋婚幏鐑芥晸鏉堝啰銆嬮幏鐑芥晸閺傘倖瀚� +#define TIMRG_PCTRL_EN_Pos 0 //开始测量脉宽，脉宽内32位计数器从0开始向上计数 #define TIMRG_PCTRL_EN_Msk (0x01 << TIMRG_PCTRL_EN_Pos) -#define TIMRG_PCTRL_HIGH_Pos 1 //0 闁跨喐鏋婚幏鐑芥晸閺傘倖瀚归柨鐔煎徍绾板瀚归獮鎶芥晸閺傘倖瀚归柨鐔告灮閹凤拷 1 闁跨喐鏋婚幏鐑芥晸閺傘倖瀚归柨鐔侯仾绾板瀚归獮鎶芥晸閺傘倖瀚归柨鐔告灮閹凤拷 +#define TIMRG_PCTRL_HIGH_Pos 1 //0 测量低电平长度 1 测量高电平长度 #define TIMRG_PCTRL_HIGH_Msk (0x01 << TIMRG_PCTRL_HIGH_Pos) -#define TIMRG_PCTRL_CLKSRC_Pos 2 //閺冨爼鏁撻弬銈嗗濠ф劙鏁撻弬銈嗗0 闁跨喕濡拠褎瀚圭化鑽ょ埠閺冨爼鏁撻弬銈嗗 1 闁跨喐鏋婚幏鐑芥晸閺傘倖瀚归柨鐔告灮閹风兘鏁撴笟銉秶閹风兘鏁撻弬銈嗗闁跨喐褰导娆愬闁跨喐鏋婚幏鐑芥晸閺傘倖瀚归柨鐔告灮閹风兘鏁撻弬銈嗗闁跨喐鏋婚幏鐑芥晸閺傘倖瀚归崐顒勬晸閺傘倖瀚归柨鐔告灮閹风兘鏁撻弬銈嗗闁跨喐鏋婚幏鐑芥晸閺傘倖瀚归柨鐔告灮閹风兘鏁撻弬銈嗗 +#define TIMRG_PCTRL_CLKSRC_Pos 2 //时钟源：0 内部系统时钟 1 脉宽测量模块变成一个计数器，不再具有脉宽测量功能 #define TIMRG_PCTRL_CLKSRC_Msk (0x01 << TIMRG_PCTRL_CLKSRC_Pos) #define TIMRG_IE_TIMR0_Pos 0 @@ -628,7 +1235,7 @@ typedef struct #define TIMRG_IE_PULSE_Pos 16 #define TIMRG_IE_PULSE_Msk (0x01 << TIMRG_IE_PULSE_Pos) -#define TIMRG_IF_TIMR0_Pos 0 //閸愶拷1闁跨喐鏋婚幏鐑芥晸閺傘倖瀚� +#define TIMRG_IF_TIMR0_Pos 0 //写1清零 #define TIMRG_IF_TIMR0_Msk (0x01 << TIMRG_IF_TIMR0_Pos) #define TIMRG_IF_TIMR1_Pos 1 #define TIMRG_IF_TIMR1_Msk (0x01 << TIMRG_IF_TIMR1_Pos) @@ -643,7 +1250,7 @@ typedef struct #define TIMRG_IF_PULSE_Pos 16 #define TIMRG_IF_PULSE_Msk (0x01 << TIMRG_IF_PULSE_Pos) -#define TIMRG_HALT_TIMR0_Pos 0 //1 闁跨喐鏋婚幏宄颁粻闁跨喐鏋婚幏鐑芥晸閺傘倖瀚� +#define TIMRG_HALT_TIMR0_Pos 0 //1 暂停计数 #define TIMRG_HALT_TIMR0_Msk (0x01 << TIMRG_HALT_TIMR0_Pos) #define TIMRG_HALT_TIMR1_Pos 1 #define TIMRG_HALT_TIMR1_Msk (0x01 << TIMRG_HALT_TIMR1_Pos) @@ -678,116 +1285,114 @@ typedef struct #define UART_DATA_DATA_Pos 0 #define UART_DATA_DATA_Msk (0x1FF << UART_DATA_DATA_Pos) -#define UART_DATA_VALID_Pos 9 //闁跨喐鏋婚幏绋TA闁跨喕顢滅拋瑙勫闁跨喐鏋婚幏鐑芥晸閺傘倖瀚归弫鍫ユ晸娓氥儲鏋婚幏鐑芥晸閺傘倖瀚归柨鐔告灮閹风兘鏁撻弬銈嗗閺冨爼鏁撻弬銈嗗闁跨喐鏋婚幏铚傜秴绾剟鏁撻弬銈嗗闁跨喐鏋婚幏锟�1闁跨喐鏋婚幏鐑芥晸閺傘倖瀚归崣鏍晸閺傘倖瀚归柨鐔稿祹閻氬瓨瀚归柨鐔烘畷鐠佽瀚归柨鐔告灮閹风兘鏁撻弬銈嗗 +#define UART_DATA_VALID_Pos 9 //当DATA字段有有效的接收数据时，该位硬件置1，读取数据后自动清零 #define UART_DATA_VALID_Msk (0x01 << UART_DATA_VALID_Pos) #define UART_DATA_PAERR_Pos 10 //Parity Error #define UART_DATA_PAERR_Msk (0x01 << UART_DATA_PAERR_Pos) -#define UART_CTRL_TXIDLE_Pos 0 //TX IDLE: 0 闁跨喐鏋婚幏鐑芥晸閼哄倸鍤栭幏鐑芥晸閺傘倖瀚归柨鐔告灮閹风兘鏁撻弬銈嗗 1 闁跨喐鏋婚幏鐑芥晸閺傘倖瀚归悩鑸碘偓渚€鏁撻弬銈嗗濞岋繝鏁撻弬銈嗗闁跨喐鏋婚幏鐑芥晸閹瑰嘲鍤栭幏鐑芥晸閺傘倖瀚� +#define UART_CTRL_TXIDLE_Pos 0 //TX IDLE: 0 正在发送数据 1 空闲状态，没有数据发送 #define UART_CTRL_TXIDLE_Msk (0x01 << UART_CTRL_TXIDLE_Pos) #define UART_CTRL_TXFF_Pos 1 //TX FIFO Full #define UART_CTRL_TXFF_Msk (0x01 << UART_CTRL_TXFF_Pos) -#define UART_CTRL_TXIE_Pos 2 //TX 闁跨喎褰ㄧ拋瑙勫娴ｅ潡鏁撻弬銈嗗: 1 TX FF 闁跨喐鏋婚幏鐑芥晸閺傘倖瀚归柨鐔告灮閹风兘鏁撻弬銈嗗闁跨喐鏋婚幏鐑芥晸閸婄喎鐣鹃柨鐔告灮閹风兘鏁撻弬銈嗗閺冨爼鏁撻弬銈嗗闁跨喐鏋婚幏鐑芥晸閸欘偉顔愰幏锟� +#define UART_CTRL_TXIE_Pos 2 //TX 中断使能: 1 TX FF 中数据少于设定个数时产生中断 #define UART_CTRL_TXIE_Msk (0x01 << UART_CTRL_TXIE_Pos) #define UART_CTRL_RXNE_Pos 3 //RX FIFO Not Empty #define UART_CTRL_RXNE_Msk (0x01 << UART_CTRL_RXNE_Pos) -#define UART_CTRL_RXIE_Pos 4 //RX 闁跨喎褰ㄧ拋瑙勫娴ｅ潡鏁撻弬銈嗗: 1 RX FF 闁跨喐鏋婚幏鐑芥晸閺傘倖瀚归柨鐔稿祹鏉堟儳鍩岄柨鐔封偓鐔风暰闁跨喐鏋婚幏鐑芥晸閺傘倖瀚归弮鍫曟晸閺傘倖瀚归柨鐔告灮閹风兘鏁撻崣顐ヮ啇閹凤拷 +#define UART_CTRL_RXIE_Pos 4 //RX 中断使能: 1 RX FF 中数据达到设定个数时产生中断 #define UART_CTRL_RXIE_Msk (0x01 << UART_CTRL_RXIE_Pos) -#define UART_CTRL_RXOV_Pos 5 //RX FIFO Overflow闁跨喐鏋婚幏宄板晸1闁跨喐鏋婚幏鐑芥晸閺傘倖瀚� +#define UART_CTRL_RXOV_Pos 5 //RX FIFO Overflow，写1清零 #define UART_CTRL_RXOV_Msk (0x01 << UART_CTRL_RXOV_Pos) -#define UART_CTRL_TXDOIE_Pos 6 //TX Done 闁跨喎褰ㄧ拋瑙勫娴ｅ潡鏁撻弶甯秶閹风兘鏁撻弬銈嗗闁跨喐鏋婚幏绋FO闁跨喐鏋婚幏鐑芥晸閹活厼鍤栭幏鐑芥晸闁伴潧鍤栭幏鐑芥晸閺傘倖瀚归柨鐔告灮閹疯渹缍呴柨鐔惰寧鏉堢偓瀚归柨鐔告灮閹风兘鏁撶粣鏍ㄦ灮閹风兘鏁撻弬銈嗗闁跨喐褰弲鍐х串閹风兘鏁撻弬銈嗗缂佺喖鏁撴鐚存嫹 +#define UART_CTRL_TXDOIE_Pos 6 //TX Done 中断使能，发送FIFO空且发送发送移位寄存器已将最后一位发送出去 #define UART_CTRL_TXDOIE_Msk (0x01 << UART_CTRL_TXDOIE_Pos) #define UART_CTRL_EN_Pos 9 #define UART_CTRL_EN_Msk (0x01 << UART_CTRL_EN_Pos) #define UART_CTRL_LOOP_Pos 10 #define UART_CTRL_LOOP_Msk (0x01 << UART_CTRL_LOOP_Pos) -#define UART_CTRL_BAUDEN_Pos 13 //闁跨喐鏋婚幏鐑芥晸閺傘倖瀚归崘锟�1 +#define UART_CTRL_BAUDEN_Pos 13 //必须写1 #define UART_CTRL_BAUDEN_Msk (0x01 << UART_CTRL_BAUDEN_Pos) -#define UART_CTRL_TOIE_Pos 14 //TimeOut 闁跨喎褰ㄧ拋瑙勫娴ｅ潡鏁撻弶甯秶閹风兘鏁撻弬銈嗗闁跨喓笑绾板瀚归柨鐔荤窛闂堚晜瀚归柨鐔活敎閸戙倖瀚归柨鐔活殼閿涘瞼顒查幏鐑芥晸閺傘倖瀚� TOTIME/BAUDRAUD 闁跨喐鏋婚幏閿嬬梾闁跨喎褰ㄩ弬銈嗗闁跨喓笑绾板瀚归柨鐔兼應绾板瀚归柨鐔告灮閹风兘鏁撻弬銈嗗 +#define UART_CTRL_TOIE_Pos 14 //TimeOut 中断使能，接收到上个字符后，超过 TOTIME/BAUDRAUD 秒没有接收到新的数据 #define UART_CTRL_TOIE_Msk (0x01 << UART_CTRL_TOIE_Pos) -#define UART_CTRL_BRKDET_Pos 15 //LIN Break Detect闁跨喐鏋婚幏鐑芥晸閺傘倖瀚归悰鍓хオIN Break闁跨喐鏋婚幏鐑芥晸閺傘倖瀚筊X闁跨喐鏋婚幏鐑芥晸鏉堝啰銆嬮幏椋庡禃閺傘倖瀚归柨鐔告灮閹风兘鏁撻敓锟�11娴ｅ秹鏁撻柊鐢殿暜閹峰嘲閽� +#define UART_CTRL_BRKDET_Pos 15 //LIN Break Detect，检测到LIN Break，即RX线上检测到连续11位低电平 #define UART_CTRL_BRKDET_Msk (0x01 << UART_CTRL_BRKDET_Pos) -#define UART_CTRL_BRKIE_Pos 16 //LIN Break Detect 闁跨喎褰ㄧ拋瑙勫娴ｅ潡鏁撻弬銈嗗 +#define UART_CTRL_BRKIE_Pos 16 //LIN Break Detect 中断使能 #define UART_CTRL_BRKIE_Msk (0x01 << UART_CTRL_BRKIE_Pos) -#define UART_CTRL_GENBRK_Pos 17 //Generate LIN Break闁跨喐鏋婚幏鐑芥晸閺傘倖瀚归柨鐔告灮閹风ìIN Break +#define UART_CTRL_GENBRK_Pos 17 //Generate LIN Break，发送LIN Break #define UART_CTRL_GENBRK_Msk (0x01 << UART_CTRL_GENBRK_Pos) -#define UART_CTRL_DATA9b_Pos 18 //1 9娴ｅ秹鏁撻弬銈嗗闁跨喐鏋婚幏铚傜秴 0 8娴ｅ秹鏁撻弬銈嗗闁跨喐鏋婚幏铚傜秴 +#define UART_CTRL_DATA9b_Pos 18 //1 9位数据位 0 8位数据位 #define UART_CTRL_DATA9b_Msk (0x01 << UART_CTRL_DATA9b_Pos) -#define UART_CTRL_PARITY_Pos 19 //000 闁跨喐鏋婚幏閿嬬墡闁跨喐鏋婚幏锟� 001 闁跨喐鏋婚幏閿嬬墡闁跨喐鏋婚幏锟� 011 閸嬭埖鐗庨柨鐔告灮閹凤拷 101 闁跨喐鏆€鐠佽瀚规稉锟�1 111 闁跨喐鏆€鐠佽瀚规稉锟�0 +#define UART_CTRL_PARITY_Pos 19 //000 无校验 001 奇校验 011 偶校验 101 固定为1 111 固定为0 #define UART_CTRL_PARITY_Msk (0x07 << UART_CTRL_PARITY_Pos) -#define UART_CTRL_STOP2b_Pos 22 //1 2娴ｅ秴浠犲顫秴 0 1娴ｅ秴浠犲顫秴 +#define UART_CTRL_STOP2b_Pos 22 //1 2位停止位 0 1位停止位 #define UART_CTRL_STOP2b_Msk (0x03 << UART_CTRL_STOP2b_Pos) -#define UART_CTRL_TOTIME_Pos 24 //TimeOut 閺冨爼鏁撻弬銈嗗 = TOTIME/(BAUDRAUD/10) 闁跨喐鏋婚幏锟� -//#define UART_CTRL_TOTIME_Msk (0xFF << UART_CTRL_TOTIME_Pos) 闁跨喐鏋婚幏鐑芥晸閺傘倖瀚归柨鐔告灮閹风兘鏁撻弬銈嗗闁跨喕濮ら敍锟� integer operation result is out of range -#define UART_CTRL_TOTIME_Msk ((uint32_t)0xFF << UART_CTRL_TOTIME_Pos) +#define UART_CTRL_TOTIME_Pos 24 //TimeOut 时长 = TOTIME/(BAUDRAUD/10) 秒 +#define UART_CTRL_TOTIME_Msk (0xFFu << UART_CTRL_TOTIME_Pos) -#define UART_BAUD_BAUD_Pos 0 //闁跨喐鏋婚幏鐑芥晸閼哄倽顕滈幏鐑芥晸閺傘倖瀚归柨鐔告灮閹凤拷 = SYS_Freq/16/BAUD - 1 +#define UART_BAUD_BAUD_Pos 0 //串口波特率 = SYS_Freq/16/BAUD - 1 #define UART_BAUD_BAUD_Msk (0x3FFF << UART_BAUD_BAUD_Pos) -#define UART_BAUD_TXD_Pos 14 //闁岸鏁撻弬銈嗗闁跨喐鏋婚幏铚傜秴闁跨喐鏋婚幏椋庢纯闁跨喐甯寸拋瑙勫閸欐牠鏁撻弬銈嗗闁跨喐鏋婚幏绋礨D闁跨喐鏋婚幏鐑芥晸閺傘倖瀚归柨鐔荤窛閻ㄥ嫮顣幏宄伴挬 +#define UART_BAUD_TXD_Pos 14 //通过此位可直接读取串口TXD引脚上的电平 #define UART_BAUD_TXD_Msk (0x01 << UART_BAUD_TXD_Pos) -#define UART_BAUD_RXD_Pos 15 //闁岸鏁撻弬銈嗗闁跨喐鏋婚幏铚傜秴闁跨喐鏋婚幏椋庢纯闁跨喐甯寸拋瑙勫閸欐牠鏁撻弬銈嗗闁跨喐鏋婚幏绋瞂D闁跨喐鏋婚幏鐑芥晸閺傘倖瀚归柨鐔荤窛閻ㄥ嫮顣幏宄伴挬 +#define UART_BAUD_RXD_Pos 15 //通过此位可直接读取串口RXD引脚上的电平 #define UART_BAUD_RXD_Msk (0x01 << UART_BAUD_RXD_Pos) -#define UART_BAUD_RXTOIF_Pos 16 //闁跨喐鏋婚幏鐑芥晸閺傘倖瀚�&闁跨喐鏋婚幏閿嬫闁跨喐鏋婚幏鐑芥晸閸欘偅鏌囬幉瀣韫囷拷 = RXIF | TOIF +#define UART_BAUD_RXTOIF_Pos 16 //接收&超时的中断标志 = RXIF | TOIF #define UART_BAUD_RXTOIF_Msk (0x01 << UART_BAUD_RXTOIF_Pos) -#define UART_BAUD_TXIF_Pos 17 //闁跨喐鏋婚幏鐑芥晸閺傘倖瀚归柨鐔峰建閺傤厽鍞婚幏宄扮箶 = TXTHRF & TXIE +#define UART_BAUD_TXIF_Pos 17 //发送中断标志 = TXTHRF & TXIE #define UART_BAUD_TXIF_Msk (0x01 << UART_BAUD_TXIF_Pos) -#define UART_BAUD_BRKIF_Pos 18 //LIN Break Detect 闁跨喎褰ㄩ弬顓熷敾閹峰嘲绻旈柨鐔告灮閹风兘鏁撻弬銈嗗閻涘墽绁狪N Break閺冨爼鏁撻弬銈嗗BRKIE=1闁跨喐鏋婚幏鐑芥晸閺傘倖瀚规担宥夋晸閺傘倖瀚圭涵顒勬晸閺傘倖瀚归柨鐔告灮閹疯渹缍� +#define UART_BAUD_BRKIF_Pos 18 //LIN Break Detect 中断标志，检测到LIN Break时若BRKIE=1，此位由硬件置位 #define UART_BAUD_BRKIF_Msk (0x01 << UART_BAUD_BRKIF_Pos) -#define UART_BAUD_RXTHRF_Pos 19 //RX FIFO Threshold Flag闁跨喐鏋婚幏绋瞂 FIFO闁跨喐鏋婚幏鐑芥晸閺傘倖瀚归柨鐔稿祹鏉堟儳鍩岄柨鐔封偓鐔风暰闁跨喐鏋婚幏鐑芥晸閺傘倖瀚归柨鐔告灮閹风úXLVL >= RXTHR闁跨喐鏋婚幏閿嬫绾剟鏁撻弬銈嗗闁跨喐鏋婚幏锟�1 +#define UART_BAUD_RXTHRF_Pos 19 //RX FIFO Threshold Flag，RX FIFO中数据达到设定个数（RXLVL >= RXTHR）时硬件置1 #define UART_BAUD_RXTHRF_Msk (0x01 << UART_BAUD_RXTHRF_Pos) -#define UART_BAUD_TXTHRF_Pos 20 //TX FIFO Threshold Flag闁跨喐鏋婚幏绋礨 FIFO闁跨喐鏋婚幏鐑芥晸閺傘倖瀚归柨鐔告灮閹风兘鏁撻弬銈嗗闁跨喐鏋婚幏鐑芥晸閸婄喎鐣鹃柨鐔告灮閹风兘鏁撻弬銈嗗闁跨喐鏋婚幏绋礨LVL <= TXTHR闁跨喐鏋婚幏閿嬫绾剟鏁撻弬銈嗗闁跨喐鏋婚幏锟�1 +#define UART_BAUD_TXTHRF_Pos 20 //TX FIFO Threshold Flag，TX FIFO中数据少于设定个数（TXLVL <= TXTHR）时硬件置1 #define UART_BAUD_TXTHRF_Msk (0x01 << UART_BAUD_TXTHRF_Pos) -#define UART_BAUD_TOIF_Pos 21 //TimeOut 闁跨喎褰ㄩ弬顓熷敾閹峰嘲绻旈柨鐔告灮閹风兘鏁撻弬銈嗗闁跨喐鏋婚幏锟� TOTIME/BAUDRAUD 闁跨喐鏋婚幏閿嬬梾闁跨喎褰ㄩ弬銈嗗闁跨喓笑绾板瀚归柨鐔兼應绾板瀚归柨鐔告灮閹风兘鏁撻弬銈嗗閺冨爼鏁撻弬銈嗗TOIE=1闁跨喐鏋婚幏鐑芥晸閺傘倖瀚规担宥夋晸閺傘倖瀚圭涵顒勬晸閺傘倖瀚归柨鐔告灮閹疯渹缍� +#define UART_BAUD_TOIF_Pos 21 //TimeOut 中断标志，超过 TOTIME/BAUDRAUD 秒没有接收到新的数据时若TOIE=1，此位由硬件置位 #define UART_BAUD_TOIF_Msk (0x01 << UART_BAUD_TOIF_Pos) -#define UART_BAUD_RXIF_Pos 22 //闁跨喐鏋婚幏鐑芥晸閺傘倖瀚归柨鐔峰建閺傤厽鍞婚幏宄扮箶 = RXTHRF & RXIE +#define UART_BAUD_RXIF_Pos 22 //接收中断标志 = RXTHRF & RXIE #define UART_BAUD_RXIF_Msk (0x01 << UART_BAUD_RXIF_Pos) -#define UART_BAUD_ABREN_Pos 23 //Auto Baudrate Enable闁跨喐鏋婚幏宄板晸1闁跨喐鏋婚幏鐑芥晸閻ㄥ棜顔愰幏鐑芥晸閺傘倖瀚归柨鐔告灮閹风兘鏁撻弬銈嗗閺嶁€冲櫙闁跨喐鏋婚幏鐑芥晸閺傘倖瀚归悵濠囨晸閺傘倖瀚规潻婊堟晸閺傘倖瀚归柨鐔告灮閹风兘鏁撻敓锟� +#define UART_BAUD_ABREN_Pos 23 //Auto Baudrate Enable，写1启动自动波特率校准，完成后自动清零 #define UART_BAUD_ABREN_Msk (0x01 << UART_BAUD_ABREN_Pos) -#define UART_BAUD_ABRBIT_Pos 24 //Auto Baudrate Bit闁跨喐鏋婚幏鐑芥晸閺傘倖瀚归柨鐔诲Ν绾攱瀚归柨鐔奉潟濞夈垽鏁撻弬銈嗗闁跨喓绮搁惃鍕€嬮幏鐑芥晸鏉炲じ绱幏鐑芥晸閺傘倖瀚归柨鐕傛嫹0 1娴ｅ秹鏁撻弬銈嗗闁岸鏁撻弬銈嗗闁跨喐鏋婚幏鐑芥晸閺傘倖瀚规慨瀣╃秴 闁跨喐鏋婚幏鐑芥晸閺傘倖瀚归柨鐔告灮閹烽攱鍋為…鎺撳闁跨喐鏋婚幏宄板⒖闁跨喐褰搴㈠闁跨喐鏋婚幏閿嬪閺堟棃鏁撻弬銈嗗闁跨噦鎷�0xFF -// 1 2娴ｅ秹鏁撻弬銈嗗闁岸鏁撻弬銈嗗闁跨喐鏋婚幏鐑芥晸閺傘倖瀚规慨瀣╃秴闁跨喐鏋婚幏锟�1娴ｅ秹鏁撻弬銈嗗闁跨喐鏋婚幏铚傜秴闁跨喐鏋婚幏鐑芥晸閺傘倖瀚归柨鐔告灮閹烽攱鍋為…鎺撳闁跨喐鏋婚幏宄板⒖闁跨喐褰搴㈠闁跨喐鏋婚幏閿嬪閺堟棃鏁撻弬銈嗗闁跨噦鎷�0xFE -// 1 4娴ｅ秹鏁撻弬銈嗗闁岸鏁撻弬銈嗗闁跨喐鏋婚幏鐑芥晸閺傘倖瀚规慨瀣╃秴闁跨喐鏋婚幏锟�3娴ｅ秹鏁撻弬銈嗗闁跨喐鏋婚幏铚傜秴闁跨喐鏋婚幏鐑芥晸閺傘倖瀚归柨鐔告灮閹烽攱鍋為…鎺撳闁跨喐鏋婚幏宄板⒖闁跨喐褰搴㈠闁跨喐鏋婚幏閿嬪閺堟棃鏁撻弬銈嗗闁跨噦鎷�0xF8 -// 1 8娴ｅ秹鏁撻弬銈嗗闁岸鏁撻弬銈嗗闁跨喐鏋婚幏鐑芥晸閺傘倖瀚规慨瀣╃秴闁跨喐鏋婚幏锟�7娴ｅ秹鏁撻弬銈嗗闁跨喐鏋婚幏铚傜秴闁跨喐鏋婚幏鐑芥晸閺傘倖瀚归柨鐔告灮閹烽攱鍋為…鎺撳闁跨喐鏋婚幏宄板⒖闁跨喐褰搴㈠闁跨喐鏋婚幏閿嬪閺堟棃鏁撻弬銈嗗闁跨噦鎷�0x80 +#define UART_BAUD_ABRBIT_Pos 24 /*Auto Baudrate Bit，用于计算波特率的检测位长，0 1位，通过测起始位 脉宽计算波特率，要求发送端发送0xFF \ + // 1 2位，通过测起始位加1位数据位脉宽计算波特率，要求发送端发送0xFE \ + // 1 4位，通过测起始位加3位数据位脉宽计算波特率，要求发送端发送0xF8 \ + // 1 8位，通过测起始位加7位数据位脉宽计算波特率，要求发送端发送0x80 */ #define UART_BAUD_ABRBIT_Msk (0x03 << UART_BAUD_ABRBIT_Pos) -#define UART_BAUD_ABRERR_Pos 26 //Auto Baudrate Error闁跨喐鏋婚幏锟�0 闁跨喓娈曠拋瑙勫闁跨喐鏋婚幏鐑芥晸閺傘倖瀚归柨鐔告灮閹烽攱鐗庨崙鍡涙晸缂傚娅㈤幏锟� 1 闁跨喓娈曠拋瑙勫闁跨喐鏋婚幏鐑芥晸閺傘倖瀚归柨鐔告灮閹烽攱鐗庨崙鍡椼亼闁跨喐鏋婚幏锟� +#define UART_BAUD_ABRERR_Pos 26 //Auto Baudrate Error，0 自动波特率校准成功 1 自动波特率校准失败 #define UART_BAUD_ABRERR_Msk (0x01 << UART_BAUD_ABRERR_Pos) -#define UART_BAUD_TXDOIF_Pos 27 //TX Done 闁跨喎褰ㄩ弬顓熷敾閹峰嘲绻旈柨鐔告灮閹风兘鏁撻弬銈嗗闁跨喐鏋婚幏绋FO闁跨喐鏋婚幏鐑芥晸閹活厼鍤栭幏鐑芥晸闁伴潧鍤栭幏鐑芥晸閺傘倖瀚归柨鐔告灮閹疯渹缍呴柨鐔惰寧鏉堢偓瀚归柨鐔告灮閹风兘鏁撶粣鏍ㄦ灮閹风兘鏁撻弬銈嗗闁跨喐褰弲鍐х串閹风兘鏁撻弬銈嗗缂佺喖鏁撴鐚存嫹 +#define UART_BAUD_TXDOIF_Pos 27 //TX Done 中断标志，发送FIFO空且发送发送移位寄存器已将最后一位发送出去 #define UART_BAUD_TXDOIF_Msk (0x01 << UART_BAUD_TXDOIF_Pos) -#define UART_FIFO_RXLVL_Pos 0 //RX FIFO Level闁跨喐鏋婚幏绋瞂 FIFO 闁跨喐鏋婚幏鐑芥晸鐞涙鍤栭幏鐑芥晸閺傘倖瀚归柨鐔告灮閹凤拷 +#define UART_FIFO_RXLVL_Pos 0 //RX FIFO Level，RX FIFO 中字符个数 #define UART_FIFO_RXLVL_Msk (0xFF << UART_FIFO_RXLVL_Pos) -#define UART_FIFO_TXLVL_Pos 8 //TX FIFO Level闁跨喐鏋婚幏绋礨 FIFO 闁跨喐鏋婚幏鐑芥晸鐞涙鍤栭幏鐑芥晸閺傘倖瀚归柨鐔告灮閹凤拷 +#define UART_FIFO_TXLVL_Pos 8 //TX FIFO Level，TX FIFO 中字符个数 #define UART_FIFO_TXLVL_Msk (0xFF << UART_FIFO_TXLVL_Pos) -#define UART_FIFO_RXTHR_Pos 16 //RX FIFO Threshold闁跨喐鏋婚幏绋瞂闁跨喎褰ㄩ弬顓℃彧閹风兘鏁撻弬銈嗗闁跨喐鏋婚幏鐑芥晸閻偓缍囬幏鐑芥晸閸欘偉顔愰幏铚傚▏闁跨喐鏋婚幏閿嬫 RXLVL >= RXTHR 闁跨喐鏋婚幏鐑芥晸閺傘倖瀚筊X闁跨喎褰ㄧ拋瑙勫 +#define UART_FIFO_RXTHR_Pos 16 //RX FIFO Threshold，RX中断触发门限，中断使能时 RXLVL >= RXTHR 触发RX中断 #define UART_FIFO_RXTHR_Msk (0xFF << UART_FIFO_RXTHR_Pos) -#define UART_FIFO_TXTHR_Pos 24 //TX FIFO Threshold闁跨喐鏋婚幏绋礨闁跨喎褰ㄩ弬顓℃彧閹风兘鏁撻弬銈嗗闁跨喐鏋婚幏鐑芥晸閻偓缍囬幏鐑芥晸閸欘偉顔愰幏铚傚▏闁跨喐鏋婚幏閿嬫 TXLVL <= TXTHR 闁跨喐鏋婚幏鐑芥晸閺傘倖瀚筎X闁跨喎褰ㄧ拋瑙勫 -//#define UART_FIFO_TXTHR_Msk (0xFF << UART_FIFO_TXTHR_Pos) 闁跨喐鏋婚幏鐑芥晸閺傘倖瀚归柨鐔告灮閹风兘鏁撻弬銈嗗闁跨喕濮ら敍锟� integer operation result is out of range -#define UART_FIFO_TXTHR_Msk ((uint32_t)0xFF << UART_FIFO_TXTHR_Pos) - -#define UART_LINCR_BRKDETIE_Pos 0 //闁跨喐鏋婚幏椋庡禃缁插儐N Break闁跨喎褰ㄧ拋瑙勫娴ｅ潡鏁撻弬銈嗗 -#define UART_LINCR_BRKDETIE_Msk (0xFF << UART_LINCR_BRKDETIE_Pos) -#define UART_LINCR_BRKDETIF_Pos 1 //闁跨喐鏋婚幏椋庡禃缁插儐N Break闁跨喎褰ㄧ拋瑙勫閻樿埖鈧拷 -#define UART_LINCR_BRKDETIF_Msk (0xFF << UART_LINCR_BRKDETIF_Pos) -#define UART_LINCR_GENBRKIE_Pos 2 //闁跨喐鏋婚幏鐑芥晸閺傘倖瀚筁IN Break闁跨喐鏋婚幏鐑芥晸閺傘倖瀚归崡鎼佹晸缂佺偟娅㈤幏鐑芥晸閿燂拷 -#define UART_LINCR_GENBRKIE_Msk (0xFF << UART_LINCR_GENBRKIE_Pos) -#define UART_LINCR_GENBRKIF_Pos 3 //闁跨喐鏋婚幏鐑芥晸閺傘倖瀚筁IN Break闁跨喐鏋婚幏鐑芥晸閺傘倖瀚归崡鎼佹晸闂冭泛鍩￠敓锟� -#define UART_LINCR_GENBRKIF_Msk (0xFF << UART_LINCR_GENBRKIF_Pos) -#define UART_LINCR_GENBRK_Pos 4 //闁跨喐鏋婚幏鐑芥晸閺傘倖瀚筁IN Break闁跨喐鏋婚幏鐑芥晸閺傘倖瀚归柨鐔告灮閹风兘鏁撻弬銈嗗闁跨喐鏋婚幏鐤箼闁跨喐鏋婚幏鐑芥晸閺傘倖瀚归柨鐕傛嫹 -#define UART_LINCR_GENBRK_Msk (0xFF << UART_LINCR_GENBRK_Pos) - -#define UART_CTSCR_EN_Pos 0 //CTS闁跨喐鏋婚幏鐑芥晸閺傘倖瀚规担鍧楁晸閺傘倖瀚� +#define UART_FIFO_TXTHR_Pos 24 //TX FIFO Threshold，TX中断触发门限，中断使能时 TXLVL <= TXTHR 触发TX中断 +#define UART_FIFO_TXTHR_Msk (0xFFu << UART_FIFO_TXTHR_Pos) + +#define UART_LINCR_BRKDETIE_Pos 0 //检测到LIN Break中断使能 +#define UART_LINCR_BRKDETIE_Msk (0x01 << UART_LINCR_BRKDETIE_Pos) +#define UART_LINCR_BRKDETIF_Pos 1 //检测到LIN Break中断状态 +#define UART_LINCR_BRKDETIF_Msk (0x01 << UART_LINCR_BRKDETIF_Pos) +#define UART_LINCR_GENBRKIE_Pos 2 //发送LIN Break完成中断使能 +#define UART_LINCR_GENBRKIE_Msk (0x01 << UART_LINCR_GENBRKIE_Pos) +#define UART_LINCR_GENBRKIF_Pos 3 //发送LIN Break完成中断状态 +#define UART_LINCR_GENBRKIF_Msk (0x01 << UART_LINCR_GENBRKIF_Pos) +#define UART_LINCR_GENBRK_Pos 4 //发送LIN Break，发送完成自动清零 +#define UART_LINCR_GENBRK_Msk (0x01 << UART_LINCR_GENBRK_Pos) + +#define UART_CTSCR_EN_Pos 0 //CTS流控使能 #define UART_CTSCR_EN_Msk (0x01 << UART_CTSCR_EN_Pos) -#define UART_CTSCR_POL_Pos 2 //CTS闁跨喕鍓奸崣椋庛€嬮幏鐑芥晸閻ㄥ棴缍囬幏锟�0 闁跨喐鏋婚幏鐑芥晸閺傘倖瀚归弫鍫ユ晸閺傘倖瀚笴TS闁跨喐鏋婚幏鐑芥晸閺傘倖瀚规稉娲晸闁板灚鍞婚幏椋庛仛闁跨喐鏋婚幏鐑芥晸閻ㄥ棗鍤栭幏鐑芥晸閺傘倖瀚归柨鐔告灮閹风兘鏁撻弬銈嗗 +#define UART_CTSCR_POL_Pos 2 //CTS信号极性，0 低有效，CTS输入为低表示可以发送数据 #define UART_CTSCR_POL_Msk (0x01 << UART_CTSCR_POL_Pos) -#define UART_CTSCR_STAT_Pos 7 //CTS闁跨喕鍓奸崣椋庢畱绾板瀚归崜宥囧Ц閹拷 +#define UART_CTSCR_STAT_Pos 7 //CTS信号的当前状态 #define UART_CTSCR_STAT_Msk (0x01 << UART_CTSCR_STAT_Pos) -#define UART_RTSCR_EN_Pos 1 //RTS闁跨喐鏋婚幏鐑芥晸閺傘倖瀚规担鍧楁晸閺傘倖瀚� +#define UART_RTSCR_EN_Pos 1 //RTS流控使能 #define UART_RTSCR_EN_Msk (0x01 << UART_RTSCR_EN_Pos) -#define UART_RTSCR_POL_Pos 3 //RTS闁跨喕鍓奸崣椋庛€嬮幏鐑芥晸閺傘倖瀚� 0 闁跨喐鏋婚幏鐑芥晸閺傘倖瀚归弫鍫ユ晸閺傘倖瀚筊TS闁跨喐鏋婚幏鐑芥晸閺傘倖瀚规稉娲晸闁板灚鍞婚幏椋庛仛闁跨喐鏋婚幏鐑芥晸閻ㄥ棙鏋婚幏鐑芥晸閺傘倖瀚归柨鐔告灮閹风兘鏁撻弬銈嗗 +#define UART_RTSCR_POL_Pos 3 //RTS信号极性 0 低有效，RTS输入为低表示可以接收数据 #define UART_RTSCR_POL_Msk (0x01 << UART_RTSCR_POL_Pos) -#define UART_RTSCR_THR_Pos 4 //RTS闁跨喐鏋婚幏鐑芥晸閹搭亞娈戞潏鐐闁跨喐鏋婚幏鐑芥晸閺傘倖瀚归崐锟� 0 1闁跨喕顢滈弬銈嗗 1 2闁跨喕顢滈弬銈嗗 2 4闁跨喕顢滈弬銈嗗 3 6闁跨喕顢滈弬銈嗗 +#define UART_RTSCR_THR_Pos 4 //RTS流控的触发阈值 0 1字节 1 2字节 2 4字节 3 6字节 #define UART_RTSCR_THR_Msk (0x07 << UART_RTSCR_THR_Pos) -#define UART_RTSCR_STAT_Pos 8 //RTS闁跨喕鍓奸崣椋庢畱绾板瀚归崜宥囧Ц閹拷 +#define UART_RTSCR_STAT_Pos 8 //RTS信号的当前状态 #define UART_RTSCR_STAT_Msk (0x01 << UART_RTSCR_STAT_Pos) typedef struct @@ -803,46 +1408,46 @@ typedef struct __IO uint32_t IF; } SPI_TypeDef; -#define SPI_CTRL_CLKDIV_Pos 0 //Clock Divider, SPI闁跨喐鏋婚幏鐑芥晸閺傘倖瀚归弮鍫曟晸閺傘倖瀚� = SYS_Freq/pow(2, CLKDIV+2) +#define SPI_CTRL_CLKDIV_Pos 0 //Clock Divider, SPI工作时钟 = SYS_Freq/pow(2, CLKDIV+2) #define SPI_CTRL_CLKDIV_Msk (0x07 << SPI_CTRL_CLKDIV_Pos) #define SPI_CTRL_EN_Pos 3 #define SPI_CTRL_EN_Msk (0x01 << SPI_CTRL_EN_Pos) -#define SPI_CTRL_SIZE_Pos 4 //Data Size Select, 閸欐牕鈧拷3--15闁跨喐鏋婚幏鐑芥晸閺傘倖瀚圭粈锟�4--16娴ｏ拷 +#define SPI_CTRL_SIZE_Pos 4 //Data Size Select, 取值3--15，表示4--16位 #define SPI_CTRL_SIZE_Msk (0x0F << SPI_CTRL_SIZE_Pos) -#define SPI_CTRL_CPHA_Pos 8 //0 闁跨喐鏋婚幏绋碈LK闁跨喍鑼庣喊澶嬪娑撯偓闁跨喐鏋婚幏鐑芥晸閺傘倖瀚归柨鐔告灮閹风兘鏁撻幋顏囶嚋閹风兘鏁撻弬銈嗗闁跨喐鏋婚幏鐑芥晸閺傘倖瀚� 1 闁跨喐鏋婚幏绋碈LK闁跨喍鑼庣粭顒冾啇閹风兘鏁撻弬銈嗗闁跨喐鏋婚幏鐑芥晸閺傘倖瀚归柨鐔稿焻鐠囇勫闁跨喐鏋婚幏鐑芥晸閺傘倖瀚归柨鐔告灮閹凤拷 +#define SPI_CTRL_CPHA_Pos 8 //0 在SCLK的第一个跳变沿采样数据 1 在SCLK的第二个跳变沿采样数据 #define SPI_CTRL_CPHA_Msk (0x01 << SPI_CTRL_CPHA_Pos) -#define SPI_CTRL_CPOL_Pos 9 //0 闁跨喐鏋婚幏鐑芥晸閺傘倖瀚归悩鑸碘偓渚€鏁撻弬銈嗗SCLK娑撴椽鏁撻柊鐢殿暜閹峰嘲閽� 1 闁跨喐鏋婚幏鐑芥晸閺傘倖瀚归悩鑸碘偓渚€鏁撻弬銈嗗SCLK娑撴椽鏁撶粩顓狀暜閹峰嘲閽� +#define SPI_CTRL_CPOL_Pos 9 //0 空闲状态下SCLK为低电平 1 空闲状态下SCLK为高电平 #define SPI_CTRL_CPOL_Msk (0x01 << SPI_CTRL_CPOL_Pos) #define SPI_CTRL_FFS_Pos 10 //Frame Format Select, 0 SPI 1 TI SSI 2 SPI 3 SPI #define SPI_CTRL_FFS_Msk (0x03 << SPI_CTRL_FFS_Pos) -#define SPI_CTRL_MSTR_Pos 12 //Master, 1 闁跨喐鏋婚幏閿嬆佸锟� 0 闁跨喐鏋婚幏閿嬆佸锟� +#define SPI_CTRL_MSTR_Pos 12 //Master, 1 主模式 0 从模式 #define SPI_CTRL_MSTR_Msk (0x01 << SPI_CTRL_MSTR_Pos) -#define SPI_CTRL_FAST_Pos 13 //1 SPI闁跨喐鏋婚幏鐑芥晸閺傘倖瀚归弮鍫曟晸閺傘倖瀚� = SYS_Freq/2 0 SPI闁跨喐鏋婚幏鐑芥晸閺傘倖瀚归弮鍫曟晸閺傘倖瀚归柨鐔告灮閹风ùPI->CTRL.CLKDIV闁跨喐鏋婚幏鐑芥晸閺傘倖瀚� +#define SPI_CTRL_FAST_Pos 13 //1 SPI工作时钟 = SYS_Freq/2 0 SPI工作时钟由SPI->CTRL.CLKDIV设置 #define SPI_CTRL_FAST_Msk (0x01 << SPI_CTRL_FAST_Pos) -#define SPI_CTRL_FILTE_Pos 16 //1 闁跨喐鏋婚幏绋碢I闁跨喐鏋婚幏鐑芥晸閺傘倖瀚归柨鐔诲壖閸欓攱鏋婚幏鐑芥晸閺傘倖瀚归崢濠氭晸閺傘倖瀚归柨鐔告灮閹风兘鏁撻弬銈嗗 0 闁跨喐鏋婚幏绋碢I闁跨喐鏋婚幏鐑芥晸閺傘倖瀚归柨鐔诲壖閸欑柉顕滈幏鐑芥晸閺傘倖瀚归柨鐔告灮閹峰嘲骞撻柨鐔告灮閹风兘鏁撻弬銈嗗闁跨喐鏋婚幏锟� +#define SPI_CTRL_FILTE_Pos 16 //1 对SPI输入信号进行去抖操作 0 对SPI输入信号不进行去抖操作 #define SPI_CTRL_FILTE_Msk (0x01 << SPI_CTRL_FILTE_Pos) -#define SPI_CTRL_SSN_H_Pos 17 //0 闁跨喐鏋婚幏鐑芥晸閺傘倖瀚归柨鐔告灮閹风兘鏁撻弬銈嗗闁跨喓绁砈N婵鏁撻弬銈嗗娑擄拷0 1 闁跨喐鏋婚幏鐑芥晸閺傘倖瀚归柨鐔告灮閹风兘鏁撻弬銈嗗闁跨喓鐓崠鈩冨閸р偓闁跨喕顢滈鍡樺闁跨喓绮ㄧ亸鍝燬N闁跨喐鏋婚幏鐑芥晸缁旑厼搴滈幏鐑芥晸缁插LK闁跨喐鏋婚幏鐑芥晸閺傘倖瀚� +#define SPI_CTRL_SSN_H_Pos 17 //0 传输过程中SSN始终为0 1 传输过程中每字符之间会将SSN拉高半个SCLK周期 #define SPI_CTRL_SSN_H_Msk (0x01 << SPI_CTRL_SSN_H_Pos) #define SPI_CTRL_TFCLR_Pos 24 //TX FIFO Clear #define SPI_CTRL_TFCLR_Msk (0x01 << SPI_CTRL_TFCLR_Pos) #define SPI_CTRL_RFCLR_Pos 25 //RX FIFO Clear #define SPI_CTRL_RFCLR_Msk (0x01 << SPI_CTRL_RFCLR_Pos) -#define SPI_STAT_WTC_Pos 0 //Word Transmit Complete闁跨喐鏋婚幏閿嬬槨闁跨喐鏋婚幏鐑芥晸閺傘倖瀚归柨鐔告灮閹风兘鏁撻幓顓濈串閹风兘鏁撻弬銈嗗闁跨喐鏋婚幏鐑芥晸閺傘倖瀚归柨鐔告灮閹风兘鏁撻幒銉嚋閹风兘鏁撻弬銈嗗闁跨噦鎷�1闁跨喐鏋婚幏鐑芥晸閺傘倖瀚归柨鐔峰建閿燂拷1闁跨喐鏋婚幏鐑芥晸閺傘倖瀚� +#define SPI_STAT_WTC_Pos 0 //Word Transmit Complete，每传输完成一个数据字由硬件置1，软件写1清零 #define SPI_STAT_WTC_Msk (0x01 << SPI_STAT_WTC_Pos) -#define SPI_STAT_TFE_Pos 1 //闁跨喐鏋婚幏鐑芥晸閺傘倖瀚笷IFO Empty +#define SPI_STAT_TFE_Pos 1 //发送FIFO Empty #define SPI_STAT_TFE_Msk (0x01 << SPI_STAT_TFE_Pos) -#define SPI_STAT_TFNF_Pos 2 //闁跨喐鏋婚幏鐑芥晸閺傘倖瀚笷IFO Not Full +#define SPI_STAT_TFNF_Pos 2 //发送FIFO Not Full #define SPI_STAT_TFNF_Msk (0x01 << SPI_STAT_TFNF_Pos) -#define SPI_STAT_RFNE_Pos 3 //闁跨喐鏋婚幏鐑芥晸閺傘倖瀚笷IFO Not Empty +#define SPI_STAT_RFNE_Pos 3 //接收FIFO Not Empty #define SPI_STAT_RFNE_Msk (0x01 << SPI_STAT_RFNE_Pos) -#define SPI_STAT_RFF_Pos 4 //闁跨喐鏋婚幏鐑芥晸閺傘倖瀚笷IFO Full +#define SPI_STAT_RFF_Pos 4 //接收FIFO Full #define SPI_STAT_RFF_Msk (0x01 << SPI_STAT_RFF_Pos) -#define SPI_STAT_RFOVF_Pos 5 //闁跨喐鏋婚幏鐑芥晸閺傘倖瀚笷IFO Overflow +#define SPI_STAT_RFOVF_Pos 5 //接收FIFO Overflow #define SPI_STAT_RFOVF_Msk (0x01 << SPI_STAT_RFOVF_Pos) -#define SPI_STAT_TFLVL_Pos 6 //闁跨喐鏋婚幏鐑芥晸閺傘倖瀚笷IFO闁跨喐鏋婚幏鐑芥晸閺傘倖瀚归柨鐔稿祹闂堚晜瀚归柨鐔告灮閹风兘鏁撻弬銈嗗 0 TFNF=0閺冨爼鏁撻弬銈嗗缁€绡嶪FO闁跨喐鏋婚幏鐑芥晸閺傘倖瀚�8闁跨喐鏋婚幏鐑芥晸閺傘倖瀚归柨鐔稿祹閿濆繑瀚筎FNF=1閺冨爼鏁撻弬銈嗗缁€绡嶪FO闁跨喐鏋婚幏鐑芥晸閺傘倖瀚�0闁跨喐鏋婚幏鐑芥晸閺傘倖瀚归柨鐔告灮閹凤拷 1--7 FIFO闁跨喐鏋婚幏鐑芥晸閺傘倖瀚�1--7闁跨喐鏋婚幏鐑芥晸閺傘倖瀚归柨鐔告灮閹凤拷 +#define SPI_STAT_TFLVL_Pos 6 //发送FIFO中数据个数， 0 TFNF=0时表示FIFO内有8个数据，TFNF=1时表示FIFO内有0个数据 1--7 FIFO内有1--7个数据 #define SPI_STAT_TFLVL_Msk (0x07 << SPI_STAT_TFLVL_Pos) -#define SPI_STAT_RFLVL_Pos 9 //闁跨喐鏋婚幏鐑芥晸閺傘倖瀚笷IFO闁跨喐鏋婚幏鐑芥晸閺傘倖瀚归柨鐔稿祹闂堚晜瀚归柨鐔告灮閹风兘鏁撻弬銈嗗 0 RFF=1閺冨爼鏁撻弬銈嗗缁€绡嶪FO闁跨喐鏋婚幏鐑芥晸閺傘倖瀚�8闁跨喐鏋婚幏鐑芥晸閺傘倖瀚归柨鐔稿祹閿濆繑瀚� RFF=0閺冨爼鏁撻弬銈嗗缁€绡嶪FO闁跨喐鏋婚幏鐑芥晸閺傘倖瀚�0闁跨喐鏋婚幏鐑芥晸閺傘倖瀚归柨鐔告灮閹凤拷 1--7 FIFO闁跨喐鏋婚幏鐑芥晸閺傘倖瀚�1--7闁跨喐鏋婚幏鐑芥晸閺傘倖瀚归柨鐔告灮閹凤拷 +#define SPI_STAT_RFLVL_Pos 9 //接收FIFO中数据个数， 0 RFF=1时表示FIFO内有8个数据， RFF=0时表示FIFO内有0个数据 1--7 FIFO内有1--7个数据 #define SPI_STAT_RFLVL_Msk (0x07 << SPI_STAT_RFLVL_Pos) #define SPI_STAT_BUSY_Pos 15 #define SPI_STAT_BUSY_Msk (0x01 << SPI_STAT_BUSY_Pos) @@ -862,7 +1467,7 @@ typedef struct #define SPI_IE_FTC_Pos 9 //Frame Transmit Complete #define SPI_IE_FTC_Msk (0x01 << SPI_IE_FTC_Pos) -#define SPI_IF_RFOVF_Pos 0 //閸愶拷1闁跨喐鏋婚幏鐑芥晸閺傘倖瀚� +#define SPI_IF_RFOVF_Pos 0 //写1清零 #define SPI_IF_RFOVF_Msk (0x01 << SPI_IF_RFOVF_Pos) #define SPI_IF_RFF_Pos 1 #define SPI_IF_RFF_Msk (0x01 << SPI_IF_RFF_Pos) @@ -872,14 +1477,14 @@ typedef struct #define SPI_IF_TFE_Msk (0x01 << SPI_IF_TFE_Pos) #define SPI_IF_TFHF_Pos 4 #define SPI_IF_TFHF_Msk (0x01 << SPI_IF_TFHF_Pos) -#define SPI_IF_WTC_Pos 8 //Word Transmit Complete闁跨喐鏋婚幏閿嬬槨闁跨喐鏋婚幏鐑芥晸閺傘倖瀚归柨鐔告灮閹风兘鏁撻幓顓濈串閹风兘鏁撻弬銈嗗闁跨喐鏋婚幏鐑芥晸閺傘倖瀚归柨鐔告灮閹风兘鏁撻幒銉嚋閹风兘鏁撻弬銈嗗闁跨噦鎷�1 +#define SPI_IF_WTC_Pos 8 //Word Transmit Complete，每传输完成一个数据字由硬件置1 #define SPI_IF_WTC_Msk (0x01 << SPI_IF_WTC_Pos) -#define SPI_IF_FTC_Pos 9 //Frame Transmit Complete闁跨喐鏋婚幏绋篢C闁跨喐鏋婚幏铚傜秴閺冨爼鏁撻弬銈嗗TX FIFO闁跨喕顫楃粚铏规畱閿濆繑瀚归柨鐔告灮閹风éTC闁跨喐鏋婚幏铚傜秴 +#define SPI_IF_FTC_Pos 9 //Frame Transmit Complete，WTC置位时若TX FIFO是空的，则FTC置位 #define SPI_IF_FTC_Msk (0x01 << SPI_IF_FTC_Pos) typedef struct { - __IO uint32_t CLKDIV; //[15:0] 闁跨喕顕犵亸鍡涙晸閼哄倽顕滈幏鐑芥晸閺傘倖瀚归柨鐔告灮閹风兘顣堕柨鐔虹哺閸掑棛顣幏绋碈L妫版垿鏁撶紒鐐殿暜閹凤拷5闁跨喐鏋婚幏鐑芥晸閺傘倖瀚归柨鐔告灮閹风áLKDIV = SYS_Freq/5/SCL_Freq - 1 + __IO uint32_t CLKDIV; //[15:0] 须将内部工作频率分到SCL频率的5倍，即CLKDIV = SYS_Freq/5/SCL_Freq - 1 __IO uint32_t CTRL; @@ -901,61 +1506,61 @@ typedef struct #define I2C_CTRL_EN_Pos 7 #define I2C_CTRL_EN_Msk (0x01 << I2C_CTRL_EN_Pos) -#define I2C_MSTCMD_IF_Pos 0 //1 闁跨喎褰ㄧ粵澶庢彧閹风兘鏁撻弬銈嗗闁跨喐鏋婚幏鐑芥晸閺傘倖瀚归崡绋跨瑖闁跨喎褰ㄩ敓锟�1闁跨喐鏋婚幏鐑芥晸閺傘倖瀚� 闁跨喐鏋婚幏鐑芥晸閺傘倖瀚归柨鐔告灮閹风兘鏁撻弬銈嗗闁跨喐鏋婚幏鐑界氨闁跨喕濞囬幐銉嚋閹风兘鏁撻弬銈嗗闁跨喕濞囨导娆愬闁跨噦鎷�1闁跨喐鏋婚幏铚傜闁跨喐鏋婚幏鐑芥晸鐞涙濡潏鐐闁跨喐鏋婚幏鐑芥晸閺傘倖瀚归柨鐕傛嫹 2闁跨喐鏋婚幏鐑芥晸閺傘倖瀚归柨鐔侯仾閸戙倖瀚归柨鐔告灮閹烽攱娼堥柨鐔告灮閹峰嘲銇� +#define I2C_MSTCMD_IF_Pos 0 //1 有等待处理的中断，写1清零 有两种情况下此位硬件置位：1、一个字节传输完成 2、总线访问权丢失 #define I2C_MSTCMD_IF_Msk (0x01 << I2C_MSTCMD_IF_Pos) #define I2C_MSTCMD_TIP_Pos 1 //Transmission In Process #define I2C_MSTCMD_TIP_Msk (0x01 << I2C_MSTCMD_TIP_Pos) -#define I2C_MSTCMD_ACK_Pos 3 //闁跨喐鏋婚幏鐑芥晸閺傘倖瀚瑰Ο鈥崇础闁跨喖鎽敐蹇斿0 闁跨喐鏋婚幏鐑芥晸闁扮數顏崙銈嗗闁跨喐鏋婚幏绋烠K 1 闁跨喐鏋婚幏鐑芥晸闁扮數顏崙銈嗗闁跨喐鏋婚幏绋瓵CK +#define I2C_MSTCMD_ACK_Pos 3 //接收模式下，0 向发送端反馈ACK 1 向发送端反馈NACK #define I2C_MSTCMD_ACK_Msk (0x01 << I2C_MSTCMD_ACK_Pos) -#define I2C_MSTCMD_WR_Pos 4 // 闁跨喐鏋婚幏绋磍ave閸愭瑩鏁撻弬銈嗗闁跨喐鏋婚幏閿嬫闁跨喐鏋婚幏鐑芥晸閺傘倖瀚归柨鐔告灮閹疯渹绔存担宥呭晸1闁跨喐鏋婚幏鐑芥晸閻ㄥ棜顔愰幏鐑芥晸閺傘倖瀚归柨鐔告灮閹凤拷 +#define I2C_MSTCMD_WR_Pos 4 // 向Slave写数据时，把这一位写1，自动清零 #define I2C_MSTCMD_WR_Msk (0x01 << I2C_MSTCMD_WR_Pos) -#define I2C_MSTCMD_RD_Pos 5 //閸愭瑩鏁撻弬銈嗗闁跨喐鏋婚幏绋磍ave闁跨喐鏋婚幏鐑芥晸閺傘倖瀚归柨鐔告灮閹烽攱妞傞柨鐔告灮閹风兘鏁撻弬銈嗗闁跨喐鏋婚幏铚傜娴ｅ秴鍟�1闁跨喐鏋婚幏鐑芥晸閻ㄥ棜顔愰幏鐑芥晸閺傘倖瀚归柨鐔告灮閹凤拷 闁跨喐鏋婚幏鐑芥晸閺傘倖瀚归柨鐔告灮閹风ī2C濡繝鏁撻弬銈嗗婢跺崬骞撻柨鐔告灮閹风兘鏁撶粩顓犳畱閸戙倖瀚归柨鐔告灮閹烽攱娼堥弮鍓佲€栭柨鐔告灮閹风兘鏁撻弬銈嗗1 +#define I2C_MSTCMD_RD_Pos 5 //写：从Slave读数据时，把这一位写1，自动清零 读：当I2C模块失去总线的访问权时硬件置1 #define I2C_MSTCMD_RD_Msk (0x01 << I2C_MSTCMD_RD_Pos) -#define I2C_MSTCMD_BUSY_Pos 6 //闁跨喐鏋婚幏鐑芥晸閺傘倖瀚归柨鐔告灮閹风兘鏁撻弬銈嗗閻涘墽绁砊ART娑斿鏁撻弬銈嗗闁跨喐鏋婚幏铚傜娴ｅ秹鏁撻弬銈嗗1闁跨喐鏋婚幏鐑芥晸閺傘倖瀚归柨鐔告灮閹烽宓曠徊濂P娑斿鏁撻弬銈嗗闁跨喐鏋婚幏铚傜娴ｅ秹鏁撻弬銈嗗0 +#define I2C_MSTCMD_BUSY_Pos 6 //读：当检测到START之后，这一位变1；当检测到STOP之后，这一位变0 #define I2C_MSTCMD_BUSY_Msk (0x01 << I2C_MSTCMD_BUSY_Pos) -#define I2C_MSTCMD_STO_Pos 6 //閸愭瑩鏁撻弬銈嗗闁跨喐鏋婚幏鐑芥晸閺傘倖瀚筍TOP闁跨喐鏋婚幏鐑芥晸閻ㄥ棜顔愰幏鐑芥晸閺傘倖瀚归柨鐔告灮閹凤拷 +#define I2C_MSTCMD_STO_Pos 6 //写：产生STOP，自动清零 #define I2C_MSTCMD_STO_Msk (0x01 << I2C_MSTCMD_STO_Pos) -#define I2C_MSTCMD_RXACK_Pos 7 //闁跨喐鏋婚幏鐑芥晸閺傘倖瀚归柨鐔告灮閹风兘鏁撶粔鍝ヮ暜閹风兘鏁撻弬銈嗗Slave闁跨喐鏋婚幏绋烠K娴ｅ秹鏁撻弬銈嗗0 闁跨喓笑绾板瀚笰CK 1 闁跨喓笑绾板瀚筃ACK +#define I2C_MSTCMD_RXACK_Pos 7 //读：接收到的Slave的ACK位，0 收到ACK 1 收到NACK #define I2C_MSTCMD_RXACK_Msk (0x01 << I2C_MSTCMD_RXACK_Pos) -#define I2C_MSTCMD_STA_Pos 7 //閸愭瑩鏁撻弬銈嗗闁跨喐鏋婚幏鐑芥晸閺傘倖瀚筍TART闁跨喐鏋婚幏鐑芥晸閻ㄥ棜顔愰幏鐑芥晸閺傘倖瀚归柨鐔告灮閹凤拷 +#define I2C_MSTCMD_STA_Pos 7 //写：产生START，自动清零 #define I2C_MSTCMD_STA_Msk (0x01 << I2C_MSTCMD_STA_Pos) -#define I2C_SLVCR_IM_RXEND_Pos 0 //闁跨喐鏋婚幏鐑芥晸閺傘倖瀚归柨鐔告灮閹风兘鏁撻弬銈嗗閸楁瓕绶伴柨鐔活敎閿燂拷 +#define I2C_SLVCR_IM_RXEND_Pos 0 //接收完成中断禁止 #define I2C_SLVCR_IM_RXEND_Msk (0x01 << I2C_SLVCR_IM_RXEND_Pos) -#define I2C_SLVCR_IM_TXEND_Pos 1 //闁跨喐鏋婚幏鐑芥晸閺傘倖瀚归柨鐔告灮閹风兘鏁撻弬銈嗗閸楁瓕绶伴柨鐔活敎閿燂拷 +#define I2C_SLVCR_IM_TXEND_Pos 1 //发送完成中断禁止 #define I2C_SLVCR_IM_TXEND_Msk (0x01 << I2C_SLVCR_IM_TXEND_Pos) -#define I2C_SLVCR_IM_STADET_Pos 2 //闁跨喐鏋婚幏椋庡禃閺傘倖瀚归柨鐔虹哺绾攱瀚归崡姝岀钒闁跨喕顢滈敓锟� +#define I2C_SLVCR_IM_STADET_Pos 2 //检测到起始中断禁止 #define I2C_SLVCR_IM_STADET_Msk (0x01 << I2C_SLVCR_IM_STADET_Pos) -#define I2C_SLVCR_IM_STODET_Pos 3 //闁跨喐鏋婚幏椋庡禃闁扮绾ч惂鍛婂閸楁瓕绶伴柨鐔活敎閿燂拷 +#define I2C_SLVCR_IM_STODET_Pos 3 //检测到停止中断禁止 #define I2C_SLVCR_IM_STODET_Msk (0x01 << I2C_SLVCR_IM_STODET_Pos) -#define I2C_SLVCR_IM_RDREQ_Pos 4 //闁跨喐鏋婚幏鐑芥晸缁夊摜顣幏鐑芥晸閺傘倖瀚归柨鐔告灮閹风兘鏁撻弬銈嗗闁跨喎褰ㄩ弬顓熸灮閹烽攱顒� +#define I2C_SLVCR_IM_RDREQ_Pos 4 //接收到读请求中断禁止 #define I2C_SLVCR_IM_RDREQ_Msk (0x01 << I2C_SLVCR_IM_RDREQ_Pos) -#define I2C_SLVCR_IM_WRREQ_Pos 5 //闁跨喐鏋婚幏鐑芥晸缁夊摜顣幏宄板晸闁跨喐鏋婚幏鐑芥晸閺傘倖瀚归柨鐔峰建閺傤厽鏋婚幏閿嬵剾 +#define I2C_SLVCR_IM_WRREQ_Pos 5 //接收到写请求中断禁止 #define I2C_SLVCR_IM_WRREQ_Msk (0x01 << I2C_SLVCR_IM_WRREQ_Pos) -#define I2C_SLVCR_ADDR7b_Pos 16 //1 7娴ｅ秹鏁撻弬銈嗗閸р偓濡€崇础 0 10娴ｅ秹鏁撻弬銈嗗閸р偓濡€崇础 +#define I2C_SLVCR_ADDR7b_Pos 16 //1 7位地址模式 0 10位地址模式 #define I2C_SLVCR_ADDR7b_Msk (0x01 << I2C_SLVCR_ADDR7b_Pos) -#define I2C_SLVCR_ACK_Pos 17 //1 鎼存棃鏁撻弬銈嗗ACK 0 鎼存棃鏁撻弬銈嗗NACK +#define I2C_SLVCR_ACK_Pos 17 //1 应答ACK 0 应答NACK #define I2C_SLVCR_ACK_Msk (0x01 << I2C_SLVCR_ACK_Pos) -#define I2C_SLVCR_SLAVE_Pos 18 //1 闁跨喐甯存导娆愬濡€崇础 0 闁跨喐鏋婚幏鐑芥晸閺傘倖瀚瑰Ο鈥崇础 +#define I2C_SLVCR_SLAVE_Pos 18 //1 从机模式 0 主机模式 #define I2C_SLVCR_SLAVE_Msk (0x01 << I2C_SLVCR_SLAVE_Pos) -#define I2C_SLVCR_DEBOUNCE_Pos 19 //閸樺鏁撻弬銈嗗闁跨喐鏋婚幏铚傚▏闁跨喐鏋婚幏锟� +#define I2C_SLVCR_DEBOUNCE_Pos 19 //去抖动使能 #define I2C_SLVCR_DEBOUNCE_Msk (0x01 << I2C_SLVCR_DEBOUNCE_Pos) -#define I2C_SLVCR_ADDR_Pos 20 //闁跨喐甯存导娆愬闁跨喐鏋婚幏宄版絻 +#define I2C_SLVCR_ADDR_Pos 20 //从机地址 #define I2C_SLVCR_ADDR_Msk (0x3FF << I2C_SLVCR_ADDR_Pos) -#define I2C_SLVIF_RXEND_Pos 0 //闁跨喐鏋婚幏鐑芥晸閺傘倖瀚归柨鐔告灮閹风兘鏁撻弬銈嗗閸楃ǹ顎掗柨鐔活敎閹惧懏瀚归柨鐔峰建閿燂拷1闁跨喐鏋婚幏鐑芥晸閺傘倖瀚� +#define I2C_SLVIF_RXEND_Pos 0 //接收完成中断标志，写1清零 #define I2C_SLVIF_RXEND_Msk (0x01 << I2C_SLVIF_RXEND_Pos) -#define I2C_SLVIF_TXEND_Pos 1 //闁跨喐鏋婚幏鐑芥晸閺傘倖瀚归柨鐔告灮閹风兘鏁撻弬銈嗗閸楃ǹ顎掗柨鐔活敎閹惧懏瀚归柨鐔峰建閿燂拷1闁跨喐鏋婚幏鐑芥晸閺傘倖瀚� +#define I2C_SLVIF_TXEND_Pos 1 //发送完成中断标志，写1清零 #define I2C_SLVIF_TXEND_Msk (0x01 << I2C_SLVIF_TXEND_Pos) -#define I2C_SLVIF_STADET_Pos 2 //闁跨喐鏋婚幏椋庡禃閺傘倖瀚归柨鐔虹哺绾攱瀚归崡绋款€掗柨鐔活敎閹惧懏瀚归柨鐔峰建閿燂拷1闁跨喐鏋婚幏鐑芥晸閺傘倖瀚� +#define I2C_SLVIF_STADET_Pos 2 //检测到起始中断标志，写1清零 #define I2C_SLVIF_STADET_Msk (0x01 << I2C_SLVIF_STADET_Pos) -#define I2C_SLVIF_STODET_Pos 3 //闁跨喐鏋婚幏椋庡禃闁扮绾ч惂鍛婂閸楃ǹ顎掗柨鐔活敎閹惧懏瀚归柨鐔峰建閿燂拷1闁跨喐鏋婚幏鐑芥晸閺傘倖瀚� +#define I2C_SLVIF_STODET_Pos 3 //检测到停止中断标志，写1清零 #define I2C_SLVIF_STODET_Msk (0x01 << I2C_SLVIF_STODET_Pos) -#define I2C_SLVIF_RDREQ_Pos 4 //闁跨喐鏋婚幏鐑芥晸缁夊摜顣幏鐑芥晸閺傘倖瀚归柨鐔告灮閹风兘鏁撻弬銈嗗闁跨喎褰ㄩ弬顓熷敾閹峰嘲绻� +#define I2C_SLVIF_RDREQ_Pos 4 //接收到读请求中断标志 #define I2C_SLVIF_RDREQ_Msk (0x01 << I2C_SLVIF_RDREQ_Pos) -#define I2C_SLVIF_WRREQ_Pos 5 //闁跨喐鏋婚幏鐑芥晸缁夊摜顣幏宄板晸闁跨喐鏋婚幏鐑芥晸閺傘倖瀚归柨鐔峰建閺傤厽鍞婚幏宄扮箶 +#define I2C_SLVIF_WRREQ_Pos 5 //接收到写请求中断标志 #define I2C_SLVIF_WRREQ_Msk (0x01 << I2C_SLVIF_WRREQ_Pos) -#define I2C_SLVIF_ACTIVE_Pos 6 //slave 闁跨喐鏋婚幏閿嬫櫏 +#define I2C_SLVIF_ACTIVE_Pos 6 //slave 有效 #define I2C_SLVIF_ACTIVE_Msk (0x01 << I2C_SLVIF_ACTIVE_Pos) typedef struct @@ -988,7 +1593,7 @@ typedef struct __IO uint32_t CALIBEN; } ADC_TypeDef; -#define ADC_CTRL_CH0_Pos 0 //闁岸鏁撻弬銈嗗闁鏁撻弬銈嗗 +#define ADC_CTRL_CH0_Pos 0 //通道选中 #define ADC_CTRL_CH0_Msk (0x01 << ADC_CTRL_CH0_Pos) #define ADC_CTRL_CH1_Pos 1 #define ADC_CTRL_CH1_Msk (0x01 << ADC_CTRL_CH1_Pos) @@ -1004,20 +1609,20 @@ typedef struct #define ADC_CTRL_CH6_Msk (0x01 << ADC_CTRL_CH6_Pos) #define ADC_CTRL_CH7_Pos 7 #define ADC_CTRL_CH7_Msk (0x01 << ADC_CTRL_CH7_Pos) -#define ADC_CTRL_AVG_Pos 8 //0 1闁跨喕濞囩拠褎瀚归柨鐔告灮閹凤拷 1 2闁跨喕濞囩拠褎瀚归柨鐔告灮閹峰嘲褰囬獮鎶芥晸閺傘倖瀚归崐锟� 3 4闁跨喕濞囩拠褎瀚归柨鐔告灮閹峰嘲褰囬獮鎶芥晸閺傘倖瀚归崐锟� 7 8闁跨喕濞囩拠褎瀚归柨鐔告灮閹峰嘲褰囬獮鎶芥晸閺傘倖瀚归崐锟� 15 16闁跨喕濞囩拠褎瀚归柨鐔告灮閹峰嘲褰囬獮鎶芥晸閺傘倖瀚归崐锟� +#define ADC_CTRL_AVG_Pos 8 //0 1次采样 1 2次采样取平均值 3 4次采样取平均值 7 8次采样取平均值 15 16次采样取平均值 #define ADC_CTRL_AVG_Msk (0x0F << ADC_CTRL_AVG_Pos) #define ADC_CTRL_EN_Pos 12 #define ADC_CTRL_EN_Msk (0x01 << ADC_CTRL_EN_Pos) -#define ADC_CTRL_CONT_Pos 13 //Continuous conversion闁跨喐鏋婚幏宄板涧闁跨喐鏋婚幏鐑芥晸閺傘倖瀚归柨鐔告灮閹风兘鏁撴笟銉悏閺傘倖瀚归柨鐔告灮閹风兘鏁撻崣顐庡秵瀚归柨鐕傛嫹0 闁跨喐鏋婚幏鐑芥晸閺傘倖瀚规潪顒勬晸閺傘倖瀚归柨鐔告灮閹风柉娴嗛柨鐔告灮閹风兘鏁撻弬銈嗗閻濆﹪鏁撶徊濂RT娴ｅ秹鏁撻惃鍡氼啇閹风兘鏁撻弬銈嗗闁跨喖鍙洪敍鑸碉細椤忓孩瀚归柨鐕傛嫹 -#define ADC_CTRL_CONT_Msk (0x01 << ADC_CTRL_CONT_Pos) // 1 闁跨喐鏋婚幏鐑芥晸閺傘倖瀚规潪顒勬晸閺傘倖瀚归柨鐔告灮閹风兘鏁撻弬銈嗗闁跨喐褰幁銏″敾閹风兘鏁撻弬銈嗗闁跨喐鏋婚幏鐑芥晸闂冮浜烽幏鐑芥晸閺傘倖瀚归柨鐔活敎閹插瀚归柨鐔告灮閹风兘鏁撻弬銈嗗闁跨喐鏋婚幏鐑芥晸缁插ィART娴ｏ拷 -#define ADC_CTRL_TRIG_Pos 14 //鏉烆剟鏁撻弬銈嗗闁跨喐鏋婚幏鐑芥晸閺傘倖瀚归柨鐔告灮閹峰嘲绱￠柨鐔告灮閹凤拷0 闁跨喐鏋婚幏鐑芥晸閺傘倖瀚归柨鐔兼▉椤忓孩瀚归柨鐕傛嫹 1 PWM闁跨喐鏋婚幏鐑芥晸閺傘倖瀚� +#define ADC_CTRL_CONT_Pos 13 //Continuous conversion，只在软件启动模式下有效，0 单次转换，转换完成后START位自动清除停止转换 +#define ADC_CTRL_CONT_Msk (0x01 << ADC_CTRL_CONT_Pos) // 1 连续转换，启动后一直采样、转换，直到软件清除START位 +#define ADC_CTRL_TRIG_Pos 14 //转换触发方式：0 软件启动转换 1 PWM触发 #define ADC_CTRL_TRIG_Msk (0x01 << ADC_CTRL_TRIG_Pos) #define ADC_CTRL_CLKSRC_Pos 15 //0 VCO 1 HRC #define ADC_CTRL_CLKSRC_Msk (0x01 << ADC_CTRL_CLKSRC_Pos) #define ADC_CTRL_FIFOCLR_Pos 24 //[24] CH0_FIFO_CLR [25] CH1_FIFO_CLR ... [31] CH7_FIFO_CLR -#define ADC_CTRL_FIFOCLR_Msk (((uint32_t)0xFF) << ADC_CTRL_FIFOCLR_Pos) +#define ADC_CTRL_FIFOCLR_Msk (0xFFu << ADC_CTRL_FIFOCLR_Pos) -#define ADC_START_GO_Pos 0 //闁跨喐鏋婚幏鐑芥晸閺傘倖瀚归柨鐔告灮閹风兘鏁撴笟銉悏閺傘倖瀚归幏銏ゆ晸閸欘偓鎷�1闁跨喐鏋婚幏绋烡C闁跨喐鏋婚幏鐑芥晸閺傘倖瀚归柨鐔告灮閹风柉娴嗛柨鐔告灮閹风兘鏁撻弬銈嗗闁跨喕濡喊澶嬪闁跨喐鏋婚幏閿嬆佸蹇涙晸閺傘倖瀚规潪顒勬晸閺傘倖瀚归柨鐔告灮閹烽寮烽柨鐔稿复鐠囇勫闁跨喐鏋婚幏鐤箼闁跨喐鏋婚幏鐑芥晸閺傘倖瀚归幃鏍村墾閹风兘鏁撶紓鎼厜閹风兘鏁撴笟銉悏閺傘倖瀚归崡銈夋晸閺傘倖瀚归柨鐔告灮閹风兘鏁撻弬銈嗗閸愶拷0閸嬫粍顒汚DC鏉烆剟鏁撻弬銈嗗 +#define ADC_START_GO_Pos 0 //软件触发模式下，写1启动ADC采样和转换，在单次模式下转换完成后硬件自动清零，在扫描模式下必须软件写0停止ADC转换 #define ADC_START_GO_Msk (0x01 << ADC_START_GO_Pos) #define ADC_START_BUSY_Pos 4 #define ADC_START_BUSY_Msk (0x01 << ADC_START_BUSY_Pos) @@ -1085,16 +1690,15 @@ typedef struct #define ADC_IE_CH7HFULL_Pos 30 #define ADC_IE_CH7HFULL_Msk (0x01 << ADC_IE_CH7HFULL_Pos) #define ADC_IE_CH7FULL_Pos 31 -//#define ADC_IE_CH7FULL_Msk (0x01 << ADC_IE_CH7FULL_Pos) 闁跨喐鏋婚幏鐑芥晸閺傘倖瀚归柨鐔告灮閹风兘鏁撻弬銈嗗闁跨喕濮ら敍锟� integer operation result is out of range -#define ADC_IE_CH7FULL_Msk ((uint32_t)0x01 << ADC_IE_CH7FULL_Pos) +#define ADC_IE_CH7FULL_Msk (0x01u << ADC_IE_CH7FULL_Pos) -#define ADC_IF_CH0EOC_Pos 0 //閸愶拷1闁跨喐鏋婚幏鐑芥晸閺傘倖瀚� +#define ADC_IF_CH0EOC_Pos 0 //写1清零 #define ADC_IF_CH0EOC_Msk (0x01 << ADC_IF_CH0EOC_Pos) -#define ADC_IF_CH0OVF_Pos 1 //閸愶拷1闁跨喐鏋婚幏鐑芥晸閺傘倖瀚� +#define ADC_IF_CH0OVF_Pos 1 //写1清零 #define ADC_IF_CH0OVF_Msk (0x01 << ADC_IF_CH0OVF_Pos) -#define ADC_IF_CH0HFULL_Pos 2 //閸愶拷1闁跨喐鏋婚幏鐑芥晸閺傘倖瀚� +#define ADC_IF_CH0HFULL_Pos 2 //写1清零 #define ADC_IF_CH0HFULL_Msk (0x01 << ADC_IF_CH0HFULL_Pos) -#define ADC_IF_CH0FULL_Pos 3 //閸愶拷1闁跨喐鏋婚幏鐑芥晸閺傘倖瀚� +#define ADC_IF_CH0FULL_Pos 3 //写1清零 #define ADC_IF_CH0FULL_Msk (0x01 << ADC_IF_CH0FULL_Pos) #define ADC_IF_CH1EOC_Pos 4 #define ADC_IF_CH1EOC_Msk (0x01 << ADC_IF_CH1EOC_Pos) @@ -1153,9 +1757,9 @@ typedef struct #define ADC_IF_CH7FULL_Pos 31 #define ADC_IF_CH7FULL_Msk (0x01 << ADC_IF_CH7FULL_Pos) -#define ADC_STAT_EOC_Pos 0 //閸愶拷1闁跨喐鏋婚幏鐑芥晸閺傘倖瀚� +#define ADC_STAT_EOC_Pos 0 //写1清零 #define ADC_STAT_EOC_Msk (0x01 << ADC_STAT_EOC_Pos) -#define ADC_STAT_OVF_Pos 1 //闁跨喐鏋婚幏鐑芥晸閺傘倖瀚归柨鐔稿祹鐎靛嫯鎻幏鐑芥晸閺傘倖瀚归柨鐔告灮閹风兘鏁撻敓锟� +#define ADC_STAT_OVF_Pos 1 //读数据寄存器清除 #define ADC_STAT_OVF_Msk (0x01 << ADC_STAT_OVF_Pos) #define ADC_STAT_HFULL_Pos 2 #define ADC_STAT_HFULL_Msk (0x01 << ADC_STAT_HFULL_Pos) @@ -1164,23 +1768,23 @@ typedef struct #define ADC_STAT_EMPTY_Pos 4 #define ADC_STAT_EMPTY_Msk (0x01 << ADC_STAT_EMPTY_Pos) -#define ADC_CTRL1_RIN_Pos 4 //闁跨喐鏋婚幏鐑芥晸閺傘倖瀚归柨鐔封偓鐔稿闁跨喐鏋婚幏锟�0 闁跨喐鏋婚幏鐑芥晸閺傘倖瀚归柨鐕傛嫹 1 105K 2 90K 3 75K 4 60K 5 45K 6 30K 7 15K +#define ADC_CTRL1_RIN_Pos 4 //输入阻抗：0 无穷大 1 105K 2 90K 3 75K 4 60K 5 45K 6 30K 7 15K #define ADC_CTRL1_RIN_Msk (0x07 << ADC_CTRL1_RIN_Pos) -#define ADC_CTRL2_RESET_Pos 0 //闁跨喐鏋婚幏鐑芥晸鐞涙顣幏鐤熅闁跨喐鏋婚幏铚傜秴 +#define ADC_CTRL2_RESET_Pos 0 //数字电路复位 #define ADC_CTRL2_RESET_Msk (0x01 << ADC_CTRL2_RESET_Pos) -#define ADC_CTRL2_ADCEVCM_Pos 1 //ADC External VCM闁跨喐鏋婚幏绋烡C闁跨喐鏋婚幏绋癎A闁跨喐鏋婚幏鐑芥晸閺傘倖瀚归柨鐔惰寧閿濆繑瀚归柨鐔哄珱缁愭牑妲勯幏鐑芥晸閿燂拷 +#define ADC_CTRL2_ADCEVCM_Pos 1 //ADC External VCM，ADC与PGA输出共模电平选择 #define ADC_CTRL2_ADCEVCM_Msk (0x01 << ADC_CTRL2_ADCEVCM_Pos) -#define ADC_CTRL2_PGAIVCM_Pos 2 //PGA Internal VCM闁跨喐鏋婚幏绋癎A闁跨喐鏋婚幏鐑芥晸鐠囶偄鍙″Ο锟犳晸閺傘倖瀚归獮鎶解偓澶愭晸閺傘倖瀚� +#define ADC_CTRL2_PGAIVCM_Pos 2 //PGA Internal VCM，PGA输入共模电平选择 #define ADC_CTRL2_PGAIVCM_Msk (0x01 << ADC_CTRL2_PGAIVCM_Pos) #define ADC_CTRL2_PGAGAIN_Pos 3 //0 25.1dB 1 21.6dB 2 11.1dB 3 3.5dB 4 0dB(1.8V) 5 -2.9dB 6 -5.3dB #define ADC_CTRL2_PGAGAIN_Msk (0x07 << ADC_CTRL2_PGAGAIN_Pos) -#define ADC_CTRL2_REFPOUT_Pos 23 //1 ADC 闁跨喕濡拠褎瀚� 1.2V REFP闁跨喐鏋婚幏宄板竾闁跨喐鏋婚幏鐑芥晸閺傘倖瀚归柨鐔告灮閹烽宕扮缓宀碏P闁跨喐鏋婚幏鐑芥晸閼存熬缍囬幏鐑芥晸閺傘倖瀚归柨鐔诲Ν鐠囇勫闁跨喐鏋婚幏鐑芥晸閺傘倖瀚归柨鐔告灮閹风兘鏁撻弬銈嗗闁跨喐鏋婚幏鐤洣1.2V闁跨喕袙闁墽EFP閺冨爼鏁撻弬銈嗗閻線鏁撶紓瀛樺敾閹凤拷 +#define ADC_CTRL2_REFPOUT_Pos 23 //1 ADC 内部 1.2V REFP电压输出到外部REFP引脚，用于测量，或在需要1.2V外部REFP时节省成本 #define ADC_CTRL2_REFPOUT_Msk (0x01 << ADC_CTRL2_REFPOUT_Pos -#define ADC_CTRL2_CLKDIV_Pos 24 //閺冨爼鏁撻幒銉ュ殩閹风兘顣堕柨鐔告灮閹峰嘲褰ч柨鐔告灮閹烽攱妞傞柨鐔告灮閹烽攱绨稉绡怰C閺冨爼鏁撻弬銈嗗閺侊拷 +#define ADC_CTRL2_CLKDIV_Pos 24 //时钟分频，只在时钟源为HRC时有效 #define ADC_CTRL2_CLKDIV_Msk (0x1F << ADC_CTRL2_CLKDIV_Pos) #define ADC_CTRL2_PGAVCM_Pos 29 -#define ADC_CTRL2_PGAVCM_Msk (((uint32_t)0x07) << ADC_CTRL2_PGAVCM_Pos) +#define ADC_CTRL2_PGAVCM_Msk (0x07u << ADC_CTRL2_PGAVCM_Pos) #define ADC_CALIBSET_OFFSET_Pos 0 #define ADC_CALIBSET_OFFSET_Msk (0x1FF << ADC_CALIBSET_OFFSET_Pos) @@ -1194,17 +1798,17 @@ typedef struct typedef struct { - __IO uint32_t MODE; //0 闁跨喐鏋婚幏鐑解偓姘佸蹇涙晸閺傘倖瀚笰闁跨喐鏋婚幏绋￠柨鐔告灮閹风柉鐭鹃柨鐔告灮閹风兘鏁撻弬銈嗗闁跨喐鏋婚幏鐑芥晸閺傘倖瀚归柨鐔告灮閹凤拷 - //1 闁跨喐鏋婚幏鐑芥晸閺傘倖瀚瑰Ο鈥崇础闁跨喐鏋婚幏绋熼柨鐔告灮閹风ā闁跨喐鏋婚幏鐤熅闁跨喐鏋婚幏鐑芥晸閺傘倖瀚归柨鐔告灮閹风兘鏁撶徊鍢怰A闁跨喐鏋婚幏绋↖GHA闁跨喐鏋婚幏鐑芥晸閻欌槄缍囬幏绋＄捄顖炴晸閺傘倖瀚归柨鐔告灮閹风兘鏁撶槐姝岀熅闁跨喐鏋婚幏鐑芥晸閺傘倖瀚归柨鐔告灮閹风兘鏁撻弬銈嗗閸犳崘鎻幏鐑芥晸閺傘倖瀚归柨鐔烘たZA闁跨喐鏋婚幏绋B闁跨喐鏋婚幏鐑芥晸閺傘倖瀚笰闁跨喐鏋婚幏绋＄捄顖炴晸閺傘倖瀚归柨鐔告灮閹风兘鏁撻弬銈嗗闁跨喐鏋婚幏鐑芥晸閺傘倖瀚归惉銉╂晸缂佺偞鍞婚幏鐑芥晸閿燂拷 - //2 闁跨喐鏋婚幏鐑芥晸閺傘倖瀚瑰Ο鈥崇础闁跨喐鏋婚幏宄版倱闁跨喐鏋婚幏鐑解偓姘佸蹇涙晸閺傘倖瀚归柨鐔告灮閹疯渹绔撮柨鐔告灮閹风兘鏁撻弬銈嗗闁跨喕濡悮瀛樺闁跨喓娈曠拋瑙勫閸嬫粍顒� - //3 闁跨喓娈曠粵瑙勫濡€崇础闁跨喐鏋婚幏绋熼柨鐔告灮閹风ā闁跨喐鏋婚幏鐤熅闁跨喐鏋婚幏鐑芥晸閺傘倖瀚归柨鐔告灮閹风兘鏁撻弬銈嗗闁跨喐鏋婚幏鐑芥晸閺傘倖瀚归柨鐔告灮閹风兘鏁撻弬銈嗗闁跨喐鏋婚幏鐑芥晸閺傘倖瀚归柨鐔告灮閹风兘鏁撻弬銈嗗闁跨喕濡拠褎瀚归柨鐔告灮閹疯渹绔撮柨鐔告灮閹风兘鏁撻弬銈嗗闁跨喐鏋婚幏鐑芥晸閺傘倖瀚归柨鐔告灮閹风兘鏁撻弬銈嗗閸愩垽鏁撻弬銈嗗閻╂挳鏁撻弬銈嗗闁跨喐鏋婚幏鐑芥晸閺傘倖瀚归柨鐔稿疆娴兼瑦瀚归柨鐔告灮閹风兘鏁撻悪锛勵暜閹峰嘲绱￠柨鐔告灮閹风兘鏁撻幓顓濈串閹风兘鏁撻敓锟� - //4 闁跨喓娈曠粔棰佺串閹风兘鏁撻弬銈嗗濡€崇础闁跨喐鏋婚幏鐑芥晸閻ㄥ棛顒查幏閿嬆佸蹇涙晸闁板吀绱幏鐑芥晸閺傘倖瀚瑰Ο鈥崇础闁跨喐鏋婚幏鐑芥晸濡楁梻灏ㄩ幏锟� + __IO uint32_t MODE; //0 普通模式，A、B两路输出互相独立 + //1 互补模式，A、B两路输出都由PERA、HIGHA控制，B路输出与A路输出极性相反，且DZA、DZB控制A、B路输出上升沿推迟时间 + //2 单次模式，同普通模式，但一个周期后自动停止 + //3 对称模式，A、B两路输出互相独立，以两个计数周期产生一个波形输出周期，分辨率提升一倍、频率降低一倍 + //4 对称互补模式，对称模式和互补模式的综合 - __IO uint32_t PERA; //[15:0] 闁跨喐鏋婚幏鐑芥晸閺傘倖瀚� + __IO uint32_t PERA; //[15:0] 周期 - __IO uint32_t HIGHA; //[15:0] 闁跨喓顏喊澶嬪楠炴娊鏁撻弬銈嗗闁跨喐鏋婚幏閿嬫闁跨喐鏋婚幏锟� + __IO uint32_t HIGHA; //[15:0] 高电平持续时长 - __IO uint32_t DZA; //[9:0] 闁跨喐鏋婚幏鐑芥晸閺傘倖瀚归柨鐔告灮閹风兘鏁撻弬銈嗗闁跨喐鏋婚幏鐑芥晸閺傘倖瀚归柨鐔告灮閹风兘鏁撻悪锛勵劜閹烽攱妞傞柨鐔告灮閹风兘鏁撻弬銈嗗闁跨喐鏋婚幏鐑芥晸閺傘倖瀚圭亸蹇涙晸閺傘倖瀚笻IGHA + __IO uint32_t DZA; //[9:0] 死区，即上升沿推迟时长，必须小于HIGHA __IO uint32_t PERB; @@ -1212,7 +1816,7 @@ typedef struct __IO uint32_t DZB; - __IO uint32_t INIOUT; //Init Output level闁跨喐鏋婚幏鐑芥晸閺傘倖瀚规慨瀣晸閺傘倖瀚归柨鐔告灮閹风兘鏁撻悪鈽呮嫹 + __IO uint32_t INIOUT; //Init Output level，初始输出电平 } PWM_TypeDef; #define PWM_INIOUT_PWMA_Pos 0 @@ -1244,7 +1848,7 @@ typedef struct uint32_t RESERVED[3]; - __IO uint32_t HALT; //閸掑綊鏁撻弬銈嗗闁跨喐鏋婚幏鐑芥晸閺傘倖瀚� + __IO uint32_t HALT; //刹车控制 __IO uint32_t CHEN; @@ -1272,7 +1876,7 @@ typedef struct #define PWMG_ADTRG_VALUE_Pos 0 #define PWMG_ADTRG_VALUE_Msk (0xFFFF << PWMG_ADTRG0A_VALUE_Pos) -#define PWMG_ADTRG_EVEN_Pos 16 //1 閸嬪爼鏁撻弬銈嗗闁跨喐鏋婚幏鐑芥晸閺傘倖瀚归柨鐔告灮閹烽攱鏅� 0 闁跨喐鏋婚幏鐑芥晸閺傘倖瀚归柨鐔告灮閹风兘鏁撻弬銈嗗闁跨喐鏋婚幏閿嬫櫏 +#define PWMG_ADTRG_EVEN_Pos 16 //1 偶数周期生效 0 奇数周期生效 #define PWMG_ADTRG_EVEN_Msk (0x01 << PWMG_ADTRG0A_EVEN_Pos) #define PWMG_ADTRG_EN_Pos 17 #define PWMG_ADTRG_EN_Msk (0x01 << PWMG_ADTRG0A_EN_Pos) @@ -1291,13 +1895,13 @@ typedef struct #define PWMG_HALT_PWM4_Msk (0x01 << PWMG_HALT_PWM4_Pos) #define PWMG_HALT_PWM5_Pos 6 #define PWMG_HALT_PWM5_Msk (0x01 << PWMG_HALT_PWM5_Pos) -#define PWMG_HALT_STOPCNT_Pos 7 //1 閸掑綊鏁撻弬銈嗗閺冨爼鏁撻弬銈嗗PWM闁跨喐鏋婚幏鐑芥晸閺傘倖瀚归柨鐔告灮閹风兘鏁撻弬銈嗗闁跨喎顫曢敍灞戒粻濮濄垽鏁撻弬銈嗗闁跨喐鏋婚幏锟� 0 閸掑綊鏁撻弬銈嗗閺冨爼鏁撻弬銈嗗PWM闁跨喐鏋婚幏鐑芥晸閺傘倖瀚归柨鐔告灮閹风兘鏁撻弬銈嗗闁跨喐鏋婚幏鐑芥晸閺傘倖瀚归柨鐔告灮閹凤拷 +#define PWMG_HALT_STOPCNT_Pos 7 //1 刹车时将PWM计数器清零，停止计数 0 刹车时，PWM计数器继续计数 #define PWMG_HALT_STOPCNT_Msk (0x01 << PWMG_HALT_STOPCNT_Pos) -#define PWMG_HALT_INLVL_Pos 8 //1 閸掑綊鏁撻弬銈嗗闁跨喐鏋婚幏鐑芥晸閺傘倖瀚归崣鈺呮晸閻欌剝鏋婚幏鐑芥晸閸欘偓鎷� +#define PWMG_HALT_INLVL_Pos 8 //1 刹车输入高电平有效 #define PWMG_HALT_INLVL_Msk (0x01 << PWMG_HALT_INLVL_Pos) -#define PWMG_HALT_OUTLVL_Pos 9 //1 閸掑綊鏁撻弬銈嗗闁跨喐鏋婚幏鐑芥晸閺傘倖瀚归柨鐔告灮閹风兘鏁撻弬銈嗗闁跨喐鏋婚幏宄板渐闁跨喓瀚涢敓锟� +#define PWMG_HALT_OUTLVL_Pos 9 //1 刹车过程中输出高电平 #define PWMG_HALT_OUTLVL_Msk (0x01 << PWMG_HALT_OUTLVL_Pos) -#define PWMG_HALT_STAT_Pos 10 //1 闁跨喐鏋婚幏鐑芥晸閺傘倖瀚归崚褰掓晸閺傘倖瀚� +#define PWMG_HALT_STAT_Pos 10 //1 正在刹车 #define PWMG_HALT_STAT_Msk (0x01 << PWMG_HALT_STAT_Pos) #define PWMG_CHEN_PWM0A_Pos 0 @@ -1533,11 +2137,11 @@ typedef struct { __IO uint32_t EN; //[0] ENABLE - __IO uint32_t IE; //閸欘亪鏁撻弬銈嗗娑擄拷1閺冨爼鏁撻弬銈嗗IF[CHx]闁跨喐鏋婚幏绋A闁跨喐鏋婚幏鐑芥晸閺傘倖瀚归柨鐔告灮閹风兘鏁撶紒鐐村敾閹风兘鏁撻弬銈嗗姒ф瑩鏁撴潪鍖℃嫹1闁跨喐鏋婚幏鐑芥晸閺傘倖瀚归柨鐔告灮閹疯渹绔撮惄鎾晸閺傘倖瀚归柨鐔告灮閹风兘鏁撻弬銈嗗0 + __IO uint32_t IE; //只有为1时，IF[CHx]在DMA传输结束时才能变为1，否则将一直保持在0 - __IO uint32_t IM; //闁跨喐鏋婚幏铚傝礋1閺冨爼鏁撻弬銈嗗闁跨喐鏋婚幏铚傚▏IF[CHx]娑擄拷1闁跨喐鏋婚幏绌宮a_int娑旂喖鏁撻弬銈嗗闁跨喐鏋婚幏鐑芥晸閺傘倖瀚归崥顕€鏁撻敓锟�1 + __IO uint32_t IM; //当为1时，即使IF[CHx]为1，dma_int也不会因此变1 - __IO uint32_t IF; //閸愶拷1闁跨喐鏋婚幏鐑芥晸閺傘倖瀚� + __IO uint32_t IF; //写1清零 uint32_t RESERVED[12]; @@ -1549,23 +2153,23 @@ typedef struct __IO uint32_t SRC; - __IO uint32_t SRCSGADDR1; //閸欘亪鏁撻弬銈嗗Scatter Gather濡€崇础闁跨喐鏋婚幏铚傚▏闁跨喐鏋婚幏锟� + __IO uint32_t SRCSGADDR1; //只在Scatter Gather模式下使用 - __IO uint32_t SRCSGADDR2; //閸欘亪鏁撻弬銈嗗Scatter Gather濡€崇础闁跨喐鏋婚幏铚傚▏闁跨喐鏋婚幏锟� + __IO uint32_t SRCSGADDR2; //只在Scatter Gather模式下使用 - __IO uint32_t SRCSGADDR3; //閸欘亪鏁撻弬銈嗗Scatter Gather濡€崇础闁跨喐鏋婚幏铚傚▏闁跨喐鏋婚幏锟� + __IO uint32_t SRCSGADDR3; //只在Scatter Gather模式下使用 - __IO uint32_t SRCSGLEN; //閸欘亪鏁撻弬銈嗗Scatter Gather濡€崇础闁跨喐鏋婚幏铚傚▏闁跨喐鏋婚幏锟� + __IO uint32_t SRCSGLEN; //只在Scatter Gather模式下使用 __IO uint32_t DST; - __IO uint32_t DSTSGADDR1; //閸欘亪鏁撻弬銈嗗Scatter Gather濡€崇础闁跨喐鏋婚幏铚傚▏闁跨喐鏋婚幏锟� + __IO uint32_t DSTSGADDR1; //只在Scatter Gather模式下使用 - __IO uint32_t DSTSGADDR2; //閸欘亪鏁撻弬銈嗗Scatter Gather濡€崇础闁跨喐鏋婚幏铚傚▏闁跨喐鏋婚幏锟� + __IO uint32_t DSTSGADDR2; //只在Scatter Gather模式下使用 - __IO uint32_t DSTSGADDR3; //閸欘亪鏁撻弬銈嗗Scatter Gather濡€崇础闁跨喐鏋婚幏铚傚▏闁跨喐鏋婚幏锟� + __IO uint32_t DSTSGADDR3; //只在Scatter Gather模式下使用 - __IO uint32_t DSTSGLEN; //閸欘亪鏁撻弬銈嗗Scatter Gather濡€崇础闁跨喐鏋婚幏铚傚▏闁跨喐鏋婚幏锟� + __IO uint32_t DSTSGLEN; //只在Scatter Gather模式下使用 uint32_t RESERVED[4]; } CH[3]; @@ -1622,16 +2226,16 @@ typedef struct #define DMA_IF_CH7_Pos 7 #define DMA_IF_CH7_Msk (0x01 << DMA_IF_CH7_Pos) -#define DMA_CR_LEN_Pos 0 //闁跨喐鏋婚幏鐑解偓姘舵晸閺傘倖瀚归柨鐔告灮閹风兘鏁撻弬銈嗗闁跨喐婢冪粵瑙勫闁跨喖銈洪敐蹇斿0闁跨喐鏋婚幏宄扮安1闁跨喕顢滈懞鍌︾秶閹风兘鏁撻弬銈嗗闁跨噦鎷�4096闁跨喕顢滈弬銈嗗 +#define DMA_CR_LEN_Pos 0 //此通道传输总长度，0对应1字节，最大4096字节 #define DMA_CR_LEN_Msk (0xFFF << DMA_CR_LEN_Pos) #define DMA_CR_RXEN_Pos 16 #define DMA_CR_RXEN_Msk (0x01 << DMA_CR_RXEN_Pos) #define DMA_CR_TXEN_Pos 17 #define DMA_CR_TXEN_Msk (0x01 << DMA_CR_TXEN_Pos) -#define DMA_CR_AUTORE_Pos 18 //Auto Restart, 闁岸鏁撻弬銈嗗闁跨喕濡潏鐐闁跨喐鏋婚幏鐑芥晸閺傘倖瀚归悵濠囨晸閺傘倖瀚瑰▎鐘绘晸閺傘倖瀚规潻婊堟晸閺傘倖瀚归柨鐔告灮閹风兘鏁撻弬銈嗗闁跨噦鎷� +#define DMA_CR_AUTORE_Pos 18 //Auto Restart, 通道在传输完成后，是否自动重新启动 #define DMA_CR_AUTORE_Msk (0x01 << DMA_CR_AUTORE_Pos) -#define DMA_AM_SRCAM_Pos 0 //Address Mode 0 闁跨喐鏋婚幏宄版絻闁跨喐鏆€鐠佽瀚� 1 闁跨喐鏋婚幏宄版絻闁跨喐鏋婚幏鐑芥晸閺傘倖瀚� 2 scatter gather濡€崇础 +#define DMA_AM_SRCAM_Pos 0 //Address Mode 0 地址固定 1 地址递增 2 scatter gather模式 #define DMA_AM_SRCAM_Msk (0x03 << DMA_AM_SRCAM_Pos) #define DMA_AM_DSTAM_Pos 8 #define DMA_AM_DSTAM_Msk (0x03 << DMA_AM_DSTAM_Pos) @@ -1646,7 +2250,7 @@ typedef struct __I uint32_t SR; //Status Register - __I uint32_t IF; //Interrupt Flag + __I uint32_t IF; //Interrupt Flag，读取清零 __IO uint32_t IE; //Interrupt Enable @@ -1658,51 +2262,41 @@ typedef struct uint32_t RESERVED2[3]; - __I uint32_t ALC; //Arbitration Lost Capture, 闁跨喎濮憗浣筋啇閹峰嘲銇戦柨鐔告灮閹烽攱宕� + __I uint32_t ALC; //Arbitration Lost Capture, 仲裁丢失捕捉 - __I uint32_t ECC; //Error code capture, 闁跨喐鏋婚幏鐑芥晸閺傘倖瀚归柨鐔告灮閹烽攱鐧岄煫璇ф嫹 + __I uint32_t ECC; //Error code capture, 错误代码捕捉 - __IO uint32_t EWLIM; //Error Warning Limit, 闁跨喐鏋婚幏鐑芥晸鐟楃喐濮ら幘鍛闁跨喐鏋婚幏鐑芥晸閺傘倖瀚� + __IO uint32_t EWLIM; //Error Warning Limit, 错误报警限制 - __IO uint32_t RXERR; //RX闁跨喐鏋婚幏鐑芥晸閺傘倖瀚归柨鐔告灮閹风兘鏁撻敓锟� + __IO uint32_t RXERR; //RX错误计数 - __IO uint32_t TXERR; //TX闁跨喐鏋婚幏鐑芥晸閺傘倖瀚归柨鐔告灮閹风兘鏁撻敓锟� + __IO uint32_t TXERR; //TX错误计数 union { - struct //闁跨喕濡棃鈺傚娴ｅ秵妞傞柨鐔哄嵆鐠佽瀚归崘娆撴晸閺傘倖瀚归柨鐔告灮閹风兘鏁撻弬銈嗗闁跨喐鏋婚幏鐑芥晸閺傘倖瀚瑰Ο鈥崇础闁跨喖鎽拠褎瀚归柨鐔哄嵆閸戙倖瀚归柨鐔告灮閹凤拷 - { - __IO uint32_t ACR[4]; //Acceptance Check Register, 闁跨喐鏋婚幏鐑芥晸缁夌ǹ鐦庢潏鐐闁跨喐鏋婚幏锟� + struct + { //在复位时可读写，正常工作模式下不可访问 + __IO uint32_t ACR[4]; //Acceptance Check Register, 验收寄存器 - __IO uint32_t AMR[4]; //Acceptance Mask Register, 闁跨喐鏋婚幏鐑芥晸閺傘倖瀚归柨鐔告灮閹风兘鏁撴潪鍨槑鏉堢偓瀚归柨鐔告灮閹风兘鏁撻弬銈嗗闁跨喐鏋婚幏宄扮安娴ｅ秴鍟�0闁跨喐鏋婚幏绋〥闁跨喐鏋婚幏鐑芥晸閺傘倖瀚归柨鐔告灮閹风兘鏁撻弬銈嗗閸楃姵濯烽柨鐔告灮閹风兘鏁撻悪掳鍎婚幏鐑芥晸閿燂拷 + __IO uint32_t AMR[4]; //Acceptance Mask Register, 验收屏蔽寄存器；对应位写0，ID必须和验收寄存器匹配 uint32_t RESERVED[5]; } FILTER; - union //闁跨喐鏋婚幏鐑芥晸閺傘倖瀚归柨鐔告灮閹风兘鏁撻弬銈嗗闁跨喐鏋婚幏閿嬆佸蹇涙晸闁炬澘褰茬拋瑙勫閸愭瑩鏁撻弬銈嗗闁跨喐鏋婚幏铚傜秴閺冨爼鏁撻弬銈嗗闁跨喓鍗抽崙銈嗗闁跨喐鏋婚幏锟� - { - struct - { - __O uint32_t INFO; + struct + { //在正常工作模式下可读写，复位时不可访问 + __IO uint32_t INFO; - __O uint32_t DATA[12]; - } TXFRAME; - - struct - { - __I uint32_t INFO; - - __I uint32_t DATA[12]; - } RXFRAME; - }; + __IO uint32_t DATA[12]; + } FRAME; }; __I uint32_t RMCNT; //Receive Message Count uint32_t RESERVED3[66]; - struct //TXFRAME闁跨喍鑼庣拋瑙勫闁跨喐甯撮崠鈩冨 - { + struct + { //TXFRAME的读接口 __I uint32_t INFO; __I uint32_t DATA[12]; @@ -1713,14 +2307,12 @@ typedef struct #define CAN_CR_RST_Msk (0x01 << CAN_CR_RST_Pos) #define CAN_CR_LOM_Pos 1 //Listen Only Mode #define CAN_CR_LOM_Msk (0x01 << CAN_CR_LOM_Pos) -#define CAN_CR_STM_Pos 2 //Self Test Mode, 闁跨喐鏋婚幏閿嬆佸蹇涙晸闁炬壆銆嬮幏铚傚▏濞岋繝鏁撻弬銈嗗鎼存棃鏁撻弬銈嗗CAN闁跨喐鏋婚幏鐑芥晸閺傘倖瀚归柨鐔告灮閹疯渹绡冮柨鐔告灮閹风兘鏁撻惃鍡樺灇閻у憡瀚归柨鐔告灮閹风兘鏁撻弬銈嗗 +#define CAN_CR_STM_Pos 2 //Self Test Mode, 此模式下即使没有应答，CAN控制器也可以成功发送 #define CAN_CR_STM_Msk (0x01 << CAN_CR_STM_Pos) -#define CAN_CR_AFM_Pos 3 //Acceptance Filter Mode, 1 闁跨喐鏋婚幏鐑芥晸閺傘倖瀚归柨鐔告灮閹风兘鏁撻弬銈嗗闁跨喎澹欑拠褎瀚归柨鐔告灮閹风兘鏁撻弬銈嗗32娴ｅ秹鏁撻弬銈嗗 0 闁跨喐鏋婚幏鐑芥晸閺傘倖瀚归柨鐔告灮閹风兘鏁撻弬銈嗗闁跨喎澹欑拠褎瀚归柨鐔告灮閹风兘鏁撻弬銈嗗16娴ｅ秹鏁撻弬銈嗗 +#define CAN_CR_AFM_Pos 3 //Acceptance Filter Mode, 1 单个验收滤波器（32位） 0 两个验收滤波器（16位） #define CAN_CR_AFM_Msk (0x01 << CAN_CR_AFM_Pos) -#define CAN_CR_SLEEP_Pos 4 //閸愶拷1闁跨喐鏋婚幏鐑芥晸閺傘倖瀚归惈锟犳晸閺傘倖瀚瑰Ο鈥崇础闁跨喐鏋婚幏鐑芥晸閺傘倖瀚归柨鐔告灮閹风兘鏁撶粩顓熸た閸斻劑鏁撻弬銈嗗闁跨喎褰ㄧ拋瑙勫閺冨爼鏁撻弬銈嗗闁跨喓鐛ょ拠褎瀚归柨鐔烘畷鐠佽瀚归柨鐔告灮閹风兘鏁撻弬銈嗗闁跨喕濞囬敓锟� +#define CAN_CR_SLEEP_Pos 4 //写1进入睡眠模式，有总线活动或中断时唤醒并自动清零此位 #define CAN_CR_SLEEP_Msk (0x01 << CAN_CR_SLEEP_Pos) -#define CAN_CR_DMAEN_Pos 5 -#define CAN_CR_DMAEN_Msk (0x01 << CAN_CR_DMAEN_Pos) #define CAN_CMD_TXREQ_Pos 0 //Transmission Request #define CAN_CMD_TXREQ_Msk (0x01 << CAN_CMD_TXREQ_Pos) @@ -1733,38 +2325,38 @@ typedef struct #define CAN_CMD_SRR_Pos 4 //Self Reception Request #define CAN_CMD_SRR_Msk (0x01 << CAN_CMD_SRR_Pos) -#define CAN_SR_RXDA_Pos 0 //Receive Data Available闁跨喐鏋婚幏鐑芥晸閺傘倖瀚归柨鐔告灮閹风éIFO闁跨喐鏋婚幏鐑芥晸閺傘倖瀚归柨鐔告灮閹风兘鏁撻弬銈嗗闁跨喐鏋婚幏閿嬩紖闁跨喐鏋婚幏鐑芥晸閻ㄥ棜顔愰幏宄板絿 +#define CAN_SR_RXDA_Pos 0 //Receive Data Available，接收FIFO中有完整消息可以读取 #define CAN_SR_RXDA_Msk (0x01 << CAN_SR_RXDA_Pos) -#define CAN_SR_RXOV_Pos 1 //Receive FIFO Overrun闁跨喐鏋婚幏鐑芥晸闁剧増鏋婚幏鐑芥晸缁夊摜顣幏鐑芥晸閺傘倖瀚归幁顖炴晸閺傘倖瀚归柨鐔诲Ν閺傘倖瀚归柨鐔告灮閹风éIFO闁跨喐鏋婚幏鐑芥晸閺傘倖瀚归柨鐔告灮閹风兘鏁撻弬銈嗗闁跨喐鏋婚幏锟� +#define CAN_SR_RXOV_Pos 1 //Receive FIFO Overrun，新接收的信息由于接收FIFO已满而丢掉 #define CAN_SR_RXOV_Msk (0x01 << CAN_SR_RXOV_Pos) -#define CAN_SR_TXBR_Pos 2 //Transmit Buffer Release闁跨喐鏋婚幏锟�0 闁跨喐鏋婚幏鐑芥晸閼哄倽鎻幏鐑芥晸閺傘倖瀚归崜宥夋晸閺傘倖瀚规慨鍡涙晸閺傘倖瀚归崑婊堟晸閺傘倖瀚归柨鐔告灮閹风柉鐦柨鐔告灮閹风兘鏁撻崣顐ユ彧閹烽顣遍柨鐔告灮閹风兘鏁撴潏鍐挎嫹 1 闁跨喐鏋婚幏鐑芥晸閺傘倖瀚归崘娆撴晸閺傘倖瀚归柨鐔兼應绾板瀚归柨鐔告灮閹烽攱浼呴柨鐔告灮閹风兘鏁撻弬銈嗗 +#define CAN_SR_TXBR_Pos 2 //Transmit Buffer Release，0 正在处理前面的发送，现在不能写新的消息 1 可以写入新的消息发送 #define CAN_SR_TXBR_Msk (0x01 << CAN_SR_TXBR_Pos) -#define CAN_SR_TXOK_Pos 3 //Transmit OK闁跨喐鏋婚幏绌漸ccessfully completed +#define CAN_SR_TXOK_Pos 3 //Transmit OK，successfully completed #define CAN_SR_TXOK_Msk (0x01 << CAN_SR_TXOK_Pos) -#define CAN_SR_RXBUSY_Pos 4 //Receive Busy闁跨喐鏋婚幏鐑芥晸閺傘倖瀚归柨鐔诲Ν閺傘倖瀚归柨鐔告灮閹凤拷 +#define CAN_SR_RXBUSY_Pos 4 //Receive Busy，正在接收 #define CAN_SR_RXBUSY_Msk (0x01 << CAN_SR_RXBUSY_Pos) -#define CAN_SR_TXBUSY_Pos 5 //Transmit Busy闁跨喐鏋婚幏鐑芥晸閺傘倖瀚归柨鐔诲Ν閸戙倖瀚归柨鐔告灮閹凤拷 +#define CAN_SR_TXBUSY_Pos 5 //Transmit Busy，正在发送 #define CAN_SR_TXBUSY_Msk (0x01 << CAN_SR_TXBUSY_Pos) -#define CAN_SR_ERRWARN_Pos 6 //1 闁跨喐鏋婚幏鐑芥晸閺傘倖瀚规稉鈧柨鐔告灮閹风兘鏁撻弬銈嗗闁跨喐鏋婚幏鐑芥晸閺傘倖瀚归柨鐔告灮閹风兘鏁撻弬銈嗗闁垮骏鎷� Warning Limit +#define CAN_SR_ERRWARN_Pos 6 //1 至少一个错误计数器达到 Warning Limit #define CAN_SR_ERRWARN_Msk (0x01 << CAN_SR_ERRWARN_Pos) -#define CAN_SR_BUSOFF_Pos 7 //1 CAN 闁跨喐鏋婚幏鐑芥晸閺傘倖瀚归柨鐔告灮閹风兘鏁撻弬銈嗗闁跨喐鏋婚幏鐑芥晸閺傘倖瀚归柨鐔侯仾閸忚櫕鍞婚幏椋庡Ц閹線鏁撻弬銈嗗濞岋繝鏁撻崣顐ヮ嚋閹风兘鏁撶拠顐㈠煂闁跨喐鏋婚幏鐑芥晸缁旑厽妞块崝锟� +#define CAN_SR_BUSOFF_Pos 7 //1 CAN 控制器处于总线关闭状态，没有参与到总线活动 #define CAN_SR_BUSOFF_Msk (0x01 << CAN_SR_BUSOFF_Pos) #define CAN_IF_RXDA_Pos 0 //IF.RXDA = SR.RXDA & IE.RXDA #define CAN_IF_RXDA_Msk (0x01 << CAN_IF_RXDA_Pos) -#define CAN_IF_TXBR_Pos 1 //闁跨喐鏋婚幏绋〦.TXBR=1閺冨爼鏁撻弬銈嗗SR.TXBR闁跨喐鏋婚幏锟�0闁跨喐鏋婚幏鐑芥晸閿燂拷1闁跨喐鏋婚幏鐑芥晸閺傘倖瀚规担宥夋晸閺傘倖瀚规担锟� +#define CAN_IF_TXBR_Pos 1 //当IE.TXBR=1时，SR.TXBR由0变成1将置位此位 #define CAN_IF_TXBR_Msk (0x01 << CAN_IF_TXBR_Pos) -#define CAN_IF_ERRWARN_Pos 2 //闁跨喐鏋婚幏绋〦.ERRWARN=1閺冨爼鏁撻弬銈嗗SR.ERRWARN闁跨喐鏋婚幏绋碦.BUSOFF 0-to-1 闁跨喐鏋婚幏锟� 1-to-0闁跨喐鏋婚幏鐑芥晸閺傘倖瀚规担宥夋晸閺傘倖瀚规担锟� +#define CAN_IF_ERRWARN_Pos 2 //当IE.ERRWARN=1时，SR.ERRWARN或SR.BUSOFF 0-to-1 或 1-to-0将置位此位 #define CAN_IF_ERRWARN_Msk (0x01 << CAN_IF_ERRWARN_Pos) #define CAN_IF_RXOV_Pos 3 //IF.RXOV = SR.RXOV & IE.RXOV #define CAN_IF_RXOV_Msk (0x01 << CAN_IF_RXOV_Pos) -#define CAN_IF_WKUP_Pos 4 //闁跨喐鏋婚幏绋〦.WKUP=1閺冨爼鏁撻弬銈嗗闁跨喐鏋婚幏椋庢蒋闁跨喐鏋婚幏閿嬆佸蹇涙晸闁炬壆顣幏绋N闁跨喐鏋婚幏鐑芥晸閺傘倖瀚归柨鐔告灮閹风兘鏁撻弬銈嗗閻涚偓鏋婚幏鐑芥晸閺傘倖瀚归崨瀣澔椤曞灝绨㈢拠褎瀚归柨鐔告灮閹风兘鏁撴潪鍖℃嫹 +#define CAN_IF_WKUP_Pos 4 //当IE.WKUP=1时，在睡眠模式下的CAN控制器检测到总线活动时硬件置位 #define CAN_IF_WKUP_Msk (0x01 << CAN_IF_WKUP_Pos) #define CAN_IF_ERRPASS_Pos 5 // #define CAN_IF_ERRPASS_Msk (0x01 << CAN_IF_ERRPASS_Pos) -#define CAN_IF_ARBLOST_Pos 6 //Arbitration Lost闁跨喐鏋婚幏鐑芥晸閺傘倖瀚笽E.ARBLOST=1閺冨爼鏁撻弬銈嗗CAN闁跨喐鏋婚幏鐑芥晸閺傘倖瀚归柨鐔告灮閹风兘鏁撻弬銈嗗婢堕亶鏁撻崝顐ヮ梿閹插瀚圭仦閬嶆晸閺傘倖瀚规潏妤呮晸缂佺偛绨㈢拠褎瀚归柨鐔告灮閹风兘鏁撴潪鍖℃嫹 +#define CAN_IF_ARBLOST_Pos 6 //Arbitration Lost，当IE.ARBLOST=1时，CAN控制器丢失仲裁变成接收方时硬件置位 #define CAN_IF_ARBLOST_Msk (0x01 << CAN_IF_ARBLOST_Pos) -#define CAN_IF_BUSERR_Pos 7 //闁跨喐鏋婚幏绋〦.BUSERR=1閺冨爼鏁撻弬銈嗗CAN闁跨喐鏋婚幏鐑芥晸閺傘倖瀚归柨鐔告灮閹风兘鏁撻弬銈嗗閻涚偓鏋婚幏鐑芥晸閺傘倖瀚归崣浠嬫晸閺傘倖瀚归柨鐔虹哺鎼村洩顕滈幏鐑芥晸閺傘倖瀚归柨鐔诲▏閿燂拷 +#define CAN_IF_BUSERR_Pos 7 //当IE.BUSERR=1时，CAN控制器检测到总线错误时硬件置位 #define CAN_IF_BUSERR_Msk (0x01 << CAN_IF_BUSERR_Pos) #define CAN_IE_RXDA_Pos 0 @@ -1784,78 +2376,67 @@ typedef struct #define CAN_IE_BUSERR_Pos 7 #define CAN_IE_BUSERR_Msk (0x01 << CAN_IE_BUSERR_Pos) -#define CAN_BT0_BRP_Pos 0 //Baud Rate Prescaler闁跨喐鏋婚幏绋N閺冨爼鏁撻幋鎺戝礋娴ｏ拷=2*Tsysclk*(BRP+1) +#define CAN_BT0_BRP_Pos 0 //Baud Rate Prescaler，CAN时间单位=2*Tsysclk*(BRP+1) #define CAN_BT0_BRP_Msk (0x3F << CAN_BT0_BRP_Pos) #define CAN_BT0_SJW_Pos 6 //Synchronization Jump Width #define CAN_BT0_SJW_Msk (0x03 << CAN_BT0_SJW_Pos) -#define CAN_BT1_TSEG1_Pos 0 //t_tseg1 = CAN閺冨爼鏁撻幋鎺戝礋娴ｏ拷 * (TSEG1+1) +#define CAN_BT1_TSEG1_Pos 0 //t_tseg1 = CAN时间单位 * (TSEG1+1) #define CAN_BT1_TSEG1_Msk (0x0F << CAN_BT1_TSEG1_Pos) -#define CAN_BT1_TSEG2_Pos 4 //t_tseg2 = CAN閺冨爼鏁撻幋鎺戝礋娴ｏ拷 * (TSEG2+1) +#define CAN_BT1_TSEG2_Pos 4 //t_tseg2 = CAN时间单位 * (TSEG2+1) #define CAN_BT1_TSEG2_Msk (0x07 << CAN_BT1_TSEG2_Pos) -#define CAN_BT1_SAM_Pos 7 //闁跨喐鏋婚幏鐑芥晸閺傘倖瀚归柨鐔告灮閹风兘鏁撻弬銈嗗 0: sampled once 1: sampled three times +#define CAN_BT1_SAM_Pos 7 //采样次数 0: sampled once 1: sampled three times #define CAN_BT1_SAM_Msk (0x01 << CAN_BT1_SAM_Pos) #define CAN_ECC_SEGCODE_Pos 0 //Segment Code -#define CAN_ECC_SEGCODE_Msk (0x0F << CAN_ECC_SEGCODE_Pos) -#define CAN_ECC_DIR_Pos 4 //0 error occurred during transmission 1 during reception +#define CAN_ECC_SEGCODE_Msk (0x1F << CAN_ECC_SEGCODE_Pos) +#define CAN_ECC_DIR_Pos 5 //0 error occurred during transmission 1 during reception #define CAN_ECC_DIR_Msk (0x01 << CAN_ECC_DIR_Pos) -#define CAN_ECC_ERRCODE_Pos 5 //Error Code闁跨喐鏋婚幏锟�0 Bit error 1 Form error 2 Stuff error 3 other error +#define CAN_ECC_ERRCODE_Pos 6 //Error Code：0 Bit error 1 Form error 2 Stuff error 3 other error #define CAN_ECC_ERRCODE_Msk (0x03 << CAN_ECC_ERRCODE_Pos) #define CAN_INFO_DLC_Pos 0 //Data Length Control #define CAN_INFO_DLC_Msk (0x0F << CAN_INFO_DLC_Pos) -#define CAN_INFO_RTR_Pos 6 //Remote Frame闁跨喐鏋婚幏锟�1 鏉╂粓鏁撻弬銈嗗鐢拷 0 闁跨喐鏋婚幏鐑芥晸閺傘倖瀚圭敮锟� +#define CAN_INFO_RTR_Pos 6 //Remote Frame，1 远程帧 0 数据帧 #define CAN_INFO_RTR_Msk (0x01 << CAN_INFO_RTR_Pos) -#define CAN_INFO_FF_Pos 7 //Frame Format闁跨喐鏋婚幏锟�0 闁跨喐鏋婚幏宄板櫙鐢囨晸閺傘倖瀚瑰锟� 1 闁跨喐鏋婚幏宄扮潔鐢囨晸閺傘倖瀚瑰锟� +#define CAN_INFO_FF_Pos 7 //Frame Format，0 标准帧格式 1 扩展帧格式 #define CAN_INFO_FF_Msk (0x01 << CAN_INFO_FF_Pos) typedef struct { - __IO uint32_t IE; //[0] 娑擄拷0闁跨喐鏋婚幏閿嬫闁跨喐鏋婚幏绋〧[0]缂佹挳鏁撻弬銈嗗娑擄拷0 + __IO uint32_t IE; //[0] 为0的时候，IF[0]维持为0 - __IO uint32_t IF; //[0] 闁跨喐鏋婚幏鐑芥晸閺傘倖瀚归柨鐔活敎闂堚晜瀚归柨鐔告灮閹风兘鏁撻弬銈嗗妤ｅ﹪鏁撻弬銈嗗闁跨喐鏋婚幏鐤禂闁跨喐鏋婚幏鐑芥晸缂佺偞鍞婚幏鐑芥晸閿燂拷1闁跨喐鏋婚幏宄板晸1闁跨喐鏋婚幏鐑芥晸閺傘倖瀚� + __IO uint32_t IF; //[0] 当完成指定长度的数据传输时置1，写1清零 - __IO uint32_t IM; //[0] 闁跨喐鏋婚幏鐑芥晸閻偄鐦庢潏鐐闁跨喐鏋婚幏铚傝礋1閺冨爼鏁撻弬銈嗗LCDC闁跨喐鏋婚幏鐑芥晸閸欘偅鏌囩拠褎瀚归柨鐔告灮閹风兘鏁撻弬銈嗗闁跨喐鏋婚幏鐑芥晸鏉堝啩缍嗙粵瑙勫闁跨喐鏋婚幏宄板祻瀹勶繝鏁撻弬銈嗗閽€宥嗗闁跨喐鏋婚幏鐑芥晸閿燂拷 + __IO uint32_t IM; //[0] 当该寄存器为1时，LCDC的中断不会输出给系统的中断控制寄存器 __IO uint32_t START; - __IO uint32_t SRCADDR; //闁跨喐鏋婚幏鐑芥晸閺傘倖瀚瑰┃鎰版晸閺傘倖瀚归崸鈧柨鐔惰寧鏉堢偓瀚归柨鐔告灮閹风兘鏁撻弬銈嗗30娴ｅ秹鏁撻弬銈嗗闁跨喐鏋婚幏鐑芥晸閺傘倖瀚规担宥夋晸閻ㄥ棜顔愰幏鐑芥晸閺傘倖瀚归柨鐔告灮閹凤拷 + __IO uint32_t SRCADDR; //数据源地址寄存器，必须字对齐（即地址的低2位必须是0） __IO uint32_t CR0; __IO uint32_t CR1; - __IO uint32_t PRECMDV; //闁跨喐鏋婚幏绋璓U闁跨喐甯撮崠鈩冨闁跨喎褰ㄩ敐蹇斿闁跨喐鏋婚幏鐑芥晸閺傘倖瀚归柨鐔告灮閹风兘鏁撻弬銈嗗閸撳秹鏁撻弬銈嗗RS闁跨喐鏋婚幏鐑芥晸闁扮數顣幏鐑芥晸閺傘倖瀚规稉鈧柨鐔惰寧閿濆繑瀚归柨鐔告灮閹风兘鏁撻弬銈嗗闁跨喐鏋婚幏鐑芥晸閺傘倖瀚归柨鐔荤窛绾板瀚归崐锟� + __IO uint32_t PRECMDV; //在MPU接口中，发送数据前，RS拉低的那一拍，数据总线上的值 } LCD_TypeDef; -#define LCD_START_MPUEN_Pos 0 //0 RGB闁跨喐甯撮崠鈩冨 1 MPU闁跨喐甯撮崠鈩冨 -#define LCD_START_MPUEN_Msk (0x01 << LCD_START_MPUEN_Pos) -#define LCD_START_GO_Pos 1 //閸愶拷1闁跨喐鏋婚幏宄邦潗闁跨喐鏋婚幏鐑芥晸閺傘倖瀚归柨鐔告灮閹风兘鏁撻幑鍑ょ秶閹风兘鏁撻弬銈嗗闁跨喐宓庢潏鐐闁跨喐鏋婚幏鐑芥晸閺傘倖瀚归柨鐔告灮閹风兘鏁撻弬銈嗗鏉╂粓鏁撻弬銈嗗闁跨喐鏋婚幏鐑芥晸閿燂拷 +#define LCD_START_GO_Pos 1 //写1开始传输数据，数据传输结束后自动清零 #define LCD_START_GO_Msk (0x01 << LCD_START_GO_Pos) #define LCD_START_BURST_Pos 2 #define LCD_START_BURST_Msk (0x01 << LCD_START_BURST_Pos) -#define LCD_START_POSTCMDE_Pos 3 //闁跨喐鏋婚幏铚傜昂闁跨喐鏋婚幏鐤洣闁跨喐鏋婚幏鐑芥晸閺傘倖瀚归崘娆撴晸閺傘倖瀚归幏鍥晸閺傘倖瀚归柨鐔活敎椤曞棙瀚归摶鍜佸劉闁跨喐褰搴㈠闁跨喐褰导娆愬闁跨噦鎷�0x80闁跨喐鏋婚幏鐑芥晸閺傘倖瀚归柨鐔告灮閹风兘鏁撻弬銈嗗闁跨喐鏋婚幏鐑芥晸鐞涙鎷� -#define LCD_START_POSTCMDE_Msk (0x01 << LCD_START_POSTCMDE_Pos) -#define LCD_START_POSTCMDV_Pos 4 //闁跨喐鏋婚幏鐑芥晸閺傘倖瀚归柨鐔告灮閹风兘鏁撻弬銈嗗闁跨喐鏋婚幏鐑芥晸鐞涙鎷濋幏鐑芥晸閺傘倖瀚归崘銏ゆ晸閺傘倖瀚归柨鐔告灮閹风兘鏁撻弬銈嗗闁跨喐鏋婚幏鐑芥晸閺傘倖瀚圭化濠氭晸鐞涙顣幏鐑芥晸娓氥儺鍓ㄩ幏鐑芥晸閺傘倖瀚归柨鐕傛嫹0x80闁跨喐鏋婚幏鐑芥晸閺傘倖瀚归柨鐔告灮閹风兘鏁撻弬銈嗗闁跨喐鏋婚幏鐤洣闁跨喐鏋婚幏鐑芥晸閺傘倖瀚归柨鐔告灮閹凤拷 -#define LCD_START_POSTCMDV_Msk (0xFFFF << LCD_START_POSTCMDV_Pos) -#define LCD_CR0_VPIX_Pos 0 //闁跨喐鏋婚幏绌歰rtrait娑擄拷0閺冨爼鏁撻弬銈嗗闁跨喐鏋婚幏椋庛仛闁跨喐鏋婚幏椋庢纯闁跨喐鏋婚幏鐑芥晸閺傘倖瀚归柨鐔告灮閹风兘鏁撻弬銈嗗妫ｆ鏁撻弬銈嗗闁跨喐鏋婚幏鐑芥晸閿燂拷0闁跨喐鏋婚幏椋庛仛1闁跨喐鏋婚幏鐑芥晸閺傘倖瀚归柨鐔告灮閹风兘鏁撴潪鍖℃嫹767 -//闁跨喐鏋婚幏绌歰rtrait娑擄拷1閺冨爼鏁撻弬銈嗗闁跨喐鏋婚幏椋庛仛濮樻潙閽╅柨鐔告灮閹风兘鏁撻弬銈嗗闁跨喐鏋婚幏鐑芥晸閺傘倖瀚规＃妤呮晸閺傘倖瀚归柨鐔告灮閹风兘鏁撻敓锟�0闁跨喐鏋婚幏椋庛仛1闁跨喐鏋婚幏鐑芥晸閺傘倖瀚归柨鐔告灮閹风兘鏁撴潪鍖℃嫹767 +#define LCD_CR0_VPIX_Pos 0 /*当portrait为0时，表示垂直方向的像素个数，0表示1个，最大为767 \ + //当portrait为1时，表示水平方向的像素个数，0表示1个，最大为767 */ #define LCD_CR0_VPIX_Msk (0x3FF << LCD_CR0_VPIX_Pos) -#define LCD_CR0_HPIX_Pos 10 //闁跨喐鏋婚幏绌歰rtrait娑擄拷0閺冨爼鏁撻弬銈嗗闁跨喐鏋婚幏椋庛仛濮樻潙閽╅柨鐔告灮閹风兘鏁撻弬銈嗗闁跨喐鏋婚幏鐑芥晸閺傘倖瀚规＃妤呮晸閺傘倖瀚归柨鐔告灮閹风兘鏁撻敓锟�0闁跨喐鏋婚幏椋庛仛1闁跨喐鏋婚幏鐑芥晸閺傘倖瀚归柨鐔告灮閹风兘鏁撴潪鍖℃嫹1023 -//闁跨喐鏋婚幏绌歰rtrait娑擄拷1閺冨爼鏁撻弬銈嗗闁跨喐鏋婚幏椋庛仛闁跨喐鏋婚幏椋庢纯闁跨喐鏋婚幏鐑芥晸閺傘倖瀚归柨鐔告灮閹风兘鏁撻弬銈嗗妫ｆ鏁撻弬銈嗗闁跨喐鏋婚幏鐑芥晸閿燂拷0闁跨喐鏋婚幏椋庛仛1闁跨喐鏋婚幏鐑芥晸閺傘倖瀚归柨鐔告灮閹风兘鏁撴潪鍖℃嫹1023 +#define LCD_CR0_HPIX_Pos 10 /*当portrait为0时，表示水平方向的像素个数，0表示1个，最大为1023 \ + //当portrait为1时，表示垂直方向的像素个数，0表示1个，最大为1023 */ #define LCD_CR0_HPIX_Msk (0x3FF << LCD_CR0_HPIX_Pos) -#define LCD_CR0_DCLK_Pos 20 //0 DOTCLK娑撯偓閻╂挳鏁撻弬銈嗗鏉烇拷 1 DOTCLK闁跨喕濡崠鈩冨闁跨喐鏋婚幏閿嬫閸嬫粓鏁撻弬銈嗗1 +#define LCD_CR0_DCLK_Pos 20 //0 DOTCLK一直翻转 1 DOTCLK在空闲时停在1 #define LCD_CR0_DCLK_Msk (0x01 << LCD_CR0_DCLK_Pos) -#define LCD_CR0_HLOW_Pos 21 //闁跨喐鏋婚幏鐑芥晸缁辩笌YNC闁跨喖鍙虹喊澶嬪楠炴娊鏁撻弬銈嗗闁跨喐鏋婚幏鐑芥晸閺傘倖瀚归柨鐔峰Л闂堚晜瀚笵OTCLK闁跨喐鏋婚幏鐑芥晸閼哄偊缍囬幏锟�0闁跨喐鏋婚幏椋庛仛1闁跨喐鏋婚幏鐑芥晸閺傘倖瀚归柨鐔告灮閹凤拷 +#define LCD_CR0_HLOW_Pos 21 //输出HSYNC低电平持续多少个DOTCLK周期，0表示1个周期 #define LCD_CR0_HLOW_Msk (0x03 << LCD_CR0_HLOW_Pos) -#define LCD_CR0_DLEN_Pos 0 //MPU闁跨喐甯撮崠鈩冨閺冨爼鏁撻弬銈嗗闁跨喎澹欏▎陇顕滈幏鐑芥晸閺傘倖瀚归柨鐔告灮閹风兘鏁撻弬銈嗗闁跨喐宓庣粵瑙勫闁跨喖銈洪敐蹇斿闁跨喐鏋婚幏铚傜秴娑撴椽鏁撶悰妤勫Ν閿濆繑瀚�0闁跨喐鏋婚幏椋庛仛1闁跨喐鏋婚幏锟� -#define LCD_CR0_DLEN_Msk (0x1FFFFF << LCD_CR0_DLEN_Pos) - -#define LCD_CR1_DIRV_Pos 0 //0 portrait=0闁跨喐鏋婚幏鐑芥晸閺傘倖瀚归柨鐔告灮閹烽攱膩瀵拷 1 portrait=1闁跨喐鏋婚幏鐑芥晸閺傘倖瀚归柨鐔告灮閹烽攱膩瀵拷 -#define LCD_CR1_DIRV_Msk (0x01 << LCD_CR1_DIRV_Pos) #define LCD_CR1_VFP_Pos 1 #define LCD_CR1_VFP_Msk (0x07 << LCD_CR1_VFP_Pos) #define LCD_CR1_VBP_Pos 4 @@ -1864,26 +2445,11 @@ typedef struct #define LCD_CR1_HFP_Msk (0x1F << LCD_CR1_HFP_Pos) #define LCD_CR1_HBP_Pos 14 #define LCD_CR1_HBP_Msk (0x7F << LCD_CR1_HBP_Pos) -#define LCD_CR1_DCLKDIV_Pos 21 //DOTCLK闁跨喐鏋婚幏鐑芥晸閺傘倖瀚归柨鐔惰寧閿濆繑瀚归柨鐔虹哺閹插瀚归幏銉ヮ潒闁跨喓瀚涚喊澶嬪姒鏁撻敓锟�0闁跨喐鏋婚幏椋庛仛2闁跨喐鏋婚幏鐑筋暥闁跨喐鏋婚幏锟�1闁跨喐鏋婚幏椋庛仛4闁跨喐鏋婚幏鐑筋暥 ... +#define LCD_CR1_DCLKDIV_Pos 21 //DOTCLK相对于模块时钟的分频比，0表示2分频，1表示4分频 ... #define LCD_CR1_DCLKDIV_Msk (0x1F << LCD_CR1_DCLKDIV_Pos) -#define LCD_CR1_DCLKINV_Pos 26 //1 闁跨喐鏋婚幏鐑芥晸缁辩睋TCLK闁跨喐鏋婚幏鐑芥晸閺傘倖瀚规惔鏃堟晸閺傘倖瀚归柨鐔告灮閹风兘鏁撻弬銈嗗DOTCLK闁跨喖鎽弬銈嗗闁跨喐鍩呯拠褎瀚归柨鐔告灮閹风兘鏁撻弬銈嗗闁跨喐宓庣喊澶嬪闁跨喐鏋婚幏锟� +#define LCD_CR1_DCLKINV_Pos 26 //1 输出DOTCLK反向，应用于用DOTCLK下降沿采样数据的屏 #define LCD_CR1_DCLKINV_Msk (0x01 << LCD_CR1_DCLKINV_Pos) -#define LCD_CR1_REG_Pos 0 //LCD_CR1_CMD_Pos閸欐牕鈧拷1閺冨爼鏁撻弬銈嗗闁跨喍鑼庢潏鐐闁跨喐鏋婚幏鐑芥晸閺傘倖瀚归柨鐔告灮閹峰嘲鈧拷 -#define LCD_CR1_REG_Msk (0xFFFF << LCD_CR1_REG_Pos) -#define LCD_CR1_I80_Pos 16 //1 闁跨喐甯撮崠鈩冨娑撶瘨80 0 闁跨喐甯撮崠鈩冨娑撶瘲68 -#define LCD_CR1_I80_Msk (0x01 << LCD_CR1_I80_Pos) -#define LCD_CR1_CMD_Pos 17 //0 闁跨喐鏋婚幏鐑芥晸閹圭柉鎻幏鐑芥晸閹存帪绱濋柨鐔告灮閹风úS娑撴椽鏁撶粩顓狀暜閹峰嘲閽� 1 闁跨喐鏋婚幏鐑芥晸缁涘绱堕柨鐔稿灊閿涘矂鏁撻弬銈嗗闁跨喐鏋婚幏鐑芥晸閺傘倖瀚归幏鍥晸閺傘倖瀚归柨鐔告灮閹风兘鏁撻弬銈嗗闁跨喐鏋婚幏鐑芥晸閺傘倖瀚归柨鐔虹ゲS娑撴椽鏁撻柊鐢殿暜閹峰嘲閽� -#define LCD_CR1_CMD_Msk (0x01 << LCD_CR1_CMD_Pos) -#define LCD_CR1_TTAIL_Pos 18 //CSn闁跨喐鏋婚幏鐑芥晸閺傘倖瀚归柨鐔稿焻绾板瀚笴Sn闁跨喖鎽弬銈嗗闁跨喐鍩呯喊澶嬪閺冨爼鏁撻弬銈嗗 -#define LCD_CR1_TTAIL_Msk (0x07 << LCD_CR1_TTAIL_Pos) -#define LCD_CR1_TAH_Pos 21 //WRn闁跨喐鏋婚幏鐑芥晸閺傘倖瀚归柨鐔稿焻绾板瀚笴Sn闁跨喐鏋婚幏鐑芥晸閺傘倖瀚归柨鐔稿焻绾板瀚归弮鍫曟晸閺傘倖瀚� -#define LCD_CR1_TAH_Msk (0x03 << LCD_CR1_TAH_Pos) -#define LCD_CR1_TPWLW_Pos 23 //WRn闁跨喖鍙虹喊澶嬪楠炴娊鏁撴笟銉ь劜閹风兘鏁撻弬銈嗗閺冨爼鏁撻弬銈嗗 -#define LCD_CR1_TPWLW_Msk (0x07 << LCD_CR1_TPWLW_Pos) -#define LCD_CR1_TAS_Pos 26 //CSn闁跨喖鎽弬銈嗗闁跨喐鍩呯喊澶嬪WRn闁跨喖鎽弬銈嗗闁跨喐鍩呯喊澶嬪閺冨爼鏁撻弬銈嗗 -#define LCD_CR1_TAS_Msk (0x03 << LCD_CR1_TAS_Pos) - typedef struct { __IO uint32_t DMA_MEM_ADDR; @@ -1906,9 +2472,9 @@ typedef struct __IO uint32_t IF; - __IO uint32_t IE; + __IO uint32_t IFE; //Interrupt Flag Enable - __IO uint32_t IM; + __IO uint32_t IE; //Interrupt Enalbe __IO uint32_t CMD12ERR; @@ -1917,9 +2483,9 @@ typedef struct __IO uint32_t MAXCURR; } SDIO_TypeDef; -#define SDIO_BLK_SIZE_Pos 0 //0x200 512闁跨喕顢滈弬銈嗗 0x400 1024闁跨喕顢滈弬銈嗗 0x800 2048闁跨喕顢滈弬銈嗗 +#define SDIO_BLK_SIZE_Pos 0 //0x200 512字节 0x400 1024字节 0x800 2048字节 #define SDIO_BLK_SIZE_Msk (0xFFF << SDIO_BLK_SIZE_Pos) -#define SDIO_BLK_COUNT_Pos 16 //0 Stop Transfer 1 1闁跨喐鏋婚幏锟� 2 2闁跨喐鏋婚幏锟� ... ... +#define SDIO_BLK_COUNT_Pos 16 //0 Stop Transfer 1 1块 2 2块 ... ... #define SDIO_BLK_COUNT_Msk (0xFFF << SDIO_BLK_COUNT_Pos) #define SDIO_CMD_DMAEN_Pos 0 @@ -1932,7 +2498,7 @@ typedef struct #define SDIO_CMD_DIRREAD_Msk (0x01 << SDIO_CMD_DIRREAD_Pos) #define SDIO_CMD_MULTBLK_Pos 5 //0 Single Block 1 Multiple Block #define SDIO_CMD_MULTBLK_Msk (0x01 << SDIO_CMD_MULTBLK_Pos) -#define SDIO_CMD_RESPTYPE_Pos 16 //闁跨喐鏋婚幏宄扮安闁跨喐鏋婚幏鐑芥晸闁扮缍囬幏锟�0 闁跨喐鏋婚幏鐑芥晸閺傘倖瀚规惔锟� 1 136娴ｅ秹鏁撻弬銈嗗鎼达拷 2 48娴ｅ秹鏁撻弬銈嗗鎼达拷 3 48娴ｅ秹鏁撻弬銈嗗鎼存棃鏁撻弬銈嗗Busy after response +#define SDIO_CMD_RESPTYPE_Pos 16 //响应类型，0 无响应 1 136位响应 2 48位响应 3 48位响应，Busy after response #define SDIO_CMD_RESPTYPE_Msk (0x03 << SDIO_CMD_RESPTYPE_Pos) #define SDIO_CMD_CRCCHECK_Pos 19 //Command CRC Check Enable #define SDIO_CMD_CRCCHECK_Msk (0x01 << SDIO_CMD_CRCCHECK_Pos) @@ -1942,7 +2508,7 @@ typedef struct #define SDIO_CMD_HAVEDATA_Msk (0x01 << SDIO_CMD_HAVEDATA_Pos) #define SDIO_CMD_CMDTYPE_Pos 22 //0 NORMAL 1 SUSPEND 2 RESUME 3 ABORT #define SDIO_CMD_CMDTYPE_Msk (0x03 << SDIO_CMD_CMDTYPE_Pos) -#define SDIO_CMD_CMDINDX_Pos 24 //Command Index闁跨喐鏋婚幏绋D0-63闁跨喐鏋婚幏绋烠MD0-63 +#define SDIO_CMD_CMDINDX_Pos 24 //Command Index，CMD0-63、ACMD0-63 #define SDIO_CMD_CMDINDX_Msk (0x3F << SDIO_CMD_CMDINDX_Pos) #define SDIO_CR1_4BIT_Pos 1 //1 4 bit mode 0 1 bit mode @@ -1951,7 +2517,7 @@ typedef struct #define SDIO_CR1_8BIT_Msk (0x01 << SDIO_CR1_8BIT_Pos) #define SDIO_CR1_CDBIT_Pos 6 //0 No Card 1 Card Inserted #define SDIO_CR1_CDBIT_Msk (0x01 << SDIO_CR1_CDBIT_Pos) -#define SDIO_CR1_CDSRC_Pos 7 //Card Detect Source, 1 CR1.CDBIT娴ｏ拷 0 SD_Detect闁跨喐鏋婚幏鐑芥晸閺傘倖瀚� +#define SDIO_CR1_CDSRC_Pos 7 //Card Detect Source, 1 CR1.CDBIT位 0 SD_Detect引脚 #define SDIO_CR1_CDSRC_Msk (0x01 << SDIO_CR1_CDSRC_Pos) #define SDIO_CR1_PWRON_Pos 8 //1 Power on 0 Power off #define SDIO_CR1_PWRON_Msk (0x01 << SDIO_CR1_PWRON_Pos) @@ -1964,9 +2530,9 @@ typedef struct #define SDIO_CR2_CLKRDY_Msk (0x01 << SDIO_CR2_CLKRDY_Pos) #define SDIO_CR2_SDCLKEN_Pos 2 //SDCLK Enable #define SDIO_CR2_SDCLKEN_Msk (0x01 << SDIO_CR2_SDCLKEN_Pos) -#define SDIO_CR2_SDCLKDIV_Pos 8 //SDCLK Frequency Div, 0x00 闁跨喐鏋婚幏鐑芥晸閺傘倖瀚规０锟� 0x01 2闁跨喐鏋婚幏鐑筋暥 0x02 4闁跨喐鏋婚幏鐑筋暥 0x04 8闁跨喐鏋婚幏鐑筋暥 0x08 16闁跨喐鏋婚幏鐑筋暥 ... 0x80 256闁跨喐鏋婚幏鐑筋暥 +#define SDIO_CR2_SDCLKDIV_Pos 8 //SDCLK Frequency Div, 0x00 不分频 0x01 2分频 0x02 4分频 0x04 8分频 0x08 16分频 ... 0x80 256分频 #define SDIO_CR2_SDCLKDIV_Msk (0xFF << SDIO_CR2_SDCLKDIV_Pos) -#define SDIO_CR2_TIMEOUT_Pos 16 //0000 TMCLK*2^13 +#define SDIO_CR2_TIMEOUT_Pos 16 //0 TMCLK*2^13 1 TMCLK*2^14 ... 14 TMCLK*2^27 #define SDIO_CR2_TIMEOUT_Msk (0x0F << SDIO_CR2_TIMEOUT_Pos) #define SDIO_CR2_RSTALL_Pos 24 //Software Reset for All #define SDIO_CR2_RSTALL_Msk (0x01 << SDIO_CR2_RSTALL_Pos) @@ -2104,7 +2670,7 @@ typedef struct { __IO uint32_t DATA; __IO uint32_t ADDR; - __IO uint32_t ERASE; + __IO uint32_t SWM_ERASE; __IO uint32_t CACHE; __IO uint32_t CFG0; __IO uint32_t CFG1; @@ -2114,7 +2680,7 @@ typedef struct } FLASH_Typedef; #define FLASH_ERASE_REQ_Pos 31 -#define FLASH_ERASE_REQ_Msk ((uint32_t)0x01 << FLASH_ERASE_REQ_Pos) +#define FLASH_ERASE_REQ_Msk (0x01u << FLASH_ERASE_REQ_Pos) #define FLASH_CACHE_PROG_Pos 2 #define FLASH_CACHE_PROG_Msk (0x01 << FLASH_CACHE_PROG_Pos) @@ -2135,11 +2701,11 @@ typedef struct __IO uint32_t CR; } SRAMC_TypeDef; -#define SRAMC_CR_RWTIME_Pos 0 //闁跨喐鏋婚幏宄板晸闁跨喐鏋婚幏鐑芥晸閺傘倖瀚归柨鐔告灮閹风兘鏁撻弬銈嗗闁跨喐鏋婚幏鐑芥晸閸旑偊娼婚幏閿嬫闁跨喐鏋婚幏鐑芥晸閺傘倖瀚归柨鐔诲Ν閳藉懏瀚�0闁跨喐鏋婚幏椋庛仛1闁跨喐鏋婚幏閿嬫闁跨喐鏋婚幏鐑芥晸閺傘倖瀚归柨鐔诲Ν閳藉懏瀚归柨鐔告灮閹峰嘲鐨柨鐔告灮閹风兘鏁撻弬銈嗗娑擄拷4 +#define SRAMC_CR_RWTIME_Pos 0 //读写操作持续多少个时钟周期。0表示1个时钟周期。最小设置为4 #define SRAMC_CR_RWTIME_Msk (0x0F << SRAMC_CR_RWTIME_Pos) -#define SRAMC_CR_BYTEIF_Pos 4 //闁跨喕袙闁娍RAM闁跨喐鏋婚幏鐑芥晸閹瑰嘲灏呴幏鐑界伐闁跨噦鎷�0 16娴ｏ拷 1 8娴ｏ拷 +#define SRAMC_CR_BYTEIF_Pos 4 //外部SRAM数据宽度，0 16位 1 8位 #define SRAMC_CR_BYTEIF_Msk (0x01 << SRAMC_CR_BYTEIF_Pos) -#define SRAMC_CR_HBLBDIS_Pos 5 //1 ADDR[23:22]娑撴椽鏁撻弬銈嗗閸р偓闁跨喐鏋婚幏锟� 0 ADDR[23]娑撴椽鏁撻弬銈嗗闁跨喕顢滈弬銈嗗娴ｅ潡鏁撻弶甯秶閹风DDR[22]娑撴椽鏁撻弬銈嗗闁跨喕顢滈弬銈嗗娴ｅ潡鏁撻弬銈嗗 +#define SRAMC_CR_HBLBDIS_Pos 5 //1 ADDR[23:22]为地址线 0 ADDR[23]为高字节使能，ADDR[22]为低字节使能 #define SRAMC_CR_HBLBDIS_Msk (0x01 << SRAMC_CR_HBLBDIS_Pos) typedef struct @@ -2150,16 +2716,16 @@ typedef struct __IO uint32_t REFRESH; - __IO uint32_t NOPNUM; //[15:0] 闁跨喐鏋婚幏宄邦潗闁跨喐鏋婚幏鐑芥晸閺傘倖瀚归悵濠囨晸閺傘倖瀚归柨鐔告灮閹风兘鏁撻弬銈嗗闁跨喐鏋婚幏鐑芥晸閺傘倖瀚归柨鐔活敎椤旂偛搴滈幏鐑芥晸閺傘倖瀚归柨鐔告灮閹烽攱濮囬柨鐔告灮閹疯渹绻庨柨鐔虹ガOP闁跨喐鏋婚幏鐑芥晸閺傘倖瀚� + __IO uint32_t NOPNUM; //[15:0] 初始化完成后，在正常操作之前，发送多少个NOP命令 __IO uint32_t LATCH; - __IO uint32_t REFDONE; //[0] Frefresh Done闁跨喐鏋婚幏鐑芥晸鏉堝啰顣幏鐑芥晸缂佺偟銆嬮幏鐑芥晸閺傘倖瀚归柨鐔告灮閹凤拷 + __IO uint32_t REFDONE; //[0] Frefresh Done，上电初始化完成 } SDRAMC_TypeDef; -#define SDRAMC_CR0_BURSTLEN_Pos 0 //闁跨喐鏋婚幏鐑芥晸閺傘倖瀚归崣锟�2闁跨喐鏋婚幏鐑芥晸閺傘倖瀚圭粈绡塽rst Length娑擄拷4 +#define SDRAMC_CR0_BURSTLEN_Pos 0 //必须取2，表示Burst Length为4 #define SDRAMC_CR0_BURSTLEN_Msk (0x07 << SDRAMC_CR0_BURSTLEN_Pos) -#define SDRAMC_CR0_CASDELAY_Pos 4 //CAS Latency闁跨喐鏋婚幏锟� 2 2 3 3 +#define SDRAMC_CR0_CASDELAY_Pos 4 //CAS Latency， 2 2 3 3 #define SDRAMC_CR0_CASDELAY_Msk (0x07 << SDRAMC_CR0_CASDELAY_Pos) #define SDRAMC_CR1_TRP_Pos 0 @@ -2174,15 +2740,15 @@ typedef struct #define SDRAMC_CR1_TRRD_Msk (0x03 << SDRAMC_CR1_TRRD_Pos) #define SDRAMC_CR1_TMRD_Pos 15 #define SDRAMC_CR1_TMRD_Msk (0x07 << SDRAMC_CR1_TMRD_Pos) -#define SDRAMC_CR1_32BIT_Pos 18 //SDRAMC闁跨喍鑼庨幒銉ュ皡閹风兘鏁撻弬銈嗗闁跨喐鏋婚幏铚傜秴闁跨喐鏋婚幏锟�1 32bit 0 16bit +#define SDRAMC_CR1_32BIT_Pos 18 //SDRAMC的接口数据位宽，1 32bit 0 16bit #define SDRAMC_CR1_32BIT_Msk (0x01 << SDRAMC_CR1_32BIT_Pos) -#define SDRAMC_CR1_BANK_Pos 19 //SDRAM濮ｅ繘鏁撻弬銈嗗闁跨喐鏋婚幏鐑芥晸閺傘倖瀚归柨鐔峰建绾攱瀚归柨鐔告灮閹风⿰ank闁跨喐鏋婚幏锟�0 2 banks 1 4 banks +#define SDRAMC_CR1_BANK_Pos 19 //SDRAM每个颗粒有几个bank，0 2 banks 1 4 banks #define SDRAMC_CR1_BANK_Msk (0x01 << SDRAMC_CR1_BANK_Pos) -#define SDRAMC_CR1_CELL32BIT_Pos 20 //SDRAM闁跨喐鏋婚幏鐑芥晸閺傘倖瀚归柨鐔告灮閹疯渹缍呴柨鐔告灮閹凤拷1 32bit 0 16bit +#define SDRAMC_CR1_CELL32BIT_Pos 20 //SDRAM颗粒的位宽，1 32bit 0 16bit #define SDRAMC_CR1_CELL32BIT_Msk (0x01 << SDRAMC_CR1_CELL32BIT_Pos) -#define SDRAMC_CR1_CELLSIZE_Pos 21 //SDRAM闁跨喐鏋婚幏鐑芥晸閺傘倖瀚归柨鐔告灮閹风兘鏁撻弬銈嗗闁跨喐鏋婚幏鐑芥晸閺傘倖瀚�0 64Mb 1 128Mb 2 256Mb 3 16Mb +#define SDRAMC_CR1_CELLSIZE_Pos 21 //SDRAM颗粒的容量，0 64Mb 1 128Mb 2 256Mb 3 16Mb #define SDRAMC_CR1_CELLSIZE_Msk (0x03 << SDRAMC_CR1_CELLSIZE_Pos) -#define SDRAMC_CR1_HIGHSPEED_Pos 23 //闁跨喐鏋婚幏绌恈lk闁跨喐鏋婚幏鐑芥晸閺傘倖瀚�100MHz閺冨爼鏁撻弬銈嗗闁跨喐鏋婚幏铚傜娴ｅ秹鏁撻弬銈嗗闁跨喐鏋婚幏鐑芥晸閺傘倖瀚归柨鐔告灮閹疯渹璐�1闁跨喐鏋婚幏鐑芥晸閺傘倖瀚归柨鐔告灮閹疯渹璐�0 +#define SDRAMC_CR1_HIGHSPEED_Pos 23 //当hclk大于100MHz时，这一位必须配置为1，否则为0 #define SDRAMC_CR1_HIGHSPEED_Msk (0x01 << SDRAMC_CR1_HIGHSPEED_Pos) #define SDRAMC_REFRESH_RATE_Pos 0 @@ -2190,9 +2756,9 @@ typedef struct #define SDRAMC_REFRESH_EN_Pos 12 #define SDRAMC_REFRESH_EN_Msk (0x01 << SDRAMC_REFRESH_EN_Pos) -#define SDRAMC_LATCH_INEDGE_Pos 0 //闁跨喍鑼庨棃鈺傚闁跨喐鏋婚幏鐑芥晸閺傘倖瀚归柨鐔告灮閹风兘鏁撻弬銈嗗闁跨喓绁矰RAM闁跨喎褰ㄧ拋瑙勫闁跨喐鍩呯喊澶嬪闁跨喐鏋婚幏鐑芥晸閹瑰嚖缍囬幏锟�0 闁跨喐鏋婚幏鐑芥晸閺傘倖瀚归柨鐔告灮閹凤拷 1 闁跨喖鎽弬銈嗗闁跨喐鏋婚幏锟� +#define SDRAMC_LATCH_INEDGE_Pos 0 //哪个沿来锁存从SDRAM中读回的数据，0 上升沿 1 下降沿 #define SDRAMC_LATCH_INEDGE_Msk (0x01 << SDRAMC_LATCH_INEDGE_Pos) -#define SDRAMC_LATCH_OUTEDGE_Pos 1 //闁跨喍鑼庨棃鈺傚闁跨喐鏋婚幏宄板箵闁跨喐鏋婚幏鐑芥晸閺傘倖瀚归柨鐔煎徍闂堚晜瀚筍DRAM闁跨喐鏋婚幏鐑芥晸閺傘倖瀚归柨鐔稿祹閿濆繑瀚�1 闁跨喐鏋婚幏鐑芥晸閺傘倖瀚归柨鐔告灮閹凤拷 0 闁跨喖鎽弬銈嗗闁跨喐鏋婚幏锟� +#define SDRAMC_LATCH_OUTEDGE_Pos 1 //哪个沿去锁存送给SDRAM的数据，1 上升沿 0 下降沿 #define SDRAMC_LATCH_OUTEDGE_Msk (0x01 << SDRAMC_LATCH_OUTEDGE_Pos) #define SDRAMC_LATCH_WAITST_Pos 2 #define SDRAMC_LATCH_WAITST_Msk (0x01 << SDRAMC_LATCH_WAITST_Pos) @@ -2201,7 +2767,7 @@ typedef struct { __IO uint32_t IE; - __IO uint32_t IF; //閸愶拷1闁跨喐鏋婚幏鐑芥晸閺傘倖瀚� + __IO uint32_t IF; //写1清零 __IO uint32_t IM; @@ -2227,16 +2793,16 @@ typedef struct #define NORFLC_IM_TIMEOUT_Pos 1 #define NORFLC_IM_TIMEOUT_Msk (0x01 << NORFLC_IM_TIMEOUT_Pos) -#define NORFLC_CR_RDTIME_Pos 0 //Oen闁跨喖鎽弬銈嗗闁跨喐鍩呴悮瀛樺闁跨喐鏋婚幏铚傜箮闁跨喓绮搁幉瀣闁跨喐鏋婚幏鐑芥晸閺傘倖瀚圭拠銈夋晸閺傘倖瀚归柨鐔告灮閹风兘鏁撻弬銈嗗闁跨喐鍩呯喊澶嬪闁跨喐鏋婚幏鐑芥晸閹瑰皝妲勯幏锟�0闁跨喐鏋婚幏椋庛仛1闁跨喐鏋婚幏閿嬫闁跨喐鏋婚幏鐑芥晸閺傘倖瀚归柨鐔告灮閹凤拷 +#define NORFLC_CR_RDTIME_Pos 0 //Oen下降沿后多少个时钟周期后采样读回的数据。0表示1个时钟周期 #define NORFLC_CR_RDTIME_Msk (0x1F << NORFLC_CR_RDTIME_Pos) -#define NORFLC_CR_WRTIME_Pos 5 //闁跨喐鏋婚幏鐑芥晸缁插穲n闁跨喍鑼庢担搴ｎ暜閹峰嘲閽╅柨鐔告灮閹峰嘲褰囬柨鐕傛嫹0闁跨喐鏋婚幏椋庛仛1闁跨喐鏋婚幏閿嬫闁跨喐鏋婚幏鐑芥晸閺傘倖瀚归柨鐔告灮閹凤拷 +#define NORFLC_CR_WRTIME_Pos 5 //输出Wen的低电平宽度。0表示1个时钟周期 #define NORFLC_CR_WRTIME_Msk (0x07 << NORFLC_CR_WRTIME_Pos) -#define NORFLC_CR_BYTEIF_Pos 8 //闁跨喕袙闁垷OR FLASH闁跨喐鏋婚幏鐑芥晸閹瑰嘲灏呴幏鐑界伐闁跨噦鎷�1 8娴ｏ拷 0 16娴ｏ拷 +#define NORFLC_CR_BYTEIF_Pos 8 //外部NOR FLASH数据宽度，1 8位 0 16位 #define NORFLC_CR_BYTEIF_Msk (0x01 << NORFLC_CR_BYTEIF_Pos) -#define NORFLC_CMD_DATA_Pos 0 //闁跨喐鏋婚幏绋癛OGRAM闁跨喐鏋婚幏鐑芥晸閺傘倖瀚归柨鐔峰建閿濆繑瀚笵ATA闁跨喐鏋婚幏鐤洣閸愭瑩鏁撻弬銈嗗NOR FLASH闁跨喐鏋婚幏鐑芥晸閺傘倖瀚归柨鐔稿祹閿濆繑瀚归柨鐔告灮閹风úEAD闁跨喐鏋婚幏鐑芥晸閺傘倖瀚归柨鐔峰建閿濆繑瀚笵ATA闁跨喕顫楁潏鐐NOR FLASH闁跨喐鏋婚幏鐑芥晸閹搭亞顣幏鐑芥晸閺傘倖瀚归柨鐔告灮閹凤拷 +#define NORFLC_CMD_DATA_Pos 0 //在PROGRAM命令中，DATA是要写入NOR FLASH的数据；在READ命令中，DATA是从NOR FLASH读回的数据 #define NORFLC_CMD_DATA_Msk (0xFFFF << NORFLC_CMD_DATA_Pos) -#define NORFLC_CMD_CMD_Pos 16 //闁跨喐鏋婚幏鐤洣閹笛囨晸閸欘偆顣幏鐑芥晸閺傘倖瀚归柨鐔虹摂閿涳拷0 READ 1 RESET 2 AUTOMATIC SELECT 3 PROGRAM 4 CHIP ERASE 5 SECTOR ERASE +#define NORFLC_CMD_CMD_Pos 16 //需要执行的命令，0 READ 1 RESET 2 AUTOMATIC SELECT 3 PROGRAM 4 CHIP ERASE 5 SECTOR ERASE #define NORFLC_CMD_CMD_Msk (0x07 << NORFLC_CMD_CMD_Pos) typedef struct @@ -2252,42 +2818,42 @@ typedef struct #define CRC_CR_EN_Pos 0 #define CRC_CR_EN_Msk (0x01 << CRC_CR_EN_Pos) -#define CRC_CR_OREV_Pos 1 //闁跨喐鏋婚幏鐑芥晸閺傘倖瀚归柨鐔告灮閹风兘鏁撶憴鎺戝殩閹风柉娴� +#define CRC_CR_OREV_Pos 1 //输出结果是否翻转 #define CRC_CR_OREV_Msk (0x01 << CRC_CR_OREV_Pos) -#define CRC_CR_ONOT_Pos 2 //闁跨喐鏋婚幏鐑芥晸閺傘倖瀚归柨鐔告灮閹风兘鏁撶憴鎺戝殩閹峰嘲褰囬柨鐔告灮閹凤拷 +#define CRC_CR_ONOT_Pos 2 //输出结果是否取反 #define CRC_CR_ONOT_Msk (0x01 << CRC_CR_ONOT_Pos) #define CRC_CR_CRC16_Pos 3 //1 CRC16 0 CRC32 #define CRC_CR_CRC16_Msk (0x01 << CRC_CR_CRC16_Pos) -#define CRC_CR_IBITS_Pos 4 //闁跨喐鏋婚幏鐑芥晸閺傘倖瀚归柨鐔告灮閹风兘鏁撻弬銈嗗闁跨喐鏋婚幏閿嬫櫏娴ｅ秹鏁撻弬銈嗗 0 32娴ｏ拷 1 16娴ｏ拷 2 8娴ｏ拷 +#define CRC_CR_IBITS_Pos 4 //输入数据有效位数 0 32位 1 16位 2 8位 #define CRC_CR_IBITS_Msk (0x03 << CRC_CR_IBITS_Pos) typedef struct { - __IO uint32_t MINSEC; //闁跨喐鏋婚幏鐑芥晸閺傘倖瀚归柨鐔告灮閹风兘鏁撻敓锟� + __IO uint32_t MINSEC; //分秒计数 - __IO uint32_t DATHUR; //闁跨喐鏋婚幏閿嬫闁跨喐鏋婚幏鐑芥晸閺傘倖瀚� + __IO uint32_t DATHUR; //日时计数 - __IO uint32_t MONDAY; //闁跨喐鏋婚幏鐑芥晸閺夋壆銆嬮幏鐑芥晸閺傘倖瀚� + __IO uint32_t MONDAY; //月周计数 - __IO uint32_t YEAR; //[11:0] 闁跨喐鏋婚幏鐑芥晸閺傘倖瀚归柨鐔告灮閹风兘鏁撶悰妞﹀秵瀚归柨鐕傛嫹1901-2199 + __IO uint32_t YEAR; //[11:0] 年计数，支持1901-2199 - __IO uint32_t MINSECAL; //闁跨喐鏋婚幏鐑芥晸閺傘倖瀚归柨鐔告灮閹风兘鏁撻弬銈嗗闁跨喐鏋婚幏鐑芥晸閺傘倖瀚� + __IO uint32_t MINSECAL; //分秒闹铃设置 - __IO uint32_t DAYHURAL; //闁跨喐鏋婚幏閿嬫闁跨喐鏋婚幏鐑芥晸閺傘倖瀚归柨鐔告灮閹风兘鏁撻弬銈嗗 + __IO uint32_t DAYHURAL; //周时闹铃设置 - __IO uint32_t LOAD; //闁跨喐鏋婚幏鐑芥晸閺傘倖瀚归柨鐔虹叓鐎靛嫯鎻幏鐑芥晸閺傘倖瀚归柨鐔峰建绾板瀚归崐鐓庢倱闁跨喐鏋婚幏鐑芥晸閺傘倖瀚筊TC闁跨喎褰ㄩ敐蹇斿閸氬矂鏁撻弬銈嗗闁跨喐鏋婚幏鐑芥晸閺傘倖瀚规潻婊堟晸閺傘倖瀚归柨鐔告灮閹风兘鏁撻敓锟� + __IO uint32_t LOAD; //将设置寄存器中的值同步到RTC中，同步完成自动清零 __IO uint32_t IE; - __IO uint32_t IF; //閸愶拷1闁跨喐鏋婚幏鐑芥晸閺傘倖瀚� + __IO uint32_t IF; //写1清零 - __IO uint32_t EN; //[0] 1 RTC娴ｅ潡鏁撻弬銈嗗 + __IO uint32_t EN; //[0] 1 RTC使能 - __IO uint32_t CFGABLE; //[0] 1 RTC闁跨喐鏋婚幏鐑芥晸閺傘倖瀚归柨鐔告灮閹凤拷 + __IO uint32_t CFGABLE; //[0] 1 RTC可配置 - __IO uint32_t TRIM; //閺冨爼鏁撻幒銉ь暜閹风兘鏁撻弬銈嗗 + __IO uint32_t TRIM; //时钟调整 - __IO uint32_t TRIMM; //閺冨爼鏁撻弬銈嗗瀵邦噣鏁撻弬銈嗗闁跨喐鏋婚幏锟� + __IO uint32_t TRIMM; //时钟微调整 } RTC_TypeDef; #define RTC_LOAD_TIME_Pos 0 @@ -2295,44 +2861,44 @@ typedef struct #define RTC_LOAD_ALARM_Pos 1 #define RTC_LOAD_ALARM_Msk (0x01 << RTC_LOAD_ALARM_Pos) -#define RTC_MINSEC_SEC_Pos 0 //闁跨喐鏋婚幏鐑芥晸閺傘倖瀚归柨鐕傛嫹 +#define RTC_MINSEC_SEC_Pos 0 //秒计数，取值0--59 #define RTC_MINSEC_SEC_Msk (0x3F << RTC_MINSEC_SEC_Pos) -#define RTC_MINSEC_MIN_Pos 6 //闁跨喐鏋婚幏鐑芥晸閹恒儳銆嬮幏鐑芥晸閺傘倖瀚� +#define RTC_MINSEC_MIN_Pos 6 //分钟计数，取值0--59 #define RTC_MINSEC_MIN_Msk (0x3F << RTC_MINSEC_MIN_Pos) -#define RTC_DATHUR_HOUR_Pos 0 //鐏忓繑妞傞柨鐔告灮閹风兘鏁撻弬銈嗗 +#define RTC_DATHUR_HOUR_Pos 0 //小时计数，取值0--23 #define RTC_DATHUR_HOUR_Msk (0x1F << RTC_DATHUR_HOUR_Pos) -#define RTC_DATHUR_DATE_Pos 5 //date of month +#define RTC_DATHUR_DATE_Pos 5 //date of month，取值1--31 #define RTC_DATHUR_DATE_Msk (0x1F << RTC_DATHUR_DATE_Pos) -#define RTC_MONDAY_DAY_Pos 0 //day of week +#define RTC_MONDAY_DAY_Pos 0 //day of week，取值0--6 #define RTC_MONDAY_DAY_Msk (0x07 << RTC_MONDAY_DAY_Pos) -#define RTC_MONDAY_MON_Pos 3 //闁跨喖鎽禒鐣屻€嬮幏鐑芥晸閺傘倖瀚� +#define RTC_MONDAY_MON_Pos 3 //月份计数，取值1--12 #define RTC_MONDAY_MON_Msk (0x0F << RTC_MONDAY_MON_Pos) -#define RTC_MINSECAL_SEC_Pos 0 //闁跨喐鏋婚幏鐑芥晸閺傘倖瀚归柨鐔告灮閹风兘鏁撻弬銈嗗闁跨喐鏋婚幏锟� +#define RTC_MINSECAL_SEC_Pos 0 //闹钟秒设置 #define RTC_MINSECAL_SEC_Msk (0x3F << RTC_MINSECAL_SEC_Pos) -#define RTC_MINSECAL_MIN_Pos 6 //闁跨喐鏋婚幏鐑芥晸閹恒儱鍤栭幏鐑芥晸閺傘倖瀚归柨鐔告灮閹风兘鏁撻弬銈嗗 +#define RTC_MINSECAL_MIN_Pos 6 //闹钟分钟设置 #define RTC_MINSECAL_MIN_Msk (0x3F << RTC_MINSECAL_MIN_Pos) -#define RTC_DAYHURAL_HOUR_Pos 0 //闁跨喐鏋婚幏鐑芥晸閺傘倖瀚圭亸蹇旀闁跨喐鏋婚幏鐑芥晸閺傘倖瀚� +#define RTC_DAYHURAL_HOUR_Pos 0 //闹钟小时设置 #define RTC_DAYHURAL_HOUR_Msk (0x1F << RTC_DAYHURAL_HOUR_Pos) -#define RTC_DAYHURAL_SUN_Pos 5 //闁跨喐鏋婚幏鐑芥晸閺傘倖瀚归柨鐔告灮閹风兘鏁撻弬銈嗗闁跨喐鏋婚幏閿嬫櫏 +#define RTC_DAYHURAL_SUN_Pos 5 //周日闹钟有效 #define RTC_DAYHURAL_SUN_Msk (0x01 << RTC_DAYHURAL_SUN_Pos) -#define RTC_DAYHURAL_MON_Pos 6 //闁跨喐鏋婚幏铚傜闁跨喐鏋婚幏鐑芥晸閺傘倖瀚归柨鐔告灮閹烽攱鏅� +#define RTC_DAYHURAL_MON_Pos 6 //周一闹钟有效 #define RTC_DAYHURAL_MON_Msk (0x01 << RTC_DAYHURAL_MON_Pos) -#define RTC_DAYHURAL_TUE_Pos 7 //闁跨喐婢冪拋瑙勫闁跨喐鏋婚幏鐑芥晸閺傘倖瀚归柨鐔告灮閹烽攱鏅� +#define RTC_DAYHURAL_TUE_Pos 7 //周二闹钟有效 #define RTC_DAYHURAL_TUE_Msk (0x01 << RTC_DAYHURAL_TUE_Pos) -#define RTC_DAYHURAL_WED_Pos 8 //闁跨喐鏋婚幏鐑芥晸閺傘倖瀚归柨鐔告灮閹风兘鏁撻弬銈嗗闁跨喐鏋婚幏閿嬫櫏 +#define RTC_DAYHURAL_WED_Pos 8 //周三闹钟有效 #define RTC_DAYHURAL_WED_Msk (0x01 << RTC_DAYHURAL_WED_Pos) -#define RTC_DAYHURAL_THU_Pos 9 //闁跨喐鏋婚幏鐑芥晸閺傘倖瀚归柨鐔告灮閹风兘鏁撻弬銈嗗闁跨喐鏋婚幏閿嬫櫏 +#define RTC_DAYHURAL_THU_Pos 9 //周四闹钟有效 #define RTC_DAYHURAL_THU_Msk (0x01 << RTC_DAYHURAL_THU_Pos) -#define RTC_DAYHURAL_FRI_Pos 10 //闁跨喐鏋婚幏鐑芥晸閺傘倖瀚归柨鐔告灮閹风兘鏁撻弬銈嗗闁跨喐鏋婚幏閿嬫櫏 +#define RTC_DAYHURAL_FRI_Pos 10 //周五闹钟有效 #define RTC_DAYHURAL_FRI_Msk (0x01 << RTC_DAYHURAL_FRI_Pos) -#define RTC_DAYHURAL_SAT_Pos 11 //闁跨喐鏋婚幏鐑芥晸閺傘倖瀚归柨鐔告灮閹风兘鏁撻弬銈嗗闁跨喐鏋婚幏閿嬫櫏 +#define RTC_DAYHURAL_SAT_Pos 11 //周六闹钟有效 #define RTC_DAYHURAL_SAT_Msk (0x01 << RTC_DAYHURAL_SAT_Pos) -#define RTC_IE_SEC_Pos 0 //闁跨喐鏋婚幏鐑芥晸閸欘偉顔愰幏铚傚▏闁跨喐鏋婚幏锟� +#define RTC_IE_SEC_Pos 0 //秒中断使能 #define RTC_IE_SEC_Msk (0x01 << RTC_IE_SEC_Pos) #define RTC_IE_MIN_Pos 1 #define RTC_IE_MIN_Msk (0x01 << RTC_IE_MIN_Pos) @@ -2343,7 +2909,7 @@ typedef struct #define RTC_IE_ALARM_Pos 4 #define RTC_IE_ALARM_Msk (0x01 << RTC_IE_ALARM_Pos) -#define RTC_IF_SEC_Pos 0 //閸愶拷1闁跨喐鏋婚幏鐑芥晸閺傘倖瀚� +#define RTC_IF_SEC_Pos 0 //写1清零 #define RTC_IF_SEC_Msk (0x01 << RTC_IF_SEC_Pos) #define RTC_IF_MIN_Pos 1 #define RTC_IF_MIN_Msk (0x01 << RTC_IF_MIN_Pos) @@ -2354,28 +2920,28 @@ typedef struct #define RTC_IF_ALARM_Pos 4 #define RTC_IF_ALARM_Msk (0x01 << RTC_IF_ALARM_Pos) -#define RTC_TRIM_ADJ_Pos 0 //闁跨喐鏋婚幏鐑芥晸閼哄倻顣幏鐑芥晸閺傘倖瀚笲ASECNT闁跨喍鑼庣涵閿嬪闁跨喐鏋婚幏鐑芥晸閺傘倖瀚归柨鐔诲Ν閿濆繑瀚规姗€鏁撻弬銈嗗娑擄拷32768闁跨喐鏋婚幏鐑芥晸閺傘倖瀚归柨鐔烘たEC娑擄拷1闁跨喐鏋婚幏鐑芥晸閺傘倖瀚归柨鐔告灮閹风兘鏁撻弬銈嗗闁跨喐鏋婚幏鐤樁闁跨喐鏋婚幏鐑芥晸鏉炲尅鎷�32768-ADJ闁跨喐鏋婚幏鐑芥晸閺傘倖瀚归柨鐔告灮閹风兘鏁撻弬銈嗗闁跨喕濞囬敓锟�32768+ADJ +#define RTC_TRIM_ADJ_Pos 0 //用于调整BASECNT的计数周期，默认为32768，如果DEC为1，则计数周期调整为32768-ADJ，否则调整为32768+ADJ #define RTC_TRIM_ADJ_Msk (0xFF << RTC_TRIM_ADJ_Pos) #define RTC_TRIM_DEC_Pos 8 #define RTC_TRIM_DEC_Msk (0x01 << RTC_TRIM_DEC_Pos) -#define RTC_TRIMM_CYCLE_Pos 0 //闁跨喐鏋婚幏鐑芥晸閼哄倻銆嬮幏鐑芥晸閺傘倖瀚归柨鐔告灮閹风兘鏁撻弬銈嗗瀵邦噣鏁撻弬銈嗗闁跨喐鏋婚幏鐑芥晸閺傘倖瀚归柨鐔虹イNC娑擄拷1闁跨喐鏋婚幏鐑芥晸閺傘倖瀚归柨鐔哄崟闁跨喐鏋婚幏鐑芥晸閺傘倖瀚归柨鐔告灮閹风兘鏁撻弬銈嗗闁跨喕濡喊澶嬪闁跨喐鏋婚幏铚傝礋(32768闁跨喐鏋婚幏绋烡J)+1,闁跨喐鏋婚幏鐑芥晸閺傘倖瀚归柨鐔告灮閹风兘鏁撴潪鍖℃嫹(32768闁跨喐鏋婚幏绋烡J)-1 -//cycles=0閺冨爼鏁撻弬銈嗗闁跨喐鏋婚幏鐑芥晸閺傘倖瀚归柨鐔告灮閹峰嘲浜曢柨鐔告灮閹风兘鏁撻弬銈嗗闁跨喐鏋婚幏绌媦cles=1闁跨喐鏋婚幏鐑芥晸閺傘倖瀚筺娑擄拷2闁跨喐鏋婚幏绌媦cles=7闁跨喐鏋婚幏鐑芥晸閺傘倖瀚筺娑擄拷8闁跨喐鏋婚幏鐑芥晸閻ㄥ棜鎻幏鐑芥晸閺傘倖瀚归柨鐔告灮閹凤拷 +#define RTC_TRIMM_CYCLE_Pos 0 /* 用于计数周期微调，如果INC为1，则第n个计数周期调整为(32768±ADJ)+1,否则调整为(32768±ADJ)-1 \ + //cycles=0时，不进行微调整；cycles=1，则n为2；cycles=7，则n为8；以此类推 */ #define RTC_TRIMM_CYCLE_Msk (0x07 << RTC_TRIMM_CYCLE_Pos) #define RTC_TRIMM_INC_Pos 3 #define RTC_TRIMM_INC_Msk (0x01 << RTC_TRIMM_INC_Pos) typedef struct { - __IO uint32_t LOAD; //閸犲倿鏁撻弬銈嗗娴ｅ潡鏁撻弬銈嗗闁跨喐鏋婚幏鐑芥晸閺傘倖瀚圭憗鍛存晸閺傘倖瀚筁OAD閸婏拷 + __IO uint32_t LOAD; //喂狗使计数器装载LOAD值 __I uint32_t VALUE; __IO uint32_t CR; - __IO uint32_t IF; //闁跨喐鏋婚幏鐑芥晸閺傘倖瀚归柨鐔告灮閹凤拷0閺冨墎鈥栭柨鐔告灮閹风兘鏁撻弬銈嗗娴ｅ秹鏁撻弬銈嗗闁跨喐鏋婚幏鐑芥晸閸欘偓鎷�1闁跨喐鏋婚幏鐑芥晸閺傘倖瀚归柨鐔活敎閿燂拷 + __IO uint32_t IF; //计数到0时硬件置位，软件写1清除标志 - __IO uint32_t FEED; //閸愶拷0x55閸犲倿鏁撻弬銈嗗 + __IO uint32_t FEED; //写0x55喂狗 } WDT_TypeDef; #define WDT_CR_EN_Pos 0 @@ -2525,6 +3091,8 @@ typedef struct #define SDRAMC ((SDRAMC_TypeDef *)SDRAMC_BASE) +typedef void (*Func_void_void)(void); + #include "SWM320_port.h" #include "SWM320_gpio.h" #include "SWM320_exti.h" @@ -2541,6 +3109,7 @@ typedef struct #include "SWM320_flash.h" #include "SWM320_norflash.h" #include "SWM320_sdram.h" +#include "SWM320_sram.h" #include "SWM320_crc.h" #include "SWM320_rtc.h" #include "SWM320_wdt.h" diff --git a/bsp/swm320-lq100/Libraries/CMSIS/DeviceSupport/startup/arm/startup_SWM320.s b/bsp/swm320-lq100/Libraries/CMSIS/DeviceSupport/startup/arm/startup_SWM320.s index 025782b081..1a16ebc768 100644 --- a/bsp/swm320-lq100/Libraries/CMSIS/DeviceSupport/startup/arm/startup_SWM320.s +++ b/bsp/swm320-lq100/Libraries/CMSIS/DeviceSupport/startup/arm/startup_SWM320.s @@ -1,10 +1,10 @@ ;****************************************************************************************************************************************** -; ļ: startup_SWM2400.s -; ˵: SWM2400Ƭļ -; ֧: http://www.synwit.com.cn/e/tool/gbook/?bid=1 -; ע: -; 汾: V1.1.0 20171025 -; ¼: +; 文件名称: startup_SWM320.s +; 功能说明: SWM2400单片机的启动文件 +; 技术支持: http://www.synwit.com.cn/e/tool/gbook/?bid=1 +; 注意事项: +; 版本日期: V1.1.0 2017年10月25日 +; 升级记录: ; ; ;****************************************************************************************************************************************** @@ -25,7 +25,7 @@ ; Stack Size (in Bytes) <0x0-0xFFFFFFFF:8> ; -Stack_Size EQU 0x00000400 +Stack_Size EQU 0x00001000 AREA STACK, NOINIT, READWRITE, ALIGN=3 Stack_Mem SPACE Stack_Size @@ -36,7 +36,7 @@ __initial_sp ; Heap Size (in Bytes) <0x0-0xFFFFFFFF:8> ; -Heap_Size EQU 0x00000200 +Heap_Size EQU 0x00000000 AREA HEAP, NOINIT, READWRITE, ALIGN=3 __heap_base @@ -94,7 +94,7 @@ __Vectors DCD __initial_sp ; Top of Stack DCD GPIOC4_Handler DCD GPIOC5_Handler DCD GPIOC6_Handler - DCD GPIOC7_Handler + DCD GPIOC7_Handler DCD GPIOM0_Handler DCD GPIOM1_Handler DCD GPIOM2_Handler @@ -102,25 +102,25 @@ __Vectors DCD __initial_sp ; Top of Stack DCD GPIOM4_Handler DCD GPIOM5_Handler DCD GPIOM6_Handler - DCD GPIOM7_Handler - DCD DMA_Handler + DCD GPIOM7_Handler + DCD DMA_Handler DCD LCD_Handler DCD NORFLC_Handler - DCD CAN_Handler + DCD CAN_Handler DCD PULSE_Handler DCD WDT_Handler DCD PWM_Handler DCD UART0_Handler - DCD UART1_Handler - DCD UART2_Handler - DCD UART3_Handler - DCD 0 - DCD I2C0_Handler + DCD UART1_Handler + DCD UART2_Handler + DCD UART3_Handler + DCD 0 + DCD I2C0_Handler DCD I2C1_Handler DCD SPI0_Handler DCD ADC0_Handler DCD RTC_Handler - DCD ANAC_Handler + DCD BOD_Handler DCD SDIO_Handler DCD GPIOA_Handler DCD GPIOB_Handler @@ -130,13 +130,13 @@ __Vectors DCD __initial_sp ; Top of Stack DCD GPIOP_Handler DCD ADC1_Handler DCD FPU_Handler - DCD SPI1_Handler - DCD TIMR0_Handler - DCD TIMR1_Handler - DCD TIMR2_Handler - DCD TIMR3_Handler - DCD TIMR4_Handler - DCD TIMR5_Handler + DCD SPI1_Handler + DCD TIMR0_Handler + DCD TIMR1_Handler + DCD TIMR2_Handler + DCD TIMR3_Handler + DCD TIMR4_Handler + DCD TIMR5_Handler __Vectors_End @@ -157,262 +157,262 @@ Reset_Handler PROC ; Dummy Exception Handlers (infinite loops which can be modified) NMI_Handler PROC - EXPORT NMI_Handler [WEAK] + EXPORT NMI_Handler [WEAK] B . ENDP HardFault_Handler PROC - EXPORT HardFault_Handler [WEAK] + EXPORT HardFault_Handler [WEAK] B . ENDP MemManage_Handler PROC - EXPORT MemManage_Handler [WEAK] + EXPORT MemManage_Handler [WEAK] B . ENDP BusFault_Handler PROC - EXPORT BusFault_Handler [WEAK] + EXPORT BusFault_Handler [WEAK] B . ENDP UsageFault_Handler PROC - EXPORT UsageFault_Handler [WEAK] + EXPORT UsageFault_Handler [WEAK] B . ENDP SVC_Handler PROC - EXPORT SVC_Handler [WEAK] + EXPORT SVC_Handler [WEAK] B . ENDP DebugMon_Handler PROC - EXPORT DebugMon_Handler [WEAK] + EXPORT DebugMon_Handler [WEAK] B . ENDP PendSV_Handler PROC - EXPORT PendSV_Handler [WEAK] + EXPORT PendSV_Handler [WEAK] B . ENDP SysTick_Handler PROC - EXPORT SysTick_Handler [WEAK] + EXPORT SysTick_Handler [WEAK] B . ENDP GPIOA0_Handler PROC - EXPORT GPIOA0_Handler [WEAK] + EXPORT GPIOA0_Handler [WEAK] B . ENDP GPIOA1_Handler PROC - EXPORT GPIOA1_Handler [WEAK] + EXPORT GPIOA1_Handler [WEAK] B . ENDP GPIOA2_Handler PROC - EXPORT GPIOA2_Handler [WEAK] + EXPORT GPIOA2_Handler [WEAK] B . ENDP GPIOA3_Handler PROC - EXPORT GPIOA3_Handler [WEAK] + EXPORT GPIOA3_Handler [WEAK] B . ENDP GPIOA4_Handler PROC - EXPORT GPIOA4_Handler [WEAK] + EXPORT GPIOA4_Handler [WEAK] B . ENDP GPIOA5_Handler PROC - EXPORT GPIOA5_Handler [WEAK] + EXPORT GPIOA5_Handler [WEAK] B . ENDP GPIOA6_Handler PROC - EXPORT GPIOA6_Handler [WEAK] + EXPORT GPIOA6_Handler [WEAK] B . ENDP GPIOA7_Handler PROC - EXPORT GPIOA7_Handler [WEAK] + EXPORT GPIOA7_Handler [WEAK] B . ENDP GPIOB0_Handler PROC - EXPORT GPIOB0_Handler [WEAK] + EXPORT GPIOB0_Handler [WEAK] B . ENDP GPIOB1_Handler PROC - EXPORT GPIOB1_Handler [WEAK] + EXPORT GPIOB1_Handler [WEAK] B . ENDP GPIOB2_Handler PROC - EXPORT GPIOB2_Handler [WEAK] + EXPORT GPIOB2_Handler [WEAK] B . ENDP GPIOB3_Handler PROC - EXPORT GPIOB3_Handler [WEAK] + EXPORT GPIOB3_Handler [WEAK] B . ENDP GPIOB4_Handler PROC - EXPORT GPIOB4_Handler [WEAK] + EXPORT GPIOB4_Handler [WEAK] B . ENDP GPIOB5_Handler PROC - EXPORT GPIOB5_Handler [WEAK] + EXPORT GPIOB5_Handler [WEAK] B . ENDP GPIOB6_Handler PROC - EXPORT GPIOB6_Handler [WEAK] + EXPORT GPIOB6_Handler [WEAK] B . ENDP GPIOB7_Handler PROC - EXPORT GPIOB7_Handler [WEAK] + EXPORT GPIOB7_Handler [WEAK] B . ENDP GPIOC0_Handler PROC - EXPORT GPIOC0_Handler [WEAK] + EXPORT GPIOC0_Handler [WEAK] B . ENDP GPIOC1_Handler PROC - EXPORT GPIOC1_Handler [WEAK] + EXPORT GPIOC1_Handler [WEAK] B . ENDP GPIOC2_Handler PROC - EXPORT GPIOC2_Handler [WEAK] + EXPORT GPIOC2_Handler [WEAK] B . ENDP GPIOC3_Handler PROC - EXPORT GPIOC3_Handler [WEAK] + EXPORT GPIOC3_Handler [WEAK] B . ENDP GPIOC4_Handler PROC - EXPORT GPIOC4_Handler [WEAK] + EXPORT GPIOC4_Handler [WEAK] B . ENDP GPIOC5_Handler PROC - EXPORT GPIOC5_Handler [WEAK] + EXPORT GPIOC5_Handler [WEAK] B . ENDP GPIOC6_Handler PROC - EXPORT GPIOC6_Handler [WEAK] + EXPORT GPIOC6_Handler [WEAK] B . ENDP GPIOC7_Handler PROC - EXPORT GPIOC7_Handler [WEAK] + EXPORT GPIOC7_Handler [WEAK] B . ENDP GPIOM0_Handler PROC - EXPORT GPIOM0_Handler [WEAK] + EXPORT GPIOM0_Handler [WEAK] B . ENDP GPIOM1_Handler PROC - EXPORT GPIOM1_Handler [WEAK] + EXPORT GPIOM1_Handler [WEAK] B . ENDP GPIOM2_Handler PROC - EXPORT GPIOM2_Handler [WEAK] + EXPORT GPIOM2_Handler [WEAK] B . ENDP GPIOM3_Handler PROC - EXPORT GPIOM3_Handler [WEAK] + EXPORT GPIOM3_Handler [WEAK] B . ENDP GPIOM4_Handler PROC - EXPORT GPIOM4_Handler [WEAK] + EXPORT GPIOM4_Handler [WEAK] B . ENDP GPIOM5_Handler PROC - EXPORT GPIOM5_Handler [WEAK] + EXPORT GPIOM5_Handler [WEAK] B . ENDP GPIOM6_Handler PROC - EXPORT GPIOM6_Handler [WEAK] + EXPORT GPIOM6_Handler [WEAK] B . ENDP GPIOM7_Handler PROC - EXPORT GPIOM7_Handler [WEAK] + EXPORT GPIOM7_Handler [WEAK] B . ENDP DMA_Handler PROC - EXPORT DMA_Handler [WEAK] + EXPORT DMA_Handler [WEAK] B . ENDP LCD_Handler PROC - EXPORT LCD_Handler [WEAK] + EXPORT LCD_Handler [WEAK] B . ENDP NORFLC_Handler PROC - EXPORT NORFLC_Handler [WEAK] + EXPORT NORFLC_Handler [WEAK] B . ENDP CAN_Handler PROC - EXPORT CAN_Handler [WEAK] + EXPORT CAN_Handler [WEAK] B . ENDP PULSE_Handler PROC - EXPORT PULSE_Handler [WEAK] + EXPORT PULSE_Handler [WEAK] B . ENDP WDT_Handler PROC - EXPORT WDT_Handler [WEAK] + EXPORT WDT_Handler [WEAK] B . ENDP PWM_Handler PROC - EXPORT PWM_Handler [WEAK] + EXPORT PWM_Handler [WEAK] B . ENDP UART0_Handler PROC - EXPORT UART0_Handler [WEAK] + EXPORT UART0_Handler [WEAK] B . ENDP UART1_Handler PROC - EXPORT UART1_Handler [WEAK] + EXPORT UART1_Handler [WEAK] B . ENDP UART2_Handler PROC - EXPORT UART2_Handler [WEAK] + EXPORT UART2_Handler [WEAK] B . ENDP UART3_Handler PROC - EXPORT UART3_Handler [WEAK] + EXPORT UART3_Handler [WEAK] B . ENDP @@ -437,12 +437,12 @@ ADC0_Handler PROC ENDP RTC_Handler PROC - EXPORT RTC_Handler [WEAK] + EXPORT RTC_Handler [WEAK] B . ENDP -ANAC_Handler PROC - EXPORT ANAC_Handler [WEAK] +BOD_Handler PROC + EXPORT BOD_Handler [WEAK] B . ENDP @@ -452,32 +452,32 @@ SDIO_Handler PROC ENDP GPIOA_Handler PROC - EXPORT GPIOA_Handler [WEAK] + EXPORT GPIOA_Handler [WEAK] B . ENDP GPIOB_Handler PROC - EXPORT GPIOB_Handler [WEAK] + EXPORT GPIOB_Handler [WEAK] B . ENDP GPIOC_Handler PROC - EXPORT GPIOC_Handler [WEAK] + EXPORT GPIOC_Handler [WEAK] B . ENDP GPIOM_Handler PROC - EXPORT GPIOM_Handler [WEAK] + EXPORT GPIOM_Handler [WEAK] B . ENDP GPION_Handler PROC - EXPORT GPION_Handler [WEAK] + EXPORT GPION_Handler [WEAK] B . ENDP GPIOP_Handler PROC - EXPORT GPIOP_Handler [WEAK] + EXPORT GPIOP_Handler [WEAK] B . ENDP @@ -487,7 +487,7 @@ ADC1_Handler PROC ENDP FPU_Handler PROC - EXPORT FPU_Handler [WEAK] + EXPORT FPU_Handler [WEAK] B . ENDP diff --git a/bsp/swm320-lq100/Libraries/CMSIS/DeviceSupport/startup/iar/startup_SWM320.s b/bsp/swm320-lq100/Libraries/CMSIS/DeviceSupport/startup/iar/startup_SWM320.s index baecc70d02..a7a4d89f50 100644 --- a/bsp/swm320-lq100/Libraries/CMSIS/DeviceSupport/startup/iar/startup_SWM320.s +++ b/bsp/swm320-lq100/Libraries/CMSIS/DeviceSupport/startup/iar/startup_SWM320.s @@ -57,7 +57,7 @@ __vector_table DCD GPIOA5_Handler DCD GPIOA6_Handler DCD GPIOA7_Handler - DCD GPIOB0_Handler + DCD GPIOB0_Handler DCD GPIOB1_Handler DCD GPIOB2_Handler DCD GPIOB3_Handler @@ -72,7 +72,7 @@ __vector_table DCD GPIOC4_Handler DCD GPIOC5_Handler DCD GPIOC6_Handler - DCD GPIOC7_Handler + DCD GPIOC7_Handler DCD GPIOM0_Handler DCD GPIOM1_Handler DCD GPIOM2_Handler @@ -80,25 +80,25 @@ __vector_table DCD GPIOM4_Handler DCD GPIOM5_Handler DCD GPIOM6_Handler - DCD GPIOM7_Handler - DCD DMA_Handler + DCD GPIOM7_Handler + DCD DMA_Handler DCD LCD_Handler DCD NORFLC_Handler - DCD CAN_Handler - DCD TIMR_Handler + DCD CAN_Handler + DCD PULSE_Handler DCD WDT_Handler DCD PWM_Handler DCD UART0_Handler - DCD UART1_Handler - DCD UART2_Handler - DCD UART3_Handler - DCD 0 - DCD I2C0_Handler + DCD UART1_Handler + DCD UART2_Handler + DCD UART3_Handler + DCD 0 + DCD I2C0_Handler DCD I2C1_Handler DCD SPI0_Handler DCD ADC0_Handler DCD RTC_Handler - DCD ANAC_Handler + DCD BOD_Handler DCD SDIO_Handler DCD GPIOA_Handler DCD GPIOB_Handler @@ -108,7 +108,13 @@ __vector_table DCD GPIOP_Handler DCD ADC1_Handler DCD FPU_Handler - DCD SPI1_Handler + DCD SPI1_Handler + DCD TIMR0_Handler + DCD TIMR1_Handler + DCD TIMR2_Handler + DCD TIMR3_Handler + DCD TIMR4_Handler + DCD TIMR5_Handler THUMB @@ -345,10 +351,10 @@ NORFLC_Handler CAN_Handler B CAN_Handler - PUBWEAK TIMR_Handler + PUBWEAK PULSE_Handler SECTION .text:CODE:REORDER:NOROOT(1) -TIMR_Handler - B TIMR_Handler +PULSE_Handler + B PULSE_Handler PUBWEAK WDT_Handler SECTION .text:CODE:REORDER:NOROOT(1) @@ -405,10 +411,10 @@ ADC0_Handler RTC_Handler B RTC_Handler - PUBWEAK ANAC_Handler + PUBWEAK BOD_Handler SECTION .text:CODE:REORDER:NOROOT(1) -ANAC_Handler - B ANAC_Handler +BOD_Handler + B BOD_Handler PUBWEAK SDIO_Handler SECTION .text:CODE:REORDER:NOROOT(1) @@ -459,6 +465,36 @@ FPU_Handler SECTION .text:CODE:REORDER:NOROOT(1) SPI1_Handler B SPI1_Handler + + PUBWEAK TIMR0_Handler + SECTION .text:CODE:REORDER:NOROOT(1) +TIMR0_Handler + B TIMR0_Handler + + PUBWEAK TIMR1_Handler + SECTION .text:CODE:REORDER:NOROOT(1) +TIMR1_Handler + B TIMR1_Handler + + PUBWEAK TIMR2_Handler + SECTION .text:CODE:REORDER:NOROOT(1) +TIMR2_Handler + B TIMR2_Handler + + PUBWEAK TIMR3_Handler + SECTION .text:CODE:REORDER:NOROOT(1) +TIMR3_Handler + B TIMR3_Handler + + PUBWEAK TIMR4_Handler + SECTION .text:CODE:REORDER:NOROOT(1) +TIMR4_Handler + B TIMR4_Handler + + PUBWEAK TIMR5_Handler + SECTION .text:CODE:REORDER:NOROOT(1) +TIMR5_Handler + B TIMR5_Handler END diff --git a/bsp/swm320-lq100/Libraries/CMSIS/DeviceSupport/system_SWM320.c b/bsp/swm320-lq100/Libraries/CMSIS/DeviceSupport/system_SWM320.c index d6e7c61809..578d15da79 100644 --- a/bsp/swm320-lq100/Libraries/CMSIS/DeviceSupport/system_SWM320.c +++ b/bsp/swm320-lq100/Libraries/CMSIS/DeviceSupport/system_SWM320.c @@ -38,14 +38,15 @@ #define SYS_CLK_DIV SYS_CLK_DIV_1 #define __HSI (20000000UL) //高速内部时钟 -#define __LSI (32000UL) //低速内部时钟 +#define __LSI (32000UL) //低速内部时钟 #define __HSE (20000000UL) //高速外部时钟 /********************************** PLL 设定 ********************************************** * VCO输出频率 = PLL输入时钟 / INDIV * 4 * FBDIV * PLL输出频率 = PLL输入时钟 / INDIV * 4 * FBDIV / OUTDIV = VCO输出频率 / OUTDIV + * 注意：VCO输出频率需要在 [600MHz, 1200MHz] 之间 *****************************************************************************************/ -#define SYS_PLL_SRC SYS_CLK_XTAL //可取值SYS_CLK_20MHz、SYS_CLK_XTAL +#define SYS_PLL_SRC SYS_CLK_20MHz //可取值SYS_CLK_20MHz、SYS_CLK_XTAL #define PLL_IN_DIV 5 @@ -57,8 +58,8 @@ #define PLL_OUT_DIV PLL_OUT_DIV8 -uint32_t SystemCoreClock = (120000000UL); //System Clock Frequency (Core Clock) -uint32_t CyclesPerUs = ((120000000UL) / 1000000); //Cycles per micro second +uint32_t SystemCoreClock = __HSI; //System Clock Frequency (Core Clock) +uint32_t CyclesPerUs = (__HSI / 1000000); //Cycles per micro second /****************************************************************************************************************************************** * 函数名称: @@ -110,6 +111,8 @@ void SystemCoreClockUpdate(void) if (SYS->CLKDIV & SYS_CLKDIV_SYS_Msk) SystemCoreClock /= 2; + + CyclesPerUs = SystemCoreClock / 1000000; } /****************************************************************************************************************************************** @@ -121,56 +124,30 @@ void SystemCoreClockUpdate(void) ******************************************************************************************************************************************/ void SystemInit(void) { - uint32_t i; - SYS->CLKEN |= (1 << SYS_CLKEN_ANAC_Pos); + Flash_Param_at_xMHz(120); + switch (SYS_CLK) { case SYS_CLK_20MHz: //0 内部高频20MHz RC振荡器 - SYS->HRCCR = (0 << SYS_HRCCR_OFF_Pos) | - (0 << SYS_HRCCR_DBL_Pos); //HRC = 20MHz - - SYS->CLKSEL &= ~SYS_CLKSEL_HFCK_Msk; //HFCK <= HRC - SYS->CLKSEL |= (1 << SYS_CLKSEL_SYS_Pos); //SYS_CLK <= HFCK + switchCLK_20MHz(); break; case SYS_CLK_40MHz: //1 内部高频40MHz RC振荡器 - SYS->HRCCR = (0 << SYS_HRCCR_OFF_Pos) | - (1 << SYS_HRCCR_DBL_Pos); //HRC = 40MHz - - SYS->CLKSEL &= ~SYS_CLKSEL_HFCK_Msk; //HFCK <= HRC - SYS->CLKSEL |= (1 << SYS_CLKSEL_SYS_Pos); //SYS_CLK <= HFCK + switchCLK_40MHz(); break; case SYS_CLK_32KHz: //2 内部低频32KHz RC振荡器 - SYS->CLKEN |= (1 << SYS_CLKEN_RTCBKP_Pos); - - SYS->LRCCR &= ~(1 << SYS_LRCCR_OFF_Pos); - - for (i = 0; i < 20000; i++) - ; - - SYS->CLKSEL &= ~SYS_CLKSEL_LFCK_Msk; //LFCK <= LRC - SYS->CLKSEL &= ~SYS_CLKSEL_SYS_Msk; //SYS_CLK <= LFCK + switchCLK_32KHz(); break; case SYS_CLK_XTAL: //3 外部晶体振荡器（2-30MHz） - SYS->XTALCR = (1 << SYS_XTALCR_EN_Pos); - - for (i = 0; i < 20000; i++) - ; - - SYS->CLKSEL |= (1 << SYS_CLKSEL_HFCK_Pos); //HFCK <= XTAL - SYS->CLKSEL |= (1 << SYS_CLKSEL_SYS_Pos); //SYS_CLK <= HFCK + switchCLK_XTAL(); break; case SYS_CLK_PLL: //4 片内锁相环输出 - PLLInit(); - SYS->PLLCR |= (1 << SYS_PLLCR_OUTEN_Pos); - - SYS->CLKSEL |= (1 << SYS_CLKSEL_LFCK_Pos); //LFCK <= PLL - SYS->CLKSEL &= ~SYS_CLKSEL_SYS_Msk; //SYS_CLK <= LFCK + switchCLK_PLL(); break; } @@ -178,25 +155,114 @@ void SystemInit(void) SYS->CLKDIV |= (SYS_CLK_DIV << SYS_CLKDIV_SYS_Pos); SystemCoreClockUpdate(); + + if (SystemCoreClock > 80000000) + { + Flash_Param_at_xMHz(120); + } + else if (SystemCoreClock > 40000000) + { + Flash_Param_at_xMHz(80); + } + else if (SystemCoreClock > 30000000) + { + Flash_Param_at_xMHz(40); + } + else + { + Flash_Param_at_xMHz(30); + } } -void PLLInit(void) +static void delay_3ms(void) { uint32_t i; + if (((SYS->CLKSEL & SYS_CLKSEL_SYS_Msk) == 0) && + ((SYS->CLKSEL & SYS_CLKSEL_LFCK_Msk) == 0)) //32KHz + { + for (i = 0; i < 20; i++) + __NOP(); + } + else + { + for (i = 0; i < 20000; i++) + __NOP(); + } +} + +void switchCLK_20MHz(void) +{ + SYS->HRCCR = (0 << SYS_HRCCR_OFF_Pos) | + (0 << SYS_HRCCR_DBL_Pos); //HRC = 20MHz + + delay_3ms(); + + SYS->CLKSEL &= ~SYS_CLKSEL_HFCK_Msk; //HFCK <= HRC + SYS->CLKSEL |= (1 << SYS_CLKSEL_SYS_Pos); //SYS_CLK <= HFCK +} + +void switchCLK_40MHz(void) +{ + SYS->HRCCR = (0 << SYS_HRCCR_OFF_Pos) | + (1 << SYS_HRCCR_DBL_Pos); //HRC = 40MHz + + delay_3ms(); + + SYS->CLKSEL &= ~SYS_CLKSEL_HFCK_Msk; //HFCK <= HRC + SYS->CLKSEL |= (1 << SYS_CLKSEL_SYS_Pos); //SYS_CLK <= HFCK +} + +void switchCLK_32KHz(void) +{ + SYS->CLKEN |= (1 << SYS_CLKEN_RTCBKP_Pos); + + SYS->LRCCR &= ~(1 << SYS_LRCCR_OFF_Pos); + + delay_3ms(); + + SYS->CLKSEL &= ~SYS_CLKSEL_LFCK_Msk; //LFCK <= LRC + SYS->CLKSEL &= ~SYS_CLKSEL_SYS_Msk; //SYS_CLK <= LFCK +} + +void switchCLK_XTAL(void) +{ + SYS->XTALCR = (1 << SYS_XTALCR_EN_Pos); + + delay_3ms(); + delay_3ms(); + + SYS->CLKSEL |= (1 << SYS_CLKSEL_HFCK_Pos); //HFCK <= XTAL + SYS->CLKSEL |= (1 << SYS_CLKSEL_SYS_Pos); //SYS_CLK <= HFCK +} + +void switchCLK_PLL(void) +{ + PLLInit(); + + SYS->PLLCR |= (1 << SYS_PLLCR_OUTEN_Pos); + + SYS->CLKSEL |= (1 << SYS_CLKSEL_LFCK_Pos); //LFCK <= PLL + SYS->CLKSEL &= ~SYS_CLKSEL_SYS_Msk; //SYS_CLK <= LFCK +} + +void PLLInit(void) +{ if (SYS_PLL_SRC == SYS_CLK_20MHz) { SYS->HRCCR = (0 << SYS_HRCCR_OFF_Pos) | (0 << SYS_HRCCR_DBL_Pos); //HRC = 20MHz + delay_3ms(); + SYS->PLLCR |= (1 << SYS_PLLCR_INSEL_Pos); //PLL_SRC <= HRC } else if (SYS_PLL_SRC == SYS_CLK_XTAL) { SYS->XTALCR = (1 << SYS_XTALCR_EN_Pos); - for (i = 0; i < 20000; i++) - ; + delay_3ms(); + delay_3ms(); SYS->PLLCR &= ~(1 << SYS_PLLCR_INSEL_Pos); //PLL_SRC <= XTAL } diff --git a/bsp/swm320-lq100/Libraries/CMSIS/DeviceSupport/system_SWM320.h b/bsp/swm320-lq100/Libraries/CMSIS/DeviceSupport/system_SWM320.h index 4f44ccd3ab..4db7f29433 100644 --- a/bsp/swm320-lq100/Libraries/CMSIS/DeviceSupport/system_SWM320.h +++ b/bsp/swm320-lq100/Libraries/CMSIS/DeviceSupport/system_SWM320.h @@ -2,20 +2,24 @@ #define __SYSTEM_SWM320_H__ #ifdef __cplusplus -extern "C" { +extern "C" +{ #endif + extern uint32_t SystemCoreClock; // System Clock Frequency (Core Clock) + extern uint32_t CyclesPerUs; // Cycles per micro second -extern uint32_t SystemCoreClock; // System Clock Frequency (Core Clock) -extern uint32_t CyclesPerUs; // Cycles per micro second + extern void SystemInit(void); + extern void SystemCoreClockUpdate(void); -extern void SystemInit(void); - -extern void SystemCoreClockUpdate(void); - -extern void PLLInit(void); + extern void switchCLK_20MHz(void); + extern void switchCLK_40MHz(void); + extern void switchCLK_32KHz(void); + extern void switchCLK_XTAL(void); + extern void switchCLK_PLL(void); + extern void PLLInit(void); #ifdef __cplusplus } diff --git a/bsp/swm320-lq100/Libraries/SWM320_StdPeriph_Driver/SWM320_adc.c b/bsp/swm320-lq100/Libraries/SWM320_StdPeriph_Driver/SWM320_adc.c index d6c48b10d4..0fcd4d1eb1 100644 --- a/bsp/swm320-lq100/Libraries/SWM320_StdPeriph_Driver/SWM320_adc.c +++ b/bsp/swm320-lq100/Libraries/SWM320_StdPeriph_Driver/SWM320_adc.c @@ -22,7 +22,7 @@ /****************************************************************************************************************************************** * 函数名称: ADC_Init() * 功能说明: ADC模数转换器初始化 -* 输 入: ADC_TypeDef * ADCx 指定要被设置的ADC，有效值包括ADC0、ADC1 +* 输 入: ADC_TypeDef * ADCx 指定要被设置的ADC，有效值包括ADC0、ADC1 * ADC_InitStructure * initStruct 包含ADC各相关定值的结构体 * 输 出: 无 * 注意事项: 无 @@ -63,9 +63,12 @@ void ADC_Init(ADC_TypeDef *ADCx, ADC_InitStructure *initStruct) SYS->PLLDIV |= (initStruct->clk_div << SYS_PLLDIV_ADDIV_Pos); } + ADCx->CALIBSET = (ADCx == ADC0) ? SYS->BKP[0] : SYS->BKP[1]; + ADCx->CALIBEN = (1 << ADC_CALIBEN_OFFSET_Pos) | (1 << ADC_CALIBEN_K_Pos); + ADCx->CTRL2 &= ~(ADC_CTRL2_ADCEVCM_Msk | ADC_CTRL2_PGAIVCM_Msk | ADC_CTRL2_PGAGAIN_Msk | ADC_CTRL2_PGAVCM_Msk); ADCx->CTRL2 |= (0 << ADC_CTRL2_ADCEVCM_Pos) | - (PGA_VCM_INTERNAL << ADC_CTRL2_PGAIVCM_Pos) | + (initStruct->pga_ref << ADC_CTRL2_PGAIVCM_Pos) | (6 << ADC_CTRL2_PGAGAIN_Pos) | ((uint32_t)6 << ADC_CTRL2_PGAVCM_Pos); @@ -152,7 +155,7 @@ void ADC_Init(ADC_TypeDef *ADCx, ADC_InitStructure *initStruct) /****************************************************************************************************************************************** * 函数名称: ADC_Open() * 功能说明: ADC开启，可以软件启动、或硬件触发ADC转换 -* 输 入: ADC_TypeDef * ADCx 指定要被设置的ADC，可取值包括ADC +* 输 入: ADC_TypeDef * ADCx 指定要被设置的ADC，可取值包括ADC * 输 出: 无 * 注意事项: 无 ******************************************************************************************************************************************/ @@ -164,7 +167,7 @@ void ADC_Open(ADC_TypeDef *ADCx) /****************************************************************************************************************************************** * 函数名称: ADC_Close() * 功能说明: ADC关闭，无法软件启动、或硬件触发ADC转换 -* 输 入: ADC_TypeDef * ADCx 指定要被设置的ADC，可取值包括ADC +* 输 入: ADC_TypeDef * ADCx 指定要被设置的ADC，可取值包括ADC * 输 出: 无 * 注意事项: 无 ******************************************************************************************************************************************/ @@ -176,7 +179,7 @@ void ADC_Close(ADC_TypeDef *ADCx) /****************************************************************************************************************************************** * 函数名称: ADC_Start() * 功能说明: 软件触发模式下启动ADC转换 -* 输 入: ADC_TypeDef * ADCx 指定要被设置的ADC，可取值包括ADC +* 输 入: ADC_TypeDef * ADCx 指定要被设置的ADC，可取值包括ADC * 输 出: 无 * 注意事项: 无 ******************************************************************************************************************************************/ @@ -188,7 +191,7 @@ void ADC_Start(ADC_TypeDef *ADCx) /****************************************************************************************************************************************** * 函数名称: ADC_Stop() * 功能说明: 软件触发模式下停止ADC转换 -* 输 入: ADC_TypeDef * ADCx 指定要被设置的ADC，可取值包括ADC +* 输 入: ADC_TypeDef * ADCx 指定要被设置的ADC，可取值包括ADC * 输 出: 无 * 注意事项: 无 ******************************************************************************************************************************************/ @@ -235,9 +238,9 @@ static uint32_t chn2idx(uint32_t chn) /****************************************************************************************************************************************** * 函数名称: ADC_Read() * 功能说明: 从指定通道读取转换结果 -* 输 入: ADC_TypeDef * ADCx 指定要被设置的ADC，可取值包括ADC +* 输 入: ADC_TypeDef * ADCx 指定要被设置的ADC，可取值包括ADC * uint32_t chn 要读取转换结果的通道，有效值ADC_CH0、ADC_CH1、... ... 、ADC_CH7 -* 输 出: uint32_t 读取到的转换结果 +* 输 出: uint32_t 读取到的转换结果 * 注意事项: 无 ******************************************************************************************************************************************/ uint32_t ADC_Read(ADC_TypeDef *ADCx, uint32_t chn) @@ -255,9 +258,9 @@ uint32_t ADC_Read(ADC_TypeDef *ADCx, uint32_t chn) /****************************************************************************************************************************************** * 函数名称: ADC_IsEOC() * 功能说明: 指定通道是否End Of Conversion -* 输 入: ADC_TypeDef * ADCx 指定要被设置的ADC，可取值包括ADC +* 输 入: ADC_TypeDef * ADCx 指定要被设置的ADC，可取值包括ADC * uint32_t chn 要查询状态的通道，有效值ADC_CH0、ADC_CH1、... ... 、ADC_CH7 -* 输 出: uint32_t 1 该通道完成了转换 0 该通道未完成转换 +* 输 出: uint32_t 1 该通道完成了转换 0 该通道未完成转换 * 注意事项: 无 ******************************************************************************************************************************************/ uint32_t ADC_IsEOC(ADC_TypeDef *ADCx, uint32_t chn) @@ -270,7 +273,7 @@ uint32_t ADC_IsEOC(ADC_TypeDef *ADCx, uint32_t chn) /****************************************************************************************************************************************** * 函数名称: ADC_ChnSelect() * 功能说明: ADC通道选通，模数转换会在选通的通道上依次采样转换 -* 输 入: ADC_TypeDef * ADCx 指定要被设置的ADC，可取值包括ADC +* 输 入: ADC_TypeDef * ADCx 指定要被设置的ADC，可取值包括ADC * uint32_t chns 要选通的通道，有效值ADC_CH0、ADC_CH1、... ... 、ADC_CH7及其组合（即“按位或”运算） * 输 出: 无 * 注意事项: 无 @@ -284,7 +287,7 @@ void ADC_ChnSelect(ADC_TypeDef *ADCx, uint32_t chns) /****************************************************************************************************************************************** * 函数名称: ADC_IntEOCEn() * 功能说明: 转换完成中断使能 -* 输 入: ADC_TypeDef * ADCx 指定要被设置的ADC，可取值包括ADC +* 输 入: ADC_TypeDef * ADCx 指定要被设置的ADC，可取值包括ADC * uint32_t chn 要设置的通道，有效值ADC_CH0、ADC_CH1、... ... 、ADC_CH7 * 输 出: 无 * 注意事项: 无 @@ -299,7 +302,7 @@ void ADC_IntEOCEn(ADC_TypeDef *ADCx, uint32_t chn) /****************************************************************************************************************************************** * 函数名称: ADC_IntEOCDis() * 功能说明: 转换完成中断禁止 -* 输 入: ADC_TypeDef * ADCx 指定要被设置的ADC，可取值包括ADC +* 输 入: ADC_TypeDef * ADCx 指定要被设置的ADC，可取值包括ADC * uint32_t chn 要设置的通道，有效值ADC_CH0、ADC_CH1、... ... 、ADC_CH7 * 输 出: 无 * 注意事项: 无 @@ -314,7 +317,7 @@ void ADC_IntEOCDis(ADC_TypeDef *ADCx, uint32_t chn) /****************************************************************************************************************************************** * 函数名称: ADC_IntEOCClr() * 功能说明: 转换完成中断标志清除 -* 输 入: ADC_TypeDef * ADCx 指定要被设置的ADC，可取值包括ADC +* 输 入: ADC_TypeDef * ADCx 指定要被设置的ADC，可取值包括ADC * uint32_t chn 要设置的通道，有效值ADC_CH0、ADC_CH1、... ... 、ADC_CH7 * 输 出: 无 * 注意事项: 无 @@ -329,9 +332,9 @@ void ADC_IntEOCClr(ADC_TypeDef *ADCx, uint32_t chn) /****************************************************************************************************************************************** * 函数名称: ADC_IntEOCStat() * 功能说明: 转换完成中断状态 -* 输 入: ADC_TypeDef * ADCx 指定要被设置的ADC，可取值包括ADC +* 输 入: ADC_TypeDef * ADCx 指定要被设置的ADC，可取值包括ADC * uint32_t chn 要查询的通道，有效值ADC_CH0、ADC_CH1、... ... 、ADC_CH7 -* 输 出: uint32_t 1 该通道完成了转换 0 该通道未完成转换 +* 输 出: uint32_t 1 该通道完成了转换 0 该通道未完成转换 * 注意事项: 无 ******************************************************************************************************************************************/ uint32_t ADC_IntEOCStat(ADC_TypeDef *ADCx, uint32_t chn) @@ -344,7 +347,7 @@ uint32_t ADC_IntEOCStat(ADC_TypeDef *ADCx, uint32_t chn) /****************************************************************************************************************************************** * 函数名称: ADC_IntOVFEn() * 功能说明: 数据溢出中断使能 -* 输 入: ADC_TypeDef * ADCx 指定要被设置的ADC，可取值包括ADC +* 输 入: ADC_TypeDef * ADCx 指定要被设置的ADC，可取值包括ADC * uint32_t chn 要设置的通道，有效值ADC_CH0、ADC_CH1、... ... 、ADC_CH7 * 输 出: 无 * 注意事项: 无 @@ -359,7 +362,7 @@ void ADC_IntOVFEn(ADC_TypeDef *ADCx, uint32_t chn) /****************************************************************************************************************************************** * 函数名称: ADC_IntOVFDis() * 功能说明: 数据溢出中断禁止 -* 输 入: ADC_TypeDef * ADCx 指定要被设置的ADC，可取值包括ADC +* 输 入: ADC_TypeDef * ADCx 指定要被设置的ADC，可取值包括ADC * uint32_t chn 要设置的通道，有效值ADC_CH0、ADC_CH1、... ... 、ADC_CH7 * 输 出: 无 * 注意事项: 无 @@ -374,7 +377,7 @@ void ADC_IntOVFDis(ADC_TypeDef *ADCx, uint32_t chn) /****************************************************************************************************************************************** * 函数名称: ADC_IntOVFClr() * 功能说明: 数据溢出中断标志清除 -* 输 入: ADC_TypeDef * ADCx 指定要被设置的ADC，可取值包括ADC +* 输 入: ADC_TypeDef * ADCx 指定要被设置的ADC，可取值包括ADC * uint32_t chn 要设置的通道，有效值ADC_CH0、ADC_CH1、... ... 、ADC_CH7 * 输 出: 无 * 注意事项: 无 @@ -389,9 +392,9 @@ void ADC_IntOVFClr(ADC_TypeDef *ADCx, uint32_t chn) /****************************************************************************************************************************************** * 函数名称: ADC_IntOVFStat() * 功能说明: 数据溢出中断状态 -* 输 入: ADC_TypeDef * ADCx 指定要被设置的ADC，可取值包括ADC +* 输 入: ADC_TypeDef * ADCx 指定要被设置的ADC，可取值包括ADC * uint32_t chn 要查询的通道，有效值ADC_CH0、ADC_CH1、... ... 、ADC_CH7 -* 输 出: uint32_t 1 该通道完成了转换 0 该通道未完成转换 +* 输 出: uint32_t 1 该通道完成了转换 0 该通道未完成转换 * 注意事项: 无 ******************************************************************************************************************************************/ uint32_t ADC_IntOVFStat(ADC_TypeDef *ADCx, uint32_t chn) @@ -404,7 +407,7 @@ uint32_t ADC_IntOVFStat(ADC_TypeDef *ADCx, uint32_t chn) /****************************************************************************************************************************************** * 函数名称: ADC_IntHFULLEn() * 功能说明: FIFO半满中断使能 -* 输 入: ADC_TypeDef * ADCx 指定要被设置的ADC，可取值包括ADC +* 输 入: ADC_TypeDef * ADCx 指定要被设置的ADC，可取值包括ADC * uint32_t chn 要设置的通道，有效值ADC_CH0、ADC_CH1、... ... 、ADC_CH7 * 输 出: 无 * 注意事项: 无 @@ -419,7 +422,7 @@ void ADC_IntHFULLEn(ADC_TypeDef *ADCx, uint32_t chn) /****************************************************************************************************************************************** * 函数名称: ADC_IntHFULLDis() * 功能说明: FIFO半满中断禁止 -* 输 入: ADC_TypeDef * ADCx 指定要被设置的ADC，可取值包括ADC +* 输 入: ADC_TypeDef * ADCx 指定要被设置的ADC，可取值包括ADC * uint32_t chn 要设置的通道，有效值ADC_CH0、ADC_CH1、... ... 、ADC_CH7 * 输 出: 无 * 注意事项: 无 @@ -434,7 +437,7 @@ void ADC_IntHFULLDis(ADC_TypeDef *ADCx, uint32_t chn) /****************************************************************************************************************************************** * 函数名称: ADC_IntHFULLClr() * 功能说明: FIFO半满中断标志清除 -* 输 入: ADC_TypeDef * ADCx 指定要被设置的ADC，可取值包括ADC +* 输 入: ADC_TypeDef * ADCx 指定要被设置的ADC，可取值包括ADC * uint32_t chn 要设置的通道，有效值ADC_CH0、ADC_CH1、... ... 、ADC_CH7 * 输 出: 无 * 注意事项: 无 @@ -449,9 +452,9 @@ void ADC_IntHFULLClr(ADC_TypeDef *ADCx, uint32_t chn) /****************************************************************************************************************************************** * 函数名称: ADC_IntHFULLStat() * 功能说明: FIFO半满中断状态 -* 输 入: ADC_TypeDef * ADCx 指定要被设置的ADC，可取值包括ADC +* 输 入: ADC_TypeDef * ADCx 指定要被设置的ADC，可取值包括ADC * uint32_t chn 要查询的通道，有效值ADC_CH0、ADC_CH1、... ... 、ADC_CH7 -* 输 出: uint32_t 1 该通道完成了转换 0 该通道未完成转换 +* 输 出: uint32_t 1 该通道完成了转换 0 该通道未完成转换 * 注意事项: 无 ******************************************************************************************************************************************/ uint32_t ADC_IntHFULLStat(ADC_TypeDef *ADCx, uint32_t chn) @@ -464,7 +467,7 @@ uint32_t ADC_IntHFULLStat(ADC_TypeDef *ADCx, uint32_t chn) /****************************************************************************************************************************************** * 函数名称: ADC_IntFULLEn() * 功能说明: FIFO满中断使能 -* 输 入: ADC_TypeDef * ADCx 指定要被设置的ADC，可取值包括ADC +* 输 入: ADC_TypeDef * ADCx 指定要被设置的ADC，可取值包括ADC * uint32_t chn 要设置的通道，有效值ADC_CH0、ADC_CH1、... ... 、ADC_CH7 * 输 出: 无 * 注意事项: 无 @@ -479,7 +482,7 @@ void ADC_IntFULLEn(ADC_TypeDef *ADCx, uint32_t chn) /****************************************************************************************************************************************** * 函数名称: ADC_IntFULLDis() * 功能说明: FIFO满中断禁止 -* 输 入: ADC_TypeDef * ADCx 指定要被设置的ADC，可取值包括ADC +* 输 入: ADC_TypeDef * ADCx 指定要被设置的ADC，可取值包括ADC * uint32_t chn 要设置的通道，有效值ADC_CH0、ADC_CH1、... ... 、ADC_CH7 * 输 出: 无 * 注意事项: 无 @@ -494,7 +497,7 @@ void ADC_IntFULLDis(ADC_TypeDef *ADCx, uint32_t chn) /****************************************************************************************************************************************** * 函数名称: ADC_IntFULLClr() * 功能说明: FIFO满中断标志清除 -* 输 入: ADC_TypeDef * ADCx 指定要被设置的ADC，可取值包括ADC +* 输 入: ADC_TypeDef * ADCx 指定要被设置的ADC，可取值包括ADC * uint32_t chn 要设置的通道，有效值ADC_CH0、ADC_CH1、... ... 、ADC_CH7 * 输 出: 无 * 注意事项: 无 @@ -509,9 +512,9 @@ void ADC_IntFULLClr(ADC_TypeDef *ADCx, uint32_t chn) /****************************************************************************************************************************************** * 函数名称: ADC_IntFULLStat() * 功能说明: FIFO满中断状态 -* 输 入: ADC_TypeDef * ADCx 指定要被设置的ADC，可取值包括ADC +* 输 入: ADC_TypeDef * ADCx 指定要被设置的ADC，可取值包括ADC * uint32_t chn 要查询的通道，有效值ADC_CH0、ADC_CH1、... ... 、ADC_CH7 -* 输 出: uint32_t 1 该通道完成了转换 0 该通道未完成转换 +* 输 出: uint32_t 1 该通道完成了转换 0 该通道未完成转换 * 注意事项: 无 ******************************************************************************************************************************************/ uint32_t ADC_IntFULLStat(ADC_TypeDef *ADCx, uint32_t chn) diff --git a/bsp/swm320-lq100/Libraries/SWM320_StdPeriph_Driver/SWM320_adc.h b/bsp/swm320-lq100/Libraries/SWM320_StdPeriph_Driver/SWM320_adc.h index b5906af908..10b4437527 100644 --- a/bsp/swm320-lq100/Libraries/SWM320_StdPeriph_Driver/SWM320_adc.h +++ b/bsp/swm320-lq100/Libraries/SWM320_StdPeriph_Driver/SWM320_adc.h @@ -3,13 +3,14 @@ typedef struct { - uint8_t clk_src; //ADC转换时钟源：ADC_CLKSRC_HRC、ADC_CLKSRC_VCO_DIV16、ADC_CLKSRC_VCO_DIV32、ADC_CLKSRC_VCO_DIV32 - uint8_t clk_div; //ADC转换时钟分频，取值1--31 - uint8_t channels; //ADC转换通道选中，ADC_CH0、ADC_CH1、... ... 、ADC_CH7及其组合（即“按位或”运算） - uint8_t samplAvg; //采样取平均，触发启动ADC转换后，ADC在一个通道上连续采样、转换多次，并将它们的平均值作为该通道转换结果 - uint8_t trig_src; //ADC触发方式：ADC_TRIGSRC_SW、ADC_TRIGSRC_PWM、ADC_TRIGSRC_TIMR2、ADC_TRIGSRC_TIMR3 - uint8_t Continue; //在软件触发模式下：1 连续转换模式，启动后一直采样、转换，直到软件清除START位 - // 0 单次转换模式，转换完成后START位自动清除停止转换 + uint8_t clk_src; //ADC转换时钟源：ADC_CLKSRC_HRC、ADC_CLKSRC_VCO_DIV16、ADC_CLKSRC_VCO_DIV32、ADC_CLKSRC_VCO_DIV32 + uint8_t clk_div; //ADC转换时钟分频，取值1--31 + uint8_t pga_ref; //PGA基准：PGA_REF_INTERNAL、PGA_REF_EXTERNAL + uint8_t channels; //ADC转换通道选中，ADC_CH0、ADC_CH1、... ... 、ADC_CH7及其组合（即“按位或”运算） + uint8_t samplAvg; //采样取平均，触发启动ADC转换后，ADC在一个通道上连续采样、转换多次，并将它们的平均值作为该通道转换结果 + uint8_t trig_src; //ADC触发方式：ADC_TRIGSRC_SW、ADC_TRIGSRC_PWM、ADC_TRIGSRC_TIMR2、ADC_TRIGSRC_TIMR3 + uint8_t Continue; //在软件触发模式下：1 连续转换模式，启动后一直采样、转换，直到软件清除START位 + // 0 单次转换模式，转换完成后START位自动清除停止转换 uint8_t EOC_IEn; //EOC中断使能，可针对每个通道设置，其有效值为ADC_CH0、ADC_CH1、... ... 、ADC_CH7及其组合（即“按位或”运算） uint8_t OVF_IEn; //OVF中断使能，可针对每个通道设置，其有效值为ADC_CH0、ADC_CH1、... ... 、ADC_CH7及其组合（即“按位或”运算） uint8_t HFULL_IEn; //FIFO半满中断使能，可针对每个通道设置，其有效值为ADC_CH0、ADC_CH1、... ... 、ADC_CH7及其组合（即“按位或”运算） @@ -39,8 +40,8 @@ typedef struct #define ADC_TRIGSRC_SW 0 //软件触发，即ADC->START.GO写1启动转换 #define ADC_TRIGSRC_PWM 1 -#define PGA_VCM_INTERNAL 1 //PGA输入共模电平由内部电路产生，ADC_REFP和ADC_REFN可悬空 -#define PGA_VCM_EXTERNAL 0 //PGA输入共模电平由外部引脚提供，(ADC_REFP + ADC_REFN) 电平值须与量程相同 +#define PGA_REF_INTERNAL 1 //PGA输入共模电平由内部电路产生，ADC_REFP和ADC_REFN可悬空 +#define PGA_REF_EXTERNAL 0 //PGA输入共模电平由外部引脚提供，(ADC_REFP + ADC_REFN) 电平值须与量程相同 void ADC_Init(ADC_TypeDef *ADCx, ADC_InitStructure *initStruct); //ADC模数转换器初始化 void ADC_Open(ADC_TypeDef *ADCx); //ADC开启，可以软件启动、或硬件触发ADC转换 @@ -73,11 +74,4 @@ void ADC_IntFULLDis(ADC_TypeDef *ADCx, uint32_t chn); //FIFO满中断禁止 void ADC_IntFULLClr(ADC_TypeDef *ADCx, uint32_t chn); //FIFO满中断标志清除 uint32_t ADC_IntFULLStat(ADC_TypeDef *ADCx, uint32_t chn); //FIFO满中断状态 -/* ADC 内部 1.2V REFP电压输出到外部REFP引脚，用于测量，或在需要1.2V外部REFP时节省成本 */ -#define ADC_TEST_INNER_REFP_OUT_EN(ADCx) (ADCx->CTRL3 |= (1 << ADC_CTRL3_REFP_OUT_Pos)) -#define ADC_TEST_INNER_REFP_OUT_DIS(ADCx) (ADCx->CTRL3 &= ~(1 << ADC_CTRL3_REFP_OUT_Pos)) - -#define ADC_TEST_ADC_PGA_EXT_VCM_EN(ADCx) (ADCx->CTRL3 |= (1 << ADC_CTRL3_EXTVCM_Pos)) -#define ADC_TEST_ADC_PGA_EXT_VCM_DIS(ADCx) (ADCx->CTRL3 &= ~(1 << ADC_CTRL3_EXTVCM_Pos)) - #endif //__SWM320_ADC_H__ diff --git a/bsp/swm320-lq100/Libraries/SWM320_StdPeriph_Driver/SWM320_can.c b/bsp/swm320-lq100/Libraries/SWM320_StdPeriph_Driver/SWM320_can.c index 2f9a345b21..85d1a81d07 100644 --- a/bsp/swm320-lq100/Libraries/SWM320_StdPeriph_Driver/SWM320_can.c +++ b/bsp/swm320-lq100/Libraries/SWM320_StdPeriph_Driver/SWM320_can.c @@ -24,7 +24,7 @@ /****************************************************************************************************************************************** * 函数名称: CAN_Init() * 功能说明: CAN接口初始化 -* 输 入: CAN_TypeDef * CANx 指定要被设置的CAN接口，有效值包括CAN +* 输 入: CAN_TypeDef * CANx 指定要被设置的CAN接口，有效值包括CAN * CAN_InitStructure * initStruct 包含CAN接口相关设定值的结构体 * 输 出: 无 * 注意事项: 无 @@ -87,7 +87,7 @@ void CAN_Init(CAN_TypeDef *CANx, CAN_InitStructure *initStruct) /****************************************************************************************************************************************** * 函数名称: CAN_Open() * 功能说明: CAN接口打开 -* 输 入: CAN_TypeDef * CANx 指定要被设置的CAN接口，有效值包括CAN +* 输 入: CAN_TypeDef * CANx 指定要被设置的CAN接口，有效值包括CAN * 输 出: 无 * 注意事项: 无 ******************************************************************************************************************************************/ @@ -99,7 +99,7 @@ void CAN_Open(CAN_TypeDef *CANx) /****************************************************************************************************************************************** * 函数名称: CAN_Close() * 功能说明: CAN接口关闭 -* 输 入: CAN_TypeDef * CANx 指定要被设置的CAN接口，有效值包括CAN +* 输 入: CAN_TypeDef * CANx 指定要被设置的CAN接口，有效值包括CAN * 输 出: 无 * 注意事项: 无 ******************************************************************************************************************************************/ @@ -111,7 +111,7 @@ void CAN_Close(CAN_TypeDef *CANx) /****************************************************************************************************************************************** * 函数名称: CAN_Transmit() * 功能说明: CAN发送数据 -* 输 入: CAN_TypeDef * CANx 指定要被设置的CAN接口，有效值包括CAN +* 输 入: CAN_TypeDef * CANx 指定要被设置的CAN接口，有效值包括CAN * uint32_t format CAN_FRAME_STD 标准帧 CAN_FRAME_EXT 扩展帧 * uint32_t id 消息ID * uint8_t data[] 要发送的数据 @@ -126,32 +126,32 @@ void CAN_Transmit(CAN_TypeDef *CANx, uint32_t format, uint32_t id, uint8_t data[ if (format == CAN_FRAME_STD) { - CANx->TXFRAME.INFO = (0 << CAN_INFO_FF_Pos) | - (0 << CAN_INFO_RTR_Pos) | - (size << CAN_INFO_DLC_Pos); + CANx->FRAME.INFO = (0 << CAN_INFO_FF_Pos) | + (0 << CAN_INFO_RTR_Pos) | + (size << CAN_INFO_DLC_Pos); - CANx->TXFRAME.DATA[0] = id >> 3; - CANx->TXFRAME.DATA[1] = id << 5; + CANx->FRAME.DATA[0] = id >> 3; + CANx->FRAME.DATA[1] = id << 5; for (i = 0; i < size; i++) { - CANx->TXFRAME.DATA[i + 2] = data[i]; + CANx->FRAME.DATA[i + 2] = data[i]; } } else //if(format == CAN_FRAME_EXT) { - CANx->TXFRAME.INFO = (1 << CAN_INFO_FF_Pos) | - (0 << CAN_INFO_RTR_Pos) | - (size << CAN_INFO_DLC_Pos); + CANx->FRAME.INFO = (1 << CAN_INFO_FF_Pos) | + (0 << CAN_INFO_RTR_Pos) | + (size << CAN_INFO_DLC_Pos); - CANx->TXFRAME.DATA[0] = id >> 21; - CANx->TXFRAME.DATA[1] = id >> 13; - CANx->TXFRAME.DATA[2] = id >> 5; - CANx->TXFRAME.DATA[3] = id << 3; + CANx->FRAME.DATA[0] = id >> 21; + CANx->FRAME.DATA[1] = id >> 13; + CANx->FRAME.DATA[2] = id >> 5; + CANx->FRAME.DATA[3] = id << 3; for (i = 0; i < size; i++) { - CANx->TXFRAME.DATA[i + 4] = data[i]; + CANx->FRAME.DATA[i + 4] = data[i]; } } @@ -175,7 +175,7 @@ void CAN_Transmit(CAN_TypeDef *CANx, uint32_t format, uint32_t id, uint8_t data[ /****************************************************************************************************************************************** * 函数名称: CAN_TransmitRequest() * 功能说明: CAN发送远程请求，请求远程节点发送数据 -* 输 入: CAN_TypeDef * CANx 指定要被设置的CAN接口，有效值包括CAN +* 输 入: CAN_TypeDef * CANx 指定要被设置的CAN接口，有效值包括CAN * uint32_t format CAN_FRAME_STD 标准帧 CAN_FRAME_EXT 扩展帧 * uint32_t id 消息ID * uint32_t once 只发送一次，即使发送失败（仲裁丢失、发送出错、NAK）也不尝试重发 @@ -186,23 +186,23 @@ void CAN_TransmitRequest(CAN_TypeDef *CANx, uint32_t format, uint32_t id, uint32 { if (format == CAN_FRAME_STD) { - CANx->TXFRAME.INFO = (0 << CAN_INFO_FF_Pos) | - (1 << CAN_INFO_RTR_Pos) | - (0 << CAN_INFO_DLC_Pos); + CANx->FRAME.INFO = (0 << CAN_INFO_FF_Pos) | + (1 << CAN_INFO_RTR_Pos) | + (0 << CAN_INFO_DLC_Pos); - CANx->TXFRAME.DATA[0] = id >> 3; - CANx->TXFRAME.DATA[1] = id << 5; + CANx->FRAME.DATA[0] = id >> 3; + CANx->FRAME.DATA[1] = id << 5; } else //if(format == CAN_FRAME_EXT) { - CANx->TXFRAME.INFO = (1 << CAN_INFO_FF_Pos) | - (1 << CAN_INFO_RTR_Pos) | - (0 << CAN_INFO_DLC_Pos); - - CANx->TXFRAME.DATA[0] = id >> 21; - CANx->TXFRAME.DATA[1] = id >> 13; - CANx->TXFRAME.DATA[2] = id >> 5; - CANx->TXFRAME.DATA[3] = id << 3; + CANx->FRAME.INFO = (1 << CAN_INFO_FF_Pos) | + (1 << CAN_INFO_RTR_Pos) | + (0 << CAN_INFO_DLC_Pos); + + CANx->FRAME.DATA[0] = id >> 21; + CANx->FRAME.DATA[1] = id >> 13; + CANx->FRAME.DATA[2] = id >> 5; + CANx->FRAME.DATA[3] = id << 3; } if (once == 0) @@ -218,7 +218,7 @@ void CAN_TransmitRequest(CAN_TypeDef *CANx, uint32_t format, uint32_t id, uint32 /****************************************************************************************************************************************** * 函数名称: CAN_Receive() * 功能说明: CAN接收数据 -* 输 入: CAN_TypeDef * CANx 指定要被设置的CAN接口，有效值包括CAN +* 输 入: CAN_TypeDef * CANx 指定要被设置的CAN接口，有效值包括CAN * CAN_RXMessage *msg 接收到的消息存储在此结构体变量中 * 输 出: 无 * 注意事项: 无 @@ -226,27 +226,27 @@ void CAN_TransmitRequest(CAN_TypeDef *CANx, uint32_t format, uint32_t id, uint32 void CAN_Receive(CAN_TypeDef *CANx, CAN_RXMessage *msg) { uint32_t i; - uint32_t format = (CANx->RXFRAME.INFO & CAN_INFO_FF_Msk) >> CAN_INFO_FF_Pos; + msg->format = (CANx->FRAME.INFO & CAN_INFO_FF_Msk) >> CAN_INFO_FF_Pos; - msg->remote = (CANx->RXFRAME.INFO & CAN_INFO_RTR_Msk) >> CAN_INFO_RTR_Pos; - msg->size = (CANx->RXFRAME.INFO & CAN_INFO_DLC_Msk) >> CAN_INFO_DLC_Pos; + msg->remote = (CANx->FRAME.INFO & CAN_INFO_RTR_Msk) >> CAN_INFO_RTR_Pos; + msg->size = (CANx->FRAME.INFO & CAN_INFO_DLC_Msk) >> CAN_INFO_DLC_Pos; - if (format == CAN_FRAME_STD) + if (msg->format == CAN_FRAME_STD) { - msg->id = (CANx->RXFRAME.DATA[0] << 3) | (CANx->RXFRAME.DATA[1] >> 5); + msg->id = (CANx->FRAME.DATA[0] << 3) | (CANx->FRAME.DATA[1] >> 5); for (i = 0; i < msg->size; i++) { - msg->data[i] = CANx->RXFRAME.DATA[i + 2]; + msg->data[i] = CANx->FRAME.DATA[i + 2]; } } - else //if(format == CAN_FRAME_EXT) + else //if(msg->format == CAN_FRAME_EXT) { - msg->id = (CANx->RXFRAME.DATA[0] << 21) | (CANx->RXFRAME.DATA[1] << 13) | (CANx->RXFRAME.DATA[2] << 5) | (CANx->RXFRAME.DATA[3] >> 3); + msg->id = (CANx->FRAME.DATA[0] << 21) | (CANx->FRAME.DATA[1] << 13) | (CANx->FRAME.DATA[2] << 5) | (CANx->FRAME.DATA[3] >> 3); for (i = 0; i < msg->size; i++) { - msg->data[i] = CANx->RXFRAME.DATA[i + 4]; + msg->data[i] = CANx->FRAME.DATA[i + 4]; } } @@ -256,8 +256,8 @@ void CAN_Receive(CAN_TypeDef *CANx, CAN_RXMessage *msg) /****************************************************************************************************************************************** * 函数名称: CAN_TXComplete() * 功能说明: 发送是否完成 -* 输 入: CAN_TypeDef * CANx 指定要被设置的CAN接口，有效值包括CAN -* 输 出: uint32_t 1 已经完成 0 还未完成 +* 输 入: CAN_TypeDef * CANx 指定要被设置的CAN接口，有效值包括CAN +* 输 出: uint32_t 1 已经完成 0 还未完成 * 注意事项: 发送被Abort也会触发发送完成，但不会触发发送成功 ******************************************************************************************************************************************/ uint32_t CAN_TXComplete(CAN_TypeDef *CANx) @@ -268,8 +268,8 @@ uint32_t CAN_TXComplete(CAN_TypeDef *CANx) /****************************************************************************************************************************************** * 函数名称: CAN_TXSuccess() * 功能说明: 发送是否成功 -* 输 入: CAN_TypeDef * CANx 指定要被设置的CAN接口，有效值包括CAN -* 输 出: uint32_t 1 发送成功 0 发送失败 +* 输 入: CAN_TypeDef * CANx 指定要被设置的CAN接口，有效值包括CAN +* 输 出: uint32_t 1 发送成功 0 发送失败 * 注意事项: 无 ******************************************************************************************************************************************/ uint32_t CAN_TXSuccess(CAN_TypeDef *CANx) @@ -280,7 +280,7 @@ uint32_t CAN_TXSuccess(CAN_TypeDef *CANx) /****************************************************************************************************************************************** * 函数名称: CAN_AbortTransmit() * 功能说明: 终止发送 -* 输 入: CAN_TypeDef * CANx 指定要被设置的CAN接口，有效值包括CAN +* 输 入: CAN_TypeDef * CANx 指定要被设置的CAN接口，有效值包括CAN * 输 出: 无 * 注意事项: 正在进行的发送无法终止，但执行此命令后若发送失败不会再重发 ******************************************************************************************************************************************/ @@ -292,8 +292,8 @@ void CAN_AbortTransmit(CAN_TypeDef *CANx) /****************************************************************************************************************************************** * 函数名称: CAN_TXBufferReady() * 功能说明: TX Buffer是否准备好可以写入消息 -* 输 入: CAN_TypeDef * CANx 指定要被设置的CAN接口，有效值包括CAN -* 输 出: uint32_t 1 已准备好 0 未准备好 +* 输 入: CAN_TypeDef * CANx 指定要被设置的CAN接口，有效值包括CAN +* 输 出: uint32_t 1 已准备好 0 未准备好 * 注意事项: 无 ******************************************************************************************************************************************/ uint32_t CAN_TXBufferReady(CAN_TypeDef *CANx) @@ -304,8 +304,8 @@ uint32_t CAN_TXBufferReady(CAN_TypeDef *CANx) /****************************************************************************************************************************************** * 函数名称: CAN_RXDataAvailable() * 功能说明: RX FIFO中是否有数据可读出 -* 输 入: CAN_TypeDef * CANx 指定要被设置的CAN接口，有效值包括CAN -* 输 出: uint32_t 1 有数据可读出 0 没有数据 +* 输 入: CAN_TypeDef * CANx 指定要被设置的CAN接口，有效值包括CAN +* 输 出: uint32_t 1 有数据可读出 0 没有数据 * 注意事项: 无 ******************************************************************************************************************************************/ uint32_t CAN_RXDataAvailable(CAN_TypeDef *CANx) @@ -316,7 +316,7 @@ uint32_t CAN_RXDataAvailable(CAN_TypeDef *CANx) /****************************************************************************************************************************************** * 函数名称: CAN_SetBaudrate() * 功能说明: 设置波特率 -* 输 入: CAN_TypeDef * CANx 指定要被设置的CAN接口，有效值包括CAN +* 输 入: CAN_TypeDef * CANx 指定要被设置的CAN接口，有效值包括CAN * uint32_t baudrate 波特率，即位传输速率 * uint32_t CAN_BS1 CAN_BS1_1tq、CAN_BS1_2tq、... ... 、CAN_BS1_16tq * uint32_t CAN_BS2 CAN_BS2_1tq、CAN_BS2_2tq、... ... 、CAN_BS2_8tq @@ -337,7 +337,7 @@ void CAN_SetBaudrate(CAN_TypeDef *CANx, uint32_t baudrate, uint32_t CAN_BS1, uin /****************************************************************************************************************************************** * 函数名称: CAN_SetFilter32b() * 功能说明: 设置接收滤波器，1个32位滤波器 -* 输 入: CAN_TypeDef * CANx 指定要被设置的CAN接口，有效值包括CAN +* 输 入: CAN_TypeDef * CANx 指定要被设置的CAN接口，有效值包括CAN * uint32_t check 与mask一起决定了接收到的Message是否是自己需要的：check & (~mask) == ID & (~mask)的Message通过过滤 * uint32_t mask * 输 出: 无 @@ -348,21 +348,21 @@ void CAN_SetFilter32b(CAN_TypeDef *CANx, uint32_t check, uint32_t mask) CANx->CR &= ~CAN_CR_AFM_Msk; CANx->CR |= (CAN_FILTER_32b << CAN_CR_AFM_Pos); - CANx->FILTER.AMR[0] = mask & 0xFF; - CANx->FILTER.AMR[1] = (mask >> 8) & 0xFF; - CANx->FILTER.AMR[2] = (mask >> 16) & 0xFF; - CANx->FILTER.AMR[3] = (mask >> 24) & 0xFF; + CANx->FILTER.AMR[3] = mask & 0xFF; + CANx->FILTER.AMR[2] = (mask >> 8) & 0xFF; + CANx->FILTER.AMR[1] = (mask >> 16) & 0xFF; + CANx->FILTER.AMR[0] = (mask >> 24) & 0xFF; - CANx->FILTER.ACR[0] = check & 0xFF; - CANx->FILTER.ACR[1] = (check >> 8) & 0xFF; - CANx->FILTER.ACR[2] = (check >> 16) & 0xFF; - CANx->FILTER.ACR[3] = (check >> 24) & 0xFF; + CANx->FILTER.ACR[3] = check & 0xFF; + CANx->FILTER.ACR[2] = (check >> 8) & 0xFF; + CANx->FILTER.ACR[1] = (check >> 16) & 0xFF; + CANx->FILTER.ACR[0] = (check >> 24) & 0xFF; } /****************************************************************************************************************************************** * 函数名称: CAN_SetFilter16b() * 功能说明: 设置接收滤波器，2个16位滤波器 -* 输 入: CAN_TypeDef * CANx 指定要被设置的CAN接口，有效值包括CAN +* 输 入: CAN_TypeDef * CANx 指定要被设置的CAN接口，有效值包括CAN * uint16_t check1 与mask一起决定了接收到的Message是否是自己需要的：check & (~mask) == ID & (~mask)的Message通过过滤 * uint16_t mask1 * uint16_t check2 @@ -375,21 +375,21 @@ void CAN_SetFilter16b(CAN_TypeDef *CANx, uint16_t check1, uint16_t mask1, uint16 CANx->CR &= ~CAN_CR_AFM_Msk; CANx->CR |= (CAN_FILTER_16b << CAN_CR_AFM_Pos); - CANx->FILTER.AMR[0] = mask1 & 0xFF; - CANx->FILTER.AMR[1] = (mask1 >> 8) & 0xFF; - CANx->FILTER.AMR[2] = mask2 & 0xFF; - CANx->FILTER.AMR[3] = (mask2 >> 8) & 0xFF; + CANx->FILTER.AMR[3] = mask1 & 0xFF; + CANx->FILTER.AMR[2] = (mask1 >> 8) & 0xFF; + CANx->FILTER.AMR[1] = mask2 & 0xFF; + CANx->FILTER.AMR[0] = (mask2 >> 8) & 0xFF; - CANx->FILTER.ACR[0] = check1 & 0xFF; - CANx->FILTER.ACR[1] = (check1 >> 8) & 0xFF; - CANx->FILTER.ACR[2] = check2 & 0xFF; - CANx->FILTER.ACR[3] = (check2 >> 8) & 0xFF; + CANx->FILTER.ACR[3] = check1 & 0xFF; + CANx->FILTER.ACR[2] = (check1 >> 8) & 0xFF; + CANx->FILTER.ACR[1] = check2 & 0xFF; + CANx->FILTER.ACR[0] = (check2 >> 8) & 0xFF; } /****************************************************************************************************************************************** * 函数名称: CAN_INTRXNotEmptyEn() * 功能说明: 当RX FIFO中有数据时（非空）触发中断使能 -* 输 入: CAN_TypeDef * CANx 指定要被设置的CAN接口，有效值包括CAN +* 输 入: CAN_TypeDef * CANx 指定要被设置的CAN接口，有效值包括CAN * 输 出: 无 * 注意事项: 无 ******************************************************************************************************************************************/ @@ -401,7 +401,7 @@ void CAN_INTRXNotEmptyEn(CAN_TypeDef *CANx) /****************************************************************************************************************************************** * 函数名称: CAN_INTRXNotEmptyDis() * 功能说明: 当RX FIFO中有数据时（非空）触发中断禁止 -* 输 入: CAN_TypeDef * CANx 指定要被设置的CAN接口，有效值包括CAN +* 输 入: CAN_TypeDef * CANx 指定要被设置的CAN接口，有效值包括CAN * 输 出: 无 * 注意事项: 无 ******************************************************************************************************************************************/ @@ -410,22 +410,10 @@ void CAN_INTRXNotEmptyDis(CAN_TypeDef *CANx) CANx->IE &= ~(1 << CAN_IE_RXDA_Pos); } -/****************************************************************************************************************************************** -* 函数名称: CAN_INTRXNotEmptyStat() -* 功能说明: RX FIFO非空中断是否触发 -* 输 入: CAN_TypeDef * CANx 指定要被设置的CAN接口，有效值包括CAN -* 输 出: uint32_t 1 已触发 0 未触发 -* 注意事项: 无 -******************************************************************************************************************************************/ -uint32_t CAN_INTRXNotEmptyStat(CAN_TypeDef *CANx) -{ - return (CANx->IF & CAN_IF_RXDA_Msk) ? 1 : 0; -} - /****************************************************************************************************************************************** * 函数名称: CAN_INTTXBufEmptyEn() * 功能说明: 当TX Buffer空时触发中断使能 -* 输 入: CAN_TypeDef * CANx 指定要被设置的CAN接口，有效值包括CAN +* 输 入: CAN_TypeDef * CANx 指定要被设置的CAN接口，有效值包括CAN * 输 出: 无 * 注意事项: 无 ******************************************************************************************************************************************/ @@ -437,7 +425,7 @@ void CAN_INTTXBufEmptyEn(CAN_TypeDef *CANx) /****************************************************************************************************************************************** * 函数名称: CAN_INTTXBufEmptyDis() * 功能说明: 当TX Buffer空时触发中断禁止 -* 输 入: CAN_TypeDef * CANx 指定要被设置的CAN接口，有效值包括CAN +* 输 入: CAN_TypeDef * CANx 指定要被设置的CAN接口，有效值包括CAN * 输 出: 无 * 注意事项: 无 ******************************************************************************************************************************************/ @@ -446,22 +434,10 @@ void CAN_INTTXBufEmptyDis(CAN_TypeDef *CANx) CANx->IE &= ~(1 << CAN_IE_TXBR_Pos); } -/****************************************************************************************************************************************** -* 函数名称: CAN_INTTXBufEmptyStat() -* 功能说明: TX Buffer空中断是否触发 -* 输 入: CAN_TypeDef * CANx 指定要被设置的CAN接口，有效值包括CAN -* 输 出: uint32_t 1 已触发 0 未触发 -* 注意事项: 无 -******************************************************************************************************************************************/ -uint32_t CAN_INTTXBufEmptyStat(CAN_TypeDef *CANx) -{ - return (CANx->IF & CAN_IF_TXBR_Msk) ? 1 : 0; -} - /****************************************************************************************************************************************** * 函数名称: CAN_INTErrWarningEn() * 功能说明: TXERR/RXERR计数值达到Error Warning Limit时触发中断使能 -* 输 入: CAN_TypeDef * CANx 指定要被设置的CAN接口，有效值包括CAN +* 输 入: CAN_TypeDef * CANx 指定要被设置的CAN接口，有效值包括CAN * 输 出: 无 * 注意事项: 无 ******************************************************************************************************************************************/ @@ -473,7 +449,7 @@ void CAN_INTErrWarningEn(CAN_TypeDef *CANx) /****************************************************************************************************************************************** * 函数名称: CAN_INTErrWarningDis() * 功能说明: TXERR/RXERR计数值达到Error Warning Limit时触发中断禁止 -* 输 入: CAN_TypeDef * CANx 指定要被设置的CAN接口，有效值包括CAN +* 输 入: CAN_TypeDef * CANx 指定要被设置的CAN接口，有效值包括CAN * 输 出: 无 * 注意事项: 无 ******************************************************************************************************************************************/ @@ -482,22 +458,10 @@ void CAN_INTErrWarningDis(CAN_TypeDef *CANx) CANx->IE &= ~(1 << CAN_IE_ERRWARN_Pos); } -/****************************************************************************************************************************************** -* 函数名称: CAN_INTErrWarningStat() -* 功能说明: TXERR/RXERR计数值达到Error Warning Limit中断是否触发 -* 输 入: CAN_TypeDef * CANx 指定要被设置的CAN接口，有效值包括CAN -* 输 出: uint32_t 1 已触发 0 未触发 -* 注意事项: 无 -******************************************************************************************************************************************/ -uint32_t CAN_INTErrWarningStat(CAN_TypeDef *CANx) -{ - return (CANx->IF & CAN_IF_ERRWARN_Msk) ? 1 : 0; -} - /****************************************************************************************************************************************** * 函数名称: CAN_INTRXOverflowEn() * 功能说明: RX FIFO 溢出时触发中断使能 -* 输 入: CAN_TypeDef * CANx 指定要被设置的CAN接口，有效值包括CAN +* 输 入: CAN_TypeDef * CANx 指定要被设置的CAN接口，有效值包括CAN * 输 出: 无 * 注意事项: 无 ******************************************************************************************************************************************/ @@ -509,7 +473,7 @@ void CAN_INTRXOverflowEn(CAN_TypeDef *CANx) /****************************************************************************************************************************************** * 函数名称: CAN_INTRXOverflowDis() * 功能说明: RX FIFO 溢出时触发中断禁止 -* 输 入: CAN_TypeDef * CANx 指定要被设置的CAN接口，有效值包括CAN +* 输 入: CAN_TypeDef * CANx 指定要被设置的CAN接口，有效值包括CAN * 输 出: 无 * 注意事项: 无 ******************************************************************************************************************************************/ @@ -518,22 +482,10 @@ void CAN_INTRXOverflowDis(CAN_TypeDef *CANx) CANx->IE &= ~(1 << CAN_IE_RXOV_Pos); } -/****************************************************************************************************************************************** -* 函数名称: CAN_INTRXOverflowStat() -* 功能说明: RX FIFO 溢出中断是否触发 -* 输 入: CAN_TypeDef * CANx 指定要被设置的CAN接口，有效值包括CAN -* 输 出: uint32_t 1 已触发 0 未触发 -* 注意事项: 无 -******************************************************************************************************************************************/ -uint32_t CAN_INTRXOverflowStat(CAN_TypeDef *CANx) -{ - return (CANx->IF & CAN_IF_RXOV_Msk) ? 1 : 0; -} - /****************************************************************************************************************************************** * 函数名称: CAN_INTRXOverflowClear() * 功能说明: RX FIFO 溢出中断清除 -* 输 入: CAN_TypeDef * CANx 指定要被设置的CAN接口，有效值包括CAN +* 输 入: CAN_TypeDef * CANx 指定要被设置的CAN接口，有效值包括CAN * 输 出: 无 * 注意事项: 无 ******************************************************************************************************************************************/ @@ -545,7 +497,7 @@ void CAN_INTRXOverflowClear(CAN_TypeDef *CANx) /****************************************************************************************************************************************** * 函数名称: CAN_INTWakeupEn() * 功能说明: 唤醒事件触发中断使能 -* 输 入: CAN_TypeDef * CANx 指定要被设置的CAN接口，有效值包括CAN +* 输 入: CAN_TypeDef * CANx 指定要被设置的CAN接口，有效值包括CAN * 输 出: 无 * 注意事项: 无 ******************************************************************************************************************************************/ @@ -557,7 +509,7 @@ void CAN_INTWakeupEn(CAN_TypeDef *CANx) /****************************************************************************************************************************************** * 函数名称: CAN_INTWakeupDis() * 功能说明: 唤醒事件触发中断禁止 -* 输 入: CAN_TypeDef * CANx 指定要被设置的CAN接口，有效值包括CAN +* 输 入: CAN_TypeDef * CANx 指定要被设置的CAN接口，有效值包括CAN * 输 出: 无 * 注意事项: 无 ******************************************************************************************************************************************/ @@ -566,22 +518,10 @@ void CAN_INTWakeupDis(CAN_TypeDef *CANx) CANx->IE &= ~(1 << CAN_IE_WKUP_Pos); } -/****************************************************************************************************************************************** -* 函数名称: CAN_INTWakeupStat() -* 功能说明: 唤醒事件中断是否触发 -* 输 入: CAN_TypeDef * CANx 指定要被设置的CAN接口，有效值包括CAN -* 输 出: uint32_t 1 已触发 0 未触发 -* 注意事项: 无 -******************************************************************************************************************************************/ -uint32_t CAN_INTWakeupStat(CAN_TypeDef *CANx) -{ - return (CANx->IF & CAN_IF_WKUP_Msk) ? 1 : 0; -} - /****************************************************************************************************************************************** * 函数名称: CAN_INTErrPassiveEn() * 功能说明: TXERR/RXERR计数值达到127时中断使能 -* 输 入: CAN_TypeDef * CANx 指定要被设置的CAN接口，有效值包括CAN +* 输 入: CAN_TypeDef * CANx 指定要被设置的CAN接口，有效值包括CAN * 输 出: 无 * 注意事项: 无 ******************************************************************************************************************************************/ @@ -593,7 +533,7 @@ void CAN_INTErrPassiveEn(CAN_TypeDef *CANx) /****************************************************************************************************************************************** * 函数名称: CAN_INTErrPassiveDis() * 功能说明: TXERR/RXERR计数值达到127时中断禁止 -* 输 入: CAN_TypeDef * CANx 指定要被设置的CAN接口，有效值包括CAN +* 输 入: CAN_TypeDef * CANx 指定要被设置的CAN接口，有效值包括CAN * 输 出: 无 * 注意事项: 无 ******************************************************************************************************************************************/ @@ -602,22 +542,10 @@ void CAN_INTErrPassiveDis(CAN_TypeDef *CANx) CANx->IE &= ~(1 << CAN_IE_ERRPASS_Pos); } -/****************************************************************************************************************************************** -* 函数名称: CAN_INTErrPassiveStat() -* 功能说明: TXERR/RXERR计数值达到127中断是否触发 -* 输 入: CAN_TypeDef * CANx 指定要被设置的CAN接口，有效值包括CAN -* 输 出: uint32_t 1 已触发 0 未触发 -* 注意事项: 无 -******************************************************************************************************************************************/ -uint32_t CAN_INTErrPassiveStat(CAN_TypeDef *CANx) -{ - return (CANx->IF & CAN_IF_ERRPASS_Msk) ? 1 : 0; -} - /****************************************************************************************************************************************** * 函数名称: CAN_INTArbitrLostEn() * 功能说明: 仲裁失败中断使能 -* 输 入: CAN_TypeDef * CANx 指定要被设置的CAN接口，有效值包括CAN +* 输 入: CAN_TypeDef * CANx 指定要被设置的CAN接口，有效值包括CAN * 输 出: 无 * 注意事项: 无 ******************************************************************************************************************************************/ @@ -629,7 +557,7 @@ void CAN_INTArbitrLostEn(CAN_TypeDef *CANx) /****************************************************************************************************************************************** * 函数名称: CAN_INTArbitrLostDis() * 功能说明: 仲裁失败中断禁止 -* 输 入: CAN_TypeDef * CANx 指定要被设置的CAN接口，有效值包括CAN +* 输 入: CAN_TypeDef * CANx 指定要被设置的CAN接口，有效值包括CAN * 输 出: 无 * 注意事项: 无 ******************************************************************************************************************************************/ @@ -638,22 +566,10 @@ void CAN_INTArbitrLostDis(CAN_TypeDef *CANx) CANx->IE &= ~(1 << CAN_IE_ARBLOST_Pos); } -/****************************************************************************************************************************************** -* 函数名称: CAN_INTArbitrLostStat() -* 功能说明: 仲裁失败中断是否触发 -* 输 入: CAN_TypeDef * CANx 指定要被设置的CAN接口，有效值包括CAN -* 输 出: uint32_t 1 已触发 0 未触发 -* 注意事项: 无 -******************************************************************************************************************************************/ -uint32_t CAN_INTArbitrLostStat(CAN_TypeDef *CANx) -{ - return (CANx->IF & CAN_IF_ARBLOST_Msk) ? 1 : 0; -} - /****************************************************************************************************************************************** * 函数名称: CAN_INTBusErrorEn() * 功能说明: 总线错误中断使能 -* 输 入: CAN_TypeDef * CANx 指定要被设置的CAN接口，有效值包括CAN +* 输 入: CAN_TypeDef * CANx 指定要被设置的CAN接口，有效值包括CAN * 输 出: 无 * 注意事项: 无 ******************************************************************************************************************************************/ @@ -665,7 +581,7 @@ void CAN_INTBusErrorEn(CAN_TypeDef *CANx) /****************************************************************************************************************************************** * 函数名称: CAN_INTBusErrorDis() * 功能说明: 总线错误中断禁止 -* 输 入: CAN_TypeDef * CANx 指定要被设置的CAN接口，有效值包括CAN +* 输 入: CAN_TypeDef * CANx 指定要被设置的CAN接口，有效值包括CAN * 输 出: 无 * 注意事项: 无 ******************************************************************************************************************************************/ @@ -675,13 +591,13 @@ void CAN_INTBusErrorDis(CAN_TypeDef *CANx) } /****************************************************************************************************************************************** -* 函数名称: CAN_INTBusErrorStat() -* 功能说明: 总线错误中断是否触发 -* 输 入: CAN_TypeDef * CANx 指定要被设置的CAN接口，有效值包括CAN -* 输 出: uint32_t 1 已触发 0 未触发 -* 注意事项: 无 +* 函数名称: CAN_INTStat() +* 功能说明: 查询中断状态 +* 输 入: CAN_TypeDef * CANx 指定要被设置的CAN接口，有效值包括CAN +* 输 出: uint32_t 当前中断状态 +* 注意事项: CANx->IF读取清零，因此在中断ISR中只能读取一次，不能多次读取 ******************************************************************************************************************************************/ -uint32_t CAN_INTBusErrorStat(CAN_TypeDef *CANx) +uint32_t CAN_INTStat(CAN_TypeDef *CANx) { - return (CANx->IF & CAN_IF_BUSERR_Msk) ? 1 : 0; + return CANx->IF; } diff --git a/bsp/swm320-lq100/Libraries/SWM320_StdPeriph_Driver/SWM320_can.h b/bsp/swm320-lq100/Libraries/SWM320_StdPeriph_Driver/SWM320_can.h index 6a239c84b3..2b31a97c7d 100644 --- a/bsp/swm320-lq100/Libraries/SWM320_StdPeriph_Driver/SWM320_can.h +++ b/bsp/swm320-lq100/Libraries/SWM320_StdPeriph_Driver/SWM320_can.h @@ -1,22 +1,22 @@ #ifndef __SWM320_CAN_H__ #define __SWM320_CAN_H__ -#define CAN_FRAME_STD 0 -#define CAN_FRAME_EXT 1 +#define CAN_FRAME_STD 0 +#define CAN_FRAME_EXT 1 typedef struct { - uint8_t Mode; //CAN_MODE_NORMALCAN_MODE_LISTENCAN_MODE_SELFTEST - uint8_t CAN_BS1; //CAN_BS1_1tqCAN_BS1_2tq... ... CAN_BS1_16tq - uint8_t CAN_BS2; //CAN_BS2_1tqCAN_BS2_2tq... ... CAN_BS2_8tq - uint8_t CAN_SJW; //CAN_SJW_1tqCAN_SJW_2tqCAN_SJW_3tqCAN_SJW_4tq - uint32_t Baudrate; //ʣλʣȡֵ1--1000000 - uint8_t FilterMode; //CAN_FILTER_16bCAN_FILTER_32b + uint8_t Mode; //CAN_MODE_NORMAL、CAN_MODE_LISTEN、CAN_MODE_SELFTEST + uint8_t CAN_BS1; //CAN_BS1_1tq、CAN_BS1_2tq、... ... 、CAN_BS1_16tq + uint8_t CAN_BS2; //CAN_BS2_1tq、CAN_BS2_2tq、... ... 、CAN_BS2_8tq + uint8_t CAN_SJW; //CAN_SJW_1tq、CAN_SJW_2tq、CAN_SJW_3tq、CAN_SJW_4tq + uint32_t Baudrate; //波特率，即位传输速率，取值1--1000000 + uint8_t FilterMode; //CAN_FILTER_16b、CAN_FILTER_32b union { - uint32_t FilterMask32b; //FilterCheck & (~FilterMask) == ID & (~FilterMask)Messageͨ - struct // 0 must match 1 don't care - { + uint32_t FilterMask32b; //FilterCheck & (~FilterMask) == ID & (~FilterMask)的Message通过过滤 + struct + { // 0 must match 1 don't care uint16_t FilterMask16b1; uint16_t FilterMask16b2; }; @@ -30,59 +30,59 @@ typedef struct uint16_t FilterCheck16b2; }; }; - uint8_t RXNotEmptyIEn; //FIFOǿգݿɶ - uint8_t RXOverflowIEn; //FIFOݶʧ - uint8_t ArbitrLostIEn; //ʧٲñɽշ - uint8_t ErrPassiveIEn; ///ʹֵﵽ127 + uint8_t RXNotEmptyIEn; //接收FIFO非空，有数据可读 + uint8_t RXOverflowIEn; //接收FIFO溢出，有数据丢失 + uint8_t ArbitrLostIEn; //控制器丢失仲裁变成接收方 + uint8_t ErrPassiveIEn; //接收/发送错误计数值达到127 } CAN_InitStructure; -#define CAN_MODE_NORMAL 0 //ģʽ -#define CAN_MODE_LISTEN 1 //ģʽ -#define CAN_MODE_SELFTEST 2 //Բģʽ - -#define CAN_BS1_1tq 0 -#define CAN_BS1_2tq 1 -#define CAN_BS1_3tq 2 -#define CAN_BS1_4tq 3 -#define CAN_BS1_5tq 4 -#define CAN_BS1_6tq 5 -#define CAN_BS1_7tq 6 -#define CAN_BS1_8tq 7 -#define CAN_BS1_9tq 8 -#define CAN_BS1_10tq 9 -#define CAN_BS1_11tq 10 -#define CAN_BS1_12tq 11 -#define CAN_BS1_13tq 12 -#define CAN_BS1_14tq 13 -#define CAN_BS1_15tq 14 -#define CAN_BS1_16tq 15 - -#define CAN_BS2_1tq 0 -#define CAN_BS2_2tq 1 -#define CAN_BS2_3tq 2 -#define CAN_BS2_4tq 3 -#define CAN_BS2_5tq 4 -#define CAN_BS2_6tq 5 -#define CAN_BS2_7tq 6 -#define CAN_BS2_8tq 7 - -#define CAN_SJW_1tq 0 -#define CAN_SJW_2tq 1 -#define CAN_SJW_3tq 2 -#define CAN_SJW_4tq 3 - -#define CAN_FILTER_16b 0 //16λ -#define CAN_FILTER_32b 1 //һ32λ +#define CAN_MODE_NORMAL 0 //常规模式 +#define CAN_MODE_LISTEN 1 //监听模式 +#define CAN_MODE_SELFTEST 2 //自测模式 + +#define CAN_BS1_1tq 0 +#define CAN_BS1_2tq 1 +#define CAN_BS1_3tq 2 +#define CAN_BS1_4tq 3 +#define CAN_BS1_5tq 4 +#define CAN_BS1_6tq 5 +#define CAN_BS1_7tq 6 +#define CAN_BS1_8tq 7 +#define CAN_BS1_9tq 8 +#define CAN_BS1_10tq 9 +#define CAN_BS1_11tq 10 +#define CAN_BS1_12tq 11 +#define CAN_BS1_13tq 12 +#define CAN_BS1_14tq 13 +#define CAN_BS1_15tq 14 +#define CAN_BS1_16tq 15 + +#define CAN_BS2_1tq 0 +#define CAN_BS2_2tq 1 +#define CAN_BS2_3tq 2 +#define CAN_BS2_4tq 3 +#define CAN_BS2_5tq 4 +#define CAN_BS2_6tq 5 +#define CAN_BS2_7tq 6 +#define CAN_BS2_8tq 7 + +#define CAN_SJW_1tq 0 +#define CAN_SJW_2tq 1 +#define CAN_SJW_3tq 2 +#define CAN_SJW_4tq 3 + +#define CAN_FILTER_16b 0 //两个16位过滤器 +#define CAN_FILTER_32b 1 //一个32位过滤器 typedef struct { - uint32_t id; //ϢID - uint8_t remote; //ϢǷΪԶ֡ - uint8_t data[8]; //յ - uint8_t size; //յݸ + uint32_t id; //消息ID + uint8_t format; //帧格式：CAN_FRAME_STD、CAN_FRAME_EXT + uint8_t remote; //消息是否为远程帧 + uint8_t size; //接收到的数据个数 + uint8_t data[8]; //接收到的数据 } CAN_RXMessage; - void CAN_Init(CAN_TypeDef *CANx, CAN_InitStructure *initStruct); void CAN_Open(CAN_TypeDef *CANx); void CAN_Close(CAN_TypeDef *CANx); @@ -104,38 +104,31 @@ void CAN_SetBaudrate(CAN_TypeDef *CANx, uint32_t baudrate, uint32_t CAN_BS1, uin void CAN_SetFilter32b(CAN_TypeDef *CANx, uint32_t check, uint32_t mask); void CAN_SetFilter16b(CAN_TypeDef *CANx, uint16_t check1, uint16_t mask1, uint16_t check2, uint16_t mask2); - void CAN_INTRXNotEmptyEn(CAN_TypeDef *CANx); void CAN_INTRXNotEmptyDis(CAN_TypeDef *CANx); -uint32_t CAN_INTRXNotEmptyStat(CAN_TypeDef *CANx); void CAN_INTTXBufEmptyEn(CAN_TypeDef *CANx); void CAN_INTTXBufEmptyDis(CAN_TypeDef *CANx); -uint32_t CAN_INTTXBufEmptyStat(CAN_TypeDef *CANx); void CAN_INTErrWarningEn(CAN_TypeDef *CANx); void CAN_INTErrWarningDis(CAN_TypeDef *CANx); -uint32_t CAN_INTErrWarningStat(CAN_TypeDef *CANx); void CAN_INTRXOverflowEn(CAN_TypeDef *CANx); void CAN_INTRXOverflowDis(CAN_TypeDef *CANx); -uint32_t CAN_INTRXOverflowStat(CAN_TypeDef *CANx); void CAN_INTRXOverflowClear(CAN_TypeDef *CANx); void CAN_INTWakeupEn(CAN_TypeDef *CANx); void CAN_INTWakeupDis(CAN_TypeDef *CANx); -uint32_t CAN_INTWakeupStat(CAN_TypeDef *CANx); void CAN_INTErrPassiveEn(CAN_TypeDef *CANx); void CAN_INTErrPassiveDis(CAN_TypeDef *CANx); -uint32_t CAN_INTErrPassiveStat(CAN_TypeDef *CANx); void CAN_INTArbitrLostEn(CAN_TypeDef *CANx); void CAN_INTArbitrLostDis(CAN_TypeDef *CANx); -uint32_t CAN_INTArbitrLostStat(CAN_TypeDef *CANx); void CAN_INTBusErrorEn(CAN_TypeDef *CANx); void CAN_INTBusErrorDis(CAN_TypeDef *CANx); -uint32_t CAN_INTBusErrorStat(CAN_TypeDef *CANx); + +uint32_t CAN_INTStat(CAN_TypeDef *CANx); #endif //__SWM320_CAN_H__ diff --git a/bsp/swm320-lq100/Libraries/SWM320_StdPeriph_Driver/SWM320_crc.c b/bsp/swm320-lq100/Libraries/SWM320_StdPeriph_Driver/SWM320_crc.c index 0258c90382..1255d3093e 100644 --- a/bsp/swm320-lq100/Libraries/SWM320_StdPeriph_Driver/SWM320_crc.c +++ b/bsp/swm320-lq100/Libraries/SWM320_StdPeriph_Driver/SWM320_crc.c @@ -1,10 +1,10 @@ /****************************************************************************************************************************************** -* ļ: SWM320_crc.c -* ˵: SWM320ƬCRCģ -* ֧: http://www.synwit.com.cn/e/tool/gbook/?bid=1 -* ע: -* 汾: V1.1.0 20171025 -* ¼: +* 文件名称: SWM320_crc.c +* 功能说明: SWM320单片机的CRC模块驱动库 +* 技术支持: http://www.synwit.com.cn/e/tool/gbook/?bid=1 +* 注意事项: +* 版本日期: V1.1.0 2017年10月25日 +* 升级记录: * * ******************************************************************************************************************************************* @@ -21,17 +21,16 @@ #include "SWM320.h" #include "SWM320_crc.h" - /****************************************************************************************************************************************** -* : CRC_Init() -* ˵: CRC ʼ -* : CRC_TypeDef * CRCx ָҪõCRCӿڣЧֵCRC -* uint32_t mode ģʽЧֵУCRC32_IN32CRC32_IN16CRC32_IN8CRC16_IN16CRC16_IN8 -* uint32_t out_not Ƿȡ -* uint32_t out_rev Ƿת -* uint32_t ini_val CRCʼֵ -* : -* ע: +* 函数名称: CRC_Init() +* 功能说明: CRC 初始化 +* 输 入: CRC_TypeDef * CRCx 指定要被设置的CRC接口，有效值包括CRC +* uint32_t mode 工作模式，有效值有：CRC32_IN32、CRC32_IN16、CRC32_IN8、CRC16_IN16、CRC16_IN8 +* uint32_t out_not 输出结果是否取反 +* uint32_t out_rev 输出结果是否翻转 +* uint32_t ini_val CRC初始值 +* 输 出: 无 +* 注意事项: 无 ******************************************************************************************************************************************/ void CRC_Init(CRC_TypeDef *CRCx, uint32_t mode, uint32_t out_not, uint32_t out_rev, uint32_t ini_val) { diff --git a/bsp/swm320-lq100/Libraries/SWM320_StdPeriph_Driver/SWM320_crc.h b/bsp/swm320-lq100/Libraries/SWM320_StdPeriph_Driver/SWM320_crc.h index 947bf85455..54de1301b2 100644 --- a/bsp/swm320-lq100/Libraries/SWM320_StdPeriph_Driver/SWM320_crc.h +++ b/bsp/swm320-lq100/Libraries/SWM320_StdPeriph_Driver/SWM320_crc.h @@ -1,23 +1,20 @@ #ifndef __SWM320_CRC_H__ #define __SWM320_CRC_H__ - -#define CRC32_IN32 0 //CRC32㷨32λ -#define CRC32_IN16 2 //CRC32㷨16λ -#define CRC32_IN8 4 //CRC32㷨 8λ -#define CRC16_IN16 3 //CRC16㷨16λ -#define CRC16_IN8 5 //CRC16㷨 8λ - +#define CRC32_IN32 0 //CRC32算法，输入数据32位 +#define CRC32_IN16 2 //CRC32算法，输入数据16位 +#define CRC32_IN8 4 //CRC32算法，输入数据 8位 +#define CRC16_IN16 3 //CRC16算法，输入数据16位 +#define CRC16_IN8 5 //CRC16算法，输入数据 8位 void CRC_Init(CRC_TypeDef *CRCx, uint32_t mode, uint32_t out_not, uint32_t out_rev, uint32_t ini_val); - /****************************************************************************************************************************************** -* : CRC_Write() -* ˵: CRCд -* : uint32_t data Ҫд -* : -* ע: +* 函数名称: CRC_Write() +* 功能说明: CRC写入数据 +* 输 入: uint32_t data 要写入的数据 +* 输 出: 无 +* 注意事项: 无 ******************************************************************************************************************************************/ static __INLINE void CRC_Write(uint32_t data) { @@ -25,11 +22,11 @@ static __INLINE void CRC_Write(uint32_t data) } /****************************************************************************************************************************************** -* : CRC_Result() -* ˵: ȡCRC -* : -* : uint32_t CRC -* ע: +* 函数名称: CRC_Result() +* 功能说明: 获取CRC计算结果 +* 输 入: 无 +* 输 出: uint32_t CRC 计算结果 +* 注意事项: 无 ******************************************************************************************************************************************/ static __INLINE uint32_t CRC_Result(void) { diff --git a/bsp/swm320-lq100/Libraries/SWM320_StdPeriph_Driver/SWM320_dma.c b/bsp/swm320-lq100/Libraries/SWM320_StdPeriph_Driver/SWM320_dma.c index 3abb4c4b3a..70e7ac559b 100644 --- a/bsp/swm320-lq100/Libraries/SWM320_StdPeriph_Driver/SWM320_dma.c +++ b/bsp/swm320-lq100/Libraries/SWM320_StdPeriph_Driver/SWM320_dma.c @@ -1,10 +1,10 @@ /****************************************************************************************************************************************** -* ļ: SWM320_dma.c -* ˵: SWM320ƬDMA -* ֧: http://www.synwit.com.cn/e/tool/gbook/?bid=1 -* ע: -* 汾: V1.1.0 20171025 -* ¼: +* 文件名称: SWM320_dma.c +* 功能说明: SWM320单片机的DMA功能驱动库 +* 技术支持: http://www.synwit.com.cn/e/tool/gbook/?bid=1 +* 注意事项: +* 版本日期: V1.1.0 2017年10月25日 +* 升级记录: * * ******************************************************************************************************************************************* @@ -22,23 +22,23 @@ #include "SWM320_dma.h" /****************************************************************************************************************************************** -* : DMA_CHM_Config() -* ˵: DMAͨãڴ洢䣨FlashRAM䣩 -* : uint32_t chn ָҪõͨЧֵDMA_CH0DMA_CH1DMA_CH1 -* uint32_t src_addr Դֶַ룬ַ2λ00 -* uint32_t src_addr_incr 0 ̶ַ 1 ַ -* uint32_t dst_addr Ŀĵֶַ룬ַ2λ00 -* uint32_t dst_addr_incr 0 ̶ַ 1 ַ -* uint32_t num_word Ҫ˵1024 -* uint32_t int_en жʹܣ1 ݰɺж 0 ݰɺ󲻲ж -* : -* ע: ΪԪֽ +* 函数名称: DMA_CHM_Config() +* 功能说明: DMA通道配置，用于存储器间（如Flash和RAM间）搬运数据 +* 输 入: uint32_t chn 指定要配置的通道，有效值有DMA_CH0、DMA_CH1、DMA_CH2 +* uint32_t src_addr 源地址，必须字对齐，即地址的最低2位必须是00 +* uint32_t src_addr_incr 0 固定地址 1 地址递增 +* uint32_t dst_addr 目的地址，必须字对齐，即地址的最低2位必须是00 +* uint32_t dst_addr_incr 0 固定地址 1 地址递增 +* uint32_t num_word 要搬运的数据字数，最大1024 +* uint32_t int_en 中断使能，1 数据搬运完成后产生中断 0 数据搬运完成后不产生中断 +* 输 出: 无 +* 注意事项: 搬运数据量以字为单元，不是字节 ******************************************************************************************************************************************/ void DMA_CHM_Config(uint32_t chn, uint32_t src_addr, uint32_t src_addr_incr, uint32_t dst_addr, uint32_t dst_addr_incr, uint32_t num_word, uint32_t int_en) { - DMA->EN = 1; //ÿͨԼĿؿƣܿؿһֱ + DMA->EN = 1; //每个通道都有自己独立的开关控制，所以总开关可以是一直开启的 - DMA_CH_Close(chn); //ǰȹرոͨ + DMA_CH_Close(chn); //配置前先关闭该通道 DMA->CH[chn].SRC = src_addr; DMA->CH[chn].DST = dst_addr; @@ -50,10 +50,12 @@ void DMA_CHM_Config(uint32_t chn, uint32_t src_addr, uint32_t src_addr_incr, uin (dst_addr_incr << DMA_AM_DSTAM_Pos) | (0 << DMA_AM_BURST_Pos); - DMA->IF = (1 << chn); //жϱ־ + DMA->IF = (1 << chn); //清除中断标志 DMA->IE |= (1 << chn); - if (int_en) DMA->IM &= ~(1 << chn); - else DMA->IM |= (1 << chn); + if (int_en) + DMA->IM &= ~(1 << chn); + else + DMA->IM |= (1 << chn); if (int_en) { @@ -61,16 +63,16 @@ void DMA_CHM_Config(uint32_t chn, uint32_t src_addr, uint32_t src_addr_incr, uin } else { - //ܵNVIC_DisalbeIRQ(DMA_IRQn)ΪͨʹDMAж + //不能调用NVIC_DisalbeIRQ(DMA_IRQn)，因为其他通道可能使用DMA中断 } } /****************************************************************************************************************************************** -* : DMA_CH_Open() -* ˵: DMAͨ -* : uint32_t chn ָҪõͨЧֵDMA_CH0DMA_CH1DMA_CH1 -* : -* ע: +* 函数名称: DMA_CH_Open() +* 功能说明: DMA通道打开 +* 输 入: uint32_t chn 指定要配置的通道，有效值有DMA_CH0、DMA_CH1、DMA_CH2 +* 输 出: 无 +* 注意事项: 无 ******************************************************************************************************************************************/ void DMA_CH_Open(uint32_t chn) { @@ -78,11 +80,11 @@ void DMA_CH_Open(uint32_t chn) } /****************************************************************************************************************************************** -* : DMA_CH_Close() -* ˵: DMAͨر -* : uint32_t chn ָҪõͨЧֵDMA_CH0DMA_CH1DMA_CH1 -* : -* ע: +* 函数名称: DMA_CH_Close() +* 功能说明: DMA通道关闭 +* 输 入: uint32_t chn 指定要配置的通道，有效值有DMA_CH0、DMA_CH1、DMA_CH2 +* 输 出: 无 +* 注意事项: 无 ******************************************************************************************************************************************/ void DMA_CH_Close(uint32_t chn) { @@ -90,11 +92,11 @@ void DMA_CH_Close(uint32_t chn) } /****************************************************************************************************************************************** -* : DMA_CH_INTEn() -* ˵: DMAжʹܣݰɺ󴥷ж -* : uint32_t chn ָҪõͨЧֵDMA_CH0DMA_CH1DMA_CH1 -* : -* ע: +* 函数名称: DMA_CH_INTEn() +* 功能说明: DMA中断使能，数据搬运完成后触发中断 +* 输 入: uint32_t chn 指定要配置的通道，有效值有DMA_CH0、DMA_CH1、DMA_CH2 +* 输 出: 无 +* 注意事项: 无 ******************************************************************************************************************************************/ void DMA_CH_INTEn(uint32_t chn) { @@ -102,11 +104,11 @@ void DMA_CH_INTEn(uint32_t chn) } /****************************************************************************************************************************************** -* : DMA_CH_INTDis() -* ˵: DMAжϽֹݰɺ󲻴ж -* : uint32_t chn ָҪõͨЧֵDMA_CH0DMA_CH1DMA_CH1 -* : -* ע: +* 函数名称: DMA_CH_INTDis() +* 功能说明: DMA中断禁止，数据搬运完成后不触发中断 +* 输 入: uint32_t chn 指定要配置的通道，有效值有DMA_CH0、DMA_CH1、DMA_CH2 +* 输 出: 无 +* 注意事项: 无 ******************************************************************************************************************************************/ void DMA_CH_INTDis(uint32_t chn) { @@ -114,11 +116,11 @@ void DMA_CH_INTDis(uint32_t chn) } /****************************************************************************************************************************************** -* : DMA_CH_INTClr() -* ˵: DMAжϱ־ -* : uint32_t chn ָҪõͨЧֵDMA_CH0DMA_CH1DMA_CH1 -* : -* ע: +* 函数名称: DMA_CH_INTClr() +* 功能说明: DMA中断标志清除 +* 输 入: uint32_t chn 指定要配置的通道，有效值有DMA_CH0、DMA_CH1、DMA_CH2 +* 输 出: 无 +* 注意事项: 无 ******************************************************************************************************************************************/ void DMA_CH_INTClr(uint32_t chn) { @@ -126,11 +128,11 @@ void DMA_CH_INTClr(uint32_t chn) } /****************************************************************************************************************************************** -* : DMA_CH_INTStat() -* ˵: DMAж״̬ѯ -* : uint32_t chn ָҪõͨЧֵDMA_CH0DMA_CH1DMA_CH1 -* : uint32_t 1 ݰ 0 ݰδ -* ע: +* 函数名称: DMA_CH_INTStat() +* 功能说明: DMA中断状态查询 +* 输 入: uint32_t chn 指定要配置的通道，有效值有DMA_CH0、DMA_CH1、DMA_CH2 +* 输 出: uint32_t 1 数据搬运完成 0 数据搬运未完成 +* 注意事项: 无 ******************************************************************************************************************************************/ uint32_t DMA_CH_INTStat(uint32_t chn) { diff --git a/bsp/swm320-lq100/Libraries/SWM320_StdPeriph_Driver/SWM320_dma.h b/bsp/swm320-lq100/Libraries/SWM320_StdPeriph_Driver/SWM320_dma.h index fc4cd98ca8..b7391a0e9e 100644 --- a/bsp/swm320-lq100/Libraries/SWM320_StdPeriph_Driver/SWM320_dma.h +++ b/bsp/swm320-lq100/Libraries/SWM320_StdPeriph_Driver/SWM320_dma.h @@ -1,20 +1,17 @@ #ifndef __SWM320_DMA_H__ #define __SWM320_DMA_H__ +#define DMA_CH0 0 +#define DMA_CH1 1 +#define DMA_CH2 2 -#define DMA_CH0 0 -#define DMA_CH1 1 -#define DMA_CH2 2 - - -void DMA_CHM_Config(uint32_t chn, uint32_t src_addr, uint32_t src_addr_incr, uint32_t dst_addr, uint32_t dst_addr_incr, uint32_t num_word, uint32_t int_en); //DMAͨãڴ洢䣨FlashRAM䣩 -void DMA_CH_Open(uint32_t chn); //DMAͨ -void DMA_CH_Close(uint32_t chn); //DMAͨر - -void DMA_CH_INTEn(uint32_t chn); //DMAжʹܣݰɺ󴥷ж -void DMA_CH_INTDis(uint32_t chn); //DMAжϽֹݰɺ󲻴ж -void DMA_CH_INTClr(uint32_t chn); //DMAжϱ־ -uint32_t DMA_CH_INTStat(uint32_t chn); //DMAж״̬ѯ1 ݰ 0 ݰδ +void DMA_CHM_Config(uint32_t chn, uint32_t src_addr, uint32_t src_addr_incr, uint32_t dst_addr, uint32_t dst_addr_incr, uint32_t num_word, uint32_t int_en); //DMA通道配置，用于存储器间（如Flash和RAM间）搬运数据 +void DMA_CH_Open(uint32_t chn); //DMA通道打开 +void DMA_CH_Close(uint32_t chn); //DMA通道关闭 +void DMA_CH_INTEn(uint32_t chn); //DMA中断使能，数据搬运完成后触发中断 +void DMA_CH_INTDis(uint32_t chn); //DMA中断禁止，数据搬运完成后不触发中断 +void DMA_CH_INTClr(uint32_t chn); //DMA中断标志清除 +uint32_t DMA_CH_INTStat(uint32_t chn); //DMA中断状态查询，1 数据搬运完成 0 数据搬运未完成 #endif //__SWM320_DMA_H__ diff --git a/bsp/swm320-lq100/Libraries/SWM320_StdPeriph_Driver/SWM320_exti.c b/bsp/swm320-lq100/Libraries/SWM320_StdPeriph_Driver/SWM320_exti.c index 0214767e6b..6bebc75601 100644 --- a/bsp/swm320-lq100/Libraries/SWM320_StdPeriph_Driver/SWM320_exti.c +++ b/bsp/swm320-lq100/Libraries/SWM320_StdPeriph_Driver/SWM320_exti.c @@ -1,10 +1,10 @@ /****************************************************************************************************************************************** -* ļ: SWM320_exti.c -* ˵: SWM320ƬⲿжϹ -* ֧: http://www.synwit.com.cn/e/tool/gbook/?bid=1 -* ע: -* 汾: V1.1.0 20171025 -* ¼: +* 文件名称: SWM320_exti.c +* 功能说明: SWM320单片机的外部中断功能驱动库 +* 技术支持: http://www.synwit.com.cn/e/tool/gbook/?bid=1 +* 注意事项: +* 版本日期: V1.1.0 2017年10月25日 +* 升级记录: * ******************************************************************************************************************************************* * @attention @@ -21,57 +21,57 @@ #include "SWM320_exti.h" /****************************************************************************************************************************************** -* : EXTI_Init() -* ˵: ָⲿжϳʼ -* : GPIO_TypeDef * GPIOx ָⲿжϵGPIO˿ڣЧֵGPIOAGPIOBGPIOCGPIOMGPIONGPIOP -* uint32_t n ָⲿжϵGPIOţЧֵPIN0PIN1PIN2... ... PIN22PIN23 -* uint32_t mode ЧֵEXTI_FALL_EDGEEXTI_RISE_EDGEEXTI_BOTH_EDGEEXTI_LOW_LEVELEXTI_HIGH_LEVEL -* : -* ע: GPIOAGPIOBGPIOCGPIOMPIN0--7żԽNVICежϣGPIOA0_IRQnҲԽNVICжϣGPIOA_IRQn -* Բڴ˺еNVIC_EnableIRQ()ʹNVICжϣӶԸҪNVIC_EnableIRQ(GPIOA0_IRQn)NVIC_EnableIRQ(GPIOA_IRQn) +* 函数名称: EXTI_Init() +* 功能说明: 指定引脚外部中断初始化 +* 输 入: GPIO_TypeDef * GPIOx 指定产生外部中断的GPIO端口，有效值包括GPIOA、GPIOB、GPIOC、GPIOM、GPION、GPIOP +* uint32_t n 指定产生外部中断的GPIO引脚，有效值包括PIN0、PIN1、PIN2、... ... PIN22、PIN23 +* uint32_t mode 有效值有EXTI_FALL_EDGE、EXTI_RISE_EDGE、EXTI_BOTH_EDGE、EXTI_LOW_LEVEL、EXTI_HIGH_LEVEL +* 输 出: 无 +* 注意事项: 由于GPIOA、GPIOB、GPIOC、GPIOM的PIN0--7引脚即可以接入NVIC中的引脚中断（如GPIOA0_IRQn），也可以接入NVIC的组中断（GPIOA_IRQn）， +* 所以不在此函数中调用NVIC_EnableIRQ()使能NVIC中断，从而可以根据需要调用NVIC_EnableIRQ(GPIOA0_IRQn)和NVIC_EnableIRQ(GPIOA_IRQn) ******************************************************************************************************************************************/ void EXTI_Init(GPIO_TypeDef *GPIOx, uint32_t n, uint32_t mode) { - EXTI_Close(GPIOx, n); //ùؼĴǰȹر + EXTI_Close(GPIOx, n); //配置关键寄存器前先关闭 if (mode & 0x10) { - GPIOx->INTLVLTRG |= (0x01 << n); //ƽ + GPIOx->INTLVLTRG |= (0x01 << n); //电平触发 if (mode & 0x01) - GPIOx->INTRISEEN |= (0x01 << n); //ߵƽ + GPIOx->INTRISEEN |= (0x01 << n); //高电平触发 else - GPIOx->INTRISEEN &= ~(0x01 << n); //͵ƽ + GPIOx->INTRISEEN &= ~(0x01 << n); //低电平触发 } else { - GPIOx->INTLVLTRG &= ~(0x01 << n); //ش + GPIOx->INTLVLTRG &= ~(0x01 << n); //边沿触发 if (mode & 0x02) { - GPIOx->INTBE |= (0x01 << n); //˫ش + GPIOx->INTBE |= (0x01 << n); //双边沿触发 } else { - GPIOx->INTBE &= ~(0x01 << n); //ش + GPIOx->INTBE &= ~(0x01 << n); //单边沿触发 if (mode & 0x01) - GPIOx->INTRISEEN |= (0x01 << n); //ش + GPIOx->INTRISEEN |= (0x01 << n); //上升沿触发 else - GPIOx->INTRISEEN &= ~(0x01 << n); //½ش + GPIOx->INTRISEEN &= ~(0x01 << n); //下降沿触发 } } - GPIOx->INTCLR = (1 << n); //Ϊģʽÿܲж + GPIOx->INTCLR = (1 << n); //清除掉因为模式配置可能产生的中断 } /****************************************************************************************************************************************** -* : EXTI_Open() -* ˵: ָⲿжϴ򿪣ʹܣ -* : GPIO_TypeDef * GPIOx ָⲿжϵGPIO˿ڣЧֵGPIOAGPIOBGPIOCGPIOMGPIONGPIOP -* uint32_t n ָⲿжϵGPIOţЧֵPIN0PIN1PIN2... ... PIN22PIN23 -* : -* ע: +* 函数名称: EXTI_Open() +* 功能说明: 指定引脚外部中断打开（即使能） +* 输 入: GPIO_TypeDef * GPIOx 指定产生外部中断的GPIO端口，有效值包括GPIOA、GPIOB、GPIOC、GPIOM、GPION、GPIOP +* uint32_t n 指定产生外部中断的GPIO引脚，有效值包括PIN0、PIN1、PIN2、... ... PIN22、PIN23 +* 输 出: 无 +* 注意事项: 无 ******************************************************************************************************************************************/ void EXTI_Open(GPIO_TypeDef *GPIOx, uint32_t n) { @@ -79,12 +79,12 @@ void EXTI_Open(GPIO_TypeDef *GPIOx, uint32_t n) } /****************************************************************************************************************************************** -* : EXTI_Close() -* ˵: ָⲿжϹرգܣ -* : GPIO_TypeDef * GPIOx ָⲿжϵGPIO˿ڣЧֵGPIOAGPIOBGPIOCGPIOMGPIONGPIOP -* uint32_t n ָⲿжϵGPIOţЧֵPIN0PIN1PIN2... ... PIN22PIN23 -* : -* ע: +* 函数名称: EXTI_Close() +* 功能说明: 指定引脚外部中断关闭（即禁能） +* 输 入: GPIO_TypeDef * GPIOx 指定产生外部中断的GPIO端口，有效值包括GPIOA、GPIOB、GPIOC、GPIOM、GPION、GPIOP +* uint32_t n 指定产生外部中断的GPIO引脚，有效值包括PIN0、PIN1、PIN2、... ... PIN22、PIN23 +* 输 出: 无 +* 注意事项: 无 ******************************************************************************************************************************************/ void EXTI_Close(GPIO_TypeDef *GPIOx, uint32_t n) { @@ -92,12 +92,12 @@ void EXTI_Close(GPIO_TypeDef *GPIOx, uint32_t n) } /****************************************************************************************************************************************** -* : EXTI_State() -* ˵: ָǷ񴥷ж -* : GPIO_TypeDef * GPIOx ָⲿжϵGPIO˿ڣЧֵGPIOAGPIOBGPIOCGPIOMGPIONGPIOP -* uint32_t n ָⲿжϵGPIOţЧֵPIN0PIN1PIN2... ... PIN22PIN23 -* : uint32_t 1 Ŵж 0 δж -* ע: +* 函数名称: EXTI_State() +* 功能说明: 指定引脚是否触发了中断 +* 输 入: GPIO_TypeDef * GPIOx 指定产生外部中断的GPIO端口，有效值包括GPIOA、GPIOB、GPIOC、GPIOM、GPION、GPIOP +* uint32_t n 指定产生外部中断的GPIO引脚，有效值包括PIN0、PIN1、PIN2、... ... PIN22、PIN23 +* 输 出: uint32_t 1 此引脚触发了中断 0 此引脚未触发中断 +* 注意事项: 无 ******************************************************************************************************************************************/ uint32_t EXTI_State(GPIO_TypeDef *GPIOx, uint32_t n) { @@ -105,25 +105,25 @@ uint32_t EXTI_State(GPIO_TypeDef *GPIOx, uint32_t n) } /****************************************************************************************************************************************** -* : EXTI_RawState() -* ˵: ָǷ/жϴжϹرʱͨô˺ԲѯķʽǷ/жϴ -* : GPIO_TypeDef * GPIOx ָⲿжϵGPIO˿ڣЧֵGPIOAGPIOBGPIOCGPIOMGPIONGPIOP -* uint32_t n ָⲿжϵGPIOţЧֵPIN0PIN1PIN2... ... PIN22PIN23 -* : uint32_t 1 /жϴ 0 δ/жϴ -* ע: +* 函数名称: EXTI_RawState() +* 功能说明: 指定引脚是否满足过/了中断触发条件，当此中断关闭时可通过调用此函数以查询的方式检测引脚上是否满足过/了中断触发条件 +* 输 入: GPIO_TypeDef * GPIOx 指定产生外部中断的GPIO端口，有效值包括GPIOA、GPIOB、GPIOC、GPIOM、GPION、GPIOP +* uint32_t n 指定产生外部中断的GPIO引脚，有效值包括PIN0、PIN1、PIN2、... ... PIN22、PIN23 +* 输 出: uint32_t 1 此引脚满足过/了中断触发条件 0 此引脚未满足过/了中断触发条件 +* 注意事项: 无 ******************************************************************************************************************************************/ uint32_t EXTI_RawState(GPIO_TypeDef *GPIOx, uint32_t n) { - return (GPIOx->INTRAWSTAT >> 1) & 0x01; + return (GPIOx->INTRAWSTAT >> n) & 0x01; } /****************************************************************************************************************************************** -* : EXTI_Clear() -* ˵: ָⲿжжϱ־ٴνжϣ -* : GPIO_TypeDef * GPIOx ָⲿжϵGPIO˿ڣЧֵGPIOAGPIOBGPIOCGPIOMGPIONGPIOP -* uint32_t n ָⲿжϵGPIOţЧֵPIN0PIN1PIN2... ... PIN22PIN23 -* : -* ע: ֻشжϵı־ƽжϵı־޷ֻŵƽжϴӲԶ +* 函数名称: EXTI_Clear() +* 功能说明: 指定引脚外部中断清除（即清除中断标志，以免再次进入此中断） +* 输 入: GPIO_TypeDef * GPIOx 指定产生外部中断的GPIO端口，有效值包括GPIOA、GPIOB、GPIOC、GPIOM、GPION、GPIOP +* uint32_t n 指定产生外部中断的GPIO引脚，有效值包括PIN0、PIN1、PIN2、... ... PIN22、PIN23 +* 输 出: 无 +* 注意事项: 只能清除边沿触发中断的标志，电平触发中断的标志无法清除，只能在引脚电平不符合中断触发条件后硬件自动清除 ******************************************************************************************************************************************/ void EXTI_Clear(GPIO_TypeDef *GPIOx, uint32_t n) { diff --git a/bsp/swm320-lq100/Libraries/SWM320_StdPeriph_Driver/SWM320_exti.h b/bsp/swm320-lq100/Libraries/SWM320_StdPeriph_Driver/SWM320_exti.h index f645fa69f8..818d647745 100644 --- a/bsp/swm320-lq100/Libraries/SWM320_StdPeriph_Driver/SWM320_exti.h +++ b/bsp/swm320-lq100/Libraries/SWM320_StdPeriph_Driver/SWM320_exti.h @@ -1,20 +1,18 @@ #ifndef __SWM320_EXTI_H__ #define __SWM320_EXTI_H__ -void EXTI_Init(GPIO_TypeDef *GPIOx, uint32_t n, uint32_t mode); //ָⲿжϳʼ -void EXTI_Open(GPIO_TypeDef *GPIOx, uint32_t n); //ָⲿжϴ򿪣ʹܣ -void EXTI_Close(GPIO_TypeDef *GPIOx, uint32_t n); //ָⲿжϹرգܣ +void EXTI_Init(GPIO_TypeDef *GPIOx, uint32_t n, uint32_t mode); //指定引脚外部中断初始化 +void EXTI_Open(GPIO_TypeDef *GPIOx, uint32_t n); //指定引脚外部中断打开（即使能） +void EXTI_Close(GPIO_TypeDef *GPIOx, uint32_t n); //指定引脚外部中断关闭（即禁能） -uint32_t EXTI_State(GPIO_TypeDef *GPIOx, uint32_t n); //ָǷ񴥷ж -uint32_t EXTI_RawState(GPIO_TypeDef *GPIOx, uint32_t n); //ָǷ/жϴжϹرʱͨô˺ԲѯķʽǷ/жϴ -void EXTI_Clear(GPIO_TypeDef *GPIOx, uint32_t n); //ָⲿжжϱ־ٴνжϣ - - -#define EXTI_FALL_EDGE 0x00 //½شж -#define EXTI_RISE_EDGE 0x01 //شж -#define EXTI_BOTH_EDGE 0x02 //˫شж -#define EXTI_LOW_LEVEL 0x10 //͵ƽж -#define EXTI_HIGH_LEVEL 0x11 //ߵƽж +uint32_t EXTI_State(GPIO_TypeDef *GPIOx, uint32_t n); //指定引脚是否触发了中断 +uint32_t EXTI_RawState(GPIO_TypeDef *GPIOx, uint32_t n); //指定引脚是否满足过/了中断触发条件，当此中断关闭时可通过调用此函数以查询的方式检测引脚上是否满足过/了中断触发条件 +void EXTI_Clear(GPIO_TypeDef *GPIOx, uint32_t n); //指定引脚外部中断清除（即清除中断标志，以免再次进入此中断） +#define EXTI_FALL_EDGE 0x00 //下降沿触发中断 +#define EXTI_RISE_EDGE 0x01 //上升沿触发中断 +#define EXTI_BOTH_EDGE 0x02 //双边沿触发中断 +#define EXTI_LOW_LEVEL 0x10 //低电平触发中断 +#define EXTI_HIGH_LEVEL 0x11 //高电平触发中断 #endif //__SWM320_EXTI_H__ diff --git a/bsp/swm320-lq100/Libraries/SWM320_StdPeriph_Driver/SWM320_flash.c b/bsp/swm320-lq100/Libraries/SWM320_StdPeriph_Driver/SWM320_flash.c index fa619e566c..6cb6e125d4 100644 --- a/bsp/swm320-lq100/Libraries/SWM320_StdPeriph_Driver/SWM320_flash.c +++ b/bsp/swm320-lq100/Libraries/SWM320_StdPeriph_Driver/SWM320_flash.c @@ -1,10 +1,10 @@ /****************************************************************************************************************************************** -* ļ: SWM320_flash.c -* ˵: ʹоƬIAPܽƬFlashģEEPROMݣ󲻶ʧ -* ֧: http://www.synwit.com.cn/e/tool/gbook/?bid=1 -* ע: -* 汾: V1.1.0 20171025 -* ¼: +* 文件名称: SWM320_flash.c +* 功能说明: 使用芯片的IAP功能将片上Flash模拟成EEPROM来保存数据，掉电后不丢失 +* 技术支持: http://www.synwit.com.cn/e/tool/gbook/?bid=1 +* 注意事项: +* 版本日期: V1.1.0 2017年10月25日 +* 升级记录: ******************************************************************************************************************************************* * @attention * @@ -19,77 +19,77 @@ #include "SWM320.h" #include "SWM320_flash.h" +IAP_Cache_Reset_t IAP_Cache_Reset = (IAP_Cache_Reset_t)0x11000601; +IAP_Flash_Param_t IAP_Flash_Param = (IAP_Flash_Param_t)0x11000681; +IAP_Flash_Erase_t IAP_Flash_Erase = (IAP_Flash_Erase_t)0x11000781; +IAP_Flash_Write_t IAP_Flash_Write = (IAP_Flash_Write_t)0x11000801; -__attribute__((section("PlaceInRAM"))) -static void switchTo80M(void) +/****************************************************************************************************************************************** +* 函数名称: FLASH_Erase() +* 功能说明: 片内Flash擦除 +* 输 入: uint32_t addr 擦除地址，扇区大小为4K Byte +* 输 出: 无 +* 注意事项: 无 +******************************************************************************************************************************************/ +void FLASH_Erase(uint32_t addr) { - uint32_t i; + __disable_irq(); - for (i = 0; i < 50; i++) __NOP(); + IAP_Flash_Erase(addr / 0x1000); - FLASH->CFG0 = 0x4bf; - FLASH->CFG1 = 0xabfc7a6e; + IAP_Cache_Reset(); - for (i = 0; i < 50; i++) __NOP(); + __enable_irq(); } /****************************************************************************************************************************************** -* : FLASH_Erase() -* ˵: ƬFlash -* : uint32_t addr ַ -* : -* ע: +* 函数名称: FLASH_Write() +* 功能说明: 片内Flash写入 +* 输 入: uint32_t addr 写入地址 +* uint32_t buff[] 要写入的数据 +* uint32_t count 要写入数据的个数，以字为单位，且必须是4的整数倍，即最少写入4个字 +* 输 出: 无 +* 注意事项: 写入数据个数必须是4的整数倍，即最少写入4个字 ******************************************************************************************************************************************/ -void FLASH_Erase(uint32_t addr) +void FLASH_Write(uint32_t addr, uint32_t buff[], uint32_t count) { -// switchTo80M(); + __disable_irq(); - FLASH->ERASE = addr | ((uint32_t)1 << FLASH_ERASE_REQ_Pos); - while ((FLASH->STAT & FLASH_STAT_ERASE_GOING_Msk) == 0); - while ((FLASH->STAT & FLASH_STAT_ERASE_GOING_Msk) == 1); + IAP_Flash_Write(addr, (uint32_t)buff, count / 4); - FLASH->ERASE = 0; + IAP_Cache_Reset(); -// switchTo40M(); + __enable_irq(); } /****************************************************************************************************************************************** -* : FLASH_Write() -* ˵: ƬFlashд -* : uint32_t addr дַ -* uint32_t buff[] Ҫд -* uint32_t size ҪдݵĸΪλ -* : -* ע: +* 函数名称: Flash_Param_at_xMHz() +* 功能说明: 将Flash参数设置成xMHz主频下运行时所需的参数 +* 输 入: uint32_t x 可取值 +* 输 出: 无 +* 注意事项: 无 ******************************************************************************************************************************************/ -void FLASH_Write(uint32_t addr, uint32_t buff[], uint32_t size) +void Flash_Param_at_xMHz(uint32_t x) { - uint32_t i, j; - - switchTo80M(); - - FLASH->CACHE |= (1 << FLASH_CACHE_PROG_Pos); - - for (i = 0; i < size / 4; i++) + __disable_irq(); + switch (x) { - FLASH->ADDR = addr + i * 4 * 4; - - for (j = 0; j < 4; j++) - FLASH->DATA = buff[i * 4 + j]; - while ((FLASH->STAT & FLASH_STAT_FIFO_EMPTY_Msk) == 0) __NOP(); - } - if ((size % 4) != 0) - { - FLASH->ADDR = addr + i * 4 * 4; - - for (j = 0; j < size % 4; j++) - FLASH->DATA = buff[i * 4 + j]; - while ((FLASH->STAT & FLASH_STAT_FIFO_EMPTY_Msk) == 0) __NOP(); + case 30: + IAP_Flash_Param(0x489, 0xabf41f25); + break; + + case 40: + IAP_Flash_Param(0x489, 0xabf42929); + break; + + case 80: + IAP_Flash_Param(0x489, 0xabf8524d); + break; + + case 120: + default: + IAP_Flash_Param(0x48a, 0xabfc7a6e); + break; } - while (FLASH->STAT & FLASH_STAT_PROG_GOING_Msk); - - FLASH->CACHE |= (1 << FLASH_CACHE_CLEAR_Pos); - FLASH->CACHE = 0; - -// switchTo40M(); + __enable_irq(); } diff --git a/bsp/swm320-lq100/Libraries/SWM320_StdPeriph_Driver/SWM320_flash.h b/bsp/swm320-lq100/Libraries/SWM320_StdPeriph_Driver/SWM320_flash.h index 5a4bfbb89f..0352eeef82 100644 --- a/bsp/swm320-lq100/Libraries/SWM320_StdPeriph_Driver/SWM320_flash.h +++ b/bsp/swm320-lq100/Libraries/SWM320_StdPeriph_Driver/SWM320_flash.h @@ -1,9 +1,19 @@ #ifndef __SWM320_FLASH_H__ #define __SWM320_FLASH_H__ - void FLASH_Erase(uint32_t addr); -void FLASH_Write(uint32_t addr, uint32_t buff[], uint32_t size); +void FLASH_Write(uint32_t addr, uint32_t buff[], uint32_t count); + +void Flash_Param_at_xMHz(uint32_t x); + +typedef void (*IAP_Cache_Reset_t)(void); +typedef void (*IAP_Flash_Param_t)(uint32_t cfg0, uint32_t cfg1); +typedef void (*IAP_Flash_Erase_t)(uint32_t sector); +typedef void (*IAP_Flash_Write_t)(uint32_t flash_addr, uint32_t ram_addr, uint32_t count); +extern IAP_Cache_Reset_t IAP_Cache_Reset; +extern IAP_Flash_Param_t IAP_Flash_Param; +extern IAP_Flash_Erase_t IAP_Flash_Erase; +extern IAP_Flash_Write_t IAP_Flash_Write; #endif //__SWM320_FLASH_H__ diff --git a/bsp/swm320-lq100/Libraries/SWM320_StdPeriph_Driver/SWM320_gpio.c b/bsp/swm320-lq100/Libraries/SWM320_StdPeriph_Driver/SWM320_gpio.c index dd81e75952..5ec03c48f6 100644 --- a/bsp/swm320-lq100/Libraries/SWM320_StdPeriph_Driver/SWM320_gpio.c +++ b/bsp/swm320-lq100/Libraries/SWM320_StdPeriph_Driver/SWM320_gpio.c @@ -1,10 +1,10 @@ /****************************************************************************************************************************************** -* ļ: SWM320_gpio.c -* ˵: SWM320Ƭͨ -* ֧: http://www.synwit.com.cn/e/tool/gbook/?bid=1 -* ע: -* 汾: V1.1.0 20171025 -* ¼: +* 文件名称: SWM320_gpio.c +* 功能说明: SWM320单片机的通用输入输出功能驱动库 +* 技术支持: http://www.synwit.com.cn/e/tool/gbook/?bid=1 +* 注意事项: +* 版本日期: V1.1.0 2017年10月25日 +* 升级记录: * * ******************************************************************************************************************************************* @@ -21,17 +21,16 @@ #include "SWM320.h" #include "SWM320_gpio.h" - /****************************************************************************************************************************************** -* : GPIO_Init() -* ˵: ųʼŷ衢衢© -* : GPIO_TypeDef * GPIOx ָGPIO˿ڣЧֵGPIOAGPIOBGPIOCGPIOMGPIONGPIOP -* uint32_t n ָGPIOţЧֵPIN0PIN1PIN2... ... PIN22PIN23 -* uint32_t dir ŷ0 1 -* uint32_t pull_up 裬0 ر 1 -* uint32_t pull_down 裬0 ر 1 -* : -* ע: +* 函数名称: GPIO_Init() +* 功能说明: 引脚初始化，包含引脚方向、上拉电阻、下拉电阻 +* 输 入: GPIO_TypeDef * GPIOx 指定GPIO端口，有效值包括GPIOA、GPIOB、GPIOC、GPIOM、GPION、GPIOP +* uint32_t n 指定GPIO引脚，有效值包括PIN0、PIN1、PIN2、... ... PIN22、PIN23 +* uint32_t dir 引脚方向，0 输入 1 输出 +* uint32_t pull_up 上拉电阻，0 关闭上拉 1 开启上拉 +* uint32_t pull_down 下拉电阻，0 关闭下拉 1 开启下拉 +* 输 出: 无 +* 注意事项: GPIOA、GPIOC、GPIOM、GPIOP只有上拉，GPIOB、GPION只有下拉（PN0、PN1、PN2三个引脚有上拉没下拉） ******************************************************************************************************************************************/ void GPIO_Init(GPIO_TypeDef *GPIOx, uint32_t n, uint32_t dir, uint32_t pull_up, uint32_t pull_down) { @@ -40,7 +39,7 @@ void GPIO_Init(GPIO_TypeDef *GPIOx, uint32_t n, uint32_t dir, uint32_t pull_up, case ((uint32_t)GPIOA): SYS->CLKEN |= (0x01 << SYS_CLKEN_GPIOA_Pos); - PORT_Init(PORTA, n, 0, 1); //PORTA.PINnΪGPIOܣ뿪 + PORT_Init(PORTA, n, 0, 1); //PORTA.PINn引脚配置为GPIO功能，数字输入开启 if (dir == 1) { GPIOA->DIR |= (0x01 << n); @@ -59,7 +58,7 @@ void GPIO_Init(GPIO_TypeDef *GPIOx, uint32_t n, uint32_t dir, uint32_t pull_up, case ((uint32_t)GPIOB): SYS->CLKEN |= (0x01 << SYS_CLKEN_GPIOB_Pos); - PORT_Init(PORTB, n, 0, 1); //PORTB.PINnΪGPIOܣ뿪 + PORT_Init(PORTB, n, 0, 1); //PORTB.PINn引脚配置为GPIO功能，数字输入开启 if (dir == 1) { GPIOB->DIR |= (0x01 << n); @@ -78,7 +77,7 @@ void GPIO_Init(GPIO_TypeDef *GPIOx, uint32_t n, uint32_t dir, uint32_t pull_up, case ((uint32_t)GPIOC): SYS->CLKEN |= (0x01 << SYS_CLKEN_GPIOC_Pos); - PORT_Init(PORTC, n, 0, 1); //PORTC.PINnΪGPIOܣ뿪 + PORT_Init(PORTC, n, 0, 1); //PORTC.PINn引脚配置为GPIO功能，数字输入开启 if (dir == 1) { GPIOC->DIR |= (0x01 << n); @@ -97,7 +96,7 @@ void GPIO_Init(GPIO_TypeDef *GPIOx, uint32_t n, uint32_t dir, uint32_t pull_up, case ((uint32_t)GPIOM): SYS->CLKEN |= (0x01 << SYS_CLKEN_GPIOM_Pos); - PORT_Init(PORTM, n, 0, 1); //PORTM.PINnΪGPIOܣ뿪 + PORT_Init(PORTM, n, 0, 1); //PORTM.PINn引脚配置为GPIO功能，数字输入开启 if (dir == 1) { GPIOM->DIR |= (0x01 << n); @@ -116,7 +115,7 @@ void GPIO_Init(GPIO_TypeDef *GPIOx, uint32_t n, uint32_t dir, uint32_t pull_up, case ((uint32_t)GPION): SYS->CLKEN |= (0x01 << SYS_CLKEN_GPION_Pos); - PORT_Init(PORTN, n, 0, 1); //PORTN.PINnΪGPIOܣ뿪 + PORT_Init(PORTN, n, 0, 1); //PORTN.PINn引脚配置为GPIO功能，数字输入开启 if (dir == 1) { GPION->DIR |= (0x01 << n); @@ -135,7 +134,7 @@ void GPIO_Init(GPIO_TypeDef *GPIOx, uint32_t n, uint32_t dir, uint32_t pull_up, case ((uint32_t)GPIOP): SYS->CLKEN |= (0x01 << SYS_CLKEN_GPIOP_Pos); - PORT_Init(PORTP, n, 0, 1); //PORTP.PINnΪGPIOܣ뿪 + PORT_Init(PORTP, n, 0, 1); //PORTP.PINn引脚配置为GPIO功能，数字输入开启 if (dir == 1) { GPIOP->DIR |= (0x01 << n); @@ -154,12 +153,12 @@ void GPIO_Init(GPIO_TypeDef *GPIOx, uint32_t n, uint32_t dir, uint32_t pull_up, } /****************************************************************************************************************************************** -* : GPIO_SetBit() -* ˵: ָŵƽø -* : GPIO_TypeDef * GPIOx ָGPIO˿ڣЧֵGPIOAGPIOBGPIOCGPIOMGPIONGPIOP -* uint32_t n ָGPIOţЧֵPIN0PIN1PIN2... ... PIN22PIN23 -* : -* ע: +* 函数名称: GPIO_SetBit() +* 功能说明: 将参数指定的引脚电平置高 +* 输 入: GPIO_TypeDef * GPIOx 指定GPIO端口，有效值包括GPIOA、GPIOB、GPIOC、GPIOM、GPION、GPIOP +* uint32_t n 指定GPIO引脚，有效值包括PIN0、PIN1、PIN2、... ... PIN22、PIN23 +* 输 出: 无 +* 注意事项: 无 ******************************************************************************************************************************************/ void GPIO_SetBit(GPIO_TypeDef *GPIOx, uint32_t n) { @@ -167,12 +166,12 @@ void GPIO_SetBit(GPIO_TypeDef *GPIOx, uint32_t n) } /****************************************************************************************************************************************** -* : GPIO_ClrBit() -* ˵: ָŵƽõ -* : GPIO_TypeDef * GPIOx ָGPIO˿ڣЧֵGPIOAGPIOBGPIOCGPIOMGPIONGPIOP -* uint32_t n ָGPIOţЧֵPIN0PIN1PIN2... ... PIN22PIN23 -* : -* ע: +* 函数名称: GPIO_ClrBit() +* 功能说明: 将参数指定的引脚电平置低 +* 输 入: GPIO_TypeDef * GPIOx 指定GPIO端口，有效值包括GPIOA、GPIOB、GPIOC、GPIOM、GPION、GPIOP +* uint32_t n 指定GPIO引脚，有效值包括PIN0、PIN1、PIN2、... ... PIN22、PIN23 +* 输 出: 无 +* 注意事项: 无 ******************************************************************************************************************************************/ void GPIO_ClrBit(GPIO_TypeDef *GPIOx, uint32_t n) { @@ -180,12 +179,12 @@ void GPIO_ClrBit(GPIO_TypeDef *GPIOx, uint32_t n) } /****************************************************************************************************************************************** -* : GPIO_InvBit() -* ˵: ָŵƽת -* : GPIO_TypeDef * GPIOx ָGPIO˿ڣЧֵGPIOAGPIOBGPIOCGPIOMGPIONGPIOP -* uint32_t n ָGPIOţЧֵPIN0PIN1PIN2... ... PIN22PIN23 -* : -* ע: +* 函数名称: GPIO_InvBit() +* 功能说明: 将参数指定的引脚电平反转 +* 输 入: GPIO_TypeDef * GPIOx 指定GPIO端口，有效值包括GPIOA、GPIOB、GPIOC、GPIOM、GPION、GPIOP +* uint32_t n 指定GPIO引脚，有效值包括PIN0、PIN1、PIN2、... ... PIN22、PIN23 +* 输 出: 无 +* 注意事项: 无 ******************************************************************************************************************************************/ void GPIO_InvBit(GPIO_TypeDef *GPIOx, uint32_t n) { @@ -193,12 +192,12 @@ void GPIO_InvBit(GPIO_TypeDef *GPIOx, uint32_t n) } /****************************************************************************************************************************************** -* : GPIO_GetBit() -* ˵: ȡָŵĵƽ״̬ -* : GPIO_TypeDef * GPIOx ָGPIO˿ڣЧֵGPIOAGPIOBGPIOCGPIOMGPIONGPIOP -* uint32_t n ָGPIOţЧֵPIN0PIN1PIN2... ... PIN22PIN23 -* : ָŵĵƽ״̬ 0 ͵ƽ 1 ߵƽ -* ע: +* 函数名称: GPIO_GetBit() +* 功能说明: 读取参数指定的引脚的电平状态 +* 输 入: GPIO_TypeDef * GPIOx 指定GPIO端口，有效值包括GPIOA、GPIOB、GPIOC、GPIOM、GPION、GPIOP +* uint32_t n 指定GPIO引脚，有效值包括PIN0、PIN1、PIN2、... ... PIN22、PIN23 +* 输 出: 参数指定的引脚的电平状态 0 低电平 1 高电平 +* 注意事项: 无 ******************************************************************************************************************************************/ uint32_t GPIO_GetBit(GPIO_TypeDef *GPIOx, uint32_t n) { @@ -206,13 +205,13 @@ uint32_t GPIO_GetBit(GPIO_TypeDef *GPIOx, uint32_t n) } /****************************************************************************************************************************************** -* : GPIO_SetBits() -* ˵: ָĴnʼwλŵĵƽø -* : GPIO_TypeDef * GPIOx ָGPIO˿ڣЧֵGPIOAGPIOBGPIOCGPIOMGPIONGPIOP -* uint32_t n ָGPIOţЧֵPIN0PIN1PIN2... ... PIN22PIN23 -* uint32_t w ָҪŵƽøߵŵĸ -* : -* ע: +* 函数名称: GPIO_SetBits() +* 功能说明: 将参数指定的从n开始的w位连续引脚的电平置高 +* 输 入: GPIO_TypeDef * GPIOx 指定GPIO端口，有效值包括GPIOA、GPIOB、GPIOC、GPIOM、GPION、GPIOP +* uint32_t n 指定GPIO引脚，有效值包括PIN0、PIN1、PIN2、... ... PIN22、PIN23 +* uint32_t w 指定要将引脚电平置高的引脚的个数 +* 输 出: 无 +* 注意事项: 无 ******************************************************************************************************************************************/ void GPIO_SetBits(GPIO_TypeDef *GPIOx, uint32_t n, uint32_t w) { @@ -224,13 +223,13 @@ void GPIO_SetBits(GPIO_TypeDef *GPIOx, uint32_t n, uint32_t w) } /****************************************************************************************************************************************** -* : GPIO_ClrBits() -* ˵: ָĴnʼwλŵĵƽõ -* : GPIO_TypeDef * GPIOx ָGPIO˿ڣЧֵGPIOAGPIOBGPIOCGPIOMGPIONGPIOP -* uint32_t n ָGPIOţЧֵPIN0PIN1PIN2... ... PIN22PIN23 -* uint32_t w ָҪŵƽõ͵ŵĸ -* : -* ע: +* 函数名称: GPIO_ClrBits() +* 功能说明: 将参数指定的从n开始的w位连续引脚的电平置低 +* 输 入: GPIO_TypeDef * GPIOx 指定GPIO端口，有效值包括GPIOA、GPIOB、GPIOC、GPIOM、GPION、GPIOP +* uint32_t n 指定GPIO引脚，有效值包括PIN0、PIN1、PIN2、... ... PIN22、PIN23 +* uint32_t w 指定要将引脚电平置低的引脚的个数 +* 输 出: 无 +* 注意事项: 无 ******************************************************************************************************************************************/ void GPIO_ClrBits(GPIO_TypeDef *GPIOx, uint32_t n, uint32_t w) { @@ -242,13 +241,13 @@ void GPIO_ClrBits(GPIO_TypeDef *GPIOx, uint32_t n, uint32_t w) } /****************************************************************************************************************************************** -* : GPIO_InvBits() -* ˵: ָĴnʼwλŵĵƽת -* : GPIO_TypeDef * GPIOx ָGPIO˿ڣЧֵGPIOAGPIOBGPIOCGPIOMGPIONGPIOP -* uint32_t n ָGPIOţЧֵPIN0PIN1PIN2... ... PIN22PIN23 -* uint32_t w ָҪŵƽתŵĸ -* : -* ע: +* 函数名称: GPIO_InvBits() +* 功能说明: 将参数指定的从n开始的w位连续引脚的电平反转 +* 输 入: GPIO_TypeDef * GPIOx 指定GPIO端口，有效值包括GPIOA、GPIOB、GPIOC、GPIOM、GPION、GPIOP +* uint32_t n 指定GPIO引脚，有效值包括PIN0、PIN1、PIN2、... ... PIN22、PIN23 +* uint32_t w 指定要将引脚电平反转的引脚的个数 +* 输 出: 无 +* 注意事项: 无 ******************************************************************************************************************************************/ void GPIO_InvBits(GPIO_TypeDef *GPIOx, uint32_t n, uint32_t w) { @@ -260,14 +259,14 @@ void GPIO_InvBits(GPIO_TypeDef *GPIOx, uint32_t n, uint32_t w) } /****************************************************************************************************************************************** -* : GPIO_GetBits() -* ˵: ȡָĴnʼwλŵĵƽ״̬ -* : GPIO_TypeDef * GPIOx ָGPIO˿ڣЧֵGPIOAGPIOBGPIOCGPIOMGPIONGPIOP -* uint32_t n ָGPIOţЧֵPIN0PIN1PIN2... ... PIN22PIN23 -* uint32_t w ָҪŵƽøߵŵĸ -* : ָĴnʼwλŵĵƽ״̬ 0 ͵ƽ 1 ߵƽ -* ֵĵ0λʾnĵƽ״ֵ̬ĵ1λʾn+1ĵƽ״̬... ...ֵĵwλʾn+wĵƽ״̬ -* ע: +* 函数名称: GPIO_GetBits() +* 功能说明: 读取参数指定的从n开始的w位连续引脚的电平状态 +* 输 入: GPIO_TypeDef * GPIOx 指定GPIO端口，有效值包括GPIOA、GPIOB、GPIOC、GPIOM、GPION、GPIOP +* uint32_t n 指定GPIO引脚，有效值包括PIN0、PIN1、PIN2、... ... PIN22、PIN23 +* uint32_t w 指定要将引脚电平置高的引脚的个数 +* 输 出: 参数指定的从n开始的w位连续引脚的电平状态 0 低电平 1 高电平 +* 返回值的第0位表示引脚n的电平状态、返回值的第1位表示引脚n+1的电平状态... ...返回值的第w位表示引脚n+w的电平状态 +* 注意事项: 无 ******************************************************************************************************************************************/ uint32_t GPIO_GetBits(GPIO_TypeDef *GPIOx, uint32_t n, uint32_t w) { @@ -277,3 +276,102 @@ uint32_t GPIO_GetBits(GPIO_TypeDef *GPIOx, uint32_t n, uint32_t w) return ((GPIOx->DATA >> n) & bits); } + +/****************************************************************************************************************************************** +* 函数名称: GPIO_AtomicSetBit() +* 功能说明: 将参数指定的引脚电平置高，确保引脚”读-改-写“操作的原子性（不被中断ISR打断） +* 输 入: GPIO_TypeDef * GPIOx 指定GPIO端口，有效值包括GPIOA、GPIOB、GPIOC、GPIOD +* uint32_t n 指定GPIO引脚，有效值包括PIN0、PIN1、PIN2、... ... PIN14、PIN15 +* 输 出: 无 +* 注意事项: 当GPIOx的16个引脚中，有些在主循环中操作，有些在中断ISR中操作时，GPIOx的引脚必须都用GPIO_Atomic类型函数操作 +******************************************************************************************************************************************/ +void GPIO_AtomicSetBit(GPIO_TypeDef *GPIOx, uint32_t n) +{ + *((volatile uint32_t *)(0x42000000 + ((uint32_t)&GPIOx->DATA - 0x40000000) * 32 + n * 4)) = 1; +} + +/****************************************************************************************************************************************** +* 函数名称: GPIO_AtomicClrBit() +* 功能说明: 将参数指定的引脚电平置低，确保引脚”读-改-写“操作的原子性（不被中断ISR打断） +* 输 入: GPIO_TypeDef * GPIOx 指定GPIO端口，有效值包括GPIOA、GPIOB、GPIOC、GPIOD +* uint32_t n 指定GPIO引脚，有效值包括PIN0、PIN1、PIN2、... ... PIN14、PIN15 +* 输 出: 无 +* 注意事项: 当GPIOx的16个引脚中，有些在主循环中操作，有些在中断ISR中操作时，GPIOx的引脚必须都用GPIO_Atomic类型函数操作 +******************************************************************************************************************************************/ +void GPIO_AtomicClrBit(GPIO_TypeDef *GPIOx, uint32_t n) +{ + *((volatile uint32_t *)(0x42000000 + ((uint32_t)&GPIOx->DATA - 0x40000000) * 32 + n * 4)) = 0; +} + +/****************************************************************************************************************************************** +* 函数名称: GPIO_AtomicInvBit() +* 功能说明: 将参数指定的引脚电平反转，确保引脚”读-改-写“操作的原子性（不被中断ISR打断） +* 输 入: GPIO_TypeDef * GPIOx 指定GPIO端口，有效值包括GPIOA、GPIOB、GPIOC、GPIOD +* uint32_t n 指定GPIO引脚，有效值包括PIN0、PIN1、PIN2、... ... PIN14、PIN15 +* 输 出: 无 +* 注意事项: 当GPIOx的16个引脚中，有些在主循环中操作，有些在中断ISR中操作时，GPIOx的引脚必须都用GPIO_Atomic类型函数操作 +******************************************************************************************************************************************/ +void GPIO_AtomicInvBit(GPIO_TypeDef *GPIOx, uint32_t n) +{ + *((volatile uint32_t *)(0x42000000 + ((uint32_t)&GPIOx->DATA - 0x40000000) * 32 + n * 4)) = 1 - *((volatile uint32_t *)(0x42000000 + ((uint32_t)&GPIOx->DATA - 0x40000000) * 32 + n * 4)); +} + +/****************************************************************************************************************************************** +* 函数名称: GPIO_AtomicSetBits() +* 功能说明: 将参数指定的从n开始的w位连续引脚的电平置高，确保引脚”读-改-写“操作的原子性（不被中断ISR打断） +* 输 入: GPIO_TypeDef * GPIOx 指定GPIO端口，有效值包括GPIOA、GPIOB、GPIOC、GPIOD +* uint32_t n 指定GPIO引脚，有效值包括PIN0、PIN1、PIN2、... ... PIN14、PIN15 +* uint32_t w 指定要将引脚电平置高的引脚的个数 +* 输 出: 无 +* 注意事项: 当GPIOx的16个引脚中，有些在主循环中操作，有些在中断ISR中操作时，GPIOx的引脚必须都用GPIO_Atomic类型函数操作 +******************************************************************************************************************************************/ +void GPIO_AtomicSetBits(GPIO_TypeDef *GPIOx, uint32_t n, uint32_t w) +{ + uint32_t bits; + + bits = 0xFFFFFF >> (24 - w); + + __disable_irq(); + GPIOx->DATA |= (bits << n); + __enable_irq(); +} + +/****************************************************************************************************************************************** +* 函数名称: GPIO_AtomicClrBits() +* 功能说明: 将参数指定的从n开始的w位连续引脚的电平置低，确保引脚”读-改-写“操作的原子性（不被中断ISR打断） +* 输 入: GPIO_TypeDef * GPIOx 指定GPIO端口，有效值包括GPIOA、GPIOB、GPIOC、GPIOD +* uint32_t n 指定GPIO引脚，有效值包括PIN0、PIN1、PIN2、... ... PIN14、PIN15 +* uint32_t w 指定要将引脚电平置低的引脚的个数 +* 输 出: 无 +* 注意事项: 当GPIOx的16个引脚中，有些在主循环中操作，有些在中断ISR中操作时，GPIOx的引脚必须都用GPIO_Atomic类型函数操作 +******************************************************************************************************************************************/ +void GPIO_AtomicClrBits(GPIO_TypeDef *GPIOx, uint32_t n, uint32_t w) +{ + uint32_t bits; + + bits = 0xFFFFFF >> (24 - w); + + __disable_irq(); + GPIOx->DATA &= ~(bits << n); + __enable_irq(); +} + +/****************************************************************************************************************************************** +* 函数名称: GPIO_AtomicInvBits() +* 功能说明: 将参数指定的从n开始的w位连续引脚的电平反转，确保引脚”读-改-写“操作的原子性（不被中断ISR打断） +* 输 入: GPIO_TypeDef * GPIOx 指定GPIO端口，有效值包括GPIOA、GPIOB、GPIOC、GPIOD +* uint32_t n 指定GPIO引脚，有效值包括PIN0、PIN1、PIN2、... ... PIN14、PIN15 +* uint32_t w 指定要将引脚电平反转的引脚的个数 +* 输 出: 无 +* 注意事项: 当GPIOx的16个引脚中，有些在主循环中操作，有些在中断ISR中操作时，GPIOx的引脚必须都用GPIO_Atomic类型函数操作 +******************************************************************************************************************************************/ +void GPIO_AtomicInvBits(GPIO_TypeDef *GPIOx, uint32_t n, uint32_t w) +{ + uint32_t bits; + + bits = 0xFFFFFF >> (24 - w); + + __disable_irq(); + GPIOx->DATA ^= (bits << n); + __enable_irq(); +} diff --git a/bsp/swm320-lq100/Libraries/SWM320_StdPeriph_Driver/SWM320_gpio.h b/bsp/swm320-lq100/Libraries/SWM320_StdPeriph_Driver/SWM320_gpio.h index a0f84999bd..056f17b07b 100644 --- a/bsp/swm320-lq100/Libraries/SWM320_StdPeriph_Driver/SWM320_gpio.h +++ b/bsp/swm320-lq100/Libraries/SWM320_StdPeriph_Driver/SWM320_gpio.h @@ -1,17 +1,22 @@ #ifndef __SWM320_GPIO_H__ #define __SWM320_GPIO_H__ +void GPIO_Init(GPIO_TypeDef *GPIOx, uint32_t n, uint32_t dir, uint32_t pull_up, uint32_t pull_down); //引脚初始化，包含引脚方向、上拉电阻、下拉电阻 -void GPIO_Init(GPIO_TypeDef *GPIOx, uint32_t n, uint32_t dir, uint32_t pull_up, uint32_t pull_down); //ųʼŷ衢 - -void GPIO_SetBit(GPIO_TypeDef *GPIOx, uint32_t n); //ָŵƽø -void GPIO_ClrBit(GPIO_TypeDef *GPIOx, uint32_t n); //ָŵƽõ -void GPIO_InvBit(GPIO_TypeDef *GPIOx, uint32_t n); //ָŵƽת -uint32_t GPIO_GetBit(GPIO_TypeDef *GPIOx, uint32_t n); //ȡָŵĵƽ״̬ -void GPIO_SetBits(GPIO_TypeDef *GPIOx, uint32_t n, uint32_t w); //ָĴnʼwλŵĵƽø -void GPIO_ClrBits(GPIO_TypeDef *GPIOx, uint32_t n, uint32_t w); //ָĴnʼwλŵĵƽõ -void GPIO_InvBits(GPIO_TypeDef *GPIOx, uint32_t n, uint32_t w); //ָĴnʼwλŵĵƽת -uint32_t GPIO_GetBits(GPIO_TypeDef *GPIOx, uint32_t n, uint32_t w); //ȡָĴnʼwλŵĵƽ״̬ +void GPIO_SetBit(GPIO_TypeDef *GPIOx, uint32_t n); //将参数指定的引脚电平置高 +void GPIO_ClrBit(GPIO_TypeDef *GPIOx, uint32_t n); //将参数指定的引脚电平置低 +void GPIO_InvBit(GPIO_TypeDef *GPIOx, uint32_t n); //将参数指定的引脚电平反转 +uint32_t GPIO_GetBit(GPIO_TypeDef *GPIOx, uint32_t n); //读取参数指定的引脚的电平状态 +void GPIO_SetBits(GPIO_TypeDef *GPIOx, uint32_t n, uint32_t w); //将参数指定的从n开始的w位连续引脚的电平置高 +void GPIO_ClrBits(GPIO_TypeDef *GPIOx, uint32_t n, uint32_t w); //将参数指定的从n开始的w位连续引脚的电平置低 +void GPIO_InvBits(GPIO_TypeDef *GPIOx, uint32_t n, uint32_t w); //将参数指定的从n开始的w位连续引脚的电平反转 +uint32_t GPIO_GetBits(GPIO_TypeDef *GPIOx, uint32_t n, uint32_t w); //读取参数指定的从n开始的w位连续引脚的电平状态 +void GPIO_AtomicSetBit(GPIO_TypeDef *GPIOx, uint32_t n); +void GPIO_AtomicClrBit(GPIO_TypeDef *GPIOx, uint32_t n); +void GPIO_AtomicInvBit(GPIO_TypeDef *GPIOx, uint32_t n); +void GPIO_AtomicSetBits(GPIO_TypeDef *GPIOx, uint32_t n, uint32_t w); +void GPIO_AtomicClrBits(GPIO_TypeDef *GPIOx, uint32_t n, uint32_t w); +void GPIO_AtomicInvBits(GPIO_TypeDef *GPIOx, uint32_t n, uint32_t w); #endif //__SWM320_GPIO_H__ diff --git a/bsp/swm320-lq100/Libraries/SWM320_StdPeriph_Driver/SWM320_i2c.c b/bsp/swm320-lq100/Libraries/SWM320_StdPeriph_Driver/SWM320_i2c.c index 34de5c5610..c69378ca1a 100644 --- a/bsp/swm320-lq100/Libraries/SWM320_StdPeriph_Driver/SWM320_i2c.c +++ b/bsp/swm320-lq100/Libraries/SWM320_StdPeriph_Driver/SWM320_i2c.c @@ -1,10 +1,10 @@ /****************************************************************************************************************************************** -* ļ: SWM320_i2c.c -* ˵: SWM320ƬI2Cнӿڹ -* ֧: http://www.synwit.com.cn/e/tool/gbook/?bid=1 -* ע: -* 汾: V1.1.0 20171025 -* ¼: +* 文件名称: SWM320_i2c.c +* 功能说明: SWM320单片机的I2C串行接口功能驱动库 +* 技术支持: http://www.synwit.com.cn/e/tool/gbook/?bid=1 +* 注意事项: +* 版本日期: V1.1.0 2017年10月25日 +* 升级记录: * * ******************************************************************************************************************************************* @@ -22,12 +22,12 @@ #include "SWM320_i2c.h" /****************************************************************************************************************************************** -* : I2C_Init() -* ˵: I2Cʼ -* : I2C_TypeDef * I2Cx ָҪõI2CЧֵI2C0I2C1 -* I2C_InitStructure * initStruct I2C趨ֵĽṹ -* : -* ע: ģֻܹģʽ +* 函数名称: I2C_Init() +* 功能说明: I2C初始化 +* 输 入: I2C_TypeDef * I2Cx 指定要被设置的I2C，有效值包括I2C0、I2C1 +* I2C_InitStructure * initStruct 包含I2C相关设定值的结构体 +* 输 出: 无 +* 注意事项: 模块只能工作于主机模式 ******************************************************************************************************************************************/ void I2C_Init(I2C_TypeDef *I2Cx, I2C_InitStructure *initStruct) { @@ -42,13 +42,13 @@ void I2C_Init(I2C_TypeDef *I2Cx, I2C_InitStructure *initStruct) break; } - I2C_Close(I2Cx); //һЩؼĴֻI2Cرʱ + I2C_Close(I2Cx); //一些关键寄存器只能在I2C关闭时设置 if (initStruct->Master == 1) { I2Cx->CLKDIV = SystemCoreClock / 5 / initStruct->MstClk; - I2Cx->MSTCMD = (I2Cx->MSTCMD & (~I2C_MSTCMD_IF_Msk)) | (1 << I2C_MSTCMD_IF_Pos); //ʹж֮ǰжϱ־ + I2Cx->MSTCMD = (I2Cx->MSTCMD & (~I2C_MSTCMD_IF_Msk)) | (1 << I2C_MSTCMD_IF_Pos); //使能中断之前先清除中断标志 I2Cx->CTRL &= ~I2C_CTRL_MSTIE_Msk; I2Cx->CTRL |= (initStruct->MstIEn << I2C_CTRL_MSTIE_Pos); @@ -86,21 +86,21 @@ void I2C_Init(I2C_TypeDef *I2Cx, I2C_InitStructure *initStruct) (initStruct->Addr7b << I2C_SLVCR_ADDR7b_Pos) | (initStruct->SlvAddr << I2C_SLVCR_ADDR_Pos); - I2Cx->SLVIF = I2C_SLVIF_RXEND_Msk | I2C_SLVIF_TXEND_Msk | I2C_SLVIF_STADET_Msk | I2C_SLVIF_STODET_Msk; //жϱ־ + I2Cx->SLVIF = I2C_SLVIF_RXEND_Msk | I2C_SLVIF_TXEND_Msk | I2C_SLVIF_STADET_Msk | I2C_SLVIF_STODET_Msk; //清中断标志 I2Cx->SLVCR &= ~(I2C_SLVCR_IM_RXEND_Msk | I2C_SLVCR_IM_TXEND_Msk | I2C_SLVCR_IM_STADET_Msk | I2C_SLVCR_IM_STODET_Msk | I2C_SLVCR_IM_RDREQ_Msk | I2C_SLVCR_IM_WRREQ_Msk); - I2Cx->SLVCR |= ((initStruct->SlvRxEndIEn ? 0 : 1) << I2C_SLVCR_IM_RXEND_Pos) | - ((initStruct->SlvTxEndIEn ? 0 : 1) << I2C_SLVCR_IM_TXEND_Pos) | + I2Cx->SLVCR |= ((initStruct->SlvRxEndIEn ? 0 : 1) << I2C_SLVCR_IM_RXEND_Pos) | + ((initStruct->SlvTxEndIEn ? 0 : 1) << I2C_SLVCR_IM_TXEND_Pos) | ((initStruct->SlvSTADetIEn ? 0 : 1) << I2C_SLVCR_IM_STADET_Pos) | ((initStruct->SlvSTODetIEn ? 0 : 1) << I2C_SLVCR_IM_STODET_Pos) | - ((initStruct->SlvRdReqIEn ? 0 : 1) << I2C_SLVCR_IM_RDREQ_Pos) | - ((initStruct->SlvWrReqIEn ? 0 : 1) << I2C_SLVCR_IM_WRREQ_Pos); + ((initStruct->SlvRdReqIEn ? 0 : 1) << I2C_SLVCR_IM_RDREQ_Pos) | + ((initStruct->SlvWrReqIEn ? 0 : 1) << I2C_SLVCR_IM_WRREQ_Pos); switch ((uint32_t)I2Cx) { case ((uint32_t)I2C0): if (initStruct->SlvRxEndIEn | initStruct->SlvTxEndIEn | initStruct->SlvSTADetIEn | - initStruct->SlvSTODetIEn | initStruct->SlvRdReqIEn | initStruct->SlvWrReqIEn) + initStruct->SlvSTODetIEn | initStruct->SlvRdReqIEn | initStruct->SlvWrReqIEn) { NVIC_EnableIRQ(I2C0_IRQn); } @@ -112,7 +112,7 @@ void I2C_Init(I2C_TypeDef *I2Cx, I2C_InitStructure *initStruct) case ((uint32_t)I2C1): if (initStruct->SlvRxEndIEn | initStruct->SlvTxEndIEn | initStruct->SlvSTADetIEn | - initStruct->SlvSTODetIEn | initStruct->SlvRdReqIEn | initStruct->SlvWrReqIEn) + initStruct->SlvSTODetIEn | initStruct->SlvRdReqIEn | initStruct->SlvWrReqIEn) { NVIC_EnableIRQ(I2C1_IRQn); } @@ -126,11 +126,11 @@ void I2C_Init(I2C_TypeDef *I2Cx, I2C_InitStructure *initStruct) } /****************************************************************************************************************************************** -* : I2C_Open() -* ˵: I2C򿪣շ -* : I2C_TypeDef * I2Cx ָҪõI2CЧֵI2C0I2C1 -* : -* ע: +* 函数名称: I2C_Open() +* 功能说明: I2C打开，允许收发 +* 输 入: I2C_TypeDef * I2Cx 指定要被设置的I2C，有效值包括I2C0、I2C1 +* 输 出: 无 +* 注意事项: 无 ******************************************************************************************************************************************/ void I2C_Open(I2C_TypeDef *I2Cx) { @@ -138,13 +138,82 @@ void I2C_Open(I2C_TypeDef *I2Cx) } /****************************************************************************************************************************************** -* : I2C_Close() -* ˵: I2Cرգֹշ -* : I2C_TypeDef * I2Cx ָҪõI2CЧֵI2C0I2C1 -* : -* ע: +* 函数名称: I2C_Close() +* 功能说明: I2C关闭，禁止收发 +* 输 入: I2C_TypeDef * I2Cx 指定要被设置的I2C，有效值包括I2C0、I2C1 +* 输 出: 无 +* 注意事项: 无 ******************************************************************************************************************************************/ void I2C_Close(I2C_TypeDef *I2Cx) { I2Cx->CTRL &= ~I2C_CTRL_EN_Msk; } + +/****************************************************************************************************************************************** +* 函数名称: I2C_Start() +* 功能说明: 产生起始信号并发送设备地址 +* 输 入: I2C_TypeDef * I2Cx 指定要被设置的I2C，有效值包括I2C0、I2C1 +* uint8_t addr 设备地址 +* 输 出: uint8_t 1 接收到ACK 0 接收到NACK +* 注意事项: 无 +******************************************************************************************************************************************/ +uint8_t I2C_Start(I2C_TypeDef *I2Cx, uint8_t addr) +{ + I2Cx->MSTDAT = addr; + I2Cx->MSTCMD = (1 << I2C_MSTCMD_STA_Pos) | + (1 << I2C_MSTCMD_WR_Pos); //发送起始位和从机地址 + while (I2Cx->MSTCMD & I2C_MSTCMD_TIP_Msk) + __NOP(); //等待发送完成 + + return (I2Cx->MSTCMD & I2C_MSTCMD_RXACK_Msk) ? 0 : 1; +} + +/****************************************************************************************************************************************** +* 函数名称: I2C_Stop() +* 功能说明: 产生停止信号 +* 输 入: I2C_TypeDef * I2Cx 指定要被设置的I2C，有效值包括I2C0、I2C1 +* 输 出: 无 +* 注意事项: 无 +******************************************************************************************************************************************/ +void I2C_Stop(I2C_TypeDef *I2Cx) +{ + I2Cx->MSTCMD = (1 << I2C_MSTCMD_STO_Pos); + while (I2Cx->MSTCMD & I2C_MSTCMD_TIP_Msk) + __NOP(); //等待发送完成 +} + +/****************************************************************************************************************************************** +* 函数名称: I2C_Write() +* 功能说明: 写入一个数据 +* 输 入: I2C_TypeDef * I2Cx 指定要被设置的I2C，有效值包括I2C0、I2C1 +* uint8_t data 要写的数据 +* 输 出: uint8_t 1 接收到ACK 0 接收到NACK +* 注意事项: 无 +******************************************************************************************************************************************/ +uint8_t I2C_Write(I2C_TypeDef *I2Cx, uint8_t data) +{ + I2Cx->MSTDAT = data; + I2Cx->MSTCMD = (1 << I2C_MSTCMD_WR_Pos); + while (I2Cx->MSTCMD & I2C_MSTCMD_TIP_Msk) + __NOP(); //等待发送完成 + + return (I2Cx->MSTCMD & I2C_MSTCMD_RXACK_Msk) ? 0 : 1; +} + +/****************************************************************************************************************************************** +* 函数名称: I2C_Read() +* 功能说明: 读取一个数据 +* 输 入: I2C_TypeDef * I2Cx 指定要被设置的I2C，有效值包括I2C0、I2C1 +* uint8_t ack 1 发送ACK 0 发送NACK +* 输 出: uint8_t 读取到的数据 +* 注意事项: 无 +******************************************************************************************************************************************/ +uint8_t I2C_Read(I2C_TypeDef *I2Cx, uint8_t ack) +{ + I2Cx->MSTCMD = (1 << I2C_MSTCMD_RD_Pos) | + ((ack ? 0 : 1) << I2C_MSTCMD_ACK_Pos); + while (I2Cx->MSTCMD & I2C_MSTCMD_TIP_Msk) + __NOP(); //等待接收完成 + + return I2Cx->MSTDAT; +} diff --git a/bsp/swm320-lq100/Libraries/SWM320_StdPeriph_Driver/SWM320_i2c.h b/bsp/swm320-lq100/Libraries/SWM320_StdPeriph_Driver/SWM320_i2c.h index 769f5a2b55..8547328b35 100644 --- a/bsp/swm320-lq100/Libraries/SWM320_StdPeriph_Driver/SWM320_i2c.h +++ b/bsp/swm320-lq100/Libraries/SWM320_StdPeriph_Driver/SWM320_i2c.h @@ -3,25 +3,29 @@ typedef struct { - uint8_t Master; //1 ģʽ - uint8_t Addr7b; //1 7λַ 0 10λַ + uint8_t Master; //1 主机模式 + uint8_t Addr7b; //1 7位地址 0 10位地址 - uint32_t MstClk; //ʱƵ - uint8_t MstIEn; //ģʽжʹ + uint32_t MstClk; //主机传输时钟频率 + uint8_t MstIEn; //主机模式中断使能 - uint16_t SlvAddr; //ӻַ - uint8_t SlvRxEndIEn; //ӻжʹ - uint8_t SlvTxEndIEn; //ӻжʹ - uint8_t SlvSTADetIEn; //ӻ⵽ʼжʹ - uint8_t SlvSTODetIEn; //ӻ⵽ֹжʹ - uint8_t SlvRdReqIEn; //ӻյжʹ - uint8_t SlvWrReqIEn; //ӻյджʹ + uint16_t SlvAddr; //从机地址 + uint8_t SlvRxEndIEn; //从机接收完成中断使能 + uint8_t SlvTxEndIEn; //从机发送完成中断使能 + uint8_t SlvSTADetIEn; //从机检测到起始中断使能 + uint8_t SlvSTODetIEn; //从机检测到终止中断使能 + uint8_t SlvRdReqIEn; //从机接收到读请求中断使能 + uint8_t SlvWrReqIEn; //从机接收到写请求中断使能 } I2C_InitStructure; - void I2C_Init(I2C_TypeDef *I2Cx, I2C_InitStructure *initStruct); void I2C_Open(I2C_TypeDef *I2Cx); void I2C_Close(I2C_TypeDef *I2Cx); +uint8_t I2C_Start(I2C_TypeDef *I2Cx, uint8_t addr); +void I2C_Stop(I2C_TypeDef *I2Cx); +uint8_t I2C_Write(I2C_TypeDef *I2Cx, uint8_t data); +uint8_t I2C_Read(I2C_TypeDef *I2Cx, uint8_t ack); + #endif //__SWM320_I2C_H__ diff --git a/bsp/swm320-lq100/Libraries/SWM320_StdPeriph_Driver/SWM320_lcd.c b/bsp/swm320-lq100/Libraries/SWM320_StdPeriph_Driver/SWM320_lcd.c index 742c5b35dd..af2f2d7c38 100644 --- a/bsp/swm320-lq100/Libraries/SWM320_StdPeriph_Driver/SWM320_lcd.c +++ b/bsp/swm320-lq100/Libraries/SWM320_StdPeriph_Driver/SWM320_lcd.c @@ -1,10 +1,10 @@ /****************************************************************************************************************************************** -* ļ: SWM320_lcd.c -* ˵: SWM320ƬLCD -* ֧: http://www.synwit.com.cn/e/tool/gbook/?bid=1 -* ע: -* 汾: V1.1.0 20171025 -* ¼: +* 文件名称: SWM320_lcd.c +* 功能说明: SWM320单片机的LCD功能驱动库 +* 技术支持: http://www.synwit.com.cn/e/tool/gbook/?bid=1 +* 注意事项: +* 版本日期: V1.1.0 2017年10月25日 +* 升级记录: * * ******************************************************************************************************************************************* @@ -24,12 +24,12 @@ #include /****************************************************************************************************************************************** -* : LCD_Init() -* ˵: LCDʼ -* : LCD_TypeDef * LCDx ָҪõLCDЧֵLCD -* LCD_InitStructure * initStruct LCD趨ֵĽṹ -* : -* ע: +* 函数名称: LCD_Init() +* 功能说明: LCD初始化 +* 输 入: LCD_TypeDef * LCDx 指定要被设置的LCD，有效值包括LCD +* LCD_InitStructure * initStruct 包含LCD相关设定值的结构体 +* 输 出: 无 +* 注意事项: 无 ******************************************************************************************************************************************/ void LCD_Init(LCD_TypeDef *LCDx, LCD_InitStructure *initStruct) { @@ -40,56 +40,24 @@ void LCD_Init(LCD_TypeDef *LCDx, LCD_InitStructure *initStruct) break; } - if (initStruct->Interface == LCD_INTERFACE_RGB) - { - LCDx->START = (0 << LCD_START_MPUEN_Pos); - - if (initStruct->Dir == LCD_DIR_LANDSCAPE) - { - LCDx->CR0 = ((initStruct->HnPixel - 1) << LCD_CR0_HPIX_Pos) | - ((initStruct->VnPixel - 1) << LCD_CR0_VPIX_Pos) | - (initStruct->ClkAlways << LCD_CR0_DCLK_Pos) | - (initStruct->HsyncWidth << LCD_CR0_HLOW_Pos); - - LCDx->CR1 = (initStruct->Dir << LCD_CR1_DIRV_Pos) | - ((initStruct->Hfp - 1) << LCD_CR1_HFP_Pos) | - ((initStruct->Hbp - 1) << LCD_CR1_HBP_Pos) | - ((initStruct->Vfp - 1) << LCD_CR1_VFP_Pos) | - ((initStruct->Vbp - 1) << LCD_CR1_VBP_Pos) | - (initStruct->ClkDiv << LCD_CR1_DCLKDIV_Pos) | - (initStruct->SamplEdge << LCD_CR1_DCLKINV_Pos); - } - else - { - LCDx->CR0 = ((initStruct->HnPixel - 1) << LCD_CR0_VPIX_Pos) | - ((initStruct->VnPixel - 1) << LCD_CR0_HPIX_Pos) | - (initStruct->ClkAlways << LCD_CR0_DCLK_Pos) | - (initStruct->HsyncWidth << LCD_CR0_HLOW_Pos); - - LCDx->CR1 = (initStruct->Dir << LCD_CR1_DIRV_Pos) | - ((initStruct->Hfp - 1) << LCD_CR1_VFP_Pos) | - ((initStruct->Hbp - 1) << LCD_CR1_VBP_Pos) | - ((initStruct->Vfp - 1) << LCD_CR1_HFP_Pos) | - ((initStruct->Vbp - 1) << LCD_CR1_HBP_Pos) | - (initStruct->ClkDiv << LCD_CR1_DCLKDIV_Pos) | - (initStruct->SamplEdge << LCD_CR1_DCLKINV_Pos); - } - } - else if (initStruct->Interface == LCD_INTERFACE_I80) - { - LCDx->START = (1 << LCD_START_MPUEN_Pos); + LCDx->CR0 = ((initStruct->HnPixel - 1) << LCD_CR0_HPIX_Pos) | + ((initStruct->VnPixel - 1) << LCD_CR0_VPIX_Pos) | + (initStruct->ClkAlways << LCD_CR0_DCLK_Pos) | + (initStruct->HsyncWidth << LCD_CR0_HLOW_Pos); - LCDx->CR1 = (1 << LCD_CR1_I80_Pos) | - (initStruct->T_CSf_WRf << LCD_CR1_TAS_Pos) | - (initStruct->T_WRnHold << LCD_CR1_TPWLW_Pos) | - (initStruct->T_WRr_CSr << LCD_CR1_TAH_Pos) | - (initStruct->T_CSr_CSf << LCD_CR1_TTAIL_Pos); - } + LCDx->CR1 = ((initStruct->Hfp - 1) << LCD_CR1_HFP_Pos) | + ((initStruct->Hbp - 1) << LCD_CR1_HBP_Pos) | + ((initStruct->Vfp - 1) << LCD_CR1_VFP_Pos) | + ((initStruct->Vbp - 1) << LCD_CR1_VBP_Pos) | + (initStruct->ClkDiv << LCD_CR1_DCLKDIV_Pos) | + (initStruct->SamplEdge << LCD_CR1_DCLKINV_Pos); LCDx->IE = 1; - LCDx->IF = 1; //־ - if (initStruct->IntEOTEn) LCD_INTEn(LCDx); - else LCD_INTDis(LCDx); + LCDx->IF = 1; //清除标志 + if (initStruct->IntEOTEn) + LCD_INTEn(LCDx); + else + LCD_INTDis(LCDx); switch ((uint32_t)LCDx) { @@ -107,23 +75,23 @@ void LCD_Init(LCD_TypeDef *LCDx, LCD_InitStructure *initStruct) } /****************************************************************************************************************************************** -* : LCD_Start() -* ˵: һݴ -* : LCD_TypeDef * LCDx ָҪõLCDЧֵLCD -* : -* ע: +* 函数名称: LCD_Start() +* 功能说明: 启动一次数据传输 +* 输 入: LCD_TypeDef * LCDx 指定要被设置的LCD，有效值包括LCD +* 输 出: 无 +* 注意事项: 无 ******************************************************************************************************************************************/ void LCD_Start(LCD_TypeDef *LCDx) { - LCDx->START |= (1 << LCD_START_GO_Pos); + LCDx->START |= (1 << LCD_START_GO_Pos) | (1 << LCD_START_BURST_Pos); } /****************************************************************************************************************************************** -* : LCD_IsBusy() -* ˵: Ƿڽݴ -* : LCD_TypeDef * LCDx ָҪõLCDЧֵLCD -* : uint32_t 1 ڴ 0 ݴ -* ע: +* 函数名称: LCD_IsBusy() +* 功能说明: 是否正在进行数据传输 +* 输 入: LCD_TypeDef * LCDx 指定要被设置的LCD，有效值包括LCD +* 输 出: uint32_t 1 正在传输数据 0 数据传输已完成 +* 注意事项: 无 ******************************************************************************************************************************************/ uint32_t LCD_IsBusy(LCD_TypeDef *LCDx) { @@ -131,91 +99,11 @@ uint32_t LCD_IsBusy(LCD_TypeDef *LCDx) } /****************************************************************************************************************************************** -* : LCD_I80_WriteReg() -* ˵: MPUӿʱдĴ -* : LCD_TypeDef * LCDx ָҪõLCDЧֵLCD -* uint16_t reg ҪдļĴʵַַ -* uint16_t val[] ĴֵַԶ -* uint16_t cnt ҪдļĴ -* : -* ע: -******************************************************************************************************************************************/ -void LCD_I80_WriteReg(LCD_TypeDef *LCDx, uint16_t reg, uint16_t val[], uint16_t cnt) -{ - LCD->SRCADDR = (uint32_t)val; - LCD->CR0 &= ~LCD_CR0_DLEN_Msk; - LCD->CR0 |= ((cnt - 1) << LCD_CR0_DLEN_Pos); - - LCD->CR1 |= (1 << LCD_CR1_CMD_Pos); - LCD->CR1 &= ~LCD_CR1_REG_Msk; - LCD->CR1 |= (reg << LCD_CR1_REG_Pos); - - LCD_Start(LCDx); - while (LCD_IsBusy(LCDx)); -} - -/****************************************************************************************************************************************** -* : LCD_I80_WriteOneReg() -* ˵: MPUӿʱдĴ -* : LCD_TypeDef * LCDx ָҪõLCDЧֵLCD -* uint16_t reg ҪдļĴʵַ -* uint16_t val Ĵֵ -* : -* ע: -******************************************************************************************************************************************/ -void LCD_I80_WriteOneReg(LCD_TypeDef *LCDx, uint16_t reg, uint16_t val) -{ - uint16_t buf[1] __attribute__((aligned(4))); - - buf[0] = val; - - LCD_I80_WriteReg(LCDx, reg, buf, 1); -} - -/****************************************************************************************************************************************** -* : LCD_I80_WriteData() -* ˵: MPUӿʱд -* : LCD_TypeDef * LCDx ָҪõLCDЧֵLCD -* uint16_t val[] ҪдݣַԶ -* uint16_t cnt Ҫдݸ -* : -* ע: -******************************************************************************************************************************************/ -void LCD_I80_WriteData(LCD_TypeDef *LCDx, uint16_t val[], uint16_t cnt) -{ - LCD->SRCADDR = (uint32_t)val; - LCD->CR0 &= ~LCD_CR0_DLEN_Msk; - LCD->CR0 |= ((cnt - 1) << LCD_CR0_DLEN_Pos); - - LCD->CR1 &= ~(1 << LCD_CR1_CMD_Pos); - - LCD_Start(LCDx); - while (LCD_IsBusy(LCDx)); -} - -/****************************************************************************************************************************************** -* : LCD_I80_WriteOneData() -* ˵: MPUӿʱд -* : LCD_TypeDef * LCDx ָҪõLCDЧֵLCD -* uint16_t val Ҫд -* : -* ע: -******************************************************************************************************************************************/ -void LCD_I80_WriteOneData(LCD_TypeDef *LCDx, uint16_t val) -{ - uint16_t buf[1] __attribute__((aligned(4))); - - buf[0] = val; - - LCD_I80_WriteData(LCDx, buf, 2); -} - -/****************************************************************************************************************************************** -* : LCD_INTEn() -* ˵: LCDжʹܣָȵݴʱж -* : LCD_TypeDef * LCDx ָҪõLCDЧֵLCD -* : -* ע: +* 函数名称: LCD_INTEn() +* 功能说明: LCD中断使能，完成指定长度的数据传输时触发中断 +* 输 入: LCD_TypeDef * LCDx 指定要被设置的LCD，有效值包括LCD +* 输 出: 无 +* 注意事项: 无 ******************************************************************************************************************************************/ void LCD_INTEn(LCD_TypeDef *LCDx) { @@ -223,11 +111,11 @@ void LCD_INTEn(LCD_TypeDef *LCDx) } /****************************************************************************************************************************************** -* : LCD_INTDis() -* ˵: LCDжϽָֹȵݴʱж -* : LCD_TypeDef * LCDx ָҪõLCDЧֵLCD -* : -* ע: +* 函数名称: LCD_INTDis() +* 功能说明: LCD中断禁止，完成指定长度的数据传输时不触发中断 +* 输 入: LCD_TypeDef * LCDx 指定要被设置的LCD，有效值包括LCD +* 输 出: 无 +* 注意事项: 无 ******************************************************************************************************************************************/ void LCD_INTDis(LCD_TypeDef *LCDx) { @@ -235,11 +123,11 @@ void LCD_INTDis(LCD_TypeDef *LCDx) } /****************************************************************************************************************************************** -* : LCD_INTClr() -* ˵: LCDжϱ־ -* : LCD_TypeDef * LCDx ָҪõLCDЧֵLCD -* : -* ע: +* 函数名称: LCD_INTClr() +* 功能说明: LCD中断标志清除 +* 输 入: LCD_TypeDef * LCDx 指定要被设置的LCD，有效值包括LCD +* 输 出: 无 +* 注意事项: 无 ******************************************************************************************************************************************/ void LCD_INTClr(LCD_TypeDef *LCDx) { @@ -247,11 +135,11 @@ void LCD_INTClr(LCD_TypeDef *LCDx) } /****************************************************************************************************************************************** -* : LCD_INTStat() -* ˵: LCDж״̬ѯ -* : LCD_TypeDef * LCDx ָҪõLCDЧֵLCD -* : uint32_t 1 ָȵݴ 0 δָȵݴ -* ע: +* 函数名称: LCD_INTStat() +* 功能说明: LCD中断状态查询 +* 输 入: LCD_TypeDef * LCDx 指定要被设置的LCD，有效值包括LCD +* 输 出: uint32_t 1 完成指定长度的数据传输 0 未完成指定长度的数据传输 +* 注意事项: 无 ******************************************************************************************************************************************/ uint32_t LCD_INTStat(LCD_TypeDef *LCDx) { diff --git a/bsp/swm320-lq100/Libraries/SWM320_StdPeriph_Driver/SWM320_lcd.h b/bsp/swm320-lq100/Libraries/SWM320_StdPeriph_Driver/SWM320_lcd.h index 0b9d9b53c3..d9c78f8d1f 100644 --- a/bsp/swm320-lq100/Libraries/SWM320_StdPeriph_Driver/SWM320_lcd.h +++ b/bsp/swm320-lq100/Libraries/SWM320_StdPeriph_Driver/SWM320_lcd.h @@ -1,96 +1,70 @@ #ifndef __SWM320_LCD_H__ #define __SWM320_LCD_H__ - typedef struct { - uint8_t Interface; //LCDӿڣLCD_INTERFACE_RGBLCD_INTERFACE_I80LCD_INTERFACE_M68 - - /* RGBͬӿڲ */ - uint8_t Dir; //LCD_DIR_LANDSCAPE LCD_DIR_PORTRAIT - uint16_t HnPixel; //ˮƽظȡֵ1024 - uint16_t VnPixel; //ֱظȡֵ 768 - uint8_t Hfp; //horizonal front porchȡֵ32 - uint8_t Hbp; //horizonal back porch ȡֵ128 - uint8_t Vfp; //vertical front porch ȡֵ8 - uint8_t Vbp; //vertical back porch ȡֵ32 - uint8_t ClkDiv; //ϵͳʱӾClkDivƵDOCCLK0 2Ƶ 1 4Ƶ 2 6Ƶ ... ... 31 64Ƶ - uint8_t SamplEdge; //ĻDOTCLKĸزݣLCD_SAMPLEDGE_RISELCD_SAMPLEDGE_FALL - uint8_t ClkAlways; //1 һֱDOTCLK 0 ֻڴʱDOTCLK - uint8_t HsyncWidth; //HSYNC͵ƽٸDOTCLKȡֵLCD_HSYNC_1DOTCLKLCD_HSYNC_2DOTCLKLCD_HSYNC_3DOTCLKLCD_HSYNC_4DOTCLK - - /* MPU8080ӿڲ */ - uint8_t T_CSf_WRf; //CSn½صWRn½صʱ䣬ȡֵ0--3 - uint8_t T_WRnHold; //WRn͵ƽijʱ䣬 ȡֵ0--7 - uint8_t T_WRr_CSr; //WRnصCSnصʱ䣬ȡֵ0--3 - uint8_t T_CSr_CSf; //CSnصCSn½صʱ䣬ȡֵ0--7 - - uint8_t IntEOTEn; //End of Transterɣжʹ + uint16_t HnPixel; //水平方向像素个数，最大取值1024 + uint16_t VnPixel; //垂直方向像素个数，最大取值 768 + uint8_t Hfp; //horizonal front porch，最大取值32 + uint8_t Hbp; //horizonal back porch， 最大取值128 + uint8_t Vfp; //vertical front porch， 最大取值8 + uint8_t Vbp; //vertical back porch， 最大取值32 + uint8_t ClkDiv; //系统时钟经ClkDiv分频后产生DOCCLK，0 2分频 1 4分频 2 6分频 ... ... 31 64分频 + uint8_t SamplEdge; //屏幕在DOTCLK的哪个边沿采样数据：LCD_SAMPLEDGE_RISE、LCD_SAMPLEDGE_FALL + uint8_t ClkAlways; //1 一直输出DOTCLK 0 只在传输数据时输出DOTCLK + uint8_t HsyncWidth; //HSYNC低电平持续多少个DOTCLK，取值：LCD_HSYNC_1DOTCLK、LCD_HSYNC_2DOTCLK、LCD_HSYNC_3DOTCLK、LCD_HSYNC_4DOTCLK + + uint8_t IntEOTEn; //End of Transter（传输完成）中断使能 } LCD_InitStructure; - -#define LCD_INTERFACE_RGB 0 -#define LCD_INTERFACE_I80 1 -#define LCD_INTERFACE_M68 2 - -#define LCD_DIR_LANDSCAPE 0 // -#define LCD_DIR_PORTRAIT 1 // - -#define LCD_SAMPLEDGE_RISE 0 //ĻDOTCLKز -#define LCD_SAMPLEDGE_FALL 1 //ĻDOTCLK½ز - -#define LCD_HSYNC_1DOTCLK 0 //1DOTCLK -#define LCD_HSYNC_2DOTCLK 1 -#define LCD_HSYNC_3DOTCLK 2 -#define LCD_HSYNC_4DOTCLK 3 - -#define LCD_CLKDIV_2 0 -#define LCD_CLKDIV_4 1 -#define LCD_CLKDIV_6 2 -#define LCD_CLKDIV_8 3 -#define LCD_CLKDIV_10 4 -#define LCD_CLKDIV_12 5 -#define LCD_CLKDIV_14 6 -#define LCD_CLKDIV_16 7 -#define LCD_CLKDIV_18 8 -#define LCD_CLKDIV_20 9 -#define LCD_CLKDIV_22 10 -#define LCD_CLKDIV_24 11 -#define LCD_CLKDIV_26 12 -#define LCD_CLKDIV_28 13 -#define LCD_CLKDIV_30 14 -#define LCD_CLKDIV_32 15 -#define LCD_CLKDIV_34 16 -#define LCD_CLKDIV_36 17 -#define LCD_CLKDIV_38 18 -#define LCD_CLKDIV_40 19 -#define LCD_CLKDIV_42 20 -#define LCD_CLKDIV_44 21 -#define LCD_CLKDIV_46 22 -#define LCD_CLKDIV_48 23 -#define LCD_CLKDIV_50 24 -#define LCD_CLKDIV_52 25 -#define LCD_CLKDIV_54 26 -#define LCD_CLKDIV_56 27 -#define LCD_CLKDIV_58 28 -#define LCD_CLKDIV_60 29 -#define LCD_CLKDIV_62 30 -#define LCD_CLKDIV_64 31 - +#define LCD_SAMPLEDGE_RISE 0 //屏幕在DOTCLK的上升沿采样数据 +#define LCD_SAMPLEDGE_FALL 1 //屏幕在DOTCLK的下降沿采样数据 + +#define LCD_HSYNC_1DOTCLK 0 //1个DOTCLK +#define LCD_HSYNC_2DOTCLK 1 +#define LCD_HSYNC_3DOTCLK 2 +#define LCD_HSYNC_4DOTCLK 3 + +#define LCD_CLKDIV_2 0 +#define LCD_CLKDIV_4 1 +#define LCD_CLKDIV_6 2 +#define LCD_CLKDIV_8 3 +#define LCD_CLKDIV_10 4 +#define LCD_CLKDIV_12 5 +#define LCD_CLKDIV_14 6 +#define LCD_CLKDIV_16 7 +#define LCD_CLKDIV_18 8 +#define LCD_CLKDIV_20 9 +#define LCD_CLKDIV_22 10 +#define LCD_CLKDIV_24 11 +#define LCD_CLKDIV_26 12 +#define LCD_CLKDIV_28 13 +#define LCD_CLKDIV_30 14 +#define LCD_CLKDIV_32 15 +#define LCD_CLKDIV_34 16 +#define LCD_CLKDIV_36 17 +#define LCD_CLKDIV_38 18 +#define LCD_CLKDIV_40 19 +#define LCD_CLKDIV_42 20 +#define LCD_CLKDIV_44 21 +#define LCD_CLKDIV_46 22 +#define LCD_CLKDIV_48 23 +#define LCD_CLKDIV_50 24 +#define LCD_CLKDIV_52 25 +#define LCD_CLKDIV_54 26 +#define LCD_CLKDIV_56 27 +#define LCD_CLKDIV_58 28 +#define LCD_CLKDIV_60 29 +#define LCD_CLKDIV_62 30 +#define LCD_CLKDIV_64 31 void LCD_Init(LCD_TypeDef *LCDx, LCD_InitStructure *initStruct); void LCD_Start(LCD_TypeDef *LCDx); uint32_t LCD_IsBusy(LCD_TypeDef *LCDx); -void LCD_I80_WriteReg(LCD_TypeDef *LCDx, uint16_t reg, uint16_t val[], uint16_t cnt); -void LCD_I80_WriteOneReg(LCD_TypeDef *LCDx, uint16_t reg, uint16_t val); -void LCD_I80_WriteData(LCD_TypeDef *LCDx, uint16_t data[], uint16_t cnt); -void LCD_I80_WriteOneData(LCD_TypeDef *LCDx, uint16_t val); - void LCD_INTEn(LCD_TypeDef *LCDx); void LCD_INTDis(LCD_TypeDef *LCDx); void LCD_INTClr(LCD_TypeDef *LCDx); uint32_t LCD_INTStat(LCD_TypeDef *LCDx); - #endif //__SWM320_LCD_H__ diff --git a/bsp/swm320-lq100/Libraries/SWM320_StdPeriph_Driver/SWM320_norflash.c b/bsp/swm320-lq100/Libraries/SWM320_StdPeriph_Driver/SWM320_norflash.c index 0d183cee36..f9e306d6fb 100644 --- a/bsp/swm320-lq100/Libraries/SWM320_StdPeriph_Driver/SWM320_norflash.c +++ b/bsp/swm320-lq100/Libraries/SWM320_StdPeriph_Driver/SWM320_norflash.c @@ -1,10 +1,10 @@ /****************************************************************************************************************************************** -* ļ: SWM320_norflash.c -* ˵: SWM320ƬNOR Flash -* ֧: http://www.synwit.com.cn/e/tool/gbook/?bid=1 -* ע: -* 汾: V1.1.0 20171025 -* ¼: +* 文件名称: SWM320_norflash.c +* 功能说明: SWM320单片机的NOR Flash驱动程序 +* 技术支持: http://www.synwit.com.cn/e/tool/gbook/?bid=1 +* 注意事项: +* 版本日期: V1.1.0 2017年10月25日 +* 升级记录: * * ******************************************************************************************************************************************* @@ -21,30 +21,30 @@ #include "SWM320.h" #include "SWM320_norflash.h" - /****************************************************************************************************************************************** -* : NORFL_Init() -* ˵: NOR Flashʼ -* : NORFL_InitStructure * initStruct NOR Flash趨ֵĽṹ -* : -* ע: +* 函数名称: NORFL_Init() +* 功能说明: NOR Flash控制器初始化 +* 输 入: NORFL_InitStructure * initStruct 包含NOR Flash控制器相关设定值的结构体 +* 输 出: 无 +* 注意事项: 无 ******************************************************************************************************************************************/ void NORFL_Init(NORFL_InitStructure *initStruct) { uint32_t i; - // SRAMǰҪˢSDRAM + // 配置SRAM前需要刷新下SDRAM控制器 do { SYS->CLKEN |= (1 << SYS_CLKEN_SDRAM_Pos); - while (SDRAMC->REFDONE == 0); + while (SDRAMC->REFDONE == 0) + ; SDRAMC->REFRESH &= ~(1 << SDRAMC_REFRESH_EN_Pos); - for (i = 0; i < 1000; i++) __NOP(); + for (i = 0; i < 1000; i++) + __NOP(); SYS->CLKEN &= ~(1 << SYS_CLKEN_SDRAM_Pos); - } - while (0); + } while (0); SYS->CLKEN |= (1 << SYS_CLKEN_NORFL_Pos); @@ -53,19 +53,23 @@ void NORFL_Init(NORFL_InitStructure *initStruct) (initStruct->OEPreValidTime << NORFLC_CR_RDTIME_Pos); NORFLC->IE = 3; - NORFLC->IF = 3; // жϱ־ - if (initStruct->OperFinishIEn) NORFLC->IM &= ~(1 << NORFLC_IM_FINISH_Pos); - else NORFLC->IM |= (1 << NORFLC_IM_FINISH_Pos); - if (initStruct->OperTimeoutIEn) NORFLC->IM &= ~(1 << NORFLC_IM_TIMEOUT_Pos); - else NORFLC->IM |= (1 << NORFLC_IM_TIMEOUT_Pos); + NORFLC->IF = 3; // 清除中断标志 + if (initStruct->OperFinishIEn) + NORFLC->IM &= ~(1 << NORFLC_IM_FINISH_Pos); + else + NORFLC->IM |= (1 << NORFLC_IM_FINISH_Pos); + if (initStruct->OperTimeoutIEn) + NORFLC->IM &= ~(1 << NORFLC_IM_TIMEOUT_Pos); + else + NORFLC->IM |= (1 << NORFLC_IM_TIMEOUT_Pos); } /****************************************************************************************************************************************** -* : NORFL_ChipErase() -* ˵: NOR FlashƬ -* : -* : uint32_t 0 ɹ 1 ʱ -* ע: +* 函数名称: NORFL_ChipErase() +* 功能说明: NOR Flash整片擦除 +* 输 入: 无 +* 输 出: uint32_t 0 擦除成功 1 擦除超时 +* 注意事项: 无 ******************************************************************************************************************************************/ uint32_t NORFL_ChipErase(void) { @@ -74,10 +78,13 @@ uint32_t NORFL_ChipErase(void) NORFLC->CMD = (NORFL_CMD_CHIP_ERASE << NORFLC_CMD_CMD_Pos); while (((NORFLC->IF & NORFLC_IF_FINISH_Msk) == 0) && - ((NORFLC->IF & NORFLC_IF_TIMEOUT_Msk) == 0)) __NOP(); + ((NORFLC->IF & NORFLC_IF_TIMEOUT_Msk) == 0)) + __NOP(); - if (NORFLC->IF & NORFLC_IF_FINISH_Msk) res = 0; - else res = 1; + if (NORFLC->IF & NORFLC_IF_FINISH_Msk) + res = 0; + else + res = 1; NORFLC->IF = NORFLC_IF_FINISH_Msk | NORFLC_IF_TIMEOUT_Msk; @@ -85,11 +92,11 @@ uint32_t NORFL_ChipErase(void) } /****************************************************************************************************************************************** -* : NORFL_SectorErase() -* ˵: NOR Flash -* : uint32_t addr Ҫʼַ -* : uint32_t 0 ɹ 1 ʱ -* ע: MX29LV128DB ǰ8Ϊ8K255Ϊ64K MX29LV128DT ǰ255Ϊ64K8Ϊ8K +* 函数名称: NORFL_SectorErase() +* 功能说明: NOR Flash扇区擦除 +* 输 入: uint32_t addr 要擦除扇区的起始地址 +* 输 出: uint32_t 0 擦除成功 1 擦除超时 +* 注意事项: MX29LV128DB 前8扇区为8K、后255扇区为64K MX29LV128DT 前255扇区为64K、后8扇区为8K ******************************************************************************************************************************************/ uint32_t NORFL_SectorErase(uint32_t addr) { @@ -99,10 +106,13 @@ uint32_t NORFL_SectorErase(uint32_t addr) NORFLC->CMD = (NORFL_CMD_SECTOR_ERASE << NORFLC_CMD_CMD_Pos); while (((NORFLC->IF & NORFLC_IF_FINISH_Msk) == 0) && - ((NORFLC->IF & NORFLC_IF_TIMEOUT_Msk) == 0)) __NOP(); + ((NORFLC->IF & NORFLC_IF_TIMEOUT_Msk) == 0)) + __NOP(); - if (NORFLC->IF & NORFLC_IF_FINISH_Msk) res = 0; - else res = 1; + if (NORFLC->IF & NORFLC_IF_FINISH_Msk) + res = 0; + else + res = 1; NORFLC->IF = NORFLC_IF_FINISH_Msk | NORFLC_IF_TIMEOUT_Msk; @@ -110,12 +120,12 @@ uint32_t NORFL_SectorErase(uint32_t addr) } /****************************************************************************************************************************************** -* : NORFL_Write() -* ˵: NOR Flashд -* : uint32_t addr Ҫдĵַ -* uint32_t data Ҫд -* : uint32_t 0 дɹ 1 д볬ʱ -* ע: ӲӣΪ16λʱд룻Ϊ8λʱֽд +* 函数名称: NORFL_Write() +* 功能说明: NOR Flash写 +* 输 入: uint32_t addr 数据要写入的地址 +* uint32_t data 要写入的数据 +* 输 出: uint32_t 0 写入成功 1 写入超时 +* 注意事项: 硬件连接，数据线为16位时，半字写入；数据线为8位时，字节写入 ******************************************************************************************************************************************/ uint32_t NORFL_Write(uint32_t addr, uint32_t data) { @@ -125,10 +135,13 @@ uint32_t NORFL_Write(uint32_t addr, uint32_t data) NORFLC->CMD = (NORFL_CMD_PROGRAM << NORFLC_CMD_CMD_Pos) | (data << NORFLC_CMD_DATA_Pos); while (((NORFLC->IF & NORFLC_IF_FINISH_Msk) == 0) && - ((NORFLC->IF & NORFLC_IF_TIMEOUT_Msk) == 0)) __NOP(); + ((NORFLC->IF & NORFLC_IF_TIMEOUT_Msk) == 0)) + __NOP(); - if (NORFLC->IF & NORFLC_IF_FINISH_Msk) res = 0; - else res = 1; + if (NORFLC->IF & NORFLC_IF_FINISH_Msk) + res = 0; + else + res = 1; NORFLC->IF = NORFLC_IF_FINISH_Msk | NORFLC_IF_TIMEOUT_Msk; @@ -136,11 +149,11 @@ uint32_t NORFL_Write(uint32_t addr, uint32_t data) } /****************************************************************************************************************************************** -* : NORFL_Read() -* ˵: NOR Flash -* : uint32_t addr Ҫĵַ -* : uint32_t -* ע: ӲӣΪ16λʱֶΪ8λʱֽڶ +* 函数名称: NORFL_Read() +* 功能说明: NOR Flash读 +* 输 入: uint32_t addr 数据要读出的地址 +* 输 出: uint32_t 读出的数据 +* 注意事项: 硬件连接，数据线为16位时，半字读出；数据线为8位时，字节读出 ******************************************************************************************************************************************/ uint32_t NORFL_Read(uint32_t addr) { @@ -151,11 +164,11 @@ uint32_t NORFL_Read(uint32_t addr) } /****************************************************************************************************************************************** -* : NORFL_ReadID() -* ˵: NOR FlashID -* : uint32_t id_addr IDַ˲оƬصģÿоƬͬ -* : uint16_t ȡID -* ע: +* 函数名称: NORFL_ReadID() +* 功能说明: NOR Flash读ID +* 输 入: uint32_t id_addr ID地址，此参数是芯片相关的，每种芯片都不同 +* 输 出: uint16_t 读取到的ID +* 注意事项: 无 ******************************************************************************************************************************************/ uint16_t NORFL_ReadID(uint32_t id_addr) { @@ -168,7 +181,7 @@ uint16_t NORFL_ReadID(uint32_t id_addr) id = NORFLC->CMD & NORFLC_CMD_DATA_Msk; - NORFLC->CMD = (NORFL_CMD_RESET << NORFLC_CMD_CMD_Pos); // ˳IDȡģʽ + NORFLC->CMD = (NORFL_CMD_RESET << NORFLC_CMD_CMD_Pos); // 退出ID读取模式 return id; } diff --git a/bsp/swm320-lq100/Libraries/SWM320_StdPeriph_Driver/SWM320_norflash.h b/bsp/swm320-lq100/Libraries/SWM320_StdPeriph_Driver/SWM320_norflash.h index fc859268fb..77fb034557 100644 --- a/bsp/swm320-lq100/Libraries/SWM320_StdPeriph_Driver/SWM320_norflash.h +++ b/bsp/swm320-lq100/Libraries/SWM320_StdPeriph_Driver/SWM320_norflash.h @@ -3,17 +3,15 @@ typedef struct { - uint8_t DataWidth; // 816 + uint8_t DataWidth; // 8、16 - uint8_t WELowPulseTime; // WE# pulse widthλΪϵͳʱڣֵΪ7 - uint8_t OEPreValidTime; // Valid data output after OE# lowλΪϵͳʱڣֵΪ15 + uint8_t WELowPulseTime; // WE# pulse width，单位为系统时钟周期，最大值为7 + uint8_t OEPreValidTime; // Valid data output after OE# low，单位为系统时钟周期，最大值为15 - uint8_t OperFinishIEn; // (д롢)жʹ + uint8_t OperFinishIEn; // 操作(写入、擦除)完成中断使能 uint8_t OperTimeoutIEn; } NORFL_InitStructure; - - void NORFL_Init(NORFL_InitStructure *initStruct); uint32_t NORFL_ChipErase(void); uint32_t NORFL_SectorErase(uint32_t addr); @@ -21,19 +19,16 @@ uint32_t NORFL_Write(uint32_t addr, uint32_t data); uint32_t NORFL_Read(uint32_t addr); uint16_t NORFL_ReadID(uint32_t id_addr); - -/* ǰ汾߶ֶֻ֧ -#define NORFL_Read8(addr) *((volatile uint8_t *)(NORFLM_BASE + addr)) -#define NORFL_Read16(addr) *((volatile uint16_t *)(NORFLM_BASE + addr)) */ -#define NORFL_Read32(addr) *((volatile uint32_t *)(NORFLM_BASE + addr)) - - - -#define NORFL_CMD_READ 0 -#define NORFL_CMD_RESET 1 -#define NORFL_CMD_AUTO_SELECT 2 -#define NORFL_CMD_PROGRAM 3 -#define NORFL_CMD_CHIP_ERASE 4 -#define NORFL_CMD_SECTOR_ERASE 5 +/* 当前版本总线读只支持字读 +#define NORFL_Read8(addr) *((volatile uint8_t *)(NORFLM_BASE + addr)) +#define NORFL_Read16(addr) *((volatile uint16_t *)(NORFLM_BASE + addr)) */ +#define NORFL_Read32(addr) *((volatile uint32_t *)(NORFLM_BASE + addr)) + +#define NORFL_CMD_READ 0 +#define NORFL_CMD_RESET 1 +#define NORFL_CMD_AUTO_SELECT 2 +#define NORFL_CMD_PROGRAM 3 +#define NORFL_CMD_CHIP_ERASE 4 +#define NORFL_CMD_SECTOR_ERASE 5 #endif // __SWM320_NORFLASH_H__ diff --git a/bsp/swm320-lq100/Libraries/SWM320_StdPeriph_Driver/SWM320_port.c b/bsp/swm320-lq100/Libraries/SWM320_StdPeriph_Driver/SWM320_port.c index bc7a555a30..5fa0be4ada 100644 --- a/bsp/swm320-lq100/Libraries/SWM320_StdPeriph_Driver/SWM320_port.c +++ b/bsp/swm320-lq100/Libraries/SWM320_StdPeriph_Driver/SWM320_port.c @@ -1,10 +1,10 @@ /****************************************************************************************************************************************** -* ļ: SWM320_port.c -* ˵: SWM320ƬĶ˿Źѡ⺯ -* ֧: http://www.synwit.com.cn/e/tool/gbook/?bid=1 -* ע: -* 汾: V1.1.0 20171025 -* ¼: +* 文件名称: SWM320_port.c +* 功能说明: SWM320单片机的端口引脚功能选择库函数 +* 技术支持: http://www.synwit.com.cn/e/tool/gbook/?bid=1 +* 注意事项: +* 版本日期: V1.1.0 2017年10月25日 +* 升级记录: * * ******************************************************************************************************************************************* @@ -21,17 +21,16 @@ #include "SWM320.h" #include "SWM320_port.h" - /****************************************************************************************************************************************** -* : PORT_Init() -* ˵: ˿Źѡ񣬿õĹܼ"SWM320_port.h"ļ -* : uint32_t PORTx ָPORT˿ڣЧֵPORTAPORTBPORTCPORTMPORTNPORTP -* uint32_t n ָPORTţЧֵPIN0PIN1PIN2... ... PIN22PIN23 -* uint32_t func ָ˿Ҫ趨Ĺܣȡֵ"SWM320_port.h"ļ -* uint32_t digit_in_en ʹ -* : -* ע: űnΪżʱfuncȡֵֻFUNMUX0ͷģFUNMUX0_UART0_RXD -* űnΪʱfuncȡֵֻFUNMUX1ͷģFUNMUX1_UART0_TXD +* 函数名称: PORT_Init() +* 功能说明: 端口引脚功能选择，可用的功能见"SWM320_port.h"文件 +* 输 入: uint32_t PORTx 指定PORT端口，有效值包括PORTA、PORTB、PORTC、PORTM、PORTN、PORTP +* uint32_t n 指定PORT引脚，有效值包括PIN0、PIN1、PIN2、... ... PIN22、PIN23 +* uint32_t func 指定端口引脚要设定的功能，其可取值见"SWM320_port.h"文件 +* uint32_t digit_in_en 数字输入使能 +* 输 出: 无 +* 注意事项: 当引脚标号n为偶数时，func取值只能是FUNMUX0开头的，如FUNMUX0_UART0_RXD +* 当引脚标号n为奇数时，func取值只能是FUNMUX1开头的，如FUNMUX1_UART0_TXD ******************************************************************************************************************************************/ void PORT_Init(uint32_t PORTx, uint32_t n, uint32_t func, uint32_t digit_in_en) { diff --git a/bsp/swm320-lq100/Libraries/SWM320_StdPeriph_Driver/SWM320_port.h b/bsp/swm320-lq100/Libraries/SWM320_StdPeriph_Driver/SWM320_port.h index ff0fd9cdc9..0d1ec56db1 100644 --- a/bsp/swm320-lq100/Libraries/SWM320_StdPeriph_Driver/SWM320_port.h +++ b/bsp/swm320-lq100/Libraries/SWM320_StdPeriph_Driver/SWM320_port.h @@ -1,482 +1,474 @@ #ifndef __SWM320_PORT_H__ #define __SWM320_PORT_H__ -void PORT_Init(uint32_t PORTx, uint32_t n, uint32_t func, uint32_t digit_in_en); //˿Źѡȡֵ£ +void PORT_Init(uint32_t PORTx, uint32_t n, uint32_t func, uint32_t digit_in_en); //端口引脚功能选择，其可取值如下： -#define PORTA 0 -#define PORTB 1 -#define PORTC 2 -#define PORTM 3 -#define PORTN 4 -#define PORTP 5 +#define PORTA 0 +#define PORTB 1 +#define PORTC 2 +#define PORTM 3 +#define PORTN 4 +#define PORTP 5 -#define PORTA_PIN0_GPIO 0 -#define PORTA_PIN0_FUNMUX 1 -#define PORTA_PIN0_SWCLK 2 +#define PORTA_PIN0_GPIO 0 +#define PORTA_PIN0_FUNMUX 1 +#define PORTA_PIN0_SWCLK 2 -#define PORTA_PIN1_GPIO 0 -#define PORTA_PIN1_FUNMUX 1 -#define PORTA_PIN1_SWDIO 2 +#define PORTA_PIN1_GPIO 0 +#define PORTA_PIN1_FUNMUX 1 +#define PORTA_PIN1_SWDIO 2 -#define PORTA_PIN2_GPIO 0 -#define PORTA_PIN2_FUNMUX 1 +#define PORTA_PIN2_GPIO 0 +#define PORTA_PIN2_FUNMUX 1 -#define PORTA_PIN3_GPIO 0 -#define PORTA_PIN3_FUNMUX 1 +#define PORTA_PIN3_GPIO 0 +#define PORTA_PIN3_FUNMUX 1 -#define PORTA_PIN4_GPIO 0 -#define PORTA_PIN4_FUNMUX 1 +#define PORTA_PIN4_GPIO 0 +#define PORTA_PIN4_FUNMUX 1 -#define PORTA_PIN5_GPIO 0 -#define PORTA_PIN5_FUNMUX 1 +#define PORTA_PIN5_GPIO 0 +#define PORTA_PIN5_FUNMUX 1 -#define PORTA_PIN6_GPIO 0 -#define PORTA_PIN6_FUNMUX 1 +#define PORTA_PIN6_GPIO 0 +#define PORTA_PIN6_FUNMUX 1 -#define PORTA_PIN7_GPIO 0 -#define PORTA_PIN7_FUNMUX 1 +#define PORTA_PIN7_GPIO 0 +#define PORTA_PIN7_FUNMUX 1 -#define PORTA_PIN8_GPIO 0 -#define PORTA_PIN8_FUNMUX 1 +#define PORTA_PIN8_GPIO 0 +#define PORTA_PIN8_FUNMUX 1 -#define PORTA_PIN9_GPIO 0 -#define PORTA_PIN9_FUNMUX 1 -#define PORTA_PIN9_ADC0_IN7 3 +#define PORTA_PIN9_GPIO 0 +#define PORTA_PIN9_FUNMUX 1 +#define PORTA_PIN9_ADC0_IN7 3 -#define PORTA_PIN10_GPIO 0 -#define PORTA_PIN10_FUNMUX 1 -#define PORTA_PIN10_ADC0_IN6 3 +#define PORTA_PIN10_GPIO 0 +#define PORTA_PIN10_FUNMUX 1 +#define PORTA_PIN10_ADC0_IN6 3 -#define PORTA_PIN11_GPIO 0 -#define PORTA_PIN11_FUNMUX 1 -#define PORTA_PIN11_ADC0_IN5 3 +#define PORTA_PIN11_GPIO 0 +#define PORTA_PIN11_FUNMUX 1 +#define PORTA_PIN11_ADC0_IN5 3 -#define PORTA_PIN12_GPIO 0 -#define PORTA_PIN12_ADC0_IN4 3 +#define PORTA_PIN12_GPIO 0 +#define PORTA_PIN12_ADC0_IN4 3 +#define PORTB_PIN0_GPIO 0 +#define PORTB_PIN0_FUNMUX 1 +#define PORTB_PIN0_SD_DETECT 2 -#define PORTB_PIN0_GPIO 0 -#define PORTB_PIN0_FUNMUX 1 -#define PORTB_PIN0_SD_DETECT 2 +#define PORTB_PIN1_GPIO 0 +#define PORTB_PIN1_FUNMUX 1 +#define PORTB_PIN1_SD_CLK 2 -#define PORTB_PIN1_GPIO 0 -#define PORTB_PIN1_FUNMUX 1 -#define PORTB_PIN1_SD_CLK 2 +#define PORTB_PIN2_GPIO 0 +#define PORTB_PIN2_FUNMUX 1 +#define PORTB_PIN2_SD_CMD 2 -#define PORTB_PIN2_GPIO 0 -#define PORTB_PIN2_FUNMUX 1 -#define PORTB_PIN2_SD_CMD 2 +#define PORTB_PIN3_GPIO 0 +#define PORTB_PIN3_FUNMUX 1 +#define PORTB_PIN3_SD_D0 2 -#define PORTB_PIN3_GPIO 0 -#define PORTB_PIN3_FUNMUX 1 -#define PORTB_PIN3_SD_D0 2 +#define PORTB_PIN4_GPIO 0 +#define PORTB_PIN4_FUNMUX 1 +#define PORTB_PIN4_SD_D1 2 -#define PORTB_PIN4_GPIO 0 -#define PORTB_PIN4_FUNMUX 1 -#define PORTB_PIN4_SD_D1 2 +#define PORTB_PIN5_GPIO 0 +#define PORTB_PIN5_FUNMUX 1 +#define PORTB_PIN5_SD_D2 2 -#define PORTB_PIN5_GPIO 0 -#define PORTB_PIN5_FUNMUX 1 -#define PORTB_PIN5_SD_D2 2 +#define PORTB_PIN6_GPIO 0 +#define PORTB_PIN6_FUNMUX 1 +#define PORTB_PIN6_SD_D3 2 -#define PORTB_PIN6_GPIO 0 -#define PORTB_PIN6_FUNMUX 1 -#define PORTB_PIN6_SD_D3 2 +#define PORTB_PIN7_GPIO 0 +#define PORTB_PIN7_FUNMUX 1 +#define PORTB_PIN7_SD_D4 2 -#define PORTB_PIN7_GPIO 0 -#define PORTB_PIN7_FUNMUX 1 -#define PORTB_PIN7_SD_D4 2 +#define PORTB_PIN8_GPIO 0 +#define PORTB_PIN8_FUNMUX 1 +#define PORTB_PIN8_SD_D5 2 -#define PORTB_PIN8_GPIO 0 -#define PORTB_PIN8_FUNMUX 1 -#define PORTB_PIN8_SD_D5 2 +#define PORTB_PIN9_GPIO 0 +#define PORTB_PIN9_FUNMUX 1 +#define PORTB_PIN9_SD_D6 2 -#define PORTB_PIN9_GPIO 0 -#define PORTB_PIN9_FUNMUX 1 -#define PORTB_PIN9_SD_D6 2 +#define PORTB_PIN10_GPIO 0 +#define PORTB_PIN10_FUNMUX 1 +#define PORTB_PIN10_SD_D7 2 -#define PORTB_PIN10_GPIO 0 -#define PORTB_PIN10_FUNMUX 1 -#define PORTB_PIN10_SD_D7 2 +#define PORTB_PIN11_GPIO 0 +#define PORTB_PIN11_FUNMUX 1 -#define PORTB_PIN11_GPIO 0 -#define PORTB_PIN11_FUNMUX 1 +#define PORTB_PIN12_GPIO 0 -#define PORTB_PIN12_GPIO 0 +#define PORTC_PIN0_GPIO 0 +#define PORTC_PIN0_FUNMUX 1 +#define PORTC_PIN1_GPIO 0 +#define PORTC_PIN1_FUNMUX 1 -#define PORTC_PIN0_GPIO 0 -#define PORTC_PIN0_FUNMUX 1 +#define PORTC_PIN2_GPIO 0 +#define PORTC_PIN2_FUNMUX 1 -#define PORTC_PIN1_GPIO 0 -#define PORTC_PIN1_FUNMUX 1 +#define PORTC_PIN3_GPIO 0 +#define PORTC_PIN3_FUNMUX 1 -#define PORTC_PIN2_GPIO 0 -#define PORTC_PIN2_FUNMUX 1 +#define PORTC_PIN4_GPIO 0 +#define PORTC_PIN4_FUNMUX 1 +#define PORTC_PIN4_ADC1_IN3 3 -#define PORTC_PIN3_GPIO 0 -#define PORTC_PIN3_FUNMUX 1 +#define PORTC_PIN5_GPIO 0 +#define PORTC_PIN5_FUNMUX 1 +#define PORTC_PIN5_ADC1_IN2 3 -#define PORTC_PIN4_GPIO 0 -#define PORTC_PIN4_FUNMUX 1 -#define PORTC_PIN4_ADC1_IN3 3 +#define PORTC_PIN6_GPIO 0 +#define PORTC_PIN6_FUNMUX 1 +#define PORTC_PIN6_ADC1_IN1 3 -#define PORTC_PIN5_GPIO 0 -#define PORTC_PIN5_FUNMUX 1 -#define PORTC_PIN5_ADC1_IN2 3 +#define PORTC_PIN7_GPIO 0 +#define PORTC_PIN7_FUNMUX 1 +#define PORTC_PIN7_ADC1_IN0 3 -#define PORTC_PIN6_GPIO 0 -#define PORTC_PIN6_FUNMUX 1 -#define PORTC_PIN6_ADC1_IN1 3 +#define PORTM_PIN0_GPIO 0 +#define PORTM_PIN0_FUNMUX 1 +#define PORTM_PIN0_NORFL_D15 2 -#define PORTC_PIN7_GPIO 0 -#define PORTC_PIN7_FUNMUX 1 -#define PORTC_PIN7_ADC1_IN0 3 +#define PORTM_PIN1_GPIO 0 +#define PORTM_PIN1_FUNMUX 1 +#define PORTM_PIN1_NORFL_D14 2 +#define PORTM_PIN2_GPIO 0 +#define PORTM_PIN2_FUNMUX 1 +#define PORTM_PIN2_NORFL_D13 2 -#define PORTM_PIN0_GPIO 0 -#define PORTM_PIN0_FUNMUX 1 -#define PORTM_PIN0_NORFL_D15 2 +#define PORTM_PIN3_GPIO 0 +#define PORTM_PIN3_FUNMUX 1 +#define PORTM_PIN3_NORFL_D12 2 -#define PORTM_PIN1_GPIO 0 -#define PORTM_PIN1_FUNMUX 1 -#define PORTM_PIN1_NORFL_D14 2 +#define PORTM_PIN4_GPIO 0 +#define PORTM_PIN4_FUNMUX 1 +#define PORTM_PIN4_NORFL_D11 2 -#define PORTM_PIN2_GPIO 0 -#define PORTM_PIN2_FUNMUX 1 -#define PORTM_PIN2_NORFL_D13 2 +#define PORTM_PIN5_GPIO 0 +#define PORTM_PIN5_FUNMUX 1 +#define PORTM_PIN5_NORFL_D10 2 -#define PORTM_PIN3_GPIO 0 -#define PORTM_PIN3_FUNMUX 1 -#define PORTM_PIN3_NORFL_D12 2 +#define PORTM_PIN6_GPIO 0 +#define PORTM_PIN6_FUNMUX 1 +#define PORTM_PIN6_NORFL_D9 2 -#define PORTM_PIN4_GPIO 0 -#define PORTM_PIN4_FUNMUX 1 -#define PORTM_PIN4_NORFL_D11 2 +#define PORTM_PIN7_GPIO 0 +#define PORTM_PIN7_FUNMUX 1 +#define PORTM_PIN7_NORFL_D8 2 -#define PORTM_PIN5_GPIO 0 -#define PORTM_PIN5_FUNMUX 1 -#define PORTM_PIN5_NORFL_D10 2 +#define PORTM_PIN8_GPIO 0 +#define PORTM_PIN8_FUNMUX 1 +#define PORTM_PIN8_NORFL_D7 2 -#define PORTM_PIN6_GPIO 0 -#define PORTM_PIN6_FUNMUX 1 -#define PORTM_PIN6_NORFL_D9 2 +#define PORTM_PIN9_GPIO 0 +#define PORTM_PIN9_FUNMUX 1 +#define PORTM_PIN9_NORFL_D6 2 -#define PORTM_PIN7_GPIO 0 -#define PORTM_PIN7_FUNMUX 1 -#define PORTM_PIN7_NORFL_D8 2 +#define PORTM_PIN10_GPIO 0 +#define PORTM_PIN10_FUNMUX 1 +#define PORTM_PIN10_NORFL_D5 2 -#define PORTM_PIN8_GPIO 0 -#define PORTM_PIN8_FUNMUX 1 -#define PORTM_PIN8_NORFL_D7 2 +#define PORTM_PIN11_GPIO 0 +#define PORTM_PIN11_FUNMUX 1 +#define PORTM_PIN11_NORFL_D4 2 -#define PORTM_PIN9_GPIO 0 -#define PORTM_PIN9_FUNMUX 1 -#define PORTM_PIN9_NORFL_D6 2 +#define PORTM_PIN12_GPIO 0 +#define PORTM_PIN12_FUNMUX 1 +#define PORTM_PIN12_NORFL_D3 2 -#define PORTM_PIN10_GPIO 0 -#define PORTM_PIN10_FUNMUX 1 -#define PORTM_PIN10_NORFL_D5 2 +#define PORTM_PIN13_GPIO 0 +#define PORTM_PIN13_FUNMUX 1 +#define PORTM_PIN13_NORFL_D2 2 -#define PORTM_PIN11_GPIO 0 -#define PORTM_PIN11_FUNMUX 1 -#define PORTM_PIN11_NORFL_D4 2 +#define PORTM_PIN14_GPIO 0 +#define PORTM_PIN14_FUNMUX 1 +#define PORTM_PIN14_NORFL_D1 2 -#define PORTM_PIN12_GPIO 0 -#define PORTM_PIN12_FUNMUX 1 -#define PORTM_PIN12_NORFL_D3 2 +#define PORTM_PIN15_GPIO 0 +#define PORTM_PIN15_FUNMUX 1 +#define PORTM_PIN15_NORFL_D0 2 -#define PORTM_PIN13_GPIO 0 -#define PORTM_PIN13_FUNMUX 1 -#define PORTM_PIN13_NORFL_D2 2 +#define PORTM_PIN16_GPIO 0 +#define PORTM_PIN16_FUNMUX 1 +#define PORTM_PIN16_NORFL_OEN 2 -#define PORTM_PIN14_GPIO 0 -#define PORTM_PIN14_FUNMUX 1 -#define PORTM_PIN14_NORFL_D1 2 - -#define PORTM_PIN15_GPIO 0 -#define PORTM_PIN15_FUNMUX 1 -#define PORTM_PIN15_NORFL_D0 2 - -#define PORTM_PIN16_GPIO 0 -#define PORTM_PIN16_FUNMUX 1 -#define PORTM_PIN16_NORFL_OEN 2 - -#define PORTM_PIN17_GPIO 0 -#define PORTM_PIN17_FUNMUX 1 -#define PORTM_PIN17_NORFL_WEN 2 - -#define PORTM_PIN18_GPIO 0 -#define PORTM_PIN18_FUNMUX 1 -#define PORTM_PIN18_NORFL_CSN 2 - -#define PORTM_PIN19_GPIO 0 -#define PORTM_PIN19_FUNMUX 1 -#define PORTM_PIN19_SDRAM_CSN 2 - -#define PORTM_PIN20_GPIO 0 -#define PORTM_PIN20_FUNMUX 1 -#define PORTM_PIN20_SRAM_CSN 2 - -#define PORTM_PIN21_GPIO 0 -#define PORTM_PIN21_FUNMUX 1 -#define PORTM_PIN21_SDRAM_CKE 2 - - -#define PORTN_PIN0_GPIO 0 -#define PORTN_PIN0_FUNMUX 1 -#define PORTN_PIN0_LCD_D0 2 -#define PORTN_PIN0_ADC1_IN4 3 - -#define PORTN_PIN1_GPIO 0 -#define PORTN_PIN1_FUNMUX 1 -#define PORTN_PIN1_LCD_D1 2 -#define PORTN_PIN1_ADC1_IN5 3 - -#define PORTN_PIN2_GPIO 0 -#define PORTN_PIN2_FUNMUX 1 -#define PORTN_PIN2_LCD_D2 2 -#define PORTN_PIN2_ADC1_IN6 3 - -#define PORTN_PIN3_GPIO 0 -#define PORTN_PIN3_FUNMUX 1 -#define PORTN_PIN3_LCD_D3 2 - -#define PORTN_PIN4_GPIO 0 -#define PORTN_PIN4_FUNMUX 1 -#define PORTN_PIN4_LCD_D4 2 - -#define PORTN_PIN5_GPIO 0 -#define PORTN_PIN5_FUNMUX 1 -#define PORTN_PIN5_LCD_D5 2 - -#define PORTN_PIN6_GPIO 0 -#define PORTN_PIN6_FUNMUX 1 -#define PORTN_PIN6_LCD_D6 2 - -#define PORTN_PIN7_GPIO 0 -#define PORTN_PIN7_FUNMUX 1 -#define PORTN_PIN7_LCD_D7 2 - -#define PORTN_PIN8_GPIO 0 -#define PORTN_PIN8_FUNMUX 1 -#define PORTN_PIN8_LCD_D8 2 - -#define PORTN_PIN9_GPIO 0 -#define PORTN_PIN9_FUNMUX 1 -#define PORTN_PIN9_LCD_D9 2 - -#define PORTN_PIN10_GPIO 0 -#define PORTN_PIN10_FUNMUX 1 -#define PORTN_PIN10_LCD_D10 2 - -#define PORTN_PIN11_GPIO 0 -#define PORTN_PIN11_FUNMUX 1 -#define PORTN_PIN11_LCD_D11 2 - -#define PORTN_PIN12_GPIO 0 -#define PORTN_PIN12_FUNMUX 1 -#define PORTN_PIN12_LCD_D12 2 - -#define PORTN_PIN13_GPIO 0 -#define PORTN_PIN13_FUNMUX 1 -#define PORTN_PIN13_LCD_D13 2 - -#define PORTN_PIN14_GPIO 0 -#define PORTN_PIN14_FUNMUX 1 -#define PORTN_PIN14_LCD_D14 2 - -#define PORTN_PIN15_GPIO 0 -#define PORTN_PIN15_FUNMUX 1 -#define PORTN_PIN15_LCD_D15 2 - -#define PORTN_PIN16_GPIO 0 -#define PORTN_PIN16_FUNMUX 1 -#define PORTN_PIN16_LCD_RD 2 -#define PORTN_PIN16_LCD_DOTCK 2 - -#define PORTN_PIN17_GPIO 0 -#define PORTN_PIN17_FUNMUX 1 -#define PORTN_PIN17_LCD_CS 2 -#define PORTN_PIN17_LCD_VSYNC 2 - -#define PORTN_PIN18_GPIO 0 -#define PORTN_PIN18_LCD_RS 2 -#define PORTN_PIN18_LCD_DATEN 2 //Data Enable - -#define PORTN_PIN19_GPIO 0 -#define PORTN_PIN19_LCD_WR 2 -#define PORTN_PIN19_LCD_HSYNC 2 - - -#define PORTP_PIN0_GPIO 0 -#define PORTP_PIN0_FUNMUX 1 -#define PORTP_PIN0_NORFL_A0 2 - -#define PORTP_PIN1_GPIO 0 -#define PORTP_PIN1_FUNMUX 1 -#define PORTP_PIN1_NORFL_A1 2 - -#define PORTP_PIN2_GPIO 0 -#define PORTP_PIN2_FUNMUX 1 -#define PORTP_PIN2_NORFL_A2 2 -#define PORTP_PIN2_SD_D7 3 - -#define PORTP_PIN3_GPIO 0 -#define PORTP_PIN3_FUNMUX 1 -#define PORTP_PIN3_NORFL_A3 2 -#define PORTP_PIN3_SD_D6 3 - -#define PORTP_PIN4_GPIO 0 -#define PORTP_PIN4_FUNMUX 1 -#define PORTP_PIN4_NORFL_A4 2 -#define PORTP_PIN4_SD_D5 3 - -#define PORTP_PIN5_GPIO 0 -#define PORTP_PIN5_FUNMUX 1 -#define PORTP_PIN5_NORFL_A5 2 -#define PORTP_PIN5_SD_D4 3 - -#define PORTP_PIN6_GPIO 0 -#define PORTP_PIN6_FUNMUX 1 -#define PORTP_PIN6_NORFL_A6 2 -#define PORTP_PIN6_SD_D3 3 - -#define PORTP_PIN7_GPIO 0 -#define PORTP_PIN7_FUNMUX 1 -#define PORTP_PIN7_NORFL_A7 2 -#define PORTP_PIN7_SD_D2 3 - -#define PORTP_PIN8_GPIO 0 -#define PORTP_PIN8_FUNMUX 1 -#define PORTP_PIN8_NORFL_A8 2 -#define PORTP_PIN8_SD_D1 3 - -#define PORTP_PIN9_GPIO 0 -#define PORTP_PIN9_FUNMUX 1 -#define PORTP_PIN9_NORFL_A9 2 -#define PORTP_PIN9_SD_D0 3 - -#define PORTP_PIN10_GPIO 0 -#define PORTP_PIN10_FUNMUX 1 -#define PORTP_PIN10_NORFL_A10 2 -#define PORTP_PIN10_SD_CMD 3 - -#define PORTP_PIN11_GPIO 0 -#define PORTP_PIN11_FUNMUX 1 -#define PORTP_PIN11_NORFL_A11 2 -#define PORTP_PIN11_SD_CLK 3 - -#define PORTP_PIN12_GPIO 0 -#define PORTP_PIN12_FUNMUX 1 -#define PORTP_PIN12_NORFL_A12 2 -#define PORTP_PIN12_SD_DETECT 3 - -#define PORTP_PIN13_GPIO 0 -#define PORTP_PIN13_FUNMUX 1 -#define PORTP_PIN13_NORFL_A13 2 -#define PORTP_PIN13_SDRAM_CLK 2 - -#define PORTP_PIN14_GPIO 0 -#define PORTP_PIN14_FUNMUX 1 -#define PORTP_PIN14_NORFL_A14 2 -#define PORTP_PIN14_SDRAM_CAS 2 - -#define PORTP_PIN15_GPIO 0 -#define PORTP_PIN15_FUNMUX 1 -#define PORTP_PIN15_NORFL_A15 2 -#define PORTP_PIN15_SDRAM_RAS 2 - -#define PORTP_PIN16_GPIO 0 -#define PORTP_PIN16_FUNMUX 1 -#define PORTP_PIN16_NORFL_A16 2 -#define PORTP_PIN16_SDRAM_LDQ 2 - -#define PORTP_PIN17_GPIO 0 -#define PORTP_PIN17_FUNMUX 1 -#define PORTP_PIN17_NORFL_A17 2 -#define PORTP_PIN17_SDRAM_UDQ 2 - -#define PORTP_PIN18_GPIO 0 -#define PORTP_PIN18_FUNMUX 1 -#define PORTP_PIN18_NORFL_A18 2 - -#define PORTP_PIN19_GPIO 0 -#define PORTP_PIN19_FUNMUX 1 -#define PORTP_PIN19_NORFL_A19 2 - -#define PORTP_PIN20_GPIO 0 -#define PORTP_PIN20_FUNMUX 1 -#define PORTP_PIN20_NORFL_A20 2 -#define PORTP_PIN20_SDRAM_BA0 2 - -#define PORTP_PIN21_GPIO 0 -#define PORTP_PIN21_FUNMUX 1 -#define PORTP_PIN21_NORFL_A21 2 -#define PORTP_PIN21_SDRAM_BA1 2 - -#define PORTP_PIN22_GPIO 0 -#define PORTP_PIN22_FUNMUX 1 -#define PORTP_PIN22_NORFL_A22 2 - -#define PORTP_PIN23_GPIO 0 -#define PORTP_PIN23_FUNMUX 1 -#define PORTP_PIN23_NORFL_A23 2 - - - -/* 궨ȡֵȫȷֵĻϡ100궨ֵӶ⺯ıд*/ -/* ЩֵżŵĹȡֵPIN0PIN2... */ -#define FUNMUX0_UART0_RXD 100 -#define FUNMUX0_UART1_RXD 101 -#define FUNMUX0_UART2_RXD 102 -#define FUNMUX0_UART3_RXD 103 -#define FUNMUX0_I2C0_SCL 105 -#define FUNMUX0_I2C1_SCL 106 -#define FUNMUX0_PWM0A_OUT 107 -#define FUNMUX0_PWM2A_OUT 108 -#define FUNMUX0_PWM4A_OUT 109 -#define FUNMUX0_PWM0B_OUT 110 -#define FUNMUX0_PWM2B_OUT 111 -#define FUNMUX0_PWM4B_OUT 112 -#define FUNMUX0_PWM_BREAK 113 -#define FUNMUX0_TIMR0_IN 114 -#define FUNMUX0_TIMR2_IN 115 -#define FUNMUX0_CAN_RX 116 -#define FUNMUX0_SPI0_SSEL 117 -#define FUNMUX0_SPI0_MOSI 118 -#define FUNMUX0_SPI1_SSEL 119 -#define FUNMUX0_SPI1_MOSI 120 -#define FUNMUX0_UART0_CTS 121 -#define FUNMUX0_UART1_CTS 122 -#define FUNMUX0_UART2_CTS 123 -#define FUNMUX0_UART3_CTS 124 - -/* ЩֵŵĹȡֵPIN1PIN3... */ -#define FUNMUX1_UART0_TXD 100 -#define FUNMUX1_UART1_TXD 101 -#define FUNMUX1_UART2_TXD 102 -#define FUNMUX1_UART3_TXD 103 -#define FUNMUX1_I2C0_SDA 105 -#define FUNMUX1_I2C1_SDA 106 -#define FUNMUX1_PWM1A_OUT 107 -#define FUNMUX1_PWM3A_OUT 108 -#define FUNMUX1_PWM5A_OUT 109 -#define FUNMUX1_PWM1B_OUT 110 -#define FUNMUX1_PWM3B_OUT 111 -#define FUNMUX1_PWM5B_OUT 112 -#define FUNMUX1_PULSE_IN 113 -#define FUNMUX1_TIMR1_IN 114 -#define FUNMUX1_TIMR3_IN 115 -#define FUNMUX1_CAN_TX 116 -#define FUNMUX1_SPI0_SCLK 117 -#define FUNMUX1_SPI0_MISO 118 -#define FUNMUX1_SPI1_SCLK 119 -#define FUNMUX1_SPI1_MISO 120 -#define FUNMUX1_UART0_RTS 121 -#define FUNMUX1_UART1_RTS 122 -#define FUNMUX1_UART2_RTS 123 -#define FUNMUX1_UART3_RTS 124 +#define PORTM_PIN17_GPIO 0 +#define PORTM_PIN17_FUNMUX 1 +#define PORTM_PIN17_NORFL_WEN 2 +#define PORTM_PIN18_GPIO 0 +#define PORTM_PIN18_FUNMUX 1 +#define PORTM_PIN18_NORFL_CSN 2 + +#define PORTM_PIN19_GPIO 0 +#define PORTM_PIN19_FUNMUX 1 +#define PORTM_PIN19_SDRAM_CSN 2 + +#define PORTM_PIN20_GPIO 0 +#define PORTM_PIN20_FUNMUX 1 +#define PORTM_PIN20_SRAM_CSN 2 + +#define PORTM_PIN21_GPIO 0 +#define PORTM_PIN21_FUNMUX 1 +#define PORTM_PIN21_SDRAM_CKE 2 + +#define PORTN_PIN0_GPIO 0 +#define PORTN_PIN0_FUNMUX 1 +#define PORTN_PIN0_LCD_D0 2 +#define PORTN_PIN0_ADC1_IN4 3 + +#define PORTN_PIN1_GPIO 0 +#define PORTN_PIN1_FUNMUX 1 +#define PORTN_PIN1_LCD_D1 2 +#define PORTN_PIN1_ADC1_IN5 3 + +#define PORTN_PIN2_GPIO 0 +#define PORTN_PIN2_FUNMUX 1 +#define PORTN_PIN2_LCD_D2 2 +#define PORTN_PIN2_ADC1_IN6 3 + +#define PORTN_PIN3_GPIO 0 +#define PORTN_PIN3_FUNMUX 1 +#define PORTN_PIN3_LCD_D3 2 + +#define PORTN_PIN4_GPIO 0 +#define PORTN_PIN4_FUNMUX 1 +#define PORTN_PIN4_LCD_D4 2 + +#define PORTN_PIN5_GPIO 0 +#define PORTN_PIN5_FUNMUX 1 +#define PORTN_PIN5_LCD_D5 2 + +#define PORTN_PIN6_GPIO 0 +#define PORTN_PIN6_FUNMUX 1 +#define PORTN_PIN6_LCD_D6 2 + +#define PORTN_PIN7_GPIO 0 +#define PORTN_PIN7_FUNMUX 1 +#define PORTN_PIN7_LCD_D7 2 + +#define PORTN_PIN8_GPIO 0 +#define PORTN_PIN8_FUNMUX 1 +#define PORTN_PIN8_LCD_D8 2 + +#define PORTN_PIN9_GPIO 0 +#define PORTN_PIN9_FUNMUX 1 +#define PORTN_PIN9_LCD_D9 2 + +#define PORTN_PIN10_GPIO 0 +#define PORTN_PIN10_FUNMUX 1 +#define PORTN_PIN10_LCD_D10 2 + +#define PORTN_PIN11_GPIO 0 +#define PORTN_PIN11_FUNMUX 1 +#define PORTN_PIN11_LCD_D11 2 + +#define PORTN_PIN12_GPIO 0 +#define PORTN_PIN12_FUNMUX 1 +#define PORTN_PIN12_LCD_D12 2 + +#define PORTN_PIN13_GPIO 0 +#define PORTN_PIN13_FUNMUX 1 +#define PORTN_PIN13_LCD_D13 2 + +#define PORTN_PIN14_GPIO 0 +#define PORTN_PIN14_FUNMUX 1 +#define PORTN_PIN14_LCD_D14 2 + +#define PORTN_PIN15_GPIO 0 +#define PORTN_PIN15_FUNMUX 1 +#define PORTN_PIN15_LCD_D15 2 + +#define PORTN_PIN16_GPIO 0 +#define PORTN_PIN16_FUNMUX 1 +#define PORTN_PIN16_LCD_RD 2 +#define PORTN_PIN16_LCD_DOTCK 2 + +#define PORTN_PIN17_GPIO 0 +#define PORTN_PIN17_FUNMUX 1 +#define PORTN_PIN17_LCD_CS 2 +#define PORTN_PIN17_LCD_VSYNC 2 + +#define PORTN_PIN18_GPIO 0 +#define PORTN_PIN18_LCD_RS 2 +#define PORTN_PIN18_LCD_DATEN 2 //Data Enable + +#define PORTN_PIN19_GPIO 0 +#define PORTN_PIN19_LCD_WR 2 +#define PORTN_PIN19_LCD_HSYNC 2 + +#define PORTP_PIN0_GPIO 0 +#define PORTP_PIN0_FUNMUX 1 +#define PORTP_PIN0_NORFL_A0 2 + +#define PORTP_PIN1_GPIO 0 +#define PORTP_PIN1_FUNMUX 1 +#define PORTP_PIN1_NORFL_A1 2 + +#define PORTP_PIN2_GPIO 0 +#define PORTP_PIN2_FUNMUX 1 +#define PORTP_PIN2_NORFL_A2 2 +#define PORTP_PIN2_SD_D7 3 + +#define PORTP_PIN3_GPIO 0 +#define PORTP_PIN3_FUNMUX 1 +#define PORTP_PIN3_NORFL_A3 2 +#define PORTP_PIN3_SD_D6 3 + +#define PORTP_PIN4_GPIO 0 +#define PORTP_PIN4_FUNMUX 1 +#define PORTP_PIN4_NORFL_A4 2 +#define PORTP_PIN4_SD_D5 3 + +#define PORTP_PIN5_GPIO 0 +#define PORTP_PIN5_FUNMUX 1 +#define PORTP_PIN5_NORFL_A5 2 +#define PORTP_PIN5_SD_D4 3 + +#define PORTP_PIN6_GPIO 0 +#define PORTP_PIN6_FUNMUX 1 +#define PORTP_PIN6_NORFL_A6 2 +#define PORTP_PIN6_SD_D3 3 + +#define PORTP_PIN7_GPIO 0 +#define PORTP_PIN7_FUNMUX 1 +#define PORTP_PIN7_NORFL_A7 2 +#define PORTP_PIN7_SD_D2 3 + +#define PORTP_PIN8_GPIO 0 +#define PORTP_PIN8_FUNMUX 1 +#define PORTP_PIN8_NORFL_A8 2 +#define PORTP_PIN8_SD_D1 3 + +#define PORTP_PIN9_GPIO 0 +#define PORTP_PIN9_FUNMUX 1 +#define PORTP_PIN9_NORFL_A9 2 +#define PORTP_PIN9_SD_D0 3 + +#define PORTP_PIN10_GPIO 0 +#define PORTP_PIN10_FUNMUX 1 +#define PORTP_PIN10_NORFL_A10 2 +#define PORTP_PIN10_SD_CMD 3 + +#define PORTP_PIN11_GPIO 0 +#define PORTP_PIN11_FUNMUX 1 +#define PORTP_PIN11_NORFL_A11 2 +#define PORTP_PIN11_SD_CLK 3 + +#define PORTP_PIN12_GPIO 0 +#define PORTP_PIN12_FUNMUX 1 +#define PORTP_PIN12_NORFL_A12 2 +#define PORTP_PIN12_SD_DETECT 3 + +#define PORTP_PIN13_GPIO 0 +#define PORTP_PIN13_FUNMUX 1 +#define PORTP_PIN13_NORFL_A13 2 +#define PORTP_PIN13_SDRAM_CLK 2 + +#define PORTP_PIN14_GPIO 0 +#define PORTP_PIN14_FUNMUX 1 +#define PORTP_PIN14_NORFL_A14 2 +#define PORTP_PIN14_SDRAM_CAS 2 + +#define PORTP_PIN15_GPIO 0 +#define PORTP_PIN15_FUNMUX 1 +#define PORTP_PIN15_NORFL_A15 2 +#define PORTP_PIN15_SDRAM_RAS 2 + +#define PORTP_PIN16_GPIO 0 +#define PORTP_PIN16_FUNMUX 1 +#define PORTP_PIN16_NORFL_A16 2 +#define PORTP_PIN16_SDRAM_LDQ 2 + +#define PORTP_PIN17_GPIO 0 +#define PORTP_PIN17_FUNMUX 1 +#define PORTP_PIN17_NORFL_A17 2 +#define PORTP_PIN17_SDRAM_UDQ 2 + +#define PORTP_PIN18_GPIO 0 +#define PORTP_PIN18_FUNMUX 1 +#define PORTP_PIN18_NORFL_A18 2 + +#define PORTP_PIN19_GPIO 0 +#define PORTP_PIN19_FUNMUX 1 +#define PORTP_PIN19_NORFL_A19 2 + +#define PORTP_PIN20_GPIO 0 +#define PORTP_PIN20_FUNMUX 1 +#define PORTP_PIN20_NORFL_A20 2 +#define PORTP_PIN20_SDRAM_BA0 2 + +#define PORTP_PIN21_GPIO 0 +#define PORTP_PIN21_FUNMUX 1 +#define PORTP_PIN21_NORFL_A21 2 +#define PORTP_PIN21_SDRAM_BA1 2 + +#define PORTP_PIN22_GPIO 0 +#define PORTP_PIN22_FUNMUX 1 +#define PORTP_PIN22_NORFL_A22 2 + +#define PORTP_PIN23_GPIO 0 +#define PORTP_PIN23_FUNMUX 1 +#define PORTP_PIN23_NORFL_A23 2 + +/* 下面宏定义的取值全部在正确值的基础上“加100”，以区分上面宏定义的值，从而方便库函数的编写*/ +/* 下面这些值是偶数编号引脚的功能取值，如PIN0、PIN2、... */ +#define FUNMUX0_UART0_RXD 100 +#define FUNMUX0_UART1_RXD 101 +#define FUNMUX0_UART2_RXD 102 +#define FUNMUX0_UART3_RXD 103 +#define FUNMUX0_I2C0_SCL 105 +#define FUNMUX0_I2C1_SCL 106 +#define FUNMUX0_PWM0A_OUT 107 +#define FUNMUX0_PWM2A_OUT 108 +#define FUNMUX0_PWM4A_OUT 109 +#define FUNMUX0_PWM0B_OUT 110 +#define FUNMUX0_PWM2B_OUT 111 +#define FUNMUX0_PWM4B_OUT 112 +#define FUNMUX0_PWM_BREAK 113 +#define FUNMUX0_TIMR0_IN 114 +#define FUNMUX0_TIMR2_IN 115 +#define FUNMUX0_CAN_RX 116 +#define FUNMUX0_SPI0_SSEL 117 +#define FUNMUX0_SPI0_MOSI 118 +#define FUNMUX0_SPI1_SSEL 119 +#define FUNMUX0_SPI1_MOSI 120 +#define FUNMUX0_UART0_CTS 121 +#define FUNMUX0_UART1_CTS 122 +#define FUNMUX0_UART2_CTS 123 +#define FUNMUX0_UART3_CTS 124 + +/* 下面这些值是奇数编号引脚的功能取值，如PIN1、PIN3、... */ +#define FUNMUX1_UART0_TXD 100 +#define FUNMUX1_UART1_TXD 101 +#define FUNMUX1_UART2_TXD 102 +#define FUNMUX1_UART3_TXD 103 +#define FUNMUX1_I2C0_SDA 105 +#define FUNMUX1_I2C1_SDA 106 +#define FUNMUX1_PWM1A_OUT 107 +#define FUNMUX1_PWM3A_OUT 108 +#define FUNMUX1_PWM5A_OUT 109 +#define FUNMUX1_PWM1B_OUT 110 +#define FUNMUX1_PWM3B_OUT 111 +#define FUNMUX1_PWM5B_OUT 112 +#define FUNMUX1_PULSE_IN 113 +#define FUNMUX1_TIMR1_IN 114 +#define FUNMUX1_TIMR3_IN 115 +#define FUNMUX1_CAN_TX 116 +#define FUNMUX1_SPI0_SCLK 117 +#define FUNMUX1_SPI0_MISO 118 +#define FUNMUX1_SPI1_SCLK 119 +#define FUNMUX1_SPI1_MISO 120 +#define FUNMUX1_UART0_RTS 121 +#define FUNMUX1_UART1_RTS 122 +#define FUNMUX1_UART2_RTS 123 +#define FUNMUX1_UART3_RTS 124 #endif //__SWM320_PORT_H__ diff --git a/bsp/swm320-lq100/Libraries/SWM320_StdPeriph_Driver/SWM320_pwm.c b/bsp/swm320-lq100/Libraries/SWM320_StdPeriph_Driver/SWM320_pwm.c index 454d19e197..0d965e4792 100644 --- a/bsp/swm320-lq100/Libraries/SWM320_StdPeriph_Driver/SWM320_pwm.c +++ b/bsp/swm320-lq100/Libraries/SWM320_StdPeriph_Driver/SWM320_pwm.c @@ -24,7 +24,7 @@ /****************************************************************************************************************************************** * 函数名称: PWM_Init() * 功能说明: PWM初始化 -* 输 入: PWM_TypeDef * PWMx 指定要被设置的PWM，有效值包括PWM0、PWM1、PWM2、PWM3、PWM4、PWM5 +* 输 入: PWM_TypeDef * PWMx 指定要被设置的PWM，有效值包括PWM0、PWM1、PWM2、PWM3、PWM4、PWM5 * PWM_InitStructure * initStruct 包含PWM相关设定值的结构体 * 输 出: 无 * 注意事项: 无 @@ -101,9 +101,9 @@ void PWM_Init(PWM_TypeDef *PWMx, PWM_InitStructure *initStruct) /****************************************************************************************************************************************** * 函数名称: PWM_Start() * 功能说明: 启动PWM，开始PWM输出 -* 输 入: PWM_TypeDef * PWMx 指定要被设置的PWM，有效值包括PWM0、PWM1、PWM2、PWM3、PWM4、PWM5 -* uint32_t chA 0 通道A不启动 1 通道A启动 -* uint32_t chB 0 通道B不启动 1 通道B启动 +* 输 入: PWM_TypeDef * PWMx 指定要被设置的PWM，有效值包括PWM0、PWM1、PWM2、PWM3、PWM4、PWM5 +* uint32_t chA 0 通道A不启动 1 通道A启动 +* uint32_t chB 0 通道B不启动 1 通道B启动 * 输 出: 无 * 注意事项: 无 ******************************************************************************************************************************************/ @@ -140,9 +140,9 @@ void PWM_Start(PWM_TypeDef *PWMx, uint32_t chA, uint32_t chB) /****************************************************************************************************************************************** * 函数名称: PWM_Stop() * 功能说明: 关闭PWM，停止PWM输出 -* 输 入: PWM_TypeDef * PWMx 指定要被设置的PWM，有效值包括PWM0、PWM1、PWM2、PWM3、PWM4、PWM5 -* uint32_t chA 0 通道A不关闭 1 通道A关闭 -* uint32_t chB 0 通道B不关闭 1 通道B关闭 +* 输 入: PWM_TypeDef * PWMx 指定要被设置的PWM，有效值包括PWM0、PWM1、PWM2、PWM3、PWM4、PWM5 +* uint32_t chA 0 通道A不关闭 1 通道A关闭 +* uint32_t chB 0 通道B不关闭 1 通道B关闭 * 输 出: 无 * 注意事项: 无 ******************************************************************************************************************************************/ @@ -179,7 +179,7 @@ void PWM_Stop(PWM_TypeDef *PWMx, uint32_t chA, uint32_t chB) /****************************************************************************************************************************************** * 函数名称: PWM_SetCycle() * 功能说明: 设置周期 -* 输 入: PWM_TypeDef * PWMx 指定要被设置的PWM，有效值包括PWM0、PWM1、PWM2、PWM3、PWM4、PWM5 +* 输 入: PWM_TypeDef * PWMx 指定要被设置的PWM，有效值包括PWM0、PWM1、PWM2、PWM3、PWM4、PWM5 * uint32_t chn 选择要设置哪个通道，有效值：PWM_CH_A、PWM_CH_B * uint16_t cycle 要设定的周期值 * 输 出: 无 @@ -196,9 +196,9 @@ void PWM_SetCycle(PWM_TypeDef *PWMx, uint32_t chn, uint16_t cycle) /****************************************************************************************************************************************** * 函数名称: PWM_GetCycle() * 功能说明: 获取周期 -* 输 入: PWM_TypeDef * PWMx 指定要被设置的PWM，有效值包括PWM0、PWM1、PWM2、PWM3、PWM4、PWM5 +* 输 入: PWM_TypeDef * PWMx 指定要被设置的PWM，有效值包括PWM0、PWM1、PWM2、PWM3、PWM4、PWM5 * uint32_t chn 选择要查询哪个通道，有效值：PWM_CH_A、PWM_CH_B -* 输 出: uint16_t 获取到的周期值 +* 输 出: uint16_t 获取到的周期值 * 注意事项: 无 ******************************************************************************************************************************************/ uint16_t PWM_GetCycle(PWM_TypeDef *PWMx, uint32_t chn) @@ -216,7 +216,7 @@ uint16_t PWM_GetCycle(PWM_TypeDef *PWMx, uint32_t chn) /****************************************************************************************************************************************** * 函数名称: PWM_SetHDuty() * 功能说明: 设置高电平时长 -* 输 入: PWM_TypeDef * PWMx 指定要被设置的PWM，有效值包括PWM0、PWM1、PWM2、PWM3、PWM4、PWM5 +* 输 入: PWM_TypeDef * PWMx 指定要被设置的PWM，有效值包括PWM0、PWM1、PWM2、PWM3、PWM4、PWM5 * uint32_t chn 选择要设置哪个通道，有效值：PWM_CH_A、PWM_CH_B * uint16_t hduty 要设定的高电平时长 * 输 出: 无 @@ -233,9 +233,9 @@ void PWM_SetHDuty(PWM_TypeDef *PWMx, uint32_t chn, uint16_t hduty) /****************************************************************************************************************************************** * 函数名称: PWM_GetHDuty() * 功能说明: 获取高电平时长 -* 输 入: PWM_TypeDef * PWMx 指定要被设置的PWM，有效值包括PWM0、PWM1、PWM2、PWM3、PWM4、PWM5 +* 输 入: PWM_TypeDef * PWMx 指定要被设置的PWM，有效值包括PWM0、PWM1、PWM2、PWM3、PWM4、PWM5 * uint32_t chn 选择要查询哪个通道，有效值：PWM_CH_A、PWM_CH_B -* 输 出: uint16_t 获取到的高电平时长 +* 输 出: uint16_t 获取到的高电平时长 * 注意事项: 无 ******************************************************************************************************************************************/ uint16_t PWM_GetHDuty(PWM_TypeDef *PWMx, uint32_t chn) @@ -253,7 +253,7 @@ uint16_t PWM_GetHDuty(PWM_TypeDef *PWMx, uint32_t chn) /****************************************************************************************************************************************** * 函数名称: PWM_SetDeadzone() * 功能说明: 设置死区时长 -* 输 入: PWM_TypeDef * PWMx 指定要被设置的PWM，有效值包括PWM0、PWM1、PWM2、PWM3、PWM4、PWM5 +* 输 入: PWM_TypeDef * PWMx 指定要被设置的PWM，有效值包括PWM0、PWM1、PWM2、PWM3、PWM4、PWM5 * uint32_t chn 选择要设置哪个通道，有效值：PWM_CH_A、PWM_CH_B * uint8_t deadzone 要设定的死区时长 * 输 出: 无 @@ -270,9 +270,9 @@ void PWM_SetDeadzone(PWM_TypeDef *PWMx, uint32_t chn, uint8_t deadzone) /****************************************************************************************************************************************** * 函数名称: PWM_GetDeadzone() * 功能说明: 获取死区时长 -* 输 入: PWM_TypeDef * PWMx 指定要被设置的PWM，有效值包括PWM0、PWM1、PWM2、PWM3、PWM4、PWM5 +* 输 入: PWM_TypeDef * PWMx 指定要被设置的PWM，有效值包括PWM0、PWM1、PWM2、PWM3、PWM4、PWM5 * uint32_t chn 选择要查询哪个通道，有效值：PWM_CH_A、PWM_CH_B -* 输 出: uint8_t 获取到的死区时长 +* 输 出: uint8_t 获取到的死区时长 * 注意事项: 无 ******************************************************************************************************************************************/ uint8_t PWM_GetDeadzone(PWM_TypeDef *PWMx, uint32_t chn) @@ -290,7 +290,7 @@ uint8_t PWM_GetDeadzone(PWM_TypeDef *PWMx, uint32_t chn) /****************************************************************************************************************************************** * 函数名称: PWM_IntNCycleEn() * 功能说明: 新周期开始中断使能 -* 输 入: PWM_TypeDef * PWMx 指定要被设置的PWM，有效值包括PWM0、PWM1、PWM2、PWM3、PWM4、PWM5 +* 输 入: PWM_TypeDef * PWMx 指定要被设置的PWM，有效值包括PWM0、PWM1、PWM2、PWM3、PWM4、PWM5 * uint32_t chn 选择要设置哪个通道，有效值：PWM_CH_A、PWM_CH_B * 输 出: 无 * 注意事项: 无 @@ -346,7 +346,7 @@ void PWM_IntNCycleEn(PWM_TypeDef *PWMx, uint32_t chn) /****************************************************************************************************************************************** * 函数名称: PWM_IntNCycleDis() * 功能说明: 新周期开始中断禁能 -* 输 入: PWM_TypeDef * PWMx 指定要被设置的PWM，有效值包括PWM0、PWM1、PWM2、PWM3、PWM4、PWM5 +* 输 入: PWM_TypeDef * PWMx 指定要被设置的PWM，有效值包括PWM0、PWM1、PWM2、PWM3、PWM4、PWM5 * uint32_t chn 选择要设置哪个通道，有效值：PWM_CH_A、PWM_CH_B * 输 出: 无 * 注意事项: 无 @@ -402,7 +402,7 @@ void PWM_IntNCycleDis(PWM_TypeDef *PWMx, uint32_t chn) /****************************************************************************************************************************************** * 函数名称: PWM_IntNCycleClr() * 功能说明: 新周期开始中断标志清除 -* 输 入: PWM_TypeDef * PWMx 指定要被设置的PWM，有效值包括PWM0、PWM1、PWM2、PWM3、PWM4、PWM5 +* 输 入: PWM_TypeDef * PWMx 指定要被设置的PWM，有效值包括PWM0、PWM1、PWM2、PWM3、PWM4、PWM5 * uint32_t chn 选择要设置哪个通道，有效值：PWM_CH_A、PWM_CH_B * 输 出: 无 * 注意事项: 无 @@ -458,9 +458,9 @@ void PWM_IntNCycleClr(PWM_TypeDef *PWMx, uint32_t chn) /****************************************************************************************************************************************** * 函数名称: PWM_IntNCycleStat() * 功能说明: 新周期开始中断是否发生 -* 输 入: PWM_TypeDef * PWMx 指定要被设置的PWM，有效值包括PWM0、PWM1、PWM2、PWM3、PWM4、PWM5 +* 输 入: PWM_TypeDef * PWMx 指定要被设置的PWM，有效值包括PWM0、PWM1、PWM2、PWM3、PWM4、PWM5 * uint32_t chn 选择要设置哪个通道，有效值：PWM_CH_A、PWM_CH_B -* 输 出: uint32_t 1 新周期开始中断已发生 0 新周期开始中断未发生 +* 输 出: uint32_t 1 新周期开始中断已发生 0 新周期开始中断未发生 * 注意事项: 无 ******************************************************************************************************************************************/ uint32_t PWM_IntNCycleStat(PWM_TypeDef *PWMx, uint32_t chn) @@ -518,7 +518,7 @@ uint32_t PWM_IntNCycleStat(PWM_TypeDef *PWMx, uint32_t chn) /****************************************************************************************************************************************** * 函数名称: PWM_IntHEndEn() * 功能说明: 高电平结束中断使能 -* 输 入: PWM_TypeDef * PWMx 指定要被设置的PWM，有效值包括PWM0、PWM1、PWM2、PWM3、PWM4、PWM5 +* 输 入: PWM_TypeDef * PWMx 指定要被设置的PWM，有效值包括PWM0、PWM1、PWM2、PWM3、PWM4、PWM5 * uint32_t chn 选择要设置哪个通道，有效值：PWM_CH_A、PWM_CH_B * 输 出: 无 * 注意事项: 无 @@ -574,7 +574,7 @@ void PWM_IntHEndEn(PWM_TypeDef *PWMx, uint32_t chn) /****************************************************************************************************************************************** * 函数名称: PWM_IntHEndDis() * 功能说明: 高电平结束中断禁能 -* 输 入: PWM_TypeDef * PWMx 指定要被设置的PWM，有效值包括PWM0、PWM1、PWM2、PWM3、PWM4、PWM5 +* 输 入: PWM_TypeDef * PWMx 指定要被设置的PWM，有效值包括PWM0、PWM1、PWM2、PWM3、PWM4、PWM5 * uint32_t chn 选择要设置哪个通道，有效值：PWM_CH_A、PWM_CH_B * 输 出: 无 * 注意事项: 无 @@ -630,7 +630,7 @@ void PWM_IntHEndDis(PWM_TypeDef *PWMx, uint32_t chn) /****************************************************************************************************************************************** * 函数名称: PWM_IntHEndClr() * 功能说明: 高电平结束中断标志清除 -* 输 入: PWM_TypeDef * PWMx 指定要被设置的PWM，有效值包括PWM0、PWM1、PWM2、PWM3、PWM4、PWM5 +* 输 入: PWM_TypeDef * PWMx 指定要被设置的PWM，有效值包括PWM0、PWM1、PWM2、PWM3、PWM4、PWM5 * uint32_t chn 选择要设置哪个通道，有效值：PWM_CH_A、PWM_CH_B * 输 出: 无 * 注意事项: 无 @@ -686,9 +686,9 @@ void PWM_IntHEndClr(PWM_TypeDef *PWMx, uint32_t chn) /****************************************************************************************************************************************** * 函数名称: PWM_IntHEndStat() * 功能说明: 高电平结束中断是否发生 -* 输 入: PWM_TypeDef * PWMx 指定要被设置的PWM，有效值包括PWM0、PWM1、PWM2、PWM3、PWM4、PWM5 +* 输 入: PWM_TypeDef * PWMx 指定要被设置的PWM，有效值包括PWM0、PWM1、PWM2、PWM3、PWM4、PWM5 * uint32_t chn 选择要设置哪个通道，有效值：PWM_CH_A、PWM_CH_B -* 输 出: uint32_t 1 高电平结束中断已发生 0 高电平结束中断未发生 +* 输 出: uint32_t 1 高电平结束中断已发生 0 高电平结束中断未发生 * 注意事项: 无 ******************************************************************************************************************************************/ uint32_t PWM_IntHEndStat(PWM_TypeDef *PWMx, uint32_t chn) diff --git a/bsp/swm320-lq100/Libraries/SWM320_StdPeriph_Driver/SWM320_rtc.c b/bsp/swm320-lq100/Libraries/SWM320_StdPeriph_Driver/SWM320_rtc.c index 60958799ed..b2cb77a5f3 100644 --- a/bsp/swm320-lq100/Libraries/SWM320_StdPeriph_Driver/SWM320_rtc.c +++ b/bsp/swm320-lq100/Libraries/SWM320_StdPeriph_Driver/SWM320_rtc.c @@ -1,10 +1,10 @@ /****************************************************************************************************************************************** -* ļ: SWM320_rtc.c -* ˵: SWM320ƬRTC -* ֧: http://www.synwit.com.cn/e/tool/gbook/?bid=1 -* ע: -* 汾: V1.1.0 20171025 -* ¼: +* 文件名称: SWM320_rtc.c +* 功能说明: SWM320单片机的RTC驱动库 +* 技术支持: http://www.synwit.com.cn/e/tool/gbook/?bid=1 +* 注意事项: +* 版本日期: V1.1.0 2017年10月25日 +* 升级记录: * * ******************************************************************************************************************************************* @@ -21,39 +21,39 @@ #include "SWM320.h" #include "SWM320_rtc.h" - static uint32_t calcWeekDay(uint32_t year, uint32_t month, uint32_t date); /****************************************************************************************************************************************** -* : RTC_Init() -* ˵: RTCʼ -* : RTC_TypeDef * RTCx ָҪõRTCЧֵRTC -* RTC_InitStructure * initStruct RTC趨ֵĽṹ -* : -* ע: +* 函数名称: RTC_Init() +* 功能说明: RTC初始化 +* 输 入: RTC_TypeDef * RTCx 指定要被设置的RTC，有效值包括RTC +* RTC_InitStructure * initStruct 包含RTC相关设定值的结构体 +* 输 出: 无 +* 注意事项: 无 ******************************************************************************************************************************************/ void RTC_Init(RTC_TypeDef *RTCx, RTC_InitStructure *initStruct) { SYS->CLKEN |= (1 << SYS_CLKEN_RTCBKP_Pos); - SYS->LRCCR &= ~(1 << SYS_LRCCR_OFF_Pos); //RTCʹ32KHz RCʱ + SYS->LRCCR &= ~(1 << SYS_LRCCR_OFF_Pos); //RTC使用32KHz RC时钟 SYS->CLKEN |= (1 << SYS_CLKEN_RTC_Pos) | ((uint32_t)1 << SYS_CLKEN_ALIVE_Pos); RTC_Stop(RTCx); - while (RTCx->CFGABLE == 0); + while (RTCx->CFGABLE == 0) + ; RTCx->MINSEC = (initStruct->Second << RTC_MINSEC_SEC_Pos) | (initStruct->Minute << RTC_MINSEC_MIN_Pos); RTCx->DATHUR = (initStruct->Hour << RTC_DATHUR_HOUR_Pos) | - ((initStruct->Date - 1) << RTC_DATHUR_DATE_Pos); + (initStruct->Date << RTC_DATHUR_DATE_Pos); RTCx->MONDAY = (calcWeekDay(initStruct->Year, initStruct->Month, initStruct->Date) << RTC_MONDAY_DAY_Pos) | - ((initStruct->Month - 1) << RTC_MONDAY_MON_Pos); + (initStruct->Month << RTC_MONDAY_MON_Pos); - RTCx->YEAR = initStruct->Year - 1901; + RTCx->YEAR = initStruct->Year; RTCx->LOAD = 1 << RTC_LOAD_TIME_Pos; @@ -72,11 +72,11 @@ void RTC_Init(RTC_TypeDef *RTCx, RTC_InitStructure *initStruct) } /****************************************************************************************************************************************** -* : RTC_Start() -* ˵: RTC -* : RTC_TypeDef * RTCx ָҪõRTCȡֵRTC -* : -* ע: +* 函数名称: RTC_Start() +* 功能说明: 启动RTC +* 输 入: RTC_TypeDef * RTCx 指定要被设置的RTC，可取值包括RTC +* 输 出: 无 +* 注意事项: 无 ******************************************************************************************************************************************/ void RTC_Start(RTC_TypeDef *RTCx) { @@ -84,11 +84,11 @@ void RTC_Start(RTC_TypeDef *RTCx) } /****************************************************************************************************************************************** -* : RTC_Stop() -* ˵: ֹͣRTC -* : RTC_TypeDef * RTCx ָҪõRTCȡֵRTC -* : -* ע: +* 函数名称: RTC_Stop() +* 功能说明: 停止RTC +* 输 入: RTC_TypeDef * RTCx 指定要被设置的RTC，可取值包括RTC +* 输 出: 无 +* 注意事项: 无 ******************************************************************************************************************************************/ void RTC_Stop(RTC_TypeDef *RTCx) { @@ -96,18 +96,18 @@ void RTC_Stop(RTC_TypeDef *RTCx) } /****************************************************************************************************************************************** -* : RTC_GetDateTime() -* ˵: ȡǰʱ -* : RTC_TypeDef * RTCx ָҪõRTCЧֵRTC -* RTC_DateTime * dateTime ȡʱ䡢ֵָָĽṹ -* : -* ע: +* 函数名称: RTC_GetDateTime() +* 功能说明: 获取当前的时间和日期 +* 输 入: RTC_TypeDef * RTCx 指定要被设置的RTC，有效值包括RTC +* RTC_DateTime * dateTime 获取到的时间、日期值存入此指针指向的结构体 +* 输 出: 无 +* 注意事项: 无 ******************************************************************************************************************************************/ void RTC_GetDateTime(RTC_TypeDef *RTCx, RTC_DateTime *dateTime) { - dateTime->Year = RTCx->YEAR + 1901; - dateTime->Month = ((RTCx->MONDAY & RTC_MONDAY_MON_Msk) >> RTC_MONDAY_MON_Pos) + 1; - dateTime->Date = ((RTCx->DATHUR & RTC_DATHUR_DATE_Msk) >> RTC_DATHUR_DATE_Pos) + 1; + dateTime->Year = RTCx->YEAR; + dateTime->Month = (RTCx->MONDAY & RTC_MONDAY_MON_Msk) >> RTC_MONDAY_MON_Pos; + dateTime->Date = (RTCx->DATHUR & RTC_DATHUR_DATE_Msk) >> RTC_DATHUR_DATE_Pos; dateTime->Day = 1 << ((RTCx->MONDAY & RTC_MONDAY_DAY_Msk) >> RTC_MONDAY_DAY_Pos); dateTime->Hour = (RTCx->DATHUR & RTC_DATHUR_HOUR_Msk) >> RTC_DATHUR_HOUR_Pos; dateTime->Minute = (RTCx->MINSEC & RTC_MINSEC_MIN_Msk) >> RTC_MINSEC_MIN_Pos; @@ -115,16 +115,17 @@ void RTC_GetDateTime(RTC_TypeDef *RTCx, RTC_DateTime *dateTime) } /****************************************************************************************************************************************** -* : RTC_AlarmSetup() -* ˵: RTC趨 -* : RTC_TypeDef * RTCx ָҪõRTCЧֵRTC -* RTC_AlarmStructure * alarmStruct RTC趨ֵĽṹ -* : -* ע: +* 函数名称: RTC_AlarmSetup() +* 功能说明: RTC闹钟设定 +* 输 入: RTC_TypeDef * RTCx 指定要被设置的RTC，有效值包括RTC +* RTC_AlarmStructure * alarmStruct 包含RTC闹钟设定值的结构体 +* 输 出: 无 +* 注意事项: 无 ******************************************************************************************************************************************/ void RTC_AlarmSetup(RTC_TypeDef *RTCx, RTC_AlarmStructure *alarmStruct) { - while (RTCx->CFGABLE == 0); + while (RTCx->CFGABLE == 0) + ; RTCx->MINSECAL = (alarmStruct->Second << RTC_MINSECAL_SEC_Pos) | (alarmStruct->Minute << RTC_MINSECAL_MIN_Pos); @@ -133,51 +134,56 @@ void RTC_AlarmSetup(RTC_TypeDef *RTCx, RTC_AlarmStructure *alarmStruct) (alarmStruct->Days << RTC_DAYHURAL_SUN_Pos); RTCx->LOAD = 1 << RTC_LOAD_ALARM_Pos; - while (RTCx->LOAD & RTC_LOAD_ALARM_Msk); + while (RTCx->LOAD & RTC_LOAD_ALARM_Msk) + ; RTCx->IF = (1 << RTC_IF_ALARM_Pos); RTCx->IE &= ~RTC_IE_ALARM_Msk; RTCx->IE |= (alarmStruct->AlarmIEn << RTC_IE_ALARM_Pos); - if (alarmStruct->AlarmIEn) NVIC_EnableIRQ(RTC_IRQn); + if (alarmStruct->AlarmIEn) + NVIC_EnableIRQ(RTC_IRQn); } /****************************************************************************************************************************************** -* : calcWeekDay() -* ˵: ָꡢ¡ڼ -* : uint32_t year -* uint32_t month -* uint32_t date -* : uint32_t 0 1 һ ... ... 6 -* ע: +* 函数名称: calcWeekDay() +* 功能说明: 计算指定年、月、日是星期几 +* 输 入: uint32_t year 年 +* uint32_t month 月 +* uint32_t date 日 +* 输 出: uint32_t 0 星期日 1 星期一 ... ... 6 星期六 +* 注意事项: 无 ******************************************************************************************************************************************/ static uint32_t calcWeekDay(uint32_t year, uint32_t month, uint32_t date) { uint32_t i, cnt = 0; const uint32_t daysOfMonth[13] = {0, 31, 28, 31, 30, 31, 30, 31, 31, 30, 31, 30, 31}; - for (i = 1; i < month; i++) cnt += daysOfMonth[i]; + for (i = 1; i < month; i++) + cnt += daysOfMonth[i]; cnt += date; - if ((year % 4 == 0) && ((year % 100 != 0) || (year % 400 == 0)) && (month >= 3)) cnt += 1; + if ((year % 4 == 0) && ((year % 100 != 0) || (year % 400 == 0)) && (month >= 3)) + cnt += 1; cnt += (year - 1901) * 365; for (i = 1901; i < year; i++) { - if ((i % 4 == 0) && ((i % 100 != 0) || (i % 400 == 0))) cnt += 1; + if ((i % 4 == 0) && ((i % 100 != 0) || (i % 400 == 0))) + cnt += 1; } return (cnt + 1) % 7; } /****************************************************************************************************************************************** -* : RTC_IntSecondEn() -* ˵: жʹ -* : RTC_TypeDef * RTCx ָҪõRTCȡֵRTC -* : -* ע: +* 函数名称: RTC_IntSecondEn() +* 功能说明: 秒中断使能 +* 输 入: RTC_TypeDef * RTCx 指定要被设置的RTC，可取值包括RTC +* 输 出: 无 +* 注意事项: 无 ******************************************************************************************************************************************/ void RTC_IntSecondEn(RTC_TypeDef *RTCx) { @@ -185,11 +191,11 @@ void RTC_IntSecondEn(RTC_TypeDef *RTCx) } /****************************************************************************************************************************************** -* : RTC_IntSecondDis() -* ˵: жϽֹ -* : RTC_TypeDef * RTCx ָҪõRTCȡֵRTC -* : -* ע: +* 函数名称: RTC_IntSecondDis() +* 功能说明: 秒中断禁止 +* 输 入: RTC_TypeDef * RTCx 指定要被设置的RTC，可取值包括RTC +* 输 出: 无 +* 注意事项: 无 ******************************************************************************************************************************************/ void RTC_IntSecondDis(RTC_TypeDef *RTCx) { @@ -197,11 +203,11 @@ void RTC_IntSecondDis(RTC_TypeDef *RTCx) } /****************************************************************************************************************************************** -* : RTC_IntSecondClr() -* ˵: жϱ־ -* : RTC_TypeDef * RTCx ָҪõRTCȡֵRTC -* : -* ע: +* 函数名称: RTC_IntSecondClr() +* 功能说明: 秒中断标志清除 +* 输 入: RTC_TypeDef * RTCx 指定要被设置的RTC，可取值包括RTC +* 输 出: 无 +* 注意事项: 无 ******************************************************************************************************************************************/ void RTC_IntSecondClr(RTC_TypeDef *RTCx) { @@ -209,11 +215,11 @@ void RTC_IntSecondClr(RTC_TypeDef *RTCx) } /****************************************************************************************************************************************** -* : RTC_IntSecondStat() -* ˵: ж״̬ -* : RTC_TypeDef * RTCx ָҪõRTCȡֵRTC -* : uint32_t 1 жϷ 0 жδ -* ע: +* 函数名称: RTC_IntSecondStat() +* 功能说明: 秒中断状态 +* 输 入: RTC_TypeDef * RTCx 指定要被设置的RTC，可取值包括RTC +* 输 出: uint32_t 1 秒中断发生 0 秒中断未发生 +* 注意事项: 无 ******************************************************************************************************************************************/ uint32_t RTC_IntSecondStat(RTC_TypeDef *RTCx) { @@ -221,11 +227,11 @@ uint32_t RTC_IntSecondStat(RTC_TypeDef *RTCx) } /****************************************************************************************************************************************** -* : RTC_IntMinuteEn() -* ˵: жʹ -* : RTC_TypeDef * RTCx ָҪõRTCȡֵRTC -* : -* ע: +* 函数名称: RTC_IntMinuteEn() +* 功能说明: 分中断使能 +* 输 入: RTC_TypeDef * RTCx 指定要被设置的RTC，可取值包括RTC +* 输 出: 无 +* 注意事项: 无 ******************************************************************************************************************************************/ void RTC_IntMinuteEn(RTC_TypeDef *RTCx) { @@ -233,11 +239,11 @@ void RTC_IntMinuteEn(RTC_TypeDef *RTCx) } /****************************************************************************************************************************************** -* : RTC_IntMinuteDis() -* ˵: жϽֹ -* : RTC_TypeDef * RTCx ָҪõRTCȡֵRTC -* : -* ע: +* 函数名称: RTC_IntMinuteDis() +* 功能说明: 分中断禁止 +* 输 入: RTC_TypeDef * RTCx 指定要被设置的RTC，可取值包括RTC +* 输 出: 无 +* 注意事项: 无 ******************************************************************************************************************************************/ void RTC_IntMinuteDis(RTC_TypeDef *RTCx) { @@ -245,11 +251,11 @@ void RTC_IntMinuteDis(RTC_TypeDef *RTCx) } /****************************************************************************************************************************************** -* : RTC_IntMinuteClr() -* ˵: жϱ־ -* : RTC_TypeDef * RTCx ָҪõRTCȡֵRTC -* : -* ע: +* 函数名称: RTC_IntMinuteClr() +* 功能说明: 分中断标志清除 +* 输 入: RTC_TypeDef * RTCx 指定要被设置的RTC，可取值包括RTC +* 输 出: 无 +* 注意事项: 无 ******************************************************************************************************************************************/ void RTC_IntMinuteClr(RTC_TypeDef *RTCx) { @@ -257,11 +263,11 @@ void RTC_IntMinuteClr(RTC_TypeDef *RTCx) } /****************************************************************************************************************************************** -* : RTC_IntMinuteStat() -* ˵: ж״̬ -* : RTC_TypeDef * RTCx ָҪõRTCȡֵRTC -* : uint32_t 1 жϷ 0 жδ -* ע: +* 函数名称: RTC_IntMinuteStat() +* 功能说明: 分中断状态 +* 输 入: RTC_TypeDef * RTCx 指定要被设置的RTC，可取值包括RTC +* 输 出: uint32_t 1 分中断发生 0 分中断未发生 +* 注意事项: 无 ******************************************************************************************************************************************/ uint32_t RTC_IntMinuteStat(RTC_TypeDef *RTCx) { @@ -269,11 +275,11 @@ uint32_t RTC_IntMinuteStat(RTC_TypeDef *RTCx) } /****************************************************************************************************************************************** -* : RTC_IntHourEn() -* ˵: ʱжʹ -* : RTC_TypeDef * RTCx ָҪõRTCȡֵRTC -* : -* ע: +* 函数名称: RTC_IntHourEn() +* 功能说明: 时中断使能 +* 输 入: RTC_TypeDef * RTCx 指定要被设置的RTC，可取值包括RTC +* 输 出: 无 +* 注意事项: 无 ******************************************************************************************************************************************/ void RTC_IntHourEn(RTC_TypeDef *RTCx) { @@ -281,11 +287,11 @@ void RTC_IntHourEn(RTC_TypeDef *RTCx) } /****************************************************************************************************************************************** -* : RTC_IntHourDis() -* ˵: ʱжϽֹ -* : RTC_TypeDef * RTCx ָҪõRTCȡֵRTC -* : -* ע: +* 函数名称: RTC_IntHourDis() +* 功能说明: 时中断禁止 +* 输 入: RTC_TypeDef * RTCx 指定要被设置的RTC，可取值包括RTC +* 输 出: 无 +* 注意事项: 无 ******************************************************************************************************************************************/ void RTC_IntHourDis(RTC_TypeDef *RTCx) { @@ -293,11 +299,11 @@ void RTC_IntHourDis(RTC_TypeDef *RTCx) } /****************************************************************************************************************************************** -* : RTC_IntHourClr() -* ˵: ʱжϱ־ -* : RTC_TypeDef * RTCx ָҪõRTCȡֵRTC -* : -* ע: +* 函数名称: RTC_IntHourClr() +* 功能说明: 时中断标志清除 +* 输 入: RTC_TypeDef * RTCx 指定要被设置的RTC，可取值包括RTC +* 输 出: 无 +* 注意事项: 无 ******************************************************************************************************************************************/ void RTC_IntHourClr(RTC_TypeDef *RTCx) { @@ -305,11 +311,11 @@ void RTC_IntHourClr(RTC_TypeDef *RTCx) } /****************************************************************************************************************************************** -* : RTC_IntHourStat() -* ˵: ʱж״̬ -* : RTC_TypeDef * RTCx ָҪõRTCȡֵRTC -* : uint32_t 1 ʱжϷ 0 ʱжδ -* ע: +* 函数名称: RTC_IntHourStat() +* 功能说明: 时中断状态 +* 输 入: RTC_TypeDef * RTCx 指定要被设置的RTC，可取值包括RTC +* 输 出: uint32_t 1 时中断发生 0 时中断未发生 +* 注意事项: 无 ******************************************************************************************************************************************/ uint32_t RTC_IntHourStat(RTC_TypeDef *RTCx) { @@ -317,11 +323,11 @@ uint32_t RTC_IntHourStat(RTC_TypeDef *RTCx) } /****************************************************************************************************************************************** -* : RTC_IntDateEn() -* ˵: жʹ -* : RTC_TypeDef * RTCx ָҪõRTCȡֵRTC -* : -* ע: +* 函数名称: RTC_IntDateEn() +* 功能说明: 日中断使能 +* 输 入: RTC_TypeDef * RTCx 指定要被设置的RTC，可取值包括RTC +* 输 出: 无 +* 注意事项: 无 ******************************************************************************************************************************************/ void RTC_IntDateEn(RTC_TypeDef *RTCx) { @@ -329,11 +335,11 @@ void RTC_IntDateEn(RTC_TypeDef *RTCx) } /****************************************************************************************************************************************** -* : RTC_IntDateDis() -* ˵: жϽֹ -* : RTC_TypeDef * RTCx ָҪõRTCȡֵRTC -* : -* ע: +* 函数名称: RTC_IntDateDis() +* 功能说明: 日中断禁止 +* 输 入: RTC_TypeDef * RTCx 指定要被设置的RTC，可取值包括RTC +* 输 出: 无 +* 注意事项: 无 ******************************************************************************************************************************************/ void RTC_IntDateDis(RTC_TypeDef *RTCx) { @@ -341,11 +347,11 @@ void RTC_IntDateDis(RTC_TypeDef *RTCx) } /****************************************************************************************************************************************** -* : RTC_IntDateClr() -* ˵: жϱ־ -* : RTC_TypeDef * RTCx ָҪõRTCȡֵRTC -* : -* ע: +* 函数名称: RTC_IntDateClr() +* 功能说明: 日中断标志清除 +* 输 入: RTC_TypeDef * RTCx 指定要被设置的RTC，可取值包括RTC +* 输 出: 无 +* 注意事项: 无 ******************************************************************************************************************************************/ void RTC_IntDateClr(RTC_TypeDef *RTCx) { @@ -353,11 +359,11 @@ void RTC_IntDateClr(RTC_TypeDef *RTCx) } /****************************************************************************************************************************************** -* : RTC_IntDateStat() -* ˵: ж״̬ -* : RTC_TypeDef * RTCx ָҪõRTCȡֵRTC -* : uint32_t 1 жϷ 0 жδ -* ע: +* 函数名称: RTC_IntDateStat() +* 功能说明: 日中断状态 +* 输 入: RTC_TypeDef * RTCx 指定要被设置的RTC，可取值包括RTC +* 输 出: uint32_t 1 日中断发生 0 日中断未发生 +* 注意事项: 无 ******************************************************************************************************************************************/ uint32_t RTC_IntDateStat(RTC_TypeDef *RTCx) { @@ -365,11 +371,11 @@ uint32_t RTC_IntDateStat(RTC_TypeDef *RTCx) } /****************************************************************************************************************************************** -* : RTC_IntAlarmEn() -* ˵: жʹ -* : RTC_TypeDef * RTCx ָҪõRTCȡֵRTC -* : -* ע: +* 函数名称: RTC_IntAlarmEn() +* 功能说明: 闹钟中断使能 +* 输 入: RTC_TypeDef * RTCx 指定要被设置的RTC，可取值包括RTC +* 输 出: 无 +* 注意事项: 无 ******************************************************************************************************************************************/ void RTC_IntAlarmEn(RTC_TypeDef *RTCx) { @@ -377,11 +383,11 @@ void RTC_IntAlarmEn(RTC_TypeDef *RTCx) } /****************************************************************************************************************************************** -* : RTC_IntAlarmDis() -* ˵: жϽֹ -* : RTC_TypeDef * RTCx ָҪõRTCȡֵRTC -* : -* ע: +* 函数名称: RTC_IntAlarmDis() +* 功能说明: 闹钟中断禁止 +* 输 入: RTC_TypeDef * RTCx 指定要被设置的RTC，可取值包括RTC +* 输 出: 无 +* 注意事项: 无 ******************************************************************************************************************************************/ void RTC_IntAlarmDis(RTC_TypeDef *RTCx) { @@ -389,11 +395,11 @@ void RTC_IntAlarmDis(RTC_TypeDef *RTCx) } /****************************************************************************************************************************************** -* : RTC_IntAlarmClr() -* ˵: жϱ־ -* : RTC_TypeDef * RTCx ָҪõRTCȡֵRTC -* : -* ע: +* 函数名称: RTC_IntAlarmClr() +* 功能说明: 闹钟中断标志清除 +* 输 入: RTC_TypeDef * RTCx 指定要被设置的RTC，可取值包括RTC +* 输 出: 无 +* 注意事项: 无 ******************************************************************************************************************************************/ void RTC_IntAlarmClr(RTC_TypeDef *RTCx) { @@ -401,11 +407,11 @@ void RTC_IntAlarmClr(RTC_TypeDef *RTCx) } /****************************************************************************************************************************************** -* : RTC_IntAlarmStat() -* ˵: ж״̬ -* : RTC_TypeDef * RTCx ָҪõRTCȡֵRTC -* : uint32_t 1 жϷ 0 жδ -* ע: +* 函数名称: RTC_IntAlarmStat() +* 功能说明: 闹钟中断状态 +* 输 入: RTC_TypeDef * RTCx 指定要被设置的RTC，可取值包括RTC +* 输 出: uint32_t 1 闹钟中断发生 0 闹钟中断未发生 +* 注意事项: 无 ******************************************************************************************************************************************/ uint32_t RTC_IntAlarmStat(RTC_TypeDef *RTCx) { diff --git a/bsp/swm320-lq100/Libraries/SWM320_StdPeriph_Driver/SWM320_rtc.h b/bsp/swm320-lq100/Libraries/SWM320_StdPeriph_Driver/SWM320_rtc.h index 8c5d6f5d63..d534fa4788 100644 --- a/bsp/swm320-lq100/Libraries/SWM320_StdPeriph_Driver/SWM320_rtc.h +++ b/bsp/swm320-lq100/Libraries/SWM320_StdPeriph_Driver/SWM320_rtc.h @@ -1,46 +1,44 @@ #ifndef __SWM320_RTC_H__ #define __SWM320_RTC_H__ - -#define RTC_SUN 0x01 -#define RTC_MON 0x02 -#define RTC_TUE 0x04 -#define RTC_WED 0x08 -#define RTC_THU 0x10 -#define RTC_FRI 0x20 -#define RTC_SAT 0x40 - +#define RTC_SUN 0x01 +#define RTC_MON 0x02 +#define RTC_TUE 0x04 +#define RTC_WED 0x08 +#define RTC_THU 0x10 +#define RTC_FRI 0x20 +#define RTC_SAT 0x40 typedef struct { uint16_t Year; - uint8_t Month; - uint8_t Date; - uint8_t Hour; - uint8_t Minute; - uint8_t Second; - uint8_t SecondIEn; - uint8_t MinuteIEn; + uint8_t Month; //取值1--12 + uint8_t Date; //取值1--31 + uint8_t Hour; //取值0--23 + uint8_t Minute; //取值0--59 + uint8_t Second; //取值0--59 + uint8_t SecondIEn; + uint8_t MinuteIEn; } RTC_InitStructure; typedef struct { - uint8_t Days; //RTC_SUNRTC_MONRTC_TUERTC_WEDRTC_THURTC_FRIRTC_SAT - uint8_t Hour; - uint8_t Minute; - uint8_t Second; - uint8_t AlarmIEn; + uint8_t Days; //RTC_SUN、RTC_MON、RTC_TUE、RTC_WED、RTC_THU、RTC_FRI、RTC_SAT及其或运算组合 + uint8_t Hour; + uint8_t Minute; + uint8_t Second; + uint8_t AlarmIEn; } RTC_AlarmStructure; typedef struct { uint16_t Year; - uint8_t Month; - uint8_t Date; - uint8_t Day; //RTC_SUNRTC_MONRTC_TUERTC_WEDRTC_THURTC_FRIRTC_SAT - uint8_t Hour; - uint8_t Minute; - uint8_t Second; + uint8_t Month; + uint8_t Date; + uint8_t Day; //RTC_SUN、RTC_MON、RTC_TUE、RTC_WED、RTC_THU、RTC_FRI、RTC_SAT + uint8_t Hour; + uint8_t Minute; + uint8_t Second; } RTC_DateTime; void RTC_Init(RTC_TypeDef *RTCx, RTC_InitStructure *initStruct); @@ -51,7 +49,6 @@ void RTC_GetDateTime(RTC_TypeDef *RTCx, RTC_DateTime *dateTime); void RTC_AlarmSetup(RTC_TypeDef *RTCx, RTC_AlarmStructure *alarmStruct); - void RTC_IntSecondEn(RTC_TypeDef *RTCx); void RTC_IntSecondDis(RTC_TypeDef *RTCx); void RTC_IntSecondClr(RTC_TypeDef *RTCx); diff --git a/bsp/swm320-lq100/Libraries/SWM320_StdPeriph_Driver/SWM320_sdio.c b/bsp/swm320-lq100/Libraries/SWM320_StdPeriph_Driver/SWM320_sdio.c index 305ab42733..849193110c 100644 --- a/bsp/swm320-lq100/Libraries/SWM320_StdPeriph_Driver/SWM320_sdio.c +++ b/bsp/swm320-lq100/Libraries/SWM320_StdPeriph_Driver/SWM320_sdio.c @@ -1,10 +1,10 @@ /****************************************************************************************************************************************** -* ļ: SWM320_sdio.c -* ˵: SWM320ƬSDIOӿ -* ֧: http://www.synwit.com.cn/e/tool/gbook/?bid=1 -* ע: Ϊͨԡԡԣֻ֧512ֽΪλĶд -* 汾: V1.1.0 20171025 -* ¼: +* 文件名称: SWM320_sdio.c +* 功能说明: SWM320单片机的SDIO接口驱动库 +* 技术支持: http://www.synwit.com.cn/e/tool/gbook/?bid=1 +* 注意事项: 为了通用性、兼容性、易用性，只支持以512字节为单位的读写 +* 版本日期: V1.1.0 2017年10月25日 +* 升级记录: * * ******************************************************************************************************************************************* @@ -21,104 +21,104 @@ #include "SWM320.h" #include "SWM320_sdio.h" - SD_CardInfo SD_cardInfo; /****************************************************************************************************************************************** -* : SDIO_Init() -* ˵: SDIOдSDʼʼɸ4ģʽд512ֽڴС -* : -* : -* ע: +* 函数名称: SDIO_Init() +* 功能说明: SDIO读写SD卡初始化，初始化成高速4线模式、读写以512字节大小进行 +* 输 入: uint32_t freq SDIO_CLK时钟频率 +* 输 出: uint32_t SD_RES_OK 操作成功 SD_RES_ERR 操作失败 SD_RES_TIMEOUT 操作超时 +* 注意事项: 无 ******************************************************************************************************************************************/ -uint32_t SDIO_Init(void) +uint32_t SDIO_Init(uint32_t freq) { + uint32_t res; uint32_t resp, resps[4]; SYS->CLKDIV &= ~SYS_CLKDIV_SDIO_Msk; - if (SystemCoreClock > 80000000) //SDIOʱҪС52MHz - SYS->CLKDIV |= (2 << SYS_CLKDIV_SDIO_Pos); //SDCLK = SYSCLK / 4 + if (SystemCoreClock > 80000000) //SDIO时钟需要小于52MHz + SYS->CLKDIV |= (2 << SYS_CLKDIV_SDIO_Pos); //SDCLK = SYSCLK / 4 else - SYS->CLKDIV |= (1 << SYS_CLKDIV_SDIO_Pos); //SDCLK = SYSCLK / 2 + SYS->CLKDIV |= (1 << SYS_CLKDIV_SDIO_Pos); //SDCLK = SYSCLK / 2 SYS->CLKEN |= (0x01 << SYS_CLKEN_SDIO_Pos); SDIO->CR2 = (1 << SDIO_CR2_RSTALL_Pos); SDIO->CR1 = (1 << SDIO_CR1_CDSRC_Pos) | - (0 << SDIO_CR1_8BIT_Pos) | - (0 << SDIO_CR1_4BIT_Pos) | + (0 << SDIO_CR1_8BIT_Pos) | + (0 << SDIO_CR1_4BIT_Pos) | (1 << SDIO_CR1_PWRON_Pos) | (7 << SDIO_CR1_VOLT_Pos); SDIO->CR2 = (1 << SDIO_CR2_CLKEN_Pos) | (1 << SDIO_CR2_SDCLKEN_Pos) | - (calcSDCLKDiv(SD_CLK_400KHz) << SDIO_CR2_SDCLKDIV_Pos) | - (0xC << SDIO_CR2_TIMEOUT_Pos); - - while ((SDIO->CR2 & SDIO_CR2_CLKRDY_Msk) == 0); - - SDIO->IE = 0xFFFF01FF; - SDIO->IM = 0x00FF00FF; + (calcSDCLKDiv(100000) << SDIO_CR2_SDCLKDIV_Pos) | + (0xC << SDIO_CR2_TIMEOUT_Pos); // 2**25 SDIO_CLK - SDIO_SendCmd(SD_CMD_GO_IDLE_STATE, 0x00, SD_RESP_NO, 0, 0, 0); //CMD0: GO_IDLE_STATE + while ((SDIO->CR2 & SDIO_CR2_CLKRDY_Msk) == 0) + ; + SDIO->IFE = 0xFFFFFFFF; - SDIO_SendCmd(SD_CMD_SEND_IF_COND, 0x1AA, SD_RESP_32b, &resp, 0, 0); //CMD8: SEND_IF_COND, ⹤ѹǷ֧SD 2.0 + SDIO_SendCmd(SD_CMD_GO_IDLE_STATE, 0x00, SD_RESP_NO, 0); //CMD0: GO_IDLE_STATE - if (resp == 0x1AA) SD_cardInfo.CardType = SDIO_STD_CAPACITY_SD_CARD_V2_0; - else SD_cardInfo.CardType = SDIO_STD_CAPACITY_SD_CARD_V1_1; + res = SDIO_SendCmd(SD_CMD_SEND_IF_COND, 0x1AA, SD_RESP_32b, &resp); //CMD8: SEND_IF_COND, 检测工作电压、检测是否支持SD 2.0 + if (res != SD_RES_OK) + return res; + if (resp == 0x1AA) + SD_cardInfo.CardType = SDIO_STD_CAPACITY_SD_CARD_V2_0; + else + SD_cardInfo.CardType = SDIO_STD_CAPACITY_SD_CARD_V1_1; - do //ACMD41: SD_CMD_SD_APP_OP_COND + do //ACMD41: SD_CMD_SD_APP_OP_COND { - SDIO_SendCmd(SD_CMD_APP_CMD, 0x00, SD_RESP_32b, &resp, 0, 0); + res = SDIO_SendCmd(SD_CMD_APP_CMD, 0x00, SD_RESP_32b, &resp); + if (res != SD_RES_OK) + return res; - if (resp != 0x120) return SD_RES_ERR; //SDMMC + if (resp != 0x120) + return SD_RES_ERR; //不是SD卡，可能是MMC卡 if (SD_cardInfo.CardType == SDIO_STD_CAPACITY_SD_CARD_V2_0) - SDIO_SendCmd(SD_CMD_SD_APP_OP_COND, 0x80100000 | 0x40000000, SD_RESP_32b, &resp, 0, 0); + SDIO_SendCmd(SD_CMD_SD_APP_OP_COND, 0x80100000 | 0x40000000, SD_RESP_32b, &resp); else - SDIO_SendCmd(SD_CMD_SD_APP_OP_COND, 0x80100000 | 0x00000000, SD_RESP_32b, &resp, 0, 0); - } - while (((resp >> 31) & 0x01) == 0); //ϵûʱresp[31] == 0 - - if (((resp >> 30) & 0x01) == 1) SD_cardInfo.CardType = SDIO_HIGH_CAPACITY_SD_CARD; + SDIO_SendCmd(SD_CMD_SD_APP_OP_COND, 0x80100000 | 0x00000000, SD_RESP_32b, &resp); + } while (((resp >> 31) & 0x01) == 0); //上电没完成时resp[31] == 0 + if (((resp >> 30) & 0x01) == 1) + SD_cardInfo.CardType = SDIO_HIGH_CAPACITY_SD_CARD; - SDIO_SendCmd(SD_CMD_ALL_SEND_CID, 0x00, SD_RESP_128b, resps, 0, 0); //CMD2: SD_CMD_ALL_SEND_CIDȡCID + SDIO_SendCmd(SD_CMD_ALL_SEND_CID, 0x00, SD_RESP_128b, resps); //CMD2: SD_CMD_ALL_SEND_CID，获取CID parseCID(resps); - - SDIO_SendCmd(SD_CMD_SET_REL_ADDR, 0x00, SD_RESP_32b, &resp, 0, 0); //CMD3: SD_CMD_SET_REL_ADDRRCA + SDIO_SendCmd(SD_CMD_SET_REL_ADDR, 0x00, SD_RESP_32b, &resp); //CMD3: SD_CMD_SET_REL_ADDR，设置RCA SD_cardInfo.RCA = resp >> 16; - - SDIO_SendCmd(SD_CMD_SEND_CSD, SD_cardInfo.RCA << 16, SD_RESP_128b, resps, 0, 0); //CMD9: SD_CMD_SEND_CSDȡCSD + SDIO_SendCmd(SD_CMD_SEND_CSD, SD_cardInfo.RCA << 16, SD_RESP_128b, resps); //CMD9: SD_CMD_SEND_CSD，获取CSD parseCSD(resps); - if (SD_cardInfo.CardBlockSize < 0x200) return SD_RES_ERR; //ֻ֧512ֽΪλĶддλ벻С512 - + if (SD_cardInfo.CardBlockSize < 0x200) + return SD_RES_ERR; //本驱动只支持以512字节为单位的读写，所以最大读写单位必须不小于512 SDIO->CR2 &= ~(SDIO_CR2_SDCLKEN_Msk | SDIO_CR2_SDCLKDIV_Msk); SDIO->CR2 |= (1 << SDIO_CR2_SDCLKEN_Pos) | - (calcSDCLKDiv(SD_CLK_20MHz) << SDIO_CR2_SDCLKDIV_Pos); //ʼɣSDCLKл - - - SDIO_SendCmd(SD_CMD_SEL_DESEL_CARD, SD_cardInfo.RCA << 16, SD_RESP_32b_busy, &resp, 0, 0); //CMD7: ѡпStandyģʽTransferģʽ + (calcSDCLKDiv(freq) << SDIO_CR2_SDCLKDIV_Pos); //初始化完成，SDCLK切换到高速 + SDIO_SendCmd(SD_CMD_SEL_DESEL_CARD, SD_cardInfo.RCA << 16, SD_RESP_32b_busy, &resp); //CMD7: 选中卡，从Standy模式进入Transfer模式 + SDIO->IF = SDIO_IF_TRXDONE_Msk; - SDIO_SendCmd(SD_CMD_APP_CMD, SD_cardInfo.RCA << 16, SD_RESP_32b, &resp, 0, 0); + SDIO_SendCmd(SD_CMD_APP_CMD, SD_cardInfo.RCA << 16, SD_RESP_32b, &resp); - SDIO_SendCmd(SD_CMD_APP_SD_SET_BUSWIDTH, SD_BUSWIDTH_4b, SD_RESP_32b, &resp, 0, 0); //л4λģʽ + SDIO_SendCmd(SD_CMD_APP_SD_SET_BUSWIDTH, SD_BUSWIDTH_4b, SD_RESP_32b, &resp); //切换成4位总线模式 SDIO->CR1 |= (1 << SDIO_CR1_4BIT_Pos); - - SDIO_SendCmd(SD_CMD_SET_BLOCKLEN, 512, SD_RESP_32b, &resp, 0, 0); //̶Сλ512ֽ + SDIO_SendCmd(SD_CMD_SET_BLOCKLEN, 512, SD_RESP_32b, &resp); //固定块大小位512字节 SDIO->BLK = 512; @@ -126,84 +126,268 @@ uint32_t SDIO_Init(void) } /****************************************************************************************************************************************** -* : SDIO_BlockWrite() -* ˵: SDд -* : uint32_t block_addr SDַÿ512ֽ -* uint32_t buff[] Ҫд -* : -* ע: +* 函数名称: SDIO_BlockWrite() +* 功能说明: 向SD卡写入数据 +* 输 入: uint32_t block_addr SD卡块地址，每块512字节 +* uint32_t buff[] 要写入的数据 +* 输 出: uint32_t SD_RES_OK 操作成功 SD_RES_ERR 操作失败 SD_RES_TIMEOUT 操作超时 +* 注意事项: 无 ******************************************************************************************************************************************/ -void SDIO_BlockWrite(uint32_t block_addr, uint32_t buff[]) +uint32_t SDIO_BlockWrite(uint32_t block_addr, uint32_t buff[]) { - uint32_t i, resp, addr; + uint32_t res, i; + uint32_t addr, resp; - if (SD_cardInfo.CardType == SDIO_HIGH_CAPACITY_SD_CARD) addr = block_addr; - else addr = block_addr * 512; + if (SD_cardInfo.CardType == SDIO_HIGH_CAPACITY_SD_CARD) + addr = block_addr; + else + addr = block_addr * 512; - SDIO_SendCmd(SD_CMD_WRITE_SINGLE_BLOCK, addr, SD_RESP_32b, &resp, 1, 0); + res = SDIO_SendCmdWithData(SD_CMD_WRITE_SINGLE_BLOCK, addr, SD_RESP_32b, &resp, 0, 1); + if (res != SD_RES_OK) + return res; - while ((SDIO->IF & SDIO_IF_BUFWRRDY_Msk) == 0); + while ((SDIO->IF & SDIO_IF_BUFWRRDY_Msk) == 0) + __NOP(); SDIO->IF = SDIO_IF_BUFWRRDY_Msk; - for (i = 0; i < 512 / 4; i++) SDIO->DATA = buff[i]; + for (i = 0; i < 512 / 4; i++) + SDIO->DATA = buff[i]; + + while ((SDIO->IF & SDIO_IF_TRXDONE_Msk) == 0) + __NOP(); + SDIO->IF = SDIO_IF_TRXDONE_Msk; + + return SD_RES_OK; +} + +/****************************************************************************************************************************************** +* 函数名称: SDIO_MultiBlockWrite() +* 功能说明: 向SD卡写入多块数据 +* 输 入: uint32_t block_addr SD卡块地址，每块512字节 +* uint16_t block_cnt 要写入的块数 +* uint32_t buff[] 要写入的数据 +* 输 出: uint32_t SD_RES_OK 操作成功 SD_RES_ERR 操作失败 SD_RES_TIMEOUT 操作超时 +* 注意事项: 无 +******************************************************************************************************************************************/ +uint32_t SDIO_MultiBlockWrite(uint32_t block_addr, uint16_t block_cnt, uint32_t buff[]) +{ + uint32_t res, i, j; + uint32_t addr, resp; + + if (SD_cardInfo.CardType == SDIO_HIGH_CAPACITY_SD_CARD) + addr = block_addr; + else + addr = block_addr * 512; + + res = SDIO_SendCmdWithData(SD_CMD_WRITE_MULT_BLOCK, addr, SD_RESP_32b, &resp, 0, block_cnt); + if (res != SD_RES_OK) + return res; + + for (i = 0; i < block_cnt; i++) + { + while ((SDIO->IF & SDIO_IF_BUFWRRDY_Msk) == 0) + __NOP(); + SDIO->IF = SDIO_IF_BUFWRRDY_Msk; - SDIO->IF = SDIO_IF_TRXDONE_Msk; //?? - while ((SDIO->IF & SDIO_IF_TRXDONE_Msk) == 0); + for (j = 0; j < 512 / 4; j++) + SDIO->DATA = buff[i * (512 / 4) + j]; + } + + while ((SDIO->IF & SDIO_IF_TRXDONE_Msk) == 0) + __NOP(); SDIO->IF = SDIO_IF_TRXDONE_Msk; + + return SD_RES_OK; } /****************************************************************************************************************************************** -* : SDIO_BlockRead() -* ˵: SD -* : uint32_t block_addr SDַÿ512ֽ -* uint32_t buff[] -* : -* ע: +* 函数名称: SDIO_DMABlockWrite() +* 功能说明: 通过DMA向SD卡写入多块数据 +* 输 入: uint32_t block_addr SD卡块地址，每块512字节 +* uint16_t block_cnt 要写入的块数 +* uint32_t buff[] 要写入的数据 +* 输 出: uint32_t SD_RES_OK 操作成功 SD_RES_ERR 操作失败 SD_RES_TIMEOUT 操作超时 +* 注意事项: 无 ******************************************************************************************************************************************/ -void SDIO_BlockRead(uint32_t block_addr, uint32_t buff[]) +uint32_t SDIO_DMABlockWrite(uint32_t block_addr, uint16_t block_cnt, uint32_t buff[]) { - uint32_t i, resp, addr; + uint32_t res; + uint32_t addr, resp; + + if (SD_cardInfo.CardType == SDIO_HIGH_CAPACITY_SD_CARD) + addr = block_addr; + else + addr = block_addr * 512; + + SDIO->DMA_MEM_ADDR = (uint32_t)buff; + + res = SDIO_SendCmdWithDataByDMA(SD_CMD_WRITE_MULT_BLOCK, addr, SD_RESP_32b, &resp, 0, block_cnt); + if (res != SD_RES_OK) + return res; - if (SD_cardInfo.CardType == SDIO_HIGH_CAPACITY_SD_CARD) addr = block_addr; - else addr = block_addr * 512; + while ((SDIO->IF & SDIO_IF_TRXDONE_Msk) == 0) + __NOP(); + SDIO->IF = SDIO_IF_TRXDONE_Msk; - SDIO_SendCmd(SD_CMD_READ_SINGLE_BLOCK, addr, SD_RESP_32b, &resp, 1, 1); + return SD_RES_OK; +} - while ((SDIO->IF & SDIO_IF_BUFRDRDY_Msk) == 0); +/****************************************************************************************************************************************** +* 函数名称: SDIO_BlockRead() +* 功能说明: 从SD卡读出数据 +* 输 入: uint32_t block_addr SD卡块地址，每块512字节 +* uint32_t buff[] 读出的数据 +* 输 出: uint32_t SD_RES_OK 操作成功 SD_RES_ERR 操作失败 SD_RES_TIMEOUT 操作超时 +* 注意事项: 无 +******************************************************************************************************************************************/ +uint32_t SDIO_BlockRead(uint32_t block_addr, uint32_t buff[]) +{ + uint32_t res, i; + uint32_t addr, resp; + + if (SD_cardInfo.CardType == SDIO_HIGH_CAPACITY_SD_CARD) + addr = block_addr; + else + addr = block_addr * 512; + + res = SDIO_SendCmdWithData(SD_CMD_READ_SINGLE_BLOCK, addr, SD_RESP_32b, &resp, 1, 1); + if (res != SD_RES_OK) + return res; + + while ((SDIO->IF & SDIO_IF_BUFRDRDY_Msk) == 0) + __NOP(); SDIO->IF = SDIO_IF_BUFRDRDY_Msk; - for (i = 0; i < 512 / 4; i++) buff[i] = SDIO->DATA; + for (i = 0; i < 512 / 4; i++) + buff[i] = SDIO->DATA; + + while ((SDIO->IF & SDIO_IF_TRXDONE_Msk) == 0) + __NOP(); + SDIO->IF = SDIO_IF_TRXDONE_Msk; + + return SD_RES_OK; +} + +/****************************************************************************************************************************************** +* 函数名称: SDIO_MultiBlockRead() +* 功能说明: 从SD卡读出多块数据 +* 输 入: uint32_t block_addr SD卡块地址，每块512字节 +* uint16_t block_cnt 要读出的块数 +* uint32_t buff[] 读出的数据 +* 输 出: uint32_t SD_RES_OK 操作成功 SD_RES_ERR 操作失败 SD_RES_TIMEOUT 操作超时 +* 注意事项: 无 +******************************************************************************************************************************************/ +uint32_t SDIO_MultiBlockRead(uint32_t block_addr, uint16_t block_cnt, uint32_t buff[]) +{ + uint32_t res, i, j; + uint32_t addr, resp; + + if (SD_cardInfo.CardType == SDIO_HIGH_CAPACITY_SD_CARD) + addr = block_addr; + else + addr = block_addr * 512; + + res = SDIO_SendCmdWithData(SD_CMD_READ_MULT_BLOCK, addr, SD_RESP_32b, &resp, 1, block_cnt); + if (res != SD_RES_OK) + return res; - while ((SDIO->IF & SDIO_IF_TRXDONE_Msk) == 0); + for (i = 0; i < block_cnt; i++) + { + while ((SDIO->IF & SDIO_IF_BUFRDRDY_Msk) == 0) + __NOP(); + SDIO->IF = SDIO_IF_BUFRDRDY_Msk; + + for (j = 0; j < 512 / 4; j++) + buff[i * (512 / 4) + j] = SDIO->DATA; + } + + while ((SDIO->IF & SDIO_IF_TRXDONE_Msk) == 0) + __NOP(); SDIO->IF = SDIO_IF_TRXDONE_Msk; + + return SD_RES_OK; } /****************************************************************************************************************************************** -* : SDIO_SendCmd() -* ˵: SDIOSD -* : uint32_t cmd -* uint32_t arg -* uint32_t resp_type ӦͣȡֵSD_RESP_NOSD_RESP_32bSD_RESP_128bSD_RESP_32b_busy -* uint32_t *resp_data Ӧ -* uint32_t have_data Ƿݴ -* uint32_t data_read 1 SD 0 дSD -* : -* ע: +* 函数名称: SDIO_DMABlockRead() +* 功能说明: 通过DMA从SD卡读出多块数据 +* 输 入: uint32_t block_addr SD卡块地址，每块512字节 +* uint16_t block_cnt 要读出的块数 +* uint32_t buff[] 读出的数据 +* 输 出: uint32_t SD_RES_OK 操作成功 SD_RES_ERR 操作失败 SD_RES_TIMEOUT 操作超时 +* 注意事项: 无 ******************************************************************************************************************************************/ -void SDIO_SendCmd(uint32_t cmd, uint32_t arg, uint32_t resp_type, uint32_t *resp_data, uint32_t have_data, uint32_t data_read) +uint32_t SDIO_DMABlockRead(uint32_t block_addr, uint16_t block_cnt, uint32_t buff[]) { + uint32_t res; + uint32_t addr, resp; + + if (SD_cardInfo.CardType == SDIO_HIGH_CAPACITY_SD_CARD) + addr = block_addr; + else + addr = block_addr * 512; + + SDIO->DMA_MEM_ADDR = (uint32_t)buff; + + res = SDIO_SendCmdWithDataByDMA(SD_CMD_READ_MULT_BLOCK, addr, SD_RESP_32b, &resp, 1, block_cnt); + if (res != SD_RES_OK) + return res; + + while ((SDIO->IF & SDIO_IF_TRXDONE_Msk) == 0) + __NOP(); + SDIO->IF = SDIO_IF_TRXDONE_Msk; + + return SD_RES_OK; +} + +/****************************************************************************************************************************************** +* 函数名称: _SDIO_SendCmd() +* 功能说明: SDIO向SD卡发送命令 +* 输 入: uint32_t cmd 命令索引 +* uint32_t arg 命令参数 +* uint32_t resp_type 响应类型，取值SD_RESP_NO、SD_RESP_32b、SD_RESP_128b、SD_RESP_32b_busy +* uint32_t *resp_data 响应内容 +* uint32_t have_data 是否有数据传输 +* uint32_t data_read 1 读SD卡 0 写SD卡 +* uint16_t block_cnt 读写块个数 +* uint32_t use_dma 1 使用DMA搬运数据 +* 输 出: uint32_t SD_RES_OK 操作成功 SD_RES_ERR 操作失败 SD_RES_TIMEOUT 操作超时 +* 注意事项: 无 +******************************************************************************************************************************************/ +uint32_t _SDIO_SendCmd(uint32_t cmd, uint32_t arg, uint32_t resp_type, uint32_t *resp_data, uint32_t have_data, uint32_t data_read, uint16_t block_cnt, uint32_t use_dma) +{ + SDIO->BLK &= ~SDIO_BLK_COUNT_Msk; + SDIO->BLK |= (block_cnt << SDIO_BLK_COUNT_Pos); + SDIO->ARG = arg; SDIO->CMD = (cmd << SDIO_CMD_CMDINDX_Pos) | - (0 << SDIO_CMD_CMDTYPE_Pos) | - (have_data << SDIO_CMD_HAVEDATA_Pos) | - (0 << SDIO_CMD_IDXCHECK_Pos) | - (0 << SDIO_CMD_CRCCHECK_Pos) | + (0 << SDIO_CMD_CMDTYPE_Pos) | + (0 << SDIO_CMD_IDXCHECK_Pos) | + (0 << SDIO_CMD_CRCCHECK_Pos) | (resp_type << SDIO_CMD_RESPTYPE_Pos) | - (0 << SDIO_CMD_MULTBLK_Pos) | - (data_read << SDIO_CMD_DIRREAD_Pos) | - (0 << SDIO_CMD_BLKCNTEN_Pos); + (have_data << SDIO_CMD_HAVEDATA_Pos) | + (data_read << SDIO_CMD_DIRREAD_Pos) | + ((block_cnt > 1) << SDIO_CMD_MULTBLK_Pos) | + ((block_cnt > 1) << SDIO_CMD_BLKCNTEN_Pos) | + ((block_cnt > 1) << SDIO_CMD_AUTOCMD12_Pos) | + (use_dma << SDIO_CMD_DMAEN_Pos); - while ((SDIO->IF & SDIO_IF_CMDDONE_Msk) == 0); + while ((SDIO->IF & SDIO_IF_CMDDONE_Msk) == 0) + { + if (SDIO->IF & SDIO_IF_CMDTIMEOUT_Msk) + { + SDIO->IF = SDIO_IF_CMDTIMEOUT_Msk; + + return SD_RES_TIMEOUT; + } + else if (SDIO->IF & SDIO_IF_ERROR_Msk) + { + SDIO->IF = 0xFFFFFFFF; + + return SD_RES_ERR; + } + } SDIO->IF = SDIO_IF_CMDDONE_Msk; if (resp_type == SD_RESP_32b) @@ -212,15 +396,16 @@ void SDIO_SendCmd(uint32_t cmd, uint32_t arg, uint32_t resp_type, uint32_t *resp } else if (resp_type == SD_RESP_128b) { - //ĴнCID/CSD[127-8]δRESP3-0[119-0]λCRC - //ʱ˳򣬽CID/CSD[127-8]resp_data0-3[127-8]8λ0x00 + //寄存器中将CID/CSD[127-8]依次存放在了RESP3-0[119-0]，最低位的CRC被丢掉 + //读出数据时调整了顺序，将CID/CSD[127-8]存放在resp_data0-3[127-8]，最低8位填充0x00 resp_data[0] = (SDIO->RESP[3] << 8) + ((SDIO->RESP[2] >> 24) & 0xFF); resp_data[1] = (SDIO->RESP[2] << 8) + ((SDIO->RESP[1] >> 24) & 0xFF); resp_data[2] = (SDIO->RESP[1] << 8) + ((SDIO->RESP[0] >> 24) & 0xFF); resp_data[3] = (SDIO->RESP[0] << 8) + 0x00; } -} + return SD_RES_OK; +} void parseCID(uint32_t CID_Tab[4]) { @@ -328,7 +513,7 @@ void parseCSD(uint32_t CSD_Tab[4]) SD_cardInfo.SD_csd.Reserved2 = 0; /*!< Reserved */ if ((SD_cardInfo.CardType == SDIO_STD_CAPACITY_SD_CARD_V1_1) || - (SD_cardInfo.CardType == SDIO_STD_CAPACITY_SD_CARD_V2_0)) + (SD_cardInfo.CardType == SDIO_STD_CAPACITY_SD_CARD_V2_0)) { SD_cardInfo.SD_csd.DeviceSize = (tmp & 0x03) << 10; @@ -352,7 +537,7 @@ void parseCSD(uint32_t CSD_Tab[4]) tmp = (uint8_t)((CSD_Tab[2] & 0x0000FF00) >> 8); SD_cardInfo.SD_csd.DeviceSizeMul |= (tmp & 0x80) >> 7; - SD_cardInfo.CardCapacity = (SD_cardInfo.SD_csd.DeviceSize + 1) ; + SD_cardInfo.CardCapacity = (SD_cardInfo.SD_csd.DeviceSize + 1); SD_cardInfo.CardCapacity *= (1 << (SD_cardInfo.SD_csd.DeviceSizeMul + 2)); SD_cardInfo.CardBlockSize = 1 << (SD_cardInfo.SD_csd.RdBlockLen); SD_cardInfo.CardCapacity *= SD_cardInfo.CardBlockSize; @@ -376,7 +561,7 @@ void parseCSD(uint32_t CSD_Tab[4]) /*!< Byte 10 */ tmp = (uint8_t)((CSD_Tab[2] & 0x0000FF00) >> 8); - SD_cardInfo.CardCapacity = (SD_cardInfo.SD_csd.DeviceSize + 1) * 512 * 1024; + SD_cardInfo.CardCapacity = (uint64_t)(SD_cardInfo.SD_csd.DeviceSize + 1) * 512 * 1024; SD_cardInfo.CardBlockSize = 512; } @@ -412,25 +597,30 @@ void parseCSD(uint32_t CSD_Tab[4]) SD_cardInfo.SD_csd.ECC = (tmp & 0x03); } -uint32_t calcSDCLKDiv(uint32_t freq_sel) +uint32_t calcSDCLKDiv(uint32_t freq) { + uint32_t prediv = ((SYS->CLKDIV & SYS_CLKDIV_SDIO_Msk) >> SYS_CLKDIV_SDIO_Pos); + uint32_t clkdiv = (SystemCoreClock / (1 << prediv)) / freq; uint32_t regdiv = 0; - uint32_t clkdiv = 0; - - if (((SYS->CLKDIV & SYS_CLKDIV_SDIO_Msk) >> SYS_CLKDIV_SDIO_Pos) == 1) - clkdiv = SystemCoreClock / 2 / ((freq_sel == SD_CLK_400KHz) ? 300000 : 15000000); - else if (((SYS->CLKDIV & SYS_CLKDIV_SDIO_Msk) >> SYS_CLKDIV_SDIO_Pos) == 2) - clkdiv = SystemCoreClock / 4 / ((freq_sel == SD_CLK_400KHz) ? 300000 : 15000000); - - if (clkdiv > 128) regdiv = 0x80; - else if (clkdiv > 64) regdiv = 0x40; - else if (clkdiv > 32) regdiv = 0x20; - else if (clkdiv > 16) regdiv = 0x10; - else if (clkdiv > 8) regdiv = 0x08; - else if (clkdiv > 4) regdiv = 0x04; - else if (clkdiv > 2) regdiv = 0x02; - else if (clkdiv > 1) regdiv = 0x01; - else regdiv = 0x00; + + if (clkdiv > 128) + regdiv = 0x80; + else if (clkdiv > 64) + regdiv = 0x40; + else if (clkdiv > 32) + regdiv = 0x20; + else if (clkdiv > 16) + regdiv = 0x10; + else if (clkdiv > 8) + regdiv = 0x08; + else if (clkdiv > 4) + regdiv = 0x04; + else if (clkdiv > 2) + regdiv = 0x02; + else if (clkdiv > 1) + regdiv = 0x01; + else + regdiv = 0x00; return regdiv; } diff --git a/bsp/swm320-lq100/Libraries/SWM320_StdPeriph_Driver/SWM320_sdio.h b/bsp/swm320-lq100/Libraries/SWM320_StdPeriph_Driver/SWM320_sdio.h index 1df6602159..d9834291ac 100644 --- a/bsp/swm320-lq100/Libraries/SWM320_StdPeriph_Driver/SWM320_sdio.h +++ b/bsp/swm320-lq100/Libraries/SWM320_StdPeriph_Driver/SWM320_sdio.h @@ -1,116 +1,109 @@ #ifndef __SWM320_SDIO_H__ #define __SWM320_SDIO_H__ - -#define SD_CMD_GO_IDLE_STATE ((uint8_t)0) -#define SD_CMD_SEND_OP_COND ((uint8_t)1) -#define SD_CMD_ALL_SEND_CID ((uint8_t)2) -#define SD_CMD_SET_REL_ADDR ((uint8_t)3) -#define SD_CMD_SET_DSR ((uint8_t)4) -#define SD_CMD_HS_SWITCH ((uint8_t)6) -#define SD_CMD_SEL_DESEL_CARD ((uint8_t)7) -#define SD_CMD_SEND_IF_COND ((uint8_t)8) -#define SD_CMD_SEND_CSD ((uint8_t)9) -#define SD_CMD_SEND_CID ((uint8_t)10) -#define SD_CMD_STOP_TRANSMISSION ((uint8_t)12) -#define SD_CMD_SEND_STATUS ((uint8_t)13) -#define SD_CMD_SET_BLOCKLEN ((uint8_t)16) -#define SD_CMD_READ_SINGLE_BLOCK ((uint8_t)17) -#define SD_CMD_READ_MULT_BLOCK ((uint8_t)18) -#define SD_CMD_WRITE_SINGLE_BLOCK ((uint8_t)24) -#define SD_CMD_WRITE_MULT_BLOCK ((uint8_t)25) -#define SD_CMD_PROG_CID ((uint8_t)26) -#define SD_CMD_PROG_CSD ((uint8_t)27) -#define SD_CMD_APP_CMD ((uint8_t)55) +#define SD_CMD_GO_IDLE_STATE ((uint8_t)0) +#define SD_CMD_SEND_OP_COND ((uint8_t)1) +#define SD_CMD_ALL_SEND_CID ((uint8_t)2) +#define SD_CMD_SET_REL_ADDR ((uint8_t)3) +#define SD_CMD_SET_DSR ((uint8_t)4) +#define SD_CMD_HS_SWITCH ((uint8_t)6) +#define SD_CMD_SEL_DESEL_CARD ((uint8_t)7) +#define SD_CMD_SEND_IF_COND ((uint8_t)8) +#define SD_CMD_SEND_CSD ((uint8_t)9) +#define SD_CMD_SEND_CID ((uint8_t)10) +#define SD_CMD_STOP_TRANSMISSION ((uint8_t)12) +#define SD_CMD_SEND_STATUS ((uint8_t)13) +#define SD_CMD_SET_BLOCKLEN ((uint8_t)16) +#define SD_CMD_READ_SINGLE_BLOCK ((uint8_t)17) +#define SD_CMD_READ_MULT_BLOCK ((uint8_t)18) +#define SD_CMD_WRITE_SINGLE_BLOCK ((uint8_t)24) +#define SD_CMD_WRITE_MULT_BLOCK ((uint8_t)25) +#define SD_CMD_PROG_CID ((uint8_t)26) +#define SD_CMD_PROG_CSD ((uint8_t)27) +#define SD_CMD_APP_CMD ((uint8_t)55) /*Following commands are SD Card Specific commands. SDIO_APP_CMD should be sent before sending these commands. */ -#define SD_CMD_APP_SD_SET_BUSWIDTH ((uint8_t)6) -#define SD_CMD_SD_APP_STAUS ((uint8_t)13) -#define SD_CMD_SD_APP_SEND_NUM_WRITE_BLOCKS ((uint8_t)22) -#define SD_CMD_SD_APP_OP_COND ((uint8_t)41) -#define SD_CMD_SD_APP_SET_CLR_CARD_DETECT ((uint8_t)42) -#define SD_CMD_SD_APP_SEND_SCR ((uint8_t)51) -#define SD_CMD_SDIO_RW_DIRECT ((uint8_t)52) -#define SD_CMD_SDIO_RW_EXTENDED ((uint8_t)53) - - -#define SD_RESP_NO 0 //0 Ӧ -#define SD_RESP_32b 2 //2 32λӦ -#define SD_RESP_128b 1 //1 128λӦ -#define SD_RESP_32b_busy 3 //3 32λӦcheck Busy after response - -#define SD_CLK_400KHz 0 -#define SD_CLK_20MHz 1 - -#define SD_BUSWIDTH_1b 0 -#define SD_BUSWIDTH_4b 2 - -#define SD_RES_OK 0 -#define SD_RES_ERR 1 - +#define SD_CMD_APP_SD_SET_BUSWIDTH ((uint8_t)6) +#define SD_CMD_SD_APP_STAUS ((uint8_t)13) +#define SD_CMD_SD_APP_SEND_NUM_WRITE_BLOCKS ((uint8_t)22) +#define SD_CMD_SD_APP_OP_COND ((uint8_t)41) +#define SD_CMD_SD_APP_SET_CLR_CARD_DETECT ((uint8_t)42) +#define SD_CMD_SD_APP_SEND_SCR ((uint8_t)51) +#define SD_CMD_SDIO_RW_DIRECT ((uint8_t)52) +#define SD_CMD_SDIO_RW_EXTENDED ((uint8_t)53) + +#define SD_RESP_NO 0 //0 无响应 +#define SD_RESP_32b 2 //2 32位响应 +#define SD_RESP_128b 1 //1 128位响应 +#define SD_RESP_32b_busy 3 //3 32位响应，check Busy after response + +#define SD_BUSWIDTH_1b 0 +#define SD_BUSWIDTH_4b 2 + +#define SD_RES_OK 0 +#define SD_RES_ERR 1 +#define SD_RES_TIMEOUT 2 typedef struct { - __IO uint8_t CSDStruct; // CSD structure - __IO uint8_t SysSpecVersion; // System specification version - __IO uint8_t Reserved1; // Reserved - __IO uint8_t TAAC; // Data read access-time 1 - __IO uint8_t NSAC; // Data read access-time 2 in CLK cycles - __IO uint8_t MaxBusClkFrec; // Max. bus clock frequency - __IO uint16_t CardComdClasses; //< Card command classes - __IO uint8_t RdBlockLen; // Max. read data block length - __IO uint8_t PartBlockRead; // Partial blocks for read allowed - __IO uint8_t WrBlockMisalign; // Write block misalignment - __IO uint8_t RdBlockMisalign; // Read block misalignment - __IO uint8_t DSRImpl; // DSR implemented - __IO uint8_t Reserved2; // Reserved - __IO uint32_t DeviceSize; // Device Size - __IO uint8_t MaxRdCurrentVDDMin; // Max. read current @ VDD min - __IO uint8_t MaxRdCurrentVDDMax; // Max. read current @ VDD max - __IO uint8_t MaxWrCurrentVDDMin; // Max. write current @ VDD min - __IO uint8_t MaxWrCurrentVDDMax; // Max. write current @ VDD max - __IO uint8_t DeviceSizeMul; // Device size multiplier - __IO uint8_t EraseGrSize; // Erase group size - __IO uint8_t EraseGrMul; // Erase group size multiplier - __IO uint8_t WrProtectGrSize; // Write protect group size - __IO uint8_t WrProtectGrEnable; // Write protect group enable - __IO uint8_t ManDeflECC; // Manufacturer default ECC - __IO uint8_t WrSpeedFact; // Write speed factor - __IO uint8_t MaxWrBlockLen; // Max. write data block length - __IO uint8_t WriteBlockPaPartial; // Partial blocks for write allowed - __IO uint8_t Reserved3; // Reserded - __IO uint8_t ContentProtectAppli; // Content protection application - __IO uint8_t FileFormatGrouop; // File format group - __IO uint8_t CopyFlag; // Copy flag (OTP) - __IO uint8_t PermWrProtect; // Permanent write protection - __IO uint8_t TempWrProtect; // Temporary write protection - __IO uint8_t FileFormat; // File Format - __IO uint8_t ECC; // ECC code + __IO uint8_t CSDStruct; // CSD structure + __IO uint8_t SysSpecVersion; // System specification version + __IO uint8_t Reserved1; // Reserved + __IO uint8_t TAAC; // Data read access-time 1 + __IO uint8_t NSAC; // Data read access-time 2 in CLK cycles + __IO uint8_t MaxBusClkFrec; // Max. bus clock frequency + __IO uint16_t CardComdClasses; //< Card command classes + __IO uint8_t RdBlockLen; // Max. read data block length + __IO uint8_t PartBlockRead; // Partial blocks for read allowed + __IO uint8_t WrBlockMisalign; // Write block misalignment + __IO uint8_t RdBlockMisalign; // Read block misalignment + __IO uint8_t DSRImpl; // DSR implemented + __IO uint8_t Reserved2; // Reserved + __IO uint32_t DeviceSize; // Device Size + __IO uint8_t MaxRdCurrentVDDMin; // Max. read current @ VDD min + __IO uint8_t MaxRdCurrentVDDMax; // Max. read current @ VDD max + __IO uint8_t MaxWrCurrentVDDMin; // Max. write current @ VDD min + __IO uint8_t MaxWrCurrentVDDMax; // Max. write current @ VDD max + __IO uint8_t DeviceSizeMul; // Device size multiplier + __IO uint8_t EraseGrSize; // Erase group size + __IO uint8_t EraseGrMul; // Erase group size multiplier + __IO uint8_t WrProtectGrSize; // Write protect group size + __IO uint8_t WrProtectGrEnable; // Write protect group enable + __IO uint8_t ManDeflECC; // Manufacturer default ECC + __IO uint8_t WrSpeedFact; // Write speed factor + __IO uint8_t MaxWrBlockLen; // Max. write data block length + __IO uint8_t WriteBlockPaPartial; // Partial blocks for write allowed + __IO uint8_t Reserved3; // Reserded + __IO uint8_t ContentProtectAppli; // Content protection application + __IO uint8_t FileFormatGrouop; // File format group + __IO uint8_t CopyFlag; // Copy flag (OTP) + __IO uint8_t PermWrProtect; // Permanent write protection + __IO uint8_t TempWrProtect; // Temporary write protection + __IO uint8_t FileFormat; // File Format + __IO uint8_t ECC; // ECC code } SD_CSD; typedef struct { - __IO uint8_t ManufacturerID; // ManufacturerID - __IO uint16_t OEM_AppliID; // OEM/Application ID - __IO uint32_t ProdName1; // Product Name part1 - __IO uint8_t ProdName2; // Product Name part2 - __IO uint8_t ProdRev; // Product Revision - __IO uint32_t ProdSN; // Product Serial Number - __IO uint8_t Reserved1; // Reserved1 - __IO uint16_t ManufactDate; // Manufacturing Date + __IO uint8_t ManufacturerID; // ManufacturerID + __IO uint16_t OEM_AppliID; // OEM/Application ID + __IO uint32_t ProdName1; // Product Name part1 + __IO uint8_t ProdName2; // Product Name part2 + __IO uint8_t ProdRev; // Product Revision + __IO uint32_t ProdSN; // Product Serial Number + __IO uint8_t Reserved1; // Reserved1 + __IO uint16_t ManufactDate; // Manufacturing Date } SD_CID; - -#define SDIO_STD_CAPACITY_SD_CARD_V1_1 ((uint32_t)0x00000000) -#define SDIO_STD_CAPACITY_SD_CARD_V2_0 ((uint32_t)0x00000001) -#define SDIO_HIGH_CAPACITY_SD_CARD ((uint32_t)0x00000002) -#define SDIO_MULTIMEDIA_CARD ((uint32_t)0x00000003) -#define SDIO_SECURE_DIGITAL_IO_CARD ((uint32_t)0x00000004) -#define SDIO_HIGH_SPEED_MULTIMEDIA_CARD ((uint32_t)0x00000005) -#define SDIO_SECURE_DIGITAL_IO_COMBO_CARD ((uint32_t)0x00000006) -#define SDIO_HIGH_CAPACITY_MMC_CARD ((uint32_t)0x00000007) - +#define SDIO_STD_CAPACITY_SD_CARD_V1_1 ((uint32_t)0x00000000) +#define SDIO_STD_CAPACITY_SD_CARD_V2_0 ((uint32_t)0x00000001) +#define SDIO_HIGH_CAPACITY_SD_CARD ((uint32_t)0x00000002) +#define SDIO_MULTIMEDIA_CARD ((uint32_t)0x00000003) +#define SDIO_SECURE_DIGITAL_IO_CARD ((uint32_t)0x00000004) +#define SDIO_HIGH_SPEED_MULTIMEDIA_CARD ((uint32_t)0x00000005) +#define SDIO_SECURE_DIGITAL_IO_COMBO_CARD ((uint32_t)0x00000006) +#define SDIO_HIGH_CAPACITY_MMC_CARD ((uint32_t)0x00000007) typedef struct { @@ -122,14 +115,23 @@ typedef struct uint8_t CardType; } SD_CardInfo; - extern SD_CardInfo SD_cardInfo; -uint32_t SDIO_Init(void); -void SDIO_BlockWrite(uint32_t block_addr, uint32_t buff[]); -void SDIO_BlockRead(uint32_t block_addr, uint32_t buff[]); +uint32_t SDIO_Init(uint32_t freq); +uint32_t SDIO_BlockWrite(uint32_t block_addr, uint32_t buff[]); +uint32_t SDIO_BlockRead(uint32_t block_addr, uint32_t buff[]); + +uint32_t SDIO_MultiBlockWrite(uint32_t block_addr, uint16_t block_cnt, uint32_t buff[]); +uint32_t SDIO_MultiBlockRead(uint32_t block_addr, uint16_t block_cnt, uint32_t buff[]); + +uint32_t SDIO_DMABlockWrite(uint32_t block_addr, uint16_t block_cnt, uint32_t buff[]); +uint32_t SDIO_DMABlockRead(uint32_t block_addr, uint16_t block_cnt, uint32_t buff[]); + +uint32_t _SDIO_SendCmd(uint32_t cmd, uint32_t arg, uint32_t resp_type, uint32_t *resp_data, uint32_t have_data, uint32_t data_read, uint16_t block_cnt, uint32_t use_dma); -void SDIO_SendCmd(uint32_t cmd, uint32_t arg, uint32_t resp_type, uint32_t *resp_data, uint32_t have_data, uint32_t data_read); +#define SDIO_SendCmd(cmd, arg, resp_type, resp_data) _SDIO_SendCmd(cmd, arg, resp_type, resp_data, 0, 0, 0, 0) +#define SDIO_SendCmdWithData(cmd, arg, resp_type, resp_data, data_read, block_cnt) _SDIO_SendCmd(cmd, arg, resp_type, resp_data, 1, data_read, block_cnt, 0) +#define SDIO_SendCmdWithDataByDMA(cmd, arg, resp_type, resp_data, data_read, block_cnt) _SDIO_SendCmd(cmd, arg, resp_type, resp_data, 1, data_read, block_cnt, 1) void parseCID(uint32_t CID_Tab[4]); void parseCSD(uint32_t CID_Tab[4]); diff --git a/bsp/swm320-lq100/Libraries/SWM320_StdPeriph_Driver/SWM320_sdram.c b/bsp/swm320-lq100/Libraries/SWM320_StdPeriph_Driver/SWM320_sdram.c index f07af4ee51..bc5751f079 100644 --- a/bsp/swm320-lq100/Libraries/SWM320_StdPeriph_Driver/SWM320_sdram.c +++ b/bsp/swm320-lq100/Libraries/SWM320_StdPeriph_Driver/SWM320_sdram.c @@ -1,10 +1,10 @@ /****************************************************************************************************************************************** -* ļ: SWM320_sdram.c -* ˵: SWM320ƬSDRAM -* ֧: http://www.synwit.com.cn/e/tool/gbook/?bid=1 -* ע: -* 汾: V1.1.0 20171025 -* ¼: +* 文件名称: SWM320_sdram.c +* 功能说明: SWM320单片机的SDRAM驱动程序 +* 技术支持: http://www.synwit.com.cn/e/tool/gbook/?bid=1 +* 注意事项: +* 版本日期: V1.1.0 2017年10月25日 +* 升级记录: * * ******************************************************************************************************************************************* @@ -22,37 +22,95 @@ #include "SWM320_sdram.h" /****************************************************************************************************************************************** -* : SDRAM_Init() -* ˵: SDRAMʼ -* : SDRAM_InitStructure * initStruct NOR Flash趨ֵĽṹ -* : -* ע: +* 函数名称: SDRAM_Init() +* 功能说明: SDRAM控制器初始化 +* 输 入: SDRAM_InitStructure * initStruct 包含 SDRAM 控制器相关设定值的结构体 +* 输 出: 无 +* 注意事项: 无 ******************************************************************************************************************************************/ void SDRAM_Init(SDRAM_InitStructure *initStruct) { + uint32_t row_n; + SYS->CLKEN |= (1 << SYS_CLKEN_SDRAM_Pos); SYS->CLKDIV &= ~SYS_CLKDIV_SDRAM_Msk; - SYS->CLKDIV |= (1 << SYS_CLKDIV_SDRAM_Pos); //2Ƶ + SYS->CLKDIV |= (1 << SYS_CLKDIV_SDRAM_Pos); //2分频 - SDRAMC->CR0 = (2 << SDRAMC_CR0_BURSTLEN_Pos) | //2 Burst LengthΪ4 - (2 << SDRAMC_CR0_CASDELAY_Pos); + SDRAMC->CR0 = (2 << SDRAMC_CR0_BURSTLEN_Pos) | //2 Burst Length为4 + (initStruct->CASLatency << SDRAMC_CR0_CASDELAY_Pos); SDRAMC->CR1 = (initStruct->CellSize << SDRAMC_CR1_CELLSIZE_Pos) | - ((initStruct->CellWidth == 16 ? 0 : 1) << SDRAMC_CR1_CELL32BIT_Pos) | + (initStruct->CellWidth << SDRAMC_CR1_CELL32BIT_Pos) | (initStruct->CellBank << SDRAMC_CR1_BANK_Pos) | - ((initStruct->DataWidth == 16 ? 0 : 1) << SDRAMC_CR1_32BIT_Pos) | - (7 << SDRAMC_CR1_TMRD_Pos) | - (3 << SDRAMC_CR1_TRRD_Pos) | - (7 << SDRAMC_CR1_TRAS_Pos) | - (8 << SDRAMC_CR1_TRC_Pos) | - (3 << SDRAMC_CR1_TRCD_Pos) | - (3 << SDRAMC_CR1_TRP_Pos); + (0 << SDRAMC_CR1_32BIT_Pos) | + (initStruct->TimeTMRD << SDRAMC_CR1_TMRD_Pos) | + (initStruct->TimeTRRD << SDRAMC_CR1_TRRD_Pos) | + (initStruct->TimeTRAS << SDRAMC_CR1_TRAS_Pos) | + (initStruct->TimeTRC << SDRAMC_CR1_TRC_Pos) | + (initStruct->TimeTRCD << SDRAMC_CR1_TRCD_Pos) | + (initStruct->TimeTRP << SDRAMC_CR1_TRP_Pos); SDRAMC->LATCH = 0x02; + switch (initStruct->CellSize) + { + case SDRAM_CELLSIZE_16Mb: + row_n = 11; + break; + case SDRAM_CELLSIZE_64Mb: + row_n = 12; + break; + case SDRAM_CELLSIZE_128Mb: + row_n = 12; + break; + case SDRAM_CELLSIZE_256Mb: + row_n = 13; + break; + default: + row_n = 13; + break; + } + SDRAMC->REFRESH = (1 << SDRAMC_REFRESH_EN_Pos) | - (0x0FA << SDRAMC_REFRESH_RATE_Pos); + (((SystemCoreClock / 2) / 1000 * 64 / (1 << row_n)) << SDRAMC_REFRESH_RATE_Pos); + + while (SDRAMC->REFDONE == 0) + ; +} + +/****************************************************************************************************************************************** +* 函数名称: SDRAM_Enable() +* 功能说明: SDRAM使能，使能后可读写SDRAM +* 输 入: 无 +* 输 出: 无 +* 注意事项: 无 +******************************************************************************************************************************************/ +void SDRAM_Enable(void) +{ + uint32_t i; + + SYS->CLKEN |= (1 << SYS_CLKEN_SDRAM_Pos); + SDRAMC->REFRESH |= (1 << SDRAMC_REFRESH_EN_Pos); + + for (i = 0; i < 100; i++) + __NOP(); +} + +/****************************************************************************************************************************************** +* 函数名称: SDRAM_Disable() +* 功能说明: SDRAM禁能，禁能后SDRAM颗粒进入低功耗模式、并自刷新，不可读写 +* 输 入: 无 +* 输 出: 无 +* 注意事项: 无 +******************************************************************************************************************************************/ +void SDRAM_Disable(void) +{ + uint32_t i; + + SYS->CLKEN |= (1 << SYS_CLKEN_SDRAM_Pos); + SDRAMC->REFRESH &= ~(1 << SDRAMC_REFRESH_EN_Pos); - while (SDRAMC->REFDONE == 0); + for (i = 0; i < 100; i++) + __NOP(); } diff --git a/bsp/swm320-lq100/Libraries/SWM320_StdPeriph_Driver/SWM320_sdram.h b/bsp/swm320-lq100/Libraries/SWM320_StdPeriph_Driver/SWM320_sdram.h index c10d82fc12..cf8ca88a7c 100644 --- a/bsp/swm320-lq100/Libraries/SWM320_StdPeriph_Driver/SWM320_sdram.h +++ b/bsp/swm320-lq100/Libraries/SWM320_StdPeriph_Driver/SWM320_sdram.h @@ -3,21 +3,79 @@ typedef struct { - uint8_t DataWidth; // 1632 + uint8_t CellSize; // SDRAM颗粒的容量，SDRAM_CELLSIZE_16Mb、SDRAM_CELLSIZE_64Mb、SDRAM_CELLSIZE_128Mb、SDRAM_CELLSIZE_256Mb + uint8_t CellBank; // SDRAM颗粒有几个bank，SDRAM_CELLBANK_2、SDRAM_CELLBANK_4 + uint8_t CellWidth; // SDRAM颗粒的位宽，SDRAM_CELLWIDTH_16、SDRAM_CELLWIDTH_32 + uint8_t CASLatency; // 列地址到有效数据输出间隔，SDRAM_CASLATENCY_2、SDRAM_CASLATENCY_3 - uint8_t CellSize; // SDRAM - uint8_t CellBank; // SDRAMмbank - uint8_t CellWidth; // SDRAMλ 1632 + uint8_t TimeTMRD; // MRS to New Command + uint8_t TimeTRRD; // Activate to activate on different banks + uint8_t TimeTRAS; // Self refresh time，最小Self-refresh周期 + uint8_t TimeTRC; // Row cycle delay，Refresh命令到Activate命令间延时，也是两个连续Refresh命令间延时 + uint8_t TimeTRCD; // Row to column delay，行地址到列地址间延时，也即Activate命令到读写命令间延时 + uint8_t TimeTRP; // Row precharge delay，Precharge命令到另一个命令间延时 } SDRAM_InitStructure; -#define SDRAM_CELLSIZE_16Mb 3 -#define SDRAM_CELLSIZE_64Mb 0 -#define SDRAM_CELLSIZE_128Mb 1 -#define SDRAM_CELLSIZE_256Mb 2 +#define SDRAM_CELLSIZE_16Mb 3 +#define SDRAM_CELLSIZE_64Mb 0 +#define SDRAM_CELLSIZE_128Mb 1 +#define SDRAM_CELLSIZE_256Mb 2 -#define SDRAM_CELLBANK_2 0 -#define SDRAM_CELLBANK_4 1 +#define SDRAM_CELLBANK_2 0 +#define SDRAM_CELLBANK_4 1 + +#define SDRAM_CELLWIDTH_16 0 +#define SDRAM_CELLWIDTH_32 1 + +#define SDRAM_CASLATENCY_2 2 +#define SDRAM_CASLATENCY_3 3 + +#define SDRAM_TMRD_3 3 +#define SDRAM_TMRD_4 4 +#define SDRAM_TMRD_5 5 +#define SDRAM_TMRD_6 6 +#define SDRAM_TMRD_7 7 + +#define SDRAM_TRRD_2 2 +#define SDRAM_TRRD_3 3 + +#define SDRAM_TRAS_2 2 +#define SDRAM_TRAS_3 3 +#define SDRAM_TRAS_4 4 +#define SDRAM_TRAS_5 5 +#define SDRAM_TRAS_6 6 +#define SDRAM_TRAS_7 7 + +#define SDRAM_TRC_2 2 +#define SDRAM_TRC_3 3 +#define SDRAM_TRC_4 4 +#define SDRAM_TRC_5 5 +#define SDRAM_TRC_6 6 +#define SDRAM_TRC_7 7 +#define SDRAM_TRC_8 8 +#define SDRAM_TRC_9 9 +#define SDRAM_TRC_10 10 +#define SDRAM_TRC_11 11 +#define SDRAM_TRC_12 12 +#define SDRAM_TRC_13 13 +#define SDRAM_TRC_14 14 +#define SDRAM_TRC_15 15 + +#define SDRAM_TRCD_3 3 +#define SDRAM_TRCD_4 4 +#define SDRAM_TRCD_5 5 +#define SDRAM_TRCD_6 6 +#define SDRAM_TRCD_7 7 + +#define SDRAM_TRP_3 3 +#define SDRAM_TRP_4 4 +#define SDRAM_TRP_5 5 +#define SDRAM_TRP_6 6 +#define SDRAM_TRP_7 7 void SDRAM_Init(SDRAM_InitStructure *initStruct); +void SDRAM_Enable(void); +void SDRAM_Disable(void); + #endif //__SWM320_SDRAM_H__ diff --git a/bsp/swm320-lq100/Libraries/SWM320_StdPeriph_Driver/SWM320_spi.c b/bsp/swm320-lq100/Libraries/SWM320_StdPeriph_Driver/SWM320_spi.c index 6c88ada224..09430547eb 100644 --- a/bsp/swm320-lq100/Libraries/SWM320_StdPeriph_Driver/SWM320_spi.c +++ b/bsp/swm320-lq100/Libraries/SWM320_StdPeriph_Driver/SWM320_spi.c @@ -1,10 +1,10 @@ /****************************************************************************************************************************************** -* ļ: SWM320_spi.c -* ˵: SWM320ƬSPI -* ֧: http://www.synwit.com.cn/e/tool/gbook/?bid=1 -* ע: -* 汾: V1.1.0 20171025 -* ¼: +* 文件名称: SWM320_spi.c +* 功能说明: SWM320单片机的SPI功能驱动库 +* 技术支持: http://www.synwit.com.cn/e/tool/gbook/?bid=1 +* 注意事项: +* 版本日期: V1.1.0 2017年10月25日 +* 升级记录: * * ******************************************************************************************************************************************* @@ -21,14 +21,13 @@ #include "SWM320.h" #include "SWM320_spi.h" - /****************************************************************************************************************************************** -* : SPI_Init() -* ˵: SPIͬнӿڳʼ֡趨ʱ趨ٶ趨ж趨FIFO趨 -* : SPI_TypeDef * SPIx ָҪõSPIЧֵSPI0SPI1 -* SPI_InitStructure * initStruct SPI趨ֵĽṹ -* : -* ע: +* 函数名称: SPI_Init() +* 功能说明: SPI同步串行接口初始化，包括帧长度设定、时序设定、速度设定、中断设定、FIFO触发设定 +* 输 入: SPI_TypeDef * SPIx 指定要被设置的SPI，有效值包括SPI0、SPI1 +* SPI_InitStructure * initStruct 包含SPI相关设定值的结构体 +* 输 出: 无 +* 注意事项: 无 ******************************************************************************************************************************************/ void SPI_Init(SPI_TypeDef *SPIx, SPI_InitStructure *initStruct) { @@ -39,23 +38,23 @@ void SPI_Init(SPI_TypeDef *SPIx, SPI_InitStructure *initStruct) break; case ((uint32_t)SPI1): - SYS->CLKEN |= (0x01 << SYS_CLKEN_SPI0_Pos); //SPI0ʹͬһλʱʹ + SYS->CLKEN |= (0x01 << SYS_CLKEN_SPI0_Pos); //与SPI0使用同一位时钟使能 break; } - SPI_Close(SPIx); //һЩؼĴֻSPIرʱ + SPI_Close(SPIx); //一些关键寄存器只能在SPI关闭时设置 SPIx->CTRL &= ~(SPI_CTRL_FFS_Msk | SPI_CTRL_CPHA_Msk | SPI_CTRL_CPOL_Msk | SPI_CTRL_SIZE_Msk | SPI_CTRL_MSTR_Msk | SPI_CTRL_CLKDIV_Msk | SPI_CTRL_SSN_H_Msk); - SPIx->CTRL |= (initStruct->FrameFormat << SPI_CTRL_FFS_Pos) | - (initStruct->SampleEdge << SPI_CTRL_CPHA_Pos) | - (initStruct->IdleLevel << SPI_CTRL_CPOL_Pos) | - ((initStruct->WordSize - 1) << SPI_CTRL_SIZE_Pos) | - (initStruct->Master << SPI_CTRL_MSTR_Pos) | - (initStruct->clkDiv << SPI_CTRL_CLKDIV_Pos) | - (0 << SPI_CTRL_SSN_H_Pos); - - SPIx->IF = (0x01 << SPI_IF_RFOVF_Pos); //жϱ־ + SPIx->CTRL |= (initStruct->FrameFormat << SPI_CTRL_FFS_Pos) | + (initStruct->SampleEdge << SPI_CTRL_CPHA_Pos) | + (initStruct->IdleLevel << SPI_CTRL_CPOL_Pos) | + ((initStruct->WordSize - 1) << SPI_CTRL_SIZE_Pos) | + (initStruct->Master << SPI_CTRL_MSTR_Pos) | + (initStruct->clkDiv << SPI_CTRL_CLKDIV_Pos) | + (0 << SPI_CTRL_SSN_H_Pos); + + SPIx->IF = (0x01 << SPI_IF_RFOVF_Pos); //清除中断标志 SPIx->IE &= ~(SPI_IE_RFHF_Msk | SPI_IE_TFHF_Msk | SPI_IE_FTC_Msk); SPIx->IE |= (initStruct->RXHFullIEn << SPI_IE_RFHF_Pos) | (initStruct->TXEmptyIEn << SPI_IE_TFHF_Pos) | @@ -88,11 +87,11 @@ void SPI_Init(SPI_TypeDef *SPIx, SPI_InitStructure *initStruct) } /****************************************************************************************************************************************** -* : SPI_Open() -* ˵: SPI򿪣շ -* : SPI_TypeDef * SPIx ָҪõSPIЧֵSPI0SPI1 -* : -* ע: +* 函数名称: SPI_Open() +* 功能说明: SPI打开，允许收发 +* 输 入: SPI_TypeDef * SPIx 指定要被设置的SPI，有效值包括SPI0、SPI1 +* 输 出: 无 +* 注意事项: 无 ******************************************************************************************************************************************/ void SPI_Open(SPI_TypeDef *SPIx) { @@ -100,11 +99,11 @@ void SPI_Open(SPI_TypeDef *SPIx) } /****************************************************************************************************************************************** -* : SPI_Close() -* ˵: SPIرգֹշ -* : SPI_TypeDef * SPIx ָҪõSPIЧֵSPI0SPI1 -* : -* ע: +* 函数名称: SPI_Close() +* 功能说明: SPI关闭，禁止收发 +* 输 入: SPI_TypeDef * SPIx 指定要被设置的SPI，有效值包括SPI0、SPI1 +* 输 出: 无 +* 注意事项: 无 ******************************************************************************************************************************************/ void SPI_Close(SPI_TypeDef *SPIx) { @@ -112,11 +111,11 @@ void SPI_Close(SPI_TypeDef *SPIx) } /****************************************************************************************************************************************** -* : SPI_Read() -* ˵: ȡһ -* : SPI_TypeDef * SPIx ָҪõSPIЧֵSPI0SPI1 -* : uint32_t ȡ -* ע: +* 函数名称: SPI_Read() +* 功能说明: 读取一个数据 +* 输 入: SPI_TypeDef * SPIx 指定要被设置的SPI，有效值包括SPI0、SPI1 +* 输 出: uint32_t 读取到的数据 +* 注意事项: 无 ******************************************************************************************************************************************/ uint32_t SPI_Read(SPI_TypeDef *SPIx) { @@ -124,12 +123,12 @@ uint32_t SPI_Read(SPI_TypeDef *SPIx) } /****************************************************************************************************************************************** -* : SPI_Write() -* ˵: дһ -* : SPI_TypeDef * SPIx ָҪõSPIЧֵSPI0SPI1 -* uint32_t Ҫд -* : -* ע: +* 函数名称: SPI_Write() +* 功能说明: 写入一个数据 +* 输 入: SPI_TypeDef * SPIx 指定要被设置的SPI，有效值包括SPI0、SPI1 +* uint32_t 要写入的数据 +* 输 出: 无 +* 注意事项: 无 ******************************************************************************************************************************************/ void SPI_Write(SPI_TypeDef *SPIx, uint32_t data) { @@ -137,12 +136,12 @@ void SPI_Write(SPI_TypeDef *SPIx, uint32_t data) } /****************************************************************************************************************************************** -* : SPI_WriteWithWait() -* ˵: дһݲȴȫͳȥ -* : SPI_TypeDef * SPIx ָҪõSPIЧֵSPI0SPI1SPI1 -* uint32_t Ҫд -* : -* ע: +* 函数名称: SPI_WriteWithWait() +* 功能说明: 写入一个数据并等待数据完全发送出去 +* 输 入: SPI_TypeDef * SPIx 指定要被设置的SPI，有效值包括SPI0、SPI1、SPI1 +* uint32_t 要写入的数据 +* 输 出: 无 +* 注意事项: 无 ******************************************************************************************************************************************/ void SPI_WriteWithWait(SPI_TypeDef *SPIx, uint32_t data) { @@ -150,31 +149,33 @@ void SPI_WriteWithWait(SPI_TypeDef *SPIx, uint32_t data) SPIx->DATA = data; - while ((SPIx->STAT & SPI_STAT_WTC_Msk) == 0); + while ((SPIx->STAT & SPI_STAT_WTC_Msk) == 0) + ; } /****************************************************************************************************************************************** -* : SPI_ReadWrite() -* ˵: һݣط͹нյ -* : SPI_TypeDef * SPIx ָҪõSPIЧֵSPI0SPI1 -* uint32_t data Ҫ͵ -* : uint32_t յ -* ע: ͬһSPIģ飬˺ӦSPI_Write()ãΪSPI_Write()SPI_STAT_RFNE״̬ +* 函数名称: SPI_ReadWrite() +* 功能说明: 发送一个数据，并返回发送过程中接收到的 +* 输 入: SPI_TypeDef * SPIx 指定要被设置的SPI，有效值包括SPI0、SPI1 +* uint32_t data 要发送的数据 +* 输 出: uint32_t 接收到的数据 +* 注意事项: 对于同一个SPI模块，此函数不应与SPI_Write()混着用，因为SPI_Write()不清除SPI_STAT_RFNE状态 ******************************************************************************************************************************************/ uint32_t SPI_ReadWrite(SPI_TypeDef *SPIx, uint32_t data) { SPIx->DATA = data; - while (!(SPIx->STAT & SPI_STAT_RFNE_Msk)); + while (!(SPIx->STAT & SPI_STAT_RFNE_Msk)) + ; return SPIx->DATA; } /****************************************************************************************************************************************** -* : SPI_IsRXEmpty() -* ˵: FIFOǷգԼSPI_Read() -* : SPI_TypeDef * SPIx ָҪõSPIЧֵSPI0SPI1 -* : uint32_t 1 FIFO 0 FIFOǿ -* ע: +* 函数名称: SPI_IsRXEmpty() +* 功能说明: 接收FIFO是否空，如果不空则可以继续SPI_Read() +* 输 入: SPI_TypeDef * SPIx 指定要被设置的SPI，有效值包括SPI0、SPI1 +* 输 出: uint32_t 1 接收FIFO空 0 接收FIFO非空 +* 注意事项: 无 ******************************************************************************************************************************************/ uint32_t SPI_IsRXEmpty(SPI_TypeDef *SPIx) { @@ -182,11 +183,11 @@ uint32_t SPI_IsRXEmpty(SPI_TypeDef *SPIx) } /****************************************************************************************************************************************** -* : SPI_IsTXFull() -* ˵: FIFOǷԼSPI_Write() -* : SPI_TypeDef * SPIx ָҪõSPIЧֵSPI0SPI1 -* : uint32_t 1 FIFO 0 FIFO -* ע: +* 函数名称: SPI_IsTXFull() +* 功能说明: 发送FIFO是否满，如果不满则可以继续SPI_Write() +* 输 入: SPI_TypeDef * SPIx 指定要被设置的SPI，有效值包括SPI0、SPI1 +* 输 出: uint32_t 1 发送FIFO满 0 发送FIFO不满 +* 注意事项: 无 ******************************************************************************************************************************************/ uint32_t SPI_IsTXFull(SPI_TypeDef *SPIx) { @@ -194,24 +195,23 @@ uint32_t SPI_IsTXFull(SPI_TypeDef *SPIx) } /****************************************************************************************************************************************** -* : SPI_IsTXEmpty() -* ˵: FIFOǷ -* : SPI_TypeDef * SPIx ָҪõSPIЧֵSPI0SPI1 -* : uint32_t 1 FIFO 0 FIFOǿ -* ע: +* 函数名称: SPI_IsTXEmpty() +* 功能说明: 发送FIFO是否空 +* 输 入: SPI_TypeDef * SPIx 指定要被设置的SPI，有效值包括SPI0、SPI1 +* 输 出: uint32_t 1 发送FIFO空 0 发送FIFO非空 +* 注意事项: 无 ******************************************************************************************************************************************/ uint32_t SPI_IsTXEmpty(SPI_TypeDef *SPIx) { return (SPIx->STAT & SPI_STAT_TFE_Msk) ? 1 : 0; } - /****************************************************************************************************************************************** -* : SPI_INTRXHalfFullEn() -* ˵: FIFOжʹ -* : SPI_TypeDef * SPIx ָҪõSPIЧֵSPI0SPI1 -* : -* ע: +* 函数名称: SPI_INTRXHalfFullEn() +* 功能说明: 接收FIFO半满中断使能 +* 输 入: SPI_TypeDef * SPIx 指定要被设置的SPI，有效值包括SPI0、SPI1 +* 输 出: 无 +* 注意事项: 无 ******************************************************************************************************************************************/ void SPI_INTRXHalfFullEn(SPI_TypeDef *SPIx) { @@ -219,11 +219,11 @@ void SPI_INTRXHalfFullEn(SPI_TypeDef *SPIx) } /****************************************************************************************************************************************** -* : SPI_INTRXHalfFullDis() -* ˵: FIFOжϽֹ -* : SPI_TypeDef * SPIx ָҪõSPIЧֵSPI0SPI1 -* : -* ע: +* 函数名称: SPI_INTRXHalfFullDis() +* 功能说明: 接收FIFO半满中断禁止 +* 输 入: SPI_TypeDef * SPIx 指定要被设置的SPI，有效值包括SPI0、SPI1 +* 输 出: 无 +* 注意事项: 无 ******************************************************************************************************************************************/ void SPI_INTRXHalfFullDis(SPI_TypeDef *SPIx) { @@ -231,11 +231,23 @@ void SPI_INTRXHalfFullDis(SPI_TypeDef *SPIx) } /****************************************************************************************************************************************** -* : SPI_INTRXHalfFullStat() -* ˵: FIFOж״̬ -* : SPI_TypeDef * SPIx ָҪõSPIЧֵSPI0SPI1 -* : uint32_t 1 FIFOﵽ 0 FIFOδﵽ -* ע: +* 函数名称: SPI_INTRXHalfFullClr() +* 功能说明: 接收FIFO半满中断标志清除 +* 输 入: SPI_TypeDef * SPIx 指定要被设置的SPI，有效值包括SPI0、SPI1 +* 输 出: 无 +* 注意事项: 无 +******************************************************************************************************************************************/ +void SPI_INTRXHalfFullClr(SPI_TypeDef *SPIx) +{ + SPIx->IF = (1 << SPI_IF_RFHF_Pos); +} + +/****************************************************************************************************************************************** +* 函数名称: SPI_INTRXHalfFullStat() +* 功能说明: 接收FIFO半满中断状态 +* 输 入: SPI_TypeDef * SPIx 指定要被设置的SPI，有效值包括SPI0、SPI1 +* 输 出: uint32_t 1 接收FIFO达到半满 0 接收FIFO未达到半满 +* 注意事项: 无 ******************************************************************************************************************************************/ uint32_t SPI_INTRXHalfFullStat(SPI_TypeDef *SPIx) { @@ -243,11 +255,11 @@ uint32_t SPI_INTRXHalfFullStat(SPI_TypeDef *SPIx) } /****************************************************************************************************************************************** -* : SPI_INTRXFullEn() -* ˵: FIFOжʹ -* : SPI_TypeDef * SPIx ָҪõSPIЧֵSPI0SPI1 -* : -* ע: +* 函数名称: SPI_INTRXFullEn() +* 功能说明: 接收FIFO满中断使能 +* 输 入: SPI_TypeDef * SPIx 指定要被设置的SPI，有效值包括SPI0、SPI1 +* 输 出: 无 +* 注意事项: 无 ******************************************************************************************************************************************/ void SPI_INTRXFullEn(SPI_TypeDef *SPIx) { @@ -255,11 +267,11 @@ void SPI_INTRXFullEn(SPI_TypeDef *SPIx) } /****************************************************************************************************************************************** -* : SPI_INTRXFullDis() -* ˵: FIFOжϽֹ -* : SPI_TypeDef * SPIx ָҪõSPIЧֵSPI0SPI1 -* : -* ע: +* 函数名称: SPI_INTRXFullDis() +* 功能说明: 接收FIFO满中断禁止 +* 输 入: SPI_TypeDef * SPIx 指定要被设置的SPI，有效值包括SPI0、SPI1 +* 输 出: 无 +* 注意事项: 无 ******************************************************************************************************************************************/ void SPI_INTRXFullDis(SPI_TypeDef *SPIx) { @@ -267,11 +279,23 @@ void SPI_INTRXFullDis(SPI_TypeDef *SPIx) } /****************************************************************************************************************************************** -* : SPI_INTRXFullStat() -* ˵: FIFOж״̬ -* : SPI_TypeDef * SPIx ָҪõSPIЧֵSPI0SPI1 -* : uint32_t 1 FIFO 0 FIFOδ -* ע: +* 函数名称: SPI_INTRXFullClr() +* 功能说明: 接收FIFO满中断标志清除 +* 输 入: SPI_TypeDef * SPIx 指定要被设置的SPI，有效值包括SPI0、SPI1 +* 输 出: 无 +* 注意事项: 无 +******************************************************************************************************************************************/ +void SPI_INTRXFullClr(SPI_TypeDef *SPIx) +{ + SPIx->IF = (1 << SPI_IF_RFF_Pos); +} + +/****************************************************************************************************************************************** +* 函数名称: SPI_INTRXFullStat() +* 功能说明: 接收FIFO满中断状态 +* 输 入: SPI_TypeDef * SPIx 指定要被设置的SPI，有效值包括SPI0、SPI1 +* 输 出: uint32_t 1 接收FIFO满 0 接收FIFO未满 +* 注意事项: 无 ******************************************************************************************************************************************/ uint32_t SPI_INTRXFullStat(SPI_TypeDef *SPIx) { @@ -279,11 +303,11 @@ uint32_t SPI_INTRXFullStat(SPI_TypeDef *SPIx) } /****************************************************************************************************************************************** -* : SPI_INTRXOverflowEn() -* ˵: FIFOжʹ -* : SPI_TypeDef * SPIx ָҪõSPIЧֵSPI0SPI1 -* : -* ע: +* 函数名称: SPI_INTRXOverflowEn() +* 功能说明: 接收FIFO溢出中断使能 +* 输 入: SPI_TypeDef * SPIx 指定要被设置的SPI，有效值包括SPI0、SPI1 +* 输 出: 无 +* 注意事项: 无 ******************************************************************************************************************************************/ void SPI_INTRXOverflowEn(SPI_TypeDef *SPIx) { @@ -291,11 +315,11 @@ void SPI_INTRXOverflowEn(SPI_TypeDef *SPIx) } /****************************************************************************************************************************************** -* : SPI_INTRXOverflowDis() -* ˵: FIFOжϽֹ -* : SPI_TypeDef * SPIx ָҪõSPIЧֵSPI0SPI1 -* : -* ע: +* 函数名称: SPI_INTRXOverflowDis() +* 功能说明: 接收FIFO溢出中断禁止 +* 输 入: SPI_TypeDef * SPIx 指定要被设置的SPI，有效值包括SPI0、SPI1 +* 输 出: 无 +* 注意事项: 无 ******************************************************************************************************************************************/ void SPI_INTRXOverflowDis(SPI_TypeDef *SPIx) { @@ -303,11 +327,11 @@ void SPI_INTRXOverflowDis(SPI_TypeDef *SPIx) } /****************************************************************************************************************************************** -* : SPI_INTRXOverflowClr() -* ˵: FIFOжϱ־ -* : SPI_TypeDef * SPIx ָҪõSPIЧֵSPI0SPI1 -* : -* ע: +* 函数名称: SPI_INTRXOverflowClr() +* 功能说明: 接收FIFO溢出中断标志清除 +* 输 入: SPI_TypeDef * SPIx 指定要被设置的SPI，有效值包括SPI0、SPI1 +* 输 出: 无 +* 注意事项: 无 ******************************************************************************************************************************************/ void SPI_INTRXOverflowClr(SPI_TypeDef *SPIx) { @@ -315,11 +339,11 @@ void SPI_INTRXOverflowClr(SPI_TypeDef *SPIx) } /****************************************************************************************************************************************** -* : SPI_INTRXOverflowStat() -* ˵: FIFOж״̬ -* : SPI_TypeDef * SPIx ָҪõSPIЧֵSPI0SPI1 -* : uint32_t 1 FIFO 0 FIFOδ -* ע: +* 函数名称: SPI_INTRXOverflowStat() +* 功能说明: 接收FIFO溢出中断状态 +* 输 入: SPI_TypeDef * SPIx 指定要被设置的SPI，有效值包括SPI0、SPI1 +* 输 出: uint32_t 1 接收FIFO溢出 0 接收FIFO未溢出 +* 注意事项: 无 ******************************************************************************************************************************************/ uint32_t SPI_INTRXOverflowStat(SPI_TypeDef *SPIx) { @@ -327,11 +351,11 @@ uint32_t SPI_INTRXOverflowStat(SPI_TypeDef *SPIx) } /****************************************************************************************************************************************** -* : SPI_INTTXHalfFullEn() -* ˵: FIFOжʹ -* : SPI_TypeDef * SPIx ָҪõSPIЧֵSPI0SPI1 -* : -* ע: +* 函数名称: SPI_INTTXHalfFullEn() +* 功能说明: 发送FIFO半满中断使能 +* 输 入: SPI_TypeDef * SPIx 指定要被设置的SPI，有效值包括SPI0、SPI1 +* 输 出: 无 +* 注意事项: 无 ******************************************************************************************************************************************/ void SPI_INTTXHalfFullEn(SPI_TypeDef *SPIx) { @@ -339,11 +363,11 @@ void SPI_INTTXHalfFullEn(SPI_TypeDef *SPIx) } /****************************************************************************************************************************************** -* : SPI_INTTXHalfFullDis() -* ˵: FIFOжϽֹ -* : SPI_TypeDef * SPIx ָҪõSPIЧֵSPI0SPI1 -* : -* ע: +* 函数名称: SPI_INTTXHalfFullDis() +* 功能说明: 发送FIFO半满中断禁止 +* 输 入: SPI_TypeDef * SPIx 指定要被设置的SPI，有效值包括SPI0、SPI1 +* 输 出: 无 +* 注意事项: 无 ******************************************************************************************************************************************/ void SPI_INTTXHalfFullDis(SPI_TypeDef *SPIx) { @@ -351,11 +375,23 @@ void SPI_INTTXHalfFullDis(SPI_TypeDef *SPIx) } /****************************************************************************************************************************************** -* : SPI_INTTXHalfFullStat() -* ˵: FIFOж״̬ -* : SPI_TypeDef * SPIx ָҪõSPIЧֵSPI0SPI1 -* : uint32_t 1 FIFOﵽ 0 FIFOδﵽ -* ע: +* 函数名称: SPI_INTTXHalfFullClr() +* 功能说明: 发送FIFO半满中断标志清除 +* 输 入: SPI_TypeDef * SPIx 指定要被设置的SPI，有效值包括SPI0、SPI1 +* 输 出: 无 +* 注意事项: 无 +******************************************************************************************************************************************/ +void SPI_INTTXHalfFullClr(SPI_TypeDef *SPIx) +{ + SPIx->IF = (1 << SPI_IF_TFHF_Pos); +} + +/****************************************************************************************************************************************** +* 函数名称: SPI_INTTXHalfFullStat() +* 功能说明: 发送FIFO半满中断状态 +* 输 入: SPI_TypeDef * SPIx 指定要被设置的SPI，有效值包括SPI0、SPI1 +* 输 出: uint32_t 1 发送FIFO达到半满 0 发送FIFO未达到半满 +* 注意事项: 无 ******************************************************************************************************************************************/ uint32_t SPI_INTTXHalfFullStat(SPI_TypeDef *SPIx) { @@ -363,11 +399,11 @@ uint32_t SPI_INTTXHalfFullStat(SPI_TypeDef *SPIx) } /****************************************************************************************************************************************** -* : SPI_INTTXEmptyEn() -* ˵: FIFOжʹ -* : SPI_TypeDef * SPIx ָҪõSPIЧֵSPI0SPI1 -* : -* ע: +* 函数名称: SPI_INTTXEmptyEn() +* 功能说明: 发送FIFO空中断使能 +* 输 入: SPI_TypeDef * SPIx 指定要被设置的SPI，有效值包括SPI0、SPI1 +* 输 出: 无 +* 注意事项: 无 ******************************************************************************************************************************************/ void SPI_INTTXEmptyEn(SPI_TypeDef *SPIx) { @@ -375,11 +411,11 @@ void SPI_INTTXEmptyEn(SPI_TypeDef *SPIx) } /****************************************************************************************************************************************** -* : SPI_INTTXEmptyDis() -* ˵: FIFOжϽֹ -* : SPI_TypeDef * SPIx ָҪõSPIЧֵSPI0SPI1 -* : -* ע: +* 函数名称: SPI_INTTXEmptyDis() +* 功能说明: 发送FIFO空中断禁止 +* 输 入: SPI_TypeDef * SPIx 指定要被设置的SPI，有效值包括SPI0、SPI1 +* 输 出: 无 +* 注意事项: 无 ******************************************************************************************************************************************/ void SPI_INTTXEmptyDis(SPI_TypeDef *SPIx) { @@ -387,11 +423,23 @@ void SPI_INTTXEmptyDis(SPI_TypeDef *SPIx) } /****************************************************************************************************************************************** -* : SPI_INTTXEmptyStat() -* ˵: FIFOж״̬ -* : SPI_TypeDef * SPIx ָҪõSPIЧֵSPI0SPI1 -* : uint32_t 1 FIFO 0 FIFOǿ -* ע: +* 函数名称: SPI_INTTXEmptyClr() +* 功能说明: 发送FIFO空中断标志清除 +* 输 入: SPI_TypeDef * SPIx 指定要被设置的SPI，有效值包括SPI0、SPI1 +* 输 出: 无 +* 注意事项: 无 +******************************************************************************************************************************************/ +void SPI_INTTXEmptyClr(SPI_TypeDef *SPIx) +{ + SPIx->IF = (1 << SPI_IF_TFE_Pos); +} + +/****************************************************************************************************************************************** +* 函数名称: SPI_INTTXEmptyStat() +* 功能说明: 发送FIFO空中断状态 +* 输 入: SPI_TypeDef * SPIx 指定要被设置的SPI，有效值包括SPI0、SPI1 +* 输 出: uint32_t 1 发送FIFO空 0 发送FIFO非空 +* 注意事项: 无 ******************************************************************************************************************************************/ uint32_t SPI_INTTXEmptyStat(SPI_TypeDef *SPIx) { @@ -399,11 +447,11 @@ uint32_t SPI_INTTXEmptyStat(SPI_TypeDef *SPIx) } /****************************************************************************************************************************************** -* : SPI_INTTXCompleteEn() -* ˵: FIFOҷλĴжʹ -* : SPI_TypeDef * SPIx ָҪõSPIЧֵSPI0SPI1 -* : -* ע: +* 函数名称: SPI_INTTXCompleteEn() +* 功能说明: 发送FIFO空且发送移位寄存器空中断使能 +* 输 入: SPI_TypeDef * SPIx 指定要被设置的SPI，有效值包括SPI0、SPI1 +* 输 出: 无 +* 注意事项: 无 ******************************************************************************************************************************************/ void SPI_INTTXCompleteEn(SPI_TypeDef *SPIx) { @@ -411,11 +459,11 @@ void SPI_INTTXCompleteEn(SPI_TypeDef *SPIx) } /****************************************************************************************************************************************** -* : SPI_INTTXCompleteDis() -* ˵: FIFOҷλĴжϽֹ -* : SPI_TypeDef * SPIx ָҪõSPIЧֵSPI0SPI1 -* : -* ע: +* 函数名称: SPI_INTTXCompleteDis() +* 功能说明: 发送FIFO空且发送移位寄存器空中断禁止 +* 输 入: SPI_TypeDef * SPIx 指定要被设置的SPI，有效值包括SPI0、SPI1 +* 输 出: 无 +* 注意事项: 无 ******************************************************************************************************************************************/ void SPI_INTTXCompleteDis(SPI_TypeDef *SPIx) { @@ -423,11 +471,11 @@ void SPI_INTTXCompleteDis(SPI_TypeDef *SPIx) } /****************************************************************************************************************************************** -* : SPI_INTTXCompleteClr() -* ˵: FIFOҷλĴж״̬ -* : SPI_TypeDef * SPIx ָҪõSPIЧֵSPI0SPI1 -* : -* ע: +* 函数名称: SPI_INTTXCompleteClr() +* 功能说明: 发送FIFO空且发送移位寄存器空中断状态清除 +* 输 入: SPI_TypeDef * SPIx 指定要被设置的SPI，有效值包括SPI0、SPI1 +* 输 出: 无 +* 注意事项: 无 ******************************************************************************************************************************************/ void SPI_INTTXCompleteClr(SPI_TypeDef *SPIx) { @@ -435,13 +483,61 @@ void SPI_INTTXCompleteClr(SPI_TypeDef *SPIx) } /****************************************************************************************************************************************** -* : SPI_INTTXCompleteStat() -* ˵: FIFOҷλĴж״̬ -* : SPI_TypeDef * SPIx ָҪõSPIЧֵSPI0SPI1 -* : uint32_t 1 FIFOҷλĴ 0 FIFOλĴǿ -* ע: +* 函数名称: SPI_INTTXCompleteStat() +* 功能说明: 发送FIFO空且发送移位寄存器空中断状态 +* 输 入: SPI_TypeDef * SPIx 指定要被设置的SPI，有效值包括SPI0、SPI1 +* 输 出: uint32_t 1 发送FIFO空且发送移位寄存器空 0 发送FIFO或发送移位寄存器非空 +* 注意事项: 无 ******************************************************************************************************************************************/ uint32_t SPI_INTTXCompleteStat(SPI_TypeDef *SPIx) { return (SPIx->IF & SPI_IF_FTC_Msk) ? 1 : 0; } + +/****************************************************************************************************************************************** +* 函数名称: SPI_INTTXWordCompleteEn() +* 功能说明: 发送FIFO字发送完成中断使能 +* 输 入: SPI_TypeDef * SPIx 指定要被设置的SPI，有效值包括SPI0、SPI1 +* 输 出: 无 +* 注意事项: 无 +******************************************************************************************************************************************/ +void SPI_INTTXWordCompleteEn(SPI_TypeDef *SPIx) +{ + SPIx->IE |= (0x01 << SPI_IE_WTC_Pos); +} + +/****************************************************************************************************************************************** +* 函数名称: SPI_INTTXWordCompleteDis() +* 功能说明: 发送FIFO字发送完成中断禁止 +* 输 入: SPI_TypeDef * SPIx 指定要被设置的SPI，有效值包括SPI0、SPI1 +* 输 出: 无 +* 注意事项: 无 +******************************************************************************************************************************************/ +void SPI_INTTXWordCompleteDis(SPI_TypeDef *SPIx) +{ + SPIx->IE &= ~(0x01 << SPI_IE_WTC_Pos); +} + +/****************************************************************************************************************************************** +* 函数名称: SPI_INTTXWordCompleteClr() +* 功能说明: 发送FIFO字发送完成中断标志清除 +* 输 入: SPI_TypeDef * SPIx 指定要被设置的SPI，有效值包括SPI0、SPI1 +* 输 出: 无 +* 注意事项: 无 +******************************************************************************************************************************************/ +void SPI_INTTXWordCompleteClr(SPI_TypeDef *SPIx) +{ + SPIx->IF = (1 << SPI_IF_WTC_Pos); +} + +/****************************************************************************************************************************************** +* 函数名称: SPI_INTTXWordCompleteStat() +* 功能说明: 发送FIFO字发送完成中断状态 +* 输 入: SPI_TypeDef * SPIx 指定要被设置的SPI，有效值包括SPI0、SPI1 +* 输 出: uint32_t 1 发送完成中断已发生 0 发送完成中断未发生 +* 注意事项: 无 +******************************************************************************************************************************************/ +uint32_t SPI_INTTXWordCompleteStat(SPI_TypeDef *SPIx) +{ + return (SPIx->IF & SPI_IF_WTC_Msk) ? 1 : 0; +} diff --git a/bsp/swm320-lq100/Libraries/SWM320_StdPeriph_Driver/SWM320_spi.h b/bsp/swm320-lq100/Libraries/SWM320_StdPeriph_Driver/SWM320_spi.h index 3230c4a774..db024d6bca 100644 --- a/bsp/swm320-lq100/Libraries/SWM320_StdPeriph_Driver/SWM320_spi.h +++ b/bsp/swm320-lq100/Libraries/SWM320_StdPeriph_Driver/SWM320_spi.h @@ -3,57 +3,56 @@ typedef struct { - uint8_t FrameFormat; //֡ʽSPI_FORMAT_SPISPI_FORMAT_TI_SSI - uint8_t SampleEdge; //SPI֡ʽ£ѡݲأSPI_FIRST_EDGESPI_SECOND_EDGE - uint8_t IdleLevel; //SPI֡ʽ£ѡʱݴʱʱߵĵƽSPI_LOW_LEVELSPI_HIGH_LEVEL - uint8_t WordSize; //ֳ, Чֵ4-16 - uint8_t Master; //1 ģʽ 0 ӻģʽ - uint8_t clkDiv; //SPI_CLK = SYS_CLK / clkDivЧֵSPI_CLKDIV_4SPI_CLKDIV_8... ... SPI_CLKDIV_512 - - uint8_t RXHFullIEn; //FIFOжʹ - uint8_t TXEmptyIEn; //FIFO жʹ - uint8_t TXCompleteIEn; //FIFO ҷλĴжʹ + uint8_t FrameFormat; //帧格式：SPI_FORMAT_SPI、SPI_FORMAT_TI_SSI + uint8_t SampleEdge; //在SPI帧格式下，选择数据采样边沿：SPI_FIRST_EDGE、SPI_SECOND_EDGE + uint8_t IdleLevel; //在SPI帧格式下，选择空闲时（无数据传输时）时钟线的电平：SPI_LOW_LEVEL、SPI_HIGH_LEVEL + uint8_t WordSize; //字长度, 有效值4-16 + uint8_t Master; //1 主机模式 0 从机模式 + uint8_t clkDiv; //SPI_CLK = SYS_CLK / clkDiv，有效值：SPI_CLKDIV_4、SPI_CLKDIV_8、... ... 、SPI_CLKDIV_512 + + uint8_t RXHFullIEn; //接收FIFO半满中断使能 + uint8_t TXEmptyIEn; //发送FIFO 空中断使能 + uint8_t TXCompleteIEn; //发送FIFO 空且发送移位寄存器空中断使能 } SPI_InitStructure; -#define SPI_FORMAT_SPI 0 //Motorola SPI ʽ -#define SPI_FORMAT_TI_SSI 1 //TI SSI ʽ - -#define SPI_FIRST_EDGE 0 //һʱؿʼ -#define SPI_SECOND_EDGE 1 //ڶʱؿʼ +#define SPI_FORMAT_SPI 0 //Motorola SPI 格式 +#define SPI_FORMAT_TI_SSI 1 //TI SSI 格式 -#define SPI_LOW_LEVEL 0 //ʱʱֵ߱͵ƽ -#define SPI_HIGH_LEVEL 1 //ʱʱָ߱ߵƽ +#define SPI_FIRST_EDGE 0 //第一个时钟沿开始采样 +#define SPI_SECOND_EDGE 1 //第二个时钟沿开始采样 -#define SPI_CLKDIV_4 0 -#define SPI_CLKDIV_8 1 -#define SPI_CLKDIV_16 2 -#define SPI_CLKDIV_32 3 -#define SPI_CLKDIV_64 4 -#define SPI_CLKDIV_128 5 -#define SPI_CLKDIV_256 6 -#define SPI_CLKDIV_512 7 +#define SPI_LOW_LEVEL 0 //空闲时时钟线保持低电平 +#define SPI_HIGH_LEVEL 1 //空闲时时钟线保持高电平 +#define SPI_CLKDIV_4 0 +#define SPI_CLKDIV_8 1 +#define SPI_CLKDIV_16 2 +#define SPI_CLKDIV_32 3 +#define SPI_CLKDIV_64 4 +#define SPI_CLKDIV_128 5 +#define SPI_CLKDIV_256 6 +#define SPI_CLKDIV_512 7 - -void SPI_Init(SPI_TypeDef *SPIx, SPI_InitStructure *initStruct); //SPIʼ -void SPI_Open(SPI_TypeDef *SPIx); //SPI򿪣շ -void SPI_Close(SPI_TypeDef *SPIx); //SPIرգֹշ +void SPI_Init(SPI_TypeDef *SPIx, SPI_InitStructure *initStruct); //SPI初始化 +void SPI_Open(SPI_TypeDef *SPIx); //SPI打开，允许收发 +void SPI_Close(SPI_TypeDef *SPIx); //SPI关闭，禁止收发 uint32_t SPI_Read(SPI_TypeDef *SPIx); void SPI_Write(SPI_TypeDef *SPIx, uint32_t data); void SPI_WriteWithWait(SPI_TypeDef *SPIx, uint32_t data); uint32_t SPI_ReadWrite(SPI_TypeDef *SPIx, uint32_t data); -uint32_t SPI_IsRXEmpty(SPI_TypeDef *SPIx); //FIFOǷգԼSPI_Read() -uint32_t SPI_IsTXFull(SPI_TypeDef *SPIx); //FIFOǷԼSPI_Write() -uint32_t SPI_IsTXEmpty(SPI_TypeDef *SPIx); //FIFOǷ - +uint32_t SPI_IsRXEmpty(SPI_TypeDef *SPIx); //接收FIFO是否空，如果不空则可以继续SPI_Read() +uint32_t SPI_IsTXFull(SPI_TypeDef *SPIx); //发送FIFO是否满，如果不满则可以继续SPI_Write() +uint32_t SPI_IsTXEmpty(SPI_TypeDef *SPIx); //发送FIFO是否空 void SPI_INTRXHalfFullEn(SPI_TypeDef *SPIx); void SPI_INTRXHalfFullDis(SPI_TypeDef *SPIx); +void SPI_INTRXHalfFullClr(SPI_TypeDef *SPIx); uint32_t SPI_INTRXHalfFullStat(SPI_TypeDef *SPIx); void SPI_INTRXFullEn(SPI_TypeDef *SPIx); void SPI_INTRXFullDis(SPI_TypeDef *SPIx); +void SPI_INTRXFullClr(SPI_TypeDef *SPIx); uint32_t SPI_INTRXFullStat(SPI_TypeDef *SPIx); void SPI_INTRXOverflowEn(SPI_TypeDef *SPIx); void SPI_INTRXOverflowDis(SPI_TypeDef *SPIx); @@ -62,14 +61,20 @@ uint32_t SPI_INTRXOverflowStat(SPI_TypeDef *SPIx); void SPI_INTTXHalfFullEn(SPI_TypeDef *SPIx); void SPI_INTTXHalfFullDis(SPI_TypeDef *SPIx); +void SPI_INTTXHalfFullClr(SPI_TypeDef *SPIx); uint32_t SPI_INTTXHalfFullStat(SPI_TypeDef *SPIx); void SPI_INTTXEmptyEn(SPI_TypeDef *SPIx); void SPI_INTTXEmptyDis(SPI_TypeDef *SPIx); +void SPI_INTTXEmptyClr(SPI_TypeDef *SPIx); uint32_t SPI_INTTXEmptyStat(SPI_TypeDef *SPIx); void SPI_INTTXCompleteEn(SPI_TypeDef *SPIx); void SPI_INTTXCompleteDis(SPI_TypeDef *SPIx); void SPI_INTTXCompleteClr(SPI_TypeDef *SPIx); uint32_t SPI_INTTXCompleteStat(SPI_TypeDef *SPIx); +void SPI_INTTXWordCompleteEn(SPI_TypeDef *SPIx); +void SPI_INTTXWordCompleteDis(SPI_TypeDef *SPIx); +void SPI_INTTXWordCompleteClr(SPI_TypeDef *SPIx); +uint32_t SPI_INTTXWordCompleteStat(SPI_TypeDef *SPIx); #endif //__SWM320_SPI_H__ diff --git a/bsp/swm320-lq100/Libraries/SWM320_StdPeriph_Driver/SWM320_sram.c b/bsp/swm320-lq100/Libraries/SWM320_StdPeriph_Driver/SWM320_sram.c new file mode 100644 index 0000000000..8d0ad56d90 --- /dev/null +++ b/bsp/swm320-lq100/Libraries/SWM320_StdPeriph_Driver/SWM320_sram.c @@ -0,0 +1,56 @@ +/****************************************************************************************************************************************** +* 文件名称: SWM320_sram.c +* 功能说明: SWM320单片机的SRAM驱动程序 +* 技术支持: http://www.synwit.com.cn/e/tool/gbook/?bid=1 +* 注意事项: +* 版本日期: V1.1.0 2017年10月25日 +* 升级记录: +* +* +******************************************************************************************************************************************* +* @attention +* +* THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS WITH CODING INFORMATION +* REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE TIME. AS A RESULT, SYNWIT SHALL NOT BE HELD LIABLE +* FOR ANY DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING FROM THE CONTENT +* OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE CODING INFORMATION CONTAINED HEREIN IN CONN- +* -ECTION WITH THEIR PRODUCTS. +* +* COPYRIGHT 2012 Synwit Technology +*******************************************************************************************************************************************/ +#include "SWM320.h" +#include "SWM320_sram.h" + +/****************************************************************************************************************************************** +* 函数名称: SRAM_Init() +* 功能说明: SRAM控制器初始化 +* 输 入: SRAM_InitStructure * initStruct 包含 SRAM 控制器相关设定值的结构体 +* 输 出: 无 +* 注意事项: 无 +******************************************************************************************************************************************/ +void SRAM_Init(SRAM_InitStructure *initStruct) +{ + uint32_t i; + + // 配置SRAM前需要刷新下SDRAM控制器 + do + { + SYS->CLKEN |= (1 << SYS_CLKEN_SDRAM_Pos); + + while (SDRAMC->REFDONE == 0) + ; + SDRAMC->REFRESH &= ~(1 << SDRAMC_REFRESH_EN_Pos); + + for (i = 0; i < 1000; i++) + __NOP(); + SYS->CLKEN &= ~(1 << SYS_CLKEN_SDRAM_Pos); + } while (0); + + SYS->CLKEN |= (1 << SYS_CLKEN_RAMC_Pos); + for (i = 0; i < 10; i++) + __NOP(); + + SRAMC->CR = (initStruct->ClkDiv << SRAMC_CR_RWTIME_Pos) | + (initStruct->DataWidth << SRAMC_CR_BYTEIF_Pos) | + (0 << SRAMC_CR_HBLBDIS_Pos); // 使能字节、半字访问 +} diff --git a/bsp/swm320-lq100/Libraries/SWM320_StdPeriph_Driver/SWM320_sram.h b/bsp/swm320-lq100/Libraries/SWM320_StdPeriph_Driver/SWM320_sram.h new file mode 100644 index 0000000000..ca3aa92dcc --- /dev/null +++ b/bsp/swm320-lq100/Libraries/SWM320_StdPeriph_Driver/SWM320_sram.h @@ -0,0 +1,29 @@ +#ifndef __SWM320_SRAM_H__ +#define __SWM320_SRAM_H__ + +typedef struct +{ + uint8_t ClkDiv; //SRAM_CLKDIV_5...SRAM_CLKDIV_16，根据SRAM芯片所能跑的最高频率选择合适分频 + uint8_t DataWidth; //SRAM_DATAWIDTH_8、SRAM_DATAWIDTH_16 +} SRAM_InitStructure; + +#define SRAM_CLKDIV_4 3 +#define SRAM_CLKDIV_5 4 +#define SRAM_CLKDIV_6 5 +#define SRAM_CLKDIV_7 6 +#define SRAM_CLKDIV_8 7 +#define SRAM_CLKDIV_9 8 +#define SRAM_CLKDIV_10 9 +#define SRAM_CLKDIV_11 10 +#define SRAM_CLKDIV_12 11 +#define SRAM_CLKDIV_13 12 +#define SRAM_CLKDIV_14 13 +#define SRAM_CLKDIV_15 14 +#define SRAM_CLKDIV_16 15 + +#define SRAM_DATAWIDTH_8 1 +#define SRAM_DATAWIDTH_16 0 + +void SRAM_Init(SRAM_InitStructure *initStruct); + +#endif //__SWM320_SRAM_H__ diff --git a/bsp/swm320-lq100/Libraries/SWM320_StdPeriph_Driver/SWM320_timr.c b/bsp/swm320-lq100/Libraries/SWM320_StdPeriph_Driver/SWM320_timr.c index 769cc2e779..6e51b0b868 100644 --- a/bsp/swm320-lq100/Libraries/SWM320_StdPeriph_Driver/SWM320_timr.c +++ b/bsp/swm320-lq100/Libraries/SWM320_StdPeriph_Driver/SWM320_timr.c @@ -1,10 +1,10 @@ /****************************************************************************************************************************************** -* ļ: SWM320_timr.c -* ˵: SWM320Ƭļ/ʱ -* ֧: http://www.synwit.com.cn/e/tool/gbook/?bid=1 -* ע: -* 汾: V1.1.0 20171025 -* ¼: +* 文件名称: SWM320_timr.c +* 功能说明: SWM320单片机的计数器/定时器功能驱动库 +* 技术支持: http://www.synwit.com.cn/e/tool/gbook/?bid=1 +* 注意事项: +* 版本日期: V1.1.0 2017年10月25日 +* 升级记录: * * ******************************************************************************************************************************************* @@ -21,22 +21,21 @@ #include "SWM320.h" #include "SWM320_timr.h" - /****************************************************************************************************************************************** -* : TIMR_Init() -* ˵: TIMRʱ/ʼ -* : TIMR_TypeDef * TIMRx ָҪõĶʱЧֵTIMR0TIMR1TIMR2TIMR3TIMR4TIMR5 -* uint32_t mode TIMR_MODE_TIMER ʱģʽ TIMR_MODE_COUNTER ģʽ -* uint32_t period ʱ/ -* uint32_t int_en жʹ -* : -* ע: +* 函数名称: TIMR_Init() +* 功能说明: TIMR定时器/计数器初始化 +* 输 入: TIMR_TypeDef * TIMRx 指定要被设置的定时器，有效值包括TIMR0、TIMR1、TIMR2、TIMR3、TIMR4、TIMR5 +* uint32_t mode TIMR_MODE_TIMER 定时器模式 TIMR_MODE_COUNTER 计数器模式 +* uint32_t period 定时/计数周期 +* uint32_t int_en 中断使能 +* 输 出: 无 +* 注意事项: 无 ******************************************************************************************************************************************/ void TIMR_Init(TIMR_TypeDef *TIMRx, uint32_t mode, uint32_t period, uint32_t int_en) { SYS->CLKEN |= (0x01 << SYS_CLKEN_TIMR_Pos); - TIMR_Stop(TIMRx); //һЩؼĴֻڶʱֹͣʱ + TIMR_Stop(TIMRx); //一些关键寄存器只能在定时器停止时设置 TIMRx->CTRL &= ~TIMR_CTRL_CLKSRC_Msk; TIMRx->CTRL |= mode << TIMR_CTRL_CLKSRC_Pos; @@ -46,11 +45,12 @@ void TIMR_Init(TIMR_TypeDef *TIMRx, uint32_t mode, uint32_t period, uint32_t int switch ((uint32_t)TIMRx) { case ((uint32_t)TIMR0): - TIMRG->IF = (1 << TIMRG_IF_TIMR0_Pos); //ʹжǰжϱ־ + TIMRG->IF = (1 << TIMRG_IF_TIMR0_Pos); //使能中断前清除中断标志 TIMRG->IE &= ~TIMRG_IE_TIMR0_Msk; TIMRG->IE |= (int_en << TIMRG_IE_TIMR0_Pos); - if (int_en) NVIC_EnableIRQ(TIMR0_IRQn); + if (int_en) + NVIC_EnableIRQ(TIMR0_IRQn); break; case ((uint32_t)TIMR1): @@ -58,7 +58,8 @@ void TIMR_Init(TIMR_TypeDef *TIMRx, uint32_t mode, uint32_t period, uint32_t int TIMRG->IE &= ~TIMRG_IE_TIMR1_Msk; TIMRG->IE |= (int_en << TIMRG_IE_TIMR1_Pos); - if (int_en) NVIC_EnableIRQ(TIMR1_IRQn); + if (int_en) + NVIC_EnableIRQ(TIMR1_IRQn); break; case ((uint32_t)TIMR2): @@ -66,7 +67,8 @@ void TIMR_Init(TIMR_TypeDef *TIMRx, uint32_t mode, uint32_t period, uint32_t int TIMRG->IE &= ~TIMRG_IE_TIMR2_Msk; TIMRG->IE |= (int_en << TIMRG_IE_TIMR2_Pos); - if (int_en) NVIC_EnableIRQ(TIMR2_IRQn); + if (int_en) + NVIC_EnableIRQ(TIMR2_IRQn); break; case ((uint32_t)TIMR3): @@ -74,7 +76,8 @@ void TIMR_Init(TIMR_TypeDef *TIMRx, uint32_t mode, uint32_t period, uint32_t int TIMRG->IE &= ~TIMRG_IE_TIMR3_Msk; TIMRG->IE |= (int_en << TIMRG_IE_TIMR3_Pos); - if (int_en) NVIC_EnableIRQ(TIMR3_IRQn); + if (int_en) + NVIC_EnableIRQ(TIMR3_IRQn); break; case ((uint32_t)TIMR4): @@ -82,7 +85,8 @@ void TIMR_Init(TIMR_TypeDef *TIMRx, uint32_t mode, uint32_t period, uint32_t int TIMRG->IE &= ~TIMRG_IE_TIMR4_Msk; TIMRG->IE |= (int_en << TIMRG_IE_TIMR4_Pos); - if (int_en) NVIC_EnableIRQ(TIMR4_IRQn); + if (int_en) + NVIC_EnableIRQ(TIMR4_IRQn); break; case ((uint32_t)TIMR5): @@ -90,17 +94,18 @@ void TIMR_Init(TIMR_TypeDef *TIMRx, uint32_t mode, uint32_t period, uint32_t int TIMRG->IE &= ~TIMRG_IE_TIMR5_Msk; TIMRG->IE |= (int_en << TIMRG_IE_TIMR5_Pos); - if (int_en) NVIC_EnableIRQ(TIMR5_IRQn); + if (int_en) + NVIC_EnableIRQ(TIMR5_IRQn); break; } } /****************************************************************************************************************************************** -* : TIMR_Start() -* ˵: ʱӳʼֵʼʱ/ -* : TIMR_TypeDef * TIMRx ָҪõĶʱȡֵTIMR0TIMR1TIMR2TIMR3TIMR4TIMR5 -* : -* ע: +* 函数名称: TIMR_Start() +* 功能说明: 启动定时器，从初始值开始计时/计数 +* 输 入: TIMR_TypeDef * TIMRx 指定要被设置的定时器，可取值包括TIMR0、TIMR1、TIMR2、TIMR3、TIMR4、TIMR5 +* 输 出: 无 +* 注意事项: 无 ******************************************************************************************************************************************/ void TIMR_Start(TIMR_TypeDef *TIMRx) { @@ -108,11 +113,11 @@ void TIMR_Start(TIMR_TypeDef *TIMRx) } /****************************************************************************************************************************************** -* : TIMR_Stop() -* ˵: ֹͣʱ -* : TIMR_TypeDef * TIMRx ָҪõĶʱȡֵTIMR0TIMR1TIMR2TIMR3TIMR4TIMR5 -* : -* ע: +* 函数名称: TIMR_Stop() +* 功能说明: 停止定时器 +* 输 入: TIMR_TypeDef * TIMRx 指定要被设置的定时器，可取值包括TIMR0、TIMR1、TIMR2、TIMR3、TIMR4、TIMR5 +* 输 出: 无 +* 注意事项: 无 ******************************************************************************************************************************************/ void TIMR_Stop(TIMR_TypeDef *TIMRx) { @@ -120,11 +125,11 @@ void TIMR_Stop(TIMR_TypeDef *TIMRx) } /****************************************************************************************************************************************** -* : TIMR_Halt() -* ˵: ͣʱֲֵ -* : TIMR_TypeDef * TIMRx ָҪõĶʱȡֵTIMR0TIMR1TIMR2TIMR3TIMR4TIMR5 -* : -* ע: +* 函数名称: TIMR_Halt() +* 功能说明: 暂停定时器，计数值保持不变 +* 输 入: TIMR_TypeDef * TIMRx 指定要被设置的定时器，可取值包括TIMR0、TIMR1、TIMR2、TIMR3、TIMR4、TIMR5 +* 输 出: 无 +* 注意事项: 无 ******************************************************************************************************************************************/ void TIMR_Halt(TIMR_TypeDef *TIMRx) { @@ -157,11 +162,11 @@ void TIMR_Halt(TIMR_TypeDef *TIMRx) } /****************************************************************************************************************************************** -* : TIMR_Resume() -* ˵: ָʱͣ -* : TIMR_TypeDef * TIMRx ָҪõĶʱȡֵTIMR0TIMR1TIMR2TIMR3TIMR4TIMR5 -* : -* ע: +* 函数名称: TIMR_Resume() +* 功能说明: 恢复定时器，从暂停处继续计数 +* 输 入: TIMR_TypeDef * TIMRx 指定要被设置的定时器，可取值包括TIMR0、TIMR1、TIMR2、TIMR3、TIMR4、TIMR5 +* 输 出: 无 +* 注意事项: 无 ******************************************************************************************************************************************/ void TIMR_Resume(TIMR_TypeDef *TIMRx) { @@ -194,12 +199,12 @@ void TIMR_Resume(TIMR_TypeDef *TIMRx) } /****************************************************************************************************************************************** -* : TIMR_SetPeriod() -* ˵: öʱ/ -* : TIMR_TypeDef * TIMRx ָҪõĶʱȡֵTIMR0TIMR1TIMR2TIMR3TIMR4TIMR5 -* uint32_t period ʱ/ -* : -* ע: +* 函数名称: TIMR_SetPeriod() +* 功能说明: 设置定时/计数周期 +* 输 入: TIMR_TypeDef * TIMRx 指定要被设置的定时器，可取值包括TIMR0、TIMR1、TIMR2、TIMR3、TIMR4、TIMR5 +* uint32_t period 定时/计数周期 +* 输 出: 无 +* 注意事项: 无 ******************************************************************************************************************************************/ void TIMR_SetPeriod(TIMR_TypeDef *TIMRx, uint32_t period) { @@ -207,11 +212,11 @@ void TIMR_SetPeriod(TIMR_TypeDef *TIMRx, uint32_t period) } /****************************************************************************************************************************************** -* : TIMR_GetPeriod() -* ˵: ȡʱ/ -* : TIMR_TypeDef * TIMRx ָҪõĶʱȡֵTIMR0TIMR1TIMR2TIMR3TIMR4TIMR5 -* : uint32_t ǰʱ/ -* ע: +* 函数名称: TIMR_GetPeriod() +* 功能说明: 获取定时/计数周期 +* 输 入: TIMR_TypeDef * TIMRx 指定要被设置的定时器，可取值包括TIMR0、TIMR1、TIMR2、TIMR3、TIMR4、TIMR5 +* 输 出: uint32_t 当前定时/计数周期 +* 注意事项: 无 ******************************************************************************************************************************************/ uint32_t TIMR_GetPeriod(TIMR_TypeDef *TIMRx) { @@ -219,11 +224,11 @@ uint32_t TIMR_GetPeriod(TIMR_TypeDef *TIMRx) } /****************************************************************************************************************************************** -* : TIMR_GetCurValue() -* ˵: ȡǰֵ -* : TIMR_TypeDef * TIMRx ָҪõĶʱȡֵTIMR0TIMR1TIMR2TIMR3TIMR4TIMR5 -* : uint32_t ǰֵ -* ע: +* 函数名称: TIMR_GetCurValue() +* 功能说明: 获取当前计数值 +* 输 入: TIMR_TypeDef * TIMRx 指定要被设置的定时器，可取值包括TIMR0、TIMR1、TIMR2、TIMR3、TIMR4、TIMR5 +* 输 出: uint32_t 当前计数值 +* 注意事项: 无 ******************************************************************************************************************************************/ uint32_t TIMR_GetCurValue(TIMR_TypeDef *TIMRx) { @@ -231,11 +236,11 @@ uint32_t TIMR_GetCurValue(TIMR_TypeDef *TIMRx) } /****************************************************************************************************************************************** -* : TIMR_INTEn() -* ˵: ʹж -* : TIMR_TypeDef * TIMRx ָҪõĶʱȡֵTIMR0TIMR1TIMR2TIMR3TIMR4TIMR5 -* : -* ע: +* 函数名称: TIMR_INTEn() +* 功能说明: 使能中断 +* 输 入: TIMR_TypeDef * TIMRx 指定要被设置的定时器，可取值包括TIMR0、TIMR1、TIMR2、TIMR3、TIMR4、TIMR5 +* 输 出: 无 +* 注意事项: 无 ******************************************************************************************************************************************/ void TIMR_INTEn(TIMR_TypeDef *TIMRx) { @@ -274,11 +279,11 @@ void TIMR_INTEn(TIMR_TypeDef *TIMRx) } /****************************************************************************************************************************************** -* : TIMR_INTDis() -* ˵: ж -* : TIMR_TypeDef * TIMRx ָҪõĶʱȡֵTIMR0TIMR1TIMR2TIMR3TIMR4TIMR5 -* : -* ע: +* 函数名称: TIMR_INTDis() +* 功能说明: 禁能中断 +* 输 入: TIMR_TypeDef * TIMRx 指定要被设置的定时器，可取值包括TIMR0、TIMR1、TIMR2、TIMR3、TIMR4、TIMR5 +* 输 出: 无 +* 注意事项: 无 ******************************************************************************************************************************************/ void TIMR_INTDis(TIMR_TypeDef *TIMRx) { @@ -311,11 +316,11 @@ void TIMR_INTDis(TIMR_TypeDef *TIMRx) } /****************************************************************************************************************************************** -* : TIMR_INTClr() -* ˵: жϱ־ -* : TIMR_TypeDef * TIMRx ָҪõĶʱȡֵTIMR0TIMR1TIMR2TIMR3TIMR4TIMR5 -* : -* ע: +* 函数名称: TIMR_INTClr() +* 功能说明: 清除中断标志 +* 输 入: TIMR_TypeDef * TIMRx 指定要被设置的定时器，可取值包括TIMR0、TIMR1、TIMR2、TIMR3、TIMR4、TIMR5 +* 输 出: 无 +* 注意事项: 无 ******************************************************************************************************************************************/ void TIMR_INTClr(TIMR_TypeDef *TIMRx) { @@ -348,11 +353,11 @@ void TIMR_INTClr(TIMR_TypeDef *TIMRx) } /****************************************************************************************************************************************** -* : TIMR_INTStat() -* ˵: ȡж״̬ -* : TIMR_TypeDef * TIMRx ָҪõĶʱȡֵTIMR0TIMR1TIMR2TIMR3TIMR4TIMR5 -* : uint32_t 0 TIMRxδж 1 TIMRxж -* ע: +* 函数名称: TIMR_INTStat() +* 功能说明: 获取中断状态 +* 输 入: TIMR_TypeDef * TIMRx 指定要被设置的定时器，可取值包括TIMR0、TIMR1、TIMR2、TIMR3、TIMR4、TIMR5 +* 输 出: uint32_t 0 TIMRx未产生中断 1 TIMRx产生了中断 +* 注意事项: 无 ******************************************************************************************************************************************/ uint32_t TIMR_INTStat(TIMR_TypeDef *TIMRx) { @@ -379,3 +384,58 @@ uint32_t TIMR_INTStat(TIMR_TypeDef *TIMRx) return 0; } + +/****************************************************************************************************************************************** +* 函数名称: Pulse_Init() +* 功能说明: 脉宽测量功能初始化 +* 输 入: uint32_t pulse PULSE_LOW 测量低脉冲宽度 PULSE_HIGH 测量高脉冲宽度 +* uint32_t int_en 是否使能脉冲测量完成中断 +* 输 出: 无 +* 注意事项: 无 +******************************************************************************************************************************************/ +void Pulse_Init(uint32_t pulse, uint32_t int_en) +{ + SYS->CLKEN |= (0x01 << SYS_CLKEN_TIMR_Pos); + + TIMRG->PCTRL = (0 << TIMRG_PCTRL_CLKSRC_Pos) | // 系统时钟作为时钟源 + (pulse << TIMRG_PCTRL_HIGH_Pos) | + (0 << TIMRG_PCTRL_EN_Pos); + + TIMRG->IE |= (1 << TIMRG_IE_PULSE_Pos); //使能才能查询中断标志 + + if (int_en) + NVIC_EnableIRQ(PULSE_IRQn); +} + +/****************************************************************************************************************************************** +* 函数名称: Pulse_Start() +* 功能说明: 脉宽测量功能启动，测量到脉宽后会自动关闭测量功能 +* 输 入: 无 +* 输 出: 无 +* 注意事项: 无 +******************************************************************************************************************************************/ +void Pulse_Start(void) +{ + TIMRG->PCTRL |= (1 << TIMRG_PCTRL_EN_Pos); +} + +/****************************************************************************************************************************************** +* 函数名称: Pulse_Done() +* 功能说明: 脉宽测量是否完成 +* 输 入: 无 +* 输 出: uint32_t 1 测量已完成 0 测量未完成 +* 注意事项: 无 +******************************************************************************************************************************************/ +uint32_t Pulse_Done(void) +{ + if (TIMRG->IF & TIMRG_IF_PULSE_Msk) + { + TIMRG->IF = TIMRG_IF_PULSE_Msk; // 清除中断标志 + + return 1; + } + else + { + return 0; + } +} diff --git a/bsp/swm320-lq100/Libraries/SWM320_StdPeriph_Driver/SWM320_timr.h b/bsp/swm320-lq100/Libraries/SWM320_StdPeriph_Driver/SWM320_timr.h index f92c0eaa73..38eaffacd8 100644 --- a/bsp/swm320-lq100/Libraries/SWM320_StdPeriph_Driver/SWM320_timr.h +++ b/bsp/swm320-lq100/Libraries/SWM320_StdPeriph_Driver/SWM320_timr.h @@ -1,23 +1,29 @@ #ifndef __SWM320_TIMR_H__ #define __SWM320_TIMR_H__ -#define TIMR_MODE_TIMER 0 -#define TIMR_MODE_COUNTER 1 +#define TIMR_MODE_TIMER 0 +#define TIMR_MODE_COUNTER 1 -void TIMR_Init(TIMR_TypeDef *TIMRx, uint32_t mode, uint32_t period, uint32_t int_en); //ʱ/ʼ -void TIMR_Start(TIMR_TypeDef *TIMRx); //ʱӳʼֵʼʱ/ -void TIMR_Stop(TIMR_TypeDef *TIMRx); //ֹͣʱ -void TIMR_Halt(TIMR_TypeDef *TIMRx); //ͣʱֲֵ -void TIMR_Resume(TIMR_TypeDef *TIMRx); //ָʱͣ +void TIMR_Init(TIMR_TypeDef *TIMRx, uint32_t mode, uint32_t period, uint32_t int_en); //定时器/计数器初始化 +void TIMR_Start(TIMR_TypeDef *TIMRx); //启动定时器，从初始值开始计时/计数 +void TIMR_Stop(TIMR_TypeDef *TIMRx); //停止定时器 +void TIMR_Halt(TIMR_TypeDef *TIMRx); //暂停定时器，计数值保持不变 +void TIMR_Resume(TIMR_TypeDef *TIMRx); //恢复定时器，从暂停处继续计数 -void TIMR_SetPeriod(TIMR_TypeDef *TIMRx, uint32_t period); //öʱ/ -uint32_t TIMR_GetPeriod(TIMR_TypeDef *TIMRx); //ȡʱ/ -uint32_t TIMR_GetCurValue(TIMR_TypeDef *TIMRx); //ȡǰֵ +void TIMR_SetPeriod(TIMR_TypeDef *TIMRx, uint32_t period); //设置定时/计数周期 +uint32_t TIMR_GetPeriod(TIMR_TypeDef *TIMRx); //获取定时/计数周期 +uint32_t TIMR_GetCurValue(TIMR_TypeDef *TIMRx); //获取当前计数值 -void TIMR_INTEn(TIMR_TypeDef *TIMRx); //ʹж -void TIMR_INTDis(TIMR_TypeDef *TIMRx); //ж -void TIMR_INTClr(TIMR_TypeDef *TIMRx); //жϱ־ -uint32_t TIMR_INTStat(TIMR_TypeDef *TIMRx); //ȡж״̬ +void TIMR_INTEn(TIMR_TypeDef *TIMRx); //使能中断 +void TIMR_INTDis(TIMR_TypeDef *TIMRx); //禁能中断 +void TIMR_INTClr(TIMR_TypeDef *TIMRx); //清除中断标志 +uint32_t TIMR_INTStat(TIMR_TypeDef *TIMRx); //获取中断状态 +#define PULSE_LOW 0 +#define PULSE_HIGH 1 + +void Pulse_Init(uint32_t pulse, uint32_t int_en); +void Pulse_Start(void); +uint32_t Pulse_Done(void); #endif //__SWM320_TIMR_H__ diff --git a/bsp/swm320-lq100/Libraries/SWM320_StdPeriph_Driver/SWM320_uart.c b/bsp/swm320-lq100/Libraries/SWM320_StdPeriph_Driver/SWM320_uart.c index 46242efa01..c60b7fa825 100644 --- a/bsp/swm320-lq100/Libraries/SWM320_StdPeriph_Driver/SWM320_uart.c +++ b/bsp/swm320-lq100/Libraries/SWM320_StdPeriph_Driver/SWM320_uart.c @@ -1,10 +1,10 @@ /****************************************************************************************************************************************** -* ļ: SWM320_uart.c -* ˵: SWM320ƬUARTڹ -* ֧: http://www.synwit.com.cn/e/tool/gbook/?bid=1 -* ע: ûбдLINصĺ -* 汾: V1.1.0 20171025 -* ¼: +* 文件名称: SWM320_uart.c +* 功能说明: SWM320单片机的UART串口功能驱动库 +* 技术支持: http://www.synwit.com.cn/e/tool/gbook/?bid=1 +* 注意事项: 没有编写LIN功能相关的函数 +* 版本日期: V1.1.0 2017年10月25日 +* 升级记录: * * ******************************************************************************************************************************************* @@ -21,14 +21,13 @@ #include "SWM320.h" #include "SWM320_uart.h" - /****************************************************************************************************************************************** -* : UART_Init() -* ˵: UARTڳʼ -* : UART_TypeDef * UARTx ָҪõUARTڣЧֵUART0UART1UART2UART3 -* UART_InitStructure * initStruct UART趨ֵĽṹ -* : -* ע: +* 函数名称: UART_Init() +* 功能说明: UART串口初始化 +* 输 入: UART_TypeDef * UARTx 指定要被设置的UART串口，有效值包括UART0、UART1、UART2、UART3 +* UART_InitStructure * initStruct 包含UART串口相关设定值的结构体 +* 输 出: 无 +* 注意事项: 无 ******************************************************************************************************************************************/ void UART_Init(UART_TypeDef *UARTx, UART_InitStructure *initStruct) { @@ -51,7 +50,7 @@ void UART_Init(UART_TypeDef *UARTx, UART_InitStructure *initStruct) break; } - UART_Close(UARTx); //һЩؼĴֻڴڹرʱ + UART_Close(UARTx); //一些关键寄存器只能在串口关闭时设置 UARTx->CTRL |= (0x01 << UART_CTRL_BAUDEN_Pos); UARTx->BAUD &= ~UART_BAUD_BAUD_Msk; @@ -59,11 +58,29 @@ void UART_Init(UART_TypeDef *UARTx, UART_InitStructure *initStruct) UARTx->CTRL &= ~(UART_CTRL_DATA9b_Msk | UART_CTRL_PARITY_Msk | UART_CTRL_STOP2b_Msk); UARTx->CTRL |= (initStruct->DataBits << UART_CTRL_DATA9b_Pos) | - (initStruct->Parity << UART_CTRL_PARITY_Pos) | + (initStruct->Parity << UART_CTRL_PARITY_Pos) | (initStruct->StopBits << UART_CTRL_STOP2b_Pos); + /* 在SWM320中，当 RXLVL >= RXTHR 时触发中断，如果RXTHR设置为0的话，在未接收到数据时就会一直触发中断； + 其他芯片中，当 RXLVL > RXTHR 时触发中断，为解决SWM320中RXTHR不能为0的问题，并统一库函数API，这里将RXTHR设置值加一 + */ + switch ((uint32_t)UARTx) // 软件复位不能清零 NVIC 寄存器，若不手动清除，下面的代码清零 RXTHR 时会导致一直进入 ISR + { + case ((uint32_t)UART0): + NVIC_DisableIRQ(UART0_IRQn); + break; + case ((uint32_t)UART1): + NVIC_DisableIRQ(UART1_IRQn); + break; + case ((uint32_t)UART2): + NVIC_DisableIRQ(UART2_IRQn); + break; + case ((uint32_t)UART3): + NVIC_DisableIRQ(UART3_IRQn); + break; + } UARTx->FIFO &= ~(UART_FIFO_RXTHR_Msk | UART_FIFO_TXTHR_Msk); - UARTx->FIFO |= (initStruct->RXThreshold << UART_FIFO_RXTHR_Pos) | + UARTx->FIFO |= ((initStruct->RXThreshold + 1) << UART_FIFO_RXTHR_Pos) | (initStruct->TXThreshold << UART_FIFO_TXTHR_Pos); UARTx->CTRL &= ~UART_CTRL_TOTIME_Msk; @@ -123,11 +140,11 @@ void UART_Init(UART_TypeDef *UARTx, UART_InitStructure *initStruct) } /****************************************************************************************************************************************** -* : UART_Open() -* ˵: UARTڴ -* : UART_TypeDef * UARTx ָҪõUARTڣЧֵUART0UART1UART2UART3 -* : -* ע: +* 函数名称: UART_Open() +* 功能说明: UART串口打开 +* 输 入: UART_TypeDef * UARTx 指定要被设置的UART串口，有效值包括UART0、UART1、UART2、UART3 +* 输 出: 无 +* 注意事项: 无 ******************************************************************************************************************************************/ void UART_Open(UART_TypeDef *UARTx) { @@ -135,11 +152,11 @@ void UART_Open(UART_TypeDef *UARTx) } /****************************************************************************************************************************************** -* : UART_Close() -* ˵: UARTڹر -* : UART_TypeDef * UARTx ָҪõUARTڣЧֵUART0UART1UART2UART3 -* : -* ע: +* 函数名称: UART_Close() +* 功能说明: UART串口关闭 +* 输 入: UART_TypeDef * UARTx 指定要被设置的UART串口，有效值包括UART0、UART1、UART2、UART3 +* 输 出: 无 +* 注意事项: 无 ******************************************************************************************************************************************/ void UART_Close(UART_TypeDef *UARTx) { @@ -147,25 +164,25 @@ void UART_Close(UART_TypeDef *UARTx) } /****************************************************************************************************************************************** -* : UART_WriteByte() -* ˵: һֽ -* : UART_TypeDef * UARTx ָҪõUARTڣȡֵUART0UART1UART2UART3UART4 -* uint8_t data Ҫ͵ֽ -* : -* ע: +* 函数名称: UART_WriteByte() +* 功能说明: 发送一个字节数据 +* 输 入: UART_TypeDef * UARTx 指定要被设置的UART串口，可取值包括UART0、UART1、UART2、UART3、UART4 +* uint32_t data 要发送的字节 +* 输 出: 无 +* 注意事项: 无 ******************************************************************************************************************************************/ -void UART_WriteByte(UART_TypeDef *UARTx, uint8_t data) +void UART_WriteByte(UART_TypeDef *UARTx, uint32_t data) { UARTx->DATA = data; } /****************************************************************************************************************************************** -* : UART_ReadByte() -* ˵: ȡһֽݣָǷValid -* : UART_TypeDef * UARTx ָҪõUARTڣȡֵUART0UART1UART2UART3UART4 -* uint32_t * data յ -* : uint32_t 0 ޴ UART_ERR_PARITY żУ -* ע: +* 函数名称: UART_ReadByte() +* 功能说明: 读取一个字节数据，并指出数据是否Valid +* 输 入: UART_TypeDef * UARTx 指定要被设置的UART串口，可取值包括UART0、UART1、UART2、UART3、UART4 +* uint32_t * data 接收到的数据 +* 输 出: uint32_t 0 无错误 UART_ERR_PARITY 奇偶校验错误 +* 注意事项: 无 ******************************************************************************************************************************************/ uint32_t UART_ReadByte(UART_TypeDef *UARTx, uint32_t *data) { @@ -173,17 +190,18 @@ uint32_t UART_ReadByte(UART_TypeDef *UARTx, uint32_t *data) *data = (reg & UART_DATA_DATA_Msk); - if (reg & UART_DATA_PAERR_Msk) return UART_ERR_PARITY; + if (reg & UART_DATA_PAERR_Msk) + return UART_ERR_PARITY; return 0; } /****************************************************************************************************************************************** -* : UART_IsTXBusy() -* ˵: UARTǷڷ -* : UART_TypeDef * UARTx ָҪõUARTڣЧֵUART0UART1UART2UART3 -* : uint32_t 1 UARTڷ 0 ѷ -* ע: +* 函数名称: UART_IsTXBusy() +* 功能说明: UART是否正在发送数据 +* 输 入: UART_TypeDef * UARTx 指定要被设置的UART串口，有效值包括UART0、UART1、UART2、UART3 +* 输 出: uint32_t 1 UART正在发送数据 0 数据已发完 +* 注意事项: 无 ******************************************************************************************************************************************/ uint32_t UART_IsTXBusy(UART_TypeDef *UARTx) { @@ -191,11 +209,11 @@ uint32_t UART_IsTXBusy(UART_TypeDef *UARTx) } /****************************************************************************************************************************************** -* : UART_IsRXFIFOEmpty() -* ˵: FIFOǷΪգ˵ݿԶȡ -* : UART_TypeDef * UARTx ָҪõUARTڣЧֵUART0UART1UART2UART3 -* : uint32_t 1 FIFO 0 FIFOǿ -* ע: +* 函数名称: UART_IsRXFIFOEmpty() +* 功能说明: 接收FIFO是否为空，如果不空则说明其中有数据可以读取 +* 输 入: UART_TypeDef * UARTx 指定要被设置的UART串口，有效值包括UART0、UART1、UART2、UART3 +* 输 出: uint32_t 1 接收FIFO空 0 接收FIFO非空 +* 注意事项: 无 ******************************************************************************************************************************************/ uint32_t UART_IsRXFIFOEmpty(UART_TypeDef *UARTx) { @@ -203,11 +221,11 @@ uint32_t UART_IsRXFIFOEmpty(UART_TypeDef *UARTx) } /****************************************************************************************************************************************** -* : UART_IsTXFIFOFull() -* ˵: FIFOǷΪԼд -* : UART_TypeDef * UARTx ָҪõUARTڣЧֵUART0UART1UART2UART3 -* : uint32_t 1 FIFO 0 FIFO -* ע: +* 函数名称: UART_IsTXFIFOFull() +* 功能说明: 发送FIFO是否为满，如果不满则可以继续向其中写入数据 +* 输 入: UART_TypeDef * UARTx 指定要被设置的UART串口，有效值包括UART0、UART1、UART2、UART3 +* 输 出: uint32_t 1 发送FIFO满 0 发送FIFO不满 +* 注意事项: 无 ******************************************************************************************************************************************/ uint32_t UART_IsTXFIFOFull(UART_TypeDef *UARTx) { @@ -215,53 +233,53 @@ uint32_t UART_IsTXFIFOFull(UART_TypeDef *UARTx) } /****************************************************************************************************************************************** -* : UART_SetBaudrate() -* ˵: ò -* : UART_TypeDef * UARTx ָҪõUARTڣЧֵUART0UART1UART2UART3 -* uint32_t baudrate ҪõIJ -* : -* ע: ҪڴڹʱIJʣʹô˺ǰȵUART_Close()رմ +* 函数名称: UART_SetBaudrate() +* 功能说明: 设置波特率 +* 输 入: UART_TypeDef * UARTx 指定要被设置的UART串口，有效值包括UART0、UART1、UART2、UART3 +* uint32_t baudrate 要设置的波特率 +* 输 出: 无 +* 注意事项: 不要在串口工作时更改波特率，使用此函数前请先调用UART_Close()关闭串口 ******************************************************************************************************************************************/ void UART_SetBaudrate(UART_TypeDef *UARTx, uint32_t baudrate) { UARTx->BAUD &= ~UART_BAUD_BAUD_Msk; - UARTx->BAUD |= ((SystemCoreClock / 16 / baudrate) << UART_BAUD_BAUD_Pos); + UARTx->BAUD |= ((SystemCoreClock / 16 / baudrate - 1) << UART_BAUD_BAUD_Pos); } /****************************************************************************************************************************************** -* : UART_GetBaudrate() -* ˵: ѯ -* : UART_TypeDef * UARTx ָҪõUARTڣЧֵUART0UART1UART2UART3 -* : uint32_t ǰ -* ע: +* 函数名称: UART_GetBaudrate() +* 功能说明: 查询波特率 +* 输 入: UART_TypeDef * UARTx 指定要被设置的UART串口，有效值包括UART0、UART1、UART2、UART3 +* 输 出: uint32_t 当前波特率 +* 注意事项: 无 ******************************************************************************************************************************************/ uint32_t UART_GetBaudrate(UART_TypeDef *UARTx) { - return (UARTx->BAUD & UART_BAUD_BAUD_Msk); + return SystemCoreClock / 16 / (((UARTx->BAUD & UART_BAUD_BAUD_Msk) >> UART_BAUD_BAUD_Pos) + 1); } /****************************************************************************************************************************************** -* : UART_CTSConfig() -* ˵: UART CTS -* : UART_TypeDef * UARTx ָҪõUARTڣЧֵUART0UART1UART2UART3 -* uint32_t enable 1 ʹCTS 0 ֹCTS -* uint32_t polarity 0 CTSΪͱʾԷ 1 CTSΪ߱ʾԷ -* : -* ע: +* 函数名称: UART_CTSConfig() +* 功能说明: UART CTS流控配置 +* 输 入: UART_TypeDef * UARTx 指定要被设置的UART串口，有效值包括UART0、UART1、UART2、UART3 +* uint32_t enable 1 使能CTS流控 0 禁止CTS流控 +* uint32_t polarity 0 CTS输入为低表示可以发送数据 1 CTS输入为高表示可以发送数据 +* 输 出: 无 +* 注意事项: 无 ******************************************************************************************************************************************/ void UART_CTSConfig(UART_TypeDef *UARTx, uint32_t enable, uint32_t polarity) { UARTx->CTSCR &= ~(UART_CTSCR_EN_Msk | UART_CTSCR_POL_Msk); - UARTx->CTSCR |= (enable << UART_CTSCR_EN_Pos) | + UARTx->CTSCR |= (enable << UART_CTSCR_EN_Pos) | (polarity << UART_CTSCR_POL_Pos); } /****************************************************************************************************************************************** -* : UART_CTSLineState() -* ˵: UART CTSߵǰ״̬ -* : UART_TypeDef * UARTx ָҪõUARTڣЧֵUART0UART1UART2UART3 -* : uint32_t 0 CTSߵǰΪ͵ƽ 1 CTSߵǰΪߵƽ -* ע: +* 函数名称: UART_CTSLineState() +* 功能说明: UART CTS线当前状态 +* 输 入: UART_TypeDef * UARTx 指定要被设置的UART串口，有效值包括UART0、UART1、UART2、UART3 +* 输 出: uint32_t 0 CTS线当前为低电平 1 CTS线当前为高电平 +* 注意事项: 无 ******************************************************************************************************************************************/ uint32_t UART_CTSLineState(UART_TypeDef *UARTx) { @@ -269,29 +287,29 @@ uint32_t UART_CTSLineState(UART_TypeDef *UARTx) } /****************************************************************************************************************************************** -* : UART_RTSConfig() -* ˵: UART RTS -* : UART_TypeDef * UARTx ָҪõUARTڣЧֵUART0UART1UART2UART3 -* uint32_t enable 1 ʹRTS 0 ֹRTS -* uint32_t polarity 0 RTSͱʾԽ 1 RTS߱ʾԽ -* uint32_t threshold RTSصĴֵȡֵUART_RTS_1BYTEUART_RTS_2BYTEUART_RTS_4BYTEUART_RTS_6BYTE -* : -* ע: +* 函数名称: UART_RTSConfig() +* 功能说明: UART RTS流控配置 +* 输 入: UART_TypeDef * UARTx 指定要被设置的UART串口，有效值包括UART0、UART1、UART2、UART3 +* uint32_t enable 1 使能RTS流控 0 禁止RTS流控 +* uint32_t polarity 0 RTS输出低表示可以接收数据 1 RTS输出高表示可以接收数据 +* uint32_t threshold RTS流控的触发阈值，可取值UART_RTS_1BYTE、UART_RTS_2BYTE、UART_RTS_4BYTE、UART_RTS_6BYTE +* 输 出: 无 +* 注意事项: 无 ******************************************************************************************************************************************/ void UART_RTSConfig(UART_TypeDef *UARTx, uint32_t enable, uint32_t polarity, uint32_t threshold) { UARTx->RTSCR &= ~(UART_RTSCR_EN_Msk | UART_RTSCR_POL_Msk | UART_RTSCR_THR_Msk); - UARTx->RTSCR |= (enable << UART_RTSCR_EN_Pos) | - (polarity << UART_RTSCR_POL_Pos) | + UARTx->RTSCR |= (enable << UART_RTSCR_EN_Pos) | + (polarity << UART_RTSCR_POL_Pos) | (threshold << UART_RTSCR_THR_Pos); } /****************************************************************************************************************************************** -* : UART_RTSLineState() -* ˵: UART RTSߵǰ״̬ -* : UART_TypeDef * UARTx ָҪõUARTڣЧֵUART0UART1UART2UART3 -* : uint32_t 0 RTSߵǰΪ͵ƽ 1 RTSߵǰΪߵƽ -* ע: +* 函数名称: UART_RTSLineState() +* 功能说明: UART RTS线当前状态 +* 输 入: UART_TypeDef * UARTx 指定要被设置的UART串口，有效值包括UART0、UART1、UART2、UART3 +* 输 出: uint32_t 0 RTS线当前为低电平 1 RTS线当前为高电平 +* 注意事项: 无 ******************************************************************************************************************************************/ uint32_t UART_RTSLineState(UART_TypeDef *UARTx) { @@ -299,27 +317,27 @@ uint32_t UART_RTSLineState(UART_TypeDef *UARTx) } /****************************************************************************************************************************************** -* : UART_LINConfig() -* ˵: UART LIN -* : UART_TypeDef * UARTx ָҪõUARTڣЧֵUART0UART1UART2UART3 -* uint32_t detectedIEn ⵽Breakжʹ -* uint32_t generatedIEn Breakжʹ -* : -* ע: +* 函数名称: UART_LINConfig() +* 功能说明: UART LIN功能配置 +* 输 入: UART_TypeDef * UARTx 指定要被设置的UART串口，有效值包括UART0、UART1、UART2、UART3 +* uint32_t detectedIEn 检测到Break中断使能 +* uint32_t generatedIEn Break发送完成中断使能 +* 输 出: 无 +* 注意事项: 无 ******************************************************************************************************************************************/ void UART_LINConfig(UART_TypeDef *UARTx, uint32_t detectedIEn, uint32_t generatedIEn) { UARTx->LINCR &= ~(UART_LINCR_BRKDETIE_Msk | UART_LINCR_GENBRKIE_Msk); - UARTx->LINCR |= (detectedIEn << UART_LINCR_BRKDETIE_Pos) | + UARTx->LINCR |= (detectedIEn << UART_LINCR_BRKDETIE_Pos) | (generatedIEn << UART_LINCR_GENBRKIE_Pos); } /****************************************************************************************************************************************** -* : UART_LINGenerate() -* ˵: UART LIN/Break -* : UART_TypeDef * UARTx ָҪõUARTڣЧֵUART0UART1UART2UART3 -* : -* ע: +* 函数名称: UART_LINGenerate() +* 功能说明: UART LIN产生/发送Break +* 输 入: UART_TypeDef * UARTx 指定要被设置的UART串口，有效值包括UART0、UART1、UART2、UART3 +* 输 出: 无 +* 注意事项: 无 ******************************************************************************************************************************************/ void UART_LINGenerate(UART_TypeDef *UARTx) { @@ -327,23 +345,23 @@ void UART_LINGenerate(UART_TypeDef *UARTx) } /****************************************************************************************************************************************** -* : UART_LINIsDetected() -* ˵: UART LINǷ⵽Break -* : UART_TypeDef * UARTx ָҪõUARTڣЧֵUART0UART1UART2UART3 -* : uint32_t 1 ⵽LIN Break 0 δ⵽LIN Break -* ע: +* 函数名称: UART_LINIsDetected() +* 功能说明: UART LIN是否检测到Break +* 输 入: UART_TypeDef * UARTx 指定要被设置的UART串口，有效值包括UART0、UART1、UART2、UART3 +* 输 出: uint32_t 1 检测到LIN Break 0 未检测到LIN Break +* 注意事项: 无 ******************************************************************************************************************************************/ uint32_t UART_LINIsDetected(UART_TypeDef *UARTx) { - return (UARTx->LINCR & UART_LINCR_BRKDETIE_Msk) ? 1 : 0; + return (UARTx->LINCR & UART_LINCR_BRKDETIF_Msk) ? 1 : 0; } /****************************************************************************************************************************************** -* : UART_LINIsGenerated() -* ˵: UART LIN BreakǷ -* : UART_TypeDef * UARTx ָҪõUARTڣЧֵUART0UART1UART2UART3 -* : uint32_t 1 LIN Break 0 LIN Breakδ -* ע: +* 函数名称: UART_LINIsGenerated() +* 功能说明: UART LIN Break是否发送完成 +* 输 入: UART_TypeDef * UARTx 指定要被设置的UART串口，有效值包括UART0、UART1、UART2、UART3 +* 输 出: uint32_t 1 LIN Break 发送完成 0 LIN Break发送未完成 +* 注意事项: 无 ******************************************************************************************************************************************/ uint32_t UART_LINIsGenerated(UART_TypeDef *UARTx) { @@ -351,36 +369,42 @@ uint32_t UART_LINIsGenerated(UART_TypeDef *UARTx) } /****************************************************************************************************************************************** -* : UART_ABRStart() -* ˵: UART Զʼ⿪ʼ -* : UART_TypeDef * UARTx ָҪõUARTڣЧֵUART0UART1UART2UART3 -* uint32_t detectChar Զ⡢㲨ʵļַ -* 8λʱȡֵ0xFF0xFE0xF80x80ֱʾͷ뷢0xFF0xFE0xF80x80 -* 9λʱȡֵ0x1FF0x1FE0x1F80x180ֱʾͷ뷢0x1FF0x1FE0x1F80x180 -* : -* ע: ԶʼʱܿżУ +* 函数名称: UART_ABRStart() +* 功能说明: UART 自动波特率检测开始 +* 输 入: UART_TypeDef * UARTx 指定要被设置的UART串口，有效值包括UART0、UART1、UART2、UART3 +* uint32_t detectChar 用于自动检测、计算波特率的检测字符 +* 8位数据时可取值：0xFF、0xFE、0xF8、0x80，分别表示发送方必须发送0xFF、0xFE、0xF8、0x80 +* 9位数据时可取值：0x1FF、0x1FE、0x1F8、0x180，分别表示发送方必须发送0x1FF、0x1FE、0x1F8、0x180 +* 输 出: 无 +* 注意事项: 自动波特率检测时不能开启奇偶校验 ******************************************************************************************************************************************/ void UART_ABRStart(UART_TypeDef *UARTx, uint32_t detectChar) { uint32_t bits; - if ((detectChar == 0xFF) || (detectChar == 0x1FF)) bits = 0; - else if ((detectChar == 0xFE) || (detectChar == 0x1FE)) bits = 1; - else if ((detectChar == 0xF8) || (detectChar == 0x1F8)) bits = 2; - else if ((detectChar == 0x80) || (detectChar == 0x180)) bits = 3; - else while (1); + if ((detectChar == 0xFF) || (detectChar == 0x1FF)) + bits = 0; + else if ((detectChar == 0xFE) || (detectChar == 0x1FE)) + bits = 1; + else if ((detectChar == 0xF8) || (detectChar == 0x1F8)) + bits = 2; + else if ((detectChar == 0x80) || (detectChar == 0x180)) + bits = 3; + else + while (1) + ; UARTx->BAUD &= ~(UART_BAUD_ABREN_Msk | UART_BAUD_ABRBIT_Msk); - UARTx->BAUD |= (1 << UART_BAUD_ABREN_Pos) | + UARTx->BAUD |= (1 << UART_BAUD_ABREN_Pos) | (bits << UART_BAUD_ABRBIT_Pos); } /****************************************************************************************************************************************** -* : UART_ABRIsDone() -* ˵: UART ԶǷ -* : UART_TypeDef * UARTx ָҪõUARTڣЧֵUART0UART1UART2UART3 -* : uint32_t 0 δ UART_ABR_RES_OK ɣҳɹ UART_ABR_RES_ERR ɣʧܡ -* ע: +* 函数名称: UART_ABRIsDone() +* 功能说明: UART 自动波特率是否完成 +* 输 入: UART_TypeDef * UARTx 指定要被设置的UART串口，有效值包括UART0、UART1、UART2、UART3 +* 输 出: uint32_t 0 未完成 UART_ABR_RES_OK 已完成，且成功 UART_ABR_RES_ERR 已完成，但失败、出错 +* 注意事项: 无 ******************************************************************************************************************************************/ uint32_t UART_ABRIsDone(UART_TypeDef *UARTx) { @@ -399,11 +423,11 @@ uint32_t UART_ABRIsDone(UART_TypeDef *UARTx) } /****************************************************************************************************************************************** -* : UART_INTRXThresholdEn() -* ˵: RX FIFOݸ >= RXThresholdʱ ж -* : UART_TypeDef * UARTx ָҪõUARTڣЧֵUART0UART1UART2UART3 -* : -* ע: +* 函数名称: UART_INTRXThresholdEn() +* 功能说明: 当RX FIFO中数据个数 >= RXThreshold时 触发中断 +* 输 入: UART_TypeDef * UARTx 指定要被设置的UART串口，有效值包括UART0、UART1、UART2、UART3 +* 输 出: 无 +* 注意事项: 无 ******************************************************************************************************************************************/ void UART_INTRXThresholdEn(UART_TypeDef *UARTx) { @@ -411,11 +435,11 @@ void UART_INTRXThresholdEn(UART_TypeDef *UARTx) } /****************************************************************************************************************************************** -* : UART_INTRXThresholdDis() -* ˵: RX FIFOݸ >= RXThresholdʱ ж -* : UART_TypeDef * UARTx ָҪõUARTڣЧֵUART0UART1UART2UART3 -* : -* ע: +* 函数名称: UART_INTRXThresholdDis() +* 功能说明: 当RX FIFO中数据个数 >= RXThreshold时 不触发中断 +* 输 入: UART_TypeDef * UARTx 指定要被设置的UART串口，有效值包括UART0、UART1、UART2、UART3 +* 输 出: 无 +* 注意事项: 无 ******************************************************************************************************************************************/ void UART_INTRXThresholdDis(UART_TypeDef *UARTx) { @@ -423,11 +447,11 @@ void UART_INTRXThresholdDis(UART_TypeDef *UARTx) } /****************************************************************************************************************************************** -* : UART_INTRXThresholdStat() -* ˵: ǷRX FIFOݸ >= RXThreshold -* : UART_TypeDef * UARTx ָҪõUARTڣЧֵUART0UART1UART2UART3 -* : uint32_t 1 RX FIFOݸ >= RXThreshold 0 RX FIFOݸ < RXThreshold -* ע: RXIF = RXTHRF & RXIE +* 函数名称: UART_INTRXThresholdStat() +* 功能说明: 是否RX FIFO中数据个数 >= RXThreshold +* 输 入: UART_TypeDef * UARTx 指定要被设置的UART串口，有效值包括UART0、UART1、UART2、UART3 +* 输 出: uint32_t 1 RX FIFO中数据个数 >= RXThreshold 0 RX FIFO中数据个数 < RXThreshold +* 注意事项: RXIF = RXTHRF & RXIE ******************************************************************************************************************************************/ uint32_t UART_INTRXThresholdStat(UART_TypeDef *UARTx) { @@ -435,11 +459,11 @@ uint32_t UART_INTRXThresholdStat(UART_TypeDef *UARTx) } /****************************************************************************************************************************************** -* : UART_INTTXThresholdEn() -* ˵: TX FIFOݸ <= TXThresholdʱ ж -* : UART_TypeDef * UARTx ָҪõUARTڣЧֵUART0UART1UART2UART3 -* : -* ע: +* 函数名称: UART_INTTXThresholdEn() +* 功能说明: 当TX FIFO中数据个数 <= TXThreshold时 触发中断 +* 输 入: UART_TypeDef * UARTx 指定要被设置的UART串口，有效值包括UART0、UART1、UART2、UART3 +* 输 出: 无 +* 注意事项: 无 ******************************************************************************************************************************************/ void UART_INTTXThresholdEn(UART_TypeDef *UARTx) { @@ -447,11 +471,11 @@ void UART_INTTXThresholdEn(UART_TypeDef *UARTx) } /****************************************************************************************************************************************** -* : UART_INTTXThresholdDis() -* ˵: TX FIFOݸ <= TXThresholdʱ ж -* : UART_TypeDef * UARTx ָҪõUARTڣЧֵUART0UART1UART2UART3 -* : -* ע: +* 函数名称: UART_INTTXThresholdDis() +* 功能说明: 当TX FIFO中数据个数 <= TXThreshold时 不触发中断 +* 输 入: UART_TypeDef * UARTx 指定要被设置的UART串口，有效值包括UART0、UART1、UART2、UART3 +* 输 出: 无 +* 注意事项: 无 ******************************************************************************************************************************************/ void UART_INTTXThresholdDis(UART_TypeDef *UARTx) { @@ -459,11 +483,11 @@ void UART_INTTXThresholdDis(UART_TypeDef *UARTx) } /****************************************************************************************************************************************** -* : UART_INTTXThresholdStat() -* ˵: ǷTX FIFOݸ <= TXThreshold -* : UART_TypeDef * UARTx ָҪõUARTڣЧֵUART0UART1UART2UART3 -* : uint32_t 1 TX FIFOݸ <= TXThreshold 0 TX FIFOݸ > TXThreshold -* ע: TXIF = TXTHRF & TXIE +* 函数名称: UART_INTTXThresholdStat() +* 功能说明: 是否TX FIFO中数据个数 <= TXThreshold +* 输 入: UART_TypeDef * UARTx 指定要被设置的UART串口，有效值包括UART0、UART1、UART2、UART3 +* 输 出: uint32_t 1 TX FIFO中数据个数 <= TXThreshold 0 TX FIFO中数据个数 > TXThreshold +* 注意事项: TXIF = TXTHRF & TXIE ******************************************************************************************************************************************/ uint32_t UART_INTTXThresholdStat(UART_TypeDef *UARTx) { @@ -471,11 +495,11 @@ uint32_t UART_INTTXThresholdStat(UART_TypeDef *UARTx) } /****************************************************************************************************************************************** -* : UART_INTTimeoutEn() -* ˵: շʱʱ ж -* : UART_TypeDef * UARTx ָҪõUARTڣЧֵUART0UART1UART2UART3 -* : -* ע: +* 函数名称: UART_INTTimeoutEn() +* 功能说明: 接收发生超时时 触发中断 +* 输 入: UART_TypeDef * UARTx 指定要被设置的UART串口，有效值包括UART0、UART1、UART2、UART3 +* 输 出: 无 +* 注意事项: 无 ******************************************************************************************************************************************/ void UART_INTTimeoutEn(UART_TypeDef *UARTx) { @@ -483,11 +507,11 @@ void UART_INTTimeoutEn(UART_TypeDef *UARTx) } /****************************************************************************************************************************************** -* : UART_INTTimeoutDis() -* ˵: շʱʱ ж -* : UART_TypeDef * UARTx ָҪõUARTڣЧֵUART0UART1UART2UART3 -* : -* ע: +* 函数名称: UART_INTTimeoutDis() +* 功能说明: 接收发生超时时 不触发中断 +* 输 入: UART_TypeDef * UARTx 指定要被设置的UART串口，有效值包括UART0、UART1、UART2、UART3 +* 输 出: 无 +* 注意事项: 无 ******************************************************************************************************************************************/ void UART_INTTimeoutDis(UART_TypeDef *UARTx) { @@ -495,11 +519,11 @@ void UART_INTTimeoutDis(UART_TypeDef *UARTx) } /****************************************************************************************************************************************** -* : UART_INTTimeoutStat() -* ˵: Ƿ˽ճʱ TimeoutTime/(Baudrate/10) ûRXϽյʱж -* : UART_TypeDef * UARTx ָҪõUARTڣЧֵUART0UART1UART2UART3 -* : uint32_t 1 ˽ճʱ 0 δճʱ -* ע: +* 函数名称: UART_INTTimeoutStat() +* 功能说明: 是否发生了接收超时，即超过 TimeoutTime/(Baudrate/10) 秒没有在RX线上接收到数据时触发中断 +* 输 入: UART_TypeDef * UARTx 指定要被设置的UART串口，有效值包括UART0、UART1、UART2、UART3 +* 输 出: uint32_t 1 发生了接收超时 0 未发生接收超时 +* 注意事项: 无 ******************************************************************************************************************************************/ uint32_t UART_INTTimeoutStat(UART_TypeDef *UARTx) { @@ -507,11 +531,11 @@ uint32_t UART_INTTimeoutStat(UART_TypeDef *UARTx) } /****************************************************************************************************************************************** -* : UART_INTTXDoneEn() -* ˵: FIFOҷλĴжʹ -* : UART_TypeDef * UARTx ָҪõUARTڣЧֵUART0UART1UART2UART3 -* : -* ע: +* 函数名称: UART_INTTXDoneEn() +* 功能说明: 发送FIFO空且发送移位寄存器空中断使能 +* 输 入: UART_TypeDef * UARTx 指定要被设置的UART串口，有效值包括UART0、UART1、UART2、UART3 +* 输 出: 无 +* 注意事项: 无 ******************************************************************************************************************************************/ void UART_INTTXDoneEn(UART_TypeDef *UARTx) { @@ -519,11 +543,11 @@ void UART_INTTXDoneEn(UART_TypeDef *UARTx) } /****************************************************************************************************************************************** -* : UART_INTTXDoneDis() -* ˵: FIFOҷλĴжϽֹ -* : UART_TypeDef * UARTx ָҪõUARTڣЧֵUART0UART1UART2UART3 -* : -* ע: +* 函数名称: UART_INTTXDoneDis() +* 功能说明: 发送FIFO空且发送移位寄存器空中断禁止 +* 输 入: UART_TypeDef * UARTx 指定要被设置的UART串口，有效值包括UART0、UART1、UART2、UART3 +* 输 出: 无 +* 注意事项: 无 ******************************************************************************************************************************************/ void UART_INTTXDoneDis(UART_TypeDef *UARTx) { @@ -531,11 +555,11 @@ void UART_INTTXDoneDis(UART_TypeDef *UARTx) } /****************************************************************************************************************************************** -* : UART_INTTXDoneStat() -* ˵: FIFOҷλĴж״̬ -* : UART_TypeDef * UARTx ָҪõUARTڣЧֵUART0UART1UART2UART3 -* : uint32_t 1 FIFOҷλĴ 0 FIFOλĴδ -* ע: +* 函数名称: UART_INTTXDoneStat() +* 功能说明: 发送FIFO空且发送移位寄存器空中断状态 +* 输 入: UART_TypeDef * UARTx 指定要被设置的UART串口，有效值包括UART0、UART1、UART2、UART3 +* 输 出: uint32_t 1 发送FIFO空且发送移位寄存器空 0 发送FIFO或发送移位寄存器未空 +* 注意事项: 无 ******************************************************************************************************************************************/ uint32_t UART_INTTXDoneStat(UART_TypeDef *UARTx) { diff --git a/bsp/swm320-lq100/Libraries/SWM320_StdPeriph_Driver/SWM320_uart.h b/bsp/swm320-lq100/Libraries/SWM320_StdPeriph_Driver/SWM320_uart.h index 1bc2ad3edc..08bd6f805b 100644 --- a/bsp/swm320-lq100/Libraries/SWM320_StdPeriph_Driver/SWM320_uart.h +++ b/bsp/swm320-lq100/Libraries/SWM320_StdPeriph_Driver/SWM320_uart.h @@ -5,62 +5,59 @@ typedef struct { uint32_t Baudrate; - uint8_t DataBits; //λλȡֵUART_DATA_8BITUART_DATA_9BIT + uint8_t DataBits; //数据位位数，可取值UART_DATA_8BIT、UART_DATA_9BIT - uint8_t Parity; //żУλȡֵUART_PARITY_NONEUART_PARITY_ODDUART_PARITY_EVENUART_PARITY_ONEUART_PARITY_ZERO + uint8_t Parity; //奇偶校验位，可取值UART_PARITY_NONE、UART_PARITY_ODD、UART_PARITY_EVEN、UART_PARITY_ONE、UART_PARITY_ZERO - uint8_t StopBits; //ֹͣλλȡֵUART_STOP_1BITUART_STOP_2BIT + uint8_t StopBits; //停止位位数，可取值UART_STOP_1BIT、UART_STOP_2BIT - uint8_t RXThreshold; //ȡֵ0--7 - uint8_t RXThresholdIEn; //RX FIFOݸ >= RXThresholdʱж + uint8_t RXThreshold; //取值0--7 + uint8_t RXThresholdIEn; //当RX FIFO中数据个数 > RXThreshold时触发中断 - uint8_t TXThreshold; //ȡֵ0--7 - uint8_t TXThresholdIEn; //TX FIFOݸ <= TXThresholdʱж + uint8_t TXThreshold; //取值0--7 + uint8_t TXThresholdIEn; //当TX FIFO中数据个数 <= TXThreshold时触发中断 - uint8_t TimeoutTime; //ʱʱ = TimeoutTime/(Baudrate/10) - uint8_t TimeoutIEn; //ʱжϣ TimeoutTime/(Baudrate/10) ûRXϽյʱж + uint8_t TimeoutTime; //超时时长 = TimeoutTime/(Baudrate/10) 秒 + uint8_t TimeoutIEn; //超时中断，RX FIFO非空，且超过 TimeoutTime/(Baudrate/10) 秒没有在RX线上接收到数据时触发中断 } UART_InitStructure; +#define UART_DATA_8BIT 0 +#define UART_DATA_9BIT 1 -#define UART_DATA_8BIT 0 -#define UART_DATA_9BIT 1 +#define UART_PARITY_NONE 0 +#define UART_PARITY_ODD 1 +#define UART_PARITY_EVEN 3 +#define UART_PARITY_ONE 5 +#define UART_PARITY_ZERO 7 -#define UART_PARITY_NONE 0 -#define UART_PARITY_ODD 1 -#define UART_PARITY_EVEN 3 -#define UART_PARITY_ONE 5 -#define UART_PARITY_ZERO 7 +#define UART_STOP_1BIT 0 +#define UART_STOP_2BIT 1 -#define UART_STOP_1BIT 0 -#define UART_STOP_2BIT 1 +#define UART_RTS_1BYTE 0 +#define UART_RTS_2BYTE 1 +#define UART_RTS_4BYTE 2 +#define UART_RTS_6BYTE 3 -#define UART_RTS_1BYTE 0 -#define UART_RTS_2BYTE 1 -#define UART_RTS_4BYTE 2 -#define UART_RTS_6BYTE 3 +#define UART_ABR_RES_OK 1 +#define UART_ABR_RES_ERR 2 -#define UART_ABR_RES_OK 1 -#define UART_ABR_RES_ERR 2 +#define UART_ERR_FRAME 1 +#define UART_ERR_PARITY 2 +#define UART_ERR_NOISE 3 -#define UART_ERR_FRAME 1 -#define UART_ERR_PARITY 2 -#define UART_ERR_NOISE 3 - - -void UART_Init(UART_TypeDef *UARTx, UART_InitStructure *initStruct); //UARTڳʼ +void UART_Init(UART_TypeDef *UARTx, UART_InitStructure *initStruct); //UART串口初始化 void UART_Open(UART_TypeDef *UARTx); void UART_Close(UART_TypeDef *UARTx); -void UART_WriteByte(UART_TypeDef *UARTx, uint8_t data); //һֽ -uint32_t UART_ReadByte(UART_TypeDef *UARTx, uint32_t *data); //ȡһֽݣָǷValid +void UART_WriteByte(UART_TypeDef *UARTx, uint32_t data); //发送一个字节数据 +uint32_t UART_ReadByte(UART_TypeDef *UARTx, uint32_t *data); //读取一个字节数据，并指出数据是否Valid uint32_t UART_IsTXBusy(UART_TypeDef *UARTx); -uint32_t UART_IsRXFIFOEmpty(UART_TypeDef *UARTx); //FIFOǷգԼUART_ReadByte() -uint32_t UART_IsTXFIFOFull(UART_TypeDef *UARTx); //FIFOǷԼUART_WriteByte() - +uint32_t UART_IsRXFIFOEmpty(UART_TypeDef *UARTx); //接收FIFO是否空，如果不空则可以继续UART_ReadByte() +uint32_t UART_IsTXFIFOFull(UART_TypeDef *UARTx); //发送FIFO是否满，如果不满则可以继续UART_WriteByte() -void UART_SetBaudrate(UART_TypeDef *UARTx, uint32_t baudrate); //ò -uint32_t UART_GetBaudrate(UART_TypeDef *UARTx); //ȡǰʹõIJ +void UART_SetBaudrate(UART_TypeDef *UARTx, uint32_t baudrate); //设置波特率 +uint32_t UART_GetBaudrate(UART_TypeDef *UARTx); //获取当前使用的波特率 void UART_CTSConfig(UART_TypeDef *UARTx, uint32_t enable, uint32_t polarity); uint32_t UART_CTSLineState(UART_TypeDef *UARTx); @@ -76,7 +73,6 @@ uint32_t UART_LINIsGenerated(UART_TypeDef *UARTx); void UART_ABRStart(UART_TypeDef *UARTx, uint32_t detectChar); uint32_t UART_ABRIsDone(UART_TypeDef *UARTx); - void UART_INTRXThresholdEn(UART_TypeDef *UARTx); void UART_INTRXThresholdDis(UART_TypeDef *UARTx); uint32_t UART_INTRXThresholdStat(UART_TypeDef *UARTx); @@ -91,5 +87,4 @@ void UART_INTTXDoneEn(UART_TypeDef *UARTx); void UART_INTTXDoneDis(UART_TypeDef *UARTx); uint32_t UART_INTTXDoneStat(UART_TypeDef *UARTx); - #endif //__SWM320_UART_H__ diff --git a/bsp/swm320-lq100/Libraries/SWM320_StdPeriph_Driver/SWM320_wdt.c b/bsp/swm320-lq100/Libraries/SWM320_StdPeriph_Driver/SWM320_wdt.c index 04faf947d7..db6d7cef28 100644 --- a/bsp/swm320-lq100/Libraries/SWM320_StdPeriph_Driver/SWM320_wdt.c +++ b/bsp/swm320-lq100/Libraries/SWM320_StdPeriph_Driver/SWM320_wdt.c @@ -1,10 +1,10 @@ /****************************************************************************************************************************************** -* ļ: SWM320_wdt.c -* ˵: SWM320ƬWDTŹ -* ֧: http://www.synwit.com.cn/e/tool/gbook/?bid=1 -* ע: -* 汾: V1.1.0 20171025 -* ¼: +* 文件名称: SWM320_wdt.c +* 功能说明: SWM320单片机的WDT看门狗功能驱动库 +* 技术支持: http://www.synwit.com.cn/e/tool/gbook/?bid=1 +* 注意事项: +* 版本日期: V1.1.0 2017年10月25日 +* 升级记录: * * ******************************************************************************************************************************************* @@ -21,32 +21,33 @@ #include "SWM320.h" #include "SWM320_wdt.h" - /****************************************************************************************************************************************** -* : WDT_Init() -* ˵: WDTŹʼ -* : WDT_TypeDef * WDTx ָҪõĿŹЧֵWDT -* uint32_t peroid ȡֵ0--4294967295λΪƬϵͳʱ -* uint32_t mode WDT_MODE_RESET ʱλ WDT_MODE_INTERRUPT ʱж -* : -* ע: λʹʱжϲãΪڽʱоƬֱӸλˣ޷Ӧж +* 函数名称: WDT_Init() +* 功能说明: WDT看门狗初始化 +* 输 入: WDT_TypeDef * WDTx 指定要被设置的看门狗，有效值包括WDT +* uint32_t peroid 取值0--4294967295，单位为单片机系统时钟周期 +* uint32_t mode WDT_MODE_RESET 超时产生复位 WDT_MODE_INTERRUPT 超时产生中断 +* 输 出: 无 +* 注意事项: 无 ******************************************************************************************************************************************/ void WDT_Init(WDT_TypeDef *WDTx, uint32_t peroid, uint32_t mode) { SYS->CLKEN |= (0x01 << SYS_CLKEN_WDT_Pos); - WDT_Stop(WDTx); //ǰȹر - - WDTx->LOAD = peroid; + WDT_Stop(WDTx); //设置前先关闭 if (mode == WDT_MODE_RESET) { + WDTx->LOAD = peroid / 2; //第一个计数周期置位中断标志、第二个计数周期将芯片复位 + NVIC_DisableIRQ(WDT_IRQn); WDTx->CR |= (1 << WDT_CR_RSTEN_Pos); } else //mode == WDT_MODE_INTERRUPT { + WDTx->LOAD = peroid; + NVIC_EnableIRQ(WDT_IRQn); WDTx->CR &= ~(1 << WDT_CR_RSTEN_Pos); @@ -54,11 +55,11 @@ void WDT_Init(WDT_TypeDef *WDTx, uint32_t peroid, uint32_t mode) } /****************************************************************************************************************************************** -* : WDT_Start() -* ˵: ָWDTʼʱ -* : WDT_TypeDef * WDTx ָҪõĿŹЧֵWDT -* : -* ע: +* 函数名称: WDT_Start() +* 功能说明: 启动指定WDT，开始倒计时 +* 输 入: WDT_TypeDef * WDTx 指定要被设置的看门狗，有效值包括WDT +* 输 出: 无 +* 注意事项: 无 ******************************************************************************************************************************************/ void WDT_Start(WDT_TypeDef *WDTx) { @@ -66,11 +67,11 @@ void WDT_Start(WDT_TypeDef *WDTx) } /****************************************************************************************************************************************** -* : WDT_Stop() -* ˵: رָWDTֹͣʱ -* : WDT_TypeDef * WDTx ָҪõĿŹЧֵWDT -* : -* ע: +* 函数名称: WDT_Stop() +* 功能说明: 关闭指定WDT，停止倒计时 +* 输 入: WDT_TypeDef * WDTx 指定要被设置的看门狗，有效值包括WDT +* 输 出: 无 +* 注意事项: 无 ******************************************************************************************************************************************/ void WDT_Stop(WDT_TypeDef *WDTx) { @@ -78,11 +79,11 @@ void WDT_Stop(WDT_TypeDef *WDTx) } /****************************************************************************************************************************************** -* : WDT_Feed() -* ˵: ι´װֵʼʱ -* : WDT_TypeDef * WDTx ָҪõĿŹЧֵWDT -* : -* ע: +* 函数名称: WDT_Feed() +* 功能说明: 喂狗，重新从装载值开始倒计时 +* 输 入: WDT_TypeDef * WDTx 指定要被设置的看门狗，有效值包括WDT +* 输 出: 无 +* 注意事项: 无 ******************************************************************************************************************************************/ void WDT_Feed(WDT_TypeDef *WDTx) { @@ -90,11 +91,11 @@ void WDT_Feed(WDT_TypeDef *WDTx) } /****************************************************************************************************************************************** -* : WDT_GetValue() -* ˵: ȡָŹʱĵǰʱֵ -* : WDT_TypeDef * WDTx ָҪõĿŹЧֵWDT -* : int32_t Źǰֵ -* ע: +* 函数名称: WDT_GetValue() +* 功能说明: 获取指定看门狗定时器的当前倒计时值 +* 输 入: WDT_TypeDef * WDTx 指定要被设置的看门狗，有效值包括WDT +* 输 出: int32_t 看门狗当前计数值 +* 注意事项: 无 ******************************************************************************************************************************************/ int32_t WDT_GetValue(WDT_TypeDef *WDTx) { @@ -102,11 +103,11 @@ int32_t WDT_GetValue(WDT_TypeDef *WDTx) } /****************************************************************************************************************************************** -* : WDT_INTClr() -* ˵: жϱ־ -* : WDT_TypeDef * WDTx ָҪõĿŹЧֵWDT -* : -* ע: +* 函数名称: WDT_INTClr() +* 功能说明: 中断标志清除 +* 输 入: WDT_TypeDef * WDTx 指定要被设置的看门狗，有效值包括WDT +* 输 出: 无 +* 注意事项: 无 ******************************************************************************************************************************************/ void WDT_INTClr(WDT_TypeDef *WDTx) { @@ -114,11 +115,11 @@ void WDT_INTClr(WDT_TypeDef *WDTx) } /****************************************************************************************************************************************** -* : WDT_INTStat() -* ˵: ж״̬ѯ -* : WDT_TypeDef * WDTx ָҪõĿŹЧֵWDT -* : int32_t 1 ж 0 δж -* ע: +* 函数名称: WDT_INTStat() +* 功能说明: 中断状态查询 +* 输 入: WDT_TypeDef * WDTx 指定要被设置的看门狗，有效值包括WDT +* 输 出: int32_t 1 发生中断溢出 0 未发生中断溢出 +* 注意事项: 无 ******************************************************************************************************************************************/ uint32_t WDT_INTStat(WDT_TypeDef *WDTx) { diff --git a/bsp/swm320-lq100/Libraries/SWM320_StdPeriph_Driver/SWM320_wdt.h b/bsp/swm320-lq100/Libraries/SWM320_StdPeriph_Driver/SWM320_wdt.h index fd435c170e..692d1fe65b 100644 --- a/bsp/swm320-lq100/Libraries/SWM320_StdPeriph_Driver/SWM320_wdt.h +++ b/bsp/swm320-lq100/Libraries/SWM320_StdPeriph_Driver/SWM320_wdt.h @@ -1,19 +1,18 @@ #ifndef __SWM320_WDT_H__ #define __SWM320_WDT_H__ -#define WDT_MODE_RESET 0 -#define WDT_MODE_INTERRUPT 1 +#define WDT_MODE_RESET 0 +#define WDT_MODE_INTERRUPT 1 -void WDT_Init(WDT_TypeDef *WDTx, uint32_t peroid, uint32_t mode); //WDTŹʼ -void WDT_Start(WDT_TypeDef *WDTx); //ָWDTʼʱ -void WDT_Stop(WDT_TypeDef *WDTx); //رָWDTֹͣʱ +void WDT_Init(WDT_TypeDef *WDTx, uint32_t peroid, uint32_t mode); //WDT看门狗初始化 +void WDT_Start(WDT_TypeDef *WDTx); //启动指定WDT，开始倒计时 +void WDT_Stop(WDT_TypeDef *WDTx); //关闭指定WDT，停止倒计时 -void WDT_Feed(WDT_TypeDef *WDTx); //ι´װֵʼʱ +void WDT_Feed(WDT_TypeDef *WDTx); //喂狗，重新从装载值开始倒计时 -int32_t WDT_GetValue(WDT_TypeDef *WDTx); //ȡָŹʱĵǰʱֵ +int32_t WDT_GetValue(WDT_TypeDef *WDTx); //获取指定看门狗定时器的当前倒计时值 - -void WDT_INTClr(WDT_TypeDef *WDTx); //жϱ־ -uint32_t WDT_INTStat(WDT_TypeDef *WDTx); //ж״̬ѯ +void WDT_INTClr(WDT_TypeDef *WDTx); //中断标志清除 +uint32_t WDT_INTStat(WDT_TypeDef *WDTx); //中断状态查询 #endif //__SWM320_WDT_H__ diff --git a/bsp/swm320-lq100/README.md b/bsp/swm320-lq100/README.md index 119b9e7b4b..ef571daaa0 100644 --- a/bsp/swm320-lq100/README.md +++ b/bsp/swm320-lq100/README.md @@ -31,7 +31,7 @@ SWXT-LQ100-32102 V1.1 开发板板载资源如下： - 常用接口：USB打印接口，TFT LCD接口，SD卡接口 - 调试接口：SWD -更多详细信息请咨询[华芯微特技术支持][http://www.synwit.cn/support.html] +更多详细信息请咨询[华芯微特技术支持](https://www.synwit.cn) ### 1.2 MCU 简介 @@ -89,36 +89,30 @@ msh /> ## 4. 驱动支持情况及计划 -|**板载外设** |**支持情况**|**备注** | -| ----------------- | :----------: | ----------------------- | -| Nor Flash | 支持 | | -| SDIO TF 卡 | 暂不支持 | | -| SRAM | 支持 | | -| TFT-LCD | 暂不支持 | 即将支持 | -|**片上外设** |**支持情况** |**备注** | -| GPIO | 支持 | PIN：1...100 | -| UART | 支持 | UART0 / UART1 / UART2 / UART3 | -| SPI | 支持 | SPI0 / SPI1 | -| I2C | 支持 | I2C0 IO模拟 | -| ADC | 暂不支持 | 即将支持 | -| PWM | 支持 | PWM0 / PWM1 /PWM2 /PWM3 其余两个后续补充| -| IWG | 支持 | | -| TIMER | 支持 | | -| RTC | 支持 | | -| CAN | 暂不支持 | | +| **片上外设** | **支持情况** | **备注** | +| :----------------- | :----------: | :----------------------------------- | +| GPIO | 支持 | PA0, PA1... PP23 ---> PIN: 0, 1...100 | +| UART | 支持 | UART0/1/2/3 | +| ADC | 支持 | ADC0/1 | +| TIM | 支持 | TIM0/1/2/3/4/5 | +| I2C | 支持 | 软件 I2C0/1 | +| PWM | 支持 | PWM0/1/2/3/4/5 | +| RTC | 支持 | RTC | +| SPI | 支持 | SPI0/1 | +| WDT | 支持 | WDT | +| CRC | 支持 | CRC | +| SDIO | 支持 | SDIO | +| SRAM | 支持 | SRAM | +| NOR FLASH | 支持 | NOR FLASH | +| CAN | 暂不支持 | | ## 5. 联系人信息 -维护人： +- [yanmowudi](https://github.com/yanmowudi) +- [邮箱](lik@synwit.cn) --[Zohar_Lee](https://github.com/zohar123) email: lizhh@synwit.cn +## 参考资料 -## 6. 参考 +* [RT-Thread 文档中心](https://www.rt-thread.org/document/site/) -- 芯片[SWM320系列数据手册][http://www.synwit.cn/Public/Uploads/2018-11-05/5bdff49b396d1.pdf] - -- [ SWM320_LQFP100原理图](http://www.synwit.cn/Public/Uploads/2018-11-01/5bdab8ad2e5b9.pdf) - -- [ SWM320_LQFP64原理图](http://www.synwit.cn/Public/Uploads/2018-11-05/5bdfea74d5712.pdf) - -- [ keil pack及其他资料](http://www.synwit.cn/support-1/2.html) +* [SWM320数据手册](https://www.synwit.cn/col.jsp?id=155) diff --git a/bsp/swm320-lq100/SConscript b/bsp/swm320-lq100/SConscript index 1b1c7506a4..c7ef7659ec 100644 --- a/bsp/swm320-lq100/SConscript +++ b/bsp/swm320-lq100/SConscript @@ -1,11 +1,14 @@ +# for module compiling +import os from building import * cwd = GetCurrentDir() - objs = [] list = os.listdir(cwd) + for d in list: path = os.path.join(cwd, d) if os.path.isfile(os.path.join(path, 'SConscript')): objs = objs + SConscript(os.path.join(d, 'SConscript')) + Return('objs') diff --git a/bsp/swm320-lq100/SConstruct b/bsp/swm320-lq100/SConstruct index 8418d596c0..c11cd41bc7 100644 --- a/bsp/swm320-lq100/SConstruct +++ b/bsp/swm320-lq100/SConstruct @@ -8,6 +8,7 @@ else: RTT_ROOT = os.path.normpath(os.getcwd() + '/../..') sys.path = sys.path + [os.path.join(RTT_ROOT, 'tools')] + try: from building import * except: @@ -17,18 +18,18 @@ except: TARGET = 'rtthread.' + rtconfig.TARGET_EXT -DefaultEnvironment(tools=[]) env = Environment(tools = ['mingw'], - AS = rtconfig.AS, ASFLAGS = rtconfig.AFLAGS, - CC = rtconfig.CC, CCFLAGS = rtconfig.CFLAGS, - AR = rtconfig.AR, ARFLAGS = '-rc', - LINK = rtconfig.LINK, LINKFLAGS = rtconfig.LFLAGS) + AS = rtconfig.AS, ASFLAGS = rtconfig.AFLAGS, + CC = rtconfig.CC, CCFLAGS = rtconfig.CFLAGS, + CXX = rtconfig.CXX, CXXFLAGS = rtconfig.CXXFLAGS, + AR = rtconfig.AR, ARFLAGS = '-rc', + LINK = rtconfig.LINK, LINKFLAGS = rtconfig.LFLAGS) env.PrependENVPath('PATH', rtconfig.EXEC_PATH) if rtconfig.PLATFORM == 'iar': env.Replace(CCCOM = ['$CC $CCFLAGS $CPPFLAGS $_CPPDEFFLAGS $_CPPINCFLAGS -o $TARGET $SOURCES']) env.Replace(ARFLAGS = ['']) - env.Replace(LINKCOM = env["LINKCOM"] + ' --map project.map') + env.Replace(LINKCOM = env["LINKCOM"] + ' --map rtthread.map') Export('RTT_ROOT') Export('rtconfig') diff --git a/bsp/swm320-lq100/applications/main.c b/bsp/swm320-lq100/applications/main.c index 004867b45c..3761e8c14d 100644 --- a/bsp/swm320-lq100/applications/main.c +++ b/bsp/swm320-lq100/applications/main.c @@ -1,31 +1,571 @@ /* - * Copyright (c) 2006-2018, Synwit Technology Co.,Ltd. + * Copyright (c) 2006-2021, RT-Thread Development Team * * SPDX-License-Identifier: Apache-2.0 * * Change Logs: * Date Author Notes - * 2018-12-10 Zohar_Lee first version */ #include #include -/* defined the LED pin: PA12 */ -#define LED_PIN 100 + +#define LED_PIN 11 int main(void) { int count = 1; - /* set LED4 pin mode to output */ - rt_pin_mode(LED_PIN, PIN_MODE_OUTPUT); + rt_pin_mode(LED_PIN, PIN_MODE_OUTPUT); while (count++) { rt_pin_write(LED_PIN, PIN_HIGH); - rt_thread_mdelay(500); + rt_thread_mdelay(1000); rt_pin_write(LED_PIN, PIN_LOW); - rt_thread_mdelay(500); + rt_thread_mdelay(1000); + } + + return RT_EOK; +} + +// #ifdef RT_USING_PIN +// #define KEY1_PIN 31 +// void key1_cb(void *args) +// { +// rt_kprintf("key1 irq!\n"); +// } +// static int pin_sample(int argc, char *argv[]) +// { +// rt_pin_mode(KEY1_PIN, PIN_IRQ_MODE_FALLING); +// rt_pin_attach_irq(KEY1_PIN, PIN_IRQ_MODE_FALLING, key1_cb, RT_NULL); +// rt_pin_irq_enable(KEY1_PIN, PIN_IRQ_ENABLE); + +// return RT_EOK; +// } +// MSH_CMD_EXPORT(pin_sample, pin sample); +// #endif + +#ifdef RT_USING_ADC +#define ADC_DEV_NAME "adc1" +#define ADC_DEV_CHANNEL 0 +#define REFER_VOLTAGE 330 +#define CONVERT_BITS (1 << 12) + +static int adc_vol_sample(int argc, char *argv[]) +{ + rt_adc_device_t adc_dev; + rt_uint32_t value, vol; + rt_err_t ret = RT_EOK; + + adc_dev = (rt_adc_device_t)rt_device_find(ADC_DEV_NAME); + if (adc_dev == RT_NULL) + { + rt_kprintf("adc sample run failed! can't find %s device!\n", ADC_DEV_NAME); + return RT_ERROR; } + ret = rt_adc_enable(adc_dev, ADC_DEV_CHANNEL); + + value = rt_adc_read(adc_dev, ADC_DEV_CHANNEL); + rt_kprintf("the value is :%d,", value); + + vol = value * REFER_VOLTAGE / CONVERT_BITS; + rt_kprintf("the voltage is :%d.%02d \n", vol / 100, vol % 100); + + ret = rt_adc_disable(adc_dev, ADC_DEV_CHANNEL); + + return ret; +} +MSH_CMD_EXPORT(adc_vol_sample, adc voltage convert sample); +#endif + +#ifdef RT_USING_HWTIMER +#define HWTIMER_DEV_NAME "timer0" + +static rt_err_t timeout_cb(rt_device_t dev, rt_size_t size) +{ + rt_kprintf("this is hwtimer timeout callback fucntion!\n"); + rt_kprintf("tick is :%d !\n", rt_tick_get()); + + return 0; +} + +static int hwtimer_sample(int argc, char *argv[]) +{ + rt_err_t ret = RT_EOK; + rt_hwtimerval_t timeout_s; + rt_device_t hw_dev = RT_NULL; + rt_hwtimer_mode_t mode; + + hw_dev = rt_device_find(HWTIMER_DEV_NAME); + if (hw_dev == RT_NULL) + { + rt_kprintf("hwtimer sample run failed! can't find %s device!\n", HWTIMER_DEV_NAME); + return RT_ERROR; + } + + ret = rt_device_open(hw_dev, RT_DEVICE_OFLAG_RDWR); + if (ret != RT_EOK) + { + rt_kprintf("open %s device failed!\n", HWTIMER_DEV_NAME); + return ret; + } + + rt_device_set_rx_indicate(hw_dev, timeout_cb); + + mode = HWTIMER_MODE_PERIOD; + //mode = HWTIMER_MODE_ONESHOT; + ret = rt_device_control(hw_dev, HWTIMER_CTRL_MODE_SET, &mode); + if (ret != RT_EOK) + { + rt_kprintf("set mode failed! ret is :%d\n", ret); + return ret; + } + + timeout_s.sec = 2; + timeout_s.usec = 0; + + if (rt_device_write(hw_dev, 0, &timeout_s, sizeof(timeout_s)) != sizeof(timeout_s)) + { + rt_kprintf("set timeout value failed\n"); + return RT_ERROR; + } + + rt_thread_mdelay(3500); + + rt_device_read(hw_dev, 0, &timeout_s, sizeof(timeout_s)); + rt_kprintf("Read: Sec = %d, Usec = %d\n", timeout_s.sec, timeout_s.usec); + + return ret; +} +MSH_CMD_EXPORT(hwtimer_sample, hwtimer sample); +#endif + +#ifdef RT_USING_PWM +#define PWM_DEV_NAME "pwm0" /* PWM设备名称 */ +#define PWM_DEV_CHANNEL 0 /* PWM通道 */ + +struct rt_device_pwm *pwm_dev; /* PWM设备句柄 */ + +static int pwm_sample(int argc, char *argv[]) +{ + rt_uint32_t period, pulse; + + period = 500000; /* 周期为0.5ms,单位为纳秒ns */ + pulse = 250000; /* PWM脉冲宽度值,单位为纳秒ns */ + + pwm_dev = (struct rt_device_pwm *)rt_device_find(PWM_DEV_NAME); + if (pwm_dev == RT_NULL) + { + rt_kprintf("pwm sample run failed! can't find %s device!\n", PWM_DEV_NAME); + return RT_ERROR; + } + + rt_pwm_set(pwm_dev, PWM_DEV_CHANNEL, period, pulse); + rt_pwm_enable(pwm_dev, PWM_DEV_CHANNEL); + return RT_EOK; +} +MSH_CMD_EXPORT(pwm_sample, pwm sample); +#endif + +#ifdef RT_USING_RTC +#include +static int rtc_sample(int argc, char *argv[]) +{ + rt_err_t ret = RT_EOK; + time_t now; + + ret = set_date(2020, 2, 28); + if (ret != RT_EOK) + { + rt_kprintf("set RTC date failed\n"); + return ret; + } + + ret = set_time(23, 59, 55); + if (ret != RT_EOK) + { + rt_kprintf("set RTC time failed\n"); + return ret; + } + + //rt_thread_mdelay(3000); + now = time(RT_NULL); + rt_kprintf("%s\n", ctime(&now)); + + return ret; +} +MSH_CMD_EXPORT(rtc_sample, rtc sample); +#endif + +#ifdef RT_USING_WDT +#define WDT_DEVICE_NAME "wdt" + +static rt_device_t wdg_dev; + +static void idle_hook(void) +{ + rt_device_control(wdg_dev, RT_DEVICE_CTRL_WDT_KEEPALIVE, RT_NULL); + rt_kprintf("feed the dog!\n "); +} + +static int wdt_sample(int argc, char *argv[]) +{ + rt_err_t ret = RT_EOK; + rt_uint32_t timeout = 1; + char device_name[RT_NAME_MAX]; + + if (argc == 2) + { + rt_strncpy(device_name, argv[1], RT_NAME_MAX); + } + else + { + rt_strncpy(device_name, WDT_DEVICE_NAME, RT_NAME_MAX); + } + wdg_dev = rt_device_find(device_name); + if (!wdg_dev) + { + rt_kprintf("find %s failed!\n", device_name); + return RT_ERROR; + } + ret = rt_device_init(wdg_dev); + if (ret != RT_EOK) + { + rt_kprintf("initialize %s failed!\n", device_name); + return RT_ERROR; + } + ret = rt_device_control(wdg_dev, RT_DEVICE_CTRL_WDT_SET_TIMEOUT, &timeout); + if (ret != RT_EOK) + { + rt_kprintf("set %s timeout failed!\n", device_name); + return RT_ERROR; + } + ret = rt_device_control(wdg_dev, RT_DEVICE_CTRL_WDT_START, RT_NULL); + if (ret != RT_EOK) + { + rt_kprintf("start %s failed!\n", device_name); + return -RT_ERROR; + } + // rt_thread_idle_sethook(idle_hook); + + return ret; +} +MSH_CMD_EXPORT(wdt_sample, wdt sample); +#endif + +#ifdef RT_USING_SPI +#define W25Q_SPI_DEVICE_NAME "spi00" +#define W25Q_FLASH_NAME "norflash0" + +#include "drv_spi.h" +#include "spi_flash_sfud.h" +#include "dfs_posix.h" + +static int rt_hw_spi_flash_init(void) +{ + rt_hw_spi_device_attach("spi0", "spi00", GPIOP, PIN22); + + if (RT_NULL == rt_sfud_flash_probe(W25Q_FLASH_NAME, W25Q_SPI_DEVICE_NAME)) + { + return -RT_ERROR; + }; + return RT_EOK; } +INIT_COMPONENT_EXPORT(rt_hw_spi_flash_init); + +static void spi_w25q_sample(int argc, char *argv[]) +{ + struct rt_spi_device *spi_dev_w25q; + char name[RT_NAME_MAX]; + rt_uint8_t w25x_read_id = 0x90; + rt_uint8_t id[5] = {0}; + + if (argc == 2) + { + rt_strncpy(name, argv[1], RT_NAME_MAX); + } + else + { + rt_strncpy(name, W25Q_SPI_DEVICE_NAME, RT_NAME_MAX); + } + + /* 查找 spi 设备获取设备句柄 */ + spi_dev_w25q = (struct rt_spi_device *)rt_device_find(name); + struct rt_spi_configuration cfg; + cfg.data_width = 8; + cfg.mode = RT_SPI_MASTER | RT_SPI_MODE_0 | RT_SPI_MSB; + cfg.max_hz = 30 * 1000 * 1000; /* 20M */ + + rt_spi_configure(spi_dev_w25q, &cfg); + if (!spi_dev_w25q) + { + rt_kprintf("spi sample run failed! can't find %s device!\n", name); + } + else + { + /* 方式1：使用 rt_spi_send_then_recv()发送命令读取ID */ + rt_spi_send_then_recv(spi_dev_w25q, &w25x_read_id, 1, id, 5); + rt_kprintf("use rt_spi_send_then_recv() read w25q ID is:%x%x\n", id[3], id[4]); + + /* 方式2：使用 rt_spi_transfer_message()发送命令读取ID */ + struct rt_spi_message msg1, msg2; + + msg1.send_buf = &w25x_read_id; + msg1.recv_buf = RT_NULL; + msg1.length = 1; + msg1.cs_take = 1; + msg1.cs_release = 0; + msg1.next = &msg2; + + msg2.send_buf = RT_NULL; + msg2.recv_buf = id; + msg2.length = 5; + msg2.cs_take = 0; + msg2.cs_release = 1; + msg2.next = RT_NULL; + + rt_spi_transfer_message(spi_dev_w25q, &msg1); + rt_kprintf("use rt_spi_transfer_message() read w25q ID is:%x%x\n", id[3], id[4]); + } +} +static void spi_flash_elmfat_sample(void) +{ + int fd, size; + struct statfs elm_stat; + char str[] = "elmfat mount to W25Q flash.\r\n", buf[80]; + + if (dfs_mkfs("elm", W25Q_FLASH_NAME) == 0) + rt_kprintf("make elmfat filesystem success.\n"); + + if (dfs_mount(W25Q_FLASH_NAME, "/", "elm", 0, 0) == 0) + rt_kprintf("elmfat filesystem mount success.\n"); + + if (statfs("/", &elm_stat) == 0) + rt_kprintf("elmfat filesystem block size: %d, total blocks: %d, free blocks: %d.\n", + elm_stat.f_bsize, elm_stat.f_blocks, elm_stat.f_bfree); + + if (mkdir("/user", 0x777) == 0) + rt_kprintf("make a directory: '/user'.\n"); + + rt_kprintf("Write string '%s' to /user/test.txt.\n", str); + + fd = open("/user/test.txt", O_WRONLY | O_CREAT); + if (fd >= 0) + { + if (write(fd, str, sizeof(str)) == sizeof(str)) + rt_kprintf("Write data done.\n"); + + close(fd); + } + + fd = open("/user/test.txt", O_RDONLY); + if (fd >= 0) + { + size = read(fd, buf, sizeof(buf)); + + close(fd); + + if (size == sizeof(str)) + rt_kprintf("Read data from file test.txt(size: %d): %s \n", size, buf); + } +} +MSH_CMD_EXPORT(spi_flash_elmfat_sample, spi flash elmfat sample); +MSH_CMD_EXPORT(spi_w25q_sample, spi w25q sample); +#endif + +//#ifdef RT_USING_SPI +//#define SD_SPI_DEVICE_NAME "spi10" +//#define SDCARD_NAME "sd0" + +//#include "drv_spi.h" +//#include "dfs_posix.h" +//#include "spi_msd.h" + +//static int rt_hw_spi1_tfcard(void) +//{ +// rt_hw_spi_device_attach("spi1", SD_SPI_DEVICE_NAME, GPIOB, PIN6); +// return msd_init(SDCARD_NAME, SD_SPI_DEVICE_NAME); +//} +//INIT_DEVICE_EXPORT(rt_hw_spi1_tfcard); + +//static void elmfat_sample(void) +//{ +// int fd, size; +// struct statfs elm_stat; +// char str[] = "elmfat mount to sdcard.", buf[80]; + +// if (dfs_mkfs("elm", SDCARD_NAME) == 0) +// rt_kprintf("make elmfat filesystem success.\n"); + +// if (dfs_mount(SDCARD_NAME, "/", "elm", 0, 0) == 0) +// rt_kprintf("elmfat filesystem mount success.\n"); + +// if (statfs("/", &elm_stat) == 0) +// rt_kprintf("elmfat filesystem block size: %d, total blocks: %d, free blocks: %d.\n", +// elm_stat.f_bsize, elm_stat.f_blocks, elm_stat.f_bfree); + +// if (mkdir("/user", 0x777) == 0) +// rt_kprintf("make a directory: '/user'.\n"); + +// rt_kprintf("Write string '%s' to /user/test.txt.\n", str); + +// fd = open("/user/test.txt", O_WRONLY | O_CREAT); +// if (fd >= 0) +// { +// if (write(fd, str, sizeof(str)) == sizeof(str)) +// rt_kprintf("Write data done.\n"); + +// close(fd); +// } + +// fd = open("/user/test.txt", O_RDONLY); +// if (fd >= 0) +// { +// size = read(fd, buf, sizeof(buf)); + +// close(fd); + +// if (size == sizeof(str)) +// rt_kprintf("Read data from file test.txt(size: %d): %s \n", size, buf); +// } +//} +//MSH_CMD_EXPORT(elmfat_sample, elmfat sample); +//#endif + +#ifdef RT_USING_SDIO +#define SDCARD_NAME "sd0" + +#include "dfs_posix.h" + +static void sdio_elmfat_sample(void) +{ + int fd, size; + struct statfs elm_stat; + char str[] = "elmfat mount to sdcard.\n", buf[80]; + + if (dfs_mkfs("elm", SDCARD_NAME) == 0) + rt_kprintf("make elmfat filesystem success.\n"); + + if (dfs_mount(SDCARD_NAME, "/", "elm", 0, 0) == 0) + rt_kprintf("elmfat filesystem mount success.\n"); + + if (statfs("/", &elm_stat) == 0) + rt_kprintf("elmfat filesystem block size: %d, total blocks: %d, free blocks: %d.\n", + elm_stat.f_bsize, elm_stat.f_blocks, elm_stat.f_bfree); + + if (mkdir("/user", 0x777) == 0) + rt_kprintf("make a directory: '/user'.\n"); + + rt_kprintf("Write string '%s' to /user/test.txt.\n", str); + + fd = open("/user/test.txt", O_WRONLY | O_CREAT); + if (fd >= 0) + { + if (write(fd, str, sizeof(str)) == sizeof(str)) + rt_kprintf("Write data done.\n"); + + close(fd); + } + + fd = open("/user/test.txt", O_RDONLY); + if (fd >= 0) + { + size = read(fd, buf, sizeof(buf)); + + close(fd); + + if (size == sizeof(str)) + rt_kprintf("Read data from file test.txt(size: %d): %s \n", size, buf); + } +} +MSH_CMD_EXPORT(sdio_elmfat_sample, sdio elmfat sample); +#endif + +#ifdef RT_USING_HWCRYPTO +static void crypto_sample(void) +{ + rt_uint8_t temp[] = {0, 1, 2, 3, 4, 5, 6, 7}; + struct rt_hwcrypto_ctx *ctx; + rt_uint32_t result = 0; + struct hwcrypto_crc_cfg cfg = + { + .last_val = 0x0, + .poly = 0x04C11DB7, + .width = 8, + .xorout = 0x00000000, + .flags = 0, + }; + + ctx = rt_hwcrypto_crc_create(rt_hwcrypto_dev_default(), HWCRYPTO_CRC_CRC32); + rt_hwcrypto_crc_cfg(ctx, &cfg); + result = rt_hwcrypto_crc_update(ctx, temp, sizeof(temp)); + rt_kprintf("result: 0x%08x \n", result); + rt_hwcrypto_crc_destroy(ctx); +} +MSH_CMD_EXPORT(crypto_sample, crypto sample); +#endif + +#ifdef BSP_USING_NOR_FLASH +#define NORFLASH_DEV_NAME "nor" +static int norflash_sample(int argc, char *argv[]) +{ + rt_err_t ret = RT_EOK; + rt_device_t hw_dev = RT_NULL; + + hw_dev = rt_device_find(NORFLASH_DEV_NAME); + if (hw_dev == RT_NULL) + { + rt_kprintf("norflash sample run failed! can't find %s device!\n", NORFLASH_DEV_NAME); + return RT_ERROR; + } + else + { + rt_kprintf("norflash sample run success! find %s device!\n", NORFLASH_DEV_NAME); + } + + ret = rt_device_open(hw_dev, RT_DEVICE_OFLAG_RDWR); + if (ret != RT_EOK) + { + rt_kprintf("open %s device failed!\n", NORFLASH_DEV_NAME); + return ret; + } + else + { + rt_kprintf("open %s device success!\n", NORFLASH_DEV_NAME); + } + + struct rt_mtd_nor_device *hw_nor; + hw_nor = RT_MTD_NOR_DEVICE(hw_dev); + long id = hw_nor->ops->read_id(hw_nor); + rt_kprintf("id = %08x!\n", id); + // rt_device_set_rx_indicate(hw_dev, timeout_cb); + + // mode = HWTIMER_MODE_PERIOD; + // //mode = HWTIMER_MODE_ONESHOT; + // ret = rt_device_control(hw_dev, HWTIMER_CTRL_MODE_SET, &mode); + // if (ret != RT_EOK) + // { + // rt_kprintf("set mode failed! ret is :%d\n", ret); + // return ret; + // } + + // timeout_s.sec = 2; + // timeout_s.usec = 0; + + // if (rt_device_write(hw_dev, 0, &timeout_s, sizeof(timeout_s)) != sizeof(timeout_s)) + // { + // rt_kprintf("set timeout value failed\n"); + // return RT_ERROR; + // } + + // rt_thread_mdelay(3500); + + // rt_device_read(hw_dev, 0, &timeout_s, sizeof(timeout_s)); + // rt_kprintf("Read: Sec = %d, Usec = %d\n", timeout_s.sec, timeout_s.usec); + + return ret; +} +MSH_CMD_EXPORT(norflash_sample, norflash sample); +#endif diff --git a/bsp/swm320-lq100/drivers/Kconfig b/bsp/swm320-lq100/drivers/Kconfig index 64d5c99241..2ad515ae90 100644 --- a/bsp/swm320-lq100/drivers/Kconfig +++ b/bsp/swm320-lq100/drivers/Kconfig @@ -1,169 +1,306 @@ menu "Hardware Drivers Config" - menu "On-chip Peripheral Drivers" - config BSP_USING_GPIO - bool "Enable GPIO" - select RT_USING_PIN - default y - - config BSP_USING_WDT - bool "Enable Watch Dog" - select RT_USING_WDT - default n +config SOC_SWM320 + bool + select RT_USING_COMPONENTS_INIT + select RT_USING_USER_MAIN + default y - menu "UART Drivers" - config BSP_USING_UART0 - bool "Enable UART0 PA2/3(R/T)" - select RT_USING_SERIAL - default y +menu "On-chip Peripheral Drivers" + menuconfig BSP_USING_UART + bool "Enable UART" + default y + select RT_USING_SERIAL + if BSP_USING_UART + config BSP_USING_UART0 + bool "Enable UART0 (A2/RX,A3/TX)" + default y config BSP_USING_UART1 - bool "Enable UART1 PC2/3(R/T)" - select RT_USING_SERIAL + bool "Enable UART1 (C2/RX,C3/TX)" default n - config BSP_USING_UART2 - bool "Enable UART2 PC4/5(R/T)" - select RT_USING_SERIAL + bool "Enable UART2 (C4/RX,C5/TX)" default n - config BSP_USING_UART3 - bool "Enable UART3 PC6/7(R/T)" - select RT_USING_SERIAL - default n - endmenu + bool "Enable UART3 (C6/RX,C7/TX)" + default n + endif - menu "SPI Drivers" - config BSP_USING_SPI0 - bool "Enable SPI0 BUS PC4/5/6(C/O/I)" - select RT_USING_SPI - select RT_USING_PIN - default n + config BSP_USING_GPIO + bool "Enable GPIO" + select RT_USING_PIN + default y - config BSP_USING_SPI1 - bool "Enable SPI1 BUS PM5/C2/C3(C/O/I)" - select RT_USING_SPI - select RT_USING_PIN + menuconfig BSP_USING_ADC + bool "Enable ADC" + default n + select RT_USING_ADC + if BSP_USING_ADC + config BSP_USING_ADC0 + bool "Enable ADC0" default n - endmenu - - menu "I2C Drivers" - config BSP_USING_I2C - bool "Enable I2C BUS" - select RT_USING_I2C - select RT_USING_PIN - select RT_USING_I2C_BITOPS + if BSP_USING_ADC0 + config BSP_USING_ADC0_CHN0 + bool "Enable ADC0_CHN0" + default n + config BSP_USING_ADC0_CHN1 + bool "Enable ADC0_CHN1" + default n + config BSP_USING_ADC0_CHN2 + bool "Enable ADC0_CHN2" + default n + config BSP_USING_ADC0_CHN3 + bool "Enable ADC0_CHN3" + default n + config BSP_USING_ADC0_CHN4 + bool "Enable ADC0_CHN4(A12)" + default n + config BSP_USING_ADC0_CHN5 + bool "Enable ADC0_CHN5(A11)" + default n + config BSP_USING_ADC0_CHN6 + bool "Enable ADC0_CHN6(A10)" + default n + config BSP_USING_ADC0_CHN7 + bool "Enable ADC0_CHN7(A9)" + default n + endif + config BSP_USING_ADC1 + bool "Enable ADC1" default n + if BSP_USING_ADC1 + config BSP_USING_ADC1_CHN0 + bool "Enable ADC1_CHN0(C7)" + default n + config BSP_USING_ADC1_CHN1 + bool "Enable ADC1_CHN1(C6)" + default n + config BSP_USING_ADC1_CHN2 + bool "Enable ADC1_CHN2(C5)" + default n + config BSP_USING_ADC1_CHN3 + bool "Enable ADC1_CHN3(C4)" + default n + config BSP_USING_ADC1_CHN4 + bool "Enable ADC1_CHN4(N0)" + default n + config BSP_USING_ADC1_CHN5 + bool "Enable ADC1_CHN5(N1)" + default n + config BSP_USING_ADC1_CHN6 + bool "Enable ADC1_CHN6(N2)" + default n + config BSP_USING_ADC1_CHN7 + bool "Enable ADC1_CHN7" + default n + endif + endif - if BSP_USING_I2C - - config BSP_I2C_SCL - int "I2C SCL Pin index" - default 98 + menuconfig BSP_USING_TIM + bool "Enable HWTIMER" + default n + select RT_USING_HWTIMER + if BSP_USING_TIM + config BSP_USING_TIM0 + bool "Enable TIM0" + default n + config BSP_USING_TIM1 + bool "Enable TIM1" + default n + config BSP_USING_TIM2 + bool "Enable TIM2" + default n + config BSP_USING_TIM3 + bool "Enable TIM3" + default n - config BSP_I2C_SDA - int "I2C SDA Pin index" - default 99 + config BSP_USING_TIM4 + bool "Enable TIM4" + default n + config BSP_USING_TIM5 + bool "Enable TIM5" + default n + endif - config BSP_I2C_BUS_NAME - string "i2c bus name" - default "i2c0" + menuconfig BSP_USING_I2C + bool "Enable I2C BUS (software simulation)" + default n + select RT_USING_I2C + select RT_USING_I2C_BITOPS + select RT_USING_PIN + if BSP_USING_I2C + config BSP_USING_I2C0 + bool "Enable I2C0" + default n + if BSP_USING_I2C0 + comment "Notice: PC2 --> 28; PC3 --> 29" + config BSP_I2C0_SCL_PIN + int "I2C0 scl pin number" + range 0 99 + default 28 + config BSP_I2C0_SDA_PIN + int "I2C0 sda pin number" + range 0 99 + default 29 endif - endmenu - - menu "PWM Drivers" - config BSP_USING_PWM0 - bool "Using PWM0 PA4/10(A/B)" - select RT_USING_PWM - default n - - config BSP_USING_PWM1 - bool "Using PWM1 PA5/9(A/B)" - select RT_USING_PWM - default n - - config BSP_USING_PWM2 - bool "Using PWM2 PP0/2(A/B)" - select RT_USING_PWM - default n - - config BSP_USING_PWM3 - bool "Using PWM3 PP1/3(A/B)" - select RT_USING_PWM - default n - endmenu - - menu "RTC Drivers" - config BSP_USING_RTC - bool "Using RTC" - select RT_USING_RTC - default n - endmenu - - menu "HWtimer Drivers" - config BSP_USING_HWTIMER0 - bool "Using timer0" - select RT_USING_HWTIMER + config BSP_USING_I2C1 + bool "Enable I2C1" default n + if BSP_USING_I2C1 + comment "Notice: PC6 --> 32; PC7 --> 33" + config BSP_I2C1_SCL_PIN + int "I2C1 scl pin number" + range 0 99 + default 32 + config BSP_I2C1_SDA_PIN + int "I2C1 sda pin number" + range 0 99 + default 33 + endif + endif - config BSP_USING_HWTIMER1 - bool "Using timer1" - select RT_USING_HWTIMER - default n + menuconfig BSP_USING_PWM + bool "Enable PWM" + default n + select RT_USING_PWM + if BSP_USING_PWM + config BSP_USING_PWM0 + bool "Enable PWM0" + default n + if BSP_USING_PWM0 + config BSP_USING_PWM0A + bool "Enable PWM0A (C2)" + default n + config BSP_USING_PWM0B + bool "Enable PWM0B (C4)" + default n + endif + config BSP_USING_PWM1 + bool "Enable PWM1" + default n + if BSP_USING_PWM1 + config BSP_USING_PWM1A + bool "Enable PWM1A (C3)" + default n + config BSP_USING_PWM1B + bool "Enable PWM1B (C5)" + default n + endif + config BSP_USING_PWM2 + bool "Enable PWM2" + default n + if BSP_USING_PWM2 + config BSP_USING_PWM2A + bool "Enable PWM2A (N4)" + default n + config BSP_USING_PWM2B + bool "Enable PWM2B (N6)" + default n + endif + config BSP_USING_PWM3 + bool "Enable PWM3" + default n + if BSP_USING_PWM3 + config BSP_USING_PWM3A + bool "Enable PWM3A (N3)" + default n + config BSP_USING_PWM3B + bool "Enable PWM3B (N5)" + default n + endif + config BSP_USING_PWM4 + bool "Enable PWM4" + default n + if BSP_USING_PWM4 + config BSP_USING_PWM4A + bool "Enable PWM4A (N8)" + default n + config BSP_USING_PWM4B + bool "Enable PWM4B (N10)" + default n + endif + config BSP_USING_PWM5 + bool "Enable PWM5" + default n + if BSP_USING_PWM5 + config BSP_USING_PWM5A + bool "Enable PWM5A (N7)" + default n + config BSP_USING_PWM5B + bool "Enable PWM5B (N9)" + default n + endif + endif - config BSP_USING_HWTIMER2 - bool "Using timer2" - select RT_USING_HWTIMER - default n + config BSP_USING_RTC + bool "Enable RTC" + select RT_USING_RTC + select RT_USING_LIBC + default n - config BSP_USING_HWTIMER3 - bool "Using timer3" - select RT_USING_HWTIMER + menuconfig BSP_USING_SPI + bool "Enable SPI BUS" + default n + select RT_USING_SPI + if BSP_USING_SPI + config BSP_USING_SPI0 + bool "Enable SPI0 BUS(CS/P22,MISO/P19,MOSI/P18,CLK/P23)" default n - config BSP_USING_HWTIMER4 - bool "Using timer4" - select RT_USING_HWTIMER + config BSP_USING_SPI1 + bool "Enable SPI1 BUS(CS/B6,MISO/B3,MOSI/B2,CLK/B1)" default n + endif - config BSP_USING_HWTIMER5 - bool "Using timer5" - select RT_USING_HWTIMER - default n - endmenu - endmenu - - menu "Onboard Peripheral Drivers" - menuconfig BSP_USING_EXT_SRAM - bool "Enable external sram" - select RT_USING_MEMHEAP - select RT_USING_MEMHEAP_AS_HEAP - default n + config BSP_USING_WDT + bool "Enable Watchdog Timer" + select RT_USING_WDT + default n - if BSP_USING_EXT_SRAM - config BSP_EXT_SRAM_SIZE - hex "external sram size" - default 0x100000 - endif + config BSP_USING_CRC + bool "Enable CRC (CRC-32 0x04C11DB7 Polynomial)" + select RT_USING_HWCRYPTO + select RT_HWCRYPTO_USING_CRC + default n +endmenu + +menu "Onboard Peripheral Drivers" + config BSP_USING_SDIO + bool "Enable SDCARD (sdio)" + select RT_USING_SDIO + select RT_USING_DFS + select RT_USING_DFS_ELMFAT + default n + + menuconfig BSP_USING_EXT_SRAM + bool "Enable external sram" + select RT_USING_MEMHEAP + select RT_USING_MEMHEAP_AS_HEAP + default n + if BSP_USING_EXT_SRAM + config BSP_EXT_SRAM_SIZE + hex "external sram size" + default 0x100000 + endif menuconfig BSP_USING_NOR_FLASH - bool "Enable mtd nor flash" - select RT_USING_MTD_NOR - select PKG_USING_FTL_SRC - default n + bool "Enable mtd nor flash" + select RT_USING_MTD_NOR + select PKG_USING_FTL_SRC + default n + if BSP_USING_NOR_FLASH + config BSP_NOR_FLASH_SIZE + hex "mtd nor flash size" + default 0x1000000 + config BSP_NOR_FLASH_SECTOR_SIZE + hex "mtd nor flsah sector" + default 0x10000 + endif +endmenu - if BSP_USING_NOR_FLASH - config BSP_NOR_FLASH_SIZE - hex "mtd nor flash size" - default 0x1000000 - config BSP_NOR_FLASH_SECTOR_SIZE - hex "mtd nor flsah sector" - default 0x10000 - endif - endmenu - - menu "Offboard Peripheral Drivers" +menu "Offboard Peripheral Drivers" + +endmenu - endmenu - endmenu diff --git a/bsp/swm320-lq100/drivers/SConscript b/bsp/swm320-lq100/drivers/SConscript index 0d9187d78a..cddf8cc0b7 100644 --- a/bsp/swm320-lq100/drivers/SConscript +++ b/bsp/swm320-lq100/drivers/SConscript @@ -1,55 +1,51 @@ -# RT-Thread building script for component - from building import * -cwd = GetCurrentDir() +cwd = GetCurrentDir() -# add the general drivers. -src = Split(""" -board.c -""") +CPPPATH = [cwd] -# add gpio driver code -if GetDepend(['BSP_USING_GPIO']): - src += ['drv_gpio.c'] +src = Split(''' + board.c + ''') -# add serial driver code -if GetDepend('BSP_USING_UART0') or GetDepend('BSP_USING_UART1') or GetDepend('BSP_USING_UART2') or GetDepend('BSP_USING_UART3'): +if GetDepend(['RT_USING_SERIAL']): src += ['drv_uart.c'] -# add spi driver code -if GetDepend('BSP_USING_SPI0') or GetDepend('BSP_USING_SPI1'): - src += ['drv_spi.c'] +if GetDepend(['RT_USING_PIN']): + src += ['drv_gpio.c'] -# add i2c driver code -if GetDepend(['BSP_USING_I2C']): - src += ['drv_i2c.c'] +if GetDepend(['RT_USING_ADC']): + src += ['drv_adc.c'] -# add sram driver code -if GetDepend(['BSP_USING_EXT_SRAM']): - src += ['drv_sram.c'] +if GetDepend(['RT_USING_HWTIMER']): + src += ['drv_hwtimer.c'] -# add nor flash driver code -if GetDepend(['BSP_USING_NOR_FLASH']): - src += ['drv_nor_flash.c'] +if GetDepend(['RT_USING_I2C']): + src += ['drv_soft_i2c.c'] -# add pwm driver code -if GetDepend('BSP_USING_PWM0') or GetDepend('BSP_USING_PWM1') or GetDepend('BSP_USING_PWM2') or GetDepend('BSP_USING_PWM3'): +if GetDepend(['RT_USING_PWM']): src += ['drv_pwm.c'] -# add rtc driver code -if GetDepend(['BSP_USING_RTC']): +if GetDepend(['RT_USING_RTC']): src += ['drv_rtc.c'] -# add hwtimer driver code -if GetDepend(['BSP_USING_WDT']): - src += ['drv_iwg.c'] +if GetDepend(['RT_USING_SPI']): + src += ['drv_spi.c'] -# add hwtimer driver code -if GetDepend('BSP_USING_HWTIMER0') or GetDepend('BSP_USING_HWTIMER1') or GetDepend('BSP_USING_HWTIMER2') or GetDepend('BSP_USING_HWTIMER3') or GetDepend('BSP_USING_HWTIMER4') or GetDepend('BSP_USING_HWTIMER5'): - src += ['drv_hwtimer.c'] +if GetDepend(['RT_USING_WDT']): + src += ['drv_wdt.c'] -CPPPATH = [cwd] +if GetDepend(['RT_USING_SDIO']): + src += ['drv_sdio.c'] + +if GetDepend(['RT_USING_HWCRYPTO']): + src += ['drv_crypto.c'] + +if GetDepend(['BSP_USING_EXT_SRAM']): + src += ['drv_sram.c'] + +if GetDepend(['BSP_USING_NOR_FLASH']): + src += ['drv_nor_flash.c'] group = DefineGroup('Drivers', src, depend = [''], CPPPATH = CPPPATH) diff --git a/bsp/swm320-lq100/drivers/board.c b/bsp/swm320-lq100/drivers/board.c index 36e6a8f4ea..f42bd98986 100644 --- a/bsp/swm320-lq100/drivers/board.c +++ b/bsp/swm320-lq100/drivers/board.c @@ -9,16 +9,15 @@ * 2018-12-10 Zohar_Lee format file */ -#include -#if defined(BSP_USING_EXT_SRAM) && defined(RT_USING_MEMHEAP_AS_HEAP) - static struct rt_memheap system_heap; -#endif +#include "board.h" + static void bsp_clock_config(void) { SystemInit(); SysTick_Config(SystemCoreClock / RT_TICK_PER_SECOND); SysTick->CTRL |= 0x00000004UL; } + void SysTick_Handler(void) { /* enter interrupt */ @@ -29,20 +28,47 @@ void SysTick_Handler(void) /* leave interrupt */ rt_interrupt_leave(); } -#ifdef BSP_USING_EXT_SRAM - extern int rt_hw_sram_init(void); -#endif + +/** + * This function will delay for some us. + * + * @param us the delay time of us + */ +void rt_hw_us_delay(rt_uint32_t us) +{ + rt_uint32_t ticks; + rt_uint32_t told, tnow, tcnt = 0; + rt_uint32_t reload = SysTick->LOAD; + + ticks = us * reload / (1000000 / RT_TICK_PER_SECOND); + told = SysTick->VAL; + while (1) + { + tnow = SysTick->VAL; + if (tnow != told) + { + if (tnow < told) + { + tcnt += told - tnow; + } + else + { + tcnt += reload - tnow + told; + } + told = tnow; + if (tcnt >= ticks) + { + break; + } + } + } +} + void rt_hw_board_init() { bsp_clock_config(); -#ifdef BSP_USING_EXT_SRAM - rt_hw_sram_init(); -#endif -#if defined(BSP_USING_EXT_SRAM) && defined(RT_USING_MEMHEAP_AS_HEAP) - rt_system_heap_init((void *)EXT_SRAM_BEGIN, (void *)EXT_SRAM_END); - rt_memheap_init(&system_heap, "sram", (void *)HEAP_BEGIN, HEAP_SIZE); -#elif defined(RT_USING_HEAP) +#ifdef RT_USING_HEAP rt_system_heap_init((void *)HEAP_BEGIN, (void *)HEAP_END); #endif #ifdef RT_USING_COMPONENTS_INIT diff --git a/bsp/swm320-lq100/drivers/board.h b/bsp/swm320-lq100/drivers/board.h index a754b5b8d1..223018920f 100644 --- a/bsp/swm320-lq100/drivers/board.h +++ b/bsp/swm320-lq100/drivers/board.h @@ -9,32 +9,49 @@ * 2018-12-10 Zohar_Lee format file */ -#ifndef BOARD_H__ -#define BOARD_H__ +#ifndef __BOARD_H__ +#define __BOARD_H__ + #include +#include +#include +#include #include + +#ifdef __cplusplus +extern "C" +{ +#endif + #define SRAM_BASE 0x20000000 #define SRAM_SIZE 0x20000 +#define SRAM_END (SRAM_BASE + SRAM_SIZE) #ifdef BSP_USING_EXT_SRAM - #define EXT_SRAM_BASE SRAMM_BASE - #define EXT_SRAM_SIZE BSP_EXT_SRAM_SIZE - #define EXT_SRAM_BEGIN EXT_SRAM_BASE - #define EXT_SRAM_END (EXT_SRAM_BASE + EXT_SRAM_SIZE) +#define EXT_SRAM_BASE SRAMM_BASE +#define EXT_SRAM_SIZE BSP_EXT_SRAM_SIZE +#define EXT_SRAM_BEGIN EXT_SRAM_BASE +#define EXT_SRAM_END (EXT_SRAM_BASE + EXT_SRAM_SIZE) #endif -#define SRAM_END (SRAM_BASE + SRAM_SIZE) #if defined(__CC_ARM) || defined(__CLANG_ARM) extern int Image$$RW_IRAM1$$ZI$$Limit; - #define HEAP_BEGIN ((void *)&Image$$RW_IRAM1$$ZI$$Limit) +#define HEAP_BEGIN ((void *)&Image$$RW_IRAM1$$ZI$$Limit) #elif __ICCARM__ - #pragma section = "HEAP" - #define HEAP_BEGIN (__segment_end("HEAP")) +#pragma section = "HEAP" +#define HEAP_BEGIN (__segment_end("HEAP")) #else - extern int __bss_end; - #define HEAP_BEGIN ((void *)&__bss_end) +extern int __bss_end; +#define HEAP_BEGIN ((void *)&__bss_end) #endif + #define HEAP_END SRAM_END #define HEAP_SIZE (HEAP_END - (rt_uint32_t)HEAP_BEGIN) -extern void rt_hw_board_init(void); + + void rt_hw_board_init(void); + +#ifdef __cplusplus +} #endif + +#endif /* __BOARD_H__ */ diff --git a/bsp/swm320-lq100/drivers/drv_adc.c b/bsp/swm320-lq100/drivers/drv_adc.c new file mode 100644 index 0000000000..fa557fda46 --- /dev/null +++ b/bsp/swm320-lq100/drivers/drv_adc.c @@ -0,0 +1,217 @@ +/* + * Copyright (c) 2006-2018, Synwit Technology Co.,Ltd. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Change Logs: + * Date Author Notes + * 2020-5-26 lik first version + */ + +#include "drv_adc.h" + +#ifdef RT_USING_ADC +#ifdef BSP_USING_ADC + +//#define DRV_DEBUG +#define LOG_TAG "drv.adc" +#include + +static struct swm_adc_cfg adc_cfg[] = + { +#ifdef BSP_USING_ADC0 + ADC0_CFG, +#endif +#ifdef BSP_USING_ADC1 + ADC1_CFG, +#endif + +}; + +static struct swm_adc adc_drv[sizeof(adc_cfg) / sizeof(adc_cfg[0])]; + +static rt_err_t swm_adc_enabled(struct rt_adc_device *adc_device, rt_uint32_t channel, rt_bool_t enabled) +{ + struct swm_adc_cfg *cfg = RT_NULL; + RT_ASSERT(adc_device != RT_NULL); + cfg = adc_device->parent.user_data; + + if (enabled) + { + ADC_Open(cfg->ADCx); + } + else + { + ADC_Close(cfg->ADCx); + } + + return RT_EOK; +} + +static rt_uint32_t swm_adc_get_channel(rt_uint32_t channel) +{ + rt_uint32_t swm_channel = 0; + + switch (channel) + { + case 0: + swm_channel = ADC_CH0; + break; + case 1: + swm_channel = ADC_CH1; + break; + case 2: + swm_channel = ADC_CH2; + break; + case 3: + swm_channel = ADC_CH3; + break; + case 4: + swm_channel = ADC_CH4; + break; + case 5: + swm_channel = ADC_CH5; + break; + case 6: + swm_channel = ADC_CH6; + break; + case 7: + swm_channel = ADC_CH7; + break; + } + + return swm_channel; +} + +static rt_err_t swm_get_adc_value(struct rt_adc_device *adc_device, rt_uint32_t channel, rt_uint32_t *value) +{ + uint32_t adc_chn; + struct swm_adc_cfg *cfg = RT_NULL; + RT_ASSERT(adc_device != RT_NULL); + RT_ASSERT(value != RT_NULL); + cfg = adc_device->parent.user_data; + + if (channel < 8) + { + /* set stm32 ADC channel */ + adc_chn = swm_adc_get_channel(channel); + } + else + { + LOG_E("ADC channel must be between 0 and 7."); + return -RT_ERROR; + } + + /* start ADC */ + ADC_Start(cfg->ADCx); + /* Wait for the ADC to convert */ + while ((cfg->ADCx->CH[channel].STAT & 0x01) == 0) + ; + + /* get ADC value */ + *value = (rt_uint32_t)ADC_Read(cfg->ADCx, adc_chn); + + return RT_EOK; +} + +static const struct rt_adc_ops swm_adc_ops = + { + .enabled = swm_adc_enabled, + .convert = swm_get_adc_value, +}; + +static int rt_hw_adc_init(void) +{ + int i = 0; + int result = RT_EOK; + + for (i = 0; i < sizeof(adc_cfg) / sizeof(adc_cfg[0]); i++) + { + /* ADC init */ + adc_drv[i].cfg = &adc_cfg[i]; + + if (adc_drv[i].cfg->ADCx == ADC0) + { +#ifdef BSP_USING_ADC0_CHN0 + adc_drv[i].cfg->adc_initstruct.channels |= ADC_CH0; +#endif +#ifdef BSP_USING_ADC0_CHN1 + adc_drv[i].cfg->adc_initstruct.channels |= ADC_CH1; +#endif +#ifdef BSP_USING_ADC0_CHN2 + adc_drv[i].cfg->adc_initstruct.channels |= ADC_CH2; +#endif +#ifdef BSP_USING_ADC0_CHN3 + adc_drv[i].cfg->adc_initstruct.channels |= ADC_CH3; +#endif +#ifdef BSP_USING_ADC0_CHN4 + adc_drv[i].cfg->adc_initstruct.channels |= ADC_CH4; + PORT_Init(PORTA, PIN12, PORTA_PIN12_ADC0_IN4, 0); //PA.12 => ADC0.CH4 +#endif +#ifdef BSP_USING_ADC0_CHN5 + adc_drv[i].cfg->adc_initstruct.channels |= ADC_CH5; + PORT_Init(PORTA, PIN11, PORTA_PIN11_ADC0_IN5, 0); //PA.11 => ADC0.CH5 +#endif +#ifdef BSP_USING_ADC0_CHN6 + adc_drv[i].cfg->adc_initstruct.channels |= ADC_CH6; + PORT_Init(PORTA, PIN10, PORTA_PIN10_ADC0_IN6, 0); //PA.10 => ADC0.CH6 +#endif +#ifdef BSP_USING_ADC0_CHN7 + adc_drv[i].cfg->adc_initstruct.channels |= ADC_CH7; + PORT_Init(PORTA, PIN9, PORTA_PIN9_ADC0_IN7, 0); //PA.9 => ADC0.CH7 +#endif + } + else if (adc_drv[i].cfg->ADCx == ADC1) + { +#ifdef BSP_USING_ADC1_CHN0 + adc_drv[i].cfg->adc_initstruct.channels |= ADC_CH0; + PORT_Init(PORTC, PIN7, PORTC_PIN7_ADC1_IN0, 0); //PC.7 => ADC1.CH0 +#endif +#ifdef BSP_USING_ADC1_CHN1 + adc_drv[i].cfg->adc_initstruct.channels |= ADC_CH1; + PORT_Init(PORTC, PIN6, PORTC_PIN6_ADC1_IN1, 0); //PC.6 => ADC1.CH1 +#endif +#ifdef BSP_USING_ADC1_CHN2 + adc_drv[i].cfg->adc_initstruct.channels |= ADC_CH2; + PORT_Init(PORTC, PIN5, PORTC_PIN5_ADC1_IN2, 0); //PC.5 => ADC1.CH2 +#endif +#ifdef BSP_USING_ADC1_CHN3 + adc_drv[i].cfg->adc_initstruct.channels |= ADC_CH3; + PORT_Init(PORTC, PIN4, PORTC_PIN4_ADC1_IN3, 0); //PC.4 => ADC1.CH3 +#endif +#ifdef BSP_USING_ADC1_CHN4 + adc_drv[i].cfg->adc_initstruct.channels |= ADC_CH4; + PORT_Init(PORTN, PIN0, PORTN_PIN0_ADC1_IN4, 0); //PN.0 => ADC1.CH4 +#endif +#ifdef BSP_USING_ADC1_CHN5 + adc_drv[i].cfg->adc_initstruct.channels |= ADC_CH5; + PORT_Init(PORTN, PIN1, PORTN_PIN1_ADC1_IN5, 0); //PN.1 => ADC1.CH5 +#endif +#ifdef BSP_USING_ADC1_CHN6 + adc_drv[i].cfg->adc_initstruct.channels |= ADC_CH6; + PORT_Init(PORTN, PIN2, PORTN_PIN2_ADC1_IN6, 0); //PN.2 => ADC1.CH6 +#endif +#ifdef BSP_USING_ADC1_CHN7 + adc_drv[i].cfg->adc_initstruct.channels |= ADC_CH7; +#endif + } + + ADC_Init(adc_drv[i].cfg->ADCx, &(adc_drv[i].cfg->adc_initstruct)); + ADC_Open(adc_drv[i].cfg->ADCx); + /* register ADC device */ + if (rt_hw_adc_register(&adc_drv[i].adc_device, adc_drv[i].cfg->name, &swm_adc_ops, adc_drv[i].cfg) == RT_EOK) + { + LOG_D("%s init success", adc_drv[i].cfg->name); + } + else + { + LOG_E("%s register failed", adc_drv[i].cfg->name); + result = -RT_ERROR; + } + } + + return result; +} +INIT_BOARD_EXPORT(rt_hw_adc_init); +#endif /* BSP_USING_ADC */ +#endif /* RT_USING_ADC */ diff --git a/bsp/swm320-lq100/drivers/drv_adc.h b/bsp/swm320-lq100/drivers/drv_adc.h new file mode 100644 index 0000000000..04cf207137 --- /dev/null +++ b/bsp/swm320-lq100/drivers/drv_adc.h @@ -0,0 +1,71 @@ +/* + * Copyright (c) 2006-2018, Synwit Technology Co.,Ltd. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Change Logs: + * Date Author Notes + * 2020-5-26 lik first version + */ + +#ifndef __DRV_ADC_H__ +#define __DRV_ADC_H__ + +#include "board.h" + +struct swm_adc_cfg +{ + const char *name; + ADC_TypeDef *ADCx; + ADC_InitStructure adc_initstruct; +}; + +struct swm_adc +{ + struct swm_adc_cfg *cfg; + struct rt_adc_device adc_device; +}; + +#ifdef BSP_USING_ADC0 +#ifndef ADC0_CFG +#define ADC0_CFG \ + { \ + .name = "adc0", \ + .ADCx = ADC0, \ + .adc_initstruct.clk_src = ADC_CLKSRC_VCO_DIV64, \ + .adc_initstruct.clk_div = 25, \ + .adc_initstruct.pga_ref = PGA_REF_INTERNAL, \ + .adc_initstruct.channels = 0, \ + .adc_initstruct.samplAvg = ADC_AVG_SAMPLE1, \ + .adc_initstruct.trig_src = ADC_TRIGSRC_SW, \ + .adc_initstruct.Continue = 0, \ + .adc_initstruct.EOC_IEn = 0, \ + .adc_initstruct.OVF_IEn = 0, \ + .adc_initstruct.HFULL_IEn = 0, \ + .adc_initstruct.FULL_IEn = 0, \ + } +#endif /* ADC0_CFG */ +#endif /* BSP_USING_ADC0 */ + +#ifdef BSP_USING_ADC1 +#ifndef ADC1_CFG +#define ADC1_CFG \ + { \ + .name = "adc1", \ + .ADCx = ADC1, \ + .adc_initstruct.clk_src = ADC_CLKSRC_VCO_DIV64, \ + .adc_initstruct.clk_div = 25, \ + .adc_initstruct.pga_ref = PGA_REF_INTERNAL, \ + .adc_initstruct.channels = 0, \ + .adc_initstruct.samplAvg = ADC_AVG_SAMPLE1, \ + .adc_initstruct.trig_src = ADC_TRIGSRC_SW, \ + .adc_initstruct.Continue = 0, \ + .adc_initstruct.EOC_IEn = 0, \ + .adc_initstruct.OVF_IEn = 0, \ + .adc_initstruct.HFULL_IEn = 0, \ + .adc_initstruct.FULL_IEn = 0, \ + } +#endif /* ADC1_CFG */ +#endif /* BSP_USING_ADC1 */ + +#endif /* __DRV_ADC_H__ */ diff --git a/bsp/swm320-lq100/drivers/drv_crypto.c b/bsp/swm320-lq100/drivers/drv_crypto.c new file mode 100644 index 0000000000..5e97ff987e --- /dev/null +++ b/bsp/swm320-lq100/drivers/drv_crypto.c @@ -0,0 +1,226 @@ +/* + * Copyright (c) 2006-2018, Synwit Technology Co.,Ltd. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Change Logs: + * Date Author Notes + * 2020-07-10 lik first version + */ + +#include "drv_crypto.h" +#include + +#ifdef RT_USING_HWCRYPTO + +struct swm_hwcrypto_device +{ + struct rt_hwcrypto_device dev; + struct rt_mutex mutex; +}; + +#ifdef BSP_USING_CRC + +static struct hwcrypto_crc_cfg crc_backup_cfg; + +static rt_uint32_t _crc_update(struct hwcrypto_crc *ctx, const rt_uint8_t *in, rt_size_t length) +{ + rt_uint32_t result = 0; + struct swm_hwcrypto_device *swm_hw_dev = (struct swm_hwcrypto_device *)ctx->parent.device->user_data; + + struct swm_crc_cfg *hw_crc_cfg = (struct swm_crc_cfg *)(ctx->parent.contex); + + rt_mutex_take(&swm_hw_dev->mutex, RT_WAITING_FOREVER); + + if (memcmp(&crc_backup_cfg, &ctx->crc_cfg, sizeof(struct hwcrypto_crc_cfg)) != 0) + { + hw_crc_cfg->CRCx = CRC; + + hw_crc_cfg->inival = ctx->crc_cfg.last_val; + + switch (ctx->crc_cfg.width) + { + case 8: + hw_crc_cfg->crc_inbits = 2; + break; + case 16: + hw_crc_cfg->crc_inbits = 1; + break; + case 32: + hw_crc_cfg->crc_inbits = 0; + break; + default: + goto _exit; + } + switch (ctx->crc_cfg.poly) + { + case 0x1021: + hw_crc_cfg->crc_1632 = 1; + break; + case 0x04C11DB7: + hw_crc_cfg->crc_1632 = 0; + break; + default: + goto _exit; + } + + hw_crc_cfg->crc_out_not = 0; + + switch (ctx->crc_cfg.flags) + { + case 0: + case CRC_FLAG_REFIN: + hw_crc_cfg->crc_out_rev = 0; + break; + case CRC_FLAG_REFOUT: + case CRC_FLAG_REFIN | CRC_FLAG_REFOUT: + hw_crc_cfg->crc_out_rev = 1; + break; + default: + goto _exit; + } + + CRC_Init(hw_crc_cfg->CRCx, (hw_crc_cfg->crc_inbits << 1) | hw_crc_cfg->crc_1632, hw_crc_cfg->crc_out_not, hw_crc_cfg->crc_out_rev, hw_crc_cfg->inival); + memcpy(&crc_backup_cfg, &ctx->crc_cfg, sizeof(struct hwcrypto_crc_cfg)); + } + + for (uint32_t i = 0; i < length; i++) + CRC_Write((uint32_t)in[i]); + result = CRC_Result(); + + ctx->crc_cfg.last_val = result; + + crc_backup_cfg.last_val = ctx->crc_cfg.last_val; + result = (result ? result ^ (ctx->crc_cfg.xorout) : result); + +_exit: + rt_mutex_release(&swm_hw_dev->mutex); + + return result; +} + +static const struct hwcrypto_crc_ops crc_ops = + { + .update = _crc_update, +}; +#endif /* BSP_USING_CRC */ + +static rt_err_t _crypto_create(struct rt_hwcrypto_ctx *ctx) +{ + rt_err_t res = RT_EOK; + + switch (ctx->type & HWCRYPTO_MAIN_TYPE_MASK) + { +#if defined(BSP_USING_CRC) + case HWCRYPTO_TYPE_CRC: + { + struct swm_crc_cfg *contex = rt_calloc(1, sizeof(struct swm_crc_cfg)); + if (RT_NULL == contex) + { + res = -RT_ERROR; + break; + } + contex->CRCx = DEFAULT_CRC; + contex->inival = DEFAULT_INIVAL; + contex->crc_inbits = DEFAULT_INBITS; + contex->crc_1632 = DEFAULT_CRC1632; + contex->crc_out_not = DEFAULT_OUT_NOT; + contex->crc_out_rev = DEFAULT_OUT_REV; + + ctx->contex = contex; + ((struct hwcrypto_crc *)ctx)->ops = &crc_ops; + break; + } +#endif /* BSP_USING_CRC */ + default: + res = -RT_ERROR; + break; + } + return res; +} + +static void _crypto_destroy(struct rt_hwcrypto_ctx *ctx) +{ + struct swm_crc_cfg *hw_crc_cfg = (struct swm_crc_cfg *)(ctx->contex); + switch (ctx->type & HWCRYPTO_MAIN_TYPE_MASK) + { +#if defined(BSP_USING_CRC) + case HWCRYPTO_TYPE_CRC: + hw_crc_cfg->CRCx->CR &= ~CRC_CR_EN_Msk; + break; +#endif /* BSP_USING_CRC */ + default: + break; + } + + rt_free(ctx->contex); +} + +static rt_err_t _crypto_clone(struct rt_hwcrypto_ctx *des, const struct rt_hwcrypto_ctx *src) +{ + rt_err_t res = RT_EOK; + + switch (src->type & HWCRYPTO_MAIN_TYPE_MASK) + { +#if defined(BSP_USING_CRC) + case HWCRYPTO_TYPE_CRC: + if (des->contex && src->contex) + { + rt_memcpy(des->contex, src->contex, sizeof(struct swm_crc_cfg)); + } + break; +#endif /* BSP_USING_CRC */ + default: + res = -RT_ERROR; + break; + } + return res; +} + +static void _crypto_reset(struct rt_hwcrypto_ctx *ctx) +{ + struct swm_crc_cfg *hw_crc_cfg = (struct swm_crc_cfg *)(ctx->contex); + switch (ctx->type & HWCRYPTO_MAIN_TYPE_MASK) + { +#if defined(BSP_USING_CRC) + case HWCRYPTO_TYPE_CRC: + hw_crc_cfg->CRCx->CR &= ~CRC_CR_EN_Msk; + break; +#endif /* BSP_USING_CRC */ + default: + break; + } +} + +static const struct rt_hwcrypto_ops _ops = + { + .create = _crypto_create, + .destroy = _crypto_destroy, + .copy = _crypto_clone, + .reset = _crypto_reset, +}; + +int rt_hw_crypto_init(void) +{ + static struct swm_hwcrypto_device _crypto_dev; + rt_uint32_t cpuid[2] = {0}; + + _crypto_dev.dev.ops = &_ops; + + cpuid[0] = SCB->CPUID; + _crypto_dev.dev.id = 0; + rt_memcpy(&_crypto_dev.dev.id, cpuid, 8); + + _crypto_dev.dev.user_data = &_crypto_dev; + + if (rt_hwcrypto_register(&_crypto_dev.dev, RT_HWCRYPTO_DEFAULT_NAME) != RT_EOK) + { + return -1; + } + rt_mutex_init(&_crypto_dev.mutex, RT_HWCRYPTO_DEFAULT_NAME, RT_IPC_FLAG_FIFO); + return 0; +} +INIT_BOARD_EXPORT(rt_hw_crypto_init); + + +#endif /* RT_USING_HWCRYPTO */ diff --git a/bsp/swm320-lq100/drivers/drv_crypto.h b/bsp/swm320-lq100/drivers/drv_crypto.h new file mode 100644 index 0000000000..3f301f4553 --- /dev/null +++ b/bsp/swm320-lq100/drivers/drv_crypto.h @@ -0,0 +1,40 @@ +/* + * Copyright (c) 2006-2018, Synwit Technology Co.,Ltd. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Change Logs: + * Date Author Notes + * 2020-07-10 lik first version + */ + +#ifndef __DRV_CRYPTO_H__ +#define __DRV_CRYPTO_H__ + +#include "board.h" + +/* swm config class */ +struct swm_crc_cfg +{ + CRC_TypeDef *CRCx; + uint32_t inival; + uint8_t crc_inbits; + uint8_t crc_1632; + uint8_t crc_out_not; + uint8_t crc_out_rev; +}; + +#ifdef BSP_USING_CRC + +#define DEFAULT_CRC (CRC) +#define DEFAULT_INIVAL (0x00000000) +#define DEFAULT_INBITS (2) +#define DEFAULT_CRC1632 (0) +#define DEFAULT_OUT_NOT (0) +#define DEFAULT_OUT_REV (0) + +#endif /* BSP_USING_CRC */ + +int rt_hw_crypto_init(void); + +#endif /* __DRV_CRYPTO_H__ */ diff --git a/bsp/swm320-lq100/drivers/drv_gpio.c b/bsp/swm320-lq100/drivers/drv_gpio.c index 439f36f379..91f0e94f02 100644 --- a/bsp/swm320-lq100/drivers/drv_gpio.c +++ b/bsp/swm320-lq100/drivers/drv_gpio.c @@ -6,162 +6,250 @@ * Change Logs: * Date Author Notes * 2018-05-31 ZYH first version - * 2018-12-10 Zohar_Lee 修复bug + * 2018-12-10 Zohar_Lee fix bug + * 2020-07-10 lik rewrite */ -#include -#include -#include -#include -#include -#include -#include +#include "drv_gpio.h" -typedef void (*pin_callback_t)(void *args); -struct pin -{ - uint32_t package_index; - const char *name; - GPIO_TypeDef *port; - uint32_t group_index; - IRQn_Type irq; - rt_uint32_t irq_mode; - pin_callback_t callback; - void *callback_args; -}; -typedef struct pin pin_t; - -#define SWM32_PIN(a, b, c, d) \ - { \ - a, #b, GPIO##c, d, GPIO##c##_IRQn \ - } -#define GPIO0 ((GPIO_TypeDef *)(0)) -#define GPIO0_IRQn (GPIOA0_IRQn) +#ifdef RT_USING_PIN +#ifdef BSP_USING_GPIO + +static const struct swm_pin_index pins[] = + { + __SWM_PIN(0, A, 0), + __SWM_PIN(1, A, 1), + __SWM_PIN(2, A, 2), + __SWM_PIN(3, A, 3), + __SWM_PIN(4, A, 4), + __SWM_PIN(5, A, 5), + __SWM_PIN(6, A, 6), + __SWM_PIN(7, A, 7), + __SWM_PIN(8, A, 8), + __SWM_PIN(9, A, 9), + __SWM_PIN(10, A, 10), + __SWM_PIN(11, A, 11), + __SWM_PIN(12, A, 12), + + __SWM_PIN(13, B, 0), + __SWM_PIN(14, B, 1), + __SWM_PIN(15, B, 2), + __SWM_PIN(16, B, 3), + __SWM_PIN(17, B, 4), + __SWM_PIN(18, B, 5), + __SWM_PIN(19, B, 6), + __SWM_PIN(20, B, 7), + __SWM_PIN(21, B, 8), + __SWM_PIN(22, B, 9), + __SWM_PIN(23, B, 10), + __SWM_PIN(24, B, 11), + __SWM_PIN(25, B, 12), + + __SWM_PIN(26, C, 0), + __SWM_PIN(27, C, 1), + __SWM_PIN(28, C, 2), + __SWM_PIN(29, C, 3), + __SWM_PIN(30, C, 4), + __SWM_PIN(31, C, 5), + __SWM_PIN(32, C, 6), + __SWM_PIN(33, C, 7), + + __SWM_PIN(34, M, 0), + __SWM_PIN(35, M, 1), + __SWM_PIN(36, M, 2), + __SWM_PIN(37, M, 3), + __SWM_PIN(38, M, 4), + __SWM_PIN(39, M, 5), + __SWM_PIN(40, M, 6), + __SWM_PIN(41, M, 7), + __SWM_PIN(42, M, 8), + __SWM_PIN(43, M, 9), + __SWM_PIN(44, M, 10), + __SWM_PIN(45, M, 11), + __SWM_PIN(46, M, 12), + __SWM_PIN(47, M, 13), + __SWM_PIN(48, M, 14), + __SWM_PIN(49, M, 15), + __SWM_PIN(50, M, 16), + __SWM_PIN(51, M, 17), + __SWM_PIN(52, M, 18), + __SWM_PIN(53, M, 19), + __SWM_PIN(54, M, 20), + __SWM_PIN(55, M, 21), + + __SWM_PIN(56, N, 0), + __SWM_PIN(57, N, 1), + __SWM_PIN(58, N, 2), + __SWM_PIN(59, N, 3), + __SWM_PIN(60, N, 4), + __SWM_PIN(61, N, 5), + __SWM_PIN(62, N, 6), + __SWM_PIN(63, N, 7), + __SWM_PIN(64, N, 8), + __SWM_PIN(65, N, 9), + __SWM_PIN(66, N, 10), + __SWM_PIN(67, N, 11), + __SWM_PIN(68, N, 12), + __SWM_PIN(69, N, 13), + __SWM_PIN(70, N, 14), + __SWM_PIN(71, N, 15), + __SWM_PIN(72, N, 16), + __SWM_PIN(73, N, 17), + __SWM_PIN(74, N, 18), + __SWM_PIN(75, N, 19), + + __SWM_PIN(76, P, 0), + __SWM_PIN(77, P, 1), + __SWM_PIN(78, P, 2), + __SWM_PIN(79, P, 3), + __SWM_PIN(80, P, 4), + __SWM_PIN(81, P, 5), + __SWM_PIN(82, P, 6), + __SWM_PIN(83, P, 7), + __SWM_PIN(84, P, 8), + __SWM_PIN(85, P, 9), + __SWM_PIN(86, P, 10), + __SWM_PIN(87, P, 11), + __SWM_PIN(88, P, 12), + __SWM_PIN(89, P, 13), + __SWM_PIN(90, P, 14), + __SWM_PIN(91, P, 15), + __SWM_PIN(92, P, 16), + __SWM_PIN(93, P, 17), + __SWM_PIN(94, P, 18), + __SWM_PIN(95, P, 19), + __SWM_PIN(96, P, 20), + __SWM_PIN(97, P, 21), + __SWM_PIN(98, P, 22), + __SWM_PIN(99, P, 23)}; + +static struct rt_pin_irq_hdr pin_irq_hdr_tab[] = + { + {0, 0, RT_NULL, RT_NULL}, + {1, 0, RT_NULL, RT_NULL}, + {2, 0, RT_NULL, RT_NULL}, + {3, 0, RT_NULL, RT_NULL}, + {4, 0, RT_NULL, RT_NULL}, + {5, 0, RT_NULL, RT_NULL}, + {6, 0, RT_NULL, RT_NULL}, + {7, 0, RT_NULL, RT_NULL}, + {8, 0, RT_NULL, RT_NULL}, + {9, 0, RT_NULL, RT_NULL}, + {10, 0, RT_NULL, RT_NULL}, + {11, 0, RT_NULL, RT_NULL}, + {12, 0, RT_NULL, RT_NULL}, + {13, 0, RT_NULL, RT_NULL}, + {14, 0, RT_NULL, RT_NULL}, + {15, 0, RT_NULL, RT_NULL}, + {16, 0, RT_NULL, RT_NULL}, + {17, 0, RT_NULL, RT_NULL}, + {18, 0, RT_NULL, RT_NULL}, + {19, 0, RT_NULL, RT_NULL}, + {20, 0, RT_NULL, RT_NULL}, + {21, 0, RT_NULL, RT_NULL}, + {22, 0, RT_NULL, RT_NULL}, + {23, 0, RT_NULL, RT_NULL}, + {24, 0, RT_NULL, RT_NULL}, + {25, 0, RT_NULL, RT_NULL}, + {26, 0, RT_NULL, RT_NULL}, + {27, 0, RT_NULL, RT_NULL}, + {28, 0, RT_NULL, RT_NULL}, + {29, 0, RT_NULL, RT_NULL}, + {30, 0, RT_NULL, RT_NULL}, + {31, 0, RT_NULL, RT_NULL}, + {32, 0, RT_NULL, RT_NULL}, + {33, 0, RT_NULL, RT_NULL}, + {34, 0, RT_NULL, RT_NULL}, + {35, 0, RT_NULL, RT_NULL}, + {36, 0, RT_NULL, RT_NULL}, + {37, 0, RT_NULL, RT_NULL}, + {38, 0, RT_NULL, RT_NULL}, + {39, 0, RT_NULL, RT_NULL}, + {40, 0, RT_NULL, RT_NULL}, + {41, 0, RT_NULL, RT_NULL}, + {42, 0, RT_NULL, RT_NULL}, + {43, 0, RT_NULL, RT_NULL}, + {44, 0, RT_NULL, RT_NULL}, + {45, 0, RT_NULL, RT_NULL}, + {46, 0, RT_NULL, RT_NULL}, + {47, 0, RT_NULL, RT_NULL}, + {48, 0, RT_NULL, RT_NULL}, + {49, 0, RT_NULL, RT_NULL}, + {50, 0, RT_NULL, RT_NULL}, + {51, 0, RT_NULL, RT_NULL}, + {52, 0, RT_NULL, RT_NULL}, + {53, 0, RT_NULL, RT_NULL}, + {54, 0, RT_NULL, RT_NULL}, + {55, 0, RT_NULL, RT_NULL}, + {56, 0, RT_NULL, RT_NULL}, + {57, 0, RT_NULL, RT_NULL}, + {58, 0, RT_NULL, RT_NULL}, + {59, 0, RT_NULL, RT_NULL}, + {60, 0, RT_NULL, RT_NULL}, + {61, 0, RT_NULL, RT_NULL}, + {62, 0, RT_NULL, RT_NULL}, + {63, 0, RT_NULL, RT_NULL}, + {64, 0, RT_NULL, RT_NULL}, + {65, 0, RT_NULL, RT_NULL}, + {66, 0, RT_NULL, RT_NULL}, + {67, 0, RT_NULL, RT_NULL}, + {68, 0, RT_NULL, RT_NULL}, + {69, 0, RT_NULL, RT_NULL}, + {70, 0, RT_NULL, RT_NULL}, + {71, 0, RT_NULL, RT_NULL}, + {72, 0, RT_NULL, RT_NULL}, + {73, 0, RT_NULL, RT_NULL}, + {74, 0, RT_NULL, RT_NULL}, + {75, 0, RT_NULL, RT_NULL}, + {76, 0, RT_NULL, RT_NULL}, + {77, 0, RT_NULL, RT_NULL}, + {78, 0, RT_NULL, RT_NULL}, + {79, 0, RT_NULL, RT_NULL}, + {80, 0, RT_NULL, RT_NULL}, + {81, 0, RT_NULL, RT_NULL}, + {82, 0, RT_NULL, RT_NULL}, + {83, 0, RT_NULL, RT_NULL}, + {84, 0, RT_NULL, RT_NULL}, + {85, 0, RT_NULL, RT_NULL}, + {86, 0, RT_NULL, RT_NULL}, + {87, 0, RT_NULL, RT_NULL}, + {88, 0, RT_NULL, RT_NULL}, + {89, 0, RT_NULL, RT_NULL}, + {90, 0, RT_NULL, RT_NULL}, + {91, 0, RT_NULL, RT_NULL}, + {92, 0, RT_NULL, RT_NULL}, + {93, 0, RT_NULL, RT_NULL}, + {94, 0, RT_NULL, RT_NULL}, + {95, 0, RT_NULL, RT_NULL}, + {96, 0, RT_NULL, RT_NULL}, + {97, 0, RT_NULL, RT_NULL}, + {98, 0, RT_NULL, RT_NULL}, + {99, 0, RT_NULL, RT_NULL}}; -const static pin_t swm32_pin_map[] = -{ - SWM32_PIN(0, None, 0, 0), - SWM32_PIN(1, ADC0 CH3, 0, 0), - SWM32_PIN(2, ADC0 REFP, 0, 0), - SWM32_PIN(3, Cap0, 0, 0), - SWM32_PIN(4, B12, B, 12), - SWM32_PIN(5, RTC VDD, 0, 0), - SWM32_PIN(6, N14, N, 14), - SWM32_PIN(7, N13, N, 13), - SWM32_PIN(8, N12, N, 12), - SWM32_PIN(9, N11, N, 11), - SWM32_PIN(10, VDD 3.3V, 0, 0), - SWM32_PIN(11, VSS 3.3V, 0, 0), - SWM32_PIN(12, Cap 2, 0, 0), - SWM32_PIN(13, N9, N, 9), - SWM32_PIN(14, N10, N, 10), - SWM32_PIN(15, Cap 1, 0, 0), - SWM32_PIN(16, AVSS, 0, 0), - SWM32_PIN(17, AVDD, 0, 0), - SWM32_PIN(18, N2, N, 2), - SWM32_PIN(19, N1, N, 1), - SWM32_PIN(20, N0, N, 0), - SWM32_PIN(21, C4, C, 4), - SWM32_PIN(22, C5, C, 5), - SWM32_PIN(23, C6, C, 6), - SWM32_PIN(24, C7, C, 7), - SWM32_PIN(25, C2, C, 2), - SWM32_PIN(26, C3, C, 3), - SWM32_PIN(27, XHIN, 0, 0), - SWM32_PIN(28, XHOUT, 0, 0), - SWM32_PIN(29, RESET, 0, 0), - SWM32_PIN(30, M2, M, 2), - SWM32_PIN(31, M3, M, 3), - SWM32_PIN(32, M4, M, 4), - SWM32_PIN(33, M5, M, 5), - SWM32_PIN(34, M6, M, 6), - SWM32_PIN(35, M7, M, 7), - SWM32_PIN(36, M8, M, 8), - SWM32_PIN(37, M9, M, 9), - SWM32_PIN(38, M10, M, 10), - SWM32_PIN(39, M11, M, 11), - SWM32_PIN(40, M12, M, 12), - SWM32_PIN(41, M13, M, 13), - SWM32_PIN(42, M14, M, 14), - SWM32_PIN(43, M15, M, 15), - SWM32_PIN(44, M16, M, 16), - SWM32_PIN(45, M17, M, 17), - SWM32_PIN(46, M18, M, 18), - SWM32_PIN(47, M19, M, 19), - SWM32_PIN(48, M20, M, 20), - SWM32_PIN(49, M21, M, 21), - SWM32_PIN(50, VDDIO, 0, 0), - SWM32_PIN(51, M1, M, 1), - SWM32_PIN(52, M0, M, 0), - SWM32_PIN(53, P0, P, 0), - SWM32_PIN(54, P1, P, 1), - SWM32_PIN(55, P2, P, 2), - SWM32_PIN(56, P3, P, 3), - SWM32_PIN(57, P4, P, 4), - SWM32_PIN(58, P5, P, 5), - SWM32_PIN(59, P6, P, 6), - SWM32_PIN(60, P7, P, 7), - SWM32_PIN(61, P8, P, 8), - SWM32_PIN(62, P9, P, 9), - SWM32_PIN(63, P10, P, 10), - SWM32_PIN(64, P11, P, 11), - SWM32_PIN(65, P12, P, 12), - SWM32_PIN(66, P13, P, 13), - SWM32_PIN(67, P14, P, 14), - SWM32_PIN(68, P15, P, 15), - SWM32_PIN(69, P16, P, 16), - SWM32_PIN(70, P17, P, 17), - SWM32_PIN(71, P18, P, 18), - SWM32_PIN(72, P19, P, 19), - SWM32_PIN(73, P20, P, 20), - SWM32_PIN(74, P21, P, 21), - SWM32_PIN(75, P22, P, 22), - SWM32_PIN(76, P23, P, 23), - SWM32_PIN(77, B0, B, 0), - SWM32_PIN(78, A0, A, 0), - SWM32_PIN(79, A1, A, 1), - SWM32_PIN(80, A2, A, 2), - SWM32_PIN(81, A3, A, 3), - SWM32_PIN(82, A4, A, 4), - SWM32_PIN(83, A5, A, 5), - SWM32_PIN(84, VSSIO, 0, 0), - SWM32_PIN(85, C1, C, 1), - SWM32_PIN(86, N19, N, 19), - SWM32_PIN(87, N18, N, 18), - SWM32_PIN(88, N17, N, 17), - SWM32_PIN(89, N16, N, 16), - SWM32_PIN(90, N15, N, 15), - SWM32_PIN(91, N8, N, 8), - SWM32_PIN(92, N7, N, 7), - SWM32_PIN(93, N6, N, 6), - SWM32_PIN(94, N5, N, 5), - SWM32_PIN(95, N4, N, 4), - SWM32_PIN(96, N3, N, 3), - SWM32_PIN(97, A9, A, 9), - SWM32_PIN(98, A10, A, 10), - SWM32_PIN(99, A11, A, 11), - SWM32_PIN(100, A12, A, 12) -}; #define ITEM_NUM(items) sizeof(items) / sizeof(items[0]) -static pin_t *get_pin(uint8_t pin) + +static const struct swm_pin_index *get_pin(uint8_t pin) { - pin_t *index; - if (pin < ITEM_NUM(swm32_pin_map)) + const struct swm_pin_index *index; + + if (pin < ITEM_NUM(pins)) { - index = (pin_t *)&swm32_pin_map[pin]; - if (index->port == GPIO0) + index = &pins[pin]; + if (index->gpio == GPIO0) index = RT_NULL; } else { index = RT_NULL; } + return index; -}; +} -static void swm320_pin_write(rt_device_t dev, rt_base_t pin, rt_base_t value) +static void swm_pin_write(rt_device_t dev, rt_base_t pin, rt_base_t value) { - pin_t *index; + const struct swm_pin_index *index; + index = get_pin(pin); if (index == RT_NULL) { @@ -169,201 +257,206 @@ static void swm320_pin_write(rt_device_t dev, rt_base_t pin, rt_base_t value) } if (value) { - GPIO_SetBit(index->port, index->group_index); + GPIO_SetBit(index->gpio, index->pin); } else { - GPIO_ClrBit(index->port, index->group_index); + GPIO_ClrBit(index->gpio, index->pin); } } -static int swm320_pin_read(rt_device_t dev, rt_base_t pin) +static int swm_pin_read(rt_device_t dev, rt_base_t pin) { - pin_t *index; + const struct swm_pin_index *index; + index = get_pin(pin); if (index == RT_NULL) { return PIN_LOW; } - return GPIO_GetBit(index->port, index->group_index); + return (int)GPIO_GetBit(index->gpio, index->pin); } -static void swm320_pin_mode(rt_device_t dev, rt_base_t pin, rt_base_t mode) +static void swm_pin_mode(rt_device_t dev, rt_base_t pin, rt_base_t mode) { - pin_t *index; + const struct swm_pin_index *index; int dir = 0; int pull_up = 0; int pull_down = 0; + index = get_pin(pin); if (index == RT_NULL) { return; } /* Configure GPIO_InitStructure */ - if (mode == PIN_MODE_OUTPUT) + switch (mode) { + case PIN_MODE_OUTPUT: /* output setting */ dir = 1; - } - else if (mode == PIN_MODE_INPUT) - { + break; + case PIN_MODE_INPUT: /* input setting: not pull. */ dir = 0; - } - else if (mode == PIN_MODE_INPUT_PULLUP) - { + break; + case PIN_MODE_INPUT_PULLUP: /* input setting: pull up. */ dir = 0; pull_up = 1; - } - else if (mode == PIN_MODE_INPUT_PULLDOWN) - { + break; + case PIN_MODE_INPUT_PULLDOWN: /* input setting: pull down. */ dir = 0; pull_down = 1; - } - else if (mode == PIN_MODE_OUTPUT_OD) - { + break; + case PIN_MODE_OUTPUT_OD: /* output setting: od. */ dir = 1; pull_up = 1; + break; } - GPIO_Init(index->port, index->group_index, dir, pull_up, pull_down); + + GPIO_Init(index->gpio, index->pin, dir, pull_up, pull_down); } -static rt_err_t swm320_pin_attach_irq(struct rt_device *device, - rt_int32_t pin, - rt_uint32_t mode, - pin_callback_t cb, - void *args) +static rt_err_t swm_pin_attach_irq(struct rt_device *device, + rt_int32_t pin, + rt_uint32_t mode, + void (*hdr)(void *args), + void *args) { - pin_t *index; + const struct swm_pin_index *index; rt_base_t level; + index = get_pin(pin); if (index == RT_NULL) { - return RT_EINVAL; + return RT_ENOSYS; } - level = rt_hw_interrupt_disable(); - index->callback = cb; - index->callback_args = args; - index->irq_mode = mode; + level = rt_hw_interrupt_disable(); + if (pin_irq_hdr_tab[pin].pin == pin && + pin_irq_hdr_tab[pin].mode == mode && + pin_irq_hdr_tab[pin].hdr == hdr && + pin_irq_hdr_tab[pin].args == args) + { + rt_hw_interrupt_enable(level); + return RT_EOK; + } + pin_irq_hdr_tab[pin].pin = pin; + pin_irq_hdr_tab[pin].mode = mode; + pin_irq_hdr_tab[pin].hdr = hdr; + pin_irq_hdr_tab[pin].args = args; rt_hw_interrupt_enable(level); return RT_EOK; } -static rt_err_t swm320_pin_detach_irq(struct rt_device *device, rt_int32_t pin) +static rt_err_t swm_pin_detach_irq(struct rt_device *device, rt_int32_t pin) { - pin_t *index; + const struct swm_pin_index *index; rt_base_t level; + index = get_pin(pin); if (index == RT_NULL) { - return RT_EINVAL; + return RT_ENOSYS; } + level = rt_hw_interrupt_disable(); - index->callback = 0; - index->callback_args = 0; - index->irq_mode = 0; + pin_irq_hdr_tab[pin].mode = 0; + pin_irq_hdr_tab[pin].hdr = RT_NULL; + pin_irq_hdr_tab[pin].args = RT_NULL; rt_hw_interrupt_enable(level); return RT_EOK; } -static rt_err_t swm320_pin_irq_enable(struct rt_device *device, - rt_base_t pin, - rt_uint32_t enabled) +static rt_err_t swm_pin_irq_enable(struct rt_device *device, + rt_base_t pin, + rt_uint32_t enabled) { - pin_t *index; + const struct swm_pin_index *index; rt_base_t level = 0; + index = get_pin(pin); if (index == RT_NULL) { - return RT_EINVAL; + return RT_ENOSYS; } + if (enabled == PIN_IRQ_ENABLE) { - switch (index->irq_mode) + switch (pin_irq_hdr_tab[pin].mode) { case PIN_IRQ_MODE_RISING: - GPIO_Init(index->port, index->group_index, 0, 0, 1); - EXTI_Init(index->port, index->group_index, EXTI_RISE_EDGE); + GPIO_Init(index->gpio, index->pin, 0, 0, 1); + EXTI_Init(index->gpio, index->pin, EXTI_RISE_EDGE); break; case PIN_IRQ_MODE_FALLING: - GPIO_Init(index->port, index->group_index, 0, 1, 0); - EXTI_Init(index->port, index->group_index, EXTI_FALL_EDGE); + GPIO_Init(index->gpio, index->pin, 0, 1, 0); + EXTI_Init(index->gpio, index->pin, EXTI_FALL_EDGE); break; case PIN_IRQ_MODE_RISING_FALLING: - GPIO_Init(index->port, index->group_index, 0, 1, 1); - EXTI_Init(index->port, index->group_index, EXTI_BOTH_EDGE); + GPIO_Init(index->gpio, index->pin, 0, 1, 1); + EXTI_Init(index->gpio, index->pin, EXTI_BOTH_EDGE); break; case PIN_IRQ_MODE_HIGH_LEVEL: - GPIO_Init(index->port, index->group_index, 0, 0, 1); - EXTI_Init(index->port, index->group_index, EXTI_HIGH_LEVEL); + GPIO_Init(index->gpio, index->pin, 0, 0, 1); + EXTI_Init(index->gpio, index->pin, EXTI_HIGH_LEVEL); break; case PIN_IRQ_MODE_LOW_LEVEL: - GPIO_Init(index->port, index->group_index, 0, 1, 0); - EXTI_Init(index->port, index->group_index, EXTI_LOW_LEVEL); + GPIO_Init(index->gpio, index->pin, 0, 1, 0); + EXTI_Init(index->gpio, index->pin, EXTI_LOW_LEVEL); break; default: - rt_hw_interrupt_enable(level); return RT_EINVAL; } level = rt_hw_interrupt_disable(); NVIC_EnableIRQ(index->irq); - EXTI_Open(index->port, index->group_index); + EXTI_Open(index->gpio, index->pin); rt_hw_interrupt_enable(level); } else if (enabled == PIN_IRQ_DISABLE) { + level = rt_hw_interrupt_disable(); NVIC_DisableIRQ(index->irq); - EXTI_Close(index->port, index->group_index); + EXTI_Close(index->gpio, index->pin); + rt_hw_interrupt_enable(level); } else { - return RT_ENOSYS; + return -RT_ENOSYS; } return RT_EOK; } -const static struct rt_pin_ops swm320_pin_ops = -{ - swm320_pin_mode, - swm320_pin_write, - swm320_pin_read, - swm320_pin_attach_irq, - swm320_pin_detach_irq, - swm320_pin_irq_enable, - RT_NULL, -}; - -int rt_hw_pin_init(void) -{ - int result; - result = rt_device_pin_register("pin", &swm320_pin_ops, RT_NULL); - return result; -} -INIT_BOARD_EXPORT(rt_hw_pin_init); +const static struct rt_pin_ops swm_pin_ops = + { + .pin_mode = swm_pin_mode, + .pin_write = swm_pin_write, + .pin_read = swm_pin_read, + .pin_attach_irq = swm_pin_attach_irq, + .pin_detach_irq = swm_pin_detach_irq, + .pin_irq_enable = swm_pin_irq_enable}; -void GPIOA_Handler(void) +static void rt_hw_pin_isr(GPIO_TypeDef *GPIOx) { static int gpio[24]; int index = 0; static int init = 0; - pin_t *pin; - /* enter interrupt */ - rt_interrupt_enter(); + const struct swm_pin_index *pin; + if (init == 0) { init = 1; - for (pin = (pin_t *)&swm32_pin_map[1]; - pin->package_index < ITEM_NUM(swm32_pin_map); - pin++) + for (pin = &pins[0]; + pin->index < ITEM_NUM(pins); + pin++) { - if (pin->port == GPIOA) + if (pin->gpio == GPIOx) { - gpio[index] = pin->package_index; + gpio[index] = pin->index; index++; RT_ASSERT(index <= 24) } @@ -372,228 +465,64 @@ void GPIOA_Handler(void) for (index = 0; index < 24; index++) { pin = get_pin(gpio[index]); - if (index != RT_NULL) + if (EXTI_State(pin->gpio, pin->pin)) { - if (EXTI_State(pin->port, pin->group_index)) + EXTI_Clear(pin->gpio, pin->pin); + if (pin_irq_hdr_tab[pin->index].hdr) { - EXTI_Clear(pin->port, pin->group_index); - if (pin->callback) - { - pin->callback(pin->callback_args); - } + pin_irq_hdr_tab[pin->index].hdr(pin_irq_hdr_tab[pin->index].args); } } } - /* leave interrupt */ +} + +void GPIOA_Handler(void) +{ + rt_interrupt_enter(); + rt_hw_pin_isr(GPIOA); rt_interrupt_leave(); } void GPIOB_Handler(void) { - static int gpio[24]; - int index = 0; - static int init = 0; - pin_t *pin; - /* enter interrupt */ rt_interrupt_enter(); - if (init == 0) - { - init = 1; - for (pin = (pin_t *)&swm32_pin_map[1]; - pin->package_index < ITEM_NUM(swm32_pin_map); - pin++) - { - if (pin->port == GPIOB) - { - gpio[index] = pin->package_index; - index++; - RT_ASSERT(index <= 24) - } - } - } - for (index = 0; index < 24; index++) - { - pin = get_pin(gpio[index]); - if (index != RT_NULL) - { - if (EXTI_State(pin->port, pin->group_index)) - { - EXTI_Clear(pin->port, pin->group_index); - if (pin->callback) - { - pin->callback(pin->callback_args); - } - } - } - } - /* leave interrupt */ + rt_hw_pin_isr(GPIOB); rt_interrupt_leave(); } void GPIOC_Handler(void) { - static int gpio[24]; - int index = 0; - static int init = 0; - pin_t *pin; - /* enter interrupt */ rt_interrupt_enter(); - if (init == 0) - { - init = 1; - for (pin = (pin_t *)&swm32_pin_map[1]; - pin->package_index < ITEM_NUM(swm32_pin_map); - pin++) - { - if (pin->port == GPIOC) - { - gpio[index] = pin->package_index; - index++; - RT_ASSERT(index <= 24) - } - } - } - for (index = 0; index < 24; index++) - { - pin = get_pin(gpio[index]); - if (index != RT_NULL) - { - if (EXTI_State(pin->port, pin->group_index)) - { - EXTI_Clear(pin->port, pin->group_index); - if (pin->callback) - { - pin->callback(pin->callback_args); - } - } - } - } - /* leave interrupt */ + rt_hw_pin_isr(GPIOC); rt_interrupt_leave(); } void GPIOM_Handler(void) { - static int gpio[24]; - int index = 0; - static int init = 0; - pin_t *pin; - /* enter interrupt */ rt_interrupt_enter(); - if (init == 0) - { - init = 1; - for (pin = (pin_t *)&swm32_pin_map[1]; - pin->package_index < ITEM_NUM(swm32_pin_map); - pin++) - { - if (pin->port == GPIOM) - { - gpio[index] = pin->package_index; - index++; - RT_ASSERT(index <= 24) - } - } - } - for (index = 0; index < 24; index++) - { - pin = get_pin(gpio[index]); - if (index != RT_NULL) - { - if (EXTI_State(pin->port, pin->group_index)) - { - EXTI_Clear(pin->port, pin->group_index); - if (pin->callback) - { - pin->callback(pin->callback_args); - } - } - } - } - /* leave interrupt */ + rt_hw_pin_isr(GPIOM); rt_interrupt_leave(); } void GPION_Handler(void) { - static int gpio[24]; - int index = 0; - static int init = 0; - pin_t *pin; - /* enter interrupt */ rt_interrupt_enter(); - if (init == 0) - { - init = 1; - for (pin = (pin_t *)&swm32_pin_map[1]; - pin->package_index < ITEM_NUM(swm32_pin_map); - pin++) - { - if (pin->port == GPION) - { - gpio[index] = pin->package_index; - index++; - RT_ASSERT(index <= 24) - } - } - } - for (index = 0; index < 24; index++) - { - pin = get_pin(gpio[index]); - if (index != RT_NULL) - { - if (EXTI_State(pin->port, pin->group_index)) - { - EXTI_Clear(pin->port, pin->group_index); - if (pin->callback) - { - pin->callback(pin->callback_args); - } - } - } - } - /* leave interrupt */ + rt_hw_pin_isr(GPION); rt_interrupt_leave(); } void GPIOP_Handler(void) { - static int gpio[24]; - int index = 0; - static int init = 0; - pin_t *pin; - /* enter interrupt */ rt_interrupt_enter(); - if (init == 0) - { - init = 1; - for (pin = (pin_t *)&swm32_pin_map[1]; - pin->package_index < ITEM_NUM(swm32_pin_map); - pin++) - { - if (pin->port == GPIOP) - { - gpio[index] = pin->package_index; - index++; - RT_ASSERT(index <= 24) - } - } - } - for (index = 0; index < 24; index++) - { - pin = get_pin(gpio[index]); - if (index != RT_NULL) - { - if (EXTI_State(pin->port, pin->group_index)) - { - EXTI_Clear(pin->port, pin->group_index); - if (pin->callback) - { - pin->callback(pin->callback_args); - } - } - } - } - /* leave interrupt */ + rt_hw_pin_isr(GPIOP); rt_interrupt_leave(); } + +int rt_hw_pin_init(void) +{ + return rt_device_pin_register("pin", &swm_pin_ops, RT_NULL); +} +INIT_BOARD_EXPORT(rt_hw_pin_init); + +#endif /* BSP_USING_GPIO */ +#endif /* RT_USING_PIN */ diff --git a/bsp/swm320-lq100/drivers/drv_gpio.h b/bsp/swm320-lq100/drivers/drv_gpio.h index 4993272726..9e67c2127f 100644 --- a/bsp/swm320-lq100/drivers/drv_gpio.h +++ b/bsp/swm320-lq100/drivers/drv_gpio.h @@ -6,11 +6,30 @@ * Change Logs: * Date Author Notes * 2018-12-10 Zohar_Lee first version + * 2020-07-10 lik rewrite */ -#ifndef DRV_GPIO_H__ -#define DRV_GPIO_H__ +#ifndef __DRV_GPIO_H__ +#define __DRV_GPIO_H__ + +#include "board.h" + +#define __SWM_PIN(index, gpio, pin_index) \ + { \ + index, GPIO##gpio, PIN##pin_index, GPIO##gpio##_IRQn \ + } +#define GPIO0 ((GPIO_TypeDef *)(0)) +#define GPIO0_IRQn (GPIOA0_IRQn) + +struct swm_pin_index +{ + uint32_t index; + GPIO_TypeDef *gpio; + uint32_t pin; + IRQn_Type irq; +}; +typedef struct swm_pin_index pin_t; int rt_hw_pin_init(void); -#endif +#endif /* __DRV_GPIO_H__ */ diff --git a/bsp/swm320-lq100/drivers/drv_hwtimer.c b/bsp/swm320-lq100/drivers/drv_hwtimer.c index b5f76660d5..6881b7170e 100644 --- a/bsp/swm320-lq100/drivers/drv_hwtimer.c +++ b/bsp/swm320-lq100/drivers/drv_hwtimer.c @@ -6,257 +6,251 @@ * Change Logs: * Date Author Notes * 2018-12-10 Zohar_Lee first version + * 2020-07-10 lik format file */ -#include -#include -#include -#include +#include "drv_hwtimer.h" -#define SWM320_HWTIMER_DEVICE(hwtimer) (struct swm320_hwtimer_dev *)(hwtimer) +#ifdef RT_USING_HWTIMER +#ifdef BSP_USING_TIM -struct swm320_hwtimer_dev +enum { - rt_hwtimer_t parent; - TIMR_TypeDef *hwtimer_periph; +#ifdef BSP_USING_TIM0 + TIM0_INDEX, +#endif +#ifdef BSP_USING_TIM1 + TIM1_INDEX, +#endif +#ifdef BSP_USING_TIM2 + TIM2_INDEX, +#endif +#ifdef BSP_USING_TIM3 + TIM3_INDEX, +#endif +#ifdef BSP_USING_TIM4 + TIM4_INDEX, +#endif +#ifdef BSP_USING_TIM5 + TIM5_INDEX, +#endif }; -#ifdef BSP_USING_HWTIMER0 -static struct swm320_hwtimer_dev hwtimer0; - -void TIMR0_Handler(void) -{ - TIMR_INTClr(TIMR0); - rt_device_hwtimer_isr(&hwtimer0.parent); - - if (HWTIMER_MODE_ONESHOT == hwtimer0.parent.mode) +static struct swm_hwtimer_cfg hwtimer_cfg[] = { - TIMR_Stop(hwtimer0.hwtimer_periph); - } -} -#endif //BSP_USING_HWTIMER0 +#ifdef BSP_USING_TIM0 + TIM0_CFG, +#endif +#ifdef BSP_USING_TIM1 + TIM1_CFG, +#endif +#ifdef BSP_USING_TIM2 + TIM2_CFG, +#endif +#ifdef BSP_USING_TIM3 + TIM3_CFG, +#endif +#ifdef BSP_USING_TIM4 + TIM4_CFG, +#endif +#ifdef BSP_USING_TIM5 + TIM5_CFG, +#endif +}; -#ifdef BSP_USING_HWTIMER1 -static struct swm320_hwtimer_dev hwtimer1; +static struct swm_hwtimer hwtimer_drv[sizeof(hwtimer_cfg) / sizeof(hwtimer_cfg[0])] = {0}; -void TIMR1_Handler(void) +static void swm_timer_init(struct rt_hwtimer_device *timer_device, rt_uint32_t state) { - TIMR_INTClr(TIMR1); - rt_device_hwtimer_isr(&hwtimer1.parent); + struct swm_hwtimer_cfg *cfg = RT_NULL; + RT_ASSERT(timer_device != RT_NULL); - if (HWTIMER_MODE_ONESHOT == hwtimer1.parent.mode) + if (state) { - TIMR_Stop(hwtimer1.hwtimer_periph); - } + cfg = timer_device->parent.user_data; + TIMR_Init(cfg->TIMRx, TIMR_MODE_TIMER, SystemCoreClock, 1); + timer_device->freq = SystemCoreClock; + } } -#endif //BSP_USING_HWTIMER1 - -#ifdef BSP_USING_HWTIMER2 -static struct swm320_hwtimer_dev hwtimer2; -void TIMR2_Handler(void) +static rt_err_t swm_timer_start(rt_hwtimer_t *timer_device, rt_uint32_t cnt, rt_hwtimer_mode_t opmode) { - TIMR_INTClr(TIMR2); - rt_device_hwtimer_isr(&hwtimer2.parent); - - if (HWTIMER_MODE_ONESHOT == hwtimer2.parent.mode) - { - TIMR_Stop(hwtimer2.hwtimer_periph); - } -} -#endif //BSP_USING_HWTIMER2 - -#ifdef BSP_USING_HWTIMER3 -static struct swm320_hwtimer_dev hwtimer3; + rt_err_t result = RT_EOK; + struct swm_hwtimer_cfg *cfg = RT_NULL; + RT_ASSERT(timer_device != RT_NULL); + cfg = timer_device->parent.user_data; -void TIMR3_Handler(void) -{ - TIMR_INTClr(TIMR3); - rt_device_hwtimer_isr(&hwtimer3.parent); - - if (HWTIMER_MODE_ONESHOT == hwtimer3.parent.mode) + if (opmode == HWTIMER_MODE_ONESHOT) { - TIMR_Stop(hwtimer3.hwtimer_periph); + /* set timer to single mode */ + timer_device->mode = HWTIMER_MODE_ONESHOT; } -} -#endif //BSP_USING_HWTIMER3 - -#ifdef BSP_USING_HWTIMER4 -static struct swm320_hwtimer_dev hwtimer4; - -void TIMR4_Handler(void) -{ - TIMR_INTClr(TIMR4); - rt_device_hwtimer_isr(&hwtimer4.parent); - - if (HWTIMER_MODE_ONESHOT == hwtimer4.parent.mode) + else { - TIMR_Stop(hwtimer4.hwtimer_periph); + timer_device->mode = HWTIMER_MODE_PERIOD; } -} -#endif //BSP_USING_HWTIMER4 + TIMR_SetPeriod(cfg->TIMRx, cnt); + TIMR_Stop(cfg->TIMRx); + TIMR_Start(cfg->TIMRx); -#ifdef BSP_USING_HWTIMER5 -static struct swm320_hwtimer_dev hwtimer5; + return result; +} -void TIMR5_Handler(void) +static void swm_timer_stop(rt_hwtimer_t *timer_device) { - TIMR_INTClr(TIMR5); - rt_device_hwtimer_isr(&hwtimer5.parent); - - if (HWTIMER_MODE_ONESHOT == hwtimer5.parent.mode) - { - TIMR_Stop(hwtimer5.hwtimer_periph); - } + struct swm_hwtimer_cfg *cfg = RT_NULL; + RT_ASSERT(timer_device != RT_NULL); + cfg = timer_device->parent.user_data; + + /* stop timer */ + TIMR_Stop(cfg->TIMRx); } -#endif //BSP_USING_HWTIMER5 -static struct rt_hwtimer_info swm320_hwtimer_info = +static rt_uint32_t swm_timer_count_get(rt_hwtimer_t *timer_device) { - 120000000, /*时钟源为系统时钟*/ - 120000000, - 4294967295, /*32位计数器，2的32次方*/ - HWTIMER_CNTMODE_DW -}; + struct swm_hwtimer_cfg *cfg = RT_NULL; + RT_ASSERT(timer_device != RT_NULL); + cfg = timer_device->parent.user_data; -static void swm320_hwtimer_init(rt_hwtimer_t *timer, rt_uint32_t state) + return TIMR_GetCurValue(cfg->TIMRx); +} + +static rt_err_t swm_timer_ctrl(rt_hwtimer_t *timer_device, rt_uint32_t cmd, void *args) { - struct swm320_hwtimer_dev *hwtimer = SWM320_HWTIMER_DEVICE(timer->parent.user_data); + struct swm_hwtimer_cfg *cfg = RT_NULL; + rt_err_t result = RT_EOK; + RT_ASSERT(timer_device != RT_NULL); + RT_ASSERT(args != RT_NULL); + cfg = timer_device->parent.user_data; - RT_ASSERT(hwtimer != RT_NULL); + switch (cmd) + { + case HWTIMER_CTRL_FREQ_SET: + { + rt_uint32_t freq; + freq = *(rt_uint32_t *)args; - if (1 == state) + TIMR_Init(cfg->TIMRx, TIMR_MODE_TIMER, SystemCoreClock / freq, 1); + } + break; + default: { - TIMR_Init(hwtimer->hwtimer_periph, - TIMR_MODE_TIMER, - SystemCoreClock, - 1); + result = -RT_ENOSYS; } - hwtimer->parent.freq = SystemCoreClock; - swm320_hwtimer_info.maxfreq = SystemCoreClock; - swm320_hwtimer_info.minfreq = SystemCoreClock; + break; + } + + return result; } -static rt_err_t swm320_hwtimer_start(rt_hwtimer_t *timer, - rt_uint32_t cnt, - rt_hwtimer_mode_t mode) -{ - struct swm320_hwtimer_dev *hwtimer = SWM320_HWTIMER_DEVICE(timer->parent.user_data); +static const struct rt_hwtimer_info _info = TIM_DEV_INFO_CONFIG; - RT_ASSERT(hwtimer != RT_NULL); +static struct rt_hwtimer_ops swm_hwtimer_ops = + { + .init = swm_timer_init, + .start = swm_timer_start, + .stop = swm_timer_stop, + .count_get = swm_timer_count_get, + .control = swm_timer_ctrl}; - TIMR_SetPeriod(hwtimer->hwtimer_periph, cnt); - TIMR_Start(hwtimer->hwtimer_periph); +void rt_hw_hwtimer_isr(rt_hwtimer_t *timer_device) +{ + struct swm_hwtimer_cfg *cfg = RT_NULL; + RT_ASSERT(timer_device != RT_NULL); + cfg = timer_device->parent.user_data; - return RT_EOK; + TIMR_INTClr(cfg->TIMRx); + rt_device_hwtimer_isr(timer_device); } - -static void swm320_hwtimer_stop(rt_hwtimer_t *timer) +#ifdef BSP_USING_TIM0 +void TIMR0_Handler(void) { - struct swm320_hwtimer_dev *hwtimer = SWM320_HWTIMER_DEVICE(timer->parent.user_data); - - RT_ASSERT(hwtimer != RT_NULL); - - TIMR_Stop(hwtimer->hwtimer_periph); + /* enter interrupt */ + rt_interrupt_enter(); + rt_hw_hwtimer_isr(&(hwtimer_drv[TIM0_INDEX].time_device)); + /* leave interrupt */ + rt_interrupt_leave(); } +#endif //BSP_USING_TIM0 -static rt_uint32_t swm320_hwtimer_count_get(rt_hwtimer_t *timer) +#ifdef BSP_USING_TIM1 +void TIMR1_Handler(void) { - struct swm320_hwtimer_dev *hwtimer = SWM320_HWTIMER_DEVICE(timer->parent.user_data); - uint32_t hwtimer_count = 0; + /* enter interrupt */ + rt_interrupt_enter(); + rt_hw_hwtimer_isr(&(hwtimer_drv[TIM1_INDEX].time_device)); + /* leave interrupt */ + rt_interrupt_leave(); +} +#endif //BSP_USING_TIM1 - RT_ASSERT(hwtimer != RT_NULL); +#ifdef BSP_USING_TIM2 +void TIMR2_Handler(void) +{ + /* enter interrupt */ + rt_interrupt_enter(); + rt_hw_hwtimer_isr(&(hwtimer_drv[TIM2_INDEX].time_device)); + /* leave interrupt */ + rt_interrupt_leave(); +} +#endif //BSP_USING_TIM2 - hwtimer_count = TIMR_GetCurValue(hwtimer->hwtimer_periph); +#ifdef BSP_USING_TIM3 +void TIMR3_Handler(void) +{ + /* enter interrupt */ + rt_interrupt_enter(); + rt_hw_hwtimer_isr(&(hwtimer_drv[TIM3_INDEX].time_device)); + /* leave interrupt */ + rt_interrupt_leave(); +} +#endif //BSP_USING_TIM3 - return hwtimer_count; +#ifdef BSP_USING_TIM4 +void TIMR4_Handler(void) +{ + /* enter interrupt */ + rt_interrupt_enter(); + rt_hw_hwtimer_isr(&(hwtimer_drv[TIM4_INDEX].time_device)); + /* leave interrupt */ + rt_interrupt_leave(); } +#endif //BSP_USING_TIM4 -static rt_err_t swm320_hwtimer_control(rt_hwtimer_t *timer, - rt_uint32_t cmd, - void *args) +#ifdef BSP_USING_TIM5 +void TIMR5_Handler(void) { - rt_err_t ret = RT_EOK; - rt_uint32_t freq = 0; - struct swm320_hwtimer_dev *hwtimer = SWM320_HWTIMER_DEVICE(timer->parent.user_data); + /* enter interrupt */ + rt_interrupt_enter(); + rt_hw_hwtimer_isr(&(hwtimer_drv[TIM5_INDEX].time_device)); + /* leave interrupt */ + rt_interrupt_leave(); +} +#endif //BSP_USING_TIM5 - RT_ASSERT(hwtimer != RT_NULL); +static int rt_hw_hwtimer_init(void) +{ + int i = 0; + int result = RT_EOK; - switch (cmd) + for (i = 0; i < sizeof(hwtimer_cfg) / sizeof(hwtimer_cfg[0]); i++) { - case HWTIMER_CTRL_FREQ_SET: - freq = *(rt_uint32_t*)args; - if (freq != SystemCoreClock) + hwtimer_drv[i].cfg = &hwtimer_cfg[i]; + hwtimer_drv[i].time_device.info = &_info; + hwtimer_drv[i].time_device.ops = &swm_hwtimer_ops; + if (rt_device_hwtimer_register(&hwtimer_drv[i].time_device, hwtimer_drv[i].cfg->name, hwtimer_drv[i].cfg) == RT_EOK) { - ret = RT_EINVAL; + ; + } + else + { + result = -RT_ERROR; } - break; - case HWTIMER_CTRL_STOP: - TIMR_Stop(hwtimer->hwtimer_periph); - break; - default: - ret = RT_EINVAL; - break; } - return ret; -} - -static struct rt_hwtimer_ops swm320_hwtimer_ops = -{ - swm320_hwtimer_init, - swm320_hwtimer_start, - swm320_hwtimer_stop, - swm320_hwtimer_count_get, - swm320_hwtimer_control -}; - -int rt_hw_hwtimer_init(void) -{ - rt_err_t ret = RT_EOK; - -#ifdef BSP_USING_HWTIMER0 - hwtimer0.hwtimer_periph = TIMR0; - hwtimer0.parent.info = &swm320_hwtimer_info; - hwtimer0.parent.ops = &swm320_hwtimer_ops; - ret = rt_device_hwtimer_register(&hwtimer0.parent, "timer0", &hwtimer0); -#endif //BSP_USING_HWTIMER0 - -#ifdef BSP_USING_HWTIMER1 - hwtimer1.hwtimer_periph = TIMR1; - hwtimer1.parent.info = &swm320_hwtimer_info; - hwtimer1.parent.ops = &swm320_hwtimer_ops; - ret = rt_device_hwtimer_register(&hwtimer1.parent, "timer1", &hwtimer1); -#endif //BSP_USING_HWTIMER1 - -#ifdef BSP_USING_HWTIMER2 - hwtimer2.hwtimer_periph = TIMR2; - hwtimer2.parent.info = &swm320_hwtimer_info; - hwtimer2.parent.ops = &swm320_hwtimer_ops; - ret = rt_device_hwtimer_register(&hwtimer2.parent, "timer2", &hwtimer2); -#endif //BSP_USING_HWTIMER2 - -#ifdef BSP_USING_HWTIMER3 - hwtimer3.hwtimer_periph = TIMR3; - hwtimer3.parent.info = &swm320_hwtimer_info; - hwtimer3.parent.ops = &swm320_hwtimer_ops; - ret = rt_device_hwtimer_register(&hwtimer3.parent, "timer3", &hwtimer3); -#endif //BSP_USING_HWTIMER3 - -#ifdef BSP_USING_HWTIMER4 - hwtimer4.hwtimer_periph = TIMR4; - hwtimer4.parent.info = &swm320_hwtimer_info; - hwtimer4.parent.ops = &swm320_hwtimer_ops; - ret = rt_device_hwtimer_register(&hwtimer4.parent, "timer4", &hwtimer4); -#endif //BSP_USING_HWTIMER4 - -#ifdef BSP_USING_HWTIMER5 - hwtimer5.hwtimer_periph = TIMR5; - hwtimer5.parent.info = &swm320_hwtimer_info; - hwtimer5.parent.ops = &swm320_hwtimer_ops; - ret = rt_device_hwtimer_register(&hwtimer5.parent, "timer5", &hwtimer5); -#endif //BSP_USING_HWTIMER5 - - return ret; + return result; } INIT_BOARD_EXPORT(rt_hw_hwtimer_init); + +#endif /* BSP_USING_TIM */ +#endif /* RT_USING_HWTIMER */ diff --git a/bsp/swm320-lq100/drivers/drv_hwtimer.h b/bsp/swm320-lq100/drivers/drv_hwtimer.h index 6ec07dedde..05d586ac44 100644 --- a/bsp/swm320-lq100/drivers/drv_hwtimer.h +++ b/bsp/swm320-lq100/drivers/drv_hwtimer.h @@ -6,11 +6,96 @@ * Change Logs: * Date Author Notes * 2018-12-10 Zohar_Lee first version + * 2020-07-10 lik rewrite */ -#ifndef DRV_HWTIMER_H__ -#define DRV_HWTIMER_H__ +#ifndef __DRV_HWTIMER_H__ +#define __DRV_HWTIMER_H__ + +#include "board.h" + +struct swm_hwtimer_cfg +{ + char *name; + TIMR_TypeDef *TIMRx; +}; + +struct swm_hwtimer +{ + struct swm_hwtimer_cfg *cfg; + rt_hwtimer_t time_device; +}; + +#ifndef TIM_DEV_INFO_CONFIG +#define TIM_DEV_INFO_CONFIG \ + { \ + .maxfreq = 120000000, \ + .minfreq = 120000000, \ + .maxcnt = 0xFFFFFFFF, \ + .cntmode = HWTIMER_CNTMODE_DW, \ + } +#endif /* TIM_DEV_INFO_CONFIG */ + +#ifdef BSP_USING_TIM0 +#ifndef TIM0_CFG +#define TIM0_CFG \ + { \ + .name = "timer0", \ + .TIMRx = TIMR0, \ + } +#endif /* TIM0_CFG */ +#endif /* BSP_USING_TIM0 */ + +#ifdef BSP_USING_TIM1 +#ifndef TIM1_CFG +#define TIM1_CFG \ + { \ + .name = "timer1", \ + .TIMRx = TIMR1, \ + } +#endif /* TIM1_CFG */ +#endif /* BSP_USING_TIM1 */ + +#ifdef BSP_USING_TIM2 +#ifndef TIM2_CFG +#define TIM2_CFG \ + { \ + .name = "timer2", \ + .TIMRx = TIMR2, \ + } +#endif /* TIM2_CFG */ +#endif /* BSP_USING_TIM2 */ + +#ifdef BSP_USING_TIM3 +#ifndef TIM3_CFG +#define TIM3_CFG \ + { \ + .name = "timer3", \ + .TIMRx = TIMR3, \ + } +#endif /* TIM3_CFG */ +#endif /* BSP_USING_TIM3 */ + +#ifdef BSP_USING_TIM4 +#ifndef TIM4_CFG +#define TIM4_CFG \ + { \ + .name = "timer4", \ + .TIMRx = TIMR4, \ + } +#endif /* TIM4_CFG */ +#endif /* BSP_USING_TIM4 */ + +#ifdef BSP_USING_TIM5 +#ifndef TIM5_CFG +#define TIM5_CFG \ + { \ + .name = "timer5", \ + .TIMRx = TIMR5, \ + } +#endif /* TIM5_CFG */ +#endif /* BSP_USING_TIM5 */ int rt_hw_hwtimer_init(void); -#endif +#endif /* __DRV_HWTIMER_H__ */ diff --git a/bsp/swm320-lq100/drivers/drv_i2c.c b/bsp/swm320-lq100/drivers/drv_i2c.c deleted file mode 100644 index 322d735a68..0000000000 --- a/bsp/swm320-lq100/drivers/drv_i2c.c +++ /dev/null @@ -1,70 +0,0 @@ -/* - * Copyright (c) 2006-2018, Synwit Technology Co.,Ltd. - * - * SPDX-License-Identifier: Apache-2.0 - * - * Change Logs: - * Date Author Notes - * 2018-05-31 ZYH first version - * 2018-12-10 Zohar_Lee format file - */ - -#include -#include -#include -#include - -static void drv_set_sda(void *data, rt_int32_t state) -{ - rt_pin_mode(BSP_I2C_SDA, PIN_MODE_OUTPUT); - rt_pin_write(BSP_I2C_SDA, state); -} - -static void drv_set_scl(void *data, rt_int32_t state) -{ - rt_pin_mode(BSP_I2C_SCL, PIN_MODE_OUTPUT); - rt_pin_write(BSP_I2C_SCL, state); -} - -static rt_int32_t drv_get_sda(void *data) -{ - rt_pin_mode(BSP_I2C_SDA, PIN_MODE_INPUT_PULLUP); - return rt_pin_read(BSP_I2C_SDA); -} - -static rt_int32_t drv_get_scl(void *data) -{ - rt_pin_mode(BSP_I2C_SCL, PIN_MODE_INPUT_PULLUP); - return rt_pin_read(BSP_I2C_SCL); -} - -static void drv_udelay(rt_uint32_t us) -{ - int i = (SystemCoreClock / 4000000 * us); - while (i) - { - i--; - } -} - -static const struct rt_i2c_bit_ops drv_bit_ops = -{ - RT_NULL, - drv_set_sda, - drv_set_scl, - drv_get_sda, - drv_get_scl, - drv_udelay, - 1, - 100 -}; - -int rt_hw_i2c_init(void) -{ - static struct rt_i2c_bus_device i2c2_bus; - rt_memset((void *)&i2c2_bus, 0, sizeof(struct rt_i2c_bus_device)); - i2c2_bus.priv = (void *)&drv_bit_ops; - rt_i2c_bit_add_bus(&i2c2_bus, BSP_I2C_BUS_NAME); - return RT_EOK; -} -INIT_DEVICE_EXPORT(rt_hw_i2c_init); diff --git a/bsp/swm320-lq100/drivers/drv_i2c.h b/bsp/swm320-lq100/drivers/drv_i2c.h deleted file mode 100644 index 01cbcd7669..0000000000 --- a/bsp/swm320-lq100/drivers/drv_i2c.h +++ /dev/null @@ -1,16 +0,0 @@ -/* - * Copyright (c) 2006-2018, Synwit Technology Co.,Ltd. - * - * SPDX-License-Identifier: Apache-2.0 - * - * Change Logs: - * Date Author Notes - * 2018-12-10 Zohar_Lee first version - */ - -#ifndef DRV_I2C_H__ -#define DRV_I2C_H__ - -int rt_hw_i2c_init(void); - -#endif diff --git a/bsp/swm320-lq100/drivers/drv_iwg.c b/bsp/swm320-lq100/drivers/drv_iwg.c deleted file mode 100644 index 55af428641..0000000000 --- a/bsp/swm320-lq100/drivers/drv_iwg.c +++ /dev/null @@ -1,77 +0,0 @@ -/* - * Copyright (c) 2006-2018, Synwit Technology Co.,Ltd. - * - * SPDX-License-Identifier: Apache-2.0 - * - * Change Logs: - * Date Author Notes - * 2018-12-10 Zohar_Lee first version - */ - -#include -#include "rtthread.h" -#include "rtdevice.h" - -static rt_err_t swm320_wdt_init(rt_watchdog_t *wdt) -{ - WDT_Init(WDT, SystemCoreClock / 2, WDT_MODE_INTERRUPT); - - return RT_EOK; -} - -static rt_err_t swm320_wdt_control(rt_watchdog_t *wdt, int cmd, void *arg) -{ - switch (cmd) - { - case RT_DEVICE_CTRL_WDT_GET_TIMEOUT: - *(uint32_t *)arg = WDT->LOAD; - break; - case RT_DEVICE_CTRL_WDT_SET_TIMEOUT: - WDT_Stop(WDT); - WDT->LOAD = SystemCoreClock / 1000 * (*(uint32_t *)arg); - break; - case RT_DEVICE_CTRL_WDT_GET_TIMELEFT: - *(uint32_t *)arg = WDT_GetValue(WDT); - break; - case RT_DEVICE_CTRL_WDT_KEEPALIVE: - WDT_Feed(WDT); - break; - case RT_DEVICE_CTRL_WDT_START: - WDT_Start(WDT); - break; - case RT_DEVICE_CTRL_WDT_STOP: - WDT_Stop(WDT); - break; - default: - break; - } - - return RT_EOK; -} - -rt_watchdog_t swm320_wdt; -const static struct rt_watchdog_ops swm320_wdt_ops = -{ - swm320_wdt_init, - swm320_wdt_control -}; - -int rt_hw_wdt_init(void) -{ - rt_err_t result = RT_EOK; - - swm320_wdt.ops = &swm320_wdt_ops; - - result = rt_hw_watchdog_register(&swm320_wdt, - "wdt", - RT_DEVICE_FLAG_RDWR, - WDT); - - return result; -} -INIT_BOARD_EXPORT(rt_hw_wdt_init); - -void WDT_Handler(void) -{ - WDT_INTClr(WDT); -} diff --git a/bsp/swm320-lq100/drivers/drv_iwg.h b/bsp/swm320-lq100/drivers/drv_iwg.h deleted file mode 100644 index f4e85df8a7..0000000000 --- a/bsp/swm320-lq100/drivers/drv_iwg.h +++ /dev/null @@ -1,16 +0,0 @@ -/* - * Copyright (c) 2006-2018, Synwit Technology Co.,Ltd. - * - * SPDX-License-Identifier: Apache-2.0 - * - * Change Logs: - * Date Author Notes - * 2018-12-10 Zohar_Lee first version - */ - -#ifndef DRV_IWG_H__ -#define DRV_IWG_H__ - -int rt_hw_wdt_init(void); - -#endif diff --git a/bsp/swm320-lq100/drivers/drv_log.h b/bsp/swm320-lq100/drivers/drv_log.h new file mode 100644 index 0000000000..52e560cc12 --- /dev/null +++ b/bsp/swm320-lq100/drivers/drv_log.h @@ -0,0 +1,27 @@ +/* + * Copyright (c) 2006-2021, RT-Thread Development Team + * + * SPDX-License-Identifier: Apache-2.0 + * + * Change Logs: + * Date Author Notes + * 2018-11-15 SummerGift first version + */ + +/* + * NOTE: DO NOT include this file on the header file. + */ + +#ifndef LOG_TAG +#define DBG_TAG "drv" +#else +#define DBG_TAG LOG_TAG +#endif /* LOG_TAG */ + +#ifdef DRV_DEBUG +#define DBG_LVL DBG_LOG +#else +#define DBG_LVL DBG_INFO +#endif /* DRV_DEBUG */ + +#include diff --git a/bsp/swm320-lq100/drivers/drv_nor_flash.c b/bsp/swm320-lq100/drivers/drv_nor_flash.c index e229d3b7ce..6940cd54d0 100644 --- a/bsp/swm320-lq100/drivers/drv_nor_flash.c +++ b/bsp/swm320-lq100/drivers/drv_nor_flash.c @@ -7,67 +7,44 @@ * Date Author Notes * 2018-05-31 ZYH first version * 2018-12-10 Zohar_Lee format file + * 2020-07-10 lik rewrite */ -#include -#include -#include -#include -#include +#include "drv_nor_flash.h" -#define BLOCK_SIZE (64 * 1024) -#define FLASH_SIZE (BSP_NOR_FLASH_SIZE) -#define BLOCK_COUNTER (FLASH_SIZE / BLOCK_SIZE) +#ifdef BSP_USING_NOR_FLASH + +#define DRV_DEBUG +#define LOG_TAG "drv.norflash" +#include static struct rt_mutex flash_lock; /* RT-Thread MTD device interface */ -static long swm320_read_id(struct rt_mtd_nor_device *device) +static long swm_norflash_read_id(struct rt_mtd_nor_device *device) { return 0xdeadbeef; } -static rt_size_t swm320_read(struct rt_mtd_nor_device *device, - rt_off_t position, - rt_uint8_t *data, - rt_size_t size) +static rt_size_t swm_norflash_read(struct rt_mtd_nor_device *device, + rt_off_t position, + rt_uint8_t *data, + rt_uint32_t size) { - int ret = rt_mutex_take(&flash_lock, RT_WAITING_FOREVER); - if (ret == -RT_ETIMEOUT) - { - rt_kprintf("Take mutex time out.\n"); - return ret; - } - else if (ret == -RT_ERROR) - { - rt_kprintf("Take mutex error.\n"); - return ret; - } - + rt_mutex_take(&flash_lock, RT_WAITING_FOREVER); memcpy(data, ((const void *)(NORFLM_BASE + position)), size); rt_mutex_release(&flash_lock); return size; } -static rt_size_t swm320_write(struct rt_mtd_nor_device *device, - rt_off_t position, - const rt_uint8_t *data, - rt_size_t size) +static rt_size_t swm_norflash_write(struct rt_mtd_nor_device *device, + rt_off_t position, + const rt_uint8_t *data, + rt_uint32_t size) { rt_size_t i; const rt_uint16_t *hwdata = (const rt_uint16_t *)data; - int ret = rt_mutex_take(&flash_lock, RT_WAITING_FOREVER); - if (ret == -RT_ETIMEOUT) - { - rt_kprintf("Take mutex time out.\n"); - return ret; - } - else if (ret == -RT_ERROR) - { - rt_kprintf("Take mutex error.\n"); - return ret; - } - + rt_mutex_take(&flash_lock, RT_WAITING_FOREVER); for (i = 0; i < size / 2; i++) { NORFL_Write(position, hwdata[i]); @@ -77,45 +54,35 @@ static rt_size_t swm320_write(struct rt_mtd_nor_device *device, return size; } -static rt_err_t swm320_erase_block(struct rt_mtd_nor_device *device, - rt_off_t offset, - rt_uint32_t length) +static rt_err_t swm_norflash_erase_block(struct rt_mtd_nor_device *device, + rt_off_t offset, + rt_uint32_t length) { - rt_err_t ret = rt_mutex_take(&flash_lock, RT_WAITING_FOREVER); - if (ret == -RT_ETIMEOUT) - { - rt_kprintf("Take mutex time out.\n"); - return ret; - } - else if (ret == -RT_ERROR) - { - rt_kprintf("Take mutex error.\n"); - return ret; - } - + rt_mutex_take(&flash_lock, RT_WAITING_FOREVER); NORFL_SectorErase(offset); rt_mutex_release(&flash_lock); return RT_EOK; } const static struct rt_mtd_nor_driver_ops mtd_ops = -{ - swm320_read_id, - swm320_read, - swm320_write, - swm320_erase_block -}; + { + swm_norflash_read_id, + swm_norflash_read, + swm_norflash_write, + swm_norflash_erase_block}; -static rt_err_t hw_init() +static struct rt_mtd_nor_device mtd; +int rt_hw_norflash_init(void) { NORFL_InitStructure NORFL_InitStruct; + PORT->PORTP_SEL0 = 0xAAAAAAAA; //PP0-23 => ADDR0-23 PORT->PORTP_SEL1 = 0xAAAA; PORT->PORTM_SEL0 = 0xAAAAAAAA; //PM0-15 => DATA15-0 PORT->PORTM_INEN = 0xFFFF; - PORT->PORTM_SEL1 = 0x2AA; //PM16 => OEN, PM17 => WEN, PM18 => NORFL_CSN,PM19 => SDRAM_CSN, PM20 => SRAM_CSN, PM21 => SDRAM_CKE + PORT->PORTM_SEL1 = 0xAAA; //PM16 => OEN、PM17 => WEN、PM18 => NORFL_CSN、PM19 => SDRAM_CSN、PM20 => SRAM_CSN、PM21 => SDRAM_CKE NORFL_InitStruct.DataWidth = 16; NORFL_InitStruct.WELowPulseTime = 5; @@ -123,12 +90,7 @@ static rt_err_t hw_init() NORFL_InitStruct.OperFinishIEn = 0; NORFL_InitStruct.OperTimeoutIEn = 0; NORFL_Init(&NORFL_InitStruct); - return RT_EOK; -} -static struct rt_mtd_nor_device mtd; -int rt_hw_norflash_init(void) -{ - hw_init(); + /* set page size and block size */ mtd.block_size = BLOCK_SIZE; /* 64kByte */ mtd.ops = &mtd_ops; @@ -148,11 +110,4 @@ int rt_hw_norflash_init(void) } INIT_DEVICE_EXPORT(rt_hw_norflash_init); -#ifdef RT_USING_FINSH -#include -void nor_erase(void) -{ - NORFL_ChipErase(); -} -MSH_CMD_EXPORT(nor_erase, erase all block in SPI flash); -#endif +#endif /* BSP_USING_NOR_FLASH */ diff --git a/bsp/swm320-lq100/drivers/drv_nor_flash.h b/bsp/swm320-lq100/drivers/drv_nor_flash.h index 86260be87e..170917c44d 100644 --- a/bsp/swm320-lq100/drivers/drv_nor_flash.h +++ b/bsp/swm320-lq100/drivers/drv_nor_flash.h @@ -6,11 +6,18 @@ * Change Logs: * Date Author Notes * 2018-12-10 Zohar_Lee first version + * 2020-07-10 lik rewrite */ #ifndef DRV_NOR_FLASH_H__ #define DRV_NOR_FLASH_H__ +#include "board.h" + +#define BLOCK_SIZE (64 * 1024) +#define FLASH_SIZE (BSP_NOR_FLASH_SIZE) +#define BLOCK_COUNTER (FLASH_SIZE / BLOCK_SIZE) + int rt_hw_norflash_init(void); #endif diff --git a/bsp/swm320-lq100/drivers/drv_pwm.c b/bsp/swm320-lq100/drivers/drv_pwm.c index 3d6f9203ef..23b2aeca0f 100644 --- a/bsp/swm320-lq100/drivers/drv_pwm.c +++ b/bsp/swm320-lq100/drivers/drv_pwm.c @@ -6,185 +6,228 @@ * Change Logs: * Date Author Notes * 2018-12-10 Zohar_Lee first version + * 2020-07-10 lik format file */ -#include -#include -#include -#include +#include "drv_pwm.h" -#define SWM320_PWM_DEVICE(pwm) (struct swm320_pwm_dev *)(pwm) +#ifdef RT_USING_PWM +#ifdef BSP_USING_PWM -#define SWM320_PWM_TIMER_SET(time) ((time) / 1000.0 * 120) +//#define DRV_DEBUG +#define LOG_TAG "drv.pwm" +#include -struct swm320_pwm_dev -{ - struct rt_device_pwm parent; - PWM_TypeDef *pwm_periph; +#define MIN_PERIOD 2 +#define MIN_PULSE 1 + +static struct swm_pwm_cfg pwm_cfg[] = + { +#ifdef BSP_USING_PWM0 + PWM0_CFG, +#endif +#ifdef BSP_USING_PWM1 + PWM1_CFG, +#endif +#ifdef BSP_USING_PWM2 + PWM2_CFG, +#endif +#ifdef BSP_USING_PWM3 + PWM3_CFG, +#endif +#ifdef BSP_USING_PWM4 + PWM4_CFG, +#endif +#ifdef BSP_USING_PWM5 + PWM5_CFG, +#endif }; -static rt_err_t swm320_pwm_enable(void *user_data, - struct rt_pwm_configuration *cfg, - rt_bool_t enable) +static struct swm_pwm pwm_drv[sizeof(pwm_cfg) / sizeof(pwm_cfg[0])] = {0}; + +static rt_err_t swm_pwm_control(struct rt_device_pwm *pwm_device, int cmd, void *arg); +static struct rt_pwm_ops pwm_ops = + { + swm_pwm_control}; + +static rt_err_t swm_pwm_enable(struct rt_device_pwm *pwm_device, struct rt_pwm_configuration *configuration, rt_bool_t enable) { - rt_err_t ret = RT_EOK; + struct swm_pwm_cfg *cfg = RT_NULL; + RT_ASSERT(pwm_device != RT_NULL); + cfg = pwm_device->parent.user_data; - if (RT_TRUE == enable) + if (!enable) { - if (2 == cfg->channel) - { - PWM_Start((PWM_TypeDef *)user_data, 1, 1); - } - if (1 == cfg->channel) - { - PWM_Start((PWM_TypeDef *)user_data, 0, 1); - } - if (0 == cfg->channel) + if (PWM_CH_A == configuration->channel) { - PWM_Start((PWM_TypeDef *)user_data, 1, 0); + PWM_Stop(cfg->PWMx, 1, 0); } - if (3 == cfg->channel) + if (PWM_CH_B == configuration->channel) { - PWM_Start((PWM_TypeDef *)user_data, 0, 0); + PWM_Stop(cfg->PWMx, 0, 1); } } - else if (RT_FALSE == enable) + else { - if (2 == cfg->channel) - { - PWM_Stop((PWM_TypeDef *)user_data, 1, 1); - } - if (1 == cfg->channel) - { - PWM_Stop((PWM_TypeDef *)user_data, 0, 1); - } - if (0 == cfg->channel) + if (PWM_CH_A == configuration->channel) { - PWM_Stop((PWM_TypeDef *)user_data, 1, 0); + PWM_Start(cfg->PWMx, 1, 0); } - if (3 == cfg->channel) + if (PWM_CH_B == configuration->channel) { - PWM_Stop((PWM_TypeDef *)user_data, 0, 0); + PWM_Start(cfg->PWMx, 0, 1); } } - else + + return RT_EOK; +} + +static rt_err_t swm_pwm_get(struct rt_device_pwm *pwm_device, struct rt_pwm_configuration *configuration) +{ + rt_uint64_t tim_clock; + tim_clock = SystemCoreClock / 8; + + struct swm_pwm_cfg *cfg = RT_NULL; + RT_ASSERT(pwm_device != RT_NULL); + cfg = pwm_device->parent.user_data; + + /* Convert nanosecond to frequency and duty cycle. 1s = 1 * 1000 * 1000 * 1000 ns */ + tim_clock /= 1000000UL; + configuration->period = PWM_GetCycle(cfg->PWMx, configuration->channel) * 1000UL / tim_clock; + configuration->pulse = PWM_GetHDuty(cfg->PWMx, configuration->channel) * 1000UL / tim_clock; + + return RT_EOK; +} + +static rt_err_t swm_pwm_set(struct rt_device_pwm *pwm_device, struct rt_pwm_configuration *configuration) +{ + rt_uint32_t period, pulse; + rt_uint64_t tim_clock; + tim_clock = SystemCoreClock / 8; + + struct swm_pwm_cfg *cfg = RT_NULL; + RT_ASSERT(pwm_device != RT_NULL); + cfg = pwm_device->parent.user_data; + + /* Convert nanosecond to frequency and duty cycle. 1s = 1 * 1000 * 1000 * 1000 ns */ + /* when SystemCoreClock = 120MHz, configuration->period max 4.369ms */ + /* when SystemCoreClock = 20MHz, configuration->period max 26.214ms */ + tim_clock /= 1000000UL; + period = (unsigned long long)configuration->period * tim_clock / 1000ULL; + pulse = (unsigned long long)configuration->pulse * tim_clock / 1000ULL; + if (period < MIN_PERIOD) + { + period = MIN_PERIOD; + } + if (pulse < MIN_PULSE) { - ret = RT_ERROR; + pulse = MIN_PULSE; } + PWM_SetCycle(cfg->PWMx, configuration->channel, period); + PWM_SetHDuty(cfg->PWMx, configuration->channel, pulse); - return ret; + return RT_EOK; } -static rt_err_t swm320_pwm_control(struct rt_device_pwm *device, - int cmd, - void *arg) +static rt_err_t swm_pwm_control(struct rt_device_pwm *pwm_device, int cmd, void *arg) { - rt_err_t ret = RT_EOK; - struct swm320_pwm_dev *pwm = SWM320_PWM_DEVICE(device->parent.user_data); - struct rt_pwm_configuration *cfg = (struct rt_pwm_configuration *)arg; + RT_ASSERT(pwm_device != RT_NULL); - RT_ASSERT(pwm != RT_NULL); + struct rt_pwm_configuration *configuration = (struct rt_pwm_configuration *)arg; switch (cmd) { case PWM_CMD_ENABLE: - - ret = swm320_pwm_enable((void *)pwm->pwm_periph, cfg, RT_TRUE); - break; + return swm_pwm_enable(pwm_device, configuration, RT_TRUE); case PWM_CMD_DISABLE: - - ret = swm320_pwm_enable((void *)pwm->pwm_periph, cfg, RT_FALSE); - break; + return swm_pwm_enable(pwm_device, configuration, RT_FALSE); case PWM_CMD_SET: - PWM_SetHDuty(pwm->pwm_periph, - cfg->channel, - SWM320_PWM_TIMER_SET(cfg->pulse)); - PWM_SetCycle(pwm->pwm_periph, - cfg->channel, - SWM320_PWM_TIMER_SET(cfg->period)); - break; + return swm_pwm_set(pwm_device, configuration); case PWM_CMD_GET: - cfg->pulse = PWM_GetHDuty(pwm->pwm_periph, cfg->channel); - break; + return swm_pwm_get(pwm_device, configuration); default: - break; + return RT_EINVAL; } - - return ret; } -const static struct rt_pwm_ops swm320_pwm_ops = -{ - swm320_pwm_control -}; - int rt_hw_pwm_init(void) { - rt_err_t ret = RT_EOK; - PWM_InitStructure PWM_initStruct; - - PWM_initStruct.clk_div = PWM_CLKDIV_1; /* F_PWM = 120M/1 = 120M */ - PWM_initStruct.mode = PWM_MODE_INDEP; /* A路和B路独立输出 */ - PWM_initStruct.cycleA = SWM320_PWM_TIMER_SET(1000); - PWM_initStruct.hdutyA = SWM320_PWM_TIMER_SET(500); - PWM_initStruct.initLevelA = 1; - PWM_initStruct.cycleB = SWM320_PWM_TIMER_SET(1000); - PWM_initStruct.hdutyB = SWM320_PWM_TIMER_SET(250); - PWM_initStruct.initLevelB = 1; - PWM_initStruct.HEndAIEn = 0; - PWM_initStruct.NCycleAIEn = 0; - PWM_initStruct.HEndBIEn = 0; - PWM_initStruct.NCycleBIEn = 0; + int i = 0; + int result = RT_EOK; -#ifdef BSP_USING_PWM0 - static struct swm320_pwm_dev pwm_dev0; - pwm_dev0.pwm_periph = PWM0; - PWM_Init(pwm_dev0.pwm_periph, &PWM_initStruct); - PORT_Init(PORTA, PIN4, FUNMUX0_PWM0A_OUT, 0); - PORT_Init(PORTA, PIN10, FUNMUX0_PWM0B_OUT, 0); - ret = rt_device_pwm_register(&pwm_dev0.parent, - "pwm0", - &swm320_pwm_ops, - &pwm_dev0); + for (i = 0; i < sizeof(pwm_cfg) / sizeof(pwm_cfg[0]); i++) + { + pwm_drv[i].cfg = &pwm_cfg[i]; + if (pwm_drv[i].cfg->PWMx == PWM0) + { +#ifdef BSP_USING_PWM0A + PORT_Init(PORTC, PIN2, FUNMUX0_PWM0A_OUT, 0); #endif - -#ifdef BSP_USING_PWM1 - static struct swm320_pwm_dev pwm_dev1; - pwm_dev1.pwm_periph = PWM1; - PWM_Init(pwm_dev1.pwm_periph, &PWM_initStruct); - PORT_Init(PORTA, PIN5, FUNMUX1_PWM1A_OUT, 0); - PORT_Init(PORTA, PIN9, FUNMUX1_PWM1B_OUT, 0); - ret = rt_device_pwm_register(&pwm_dev1.parent, - "pwm1", - &swm320_pwm_ops, - &pwm_dev1); +#ifdef BSP_USING_PWM0B + PORT_Init(PORTC, PIN4, FUNMUX0_PWM0B_OUT, 0); #endif - -#ifdef BSP_USING_PWM2 - static struct swm320_pwm_dev pwm_dev2; - pwm_dev2.pwm_periph = PWM2; - PWM_Init(pwm_dev2.pwm_periph, &PWM_initStruct); - PORT_Init(PORTP, PIN0, FUNMUX0_PWM2A_OUT, 0); - PORT_Init(PORTP, PIN2, FUNMUX0_PWM2B_OUT, 0); - ret = rt_device_pwm_register(&pwm_dev2.parent, - "pwm2", - &swm320_pwm_ops, - &pwm_dev2); + } + else if (pwm_drv[i].cfg->PWMx == PWM1) + { +#ifdef BSP_USING_PWM1A + PORT_Init(PORTC, PIN3, FUNMUX1_PWM1A_OUT, 0); +#endif +#ifdef BSP_USING_PWM1B + PORT_Init(PORTC, PIN5, FUNMUX1_PWM1B_OUT, 0); #endif + } + else if (pwm_drv[i].cfg->PWMx == PWM2) + { +#ifdef BSP_USING_PWM2A + PORT_Init(PORTN, PIN4, FUNMUX0_PWM2A_OUT, 0); +#endif +#ifdef BSP_USING_PWM2B + PORT_Init(PORTN, PIN6, FUNMUX0_PWM2B_OUT, 0); +#endif + } + else if (pwm_drv[i].cfg->PWMx == PWM3) + { +#ifdef BSP_USING_PWM3A + PORT_Init(PORTN, PIN3, FUNMUX1_PWM3A_OUT, 0); +#endif +#ifdef BSP_USING_PWM3B + PORT_Init(PORTN, PIN5, FUNMUX1_PWM3B_OUT, 0); +#endif + } + else if (pwm_drv[i].cfg->PWMx == PWM4) + { +#ifdef BSP_USING_PWM4A + PORT_Init(PORTN, PIN8, FUNMUX0_PWM4A_OUT, 0); +#endif +#ifdef BSP_USING_PWM4B + PORT_Init(PORTN, PIN10, FUNMUX0_PWM4B_OUT, 0); +#endif + } + else if (pwm_drv[i].cfg->PWMx == PWM5) + { +#ifdef BSP_USING_PWM5A + PORT_Init(PORTN, PIN7, FUNMUX1_PWM5A_OUT, 0); +#endif +#ifdef BSP_USING_PWM5B + PORT_Init(PORTN, PIN9, FUNMUX1_PWM5B_OUT, 0); +#endif + } -#ifdef BSP_USING_PWM3 - static struct swm320_pwm_dev pwm_dev3; - pwm_dev3.pwm_periph = PWM3; - PWM_Init(pwm_dev3.pwm_periph, &PWM_initStruct); - PORT_Init(PORTP, PIN1, FUNMUX1_PWM3A_OUT, 0); - PORT_Init(PORTP, PIN3, FUNMUX1_PWM3B_OUT, 0); - ret = rt_device_pwm_register(&pwm_dev3.parent, - "pwm3", - &swm320_pwm_ops, - &pwm_dev3); -#endif - - return ret; + PWM_Init(pwm_drv[i].cfg->PWMx, &(pwm_drv[i].cfg->pwm_initstruct)); + if (rt_device_pwm_register(&pwm_drv[i].pwm_device, pwm_drv[i].cfg->name, &pwm_ops, pwm_drv[i].cfg) == RT_EOK) + { + LOG_D("%s register success", pwm_drv[i].cfg->name); + } + else + { + LOG_E("%s register failed", pwm_drv[i].cfg->name); + result = -RT_ERROR; + } + } + return result; } INIT_DEVICE_EXPORT(rt_hw_pwm_init); + +#endif /* BSP_USING_PWM */ +#endif /* RT_USING_PWM */ diff --git a/bsp/swm320-lq100/drivers/drv_pwm.h b/bsp/swm320-lq100/drivers/drv_pwm.h index 94bbf0c750..0e27cb2e7b 100644 --- a/bsp/swm320-lq100/drivers/drv_pwm.h +++ b/bsp/swm320-lq100/drivers/drv_pwm.h @@ -6,11 +6,159 @@ * Change Logs: * Date Author Notes * 2018-12-10 Zohar_Lee first version + * 2020-07-10 lik rewrite */ -#ifndef DRV_PWM_H__ -#define DRV_PWM_H__ +#ifndef __DRV_PWM_H__ +#define __DRV_PWM_H__ + +#include "board.h" + +struct swm_pwm_cfg +{ + const char *name; + PWM_TypeDef *PWMx; + PWM_InitStructure pwm_initstruct; +}; + +struct swm_pwm +{ + struct swm_pwm_cfg *cfg; + struct rt_device_pwm pwm_device; +}; + +#ifdef BSP_USING_PWM0 +#ifndef PWM0_CFG +#define PWM0_CFG \ + { \ + .name = "pwm0", \ + .PWMx = PWM0, \ + .pwm_initstruct.clk_div = PWM_CLKDIV_8, \ + .pwm_initstruct.mode = PWM_MODE_INDEP, \ + .pwm_initstruct.cycleA = 10000, \ + .pwm_initstruct.hdutyA = 5000, \ + .pwm_initstruct.initLevelA = 1, \ + .pwm_initstruct.cycleB = 10000, \ + .pwm_initstruct.hdutyB = 5000, \ + .pwm_initstruct.initLevelB = 1, \ + .pwm_initstruct.HEndAIEn = 0, \ + .pwm_initstruct.NCycleAIEn = 0, \ + .pwm_initstruct.HEndBIEn = 0, \ + .pwm_initstruct.NCycleBIEn = 0, \ + } +#endif /* PWM0_CFG */ +#endif /* BSP_USING_PWM0 */ + +#ifdef BSP_USING_PWM1 +#ifndef PWM1_CFG +#define PWM1_CFG \ + { \ + .name = "pwm1", \ + .PWMx = PWM1, \ + .pwm_initstruct.clk_div = PWM_CLKDIV_8, \ + .pwm_initstruct.mode = PWM_MODE_INDEP, \ + .pwm_initstruct.cycleA = 10000, \ + .pwm_initstruct.hdutyA = 5000, \ + .pwm_initstruct.initLevelA = 1, \ + .pwm_initstruct.cycleB = 10000, \ + .pwm_initstruct.hdutyB = 5000, \ + .pwm_initstruct.initLevelB = 1, \ + .pwm_initstruct.HEndAIEn = 0, \ + .pwm_initstruct.NCycleAIEn = 0, \ + .pwm_initstruct.HEndBIEn = 0, \ + .pwm_initstruct.NCycleBIEn = 0, \ + } +#endif /* PWM1_CFG */ +#endif /* BSP_USING_PWM1 */ + +#ifdef BSP_USING_PWM2 +#ifndef PWM2_CFG +#define PWM2_CFG \ + { \ + .name = "pwm2", \ + .PWMx = PWM2, \ + .pwm_initstruct.clk_div = PWM_CLKDIV_8, \ + .pwm_initstruct.mode = PWM_MODE_INDEP, \ + .pwm_initstruct.cycleA = 10000, \ + .pwm_initstruct.hdutyA = 5000, \ + .pwm_initstruct.initLevelA = 1, \ + .pwm_initstruct.cycleB = 10000, \ + .pwm_initstruct.hdutyB = 5000, \ + .pwm_initstruct.initLevelB = 1, \ + .pwm_initstruct.HEndAIEn = 0, \ + .pwm_initstruct.NCycleAIEn = 0, \ + .pwm_initstruct.HEndBIEn = 0, \ + .pwm_initstruct.NCycleBIEn = 0, \ + } +#endif /* PWM2_CFG */ +#endif /* BSP_USING_PWM2 */ + +#ifdef BSP_USING_PWM3 +#ifndef PWM3_CFG +#define PWM3_CFG \ + { \ + .name = "pwm3", \ + .PWMx = PWM3, \ + .pwm_initstruct.clk_div = PWM_CLKDIV_8, \ + .pwm_initstruct.mode = PWM_MODE_INDEP, \ + .pwm_initstruct.cycleA = 10000, \ + .pwm_initstruct.hdutyA = 5000, \ + .pwm_initstruct.initLevelA = 1, \ + .pwm_initstruct.cycleB = 10000, \ + .pwm_initstruct.hdutyB = 5000, \ + .pwm_initstruct.initLevelB = 1, \ + .pwm_initstruct.HEndAIEn = 0, \ + .pwm_initstruct.NCycleAIEn = 0, \ + .pwm_initstruct.HEndBIEn = 0, \ + .pwm_initstruct.NCycleBIEn = 0, \ + } +#endif /* PWM3_CFG */ +#endif /* BSP_USING_PWM3 */ + +#ifdef BSP_USING_PWM4 +#ifndef PWM4_CFG +#define PWM4_CFG \ + { \ + .name = "pwm4", \ + .PWMx = PWM4, \ + .pwm_initstruct.clk_div = PWM_CLKDIV_8, \ + .pwm_initstruct.mode = PWM_MODE_INDEP, \ + .pwm_initstruct.cycleA = 10000, \ + .pwm_initstruct.hdutyA = 5000, \ + .pwm_initstruct.initLevelA = 1, \ + .pwm_initstruct.cycleB = 10000, \ + .pwm_initstruct.hdutyB = 5000, \ + .pwm_initstruct.initLevelB = 1, \ + .pwm_initstruct.HEndAIEn = 0, \ + .pwm_initstruct.NCycleAIEn = 0, \ + .pwm_initstruct.HEndBIEn = 0, \ + .pwm_initstruct.NCycleBIEn = 0, \ + } +#endif /* PWM4_CFG */ +#endif /* BSP_USING_PWM4 */ + +#ifdef BSP_USING_PWM5 +#ifndef PWM5_CFG +#define PWM5_CFG \ + { \ + .name = "pwm5", \ + .PWMx = PWM5, \ + .pwm_initstruct.clk_div = PWM_CLKDIV_8, \ + .pwm_initstruct.mode = PWM_MODE_INDEP, \ + .pwm_initstruct.cycleA = 10000, \ + .pwm_initstruct.hdutyA = 5000, \ + .pwm_initstruct.initLevelA = 1, \ + .pwm_initstruct.cycleB = 10000, \ + .pwm_initstruct.hdutyB = 5000, \ + .pwm_initstruct.initLevelB = 1, \ + .pwm_initstruct.HEndAIEn = 0, \ + .pwm_initstruct.NCycleAIEn = 0, \ + .pwm_initstruct.HEndBIEn = 0, \ + .pwm_initstruct.NCycleBIEn = 0, \ + } +#endif /* PWM5_CFG */ +#endif /* BSP_USING_PWM5 */ int rt_hw_pwm_init(void); -#endif +#endif /* __DRV_PWM_H__ */ diff --git a/bsp/swm320-lq100/drivers/drv_rtc.c b/bsp/swm320-lq100/drivers/drv_rtc.c index 5219a5b013..74d41a2752 100644 --- a/bsp/swm320-lq100/drivers/drv_rtc.c +++ b/bsp/swm320-lq100/drivers/drv_rtc.c @@ -6,26 +6,19 @@ * Change Logs: * Date Author Notes * 2018-12-10 Zohar_Lee first version + * 2020-07-10 lik format file */ -#include -#include -#include -#include -#include +#include "drv_rtc.h" #include -/** - * This function will get the weed day from a date. - * - * @param year the year of time - * @param month the month of time - * @param date the date of time - * - * @return the week day 0 ~ 6 : sun ~ sat - * - * @note No - */ +#ifdef RT_USING_RTC +#ifdef BSP_USING_RTC + +//#define DRV_DEBUG +#define LOG_TAG "drv.rtc" +#include + static uint32_t calcWeekDay(uint32_t year, uint32_t month, uint32_t date) { uint32_t i, cnt = 0; @@ -36,8 +29,7 @@ static uint32_t calcWeekDay(uint32_t year, uint32_t month, uint32_t date) cnt += date; - if ((year % 4 == 0) && ((year % 100 != 0) || (year % 400 == 0)) && - (month >= 3)) + if ((year % 4 == 0) && ((year % 100 != 0) || (year % 400 == 0)) && (month >= 3)) cnt += 1; cnt += (year - 1901) * 365; @@ -51,127 +43,123 @@ static uint32_t calcWeekDay(uint32_t year, uint32_t month, uint32_t date) return (cnt + 1) % 7; } -static void RTC_SetDateTime(RTC_TypeDef *RTCx, RTC_DateTime *dateTime) +static time_t swm_get_rtc_time_stamp(void) { - RTC_Stop(RTCx); + RTC_DateTime get_datetime = {0}; + struct tm tm_new; - while (RTCx->CFGABLE == 0); + RTC_GetDateTime(RTC, &get_datetime); - RTCx->MINSEC = (dateTime->Second << RTC_MINSEC_SEC_Pos) | - (dateTime->Minute << RTC_MINSEC_MIN_Pos); + tm_new.tm_sec = get_datetime.Second; + tm_new.tm_min = get_datetime.Minute; + tm_new.tm_hour = get_datetime.Hour; + tm_new.tm_mday = get_datetime.Date; + tm_new.tm_mon = get_datetime.Month; + tm_new.tm_year = get_datetime.Year; - RTCx->DATHUR = (dateTime->Hour << RTC_DATHUR_HOUR_Pos) | - ((dateTime->Date - 1) << RTC_DATHUR_DATE_Pos); + LOG_D("get rtc time."); + return mktime(&tm_new); +} +static rt_err_t swm_set_rtc_time_stamp(time_t time_stamp) +{ + RTC_DateTime set_datetime = {0}; + struct tm *p_tm; + + p_tm = gmtime(&time_stamp); + + set_datetime.Second = p_tm->tm_sec; + set_datetime.Minute = p_tm->tm_min; + set_datetime.Hour = p_tm->tm_hour; + set_datetime.Date = p_tm->tm_mday; + set_datetime.Month = p_tm->tm_mon; + set_datetime.Year = p_tm->tm_year; + // set_datetime.Day = p_tm->tm_wday; + + RTC_Stop(RTC); + while (RTC->CFGABLE == 0) + ; + RTC->MINSEC = (set_datetime.Second << RTC_MINSEC_SEC_Pos) | + (set_datetime.Minute << RTC_MINSEC_MIN_Pos); + RTC->DATHUR = (set_datetime.Hour << RTC_DATHUR_HOUR_Pos) | + ((set_datetime.Date) << RTC_DATHUR_DATE_Pos); + RTC->MONDAY = (calcWeekDay(set_datetime.Year, set_datetime.Month, set_datetime.Date) + << RTC_MONDAY_DAY_Pos) | + ((set_datetime.Month) << RTC_MONDAY_MON_Pos); + RTC->YEAR = set_datetime.Year; + RTC->LOAD = 1 << RTC_LOAD_TIME_Pos; + RTC_Start(RTC); - RTCx->MONDAY = (calcWeekDay(dateTime->Year, dateTime->Month, dateTime->Date) - << RTC_MONDAY_DAY_Pos) | - ((dateTime->Month - 1) << RTC_MONDAY_MON_Pos); + LOG_D("set rtc time."); + return RT_EOK; +} - RTCx->YEAR = dateTime->Year - 1901; +static rt_err_t swm_rtc_init(void) +{ + RTC_InitStructure rtc_initstruct; + + rtc_initstruct.Year = 2020; + rtc_initstruct.Month = 6; + rtc_initstruct.Date = 8; + rtc_initstruct.Hour = 12; + rtc_initstruct.Minute = 0; + rtc_initstruct.Second = 0; + rtc_initstruct.SecondIEn = 0; + rtc_initstruct.MinuteIEn = 0; + RTC_Init(RTC, &rtc_initstruct); + RTC_Start(RTC); - RTCx->LOAD = 1 << RTC_LOAD_TIME_Pos; + return RT_EOK; +} - RTC_Start(RTC); +static rt_err_t swm_rtc_get_secs(void *args) +{ + *(rt_uint32_t *)args = swm_get_rtc_time_stamp(); + LOG_D("RTC: get rtc_time %x\n", *(rt_uint32_t *)args); + + return RT_EOK; } -static rt_err_t swm320_rtc_control(rt_device_t dev, int cmd, void *args) +static rt_err_t swm_rtc_set_secs(void *args) { rt_err_t result = RT_EOK; - struct tm time_temp; - struct tm *pNow; - RTC_DateTime dateTime; - - switch (cmd) + if (swm_set_rtc_time_stamp(*(rt_uint32_t *)args)) { - case RT_DEVICE_CTRL_RTC_GET_TIME: - RTC_GetDateTime(RTC, &dateTime); - time_temp.tm_sec = dateTime.Second; - time_temp.tm_min = dateTime.Minute; - time_temp.tm_hour = dateTime.Hour; - time_temp.tm_mday = dateTime.Date; - time_temp.tm_mon = dateTime.Month - 1; - time_temp.tm_year = dateTime.Year - 1900; - *((time_t *)args) = timegm(&time_temp); - break; - case RT_DEVICE_CTRL_RTC_SET_TIME: - rt_enter_critical(); - /* converts calendar time time into local time. */ - pNow = gmtime((const time_t *)args); - /* copy the statically located variable */ - memcpy(&time_temp, pNow, sizeof(struct tm)); - /* unlock scheduler. */ - rt_exit_critical(); - - dateTime.Hour = time_temp.tm_hour; - dateTime.Minute = time_temp.tm_min; - dateTime.Second = time_temp.tm_sec; - dateTime.Year = time_temp.tm_year + 1900; - dateTime.Month = time_temp.tm_mon + 1; - dateTime.Date = time_temp.tm_mday; - RTC_SetDateTime(RTC, &dateTime); - break; - case RT_DEVICE_CTRL_RTC_GET_ALARM: - - break; - case RT_DEVICE_CTRL_RTC_SET_ALARM: - - break; - default: - break; + result = -RT_ERROR; } + LOG_D("RTC: set rtc_time %x\n", *(rt_uint32_t *)args); return result; } -#ifdef RT_USING_DEVICE_OPS -const static struct rt_device_ops swm320_rtc_ops = +static const struct rt_rtc_ops swm_rtc_ops = { + swm_rtc_init, + swm_rtc_get_secs, + swm_rtc_set_secs, RT_NULL, RT_NULL, RT_NULL, RT_NULL, - RT_NULL, - swm320_rtc_control }; -#endif + +static rt_rtc_dev_t swm_rtc_device; int rt_hw_rtc_init(void) { - rt_err_t ret = RT_EOK; - static struct rt_device rtc_dev; - RTC_InitStructure RTC_initStruct; - - RTC_initStruct.Year = 2018; - RTC_initStruct.Month = 1; - RTC_initStruct.Date = 1; - RTC_initStruct.Hour = 12; - RTC_initStruct.Minute = 0; - RTC_initStruct.Second = 0; - RTC_initStruct.SecondIEn = 0; - RTC_initStruct.MinuteIEn = 0; - RTC_Init(RTC, &RTC_initStruct); - RTC_Start(RTC); - - rtc_dev.type = RT_Device_Class_RTC; - rtc_dev.rx_indicate = RT_NULL; - rtc_dev.tx_complete = RT_NULL; + rt_err_t result; -#ifdef RT_USING_DEVICE_OPS - rtc_dev.ops = &swm320_rtc_ops; -#else - rtc_dev.init = RT_NULL; - rtc_dev.open = RT_NULL; - rtc_dev.close = RT_NULL; - rtc_dev.read = RT_NULL; - rtc_dev.write = RT_NULL; - rtc_dev.control = swm320_rtc_control; -#endif - - rtc_dev.user_data = RTC; - - ret = rt_device_register(&rtc_dev, "rtc", RT_DEVICE_FLAG_RDWR); - - return ret; + swm_rtc_device.ops = &swm_rtc_ops; + result = rt_hw_rtc_register(&swm_rtc_device, "rtc", RT_DEVICE_FLAG_RDWR,RT_NULL); + if (result != RT_EOK) + { + LOG_E("rtc register err code: %d", result); + return result; + } + LOG_D("rtc init success"); + return RT_EOK; } INIT_DEVICE_EXPORT(rt_hw_rtc_init); + +#endif /* BSP_USING_RTC */ +#endif /* RT_USING_RTC */ diff --git a/bsp/swm320-lq100/drivers/drv_rtc.h b/bsp/swm320-lq100/drivers/drv_rtc.h index f72d3d3d94..7a649c98af 100644 --- a/bsp/swm320-lq100/drivers/drv_rtc.h +++ b/bsp/swm320-lq100/drivers/drv_rtc.h @@ -6,11 +6,14 @@ * Change Logs: * Date Author Notes * 2018-12-10 Zohar_Lee first version + * 2020-07-10 lik rewrite */ -#ifndef DRV_RTC_H__ -#define DRV_RTC_H__ +#ifndef __DRV_RTC_H__ +#define __DRV_RTC_H__ + +#include "board.h" int rt_hw_rtc_init(void); -#endif +#endif /* __DRV_RTC_H__ */ diff --git a/bsp/swm320-lq100/drivers/drv_sdio.c b/bsp/swm320-lq100/drivers/drv_sdio.c new file mode 100644 index 0000000000..1fbbf3bce4 --- /dev/null +++ b/bsp/swm320-lq100/drivers/drv_sdio.c @@ -0,0 +1,664 @@ +/* + * Copyright (c) 2006-2018, Synwit Technology Co.,Ltd. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Change Logs: + * Date Author Notes + * 2020-07-10 lik first version + */ + +#include "drv_sdio.h" + +#ifdef RT_USING_SDIO +#ifdef BSP_USING_SDIO + +//#define DRV_DEBUG +#define LOG_TAG "drv.sdio" +#include + +static struct rt_mmcsd_host *host; + +#define RTHW_SDIO_LOCK(_sdio) rt_mutex_take(&_sdio->mutex, RT_WAITING_FOREVER) +#define RTHW_SDIO_UNLOCK(_sdio) rt_mutex_release(&_sdio->mutex); + +struct rthw_sdio +{ + struct rt_mmcsd_host *host; + struct swm_sdio_des sdio_des; + struct rt_event event; + struct rt_mutex mutex; + struct sdio_pkg *pkg; +}; + +ALIGN(SDIO_ALIGN_LEN) +static rt_uint8_t cache_buf[SDIO_BUFF_SIZE]; + +/** + * @brief This function wait sdio completed. + * @param sdio rthw_sdio + * @retval None + */ +static void rthw_sdio_wait_completed(struct rthw_sdio *sdio) +{ + rt_uint32_t status; + struct rt_mmcsd_cmd *cmd = sdio->pkg->cmd; + struct rt_mmcsd_data *data = cmd->data; + SDIO_TypeDef *hw_sdio = sdio->sdio_des.hw_sdio; + + if (rt_event_recv(&sdio->event, 0xffffffff, RT_EVENT_FLAG_OR | RT_EVENT_FLAG_CLEAR, + rt_tick_from_millisecond(1000), &status) != RT_EOK) + { + LOG_E("wait completed timeout"); + cmd->err = -RT_ETIMEOUT; + return; + } + + if (sdio->pkg == RT_NULL) + { + return; + } + + if (resp_type(cmd) == RESP_NONE) + { + ; + } + else if (resp_type(cmd) == RESP_R2) + { + cmd->resp[0] = (hw_sdio->RESP[3] << 8) + ((hw_sdio->RESP[2] >> 24) & 0xFF); + cmd->resp[1] = (hw_sdio->RESP[2] << 8) + ((hw_sdio->RESP[1] >> 24) & 0xFF); + cmd->resp[2] = (hw_sdio->RESP[1] << 8) + ((hw_sdio->RESP[0] >> 24) & 0xFF); + cmd->resp[3] = (hw_sdio->RESP[0] << 8) + 0x00; + } + else + { + cmd->resp[0] = hw_sdio->RESP[0]; + } + + if (status & SDIO_IF_ERROR_Msk) + { + if ((status & SDIO_IF_CMDCRCERR_Msk) && (resp_type(cmd) & (RESP_R3 | RESP_R4))) + { + cmd->err = RT_EOK; + } + else + { + cmd->err = -RT_ERROR; + } + + if (status & SDIO_IF_CMDTIMEOUT_Msk) + { + cmd->err = -RT_ETIMEOUT; + } + + if (status & SDIO_IF_DATCRCERR_Msk) + { + data->err = -RT_ERROR; + } + + if (status & SDIO_IF_DATTIMEOUT_Msk) + { + data->err = -RT_ETIMEOUT; + } + + if (cmd->err == RT_EOK) + { + LOG_D("sta:0x%08X [%08X %08X %08X %08X]", status, cmd->resp[0], cmd->resp[1], cmd->resp[2], cmd->resp[3]); + } + else + { + LOG_D("err:0x%08x, %s cmd:%d arg:0x%08x rw:%c len:%d blksize:%d", + status, + status == 0 ? "NULL" : "", + cmd->cmd_code, + cmd->arg, + data ? (data->flags & DATA_DIR_WRITE ? 'w' : 'r') : '-', + data ? data->blks * data->blksize : 0, + data ? data->blksize : 0); + } + } + else + { + cmd->err = RT_EOK; + LOG_D("sta:0x%08X [%08X %08X %08X %08X]", status, cmd->resp[0], cmd->resp[1], cmd->resp[2], cmd->resp[3]); + } +} + +/** + * @brief This function transfer data by dma. + * @param sdio rthw_sdio + * @param pkg sdio package + * @retval None + */ +static void rthw_sdio_transfer(struct rthw_sdio *sdio, struct sdio_pkg *pkg) +{ + struct rt_mmcsd_data *data; + int size; + void *buff; + + if ((RT_NULL == pkg) || (RT_NULL == sdio)) + { + LOG_E("rthw_sdio_transfer invalid args"); + return; + } + + data = pkg->cmd->data; + if (RT_NULL == data) + { + LOG_E("rthw_sdio_transfer invalid args"); + return; + } + + buff = pkg->buff; + if (RT_NULL == buff) + { + LOG_E("rthw_sdio_transfer invalid args"); + return; + } + + size = data->blks * data->blksize; + + if (data->flags & DATA_DIR_WRITE) + { + sdio->sdio_des.txconfig(pkg, (rt_uint32_t *)buff, size); + } + else if (data->flags & DATA_DIR_READ) + { + sdio->sdio_des.rxconfig(pkg, (rt_uint32_t *)buff, size); + } +} + +/** + * @brief This function send command. + * @param sdio rthw_sdio + * @param pkg sdio package + * @retval None + */ +static void rthw_sdio_send_command(struct rthw_sdio *sdio, struct sdio_pkg *pkg) +{ + struct rt_mmcsd_cmd *cmd = pkg->cmd; + struct rt_mmcsd_data *data = cmd->data; + SDIO_TypeDef *hw_sdio = sdio->sdio_des.hw_sdio; + rt_uint32_t reg_cmd; + + /* save pkg */ + sdio->pkg = pkg; + + LOG_D("CMD:%d ARG:0x%08x RES:%s%s%s%s%s%s%s%s%s rw:%c len:%d blksize:%d", + cmd->cmd_code, + cmd->arg, + resp_type(cmd) == RESP_NONE ? "NONE" : "", + resp_type(cmd) == RESP_R1 ? "R1" : "", + resp_type(cmd) == RESP_R1B ? "R1B" : "", + resp_type(cmd) == RESP_R2 ? "R2" : "", + resp_type(cmd) == RESP_R3 ? "R3" : "", + resp_type(cmd) == RESP_R4 ? "R4" : "", + resp_type(cmd) == RESP_R5 ? "R5" : "", + resp_type(cmd) == RESP_R6 ? "R6" : "", + resp_type(cmd) == RESP_R7 ? "R7" : "", + data ? (data->flags & DATA_DIR_WRITE ? 'w' : 'r') : '-', + data ? data->blks * data->blksize : 0, + data ? data->blksize : 0); + + /* config cmd reg */ + reg_cmd = (cmd->cmd_code << SDIO_CMD_CMDINDX_Pos) | + (0 << SDIO_CMD_CMDTYPE_Pos) | + (0 << SDIO_CMD_IDXCHECK_Pos) | + (0 << SDIO_CMD_CRCCHECK_Pos) | + (0 << SDIO_CMD_DMAEN_Pos); + if (resp_type(cmd) == RESP_NONE) + reg_cmd |= SD_RESP_NO << SDIO_CMD_RESPTYPE_Pos; + else if (resp_type(cmd) == RESP_R2) + reg_cmd |= SD_RESP_128b << SDIO_CMD_RESPTYPE_Pos; + else + reg_cmd |= SD_RESP_32b << SDIO_CMD_RESPTYPE_Pos; + + /* config data reg */ + if (data != RT_NULL) + { + rt_uint32_t dir = 0; + dir = (data->flags & DATA_DIR_READ) ? 1 : 0; + + hw_sdio->BLK = (data->blks << SDIO_BLK_COUNT_Pos) | (data->blksize << SDIO_BLK_SIZE_Pos); + + reg_cmd |= (1 << SDIO_CMD_HAVEDATA_Pos) | + (dir << SDIO_CMD_DIRREAD_Pos) | + ((data->blks > 1) << SDIO_CMD_MULTBLK_Pos) | + ((data->blks > 1) << SDIO_CMD_BLKCNTEN_Pos) | + (0 << SDIO_CMD_AUTOCMD12_Pos); + } + else + { + reg_cmd |= (0 << SDIO_CMD_HAVEDATA_Pos); + } + + if (cmd->cmd_code != SD_IO_SEND_OP_COND) + { + /* send cmd */ + hw_sdio->ARG = cmd->arg; + hw_sdio->CMD = reg_cmd; + } + + /* transfer config */ + if (data != RT_NULL) + { + rthw_sdio_transfer(sdio, pkg); + } + + /* wait completed */ + rthw_sdio_wait_completed(sdio); + + /* clear pkg */ + sdio->pkg = RT_NULL; +} + +/** + * @brief This function send sdio request. + * @param sdio rthw_sdio + * @param req request + * @retval None + */ +static void rthw_sdio_request(struct rt_mmcsd_host *host, struct rt_mmcsd_req *req) +{ + struct sdio_pkg pkg; + struct rthw_sdio *sdio = host->private_data; + struct rt_mmcsd_data *data; + + RTHW_SDIO_LOCK(sdio); + + if (req->cmd != RT_NULL) + { + rt_memset(&pkg, 0, sizeof(pkg)); + data = req->cmd->data; + pkg.cmd = req->cmd; + + if (data != RT_NULL) + { + rt_uint32_t size = data->blks * data->blksize; + + RT_ASSERT(size <= SDIO_BUFF_SIZE); + + pkg.buff = data->buf; + if ((rt_uint32_t)data->buf & (SDIO_ALIGN_LEN - 1)) + { + pkg.buff = cache_buf; + if (data->flags & DATA_DIR_WRITE) + { + rt_memcpy(cache_buf, data->buf, size); + } + } + } + + rthw_sdio_send_command(sdio, &pkg); + + if ((data != RT_NULL) && (data->flags & DATA_DIR_READ) && ((rt_uint32_t)data->buf & (SDIO_ALIGN_LEN - 1))) + { + rt_memcpy(data->buf, cache_buf, data->blksize * data->blks); + } + } + + if (req->stop != RT_NULL) + { + rt_memset(&pkg, 0, sizeof(pkg)); + pkg.cmd = req->stop; + rthw_sdio_send_command(sdio, &pkg); + } + + RTHW_SDIO_UNLOCK(sdio); + + mmcsd_req_complete(sdio->host); +} + +/** + * @brief This function config sdio. + * @param host rt_mmcsd_host + * @param io_cfg rt_mmcsd_io_cfg + * @retval None + */ +static void rthw_sdio_iocfg(struct rt_mmcsd_host *host, struct rt_mmcsd_io_cfg *io_cfg) +{ + rt_uint32_t clkcr, div, clk_src; + rt_uint32_t clk = io_cfg->clock; + struct rthw_sdio *sdio = host->private_data; + SDIO_TypeDef *hw_sdio = sdio->sdio_des.hw_sdio; + + clk_src = sdio->sdio_des.clk_get(sdio->sdio_des.hw_sdio); + if (clk_src < 400 * 1000) + { + LOG_E("The clock rate is too low! rata:%d", clk_src); + return; + } + + if (clk > host->freq_max) + clk = host->freq_max; + + if (clk > clk_src) + { + LOG_W("Setting rate is greater than clock source rate."); + clk = clk_src; + } + + LOG_D("clk:%d width:%s%s%s power:%s%s%s", + clk, + io_cfg->bus_width == MMCSD_BUS_WIDTH_8 ? "8" : "", + io_cfg->bus_width == MMCSD_BUS_WIDTH_4 ? "4" : "", + io_cfg->bus_width == MMCSD_BUS_WIDTH_1 ? "1" : "", + io_cfg->power_mode == MMCSD_POWER_OFF ? "OFF" : "", + io_cfg->power_mode == MMCSD_POWER_UP ? "UP" : "", + io_cfg->power_mode == MMCSD_POWER_ON ? "ON" : ""); + + RTHW_SDIO_LOCK(sdio); + + hw_sdio->CR1 = (1 << SDIO_CR1_CDSRC_Pos) | (7 << SDIO_CR1_VOLT_Pos); + if (io_cfg->bus_width == MMCSD_BUS_WIDTH_8) + { + hw_sdio->CR1 |= (1 << SDIO_CR1_8BIT_Pos); + } + else + { + hw_sdio->CR1 &= ~SDIO_CR1_8BIT_Msk; + if (io_cfg->bus_width == MMCSD_BUS_WIDTH_4) + { + hw_sdio->CR1 |= (1 << SDIO_CR1_4BIT_Pos); + } + else + { + hw_sdio->CR1 &= ~SDIO_CR1_4BIT_Msk; + } + } + switch (io_cfg->power_mode) + { + case MMCSD_POWER_OFF: + hw_sdio->CR1 &= ~SDIO_CR1_PWRON_Msk; + break; + case MMCSD_POWER_UP: + case MMCSD_POWER_ON: + hw_sdio->CR1 |= (1 << SDIO_CR1_PWRON_Pos); + break; + default: + LOG_W("unknown power_mode %d", io_cfg->power_mode); + break; + } + + div = clk_src / clk; + if ((clk == 0) || (div == 0)) + { + clkcr = 0; + } + else + { + if (div > 128) + clkcr = 0x80; + else if (div > 64) + clkcr = 0x40; + else if (div > 32) + clkcr = 0x20; + else if (div > 16) + clkcr = 0x10; + else if (div > 8) + clkcr = 0x08; + else if (div > 4) + clkcr = 0x04; + else if (div > 2) + clkcr = 0x02; + else if (div > 1) + clkcr = 0x01; + else + clkcr = 0x00; + } + + SDIO->CR2 = (1 << SDIO_CR2_CLKEN_Pos) | + (1 << SDIO_CR2_SDCLKEN_Pos) | + (clkcr << SDIO_CR2_SDCLKDIV_Pos) | + (0xC << SDIO_CR2_TIMEOUT_Pos); // 2**25 SDIO_CLK + + while ((SDIO->CR2 & SDIO_CR2_CLKRDY_Msk) == 0) + ; + + RTHW_SDIO_UNLOCK(sdio); +} + +/** + * @brief This function delect sdcard. + * @param host rt_mmcsd_host + * @retval 0x01 + */ +static rt_int32_t rthw_sdio_delect(struct rt_mmcsd_host *host) +{ + LOG_D("try to detect device"); + return 0x01; +} + +/** + * @brief This function update sdio interrupt. + * @param host rt_mmcsd_host + * @param enable + * @retval None + */ +void rthw_sdio_irq_update(struct rt_mmcsd_host *host, rt_int32_t enable) +{ + struct rthw_sdio *sdio = host->private_data; + SDIO_TypeDef *hw_sdio = sdio->sdio_des.hw_sdio; + + if (enable) + { + LOG_D("enable sdio irq"); + hw_sdio->IFE = 0xFFFFFFFF; + hw_sdio->IE = 0xFFFF000F; + } + else + { + LOG_D("disable sdio irq"); + hw_sdio->IFE &= ~0xFFFFFFFF; + hw_sdio->IE &= ~0xFFFFFFFF; + } +} + +static const struct rt_mmcsd_host_ops swm_sdio_ops = + { + rthw_sdio_request, + rthw_sdio_iocfg, + rthw_sdio_delect, + rthw_sdio_irq_update, +}; + +struct rt_mmcsd_host *sdio_host_create(struct swm_sdio_des *sdio_des) +{ + struct rt_mmcsd_host *host; + struct rthw_sdio *sdio = RT_NULL; + + if ((sdio_des == RT_NULL) || (sdio_des->txconfig == RT_NULL) || (sdio_des->rxconfig == RT_NULL)) + { + LOG_E("L:%d F:%s %s %s %s", + (sdio_des == RT_NULL ? "sdio_des is NULL" : ""), + (sdio_des ? (sdio_des->txconfig ? "txconfig is NULL" : "") : ""), + (sdio_des ? (sdio_des->rxconfig ? "rxconfig is NULL" : "") : "")); + return RT_NULL; + } + + sdio = rt_malloc(sizeof(struct rthw_sdio)); + if (sdio == RT_NULL) + { + LOG_E("L:%d F:%s malloc rthw_sdio fail"); + return RT_NULL; + } + rt_memset(sdio, 0, sizeof(struct rthw_sdio)); + + host = mmcsd_alloc_host(); + if (host == RT_NULL) + { + LOG_E("L:%d F:%s mmcsd alloc host fail"); + rt_free(sdio); + return RT_NULL; + } + + rt_memcpy(&sdio->sdio_des, sdio_des, sizeof(struct swm_sdio_des)); + + rt_event_init(&sdio->event, "sdio", RT_IPC_FLAG_FIFO); + rt_mutex_init(&sdio->mutex, "sdio", RT_IPC_FLAG_FIFO); + + /* set host defautl attributes */ + host->ops = &swm_sdio_ops; + host->freq_min = 400 * 1000; + host->freq_max = SDIO_MAX_FREQ; + host->valid_ocr = 0X00FFFF80; /* The voltage range supported is 1.65v-3.6v */ +#ifndef SDIO_USING_1_BIT + host->flags = MMCSD_BUSWIDTH_4 | MMCSD_MUTBLKWRITE | MMCSD_SUP_SDIO_IRQ; +#else + host->flags = MMCSD_MUTBLKWRITE | MMCSD_SUP_SDIO_IRQ; +#endif + host->max_seg_size = SDIO_BUFF_SIZE; + host->max_dma_segs = 1; + host->max_blk_size = 512; + host->max_blk_count = 512; + + /* link up host and sdio */ + sdio->host = host; + host->private_data = sdio; + + rthw_sdio_irq_update(host, 1); + + /* ready to change */ + mmcsd_change(host); + + return host; +} + +static rt_uint32_t swm_sdio_clock_get(SDIO_TypeDef *hw_sdio) +{ + uint32_t prediv = ((SYS->CLKDIV & SYS_CLKDIV_SDIO_Msk) >> SYS_CLKDIV_SDIO_Pos); + return (SystemCoreClock / (1 << prediv)); +} + +static rt_err_t swm_sdio_rxconfig(struct sdio_pkg *pkg, rt_uint32_t *buff, int size) +{ + struct rt_mmcsd_cmd *cmd = pkg->cmd; + struct rt_mmcsd_data *data = cmd->data; + for (uint32_t i = 0; i < data->blks; i++) + { + while ((SDIO->IF & SDIO_IF_BUFRDRDY_Msk) == 0) + __NOP(); + SDIO->IF = SDIO_IF_BUFRDRDY_Msk; + for (uint32_t j = 0; j < data->blksize / 4; j++) + buff[j] = SDIO->DATA; + } + return RT_EOK; +} + +static rt_err_t swm_sdio_txconfig(struct sdio_pkg *pkg, rt_uint32_t *buff, int size) +{ + struct rt_mmcsd_cmd *cmd = pkg->cmd; + struct rt_mmcsd_data *data = cmd->data; + for (uint32_t i = 0; i < data->blks; i++) + { + while ((SDIO->IF & SDIO_IF_BUFWRRDY_Msk) == 0) + __NOP(); + SDIO->IF = SDIO_IF_BUFWRRDY_Msk; + for (uint32_t j = 0; j < data->blksize / 4; j++) + SDIO->DATA = buff[j]; + } + return RT_EOK; +} + +/** + * @brief This function interrupt process function. + * @param host rt_mmcsd_host + * @retval None + */ +void rthw_sdio_irq_process(struct rt_mmcsd_host *host) +{ + int complete = 0; + struct rthw_sdio *sdio = host->private_data; + SDIO_TypeDef *hw_sdio = sdio->sdio_des.hw_sdio; + rt_uint32_t intstatus = hw_sdio->IF; + + if (intstatus & SDIO_IF_ERROR_Msk) + { + hw_sdio->IF = 0xFFFFFFFF; + complete = 1; + } + else + { + if (intstatus & SDIO_IF_CMDDONE_Msk) + { + hw_sdio->IF = SDIO_IF_CMDDONE_Msk; + if (sdio->pkg != RT_NULL) + { + if (!sdio->pkg->cmd->data) + { + complete = 1; + } + } + } + + if (intstatus & SDIO_IF_TRXDONE_Msk) + { + hw_sdio->IF = SDIO_IF_TRXDONE_Msk; + complete = 1; + } + } + + if (complete) + { + rt_event_send(&sdio->event, intstatus); + } +} + +void SDIO_Handler(void) +{ + /* enter interrupt */ + rt_interrupt_enter(); + /* Process All SDIO Interrupt Sources */ + rthw_sdio_irq_process(host); + /* leave interrupt */ + rt_interrupt_leave(); +} + +int rt_hw_sdio_init(void) +{ + struct swm_sdio_des sdio_des; + +#if 0 + PORT_Init(PORTB, PIN1, PORTB_PIN1_SD_CLK, 0); + PORT_Init(PORTB, PIN2, PORTB_PIN2_SD_CMD, 1); + PORT_Init(PORTB, PIN3, PORTB_PIN3_SD_D0, 1); + PORT_Init(PORTB, PIN4, PORTB_PIN4_SD_D1, 1); + PORT_Init(PORTB, PIN5, PORTB_PIN5_SD_D2, 1); + PORT_Init(PORTB, PIN6, PORTB_PIN6_SD_D3, 1); +#else + PORT_Init(PORTP, PIN11, PORTP_PIN11_SD_CLK, 0); + PORT_Init(PORTP, PIN10, PORTP_PIN10_SD_CMD, 1); + PORT_Init(PORTP, PIN9, PORTP_PIN9_SD_D0, 1); + PORT_Init(PORTP, PIN8, PORTP_PIN8_SD_D1, 1); + PORT_Init(PORTP, PIN7, PORTP_PIN7_SD_D2, 1); + PORT_Init(PORTP, PIN6, PORTP_PIN6_SD_D3, 1); +#endif + NVIC_EnableIRQ(SDIO_IRQn); + SYS->CLKDIV &= ~SYS_CLKDIV_SDIO_Msk; + if (SystemCoreClock > 80000000) //SDIO时钟需要小于52MHz + SYS->CLKDIV |= (2 << SYS_CLKDIV_SDIO_Pos); //SDCLK = SYSCLK / 4 + else + SYS->CLKDIV |= (1 << SYS_CLKDIV_SDIO_Pos); //SDCLK = SYSCLK / 2 + + SYS->CLKEN |= (0x01 << SYS_CLKEN_SDIO_Pos); + + SDIO->CR2 = (1 << SDIO_CR2_RSTALL_Pos); + + NVIC_EnableIRQ(SDIO_IRQn); + sdio_des.clk_get = swm_sdio_clock_get; + sdio_des.hw_sdio = SDIO; + sdio_des.rxconfig = swm_sdio_rxconfig; + sdio_des.txconfig = swm_sdio_txconfig; + + host = sdio_host_create(&sdio_des); + if (host == RT_NULL) + { + LOG_E("host create fail"); + return -1; + } + return 0; +} +INIT_DEVICE_EXPORT(rt_hw_sdio_init); + +#endif /* BSP_USING_SDIO */ +#endif /* RT_USING_SDIO */ diff --git a/bsp/swm320-lq100/drivers/drv_sdio.h b/bsp/swm320-lq100/drivers/drv_sdio.h new file mode 100644 index 0000000000..16f2420344 --- /dev/null +++ b/bsp/swm320-lq100/drivers/drv_sdio.h @@ -0,0 +1,42 @@ +/* + * Copyright (c) 2006-2018, Synwit Technology Co.,Ltd. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Change Logs: + * Date Author Notes + * 2020-07-10 lik first version + */ + +#ifndef __DRV_SDIO_H__ +#define __DRV_SDIO_H__ + +#include "board.h" + +#define SDIO_BUFF_SIZE 4096 +#define SDIO_ALIGN_LEN 4 + +#ifndef SDIO_MAX_FREQ +#define SDIO_MAX_FREQ (30000000) +#endif + +struct sdio_pkg +{ + struct rt_mmcsd_cmd *cmd; + void *buff; + rt_uint32_t flag; +}; + +typedef rt_err_t (*sdio_txconfig)(struct sdio_pkg *pkg, rt_uint32_t *buff, int size); +typedef rt_err_t (*sdio_rxconfig)(struct sdio_pkg *pkg, rt_uint32_t *buff, int size); +typedef rt_uint32_t (*sdio_clk_get)(SDIO_TypeDef *hw_sdio); + +struct swm_sdio_des +{ + SDIO_TypeDef *hw_sdio; + sdio_txconfig txconfig; + sdio_rxconfig rxconfig; + sdio_clk_get clk_get; +}; + +#endif /* __DRV_SDIO_H__ */ diff --git a/bsp/swm320-lq100/drivers/drv_soft_i2c.c b/bsp/swm320-lq100/drivers/drv_soft_i2c.c new file mode 100644 index 0000000000..d63b7ca35c --- /dev/null +++ b/bsp/swm320-lq100/drivers/drv_soft_i2c.c @@ -0,0 +1,197 @@ +/* + * Copyright (c) 2006-2018, Synwit Technology Co.,Ltd. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Change Logs: + * Date Author Notes + * 2018-05-31 ZYH first version + * 2018-12-10 Zohar_Lee format file + * 2020-07-10 lik rewrite + */ + +#include "drv_soft_i2c.h" + +#ifdef RT_USING_I2C +#ifdef BSP_USING_I2C + +/*************************************************************** +*!!!!!!!!!!!!!!!!!!!!!!!!!!!!NOTICE!!!!!!!!!!!!!!!!!!!!!!!!!!!!! +*In order to use swm drv_soft_i2c,you need to commented out +line 114 (SDA_H(ops);) and line 167 (SDA_H(ops);) in i2c-bit-ops.c +At the same time, add one line (SDA_L(ops);)after line 154 (SCL_L(ops);) +in i2c-bit-ops.c +***************************************************************/ + +//#define DRV_DEBUG +#define LOG_TAG "drv.i2c" +#include + +#if !defined(BSP_USING_I2C0) && !defined(BSP_USING_I2C1) +#error "Please define at least one BSP_USING_I2Cx" +/* this driver can be disabled at menuconfig ? RT-Thread Components ? Device Drivers */ +#endif + +static const struct swm_soft_i2c_cfg soft_i2c_cfg[] = + { +#ifdef BSP_USING_I2C0 + I2C0_BUS_CFG, +#endif +#ifdef BSP_USING_I2C1 + I2C1_BUS_CFG, +#endif +}; + +static struct swm_i2c i2c_drv[sizeof(soft_i2c_cfg) / sizeof(soft_i2c_cfg[0])]; + +/** + * This function initializes the i2c pin. + * + * @param swm i2c dirver class. + */ +static void swm_i2c_gpio_init(struct swm_i2c *i2c) +{ + struct swm_soft_i2c_cfg *cfg = (struct swm_soft_i2c_cfg *)i2c->ops.data; + + rt_pin_mode(cfg->scl, PIN_MODE_OUTPUT_OD); + rt_pin_mode(cfg->sda, PIN_MODE_OUTPUT_OD); + + rt_pin_write(cfg->scl, PIN_HIGH); + rt_pin_write(cfg->sda, PIN_HIGH); +} + +/** + * This function sets the sda pin. + * + * @param swm config class. + * @param The sda pin state. + */ +static void swm_set_sda(void *data, rt_int32_t state) +{ + struct swm_soft_i2c_cfg *cfg = (struct swm_soft_i2c_cfg *)data; + rt_pin_mode(cfg->sda, PIN_MODE_OUTPUT_OD); + if (state) + { + rt_pin_write(cfg->sda, PIN_HIGH); + } + else + { + rt_pin_write(cfg->sda, PIN_LOW); + } +} + +/** + * This function sets the scl pin. + * + * @param swm config class. + * @param The scl pin state. + */ +static void swm_set_scl(void *data, rt_int32_t state) +{ + struct swm_soft_i2c_cfg *cfg = (struct swm_soft_i2c_cfg *)data; + rt_pin_mode(cfg->scl, PIN_MODE_OUTPUT_OD); + if (state) + { + rt_pin_write(cfg->scl, PIN_HIGH); + } + else + { + rt_pin_write(cfg->scl, PIN_LOW); + } +} + +/** + * This function gets the sda pin state. + * + * @param The sda pin state. + */ +static rt_int32_t swm_get_sda(void *data) +{ + struct swm_soft_i2c_cfg *cfg = (struct swm_soft_i2c_cfg *)data; + rt_pin_mode(cfg->sda, PIN_MODE_INPUT_PULLUP); + return rt_pin_read(cfg->sda); +} + +/** + * This function gets the scl pin state. + * + * @param The scl pin state. + */ +static rt_int32_t swm_get_scl(void *data) +{ + struct swm_soft_i2c_cfg *cfg = (struct swm_soft_i2c_cfg *)data; + rt_pin_mode(cfg->scl, PIN_MODE_INPUT_PULLUP); + return rt_pin_read(cfg->scl); +} + +/** + * The time delay function. + * + * @param microseconds. + */ +static void swm_udelay(rt_uint32_t us) +{ + rt_uint32_t ticks; + rt_uint32_t told, tnow, tcnt = 0; + rt_uint32_t reload = SysTick->LOAD; + + ticks = us * reload / (1000000 / RT_TICK_PER_SECOND); + told = SysTick->VAL; + while (1) + { + tnow = SysTick->VAL; + if (tnow != told) + { + if (tnow < told) + { + tcnt += told - tnow; + } + else + { + tcnt += reload - tnow + told; + } + told = tnow; + if (tcnt >= ticks) + { + break; + } + } + } +} + +static const struct rt_i2c_bit_ops swm_bit_ops = + { + .data = RT_NULL, + .set_sda = swm_set_sda, + .set_scl = swm_set_scl, + .get_sda = swm_get_sda, + .get_scl = swm_get_scl, + .udelay = swm_udelay, + .delay_us = 1, + .timeout = 100}; + +/* I2C initialization function */ +int rt_hw_i2c_init(void) +{ + rt_err_t result; + + for (int i = 0; i < sizeof(i2c_drv) / sizeof(struct swm_i2c); i++) + { + i2c_drv[i].ops = swm_bit_ops; + i2c_drv[i].ops.data = (void *)&soft_i2c_cfg[i]; + i2c_drv[i].i2c2_bus.priv = &i2c_drv[i].ops; + swm_i2c_gpio_init(&i2c_drv[i]); + result = rt_i2c_bit_add_bus(&i2c_drv[i].i2c2_bus, soft_i2c_cfg[i].name); + RT_ASSERT(result == RT_EOK); + + LOG_D("software simulation %s init done, pin scl: %d, pin sda %d", + soft_i2c_cfg[i].name, + soft_i2c_cfg[i].scl, + soft_i2c_cfg[i].sda); + } + + return RT_EOK; +} +INIT_DEVICE_EXPORT(rt_hw_i2c_init); +#endif /* BSP_USING_I2C */ +#endif /* RT_USING_I2C */ diff --git a/bsp/swm320-lq100/drivers/drv_soft_i2c.h b/bsp/swm320-lq100/drivers/drv_soft_i2c.h new file mode 100644 index 0000000000..f22922c7d0 --- /dev/null +++ b/bsp/swm320-lq100/drivers/drv_soft_i2c.h @@ -0,0 +1,51 @@ +/* + * Copyright (c) 2006-2018, Synwit Technology Co.,Ltd. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Change Logs: + * Date Author Notes + * 2018-12-10 Zohar_Lee first version + * 2020-07-10 lik rewrite + */ + +#ifndef __DRV_SOFT_I2C_H__ +#define __DRV_SOFT_I2C_H__ + +#include "board.h" + +/* swm config class */ +struct swm_soft_i2c_cfg +{ + rt_uint8_t scl; + rt_uint8_t sda; + const char *name; +}; +/* swm i2c dirver class */ +struct swm_i2c +{ + struct rt_i2c_bit_ops ops; + struct rt_i2c_bus_device i2c2_bus; +}; + +#ifdef BSP_USING_I2C0 +#define I2C0_BUS_CFG \ + { \ + .scl = BSP_I2C0_SCL_PIN, \ + .sda = BSP_I2C0_SDA_PIN, \ + .name = "i2c0", \ + } +#endif + +#ifdef BSP_USING_I2C1 +#define I2C1_BUS_CFG \ + { \ + .scl = BSP_I2C1_SCL_PIN, \ + .sda = BSP_I2C1_SDA_PIN, \ + .name = "i2c1", \ + } +#endif + +int rt_hw_i2c_init(void); + +#endif /* __DRV_SOFT_I2C_H__ */ diff --git a/bsp/swm320-lq100/drivers/drv_spi.c b/bsp/swm320-lq100/drivers/drv_spi.c index e766f0ea81..20ea69cb85 100644 --- a/bsp/swm320-lq100/drivers/drv_spi.c +++ b/bsp/swm320-lq100/drivers/drv_spi.c @@ -7,109 +7,119 @@ * Date Author Notes * 2018-05-31 ZYH first version * 2018-12-10 Zohar_Lee format file + * 2020-07-10 lik format file */ -#include -#include -#include -#include -#include -#include +#include "drv_spi.h" -#define SPIRXEVENT 0x01 -#define SPITXEVENT 0x02 -#define SPITIMEOUT 2 -#define SPICRCEN 0 +#ifdef RT_USING_SPI +#ifdef BSP_USING_SPI -struct swm320_spi -{ - SPI_TypeDef *swm320_spi; - struct rt_spi_configuration *cfg; +//#define DRV_DEBUG +#define LOG_TAG "drv.spi" +#include + +static struct swm_spi_cfg spi_cfg[] = + { +#ifdef BSP_USING_SPI0 + SPI0_BUS_CONFIG, +#endif +#ifdef BSP_USING_SPI1 + SPI1_BUS_CONFIG, +#endif }; -static rt_err_t swm320_spi_init(SPI_TypeDef *spix, - struct rt_spi_configuration *cfg) +static struct swm_spi spi_bus_drv[sizeof(spi_cfg) / sizeof(spi_cfg[0])] = {0}; + +static rt_err_t swm_spi_init(struct swm_spi *spi_drv, struct rt_spi_configuration *configure) { - SPI_InitStructure SPI_initStruct; - if (cfg->mode & RT_SPI_SLAVE) + RT_ASSERT(spi_drv != RT_NULL); + RT_ASSERT(configure != RT_NULL); + + struct swm_spi_cfg *cfg = spi_drv->cfg; + + if (configure->mode & RT_SPI_SLAVE) { - SPI_initStruct.Master = 0; + cfg->spi_initstruct.Master = 0; } else { - SPI_initStruct.Master = 1; + cfg->spi_initstruct.Master = 1; } - if (cfg->mode & RT_SPI_3WIRE) + + if (configure->mode & RT_SPI_3WIRE) { return RT_EINVAL; } - if (cfg->data_width == 8) + + if (configure->data_width == 8) { - SPI_initStruct.WordSize = 8; + cfg->spi_initstruct.WordSize = 8; } - else if (cfg->data_width == 16) + else if (configure->data_width == 16) { - SPI_initStruct.WordSize = 16; + cfg->spi_initstruct.WordSize = 16; } else { - return RT_EINVAL; + return RT_EIO; } - if (cfg->mode & RT_SPI_CPHA) + + if (configure->mode & RT_SPI_CPHA) { - SPI_initStruct.SampleEdge = SPI_SECOND_EDGE; + cfg->spi_initstruct.SampleEdge = SPI_SECOND_EDGE; } else { - SPI_initStruct.SampleEdge = SPI_FIRST_EDGE; + cfg->spi_initstruct.SampleEdge = SPI_FIRST_EDGE; } - if (cfg->mode & RT_SPI_CPOL) + + if (configure->mode & RT_SPI_CPOL) { - SPI_initStruct.IdleLevel = SPI_HIGH_LEVEL; + cfg->spi_initstruct.IdleLevel = SPI_HIGH_LEVEL; } else { - SPI_initStruct.IdleLevel = SPI_LOW_LEVEL; + cfg->spi_initstruct.IdleLevel = SPI_LOW_LEVEL; } - if (cfg->max_hz >= SystemCoreClock / 4) + + if (configure->max_hz >= SystemCoreClock / 4) { - SPI_initStruct.clkDiv = SPI_CLKDIV_4; + cfg->spi_initstruct.clkDiv = SPI_CLKDIV_4; } - else if (cfg->max_hz >= SystemCoreClock / 8) + else if (configure->max_hz >= SystemCoreClock / 8) { - SPI_initStruct.clkDiv = SPI_CLKDIV_8; + cfg->spi_initstruct.clkDiv = SPI_CLKDIV_8; } - else if (cfg->max_hz >= SystemCoreClock / 16) + else if (configure->max_hz >= SystemCoreClock / 16) { - SPI_initStruct.clkDiv = SPI_CLKDIV_16; + cfg->spi_initstruct.clkDiv = SPI_CLKDIV_16; } - else if (cfg->max_hz >= SystemCoreClock / 32) + else if (configure->max_hz >= SystemCoreClock / 32) { - SPI_initStruct.clkDiv = SPI_CLKDIV_32; + cfg->spi_initstruct.clkDiv = SPI_CLKDIV_32; } - else if (cfg->max_hz >= SystemCoreClock / 64) + else if (configure->max_hz >= SystemCoreClock / 64) { - SPI_initStruct.clkDiv = SPI_CLKDIV_64; + cfg->spi_initstruct.clkDiv = SPI_CLKDIV_64; } - else if (cfg->max_hz >= SystemCoreClock / 128) + else if (configure->max_hz >= SystemCoreClock / 128) { - SPI_initStruct.clkDiv = SPI_CLKDIV_128; + cfg->spi_initstruct.clkDiv = SPI_CLKDIV_128; } - else if (cfg->max_hz >= SystemCoreClock / 256) + else if (configure->max_hz >= SystemCoreClock / 256) { - SPI_initStruct.clkDiv = SPI_CLKDIV_256; + cfg->spi_initstruct.clkDiv = SPI_CLKDIV_256; } else { /* min prescaler 512 */ - SPI_initStruct.clkDiv = SPI_CLKDIV_512; + cfg->spi_initstruct.clkDiv = SPI_CLKDIV_512; } - SPI_initStruct.FrameFormat = SPI_FORMAT_SPI; - SPI_initStruct.RXHFullIEn = 0; - SPI_initStruct.TXEmptyIEn = 0; - SPI_initStruct.TXCompleteIEn = 0; - SPI_Init(spix, &SPI_initStruct); - SPI_Open(spix); + + SPI_Init(cfg->SPIx, &(cfg->spi_initstruct)); + SPI_Open(cfg->SPIx); + LOG_D("%s init done", cfg->name); return RT_EOK; } @@ -139,7 +149,7 @@ static rt_err_t swm320_spi_init(SPI_TypeDef *spix, } \ } while (0) -static rt_err_t spitxrx1b(struct swm320_spi *hspi, void *rcvb, const void *sndb) +static rt_err_t spitxrx1b(struct swm_spi *spi_drv, void *rcvb, const void *sndb) { rt_uint32_t padrcv = 0; rt_uint32_t padsnd = 0xFF; @@ -155,39 +165,51 @@ static rt_err_t spitxrx1b(struct swm320_spi *hspi, void *rcvb, const void *sndb) { sndb = &padsnd; } - while (SPI_IsTXFull(hspi->swm320_spi)); - SPISEND_1(hspi->swm320_spi->DATA, sndb, hspi->cfg->data_width); - while (SPI_IsRXEmpty(hspi->swm320_spi)); - SPIRECV_1(hspi->swm320_spi->DATA, rcvb, hspi->cfg->data_width); + while (SPI_IsTXFull(spi_drv->cfg->SPIx)) + ; + SPISEND_1(spi_drv->cfg->SPIx->DATA, sndb, spi_drv->cfg->spi_initstruct.WordSize); + while (SPI_IsRXEmpty(spi_drv->cfg->SPIx)) + ; + SPIRECV_1(spi_drv->cfg->SPIx->DATA, rcvb, spi_drv->cfg->spi_initstruct.WordSize); return RT_EOK; } -static rt_uint32_t swm320_spi_xfer(struct rt_spi_device *device, - struct rt_spi_message *message) +static rt_uint32_t swm_spi_xfer(struct rt_spi_device *device, struct rt_spi_message *message) { rt_err_t res; - struct swm320_spi *hspi = (struct swm320_spi *)device->bus->parent.user_data; - struct swm320_spi_cs *cs = device->parent.user_data; - const rt_uint8_t *sndb = message->send_buf; - rt_uint8_t *rcvb = message->recv_buf; - rt_int32_t length = message->length; + RT_ASSERT(device != RT_NULL); RT_ASSERT(device->bus != RT_NULL); RT_ASSERT(device->bus->parent.user_data != RT_NULL); + RT_ASSERT(message != RT_NULL); + + struct swm_spi *spi_drv = rt_container_of(device->bus, struct swm_spi, spi_bus); + struct swm_spi_cfg *cfg = spi_drv->cfg; + struct swm_spi_cs *cs = device->parent.user_data; + if (message->cs_take) { - rt_pin_write(cs->pin, 0); + GPIO_ClrBit(cs->GPIOx, cs->gpio_pin); } + + LOG_D("%s transfer prepare and start", cfg->name); + LOG_D("%s sendbuf: %X, recvbuf: %X, length: %d", + cfg->name, (uint32_t)message->send_buf, (uint32_t)message->recv_buf, message->length); + + const rt_uint8_t *sndb = message->send_buf; + rt_uint8_t *rcvb = message->recv_buf; + rt_int32_t length = message->length; + while (length) { - res = spitxrx1b(hspi, rcvb, sndb); + res = spitxrx1b(spi_drv, rcvb, sndb); if (rcvb) { - rcvb += SPISTEP(hspi->cfg->data_width); + rcvb += SPISTEP(cfg->spi_initstruct.WordSize); } if (sndb) { - sndb += SPISTEP(hspi->cfg->data_width); + sndb += SPISTEP(cfg->spi_initstruct.WordSize); } if (res != RT_EOK) { @@ -196,93 +218,90 @@ static rt_uint32_t swm320_spi_xfer(struct rt_spi_device *device, length--; } /* Wait until Busy flag is reset before disabling SPI */ - while (!SPI_IsTXEmpty(hspi->swm320_spi) && !SPI_IsRXEmpty(hspi->swm320_spi)); + while (!SPI_IsTXEmpty(cfg->SPIx) && !SPI_IsRXEmpty(cfg->SPIx)) + ; if (message->cs_release) { - rt_pin_write(cs->pin, 1); + GPIO_SetBit(cs->GPIOx, cs->gpio_pin); } return message->length - length; } -static rt_err_t swm320_spi_configure(struct rt_spi_device *device, - struct rt_spi_configuration *configuration) +static rt_err_t swm_spi_configure(struct rt_spi_device *device, + struct rt_spi_configuration *configure) { - struct swm320_spi *hspi = (struct swm320_spi *)device->bus->parent.user_data; - hspi->cfg = configuration; - return swm320_spi_init(hspi->swm320_spi, configuration); -} -const static struct rt_spi_ops swm320_spi_ops = -{ - .configure = swm320_spi_configure, - .xfer = swm320_spi_xfer, -}; - -#ifdef BSP_USING_SPI0 - static struct rt_spi_bus swm320_spi_bus0; - static struct swm320_spi swm320_spi0; -#endif //BSP_USING_SPI0 + RT_ASSERT(device != RT_NULL); + RT_ASSERT(configure != RT_NULL); -#ifdef BSP_USING_SPI1 - static struct rt_spi_bus swm320_spi_bus1; - static struct swm320_spi swm320_spi1; -#endif //BSP_USING_SPI1 + struct swm_spi *spi_drv = rt_container_of(device->bus, struct swm_spi, spi_bus); + spi_drv->configure = configure; -static int swm320_spi_register_bus(SPI_TypeDef *SPIx, const char *name) -{ - struct rt_spi_bus *spi_bus; - struct swm320_spi *swm320_spi; - if (SPIx == SPI0) - { - PORT_Init(PORTC, PIN5, FUNMUX1_SPI0_SCLK, 0); - PORT_Init(PORTC, PIN6, FUNMUX0_SPI0_MOSI, 0); - PORT_Init(PORTC, PIN7, FUNMUX1_SPI0_MISO, 1); - spi_bus = &swm320_spi_bus0; - swm320_spi = &swm320_spi0; - } - else if (SPIx == SPI1) - { - PORT_Init(PORTM, PIN5, FUNMUX1_SPI1_SCLK, 0); - PORT_Init(PORTC, PIN2, FUNMUX0_SPI1_MOSI, 0); - PORT_Init(PORTC, PIN3, FUNMUX1_SPI1_MISO, 1); - spi_bus = &swm320_spi_bus1; - swm320_spi = &swm320_spi1; - } - else - { - return -1; - } - swm320_spi->swm320_spi = SPIx; - spi_bus->parent.user_data = swm320_spi; - return rt_spi_bus_register(spi_bus, name, &swm320_spi_ops); + return swm_spi_init(spi_drv, configure); } +const static struct rt_spi_ops swm_spi_ops = + { + .configure = swm_spi_configure, + .xfer = swm_spi_xfer, +}; //cannot be used before completion init -static rt_err_t swm320_spi_bus_attach_device(rt_uint32_t pin, - const char *bus_name, - const char *device_name) +rt_err_t rt_hw_spi_device_attach(const char *bus_name, const char *device_name, GPIO_TypeDef *cs_gpiox, uint32_t cs_gpio_pin) { - struct rt_spi_device *spi_device = (struct rt_spi_device *)rt_malloc(sizeof(struct rt_spi_device)); + RT_ASSERT(bus_name != RT_NULL); + RT_ASSERT(device_name != RT_NULL); + + rt_err_t result; + struct rt_spi_device *spi_device; + struct swm_spi_cs *cs_pin; + + GPIO_Init(cs_gpiox, cs_gpio_pin, 1, 0, 0); + GPIO_SetBit(cs_gpiox, cs_gpio_pin); + + spi_device = (struct rt_spi_device *)rt_malloc(sizeof(struct rt_spi_device)); RT_ASSERT(spi_device != RT_NULL); - struct swm320_spi_cs *cs_pin = (struct swm320_spi_cs *)rt_malloc(sizeof(struct swm320_spi_cs)); + cs_pin = (struct swm_spi_cs *)rt_malloc(sizeof(struct swm_spi_cs)); RT_ASSERT(cs_pin != RT_NULL); - cs_pin->pin = pin; - rt_pin_mode(pin, PIN_MODE_OUTPUT); - rt_pin_write(pin, 1); - return rt_spi_bus_attach_device(spi_device, - device_name, - bus_name, - (void *)cs_pin); + cs_pin->GPIOx = cs_gpiox; + cs_pin->gpio_pin = cs_gpio_pin; + + result = rt_spi_bus_attach_device(spi_device, device_name, bus_name, (void *)cs_pin); + if (result != RT_EOK) + { + LOG_E("%s attach to %s faild, %d\n", device_name, bus_name, result); + } + RT_ASSERT(result == RT_EOK); + LOG_D("%s attach to %s done", device_name, bus_name); + return result; } int rt_hw_spi_init(void) { - int result = 0; + rt_err_t result; + #ifdef BSP_USING_SPI0 - result = swm320_spi_register_bus(SPI0, "spi0"); -#endif + PORT_Init(PORTP, PIN23, FUNMUX1_SPI0_SCLK, 0); + PORT_Init(PORTP, PIN18, FUNMUX0_SPI0_MOSI, 0); + PORT_Init(PORTP, PIN19, FUNMUX1_SPI0_MISO, 1); +#endif //BSP_USING_SPI0 + #ifdef BSP_USING_SPI1 - result = swm320_spi_register_bus(SPI1, "spi1"); -#endif + PORT_Init(PORTB, PIN1, FUNMUX1_SPI1_SCLK, 0); + PORT_Init(PORTB, PIN2, FUNMUX0_SPI1_MOSI, 0); + PORT_Init(PORTB, PIN3, FUNMUX1_SPI1_MISO, 1); +#endif //BSP_USING_SPI1 + for (int i = 0; i < sizeof(spi_cfg) / sizeof(spi_cfg[0]); i++) + { + spi_bus_drv[i].cfg = &spi_cfg[i]; + spi_bus_drv[i].spi_bus.parent.user_data = &spi_cfg[i]; + result = rt_spi_bus_register(&spi_bus_drv[i].spi_bus, spi_cfg[i].name, &swm_spi_ops); + RT_ASSERT(result == RT_EOK); + + LOG_D("%s bus init done", spi_config[i].bus_name); + } + return result; } INIT_BOARD_EXPORT(rt_hw_spi_init); + +#endif /* BSP_USING_SPI */ +#endif /* RT_USING_SPI */ diff --git a/bsp/swm320-lq100/drivers/drv_spi.h b/bsp/swm320-lq100/drivers/drv_spi.h index 7e5366ab58..7af96779d2 100644 --- a/bsp/swm320-lq100/drivers/drv_spi.h +++ b/bsp/swm320-lq100/drivers/drv_spi.h @@ -6,22 +6,75 @@ * Change Logs: * Date Author Notes * 2018-12-10 Zohar_Lee first version + * 2020-07-10 lik rewrite */ -#ifndef DRV_SPI_H__ -#define DRV_SPI_H__ +#ifndef __DRV_SPI_H__ +#define __DRV_SPI_H__ -#include +#include "board.h" -struct swm320_spi_cs +struct swm_spi_cs { - rt_uint32_t pin; + GPIO_TypeDef *GPIOx; + uint32_t gpio_pin; }; +struct swm_spi_cfg +{ + const char *name; + SPI_TypeDef *SPIx; + SPI_InitStructure spi_initstruct; +}; + +/* swm spi dirver class */ +struct swm_spi +{ + struct swm_spi_cfg *cfg; + struct rt_spi_configuration *configure; + struct rt_spi_bus spi_bus; +}; + +#ifdef BSP_USING_SPI0 +#ifndef SPI0_BUS_CONFIG +#define SPI0_BUS_CONFIG \ + { \ + .name = "spi0", \ + .SPIx = SPI0, \ + .spi_initstruct.clkDiv = SPI_CLKDIV_32, \ + .spi_initstruct.FrameFormat = SPI_FORMAT_SPI, \ + .spi_initstruct.SampleEdge = SPI_SECOND_EDGE, \ + .spi_initstruct.IdleLevel = SPI_HIGH_LEVEL, \ + .spi_initstruct.WordSize = 8, \ + .spi_initstruct.Master = 1, \ + .spi_initstruct.RXHFullIEn = 0, \ + .spi_initstruct.TXEmptyIEn = 0, \ + .spi_initstruct.TXCompleteIEn = 0, \ + } +#endif /* SPI1_BUS_CONFIG */ +#endif /* BSP_USING_SPI1 */ + +#ifdef BSP_USING_SPI1 +#ifndef SPI1_BUS_CONFIG +#define SPI1_BUS_CONFIG \ + { \ + .name = "spi1", \ + .SPIx = SPI1, \ + .spi_initstruct.clkDiv = SPI_CLKDIV_32, \ + .spi_initstruct.FrameFormat = SPI_FORMAT_SPI, \ + .spi_initstruct.SampleEdge = SPI_SECOND_EDGE, \ + .spi_initstruct.IdleLevel = SPI_HIGH_LEVEL, \ + .spi_initstruct.WordSize = 8, \ + .spi_initstruct.Master = 1, \ + .spi_initstruct.RXHFullIEn = 0, \ + .spi_initstruct.TXEmptyIEn = 0, \ + .spi_initstruct.TXCompleteIEn = 0, \ + } +#endif /* SPI1_BUS_CONFIG */ +#endif /* BSP_USING_SPI1 */ + //cannot be used before completion init -static rt_err_t swm320_spi_bus_attach_device(rt_uint32_t pin, - const char *bus_name, - const char *device_name); +rt_err_t rt_hw_spi_device_attach(const char *bus_name, const char *device_name, GPIO_TypeDef *GPIOx, uint32_t n); int rt_hw_spi_init(void); -#endif +#endif /* __DRV_SPI_H__ */ diff --git a/bsp/swm320-lq100/drivers/drv_sram.c b/bsp/swm320-lq100/drivers/drv_sram.c index b23c76beac..90c2d94676 100644 --- a/bsp/swm320-lq100/drivers/drv_sram.c +++ b/bsp/swm320-lq100/drivers/drv_sram.c @@ -7,40 +7,44 @@ * Date Author Notes * 2018-05-31 ZYH first version * 2018-12-10 Zohar_Lee format file + * 2020-07-10 lik rewrite */ -#include -#include -#include -#include -#include +#include "drv_sram.h" -int rt_hw_sram_init(void) -{ - int i; - PORT->PORTP_SEL0 = 0xAAAAAAAA; /* PP0-23 => ADDR0-23 */ - PORT->PORTP_SEL1 = 0xAAAA; - PORT->PORTM_SEL0 = 0xAAAAAAAA; /* PM0-15 => DATA15-0 */ - PORT->PORTM_INEN |= 0xFFFF; - PORT->PORTM_SEL1 = 0x2AA; /* PM16 => OEN、PM17 => WEN、PM18 => NORFL_CSN、PM19 => SDRAM_CSN、PM20 => SRAM_CSN、PM21 => SDRAM_CKE */ +#ifdef BSP_USING_EXT_SRAM - /* 配置SRAM前需要刷新下SDRAM控制器 */ +#define DRV_DEBUG +#define LOG_TAG "drv.ext_sram" +#include - SYS->CLKEN |= (1 << SYS_CLKEN_SDRAM_Pos); +#ifdef RT_USING_MEMHEAP_AS_HEAP +static struct rt_memheap system_heap; +#endif - while (SDRAMC->REFDONE == 0); - SDRAMC->REFRESH &= ~(1 << SDRAMC_REFRESH_EN_Pos); +static int rt_hw_sram_init(void) +{ + SRAM_InitStructure SRAM_InitStruct; - for (i = 0; i < 1000; i++) - { - } - SYS->CLKEN &= ~(1 << SYS_CLKEN_SDRAM_Pos); + PORT->PORTP_SEL0 = 0xAAAAAAAA; //PP0-23 => ADDR0-23 + PORT->PORTP_SEL1 = 0xAAAA; - SYS->CLKEN |= (1 << SYS_CLKEN_RAMC_Pos); + PORT->PORTM_SEL0 = 0xAAAAAAAA; //PM0-15 => DATA15-0 + PORT->PORTM_INEN = 0xFFFF; - SRAMC->CR = (9 << SRAMC_CR_RWTIME_Pos) | - (0 << SRAMC_CR_BYTEIF_Pos) | // 16位接口 - (0 << SRAMC_CR_HBLBDIS_Pos); // 使能字节、半字访问 + PORT->PORTM_SEL1 = 0xAAA; //PM16 => OEN,PM17 => WEN,PM18 => NORFL_CSN,PM19 => SDRAM_CSN,PM20 => SRAM_CSN,PM21 => SDRAM_CKE + + SRAM_InitStruct.ClkDiv = SRAM_CLKDIV_8; + SRAM_InitStruct.DataWidth = SRAM_DATAWIDTH_16; + SRAM_Init(&SRAM_InitStruct); + +#ifdef RT_USING_MEMHEAP_AS_HEAP + /* If RT_USING_MEMHEAP_AS_HEAP is enabled, SRAM is initialized to the heap */ + rt_memheap_init(&system_heap, "sram", (void *)EXT_SRAM_BEGIN, EXT_SRAM_SIZE); +#endif return 0; } +INIT_BOARD_EXPORT(rt_hw_sram_init); + +#endif /* BSP_USING_EXT_SRAM */ diff --git a/bsp/swm320-lq100/drivers/drv_sram.h b/bsp/swm320-lq100/drivers/drv_sram.h index 5f81319733..043de498e2 100644 --- a/bsp/swm320-lq100/drivers/drv_sram.h +++ b/bsp/swm320-lq100/drivers/drv_sram.h @@ -6,11 +6,19 @@ * Change Logs: * Date Author Notes * 2018-12-10 Zohar_Lee first version + * 2020-07-10 lik rewrite */ #ifndef DRV_SRAM_H__ #define DRV_SRAM_H__ +#include "board.h" + +#define EXT_SRAM_BASE SRAMM_BASE +#define EXT_SRAM_SIZE BSP_EXT_SRAM_SIZE +#define EXT_SRAM_BEGIN EXT_SRAM_BASE +#define EXT_SRAM_END (EXT_SRAM_BASE + EXT_SRAM_SIZE) + int rt_hw_sram_init(void); #endif diff --git a/bsp/swm320-lq100/drivers/drv_uart.c b/bsp/swm320-lq100/drivers/drv_uart.c index fe02c4da55..d193eb1238 100644 --- a/bsp/swm320-lq100/drivers/drv_uart.c +++ b/bsp/swm320-lq100/drivers/drv_uart.c @@ -7,193 +7,253 @@ * Date Author Notes * 2018-05-31 ZYH first version * 2018-12-10 Zohar_Lee format file + * 2020-07-10 lik format file */ -#include -#include -#include -#include -#include +#include "drv_uart.h" -struct swm320_uart +#ifdef RT_USING_SERIAL +#ifdef BSP_USING_UART + +//#define DRV_DEBUG +#define LOG_TAG "drv.uart" +#include + +#if !defined(BSP_USING_UART0) && !defined(BSP_USING_UART1) && !defined(BSP_USING_UART2) && \ + !defined(BSP_USING_UART3) +#error "Please define at least one BSP_USING_UARTx" +/* this driver can be disabled at menuconfig -> RT-Thread Components -> Device Drivers */ +#endif + +enum { - UART_TypeDef *uart; - IRQn_Type irq; +#ifdef BSP_USING_UART0 + UART0_INDEX, +#endif +#ifdef BSP_USING_UART1 + UART1_INDEX, +#endif +#ifdef BSP_USING_UART2 + UART2_INDEX, +#endif +#ifdef BSP_USING_UART3 + UART3_INDEX, +#endif +}; + +static struct swm_uart_cfg uart_cfg[] = + { +#ifdef BSP_USING_UART0 + UART0_CFG, +#endif +#ifdef BSP_USING_UART1 + UART1_CFG, +#endif +#ifdef BSP_USING_UART2 + UART2_CFG, +#endif +#ifdef BSP_USING_UART3 + UART3_CFG, +#endif }; -static rt_err_t swm320_uart_configure(struct rt_serial_device *serial, - struct serial_configure *cfg) +static struct swm_uart uart_drv[sizeof(uart_cfg) / sizeof(uart_cfg[0])] = {0}; + +static rt_err_t swm_uart_init(struct rt_serial_device *serial_device, struct serial_configure *configure) { - struct swm320_uart *uart; - UART_InitStructure UART_initStruct; - RT_ASSERT(serial != RT_NULL); - RT_ASSERT(cfg != RT_NULL); - uart = (struct swm320_uart *)serial->parent.user_data; - NVIC_DisableIRQ(uart->irq); - UART_initStruct.Baudrate = cfg->baud_rate; - UART_initStruct.RXThreshold = 1; - UART_initStruct.RXThresholdIEn = 1; - UART_initStruct.TXThresholdIEn = 0; - UART_initStruct.TimeoutTime = 10; - UART_initStruct.TimeoutIEn = 0; - switch (cfg->data_bits) + struct swm_uart_cfg *cfg; + RT_ASSERT(serial_device != RT_NULL); + RT_ASSERT(configure != RT_NULL); + cfg = serial_device->parent.user_data; + + cfg->uart_initstruct.Baudrate = configure->baud_rate; + switch (configure->data_bits) { + case DATA_BITS_8: + cfg->uart_initstruct.DataBits = UART_DATA_8BIT; + break; case DATA_BITS_9: - UART_initStruct.DataBits = UART_DATA_9BIT; + cfg->uart_initstruct.DataBits = UART_DATA_9BIT; break; default: - UART_initStruct.DataBits = UART_DATA_8BIT; + cfg->uart_initstruct.DataBits = UART_DATA_8BIT; break; } - switch (cfg->stop_bits) + switch (configure->stop_bits) { + case STOP_BITS_1: + cfg->uart_initstruct.StopBits = UART_STOP_1BIT; + break; case STOP_BITS_2: - UART_initStruct.StopBits = UART_STOP_2BIT; + cfg->uart_initstruct.StopBits = UART_STOP_2BIT; break; default: - UART_initStruct.StopBits = UART_STOP_1BIT; + cfg->uart_initstruct.StopBits = UART_STOP_1BIT; break; } - switch (cfg->parity) + switch (configure->parity) { + case PARITY_NONE: + cfg->uart_initstruct.Parity = UART_PARITY_NONE; + break; case PARITY_ODD: - UART_initStruct.Parity = UART_PARITY_ODD; + cfg->uart_initstruct.Parity = UART_PARITY_ODD; break; case PARITY_EVEN: - UART_initStruct.Parity = UART_PARITY_EVEN; + cfg->uart_initstruct.Parity = UART_PARITY_EVEN; + break; + default: + cfg->uart_initstruct.Parity = UART_PARITY_NONE; + break; + } + switch ((uint32_t)cfg->UARTx) + { + case ((uint32_t)UART0): + PORT_Init(PORTA, PIN2, FUNMUX0_UART0_RXD, 1); + PORT_Init(PORTA, PIN3, FUNMUX1_UART0_TXD, 0); + break; + case ((uint32_t)UART1): + PORT_Init(PORTC, PIN2, FUNMUX0_UART1_RXD, 1); + PORT_Init(PORTC, PIN3, FUNMUX1_UART1_TXD, 0); + break; + case ((uint32_t)UART2): + PORT_Init(PORTC, PIN4, FUNMUX0_UART2_RXD, 1); + PORT_Init(PORTC, PIN5, FUNMUX1_UART2_TXD, 0); + break; + case ((uint32_t)UART3): + PORT_Init(PORTC, PIN6, FUNMUX0_UART3_RXD, 1); + PORT_Init(PORTC, PIN7, FUNMUX1_UART3_TXD, 0); break; default: - UART_initStruct.Parity = UART_PARITY_NONE; break; } - UART_Init(uart->uart, &UART_initStruct); - UART_Open(uart->uart); + UART_Init(cfg->UARTx, &(cfg->uart_initstruct)); + UART_Open(cfg->UARTx); return RT_EOK; } -static rt_err_t swm320_uart_control(struct rt_serial_device *serial, - int cmd, void *arg) +static rt_err_t swm_uart_control(struct rt_serial_device *serial_device, int cmd, void *arg) { - struct swm320_uart *uart; - RT_ASSERT(serial != RT_NULL); - uart = (struct swm320_uart *)serial->parent.user_data; + struct swm_uart_cfg *cfg; + RT_ASSERT(serial_device != RT_NULL); + cfg = serial_device->parent.user_data; + switch (cmd) { case RT_DEVICE_CTRL_CLR_INT: /* disable rx irq */ - NVIC_DisableIRQ(uart->irq); + NVIC_DisableIRQ(cfg->irq); break; case RT_DEVICE_CTRL_SET_INT: /* enable rx irq */ - NVIC_EnableIRQ(uart->irq); + NVIC_EnableIRQ(cfg->irq); break; } return RT_EOK; } -static int swm320_uart_putc(struct rt_serial_device *serial, char c) +static int swm_uart_putc(struct rt_serial_device *serial_device, char c) { - struct swm320_uart *uart; - RT_ASSERT(serial != RT_NULL); - uart = (struct swm320_uart *)serial->parent.user_data; - while (UART_IsTXBusy(uart->uart)); - uart->uart->DATA = c; + struct swm_uart_cfg *cfg; + RT_ASSERT(serial_device != RT_NULL); + cfg = serial_device->parent.user_data; + + while (UART_IsTXFIFOFull(cfg->UARTx)) + ; + UART_WriteByte(cfg->UARTx, c); + while (UART_IsTXBusy(cfg->UARTx)) + ; return 1; } -static int swm320_uart_getc(struct rt_serial_device *serial) +static int swm_uart_getc(struct rt_serial_device *serial_device) { int ch; - struct swm320_uart *uart; - RT_ASSERT(serial != RT_NULL); - uart = (struct swm320_uart *)serial->parent.user_data; + struct swm_uart_cfg *cfg; + RT_ASSERT(serial_device != RT_NULL); + cfg = serial_device->parent.user_data; + ch = -1; - if (UART_IsRXFIFOEmpty(uart->uart) == 0) + if (UART_IsRXFIFOEmpty(cfg->UARTx) == 0) { - UART_ReadByte(uart->uart, (uint32_t *)&ch); + UART_ReadByte(cfg->UARTx, (uint32_t *)&ch); } return ch; } -static const struct rt_uart_ops swm320_uart_ops = +static const struct rt_uart_ops swm_uart_ops = + { + .configure = swm_uart_init, + .control = swm_uart_control, + .putc = swm_uart_putc, + .getc = swm_uart_getc, + .dma_transmit = RT_NULL}; + +/** + * Uart common interrupt process. This need add to uart ISR. + * + * @param serial serial device + */ +static void rt_hw_uart_isr(struct rt_serial_device *serial_device) { - swm320_uart_configure, - swm320_uart_control, - swm320_uart_putc, - swm320_uart_getc, -}; + struct swm_uart_cfg *cfg; + RT_ASSERT(serial_device != RT_NULL); + cfg = serial_device->parent.user_data; + + /* UART in mode Receiver -------------------------------------------------*/ + if (UART_INTRXThresholdStat(cfg->UARTx) || UART_INTTimeoutStat(cfg->UARTx)) + { + rt_hw_serial_isr(serial_device, RT_SERIAL_EVENT_RX_IND); + } +} #if defined(BSP_USING_UART0) -/* UART0 device driver structure */ -static struct swm320_uart uart0; -static struct rt_serial_device serial0; void UART0_Handler(void) { /* enter interrupt */ rt_interrupt_enter(); - /* UART in mode Receiver */ - if (UART_INTRXThresholdStat(uart0.uart) || UART_INTTimeoutStat(uart0.uart)) - { - rt_hw_serial_isr(&serial0, RT_SERIAL_EVENT_RX_IND); - } + rt_hw_uart_isr(&(uart_drv[UART0_INDEX].serial_device)); + /* leave interrupt */ rt_interrupt_leave(); } #endif /* BSP_USING_UART0 */ #if defined(BSP_USING_UART1) -/* UART1 device driver structure */ -static struct swm320_uart uart1; -static struct rt_serial_device serial1; void UART1_Handler(void) { /* enter interrupt */ rt_interrupt_enter(); - /* UART in mode Receiver */ - if (UART_INTRXThresholdStat(uart1.uart) || UART_INTTimeoutStat(uart1.uart)) - { - rt_hw_serial_isr(&serial1, RT_SERIAL_EVENT_RX_IND); - } + rt_hw_uart_isr(&(uart_drv[UART1_INDEX].serial_device)); + /* leave interrupt */ rt_interrupt_leave(); } #endif /* BSP_USING_UART1 */ #if defined(BSP_USING_UART2) -/* UART2 device driver structure */ -static struct swm320_uart uart2; -static struct rt_serial_device serial2; void UART2_Handler(void) { /* enter interrupt */ rt_interrupt_enter(); - /* UART in mode Receiver */ - if (UART_INTRXThresholdStat(uart2.uart) || UART_INTTimeoutStat(uart2.uart)) - { - rt_hw_serial_isr(&serial2, RT_SERIAL_EVENT_RX_IND); - } + rt_hw_uart_isr(&(uart_drv[UART2_INDEX].serial_device)); + /* leave interrupt */ rt_interrupt_leave(); } #endif /* BSP_USING_UART2 */ #if defined(BSP_USING_UART3) -/* UART3 device driver structure */ -static struct swm320_uart uart3; -static struct rt_serial_device serial3; void UART3_Handler(void) { /* enter interrupt */ rt_interrupt_enter(); - /* UART in mode Receiver */ - if (UART_INTRXThresholdStat(uart3.uart) || UART_INTTimeoutStat(uart3.uart)) - { - rt_hw_serial_isr(&serial3, RT_SERIAL_EVENT_RX_IND); - } + rt_hw_uart_isr(&(uart_drv[UART3_INDEX].serial_device)); + /* leave interrupt */ rt_interrupt_leave(); } @@ -201,60 +261,24 @@ void UART3_Handler(void) int rt_hw_uart_init(void) { - struct swm320_uart *uart; - struct serial_configure config = RT_SERIAL_CONFIG_DEFAULT; -#ifdef BSP_USING_UART0 - PORT_Init(PORTA, PIN2, FUNMUX0_UART0_RXD, 1); - PORT_Init(PORTA, PIN3, FUNMUX1_UART0_TXD, 0); - uart = &uart0; - uart->uart = UART0; - uart->irq = UART0_IRQn; - serial0.ops = &swm320_uart_ops; - serial0.config = config; - /* register UART0 device */ - rt_hw_serial_register(&serial0, "uart0", - RT_DEVICE_FLAG_RDWR | RT_DEVICE_FLAG_INT_RX, - uart); -#endif /* BSP_USING_UART0 */ -#ifdef BSP_USING_UART1 - PORT_Init(PORTC, PIN2, FUNMUX0_UART1_RXD, 1); - PORT_Init(PORTC, PIN3, FUNMUX1_UART1_TXD, 0); - uart = &uart1; - uart->uart = UART1; - uart->irq = UART1_IRQn; - serial1.ops = &swm320_uart_ops; - serial1.config = config; - /* register UART1 device */ - rt_hw_serial_register(&serial1, "uart1", - RT_DEVICE_FLAG_RDWR | RT_DEVICE_FLAG_INT_RX, - uart); -#endif /* BSP_USING_UART1 */ -#ifdef BSP_USING_UART2 - PORT_Init(PORTC, PIN4, FUNMUX0_UART2_RXD, 1); - PORT_Init(PORTC, PIN5, FUNMUX1_UART2_TXD, 0); - uart = &uart2; - uart->uart = UART2; - uart->irq = UART2_IRQn; - serial2.ops = &swm320_uart_ops; - serial2.config = config; - /* register UART2 device */ - rt_hw_serial_register(&serial2, "uart2", - RT_DEVICE_FLAG_RDWR | RT_DEVICE_FLAG_INT_RX, - uart); -#endif /* BSP_USING_UART2 */ -#ifdef BSP_USING_UART3 - PORT_Init(PORTC, PIN6, FUNMUX0_UART3_RXD, 1); - PORT_Init(PORTC, PIN7, FUNMUX1_UART3_TXD, 0); - uart = &uart3; - uart->uart = UART3; - uart->irq = UART3_IRQn; - serial3.ops = &swm320_uart_ops; - serial3.config = config; - /* register UART3 device */ - rt_hw_serial_register(&serial3, "uart3", - RT_DEVICE_FLAG_RDWR | RT_DEVICE_FLAG_INT_RX, - uart); -#endif /* BSP_USING_UART3 */ - return 0; + struct serial_configure cfg = RT_SERIAL_CONFIG_DEFAULT; + int i = 0; + rt_err_t result = RT_EOK; + + for (i = 0; i < sizeof(uart_cfg) / sizeof(uart_cfg[0]); i++) + { + uart_drv[i].cfg = &uart_cfg[i]; + uart_drv[i].serial_device.ops = &swm_uart_ops; + uart_drv[i].serial_device.config = cfg; + /* register UART device */ + result = rt_hw_serial_register(&uart_drv[i].serial_device, uart_drv[i].cfg->name, + RT_DEVICE_FLAG_RDWR | RT_DEVICE_FLAG_INT_RX, uart_drv[i].cfg); + RT_ASSERT(result == RT_EOK); + } + + return result; } INIT_BOARD_EXPORT(rt_hw_uart_init); + +#endif /* BSP_USING_UART */ +#endif /* RT_USING_SERIAL */ diff --git a/bsp/swm320-lq100/drivers/drv_uart.h b/bsp/swm320-lq100/drivers/drv_uart.h index 67193a45d4..66c6535a5b 100644 --- a/bsp/swm320-lq100/drivers/drv_uart.h +++ b/bsp/swm320-lq100/drivers/drv_uart.h @@ -6,11 +6,110 @@ * Change Logs: * Date Author Notes * 2018-12-10 Zohar_Lee first version + * 2020-07-10 lik rewrite */ -#ifndef DRV_UART_H__ -#define DRV_UART_H__ +#ifndef __DRV_UART_H__ +#define __DRV_UART_H__ -int rt_hw_uart_init(void); +#include "board.h" -#endif +/* swm config class */ +struct swm_uart_cfg +{ + const char *name; + UART_TypeDef *UARTx; + IRQn_Type irq; + UART_InitStructure uart_initstruct; +}; + +/* swm uart dirver class */ +struct swm_uart +{ + struct swm_uart_cfg *cfg; + struct rt_serial_device serial_device; +}; + +#ifdef BSP_USING_UART0 +#ifndef UART0_CFG +#define UART0_CFG \ + { \ + .name = "uart0", \ + .UARTx = UART0, \ + .irq = UART0_IRQn, \ + .uart_initstruct.Baudrate = 115200, \ + .uart_initstruct.DataBits = UART_DATA_8BIT, \ + .uart_initstruct.Parity = UART_PARITY_NONE, \ + .uart_initstruct.StopBits = UART_STOP_1BIT, \ + .uart_initstruct.RXThreshold = 0, \ + .uart_initstruct.RXThresholdIEn = 1, \ + .uart_initstruct.TXThresholdIEn = 0, \ + .uart_initstruct.TimeoutTime = 10, \ + .uart_initstruct.TimeoutIEn = 1, \ + } +#endif /* UART0_CFG */ +#endif /* BSP_USING_UART0 */ + +#ifdef BSP_USING_UART1 +#ifndef UART1_CFG +#define UART1_CFG \ + { \ + .name = "uart1", \ + .UARTx = UART1, \ + .irq = UART1_IRQn, \ + .uart_initstruct.Baudrate = 115200, \ + .uart_initstruct.DataBits = UART_DATA_8BIT, \ + .uart_initstruct.Parity = UART_PARITY_NONE, \ + .uart_initstruct.StopBits = UART_STOP_1BIT, \ + .uart_initstruct.RXThreshold = 0, \ + .uart_initstruct.RXThresholdIEn = 1, \ + .uart_initstruct.TXThresholdIEn = 0, \ + .uart_initstruct.TimeoutTime = 10, \ + .uart_initstruct.TimeoutIEn = 1, \ + } +#endif /* UART1_CFG */ +#endif /* BSP_USING_UART1 */ + +#ifdef BSP_USING_UART2 +#ifndef UART2_CFG +#define UART2_CFG \ + { \ + .name = "uart2", \ + .UARTx = UART2, \ + .irq = UART2_IRQn, \ + .uart_initstruct.Baudrate = 115200, \ + .uart_initstruct.DataBits = UART_DATA_8BIT, \ + .uart_initstruct.Parity = UART_PARITY_NONE, \ + .uart_initstruct.StopBits = UART_STOP_1BIT, \ + .uart_initstruct.RXThreshold = 0, \ + .uart_initstruct.RXThresholdIEn = 1, \ + .uart_initstruct.TXThresholdIEn = 0, \ + .uart_initstruct.TimeoutTime = 10, \ + .uart_initstruct.TimeoutIEn = 1, \ + } +#endif /* UART2_CFG */ +#endif /* BSP_USING_UART2 */ + +#ifdef BSP_USING_UART3 +#ifndef UART3_CFG +#define UART3_CFG \ + { \ + .name = "uart3", \ + .UARTx = UART3, \ + .irq = UART3_IRQn, \ + .uart_initstruct.Baudrate = 115200, \ + .uart_initstruct.DataBits = UART_DATA_8BIT, \ + .uart_initstruct.Parity = UART_PARITY_NONE, \ + .uart_initstruct.StopBits = UART_STOP_1BIT, \ + .uart_initstruct.RXThreshold = 0, \ + .uart_initstruct.RXThresholdIEn = 1, \ + .uart_initstruct.TXThresholdIEn = 0, \ + .uart_initstruct.TimeoutTime = 10, \ + .uart_initstruct.TimeoutIEn = 1, \ + } +#endif /* UART3_CFG */ +#endif /* BSP_USING_UART3 */ + +int rt_hw_serial_init(void); + +#endif /* __DRV_UART_H__ */ diff --git a/bsp/swm320-lq100/drivers/drv_wdt.c b/bsp/swm320-lq100/drivers/drv_wdt.c new file mode 100644 index 0000000000..36d5fde26d --- /dev/null +++ b/bsp/swm320-lq100/drivers/drv_wdt.c @@ -0,0 +1,88 @@ +/* + * Copyright (c) 2006-2018, Synwit Technology Co.,Ltd. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Change Logs: + * Date Author Notes + * 2018-12-10 Zohar_Lee first version + * 2020-07-10 lik format file + */ + +#include "drv_wdt.h" + +#ifdef RT_USING_WDT +#ifdef BSP_USING_WDT +//#define DRV_DEBUG +#define LOG_TAG "drv.wdt" +#include + +static struct swm_wdt_cfg wdt_cfg = + { + .name = "wdt", + .WDTx = WDT, +}; + +static struct swm_wdt wdt_drv; + +static rt_err_t swm_wdt_init(rt_watchdog_t *wdt_device) +{ + return RT_EOK; +} + +static rt_err_t swm_wdt_control(rt_watchdog_t *wdt_device, int cmd, void *arg) +{ + struct swm_wdt_cfg *cfg; + RT_ASSERT(wdt_device != RT_NULL); + cfg = wdt_device->parent.user_data; + + switch (cmd) + { + case RT_DEVICE_CTRL_WDT_KEEPALIVE: + WDT_Feed(cfg->WDTx); + break; + case RT_DEVICE_CTRL_WDT_SET_TIMEOUT: + WDT_Init(cfg->WDTx, (SystemCoreClock * (*(rt_uint32_t *)arg)), WDT_MODE_RESET); + break; + case RT_DEVICE_CTRL_WDT_GET_TIMEOUT: + *(rt_uint32_t *)arg = (cfg->WDTx->LOAD) / SystemCoreClock; + break; + case RT_DEVICE_CTRL_WDT_GET_TIMELEFT: + *(rt_uint32_t *)arg = WDT_GetValue(cfg->WDTx) / SystemCoreClock; + break; + case RT_DEVICE_CTRL_WDT_START: + WDT_Start(cfg->WDTx); + break; + case RT_DEVICE_CTRL_WDT_STOP: + WDT_Stop(cfg->WDTx); + break; + default: + LOG_W("This command is not supported."); + return -RT_ERROR; + } + + return RT_EOK; +} + +const static struct rt_watchdog_ops swm_wdt_ops = + { + swm_wdt_init, + swm_wdt_control}; + +int rt_hw_wdt_init(void) +{ + wdt_drv.cfg = &wdt_cfg; + wdt_drv.wdt_device.ops = &swm_wdt_ops; + + if (rt_hw_watchdog_register(&wdt_drv.wdt_device, wdt_drv.cfg->name, RT_DEVICE_FLAG_RDWR, wdt_drv.cfg) != RT_EOK) + { + LOG_E("wdt device register failed."); + return -RT_ERROR; + } + LOG_D("wdt device register success."); + return RT_EOK; +} +INIT_BOARD_EXPORT(rt_hw_wdt_init); + +#endif /* BSP_USING_WDT */ +#endif /* RT_USING_WDT */ diff --git a/bsp/swm320-lq100/drivers/drv_wdt.h b/bsp/swm320-lq100/drivers/drv_wdt.h new file mode 100644 index 0000000000..28be110f01 --- /dev/null +++ b/bsp/swm320-lq100/drivers/drv_wdt.h @@ -0,0 +1,31 @@ +/* + * Copyright (c) 2006-2018, Synwit Technology Co.,Ltd. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Change Logs: + * Date Author Notes + * 2018-12-10 Zohar_Lee first version + * 2020-07-10 lik rewrite + */ + +#ifndef __DRV_WDT_H__ +#define __DRV_WDT_H__ + +#include "board.h" + +struct swm_wdt_cfg +{ + const char *name; + WDT_TypeDef *WDTx; +}; + +struct swm_wdt +{ + struct swm_wdt_cfg *cfg; + struct rt_watchdog_device wdt_device; +}; + +int rt_hw_wdt_init(void); + +#endif /* __DRV_WDT_H__ */ diff --git a/bsp/swm320-lq100/keilkill.bat b/bsp/swm320-lq100/keilkill.bat new file mode 100644 index 0000000000..52d5f3375a --- /dev/null +++ b/bsp/swm320-lq100/keilkill.bat @@ -0,0 +1,37 @@ +del *.bak /s +del *.ddk /s +del *.edk /s +del *.lst /s +::del *.lnp /s +del *.mpf /s +del *.mpj /s +del *.obj /s +del *.omf /s +::del *.opt /s ::不允许删除JLINK的设置 +del *.plg /s +del *.rpt /s +del *.tmp /s +::del *.__i /s +::del *._ia /s +del *.crf /s +del *.o /s +del *.d /s +del *.axf /s +del *.tra /s +del *.dep /s +::del JLinkLog.txt /s + +del *.iex /s +del *.htm /s +::del *.sct /s +del *.map /s + +del *.whsj2 /s +del *.SYNWIT_Lik /s +del *.whsj2 /s +del *.scvd /s + +rmdir /s/q .git +rmdir /s/q .vscode + +exit diff --git a/bsp/swm320-lq100/project.ewd b/bsp/swm320-lq100/project.ewd index 52cc221b07..e94c83ed06 100644 --- a/bsp/swm320-lq100/project.ewd +++ b/bsp/swm320-lq100/project.ewd @@ -44,7 +44,7 @@